add ls2k bsp

6 files changed, 159 insertions, 16 deletions

diff --git a/libcpu/Kconfig b/libcpu/Kconfig
index 3c8c73636d..95d3dd5228 100644
--- a/libcpu/Kconfig
+++ b/libcpu/Kconfig
@@ -77,6 +77,9 @@ config ARCH_ARM_CORTEX_A9
 config ARCH_MIPS
     bool
 
+config ARCH_MIPS64
+    bool
+
 config ARCH_MIPS_XBURST
     bool
     select ARCH_MIPS
diff --git a/libcpu/mips/common/asm.h b/libcpu/mips/common/asm.h
index ec451650d2..987a1fb2b6 100644
--- a/libcpu/mips/common/asm.h
+++ b/libcpu/mips/common/asm.h
@@ -14,6 +14,7 @@
 #ifndef __ASM_H__
 #define __ASM_H__
 
+#include <rtconfig.h>
 /*
  * LEAF - declare leaf routine
  */
@@ -117,7 +118,94 @@ symbol		=	value
 /*
  * Macros to handle different pointer/register sizes for 32/64-bit code
  */
+#if defined SOC_LS2K1000
+/*
+ * Size of a register
+ */
+#define SZREG	8
+
+/*
+ * Use the following macros in assemblercode to load/store registers,
+ * pointers etc.
+ */
+#define REG_S		sd
+#define REG_L		ld
+#define REG_SUBU	dsubu
+#define REG_ADDU	daddu
+
+/*
+ * How to add/sub/load/store/shift C int variables.
+ */
+#define INT_ADD		dadd
+#define INT_ADDU	daddu
+#define INT_ADDI	daddi
+#define INT_ADDIU	daddiu
+#define INT_SUB		dsub
+#define INT_SUBU	dsubu
+#define INT_L		ld
+#define INT_S		sd
+#define INT_SLL		dsll
+#define INT_SLLV	dsllv
+#define INT_SRL		dsrl
+#define INT_SRLV	dsrlv
+#define INT_SRA		dsra
+#define INT_SRAV	dsrav
+
+/*
+ * Use the following macros in assemblercode to load/store registers,
+ * pointers etc.
+ */
+#define LONG_ADD	dadd
+#define LONG_ADDU	daddu
+#define LONG_ADDI	daddi
+#define LONG_ADDIU	daddiu
+#define LONG_SUB	dsub
+#define LONG_SUBU	dsubu
+#define LONG_L		ld
+#define LONG_S		sd
+#define LONG_SP		sdp
+#define LONG_SLL	dsll
+#define LONG_SLLV	dsllv
+#define LONG_SRL	dsrl
+#define LONG_SRLV	dsrlv
+#define LONG_SRA	dsra
+#define LONG_SRAV	dsrav
+
+#define LONG		.dword
+#define LONGSIZE	8
+#define LONGMASK	7
+#define LONGLOG		3
+
+/*
+ * How to add/sub/load/store/shift pointers.
+ */
+#define PTR_ADD		dadd
+#define PTR_ADDU	daddu
+#define PTR_ADDI	daddi
+#define PTR_ADDIU	daddiu
+#define PTR_SUB		dsub
+#define PTR_SUBU	dsubu
+#define PTR_L		ld
+#define PTR_S		sd
+#define PTR_LA		dla
+#define PTR_LI		dli
+#define PTR_SLL		dsll
+#define PTR_SLLV	dsllv
+#define PTR_SRL		dsrl
+#define PTR_SRLV	dsrlv
+#define PTR_SRA		dsra
+#define PTR_SRAV	dsrav
+
+#define PTR_SCALESHIFT	3
+
+#define PTR		.dword
+#define PTRSIZE		8
+#define PTRLOG		3
+
+#define MFC0		dmfc0
+#define MTC0		dmtc0
 
+#else
 /*
  * Size of a register
  */
@@ -211,6 +299,7 @@ symbol		=	value
 #define MFC0		mfc0
 #define MTC0		mtc0
 
+#endif
 
 #define SSNOP		sll zero, zero, 1
 
diff --git a/libcpu/mips/common/entry_gcc.S b/libcpu/mips/common/entry_gcc.S
index b6f758e273..757774cfd9 100644
--- a/libcpu/mips/common/entry_gcc.S
+++ b/libcpu/mips/common/entry_gcc.S
@@ -15,6 +15,9 @@
 #include <mips.h>
 #include <rtconfig.h>
 
+#include "asm.h"
+#include <rtconfig.h>
+
     .section ".start", "ax"
     .set noreorder
 
@@ -25,27 +28,33 @@ _rtthread_entry:
     .globl  _start
 _start:
 #endif
-    la	ra, _rtthread_entry
+    PTR_LA	ra, _rtthread_entry
 
     /* disable interrupt */
     mtc0	zero, CP0_CAUSE
     mtc0	zero, CP0_STATUS	# Set CPU to disable interrupt.
     ehb
+
+#ifdef ARCH_MIPS64
+    dli		t0, ST0_KX
+    MTC0	t0, CP0_STATUS
+#endif
+
     /* setup stack pointer */
-    la	sp, _system_stack
-    la	gp, _gp
+    PTR_LA	sp, _system_stack
+    PTR_LA	gp, _gp
 
     bal	rt_cpu_early_init
     nop
 
     /* clear bss */
-    la	t0, __bss_start
-    la	t1, __bss_end
+    PTR_LA	t0, __bss_start
+    PTR_LA	t1, __bss_end
+
 _clr_bss_loop:
     sw	zero, 0(t0)
-    bne	t0, t1, _clr_bss_loop
-    addiu	t0, t0, 4
-
+    bne	t1, t0, _clr_bss_loop
+    addu	t0, 4
     /* jump to RT-Thread RTOS */
     jal	rtthread_startup
     nop
diff --git a/libcpu/mips/common/mips_addrspace.h b/libcpu/mips/common/mips_addrspace.h
index 10fc2d6593..b057e1e917 100644
--- a/libcpu/mips/common/mips_addrspace.h
+++ b/libcpu/mips/common/mips_addrspace.h
@@ -24,7 +24,7 @@
 #define _ATYPE_		__PTRDIFF_TYPE__
 #define _ATYPE32_	int
 #define _ATYPE64_	__s64
-#ifdef CONFIG_64BIT
+#ifdef ARCH_MIPS64
 #define _CONST64_(x)	x ## L
 #else
 #define _CONST64_(x)	x ## LL
@@ -54,7 +54,7 @@
 #define XPHYSADDR(a)		((_ACAST64_(a)) &			\
 				 _CONST64_(0x000000ffffffffff))
 
-#ifdef CONFIG_64BIT
+#ifdef ARCH_MIPS64
 
 /*
  * Memory segments (64bit kernel mode addresses)
@@ -90,6 +90,14 @@
 #define KSEG2ADDR(a)		(CPHYSADDR(a) | KSEG2BASE)
 #define KSEG3ADDR(a)		(CPHYSADDR(a) | KSEG3BASE)
 
+#define CKUSEG			0x00000000
+#define CKSEG0			0x80000000
+#define CKSEG1			0xa0000000
+#define CKSEG2			0xc0000000
+#define CKSEG3			0xe0000000
+
+#endif
+
 /*
  * Memory segments (32bit kernel mode addresses)
  * These are the traditional names used in the 32-bit universe.
@@ -100,13 +108,7 @@
 #define KSEG2BASE			0xc0000000
 #define KSEG3BASE			0xe0000000
 
-#define CKUSEG			0x00000000
-#define CKSEG0			0x80000000
-#define CKSEG1			0xa0000000
-#define CKSEG2			0xc0000000
-#define CKSEG3			0xe0000000
 
-#endif
 
 /*
  * Cache modes for XKPHYS address conversion macros
diff --git a/libcpu/mips/gs264/SConscript b/libcpu/mips/gs264/SConscript
new file mode 100644
index 0000000000..b0ae20ba02
--- /dev/null
+++ b/libcpu/mips/gs264/SConscript
@@ -0,0 +1,14 @@
+# RT-Thread building script for component
+
+from building import *
+
+Import('rtconfig')
+
+cwd     = GetCurrentDir()
+src     = Glob('*.c') + Glob('*.cpp') + Glob('*_gcc.S')
+CPPPATH = [cwd]
+ASFLAGS = ''
+
+group = DefineGroup('cpu', src, depend = [''], CPPPATH = CPPPATH, ASFLAGS = ASFLAGS)
+
+Return('group')
diff --git a/libcpu/mips/gs264/cpuinit_gcc.S b/libcpu/mips/gs264/cpuinit_gcc.S
new file mode 100644
index 0000000000..bd84663350
--- /dev/null
+++ b/libcpu/mips/gs264/cpuinit_gcc.S
@@ -0,0 +1,26 @@
+/*
+ * Copyright (c) 2006-2020, RT-Thread Development Team
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Change Logs:
+ * Date           Author       Notes
+ * 2020-04-05     bigmagic     Initial version
+ */
+
+#ifndef __ASSEMBLY__
+#define __ASSEMBLY__
+#endif
+
+#include <mips.h>
+
+    .section ".text", "ax"
+    .set noreorder
+
+    .globl  rt_cpu_early_init
+rt_cpu_early_init:
+     mfc0	t0, CP0_CONFIG
+     ori	t0, 3
+     mtc0	t0, CP0_CONFIG
+     ehb
+     jr	ra
\ No newline at end of file