diff options
| author | Fan YANG <[email protected]> | 2023-08-09 10:51:32 +0800 |
|---|---|---|
| committer | Meco Man <[email protected]> | 2023-08-09 01:07:11 -0400 |
| commit | 5ac509b6d031b29e2d95c52fc179771e62664378 (patch) | |
| tree | af3381cdd5e536359cfa0ba8e8a69c45182831df /libcpu | |
| parent | c6a2f5b7bdee378cc868ee9284e760ebbdf635f0 (diff) | |
[libcpu][risc-v][common] Avoid using t0 before being saved
- Fixed the issue that t0 was modified unexpectedly before being saved
Signed-off-by: Fan YANG <[email protected]>
Diffstat (limited to 'libcpu')
| -rw-r--r-- | libcpu/risc-v/common/interrupt_gcc.S | 9 |
1 files changed, 4 insertions, 5 deletions
diff --git a/libcpu/risc-v/common/interrupt_gcc.S b/libcpu/risc-v/common/interrupt_gcc.S index a887199ca8..4cec0d5a5e 100644 --- a/libcpu/risc-v/common/interrupt_gcc.S +++ b/libcpu/risc-v/common/interrupt_gcc.S @@ -1,12 +1,13 @@ /* - * Copyright (c) 2006-2018, RT-Thread Development Team + * Copyright (c) 2006-2023, RT-Thread Development Team * * SPDX-License-Identifier: Apache-2.0 * * Change Logs: * Date Author Notes - * 2023/01/17 WangShun The first version + * 2023/01/17 WangShun The first version * 2023/03/19 Flyingcys Add riscv_32e support + * 2023/08/09 HPMicro Fix the issue t0 was modified unexpectedly before being saved */ #define __ASSEMBLY__ #include "cpuport.h" @@ -20,9 +21,7 @@ .global SW_handler SW_handler: - li t0, 0x08 - csrc mstatus, t0 - + csrci mstatus, 0x8 #ifdef ARCH_RISCV_FPU addi sp, sp, -32 * FREGBYTES FSTORE f0, 0 * FREGBYTES(sp) |