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authorbernard.xiong <[email protected]>2009-12-11 09:42:01 +0000
committerbernard.xiong <[email protected]>2009-12-11 09:42:01 +0000
commit7ae254abf8e890ad83e47150e9aee1d08f50eab4 (patch)
tree3b27d0a185e109c2050ca82c73d89910d82f7831 /libcpu
parenta7b56e9c45d78b1906ce1cd524e4c0799ab95d71 (diff)
add the s3c2440 code from old s3c2410 port.
git-svn-id: https://rt-thread.googlecode.com/svn/trunk@196 bbd45198-f89e-11dd-88c7-29a3b14d5316
Diffstat (limited to 'libcpu')
-rw-r--r--libcpu/arm/s3c24x0/clock.c77
-rw-r--r--libcpu/arm/s3c24x0/context_gcc.S99
-rw-r--r--libcpu/arm/s3c24x0/context_rvds.s107
-rw-r--r--libcpu/arm/s3c24x0/cpu.c143
-rw-r--r--libcpu/arm/s3c24x0/interrupt.c117
-rw-r--r--libcpu/arm/s3c24x0/mmu.c248
-rw-r--r--libcpu/arm/s3c24x0/rtc.c152
-rw-r--r--libcpu/arm/s3c24x0/rtc.h40
-rw-r--r--libcpu/arm/s3c24x0/s3c24x0.h611
-rw-r--r--libcpu/arm/s3c24x0/serial.c313
-rw-r--r--libcpu/arm/s3c24x0/serial.h58
-rw-r--r--libcpu/arm/s3c24x0/stack.c60
-rw-r--r--libcpu/arm/s3c24x0/trap.c160
13 files changed, 2185 insertions, 0 deletions
diff --git a/libcpu/arm/s3c24x0/clock.c b/libcpu/arm/s3c24x0/clock.c
new file mode 100644
index 0000000000..c701829449
--- /dev/null
+++ b/libcpu/arm/s3c24x0/clock.c
@@ -0,0 +1,77 @@
+/*
+ * File : clock.c
+ * This file is part of RT-Thread RTOS
+ * COPYRIGHT (C) 2006, RT-Thread Development Team
+ *
+ * The license and distribution terms for this file may be
+ * found in the file LICENSE in this distribution or at
+ * http://openlab.rt-thread.com/license/LICENSE
+ *
+ * Change Logs:
+ * Date Author Notes
+ * 2008-04-25 Yi.qiu first version
+ */
+
+#include <rtthread.h>
+#include "s3c24x0.h"
+
+#define CONFIG_SYS_CLK_FREQ 12000000 // Fin = 12.00MHz
+
+rt_uint32_t PCLK;
+rt_uint32_t FCLK;
+rt_uint32_t HCLK;
+rt_uint32_t UCLK;
+
+void rt_hw_get_clock(void)
+{
+ rt_uint32_t val;
+ rt_uint8_t m, p, s;
+
+ val = MPLLCON;
+ m = (val>>12)&0xff;
+ p = (val>>4)&0x3f;
+ s = val&3;
+
+ FCLK = ((m+8)*(CONFIG_SYS_CLK_FREQ/100)*2)/((p+2)*(1<<s))*100;
+
+ val = CLKDIVN;
+ m = (val>>1)&3;
+ p = val&1;
+
+ switch (m) {
+ case 0:
+ HCLK = FCLK;
+ break;
+ case 1:
+ HCLK = FCLK>>1;
+ break;
+ case 2:
+ if(s&2)
+ HCLK = FCLK>>3;
+ else
+ HCLK = FCLK>>2;
+ break;
+ case 3:
+ if(s&1)
+ HCLK = FCLK/6;
+ else
+ HCLK = FCLK/3;
+ break;
+}
+
+ if(p)
+ PCLK = HCLK>>1;
+ else
+ PCLK = HCLK;
+}
+
+void rt_hw_set_clock(rt_uint8_t sdiv, rt_uint8_t pdiv, rt_uint8_t mdiv)
+{
+ MPLLCON = sdiv | pdiv<<4 | mdiv<<12;
+}
+
+void rt_hw_set_dividor(rt_uint8_t hdivn, rt_uint8_t pdivn)
+{
+ CLKDIVN = (hdivn<<1) | pdivn;
+}
+
diff --git a/libcpu/arm/s3c24x0/context_gcc.S b/libcpu/arm/s3c24x0/context_gcc.S
new file mode 100644
index 0000000000..80e9245698
--- /dev/null
+++ b/libcpu/arm/s3c24x0/context_gcc.S
@@ -0,0 +1,99 @@
+/*
+ * File : context.S
+ * This file is part of RT-Thread RTOS
+ * COPYRIGHT (C) 2006, RT-Thread Development Team
+ *
+ * The license and distribution terms for this file may be
+ * found in the file LICENSE in this distribution or at
+ * http://openlab.rt-thread.com/license/LICENSE
+ *
+ * Change Logs:
+ * Date Author Notes
+ * 2006-09-06 XuXinming first version
+ */
+
+/*!
+ * \addtogroup S3C24X0
+ */
+/*@{*/
+
+#define NOINT 0xc0
+
+/*
+ * rt_base_t rt_hw_interrupt_disable();
+ */
+.globl rt_hw_interrupt_disable
+rt_hw_interrupt_disable:
+ mrs r0, cpsr
+ orr r1, r0, #NOINT
+ msr cpsr_c, r1
+ mov pc, lr
+
+/*
+ * void rt_hw_interrupt_enable(rt_base_t level);
+ */
+.globl rt_hw_interrupt_enable
+rt_hw_interrupt_enable:
+ msr cpsr, r0
+ mov pc, lr
+
+/*
+ * void rt_hw_context_switch(rt_uint32 from, rt_uint32 to);
+ * r0 --> from
+ * r1 --> to
+ */
+.globl rt_hw_context_switch
+rt_hw_context_switch:
+ stmfd sp!, {lr} @ push pc (lr should be pushed in place of PC)
+ stmfd sp!, {r0-r12, lr} @ push lr & register file
+
+ mrs r4, cpsr
+ stmfd sp!, {r4} @ push cpsr
+ mrs r4, spsr
+ stmfd sp!, {r4} @ push spsr
+
+ str sp, [r0] @ store sp in preempted tasks TCB
+ ldr sp, [r1] @ get new task stack pointer
+
+ ldmfd sp!, {r4} @ pop new task spsr
+ msr spsr_cxsf, r4
+ ldmfd sp!, {r4} @ pop new task cpsr
+ msr cpsr_cxsf, r4
+
+ ldmfd sp!, {r0-r12, lr, pc} @ pop new task r0-r12, lr & pc
+
+/*
+ * void rt_hw_context_switch_to(rt_uint32 to);
+ * r0 --> to
+ */
+.globl rt_hw_context_switch_to
+rt_hw_context_switch_to:
+ ldr sp, [r0] @ get new task stack pointer
+
+ ldmfd sp!, {r4} @ pop new task spsr
+ msr spsr_cxsf, r4
+ ldmfd sp!, {r4} @ pop new task cpsr
+ msr cpsr_cxsf, r4
+
+ ldmfd sp!, {r0-r12, lr, pc} @ pop new task r0-r12, lr & pc
+
+/*
+ * void rt_hw_context_switch_interrupt(rt_uint32 from, rt_uint32 to);
+ */
+.globl rt_thread_switch_interrput_flag
+.globl rt_interrupt_from_thread
+.globl rt_interrupt_to_thread
+.globl rt_hw_context_switch_interrupt
+rt_hw_context_switch_interrupt:
+ ldr r2, =rt_thread_switch_interrput_flag
+ ldr r3, [r2]
+ cmp r3, #1
+ beq _reswitch
+ mov r3, #1 @ set rt_thread_switch_interrput_flag to 1
+ str r3, [r2]
+ ldr r2, =rt_interrupt_from_thread @ set rt_interrupt_from_thread
+ str r0, [r2]
+_reswitch:
+ ldr r2, =rt_interrupt_to_thread @ set rt_interrupt_to_thread
+ str r1, [r2]
+ mov pc, lr
diff --git a/libcpu/arm/s3c24x0/context_rvds.s b/libcpu/arm/s3c24x0/context_rvds.s
new file mode 100644
index 0000000000..82c5adc574
--- /dev/null
+++ b/libcpu/arm/s3c24x0/context_rvds.s
@@ -0,0 +1,107 @@
+;/*
+; * File : context_rvds.S
+; * This file is part of RT-Thread RTOS
+; * COPYRIGHT (C) 2006, RT-Thread Development Team
+; *
+; * The license and distribution terms for this file may be
+; * found in the file LICENSE in this distribution or at
+; * http://www.rt-thread.org/license/LICENSE
+; *
+; * Change Logs:
+; * Date Author Notes
+; * 2009-01-20 Bernard first version
+; */
+
+NOINT EQU 0xc0 ; disable interrupt in psr
+
+ AREA |.text|, CODE, READONLY, ALIGN=2
+ ARM
+ REQUIRE8
+ PRESERVE8
+
+;/*
+; * rt_base_t rt_hw_interrupt_disable();
+; */
+rt_hw_interrupt_disable PROC
+ EXPORT rt_hw_interrupt_disable
+ MRS r0, cpsr
+ ORR r1, r0, #NOINT
+ MSR cpsr_c, r1
+ BX lr
+ ENDP
+
+;/*
+; * void rt_hw_interrupt_enable(rt_base_t level);
+; */
+rt_hw_interrupt_enable PROC
+ EXPORT rt_hw_interrupt_enable
+ MSR cpsr_c, r0
+ BX lr
+ ENDP
+
+;/*
+; * void rt_hw_context_switch(rt_uint32 from, rt_uint32 to);
+; * r0 --> from
+; * r1 --> to
+; */
+rt_hw_context_switch PROC
+ EXPORT rt_hw_context_switch
+ STMFD sp!, {lr} ; push pc (lr should be pushed in place of PC)
+ STMFD sp!, {r0-r12, lr} ; push lr & register file
+
+ MRS r4, cpsr
+ STMFD sp!, {r4} ; push cpsr
+ MRS r4, spsr
+ STMFD sp!, {r4} ; push spsr
+
+ STR sp, [r0] ; store sp in preempted tasks TCB
+ LDR sp, [r1] ; get new task stack pointer
+
+ LDMFD sp!, {r4} ; pop new task spsr
+ MSR spsr_cxsf, r4
+ LDMFD sp!, {r4} ; pop new task cpsr
+ MSR cpsr_cxsf, r4
+
+ LDMFD sp!, {r0-r12, lr, pc} ; pop new task r0-r12, lr & pc
+ ENDP
+
+;/*
+; * void rt_hw_context_switch_to(rt_uint32 to);
+; * r0 --> to
+; */
+rt_hw_context_switch_to PROC
+ EXPORT rt_hw_context_switch_to
+ LDR sp, [r0] ; get new task stack pointer
+
+ LDMFD sp!, {r4} ; pop new task spsr
+ MSR spsr_cxsf, r4
+ LDMFD sp!, {r4} ; pop new task cpsr
+ MSR cpsr_cxsf, r4
+
+ LDMFD sp!, {r0-r12, lr, pc} ; pop new task r0-r12, lr & pc
+ ENDP
+
+;/*
+; * void rt_hw_context_switch_interrupt(rt_uint32 from, rt_uint32 to);
+; */
+ IMPORT rt_thread_switch_interrput_flag
+ IMPORT rt_interrupt_from_thread
+ IMPORT rt_interrupt_to_thread
+
+rt_hw_context_switch_interrupt PROC
+ EXPORT rt_hw_context_switch_interrupt
+ LDR r2, =rt_thread_switch_interrput_flag
+ LDR r3, [r2]
+ CMP r3, #1
+ BEQ _reswitch
+ MOV r3, #1 ; set rt_thread_switch_interrput_flag to 1
+ STR r3, [r2]
+ LDR r2, =rt_interrupt_from_thread ; set rt_interrupt_from_thread
+ STR r0, [r2]
+_reswitch
+ LDR r2, =rt_interrupt_to_thread ; set rt_interrupt_to_thread
+ STR r1, [r2]
+ BX lr
+ ENDP
+
+ END \ No newline at end of file
diff --git a/libcpu/arm/s3c24x0/cpu.c b/libcpu/arm/s3c24x0/cpu.c
new file mode 100644
index 0000000000..356254a9db
--- /dev/null
+++ b/libcpu/arm/s3c24x0/cpu.c
@@ -0,0 +1,143 @@
+/*
+ * File : cpu.c
+ * This file is part of RT-Thread RTOS
+ * COPYRIGHT (C) 2006, RT-Thread Develop Team
+ *
+ * The license and distribution terms for this file may be
+ * found in the file LICENSE in this distribution or at
+ * http://openlab.rt-thread.com/license/LICENSE
+ *
+ * Change Logs:
+ * Date Author Notes
+ * 2006-03-13 Bernard first version
+ */
+
+#include <rtthread.h>
+#include "s3c24x0.h"
+
+/**
+ * @addtogroup S3C24X0
+ */
+/*@{*/
+
+#define ICACHE_MASK (rt_uint32_t)(1 << 12)
+#define DCACHE_MASK (rt_uint32_t)(1 << 2)
+
+static rt_uint32_t cp15_rd(void)
+{
+ rt_uint32_t i;
+
+ asm ("mrc p15, 0, %0, c1, c0, 0":"=r" (i));
+ return i;
+}
+
+rt_inline void cache_enable(rt_uint32_t bit)
+{
+ __asm__ __volatile__( \
+ "mrc p15,0,r0,c1,c0,0\n\t" \
+ "orr r0,r0,%0\n\t" \
+ "mcr p15,0,r0,c1,c0,0" \
+ : \
+ :"r" (bit) \
+ :"memory");
+}
+rt_inline void cache_disable(rt_uint32_t bit)
+{
+ __asm__ __volatile__( \
+ "mrc p15,0,r0,c1,c0,0\n\t" \
+ "bic r0,r0,%0\n\t" \
+ "mcr p15,0,%0,c1,c0,0" \
+ : \
+ :"r" (bit) \
+ :"memory");
+}
+
+/**
+ * enable I-Cache
+ *
+ */
+void rt_hw_cpu_icache_enable()
+{
+ cache_enable(ICACHE_MASK);
+}
+
+/**
+ * disable I-Cache
+ *
+ */
+void rt_hw_cpu_icache_disable()
+{
+ cache_disable(ICACHE_MASK);
+}
+
+/**
+ * return the status of I-Cache
+ *
+ */
+rt_base_t rt_hw_cpu_icache_status()
+{
+ return (cp15_rd() & ICACHE_MASK);
+}
+
+/**
+ * enable D-Cache
+ *
+ */
+void rt_hw_cpu_dcache_enable()
+{
+ cache_enable(DCACHE_MASK);
+}
+
+/**
+ * disable D-Cache
+ *
+ */
+void rt_hw_cpu_dcache_disable()
+{
+ cache_disable(DCACHE_MASK);
+}
+
+/**
+ * return the status of D-Cache
+ *
+ */
+rt_base_t rt_hw_cpu_dcache_status()
+{
+ return (cp15_rd() & DCACHE_MASK);
+}
+
+/**
+ * reset cpu by dog's time-out
+ *
+ */
+void rt_hw_cpu_reset()
+{
+ /* Disable all interrupt except the WDT */
+ INTMSK = (~((rt_uint32_t)1 << INTWDT));
+
+ /* Disable watchdog */
+ WTCON = 0x0000;
+
+ /* Initialize watchdog timer count register */
+ WTCNT = 0x0001;
+
+ /* Enable watchdog timer; assert reset at timer timeout */
+ WTCON = 0x0021;
+
+ while(1); /* loop forever and wait for reset to happen */
+
+ /*NOTREACHED*/
+}
+
+/**
+ * shutdown CPU
+ *
+ */
+void rt_hw_cpu_shutdown()
+{
+ rt_kprintf("shutdown...\n");
+
+ RT_ASSERT(RT_NULL);
+}
+
+/*@}*/
diff --git a/libcpu/arm/s3c24x0/interrupt.c b/libcpu/arm/s3c24x0/interrupt.c
new file mode 100644
index 0000000000..4b46b312d0
--- /dev/null
+++ b/libcpu/arm/s3c24x0/interrupt.c
@@ -0,0 +1,117 @@
+/*
+ * File : trap.c
+ * This file is part of RT-Thread RTOS
+ * COPYRIGHT (C) 2006, RT-Thread Development Team
+ *
+ * The license and distribution terms for this file may be
+ * found in the file LICENSE in this distribution or at
+ * http://openlab.rt-thread.com/license/LICENSE
+ *
+ * Change Logs:
+ * Date Author Notes
+ * 2006-03-13 Bernard first version
+ */
+
+#include <rtthread.h>
+#include "s3c24x0.h"
+
+#define MAX_HANDLERS 32
+
+extern rt_uint32_t rt_interrupt_nest;
+
+/* exception and interrupt handler table */
+rt_isr_handler_t isr_table[MAX_HANDLERS];
+rt_uint32_t rt_interrupt_from_thread, rt_interrupt_to_thread;
+rt_uint32_t rt_thread_switch_interrput_flag;
+
+/**
+ * @addtogroup S3C24X0
+ */
+/*@{*/
+
+rt_isr_handler_t rt_hw_interrupt_handle(rt_uint32_t vector)
+{
+ rt_kprintf("Unhandled interrupt %d occured!!!\n", vector);
+ return RT_NULL;
+}
+
+/**
+ * This function will initialize hardware interrupt
+ */
+void rt_hw_interrupt_init()
+{
+ register rt_uint32_t idx;
+
+ /* all clear source pending */
+ SRCPND = 0x0;
+
+ /* all clear sub source pending */
+ SUBSRCPND = 0x0;
+
+ /* all=IRQ mode */
+ INTMOD = 0x0;
+
+ /* all interrupt disabled include global bit */
+ INTMSK = BIT_ALLMSK;
+
+ /* all sub interrupt disable */
+ INTSUBMSK = BIT_SUB_ALLMSK;
+
+ /* all clear interrupt pending */
+ INTPND = BIT_ALLMSK;
+
+ /* init exceptions table */
+ for(idx=0; idx < MAX_HANDLERS; idx++)
+ {
+ isr_table[idx] = (rt_isr_handler_t)rt_hw_interrupt_handle;
+ }
+
+ /* init interrupt nest, and context in thread sp */
+ rt_interrupt_nest = 0;
+ rt_interrupt_from_thread = 0;
+ rt_interrupt_to_thread = 0;
+ rt_thread_switch_interrput_flag = 0;
+}
+
+/**
+ * This function will mask a interrupt.
+ * @param vector the interrupt number
+ */
+void rt_hw_interrupt_mask(rt_uint32_t vector)
+{
+ INTMSK |= 1 << vector;
+}
+
+/**
+ * This function will un-mask a interrupt.
+ * @param vector the interrupt number
+ */
+void rt_hw_interrupt_umask(rt_uint32_t vector)
+{
+ if (vector == INTNOTUSED6)
+ {
+ rt_kprintf("Interrupt vec %d is not used!\n", vector);
+ // while(1);
+ }
+ else if (vector == INTGLOBAL)
+ INTMSK = 0x0;
+ else
+ INTMSK &= ~(1 << vector);
+}
+
+/**
+ * This function will install a interrupt service routine to a interrupt.
+ * @param vector the interrupt number
+ * @param new_handler the interrupt service routine to be installed
+ * @param old_handler the old interrupt service routine
+ */
+void rt_hw_interrupt_install(rt_uint32_t vector, rt_isr_handler_t new_handler, rt_isr_handler_t *old_handler)
+{
+ if(vector < MAX_HANDLERS)
+ {
+ if (*old_handler != RT_NULL) *old_handler = isr_table[vector];
+ if (new_handler != RT_NULL) isr_table[vector] = new_handler;
+ }
+}
+
+/*@}*/
diff --git a/libcpu/arm/s3c24x0/mmu.c b/libcpu/arm/s3c24x0/mmu.c
new file mode 100644
index 0000000000..d86621fc53
--- /dev/null
+++ b/libcpu/arm/s3c24x0/mmu.c
@@ -0,0 +1,248 @@
+/*
+ * File : mmu.c
+ * This file is part of RT-Thread RTOS
+ * COPYRIGHT (C) 2006, RT-Thread Development Team
+ *
+ * The license and distribution terms for this file may be
+ * found in the file LICENSE in this distribution or at
+ * http://openlab.rt-thread.com/license/LICENSE
+ *
+ * Change Logs:
+ * Date Author Notes
+ * 2008-04-25 Yi.qiu first version
+ */
+
+#include <rtthread.h>
+#include "s3c24x0.h"
+
+// #define _MMUTT_STARTADDRESS 0x30080000
+#define _MMUTT_STARTADDRESS 0x30200000
+
+#define DESC_SEC (0x2|(1<<4))
+#define CB (3<<2) //cache_on, write_back
+#define CNB (2<<2) //cache_on, write_through
+#define NCB (1<<2) //cache_off,WR_BUF on
+#define NCNB (0<<2) //cache_off,WR_BUF off
+#define AP_RW (3<<10) //supervisor=RW, user=RW
+#define AP_RO (2<<10) //supervisor=RW, user=RO
+
+#define DOMAIN_FAULT (0x0)
+#define DOMAIN_CHK (0x1)
+#define DOMAIN_NOTCHK (0x3)
+#define DOMAIN0 (0x0<<5)
+#define DOMAIN1 (0x1<<5)
+
+#define DOMAIN0_ATTR (DOMAIN_CHK<<0)
+#define DOMAIN1_ATTR (DOMAIN_FAULT<<2)
+
+#define RW_CB (AP_RW|DOMAIN0|CB|DESC_SEC)
+#define RW_CNB (AP_RW|DOMAIN0|CNB|DESC_SEC)
+#define RW_NCNB (AP_RW|DOMAIN0|NCNB|DESC_SEC)
+#define RW_FAULT (AP_RW|DOMAIN1|NCNB|DESC_SEC)
+
+void rt_hw_mmu_init(void);
+
+void mmu_setttbase(register rt_uint32_t i)
+{
+ asm ("mcr p15, 0, %0, c2, c2, 0": :"r" (i));
+}
+
+void mmu_setdomain(register rt_uint32_t i)
+{
+ asm ("mcr p15,0, %0, c3, c0, 0": :"r" (i));
+}
+
+void mmu_enablemmu()
+{
+ register rt_uint32_t i;
+
+ /* read control register */
+ asm ("mrc p15, 0, %0, c1, c0, 0":"=r" (i));
+
+ i |= 0x1;
+
+ /* write back to control register */
+ asm ("mcr p15, 0, %0, c1, c0, 0": :"r" (i));
+}
+
+void mmu_disablemmu()
+{
+ register rt_uint32_t i;
+
+ /* read control register */
+ asm ("mrc p15, 0, %0, c1, c0, 0":"=r" (i));
+
+ i &= ~0x1;
+
+ /* write back to control register */
+ asm ("mcr p15, 0, %0, c1, c0, 0": :"r" (i));
+}
+
+void mmu_enableicache()
+{
+ register rt_uint32_t i;
+
+ /* read control register */
+ asm ("mrc p15, 0, %0, c1, c0, 0":"=r" (i));
+
+ i |= (1 << 12);
+
+ /* write back to control register */
+ asm ("mcr p15, 0, %0, c1, c0, 0": :"r" (i));
+}
+
+void mmu_enabledcache()
+{
+ register rt_uint32_t i;
+
+ /* read control register */
+ asm ("mrc p15, 0, %0, c1, c0, 0":"=r" (i));
+
+ i |= (1 << 2);
+
+ /* write back to control register */
+ asm ("mcr p15, 0, %0, c1, c0, 0": :"r" (i));
+}
+
+void mmu_disableicache()
+{
+ register rt_uint32_t i;
+
+ /* read control register */
+ asm ("mrc p15, 0, %0, c1, c0, 0":"=r" (i));
+
+ i &= ~(1 << 12);
+
+ /* write back to control register */
+ asm ("mcr p15, 0, %0, c1, c0, 0": :"r" (i));
+}
+
+void mmu_disabledcache()
+{
+ register rt_uint32_t i;
+
+ /* read control register */
+ asm ("mrc p15, 0, %0, c1, c0, 0":"=r" (i));
+
+ i &= ~(1 << 2);
+
+ /* write back to control register */
+ asm ("mcr p15, 0, %0, c1, c0, 0": :"r" (i));
+}
+
+void mmu_enablealignfault()
+{
+ register rt_uint32_t i;
+
+ /* read control register */
+ asm ("mrc p15, 0, %0, c1, c0, 0":"=r" (i));
+
+ i |= (1 << 1);
+
+ /* write back to control register */
+ asm ("mcr p15, 0, %0, c1, c0, 0": :"r" (i));
+}
+
+void mmu_disablealignfault()
+{
+ register rt_uint32_t i;
+
+ /* read control register */
+ asm ("mrc p15, 0, %0, c1, c0, 0":"=r" (i));
+
+ i &= ~(1 << 1);
+
+ /* write back to control register */
+ asm ("mcr p15, 0, %0, c1, c0, 0": :"r" (i));
+}
+
+void mmu_cleaninvalidatedcacheindex(int index)
+{
+ asm ("mcr p15, 0, %0, c7, c14, 2": :"r" (index));
+}
+
+void mmu_invalidatetlb()
+{
+ asm ("mcr p15, 0, %0, c8, c7, 0": :"r" (0));
+}
+
+void mmu_invalidateicache()
+{
+ asm ("mcr p15, 0, %0, c7, c5, 0": :"r" (0));
+}
+
+void mmu_setmtt(int vaddrStart,int vaddrEnd,int paddrStart,int attr)
+{
+ volatile rt_uint32_t *pTT;
+ volatile int i,nSec;
+ pTT=(rt_uint32_t *)_MMUTT_STARTADDRESS+(vaddrStart>>20);
+ nSec=(vaddrEnd>>20)-(vaddrStart>>20);
+ for(i=0;i<=nSec;i++)
+ {
+ *pTT = attr |(((paddrStart>>20)+i)<<20);
+ pTT++;
+ }
+}
+
+void rt_hw_mmu_init(void)
+{
+ int i,j;
+ //========================== IMPORTANT NOTE =========================
+ //The current stack and code area can't be re-mapped in this routine.
+ //If you want memory map mapped freely, your own sophiscated mmu
+ //initialization code is needed.
+ //===================================================================
+
+ mmu_disabledcache();
+ mmu_disableicache();
+
+ //If write-back is used,the DCache should be cleared.
+ for(i=0;i<64;i++)
+ for(j=0;j<8;j++)
+ mmu_cleaninvalidatedcacheindex((i<<26)|(j<<5));
+
+ mmu_invalidateicache();
+
+ //To complete mmu_Init() fast, Icache may be turned on here.
+ mmu_enableicache();
+
+ mmu_disablemmu();
+ mmu_invalidatetlb();
+
+ //mmu_setmtt(int vaddrStart,int vaddrEnd,int paddrStart,int attr);
+ mmu_setmtt(0x00000000,0x07f00000,0x00000000,RW_CNB); //bank0
+ mmu_setmtt(0x00000000,0x03f00000,(int)0x30000000,RW_CB); //bank0
+ mmu_setmtt(0x04000000,0x07f00000,0,RW_NCNB); //bank0
+ mmu_setmtt(0x08000000,0x0ff00000,0x08000000,RW_CNB); //bank1
+ mmu_setmtt(0x10000000,0x17f00000,0x10000000,RW_NCNB); //bank2
+ mmu_setmtt(0x18000000,0x1ff00000,0x18000000,RW_NCNB); //bank3
+ //mmu_setmtt(0x20000000,0x27f00000,0x20000000,RW_CB); //bank4
+ mmu_setmtt(0x20000000,0x27f00000,0x20000000,RW_CNB); //bank4 for STRATA Flash
+ mmu_setmtt(0x28000000,0x2ff00000,0x28000000,RW_NCNB); //bank5
+ //30f00000->30100000, 31000000->30200000
+ mmu_setmtt(0x30000000,0x30100000,0x30000000,RW_CB); //bank6-1
+ mmu_setmtt(0x30200000,0x33e00000,0x30200000,RW_NCNB); //bank6-2
+
+ mmu_setmtt(0x33f00000,0x33f00000,0x33f00000,RW_CB); //bank6-3
+ mmu_setmtt(0x38000000,0x3ff00000,0x38000000,RW_NCNB); //bank7
+
+ mmu_setmtt(0x40000000,0x47f00000,0x40000000,RW_NCNB); //SFR
+ mmu_setmtt(0x48000000,0x5af00000,0x48000000,RW_NCNB); //SFR
+ mmu_setmtt(0x5b000000,0x5b000000,0x5b000000,RW_NCNB); //SFR
+ mmu_setmtt(0x5b100000,0xfff00000,0x5b100000,RW_FAULT);//not used
+ mmu_setmtt(0x60000000,0x67f00000,0x60000000,RW_NCNB); //SFR
+
+ mmu_setttbase(_MMUTT_STARTADDRESS);
+
+ /* DOMAIN1: no_access, DOMAIN0,2~15=client(AP is checked) */
+ mmu_setdomain(0x55555550|DOMAIN1_ATTR|DOMAIN0_ATTR);
+
+ //mmu_SetProcessId(0x0);
+ mmu_enablealignfault();
+
+ mmu_enablemmu();
+ mmu_enableicache();
+
+ /* DCache should be turned on after mmu is turned on. */
+ mmu_enabledcache();
+}
diff --git a/libcpu/arm/s3c24x0/rtc.c b/libcpu/arm/s3c24x0/rtc.c
new file mode 100644
index 0000000000..6f69840569
--- /dev/null
+++ b/libcpu/arm/s3c24x0/rtc.c
@@ -0,0 +1,152 @@
+/*
+ * File : rtc.c
+ * This file is part of RT-Thread RTOS
+ * COPYRIGHT (C) 2006, RT-Thread Development Team
+ *
+ * The license and distribution terms for this file may be
+ * found in the file LICENSE in this distribution or at
+ * http://openlab.rt-thread.com/license/LICENSE
+ *
+ * Change Logs:
+ * Date Author Notes
+ * 2009-04-26 yi.qiu first version
+ */
+
+#include "rtc.h"
+
+/**
+ * This function access to rtc
+ */
+static inline void rt_hw_rtc_access(int a)
+{
+ switch (a)
+ {
+ case RTC_ENABLE:
+ RTCCON |= 0x01;
+ break;
+
+ case RTC_DISABLE:
+ RTCCON &= ~0x01;
+ break;
+ }
+}
+
+static inline rt_uint32_t BCD2BIN(rt_uint8_t n)
+{
+ return ((((n >> 4) & 0x0F) * 10) + (n & 0x0F));
+}
+
+static inline rt_uint8_t BIN2BCD(rt_uint32_t n)
+{
+ return (((n / 10) << 4) | (n % 10));
+}
+
+/**
+ * This function get rtc time
+ */
+void rt_hw_rtc_get (struct rtc_time *tmp)
+{
+ rt_uint8_t sec, min, hour, mday, wday, mon, year;
+ rt_uint8_t a_sec,a_min, a_hour, a_date, a_mon, a_year, a_armed;
+
+ /* enable access to RTC registers */
+ rt_hw_rtc_access(RTC_ENABLE);
+
+ /* read RTC registers */
+ do
+ {
+ sec = BCDSEC;
+ min = BCDMIN;
+ hour = BCDHOUR;
+ mday = BCDDATE;
+ wday = BCDDAY;
+ mon = BCDMON;
+ year = BCDYEAR;
+ } while (sec != BCDSEC);
+
+ /* read ALARM registers */
+ a_sec = ALMSEC;
+ a_min = ALMMIN;
+ a_hour = ALMHOUR;
+ a_date = ALMDATE;
+ a_mon = ALMMON;
+ a_year = ALMYEAR;
+ a_armed = RTCALM;
+
+ /* disable access to RTC registers */
+ rt_hw_rtc_access(RTC_DISABLE);
+
+#ifdef RTC_DEBUG
+ rt_kprintf ( "Get RTC year: %02x mon/cent: %02x mday: %02x wday: %02x "
+ "hr: %02x min: %02x sec: %02x\n",
+ year, mon, mday, wday,
+ hour, min, sec);
+ rt_kprintf ( "Alarms: %02x: year: %02x month: %02x date: %02x hour: %02x min: %02x sec: %02x\n",
+ a_armed,
+ a_year, a_mon, a_date,
+ a_hour, a_min, a_sec);
+#endif
+
+ tmp->tm_sec = BCD2BIN(sec & 0x7F);
+ tmp->tm_min = BCD2BIN(min & 0x7F);
+ tmp->tm_hour = BCD2BIN(hour & 0x3F);
+ tmp->tm_mday = BCD2BIN(mday & 0x3F);
+ tmp->tm_mon = BCD2BIN(mon & 0x1F);
+ tmp->tm_year = BCD2BIN(year);
+ tmp->tm_wday = BCD2BIN(wday & 0x07);
+ if(tmp->tm_year < 70) tmp->tm_year += 2000;
+ else tmp->tm_year += 1900;
+ tmp->tm_yday = 0;
+ tmp->tm_isdst = 0;
+#ifdef RTC_DEBUG
+ rt_kprintf ( "Get DATE: %4d-%02d-%02d (wday=%d) TIME: %2d:%02d:%02d\n",
+ tmp->tm_year, tmp->tm_mon, tmp->tm_mday, tmp->tm_wday,
+ tmp->tm_hour, tmp->tm_min, tmp->tm_sec);
+#endif
+}
+
+/**
+ * This function set rtc time
+ */
+void rt_hw_rtc_set (struct rtc_time *tmp)
+{
+ rt_uint8_t sec, min, hour, mday, wday, mon, year;
+
+#ifdef RTC_DEBUG
+ rt_kprintf ( "Set DATE: %4d-%02d-%02d (wday=%d) TIME: %2d:%02d:%02d\n",
+ tmp->tm_year, tmp->tm_mon, tmp->tm_mday, tmp->tm_wday,
+ tmp->tm_hour, tmp->tm_min, tmp->tm_sec);
+#endif
+ year = BIN2BCD(tmp->tm_year % 100);
+ mon = BIN2BCD(tmp->tm_mon);
+ wday = BIN2BCD(tmp->tm_wday);
+ mday = BIN2BCD(tmp->tm_mday);
+ hour = BIN2BCD(tmp->tm_hour);
+ min = BIN2BCD(tmp->tm_min);
+ sec = BIN2BCD(tmp->tm_sec);
+
+ /* enable access to RTC registers */
+ rt_hw_rtc_access(RTC_ENABLE);
+
+ /* write RTC registers */
+ BCDSEC = sec;
+ BCDMIN = min;
+ BCDHOUR = hour;
+ BCDDATE = mday;
+ BCDDAY = wday;
+ BCDMON = mon;
+ BCDYEAR = year;
+
+ /* disable access to RTC registers */
+ rt_hw_rtc_access(RTC_DISABLE);
+}
+
+/**
+ * This function reset rtc
+ */
+void rt_hw_rtc_reset (void)
+{
+ RTCCON = (RTCCON & ~0x06) | 0x08;
+ RTCCON &= ~(0x08|0x01);
+}
+
diff --git a/libcpu/arm/s3c24x0/rtc.h b/libcpu/arm/s3c24x0/rtc.h
new file mode 100644
index 0000000000..ef052b8acd
--- /dev/null
+++ b/libcpu/arm/s3c24x0/rtc.h
@@ -0,0 +1,40 @@
+#ifndef __RT_HW_SERIAL_H__
+#define __RT_HW_SERIAL_H__
+
+#include <rthw.h>
+#include <rtthread.h>
+
+#include "s3c24x0.h"
+
+#define RTC_DEBUG
+
+#define RTC_ENABLE 0x01
+#define RTC_DISABLE 0x02
+
+static const unsigned char days_in_month[] =
+{
+ 31, 28, 31, 30, 31, 30, 31, 31, 30, 31, 30, 31
+};
+
+#define LEAPS_THRU_END_OF(y) ((y)/4 - (y)/100 + (y)/400)
+#define LEAP_YEAR(year) ((!(year % 4) && (year % 100)) || !(year % 400))
+
+struct rtc_time
+{
+ int tm_sec;
+ int tm_min;
+ int tm_hour;
+ int tm_mday;
+ int tm_mon;
+ int tm_year;
+ int tm_wday;
+ int tm_yday;
+ int tm_isdst;
+};
+
+void rt_hw_rtc_get (struct rtc_time *tmp);
+void rt_hw_rtc_set (struct rtc_time *tmp);
+void rt_hw_rtc_reset (void);
+void rt_rtc_time_to_tm(rt_uint32_t time, struct rtc_time *tm);
+
+#endif
diff --git a/libcpu/arm/s3c24x0/s3c24x0.h b/libcpu/arm/s3c24x0/s3c24x0.h
new file mode 100644
index 0000000000..f9e779cd23
--- /dev/null
+++ b/libcpu/arm/s3c24x0/s3c24x0.h
@@ -0,0 +1,611 @@
+/*
+ * File : s3c24x0.h
+ * This file is part of RT-Thread RTOS
+ * COPYRIGHT (C) 2006, RT-Thread Develop Team
+ *
+ * The license and distribution terms for this file may be
+ * found in the file LICENSE in this distribution or at
+ * http://openlab.rt-thread.com/license/LICENSE
+ *
+ * Change Logs:
+ * Date Author Notes
+ * 2009-12-11 Bernard first version
+ */
+
+#ifndef __S3C24X0_H__
+#define __S3C24X0_H__
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+#include <rtthread.h>
+
+/**
+ * @addtogroup S3C24X0
+ */
+/*@{*/
+
+// Memory control
+#define BWSCON (*(volatile unsigned *)0x48000000) //Bus width & wait status
+#define BANKCON0 (*(volatile unsigned *)0x48000004) //Boot ROM control
+#define BANKCON1 (*(volatile unsigned *)0x48000008) //BANK1 control
+#define BANKCON2 (*(volatile unsigned *)0x4800000c) //BANK2 cControl
+#define BANKCON3 (*(volatile unsigned *)0x48000010) //BANK3 control
+#define BANKCON4 (*(volatile unsigned *)0x48000014) //BANK4 control
+#define BANKCON5 (*(volatile unsigned *)0x48000018) //BANK5 control
+#define BANKCON6 (*(volatile unsigned *)0x4800001c) //BANK6 control
+#define BANKCON7 (*(volatile unsigned *)0x48000020) //BANK7 control
+#define REFRESH (*(volatile unsigned *)0x48000024) //DRAM/SDRAM efresh
+#define BANKSIZE (*(volatile unsigned *)0x48000028) //Flexible Bank Size
+#define MRSRB6 (*(volatile unsigned *)0x4800002c) //Mode egister set for SDRAM
+#define MRSRB7 (*(volatile unsigned *)0x48000030) //Mode egister set for SDRAM
+
+
+// USB Host
+
+
+// INTERRUPT
+#define SRCPND (*(volatile unsigned *)0x4a000000) //Interrupt request status
+#define INTMOD (*(volatile unsigned *)0x4a000004) //Interrupt mode control
+#define INTMSK (*(volatile unsigned *)0x4a000008) //Interrupt mask control
+#define PRIORITY (*(volatile unsigned *)0x4a00000c) //IRQ priority control
+#define INTPND (*(volatile unsigned *)0x4a000010) //Interrupt request status
+#define INTOFFSET (*(volatile unsigned *)0x4a000014) //Interruot request source offset
+#define SUBSRCPND (*(volatile unsigned *)0x4a000018) //Sub source pending
+#define INTSUBMSK (*(volatile unsigned *)0x4a00001c) //Interrupt sub mask
+
+
+// DMA
+#define DISRC0 (*(volatile unsigned *)0x4b000000) //DMA 0 Initial source
+#define DISRCC0 (*(volatile unsigned *)0x4b000004) //DMA 0 Initial source control
+#define DIDST0 (*(volatile unsigned *)0x4b000008) //DMA 0 Initial Destination
+#define DIDSTC0 (*(volatile unsigned *)0x4b00000c) //DMA 0 Initial Destination control
+#define DCON0 (*(volatile unsigned *)0x4b000010) //DMA 0 Control
+#define DSTAT0 (*(volatile unsigned *)0x4b000014) //DMA 0 Status
+#define DCSRC0 (*(volatile unsigned *)0x4b000018) //DMA 0 Current source
+#define DCDST0 (*(volatile unsigned *)0x4b00001c) //DMA 0 Current destination
+#define DMASKTRIG0 (*(volatile unsigned *)0x4b000020) //DMA 0 Mask trigger
+
+#define DISRC1 (*(volatile unsigned *)0x4b000040) //DMA 1 Initial source
+#define DISRCC1 (*(volatile unsigned *)0x4b000044) //DMA 1 Initial source control
+#define DIDST1 (*(volatile unsigned *)0x4b000048) //DMA 1 Initial Destination
+#define DIDSTC1 (*(volatile unsigned *)0x4b00004c) //DMA 1 Initial Destination control
+#define DCON1 (*(volatile unsigned *)0x4b000050) //DMA 1 Control
+#define DSTAT1 (*(volatile unsigned *)0x4b000054) //DMA 1 Status
+#define DCSRC1 (*(volatile unsigned *)0x4b000058) //DMA 1 Current source
+#define DCDST1 (*(volatile unsigned *)0x4b00005c) //DMA 1 Current destination
+#define DMASKTRIG1 (*(volatile unsigned *)0x4b000060) //DMA 1 Mask trigger
+
+#define DISRC2 (*(volatile unsigned *)0x4b000080) //DMA 2 Initial source
+#define DISRCC2 (*(volatile unsigned *)0x4b000084) //DMA 2 Initial source control
+#define DIDST2 (*(volatile unsigned *)0x4b000088) //DMA 2 Initial Destination
+#define DIDSTC2 (*(volatile unsigned *)0x4b00008c) //DMA 2 Initial Destination control
+#define DCON2 (*(volatile unsigned *)0x4b000090) //DMA 2 Control
+#define DSTAT2 (*(volatile unsigned *)0x4b000094) //DMA 2 Status
+#define DCSRC2 (*(volatile unsigned *)0x4b000098) //DMA 2 Current source
+#define DCDST2 (*(volatile unsigned *)0x4b00009c) //DMA 2 Current destination
+#define DMASKTRIG2 (*(volatile unsigned *)0x4b0000a0) //DMA 2 Mask trigger
+
+#define DISRC3 (*(volatile unsigned *)0x4b0000c0) //DMA 3 Initial source
+#define DISRCC3 (*(volatile unsigned *)0x4b0000c4) //DMA 3 Initial source control
+#define DIDST3 (*(volatile unsigned *)0x4b0000c8) //DMA 3 Initial Destination
+#define DIDSTC3 (*(volatile unsigned *)0x4b0000cc) //DMA 3 Initial Destination control
+#define DCON3 (*(volatile unsigned *)0x4b0000d0) //DMA 3 Control
+#define DSTAT3 (*(volatile unsigned *)0x4b0000d4) //DMA 3 Status
+#define DCSRC3 (*(volatile unsigned *)0x4b0000d8) //DMA 3 Current source
+#define DCDST3 (*(volatile unsigned *)0x4b0000dc) //DMA 3 Current destination
+#define DMASKTRIG3 (*(volatile unsigned *)0x4b0000e0) //DMA 3 Mask trigger
+
+
+// CLOCK & POWER MANAGEMENT
+#define LOCKTIME (*(volatile unsigned *)0x4c000000) //PLL lock time counter
+#define MPLLCON (*(volatile unsigned *)0x4c000004) //MPLL Control
+#define UPLLCON (*(volatile unsigned *)0x4c000008) //UPLL Control
+#define CLKCON (*(volatile unsigned *)0x4c00000c) //Clock generator control
+#define CLKSLOW (*(volatile unsigned *)0x4c000010) //Slow clock control
+#define CLKDIVN (*(volatile unsigned *)0x4c000014) //Clock divider control
+#define CAMDIVN (*(volatile unsigned *)0x4c000018) //USB, CAM Clock divider control
+
+
+// LCD CONTROLLER
+#define LCDCON1 (*(volatile unsigned *)0x4d000000) //LCD control 1
+#define LCDCON2 (*(volatile unsigned *)0x4d000004) //LCD control 2
+#define LCDCON3 (*(volatile unsigned *)0x4d000008) //LCD control 3
+#define LCDCON4 (*(volatile unsigned *)0x4d00000c) //LCD control 4
+#define LCDCON5 (*(volatile unsigned *)0x4d000010) //LCD control 5
+#define LCDSADDR1 (*(volatile unsigned *)0x4d000014) //STN/TFT Frame buffer start address 1
+#define LCDSADDR2 (*(volatile unsigned *)0x4d000018) //STN/TFT Frame buffer start address 2
+#define LCDSADDR3 (*(volatile unsigned *)0x4d00001c) //STN/TFT Virtual screen address set
+#define REDLUT (*(volatile unsigned *)0x4d000020) //STN Red lookup table
+#define GREENLUT (*(volatile unsigned *)0x4d000024) //STN Green lookup table
+#define BLUELUT (*(volatile unsigned *)0x4d000028) //STN Blue lookup table
+#define DITHMODE (*(volatile unsigned *)0x4d00004c) //STN Dithering mode
+#define TPAL (*(volatile unsigned *)0x4d000050) //TFT Temporary palette
+#define LCDINTPND (*(volatile unsigned *)0x4d000054) //LCD Interrupt pending
+#define LCDSRCPND (*(volatile unsigned *)0x4d000058) //LCD Interrupt source
+#define LCDINTMSK (*(volatile unsigned *)0x4d00005c) //LCD Interrupt mask
+#define LPCSEL (*(volatile unsigned *)0x4d000060) //LPC3600 Control
+#define PALETTE 0x4d000400 //Palette start address
+
+
+// NAND flash
+#define NFCONF (*(volatile unsigned *)0x4e000000) //NAND Flash configuration
+#define NFCMD (*(volatile U8 *)0x4e000004) //NADD Flash command
+#define NFADDR (*(volatile U8 *)0x4e000008) //NAND Flash address
+#define NFDATA (*(volatile U8 *)0x4e00000c) //NAND Flash data
+#define NFSTAT (*(volatile unsigned *)0x4e000010) //NAND Flash operation status
+#define NFECC (*(volatile unsigned *)0x4e000014) //NAND Flash ECC
+#define NFECC0 (*(volatile U8 *)0x4e000014)
+#define NFECC1 (*(volatile U8 *)0x4e000015)
+#define NFECC2 (*(volatile U8 *)0x4e000016)
+
+// UART
+#define U0BASE (volatile unsigned *)0x50000000 //UART 0 Line control
+#define ULCON0 (*(volatile unsigned *)0x50000000) //UART 0 Line control
+#define UCON0 (*(volatile unsigned *)0x50000004) //UART 0 Control
+#define UFCON0 (*(volatile unsigned *)0x50000008) //UART 0 FIFO control
+#define UMCON0 (*(volatile unsigned *)0x5000000c) //UART 0 Modem control
+#define USTAT0 (*(volatile unsigned *)0x50000010) //UART 0 Tx/Rx status
+#define URXB0 (*(volatile unsigned *)0x50000014) //UART 0 Rx error status
+#define UFSTAT0 (*(volatile unsigned *)0x50000018) //UART 0 FIFO status
+#define UMSTAT0 (*(volatile unsigned *)0x5000001c) //UART 0 Modem status
+#define UBRD0 (*(volatile unsigned *)0x50000028) //UART 0 Baud ate divisor
+
+#define U1BASE *(volatile unsigned *)0x50004000 //UART 1 Line control
+#define ULCON1 (*(volatile unsigned *)0x50004000) //UART 1 Line control
+#define UCON1 (*(volatile unsigned *)0x50004004) //UART 1 Control
+#define UFCON1 (*(volatile unsigned *)0x50004008) //UART 1 FIFO control
+#define UMCON1 (*(volatile unsigned *)0x5000400c) //UART 1 Modem control
+#define USTAT1 (*(volatile unsigned *)0x50004010) //UART 1 Tx/Rx status
+#define URXB1 (*(volatile unsigned *)0x50004014) //UART 1 Rx error status
+#define UFSTAT1 (*(volatile unsigned *)0x50004018) //UART 1 FIFO status
+#define UMSTAT1 (*(volatile unsigned *)0x5000401c) //UART 1 Modem status
+#define UBRD1 (*(volatile unsigned *)0x50004028) //UART 1 Baud ate divisor
+
+#define U2BASE *(volatile unsigned *)0x50008000 //UART 2 Line control
+#define ULCON2 (*(volatile unsigned *)0x50008000) //UART 2 Line control
+#define UCON2 (*(volatile unsigned *)0x50008004) //UART 2 Control
+#define UFCON2 (*(volatile unsigned *)0x50008008) //UART 2 FIFO control
+#define UMCON2 (*(volatile unsigned *)0x5000800c) //UART 2 Modem control
+#define USTAT2 (*(volatile unsigned *)0x50008010) //UART 2 Tx/Rx status
+#define URXB2 (*(volatile unsigned *)0x50008014) //UART 2 Rx error status
+#define UFSTAT2 (*(volatile unsigned *)0x50008018) //UART 2 FIFO status
+#define UMSTAT2 (*(volatile unsigned *)0x5000801c) //UART 2 Modem status
+#define UBRD2 (*(volatile unsigned *)0x50008028) //UART 2 Baud ate divisor
+
+#ifdef __BIG_ENDIAN
+#define UTXH0 (*(volatile unsigned char *)0x50000023) //UART 0 Transmission Hold
+#define URXH0 (*(volatile unsigned char *)0x50000027) //UART 0 Receive buffer
+#define UTXH1 (*(volatile unsigned char *)0x50004023) //UART 1 Transmission Hold
+#define URXH1 (*(volatile unsigned char *)0x50004027) //UART 1 Receive buffer
+#define UTXH2 (*(volatile unsigned char *)0x50008023) //UART 2 Transmission Hold
+#define URXH2 (*(volatile unsigned char *)0x50008027) //UART 2 Receive buffer
+
+#define WrUTXH0(ch) (*(volatile unsigned char *)0x50000023)=(unsigned char)(ch)
+#define RdURXH0() (*(volatile unsigned char *)0x50000027)
+#define WrUTXH1(ch) (*(volatile unsigned char *)0x50004023)=(unsigned char)(ch)
+#define RdURXH1() (*(volatile unsigned char *)0x50004027)
+#define WrUTXH2(ch) (*(volatile unsigned char *)0x50008023)=(unsigned char)(ch)
+#define RdURXH2() (*(volatile unsigned char *)0x50008027)
+
+#else //Little Endian
+#define UTXH0 (*(volatile unsigned char *)0x50000020) //UART 0 Transmission Hold
+#define URXH0 (*(volatile unsigned char *)0x50000024) //UART 0 Receive buffer
+#define UTXH1 (*(volatile unsigned char *)0x50004020) //UART 1 Transmission Hold
+#define URXH1 (*(volatile unsigned char *)0x50004024) //UART 1 Receive buffer
+#define UTXH2 (*(volatile unsigned char *)0x50008020) //UART 2 Transmission Hold
+#define URXH2 (*(volatile unsigned char *)0x50008024) //UART 2 Receive buffer
+
+#define WrUTXH0(ch) (*(volatile unsigned char *)0x50000020)=(unsigned char)(ch)
+#define RdURXH0() (*(volatile unsigned char *)0x50000024)
+#define WrUTXH1(ch) (*(volatile unsigned char *)0x50004020)=(unsigned char)(ch)
+#define RdURXH1() (*(volatile unsigned char *)0x50004024)
+#define WrUTXH2(ch) (*(volatile unsigned char *)0x50008020)=(unsigned char)(ch)
+#define RdURXH2() (*(volatile unsigned char *)0x50008024)
+
+#endif
+
+
+// PWM TIMER
+#define TCFG0 (*(volatile unsigned *)0x51000000) //Timer 0 configuration
+#define TCFG1 (*(volatile unsigned *)0x51000004) //Timer 1 configuration
+#define TCON (*(volatile unsigned *)0x51000008) //Timer control
+#define TCNTB0 (*(volatile unsigned *)0x5100000c) //Timer count buffer 0
+#define TCMPB0 (*(volatile unsigned *)0x51000010) //Timer compare buffer 0
+#define TCNTO0 (*(volatile unsigned *)0x51000014) //Timer count observation 0
+#define TCNTB1 (*(volatile unsigned *)0x51000018) //Timer count buffer 1
+#define TCMPB1 (*(volatile unsigned *)0x5100001c) //Timer compare buffer 1
+#define TCNTO1 (*(volatile unsigned *)0x51000020) //Timer count observation 1
+#define TCNTB2 (*(volatile unsigned *)0x51000024) //Timer count buffer 2
+#define TCMPB2 (*(volatile unsigned *)0x51000028) //Timer compare buffer 2
+#define TCNTO2 (*(volatile unsigned *)0x5100002c) //Timer count observation 2
+#define TCNTB3 (*(volatile unsigned *)0x51000030) //Timer count buffer 3
+#define TCMPB3 (*(volatile unsigned *)0x51000034) //Timer compare buffer 3
+#define TCNTO3 (*(volatile unsigned *)0x51000038) //Timer count observation 3
+#define TCNTB4 (*(volatile unsigned *)0x5100003c) //Timer count buffer 4
+#define TCNTO4 (*(volatile unsigned *)0x51000040) //Timer count observation 4
+
+// Added for 2440
+#define FLTOUT (*(volatile unsigned *)0x560000c0) // Filter output(Read only)
+#define DSC0 (*(volatile unsigned *)0x560000c4) // Strength control register 0
+#define DSC1 (*(volatile unsigned *)0x560000c8) // Strength control register 1
+#define MSLCON (*(volatile unsigned *)0x560000cc) // Memory sleep control register
+
+
+// USB DEVICE
+#ifdef __BIG_ENDIAN
+#define FUNC_ADDR_REG (*(volatile unsigned char *)0x52000143) //Function address
+#define PWR_REG (*(volatile unsigned char *)0x52000147) //Power management
+#define EP_INT_REG (*(volatile unsigned char *)0x5200014b) //EP Interrupt pending and clear
+#define USB_INT_REG (*(volatile unsigned char *)0x5200015b) //USB Interrupt pending and clear
+#define EP_INT_EN_REG (*(volatile unsigned char *)0x5200015f) //Interrupt enable
+#define USB_INT_EN_REG (*(volatile unsigned char *)0x5200016f)
+#define FRAME_NUM1_REG (*(volatile unsigned char *)0x52000173) //Frame number lower byte
+#define FRAME_NUM2_REG (*(volatile unsigned char *)0x52000177) //Frame number higher byte
+#define INDEX_REG (*(volatile unsigned char *)0x5200017b) //Register index
+#define MAXP_REG (*(volatile unsigned char *)0x52000183) //Endpoint max packet
+#define EP0_CSR (*(volatile unsigned char *)0x52000187) //Endpoint 0 status
+#define IN_CSR1_REG (*(volatile unsigned char *)0x52000187) //In endpoint control status
+#define IN_CSR2_REG (*(volatile unsigned char *)0x5200018b)
+#define OUT_CSR1_REG (*(volatile unsigned char *)0x52000193) //Out endpoint control status
+#define OUT_CSR2_REG (*(volatile unsigned char *)0x52000197)
+#define OUT_FIFO_CNT1_REG (*(volatile unsigned char *)0x5200019b) //Endpoint out write count
+#define OUT_FIFO_CNT2_REG (*(volatile unsigned char *)0x5200019f)
+#define EP0_FIFO (*(volatile unsigned char *)0x520001c3) //Endpoint 0 FIFO
+#define EP1_FIFO (*(volatile unsigned char *)0x520001c7) //Endpoint 1 FIFO
+#define EP2_FIFO (*(volatile unsigned char *)0x520001cb) //Endpoint 2 FIFO
+#define EP3_FIFO (*(volatile unsigned char *)0x520001cf) //Endpoint 3 FIFO
+#define EP4_FIFO (*(volatile unsigned char *)0x520001d3) //Endpoint 4 FIFO
+#define EP1_DMA_CON (*(volatile unsigned char *)0x52000203) //EP1 DMA interface control
+#define EP1_DMA_UNIT (*(volatile unsigned char *)0x52000207) //EP1 DMA Tx unit counter
+#define EP1_DMA_FIFO (*(volatile unsigned char *)0x5200020b) //EP1 DMA Tx FIFO counter
+#define EP1_DMA_TTC_L (*(volatile unsigned char *)0x5200020f) //EP1 DMA total Tx counter
+#define EP1_DMA_TTC_M (*(volatile unsigned char *)0x52000213)
+#define EP1_DMA_TTC_H (*(volatile unsigned char *)0x52000217)
+#define EP2_DMA_CON (*(volatile unsigned char *)0x5200021b) //EP2 DMA interface control
+#define EP2_DMA_UNIT (*(volatile unsigned char *)0x5200021f) //EP2 DMA Tx unit counter
+#define EP2_DMA_FIFO (*(volatile unsigned char *)0x52000223) //EP2 DMA Tx FIFO counter
+#define EP2_DMA_TTC_L (*(volatile unsigned char *)0x52000227) //EP2 DMA total Tx counter
+#define EP2_DMA_TTC_M (*(volatile unsigned char *)0x5200022b)
+#define EP2_DMA_TTC_H (*(volatile unsigned char *)0x5200022f)
+#define EP3_DMA_CON (*(volatile unsigned char *)0x52000243) //EP3 DMA interface control
+#define EP3_DMA_UNIT (*(volatile unsigned char *)0x52000247) //EP3 DMA Tx unit counter
+#define EP3_DMA_FIFO (*(volatile unsigned char *)0x5200024b) //EP3 DMA Tx FIFO counter
+#define EP3_DMA_TTC_L (*(volatile unsigned char *)0x5200024f) //EP3 DMA total Tx counter
+#define EP3_DMA_TTC_M (*(volatile unsigned char *)0x52000253)
+#define EP3_DMA_TTC_H (*(volatile unsigned char *)0x52000257)
+#define EP4_DMA_CON (*(volatile unsigned char *)0x5200025b) //EP4 DMA interface control
+#define EP4_DMA_UNIT (*(volatile unsigned char *)0x5200025f) //EP4 DMA Tx unit counter
+#define EP4_DMA_FIFO (*(volatile unsigned char *)0x52000263) //EP4 DMA Tx FIFO counter
+#define EP4_DMA_TTC_L (*(volatile unsigned char *)0x52000267) //EP4 DMA total Tx counter
+#define EP4_DMA_TTC_M (*(volatile unsigned char *)0x5200026b)
+#define EP4_DMA_TTC_H (*(volatile unsigned char *)0x5200026f)
+
+#else // Little Endian
+#define FUNC_ADDR_REG (*(volatile unsigned char *)0x52000140) //Function address
+#define PWR_REG (*(volatile unsigned char *)0x52000144) //Power management
+#define EP_INT_REG (*(volatile unsigned char *)0x52000148) //EP Interrupt pending and clear
+#define USB_INT_REG (*(volatile unsigned char *)0x52000158) //USB Interrupt pending and clear
+#define EP_INT_EN_REG (*(volatile unsigned char *)0x5200015c) //Interrupt enable
+#define USB_INT_EN_REG (*(volatile unsigned char *)0x5200016c)
+#define FRAME_NUM1_REG (*(volatile unsigned char *)0x52000170) //Frame number lower byte
+#define FRAME_NUM2_REG (*(volatile unsigned char *)0x52000174) //Frame number higher byte
+#define INDEX_REG (*(volatile unsigned char *)0x52000178) //Register index
+#define MAXP_REG (*(volatile unsigned char *)0x52000180) //Endpoint max packet
+#define EP0_CSR (*(volatile unsigned char *)0x52000184) //Endpoint 0 status
+#define IN_CSR1_REG (*(volatile unsigned char *)0x52000184) //In endpoint control status
+#define IN_CSR2_REG (*(volatile unsigned char *)0x52000188)
+#define OUT_CSR1_REG (*(volatile unsigned char *)0x52000190) //Out endpoint control status
+#define OUT_CSR2_REG (*(volatile unsigned char *)0x52000194)
+#define OUT_FIFO_CNT1_REG (*(volatile unsigned char *)0x52000198) //Endpoint out write count
+#define OUT_FIFO_CNT2_REG (*(volatile unsigned char *)0x5200019c)
+#define EP0_FIFO (*(volatile unsigned char *)0x520001c0) //Endpoint 0 FIFO
+#define EP1_FIFO (*(volatile unsigned char *)0x520001c4) //Endpoint 1 FIFO
+#define EP2_FIFO (*(volatile unsigned char *)0x520001c8) //Endpoint 2 FIFO
+#define EP3_FIFO (*(volatile unsigned char *)0x520001cc) //Endpoint 3 FIFO
+#define EP4_FIFO (*(volatile unsigned char *)0x520001d0) //Endpoint 4 FIFO
+#define EP1_DMA_CON (*(volatile unsigned char *)0x52000200) //EP1 DMA interface control
+#define EP1_DMA_UNIT (*(volatile unsigned char *)0x52000204) //EP1 DMA Tx unit counter
+#define EP1_DMA_FIFO (*(volatile unsigned char *)0x52000208) //EP1 DMA Tx FIFO counter
+#define EP1_DMA_TTC_L (*(volatile unsigned char *)0x5200020c) //EP1 DMA total Tx counter
+#define EP1_DMA_TTC_M (*(volatile unsigned char *)0x52000210)
+#define EP1_DMA_TTC_H (*(volatile unsigned char *)0x52000214)
+#define EP2_DMA_CON (*(volatile unsigned char *)0x52000218) //EP2 DMA interface control
+#define EP2_DMA_UNIT (*(volatile unsigned char *)0x5200021c) //EP2 DMA Tx unit counter
+#define EP2_DMA_FIFO (*(volatile unsigned char *)0x52000220) //EP2 DMA Tx FIFO counter
+#define EP2_DMA_TTC_L (*(volatile unsigned char *)0x52000224) //EP2 DMA total Tx counter
+#define EP2_DMA_TTC_M (*(volatile unsigned char *)0x52000228)
+#define EP2_DMA_TTC_H (*(volatile unsigned char *)0x5200022c)
+#define EP3_DMA_CON (*(volatile unsigned char *)0x52000240) //EP3 DMA interface control
+#define EP3_DMA_UNIT (*(volatile unsigned char *)0x52000244) //EP3 DMA Tx unit counter
+#define EP3_DMA_FIFO (*(volatile unsigned char *)0x52000248) //EP3 DMA Tx FIFO counter
+#define EP3_DMA_TTC_L (*(volatile unsigned char *)0x5200024c) //EP3 DMA total Tx counter
+#define EP3_DMA_TTC_M (*(volatile unsigned char *)0x52000250)
+#define EP3_DMA_TTC_H (*(volatile unsigned char *)0x52000254)
+#define EP4_DMA_CON (*(volatile unsigned char *)0x52000258) //EP4 DMA interface control
+#define EP4_DMA_UNIT (*(volatile unsigned char *)0x5200025c) //EP4 DMA Tx unit counter
+#define EP4_DMA_FIFO (*(volatile unsigned char *)0x52000260) //EP4 DMA Tx FIFO counter
+#define EP4_DMA_TTC_L (*(volatile unsigned char *)0x52000264) //EP4 DMA total Tx counter
+#define EP4_DMA_TTC_M (*(volatile unsigned char *)0x52000268)
+#define EP4_DMA_TTC_H (*(volatile unsigned char *)0x5200026c)
+#endif // __BIG_ENDIAN
+
+
+// WATCH DOG TIMER
+#define WTCON (*(volatile unsigned *)0x53000000) //Watch-dog timer mode
+#define WTDAT (*(volatile unsigned *)0x53000004) //Watch-dog timer data
+#define WTCNT (*(volatile unsigned *)0x53000008) //Eatch-dog timer count
+
+
+// IIC
+#define IICCON (*(volatile unsigned *)0x54000000) //IIC control
+#define IICSTAT (*(volatile unsigned *)0x54000004) //IIC status
+#define IICADD (*(volatile unsigned *)0x54000008) //IIC address
+#define IICDS (*(volatile unsigned *)0x5400000c) //IIC data shift
+
+
+// IIS
+#define IISCON (*(volatile unsigned *)0x55000000) //IIS Control
+#define IISMOD (*(volatile unsigned *)0x55000004) //IIS Mode
+#define IISPSR (*(volatile unsigned *)0x55000008) //IIS Prescaler
+#define IISFCON (*(volatile unsigned *)0x5500000c) //IIS FIFO control
+
+#ifdef __BIG_ENDIAN
+#define IISFIFO ((volatile unsigned short *)0x55000012) //IIS FIFO entry
+
+#else //Little Endian
+#define IISFIFO ((volatile unsigned short *)0x55000010) //IIS FIFO entry
+
+#endif
+
+
+// I/O PORT
+#define GPACON (*(volatile unsigned *)0x56000000) //Port A control
+#define GPADAT (*(volatile unsigned *)0x56000004) //Port A data
+
+#define GPBCON (*(volatile unsigned *)0x56000010) //Port B control
+#define GPBDAT (*(volatile unsigned *)0x56000014) //Port B data
+#define GPBUP (*(volatile unsigned *)0x56000018) //Pull-up control B
+
+#define GPCCON (*(volatile unsigned *)0x56000020) //Port C control
+#define GPCDAT (*(volatile unsigned *)0x56000024) //Port C data
+#define GPCUP (*(volatile unsigned *)0x56000028) //Pull-up control C
+
+#define GPDCON (*(volatile unsigned *)0x56000030) //Port D control
+#define GPDDAT (*(volatile unsigned *)0x56000034) //Port D data
+#define GPDUP (*(volatile unsigned *)0x56000038) //Pull-up control D
+
+#define GPECON (*(volatile unsigned *)0x56000040) //Port E control
+#define GPEDAT (*(volatile unsigned *)0x56000044) //Port E data
+#define GPEUP (*(volatile unsigned *)0x56000048) //Pull-up control E
+
+#define GPFCON (*(volatile unsigned *)0x56000050) //Port F control
+#define GPFDAT (*(volatile unsigned *)0x56000054) //Port F data
+#define GPFUP (*(volatile unsigned *)0x56000058) //Pull-up control F
+
+#define GPGCON (*(volatile unsigned *)0x56000060) //Port G control
+#define GPGDAT (*(volatile unsigned *)0x56000064) //Port G data
+#define GPGUP (*(volatile unsigned *)0x56000068) //Pull-up control G
+
+#define GPHCON (*(volatile unsigned *)0x56000070) //Port H control
+#define GPHDAT (*(volatile unsigned *)0x56000074) //Port H data
+#define GPHUP (*(volatile unsigned *)0x56000078) //Pull-up control H
+
+#define GPJCON (*(volatile unsigned *)0x560000d0) //Port J control
+#define GPJDAT (*(volatile unsigned *)0x560000d4) //Port J data
+#define GPJUP (*(volatile unsigned *)0x560000d8) //Pull-up control J
+
+#define MISCCR (*(volatile unsigned *)0x56000080) //Miscellaneous control
+#define DCLKCON (*(volatile unsigned *)0x56000084) //DCLK0/1 control
+#define EXTINT0 (*(volatile unsigned *)0x56000088) //External interrupt control egister 0
+#define EXTINT1 (*(volatile unsigned *)0x5600008c) //External interrupt control egister 1
+#define EXTINT2 (*(volatile unsigned *)0x56000090) //External interrupt control egister 2
+#define EINTFLT0 (*(volatile unsigned *)0x56000094) //Reserved
+#define EINTFLT1 (*(volatile unsigned *)0x56000098) //Reserved
+#define EINTFLT2 (*(volatile unsigned *)0x5600009c) //External interrupt filter control egister 2
+#define EINTFLT3 (*(volatile unsigned *)0x560000a0) //External interrupt filter control egister 3
+#define EINTMASK (*(volatile unsigned *)0x560000a4) //External interrupt mask
+#define EINTPEND (*(volatile unsigned *)0x560000a8) //External interrupt pending
+#define GSTATUS0 (*(volatile unsigned *)0x560000ac) //External pin status
+#define GSTATUS1 (*(volatile unsigned *)0x560000b0) //Chip ID(0x32410000)
+#define GSTATUS2 (*(volatile unsigned *)0x560000b4) //Reset type
+#define GSTATUS3 (*(volatile unsigned *)0x560000b8) //Saved data0(32-bit) before entering POWER_OFF mode
+#define GSTATUS4 (*(volatile unsigned *)0x560000bc) //Saved data0(32-bit) before entering POWER_OFF mode
+
+
+// RTC
+#ifdef __BIG_ENDIAN
+#define RTCCON (*(volatile unsigned char *)0x57000043) //RTC control
+#define TICNT (*(volatile unsigned char *)0x57000047) //Tick time count
+#define RTCALM (*(volatile unsigned char *)0x57000053) //RTC alarm control
+#define ALMSEC (*(volatile unsigned char *)0x57000057) //Alarm second
+#define ALMMIN (*(volatile unsigned char *)0x5700005b) //Alarm minute
+#define ALMHOUR (*(volatile unsigned char *)0x5700005f) //Alarm Hour
+#define ALMDATE (*(volatile unsigned char *)0x57000063) //Alarm day <-- May 06, 2002 SOP
+#define ALMMON (*(volatile unsigned char *)0x57000067) //Alarm month
+#define ALMYEAR (*(volatile unsigned char *)0x5700006b) //Alarm year
+#define RTCRST (*(volatile unsigned char *)0x5700006f) //RTC ound eset
+#define BCDSEC (*(volatile unsigned char *)0x57000073) //BCD second
+#define BCDMIN (*(volatile unsigned char *)0x57000077) //BCD minute
+#define BCDHOUR (*(volatile unsigned char *)0x5700007b) //BCD hour
+#define BCDDATE (*(volatile unsigned char *)0x5700007f) //BCD day <-- May 06, 2002 SOP
+#define BCDDAY (*(volatile unsigned char *)0x57000083) //BCD date <-- May 06, 2002 SOP
+#define BCDMON (*(volatile unsigned char *)0x57000087) //BCD month
+#define BCDYEAR (*(volatile unsigned char *)0x5700008b) //BCD year
+
+#else //Little Endian
+#define RTCCON (*(volatile unsigned char *)0x57000040) //RTC control
+#define TICNT (*(volatile unsigned char *)0x57000044) //Tick time count
+#define RTCALM (*(volatile unsigned char *)0x57000050) //RTC alarm control
+#define ALMSEC (*(volatile unsigned char *)0x57000054) //Alarm second
+#define ALMMIN (*(volatile unsigned char *)0x57000058) //Alarm minute
+#define ALMHOUR (*(volatile unsigned char *)0x5700005c) //Alarm Hour
+#define ALMDATE (*(volatile unsigned char *)0x57000060) //Alarm day <-- May 06, 2002 SOP
+#define ALMMON (*(volatile unsigned char *)0x57000064) //Alarm month
+#define ALMYEAR (*(volatile unsigned char *)0x57000068) //Alarm year
+#define RTCRST (*(volatile unsigned char *)0x5700006c) //RTC ound eset
+#define BCDSEC (*(volatile unsigned char *)0x57000070) //BCD second
+#define BCDMIN (*(volatile unsigned char *)0x57000074) //BCD minute
+#define BCDHOUR (*(volatile unsigned char *)0x57000078) //BCD hour
+#define BCDDATE (*(volatile unsigned char *)0x5700007c) //BCD day <-- May 06, 2002 SOP
+#define BCDDAY (*(volatile unsigned char *)0x57000080) //BCD date <-- May 06, 2002 SOP
+#define BCDMON (*(volatile unsigned char *)0x57000084) //BCD month
+#define BCDYEAR (*(volatile unsigned char *)0x57000088) //BCD year
+#endif //RTC
+
+
+// ADC
+#define ADCCON (*(volatile unsigned *)0x58000000) //ADC control
+#define ADCTSC (*(volatile unsigned *)0x58000004) //ADC touch screen control
+#define ADCDLY (*(volatile unsigned *)0x58000008) //ADC start or Interval Delay
+#define ADCDAT0 (*(volatile unsigned *)0x5800000c) //ADC conversion data 0
+#define ADCDAT1 (*(volatile unsigned *)0x58000010) //ADC conversion data 1
+
+// SPI
+#define SPCON0 (*(volatile unsigned *)0x59000000) //SPI0 control
+#define SPSTA0 (*(volatile unsigned *)0x59000004) //SPI0 status
+#define SPPIN0 (*(volatile unsigned *)0x59000008) //SPI0 pin control
+#define SPPRE0 (*(volatile unsigned *)0x5900000c) //SPI0 baud ate prescaler
+#define SPTDAT0 (*(volatile unsigned *)0x59000010) //SPI0 Tx data
+#define SPRDAT0 (*(volatile unsigned *)0x59000014) //SPI0 Rx data
+
+#define SPCON1 (*(volatile unsigned *)0x59000020) //SPI1 control
+#define SPSTA1 (*(volatile unsigned *)0x59000024) //SPI1 status
+#define SPPIN1 (*(volatile unsigned *)0x59000028) //SPI1 pin control
+#define SPPRE1 (*(volatile unsigned *)0x5900002c) //SPI1 baud ate prescaler
+#define SPTDAT1 (*(volatile unsigned *)0x59000030) //SPI1 Tx data
+#define SPRDAT1 (*(volatile unsigned *)0x59000034) //SPI1 Rx data
+
+
+// SD Interface
+#define SDICON (*(volatile unsigned *)0x5a000000) //SDI control
+#define SDIPRE (*(volatile unsigned *)0x5a000004) //SDI baud ate prescaler
+#define SDICARG (*(volatile unsigned *)0x5a000008) //SDI command argument
+#define SDICCON (*(volatile unsigned *)0x5a00000c) //SDI command control
+#define SDICSTA (*(volatile unsigned *)0x5a000010) //SDI command status
+#define SDIRSP0 (*(volatile unsigned *)0x5a000014) //SDI esponse 0
+#define SDIRSP1 (*(volatile unsigned *)0x5a000018) //SDI esponse 1
+#define SDIRSP2 (*(volatile unsigned *)0x5a00001c) //SDI esponse 2
+#define SDIRSP3 (*(volatile unsigned *)0x5a000020) //SDI esponse 3
+#define SDIDTIMER (*(volatile unsigned *)0x5a000024) //SDI data/busy timer
+#define SDIBSIZE (*(volatile unsigned *)0x5a000028) //SDI block size
+#define SDIDCON (*(volatile unsigned *)0x5a00002c) //SDI data control
+#define SDIDCNT (*(volatile unsigned *)0x5a000030) //SDI data emain counter
+#define SDIDSTA (*(volatile unsigned *)0x5a000034) //SDI data status
+#define SDIFSTA (*(volatile unsigned *)0x5a000038) //SDI FIFO status
+#define SDIIMSK (*(volatile unsigned *)0x5a000040) //SDI interrupt mask
+
+#ifdef __BIG_ENDIAN /* edited for 2440A */
+#define SDIDAT (*(volatile unsigned *)0x5a00004c)
+#else // Little Endian
+#define SDIDAT (*(volatile unsigned *)0x5a000040)
+#endif //SD Interface
+
+// PENDING BIT
+#define INTEINT0 (0)
+#define INTEINT1 (1)
+#define INTEINT2 (2)
+#define INTEINT3 (3)
+#define INTEINT4_7 (4)
+#define INTEINT8_23 (5)
+#define INTNOTUSED6 (6)
+#define INTBAT_FLT (7)
+#define INTTICK (8)
+#define INTWDT (9)
+#define INTTIMER0 (10)
+#define INTTIMER1 (11)
+#define INTTIMER2 (12)
+#define INTTIMER3 (13)
+#define INTTIMER4 (14)
+#define INTUART2 (15)
+#define INTLCD (16)
+#define INTDMA0 (17)
+#define INTDMA1 (18)
+#define INTDMA2 (19)
+#define INTDMA3 (20)
+#define INTSDI (21)
+#define INTSPI0 (22)
+#define INTUART1 (23)
+//#define INTNOTUSED24 (24)
+#define INTNIC (24)
+#define INTUSBD (25)
+#define INTUSBH (26)
+#define INTIIC (27)
+#define INTUART0 (28)
+#define INTSPI1 (29)
+#define INTRTC (30)
+#define INTADC (31)
+#define BIT_ALLMSK (0xffffffff)
+
+#define BIT_SUB_ALLMSK (0x7ff)
+#define INTSUB_ADC (10)
+#define INTSUB_TC (9)
+#define INTSUB_ERR2 (8)
+#define INTSUB_TXD2 (7)
+#define INTSUB_RXD2 (6)
+#define INTSUB_ERR1 (5)
+#define INTSUB_TXD1 (4)
+#define INTSUB_RXD1 (3)
+#define INTSUB_ERR0 (2)
+#define INTSUB_TXD0 (1)
+#define INTSUB_RXD0 (0)
+
+#define BIT_SUB_ADC (0x1<<10)
+#define BIT_SUB_TC (0x1<<9)
+#define BIT_SUB_ERR2 (0x1<<8)
+#define BIT_SUB_TXD2 (0x1<<7)
+#define BIT_SUB_RXD2 (0x1<<6)
+#define BIT_SUB_ERR1 (0x1<<5)
+#define BIT_SUB_TXD1 (0x1<<4)
+#define BIT_SUB_RXD1 (0x1<<3)
+#define BIT_SUB_ERR0 (0x1<<2)
+#define BIT_SUB_TXD0 (0x1<<1)
+#define BIT_SUB_RXD0 (0x1<<0)
+
+#define ClearPending(bit) {SRCPND = bit;INTPND = bit;INTPND;}
+//Wait until INTPND is changed for the case that the ISR is very short.
+
+#define INTGLOBAL 32
+
+/*****************************/
+/* CPU Mode */
+/*****************************/
+#define USERMODE 0x10
+#define FIQMODE 0x11
+#define IRQMODE 0x12
+#define SVCMODE 0x13
+#define ABORTMODE 0x17
+#define UNDEFMODE 0x1b
+#define MODEMASK 0x1f
+#define NOINT 0xc0
+
+struct rt_hw_register
+{
+ rt_uint32_t r0;
+ rt_uint32_t r1;
+ rt_uint32_t r2;
+ rt_uint32_t r3;
+ rt_uint32_t r4;
+ rt_uint32_t r5;
+ rt_uint32_t r6;
+ rt_uint32_t r7;
+ rt_uint32_t r8;
+ rt_uint32_t r9;
+ rt_uint32_t r10;
+ rt_uint32_t fp;
+ rt_uint32_t ip;
+ rt_uint32_t sp;
+ rt_uint32_t lr;
+ rt_uint32_t pc;
+ rt_uint32_t cpsr;
+ rt_uint32_t ORIG_r0;
+};
+
+#ifdef __cplusplus
+}
+#endif
+
+/*@}*/
+
+#endif
diff --git a/libcpu/arm/s3c24x0/serial.c b/libcpu/arm/s3c24x0/serial.c
new file mode 100644
index 0000000000..2a572f0dfa
--- /dev/null
+++ b/libcpu/arm/s3c24x0/serial.c
@@ -0,0 +1,313 @@
+/*
+ * File : serial.c
+ * This file is part of RT-Thread RTOS
+ * COPYRIGHT (C) 2006, RT-Thread Development Team
+ *
+ * The license and distribution terms for this file may be
+ * found in the file LICENSE in this distribution or at
+ * http://openlab.rt-thread.com/license/LICENSE
+ *
+ * Change Logs:
+ * Date Author Notes
+ * 2006-03-13 Bernard first version
+ * 2009-04-20 yi.qiu modified according bernard's stm32 version
+ */
+
+#include <rtthread.h>
+
+#include "serial.h"
+
+/**
+ * @addtogroup S3C24X0
+ */
+/*@{*/
+
+/* RT-Thread Device Interface */
+/**
+ * This function initializes serial
+ */
+static rt_err_t rt_serial_init (rt_device_t dev)
+{
+ struct serial_device* uart = (struct serial_device*) dev->private;
+
+ if (!(dev->flag & RT_DEVICE_FLAG_ACTIVATED))
+ {
+
+ if (dev->flag & RT_DEVICE_FLAG_INT_RX)
+ {
+ rt_memset(uart->int_rx->rx_buffer, 0,
+ sizeof(uart->int_rx->rx_buffer));
+ uart->int_rx->read_index = uart->int_rx->read_index = 0;
+ }
+
+ if (dev->flag & RT_DEVICE_FLAG_INT_TX)
+ {
+ rt_memset(uart->int_tx->tx_buffer, 0,
+ sizeof(uart->int_tx->tx_buffer));
+ uart->int_tx->write_index = uart->int_tx->save_index = 0;
+ }
+
+ dev->flag |= RT_DEVICE_FLAG_ACTIVATED;
+ }
+
+ return RT_EOK;
+}
+
+/**
+ * This function read a character from serial without interrupt enable mode
+ *
+ * @return the read char
+ */
+char rt_serial_getc(struct serial_device* uart)
+{
+ rt_base_t level;
+ char ch = 0;
+
+ /* disable interrupt */
+ level = rt_hw_interrupt_disable();
+
+ if (uart->int_rx->read_index != uart->int_rx->save_index)
+ {
+ ch = uart->int_rx->rx_buffer[uart->int_rx->read_index];
+
+ uart->int_rx->read_index ++;
+ if (uart->int_rx->read_index >= UART_RX_BUFFER_SIZE)
+ uart->int_rx->read_index = 0;
+ }
+
+ /* enable interrupt */
+ rt_hw_interrupt_enable(level);
+
+ return ch;
+}
+
+/* save a char to serial buffer */
+void rt_serial_savechar(struct serial_device* uart, char ch)
+{
+ rt_base_t level;
+
+ /* disable interrupt */
+ level = rt_hw_interrupt_disable();
+
+ uart->int_rx->rx_buffer[uart->int_rx->save_index] = ch;
+ uart->int_rx->save_index ++;
+ if (uart->int_rx->save_index >= UART_RX_BUFFER_SIZE)
+ uart->int_rx->save_index = 0;
+
+ /* if the next position is read index, discard this 'read char' */
+ if (uart->int_rx->save_index == uart->int_rx->read_index)
+ {
+ uart->int_rx->read_index ++;
+ if (uart->int_rx->read_index >= UART_RX_BUFFER_SIZE)
+ uart->int_rx->read_index = 0;
+ }
+
+ /* enable interrupt */
+ rt_hw_interrupt_enable(level);
+}
+
+/**
+ * This function will write a character to serial without interrupt enable mode
+ *
+ * @param c the char to write
+ */
+void rt_serial_putc(rt_device_t device, const char c)
+{
+ struct serial_device* uart = (struct serial_device*) device->private;
+
+ /*
+ * to be polite with serial console add a line feed
+ * to the carriage return character
+ */
+ if (c=='\n' && (device->flag & RT_DEVICE_FLAG_STREAM))
+ rt_serial_putc(device, '\r');
+
+ while (!(uart->uart_device->ustat & USTAT_TXB_EMPTY));
+ uart->uart_device->utxh = (c & 0x1FF);
+}
+
+static rt_err_t rt_serial_open(rt_device_t dev, rt_uint16_t oflag)
+{
+ RT_ASSERT(dev != RT_NULL);
+
+ return RT_EOK;
+}
+
+static rt_err_t rt_serial_close(rt_device_t dev)
+{
+ RT_ASSERT(dev != RT_NULL);
+
+ return RT_EOK;
+}
+
+static rt_size_t rt_serial_read (rt_device_t dev, rt_off_t pos, void* buffer, rt_size_t size)
+{
+ rt_uint8_t* ptr;
+ rt_err_t err_code;
+ struct serial_device* uart;
+
+ ptr = buffer;
+ err_code = RT_EOK;
+ uart = (struct serial_device*)dev->private;
+
+ if (dev->flag & RT_DEVICE_FLAG_INT_RX)
+ {
+ rt_int32_t ch;
+
+ /* interrupt mode Rx */
+ while (size)
+ {
+ /* get a character */
+ ch = rt_serial_getc(uart);
+ if (ch < 0)
+ {
+ /* set error code */
+ err_code = -RT_EEMPTY;
+ }
+ else
+ {
+ *ptr++ = ch;
+ size --;
+ }
+ }
+ }
+ else
+ {
+ /* polling mode */
+ while ((rt_uint32_t)ptr - (rt_uint32_t)buffer < size)
+ {
+ while (uart->uart_device->ustat & USTAT_RCV_READY)
+ {
+ *ptr = uart->uart_device->urxh & 0xff;
+ ptr ++;
+ }
+ }
+ }
+
+ /* set error code */
+ rt_set_errno(err_code);
+ return (rt_uint32_t)ptr - (rt_uint32_t)buffer;
+}
+
+static rt_size_t rt_serial_write (rt_device_t dev, rt_off_t pos, const void* buffer, rt_size_t size)
+{
+ rt_uint8_t* ptr;
+ rt_err_t err_code;
+ struct serial_device* uart;
+
+ err_code = RT_EOK;
+ ptr = (rt_uint8_t*)buffer;
+ uart = (struct serial_device*)dev->private;
+
+ if (dev->flag & RT_DEVICE_FLAG_INT_TX)
+ {
+ /* interrupt mode Tx */
+ while (uart->int_tx->save_index != uart->int_tx->write_index)
+ {
+ /* save on tx buffer */
+ uart->int_tx->tx_buffer[uart->int_tx->save_index] = *ptr++;
+
+ -- size;
+
+ /* move to next position */
+ uart->int_tx->save_index ++;
+
+ /* wrap save index */
+ if (uart->int_tx->save_index >= UART_TX_BUFFER_SIZE)
+ uart->int_tx->save_index = 0;
+ }
+
+ /* set error code */
+ if (size > 0)
+ err_code = -RT_EFULL;
+ }
+ else
+ {
+ /* polling mode */
+ while (size)
+ {
+ rt_serial_putc(dev, *ptr);
+ ++ptr; --size;
+ }
+ }
+
+ /* set error code */
+ rt_set_errno(err_code);
+
+ return (rt_uint32_t)ptr - (rt_uint32_t)buffer;
+}
+
+static rt_err_t rt_serial_control (rt_device_t dev, rt_uint8_t cmd, void *args)
+{
+ struct serial_device* uart;
+
+ RT_ASSERT(dev != RT_NULL);
+
+ uart = (struct serial_device*)dev->private;
+ switch (cmd)
+ {
+ case RT_DEVICE_CTRL_SUSPEND:
+ /* suspend device */
+ dev->flag |= RT_DEVICE_FLAG_SUSPENDED;
+ break;
+
+ case RT_DEVICE_CTRL_RESUME:
+ /* resume device */
+ dev->flag &= ~RT_DEVICE_FLAG_SUSPENDED;
+ break;
+ }
+
+ return RT_EOK;
+}
+
+/*
+ * serial register
+ */
+rt_err_t rt_hw_serial_register(rt_device_t device, const char* name, rt_uint32_t flag, struct serial_device *serial)
+{
+ RT_ASSERT(device != RT_NULL);
+
+ device->type = RT_Device_Class_Char;
+ device->rx_indicate = RT_NULL;
+ device->tx_complete = RT_NULL;
+ device->init = rt_serial_init;
+ device->open = rt_serial_open;
+ device->close = rt_serial_close;
+ device->read = rt_serial_read;
+ device->write = rt_serial_write;
+ device->control = rt_serial_control;
+ device->private = serial;
+
+ /* register a character device */
+ return rt_device_register(device, name, RT_DEVICE_FLAG_RDWR | flag);
+}
+
+/* ISR for serial interrupt */
+void rt_hw_serial_isr(rt_device_t device)
+{
+ struct serial_device* uart = (struct serial_device*) device->private;
+
+ /* interrupt mode receive */
+ RT_ASSERT(device->flag & RT_DEVICE_FLAG_INT_RX);
+
+ /* save on rx buffer */
+ while (uart->uart_device->ustat & USTAT_RCV_READY)
+ {
+ rt_serial_savechar(uart, uart->uart_device->urxh & 0xff);
+ }
+
+ /* invoke callback */
+ if (device->rx_indicate != RT_NULL)
+ {
+ rt_size_t rx_length;
+
+ /* get rx length */
+ rx_length = uart->int_rx->read_index > uart->int_rx->save_index ?
+ UART_RX_BUFFER_SIZE - uart->int_rx->read_index + uart->int_rx->save_index :
+ uart->int_rx->save_index - uart->int_rx->read_index;
+
+ device->rx_indicate(device, rx_length);
+ }
+}
+
+/*@}*/
diff --git a/libcpu/arm/s3c24x0/serial.h b/libcpu/arm/s3c24x0/serial.h
new file mode 100644
index 0000000000..2869e56670
--- /dev/null
+++ b/libcpu/arm/s3c24x0/serial.h
@@ -0,0 +1,58 @@
+#ifndef __RT_HW_SERIAL_H__
+#define __RT_HW_SERIAL_H__
+
+#include <rthw.h>
+#include <rtthread.h>
+
+#include "s3c24x0.h"
+
+#define USTAT_RCV_READY 0x01 /* receive data ready */
+#define USTAT_TXB_EMPTY 0x02 /* tx buffer empty */
+#define BPS 115200 /* serial baudrate */
+
+#define UART_RX_BUFFER_SIZE 64
+#define UART_TX_BUFFER_SIZE 64
+
+struct serial_int_rx
+{
+ rt_uint8_t rx_buffer[UART_RX_BUFFER_SIZE];
+ rt_uint32_t read_index, save_index;
+};
+
+struct serial_int_tx
+{
+ rt_uint8_t tx_buffer[UART_TX_BUFFER_SIZE];
+ rt_uint32_t write_index, save_index;
+};
+
+typedef struct uartport
+{
+ rt_uint32_t ulcon;
+ rt_uint32_t ucon;
+ rt_uint32_t ufcon;
+ rt_uint32_t umcon;
+ rt_uint32_t ustat;
+ rt_uint32_t urxb;
+ rt_uint32_t ufstat;
+ rt_uint32_t umstat;
+ rt_uint32_t utxh;
+ rt_uint32_t urxh;
+ rt_uint32_t ubrd;
+}uartport;
+
+struct serial_device
+{
+ uartport* uart_device;
+
+ /* rx structure */
+ struct serial_int_rx* int_rx;
+
+ /* tx structure */
+ struct serial_int_tx* int_tx;
+};
+
+rt_err_t rt_hw_serial_register(rt_device_t device, const char* name, rt_uint32_t flag, struct serial_device *serial);
+
+void rt_hw_serial_isr(rt_device_t device);
+
+#endif
diff --git a/libcpu/arm/s3c24x0/stack.c b/libcpu/arm/s3c24x0/stack.c
new file mode 100644
index 0000000000..a284989fe8
--- /dev/null
+++ b/libcpu/arm/s3c24x0/stack.c
@@ -0,0 +1,60 @@
+/*
+ * File : stack.c
+ * This file is part of RT-Thread RTOS
+ * COPYRIGHT (C) 2006, RT-Thread Development Team
+ *
+ * The license and distribution terms for this file may be
+ * found in the file LICENSE in this distribution or at
+ * http://openlab.rt-thread.com/license/LICENSE
+ *
+ * Change Logs:
+ * Date Author Notes
+ * 2006-03-13 Bernard the first version
+ */
+#include <rtthread.h>
+#include "s3c24x0.h"
+
+/**
+ * @addtogroup S3C24X0
+ */
+/*@{*/
+
+/**
+ * This function will initialize thread stack
+ *
+ * @param tentry the entry of thread
+ * @param parameter the parameter of entry
+ * @param stack_addr the beginning stack address
+ * @param texit the function will be called when thread exit
+ *
+ * @return stack address
+ */
+rt_uint8_t *rt_hw_stack_init(void *tentry, void *parameter,
+ rt_uint8_t *stack_addr, void *texit)
+{
+ rt_uint32_t *stk;
+
+ stk = (rt_uint32_t*)stack_addr;
+ *(stk) = (rt_uint32_t)tentry; /* entry point */
+ *(--stk) = (rt_uint32_t)texit; /* lr */
+ *(--stk) = 0; /* r12 */
+ *(--stk) = 0; /* r11 */
+ *(--stk) = 0; /* r10 */
+ *(--stk) = 0; /* r9 */
+ *(--stk) = 0; /* r8 */
+ *(--stk) = 0; /* r7 */
+ *(--stk) = 0; /* r6 */
+ *(--stk) = 0; /* r5 */
+ *(--stk) = 0; /* r4 */
+ *(--stk) = 0; /* r3 */
+ *(--stk) = 0; /* r2 */
+ *(--stk) = 0; /* r1 */
+ *(--stk) = (rt_uint32_t)parameter; /* r0 : argument */
+ *(--stk) = SVCMODE; /* cpsr */
+ *(--stk) = SVCMODE; /* spsr */
+
+ /* return task's current stack address */
+ return (rt_uint8_t *)stk;
+}
+
+/*@}*/
diff --git a/libcpu/arm/s3c24x0/trap.c b/libcpu/arm/s3c24x0/trap.c
new file mode 100644
index 0000000000..0a99c54143
--- /dev/null
+++ b/libcpu/arm/s3c24x0/trap.c
@@ -0,0 +1,160 @@
+/*
+ * File : trap.c
+ * This file is part of RT-Thread RTOS
+ * COPYRIGHT (C) 2006, RT-Thread Development Team
+ *
+ * The license and distribution terms for this file may be
+ * found in the file LICENSE in this distribution or at
+ * http://openlab.rt-thread.com/license/LICENSE
+ *
+ * Change Logs:
+ * Date Author Notes
+ * 2006-03-13 Bernard first version
+ * 2006-05-27 Bernard add skyeye support
+ * 2007-11-19 Yi.Qiu fix rt_hw_trap_irq function
+ */
+
+#include <rtthread.h>
+#include <rthw.h>
+
+#include "s3c24x0.h"
+
+/**
+ * @addtogroup S3C24X0
+ */
+/*@{*/
+
+extern struct rt_thread *rt_current_thread;
+
+/**
+ * this function will show registers of CPU
+ *
+ * @param regs the registers point
+ */
+
+void rt_hw_show_register (struct rt_hw_register *regs)
+{
+ rt_kprintf("Execption:\n");
+ rt_kprintf("r00:0x%08x r01:0x%08x r02:0x%08x r03:0x%08x\n", regs->r0, regs->r1, regs->r2, regs->r3);
+ rt_kprintf("r04:0x%08x r05:0x%08x r06:0x%08x r07:0x%08x\n", regs->r4, regs->r5, regs->r6, regs->r7);
+ rt_kprintf("r08:0x%08x r09:0x%08x r10:0x%08x\n", regs->r8, regs->r9, regs->r10);
+ rt_kprintf("fp :0x%08x ip :0x%08x\n", regs->fp, regs->ip);
+ rt_kprintf("sp :0x%08x lr :0x%08x pc :0x%08x\n", regs->sp, regs->lr, regs->pc);
+ rt_kprintf("cpsr:0x%08x\n", regs->cpsr);
+}
+
+/**
+ * When ARM7TDMI comes across an instruction which it cannot handle,
+ * it takes the undefined instruction trap.
+ *
+ * @param regs system registers
+ *
+ * @note never invoke this function in application
+ */
+void rt_hw_trap_udef(struct rt_hw_register *regs)
+{
+ rt_hw_show_register(regs);
+
+ rt_kprintf("undefined instruction\n");
+ rt_kprintf("thread - %s stack:\n", rt_current_thread->name);
+ rt_hw_backtrace((rt_uint32_t *)regs->fp, (rt_uint32_t)rt_current_thread->entry);
+
+ rt_hw_cpu_shutdown();
+}
+
+/**
+ * The software interrupt instruction (SWI) is used for entering
+ * Supervisor mode, usually to request a particular supervisor
+ * function.
+ *
+ * @param regs system registers
+ *
+ * @note never invoke this function in application
+ */
+void rt_hw_trap_swi(struct rt_hw_register *regs)
+{
+ rt_hw_show_register(regs);
+
+ rt_kprintf("software interrupt\n");
+ rt_hw_cpu_shutdown();
+}
+
+/**
+ * An abort indicates that the current memory access cannot be completed,
+ * which occurs during an instruction prefetch.
+ *
+ * @param regs system registers
+ *
+ * @note never invoke this function in application
+ */
+void rt_hw_trap_pabt(struct rt_hw_register *regs)
+{
+ rt_hw_show_register(regs);
+
+ rt_kprintf("prefetch abort\n");
+ rt_kprintf("thread - %s stack:\n", rt_current_thread->name);
+ rt_hw_backtrace((rt_uint32_t *)regs->fp, (rt_uint32_t)rt_current_thread->entry);
+
+ rt_hw_cpu_shutdown();
+}
+
+/**
+ * An abort indicates that the current memory access cannot be completed,
+ * which occurs during a data access.
+ *
+ * @param regs system registers
+ *
+ * @note never invoke this function in application
+ */
+void rt_hw_trap_dabt(struct rt_hw_register *regs)
+{
+ rt_hw_show_register(regs);
+
+ rt_kprintf("data abort\n");
+ rt_kprintf("thread - %s stack:\n", rt_current_thread->name);
+ rt_hw_backtrace((rt_uint32_t *)regs->fp, (rt_uint32_t)rt_current_thread->entry);
+
+ rt_hw_cpu_shutdown();
+}
+
+/**
+ * Normally, system will never reach here
+ *
+ * @param regs system registers
+ *
+ * @note never invoke this function in application
+ */
+void rt_hw_trap_resv(struct rt_hw_register *regs)
+{
+ rt_kprintf("not used\n");
+ rt_hw_show_register(regs);
+ rt_hw_cpu_shutdown();
+}
+
+extern rt_isr_handler_t isr_table[];
+
+void rt_hw_trap_irq()
+{
+ unsigned long intstat;
+ rt_isr_handler_t isr_func;
+
+ intstat = INTOFFSET;
+
+ if (intstat == INTGLOBAL) return;
+
+ /* get interrupt service routine */
+ isr_func = isr_table[intstat];
+
+ /* turn to interrupt service routine */
+ isr_func(intstat);
+
+ /* clear pending register */
+ ClearPending(1 << intstat);
+}
+
+void rt_hw_trap_fiq()
+{
+ rt_kprintf("fast interrupt request\n");
+}
+
+/*@}*/
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