Merge branch 'master' into gitee_master

10 files changed, 38 insertions, 31 deletions

diff --git a/libcpu/arm/cortex-a/gic.c b/libcpu/arm/cortex-a/gic.c
index 2a46142b54..2e94b88277 100644
--- a/libcpu/arm/cortex-a/gic.c
+++ b/libcpu/arm/cortex-a/gic.c
@@ -74,9 +74,8 @@ void arm_gic_ack(rt_uint32_t index, int irq)
     irq = irq - _gic_table[index].offset;
     RT_ASSERT(irq >= 0);
 
-    GIC_DIST_ENABLE_CLEAR(_gic_table[index].dist_hw_base, irq) = mask;
+    GIC_DIST_PENDING_CLEAR(_gic_table[index].dist_hw_base, irq) = mask;
     GIC_CPU_EOI(_gic_table[index].cpu_hw_base) = irq;
-    GIC_DIST_ENABLE_SET(_gic_table[index].dist_hw_base, irq) = mask;
 }
 
 void arm_gic_mask(rt_uint32_t index, int irq)
diff --git a/libcpu/arm/cortex-m23/context_gcc.S b/libcpu/arm/cortex-m23/context_gcc.S
index 067348181d..48f90413d9 100644
--- a/libcpu/arm/cortex-m23/context_gcc.S
+++ b/libcpu/arm/cortex-m23/context_gcc.S
@@ -137,7 +137,7 @@ pendsv_exit:
     /* restore interrupt */
     MSR     PRIMASK, R2
 
-    MOVS    R0, #0x04
+    MOVS    R0, #0x03
     RSBS    R0, R0, #0x00
     BX      R0
 /*
diff --git a/libcpu/arm/cortex-m23/context_iar.S b/libcpu/arm/cortex-m23/context_iar.S
index 4d50d0fdec..c7d85cc5e2 100644
--- a/libcpu/arm/cortex-m23/context_iar.S
+++ b/libcpu/arm/cortex-m23/context_iar.S
@@ -139,7 +139,7 @@ pendsv_exit
     ; restore interrupt
     MSR     PRIMASK, r2
 
-    MOVS    r0, #0x04
+    MOVS    r0, #0x03
     RSBS    r0, r0, #0x00
     BX      r0
 
diff --git a/libcpu/arm/cortex-m23/context_rvds.S b/libcpu/arm/cortex-m23/context_rvds.S
index 4486ceaf08..ca381d0f8f 100644
--- a/libcpu/arm/cortex-m23/context_rvds.S
+++ b/libcpu/arm/cortex-m23/context_rvds.S
@@ -143,7 +143,7 @@ pendsv_exit
     ; restore interrupt
     MSR     PRIMASK, r2
 
-    MOVS    r0, #0x04
+    MOVS    r0, #0x03
     RSBS    r0, r0, #0x00
     BX      r0
     ENDP
diff --git a/libcpu/arm/cortex-m3/cpuport.c b/libcpu/arm/cortex-m3/cpuport.c
index d17d4fdf2e..d58782e2c5 100644
--- a/libcpu/arm/cortex-m3/cpuport.c
+++ b/libcpu/arm/cortex-m3/cpuport.c
@@ -388,13 +388,13 @@ int __rt_ffs(int value)
 {
     __asm volatile(
         "CMP     r0, #0x00            \n"
-        "BEQ     exit                 \n"
+        "BEQ     1f                   \n"
 
         "RBIT    r0, r0               \n"
         "CLZ     r0, r0               \n"
         "ADDS    r0, r0, #0x01        \n"
 
-        "exit:                        \n"
+        "1:                           \n"
 
         : "=r"(value)
         : "r"(value)
diff --git a/libcpu/arm/cortex-m33/cpuport.c b/libcpu/arm/cortex-m33/cpuport.c
index 415f560911..a589ba3462 100644
--- a/libcpu/arm/cortex-m33/cpuport.c
+++ b/libcpu/arm/cortex-m33/cpuport.c
@@ -475,13 +475,13 @@ int __rt_ffs(int value)
 {
     __asm volatile(
         "CMP     r0, #0x00            \n"
-        "BEQ     exit                 \n"
+        "BEQ     1f                   \n"
 
         "RBIT    r0, r0               \n"
         "CLZ     r0, r0               \n"
         "ADDS    r0, r0, #0x01        \n"
 
-        "exit:                        \n"
+        "1:                           \n"
         "BX      lr                   \n"
 
         : "=r"(value)
diff --git a/libcpu/arm/cortex-m4/cpuport.c b/libcpu/arm/cortex-m4/cpuport.c
index f556ba0c26..dc8a9aab59 100644
--- a/libcpu/arm/cortex-m4/cpuport.c
+++ b/libcpu/arm/cortex-m4/cpuport.c
@@ -472,13 +472,13 @@ int __rt_ffs(int value)
 {
     __asm volatile(
         "CMP     r0, #0x00            \n"
-        "BEQ     exit                 \n"
+        "BEQ     1f                   \n"
 
         "RBIT    r0, r0               \n"
         "CLZ     r0, r0               \n"
         "ADDS    r0, r0, #0x01        \n"
 
-        "exit:                        \n"
+        "1:                           \n"
 
         : "=r"(value)
         : "r"(value)
diff --git a/libcpu/arm/cortex-m7/cpuport.c b/libcpu/arm/cortex-m7/cpuport.c
index c22242f140..e701a52307 100644
--- a/libcpu/arm/cortex-m7/cpuport.c
+++ b/libcpu/arm/cortex-m7/cpuport.c
@@ -472,13 +472,13 @@ int __rt_ffs(int value)
 {
     __asm volatile(
         "CMP     r0, #0x00            \n"
-        "BEQ     exit                 \n"
+        "BEQ     1f                   \n"
 
         "RBIT    r0, r0               \n"
         "CLZ     r0, r0               \n"
         "ADDS    r0, r0, #0x01        \n"
 
-        "exit:                        \n"
+        "1:                           \n"
 
         : "=r"(value)
         : "r"(value)
diff --git a/libcpu/arm/zynq7000/gic.c b/libcpu/arm/zynq7000/gic.c
index e23a359e6e..76404d4c46 100644
--- a/libcpu/arm/zynq7000/gic.c
+++ b/libcpu/arm/zynq7000/gic.c
@@ -37,7 +37,7 @@ static struct arm_gic _gic_table[ARM_GIC_MAX_NR];
 #define GIC_DIST_ENABLE_SET(hw_base, n)     __REG32((hw_base) + 0x100 + (n/32) * 4)
 #define GIC_DIST_ENABLE_CLEAR(hw_base, n)   __REG32((hw_base) + 0x180 + (n/32) * 4)
 #define GIC_DIST_PENDING_SET(hw_base, n)    __REG32((hw_base) + 0x200)
-#define GIC_DIST_PENDING_CLEAR(hw_base, n)  __REG32((hw_base) + 0x280)
+#define GIC_DIST_PENDING_CLEAR(hw_base, n)  __REG32((hw_base) + 0x280 + (n/32) * 4)
 #define GIC_DIST_ACTIVE_BIT(hw_base)        __REG32((hw_base) + 0x300)
 #define GIC_DIST_PRI(hw_base, n)            __REG32((hw_base) + 0x400 +  (n/4) * 4)
 #define GIC_DIST_TARGET(hw_base, n)         __REG32((hw_base) + 0x800 +  (n/4) * 4)
@@ -68,9 +68,8 @@ void arm_gic_ack(rt_uint32_t index, int irq)
     irq = irq - _gic_table[index].offset;
     RT_ASSERT(irq >= 0);
 
-    GIC_DIST_ENABLE_CLEAR(_gic_table[index].dist_hw_base, irq) = mask;
+    GIC_DIST_PENDING_CLEAR(_gic_table[index].dist_hw_base, irq) = mask;
     GIC_CPU_EOI(_gic_table[index].cpu_hw_base) = irq;
-    GIC_DIST_ENABLE_SET(_gic_table[index].dist_hw_base, irq) = mask;
 }
 
 void arm_gic_mask(rt_uint32_t index, int irq)
diff --git a/libcpu/mips/common/exception.c b/libcpu/mips/common/exception.c
index cd7d97e6c0..84bb0446d6 100644
--- a/libcpu/mips/common/exception.c
+++ b/libcpu/mips/common/exception.c
@@ -39,7 +39,7 @@ void rt_hw_interrupt_enable(rt_base_t level)
 /**
  * exception handle table
  */
-#define RT_EXCEPTION_MAX	31
+#define RT_EXCEPTION_MAX 31
 exception_func_t sys_exception_handlers[RT_EXCEPTION_MAX];
 
 /**
@@ -59,10 +59,13 @@ exception_func_t rt_set_except_vector(int n, exception_func_t func)
     return old_handler;
 }
 
-void mips_dump_regs(struct pt_regs *regs) {
+void mips_dump_regs(struct pt_regs *regs)
+{
     int i, j;
-    for(i = 0; i < 32 / 4; i++) {
-        for(j = 0; j < 4; j++) {
+    for (i = 0; i < 32 / 4; i++)
+    {
+        for (j = 0; j < 4; j++)
+        {
             int reg = 4 * i + j;
             rt_kprintf("%d: 0x%08x, ", reg, regs->regs[reg]);
         }
@@ -84,9 +87,10 @@ void cache_error_handler(void)
 
 static void unhandled_exception_handle(struct pt_regs *regs)
 {
-    rt_kprintf("Unknown Exception, EPC: 0x%08x, CAUSE: 0x%08x\n", read_c0_epc(), read_c0_cause());
-    rt_kprintf("ST0: 0x%08x ",regs->cp0_status);
-    rt_kprintf("ErrorPC: 0x%08x\n",read_c0_errorepc());
+    rt_kprintf("Unknown Exception, EPC: 0x%08x, CAUSE: 0x%08x\n", read_c0_epc(),
+               read_c0_cause());
+    rt_kprintf("ST0: 0x%08x ", regs->cp0_status);
+    rt_kprintf("ErrorPC: 0x%08x\n", read_c0_errorepc());
     mips_dump_regs(regs);
     rt_hw_cpu_shutdown();
 }
@@ -95,8 +99,9 @@ static void install_default_exception_handler(void)
 {
     rt_int32_t i;
 
-    for (i=0; i<RT_EXCEPTION_MAX; i++)
-        sys_exception_handlers[i] = (exception_func_t)unhandled_exception_handle;
+    for (i = 0; i < RT_EXCEPTION_MAX; i++)
+        sys_exception_handlers[i] =
+                (exception_func_t)unhandled_exception_handle;
 }
 
 int rt_hw_exception_init(void)
@@ -117,14 +122,16 @@ int rt_hw_exception_init(void)
 
 void rt_general_exc_dispatch(struct pt_regs *regs)
 {
-    rt_ubase_t exccode = 0;
+    rt_ubase_t cause, exccode;
+    cause = read_c0_cause();
+    exccode = (cause & CAUSEF_EXCCODE) >> CAUSEB_EXCCODE;    
 
-
-    if (exccode == 0) {
+    if (exccode == 0)
+    {
         rt_ubase_t status, pending;
-        status = read_c0_status();
 
-        pending =  (CAUSEF_IP) & (status & ST0_IM);
+        status = read_c0_status();
+        pending = (cause & CAUSEF_IP) & (status & ST0_IM);
         if (pending & CAUSEF_IP0)
             rt_do_mips_cpu_irq(0);
         if (pending & CAUSEF_IP1)
@@ -141,7 +148,9 @@ void rt_general_exc_dispatch(struct pt_regs *regs)
             rt_do_mips_cpu_irq(6);
         if (pending & CAUSEF_IP7)
             rt_do_mips_cpu_irq(7);
-    } else {
+    }
+    else
+    {
         if (sys_exception_handlers[exccode])
             sys_exception_handlers[exccode](regs);
     }