diff options
| author | Bernard Xiong <[email protected]> | 2013-01-08 05:05:02 -0800 |
|---|---|---|
| committer | Bernard Xiong <[email protected]> | 2013-01-08 05:05:02 -0800 |
| commit | 72782e920325808bbc58fc2344fc52033479b627 (patch) | |
| tree | 45badbfa9818b8d1722463949beba0f88d1cbd9f /libcpu | |
| parent | b3cf278502e605fa03861a2da5685b4c8d72879e (diff) | |
convert end of line
Diffstat (limited to 'libcpu')
146 files changed, 26874 insertions, 26874 deletions
diff --git a/libcpu/arm/AT91SAM7S/AT91SAM7S.h b/libcpu/arm/AT91SAM7S/AT91SAM7S.h index 3f0fef7097..0c8d652c19 100644 --- a/libcpu/arm/AT91SAM7S/AT91SAM7S.h +++ b/libcpu/arm/AT91SAM7S/AT91SAM7S.h @@ -57,11 +57,11 @@ extern "C" { #define AT91C_TC2_IER (AT91_REG(0xFFFA00A4)) /* TC2 Interrupt Enable Register */ #define AT91C_TC2_SR (AT91_REG(0xFFFA00A0)) /* TC2 Status Register */ -/* ========== Register definition for PITC peripheral ========== */
-#define AT91C_PITC_PIVR (AT91_REG(0xFFFFFD38)) /* PITC Period Interval Value Register */
-#define AT91C_PITC_PISR (AT91_REG(0xFFFFFD34)) /* PITC Period Interval Status Register */
-#define AT91C_PITC_PIIR (AT91_REG(0xFFFFFD3C)) /* PITC Period Interval Image Register */
-#define AT91C_PITC_PIMR (AT91_REG(0xFFFFFD30)) /* PITC Period Interval Mode Register */
+/* ========== Register definition for PITC peripheral ========== */ +#define AT91C_PITC_PIVR (AT91_REG(0xFFFFFD38)) /* PITC Period Interval Value Register */ +#define AT91C_PITC_PISR (AT91_REG(0xFFFFFD34)) /* PITC Period Interval Status Register */ +#define AT91C_PITC_PIIR (AT91_REG(0xFFFFFD3C)) /* PITC Period Interval Image Register */ +#define AT91C_PITC_PIMR (AT91_REG(0xFFFFFD30)) /* PITC Period Interval Mode Register */ /* ========== Register definition for UDP peripheral ========== */ #define AT91C_UDP_NUM (AT91_REG(0xFFFB0000)) /* UDP Frame Number Register */ @@ -241,42 +241,42 @@ extern "C" { #define AT91C_PMC_SR (AT91_REG(0xFFFFFC68)) /* PMC Status Register */ #define AT91C_PMC_IMR (AT91_REG(0xFFFFFC6C)) /* PMC Interrupt Mask Register */ -/******************************************************************************/
-/* PERIPHERAL ID DEFINITIONS FOR AT91SAM7S64 */
-/******************************************************************************/
-#define AT91C_ID_FIQ 0 /* Advanced Interrupt Controller (FIQ) */
-#define AT91C_ID_SYS 1 /* System Peripheral */
-#define AT91C_ID_PIOA 2 /* Parallel IO Controller A */
+/******************************************************************************/ +/* PERIPHERAL ID DEFINITIONS FOR AT91SAM7S64 */ +/******************************************************************************/ +#define AT91C_ID_FIQ 0 /* Advanced Interrupt Controller (FIQ) */ +#define AT91C_ID_SYS 1 /* System Peripheral */ +#define AT91C_ID_PIOA 2 /* Parallel IO Controller A */ #define AT91C_ID_PIOB 3 /* Parallel IO Controller B */ -#define AT91C_ID_ADC 4 /* Analog-to-Digital Converter */
-#define AT91C_ID_SPI 5 /* Serial Peripheral Interface */
-#define AT91C_ID_US0 6 /* USART 0 */
-#define AT91C_ID_US1 7 /* USART 1 */
-#define AT91C_ID_SSC 8 /* Serial Synchronous Controller */
-#define AT91C_ID_TWI 9 /* Two-Wire Interface */
-#define AT91C_ID_PWMC 10 /* PWM Controller */
-#define AT91C_ID_UDP 11 /* USB Device Port */
-#define AT91C_ID_TC0 12 /* Timer Counter 0 */
-#define AT91C_ID_TC1 13 /* Timer Counter 1 */
-#define AT91C_ID_TC2 14 /* Timer Counter 2 */
-#define AT91C_ID_15 15 /* Reserved */
-#define AT91C_ID_16 16 /* Reserved */
-#define AT91C_ID_17 17 /* Reserved */
-#define AT91C_ID_18 18 /* Reserved */
-#define AT91C_ID_19 19 /* Reserved */
-#define AT91C_ID_20 20 /* Reserved */
-#define AT91C_ID_21 21 /* Reserved */
-#define AT91C_ID_22 22 /* Reserved */
-#define AT91C_ID_23 23 /* Reserved */
-#define AT91C_ID_24 24 /* Reserved */
-#define AT91C_ID_25 25 /* Reserved */
-#define AT91C_ID_26 26 /* Reserved */
-#define AT91C_ID_27 27 /* Reserved */
-#define AT91C_ID_28 28 /* Reserved */
-#define AT91C_ID_29 29 /* Reserved */
-#define AT91C_ID_IRQ0 30 /* Advanced Interrupt Controller (IRQ0) */
-#define AT91C_ID_IRQ1 31 /* Advanced Interrupt Controller (IRQ1) */
-#define AT91C_ALL_INT 0xC0007FF7 /* ALL VALID INTERRUPTS */
+#define AT91C_ID_ADC 4 /* Analog-to-Digital Converter */ +#define AT91C_ID_SPI 5 /* Serial Peripheral Interface */ +#define AT91C_ID_US0 6 /* USART 0 */ +#define AT91C_ID_US1 7 /* USART 1 */ +#define AT91C_ID_SSC 8 /* Serial Synchronous Controller */ +#define AT91C_ID_TWI 9 /* Two-Wire Interface */ +#define AT91C_ID_PWMC 10 /* PWM Controller */ +#define AT91C_ID_UDP 11 /* USB Device Port */ +#define AT91C_ID_TC0 12 /* Timer Counter 0 */ +#define AT91C_ID_TC1 13 /* Timer Counter 1 */ +#define AT91C_ID_TC2 14 /* Timer Counter 2 */ +#define AT91C_ID_15 15 /* Reserved */ +#define AT91C_ID_16 16 /* Reserved */ +#define AT91C_ID_17 17 /* Reserved */ +#define AT91C_ID_18 18 /* Reserved */ +#define AT91C_ID_19 19 /* Reserved */ +#define AT91C_ID_20 20 /* Reserved */ +#define AT91C_ID_21 21 /* Reserved */ +#define AT91C_ID_22 22 /* Reserved */ +#define AT91C_ID_23 23 /* Reserved */ +#define AT91C_ID_24 24 /* Reserved */ +#define AT91C_ID_25 25 /* Reserved */ +#define AT91C_ID_26 26 /* Reserved */ +#define AT91C_ID_27 27 /* Reserved */ +#define AT91C_ID_28 28 /* Reserved */ +#define AT91C_ID_29 29 /* Reserved */ +#define AT91C_ID_IRQ0 30 /* Advanced Interrupt Controller (IRQ0) */ +#define AT91C_ID_IRQ1 31 /* Advanced Interrupt Controller (IRQ1) */ +#define AT91C_ALL_INT 0xC0007FF7 /* ALL VALID INTERRUPTS */ /*****************************/ /* CPU Mode */ diff --git a/libcpu/arm/AT91SAM7S/context_rvds.S b/libcpu/arm/AT91SAM7S/context_rvds.S index e24fa62a3d..641ec7a6b1 100644 --- a/libcpu/arm/AT91SAM7S/context_rvds.S +++ b/libcpu/arm/AT91SAM7S/context_rvds.S @@ -12,12 +12,12 @@ ; * 2009-01-20 Bernard first version ; */ -NOINT EQU 0xc0 ; disable interrupt in psr
+NOINT EQU 0xc0 ; disable interrupt in psr - AREA |.text|, CODE, READONLY, ALIGN=2
- ARM
- REQUIRE8
- PRESERVE8
+ AREA |.text|, CODE, READONLY, ALIGN=2 + ARM + REQUIRE8 + PRESERVE8 ;/* ; * rt_base_t rt_hw_interrupt_disable(); @@ -26,16 +26,16 @@ rt_hw_interrupt_disable PROC EXPORT rt_hw_interrupt_disable MRS r0, cpsr ORR r1, r0, #NOINT - MSR cpsr_c, r1
+ MSR cpsr_c, r1 BX lr - ENDP
+ ENDP ;/* ; * void rt_hw_interrupt_enable(rt_base_t level); ; */ rt_hw_interrupt_enable PROC EXPORT rt_hw_interrupt_enable - MSR cpsr_c, r0
+ MSR cpsr_c, r0 BX lr ENDP @@ -63,7 +63,7 @@ rt_hw_context_switch PROC MSR cpsr_cxsf, r4 LDMFD sp!, {r0-r12, lr, pc} ; pop new task r0-r12, lr & pc - ENDP
+ ENDP ;/* ; * void rt_hw_context_switch_to(rt_uint32 to); @@ -79,14 +79,14 @@ rt_hw_context_switch_to PROC MSR cpsr_cxsf, r4 LDMFD sp!, {r0-r12, lr, pc} ; pop new task r0-r12, lr & pc - ENDP
+ ENDP ;/* ; * void rt_hw_context_switch_interrupt(rt_uint32 from, rt_uint32 to); ; */ IMPORT rt_thread_switch_interrupt_flag IMPORT rt_interrupt_from_thread - IMPORT rt_interrupt_to_thread
+ IMPORT rt_interrupt_to_thread rt_hw_context_switch_interrupt PROC EXPORT rt_hw_context_switch_interrupt @@ -100,8 +100,8 @@ rt_hw_context_switch_interrupt PROC STR r0, [r2] _reswitch LDR r2, =rt_interrupt_to_thread ; set rt_interrupt_to_thread - STR r1, [r2]
+ STR r1, [r2] BX lr - ENDP
-
+ ENDP + END
\ No newline at end of file diff --git a/libcpu/arm/AT91SAM7S/interrupt.c b/libcpu/arm/AT91SAM7S/interrupt.c index cd80a5d408..fd84a72ea3 100644 --- a/libcpu/arm/AT91SAM7S/interrupt.c +++ b/libcpu/arm/AT91SAM7S/interrupt.c @@ -56,11 +56,11 @@ void rt_hw_interrupt_init() * @param vector the interrupt number */ void rt_hw_interrupt_mask(int vector) -{
+{ /* disable interrupt */ - AT91C_AIC_IDCR = 1 << vector;
-
- /* clear interrupt */
+ AT91C_AIC_IDCR = 1 << vector; + + /* clear interrupt */ AT91C_AIC_ICCR = 1 << vector; } diff --git a/libcpu/arm/AT91SAM7S/serial.c b/libcpu/arm/AT91SAM7S/serial.c index c939de88b4..77a7bd8608 100644 --- a/libcpu/arm/AT91SAM7S/serial.c +++ b/libcpu/arm/AT91SAM7S/serial.c @@ -9,7 +9,7 @@ * * Change Logs: * Date Author Notes - * 2006-08-23 Bernard first version
+ * 2006-08-23 Bernard first version * 2009-05-14 Bernard add RT-THread device interface */ @@ -17,142 +17,142 @@ #include <rtthread.h> #include "AT91SAM7S.h" -#include "serial.h"
+#include "serial.h" /** * @addtogroup AT91SAM7 */ -/*@{*/
-typedef volatile rt_uint32_t REG32;
-struct rt_at91serial_hw
-{
- REG32 US_CR; // Control Register
- REG32 US_MR; // Mode Register
- REG32 US_IER; // Interrupt Enable Register
- REG32 US_IDR; // Interrupt Disable Register
- REG32 US_IMR; // Interrupt Mask Register
- REG32 US_CSR; // Channel Status Register
- REG32 US_RHR; // Receiver Holding Register
- REG32 US_THR; // Transmitter Holding Register
- REG32 US_BRGR; // Baud Rate Generator Register
- REG32 US_RTOR; // Receiver Time-out Register
- REG32 US_TTGR; // Transmitter Time-guard Register
- REG32 Reserved0[5]; //
- REG32 US_FIDI; // FI_DI_Ratio Register
- REG32 US_NER; // Nb Errors Register
- REG32 Reserved1[1]; //
- REG32 US_IF; // IRDA_FILTER Register
- REG32 Reserved2[44]; //
- REG32 US_RPR; // Receive Pointer Register
- REG32 US_RCR; // Receive Counter Register
- REG32 US_TPR; // Transmit Pointer Register
- REG32 US_TCR; // Transmit Counter Register
- REG32 US_RNPR; // Receive Next Pointer Register
- REG32 US_RNCR; // Receive Next Counter Register
- REG32 US_TNPR; // Transmit Next Pointer Register
- REG32 US_TNCR; // Transmit Next Counter Register
- REG32 US_PTCR; // PDC Transfer Control Register
- REG32 US_PTSR; // PDC Transfer Status Register
-};
-
-struct rt_at91serial
-{
- struct rt_device parent;
-
- struct rt_at91serial_hw* hw_base;
- rt_uint16_t peripheral_id;
- rt_uint32_t baudrate;
-
- /* reception field */
- rt_uint16_t save_index, read_index;
- rt_uint8_t rx_buffer[RT_UART_RX_BUFFER_SIZE];
-};
-#ifdef RT_USING_UART1
-struct rt_at91serial serial1;
-#endif
-#ifdef RT_USING_UART2
-struct rt_at91serial serial2;
-#endif
-
-static void rt_hw_serial_isr(int irqno)
-{
- rt_base_t level;
- struct rt_device* device;
- struct rt_at91serial* serial = RT_NULL;
-
- if (irqno == AT91C_ID_US0)
- {
-#ifdef RT_USING_UART1
- /* serial 1 */
- serial = &serial1;
-#endif
- }
- else if (irqno == AT91C_ID_US1)
- {
-#ifdef RT_USING_UART2
- /* serial 2 */
- serial = &serial2;
-#endif
- }
- RT_ASSERT(serial != RT_NULL);
-
- /* get generic device object */
- device = (rt_device_t)serial;
-
- /* disable interrupt */
- level = rt_hw_interrupt_disable();
-
- /* get received character */
- serial->rx_buffer[serial->save_index] = serial->hw_base->US_RHR;
-
- /* move to next position */
- serial->save_index ++;
- if (serial->save_index >= RT_UART_RX_BUFFER_SIZE)
- serial->save_index = 0;
-
- /* if the next position is read index, discard this 'read char' */
- if (serial->save_index == serial->read_index)
- {
- serial->read_index ++;
- if (serial->read_index >= RT_UART_RX_BUFFER_SIZE)
- serial->read_index = 0;
- }
-
- /* enable interrupt */
- rt_hw_interrupt_enable(level);
-
- /* indicate to upper layer application */
- if (device->rx_indicate != RT_NULL)
- device->rx_indicate(device, 1);
-
- /* ack interrupt */
- AT91C_AIC_EOICR = 1;
-}
-
-static rt_err_t rt_serial_init (rt_device_t dev)
-{
- rt_uint32_t bd;
- struct rt_at91serial* serial = (struct rt_at91serial*) dev;
-
- RT_ASSERT(serial != RT_NULL);
- /* must be US0 or US1 */
- RT_ASSERT(((serial->peripheral_id == AT91C_ID_US0) ||
- (serial->peripheral_id == AT91C_ID_US1)));
-
- /* Enable Clock for USART */
- AT91C_PMC_PCER = 1 << serial->peripheral_id;
+/*@{*/ +typedef volatile rt_uint32_t REG32; +struct rt_at91serial_hw +{ + REG32 US_CR; // Control Register + REG32 US_MR; // Mode Register + REG32 US_IER; // Interrupt Enable Register + REG32 US_IDR; // Interrupt Disable Register + REG32 US_IMR; // Interrupt Mask Register + REG32 US_CSR; // Channel Status Register + REG32 US_RHR; // Receiver Holding Register + REG32 US_THR; // Transmitter Holding Register + REG32 US_BRGR; // Baud Rate Generator Register + REG32 US_RTOR; // Receiver Time-out Register + REG32 US_TTGR; // Transmitter Time-guard Register + REG32 Reserved0[5]; // + REG32 US_FIDI; // FI_DI_Ratio Register + REG32 US_NER; // Nb Errors Register + REG32 Reserved1[1]; // + REG32 US_IF; // IRDA_FILTER Register + REG32 Reserved2[44]; // + REG32 US_RPR; // Receive Pointer Register + REG32 US_RCR; // Receive Counter Register + REG32 US_TPR; // Transmit Pointer Register + REG32 US_TCR; // Transmit Counter Register + REG32 US_RNPR; // Receive Next Pointer Register + REG32 US_RNCR; // Receive Next Counter Register + REG32 US_TNPR; // Transmit Next Pointer Register + REG32 US_TNCR; // Transmit Next Counter Register + REG32 US_PTCR; // PDC Transfer Control Register + REG32 US_PTSR; // PDC Transfer Status Register +}; + +struct rt_at91serial +{ + struct rt_device parent; + + struct rt_at91serial_hw* hw_base; + rt_uint16_t peripheral_id; + rt_uint32_t baudrate; + + /* reception field */ + rt_uint16_t save_index, read_index; + rt_uint8_t rx_buffer[RT_UART_RX_BUFFER_SIZE]; +}; +#ifdef RT_USING_UART1 +struct rt_at91serial serial1; +#endif +#ifdef RT_USING_UART2 +struct rt_at91serial serial2; +#endif + +static void rt_hw_serial_isr(int irqno) +{ + rt_base_t level; + struct rt_device* device; + struct rt_at91serial* serial = RT_NULL; + + if (irqno == AT91C_ID_US0) + { +#ifdef RT_USING_UART1 + /* serial 1 */ + serial = &serial1; +#endif + } + else if (irqno == AT91C_ID_US1) + { +#ifdef RT_USING_UART2 + /* serial 2 */ + serial = &serial2; +#endif + } + RT_ASSERT(serial != RT_NULL); + + /* get generic device object */ + device = (rt_device_t)serial; + + /* disable interrupt */ + level = rt_hw_interrupt_disable(); + + /* get received character */ + serial->rx_buffer[serial->save_index] = serial->hw_base->US_RHR; + + /* move to next position */ + serial->save_index ++; + if (serial->save_index >= RT_UART_RX_BUFFER_SIZE) + serial->save_index = 0; + + /* if the next position is read index, discard this 'read char' */ + if (serial->save_index == serial->read_index) + { + serial->read_index ++; + if (serial->read_index >= RT_UART_RX_BUFFER_SIZE) + serial->read_index = 0; + } + + /* enable interrupt */ + rt_hw_interrupt_enable(level); + + /* indicate to upper layer application */ + if (device->rx_indicate != RT_NULL) + device->rx_indicate(device, 1); + + /* ack interrupt */ + AT91C_AIC_EOICR = 1; +} + +static rt_err_t rt_serial_init (rt_device_t dev) +{ + rt_uint32_t bd; + struct rt_at91serial* serial = (struct rt_at91serial*) dev; + + RT_ASSERT(serial != RT_NULL); + /* must be US0 or US1 */ + RT_ASSERT(((serial->peripheral_id == AT91C_ID_US0) || + (serial->peripheral_id == AT91C_ID_US1))); + + /* Enable Clock for USART */ + AT91C_PMC_PCER = 1 << serial->peripheral_id; /* Enable RxD0 and TxDO Pin */ - if (serial->peripheral_id == AT91C_ID_US0)
- {
+ if (serial->peripheral_id == AT91C_ID_US0) + { /* set pinmux */ - AT91C_PIO_PDR = (1 << 5) | (1 << 6);
- }
- else if (serial->peripheral_id == AT91C_ID_US1)
- {
+ AT91C_PIO_PDR = (1 << 5) | (1 << 6); + } + else if (serial->peripheral_id == AT91C_ID_US1) + { /* set pinmux */ - AT91C_PIO_PDR = (1 << 21) | (1 << 22);
- }
+ AT91C_PIO_PDR = (1 << 21) | (1 << 22); + } serial->hw_base->US_CR = AT91C_US_RSTRX | /* Reset Receiver */ AT91C_US_RSTTX | /* Reset Transmitter */ @@ -165,143 +165,143 @@ static rt_err_t rt_serial_init (rt_device_t dev) AT91C_US_PAR_NONE | /* No Parity */ AT91C_US_NBSTOP_1_BIT; /* 1 Stop Bit */ - /* set baud rate divisor */
- bd = ((MCK*10)/(serial->baudrate * 16));
- if ((bd % 10) >= 5) bd = (bd / 10) + 1;
- else bd /= 10;
-
- serial->hw_base->US_BRGR = bd;
+ /* set baud rate divisor */ + bd = ((MCK*10)/(serial->baudrate * 16)); + if ((bd % 10) >= 5) bd = (bd / 10) + 1; + else bd /= 10; + + serial->hw_base->US_BRGR = bd; serial->hw_base->US_CR = AT91C_US_RXEN | /* Receiver Enable */ - AT91C_US_TXEN; /* Transmitter Enable */
-
- /* reset rx index */
- serial->save_index = 0;
- serial->read_index = 0;
-
- /* reset rx buffer */
- rt_memset(serial->rx_buffer, 0, RT_UART_RX_BUFFER_SIZE);
-
- return RT_EOK;
-}
-
-static rt_err_t rt_serial_open(rt_device_t dev, rt_uint16_t oflag)
-{
- struct rt_at91serial *serial = (struct rt_at91serial*)dev;
- RT_ASSERT(serial != RT_NULL);
+ AT91C_US_TXEN; /* Transmitter Enable */ + + /* reset rx index */ + serial->save_index = 0; + serial->read_index = 0; + + /* reset rx buffer */ + rt_memset(serial->rx_buffer, 0, RT_UART_RX_BUFFER_SIZE); + + return RT_EOK; +} - if (dev->flag & RT_DEVICE_FLAG_INT_RX)
- {
- /* enable UART rx interrupt */
- serial->hw_base->US_IER = 1 << 0; /* RxReady interrupt */
- serial->hw_base->US_IMR |= 1 << 0; /* umask RxReady interrupt */
-
- /* install UART handler */
- rt_hw_interrupt_install(serial->peripheral_id, rt_hw_serial_isr, RT_NULL);
- AT91C_AIC_SMR(serial->peripheral_id) = 5 | (0x01 << 5);
- rt_hw_interrupt_umask(serial->peripheral_id);
- }
-
- return RT_EOK;
-}
-
-static rt_err_t rt_serial_close(rt_device_t dev)
-{
- struct rt_at91serial *serial = (struct rt_at91serial*)dev;
- RT_ASSERT(serial != RT_NULL);
-
- if (dev->flag & RT_DEVICE_FLAG_INT_RX)
- {
- /* disable interrupt */
- serial->hw_base->US_IDR = 1 << 0; /* RxReady interrupt */
- serial->hw_base->US_IMR &= ~(1 << 0); /* mask RxReady interrupt */
- }
+static rt_err_t rt_serial_open(rt_device_t dev, rt_uint16_t oflag) +{ + struct rt_at91serial *serial = (struct rt_at91serial*)dev; + RT_ASSERT(serial != RT_NULL); + + if (dev->flag & RT_DEVICE_FLAG_INT_RX) + { + /* enable UART rx interrupt */ + serial->hw_base->US_IER = 1 << 0; /* RxReady interrupt */ + serial->hw_base->US_IMR |= 1 << 0; /* umask RxReady interrupt */ + + /* install UART handler */ + rt_hw_interrupt_install(serial->peripheral_id, rt_hw_serial_isr, RT_NULL); + AT91C_AIC_SMR(serial->peripheral_id) = 5 | (0x01 << 5); + rt_hw_interrupt_umask(serial->peripheral_id); + } return RT_EOK; -}
-
-static rt_size_t rt_serial_read (rt_device_t dev, rt_off_t pos, void* buffer, rt_size_t size)
-{
- rt_uint8_t* ptr;
- struct rt_at91serial *serial = (struct rt_at91serial*)dev;
- RT_ASSERT(serial != RT_NULL);
-
- /* point to buffer */
- ptr = (rt_uint8_t*) buffer;
-
- if (dev->flag & RT_DEVICE_FLAG_INT_RX)
- {
- while (size)
- {
- /* interrupt receive */
- rt_base_t level;
-
- /* disable interrupt */
- level = rt_hw_interrupt_disable();
- if (serial->read_index != serial->save_index)
- {
- *ptr = serial->rx_buffer[serial->read_index];
-
- serial->read_index ++;
- if (serial->read_index >= RT_UART_RX_BUFFER_SIZE)
- serial->read_index = 0;
- }
- else
- {
- /* no data in rx buffer */
-
- /* enable interrupt */
- rt_hw_interrupt_enable(level);
- break;
- }
-
- /* enable interrupt */
- rt_hw_interrupt_enable(level);
-
- ptr ++; size --;
- }
-
- return (rt_uint32_t)ptr - (rt_uint32_t)buffer;
- }
- else if (dev->flag & RT_DEVICE_FLAG_DMA_RX)
- {
- /* not support right now */
- RT_ASSERT(0);
- }
- else
- {
- /* poll mode */
- while (size)
- {
+} + +static rt_err_t rt_serial_close(rt_device_t dev) +{ + struct rt_at91serial *serial = (struct rt_at91serial*)dev; + RT_ASSERT(serial != RT_NULL); + + if (dev->flag & RT_DEVICE_FLAG_INT_RX) + { + /* disable interrupt */ + serial->hw_base->US_IDR = 1 << 0; /* RxReady interrupt */ + serial->hw_base->US_IMR &= ~(1 << 0); /* mask RxReady interrupt */ + } + + return RT_EOK; +} + +static rt_size_t rt_serial_read (rt_device_t dev, rt_off_t pos, void* buffer, rt_size_t size) +{ + rt_uint8_t* ptr; + struct rt_at91serial *serial = (struct rt_at91serial*)dev; + RT_ASSERT(serial != RT_NULL); + + /* point to buffer */ + ptr = (rt_uint8_t*) buffer; + + if (dev->flag & RT_DEVICE_FLAG_INT_RX) + { + while (size) + { + /* interrupt receive */ + rt_base_t level; + + /* disable interrupt */ + level = rt_hw_interrupt_disable(); + if (serial->read_index != serial->save_index) + { + *ptr = serial->rx_buffer[serial->read_index]; + + serial->read_index ++; + if (serial->read_index >= RT_UART_RX_BUFFER_SIZE) + serial->read_index = 0; + } + else + { + /* no data in rx buffer */ + + /* enable interrupt */ + rt_hw_interrupt_enable(level); + break; + } + + /* enable interrupt */ + rt_hw_interrupt_enable(level); + + ptr ++; size --; + } + + return (rt_uint32_t)ptr - (rt_uint32_t)buffer; + } + else if (dev->flag & RT_DEVICE_FLAG_DMA_RX) + { + /* not support right now */ + RT_ASSERT(0); + } + else + { + /* poll mode */ + while (size) + { /* Wait for Full Rx Buffer */ while (!(serial->hw_base->US_CSR & AT91C_US_RXRDY)); /* Read Character */ - *ptr = serial->hw_base->US_RHR;
- ptr ++;
+ *ptr = serial->hw_base->US_RHR; + ptr ++; size --; - }
-
- return (rt_size_t)ptr - (rt_size_t)buffer;
- }
-
- return 0;
-}
-
-static rt_size_t rt_serial_write (rt_device_t dev, rt_off_t pos, const void* buffer, rt_size_t size)
-{
- rt_uint8_t* ptr;
- struct rt_at91serial *serial = (struct rt_at91serial*)dev;
- RT_ASSERT(serial != RT_NULL);
-
- ptr = (rt_uint8_t*) buffer;
- if (dev->open_flag & RT_DEVICE_OFLAG_WRONLY)
- {
- if (dev->flag & RT_DEVICE_FLAG_STREAM)
- {
- /* it's a stream mode device */
- while (size)
- {
- /* stream mode */
+ } + + return (rt_size_t)ptr - (rt_size_t)buffer; + } + + return 0; +} + +static rt_size_t rt_serial_write (rt_device_t dev, rt_off_t pos, const void* buffer, rt_size_t size) +{ + rt_uint8_t* ptr; + struct rt_at91serial *serial = (struct rt_at91serial*)dev; + RT_ASSERT(serial != RT_NULL); + + ptr = (rt_uint8_t*) buffer; + if (dev->open_flag & RT_DEVICE_OFLAG_WRONLY) + { + if (dev->flag & RT_DEVICE_FLAG_STREAM) + { + /* it's a stream mode device */ + while (size) + { + /* stream mode */ if (*ptr == '\n') { while (!(serial->hw_base->US_CSR & AT91C_US_TXRDY)); @@ -312,76 +312,76 @@ static rt_size_t rt_serial_write (rt_device_t dev, rt_off_t pos, const void* buf while (!(serial->hw_base->US_CSR & AT91C_US_TXRDY)); /* Transmit Character */ - serial->hw_base->US_THR = *ptr;
+ serial->hw_base->US_THR = *ptr; ptr ++; size --; - }
- }
- else
- {
- while (size)
- {
+ } + } + else + { + while (size) + { /* Wait for Empty Tx Buffer */ while (!(serial->hw_base->US_CSR & AT91C_US_TXRDY)); /* Transmit Character */ - serial->hw_base->US_THR = *ptr;
- ptr ++; size --;
- }
- }
- }
-
- return (rt_size_t)ptr - (rt_size_t)buffer;
-}
-
-static rt_err_t rt_serial_control (rt_device_t dev, rt_uint8_t cmd, void *args)
-{
- return RT_EOK;
-}
-
-rt_err_t rt_hw_serial_init()
-{
- rt_device_t device;
-
-#ifdef RT_USING_UART1
- device = (rt_device_t) &serial1;
-
- /* init serial device private data */
- serial1.hw_base = (struct rt_at91serial_hw*)AT91C_BASE_US0;
- serial1.peripheral_id = AT91C_ID_US0;
- serial1.baudrate = 115200;
-
- /* set device virtual interface */
- device->init = rt_serial_init;
- device->open = rt_serial_open;
- device->close = rt_serial_close;
- device->read = rt_serial_read;
- device->write = rt_serial_write;
- device->control = rt_serial_control;
-
- /* register uart1 on device subsystem */
- rt_device_register(device, "uart1", RT_DEVICE_FLAG_RDWR | RT_DEVICE_FLAG_INT_RX);
-#endif
-
-#ifdef RT_USING_UART2
- device = (rt_device_t) &serial2;
-
- serial2.hw_base = (struct rt_at91serial_hw*)AT91C_BASE_US1;
- serial2.peripheral_id = AT91C_ID_US1;
- serial2.baudrate = 115200;
-
- /* set device virtual interface */
- device->init = rt_serial_init;
- device->open = rt_serial_open;
- device->close = rt_serial_close;
- device->read = rt_serial_read;
- device->write = rt_serial_write;
- device->control = rt_serial_control;
-
- /* register uart2 on device subsystem */
- rt_device_register(device, "uart2", RT_DEVICE_FLAG_RDWR | RT_DEVICE_FLAG_INT_RX);
-#endif
-
- return RT_EOK;
-}
-
+ serial->hw_base->US_THR = *ptr; + ptr ++; size --; + } + } + } + + return (rt_size_t)ptr - (rt_size_t)buffer; +} + +static rt_err_t rt_serial_control (rt_device_t dev, rt_uint8_t cmd, void *args) +{ + return RT_EOK; +} + +rt_err_t rt_hw_serial_init() +{ + rt_device_t device; + +#ifdef RT_USING_UART1 + device = (rt_device_t) &serial1; + + /* init serial device private data */ + serial1.hw_base = (struct rt_at91serial_hw*)AT91C_BASE_US0; + serial1.peripheral_id = AT91C_ID_US0; + serial1.baudrate = 115200; + + /* set device virtual interface */ + device->init = rt_serial_init; + device->open = rt_serial_open; + device->close = rt_serial_close; + device->read = rt_serial_read; + device->write = rt_serial_write; + device->control = rt_serial_control; + + /* register uart1 on device subsystem */ + rt_device_register(device, "uart1", RT_DEVICE_FLAG_RDWR | RT_DEVICE_FLAG_INT_RX); +#endif + +#ifdef RT_USING_UART2 + device = (rt_device_t) &serial2; + + serial2.hw_base = (struct rt_at91serial_hw*)AT91C_BASE_US1; + serial2.peripheral_id = AT91C_ID_US1; + serial2.baudrate = 115200; + + /* set device virtual interface */ + device->init = rt_serial_init; + device->open = rt_serial_open; + device->close = rt_serial_close; + device->read = rt_serial_read; + device->write = rt_serial_write; + device->control = rt_serial_control; + + /* register uart2 on device subsystem */ + rt_device_register(device, "uart2", RT_DEVICE_FLAG_RDWR | RT_DEVICE_FLAG_INT_RX); +#endif + + return RT_EOK; +} + /*@}*/ diff --git a/libcpu/arm/AT91SAM7S/serial.h b/libcpu/arm/AT91SAM7S/serial.h index 5fe0928c9a..401b0c3129 100644 --- a/libcpu/arm/AT91SAM7S/serial.h +++ b/libcpu/arm/AT91SAM7S/serial.h @@ -1,14 +1,14 @@ -#ifndef __RT_SERIAL_H__
-#define __RT_SERIAL_H__
-
-#ifndef AT91C_BASE_US0
-#define AT91C_BASE_US0 (0xFFFC0000) // (US0) Base Address
-#endif
-
-#ifndef AT91C_BASE_US1
-#define AT91C_BASE_US1 (0xFFFC4000) // (US1) Base Address
-#endif
-
+#ifndef __RT_SERIAL_H__ +#define __RT_SERIAL_H__ + +#ifndef AT91C_BASE_US0 +#define AT91C_BASE_US0 (0xFFFC0000) // (US0) Base Address +#endif + +#ifndef AT91C_BASE_US1 +#define AT91C_BASE_US1 (0xFFFC4000) // (US1) Base Address +#endif + #define AT91C_US_RXRDY ((unsigned int) 0x1 << 0) /* US RXRDY Interrupt */ #define AT91C_US_TXRDY ((unsigned int) 0x1 << 1) /* US TXRDY Interrupt */ #define AT91C_US_RSTRX ((unsigned int) 0x1 << 2) /* US Reset Receiver */ @@ -52,5 +52,5 @@ #define MCK 48054857 #define BR 115200 /* Baud Rate */ #define BRD (MCK/16/BR) /* Baud Rate Divisor */ -
-#endif
+ +#endif diff --git a/libcpu/arm/AT91SAM7S/start_rvds.S b/libcpu/arm/AT91SAM7S/start_rvds.S index a4e403c1af..84274bbe20 100644 --- a/libcpu/arm/AT91SAM7S/start_rvds.S +++ b/libcpu/arm/AT91SAM7S/start_rvds.S @@ -1,499 +1,499 @@ -;/*****************************************************************************/
-;/* SAM7.S: Startup file for Atmel AT91SAM7 device series */
-;/*****************************************************************************/
-;/* <<< Use Configuration Wizard in Context Menu >>> */
-;/*****************************************************************************/
-;/* This file is part of the uVision/ARM development tools. */
-;/* Copyright (c) 2005-2006 Keil Software. All rights reserved. */
-;/* This software may only be used under the terms of a valid, current, */
-;/* end user licence from KEIL for a compatible version of KEIL software */
-;/* development tools. Nothing else gives you the right to use this software. */
-;/*****************************************************************************/
-
-
-;/*
-; * The SAM7.S code is executed after CPU Reset. This file may be
-; * translated with the following SET symbols. In uVision these SET
-; * symbols are entered under Options - ASM - Define.
-; *
-; * REMAP: when set the startup code remaps exception vectors from
-; * on-chip RAM to address 0.
-; *
-; * RAM_INTVEC: when set the startup code copies exception vectors
-; * from on-chip Flash to on-chip RAM.
-; */
-
-
-; Standard definitions of Mode bits and Interrupt (I & F) flags in PSRs
-
-Mode_USR EQU 0x10
-Mode_FIQ EQU 0x11
-Mode_IRQ EQU 0x12
-Mode_SVC EQU 0x13
-Mode_ABT EQU 0x17
-Mode_UND EQU 0x1B
-Mode_SYS EQU 0x1F
-
-I_Bit EQU 0x80 ; when I bit is set, IRQ is disabled
-F_Bit EQU 0x40 ; when F bit is set, FIQ is disabled
-
-
-; Internal Memory Base Addresses
-FLASH_BASE EQU 0x00100000
-RAM_BASE EQU 0x00200000
-
-
-;// <h> Stack Configuration (Stack Sizes in Bytes)
-;// <o0> Undefined Mode <0x0-0xFFFFFFFF:8>
-;// <o1> Supervisor Mode <0x0-0xFFFFFFFF:8>
-;// <o2> Abort Mode <0x0-0xFFFFFFFF:8>
-;// <o3> Fast Interrupt Mode <0x0-0xFFFFFFFF:8>
-;// <o4> Interrupt Mode <0x0-0xFFFFFFFF:8>
-;// <o5> User/System Mode <0x0-0xFFFFFFFF:8>
-;// </h>
-
-UND_Stack_Size EQU 0x00000000
-SVC_Stack_Size EQU 0x00000100
-ABT_Stack_Size EQU 0x00000000
-FIQ_Stack_Size EQU 0x00000000
-IRQ_Stack_Size EQU 0x00000100
-USR_Stack_Size EQU 0x00000100
-
-ISR_Stack_Size EQU (UND_Stack_Size + SVC_Stack_Size + ABT_Stack_Size + \
- FIQ_Stack_Size + IRQ_Stack_Size)
-
- AREA STACK, NOINIT, READWRITE, ALIGN=3
-
-Stack_Mem SPACE USR_Stack_Size
-__initial_sp SPACE ISR_Stack_Size
-Stack_Top
-
-
-;// <h> Heap Configuration
-;// <o> Heap Size (in Bytes) <0x0-0xFFFFFFFF>
-;// </h>
-
-Heap_Size EQU 0x00000000
-
- AREA HEAP, NOINIT, READWRITE, ALIGN=3
-__heap_base
-Heap_Mem SPACE Heap_Size
-__heap_limit
-
-
-; Reset Controller (RSTC) definitions
-RSTC_BASE EQU 0xFFFFFD00 ; RSTC Base Address
-RSTC_MR EQU 0x08 ; RSTC_MR Offset
-
-;/*
-;// <e> Reset Controller (RSTC)
-;// <o1.0> URSTEN: User Reset Enable
-;// <i> Enables NRST Pin to generate Reset
-;// <o1.8..11> ERSTL: External Reset Length <0-15>
-;// <i> External Reset Time in 2^(ERSTL+1) Slow Clock Cycles
-;// </e>
-;*/
-RSTC_SETUP EQU 1
-RSTC_MR_Val EQU 0xA5000401
-
-
-; Embedded Flash Controller (EFC) definitions
-EFC_BASE EQU 0xFFFFFF00 ; EFC Base Address
-EFC0_FMR EQU 0x60 ; EFC0_FMR Offset
-EFC1_FMR EQU 0x70 ; EFC1_FMR Offset
-
-;// <e> Embedded Flash Controller 0 (EFC0)
-;// <o1.16..23> FMCN: Flash Microsecond Cycle Number <0-255>
-;// <i> Number of Master Clock Cycles in 1us
-;// <o1.8..9> FWS: Flash Wait State
-;// <0=> Read: 1 cycle / Write: 2 cycles
-;// <1=> Read: 2 cycle / Write: 3 cycles
-;// <2=> Read: 3 cycle / Write: 4 cycles
-;// <3=> Read: 4 cycle / Write: 4 cycles
-;// </e>
-EFC0_SETUP EQU 1
-EFC0_FMR_Val EQU 0x00320100
-
-;// <e> Embedded Flash Controller 1 (EFC1)
-;// <o1.16..23> FMCN: Flash Microsecond Cycle Number <0-255>
-;// <i> Number of Master Clock Cycles in 1us
-;// <o1.8..9> FWS: Flash Wait State
-;// <0=> Read: 1 cycle / Write: 2 cycles
-;// <1=> Read: 2 cycle / Write: 3 cycles
-;// <2=> Read: 3 cycle / Write: 4 cycles
-;// <3=> Read: 4 cycle / Write: 4 cycles
-;// </e>
-EFC1_SETUP EQU 0
-EFC1_FMR_Val EQU 0x00320100
-
-
-; Watchdog Timer (WDT) definitions
-WDT_BASE EQU 0xFFFFFD40 ; WDT Base Address
-WDT_MR EQU 0x04 ; WDT_MR Offset
-
-;// <e> Watchdog Timer (WDT)
-;// <o1.0..11> WDV: Watchdog Counter Value <0-4095>
-;// <o1.16..27> WDD: Watchdog Delta Value <0-4095>
-;// <o1.12> WDFIEN: Watchdog Fault Interrupt Enable
-;// <o1.13> WDRSTEN: Watchdog Reset Enable
-;// <o1.14> WDRPROC: Watchdog Reset Processor
-;// <o1.28> WDDBGHLT: Watchdog Debug Halt
-;// <o1.29> WDIDLEHLT: Watchdog Idle Halt
-;// <o1.15> WDDIS: Watchdog Disable
-;// </e>
-WDT_SETUP EQU 1
-WDT_MR_Val EQU 0x00008000
-
-
-; Power Mangement Controller (PMC) definitions
-PMC_BASE EQU 0xFFFFFC00 ; PMC Base Address
-PMC_MOR EQU 0x20 ; PMC_MOR Offset
-PMC_MCFR EQU 0x24 ; PMC_MCFR Offset
-PMC_PLLR EQU 0x2C ; PMC_PLLR Offset
-PMC_MCKR EQU 0x30 ; PMC_MCKR Offset
-PMC_SR EQU 0x68 ; PMC_SR Offset
-PMC_MOSCEN EQU (1<<0) ; Main Oscillator Enable
-PMC_OSCBYPASS EQU (1<<1) ; Main Oscillator Bypass
-PMC_OSCOUNT EQU (0xFF<<8) ; Main OScillator Start-up Time
-PMC_DIV EQU (0xFF<<0) ; PLL Divider
-PMC_PLLCOUNT EQU (0x3F<<8) ; PLL Lock Counter
-PMC_OUT EQU (0x03<<14) ; PLL Clock Frequency Range
-PMC_MUL EQU (0x7FF<<16) ; PLL Multiplier
-PMC_USBDIV EQU (0x03<<28) ; USB Clock Divider
-PMC_CSS EQU (3<<0) ; Clock Source Selection
-PMC_PRES EQU (7<<2) ; Prescaler Selection
-PMC_MOSCS EQU (1<<0) ; Main Oscillator Stable
-PMC_LOCK EQU (1<<2) ; PLL Lock Status
-PMC_MCKRDY EQU (1<<3) ; Master Clock Status
-
-;// <e> Power Mangement Controller (PMC)
-;// <h> Main Oscillator
-;// <o1.0> MOSCEN: Main Oscillator Enable
-;// <o1.1> OSCBYPASS: Oscillator Bypass
-;// <o1.8..15> OSCCOUNT: Main Oscillator Startup Time <0-255>
-;// </h>
-;// <h> Phase Locked Loop (PLL)
-;// <o2.0..7> DIV: PLL Divider <0-255>
-;// <o2.16..26> MUL: PLL Multiplier <0-2047>
-;// <i> PLL Output is multiplied by MUL+1
-;// <o2.14..15> OUT: PLL Clock Frequency Range
-;// <0=> 80..160MHz <1=> Reserved
-;// <2=> 150..220MHz <3=> Reserved
-;// <o2.8..13> PLLCOUNT: PLL Lock Counter <0-63>
-;// <o2.28..29> USBDIV: USB Clock Divider
-;// <0=> None <1=> 2 <2=> 4 <3=> Reserved
-;// </h>
-;// <o3.0..1> CSS: Clock Source Selection
-;// <0=> Slow Clock
-;// <1=> Main Clock
-;// <2=> Reserved
-;// <3=> PLL Clock
-;// <o3.2..4> PRES: Prescaler
-;// <0=> None
-;// <1=> Clock / 2 <2=> Clock / 4
-;// <3=> Clock / 8 <4=> Clock / 16
-;// <5=> Clock / 32 <6=> Clock / 64
-;// <7=> Reserved
-;// </e>
-PMC_SETUP EQU 1
-PMC_MOR_Val EQU 0x00000601
-PMC_PLLR_Val EQU 0x00191C05
-PMC_MCKR_Val EQU 0x00000007
-
-
- PRESERVE8
-
-
-; Area Definition and Entry Point
-; Startup Code must be linked first at Address at which it expects to run.
-
- AREA RESET, CODE, READONLY
- ARM
-
-
-; Exception Vectors
-; Mapped to Address 0.
-; Absolute addressing mode must be used.
-; Dummy Handlers are implemented as infinite loops which can be modified.
-
-Vectors LDR PC,Reset_Addr
- LDR PC,Undef_Addr
- LDR PC,SWI_Addr
- LDR PC,PAbt_Addr
- LDR PC,DAbt_Addr
- NOP ; Reserved Vector
- LDR PC,IRQ_Addr
- LDR PC,FIQ_Addr
-
-Reset_Addr DCD Reset_Handler
-Undef_Addr DCD Undef_Handler
-SWI_Addr DCD SWI_Handler
-PAbt_Addr DCD PAbt_Handler
-DAbt_Addr DCD DAbt_Handler
- DCD 0 ; Reserved Address
-IRQ_Addr DCD IRQ_Handler
-FIQ_Addr DCD FIQ_Handler
-
-Undef_Handler B Undef_Handler
-SWI_Handler B SWI_Handler
-PAbt_Handler B PAbt_Handler
-DAbt_Handler B DAbt_Handler
-FIQ_Handler B FIQ_Handler
-
-
-; Reset Handler
-
- EXPORT Reset_Handler
-Reset_Handler
-
-
-; Setup RSTC
- IF RSTC_SETUP != 0
- LDR R0, =RSTC_BASE
- LDR R1, =RSTC_MR_Val
- STR R1, [R0, #RSTC_MR]
- ENDIF
-
-
-; Setup EFC0
- IF EFC0_SETUP != 0
- LDR R0, =EFC_BASE
- LDR R1, =EFC0_FMR_Val
- STR R1, [R0, #EFC0_FMR]
- ENDIF
-
-; Setup EFC1
- IF EFC1_SETUP != 0
- LDR R0, =EFC_BASE
- LDR R1, =EFC1_FMR_Val
- STR R1, [R0, #EFC1_FMR]
- ENDIF
-
-; Setup WDT
- IF WDT_SETUP != 0
- LDR R0, =WDT_BASE
- LDR R1, =WDT_MR_Val
- STR R1, [R0, #WDT_MR]
- ENDIF
-
-
-; Setup PMC
- IF PMC_SETUP != 0
- LDR R0, =PMC_BASE
-
-; Setup Main Oscillator
- LDR R1, =PMC_MOR_Val
- STR R1, [R0, #PMC_MOR]
-
-; Wait until Main Oscillator is stablilized
- IF (PMC_MOR_Val:AND:PMC_MOSCEN) != 0
-MOSCS_Loop LDR R2, [R0, #PMC_SR]
- ANDS R2, R2, #PMC_MOSCS
- BEQ MOSCS_Loop
- ENDIF
-
-; Setup the PLL
- IF (PMC_PLLR_Val:AND:PMC_MUL) != 0
- LDR R1, =PMC_PLLR_Val
- STR R1, [R0, #PMC_PLLR]
-
-; Wait until PLL is stabilized
-PLL_Loop LDR R2, [R0, #PMC_SR]
- ANDS R2, R2, #PMC_LOCK
- BEQ PLL_Loop
- ENDIF
-
-; Select Clock
- IF (PMC_MCKR_Val:AND:PMC_CSS) == 1 ; Main Clock Selected
- LDR R1, =PMC_MCKR_Val
- AND R1, #PMC_CSS
- STR R1, [R0, #PMC_MCKR]
-WAIT_Rdy1 LDR R2, [R0, #PMC_SR]
- ANDS R2, R2, #PMC_MCKRDY
- BEQ WAIT_Rdy1
- LDR R1, =PMC_MCKR_Val
- STR R1, [R0, #PMC_MCKR]
-WAIT_Rdy2 LDR R2, [R0, #PMC_SR]
- ANDS R2, R2, #PMC_MCKRDY
- BEQ WAIT_Rdy2
- ELIF (PMC_MCKR_Val:AND:PMC_CSS) == 3 ; PLL Clock Selected
- LDR R1, =PMC_MCKR_Val
- AND R1, #PMC_PRES
- STR R1, [R0, #PMC_MCKR]
-WAIT_Rdy1 LDR R2, [R0, #PMC_SR]
- ANDS R2, R2, #PMC_MCKRDY
- BEQ WAIT_Rdy1
- LDR R1, =PMC_MCKR_Val
- STR R1, [R0, #PMC_MCKR]
-WAIT_Rdy2 LDR R2, [R0, #PMC_SR]
- ANDS R2, R2, #PMC_MCKRDY
- BEQ WAIT_Rdy2
- ENDIF ; Select Clock
- ENDIF ; PMC_SETUP
-
-
-; Copy Exception Vectors to Internal RAM
-
- IF :DEF:RAM_INTVEC
- ADR R8, Vectors ; Source
- LDR R9, =RAM_BASE ; Destination
- LDMIA R8!, {R0-R7} ; Load Vectors
- STMIA R9!, {R0-R7} ; Store Vectors
- LDMIA R8!, {R0-R7} ; Load Handler Addresses
- STMIA R9!, {R0-R7} ; Store Handler Addresses
- ENDIF
-
-
-; Remap on-chip RAM to address 0
-
-MC_BASE EQU 0xFFFFFF00 ; MC Base Address
-MC_RCR EQU 0x00 ; MC_RCR Offset
-
- IF :DEF:REMAP
- LDR R0, =MC_BASE
- MOV R1, #1
- STR R1, [R0, #MC_RCR] ; Remap
- ENDIF
-
-
-; Setup Stack for each mode
-
- LDR R0, =Stack_Top
-
-; Enter Undefined Instruction Mode and set its Stack Pointer
- MSR CPSR_c, #Mode_UND:OR:I_Bit:OR:F_Bit
- MOV SP, R0
- SUB R0, R0, #UND_Stack_Size
-
-; Enter Abort Mode and set its Stack Pointer
- MSR CPSR_c, #Mode_ABT:OR:I_Bit:OR:F_Bit
- MOV SP, R0
- SUB R0, R0, #ABT_Stack_Size
-
-; Enter FIQ Mode and set its Stack Pointer
- MSR CPSR_c, #Mode_FIQ:OR:I_Bit:OR:F_Bit
- MOV SP, R0
- SUB R0, R0, #FIQ_Stack_Size
-
-; Enter IRQ Mode and set its Stack Pointer
- MSR CPSR_c, #Mode_IRQ:OR:I_Bit:OR:F_Bit
- MOV SP, R0
- SUB R0, R0, #IRQ_Stack_Size
-
-; Enter Supervisor Mode and set its Stack Pointer
- MSR CPSR_c, #Mode_SVC:OR:I_Bit:OR:F_Bit
- MOV SP, R0
- SUB R0, R0, #SVC_Stack_Size
-
-; Enter User Mode and set its Stack Pointer
- ; MSR CPSR_c, #Mode_USR
- IF :DEF:__MICROLIB
-
- EXPORT __initial_sp
-
- ELSE
-
- ; No usr mode stack here.
- ;MOV SP, R0
- ;SUB SL, SP, #USR_Stack_Size
-
- ENDIF
-
-
-; Enter the C code
-
- IMPORT __main
- LDR R0, =__main
- BX R0
-
- IMPORT rt_interrupt_enter
- IMPORT rt_interrupt_leave
- IMPORT rt_thread_switch_interrupt_flag
- IMPORT rt_interrupt_from_thread
- IMPORT rt_interrupt_to_thread
- IMPORT rt_hw_trap_irq
-
-IRQ_Handler PROC
- EXPORT IRQ_Handler
- STMFD sp!, {r0-r12,lr}
- BL rt_interrupt_enter
- BL rt_hw_trap_irq
- BL rt_interrupt_leave
-
- ; if rt_thread_switch_interrupt_flag set, jump to
- ; rt_hw_context_switch_interrupt_do and don't return
- LDR r0, =rt_thread_switch_interrupt_flag
- LDR r1, [r0]
- CMP r1, #1
- BEQ rt_hw_context_switch_interrupt_do
-
- LDMFD sp!, {r0-r12,lr}
- SUBS pc, lr, #4
- ENDP
-
-; /*
-; * void rt_hw_context_switch_interrupt_do(rt_base_t flag)
-; */
-rt_hw_context_switch_interrupt_do PROC
- EXPORT rt_hw_context_switch_interrupt_do
- MOV r1, #0 ; clear flag
- STR r1, [r0]
-
- LDMFD sp!, {r0-r12,lr}; reload saved registers
- STMFD sp!, {r0-r3} ; save r0-r3
- MOV r1, sp
- ADD sp, sp, #16 ; restore sp
- SUB r2, lr, #4 ; save old task's pc to r2
-
- MRS r3, spsr ; get cpsr of interrupt thread
-
- ; switch to SVC mode and no interrupt
- MSR cpsr_c, #I_Bit|F_Bit|Mode_SVC
-
- STMFD sp!, {r2} ; push old task's pc
- STMFD sp!, {r4-r12,lr}; push old task's lr,r12-r4
- MOV r4, r1 ; Special optimised code below
- MOV r5, r3
- LDMFD r4!, {r0-r3}
- STMFD sp!, {r0-r3} ; push old task's r3-r0
- STMFD sp!, {r5} ; push old task's cpsr
- MRS r4, spsr
- STMFD sp!, {r4} ; push old task's spsr
-
- LDR r4, =rt_interrupt_from_thread
- LDR r5, [r4]
- STR sp, [r5] ; store sp in preempted tasks's TCB
-
- LDR r6, =rt_interrupt_to_thread
- LDR r6, [r6]
- LDR sp, [r6] ; get new task's stack pointer
-
- LDMFD sp!, {r4} ; pop new task's spsr
- MSR spsr_cxsf, r4
- LDMFD sp!, {r4} ; pop new task's psr
- MSR cpsr_cxsf, r4
-
- LDMFD sp!, {r0-r12,lr,pc} ; pop new task's r0-r12,lr & pc
- ENDP
-
- IF :DEF:__MICROLIB
-
- EXPORT __heap_base
- EXPORT __heap_limit
-
- ELSE
-; User Initial Stack & Heap
- AREA |.text|, CODE, READONLY
-
- IMPORT __use_two_region_memory
- EXPORT __user_initial_stackheap
-__user_initial_stackheap
-
- LDR R0, = Heap_Mem
- LDR R1, = (Stack_Mem + IRQ_Stack_Size)
- LDR R2, = (Heap_Mem + Heap_Size)
- LDR R3, = Stack_Mem
- BX LR
- ENDIF
-
- END
+;/*****************************************************************************/ +;/* SAM7.S: Startup file for Atmel AT91SAM7 device series */ +;/*****************************************************************************/ +;/* <<< Use Configuration Wizard in Context Menu >>> */ +;/*****************************************************************************/ +;/* This file is part of the uVision/ARM development tools. */ +;/* Copyright (c) 2005-2006 Keil Software. All rights reserved. */ +;/* This software may only be used under the terms of a valid, current, */ +;/* end user licence from KEIL for a compatible version of KEIL software */ +;/* development tools. Nothing else gives you the right to use this software. */ +;/*****************************************************************************/ + + +;/* +; * The SAM7.S code is executed after CPU Reset. This file may be +; * translated with the following SET symbols. In uVision these SET +; * symbols are entered under Options - ASM - Define. +; * +; * REMAP: when set the startup code remaps exception vectors from +; * on-chip RAM to address 0. +; * +; * RAM_INTVEC: when set the startup code copies exception vectors +; * from on-chip Flash to on-chip RAM. +; */ + + +; Standard definitions of Mode bits and Interrupt (I & F) flags in PSRs + +Mode_USR EQU 0x10 +Mode_FIQ EQU 0x11 +Mode_IRQ EQU 0x12 +Mode_SVC EQU 0x13 +Mode_ABT EQU 0x17 +Mode_UND EQU 0x1B +Mode_SYS EQU 0x1F + +I_Bit EQU 0x80 ; when I bit is set, IRQ is disabled +F_Bit EQU 0x40 ; when F bit is set, FIQ is disabled + + +; Internal Memory Base Addresses +FLASH_BASE EQU 0x00100000 +RAM_BASE EQU 0x00200000 + + +;// <h> Stack Configuration (Stack Sizes in Bytes) +;// <o0> Undefined Mode <0x0-0xFFFFFFFF:8> +;// <o1> Supervisor Mode <0x0-0xFFFFFFFF:8> +;// <o2> Abort Mode <0x0-0xFFFFFFFF:8> +;// <o3> Fast Interrupt Mode <0x0-0xFFFFFFFF:8> +;// <o4> Interrupt Mode <0x0-0xFFFFFFFF:8> +;// <o5> User/System Mode <0x0-0xFFFFFFFF:8> +;// </h> + +UND_Stack_Size EQU 0x00000000 +SVC_Stack_Size EQU 0x00000100 +ABT_Stack_Size EQU 0x00000000 +FIQ_Stack_Size EQU 0x00000000 +IRQ_Stack_Size EQU 0x00000100 +USR_Stack_Size EQU 0x00000100 + +ISR_Stack_Size EQU (UND_Stack_Size + SVC_Stack_Size + ABT_Stack_Size + \ + FIQ_Stack_Size + IRQ_Stack_Size) + + AREA STACK, NOINIT, READWRITE, ALIGN=3 + +Stack_Mem SPACE USR_Stack_Size +__initial_sp SPACE ISR_Stack_Size +Stack_Top + + +;// <h> Heap Configuration +;// <o> Heap Size (in Bytes) <0x0-0xFFFFFFFF> +;// </h> + +Heap_Size EQU 0x00000000 + + AREA HEAP, NOINIT, READWRITE, ALIGN=3 +__heap_base +Heap_Mem SPACE Heap_Size +__heap_limit + + +; Reset Controller (RSTC) definitions +RSTC_BASE EQU 0xFFFFFD00 ; RSTC Base Address +RSTC_MR EQU 0x08 ; RSTC_MR Offset + +;/* +;// <e> Reset Controller (RSTC) +;// <o1.0> URSTEN: User Reset Enable +;// <i> Enables NRST Pin to generate Reset +;// <o1.8..11> ERSTL: External Reset Length <0-15> +;// <i> External Reset Time in 2^(ERSTL+1) Slow Clock Cycles +;// </e> +;*/ +RSTC_SETUP EQU 1 +RSTC_MR_Val EQU 0xA5000401 + + +; Embedded Flash Controller (EFC) definitions +EFC_BASE EQU 0xFFFFFF00 ; EFC Base Address +EFC0_FMR EQU 0x60 ; EFC0_FMR Offset +EFC1_FMR EQU 0x70 ; EFC1_FMR Offset + +;// <e> Embedded Flash Controller 0 (EFC0) +;// <o1.16..23> FMCN: Flash Microsecond Cycle Number <0-255> +;// <i> Number of Master Clock Cycles in 1us +;// <o1.8..9> FWS: Flash Wait State +;// <0=> Read: 1 cycle / Write: 2 cycles +;// <1=> Read: 2 cycle / Write: 3 cycles +;// <2=> Read: 3 cycle / Write: 4 cycles +;// <3=> Read: 4 cycle / Write: 4 cycles +;// </e> +EFC0_SETUP EQU 1 +EFC0_FMR_Val EQU 0x00320100 + +;// <e> Embedded Flash Controller 1 (EFC1) +;// <o1.16..23> FMCN: Flash Microsecond Cycle Number <0-255> +;// <i> Number of Master Clock Cycles in 1us +;// <o1.8..9> FWS: Flash Wait State +;// <0=> Read: 1 cycle / Write: 2 cycles +;// <1=> Read: 2 cycle / Write: 3 cycles +;// <2=> Read: 3 cycle / Write: 4 cycles +;// <3=> Read: 4 cycle / Write: 4 cycles +;// </e> +EFC1_SETUP EQU 0 +EFC1_FMR_Val EQU 0x00320100 + + +; Watchdog Timer (WDT) definitions +WDT_BASE EQU 0xFFFFFD40 ; WDT Base Address +WDT_MR EQU 0x04 ; WDT_MR Offset + +;// <e> Watchdog Timer (WDT) +;// <o1.0..11> WDV: Watchdog Counter Value <0-4095> +;// <o1.16..27> WDD: Watchdog Delta Value <0-4095> +;// <o1.12> WDFIEN: Watchdog Fault Interrupt Enable +;// <o1.13> WDRSTEN: Watchdog Reset Enable +;// <o1.14> WDRPROC: Watchdog Reset Processor +;// <o1.28> WDDBGHLT: Watchdog Debug Halt +;// <o1.29> WDIDLEHLT: Watchdog Idle Halt +;// <o1.15> WDDIS: Watchdog Disable +;// </e> +WDT_SETUP EQU 1 +WDT_MR_Val EQU 0x00008000 + + +; Power Mangement Controller (PMC) definitions +PMC_BASE EQU 0xFFFFFC00 ; PMC Base Address +PMC_MOR EQU 0x20 ; PMC_MOR Offset +PMC_MCFR EQU 0x24 ; PMC_MCFR Offset +PMC_PLLR EQU 0x2C ; PMC_PLLR Offset +PMC_MCKR EQU 0x30 ; PMC_MCKR Offset +PMC_SR EQU 0x68 ; PMC_SR Offset +PMC_MOSCEN EQU (1<<0) ; Main Oscillator Enable +PMC_OSCBYPASS EQU (1<<1) ; Main Oscillator Bypass +PMC_OSCOUNT EQU (0xFF<<8) ; Main OScillator Start-up Time +PMC_DIV EQU (0xFF<<0) ; PLL Divider +PMC_PLLCOUNT EQU (0x3F<<8) ; PLL Lock Counter +PMC_OUT EQU (0x03<<14) ; PLL Clock Frequency Range +PMC_MUL EQU (0x7FF<<16) ; PLL Multiplier +PMC_USBDIV EQU (0x03<<28) ; USB Clock Divider +PMC_CSS EQU (3<<0) ; Clock Source Selection +PMC_PRES EQU (7<<2) ; Prescaler Selection +PMC_MOSCS EQU (1<<0) ; Main Oscillator Stable +PMC_LOCK EQU (1<<2) ; PLL Lock Status +PMC_MCKRDY EQU (1<<3) ; Master Clock Status + +;// <e> Power Mangement Controller (PMC) +;// <h> Main Oscillator +;// <o1.0> MOSCEN: Main Oscillator Enable +;// <o1.1> OSCBYPASS: Oscillator Bypass +;// <o1.8..15> OSCCOUNT: Main Oscillator Startup Time <0-255> +;// </h> +;// <h> Phase Locked Loop (PLL) +;// <o2.0..7> DIV: PLL Divider <0-255> +;// <o2.16..26> MUL: PLL Multiplier <0-2047> +;// <i> PLL Output is multiplied by MUL+1 +;// <o2.14..15> OUT: PLL Clock Frequency Range +;// <0=> 80..160MHz <1=> Reserved +;// <2=> 150..220MHz <3=> Reserved +;// <o2.8..13> PLLCOUNT: PLL Lock Counter <0-63> +;// <o2.28..29> USBDIV: USB Clock Divider +;// <0=> None <1=> 2 <2=> 4 <3=> Reserved +;// </h> +;// <o3.0..1> CSS: Clock Source Selection +;// <0=> Slow Clock +;// <1=> Main Clock +;// <2=> Reserved +;// <3=> PLL Clock +;// <o3.2..4> PRES: Prescaler +;// <0=> None +;// <1=> Clock / 2 <2=> Clock / 4 +;// <3=> Clock / 8 <4=> Clock / 16 +;// <5=> Clock / 32 <6=> Clock / 64 +;// <7=> Reserved +;// </e> +PMC_SETUP EQU 1 +PMC_MOR_Val EQU 0x00000601 +PMC_PLLR_Val EQU 0x00191C05 +PMC_MCKR_Val EQU 0x00000007 + + + PRESERVE8 + + +; Area Definition and Entry Point +; Startup Code must be linked first at Address at which it expects to run. + + AREA RESET, CODE, READONLY + ARM + + +; Exception Vectors +; Mapped to Address 0. +; Absolute addressing mode must be used. +; Dummy Handlers are implemented as infinite loops which can be modified. + +Vectors LDR PC,Reset_Addr + LDR PC,Undef_Addr + LDR PC,SWI_Addr + LDR PC,PAbt_Addr + LDR PC,DAbt_Addr + NOP ; Reserved Vector + LDR PC,IRQ_Addr + LDR PC,FIQ_Addr + +Reset_Addr DCD Reset_Handler +Undef_Addr DCD Undef_Handler +SWI_Addr DCD SWI_Handler +PAbt_Addr DCD PAbt_Handler +DAbt_Addr DCD DAbt_Handler + DCD 0 ; Reserved Address +IRQ_Addr DCD IRQ_Handler +FIQ_Addr DCD FIQ_Handler + +Undef_Handler B Undef_Handler +SWI_Handler B SWI_Handler +PAbt_Handler B PAbt_Handler +DAbt_Handler B DAbt_Handler +FIQ_Handler B FIQ_Handler + + +; Reset Handler + + EXPORT Reset_Handler +Reset_Handler + + +; Setup RSTC + IF RSTC_SETUP != 0 + LDR R0, =RSTC_BASE + LDR R1, =RSTC_MR_Val + STR R1, [R0, #RSTC_MR] + ENDIF + + +; Setup EFC0 + IF EFC0_SETUP != 0 + LDR R0, =EFC_BASE + LDR R1, =EFC0_FMR_Val + STR R1, [R0, #EFC0_FMR] + ENDIF + +; Setup EFC1 + IF EFC1_SETUP != 0 + LDR R0, =EFC_BASE + LDR R1, =EFC1_FMR_Val + STR R1, [R0, #EFC1_FMR] + ENDIF + +; Setup WDT + IF WDT_SETUP != 0 + LDR R0, =WDT_BASE + LDR R1, =WDT_MR_Val + STR R1, [R0, #WDT_MR] + ENDIF + + +; Setup PMC + IF PMC_SETUP != 0 + LDR R0, =PMC_BASE + +; Setup Main Oscillator + LDR R1, =PMC_MOR_Val + STR R1, [R0, #PMC_MOR] + +; Wait until Main Oscillator is stablilized + IF (PMC_MOR_Val:AND:PMC_MOSCEN) != 0 +MOSCS_Loop LDR R2, [R0, #PMC_SR] + ANDS R2, R2, #PMC_MOSCS + BEQ MOSCS_Loop + ENDIF + +; Setup the PLL + IF (PMC_PLLR_Val:AND:PMC_MUL) != 0 + LDR R1, =PMC_PLLR_Val + STR R1, [R0, #PMC_PLLR] + +; Wait until PLL is stabilized +PLL_Loop LDR R2, [R0, #PMC_SR] + ANDS R2, R2, #PMC_LOCK + BEQ PLL_Loop + ENDIF + +; Select Clock + IF (PMC_MCKR_Val:AND:PMC_CSS) == 1 ; Main Clock Selected + LDR R1, =PMC_MCKR_Val + AND R1, #PMC_CSS + STR R1, [R0, #PMC_MCKR] +WAIT_Rdy1 LDR R2, [R0, #PMC_SR] + ANDS R2, R2, #PMC_MCKRDY + BEQ WAIT_Rdy1 + LDR R1, =PMC_MCKR_Val + STR R1, [R0, #PMC_MCKR] +WAIT_Rdy2 LDR R2, [R0, #PMC_SR] + ANDS R2, R2, #PMC_MCKRDY + BEQ WAIT_Rdy2 + ELIF (PMC_MCKR_Val:AND:PMC_CSS) == 3 ; PLL Clock Selected + LDR R1, =PMC_MCKR_Val + AND R1, #PMC_PRES + STR R1, [R0, #PMC_MCKR] +WAIT_Rdy1 LDR R2, [R0, #PMC_SR] + ANDS R2, R2, #PMC_MCKRDY + BEQ WAIT_Rdy1 + LDR R1, =PMC_MCKR_Val + STR R1, [R0, #PMC_MCKR] +WAIT_Rdy2 LDR R2, [R0, #PMC_SR] + ANDS R2, R2, #PMC_MCKRDY + BEQ WAIT_Rdy2 + ENDIF ; Select Clock + ENDIF ; PMC_SETUP + + +; Copy Exception Vectors to Internal RAM + + IF :DEF:RAM_INTVEC + ADR R8, Vectors ; Source + LDR R9, =RAM_BASE ; Destination + LDMIA R8!, {R0-R7} ; Load Vectors + STMIA R9!, {R0-R7} ; Store Vectors + LDMIA R8!, {R0-R7} ; Load Handler Addresses + STMIA R9!, {R0-R7} ; Store Handler Addresses + ENDIF + + +; Remap on-chip RAM to address 0 + +MC_BASE EQU 0xFFFFFF00 ; MC Base Address +MC_RCR EQU 0x00 ; MC_RCR Offset + + IF :DEF:REMAP + LDR R0, =MC_BASE + MOV R1, #1 + STR R1, [R0, #MC_RCR] ; Remap + ENDIF + + +; Setup Stack for each mode + + LDR R0, =Stack_Top + +; Enter Undefined Instruction Mode and set its Stack Pointer + MSR CPSR_c, #Mode_UND:OR:I_Bit:OR:F_Bit + MOV SP, R0 + SUB R0, R0, #UND_Stack_Size + +; Enter Abort Mode and set its Stack Pointer + MSR CPSR_c, #Mode_ABT:OR:I_Bit:OR:F_Bit + MOV SP, R0 + SUB R0, R0, #ABT_Stack_Size + +; Enter FIQ Mode and set its Stack Pointer + MSR CPSR_c, #Mode_FIQ:OR:I_Bit:OR:F_Bit + MOV SP, R0 + SUB R0, R0, #FIQ_Stack_Size + +; Enter IRQ Mode and set its Stack Pointer + MSR CPSR_c, #Mode_IRQ:OR:I_Bit:OR:F_Bit + MOV SP, R0 + SUB R0, R0, #IRQ_Stack_Size + +; Enter Supervisor Mode and set its Stack Pointer + MSR CPSR_c, #Mode_SVC:OR:I_Bit:OR:F_Bit + MOV SP, R0 + SUB R0, R0, #SVC_Stack_Size + +; Enter User Mode and set its Stack Pointer + ; MSR CPSR_c, #Mode_USR + IF :DEF:__MICROLIB + + EXPORT __initial_sp + + ELSE + + ; No usr mode stack here. + ;MOV SP, R0 + ;SUB SL, SP, #USR_Stack_Size + + ENDIF + + +; Enter the C code + + IMPORT __main + LDR R0, =__main + BX R0 + + IMPORT rt_interrupt_enter + IMPORT rt_interrupt_leave + IMPORT rt_thread_switch_interrupt_flag + IMPORT rt_interrupt_from_thread + IMPORT rt_interrupt_to_thread + IMPORT rt_hw_trap_irq + +IRQ_Handler PROC + EXPORT IRQ_Handler + STMFD sp!, {r0-r12,lr} + BL rt_interrupt_enter + BL rt_hw_trap_irq + BL rt_interrupt_leave + + ; if rt_thread_switch_interrupt_flag set, jump to + ; rt_hw_context_switch_interrupt_do and don't return + LDR r0, =rt_thread_switch_interrupt_flag + LDR r1, [r0] + CMP r1, #1 + BEQ rt_hw_context_switch_interrupt_do + + LDMFD sp!, {r0-r12,lr} + SUBS pc, lr, #4 + ENDP + +; /* +; * void rt_hw_context_switch_interrupt_do(rt_base_t flag) +; */ +rt_hw_context_switch_interrupt_do PROC + EXPORT rt_hw_context_switch_interrupt_do + MOV r1, #0 ; clear flag + STR r1, [r0] + + LDMFD sp!, {r0-r12,lr}; reload saved registers + STMFD sp!, {r0-r3} ; save r0-r3 + MOV r1, sp + ADD sp, sp, #16 ; restore sp + SUB r2, lr, #4 ; save old task's pc to r2 + + MRS r3, spsr ; get cpsr of interrupt thread + + ; switch to SVC mode and no interrupt + MSR cpsr_c, #I_Bit|F_Bit|Mode_SVC + + STMFD sp!, {r2} ; push old task's pc + STMFD sp!, {r4-r12,lr}; push old task's lr,r12-r4 + MOV r4, r1 ; Special optimised code below + MOV r5, r3 + LDMFD r4!, {r0-r3} + STMFD sp!, {r0-r3} ; push old task's r3-r0 + STMFD sp!, {r5} ; push old task's cpsr + MRS r4, spsr + STMFD sp!, {r4} ; push old task's spsr + + LDR r4, =rt_interrupt_from_thread + LDR r5, [r4] + STR sp, [r5] ; store sp in preempted tasks's TCB + + LDR r6, =rt_interrupt_to_thread + LDR r6, [r6] + LDR sp, [r6] ; get new task's stack pointer + + LDMFD sp!, {r4} ; pop new task's spsr + MSR spsr_cxsf, r4 + LDMFD sp!, {r4} ; pop new task's psr + MSR cpsr_cxsf, r4 + + LDMFD sp!, {r0-r12,lr,pc} ; pop new task's r0-r12,lr & pc + ENDP + + IF :DEF:__MICROLIB + + EXPORT __heap_base + EXPORT __heap_limit + + ELSE +; User Initial Stack & Heap + AREA |.text|, CODE, READONLY + + IMPORT __use_two_region_memory + EXPORT __user_initial_stackheap +__user_initial_stackheap + + LDR R0, = Heap_Mem + LDR R1, = (Stack_Mem + IRQ_Stack_Size) + LDR R2, = (Heap_Mem + Heap_Size) + LDR R3, = Stack_Mem + BX LR + ENDIF + + END diff --git a/libcpu/arm/AT91SAM7X/start_rvds.S b/libcpu/arm/AT91SAM7X/start_rvds.S index eaee2a39ea..976096563c 100644 --- a/libcpu/arm/AT91SAM7X/start_rvds.S +++ b/libcpu/arm/AT91SAM7X/start_rvds.S @@ -1,517 +1,517 @@ -;/*****************************************************************************/
-;/* SAM7.S: Startup file for Atmel AT91SAM7 device series */
-;/*****************************************************************************/
-;/* <<< Use Configuration Wizard in Context Menu >>> */
-;/*****************************************************************************/
-;/* This file is part of the uVision/ARM development tools. */
-;/* Copyright (c) 2005-2006 Keil Software. All rights reserved. */
-;/* This software may only be used under the terms of a valid, current, */
-;/* end user licence from KEIL for a compatible version of KEIL software */
-;/* development tools. Nothing else gives you the right to use this software. */
-;/*****************************************************************************/
-
-
-;/*
-; * The SAM7.S code is executed after CPU Reset. This file may be
-; * translated with the following SET symbols. In uVision these SET
-; * symbols are entered under Options - ASM - Define.
-; *
-; * REMAP: when set the startup code remaps exception vectors from
-; * on-chip RAM to address 0.
-; *
-; * RAM_INTVEC: when set the startup code copies exception vectors
-; * from on-chip Flash to on-chip RAM.
-; */
-
-
-; Standard definitions of Mode bits and Interrupt (I & F) flags in PSRs
-
-; 2009-12-28 MingBai Bug fix (USR mode stack removed).
-; 2009-12-29 MingBai Merge svc and irq stack, add abort handler.
-
-Mode_USR EQU 0x10
-Mode_FIQ EQU 0x11
-Mode_IRQ EQU 0x12
-Mode_SVC EQU 0x13
-Mode_ABT EQU 0x17
-Mode_UND EQU 0x1B
-Mode_SYS EQU 0x1F
-
-I_Bit EQU 0x80 ; when I bit is set, IRQ is disabled
-F_Bit EQU 0x40 ; when F bit is set, FIQ is disabled
-
-
-; Internal Memory Base Addresses
-FLASH_BASE EQU 0x00100000
-RAM_BASE EQU 0x00200000
-
-
-;// <h> Stack Configuration (Stack Sizes in Bytes)
-;// <o0> Undefined Mode <0x0-0xFFFFFFFF:8>
-;// <o1> Supervisor Mode <0x0-0xFFFFFFFF:8>
-;// <o2> Abort Mode <0x0-0xFFFFFFFF:8>
-;// <o3> Fast Interrupt Mode <0x0-0xFFFFFFFF:8>
-;// <o4> Interrupt Mode <0x0-0xFFFFFFFF:8>
-;// <o5> User/System Mode <0x0-0xFFFFFFFF:8>
-;// </h>
-
-UND_Stack_Size EQU 0x00000000
-SVC_Stack_Size EQU 0x00000000
-ABT_Stack_Size EQU 0x00000000
-FIQ_Stack_Size EQU 0x00000000
-IRQ_Stack_Size EQU 0x00000100
-USR_Stack_Size EQU 0x00000000
-
-ISR_Stack_Size EQU (UND_Stack_Size + SVC_Stack_Size + ABT_Stack_Size + \
- FIQ_Stack_Size + IRQ_Stack_Size)
-
- AREA STACK, NOINIT, READWRITE, ALIGN=3
-
-Stack_Mem SPACE USR_Stack_Size
-__initial_sp SPACE ISR_Stack_Size
-Stack_Top
-
-
-;// <h> Heap Configuration
-;// <o> Heap Size (in Bytes) <0x0-0xFFFFFFFF>
-;// </h>
-
-Heap_Size EQU 0x00000000
-
- AREA HEAP, NOINIT, READWRITE, ALIGN=3
-__heap_base
-Heap_Mem SPACE Heap_Size
-__heap_limit
-
-
-; Reset Controller (RSTC) definitions
-RSTC_BASE EQU 0xFFFFFD00 ; RSTC Base Address
-RSTC_MR EQU 0x08 ; RSTC_MR Offset
-
-;/*
-;// <e> Reset Controller (RSTC)
-;// <o1.0> URSTEN: User Reset Enable
-;// <i> Enables NRST Pin to generate Reset
-;// <o1.8..11> ERSTL: External Reset Length <0-15>
-;// <i> External Reset Time in 2^(ERSTL+1) Slow Clock Cycles
-;// </e>
-;*/
-RSTC_SETUP EQU 1
-RSTC_MR_Val EQU 0xA5000401
-
-
-; Embedded Flash Controller (EFC) definitions
-EFC_BASE EQU 0xFFFFFF00 ; EFC Base Address
-EFC0_FMR EQU 0x60 ; EFC0_FMR Offset
-EFC1_FMR EQU 0x70 ; EFC1_FMR Offset
-
-;// <e> Embedded Flash Controller 0 (EFC0)
-;// <o1.16..23> FMCN: Flash Microsecond Cycle Number <0-255>
-;// <i> Number of Master Clock Cycles in 1us
-;// <o1.8..9> FWS: Flash Wait State
-;// <0=> Read: 1 cycle / Write: 2 cycles
-;// <1=> Read: 2 cycle / Write: 3 cycles
-;// <2=> Read: 3 cycle / Write: 4 cycles
-;// <3=> Read: 4 cycle / Write: 4 cycles
-;// </e>
-EFC0_SETUP EQU 1
-EFC0_FMR_Val EQU 0x00320100
-
-;// <e> Embedded Flash Controller 1 (EFC1)
-;// <o1.16..23> FMCN: Flash Microsecond Cycle Number <0-255>
-;// <i> Number of Master Clock Cycles in 1us
-;// <o1.8..9> FWS: Flash Wait State
-;// <0=> Read: 1 cycle / Write: 2 cycles
-;// <1=> Read: 2 cycle / Write: 3 cycles
-;// <2=> Read: 3 cycle / Write: 4 cycles
-;// <3=> Read: 4 cycle / Write: 4 cycles
-;// </e>
-EFC1_SETUP EQU 0
-EFC1_FMR_Val EQU 0x00320100
-
-
-; Watchdog Timer (WDT) definitions
-WDT_BASE EQU 0xFFFFFD40 ; WDT Base Address
-WDT_MR EQU 0x04 ; WDT_MR Offset
-
-;// <e> Watchdog Timer (WDT)
-;// <o1.0..11> WDV: Watchdog Counter Value <0-4095>
-;// <o1.16..27> WDD: Watchdog Delta Value <0-4095>
-;// <o1.12> WDFIEN: Watchdog Fault Interrupt Enable
-;// <o1.13> WDRSTEN: Watchdog Reset Enable
-;// <o1.14> WDRPROC: Watchdog Reset Processor
-;// <o1.28> WDDBGHLT: Watchdog Debug Halt
-;// <o1.29> WDIDLEHLT: Watchdog Idle Halt
-;// <o1.15> WDDIS: Watchdog Disable
-;// </e>
-WDT_SETUP EQU 1
-WDT_MR_Val EQU 0x00008000
-
-
-; Power Mangement Controller (PMC) definitions
-PMC_BASE EQU 0xFFFFFC00 ; PMC Base Address
-PMC_MOR EQU 0x20 ; PMC_MOR Offset
-PMC_MCFR EQU 0x24 ; PMC_MCFR Offset
-PMC_PLLR EQU 0x2C ; PMC_PLLR Offset
-PMC_MCKR EQU 0x30 ; PMC_MCKR Offset
-PMC_SR EQU 0x68 ; PMC_SR Offset
-PMC_MOSCEN EQU (1<<0) ; Main Oscillator Enable
-PMC_OSCBYPASS EQU (1<<1) ; Main Oscillator Bypass
-PMC_OSCOUNT EQU (0xFF<<8) ; Main OScillator Start-up Time
-PMC_DIV EQU (0xFF<<0) ; PLL Divider
-PMC_PLLCOUNT EQU (0x3F<<8) ; PLL Lock Counter
-PMC_OUT EQU (0x03<<14) ; PLL Clock Frequency Range
-PMC_MUL EQU (0x7FF<<16) ; PLL Multiplier
-PMC_USBDIV EQU (0x03<<28) ; USB Clock Divider
-PMC_CSS EQU (3<<0) ; Clock Source Selection
-PMC_PRES EQU (7<<2) ; Prescaler Selection
-PMC_MOSCS EQU (1<<0) ; Main Oscillator Stable
-PMC_LOCK EQU (1<<2) ; PLL Lock Status
-PMC_MCKRDY EQU (1<<3) ; Master Clock Status
-
-;// <e> Power Mangement Controller (PMC)
-;// <h> Main Oscillator
-;// <o1.0> MOSCEN: Main Oscillator Enable
-;// <o1.1> OSCBYPASS: Oscillator Bypass
-;// <o1.8..15> OSCCOUNT: Main Oscillator Startup Time <0-255>
-;// </h>
-;// <h> Phase Locked Loop (PLL)
-;// <o2.0..7> DIV: PLL Divider <0-255>
-;// <o2.16..26> MUL: PLL Multiplier <0-2047>
-;// <i> PLL Output is multiplied by MUL+1
-;// <o2.14..15> OUT: PLL Clock Frequency Range
-;// <0=> 80..160MHz <1=> Reserved
-;// <2=> 150..220MHz <3=> Reserved
-;// <o2.8..13> PLLCOUNT: PLL Lock Counter <0-63>
-;// <o2.28..29> USBDIV: USB Clock Divider
-;// <0=> None <1=> 2 <2=> 4 <3=> Reserved
-;// </h>
-;// <o3.0..1> CSS: Clock Source Selection
-;// <0=> Slow Clock
-;// <1=> Main Clock
-;// <2=> Reserved
-;// <3=> PLL Clock
-;// <o3.2..4> PRES: Prescaler
-;// <0=> None
-;// <1=> Clock / 2 <2=> Clock / 4
-;// <3=> Clock / 8 <4=> Clock / 16
-;// <5=> Clock / 32 <6=> Clock / 64
-;// <7=> Reserved
-;// </e>
-PMC_SETUP EQU 1
-PMC_MOR_Val EQU 0x00000601
-PMC_PLLR_Val EQU 0x00191C05
-PMC_MCKR_Val EQU 0x00000007
-
-
- PRESERVE8
-
-
-; Area Definition and Entry Point
-; Startup Code must be linked first at Address at which it expects to run.
-
- AREA RESET, CODE, READONLY
- ARM
-
-
-; Exception Vectors
-; Mapped to Address 0.
-; Absolute addressing mode must be used.
-; Dummy Handlers are implemented as infinite loops which can be modified.
-
-Vectors LDR PC,Reset_Addr
- LDR PC,Undef_Addr
- LDR PC,SWI_Addr
- LDR PC,PAbt_Addr
- LDR PC,DAbt_Addr
- NOP ; Reserved Vector
- LDR PC,IRQ_Addr
- LDR PC,FIQ_Addr
-
-Reset_Addr DCD Reset_Handler
-Undef_Addr DCD Undef_Handler
-SWI_Addr DCD SWI_Handler
-PAbt_Addr DCD PAbt_Handler
-DAbt_Addr DCD DAbt_Handler
- DCD 0 ; Reserved Address
-IRQ_Addr DCD IRQ_Handler
-FIQ_Addr DCD FIQ_Handler
-
-Undef_Handler B Undef_Handler
-SWI_Handler B SWI_Handler
-PAbt_Handler B Abort_Handler
-DAbt_Handler B Abort_Handler
-FIQ_Handler B FIQ_Handler
-
-
-; Reset Handler
-
- EXPORT Reset_Handler
-Reset_Handler
-
-
-; Setup RSTC
- IF RSTC_SETUP != 0
- LDR R0, =RSTC_BASE
- LDR R1, =RSTC_MR_Val
- STR R1, [R0, #RSTC_MR]
- ENDIF
-
-
-; Setup EFC0
- IF EFC0_SETUP != 0
- LDR R0, =EFC_BASE
- LDR R1, =EFC0_FMR_Val
- STR R1, [R0, #EFC0_FMR]
- ENDIF
-
-; Setup EFC1
- IF EFC1_SETUP != 0
- LDR R0, =EFC_BASE
- LDR R1, =EFC1_FMR_Val
- STR R1, [R0, #EFC1_FMR]
- ENDIF
-
-; Setup WDT
- IF WDT_SETUP != 0
- LDR R0, =WDT_BASE
- LDR R1, =WDT_MR_Val
- STR R1, [R0, #WDT_MR]
- ENDIF
-
-
-; Setup PMC
- IF PMC_SETUP != 0
- LDR R0, =PMC_BASE
-
-; Setup Main Oscillator
- LDR R1, =PMC_MOR_Val
- STR R1, [R0, #PMC_MOR]
-
-; Wait until Main Oscillator is stablilized
- IF (PMC_MOR_Val:AND:PMC_MOSCEN) != 0
-MOSCS_Loop LDR R2, [R0, #PMC_SR]
- ANDS R2, R2, #PMC_MOSCS
- BEQ MOSCS_Loop
- ENDIF
-
-; Setup the PLL
- IF (PMC_PLLR_Val:AND:PMC_MUL) != 0
- LDR R1, =PMC_PLLR_Val
- STR R1, [R0, #PMC_PLLR]
-
-; Wait until PLL is stabilized
-PLL_Loop LDR R2, [R0, #PMC_SR]
- ANDS R2, R2, #PMC_LOCK
- BEQ PLL_Loop
- ENDIF
-
-; Select Clock
- IF (PMC_MCKR_Val:AND:PMC_CSS) == 1 ; Main Clock Selected
- LDR R1, =PMC_MCKR_Val
- AND R1, #PMC_CSS
- STR R1, [R0, #PMC_MCKR]
-WAIT_Rdy1 LDR R2, [R0, #PMC_SR]
- ANDS R2, R2, #PMC_MCKRDY
- BEQ WAIT_Rdy1
- LDR R1, =PMC_MCKR_Val
- STR R1, [R0, #PMC_MCKR]
-WAIT_Rdy2 LDR R2, [R0, #PMC_SR]
- ANDS R2, R2, #PMC_MCKRDY
- BEQ WAIT_Rdy2
- ELIF (PMC_MCKR_Val:AND:PMC_CSS) == 3 ; PLL Clock Selected
- LDR R1, =PMC_MCKR_Val
- AND R1, #PMC_PRES
- STR R1, [R0, #PMC_MCKR]
-WAIT_Rdy1 LDR R2, [R0, #PMC_SR]
- ANDS R2, R2, #PMC_MCKRDY
- BEQ WAIT_Rdy1
- LDR R1, =PMC_MCKR_Val
- STR R1, [R0, #PMC_MCKR]
-WAIT_Rdy2 LDR R2, [R0, #PMC_SR]
- ANDS R2, R2, #PMC_MCKRDY
- BEQ WAIT_Rdy2
- ENDIF ; Select Clock
- ENDIF ; PMC_SETUP
-
-
-; Copy Exception Vectors to Internal RAM
-
- IF :DEF:RAM_INTVEC
- ADR R8, Vectors ; Source
- LDR R9, =RAM_BASE ; Destination
- LDMIA R8!, {R0-R7} ; Load Vectors
- STMIA R9!, {R0-R7} ; Store Vectors
- LDMIA R8!, {R0-R7} ; Load Handler Addresses
- STMIA R9!, {R0-R7} ; Store Handler Addresses
- ENDIF
-
-
-; Remap on-chip RAM to address 0
-
-MC_BASE EQU 0xFFFFFF00 ; MC Base Address
-MC_RCR EQU 0x00 ; MC_RCR Offset
-
- IF :DEF:REMAP
- LDR R0, =MC_BASE
- MOV R1, #1
- STR R1, [R0, #MC_RCR] ; Remap
- ENDIF
-
-
-; Setup Stack for each mode
-
- LDR R0, =Stack_Top
-
-; Enter Undefined Instruction Mode and set its Stack Pointer
- MSR CPSR_c, #Mode_UND:OR:I_Bit:OR:F_Bit
- MOV SP, R0
- ;SUB R0, R0, #UND_Stack_Size
-
-; Enter Abort Mode and set its Stack Pointer
- MSR CPSR_c, #Mode_ABT:OR:I_Bit:OR:F_Bit
- MOV SP, R0
- ;SUB R0, R0, #ABT_Stack_Size
-
-; Enter FIQ Mode and set its Stack Pointer
- MSR CPSR_c, #Mode_FIQ:OR:I_Bit:OR:F_Bit
- MOV SP, R0
- ;SUB R0, R0, #FIQ_Stack_Size
-
-; Enter IRQ Mode and set its Stack Pointer
- MSR CPSR_c, #Mode_IRQ:OR:I_Bit:OR:F_Bit
- MOV SP, R0
- ;SUB R0, R0, #IRQ_Stack_Size
-
-; Enter Supervisor Mode and set its Stack Pointer
- MSR CPSR_c, #Mode_SVC:OR:I_Bit:OR:F_Bit
- MOV SP, R0
- ; SUB R0, R0, #SVC_Stack_Size
-
-; Enter User Mode and set its Stack Pointer
- ; MSR CPSR_c, #Mode_USR
- IF :DEF:__MICROLIB
-
- EXPORT __initial_sp
-
- ELSE
-
- ; No usr mode stack here.
- ;MOV SP, R0
- ;SUB SL, SP, #USR_Stack_Size
-
- ENDIF
-
-
-; Enter the C code
-
- IMPORT __main
- LDR R0, =__main
- BX R0
-
- IMPORT rt_interrupt_enter
- IMPORT rt_interrupt_leave
- IMPORT rt_thread_switch_interrupt_flag
- IMPORT rt_interrupt_from_thread
- IMPORT rt_interrupt_to_thread
- IMPORT rt_hw_trap_irq
- IMPORT rt_hw_trap_abort
- IMPORT rt_interrupt_nest
-
-Abort_Handler PROC
- EXPORT Abort_Handler
- stmfd sp!, {r0-r12,lr}
- LDR r0, =rt_interrupt_nest
- LDR r1, [r0]
- CMP r1, #0
-DeadLoop BHI DeadLoop ; Abort happened in irq mode, halt system.
- bl rt_interrupt_enter
- bl rt_hw_trap_abort
- bl rt_interrupt_leave
- b SWITCH
- ENDP
-
-IRQ_Handler PROC
- EXPORT IRQ_Handler
- STMFD sp!, {r0-r12,lr}
- BL rt_interrupt_enter
- BL rt_hw_trap_irq
- BL rt_interrupt_leave
-
- ; if rt_thread_switch_interrupt_flag set, jump to
- ; rt_hw_context_switch_interrupt_do and don't return
-SWITCH LDR r0, =rt_thread_switch_interrupt_flag
- LDR r1, [r0]
- CMP r1, #1
- BEQ rt_hw_context_switch_interrupt_do
-
- LDMFD sp!, {r0-r12,lr}
- SUBS pc, lr, #4
- ENDP
-
-; /*
-; * void rt_hw_context_switch_interrupt_do(rt_base_t flag)
-; */
-rt_hw_context_switch_interrupt_do PROC
- EXPORT rt_hw_context_switch_interrupt_do
- MOV r1, #0 ; clear flag
- STR r1, [r0]
-
- LDMFD sp!, {r0-r12,lr}; reload saved registers
- STMFD sp!, {r0-r3} ; save r0-r3
- MOV r1, sp
- ADD sp, sp, #16 ; restore sp
- SUB r2, lr, #4 ; save old task's pc to r2
-
- MRS r3, spsr ; get cpsr of interrupt thread
-
- ; switch to SVC mode and no interrupt
- MSR cpsr_c, #I_Bit|F_Bit|Mode_SVC
-
- STMFD sp!, {r2} ; push old task's pc
- STMFD sp!, {r4-r12,lr}; push old task's lr,r12-r4
- MOV r4, r1 ; Special optimised code below
- MOV r5, r3
- LDMFD r4!, {r0-r3}
- STMFD sp!, {r0-r3} ; push old task's r3-r0
- STMFD sp!, {r5} ; push old task's cpsr
- MRS r4, spsr
- STMFD sp!, {r4} ; push old task's spsr
-
- LDR r4, =rt_interrupt_from_thread
- LDR r5, [r4]
- STR sp, [r5] ; store sp in preempted tasks's TCB
-
- LDR r6, =rt_interrupt_to_thread
- LDR r6, [r6]
- LDR sp, [r6] ; get new task's stack pointer
-
- LDMFD sp!, {r4} ; pop new task's spsr
- MSR spsr_cxsf, r4
- LDMFD sp!, {r4} ; pop new task's psr
- MSR cpsr_cxsf, r4
-
- LDMFD sp!, {r0-r12,lr,pc} ; pop new task's r0-r12,lr & pc
- ENDP
-
- IF :DEF:__MICROLIB
-
- EXPORT __heap_base
- EXPORT __heap_limit
-
- ELSE
-; User Initial Stack & Heap
- AREA |.text|, CODE, READONLY
-
- IMPORT __use_two_region_memory
- EXPORT __user_initial_stackheap
-__user_initial_stackheap
-
- LDR R0, = Heap_Mem
- LDR R1, = (Stack_Mem + IRQ_Stack_Size)
- LDR R2, = (Heap_Mem + Heap_Size)
- LDR R3, = Stack_Mem
- BX LR
- ENDIF
-
- END
+;/*****************************************************************************/ +;/* SAM7.S: Startup file for Atmel AT91SAM7 device series */ +;/*****************************************************************************/ +;/* <<< Use Configuration Wizard in Context Menu >>> */ +;/*****************************************************************************/ +;/* This file is part of the uVision/ARM development tools. */ +;/* Copyright (c) 2005-2006 Keil Software. All rights reserved. */ +;/* This software may only be used under the terms of a valid, current, */ +;/* end user licence from KEIL for a compatible version of KEIL software */ +;/* development tools. Nothing else gives you the right to use this software. */ +;/*****************************************************************************/ + + +;/* +; * The SAM7.S code is executed after CPU Reset. This file may be +; * translated with the following SET symbols. In uVision these SET +; * symbols are entered under Options - ASM - Define. +; * +; * REMAP: when set the startup code remaps exception vectors from +; * on-chip RAM to address 0. +; * +; * RAM_INTVEC: when set the startup code copies exception vectors +; * from on-chip Flash to on-chip RAM. +; */ + + +; Standard definitions of Mode bits and Interrupt (I & F) flags in PSRs + +; 2009-12-28 MingBai Bug fix (USR mode stack removed). +; 2009-12-29 MingBai Merge svc and irq stack, add abort handler. + +Mode_USR EQU 0x10 +Mode_FIQ EQU 0x11 +Mode_IRQ EQU 0x12 +Mode_SVC EQU 0x13 +Mode_ABT EQU 0x17 +Mode_UND EQU 0x1B +Mode_SYS EQU 0x1F + +I_Bit EQU 0x80 ; when I bit is set, IRQ is disabled +F_Bit EQU 0x40 ; when F bit is set, FIQ is disabled + + +; Internal Memory Base Addresses +FLASH_BASE EQU 0x00100000 +RAM_BASE EQU 0x00200000 + + +;// <h> Stack Configuration (Stack Sizes in Bytes) +;// <o0> Undefined Mode <0x0-0xFFFFFFFF:8> +;// <o1> Supervisor Mode <0x0-0xFFFFFFFF:8> +;// <o2> Abort Mode <0x0-0xFFFFFFFF:8> +;// <o3> Fast Interrupt Mode <0x0-0xFFFFFFFF:8> +;// <o4> Interrupt Mode <0x0-0xFFFFFFFF:8> +;// <o5> User/System Mode <0x0-0xFFFFFFFF:8> +;// </h> + +UND_Stack_Size EQU 0x00000000 +SVC_Stack_Size EQU 0x00000000 +ABT_Stack_Size EQU 0x00000000 +FIQ_Stack_Size EQU 0x00000000 +IRQ_Stack_Size EQU 0x00000100 +USR_Stack_Size EQU 0x00000000 + +ISR_Stack_Size EQU (UND_Stack_Size + SVC_Stack_Size + ABT_Stack_Size + \ + FIQ_Stack_Size + IRQ_Stack_Size) + + AREA STACK, NOINIT, READWRITE, ALIGN=3 + +Stack_Mem SPACE USR_Stack_Size +__initial_sp SPACE ISR_Stack_Size +Stack_Top + + +;// <h> Heap Configuration +;// <o> Heap Size (in Bytes) <0x0-0xFFFFFFFF> +;// </h> + +Heap_Size EQU 0x00000000 + + AREA HEAP, NOINIT, READWRITE, ALIGN=3 +__heap_base +Heap_Mem SPACE Heap_Size +__heap_limit + + +; Reset Controller (RSTC) definitions +RSTC_BASE EQU 0xFFFFFD00 ; RSTC Base Address +RSTC_MR EQU 0x08 ; RSTC_MR Offset + +;/* +;// <e> Reset Controller (RSTC) +;// <o1.0> URSTEN: User Reset Enable +;// <i> Enables NRST Pin to generate Reset +;// <o1.8..11> ERSTL: External Reset Length <0-15> +;// <i> External Reset Time in 2^(ERSTL+1) Slow Clock Cycles +;// </e> +;*/ +RSTC_SETUP EQU 1 +RSTC_MR_Val EQU 0xA5000401 + + +; Embedded Flash Controller (EFC) definitions +EFC_BASE EQU 0xFFFFFF00 ; EFC Base Address +EFC0_FMR EQU 0x60 ; EFC0_FMR Offset +EFC1_FMR EQU 0x70 ; EFC1_FMR Offset + +;// <e> Embedded Flash Controller 0 (EFC0) +;// <o1.16..23> FMCN: Flash Microsecond Cycle Number <0-255> +;// <i> Number of Master Clock Cycles in 1us +;// <o1.8..9> FWS: Flash Wait State +;// <0=> Read: 1 cycle / Write: 2 cycles +;// <1=> Read: 2 cycle / Write: 3 cycles +;// <2=> Read: 3 cycle / Write: 4 cycles +;// <3=> Read: 4 cycle / Write: 4 cycles +;// </e> +EFC0_SETUP EQU 1 +EFC0_FMR_Val EQU 0x00320100 + +;// <e> Embedded Flash Controller 1 (EFC1) +;// <o1.16..23> FMCN: Flash Microsecond Cycle Number <0-255> +;// <i> Number of Master Clock Cycles in 1us +;// <o1.8..9> FWS: Flash Wait State +;// <0=> Read: 1 cycle / Write: 2 cycles +;// <1=> Read: 2 cycle / Write: 3 cycles +;// <2=> Read: 3 cycle / Write: 4 cycles +;// <3=> Read: 4 cycle / Write: 4 cycles +;// </e> +EFC1_SETUP EQU 0 +EFC1_FMR_Val EQU 0x00320100 + + +; Watchdog Timer (WDT) definitions +WDT_BASE EQU 0xFFFFFD40 ; WDT Base Address +WDT_MR EQU 0x04 ; WDT_MR Offset + +;// <e> Watchdog Timer (WDT) +;// <o1.0..11> WDV: Watchdog Counter Value <0-4095> +;// <o1.16..27> WDD: Watchdog Delta Value <0-4095> +;// <o1.12> WDFIEN: Watchdog Fault Interrupt Enable +;// <o1.13> WDRSTEN: Watchdog Reset Enable +;// <o1.14> WDRPROC: Watchdog Reset Processor +;// <o1.28> WDDBGHLT: Watchdog Debug Halt +;// <o1.29> WDIDLEHLT: Watchdog Idle Halt +;// <o1.15> WDDIS: Watchdog Disable +;// </e> +WDT_SETUP EQU 1 +WDT_MR_Val EQU 0x00008000 + + +; Power Mangement Controller (PMC) definitions +PMC_BASE EQU 0xFFFFFC00 ; PMC Base Address +PMC_MOR EQU 0x20 ; PMC_MOR Offset +PMC_MCFR EQU 0x24 ; PMC_MCFR Offset +PMC_PLLR EQU 0x2C ; PMC_PLLR Offset +PMC_MCKR EQU 0x30 ; PMC_MCKR Offset +PMC_SR EQU 0x68 ; PMC_SR Offset +PMC_MOSCEN EQU (1<<0) ; Main Oscillator Enable +PMC_OSCBYPASS EQU (1<<1) ; Main Oscillator Bypass +PMC_OSCOUNT EQU (0xFF<<8) ; Main OScillator Start-up Time +PMC_DIV EQU (0xFF<<0) ; PLL Divider +PMC_PLLCOUNT EQU (0x3F<<8) ; PLL Lock Counter +PMC_OUT EQU (0x03<<14) ; PLL Clock Frequency Range +PMC_MUL EQU (0x7FF<<16) ; PLL Multiplier +PMC_USBDIV EQU (0x03<<28) ; USB Clock Divider +PMC_CSS EQU (3<<0) ; Clock Source Selection +PMC_PRES EQU (7<<2) ; Prescaler Selection +PMC_MOSCS EQU (1<<0) ; Main Oscillator Stable +PMC_LOCK EQU (1<<2) ; PLL Lock Status +PMC_MCKRDY EQU (1<<3) ; Master Clock Status + +;// <e> Power Mangement Controller (PMC) +;// <h> Main Oscillator +;// <o1.0> MOSCEN: Main Oscillator Enable +;// <o1.1> OSCBYPASS: Oscillator Bypass +;// <o1.8..15> OSCCOUNT: Main Oscillator Startup Time <0-255> +;// </h> +;// <h> Phase Locked Loop (PLL) +;// <o2.0..7> DIV: PLL Divider <0-255> +;// <o2.16..26> MUL: PLL Multiplier <0-2047> +;// <i> PLL Output is multiplied by MUL+1 +;// <o2.14..15> OUT: PLL Clock Frequency Range +;// <0=> 80..160MHz <1=> Reserved +;// <2=> 150..220MHz <3=> Reserved +;// <o2.8..13> PLLCOUNT: PLL Lock Counter <0-63> +;// <o2.28..29> USBDIV: USB Clock Divider +;// <0=> None <1=> 2 <2=> 4 <3=> Reserved +;// </h> +;// <o3.0..1> CSS: Clock Source Selection +;// <0=> Slow Clock +;// <1=> Main Clock +;// <2=> Reserved +;// <3=> PLL Clock +;// <o3.2..4> PRES: Prescaler +;// <0=> None +;// <1=> Clock / 2 <2=> Clock / 4 +;// <3=> Clock / 8 <4=> Clock / 16 +;// <5=> Clock / 32 <6=> Clock / 64 +;// <7=> Reserved +;// </e> +PMC_SETUP EQU 1 +PMC_MOR_Val EQU 0x00000601 +PMC_PLLR_Val EQU 0x00191C05 +PMC_MCKR_Val EQU 0x00000007 + + + PRESERVE8 + + +; Area Definition and Entry Point +; Startup Code must be linked first at Address at which it expects to run. + + AREA RESET, CODE, READONLY + ARM + + +; Exception Vectors +; Mapped to Address 0. +; Absolute addressing mode must be used. +; Dummy Handlers are implemented as infinite loops which can be modified. + +Vectors LDR PC,Reset_Addr + LDR PC,Undef_Addr + LDR PC,SWI_Addr + LDR PC,PAbt_Addr + LDR PC,DAbt_Addr + NOP ; Reserved Vector + LDR PC,IRQ_Addr + LDR PC,FIQ_Addr + +Reset_Addr DCD Reset_Handler +Undef_Addr DCD Undef_Handler +SWI_Addr DCD SWI_Handler +PAbt_Addr DCD PAbt_Handler +DAbt_Addr DCD DAbt_Handler + DCD 0 ; Reserved Address +IRQ_Addr DCD IRQ_Handler +FIQ_Addr DCD FIQ_Handler + +Undef_Handler B Undef_Handler +SWI_Handler B SWI_Handler +PAbt_Handler B Abort_Handler +DAbt_Handler B Abort_Handler +FIQ_Handler B FIQ_Handler + + +; Reset Handler + + EXPORT Reset_Handler +Reset_Handler + + +; Setup RSTC + IF RSTC_SETUP != 0 + LDR R0, =RSTC_BASE + LDR R1, =RSTC_MR_Val + STR R1, [R0, #RSTC_MR] + ENDIF + + +; Setup EFC0 + IF EFC0_SETUP != 0 + LDR R0, =EFC_BASE + LDR R1, =EFC0_FMR_Val + STR R1, [R0, #EFC0_FMR] + ENDIF + +; Setup EFC1 + IF EFC1_SETUP != 0 + LDR R0, =EFC_BASE + LDR R1, =EFC1_FMR_Val + STR R1, [R0, #EFC1_FMR] + ENDIF + +; Setup WDT + IF WDT_SETUP != 0 + LDR R0, =WDT_BASE + LDR R1, =WDT_MR_Val + STR R1, [R0, #WDT_MR] + ENDIF + + +; Setup PMC + IF PMC_SETUP != 0 + LDR R0, =PMC_BASE + +; Setup Main Oscillator + LDR R1, =PMC_MOR_Val + STR R1, [R0, #PMC_MOR] + +; Wait until Main Oscillator is stablilized + IF (PMC_MOR_Val:AND:PMC_MOSCEN) != 0 +MOSCS_Loop LDR R2, [R0, #PMC_SR] + ANDS R2, R2, #PMC_MOSCS + BEQ MOSCS_Loop + ENDIF + +; Setup the PLL + IF (PMC_PLLR_Val:AND:PMC_MUL) != 0 + LDR R1, =PMC_PLLR_Val + STR R1, [R0, #PMC_PLLR] + +; Wait until PLL is stabilized +PLL_Loop LDR R2, [R0, #PMC_SR] + ANDS R2, R2, #PMC_LOCK + BEQ PLL_Loop + ENDIF + +; Select Clock + IF (PMC_MCKR_Val:AND:PMC_CSS) == 1 ; Main Clock Selected + LDR R1, =PMC_MCKR_Val + AND R1, #PMC_CSS + STR R1, [R0, #PMC_MCKR] +WAIT_Rdy1 LDR R2, [R0, #PMC_SR] + ANDS R2, R2, #PMC_MCKRDY + BEQ WAIT_Rdy1 + LDR R1, =PMC_MCKR_Val + STR R1, [R0, #PMC_MCKR] +WAIT_Rdy2 LDR R2, [R0, #PMC_SR] + ANDS R2, R2, #PMC_MCKRDY + BEQ WAIT_Rdy2 + ELIF (PMC_MCKR_Val:AND:PMC_CSS) == 3 ; PLL Clock Selected + LDR R1, =PMC_MCKR_Val + AND R1, #PMC_PRES + STR R1, [R0, #PMC_MCKR] +WAIT_Rdy1 LDR R2, [R0, #PMC_SR] + ANDS R2, R2, #PMC_MCKRDY + BEQ WAIT_Rdy1 + LDR R1, =PMC_MCKR_Val + STR R1, [R0, #PMC_MCKR] +WAIT_Rdy2 LDR R2, [R0, #PMC_SR] + ANDS R2, R2, #PMC_MCKRDY + BEQ WAIT_Rdy2 + ENDIF ; Select Clock + ENDIF ; PMC_SETUP + + +; Copy Exception Vectors to Internal RAM + + IF :DEF:RAM_INTVEC + ADR R8, Vectors ; Source + LDR R9, =RAM_BASE ; Destination + LDMIA R8!, {R0-R7} ; Load Vectors + STMIA R9!, {R0-R7} ; Store Vectors + LDMIA R8!, {R0-R7} ; Load Handler Addresses + STMIA R9!, {R0-R7} ; Store Handler Addresses + ENDIF + + +; Remap on-chip RAM to address 0 + +MC_BASE EQU 0xFFFFFF00 ; MC Base Address +MC_RCR EQU 0x00 ; MC_RCR Offset + + IF :DEF:REMAP + LDR R0, =MC_BASE + MOV R1, #1 + STR R1, [R0, #MC_RCR] ; Remap + ENDIF + + +; Setup Stack for each mode + + LDR R0, =Stack_Top + +; Enter Undefined Instruction Mode and set its Stack Pointer + MSR CPSR_c, #Mode_UND:OR:I_Bit:OR:F_Bit + MOV SP, R0 + ;SUB R0, R0, #UND_Stack_Size + +; Enter Abort Mode and set its Stack Pointer + MSR CPSR_c, #Mode_ABT:OR:I_Bit:OR:F_Bit + MOV SP, R0 + ;SUB R0, R0, #ABT_Stack_Size + +; Enter FIQ Mode and set its Stack Pointer + MSR CPSR_c, #Mode_FIQ:OR:I_Bit:OR:F_Bit + MOV SP, R0 + ;SUB R0, R0, #FIQ_Stack_Size + +; Enter IRQ Mode and set its Stack Pointer + MSR CPSR_c, #Mode_IRQ:OR:I_Bit:OR:F_Bit + MOV SP, R0 + ;SUB R0, R0, #IRQ_Stack_Size + +; Enter Supervisor Mode and set its Stack Pointer + MSR CPSR_c, #Mode_SVC:OR:I_Bit:OR:F_Bit + MOV SP, R0 + ; SUB R0, R0, #SVC_Stack_Size + +; Enter User Mode and set its Stack Pointer + ; MSR CPSR_c, #Mode_USR + IF :DEF:__MICROLIB + + EXPORT __initial_sp + + ELSE + + ; No usr mode stack here. + ;MOV SP, R0 + ;SUB SL, SP, #USR_Stack_Size + + ENDIF + + +; Enter the C code + + IMPORT __main + LDR R0, =__main + BX R0 + + IMPORT rt_interrupt_enter + IMPORT rt_interrupt_leave + IMPORT rt_thread_switch_interrupt_flag + IMPORT rt_interrupt_from_thread + IMPORT rt_interrupt_to_thread + IMPORT rt_hw_trap_irq + IMPORT rt_hw_trap_abort + IMPORT rt_interrupt_nest + +Abort_Handler PROC + EXPORT Abort_Handler + stmfd sp!, {r0-r12,lr} + LDR r0, =rt_interrupt_nest + LDR r1, [r0] + CMP r1, #0 +DeadLoop BHI DeadLoop ; Abort happened in irq mode, halt system. + bl rt_interrupt_enter + bl rt_hw_trap_abort + bl rt_interrupt_leave + b SWITCH + ENDP + +IRQ_Handler PROC + EXPORT IRQ_Handler + STMFD sp!, {r0-r12,lr} + BL rt_interrupt_enter + BL rt_hw_trap_irq + BL rt_interrupt_leave + + ; if rt_thread_switch_interrupt_flag set, jump to + ; rt_hw_context_switch_interrupt_do and don't return +SWITCH LDR r0, =rt_thread_switch_interrupt_flag + LDR r1, [r0] + CMP r1, #1 + BEQ rt_hw_context_switch_interrupt_do + + LDMFD sp!, {r0-r12,lr} + SUBS pc, lr, #4 + ENDP + +; /* +; * void rt_hw_context_switch_interrupt_do(rt_base_t flag) +; */ +rt_hw_context_switch_interrupt_do PROC + EXPORT rt_hw_context_switch_interrupt_do + MOV r1, #0 ; clear flag + STR r1, [r0] + + LDMFD sp!, {r0-r12,lr}; reload saved registers + STMFD sp!, {r0-r3} ; save r0-r3 + MOV r1, sp + ADD sp, sp, #16 ; restore sp + SUB r2, lr, #4 ; save old task's pc to r2 + + MRS r3, spsr ; get cpsr of interrupt thread + + ; switch to SVC mode and no interrupt + MSR cpsr_c, #I_Bit|F_Bit|Mode_SVC + + STMFD sp!, {r2} ; push old task's pc + STMFD sp!, {r4-r12,lr}; push old task's lr,r12-r4 + MOV r4, r1 ; Special optimised code below + MOV r5, r3 + LDMFD r4!, {r0-r3} + STMFD sp!, {r0-r3} ; push old task's r3-r0 + STMFD sp!, {r5} ; push old task's cpsr + MRS r4, spsr + STMFD sp!, {r4} ; push old task's spsr + + LDR r4, =rt_interrupt_from_thread + LDR r5, [r4] + STR sp, [r5] ; store sp in preempted tasks's TCB + + LDR r6, =rt_interrupt_to_thread + LDR r6, [r6] + LDR sp, [r6] ; get new task's stack pointer + + LDMFD sp!, {r4} ; pop new task's spsr + MSR spsr_cxsf, r4 + LDMFD sp!, {r4} ; pop new task's psr + MSR cpsr_cxsf, r4 + + LDMFD sp!, {r0-r12,lr,pc} ; pop new task's r0-r12,lr & pc + ENDP + + IF :DEF:__MICROLIB + + EXPORT __heap_base + EXPORT __heap_limit + + ELSE +; User Initial Stack & Heap + AREA |.text|, CODE, READONLY + + IMPORT __use_two_region_memory + EXPORT __user_initial_stackheap +__user_initial_stackheap + + LDR R0, = Heap_Mem + LDR R1, = (Stack_Mem + IRQ_Stack_Size) + LDR R2, = (Heap_Mem + Heap_Size) + LDR R3, = Stack_Mem + BX LR + ENDIF + + END diff --git a/libcpu/arm/AT91SAM7X/trap.c b/libcpu/arm/AT91SAM7X/trap.c index 8bc0559d23..2e137fc009 100644 --- a/libcpu/arm/AT91SAM7X/trap.c +++ b/libcpu/arm/AT91SAM7X/trap.c @@ -36,12 +36,12 @@ void rt_hw_trap_fiq() { rt_kprintf("fast interrupt request\n"); } -
+ extern struct rt_thread* rt_current_thread; void rt_hw_trap_abort() -{
- rt_kprintf("Abort occured!!! Thread [%s] suspended.\n",rt_current_thread->name);
- rt_thread_suspend(rt_current_thread);
+{ + rt_kprintf("Abort occured!!! Thread [%s] suspended.\n",rt_current_thread->name); + rt_thread_suspend(rt_current_thread); rt_schedule(); } diff --git a/libcpu/arm/at91sam926x/cpu.c b/libcpu/arm/at91sam926x/cpu.c index fff3e59b34..abda8deb29 100755 --- a/libcpu/arm/at91sam926x/cpu.c +++ b/libcpu/arm/at91sam926x/cpu.c @@ -1,193 +1,193 @@ -/*
- * File : cpu.c
- * This file is part of RT-Thread RTOS
- * COPYRIGHT (C) 2006, RT-Thread Develop Team
- *
- * The license and distribution terms for this file may be
- * found in the file LICENSE in this distribution or at
- * http://openlab.rt-thread.com/license/LICENSE
- *
- * Change Logs:
- * Date Author Notes
- * 2011-01-13 weety modified from mini2440
- */
-
-#include <rthw.h>
-#include <rtthread.h>
-#include "at91sam926x.h"
-
-/**
- * @addtogroup AT91SAM926X
- */
-/*@{*/
-
-#define ICACHE_MASK (rt_uint32_t)(1 << 12)
-#define DCACHE_MASK (rt_uint32_t)(1 << 2)
-
-#ifdef __GNUC__
-rt_inline rt_uint32_t cp15_rd(void)
-{
- rt_uint32_t i;
-
- asm ("mrc p15, 0, %0, c1, c0, 0":"=r" (i));
- return i;
-}
-
-rt_inline void cache_enable(rt_uint32_t bit)
-{
- __asm__ __volatile__( \
- "mrc p15,0,r0,c1,c0,0\n\t" \
- "orr r0,r0,%0\n\t" \
- "mcr p15,0,r0,c1,c0,0" \
- : \
- :"r" (bit) \
- :"memory");
-}
-
-rt_inline void cache_disable(rt_uint32_t bit)
-{
- __asm__ __volatile__( \
- "mrc p15,0,r0,c1,c0,0\n\t" \
- "bic r0,r0,%0\n\t" \
- "mcr p15,0,r0,c1,c0,0" \
- : \
- :"r" (bit) \
- :"memory");
-}
-#endif
-
-#ifdef __CC_ARM
-rt_inline rt_uint32_t cp15_rd(void)
-{
- rt_uint32_t i;
-
- __asm
- {
- mrc p15, 0, i, c1, c0, 0
- }
-
- return i;
-}
-
-rt_inline void cache_enable(rt_uint32_t bit)
-{
- rt_uint32_t value;
-
- __asm
- {
- mrc p15, 0, value, c1, c0, 0
- orr value, value, bit
- mcr p15, 0, value, c1, c0, 0
- }
-}
-
-rt_inline void cache_disable(rt_uint32_t bit)
-{
- rt_uint32_t value;
-
- __asm
- {
- mrc p15, 0, value, c1, c0, 0
- bic value, value, bit
- mcr p15, 0, value, c1, c0, 0
- }
-}
-#endif
-
-/**
- * enable I-Cache
- *
- */
-void rt_hw_cpu_icache_enable()
-{
- cache_enable(ICACHE_MASK);
-}
-
-/**
- * disable I-Cache
- *
- */
-void rt_hw_cpu_icache_disable()
-{
- cache_disable(ICACHE_MASK);
-}
-
-/**
- * return the status of I-Cache
- *
- */
-rt_base_t rt_hw_cpu_icache_status()
-{
- return (cp15_rd() & ICACHE_MASK);
-}
-
-/**
- * enable D-Cache
- *
- */
-void rt_hw_cpu_dcache_enable()
-{
- cache_enable(DCACHE_MASK);
-}
-
-/**
- * disable D-Cache
- *
- */
-void rt_hw_cpu_dcache_disable()
-{
- cache_disable(DCACHE_MASK);
-}
-
-/**
- * return the status of D-Cache
- *
- */
-rt_base_t rt_hw_cpu_dcache_status()
-{
- return (cp15_rd() & DCACHE_MASK);
-}
-
-static void at91sam9260_reset(void)
-{
- at91_sys_write(AT91_RSTC_CR, AT91_RSTC_KEY | AT91_RSTC_PROCRST | AT91_RSTC_PERRST);
-}
-
-static void at91sam9260_poweroff(void)
-{
- at91_sys_write(AT91_SHDW_CR, AT91_SHDW_KEY | AT91_SHDW_SHDW);
-}
-
-/**
- * reset cpu by dog's time-out
- *
- */
-void rt_hw_cpu_reset()
-{
-
- rt_kprintf("Restarting system...\n");
- at91sam9260_reset();
-
- while(1); /* loop forever and wait for reset to happen */
-
- /* NEVER REACHED */
-}
-
-/**
- * shutdown CPU
- *
- */
-void rt_hw_cpu_shutdown()
-{
- rt_uint32_t level;
- rt_kprintf("shutdown...\n");
-
- level = rt_hw_interrupt_disable();
- at91sam9260_poweroff();
- while (level)
- {
- RT_ASSERT(0);
- }
-}
-
-/*@}*/
+/* + * File : cpu.c + * This file is part of RT-Thread RTOS + * COPYRIGHT (C) 2006, RT-Thread Develop Team + * + * The license and distribution terms for this file may be + * found in the file LICENSE in this distribution or at + * http://openlab.rt-thread.com/license/LICENSE + * + * Change Logs: + * Date Author Notes + * 2011-01-13 weety modified from mini2440 + */ + +#include <rthw.h> +#include <rtthread.h> +#include "at91sam926x.h" + +/** + * @addtogroup AT91SAM926X + */ +/*@{*/ + +#define ICACHE_MASK (rt_uint32_t)(1 << 12) +#define DCACHE_MASK (rt_uint32_t)(1 << 2) + +#ifdef __GNUC__ +rt_inline rt_uint32_t cp15_rd(void) +{ + rt_uint32_t i; + + asm ("mrc p15, 0, %0, c1, c0, 0":"=r" (i)); + return i; +} + +rt_inline void cache_enable(rt_uint32_t bit) +{ + __asm__ __volatile__( \ + "mrc p15,0,r0,c1,c0,0\n\t" \ + "orr r0,r0,%0\n\t" \ + "mcr p15,0,r0,c1,c0,0" \ + : \ + :"r" (bit) \ + :"memory"); +} + +rt_inline void cache_disable(rt_uint32_t bit) +{ + __asm__ __volatile__( \ + "mrc p15,0,r0,c1,c0,0\n\t" \ + "bic r0,r0,%0\n\t" \ + "mcr p15,0,r0,c1,c0,0" \ + : \ + :"r" (bit) \ + :"memory"); +} +#endif + +#ifdef __CC_ARM +rt_inline rt_uint32_t cp15_rd(void) +{ + rt_uint32_t i; + + __asm + { + mrc p15, 0, i, c1, c0, 0 + } + + return i; +} + +rt_inline void cache_enable(rt_uint32_t bit) +{ + rt_uint32_t value; + + __asm + { + mrc p15, 0, value, c1, c0, 0 + orr value, value, bit + mcr p15, 0, value, c1, c0, 0 + } +} + +rt_inline void cache_disable(rt_uint32_t bit) +{ + rt_uint32_t value; + + __asm + { + mrc p15, 0, value, c1, c0, 0 + bic value, value, bit + mcr p15, 0, value, c1, c0, 0 + } +} +#endif + +/** + * enable I-Cache + * + */ +void rt_hw_cpu_icache_enable() +{ + cache_enable(ICACHE_MASK); +} + +/** + * disable I-Cache + * + */ +void rt_hw_cpu_icache_disable() +{ + cache_disable(ICACHE_MASK); +} + +/** + * return the status of I-Cache + * + */ +rt_base_t rt_hw_cpu_icache_status() +{ + return (cp15_rd() & ICACHE_MASK); +} + +/** + * enable D-Cache + * + */ +void rt_hw_cpu_dcache_enable() +{ + cache_enable(DCACHE_MASK); +} + +/** + * disable D-Cache + * + */ +void rt_hw_cpu_dcache_disable() +{ + cache_disable(DCACHE_MASK); +} + +/** + * return the status of D-Cache + * + */ +rt_base_t rt_hw_cpu_dcache_status() +{ + return (cp15_rd() & DCACHE_MASK); +} + +static void at91sam9260_reset(void) +{ + at91_sys_write(AT91_RSTC_CR, AT91_RSTC_KEY | AT91_RSTC_PROCRST | AT91_RSTC_PERRST); +} + +static void at91sam9260_poweroff(void) +{ + at91_sys_write(AT91_SHDW_CR, AT91_SHDW_KEY | AT91_SHDW_SHDW); +} + +/** + * reset cpu by dog's time-out + * + */ +void rt_hw_cpu_reset() +{ + + rt_kprintf("Restarting system...\n"); + at91sam9260_reset(); + + while(1); /* loop forever and wait for reset to happen */ + + /* NEVER REACHED */ +} + +/** + * shutdown CPU + * + */ +void rt_hw_cpu_shutdown() +{ + rt_uint32_t level; + rt_kprintf("shutdown...\n"); + + level = rt_hw_interrupt_disable(); + at91sam9260_poweroff(); + while (level) + { + RT_ASSERT(0); + } +} + +/*@}*/ diff --git a/libcpu/arm/at91sam926x/mmu.c b/libcpu/arm/at91sam926x/mmu.c index 59ae7824d6..32c903eaa2 100755 --- a/libcpu/arm/at91sam926x/mmu.c +++ b/libcpu/arm/at91sam926x/mmu.c @@ -1,395 +1,395 @@ -/*
- * File : mmu.c
- * This file is part of RT-Thread RTOS
- * COPYRIGHT (C) 2006, RT-Thread Development Team
- *
- * The license and distribution terms for this file may be
- * found in the file LICENSE in this distribution or at
- * http://www.rt-thread.org/license/LICENSE
- *
- * Change Logs:
- * Date Author Notes
- * 2011-01-13 weety modified from mini2440
- */
-
-#include <rtthread.h>
-#include "at91sam926x.h"
-
-#define _MMUTT_STARTADDRESS 0x33FF0000
-
-#define DESC_SEC (0x2|(1<<4))
-#define CB (3<<2) //cache_on, write_back
-#define CNB (2<<2) //cache_on, write_through
-#define NCB (1<<2) //cache_off,WR_BUF on
-#define NCNB (0<<2) //cache_off,WR_BUF off
-#define AP_RW (3<<10) //supervisor=RW, user=RW
-#define AP_RO (2<<10) //supervisor=RW, user=RO
-
-#define DOMAIN_FAULT (0x0)
-#define DOMAIN_CHK (0x1)
-#define DOMAIN_NOTCHK (0x3)
-#define DOMAIN0 (0x0<<5)
-#define DOMAIN1 (0x1<<5)
-
-#define DOMAIN0_ATTR (DOMAIN_CHK<<0)
-#define DOMAIN1_ATTR (DOMAIN_FAULT<<2)
-
-#define RW_CB (AP_RW|DOMAIN0|CB|DESC_SEC)
-#define RW_CNB (AP_RW|DOMAIN0|CNB|DESC_SEC)
-#define RW_NCNB (AP_RW|DOMAIN0|NCNB|DESC_SEC)
-#define RW_FAULT (AP_RW|DOMAIN1|NCNB|DESC_SEC)
-
-#ifdef __GNUC__
-void mmu_setttbase(register rt_uint32_t i)
-{
- asm ("mcr p15, 0, %0, c2, c0, 0": :"r" (i));
-}
-
-void mmu_set_domain(register rt_uint32_t i)
-{
- asm ("mcr p15,0, %0, c3, c0, 0": :"r" (i));
-}
-
-void mmu_enable()
-{
- register rt_uint32_t i;
-
- /* read control register */
- asm ("mrc p15, 0, %0, c1, c0, 0":"=r" (i));
-
- i |= 0x1;
-
- /* write back to control register */
- asm ("mcr p15, 0, %0, c1, c0, 0": :"r" (i));
-}
-
-void mmu_disable()
-{
- register rt_uint32_t i;
-
- /* read control register */
- asm ("mrc p15, 0, %0, c1, c0, 0":"=r" (i));
-
- i &= ~0x1;
-
- /* write back to control register */
- asm ("mcr p15, 0, %0, c1, c0, 0": :"r" (i));
-}
-
-void mmu_enable_icache()
-{
- register rt_uint32_t i;
-
- /* read control register */
- asm ("mrc p15, 0, %0, c1, c0, 0":"=r" (i));
-
- i |= (1 << 12);
-
- /* write back to control register */
- asm ("mcr p15, 0, %0, c1, c0, 0": :"r" (i));
-}
-
-void mmu_enable_dcache()
-{
- register rt_uint32_t i;
-
- /* read control register */
- asm ("mrc p15, 0, %0, c1, c0, 0":"=r" (i));
-
- i |= (1 << 2);
-
- /* write back to control register */
- asm ("mcr p15, 0, %0, c1, c0, 0": :"r" (i));
-}
-
-void mmu_disable_icache()
-{
- register rt_uint32_t i;
-
- /* read control register */
- asm ("mrc p15, 0, %0, c1, c0, 0":"=r" (i));
-
- i &= ~(1 << 12);
-
- /* write back to control register */
- asm ("mcr p15, 0, %0, c1, c0, 0": :"r" (i));
-}
-
-void mmu_disable_dcache()
-{
- register rt_uint32_t i;
-
- /* read control register */
- asm ("mrc p15, 0, %0, c1, c0, 0":"=r" (i));
-
- i &= ~(1 << 2);
-
- /* write back to control register */
- asm ("mcr p15, 0, %0, c1, c0, 0": :"r" (i));
-}
-
-void mmu_enable_alignfault()
-{
- register rt_uint32_t i;
-
- /* read control register */
- asm ("mrc p15, 0, %0, c1, c0, 0":"=r" (i));
-
- i |= (1 << 1);
-
- /* write back to control register */
- asm ("mcr p15, 0, %0, c1, c0, 0": :"r" (i));
-}
-
-void mmu_disable_alignfault()
-{
- register rt_uint32_t i;
-
- /* read control register */
- asm ("mrc p15, 0, %0, c1, c0, 0":"=r" (i));
-
- i &= ~(1 << 1);
-
- /* write back to control register */
- asm ("mcr p15, 0, %0, c1, c0, 0": :"r" (i));
-}
-
-void mmu_clean_invalidated_cache_index(int index)
-{
- asm ("mcr p15, 0, %0, c7, c14, 2": :"r" (index));
-}
-
-void mmu_invalidate_tlb()
-{
- asm ("mcr p15, 0, %0, c8, c7, 0": :"r" (0));
-}
-
-void mmu_invalidate_icache()
-{
- asm ("mcr p15, 0, %0, c7, c5, 0": :"r" (0));
-}
-#endif
-
-#ifdef __CC_ARM
-void mmu_setttbase(rt_uint32_t i)
-{
- __asm
- {
- mcr p15, 0, i, c2, c0, 0
- }
-}
-
-void mmu_set_domain(rt_uint32_t i)
-{
- __asm
- {
- mcr p15,0, i, c3, c0, 0
- }
-}
-
-void mmu_enable()
-{
- register rt_uint32_t value;
-
- __asm
- {
- mrc p15, 0, value, c1, c0, 0
- orr value, value, #0x01
- mcr p15, 0, value, c1, c0, 0
- }
-}
-
-void mmu_disable()
-{
- register rt_uint32_t value;
-
- __asm
- {
- mrc p15, 0, value, c1, c0, 0
- bic value, value, #0x01
- mcr p15, 0, value, c1, c0, 0
- }
-}
-
-void mmu_enable_icache()
-{
- register rt_uint32_t value;
-
- __asm
- {
- mrc p15, 0, value, c1, c0, 0
- orr value, value, #0x1000
- mcr p15, 0, value, c1, c0, 0
- }
-}
-
-void mmu_enable_dcache()
-{
- register rt_uint32_t value;
-
- __asm
- {
- mrc p15, 0, value, c1, c0, 0
- orr value, value, #0x04
- mcr p15, 0, value, c1, c0, 0
- }
-}
-
-void mmu_disable_icache()
-{
- register rt_uint32_t value;
-
- __asm
- {
- mrc p15, 0, value, c1, c0, 0
- bic value, value, #0x1000
- mcr p15, 0, value, c1, c0, 0
- }
-}
-
-void mmu_disable_dcache()
-{
- register rt_uint32_t value;
-
- __asm
- {
- mrc p15, 0, value, c1, c0, 0
- bic value, value, #0x04
- mcr p15, 0, value, c1, c0, 0
- }
-}
-
-void mmu_enable_alignfault()
-{
- register rt_uint32_t value;
-
- __asm
- {
- mrc p15, 0, value, c1, c0, 0
- orr value, value, #0x02
- mcr p15, 0, value, c1, c0, 0
- }
-}
-
-void mmu_disable_alignfault()
-{
- register rt_uint32_t value;
-
- __asm
- {
- mrc p15, 0, value, c1, c0, 0
- bic value, value, #0x02
- mcr p15, 0, value, c1, c0, 0
- }
-}
-
-void mmu_clean_invalidated_cache_index(int index)
-{
- __asm
- {
- mcr p15, 0, index, c7, c14, 2
- }
-}
-
-void mmu_invalidate_tlb()
-{
- register rt_uint32_t value;
-
- value = 0;
- __asm
- {
- mcr p15, 0, value, c8, c7, 0
- }
-}
-
-void mmu_invalidate_icache()
-{
- register rt_uint32_t value;
-
- value = 0;
-
- __asm
- {
- mcr p15, 0, value, c7, c5, 0
- }
-}
-#endif
-
-void mmu_setmtt(int vaddrStart,int vaddrEnd,int paddrStart,int attr)
-{
- volatile rt_uint32_t *pTT;
- volatile int i,nSec;
- pTT=(rt_uint32_t *)_MMUTT_STARTADDRESS+(vaddrStart>>20);
- nSec=(vaddrEnd>>20)-(vaddrStart>>20);
- for(i=0;i<=nSec;i++)
- {
- *pTT = attr |(((paddrStart>>20)+i)<<20);
- pTT++;
- }
-}
-
-void rt_hw_mmu_init(void)
-{
-#if 0
- int i,j;
- //========================== IMPORTANT NOTE =========================
- //The current stack and code area can't be re-mapped in this routine.
- //If you want memory map mapped freely, your own sophiscated mmu
- //initialization code is needed.
- //===================================================================
-
- mmu_disable_dcache();
- mmu_disable_icache();
-
- //If write-back is used,the DCache should be cleared.
- for(i=0;i<64;i++)
- for(j=0;j<8;j++)
- mmu_clean_invalidated_cache_index((i<<26)|(j<<5));
-
- mmu_invalidate_icache();
-
- //To complete mmu_Init() fast, Icache may be turned on here.
- mmu_enable_icache();
-
- mmu_disable();
- mmu_invalidate_tlb();
-
- //mmu_setmtt(int vaddrStart,int vaddrEnd,int paddrStart,int attr);
- mmu_setmtt(0x00000000,0x07f00000,0x00000000,RW_CNB); //bank0
- mmu_setmtt(0x00000000,0x03f00000,(int)0x30000000,RW_CB); //bank0
- mmu_setmtt(0x04000000,0x07f00000,0,RW_NCNB); //bank0
- mmu_setmtt(0x08000000,0x0ff00000,0x08000000,RW_CNB); //bank1
- mmu_setmtt(0x10000000,0x17f00000,0x10000000,RW_NCNB); //bank2
- mmu_setmtt(0x18000000,0x1ff00000,0x18000000,RW_NCNB); //bank3
- //mmu_setmtt(0x20000000,0x27f00000,0x20000000,RW_CB); //bank4
- mmu_setmtt(0x20000000,0x27f00000,0x20000000,RW_NCNB); //bank4 for DM9000
- mmu_setmtt(0x28000000,0x2ff00000,0x28000000,RW_NCNB); //bank5
- //30f00000->30100000, 31000000->30200000
- mmu_setmtt(0x30000000,0x30100000,0x30000000,RW_CB); //bank6-1
- mmu_setmtt(0x30200000,0x33e00000,0x30200000,RW_CB); //bank6-2
-
- mmu_setmtt(0x33f00000,0x34000000,0x33f00000,RW_NCNB); //bank6-3
- mmu_setmtt(0x38000000,0x3ff00000,0x38000000,RW_NCNB); //bank7
-
- mmu_setmtt(0x40000000,0x47f00000,0x40000000,RW_NCNB); //SFR
- mmu_setmtt(0x48000000,0x5af00000,0x48000000,RW_NCNB); //SFR
- mmu_setmtt(0x5b000000,0x5b000000,0x5b000000,RW_NCNB); //SFR
- mmu_setmtt(0x5b100000,0xfff00000,0x5b100000,RW_FAULT);//not used
- mmu_setmtt(0x60000000,0x67f00000,0x60000000,RW_NCNB); //SFR
-
- mmu_setttbase(_MMUTT_STARTADDRESS);
-
- /* DOMAIN1: no_access, DOMAIN0,2~15=client(AP is checked) */
- mmu_set_domain(0x55555550|DOMAIN1_ATTR|DOMAIN0_ATTR);
-
- mmu_enable_alignfault();
-
- mmu_enable();
-
- /* ICache enable */
- mmu_enable_icache();
- /* DCache should be turned on after mmu is turned on. */
- mmu_enable_dcache();
-#endif
-}
-
+/* + * File : mmu.c + * This file is part of RT-Thread RTOS + * COPYRIGHT (C) 2006, RT-Thread Development Team + * + * The license and distribution terms for this file may be + * found in the file LICENSE in this distribution or at + * http://www.rt-thread.org/license/LICENSE + * + * Change Logs: + * Date Author Notes + * 2011-01-13 weety modified from mini2440 + */ + +#include <rtthread.h> +#include "at91sam926x.h" + +#define _MMUTT_STARTADDRESS 0x33FF0000 + +#define DESC_SEC (0x2|(1<<4)) +#define CB (3<<2) //cache_on, write_back +#define CNB (2<<2) //cache_on, write_through +#define NCB (1<<2) //cache_off,WR_BUF on +#define NCNB (0<<2) //cache_off,WR_BUF off +#define AP_RW (3<<10) //supervisor=RW, user=RW +#define AP_RO (2<<10) //supervisor=RW, user=RO + +#define DOMAIN_FAULT (0x0) +#define DOMAIN_CHK (0x1) +#define DOMAIN_NOTCHK (0x3) +#define DOMAIN0 (0x0<<5) +#define DOMAIN1 (0x1<<5) + +#define DOMAIN0_ATTR (DOMAIN_CHK<<0) +#define DOMAIN1_ATTR (DOMAIN_FAULT<<2) + +#define RW_CB (AP_RW|DOMAIN0|CB|DESC_SEC) +#define RW_CNB (AP_RW|DOMAIN0|CNB|DESC_SEC) +#define RW_NCNB (AP_RW|DOMAIN0|NCNB|DESC_SEC) +#define RW_FAULT (AP_RW|DOMAIN1|NCNB|DESC_SEC) + +#ifdef __GNUC__ +void mmu_setttbase(register rt_uint32_t i) +{ + asm ("mcr p15, 0, %0, c2, c0, 0": :"r" (i)); +} + +void mmu_set_domain(register rt_uint32_t i) +{ + asm ("mcr p15,0, %0, c3, c0, 0": :"r" (i)); +} + +void mmu_enable() +{ + register rt_uint32_t i; + + /* read control register */ + asm ("mrc p15, 0, %0, c1, c0, 0":"=r" (i)); + + i |= 0x1; + + /* write back to control register */ + asm ("mcr p15, 0, %0, c1, c0, 0": :"r" (i)); +} + +void mmu_disable() +{ + register rt_uint32_t i; + + /* read control register */ + asm ("mrc p15, 0, %0, c1, c0, 0":"=r" (i)); + + i &= ~0x1; + + /* write back to control register */ + asm ("mcr p15, 0, %0, c1, c0, 0": :"r" (i)); +} + +void mmu_enable_icache() +{ + register rt_uint32_t i; + + /* read control register */ + asm ("mrc p15, 0, %0, c1, c0, 0":"=r" (i)); + + i |= (1 << 12); + + /* write back to control register */ + asm ("mcr p15, 0, %0, c1, c0, 0": :"r" (i)); +} + +void mmu_enable_dcache() +{ + register rt_uint32_t i; + + /* read control register */ + asm ("mrc p15, 0, %0, c1, c0, 0":"=r" (i)); + + i |= (1 << 2); + + /* write back to control register */ + asm ("mcr p15, 0, %0, c1, c0, 0": :"r" (i)); +} + +void mmu_disable_icache() +{ + register rt_uint32_t i; + + /* read control register */ + asm ("mrc p15, 0, %0, c1, c0, 0":"=r" (i)); + + i &= ~(1 << 12); + + /* write back to control register */ + asm ("mcr p15, 0, %0, c1, c0, 0": :"r" (i)); +} + +void mmu_disable_dcache() +{ + register rt_uint32_t i; + + /* read control register */ + asm ("mrc p15, 0, %0, c1, c0, 0":"=r" (i)); + + i &= ~(1 << 2); + + /* write back to control register */ + asm ("mcr p15, 0, %0, c1, c0, 0": :"r" (i)); +} + +void mmu_enable_alignfault() +{ + register rt_uint32_t i; + + /* read control register */ + asm ("mrc p15, 0, %0, c1, c0, 0":"=r" (i)); + + i |= (1 << 1); + + /* write back to control register */ + asm ("mcr p15, 0, %0, c1, c0, 0": :"r" (i)); +} + +void mmu_disable_alignfault() +{ + register rt_uint32_t i; + + /* read control register */ + asm ("mrc p15, 0, %0, c1, c0, 0":"=r" (i)); + + i &= ~(1 << 1); + + /* write back to control register */ + asm ("mcr p15, 0, %0, c1, c0, 0": :"r" (i)); +} + +void mmu_clean_invalidated_cache_index(int index) +{ + asm ("mcr p15, 0, %0, c7, c14, 2": :"r" (index)); +} + +void mmu_invalidate_tlb() +{ + asm ("mcr p15, 0, %0, c8, c7, 0": :"r" (0)); +} + +void mmu_invalidate_icache() +{ + asm ("mcr p15, 0, %0, c7, c5, 0": :"r" (0)); +} +#endif + +#ifdef __CC_ARM +void mmu_setttbase(rt_uint32_t i) +{ + __asm + { + mcr p15, 0, i, c2, c0, 0 + } +} + +void mmu_set_domain(rt_uint32_t i) +{ + __asm + { + mcr p15,0, i, c3, c0, 0 + } +} + +void mmu_enable() +{ + register rt_uint32_t value; + + __asm + { + mrc p15, 0, value, c1, c0, 0 + orr value, value, #0x01 + mcr p15, 0, value, c1, c0, 0 + } +} + +void mmu_disable() +{ + register rt_uint32_t value; + + __asm + { + mrc p15, 0, value, c1, c0, 0 + bic value, value, #0x01 + mcr p15, 0, value, c1, c0, 0 + } +} + +void mmu_enable_icache() +{ + register rt_uint32_t value; + + __asm + { + mrc p15, 0, value, c1, c0, 0 + orr value, value, #0x1000 + mcr p15, 0, value, c1, c0, 0 + } +} + +void mmu_enable_dcache() +{ + register rt_uint32_t value; + + __asm + { + mrc p15, 0, value, c1, c0, 0 + orr value, value, #0x04 + mcr p15, 0, value, c1, c0, 0 + } +} + +void mmu_disable_icache() +{ + register rt_uint32_t value; + + __asm + { + mrc p15, 0, value, c1, c0, 0 + bic value, value, #0x1000 + mcr p15, 0, value, c1, c0, 0 + } +} + +void mmu_disable_dcache() +{ + register rt_uint32_t value; + + __asm + { + mrc p15, 0, value, c1, c0, 0 + bic value, value, #0x04 + mcr p15, 0, value, c1, c0, 0 + } +} + +void mmu_enable_alignfault() +{ + register rt_uint32_t value; + + __asm + { + mrc p15, 0, value, c1, c0, 0 + orr value, value, #0x02 + mcr p15, 0, value, c1, c0, 0 + } +} + +void mmu_disable_alignfault() +{ + register rt_uint32_t value; + + __asm + { + mrc p15, 0, value, c1, c0, 0 + bic value, value, #0x02 + mcr p15, 0, value, c1, c0, 0 + } +} + +void mmu_clean_invalidated_cache_index(int index) +{ + __asm + { + mcr p15, 0, index, c7, c14, 2 + } +} + +void mmu_invalidate_tlb() +{ + register rt_uint32_t value; + + value = 0; + __asm + { + mcr p15, 0, value, c8, c7, 0 + } +} + +void mmu_invalidate_icache() +{ + register rt_uint32_t value; + + value = 0; + + __asm + { + mcr p15, 0, value, c7, c5, 0 + } +} +#endif + +void mmu_setmtt(int vaddrStart,int vaddrEnd,int paddrStart,int attr) +{ + volatile rt_uint32_t *pTT; + volatile int i,nSec; + pTT=(rt_uint32_t *)_MMUTT_STARTADDRESS+(vaddrStart>>20); + nSec=(vaddrEnd>>20)-(vaddrStart>>20); + for(i=0;i<=nSec;i++) + { + *pTT = attr |(((paddrStart>>20)+i)<<20); + pTT++; + } +} + +void rt_hw_mmu_init(void) +{ +#if 0 + int i,j; + //========================== IMPORTANT NOTE ========================= + //The current stack and code area can't be re-mapped in this routine. + //If you want memory map mapped freely, your own sophiscated mmu + //initialization code is needed. + //=================================================================== + + mmu_disable_dcache(); + mmu_disable_icache(); + + //If write-back is used,the DCache should be cleared. + for(i=0;i<64;i++) + for(j=0;j<8;j++) + mmu_clean_invalidated_cache_index((i<<26)|(j<<5)); + + mmu_invalidate_icache(); + + //To complete mmu_Init() fast, Icache may be turned on here. + mmu_enable_icache(); + + mmu_disable(); + mmu_invalidate_tlb(); + + //mmu_setmtt(int vaddrStart,int vaddrEnd,int paddrStart,int attr); + mmu_setmtt(0x00000000,0x07f00000,0x00000000,RW_CNB); //bank0 + mmu_setmtt(0x00000000,0x03f00000,(int)0x30000000,RW_CB); //bank0 + mmu_setmtt(0x04000000,0x07f00000,0,RW_NCNB); //bank0 + mmu_setmtt(0x08000000,0x0ff00000,0x08000000,RW_CNB); //bank1 + mmu_setmtt(0x10000000,0x17f00000,0x10000000,RW_NCNB); //bank2 + mmu_setmtt(0x18000000,0x1ff00000,0x18000000,RW_NCNB); //bank3 + //mmu_setmtt(0x20000000,0x27f00000,0x20000000,RW_CB); //bank4 + mmu_setmtt(0x20000000,0x27f00000,0x20000000,RW_NCNB); //bank4 for DM9000 + mmu_setmtt(0x28000000,0x2ff00000,0x28000000,RW_NCNB); //bank5 + //30f00000->30100000, 31000000->30200000 + mmu_setmtt(0x30000000,0x30100000,0x30000000,RW_CB); //bank6-1 + mmu_setmtt(0x30200000,0x33e00000,0x30200000,RW_CB); //bank6-2 + + mmu_setmtt(0x33f00000,0x34000000,0x33f00000,RW_NCNB); //bank6-3 + mmu_setmtt(0x38000000,0x3ff00000,0x38000000,RW_NCNB); //bank7 + + mmu_setmtt(0x40000000,0x47f00000,0x40000000,RW_NCNB); //SFR + mmu_setmtt(0x48000000,0x5af00000,0x48000000,RW_NCNB); //SFR + mmu_setmtt(0x5b000000,0x5b000000,0x5b000000,RW_NCNB); //SFR + mmu_setmtt(0x5b100000,0xfff00000,0x5b100000,RW_FAULT);//not used + mmu_setmtt(0x60000000,0x67f00000,0x60000000,RW_NCNB); //SFR + + mmu_setttbase(_MMUTT_STARTADDRESS); + + /* DOMAIN1: no_access, DOMAIN0,2~15=client(AP is checked) */ + mmu_set_domain(0x55555550|DOMAIN1_ATTR|DOMAIN0_ATTR); + + mmu_enable_alignfault(); + + mmu_enable(); + + /* ICache enable */ + mmu_enable_icache(); + /* DCache should be turned on after mmu is turned on. */ + mmu_enable_dcache(); +#endif +} + diff --git a/libcpu/arm/at91sam926x/serial.h b/libcpu/arm/at91sam926x/serial.h index a1c5471403..67f6d3c659 100755 --- a/libcpu/arm/at91sam926x/serial.h +++ b/libcpu/arm/at91sam926x/serial.h @@ -1,76 +1,76 @@ -#ifndef __RT_HW_SERIAL_H__
-#define __RT_HW_SERIAL_H__
-
-#include <rthw.h>
-#include <rtthread.h>
-
-#include "at91sam926x.h"
-
-#define RXRDY 0x01
-#define TXRDY (1 << 1)
-#define BPS 115200 /* serial baudrate */
-
-#define UART_RX_BUFFER_SIZE 64
-#define UART_TX_BUFFER_SIZE 64
-
-struct serial_int_rx
-{
- rt_uint8_t rx_buffer[UART_RX_BUFFER_SIZE];
- rt_uint32_t read_index, save_index;
-};
-
-struct serial_int_tx
-{
- rt_uint8_t tx_buffer[UART_TX_BUFFER_SIZE];
- rt_uint32_t write_index, save_index;
-};
-
-typedef struct uartport
-{
-/* USART register offsets */
- volatile rt_uint32_t USART_CR;
- volatile rt_uint32_t USART_MR;
- volatile rt_uint32_t USART_IER;
- volatile rt_uint32_t USART_IDR;
- volatile rt_uint32_t USART_IMR;
- volatile rt_uint32_t USART_CSR;
- volatile rt_uint32_t USART_RHR;
- volatile rt_uint32_t USART_THR;
- volatile rt_uint32_t USART_BRGR;
- volatile rt_uint32_t USART_RTOR;
- volatile rt_uint32_t USART_TTGR;
- volatile rt_uint32_t reseverd0[5];
- volatile rt_uint32_t USART_FIDI;
- volatile rt_uint32_t USART_NER;
- volatile rt_uint32_t USART_XXR;
- volatile rt_uint32_t USART_IFR;
- volatile rt_uint32_t reserved1[44];
- volatile rt_uint32_t USART_RPR;
- volatile rt_uint32_t USART_RCR;
- volatile rt_uint32_t USART_TPR;
- volatile rt_uint32_t USART_TCR;
- volatile rt_uint32_t USART_RNPR;
- volatile rt_uint32_t USART_RNCR;
- volatile rt_uint32_t USART_TNPR;
- volatile rt_uint32_t USART_TNCR;
- volatile rt_uint32_t USART_PTCR;
- volatile rt_uint32_t USART_PTSR;
-}uartport;
-
-
-struct serial_device
-{
- uartport* uart_device;
-
- /* rx structure */
- struct serial_int_rx* int_rx;
-
- /* tx structure */
- struct serial_int_tx* int_tx;
-};
-
-rt_err_t rt_hw_serial_register(rt_device_t device, const char* name, rt_uint32_t flag, struct serial_device *serial);
-
-void rt_hw_serial_isr(rt_device_t device);
-
-#endif
+#ifndef __RT_HW_SERIAL_H__ +#define __RT_HW_SERIAL_H__ + +#include <rthw.h> +#include <rtthread.h> + +#include "at91sam926x.h" + +#define RXRDY 0x01 +#define TXRDY (1 << 1) +#define BPS 115200 /* serial baudrate */ + +#define UART_RX_BUFFER_SIZE 64 +#define UART_TX_BUFFER_SIZE 64 + +struct serial_int_rx +{ + rt_uint8_t rx_buffer[UART_RX_BUFFER_SIZE]; + rt_uint32_t read_index, save_index; +}; + +struct serial_int_tx +{ + rt_uint8_t tx_buffer[UART_TX_BUFFER_SIZE]; + rt_uint32_t write_index, save_index; +}; + +typedef struct uartport +{ +/* USART register offsets */ + volatile rt_uint32_t USART_CR; + volatile rt_uint32_t USART_MR; + volatile rt_uint32_t USART_IER; + volatile rt_uint32_t USART_IDR; + volatile rt_uint32_t USART_IMR; + volatile rt_uint32_t USART_CSR; + volatile rt_uint32_t USART_RHR; + volatile rt_uint32_t USART_THR; + volatile rt_uint32_t USART_BRGR; + volatile rt_uint32_t USART_RTOR; + volatile rt_uint32_t USART_TTGR; + volatile rt_uint32_t reseverd0[5]; + volatile rt_uint32_t USART_FIDI; + volatile rt_uint32_t USART_NER; + volatile rt_uint32_t USART_XXR; + volatile rt_uint32_t USART_IFR; + volatile rt_uint32_t reserved1[44]; + volatile rt_uint32_t USART_RPR; + volatile rt_uint32_t USART_RCR; + volatile rt_uint32_t USART_TPR; + volatile rt_uint32_t USART_TCR; + volatile rt_uint32_t USART_RNPR; + volatile rt_uint32_t USART_RNCR; + volatile rt_uint32_t USART_TNPR; + volatile rt_uint32_t USART_TNCR; + volatile rt_uint32_t USART_PTCR; + volatile rt_uint32_t USART_PTSR; +}uartport; + + +struct serial_device +{ + uartport* uart_device; + + /* rx structure */ + struct serial_int_rx* int_rx; + + /* tx structure */ + struct serial_int_tx* int_tx; +}; + +rt_err_t rt_hw_serial_register(rt_device_t device, const char* name, rt_uint32_t flag, struct serial_device *serial); + +void rt_hw_serial_isr(rt_device_t device); + +#endif diff --git a/libcpu/arm/at91sam926x/start_rvds.S b/libcpu/arm/at91sam926x/start_rvds.S index 7fdb08b30a..49ad09ea17 100644 --- a/libcpu/arm/at91sam926x/start_rvds.S +++ b/libcpu/arm/at91sam926x/start_rvds.S @@ -1,315 +1,315 @@ -;/*
-; * File : start_rvds.S
-; * This file is part of RT-Thread RTOS
-; * COPYRIGHT (C) 2006, RT-Thread Development Team
-; *
-; * The license and distribution terms for this file may be
-; * found in the file LICENSE in this distribution or at
-; * http://www.rt-thread.org/license/LICENSE
-; *
-; * Change Logs:
-; * Date Author Notes
-; * 2011-08-14 weety first version
-; */
-
-
-; Standard definitions of Mode bits and Interrupt (I & F) flags in PSRs
-
-Mode_USR EQU 0x10
-Mode_FIQ EQU 0x11
-Mode_IRQ EQU 0x12
-Mode_SVC EQU 0x13
-Mode_ABT EQU 0x17
-Mode_UND EQU 0x1B
-Mode_SYS EQU 0x1F
-
-SVCMODE EQU 0x13
-MODEMASK EQU 0x1f
-
-I_Bit EQU 0x80 ; when I bit is set, IRQ is disabled
-F_Bit EQU 0x40 ; when F bit is set, FIQ is disabled
-
-
-;----------------------- Stack and Heap Definitions ----------------------------
-
-;// <h> Stack Configuration (Stack Sizes in Bytes)
-;// <o0> Undefined Mode <0x0-0xFFFFFFFF:8>
-;// <o1> Supervisor Mode <0x0-0xFFFFFFFF:8>
-;// <o2> Abort Mode <0x0-0xFFFFFFFF:8>
-;// <o3> Fast Interrupt Mode <0x0-0xFFFFFFFF:8>
-;// <o4> Interrupt Mode <0x0-0xFFFFFFFF:8>
-;// <o5> User/System Mode <0x0-0xFFFFFFFF:8>
-;// </h>
-
-UND_Stack_Size EQU 512
-SVC_Stack_Size EQU 4096
-ABT_Stack_Size EQU 512
-FIQ_Stack_Size EQU 1024
-IRQ_Stack_Size EQU 1024
-USR_Stack_Size EQU 512
-
-ISR_Stack_Size EQU (UND_Stack_Size + SVC_Stack_Size + ABT_Stack_Size + \
- FIQ_Stack_Size + IRQ_Stack_Size)
-
- AREA STACK, NOINIT, READWRITE, ALIGN=3
-
-Stack_Mem SPACE USR_Stack_Size
-__initial_sp SPACE ISR_Stack_Size
-Stack_Top
-
-
-;// <h> Heap Configuration
-;// <o> Heap Size (in Bytes) <0x0-0xFFFFFFFF>
-;// </h>
-
-Heap_Size EQU 0x00000000
-
- AREA HEAP, NOINIT, READWRITE, ALIGN=3
-__heap_base
-Heap_Mem SPACE Heap_Size
-__heap_limit
-
-
-;----------------------- Memory Definitions ------------------------------------
-
-AT91_MATRIX_BASE EQU 0xffffee00
-AT91_MATRIX_MRCR EQU (AT91_MATRIX_BASE + 0x100)
-AT91_MATRIX_RCB0 EQU 0x00000001
-AT91_MATRIX_RCB1 EQU 0x00000002
-AT91_AIC_BASE EQU 0xfffff000
-AT91_AIC_IDCR EQU 0x124
-AT91_AIC_ICCR EQU 0x128
-
-;----------------------- CODE --------------------------------------------------
-
- PRESERVE8
-
-
-; Area Definition and Entry Point
-; Startup Code must be linked first at Address at which it expects to run.
-
- AREA RESET, CODE, READONLY
- ARM
-
-; Exception Vectors
-; Mapped to Address 0.
-; Absolute addressing mode must be used.
-; Dummy Handlers are implemented as infinite loops which can be modified.
-
- EXPORT Entry_Point
-Entry_Point
-Vectors LDR PC, Reset_Addr
- LDR PC, Undef_Addr
- LDR PC, SWI_Addr
- LDR PC, PAbt_Addr
- LDR PC, DAbt_Addr
- NOP
- LDR PC, IRQ_Addr
- LDR PC, FIQ_Addr
-
-Reset_Addr DCD Reset_Handler
-Undef_Addr DCD Undef_Handler
-SWI_Addr DCD SWI_Handler
-PAbt_Addr DCD PAbt_Handler
-DAbt_Addr DCD DAbt_Handler
- DCD 0 ; Reserved Address
-IRQ_Addr DCD IRQ_Handler
-FIQ_Addr DCD FIQ_Handler
-
-Undef_Handler B Undef_Handler
-SWI_Handler B SWI_Handler
-PAbt_Handler B PAbt_Handler
-;DAbt_Handler B DAbt_Handler
-FIQ_Handler B FIQ_Handler
-
-;*
-;*************************************************************************
-;*
-;* Interrupt handling
-;*
-;*************************************************************************
-;*
-; DAbt Handler
-DAbt_Handler
- IMPORT rt_hw_trap_dabt
-
- sub sp, sp, #72
- stmia sp, {r0 - r12} ;/* Calling r0-r12 */
- add r8, sp, #60
- stmdb r8, {sp, lr} ;/* Calling SP, LR */
- str lr, [r8, #0] ;/* Save calling PC */
- mrs r6, spsr
- str r6, [r8, #4] ;/* Save CPSR */
- str r0, [r8, #8] ;/* Save OLD_R0 */
- mov r0, sp
-
- bl rt_hw_trap_dabt
-
-
-;##########################################
-; Reset Handler
-
- EXPORT Reset_Handler
-Reset_Handler
-
-
-; set the cpu to SVC32 mode-----------------------------------------------------
-
- MRS R0,CPSR
- BIC R0,R0,#MODEMASK
- ORR R0,R0,#SVCMODE
- MSR CPSR_cxsf,R0
- LDR R1, =AT91_AIC_BASE
- LDR R0, =0xffffffff
- STR R0, [R1, #AT91_AIC_IDCR]
- STR R0, [R1, #AT91_AIC_ICCR]
-
-; remap internal ram to 0x00000000 address
- LDR R0, =AT91_MATRIX_MRCR
- LDR R1, =(AT91_MATRIX_RCB0|AT91_MATRIX_RCB1)
- STR R1, [R0]
-
-
-; Copy Exception Vectors to Internal RAM ---------------------------------------
-
- ADR R8, Vectors ; Source
- LDR R9, =0x00 ; Destination
- LDMIA R8!, {R0-R7} ; Load Vectors
- STMIA R9!, {R0-R7} ; Store Vectors
- LDMIA R8!, {R0-R7} ; Load Handler Addresses
- STMIA R9!, {R0-R7} ; Store Handler Addresses
-
-
-; Setup Stack for each mode ----------------------------------------------------
-
- LDR R0, =Stack_Top
-
-; Enter Undefined Instruction Mode and set its Stack Pointer
- MSR CPSR_c, #Mode_UND:OR:I_Bit:OR:F_Bit
- MOV SP, R0
- SUB R0, R0, #UND_Stack_Size
-
-; Enter Abort Mode and set its Stack Pointer
- MSR CPSR_c, #Mode_ABT:OR:I_Bit:OR:F_Bit
- MOV SP, R0
- SUB R0, R0, #ABT_Stack_Size
-
-; Enter FIQ Mode and set its Stack Pointer
- MSR CPSR_c, #Mode_FIQ:OR:I_Bit:OR:F_Bit
- MOV SP, R0
- SUB R0, R0, #FIQ_Stack_Size
-
-; Enter IRQ Mode and set its Stack Pointer
- MSR CPSR_c, #Mode_IRQ:OR:I_Bit:OR:F_Bit
- MOV SP, R0
- SUB R0, R0, #IRQ_Stack_Size
-
-; Enter Supervisor Mode and set its Stack Pointer
- MSR CPSR_c, #Mode_SVC:OR:I_Bit:OR:F_Bit
- MOV SP, R0
- SUB R0, R0, #SVC_Stack_Size
-
-; Enter User Mode and set its Stack Pointer
- ; MSR CPSR_c, #Mode_USR
- MOV SP, R0
- SUB SL, SP, #USR_Stack_Size
-
-; Enter the C code -------------------------------------------------------------
-
- IMPORT __main
- LDR R0, =__main
- BX R0
-
- IMPORT rt_interrupt_enter
- IMPORT rt_interrupt_leave
- IMPORT rt_thread_switch_interrupt_flag
- IMPORT rt_interrupt_from_thread
- IMPORT rt_interrupt_to_thread
- IMPORT rt_hw_trap_irq
-
-IRQ_Handler PROC
- EXPORT IRQ_Handler
- STMFD sp!, {r0-r12,lr}
- BL rt_interrupt_enter
- BL rt_hw_trap_irq
- BL rt_interrupt_leave
-
- ; if rt_thread_switch_interrupt_flag set, jump to
- ; rt_hw_context_switch_interrupt_do and don't return
- LDR r0, =rt_thread_switch_interrupt_flag
- LDR r1, [r0]
- CMP r1, #1
- BEQ rt_hw_context_switch_interrupt_do
-
- LDMFD sp!, {r0-r12,lr}
- SUBS pc, lr, #4
- ENDP
-
-; /*
-; * void rt_hw_context_switch_interrupt_do(rt_base_t flag)
-; */
-rt_hw_context_switch_interrupt_do PROC
- EXPORT rt_hw_context_switch_interrupt_do
- MOV r1, #0 ; clear flag
- STR r1, [r0]
-
- LDMFD sp!, {r0-r12,lr}; reload saved registers
- STMFD sp!, {r0-r3} ; save r0-r3
- MOV r1, sp
- ADD sp, sp, #16 ; restore sp
- SUB r2, lr, #4 ; save old task's pc to r2
-
- MRS r3, spsr ; get cpsr of interrupt thread
-
- ; switch to SVC mode and no interrupt
- MSR cpsr_c, #I_Bit:OR:F_Bit:OR:Mode_SVC
-
- STMFD sp!, {r2} ; push old task's pc
- STMFD sp!, {r4-r12,lr}; push old task's lr,r12-r4
- MOV r4, r1 ; Special optimised code below
- MOV r5, r3
- LDMFD r4!, {r0-r3}
- STMFD sp!, {r0-r3} ; push old task's r3-r0
- STMFD sp!, {r5} ; push old task's cpsr
- MRS r4, spsr
- STMFD sp!, {r4} ; push old task's spsr
-
- LDR r4, =rt_interrupt_from_thread
- LDR r5, [r4]
- STR sp, [r5] ; store sp in preempted tasks's TCB
-
- LDR r6, =rt_interrupt_to_thread
- LDR r6, [r6]
- LDR sp, [r6] ; get new task's stack pointer
-
- LDMFD sp!, {r4} ; pop new task's spsr
- MSR spsr_cxsf, r4
- LDMFD sp!, {r4} ; pop new task's psr
- MSR cpsr_cxsf, r4
-
- LDMFD sp!, {r0-r12,lr,pc} ; pop new task's r0-r12,lr & pc
- ENDP
-
- IF :DEF:__MICROLIB
-
- EXPORT __heap_base
- EXPORT __heap_limit
-
- ELSE
-; User Initial Stack & Heap
- AREA |.text|, CODE, READONLY
-
- IMPORT __use_two_region_memory
- EXPORT __user_initial_stackheap
-__user_initial_stackheap
-
- LDR R0, = Heap_Mem
- LDR R1, =(Stack_Mem + USR_Stack_Size)
- LDR R2, = (Heap_Mem + Heap_Size)
- LDR R3, = Stack_Mem
- BX LR
- ENDIF
-
-
- END
-
+;/* +; * File : start_rvds.S +; * This file is part of RT-Thread RTOS +; * COPYRIGHT (C) 2006, RT-Thread Development Team +; * +; * The license and distribution terms for this file may be +; * found in the file LICENSE in this distribution or at +; * http://www.rt-thread.org/license/LICENSE +; * +; * Change Logs: +; * Date Author Notes +; * 2011-08-14 weety first version +; */ + + +; Standard definitions of Mode bits and Interrupt (I & F) flags in PSRs + +Mode_USR EQU 0x10 +Mode_FIQ EQU 0x11 +Mode_IRQ EQU 0x12 +Mode_SVC EQU 0x13 +Mode_ABT EQU 0x17 +Mode_UND EQU 0x1B +Mode_SYS EQU 0x1F + +SVCMODE EQU 0x13 +MODEMASK EQU 0x1f + +I_Bit EQU 0x80 ; when I bit is set, IRQ is disabled +F_Bit EQU 0x40 ; when F bit is set, FIQ is disabled + + +;----------------------- Stack and Heap Definitions ---------------------------- + +;// <h> Stack Configuration (Stack Sizes in Bytes) +;// <o0> Undefined Mode <0x0-0xFFFFFFFF:8> +;// <o1> Supervisor Mode <0x0-0xFFFFFFFF:8> +;// <o2> Abort Mode <0x0-0xFFFFFFFF:8> +;// <o3> Fast Interrupt Mode <0x0-0xFFFFFFFF:8> +;// <o4> Interrupt Mode <0x0-0xFFFFFFFF:8> +;// <o5> User/System Mode <0x0-0xFFFFFFFF:8> +;// </h> + +UND_Stack_Size EQU 512 +SVC_Stack_Size EQU 4096 +ABT_Stack_Size EQU 512 +FIQ_Stack_Size EQU 1024 +IRQ_Stack_Size EQU 1024 +USR_Stack_Size EQU 512 + +ISR_Stack_Size EQU (UND_Stack_Size + SVC_Stack_Size + ABT_Stack_Size + \ + FIQ_Stack_Size + IRQ_Stack_Size) + + AREA STACK, NOINIT, READWRITE, ALIGN=3 + +Stack_Mem SPACE USR_Stack_Size +__initial_sp SPACE ISR_Stack_Size +Stack_Top + + +;// <h> Heap Configuration +;// <o> Heap Size (in Bytes) <0x0-0xFFFFFFFF> +;// </h> + +Heap_Size EQU 0x00000000 + + AREA HEAP, NOINIT, READWRITE, ALIGN=3 +__heap_base +Heap_Mem SPACE Heap_Size +__heap_limit + + +;----------------------- Memory Definitions ------------------------------------ + +AT91_MATRIX_BASE EQU 0xffffee00 +AT91_MATRIX_MRCR EQU (AT91_MATRIX_BASE + 0x100) +AT91_MATRIX_RCB0 EQU 0x00000001 +AT91_MATRIX_RCB1 EQU 0x00000002 +AT91_AIC_BASE EQU 0xfffff000 +AT91_AIC_IDCR EQU 0x124 +AT91_AIC_ICCR EQU 0x128 + +;----------------------- CODE -------------------------------------------------- + + PRESERVE8 + + +; Area Definition and Entry Point +; Startup Code must be linked first at Address at which it expects to run. + + AREA RESET, CODE, READONLY + ARM + +; Exception Vectors +; Mapped to Address 0. +; Absolute addressing mode must be used. +; Dummy Handlers are implemented as infinite loops which can be modified. + + EXPORT Entry_Point +Entry_Point +Vectors LDR PC, Reset_Addr + LDR PC, Undef_Addr + LDR PC, SWI_Addr + LDR PC, PAbt_Addr + LDR PC, DAbt_Addr + NOP + LDR PC, IRQ_Addr + LDR PC, FIQ_Addr + +Reset_Addr DCD Reset_Handler +Undef_Addr DCD Undef_Handler +SWI_Addr DCD SWI_Handler +PAbt_Addr DCD PAbt_Handler +DAbt_Addr DCD DAbt_Handler + DCD 0 ; Reserved Address +IRQ_Addr DCD IRQ_Handler +FIQ_Addr DCD FIQ_Handler + +Undef_Handler B Undef_Handler +SWI_Handler B SWI_Handler +PAbt_Handler B PAbt_Handler +;DAbt_Handler B DAbt_Handler +FIQ_Handler B FIQ_Handler + +;* +;************************************************************************* +;* +;* Interrupt handling +;* +;************************************************************************* +;* +; DAbt Handler +DAbt_Handler + IMPORT rt_hw_trap_dabt + + sub sp, sp, #72 + stmia sp, {r0 - r12} ;/* Calling r0-r12 */ + add r8, sp, #60 + stmdb r8, {sp, lr} ;/* Calling SP, LR */ + str lr, [r8, #0] ;/* Save calling PC */ + mrs r6, spsr + str r6, [r8, #4] ;/* Save CPSR */ + str r0, [r8, #8] ;/* Save OLD_R0 */ + mov r0, sp + + bl rt_hw_trap_dabt + + +;########################################## +; Reset Handler + + EXPORT Reset_Handler +Reset_Handler + + +; set the cpu to SVC32 mode----------------------------------------------------- + + MRS R0,CPSR + BIC R0,R0,#MODEMASK + ORR R0,R0,#SVCMODE + MSR CPSR_cxsf,R0 + LDR R1, =AT91_AIC_BASE + LDR R0, =0xffffffff + STR R0, [R1, #AT91_AIC_IDCR] + STR R0, [R1, #AT91_AIC_ICCR] + +; remap internal ram to 0x00000000 address + LDR R0, =AT91_MATRIX_MRCR + LDR R1, =(AT91_MATRIX_RCB0|AT91_MATRIX_RCB1) + STR R1, [R0] + + +; Copy Exception Vectors to Internal RAM --------------------------------------- + + ADR R8, Vectors ; Source + LDR R9, =0x00 ; Destination + LDMIA R8!, {R0-R7} ; Load Vectors + STMIA R9!, {R0-R7} ; Store Vectors + LDMIA R8!, {R0-R7} ; Load Handler Addresses + STMIA R9!, {R0-R7} ; Store Handler Addresses + + +; Setup Stack for each mode ---------------------------------------------------- + + LDR R0, =Stack_Top + +; Enter Undefined Instruction Mode and set its Stack Pointer + MSR CPSR_c, #Mode_UND:OR:I_Bit:OR:F_Bit + MOV SP, R0 + SUB R0, R0, #UND_Stack_Size + +; Enter Abort Mode and set its Stack Pointer + MSR CPSR_c, #Mode_ABT:OR:I_Bit:OR:F_Bit + MOV SP, R0 + SUB R0, R0, #ABT_Stack_Size + +; Enter FIQ Mode and set its Stack Pointer + MSR CPSR_c, #Mode_FIQ:OR:I_Bit:OR:F_Bit + MOV SP, R0 + SUB R0, R0, #FIQ_Stack_Size + +; Enter IRQ Mode and set its Stack Pointer + MSR CPSR_c, #Mode_IRQ:OR:I_Bit:OR:F_Bit + MOV SP, R0 + SUB R0, R0, #IRQ_Stack_Size + +; Enter Supervisor Mode and set its Stack Pointer + MSR CPSR_c, #Mode_SVC:OR:I_Bit:OR:F_Bit + MOV SP, R0 + SUB R0, R0, #SVC_Stack_Size + +; Enter User Mode and set its Stack Pointer + ; MSR CPSR_c, #Mode_USR + MOV SP, R0 + SUB SL, SP, #USR_Stack_Size + +; Enter the C code ------------------------------------------------------------- + + IMPORT __main + LDR R0, =__main + BX R0 + + IMPORT rt_interrupt_enter + IMPORT rt_interrupt_leave + IMPORT rt_thread_switch_interrupt_flag + IMPORT rt_interrupt_from_thread + IMPORT rt_interrupt_to_thread + IMPORT rt_hw_trap_irq + +IRQ_Handler PROC + EXPORT IRQ_Handler + STMFD sp!, {r0-r12,lr} + BL rt_interrupt_enter + BL rt_hw_trap_irq + BL rt_interrupt_leave + + ; if rt_thread_switch_interrupt_flag set, jump to + ; rt_hw_context_switch_interrupt_do and don't return + LDR r0, =rt_thread_switch_interrupt_flag + LDR r1, [r0] + CMP r1, #1 + BEQ rt_hw_context_switch_interrupt_do + + LDMFD sp!, {r0-r12,lr} + SUBS pc, lr, #4 + ENDP + +; /* +; * void rt_hw_context_switch_interrupt_do(rt_base_t flag) +; */ +rt_hw_context_switch_interrupt_do PROC + EXPORT rt_hw_context_switch_interrupt_do + MOV r1, #0 ; clear flag + STR r1, [r0] + + LDMFD sp!, {r0-r12,lr}; reload saved registers + STMFD sp!, {r0-r3} ; save r0-r3 + MOV r1, sp + ADD sp, sp, #16 ; restore sp + SUB r2, lr, #4 ; save old task's pc to r2 + + MRS r3, spsr ; get cpsr of interrupt thread + + ; switch to SVC mode and no interrupt + MSR cpsr_c, #I_Bit:OR:F_Bit:OR:Mode_SVC + + STMFD sp!, {r2} ; push old task's pc + STMFD sp!, {r4-r12,lr}; push old task's lr,r12-r4 + MOV r4, r1 ; Special optimised code below + MOV r5, r3 + LDMFD r4!, {r0-r3} + STMFD sp!, {r0-r3} ; push old task's r3-r0 + STMFD sp!, {r5} ; push old task's cpsr + MRS r4, spsr + STMFD sp!, {r4} ; push old task's spsr + + LDR r4, =rt_interrupt_from_thread + LDR r5, [r4] + STR sp, [r5] ; store sp in preempted tasks's TCB + + LDR r6, =rt_interrupt_to_thread + LDR r6, [r6] + LDR sp, [r6] ; get new task's stack pointer + + LDMFD sp!, {r4} ; pop new task's spsr + MSR spsr_cxsf, r4 + LDMFD sp!, {r4} ; pop new task's psr + MSR cpsr_cxsf, r4 + + LDMFD sp!, {r0-r12,lr,pc} ; pop new task's r0-r12,lr & pc + ENDP + + IF :DEF:__MICROLIB + + EXPORT __heap_base + EXPORT __heap_limit + + ELSE +; User Initial Stack & Heap + AREA |.text|, CODE, READONLY + + IMPORT __use_two_region_memory + EXPORT __user_initial_stackheap +__user_initial_stackheap + + LDR R0, = Heap_Mem + LDR R1, =(Stack_Mem + USR_Stack_Size) + LDR R2, = (Heap_Mem + Heap_Size) + LDR R3, = Stack_Mem + BX LR + ENDIF + + + END + diff --git a/libcpu/arm/at91sam926x/system_clock.c b/libcpu/arm/at91sam926x/system_clock.c index 415e518258..8af42bfccf 100755 --- a/libcpu/arm/at91sam926x/system_clock.c +++ b/libcpu/arm/at91sam926x/system_clock.c @@ -1,294 +1,294 @@ -/*
- * File : clock.c
- * This file is part of RT-Thread RTOS
- * COPYRIGHT (C) 2006, RT-Thread Development Team
- *
- * The license and distribution terms for this file may be
- * found in the file LICENSE in this distribution or at
- * http://openlab.rt-thread.com/license/LICENSE
- *
- * Change Logs:
- * Date Author Notes
- * 2011-01-13 weety first version
- */
-
-#include <rtthread.h>
-#include "at91sam926x.h"
-
-static rt_list_t clocks;
-
-struct clk {
- char name[32];
- rt_uint32_t rate_hz;
- struct clk *parent;
- rt_list_t node;
-};
-
-static struct clk clk32k = {
- "clk32k",
- AT91_SLOW_CLOCK,
- RT_NULL,
- {RT_NULL, RT_NULL},
-};
-
-static struct clk main_clk = {
- "main",
- 0,
- RT_NULL,
- {RT_NULL, RT_NULL},
-};
-
-static struct clk plla = {
- "plla",
- 0,
- RT_NULL,
- {RT_NULL, RT_NULL},
-};
-
-static struct clk mck = {
- "mck",
- 0,
- RT_NULL,
- {RT_NULL, RT_NULL},
-};
-
-static struct clk uhpck = {
- "uhpck",
- 0,
- RT_NULL,
- {RT_NULL, RT_NULL},
-};
-
-static struct clk pllb = {
- "pllb",
- 0,
- &main_clk,
- {RT_NULL, RT_NULL},
-};
-
-static struct clk udpck = {
- "udpck",
- 0,
- &pllb,
- {RT_NULL, RT_NULL},
-};
-
-static struct clk *const standard_pmc_clocks[] = {
- /* four primary clocks */
- &clk32k,
- &main_clk,
- &plla,
-
- /* MCK */
- &mck
-};
-
-/* clocks cannot be de-registered no refcounting necessary */
-struct clk *clk_get(const char *id)
-{
- struct clk *clk;
- rt_list_t *list;
-
- for (list = (&clocks)->next; list != &clocks; list = list->next)
- {
- clk = (struct clk *)rt_list_entry(list, struct clk, node);
- if (rt_strcmp(id, clk->name) == 0)
- return clk;
- }
-
- return RT_NULL;
-}
-
-rt_uint32_t clk_get_rate(struct clk *clk)
-{
- rt_uint32_t flags;
- rt_uint32_t rate;
-
- for (;;) {
- rate = clk->rate_hz;
- if (rate || !clk->parent)
- break;
- clk = clk->parent;
- }
- return rate;
-}
-
-static rt_uint32_t at91_pll_rate(struct clk *pll, rt_uint32_t freq, rt_uint32_t reg)
-{
- unsigned mul, div;
-
- div = reg & 0xff;
- mul = (reg >> 16) & 0x7ff;
- if (div && mul) {
- freq /= div;
- freq *= mul + 1;
- } else
- freq = 0;
-
- return freq;
-}
-
-static unsigned at91_pll_calc(unsigned main_freq, unsigned out_freq)
-{
- unsigned i, div = 0, mul = 0, diff = 1 << 30;
- unsigned ret = (out_freq > 155000000) ? 0xbe00 : 0x3e00;
-
- /* PLL output max 240 MHz (or 180 MHz per errata) */
- if (out_freq > 240000000)
- goto fail;
-
- for (i = 1; i < 256; i++) {
- int diff1;
- unsigned input, mul1;
-
- /*
- * PLL input between 1MHz and 32MHz per spec, but lower
- * frequences seem necessary in some cases so allow 100K.
- * Warning: some newer products need 2MHz min.
- */
- input = main_freq / i;
- if (input < 100000)
- continue;
- if (input > 32000000)
- continue;
-
- mul1 = out_freq / input;
- if (mul1 > 2048)
- continue;
- if (mul1 < 2)
- goto fail;
-
- diff1 = out_freq - input * mul1;
- if (diff1 < 0)
- diff1 = -diff1;
- if (diff > diff1) {
- diff = diff1;
- div = i;
- mul = mul1;
- if (diff == 0)
- break;
- }
- }
- if (i == 256 && diff > (out_freq >> 5))
- goto fail;
- return ret | ((mul - 1) << 16) | div;
-fail:
- return 0;
-}
-
-static rt_uint32_t at91_usb_rate(struct clk *pll, rt_uint32_t freq, rt_uint32_t reg)
-{
- if (pll == &pllb && (reg & AT91_PMC_USB96M))
- return freq / 2;
- else
- return freq;
-}
-
-
-/* PLLB generated USB full speed clock init */
-static void at91_pllb_usbfs_clock_init(rt_uint32_t main_clock)
-{
- rt_uint32_t at91_pllb_usb_init;
- /*
- * USB clock init: choose 48 MHz PLLB value,
- * disable 48MHz clock during usb peripheral suspend.
- *
- * REVISIT: assumes MCK doesn't derive from PLLB!
- */
- uhpck.parent = &pllb;
-
- at91_pllb_usb_init = at91_pll_calc(main_clock, 48000000 * 2) | AT91_PMC_USB96M;
- pllb.rate_hz = at91_pll_rate(&pllb, main_clock, at91_pllb_usb_init);
-
- at91_sys_write(AT91_CKGR_PLLBR, 0);
-
- udpck.rate_hz = at91_usb_rate(&pllb, pllb.rate_hz, at91_pllb_usb_init);
- uhpck.rate_hz = at91_usb_rate(&pllb, pllb.rate_hz, at91_pllb_usb_init);
-}
-
-static struct clk *at91_css_to_clk(unsigned long css)
-{
- switch (css) {
- case AT91_PMC_CSS_SLOW:
- return &clk32k;
- case AT91_PMC_CSS_MAIN:
- return &main_clk;
- case AT91_PMC_CSS_PLLA:
- return &plla;
- case AT91_PMC_CSS_PLLB:
- return &pllb;
- }
-
- return RT_NULL;
-}
-
-#define false 0
-#define true 1
-int at91_clock_init(rt_uint32_t main_clock)
-{
- unsigned tmp, freq, mckr;
- int i;
- int pll_overclock = false;
-
- /*
- * When the bootloader initialized the main oscillator correctly,
- * there's no problem using the cycle counter. But if it didn't,
- * or when using oscillator bypass mode, we must be told the speed
- * of the main clock.
- */
- if (!main_clock) {
- do {
- tmp = at91_sys_read(AT91_CKGR_MCFR);
- } while (!(tmp & AT91_PMC_MAINRDY));
- main_clock = (tmp & AT91_PMC_MAINF) * (AT91_SLOW_CLOCK / 16);
- }
- main_clk.rate_hz = main_clock;
-
- /* report if PLLA is more than mildly overclocked */
- plla.rate_hz = at91_pll_rate(&plla, main_clock, at91_sys_read(AT91_CKGR_PLLAR));
- if (plla.rate_hz > 209000000)
- pll_overclock = true;
- if (pll_overclock)
- ;//rt_kprintf("Clocks: PLLA overclocked, %ld MHz\n", plla.rate_hz / 1000000);
-
- at91_pllb_usbfs_clock_init(main_clock);
-
- /*
- * MCK and CPU derive from one of those primary clocks.
- * For now, assume this parentage won't change.
- */
- mckr = at91_sys_read(AT91_PMC_MCKR);
- mck.parent = at91_css_to_clk(mckr & AT91_PMC_CSS);
- freq = mck.parent->rate_hz;
- freq /= (1 << ((mckr & AT91_PMC_PRES) >> 2)); /* prescale */
-
- mck.rate_hz = freq / (1 << ((mckr & AT91_PMC_MDIV) >> 8)); /* mdiv */
-
- /* Register the PMC's standard clocks */
- rt_list_init(&clocks);
- for (i = 0; i < ARRAY_SIZE(standard_pmc_clocks); i++)
- rt_list_insert_after(&clocks, &standard_pmc_clocks[i]->node);
-
- rt_list_insert_after(&clocks, &pllb.node);
- rt_list_insert_after(&clocks, &uhpck.node);
- rt_list_insert_after(&clocks, &udpck.node);
-
- /* MCK and CPU clock are "always on" */
- //clk_enable(&mck);
-
- /*rt_kprintf("Clocks: CPU %u MHz, master %u MHz, main %u.%03u MHz\n",
- freq / 1000000, (unsigned) mck.rate_hz / 1000000,
- (unsigned) main_clock / 1000000,
- ((unsigned) main_clock % 1000000) / 1000);*///cause blocked
-
- return 0;
-}
-
-/**
- * @brief System Clock Configuration
- */
-void rt_hw_clock_init(void)
-{
- at91_clock_init(18432000);
-}
-
+/* + * File : clock.c + * This file is part of RT-Thread RTOS + * COPYRIGHT (C) 2006, RT-Thread Development Team + * + * The license and distribution terms for this file may be + * found in the file LICENSE in this distribution or at + * http://openlab.rt-thread.com/license/LICENSE + * + * Change Logs: + * Date Author Notes + * 2011-01-13 weety first version + */ + +#include <rtthread.h> +#include "at91sam926x.h" + +static rt_list_t clocks; + +struct clk { + char name[32]; + rt_uint32_t rate_hz; + struct clk *parent; + rt_list_t node; +}; + +static struct clk clk32k = { + "clk32k", + AT91_SLOW_CLOCK, + RT_NULL, + {RT_NULL, RT_NULL}, +}; + +static struct clk main_clk = { + "main", + 0, + RT_NULL, + {RT_NULL, RT_NULL}, +}; + +static struct clk plla = { + "plla", + 0, + RT_NULL, + {RT_NULL, RT_NULL}, +}; + +static struct clk mck = { + "mck", + 0, + RT_NULL, + {RT_NULL, RT_NULL}, +}; + +static struct clk uhpck = { + "uhpck", + 0, + RT_NULL, + {RT_NULL, RT_NULL}, +}; + +static struct clk pllb = { + "pllb", + 0, + &main_clk, + {RT_NULL, RT_NULL}, +}; + +static struct clk udpck = { + "udpck", + 0, + &pllb, + {RT_NULL, RT_NULL}, +}; + +static struct clk *const standard_pmc_clocks[] = { + /* four primary clocks */ + &clk32k, + &main_clk, + &plla, + + /* MCK */ + &mck +}; + +/* clocks cannot be de-registered no refcounting necessary */ +struct clk *clk_get(const char *id) +{ + struct clk *clk; + rt_list_t *list; + + for (list = (&clocks)->next; list != &clocks; list = list->next) + { + clk = (struct clk *)rt_list_entry(list, struct clk, node); + if (rt_strcmp(id, clk->name) == 0) + return clk; + } + + return RT_NULL; +} + +rt_uint32_t clk_get_rate(struct clk *clk) +{ + rt_uint32_t flags; + rt_uint32_t rate; + + for (;;) { + rate = clk->rate_hz; + if (rate || !clk->parent) + break; + clk = clk->parent; + } + return rate; +} + +static rt_uint32_t at91_pll_rate(struct clk *pll, rt_uint32_t freq, rt_uint32_t reg) +{ + unsigned mul, div; + + div = reg & 0xff; + mul = (reg >> 16) & 0x7ff; + if (div && mul) { + freq /= div; + freq *= mul + 1; + } else + freq = 0; + + return freq; +} + +static unsigned at91_pll_calc(unsigned main_freq, unsigned out_freq) +{ + unsigned i, div = 0, mul = 0, diff = 1 << 30; + unsigned ret = (out_freq > 155000000) ? 0xbe00 : 0x3e00; + + /* PLL output max 240 MHz (or 180 MHz per errata) */ + if (out_freq > 240000000) + goto fail; + + for (i = 1; i < 256; i++) { + int diff1; + unsigned input, mul1; + + /* + * PLL input between 1MHz and 32MHz per spec, but lower + * frequences seem necessary in some cases so allow 100K. + * Warning: some newer products need 2MHz min. + */ + input = main_freq / i; + if (input < 100000) + continue; + if (input > 32000000) + continue; + + mul1 = out_freq / input; + if (mul1 > 2048) + continue; + if (mul1 < 2) + goto fail; + + diff1 = out_freq - input * mul1; + if (diff1 < 0) + diff1 = -diff1; + if (diff > diff1) { + diff = diff1; + div = i; + mul = mul1; + if (diff == 0) + break; + } + } + if (i == 256 && diff > (out_freq >> 5)) + goto fail; + return ret | ((mul - 1) << 16) | div; +fail: + return 0; +} + +static rt_uint32_t at91_usb_rate(struct clk *pll, rt_uint32_t freq, rt_uint32_t reg) +{ + if (pll == &pllb && (reg & AT91_PMC_USB96M)) + return freq / 2; + else + return freq; +} + + +/* PLLB generated USB full speed clock init */ +static void at91_pllb_usbfs_clock_init(rt_uint32_t main_clock) +{ + rt_uint32_t at91_pllb_usb_init; + /* + * USB clock init: choose 48 MHz PLLB value, + * disable 48MHz clock during usb peripheral suspend. + * + * REVISIT: assumes MCK doesn't derive from PLLB! + */ + uhpck.parent = &pllb; + + at91_pllb_usb_init = at91_pll_calc(main_clock, 48000000 * 2) | AT91_PMC_USB96M; + pllb.rate_hz = at91_pll_rate(&pllb, main_clock, at91_pllb_usb_init); + + at91_sys_write(AT91_CKGR_PLLBR, 0); + + udpck.rate_hz = at91_usb_rate(&pllb, pllb.rate_hz, at91_pllb_usb_init); + uhpck.rate_hz = at91_usb_rate(&pllb, pllb.rate_hz, at91_pllb_usb_init); +} + +static struct clk *at91_css_to_clk(unsigned long css) +{ + switch (css) { + case AT91_PMC_CSS_SLOW: + return &clk32k; + case AT91_PMC_CSS_MAIN: + return &main_clk; + case AT91_PMC_CSS_PLLA: + return &plla; + case AT91_PMC_CSS_PLLB: + return &pllb; + } + + return RT_NULL; +} + +#define false 0 +#define true 1 +int at91_clock_init(rt_uint32_t main_clock) +{ + unsigned tmp, freq, mckr; + int i; + int pll_overclock = false; + + /* + * When the bootloader initialized the main oscillator correctly, + * there's no problem using the cycle counter. But if it didn't, + * or when using oscillator bypass mode, we must be told the speed + * of the main clock. + */ + if (!main_clock) { + do { + tmp = at91_sys_read(AT91_CKGR_MCFR); + } while (!(tmp & AT91_PMC_MAINRDY)); + main_clock = (tmp & AT91_PMC_MAINF) * (AT91_SLOW_CLOCK / 16); + } + main_clk.rate_hz = main_clock; + + /* report if PLLA is more than mildly overclocked */ + plla.rate_hz = at91_pll_rate(&plla, main_clock, at91_sys_read(AT91_CKGR_PLLAR)); + if (plla.rate_hz > 209000000) + pll_overclock = true; + if (pll_overclock) + ;//rt_kprintf("Clocks: PLLA overclocked, %ld MHz\n", plla.rate_hz / 1000000); + + at91_pllb_usbfs_clock_init(main_clock); + + /* + * MCK and CPU derive from one of those primary clocks. + * For now, assume this parentage won't change. + */ + mckr = at91_sys_read(AT91_PMC_MCKR); + mck.parent = at91_css_to_clk(mckr & AT91_PMC_CSS); + freq = mck.parent->rate_hz; + freq /= (1 << ((mckr & AT91_PMC_PRES) >> 2)); /* prescale */ + + mck.rate_hz = freq / (1 << ((mckr & AT91_PMC_MDIV) >> 8)); /* mdiv */ + + /* Register the PMC's standard clocks */ + rt_list_init(&clocks); + for (i = 0; i < ARRAY_SIZE(standard_pmc_clocks); i++) + rt_list_insert_after(&clocks, &standard_pmc_clocks[i]->node); + + rt_list_insert_after(&clocks, &pllb.node); + rt_list_insert_after(&clocks, &uhpck.node); + rt_list_insert_after(&clocks, &udpck.node); + + /* MCK and CPU clock are "always on" */ + //clk_enable(&mck); + + /*rt_kprintf("Clocks: CPU %u MHz, master %u MHz, main %u.%03u MHz\n", + freq / 1000000, (unsigned) mck.rate_hz / 1000000, + (unsigned) main_clock / 1000000, + ((unsigned) main_clock % 1000000) / 1000);*///cause blocked + + return 0; +} + +/** + * @brief System Clock Configuration + */ +void rt_hw_clock_init(void) +{ + at91_clock_init(18432000); +} + diff --git a/libcpu/arm/common/backtrace.c b/libcpu/arm/common/backtrace.c index 764c0f5e1b..a9f9f63bf8 100644 --- a/libcpu/arm/common/backtrace.c +++ b/libcpu/arm/common/backtrace.c @@ -1,67 +1,67 @@ -/*
- * File : backtrace.c
- * This file is part of RT-Thread RTOS
- * COPYRIGHT (C) 2006, 2008 RT-Thread Development Team
- *
- * The license and distribution terms for this file may be
- * found in the file LICENSE in this distribution or at
- * http://openlab.rt-thread.com/license/LICENSE
- *
- * Change Logs:
- * Date Author Notes
- * 2008-07-29 Bernard first version from QiuYi implementation
- */
-
-#include <rtthread.h>
-
-#ifdef __GNUC__
-/*
--->High Address,Stack Top
-PC<-----|
-LR |
-IP |
-FP |
-...... |
-PC<-| |
-LR | |
-IP | |
-FP---|-- |
-...... |
-PC |
-LR |
-IP |
-FP---
--->Low Address,Stack Bottom
-*/
-void rt_hw_backtrace(rt_uint32_t *fp, rt_uint32_t thread_entry)
-{
- rt_uint32_t i, pc, func_entry;
-
- pc = *fp;
- rt_kprintf("[0x%x]\n", pc-0xC);
-
- for(i=0; i<10; i++)
- {
- fp = (rt_uint32_t *)*(fp - 3);
- pc = *fp ;
-
- func_entry = pc - 0xC;
-
- if(func_entry <= 0x30000000) break;
-
- if((func_entry == thread_entry))
- {
- rt_kprintf("EntryPoint:0x%x\n", func_entry);
-
- break;
- }
-
- rt_kprintf("[0x%x]\n", func_entry);
- }
-}
-#else
-void rt_hw_backtrace(rt_uint32_t *fp, rt_uint32_t thread_entry)
-{
- /* old compiler implementation */
-}
-#endif
+/* + * File : backtrace.c + * This file is part of RT-Thread RTOS + * COPYRIGHT (C) 2006, 2008 RT-Thread Development Team + * + * The license and distribution terms for this file may be + * found in the file LICENSE in this distribution or at + * http://openlab.rt-thread.com/license/LICENSE + * + * Change Logs: + * Date Author Notes + * 2008-07-29 Bernard first version from QiuYi implementation + */ + +#include <rtthread.h> + +#ifdef __GNUC__ +/* +-->High Address,Stack Top +PC<-----| +LR | +IP | +FP | +...... | +PC<-| | +LR | | +IP | | +FP---|-- | +...... | +PC | +LR | +IP | +FP--- +-->Low Address,Stack Bottom +*/ +void rt_hw_backtrace(rt_uint32_t *fp, rt_uint32_t thread_entry) +{ + rt_uint32_t i, pc, func_entry; + + pc = *fp; + rt_kprintf("[0x%x]\n", pc-0xC); + + for(i=0; i<10; i++) + { + fp = (rt_uint32_t *)*(fp - 3); + pc = *fp ; + + func_entry = pc - 0xC; + + if(func_entry <= 0x30000000) break; + + if((func_entry == thread_entry)) + { + rt_kprintf("EntryPoint:0x%x\n", func_entry); + + break; + } + + rt_kprintf("[0x%x]\n", func_entry); + } +} +#else +void rt_hw_backtrace(rt_uint32_t *fp, rt_uint32_t thread_entry) +{ + /* old compiler implementation */ +} +#endif diff --git a/libcpu/arm/common/showmem.c b/libcpu/arm/common/showmem.c index c171a9bcd7..38f037f83d 100644 --- a/libcpu/arm/common/showmem.c +++ b/libcpu/arm/common/showmem.c @@ -1,42 +1,42 @@ -/*
- * File : showmem.c
- * This file is part of RT-Thread RTOS
- * COPYRIGHT (C) 2006, 2008 RT-Thread Development Team
- *
- * The license and distribution terms for this file may be
- * found in the file LICENSE in this distribution or at
- * http://openlab.rt-thread.com/license/LICENSE
- *
- * Change Logs:
- * Date Author Notes
- * 2008-07-29 Bernard first version from QiuYi implementation
- */
-
-#include <rtthread.h>
-
-void rt_hw_show_memory(rt_uint32_t addr, rt_uint32_t size)
-{
- int i = 0, j =0;
-
- RT_ASSERT(addr);
-
- addr = addr & ~0xF;
- size = 4*((size + 3)/4);
-
- while(i < size)
- {
- rt_kprintf("0x%08x: ", addr );
-
- for(j=0; j<4; j++)
- {
- rt_kprintf("0x%08x ", *(rt_uint32_t *)addr);
-
- addr += 4;
- i++;
- }
-
- rt_kprintf("\n");
- }
-
- return;
-}
+/* + * File : showmem.c + * This file is part of RT-Thread RTOS + * COPYRIGHT (C) 2006, 2008 RT-Thread Development Team + * + * The license and distribution terms for this file may be + * found in the file LICENSE in this distribution or at + * http://openlab.rt-thread.com/license/LICENSE + * + * Change Logs: + * Date Author Notes + * 2008-07-29 Bernard first version from QiuYi implementation + */ + +#include <rtthread.h> + +void rt_hw_show_memory(rt_uint32_t addr, rt_uint32_t size) +{ + int i = 0, j =0; + + RT_ASSERT(addr); + + addr = addr & ~0xF; + size = 4*((size + 3)/4); + + while(i < size) + { + rt_kprintf("0x%08x: ", addr ); + + for(j=0; j<4; j++) + { + rt_kprintf("0x%08x ", *(rt_uint32_t *)addr); + + addr += 4; + i++; + } + + rt_kprintf("\n"); + } + + return; +} diff --git a/libcpu/arm/cortex-m0/context_iar.S b/libcpu/arm/cortex-m0/context_iar.S index 500e46d065..9b8a7dddb1 100644 --- a/libcpu/arm/cortex-m0/context_iar.S +++ b/libcpu/arm/cortex-m0/context_iar.S @@ -1,201 +1,201 @@ -;/*
-; * File : context_iar.S
-; * This file is part of RT-Thread RTOS
-; * COPYRIGHT (C) 2009, RT-Thread Development Team
-; *
-; * The license and distribution terms for this file may be
-; * found in the file LICENSE in this distribution or at
-; * http://www.rt-thread.org/license/LICENSE
-; *
-; * Change Logs:
-; * Date Author Notes
-; * 2010-01-25 Bernard first version
-; * 2012-06-01 aozima set pendsv priority to 0xFF.
-; * 2012-08-17 aozima fixed bug: store r8 - r11.
-; */
-
-;/**
-; * @addtogroup CORTEX-M0
-; */
-;/*@{*/
-
-NVIC_INT_CTRL EQU 0xE000ED04 ; interrupt control state register
-NVIC_SHPR3 EQU 0xE000ED20 ; system priority register (2)
-NVIC_PENDSV_PRI EQU 0x00FF0000 ; PendSV priority value (lowest)
-NVIC_PENDSVSET EQU 0x10000000 ; value to trigger PendSV exception
-
- SECTION .text:CODE(2)
- THUMB
- REQUIRE8
- PRESERVE8
-
- IMPORT rt_thread_switch_interrupt_flag
- IMPORT rt_interrupt_from_thread
- IMPORT rt_interrupt_to_thread
-
-;/*
-; * rt_base_t rt_hw_interrupt_disable();
-; */
- EXPORT rt_hw_interrupt_disable
-rt_hw_interrupt_disable:
- MRS r0, PRIMASK
- CPSID I
- BX LR
-
-;/*
-; * void rt_hw_interrupt_enable(rt_base_t level);
-; */
- EXPORT rt_hw_interrupt_enable
-rt_hw_interrupt_enable:
- MSR PRIMASK, r0
- BX LR
-
-;/*
-; * void rt_hw_context_switch(rt_uint32 from, rt_uint32 to);
-; * r0 --> from
-; * r1 --> to
-; */
- EXPORT rt_hw_context_switch_interrupt
- EXPORT rt_hw_context_switch
-rt_hw_context_switch_interrupt:
-rt_hw_context_switch:
- ; set rt_thread_switch_interrupt_flag to 1
- LDR r2, =rt_thread_switch_interrupt_flag
- LDR r3, [r2]
- CMP r3, #1
- BEQ _reswitch
- MOVS r3, #0x1
- STR r3, [r2]
-
- LDR r2, =rt_interrupt_from_thread ; set rt_interrupt_from_thread
- STR r0, [r2]
-
-_reswitch
- LDR r2, =rt_interrupt_to_thread ; set rt_interrupt_to_thread
- STR r1, [r2]
-
- LDR r0, =NVIC_INT_CTRL ; trigger the PendSV exception (causes context switch)
- LDR r1, =NVIC_PENDSVSET
- STR r1, [r0]
- BX LR
-
-; r0 --> swith from thread stack
-; r1 --> swith to thread stack
-; psr, pc, lr, r12, r3, r2, r1, r0 are pushed into [from] stack
- EXPORT PendSV_Handler
-PendSV_Handler:
-
- ; disable interrupt to protect context switch
- MRS r2, PRIMASK
- CPSID I
-
- ; get rt_thread_switch_interrupt_flag
- LDR r0, =rt_thread_switch_interrupt_flag
- LDR r1, [r0]
- CMP r1, #0x00
- BEQ pendsv_exit ; pendsv already handled
-
- ; clear rt_thread_switch_interrupt_flag to 0
- MOVS r1, #0x00
- STR r1, [r0]
-
- LDR r0, =rt_interrupt_from_thread
- LDR r1, [r0]
- CMP r1, #0x00
- BEQ swtich_to_thread ; skip register save at the first time
-
- MRS r1, psp ; get from thread stack pointer
-
- SUBS r1, r1, #0x20 ; space for {r4 - r7} and {r8 - r11}
- LDR r0, [r0]
- STR r1, [r0] ; update from thread stack pointer
-
- STMIA r1!, {r4 - r7} ; push thread {r4 - r7} register to thread stack
-
- MOV r4, r8 ; mov thread {r8 - r11} to {r4 - r7}
- MOV r5, r9
- MOV r6, r10
- MOV r7, r11
- STMIA r1!, {r4 - r7} ; push thread {r8 - r11} high register to thread stack
-
-swtich_to_thread
- LDR r1, =rt_interrupt_to_thread
- LDR r1, [r1]
- LDR r1, [r1] ; load thread stack pointer
-
- LDMIA r1!, {r4 - r7} ; pop thread {r4 - r7} register from thread stack
- PUSH {r4 - r7} ; push {r4 - r7} to MSP for copy {r8 - r11}
-
- LDMIA r1!, {r4 - r7} ; pop thread {r8 - r11} high register from thread stack to {r4 - r7}
- MOV r8, r4 ; mov {r4 - r7} to {r8 - r11}
- MOV r9, r5
- MOV r10, r6
- MOV r11, r7
-
- POP {r4 - r7} ; pop {r4 - r7} from MSP
-
- MSR psp, r1 ; update stack pointer
-
-pendsv_exit
- ; restore interrupt
- MSR PRIMASK, r2
-
- MOVS r0, #0x04
- RSBS r0, r0, #0x00
- BX r0
-
-;/*
-; * void rt_hw_context_switch_to(rt_uint32 to);
-; * r0 --> to
-; * this fucntion is used to perform the first thread switch
-; */
- EXPORT rt_hw_context_switch_to
-rt_hw_context_switch_to:
- ; set to thread
- LDR r1, =rt_interrupt_to_thread
- STR r0, [r1]
-
- ; set from thread to 0
- LDR r1, =rt_interrupt_from_thread
- MOVS r0, #0x0
- STR r0, [r1]
-
- ; set interrupt flag to 1
- LDR r1, =rt_thread_switch_interrupt_flag
- MOVS r0, #1
- STR r0, [r1]
-
- ; set the PendSV exception priority
- LDR r0, =NVIC_SHPR3
- LDR r1, =NVIC_PENDSV_PRI
- LDR r2, [r0,#0x00] ; read
- ORRS r1,r1,r2 ; modify
- STR r1, [r0] ; write-back
-
- ; trigger the PendSV exception (causes context switch)
- LDR r0, =NVIC_INT_CTRL
- LDR r1, =NVIC_PENDSVSET
- STR r1, [r0]
- NOP
-
- ; enable interrupts at processor level
- CPSIE I
-
- ; never reach here!
-
-; compatible with old version
- EXPORT rt_hw_interrupt_thread_switch
-rt_hw_interrupt_thread_switch:
- BX lr
-
- IMPORT rt_hw_hard_fault_exception
- EXPORT HardFault_Handler
-HardFault_Handler:
-
- ; get current context
- MRS r0, psp ; get fault thread stack pointer
- PUSH {lr}
- BL rt_hw_hard_fault_exception
- POP {pc}
-
- END
+;/* +; * File : context_iar.S +; * This file is part of RT-Thread RTOS +; * COPYRIGHT (C) 2009, RT-Thread Development Team +; * +; * The license and distribution terms for this file may be +; * found in the file LICENSE in this distribution or at +; * http://www.rt-thread.org/license/LICENSE +; * +; * Change Logs: +; * Date Author Notes +; * 2010-01-25 Bernard first version +; * 2012-06-01 aozima set pendsv priority to 0xFF. +; * 2012-08-17 aozima fixed bug: store r8 - r11. +; */ + +;/** +; * @addtogroup CORTEX-M0 +; */ +;/*@{*/ + +NVIC_INT_CTRL EQU 0xE000ED04 ; interrupt control state register +NVIC_SHPR3 EQU 0xE000ED20 ; system priority register (2) +NVIC_PENDSV_PRI EQU 0x00FF0000 ; PendSV priority value (lowest) +NVIC_PENDSVSET EQU 0x10000000 ; value to trigger PendSV exception + + SECTION .text:CODE(2) + THUMB + REQUIRE8 + PRESERVE8 + + IMPORT rt_thread_switch_interrupt_flag + IMPORT rt_interrupt_from_thread + IMPORT rt_interrupt_to_thread + +;/* +; * rt_base_t rt_hw_interrupt_disable(); +; */ + EXPORT rt_hw_interrupt_disable +rt_hw_interrupt_disable: + MRS r0, PRIMASK + CPSID I + BX LR + +;/* +; * void rt_hw_interrupt_enable(rt_base_t level); +; */ + EXPORT rt_hw_interrupt_enable +rt_hw_interrupt_enable: + MSR PRIMASK, r0 + BX LR + +;/* +; * void rt_hw_context_switch(rt_uint32 from, rt_uint32 to); +; * r0 --> from +; * r1 --> to +; */ + EXPORT rt_hw_context_switch_interrupt + EXPORT rt_hw_context_switch +rt_hw_context_switch_interrupt: +rt_hw_context_switch: + ; set rt_thread_switch_interrupt_flag to 1 + LDR r2, =rt_thread_switch_interrupt_flag + LDR r3, [r2] + CMP r3, #1 + BEQ _reswitch + MOVS r3, #0x1 + STR r3, [r2] + + LDR r2, =rt_interrupt_from_thread ; set rt_interrupt_from_thread + STR r0, [r2] + +_reswitch + LDR r2, =rt_interrupt_to_thread ; set rt_interrupt_to_thread + STR r1, [r2] + + LDR r0, =NVIC_INT_CTRL ; trigger the PendSV exception (causes context switch) + LDR r1, =NVIC_PENDSVSET + STR r1, [r0] + BX LR + +; r0 --> swith from thread stack +; r1 --> swith to thread stack +; psr, pc, lr, r12, r3, r2, r1, r0 are pushed into [from] stack + EXPORT PendSV_Handler +PendSV_Handler: + + ; disable interrupt to protect context switch + MRS r2, PRIMASK + CPSID I + + ; get rt_thread_switch_interrupt_flag + LDR r0, =rt_thread_switch_interrupt_flag + LDR r1, [r0] + CMP r1, #0x00 + BEQ pendsv_exit ; pendsv already handled + + ; clear rt_thread_switch_interrupt_flag to 0 + MOVS r1, #0x00 + STR r1, [r0] + + LDR r0, =rt_interrupt_from_thread + LDR r1, [r0] + CMP r1, #0x00 + BEQ swtich_to_thread ; skip register save at the first time + + MRS r1, psp ; get from thread stack pointer + + SUBS r1, r1, #0x20 ; space for {r4 - r7} and {r8 - r11} + LDR r0, [r0] + STR r1, [r0] ; update from thread stack pointer + + STMIA r1!, {r4 - r7} ; push thread {r4 - r7} register to thread stack + + MOV r4, r8 ; mov thread {r8 - r11} to {r4 - r7} + MOV r5, r9 + MOV r6, r10 + MOV r7, r11 + STMIA r1!, {r4 - r7} ; push thread {r8 - r11} high register to thread stack + +swtich_to_thread + LDR r1, =rt_interrupt_to_thread + LDR r1, [r1] + LDR r1, [r1] ; load thread stack pointer + + LDMIA r1!, {r4 - r7} ; pop thread {r4 - r7} register from thread stack + PUSH {r4 - r7} ; push {r4 - r7} to MSP for copy {r8 - r11} + + LDMIA r1!, {r4 - r7} ; pop thread {r8 - r11} high register from thread stack to {r4 - r7} + MOV r8, r4 ; mov {r4 - r7} to {r8 - r11} + MOV r9, r5 + MOV r10, r6 + MOV r11, r7 + + POP {r4 - r7} ; pop {r4 - r7} from MSP + + MSR psp, r1 ; update stack pointer + +pendsv_exit + ; restore interrupt + MSR PRIMASK, r2 + + MOVS r0, #0x04 + RSBS r0, r0, #0x00 + BX r0 + +;/* +; * void rt_hw_context_switch_to(rt_uint32 to); +; * r0 --> to +; * this fucntion is used to perform the first thread switch +; */ + EXPORT rt_hw_context_switch_to +rt_hw_context_switch_to: + ; set to thread + LDR r1, =rt_interrupt_to_thread + STR r0, [r1] + + ; set from thread to 0 + LDR r1, =rt_interrupt_from_thread + MOVS r0, #0x0 + STR r0, [r1] + + ; set interrupt flag to 1 + LDR r1, =rt_thread_switch_interrupt_flag + MOVS r0, #1 + STR r0, [r1] + + ; set the PendSV exception priority + LDR r0, =NVIC_SHPR3 + LDR r1, =NVIC_PENDSV_PRI + LDR r2, [r0,#0x00] ; read + ORRS r1,r1,r2 ; modify + STR r1, [r0] ; write-back + + ; trigger the PendSV exception (causes context switch) + LDR r0, =NVIC_INT_CTRL + LDR r1, =NVIC_PENDSVSET + STR r1, [r0] + NOP + + ; enable interrupts at processor level + CPSIE I + + ; never reach here! + +; compatible with old version + EXPORT rt_hw_interrupt_thread_switch +rt_hw_interrupt_thread_switch: + BX lr + + IMPORT rt_hw_hard_fault_exception + EXPORT HardFault_Handler +HardFault_Handler: + + ; get current context + MRS r0, psp ; get fault thread stack pointer + PUSH {lr} + BL rt_hw_hard_fault_exception + POP {pc} + + END diff --git a/libcpu/arm/cortex-m0/context_rvds.S b/libcpu/arm/cortex-m0/context_rvds.S index 29bef74684..1194d8f4ae 100644 --- a/libcpu/arm/cortex-m0/context_rvds.S +++ b/libcpu/arm/cortex-m0/context_rvds.S @@ -1,210 +1,210 @@ -;/*
-; * File : context_rvds.S
-; * This file is part of RT-Thread RTOS
-; * COPYRIGHT (C) 2009, RT-Thread Development Team
-; *
-; * The license and distribution terms for this file may be
-; * found in the file LICENSE in this distribution or at
-; * http://www.rt-thread.org/license/LICENSE
-; *
-; * Change Logs:
-; * Date Author Notes
-; * 2010-01-25 Bernard first version
-; * 2012-06-01 aozima set pendsv priority to 0xFF.
-; * 2012-08-17 aozima fixed bug: store r8 - r11.
-; */
-
-;/**
-; * @addtogroup CORTEX-M0
-; */
-;/*@{*/
-
-NVIC_INT_CTRL EQU 0xE000ED04 ; interrupt control state register
-NVIC_SHPR3 EQU 0xE000ED20 ; system priority register (2)
-NVIC_PENDSV_PRI EQU 0x00FF0000 ; PendSV priority value (lowest)
-NVIC_PENDSVSET EQU 0x10000000 ; value to trigger PendSV exception
-
- AREA |.text|, CODE, READONLY, ALIGN=2
- THUMB
- REQUIRE8
- PRESERVE8
-
- IMPORT rt_thread_switch_interrupt_flag
- IMPORT rt_interrupt_from_thread
- IMPORT rt_interrupt_to_thread
-
-;/*
-; * rt_base_t rt_hw_interrupt_disable();
-; */
-rt_hw_interrupt_disable PROC
- EXPORT rt_hw_interrupt_disable
- MRS r0, PRIMASK
- CPSID I
- BX LR
- ENDP
-
-;/*
-; * void rt_hw_interrupt_enable(rt_base_t level);
-; */
-rt_hw_interrupt_enable PROC
- EXPORT rt_hw_interrupt_enable
- MSR PRIMASK, r0
- BX LR
- ENDP
-
-;/*
-; * void rt_hw_context_switch(rt_uint32 from, rt_uint32 to);
-; * r0 --> from
-; * r1 --> to
-; */
-rt_hw_context_switch_interrupt
- EXPORT rt_hw_context_switch_interrupt
-rt_hw_context_switch PROC
- EXPORT rt_hw_context_switch
-
- ; set rt_thread_switch_interrupt_flag to 1
- LDR r2, =rt_thread_switch_interrupt_flag
- LDR r3, [r2]
- CMP r3, #1
- BEQ _reswitch
- MOVS r3, #0x01
- STR r3, [r2]
-
- LDR r2, =rt_interrupt_from_thread ; set rt_interrupt_from_thread
- STR r0, [r2]
-
-_reswitch
- LDR r2, =rt_interrupt_to_thread ; set rt_interrupt_to_thread
- STR r1, [r2]
-
- LDR r0, =NVIC_INT_CTRL ; trigger the PendSV exception (causes context switch)
- LDR r1, =NVIC_PENDSVSET
- STR r1, [r0]
- BX LR
- ENDP
-
-; r0 --> swith from thread stack
-; r1 --> swith to thread stack
-; psr, pc, lr, r12, r3, r2, r1, r0 are pushed into [from] stack
-PendSV_Handler PROC
- EXPORT PendSV_Handler
-
- ; disable interrupt to protect context switch
- MRS r2, PRIMASK
- CPSID I
-
- ; get rt_thread_switch_interrupt_flag
- LDR r0, =rt_thread_switch_interrupt_flag
- LDR r1, [r0]
- CMP r1, #0x00
- BEQ pendsv_exit ; pendsv already handled
-
- ; clear rt_thread_switch_interrupt_flag to 0
- MOVS r1, #0x00
- STR r1, [r0]
-
- LDR r0, =rt_interrupt_from_thread
- LDR r1, [r0]
- CMP r1, #0x00
- BEQ swtich_to_thread ; skip register save at the first time
-
- MRS r1, psp ; get from thread stack pointer
-
- SUBS r1, r1, #0x20 ; space for {r4 - r7} and {r8 - r11}
- LDR r0, [r0]
- STR r1, [r0] ; update from thread stack pointer
-
- STMIA r1!, {r4 - r7} ; push thread {r4 - r7} register to thread stack
-
- MOV r4, r8 ; mov thread {r8 - r11} to {r4 - r7}
- MOV r5, r9
- MOV r6, r10
- MOV r7, r11
- STMIA r1!, {r4 - r7} ; push thread {r8 - r11} high register to thread stack
-
-swtich_to_thread
- LDR r1, =rt_interrupt_to_thread
- LDR r1, [r1]
- LDR r1, [r1] ; load thread stack pointer
-
- LDMIA r1!, {r4 - r7} ; pop thread {r4 - r7} register from thread stack
- PUSH {r4 - r7} ; push {r4 - r7} to MSP for copy {r8 - r11}
-
- LDMIA r1!, {r4 - r7} ; pop thread {r8 - r11} high register from thread stack to {r4 - r7}
- MOV r8, r4 ; mov {r4 - r7} to {r8 - r11}
- MOV r9, r5
- MOV r10, r6
- MOV r11, r7
-
- POP {r4 - r7} ; pop {r4 - r7} from MSP
-
- MSR psp, r1 ; update stack pointer
-
-pendsv_exit
- ; restore interrupt
- MSR PRIMASK, r2
-
- MOVS r0, #0x04
- RSBS r0, r0, #0x00
- BX r0
- ENDP
-
-;/*
-; * void rt_hw_context_switch_to(rt_uint32 to);
-; * r0 --> to
-; * this fucntion is used to perform the first thread switch
-; */
-rt_hw_context_switch_to PROC
- EXPORT rt_hw_context_switch_to
- ; set to thread
- LDR r1, =rt_interrupt_to_thread
- STR r0, [r1]
-
- ; set from thread to 0
- LDR r1, =rt_interrupt_from_thread
- MOVS r0, #0x0
- STR r0, [r1]
-
- ; set interrupt flag to 1
- LDR r1, =rt_thread_switch_interrupt_flag
- MOVS r0, #1
- STR r0, [r1]
-
- ; set the PendSV exception priority
- LDR r0, =NVIC_SHPR3
- LDR r1, =NVIC_PENDSV_PRI
- LDR r2, [r0,#0x00] ; read
- ORRS r1,r1,r2 ; modify
- STR r1, [r0] ; write-back
-
- ; trigger the PendSV exception (causes context switch)
- LDR r0, =NVIC_INT_CTRL
- LDR r1, =NVIC_PENDSVSET
- STR r1, [r0]
- NOP
-
- ; enable interrupts at processor level
- CPSIE I
-
- ; never reach here!
- ENDP
-
-; compatible with old version
-rt_hw_interrupt_thread_switch PROC
- EXPORT rt_hw_interrupt_thread_switch
- BX lr
- ENDP
-
- IMPORT rt_hw_hard_fault_exception
-
-HardFault_Handler PROC
- EXPORT HardFault_Handler
-
- ; get current context
- MRS r0, psp ; get fault thread stack pointer
- PUSH {lr}
- BL rt_hw_hard_fault_exception
- POP {pc}
- ENDP
-
- END
+;/* +; * File : context_rvds.S +; * This file is part of RT-Thread RTOS +; * COPYRIGHT (C) 2009, RT-Thread Development Team +; * +; * The license and distribution terms for this file may be +; * found in the file LICENSE in this distribution or at +; * http://www.rt-thread.org/license/LICENSE +; * +; * Change Logs: +; * Date Author Notes +; * 2010-01-25 Bernard first version +; * 2012-06-01 aozima set pendsv priority to 0xFF. +; * 2012-08-17 aozima fixed bug: store r8 - r11. +; */ + +;/** +; * @addtogroup CORTEX-M0 +; */ +;/*@{*/ + +NVIC_INT_CTRL EQU 0xE000ED04 ; interrupt control state register +NVIC_SHPR3 EQU 0xE000ED20 ; system priority register (2) +NVIC_PENDSV_PRI EQU 0x00FF0000 ; PendSV priority value (lowest) +NVIC_PENDSVSET EQU 0x10000000 ; value to trigger PendSV exception + + AREA |.text|, CODE, READONLY, ALIGN=2 + THUMB + REQUIRE8 + PRESERVE8 + + IMPORT rt_thread_switch_interrupt_flag + IMPORT rt_interrupt_from_thread + IMPORT rt_interrupt_to_thread + +;/* +; * rt_base_t rt_hw_interrupt_disable(); +; */ +rt_hw_interrupt_disable PROC + EXPORT rt_hw_interrupt_disable + MRS r0, PRIMASK + CPSID I + BX LR + ENDP + +;/* +; * void rt_hw_interrupt_enable(rt_base_t level); +; */ +rt_hw_interrupt_enable PROC + EXPORT rt_hw_interrupt_enable + MSR PRIMASK, r0 + BX LR + ENDP + +;/* +; * void rt_hw_context_switch(rt_uint32 from, rt_uint32 to); +; * r0 --> from +; * r1 --> to +; */ +rt_hw_context_switch_interrupt + EXPORT rt_hw_context_switch_interrupt +rt_hw_context_switch PROC + EXPORT rt_hw_context_switch + + ; set rt_thread_switch_interrupt_flag to 1 + LDR r2, =rt_thread_switch_interrupt_flag + LDR r3, [r2] + CMP r3, #1 + BEQ _reswitch + MOVS r3, #0x01 + STR r3, [r2] + + LDR r2, =rt_interrupt_from_thread ; set rt_interrupt_from_thread + STR r0, [r2] + +_reswitch + LDR r2, =rt_interrupt_to_thread ; set rt_interrupt_to_thread + STR r1, [r2] + + LDR r0, =NVIC_INT_CTRL ; trigger the PendSV exception (causes context switch) + LDR r1, =NVIC_PENDSVSET + STR r1, [r0] + BX LR + ENDP + +; r0 --> swith from thread stack +; r1 --> swith to thread stack +; psr, pc, lr, r12, r3, r2, r1, r0 are pushed into [from] stack +PendSV_Handler PROC + EXPORT PendSV_Handler + + ; disable interrupt to protect context switch + MRS r2, PRIMASK + CPSID I + + ; get rt_thread_switch_interrupt_flag + LDR r0, =rt_thread_switch_interrupt_flag + LDR r1, [r0] + CMP r1, #0x00 + BEQ pendsv_exit ; pendsv already handled + + ; clear rt_thread_switch_interrupt_flag to 0 + MOVS r1, #0x00 + STR r1, [r0] + + LDR r0, =rt_interrupt_from_thread + LDR r1, [r0] + CMP r1, #0x00 + BEQ swtich_to_thread ; skip register save at the first time + + MRS r1, psp ; get from thread stack pointer + + SUBS r1, r1, #0x20 ; space for {r4 - r7} and {r8 - r11} + LDR r0, [r0] + STR r1, [r0] ; update from thread stack pointer + + STMIA r1!, {r4 - r7} ; push thread {r4 - r7} register to thread stack + + MOV r4, r8 ; mov thread {r8 - r11} to {r4 - r7} + MOV r5, r9 + MOV r6, r10 + MOV r7, r11 + STMIA r1!, {r4 - r7} ; push thread {r8 - r11} high register to thread stack + +swtich_to_thread + LDR r1, =rt_interrupt_to_thread + LDR r1, [r1] + LDR r1, [r1] ; load thread stack pointer + + LDMIA r1!, {r4 - r7} ; pop thread {r4 - r7} register from thread stack + PUSH {r4 - r7} ; push {r4 - r7} to MSP for copy {r8 - r11} + + LDMIA r1!, {r4 - r7} ; pop thread {r8 - r11} high register from thread stack to {r4 - r7} + MOV r8, r4 ; mov {r4 - r7} to {r8 - r11} + MOV r9, r5 + MOV r10, r6 + MOV r11, r7 + + POP {r4 - r7} ; pop {r4 - r7} from MSP + + MSR psp, r1 ; update stack pointer + +pendsv_exit + ; restore interrupt + MSR PRIMASK, r2 + + MOVS r0, #0x04 + RSBS r0, r0, #0x00 + BX r0 + ENDP + +;/* +; * void rt_hw_context_switch_to(rt_uint32 to); +; * r0 --> to +; * this fucntion is used to perform the first thread switch +; */ +rt_hw_context_switch_to PROC + EXPORT rt_hw_context_switch_to + ; set to thread + LDR r1, =rt_interrupt_to_thread + STR r0, [r1] + + ; set from thread to 0 + LDR r1, =rt_interrupt_from_thread + MOVS r0, #0x0 + STR r0, [r1] + + ; set interrupt flag to 1 + LDR r1, =rt_thread_switch_interrupt_flag + MOVS r0, #1 + STR r0, [r1] + + ; set the PendSV exception priority + LDR r0, =NVIC_SHPR3 + LDR r1, =NVIC_PENDSV_PRI + LDR r2, [r0,#0x00] ; read + ORRS r1,r1,r2 ; modify + STR r1, [r0] ; write-back + + ; trigger the PendSV exception (causes context switch) + LDR r0, =NVIC_INT_CTRL + LDR r1, =NVIC_PENDSVSET + STR r1, [r0] + NOP + + ; enable interrupts at processor level + CPSIE I + + ; never reach here! + ENDP + +; compatible with old version +rt_hw_interrupt_thread_switch PROC + EXPORT rt_hw_interrupt_thread_switch + BX lr + ENDP + + IMPORT rt_hw_hard_fault_exception + +HardFault_Handler PROC + EXPORT HardFault_Handler + + ; get current context + MRS r0, psp ; get fault thread stack pointer + PUSH {lr} + BL rt_hw_hard_fault_exception + POP {pc} + ENDP + + END diff --git a/libcpu/arm/cortex-m3/context_gcc.S b/libcpu/arm/cortex-m3/context_gcc.S index 6c981bdfb3..c0cf140daf 100644 --- a/libcpu/arm/cortex-m3/context_gcc.S +++ b/libcpu/arm/cortex-m3/context_gcc.S @@ -1,186 +1,186 @@ -/*
- * File : context_gcc.S
- * This file is part of RT-Thread RTOS
- * COPYRIGHT (C) 2009 - 2011, RT-Thread Development Team
- *
- * The license and distribution terms for this file may be
- * found in the file LICENSE in this distribution or at
- * http://www.rt-thread.org/license/LICENSE
- *
- * Change Logs:
- * Date Author Notes
- * 2009-10-11 Bernard First version
- * 2010-12-29 onelife Modify for EFM32
- * 2011-06-17 onelife Merge all of the assembly source code into context_gcc.S
- * 2011-07-12 onelife Add interrupt context check function
- */
-
- .cpu cortex-m3
- .fpu softvfp
- .syntax unified
- .thumb
- .text
-
- .equ ICSR, 0xE000ED04 /* interrupt control state register */
- .equ PENDSVSET_BIT, 0x10000000 /* value to trigger PendSV exception */
-
- .equ SHPR3, 0xE000ED20 /* system priority register (3) */
- .equ PENDSV_PRI_LOWEST, 0x00FF0000 /* PendSV priority value (lowest) */
-
-/*
- * rt_base_t rt_hw_interrupt_disable();
- */
- .global rt_hw_interrupt_disable
- .type rt_hw_interrupt_disable, %function
-rt_hw_interrupt_disable:
- MRS R0, PRIMASK
- CPSID I
- BX LR
-
-/*
- * void rt_hw_interrupt_enable(rt_base_t level);
- */
- .global rt_hw_interrupt_enable
- .type rt_hw_interrupt_enable, %function
-rt_hw_interrupt_enable:
- MSR PRIMASK, R0
- BX LR
-
-/*
- * void rt_hw_context_switch(rt_uint32 from, rt_uint32 to);
- * R0 --> from
- * R1 --> to
- */
- .global rt_hw_context_switch_interrupt
- .type rt_hw_context_switch_interrupt, %function
- .global rt_hw_context_switch
- .type rt_hw_context_switch, %function
-rt_hw_context_switch_interrupt:
-rt_hw_context_switch:
- /* set rt_thread_switch_interrupt_flag to 1 */
- LDR R2, =rt_thread_switch_interrupt_flag
- LDR R3, [R2]
- CMP R3, #1
- BEQ _reswitch
- MOV R3, #1
- STR R3, [R2]
-
- LDR R2, =rt_interrupt_from_thread /* set rt_interrupt_from_thread */
- STR R0, [R2]
-
-_reswitch:
- LDR R2, =rt_interrupt_to_thread /* set rt_interrupt_to_thread */
- STR R1, [R2]
-
- LDR R0, =ICSR /* trigger the PendSV exception (causes context switch) */
- LDR R1, =PENDSVSET_BIT
- STR R1, [R0]
- BX LR
-
-/* R0 --> swith from thread stack
- * R1 --> swith to thread stack
- * psr, pc, LR, R12, R3, R2, R1, R0 are pushed into [from] stack
- */
- .global PendSV_Handler
- .type PendSV_Handler, %function
-PendSV_Handler:
- /* disable interrupt to protect context switch */
- MRS R2, PRIMASK
- CPSID I
-
- /* get rt_thread_switch_interrupt_flag */
- LDR R0, =rt_thread_switch_interrupt_flag
- LDR R1, [R0]
- CBZ R1, pendsv_exit /* pendsv aLReady handled */
-
- /* clear rt_thread_switch_interrupt_flag to 0 */
- MOV R1, #0
- STR R1, [R0]
-
- LDR R0, =rt_interrupt_from_thread
- LDR R1, [R0]
- CBZ R1, swtich_to_thread /* skip register save at the first time */
-
- MRS R1, PSP /* get from thread stack pointer */
- STMFD R1!, {R4 - R11} /* push R4 - R11 register */
- LDR R0, [R0]
- STR R1, [R0] /* update from thread stack pointer */
-
-swtich_to_thread:
- LDR R1, =rt_interrupt_to_thread
- LDR R1, [R1]
- LDR R1, [R1] /* load thread stack pointer */
-
- LDMFD R1!, {R4 - R11} /* pop R4 - R11 register */
- MSR PSP, R1 /* update stack pointer */
-
-pendsv_exit:
- /* restore interrupt */
- MSR PRIMASK, R2
-
- ORR LR, LR, #0x04
- BX LR
-
-/*
- * void rt_hw_context_switch_to(rt_uint32 to);
- * R0 --> to
- */
- .global rt_hw_context_switch_to
- .type rt_hw_context_switch_to, %function
-rt_hw_context_switch_to:
- LDR R1, =rt_interrupt_to_thread
- STR R0, [R1]
-
- /* set from thread to 0 */
- LDR R1, =rt_interrupt_from_thread
- MOV R0, #0
- STR R0, [R1]
-
- /* set interrupt flag to 1 */
- LDR R1, =rt_thread_switch_interrupt_flag
- MOV R0, #1
- STR R0, [R1]
-
- /* set the PendSV exception priority */
- LDR R0, =SHPR3
- LDR R1, =PENDSV_PRI_LOWEST
- LDR.W R2, [R0,#0] /* read */
- ORR R1, R1, R2 /* modify */
- STR R1, [R0] /* write-back */
-
- LDR R0, =ICSR /* trigger the PendSV exception (causes context switch) */
- LDR R1, =PENDSVSET_BIT
- STR R1, [R0]
-
- CPSIE I /* enable interrupts at processor level */
-
- /* never reach here! */
-
-/* compatible with old version */
- .global rt_hw_interrupt_thread_switch
- .type rt_hw_interrupt_thread_switch, %function
-rt_hw_interrupt_thread_switch:
- BX LR
- NOP
-
- .global HardFault_Handler
- .type HardFault_Handler, %function
-HardFault_Handler:
- /* get current context */
- MRS R0, PSP /* get fault thread stack pointer */
- PUSH {LR}
- BL rt_hw_hard_fault_exception
- POP {LR}
-
- ORR LR, LR, #0x04
- BX LR
-
-/*
- * rt_uint32_t rt_hw_interrupt_check(void);
- * R0 --> state
- */
- .global rt_hw_interrupt_check
- .type rt_hw_interrupt_check, %function
-rt_hw_interrupt_check:
- MRS R0, IPSR
- BX LR
+/* + * File : context_gcc.S + * This file is part of RT-Thread RTOS + * COPYRIGHT (C) 2009 - 2011, RT-Thread Development Team + * + * The license and distribution terms for this file may be + * found in the file LICENSE in this distribution or at + * http://www.rt-thread.org/license/LICENSE + * + * Change Logs: + * Date Author Notes + * 2009-10-11 Bernard First version + * 2010-12-29 onelife Modify for EFM32 + * 2011-06-17 onelife Merge all of the assembly source code into context_gcc.S + * 2011-07-12 onelife Add interrupt context check function + */ + + .cpu cortex-m3 + .fpu softvfp + .syntax unified + .thumb + .text + + .equ ICSR, 0xE000ED04 /* interrupt control state register */ + .equ PENDSVSET_BIT, 0x10000000 /* value to trigger PendSV exception */ + + .equ SHPR3, 0xE000ED20 /* system priority register (3) */ + .equ PENDSV_PRI_LOWEST, 0x00FF0000 /* PendSV priority value (lowest) */ + +/* + * rt_base_t rt_hw_interrupt_disable(); + */ + .global rt_hw_interrupt_disable + .type rt_hw_interrupt_disable, %function +rt_hw_interrupt_disable: + MRS R0, PRIMASK + CPSID I + BX LR + +/* + * void rt_hw_interrupt_enable(rt_base_t level); + */ + .global rt_hw_interrupt_enable + .type rt_hw_interrupt_enable, %function +rt_hw_interrupt_enable: + MSR PRIMASK, R0 + BX LR + +/* + * void rt_hw_context_switch(rt_uint32 from, rt_uint32 to); + * R0 --> from + * R1 --> to + */ + .global rt_hw_context_switch_interrupt + .type rt_hw_context_switch_interrupt, %function + .global rt_hw_context_switch + .type rt_hw_context_switch, %function +rt_hw_context_switch_interrupt: +rt_hw_context_switch: + /* set rt_thread_switch_interrupt_flag to 1 */ + LDR R2, =rt_thread_switch_interrupt_flag + LDR R3, [R2] + CMP R3, #1 + BEQ _reswitch + MOV R3, #1 + STR R3, [R2] + + LDR R2, =rt_interrupt_from_thread /* set rt_interrupt_from_thread */ + STR R0, [R2] + +_reswitch: + LDR R2, =rt_interrupt_to_thread /* set rt_interrupt_to_thread */ + STR R1, [R2] + + LDR R0, =ICSR /* trigger the PendSV exception (causes context switch) */ + LDR R1, =PENDSVSET_BIT + STR R1, [R0] + BX LR + +/* R0 --> swith from thread stack + * R1 --> swith to thread stack + * psr, pc, LR, R12, R3, R2, R1, R0 are pushed into [from] stack + */ + .global PendSV_Handler + .type PendSV_Handler, %function +PendSV_Handler: + /* disable interrupt to protect context switch */ + MRS R2, PRIMASK + CPSID I + + /* get rt_thread_switch_interrupt_flag */ + LDR R0, =rt_thread_switch_interrupt_flag + LDR R1, [R0] + CBZ R1, pendsv_exit /* pendsv aLReady handled */ + + /* clear rt_thread_switch_interrupt_flag to 0 */ + MOV R1, #0 + STR R1, [R0] + + LDR R0, =rt_interrupt_from_thread + LDR R1, [R0] + CBZ R1, swtich_to_thread /* skip register save at the first time */ + + MRS R1, PSP /* get from thread stack pointer */ + STMFD R1!, {R4 - R11} /* push R4 - R11 register */ + LDR R0, [R0] + STR R1, [R0] /* update from thread stack pointer */ + +swtich_to_thread: + LDR R1, =rt_interrupt_to_thread + LDR R1, [R1] + LDR R1, [R1] /* load thread stack pointer */ + + LDMFD R1!, {R4 - R11} /* pop R4 - R11 register */ + MSR PSP, R1 /* update stack pointer */ + +pendsv_exit: + /* restore interrupt */ + MSR PRIMASK, R2 + + ORR LR, LR, #0x04 + BX LR + +/* + * void rt_hw_context_switch_to(rt_uint32 to); + * R0 --> to + */ + .global rt_hw_context_switch_to + .type rt_hw_context_switch_to, %function +rt_hw_context_switch_to: + LDR R1, =rt_interrupt_to_thread + STR R0, [R1] + + /* set from thread to 0 */ + LDR R1, =rt_interrupt_from_thread + MOV R0, #0 + STR R0, [R1] + + /* set interrupt flag to 1 */ + LDR R1, =rt_thread_switch_interrupt_flag + MOV R0, #1 + STR R0, [R1] + + /* set the PendSV exception priority */ + LDR R0, =SHPR3 + LDR R1, =PENDSV_PRI_LOWEST + LDR.W R2, [R0,#0] /* read */ + ORR R1, R1, R2 /* modify */ + STR R1, [R0] /* write-back */ + + LDR R0, =ICSR /* trigger the PendSV exception (causes context switch) */ + LDR R1, =PENDSVSET_BIT + STR R1, [R0] + + CPSIE I /* enable interrupts at processor level */ + + /* never reach here! */ + +/* compatible with old version */ + .global rt_hw_interrupt_thread_switch + .type rt_hw_interrupt_thread_switch, %function +rt_hw_interrupt_thread_switch: + BX LR + NOP + + .global HardFault_Handler + .type HardFault_Handler, %function +HardFault_Handler: + /* get current context */ + MRS R0, PSP /* get fault thread stack pointer */ + PUSH {LR} + BL rt_hw_hard_fault_exception + POP {LR} + + ORR LR, LR, #0x04 + BX LR + +/* + * rt_uint32_t rt_hw_interrupt_check(void); + * R0 --> state + */ + .global rt_hw_interrupt_check + .type rt_hw_interrupt_check, %function +rt_hw_interrupt_check: + MRS R0, IPSR + BX LR diff --git a/libcpu/arm/cortex-m3/context_rvds.S b/libcpu/arm/cortex-m3/context_rvds.S index 51c4967765..7f2e8e67d1 100644 --- a/libcpu/arm/cortex-m3/context_rvds.S +++ b/libcpu/arm/cortex-m3/context_rvds.S @@ -1,188 +1,188 @@ -;/*
-; * File : context_rvds.S
-; * This file is part of RT-Thread RTOS
-; * COPYRIGHT (C) 2009, RT-Thread Development Team
-; *
-; * The license and distribution terms for this file may be
-; * found in the file LICENSE in this distribution or at
-; * http://www.rt-thread.org/license/LICENSE
-; *
-; * Change Logs:
-; * Date Author Notes
-; * 2009-01-17 Bernard first version
-; */
-
-;/**
-; * @addtogroup CORTEX-M3
-; */
-;/*@{*/
-
-NVIC_INT_CTRL EQU 0xE000ED04 ; interrupt control state register
-NVIC_SYSPRI2 EQU 0xE000ED20 ; system priority register (2)
-NVIC_PENDSV_PRI EQU 0x00FF0000 ; PendSV priority value (lowest)
-NVIC_PENDSVSET EQU 0x10000000 ; value to trigger PendSV exception
-
- AREA |.text|, CODE, READONLY, ALIGN=2
- THUMB
- REQUIRE8
- PRESERVE8
-
- IMPORT rt_thread_switch_interrupt_flag
- IMPORT rt_interrupt_from_thread
- IMPORT rt_interrupt_to_thread
-
-;/*
-; * rt_base_t rt_hw_interrupt_disable();
-; */
-rt_hw_interrupt_disable PROC
- EXPORT rt_hw_interrupt_disable
- MRS r0, PRIMASK
- CPSID I
- BX LR
- ENDP
-
-;/*
-; * void rt_hw_interrupt_enable(rt_base_t level);
-; */
-rt_hw_interrupt_enable PROC
- EXPORT rt_hw_interrupt_enable
- MSR PRIMASK, r0
- BX LR
- ENDP
-
-;/*
-; * void rt_hw_context_switch(rt_uint32 from, rt_uint32 to);
-; * r0 --> from
-; * r1 --> to
-; */
-rt_hw_context_switch_interrupt
- EXPORT rt_hw_context_switch_interrupt
-rt_hw_context_switch PROC
- EXPORT rt_hw_context_switch
-
- ; set rt_thread_switch_interrupt_flag to 1
- LDR r2, =rt_thread_switch_interrupt_flag
- LDR r3, [r2]
- CMP r3, #1
- BEQ _reswitch
- MOV r3, #1
- STR r3, [r2]
-
- LDR r2, =rt_interrupt_from_thread ; set rt_interrupt_from_thread
- STR r0, [r2]
-
-_reswitch
- LDR r2, =rt_interrupt_to_thread ; set rt_interrupt_to_thread
- STR r1, [r2]
-
- LDR r0, =NVIC_INT_CTRL ; trigger the PendSV exception (causes context switch)
- LDR r1, =NVIC_PENDSVSET
- STR r1, [r0]
- BX LR
- ENDP
-
-; r0 --> swith from thread stack
-; r1 --> swith to thread stack
-; psr, pc, lr, r12, r3, r2, r1, r0 are pushed into [from] stack
-PendSV_Handler PROC
- EXPORT PendSV_Handler
-
- ; disable interrupt to protect context switch
- MRS r2, PRIMASK
- CPSID I
-
- ; get rt_thread_switch_interrupt_flag
- LDR r0, =rt_thread_switch_interrupt_flag
- LDR r1, [r0]
- CBZ r1, pendsv_exit ; pendsv already handled
-
- ; clear rt_thread_switch_interrupt_flag to 0
- MOV r1, #0x00
- STR r1, [r0]
-
- LDR r0, =rt_interrupt_from_thread
- LDR r1, [r0]
- CBZ r1, swtich_to_thread ; skip register save at the first time
-
- MRS r1, psp ; get from thread stack pointer
- STMFD r1!, {r4 - r11} ; push r4 - r11 register
- LDR r0, [r0]
- STR r1, [r0] ; update from thread stack pointer
-
-swtich_to_thread
- LDR r1, =rt_interrupt_to_thread
- LDR r1, [r1]
- LDR r1, [r1] ; load thread stack pointer
-
- LDMFD r1!, {r4 - r11} ; pop r4 - r11 register
- MSR psp, r1 ; update stack pointer
-
-pendsv_exit
- ; restore interrupt
- MSR PRIMASK, r2
-
- ORR lr, lr, #0x04
- BX lr
- ENDP
-
-;/*
-; * void rt_hw_context_switch_to(rt_uint32 to);
-; * r0 --> to
-; * this fucntion is used to perform the first thread switch
-; */
-rt_hw_context_switch_to PROC
- EXPORT rt_hw_context_switch_to
- ; set to thread
- LDR r1, =rt_interrupt_to_thread
- STR r0, [r1]
-
- ; set from thread to 0
- LDR r1, =rt_interrupt_from_thread
- MOV r0, #0x0
- STR r0, [r1]
-
- ; set interrupt flag to 1
- LDR r1, =rt_thread_switch_interrupt_flag
- MOV r0, #1
- STR r0, [r1]
-
- ; set the PendSV exception priority
- LDR r0, =NVIC_SYSPRI2
- LDR r1, =NVIC_PENDSV_PRI
- LDR.W r2, [r0,#0x00] ; read
- ORR r1,r1,r2 ; modify
- STR r1, [r0] ; write-back
-
- ; trigger the PendSV exception (causes context switch)
- LDR r0, =NVIC_INT_CTRL
- LDR r1, =NVIC_PENDSVSET
- STR r1, [r0]
-
- ; enable interrupts at processor level
- CPSIE I
-
- ; never reach here!
- ENDP
-
-; compatible with old version
-rt_hw_interrupt_thread_switch PROC
- EXPORT rt_hw_interrupt_thread_switch
- BX lr
- NOP
- ENDP
-
- IMPORT rt_hw_hard_fault_exception
- EXPORT HardFault_Handler
-HardFault_Handler PROC
-
- ; get current context
- MRS r0, psp ; get fault thread stack pointer
- PUSH {lr}
- BL rt_hw_hard_fault_exception
- POP {lr}
-
- ORR lr, lr, #0x04
- BX lr
- ENDP
-
- END
+;/* +; * File : context_rvds.S +; * This file is part of RT-Thread RTOS +; * COPYRIGHT (C) 2009, RT-Thread Development Team +; * +; * The license and distribution terms for this file may be +; * found in the file LICENSE in this distribution or at +; * http://www.rt-thread.org/license/LICENSE +; * +; * Change Logs: +; * Date Author Notes +; * 2009-01-17 Bernard first version +; */ + +;/** +; * @addtogroup CORTEX-M3 +; */ +;/*@{*/ + +NVIC_INT_CTRL EQU 0xE000ED04 ; interrupt control state register +NVIC_SYSPRI2 EQU 0xE000ED20 ; system priority register (2) +NVIC_PENDSV_PRI EQU 0x00FF0000 ; PendSV priority value (lowest) +NVIC_PENDSVSET EQU 0x10000000 ; value to trigger PendSV exception + + AREA |.text|, CODE, READONLY, ALIGN=2 + THUMB + REQUIRE8 + PRESERVE8 + + IMPORT rt_thread_switch_interrupt_flag + IMPORT rt_interrupt_from_thread + IMPORT rt_interrupt_to_thread + +;/* +; * rt_base_t rt_hw_interrupt_disable(); +; */ +rt_hw_interrupt_disable PROC + EXPORT rt_hw_interrupt_disable + MRS r0, PRIMASK + CPSID I + BX LR + ENDP + +;/* +; * void rt_hw_interrupt_enable(rt_base_t level); +; */ +rt_hw_interrupt_enable PROC + EXPORT rt_hw_interrupt_enable + MSR PRIMASK, r0 + BX LR + ENDP + +;/* +; * void rt_hw_context_switch(rt_uint32 from, rt_uint32 to); +; * r0 --> from +; * r1 --> to +; */ +rt_hw_context_switch_interrupt + EXPORT rt_hw_context_switch_interrupt +rt_hw_context_switch PROC + EXPORT rt_hw_context_switch + + ; set rt_thread_switch_interrupt_flag to 1 + LDR r2, =rt_thread_switch_interrupt_flag + LDR r3, [r2] + CMP r3, #1 + BEQ _reswitch + MOV r3, #1 + STR r3, [r2] + + LDR r2, =rt_interrupt_from_thread ; set rt_interrupt_from_thread + STR r0, [r2] + +_reswitch + LDR r2, =rt_interrupt_to_thread ; set rt_interrupt_to_thread + STR r1, [r2] + + LDR r0, =NVIC_INT_CTRL ; trigger the PendSV exception (causes context switch) + LDR r1, =NVIC_PENDSVSET + STR r1, [r0] + BX LR + ENDP + +; r0 --> swith from thread stack +; r1 --> swith to thread stack +; psr, pc, lr, r12, r3, r2, r1, r0 are pushed into [from] stack +PendSV_Handler PROC + EXPORT PendSV_Handler + + ; disable interrupt to protect context switch + MRS r2, PRIMASK + CPSID I + + ; get rt_thread_switch_interrupt_flag + LDR r0, =rt_thread_switch_interrupt_flag + LDR r1, [r0] + CBZ r1, pendsv_exit ; pendsv already handled + + ; clear rt_thread_switch_interrupt_flag to 0 + MOV r1, #0x00 + STR r1, [r0] + + LDR r0, =rt_interrupt_from_thread + LDR r1, [r0] + CBZ r1, swtich_to_thread ; skip register save at the first time + + MRS r1, psp ; get from thread stack pointer + STMFD r1!, {r4 - r11} ; push r4 - r11 register + LDR r0, [r0] + STR r1, [r0] ; update from thread stack pointer + +swtich_to_thread + LDR r1, =rt_interrupt_to_thread + LDR r1, [r1] + LDR r1, [r1] ; load thread stack pointer + + LDMFD r1!, {r4 - r11} ; pop r4 - r11 register + MSR psp, r1 ; update stack pointer + +pendsv_exit + ; restore interrupt + MSR PRIMASK, r2 + + ORR lr, lr, #0x04 + BX lr + ENDP + +;/* +; * void rt_hw_context_switch_to(rt_uint32 to); +; * r0 --> to +; * this fucntion is used to perform the first thread switch +; */ +rt_hw_context_switch_to PROC + EXPORT rt_hw_context_switch_to + ; set to thread + LDR r1, =rt_interrupt_to_thread + STR r0, [r1] + + ; set from thread to 0 + LDR r1, =rt_interrupt_from_thread + MOV r0, #0x0 + STR r0, [r1] + + ; set interrupt flag to 1 + LDR r1, =rt_thread_switch_interrupt_flag + MOV r0, #1 + STR r0, [r1] + + ; set the PendSV exception priority + LDR r0, =NVIC_SYSPRI2 + LDR r1, =NVIC_PENDSV_PRI + LDR.W r2, [r0,#0x00] ; read + ORR r1,r1,r2 ; modify + STR r1, [r0] ; write-back + + ; trigger the PendSV exception (causes context switch) + LDR r0, =NVIC_INT_CTRL + LDR r1, =NVIC_PENDSVSET + STR r1, [r0] + + ; enable interrupts at processor level + CPSIE I + + ; never reach here! + ENDP + +; compatible with old version +rt_hw_interrupt_thread_switch PROC + EXPORT rt_hw_interrupt_thread_switch + BX lr + NOP + ENDP + + IMPORT rt_hw_hard_fault_exception + EXPORT HardFault_Handler +HardFault_Handler PROC + + ; get current context + MRS r0, psp ; get fault thread stack pointer + PUSH {lr} + BL rt_hw_hard_fault_exception + POP {lr} + + ORR lr, lr, #0x04 + BX lr + ENDP + + END diff --git a/libcpu/arm/cortex-m4/context_gcc.S b/libcpu/arm/cortex-m4/context_gcc.S index 8f50096d57..97c3f1b44e 100644 --- a/libcpu/arm/cortex-m4/context_gcc.S +++ b/libcpu/arm/cortex-m4/context_gcc.S @@ -1,188 +1,188 @@ -/*
- * File : context_gcc.S
- * This file is part of RT-Thread RTOS
- * COPYRIGHT (C) 2009, RT-Thread Development Team
- *
- * The license and distribution terms for this file may be
- * found in the file LICENSE in this distribution or at
- * http://www.rt-thread.org/license/LICENSE
- *
- * Change Logs:
- * Date Author Notes
- * 2009-10-11 Bernard first version
- * 2012-01-01 aozima support context switch load/store FPU register.
- */
-
-/**
- * @addtogroup STM32
- */
-/*@{*/
-
-.cpu cortex-m4
-.syntax unified
-.thumb
-.text
-
-.equ NVIC_INT_CTRL, 0xE000ED04 /* interrupt control state register */
-.equ NVIC_SYSPRI2, 0xE000ED20 /* system priority register (2) */
-.equ NVIC_PENDSV_PRI, 0x00FF0000 /* PendSV priority value (lowest) */
-.equ NVIC_PENDSVSET, 0x10000000 /* value to trigger PendSV exception */
-
-/*
- * rt_base_t rt_hw_interrupt_disable();
- */
-.global rt_hw_interrupt_disable
-.type rt_hw_interrupt_disable, %function
-rt_hw_interrupt_disable:
- MRS r0, PRIMASK
- CPSID I
- BX LR
-
-/*
- * void rt_hw_interrupt_enable(rt_base_t level);
- */
-.global rt_hw_interrupt_enable
-.type rt_hw_interrupt_enable, %function
-rt_hw_interrupt_enable:
- MSR PRIMASK, r0
- BX LR
-
-/*
- * void rt_hw_context_switch(rt_uint32 from, rt_uint32 to);
- * r0 --> from
- * r1 --> to
- */
-.global rt_hw_context_switch_interrupt
-.type rt_hw_context_switch_interrupt, %function
-.global rt_hw_context_switch
-.type rt_hw_context_switch, %function
-
-rt_hw_context_switch_interrupt:
-rt_hw_context_switch:
- /* set rt_thread_switch_interrupt_flag to 1 */
- LDR r2, =rt_thread_switch_interrupt_flag
- LDR r3, [r2]
- CMP r3, #1
- BEQ _reswitch
- MOV r3, #1
- STR r3, [r2]
-
- LDR r2, =rt_interrupt_from_thread /* set rt_interrupt_from_thread */
- STR r0, [r2]
-
-_reswitch:
- LDR r2, =rt_interrupt_to_thread /* set rt_interrupt_to_thread */
- STR r1, [r2]
-
- LDR r0, =NVIC_INT_CTRL /* trigger the PendSV exception (causes context switch) */
- LDR r1, =NVIC_PENDSVSET
- STR r1, [r0]
- BX LR
-
-/* r0 --> swith from thread stack
- * r1 --> swith to thread stack
- * psr, pc, lr, r12, r3, r2, r1, r0 are pushed into [from] stack
- */
-.global PendSV_Handler
-.type PendSV_Handler, %function
-PendSV_Handler:
- /* disable interrupt to protect context switch */
- MRS r2, PRIMASK
- CPSID I
-
- /* get rt_thread_switch_interrupt_flag */
- LDR r0, =rt_thread_switch_interrupt_flag
- LDR r1, [r0]
- CBZ r1, pendsv_exit /* pendsv already handled */
-
- /* clear rt_thread_switch_interrupt_flag to 0 */
- MOV r1, #0x00
- STR r1, [r0]
-
- LDR r0, =rt_interrupt_from_thread
- LDR r1, [r0]
- CBZ r1, swtich_to_thread /* skip register save at the first time */
-
- MRS r1, psp /* get from thread stack pointer */
-
-#if defined (__VFP_FP__) && !defined(__SOFTFP__)
- VSTMDB r1!, {d8 - d15} /* push FPU register s16~s31 */
-#endif
-
- STMFD r1!, {r4 - r11} /* push r4 - r11 register */
- LDR r0, [r0]
- STR r1, [r0] /* update from thread stack pointer */
-
-swtich_to_thread:
- LDR r1, =rt_interrupt_to_thread
- LDR r1, [r1]
- LDR r1, [r1] /* load thread stack pointer */
-
- LDMFD r1!, {r4 - r11} /* pop r4 - r11 register */
-
-#if defined (__VFP_FP__) && !defined(__SOFTFP__)
- VLDMIA r1!, {d8 - d15} /* pop FPU register s16~s31 */
-#endif
-
- MSR psp, r1 /* update stack pointer */
-
-pendsv_exit:
- /* restore interrupt */
- MSR PRIMASK, r2
-
- ORR lr, lr, #0x04
- BX lr
-
-/*
- * void rt_hw_context_switch_to(rt_uint32 to);
- * r0 --> to
- */
-.global rt_hw_context_switch_to
-.type rt_hw_context_switch_to, %function
-rt_hw_context_switch_to:
- LDR r1, =rt_interrupt_to_thread
- STR r0, [r1]
-
- /* set from thread to 0 */
- LDR r1, =rt_interrupt_from_thread
- MOV r0, #0x0
- STR r0, [r1]
-
- /* set interrupt flag to 1 */
- LDR r1, =rt_thread_switch_interrupt_flag
- MOV r0, #1
- STR r0, [r1]
-
- /* set the PendSV exception priority */
- LDR r0, =NVIC_SYSPRI2
- LDR r1, =NVIC_PENDSV_PRI
- LDR.W r2, [r0,#0x00] /* read */
- ORR r1,r1,r2 /* modify */
- STR r1, [r0] /* write-back */
-
- LDR r0, =NVIC_INT_CTRL /* trigger the PendSV exception (causes context switch) */
- LDR r1, =NVIC_PENDSVSET
- STR r1, [r0]
-
- CPSIE I /* enable interrupts at processor level */
-
- /* never reach here! */
-
-/* compatible with old version */
-.global rt_hw_interrupt_thread_switch
-.type rt_hw_interrupt_thread_switch, %function
-rt_hw_interrupt_thread_switch:
- BX lr
- NOP
-
-.global HardFault_Handler
-.type HardFault_Handler, %function
-HardFault_Handler:
- /* get current context */
- MRS r0, psp /* get fault thread stack pointer */
- PUSH {lr}
- BL rt_hw_hard_fault_exception
- POP {lr}
-
- ORR lr, lr, #0x04
- BX lr
+/* + * File : context_gcc.S + * This file is part of RT-Thread RTOS + * COPYRIGHT (C) 2009, RT-Thread Development Team + * + * The license and distribution terms for this file may be + * found in the file LICENSE in this distribution or at + * http://www.rt-thread.org/license/LICENSE + * + * Change Logs: + * Date Author Notes + * 2009-10-11 Bernard first version + * 2012-01-01 aozima support context switch load/store FPU register. + */ + +/** + * @addtogroup STM32 + */ +/*@{*/ + +.cpu cortex-m4 +.syntax unified +.thumb +.text + +.equ NVIC_INT_CTRL, 0xE000ED04 /* interrupt control state register */ +.equ NVIC_SYSPRI2, 0xE000ED20 /* system priority register (2) */ +.equ NVIC_PENDSV_PRI, 0x00FF0000 /* PendSV priority value (lowest) */ +.equ NVIC_PENDSVSET, 0x10000000 /* value to trigger PendSV exception */ + +/* + * rt_base_t rt_hw_interrupt_disable(); + */ +.global rt_hw_interrupt_disable +.type rt_hw_interrupt_disable, %function +rt_hw_interrupt_disable: + MRS r0, PRIMASK + CPSID I + BX LR + +/* + * void rt_hw_interrupt_enable(rt_base_t level); + */ +.global rt_hw_interrupt_enable +.type rt_hw_interrupt_enable, %function +rt_hw_interrupt_enable: + MSR PRIMASK, r0 + BX LR + +/* + * void rt_hw_context_switch(rt_uint32 from, rt_uint32 to); + * r0 --> from + * r1 --> to + */ +.global rt_hw_context_switch_interrupt +.type rt_hw_context_switch_interrupt, %function +.global rt_hw_context_switch +.type rt_hw_context_switch, %function + +rt_hw_context_switch_interrupt: +rt_hw_context_switch: + /* set rt_thread_switch_interrupt_flag to 1 */ + LDR r2, =rt_thread_switch_interrupt_flag + LDR r3, [r2] + CMP r3, #1 + BEQ _reswitch + MOV r3, #1 + STR r3, [r2] + + LDR r2, =rt_interrupt_from_thread /* set rt_interrupt_from_thread */ + STR r0, [r2] + +_reswitch: + LDR r2, =rt_interrupt_to_thread /* set rt_interrupt_to_thread */ + STR r1, [r2] + + LDR r0, =NVIC_INT_CTRL /* trigger the PendSV exception (causes context switch) */ + LDR r1, =NVIC_PENDSVSET + STR r1, [r0] + BX LR + +/* r0 --> swith from thread stack + * r1 --> swith to thread stack + * psr, pc, lr, r12, r3, r2, r1, r0 are pushed into [from] stack + */ +.global PendSV_Handler +.type PendSV_Handler, %function +PendSV_Handler: + /* disable interrupt to protect context switch */ + MRS r2, PRIMASK + CPSID I + + /* get rt_thread_switch_interrupt_flag */ + LDR r0, =rt_thread_switch_interrupt_flag + LDR r1, [r0] + CBZ r1, pendsv_exit /* pendsv already handled */ + + /* clear rt_thread_switch_interrupt_flag to 0 */ + MOV r1, #0x00 + STR r1, [r0] + + LDR r0, =rt_interrupt_from_thread + LDR r1, [r0] + CBZ r1, swtich_to_thread /* skip register save at the first time */ + + MRS r1, psp /* get from thread stack pointer */ + +#if defined (__VFP_FP__) && !defined(__SOFTFP__) + VSTMDB r1!, {d8 - d15} /* push FPU register s16~s31 */ +#endif + + STMFD r1!, {r4 - r11} /* push r4 - r11 register */ + LDR r0, [r0] + STR r1, [r0] /* update from thread stack pointer */ + +swtich_to_thread: + LDR r1, =rt_interrupt_to_thread + LDR r1, [r1] + LDR r1, [r1] /* load thread stack pointer */ + + LDMFD r1!, {r4 - r11} /* pop r4 - r11 register */ + +#if defined (__VFP_FP__) && !defined(__SOFTFP__) + VLDMIA r1!, {d8 - d15} /* pop FPU register s16~s31 */ +#endif + + MSR psp, r1 /* update stack pointer */ + +pendsv_exit: + /* restore interrupt */ + MSR PRIMASK, r2 + + ORR lr, lr, #0x04 + BX lr + +/* + * void rt_hw_context_switch_to(rt_uint32 to); + * r0 --> to + */ +.global rt_hw_context_switch_to +.type rt_hw_context_switch_to, %function +rt_hw_context_switch_to: + LDR r1, =rt_interrupt_to_thread + STR r0, [r1] + + /* set from thread to 0 */ + LDR r1, =rt_interrupt_from_thread + MOV r0, #0x0 + STR r0, [r1] + + /* set interrupt flag to 1 */ + LDR r1, =rt_thread_switch_interrupt_flag + MOV r0, #1 + STR r0, [r1] + + /* set the PendSV exception priority */ + LDR r0, =NVIC_SYSPRI2 + LDR r1, =NVIC_PENDSV_PRI + LDR.W r2, [r0,#0x00] /* read */ + ORR r1,r1,r2 /* modify */ + STR r1, [r0] /* write-back */ + + LDR r0, =NVIC_INT_CTRL /* trigger the PendSV exception (causes context switch) */ + LDR r1, =NVIC_PENDSVSET + STR r1, [r0] + + CPSIE I /* enable interrupts at processor level */ + + /* never reach here! */ + +/* compatible with old version */ +.global rt_hw_interrupt_thread_switch +.type rt_hw_interrupt_thread_switch, %function +rt_hw_interrupt_thread_switch: + BX lr + NOP + +.global HardFault_Handler +.type HardFault_Handler, %function +HardFault_Handler: + /* get current context */ + MRS r0, psp /* get fault thread stack pointer */ + PUSH {lr} + BL rt_hw_hard_fault_exception + POP {lr} + + ORR lr, lr, #0x04 + BX lr diff --git a/libcpu/arm/cortex-m4/context_iar.S b/libcpu/arm/cortex-m4/context_iar.S index 0a28a37a90..db3f370473 100644 --- a/libcpu/arm/cortex-m4/context_iar.S +++ b/libcpu/arm/cortex-m4/context_iar.S @@ -1,187 +1,187 @@ -;/*
-; * File : context_iar.S
-; * This file is part of RT-Thread RTOS
-; * COPYRIGHT (C) 2009, RT-Thread Development Team
-; *
-; * The license and distribution terms for this file may be
-; * found in the file LICENSE in this distribution or at
-; * http://www.rt-thread.org/license/LICENSE
-; *
-; * Change Logs:
-; * Date Author Notes
-; * 2009-01-17 Bernard first version
-; * 2009-09-27 Bernard add protect when contex switch occurs
-; * 2012-01-01 aozima support context switch load/store FPU register.
-; */
-
-;/**
-; * @addtogroup STM32
-; */
-;/*@{*/
-
-NVIC_INT_CTRL EQU 0xE000ED04 ; interrupt control state register
-NVIC_SYSPRI2 EQU 0xE000ED20 ; system priority register (2)
-NVIC_PENDSV_PRI EQU 0x00FF0000 ; PendSV priority value (lowest)
-NVIC_PENDSVSET EQU 0x10000000 ; value to trigger PendSV exception
-
- SECTION .text:CODE(2)
- THUMB
- REQUIRE8
- PRESERVE8
-
- IMPORT rt_thread_switch_interrupt_flag
- IMPORT rt_interrupt_from_thread
- IMPORT rt_interrupt_to_thread
-
-;/*
-; * rt_base_t rt_hw_interrupt_disable();
-; */
- EXPORT rt_hw_interrupt_disable
-rt_hw_interrupt_disable:
- MRS r0, PRIMASK
- CPSID I
- BX LR
-
-;/*
-; * void rt_hw_interrupt_enable(rt_base_t level);
-; */
- EXPORT rt_hw_interrupt_enable
-rt_hw_interrupt_enable:
- MSR PRIMASK, r0
- BX LR
-
-;/*
-; * void rt_hw_context_switch(rt_uint32 from, rt_uint32 to);
-; * r0 --> from
-; * r1 --> to
-; */
- EXPORT rt_hw_context_switch_interrupt
- EXPORT rt_hw_context_switch
-rt_hw_context_switch_interrupt:
-rt_hw_context_switch:
- ; set rt_thread_switch_interrupt_flag to 1
- LDR r2, =rt_thread_switch_interrupt_flag
- LDR r3, [r2]
- CMP r3, #1
- BEQ _reswitch
- MOV r3, #1
- STR r3, [r2]
-
- LDR r2, =rt_interrupt_from_thread ; set rt_interrupt_from_thread
- STR r0, [r2]
-
-_reswitch
- LDR r2, =rt_interrupt_to_thread ; set rt_interrupt_to_thread
- STR r1, [r2]
-
- LDR r0, =NVIC_INT_CTRL ; trigger the PendSV exception (causes context switch)
- LDR r1, =NVIC_PENDSVSET
- STR r1, [r0]
- BX LR
-
-; r0 --> swith from thread stack
-; r1 --> swith to thread stack
-; psr, pc, lr, r12, r3, r2, r1, r0 are pushed into [from] stack
- EXPORT PendSV_Handler
-PendSV_Handler:
-
- ; disable interrupt to protect context switch
- MRS r2, PRIMASK
- CPSID I
-
- ; get rt_thread_switch_interrupt_flag
- LDR r0, =rt_thread_switch_interrupt_flag
- LDR r1, [r0]
- CBZ r1, pendsv_exit ; pendsv already handled
-
- ; clear rt_thread_switch_interrupt_flag to 0
- MOV r1, #0x00
- STR r1, [r0]
-
- LDR r0, =rt_interrupt_from_thread
- LDR r1, [r0]
- CBZ r1, swtich_to_thread ; skip register save at the first time
-
- MRS r1, psp ; get from thread stack pointer
-
-#if defined ( __ARMVFP__ )
- VSTMDB r1!, {d8 - d15} ; push FPU register s16~s31
-#endif
-
- STMFD r1!, {r4 - r11} ; push r4 - r11 register
- LDR r0, [r0]
- STR r1, [r0] ; update from thread stack pointer
-
-swtich_to_thread
- LDR r1, =rt_interrupt_to_thread
- LDR r1, [r1]
- LDR r1, [r1] ; load thread stack pointer
-
- LDMFD r1!, {r4 - r11} ; pop r4 - r11 register
-
-#if defined ( __ARMVFP__ )
- VLDMIA r1!, {d8 - d15} ; pop FPU register s16~s31
-#endif
-
- MSR psp, r1 ; update stack pointer
-
-pendsv_exit
- ; restore interrupt
- MSR PRIMASK, r2
-
- ORR lr, lr, #0x04
- BX lr
-
-;/*
-; * void rt_hw_context_switch_to(rt_uint32 to);
-; * r0 --> to
-; */
- EXPORT rt_hw_context_switch_to
-rt_hw_context_switch_to:
- LDR r1, =rt_interrupt_to_thread
- STR r0, [r1]
-
- ; set from thread to 0
- LDR r1, =rt_interrupt_from_thread
- MOV r0, #0x0
- STR r0, [r1]
-
- ; set interrupt flag to 1
- LDR r1, =rt_thread_switch_interrupt_flag
- MOV r0, #1
- STR r0, [r1]
-
- ; set the PendSV exception priority
- LDR r0, =NVIC_SYSPRI2
- LDR r1, =NVIC_PENDSV_PRI
- LDR.W r2, [r0,#0x00] ; read
- ORR r1,r1,r2 ; modify
- STR r1, [r0] ; write-back
-
- LDR r0, =NVIC_INT_CTRL ; trigger the PendSV exception (causes context switch)
- LDR r1, =NVIC_PENDSVSET
- STR r1, [r0]
-
- CPSIE I ; enable interrupts at processor level
-
- ; never reach here!
-
-; compatible with old version
- EXPORT rt_hw_interrupt_thread_switch
-rt_hw_interrupt_thread_switch:
- BX lr
-
- IMPORT rt_hw_hard_fault_exception
- EXPORT HardFault_Handler
-HardFault_Handler:
-
- ; get current context
- MRS r0, psp ; get fault thread stack pointer
- PUSH {lr}
- BL rt_hw_hard_fault_exception
- POP {lr}
-
- ORR lr, lr, #0x04
- BX lr
-
- END
+;/* +; * File : context_iar.S +; * This file is part of RT-Thread RTOS +; * COPYRIGHT (C) 2009, RT-Thread Development Team +; * +; * The license and distribution terms for this file may be +; * found in the file LICENSE in this distribution or at +; * http://www.rt-thread.org/license/LICENSE +; * +; * Change Logs: +; * Date Author Notes +; * 2009-01-17 Bernard first version +; * 2009-09-27 Bernard add protect when contex switch occurs +; * 2012-01-01 aozima support context switch load/store FPU register. +; */ + +;/** +; * @addtogroup STM32 +; */ +;/*@{*/ + +NVIC_INT_CTRL EQU 0xE000ED04 ; interrupt control state register +NVIC_SYSPRI2 EQU 0xE000ED20 ; system priority register (2) +NVIC_PENDSV_PRI EQU 0x00FF0000 ; PendSV priority value (lowest) +NVIC_PENDSVSET EQU 0x10000000 ; value to trigger PendSV exception + + SECTION .text:CODE(2) + THUMB + REQUIRE8 + PRESERVE8 + + IMPORT rt_thread_switch_interrupt_flag + IMPORT rt_interrupt_from_thread + IMPORT rt_interrupt_to_thread + +;/* +; * rt_base_t rt_hw_interrupt_disable(); +; */ + EXPORT rt_hw_interrupt_disable +rt_hw_interrupt_disable: + MRS r0, PRIMASK + CPSID I + BX LR + +;/* +; * void rt_hw_interrupt_enable(rt_base_t level); +; */ + EXPORT rt_hw_interrupt_enable +rt_hw_interrupt_enable: + MSR PRIMASK, r0 + BX LR + +;/* +; * void rt_hw_context_switch(rt_uint32 from, rt_uint32 to); +; * r0 --> from +; * r1 --> to +; */ + EXPORT rt_hw_context_switch_interrupt + EXPORT rt_hw_context_switch +rt_hw_context_switch_interrupt: +rt_hw_context_switch: + ; set rt_thread_switch_interrupt_flag to 1 + LDR r2, =rt_thread_switch_interrupt_flag + LDR r3, [r2] + CMP r3, #1 + BEQ _reswitch + MOV r3, #1 + STR r3, [r2] + + LDR r2, =rt_interrupt_from_thread ; set rt_interrupt_from_thread + STR r0, [r2] + +_reswitch + LDR r2, =rt_interrupt_to_thread ; set rt_interrupt_to_thread + STR r1, [r2] + + LDR r0, =NVIC_INT_CTRL ; trigger the PendSV exception (causes context switch) + LDR r1, =NVIC_PENDSVSET + STR r1, [r0] + BX LR + +; r0 --> swith from thread stack +; r1 --> swith to thread stack +; psr, pc, lr, r12, r3, r2, r1, r0 are pushed into [from] stack + EXPORT PendSV_Handler +PendSV_Handler: + + ; disable interrupt to protect context switch + MRS r2, PRIMASK + CPSID I + + ; get rt_thread_switch_interrupt_flag + LDR r0, =rt_thread_switch_interrupt_flag + LDR r1, [r0] + CBZ r1, pendsv_exit ; pendsv already handled + + ; clear rt_thread_switch_interrupt_flag to 0 + MOV r1, #0x00 + STR r1, [r0] + + LDR r0, =rt_interrupt_from_thread + LDR r1, [r0] + CBZ r1, swtich_to_thread ; skip register save at the first time + + MRS r1, psp ; get from thread stack pointer + +#if defined ( __ARMVFP__ ) + VSTMDB r1!, {d8 - d15} ; push FPU register s16~s31 +#endif + + STMFD r1!, {r4 - r11} ; push r4 - r11 register + LDR r0, [r0] + STR r1, [r0] ; update from thread stack pointer + +swtich_to_thread + LDR r1, =rt_interrupt_to_thread + LDR r1, [r1] + LDR r1, [r1] ; load thread stack pointer + + LDMFD r1!, {r4 - r11} ; pop r4 - r11 register + +#if defined ( __ARMVFP__ ) + VLDMIA r1!, {d8 - d15} ; pop FPU register s16~s31 +#endif + + MSR psp, r1 ; update stack pointer + +pendsv_exit + ; restore interrupt + MSR PRIMASK, r2 + + ORR lr, lr, #0x04 + BX lr + +;/* +; * void rt_hw_context_switch_to(rt_uint32 to); +; * r0 --> to +; */ + EXPORT rt_hw_context_switch_to +rt_hw_context_switch_to: + LDR r1, =rt_interrupt_to_thread + STR r0, [r1] + + ; set from thread to 0 + LDR r1, =rt_interrupt_from_thread + MOV r0, #0x0 + STR r0, [r1] + + ; set interrupt flag to 1 + LDR r1, =rt_thread_switch_interrupt_flag + MOV r0, #1 + STR r0, [r1] + + ; set the PendSV exception priority + LDR r0, =NVIC_SYSPRI2 + LDR r1, =NVIC_PENDSV_PRI + LDR.W r2, [r0,#0x00] ; read + ORR r1,r1,r2 ; modify + STR r1, [r0] ; write-back + + LDR r0, =NVIC_INT_CTRL ; trigger the PendSV exception (causes context switch) + LDR r1, =NVIC_PENDSVSET + STR r1, [r0] + + CPSIE I ; enable interrupts at processor level + + ; never reach here! + +; compatible with old version + EXPORT rt_hw_interrupt_thread_switch +rt_hw_interrupt_thread_switch: + BX lr + + IMPORT rt_hw_hard_fault_exception + EXPORT HardFault_Handler +HardFault_Handler: + + ; get current context + MRS r0, psp ; get fault thread stack pointer + PUSH {lr} + BL rt_hw_hard_fault_exception + POP {lr} + + ORR lr, lr, #0x04 + BX lr + + END diff --git a/libcpu/arm/cortex-m4/context_rvds.S b/libcpu/arm/cortex-m4/context_rvds.S index 1bc7b11045..ee72c44d01 100644 --- a/libcpu/arm/cortex-m4/context_rvds.S +++ b/libcpu/arm/cortex-m4/context_rvds.S @@ -1,199 +1,199 @@ -;/*
-; * File : context_rvds.S
-; * This file is part of RT-Thread RTOS
-; * COPYRIGHT (C) 2009, RT-Thread Development Team
-; *
-; * The license and distribution terms for this file may be
-; * found in the file LICENSE in this distribution or at
-; * http://www.rt-thread.org/license/LICENSE
-; *
-; * Change Logs:
-; * Date Author Notes
-; * 2009-01-17 Bernard first version.
-; * 2012-01-01 aozima support context switch load/store FPU register.
-; */
-
-;/**
-; * @addtogroup STM32
-; */
-;/*@{*/
-
-NVIC_INT_CTRL EQU 0xE000ED04 ; interrupt control state register
-NVIC_SYSPRI2 EQU 0xE000ED20 ; system priority register (2)
-NVIC_PENDSV_PRI EQU 0x00FF0000 ; PendSV priority value (lowest)
-NVIC_PENDSVSET EQU 0x10000000 ; value to trigger PendSV exception
-
- AREA |.text|, CODE, READONLY, ALIGN=2
- THUMB
- REQUIRE8
- PRESERVE8
-
- IMPORT rt_thread_switch_interrupt_flag
- IMPORT rt_interrupt_from_thread
- IMPORT rt_interrupt_to_thread
-
-;/*
-; * rt_base_t rt_hw_interrupt_disable();
-; */
-rt_hw_interrupt_disable PROC
- EXPORT rt_hw_interrupt_disable
- MRS r0, PRIMASK
- CPSID I
- BX LR
- ENDP
-
-;/*
-; * void rt_hw_interrupt_enable(rt_base_t level);
-; */
-rt_hw_interrupt_enable PROC
- EXPORT rt_hw_interrupt_enable
- MSR PRIMASK, r0
- BX LR
- ENDP
-
-;/*
-; * void rt_hw_context_switch(rt_uint32 from, rt_uint32 to);
-; * r0 --> from
-; * r1 --> to
-; */
-rt_hw_context_switch_interrupt
- EXPORT rt_hw_context_switch_interrupt
-rt_hw_context_switch PROC
- EXPORT rt_hw_context_switch
-
- ; set rt_thread_switch_interrupt_flag to 1
- LDR r2, =rt_thread_switch_interrupt_flag
- LDR r3, [r2]
- CMP r3, #1
- BEQ _reswitch
- MOV r3, #1
- STR r3, [r2]
-
- LDR r2, =rt_interrupt_from_thread ; set rt_interrupt_from_thread
- STR r0, [r2]
-
-_reswitch
- LDR r2, =rt_interrupt_to_thread ; set rt_interrupt_to_thread
- STR r1, [r2]
-
- LDR r0, =NVIC_INT_CTRL ; trigger the PendSV exception (causes context switch)
- LDR r1, =NVIC_PENDSVSET
- STR r1, [r0]
- BX LR
- ENDP
-
-; r0 --> swith from thread stack
-; r1 --> swith to thread stack
-; psr, pc, lr, r12, r3, r2, r1, r0 are pushed into [from] stack
-PendSV_Handler PROC
- EXPORT PendSV_Handler
-
- ; disable interrupt to protect context switch
- MRS r2, PRIMASK
- CPSID I
-
- ; get rt_thread_switch_interrupt_flag
- LDR r0, =rt_thread_switch_interrupt_flag
- LDR r1, [r0]
- CBZ r1, pendsv_exit ; pendsv already handled
-
- ; clear rt_thread_switch_interrupt_flag to 0
- MOV r1, #0x00
- STR r1, [r0]
-
- LDR r0, =rt_interrupt_from_thread
- LDR r1, [r0]
- CBZ r1, swtich_to_thread ; skip register save at the first time
-
- MRS r1, psp ; get from thread stack pointer
-
- IF {FPU} != "SoftVFP"
- VSTMFD r1!, {d8 - d15} ; push FPU register s16~s31
- ENDIF
-
- STMFD r1!, {r4 - r11} ; push r4 - r11 register
- LDR r0, [r0]
- STR r1, [r0] ; update from thread stack pointer
-
-swtich_to_thread
- LDR r1, =rt_interrupt_to_thread
- LDR r1, [r1]
- LDR r1, [r1] ; load thread stack pointer
-
- LDMFD r1!, {r4 - r11} ; pop r4 - r11 register
-
- IF {FPU} != "SoftVFP"
- VLDMFD r1!, {d8 - d15} ; pop FPU register s16~s31
- ENDIF
-
- MSR psp, r1 ; update stack pointer
-
-pendsv_exit
- ; restore interrupt
- MSR PRIMASK, r2
-
- ORR lr, lr, #0x04
- BX lr
- ENDP
-
-;/*
-; * void rt_hw_context_switch_to(rt_uint32 to);
-; * r0 --> to
-; * this fucntion is used to perform the first thread switch
-; */
-rt_hw_context_switch_to PROC
- EXPORT rt_hw_context_switch_to
- ; set to thread
- LDR r1, =rt_interrupt_to_thread
- STR r0, [r1]
-
- ; set from thread to 0
- LDR r1, =rt_interrupt_from_thread
- MOV r0, #0x0
- STR r0, [r1]
-
- ; set interrupt flag to 1
- LDR r1, =rt_thread_switch_interrupt_flag
- MOV r0, #1
- STR r0, [r1]
-
- ; set the PendSV exception priority
- LDR r0, =NVIC_SYSPRI2
- LDR r1, =NVIC_PENDSV_PRI
- LDR.W r2, [r0,#0x00] ; read
- ORR r1,r1,r2 ; modify
- STR r1, [r0] ; write-back
-
- ; trigger the PendSV exception (causes context switch)
- LDR r0, =NVIC_INT_CTRL
- LDR r1, =NVIC_PENDSVSET
- STR r1, [r0]
-
- ; enable interrupts at processor level
- CPSIE I
-
- ; never reach here!
- ENDP
-
-; compatible with old version
-rt_hw_interrupt_thread_switch PROC
- EXPORT rt_hw_interrupt_thread_switch
- BX lr
- NOP
- ENDP
-
- IMPORT rt_hw_hard_fault_exception
- EXPORT HardFault_Handler
-HardFault_Handler PROC
-
- ; get current context
- MRS r0, psp ; get fault thread stack pointer
- PUSH {lr}
- BL rt_hw_hard_fault_exception
- POP {lr}
-
- ORR lr, lr, #0x04
- BX lr
- ENDP
-
- END
+;/* +; * File : context_rvds.S +; * This file is part of RT-Thread RTOS +; * COPYRIGHT (C) 2009, RT-Thread Development Team +; * +; * The license and distribution terms for this file may be +; * found in the file LICENSE in this distribution or at +; * http://www.rt-thread.org/license/LICENSE +; * +; * Change Logs: +; * Date Author Notes +; * 2009-01-17 Bernard first version. +; * 2012-01-01 aozima support context switch load/store FPU register. +; */ + +;/** +; * @addtogroup STM32 +; */ +;/*@{*/ + +NVIC_INT_CTRL EQU 0xE000ED04 ; interrupt control state register +NVIC_SYSPRI2 EQU 0xE000ED20 ; system priority register (2) +NVIC_PENDSV_PRI EQU 0x00FF0000 ; PendSV priority value (lowest) +NVIC_PENDSVSET EQU 0x10000000 ; value to trigger PendSV exception + + AREA |.text|, CODE, READONLY, ALIGN=2 + THUMB + REQUIRE8 + PRESERVE8 + + IMPORT rt_thread_switch_interrupt_flag + IMPORT rt_interrupt_from_thread + IMPORT rt_interrupt_to_thread + +;/* +; * rt_base_t rt_hw_interrupt_disable(); +; */ +rt_hw_interrupt_disable PROC + EXPORT rt_hw_interrupt_disable + MRS r0, PRIMASK + CPSID I + BX LR + ENDP + +;/* +; * void rt_hw_interrupt_enable(rt_base_t level); +; */ +rt_hw_interrupt_enable PROC + EXPORT rt_hw_interrupt_enable + MSR PRIMASK, r0 + BX LR + ENDP + +;/* +; * void rt_hw_context_switch(rt_uint32 from, rt_uint32 to); +; * r0 --> from +; * r1 --> to +; */ +rt_hw_context_switch_interrupt + EXPORT rt_hw_context_switch_interrupt +rt_hw_context_switch PROC + EXPORT rt_hw_context_switch + + ; set rt_thread_switch_interrupt_flag to 1 + LDR r2, =rt_thread_switch_interrupt_flag + LDR r3, [r2] + CMP r3, #1 + BEQ _reswitch + MOV r3, #1 + STR r3, [r2] + + LDR r2, =rt_interrupt_from_thread ; set rt_interrupt_from_thread + STR r0, [r2] + +_reswitch + LDR r2, =rt_interrupt_to_thread ; set rt_interrupt_to_thread + STR r1, [r2] + + LDR r0, =NVIC_INT_CTRL ; trigger the PendSV exception (causes context switch) + LDR r1, =NVIC_PENDSVSET + STR r1, [r0] + BX LR + ENDP + +; r0 --> swith from thread stack +; r1 --> swith to thread stack +; psr, pc, lr, r12, r3, r2, r1, r0 are pushed into [from] stack +PendSV_Handler PROC + EXPORT PendSV_Handler + + ; disable interrupt to protect context switch + MRS r2, PRIMASK + CPSID I + + ; get rt_thread_switch_interrupt_flag + LDR r0, =rt_thread_switch_interrupt_flag + LDR r1, [r0] + CBZ r1, pendsv_exit ; pendsv already handled + + ; clear rt_thread_switch_interrupt_flag to 0 + MOV r1, #0x00 + STR r1, [r0] + + LDR r0, =rt_interrupt_from_thread + LDR r1, [r0] + CBZ r1, swtich_to_thread ; skip register save at the first time + + MRS r1, psp ; get from thread stack pointer + + IF {FPU} != "SoftVFP" + VSTMFD r1!, {d8 - d15} ; push FPU register s16~s31 + ENDIF + + STMFD r1!, {r4 - r11} ; push r4 - r11 register + LDR r0, [r0] + STR r1, [r0] ; update from thread stack pointer + +swtich_to_thread + LDR r1, =rt_interrupt_to_thread + LDR r1, [r1] + LDR r1, [r1] ; load thread stack pointer + + LDMFD r1!, {r4 - r11} ; pop r4 - r11 register + + IF {FPU} != "SoftVFP" + VLDMFD r1!, {d8 - d15} ; pop FPU register s16~s31 + ENDIF + + MSR psp, r1 ; update stack pointer + +pendsv_exit + ; restore interrupt + MSR PRIMASK, r2 + + ORR lr, lr, #0x04 + BX lr + ENDP + +;/* +; * void rt_hw_context_switch_to(rt_uint32 to); +; * r0 --> to +; * this fucntion is used to perform the first thread switch +; */ +rt_hw_context_switch_to PROC + EXPORT rt_hw_context_switch_to + ; set to thread + LDR r1, =rt_interrupt_to_thread + STR r0, [r1] + + ; set from thread to 0 + LDR r1, =rt_interrupt_from_thread + MOV r0, #0x0 + STR r0, [r1] + + ; set interrupt flag to 1 + LDR r1, =rt_thread_switch_interrupt_flag + MOV r0, #1 + STR r0, [r1] + + ; set the PendSV exception priority + LDR r0, =NVIC_SYSPRI2 + LDR r1, =NVIC_PENDSV_PRI + LDR.W r2, [r0,#0x00] ; read + ORR r1,r1,r2 ; modify + STR r1, [r0] ; write-back + + ; trigger the PendSV exception (causes context switch) + LDR r0, =NVIC_INT_CTRL + LDR r1, =NVIC_PENDSVSET + STR r1, [r0] + + ; enable interrupts at processor level + CPSIE I + + ; never reach here! + ENDP + +; compatible with old version +rt_hw_interrupt_thread_switch PROC + EXPORT rt_hw_interrupt_thread_switch + BX lr + NOP + ENDP + + IMPORT rt_hw_hard_fault_exception + EXPORT HardFault_Handler +HardFault_Handler PROC + + ; get current context + MRS r0, psp ; get fault thread stack pointer + PUSH {lr} + BL rt_hw_hard_fault_exception + POP {lr} + + ORR lr, lr, #0x04 + BX lr + ENDP + + END diff --git a/libcpu/arm/lpc214x/context_rvds.S b/libcpu/arm/lpc214x/context_rvds.S index b3a3b5bf8e..762b67d42e 100644 --- a/libcpu/arm/lpc214x/context_rvds.S +++ b/libcpu/arm/lpc214x/context_rvds.S @@ -24,12 +24,12 @@ Mode_SYS EQU 0x1F I_Bit EQU 0x80 ; when I bit is set, IRQ is disabled F_Bit EQU 0x40 ; when F bit is set, FIQ is disabled -NOINT EQU 0xc0 ; disable interrupt in psr
+NOINT EQU 0xc0 ; disable interrupt in psr - AREA |.text|, CODE, READONLY, ALIGN=2
- ARM
- REQUIRE8
- PRESERVE8
+ AREA |.text|, CODE, READONLY, ALIGN=2 + ARM + REQUIRE8 + PRESERVE8 ;/* ; * rt_base_t rt_hw_interrupt_disable(); @@ -38,16 +38,16 @@ rt_hw_interrupt_disable PROC EXPORT rt_hw_interrupt_disable MRS r0, cpsr ORR r1, r0, #NOINT - MSR cpsr_c, r1
+ MSR cpsr_c, r1 BX lr - ENDP
+ ENDP ;/* ; * void rt_hw_interrupt_enable(rt_base_t level); ; */ rt_hw_interrupt_enable PROC EXPORT rt_hw_interrupt_enable - MSR cpsr_c, r0
+ MSR cpsr_c, r0 BX lr ENDP @@ -77,7 +77,7 @@ _ARM_MODE MSR cpsr_cxsf, r4 LDMFD sp!, {r0-r12, lr, pc}^ ; pop new task r0-r12, lr & pc, copy spsr to cpsr - ENDP
+ ENDP ;/* ; * void rt_hw_context_switch_to(rt_uint32 to); @@ -93,14 +93,14 @@ rt_hw_context_switch_to PROC MSR cpsr_cxsf, r4 LDMFD sp!, {r0-r12, lr, pc}^ ; pop new task r0-r12, lr & pc, copy spsr to cpsr - ENDP
+ ENDP ;/* ; * void rt_hw_context_switch_interrupt(rt_uint32 from, rt_uint32 to); ; */ IMPORT rt_thread_switch_interrupt_flag IMPORT rt_interrupt_from_thread - IMPORT rt_interrupt_to_thread
+ IMPORT rt_interrupt_to_thread rt_hw_context_switch_interrupt PROC EXPORT rt_hw_context_switch_interrupt @@ -114,9 +114,9 @@ rt_hw_context_switch_interrupt PROC STR r0, [r2] _reswitch LDR r2, =rt_interrupt_to_thread ; set rt_interrupt_to_thread - STR r1, [r2]
+ STR r1, [r2] BX lr - ENDP
+ ENDP ; /* ; * void rt_hw_context_switch_interrupt_do(rt_base_t flag) diff --git a/libcpu/arm/lpc214x/cpuport.c b/libcpu/arm/lpc214x/cpuport.c index 7986dad54b..512ff89f08 100644 --- a/libcpu/arm/lpc214x/cpuport.c +++ b/libcpu/arm/lpc214x/cpuport.c @@ -1,30 +1,30 @@ -/*
- * File : cpuport.c
- * This file is part of RT-Thread RTOS
- * COPYRIGHT (C) 2009 - 2011, RT-Thread Development Team
- *
- * The license and distribution terms for this file may be
- * found in the file LICENSE in this distribution or at
- * http://www.rt-thread.org/license/LICENSE
- *
- * Change Logs:
- * Date Author Notes
- * 2011-06-15 aozima the first version for lpc214x
- */
-
-#include <rtthread.h>
-#include "lpc214x.h"
-
-#define MAX_HANDLERS 32
-#define SVCMODE 0x13
+/* + * File : cpuport.c + * This file is part of RT-Thread RTOS + * COPYRIGHT (C) 2009 - 2011, RT-Thread Development Team + * + * The license and distribution terms for this file may be + * found in the file LICENSE in this distribution or at + * http://www.rt-thread.org/license/LICENSE + * + * Change Logs: + * Date Author Notes + * 2011-06-15 aozima the first version for lpc214x + */ + +#include <rtthread.h> +#include "lpc214x.h" -extern rt_uint32_t rt_interrupt_nest;
+#define MAX_HANDLERS 32 +#define SVCMODE 0x13 + +extern rt_uint32_t rt_interrupt_nest; /** * @addtogroup LPC214x */ -/*@{*/
-
+/*@{*/ + /** * This function will initialize thread stack * @@ -56,25 +56,25 @@ rt_uint8_t *rt_hw_stack_init(void *tentry, void *parameter, *(--stk) = 0; /* r2 */ *(--stk) = 0; /* r1 */ *(--stk) = (unsigned long)parameter; /* r0 : argument */ -
- /* cpsr */
- if ((rt_uint32_t)tentry & 0x01)
+ + /* cpsr */ + if ((rt_uint32_t)tentry & 0x01) *(--stk) = SVCMODE | 0x20; /* thumb mode */ - else
+ else *(--stk) = SVCMODE; /* arm mode */ /* return task's current stack address */ return (rt_uint8_t *)stk; -}
+} -/* exception and interrupt handler table */
-rt_uint32_t rt_interrupt_from_thread, rt_interrupt_to_thread;
+/* exception and interrupt handler table */ +rt_uint32_t rt_interrupt_from_thread, rt_interrupt_to_thread; rt_uint32_t rt_thread_switch_interrupt_flag; -
+ void rt_hw_interrupt_handler(int vector) { rt_kprintf("Unhandled interrupt %d occured!!!\n", vector); -}
+} /** * This function will initialize hardware interrupt @@ -82,21 +82,21 @@ void rt_hw_interrupt_handler(int vector) void rt_hw_interrupt_init() { rt_base_t index; - rt_uint32_t *vect_addr, *vect_ctl;
-
- /* initialize VIC*/
- VICIntEnClr = 0xffffffff;
- VICVectAddr = 0;
- /* set all to IRQ */
- VICIntSelect = 0;
+ rt_uint32_t *vect_addr, *vect_ctl; + + /* initialize VIC*/ + VICIntEnClr = 0xffffffff; + VICVectAddr = 0; + /* set all to IRQ */ + VICIntSelect = 0; for (index = 0; index < MAX_HANDLERS; index ++) { - vect_addr = (rt_uint32_t *)(VIC_BASE_ADDR + 0x100 + (index << 2));
- vect_ctl = (rt_uint32_t *)(VIC_BASE_ADDR + 0x200 + (index << 2));
-
- *vect_addr = (rt_uint32_t)rt_hw_interrupt_handler;
- *vect_ctl = 0xF;
+ vect_addr = (rt_uint32_t *)(VIC_BASE_ADDR + 0x100 + (index << 2)); + vect_ctl = (rt_uint32_t *)(VIC_BASE_ADDR + 0x200 + (index << 2)); + + *vect_addr = (rt_uint32_t)rt_hw_interrupt_handler; + *vect_ctl = 0xF; } /* init interrupt nest, and context in thread sp */ @@ -104,26 +104,26 @@ void rt_hw_interrupt_init() rt_interrupt_from_thread = 0; rt_interrupt_to_thread = 0; rt_thread_switch_interrupt_flag = 0; -}
+} /** * This function will mask a interrupt. * @param vector the interrupt number */ void rt_hw_interrupt_mask(int vector) -{
- VICIntEnClr = (1 << vector);
-}
-
+{ + VICIntEnClr = (1 << vector); +} + /** * This function will un-mask a interrupt. * @param vector the interrupt number */ void rt_hw_interrupt_umask(int vector) -{
+{ VICIntEnable = (1 << vector); -}
-
+} + /** * This function will install a interrupt service routine to a interrupt. * @param vector the interrupt number @@ -131,21 +131,21 @@ void rt_hw_interrupt_umask(int vector) * @param old_handler the old interrupt service routine */ void rt_hw_interrupt_install(int vector, rt_isr_handler_t new_handler, rt_isr_handler_t *old_handler) -{
+{ if(vector >= 0 && vector < MAX_HANDLERS) { - /* get VIC address */
- rt_uint32_t* vect_addr = (rt_uint32_t *)(VIC_BASE_ADDR + 0x100 + (vector << 2));
- rt_uint32_t* vect_ctl = (rt_uint32_t *)(VIC_BASE_ADDR + 0x200 + (vector << 2));
-
- /* assign IRQ slot and enable this slot */
- *vect_ctl = 0x20 | (vector & 0x1F);
-
+ /* get VIC address */ + rt_uint32_t* vect_addr = (rt_uint32_t *)(VIC_BASE_ADDR + 0x100 + (vector << 2)); + rt_uint32_t* vect_ctl = (rt_uint32_t *)(VIC_BASE_ADDR + 0x200 + (vector << 2)); + + /* assign IRQ slot and enable this slot */ + *vect_ctl = 0x20 | (vector & 0x1F); + if (old_handler != RT_NULL) *old_handler = (rt_isr_handler_t) *vect_addr; if (new_handler != RT_NULL) *vect_addr = (rt_uint32_t) new_handler; } -}
-
+} + /** * this function will reset CPU * @@ -163,22 +163,22 @@ void rt_hw_cpu_shutdown() rt_kprintf("shutdown...\n"); while (1); -}
-
+} + void rt_hw_trap_irq() -{
- rt_isr_handler_t isr_func;
-
- isr_func = (rt_isr_handler_t) VICVectAddr;
- isr_func(0);
-
- /* acknowledge Interrupt */
- // VICVectAddr = 0;
+{ + rt_isr_handler_t isr_func; + + isr_func = (rt_isr_handler_t) VICVectAddr; + isr_func(0); + + /* acknowledge Interrupt */ + // VICVectAddr = 0; } void rt_hw_trap_fiq() { rt_kprintf("fast interrupt request\n"); } -
+ /*@}*/ diff --git a/libcpu/arm/lpc214x/lpc214x.h b/libcpu/arm/lpc214x/lpc214x.h index ddf655a483..1805bc6c03 100644 --- a/libcpu/arm/lpc214x/lpc214x.h +++ b/libcpu/arm/lpc214x/lpc214x.h @@ -1,393 +1,393 @@ -/***********************************************************************/
-/* This file is part of the uVision/ARM development tools */
-/* Copyright KEIL ELEKTRONIK GmbH 2002-2005 */
-/***********************************************************************/
-/* */
-/* LPC214X.H: Header file for Philips LPC2141/42/44/46/48 */
-/* */
-/***********************************************************************/
-
-#ifndef __LPC214x_H
-#define __LPC214x_H
-
-/* Vectored Interrupt Controller (VIC) */
-#define VICIRQStatus (*((volatile unsigned long *) 0xFFFFF000))
-#define VICFIQStatus (*((volatile unsigned long *) 0xFFFFF004))
-#define VICRawIntr (*((volatile unsigned long *) 0xFFFFF008))
-#define VICIntSelect (*((volatile unsigned long *) 0xFFFFF00C))
-#define VICIntEnable (*((volatile unsigned long *) 0xFFFFF010))
-#define VICIntEnClr (*((volatile unsigned long *) 0xFFFFF014))
-#define VICSoftInt (*((volatile unsigned long *) 0xFFFFF018))
-#define VICSoftIntClr (*((volatile unsigned long *) 0xFFFFF01C))
-#define VICProtection (*((volatile unsigned long *) 0xFFFFF020))
-#define VICVectAddr (*((volatile unsigned long *) 0xFFFFF030))
-#define VICDefVectAddr (*((volatile unsigned long *) 0xFFFFF034))
-#define VICVectAddr0 (*((volatile unsigned long *) 0xFFFFF100))
-#define VICVectAddr1 (*((volatile unsigned long *) 0xFFFFF104))
-#define VICVectAddr2 (*((volatile unsigned long *) 0xFFFFF108))
-#define VICVectAddr3 (*((volatile unsigned long *) 0xFFFFF10C))
-#define VICVectAddr4 (*((volatile unsigned long *) 0xFFFFF110))
-#define VICVectAddr5 (*((volatile unsigned long *) 0xFFFFF114))
-#define VICVectAddr6 (*((volatile unsigned long *) 0xFFFFF118))
-#define VICVectAddr7 (*((volatile unsigned long *) 0xFFFFF11C))
-#define VICVectAddr8 (*((volatile unsigned long *) 0xFFFFF120))
-#define VICVectAddr9 (*((volatile unsigned long *) 0xFFFFF124))
-#define VICVectAddr10 (*((volatile unsigned long *) 0xFFFFF128))
-#define VICVectAddr11 (*((volatile unsigned long *) 0xFFFFF12C))
-#define VICVectAddr12 (*((volatile unsigned long *) 0xFFFFF130))
-#define VICVectAddr13 (*((volatile unsigned long *) 0xFFFFF134))
-#define VICVectAddr14 (*((volatile unsigned long *) 0xFFFFF138))
-#define VICVectAddr15 (*((volatile unsigned long *) 0xFFFFF13C))
-#define VICVectCntl0 (*((volatile unsigned long *) 0xFFFFF200))
-#define VICVectCntl1 (*((volatile unsigned long *) 0xFFFFF204))
-#define VICVectCntl2 (*((volatile unsigned long *) 0xFFFFF208))
-#define VICVectCntl3 (*((volatile unsigned long *) 0xFFFFF20C))
-#define VICVectCntl4 (*((volatile unsigned long *) 0xFFFFF210))
-#define VICVectCntl5 (*((volatile unsigned long *) 0xFFFFF214))
-#define VICVectCntl6 (*((volatile unsigned long *) 0xFFFFF218))
-#define VICVectCntl7 (*((volatile unsigned long *) 0xFFFFF21C))
-#define VICVectCntl8 (*((volatile unsigned long *) 0xFFFFF220))
-#define VICVectCntl9 (*((volatile unsigned long *) 0xFFFFF224))
-#define VICVectCntl10 (*((volatile unsigned long *) 0xFFFFF228))
-#define VICVectCntl11 (*((volatile unsigned long *) 0xFFFFF22C))
-#define VICVectCntl12 (*((volatile unsigned long *) 0xFFFFF230))
-#define VICVectCntl13 (*((volatile unsigned long *) 0xFFFFF234))
-#define VICVectCntl14 (*((volatile unsigned long *) 0xFFFFF238))
-#define VICVectCntl15 (*((volatile unsigned long *) 0xFFFFF23C))
-
-/* Pin Connect Block */
-#define PINSEL0 (*((volatile unsigned long *) 0xE002C000))
-#define PINSEL1 (*((volatile unsigned long *) 0xE002C004))
-#define PINSEL2 (*((volatile unsigned long *) 0xE002C014))
-
-/* General Purpose Input/Output (GPIO) */
-#define IOPIN0 (*((volatile unsigned long *) 0xE0028000))
-#define IOSET0 (*((volatile unsigned long *) 0xE0028004))
-#define IODIR0 (*((volatile unsigned long *) 0xE0028008))
-#define IOCLR0 (*((volatile unsigned long *) 0xE002800C))
-#define IOPIN1 (*((volatile unsigned long *) 0xE0028010))
-#define IOSET1 (*((volatile unsigned long *) 0xE0028014))
-#define IODIR1 (*((volatile unsigned long *) 0xE0028018))
-#define IOCLR1 (*((volatile unsigned long *) 0xE002801C))
-#define IO0PIN (*((volatile unsigned long *) 0xE0028000))
-#define IO0SET (*((volatile unsigned long *) 0xE0028004))
-#define IO0DIR (*((volatile unsigned long *) 0xE0028008))
-#define IO0CLR (*((volatile unsigned long *) 0xE002800C))
-#define IO1PIN (*((volatile unsigned long *) 0xE0028010))
-#define IO1SET (*((volatile unsigned long *) 0xE0028014))
-#define IO1DIR (*((volatile unsigned long *) 0xE0028018))
-#define IO1CLR (*((volatile unsigned long *) 0xE002801C))
-#define FIO0DIR (*((volatile unsigned long *) 0x3FFFC000))
-#define FIO0MASK (*((volatile unsigned long *) 0x3FFFC010))
-#define FIO0PIN (*((volatile unsigned long *) 0x3FFFC014))
-#define FIO0SET (*((volatile unsigned long *) 0x3FFFC018))
-#define FIO0CLR (*((volatile unsigned long *) 0x3FFFC01C))
-#define FIO1DIR (*((volatile unsigned long *) 0x3FFFC020))
-#define FIO1MASK (*((volatile unsigned long *) 0x3FFFC030))
-#define FIO1PIN (*((volatile unsigned long *) 0x3FFFC034))
-#define FIO1SET (*((volatile unsigned long *) 0x3FFFC038))
-#define FIO1CLR (*((volatile unsigned long *) 0x3FFFC03C))
-
-/* Memory Accelerator Module (MAM) */
-#define MAMCR (*((volatile unsigned char *) 0xE01FC000))
-#define MAMTIM (*((volatile unsigned char *) 0xE01FC004))
-#define MEMMAP (*((volatile unsigned char *) 0xE01FC040))
-
-/* Phase Locked Loop 0 (PLL0) */
-#define PLL0CON (*((volatile unsigned char *) 0xE01FC080))
-#define PLL0CFG (*((volatile unsigned char *) 0xE01FC084))
-#define PLL0STAT (*((volatile unsigned short*) 0xE01FC088))
-#define PLL0FEED (*((volatile unsigned char *) 0xE01FC08C))
-
-/* Phase Locked Loop 1 (PLL1) */
-#define PLL1CON (*((volatile unsigned char *) 0xE01FC0A0))
-#define PLL1CFG (*((volatile unsigned char *) 0xE01FC0A4))
-#define PLL1STAT (*((volatile unsigned short*) 0xE01FC0A8))
-#define PLL1FEED (*((volatile unsigned char *) 0xE01FC0AC))
-
-/* VPB Divider */
-#define VPBDIV (*((volatile unsigned char *) 0xE01FC100))
-
-/* Power Control */
-#define PCON (*((volatile unsigned char *) 0xE01FC0C0))
-#define PCONP (*((volatile unsigned long *) 0xE01FC0C4))
-
-/* External Interrupts */
-#define EXTINT (*((volatile unsigned char *) 0xE01FC140))
-#define INTWAKE (*((volatile unsigned short*) 0xE01FC144))
-#define EXTMODE (*((volatile unsigned char *) 0xE01FC148))
-#define EXTPOLAR (*((volatile unsigned char *) 0xE01FC14C))
-
-/* Reset */
-#define RSID (*((volatile unsigned char *) 0xE01FC180))
-
-/* Code Security / Debugging */
-#define CSPR (*((volatile unsigned char *) 0xE01FC184))
-
-/* System Control Miscellaneous */
-#define SCS (*((volatile unsigned long *) 0xE01FC1A0))
-
-/* Timer 0 */
-#define T0IR (*((volatile unsigned long *) 0xE0004000))
-#define T0TCR (*((volatile unsigned long *) 0xE0004004))
-#define T0TC (*((volatile unsigned long *) 0xE0004008))
-#define T0PR (*((volatile unsigned long *) 0xE000400C))
-#define T0PC (*((volatile unsigned long *) 0xE0004010))
-#define T0MCR (*((volatile unsigned long *) 0xE0004014))
-#define T0MR0 (*((volatile unsigned long *) 0xE0004018))
-#define T0MR1 (*((volatile unsigned long *) 0xE000401C))
-#define T0MR2 (*((volatile unsigned long *) 0xE0004020))
-#define T0MR3 (*((volatile unsigned long *) 0xE0004024))
-#define T0CCR (*((volatile unsigned long *) 0xE0004028))
-#define T0CR0 (*((volatile unsigned long *) 0xE000402C))
-#define T0CR1 (*((volatile unsigned long *) 0xE0004030))
-#define T0CR2 (*((volatile unsigned long *) 0xE0004034))
-#define T0CR3 (*((volatile unsigned long *) 0xE0004038))
-#define T0EMR (*((volatile unsigned long *) 0xE000403C))
-#define T0CTCR (*((volatile unsigned long *) 0xE0004070))
-
-/* Timer 1 */
-#define T1IR (*((volatile unsigned long *) 0xE0008000))
-#define T1TCR (*((volatile unsigned long *) 0xE0008004))
-#define T1TC (*((volatile unsigned long *) 0xE0008008))
-#define T1PR (*((volatile unsigned long *) 0xE000800C))
-#define T1PC (*((volatile unsigned long *) 0xE0008010))
-#define T1MCR (*((volatile unsigned long *) 0xE0008014))
-#define T1MR0 (*((volatile unsigned long *) 0xE0008018))
-#define T1MR1 (*((volatile unsigned long *) 0xE000801C))
-#define T1MR2 (*((volatile unsigned long *) 0xE0008020))
-#define T1MR3 (*((volatile unsigned long *) 0xE0008024))
-#define T1CCR (*((volatile unsigned long *) 0xE0008028))
-#define T1CR0 (*((volatile unsigned long *) 0xE000802C))
-#define T1CR1 (*((volatile unsigned long *) 0xE0008030))
-#define T1CR2 (*((volatile unsigned long *) 0xE0008034))
-#define T1CR3 (*((volatile unsigned long *) 0xE0008038))
-#define T1EMR (*((volatile unsigned long *) 0xE000803C))
-#define T1CTCR (*((volatile unsigned long *) 0xE0008070))
-
-/* Pulse Width Modulator (PWM) */
-#define PWMIR (*((volatile unsigned long *) 0xE0014000))
-#define PWMTCR (*((volatile unsigned long *) 0xE0014004))
-#define PWMTC (*((volatile unsigned long *) 0xE0014008))
-#define PWMPR (*((volatile unsigned long *) 0xE001400C))
-#define PWMPC (*((volatile unsigned long *) 0xE0014010))
-#define PWMMCR (*((volatile unsigned long *) 0xE0014014))
-#define PWMMR0 (*((volatile unsigned long *) 0xE0014018))
-#define PWMMR1 (*((volatile unsigned long *) 0xE001401C))
-#define PWMMR2 (*((volatile unsigned long *) 0xE0014020))
-#define PWMMR3 (*((volatile unsigned long *) 0xE0014024))
-#define PWMMR4 (*((volatile unsigned long *) 0xE0014040))
-#define PWMMR5 (*((volatile unsigned long *) 0xE0014044))
-#define PWMMR6 (*((volatile unsigned long *) 0xE0014048))
-#define PWMPCR (*((volatile unsigned long *) 0xE001404C))
-#define PWMLER (*((volatile unsigned long *) 0xE0014050))
-
-/* Universal Asynchronous Receiver Transmitter 0 (UART0) */
-#define U0RBR (*((volatile unsigned char *) 0xE000C000))
-#define U0THR (*((volatile unsigned char *) 0xE000C000))
-#define U0IER (*((volatile unsigned long *) 0xE000C004))
-#define U0IIR (*((volatile unsigned long *) 0xE000C008))
-#define U0FCR (*((volatile unsigned char *) 0xE000C008))
-#define U0LCR (*((volatile unsigned char *) 0xE000C00C))
-#define U0MCR (*((volatile unsigned char *) 0xE000C010))
-#define U0LSR (*((volatile unsigned char *) 0xE000C014))
-#define U0MSR (*((volatile unsigned char *) 0xE000C018))
-#define U0SCR (*((volatile unsigned char *) 0xE000C01C))
-#define U0DLL (*((volatile unsigned char *) 0xE000C000))
-#define U0DLM (*((volatile unsigned char *) 0xE000C004))
-#define U0ACR (*((volatile unsigned long *) 0xE000C020))
-#define U0FDR (*((volatile unsigned long *) 0xE000C028))
-#define U0TER (*((volatile unsigned char *) 0xE000C030))
-
-/* Universal Asynchronous Receiver Transmitter 1 (UART1) */
-#define U1RBR (*((volatile unsigned char *) 0xE0010000))
-#define U1THR (*((volatile unsigned char *) 0xE0010000))
-#define U1IER (*((volatile unsigned long *) 0xE0010004))
-#define U1IIR (*((volatile unsigned long *) 0xE0010008))
-#define U1FCR (*((volatile unsigned char *) 0xE0010008))
-#define U1LCR (*((volatile unsigned char *) 0xE001000C))
-#define U1MCR (*((volatile unsigned char *) 0xE0010010))
-#define U1LSR (*((volatile unsigned char *) 0xE0010014))
-#define U1MSR (*((volatile unsigned char *) 0xE0010018))
-#define U1SCR (*((volatile unsigned char *) 0xE001001C))
-#define U1DLL (*((volatile unsigned char *) 0xE0010000))
-#define U1DLM (*((volatile unsigned char *) 0xE0010004))
-#define U1ACR (*((volatile unsigned long *) 0xE0010020))
-#define U1FDR (*((volatile unsigned long *) 0xE0010028))
-#define U1TER (*((volatile unsigned char *) 0xE0010030))
-
-/* I2C Interface 0 */
-#define I2C0CONSET (*((volatile unsigned char *) 0xE001C000))
-#define I2C0STAT (*((volatile unsigned char *) 0xE001C004))
-#define I2C0DAT (*((volatile unsigned char *) 0xE001C008))
-#define I2C0ADR (*((volatile unsigned char *) 0xE001C00C))
-#define I2C0SCLH (*((volatile unsigned short*) 0xE001C010))
-#define I2C0SCLL (*((volatile unsigned short*) 0xE001C014))
-#define I2C0CONCLR (*((volatile unsigned char *) 0xE001C018))
-
-/* I2C Interface 1 */
-#define I2C1CONSET (*((volatile unsigned char *) 0xE005C000))
-#define I2C1STAT (*((volatile unsigned char *) 0xE005C004))
-#define I2C1DAT (*((volatile unsigned char *) 0xE005C008))
-#define I2C1ADR (*((volatile unsigned char *) 0xE005C00C))
-#define I2C1SCLH (*((volatile unsigned short*) 0xE005C010))
-#define I2C1SCLL (*((volatile unsigned short*) 0xE005C014))
-#define I2C1CONCLR (*((volatile unsigned char *) 0xE005C018))
-
-/* SPI0 (Serial Peripheral Interface 0) */
-#define S0SPCR (*((volatile unsigned short*) 0xE0020000))
-#define S0SPSR (*((volatile unsigned char *) 0xE0020004))
-#define S0SPDR (*((volatile unsigned short*) 0xE0020008))
-#define S0SPCCR (*((volatile unsigned char *) 0xE002000C))
-#define S0SPINT (*((volatile unsigned char *) 0xE002001C))
-
-/* SSP Controller (SPI1) */
-#define SSPCR0 (*((volatile unsigned short*) 0xE0068000))
-#define SSPCR1 (*((volatile unsigned char *) 0xE0068004))
-#define SSPDR (*((volatile unsigned short*) 0xE0068008))
-#define SSPSR (*((volatile unsigned char *) 0xE006800C))
-#define SSPCPSR (*((volatile unsigned char *) 0xE0068010))
-#define SSPIMSC (*((volatile unsigned char *) 0xE0068014))
-#define SSPRIS (*((volatile unsigned char *) 0xE0068018))
-#define SSPMIS (*((volatile unsigned char *) 0xE006801C))
-#define SSPICR (*((volatile unsigned char *) 0xE0068020))
-
-/* Real Time Clock */
-#define ILR (*((volatile unsigned char *) 0xE0024000))
-#define CTC (*((volatile unsigned short*) 0xE0024004))
-#define CCR (*((volatile unsigned char *) 0xE0024008))
-#define CIIR (*((volatile unsigned char *) 0xE002400C))
-#define AMR (*((volatile unsigned char *) 0xE0024010))
-#define CTIME0 (*((volatile unsigned long *) 0xE0024014))
-#define CTIME1 (*((volatile unsigned long *) 0xE0024018))
-#define CTIME2 (*((volatile unsigned long *) 0xE002401C))
-#define SEC (*((volatile unsigned char *) 0xE0024020))
-#define MIN (*((volatile unsigned char *) 0xE0024024))
-#define HOUR (*((volatile unsigned char *) 0xE0024028))
-#define DOM (*((volatile unsigned char *) 0xE002402C))
-#define DOW (*((volatile unsigned char *) 0xE0024030))
-#define DOY (*((volatile unsigned short*) 0xE0024034))
-#define MONTH (*((volatile unsigned char *) 0xE0024038))
-#define YEAR (*((volatile unsigned short*) 0xE002403C))
-#define ALSEC (*((volatile unsigned char *) 0xE0024060))
-#define ALMIN (*((volatile unsigned char *) 0xE0024064))
-#define ALHOUR (*((volatile unsigned char *) 0xE0024068))
-#define ALDOM (*((volatile unsigned char *) 0xE002406C))
-#define ALDOW (*((volatile unsigned char *) 0xE0024070))
-#define ALDOY (*((volatile unsigned short*) 0xE0024074))
-#define ALMON (*((volatile unsigned char *) 0xE0024078))
-#define ALYEAR (*((volatile unsigned short*) 0xE002407C))
-#define PREINT (*((volatile unsigned short*) 0xE0024080))
-#define PREFRAC (*((volatile unsigned short*) 0xE0024084))
-
-/* A/D Converter 0 (AD0) */
-#define AD0CR (*((volatile unsigned long *) 0xE0034000))
-#define AD0GDR (*((volatile unsigned long *) 0xE0034004))
-#define AD0STAT (*((volatile unsigned long *) 0xE0034030))
-#define AD0INTEN (*((volatile unsigned long *) 0xE003400C))
-#define AD0DR0 (*((volatile unsigned long *) 0xE0034010))
-#define AD0DR1 (*((volatile unsigned long *) 0xE0034014))
-#define AD0DR2 (*((volatile unsigned long *) 0xE0034018))
-#define AD0DR3 (*((volatile unsigned long *) 0xE003401C))
-#define AD0DR4 (*((volatile unsigned long *) 0xE0034020))
-#define AD0DR5 (*((volatile unsigned long *) 0xE0034024))
-#define AD0DR6 (*((volatile unsigned long *) 0xE0034028))
-#define AD0DR7 (*((volatile unsigned long *) 0xE003402C))
-
-/* A/D Converter 1 (AD1) */
-#define AD1CR (*((volatile unsigned long *) 0xE0060000))
-#define AD1GDR (*((volatile unsigned long *) 0xE0060004))
-#define AD1STAT (*((volatile unsigned long *) 0xE0060030))
-#define AD1INTEN (*((volatile unsigned long *) 0xE006000C))
-#define AD1DR0 (*((volatile unsigned long *) 0xE0060010))
-#define AD1DR1 (*((volatile unsigned long *) 0xE0060014))
-#define AD1DR2 (*((volatile unsigned long *) 0xE0060018))
-#define AD1DR3 (*((volatile unsigned long *) 0xE006001C))
-#define AD1DR4 (*((volatile unsigned long *) 0xE0060020))
-#define AD1DR5 (*((volatile unsigned long *) 0xE0060024))
-#define AD1DR6 (*((volatile unsigned long *) 0xE0060028))
-#define AD1DR7 (*((volatile unsigned long *) 0xE006002C))
-
-/* A/D Converter Global */
-#define ADGSR (*((volatile unsigned long *) 0xE0034008))
-
-/* D/A Converter */
-#define DACR (*((volatile unsigned long *) 0xE006C000))
-
-/* Watchdog */
-#define WDMOD (*((volatile unsigned char *) 0xE0000000))
-#define WDTC (*((volatile unsigned long *) 0xE0000004))
-#define WDFEED (*((volatile unsigned char *) 0xE0000008))
-#define WDTV (*((volatile unsigned long *) 0xE000000C))
-
-/* USB Controller */
-#define USBIntSt (*((volatile unsigned long *) 0xE01FC1C0))
-#define USBDevIntSt (*((volatile unsigned long *) 0xE0090000))
-#define USBDevIntEn (*((volatile unsigned long *) 0xE0090004))
-#define USBDevIntClr (*((volatile unsigned long *) 0xE0090008))
-#define USBDevIntSet (*((volatile unsigned long *) 0xE009000C))
-#define USBDevIntPri (*((volatile unsigned char *) 0xE009002C))
-#define USBEpIntSt (*((volatile unsigned long *) 0xE0090030))
-#define USBEpIntEn (*((volatile unsigned long *) 0xE0090034))
-#define USBEpIntClr (*((volatile unsigned long *) 0xE0090038))
-#define USBEpIntSet (*((volatile unsigned long *) 0xE009003C))
-#define USBEpIntPri (*((volatile unsigned long *) 0xE0090040))
-#define USBReEp (*((volatile unsigned long *) 0xE0090044))
-#define USBEpInd (*((volatile unsigned long *) 0xE0090048))
-#define USBMaxPSize (*((volatile unsigned long *) 0xE009004C))
-#define USBRxData (*((volatile unsigned long *) 0xE0090018))
-#define USBRxPLen (*((volatile unsigned long *) 0xE0090020))
-#define USBTxData (*((volatile unsigned long *) 0xE009001C))
-#define USBTxPLen (*((volatile unsigned long *) 0xE0090024))
-#define USBCtrl (*((volatile unsigned long *) 0xE0090028))
-#define USBCmdCode (*((volatile unsigned long *) 0xE0090010))
-#define USBCmdData (*((volatile unsigned long *) 0xE0090014))
-#define USBDMARSt (*((volatile unsigned long *) 0xE0090050))
-#define USBDMARClr (*((volatile unsigned long *) 0xE0090054))
-#define USBDMARSet (*((volatile unsigned long *) 0xE0090058))
-#define USBUDCAH (*((volatile unsigned long *) 0xE0090080))
-#define USBEpDMASt (*((volatile unsigned long *) 0xE0090084))
-#define USBEpDMAEn (*((volatile unsigned long *) 0xE0090088))
-#define USBEpDMADis (*((volatile unsigned long *) 0xE009008C))
-#define USBDMAIntSt (*((volatile unsigned long *) 0xE0090090))
-#define USBDMAIntEn (*((volatile unsigned long *) 0xE0090094))
-#define USBEoTIntSt (*((volatile unsigned long *) 0xE00900A0))
-#define USBEoTIntClr (*((volatile unsigned long *) 0xE00900A4))
-#define USBEoTIntSet (*((volatile unsigned long *) 0xE00900A8))
-#define USBNDDRIntSt (*((volatile unsigned long *) 0xE00900AC))
-#define USBNDDRIntClr (*((volatile unsigned long *) 0xE00900B0))
-#define USBNDDRIntSet (*((volatile unsigned long *) 0xE00900B4))
-#define USBSysErrIntSt (*((volatile unsigned long *) 0xE00900B8))
-#define USBSysErrIntClr (*((volatile unsigned long *) 0xE00900BC))
-#define USBSysErrIntSet (*((volatile unsigned long *) 0xE00900C0))
-
-#define VIC_BASE_ADDR 0xFFFFF000
-
-enum LPC214x_INT
-{
- WDT_INT = 0,
- SW_INT_reserved,
- DbgCommRx_INT,
- DbgCommTx_INT,
- TIMER0_INT,
- TIMER1_INT,
- UART0_INT,
- UART1_INT,
- PWM0_INT,
- I2C0_INT,
- SP0_INT,
- SP1_INT,
- PLL_INT,
- RTC_INT,
- EINT0_INT,
- EINT1_INT,
- EINT2_INT,
- EINT3_INT,
- ADC0_INT,
- I2C1_INT,
- BOD_INT,
- ADC1_INT,
- USB_INT
-};
-
-#endif // __LPC214x_H
+/***********************************************************************/ +/* This file is part of the uVision/ARM development tools */ +/* Copyright KEIL ELEKTRONIK GmbH 2002-2005 */ +/***********************************************************************/ +/* */ +/* LPC214X.H: Header file for Philips LPC2141/42/44/46/48 */ +/* */ +/***********************************************************************/ + +#ifndef __LPC214x_H +#define __LPC214x_H + +/* Vectored Interrupt Controller (VIC) */ +#define VICIRQStatus (*((volatile unsigned long *) 0xFFFFF000)) +#define VICFIQStatus (*((volatile unsigned long *) 0xFFFFF004)) +#define VICRawIntr (*((volatile unsigned long *) 0xFFFFF008)) +#define VICIntSelect (*((volatile unsigned long *) 0xFFFFF00C)) +#define VICIntEnable (*((volatile unsigned long *) 0xFFFFF010)) +#define VICIntEnClr (*((volatile unsigned long *) 0xFFFFF014)) +#define VICSoftInt (*((volatile unsigned long *) 0xFFFFF018)) +#define VICSoftIntClr (*((volatile unsigned long *) 0xFFFFF01C)) +#define VICProtection (*((volatile unsigned long *) 0xFFFFF020)) +#define VICVectAddr (*((volatile unsigned long *) 0xFFFFF030)) +#define VICDefVectAddr (*((volatile unsigned long *) 0xFFFFF034)) +#define VICVectAddr0 (*((volatile unsigned long *) 0xFFFFF100)) +#define VICVectAddr1 (*((volatile unsigned long *) 0xFFFFF104)) +#define VICVectAddr2 (*((volatile unsigned long *) 0xFFFFF108)) +#define VICVectAddr3 (*((volatile unsigned long *) 0xFFFFF10C)) +#define VICVectAddr4 (*((volatile unsigned long *) 0xFFFFF110)) +#define VICVectAddr5 (*((volatile unsigned long *) 0xFFFFF114)) +#define VICVectAddr6 (*((volatile unsigned long *) 0xFFFFF118)) +#define VICVectAddr7 (*((volatile unsigned long *) 0xFFFFF11C)) +#define VICVectAddr8 (*((volatile unsigned long *) 0xFFFFF120)) +#define VICVectAddr9 (*((volatile unsigned long *) 0xFFFFF124)) +#define VICVectAddr10 (*((volatile unsigned long *) 0xFFFFF128)) +#define VICVectAddr11 (*((volatile unsigned long *) 0xFFFFF12C)) +#define VICVectAddr12 (*((volatile unsigned long *) 0xFFFFF130)) +#define VICVectAddr13 (*((volatile unsigned long *) 0xFFFFF134)) +#define VICVectAddr14 (*((volatile unsigned long *) 0xFFFFF138)) +#define VICVectAddr15 (*((volatile unsigned long *) 0xFFFFF13C)) +#define VICVectCntl0 (*((volatile unsigned long *) 0xFFFFF200)) +#define VICVectCntl1 (*((volatile unsigned long *) 0xFFFFF204)) +#define VICVectCntl2 (*((volatile unsigned long *) 0xFFFFF208)) +#define VICVectCntl3 (*((volatile unsigned long *) 0xFFFFF20C)) +#define VICVectCntl4 (*((volatile unsigned long *) 0xFFFFF210)) +#define VICVectCntl5 (*((volatile unsigned long *) 0xFFFFF214)) +#define VICVectCntl6 (*((volatile unsigned long *) 0xFFFFF218)) +#define VICVectCntl7 (*((volatile unsigned long *) 0xFFFFF21C)) +#define VICVectCntl8 (*((volatile unsigned long *) 0xFFFFF220)) +#define VICVectCntl9 (*((volatile unsigned long *) 0xFFFFF224)) +#define VICVectCntl10 (*((volatile unsigned long *) 0xFFFFF228)) +#define VICVectCntl11 (*((volatile unsigned long *) 0xFFFFF22C)) +#define VICVectCntl12 (*((volatile unsigned long *) 0xFFFFF230)) +#define VICVectCntl13 (*((volatile unsigned long *) 0xFFFFF234)) +#define VICVectCntl14 (*((volatile unsigned long *) 0xFFFFF238)) +#define VICVectCntl15 (*((volatile unsigned long *) 0xFFFFF23C)) + +/* Pin Connect Block */ +#define PINSEL0 (*((volatile unsigned long *) 0xE002C000)) +#define PINSEL1 (*((volatile unsigned long *) 0xE002C004)) +#define PINSEL2 (*((volatile unsigned long *) 0xE002C014)) + +/* General Purpose Input/Output (GPIO) */ +#define IOPIN0 (*((volatile unsigned long *) 0xE0028000)) +#define IOSET0 (*((volatile unsigned long *) 0xE0028004)) +#define IODIR0 (*((volatile unsigned long *) 0xE0028008)) +#define IOCLR0 (*((volatile unsigned long *) 0xE002800C)) +#define IOPIN1 (*((volatile unsigned long *) 0xE0028010)) +#define IOSET1 (*((volatile unsigned long *) 0xE0028014)) +#define IODIR1 (*((volatile unsigned long *) 0xE0028018)) +#define IOCLR1 (*((volatile unsigned long *) 0xE002801C)) +#define IO0PIN (*((volatile unsigned long *) 0xE0028000)) +#define IO0SET (*((volatile unsigned long *) 0xE0028004)) +#define IO0DIR (*((volatile unsigned long *) 0xE0028008)) +#define IO0CLR (*((volatile unsigned long *) 0xE002800C)) +#define IO1PIN (*((volatile unsigned long *) 0xE0028010)) +#define IO1SET (*((volatile unsigned long *) 0xE0028014)) +#define IO1DIR (*((volatile unsigned long *) 0xE0028018)) +#define IO1CLR (*((volatile unsigned long *) 0xE002801C)) +#define FIO0DIR (*((volatile unsigned long *) 0x3FFFC000)) +#define FIO0MASK (*((volatile unsigned long *) 0x3FFFC010)) +#define FIO0PIN (*((volatile unsigned long *) 0x3FFFC014)) +#define FIO0SET (*((volatile unsigned long *) 0x3FFFC018)) +#define FIO0CLR (*((volatile unsigned long *) 0x3FFFC01C)) +#define FIO1DIR (*((volatile unsigned long *) 0x3FFFC020)) +#define FIO1MASK (*((volatile unsigned long *) 0x3FFFC030)) +#define FIO1PIN (*((volatile unsigned long *) 0x3FFFC034)) +#define FIO1SET (*((volatile unsigned long *) 0x3FFFC038)) +#define FIO1CLR (*((volatile unsigned long *) 0x3FFFC03C)) + +/* Memory Accelerator Module (MAM) */ +#define MAMCR (*((volatile unsigned char *) 0xE01FC000)) +#define MAMTIM (*((volatile unsigned char *) 0xE01FC004)) +#define MEMMAP (*((volatile unsigned char *) 0xE01FC040)) + +/* Phase Locked Loop 0 (PLL0) */ +#define PLL0CON (*((volatile unsigned char *) 0xE01FC080)) +#define PLL0CFG (*((volatile unsigned char *) 0xE01FC084)) +#define PLL0STAT (*((volatile unsigned short*) 0xE01FC088)) +#define PLL0FEED (*((volatile unsigned char *) 0xE01FC08C)) + +/* Phase Locked Loop 1 (PLL1) */ +#define PLL1CON (*((volatile unsigned char *) 0xE01FC0A0)) +#define PLL1CFG (*((volatile unsigned char *) 0xE01FC0A4)) +#define PLL1STAT (*((volatile unsigned short*) 0xE01FC0A8)) +#define PLL1FEED (*((volatile unsigned char *) 0xE01FC0AC)) + +/* VPB Divider */ +#define VPBDIV (*((volatile unsigned char *) 0xE01FC100)) + +/* Power Control */ +#define PCON (*((volatile unsigned char *) 0xE01FC0C0)) +#define PCONP (*((volatile unsigned long *) 0xE01FC0C4)) + +/* External Interrupts */ +#define EXTINT (*((volatile unsigned char *) 0xE01FC140)) +#define INTWAKE (*((volatile unsigned short*) 0xE01FC144)) +#define EXTMODE (*((volatile unsigned char *) 0xE01FC148)) +#define EXTPOLAR (*((volatile unsigned char *) 0xE01FC14C)) + +/* Reset */ +#define RSID (*((volatile unsigned char *) 0xE01FC180)) + +/* Code Security / Debugging */ +#define CSPR (*((volatile unsigned char *) 0xE01FC184)) + +/* System Control Miscellaneous */ +#define SCS (*((volatile unsigned long *) 0xE01FC1A0)) + +/* Timer 0 */ +#define T0IR (*((volatile unsigned long *) 0xE0004000)) +#define T0TCR (*((volatile unsigned long *) 0xE0004004)) +#define T0TC (*((volatile unsigned long *) 0xE0004008)) +#define T0PR (*((volatile unsigned long *) 0xE000400C)) +#define T0PC (*((volatile unsigned long *) 0xE0004010)) +#define T0MCR (*((volatile unsigned long *) 0xE0004014)) +#define T0MR0 (*((volatile unsigned long *) 0xE0004018)) +#define T0MR1 (*((volatile unsigned long *) 0xE000401C)) +#define T0MR2 (*((volatile unsigned long *) 0xE0004020)) +#define T0MR3 (*((volatile unsigned long *) 0xE0004024)) +#define T0CCR (*((volatile unsigned long *) 0xE0004028)) +#define T0CR0 (*((volatile unsigned long *) 0xE000402C)) +#define T0CR1 (*((volatile unsigned long *) 0xE0004030)) +#define T0CR2 (*((volatile unsigned long *) 0xE0004034)) +#define T0CR3 (*((volatile unsigned long *) 0xE0004038)) +#define T0EMR (*((volatile unsigned long *) 0xE000403C)) +#define T0CTCR (*((volatile unsigned long *) 0xE0004070)) + +/* Timer 1 */ +#define T1IR (*((volatile unsigned long *) 0xE0008000)) +#define T1TCR (*((volatile unsigned long *) 0xE0008004)) +#define T1TC (*((volatile unsigned long *) 0xE0008008)) +#define T1PR (*((volatile unsigned long *) 0xE000800C)) +#define T1PC (*((volatile unsigned long *) 0xE0008010)) +#define T1MCR (*((volatile unsigned long *) 0xE0008014)) +#define T1MR0 (*((volatile unsigned long *) 0xE0008018)) +#define T1MR1 (*((volatile unsigned long *) 0xE000801C)) +#define T1MR2 (*((volatile unsigned long *) 0xE0008020)) +#define T1MR3 (*((volatile unsigned long *) 0xE0008024)) +#define T1CCR (*((volatile unsigned long *) 0xE0008028)) +#define T1CR0 (*((volatile unsigned long *) 0xE000802C)) +#define T1CR1 (*((volatile unsigned long *) 0xE0008030)) +#define T1CR2 (*((volatile unsigned long *) 0xE0008034)) +#define T1CR3 (*((volatile unsigned long *) 0xE0008038)) +#define T1EMR (*((volatile unsigned long *) 0xE000803C)) +#define T1CTCR (*((volatile unsigned long *) 0xE0008070)) + +/* Pulse Width Modulator (PWM) */ +#define PWMIR (*((volatile unsigned long *) 0xE0014000)) +#define PWMTCR (*((volatile unsigned long *) 0xE0014004)) +#define PWMTC (*((volatile unsigned long *) 0xE0014008)) +#define PWMPR (*((volatile unsigned long *) 0xE001400C)) +#define PWMPC (*((volatile unsigned long *) 0xE0014010)) +#define PWMMCR (*((volatile unsigned long *) 0xE0014014)) +#define PWMMR0 (*((volatile unsigned long *) 0xE0014018)) +#define PWMMR1 (*((volatile unsigned long *) 0xE001401C)) +#define PWMMR2 (*((volatile unsigned long *) 0xE0014020)) +#define PWMMR3 (*((volatile unsigned long *) 0xE0014024)) +#define PWMMR4 (*((volatile unsigned long *) 0xE0014040)) +#define PWMMR5 (*((volatile unsigned long *) 0xE0014044)) +#define PWMMR6 (*((volatile unsigned long *) 0xE0014048)) +#define PWMPCR (*((volatile unsigned long *) 0xE001404C)) +#define PWMLER (*((volatile unsigned long *) 0xE0014050)) + +/* Universal Asynchronous Receiver Transmitter 0 (UART0) */ +#define U0RBR (*((volatile unsigned char *) 0xE000C000)) +#define U0THR (*((volatile unsigned char *) 0xE000C000)) +#define U0IER (*((volatile unsigned long *) 0xE000C004)) +#define U0IIR (*((volatile unsigned long *) 0xE000C008)) +#define U0FCR (*((volatile unsigned char *) 0xE000C008)) +#define U0LCR (*((volatile unsigned char *) 0xE000C00C)) +#define U0MCR (*((volatile unsigned char *) 0xE000C010)) +#define U0LSR (*((volatile unsigned char *) 0xE000C014)) +#define U0MSR (*((volatile unsigned char *) 0xE000C018)) +#define U0SCR (*((volatile unsigned char *) 0xE000C01C)) +#define U0DLL (*((volatile unsigned char *) 0xE000C000)) +#define U0DLM (*((volatile unsigned char *) 0xE000C004)) +#define U0ACR (*((volatile unsigned long *) 0xE000C020)) +#define U0FDR (*((volatile unsigned long *) 0xE000C028)) +#define U0TER (*((volatile unsigned char *) 0xE000C030)) + +/* Universal Asynchronous Receiver Transmitter 1 (UART1) */ +#define U1RBR (*((volatile unsigned char *) 0xE0010000)) +#define U1THR (*((volatile unsigned char *) 0xE0010000)) +#define U1IER (*((volatile unsigned long *) 0xE0010004)) +#define U1IIR (*((volatile unsigned long *) 0xE0010008)) +#define U1FCR (*((volatile unsigned char *) 0xE0010008)) +#define U1LCR (*((volatile unsigned char *) 0xE001000C)) +#define U1MCR (*((volatile unsigned char *) 0xE0010010)) +#define U1LSR (*((volatile unsigned char *) 0xE0010014)) +#define U1MSR (*((volatile unsigned char *) 0xE0010018)) +#define U1SCR (*((volatile unsigned char *) 0xE001001C)) +#define U1DLL (*((volatile unsigned char *) 0xE0010000)) +#define U1DLM (*((volatile unsigned char *) 0xE0010004)) +#define U1ACR (*((volatile unsigned long *) 0xE0010020)) +#define U1FDR (*((volatile unsigned long *) 0xE0010028)) +#define U1TER (*((volatile unsigned char *) 0xE0010030)) + +/* I2C Interface 0 */ +#define I2C0CONSET (*((volatile unsigned char *) 0xE001C000)) +#define I2C0STAT (*((volatile unsigned char *) 0xE001C004)) +#define I2C0DAT (*((volatile unsigned char *) 0xE001C008)) +#define I2C0ADR (*((volatile unsigned char *) 0xE001C00C)) +#define I2C0SCLH (*((volatile unsigned short*) 0xE001C010)) +#define I2C0SCLL (*((volatile unsigned short*) 0xE001C014)) +#define I2C0CONCLR (*((volatile unsigned char *) 0xE001C018)) + +/* I2C Interface 1 */ +#define I2C1CONSET (*((volatile unsigned char *) 0xE005C000)) +#define I2C1STAT (*((volatile unsigned char *) 0xE005C004)) +#define I2C1DAT (*((volatile unsigned char *) 0xE005C008)) +#define I2C1ADR (*((volatile unsigned char *) 0xE005C00C)) +#define I2C1SCLH (*((volatile unsigned short*) 0xE005C010)) +#define I2C1SCLL (*((volatile unsigned short*) 0xE005C014)) +#define I2C1CONCLR (*((volatile unsigned char *) 0xE005C018)) + +/* SPI0 (Serial Peripheral Interface 0) */ +#define S0SPCR (*((volatile unsigned short*) 0xE0020000)) +#define S0SPSR (*((volatile unsigned char *) 0xE0020004)) +#define S0SPDR (*((volatile unsigned short*) 0xE0020008)) +#define S0SPCCR (*((volatile unsigned char *) 0xE002000C)) +#define S0SPINT (*((volatile unsigned char *) 0xE002001C)) + +/* SSP Controller (SPI1) */ +#define SSPCR0 (*((volatile unsigned short*) 0xE0068000)) +#define SSPCR1 (*((volatile unsigned char *) 0xE0068004)) +#define SSPDR (*((volatile unsigned short*) 0xE0068008)) +#define SSPSR (*((volatile unsigned char *) 0xE006800C)) +#define SSPCPSR (*((volatile unsigned char *) 0xE0068010)) +#define SSPIMSC (*((volatile unsigned char *) 0xE0068014)) +#define SSPRIS (*((volatile unsigned char *) 0xE0068018)) +#define SSPMIS (*((volatile unsigned char *) 0xE006801C)) +#define SSPICR (*((volatile unsigned char *) 0xE0068020)) + +/* Real Time Clock */ +#define ILR (*((volatile unsigned char *) 0xE0024000)) +#define CTC (*((volatile unsigned short*) 0xE0024004)) +#define CCR (*((volatile unsigned char *) 0xE0024008)) +#define CIIR (*((volatile unsigned char *) 0xE002400C)) +#define AMR (*((volatile unsigned char *) 0xE0024010)) +#define CTIME0 (*((volatile unsigned long *) 0xE0024014)) +#define CTIME1 (*((volatile unsigned long *) 0xE0024018)) +#define CTIME2 (*((volatile unsigned long *) 0xE002401C)) +#define SEC (*((volatile unsigned char *) 0xE0024020)) +#define MIN (*((volatile unsigned char *) 0xE0024024)) +#define HOUR (*((volatile unsigned char *) 0xE0024028)) +#define DOM (*((volatile unsigned char *) 0xE002402C)) +#define DOW (*((volatile unsigned char *) 0xE0024030)) +#define DOY (*((volatile unsigned short*) 0xE0024034)) +#define MONTH (*((volatile unsigned char *) 0xE0024038)) +#define YEAR (*((volatile unsigned short*) 0xE002403C)) +#define ALSEC (*((volatile unsigned char *) 0xE0024060)) +#define ALMIN (*((volatile unsigned char *) 0xE0024064)) +#define ALHOUR (*((volatile unsigned char *) 0xE0024068)) +#define ALDOM (*((volatile unsigned char *) 0xE002406C)) +#define ALDOW (*((volatile unsigned char *) 0xE0024070)) +#define ALDOY (*((volatile unsigned short*) 0xE0024074)) +#define ALMON (*((volatile unsigned char *) 0xE0024078)) +#define ALYEAR (*((volatile unsigned short*) 0xE002407C)) +#define PREINT (*((volatile unsigned short*) 0xE0024080)) +#define PREFRAC (*((volatile unsigned short*) 0xE0024084)) + +/* A/D Converter 0 (AD0) */ +#define AD0CR (*((volatile unsigned long *) 0xE0034000)) +#define AD0GDR (*((volatile unsigned long *) 0xE0034004)) +#define AD0STAT (*((volatile unsigned long *) 0xE0034030)) +#define AD0INTEN (*((volatile unsigned long *) 0xE003400C)) +#define AD0DR0 (*((volatile unsigned long *) 0xE0034010)) +#define AD0DR1 (*((volatile unsigned long *) 0xE0034014)) +#define AD0DR2 (*((volatile unsigned long *) 0xE0034018)) +#define AD0DR3 (*((volatile unsigned long *) 0xE003401C)) +#define AD0DR4 (*((volatile unsigned long *) 0xE0034020)) +#define AD0DR5 (*((volatile unsigned long *) 0xE0034024)) +#define AD0DR6 (*((volatile unsigned long *) 0xE0034028)) +#define AD0DR7 (*((volatile unsigned long *) 0xE003402C)) + +/* A/D Converter 1 (AD1) */ +#define AD1CR (*((volatile unsigned long *) 0xE0060000)) +#define AD1GDR (*((volatile unsigned long *) 0xE0060004)) +#define AD1STAT (*((volatile unsigned long *) 0xE0060030)) +#define AD1INTEN (*((volatile unsigned long *) 0xE006000C)) +#define AD1DR0 (*((volatile unsigned long *) 0xE0060010)) +#define AD1DR1 (*((volatile unsigned long *) 0xE0060014)) +#define AD1DR2 (*((volatile unsigned long *) 0xE0060018)) +#define AD1DR3 (*((volatile unsigned long *) 0xE006001C)) +#define AD1DR4 (*((volatile unsigned long *) 0xE0060020)) +#define AD1DR5 (*((volatile unsigned long *) 0xE0060024)) +#define AD1DR6 (*((volatile unsigned long *) 0xE0060028)) +#define AD1DR7 (*((volatile unsigned long *) 0xE006002C)) + +/* A/D Converter Global */ +#define ADGSR (*((volatile unsigned long *) 0xE0034008)) + +/* D/A Converter */ +#define DACR (*((volatile unsigned long *) 0xE006C000)) + +/* Watchdog */ +#define WDMOD (*((volatile unsigned char *) 0xE0000000)) +#define WDTC (*((volatile unsigned long *) 0xE0000004)) +#define WDFEED (*((volatile unsigned char *) 0xE0000008)) +#define WDTV (*((volatile unsigned long *) 0xE000000C)) + +/* USB Controller */ +#define USBIntSt (*((volatile unsigned long *) 0xE01FC1C0)) +#define USBDevIntSt (*((volatile unsigned long *) 0xE0090000)) +#define USBDevIntEn (*((volatile unsigned long *) 0xE0090004)) +#define USBDevIntClr (*((volatile unsigned long *) 0xE0090008)) +#define USBDevIntSet (*((volatile unsigned long *) 0xE009000C)) +#define USBDevIntPri (*((volatile unsigned char *) 0xE009002C)) +#define USBEpIntSt (*((volatile unsigned long *) 0xE0090030)) +#define USBEpIntEn (*((volatile unsigned long *) 0xE0090034)) +#define USBEpIntClr (*((volatile unsigned long *) 0xE0090038)) +#define USBEpIntSet (*((volatile unsigned long *) 0xE009003C)) +#define USBEpIntPri (*((volatile unsigned long *) 0xE0090040)) +#define USBReEp (*((volatile unsigned long *) 0xE0090044)) +#define USBEpInd (*((volatile unsigned long *) 0xE0090048)) +#define USBMaxPSize (*((volatile unsigned long *) 0xE009004C)) +#define USBRxData (*((volatile unsigned long *) 0xE0090018)) +#define USBRxPLen (*((volatile unsigned long *) 0xE0090020)) +#define USBTxData (*((volatile unsigned long *) 0xE009001C)) +#define USBTxPLen (*((volatile unsigned long *) 0xE0090024)) +#define USBCtrl (*((volatile unsigned long *) 0xE0090028)) +#define USBCmdCode (*((volatile unsigned long *) 0xE0090010)) +#define USBCmdData (*((volatile unsigned long *) 0xE0090014)) +#define USBDMARSt (*((volatile unsigned long *) 0xE0090050)) +#define USBDMARClr (*((volatile unsigned long *) 0xE0090054)) +#define USBDMARSet (*((volatile unsigned long *) 0xE0090058)) +#define USBUDCAH (*((volatile unsigned long *) 0xE0090080)) +#define USBEpDMASt (*((volatile unsigned long *) 0xE0090084)) +#define USBEpDMAEn (*((volatile unsigned long *) 0xE0090088)) +#define USBEpDMADis (*((volatile unsigned long *) 0xE009008C)) +#define USBDMAIntSt (*((volatile unsigned long *) 0xE0090090)) +#define USBDMAIntEn (*((volatile unsigned long *) 0xE0090094)) +#define USBEoTIntSt (*((volatile unsigned long *) 0xE00900A0)) +#define USBEoTIntClr (*((volatile unsigned long *) 0xE00900A4)) +#define USBEoTIntSet (*((volatile unsigned long *) 0xE00900A8)) +#define USBNDDRIntSt (*((volatile unsigned long *) 0xE00900AC)) +#define USBNDDRIntClr (*((volatile unsigned long *) 0xE00900B0)) +#define USBNDDRIntSet (*((volatile unsigned long *) 0xE00900B4)) +#define USBSysErrIntSt (*((volatile unsigned long *) 0xE00900B8)) +#define USBSysErrIntClr (*((volatile unsigned long *) 0xE00900BC)) +#define USBSysErrIntSet (*((volatile unsigned long *) 0xE00900C0)) + +#define VIC_BASE_ADDR 0xFFFFF000 + +enum LPC214x_INT +{ + WDT_INT = 0, + SW_INT_reserved, + DbgCommRx_INT, + DbgCommTx_INT, + TIMER0_INT, + TIMER1_INT, + UART0_INT, + UART1_INT, + PWM0_INT, + I2C0_INT, + SP0_INT, + SP1_INT, + PLL_INT, + RTC_INT, + EINT0_INT, + EINT1_INT, + EINT2_INT, + EINT3_INT, + ADC0_INT, + I2C1_INT, + BOD_INT, + ADC1_INT, + USB_INT +}; + +#endif // __LPC214x_H diff --git a/libcpu/arm/lpc214x/start_rvds.S b/libcpu/arm/lpc214x/start_rvds.S index bee5c64de3..bef523bc74 100644 --- a/libcpu/arm/lpc214x/start_rvds.S +++ b/libcpu/arm/lpc214x/start_rvds.S @@ -1,464 +1,464 @@ -;/*****************************************************************************/
-;/* STARTUP.S: Startup file for Philips LPC2000 */
-;/*****************************************************************************/
-;/* <<< Use Configuration Wizard in Context Menu >>> */
-;/*****************************************************************************/
-;/* This file is part of the uVision/ARM development tools. */
-;/* Copyright (c) 2005-2007 Keil Software. All rights reserved. */
-;/* This software may only be used under the terms of a valid, current, */
-;/* end user licence from KEIL for a compatible version of KEIL software */
-;/* development tools. Nothing else gives you the right to use this software. */
-;/*****************************************************************************/
-
-
-;/*
-; * The STARTUP.S code is executed after CPU Reset. This file may be
-; * translated with the following SET symbols. In uVision these SET
-; * symbols are entered under Options - ASM - Define.
-; *
-; * REMAP: when set the startup code initializes the register MEMMAP
-; * which overwrites the settings of the CPU configuration pins. The
-; * startup and interrupt vectors are remapped from:
-; * 0x00000000 default setting (not remapped)
-; * 0x80000000 when EXTMEM_MODE is used
-; * 0x40000000 when RAM_MODE is used
-; *
-; * EXTMEM_MODE: when set the device is configured for code execution
-; * from external memory starting at address 0x80000000.
-; *
-; * RAM_MODE: when set the device is configured for code execution
-; * from on-chip RAM starting at address 0x40000000.
-; *
-; * EXTERNAL_MODE: when set the PIN2SEL values are written that enable
-; * the external BUS at startup.
-; */
-
-
-; Standard definitions of Mode bits and Interrupt (I & F) flags in PSRs
-
-Mode_USR EQU 0x10
-Mode_FIQ EQU 0x11
-Mode_IRQ EQU 0x12
-Mode_SVC EQU 0x13
-Mode_ABT EQU 0x17
-Mode_UND EQU 0x1B
-Mode_SYS EQU 0x1F
-
-I_Bit EQU 0x80 ; when I bit is set, IRQ is disabled
-F_Bit EQU 0x40 ; when F bit is set, FIQ is disabled
-
-
-;// <h> Stack Configuration (Stack Sizes in Bytes)
-;// <o0> Undefined Mode <0x0-0xFFFFFFFF:8>
-;// <o1> Supervisor Mode <0x0-0xFFFFFFFF:8>
-;// <o2> Abort Mode <0x0-0xFFFFFFFF:8>
-;// <o3> Fast Interrupt Mode <0x0-0xFFFFFFFF:8>
-;// <o4> Interrupt Mode <0x0-0xFFFFFFFF:8>
-;// <o5> User/System Mode <0x0-0xFFFFFFFF:8>
-;// </h>
-
-UND_Stack_Size EQU 0x00000000
-SVC_Stack_Size EQU 0x00000100
-ABT_Stack_Size EQU 0x00000000
-FIQ_Stack_Size EQU 0x00000000
-IRQ_Stack_Size EQU 0x00000100
-USR_Stack_Size EQU 0x00000100
-
-ISR_Stack_Size EQU (UND_Stack_Size + SVC_Stack_Size + ABT_Stack_Size + \
- FIQ_Stack_Size + IRQ_Stack_Size)
-
- AREA STACK, NOINIT, READWRITE, ALIGN=3
-
-Stack_Mem SPACE USR_Stack_Size
-__initial_sp SPACE ISR_Stack_Size
-
-Stack_Top
-
-
-;// <h> Heap Configuration
-;// <o> Heap Size (in Bytes) <0x0-0xFFFFFFFF>
-;// </h>
-
-Heap_Size EQU 0x00000000
-
- AREA HEAP, NOINIT, READWRITE, ALIGN=3
-__heap_base
-Heap_Mem SPACE Heap_Size
-__heap_limit
-
-
-; VPBDIV definitions
-VPBDIV EQU 0xE01FC100 ; VPBDIV Address
-
-;// <e> VPBDIV Setup
-;// <i> Peripheral Bus Clock Rate
-;// <o1.0..1> VPBDIV: VPB Clock
-;// <0=> VPB Clock = CPU Clock / 4
-;// <1=> VPB Clock = CPU Clock
-;// <2=> VPB Clock = CPU Clock / 2
-;// <o1.4..5> XCLKDIV: XCLK Pin
-;// <0=> XCLK Pin = CPU Clock / 4
-;// <1=> XCLK Pin = CPU Clock
-;// <2=> XCLK Pin = CPU Clock / 2
-;// </e>
-VPBDIV_SETUP EQU 0
-VPBDIV_Val EQU 0x00000000
-
-
-; Phase Locked Loop (PLL) definitions
-PLL_BASE EQU 0xE01FC080 ; PLL Base Address
-PLLCON_OFS EQU 0x00 ; PLL Control Offset
-PLLCFG_OFS EQU 0x04 ; PLL Configuration Offset
-PLLSTAT_OFS EQU 0x08 ; PLL Status Offset
-PLLFEED_OFS EQU 0x0C ; PLL Feed Offset
-PLLCON_PLLE EQU (1<<0) ; PLL Enable
-PLLCON_PLLC EQU (1<<1) ; PLL Connect
-PLLCFG_MSEL EQU (0x1F<<0) ; PLL Multiplier
-PLLCFG_PSEL EQU (0x03<<5) ; PLL Divider
-PLLSTAT_PLOCK EQU (1<<10) ; PLL Lock Status
-
-;// <e> PLL Setup
-;// <o1.0..4> MSEL: PLL Multiplier Selection
-;// <1-32><#-1>
-;// <i> M Value
-;// <o1.5..6> PSEL: PLL Divider Selection
-;// <0=> 1 <1=> 2 <2=> 4 <3=> 8
-;// <i> P Value
-;// </e>
-PLL_SETUP EQU 1
-PLLCFG_Val EQU 0x00000024
-
-
-; Memory Accelerator Module (MAM) definitions
-MAM_BASE EQU 0xE01FC000 ; MAM Base Address
-MAMCR_OFS EQU 0x00 ; MAM Control Offset
-MAMTIM_OFS EQU 0x04 ; MAM Timing Offset
-
-;// <e> MAM Setup
-;// <o1.0..1> MAM Control
-;// <0=> Disabled
-;// <1=> Partially Enabled
-;// <2=> Fully Enabled
-;// <i> Mode
-;// <o2.0..2> MAM Timing
-;// <0=> Reserved <1=> 1 <2=> 2 <3=> 3
-;// <4=> 4 <5=> 5 <6=> 6 <7=> 7
-;// <i> Fetch Cycles
-;// </e>
-MAM_SETUP EQU 1
-MAMCR_Val EQU 0x00000002
-MAMTIM_Val EQU 0x00000004
-
-
-; External Memory Controller (EMC) definitions
-EMC_BASE EQU 0xFFE00000 ; EMC Base Address
-BCFG0_OFS EQU 0x00 ; BCFG0 Offset
-BCFG1_OFS EQU 0x04 ; BCFG1 Offset
-BCFG2_OFS EQU 0x08 ; BCFG2 Offset
-BCFG3_OFS EQU 0x0C ; BCFG3 Offset
-
-;// <e> External Memory Controller (EMC)
-EMC_SETUP EQU 0
-
-;// <e> Bank Configuration 0 (BCFG0)
-;// <o1.0..3> IDCY: Idle Cycles <0-15>
-;// <o1.5..9> WST1: Wait States 1 <0-31>
-;// <o1.11..15> WST2: Wait States 2 <0-31>
-;// <o1.10> RBLE: Read Byte Lane Enable
-;// <o1.26> WP: Write Protect
-;// <o1.27> BM: Burst ROM
-;// <o1.28..29> MW: Memory Width <0=> 8-bit <1=> 16-bit
-;// <2=> 32-bit <3=> Reserved
-;// </e>
-BCFG0_SETUP EQU 0
-BCFG0_Val EQU 0x0000FBEF
-
-;// <e> Bank Configuration 1 (BCFG1)
-;// <o1.0..3> IDCY: Idle Cycles <0-15>
-;// <o1.5..9> WST1: Wait States 1 <0-31>
-;// <o1.11..15> WST2: Wait States 2 <0-31>
-;// <o1.10> RBLE: Read Byte Lane Enable
-;// <o1.26> WP: Write Protect
-;// <o1.27> BM: Burst ROM
-;// <o1.28..29> MW: Memory Width <0=> 8-bit <1=> 16-bit
-;// <2=> 32-bit <3=> Reserved
-;// </e>
-BCFG1_SETUP EQU 0
-BCFG1_Val EQU 0x0000FBEF
-
-;// <e> Bank Configuration 2 (BCFG2)
-;// <o1.0..3> IDCY: Idle Cycles <0-15>
-;// <o1.5..9> WST1: Wait States 1 <0-31>
-;// <o1.11..15> WST2: Wait States 2 <0-31>
-;// <o1.10> RBLE: Read Byte Lane Enable
-;// <o1.26> WP: Write Protect
-;// <o1.27> BM: Burst ROM
-;// <o1.28..29> MW: Memory Width <0=> 8-bit <1=> 16-bit
-;// <2=> 32-bit <3=> Reserved
-;// </e>
-BCFG2_SETUP EQU 0
-BCFG2_Val EQU 0x0000FBEF
-
-;// <e> Bank Configuration 3 (BCFG3)
-;// <o1.0..3> IDCY: Idle Cycles <0-15>
-;// <o1.5..9> WST1: Wait States 1 <0-31>
-;// <o1.11..15> WST2: Wait States 2 <0-31>
-;// <o1.10> RBLE: Read Byte Lane Enable
-;// <o1.26> WP: Write Protect
-;// <o1.27> BM: Burst ROM
-;// <o1.28..29> MW: Memory Width <0=> 8-bit <1=> 16-bit
-;// <2=> 32-bit <3=> Reserved
-;// </e>
-BCFG3_SETUP EQU 0
-BCFG3_Val EQU 0x0000FBEF
-
-;// </e> End of EMC
-
-
-; External Memory Pins definitions
-PINSEL2 EQU 0xE002C014 ; PINSEL2 Address
-PINSEL2_Val EQU 0x0E6149E4 ; CS0..3, OE, WE, BLS0..3,
- ; D0..31, A2..23, JTAG Pins
-
-
- PRESERVE8
-
-
-; Area Definition and Entry Point
-; Startup Code must be linked first at Address at which it expects to run.
-
- AREA RESET, CODE, READONLY
- ARM
-
-
-; Exception Vectors
-; Mapped to Address 0.
-; Absolute addressing mode must be used.
-; Dummy Handlers are implemented as infinite loops which can be modified.
-
-Vectors LDR PC, Reset_Addr
- LDR PC, Undef_Addr
- LDR PC, SWI_Addr
- LDR PC, PAbt_Addr
- LDR PC, DAbt_Addr
- NOP ; Reserved Vector
- LDR PC, IRQ_Addr
- LDR PC, FIQ_Addr
-
-Reset_Addr DCD Reset_Handler
-Undef_Addr DCD Undef_Handler
-SWI_Addr DCD SWI_Handler
-PAbt_Addr DCD PAbt_Handler
-DAbt_Addr DCD DAbt_Handler
- DCD 0 ; Reserved Address
-IRQ_Addr DCD IRQ_Handler
-FIQ_Addr DCD FIQ_Handler
-
-Undef_Handler B Undef_Handler
-SWI_Handler B SWI_Handler
-PAbt_Handler B PAbt_Handler
-DAbt_Handler B DAbt_Handler
-FIQ_Handler B FIQ_Handler
-
-
-; Reset Handler
-
- EXPORT Reset_Handler
-Reset_Handler
-
-
-; Setup External Memory Pins
- IF :DEF:EXTERNAL_MODE
- LDR R0, =PINSEL2
- LDR R1, =PINSEL2_Val
- STR R1, [R0]
- ENDIF
-
-
-; Setup External Memory Controller
- IF EMC_SETUP <> 0
- LDR R0, =EMC_BASE
-
- IF BCFG0_SETUP <> 0
- LDR R1, =BCFG0_Val
- STR R1, [R0, #BCFG0_OFS]
- ENDIF
-
- IF BCFG1_SETUP <> 0
- LDR R1, =BCFG1_Val
- STR R1, [R0, #BCFG1_OFS]
- ENDIF
-
- IF BCFG2_SETUP <> 0
- LDR R1, =BCFG2_Val
- STR R1, [R0, #BCFG2_OFS]
- ENDIF
-
- IF BCFG3_SETUP <> 0
- LDR R1, =BCFG3_Val
- STR R1, [R0, #BCFG3_OFS]
- ENDIF
-
- ENDIF ; EMC_SETUP
-
-
-; Setup VPBDIV
- IF VPBDIV_SETUP <> 0
- LDR R0, =VPBDIV
- LDR R1, =VPBDIV_Val
- STR R1, [R0]
- ENDIF
-
-
-; Setup PLL
- IF PLL_SETUP <> 0
- LDR R0, =PLL_BASE
- MOV R1, #0xAA
- MOV R2, #0x55
-
-; Configure and Enable PLL
- MOV R3, #PLLCFG_Val
- STR R3, [R0, #PLLCFG_OFS]
- MOV R3, #PLLCON_PLLE
- STR R3, [R0, #PLLCON_OFS]
- STR R1, [R0, #PLLFEED_OFS]
- STR R2, [R0, #PLLFEED_OFS]
-
-; Wait until PLL Locked
-PLL_Loop LDR R3, [R0, #PLLSTAT_OFS]
- ANDS R3, R3, #PLLSTAT_PLOCK
- BEQ PLL_Loop
-
-; Switch to PLL Clock
- MOV R3, #(PLLCON_PLLE:OR:PLLCON_PLLC)
- STR R3, [R0, #PLLCON_OFS]
- STR R1, [R0, #PLLFEED_OFS]
- STR R2, [R0, #PLLFEED_OFS]
- ENDIF ; PLL_SETUP
-
-
-; Setup MAM
- IF MAM_SETUP <> 0
- LDR R0, =MAM_BASE
- MOV R1, #MAMTIM_Val
- STR R1, [R0, #MAMTIM_OFS]
- MOV R1, #MAMCR_Val
- STR R1, [R0, #MAMCR_OFS]
- ENDIF ; MAM_SETUP
-
-
-; Memory Mapping (when Interrupt Vectors are in RAM)
-MEMMAP EQU 0xE01FC040 ; Memory Mapping Control
- IF :DEF:REMAP
- LDR R0, =MEMMAP
- IF :DEF:EXTMEM_MODE
- MOV R1, #3
- ELIF :DEF:RAM_MODE
- MOV R1, #2
- ELSE
- MOV R1, #1
- ENDIF
- STR R1, [R0]
- ENDIF
-
-
-; Initialise Interrupt System
-; ...
-
-
-; Setup Stack for each mode
-
- LDR R0, =Stack_Top
-
-; Enter Undefined Instruction Mode and set its Stack Pointer
- MSR CPSR_c, #Mode_UND:OR:I_Bit:OR:F_Bit
- MOV SP, R0
- SUB R0, R0, #UND_Stack_Size
-
-; Enter Abort Mode and set its Stack Pointer
- MSR CPSR_c, #Mode_ABT:OR:I_Bit:OR:F_Bit
- MOV SP, R0
- SUB R0, R0, #ABT_Stack_Size
-
-; Enter FIQ Mode and set its Stack Pointer
- MSR CPSR_c, #Mode_FIQ:OR:I_Bit:OR:F_Bit
- MOV SP, R0
- SUB R0, R0, #FIQ_Stack_Size
-
-; Enter IRQ Mode and set its Stack Pointer
- MSR CPSR_c, #Mode_IRQ:OR:I_Bit:OR:F_Bit
- MOV SP, R0
- SUB R0, R0, #IRQ_Stack_Size
-
-; Enter Supervisor Mode and set its Stack Pointer
- MSR CPSR_c, #Mode_SVC:OR:I_Bit:OR:F_Bit
- MOV SP, R0
- ; SUB R0, R0, #SVC_Stack_Size
-
-; Enter User Mode and set its Stack Pointer
- ; RT-Thread does not use user mode
- ; MSR CPSR_c, #Mode_USR
- IF :DEF:__MICROLIB
-
- EXPORT __initial_sp
-
- ELSE
-
- ; MOV SP, R0
- ; SUB SL, SP, #USR_Stack_Size
-
- ENDIF
-
-; Enter the C code
-
- IMPORT __main
- LDR R0, =__main
- BX R0
-
- IMPORT rt_interrupt_enter
- IMPORT rt_interrupt_leave
- IMPORT rt_thread_switch_interrupt_flag
- IMPORT rt_interrupt_from_thread
- IMPORT rt_interrupt_to_thread
- IMPORT rt_hw_trap_irq
- IMPORT rt_hw_context_switch_interrupt_do
-
-IRQ_Handler PROC
- EXPORT IRQ_Handler
- STMFD sp!, {r0-r12,lr}
- BL rt_interrupt_enter
- BL rt_hw_trap_irq
- BL rt_interrupt_leave
-
- ; if rt_thread_switch_interrupt_flag set, jump to
- ; rt_hw_context_switch_interrupt_do and don't return
- LDR r0, =rt_thread_switch_interrupt_flag
- LDR r1, [r0]
- CMP r1, #1
- BEQ rt_hw_context_switch_interrupt_do
-
- LDMFD sp!, {r0-r12,lr}
- SUBS pc, lr, #4
- ENDP
-
- IF :DEF:__MICROLIB
-
- EXPORT __heap_base
- EXPORT __heap_limit
-
- ELSE
-; User Initial Stack & Heap
- AREA |.text|, CODE, READONLY
-
- IMPORT __use_two_region_memory
- EXPORT __user_initial_stackheap
-__user_initial_stackheap
-
- LDR R0, = Heap_Mem
- LDR R1, =(Stack_Mem + USR_Stack_Size)
- LDR R2, = (Heap_Mem + Heap_Size)
- LDR R3, = Stack_Mem
- BX LR
- ENDIF
-
- END
+;/*****************************************************************************/ +;/* STARTUP.S: Startup file for Philips LPC2000 */ +;/*****************************************************************************/ +;/* <<< Use Configuration Wizard in Context Menu >>> */ +;/*****************************************************************************/ +;/* This file is part of the uVision/ARM development tools. */ +;/* Copyright (c) 2005-2007 Keil Software. All rights reserved. */ +;/* This software may only be used under the terms of a valid, current, */ +;/* end user licence from KEIL for a compatible version of KEIL software */ +;/* development tools. Nothing else gives you the right to use this software. */ +;/*****************************************************************************/ + + +;/* +; * The STARTUP.S code is executed after CPU Reset. This file may be +; * translated with the following SET symbols. In uVision these SET +; * symbols are entered under Options - ASM - Define. +; * +; * REMAP: when set the startup code initializes the register MEMMAP +; * which overwrites the settings of the CPU configuration pins. The +; * startup and interrupt vectors are remapped from: +; * 0x00000000 default setting (not remapped) +; * 0x80000000 when EXTMEM_MODE is used +; * 0x40000000 when RAM_MODE is used +; * +; * EXTMEM_MODE: when set the device is configured for code execution +; * from external memory starting at address 0x80000000. +; * +; * RAM_MODE: when set the device is configured for code execution +; * from on-chip RAM starting at address 0x40000000. +; * +; * EXTERNAL_MODE: when set the PIN2SEL values are written that enable +; * the external BUS at startup. +; */ + + +; Standard definitions of Mode bits and Interrupt (I & F) flags in PSRs + +Mode_USR EQU 0x10 +Mode_FIQ EQU 0x11 +Mode_IRQ EQU 0x12 +Mode_SVC EQU 0x13 +Mode_ABT EQU 0x17 +Mode_UND EQU 0x1B +Mode_SYS EQU 0x1F + +I_Bit EQU 0x80 ; when I bit is set, IRQ is disabled +F_Bit EQU 0x40 ; when F bit is set, FIQ is disabled + + +;// <h> Stack Configuration (Stack Sizes in Bytes) +;// <o0> Undefined Mode <0x0-0xFFFFFFFF:8> +;// <o1> Supervisor Mode <0x0-0xFFFFFFFF:8> +;// <o2> Abort Mode <0x0-0xFFFFFFFF:8> +;// <o3> Fast Interrupt Mode <0x0-0xFFFFFFFF:8> +;// <o4> Interrupt Mode <0x0-0xFFFFFFFF:8> +;// <o5> User/System Mode <0x0-0xFFFFFFFF:8> +;// </h> + +UND_Stack_Size EQU 0x00000000 +SVC_Stack_Size EQU 0x00000100 +ABT_Stack_Size EQU 0x00000000 +FIQ_Stack_Size EQU 0x00000000 +IRQ_Stack_Size EQU 0x00000100 +USR_Stack_Size EQU 0x00000100 + +ISR_Stack_Size EQU (UND_Stack_Size + SVC_Stack_Size + ABT_Stack_Size + \ + FIQ_Stack_Size + IRQ_Stack_Size) + + AREA STACK, NOINIT, READWRITE, ALIGN=3 + +Stack_Mem SPACE USR_Stack_Size +__initial_sp SPACE ISR_Stack_Size + +Stack_Top + + +;// <h> Heap Configuration +;// <o> Heap Size (in Bytes) <0x0-0xFFFFFFFF> +;// </h> + +Heap_Size EQU 0x00000000 + + AREA HEAP, NOINIT, READWRITE, ALIGN=3 +__heap_base +Heap_Mem SPACE Heap_Size +__heap_limit + + +; VPBDIV definitions +VPBDIV EQU 0xE01FC100 ; VPBDIV Address + +;// <e> VPBDIV Setup +;// <i> Peripheral Bus Clock Rate +;// <o1.0..1> VPBDIV: VPB Clock +;// <0=> VPB Clock = CPU Clock / 4 +;// <1=> VPB Clock = CPU Clock +;// <2=> VPB Clock = CPU Clock / 2 +;// <o1.4..5> XCLKDIV: XCLK Pin +;// <0=> XCLK Pin = CPU Clock / 4 +;// <1=> XCLK Pin = CPU Clock +;// <2=> XCLK Pin = CPU Clock / 2 +;// </e> +VPBDIV_SETUP EQU 0 +VPBDIV_Val EQU 0x00000000 + + +; Phase Locked Loop (PLL) definitions +PLL_BASE EQU 0xE01FC080 ; PLL Base Address +PLLCON_OFS EQU 0x00 ; PLL Control Offset +PLLCFG_OFS EQU 0x04 ; PLL Configuration Offset +PLLSTAT_OFS EQU 0x08 ; PLL Status Offset +PLLFEED_OFS EQU 0x0C ; PLL Feed Offset +PLLCON_PLLE EQU (1<<0) ; PLL Enable +PLLCON_PLLC EQU (1<<1) ; PLL Connect +PLLCFG_MSEL EQU (0x1F<<0) ; PLL Multiplier +PLLCFG_PSEL EQU (0x03<<5) ; PLL Divider +PLLSTAT_PLOCK EQU (1<<10) ; PLL Lock Status + +;// <e> PLL Setup +;// <o1.0..4> MSEL: PLL Multiplier Selection +;// <1-32><#-1> +;// <i> M Value +;// <o1.5..6> PSEL: PLL Divider Selection +;// <0=> 1 <1=> 2 <2=> 4 <3=> 8 +;// <i> P Value +;// </e> +PLL_SETUP EQU 1 +PLLCFG_Val EQU 0x00000024 + + +; Memory Accelerator Module (MAM) definitions +MAM_BASE EQU 0xE01FC000 ; MAM Base Address +MAMCR_OFS EQU 0x00 ; MAM Control Offset +MAMTIM_OFS EQU 0x04 ; MAM Timing Offset + +;// <e> MAM Setup +;// <o1.0..1> MAM Control +;// <0=> Disabled +;// <1=> Partially Enabled +;// <2=> Fully Enabled +;// <i> Mode +;// <o2.0..2> MAM Timing +;// <0=> Reserved <1=> 1 <2=> 2 <3=> 3 +;// <4=> 4 <5=> 5 <6=> 6 <7=> 7 +;// <i> Fetch Cycles +;// </e> +MAM_SETUP EQU 1 +MAMCR_Val EQU 0x00000002 +MAMTIM_Val EQU 0x00000004 + + +; External Memory Controller (EMC) definitions +EMC_BASE EQU 0xFFE00000 ; EMC Base Address +BCFG0_OFS EQU 0x00 ; BCFG0 Offset +BCFG1_OFS EQU 0x04 ; BCFG1 Offset +BCFG2_OFS EQU 0x08 ; BCFG2 Offset +BCFG3_OFS EQU 0x0C ; BCFG3 Offset + +;// <e> External Memory Controller (EMC) +EMC_SETUP EQU 0 + +;// <e> Bank Configuration 0 (BCFG0) +;// <o1.0..3> IDCY: Idle Cycles <0-15> +;// <o1.5..9> WST1: Wait States 1 <0-31> +;// <o1.11..15> WST2: Wait States 2 <0-31> +;// <o1.10> RBLE: Read Byte Lane Enable +;// <o1.26> WP: Write Protect +;// <o1.27> BM: Burst ROM +;// <o1.28..29> MW: Memory Width <0=> 8-bit <1=> 16-bit +;// <2=> 32-bit <3=> Reserved +;// </e> +BCFG0_SETUP EQU 0 +BCFG0_Val EQU 0x0000FBEF + +;// <e> Bank Configuration 1 (BCFG1) +;// <o1.0..3> IDCY: Idle Cycles <0-15> +;// <o1.5..9> WST1: Wait States 1 <0-31> +;// <o1.11..15> WST2: Wait States 2 <0-31> +;// <o1.10> RBLE: Read Byte Lane Enable +;// <o1.26> WP: Write Protect +;// <o1.27> BM: Burst ROM +;// <o1.28..29> MW: Memory Width <0=> 8-bit <1=> 16-bit +;// <2=> 32-bit <3=> Reserved +;// </e> +BCFG1_SETUP EQU 0 +BCFG1_Val EQU 0x0000FBEF + +;// <e> Bank Configuration 2 (BCFG2) +;// <o1.0..3> IDCY: Idle Cycles <0-15> +;// <o1.5..9> WST1: Wait States 1 <0-31> +;// <o1.11..15> WST2: Wait States 2 <0-31> +;// <o1.10> RBLE: Read Byte Lane Enable +;// <o1.26> WP: Write Protect +;// <o1.27> BM: Burst ROM +;// <o1.28..29> MW: Memory Width <0=> 8-bit <1=> 16-bit +;// <2=> 32-bit <3=> Reserved +;// </e> +BCFG2_SETUP EQU 0 +BCFG2_Val EQU 0x0000FBEF + +;// <e> Bank Configuration 3 (BCFG3) +;// <o1.0..3> IDCY: Idle Cycles <0-15> +;// <o1.5..9> WST1: Wait States 1 <0-31> +;// <o1.11..15> WST2: Wait States 2 <0-31> +;// <o1.10> RBLE: Read Byte Lane Enable +;// <o1.26> WP: Write Protect +;// <o1.27> BM: Burst ROM +;// <o1.28..29> MW: Memory Width <0=> 8-bit <1=> 16-bit +;// <2=> 32-bit <3=> Reserved +;// </e> +BCFG3_SETUP EQU 0 +BCFG3_Val EQU 0x0000FBEF + +;// </e> End of EMC + + +; External Memory Pins definitions +PINSEL2 EQU 0xE002C014 ; PINSEL2 Address +PINSEL2_Val EQU 0x0E6149E4 ; CS0..3, OE, WE, BLS0..3, + ; D0..31, A2..23, JTAG Pins + + + PRESERVE8 + + +; Area Definition and Entry Point +; Startup Code must be linked first at Address at which it expects to run. + + AREA RESET, CODE, READONLY + ARM + + +; Exception Vectors +; Mapped to Address 0. +; Absolute addressing mode must be used. +; Dummy Handlers are implemented as infinite loops which can be modified. + +Vectors LDR PC, Reset_Addr + LDR PC, Undef_Addr + LDR PC, SWI_Addr + LDR PC, PAbt_Addr + LDR PC, DAbt_Addr + NOP ; Reserved Vector + LDR PC, IRQ_Addr + LDR PC, FIQ_Addr + +Reset_Addr DCD Reset_Handler +Undef_Addr DCD Undef_Handler +SWI_Addr DCD SWI_Handler +PAbt_Addr DCD PAbt_Handler +DAbt_Addr DCD DAbt_Handler + DCD 0 ; Reserved Address +IRQ_Addr DCD IRQ_Handler +FIQ_Addr DCD FIQ_Handler + +Undef_Handler B Undef_Handler +SWI_Handler B SWI_Handler +PAbt_Handler B PAbt_Handler +DAbt_Handler B DAbt_Handler +FIQ_Handler B FIQ_Handler + + +; Reset Handler + + EXPORT Reset_Handler +Reset_Handler + + +; Setup External Memory Pins + IF :DEF:EXTERNAL_MODE + LDR R0, =PINSEL2 + LDR R1, =PINSEL2_Val + STR R1, [R0] + ENDIF + + +; Setup External Memory Controller + IF EMC_SETUP <> 0 + LDR R0, =EMC_BASE + + IF BCFG0_SETUP <> 0 + LDR R1, =BCFG0_Val + STR R1, [R0, #BCFG0_OFS] + ENDIF + + IF BCFG1_SETUP <> 0 + LDR R1, =BCFG1_Val + STR R1, [R0, #BCFG1_OFS] + ENDIF + + IF BCFG2_SETUP <> 0 + LDR R1, =BCFG2_Val + STR R1, [R0, #BCFG2_OFS] + ENDIF + + IF BCFG3_SETUP <> 0 + LDR R1, =BCFG3_Val + STR R1, [R0, #BCFG3_OFS] + ENDIF + + ENDIF ; EMC_SETUP + + +; Setup VPBDIV + IF VPBDIV_SETUP <> 0 + LDR R0, =VPBDIV + LDR R1, =VPBDIV_Val + STR R1, [R0] + ENDIF + + +; Setup PLL + IF PLL_SETUP <> 0 + LDR R0, =PLL_BASE + MOV R1, #0xAA + MOV R2, #0x55 + +; Configure and Enable PLL + MOV R3, #PLLCFG_Val + STR R3, [R0, #PLLCFG_OFS] + MOV R3, #PLLCON_PLLE + STR R3, [R0, #PLLCON_OFS] + STR R1, [R0, #PLLFEED_OFS] + STR R2, [R0, #PLLFEED_OFS] + +; Wait until PLL Locked +PLL_Loop LDR R3, [R0, #PLLSTAT_OFS] + ANDS R3, R3, #PLLSTAT_PLOCK + BEQ PLL_Loop + +; Switch to PLL Clock + MOV R3, #(PLLCON_PLLE:OR:PLLCON_PLLC) + STR R3, [R0, #PLLCON_OFS] + STR R1, [R0, #PLLFEED_OFS] + STR R2, [R0, #PLLFEED_OFS] + ENDIF ; PLL_SETUP + + +; Setup MAM + IF MAM_SETUP <> 0 + LDR R0, =MAM_BASE + MOV R1, #MAMTIM_Val + STR R1, [R0, #MAMTIM_OFS] + MOV R1, #MAMCR_Val + STR R1, [R0, #MAMCR_OFS] + ENDIF ; MAM_SETUP + + +; Memory Mapping (when Interrupt Vectors are in RAM) +MEMMAP EQU 0xE01FC040 ; Memory Mapping Control + IF :DEF:REMAP + LDR R0, =MEMMAP + IF :DEF:EXTMEM_MODE + MOV R1, #3 + ELIF :DEF:RAM_MODE + MOV R1, #2 + ELSE + MOV R1, #1 + ENDIF + STR R1, [R0] + ENDIF + + +; Initialise Interrupt System +; ... + + +; Setup Stack for each mode + + LDR R0, =Stack_Top + +; Enter Undefined Instruction Mode and set its Stack Pointer + MSR CPSR_c, #Mode_UND:OR:I_Bit:OR:F_Bit + MOV SP, R0 + SUB R0, R0, #UND_Stack_Size + +; Enter Abort Mode and set its Stack Pointer + MSR CPSR_c, #Mode_ABT:OR:I_Bit:OR:F_Bit + MOV SP, R0 + SUB R0, R0, #ABT_Stack_Size + +; Enter FIQ Mode and set its Stack Pointer + MSR CPSR_c, #Mode_FIQ:OR:I_Bit:OR:F_Bit + MOV SP, R0 + SUB R0, R0, #FIQ_Stack_Size + +; Enter IRQ Mode and set its Stack Pointer + MSR CPSR_c, #Mode_IRQ:OR:I_Bit:OR:F_Bit + MOV SP, R0 + SUB R0, R0, #IRQ_Stack_Size + +; Enter Supervisor Mode and set its Stack Pointer + MSR CPSR_c, #Mode_SVC:OR:I_Bit:OR:F_Bit + MOV SP, R0 + ; SUB R0, R0, #SVC_Stack_Size + +; Enter User Mode and set its Stack Pointer + ; RT-Thread does not use user mode + ; MSR CPSR_c, #Mode_USR + IF :DEF:__MICROLIB + + EXPORT __initial_sp + + ELSE + + ; MOV SP, R0 + ; SUB SL, SP, #USR_Stack_Size + + ENDIF + +; Enter the C code + + IMPORT __main + LDR R0, =__main + BX R0 + + IMPORT rt_interrupt_enter + IMPORT rt_interrupt_leave + IMPORT rt_thread_switch_interrupt_flag + IMPORT rt_interrupt_from_thread + IMPORT rt_interrupt_to_thread + IMPORT rt_hw_trap_irq + IMPORT rt_hw_context_switch_interrupt_do + +IRQ_Handler PROC + EXPORT IRQ_Handler + STMFD sp!, {r0-r12,lr} + BL rt_interrupt_enter + BL rt_hw_trap_irq + BL rt_interrupt_leave + + ; if rt_thread_switch_interrupt_flag set, jump to + ; rt_hw_context_switch_interrupt_do and don't return + LDR r0, =rt_thread_switch_interrupt_flag + LDR r1, [r0] + CMP r1, #1 + BEQ rt_hw_context_switch_interrupt_do + + LDMFD sp!, {r0-r12,lr} + SUBS pc, lr, #4 + ENDP + + IF :DEF:__MICROLIB + + EXPORT __heap_base + EXPORT __heap_limit + + ELSE +; User Initial Stack & Heap + AREA |.text|, CODE, READONLY + + IMPORT __use_two_region_memory + EXPORT __user_initial_stackheap +__user_initial_stackheap + + LDR R0, = Heap_Mem + LDR R1, =(Stack_Mem + USR_Stack_Size) + LDR R2, = (Heap_Mem + Heap_Size) + LDR R3, = Stack_Mem + BX LR + ENDIF + + END diff --git a/libcpu/arm/lpc214x/startup_gcc.S b/libcpu/arm/lpc214x/startup_gcc.S index 1c25f3bd2e..ce13d57083 100644 --- a/libcpu/arm/lpc214x/startup_gcc.S +++ b/libcpu/arm/lpc214x/startup_gcc.S @@ -1,312 +1,312 @@ - .extern main /* �����ⲿC��� */
-
- .extern rt_interrupt_enter
- .extern rt_interrupt_leave
- .extern rt_thread_switch_interrupt_flag
- .extern rt_interrupt_from_thread
- .extern rt_interrupt_to_thread
- .extern rt_hw_trap_irq
-
- .global start
- .global endless_loop
- .global rt_hw_context_switch_interrupt_do
-
- /* Standard definitions of Mode bits and Interrupt (I & F) flags in PSRs */
- .set MODE_USR, 0x10 /* User Mode */
- .set MODE_FIQ, 0x11 /* FIQ Mode */
- .set MODE_IRQ, 0x12 /* IRQ Mode */
- .set MODE_SVC, 0x13 /* Supervisor Mode */
- .set MODE_ABT, 0x17 /* Abort Mode */
- .set MODE_UND, 0x1B /* Undefined Mode */
- .set MODE_SYS, 0x1F /* System Mode */
-
- .equ I_BIT, 0x80 /* when I bit is set, IRQ is disabled */
- .equ F_BIT, 0x40 /* when F bit is set, FIQ is disabled */
- .equ I_Bit, 0x80 /* when I bit is set, IRQ is disabled */
- .equ F_Bit, 0x40 /* when F bit is set, FIQ is disabled */
-
- /* VPBDIV definitions*/
- .equ VPBDIV, 0xE01FC100
- .set VPBDIV_VALUE, 0x00000000
-
- /* Phase Locked Loop (PLL) definitions*/
- .equ PLL_BASE, 0xE01FC080 /* PLL Base Address */
- .equ PLLCON_OFS, 0x00 /* PLL Control Offset */
- .equ PLLCFG_OFS, 0x04 /* PLL Configuration Offset */
- .equ PLLSTAT_OFS, 0x08 /* PLL Status Offset */
- .equ PLLFEED_OFS, 0x0C /* PLL Feed Offset */
- .equ PLLCON_PLLE, (1<<0) /* PLL Enable */
- .equ PLLCON_PLLC, (1<<1) /* PLL Connect */
- .equ PLLCFG_MSEL, (0x1F<<0) /* PLL Multiplier */
- .equ PLLCFG_PSEL, (0x03<<5) /* PLL Divider */
- .equ PLLSTAT_PLOCK, (1<<10) /* PLL Lock Status */
- .equ PLLCFG_Val, 0x00000024 /* <o1.0..4> MSEL: PLL Multiplier Selection,<o1.5..6> PSEL: PLL Divider Selection */
-
- .equ MEMMAP, 0xE01FC040 /*Memory Mapping Control*/
-
-
- /* Memory Accelerator Module (MAM) definitions*/
- .equ MAM_BASE, 0xE01FC000
- .equ MAMCR_OFS, 0x00
- .equ MAMTIM_OFS, 0x04
- .equ MAMCR_Val, 0x00000002
- .equ MAMTIM_Val, 0x00000004
-
- .equ VICIntEnClr, 0xFFFFF014
- .equ VICIntSelect, 0xFFFFF00C
-/************* Ŀ�����ý��� *************/
-
-
-/* Setup the operating mode & stack.*/
-/* --------------------------------- */
- .global _reset
-_reset:
- .code 32
- .align 0
-
-/************************* PLL_SETUP **********************************/
- ldr r0, =PLL_BASE
- mov r1, #0xAA
- mov r2, #0x55
-
-/* Configure and Enable PLL */
- mov r3, #PLLCFG_Val
- str r3, [r0, #PLLCFG_OFS]
- mov r3, #PLLCON_PLLE
- str r3, [r0, #PLLCON_OFS]
- str r1, [r0, #PLLFEED_OFS]
- str r2, [r0, #PLLFEED_OFS]
-
-/* Wait until PLL Locked */
-PLL_Locked_loop:
- ldr r3, [r0, #PLLSTAT_OFS]
- ands r3, r3, #PLLSTAT_PLOCK
- beq PLL_Locked_loop
-
-/* Switch to PLL Clock */
- mov r3, #(PLLCON_PLLE|PLLCON_PLLC)
- str r3, [r0, #PLLCON_OFS]
- str r1, [r0, #PLLFEED_OFS]
- str R2, [r0, #PLLFEED_OFS]
-/************************* PLL_SETUP **********************************/
-
-/************************ Setup VPBDIV ********************************/
- ldr r0, =VPBDIV
- ldr r1, =VPBDIV_VALUE
- str r1, [r0]
-/************************ Setup VPBDIV ********************************/
-
-/************** Setup MAM **************/
- ldr r0, =MAM_BASE
- mov r1, #MAMTIM_Val
- str r1, [r0, #MAMTIM_OFS]
- mov r1, #MAMCR_Val
- str r1, [r0, #MAMCR_OFS]
-/************** Setup MAM **************/
-
-/************************ setup stack *********************************/
- ldr r0, .undefined_stack_top
- sub r0, r0, #4
- msr CPSR_c, #MODE_UND|I_BIT|F_BIT /* Undefined Instruction Mode */
- mov sp, r0
-
- ldr r0, .abort_stack_top
- sub r0, r0, #4
- msr CPSR_c, #MODE_ABT|I_BIT|F_BIT /* Abort Mode */
- mov sp, r0
-
- ldr r0, .fiq_stack_top
- sub r0, r0, #4
- msr CPSR_c, #MODE_FIQ|I_BIT|F_BIT /* FIQ Mode */
- mov sp, r0
-
- ldr r0, .irq_stack_top
- sub r0, r0, #4
- msr CPSR_c, #MODE_IRQ|I_BIT|F_BIT /* IRQ Mode */
- mov sp, r0
-
- ldr r0, .svc_stack_top
- sub r0, r0, #4
- msr CPSR_c, #MODE_SVC|I_BIT|F_BIT /* Supervisor Mode */
- mov sp, r0
-/************************ setup stack ********************************/
-
- /* copy .data to SRAM */
- ldr r1, =_sidata /* .data start in image */
- ldr r2, =_edata /* .data end in image */
- ldr r3, =_sdata /* sram data start */
-data_loop:
- ldr r0, [r1, #0]
- str r0, [r3]
-
- add r1, r1, #4
- add r3, r3, #4
-
- cmp r3, r2 /* check if data to clear */
- blo data_loop /* loop until done */
-
- /* clear .bss */
- mov r0,#0 /* get a zero */
- ldr r1,=__bss_start /* bss start */
- ldr r2,=__bss_end /* bss end */
-
-bss_loop:
- cmp r1,r2 /* check if data to clear */
- strlo r0,[r1],#4 /* clear 4 bytes */
- blo bss_loop /* loop until done */
-
-
- /* call C++ constructors of global objects */
- ldr r0, =__ctors_start__
- ldr r1, =__ctors_end__
-
-ctor_loop:
- cmp r0, r1
- beq ctor_end
- ldr r2, [r0], #4
- stmfd sp!, {r0-r1}
- mov lr, pc
- bx r2
- ldmfd sp!, {r0-r1}
- b ctor_loop
-ctor_end:
-
- /* enter C code */
- bl main
-
- .align 0
- .undefined_stack_top:
- .word _undefined_stack_top
- .abort_stack_top:
- .word _abort_stack_top
- .fiq_stack_top:
- .word _fiq_stack_top
- .irq_stack_top:
- .word _irq_stack_top
- .svc_stack_top:
- .word _svc_stack_top
-/*********************** END Clear BSS ******************************/
-
-.section .init,"ax"
-.code 32
-.align 0
-.globl _start
-_start:
-
- ldr pc, __start /* reset - _start */
- ldr pc, _undf /* undefined - _undf */
- ldr pc, _swi /* SWI - _swi */
- ldr pc, _pabt /* program abort - _pabt */
- ldr pc, _dabt /* data abort - _dabt */
- .word 0xB8A06F58 /* reserved */
- ldr pc, __IRQ_Handler /* IRQ - read the VIC */
- ldr pc, _fiq /* FIQ - _fiq */
-
-__start:.word _reset
-_undf: .word __undf /* undefined */
-_swi: .word __swi /* SWI */
-_pabt: .word __pabt /* program abort */
-_dabt: .word __dabt /* data abort */
-temp1: .word 0
-__IRQ_Handler: .word IRQ_Handler
-_fiq: .word __fiq /* FIQ */
-
-__undf: b . /* undefined */
-__swi : b .
-__pabt: b . /* program abort */
-__dabt: b . /* data abort */
-__fiq : b . /* FIQ */
-
-/* IRQ��� */
-IRQ_Handler :
- stmfd sp!, {r0-r12,lr} /* ��R0 �C R12��LR�Ĵ���ѹջ */
- bl rt_interrupt_enter /* ֪ͨRT-Thread�����ж�ģʽ */
- bl rt_hw_trap_irq /* ��Ӧ�жϷ������̴��� */
- bl rt_interrupt_leave /* ; ֪ͨRT-ThreadҪ�뿪�ж�ģʽ */
-
- /* ���������rt_thread_switch_interrupt_flag�������ж��е��߳������Ĵ��� */
- ldr r0, =rt_thread_switch_interrupt_flag
- ldr r1, [r0]
- cmp r1, #1
- beq rt_hw_context_switch_interrupt_do /* �������� */
- /* �����ת�ˣ���������� */
- ldmfd sp!, {r0-r12,lr} /* �ָ�ջ */
- subs pc, lr, #4 /* ��IRQ��� */
-
-/*
-* void rt_hw_context_switch_interrupt_do(rt_base_t flag)
-* �жϽ�������������л�
-*/
-rt_hw_context_switch_interrupt_do:
- mov r1, #0 /* clear flag */
- /* ����ж����л���־ */
- str r1, [r0] /* */
-
- ldmfd sp!, {r0-r12,lr}/* reload saved registers */
- /* �Ȼָ����ж��̵߳������� */
- stmfd sp!, {r0-r3} /* save r0-r3 */
- /* ��R0 �C R3ѹջ����Ϊ������õ� */
- mov r1, sp /* �Ѵ˴���ջֵ���浽R1 */
- add sp, sp, #16 /* restore sp */
- /* �ָ�IRQ��ջ�����������IRQģʽ */
- sub r2, lr, #4 /* save old task's pc to r2 */
- /* �����л����̵߳�PC��R2 */
-
- mrs r3, spsr /* disable interrupt �����ж�ǰ��CPSR��R3�Ĵ��� */
- /* ���SPSR�Ĵ���ֵ */
- orr r0, r3, #I_BIT|F_BIT
- msr spsr_c, r0 /* �ر�SPSR�е�IRQ/FIQ�ж� */
-
- ldr r0, =.+8 /* �ѵ�ǰ��ַ+8���뵽R0�Ĵ����� switch to interrupted task's stack */
- movs pc, r0 /* �˳�IRQģʽ������SPSR�����óɹ��ж�ģʽ */
- /* ���Դ�IRQ���غ��жϲ�û�д�
- ; R0�Ĵ����е�λ��ʵ�ʾ�����һ��ָ�
- ; ��PC����������
- ; ��ʱ
- ; ģʽ�Ѿ������ж�ǰ��SVCģʽ��
- ; SP�Ĵ���Ҳ��SVCģʽ�µ�ջ�Ĵ���
- ; R1����IRQģʽ�µ�ջָ��
- ; R2�����л����̵߳�PC
- ; R3�����л����̵߳�CPSR */
- stmfd sp!, {r2} /* push old task's pc */
- /* ������������PC */
- stmfd sp!, {r4-r12,lr}/* push old task's lr,r12-r4 */
- /* ����R4 �C R12��LR�Ĵ��� */
- mov r4, r1 /* Special optimised code below */
- /* R1������ѹջR0 �C R3����ջλ�� */
- mov r5, r3 /* R3�л����̵߳�CPSR */
- ldmfd r4!, {r0-r3} /* �ָ�R0 �C R3 */
- stmfd sp!, {r0-r3} /* push old task's r3-r0 */
- /* R0 �C R3ѹջ���л����߳� */
- stmfd sp!, {r5} /* push old task's psr */
- /* �л����߳�CPSRѹջ */
- mrs r4, spsr
- stmfd sp!, {r4} /* push old task's spsr */
- /* �л����߳�SPSRѹջ */
-
- ldr r4, =rt_interrupt_from_thread
- ldr r5, [r4]
- str sp, [r5] /* store sp in preempted tasks's TCB */
- /* �����л����̵߳�SPָ�� */
-
- ldr r6, =rt_interrupt_to_thread
- ldr r6, [r6]
- ldr sp, [r6] /* get new task's stack pointer */
- /* ����л����̵߳�ջ */
-
- ldmfd sp!, {r4} /* pop new task's spsr */
- /* �ָ�SPSR */
- msr SPSR_cxsf, r4
- ldmfd sp!, {r4} /* pop new task's psr */
- /* �ָ�CPSR */
- msr CPSR_cxsf, r4
-
- ldmfd sp!, {r0-r12,lr,pc} /* pop new task's r0-r12,lr & pc */
- /* �ָ�R0 �C R12��LR��PC�Ĵ��� */
-
-/* ������ܹ��� */
-#if defined(CODE_PROTECTION)
-.org 0x01FC
-.word 0x87654321
-#endif
-
+ .extern main /* �����ⲿC��� */ + + .extern rt_interrupt_enter + .extern rt_interrupt_leave + .extern rt_thread_switch_interrupt_flag + .extern rt_interrupt_from_thread + .extern rt_interrupt_to_thread + .extern rt_hw_trap_irq + + .global start + .global endless_loop + .global rt_hw_context_switch_interrupt_do + + /* Standard definitions of Mode bits and Interrupt (I & F) flags in PSRs */ + .set MODE_USR, 0x10 /* User Mode */ + .set MODE_FIQ, 0x11 /* FIQ Mode */ + .set MODE_IRQ, 0x12 /* IRQ Mode */ + .set MODE_SVC, 0x13 /* Supervisor Mode */ + .set MODE_ABT, 0x17 /* Abort Mode */ + .set MODE_UND, 0x1B /* Undefined Mode */ + .set MODE_SYS, 0x1F /* System Mode */ + + .equ I_BIT, 0x80 /* when I bit is set, IRQ is disabled */ + .equ F_BIT, 0x40 /* when F bit is set, FIQ is disabled */ + .equ I_Bit, 0x80 /* when I bit is set, IRQ is disabled */ + .equ F_Bit, 0x40 /* when F bit is set, FIQ is disabled */ + + /* VPBDIV definitions*/ + .equ VPBDIV, 0xE01FC100 + .set VPBDIV_VALUE, 0x00000000 + + /* Phase Locked Loop (PLL) definitions*/ + .equ PLL_BASE, 0xE01FC080 /* PLL Base Address */ + .equ PLLCON_OFS, 0x00 /* PLL Control Offset */ + .equ PLLCFG_OFS, 0x04 /* PLL Configuration Offset */ + .equ PLLSTAT_OFS, 0x08 /* PLL Status Offset */ + .equ PLLFEED_OFS, 0x0C /* PLL Feed Offset */ + .equ PLLCON_PLLE, (1<<0) /* PLL Enable */ + .equ PLLCON_PLLC, (1<<1) /* PLL Connect */ + .equ PLLCFG_MSEL, (0x1F<<0) /* PLL Multiplier */ + .equ PLLCFG_PSEL, (0x03<<5) /* PLL Divider */ + .equ PLLSTAT_PLOCK, (1<<10) /* PLL Lock Status */ + .equ PLLCFG_Val, 0x00000024 /* <o1.0..4> MSEL: PLL Multiplier Selection,<o1.5..6> PSEL: PLL Divider Selection */ + + .equ MEMMAP, 0xE01FC040 /*Memory Mapping Control*/ + + + /* Memory Accelerator Module (MAM) definitions*/ + .equ MAM_BASE, 0xE01FC000 + .equ MAMCR_OFS, 0x00 + .equ MAMTIM_OFS, 0x04 + .equ MAMCR_Val, 0x00000002 + .equ MAMTIM_Val, 0x00000004 + + .equ VICIntEnClr, 0xFFFFF014 + .equ VICIntSelect, 0xFFFFF00C +/************* Ŀ�����ý��� *************/ + + +/* Setup the operating mode & stack.*/ +/* --------------------------------- */ + .global _reset +_reset: + .code 32 + .align 0 + +/************************* PLL_SETUP **********************************/ + ldr r0, =PLL_BASE + mov r1, #0xAA + mov r2, #0x55 + +/* Configure and Enable PLL */ + mov r3, #PLLCFG_Val + str r3, [r0, #PLLCFG_OFS] + mov r3, #PLLCON_PLLE + str r3, [r0, #PLLCON_OFS] + str r1, [r0, #PLLFEED_OFS] + str r2, [r0, #PLLFEED_OFS] + +/* Wait until PLL Locked */ +PLL_Locked_loop: + ldr r3, [r0, #PLLSTAT_OFS] + ands r3, r3, #PLLSTAT_PLOCK + beq PLL_Locked_loop + +/* Switch to PLL Clock */ + mov r3, #(PLLCON_PLLE|PLLCON_PLLC) + str r3, [r0, #PLLCON_OFS] + str r1, [r0, #PLLFEED_OFS] + str R2, [r0, #PLLFEED_OFS] +/************************* PLL_SETUP **********************************/ + +/************************ Setup VPBDIV ********************************/ + ldr r0, =VPBDIV + ldr r1, =VPBDIV_VALUE + str r1, [r0] +/************************ Setup VPBDIV ********************************/ + +/************** Setup MAM **************/ + ldr r0, =MAM_BASE + mov r1, #MAMTIM_Val + str r1, [r0, #MAMTIM_OFS] + mov r1, #MAMCR_Val + str r1, [r0, #MAMCR_OFS] +/************** Setup MAM **************/ + +/************************ setup stack *********************************/ + ldr r0, .undefined_stack_top + sub r0, r0, #4 + msr CPSR_c, #MODE_UND|I_BIT|F_BIT /* Undefined Instruction Mode */ + mov sp, r0 + + ldr r0, .abort_stack_top + sub r0, r0, #4 + msr CPSR_c, #MODE_ABT|I_BIT|F_BIT /* Abort Mode */ + mov sp, r0 + + ldr r0, .fiq_stack_top + sub r0, r0, #4 + msr CPSR_c, #MODE_FIQ|I_BIT|F_BIT /* FIQ Mode */ + mov sp, r0 + + ldr r0, .irq_stack_top + sub r0, r0, #4 + msr CPSR_c, #MODE_IRQ|I_BIT|F_BIT /* IRQ Mode */ + mov sp, r0 + + ldr r0, .svc_stack_top + sub r0, r0, #4 + msr CPSR_c, #MODE_SVC|I_BIT|F_BIT /* Supervisor Mode */ + mov sp, r0 +/************************ setup stack ********************************/ + + /* copy .data to SRAM */ + ldr r1, =_sidata /* .data start in image */ + ldr r2, =_edata /* .data end in image */ + ldr r3, =_sdata /* sram data start */ +data_loop: + ldr r0, [r1, #0] + str r0, [r3] + + add r1, r1, #4 + add r3, r3, #4 + + cmp r3, r2 /* check if data to clear */ + blo data_loop /* loop until done */ + + /* clear .bss */ + mov r0,#0 /* get a zero */ + ldr r1,=__bss_start /* bss start */ + ldr r2,=__bss_end /* bss end */ + +bss_loop: + cmp r1,r2 /* check if data to clear */ + strlo r0,[r1],#4 /* clear 4 bytes */ + blo bss_loop /* loop until done */ + + + /* call C++ constructors of global objects */ + ldr r0, =__ctors_start__ + ldr r1, =__ctors_end__ + +ctor_loop: + cmp r0, r1 + beq ctor_end + ldr r2, [r0], #4 + stmfd sp!, {r0-r1} + mov lr, pc + bx r2 + ldmfd sp!, {r0-r1} + b ctor_loop +ctor_end: + + /* enter C code */ + bl main + + .align 0 + .undefined_stack_top: + .word _undefined_stack_top + .abort_stack_top: + .word _abort_stack_top + .fiq_stack_top: + .word _fiq_stack_top + .irq_stack_top: + .word _irq_stack_top + .svc_stack_top: + .word _svc_stack_top +/*********************** END Clear BSS ******************************/ + +.section .init,"ax" +.code 32 +.align 0 +.globl _start +_start: + + ldr pc, __start /* reset - _start */ + ldr pc, _undf /* undefined - _undf */ + ldr pc, _swi /* SWI - _swi */ + ldr pc, _pabt /* program abort - _pabt */ + ldr pc, _dabt /* data abort - _dabt */ + .word 0xB8A06F58 /* reserved */ + ldr pc, __IRQ_Handler /* IRQ - read the VIC */ + ldr pc, _fiq /* FIQ - _fiq */ + +__start:.word _reset +_undf: .word __undf /* undefined */ +_swi: .word __swi /* SWI */ +_pabt: .word __pabt /* program abort */ +_dabt: .word __dabt /* data abort */ +temp1: .word 0 +__IRQ_Handler: .word IRQ_Handler +_fiq: .word __fiq /* FIQ */ + +__undf: b . /* undefined */ +__swi : b . +__pabt: b . /* program abort */ +__dabt: b . /* data abort */ +__fiq : b . /* FIQ */ + +/* IRQ��� */ +IRQ_Handler : + stmfd sp!, {r0-r12,lr} /* ��R0 �C R12��LR�Ĵ���ѹջ */ + bl rt_interrupt_enter /* ֪ͨRT-Thread�����ж�ģʽ */ + bl rt_hw_trap_irq /* ��Ӧ�жϷ������̴��� */ + bl rt_interrupt_leave /* ; ֪ͨRT-ThreadҪ�뿪�ж�ģʽ */ + + /* ���������rt_thread_switch_interrupt_flag�������ж��е��߳������Ĵ��� */ + ldr r0, =rt_thread_switch_interrupt_flag + ldr r1, [r0] + cmp r1, #1 + beq rt_hw_context_switch_interrupt_do /* �ж����л����� */ + /* �����ת�ˣ���������� */ + ldmfd sp!, {r0-r12,lr} /* �ָ�ջ */ + subs pc, lr, #4 /* ��IRQ�з��� */ + +/* +* void rt_hw_context_switch_interrupt_do(rt_base_t flag) +* �жϽ�������������л� +*/ +rt_hw_context_switch_interrupt_do: + mov r1, #0 /* clear flag */ + /* ����ж����л���־ */ + str r1, [r0] /* */ + + ldmfd sp!, {r0-r12,lr}/* reload saved registers */ + /* �Ȼָ����ж��̵߳������� */ + stmfd sp!, {r0-r3} /* save r0-r3 */ + /* ��R0 �C R3ѹջ����Ϊ������õ� */ + mov r1, sp /* �Ѵ˴���ջֵ���浽R1 */ + add sp, sp, #16 /* restore sp */ + /* �ָ�IRQ��ջ�����������IRQģʽ */ + sub r2, lr, #4 /* save old task's pc to r2 */ + /* �����л����̵߳�PC��R2 */ + + mrs r3, spsr /* disable interrupt �����ж�ǰ��CPSR��R3�Ĵ��� */ + /* ���SPSR�Ĵ���ֵ */ + orr r0, r3, #I_BIT|F_BIT + msr spsr_c, r0 /* �ر�SPSR�е�IRQ/FIQ�ж� */ + + ldr r0, =.+8 /* �ѵ�ǰ��ַ+8���뵽R0�Ĵ����� switch to interrupted task's stack */ + movs pc, r0 /* �˳�IRQģʽ������SPSR�����óɹ��ж�ģʽ */ + /* ���Դ�IRQ���غ��жϲ�û�д� + ; R0�Ĵ����е�λ��ʵ�ʾ�����һ��ָ� + ; ��PC���������� + ; ��ʱ + ; ģʽ�Ѿ������ж�ǰ��SVCģʽ�� + ; SP�Ĵ���Ҳ��SVCģʽ�µ�ջ�Ĵ��� + ; R1����IRQģʽ�µ�ջָ�� + ; R2�����л����̵߳�PC + ; R3�����л����̵߳�CPSR */ + stmfd sp!, {r2} /* push old task's pc */ + /* �����л��������PC */ + stmfd sp!, {r4-r12,lr}/* push old task's lr,r12-r4 */ + /* ����R4 �C R12��LR�Ĵ��� */ + mov r4, r1 /* Special optimised code below */ + /* R1������ѹջR0 �C R3����ջλ�� */ + mov r5, r3 /* R3�л����̵߳�CPSR */ + ldmfd r4!, {r0-r3} /* �ָ�R0 �C R3 */ + stmfd sp!, {r0-r3} /* push old task's r3-r0 */ + /* R0 �C R3ѹջ���л����߳� */ + stmfd sp!, {r5} /* push old task's psr */ + /* �л����߳�CPSRѹջ */ + mrs r4, spsr + stmfd sp!, {r4} /* push old task's spsr */ + /* �л����߳�SPSRѹջ */ + + ldr r4, =rt_interrupt_from_thread + ldr r5, [r4] + str sp, [r5] /* store sp in preempted tasks's TCB */ + /* �����л����̵߳�SPָ�� */ + + ldr r6, =rt_interrupt_to_thread + ldr r6, [r6] + ldr sp, [r6] /* get new task's stack pointer */ + /* ����л����̵߳�ջ */ + + ldmfd sp!, {r4} /* pop new task's spsr */ + /* �ָ�SPSR */ + msr SPSR_cxsf, r4 + ldmfd sp!, {r4} /* pop new task's psr */ + /* �ָ�CPSR */ + msr CPSR_cxsf, r4 + + ldmfd sp!, {r0-r12,lr,pc} /* pop new task's r0-r12,lr & pc */ + /* �ָ�R0 �C R12��LR��PC�Ĵ��� */ + +/* ������ܹ��� */ +#if defined(CODE_PROTECTION) +.org 0x01FC +.word 0x87654321 +#endif + diff --git a/libcpu/arm/lpc24xx/LPC24xx.h b/libcpu/arm/lpc24xx/LPC24xx.h index 01cbeec669..7c70fd1aa5 100644 --- a/libcpu/arm/lpc24xx/LPC24xx.h +++ b/libcpu/arm/lpc24xx/LPC24xx.h @@ -1,1201 +1,1201 @@ -/*
- * File : LPC2478.h
- * This file is part of RT-Thread RTOS
- * COPYRIGHT (C) 2006, RT-Thread Develop Team
- *
- * The license and distribution terms for this file may be
- * found in the file LICENSE in this distribution or at
- * http://openlab.rt-thread.com/license/LICENSE
- *
- * Change Logs:
- * Date Author Notes
- * 2008-12-11 xuxinming first version
- */
-
-#ifndef __LPC24xx_H
-#define __LPC24xx_H
-
-#ifdef __cplusplus
-extern "C" {
-#endif
-
-#define USERMODE 0x10
-#define FIQMODE 0x11
-#define IRQMODE 0x12
-#define SVCMODE 0x13
-#define ABORTMODE 0x17
-#define UNDEFMODE 0x1b
-#define MODEMASK 0x1f
-#define NOINT 0xc0
-
-#define MCLK (72000000)
-
-/* Vectored Interrupt Controller (VIC) */
-#define VIC_BASE_ADDR 0xFFFFF000
-#define VICIRQStatus (*(volatile unsigned long *)(VIC_BASE_ADDR + 0x000))
-#define VICFIQStatus (*(volatile unsigned long *)(VIC_BASE_ADDR + 0x004))
-#define VICRawIntr (*(volatile unsigned long *)(VIC_BASE_ADDR + 0x008))
-#define VICIntSelect (*(volatile unsigned long *)(VIC_BASE_ADDR + 0x00C))
-#define VICIntEnable (*(volatile unsigned long *)(VIC_BASE_ADDR + 0x010))
-#define VICIntEnClr (*(volatile unsigned long *)(VIC_BASE_ADDR + 0x014))
-#define VICSoftInt (*(volatile unsigned long *)(VIC_BASE_ADDR + 0x018))
-#define VICSoftIntClr (*(volatile unsigned long *)(VIC_BASE_ADDR + 0x01C))
-#define VICProtection (*(volatile unsigned long *)(VIC_BASE_ADDR + 0x020))
-#define VICSWPrioMask (*(volatile unsigned long *)(VIC_BASE_ADDR + 0x024))
-
-#define VICVectAddr0 (*(volatile unsigned long *)(VIC_BASE_ADDR + 0x100))
-#define VICVectAddr1 (*(volatile unsigned long *)(VIC_BASE_ADDR + 0x104))
-#define VICVectAddr2 (*(volatile unsigned long *)(VIC_BASE_ADDR + 0x108))
-#define VICVectAddr3 (*(volatile unsigned long *)(VIC_BASE_ADDR + 0x10C))
-#define VICVectAddr4 (*(volatile unsigned long *)(VIC_BASE_ADDR + 0x110))
-#define VICVectAddr5 (*(volatile unsigned long *)(VIC_BASE_ADDR + 0x114))
-#define VICVectAddr6 (*(volatile unsigned long *)(VIC_BASE_ADDR + 0x118))
-#define VICVectAddr7 (*(volatile unsigned long *)(VIC_BASE_ADDR + 0x11C))
-#define VICVectAddr8 (*(volatile unsigned long *)(VIC_BASE_ADDR + 0x120))
-#define VICVectAddr9 (*(volatile unsigned long *)(VIC_BASE_ADDR + 0x124))
-#define VICVectAddr10 (*(volatile unsigned long *)(VIC_BASE_ADDR + 0x128))
-#define VICVectAddr11 (*(volatile unsigned long *)(VIC_BASE_ADDR + 0x12C))
-#define VICVectAddr12 (*(volatile unsigned long *)(VIC_BASE_ADDR + 0x130))
-#define VICVectAddr13 (*(volatile unsigned long *)(VIC_BASE_ADDR + 0x134))
-#define VICVectAddr14 (*(volatile unsigned long *)(VIC_BASE_ADDR + 0x138))
-#define VICVectAddr15 (*(volatile unsigned long *)(VIC_BASE_ADDR + 0x13C))
-#define VICVectAddr16 (*(volatile unsigned long *)(VIC_BASE_ADDR + 0x140))
-#define VICVectAddr17 (*(volatile unsigned long *)(VIC_BASE_ADDR + 0x144))
-#define VICVectAddr18 (*(volatile unsigned long *)(VIC_BASE_ADDR + 0x148))
-#define VICVectAddr19 (*(volatile unsigned long *)(VIC_BASE_ADDR + 0x14C))
-#define VICVectAddr20 (*(volatile unsigned long *)(VIC_BASE_ADDR + 0x150))
-#define VICVectAddr21 (*(volatile unsigned long *)(VIC_BASE_ADDR + 0x154))
-#define VICVectAddr22 (*(volatile unsigned long *)(VIC_BASE_ADDR + 0x158))
-#define VICVectAddr23 (*(volatile unsigned long *)(VIC_BASE_ADDR + 0x15C))
-#define VICVectAddr24 (*(volatile unsigned long *)(VIC_BASE_ADDR + 0x160))
-#define VICVectAddr25 (*(volatile unsigned long *)(VIC_BASE_ADDR + 0x164))
-#define VICVectAddr26 (*(volatile unsigned long *)(VIC_BASE_ADDR + 0x168))
-#define VICVectAddr27 (*(volatile unsigned long *)(VIC_BASE_ADDR + 0x16C))
-#define VICVectAddr28 (*(volatile unsigned long *)(VIC_BASE_ADDR + 0x170))
-#define VICVectAddr29 (*(volatile unsigned long *)(VIC_BASE_ADDR + 0x174))
-#define VICVectAddr30 (*(volatile unsigned long *)(VIC_BASE_ADDR + 0x178))
-#define VICVectAddr31 (*(volatile unsigned long *)(VIC_BASE_ADDR + 0x17C))
-
-/* The name convention below is from previous LPC2000 family MCUs, in LPC23xx/24xx,
-these registers are known as "VICVectPriority(x)". */
-#define VICVectCntl0 (*(volatile unsigned long *)(VIC_BASE_ADDR + 0x200))
-#define VICVectCntl1 (*(volatile unsigned long *)(VIC_BASE_ADDR + 0x204))
-#define VICVectCntl2 (*(volatile unsigned long *)(VIC_BASE_ADDR + 0x208))
-#define VICVectCntl3 (*(volatile unsigned long *)(VIC_BASE_ADDR + 0x20C))
-#define VICVectCntl4 (*(volatile unsigned long *)(VIC_BASE_ADDR + 0x210))
-#define VICVectCntl5 (*(volatile unsigned long *)(VIC_BASE_ADDR + 0x214))
-#define VICVectCntl6 (*(volatile unsigned long *)(VIC_BASE_ADDR + 0x218))
-#define VICVectCntl7 (*(volatile unsigned long *)(VIC_BASE_ADDR + 0x21C))
-#define VICVectCntl8 (*(volatile unsigned long *)(VIC_BASE_ADDR + 0x220))
-#define VICVectCntl9 (*(volatile unsigned long *)(VIC_BASE_ADDR + 0x224))
-#define VICVectCntl10 (*(volatile unsigned long *)(VIC_BASE_ADDR + 0x228))
-#define VICVectCntl11 (*(volatile unsigned long *)(VIC_BASE_ADDR + 0x22C))
-#define VICVectCntl12 (*(volatile unsigned long *)(VIC_BASE_ADDR + 0x230))
-#define VICVectCntl13 (*(volatile unsigned long *)(VIC_BASE_ADDR + 0x234))
-#define VICVectCntl14 (*(volatile unsigned long *)(VIC_BASE_ADDR + 0x238))
-#define VICVectCntl15 (*(volatile unsigned long *)(VIC_BASE_ADDR + 0x23C))
-#define VICVectCntl16 (*(volatile unsigned long *)(VIC_BASE_ADDR + 0x240))
-#define VICVectCntl17 (*(volatile unsigned long *)(VIC_BASE_ADDR + 0x244))
-#define VICVectCntl18 (*(volatile unsigned long *)(VIC_BASE_ADDR + 0x248))
-#define VICVectCntl19 (*(volatile unsigned long *)(VIC_BASE_ADDR + 0x24C))
-#define VICVectCntl20 (*(volatile unsigned long *)(VIC_BASE_ADDR + 0x250))
-#define VICVectCntl21 (*(volatile unsigned long *)(VIC_BASE_ADDR + 0x254))
-#define VICVectCntl22 (*(volatile unsigned long *)(VIC_BASE_ADDR + 0x258))
-#define VICVectCntl23 (*(volatile unsigned long *)(VIC_BASE_ADDR + 0x25C))
-#define VICVectCntl24 (*(volatile unsigned long *)(VIC_BASE_ADDR + 0x260))
-#define VICVectCntl25 (*(volatile unsigned long *)(VIC_BASE_ADDR + 0x264))
-#define VICVectCntl26 (*(volatile unsigned long *)(VIC_BASE_ADDR + 0x268))
-#define VICVectCntl27 (*(volatile unsigned long *)(VIC_BASE_ADDR + 0x26C))
-#define VICVectCntl28 (*(volatile unsigned long *)(VIC_BASE_ADDR + 0x270))
-#define VICVectCntl29 (*(volatile unsigned long *)(VIC_BASE_ADDR + 0x274))
-#define VICVectCntl30 (*(volatile unsigned long *)(VIC_BASE_ADDR + 0x278))
-#define VICVectCntl31 (*(volatile unsigned long *)(VIC_BASE_ADDR + 0x27C))
-
-#define VICVectAddr (*(volatile unsigned long *)(VIC_BASE_ADDR + 0xF00))
-
-
-/* Pin Connect Block */
-#define PINSEL_BASE_ADDR 0xE002C000
-#define PINSEL0 (*(volatile unsigned long *)(PINSEL_BASE_ADDR + 0x00))
-#define PINSEL1 (*(volatile unsigned long *)(PINSEL_BASE_ADDR + 0x04))
-#define PINSEL2 (*(volatile unsigned long *)(PINSEL_BASE_ADDR + 0x08))
-#define PINSEL3 (*(volatile unsigned long *)(PINSEL_BASE_ADDR + 0x0C))
-#define PINSEL4 (*(volatile unsigned long *)(PINSEL_BASE_ADDR + 0x10))
-#define PINSEL5 (*(volatile unsigned long *)(PINSEL_BASE_ADDR + 0x14))
-#define PINSEL6 (*(volatile unsigned long *)(PINSEL_BASE_ADDR + 0x18))
-#define PINSEL7 (*(volatile unsigned long *)(PINSEL_BASE_ADDR + 0x1C))
-#define PINSEL8 (*(volatile unsigned long *)(PINSEL_BASE_ADDR + 0x20))
-#define PINSEL9 (*(volatile unsigned long *)(PINSEL_BASE_ADDR + 0x24))
-#define PINSEL10 (*(volatile unsigned long *)(PINSEL_BASE_ADDR + 0x28))
-#define PINSEL11 (*(volatile unsigned long *)(PINSEL_BASE_ADDR + 0x2C))
-
-#define PINMODE0 (*(volatile unsigned long *)(PINSEL_BASE_ADDR + 0x40))
-#define PINMODE1 (*(volatile unsigned long *)(PINSEL_BASE_ADDR + 0x44))
-#define PINMODE2 (*(volatile unsigned long *)(PINSEL_BASE_ADDR + 0x48))
-#define PINMODE3 (*(volatile unsigned long *)(PINSEL_BASE_ADDR + 0x4C))
-#define PINMODE4 (*(volatile unsigned long *)(PINSEL_BASE_ADDR + 0x50))
-#define PINMODE5 (*(volatile unsigned long *)(PINSEL_BASE_ADDR + 0x54))
-#define PINMODE6 (*(volatile unsigned long *)(PINSEL_BASE_ADDR + 0x58))
-#define PINMODE7 (*(volatile unsigned long *)(PINSEL_BASE_ADDR + 0x5C))
-#define PINMODE8 (*(volatile unsigned long *)(PINSEL_BASE_ADDR + 0x60))
-#define PINMODE9 (*(volatile unsigned long *)(PINSEL_BASE_ADDR + 0x64))
-
-/* General Purpose Input/Output (GPIO) */
-#define GPIO_BASE_ADDR 0xE0028000
-#define IOPIN0 (*(volatile unsigned long *)(GPIO_BASE_ADDR + 0x00))
-#define IOSET0 (*(volatile unsigned long *)(GPIO_BASE_ADDR + 0x04))
-#define IODIR0 (*(volatile unsigned long *)(GPIO_BASE_ADDR + 0x08))
-#define IOCLR0 (*(volatile unsigned long *)(GPIO_BASE_ADDR + 0x0C))
-#define IOPIN1 (*(volatile unsigned long *)(GPIO_BASE_ADDR + 0x10))
-#define IOSET1 (*(volatile unsigned long *)(GPIO_BASE_ADDR + 0x14))
-#define IODIR1 (*(volatile unsigned long *)(GPIO_BASE_ADDR + 0x18))
-#define IOCLR1 (*(volatile unsigned long *)(GPIO_BASE_ADDR + 0x1C))
-
-/* GPIO Interrupt Registers */
-#define IO0_INT_EN_R (*(volatile unsigned long *)(GPIO_BASE_ADDR + 0x90))
-#define IO0_INT_EN_F (*(volatile unsigned long *)(GPIO_BASE_ADDR + 0x94))
-#define IO0_INT_STAT_R (*(volatile unsigned long *)(GPIO_BASE_ADDR + 0x84))
-#define IO0_INT_STAT_F (*(volatile unsigned long *)(GPIO_BASE_ADDR + 0x88))
-#define IO0_INT_CLR (*(volatile unsigned long *)(GPIO_BASE_ADDR + 0x8C))
-
-#define IO2_INT_EN_R (*(volatile unsigned long *)(GPIO_BASE_ADDR + 0xB0))
-#define IO2_INT_EN_F (*(volatile unsigned long *)(GPIO_BASE_ADDR + 0xB4))
-#define IO2_INT_STAT_R (*(volatile unsigned long *)(GPIO_BASE_ADDR + 0xA4))
-#define IO2_INT_STAT_F (*(volatile unsigned long *)(GPIO_BASE_ADDR + 0xA8))
-#define IO2_INT_CLR (*(volatile unsigned long *)(GPIO_BASE_ADDR + 0xAC))
-
-#define IO_INT_STAT (*(volatile unsigned long *)(GPIO_BASE_ADDR + 0x80))
-
-#define PARTCFG_BASE_ADDR 0x3FFF8000
-#define PARTCFG (*(volatile unsigned long *)(PARTCFG_BASE_ADDR + 0x00))
-
-/* Fast I/O setup */
-#define FIO_BASE_ADDR 0x3FFFC000
-#define FIO0DIR (*(volatile unsigned long *)(FIO_BASE_ADDR + 0x00))
-#define FIO0MASK (*(volatile unsigned long *)(FIO_BASE_ADDR + 0x10))
-#define FIO0PIN (*(volatile unsigned long *)(FIO_BASE_ADDR + 0x14))
-#define FIO0SET (*(volatile unsigned long *)(FIO_BASE_ADDR + 0x18))
-#define FIO0CLR (*(volatile unsigned long *)(FIO_BASE_ADDR + 0x1C))
-
-#define FIO1DIR (*(volatile unsigned long *)(FIO_BASE_ADDR + 0x20))
-#define FIO1MASK (*(volatile unsigned long *)(FIO_BASE_ADDR + 0x30))
-#define FIO1PIN (*(volatile unsigned long *)(FIO_BASE_ADDR + 0x34))
-#define FIO1SET (*(volatile unsigned long *)(FIO_BASE_ADDR + 0x38))
-#define FIO1CLR (*(volatile unsigned long *)(FIO_BASE_ADDR + 0x3C))
-
-#define FIO2DIR (*(volatile unsigned long *)(FIO_BASE_ADDR + 0x40))
-#define FIO2MASK (*(volatile unsigned long *)(FIO_BASE_ADDR + 0x50))
-#define FIO2PIN (*(volatile unsigned long *)(FIO_BASE_ADDR + 0x54))
-#define FIO2SET (*(volatile unsigned long *)(FIO_BASE_ADDR + 0x58))
-#define FIO2CLR (*(volatile unsigned long *)(FIO_BASE_ADDR + 0x5C))
-
-#define FIO3DIR (*(volatile unsigned long *)(FIO_BASE_ADDR + 0x60))
-#define FIO3MASK (*(volatile unsigned long *)(FIO_BASE_ADDR + 0x70))
-#define FIO3PIN (*(volatile unsigned long *)(FIO_BASE_ADDR + 0x74))
-#define FIO3SET (*(volatile unsigned long *)(FIO_BASE_ADDR + 0x78))
-#define FIO3CLR (*(volatile unsigned long *)(FIO_BASE_ADDR + 0x7C))
-
-#define FIO4DIR (*(volatile unsigned long *)(FIO_BASE_ADDR + 0x80))
-#define FIO4MASK (*(volatile unsigned long *)(FIO_BASE_ADDR + 0x90))
-#define FIO4PIN (*(volatile unsigned long *)(FIO_BASE_ADDR + 0x94))
-#define FIO4SET (*(volatile unsigned long *)(FIO_BASE_ADDR + 0x98))
-#define FIO4CLR (*(volatile unsigned long *)(FIO_BASE_ADDR + 0x9C))
-
-/* FIOs can be accessed through WORD, HALF-WORD or BYTE. */
-#define FIO0DIR0 (*(volatile unsigned char *)(FIO_BASE_ADDR + 0x00))
-#define FIO1DIR0 (*(volatile unsigned char *)(FIO_BASE_ADDR + 0x20))
-#define FIO2DIR0 (*(volatile unsigned char *)(FIO_BASE_ADDR + 0x40))
-#define FIO3DIR0 (*(volatile unsigned char *)(FIO_BASE_ADDR + 0x60))
-#define FIO4DIR0 (*(volatile unsigned char *)(FIO_BASE_ADDR + 0x80))
-
-#define FIO0DIR1 (*(volatile unsigned char *)(FIO_BASE_ADDR + 0x01))
-#define FIO1DIR1 (*(volatile unsigned char *)(FIO_BASE_ADDR + 0x21))
-#define FIO2DIR1 (*(volatile unsigned char *)(FIO_BASE_ADDR + 0x41))
-#define FIO3DIR1 (*(volatile unsigned char *)(FIO_BASE_ADDR + 0x61))
-#define FIO4DIR1 (*(volatile unsigned char *)(FIO_BASE_ADDR + 0x81))
-
-#define FIO0DIR2 (*(volatile unsigned char *)(FIO_BASE_ADDR + 0x02))
-#define FIO1DIR2 (*(volatile unsigned char *)(FIO_BASE_ADDR + 0x22))
-#define FIO2DIR2 (*(volatile unsigned char *)(FIO_BASE_ADDR + 0x42))
-#define FIO3DIR2 (*(volatile unsigned char *)(FIO_BASE_ADDR + 0x62))
-#define FIO4DIR2 (*(volatile unsigned char *)(FIO_BASE_ADDR + 0x82))
-
-#define FIO0DIR3 (*(volatile unsigned char *)(FIO_BASE_ADDR + 0x03))
-#define FIO1DIR3 (*(volatile unsigned char *)(FIO_BASE_ADDR + 0x23))
-#define FIO2DIR3 (*(volatile unsigned char *)(FIO_BASE_ADDR + 0x43))
-#define FIO3DIR3 (*(volatile unsigned char *)(FIO_BASE_ADDR + 0x63))
-#define FIO4DIR3 (*(volatile unsigned char *)(FIO_BASE_ADDR + 0x83))
-
-#define FIO0DIRL (*(volatile unsigned short *)(FIO_BASE_ADDR + 0x00))
-#define FIO1DIRL (*(volatile unsigned short *)(FIO_BASE_ADDR + 0x20))
-#define FIO2DIRL (*(volatile unsigned short *)(FIO_BASE_ADDR + 0x40))
-#define FIO3DIRL (*(volatile unsigned short *)(FIO_BASE_ADDR + 0x60))
-#define FIO4DIRL (*(volatile unsigned short *)(FIO_BASE_ADDR + 0x80))
-
-#define FIO0DIRU (*(volatile unsigned short *)(FIO_BASE_ADDR + 0x02))
-#define FIO1DIRU (*(volatile unsigned short *)(FIO_BASE_ADDR + 0x22))
-#define FIO2DIRU (*(volatile unsigned short *)(FIO_BASE_ADDR + 0x42))
-#define FIO3DIRU (*(volatile unsigned short *)(FIO_BASE_ADDR + 0x62))
-#define FIO4DIRU (*(volatile unsigned short *)(FIO_BASE_ADDR + 0x82))
-
-#define FIO0MASK0 (*(volatile unsigned char *)(FIO_BASE_ADDR + 0x10))
-#define FIO1MASK0 (*(volatile unsigned char *)(FIO_BASE_ADDR + 0x30))
-#define FIO2MASK0 (*(volatile unsigned char *)(FIO_BASE_ADDR + 0x50))
-#define FIO3MASK0 (*(volatile unsigned char *)(FIO_BASE_ADDR + 0x70))
-#define FIO4MASK0 (*(volatile unsigned char *)(FIO_BASE_ADDR + 0x90))
-
-#define FIO0MASK1 (*(volatile unsigned char *)(FIO_BASE_ADDR + 0x11))
-#define FIO1MASK1 (*(volatile unsigned char *)(FIO_BASE_ADDR + 0x21))
-#define FIO2MASK1 (*(volatile unsigned char *)(FIO_BASE_ADDR + 0x51))
-#define FIO3MASK1 (*(volatile unsigned char *)(FIO_BASE_ADDR + 0x71))
-#define FIO4MASK1 (*(volatile unsigned char *)(FIO_BASE_ADDR + 0x91))
-
-#define FIO0MASK2 (*(volatile unsigned char *)(FIO_BASE_ADDR + 0x12))
-#define FIO1MASK2 (*(volatile unsigned char *)(FIO_BASE_ADDR + 0x32))
-#define FIO2MASK2 (*(volatile unsigned char *)(FIO_BASE_ADDR + 0x52))
-#define FIO3MASK2 (*(volatile unsigned char *)(FIO_BASE_ADDR + 0x72))
-#define FIO4MASK2 (*(volatile unsigned char *)(FIO_BASE_ADDR + 0x92))
-
-#define FIO0MASK3 (*(volatile unsigned char *)(FIO_BASE_ADDR + 0x13))
-#define FIO1MASK3 (*(volatile unsigned char *)(FIO_BASE_ADDR + 0x33))
-#define FIO2MASK3 (*(volatile unsigned char *)(FIO_BASE_ADDR + 0x53))
-#define FIO3MASK3 (*(volatile unsigned char *)(FIO_BASE_ADDR + 0x73))
-#define FIO4MASK3 (*(volatile unsigned char *)(FIO_BASE_ADDR + 0x93))
-
-#define FIO0MASKL (*(volatile unsigned short *)(FIO_BASE_ADDR + 0x10))
-#define FIO1MASKL (*(volatile unsigned short *)(FIO_BASE_ADDR + 0x30))
-#define FIO2MASKL (*(volatile unsigned short *)(FIO_BASE_ADDR + 0x50))
-#define FIO3MASKL (*(volatile unsigned short *)(FIO_BASE_ADDR + 0x70))
-#define FIO4MASKL (*(volatile unsigned short *)(FIO_BASE_ADDR + 0x90))
-
-#define FIO0MASKU (*(volatile unsigned short *)(FIO_BASE_ADDR + 0x12))
-#define FIO1MASKU (*(volatile unsigned short *)(FIO_BASE_ADDR + 0x32))
-#define FIO2MASKU (*(volatile unsigned short *)(FIO_BASE_ADDR + 0x52))
-#define FIO3MASKU (*(volatile unsigned short *)(FIO_BASE_ADDR + 0x72))
-#define FIO4MASKU (*(volatile unsigned short *)(FIO_BASE_ADDR + 0x92))
-
-#define FIO0PIN0 (*(volatile unsigned char *)(FIO_BASE_ADDR + 0x14))
-#define FIO1PIN0 (*(volatile unsigned char *)(FIO_BASE_ADDR + 0x34))
-#define FIO2PIN0 (*(volatile unsigned char *)(FIO_BASE_ADDR + 0x54))
-#define FIO3PIN0 (*(volatile unsigned char *)(FIO_BASE_ADDR + 0x74))
-#define FIO4PIN0 (*(volatile unsigned char *)(FIO_BASE_ADDR + 0x94))
-
-#define FIO0PIN1 (*(volatile unsigned char *)(FIO_BASE_ADDR + 0x15))
-#define FIO1PIN1 (*(volatile unsigned char *)(FIO_BASE_ADDR + 0x35))
-#define FIO2PIN1 (*(volatile unsigned char *)(FIO_BASE_ADDR + 0x55))
-#define FIO3PIN1 (*(volatile unsigned char *)(FIO_BASE_ADDR + 0x75))
-#define FIO4PIN1 (*(volatile unsigned char *)(FIO_BASE_ADDR + 0x95))
-
-#define FIO0PIN2 (*(volatile unsigned char *)(FIO_BASE_ADDR + 0x16))
-#define FIO1PIN2 (*(volatile unsigned char *)(FIO_BASE_ADDR + 0x36))
-#define FIO2PIN2 (*(volatile unsigned char *)(FIO_BASE_ADDR + 0x56))
-#define FIO3PIN2 (*(volatile unsigned char *)(FIO_BASE_ADDR + 0x76))
-#define FIO4PIN2 (*(volatile unsigned char *)(FIO_BASE_ADDR + 0x96))
-
-#define FIO0PIN3 (*(volatile unsigned char *)(FIO_BASE_ADDR + 0x17))
-#define FIO1PIN3 (*(volatile unsigned char *)(FIO_BASE_ADDR + 0x37))
-#define FIO2PIN3 (*(volatile unsigned char *)(FIO_BASE_ADDR + 0x57))
-#define FIO3PIN3 (*(volatile unsigned char *)(FIO_BASE_ADDR + 0x77))
-#define FIO4PIN3 (*(volatile unsigned char *)(FIO_BASE_ADDR + 0x97))
-
-#define FIO0PINL (*(volatile unsigned short *)(FIO_BASE_ADDR + 0x14))
-#define FIO1PINL (*(volatile unsigned short *)(FIO_BASE_ADDR + 0x34))
-#define FIO2PINL (*(volatile unsigned short *)(FIO_BASE_ADDR + 0x54))
-#define FIO3PINL (*(volatile unsigned short *)(FIO_BASE_ADDR + 0x74))
-#define FIO4PINL (*(volatile unsigned short *)(FIO_BASE_ADDR + 0x94))
-
-#define FIO0PINU (*(volatile unsigned short *)(FIO_BASE_ADDR + 0x16))
-#define FIO1PINU (*(volatile unsigned short *)(FIO_BASE_ADDR + 0x36))
-#define FIO2PINU (*(volatile unsigned short *)(FIO_BASE_ADDR + 0x56))
-#define FIO3PINU (*(volatile unsigned short *)(FIO_BASE_ADDR + 0x76))
-#define FIO4PINU (*(volatile unsigned short *)(FIO_BASE_ADDR + 0x96))
-
-#define FIO0SET0 (*(volatile unsigned char *)(FIO_BASE_ADDR + 0x18))
-#define FIO1SET0 (*(volatile unsigned char *)(FIO_BASE_ADDR + 0x38))
-#define FIO2SET0 (*(volatile unsigned char *)(FIO_BASE_ADDR + 0x58))
-#define FIO3SET0 (*(volatile unsigned char *)(FIO_BASE_ADDR + 0x78))
-#define FIO4SET0 (*(volatile unsigned char *)(FIO_BASE_ADDR + 0x98))
-
-#define FIO0SET1 (*(volatile unsigned char *)(FIO_BASE_ADDR + 0x19))
-#define FIO1SET1 (*(volatile unsigned char *)(FIO_BASE_ADDR + 0x29))
-#define FIO2SET1 (*(volatile unsigned char *)(FIO_BASE_ADDR + 0x59))
-#define FIO3SET1 (*(volatile unsigned char *)(FIO_BASE_ADDR + 0x79))
-#define FIO4SET1 (*(volatile unsigned char *)(FIO_BASE_ADDR + 0x99))
-
-#define FIO0SET2 (*(volatile unsigned char *)(FIO_BASE_ADDR + 0x1A))
-#define FIO1SET2 (*(volatile unsigned char *)(FIO_BASE_ADDR + 0x3A))
-#define FIO2SET2 (*(volatile unsigned char *)(FIO_BASE_ADDR + 0x5A))
-#define FIO3SET2 (*(volatile unsigned char *)(FIO_BASE_ADDR + 0x7A))
-#define FIO4SET2 (*(volatile unsigned char *)(FIO_BASE_ADDR + 0x9A))
-
-#define FIO0SET3 (*(volatile unsigned char *)(FIO_BASE_ADDR + 0x1B))
-#define FIO1SET3 (*(volatile unsigned char *)(FIO_BASE_ADDR + 0x3B))
-#define FIO2SET3 (*(volatile unsigned char *)(FIO_BASE_ADDR + 0x5B))
-#define FIO3SET3 (*(volatile unsigned char *)(FIO_BASE_ADDR + 0x7B))
-#define FIO4SET3 (*(volatile unsigned char *)(FIO_BASE_ADDR + 0x9B))
-
-#define FIO0SETL (*(volatile unsigned short *)(FIO_BASE_ADDR + 0x18))
-#define FIO1SETL (*(volatile unsigned short *)(FIO_BASE_ADDR + 0x38))
-#define FIO2SETL (*(volatile unsigned short *)(FIO_BASE_ADDR + 0x58))
-#define FIO3SETL (*(volatile unsigned short *)(FIO_BASE_ADDR + 0x78))
-#define FIO4SETL (*(volatile unsigned short *)(FIO_BASE_ADDR + 0x98))
-
-#define FIO0SETU (*(volatile unsigned short *)(FIO_BASE_ADDR + 0x1A))
-#define FIO1SETU (*(volatile unsigned short *)(FIO_BASE_ADDR + 0x3A))
-#define FIO2SETU (*(volatile unsigned short *)(FIO_BASE_ADDR + 0x5A))
-#define FIO3SETU (*(volatile unsigned short *)(FIO_BASE_ADDR + 0x7A))
-#define FIO4SETU (*(volatile unsigned short *)(FIO_BASE_ADDR + 0x9A))
-
-#define FIO0CLR0 (*(volatile unsigned char *)(FIO_BASE_ADDR + 0x1C))
-#define FIO1CLR0 (*(volatile unsigned char *)(FIO_BASE_ADDR + 0x3C))
-#define FIO2CLR0 (*(volatile unsigned char *)(FIO_BASE_ADDR + 0x5C))
-#define FIO3CLR0 (*(volatile unsigned char *)(FIO_BASE_ADDR + 0x7C))
-#define FIO4CLR0 (*(volatile unsigned char *)(FIO_BASE_ADDR + 0x9C))
-
-#define FIO0CLR1 (*(volatile unsigned char *)(FIO_BASE_ADDR + 0x1D))
-#define FIO1CLR1 (*(volatile unsigned char *)(FIO_BASE_ADDR + 0x2D))
-#define FIO2CLR1 (*(volatile unsigned char *)(FIO_BASE_ADDR + 0x5D))
-#define FIO3CLR1 (*(volatile unsigned char *)(FIO_BASE_ADDR + 0x7D))
-#define FIO4CLR1 (*(volatile unsigned char *)(FIO_BASE_ADDR + 0x9D))
-
-#define FIO0CLR2 (*(volatile unsigned char *)(FIO_BASE_ADDR + 0x1E))
-#define FIO1CLR2 (*(volatile unsigned char *)(FIO_BASE_ADDR + 0x3E))
-#define FIO2CLR2 (*(volatile unsigned char *)(FIO_BASE_ADDR + 0x5E))
-#define FIO3CLR2 (*(volatile unsigned char *)(FIO_BASE_ADDR + 0x7E))
-#define FIO4CLR2 (*(volatile unsigned char *)(FIO_BASE_ADDR + 0x9E))
-
-#define FIO0CLR3 (*(volatile unsigned char *)(FIO_BASE_ADDR + 0x1F))
-#define FIO1CLR3 (*(volatile unsigned char *)(FIO_BASE_ADDR + 0x3F))
-#define FIO2CLR3 (*(volatile unsigned char *)(FIO_BASE_ADDR + 0x5F))
-#define FIO3CLR3 (*(volatile unsigned char *)(FIO_BASE_ADDR + 0x7F))
-#define FIO4CLR3 (*(volatile unsigned char *)(FIO_BASE_ADDR + 0x9F))
-
-#define FIO0CLRL (*(volatile unsigned short *)(FIO_BASE_ADDR + 0x1C))
-#define FIO1CLRL (*(volatile unsigned short *)(FIO_BASE_ADDR + 0x3C))
-#define FIO2CLRL (*(volatile unsigned short *)(FIO_BASE_ADDR + 0x5C))
-#define FIO3CLRL (*(volatile unsigned short *)(FIO_BASE_ADDR + 0x7C))
-#define FIO4CLRL (*(volatile unsigned short *)(FIO_BASE_ADDR + 0x9C))
-
-#define FIO0CLRU (*(volatile unsigned short *)(FIO_BASE_ADDR + 0x1E))
-#define FIO1CLRU (*(volatile unsigned short *)(FIO_BASE_ADDR + 0x3E))
-#define FIO2CLRU (*(volatile unsigned short *)(FIO_BASE_ADDR + 0x5E))
-#define FIO3CLRU (*(volatile unsigned short *)(FIO_BASE_ADDR + 0x7E))
-#define FIO4CLRU (*(volatile unsigned short *)(FIO_BASE_ADDR + 0x9E))
-
-
-/* System Control Block(SCB) modules include Memory Accelerator Module,
-Phase Locked Loop, VPB divider, Power Control, External Interrupt,
-Reset, and Code Security/Debugging */
-#define SCB_BASE_ADDR 0xE01FC000
-
-/* Memory Accelerator Module (MAM) */
-#define MAMCR (*(volatile unsigned long *)(SCB_BASE_ADDR + 0x000))
-#define MAMTIM (*(volatile unsigned long *)(SCB_BASE_ADDR + 0x004))
-#define MEMMAP (*(volatile unsigned long *)(SCB_BASE_ADDR + 0x040))
-
-/* Phase Locked Loop (PLL) */
-#define PLLCON (*(volatile unsigned long *)(SCB_BASE_ADDR + 0x080))
-#define PLLCFG (*(volatile unsigned long *)(SCB_BASE_ADDR + 0x084))
-#define PLLSTAT (*(volatile unsigned long *)(SCB_BASE_ADDR + 0x088))
-#define PLLFEED (*(volatile unsigned long *)(SCB_BASE_ADDR + 0x08C))
-
-/* Power Control */
-#define PCON (*(volatile unsigned long *)(SCB_BASE_ADDR + 0x0C0))
-#define PCONP (*(volatile unsigned long *)(SCB_BASE_ADDR + 0x0C4))
-
-/* Clock Divider */
-#define CCLKCFG (*(volatile unsigned long *)(SCB_BASE_ADDR + 0x104))
-#define USBCLKCFG (*(volatile unsigned long *)(SCB_BASE_ADDR + 0x108))
-#define CLKSRCSEL (*(volatile unsigned long *)(SCB_BASE_ADDR + 0x10C))
-#define PCLKSEL0 (*(volatile unsigned long *)(SCB_BASE_ADDR + 0x1A8))
-#define PCLKSEL1 (*(volatile unsigned long *)(SCB_BASE_ADDR + 0x1AC))
-
-/* External Interrupts */
-#define EXTINT (*(volatile unsigned long *)(SCB_BASE_ADDR + 0x140))
-#define INTWAKE (*(volatile unsigned long *)(SCB_BASE_ADDR + 0x144))
-#define EXTMODE (*(volatile unsigned long *)(SCB_BASE_ADDR + 0x148))
-#define EXTPOLAR (*(volatile unsigned long *)(SCB_BASE_ADDR + 0x14C))
-
-/* Reset, reset source identification */
-#define RSIR (*(volatile unsigned long *)(SCB_BASE_ADDR + 0x180))
-
-/* RSID, code security protection */
-#define CSPR (*(volatile unsigned long *)(SCB_BASE_ADDR + 0x184))
-
-/* AHB configuration */
-#define AHBCFG1 (*(volatile unsigned long *)(SCB_BASE_ADDR + 0x188))
-#define AHBCFG2 (*(volatile unsigned long *)(SCB_BASE_ADDR + 0x18C))
-
-/* System Controls and Status */
-#define SCS (*(volatile unsigned long *)(SCB_BASE_ADDR + 0x1A0))
-
-/* MPMC(EMC) registers, note: all the external memory controller(EMC) registers
-are for LPC24xx only. */
-#define STATIC_MEM0_BASE 0x80000000
-#define STATIC_MEM1_BASE 0x81000000
-#define STATIC_MEM2_BASE 0x82000000
-#define STATIC_MEM3_BASE 0x83000000
-
-#define DYNAMIC_MEM0_BASE 0xA0000000
-#define DYNAMIC_MEM1_BASE 0xB0000000
-#define DYNAMIC_MEM2_BASE 0xC0000000
-#define DYNAMIC_MEM3_BASE 0xD0000000
-
-/* External Memory Controller (EMC) */
-#define EMC_BASE_ADDR 0xFFE08000
-#define EMC_CTRL (*(volatile unsigned long *)(EMC_BASE_ADDR + 0x000))
-#define EMC_STAT (*(volatile unsigned long *)(EMC_BASE_ADDR + 0x004))
-#define EMC_CONFIG (*(volatile unsigned long *)(EMC_BASE_ADDR + 0x008))
-
-/* Dynamic RAM access registers */
-#define EMC_DYN_CTRL (*(volatile unsigned long *)(EMC_BASE_ADDR + 0x020))
-#define EMC_DYN_RFSH (*(volatile unsigned long *)(EMC_BASE_ADDR + 0x024))
-#define EMC_DYN_RD_CFG (*(volatile unsigned long *)(EMC_BASE_ADDR + 0x028))
-#define EMC_DYN_RP (*(volatile unsigned long *)(EMC_BASE_ADDR + 0x030))
-#define EMC_DYN_RAS (*(volatile unsigned long *)(EMC_BASE_ADDR + 0x034))
-#define EMC_DYN_SREX (*(volatile unsigned long *)(EMC_BASE_ADDR + 0x038))
-#define EMC_DYN_APR (*(volatile unsigned long *)(EMC_BASE_ADDR + 0x03C))
-#define EMC_DYN_DAL (*(volatile unsigned long *)(EMC_BASE_ADDR + 0x040))
-#define EMC_DYN_WR (*(volatile unsigned long *)(EMC_BASE_ADDR + 0x044))
-#define EMC_DYN_RC (*(volatile unsigned long *)(EMC_BASE_ADDR + 0x048))
-#define EMC_DYN_RFC (*(volatile unsigned long *)(EMC_BASE_ADDR + 0x04C))
-#define EMC_DYN_XSR (*(volatile unsigned long *)(EMC_BASE_ADDR + 0x050))
-#define EMC_DYN_RRD (*(volatile unsigned long *)(EMC_BASE_ADDR + 0x054))
-#define EMC_DYN_MRD (*(volatile unsigned long *)(EMC_BASE_ADDR + 0x058))
-
-#define EMC_DYN_CFG0 (*(volatile unsigned long *)(EMC_BASE_ADDR + 0x100))
-#define EMC_DYN_RASCAS0 (*(volatile unsigned long *)(EMC_BASE_ADDR + 0x104))
-#define EMC_DYN_CFG1 (*(volatile unsigned long *)(EMC_BASE_ADDR + 0x140))
-#define EMC_DYN_RASCAS1 (*(volatile unsigned long *)(EMC_BASE_ADDR + 0x144))
-#define EMC_DYN_CFG2 (*(volatile unsigned long *)(EMC_BASE_ADDR + 0x160))
-#define EMC_DYN_RASCAS2 (*(volatile unsigned long *)(EMC_BASE_ADDR + 0x164))
-#define EMC_DYN_CFG3 (*(volatile unsigned long *)(EMC_BASE_ADDR + 0x180))
-#define EMC_DYN_RASCAS3 (*(volatile unsigned long *)(EMC_BASE_ADDR + 0x184))
-
-/* static RAM access registers */
-#define EMC_STA_CFG0 (*(volatile unsigned long *)(EMC_BASE_ADDR + 0x200))
-#define EMC_STA_WAITWEN0 (*(volatile unsigned long *)(EMC_BASE_ADDR + 0x204))
-#define EMC_STA_WAITOEN0 (*(volatile unsigned long *)(EMC_BASE_ADDR + 0x208))
-#define EMC_STA_WAITRD0 (*(volatile unsigned long *)(EMC_BASE_ADDR + 0x20C))
-#define EMC_STA_WAITPAGE0 (*(volatile unsigned long *)(EMC_BASE_ADDR + 0x210))
-#define EMC_STA_WAITWR0 (*(volatile unsigned long *)(EMC_BASE_ADDR + 0x214))
-#define EMC_STA_WAITTURN0 (*(volatile unsigned long *)(EMC_BASE_ADDR + 0x218))
-
-#define EMC_STA_CFG1 (*(volatile unsigned long *)(EMC_BASE_ADDR + 0x220))
-#define EMC_STA_WAITWEN1 (*(volatile unsigned long *)(EMC_BASE_ADDR + 0x224))
-#define EMC_STA_WAITOEN1 (*(volatile unsigned long *)(EMC_BASE_ADDR + 0x228))
-#define EMC_STA_WAITRD1 (*(volatile unsigned long *)(EMC_BASE_ADDR + 0x22C))
-#define EMC_STA_WAITPAGE1 (*(volatile unsigned long *)(EMC_BASE_ADDR + 0x230))
-#define EMC_STA_WAITWR1 (*(volatile unsigned long *)(EMC_BASE_ADDR + 0x234))
-#define EMC_STA_WAITTURN1 (*(volatile unsigned long *)(EMC_BASE_ADDR + 0x238))
-
-#define EMC_STA_CFG2 (*(volatile unsigned long *)(EMC_BASE_ADDR + 0x240))
-#define EMC_STA_WAITWEN2 (*(volatile unsigned long *)(EMC_BASE_ADDR + 0x244))
-#define EMC_STA_WAITOEN2 (*(volatile unsigned long *)(EMC_BASE_ADDR + 0x248))
-#define EMC_STA_WAITRD2 (*(volatile unsigned long *)(EMC_BASE_ADDR + 0x24C))
-#define EMC_STA_WAITPAGE2 (*(volatile unsigned long *)(EMC_BASE_ADDR + 0x250))
-#define EMC_STA_WAITWR2 (*(volatile unsigned long *)(EMC_BASE_ADDR + 0x254))
-#define EMC_STA_WAITTURN2 (*(volatile unsigned long *)(EMC_BASE_ADDR + 0x258))
-
-#define EMC_STA_CFG3 (*(volatile unsigned long *)(EMC_BASE_ADDR + 0x260))
-#define EMC_STA_WAITWEN3 (*(volatile unsigned long *)(EMC_BASE_ADDR + 0x264))
-#define EMC_STA_WAITOEN3 (*(volatile unsigned long *)(EMC_BASE_ADDR + 0x268))
-#define EMC_STA_WAITRD3 (*(volatile unsigned long *)(EMC_BASE_ADDR + 0x26C))
-#define EMC_STA_WAITPAGE3 (*(volatile unsigned long *)(EMC_BASE_ADDR + 0x270))
-#define EMC_STA_WAITWR3 (*(volatile unsigned long *)(EMC_BASE_ADDR + 0x274))
-#define EMC_STA_WAITTURN3 (*(volatile unsigned long *)(EMC_BASE_ADDR + 0x278))
-
-#define EMC_STA_EXT_WAIT (*(volatile unsigned long *)(EMC_BASE_ADDR + 0x880))
-
-
-/* Timer 0 */
-#define TMR0_BASE_ADDR 0xE0004000
-#define T0IR (*(volatile unsigned long *)(TMR0_BASE_ADDR + 0x00))
-#define T0TCR (*(volatile unsigned long *)(TMR0_BASE_ADDR + 0x04))
-#define T0TC (*(volatile unsigned long *)(TMR0_BASE_ADDR + 0x08))
-#define T0PR (*(volatile unsigned long *)(TMR0_BASE_ADDR + 0x0C))
-#define T0PC (*(volatile unsigned long *)(TMR0_BASE_ADDR + 0x10))
-#define T0MCR (*(volatile unsigned long *)(TMR0_BASE_ADDR + 0x14))
-#define T0MR0 (*(volatile unsigned long *)(TMR0_BASE_ADDR + 0x18))
-#define T0MR1 (*(volatile unsigned long *)(TMR0_BASE_ADDR + 0x1C))
-#define T0MR2 (*(volatile unsigned long *)(TMR0_BASE_ADDR + 0x20))
-#define T0MR3 (*(volatile unsigned long *)(TMR0_BASE_ADDR + 0x24))
-#define T0CCR (*(volatile unsigned long *)(TMR0_BASE_ADDR + 0x28))
-#define T0CR0 (*(volatile unsigned long *)(TMR0_BASE_ADDR + 0x2C))
-#define T0CR1 (*(volatile unsigned long *)(TMR0_BASE_ADDR + 0x30))
-#define T0CR2 (*(volatile unsigned long *)(TMR0_BASE_ADDR + 0x34))
-#define T0CR3 (*(volatile unsigned long *)(TMR0_BASE_ADDR + 0x38))
-#define T0EMR (*(volatile unsigned long *)(TMR0_BASE_ADDR + 0x3C))
-#define T0CTCR (*(volatile unsigned long *)(TMR0_BASE_ADDR + 0x70))
-
-/* Timer 1 */
-#define TMR1_BASE_ADDR 0xE0008000
-#define T1IR (*(volatile unsigned long *)(TMR1_BASE_ADDR + 0x00))
-#define T1TCR (*(volatile unsigned long *)(TMR1_BASE_ADDR + 0x04))
-#define T1TC (*(volatile unsigned long *)(TMR1_BASE_ADDR + 0x08))
-#define T1PR (*(volatile unsigned long *)(TMR1_BASE_ADDR + 0x0C))
-#define T1PC (*(volatile unsigned long *)(TMR1_BASE_ADDR + 0x10))
-#define T1MCR (*(volatile unsigned long *)(TMR1_BASE_ADDR + 0x14))
-#define T1MR0 (*(volatile unsigned long *)(TMR1_BASE_ADDR + 0x18))
-#define T1MR1 (*(volatile unsigned long *)(TMR1_BASE_ADDR + 0x1C))
-#define T1MR2 (*(volatile unsigned long *)(TMR1_BASE_ADDR + 0x20))
-#define T1MR3 (*(volatile unsigned long *)(TMR1_BASE_ADDR + 0x24))
-#define T1CCR (*(volatile unsigned long *)(TMR1_BASE_ADDR + 0x28))
-#define T1CR0 (*(volatile unsigned long *)(TMR1_BASE_ADDR + 0x2C))
-#define T1CR1 (*(volatile unsigned long *)(TMR1_BASE_ADDR + 0x30))
-#define T1CR2 (*(volatile unsigned long *)(TMR1_BASE_ADDR + 0x34))
-#define T1CR3 (*(volatile unsigned long *)(TMR1_BASE_ADDR + 0x38))
-#define T1EMR (*(volatile unsigned long *)(TMR1_BASE_ADDR + 0x3C))
-#define T1CTCR (*(volatile unsigned long *)(TMR1_BASE_ADDR + 0x70))
-
-/* Timer 2 */
-#define TMR2_BASE_ADDR 0xE0070000
-#define T2IR (*(volatile unsigned long *)(TMR2_BASE_ADDR + 0x00))
-#define T2TCR (*(volatile unsigned long *)(TMR2_BASE_ADDR + 0x04))
-#define T2TC (*(volatile unsigned long *)(TMR2_BASE_ADDR + 0x08))
-#define T2PR (*(volatile unsigned long *)(TMR2_BASE_ADDR + 0x0C))
-#define T2PC (*(volatile unsigned long *)(TMR2_BASE_ADDR + 0x10))
-#define T2MCR (*(volatile unsigned long *)(TMR2_BASE_ADDR + 0x14))
-#define T2MR0 (*(volatile unsigned long *)(TMR2_BASE_ADDR + 0x18))
-#define T2MR1 (*(volatile unsigned long *)(TMR2_BASE_ADDR + 0x1C))
-#define T2MR2 (*(volatile unsigned long *)(TMR2_BASE_ADDR + 0x20))
-#define T2MR3 (*(volatile unsigned long *)(TMR2_BASE_ADDR + 0x24))
-#define T2CCR (*(volatile unsigned long *)(TMR2_BASE_ADDR + 0x28))
-#define T2CR0 (*(volatile unsigned long *)(TMR2_BASE_ADDR + 0x2C))
-#define T2CR1 (*(volatile unsigned long *)(TMR2_BASE_ADDR + 0x30))
-#define T2CR2 (*(volatile unsigned long *)(TMR2_BASE_ADDR + 0x34))
-#define T2CR3 (*(volatile unsigned long *)(TMR2_BASE_ADDR + 0x38))
-#define T2EMR (*(volatile unsigned long *)(TMR2_BASE_ADDR + 0x3C))
-#define T2CTCR (*(volatile unsigned long *)(TMR2_BASE_ADDR + 0x70))
-
-/* Timer 3 */
-#define TMR3_BASE_ADDR 0xE0074000
-#define T3IR (*(volatile unsigned long *)(TMR3_BASE_ADDR + 0x00))
-#define T3TCR (*(volatile unsigned long *)(TMR3_BASE_ADDR + 0x04))
-#define T3TC (*(volatile unsigned long *)(TMR3_BASE_ADDR + 0x08))
-#define T3PR (*(volatile unsigned long *)(TMR3_BASE_ADDR + 0x0C))
-#define T3PC (*(volatile unsigned long *)(TMR3_BASE_ADDR + 0x10))
-#define T3MCR (*(volatile unsigned long *)(TMR3_BASE_ADDR + 0x14))
-#define T3MR0 (*(volatile unsigned long *)(TMR3_BASE_ADDR + 0x18))
-#define T3MR1 (*(volatile unsigned long *)(TMR3_BASE_ADDR + 0x1C))
-#define T3MR2 (*(volatile unsigned long *)(TMR3_BASE_ADDR + 0x20))
-#define T3MR3 (*(volatile unsigned long *)(TMR3_BASE_ADDR + 0x24))
-#define T3CCR (*(volatile unsigned long *)(TMR3_BASE_ADDR + 0x28))
-#define T3CR0 (*(volatile unsigned long *)(TMR3_BASE_ADDR + 0x2C))
-#define T3CR1 (*(volatile unsigned long *)(TMR3_BASE_ADDR + 0x30))
-#define T3CR2 (*(volatile unsigned long *)(TMR3_BASE_ADDR + 0x34))
-#define T3CR3 (*(volatile unsigned long *)(TMR3_BASE_ADDR + 0x38))
-#define T3EMR (*(volatile unsigned long *)(TMR3_BASE_ADDR + 0x3C))
-#define T3CTCR (*(volatile unsigned long *)(TMR3_BASE_ADDR + 0x70))
-
-
-/* Pulse Width Modulator (PWM) */
-#define PWM0_BASE_ADDR 0xE0014000
-#define PWM0IR (*(volatile unsigned long *)(PWM0_BASE_ADDR + 0x00))
-#define PWM0TCR (*(volatile unsigned long *)(PWM0_BASE_ADDR + 0x04))
-#define PWM0TC (*(volatile unsigned long *)(PWM0_BASE_ADDR + 0x08))
-#define PWM0PR (*(volatile unsigned long *)(PWM0_BASE_ADDR + 0x0C))
-#define PWM0PC (*(volatile unsigned long *)(PWM0_BASE_ADDR + 0x10))
-#define PWM0MCR (*(volatile unsigned long *)(PWM0_BASE_ADDR + 0x14))
-#define PWM0MR0 (*(volatile unsigned long *)(PWM0_BASE_ADDR + 0x18))
-#define PWM0MR1 (*(volatile unsigned long *)(PWM0_BASE_ADDR + 0x1C))
-#define PWM0MR2 (*(volatile unsigned long *)(PWM0_BASE_ADDR + 0x20))
-#define PWM0MR3 (*(volatile unsigned long *)(PWM0_BASE_ADDR + 0x24))
-#define PWM0CCR (*(volatile unsigned long *)(PWM0_BASE_ADDR + 0x28))
-#define PWM0CR0 (*(volatile unsigned long *)(PWM0_BASE_ADDR + 0x2C))
-#define PWM0CR1 (*(volatile unsigned long *)(PWM0_BASE_ADDR + 0x30))
-#define PWM0CR2 (*(volatile unsigned long *)(PWM0_BASE_ADDR + 0x34))
-#define PWM0CR3 (*(volatile unsigned long *)(PWM0_BASE_ADDR + 0x38))
-#define PWM0EMR (*(volatile unsigned long *)(PWM0_BASE_ADDR + 0x3C))
-#define PWM0MR4 (*(volatile unsigned long *)(PWM0_BASE_ADDR + 0x40))
-#define PWM0MR5 (*(volatile unsigned long *)(PWM0_BASE_ADDR + 0x44))
-#define PWM0MR6 (*(volatile unsigned long *)(PWM0_BASE_ADDR + 0x48))
-#define PWM0PCR (*(volatile unsigned long *)(PWM0_BASE_ADDR + 0x4C))
-#define PWM0LER (*(volatile unsigned long *)(PWM0_BASE_ADDR + 0x50))
-#define PWM0CTCR (*(volatile unsigned long *)(PWM0_BASE_ADDR + 0x70))
-
-#define PWM1_BASE_ADDR 0xE0018000
-#define PWM1IR (*(volatile unsigned long *)(PWM1_BASE_ADDR + 0x00))
-#define PWM1TCR (*(volatile unsigned long *)(PWM1_BASE_ADDR + 0x04))
-#define PWM1TC (*(volatile unsigned long *)(PWM1_BASE_ADDR + 0x08))
-#define PWM1PR (*(volatile unsigned long *)(PWM1_BASE_ADDR + 0x0C))
-#define PWM1PC (*(volatile unsigned long *)(PWM1_BASE_ADDR + 0x10))
-#define PWM1MCR (*(volatile unsigned long *)(PWM1_BASE_ADDR + 0x14))
-#define PWM1MR0 (*(volatile unsigned long *)(PWM1_BASE_ADDR + 0x18))
-#define PWM1MR1 (*(volatile unsigned long *)(PWM1_BASE_ADDR + 0x1C))
-#define PWM1MR2 (*(volatile unsigned long *)(PWM1_BASE_ADDR + 0x20))
-#define PWM1MR3 (*(volatile unsigned long *)(PWM1_BASE_ADDR + 0x24))
-#define PWM1CCR (*(volatile unsigned long *)(PWM1_BASE_ADDR + 0x28))
-#define PWM1CR0 (*(volatile unsigned long *)(PWM1_BASE_ADDR + 0x2C))
-#define PWM1CR1 (*(volatile unsigned long *)(PWM1_BASE_ADDR + 0x30))
-#define PWM1CR2 (*(volatile unsigned long *)(PWM1_BASE_ADDR + 0x34))
-#define PWM1CR3 (*(volatile unsigned long *)(PWM1_BASE_ADDR + 0x38))
-#define PWM1EMR (*(volatile unsigned long *)(PWM1_BASE_ADDR + 0x3C))
-#define PWM1MR4 (*(volatile unsigned long *)(PWM1_BASE_ADDR + 0x40))
-#define PWM1MR5 (*(volatile unsigned long *)(PWM1_BASE_ADDR + 0x44))
-#define PWM1MR6 (*(volatile unsigned long *)(PWM1_BASE_ADDR + 0x48))
-#define PWM1PCR (*(volatile unsigned long *)(PWM1_BASE_ADDR + 0x4C))
-#define PWM1LER (*(volatile unsigned long *)(PWM1_BASE_ADDR + 0x50))
-#define PWM1CTCR (*(volatile unsigned long *)(PWM1_BASE_ADDR + 0x70))
-
-
-/* Universal Asynchronous Receiver Transmitter 0 (UART0) */
-#define UART0_BASE_ADDR 0xE000C000
-#define U0RBR (*(volatile unsigned long *)(UART0_BASE_ADDR + 0x00))
-#define U0THR (*(volatile unsigned long *)(UART0_BASE_ADDR + 0x00))
-#define U0DLL (*(volatile unsigned long *)(UART0_BASE_ADDR + 0x00))
-#define U0DLM (*(volatile unsigned long *)(UART0_BASE_ADDR + 0x04))
-#define U0IER (*(volatile unsigned long *)(UART0_BASE_ADDR + 0x04))
-#define U0IIR (*(volatile unsigned long *)(UART0_BASE_ADDR + 0x08))
-#define U0FCR (*(volatile unsigned long *)(UART0_BASE_ADDR + 0x08))
-#define U0LCR (*(volatile unsigned long *)(UART0_BASE_ADDR + 0x0C))
-#define U0LSR (*(volatile unsigned long *)(UART0_BASE_ADDR + 0x14))
-#define U0SCR (*(volatile unsigned long *)(UART0_BASE_ADDR + 0x1C))
-#define U0ACR (*(volatile unsigned long *)(UART0_BASE_ADDR + 0x20))
-#define U0ICR (*(volatile unsigned long *)(UART0_BASE_ADDR + 0x24))
-#define U0FDR (*(volatile unsigned long *)(UART0_BASE_ADDR + 0x28))
-#define U0TER (*(volatile unsigned long *)(UART0_BASE_ADDR + 0x30))
-
-/* Universal Asynchronous Receiver Transmitter 1 (UART1) */
-#define UART1_BASE_ADDR 0xE0010000
-#define U1RBR (*(volatile unsigned long *)(UART1_BASE_ADDR + 0x00))
-#define U1THR (*(volatile unsigned long *)(UART1_BASE_ADDR + 0x00))
-#define U1DLL (*(volatile unsigned long *)(UART1_BASE_ADDR + 0x00))
-#define U1DLM (*(volatile unsigned long *)(UART1_BASE_ADDR + 0x04))
-#define U1IER (*(volatile unsigned long *)(UART1_BASE_ADDR + 0x04))
-#define U1IIR (*(volatile unsigned long *)(UART1_BASE_ADDR + 0x08))
-#define U1FCR (*(volatile unsigned long *)(UART1_BASE_ADDR + 0x08))
-#define U1LCR (*(volatile unsigned long *)(UART1_BASE_ADDR + 0x0C))
-#define U1MCR (*(volatile unsigned long *)(UART1_BASE_ADDR + 0x10))
-#define U1LSR (*(volatile unsigned long *)(UART1_BASE_ADDR + 0x14))
-#define U1MSR (*(volatile unsigned long *)(UART1_BASE_ADDR + 0x18))
-#define U1SCR (*(volatile unsigned long *)(UART1_BASE_ADDR + 0x1C))
-#define U1ACR (*(volatile unsigned long *)(UART1_BASE_ADDR + 0x20))
-#define U1FDR (*(volatile unsigned long *)(UART1_BASE_ADDR + 0x28))
-#define U1TER (*(volatile unsigned long *)(UART1_BASE_ADDR + 0x30))
-
-/* Universal Asynchronous Receiver Transmitter 2 (UART2) */
-#define UART2_BASE_ADDR 0xE0078000
-#define U2RBR (*(volatile unsigned long *)(UART2_BASE_ADDR + 0x00))
-#define U2THR (*(volatile unsigned long *)(UART2_BASE_ADDR + 0x00))
-#define U2DLL (*(volatile unsigned long *)(UART2_BASE_ADDR + 0x00))
-#define U2DLM (*(volatile unsigned long *)(UART2_BASE_ADDR + 0x04))
-#define U2IER (*(volatile unsigned long *)(UART2_BASE_ADDR + 0x04))
-#define U2IIR (*(volatile unsigned long *)(UART2_BASE_ADDR + 0x08))
-#define U2FCR (*(volatile unsigned long *)(UART2_BASE_ADDR + 0x08))
-#define U2LCR (*(volatile unsigned long *)(UART2_BASE_ADDR + 0x0C))
-#define U2LSR (*(volatile unsigned long *)(UART2_BASE_ADDR + 0x14))
-#define U2SCR (*(volatile unsigned long *)(UART2_BASE_ADDR + 0x1C))
-#define U2ACR (*(volatile unsigned long *)(UART2_BASE_ADDR + 0x20))
-#define U2ICR (*(volatile unsigned long *)(UART2_BASE_ADDR + 0x24))
-#define U2FDR (*(volatile unsigned long *)(UART2_BASE_ADDR + 0x28))
-#define U2TER (*(volatile unsigned long *)(UART2_BASE_ADDR + 0x30))
-
-/* Universal Asynchronous Receiver Transmitter 3 (UART3) */
-#define UART3_BASE_ADDR 0xE007C000
-#define U3RBR (*(volatile unsigned long *)(UART3_BASE_ADDR + 0x00))
-#define U3THR (*(volatile unsigned long *)(UART3_BASE_ADDR + 0x00))
-#define U3DLL (*(volatile unsigned long *)(UART3_BASE_ADDR + 0x00))
-#define U3DLM (*(volatile unsigned long *)(UART3_BASE_ADDR + 0x04))
-#define U3IER (*(volatile unsigned long *)(UART3_BASE_ADDR + 0x04))
-#define U3IIR (*(volatile unsigned long *)(UART3_BASE_ADDR + 0x08))
-#define U3FCR (*(volatile unsigned long *)(UART3_BASE_ADDR + 0x08))
-#define U3LCR (*(volatile unsigned long *)(UART3_BASE_ADDR + 0x0C))
-#define U3LSR (*(volatile unsigned long *)(UART3_BASE_ADDR + 0x14))
-#define U3SCR (*(volatile unsigned long *)(UART3_BASE_ADDR + 0x1C))
-#define U3ACR (*(volatile unsigned long *)(UART3_BASE_ADDR + 0x20))
-#define U3ICR (*(volatile unsigned long *)(UART3_BASE_ADDR + 0x24))
-#define U3FDR (*(volatile unsigned long *)(UART3_BASE_ADDR + 0x28))
-#define U3TER (*(volatile unsigned long *)(UART3_BASE_ADDR + 0x30))
-
-/* I2C Interface 0 */
-#define I2C0_BASE_ADDR 0xE001C000
-#define I20CONSET (*(volatile unsigned long *)(I2C0_BASE_ADDR + 0x00))
-#define I20STAT (*(volatile unsigned long *)(I2C0_BASE_ADDR + 0x04))
-#define I20DAT (*(volatile unsigned long *)(I2C0_BASE_ADDR + 0x08))
-#define I20ADR (*(volatile unsigned long *)(I2C0_BASE_ADDR + 0x0C))
-#define I20SCLH (*(volatile unsigned long *)(I2C0_BASE_ADDR + 0x10))
-#define I20SCLL (*(volatile unsigned long *)(I2C0_BASE_ADDR + 0x14))
-#define I20CONCLR (*(volatile unsigned long *)(I2C0_BASE_ADDR + 0x18))
-
-/* I2C Interface 1 */
-#define I2C1_BASE_ADDR 0xE005C000
-#define I21CONSET (*(volatile unsigned long *)(I2C1_BASE_ADDR + 0x00))
-#define I21STAT (*(volatile unsigned long *)(I2C1_BASE_ADDR + 0x04))
-#define I21DAT (*(volatile unsigned long *)(I2C1_BASE_ADDR + 0x08))
-#define I21ADR (*(volatile unsigned long *)(I2C1_BASE_ADDR + 0x0C))
-#define I21SCLH (*(volatile unsigned long *)(I2C1_BASE_ADDR + 0x10))
-#define I21SCLL (*(volatile unsigned long *)(I2C1_BASE_ADDR + 0x14))
-#define I21CONCLR (*(volatile unsigned long *)(I2C1_BASE_ADDR + 0x18))
-
-/* I2C Interface 2 */
-#define I2C2_BASE_ADDR 0xE0080000
-#define I22CONSET (*(volatile unsigned long *)(I2C2_BASE_ADDR + 0x00))
-#define I22STAT (*(volatile unsigned long *)(I2C2_BASE_ADDR + 0x04))
-#define I22DAT (*(volatile unsigned long *)(I2C2_BASE_ADDR + 0x08))
-#define I22ADR (*(volatile unsigned long *)(I2C2_BASE_ADDR + 0x0C))
-#define I22SCLH (*(volatile unsigned long *)(I2C2_BASE_ADDR + 0x10))
-#define I22SCLL (*(volatile unsigned long *)(I2C2_BASE_ADDR + 0x14))
-#define I22CONCLR (*(volatile unsigned long *)(I2C2_BASE_ADDR + 0x18))
-
-/* SPI0 (Serial Peripheral Interface 0) */
-#define SPI0_BASE_ADDR 0xE0020000
-#define S0SPCR (*(volatile unsigned long *)(SPI0_BASE_ADDR + 0x00))
-#define S0SPSR (*(volatile unsigned long *)(SPI0_BASE_ADDR + 0x04))
-#define S0SPDR (*(volatile unsigned long *)(SPI0_BASE_ADDR + 0x08))
-#define S0SPCCR (*(volatile unsigned long *)(SPI0_BASE_ADDR + 0x0C))
-#define S0SPINT (*(volatile unsigned long *)(SPI0_BASE_ADDR + 0x1C))
-
-/* SSP0 Controller */
-#define SSP0_BASE_ADDR 0xE0068000
-#define SSP0CR0 (*(volatile unsigned long *)(SSP0_BASE_ADDR + 0x00))
-#define SSP0CR1 (*(volatile unsigned long *)(SSP0_BASE_ADDR + 0x04))
-#define SSP0DR (*(volatile unsigned long *)(SSP0_BASE_ADDR + 0x08))
-#define SSP0SR (*(volatile unsigned long *)(SSP0_BASE_ADDR + 0x0C))
-#define SSP0CPSR (*(volatile unsigned long *)(SSP0_BASE_ADDR + 0x10))
-#define SSP0IMSC (*(volatile unsigned long *)(SSP0_BASE_ADDR + 0x14))
-#define SSP0RIS (*(volatile unsigned long *)(SSP0_BASE_ADDR + 0x18))
-#define SSP0MIS (*(volatile unsigned long *)(SSP0_BASE_ADDR + 0x1C))
-#define SSP0ICR (*(volatile unsigned long *)(SSP0_BASE_ADDR + 0x20))
-#define SSP0DMACR (*(volatile unsigned long *)(SSP0_BASE_ADDR + 0x24))
-
-/* SSP1 Controller */
-#define SSP1_BASE_ADDR 0xE0030000
-#define SSP1CR0 (*(volatile unsigned long *)(SSP1_BASE_ADDR + 0x00))
-#define SSP1CR1 (*(volatile unsigned long *)(SSP1_BASE_ADDR + 0x04))
-#define SSP1DR (*(volatile unsigned long *)(SSP1_BASE_ADDR + 0x08))
-#define SSP1SR (*(volatile unsigned long *)(SSP1_BASE_ADDR + 0x0C))
-#define SSP1CPSR (*(volatile unsigned long *)(SSP1_BASE_ADDR + 0x10))
-#define SSP1IMSC (*(volatile unsigned long *)(SSP1_BASE_ADDR + 0x14))
-#define SSP1RIS (*(volatile unsigned long *)(SSP1_BASE_ADDR + 0x18))
-#define SSP1MIS (*(volatile unsigned long *)(SSP1_BASE_ADDR + 0x1C))
-#define SSP1ICR (*(volatile unsigned long *)(SSP1_BASE_ADDR + 0x20))
-#define SSP1DMACR (*(volatile unsigned long *)(SSP1_BASE_ADDR + 0x24))
-
-
-/* Real Time Clock */
-#define RTC_BASE_ADDR 0xE0024000
-#define RTC_ILR (*(volatile unsigned long *)(RTC_BASE_ADDR + 0x00))
-#define RTC_CTC (*(volatile unsigned long *)(RTC_BASE_ADDR + 0x04))
-#define RTC_CCR (*(volatile unsigned long *)(RTC_BASE_ADDR + 0x08))
-#define RTC_CIIR (*(volatile unsigned long *)(RTC_BASE_ADDR + 0x0C))
-#define RTC_AMR (*(volatile unsigned long *)(RTC_BASE_ADDR + 0x10))
-#define RTC_CTIME0 (*(volatile unsigned long *)(RTC_BASE_ADDR + 0x14))
-#define RTC_CTIME1 (*(volatile unsigned long *)(RTC_BASE_ADDR + 0x18))
-#define RTC_CTIME2 (*(volatile unsigned long *)(RTC_BASE_ADDR + 0x1C))
-#define RTC_SEC (*(volatile unsigned long *)(RTC_BASE_ADDR + 0x20))
-#define RTC_MIN (*(volatile unsigned long *)(RTC_BASE_ADDR + 0x24))
-#define RTC_HOUR (*(volatile unsigned long *)(RTC_BASE_ADDR + 0x28))
-#define RTC_DOM (*(volatile unsigned long *)(RTC_BASE_ADDR + 0x2C))
-#define RTC_DOW (*(volatile unsigned long *)(RTC_BASE_ADDR + 0x30))
-#define RTC_DOY (*(volatile unsigned long *)(RTC_BASE_ADDR + 0x34))
-#define RTC_MONTH (*(volatile unsigned long *)(RTC_BASE_ADDR + 0x38))
-#define RTC_YEAR (*(volatile unsigned long *)(RTC_BASE_ADDR + 0x3C))
-#define RTC_CISS (*(volatile unsigned long *)(RTC_BASE_ADDR + 0x40))
-#define RTC_ALSEC (*(volatile unsigned long *)(RTC_BASE_ADDR + 0x60))
-#define RTC_ALMIN (*(volatile unsigned long *)(RTC_BASE_ADDR + 0x64))
-#define RTC_ALHOUR (*(volatile unsigned long *)(RTC_BASE_ADDR + 0x68))
-#define RTC_ALDOM (*(volatile unsigned long *)(RTC_BASE_ADDR + 0x6C))
-#define RTC_ALDOW (*(volatile unsigned long *)(RTC_BASE_ADDR + 0x70))
-#define RTC_ALDOY (*(volatile unsigned long *)(RTC_BASE_ADDR + 0x74))
-#define RTC_ALMON (*(volatile unsigned long *)(RTC_BASE_ADDR + 0x78))
-#define RTC_ALYEAR (*(volatile unsigned long *)(RTC_BASE_ADDR + 0x7C))
-#define RTC_PREINT (*(volatile unsigned long *)(RTC_BASE_ADDR + 0x80))
-#define RTC_PREFRAC (*(volatile unsigned long *)(RTC_BASE_ADDR + 0x84))
-
-
-/* A/D Converter 0 (AD0) */
-#define AD0_BASE_ADDR 0xE0034000
-#define AD0CR (*(volatile unsigned long *)(AD0_BASE_ADDR + 0x00))
-#define AD0GDR (*(volatile unsigned long *)(AD0_BASE_ADDR + 0x04))
-#define AD0INTEN (*(volatile unsigned long *)(AD0_BASE_ADDR + 0x0C))
-#define AD0DR0 (*(volatile unsigned long *)(AD0_BASE_ADDR + 0x10))
-#define AD0DR1 (*(volatile unsigned long *)(AD0_BASE_ADDR + 0x14))
-#define AD0DR2 (*(volatile unsigned long *)(AD0_BASE_ADDR + 0x18))
-#define AD0DR3 (*(volatile unsigned long *)(AD0_BASE_ADDR + 0x1C))
-#define AD0DR4 (*(volatile unsigned long *)(AD0_BASE_ADDR + 0x20))
-#define AD0DR5 (*(volatile unsigned long *)(AD0_BASE_ADDR + 0x24))
-#define AD0DR6 (*(volatile unsigned long *)(AD0_BASE_ADDR + 0x28))
-#define AD0DR7 (*(volatile unsigned long *)(AD0_BASE_ADDR + 0x2C))
-#define AD0STAT (*(volatile unsigned long *)(AD0_BASE_ADDR + 0x30))
-
-
-/* D/A Converter */
-#define DAC_BASE_ADDR 0xE006C000
-#define DACR (*(volatile unsigned long *)(DAC_BASE_ADDR + 0x00))
-
-
-/* Watchdog */
-#define WDG_BASE_ADDR 0xE0000000
-#define WDMOD (*(volatile unsigned long *)(WDG_BASE_ADDR + 0x00))
-#define WDTC (*(volatile unsigned long *)(WDG_BASE_ADDR + 0x04))
-#define WDFEED (*(volatile unsigned long *)(WDG_BASE_ADDR + 0x08))
-#define WDTV (*(volatile unsigned long *)(WDG_BASE_ADDR + 0x0C))
-#define WDCLKSEL (*(volatile unsigned long *)(WDG_BASE_ADDR + 0x10))
-
-/* CAN CONTROLLERS AND ACCEPTANCE FILTER */
-#define CAN_ACCEPT_BASE_ADDR 0xE003C000
-#define CAN_AFMR (*(volatile unsigned long *)(CAN_ACCEPT_BASE_ADDR + 0x00))
-#define CAN_SFF_SA (*(volatile unsigned long *)(CAN_ACCEPT_BASE_ADDR + 0x04))
-#define CAN_SFF_GRP_SA (*(volatile unsigned long *)(CAN_ACCEPT_BASE_ADDR + 0x08))
-#define CAN_EFF_SA (*(volatile unsigned long *)(CAN_ACCEPT_BASE_ADDR + 0x0C))
-#define CAN_EFF_GRP_SA (*(volatile unsigned long *)(CAN_ACCEPT_BASE_ADDR + 0x10))
-#define CAN_EOT (*(volatile unsigned long *)(CAN_ACCEPT_BASE_ADDR + 0x14))
-#define CAN_LUT_ERR_ADR (*(volatile unsigned long *)(CAN_ACCEPT_BASE_ADDR + 0x18))
-#define CAN_LUT_ERR (*(volatile unsigned long *)(CAN_ACCEPT_BASE_ADDR + 0x1C))
-
-#define CAN_CENTRAL_BASE_ADDR 0xE0040000
-#define CAN_TX_SR (*(volatile unsigned long *)(CAN_CENTRAL_BASE_ADDR + 0x00))
-#define CAN_RX_SR (*(volatile unsigned long *)(CAN_CENTRAL_BASE_ADDR + 0x04))
-#define CAN_MSR (*(volatile unsigned long *)(CAN_CENTRAL_BASE_ADDR + 0x08))
-
-#define CAN1_BASE_ADDR 0xE0044000
-#define CAN1MOD (*(volatile unsigned long *)(CAN1_BASE_ADDR + 0x00))
-#define CAN1CMR (*(volatile unsigned long *)(CAN1_BASE_ADDR + 0x04))
-#define CAN1GSR (*(volatile unsigned long *)(CAN1_BASE_ADDR + 0x08))
-#define CAN1ICR (*(volatile unsigned long *)(CAN1_BASE_ADDR + 0x0C))
-#define CAN1IER (*(volatile unsigned long *)(CAN1_BASE_ADDR + 0x10))
-#define CAN1BTR (*(volatile unsigned long *)(CAN1_BASE_ADDR + 0x14))
-#define CAN1EWL (*(volatile unsigned long *)(CAN1_BASE_ADDR + 0x18))
-#define CAN1SR (*(volatile unsigned long *)(CAN1_BASE_ADDR + 0x1C))
-#define CAN1RFS (*(volatile unsigned long *)(CAN1_BASE_ADDR + 0x20))
-#define CAN1RID (*(volatile unsigned long *)(CAN1_BASE_ADDR + 0x24))
-#define CAN1RDA (*(volatile unsigned long *)(CAN1_BASE_ADDR + 0x28))
-#define CAN1RDB (*(volatile unsigned long *)(CAN1_BASE_ADDR + 0x2C))
-
-#define CAN1TFI1 (*(volatile unsigned long *)(CAN1_BASE_ADDR + 0x30))
-#define CAN1TID1 (*(volatile unsigned long *)(CAN1_BASE_ADDR + 0x34))
-#define CAN1TDA1 (*(volatile unsigned long *)(CAN1_BASE_ADDR + 0x38))
-#define CAN1TDB1 (*(volatile unsigned long *)(CAN1_BASE_ADDR + 0x3C))
-#define CAN1TFI2 (*(volatile unsigned long *)(CAN1_BASE_ADDR + 0x40))
-#define CAN1TID2 (*(volatile unsigned long *)(CAN1_BASE_ADDR + 0x44))
-#define CAN1TDA2 (*(volatile unsigned long *)(CAN1_BASE_ADDR + 0x48))
-#define CAN1TDB2 (*(volatile unsigned long *)(CAN1_BASE_ADDR + 0x4C))
-#define CAN1TFI3 (*(volatile unsigned long *)(CAN1_BASE_ADDR + 0x50))
-#define CAN1TID3 (*(volatile unsigned long *)(CAN1_BASE_ADDR + 0x54))
-#define CAN1TDA3 (*(volatile unsigned long *)(CAN1_BASE_ADDR + 0x58))
-#define CAN1TDB3 (*(volatile unsigned long *)(CAN1_BASE_ADDR + 0x5C))
-
-#define CAN2_BASE_ADDR 0xE0048000
-#define CAN2MOD (*(volatile unsigned long *)(CAN2_BASE_ADDR + 0x00))
-#define CAN2CMR (*(volatile unsigned long *)(CAN2_BASE_ADDR + 0x04))
-#define CAN2GSR (*(volatile unsigned long *)(CAN2_BASE_ADDR + 0x08))
-#define CAN2ICR (*(volatile unsigned long *)(CAN2_BASE_ADDR + 0x0C))
-#define CAN2IER (*(volatile unsigned long *)(CAN2_BASE_ADDR + 0x10))
-#define CAN2BTR (*(volatile unsigned long *)(CAN2_BASE_ADDR + 0x14))
-#define CAN2EWL (*(volatile unsigned long *)(CAN2_BASE_ADDR + 0x18))
-#define CAN2SR (*(volatile unsigned long *)(CAN2_BASE_ADDR + 0x1C))
-#define CAN2RFS (*(volatile unsigned long *)(CAN2_BASE_ADDR + 0x20))
-#define CAN2RID (*(volatile unsigned long *)(CAN2_BASE_ADDR + 0x24))
-#define CAN2RDA (*(volatile unsigned long *)(CAN2_BASE_ADDR + 0x28))
-#define CAN2RDB (*(volatile unsigned long *)(CAN2_BASE_ADDR + 0x2C))
-
-#define CAN2TFI1 (*(volatile unsigned long *)(CAN2_BASE_ADDR + 0x30))
-#define CAN2TID1 (*(volatile unsigned long *)(CAN2_BASE_ADDR + 0x34))
-#define CAN2TDA1 (*(volatile unsigned long *)(CAN2_BASE_ADDR + 0x38))
-#define CAN2TDB1 (*(volatile unsigned long *)(CAN2_BASE_ADDR + 0x3C))
-#define CAN2TFI2 (*(volatile unsigned long *)(CAN2_BASE_ADDR + 0x40))
-#define CAN2TID2 (*(volatile unsigned long *)(CAN2_BASE_ADDR + 0x44))
-#define CAN2TDA2 (*(volatile unsigned long *)(CAN2_BASE_ADDR + 0x48))
-#define CAN2TDB2 (*(volatile unsigned long *)(CAN2_BASE_ADDR + 0x4C))
-#define CAN2TFI3 (*(volatile unsigned long *)(CAN2_BASE_ADDR + 0x50))
-#define CAN2TID3 (*(volatile unsigned long *)(CAN2_BASE_ADDR + 0x54))
-#define CAN2TDA3 (*(volatile unsigned long *)(CAN2_BASE_ADDR + 0x58))
-#define CAN2TDB3 (*(volatile unsigned long *)(CAN2_BASE_ADDR + 0x5C))
-
-
-/* MultiMedia Card Interface(MCI) Controller */
-#define MCI_BASE_ADDR 0xE008C000
-#define MCI_POWER (*(volatile unsigned long *)(MCI_BASE_ADDR + 0x00))
-#define MCI_CLOCK (*(volatile unsigned long *)(MCI_BASE_ADDR + 0x04))
-#define MCI_ARGUMENT (*(volatile unsigned long *)(MCI_BASE_ADDR + 0x08))
-#define MCI_COMMAND (*(volatile unsigned long *)(MCI_BASE_ADDR + 0x0C))
-#define MCI_RESP_CMD (*(volatile unsigned long *)(MCI_BASE_ADDR + 0x10))
-#define MCI_RESP0 (*(volatile unsigned long *)(MCI_BASE_ADDR + 0x14))
-#define MCI_RESP1 (*(volatile unsigned long *)(MCI_BASE_ADDR + 0x18))
-#define MCI_RESP2 (*(volatile unsigned long *)(MCI_BASE_ADDR + 0x1C))
-#define MCI_RESP3 (*(volatile unsigned long *)(MCI_BASE_ADDR + 0x20))
-#define MCI_DATA_TMR (*(volatile unsigned long *)(MCI_BASE_ADDR + 0x24))
-#define MCI_DATA_LEN (*(volatile unsigned long *)(MCI_BASE_ADDR + 0x28))
-#define MCI_DATA_CTRL (*(volatile unsigned long *)(MCI_BASE_ADDR + 0x2C))
-#define MCI_DATA_CNT (*(volatile unsigned long *)(MCI_BASE_ADDR + 0x30))
-#define MCI_STATUS (*(volatile unsigned long *)(MCI_BASE_ADDR + 0x34))
-#define MCI_CLEAR (*(volatile unsigned long *)(MCI_BASE_ADDR + 0x38))
-#define MCI_MASK0 (*(volatile unsigned long *)(MCI_BASE_ADDR + 0x3C))
-#define MCI_MASK1 (*(volatile unsigned long *)(MCI_BASE_ADDR + 0x40))
-#define MCI_FIFO_CNT (*(volatile unsigned long *)(MCI_BASE_ADDR + 0x48))
-#define MCI_FIFO (*(volatile unsigned long *)(MCI_BASE_ADDR + 0x80))
-
-
-/* I2S Interface Controller (I2S) */
-#define I2S_BASE_ADDR 0xE0088000
-#define I2S_DAO (*(volatile unsigned long *)(I2S_BASE_ADDR + 0x00))
-#define I2S_DAI (*(volatile unsigned long *)(I2S_BASE_ADDR + 0x04))
-#define I2S_TX_FIFO (*(volatile unsigned long *)(I2S_BASE_ADDR + 0x08))
-#define I2S_RX_FIFO (*(volatile unsigned long *)(I2S_BASE_ADDR + 0x0C))
-#define I2S_STATE (*(volatile unsigned long *)(I2S_BASE_ADDR + 0x10))
-#define I2S_DMA1 (*(volatile unsigned long *)(I2S_BASE_ADDR + 0x14))
-#define I2S_DMA2 (*(volatile unsigned long *)(I2S_BASE_ADDR + 0x18))
-#define I2S_IRQ (*(volatile unsigned long *)(I2S_BASE_ADDR + 0x1C))
-#define I2S_TXRATE (*(volatile unsigned long *)(I2S_BASE_ADDR + 0x20))
-#define I2S_RXRATE (*(volatile unsigned long *)(I2S_BASE_ADDR + 0x24))
-
-
-/* General-purpose DMA Controller */
-#define DMA_BASE_ADDR 0xFFE04000
-#define GPDMA_INT_STAT (*(volatile unsigned long *)(DMA_BASE_ADDR + 0x000))
-#define GPDMA_INT_TCSTAT (*(volatile unsigned long *)(DMA_BASE_ADDR + 0x004))
-#define GPDMA_INT_TCCLR (*(volatile unsigned long *)(DMA_BASE_ADDR + 0x008))
-#define GPDMA_INT_ERR_STAT (*(volatile unsigned long *)(DMA_BASE_ADDR + 0x00C))
-#define GPDMA_INT_ERR_CLR (*(volatile unsigned long *)(DMA_BASE_ADDR + 0x010))
-#define GPDMA_RAW_INT_TCSTAT (*(volatile unsigned long *)(DMA_BASE_ADDR + 0x014))
-#define GPDMA_RAW_INT_ERR_STAT (*(volatile unsigned long *)(DMA_BASE_ADDR + 0x018))
-#define GPDMA_ENABLED_CHNS (*(volatile unsigned long *)(DMA_BASE_ADDR + 0x01C))
-#define GPDMA_SOFT_BREQ (*(volatile unsigned long *)(DMA_BASE_ADDR + 0x020))
-#define GPDMA_SOFT_SREQ (*(volatile unsigned long *)(DMA_BASE_ADDR + 0x024))
-#define GPDMA_SOFT_LBREQ (*(volatile unsigned long *)(DMA_BASE_ADDR + 0x028))
-#define GPDMA_SOFT_LSREQ (*(volatile unsigned long *)(DMA_BASE_ADDR + 0x02C))
-#define GPDMA_CONFIG (*(volatile unsigned long *)(DMA_BASE_ADDR + 0x030))
-#define GPDMA_SYNC (*(volatile unsigned long *)(DMA_BASE_ADDR + 0x034))
-
-/* DMA channel 0 registers */
-#define GPDMA_CH0_SRC (*(volatile unsigned long *)(DMA_BASE_ADDR + 0x100))
-#define GPDMA_CH0_DEST (*(volatile unsigned long *)(DMA_BASE_ADDR + 0x104))
-#define GPDMA_CH0_LLI (*(volatile unsigned long *)(DMA_BASE_ADDR + 0x108))
-#define GPDMA_CH0_CTRL (*(volatile unsigned long *)(DMA_BASE_ADDR + 0x10C))
-#define GPDMA_CH0_CFG (*(volatile unsigned long *)(DMA_BASE_ADDR + 0x110))
-
-/* DMA channel 1 registers */
-#define GPDMA_CH1_SRC (*(volatile unsigned long *)(DMA_BASE_ADDR + 0x120))
-#define GPDMA_CH1_DEST (*(volatile unsigned long *)(DMA_BASE_ADDR + 0x124))
-#define GPDMA_CH1_LLI (*(volatile unsigned long *)(DMA_BASE_ADDR + 0x128))
-#define GPDMA_CH1_CTRL (*(volatile unsigned long *)(DMA_BASE_ADDR + 0x12C))
-#define GPDMA_CH1_CFG (*(volatile unsigned long *)(DMA_BASE_ADDR + 0x130))
-
-
-/* USB Controller */
-#define USB_INT_BASE_ADDR 0xE01FC1C0
-#define USB_BASE_ADDR 0xFFE0C200 /* USB Base Address */
-
-#define USB_INT_STAT (*(volatile unsigned long *)(USB_INT_BASE_ADDR + 0x00))
-
-/* USB Device Interrupt Registers */
-#define DEV_INT_STAT (*(volatile unsigned long *)(USB_BASE_ADDR + 0x00))
-#define DEV_INT_EN (*(volatile unsigned long *)(USB_BASE_ADDR + 0x04))
-#define DEV_INT_CLR (*(volatile unsigned long *)(USB_BASE_ADDR + 0x08))
-#define DEV_INT_SET (*(volatile unsigned long *)(USB_BASE_ADDR + 0x0C))
-#define DEV_INT_PRIO (*(volatile unsigned long *)(USB_BASE_ADDR + 0x2C))
-
-/* USB Device Endpoint Interrupt Registers */
-#define EP_INT_STAT (*(volatile unsigned long *)(USB_BASE_ADDR + 0x30))
-#define EP_INT_EN (*(volatile unsigned long *)(USB_BASE_ADDR + 0x34))
-#define EP_INT_CLR (*(volatile unsigned long *)(USB_BASE_ADDR + 0x38))
-#define EP_INT_SET (*(volatile unsigned long *)(USB_BASE_ADDR + 0x3C))
-#define EP_INT_PRIO (*(volatile unsigned long *)(USB_BASE_ADDR + 0x40))
-
-/* USB Device Endpoint Realization Registers */
-#define REALIZE_EP (*(volatile unsigned long *)(USB_BASE_ADDR + 0x44))
-#define EP_INDEX (*(volatile unsigned long *)(USB_BASE_ADDR + 0x48))
-#define MAXPACKET_SIZE (*(volatile unsigned long *)(USB_BASE_ADDR + 0x4C))
-
-/* USB Device Command Reagisters */
-#define CMD_CODE (*(volatile unsigned long *)(USB_BASE_ADDR + 0x10))
-#define CMD_DATA (*(volatile unsigned long *)(USB_BASE_ADDR + 0x14))
-
-/* USB Device Data Transfer Registers */
-#define RX_DATA (*(volatile unsigned long *)(USB_BASE_ADDR + 0x18))
-#define TX_DATA (*(volatile unsigned long *)(USB_BASE_ADDR + 0x1C))
-#define RX_PLENGTH (*(volatile unsigned long *)(USB_BASE_ADDR + 0x20))
-#define TX_PLENGTH (*(volatile unsigned long *)(USB_BASE_ADDR + 0x24))
-#define USB_CTRL (*(volatile unsigned long *)(USB_BASE_ADDR + 0x28))
-
-/* USB Device DMA Registers */
-#define DMA_REQ_STAT (*(volatile unsigned long *)(USB_BASE_ADDR + 0x50))
-#define DMA_REQ_CLR (*(volatile unsigned long *)(USB_BASE_ADDR + 0x54))
-#define DMA_REQ_SET (*(volatile unsigned long *)(USB_BASE_ADDR + 0x58))
-#define UDCA_HEAD (*(volatile unsigned long *)(USB_BASE_ADDR + 0x80))
-#define EP_DMA_STAT (*(volatile unsigned long *)(USB_BASE_ADDR + 0x84))
-#define EP_DMA_EN (*(volatile unsigned long *)(USB_BASE_ADDR + 0x88))
-#define EP_DMA_DIS (*(volatile unsigned long *)(USB_BASE_ADDR + 0x8C))
-#define DMA_INT_STAT (*(volatile unsigned long *)(USB_BASE_ADDR + 0x90))
-#define DMA_INT_EN (*(volatile unsigned long *)(USB_BASE_ADDR + 0x94))
-#define EOT_INT_STAT (*(volatile unsigned long *)(USB_BASE_ADDR + 0xA0))
-#define EOT_INT_CLR (*(volatile unsigned long *)(USB_BASE_ADDR + 0xA4))
-#define EOT_INT_SET (*(volatile unsigned long *)(USB_BASE_ADDR + 0xA8))
-#define NDD_REQ_INT_STAT (*(volatile unsigned long *)(USB_BASE_ADDR + 0xAC))
-#define NDD_REQ_INT_CLR (*(volatile unsigned long *)(USB_BASE_ADDR + 0xB0))
-#define NDD_REQ_INT_SET (*(volatile unsigned long *)(USB_BASE_ADDR + 0xB4))
-#define SYS_ERR_INT_STAT (*(volatile unsigned long *)(USB_BASE_ADDR + 0xB8))
-#define SYS_ERR_INT_CLR (*(volatile unsigned long *)(USB_BASE_ADDR + 0xBC))
-#define SYS_ERR_INT_SET (*(volatile unsigned long *)(USB_BASE_ADDR + 0xC0))
-
-/* USB Host and OTG registers are for LPC24xx only */
-/* USB Host Controller */
-#define USBHC_BASE_ADDR 0xFFE0C000
-#define HC_REVISION (*(volatile unsigned long *)(USBHC_BASE_ADDR + 0x00))
-#define HC_CONTROL (*(volatile unsigned long *)(USBHC_BASE_ADDR + 0x04))
-#define HC_CMD_STAT (*(volatile unsigned long *)(USBHC_BASE_ADDR + 0x08))
-#define HC_INT_STAT (*(volatile unsigned long *)(USBHC_BASE_ADDR + 0x0C))
-#define HC_INT_EN (*(volatile unsigned long *)(USBHC_BASE_ADDR + 0x10))
-#define HC_INT_DIS (*(volatile unsigned long *)(USBHC_BASE_ADDR + 0x14))
-#define HC_HCCA (*(volatile unsigned long *)(USBHC_BASE_ADDR + 0x18))
-#define HC_PERIOD_CUR_ED (*(volatile unsigned long *)(USBHC_BASE_ADDR + 0x1C))
-#define HC_CTRL_HEAD_ED (*(volatile unsigned long *)(USBHC_BASE_ADDR + 0x20))
-#define HC_CTRL_CUR_ED (*(volatile unsigned long *)(USBHC_BASE_ADDR + 0x24))
-#define HC_BULK_HEAD_ED (*(volatile unsigned long *)(USBHC_BASE_ADDR + 0x28))
-#define HC_BULK_CUR_ED (*(volatile unsigned long *)(USBHC_BASE_ADDR + 0x2C))
-#define HC_DONE_HEAD (*(volatile unsigned long *)(USBHC_BASE_ADDR + 0x30))
-#define HC_FM_INTERVAL (*(volatile unsigned long *)(USBHC_BASE_ADDR + 0x34))
-#define HC_FM_REMAINING (*(volatile unsigned long *)(USBHC_BASE_ADDR + 0x38))
-#define HC_FM_NUMBER (*(volatile unsigned long *)(USBHC_BASE_ADDR + 0x3C))
-#define HC_PERIOD_START (*(volatile unsigned long *)(USBHC_BASE_ADDR + 0x40))
-#define HC_LS_THRHLD (*(volatile unsigned long *)(USBHC_BASE_ADDR + 0x44))
-#define HC_RH_DESCA (*(volatile unsigned long *)(USBHC_BASE_ADDR + 0x48))
-#define HC_RH_DESCB (*(volatile unsigned long *)(USBHC_BASE_ADDR + 0x4C))
-#define HC_RH_STAT (*(volatile unsigned long *)(USBHC_BASE_ADDR + 0x50))
-#define HC_RH_PORT_STAT1 (*(volatile unsigned long *)(USBHC_BASE_ADDR + 0x54))
-#define HC_RH_PORT_STAT2 (*(volatile unsigned long *)(USBHC_BASE_ADDR + 0x58))
-
-/* USB OTG Controller */
-#define USBOTG_BASE_ADDR 0xFFE0C100
-#define OTG_INT_STAT (*(volatile unsigned long *)(USBOTG_BASE_ADDR + 0x00))
-#define OTG_INT_EN (*(volatile unsigned long *)(USBOTG_BASE_ADDR + 0x04))
-#define OTG_INT_SET (*(volatile unsigned long *)(USBOTG_BASE_ADDR + 0x08))
-#define OTG_INT_CLR (*(volatile unsigned long *)(USBOTG_BASE_ADDR + 0x0C))
-/* On LPC23xx, the name is USBPortSel, on LPC24xx, the name is OTG_STAT_CTRL */
-#define OTG_STAT_CTRL (*(volatile unsigned long *)(USBOTG_BASE_ADDR + 0x10))
-#define OTG_TIMER (*(volatile unsigned long *)(USBOTG_BASE_ADDR + 0x14))
-
-#define USBOTG_I2C_BASE_ADDR 0xFFE0C300
-#define OTG_I2C_RX (*(volatile unsigned long *)(USBOTG_I2C_BASE_ADDR + 0x00))
-#define OTG_I2C_TX (*(volatile unsigned long *)(USBOTG_I2C_BASE_ADDR + 0x00))
-#define OTG_I2C_STS (*(volatile unsigned long *)(USBOTG_I2C_BASE_ADDR + 0x04))
-#define OTG_I2C_CTL (*(volatile unsigned long *)(USBOTG_I2C_BASE_ADDR + 0x08))
-#define OTG_I2C_CLKHI (*(volatile unsigned long *)(USBOTG_I2C_BASE_ADDR + 0x0C))
-#define OTG_I2C_CLKLO (*(volatile unsigned long *)(USBOTG_I2C_BASE_ADDR + 0x10))
-
-/* On LPC23xx, the names are USBClkCtrl and USBClkSt; on LPC24xx, the names are
-OTG_CLK_CTRL and OTG_CLK_STAT respectively. */
-#define USBOTG_CLK_BASE_ADDR 0xFFE0CFF0
-#define OTG_CLK_CTRL (*(volatile unsigned long *)(USBOTG_CLK_BASE_ADDR + 0x04))
-#define OTG_CLK_STAT (*(volatile unsigned long *)(USBOTG_CLK_BASE_ADDR + 0x08))
-
-/* Note: below three register name convention is for LPC23xx USB device only, match
-with the spec. update in USB Device Section. */
-#define USBPortSel (*(volatile unsigned long *)(USBOTG_BASE_ADDR + 0x10))
-#define USBClkCtrl (*(volatile unsigned long *)(USBOTG_CLK_BASE_ADDR + 0x04))
-#define USBClkSt (*(volatile unsigned long *)(USBOTG_CLK_BASE_ADDR + 0x08))
-
-/* Ethernet MAC (32 bit data bus) -- all registers are RW unless indicated in parentheses */
-#define MAC_BASE_ADDR 0xFFE00000 /* AHB Peripheral # 0 */
-#define MAC_MAC1 (*(volatile unsigned long *)(MAC_BASE_ADDR + 0x000)) /* MAC config reg 1 */
-#define MAC_MAC2 (*(volatile unsigned long *)(MAC_BASE_ADDR + 0x004)) /* MAC config reg 2 */
-#define MAC_IPGT (*(volatile unsigned long *)(MAC_BASE_ADDR + 0x008)) /* b2b InterPacketGap reg */
-#define MAC_IPGR (*(volatile unsigned long *)(MAC_BASE_ADDR + 0x00C)) /* non b2b InterPacketGap reg */
-#define MAC_CLRT (*(volatile unsigned long *)(MAC_BASE_ADDR + 0x010)) /* CoLlision window/ReTry reg */
-#define MAC_MAXF (*(volatile unsigned long *)(MAC_BASE_ADDR + 0x014)) /* MAXimum Frame reg */
-#define MAC_SUPP (*(volatile unsigned long *)(MAC_BASE_ADDR + 0x018)) /* PHY SUPPort reg */
-#define MAC_TEST (*(volatile unsigned long *)(MAC_BASE_ADDR + 0x01C)) /* TEST reg */
-#define MAC_MCFG (*(volatile unsigned long *)(MAC_BASE_ADDR + 0x020)) /* MII Mgmt ConFiG reg */
-#define MAC_MCMD (*(volatile unsigned long *)(MAC_BASE_ADDR + 0x024)) /* MII Mgmt CoMmanD reg */
-#define MAC_MADR (*(volatile unsigned long *)(MAC_BASE_ADDR + 0x028)) /* MII Mgmt ADdRess reg */
-#define MAC_MWTD (*(volatile unsigned long *)(MAC_BASE_ADDR + 0x02C)) /* MII Mgmt WriTe Data reg (WO) */
-#define MAC_MRDD (*(volatile unsigned long *)(MAC_BASE_ADDR + 0x030)) /* MII Mgmt ReaD Data reg (RO) */
-#define MAC_MIND (*(volatile unsigned long *)(MAC_BASE_ADDR + 0x034)) /* MII Mgmt INDicators reg (RO) */
-
-#define MAC_SA0 (*(volatile unsigned long *)(MAC_BASE_ADDR + 0x040)) /* Station Address 0 reg */
-#define MAC_SA1 (*(volatile unsigned long *)(MAC_BASE_ADDR + 0x044)) /* Station Address 1 reg */
-#define MAC_SA2 (*(volatile unsigned long *)(MAC_BASE_ADDR + 0x048)) /* Station Address 2 reg */
-
-#define MAC_COMMAND (*(volatile unsigned long *)(MAC_BASE_ADDR + 0x100)) /* Command reg */
-#define MAC_STATUS (*(volatile unsigned long *)(MAC_BASE_ADDR + 0x104)) /* Status reg (RO) */
-#define MAC_RXDESCRIPTOR (*(volatile unsigned long *)(MAC_BASE_ADDR + 0x108)) /* Rx descriptor base address reg */
-#define MAC_RXSTATUS (*(volatile unsigned long *)(MAC_BASE_ADDR + 0x10C)) /* Rx status base address reg */
-#define MAC_RXDESCRIPTORNUM (*(volatile unsigned long *)(MAC_BASE_ADDR + 0x110)) /* Rx number of descriptors reg */
-#define MAC_RXPRODUCEINDEX (*(volatile unsigned long *)(MAC_BASE_ADDR + 0x114)) /* Rx produce index reg (RO) */
-#define MAC_RXCONSUMEINDEX (*(volatile unsigned long *)(MAC_BASE_ADDR + 0x118)) /* Rx consume index reg */
-#define MAC_TXDESCRIPTOR (*(volatile unsigned long *)(MAC_BASE_ADDR + 0x11C)) /* Tx descriptor base address reg */
-#define MAC_TXSTATUS (*(volatile unsigned long *)(MAC_BASE_ADDR + 0x120)) /* Tx status base address reg */
-#define MAC_TXDESCRIPTORNUM (*(volatile unsigned long *)(MAC_BASE_ADDR + 0x124)) /* Tx number of descriptors reg */
-#define MAC_TXPRODUCEINDEX (*(volatile unsigned long *)(MAC_BASE_ADDR + 0x128)) /* Tx produce index reg */
-#define MAC_TXCONSUMEINDEX (*(volatile unsigned long *)(MAC_BASE_ADDR + 0x12C)) /* Tx consume index reg (RO) */
-
-#define MAC_TSV0 (*(volatile unsigned long *)(MAC_BASE_ADDR + 0x158)) /* Tx status vector 0 reg (RO) */
-#define MAC_TSV1 (*(volatile unsigned long *)(MAC_BASE_ADDR + 0x15C)) /* Tx status vector 1 reg (RO) */
-#define MAC_RSV (*(volatile unsigned long *)(MAC_BASE_ADDR + 0x160)) /* Rx status vector reg (RO) */
-
-#define MAC_FLOWCONTROLCNT (*(volatile unsigned long *)(MAC_BASE_ADDR + 0x170)) /* Flow control counter reg */
-#define MAC_FLOWCONTROLSTS (*(volatile unsigned long *)(MAC_BASE_ADDR + 0x174)) /* Flow control status reg */
-
-#define MAC_RXFILTERCTRL (*(volatile unsigned long *)(MAC_BASE_ADDR + 0x200)) /* Rx filter ctrl reg */
-#define MAC_RXFILTERWOLSTS (*(volatile unsigned long *)(MAC_BASE_ADDR + 0x204)) /* Rx filter WoL status reg (RO) */
-#define MAC_RXFILTERWOLCLR (*(volatile unsigned long *)(MAC_BASE_ADDR + 0x208)) /* Rx filter WoL clear reg (WO) */
-
-#define MAC_HASHFILTERL (*(volatile unsigned long *)(MAC_BASE_ADDR + 0x210)) /* Hash filter LSBs reg */
-#define MAC_HASHFILTERH (*(volatile unsigned long *)(MAC_BASE_ADDR + 0x214)) /* Hash filter MSBs reg */
-
-#define MAC_INTSTATUS (*(volatile unsigned long *)(MAC_BASE_ADDR + 0xFE0)) /* Interrupt status reg (RO) */
-#define MAC_INTENABLE (*(volatile unsigned long *)(MAC_BASE_ADDR + 0xFE4)) /* Interrupt enable reg */
-#define MAC_INTCLEAR (*(volatile unsigned long *)(MAC_BASE_ADDR + 0xFE8)) /* Interrupt clear reg (WO) */
-#define MAC_INTSET (*(volatile unsigned long *)(MAC_BASE_ADDR + 0xFEC)) /* Interrupt set reg (WO) */
-
-#define MAC_POWERDOWN (*(volatile unsigned long *)(MAC_BASE_ADDR + 0xFF4)) /* Power-down reg */
-#define MAC_MODULEID (*(volatile unsigned long *)(MAC_BASE_ADDR + 0xFFC)) /* Module ID reg (RO) */
-
-/* LCD Controller registers */
-#define LCD_BASE_ADDR 0xFFE10000 /* AHB Peripheral # 4 */
-#define LCD_CFG (*(volatile unsigned long *)(0xE01FC1B8))
-#define LCD_TIMH (*(volatile unsigned long *)(LCD_BASE_ADDR + 0x000))
-#define LCD_TIMV (*(volatile unsigned long *)(LCD_BASE_ADDR + 0x004))
-#define LCD_POL (*(volatile unsigned long *)(LCD_BASE_ADDR + 0x008))
-#define LCD_LE (*(volatile unsigned long *)(LCD_BASE_ADDR + 0x00C))
-#define LCD_UPBASE (*(volatile unsigned long *)(LCD_BASE_ADDR + 0x010))
-#define LCD_LPBASE (*(volatile unsigned long *)(LCD_BASE_ADDR + 0x014))
-#define LCD_CTRL (*(volatile unsigned long *)(LCD_BASE_ADDR + 0x018))
-#define LCD_INTMSK (*(volatile unsigned long *)(LCD_BASE_ADDR + 0x01C))
-#define LCD_INTRAW (*(volatile unsigned long *)(LCD_BASE_ADDR + 0x020))
-#define LCD_INTSTAT (*(volatile unsigned long *)(LCD_BASE_ADDR + 0x024))
-#define LCD_INTCLR (*(volatile unsigned long *)(LCD_BASE_ADDR + 0x028))
-#define LCD_UPCURR (*(volatile unsigned long *)(LCD_BASE_ADDR + 0x02C))
-#define LCD_LPCURR (*(volatile unsigned long *)(LCD_BASE_ADDR + 0x030))
-#define LCD_PAL (*(volatile unsigned long *)(LCD_BASE_ADDR + 0x200))
-#define CRSR_IMG (*(volatile unsigned long *)(LCD_BASE_ADDR + 0x800))
-#define CRSR_CTRL (*(volatile unsigned long *)(LCD_BASE_ADDR + 0xC00))
-#define CRSR_CFG (*(volatile unsigned long *)(LCD_BASE_ADDR + 0xC04))
-#define CRSR_PAL0 (*(volatile unsigned long *)(LCD_BASE_ADDR + 0xC08))
-#define CRSR_PAL1 (*(volatile unsigned long *)(LCD_BASE_ADDR + 0xC0C))
-#define CRSR_XY (*(volatile unsigned long *)(LCD_BASE_ADDR + 0xC10))
-#define CRSR_CLIP (*(volatile unsigned long *)(LCD_BASE_ADDR + 0xC14))
-#define CRSR_INTMSK (*(volatile unsigned long *)(LCD_BASE_ADDR + 0xC20))
-#define CRSR_INTCLR (*(volatile unsigned long *)(LCD_BASE_ADDR + 0xC24))
-#define CRSR_INTRAW (*(volatile unsigned long *)(LCD_BASE_ADDR + 0xC28))
-#define CRSR_INTSTAT (*(volatile unsigned long *)(LCD_BASE_ADDR + 0xC2C))
-
-struct rt_hw_register
-{
- unsigned long r0;
- unsigned long r1;
- unsigned long r2;
- unsigned long r3;
- unsigned long r4;
- unsigned long r5;
- unsigned long r6;
- unsigned long r7;
- unsigned long r8;
- unsigned long r9;
- unsigned long r10;
- unsigned long fp;
- unsigned long ip;
- unsigned long sp;
- unsigned long lr;
- unsigned long pc;
- unsigned long cpsr;
- unsigned long ORIG_r0;
-};
-
-#ifdef __cplusplus
-}
-#endif
-
-#endif // __LPC24xx_H
-
+/* + * File : LPC2478.h + * This file is part of RT-Thread RTOS + * COPYRIGHT (C) 2006, RT-Thread Develop Team + * + * The license and distribution terms for this file may be + * found in the file LICENSE in this distribution or at + * http://openlab.rt-thread.com/license/LICENSE + * + * Change Logs: + * Date Author Notes + * 2008-12-11 xuxinming first version + */ + +#ifndef __LPC24xx_H +#define __LPC24xx_H + +#ifdef __cplusplus +extern "C" { +#endif + +#define USERMODE 0x10 +#define FIQMODE 0x11 +#define IRQMODE 0x12 +#define SVCMODE 0x13 +#define ABORTMODE 0x17 +#define UNDEFMODE 0x1b +#define MODEMASK 0x1f +#define NOINT 0xc0 + +#define MCLK (72000000) + +/* Vectored Interrupt Controller (VIC) */ +#define VIC_BASE_ADDR 0xFFFFF000 +#define VICIRQStatus (*(volatile unsigned long *)(VIC_BASE_ADDR + 0x000)) +#define VICFIQStatus (*(volatile unsigned long *)(VIC_BASE_ADDR + 0x004)) +#define VICRawIntr (*(volatile unsigned long *)(VIC_BASE_ADDR + 0x008)) +#define VICIntSelect (*(volatile unsigned long *)(VIC_BASE_ADDR + 0x00C)) +#define VICIntEnable (*(volatile unsigned long *)(VIC_BASE_ADDR + 0x010)) +#define VICIntEnClr (*(volatile unsigned long *)(VIC_BASE_ADDR + 0x014)) +#define VICSoftInt (*(volatile unsigned long *)(VIC_BASE_ADDR + 0x018)) +#define VICSoftIntClr (*(volatile unsigned long *)(VIC_BASE_ADDR + 0x01C)) +#define VICProtection (*(volatile unsigned long *)(VIC_BASE_ADDR + 0x020)) +#define VICSWPrioMask (*(volatile unsigned long *)(VIC_BASE_ADDR + 0x024)) + +#define VICVectAddr0 (*(volatile unsigned long *)(VIC_BASE_ADDR + 0x100)) +#define VICVectAddr1 (*(volatile unsigned long *)(VIC_BASE_ADDR + 0x104)) +#define VICVectAddr2 (*(volatile unsigned long *)(VIC_BASE_ADDR + 0x108)) +#define VICVectAddr3 (*(volatile unsigned long *)(VIC_BASE_ADDR + 0x10C)) +#define VICVectAddr4 (*(volatile unsigned long *)(VIC_BASE_ADDR + 0x110)) +#define VICVectAddr5 (*(volatile unsigned long *)(VIC_BASE_ADDR + 0x114)) +#define VICVectAddr6 (*(volatile unsigned long *)(VIC_BASE_ADDR + 0x118)) +#define VICVectAddr7 (*(volatile unsigned long *)(VIC_BASE_ADDR + 0x11C)) +#define VICVectAddr8 (*(volatile unsigned long *)(VIC_BASE_ADDR + 0x120)) +#define VICVectAddr9 (*(volatile unsigned long *)(VIC_BASE_ADDR + 0x124)) +#define VICVectAddr10 (*(volatile unsigned long *)(VIC_BASE_ADDR + 0x128)) +#define VICVectAddr11 (*(volatile unsigned long *)(VIC_BASE_ADDR + 0x12C)) +#define VICVectAddr12 (*(volatile unsigned long *)(VIC_BASE_ADDR + 0x130)) +#define VICVectAddr13 (*(volatile unsigned long *)(VIC_BASE_ADDR + 0x134)) +#define VICVectAddr14 (*(volatile unsigned long *)(VIC_BASE_ADDR + 0x138)) +#define VICVectAddr15 (*(volatile unsigned long *)(VIC_BASE_ADDR + 0x13C)) +#define VICVectAddr16 (*(volatile unsigned long *)(VIC_BASE_ADDR + 0x140)) +#define VICVectAddr17 (*(volatile unsigned long *)(VIC_BASE_ADDR + 0x144)) +#define VICVectAddr18 (*(volatile unsigned long *)(VIC_BASE_ADDR + 0x148)) +#define VICVectAddr19 (*(volatile unsigned long *)(VIC_BASE_ADDR + 0x14C)) +#define VICVectAddr20 (*(volatile unsigned long *)(VIC_BASE_ADDR + 0x150)) +#define VICVectAddr21 (*(volatile unsigned long *)(VIC_BASE_ADDR + 0x154)) +#define VICVectAddr22 (*(volatile unsigned long *)(VIC_BASE_ADDR + 0x158)) +#define VICVectAddr23 (*(volatile unsigned long *)(VIC_BASE_ADDR + 0x15C)) +#define VICVectAddr24 (*(volatile unsigned long *)(VIC_BASE_ADDR + 0x160)) +#define VICVectAddr25 (*(volatile unsigned long *)(VIC_BASE_ADDR + 0x164)) +#define VICVectAddr26 (*(volatile unsigned long *)(VIC_BASE_ADDR + 0x168)) +#define VICVectAddr27 (*(volatile unsigned long *)(VIC_BASE_ADDR + 0x16C)) +#define VICVectAddr28 (*(volatile unsigned long *)(VIC_BASE_ADDR + 0x170)) +#define VICVectAddr29 (*(volatile unsigned long *)(VIC_BASE_ADDR + 0x174)) +#define VICVectAddr30 (*(volatile unsigned long *)(VIC_BASE_ADDR + 0x178)) +#define VICVectAddr31 (*(volatile unsigned long *)(VIC_BASE_ADDR + 0x17C)) + +/* The name convention below is from previous LPC2000 family MCUs, in LPC23xx/24xx, +these registers are known as "VICVectPriority(x)". */ +#define VICVectCntl0 (*(volatile unsigned long *)(VIC_BASE_ADDR + 0x200)) +#define VICVectCntl1 (*(volatile unsigned long *)(VIC_BASE_ADDR + 0x204)) +#define VICVectCntl2 (*(volatile unsigned long *)(VIC_BASE_ADDR + 0x208)) +#define VICVectCntl3 (*(volatile unsigned long *)(VIC_BASE_ADDR + 0x20C)) +#define VICVectCntl4 (*(volatile unsigned long *)(VIC_BASE_ADDR + 0x210)) +#define VICVectCntl5 (*(volatile unsigned long *)(VIC_BASE_ADDR + 0x214)) +#define VICVectCntl6 (*(volatile unsigned long *)(VIC_BASE_ADDR + 0x218)) +#define VICVectCntl7 (*(volatile unsigned long *)(VIC_BASE_ADDR + 0x21C)) +#define VICVectCntl8 (*(volatile unsigned long *)(VIC_BASE_ADDR + 0x220)) +#define VICVectCntl9 (*(volatile unsigned long *)(VIC_BASE_ADDR + 0x224)) +#define VICVectCntl10 (*(volatile unsigned long *)(VIC_BASE_ADDR + 0x228)) +#define VICVectCntl11 (*(volatile unsigned long *)(VIC_BASE_ADDR + 0x22C)) +#define VICVectCntl12 (*(volatile unsigned long *)(VIC_BASE_ADDR + 0x230)) +#define VICVectCntl13 (*(volatile unsigned long *)(VIC_BASE_ADDR + 0x234)) +#define VICVectCntl14 (*(volatile unsigned long *)(VIC_BASE_ADDR + 0x238)) +#define VICVectCntl15 (*(volatile unsigned long *)(VIC_BASE_ADDR + 0x23C)) +#define VICVectCntl16 (*(volatile unsigned long *)(VIC_BASE_ADDR + 0x240)) +#define VICVectCntl17 (*(volatile unsigned long *)(VIC_BASE_ADDR + 0x244)) +#define VICVectCntl18 (*(volatile unsigned long *)(VIC_BASE_ADDR + 0x248)) +#define VICVectCntl19 (*(volatile unsigned long *)(VIC_BASE_ADDR + 0x24C)) +#define VICVectCntl20 (*(volatile unsigned long *)(VIC_BASE_ADDR + 0x250)) +#define VICVectCntl21 (*(volatile unsigned long *)(VIC_BASE_ADDR + 0x254)) +#define VICVectCntl22 (*(volatile unsigned long *)(VIC_BASE_ADDR + 0x258)) +#define VICVectCntl23 (*(volatile unsigned long *)(VIC_BASE_ADDR + 0x25C)) +#define VICVectCntl24 (*(volatile unsigned long *)(VIC_BASE_ADDR + 0x260)) +#define VICVectCntl25 (*(volatile unsigned long *)(VIC_BASE_ADDR + 0x264)) +#define VICVectCntl26 (*(volatile unsigned long *)(VIC_BASE_ADDR + 0x268)) +#define VICVectCntl27 (*(volatile unsigned long *)(VIC_BASE_ADDR + 0x26C)) +#define VICVectCntl28 (*(volatile unsigned long *)(VIC_BASE_ADDR + 0x270)) +#define VICVectCntl29 (*(volatile unsigned long *)(VIC_BASE_ADDR + 0x274)) +#define VICVectCntl30 (*(volatile unsigned long *)(VIC_BASE_ADDR + 0x278)) +#define VICVectCntl31 (*(volatile unsigned long *)(VIC_BASE_ADDR + 0x27C)) + +#define VICVectAddr (*(volatile unsigned long *)(VIC_BASE_ADDR + 0xF00)) + + +/* Pin Connect Block */ +#define PINSEL_BASE_ADDR 0xE002C000 +#define PINSEL0 (*(volatile unsigned long *)(PINSEL_BASE_ADDR + 0x00)) +#define PINSEL1 (*(volatile unsigned long *)(PINSEL_BASE_ADDR + 0x04)) +#define PINSEL2 (*(volatile unsigned long *)(PINSEL_BASE_ADDR + 0x08)) +#define PINSEL3 (*(volatile unsigned long *)(PINSEL_BASE_ADDR + 0x0C)) +#define PINSEL4 (*(volatile unsigned long *)(PINSEL_BASE_ADDR + 0x10)) +#define PINSEL5 (*(volatile unsigned long *)(PINSEL_BASE_ADDR + 0x14)) +#define PINSEL6 (*(volatile unsigned long *)(PINSEL_BASE_ADDR + 0x18)) +#define PINSEL7 (*(volatile unsigned long *)(PINSEL_BASE_ADDR + 0x1C)) +#define PINSEL8 (*(volatile unsigned long *)(PINSEL_BASE_ADDR + 0x20)) +#define PINSEL9 (*(volatile unsigned long *)(PINSEL_BASE_ADDR + 0x24)) +#define PINSEL10 (*(volatile unsigned long *)(PINSEL_BASE_ADDR + 0x28)) +#define PINSEL11 (*(volatile unsigned long *)(PINSEL_BASE_ADDR + 0x2C)) + +#define PINMODE0 (*(volatile unsigned long *)(PINSEL_BASE_ADDR + 0x40)) +#define PINMODE1 (*(volatile unsigned long *)(PINSEL_BASE_ADDR + 0x44)) +#define PINMODE2 (*(volatile unsigned long *)(PINSEL_BASE_ADDR + 0x48)) +#define PINMODE3 (*(volatile unsigned long *)(PINSEL_BASE_ADDR + 0x4C)) +#define PINMODE4 (*(volatile unsigned long *)(PINSEL_BASE_ADDR + 0x50)) +#define PINMODE5 (*(volatile unsigned long *)(PINSEL_BASE_ADDR + 0x54)) +#define PINMODE6 (*(volatile unsigned long *)(PINSEL_BASE_ADDR + 0x58)) +#define PINMODE7 (*(volatile unsigned long *)(PINSEL_BASE_ADDR + 0x5C)) +#define PINMODE8 (*(volatile unsigned long *)(PINSEL_BASE_ADDR + 0x60)) +#define PINMODE9 (*(volatile unsigned long *)(PINSEL_BASE_ADDR + 0x64)) + +/* General Purpose Input/Output (GPIO) */ +#define GPIO_BASE_ADDR 0xE0028000 +#define IOPIN0 (*(volatile unsigned long *)(GPIO_BASE_ADDR + 0x00)) +#define IOSET0 (*(volatile unsigned long *)(GPIO_BASE_ADDR + 0x04)) +#define IODIR0 (*(volatile unsigned long *)(GPIO_BASE_ADDR + 0x08)) +#define IOCLR0 (*(volatile unsigned long *)(GPIO_BASE_ADDR + 0x0C)) +#define IOPIN1 (*(volatile unsigned long *)(GPIO_BASE_ADDR + 0x10)) +#define IOSET1 (*(volatile unsigned long *)(GPIO_BASE_ADDR + 0x14)) +#define IODIR1 (*(volatile unsigned long *)(GPIO_BASE_ADDR + 0x18)) +#define IOCLR1 (*(volatile unsigned long *)(GPIO_BASE_ADDR + 0x1C)) + +/* GPIO Interrupt Registers */ +#define IO0_INT_EN_R (*(volatile unsigned long *)(GPIO_BASE_ADDR + 0x90)) +#define IO0_INT_EN_F (*(volatile unsigned long *)(GPIO_BASE_ADDR + 0x94)) +#define IO0_INT_STAT_R (*(volatile unsigned long *)(GPIO_BASE_ADDR + 0x84)) +#define IO0_INT_STAT_F (*(volatile unsigned long *)(GPIO_BASE_ADDR + 0x88)) +#define IO0_INT_CLR (*(volatile unsigned long *)(GPIO_BASE_ADDR + 0x8C)) + +#define IO2_INT_EN_R (*(volatile unsigned long *)(GPIO_BASE_ADDR + 0xB0)) +#define IO2_INT_EN_F (*(volatile unsigned long *)(GPIO_BASE_ADDR + 0xB4)) +#define IO2_INT_STAT_R (*(volatile unsigned long *)(GPIO_BASE_ADDR + 0xA4)) +#define IO2_INT_STAT_F (*(volatile unsigned long *)(GPIO_BASE_ADDR + 0xA8)) +#define IO2_INT_CLR (*(volatile unsigned long *)(GPIO_BASE_ADDR + 0xAC)) + +#define IO_INT_STAT (*(volatile unsigned long *)(GPIO_BASE_ADDR + 0x80)) + +#define PARTCFG_BASE_ADDR 0x3FFF8000 +#define PARTCFG (*(volatile unsigned long *)(PARTCFG_BASE_ADDR + 0x00)) + +/* Fast I/O setup */ +#define FIO_BASE_ADDR 0x3FFFC000 +#define FIO0DIR (*(volatile unsigned long *)(FIO_BASE_ADDR + 0x00)) +#define FIO0MASK (*(volatile unsigned long *)(FIO_BASE_ADDR + 0x10)) +#define FIO0PIN (*(volatile unsigned long *)(FIO_BASE_ADDR + 0x14)) +#define FIO0SET (*(volatile unsigned long *)(FIO_BASE_ADDR + 0x18)) +#define FIO0CLR (*(volatile unsigned long *)(FIO_BASE_ADDR + 0x1C)) + +#define FIO1DIR (*(volatile unsigned long *)(FIO_BASE_ADDR + 0x20)) +#define FIO1MASK (*(volatile unsigned long *)(FIO_BASE_ADDR + 0x30)) +#define FIO1PIN (*(volatile unsigned long *)(FIO_BASE_ADDR + 0x34)) +#define FIO1SET (*(volatile unsigned long *)(FIO_BASE_ADDR + 0x38)) +#define FIO1CLR (*(volatile unsigned long *)(FIO_BASE_ADDR + 0x3C)) + +#define FIO2DIR (*(volatile unsigned long *)(FIO_BASE_ADDR + 0x40)) +#define FIO2MASK (*(volatile unsigned long *)(FIO_BASE_ADDR + 0x50)) +#define FIO2PIN (*(volatile unsigned long *)(FIO_BASE_ADDR + 0x54)) +#define FIO2SET (*(volatile unsigned long *)(FIO_BASE_ADDR + 0x58)) +#define FIO2CLR (*(volatile unsigned long *)(FIO_BASE_ADDR + 0x5C)) + +#define FIO3DIR (*(volatile unsigned long *)(FIO_BASE_ADDR + 0x60)) +#define FIO3MASK (*(volatile unsigned long *)(FIO_BASE_ADDR + 0x70)) +#define FIO3PIN (*(volatile unsigned long *)(FIO_BASE_ADDR + 0x74)) +#define FIO3SET (*(volatile unsigned long *)(FIO_BASE_ADDR + 0x78)) +#define FIO3CLR (*(volatile unsigned long *)(FIO_BASE_ADDR + 0x7C)) + +#define FIO4DIR (*(volatile unsigned long *)(FIO_BASE_ADDR + 0x80)) +#define FIO4MASK (*(volatile unsigned long *)(FIO_BASE_ADDR + 0x90)) +#define FIO4PIN (*(volatile unsigned long *)(FIO_BASE_ADDR + 0x94)) +#define FIO4SET (*(volatile unsigned long *)(FIO_BASE_ADDR + 0x98)) +#define FIO4CLR (*(volatile unsigned long *)(FIO_BASE_ADDR + 0x9C)) + +/* FIOs can be accessed through WORD, HALF-WORD or BYTE. */ +#define FIO0DIR0 (*(volatile unsigned char *)(FIO_BASE_ADDR + 0x00)) +#define FIO1DIR0 (*(volatile unsigned char *)(FIO_BASE_ADDR + 0x20)) +#define FIO2DIR0 (*(volatile unsigned char *)(FIO_BASE_ADDR + 0x40)) +#define FIO3DIR0 (*(volatile unsigned char *)(FIO_BASE_ADDR + 0x60)) +#define FIO4DIR0 (*(volatile unsigned char *)(FIO_BASE_ADDR + 0x80)) + +#define FIO0DIR1 (*(volatile unsigned char *)(FIO_BASE_ADDR + 0x01)) +#define FIO1DIR1 (*(volatile unsigned char *)(FIO_BASE_ADDR + 0x21)) +#define FIO2DIR1 (*(volatile unsigned char *)(FIO_BASE_ADDR + 0x41)) +#define FIO3DIR1 (*(volatile unsigned char *)(FIO_BASE_ADDR + 0x61)) +#define FIO4DIR1 (*(volatile unsigned char *)(FIO_BASE_ADDR + 0x81)) + +#define FIO0DIR2 (*(volatile unsigned char *)(FIO_BASE_ADDR + 0x02)) +#define FIO1DIR2 (*(volatile unsigned char *)(FIO_BASE_ADDR + 0x22)) +#define FIO2DIR2 (*(volatile unsigned char *)(FIO_BASE_ADDR + 0x42)) +#define FIO3DIR2 (*(volatile unsigned char *)(FIO_BASE_ADDR + 0x62)) +#define FIO4DIR2 (*(volatile unsigned char *)(FIO_BASE_ADDR + 0x82)) + +#define FIO0DIR3 (*(volatile unsigned char *)(FIO_BASE_ADDR + 0x03)) +#define FIO1DIR3 (*(volatile unsigned char *)(FIO_BASE_ADDR + 0x23)) +#define FIO2DIR3 (*(volatile unsigned char *)(FIO_BASE_ADDR + 0x43)) +#define FIO3DIR3 (*(volatile unsigned char *)(FIO_BASE_ADDR + 0x63)) +#define FIO4DIR3 (*(volatile unsigned char *)(FIO_BASE_ADDR + 0x83)) + +#define FIO0DIRL (*(volatile unsigned short *)(FIO_BASE_ADDR + 0x00)) +#define FIO1DIRL (*(volatile unsigned short *)(FIO_BASE_ADDR + 0x20)) +#define FIO2DIRL (*(volatile unsigned short *)(FIO_BASE_ADDR + 0x40)) +#define FIO3DIRL (*(volatile unsigned short *)(FIO_BASE_ADDR + 0x60)) +#define FIO4DIRL (*(volatile unsigned short *)(FIO_BASE_ADDR + 0x80)) + +#define FIO0DIRU (*(volatile unsigned short *)(FIO_BASE_ADDR + 0x02)) +#define FIO1DIRU (*(volatile unsigned short *)(FIO_BASE_ADDR + 0x22)) +#define FIO2DIRU (*(volatile unsigned short *)(FIO_BASE_ADDR + 0x42)) +#define FIO3DIRU (*(volatile unsigned short *)(FIO_BASE_ADDR + 0x62)) +#define FIO4DIRU (*(volatile unsigned short *)(FIO_BASE_ADDR + 0x82)) + +#define FIO0MASK0 (*(volatile unsigned char *)(FIO_BASE_ADDR + 0x10)) +#define FIO1MASK0 (*(volatile unsigned char *)(FIO_BASE_ADDR + 0x30)) +#define FIO2MASK0 (*(volatile unsigned char *)(FIO_BASE_ADDR + 0x50)) +#define FIO3MASK0 (*(volatile unsigned char *)(FIO_BASE_ADDR + 0x70)) +#define FIO4MASK0 (*(volatile unsigned char *)(FIO_BASE_ADDR + 0x90)) + +#define FIO0MASK1 (*(volatile unsigned char *)(FIO_BASE_ADDR + 0x11)) +#define FIO1MASK1 (*(volatile unsigned char *)(FIO_BASE_ADDR + 0x21)) +#define FIO2MASK1 (*(volatile unsigned char *)(FIO_BASE_ADDR + 0x51)) +#define FIO3MASK1 (*(volatile unsigned char *)(FIO_BASE_ADDR + 0x71)) +#define FIO4MASK1 (*(volatile unsigned char *)(FIO_BASE_ADDR + 0x91)) + +#define FIO0MASK2 (*(volatile unsigned char *)(FIO_BASE_ADDR + 0x12)) +#define FIO1MASK2 (*(volatile unsigned char *)(FIO_BASE_ADDR + 0x32)) +#define FIO2MASK2 (*(volatile unsigned char *)(FIO_BASE_ADDR + 0x52)) +#define FIO3MASK2 (*(volatile unsigned char *)(FIO_BASE_ADDR + 0x72)) +#define FIO4MASK2 (*(volatile unsigned char *)(FIO_BASE_ADDR + 0x92)) + +#define FIO0MASK3 (*(volatile unsigned char *)(FIO_BASE_ADDR + 0x13)) +#define FIO1MASK3 (*(volatile unsigned char *)(FIO_BASE_ADDR + 0x33)) +#define FIO2MASK3 (*(volatile unsigned char *)(FIO_BASE_ADDR + 0x53)) +#define FIO3MASK3 (*(volatile unsigned char *)(FIO_BASE_ADDR + 0x73)) +#define FIO4MASK3 (*(volatile unsigned char *)(FIO_BASE_ADDR + 0x93)) + +#define FIO0MASKL (*(volatile unsigned short *)(FIO_BASE_ADDR + 0x10)) +#define FIO1MASKL (*(volatile unsigned short *)(FIO_BASE_ADDR + 0x30)) +#define FIO2MASKL (*(volatile unsigned short *)(FIO_BASE_ADDR + 0x50)) +#define FIO3MASKL (*(volatile unsigned short *)(FIO_BASE_ADDR + 0x70)) +#define FIO4MASKL (*(volatile unsigned short *)(FIO_BASE_ADDR + 0x90)) + +#define FIO0MASKU (*(volatile unsigned short *)(FIO_BASE_ADDR + 0x12)) +#define FIO1MASKU (*(volatile unsigned short *)(FIO_BASE_ADDR + 0x32)) +#define FIO2MASKU (*(volatile unsigned short *)(FIO_BASE_ADDR + 0x52)) +#define FIO3MASKU (*(volatile unsigned short *)(FIO_BASE_ADDR + 0x72)) +#define FIO4MASKU (*(volatile unsigned short *)(FIO_BASE_ADDR + 0x92)) + +#define FIO0PIN0 (*(volatile unsigned char *)(FIO_BASE_ADDR + 0x14)) +#define FIO1PIN0 (*(volatile unsigned char *)(FIO_BASE_ADDR + 0x34)) +#define FIO2PIN0 (*(volatile unsigned char *)(FIO_BASE_ADDR + 0x54)) +#define FIO3PIN0 (*(volatile unsigned char *)(FIO_BASE_ADDR + 0x74)) +#define FIO4PIN0 (*(volatile unsigned char *)(FIO_BASE_ADDR + 0x94)) + +#define FIO0PIN1 (*(volatile unsigned char *)(FIO_BASE_ADDR + 0x15)) +#define FIO1PIN1 (*(volatile unsigned char *)(FIO_BASE_ADDR + 0x35)) +#define FIO2PIN1 (*(volatile unsigned char *)(FIO_BASE_ADDR + 0x55)) +#define FIO3PIN1 (*(volatile unsigned char *)(FIO_BASE_ADDR + 0x75)) +#define FIO4PIN1 (*(volatile unsigned char *)(FIO_BASE_ADDR + 0x95)) + +#define FIO0PIN2 (*(volatile unsigned char *)(FIO_BASE_ADDR + 0x16)) +#define FIO1PIN2 (*(volatile unsigned char *)(FIO_BASE_ADDR + 0x36)) +#define FIO2PIN2 (*(volatile unsigned char *)(FIO_BASE_ADDR + 0x56)) +#define FIO3PIN2 (*(volatile unsigned char *)(FIO_BASE_ADDR + 0x76)) +#define FIO4PIN2 (*(volatile unsigned char *)(FIO_BASE_ADDR + 0x96)) + +#define FIO0PIN3 (*(volatile unsigned char *)(FIO_BASE_ADDR + 0x17)) +#define FIO1PIN3 (*(volatile unsigned char *)(FIO_BASE_ADDR + 0x37)) +#define FIO2PIN3 (*(volatile unsigned char *)(FIO_BASE_ADDR + 0x57)) +#define FIO3PIN3 (*(volatile unsigned char *)(FIO_BASE_ADDR + 0x77)) +#define FIO4PIN3 (*(volatile unsigned char *)(FIO_BASE_ADDR + 0x97)) + +#define FIO0PINL (*(volatile unsigned short *)(FIO_BASE_ADDR + 0x14)) +#define FIO1PINL (*(volatile unsigned short *)(FIO_BASE_ADDR + 0x34)) +#define FIO2PINL (*(volatile unsigned short *)(FIO_BASE_ADDR + 0x54)) +#define FIO3PINL (*(volatile unsigned short *)(FIO_BASE_ADDR + 0x74)) +#define FIO4PINL (*(volatile unsigned short *)(FIO_BASE_ADDR + 0x94)) + +#define FIO0PINU (*(volatile unsigned short *)(FIO_BASE_ADDR + 0x16)) +#define FIO1PINU (*(volatile unsigned short *)(FIO_BASE_ADDR + 0x36)) +#define FIO2PINU (*(volatile unsigned short *)(FIO_BASE_ADDR + 0x56)) +#define FIO3PINU (*(volatile unsigned short *)(FIO_BASE_ADDR + 0x76)) +#define FIO4PINU (*(volatile unsigned short *)(FIO_BASE_ADDR + 0x96)) + +#define FIO0SET0 (*(volatile unsigned char *)(FIO_BASE_ADDR + 0x18)) +#define FIO1SET0 (*(volatile unsigned char *)(FIO_BASE_ADDR + 0x38)) +#define FIO2SET0 (*(volatile unsigned char *)(FIO_BASE_ADDR + 0x58)) +#define FIO3SET0 (*(volatile unsigned char *)(FIO_BASE_ADDR + 0x78)) +#define FIO4SET0 (*(volatile unsigned char *)(FIO_BASE_ADDR + 0x98)) + +#define FIO0SET1 (*(volatile unsigned char *)(FIO_BASE_ADDR + 0x19)) +#define FIO1SET1 (*(volatile unsigned char *)(FIO_BASE_ADDR + 0x29)) +#define FIO2SET1 (*(volatile unsigned char *)(FIO_BASE_ADDR + 0x59)) +#define FIO3SET1 (*(volatile unsigned char *)(FIO_BASE_ADDR + 0x79)) +#define FIO4SET1 (*(volatile unsigned char *)(FIO_BASE_ADDR + 0x99)) + +#define FIO0SET2 (*(volatile unsigned char *)(FIO_BASE_ADDR + 0x1A)) +#define FIO1SET2 (*(volatile unsigned char *)(FIO_BASE_ADDR + 0x3A)) +#define FIO2SET2 (*(volatile unsigned char *)(FIO_BASE_ADDR + 0x5A)) +#define FIO3SET2 (*(volatile unsigned char *)(FIO_BASE_ADDR + 0x7A)) +#define FIO4SET2 (*(volatile unsigned char *)(FIO_BASE_ADDR + 0x9A)) + +#define FIO0SET3 (*(volatile unsigned char *)(FIO_BASE_ADDR + 0x1B)) +#define FIO1SET3 (*(volatile unsigned char *)(FIO_BASE_ADDR + 0x3B)) +#define FIO2SET3 (*(volatile unsigned char *)(FIO_BASE_ADDR + 0x5B)) +#define FIO3SET3 (*(volatile unsigned char *)(FIO_BASE_ADDR + 0x7B)) +#define FIO4SET3 (*(volatile unsigned char *)(FIO_BASE_ADDR + 0x9B)) + +#define FIO0SETL (*(volatile unsigned short *)(FIO_BASE_ADDR + 0x18)) +#define FIO1SETL (*(volatile unsigned short *)(FIO_BASE_ADDR + 0x38)) +#define FIO2SETL (*(volatile unsigned short *)(FIO_BASE_ADDR + 0x58)) +#define FIO3SETL (*(volatile unsigned short *)(FIO_BASE_ADDR + 0x78)) +#define FIO4SETL (*(volatile unsigned short *)(FIO_BASE_ADDR + 0x98)) + +#define FIO0SETU (*(volatile unsigned short *)(FIO_BASE_ADDR + 0x1A)) +#define FIO1SETU (*(volatile unsigned short *)(FIO_BASE_ADDR + 0x3A)) +#define FIO2SETU (*(volatile unsigned short *)(FIO_BASE_ADDR + 0x5A)) +#define FIO3SETU (*(volatile unsigned short *)(FIO_BASE_ADDR + 0x7A)) +#define FIO4SETU (*(volatile unsigned short *)(FIO_BASE_ADDR + 0x9A)) + +#define FIO0CLR0 (*(volatile unsigned char *)(FIO_BASE_ADDR + 0x1C)) +#define FIO1CLR0 (*(volatile unsigned char *)(FIO_BASE_ADDR + 0x3C)) +#define FIO2CLR0 (*(volatile unsigned char *)(FIO_BASE_ADDR + 0x5C)) +#define FIO3CLR0 (*(volatile unsigned char *)(FIO_BASE_ADDR + 0x7C)) +#define FIO4CLR0 (*(volatile unsigned char *)(FIO_BASE_ADDR + 0x9C)) + +#define FIO0CLR1 (*(volatile unsigned char *)(FIO_BASE_ADDR + 0x1D)) +#define FIO1CLR1 (*(volatile unsigned char *)(FIO_BASE_ADDR + 0x2D)) +#define FIO2CLR1 (*(volatile unsigned char *)(FIO_BASE_ADDR + 0x5D)) +#define FIO3CLR1 (*(volatile unsigned char *)(FIO_BASE_ADDR + 0x7D)) +#define FIO4CLR1 (*(volatile unsigned char *)(FIO_BASE_ADDR + 0x9D)) + +#define FIO0CLR2 (*(volatile unsigned char *)(FIO_BASE_ADDR + 0x1E)) +#define FIO1CLR2 (*(volatile unsigned char *)(FIO_BASE_ADDR + 0x3E)) +#define FIO2CLR2 (*(volatile unsigned char *)(FIO_BASE_ADDR + 0x5E)) +#define FIO3CLR2 (*(volatile unsigned char *)(FIO_BASE_ADDR + 0x7E)) +#define FIO4CLR2 (*(volatile unsigned char *)(FIO_BASE_ADDR + 0x9E)) + +#define FIO0CLR3 (*(volatile unsigned char *)(FIO_BASE_ADDR + 0x1F)) +#define FIO1CLR3 (*(volatile unsigned char *)(FIO_BASE_ADDR + 0x3F)) +#define FIO2CLR3 (*(volatile unsigned char *)(FIO_BASE_ADDR + 0x5F)) +#define FIO3CLR3 (*(volatile unsigned char *)(FIO_BASE_ADDR + 0x7F)) +#define FIO4CLR3 (*(volatile unsigned char *)(FIO_BASE_ADDR + 0x9F)) + +#define FIO0CLRL (*(volatile unsigned short *)(FIO_BASE_ADDR + 0x1C)) +#define FIO1CLRL (*(volatile unsigned short *)(FIO_BASE_ADDR + 0x3C)) +#define FIO2CLRL (*(volatile unsigned short *)(FIO_BASE_ADDR + 0x5C)) +#define FIO3CLRL (*(volatile unsigned short *)(FIO_BASE_ADDR + 0x7C)) +#define FIO4CLRL (*(volatile unsigned short *)(FIO_BASE_ADDR + 0x9C)) + +#define FIO0CLRU (*(volatile unsigned short *)(FIO_BASE_ADDR + 0x1E)) +#define FIO1CLRU (*(volatile unsigned short *)(FIO_BASE_ADDR + 0x3E)) +#define FIO2CLRU (*(volatile unsigned short *)(FIO_BASE_ADDR + 0x5E)) +#define FIO3CLRU (*(volatile unsigned short *)(FIO_BASE_ADDR + 0x7E)) +#define FIO4CLRU (*(volatile unsigned short *)(FIO_BASE_ADDR + 0x9E)) + + +/* System Control Block(SCB) modules include Memory Accelerator Module, +Phase Locked Loop, VPB divider, Power Control, External Interrupt, +Reset, and Code Security/Debugging */ +#define SCB_BASE_ADDR 0xE01FC000 + +/* Memory Accelerator Module (MAM) */ +#define MAMCR (*(volatile unsigned long *)(SCB_BASE_ADDR + 0x000)) +#define MAMTIM (*(volatile unsigned long *)(SCB_BASE_ADDR + 0x004)) +#define MEMMAP (*(volatile unsigned long *)(SCB_BASE_ADDR + 0x040)) + +/* Phase Locked Loop (PLL) */ +#define PLLCON (*(volatile unsigned long *)(SCB_BASE_ADDR + 0x080)) +#define PLLCFG (*(volatile unsigned long *)(SCB_BASE_ADDR + 0x084)) +#define PLLSTAT (*(volatile unsigned long *)(SCB_BASE_ADDR + 0x088)) +#define PLLFEED (*(volatile unsigned long *)(SCB_BASE_ADDR + 0x08C)) + +/* Power Control */ +#define PCON (*(volatile unsigned long *)(SCB_BASE_ADDR + 0x0C0)) +#define PCONP (*(volatile unsigned long *)(SCB_BASE_ADDR + 0x0C4)) + +/* Clock Divider */ +#define CCLKCFG (*(volatile unsigned long *)(SCB_BASE_ADDR + 0x104)) +#define USBCLKCFG (*(volatile unsigned long *)(SCB_BASE_ADDR + 0x108)) +#define CLKSRCSEL (*(volatile unsigned long *)(SCB_BASE_ADDR + 0x10C)) +#define PCLKSEL0 (*(volatile unsigned long *)(SCB_BASE_ADDR + 0x1A8)) +#define PCLKSEL1 (*(volatile unsigned long *)(SCB_BASE_ADDR + 0x1AC)) + +/* External Interrupts */ +#define EXTINT (*(volatile unsigned long *)(SCB_BASE_ADDR + 0x140)) +#define INTWAKE (*(volatile unsigned long *)(SCB_BASE_ADDR + 0x144)) +#define EXTMODE (*(volatile unsigned long *)(SCB_BASE_ADDR + 0x148)) +#define EXTPOLAR (*(volatile unsigned long *)(SCB_BASE_ADDR + 0x14C)) + +/* Reset, reset source identification */ +#define RSIR (*(volatile unsigned long *)(SCB_BASE_ADDR + 0x180)) + +/* RSID, code security protection */ +#define CSPR (*(volatile unsigned long *)(SCB_BASE_ADDR + 0x184)) + +/* AHB configuration */ +#define AHBCFG1 (*(volatile unsigned long *)(SCB_BASE_ADDR + 0x188)) +#define AHBCFG2 (*(volatile unsigned long *)(SCB_BASE_ADDR + 0x18C)) + +/* System Controls and Status */ +#define SCS (*(volatile unsigned long *)(SCB_BASE_ADDR + 0x1A0)) + +/* MPMC(EMC) registers, note: all the external memory controller(EMC) registers +are for LPC24xx only. */ +#define STATIC_MEM0_BASE 0x80000000 +#define STATIC_MEM1_BASE 0x81000000 +#define STATIC_MEM2_BASE 0x82000000 +#define STATIC_MEM3_BASE 0x83000000 + +#define DYNAMIC_MEM0_BASE 0xA0000000 +#define DYNAMIC_MEM1_BASE 0xB0000000 +#define DYNAMIC_MEM2_BASE 0xC0000000 +#define DYNAMIC_MEM3_BASE 0xD0000000 + +/* External Memory Controller (EMC) */ +#define EMC_BASE_ADDR 0xFFE08000 +#define EMC_CTRL (*(volatile unsigned long *)(EMC_BASE_ADDR + 0x000)) +#define EMC_STAT (*(volatile unsigned long *)(EMC_BASE_ADDR + 0x004)) +#define EMC_CONFIG (*(volatile unsigned long *)(EMC_BASE_ADDR + 0x008)) + +/* Dynamic RAM access registers */ +#define EMC_DYN_CTRL (*(volatile unsigned long *)(EMC_BASE_ADDR + 0x020)) +#define EMC_DYN_RFSH (*(volatile unsigned long *)(EMC_BASE_ADDR + 0x024)) +#define EMC_DYN_RD_CFG (*(volatile unsigned long *)(EMC_BASE_ADDR + 0x028)) +#define EMC_DYN_RP (*(volatile unsigned long *)(EMC_BASE_ADDR + 0x030)) +#define EMC_DYN_RAS (*(volatile unsigned long *)(EMC_BASE_ADDR + 0x034)) +#define EMC_DYN_SREX (*(volatile unsigned long *)(EMC_BASE_ADDR + 0x038)) +#define EMC_DYN_APR (*(volatile unsigned long *)(EMC_BASE_ADDR + 0x03C)) +#define EMC_DYN_DAL (*(volatile unsigned long *)(EMC_BASE_ADDR + 0x040)) +#define EMC_DYN_WR (*(volatile unsigned long *)(EMC_BASE_ADDR + 0x044)) +#define EMC_DYN_RC (*(volatile unsigned long *)(EMC_BASE_ADDR + 0x048)) +#define EMC_DYN_RFC (*(volatile unsigned long *)(EMC_BASE_ADDR + 0x04C)) +#define EMC_DYN_XSR (*(volatile unsigned long *)(EMC_BASE_ADDR + 0x050)) +#define EMC_DYN_RRD (*(volatile unsigned long *)(EMC_BASE_ADDR + 0x054)) +#define EMC_DYN_MRD (*(volatile unsigned long *)(EMC_BASE_ADDR + 0x058)) + +#define EMC_DYN_CFG0 (*(volatile unsigned long *)(EMC_BASE_ADDR + 0x100)) +#define EMC_DYN_RASCAS0 (*(volatile unsigned long *)(EMC_BASE_ADDR + 0x104)) +#define EMC_DYN_CFG1 (*(volatile unsigned long *)(EMC_BASE_ADDR + 0x140)) +#define EMC_DYN_RASCAS1 (*(volatile unsigned long *)(EMC_BASE_ADDR + 0x144)) +#define EMC_DYN_CFG2 (*(volatile unsigned long *)(EMC_BASE_ADDR + 0x160)) +#define EMC_DYN_RASCAS2 (*(volatile unsigned long *)(EMC_BASE_ADDR + 0x164)) +#define EMC_DYN_CFG3 (*(volatile unsigned long *)(EMC_BASE_ADDR + 0x180)) +#define EMC_DYN_RASCAS3 (*(volatile unsigned long *)(EMC_BASE_ADDR + 0x184)) + +/* static RAM access registers */ +#define EMC_STA_CFG0 (*(volatile unsigned long *)(EMC_BASE_ADDR + 0x200)) +#define EMC_STA_WAITWEN0 (*(volatile unsigned long *)(EMC_BASE_ADDR + 0x204)) +#define EMC_STA_WAITOEN0 (*(volatile unsigned long *)(EMC_BASE_ADDR + 0x208)) +#define EMC_STA_WAITRD0 (*(volatile unsigned long *)(EMC_BASE_ADDR + 0x20C)) +#define EMC_STA_WAITPAGE0 (*(volatile unsigned long *)(EMC_BASE_ADDR + 0x210)) +#define EMC_STA_WAITWR0 (*(volatile unsigned long *)(EMC_BASE_ADDR + 0x214)) +#define EMC_STA_WAITTURN0 (*(volatile unsigned long *)(EMC_BASE_ADDR + 0x218)) + +#define EMC_STA_CFG1 (*(volatile unsigned long *)(EMC_BASE_ADDR + 0x220)) +#define EMC_STA_WAITWEN1 (*(volatile unsigned long *)(EMC_BASE_ADDR + 0x224)) +#define EMC_STA_WAITOEN1 (*(volatile unsigned long *)(EMC_BASE_ADDR + 0x228)) +#define EMC_STA_WAITRD1 (*(volatile unsigned long *)(EMC_BASE_ADDR + 0x22C)) +#define EMC_STA_WAITPAGE1 (*(volatile unsigned long *)(EMC_BASE_ADDR + 0x230)) +#define EMC_STA_WAITWR1 (*(volatile unsigned long *)(EMC_BASE_ADDR + 0x234)) +#define EMC_STA_WAITTURN1 (*(volatile unsigned long *)(EMC_BASE_ADDR + 0x238)) + +#define EMC_STA_CFG2 (*(volatile unsigned long *)(EMC_BASE_ADDR + 0x240)) +#define EMC_STA_WAITWEN2 (*(volatile unsigned long *)(EMC_BASE_ADDR + 0x244)) +#define EMC_STA_WAITOEN2 (*(volatile unsigned long *)(EMC_BASE_ADDR + 0x248)) +#define EMC_STA_WAITRD2 (*(volatile unsigned long *)(EMC_BASE_ADDR + 0x24C)) +#define EMC_STA_WAITPAGE2 (*(volatile unsigned long *)(EMC_BASE_ADDR + 0x250)) +#define EMC_STA_WAITWR2 (*(volatile unsigned long *)(EMC_BASE_ADDR + 0x254)) +#define EMC_STA_WAITTURN2 (*(volatile unsigned long *)(EMC_BASE_ADDR + 0x258)) + +#define EMC_STA_CFG3 (*(volatile unsigned long *)(EMC_BASE_ADDR + 0x260)) +#define EMC_STA_WAITWEN3 (*(volatile unsigned long *)(EMC_BASE_ADDR + 0x264)) +#define EMC_STA_WAITOEN3 (*(volatile unsigned long *)(EMC_BASE_ADDR + 0x268)) +#define EMC_STA_WAITRD3 (*(volatile unsigned long *)(EMC_BASE_ADDR + 0x26C)) +#define EMC_STA_WAITPAGE3 (*(volatile unsigned long *)(EMC_BASE_ADDR + 0x270)) +#define EMC_STA_WAITWR3 (*(volatile unsigned long *)(EMC_BASE_ADDR + 0x274)) +#define EMC_STA_WAITTURN3 (*(volatile unsigned long *)(EMC_BASE_ADDR + 0x278)) + +#define EMC_STA_EXT_WAIT (*(volatile unsigned long *)(EMC_BASE_ADDR + 0x880)) + + +/* Timer 0 */ +#define TMR0_BASE_ADDR 0xE0004000 +#define T0IR (*(volatile unsigned long *)(TMR0_BASE_ADDR + 0x00)) +#define T0TCR (*(volatile unsigned long *)(TMR0_BASE_ADDR + 0x04)) +#define T0TC (*(volatile unsigned long *)(TMR0_BASE_ADDR + 0x08)) +#define T0PR (*(volatile unsigned long *)(TMR0_BASE_ADDR + 0x0C)) +#define T0PC (*(volatile unsigned long *)(TMR0_BASE_ADDR + 0x10)) +#define T0MCR (*(volatile unsigned long *)(TMR0_BASE_ADDR + 0x14)) +#define T0MR0 (*(volatile unsigned long *)(TMR0_BASE_ADDR + 0x18)) +#define T0MR1 (*(volatile unsigned long *)(TMR0_BASE_ADDR + 0x1C)) +#define T0MR2 (*(volatile unsigned long *)(TMR0_BASE_ADDR + 0x20)) +#define T0MR3 (*(volatile unsigned long *)(TMR0_BASE_ADDR + 0x24)) +#define T0CCR (*(volatile unsigned long *)(TMR0_BASE_ADDR + 0x28)) +#define T0CR0 (*(volatile unsigned long *)(TMR0_BASE_ADDR + 0x2C)) +#define T0CR1 (*(volatile unsigned long *)(TMR0_BASE_ADDR + 0x30)) +#define T0CR2 (*(volatile unsigned long *)(TMR0_BASE_ADDR + 0x34)) +#define T0CR3 (*(volatile unsigned long *)(TMR0_BASE_ADDR + 0x38)) +#define T0EMR (*(volatile unsigned long *)(TMR0_BASE_ADDR + 0x3C)) +#define T0CTCR (*(volatile unsigned long *)(TMR0_BASE_ADDR + 0x70)) + +/* Timer 1 */ +#define TMR1_BASE_ADDR 0xE0008000 +#define T1IR (*(volatile unsigned long *)(TMR1_BASE_ADDR + 0x00)) +#define T1TCR (*(volatile unsigned long *)(TMR1_BASE_ADDR + 0x04)) +#define T1TC (*(volatile unsigned long *)(TMR1_BASE_ADDR + 0x08)) +#define T1PR (*(volatile unsigned long *)(TMR1_BASE_ADDR + 0x0C)) +#define T1PC (*(volatile unsigned long *)(TMR1_BASE_ADDR + 0x10)) +#define T1MCR (*(volatile unsigned long *)(TMR1_BASE_ADDR + 0x14)) +#define T1MR0 (*(volatile unsigned long *)(TMR1_BASE_ADDR + 0x18)) +#define T1MR1 (*(volatile unsigned long *)(TMR1_BASE_ADDR + 0x1C)) +#define T1MR2 (*(volatile unsigned long *)(TMR1_BASE_ADDR + 0x20)) +#define T1MR3 (*(volatile unsigned long *)(TMR1_BASE_ADDR + 0x24)) +#define T1CCR (*(volatile unsigned long *)(TMR1_BASE_ADDR + 0x28)) +#define T1CR0 (*(volatile unsigned long *)(TMR1_BASE_ADDR + 0x2C)) +#define T1CR1 (*(volatile unsigned long *)(TMR1_BASE_ADDR + 0x30)) +#define T1CR2 (*(volatile unsigned long *)(TMR1_BASE_ADDR + 0x34)) +#define T1CR3 (*(volatile unsigned long *)(TMR1_BASE_ADDR + 0x38)) +#define T1EMR (*(volatile unsigned long *)(TMR1_BASE_ADDR + 0x3C)) +#define T1CTCR (*(volatile unsigned long *)(TMR1_BASE_ADDR + 0x70)) + +/* Timer 2 */ +#define TMR2_BASE_ADDR 0xE0070000 +#define T2IR (*(volatile unsigned long *)(TMR2_BASE_ADDR + 0x00)) +#define T2TCR (*(volatile unsigned long *)(TMR2_BASE_ADDR + 0x04)) +#define T2TC (*(volatile unsigned long *)(TMR2_BASE_ADDR + 0x08)) +#define T2PR (*(volatile unsigned long *)(TMR2_BASE_ADDR + 0x0C)) +#define T2PC (*(volatile unsigned long *)(TMR2_BASE_ADDR + 0x10)) +#define T2MCR (*(volatile unsigned long *)(TMR2_BASE_ADDR + 0x14)) +#define T2MR0 (*(volatile unsigned long *)(TMR2_BASE_ADDR + 0x18)) +#define T2MR1 (*(volatile unsigned long *)(TMR2_BASE_ADDR + 0x1C)) +#define T2MR2 (*(volatile unsigned long *)(TMR2_BASE_ADDR + 0x20)) +#define T2MR3 (*(volatile unsigned long *)(TMR2_BASE_ADDR + 0x24)) +#define T2CCR (*(volatile unsigned long *)(TMR2_BASE_ADDR + 0x28)) +#define T2CR0 (*(volatile unsigned long *)(TMR2_BASE_ADDR + 0x2C)) +#define T2CR1 (*(volatile unsigned long *)(TMR2_BASE_ADDR + 0x30)) +#define T2CR2 (*(volatile unsigned long *)(TMR2_BASE_ADDR + 0x34)) +#define T2CR3 (*(volatile unsigned long *)(TMR2_BASE_ADDR + 0x38)) +#define T2EMR (*(volatile unsigned long *)(TMR2_BASE_ADDR + 0x3C)) +#define T2CTCR (*(volatile unsigned long *)(TMR2_BASE_ADDR + 0x70)) + +/* Timer 3 */ +#define TMR3_BASE_ADDR 0xE0074000 +#define T3IR (*(volatile unsigned long *)(TMR3_BASE_ADDR + 0x00)) +#define T3TCR (*(volatile unsigned long *)(TMR3_BASE_ADDR + 0x04)) +#define T3TC (*(volatile unsigned long *)(TMR3_BASE_ADDR + 0x08)) +#define T3PR (*(volatile unsigned long *)(TMR3_BASE_ADDR + 0x0C)) +#define T3PC (*(volatile unsigned long *)(TMR3_BASE_ADDR + 0x10)) +#define T3MCR (*(volatile unsigned long *)(TMR3_BASE_ADDR + 0x14)) +#define T3MR0 (*(volatile unsigned long *)(TMR3_BASE_ADDR + 0x18)) +#define T3MR1 (*(volatile unsigned long *)(TMR3_BASE_ADDR + 0x1C)) +#define T3MR2 (*(volatile unsigned long *)(TMR3_BASE_ADDR + 0x20)) +#define T3MR3 (*(volatile unsigned long *)(TMR3_BASE_ADDR + 0x24)) +#define T3CCR (*(volatile unsigned long *)(TMR3_BASE_ADDR + 0x28)) +#define T3CR0 (*(volatile unsigned long *)(TMR3_BASE_ADDR + 0x2C)) +#define T3CR1 (*(volatile unsigned long *)(TMR3_BASE_ADDR + 0x30)) +#define T3CR2 (*(volatile unsigned long *)(TMR3_BASE_ADDR + 0x34)) +#define T3CR3 (*(volatile unsigned long *)(TMR3_BASE_ADDR + 0x38)) +#define T3EMR (*(volatile unsigned long *)(TMR3_BASE_ADDR + 0x3C)) +#define T3CTCR (*(volatile unsigned long *)(TMR3_BASE_ADDR + 0x70)) + + +/* Pulse Width Modulator (PWM) */ +#define PWM0_BASE_ADDR 0xE0014000 +#define PWM0IR (*(volatile unsigned long *)(PWM0_BASE_ADDR + 0x00)) +#define PWM0TCR (*(volatile unsigned long *)(PWM0_BASE_ADDR + 0x04)) +#define PWM0TC (*(volatile unsigned long *)(PWM0_BASE_ADDR + 0x08)) +#define PWM0PR (*(volatile unsigned long *)(PWM0_BASE_ADDR + 0x0C)) +#define PWM0PC (*(volatile unsigned long *)(PWM0_BASE_ADDR + 0x10)) +#define PWM0MCR (*(volatile unsigned long *)(PWM0_BASE_ADDR + 0x14)) +#define PWM0MR0 (*(volatile unsigned long *)(PWM0_BASE_ADDR + 0x18)) +#define PWM0MR1 (*(volatile unsigned long *)(PWM0_BASE_ADDR + 0x1C)) +#define PWM0MR2 (*(volatile unsigned long *)(PWM0_BASE_ADDR + 0x20)) +#define PWM0MR3 (*(volatile unsigned long *)(PWM0_BASE_ADDR + 0x24)) +#define PWM0CCR (*(volatile unsigned long *)(PWM0_BASE_ADDR + 0x28)) +#define PWM0CR0 (*(volatile unsigned long *)(PWM0_BASE_ADDR + 0x2C)) +#define PWM0CR1 (*(volatile unsigned long *)(PWM0_BASE_ADDR + 0x30)) +#define PWM0CR2 (*(volatile unsigned long *)(PWM0_BASE_ADDR + 0x34)) +#define PWM0CR3 (*(volatile unsigned long *)(PWM0_BASE_ADDR + 0x38)) +#define PWM0EMR (*(volatile unsigned long *)(PWM0_BASE_ADDR + 0x3C)) +#define PWM0MR4 (*(volatile unsigned long *)(PWM0_BASE_ADDR + 0x40)) +#define PWM0MR5 (*(volatile unsigned long *)(PWM0_BASE_ADDR + 0x44)) +#define PWM0MR6 (*(volatile unsigned long *)(PWM0_BASE_ADDR + 0x48)) +#define PWM0PCR (*(volatile unsigned long *)(PWM0_BASE_ADDR + 0x4C)) +#define PWM0LER (*(volatile unsigned long *)(PWM0_BASE_ADDR + 0x50)) +#define PWM0CTCR (*(volatile unsigned long *)(PWM0_BASE_ADDR + 0x70)) + +#define PWM1_BASE_ADDR 0xE0018000 +#define PWM1IR (*(volatile unsigned long *)(PWM1_BASE_ADDR + 0x00)) +#define PWM1TCR (*(volatile unsigned long *)(PWM1_BASE_ADDR + 0x04)) +#define PWM1TC (*(volatile unsigned long *)(PWM1_BASE_ADDR + 0x08)) +#define PWM1PR (*(volatile unsigned long *)(PWM1_BASE_ADDR + 0x0C)) +#define PWM1PC (*(volatile unsigned long *)(PWM1_BASE_ADDR + 0x10)) +#define PWM1MCR (*(volatile unsigned long *)(PWM1_BASE_ADDR + 0x14)) +#define PWM1MR0 (*(volatile unsigned long *)(PWM1_BASE_ADDR + 0x18)) +#define PWM1MR1 (*(volatile unsigned long *)(PWM1_BASE_ADDR + 0x1C)) +#define PWM1MR2 (*(volatile unsigned long *)(PWM1_BASE_ADDR + 0x20)) +#define PWM1MR3 (*(volatile unsigned long *)(PWM1_BASE_ADDR + 0x24)) +#define PWM1CCR (*(volatile unsigned long *)(PWM1_BASE_ADDR + 0x28)) +#define PWM1CR0 (*(volatile unsigned long *)(PWM1_BASE_ADDR + 0x2C)) +#define PWM1CR1 (*(volatile unsigned long *)(PWM1_BASE_ADDR + 0x30)) +#define PWM1CR2 (*(volatile unsigned long *)(PWM1_BASE_ADDR + 0x34)) +#define PWM1CR3 (*(volatile unsigned long *)(PWM1_BASE_ADDR + 0x38)) +#define PWM1EMR (*(volatile unsigned long *)(PWM1_BASE_ADDR + 0x3C)) +#define PWM1MR4 (*(volatile unsigned long *)(PWM1_BASE_ADDR + 0x40)) +#define PWM1MR5 (*(volatile unsigned long *)(PWM1_BASE_ADDR + 0x44)) +#define PWM1MR6 (*(volatile unsigned long *)(PWM1_BASE_ADDR + 0x48)) +#define PWM1PCR (*(volatile unsigned long *)(PWM1_BASE_ADDR + 0x4C)) +#define PWM1LER (*(volatile unsigned long *)(PWM1_BASE_ADDR + 0x50)) +#define PWM1CTCR (*(volatile unsigned long *)(PWM1_BASE_ADDR + 0x70)) + + +/* Universal Asynchronous Receiver Transmitter 0 (UART0) */ +#define UART0_BASE_ADDR 0xE000C000 +#define U0RBR (*(volatile unsigned long *)(UART0_BASE_ADDR + 0x00)) +#define U0THR (*(volatile unsigned long *)(UART0_BASE_ADDR + 0x00)) +#define U0DLL (*(volatile unsigned long *)(UART0_BASE_ADDR + 0x00)) +#define U0DLM (*(volatile unsigned long *)(UART0_BASE_ADDR + 0x04)) +#define U0IER (*(volatile unsigned long *)(UART0_BASE_ADDR + 0x04)) +#define U0IIR (*(volatile unsigned long *)(UART0_BASE_ADDR + 0x08)) +#define U0FCR (*(volatile unsigned long *)(UART0_BASE_ADDR + 0x08)) +#define U0LCR (*(volatile unsigned long *)(UART0_BASE_ADDR + 0x0C)) +#define U0LSR (*(volatile unsigned long *)(UART0_BASE_ADDR + 0x14)) +#define U0SCR (*(volatile unsigned long *)(UART0_BASE_ADDR + 0x1C)) +#define U0ACR (*(volatile unsigned long *)(UART0_BASE_ADDR + 0x20)) +#define U0ICR (*(volatile unsigned long *)(UART0_BASE_ADDR + 0x24)) +#define U0FDR (*(volatile unsigned long *)(UART0_BASE_ADDR + 0x28)) +#define U0TER (*(volatile unsigned long *)(UART0_BASE_ADDR + 0x30)) + +/* Universal Asynchronous Receiver Transmitter 1 (UART1) */ +#define UART1_BASE_ADDR 0xE0010000 +#define U1RBR (*(volatile unsigned long *)(UART1_BASE_ADDR + 0x00)) +#define U1THR (*(volatile unsigned long *)(UART1_BASE_ADDR + 0x00)) +#define U1DLL (*(volatile unsigned long *)(UART1_BASE_ADDR + 0x00)) +#define U1DLM (*(volatile unsigned long *)(UART1_BASE_ADDR + 0x04)) +#define U1IER (*(volatile unsigned long *)(UART1_BASE_ADDR + 0x04)) +#define U1IIR (*(volatile unsigned long *)(UART1_BASE_ADDR + 0x08)) +#define U1FCR (*(volatile unsigned long *)(UART1_BASE_ADDR + 0x08)) +#define U1LCR (*(volatile unsigned long *)(UART1_BASE_ADDR + 0x0C)) +#define U1MCR (*(volatile unsigned long *)(UART1_BASE_ADDR + 0x10)) +#define U1LSR (*(volatile unsigned long *)(UART1_BASE_ADDR + 0x14)) +#define U1MSR (*(volatile unsigned long *)(UART1_BASE_ADDR + 0x18)) +#define U1SCR (*(volatile unsigned long *)(UART1_BASE_ADDR + 0x1C)) +#define U1ACR (*(volatile unsigned long *)(UART1_BASE_ADDR + 0x20)) +#define U1FDR (*(volatile unsigned long *)(UART1_BASE_ADDR + 0x28)) +#define U1TER (*(volatile unsigned long *)(UART1_BASE_ADDR + 0x30)) + +/* Universal Asynchronous Receiver Transmitter 2 (UART2) */ +#define UART2_BASE_ADDR 0xE0078000 +#define U2RBR (*(volatile unsigned long *)(UART2_BASE_ADDR + 0x00)) +#define U2THR (*(volatile unsigned long *)(UART2_BASE_ADDR + 0x00)) +#define U2DLL (*(volatile unsigned long *)(UART2_BASE_ADDR + 0x00)) +#define U2DLM (*(volatile unsigned long *)(UART2_BASE_ADDR + 0x04)) +#define U2IER (*(volatile unsigned long *)(UART2_BASE_ADDR + 0x04)) +#define U2IIR (*(volatile unsigned long *)(UART2_BASE_ADDR + 0x08)) +#define U2FCR (*(volatile unsigned long *)(UART2_BASE_ADDR + 0x08)) +#define U2LCR (*(volatile unsigned long *)(UART2_BASE_ADDR + 0x0C)) +#define U2LSR (*(volatile unsigned long *)(UART2_BASE_ADDR + 0x14)) +#define U2SCR (*(volatile unsigned long *)(UART2_BASE_ADDR + 0x1C)) +#define U2ACR (*(volatile unsigned long *)(UART2_BASE_ADDR + 0x20)) +#define U2ICR (*(volatile unsigned long *)(UART2_BASE_ADDR + 0x24)) +#define U2FDR (*(volatile unsigned long *)(UART2_BASE_ADDR + 0x28)) +#define U2TER (*(volatile unsigned long *)(UART2_BASE_ADDR + 0x30)) + +/* Universal Asynchronous Receiver Transmitter 3 (UART3) */ +#define UART3_BASE_ADDR 0xE007C000 +#define U3RBR (*(volatile unsigned long *)(UART3_BASE_ADDR + 0x00)) +#define U3THR (*(volatile unsigned long *)(UART3_BASE_ADDR + 0x00)) +#define U3DLL (*(volatile unsigned long *)(UART3_BASE_ADDR + 0x00)) +#define U3DLM (*(volatile unsigned long *)(UART3_BASE_ADDR + 0x04)) +#define U3IER (*(volatile unsigned long *)(UART3_BASE_ADDR + 0x04)) +#define U3IIR (*(volatile unsigned long *)(UART3_BASE_ADDR + 0x08)) +#define U3FCR (*(volatile unsigned long *)(UART3_BASE_ADDR + 0x08)) +#define U3LCR (*(volatile unsigned long *)(UART3_BASE_ADDR + 0x0C)) +#define U3LSR (*(volatile unsigned long *)(UART3_BASE_ADDR + 0x14)) +#define U3SCR (*(volatile unsigned long *)(UART3_BASE_ADDR + 0x1C)) +#define U3ACR (*(volatile unsigned long *)(UART3_BASE_ADDR + 0x20)) +#define U3ICR (*(volatile unsigned long *)(UART3_BASE_ADDR + 0x24)) +#define U3FDR (*(volatile unsigned long *)(UART3_BASE_ADDR + 0x28)) +#define U3TER (*(volatile unsigned long *)(UART3_BASE_ADDR + 0x30)) + +/* I2C Interface 0 */ +#define I2C0_BASE_ADDR 0xE001C000 +#define I20CONSET (*(volatile unsigned long *)(I2C0_BASE_ADDR + 0x00)) +#define I20STAT (*(volatile unsigned long *)(I2C0_BASE_ADDR + 0x04)) +#define I20DAT (*(volatile unsigned long *)(I2C0_BASE_ADDR + 0x08)) +#define I20ADR (*(volatile unsigned long *)(I2C0_BASE_ADDR + 0x0C)) +#define I20SCLH (*(volatile unsigned long *)(I2C0_BASE_ADDR + 0x10)) +#define I20SCLL (*(volatile unsigned long *)(I2C0_BASE_ADDR + 0x14)) +#define I20CONCLR (*(volatile unsigned long *)(I2C0_BASE_ADDR + 0x18)) + +/* I2C Interface 1 */ +#define I2C1_BASE_ADDR 0xE005C000 +#define I21CONSET (*(volatile unsigned long *)(I2C1_BASE_ADDR + 0x00)) +#define I21STAT (*(volatile unsigned long *)(I2C1_BASE_ADDR + 0x04)) +#define I21DAT (*(volatile unsigned long *)(I2C1_BASE_ADDR + 0x08)) +#define I21ADR (*(volatile unsigned long *)(I2C1_BASE_ADDR + 0x0C)) +#define I21SCLH (*(volatile unsigned long *)(I2C1_BASE_ADDR + 0x10)) +#define I21SCLL (*(volatile unsigned long *)(I2C1_BASE_ADDR + 0x14)) +#define I21CONCLR (*(volatile unsigned long *)(I2C1_BASE_ADDR + 0x18)) + +/* I2C Interface 2 */ +#define I2C2_BASE_ADDR 0xE0080000 +#define I22CONSET (*(volatile unsigned long *)(I2C2_BASE_ADDR + 0x00)) +#define I22STAT (*(volatile unsigned long *)(I2C2_BASE_ADDR + 0x04)) +#define I22DAT (*(volatile unsigned long *)(I2C2_BASE_ADDR + 0x08)) +#define I22ADR (*(volatile unsigned long *)(I2C2_BASE_ADDR + 0x0C)) +#define I22SCLH (*(volatile unsigned long *)(I2C2_BASE_ADDR + 0x10)) +#define I22SCLL (*(volatile unsigned long *)(I2C2_BASE_ADDR + 0x14)) +#define I22CONCLR (*(volatile unsigned long *)(I2C2_BASE_ADDR + 0x18)) + +/* SPI0 (Serial Peripheral Interface 0) */ +#define SPI0_BASE_ADDR 0xE0020000 +#define S0SPCR (*(volatile unsigned long *)(SPI0_BASE_ADDR + 0x00)) +#define S0SPSR (*(volatile unsigned long *)(SPI0_BASE_ADDR + 0x04)) +#define S0SPDR (*(volatile unsigned long *)(SPI0_BASE_ADDR + 0x08)) +#define S0SPCCR (*(volatile unsigned long *)(SPI0_BASE_ADDR + 0x0C)) +#define S0SPINT (*(volatile unsigned long *)(SPI0_BASE_ADDR + 0x1C)) + +/* SSP0 Controller */ +#define SSP0_BASE_ADDR 0xE0068000 +#define SSP0CR0 (*(volatile unsigned long *)(SSP0_BASE_ADDR + 0x00)) +#define SSP0CR1 (*(volatile unsigned long *)(SSP0_BASE_ADDR + 0x04)) +#define SSP0DR (*(volatile unsigned long *)(SSP0_BASE_ADDR + 0x08)) +#define SSP0SR (*(volatile unsigned long *)(SSP0_BASE_ADDR + 0x0C)) +#define SSP0CPSR (*(volatile unsigned long *)(SSP0_BASE_ADDR + 0x10)) +#define SSP0IMSC (*(volatile unsigned long *)(SSP0_BASE_ADDR + 0x14)) +#define SSP0RIS (*(volatile unsigned long *)(SSP0_BASE_ADDR + 0x18)) +#define SSP0MIS (*(volatile unsigned long *)(SSP0_BASE_ADDR + 0x1C)) +#define SSP0ICR (*(volatile unsigned long *)(SSP0_BASE_ADDR + 0x20)) +#define SSP0DMACR (*(volatile unsigned long *)(SSP0_BASE_ADDR + 0x24)) + +/* SSP1 Controller */ +#define SSP1_BASE_ADDR 0xE0030000 +#define SSP1CR0 (*(volatile unsigned long *)(SSP1_BASE_ADDR + 0x00)) +#define SSP1CR1 (*(volatile unsigned long *)(SSP1_BASE_ADDR + 0x04)) +#define SSP1DR (*(volatile unsigned long *)(SSP1_BASE_ADDR + 0x08)) +#define SSP1SR (*(volatile unsigned long *)(SSP1_BASE_ADDR + 0x0C)) +#define SSP1CPSR (*(volatile unsigned long *)(SSP1_BASE_ADDR + 0x10)) +#define SSP1IMSC (*(volatile unsigned long *)(SSP1_BASE_ADDR + 0x14)) +#define SSP1RIS (*(volatile unsigned long *)(SSP1_BASE_ADDR + 0x18)) +#define SSP1MIS (*(volatile unsigned long *)(SSP1_BASE_ADDR + 0x1C)) +#define SSP1ICR (*(volatile unsigned long *)(SSP1_BASE_ADDR + 0x20)) +#define SSP1DMACR (*(volatile unsigned long *)(SSP1_BASE_ADDR + 0x24)) + + +/* Real Time Clock */ +#define RTC_BASE_ADDR 0xE0024000 +#define RTC_ILR (*(volatile unsigned long *)(RTC_BASE_ADDR + 0x00)) +#define RTC_CTC (*(volatile unsigned long *)(RTC_BASE_ADDR + 0x04)) +#define RTC_CCR (*(volatile unsigned long *)(RTC_BASE_ADDR + 0x08)) +#define RTC_CIIR (*(volatile unsigned long *)(RTC_BASE_ADDR + 0x0C)) +#define RTC_AMR (*(volatile unsigned long *)(RTC_BASE_ADDR + 0x10)) +#define RTC_CTIME0 (*(volatile unsigned long *)(RTC_BASE_ADDR + 0x14)) +#define RTC_CTIME1 (*(volatile unsigned long *)(RTC_BASE_ADDR + 0x18)) +#define RTC_CTIME2 (*(volatile unsigned long *)(RTC_BASE_ADDR + 0x1C)) +#define RTC_SEC (*(volatile unsigned long *)(RTC_BASE_ADDR + 0x20)) +#define RTC_MIN (*(volatile unsigned long *)(RTC_BASE_ADDR + 0x24)) +#define RTC_HOUR (*(volatile unsigned long *)(RTC_BASE_ADDR + 0x28)) +#define RTC_DOM (*(volatile unsigned long *)(RTC_BASE_ADDR + 0x2C)) +#define RTC_DOW (*(volatile unsigned long *)(RTC_BASE_ADDR + 0x30)) +#define RTC_DOY (*(volatile unsigned long *)(RTC_BASE_ADDR + 0x34)) +#define RTC_MONTH (*(volatile unsigned long *)(RTC_BASE_ADDR + 0x38)) +#define RTC_YEAR (*(volatile unsigned long *)(RTC_BASE_ADDR + 0x3C)) +#define RTC_CISS (*(volatile unsigned long *)(RTC_BASE_ADDR + 0x40)) +#define RTC_ALSEC (*(volatile unsigned long *)(RTC_BASE_ADDR + 0x60)) +#define RTC_ALMIN (*(volatile unsigned long *)(RTC_BASE_ADDR + 0x64)) +#define RTC_ALHOUR (*(volatile unsigned long *)(RTC_BASE_ADDR + 0x68)) +#define RTC_ALDOM (*(volatile unsigned long *)(RTC_BASE_ADDR + 0x6C)) +#define RTC_ALDOW (*(volatile unsigned long *)(RTC_BASE_ADDR + 0x70)) +#define RTC_ALDOY (*(volatile unsigned long *)(RTC_BASE_ADDR + 0x74)) +#define RTC_ALMON (*(volatile unsigned long *)(RTC_BASE_ADDR + 0x78)) +#define RTC_ALYEAR (*(volatile unsigned long *)(RTC_BASE_ADDR + 0x7C)) +#define RTC_PREINT (*(volatile unsigned long *)(RTC_BASE_ADDR + 0x80)) +#define RTC_PREFRAC (*(volatile unsigned long *)(RTC_BASE_ADDR + 0x84)) + + +/* A/D Converter 0 (AD0) */ +#define AD0_BASE_ADDR 0xE0034000 +#define AD0CR (*(volatile unsigned long *)(AD0_BASE_ADDR + 0x00)) +#define AD0GDR (*(volatile unsigned long *)(AD0_BASE_ADDR + 0x04)) +#define AD0INTEN (*(volatile unsigned long *)(AD0_BASE_ADDR + 0x0C)) +#define AD0DR0 (*(volatile unsigned long *)(AD0_BASE_ADDR + 0x10)) +#define AD0DR1 (*(volatile unsigned long *)(AD0_BASE_ADDR + 0x14)) +#define AD0DR2 (*(volatile unsigned long *)(AD0_BASE_ADDR + 0x18)) +#define AD0DR3 (*(volatile unsigned long *)(AD0_BASE_ADDR + 0x1C)) +#define AD0DR4 (*(volatile unsigned long *)(AD0_BASE_ADDR + 0x20)) +#define AD0DR5 (*(volatile unsigned long *)(AD0_BASE_ADDR + 0x24)) +#define AD0DR6 (*(volatile unsigned long *)(AD0_BASE_ADDR + 0x28)) +#define AD0DR7 (*(volatile unsigned long *)(AD0_BASE_ADDR + 0x2C)) +#define AD0STAT (*(volatile unsigned long *)(AD0_BASE_ADDR + 0x30)) + + +/* D/A Converter */ +#define DAC_BASE_ADDR 0xE006C000 +#define DACR (*(volatile unsigned long *)(DAC_BASE_ADDR + 0x00)) + + +/* Watchdog */ +#define WDG_BASE_ADDR 0xE0000000 +#define WDMOD (*(volatile unsigned long *)(WDG_BASE_ADDR + 0x00)) +#define WDTC (*(volatile unsigned long *)(WDG_BASE_ADDR + 0x04)) +#define WDFEED (*(volatile unsigned long *)(WDG_BASE_ADDR + 0x08)) +#define WDTV (*(volatile unsigned long *)(WDG_BASE_ADDR + 0x0C)) +#define WDCLKSEL (*(volatile unsigned long *)(WDG_BASE_ADDR + 0x10)) + +/* CAN CONTROLLERS AND ACCEPTANCE FILTER */ +#define CAN_ACCEPT_BASE_ADDR 0xE003C000 +#define CAN_AFMR (*(volatile unsigned long *)(CAN_ACCEPT_BASE_ADDR + 0x00)) +#define CAN_SFF_SA (*(volatile unsigned long *)(CAN_ACCEPT_BASE_ADDR + 0x04)) +#define CAN_SFF_GRP_SA (*(volatile unsigned long *)(CAN_ACCEPT_BASE_ADDR + 0x08)) +#define CAN_EFF_SA (*(volatile unsigned long *)(CAN_ACCEPT_BASE_ADDR + 0x0C)) +#define CAN_EFF_GRP_SA (*(volatile unsigned long *)(CAN_ACCEPT_BASE_ADDR + 0x10)) +#define CAN_EOT (*(volatile unsigned long *)(CAN_ACCEPT_BASE_ADDR + 0x14)) +#define CAN_LUT_ERR_ADR (*(volatile unsigned long *)(CAN_ACCEPT_BASE_ADDR + 0x18)) +#define CAN_LUT_ERR (*(volatile unsigned long *)(CAN_ACCEPT_BASE_ADDR + 0x1C)) + +#define CAN_CENTRAL_BASE_ADDR 0xE0040000 +#define CAN_TX_SR (*(volatile unsigned long *)(CAN_CENTRAL_BASE_ADDR + 0x00)) +#define CAN_RX_SR (*(volatile unsigned long *)(CAN_CENTRAL_BASE_ADDR + 0x04)) +#define CAN_MSR (*(volatile unsigned long *)(CAN_CENTRAL_BASE_ADDR + 0x08)) + +#define CAN1_BASE_ADDR 0xE0044000 +#define CAN1MOD (*(volatile unsigned long *)(CAN1_BASE_ADDR + 0x00)) +#define CAN1CMR (*(volatile unsigned long *)(CAN1_BASE_ADDR + 0x04)) +#define CAN1GSR (*(volatile unsigned long *)(CAN1_BASE_ADDR + 0x08)) +#define CAN1ICR (*(volatile unsigned long *)(CAN1_BASE_ADDR + 0x0C)) +#define CAN1IER (*(volatile unsigned long *)(CAN1_BASE_ADDR + 0x10)) +#define CAN1BTR (*(volatile unsigned long *)(CAN1_BASE_ADDR + 0x14)) +#define CAN1EWL (*(volatile unsigned long *)(CAN1_BASE_ADDR + 0x18)) +#define CAN1SR (*(volatile unsigned long *)(CAN1_BASE_ADDR + 0x1C)) +#define CAN1RFS (*(volatile unsigned long *)(CAN1_BASE_ADDR + 0x20)) +#define CAN1RID (*(volatile unsigned long *)(CAN1_BASE_ADDR + 0x24)) +#define CAN1RDA (*(volatile unsigned long *)(CAN1_BASE_ADDR + 0x28)) +#define CAN1RDB (*(volatile unsigned long *)(CAN1_BASE_ADDR + 0x2C)) + +#define CAN1TFI1 (*(volatile unsigned long *)(CAN1_BASE_ADDR + 0x30)) +#define CAN1TID1 (*(volatile unsigned long *)(CAN1_BASE_ADDR + 0x34)) +#define CAN1TDA1 (*(volatile unsigned long *)(CAN1_BASE_ADDR + 0x38)) +#define CAN1TDB1 (*(volatile unsigned long *)(CAN1_BASE_ADDR + 0x3C)) +#define CAN1TFI2 (*(volatile unsigned long *)(CAN1_BASE_ADDR + 0x40)) +#define CAN1TID2 (*(volatile unsigned long *)(CAN1_BASE_ADDR + 0x44)) +#define CAN1TDA2 (*(volatile unsigned long *)(CAN1_BASE_ADDR + 0x48)) +#define CAN1TDB2 (*(volatile unsigned long *)(CAN1_BASE_ADDR + 0x4C)) +#define CAN1TFI3 (*(volatile unsigned long *)(CAN1_BASE_ADDR + 0x50)) +#define CAN1TID3 (*(volatile unsigned long *)(CAN1_BASE_ADDR + 0x54)) +#define CAN1TDA3 (*(volatile unsigned long *)(CAN1_BASE_ADDR + 0x58)) +#define CAN1TDB3 (*(volatile unsigned long *)(CAN1_BASE_ADDR + 0x5C)) + +#define CAN2_BASE_ADDR 0xE0048000 +#define CAN2MOD (*(volatile unsigned long *)(CAN2_BASE_ADDR + 0x00)) +#define CAN2CMR (*(volatile unsigned long *)(CAN2_BASE_ADDR + 0x04)) +#define CAN2GSR (*(volatile unsigned long *)(CAN2_BASE_ADDR + 0x08)) +#define CAN2ICR (*(volatile unsigned long *)(CAN2_BASE_ADDR + 0x0C)) +#define CAN2IER (*(volatile unsigned long *)(CAN2_BASE_ADDR + 0x10)) +#define CAN2BTR (*(volatile unsigned long *)(CAN2_BASE_ADDR + 0x14)) +#define CAN2EWL (*(volatile unsigned long *)(CAN2_BASE_ADDR + 0x18)) +#define CAN2SR (*(volatile unsigned long *)(CAN2_BASE_ADDR + 0x1C)) +#define CAN2RFS (*(volatile unsigned long *)(CAN2_BASE_ADDR + 0x20)) +#define CAN2RID (*(volatile unsigned long *)(CAN2_BASE_ADDR + 0x24)) +#define CAN2RDA (*(volatile unsigned long *)(CAN2_BASE_ADDR + 0x28)) +#define CAN2RDB (*(volatile unsigned long *)(CAN2_BASE_ADDR + 0x2C)) + +#define CAN2TFI1 (*(volatile unsigned long *)(CAN2_BASE_ADDR + 0x30)) +#define CAN2TID1 (*(volatile unsigned long *)(CAN2_BASE_ADDR + 0x34)) +#define CAN2TDA1 (*(volatile unsigned long *)(CAN2_BASE_ADDR + 0x38)) +#define CAN2TDB1 (*(volatile unsigned long *)(CAN2_BASE_ADDR + 0x3C)) +#define CAN2TFI2 (*(volatile unsigned long *)(CAN2_BASE_ADDR + 0x40)) +#define CAN2TID2 (*(volatile unsigned long *)(CAN2_BASE_ADDR + 0x44)) +#define CAN2TDA2 (*(volatile unsigned long *)(CAN2_BASE_ADDR + 0x48)) +#define CAN2TDB2 (*(volatile unsigned long *)(CAN2_BASE_ADDR + 0x4C)) +#define CAN2TFI3 (*(volatile unsigned long *)(CAN2_BASE_ADDR + 0x50)) +#define CAN2TID3 (*(volatile unsigned long *)(CAN2_BASE_ADDR + 0x54)) +#define CAN2TDA3 (*(volatile unsigned long *)(CAN2_BASE_ADDR + 0x58)) +#define CAN2TDB3 (*(volatile unsigned long *)(CAN2_BASE_ADDR + 0x5C)) + + +/* MultiMedia Card Interface(MCI) Controller */ +#define MCI_BASE_ADDR 0xE008C000 +#define MCI_POWER (*(volatile unsigned long *)(MCI_BASE_ADDR + 0x00)) +#define MCI_CLOCK (*(volatile unsigned long *)(MCI_BASE_ADDR + 0x04)) +#define MCI_ARGUMENT (*(volatile unsigned long *)(MCI_BASE_ADDR + 0x08)) +#define MCI_COMMAND (*(volatile unsigned long *)(MCI_BASE_ADDR + 0x0C)) +#define MCI_RESP_CMD (*(volatile unsigned long *)(MCI_BASE_ADDR + 0x10)) +#define MCI_RESP0 (*(volatile unsigned long *)(MCI_BASE_ADDR + 0x14)) +#define MCI_RESP1 (*(volatile unsigned long *)(MCI_BASE_ADDR + 0x18)) +#define MCI_RESP2 (*(volatile unsigned long *)(MCI_BASE_ADDR + 0x1C)) +#define MCI_RESP3 (*(volatile unsigned long *)(MCI_BASE_ADDR + 0x20)) +#define MCI_DATA_TMR (*(volatile unsigned long *)(MCI_BASE_ADDR + 0x24)) +#define MCI_DATA_LEN (*(volatile unsigned long *)(MCI_BASE_ADDR + 0x28)) +#define MCI_DATA_CTRL (*(volatile unsigned long *)(MCI_BASE_ADDR + 0x2C)) +#define MCI_DATA_CNT (*(volatile unsigned long *)(MCI_BASE_ADDR + 0x30)) +#define MCI_STATUS (*(volatile unsigned long *)(MCI_BASE_ADDR + 0x34)) +#define MCI_CLEAR (*(volatile unsigned long *)(MCI_BASE_ADDR + 0x38)) +#define MCI_MASK0 (*(volatile unsigned long *)(MCI_BASE_ADDR + 0x3C)) +#define MCI_MASK1 (*(volatile unsigned long *)(MCI_BASE_ADDR + 0x40)) +#define MCI_FIFO_CNT (*(volatile unsigned long *)(MCI_BASE_ADDR + 0x48)) +#define MCI_FIFO (*(volatile unsigned long *)(MCI_BASE_ADDR + 0x80)) + + +/* I2S Interface Controller (I2S) */ +#define I2S_BASE_ADDR 0xE0088000 +#define I2S_DAO (*(volatile unsigned long *)(I2S_BASE_ADDR + 0x00)) +#define I2S_DAI (*(volatile unsigned long *)(I2S_BASE_ADDR + 0x04)) +#define I2S_TX_FIFO (*(volatile unsigned long *)(I2S_BASE_ADDR + 0x08)) +#define I2S_RX_FIFO (*(volatile unsigned long *)(I2S_BASE_ADDR + 0x0C)) +#define I2S_STATE (*(volatile unsigned long *)(I2S_BASE_ADDR + 0x10)) +#define I2S_DMA1 (*(volatile unsigned long *)(I2S_BASE_ADDR + 0x14)) +#define I2S_DMA2 (*(volatile unsigned long *)(I2S_BASE_ADDR + 0x18)) +#define I2S_IRQ (*(volatile unsigned long *)(I2S_BASE_ADDR + 0x1C)) +#define I2S_TXRATE (*(volatile unsigned long *)(I2S_BASE_ADDR + 0x20)) +#define I2S_RXRATE (*(volatile unsigned long *)(I2S_BASE_ADDR + 0x24)) + + +/* General-purpose DMA Controller */ +#define DMA_BASE_ADDR 0xFFE04000 +#define GPDMA_INT_STAT (*(volatile unsigned long *)(DMA_BASE_ADDR + 0x000)) +#define GPDMA_INT_TCSTAT (*(volatile unsigned long *)(DMA_BASE_ADDR + 0x004)) +#define GPDMA_INT_TCCLR (*(volatile unsigned long *)(DMA_BASE_ADDR + 0x008)) +#define GPDMA_INT_ERR_STAT (*(volatile unsigned long *)(DMA_BASE_ADDR + 0x00C)) +#define GPDMA_INT_ERR_CLR (*(volatile unsigned long *)(DMA_BASE_ADDR + 0x010)) +#define GPDMA_RAW_INT_TCSTAT (*(volatile unsigned long *)(DMA_BASE_ADDR + 0x014)) +#define GPDMA_RAW_INT_ERR_STAT (*(volatile unsigned long *)(DMA_BASE_ADDR + 0x018)) +#define GPDMA_ENABLED_CHNS (*(volatile unsigned long *)(DMA_BASE_ADDR + 0x01C)) +#define GPDMA_SOFT_BREQ (*(volatile unsigned long *)(DMA_BASE_ADDR + 0x020)) +#define GPDMA_SOFT_SREQ (*(volatile unsigned long *)(DMA_BASE_ADDR + 0x024)) +#define GPDMA_SOFT_LBREQ (*(volatile unsigned long *)(DMA_BASE_ADDR + 0x028)) +#define GPDMA_SOFT_LSREQ (*(volatile unsigned long *)(DMA_BASE_ADDR + 0x02C)) +#define GPDMA_CONFIG (*(volatile unsigned long *)(DMA_BASE_ADDR + 0x030)) +#define GPDMA_SYNC (*(volatile unsigned long *)(DMA_BASE_ADDR + 0x034)) + +/* DMA channel 0 registers */ +#define GPDMA_CH0_SRC (*(volatile unsigned long *)(DMA_BASE_ADDR + 0x100)) +#define GPDMA_CH0_DEST (*(volatile unsigned long *)(DMA_BASE_ADDR + 0x104)) +#define GPDMA_CH0_LLI (*(volatile unsigned long *)(DMA_BASE_ADDR + 0x108)) +#define GPDMA_CH0_CTRL (*(volatile unsigned long *)(DMA_BASE_ADDR + 0x10C)) +#define GPDMA_CH0_CFG (*(volatile unsigned long *)(DMA_BASE_ADDR + 0x110)) + +/* DMA channel 1 registers */ +#define GPDMA_CH1_SRC (*(volatile unsigned long *)(DMA_BASE_ADDR + 0x120)) +#define GPDMA_CH1_DEST (*(volatile unsigned long *)(DMA_BASE_ADDR + 0x124)) +#define GPDMA_CH1_LLI (*(volatile unsigned long *)(DMA_BASE_ADDR + 0x128)) +#define GPDMA_CH1_CTRL (*(volatile unsigned long *)(DMA_BASE_ADDR + 0x12C)) +#define GPDMA_CH1_CFG (*(volatile unsigned long *)(DMA_BASE_ADDR + 0x130)) + + +/* USB Controller */ +#define USB_INT_BASE_ADDR 0xE01FC1C0 +#define USB_BASE_ADDR 0xFFE0C200 /* USB Base Address */ + +#define USB_INT_STAT (*(volatile unsigned long *)(USB_INT_BASE_ADDR + 0x00)) + +/* USB Device Interrupt Registers */ +#define DEV_INT_STAT (*(volatile unsigned long *)(USB_BASE_ADDR + 0x00)) +#define DEV_INT_EN (*(volatile unsigned long *)(USB_BASE_ADDR + 0x04)) +#define DEV_INT_CLR (*(volatile unsigned long *)(USB_BASE_ADDR + 0x08)) +#define DEV_INT_SET (*(volatile unsigned long *)(USB_BASE_ADDR + 0x0C)) +#define DEV_INT_PRIO (*(volatile unsigned long *)(USB_BASE_ADDR + 0x2C)) + +/* USB Device Endpoint Interrupt Registers */ +#define EP_INT_STAT (*(volatile unsigned long *)(USB_BASE_ADDR + 0x30)) +#define EP_INT_EN (*(volatile unsigned long *)(USB_BASE_ADDR + 0x34)) +#define EP_INT_CLR (*(volatile unsigned long *)(USB_BASE_ADDR + 0x38)) +#define EP_INT_SET (*(volatile unsigned long *)(USB_BASE_ADDR + 0x3C)) +#define EP_INT_PRIO (*(volatile unsigned long *)(USB_BASE_ADDR + 0x40)) + +/* USB Device Endpoint Realization Registers */ +#define REALIZE_EP (*(volatile unsigned long *)(USB_BASE_ADDR + 0x44)) +#define EP_INDEX (*(volatile unsigned long *)(USB_BASE_ADDR + 0x48)) +#define MAXPACKET_SIZE (*(volatile unsigned long *)(USB_BASE_ADDR + 0x4C)) + +/* USB Device Command Reagisters */ +#define CMD_CODE (*(volatile unsigned long *)(USB_BASE_ADDR + 0x10)) +#define CMD_DATA (*(volatile unsigned long *)(USB_BASE_ADDR + 0x14)) + +/* USB Device Data Transfer Registers */ +#define RX_DATA (*(volatile unsigned long *)(USB_BASE_ADDR + 0x18)) +#define TX_DATA (*(volatile unsigned long *)(USB_BASE_ADDR + 0x1C)) +#define RX_PLENGTH (*(volatile unsigned long *)(USB_BASE_ADDR + 0x20)) +#define TX_PLENGTH (*(volatile unsigned long *)(USB_BASE_ADDR + 0x24)) +#define USB_CTRL (*(volatile unsigned long *)(USB_BASE_ADDR + 0x28)) + +/* USB Device DMA Registers */ +#define DMA_REQ_STAT (*(volatile unsigned long *)(USB_BASE_ADDR + 0x50)) +#define DMA_REQ_CLR (*(volatile unsigned long *)(USB_BASE_ADDR + 0x54)) +#define DMA_REQ_SET (*(volatile unsigned long *)(USB_BASE_ADDR + 0x58)) +#define UDCA_HEAD (*(volatile unsigned long *)(USB_BASE_ADDR + 0x80)) +#define EP_DMA_STAT (*(volatile unsigned long *)(USB_BASE_ADDR + 0x84)) +#define EP_DMA_EN (*(volatile unsigned long *)(USB_BASE_ADDR + 0x88)) +#define EP_DMA_DIS (*(volatile unsigned long *)(USB_BASE_ADDR + 0x8C)) +#define DMA_INT_STAT (*(volatile unsigned long *)(USB_BASE_ADDR + 0x90)) +#define DMA_INT_EN (*(volatile unsigned long *)(USB_BASE_ADDR + 0x94)) +#define EOT_INT_STAT (*(volatile unsigned long *)(USB_BASE_ADDR + 0xA0)) +#define EOT_INT_CLR (*(volatile unsigned long *)(USB_BASE_ADDR + 0xA4)) +#define EOT_INT_SET (*(volatile unsigned long *)(USB_BASE_ADDR + 0xA8)) +#define NDD_REQ_INT_STAT (*(volatile unsigned long *)(USB_BASE_ADDR + 0xAC)) +#define NDD_REQ_INT_CLR (*(volatile unsigned long *)(USB_BASE_ADDR + 0xB0)) +#define NDD_REQ_INT_SET (*(volatile unsigned long *)(USB_BASE_ADDR + 0xB4)) +#define SYS_ERR_INT_STAT (*(volatile unsigned long *)(USB_BASE_ADDR + 0xB8)) +#define SYS_ERR_INT_CLR (*(volatile unsigned long *)(USB_BASE_ADDR + 0xBC)) +#define SYS_ERR_INT_SET (*(volatile unsigned long *)(USB_BASE_ADDR + 0xC0)) + +/* USB Host and OTG registers are for LPC24xx only */ +/* USB Host Controller */ +#define USBHC_BASE_ADDR 0xFFE0C000 +#define HC_REVISION (*(volatile unsigned long *)(USBHC_BASE_ADDR + 0x00)) +#define HC_CONTROL (*(volatile unsigned long *)(USBHC_BASE_ADDR + 0x04)) +#define HC_CMD_STAT (*(volatile unsigned long *)(USBHC_BASE_ADDR + 0x08)) +#define HC_INT_STAT (*(volatile unsigned long *)(USBHC_BASE_ADDR + 0x0C)) +#define HC_INT_EN (*(volatile unsigned long *)(USBHC_BASE_ADDR + 0x10)) +#define HC_INT_DIS (*(volatile unsigned long *)(USBHC_BASE_ADDR + 0x14)) +#define HC_HCCA (*(volatile unsigned long *)(USBHC_BASE_ADDR + 0x18)) +#define HC_PERIOD_CUR_ED (*(volatile unsigned long *)(USBHC_BASE_ADDR + 0x1C)) +#define HC_CTRL_HEAD_ED (*(volatile unsigned long *)(USBHC_BASE_ADDR + 0x20)) +#define HC_CTRL_CUR_ED (*(volatile unsigned long *)(USBHC_BASE_ADDR + 0x24)) +#define HC_BULK_HEAD_ED (*(volatile unsigned long *)(USBHC_BASE_ADDR + 0x28)) +#define HC_BULK_CUR_ED (*(volatile unsigned long *)(USBHC_BASE_ADDR + 0x2C)) +#define HC_DONE_HEAD (*(volatile unsigned long *)(USBHC_BASE_ADDR + 0x30)) +#define HC_FM_INTERVAL (*(volatile unsigned long *)(USBHC_BASE_ADDR + 0x34)) +#define HC_FM_REMAINING (*(volatile unsigned long *)(USBHC_BASE_ADDR + 0x38)) +#define HC_FM_NUMBER (*(volatile unsigned long *)(USBHC_BASE_ADDR + 0x3C)) +#define HC_PERIOD_START (*(volatile unsigned long *)(USBHC_BASE_ADDR + 0x40)) +#define HC_LS_THRHLD (*(volatile unsigned long *)(USBHC_BASE_ADDR + 0x44)) +#define HC_RH_DESCA (*(volatile unsigned long *)(USBHC_BASE_ADDR + 0x48)) +#define HC_RH_DESCB (*(volatile unsigned long *)(USBHC_BASE_ADDR + 0x4C)) +#define HC_RH_STAT (*(volatile unsigned long *)(USBHC_BASE_ADDR + 0x50)) +#define HC_RH_PORT_STAT1 (*(volatile unsigned long *)(USBHC_BASE_ADDR + 0x54)) +#define HC_RH_PORT_STAT2 (*(volatile unsigned long *)(USBHC_BASE_ADDR + 0x58)) + +/* USB OTG Controller */ +#define USBOTG_BASE_ADDR 0xFFE0C100 +#define OTG_INT_STAT (*(volatile unsigned long *)(USBOTG_BASE_ADDR + 0x00)) +#define OTG_INT_EN (*(volatile unsigned long *)(USBOTG_BASE_ADDR + 0x04)) +#define OTG_INT_SET (*(volatile unsigned long *)(USBOTG_BASE_ADDR + 0x08)) +#define OTG_INT_CLR (*(volatile unsigned long *)(USBOTG_BASE_ADDR + 0x0C)) +/* On LPC23xx, the name is USBPortSel, on LPC24xx, the name is OTG_STAT_CTRL */ +#define OTG_STAT_CTRL (*(volatile unsigned long *)(USBOTG_BASE_ADDR + 0x10)) +#define OTG_TIMER (*(volatile unsigned long *)(USBOTG_BASE_ADDR + 0x14)) + +#define USBOTG_I2C_BASE_ADDR 0xFFE0C300 +#define OTG_I2C_RX (*(volatile unsigned long *)(USBOTG_I2C_BASE_ADDR + 0x00)) +#define OTG_I2C_TX (*(volatile unsigned long *)(USBOTG_I2C_BASE_ADDR + 0x00)) +#define OTG_I2C_STS (*(volatile unsigned long *)(USBOTG_I2C_BASE_ADDR + 0x04)) +#define OTG_I2C_CTL (*(volatile unsigned long *)(USBOTG_I2C_BASE_ADDR + 0x08)) +#define OTG_I2C_CLKHI (*(volatile unsigned long *)(USBOTG_I2C_BASE_ADDR + 0x0C)) +#define OTG_I2C_CLKLO (*(volatile unsigned long *)(USBOTG_I2C_BASE_ADDR + 0x10)) + +/* On LPC23xx, the names are USBClkCtrl and USBClkSt; on LPC24xx, the names are +OTG_CLK_CTRL and OTG_CLK_STAT respectively. */ +#define USBOTG_CLK_BASE_ADDR 0xFFE0CFF0 +#define OTG_CLK_CTRL (*(volatile unsigned long *)(USBOTG_CLK_BASE_ADDR + 0x04)) +#define OTG_CLK_STAT (*(volatile unsigned long *)(USBOTG_CLK_BASE_ADDR + 0x08)) + +/* Note: below three register name convention is for LPC23xx USB device only, match +with the spec. update in USB Device Section. */ +#define USBPortSel (*(volatile unsigned long *)(USBOTG_BASE_ADDR + 0x10)) +#define USBClkCtrl (*(volatile unsigned long *)(USBOTG_CLK_BASE_ADDR + 0x04)) +#define USBClkSt (*(volatile unsigned long *)(USBOTG_CLK_BASE_ADDR + 0x08)) + +/* Ethernet MAC (32 bit data bus) -- all registers are RW unless indicated in parentheses */ +#define MAC_BASE_ADDR 0xFFE00000 /* AHB Peripheral # 0 */ +#define MAC_MAC1 (*(volatile unsigned long *)(MAC_BASE_ADDR + 0x000)) /* MAC config reg 1 */ +#define MAC_MAC2 (*(volatile unsigned long *)(MAC_BASE_ADDR + 0x004)) /* MAC config reg 2 */ +#define MAC_IPGT (*(volatile unsigned long *)(MAC_BASE_ADDR + 0x008)) /* b2b InterPacketGap reg */ +#define MAC_IPGR (*(volatile unsigned long *)(MAC_BASE_ADDR + 0x00C)) /* non b2b InterPacketGap reg */ +#define MAC_CLRT (*(volatile unsigned long *)(MAC_BASE_ADDR + 0x010)) /* CoLlision window/ReTry reg */ +#define MAC_MAXF (*(volatile unsigned long *)(MAC_BASE_ADDR + 0x014)) /* MAXimum Frame reg */ +#define MAC_SUPP (*(volatile unsigned long *)(MAC_BASE_ADDR + 0x018)) /* PHY SUPPort reg */ +#define MAC_TEST (*(volatile unsigned long *)(MAC_BASE_ADDR + 0x01C)) /* TEST reg */ +#define MAC_MCFG (*(volatile unsigned long *)(MAC_BASE_ADDR + 0x020)) /* MII Mgmt ConFiG reg */ +#define MAC_MCMD (*(volatile unsigned long *)(MAC_BASE_ADDR + 0x024)) /* MII Mgmt CoMmanD reg */ +#define MAC_MADR (*(volatile unsigned long *)(MAC_BASE_ADDR + 0x028)) /* MII Mgmt ADdRess reg */ +#define MAC_MWTD (*(volatile unsigned long *)(MAC_BASE_ADDR + 0x02C)) /* MII Mgmt WriTe Data reg (WO) */ +#define MAC_MRDD (*(volatile unsigned long *)(MAC_BASE_ADDR + 0x030)) /* MII Mgmt ReaD Data reg (RO) */ +#define MAC_MIND (*(volatile unsigned long *)(MAC_BASE_ADDR + 0x034)) /* MII Mgmt INDicators reg (RO) */ + +#define MAC_SA0 (*(volatile unsigned long *)(MAC_BASE_ADDR + 0x040)) /* Station Address 0 reg */ +#define MAC_SA1 (*(volatile unsigned long *)(MAC_BASE_ADDR + 0x044)) /* Station Address 1 reg */ +#define MAC_SA2 (*(volatile unsigned long *)(MAC_BASE_ADDR + 0x048)) /* Station Address 2 reg */ + +#define MAC_COMMAND (*(volatile unsigned long *)(MAC_BASE_ADDR + 0x100)) /* Command reg */ +#define MAC_STATUS (*(volatile unsigned long *)(MAC_BASE_ADDR + 0x104)) /* Status reg (RO) */ +#define MAC_RXDESCRIPTOR (*(volatile unsigned long *)(MAC_BASE_ADDR + 0x108)) /* Rx descriptor base address reg */ +#define MAC_RXSTATUS (*(volatile unsigned long *)(MAC_BASE_ADDR + 0x10C)) /* Rx status base address reg */ +#define MAC_RXDESCRIPTORNUM (*(volatile unsigned long *)(MAC_BASE_ADDR + 0x110)) /* Rx number of descriptors reg */ +#define MAC_RXPRODUCEINDEX (*(volatile unsigned long *)(MAC_BASE_ADDR + 0x114)) /* Rx produce index reg (RO) */ +#define MAC_RXCONSUMEINDEX (*(volatile unsigned long *)(MAC_BASE_ADDR + 0x118)) /* Rx consume index reg */ +#define MAC_TXDESCRIPTOR (*(volatile unsigned long *)(MAC_BASE_ADDR + 0x11C)) /* Tx descriptor base address reg */ +#define MAC_TXSTATUS (*(volatile unsigned long *)(MAC_BASE_ADDR + 0x120)) /* Tx status base address reg */ +#define MAC_TXDESCRIPTORNUM (*(volatile unsigned long *)(MAC_BASE_ADDR + 0x124)) /* Tx number of descriptors reg */ +#define MAC_TXPRODUCEINDEX (*(volatile unsigned long *)(MAC_BASE_ADDR + 0x128)) /* Tx produce index reg */ +#define MAC_TXCONSUMEINDEX (*(volatile unsigned long *)(MAC_BASE_ADDR + 0x12C)) /* Tx consume index reg (RO) */ + +#define MAC_TSV0 (*(volatile unsigned long *)(MAC_BASE_ADDR + 0x158)) /* Tx status vector 0 reg (RO) */ +#define MAC_TSV1 (*(volatile unsigned long *)(MAC_BASE_ADDR + 0x15C)) /* Tx status vector 1 reg (RO) */ +#define MAC_RSV (*(volatile unsigned long *)(MAC_BASE_ADDR + 0x160)) /* Rx status vector reg (RO) */ + +#define MAC_FLOWCONTROLCNT (*(volatile unsigned long *)(MAC_BASE_ADDR + 0x170)) /* Flow control counter reg */ +#define MAC_FLOWCONTROLSTS (*(volatile unsigned long *)(MAC_BASE_ADDR + 0x174)) /* Flow control status reg */ + +#define MAC_RXFILTERCTRL (*(volatile unsigned long *)(MAC_BASE_ADDR + 0x200)) /* Rx filter ctrl reg */ +#define MAC_RXFILTERWOLSTS (*(volatile unsigned long *)(MAC_BASE_ADDR + 0x204)) /* Rx filter WoL status reg (RO) */ +#define MAC_RXFILTERWOLCLR (*(volatile unsigned long *)(MAC_BASE_ADDR + 0x208)) /* Rx filter WoL clear reg (WO) */ + +#define MAC_HASHFILTERL (*(volatile unsigned long *)(MAC_BASE_ADDR + 0x210)) /* Hash filter LSBs reg */ +#define MAC_HASHFILTERH (*(volatile unsigned long *)(MAC_BASE_ADDR + 0x214)) /* Hash filter MSBs reg */ + +#define MAC_INTSTATUS (*(volatile unsigned long *)(MAC_BASE_ADDR + 0xFE0)) /* Interrupt status reg (RO) */ +#define MAC_INTENABLE (*(volatile unsigned long *)(MAC_BASE_ADDR + 0xFE4)) /* Interrupt enable reg */ +#define MAC_INTCLEAR (*(volatile unsigned long *)(MAC_BASE_ADDR + 0xFE8)) /* Interrupt clear reg (WO) */ +#define MAC_INTSET (*(volatile unsigned long *)(MAC_BASE_ADDR + 0xFEC)) /* Interrupt set reg (WO) */ + +#define MAC_POWERDOWN (*(volatile unsigned long *)(MAC_BASE_ADDR + 0xFF4)) /* Power-down reg */ +#define MAC_MODULEID (*(volatile unsigned long *)(MAC_BASE_ADDR + 0xFFC)) /* Module ID reg (RO) */ + +/* LCD Controller registers */ +#define LCD_BASE_ADDR 0xFFE10000 /* AHB Peripheral # 4 */ +#define LCD_CFG (*(volatile unsigned long *)(0xE01FC1B8)) +#define LCD_TIMH (*(volatile unsigned long *)(LCD_BASE_ADDR + 0x000)) +#define LCD_TIMV (*(volatile unsigned long *)(LCD_BASE_ADDR + 0x004)) +#define LCD_POL (*(volatile unsigned long *)(LCD_BASE_ADDR + 0x008)) +#define LCD_LE (*(volatile unsigned long *)(LCD_BASE_ADDR + 0x00C)) +#define LCD_UPBASE (*(volatile unsigned long *)(LCD_BASE_ADDR + 0x010)) +#define LCD_LPBASE (*(volatile unsigned long *)(LCD_BASE_ADDR + 0x014)) +#define LCD_CTRL (*(volatile unsigned long *)(LCD_BASE_ADDR + 0x018)) +#define LCD_INTMSK (*(volatile unsigned long *)(LCD_BASE_ADDR + 0x01C)) +#define LCD_INTRAW (*(volatile unsigned long *)(LCD_BASE_ADDR + 0x020)) +#define LCD_INTSTAT (*(volatile unsigned long *)(LCD_BASE_ADDR + 0x024)) +#define LCD_INTCLR (*(volatile unsigned long *)(LCD_BASE_ADDR + 0x028)) +#define LCD_UPCURR (*(volatile unsigned long *)(LCD_BASE_ADDR + 0x02C)) +#define LCD_LPCURR (*(volatile unsigned long *)(LCD_BASE_ADDR + 0x030)) +#define LCD_PAL (*(volatile unsigned long *)(LCD_BASE_ADDR + 0x200)) +#define CRSR_IMG (*(volatile unsigned long *)(LCD_BASE_ADDR + 0x800)) +#define CRSR_CTRL (*(volatile unsigned long *)(LCD_BASE_ADDR + 0xC00)) +#define CRSR_CFG (*(volatile unsigned long *)(LCD_BASE_ADDR + 0xC04)) +#define CRSR_PAL0 (*(volatile unsigned long *)(LCD_BASE_ADDR + 0xC08)) +#define CRSR_PAL1 (*(volatile unsigned long *)(LCD_BASE_ADDR + 0xC0C)) +#define CRSR_XY (*(volatile unsigned long *)(LCD_BASE_ADDR + 0xC10)) +#define CRSR_CLIP (*(volatile unsigned long *)(LCD_BASE_ADDR + 0xC14)) +#define CRSR_INTMSK (*(volatile unsigned long *)(LCD_BASE_ADDR + 0xC20)) +#define CRSR_INTCLR (*(volatile unsigned long *)(LCD_BASE_ADDR + 0xC24)) +#define CRSR_INTRAW (*(volatile unsigned long *)(LCD_BASE_ADDR + 0xC28)) +#define CRSR_INTSTAT (*(volatile unsigned long *)(LCD_BASE_ADDR + 0xC2C)) + +struct rt_hw_register +{ + unsigned long r0; + unsigned long r1; + unsigned long r2; + unsigned long r3; + unsigned long r4; + unsigned long r5; + unsigned long r6; + unsigned long r7; + unsigned long r8; + unsigned long r9; + unsigned long r10; + unsigned long fp; + unsigned long ip; + unsigned long sp; + unsigned long lr; + unsigned long pc; + unsigned long cpsr; + unsigned long ORIG_r0; +}; + +#ifdef __cplusplus +} +#endif + +#endif // __LPC24xx_H + diff --git a/libcpu/arm/lpc24xx/context_rvds.S b/libcpu/arm/lpc24xx/context_rvds.S index a867d7d552..ecd20e4bbe 100644 --- a/libcpu/arm/lpc24xx/context_rvds.S +++ b/libcpu/arm/lpc24xx/context_rvds.S @@ -13,12 +13,12 @@ ; * 2011-07-22 Bernard added thumb mode porting ; */ -NOINT EQU 0xc0 ; disable interrupt in psr
+NOINT EQU 0xc0 ; disable interrupt in psr - AREA |.text|, CODE, READONLY, ALIGN=2
- ARM
- REQUIRE8
- PRESERVE8
+ AREA |.text|, CODE, READONLY, ALIGN=2 + ARM + REQUIRE8 + PRESERVE8 ;/* ; * rt_base_t rt_hw_interrupt_disable(); @@ -27,16 +27,16 @@ rt_hw_interrupt_disable PROC EXPORT rt_hw_interrupt_disable MRS r0, cpsr ORR r1, r0, #NOINT - MSR cpsr_c, r1
+ MSR cpsr_c, r1 BX lr - ENDP
+ ENDP ;/* ; * void rt_hw_interrupt_enable(rt_base_t level); ; */ rt_hw_interrupt_enable PROC EXPORT rt_hw_interrupt_enable - MSR cpsr_c, r0
+ MSR cpsr_c, r0 BX lr ENDP @@ -50,24 +50,24 @@ rt_hw_context_switch PROC STMFD sp!, {lr} ; push pc (lr should be pushed in place of PC) STMFD sp!, {r0-r12, lr} ; push lr & register file - MRS r4, cpsr
- TST lr, #0x01
- BEQ _ARM_MODE
- ORR r4, r4, #0x20 ; it's thumb code
-
-_ARM_MODE
+ MRS r4, cpsr + TST lr, #0x01 + BEQ _ARM_MODE + ORR r4, r4, #0x20 ; it's thumb code + +_ARM_MODE STMFD sp!, {r4} ; push cpsr STR sp, [r0] ; store sp in preempted tasks TCB LDR sp, [r1] ; get new task stack pointer - LDMFD sp!, {r4} ; pop new task cpsr to spsr
- MSR spsr_cxsf, r4
+ LDMFD sp!, {r4} ; pop new task cpsr to spsr + MSR spsr_cxsf, r4 BIC r4, r4, #0x20 ; must be ARM mode MSR cpsr_cxsf, r4 LDMFD sp!, {r0-r12, lr, pc}^ ; pop new task r0-r12, lr & pc, copy spsr to cpsr - ENDP
+ ENDP ;/* ; * void rt_hw_context_switch_to(rt_uint32 to); @@ -77,20 +77,20 @@ rt_hw_context_switch_to PROC EXPORT rt_hw_context_switch_to LDR sp, [r0] ; get new task stack pointer - LDMFD sp!, {r4} ; pop new task cpsr to spsr
- MSR spsr_cxsf, r4
+ LDMFD sp!, {r4} ; pop new task cpsr to spsr + MSR spsr_cxsf, r4 BIC r4, r4, #0x20 ; must be ARM mode MSR cpsr_cxsf, r4 LDMFD sp!, {r0-r12, lr, pc}^ ; pop new task r0-r12, lr & pc, copy spsr to cpsr - ENDP
+ ENDP ;/* ; * void rt_hw_context_switch_interrupt(rt_uint32 from, rt_uint32 to); ; */ IMPORT rt_thread_switch_interrupt_flag IMPORT rt_interrupt_from_thread - IMPORT rt_interrupt_to_thread
+ IMPORT rt_interrupt_to_thread rt_hw_context_switch_interrupt PROC EXPORT rt_hw_context_switch_interrupt @@ -104,8 +104,8 @@ rt_hw_context_switch_interrupt PROC STR r0, [r2] _reswitch LDR r2, =rt_interrupt_to_thread ; set rt_interrupt_to_thread - STR r1, [r2]
+ STR r1, [r2] BX lr - ENDP
-
+ ENDP + END
\ No newline at end of file diff --git a/libcpu/arm/lpc24xx/stack.c b/libcpu/arm/lpc24xx/stack.c index c07176a874..ad6419da4b 100644 --- a/libcpu/arm/lpc24xx/stack.c +++ b/libcpu/arm/lpc24xx/stack.c @@ -12,7 +12,7 @@ * 2008-12-11 XuXinming first version */ #include <rtthread.h> -#include "LPC24xx.h"
+#include "LPC24xx.h" /** * @addtogroup LPC2478 @@ -49,13 +49,13 @@ rt_uint8_t *rt_hw_stack_init(void *tentry, void *parameter, *(--stk) = 0; /* r3 */ *(--stk) = 0; /* r2 */ *(--stk) = 0; /* r1 */ - *(--stk) = (unsigned long)parameter; /* r0 : argument */
-
- /* cpsr */
- if ((rt_uint32_t)tentry & 0x01)
- *(--stk) = SVCMODE | 0x20; /* thumb mode */
- else
- *(--stk) = SVCMODE; /* arm mode */
+ *(--stk) = (unsigned long)parameter; /* r0 : argument */ + + /* cpsr */ + if ((rt_uint32_t)tentry & 0x01) + *(--stk) = SVCMODE | 0x20; /* thumb mode */ + else + *(--stk) = SVCMODE; /* arm mode */ /* return task's current stack address */ return (rt_uint8_t *)stk; diff --git a/libcpu/arm/lpc24xx/start_rvds.S b/libcpu/arm/lpc24xx/start_rvds.S index 162bfecfc2..e49cf2df45 100644 --- a/libcpu/arm/lpc24xx/start_rvds.S +++ b/libcpu/arm/lpc24xx/start_rvds.S @@ -1,1632 +1,1632 @@ -;/*****************************************************************************/
-;/* LPC2400.S: Startup file for Philips LPC2400 device series */
-;/*****************************************************************************/
-;/* <<< Use Configuration Wizard in Context Menu >>> */
-;/*****************************************************************************/
-;/* This file is part of the uVision/ARM development tools. */
-;/* Copyright (c) 2007-2008 Keil - An ARM Company. All rights reserved. */
-;/* This software may only be used under the terms of a valid, current, */
-;/* end user licence from KEIL for a compatible version of KEIL software */
-;/* development tools. Nothing else gives you the right to use this software. */
-;/*****************************************************************************/
-
-;/*
-; * The LPC2400.S code is executed after CPU Reset. This file may be
-; * translated with the following SET symbols. In uVision these SET
-; * symbols are entered under Options - ASM - Define.
-; *
-; * NO_CLOCK_SETUP: when set the startup code will not initialize Clock
-; * (used mostly when clock is already initialized from script .ini
-; * file).
-; *
-; * NO_EMC_SETUP: when set the startup code will not initialize
-; * External Bus Controller.
-; *
-; * RAM_INTVEC: when set the startup code copies exception vectors
-; * from on-chip Flash to on-chip RAM.
-; *
-; * REMAP: when set the startup code initializes the register MEMMAP
-; * which overwrites the settings of the CPU configuration pins. The
-; * startup and interrupt vectors are remapped from:
-; * 0x00000000 default setting (not remapped)
-; * 0x40000000 when RAM_MODE is used
-; * 0x80000000 when EXTMEM_MODE is used
-; *
-; * EXTMEM_MODE: when set the device is configured for code execution
-; * from external memory starting at address 0x80000000.
-; *
-; * RAM_MODE: when set the device is configured for code execution
-; * from on-chip RAM starting at address 0x40000000.
-; */
-
-
-; Standard definitions of Mode bits and Interrupt (I & F) flags in PSRs
-
-Mode_USR EQU 0x10
-Mode_FIQ EQU 0x11
-Mode_IRQ EQU 0x12
-Mode_SVC EQU 0x13
-Mode_ABT EQU 0x17
-Mode_UND EQU 0x1B
-Mode_SYS EQU 0x1F
-I_Bit EQU 0x80 ; when I bit is set, IRQ is disabled
-F_Bit EQU 0x40 ; when F bit is set, FIQ is disabled
-
-;----------------------- Memory Definitions ------------------------------------
-
-; Internal Memory Base Addresses
-FLASH_BASE EQU 0x00000000
-RAM_BASE EQU 0x40000000
-EXTMEM_BASE EQU 0x80000000
-
-; External Memory Base Addresses
-STA_MEM0_BASE EQU 0x80000000
-STA_MEM1_BASE EQU 0x81000000
-STA_MEM2_BASE EQU 0x82000000
-STA_MEM3_BASE EQU 0x83000000
-DYN_MEM0_BASE EQU 0xA0000000
-DYN_MEM1_BASE EQU 0xB0000000
-DYN_MEM2_BASE EQU 0xC0000000
-DYN_MEM3_BASE EQU 0xD0000000
-
-
-;----------------------- Stack and Heap Definitions ----------------------------
-
-;// <h> Stack Configuration (Stack Sizes in Bytes)
-;// <o0> Undefined Mode <0x0-0xFFFFFFFF:8>
-;// <o1> Supervisor Mode <0x0-0xFFFFFFFF:8>
-;// <o2> Abort Mode <0x0-0xFFFFFFFF:8>
-;// <o3> Fast Interrupt Mode <0x0-0xFFFFFFFF:8>
-;// <o4> Interrupt Mode <0x0-0xFFFFFFFF:8>
-;// <o5> User/System Mode <0x0-0xFFFFFFFF:8>
-;// </h>
-
-UND_Stack_Size EQU 0x00000000
-SVC_Stack_Size EQU 0x00000100
-ABT_Stack_Size EQU 0x00000000
-FIQ_Stack_Size EQU 0x00000000
-IRQ_Stack_Size EQU 0x00000100
-USR_Stack_Size EQU 0x00000100
-
-ISR_Stack_Size EQU (UND_Stack_Size + SVC_Stack_Size + ABT_Stack_Size + \
- FIQ_Stack_Size + IRQ_Stack_Size)
-
- AREA STACK, NOINIT, READWRITE, ALIGN=3
-
-Stack_Mem SPACE USR_Stack_Size
-__initial_sp SPACE ISR_Stack_Size
-
-Stack_Top
-
-
-;// <h> Heap Configuration
-;// <o> Heap Size (in Bytes) <0x0-0xFFFFFFFF>
-;// </h>
-
-Heap_Size EQU 0x00000000
-
- AREA HEAP, NOINIT, READWRITE, ALIGN=3
-__heap_base
-Heap_Mem SPACE Heap_Size
-__heap_limit
-
-
-;----------------------- Clock Definitions -------------------------------------
-
-; System Control Block (SCB) Module Definitions
-SCB_BASE EQU 0xE01FC000 ; SCB Base Address
-PLLCON_OFS EQU 0x80 ; PLL Control Offset
-PLLCFG_OFS EQU 0x84 ; PLL Configuration Offset
-PLLSTAT_OFS EQU 0x88 ; PLL Status Offset
-PLLFEED_OFS EQU 0x8C ; PLL Feed Offset
-CCLKCFG_OFS EQU 0x104 ; CPU Clock Divider Reg Offset
-USBCLKCFG_OFS EQU 0x108 ; USB Clock Divider Reg Offset
-CLKSRCSEL_OFS EQU 0x10C ; Clock Source Sel Reg Offset
-SCS_OFS EQU 0x1A0 ; Sys Control and Status Reg Offset
-PCLKSEL0_OFS EQU 0x1A8 ; Periph Clock Sel Reg 0 Offset
-PCLKSEL1_OFS EQU 0x1AC ; Periph Clock Sel Reg 0 Offset
-
-PCON_OFS EQU 0x0C0 ; Power Mode Control Reg Offset
-PCONP_OFS EQU 0x0C4 ; Power Control for Periphs Reg Offset
-
-; Constants
-OSCRANGE EQU (1<<4) ; Oscillator Range Select
-OSCEN EQU (1<<5) ; Main oscillator Enable
-OSCSTAT EQU (1<<6) ; Main Oscillator Status
-PLLCON_PLLE EQU (1<<0) ; PLL Enable
-PLLCON_PLLC EQU (1<<1) ; PLL Connect
-PLLSTAT_M EQU (0x7FFF<<0) ; PLL M Value
-PLLSTAT_N EQU (0xFF<<16) ; PLL N Value
-PLLSTAT_PLOCK EQU (1<<26) ; PLL Lock Status
-
-;// <e> Clock Setup
-;// <h> System Controls and Status Register (SYS)
-;// <o1.4> OSCRANGE: Main Oscillator Range Select
-;// <0=> 1 MHz to 20 MHz
-;// <1=> 15 MHz to 24 MHz
-;// <e1.5> OSCEN: Main Oscillator Enable
-;// </e>
-;// </h>
-;//
-;// <h> PLL Clock Source Select Register (CLKSRCSEL)
-;// <o2.0..1> CLKSRC: PLL Clock Source Selection
-;// <0=> Internal RC oscillator
-;// <1=> Main oscillator
-;// <2=> RTC oscillator
-;// </h>
-;//
-;// <h> PLL Configuration Register (PLLCFG)
-;// <i> PLL_clk = (2* M * PLL_clk_src) / N
-;// <o3.0..14> MSEL: PLL Multiplier Selection
-;// <1-32768><#-1>
-;// <i> M Value
-;// <o3.16..23> NSEL: PLL Divider Selection
-;// <1-256><#-1>
-;// <i> N Value
-;// </h>
-;//
-;// <h> CPU Clock Configuration Register (CCLKCFG)
-;// <o4.0..7> CCLKSEL: Divide Value for CPU Clock from PLL
-;// <1-256><#-1>
-;// </h>
-;//
-;// <h> USB Clock Configuration Register (USBCLKCFG)
-;// <o5.0..3> USBSEL: Divide Value for USB Clock from PLL
-;// <1-16><#-1>
-;// </h>
-;//
-;// <h> Peripheral Clock Selection Register 0 (PCLKSEL0)
-;// <o6.0..1> PCLK_WDT: Peripheral Clock Selection for WDT
-;// <0=> Pclk = Cclk / 4
-;// <1=> Pclk = Cclk
-;// <2=> Pclk = Cclk / 2
-;// <3=> Pclk = Cclk / 8
-;// <o6.2..3> PCLK_TIMER0: Peripheral Clock Selection for TIMER0
-;// <0=> Pclk = Cclk / 4
-;// <1=> Pclk = Cclk
-;// <2=> Pclk = Cclk / 2
-;// <3=> Pclk = Cclk / 8
-;// <o6.4..5> PCLK_TIMER1: Peripheral Clock Selection for TIMER1
-;// <0=> Pclk = Cclk / 4
-;// <1=> Pclk = Cclk
-;// <2=> Pclk = Cclk / 2
-;// <3=> Pclk = Cclk / 8
-;// <o6.6..7> PCLK_UART0: Peripheral Clock Selection for UART0
-;// <0=> Pclk = Cclk / 4
-;// <1=> Pclk = Cclk
-;// <2=> Pclk = Cclk / 2
-;// <3=> Pclk = Cclk / 8
-;// <o6.8..9> PCLK_UART1: Peripheral Clock Selection for UART1
-;// <0=> Pclk = Cclk / 4
-;// <1=> Pclk = Cclk
-;// <2=> Pclk = Cclk / 2
-;// <3=> Pclk = Cclk / 8
-;// <o6.10..11> PCLK_PWM0: Peripheral Clock Selection for PWM0
-;// <0=> Pclk = Cclk / 4
-;// <1=> Pclk = Cclk
-;// <2=> Pclk = Cclk / 2
-;// <3=> Pclk = Cclk / 8
-;// <o6.12..13> PCLK_PWM1: Peripheral Clock Selection for PWM1
-;// <0=> Pclk = Cclk / 4
-;// <1=> Pclk = Cclk
-;// <2=> Pclk = Cclk / 2
-;// <3=> Pclk = Cclk / 8
-;// <o6.14..15> PCLK_I2C0: Peripheral Clock Selection for I2C0
-;// <0=> Pclk = Cclk / 4
-;// <1=> Pclk = Cclk
-;// <2=> Pclk = Cclk / 2
-;// <3=> Pclk = Cclk / 8
-;// <o6.16..17> PCLK_SPI: Peripheral Clock Selection for SPI
-;// <0=> Pclk = Cclk / 4
-;// <1=> Pclk = Cclk
-;// <2=> Pclk = Cclk / 2
-;// <3=> Pclk = Cclk / 8
-;// <o6.18..19> PCLK_RTC: Peripheral Clock Selection for RTC
-;// <0=> Pclk = Cclk / 4
-;// <1=> Pclk = Cclk
-;// <2=> Pclk = Cclk / 2
-;// <3=> Pclk = Cclk / 8
-;// <o6.20..21> PCLK_SSP1: Peripheral Clock Selection for SSP1
-;// <0=> Pclk = Cclk / 4
-;// <1=> Pclk = Cclk
-;// <2=> Pclk = Cclk / 2
-;// <3=> Pclk = Cclk / 8
-;// <o6.22..23> PCLK_DAC: Peripheral Clock Selection for DAC
-;// <0=> Pclk = Cclk / 4
-;// <1=> Pclk = Cclk
-;// <2=> Pclk = Cclk / 2
-;// <3=> Pclk = Cclk / 8
-;// <o6.24..25> PCLK_ADC: Peripheral Clock Selection for ADC
-;// <0=> Pclk = Cclk / 4
-;// <1=> Pclk = Cclk
-;// <2=> Pclk = Cclk / 2
-;// <3=> Pclk = Cclk / 8
-;// <o6.26..27> PCLK_CAN1: Peripheral Clock Selection for CAN1
-;// <0=> Pclk = Cclk / 4
-;// <1=> Pclk = Cclk
-;// <2=> Pclk = Cclk / 2
-;// <3=> Pclk = Cclk / 6
-;// <o6.28..29> PCLK_CAN2: Peripheral Clock Selection for CAN2
-;// <0=> Pclk = Cclk / 4
-;// <1=> Pclk = Cclk
-;// <2=> Pclk = Cclk / 2
-;// <3=> Pclk = Cclk / 6
-;// <o6.30..31> PCLK_ACF: Peripheral Clock Selection for ACF
-;// <0=> Pclk = Cclk / 4
-;// <1=> Pclk = Cclk
-;// <2=> Pclk = Cclk / 2
-;// <3=> Pclk = Cclk / 6
-;// </h>
-;//
-;// <h> Peripheral Clock Selection Register 1 (PCLKSEL1)
-;// <o7.0..1> PCLK_BAT_RAM: Peripheral Clock Selection for the Battery Supported RAM
-;// <0=> Pclk = Cclk / 4
-;// <1=> Pclk = Cclk
-;// <2=> Pclk = Cclk / 2
-;// <3=> Pclk = Cclk / 8
-;// <o7.2..3> PCLK_GPIO: Peripheral Clock Selection for GPIOs
-;// <0=> Pclk = Cclk / 4
-;// <1=> Pclk = Cclk
-;// <2=> Pclk = Cclk / 2
-;// <3=> Pclk = Cclk / 8
-;// <o7.4..5> PCLK_PCB: Peripheral Clock Selection for Pin Connect Block
-;// <0=> Pclk = Cclk / 4
-;// <1=> Pclk = Cclk
-;// <2=> Pclk = Cclk / 2
-;// <3=> Pclk = Cclk / 8
-;// <o7.6..7> PCLK_I2C1: Peripheral Clock Selection for I2C1
-;// <0=> Pclk = Cclk / 4
-;// <1=> Pclk = Cclk
-;// <2=> Pclk = Cclk / 2
-;// <3=> Pclk = Cclk / 8
-;// <o7.10..11> PCLK_SSP0: Peripheral Clock Selection for SSP0
-;// <0=> Pclk = Cclk / 4
-;// <1=> Pclk = Cclk
-;// <2=> Pclk = Cclk / 2
-;// <3=> Pclk = Cclk / 8
-;// <o7.12..13> PCLK_TIMER2: Peripheral Clock Selection for TIMER2
-;// <0=> Pclk = Cclk / 4
-;// <1=> Pclk = Cclk
-;// <2=> Pclk = Cclk / 2
-;// <3=> Pclk = Cclk / 8
-;// <o7.14..15> PCLK_TIMER3: Peripheral Clock Selection for TIMER3
-;// <0=> Pclk = Cclk / 4
-;// <1=> Pclk = Cclk
-;// <2=> Pclk = Cclk / 2
-;// <3=> Pclk = Cclk / 8
-;// <o7.16..17> PCLK_UART2: Peripheral Clock Selection for UART2
-;// <0=> Pclk = Cclk / 4
-;// <1=> Pclk = Cclk
-;// <2=> Pclk = Cclk / 2
-;// <3=> Pclk = Cclk / 8
-;// <o7.18..19> PCLK_UART3: Peripheral Clock Selection for UART3
-;// <0=> Pclk = Cclk / 4
-;// <1=> Pclk = Cclk
-;// <2=> Pclk = Cclk / 2
-;// <3=> Pclk = Cclk / 8
-;// <o7.20..21> PCLK_I2C2: Peripheral Clock Selection for I2C2
-;// <0=> Pclk = Cclk / 4
-;// <1=> Pclk = Cclk
-;// <2=> Pclk = Cclk / 2
-;// <3=> Pclk = Cclk / 8
-;// <o7.22..23> PCLK_I2S: Peripheral Clock Selection for I2S
-;// <0=> Pclk = Cclk / 4
-;// <1=> Pclk = Cclk
-;// <2=> Pclk = Cclk / 2
-;// <3=> Pclk = Cclk / 8
-;// <o7.24..25> PCLK_MCI: Peripheral Clock Selection for MCI
-;// <0=> Pclk = Cclk / 4
-;// <1=> Pclk = Cclk
-;// <2=> Pclk = Cclk / 2
-;// <3=> Pclk = Cclk / 8
-;// <o7.28..29> PCLK_SYSCON: Peripheral Clock Selection for System Control Block
-;// <0=> Pclk = Cclk / 4
-;// <1=> Pclk = Cclk
-;// <2=> Pclk = Cclk / 2
-;// <3=> Pclk = Cclk / 8
-;// </h>
-;// </e>
-CLOCK_SETUP EQU 1
-SCS_Val EQU 0x00000020
-CLKSRCSEL_Val EQU 0x00000001
-PLLCFG_Val EQU 0x0000000B
-CCLKCFG_Val EQU 0x00000004
-USBCLKCFG_Val EQU 0x00000005
-PCLKSEL0_Val EQU 0x00000000
-PCLKSEL1_Val EQU 0x00000000
-
-
-;----------------------- Memory Accelerator Module (MAM) Definitions -----------
-
-MAM_BASE EQU 0xE01FC000 ; MAM Base Address
-MAMCR_OFS EQU 0x00 ; MAM Control Offset
-MAMTIM_OFS EQU 0x04 ; MAM Timing Offset
-
-;// <e> MAM Setup
-;// <o1.0..1> MAM Control
-;// <0=> Disabled
-;// <1=> Partially Enabled
-;// <2=> Fully Enabled
-;// <i> Mode
-;// <o2.0..2> MAM Timing
-;// <0=> Reserved <1=> 1 <2=> 2 <3=> 3
-;// <4=> 4 <5=> 5 <6=> 6 <7=> 7
-;// <i> Fetch Cycles
-;// </e>
-MAM_SETUP EQU 1
-MAMCR_Val EQU 0x00000002
-MAMTIM_Val EQU 0x00000004
-
-
-;----------------------- Pin Connect Block Definitions -------------------------
-
-PCB_BASE EQU 0xE002C000 ; PCB Base Address
-PINSEL0_OFS EQU 0x00 ; PINSEL0 Address Offset
-PINSEL1_OFS EQU 0x04 ; PINSEL1 Address Offset
-PINSEL2_OFS EQU 0x08 ; PINSEL2 Address Offset
-PINSEL3_OFS EQU 0x0C ; PINSEL3 Address Offset
-PINSEL4_OFS EQU 0x10 ; PINSEL4 Address Offset
-PINSEL5_OFS EQU 0x14 ; PINSEL5 Address Offset
-PINSEL6_OFS EQU 0x18 ; PINSEL6 Address Offset
-PINSEL7_OFS EQU 0x1C ; PINSEL7 Address Offset
-PINSEL8_OFS EQU 0x20 ; PINSEL8 Address Offset
-PINSEL9_OFS EQU 0x24 ; PINSEL9 Address Offset
-PINSEL10_OFS EQU 0x28 ; PINSEL10 Address Offset
-
-
-;----------------------- External Memory Controller (EMC) Definitons -----------
-
-EMC_BASE EQU 0xFFE08000 ; EMC Base Address
-
-EMC_CTRL_OFS EQU 0x000
-EMC_STAT_OFS EQU 0x004
-EMC_CONFIG_OFS EQU 0x008
-EMC_DYN_CTRL_OFS EQU 0x020
-EMC_DYN_RFSH_OFS EQU 0x024
-EMC_DYN_RD_CFG_OFS EQU 0x028
-EMC_DYN_RP_OFS EQU 0x030
-EMC_DYN_RAS_OFS EQU 0x034
-EMC_DYN_SREX_OFS EQU 0x038
-EMC_DYN_APR_OFS EQU 0x03C
-EMC_DYN_DAL_OFS EQU 0x040
-EMC_DYN_WR_OFS EQU 0x044
-EMC_DYN_RC_OFS EQU 0x048
-EMC_DYN_RFC_OFS EQU 0x04C
-EMC_DYN_XSR_OFS EQU 0x050
-EMC_DYN_RRD_OFS EQU 0x054
-EMC_DYN_MRD_OFS EQU 0x058
-EMC_DYN_CFG0_OFS EQU 0x100
-EMC_DYN_RASCAS0_OFS EQU 0x104
-EMC_DYN_CFG1_OFS EQU 0x140
-EMC_DYN_RASCAS1_OFS EQU 0x144
-EMC_DYN_CFG2_OFS EQU 0x160
-EMC_DYN_RASCAS2_OFS EQU 0x164
-EMC_DYN_CFG3_OFS EQU 0x180
-EMC_DYN_RASCAS3_OFS EQU 0x184
-EMC_STA_CFG0_OFS EQU 0x200
-EMC_STA_WWEN0_OFS EQU 0x204
-EMC_STA_WOEN0_OFS EQU 0x208
-EMC_STA_WRD0_OFS EQU 0x20C
-EMC_STA_WPAGE0_OFS EQU 0x210
-EMC_STA_WWR0_OFS EQU 0x214
-EMC_STA_WTURN0_OFS EQU 0x218
-EMC_STA_CFG1_OFS EQU 0x220
-EMC_STA_WWEN1_OFS EQU 0x224
-EMC_STA_WOEN1_OFS EQU 0x228
-EMC_STA_WRD1_OFS EQU 0x22C
-EMC_STA_WPAGE1_OFS EQU 0x230
-EMC_STA_WWR1_OFS EQU 0x234
-EMC_STA_WTURN1_OFS EQU 0x238
-EMC_STA_CFG2_OFS EQU 0x240
-EMC_STA_WWEN2_OFS EQU 0x244
-EMC_STA_WOEN2_OFS EQU 0x248
-EMC_STA_WRD2_OFS EQU 0x24C
-EMC_STA_WPAGE2_OFS EQU 0x250
-EMC_STA_WWR2_OFS EQU 0x254
-EMC_STA_WTURN2_OFS EQU 0x258
-EMC_STA_CFG3_OFS EQU 0x260
-EMC_STA_WWEN3_OFS EQU 0x264
-EMC_STA_WOEN3_OFS EQU 0x268
-EMC_STA_WRD3_OFS EQU 0x26C
-EMC_STA_WPAGE3_OFS EQU 0x270
-EMC_STA_WWR3_OFS EQU 0x274
-EMC_STA_WTURN3_OFS EQU 0x278
-EMC_STA_EXT_W_OFS EQU 0x880
-
-; Constants
-NORMAL_CMD EQU (0x0 << 7) ; NORMAL Command
-MODE_CMD EQU (0x1 << 7) ; MODE Command
-PALL_CMD EQU (0x2 << 7) ; Precharge All Command
-NOP_CMD EQU (0x3 << 7) ; NOP Command
-
-BUFEN_Const EQU (1 << 19) ; Buffer enable bit
-EMC_PCONP_Const EQU (1 << 11) ; PCONP val to enable power for EMC
-
-; External Memory Pins definitions
-; pin functions for SDRAM, NOR and NAND flash interfacing
-EMC_PINSEL5_Val EQU 0x05010115 ; !CAS, !RAS, CLKOUT0, !DYCS0, DQMOUT0, DQMOUT1
-EMC_PINSEL6_Val EQU 0x55555555 ; D0 .. D15
-EMC_PINSEL8_Val EQU 0x55555555 ; A0 .. A15
-EMC_PINSEL9_Val EQU 0x50055555; ; A16 .. A23, !OE, !WE, !CS0, !CS1
-
-;// External Memory Controller Setup (EMC) ---------------------------------
-;// <e> External Memory Controller Setup (EMC)
-EMC_SETUP EQU 0
-
-;// <h> EMC Control Register (EMCControl)
-;// <i> Controls operation of the memory controller
-;// <o0.2> L: Low-power mode enable
-;// <o0.1> M: Address mirror enable
-;// <o0.0> E: EMC enable
-;// </h>
-EMC_CTRL_Val EQU 0x00000001
-
-;// <h> EMC Configuration Register (EMCConfig)
-;// <i> Configures operation of the memory controller
-;// <o0.8> CCLK: CLKOUT ratio
-;// <0=> 1:1
-;// <1=> 1:2
-;// <o0.0> Endian mode
-;// <0=> Little-endian
-;// <1=> Big-endian
-;// </h>
-EMC_CONFIG_Val EQU 0x00000000
-
-;// Dynamic Memory Interface Setup ---------------------------------------
-;// <e> Dynamic Memory Interface Setup
-EMC_DYNAMIC_SETUP EQU 1
-
-;// <h> Dynamic Memory Refresh Timer Register (EMCDynamicRefresh)
-;// <i> Configures dynamic memory refresh operation
-;// <o0.0..10> REFRESH: Refresh timer <0x000-0x7FF>
-;// <i> 0 = refresh disabled, 0x01-0x7FF: value * 16 CCLKS
-;// </h>
-EMC_DYN_RFSH_Val EQU 0x0000001C
-
-;// <h> Dynamic Memory Read Configuration Register (EMCDynamicReadConfig)
-;// <i> Configures the dynamic memory read strategy
-;// <o0.0..1> RD: Read data strategy
-;// <0=> Clock out delayed strategy
-;// <1=> Command delayed strategy
-;// <2=> Command delayed strategy plus one clock cycle
-;// <3=> Command delayed strategy plus two clock cycles
-;// </h>
-EMC_DYN_RD_CFG_Val EQU 0x00000001
-
-;// <h> Dynamic Memory Timings
-;// <h> Dynamic Memory Percentage Command Period Register (EMCDynamictRP)
-;// <o0.0..3> tRP: Precharge command period <1-16> <#-1>
-;// <i> The delay is in EMCCLK cycles
-;// <i> This value is normally found in SDRAM data sheets as tRP
-;// </h>
-;// <h> Dynamic Memory Active to Precharge Command Period Register (EMCDynamictRAS)
-;// <o1.0..3> tRAS: Active to precharge command period <1-16> <#-1>
-;// <i> The delay is in EMCCLK cycles
-;// <i> This value is normally found in SDRAM data sheets as tRAS
-;// </h>
-;// <h> Dynamic Memory Self-refresh Exit Time Register (EMCDynamictSREX)
-;// <o2.0..3> tSREX: Self-refresh exit time <1-16> <#-1>
-;// <i> The delay is in CCLK cycles
-;// <i> This value is normally found in SDRAM data sheets as tSREX,
-;// <i> for devices without this parameter you use the same value as tXSR
-;// </h>
-;// <h> Dynamic Memory Last Data Out to Active Time Register (EMCDynamictAPR)
-;// <o3.0..3> tAPR: Last-data-out to active command time <1-16> <#-1>
-;// <i> The delay is in CCLK cycles
-;// <i> This value is normally found in SDRAM data sheets as tAPR
-;// </h>
-;// <h> Dynamic Memory Data-in to Active Command Time Register (EMCDynamictDAL)
-;// <o4.0..3> tDAL: Data-in to active command time <1-16> <#-1>
-;// <i> The delay is in CCLK cycles
-;// <i> This value is normally found in SDRAM data sheets as tDAL or tAPW
-;// </h>
-;// <h> Dynamic Memory Write Recovery Time Register (EMCDynamictWR)
-;// <o5.0..3> tWR: Write recovery time <1-16> <#-1>
-;// <i> The delay is in CCLK cycles
-;// <i> This value is normally found in SDRAM data sheets as tWR, tDPL, tRWL, or tRDL
-;// </h>
-;// <h> Dynamic Memory Active to Active Command Period Register (EMCDynamictRC)
-;// <o6.0..4> tRC: Active to active command period <1-32> <#-1>
-;// <i> The delay is in CCLK cycles
-;// <i> This value is normally found in SDRAM data sheets as tRC
-;// </h>
-;// <h> Dynamic Memory Auto-refresh Period Register (EMCDynamictRFC)
-;// <o7.0..4> tRFC: Auto-refresh period and auto-refresh to active command period <1-32> <#-1>
-;// <i> The delay is in CCLK cycles
-;// <i> This value is normally found in SDRAM data sheets as tRFC or tRC
-;// </h>
-;// <h> Dynamic Memory Exit Self-refresh Register (EMCDynamictXSR)
-;// <o8.0..4> tXSR: Exit self-refresh to active command time <1-32> <#-1>
-;// <i> The delay is in CCLK cycles
-;// <i> This value is normally found in SDRAM data sheets as tXSR
-;// </h>
-;// <h> Dynamic Memory Active Bank A to Active Bank B Time Register (EMCDynamicRRD)
-;// <o9.0..3> tRRD: Active bank A to active bank B latency <1-16> <#-1>
-;// <i> The delay is in CCLK cycles
-;// <i> This value is normally found in SDRAM data sheets as tRRD
-;// </h>
-;// <h> Dynamic Memory Load Mode Register to Active Command Time (EMCDynamictMRD)
-;// <o10.0..3> tMRD: Load mode register to active command time <1-16> <#-1>
-;// <i> The delay is in CCLK cycles
-;// <i> This value is normally found in SDRAM data sheets as tMRD or tRSA
-;// </h>
-;// </h>
-EMC_DYN_RP_Val EQU 0x00000002
-EMC_DYN_RAS_Val EQU 0x00000003
-EMC_DYN_SREX_Val EQU 0x00000007
-EMC_DYN_APR_Val EQU 0x00000002
-EMC_DYN_DAL_Val EQU 0x00000005
-EMC_DYN_WR_Val EQU 0x00000001
-EMC_DYN_RC_Val EQU 0x00000005
-EMC_DYN_RFC_Val EQU 0x00000005
-EMC_DYN_XSR_Val EQU 0x00000007
-EMC_DYN_RRD_Val EQU 0x00000001
-EMC_DYN_MRD_Val EQU 0x00000002
-
-;// <e> Configure External Bus Behaviour for Dynamic CS0 Area
-EMC_DYNCS0_SETUP EQU 1
-
-;// <h> Dynamic Memory Configuration Register (EMCDynamicConfig0)
-;// <i> Defines the configuration information for the dynamic memory CS0
-;// <o0.20> P: Write protect
-;// <o0.19> B: Buffer enable
-;// <o0.14> AM 14: External bus data width
-;// <0=> 16 bit
-;// <1=> 32 bit
-;// <o0.12> AM 12: External bus memory type
-;// <0=> High-performance
-;// <1=> Low-power SDRAM
-;// <o0.7..11> AM 11..7: External bus address mapping (Row, Bank, Column)
-;// <0x00=> 16 Mb = 2MB (2Mx8), 2 banks, row length = 11, column length = 9
-;// <0x01=> 16 Mb = 2MB (1Mx16), 2 banks, row length = 11, column length = 8
-;// <0x04=> 64 Mb = 8MB (8Mx8), 4 banks, row length = 12, column length = 9
-;// <0x05=> 64 Mb = 8MB (4Mx16), 4 banks, row length = 12, column length = 8
-;// <0x08=> 128 Mb = 16MB (16Mx8), 4 banks, row length = 12, column length = 10
-;// <0x09=> 128 Mb = 16MB (8Mx16), 4 banks, row length = 12, column length = 9
-;// <0x0C=> 256 Mb = 32MB (32Mx8), 4 banks, row length = 13, column length = 10
-;// <0x0D=> 256 Mb = 32MB (16Mx16), 4 banks, row length = 13, column length = 9
-;// <0x10=> 512 Mb = 64MB (64Mx8), 4 banks, row length = 13, column length = 11
-;// <0x11=> 512 Mb = 64MB (32Mx16), 4 banks, row length = 13, column length = 10
-;// <o0.3..4> MD: Memory device
-;// <0=> SDRAM
-;// <1=> Low-power SDRAM
-;// <2=> Micron SyncFlash
-;// </h>
-EMC_DYN_CFG0_Val EQU 0x00080680
-
-;// <h> Dynamic Memory RAS & CAS Delay register (EMCDynamicRASCAS0)
-;// <i> Controls the RAS and CAS latencies for the dynamic memory CS0
-;// <o0.8..9> CAS: CAS latency
-;// <1=> One CCLK cycle
-;// <2=> Two CCLK cycles
-;// <3=> Three CCLK cycles
-;// <o0.0..1> RAS: RAS latency (active to read/write delay)
-;// <1=> One CCLK cycle
-;// <2=> Two CCLK cycles
-;// <3=> Three CCLK cycles
-;// </h>
-EMC_DYN_RASCAS0_Val EQU 0x00000303
-
-;// </e> End of Dynamic Setup for CS0 Area
-
-
-;// <e> Configure External Bus Behaviour for Dynamic CS1 Area
-EMC_DYNCS1_SETUP EQU 0
-
-;// <h> Dynamic Memory Configuration Register (EMCDynamicConfig1)
-;// <i> Defines the configuration information for the dynamic memory CS1
-;// <o0.20> P: Write protect
-;// <o0.19> B: Buffer enable
-;// <o0.14> AM 14: External bus data width
-;// <0=> 16 bit
-;// <1=> 32 bit
-;// <o0.12> AM 12: External bus memory type
-;// <0=> High-performance
-;// <1=> Low-power SDRAM
-;// <o0.7..11> AM 11..7: External bus address mapping (Row, Bank, Column)
-;// <0x00=> 16 Mb = 2MB (2Mx8), 2 banks, row length = 11, column length = 9
-;// <0x01=> 16 Mb = 2MB (1Mx16), 2 banks, row length = 11, column length = 8
-;// <0x04=> 64 Mb = 8MB (8Mx8), 4 banks, row length = 12, column length = 9
-;// <0x05=> 64 Mb = 8MB (4Mx16), 4 banks, row length = 12, column length = 8
-;// <0x08=> 128 Mb = 16MB (16Mx8), 4 banks, row length = 12, column length = 10
-;// <0x09=> 128 Mb = 16MB (8Mx16), 4 banks, row length = 12, column length = 9
-;// <0x0C=> 256 Mb = 32MB (32Mx8), 4 banks, row length = 13, column length = 10
-;// <0x0D=> 256 Mb = 32MB (16Mx16), 4 banks, row length = 13, column length = 9
-;// <0x10=> 512 Mb = 64MB (64Mx8), 4 banks, row length = 13, column length = 11
-;// <0x11=> 512 Mb = 64MB (32Mx16), 4 banks, row length = 13, column length = 10
-;// <o0.3..4> MD: Memory device
-;// <0=> SDRAM
-;// <1=> Low-power SDRAM
-;// <2=> Micron SyncFlash
-;// </h>
-EMC_DYN_CFG1_Val EQU 0x00000000
-
-;// <h> Dynamic Memory RAS & CAS Delay register (EMCDynamicRASCAS1)
-;// <i> Controls the RAS and CAS latencies for the dynamic memory CS1
-;// <o0.8..9> CAS: CAS latency
-;// <1=> One CCLK cycle
-;// <2=> Two CCLK cycles
-;// <3=> Three CCLK cycles
-;// <o0.0..1> RAS: RAS latency (active to read/write delay)
-;// <1=> One CCLK cycle
-;// <2=> Two CCLK cycles
-;// <3=> Three CCLK cycles
-;// </h>
-EMC_DYN_RASCAS1_Val EQU 0x00000303
-
-;// </e> End of Dynamic Setup for CS1 Area
-
-;// <e> Configure External Bus Behaviour for Dynamic CS2 Area
-EMC_DYNCS2_SETUP EQU 0
-
-;// <h> Dynamic Memory Configuration Register (EMCDynamicConfig2)
-;// <i> Defines the configuration information for the dynamic memory CS2
-;// <o0.20> P: Write protect
-;// <o0.19> B: Buffer enable
-;// <o0.14> AM 14: External bus data width
-;// <0=> 16 bit
-;// <1=> 32 bit
-;// <o0.12> AM 12: External bus memory type
-;// <0=> High-performance
-;// <1=> Low-power SDRAM
-;// <o0.7..11> AM 11..7: External bus address mapping (Row, Bank, Column)
-;// <0x00=> 16 Mb = 2MB (2Mx8), 2 banks, row length = 11, column length = 9
-;// <0x01=> 16 Mb = 2MB (1Mx16), 2 banks, row length = 11, column length = 8
-;// <0x04=> 64 Mb = 8MB (8Mx8), 4 banks, row length = 12, column length = 9
-;// <0x05=> 64 Mb = 8MB (4Mx16), 4 banks, row length = 12, column length = 8
-;// <0x08=> 128 Mb = 16MB (16Mx8), 4 banks, row length = 12, column length = 10
-;// <0x09=> 128 Mb = 16MB (8Mx16), 4 banks, row length = 12, column length = 9
-;// <0x0C=> 256 Mb = 32MB (32Mx8), 4 banks, row length = 13, column length = 10
-;// <0x0D=> 256 Mb = 32MB (16Mx16), 4 banks, row length = 13, column length = 9
-;// <0x10=> 512 Mb = 64MB (64Mx8), 4 banks, row length = 13, column length = 11
-;// <0x11=> 512 Mb = 64MB (32Mx16), 4 banks, row length = 13, column length = 10
-;// <o0.3..4> MD: Memory device
-;// <0=> SDRAM
-;// <1=> Low-power SDRAM
-;// <2=> Micron SyncFlash
-;// </h>
-EMC_DYN_CFG2_Val EQU 0x00000000
-
-;// <h> Dynamic Memory RAS & CAS Delay register (EMCDynamicRASCAS2)
-;// <i> Controls the RAS and CAS latencies for the dynamic memory CS2
-;// <o0.8..9> CAS: CAS latency
-;// <1=> One CCLK cycle
-;// <2=> Two CCLK cycles
-;// <3=> Three CCLK cycles
-;// <o0.0..1> RAS: RAS latency (active to read/write delay)
-;// <1=> One CCLK cycle
-;// <2=> Two CCLK cycles
-;// <3=> Three CCLK cycles
-;// </h>
-EMC_DYN_RASCAS2_Val EQU 0x00000303
-
-;// </e> End of Dynamic Setup for CS2 Area
-
-;// <e> Configure External Bus Behaviour for Dynamic CS3 Area
-EMC_DYNCS3_SETUP EQU 0
-
-;// <h> Dynamic Memory Configuration Register (EMCDynamicConfig3)
-;// <i> Defines the configuration information for the dynamic memory CS3
-;// <o0.20> P: Write protect
-;// <o0.19> B: Buffer enable
-;// <o0.14> AM 14: External bus data width
-;// <0=> 16 bit
-;// <1=> 32 bit
-;// <o0.12> AM 12: External bus memory type
-;// <0=> High-performance
-;// <1=> Low-power SDRAM
-;// <o0.7..11> AM 11..7: External bus address mapping (Row, Bank, Column)
-;// <0x00=> 16 Mb = 2MB (2Mx8), 2 banks, row length = 11, column length = 9
-;// <0x01=> 16 Mb = 2MB (1Mx16), 2 banks, row length = 11, column length = 8
-;// <0x04=> 64 Mb = 8MB (8Mx8), 4 banks, row length = 12, column length = 9
-;// <0x05=> 64 Mb = 8MB (4Mx16), 4 banks, row length = 12, column length = 8
-;// <0x08=> 128 Mb = 16MB (16Mx8), 4 banks, row length = 12, column length = 10
-;// <0x09=> 128 Mb = 16MB (8Mx16), 4 banks, row length = 12, column length = 9
-;// <0x0C=> 256 Mb = 32MB (32Mx8), 4 banks, row length = 13, column length = 10
-;// <0x0D=> 256 Mb = 32MB (16Mx16), 4 banks, row length = 13, column length = 9
-;// <0x10=> 512 Mb = 64MB (64Mx8), 4 banks, row length = 13, column length = 11
-;// <0x11=> 512 Mb = 64MB (32Mx16), 4 banks, row length = 13, column length = 10
-;// <o0.3..4> MD: Memory device
-;// <0=> SDRAM
-;// <1=> Low-power SDRAM
-;// <2=> Micron SyncFlash
-;// </h>
-EMC_DYN_CFG3_Val EQU 0x00000000
-
-;// <h> Dynamic Memory RAS & CAS Delay register (EMCDynamicRASCAS3)
-;// <i> Controls the RAS and CAS latencies for the dynamic memory CS3
-;// <o0.8..9> CAS: CAS latency
-;// <1=> One CCLK cycle
-;// <2=> Two CCLK cycles
-;// <3=> Three CCLK cycles
-;// <o0.0..1> RAS: RAS latency (active to read/write delay)
-;// <1=> One CCLK cycle
-;// <2=> Two CCLK cycles
-;// <3=> Three CCLK cycles
-;// </h>
-EMC_DYN_RASCAS3_Val EQU 0x00000303
-
-;// </e> End of Dynamic Setup for CS3 Area
-
-;// </e> End of Dynamic Setup
-
-;// Static Memory Interface Setup ----------------------------------------
-;// <e> Static Memory Interface Setup
-EMC_STATIC_SETUP EQU 1
-
-;// Configure External Bus Behaviour for Static CS0 Area ---------------
-;// <e> Configure External Bus Behaviour for Static CS0 Area
-EMC_STACS0_SETUP EQU 1
-
-;// <h> Static Memory Configuration Register (EMCStaticConfig0)
-;// <i> Defines the configuration information for the static memory CS0
-;// <o0.20> WP: Write protect
-;// <o0.19> B: Buffer enable
-;// <o0.8> EW: Extended wait enable
-;// <o0.7> PB: Byte lane state
-;// <0=> For reads BLSn are HIGH, for writes BLSn are LOW
-;// <1=> For reads BLSn are LOW, for writes BLSn are LOW
-;// <o0.6> PC: Chip select polarity
-;// <0=> Active LOW chip select
-;// <1=> Active HIGH chip select
-;// <o0.3> PM: Page mode enable
-;// <o0.0..1> MW: Memory width
-;// <0=> 8 bit
-;// <1=> 16 bit
-;// <2=> 32 bit
-;// </h>
-EMC_STA_CFG0_Val EQU 0x00000081
-
-;// <h> Static Memory Write Enable Delay Register (EMCStaticWaitWen0)
-;// <i> Selects the delay from CS0 to write enable
-;// <o.0..3> WAITWEN: Wait write enable <1-16> <#-1>
-;// <i> The delay is in CCLK cycles
-;// </h>
-EMC_STA_WWEN0_Val EQU 0x00000002
-
-;// <h> Static Memory Output Enable Delay register (EMCStaticWaitOen0)
-;// <i> Selects the delay from CS0 or address change, whichever is later, to output enable
-;// <o.0..3> WAITOEN: Wait output enable <0-15>
-;// <i> The delay is in CCLK cycles
-;// </h>
-EMC_STA_WOEN0_Val EQU 0x00000002
-
-;// <h> Static Memory Read Delay Register (EMCStaticWaitRd0)
-;// <i> Selects the delay from CS0 to a read access
-;// <o.0..4> WAITRD: Non-page mode read wait states or asynchronous page mode read first access wait states <1-32> <#-1>
-;// <i> The delay is in CCLK cycles
-;// </h>
-EMC_STA_WRD0_Val EQU 0x0000001F
-
-;// <h> Static Memory Page Mode Read Delay Register (EMCStaticWaitPage0)
-;// <i> Selects the delay for asynchronous page mode sequential accesses for CS0
-;// <o.0..4> WAITPAGE: Asynchronous page mode read after the first read wait states <1-32> <#-1>
-;// <i> The delay is in CCLK cycles
-;// </h>
-EMC_STA_WPAGE0_Val EQU 0x0000001F
-
-;// <h> Static Memory Write Delay Register (EMCStaticWaitWr0)
-;// <i> Selects the delay from CS0 to a write access
-;// <o.0..4> WAITWR: Write wait states <2-33> <#-2>
-;// <i> The delay is in CCLK cycles
-;// </h>
-EMC_STA_WWR0_Val EQU 0x0000001F
-
-;// <h> Static Memory Turn Round Delay Register (EMCStaticWaitTurn0)
-;// <i> Selects the number of bus turnaround cycles for CS0
-;// <o.0..4> WAITTURN: Bus turnaround cycles <1-16> <#-1>
-;// <i> The delay is in CCLK cycles
-;// </h>
-EMC_STA_WTURN0_Val EQU 0x0000000F
-
-;// </e> End of Static Setup for Static CS0 Area
-
-;// Configure External Bus Behaviour for Static CS1 Area ---------------
-;// <e> Configure External Bus Behaviour for Static CS1 Area
-EMC_STACS1_SETUP EQU 0
-
-;// <h> Static Memory Configuration Register (EMCStaticConfig1)
-;// <i> Defines the configuration information for the static memory CS1
-;// <o0.20> WP: Write protect
-;// <o0.19> B: Buffer enable
-;// <o0.8> EW: Extended wait enable
-;// <o0.7> PB: Byte lane state
-;// <0=> For reads BLSn are HIGH, for writes BLSn are LOW
-;// <1=> For reads BLSn are LOW, for writes BLSn are LOW
-;// <o0.6> PC: Chip select polarity
-;// <0=> Active LOW chip select
-;// <1=> Active HIGH chip select
-;// <o0.3> PM: Page mode enable
-;// <o0.0..1> MW: Memory width
-;// <0=> 8 bit
-;// <1=> 16 bit
-;// <2=> 32 bit
-;// </h>
-EMC_STA_CFG1_Val EQU 0x00000000
-
-;// <h> Static Memory Write Enable Delay Register (EMCStaticWaitWen1)
-;// <i> Selects the delay from CS1 to write enable
-;// <o.0..3> WAITWEN: Wait write enable <1-16> <#-1>
-;// <i> The delay is in CCLK cycles
-;// </h>
-EMC_STA_WWEN1_Val EQU 0x00000000
-
-;// <h> Static Memory Output Enable Delay register (EMCStaticWaitOen1)
-;// <i> Selects the delay from CS1 or address change, whichever is later, to output enable
-;// <o.0..3> WAITOEN: Wait output enable <0-15>
-;// <i> The delay is in CCLK cycles
-;// </h>
-EMC_STA_WOEN1_Val EQU 0x00000000
-
-;// <h> Static Memory Read Delay Register (EMCStaticWaitRd1)
-;// <i> Selects the delay from CS1 to a read access
-;// <o.0..4> WAITRD: Non-page mode read wait states or asynchronous page mode read first access wait states <1-32> <#-1>
-;// <i> The delay is in CCLK cycles
-;// </h>
-EMC_STA_WRD1_Val EQU 0x0000001F
-
-;// <h> Static Memory Page Mode Read Delay Register (EMCStaticWaitPage0)
-;// <i> Selects the delay for asynchronous page mode sequential accesses for CS1
-;// <o.0..4> WAITPAGE: Asynchronous page mode read after the first read wait states <1-32> <#-1>
-;// <i> The delay is in CCLK cycles
-;// </h>
-EMC_STA_WPAGE1_Val EQU 0x0000001F
-
-;// <h> Static Memory Write Delay Register (EMCStaticWaitWr1)
-;// <i> Selects the delay from CS1 to a write access
-;// <o.0..4> WAITWR: Write wait states <2-33> <#-2>
-;// <i> The delay is in CCLK cycles
-;// </h>
-EMC_STA_WWR1_Val EQU 0x0000001F
-
-;// <h> Static Memory Turn Round Delay Register (EMCStaticWaitTurn1)
-;// <i> Selects the number of bus turnaround cycles for CS1
-;// <o.0..4> WAITTURN: Bus turnaround cycles <1-16> <#-1>
-;// <i> The delay is in CCLK cycles
-;// </h>
-EMC_STA_WTURN1_Val EQU 0x0000000F
-
-;// </e> End of Static Setup for Static CS1 Area
-
-;// Configure External Bus Behaviour for Static CS2 Area ---------------
-;// <e> Configure External Bus Behaviour for Static CS2 Area
-EMC_STACS2_SETUP EQU 0
-
-;// <h> Static Memory Configuration Register (EMCStaticConfig2)
-;// <i> Defines the configuration information for the static memory CS2
-;// <o0.20> WP: Write protect
-;// <o0.19> B: Buffer enable
-;// <o0.8> EW: Extended wait enable
-;// <o0.7> PB: Byte lane state
-;// <0=> For reads BLSn are HIGH, for writes BLSn are LOW
-;// <1=> For reads BLSn are LOW, for writes BLSn are LOW
-;// <o0.6> PC: Chip select polarity
-;// <0=> Active LOW chip select
-;// <1=> Active HIGH chip select
-;// <o0.3> PM: Page mode enable
-;// <o0.0..1> MW: Memory width
-;// <0=> 8 bit
-;// <1=> 16 bit
-;// <2=> 32 bit
-;// </h>
-EMC_STA_CFG2_Val EQU 0x00000000
-
-;// <h> Static Memory Write Enable Delay Register (EMCStaticWaitWen2)
-;// <i> Selects the delay from CS2 to write enable
-;// <o.0..3> WAITWEN: Wait write enable <1-16> <#-1>
-;// <i> The delay is in CCLK cycles
-;// </h>
-EMC_STA_WWEN2_Val EQU 0x00000000
-
-;// <h> Static Memory Output Enable Delay register (EMCStaticWaitOen2)
-;// <i> Selects the delay from CS2 or address change, whichever is later, to output enable
-;// <o.0..3> WAITOEN: Wait output enable <0-15>
-;// <i> The delay is in CCLK cycles
-;// </h>
-EMC_STA_WOEN2_Val EQU 0x00000000
-
-;// <h> Static Memory Read Delay Register (EMCStaticWaitRd2)
-;// <i> Selects the delay from CS2 to a read access
-;// <o.0..4> WAITRD: Non-page mode read wait states or asynchronous page mode read first access wait states <1-32> <#-1>
-;// <i> The delay is in CCLK cycles
-;// </h>
-EMC_STA_WRD2_Val EQU 0x0000001F
-
-;// <h> Static Memory Page Mode Read Delay Register (EMCStaticWaitPage2)
-;// <i> Selects the delay for asynchronous page mode sequential accesses for CS2
-;// <o.0..4> WAITPAGE: Asynchronous page mode read after the first read wait states <1-32> <#-1>
-;// <i> The delay is in CCLK cycles
-;// </h>
-EMC_STA_WPAGE2_Val EQU 0x0000001F
-
-;// <h> Static Memory Write Delay Register (EMCStaticWaitWr2)
-;// <i> Selects the delay from CS2 to a write access
-;// <o.0..4> WAITWR: Write wait states <2-33> <#-2>
-;// <i> The delay is in CCLK cycles
-;// </h>
-EMC_STA_WWR2_Val EQU 0x0000001F
-
-;// <h> Static Memory Turn Round Delay Register (EMCStaticWaitTurn2)
-;// <i> Selects the number of bus turnaround cycles for CS2
-;// <o.0..4> WAITTURN: Bus turnaround cycles <1-16> <#-1>
-;// <i> The delay is in CCLK cycles
-;// </h>
-EMC_STA_WTURN2_Val EQU 0x0000000F
-
-;// </e> End of Static Setup for Static CS2 Area
-
-;// Configure External Bus Behaviour for Static CS3 Area ---------------
-;// <e> Configure External Bus Behaviour for Static CS3 Area
-EMC_STACS3_SETUP EQU 0
-
-;// <h> Static Memory Configuration Register (EMCStaticConfig3)
-;// <i> Defines the configuration information for the static memory CS3
-;// <o0.20> WP: Write protect
-;// <o0.19> B: Buffer enable
-;// <o0.8> EW: Extended wait enable
-;// <o0.7> PB: Byte lane state
-;// <0=> For reads BLSn are HIGH, for writes BLSn are LOW
-;// <1=> For reads BLSn are LOW, for writes BLSn are LOW
-;// <o0.6> PC: Chip select polarity
-;// <0=> Active LOW chip select
-;// <1=> Active HIGH chip select
-;// <o0.3> PM: Page mode enable
-;// <o0.0..1> MW: Memory width
-;// <0=> 8 bit
-;// <1=> 16 bit
-;// <2=> 32 bit
-;// </h>
-EMC_STA_CFG3_Val EQU 0x00000000
-
-;// <h> Static Memory Write Enable Delay Register (EMCStaticWaitWen3)
-;// <i> Selects the delay from CS3 to write enable
-;// <o.0..3> WAITWEN: Wait write enable <1-16> <#-1>
-;// <i> The delay is in CCLK cycles
-;// </h>
-EMC_STA_WWEN3_Val EQU 0x00000000
-
-;// <h> Static Memory Output Enable Delay register (EMCStaticWaitOen3)
-;// <i> Selects the delay from CS3 or address change, whichever is later, to output enable
-;// <o.0..3> WAITOEN: Wait output enable <0-15>
-;// <i> The delay is in CCLK cycles
-;// </h>
-EMC_STA_WOEN3_Val EQU 0x00000000
-
-;// <h> Static Memory Read Delay Register (EMCStaticWaitRd3)
-;// <i> Selects the delay from CS3 to a read access
-;// <o.0..4> WAITRD: Non-page mode read wait states or asynchronous page mode read first access wait states <1-32> <#-1>
-;// <i> The delay is in CCLK cycles
-;// </h>
-EMC_STA_WRD3_Val EQU 0x0000001F
-
-;// <h> Static Memory Page Mode Read Delay Register (EMCStaticWaitPage3)
-;// <i> Selects the delay for asynchronous page mode sequential accesses for CS3
-;// <o.0..4> WAITPAGE: Asynchronous page mode read after the first read wait states <1-32> <#-1>
-;// <i> The delay is in CCLK cycles
-;// </h>
-EMC_STA_WPAGE3_Val EQU 0x0000001F
-
-;// <h> Static Memory Write Delay Register (EMCStaticWaitWr3)
-;// <i> Selects the delay from CS3 to a write access
-;// <o.0..4> WAITWR: Write wait states <2-33> <#-2>
-;// <i> The delay is in CCLK cycles
-;// </h>
-EMC_STA_WWR3_Val EQU 0x0000001F
-
-;// <h> Static Memory Turn Round Delay Register (EMCStaticWaitTurn3)
-;// <i> Selects the number of bus turnaround cycles for CS3
-;// <o.0..4> WAITTURN: Bus turnaround cycles <1-16> <#-1>
-;// <i> The delay is in CCLK cycles
-;// </h>
-EMC_STA_WTURN3_Val EQU 0x0000000F
-
-;// </e> End of Static Setup for Static CS3 Area
-
-;// <h> Static Memory Extended Wait Register (EMCStaticExtendedWait)
-;// <i> Time long static memory read and write transfers
-;// <o.0..9> EXTENDEDWAIT: Extended wait time out <0-1023>
-;// <i> The delay is in (16 * CCLK) cycles
-;// </h>
-EMC_STA_EXT_W_Val EQU 0x00000000
-
-;// </e> End of Static Setup
-
-;// </e> End of EMC Setup
-
-
- PRESERVE8
-
-; Area Definition and Entry Point
-; Startup Code must be linked first at Address at which it expects to run.
-
- AREA RESET, CODE, READONLY
- ARM
-
-
-; Exception Vectors
-; Mapped to Address 0.
-; Absolute addressing mode must be used.
-; Dummy Handlers are implemented as infinite loops which can be modified.
-
-Vectors LDR PC, Reset_Addr
- LDR PC, Undef_Addr
- LDR PC, SWI_Addr
- LDR PC, PAbt_Addr
- LDR PC, DAbt_Addr
- NOP ; Reserved Vector
- LDR PC, IRQ_Addr
- LDR PC, FIQ_Addr
-
-Reset_Addr DCD Reset_Handler
-Undef_Addr DCD Undef_Handler
-SWI_Addr DCD SWI_Handler
-PAbt_Addr DCD PAbt_Handler
-DAbt_Addr DCD DAbt_Handler
- DCD 0 ; Reserved Address
-IRQ_Addr DCD IRQ_Handler
-FIQ_Addr DCD FIQ_Handler
-
-
-; Exception Handler
- IMPORT rt_hw_trap_udef
- IMPORT rt_hw_trap_swi
- IMPORT rt_hw_trap_pabt
- IMPORT rt_hw_trap_dabt
- IMPORT rt_hw_trap_fiq
-
-; Prepare Fatal Context
- MACRO
- prepare_fatal
- STMFD sp!, {r0-r3}
- MOV r1, sp
- ADD sp, sp, #16
- SUB r2, lr, #4
- MRS r3, spsr
-
- ; switch to SVC mode and no interrupt
- MSR cpsr_c, #I_Bit :OR: F_Bit :OR: Mode_SVC
-
- STMFD sp!, {r0} ; old r0
- ; get sp
- ADD r0, sp, #4
- STMFD sp!, {r3} ; cpsr
- STMFD sp!, {r2} ; pc
- STMFD sp!, {lr} ; lr
- STMFD sp!, {r0} ; sp
- STMFD sp!, {r4-r12}
-
- MOV r4, r1
-
- LDMFD r4!, {r0-r3}
- STMFD sp!, {r0-r3}
-
- MOV r0, sp
- MEND
-
-Undef_Handler
- prepare_fatal
- BL rt_hw_trap_irq
- B .
-
-SWI_Handler
- prepare_fatal
- BL rt_hw_trap_swi
- B .
-
-PAbt_Handler
- prepare_fatal
- BL rt_hw_trap_pabt
- B .
-
-DAbt_Handler
- prepare_fatal
- BL rt_hw_trap_dabt
- B .
-
-FIQ_Handler
- prepare_fatal
- BL rt_hw_trap_fiq
- B .
-
-; Reset Handler
-
- EXPORT Reset_Handler
-Reset_Handler
-
-
-; Clock Setup ------------------------------------------------------------------
-
- IF (:LNOT:(:DEF:NO_CLOCK_SETUP)):LAND:(CLOCK_SETUP != 0)
- LDR R0, =SCB_BASE
- MOV R1, #0xAA
- MOV R2, #0x55
-
-; Configure and Enable PLL
- LDR R3, =SCS_Val ; Enable main oscillator
- STR R3, [R0, #SCS_OFS]
-
- IF (SCS_Val:AND:OSCEN) != 0
-OSC_Loop LDR R3, [R0, #SCS_OFS] ; Wait for main osc stabilize
- ANDS R3, R3, #OSCSTAT
- BEQ OSC_Loop
- ENDIF
-
- LDR R3, =CLKSRCSEL_Val ; Select PLL source clock
- STR R3, [R0, #CLKSRCSEL_OFS]
- LDR R3, =PLLCFG_Val
- STR R3, [R0, #PLLCFG_OFS]
- STR R1, [R0, #PLLFEED_OFS]
- STR R2, [R0, #PLLFEED_OFS]
- MOV R3, #PLLCON_PLLE
- STR R3, [R0, #PLLCON_OFS]
- STR R1, [R0, #PLLFEED_OFS]
- STR R2, [R0, #PLLFEED_OFS]
-
- IF (CLKSRCSEL_Val:AND:3) != 2
-; Wait until PLL Locked (if source is not RTC oscillator)
-PLL_Loop LDR R3, [R0, #PLLSTAT_OFS]
- ANDS R3, R3, #PLLSTAT_PLOCK
- BEQ PLL_Loop
- ELSE
-; Wait at least 200 cycles (if source is RTC oscillator)
- MOV R3, #(200/4)
-PLL_Loop SUBS R3, R3, #1
- BNE PLL_Loop
- ENDIF
-
-M_N_Lock LDR R3, [R0, #PLLSTAT_OFS]
- LDR R4, =(PLLSTAT_M:OR:PLLSTAT_N)
- AND R3, R3, R4
- LDR R4, =PLLCFG_Val
- EORS R3, R3, R4
- BNE M_N_Lock
-
-; Setup CPU clock divider
- MOV R3, #CCLKCFG_Val
- STR R3, [R0, #CCLKCFG_OFS]
-
-; Setup USB clock divider
- LDR R3, =USBCLKCFG_Val
- STR R3, [R0, #USBCLKCFG_OFS]
-
-; Setup Peripheral Clock
- LDR R3, =PCLKSEL0_Val
- STR R3, [R0, #PCLKSEL0_OFS]
- LDR R3, =PCLKSEL1_Val
- STR R3, [R0, #PCLKSEL1_OFS]
-
-; Switch to PLL Clock
- MOV R3, #(PLLCON_PLLE:OR:PLLCON_PLLC)
- STR R3, [R0, #PLLCON_OFS]
- STR R1, [R0, #PLLFEED_OFS]
- STR R2, [R0, #PLLFEED_OFS]
- ENDIF ; CLOCK_SETUP
-
-
-; Setup Memory Accelerator Module ----------------------------------------------
-
- IF MAM_SETUP != 0
- LDR R0, =MAM_BASE
- MOV R1, #MAMTIM_Val
- STR R1, [R0, #MAMTIM_OFS]
- MOV R1, #MAMCR_Val
- STR R1, [R0, #MAMCR_OFS]
- ENDIF ; MAM_SETUP
-
-
-; Setup External Memory Controller ---------------------------------------------
-
- IF (:LNOT:(:DEF:NO_EMC_SETUP)):LAND:(EMC_SETUP != 0)
- LDR R0, =EMC_BASE
- LDR R1, =SCB_BASE
- LDR R2, =PCB_BASE
-
- LDR R4, =EMC_PCONP_Const ; Enable EMC
- LDR R3, [R1, #PCONP_OFS]
- ORR R4, R4, R3
- STR R4, [R1, #PCONP_OFS]
-
- LDR R4, =EMC_CTRL_Val
- STR R4, [R0, #EMC_CTRL_OFS]
- LDR R4, =EMC_CONFIG_Val
- STR R4, [R0, #EMC_CONFIG_OFS]
-
-; Setup pin functions for External Bus functionality
- LDR R4, =EMC_PINSEL5_Val
- STR R4, [R2, #PINSEL5_OFS]
- LDR R4, =EMC_PINSEL6_Val
- STR R4, [R2, #PINSEL6_OFS]
- LDR R4, =EMC_PINSEL8_Val
- STR R4, [R2, #PINSEL8_OFS]
- LDR R4, =EMC_PINSEL9_Val
- STR R4, [R2, #PINSEL9_OFS]
-
-; Setup Dynamic Memory Interface
- IF (EMC_DYNAMIC_SETUP != 0)
-
- LDR R4, =EMC_DYN_RP_Val
- STR R4, [R0, #EMC_DYN_RP_OFS]
- LDR R4, =EMC_DYN_RAS_Val
- STR R4, [R0, #EMC_DYN_RAS_OFS]
- LDR R4, =EMC_DYN_SREX_Val
- STR R4, [R0, #EMC_DYN_SREX_OFS]
- LDR R4, =EMC_DYN_APR_Val
- STR R4, [R0, #EMC_DYN_APR_OFS]
- LDR R4, =EMC_DYN_DAL_Val
- STR R4, [R0, #EMC_DYN_DAL_OFS]
- LDR R4, =EMC_DYN_WR_Val
- STR R4, [R0, #EMC_DYN_WR_OFS]
- LDR R4, =EMC_DYN_RC_Val
- STR R4, [R0, #EMC_DYN_RC_OFS]
- LDR R4, =EMC_DYN_RFC_Val
- STR R4, [R0, #EMC_DYN_RFC_OFS]
- LDR R4, =EMC_DYN_XSR_Val
- STR R4, [R0, #EMC_DYN_XSR_OFS]
- LDR R4, =EMC_DYN_RRD_Val
- STR R4, [R0, #EMC_DYN_RRD_OFS]
- LDR R4, =EMC_DYN_MRD_Val
- STR R4, [R0, #EMC_DYN_MRD_OFS]
-
- LDR R4, =EMC_DYN_RD_CFG_Val
- STR R4, [R0, #EMC_DYN_RD_CFG_OFS]
-
- IF (EMC_DYNCS0_SETUP != 0)
- LDR R4, =EMC_DYN_RASCAS0_Val
- STR R4, [R0, #EMC_DYN_RASCAS0_OFS]
- LDR R4, =EMC_DYN_CFG0_Val
- MVN R5, #BUFEN_Const
- AND R4, R4, R5
- STR R4, [R0, #EMC_DYN_CFG0_OFS]
- ENDIF
- IF (EMC_DYNCS1_SETUP != 0)
- LDR R4, =EMC_DYN_RASCAS1_Val
- STR R4, [R0, #EMC_DYN_RASCAS1_OFS]
- LDR R4, =EMC_DYN_CFG1_Val
- MVN R5, =BUFEN_Const
- AND R4, R4, R5
- STR R4, [R0, #EMC_DYN_CFG1_OFS]
- ENDIF
- IF (EMC_DYNCS2_SETUP != 0)
- LDR R4, =EMC_DYN_RASCAS2_Val
- STR R4, [R0, #EMC_DYN_RASCAS2_OFS]
- LDR R4, =EMC_DYN_CFG2_Val
- MVN R5, =BUFEN_Const
- AND R4, R4, R5
- STR R4, [R0, #EMC_DYN_CFG2_OFS]
- ENDIF
- IF (EMC_DYNCS3_SETUP != 0)
- LDR R4, =EMC_DYN_RASCAS3_Val
- STR R4, [R0, #EMC_DYN_RASCAS3_OFS]
- LDR R4, =EMC_DYN_CFG3_Val
- MVN R5, =BUFEN_Const
- AND R4, R4, R5
- STR R4, [R0, #EMC_DYN_CFG3_OFS]
- ENDIF
-
- LDR R6, =1440000 ; Number of cycles to delay
-Wait_0 SUBS R6, R6, #1 ; Delay ~100 ms proc clk 57.6 MHz
- BNE Wait_0 ; BNE (3 cyc) + SUBS (1 cyc) = 4 cyc
-
- LDR R4, =(NOP_CMD:OR:0x03) ; Write NOP Command
- STR R4, [R0, #EMC_DYN_CTRL_OFS]
-
- LDR R6, =2880000 ; Number of cycles to delay
-Wait_1 SUBS R6, R6, #1 ; Delay ~200 ms proc clk 57.6 MHz
- BNE Wait_1
-
- LDR R4, =(PALL_CMD:OR:0x03) ; Write Precharge All Command
- STR R4, [R0, #EMC_DYN_CTRL_OFS]
-
- MOV R4, #2
- STR R4, [R0, #EMC_DYN_RFSH_OFS]
-
- MOV R6, #64 ; Number of cycles to delay
-Wait_2 SUBS R6, R6, #1 ; Delay
- BNE Wait_2
-
- LDR R4, =EMC_DYN_RFSH_Val
- STR R4, [R0, #EMC_DYN_RFSH_OFS]
-
- LDR R4, =(MODE_CMD:OR:0x03) ; Write MODE Command
- STR R4, [R0, #EMC_DYN_CTRL_OFS]
-
- ; Dummy read
- IF (EMC_DYNCS0_SETUP != 0)
- LDR R4, =DYN_MEM0_BASE
- MOV R5, #(0x33 << 12)
- ADD R4, R4, R5
- LDR R4, [R4, #0]
- ENDIF
- IF (EMC_DYNCS1_SETUP != 0)
- LDR R4, =DYN_MEM1_BASE
- MOV R5, #(0x33 << 12)
- ADD R4, R4, R5
- LDR R4, [R4, #0]
- ENDIF
- IF (EMC_DYNCS2_SETUP != 0)
- LDR R4, =DYN_MEM2_BASE
- MOV R5, #(0x33 << 12)
- ADD R4, R4, R5
- LDR R4, [R4, #0]
- ENDIF
- IF (EMC_DYNCS3_SETUP != 0)
- LDR R4, =DYN_MEM3_BASE
- MOV R5, #(0x33 << 12)
- ADD R4, R4, R5
- LDR R4, [R4, #0]
- ENDIF
-
- LDR R4, =NORMAL_CMD ; Write NORMAL Command
- STR R4, [R0, #EMC_DYN_CTRL_OFS]
-
- ; Enable buffer if requested by settings
- IF (EMC_DYNCS0_SETUP != 0):LAND:((EMC_DYN_CFG0_Val:AND:BUFEN_Const) != 0)
- LDR R4, =EMC_DYN_CFG0_Val
- STR R4, [R0, #EMC_DYN_CFG0_OFS]
- ENDIF
- IF (EMC_DYNCS1_SETUP != 0):LAND:((EMC_DYN_CFG1_Val:AND:BUFEN_Const) != 0)
- LDR R4, =EMC_DYN_CFG1_Val
- STR R4, [R0, #EMC_DYN_CFG1_OFS]
- ENDIF
- IF (EMC_DYNCS2_SETUP != 0):LAND:((EMC_DYN_CFG2_Val:AND:BUFEN_Const) != 0)
- LDR R4, =EMC_DYN_CFG2_Val
- STR R4, [R0, #EMC_DYN_CFG2_OFS]
- ENDIF
- IF (EMC_DYNCS3_SETUP != 0):LAND:((EMC_DYN_CFG3_Val:AND:BUFEN_Const) != 0)
- LDR R4, =EMC_DYN_CFG3_Val
- STR R4, [R0, #EMC_DYN_CFG3_OFS]
- ENDIF
-
- LDR R6, =14400 ; Number of cycles to delay
-Wait_3 SUBS R6, R6, #1 ; Delay ~1 ms @ proc clk 57.6 MHz
- BNE Wait_3
-
- ENDIF ; EMC_DYNAMIC_SETUP
-
-; Setup Static Memory Interface
- IF (EMC_STATIC_SETUP != 0)
-
- LDR R6, =1440000 ; Number of cycles to delay
-Wait_4 SUBS R6, R6, #1 ; Delay ~100 ms @ proc clk 57.6 MHz
- BNE Wait_4
-
- IF (EMC_STACS0_SETUP != 0)
- LDR R4, =EMC_STA_CFG0_Val
- STR R4, [R0, #EMC_STA_CFG0_OFS]
- LDR R4, =EMC_STA_WWEN0_Val
- STR R4, [R0, #EMC_STA_WWEN0_OFS]
- LDR R4, =EMC_STA_WOEN0_Val
- STR R4, [R0, #EMC_STA_WOEN0_OFS]
- LDR R4, =EMC_STA_WRD0_Val
- STR R4, [R0, #EMC_STA_WRD0_OFS]
- LDR R4, =EMC_STA_WPAGE0_Val
- STR R4, [R0, #EMC_STA_WPAGE0_OFS]
- LDR R4, =EMC_STA_WWR0_Val
- STR R4, [R0, #EMC_STA_WWR0_OFS]
- LDR R4, =EMC_STA_WTURN0_Val
- STR R4, [R0, #EMC_STA_WTURN0_OFS]
- ENDIF
-
- IF (EMC_STACS1_SETUP != 0)
- LDR R4, =EMC_STA_CFG1_Val
- STR R4, [R0, #EMC_STA_CFG1_OFS]
- LDR R4, =EMC_STA_WWEN1_Val
- STR R4, [R0, #EMC_STA_WWEN1_OFS]
- LDR R4, =EMC_STA_WOEN1_Val
- STR R4, [R0, #EMC_STA_WOEN1_OFS]
- LDR R4, =EMC_STA_WRD1_Val
- STR R4, [R0, #EMC_STA_WRD1_OFS]
- LDR R4, =EMC_STA_WPAGE1_Val
- STR R4, [R0, #EMC_STA_WPAGE1_OFS]
- LDR R4, =EMC_STA_WWR1_Val
- STR R4, [R0, #EMC_STA_WWR1_OFS]
- LDR R4, =EMC_STA_WTURN1_Val
- STR R4, [R0, #EMC_STA_WTURN1_OFS]
- ENDIF
-
- IF (EMC_STACS2_SETUP != 0)
- LDR R4, =EMC_STA_CFG2_Val
- STR R4, [R0, #EMC_STA_CFG2_OFS]
- LDR R4, =EMC_STA_WWEN2_Val
- STR R4, [R0, #EMC_STA_WWEN2_OFS]
- LDR R4, =EMC_STA_WOEN2_Val
- STR R4, [R0, #EMC_STA_WOEN2_OFS]
- LDR R4, =EMC_STA_WRD2_Val
- STR R4, [R0, #EMC_STA_WRD2_OFS]
- LDR R4, =EMC_STA_WPAGE2_Val
- STR R4, [R0, #EMC_STA_WPAGE2_OFS]
- LDR R4, =EMC_STA_WWR2_Val
- STR R4, [R0, #EMC_STA_WWR2_OFS]
- LDR R4, =EMC_STA_WTURN2_Val
- STR R4, [R0, #EMC_STA_WTURN2_OFS]
- ENDIF
-
- IF (EMC_STACS3_SETUP != 0)
- LDR R4, =EMC_STA_CFG3_Val
- STR R4, [R0, #EMC_STA_CFG3_OFS]
- LDR R4, =EMC_STA_WWEN3_Val
- STR R4, [R0, #EMC_STA_WWEN3_OFS]
- LDR R4, =EMC_STA_WOEN3_Val
- STR R4, [R0, #EMC_STA_WOEN3_OFS]
- LDR R4, =EMC_STA_WRD3_Val
- STR R4, [R0, #EMC_STA_WRD3_OFS]
- LDR R4, =EMC_STA_WPAGE3_Val
- STR R4, [R0, #EMC_STA_WPAGE3_OFS]
- LDR R4, =EMC_STA_WWR3_Val
- STR R4, [R0, #EMC_STA_WWR3_OFS]
- LDR R4, =EMC_STA_WTURN3_Val
- STR R4, [R0, #EMC_STA_WTURN3_OFS]
- ENDIF
-
- LDR R6, =144000 ; Number of cycles to delay
-Wait_5 SUBS R6, R6, #1 ; Delay ~10 ms @ proc clk 57.6 MHz
- BNE Wait_5
-
- LDR R4, =EMC_STA_EXT_W_Val
- LDR R5, =EMC_STA_EXT_W_OFS
- ADD R5, R5, R0
- STR R4, [R5, #0]
-
- ENDIF ; EMC_STATIC_SETUP
-
- ENDIF ; EMC_SETUP
-
-
-; Copy Exception Vectors to Internal RAM ---------------------------------------
-
- IF :DEF:RAM_INTVEC
- ADR R8, Vectors ; Source
- LDR R9, =RAM_BASE ; Destination
- LDMIA R8!, {R0-R7} ; Load Vectors
- STMIA R9!, {R0-R7} ; Store Vectors
- LDMIA R8!, {R0-R7} ; Load Handler Addresses
- STMIA R9!, {R0-R7} ; Store Handler Addresses
- ENDIF
-
-
-; Memory Mapping (when Interrupt Vectors are in RAM) ---------------------------
-
-MEMMAP EQU 0xE01FC040 ; Memory Mapping Control
- IF :DEF:REMAP
- LDR R0, =MEMMAP
- IF :DEF:EXTMEM_MODE
- MOV R1, #3
- ELIF :DEF:RAM_MODE
- MOV R1, #2
- ELSE
- MOV R1, #1
- ENDIF
- STR R1, [R0]
- ENDIF
-
-
-; Setup Stack for each mode ----------------------------------------------------
-
- LDR R0, =Stack_Top
-
-; Enter Undefined Instruction Mode and set its Stack Pointer
- MSR CPSR_c, #Mode_UND:OR:I_Bit:OR:F_Bit
- MOV SP, R0
- SUB R0, R0, #UND_Stack_Size
-
-; Enter Abort Mode and set its Stack Pointer
- MSR CPSR_c, #Mode_ABT:OR:I_Bit:OR:F_Bit
- MOV SP, R0
- SUB R0, R0, #ABT_Stack_Size
-
-; Enter FIQ Mode and set its Stack Pointer
- MSR CPSR_c, #Mode_FIQ:OR:I_Bit:OR:F_Bit
- MOV SP, R0
- SUB R0, R0, #FIQ_Stack_Size
-
-; Enter IRQ Mode and set its Stack Pointer
- MSR CPSR_c, #Mode_IRQ:OR:I_Bit:OR:F_Bit
- MOV SP, R0
- SUB R0, R0, #IRQ_Stack_Size
-
-; Enter Supervisor Mode and set its Stack Pointer
- MSR CPSR_c, #Mode_SVC:OR:I_Bit:OR:F_Bit
- MOV SP, R0
- SUB R0, R0, #SVC_Stack_Size
-
- IF :DEF:__MICROLIB
- EXPORT __initial_sp
- ELSE
- ENDIF
-
-; Enter the C code -------------------------------------------------------------
-
- IMPORT __main
- LDR R0, =__main
- BX R0
-
- IMPORT rt_interrupt_enter
- IMPORT rt_interrupt_leave
- IMPORT rt_thread_switch_interrupt_flag
- IMPORT rt_interrupt_from_thread
- IMPORT rt_interrupt_to_thread
- IMPORT rt_hw_trap_irq
-
-IRQ_Handler PROC
- EXPORT IRQ_Handler
- STMFD sp!, {r0-r12,lr}
- BL rt_interrupt_enter
- BL rt_hw_trap_irq
- BL rt_interrupt_leave
-
- ; if rt_thread_switch_interrupt_flag set, jump to
- ; rt_hw_context_switch_interrupt_do and don't return
- LDR r0, =rt_thread_switch_interrupt_flag
- LDR r1, [r0]
- CMP r1, #1
- BEQ rt_hw_context_switch_interrupt_do
-
- LDMFD sp!, {r0-r12,lr}
- SUBS pc, lr, #4
- ENDP
-
-; /*
-; * void rt_hw_context_switch_interrupt_do(rt_base_t flag)
-; */
-rt_hw_context_switch_interrupt_do PROC
- EXPORT rt_hw_context_switch_interrupt_do
- MOV r1, #0 ; clear flag
- STR r1, [r0]
-
- LDMFD sp!, {r0-r12,lr}; reload saved registers
- STMFD sp!, {r0-r3} ; save r0-r3
- MOV r1, sp
- ADD sp, sp, #16 ; restore sp
- SUB r2, lr, #4 ; save old task's pc to r2
-
- MRS r3, spsr ; get cpsr of interrupt thread
-
- ; switch to SVC mode and no interrupt
- MSR cpsr_c, #I_Bit :OR: F_Bit :OR: Mode_SVC
-
- STMFD sp!, {r2} ; push old task's pc
- STMFD sp!, {r4-r12,lr}; push old task's lr,r12-r4
- MOV r4, r1 ; Special optimised code below
- MOV r5, r3
- LDMFD r4!, {r0-r3}
- STMFD sp!, {r0-r3} ; push old task's r3-r0
- STMFD sp!, {r5} ; push old task's cpsr
-
- LDR r4, =rt_interrupt_from_thread
- LDR r5, [r4]
- STR sp, [r5] ; store sp in preempted tasks's TCB
-
- LDR r6, =rt_interrupt_to_thread
- LDR r6, [r6]
- LDR sp, [r6] ; get new task's stack pointer
-
- LDMFD sp!, {r4} ; pop new task's cpsr to spsr
- MSR spsr_cxsf, r4
- BIC r4, r4, #0x20 ; must be ARM mode
- MSR cpsr_cxsf, r4
-
- LDMFD sp!, {r0-r12,lr,pc}^ ; pop new task's r0-r12,lr & pc, copy spsr to cpsr
- ENDP
-
- IF :DEF:__MICROLIB
-
- EXPORT __heap_base
- EXPORT __heap_limit
-
- ELSE
-; User Initial Stack & Heap
- AREA |.text|, CODE, READONLY
-
- IMPORT __use_two_region_memory
- EXPORT __user_initial_stackheap
-__user_initial_stackheap
-
- LDR R0, = Heap_Mem
- LDR R1, =(Stack_Mem + USR_Stack_Size)
- LDR R2, = (Heap_Mem + Heap_Size)
- LDR R3, = Stack_Mem
- BX LR
- ENDIF
-
-
- END
+;/*****************************************************************************/ +;/* LPC2400.S: Startup file for Philips LPC2400 device series */ +;/*****************************************************************************/ +;/* <<< Use Configuration Wizard in Context Menu >>> */ +;/*****************************************************************************/ +;/* This file is part of the uVision/ARM development tools. */ +;/* Copyright (c) 2007-2008 Keil - An ARM Company. All rights reserved. */ +;/* This software may only be used under the terms of a valid, current, */ +;/* end user licence from KEIL for a compatible version of KEIL software */ +;/* development tools. Nothing else gives you the right to use this software. */ +;/*****************************************************************************/ + +;/* +; * The LPC2400.S code is executed after CPU Reset. This file may be +; * translated with the following SET symbols. In uVision these SET +; * symbols are entered under Options - ASM - Define. +; * +; * NO_CLOCK_SETUP: when set the startup code will not initialize Clock +; * (used mostly when clock is already initialized from script .ini +; * file). +; * +; * NO_EMC_SETUP: when set the startup code will not initialize +; * External Bus Controller. +; * +; * RAM_INTVEC: when set the startup code copies exception vectors +; * from on-chip Flash to on-chip RAM. +; * +; * REMAP: when set the startup code initializes the register MEMMAP +; * which overwrites the settings of the CPU configuration pins. The +; * startup and interrupt vectors are remapped from: +; * 0x00000000 default setting (not remapped) +; * 0x40000000 when RAM_MODE is used +; * 0x80000000 when EXTMEM_MODE is used +; * +; * EXTMEM_MODE: when set the device is configured for code execution +; * from external memory starting at address 0x80000000. +; * +; * RAM_MODE: when set the device is configured for code execution +; * from on-chip RAM starting at address 0x40000000. +; */ + + +; Standard definitions of Mode bits and Interrupt (I & F) flags in PSRs + +Mode_USR EQU 0x10 +Mode_FIQ EQU 0x11 +Mode_IRQ EQU 0x12 +Mode_SVC EQU 0x13 +Mode_ABT EQU 0x17 +Mode_UND EQU 0x1B +Mode_SYS EQU 0x1F +I_Bit EQU 0x80 ; when I bit is set, IRQ is disabled +F_Bit EQU 0x40 ; when F bit is set, FIQ is disabled + +;----------------------- Memory Definitions ------------------------------------ + +; Internal Memory Base Addresses +FLASH_BASE EQU 0x00000000 +RAM_BASE EQU 0x40000000 +EXTMEM_BASE EQU 0x80000000 + +; External Memory Base Addresses +STA_MEM0_BASE EQU 0x80000000 +STA_MEM1_BASE EQU 0x81000000 +STA_MEM2_BASE EQU 0x82000000 +STA_MEM3_BASE EQU 0x83000000 +DYN_MEM0_BASE EQU 0xA0000000 +DYN_MEM1_BASE EQU 0xB0000000 +DYN_MEM2_BASE EQU 0xC0000000 +DYN_MEM3_BASE EQU 0xD0000000 + + +;----------------------- Stack and Heap Definitions ---------------------------- + +;// <h> Stack Configuration (Stack Sizes in Bytes) +;// <o0> Undefined Mode <0x0-0xFFFFFFFF:8> +;// <o1> Supervisor Mode <0x0-0xFFFFFFFF:8> +;// <o2> Abort Mode <0x0-0xFFFFFFFF:8> +;// <o3> Fast Interrupt Mode <0x0-0xFFFFFFFF:8> +;// <o4> Interrupt Mode <0x0-0xFFFFFFFF:8> +;// <o5> User/System Mode <0x0-0xFFFFFFFF:8> +;// </h> + +UND_Stack_Size EQU 0x00000000 +SVC_Stack_Size EQU 0x00000100 +ABT_Stack_Size EQU 0x00000000 +FIQ_Stack_Size EQU 0x00000000 +IRQ_Stack_Size EQU 0x00000100 +USR_Stack_Size EQU 0x00000100 + +ISR_Stack_Size EQU (UND_Stack_Size + SVC_Stack_Size + ABT_Stack_Size + \ + FIQ_Stack_Size + IRQ_Stack_Size) + + AREA STACK, NOINIT, READWRITE, ALIGN=3 + +Stack_Mem SPACE USR_Stack_Size +__initial_sp SPACE ISR_Stack_Size + +Stack_Top + + +;// <h> Heap Configuration +;// <o> Heap Size (in Bytes) <0x0-0xFFFFFFFF> +;// </h> + +Heap_Size EQU 0x00000000 + + AREA HEAP, NOINIT, READWRITE, ALIGN=3 +__heap_base +Heap_Mem SPACE Heap_Size +__heap_limit + + +;----------------------- Clock Definitions ------------------------------------- + +; System Control Block (SCB) Module Definitions +SCB_BASE EQU 0xE01FC000 ; SCB Base Address +PLLCON_OFS EQU 0x80 ; PLL Control Offset +PLLCFG_OFS EQU 0x84 ; PLL Configuration Offset +PLLSTAT_OFS EQU 0x88 ; PLL Status Offset +PLLFEED_OFS EQU 0x8C ; PLL Feed Offset +CCLKCFG_OFS EQU 0x104 ; CPU Clock Divider Reg Offset +USBCLKCFG_OFS EQU 0x108 ; USB Clock Divider Reg Offset +CLKSRCSEL_OFS EQU 0x10C ; Clock Source Sel Reg Offset +SCS_OFS EQU 0x1A0 ; Sys Control and Status Reg Offset +PCLKSEL0_OFS EQU 0x1A8 ; Periph Clock Sel Reg 0 Offset +PCLKSEL1_OFS EQU 0x1AC ; Periph Clock Sel Reg 0 Offset + +PCON_OFS EQU 0x0C0 ; Power Mode Control Reg Offset +PCONP_OFS EQU 0x0C4 ; Power Control for Periphs Reg Offset + +; Constants +OSCRANGE EQU (1<<4) ; Oscillator Range Select +OSCEN EQU (1<<5) ; Main oscillator Enable +OSCSTAT EQU (1<<6) ; Main Oscillator Status +PLLCON_PLLE EQU (1<<0) ; PLL Enable +PLLCON_PLLC EQU (1<<1) ; PLL Connect +PLLSTAT_M EQU (0x7FFF<<0) ; PLL M Value +PLLSTAT_N EQU (0xFF<<16) ; PLL N Value +PLLSTAT_PLOCK EQU (1<<26) ; PLL Lock Status + +;// <e> Clock Setup +;// <h> System Controls and Status Register (SYS) +;// <o1.4> OSCRANGE: Main Oscillator Range Select +;// <0=> 1 MHz to 20 MHz +;// <1=> 15 MHz to 24 MHz +;// <e1.5> OSCEN: Main Oscillator Enable +;// </e> +;// </h> +;// +;// <h> PLL Clock Source Select Register (CLKSRCSEL) +;// <o2.0..1> CLKSRC: PLL Clock Source Selection +;// <0=> Internal RC oscillator +;// <1=> Main oscillator +;// <2=> RTC oscillator +;// </h> +;// +;// <h> PLL Configuration Register (PLLCFG) +;// <i> PLL_clk = (2* M * PLL_clk_src) / N +;// <o3.0..14> MSEL: PLL Multiplier Selection +;// <1-32768><#-1> +;// <i> M Value +;// <o3.16..23> NSEL: PLL Divider Selection +;// <1-256><#-1> +;// <i> N Value +;// </h> +;// +;// <h> CPU Clock Configuration Register (CCLKCFG) +;// <o4.0..7> CCLKSEL: Divide Value for CPU Clock from PLL +;// <1-256><#-1> +;// </h> +;// +;// <h> USB Clock Configuration Register (USBCLKCFG) +;// <o5.0..3> USBSEL: Divide Value for USB Clock from PLL +;// <1-16><#-1> +;// </h> +;// +;// <h> Peripheral Clock Selection Register 0 (PCLKSEL0) +;// <o6.0..1> PCLK_WDT: Peripheral Clock Selection for WDT +;// <0=> Pclk = Cclk / 4 +;// <1=> Pclk = Cclk +;// <2=> Pclk = Cclk / 2 +;// <3=> Pclk = Cclk / 8 +;// <o6.2..3> PCLK_TIMER0: Peripheral Clock Selection for TIMER0 +;// <0=> Pclk = Cclk / 4 +;// <1=> Pclk = Cclk +;// <2=> Pclk = Cclk / 2 +;// <3=> Pclk = Cclk / 8 +;// <o6.4..5> PCLK_TIMER1: Peripheral Clock Selection for TIMER1 +;// <0=> Pclk = Cclk / 4 +;// <1=> Pclk = Cclk +;// <2=> Pclk = Cclk / 2 +;// <3=> Pclk = Cclk / 8 +;// <o6.6..7> PCLK_UART0: Peripheral Clock Selection for UART0 +;// <0=> Pclk = Cclk / 4 +;// <1=> Pclk = Cclk +;// <2=> Pclk = Cclk / 2 +;// <3=> Pclk = Cclk / 8 +;// <o6.8..9> PCLK_UART1: Peripheral Clock Selection for UART1 +;// <0=> Pclk = Cclk / 4 +;// <1=> Pclk = Cclk +;// <2=> Pclk = Cclk / 2 +;// <3=> Pclk = Cclk / 8 +;// <o6.10..11> PCLK_PWM0: Peripheral Clock Selection for PWM0 +;// <0=> Pclk = Cclk / 4 +;// <1=> Pclk = Cclk +;// <2=> Pclk = Cclk / 2 +;// <3=> Pclk = Cclk / 8 +;// <o6.12..13> PCLK_PWM1: Peripheral Clock Selection for PWM1 +;// <0=> Pclk = Cclk / 4 +;// <1=> Pclk = Cclk +;// <2=> Pclk = Cclk / 2 +;// <3=> Pclk = Cclk / 8 +;// <o6.14..15> PCLK_I2C0: Peripheral Clock Selection for I2C0 +;// <0=> Pclk = Cclk / 4 +;// <1=> Pclk = Cclk +;// <2=> Pclk = Cclk / 2 +;// <3=> Pclk = Cclk / 8 +;// <o6.16..17> PCLK_SPI: Peripheral Clock Selection for SPI +;// <0=> Pclk = Cclk / 4 +;// <1=> Pclk = Cclk +;// <2=> Pclk = Cclk / 2 +;// <3=> Pclk = Cclk / 8 +;// <o6.18..19> PCLK_RTC: Peripheral Clock Selection for RTC +;// <0=> Pclk = Cclk / 4 +;// <1=> Pclk = Cclk +;// <2=> Pclk = Cclk / 2 +;// <3=> Pclk = Cclk / 8 +;// <o6.20..21> PCLK_SSP1: Peripheral Clock Selection for SSP1 +;// <0=> Pclk = Cclk / 4 +;// <1=> Pclk = Cclk +;// <2=> Pclk = Cclk / 2 +;// <3=> Pclk = Cclk / 8 +;// <o6.22..23> PCLK_DAC: Peripheral Clock Selection for DAC +;// <0=> Pclk = Cclk / 4 +;// <1=> Pclk = Cclk +;// <2=> Pclk = Cclk / 2 +;// <3=> Pclk = Cclk / 8 +;// <o6.24..25> PCLK_ADC: Peripheral Clock Selection for ADC +;// <0=> Pclk = Cclk / 4 +;// <1=> Pclk = Cclk +;// <2=> Pclk = Cclk / 2 +;// <3=> Pclk = Cclk / 8 +;// <o6.26..27> PCLK_CAN1: Peripheral Clock Selection for CAN1 +;// <0=> Pclk = Cclk / 4 +;// <1=> Pclk = Cclk +;// <2=> Pclk = Cclk / 2 +;// <3=> Pclk = Cclk / 6 +;// <o6.28..29> PCLK_CAN2: Peripheral Clock Selection for CAN2 +;// <0=> Pclk = Cclk / 4 +;// <1=> Pclk = Cclk +;// <2=> Pclk = Cclk / 2 +;// <3=> Pclk = Cclk / 6 +;// <o6.30..31> PCLK_ACF: Peripheral Clock Selection for ACF +;// <0=> Pclk = Cclk / 4 +;// <1=> Pclk = Cclk +;// <2=> Pclk = Cclk / 2 +;// <3=> Pclk = Cclk / 6 +;// </h> +;// +;// <h> Peripheral Clock Selection Register 1 (PCLKSEL1) +;// <o7.0..1> PCLK_BAT_RAM: Peripheral Clock Selection for the Battery Supported RAM +;// <0=> Pclk = Cclk / 4 +;// <1=> Pclk = Cclk +;// <2=> Pclk = Cclk / 2 +;// <3=> Pclk = Cclk / 8 +;// <o7.2..3> PCLK_GPIO: Peripheral Clock Selection for GPIOs +;// <0=> Pclk = Cclk / 4 +;// <1=> Pclk = Cclk +;// <2=> Pclk = Cclk / 2 +;// <3=> Pclk = Cclk / 8 +;// <o7.4..5> PCLK_PCB: Peripheral Clock Selection for Pin Connect Block +;// <0=> Pclk = Cclk / 4 +;// <1=> Pclk = Cclk +;// <2=> Pclk = Cclk / 2 +;// <3=> Pclk = Cclk / 8 +;// <o7.6..7> PCLK_I2C1: Peripheral Clock Selection for I2C1 +;// <0=> Pclk = Cclk / 4 +;// <1=> Pclk = Cclk +;// <2=> Pclk = Cclk / 2 +;// <3=> Pclk = Cclk / 8 +;// <o7.10..11> PCLK_SSP0: Peripheral Clock Selection for SSP0 +;// <0=> Pclk = Cclk / 4 +;// <1=> Pclk = Cclk +;// <2=> Pclk = Cclk / 2 +;// <3=> Pclk = Cclk / 8 +;// <o7.12..13> PCLK_TIMER2: Peripheral Clock Selection for TIMER2 +;// <0=> Pclk = Cclk / 4 +;// <1=> Pclk = Cclk +;// <2=> Pclk = Cclk / 2 +;// <3=> Pclk = Cclk / 8 +;// <o7.14..15> PCLK_TIMER3: Peripheral Clock Selection for TIMER3 +;// <0=> Pclk = Cclk / 4 +;// <1=> Pclk = Cclk +;// <2=> Pclk = Cclk / 2 +;// <3=> Pclk = Cclk / 8 +;// <o7.16..17> PCLK_UART2: Peripheral Clock Selection for UART2 +;// <0=> Pclk = Cclk / 4 +;// <1=> Pclk = Cclk +;// <2=> Pclk = Cclk / 2 +;// <3=> Pclk = Cclk / 8 +;// <o7.18..19> PCLK_UART3: Peripheral Clock Selection for UART3 +;// <0=> Pclk = Cclk / 4 +;// <1=> Pclk = Cclk +;// <2=> Pclk = Cclk / 2 +;// <3=> Pclk = Cclk / 8 +;// <o7.20..21> PCLK_I2C2: Peripheral Clock Selection for I2C2 +;// <0=> Pclk = Cclk / 4 +;// <1=> Pclk = Cclk +;// <2=> Pclk = Cclk / 2 +;// <3=> Pclk = Cclk / 8 +;// <o7.22..23> PCLK_I2S: Peripheral Clock Selection for I2S +;// <0=> Pclk = Cclk / 4 +;// <1=> Pclk = Cclk +;// <2=> Pclk = Cclk / 2 +;// <3=> Pclk = Cclk / 8 +;// <o7.24..25> PCLK_MCI: Peripheral Clock Selection for MCI +;// <0=> Pclk = Cclk / 4 +;// <1=> Pclk = Cclk +;// <2=> Pclk = Cclk / 2 +;// <3=> Pclk = Cclk / 8 +;// <o7.28..29> PCLK_SYSCON: Peripheral Clock Selection for System Control Block +;// <0=> Pclk = Cclk / 4 +;// <1=> Pclk = Cclk +;// <2=> Pclk = Cclk / 2 +;// <3=> Pclk = Cclk / 8 +;// </h> +;// </e> +CLOCK_SETUP EQU 1 +SCS_Val EQU 0x00000020 +CLKSRCSEL_Val EQU 0x00000001 +PLLCFG_Val EQU 0x0000000B +CCLKCFG_Val EQU 0x00000004 +USBCLKCFG_Val EQU 0x00000005 +PCLKSEL0_Val EQU 0x00000000 +PCLKSEL1_Val EQU 0x00000000 + + +;----------------------- Memory Accelerator Module (MAM) Definitions ----------- + +MAM_BASE EQU 0xE01FC000 ; MAM Base Address +MAMCR_OFS EQU 0x00 ; MAM Control Offset +MAMTIM_OFS EQU 0x04 ; MAM Timing Offset + +;// <e> MAM Setup +;// <o1.0..1> MAM Control +;// <0=> Disabled +;// <1=> Partially Enabled +;// <2=> Fully Enabled +;// <i> Mode +;// <o2.0..2> MAM Timing +;// <0=> Reserved <1=> 1 <2=> 2 <3=> 3 +;// <4=> 4 <5=> 5 <6=> 6 <7=> 7 +;// <i> Fetch Cycles +;// </e> +MAM_SETUP EQU 1 +MAMCR_Val EQU 0x00000002 +MAMTIM_Val EQU 0x00000004 + + +;----------------------- Pin Connect Block Definitions ------------------------- + +PCB_BASE EQU 0xE002C000 ; PCB Base Address +PINSEL0_OFS EQU 0x00 ; PINSEL0 Address Offset +PINSEL1_OFS EQU 0x04 ; PINSEL1 Address Offset +PINSEL2_OFS EQU 0x08 ; PINSEL2 Address Offset +PINSEL3_OFS EQU 0x0C ; PINSEL3 Address Offset +PINSEL4_OFS EQU 0x10 ; PINSEL4 Address Offset +PINSEL5_OFS EQU 0x14 ; PINSEL5 Address Offset +PINSEL6_OFS EQU 0x18 ; PINSEL6 Address Offset +PINSEL7_OFS EQU 0x1C ; PINSEL7 Address Offset +PINSEL8_OFS EQU 0x20 ; PINSEL8 Address Offset +PINSEL9_OFS EQU 0x24 ; PINSEL9 Address Offset +PINSEL10_OFS EQU 0x28 ; PINSEL10 Address Offset + + +;----------------------- External Memory Controller (EMC) Definitons ----------- + +EMC_BASE EQU 0xFFE08000 ; EMC Base Address + +EMC_CTRL_OFS EQU 0x000 +EMC_STAT_OFS EQU 0x004 +EMC_CONFIG_OFS EQU 0x008 +EMC_DYN_CTRL_OFS EQU 0x020 +EMC_DYN_RFSH_OFS EQU 0x024 +EMC_DYN_RD_CFG_OFS EQU 0x028 +EMC_DYN_RP_OFS EQU 0x030 +EMC_DYN_RAS_OFS EQU 0x034 +EMC_DYN_SREX_OFS EQU 0x038 +EMC_DYN_APR_OFS EQU 0x03C +EMC_DYN_DAL_OFS EQU 0x040 +EMC_DYN_WR_OFS EQU 0x044 +EMC_DYN_RC_OFS EQU 0x048 +EMC_DYN_RFC_OFS EQU 0x04C +EMC_DYN_XSR_OFS EQU 0x050 +EMC_DYN_RRD_OFS EQU 0x054 +EMC_DYN_MRD_OFS EQU 0x058 +EMC_DYN_CFG0_OFS EQU 0x100 +EMC_DYN_RASCAS0_OFS EQU 0x104 +EMC_DYN_CFG1_OFS EQU 0x140 +EMC_DYN_RASCAS1_OFS EQU 0x144 +EMC_DYN_CFG2_OFS EQU 0x160 +EMC_DYN_RASCAS2_OFS EQU 0x164 +EMC_DYN_CFG3_OFS EQU 0x180 +EMC_DYN_RASCAS3_OFS EQU 0x184 +EMC_STA_CFG0_OFS EQU 0x200 +EMC_STA_WWEN0_OFS EQU 0x204 +EMC_STA_WOEN0_OFS EQU 0x208 +EMC_STA_WRD0_OFS EQU 0x20C +EMC_STA_WPAGE0_OFS EQU 0x210 +EMC_STA_WWR0_OFS EQU 0x214 +EMC_STA_WTURN0_OFS EQU 0x218 +EMC_STA_CFG1_OFS EQU 0x220 +EMC_STA_WWEN1_OFS EQU 0x224 +EMC_STA_WOEN1_OFS EQU 0x228 +EMC_STA_WRD1_OFS EQU 0x22C +EMC_STA_WPAGE1_OFS EQU 0x230 +EMC_STA_WWR1_OFS EQU 0x234 +EMC_STA_WTURN1_OFS EQU 0x238 +EMC_STA_CFG2_OFS EQU 0x240 +EMC_STA_WWEN2_OFS EQU 0x244 +EMC_STA_WOEN2_OFS EQU 0x248 +EMC_STA_WRD2_OFS EQU 0x24C +EMC_STA_WPAGE2_OFS EQU 0x250 +EMC_STA_WWR2_OFS EQU 0x254 +EMC_STA_WTURN2_OFS EQU 0x258 +EMC_STA_CFG3_OFS EQU 0x260 +EMC_STA_WWEN3_OFS EQU 0x264 +EMC_STA_WOEN3_OFS EQU 0x268 +EMC_STA_WRD3_OFS EQU 0x26C +EMC_STA_WPAGE3_OFS EQU 0x270 +EMC_STA_WWR3_OFS EQU 0x274 +EMC_STA_WTURN3_OFS EQU 0x278 +EMC_STA_EXT_W_OFS EQU 0x880 + +; Constants +NORMAL_CMD EQU (0x0 << 7) ; NORMAL Command +MODE_CMD EQU (0x1 << 7) ; MODE Command +PALL_CMD EQU (0x2 << 7) ; Precharge All Command +NOP_CMD EQU (0x3 << 7) ; NOP Command + +BUFEN_Const EQU (1 << 19) ; Buffer enable bit +EMC_PCONP_Const EQU (1 << 11) ; PCONP val to enable power for EMC + +; External Memory Pins definitions +; pin functions for SDRAM, NOR and NAND flash interfacing +EMC_PINSEL5_Val EQU 0x05010115 ; !CAS, !RAS, CLKOUT0, !DYCS0, DQMOUT0, DQMOUT1 +EMC_PINSEL6_Val EQU 0x55555555 ; D0 .. D15 +EMC_PINSEL8_Val EQU 0x55555555 ; A0 .. A15 +EMC_PINSEL9_Val EQU 0x50055555; ; A16 .. A23, !OE, !WE, !CS0, !CS1 + +;// External Memory Controller Setup (EMC) --------------------------------- +;// <e> External Memory Controller Setup (EMC) +EMC_SETUP EQU 0 + +;// <h> EMC Control Register (EMCControl) +;// <i> Controls operation of the memory controller +;// <o0.2> L: Low-power mode enable +;// <o0.1> M: Address mirror enable +;// <o0.0> E: EMC enable +;// </h> +EMC_CTRL_Val EQU 0x00000001 + +;// <h> EMC Configuration Register (EMCConfig) +;// <i> Configures operation of the memory controller +;// <o0.8> CCLK: CLKOUT ratio +;// <0=> 1:1 +;// <1=> 1:2 +;// <o0.0> Endian mode +;// <0=> Little-endian +;// <1=> Big-endian +;// </h> +EMC_CONFIG_Val EQU 0x00000000 + +;// Dynamic Memory Interface Setup --------------------------------------- +;// <e> Dynamic Memory Interface Setup +EMC_DYNAMIC_SETUP EQU 1 + +;// <h> Dynamic Memory Refresh Timer Register (EMCDynamicRefresh) +;// <i> Configures dynamic memory refresh operation +;// <o0.0..10> REFRESH: Refresh timer <0x000-0x7FF> +;// <i> 0 = refresh disabled, 0x01-0x7FF: value * 16 CCLKS +;// </h> +EMC_DYN_RFSH_Val EQU 0x0000001C + +;// <h> Dynamic Memory Read Configuration Register (EMCDynamicReadConfig) +;// <i> Configures the dynamic memory read strategy +;// <o0.0..1> RD: Read data strategy +;// <0=> Clock out delayed strategy +;// <1=> Command delayed strategy +;// <2=> Command delayed strategy plus one clock cycle +;// <3=> Command delayed strategy plus two clock cycles +;// </h> +EMC_DYN_RD_CFG_Val EQU 0x00000001 + +;// <h> Dynamic Memory Timings +;// <h> Dynamic Memory Percentage Command Period Register (EMCDynamictRP) +;// <o0.0..3> tRP: Precharge command period <1-16> <#-1> +;// <i> The delay is in EMCCLK cycles +;// <i> This value is normally found in SDRAM data sheets as tRP +;// </h> +;// <h> Dynamic Memory Active to Precharge Command Period Register (EMCDynamictRAS) +;// <o1.0..3> tRAS: Active to precharge command period <1-16> <#-1> +;// <i> The delay is in EMCCLK cycles +;// <i> This value is normally found in SDRAM data sheets as tRAS +;// </h> +;// <h> Dynamic Memory Self-refresh Exit Time Register (EMCDynamictSREX) +;// <o2.0..3> tSREX: Self-refresh exit time <1-16> <#-1> +;// <i> The delay is in CCLK cycles +;// <i> This value is normally found in SDRAM data sheets as tSREX, +;// <i> for devices without this parameter you use the same value as tXSR +;// </h> +;// <h> Dynamic Memory Last Data Out to Active Time Register (EMCDynamictAPR) +;// <o3.0..3> tAPR: Last-data-out to active command time <1-16> <#-1> +;// <i> The delay is in CCLK cycles +;// <i> This value is normally found in SDRAM data sheets as tAPR +;// </h> +;// <h> Dynamic Memory Data-in to Active Command Time Register (EMCDynamictDAL) +;// <o4.0..3> tDAL: Data-in to active command time <1-16> <#-1> +;// <i> The delay is in CCLK cycles +;// <i> This value is normally found in SDRAM data sheets as tDAL or tAPW +;// </h> +;// <h> Dynamic Memory Write Recovery Time Register (EMCDynamictWR) +;// <o5.0..3> tWR: Write recovery time <1-16> <#-1> +;// <i> The delay is in CCLK cycles +;// <i> This value is normally found in SDRAM data sheets as tWR, tDPL, tRWL, or tRDL +;// </h> +;// <h> Dynamic Memory Active to Active Command Period Register (EMCDynamictRC) +;// <o6.0..4> tRC: Active to active command period <1-32> <#-1> +;// <i> The delay is in CCLK cycles +;// <i> This value is normally found in SDRAM data sheets as tRC +;// </h> +;// <h> Dynamic Memory Auto-refresh Period Register (EMCDynamictRFC) +;// <o7.0..4> tRFC: Auto-refresh period and auto-refresh to active command period <1-32> <#-1> +;// <i> The delay is in CCLK cycles +;// <i> This value is normally found in SDRAM data sheets as tRFC or tRC +;// </h> +;// <h> Dynamic Memory Exit Self-refresh Register (EMCDynamictXSR) +;// <o8.0..4> tXSR: Exit self-refresh to active command time <1-32> <#-1> +;// <i> The delay is in CCLK cycles +;// <i> This value is normally found in SDRAM data sheets as tXSR +;// </h> +;// <h> Dynamic Memory Active Bank A to Active Bank B Time Register (EMCDynamicRRD) +;// <o9.0..3> tRRD: Active bank A to active bank B latency <1-16> <#-1> +;// <i> The delay is in CCLK cycles +;// <i> This value is normally found in SDRAM data sheets as tRRD +;// </h> +;// <h> Dynamic Memory Load Mode Register to Active Command Time (EMCDynamictMRD) +;// <o10.0..3> tMRD: Load mode register to active command time <1-16> <#-1> +;// <i> The delay is in CCLK cycles +;// <i> This value is normally found in SDRAM data sheets as tMRD or tRSA +;// </h> +;// </h> +EMC_DYN_RP_Val EQU 0x00000002 +EMC_DYN_RAS_Val EQU 0x00000003 +EMC_DYN_SREX_Val EQU 0x00000007 +EMC_DYN_APR_Val EQU 0x00000002 +EMC_DYN_DAL_Val EQU 0x00000005 +EMC_DYN_WR_Val EQU 0x00000001 +EMC_DYN_RC_Val EQU 0x00000005 +EMC_DYN_RFC_Val EQU 0x00000005 +EMC_DYN_XSR_Val EQU 0x00000007 +EMC_DYN_RRD_Val EQU 0x00000001 +EMC_DYN_MRD_Val EQU 0x00000002 + +;// <e> Configure External Bus Behaviour for Dynamic CS0 Area +EMC_DYNCS0_SETUP EQU 1 + +;// <h> Dynamic Memory Configuration Register (EMCDynamicConfig0) +;// <i> Defines the configuration information for the dynamic memory CS0 +;// <o0.20> P: Write protect +;// <o0.19> B: Buffer enable +;// <o0.14> AM 14: External bus data width +;// <0=> 16 bit +;// <1=> 32 bit +;// <o0.12> AM 12: External bus memory type +;// <0=> High-performance +;// <1=> Low-power SDRAM +;// <o0.7..11> AM 11..7: External bus address mapping (Row, Bank, Column) +;// <0x00=> 16 Mb = 2MB (2Mx8), 2 banks, row length = 11, column length = 9 +;// <0x01=> 16 Mb = 2MB (1Mx16), 2 banks, row length = 11, column length = 8 +;// <0x04=> 64 Mb = 8MB (8Mx8), 4 banks, row length = 12, column length = 9 +;// <0x05=> 64 Mb = 8MB (4Mx16), 4 banks, row length = 12, column length = 8 +;// <0x08=> 128 Mb = 16MB (16Mx8), 4 banks, row length = 12, column length = 10 +;// <0x09=> 128 Mb = 16MB (8Mx16), 4 banks, row length = 12, column length = 9 +;// <0x0C=> 256 Mb = 32MB (32Mx8), 4 banks, row length = 13, column length = 10 +;// <0x0D=> 256 Mb = 32MB (16Mx16), 4 banks, row length = 13, column length = 9 +;// <0x10=> 512 Mb = 64MB (64Mx8), 4 banks, row length = 13, column length = 11 +;// <0x11=> 512 Mb = 64MB (32Mx16), 4 banks, row length = 13, column length = 10 +;// <o0.3..4> MD: Memory device +;// <0=> SDRAM +;// <1=> Low-power SDRAM +;// <2=> Micron SyncFlash +;// </h> +EMC_DYN_CFG0_Val EQU 0x00080680 + +;// <h> Dynamic Memory RAS & CAS Delay register (EMCDynamicRASCAS0) +;// <i> Controls the RAS and CAS latencies for the dynamic memory CS0 +;// <o0.8..9> CAS: CAS latency +;// <1=> One CCLK cycle +;// <2=> Two CCLK cycles +;// <3=> Three CCLK cycles +;// <o0.0..1> RAS: RAS latency (active to read/write delay) +;// <1=> One CCLK cycle +;// <2=> Two CCLK cycles +;// <3=> Three CCLK cycles +;// </h> +EMC_DYN_RASCAS0_Val EQU 0x00000303 + +;// </e> End of Dynamic Setup for CS0 Area + + +;// <e> Configure External Bus Behaviour for Dynamic CS1 Area +EMC_DYNCS1_SETUP EQU 0 + +;// <h> Dynamic Memory Configuration Register (EMCDynamicConfig1) +;// <i> Defines the configuration information for the dynamic memory CS1 +;// <o0.20> P: Write protect +;// <o0.19> B: Buffer enable +;// <o0.14> AM 14: External bus data width +;// <0=> 16 bit +;// <1=> 32 bit +;// <o0.12> AM 12: External bus memory type +;// <0=> High-performance +;// <1=> Low-power SDRAM +;// <o0.7..11> AM 11..7: External bus address mapping (Row, Bank, Column) +;// <0x00=> 16 Mb = 2MB (2Mx8), 2 banks, row length = 11, column length = 9 +;// <0x01=> 16 Mb = 2MB (1Mx16), 2 banks, row length = 11, column length = 8 +;// <0x04=> 64 Mb = 8MB (8Mx8), 4 banks, row length = 12, column length = 9 +;// <0x05=> 64 Mb = 8MB (4Mx16), 4 banks, row length = 12, column length = 8 +;// <0x08=> 128 Mb = 16MB (16Mx8), 4 banks, row length = 12, column length = 10 +;// <0x09=> 128 Mb = 16MB (8Mx16), 4 banks, row length = 12, column length = 9 +;// <0x0C=> 256 Mb = 32MB (32Mx8), 4 banks, row length = 13, column length = 10 +;// <0x0D=> 256 Mb = 32MB (16Mx16), 4 banks, row length = 13, column length = 9 +;// <0x10=> 512 Mb = 64MB (64Mx8), 4 banks, row length = 13, column length = 11 +;// <0x11=> 512 Mb = 64MB (32Mx16), 4 banks, row length = 13, column length = 10 +;// <o0.3..4> MD: Memory device +;// <0=> SDRAM +;// <1=> Low-power SDRAM +;// <2=> Micron SyncFlash +;// </h> +EMC_DYN_CFG1_Val EQU 0x00000000 + +;// <h> Dynamic Memory RAS & CAS Delay register (EMCDynamicRASCAS1) +;// <i> Controls the RAS and CAS latencies for the dynamic memory CS1 +;// <o0.8..9> CAS: CAS latency +;// <1=> One CCLK cycle +;// <2=> Two CCLK cycles +;// <3=> Three CCLK cycles +;// <o0.0..1> RAS: RAS latency (active to read/write delay) +;// <1=> One CCLK cycle +;// <2=> Two CCLK cycles +;// <3=> Three CCLK cycles +;// </h> +EMC_DYN_RASCAS1_Val EQU 0x00000303 + +;// </e> End of Dynamic Setup for CS1 Area + +;// <e> Configure External Bus Behaviour for Dynamic CS2 Area +EMC_DYNCS2_SETUP EQU 0 + +;// <h> Dynamic Memory Configuration Register (EMCDynamicConfig2) +;// <i> Defines the configuration information for the dynamic memory CS2 +;// <o0.20> P: Write protect +;// <o0.19> B: Buffer enable +;// <o0.14> AM 14: External bus data width +;// <0=> 16 bit +;// <1=> 32 bit +;// <o0.12> AM 12: External bus memory type +;// <0=> High-performance +;// <1=> Low-power SDRAM +;// <o0.7..11> AM 11..7: External bus address mapping (Row, Bank, Column) +;// <0x00=> 16 Mb = 2MB (2Mx8), 2 banks, row length = 11, column length = 9 +;// <0x01=> 16 Mb = 2MB (1Mx16), 2 banks, row length = 11, column length = 8 +;// <0x04=> 64 Mb = 8MB (8Mx8), 4 banks, row length = 12, column length = 9 +;// <0x05=> 64 Mb = 8MB (4Mx16), 4 banks, row length = 12, column length = 8 +;// <0x08=> 128 Mb = 16MB (16Mx8), 4 banks, row length = 12, column length = 10 +;// <0x09=> 128 Mb = 16MB (8Mx16), 4 banks, row length = 12, column length = 9 +;// <0x0C=> 256 Mb = 32MB (32Mx8), 4 banks, row length = 13, column length = 10 +;// <0x0D=> 256 Mb = 32MB (16Mx16), 4 banks, row length = 13, column length = 9 +;// <0x10=> 512 Mb = 64MB (64Mx8), 4 banks, row length = 13, column length = 11 +;// <0x11=> 512 Mb = 64MB (32Mx16), 4 banks, row length = 13, column length = 10 +;// <o0.3..4> MD: Memory device +;// <0=> SDRAM +;// <1=> Low-power SDRAM +;// <2=> Micron SyncFlash +;// </h> +EMC_DYN_CFG2_Val EQU 0x00000000 + +;// <h> Dynamic Memory RAS & CAS Delay register (EMCDynamicRASCAS2) +;// <i> Controls the RAS and CAS latencies for the dynamic memory CS2 +;// <o0.8..9> CAS: CAS latency +;// <1=> One CCLK cycle +;// <2=> Two CCLK cycles +;// <3=> Three CCLK cycles +;// <o0.0..1> RAS: RAS latency (active to read/write delay) +;// <1=> One CCLK cycle +;// <2=> Two CCLK cycles +;// <3=> Three CCLK cycles +;// </h> +EMC_DYN_RASCAS2_Val EQU 0x00000303 + +;// </e> End of Dynamic Setup for CS2 Area + +;// <e> Configure External Bus Behaviour for Dynamic CS3 Area +EMC_DYNCS3_SETUP EQU 0 + +;// <h> Dynamic Memory Configuration Register (EMCDynamicConfig3) +;// <i> Defines the configuration information for the dynamic memory CS3 +;// <o0.20> P: Write protect +;// <o0.19> B: Buffer enable +;// <o0.14> AM 14: External bus data width +;// <0=> 16 bit +;// <1=> 32 bit +;// <o0.12> AM 12: External bus memory type +;// <0=> High-performance +;// <1=> Low-power SDRAM +;// <o0.7..11> AM 11..7: External bus address mapping (Row, Bank, Column) +;// <0x00=> 16 Mb = 2MB (2Mx8), 2 banks, row length = 11, column length = 9 +;// <0x01=> 16 Mb = 2MB (1Mx16), 2 banks, row length = 11, column length = 8 +;// <0x04=> 64 Mb = 8MB (8Mx8), 4 banks, row length = 12, column length = 9 +;// <0x05=> 64 Mb = 8MB (4Mx16), 4 banks, row length = 12, column length = 8 +;// <0x08=> 128 Mb = 16MB (16Mx8), 4 banks, row length = 12, column length = 10 +;// <0x09=> 128 Mb = 16MB (8Mx16), 4 banks, row length = 12, column length = 9 +;// <0x0C=> 256 Mb = 32MB (32Mx8), 4 banks, row length = 13, column length = 10 +;// <0x0D=> 256 Mb = 32MB (16Mx16), 4 banks, row length = 13, column length = 9 +;// <0x10=> 512 Mb = 64MB (64Mx8), 4 banks, row length = 13, column length = 11 +;// <0x11=> 512 Mb = 64MB (32Mx16), 4 banks, row length = 13, column length = 10 +;// <o0.3..4> MD: Memory device +;// <0=> SDRAM +;// <1=> Low-power SDRAM +;// <2=> Micron SyncFlash +;// </h> +EMC_DYN_CFG3_Val EQU 0x00000000 + +;// <h> Dynamic Memory RAS & CAS Delay register (EMCDynamicRASCAS3) +;// <i> Controls the RAS and CAS latencies for the dynamic memory CS3 +;// <o0.8..9> CAS: CAS latency +;// <1=> One CCLK cycle +;// <2=> Two CCLK cycles +;// <3=> Three CCLK cycles +;// <o0.0..1> RAS: RAS latency (active to read/write delay) +;// <1=> One CCLK cycle +;// <2=> Two CCLK cycles +;// <3=> Three CCLK cycles +;// </h> +EMC_DYN_RASCAS3_Val EQU 0x00000303 + +;// </e> End of Dynamic Setup for CS3 Area + +;// </e> End of Dynamic Setup + +;// Static Memory Interface Setup ---------------------------------------- +;// <e> Static Memory Interface Setup +EMC_STATIC_SETUP EQU 1 + +;// Configure External Bus Behaviour for Static CS0 Area --------------- +;// <e> Configure External Bus Behaviour for Static CS0 Area +EMC_STACS0_SETUP EQU 1 + +;// <h> Static Memory Configuration Register (EMCStaticConfig0) +;// <i> Defines the configuration information for the static memory CS0 +;// <o0.20> WP: Write protect +;// <o0.19> B: Buffer enable +;// <o0.8> EW: Extended wait enable +;// <o0.7> PB: Byte lane state +;// <0=> For reads BLSn are HIGH, for writes BLSn are LOW +;// <1=> For reads BLSn are LOW, for writes BLSn are LOW +;// <o0.6> PC: Chip select polarity +;// <0=> Active LOW chip select +;// <1=> Active HIGH chip select +;// <o0.3> PM: Page mode enable +;// <o0.0..1> MW: Memory width +;// <0=> 8 bit +;// <1=> 16 bit +;// <2=> 32 bit +;// </h> +EMC_STA_CFG0_Val EQU 0x00000081 + +;// <h> Static Memory Write Enable Delay Register (EMCStaticWaitWen0) +;// <i> Selects the delay from CS0 to write enable +;// <o.0..3> WAITWEN: Wait write enable <1-16> <#-1> +;// <i> The delay is in CCLK cycles +;// </h> +EMC_STA_WWEN0_Val EQU 0x00000002 + +;// <h> Static Memory Output Enable Delay register (EMCStaticWaitOen0) +;// <i> Selects the delay from CS0 or address change, whichever is later, to output enable +;// <o.0..3> WAITOEN: Wait output enable <0-15> +;// <i> The delay is in CCLK cycles +;// </h> +EMC_STA_WOEN0_Val EQU 0x00000002 + +;// <h> Static Memory Read Delay Register (EMCStaticWaitRd0) +;// <i> Selects the delay from CS0 to a read access +;// <o.0..4> WAITRD: Non-page mode read wait states or asynchronous page mode read first access wait states <1-32> <#-1> +;// <i> The delay is in CCLK cycles +;// </h> +EMC_STA_WRD0_Val EQU 0x0000001F + +;// <h> Static Memory Page Mode Read Delay Register (EMCStaticWaitPage0) +;// <i> Selects the delay for asynchronous page mode sequential accesses for CS0 +;// <o.0..4> WAITPAGE: Asynchronous page mode read after the first read wait states <1-32> <#-1> +;// <i> The delay is in CCLK cycles +;// </h> +EMC_STA_WPAGE0_Val EQU 0x0000001F + +;// <h> Static Memory Write Delay Register (EMCStaticWaitWr0) +;// <i> Selects the delay from CS0 to a write access +;// <o.0..4> WAITWR: Write wait states <2-33> <#-2> +;// <i> The delay is in CCLK cycles +;// </h> +EMC_STA_WWR0_Val EQU 0x0000001F + +;// <h> Static Memory Turn Round Delay Register (EMCStaticWaitTurn0) +;// <i> Selects the number of bus turnaround cycles for CS0 +;// <o.0..4> WAITTURN: Bus turnaround cycles <1-16> <#-1> +;// <i> The delay is in CCLK cycles +;// </h> +EMC_STA_WTURN0_Val EQU 0x0000000F + +;// </e> End of Static Setup for Static CS0 Area + +;// Configure External Bus Behaviour for Static CS1 Area --------------- +;// <e> Configure External Bus Behaviour for Static CS1 Area +EMC_STACS1_SETUP EQU 0 + +;// <h> Static Memory Configuration Register (EMCStaticConfig1) +;// <i> Defines the configuration information for the static memory CS1 +;// <o0.20> WP: Write protect +;// <o0.19> B: Buffer enable +;// <o0.8> EW: Extended wait enable +;// <o0.7> PB: Byte lane state +;// <0=> For reads BLSn are HIGH, for writes BLSn are LOW +;// <1=> For reads BLSn are LOW, for writes BLSn are LOW +;// <o0.6> PC: Chip select polarity +;// <0=> Active LOW chip select +;// <1=> Active HIGH chip select +;// <o0.3> PM: Page mode enable +;// <o0.0..1> MW: Memory width +;// <0=> 8 bit +;// <1=> 16 bit +;// <2=> 32 bit +;// </h> +EMC_STA_CFG1_Val EQU 0x00000000 + +;// <h> Static Memory Write Enable Delay Register (EMCStaticWaitWen1) +;// <i> Selects the delay from CS1 to write enable +;// <o.0..3> WAITWEN: Wait write enable <1-16> <#-1> +;// <i> The delay is in CCLK cycles +;// </h> +EMC_STA_WWEN1_Val EQU 0x00000000 + +;// <h> Static Memory Output Enable Delay register (EMCStaticWaitOen1) +;// <i> Selects the delay from CS1 or address change, whichever is later, to output enable +;// <o.0..3> WAITOEN: Wait output enable <0-15> +;// <i> The delay is in CCLK cycles +;// </h> +EMC_STA_WOEN1_Val EQU 0x00000000 + +;// <h> Static Memory Read Delay Register (EMCStaticWaitRd1) +;// <i> Selects the delay from CS1 to a read access +;// <o.0..4> WAITRD: Non-page mode read wait states or asynchronous page mode read first access wait states <1-32> <#-1> +;// <i> The delay is in CCLK cycles +;// </h> +EMC_STA_WRD1_Val EQU 0x0000001F + +;// <h> Static Memory Page Mode Read Delay Register (EMCStaticWaitPage0) +;// <i> Selects the delay for asynchronous page mode sequential accesses for CS1 +;// <o.0..4> WAITPAGE: Asynchronous page mode read after the first read wait states <1-32> <#-1> +;// <i> The delay is in CCLK cycles +;// </h> +EMC_STA_WPAGE1_Val EQU 0x0000001F + +;// <h> Static Memory Write Delay Register (EMCStaticWaitWr1) +;// <i> Selects the delay from CS1 to a write access +;// <o.0..4> WAITWR: Write wait states <2-33> <#-2> +;// <i> The delay is in CCLK cycles +;// </h> +EMC_STA_WWR1_Val EQU 0x0000001F + +;// <h> Static Memory Turn Round Delay Register (EMCStaticWaitTurn1) +;// <i> Selects the number of bus turnaround cycles for CS1 +;// <o.0..4> WAITTURN: Bus turnaround cycles <1-16> <#-1> +;// <i> The delay is in CCLK cycles +;// </h> +EMC_STA_WTURN1_Val EQU 0x0000000F + +;// </e> End of Static Setup for Static CS1 Area + +;// Configure External Bus Behaviour for Static CS2 Area --------------- +;// <e> Configure External Bus Behaviour for Static CS2 Area +EMC_STACS2_SETUP EQU 0 + +;// <h> Static Memory Configuration Register (EMCStaticConfig2) +;// <i> Defines the configuration information for the static memory CS2 +;// <o0.20> WP: Write protect +;// <o0.19> B: Buffer enable +;// <o0.8> EW: Extended wait enable +;// <o0.7> PB: Byte lane state +;// <0=> For reads BLSn are HIGH, for writes BLSn are LOW +;// <1=> For reads BLSn are LOW, for writes BLSn are LOW +;// <o0.6> PC: Chip select polarity +;// <0=> Active LOW chip select +;// <1=> Active HIGH chip select +;// <o0.3> PM: Page mode enable +;// <o0.0..1> MW: Memory width +;// <0=> 8 bit +;// <1=> 16 bit +;// <2=> 32 bit +;// </h> +EMC_STA_CFG2_Val EQU 0x00000000 + +;// <h> Static Memory Write Enable Delay Register (EMCStaticWaitWen2) +;// <i> Selects the delay from CS2 to write enable +;// <o.0..3> WAITWEN: Wait write enable <1-16> <#-1> +;// <i> The delay is in CCLK cycles +;// </h> +EMC_STA_WWEN2_Val EQU 0x00000000 + +;// <h> Static Memory Output Enable Delay register (EMCStaticWaitOen2) +;// <i> Selects the delay from CS2 or address change, whichever is later, to output enable +;// <o.0..3> WAITOEN: Wait output enable <0-15> +;// <i> The delay is in CCLK cycles +;// </h> +EMC_STA_WOEN2_Val EQU 0x00000000 + +;// <h> Static Memory Read Delay Register (EMCStaticWaitRd2) +;// <i> Selects the delay from CS2 to a read access +;// <o.0..4> WAITRD: Non-page mode read wait states or asynchronous page mode read first access wait states <1-32> <#-1> +;// <i> The delay is in CCLK cycles +;// </h> +EMC_STA_WRD2_Val EQU 0x0000001F + +;// <h> Static Memory Page Mode Read Delay Register (EMCStaticWaitPage2) +;// <i> Selects the delay for asynchronous page mode sequential accesses for CS2 +;// <o.0..4> WAITPAGE: Asynchronous page mode read after the first read wait states <1-32> <#-1> +;// <i> The delay is in CCLK cycles +;// </h> +EMC_STA_WPAGE2_Val EQU 0x0000001F + +;// <h> Static Memory Write Delay Register (EMCStaticWaitWr2) +;// <i> Selects the delay from CS2 to a write access +;// <o.0..4> WAITWR: Write wait states <2-33> <#-2> +;// <i> The delay is in CCLK cycles +;// </h> +EMC_STA_WWR2_Val EQU 0x0000001F + +;// <h> Static Memory Turn Round Delay Register (EMCStaticWaitTurn2) +;// <i> Selects the number of bus turnaround cycles for CS2 +;// <o.0..4> WAITTURN: Bus turnaround cycles <1-16> <#-1> +;// <i> The delay is in CCLK cycles +;// </h> +EMC_STA_WTURN2_Val EQU 0x0000000F + +;// </e> End of Static Setup for Static CS2 Area + +;// Configure External Bus Behaviour for Static CS3 Area --------------- +;// <e> Configure External Bus Behaviour for Static CS3 Area +EMC_STACS3_SETUP EQU 0 + +;// <h> Static Memory Configuration Register (EMCStaticConfig3) +;// <i> Defines the configuration information for the static memory CS3 +;// <o0.20> WP: Write protect +;// <o0.19> B: Buffer enable +;// <o0.8> EW: Extended wait enable +;// <o0.7> PB: Byte lane state +;// <0=> For reads BLSn are HIGH, for writes BLSn are LOW +;// <1=> For reads BLSn are LOW, for writes BLSn are LOW +;// <o0.6> PC: Chip select polarity +;// <0=> Active LOW chip select +;// <1=> Active HIGH chip select +;// <o0.3> PM: Page mode enable +;// <o0.0..1> MW: Memory width +;// <0=> 8 bit +;// <1=> 16 bit +;// <2=> 32 bit +;// </h> +EMC_STA_CFG3_Val EQU 0x00000000 + +;// <h> Static Memory Write Enable Delay Register (EMCStaticWaitWen3) +;// <i> Selects the delay from CS3 to write enable +;// <o.0..3> WAITWEN: Wait write enable <1-16> <#-1> +;// <i> The delay is in CCLK cycles +;// </h> +EMC_STA_WWEN3_Val EQU 0x00000000 + +;// <h> Static Memory Output Enable Delay register (EMCStaticWaitOen3) +;// <i> Selects the delay from CS3 or address change, whichever is later, to output enable +;// <o.0..3> WAITOEN: Wait output enable <0-15> +;// <i> The delay is in CCLK cycles +;// </h> +EMC_STA_WOEN3_Val EQU 0x00000000 + +;// <h> Static Memory Read Delay Register (EMCStaticWaitRd3) +;// <i> Selects the delay from CS3 to a read access +;// <o.0..4> WAITRD: Non-page mode read wait states or asynchronous page mode read first access wait states <1-32> <#-1> +;// <i> The delay is in CCLK cycles +;// </h> +EMC_STA_WRD3_Val EQU 0x0000001F + +;// <h> Static Memory Page Mode Read Delay Register (EMCStaticWaitPage3) +;// <i> Selects the delay for asynchronous page mode sequential accesses for CS3 +;// <o.0..4> WAITPAGE: Asynchronous page mode read after the first read wait states <1-32> <#-1> +;// <i> The delay is in CCLK cycles +;// </h> +EMC_STA_WPAGE3_Val EQU 0x0000001F + +;// <h> Static Memory Write Delay Register (EMCStaticWaitWr3) +;// <i> Selects the delay from CS3 to a write access +;// <o.0..4> WAITWR: Write wait states <2-33> <#-2> +;// <i> The delay is in CCLK cycles +;// </h> +EMC_STA_WWR3_Val EQU 0x0000001F + +;// <h> Static Memory Turn Round Delay Register (EMCStaticWaitTurn3) +;// <i> Selects the number of bus turnaround cycles for CS3 +;// <o.0..4> WAITTURN: Bus turnaround cycles <1-16> <#-1> +;// <i> The delay is in CCLK cycles +;// </h> +EMC_STA_WTURN3_Val EQU 0x0000000F + +;// </e> End of Static Setup for Static CS3 Area + +;// <h> Static Memory Extended Wait Register (EMCStaticExtendedWait) +;// <i> Time long static memory read and write transfers +;// <o.0..9> EXTENDEDWAIT: Extended wait time out <0-1023> +;// <i> The delay is in (16 * CCLK) cycles +;// </h> +EMC_STA_EXT_W_Val EQU 0x00000000 + +;// </e> End of Static Setup + +;// </e> End of EMC Setup + + + PRESERVE8 + +; Area Definition and Entry Point +; Startup Code must be linked first at Address at which it expects to run. + + AREA RESET, CODE, READONLY + ARM + + +; Exception Vectors +; Mapped to Address 0. +; Absolute addressing mode must be used. +; Dummy Handlers are implemented as infinite loops which can be modified. + +Vectors LDR PC, Reset_Addr + LDR PC, Undef_Addr + LDR PC, SWI_Addr + LDR PC, PAbt_Addr + LDR PC, DAbt_Addr + NOP ; Reserved Vector + LDR PC, IRQ_Addr + LDR PC, FIQ_Addr + +Reset_Addr DCD Reset_Handler +Undef_Addr DCD Undef_Handler +SWI_Addr DCD SWI_Handler +PAbt_Addr DCD PAbt_Handler +DAbt_Addr DCD DAbt_Handler + DCD 0 ; Reserved Address +IRQ_Addr DCD IRQ_Handler +FIQ_Addr DCD FIQ_Handler + + +; Exception Handler + IMPORT rt_hw_trap_udef + IMPORT rt_hw_trap_swi + IMPORT rt_hw_trap_pabt + IMPORT rt_hw_trap_dabt + IMPORT rt_hw_trap_fiq + +; Prepare Fatal Context + MACRO + prepare_fatal + STMFD sp!, {r0-r3} + MOV r1, sp + ADD sp, sp, #16 + SUB r2, lr, #4 + MRS r3, spsr + + ; switch to SVC mode and no interrupt + MSR cpsr_c, #I_Bit :OR: F_Bit :OR: Mode_SVC + + STMFD sp!, {r0} ; old r0 + ; get sp + ADD r0, sp, #4 + STMFD sp!, {r3} ; cpsr + STMFD sp!, {r2} ; pc + STMFD sp!, {lr} ; lr + STMFD sp!, {r0} ; sp + STMFD sp!, {r4-r12} + + MOV r4, r1 + + LDMFD r4!, {r0-r3} + STMFD sp!, {r0-r3} + + MOV r0, sp + MEND + +Undef_Handler + prepare_fatal + BL rt_hw_trap_irq + B . + +SWI_Handler + prepare_fatal + BL rt_hw_trap_swi + B . + +PAbt_Handler + prepare_fatal + BL rt_hw_trap_pabt + B . + +DAbt_Handler + prepare_fatal + BL rt_hw_trap_dabt + B . + +FIQ_Handler + prepare_fatal + BL rt_hw_trap_fiq + B . + +; Reset Handler + + EXPORT Reset_Handler +Reset_Handler + + +; Clock Setup ------------------------------------------------------------------ + + IF (:LNOT:(:DEF:NO_CLOCK_SETUP)):LAND:(CLOCK_SETUP != 0) + LDR R0, =SCB_BASE + MOV R1, #0xAA + MOV R2, #0x55 + +; Configure and Enable PLL + LDR R3, =SCS_Val ; Enable main oscillator + STR R3, [R0, #SCS_OFS] + + IF (SCS_Val:AND:OSCEN) != 0 +OSC_Loop LDR R3, [R0, #SCS_OFS] ; Wait for main osc stabilize + ANDS R3, R3, #OSCSTAT + BEQ OSC_Loop + ENDIF + + LDR R3, =CLKSRCSEL_Val ; Select PLL source clock + STR R3, [R0, #CLKSRCSEL_OFS] + LDR R3, =PLLCFG_Val + STR R3, [R0, #PLLCFG_OFS] + STR R1, [R0, #PLLFEED_OFS] + STR R2, [R0, #PLLFEED_OFS] + MOV R3, #PLLCON_PLLE + STR R3, [R0, #PLLCON_OFS] + STR R1, [R0, #PLLFEED_OFS] + STR R2, [R0, #PLLFEED_OFS] + + IF (CLKSRCSEL_Val:AND:3) != 2 +; Wait until PLL Locked (if source is not RTC oscillator) +PLL_Loop LDR R3, [R0, #PLLSTAT_OFS] + ANDS R3, R3, #PLLSTAT_PLOCK + BEQ PLL_Loop + ELSE +; Wait at least 200 cycles (if source is RTC oscillator) + MOV R3, #(200/4) +PLL_Loop SUBS R3, R3, #1 + BNE PLL_Loop + ENDIF + +M_N_Lock LDR R3, [R0, #PLLSTAT_OFS] + LDR R4, =(PLLSTAT_M:OR:PLLSTAT_N) + AND R3, R3, R4 + LDR R4, =PLLCFG_Val + EORS R3, R3, R4 + BNE M_N_Lock + +; Setup CPU clock divider + MOV R3, #CCLKCFG_Val + STR R3, [R0, #CCLKCFG_OFS] + +; Setup USB clock divider + LDR R3, =USBCLKCFG_Val + STR R3, [R0, #USBCLKCFG_OFS] + +; Setup Peripheral Clock + LDR R3, =PCLKSEL0_Val + STR R3, [R0, #PCLKSEL0_OFS] + LDR R3, =PCLKSEL1_Val + STR R3, [R0, #PCLKSEL1_OFS] + +; Switch to PLL Clock + MOV R3, #(PLLCON_PLLE:OR:PLLCON_PLLC) + STR R3, [R0, #PLLCON_OFS] + STR R1, [R0, #PLLFEED_OFS] + STR R2, [R0, #PLLFEED_OFS] + ENDIF ; CLOCK_SETUP + + +; Setup Memory Accelerator Module ---------------------------------------------- + + IF MAM_SETUP != 0 + LDR R0, =MAM_BASE + MOV R1, #MAMTIM_Val + STR R1, [R0, #MAMTIM_OFS] + MOV R1, #MAMCR_Val + STR R1, [R0, #MAMCR_OFS] + ENDIF ; MAM_SETUP + + +; Setup External Memory Controller --------------------------------------------- + + IF (:LNOT:(:DEF:NO_EMC_SETUP)):LAND:(EMC_SETUP != 0) + LDR R0, =EMC_BASE + LDR R1, =SCB_BASE + LDR R2, =PCB_BASE + + LDR R4, =EMC_PCONP_Const ; Enable EMC + LDR R3, [R1, #PCONP_OFS] + ORR R4, R4, R3 + STR R4, [R1, #PCONP_OFS] + + LDR R4, =EMC_CTRL_Val + STR R4, [R0, #EMC_CTRL_OFS] + LDR R4, =EMC_CONFIG_Val + STR R4, [R0, #EMC_CONFIG_OFS] + +; Setup pin functions for External Bus functionality + LDR R4, =EMC_PINSEL5_Val + STR R4, [R2, #PINSEL5_OFS] + LDR R4, =EMC_PINSEL6_Val + STR R4, [R2, #PINSEL6_OFS] + LDR R4, =EMC_PINSEL8_Val + STR R4, [R2, #PINSEL8_OFS] + LDR R4, =EMC_PINSEL9_Val + STR R4, [R2, #PINSEL9_OFS] + +; Setup Dynamic Memory Interface + IF (EMC_DYNAMIC_SETUP != 0) + + LDR R4, =EMC_DYN_RP_Val + STR R4, [R0, #EMC_DYN_RP_OFS] + LDR R4, =EMC_DYN_RAS_Val + STR R4, [R0, #EMC_DYN_RAS_OFS] + LDR R4, =EMC_DYN_SREX_Val + STR R4, [R0, #EMC_DYN_SREX_OFS] + LDR R4, =EMC_DYN_APR_Val + STR R4, [R0, #EMC_DYN_APR_OFS] + LDR R4, =EMC_DYN_DAL_Val + STR R4, [R0, #EMC_DYN_DAL_OFS] + LDR R4, =EMC_DYN_WR_Val + STR R4, [R0, #EMC_DYN_WR_OFS] + LDR R4, =EMC_DYN_RC_Val + STR R4, [R0, #EMC_DYN_RC_OFS] + LDR R4, =EMC_DYN_RFC_Val + STR R4, [R0, #EMC_DYN_RFC_OFS] + LDR R4, =EMC_DYN_XSR_Val + STR R4, [R0, #EMC_DYN_XSR_OFS] + LDR R4, =EMC_DYN_RRD_Val + STR R4, [R0, #EMC_DYN_RRD_OFS] + LDR R4, =EMC_DYN_MRD_Val + STR R4, [R0, #EMC_DYN_MRD_OFS] + + LDR R4, =EMC_DYN_RD_CFG_Val + STR R4, [R0, #EMC_DYN_RD_CFG_OFS] + + IF (EMC_DYNCS0_SETUP != 0) + LDR R4, =EMC_DYN_RASCAS0_Val + STR R4, [R0, #EMC_DYN_RASCAS0_OFS] + LDR R4, =EMC_DYN_CFG0_Val + MVN R5, #BUFEN_Const + AND R4, R4, R5 + STR R4, [R0, #EMC_DYN_CFG0_OFS] + ENDIF + IF (EMC_DYNCS1_SETUP != 0) + LDR R4, =EMC_DYN_RASCAS1_Val + STR R4, [R0, #EMC_DYN_RASCAS1_OFS] + LDR R4, =EMC_DYN_CFG1_Val + MVN R5, =BUFEN_Const + AND R4, R4, R5 + STR R4, [R0, #EMC_DYN_CFG1_OFS] + ENDIF + IF (EMC_DYNCS2_SETUP != 0) + LDR R4, =EMC_DYN_RASCAS2_Val + STR R4, [R0, #EMC_DYN_RASCAS2_OFS] + LDR R4, =EMC_DYN_CFG2_Val + MVN R5, =BUFEN_Const + AND R4, R4, R5 + STR R4, [R0, #EMC_DYN_CFG2_OFS] + ENDIF + IF (EMC_DYNCS3_SETUP != 0) + LDR R4, =EMC_DYN_RASCAS3_Val + STR R4, [R0, #EMC_DYN_RASCAS3_OFS] + LDR R4, =EMC_DYN_CFG3_Val + MVN R5, =BUFEN_Const + AND R4, R4, R5 + STR R4, [R0, #EMC_DYN_CFG3_OFS] + ENDIF + + LDR R6, =1440000 ; Number of cycles to delay +Wait_0 SUBS R6, R6, #1 ; Delay ~100 ms proc clk 57.6 MHz + BNE Wait_0 ; BNE (3 cyc) + SUBS (1 cyc) = 4 cyc + + LDR R4, =(NOP_CMD:OR:0x03) ; Write NOP Command + STR R4, [R0, #EMC_DYN_CTRL_OFS] + + LDR R6, =2880000 ; Number of cycles to delay +Wait_1 SUBS R6, R6, #1 ; Delay ~200 ms proc clk 57.6 MHz + BNE Wait_1 + + LDR R4, =(PALL_CMD:OR:0x03) ; Write Precharge All Command + STR R4, [R0, #EMC_DYN_CTRL_OFS] + + MOV R4, #2 + STR R4, [R0, #EMC_DYN_RFSH_OFS] + + MOV R6, #64 ; Number of cycles to delay +Wait_2 SUBS R6, R6, #1 ; Delay + BNE Wait_2 + + LDR R4, =EMC_DYN_RFSH_Val + STR R4, [R0, #EMC_DYN_RFSH_OFS] + + LDR R4, =(MODE_CMD:OR:0x03) ; Write MODE Command + STR R4, [R0, #EMC_DYN_CTRL_OFS] + + ; Dummy read + IF (EMC_DYNCS0_SETUP != 0) + LDR R4, =DYN_MEM0_BASE + MOV R5, #(0x33 << 12) + ADD R4, R4, R5 + LDR R4, [R4, #0] + ENDIF + IF (EMC_DYNCS1_SETUP != 0) + LDR R4, =DYN_MEM1_BASE + MOV R5, #(0x33 << 12) + ADD R4, R4, R5 + LDR R4, [R4, #0] + ENDIF + IF (EMC_DYNCS2_SETUP != 0) + LDR R4, =DYN_MEM2_BASE + MOV R5, #(0x33 << 12) + ADD R4, R4, R5 + LDR R4, [R4, #0] + ENDIF + IF (EMC_DYNCS3_SETUP != 0) + LDR R4, =DYN_MEM3_BASE + MOV R5, #(0x33 << 12) + ADD R4, R4, R5 + LDR R4, [R4, #0] + ENDIF + + LDR R4, =NORMAL_CMD ; Write NORMAL Command + STR R4, [R0, #EMC_DYN_CTRL_OFS] + + ; Enable buffer if requested by settings + IF (EMC_DYNCS0_SETUP != 0):LAND:((EMC_DYN_CFG0_Val:AND:BUFEN_Const) != 0) + LDR R4, =EMC_DYN_CFG0_Val + STR R4, [R0, #EMC_DYN_CFG0_OFS] + ENDIF + IF (EMC_DYNCS1_SETUP != 0):LAND:((EMC_DYN_CFG1_Val:AND:BUFEN_Const) != 0) + LDR R4, =EMC_DYN_CFG1_Val + STR R4, [R0, #EMC_DYN_CFG1_OFS] + ENDIF + IF (EMC_DYNCS2_SETUP != 0):LAND:((EMC_DYN_CFG2_Val:AND:BUFEN_Const) != 0) + LDR R4, =EMC_DYN_CFG2_Val + STR R4, [R0, #EMC_DYN_CFG2_OFS] + ENDIF + IF (EMC_DYNCS3_SETUP != 0):LAND:((EMC_DYN_CFG3_Val:AND:BUFEN_Const) != 0) + LDR R4, =EMC_DYN_CFG3_Val + STR R4, [R0, #EMC_DYN_CFG3_OFS] + ENDIF + + LDR R6, =14400 ; Number of cycles to delay +Wait_3 SUBS R6, R6, #1 ; Delay ~1 ms @ proc clk 57.6 MHz + BNE Wait_3 + + ENDIF ; EMC_DYNAMIC_SETUP + +; Setup Static Memory Interface + IF (EMC_STATIC_SETUP != 0) + + LDR R6, =1440000 ; Number of cycles to delay +Wait_4 SUBS R6, R6, #1 ; Delay ~100 ms @ proc clk 57.6 MHz + BNE Wait_4 + + IF (EMC_STACS0_SETUP != 0) + LDR R4, =EMC_STA_CFG0_Val + STR R4, [R0, #EMC_STA_CFG0_OFS] + LDR R4, =EMC_STA_WWEN0_Val + STR R4, [R0, #EMC_STA_WWEN0_OFS] + LDR R4, =EMC_STA_WOEN0_Val + STR R4, [R0, #EMC_STA_WOEN0_OFS] + LDR R4, =EMC_STA_WRD0_Val + STR R4, [R0, #EMC_STA_WRD0_OFS] + LDR R4, =EMC_STA_WPAGE0_Val + STR R4, [R0, #EMC_STA_WPAGE0_OFS] + LDR R4, =EMC_STA_WWR0_Val + STR R4, [R0, #EMC_STA_WWR0_OFS] + LDR R4, =EMC_STA_WTURN0_Val + STR R4, [R0, #EMC_STA_WTURN0_OFS] + ENDIF + + IF (EMC_STACS1_SETUP != 0) + LDR R4, =EMC_STA_CFG1_Val + STR R4, [R0, #EMC_STA_CFG1_OFS] + LDR R4, =EMC_STA_WWEN1_Val + STR R4, [R0, #EMC_STA_WWEN1_OFS] + LDR R4, =EMC_STA_WOEN1_Val + STR R4, [R0, #EMC_STA_WOEN1_OFS] + LDR R4, =EMC_STA_WRD1_Val + STR R4, [R0, #EMC_STA_WRD1_OFS] + LDR R4, =EMC_STA_WPAGE1_Val + STR R4, [R0, #EMC_STA_WPAGE1_OFS] + LDR R4, =EMC_STA_WWR1_Val + STR R4, [R0, #EMC_STA_WWR1_OFS] + LDR R4, =EMC_STA_WTURN1_Val + STR R4, [R0, #EMC_STA_WTURN1_OFS] + ENDIF + + IF (EMC_STACS2_SETUP != 0) + LDR R4, =EMC_STA_CFG2_Val + STR R4, [R0, #EMC_STA_CFG2_OFS] + LDR R4, =EMC_STA_WWEN2_Val + STR R4, [R0, #EMC_STA_WWEN2_OFS] + LDR R4, =EMC_STA_WOEN2_Val + STR R4, [R0, #EMC_STA_WOEN2_OFS] + LDR R4, =EMC_STA_WRD2_Val + STR R4, [R0, #EMC_STA_WRD2_OFS] + LDR R4, =EMC_STA_WPAGE2_Val + STR R4, [R0, #EMC_STA_WPAGE2_OFS] + LDR R4, =EMC_STA_WWR2_Val + STR R4, [R0, #EMC_STA_WWR2_OFS] + LDR R4, =EMC_STA_WTURN2_Val + STR R4, [R0, #EMC_STA_WTURN2_OFS] + ENDIF + + IF (EMC_STACS3_SETUP != 0) + LDR R4, =EMC_STA_CFG3_Val + STR R4, [R0, #EMC_STA_CFG3_OFS] + LDR R4, =EMC_STA_WWEN3_Val + STR R4, [R0, #EMC_STA_WWEN3_OFS] + LDR R4, =EMC_STA_WOEN3_Val + STR R4, [R0, #EMC_STA_WOEN3_OFS] + LDR R4, =EMC_STA_WRD3_Val + STR R4, [R0, #EMC_STA_WRD3_OFS] + LDR R4, =EMC_STA_WPAGE3_Val + STR R4, [R0, #EMC_STA_WPAGE3_OFS] + LDR R4, =EMC_STA_WWR3_Val + STR R4, [R0, #EMC_STA_WWR3_OFS] + LDR R4, =EMC_STA_WTURN3_Val + STR R4, [R0, #EMC_STA_WTURN3_OFS] + ENDIF + + LDR R6, =144000 ; Number of cycles to delay +Wait_5 SUBS R6, R6, #1 ; Delay ~10 ms @ proc clk 57.6 MHz + BNE Wait_5 + + LDR R4, =EMC_STA_EXT_W_Val + LDR R5, =EMC_STA_EXT_W_OFS + ADD R5, R5, R0 + STR R4, [R5, #0] + + ENDIF ; EMC_STATIC_SETUP + + ENDIF ; EMC_SETUP + + +; Copy Exception Vectors to Internal RAM --------------------------------------- + + IF :DEF:RAM_INTVEC + ADR R8, Vectors ; Source + LDR R9, =RAM_BASE ; Destination + LDMIA R8!, {R0-R7} ; Load Vectors + STMIA R9!, {R0-R7} ; Store Vectors + LDMIA R8!, {R0-R7} ; Load Handler Addresses + STMIA R9!, {R0-R7} ; Store Handler Addresses + ENDIF + + +; Memory Mapping (when Interrupt Vectors are in RAM) --------------------------- + +MEMMAP EQU 0xE01FC040 ; Memory Mapping Control + IF :DEF:REMAP + LDR R0, =MEMMAP + IF :DEF:EXTMEM_MODE + MOV R1, #3 + ELIF :DEF:RAM_MODE + MOV R1, #2 + ELSE + MOV R1, #1 + ENDIF + STR R1, [R0] + ENDIF + + +; Setup Stack for each mode ---------------------------------------------------- + + LDR R0, =Stack_Top + +; Enter Undefined Instruction Mode and set its Stack Pointer + MSR CPSR_c, #Mode_UND:OR:I_Bit:OR:F_Bit + MOV SP, R0 + SUB R0, R0, #UND_Stack_Size + +; Enter Abort Mode and set its Stack Pointer + MSR CPSR_c, #Mode_ABT:OR:I_Bit:OR:F_Bit + MOV SP, R0 + SUB R0, R0, #ABT_Stack_Size + +; Enter FIQ Mode and set its Stack Pointer + MSR CPSR_c, #Mode_FIQ:OR:I_Bit:OR:F_Bit + MOV SP, R0 + SUB R0, R0, #FIQ_Stack_Size + +; Enter IRQ Mode and set its Stack Pointer + MSR CPSR_c, #Mode_IRQ:OR:I_Bit:OR:F_Bit + MOV SP, R0 + SUB R0, R0, #IRQ_Stack_Size + +; Enter Supervisor Mode and set its Stack Pointer + MSR CPSR_c, #Mode_SVC:OR:I_Bit:OR:F_Bit + MOV SP, R0 + SUB R0, R0, #SVC_Stack_Size + + IF :DEF:__MICROLIB + EXPORT __initial_sp + ELSE + ENDIF + +; Enter the C code ------------------------------------------------------------- + + IMPORT __main + LDR R0, =__main + BX R0 + + IMPORT rt_interrupt_enter + IMPORT rt_interrupt_leave + IMPORT rt_thread_switch_interrupt_flag + IMPORT rt_interrupt_from_thread + IMPORT rt_interrupt_to_thread + IMPORT rt_hw_trap_irq + +IRQ_Handler PROC + EXPORT IRQ_Handler + STMFD sp!, {r0-r12,lr} + BL rt_interrupt_enter + BL rt_hw_trap_irq + BL rt_interrupt_leave + + ; if rt_thread_switch_interrupt_flag set, jump to + ; rt_hw_context_switch_interrupt_do and don't return + LDR r0, =rt_thread_switch_interrupt_flag + LDR r1, [r0] + CMP r1, #1 + BEQ rt_hw_context_switch_interrupt_do + + LDMFD sp!, {r0-r12,lr} + SUBS pc, lr, #4 + ENDP + +; /* +; * void rt_hw_context_switch_interrupt_do(rt_base_t flag) +; */ +rt_hw_context_switch_interrupt_do PROC + EXPORT rt_hw_context_switch_interrupt_do + MOV r1, #0 ; clear flag + STR r1, [r0] + + LDMFD sp!, {r0-r12,lr}; reload saved registers + STMFD sp!, {r0-r3} ; save r0-r3 + MOV r1, sp + ADD sp, sp, #16 ; restore sp + SUB r2, lr, #4 ; save old task's pc to r2 + + MRS r3, spsr ; get cpsr of interrupt thread + + ; switch to SVC mode and no interrupt + MSR cpsr_c, #I_Bit :OR: F_Bit :OR: Mode_SVC + + STMFD sp!, {r2} ; push old task's pc + STMFD sp!, {r4-r12,lr}; push old task's lr,r12-r4 + MOV r4, r1 ; Special optimised code below + MOV r5, r3 + LDMFD r4!, {r0-r3} + STMFD sp!, {r0-r3} ; push old task's r3-r0 + STMFD sp!, {r5} ; push old task's cpsr + + LDR r4, =rt_interrupt_from_thread + LDR r5, [r4] + STR sp, [r5] ; store sp in preempted tasks's TCB + + LDR r6, =rt_interrupt_to_thread + LDR r6, [r6] + LDR sp, [r6] ; get new task's stack pointer + + LDMFD sp!, {r4} ; pop new task's cpsr to spsr + MSR spsr_cxsf, r4 + BIC r4, r4, #0x20 ; must be ARM mode + MSR cpsr_cxsf, r4 + + LDMFD sp!, {r0-r12,lr,pc}^ ; pop new task's r0-r12,lr & pc, copy spsr to cpsr + ENDP + + IF :DEF:__MICROLIB + + EXPORT __heap_base + EXPORT __heap_limit + + ELSE +; User Initial Stack & Heap + AREA |.text|, CODE, READONLY + + IMPORT __use_two_region_memory + EXPORT __user_initial_stackheap +__user_initial_stackheap + + LDR R0, = Heap_Mem + LDR R1, =(Stack_Mem + USR_Stack_Size) + LDR R2, = (Heap_Mem + Heap_Size) + LDR R3, = Stack_Mem + BX LR + ENDIF + + + END diff --git a/libcpu/arm/s3c24x0/context_rvds.S b/libcpu/arm/s3c24x0/context_rvds.S index 6fe5c5ea07..54d655afe1 100644 --- a/libcpu/arm/s3c24x0/context_rvds.S +++ b/libcpu/arm/s3c24x0/context_rvds.S @@ -12,12 +12,12 @@ ; * 2009-01-20 Bernard first version ; */ -NOINT EQU 0xc0 ; disable interrupt in psr
+NOINT EQU 0xc0 ; disable interrupt in psr - AREA |.text|, CODE, READONLY, ALIGN=2
- ARM
- REQUIRE8
- PRESERVE8
+ AREA |.text|, CODE, READONLY, ALIGN=2 + ARM + REQUIRE8 + PRESERVE8 ;/* ; * rt_base_t rt_hw_interrupt_disable(); @@ -26,16 +26,16 @@ rt_hw_interrupt_disable PROC EXPORT rt_hw_interrupt_disable MRS r0, cpsr ORR r1, r0, #NOINT - MSR cpsr_c, r1
+ MSR cpsr_c, r1 BX lr - ENDP
+ ENDP ;/* ; * void rt_hw_interrupt_enable(rt_base_t level); ; */ rt_hw_interrupt_enable PROC EXPORT rt_hw_interrupt_enable - MSR cpsr_c, r0
+ MSR cpsr_c, r0 BX lr ENDP @@ -63,7 +63,7 @@ rt_hw_context_switch PROC MSR spsr_cxsf, r4 LDMFD sp!, {r0-r12, lr, pc}^ ; pop new task r0-r12, lr & pc - ENDP
+ ENDP ;/* ; * void rt_hw_context_switch_to(rt_uint32 to); @@ -79,14 +79,14 @@ rt_hw_context_switch_to PROC MSR cpsr_cxsf, r4 LDMFD sp!, {r0-r12, lr, pc} ; pop new task r0-r12, lr & pc - ENDP
+ ENDP ;/* ; * void rt_hw_context_switch_interrupt(rt_uint32 from, rt_uint32 to); ; */ IMPORT rt_thread_switch_interrupt_flag IMPORT rt_interrupt_from_thread - IMPORT rt_interrupt_to_thread
+ IMPORT rt_interrupt_to_thread rt_hw_context_switch_interrupt PROC EXPORT rt_hw_context_switch_interrupt @@ -100,8 +100,8 @@ rt_hw_context_switch_interrupt PROC STR r0, [r2] _reswitch LDR r2, =rt_interrupt_to_thread ; set rt_interrupt_to_thread - STR r1, [r2]
+ STR r1, [r2] BX lr - ENDP
-
+ ENDP + END
\ No newline at end of file diff --git a/libcpu/arm/s3c24x0/cpu.c b/libcpu/arm/s3c24x0/cpu.c index a9845f4125..907f08145a 100644 --- a/libcpu/arm/s3c24x0/cpu.c +++ b/libcpu/arm/s3c24x0/cpu.c @@ -1,190 +1,190 @@ -/*
- * File : cpu.c
- * This file is part of RT-Thread RTOS
- * COPYRIGHT (C) 2006, RT-Thread Develop Team
- *
- * The license and distribution terms for this file may be
- * found in the file LICENSE in this distribution or at
- * http://openlab.rt-thread.com/license/LICENSE
- *
- * Change Logs:
- * Date Author Notes
- * 2006-03-13 Bernard first version
- */
-
-#include <rthw.h>
-#include <rtthread.h>
-#include "s3c24x0.h"
-
-/**
- * @addtogroup S3C24X0
- */
-/*@{*/
-
-#define ICACHE_MASK (rt_uint32_t)(1 << 12)
-#define DCACHE_MASK (rt_uint32_t)(1 << 2)
-
-#ifdef __GNUC__
-rt_inline rt_uint32_t cp15_rd(void)
-{
- rt_uint32_t i;
-
- asm ("mrc p15, 0, %0, c1, c0, 0":"=r" (i));
- return i;
-}
-
-rt_inline void cache_enable(rt_uint32_t bit)
-{
- __asm__ __volatile__( \
- "mrc p15,0,r0,c1,c0,0\n\t" \
- "orr r0,r0,%0\n\t" \
- "mcr p15,0,r0,c1,c0,0" \
- : \
- :"r" (bit) \
- :"memory");
-}
-
-rt_inline void cache_disable(rt_uint32_t bit)
-{
- __asm__ __volatile__( \
- "mrc p15,0,r0,c1,c0,0\n\t" \
- "bic r0,r0,%0\n\t" \
- "mcr p15,0,r0,c1,c0,0" \
- : \
- :"r" (bit) \
- :"memory");
-}
-#endif
-
-#ifdef __CC_ARM
-rt_inline rt_uint32_t cp15_rd(void)
-{
- rt_uint32_t i;
-
- __asm
- {
- mrc p15, 0, i, c1, c0, 0
- }
-
- return i;
-}
-
-rt_inline void cache_enable(rt_uint32_t bit)
-{
- rt_uint32_t value;
-
- __asm
- {
- mrc p15, 0, value, c1, c0, 0
- orr value, value, bit
- mcr p15, 0, value, c1, c0, 0
- }
-}
-
-rt_inline void cache_disable(rt_uint32_t bit)
-{
- rt_uint32_t value;
-
- __asm
- {
- mrc p15, 0, value, c1, c0, 0
- bic value, value, bit
- mcr p15, 0, value, c1, c0, 0
- }
-}
-#endif
-
-/**
- * enable I-Cache
- *
- */
-void rt_hw_cpu_icache_enable()
-{
- cache_enable(ICACHE_MASK);
-}
-
-/**
- * disable I-Cache
- *
- */
-void rt_hw_cpu_icache_disable()
-{
- cache_disable(ICACHE_MASK);
-}
-
-/**
- * return the status of I-Cache
- *
- */
-rt_base_t rt_hw_cpu_icache_status()
-{
- return (cp15_rd() & ICACHE_MASK);
-}
-
-/**
- * enable D-Cache
- *
- */
-void rt_hw_cpu_dcache_enable()
-{
- cache_enable(DCACHE_MASK);
-}
-
-/**
- * disable D-Cache
- *
- */
-void rt_hw_cpu_dcache_disable()
-{
- cache_disable(DCACHE_MASK);
-}
-
-/**
- * return the status of D-Cache
- *
- */
-rt_base_t rt_hw_cpu_dcache_status()
-{
- return (cp15_rd() & DCACHE_MASK);
-}
-
-/**
- * reset cpu by dog's time-out
- *
- */
-void rt_hw_cpu_reset()
-{
- /* Disable all interrupt except the WDT */
- INTMSK = (~((rt_uint32_t)1 << INTWDT));
-
- /* Disable watchdog */
- WTCON = 0x0000;
-
- /* Initialize watchdog timer count register */
- WTCNT = 0x0001;
-
- /* Enable watchdog timer; assert reset at timer timeout */
- WTCON = 0x0021;
-
- while(1); /* loop forever and wait for reset to happen */
-
- /* NEVER REACHED */
-}
-
-/**
- * shutdown CPU
- *
- */
-void rt_hw_cpu_shutdown()
-{
- rt_uint32_t level;
- rt_kprintf("shutdown...\n");
-
- level = rt_hw_interrupt_disable();
- while (level)
- {
- RT_ASSERT(0);
- }
-}
-
-/*@}*/
+/* + * File : cpu.c + * This file is part of RT-Thread RTOS + * COPYRIGHT (C) 2006, RT-Thread Develop Team + * + * The license and distribution terms for this file may be + * found in the file LICENSE in this distribution or at + * http://openlab.rt-thread.com/license/LICENSE + * + * Change Logs: + * Date Author Notes + * 2006-03-13 Bernard first version + */ + +#include <rthw.h> +#include <rtthread.h> +#include "s3c24x0.h" + +/** + * @addtogroup S3C24X0 + */ +/*@{*/ + +#define ICACHE_MASK (rt_uint32_t)(1 << 12) +#define DCACHE_MASK (rt_uint32_t)(1 << 2) + +#ifdef __GNUC__ +rt_inline rt_uint32_t cp15_rd(void) +{ + rt_uint32_t i; + + asm ("mrc p15, 0, %0, c1, c0, 0":"=r" (i)); + return i; +} + +rt_inline void cache_enable(rt_uint32_t bit) +{ + __asm__ __volatile__( \ + "mrc p15,0,r0,c1,c0,0\n\t" \ + "orr r0,r0,%0\n\t" \ + "mcr p15,0,r0,c1,c0,0" \ + : \ + :"r" (bit) \ + :"memory"); +} + +rt_inline void cache_disable(rt_uint32_t bit) +{ + __asm__ __volatile__( \ + "mrc p15,0,r0,c1,c0,0\n\t" \ + "bic r0,r0,%0\n\t" \ + "mcr p15,0,r0,c1,c0,0" \ + : \ + :"r" (bit) \ + :"memory"); +} +#endif + +#ifdef __CC_ARM +rt_inline rt_uint32_t cp15_rd(void) +{ + rt_uint32_t i; + + __asm + { + mrc p15, 0, i, c1, c0, 0 + } + + return i; +} + +rt_inline void cache_enable(rt_uint32_t bit) +{ + rt_uint32_t value; + + __asm + { + mrc p15, 0, value, c1, c0, 0 + orr value, value, bit + mcr p15, 0, value, c1, c0, 0 + } +} + +rt_inline void cache_disable(rt_uint32_t bit) +{ + rt_uint32_t value; + + __asm + { + mrc p15, 0, value, c1, c0, 0 + bic value, value, bit + mcr p15, 0, value, c1, c0, 0 + } +} +#endif + +/** + * enable I-Cache + * + */ +void rt_hw_cpu_icache_enable() +{ + cache_enable(ICACHE_MASK); +} + +/** + * disable I-Cache + * + */ +void rt_hw_cpu_icache_disable() +{ + cache_disable(ICACHE_MASK); +} + +/** + * return the status of I-Cache + * + */ +rt_base_t rt_hw_cpu_icache_status() +{ + return (cp15_rd() & ICACHE_MASK); +} + +/** + * enable D-Cache + * + */ +void rt_hw_cpu_dcache_enable() +{ + cache_enable(DCACHE_MASK); +} + +/** + * disable D-Cache + * + */ +void rt_hw_cpu_dcache_disable() +{ + cache_disable(DCACHE_MASK); +} + +/** + * return the status of D-Cache + * + */ +rt_base_t rt_hw_cpu_dcache_status() +{ + return (cp15_rd() & DCACHE_MASK); +} + +/** + * reset cpu by dog's time-out + * + */ +void rt_hw_cpu_reset() +{ + /* Disable all interrupt except the WDT */ + INTMSK = (~((rt_uint32_t)1 << INTWDT)); + + /* Disable watchdog */ + WTCON = 0x0000; + + /* Initialize watchdog timer count register */ + WTCNT = 0x0001; + + /* Enable watchdog timer; assert reset at timer timeout */ + WTCON = 0x0021; + + while(1); /* loop forever and wait for reset to happen */ + + /* NEVER REACHED */ +} + +/** + * shutdown CPU + * + */ +void rt_hw_cpu_shutdown() +{ + rt_uint32_t level; + rt_kprintf("shutdown...\n"); + + level = rt_hw_interrupt_disable(); + while (level) + { + RT_ASSERT(0); + } +} + +/*@}*/ diff --git a/libcpu/arm/s3c24x0/mmu.c b/libcpu/arm/s3c24x0/mmu.c index cb14c4cab7..2bc79deca6 100644 --- a/libcpu/arm/s3c24x0/mmu.c +++ b/libcpu/arm/s3c24x0/mmu.c @@ -1,394 +1,394 @@ -/*
- * File : mmu.c
- * This file is part of RT-Thread RTOS
- * COPYRIGHT (C) 2006, RT-Thread Development Team
- *
- * The license and distribution terms for this file may be
- * found in the file LICENSE in this distribution or at
- * http://www.rt-thread.org/license/LICENSE
- *
- * Change Logs:
- * Date Author Notes
- * 2008-04-25 Yi.qiu first version
- * 2009-12-18 Bernard port to armcc
- */
-
-#include <rtthread.h>
-#include "s3c24x0.h"
-
-#define _MMUTT_STARTADDRESS 0x33FF0000
-
-#define DESC_SEC (0x2|(1<<4))
-#define CB (3<<2) //cache_on, write_back
-#define CNB (2<<2) //cache_on, write_through
-#define NCB (1<<2) //cache_off,WR_BUF on
-#define NCNB (0<<2) //cache_off,WR_BUF off
-#define AP_RW (3<<10) //supervisor=RW, user=RW
-#define AP_RO (2<<10) //supervisor=RW, user=RO
-
-#define DOMAIN_FAULT (0x0)
-#define DOMAIN_CHK (0x1)
-#define DOMAIN_NOTCHK (0x3)
-#define DOMAIN0 (0x0<<5)
-#define DOMAIN1 (0x1<<5)
-
-#define DOMAIN0_ATTR (DOMAIN_CHK<<0)
-#define DOMAIN1_ATTR (DOMAIN_FAULT<<2)
-
-#define RW_CB (AP_RW|DOMAIN0|CB|DESC_SEC)
-#define RW_CNB (AP_RW|DOMAIN0|CNB|DESC_SEC)
-#define RW_NCNB (AP_RW|DOMAIN0|NCNB|DESC_SEC)
-#define RW_FAULT (AP_RW|DOMAIN1|NCNB|DESC_SEC)
-
-#ifdef __GNUC__
-void mmu_setttbase(register rt_uint32_t i)
-{
- asm ("mcr p15, 0, %0, c2, c0, 0": :"r" (i));
-}
-
-void mmu_set_domain(register rt_uint32_t i)
-{
- asm ("mcr p15,0, %0, c3, c0, 0": :"r" (i));
-}
-
-void mmu_enable()
-{
- register rt_uint32_t i;
-
- /* read control register */
- asm ("mrc p15, 0, %0, c1, c0, 0":"=r" (i));
-
- i |= 0x1;
-
- /* write back to control register */
- asm ("mcr p15, 0, %0, c1, c0, 0": :"r" (i));
-}
-
-void mmu_disable()
-{
- register rt_uint32_t i;
-
- /* read control register */
- asm ("mrc p15, 0, %0, c1, c0, 0":"=r" (i));
-
- i &= ~0x1;
-
- /* write back to control register */
- asm ("mcr p15, 0, %0, c1, c0, 0": :"r" (i));
-}
-
-void mmu_enable_icache()
-{
- register rt_uint32_t i;
-
- /* read control register */
- asm ("mrc p15, 0, %0, c1, c0, 0":"=r" (i));
-
- i |= (1 << 12);
-
- /* write back to control register */
- asm ("mcr p15, 0, %0, c1, c0, 0": :"r" (i));
-}
-
-void mmu_enable_dcache()
-{
- register rt_uint32_t i;
-
- /* read control register */
- asm ("mrc p15, 0, %0, c1, c0, 0":"=r" (i));
-
- i |= (1 << 2);
-
- /* write back to control register */
- asm ("mcr p15, 0, %0, c1, c0, 0": :"r" (i));
-}
-
-void mmu_disable_icache()
-{
- register rt_uint32_t i;
-
- /* read control register */
- asm ("mrc p15, 0, %0, c1, c0, 0":"=r" (i));
-
- i &= ~(1 << 12);
-
- /* write back to control register */
- asm ("mcr p15, 0, %0, c1, c0, 0": :"r" (i));
-}
-
-void mmu_disable_dcache()
-{
- register rt_uint32_t i;
-
- /* read control register */
- asm ("mrc p15, 0, %0, c1, c0, 0":"=r" (i));
-
- i &= ~(1 << 2);
-
- /* write back to control register */
- asm ("mcr p15, 0, %0, c1, c0, 0": :"r" (i));
-}
-
-void mmu_enable_alignfault()
-{
- register rt_uint32_t i;
-
- /* read control register */
- asm ("mrc p15, 0, %0, c1, c0, 0":"=r" (i));
-
- i |= (1 << 1);
-
- /* write back to control register */
- asm ("mcr p15, 0, %0, c1, c0, 0": :"r" (i));
-}
-
-void mmu_disable_alignfault()
-{
- register rt_uint32_t i;
-
- /* read control register */
- asm ("mrc p15, 0, %0, c1, c0, 0":"=r" (i));
-
- i &= ~(1 << 1);
-
- /* write back to control register */
- asm ("mcr p15, 0, %0, c1, c0, 0": :"r" (i));
-}
-
-void mmu_clean_invalidated_cache_index(int index)
-{
- asm ("mcr p15, 0, %0, c7, c14, 2": :"r" (index));
-}
-
-void mmu_invalidate_tlb()
-{
- asm ("mcr p15, 0, %0, c8, c7, 0": :"r" (0));
-}
-
-void mmu_invalidate_icache()
-{
- asm ("mcr p15, 0, %0, c7, c5, 0": :"r" (0));
-}
-#endif
-
-#ifdef __CC_ARM
-void mmu_setttbase(rt_uint32_t i)
-{
- __asm
- {
- mcr p15, 0, i, c2, c0, 0
- }
-}
-
-void mmu_set_domain(rt_uint32_t i)
-{
- __asm
- {
- mcr p15,0, i, c3, c0, 0
- }
-}
-
-void mmu_enable()
-{
- register rt_uint32_t value;
-
- __asm
- {
- mrc p15, 0, value, c1, c0, 0
- orr value, value, #0x01
- mcr p15, 0, value, c1, c0, 0
- }
-}
-
-void mmu_disable()
-{
- register rt_uint32_t value;
-
- __asm
- {
- mrc p15, 0, value, c1, c0, 0
- bic value, value, #0x01
- mcr p15, 0, value, c1, c0, 0
- }
-}
-
-void mmu_enable_icache()
-{
- register rt_uint32_t value;
-
- __asm
- {
- mrc p15, 0, value, c1, c0, 0
- orr value, value, #0x1000
- mcr p15, 0, value, c1, c0, 0
- }
-}
-
-void mmu_enable_dcache()
-{
- register rt_uint32_t value;
-
- __asm
- {
- mrc p15, 0, value, c1, c0, 0
- orr value, value, #0x04
- mcr p15, 0, value, c1, c0, 0
- }
-}
-
-void mmu_disable_icache()
-{
- register rt_uint32_t value;
-
- __asm
- {
- mrc p15, 0, value, c1, c0, 0
- bic value, value, #0x1000
- mcr p15, 0, value, c1, c0, 0
- }
-}
-
-void mmu_disable_dcache()
-{
- register rt_uint32_t value;
-
- __asm
- {
- mrc p15, 0, value, c1, c0, 0
- bic value, value, #0x04
- mcr p15, 0, value, c1, c0, 0
- }
-}
-
-void mmu_enable_alignfault()
-{
- register rt_uint32_t value;
-
- __asm
- {
- mrc p15, 0, value, c1, c0, 0
- orr value, value, #0x02
- mcr p15, 0, value, c1, c0, 0
- }
-}
-
-void mmu_disable_alignfault()
-{
- register rt_uint32_t value;
-
- __asm
- {
- mrc p15, 0, value, c1, c0, 0
- bic value, value, #0x02
- mcr p15, 0, value, c1, c0, 0
- }
-}
-
-void mmu_clean_invalidated_cache_index(int index)
-{
- __asm
- {
- mcr p15, 0, index, c7, c14, 2
- }
-}
-
-void mmu_invalidate_tlb()
-{
- register rt_uint32_t value;
-
- value = 0;
- __asm
- {
- mcr p15, 0, value, c8, c7, 0
- }
-}
-
-void mmu_invalidate_icache()
-{
- register rt_uint32_t value;
-
- value = 0;
-
- __asm
- {
- mcr p15, 0, value, c7, c5, 0
- }
-}
-#endif
-
-void mmu_setmtt(int vaddrStart,int vaddrEnd,int paddrStart,int attr)
-{
- volatile rt_uint32_t *pTT;
- volatile int i,nSec;
- pTT=(rt_uint32_t *)_MMUTT_STARTADDRESS+(vaddrStart>>20);
- nSec=(vaddrEnd>>20)-(vaddrStart>>20);
- for(i=0;i<=nSec;i++)
- {
- *pTT = attr |(((paddrStart>>20)+i)<<20);
- pTT++;
- }
-}
-
-void rt_hw_mmu_init(void)
-{
- int i,j;
- //========================== IMPORTANT NOTE =========================
- //The current stack and code area can't be re-mapped in this routine.
- //If you want memory map mapped freely, your own sophiscated mmu
- //initialization code is needed.
- //===================================================================
-
- mmu_disable_dcache();
- mmu_disable_icache();
-
- //If write-back is used,the DCache should be cleared.
- for(i=0;i<64;i++)
- for(j=0;j<8;j++)
- mmu_clean_invalidated_cache_index((i<<26)|(j<<5));
-
- mmu_invalidate_icache();
-
- //To complete mmu_Init() fast, Icache may be turned on here.
- mmu_enable_icache();
-
- mmu_disable();
- mmu_invalidate_tlb();
-
- //mmu_setmtt(int vaddrStart,int vaddrEnd,int paddrStart,int attr);
- mmu_setmtt(0x00000000,0x07f00000,0x00000000,RW_CNB); //bank0
- mmu_setmtt(0x00000000,0x03f00000,(int)0x30000000,RW_CB); //bank0
- mmu_setmtt(0x04000000,0x07f00000,0,RW_NCNB); //bank0
- mmu_setmtt(0x08000000,0x0ff00000,0x08000000,RW_CNB); //bank1
- mmu_setmtt(0x10000000,0x17f00000,0x10000000,RW_NCNB); //bank2
- mmu_setmtt(0x18000000,0x1ff00000,0x18000000,RW_NCNB); //bank3
- //mmu_setmtt(0x20000000,0x27f00000,0x20000000,RW_CB); //bank4
- mmu_setmtt(0x20000000,0x27f00000,0x20000000,RW_NCNB); //bank4 for DM9000
- mmu_setmtt(0x28000000,0x2ff00000,0x28000000,RW_NCNB); //bank5
- //30f00000->30100000, 31000000->30200000
- mmu_setmtt(0x30000000,0x30100000,0x30000000,RW_CB); //bank6-1
- mmu_setmtt(0x30200000,0x33e00000,0x30200000,RW_CB); //bank6-2
-
- mmu_setmtt(0x33f00000,0x34000000,0x33f00000,RW_NCNB); //bank6-3
- mmu_setmtt(0x38000000,0x3ff00000,0x38000000,RW_NCNB); //bank7
-
- mmu_setmtt(0x40000000,0x47f00000,0x40000000,RW_NCNB); //SFR
- mmu_setmtt(0x48000000,0x5af00000,0x48000000,RW_NCNB); //SFR
- mmu_setmtt(0x5b000000,0x5b000000,0x5b000000,RW_NCNB); //SFR
- mmu_setmtt(0x5b100000,0xfff00000,0x5b100000,RW_FAULT);//not used
- mmu_setmtt(0x60000000,0x67f00000,0x60000000,RW_NCNB); //SFR
-
- mmu_setttbase(_MMUTT_STARTADDRESS);
-
- /* DOMAIN1: no_access, DOMAIN0,2~15=client(AP is checked) */
- mmu_set_domain(0x55555550|DOMAIN1_ATTR|DOMAIN0_ATTR);
-
- mmu_enable_alignfault();
-
- mmu_enable();
-
- /* ICache enable */
- mmu_enable_icache();
- /* DCache should be turned on after mmu is turned on. */
- mmu_enable_dcache();
-}
-
+/* + * File : mmu.c + * This file is part of RT-Thread RTOS + * COPYRIGHT (C) 2006, RT-Thread Development Team + * + * The license and distribution terms for this file may be + * found in the file LICENSE in this distribution or at + * http://www.rt-thread.org/license/LICENSE + * + * Change Logs: + * Date Author Notes + * 2008-04-25 Yi.qiu first version + * 2009-12-18 Bernard port to armcc + */ + +#include <rtthread.h> +#include "s3c24x0.h" + +#define _MMUTT_STARTADDRESS 0x33FF0000 + +#define DESC_SEC (0x2|(1<<4)) +#define CB (3<<2) //cache_on, write_back +#define CNB (2<<2) //cache_on, write_through +#define NCB (1<<2) //cache_off,WR_BUF on +#define NCNB (0<<2) //cache_off,WR_BUF off +#define AP_RW (3<<10) //supervisor=RW, user=RW +#define AP_RO (2<<10) //supervisor=RW, user=RO + +#define DOMAIN_FAULT (0x0) +#define DOMAIN_CHK (0x1) +#define DOMAIN_NOTCHK (0x3) +#define DOMAIN0 (0x0<<5) +#define DOMAIN1 (0x1<<5) + +#define DOMAIN0_ATTR (DOMAIN_CHK<<0) +#define DOMAIN1_ATTR (DOMAIN_FAULT<<2) + +#define RW_CB (AP_RW|DOMAIN0|CB|DESC_SEC) +#define RW_CNB (AP_RW|DOMAIN0|CNB|DESC_SEC) +#define RW_NCNB (AP_RW|DOMAIN0|NCNB|DESC_SEC) +#define RW_FAULT (AP_RW|DOMAIN1|NCNB|DESC_SEC) + +#ifdef __GNUC__ +void mmu_setttbase(register rt_uint32_t i) +{ + asm ("mcr p15, 0, %0, c2, c0, 0": :"r" (i)); +} + +void mmu_set_domain(register rt_uint32_t i) +{ + asm ("mcr p15,0, %0, c3, c0, 0": :"r" (i)); +} + +void mmu_enable() +{ + register rt_uint32_t i; + + /* read control register */ + asm ("mrc p15, 0, %0, c1, c0, 0":"=r" (i)); + + i |= 0x1; + + /* write back to control register */ + asm ("mcr p15, 0, %0, c1, c0, 0": :"r" (i)); +} + +void mmu_disable() +{ + register rt_uint32_t i; + + /* read control register */ + asm ("mrc p15, 0, %0, c1, c0, 0":"=r" (i)); + + i &= ~0x1; + + /* write back to control register */ + asm ("mcr p15, 0, %0, c1, c0, 0": :"r" (i)); +} + +void mmu_enable_icache() +{ + register rt_uint32_t i; + + /* read control register */ + asm ("mrc p15, 0, %0, c1, c0, 0":"=r" (i)); + + i |= (1 << 12); + + /* write back to control register */ + asm ("mcr p15, 0, %0, c1, c0, 0": :"r" (i)); +} + +void mmu_enable_dcache() +{ + register rt_uint32_t i; + + /* read control register */ + asm ("mrc p15, 0, %0, c1, c0, 0":"=r" (i)); + + i |= (1 << 2); + + /* write back to control register */ + asm ("mcr p15, 0, %0, c1, c0, 0": :"r" (i)); +} + +void mmu_disable_icache() +{ + register rt_uint32_t i; + + /* read control register */ + asm ("mrc p15, 0, %0, c1, c0, 0":"=r" (i)); + + i &= ~(1 << 12); + + /* write back to control register */ + asm ("mcr p15, 0, %0, c1, c0, 0": :"r" (i)); +} + +void mmu_disable_dcache() +{ + register rt_uint32_t i; + + /* read control register */ + asm ("mrc p15, 0, %0, c1, c0, 0":"=r" (i)); + + i &= ~(1 << 2); + + /* write back to control register */ + asm ("mcr p15, 0, %0, c1, c0, 0": :"r" (i)); +} + +void mmu_enable_alignfault() +{ + register rt_uint32_t i; + + /* read control register */ + asm ("mrc p15, 0, %0, c1, c0, 0":"=r" (i)); + + i |= (1 << 1); + + /* write back to control register */ + asm ("mcr p15, 0, %0, c1, c0, 0": :"r" (i)); +} + +void mmu_disable_alignfault() +{ + register rt_uint32_t i; + + /* read control register */ + asm ("mrc p15, 0, %0, c1, c0, 0":"=r" (i)); + + i &= ~(1 << 1); + + /* write back to control register */ + asm ("mcr p15, 0, %0, c1, c0, 0": :"r" (i)); +} + +void mmu_clean_invalidated_cache_index(int index) +{ + asm ("mcr p15, 0, %0, c7, c14, 2": :"r" (index)); +} + +void mmu_invalidate_tlb() +{ + asm ("mcr p15, 0, %0, c8, c7, 0": :"r" (0)); +} + +void mmu_invalidate_icache() +{ + asm ("mcr p15, 0, %0, c7, c5, 0": :"r" (0)); +} +#endif + +#ifdef __CC_ARM +void mmu_setttbase(rt_uint32_t i) +{ + __asm + { + mcr p15, 0, i, c2, c0, 0 + } +} + +void mmu_set_domain(rt_uint32_t i) +{ + __asm + { + mcr p15,0, i, c3, c0, 0 + } +} + +void mmu_enable() +{ + register rt_uint32_t value; + + __asm + { + mrc p15, 0, value, c1, c0, 0 + orr value, value, #0x01 + mcr p15, 0, value, c1, c0, 0 + } +} + +void mmu_disable() +{ + register rt_uint32_t value; + + __asm + { + mrc p15, 0, value, c1, c0, 0 + bic value, value, #0x01 + mcr p15, 0, value, c1, c0, 0 + } +} + +void mmu_enable_icache() +{ + register rt_uint32_t value; + + __asm + { + mrc p15, 0, value, c1, c0, 0 + orr value, value, #0x1000 + mcr p15, 0, value, c1, c0, 0 + } +} + +void mmu_enable_dcache() +{ + register rt_uint32_t value; + + __asm + { + mrc p15, 0, value, c1, c0, 0 + orr value, value, #0x04 + mcr p15, 0, value, c1, c0, 0 + } +} + +void mmu_disable_icache() +{ + register rt_uint32_t value; + + __asm + { + mrc p15, 0, value, c1, c0, 0 + bic value, value, #0x1000 + mcr p15, 0, value, c1, c0, 0 + } +} + +void mmu_disable_dcache() +{ + register rt_uint32_t value; + + __asm + { + mrc p15, 0, value, c1, c0, 0 + bic value, value, #0x04 + mcr p15, 0, value, c1, c0, 0 + } +} + +void mmu_enable_alignfault() +{ + register rt_uint32_t value; + + __asm + { + mrc p15, 0, value, c1, c0, 0 + orr value, value, #0x02 + mcr p15, 0, value, c1, c0, 0 + } +} + +void mmu_disable_alignfault() +{ + register rt_uint32_t value; + + __asm + { + mrc p15, 0, value, c1, c0, 0 + bic value, value, #0x02 + mcr p15, 0, value, c1, c0, 0 + } +} + +void mmu_clean_invalidated_cache_index(int index) +{ + __asm + { + mcr p15, 0, index, c7, c14, 2 + } +} + +void mmu_invalidate_tlb() +{ + register rt_uint32_t value; + + value = 0; + __asm + { + mcr p15, 0, value, c8, c7, 0 + } +} + +void mmu_invalidate_icache() +{ + register rt_uint32_t value; + + value = 0; + + __asm + { + mcr p15, 0, value, c7, c5, 0 + } +} +#endif + +void mmu_setmtt(int vaddrStart,int vaddrEnd,int paddrStart,int attr) +{ + volatile rt_uint32_t *pTT; + volatile int i,nSec; + pTT=(rt_uint32_t *)_MMUTT_STARTADDRESS+(vaddrStart>>20); + nSec=(vaddrEnd>>20)-(vaddrStart>>20); + for(i=0;i<=nSec;i++) + { + *pTT = attr |(((paddrStart>>20)+i)<<20); + pTT++; + } +} + +void rt_hw_mmu_init(void) +{ + int i,j; + //========================== IMPORTANT NOTE ========================= + //The current stack and code area can't be re-mapped in this routine. + //If you want memory map mapped freely, your own sophiscated mmu + //initialization code is needed. + //=================================================================== + + mmu_disable_dcache(); + mmu_disable_icache(); + + //If write-back is used,the DCache should be cleared. + for(i=0;i<64;i++) + for(j=0;j<8;j++) + mmu_clean_invalidated_cache_index((i<<26)|(j<<5)); + + mmu_invalidate_icache(); + + //To complete mmu_Init() fast, Icache may be turned on here. + mmu_enable_icache(); + + mmu_disable(); + mmu_invalidate_tlb(); + + //mmu_setmtt(int vaddrStart,int vaddrEnd,int paddrStart,int attr); + mmu_setmtt(0x00000000,0x07f00000,0x00000000,RW_CNB); //bank0 + mmu_setmtt(0x00000000,0x03f00000,(int)0x30000000,RW_CB); //bank0 + mmu_setmtt(0x04000000,0x07f00000,0,RW_NCNB); //bank0 + mmu_setmtt(0x08000000,0x0ff00000,0x08000000,RW_CNB); //bank1 + mmu_setmtt(0x10000000,0x17f00000,0x10000000,RW_NCNB); //bank2 + mmu_setmtt(0x18000000,0x1ff00000,0x18000000,RW_NCNB); //bank3 + //mmu_setmtt(0x20000000,0x27f00000,0x20000000,RW_CB); //bank4 + mmu_setmtt(0x20000000,0x27f00000,0x20000000,RW_NCNB); //bank4 for DM9000 + mmu_setmtt(0x28000000,0x2ff00000,0x28000000,RW_NCNB); //bank5 + //30f00000->30100000, 31000000->30200000 + mmu_setmtt(0x30000000,0x30100000,0x30000000,RW_CB); //bank6-1 + mmu_setmtt(0x30200000,0x33e00000,0x30200000,RW_CB); //bank6-2 + + mmu_setmtt(0x33f00000,0x34000000,0x33f00000,RW_NCNB); //bank6-3 + mmu_setmtt(0x38000000,0x3ff00000,0x38000000,RW_NCNB); //bank7 + + mmu_setmtt(0x40000000,0x47f00000,0x40000000,RW_NCNB); //SFR + mmu_setmtt(0x48000000,0x5af00000,0x48000000,RW_NCNB); //SFR + mmu_setmtt(0x5b000000,0x5b000000,0x5b000000,RW_NCNB); //SFR + mmu_setmtt(0x5b100000,0xfff00000,0x5b100000,RW_FAULT);//not used + mmu_setmtt(0x60000000,0x67f00000,0x60000000,RW_NCNB); //SFR + + mmu_setttbase(_MMUTT_STARTADDRESS); + + /* DOMAIN1: no_access, DOMAIN0,2~15=client(AP is checked) */ + mmu_set_domain(0x55555550|DOMAIN1_ATTR|DOMAIN0_ATTR); + + mmu_enable_alignfault(); + + mmu_enable(); + + /* ICache enable */ + mmu_enable_icache(); + /* DCache should be turned on after mmu is turned on. */ + mmu_enable_dcache(); +} + diff --git a/libcpu/arm/s3c24x0/rtc.c b/libcpu/arm/s3c24x0/rtc.c index 5d1193586f..0f05acd687 100644 --- a/libcpu/arm/s3c24x0/rtc.c +++ b/libcpu/arm/s3c24x0/rtc.c @@ -1,189 +1,189 @@ -/*
- * File : rtc.c
- * This file is part of RT-Thread RTOS
- * COPYRIGHT (C) 2006, RT-Thread Development Team
- *
- * The license and distribution terms for this file may be
- * found in the file LICENSE in this distribution or at
- * http://openlab.rt-thread.com/license/LICENSE
- *
- * Change Logs:
- * Date Author Notes
- * 2009-04-26 yi.qiu first version
- * 2010-03-18 Gary Lee add functions such as GregorianDay
- * and rtc_time_to_tm
- * 2009-03-20 yi.qiu clean up
- */
-
-#include <rtthread.h>
-#include <time.h>
-#include <s3c24x0.h>
-
-// #define RTC_DEBUG
-
-#define RTC_ENABLE RTCCON |= 0x01; /*RTC read and write enable */
-#define RTC_DISABLE RTCCON &= ~0x01; /* RTC read and write disable */
-#define BCD2BIN(n) (((((n) >> 4) & 0x0F) * 10) + ((n) & 0x0F))
-#define BIN2BCD(n) ((((n) / 10) << 4) | ((n) % 10))
-
-/**
- * This function get rtc time
- */
-void rt_hw_rtc_get(struct tm *ti)
-{
- rt_uint8_t sec, min, hour, mday, wday, mon, year;
-
- /* enable access to RTC registers */
- RTCCON |= RTC_ENABLE;
-
- /* read RTC registers */
- do
- {
- sec = BCDSEC;
- min = BCDMIN;
- hour = BCDHOUR;
- mday = BCDDATE;
- wday = BCDDAY;
- mon = BCDMON;
- year = BCDYEAR;
- } while (sec != BCDSEC);
-
-#ifdef RTC_DEBUG
- rt_kprintf("sec:%x min:%x hour:%x mday:%x wday:%x mon:%x year:%x\n",
- sec, min, hour, mday, wday, mon, year);
-#endif
-
- /* disable access to RTC registers */
- RTC_DISABLE
-
- ti->tm_sec = BCD2BIN(sec & 0x7F);
- ti->tm_min = BCD2BIN(min & 0x7F);
- ti->tm_hour = BCD2BIN(hour & 0x3F);
- ti->tm_mday = BCD2BIN(mday & 0x3F);
- ti->tm_mon = BCD2BIN(mon & 0x1F);
- ti->tm_year = BCD2BIN(year);
- ti->tm_wday = BCD2BIN(wday & 0x07);
- ti->tm_yday = 0;
- ti->tm_isdst = 0;
-}
-
-/**
- * This function set rtc time
- */
-void rt_hw_rtc_set(struct tm *ti)
-{
- rt_uint8_t sec, min, hour, mday, wday, mon, year;
-
- year = BIN2BCD(ti->tm_year);
- mon = BIN2BCD(ti->tm_mon);
- wday = BIN2BCD(ti->tm_wday);
- mday = BIN2BCD(ti->tm_mday);
- hour = BIN2BCD(ti->tm_hour);
- min = BIN2BCD(ti->tm_min);
- sec = BIN2BCD(ti->tm_sec);
-
- /* enable access to RTC registers */
- RTC_ENABLE
-
- do{
- /* write RTC registers */
- BCDSEC = sec;
- BCDMIN = min;
- BCDHOUR = hour;
- BCDDATE = mday;
- BCDDAY = wday;
- BCDMON = mon;
- BCDYEAR = year;
- }while (sec != BCDSEC);
-
- /* disable access to RTC registers */
- RTC_DISABLE
-}
-
-/**
- * This function reset rtc
- */
-void rt_hw_rtc_reset (void)
-{
- RTCCON = (RTCCON & ~0x06) | 0x08;
- RTCCON &= ~(0x08|0x01);
-}
-
-static struct rt_device rtc;
-static rt_err_t rtc_open(rt_device_t dev, rt_uint16_t oflag)
-{
- RTC_ENABLE
- return RT_EOK;
-}
-
-static rt_err_t rtc_close(rt_device_t dev)
-{
- RTC_DISABLE
- return RT_EOK;
-}
-
-static rt_size_t rtc_read(rt_device_t dev, rt_off_t pos, void* buffer, rt_size_t size)
-{
- return RT_EOK;
-}
-
-static rt_err_t rtc_control(rt_device_t dev, rt_uint8_t cmd, void *args)
-{
- struct tm tm, *tm_ptr;
- time_t *time;
- RT_ASSERT(dev != RT_NULL);
-
- time = (time_t *)args;
- switch (cmd)
- {
- case RT_DEVICE_CTRL_RTC_GET_TIME:
- /* read device */
- rt_hw_rtc_get(&tm);
- *((rt_time_t *)args) = mktime(&tm);
- break;
-
- case RT_DEVICE_CTRL_RTC_SET_TIME:
- tm_ptr = localtime(time);
- /* write device */
- rt_hw_rtc_set(tm_ptr);
- break;
- }
-
- return RT_EOK;
-}
-
-void rt_hw_rtc_init(void)
-{
- rtc.type = RT_Device_Class_RTC;
-
- /* register rtc device */
- rtc.init = RT_NULL;
- rtc.open = rtc_open;
- rtc.close = rtc_close;
- rtc.read = rtc_read;
- rtc.write = RT_NULL;
- rtc.control = rtc_control;
-
- /* no private */
- rtc.user_data = RT_NULL;
-
- rt_device_register(&rtc, "rtc", RT_DEVICE_FLAG_RDWR);
-}
-
-#ifdef RT_USING_FINSH
-#include <finsh.h>
-void list_date()
-{
- time_t time;
- rt_device_t device;
-
- device = rt_device_find("rtc");
- if (device != RT_NULL)
- {
- rt_device_control(device, RT_DEVICE_CTRL_RTC_GET_TIME, &time);
-
- rt_kprintf("%d, %s\n", time, ctime(&time));
- }
-}
-FINSH_FUNCTION_EXPORT(list_date, list date);
-#endif
+/* + * File : rtc.c + * This file is part of RT-Thread RTOS + * COPYRIGHT (C) 2006, RT-Thread Development Team + * + * The license and distribution terms for this file may be + * found in the file LICENSE in this distribution or at + * http://openlab.rt-thread.com/license/LICENSE + * + * Change Logs: + * Date Author Notes + * 2009-04-26 yi.qiu first version + * 2010-03-18 Gary Lee add functions such as GregorianDay + * and rtc_time_to_tm + * 2009-03-20 yi.qiu clean up + */ + +#include <rtthread.h> +#include <time.h> +#include <s3c24x0.h> + +// #define RTC_DEBUG + +#define RTC_ENABLE RTCCON |= 0x01; /*RTC read and write enable */ +#define RTC_DISABLE RTCCON &= ~0x01; /* RTC read and write disable */ +#define BCD2BIN(n) (((((n) >> 4) & 0x0F) * 10) + ((n) & 0x0F)) +#define BIN2BCD(n) ((((n) / 10) << 4) | ((n) % 10)) + +/** + * This function get rtc time + */ +void rt_hw_rtc_get(struct tm *ti) +{ + rt_uint8_t sec, min, hour, mday, wday, mon, year; + + /* enable access to RTC registers */ + RTCCON |= RTC_ENABLE; + + /* read RTC registers */ + do + { + sec = BCDSEC; + min = BCDMIN; + hour = BCDHOUR; + mday = BCDDATE; + wday = BCDDAY; + mon = BCDMON; + year = BCDYEAR; + } while (sec != BCDSEC); + +#ifdef RTC_DEBUG + rt_kprintf("sec:%x min:%x hour:%x mday:%x wday:%x mon:%x year:%x\n", + sec, min, hour, mday, wday, mon, year); +#endif + + /* disable access to RTC registers */ + RTC_DISABLE + + ti->tm_sec = BCD2BIN(sec & 0x7F); + ti->tm_min = BCD2BIN(min & 0x7F); + ti->tm_hour = BCD2BIN(hour & 0x3F); + ti->tm_mday = BCD2BIN(mday & 0x3F); + ti->tm_mon = BCD2BIN(mon & 0x1F); + ti->tm_year = BCD2BIN(year); + ti->tm_wday = BCD2BIN(wday & 0x07); + ti->tm_yday = 0; + ti->tm_isdst = 0; +} + +/** + * This function set rtc time + */ +void rt_hw_rtc_set(struct tm *ti) +{ + rt_uint8_t sec, min, hour, mday, wday, mon, year; + + year = BIN2BCD(ti->tm_year); + mon = BIN2BCD(ti->tm_mon); + wday = BIN2BCD(ti->tm_wday); + mday = BIN2BCD(ti->tm_mday); + hour = BIN2BCD(ti->tm_hour); + min = BIN2BCD(ti->tm_min); + sec = BIN2BCD(ti->tm_sec); + + /* enable access to RTC registers */ + RTC_ENABLE + + do{ + /* write RTC registers */ + BCDSEC = sec; + BCDMIN = min; + BCDHOUR = hour; + BCDDATE = mday; + BCDDAY = wday; + BCDMON = mon; + BCDYEAR = year; + }while (sec != BCDSEC); + + /* disable access to RTC registers */ + RTC_DISABLE +} + +/** + * This function reset rtc + */ +void rt_hw_rtc_reset (void) +{ + RTCCON = (RTCCON & ~0x06) | 0x08; + RTCCON &= ~(0x08|0x01); +} + +static struct rt_device rtc; +static rt_err_t rtc_open(rt_device_t dev, rt_uint16_t oflag) +{ + RTC_ENABLE + return RT_EOK; +} + +static rt_err_t rtc_close(rt_device_t dev) +{ + RTC_DISABLE + return RT_EOK; +} + +static rt_size_t rtc_read(rt_device_t dev, rt_off_t pos, void* buffer, rt_size_t size) +{ + return RT_EOK; +} + +static rt_err_t rtc_control(rt_device_t dev, rt_uint8_t cmd, void *args) +{ + struct tm tm, *tm_ptr; + time_t *time; + RT_ASSERT(dev != RT_NULL); + + time = (time_t *)args; + switch (cmd) + { + case RT_DEVICE_CTRL_RTC_GET_TIME: + /* read device */ + rt_hw_rtc_get(&tm); + *((rt_time_t *)args) = mktime(&tm); + break; + + case RT_DEVICE_CTRL_RTC_SET_TIME: + tm_ptr = localtime(time); + /* write device */ + rt_hw_rtc_set(tm_ptr); + break; + } + + return RT_EOK; +} + +void rt_hw_rtc_init(void) +{ + rtc.type = RT_Device_Class_RTC; + + /* register rtc device */ + rtc.init = RT_NULL; + rtc.open = rtc_open; + rtc.close = rtc_close; + rtc.read = rtc_read; + rtc.write = RT_NULL; + rtc.control = rtc_control; + + /* no private */ + rtc.user_data = RT_NULL; + + rt_device_register(&rtc, "rtc", RT_DEVICE_FLAG_RDWR); +} + +#ifdef RT_USING_FINSH +#include <finsh.h> +void list_date() +{ + time_t time; + rt_device_t device; + + device = rt_device_find("rtc"); + if (device != RT_NULL) + { + rt_device_control(device, RT_DEVICE_CTRL_RTC_GET_TIME, &time); + + rt_kprintf("%d, %s\n", time, ctime(&time)); + } +} +FINSH_FUNCTION_EXPORT(list_date, list date); +#endif diff --git a/libcpu/arm/s3c24x0/rtc.h b/libcpu/arm/s3c24x0/rtc.h index fa4ea397ea..f7073e259b 100644 --- a/libcpu/arm/s3c24x0/rtc.h +++ b/libcpu/arm/s3c24x0/rtc.h @@ -1,21 +1,21 @@ -/*
- * File : rtc.h
- * This file is part of RT-Thread RTOS
- * COPYRIGHT (C) 2009, RT-Thread Development Team
- *
- * The license and distribution terms for this file may be
- * found in the file LICENSE in this distribution or at
- * http://www.rt-thread.org/license/LICENSE
- *
- * Change Logs:
- * Date Author Notes
- * 2010-03-20 yi.qiu the first version
- */
-
-#ifndef __RTC_H__
-#define __RTC_H__
-
-void rt_hw_rtc_init(void);
-
-#endif
-
+/* + * File : rtc.h + * This file is part of RT-Thread RTOS + * COPYRIGHT (C) 2009, RT-Thread Development Team + * + * The license and distribution terms for this file may be + * found in the file LICENSE in this distribution or at + * http://www.rt-thread.org/license/LICENSE + * + * Change Logs: + * Date Author Notes + * 2010-03-20 yi.qiu the first version + */ + +#ifndef __RTC_H__ +#define __RTC_H__ + +void rt_hw_rtc_init(void); + +#endif + diff --git a/libcpu/arm/s3c24x0/s3c24x0.h b/libcpu/arm/s3c24x0/s3c24x0.h index c5de9ee396..8308148c3b 100644 --- a/libcpu/arm/s3c24x0/s3c24x0.h +++ b/libcpu/arm/s3c24x0/s3c24x0.h @@ -1,611 +1,611 @@ -/*
- * File : s3c24x0.h
- * This file is part of RT-Thread RTOS
- * COPYRIGHT (C) 2006, RT-Thread Develop Team
- *
- * The license and distribution terms for this file may be
- * found in the file LICENSE in this distribution or at
- * http://openlab.rt-thread.com/license/LICENSE
- *
- * Change Logs:
- * Date Author Notes
- * 2009-12-11 Bernard first version
- */
-
-#ifndef __S3C24X0_H__
-#define __S3C24X0_H__
-
-#ifdef __cplusplus
-extern "C" {
-#endif
-
-#include <rtthread.h>
-
-/**
- * @addtogroup S3C24X0
- */
-/*@{*/
-
-// Memory control
-#define BWSCON (*(volatile unsigned *)0x48000000) //Bus width & wait status
-#define BANKCON0 (*(volatile unsigned *)0x48000004) //Boot ROM control
-#define BANKCON1 (*(volatile unsigned *)0x48000008) //BANK1 control
-#define BANKCON2 (*(volatile unsigned *)0x4800000c) //BANK2 cControl
-#define BANKCON3 (*(volatile unsigned *)0x48000010) //BANK3 control
-#define BANKCON4 (*(volatile unsigned *)0x48000014) //BANK4 control
-#define BANKCON5 (*(volatile unsigned *)0x48000018) //BANK5 control
-#define BANKCON6 (*(volatile unsigned *)0x4800001c) //BANK6 control
-#define BANKCON7 (*(volatile unsigned *)0x48000020) //BANK7 control
-#define REFRESH (*(volatile unsigned *)0x48000024) //DRAM/SDRAM efresh
-#define BANKSIZE (*(volatile unsigned *)0x48000028) //Flexible Bank Size
-#define MRSRB6 (*(volatile unsigned *)0x4800002c) //Mode egister set for SDRAM
-#define MRSRB7 (*(volatile unsigned *)0x48000030) //Mode egister set for SDRAM
-
-
-// USB Host
-
-
-// INTERRUPT
-#define SRCPND (*(volatile unsigned *)0x4a000000) //Interrupt request status
-#define INTMOD (*(volatile unsigned *)0x4a000004) //Interrupt mode control
-#define INTMSK (*(volatile unsigned *)0x4a000008) //Interrupt mask control
-#define PRIORITY (*(volatile unsigned *)0x4a00000c) //IRQ priority control
-#define INTPND (*(volatile unsigned *)0x4a000010) //Interrupt request status
-#define INTOFFSET (*(volatile unsigned *)0x4a000014) //Interruot request source offset
-#define SUBSRCPND (*(volatile unsigned *)0x4a000018) //Sub source pending
-#define INTSUBMSK (*(volatile unsigned *)0x4a00001c) //Interrupt sub mask
-
-
-// DMA
-#define DISRC0 (*(volatile unsigned *)0x4b000000) //DMA 0 Initial source
-#define DISRCC0 (*(volatile unsigned *)0x4b000004) //DMA 0 Initial source control
-#define DIDST0 (*(volatile unsigned *)0x4b000008) //DMA 0 Initial Destination
-#define DIDSTC0 (*(volatile unsigned *)0x4b00000c) //DMA 0 Initial Destination control
-#define DCON0 (*(volatile unsigned *)0x4b000010) //DMA 0 Control
-#define DSTAT0 (*(volatile unsigned *)0x4b000014) //DMA 0 Status
-#define DCSRC0 (*(volatile unsigned *)0x4b000018) //DMA 0 Current source
-#define DCDST0 (*(volatile unsigned *)0x4b00001c) //DMA 0 Current destination
-#define DMASKTRIG0 (*(volatile unsigned *)0x4b000020) //DMA 0 Mask trigger
-
-#define DISRC1 (*(volatile unsigned *)0x4b000040) //DMA 1 Initial source
-#define DISRCC1 (*(volatile unsigned *)0x4b000044) //DMA 1 Initial source control
-#define DIDST1 (*(volatile unsigned *)0x4b000048) //DMA 1 Initial Destination
-#define DIDSTC1 (*(volatile unsigned *)0x4b00004c) //DMA 1 Initial Destination control
-#define DCON1 (*(volatile unsigned *)0x4b000050) //DMA 1 Control
-#define DSTAT1 (*(volatile unsigned *)0x4b000054) //DMA 1 Status
-#define DCSRC1 (*(volatile unsigned *)0x4b000058) //DMA 1 Current source
-#define DCDST1 (*(volatile unsigned *)0x4b00005c) //DMA 1 Current destination
-#define DMASKTRIG1 (*(volatile unsigned *)0x4b000060) //DMA 1 Mask trigger
-
-#define DISRC2 (*(volatile unsigned *)0x4b000080) //DMA 2 Initial source
-#define DISRCC2 (*(volatile unsigned *)0x4b000084) //DMA 2 Initial source control
-#define DIDST2 (*(volatile unsigned *)0x4b000088) //DMA 2 Initial Destination
-#define DIDSTC2 (*(volatile unsigned *)0x4b00008c) //DMA 2 Initial Destination control
-#define DCON2 (*(volatile unsigned *)0x4b000090) //DMA 2 Control
-#define DSTAT2 (*(volatile unsigned *)0x4b000094) //DMA 2 Status
-#define DCSRC2 (*(volatile unsigned *)0x4b000098) //DMA 2 Current source
-#define DCDST2 (*(volatile unsigned *)0x4b00009c) //DMA 2 Current destination
-#define DMASKTRIG2 (*(volatile unsigned *)0x4b0000a0) //DMA 2 Mask trigger
-
-#define DISRC3 (*(volatile unsigned *)0x4b0000c0) //DMA 3 Initial source
-#define DISRCC3 (*(volatile unsigned *)0x4b0000c4) //DMA 3 Initial source control
-#define DIDST3 (*(volatile unsigned *)0x4b0000c8) //DMA 3 Initial Destination
-#define DIDSTC3 (*(volatile unsigned *)0x4b0000cc) //DMA 3 Initial Destination control
-#define DCON3 (*(volatile unsigned *)0x4b0000d0) //DMA 3 Control
-#define DSTAT3 (*(volatile unsigned *)0x4b0000d4) //DMA 3 Status
-#define DCSRC3 (*(volatile unsigned *)0x4b0000d8) //DMA 3 Current source
-#define DCDST3 (*(volatile unsigned *)0x4b0000dc) //DMA 3 Current destination
-#define DMASKTRIG3 (*(volatile unsigned *)0x4b0000e0) //DMA 3 Mask trigger
-
-
-// CLOCK & POWER MANAGEMENT
-#define LOCKTIME (*(volatile unsigned *)0x4c000000) //PLL lock time counter
-#define MPLLCON (*(volatile unsigned *)0x4c000004) //MPLL Control
-#define UPLLCON (*(volatile unsigned *)0x4c000008) //UPLL Control
-#define CLKCON (*(volatile unsigned *)0x4c00000c) //Clock generator control
-#define CLKSLOW (*(volatile unsigned *)0x4c000010) //Slow clock control
-#define CLKDIVN (*(volatile unsigned *)0x4c000014) //Clock divider control
-#define CAMDIVN (*(volatile unsigned *)0x4c000018) //USB, CAM Clock divider control
-
-
-// LCD CONTROLLER
-#define LCDCON1 (*(volatile unsigned *)0x4d000000) //LCD control 1
-#define LCDCON2 (*(volatile unsigned *)0x4d000004) //LCD control 2
-#define LCDCON3 (*(volatile unsigned *)0x4d000008) //LCD control 3
-#define LCDCON4 (*(volatile unsigned *)0x4d00000c) //LCD control 4
-#define LCDCON5 (*(volatile unsigned *)0x4d000010) //LCD control 5
-#define LCDSADDR1 (*(volatile unsigned *)0x4d000014) //STN/TFT Frame buffer start address 1
-#define LCDSADDR2 (*(volatile unsigned *)0x4d000018) //STN/TFT Frame buffer start address 2
-#define LCDSADDR3 (*(volatile unsigned *)0x4d00001c) //STN/TFT Virtual screen address set
-#define REDLUT (*(volatile unsigned *)0x4d000020) //STN Red lookup table
-#define GREENLUT (*(volatile unsigned *)0x4d000024) //STN Green lookup table
-#define BLUELUT (*(volatile unsigned *)0x4d000028) //STN Blue lookup table
-#define DITHMODE (*(volatile unsigned *)0x4d00004c) //STN Dithering mode
-#define TPAL (*(volatile unsigned *)0x4d000050) //TFT Temporary palette
-#define LCDINTPND (*(volatile unsigned *)0x4d000054) //LCD Interrupt pending
-#define LCDSRCPND (*(volatile unsigned *)0x4d000058) //LCD Interrupt source
-#define LCDINTMSK (*(volatile unsigned *)0x4d00005c) //LCD Interrupt mask
-#define LPCSEL (*(volatile unsigned *)0x4d000060) //LPC3600 Control
-#define PALETTE 0x4d000400 //Palette start address
-
-
-// NAND flash
-#define NFCONF (*(volatile unsigned *)0x4e000000) //NAND Flash configuration
-#define NFCMD (*(volatile unsigned *)0x4e000004) //NADD Flash command
-#define NFADDR (*(volatile unsigned *)0x4e000008) //NAND Flash address
-#define NFDATA (*(volatile unsigned *)0x4e00000c) //NAND Flash data
-#define NFSTAT (*(volatile unsigned *)0x4e000010) //NAND Flash operation status
-#define NFECC (*(volatile unsigned *)0x4e000014) //NAND Flash ECC
-#define NFECC0 (*(volatile unsigned *)0x4e000014)
-#define NFECC1 (*(volatile unsigned *)0x4e000015)
-#define NFECC2 (*(volatile unsigned *)0x4e000016)
-
-// UART
-#define U0BASE (*(volatile unsigned *)0x50000000) //UART 0 Line control
-#define ULCON0 (*(volatile unsigned *)0x50000000) //UART 0 Line control
-#define UCON0 (*(volatile unsigned *)0x50000004) //UART 0 Control
-#define UFCON0 (*(volatile unsigned *)0x50000008) //UART 0 FIFO control
-#define UMCON0 (*(volatile unsigned *)0x5000000c) //UART 0 Modem control
-#define USTAT0 (*(volatile unsigned *)0x50000010) //UART 0 Tx/Rx status
-#define URXB0 (*(volatile unsigned *)0x50000014) //UART 0 Rx error status
-#define UFSTAT0 (*(volatile unsigned *)0x50000018) //UART 0 FIFO status
-#define UMSTAT0 (*(volatile unsigned *)0x5000001c) //UART 0 Modem status
-#define UBRD0 (*(volatile unsigned *)0x50000028) //UART 0 Baud ate divisor
-
-#define U1BASE (*(volatile unsigned *)0x50004000) //UART 1 Line control
-#define ULCON1 (*(volatile unsigned *)0x50004000) //UART 1 Line control
-#define UCON1 (*(volatile unsigned *)0x50004004) //UART 1 Control
-#define UFCON1 (*(volatile unsigned *)0x50004008) //UART 1 FIFO control
-#define UMCON1 (*(volatile unsigned *)0x5000400c) //UART 1 Modem control
-#define USTAT1 (*(volatile unsigned *)0x50004010) //UART 1 Tx/Rx status
-#define URXB1 (*(volatile unsigned *)0x50004014) //UART 1 Rx error status
-#define UFSTAT1 (*(volatile unsigned *)0x50004018) //UART 1 FIFO status
-#define UMSTAT1 (*(volatile unsigned *)0x5000401c) //UART 1 Modem status
-#define UBRD1 (*(volatile unsigned *)0x50004028) //UART 1 Baud ate divisor
-
-#define U2BASE *(volatile unsigned *)0x50008000 //UART 2 Line control
-#define ULCON2 (*(volatile unsigned *)0x50008000) //UART 2 Line control
-#define UCON2 (*(volatile unsigned *)0x50008004) //UART 2 Control
-#define UFCON2 (*(volatile unsigned *)0x50008008) //UART 2 FIFO control
-#define UMCON2 (*(volatile unsigned *)0x5000800c) //UART 2 Modem control
-#define USTAT2 (*(volatile unsigned *)0x50008010) //UART 2 Tx/Rx status
-#define URXB2 (*(volatile unsigned *)0x50008014) //UART 2 Rx error status
-#define UFSTAT2 (*(volatile unsigned *)0x50008018) //UART 2 FIFO status
-#define UMSTAT2 (*(volatile unsigned *)0x5000801c) //UART 2 Modem status
-#define UBRD2 (*(volatile unsigned *)0x50008028) //UART 2 Baud ate divisor
-
-#ifdef __BIG_ENDIAN
-#define UTXH0 (*(volatile unsigned char *)0x50000023) //UART 0 Transmission Hold
-#define URXH0 (*(volatile unsigned char *)0x50000027) //UART 0 Receive buffer
-#define UTXH1 (*(volatile unsigned char *)0x50004023) //UART 1 Transmission Hold
-#define URXH1 (*(volatile unsigned char *)0x50004027) //UART 1 Receive buffer
-#define UTXH2 (*(volatile unsigned char *)0x50008023) //UART 2 Transmission Hold
-#define URXH2 (*(volatile unsigned char *)0x50008027) //UART 2 Receive buffer
-
-#define WrUTXH0(ch) (*(volatile unsigned char *)0x50000023)=(unsigned char)(ch)
-#define RdURXH0() (*(volatile unsigned char *)0x50000027)
-#define WrUTXH1(ch) (*(volatile unsigned char *)0x50004023)=(unsigned char)(ch)
-#define RdURXH1() (*(volatile unsigned char *)0x50004027)
-#define WrUTXH2(ch) (*(volatile unsigned char *)0x50008023)=(unsigned char)(ch)
-#define RdURXH2() (*(volatile unsigned char *)0x50008027)
-
-#else //Little Endian
-#define UTXH0 (*(volatile unsigned char *)0x50000020) //UART 0 Transmission Hold
-#define URXH0 (*(volatile unsigned char *)0x50000024) //UART 0 Receive buffer
-#define UTXH1 (*(volatile unsigned char *)0x50004020) //UART 1 Transmission Hold
-#define URXH1 (*(volatile unsigned char *)0x50004024) //UART 1 Receive buffer
-#define UTXH2 (*(volatile unsigned char *)0x50008020) //UART 2 Transmission Hold
-#define URXH2 (*(volatile unsigned char *)0x50008024) //UART 2 Receive buffer
-
-#define WrUTXH0(ch) (*(volatile unsigned char *)0x50000020)=(unsigned char)(ch)
-#define RdURXH0() (*(volatile unsigned char *)0x50000024)
-#define WrUTXH1(ch) (*(volatile unsigned char *)0x50004020)=(unsigned char)(ch)
-#define RdURXH1() (*(volatile unsigned char *)0x50004024)
-#define WrUTXH2(ch) (*(volatile unsigned char *)0x50008020)=(unsigned char)(ch)
-#define RdURXH2() (*(volatile unsigned char *)0x50008024)
-
-#endif
-
-
-// PWM TIMER
-#define TCFG0 (*(volatile unsigned *)0x51000000) //Timer 0 configuration
-#define TCFG1 (*(volatile unsigned *)0x51000004) //Timer 1 configuration
-#define TCON (*(volatile unsigned *)0x51000008) //Timer control
-#define TCNTB0 (*(volatile unsigned *)0x5100000c) //Timer count buffer 0
-#define TCMPB0 (*(volatile unsigned *)0x51000010) //Timer compare buffer 0
-#define TCNTO0 (*(volatile unsigned *)0x51000014) //Timer count observation 0
-#define TCNTB1 (*(volatile unsigned *)0x51000018) //Timer count buffer 1
-#define TCMPB1 (*(volatile unsigned *)0x5100001c) //Timer compare buffer 1
-#define TCNTO1 (*(volatile unsigned *)0x51000020) //Timer count observation 1
-#define TCNTB2 (*(volatile unsigned *)0x51000024) //Timer count buffer 2
-#define TCMPB2 (*(volatile unsigned *)0x51000028) //Timer compare buffer 2
-#define TCNTO2 (*(volatile unsigned *)0x5100002c) //Timer count observation 2
-#define TCNTB3 (*(volatile unsigned *)0x51000030) //Timer count buffer 3
-#define TCMPB3 (*(volatile unsigned *)0x51000034) //Timer compare buffer 3
-#define TCNTO3 (*(volatile unsigned *)0x51000038) //Timer count observation 3
-#define TCNTB4 (*(volatile unsigned *)0x5100003c) //Timer count buffer 4
-#define TCNTO4 (*(volatile unsigned *)0x51000040) //Timer count observation 4
-
-// Added for 2440
-#define FLTOUT (*(volatile unsigned *)0x560000c0) // Filter output(Read only)
-#define DSC0 (*(volatile unsigned *)0x560000c4) // Strength control register 0
-#define DSC1 (*(volatile unsigned *)0x560000c8) // Strength control register 1
-#define MSLCON (*(volatile unsigned *)0x560000cc) // Memory sleep control register
-
-
-// USB DEVICE
-#ifdef __BIG_ENDIAN
-#define FUNC_ADDR_REG (*(volatile unsigned char *)0x52000143) //Function address
-#define PWR_REG (*(volatile unsigned char *)0x52000147) //Power management
-#define EP_INT_REG (*(volatile unsigned char *)0x5200014b) //EP Interrupt pending and clear
-#define USB_INT_REG (*(volatile unsigned char *)0x5200015b) //USB Interrupt pending and clear
-#define EP_INT_EN_REG (*(volatile unsigned char *)0x5200015f) //Interrupt enable
-#define USB_INT_EN_REG (*(volatile unsigned char *)0x5200016f)
-#define FRAME_NUM1_REG (*(volatile unsigned char *)0x52000173) //Frame number lower byte
-#define FRAME_NUM2_REG (*(volatile unsigned char *)0x52000177) //Frame number higher byte
-#define INDEX_REG (*(volatile unsigned char *)0x5200017b) //Register index
-#define MAXP_REG (*(volatile unsigned char *)0x52000183) //Endpoint max packet
-#define EP0_CSR (*(volatile unsigned char *)0x52000187) //Endpoint 0 status
-#define IN_CSR1_REG (*(volatile unsigned char *)0x52000187) //In endpoint control status
-#define IN_CSR2_REG (*(volatile unsigned char *)0x5200018b)
-#define OUT_CSR1_REG (*(volatile unsigned char *)0x52000193) //Out endpoint control status
-#define OUT_CSR2_REG (*(volatile unsigned char *)0x52000197)
-#define OUT_FIFO_CNT1_REG (*(volatile unsigned char *)0x5200019b) //Endpoint out write count
-#define OUT_FIFO_CNT2_REG (*(volatile unsigned char *)0x5200019f)
-#define EP0_FIFO (*(volatile unsigned char *)0x520001c3) //Endpoint 0 FIFO
-#define EP1_FIFO (*(volatile unsigned char *)0x520001c7) //Endpoint 1 FIFO
-#define EP2_FIFO (*(volatile unsigned char *)0x520001cb) //Endpoint 2 FIFO
-#define EP3_FIFO (*(volatile unsigned char *)0x520001cf) //Endpoint 3 FIFO
-#define EP4_FIFO (*(volatile unsigned char *)0x520001d3) //Endpoint 4 FIFO
-#define EP1_DMA_CON (*(volatile unsigned char *)0x52000203) //EP1 DMA interface control
-#define EP1_DMA_UNIT (*(volatile unsigned char *)0x52000207) //EP1 DMA Tx unit counter
-#define EP1_DMA_FIFO (*(volatile unsigned char *)0x5200020b) //EP1 DMA Tx FIFO counter
-#define EP1_DMA_TTC_L (*(volatile unsigned char *)0x5200020f) //EP1 DMA total Tx counter
-#define EP1_DMA_TTC_M (*(volatile unsigned char *)0x52000213)
-#define EP1_DMA_TTC_H (*(volatile unsigned char *)0x52000217)
-#define EP2_DMA_CON (*(volatile unsigned char *)0x5200021b) //EP2 DMA interface control
-#define EP2_DMA_UNIT (*(volatile unsigned char *)0x5200021f) //EP2 DMA Tx unit counter
-#define EP2_DMA_FIFO (*(volatile unsigned char *)0x52000223) //EP2 DMA Tx FIFO counter
-#define EP2_DMA_TTC_L (*(volatile unsigned char *)0x52000227) //EP2 DMA total Tx counter
-#define EP2_DMA_TTC_M (*(volatile unsigned char *)0x5200022b)
-#define EP2_DMA_TTC_H (*(volatile unsigned char *)0x5200022f)
-#define EP3_DMA_CON (*(volatile unsigned char *)0x52000243) //EP3 DMA interface control
-#define EP3_DMA_UNIT (*(volatile unsigned char *)0x52000247) //EP3 DMA Tx unit counter
-#define EP3_DMA_FIFO (*(volatile unsigned char *)0x5200024b) //EP3 DMA Tx FIFO counter
-#define EP3_DMA_TTC_L (*(volatile unsigned char *)0x5200024f) //EP3 DMA total Tx counter
-#define EP3_DMA_TTC_M (*(volatile unsigned char *)0x52000253)
-#define EP3_DMA_TTC_H (*(volatile unsigned char *)0x52000257)
-#define EP4_DMA_CON (*(volatile unsigned char *)0x5200025b) //EP4 DMA interface control
-#define EP4_DMA_UNIT (*(volatile unsigned char *)0x5200025f) //EP4 DMA Tx unit counter
-#define EP4_DMA_FIFO (*(volatile unsigned char *)0x52000263) //EP4 DMA Tx FIFO counter
-#define EP4_DMA_TTC_L (*(volatile unsigned char *)0x52000267) //EP4 DMA total Tx counter
-#define EP4_DMA_TTC_M (*(volatile unsigned char *)0x5200026b)
-#define EP4_DMA_TTC_H (*(volatile unsigned char *)0x5200026f)
-
-#else // Little Endian
-#define FUNC_ADDR_REG (*(volatile unsigned char *)0x52000140) //Function address
-#define PWR_REG (*(volatile unsigned char *)0x52000144) //Power management
-#define EP_INT_REG (*(volatile unsigned char *)0x52000148) //EP Interrupt pending and clear
-#define USB_INT_REG (*(volatile unsigned char *)0x52000158) //USB Interrupt pending and clear
-#define EP_INT_EN_REG (*(volatile unsigned char *)0x5200015c) //Interrupt enable
-#define USB_INT_EN_REG (*(volatile unsigned char *)0x5200016c)
-#define FRAME_NUM1_REG (*(volatile unsigned char *)0x52000170) //Frame number lower byte
-#define FRAME_NUM2_REG (*(volatile unsigned char *)0x52000174) //Frame number higher byte
-#define INDEX_REG (*(volatile unsigned char *)0x52000178) //Register index
-#define MAXP_REG (*(volatile unsigned char *)0x52000180) //Endpoint max packet
-#define EP0_CSR (*(volatile unsigned char *)0x52000184) //Endpoint 0 status
-#define IN_CSR1_REG (*(volatile unsigned char *)0x52000184) //In endpoint control status
-#define IN_CSR2_REG (*(volatile unsigned char *)0x52000188)
-#define OUT_CSR1_REG (*(volatile unsigned char *)0x52000190) //Out endpoint control status
-#define OUT_CSR2_REG (*(volatile unsigned char *)0x52000194)
-#define OUT_FIFO_CNT1_REG (*(volatile unsigned char *)0x52000198) //Endpoint out write count
-#define OUT_FIFO_CNT2_REG (*(volatile unsigned char *)0x5200019c)
-#define EP0_FIFO (*(volatile unsigned char *)0x520001c0) //Endpoint 0 FIFO
-#define EP1_FIFO (*(volatile unsigned char *)0x520001c4) //Endpoint 1 FIFO
-#define EP2_FIFO (*(volatile unsigned char *)0x520001c8) //Endpoint 2 FIFO
-#define EP3_FIFO (*(volatile unsigned char *)0x520001cc) //Endpoint 3 FIFO
-#define EP4_FIFO (*(volatile unsigned char *)0x520001d0) //Endpoint 4 FIFO
-#define EP1_DMA_CON (*(volatile unsigned char *)0x52000200) //EP1 DMA interface control
-#define EP1_DMA_UNIT (*(volatile unsigned char *)0x52000204) //EP1 DMA Tx unit counter
-#define EP1_DMA_FIFO (*(volatile unsigned char *)0x52000208) //EP1 DMA Tx FIFO counter
-#define EP1_DMA_TTC_L (*(volatile unsigned char *)0x5200020c) //EP1 DMA total Tx counter
-#define EP1_DMA_TTC_M (*(volatile unsigned char *)0x52000210)
-#define EP1_DMA_TTC_H (*(volatile unsigned char *)0x52000214)
-#define EP2_DMA_CON (*(volatile unsigned char *)0x52000218) //EP2 DMA interface control
-#define EP2_DMA_UNIT (*(volatile unsigned char *)0x5200021c) //EP2 DMA Tx unit counter
-#define EP2_DMA_FIFO (*(volatile unsigned char *)0x52000220) //EP2 DMA Tx FIFO counter
-#define EP2_DMA_TTC_L (*(volatile unsigned char *)0x52000224) //EP2 DMA total Tx counter
-#define EP2_DMA_TTC_M (*(volatile unsigned char *)0x52000228)
-#define EP2_DMA_TTC_H (*(volatile unsigned char *)0x5200022c)
-#define EP3_DMA_CON (*(volatile unsigned char *)0x52000240) //EP3 DMA interface control
-#define EP3_DMA_UNIT (*(volatile unsigned char *)0x52000244) //EP3 DMA Tx unit counter
-#define EP3_DMA_FIFO (*(volatile unsigned char *)0x52000248) //EP3 DMA Tx FIFO counter
-#define EP3_DMA_TTC_L (*(volatile unsigned char *)0x5200024c) //EP3 DMA total Tx counter
-#define EP3_DMA_TTC_M (*(volatile unsigned char *)0x52000250)
-#define EP3_DMA_TTC_H (*(volatile unsigned char *)0x52000254)
-#define EP4_DMA_CON (*(volatile unsigned char *)0x52000258) //EP4 DMA interface control
-#define EP4_DMA_UNIT (*(volatile unsigned char *)0x5200025c) //EP4 DMA Tx unit counter
-#define EP4_DMA_FIFO (*(volatile unsigned char *)0x52000260) //EP4 DMA Tx FIFO counter
-#define EP4_DMA_TTC_L (*(volatile unsigned char *)0x52000264) //EP4 DMA total Tx counter
-#define EP4_DMA_TTC_M (*(volatile unsigned char *)0x52000268)
-#define EP4_DMA_TTC_H (*(volatile unsigned char *)0x5200026c)
-#endif // __BIG_ENDIAN
-
-
-// WATCH DOG TIMER
-#define WTCON (*(volatile unsigned *)0x53000000) //Watch-dog timer mode
-#define WTDAT (*(volatile unsigned *)0x53000004) //Watch-dog timer data
-#define WTCNT (*(volatile unsigned *)0x53000008) //Eatch-dog timer count
-
-
-// IIC
-#define IICCON (*(volatile unsigned *)0x54000000) //IIC control
-#define IICSTAT (*(volatile unsigned *)0x54000004) //IIC status
-#define IICADD (*(volatile unsigned *)0x54000008) //IIC address
-#define IICDS (*(volatile unsigned *)0x5400000c) //IIC data shift
-
-
-// IIS
-#define IISCON (*(volatile unsigned *)0x55000000) //IIS Control
-#define IISMOD (*(volatile unsigned *)0x55000004) //IIS Mode
-#define IISPSR (*(volatile unsigned *)0x55000008) //IIS Prescaler
-#define IISFCON (*(volatile unsigned *)0x5500000c) //IIS FIFO control
-
-#ifdef __BIG_ENDIAN
-#define IISFIFO ((volatile unsigned short *)0x55000012) //IIS FIFO entry
-
-#else //Little Endian
-#define IISFIFO ((volatile unsigned short *)0x55000010) //IIS FIFO entry
-
-#endif
-
-
-// I/O PORT
-#define GPACON (*(volatile unsigned *)0x56000000) //Port A control
-#define GPADAT (*(volatile unsigned *)0x56000004) //Port A data
-
-#define GPBCON (*(volatile unsigned *)0x56000010) //Port B control
-#define GPBDAT (*(volatile unsigned *)0x56000014) //Port B data
-#define GPBUP (*(volatile unsigned *)0x56000018) //Pull-up control B
-
-#define GPCCON (*(volatile unsigned *)0x56000020) //Port C control
-#define GPCDAT (*(volatile unsigned *)0x56000024) //Port C data
-#define GPCUP (*(volatile unsigned *)0x56000028) //Pull-up control C
-
-#define GPDCON (*(volatile unsigned *)0x56000030) //Port D control
-#define GPDDAT (*(volatile unsigned *)0x56000034) //Port D data
-#define GPDUP (*(volatile unsigned *)0x56000038) //Pull-up control D
-
-#define GPECON (*(volatile unsigned *)0x56000040) //Port E control
-#define GPEDAT (*(volatile unsigned *)0x56000044) //Port E data
-#define GPEUP (*(volatile unsigned *)0x56000048) //Pull-up control E
-
-#define GPFCON (*(volatile unsigned *)0x56000050) //Port F control
-#define GPFDAT (*(volatile unsigned *)0x56000054) //Port F data
-#define GPFUP (*(volatile unsigned *)0x56000058) //Pull-up control F
-
-#define GPGCON (*(volatile unsigned *)0x56000060) //Port G control
-#define GPGDAT (*(volatile unsigned *)0x56000064) //Port G data
-#define GPGUP (*(volatile unsigned *)0x56000068) //Pull-up control G
-
-#define GPHCON (*(volatile unsigned *)0x56000070) //Port H control
-#define GPHDAT (*(volatile unsigned *)0x56000074) //Port H data
-#define GPHUP (*(volatile unsigned *)0x56000078) //Pull-up control H
-
-#define GPJCON (*(volatile unsigned *)0x560000d0) //Port J control
-#define GPJDAT (*(volatile unsigned *)0x560000d4) //Port J data
-#define GPJUP (*(volatile unsigned *)0x560000d8) //Pull-up control J
-
-#define MISCCR (*(volatile unsigned *)0x56000080) //Miscellaneous control
-#define DCLKCON (*(volatile unsigned *)0x56000084) //DCLK0/1 control
-#define EXTINT0 (*(volatile unsigned *)0x56000088) //External interrupt control egister 0
-#define EXTINT1 (*(volatile unsigned *)0x5600008c) //External interrupt control egister 1
-#define EXTINT2 (*(volatile unsigned *)0x56000090) //External interrupt control egister 2
-#define EINTFLT0 (*(volatile unsigned *)0x56000094) //Reserved
-#define EINTFLT1 (*(volatile unsigned *)0x56000098) //Reserved
-#define EINTFLT2 (*(volatile unsigned *)0x5600009c) //External interrupt filter control egister 2
-#define EINTFLT3 (*(volatile unsigned *)0x560000a0) //External interrupt filter control egister 3
-#define EINTMASK (*(volatile unsigned *)0x560000a4) //External interrupt mask
-#define EINTPEND (*(volatile unsigned *)0x560000a8) //External interrupt pending
-#define GSTATUS0 (*(volatile unsigned *)0x560000ac) //External pin status
-#define GSTATUS1 (*(volatile unsigned *)0x560000b0) //Chip ID(0x32410000)
-#define GSTATUS2 (*(volatile unsigned *)0x560000b4) //Reset type
-#define GSTATUS3 (*(volatile unsigned *)0x560000b8) //Saved data0(32-bit) before entering POWER_OFF mode
-#define GSTATUS4 (*(volatile unsigned *)0x560000bc) //Saved data0(32-bit) before entering POWER_OFF mode
-
-
-// RTC
-#ifdef __BIG_ENDIAN
-#define RTCCON (*(volatile unsigned char *)0x57000043) //RTC control
-#define TICNT (*(volatile unsigned char *)0x57000047) //Tick time count
-#define RTCALM (*(volatile unsigned char *)0x57000053) //RTC alarm control
-#define ALMSEC (*(volatile unsigned char *)0x57000057) //Alarm second
-#define ALMMIN (*(volatile unsigned char *)0x5700005b) //Alarm minute
-#define ALMHOUR (*(volatile unsigned char *)0x5700005f) //Alarm Hour
-#define ALMDATE (*(volatile unsigned char *)0x57000063) //Alarm day <-- May 06, 2002 SOP
-#define ALMMON (*(volatile unsigned char *)0x57000067) //Alarm month
-#define ALMYEAR (*(volatile unsigned char *)0x5700006b) //Alarm year
-#define RTCRST (*(volatile unsigned char *)0x5700006f) //RTC ound eset
-#define BCDSEC (*(volatile unsigned char *)0x57000073) //BCD second
-#define BCDMIN (*(volatile unsigned char *)0x57000077) //BCD minute
-#define BCDHOUR (*(volatile unsigned char *)0x5700007b) //BCD hour
-#define BCDDATE (*(volatile unsigned char *)0x5700007f) //BCD day <-- May 06, 2002 SOP
-#define BCDDAY (*(volatile unsigned char *)0x57000083) //BCD date <-- May 06, 2002 SOP
-#define BCDMON (*(volatile unsigned char *)0x57000087) //BCD month
-#define BCDYEAR (*(volatile unsigned char *)0x5700008b) //BCD year
-
-#else //Little Endian
-#define RTCCON (*(volatile unsigned char *)0x57000040) //RTC control
-#define TICNT (*(volatile unsigned char *)0x57000044) //Tick time count
-#define RTCALM (*(volatile unsigned char *)0x57000050) //RTC alarm control
-#define ALMSEC (*(volatile unsigned char *)0x57000054) //Alarm second
-#define ALMMIN (*(volatile unsigned char *)0x57000058) //Alarm minute
-#define ALMHOUR (*(volatile unsigned char *)0x5700005c) //Alarm Hour
-#define ALMDATE (*(volatile unsigned char *)0x57000060) //Alarm day <-- May 06, 2002 SOP
-#define ALMMON (*(volatile unsigned char *)0x57000064) //Alarm month
-#define ALMYEAR (*(volatile unsigned char *)0x57000068) //Alarm year
-#define RTCRST (*(volatile unsigned char *)0x5700006c) //RTC ound eset
-#define BCDSEC (*(volatile unsigned char *)0x57000070) //BCD second
-#define BCDMIN (*(volatile unsigned char *)0x57000074) //BCD minute
-#define BCDHOUR (*(volatile unsigned char *)0x57000078) //BCD hour
-#define BCDDATE (*(volatile unsigned char *)0x5700007c) //BCD day <-- May 06, 2002 SOP
-#define BCDDAY (*(volatile unsigned char *)0x57000080) //BCD date <-- May 06, 2002 SOP
-#define BCDMON (*(volatile unsigned char *)0x57000084) //BCD month
-#define BCDYEAR (*(volatile unsigned char *)0x57000088) //BCD year
-#endif //RTC
-
-
-// ADC
-#define ADCCON (*(volatile unsigned *)0x58000000) //ADC control
-#define ADCTSC (*(volatile unsigned *)0x58000004) //ADC touch screen control
-#define ADCDLY (*(volatile unsigned *)0x58000008) //ADC start or Interval Delay
-#define ADCDAT0 (*(volatile unsigned *)0x5800000c) //ADC conversion data 0
-#define ADCDAT1 (*(volatile unsigned *)0x58000010) //ADC conversion data 1
-
-// SPI
-#define SPCON0 (*(volatile unsigned *)0x59000000) //SPI0 control
-#define SPSTA0 (*(volatile unsigned *)0x59000004) //SPI0 status
-#define SPPIN0 (*(volatile unsigned *)0x59000008) //SPI0 pin control
-#define SPPRE0 (*(volatile unsigned *)0x5900000c) //SPI0 baud ate prescaler
-#define SPTDAT0 (*(volatile unsigned *)0x59000010) //SPI0 Tx data
-#define SPRDAT0 (*(volatile unsigned *)0x59000014) //SPI0 Rx data
-
-#define SPCON1 (*(volatile unsigned *)0x59000020) //SPI1 control
-#define SPSTA1 (*(volatile unsigned *)0x59000024) //SPI1 status
-#define SPPIN1 (*(volatile unsigned *)0x59000028) //SPI1 pin control
-#define SPPRE1 (*(volatile unsigned *)0x5900002c) //SPI1 baud ate prescaler
-#define SPTDAT1 (*(volatile unsigned *)0x59000030) //SPI1 Tx data
-#define SPRDAT1 (*(volatile unsigned *)0x59000034) //SPI1 Rx data
-
-
-// SD Interface
-#define SDICON (*(volatile unsigned *)0x5a000000) //SDI control
-#define SDIPRE (*(volatile unsigned *)0x5a000004) //SDI baud ate prescaler
-#define SDICARG (*(volatile unsigned *)0x5a000008) //SDI command argument
-#define SDICCON (*(volatile unsigned *)0x5a00000c) //SDI command control
-#define SDICSTA (*(volatile unsigned *)0x5a000010) //SDI command status
-#define SDIRSP0 (*(volatile unsigned *)0x5a000014) //SDI esponse 0
-#define SDIRSP1 (*(volatile unsigned *)0x5a000018) //SDI esponse 1
-#define SDIRSP2 (*(volatile unsigned *)0x5a00001c) //SDI esponse 2
-#define SDIRSP3 (*(volatile unsigned *)0x5a000020) //SDI esponse 3
-#define SDIDTIMER (*(volatile unsigned *)0x5a000024) //SDI data/busy timer
-#define SDIBSIZE (*(volatile unsigned *)0x5a000028) //SDI block size
-#define SDIDCON (*(volatile unsigned *)0x5a00002c) //SDI data control
-#define SDIDCNT (*(volatile unsigned *)0x5a000030) //SDI data emain counter
-#define SDIDSTA (*(volatile unsigned *)0x5a000034) //SDI data status
-#define SDIFSTA (*(volatile unsigned *)0x5a000038) //SDI FIFO status
-#define SDIIMSK (*(volatile unsigned *)0x5a000040) //SDI interrupt mask
-
-#ifdef __BIG_ENDIAN /* edited for 2440A */
-#define SDIDAT (*(volatile unsigned *)0x5a00004c)
-#else // Little Endian
-#define SDIDAT (*(volatile unsigned *)0x5a000040)
-#endif //SD Interface
-
-// PENDING BIT
-#define INTEINT0 (0)
-#define INTEINT1 (1)
-#define INTEINT2 (2)
-#define INTEINT3 (3)
-#define INTEINT4_7 (4)
-#define INTEINT8_23 (5)
-#define INTNOTUSED6 (6)
-#define INTBAT_FLT (7)
-#define INTTICK (8)
-#define INTWDT (9)
-#define INTTIMER0 (10)
-#define INTTIMER1 (11)
-#define INTTIMER2 (12)
-#define INTTIMER3 (13)
-#define INTTIMER4 (14)
-#define INTUART2 (15)
-#define INTLCD (16)
-#define INTDMA0 (17)
-#define INTDMA1 (18)
-#define INTDMA2 (19)
-#define INTDMA3 (20)
-#define INTSDI (21)
-#define INTSPI0 (22)
-#define INTUART1 (23)
-//#define INTNOTUSED24 (24)
-#define INTNIC (24)
-#define INTUSBD (25)
-#define INTUSBH (26)
-#define INTIIC (27)
-#define INTUART0 (28)
-#define INTSPI1 (29)
-#define INTRTC (30)
-#define INTADC (31)
-#define BIT_ALLMSK (0xffffffff)
-
-#define BIT_SUB_ALLMSK (0x7ff)
-#define INTSUB_ADC (10)
-#define INTSUB_TC (9)
-#define INTSUB_ERR2 (8)
-#define INTSUB_TXD2 (7)
-#define INTSUB_RXD2 (6)
-#define INTSUB_ERR1 (5)
-#define INTSUB_TXD1 (4)
-#define INTSUB_RXD1 (3)
-#define INTSUB_ERR0 (2)
-#define INTSUB_TXD0 (1)
-#define INTSUB_RXD0 (0)
-
-#define BIT_SUB_ADC (0x1<<10)
-#define BIT_SUB_TC (0x1<<9)
-#define BIT_SUB_ERR2 (0x1<<8)
-#define BIT_SUB_TXD2 (0x1<<7)
-#define BIT_SUB_RXD2 (0x1<<6)
-#define BIT_SUB_ERR1 (0x1<<5)
-#define BIT_SUB_TXD1 (0x1<<4)
-#define BIT_SUB_RXD1 (0x1<<3)
-#define BIT_SUB_ERR0 (0x1<<2)
-#define BIT_SUB_TXD0 (0x1<<1)
-#define BIT_SUB_RXD0 (0x1<<0)
-
-#define ClearPending(bit) {SRCPND = bit;INTPND = bit;INTPND;}
-//Wait until INTPND is changed for the case that the ISR is very short.
-
-#define INTGLOBAL 32
-
-/*****************************/
-/* CPU Mode */
-/*****************************/
-#define USERMODE 0x10
-#define FIQMODE 0x11
-#define IRQMODE 0x12
-#define SVCMODE 0x13
-#define ABORTMODE 0x17
-#define UNDEFMODE 0x1b
-#define MODEMASK 0x1f
-#define NOINT 0xc0
-
-struct rt_hw_register
-{
- rt_uint32_t r0;
- rt_uint32_t r1;
- rt_uint32_t r2;
- rt_uint32_t r3;
- rt_uint32_t r4;
- rt_uint32_t r5;
- rt_uint32_t r6;
- rt_uint32_t r7;
- rt_uint32_t r8;
- rt_uint32_t r9;
- rt_uint32_t r10;
- rt_uint32_t fp;
- rt_uint32_t ip;
- rt_uint32_t sp;
- rt_uint32_t lr;
- rt_uint32_t pc;
- rt_uint32_t cpsr;
- rt_uint32_t ORIG_r0;
-};
-
-#ifdef __cplusplus
-}
-#endif
-
-/*@}*/
-
-#endif
+/* + * File : s3c24x0.h + * This file is part of RT-Thread RTOS + * COPYRIGHT (C) 2006, RT-Thread Develop Team + * + * The license and distribution terms for this file may be + * found in the file LICENSE in this distribution or at + * http://openlab.rt-thread.com/license/LICENSE + * + * Change Logs: + * Date Author Notes + * 2009-12-11 Bernard first version + */ + +#ifndef __S3C24X0_H__ +#define __S3C24X0_H__ + +#ifdef __cplusplus +extern "C" { +#endif + +#include <rtthread.h> + +/** + * @addtogroup S3C24X0 + */ +/*@{*/ + +// Memory control +#define BWSCON (*(volatile unsigned *)0x48000000) //Bus width & wait status +#define BANKCON0 (*(volatile unsigned *)0x48000004) //Boot ROM control +#define BANKCON1 (*(volatile unsigned *)0x48000008) //BANK1 control +#define BANKCON2 (*(volatile unsigned *)0x4800000c) //BANK2 cControl +#define BANKCON3 (*(volatile unsigned *)0x48000010) //BANK3 control +#define BANKCON4 (*(volatile unsigned *)0x48000014) //BANK4 control +#define BANKCON5 (*(volatile unsigned *)0x48000018) //BANK5 control +#define BANKCON6 (*(volatile unsigned *)0x4800001c) //BANK6 control +#define BANKCON7 (*(volatile unsigned *)0x48000020) //BANK7 control +#define REFRESH (*(volatile unsigned *)0x48000024) //DRAM/SDRAM efresh +#define BANKSIZE (*(volatile unsigned *)0x48000028) //Flexible Bank Size +#define MRSRB6 (*(volatile unsigned *)0x4800002c) //Mode egister set for SDRAM +#define MRSRB7 (*(volatile unsigned *)0x48000030) //Mode egister set for SDRAM + + +// USB Host + + +// INTERRUPT +#define SRCPND (*(volatile unsigned *)0x4a000000) //Interrupt request status +#define INTMOD (*(volatile unsigned *)0x4a000004) //Interrupt mode control +#define INTMSK (*(volatile unsigned *)0x4a000008) //Interrupt mask control +#define PRIORITY (*(volatile unsigned *)0x4a00000c) //IRQ priority control +#define INTPND (*(volatile unsigned *)0x4a000010) //Interrupt request status +#define INTOFFSET (*(volatile unsigned *)0x4a000014) //Interruot request source offset +#define SUBSRCPND (*(volatile unsigned *)0x4a000018) //Sub source pending +#define INTSUBMSK (*(volatile unsigned *)0x4a00001c) //Interrupt sub mask + + +// DMA +#define DISRC0 (*(volatile unsigned *)0x4b000000) //DMA 0 Initial source +#define DISRCC0 (*(volatile unsigned *)0x4b000004) //DMA 0 Initial source control +#define DIDST0 (*(volatile unsigned *)0x4b000008) //DMA 0 Initial Destination +#define DIDSTC0 (*(volatile unsigned *)0x4b00000c) //DMA 0 Initial Destination control +#define DCON0 (*(volatile unsigned *)0x4b000010) //DMA 0 Control +#define DSTAT0 (*(volatile unsigned *)0x4b000014) //DMA 0 Status +#define DCSRC0 (*(volatile unsigned *)0x4b000018) //DMA 0 Current source +#define DCDST0 (*(volatile unsigned *)0x4b00001c) //DMA 0 Current destination +#define DMASKTRIG0 (*(volatile unsigned *)0x4b000020) //DMA 0 Mask trigger + +#define DISRC1 (*(volatile unsigned *)0x4b000040) //DMA 1 Initial source +#define DISRCC1 (*(volatile unsigned *)0x4b000044) //DMA 1 Initial source control +#define DIDST1 (*(volatile unsigned *)0x4b000048) //DMA 1 Initial Destination +#define DIDSTC1 (*(volatile unsigned *)0x4b00004c) //DMA 1 Initial Destination control +#define DCON1 (*(volatile unsigned *)0x4b000050) //DMA 1 Control +#define DSTAT1 (*(volatile unsigned *)0x4b000054) //DMA 1 Status +#define DCSRC1 (*(volatile unsigned *)0x4b000058) //DMA 1 Current source +#define DCDST1 (*(volatile unsigned *)0x4b00005c) //DMA 1 Current destination +#define DMASKTRIG1 (*(volatile unsigned *)0x4b000060) //DMA 1 Mask trigger + +#define DISRC2 (*(volatile unsigned *)0x4b000080) //DMA 2 Initial source +#define DISRCC2 (*(volatile unsigned *)0x4b000084) //DMA 2 Initial source control +#define DIDST2 (*(volatile unsigned *)0x4b000088) //DMA 2 Initial Destination +#define DIDSTC2 (*(volatile unsigned *)0x4b00008c) //DMA 2 Initial Destination control +#define DCON2 (*(volatile unsigned *)0x4b000090) //DMA 2 Control +#define DSTAT2 (*(volatile unsigned *)0x4b000094) //DMA 2 Status +#define DCSRC2 (*(volatile unsigned *)0x4b000098) //DMA 2 Current source +#define DCDST2 (*(volatile unsigned *)0x4b00009c) //DMA 2 Current destination +#define DMASKTRIG2 (*(volatile unsigned *)0x4b0000a0) //DMA 2 Mask trigger + +#define DISRC3 (*(volatile unsigned *)0x4b0000c0) //DMA 3 Initial source +#define DISRCC3 (*(volatile unsigned *)0x4b0000c4) //DMA 3 Initial source control +#define DIDST3 (*(volatile unsigned *)0x4b0000c8) //DMA 3 Initial Destination +#define DIDSTC3 (*(volatile unsigned *)0x4b0000cc) //DMA 3 Initial Destination control +#define DCON3 (*(volatile unsigned *)0x4b0000d0) //DMA 3 Control +#define DSTAT3 (*(volatile unsigned *)0x4b0000d4) //DMA 3 Status +#define DCSRC3 (*(volatile unsigned *)0x4b0000d8) //DMA 3 Current source +#define DCDST3 (*(volatile unsigned *)0x4b0000dc) //DMA 3 Current destination +#define DMASKTRIG3 (*(volatile unsigned *)0x4b0000e0) //DMA 3 Mask trigger + + +// CLOCK & POWER MANAGEMENT +#define LOCKTIME (*(volatile unsigned *)0x4c000000) //PLL lock time counter +#define MPLLCON (*(volatile unsigned *)0x4c000004) //MPLL Control +#define UPLLCON (*(volatile unsigned *)0x4c000008) //UPLL Control +#define CLKCON (*(volatile unsigned *)0x4c00000c) //Clock generator control +#define CLKSLOW (*(volatile unsigned *)0x4c000010) //Slow clock control +#define CLKDIVN (*(volatile unsigned *)0x4c000014) //Clock divider control +#define CAMDIVN (*(volatile unsigned *)0x4c000018) //USB, CAM Clock divider control + + +// LCD CONTROLLER +#define LCDCON1 (*(volatile unsigned *)0x4d000000) //LCD control 1 +#define LCDCON2 (*(volatile unsigned *)0x4d000004) //LCD control 2 +#define LCDCON3 (*(volatile unsigned *)0x4d000008) //LCD control 3 +#define LCDCON4 (*(volatile unsigned *)0x4d00000c) //LCD control 4 +#define LCDCON5 (*(volatile unsigned *)0x4d000010) //LCD control 5 +#define LCDSADDR1 (*(volatile unsigned *)0x4d000014) //STN/TFT Frame buffer start address 1 +#define LCDSADDR2 (*(volatile unsigned *)0x4d000018) //STN/TFT Frame buffer start address 2 +#define LCDSADDR3 (*(volatile unsigned *)0x4d00001c) //STN/TFT Virtual screen address set +#define REDLUT (*(volatile unsigned *)0x4d000020) //STN Red lookup table +#define GREENLUT (*(volatile unsigned *)0x4d000024) //STN Green lookup table +#define BLUELUT (*(volatile unsigned *)0x4d000028) //STN Blue lookup table +#define DITHMODE (*(volatile unsigned *)0x4d00004c) //STN Dithering mode +#define TPAL (*(volatile unsigned *)0x4d000050) //TFT Temporary palette +#define LCDINTPND (*(volatile unsigned *)0x4d000054) //LCD Interrupt pending +#define LCDSRCPND (*(volatile unsigned *)0x4d000058) //LCD Interrupt source +#define LCDINTMSK (*(volatile unsigned *)0x4d00005c) //LCD Interrupt mask +#define LPCSEL (*(volatile unsigned *)0x4d000060) //LPC3600 Control +#define PALETTE 0x4d000400 //Palette start address + + +// NAND flash +#define NFCONF (*(volatile unsigned *)0x4e000000) //NAND Flash configuration +#define NFCMD (*(volatile unsigned *)0x4e000004) //NADD Flash command +#define NFADDR (*(volatile unsigned *)0x4e000008) //NAND Flash address +#define NFDATA (*(volatile unsigned *)0x4e00000c) //NAND Flash data +#define NFSTAT (*(volatile unsigned *)0x4e000010) //NAND Flash operation status +#define NFECC (*(volatile unsigned *)0x4e000014) //NAND Flash ECC +#define NFECC0 (*(volatile unsigned *)0x4e000014) +#define NFECC1 (*(volatile unsigned *)0x4e000015) +#define NFECC2 (*(volatile unsigned *)0x4e000016) + +// UART +#define U0BASE (*(volatile unsigned *)0x50000000) //UART 0 Line control +#define ULCON0 (*(volatile unsigned *)0x50000000) //UART 0 Line control +#define UCON0 (*(volatile unsigned *)0x50000004) //UART 0 Control +#define UFCON0 (*(volatile unsigned *)0x50000008) //UART 0 FIFO control +#define UMCON0 (*(volatile unsigned *)0x5000000c) //UART 0 Modem control +#define USTAT0 (*(volatile unsigned *)0x50000010) //UART 0 Tx/Rx status +#define URXB0 (*(volatile unsigned *)0x50000014) //UART 0 Rx error status +#define UFSTAT0 (*(volatile unsigned *)0x50000018) //UART 0 FIFO status +#define UMSTAT0 (*(volatile unsigned *)0x5000001c) //UART 0 Modem status +#define UBRD0 (*(volatile unsigned *)0x50000028) //UART 0 Baud ate divisor + +#define U1BASE (*(volatile unsigned *)0x50004000) //UART 1 Line control +#define ULCON1 (*(volatile unsigned *)0x50004000) //UART 1 Line control +#define UCON1 (*(volatile unsigned *)0x50004004) //UART 1 Control +#define UFCON1 (*(volatile unsigned *)0x50004008) //UART 1 FIFO control +#define UMCON1 (*(volatile unsigned *)0x5000400c) //UART 1 Modem control +#define USTAT1 (*(volatile unsigned *)0x50004010) //UART 1 Tx/Rx status +#define URXB1 (*(volatile unsigned *)0x50004014) //UART 1 Rx error status +#define UFSTAT1 (*(volatile unsigned *)0x50004018) //UART 1 FIFO status +#define UMSTAT1 (*(volatile unsigned *)0x5000401c) //UART 1 Modem status +#define UBRD1 (*(volatile unsigned *)0x50004028) //UART 1 Baud ate divisor + +#define U2BASE *(volatile unsigned *)0x50008000 //UART 2 Line control +#define ULCON2 (*(volatile unsigned *)0x50008000) //UART 2 Line control +#define UCON2 (*(volatile unsigned *)0x50008004) //UART 2 Control +#define UFCON2 (*(volatile unsigned *)0x50008008) //UART 2 FIFO control +#define UMCON2 (*(volatile unsigned *)0x5000800c) //UART 2 Modem control +#define USTAT2 (*(volatile unsigned *)0x50008010) //UART 2 Tx/Rx status +#define URXB2 (*(volatile unsigned *)0x50008014) //UART 2 Rx error status +#define UFSTAT2 (*(volatile unsigned *)0x50008018) //UART 2 FIFO status +#define UMSTAT2 (*(volatile unsigned *)0x5000801c) //UART 2 Modem status +#define UBRD2 (*(volatile unsigned *)0x50008028) //UART 2 Baud ate divisor + +#ifdef __BIG_ENDIAN +#define UTXH0 (*(volatile unsigned char *)0x50000023) //UART 0 Transmission Hold +#define URXH0 (*(volatile unsigned char *)0x50000027) //UART 0 Receive buffer +#define UTXH1 (*(volatile unsigned char *)0x50004023) //UART 1 Transmission Hold +#define URXH1 (*(volatile unsigned char *)0x50004027) //UART 1 Receive buffer +#define UTXH2 (*(volatile unsigned char *)0x50008023) //UART 2 Transmission Hold +#define URXH2 (*(volatile unsigned char *)0x50008027) //UART 2 Receive buffer + +#define WrUTXH0(ch) (*(volatile unsigned char *)0x50000023)=(unsigned char)(ch) +#define RdURXH0() (*(volatile unsigned char *)0x50000027) +#define WrUTXH1(ch) (*(volatile unsigned char *)0x50004023)=(unsigned char)(ch) +#define RdURXH1() (*(volatile unsigned char *)0x50004027) +#define WrUTXH2(ch) (*(volatile unsigned char *)0x50008023)=(unsigned char)(ch) +#define RdURXH2() (*(volatile unsigned char *)0x50008027) + +#else //Little Endian +#define UTXH0 (*(volatile unsigned char *)0x50000020) //UART 0 Transmission Hold +#define URXH0 (*(volatile unsigned char *)0x50000024) //UART 0 Receive buffer +#define UTXH1 (*(volatile unsigned char *)0x50004020) //UART 1 Transmission Hold +#define URXH1 (*(volatile unsigned char *)0x50004024) //UART 1 Receive buffer +#define UTXH2 (*(volatile unsigned char *)0x50008020) //UART 2 Transmission Hold +#define URXH2 (*(volatile unsigned char *)0x50008024) //UART 2 Receive buffer + +#define WrUTXH0(ch) (*(volatile unsigned char *)0x50000020)=(unsigned char)(ch) +#define RdURXH0() (*(volatile unsigned char *)0x50000024) +#define WrUTXH1(ch) (*(volatile unsigned char *)0x50004020)=(unsigned char)(ch) +#define RdURXH1() (*(volatile unsigned char *)0x50004024) +#define WrUTXH2(ch) (*(volatile unsigned char *)0x50008020)=(unsigned char)(ch) +#define RdURXH2() (*(volatile unsigned char *)0x50008024) + +#endif + + +// PWM TIMER +#define TCFG0 (*(volatile unsigned *)0x51000000) //Timer 0 configuration +#define TCFG1 (*(volatile unsigned *)0x51000004) //Timer 1 configuration +#define TCON (*(volatile unsigned *)0x51000008) //Timer control +#define TCNTB0 (*(volatile unsigned *)0x5100000c) //Timer count buffer 0 +#define TCMPB0 (*(volatile unsigned *)0x51000010) //Timer compare buffer 0 +#define TCNTO0 (*(volatile unsigned *)0x51000014) //Timer count observation 0 +#define TCNTB1 (*(volatile unsigned *)0x51000018) //Timer count buffer 1 +#define TCMPB1 (*(volatile unsigned *)0x5100001c) //Timer compare buffer 1 +#define TCNTO1 (*(volatile unsigned *)0x51000020) //Timer count observation 1 +#define TCNTB2 (*(volatile unsigned *)0x51000024) //Timer count buffer 2 +#define TCMPB2 (*(volatile unsigned *)0x51000028) //Timer compare buffer 2 +#define TCNTO2 (*(volatile unsigned *)0x5100002c) //Timer count observation 2 +#define TCNTB3 (*(volatile unsigned *)0x51000030) //Timer count buffer 3 +#define TCMPB3 (*(volatile unsigned *)0x51000034) //Timer compare buffer 3 +#define TCNTO3 (*(volatile unsigned *)0x51000038) //Timer count observation 3 +#define TCNTB4 (*(volatile unsigned *)0x5100003c) //Timer count buffer 4 +#define TCNTO4 (*(volatile unsigned *)0x51000040) //Timer count observation 4 + +// Added for 2440 +#define FLTOUT (*(volatile unsigned *)0x560000c0) // Filter output(Read only) +#define DSC0 (*(volatile unsigned *)0x560000c4) // Strength control register 0 +#define DSC1 (*(volatile unsigned *)0x560000c8) // Strength control register 1 +#define MSLCON (*(volatile unsigned *)0x560000cc) // Memory sleep control register + + +// USB DEVICE +#ifdef __BIG_ENDIAN +#define FUNC_ADDR_REG (*(volatile unsigned char *)0x52000143) //Function address +#define PWR_REG (*(volatile unsigned char *)0x52000147) //Power management +#define EP_INT_REG (*(volatile unsigned char *)0x5200014b) //EP Interrupt pending and clear +#define USB_INT_REG (*(volatile unsigned char *)0x5200015b) //USB Interrupt pending and clear +#define EP_INT_EN_REG (*(volatile unsigned char *)0x5200015f) //Interrupt enable +#define USB_INT_EN_REG (*(volatile unsigned char *)0x5200016f) +#define FRAME_NUM1_REG (*(volatile unsigned char *)0x52000173) //Frame number lower byte +#define FRAME_NUM2_REG (*(volatile unsigned char *)0x52000177) //Frame number higher byte +#define INDEX_REG (*(volatile unsigned char *)0x5200017b) //Register index +#define MAXP_REG (*(volatile unsigned char *)0x52000183) //Endpoint max packet +#define EP0_CSR (*(volatile unsigned char *)0x52000187) //Endpoint 0 status +#define IN_CSR1_REG (*(volatile unsigned char *)0x52000187) //In endpoint control status +#define IN_CSR2_REG (*(volatile unsigned char *)0x5200018b) +#define OUT_CSR1_REG (*(volatile unsigned char *)0x52000193) //Out endpoint control status +#define OUT_CSR2_REG (*(volatile unsigned char *)0x52000197) +#define OUT_FIFO_CNT1_REG (*(volatile unsigned char *)0x5200019b) //Endpoint out write count +#define OUT_FIFO_CNT2_REG (*(volatile unsigned char *)0x5200019f) +#define EP0_FIFO (*(volatile unsigned char *)0x520001c3) //Endpoint 0 FIFO +#define EP1_FIFO (*(volatile unsigned char *)0x520001c7) //Endpoint 1 FIFO +#define EP2_FIFO (*(volatile unsigned char *)0x520001cb) //Endpoint 2 FIFO +#define EP3_FIFO (*(volatile unsigned char *)0x520001cf) //Endpoint 3 FIFO +#define EP4_FIFO (*(volatile unsigned char *)0x520001d3) //Endpoint 4 FIFO +#define EP1_DMA_CON (*(volatile unsigned char *)0x52000203) //EP1 DMA interface control +#define EP1_DMA_UNIT (*(volatile unsigned char *)0x52000207) //EP1 DMA Tx unit counter +#define EP1_DMA_FIFO (*(volatile unsigned char *)0x5200020b) //EP1 DMA Tx FIFO counter +#define EP1_DMA_TTC_L (*(volatile unsigned char *)0x5200020f) //EP1 DMA total Tx counter +#define EP1_DMA_TTC_M (*(volatile unsigned char *)0x52000213) +#define EP1_DMA_TTC_H (*(volatile unsigned char *)0x52000217) +#define EP2_DMA_CON (*(volatile unsigned char *)0x5200021b) //EP2 DMA interface control +#define EP2_DMA_UNIT (*(volatile unsigned char *)0x5200021f) //EP2 DMA Tx unit counter +#define EP2_DMA_FIFO (*(volatile unsigned char *)0x52000223) //EP2 DMA Tx FIFO counter +#define EP2_DMA_TTC_L (*(volatile unsigned char *)0x52000227) //EP2 DMA total Tx counter +#define EP2_DMA_TTC_M (*(volatile unsigned char *)0x5200022b) +#define EP2_DMA_TTC_H (*(volatile unsigned char *)0x5200022f) +#define EP3_DMA_CON (*(volatile unsigned char *)0x52000243) //EP3 DMA interface control +#define EP3_DMA_UNIT (*(volatile unsigned char *)0x52000247) //EP3 DMA Tx unit counter +#define EP3_DMA_FIFO (*(volatile unsigned char *)0x5200024b) //EP3 DMA Tx FIFO counter +#define EP3_DMA_TTC_L (*(volatile unsigned char *)0x5200024f) //EP3 DMA total Tx counter +#define EP3_DMA_TTC_M (*(volatile unsigned char *)0x52000253) +#define EP3_DMA_TTC_H (*(volatile unsigned char *)0x52000257) +#define EP4_DMA_CON (*(volatile unsigned char *)0x5200025b) //EP4 DMA interface control +#define EP4_DMA_UNIT (*(volatile unsigned char *)0x5200025f) //EP4 DMA Tx unit counter +#define EP4_DMA_FIFO (*(volatile unsigned char *)0x52000263) //EP4 DMA Tx FIFO counter +#define EP4_DMA_TTC_L (*(volatile unsigned char *)0x52000267) //EP4 DMA total Tx counter +#define EP4_DMA_TTC_M (*(volatile unsigned char *)0x5200026b) +#define EP4_DMA_TTC_H (*(volatile unsigned char *)0x5200026f) + +#else // Little Endian +#define FUNC_ADDR_REG (*(volatile unsigned char *)0x52000140) //Function address +#define PWR_REG (*(volatile unsigned char *)0x52000144) //Power management +#define EP_INT_REG (*(volatile unsigned char *)0x52000148) //EP Interrupt pending and clear +#define USB_INT_REG (*(volatile unsigned char *)0x52000158) //USB Interrupt pending and clear +#define EP_INT_EN_REG (*(volatile unsigned char *)0x5200015c) //Interrupt enable +#define USB_INT_EN_REG (*(volatile unsigned char *)0x5200016c) +#define FRAME_NUM1_REG (*(volatile unsigned char *)0x52000170) //Frame number lower byte +#define FRAME_NUM2_REG (*(volatile unsigned char *)0x52000174) //Frame number higher byte +#define INDEX_REG (*(volatile unsigned char *)0x52000178) //Register index +#define MAXP_REG (*(volatile unsigned char *)0x52000180) //Endpoint max packet +#define EP0_CSR (*(volatile unsigned char *)0x52000184) //Endpoint 0 status +#define IN_CSR1_REG (*(volatile unsigned char *)0x52000184) //In endpoint control status +#define IN_CSR2_REG (*(volatile unsigned char *)0x52000188) +#define OUT_CSR1_REG (*(volatile unsigned char *)0x52000190) //Out endpoint control status +#define OUT_CSR2_REG (*(volatile unsigned char *)0x52000194) +#define OUT_FIFO_CNT1_REG (*(volatile unsigned char *)0x52000198) //Endpoint out write count +#define OUT_FIFO_CNT2_REG (*(volatile unsigned char *)0x5200019c) +#define EP0_FIFO (*(volatile unsigned char *)0x520001c0) //Endpoint 0 FIFO +#define EP1_FIFO (*(volatile unsigned char *)0x520001c4) //Endpoint 1 FIFO +#define EP2_FIFO (*(volatile unsigned char *)0x520001c8) //Endpoint 2 FIFO +#define EP3_FIFO (*(volatile unsigned char *)0x520001cc) //Endpoint 3 FIFO +#define EP4_FIFO (*(volatile unsigned char *)0x520001d0) //Endpoint 4 FIFO +#define EP1_DMA_CON (*(volatile unsigned char *)0x52000200) //EP1 DMA interface control +#define EP1_DMA_UNIT (*(volatile unsigned char *)0x52000204) //EP1 DMA Tx unit counter +#define EP1_DMA_FIFO (*(volatile unsigned char *)0x52000208) //EP1 DMA Tx FIFO counter +#define EP1_DMA_TTC_L (*(volatile unsigned char *)0x5200020c) //EP1 DMA total Tx counter +#define EP1_DMA_TTC_M (*(volatile unsigned char *)0x52000210) +#define EP1_DMA_TTC_H (*(volatile unsigned char *)0x52000214) +#define EP2_DMA_CON (*(volatile unsigned char *)0x52000218) //EP2 DMA interface control +#define EP2_DMA_UNIT (*(volatile unsigned char *)0x5200021c) //EP2 DMA Tx unit counter +#define EP2_DMA_FIFO (*(volatile unsigned char *)0x52000220) //EP2 DMA Tx FIFO counter +#define EP2_DMA_TTC_L (*(volatile unsigned char *)0x52000224) //EP2 DMA total Tx counter +#define EP2_DMA_TTC_M (*(volatile unsigned char *)0x52000228) +#define EP2_DMA_TTC_H (*(volatile unsigned char *)0x5200022c) +#define EP3_DMA_CON (*(volatile unsigned char *)0x52000240) //EP3 DMA interface control +#define EP3_DMA_UNIT (*(volatile unsigned char *)0x52000244) //EP3 DMA Tx unit counter +#define EP3_DMA_FIFO (*(volatile unsigned char *)0x52000248) //EP3 DMA Tx FIFO counter +#define EP3_DMA_TTC_L (*(volatile unsigned char *)0x5200024c) //EP3 DMA total Tx counter +#define EP3_DMA_TTC_M (*(volatile unsigned char *)0x52000250) +#define EP3_DMA_TTC_H (*(volatile unsigned char *)0x52000254) +#define EP4_DMA_CON (*(volatile unsigned char *)0x52000258) //EP4 DMA interface control +#define EP4_DMA_UNIT (*(volatile unsigned char *)0x5200025c) //EP4 DMA Tx unit counter +#define EP4_DMA_FIFO (*(volatile unsigned char *)0x52000260) //EP4 DMA Tx FIFO counter +#define EP4_DMA_TTC_L (*(volatile unsigned char *)0x52000264) //EP4 DMA total Tx counter +#define EP4_DMA_TTC_M (*(volatile unsigned char *)0x52000268) +#define EP4_DMA_TTC_H (*(volatile unsigned char *)0x5200026c) +#endif // __BIG_ENDIAN + + +// WATCH DOG TIMER +#define WTCON (*(volatile unsigned *)0x53000000) //Watch-dog timer mode +#define WTDAT (*(volatile unsigned *)0x53000004) //Watch-dog timer data +#define WTCNT (*(volatile unsigned *)0x53000008) //Eatch-dog timer count + + +// IIC +#define IICCON (*(volatile unsigned *)0x54000000) //IIC control +#define IICSTAT (*(volatile unsigned *)0x54000004) //IIC status +#define IICADD (*(volatile unsigned *)0x54000008) //IIC address +#define IICDS (*(volatile unsigned *)0x5400000c) //IIC data shift + + +// IIS +#define IISCON (*(volatile unsigned *)0x55000000) //IIS Control +#define IISMOD (*(volatile unsigned *)0x55000004) //IIS Mode +#define IISPSR (*(volatile unsigned *)0x55000008) //IIS Prescaler +#define IISFCON (*(volatile unsigned *)0x5500000c) //IIS FIFO control + +#ifdef __BIG_ENDIAN +#define IISFIFO ((volatile unsigned short *)0x55000012) //IIS FIFO entry + +#else //Little Endian +#define IISFIFO ((volatile unsigned short *)0x55000010) //IIS FIFO entry + +#endif + + +// I/O PORT +#define GPACON (*(volatile unsigned *)0x56000000) //Port A control +#define GPADAT (*(volatile unsigned *)0x56000004) //Port A data + +#define GPBCON (*(volatile unsigned *)0x56000010) //Port B control +#define GPBDAT (*(volatile unsigned *)0x56000014) //Port B data +#define GPBUP (*(volatile unsigned *)0x56000018) //Pull-up control B + +#define GPCCON (*(volatile unsigned *)0x56000020) //Port C control +#define GPCDAT (*(volatile unsigned *)0x56000024) //Port C data +#define GPCUP (*(volatile unsigned *)0x56000028) //Pull-up control C + +#define GPDCON (*(volatile unsigned *)0x56000030) //Port D control +#define GPDDAT (*(volatile unsigned *)0x56000034) //Port D data +#define GPDUP (*(volatile unsigned *)0x56000038) //Pull-up control D + +#define GPECON (*(volatile unsigned *)0x56000040) //Port E control +#define GPEDAT (*(volatile unsigned *)0x56000044) //Port E data +#define GPEUP (*(volatile unsigned *)0x56000048) //Pull-up control E + +#define GPFCON (*(volatile unsigned *)0x56000050) //Port F control +#define GPFDAT (*(volatile unsigned *)0x56000054) //Port F data +#define GPFUP (*(volatile unsigned *)0x56000058) //Pull-up control F + +#define GPGCON (*(volatile unsigned *)0x56000060) //Port G control +#define GPGDAT (*(volatile unsigned *)0x56000064) //Port G data +#define GPGUP (*(volatile unsigned *)0x56000068) //Pull-up control G + +#define GPHCON (*(volatile unsigned *)0x56000070) //Port H control +#define GPHDAT (*(volatile unsigned *)0x56000074) //Port H data +#define GPHUP (*(volatile unsigned *)0x56000078) //Pull-up control H + +#define GPJCON (*(volatile unsigned *)0x560000d0) //Port J control +#define GPJDAT (*(volatile unsigned *)0x560000d4) //Port J data +#define GPJUP (*(volatile unsigned *)0x560000d8) //Pull-up control J + +#define MISCCR (*(volatile unsigned *)0x56000080) //Miscellaneous control +#define DCLKCON (*(volatile unsigned *)0x56000084) //DCLK0/1 control +#define EXTINT0 (*(volatile unsigned *)0x56000088) //External interrupt control egister 0 +#define EXTINT1 (*(volatile unsigned *)0x5600008c) //External interrupt control egister 1 +#define EXTINT2 (*(volatile unsigned *)0x56000090) //External interrupt control egister 2 +#define EINTFLT0 (*(volatile unsigned *)0x56000094) //Reserved +#define EINTFLT1 (*(volatile unsigned *)0x56000098) //Reserved +#define EINTFLT2 (*(volatile unsigned *)0x5600009c) //External interrupt filter control egister 2 +#define EINTFLT3 (*(volatile unsigned *)0x560000a0) //External interrupt filter control egister 3 +#define EINTMASK (*(volatile unsigned *)0x560000a4) //External interrupt mask +#define EINTPEND (*(volatile unsigned *)0x560000a8) //External interrupt pending +#define GSTATUS0 (*(volatile unsigned *)0x560000ac) //External pin status +#define GSTATUS1 (*(volatile unsigned *)0x560000b0) //Chip ID(0x32410000) +#define GSTATUS2 (*(volatile unsigned *)0x560000b4) //Reset type +#define GSTATUS3 (*(volatile unsigned *)0x560000b8) //Saved data0(32-bit) before entering POWER_OFF mode +#define GSTATUS4 (*(volatile unsigned *)0x560000bc) //Saved data0(32-bit) before entering POWER_OFF mode + + +// RTC +#ifdef __BIG_ENDIAN +#define RTCCON (*(volatile unsigned char *)0x57000043) //RTC control +#define TICNT (*(volatile unsigned char *)0x57000047) //Tick time count +#define RTCALM (*(volatile unsigned char *)0x57000053) //RTC alarm control +#define ALMSEC (*(volatile unsigned char *)0x57000057) //Alarm second +#define ALMMIN (*(volatile unsigned char *)0x5700005b) //Alarm minute +#define ALMHOUR (*(volatile unsigned char *)0x5700005f) //Alarm Hour +#define ALMDATE (*(volatile unsigned char *)0x57000063) //Alarm day <-- May 06, 2002 SOP +#define ALMMON (*(volatile unsigned char *)0x57000067) //Alarm month +#define ALMYEAR (*(volatile unsigned char *)0x5700006b) //Alarm year +#define RTCRST (*(volatile unsigned char *)0x5700006f) //RTC ound eset +#define BCDSEC (*(volatile unsigned char *)0x57000073) //BCD second +#define BCDMIN (*(volatile unsigned char *)0x57000077) //BCD minute +#define BCDHOUR (*(volatile unsigned char *)0x5700007b) //BCD hour +#define BCDDATE (*(volatile unsigned char *)0x5700007f) //BCD day <-- May 06, 2002 SOP +#define BCDDAY (*(volatile unsigned char *)0x57000083) //BCD date <-- May 06, 2002 SOP +#define BCDMON (*(volatile unsigned char *)0x57000087) //BCD month +#define BCDYEAR (*(volatile unsigned char *)0x5700008b) //BCD year + +#else //Little Endian +#define RTCCON (*(volatile unsigned char *)0x57000040) //RTC control +#define TICNT (*(volatile unsigned char *)0x57000044) //Tick time count +#define RTCALM (*(volatile unsigned char *)0x57000050) //RTC alarm control +#define ALMSEC (*(volatile unsigned char *)0x57000054) //Alarm second +#define ALMMIN (*(volatile unsigned char *)0x57000058) //Alarm minute +#define ALMHOUR (*(volatile unsigned char *)0x5700005c) //Alarm Hour +#define ALMDATE (*(volatile unsigned char *)0x57000060) //Alarm day <-- May 06, 2002 SOP +#define ALMMON (*(volatile unsigned char *)0x57000064) //Alarm month +#define ALMYEAR (*(volatile unsigned char *)0x57000068) //Alarm year +#define RTCRST (*(volatile unsigned char *)0x5700006c) //RTC ound eset +#define BCDSEC (*(volatile unsigned char *)0x57000070) //BCD second +#define BCDMIN (*(volatile unsigned char *)0x57000074) //BCD minute +#define BCDHOUR (*(volatile unsigned char *)0x57000078) //BCD hour +#define BCDDATE (*(volatile unsigned char *)0x5700007c) //BCD day <-- May 06, 2002 SOP +#define BCDDAY (*(volatile unsigned char *)0x57000080) //BCD date <-- May 06, 2002 SOP +#define BCDMON (*(volatile unsigned char *)0x57000084) //BCD month +#define BCDYEAR (*(volatile unsigned char *)0x57000088) //BCD year +#endif //RTC + + +// ADC +#define ADCCON (*(volatile unsigned *)0x58000000) //ADC control +#define ADCTSC (*(volatile unsigned *)0x58000004) //ADC touch screen control +#define ADCDLY (*(volatile unsigned *)0x58000008) //ADC start or Interval Delay +#define ADCDAT0 (*(volatile unsigned *)0x5800000c) //ADC conversion data 0 +#define ADCDAT1 (*(volatile unsigned *)0x58000010) //ADC conversion data 1 + +// SPI +#define SPCON0 (*(volatile unsigned *)0x59000000) //SPI0 control +#define SPSTA0 (*(volatile unsigned *)0x59000004) //SPI0 status +#define SPPIN0 (*(volatile unsigned *)0x59000008) //SPI0 pin control +#define SPPRE0 (*(volatile unsigned *)0x5900000c) //SPI0 baud ate prescaler +#define SPTDAT0 (*(volatile unsigned *)0x59000010) //SPI0 Tx data +#define SPRDAT0 (*(volatile unsigned *)0x59000014) //SPI0 Rx data + +#define SPCON1 (*(volatile unsigned *)0x59000020) //SPI1 control +#define SPSTA1 (*(volatile unsigned *)0x59000024) //SPI1 status +#define SPPIN1 (*(volatile unsigned *)0x59000028) //SPI1 pin control +#define SPPRE1 (*(volatile unsigned *)0x5900002c) //SPI1 baud ate prescaler +#define SPTDAT1 (*(volatile unsigned *)0x59000030) //SPI1 Tx data +#define SPRDAT1 (*(volatile unsigned *)0x59000034) //SPI1 Rx data + + +// SD Interface +#define SDICON (*(volatile unsigned *)0x5a000000) //SDI control +#define SDIPRE (*(volatile unsigned *)0x5a000004) //SDI baud ate prescaler +#define SDICARG (*(volatile unsigned *)0x5a000008) //SDI command argument +#define SDICCON (*(volatile unsigned *)0x5a00000c) //SDI command control +#define SDICSTA (*(volatile unsigned *)0x5a000010) //SDI command status +#define SDIRSP0 (*(volatile unsigned *)0x5a000014) //SDI esponse 0 +#define SDIRSP1 (*(volatile unsigned *)0x5a000018) //SDI esponse 1 +#define SDIRSP2 (*(volatile unsigned *)0x5a00001c) //SDI esponse 2 +#define SDIRSP3 (*(volatile unsigned *)0x5a000020) //SDI esponse 3 +#define SDIDTIMER (*(volatile unsigned *)0x5a000024) //SDI data/busy timer +#define SDIBSIZE (*(volatile unsigned *)0x5a000028) //SDI block size +#define SDIDCON (*(volatile unsigned *)0x5a00002c) //SDI data control +#define SDIDCNT (*(volatile unsigned *)0x5a000030) //SDI data emain counter +#define SDIDSTA (*(volatile unsigned *)0x5a000034) //SDI data status +#define SDIFSTA (*(volatile unsigned *)0x5a000038) //SDI FIFO status +#define SDIIMSK (*(volatile unsigned *)0x5a000040) //SDI interrupt mask + +#ifdef __BIG_ENDIAN /* edited for 2440A */ +#define SDIDAT (*(volatile unsigned *)0x5a00004c) +#else // Little Endian +#define SDIDAT (*(volatile unsigned *)0x5a000040) +#endif //SD Interface + +// PENDING BIT +#define INTEINT0 (0) +#define INTEINT1 (1) +#define INTEINT2 (2) +#define INTEINT3 (3) +#define INTEINT4_7 (4) +#define INTEINT8_23 (5) +#define INTNOTUSED6 (6) +#define INTBAT_FLT (7) +#define INTTICK (8) +#define INTWDT (9) +#define INTTIMER0 (10) +#define INTTIMER1 (11) +#define INTTIMER2 (12) +#define INTTIMER3 (13) +#define INTTIMER4 (14) +#define INTUART2 (15) +#define INTLCD (16) +#define INTDMA0 (17) +#define INTDMA1 (18) +#define INTDMA2 (19) +#define INTDMA3 (20) +#define INTSDI (21) +#define INTSPI0 (22) +#define INTUART1 (23) +//#define INTNOTUSED24 (24) +#define INTNIC (24) +#define INTUSBD (25) +#define INTUSBH (26) +#define INTIIC (27) +#define INTUART0 (28) +#define INTSPI1 (29) +#define INTRTC (30) +#define INTADC (31) +#define BIT_ALLMSK (0xffffffff) + +#define BIT_SUB_ALLMSK (0x7ff) +#define INTSUB_ADC (10) +#define INTSUB_TC (9) +#define INTSUB_ERR2 (8) +#define INTSUB_TXD2 (7) +#define INTSUB_RXD2 (6) +#define INTSUB_ERR1 (5) +#define INTSUB_TXD1 (4) +#define INTSUB_RXD1 (3) +#define INTSUB_ERR0 (2) +#define INTSUB_TXD0 (1) +#define INTSUB_RXD0 (0) + +#define BIT_SUB_ADC (0x1<<10) +#define BIT_SUB_TC (0x1<<9) +#define BIT_SUB_ERR2 (0x1<<8) +#define BIT_SUB_TXD2 (0x1<<7) +#define BIT_SUB_RXD2 (0x1<<6) +#define BIT_SUB_ERR1 (0x1<<5) +#define BIT_SUB_TXD1 (0x1<<4) +#define BIT_SUB_RXD1 (0x1<<3) +#define BIT_SUB_ERR0 (0x1<<2) +#define BIT_SUB_TXD0 (0x1<<1) +#define BIT_SUB_RXD0 (0x1<<0) + +#define ClearPending(bit) {SRCPND = bit;INTPND = bit;INTPND;} +//Wait until INTPND is changed for the case that the ISR is very short. + +#define INTGLOBAL 32 + +/*****************************/ +/* CPU Mode */ +/*****************************/ +#define USERMODE 0x10 +#define FIQMODE 0x11 +#define IRQMODE 0x12 +#define SVCMODE 0x13 +#define ABORTMODE 0x17 +#define UNDEFMODE 0x1b +#define MODEMASK 0x1f +#define NOINT 0xc0 + +struct rt_hw_register +{ + rt_uint32_t r0; + rt_uint32_t r1; + rt_uint32_t r2; + rt_uint32_t r3; + rt_uint32_t r4; + rt_uint32_t r5; + rt_uint32_t r6; + rt_uint32_t r7; + rt_uint32_t r8; + rt_uint32_t r9; + rt_uint32_t r10; + rt_uint32_t fp; + rt_uint32_t ip; + rt_uint32_t sp; + rt_uint32_t lr; + rt_uint32_t pc; + rt_uint32_t cpsr; + rt_uint32_t ORIG_r0; +}; + +#ifdef __cplusplus +} +#endif + +/*@}*/ + +#endif diff --git a/libcpu/arm/s3c24x0/serial.h b/libcpu/arm/s3c24x0/serial.h index 1015f2a935..e3deb5b887 100644 --- a/libcpu/arm/s3c24x0/serial.h +++ b/libcpu/arm/s3c24x0/serial.h @@ -1,58 +1,58 @@ -#ifndef __RT_HW_SERIAL_H__
-#define __RT_HW_SERIAL_H__
-
-#include <rthw.h>
-#include <rtthread.h>
-
-#include "s3c24x0.h"
-
-#define USTAT_RCV_READY 0x01 /* receive data ready */
-#define USTAT_TXB_EMPTY 0x02 /* tx buffer empty */
-#define BPS 115200 /* serial baudrate */
-
-#define UART_RX_BUFFER_SIZE 64
-#define UART_TX_BUFFER_SIZE 64
-
-struct serial_int_rx
-{
- rt_uint8_t rx_buffer[UART_RX_BUFFER_SIZE];
- rt_uint32_t read_index, save_index;
-};
-
-struct serial_int_tx
-{
- rt_uint8_t tx_buffer[UART_TX_BUFFER_SIZE];
- rt_uint32_t write_index, save_index;
-};
-
-typedef struct uartport
-{
- volatile rt_uint32_t ulcon;
- volatile rt_uint32_t ucon;
- volatile rt_uint32_t ufcon;
- volatile rt_uint32_t umcon;
- volatile rt_uint32_t ustat;
- volatile rt_uint32_t urxb;
- volatile rt_uint32_t ufstat;
- volatile rt_uint32_t umstat;
- volatile rt_uint32_t utxh;
- volatile rt_uint32_t urxh;
- volatile rt_uint32_t ubrd;
-}uartport;
-
-struct serial_device
-{
- uartport* uart_device;
-
- /* rx structure */
- struct serial_int_rx* int_rx;
-
- /* tx structure */
- struct serial_int_tx* int_tx;
-};
-
-rt_err_t rt_hw_serial_register(rt_device_t device, const char* name, rt_uint32_t flag, struct serial_device *serial);
-
-void rt_hw_serial_isr(rt_device_t device);
-
-#endif
+#ifndef __RT_HW_SERIAL_H__ +#define __RT_HW_SERIAL_H__ + +#include <rthw.h> +#include <rtthread.h> + +#include "s3c24x0.h" + +#define USTAT_RCV_READY 0x01 /* receive data ready */ +#define USTAT_TXB_EMPTY 0x02 /* tx buffer empty */ +#define BPS 115200 /* serial baudrate */ + +#define UART_RX_BUFFER_SIZE 64 +#define UART_TX_BUFFER_SIZE 64 + +struct serial_int_rx +{ + rt_uint8_t rx_buffer[UART_RX_BUFFER_SIZE]; + rt_uint32_t read_index, save_index; +}; + +struct serial_int_tx +{ + rt_uint8_t tx_buffer[UART_TX_BUFFER_SIZE]; + rt_uint32_t write_index, save_index; +}; + +typedef struct uartport +{ + volatile rt_uint32_t ulcon; + volatile rt_uint32_t ucon; + volatile rt_uint32_t ufcon; + volatile rt_uint32_t umcon; + volatile rt_uint32_t ustat; + volatile rt_uint32_t urxb; + volatile rt_uint32_t ufstat; + volatile rt_uint32_t umstat; + volatile rt_uint32_t utxh; + volatile rt_uint32_t urxh; + volatile rt_uint32_t ubrd; +}uartport; + +struct serial_device +{ + uartport* uart_device; + + /* rx structure */ + struct serial_int_rx* int_rx; + + /* tx structure */ + struct serial_int_tx* int_tx; +}; + +rt_err_t rt_hw_serial_register(rt_device_t device, const char* name, rt_uint32_t flag, struct serial_device *serial); + +void rt_hw_serial_isr(rt_device_t device); + +#endif diff --git a/libcpu/arm/s3c24x0/start_rvds.S b/libcpu/arm/s3c24x0/start_rvds.S index 38872cd93b..dd5e9cc309 100644 --- a/libcpu/arm/s3c24x0/start_rvds.S +++ b/libcpu/arm/s3c24x0/start_rvds.S @@ -1,1190 +1,1190 @@ -;/*****************************************************************************/
-;/* S3C2440.S: Startup file for Samsung S3C440 */
-;/*****************************************************************************/
-;/* <<< Use Configuration Wizard in Context Menu >>> */
-;/*****************************************************************************/
-;/* This file is part of the uVision/ARM development tools. */
-;/* Copyright (c) 2005-2008 Keil Software. All rights reserved. */
-;/* This software may only be used under the terms of a valid, current, */
-;/* end user licence from KEIL for a compatible version of KEIL software */
-;/* development tools. Nothing else gives you the right to use this software. */
-;/*****************************************************************************/
-
-
-;/*
-; * The S3C2440.S code is executed after CPU Reset. This file may be
-; * translated with the following SET symbols. In uVision these SET
-; * symbols are entered under Options - ASM - Define.
-; *
-; * NO_CLOCK_SETUP: when set the startup code will not initialize Clock
-; * (used mostly when clock is already initialized from script .ini
-; * file).
-; *
-; * NO_MC_SETUP: when set the startup code will not initialize Memory
-; * Controller (used mostly when clock is already initialized from script
-; * .ini file).
-; *
-; * NO_GP_SETUP: when set the startup code will not initialize General Ports
-; * (used mostly when clock is already initialized from script .ini
-; * file).
-; *
-; * RAM_INTVEC: when set the startup code copies exception vectors
-; * from execution address to on-chip RAM.
-; */
-
-
-; Standard definitions of Mode bits and Interrupt (I & F) flags in PSRs
-
-Mode_USR EQU 0x10
-Mode_FIQ EQU 0x11
-Mode_IRQ EQU 0x12
-Mode_SVC EQU 0x13
-Mode_ABT EQU 0x17
-Mode_UND EQU 0x1B
-Mode_SYS EQU 0x1F
-
-I_Bit EQU 0x80 ; when I bit is set, IRQ is disabled
-F_Bit EQU 0x40 ; when F bit is set, FIQ is disabled
-
-
-;----------------------- Stack and Heap Definitions ----------------------------
-
-;// <h> Stack Configuration (Stack Sizes in Bytes)
-;// <o0> Undefined Mode <0x0-0xFFFFFFFF:8>
-;// <o1> Supervisor Mode <0x0-0xFFFFFFFF:8>
-;// <o2> Abort Mode <0x0-0xFFFFFFFF:8>
-;// <o3> Fast Interrupt Mode <0x0-0xFFFFFFFF:8>
-;// <o4> Interrupt Mode <0x0-0xFFFFFFFF:8>
-;// <o5> User/System Mode <0x0-0xFFFFFFFF:8>
-;// </h>
-
-UND_Stack_Size EQU 0x00000000
-SVC_Stack_Size EQU 0x00000100
-ABT_Stack_Size EQU 0x00000000
-FIQ_Stack_Size EQU 0x00000000
-IRQ_Stack_Size EQU 0x00000100
-USR_Stack_Size EQU 0x00000100
-
-ISR_Stack_Size EQU (UND_Stack_Size + SVC_Stack_Size + ABT_Stack_Size + \
- FIQ_Stack_Size + IRQ_Stack_Size)
-
- AREA STACK, NOINIT, READWRITE, ALIGN=3
-
-Stack_Mem SPACE USR_Stack_Size
-__initial_sp SPACE ISR_Stack_Size
-Stack_Top
-
-
-;// <h> Heap Configuration
-;// <o> Heap Size (in Bytes) <0x0-0xFFFFFFFF>
-;// </h>
-
-Heap_Size EQU 0x00000000
-
- AREA HEAP, NOINIT, READWRITE, ALIGN=3
-__heap_base
-Heap_Mem SPACE Heap_Size
-__heap_limit
-
-
-;----------------------- Memory Definitions ------------------------------------
-
-; Internal Memory Base Addresses
-IRAM_BASE EQU 0x40000000
-
-
-;----------------------- Watchdog Timer Definitions ----------------------------
-
-WT_BASE EQU 0x53000000 ; Watchdog Timer Base Address
-WTCON_OFS EQU 0x00 ; Watchdog Timer Control Register Offset
-WTDAT_OFS EQU 0x04 ; Watchdog Timer Data Register Offset
-WTCNT_OFS EQU 0x08 ; Watchdog Timer Count Register Offset
-
-;// <e> Watchdog Timer Setup
-;// <h> Watchdog Timer Control Register (WTCON)
-;// <o1.8..15> Prescaler Value <0-255>
-;// <o1.5> Watchdog Timer Enable
-;// <o1.3..4> Clock Division Factor
-;// <0=> 16 <1=> 32 <2=> 64 <3=> 128
-;// <o1.2> Interrupt Generation Enable
-;// <o1.0> Reset Enable
-;// </h>
-;// <h> Watchdog Timer Data Register (WTDAT)
-;// <o2.0..15> Count Reload Value <0-65535>
-;// </h>
-;// </e> Watchdog Timer Setup
-WT_SETUP EQU 1
-WTCON_Val EQU 0x00000000
-WTDAT_Val EQU 0x00008000
-
-
-;----------------------- Clock and Power Management Definitions ----------------
-
-CLOCK_BASE EQU 0x4C000000 ; Clock Base Address
-LOCKTIME_OFS EQU 0x00 ; PLL Lock Time Count Register Offset
-MPLLCON_OFS EQU 0x04 ; MPLL Configuration Register Offset
-UPLLCON_OFS EQU 0x08 ; UPLL Configuration Register Offset
-CLKCON_OFS EQU 0x0C ; Clock Generator Control Reg Offset
-CLKSLOW_OFS EQU 0x10 ; Clock Slow Control Register Offset
-CLKDIVN_OFS EQU 0x14 ; Clock Divider Control Register Offset
-CAMDIVN_OFS EQU 0x18 ; Camera Clock Divider Register Offset
-
-;// <e> Clock Setup
-;// <h> PLL Lock Time Count Register (LOCKTIME)
-;// <o1.16..31> U_LTIME: UPLL Lock Time Count Value for UCLK <0x0-0xFFFF>
-;// <o1.0..15> M_LTIME: MPLL Lock Time Count Value for FCLK, HCLK and PCLK <0x0-0xFFFF>
-;// </h>
-;// <h> MPLL Configuration Register (MPLLCON)
-;// <i> MPLL = (2 * m * Fin) / (p * 2^s)
-;// <o2.12..19> m: Main Divider m Value <9-256><#-8>
-;// <i> m = MDIV + 8
-;// <o2.4..9> p: Pre-divider p Value <3-64><#-2>
-;// <i> p = PDIV + 2
-;// <o2.0..1> s: Post Divider s Value <0-3>
-;// <i> s = SDIV
-;// </h>
-;// <h> UPLL Configuration Register (UPLLCON)
-;// <i> UPLL = ( m * Fin) / (p * 2^s)
-;// <o3.12..19> m: Main Divider m Value <8-263><#-8>
-;// <i> m = MDIV + 8
-;// <o3.4..9> p: Pre-divider p Value <2-65><#-2>
-;// <i> p = PDIV + 2
-;// <o3.0..1> s: Post Divider s Value <0-3>
-;// <i> s = SDIV
-;// </h>
-;// <h> Clock Generation Control Register (CLKCON)
-;// <o4.20> AC97 Enable
-;// <o4.19> Camera Enable
-;// <o4.18> SPI Enable
-;// <o4.17> IIS Enable
-;// <o4.16> IIC Enable
-;// <o4.15> ADC + Touch Screen Enable
-;// <o4.14> RTC Enable
-;// <o4.13> GPIO Enable
-;// <o4.12> UART2 Enable
-;// <o4.11> UART1 Enable
-;// <o4.10> UART0 Enable
-;// <o4.9> SDI Enable
-;// <o4.8> PWMTIMER Enable
-;// <o4.7> USB Device Enable
-;// <o4.6> USB Host Enable
-;// <o4.5> LCDC Enable
-;// <o4.4> NAND FLASH Controller Enable
-;// <o4.3> SLEEP Enable
-;// <o4.2> IDLE BIT Enable
-;// </h>
-;// <h> Clock Slow Control Register (CLKSLOW)
-;// <o5.7> UCLK_ON: UCLK ON
-;// <o5.5> MPLL_OFF: Turn off PLL
-;// <o5.4> SLOW_BIT: Slow Mode Enable
-;// <o5.0..2> SLOW_VAL: Slow Clock Divider <0-7>
-;// </h>
-;// <h> Clock Divider Control Register (CLKDIVN)
-;// <o6.3> DIVN_UPLL: UCLK Select
-;// <0=> UCLK = UPLL clock
-;// <1=> UCLK = UPLL clock / 2
-;// <o6.1..2> HDIVN: HCLK Select
-;// <0=> HCLK = FCLK
-;// <1=> HCLK = FCLK / 2
-;// <2=> HCLK = FCLK / 4 if HCLK4_HALF = 0 in CAMDIVN, else HCLK = FCLK / 8
-;// <3=> HCLK = FCLK / 3 if HCLK3_HALF = 0 in CAMDIVN, else HCLK = FCLK / 6
-;// <o6.0> PDIVN: PCLK Select
-;// <0=> PCLK = HCLK
-;// <1=> PCLK = HCLK / 2
-;// </h>
-;// <h> Camera Clock Divider Control Register (CAMDIVN)
-;// <o7.12> DVS_EN: ARM Core Clock Select
-;// <0=> ARM core runs at FCLK
-;// <1=> ARM core runs at HCLK
-;// <o7.9> HCLK4_HALF: HDIVN Division Rate Change Bit
-;// <0=> If HDIVN = 2 in CLKDIVN then HCLK = FCLK / 4
-;// <1=> If HDIVN = 2 in CLKDIVN then HCLK = FCLK / 8
-;// <o7.8> HCLK3_HALF: HDIVN Division Rate Change Bit
-;// <0=> If HDIVN = 3 in CLKDIVN then HCLK = FCLK / 3
-;// <1=> If HDIVN = 3 in CLKDIVN then HCLK = FCLK / 6
-;// <o7.4> CAMCLK Select
-;// <0=> CAMCLK = UPLL
-;// <1=> CAMCLK = UPLL / CAMCLK_DIV
-;// <o7.0..3> CAMCLK_DIV: CAMCLK Divider <0-15>
-;// <i> Camera Clock = UPLL / (2 * (CAMCLK_DIV + 1))
-;// <i> Divider is used only if CAMCLK_SEL = 1
-;// </h>
-;// </e> Clock Setup
-CLOCK_SETUP EQU 0
-LOCKTIME_Val EQU 0x0FFF0FFF
-MPLLCON_Val EQU 0x00043011
-UPLLCON_Val EQU 0x00038021
-CLKCON_Val EQU 0x001FFFF0
-CLKSLOW_Val EQU 0x00000004
-CLKDIVN_Val EQU 0x0000000F
-CAMDIVN_Val EQU 0x00000000
-
-
-;----------------------- Memory Controller Definitions -------------------------
-
-MC_BASE EQU 0x48000000 ; Memory Controller Base Address
-BWSCON_OFS EQU 0x00 ; Bus Width and Wait Status Ctrl Offset
-BANKCON0_OFS EQU 0x04 ; Bank 0 Control Register Offset
-BANKCON1_OFS EQU 0x08 ; Bank 1 Control Register Offset
-BANKCON2_OFS EQU 0x0C ; Bank 2 Control Register Offset
-BANKCON3_OFS EQU 0x10 ; Bank 3 Control Register Offset
-BANKCON4_OFS EQU 0x14 ; Bank 4 Control Register Offset
-BANKCON5_OFS EQU 0x18 ; Bank 5 Control Register Offset
-BANKCON6_OFS EQU 0x1C ; Bank 6 Control Register Offset
-BANKCON7_OFS EQU 0x20 ; Bank 7 Control Register Offset
-REFRESH_OFS EQU 0x24 ; SDRAM Refresh Control Register Offset
-BANKSIZE_OFS EQU 0x28 ; Flexible Bank Size Register Offset
-MRSRB6_OFS EQU 0x2C ; Bank 6 Mode Register Offset
-MRSRB7_OFS EQU 0x30 ; Bank 7 Mode Register Offset
-
-;// <e> Memory Controller Setup
-;// <h> Bus Width and Wait Control Register (BWSCON)
-;// <o1.31> ST7: Use UB/LB for Bank 7
-;// <o1.30> WS7: Enable Wait Status for Bank 7
-;// <o1.28..29> DW7: Data Bus Width for Bank 7
-;// <0=> 8-bit <1=> 16-bit <2=> 32-bit <3=> Reserved
-;// <o1.27> ST6: Use UB/LB for Bank 6
-;// <o1.26> WS6: Enable Wait Status for Bank 6
-;// <o1.24..25> DW6: Data Bus Width for Bank 6
-;// <0=> 8-bit <1=> 16-bit <2=> 32-bit <3=> Reserved
-;// <o1.23> ST5: Use UB/LB for Bank 5
-;// <o1.22> WS5: Enable Wait Status for Bank 5
-;// <o1.20..21> DW5: Data Bus Width for Bank 5
-;// <0=> 8-bit <1=> 16-bit <2=> 32-bit <3=> Reserved
-;// <o1.19> ST4: Use UB/LB for Bank 4
-;// <o1.18> WS4: Enable Wait Status for Bank 4
-;// <o1.16..17> DW4: Data Bus Width for Bank 4
-;// <0=> 8-bit <1=> 16-bit <2=> 32-bit <3=> Reserved
-;// <o1.15> ST3: Use UB/LB for Bank 3
-;// <o1.14> WS3: Enable Wait Status for Bank 3
-;// <o1.12..13> DW3: Data Bus Width for Bank 3
-;// <0=> 8-bit <1=> 16-bit <2=> 32-bit <3=> Reserved
-;// <o1.11> ST2: Use UB/LB for Bank 2
-;// <o1.10> WS2: Enable Wait Status for Bank 2
-;// <o1.8..9> DW2: Data Bus Width for Bank 2
-;// <0=> 8-bit <1=> 16-bit <2=> 32-bit <3=> Reserved
-;// <o1.7> ST1: Use UB/LB for Bank 1
-;// <o1.6> WS1: Enable Wait Status for Bank 1
-;// <o1.4..5> DW1: Data Bus Width for Bank 1
-;// <0=> 8-bit <1=> 16-bit <2=> 32-bit <3=> Reserved
-;// <o1.1..2> DW0: Indicate Data Bus Width for Bank 0
-;// <1=> 16-bit <2=> 32-bit
-;// </h>
-;// <h> Bank 0 Control Register (BANKCON0)
-;// <o2.13..14> Tacs: Address Set-up Time before nGCS
-;// <0=> 0 clocks <1=> 1 clocks <2=> 2 clocks <3=> 4 clocks
-;// <o2.11..12> Tcos: Chip Selection Set-up Time before nOE
-;// <0=> 0 clocks <1=> 1 clocks <2=> 2 clocks <3=> 4 clocks
-;// <o2.8..10> Tacc: Access Cycle
-;// <0=> 1 clocks <1=> 2 clocks <2=> 3 clocks <3=> 4 clocks
-;// <4=> 6 clocks <5=> 8 clocks <6=> 10 clocks <7=> 14 clocks
-;// <o2.6..7> Tcoh: Chip Selection Hold Time after nOE
-;// <0=> 0 clocks <1=> 1 clocks <2=> 2 clocks <3=> 4 clocks
-;// <o2.4..5> Tcah: Address Hold Time after nGCS
-;// <0=> 0 clocks <1=> 1 clocks <2=> 2 clocks <3=> 4 clocks
-;// <o2.2..3> Tacp: Page Mode Access Cycle at Page Mode
-;// <0=> 2 clocks <1=> 3 clocks <2=> 4 clocks <3=> 6 clocks
-;// <o2.0..1> PMC: Page Mode Configuration
-;// <0=> normal (1 data) <1=> 4 data <2=> 8 data <3=> 16 data
-;// </h>
-;// <h> Bank 1 Control Register (BANKCON1)
-;// <o3.13..14> Tacs: Address Set-up Time before nGCS
-;// <0=> 0 clocks <1=> 1 clocks <2=> 2 clocks <3=> 4 clocks
-;// <o3.11..12> Tcos: Chip Selection Set-up Time before nOE
-;// <0=> 0 clocks <1=> 1 clocks <2=> 2 clocks <3=> 4 clocks
-;// <o3.8..10> Tacc: Access Cycle
-;// <0=> 1 clocks <1=> 2 clocks <2=> 3 clocks <3=> 4 clocks
-;// <4=> 6 clocks <5=> 8 clocks <6=> 10 clocks <7=> 14 clocks
-;// <o3.6..7> Tcoh: Chip Selection Hold Time after nOE
-;// <0=> 0 clocks <1=> 1 clocks <2=> 2 clocks <3=> 4 clocks
-;// <o3.4..5> Tcah: Address Hold Time after nGCS
-;// <0=> 0 clocks <1=> 1 clocks <2=> 2 clocks <3=> 4 clocks
-;// <o3.2..3> Tacp: Page Mode Access Cycle at Page Mode
-;// <0=> 2 clocks <1=> 3 clocks <2=> 4 clocks <3=> 6 clocks
-;// <o3.0..1> PMC: Page Mode Configuration
-;// <0=> normal (1 data) <1=> 4 data <2=> 8 data <3=> 16 data
-;// </h>
-;// <h> Bank 2 Control Register (BANKCON2)
-;// <o4.13..14> Tacs: Address Set-up Time before nGCS
-;// <0=> 0 clocks <1=> 1 clocks <2=> 2 clocks <3=> 4 clocks
-;// <o4.11..12> Tcos: Chip Selection Set-up Time before nOE
-;// <0=> 0 clocks <1=> 1 clocks <2=> 2 clocks <3=> 4 clocks
-;// <o4.8..10> Tacc: Access Cycle
-;// <0=> 1 clocks <1=> 2 clocks <2=> 3 clocks <3=> 4 clocks
-;// <4=> 6 clocks <5=> 8 clocks <6=> 10 clocks <7=> 14 clocks
-;// <o4.6..7> Tcoh: Chip Selection Hold Time after nOE
-;// <0=> 0 clocks <1=> 1 clocks <2=> 2 clocks <3=> 4 clocks
-;// <o4.4..5> Tcah: Address Hold Time after nGCS
-;// <0=> 0 clocks <1=> 1 clocks <2=> 2 clocks <3=> 4 clocks
-;// <o4.2..3> Tacp: Page Mode Access Cycle at Page Mode
-;// <0=> 2 clocks <1=> 3 clocks <2=> 4 clocks <3=> 6 clocks
-;// <o4.0..1> PMC: Page Mode Configuration
-;// <0=> normal (1 data) <1=> 4 data <2=> 8 data <3=> 16 data
-;// </h>
-;// <h> Bank 3 Control Register (BANKCON3)
-;// <o5.13..14> Tacs: Address Set-up Time before nGCS
-;// <0=> 0 clocks <1=> 1 clocks <2=> 2 clocks <3=> 4 clocks
-;// <o5.11..12> Tcos: Chip Selection Set-up Time before nOE
-;// <0=> 0 clocks <1=> 1 clocks <2=> 2 clocks <3=> 4 clocks
-;// <o5.8..10> Tacc: Access Cycle
-;// <0=> 1 clocks <1=> 2 clocks <2=> 3 clocks <3=> 4 clocks
-;// <4=> 6 clocks <5=> 8 clocks <6=> 10 clocks <7=> 14 clocks
-;// <o5.6..7> Tcoh: Chip Selection Hold Time after nOE
-;// <0=> 0 clocks <1=> 1 clocks <2=> 2 clocks <3=> 4 clocks
-;// <o5.4..5> Tcah: Address Hold Time after nGCS
-;// <0=> 0 clocks <1=> 1 clocks <2=> 2 clocks <3=> 4 clocks
-;// <o5.2..3> Tacp: Page Mode Access Cycle at Page Mode
-;// <0=> 2 clocks <1=> 3 clocks <2=> 4 clocks <3=> 6 clocks
-;// <o5.0..1> PMC: Page Mode Configuration
-;// <0=> normal (1 data) <1=> 4 data <2=> 8 data <3=> 16 data
-;// </h>
-;// <h> Bank 4 Control Register (BANKCON4)
-;// <o6.13..14> Tacs: Address Set-up Time before nGCS
-;// <0=> 0 clocks <1=> 1 clocks <2=> 2 clocks <3=> 4 clocks
-;// <o6.11..12> Tcos: Chip Selection Set-up Time before nOE
-;// <0=> 0 clocks <1=> 1 clocks <2=> 2 clocks <3=> 4 clocks
-;// <o6.8..10> Tacc: Access Cycle
-;// <0=> 1 clocks <1=> 2 clocks <2=> 3 clocks <3=> 4 clocks
-;// <4=> 6 clocks <5=> 8 clocks <6=> 10 clocks <7=> 14 clocks
-;// <o6.6..7> Tcoh: Chip Selection Hold Time after nOE
-;// <0=> 0 clocks <1=> 1 clocks <2=> 2 clocks <3=> 4 clocks
-;// <o6.4..5> Tcah: Address Hold Time after nGCS
-;// <0=> 0 clocks <1=> 1 clocks <2=> 2 clocks <3=> 4 clocks
-;// <o6.2..3> Tacp: Page Mode Access Cycle at Page Mode
-;// <0=> 2 clocks <1=> 3 clocks <2=> 4 clocks <3=> 6 clocks
-;// <o6.0..1> PMC: Page Mode Configuration
-;// <0=> normal (1 data) <1=> 4 data <2=> 8 data <3=> 16 data
-;// </h>
-;// <h> Bank 5 Control Register (BANKCON5)
-;// <o7.13..14> Tacs: Address Set-up Time before nGCS
-;// <0=> 0 clocks <1=> 1 clocks <2=> 2 clocks <3=> 4 clocks
-;// <o7.11..12> Tcos: Chip Selection Set-up Time before nOE
-;// <0=> 0 clocks <1=> 1 clocks <2=> 2 clocks <3=> 4 clocks
-;// <o7.8..10> Tacc: Access Cycle
-;// <0=> 1 clocks <1=> 2 clocks <2=> 3 clocks <3=> 4 clocks
-;// <4=> 6 clocks <5=> 8 clocks <6=> 10 clocks <7=> 14 clocks
-;// <o7.6..7> Tcoh: Chip Selection Hold Time after nOE
-;// <0=> 0 clocks <1=> 1 clocks <2=> 2 clocks <3=> 4 clocks
-;// <o7.4..5> Tcah: Address Hold Time after nGCS
-;// <0=> 0 clocks <1=> 1 clocks <2=> 2 clocks <3=> 4 clocks
-;// <o7.2..3> Tacp: Page Mode Access Cycle at Page Mode
-;// <0=> 2 clocks <1=> 3 clocks <2=> 4 clocks <3=> 6 clocks
-;// <o7.0..1> PMC: Page Mode Configuration
-;// <0=> normal (1 data) <1=> 4 data <2=> 8 data <3=> 16 data
-;// </h>
-;// <h> Bank 6 Control Register (BANKCON6)
-;// <o8.15..16> Memory Type Selection
-;// <0=> ROM or SRAM <3=> SDRAM
-;// <o8.13..14> Tacs: Address Set-up Time before nGCS
-;// <0=> 0 clocks <1=> 1 clocks <2=> 2 clocks <3=> 4 clocks
-;// <o8.11..12> Tcos: Chip Selection Set-up Time before nOE
-;// <0=> 0 clocks <1=> 1 clocks <2=> 2 clocks <3=> 4 clocks
-;// <o8.8..10> Tacc: Access Cycle
-;// <0=> 1 clocks <1=> 2 clocks <2=> 3 clocks <3=> 4 clocks
-;// <4=> 6 clocks <5=> 8 clocks <6=> 10 clocks <7=> 14 clocks
-;// <o8.6..7> Tcoh: Chip Selection Hold Time after nOE
-;// <0=> 0 clocks <1=> 1 clocks <2=> 2 clocks <3=> 4 clocks
-;// <o8.4..5> Tcah: Address Hold Time after nGCS
-;// <0=> 0 clocks <1=> 1 clocks <2=> 2 clocks <3=> 4 clocks
-;// <o8.2..3> Tacp/Trcd: Page Mode Access Cycle at Page Mode / RAS to CAS Delay
-;// <i> Parameter depends on Memory Type: if type SRAM then parameter is Tacp,
-;// <i> if type is SDRAM then parameter is Trcd
-;// <i> For SDRAM 6 cycles setting is not allowed
-;// <0=> 2 clocks <1=> 3 clocks <2=> 4 clocks <3=> 6 clocks
-;// <o8.0..1> PMC/SCAN: Page Mode Configuration / Column Address Number <0-3>
-;// <i> Parameter depends on Memory Type: if type SRAM then parameter is PMC,
-;// <i> if type is SDRAM then parameter is SCAN
-;// </h>
-;// <h> Bank 7 Control Register (BANKCON7)
-;// <o9.15..16> Memory Type Selection
-;// <0=> ROM or SRAM <3=> SDRAM
-;// <o9.13..14> Tacs: Address Set-up Time before nGCS
-;// <0=> 0 clocks <1=> 1 clocks <2=> 2 clocks <3=> 4 clocks
-;// <o9.11..12> Tcos: Chip Selection Set-up Time before nOE
-;// <0=> 0 clocks <1=> 1 clocks <2=> 2 clocks <3=> 4 clocks
-;// <o9.8..10> Tacc: Access Cycle
-;// <0=> 1 clocks <1=> 2 clocks <2=> 3 clocks <3=> 4 clocks
-;// <4=> 6 clocks <5=> 8 clocks <6=> 10 clocks <7=> 14 clocks
-;// <o9.6..7> Tcoh: Chip Selection Hold Time after nOE
-;// <0=> 0 clocks <1=> 1 clocks <2=> 2 clocks <3=> 4 clocks
-;// <o9.4..5> Tcah: Address Hold Time after nGCS
-;// <0=> 0 clocks <1=> 1 clocks <2=> 2 clocks <3=> 4 clocks
-;// <o9.2..3> Tacp/Trcd: Page Mode Access Cycle at Page Mode / RAS to CAS Delay
-;// <i> Parameter depends on Memory Type: if type SRAM then parameter is Tacp,
-;// <i> if type is SDRAM then parameter is Trcd
-;// <i> For SDRAM 6 cycles setting is not allowed
-;// <0=> 2 clocks <1=> 3 clocks <2=> 4 clocks <3=> 6 clocks
-;// <o9.0..1> PMC/SCAN: Page Mode Configuration / Column Address Number <0-3>
-;// <i> Parameter depends on Memory Type: if type SRAM then parameter is PMC,
-;// <i> if type is SDRAM then parameter is SCAN
-;// </h>
-;// <h> SDRAM Refresh Control Register (REFRESH)
-;// <o10.23> REFEN: SDRAM Refresh Enable
-;// <o10.22> TREFMD: SDRAM Refresh Mode
-;// <0=> CBR/Auto Refresh <1=> Self Refresh
-;// <o10.20..21> Trp: SDRAM RAS Pre-charge Time
-;// <0=> 2 clocks <1=> 3 clocks <2=> 4 clocks <3=> Reserved
-;// <o10.18..19> Tsrc: SDRAM Semi Row Cycle Time
-;// <i> SDRAM Row cycle time: Trc = Tsrc + Trp
-;// <0=> 4 clocks <1=> 5 clocks <2=> 6 clocks <3=> 7 clocks
-;// <o10.0..10> Refresh Counter <0-1023>
-;// <i> Refresh Period = (2048 - Refresh Count + 1) / HCLK
-;// </h>
-;// <h> Flexible Bank Size Register (BANKSIZE)
-;// <o11.7> BURST_EN: ARM Core Burst Operation Enable
-;// <o11.5> SCKE_EN: SDRAM Power Down Mode Enable
-;// <o11.4> SCLK_EN: SCLK Enabled During SDRAM Access Cycle
-;// <0=> SCLK is always active <1=> SCLK is active only during the access
-;// <o11.0..2> BK76MAP: BANK6 and BANK7 Memory Map
-;// <0=> 32MB / 32MB <1=> 64MB / 64MB <2=> 128MB / 128MB
-;// <4=> 2MB / 2MB <5=> 4MB / 4MB <6=> 8MB / 8MB <7=> 16MB / 16MB
-;// <o11.0..10> Refresh Counter <0-1023>
-;// <i> Refresh Period = (2048 - Refresh Count + 1) / HCLK
-;// </h>
-;// <h> SDRAM Mode Register Set Register 6 (MRSRB6)
-;// <o12.7> WBL: Write Burst Length
-;// <0=> Burst (Fixed)
-;// <o12.7..8> TM: Test Mode
-;// <0=> Mode register set (Fixed)
-;// <o12.4..6> CL: CAS Latency
-;// <0=> 1 clocks <1=> 2 clocks <2=> 3 clocks
-;// <o12.3> BT: Burst Type
-;// <0=> Sequential (Fixed)
-;// <o12.0..2> BL: Burst Length
-;// <0=> 1 (Fixed)
-;// </h>
-;// <h> SDRAM Mode Register Set Register 7 (MRSRB7)
-;// <o13.7> WBL: Write Burst Length
-;// <0=> Burst (Fixed)
-;// <o13.7..8> TM: Test Mode
-;// <0=> Mode register set (Fixed)
-;// <o13.4..6> CL: CAS Latency
-;// <0=> 1 clocks <1=> 2 clocks <2=> 3 clocks
-;// <o13.3> BT: Burst Type
-;// <0=> Sequential (Fixed)
-;// <o13.0..2> BL: Burst Length
-;// <0=> 1 (Fixed)
-;// </h>
-;// </e> Memory Controller Setup
-MC_SETUP EQU 0
-BWSCON_Val EQU 0x22000000
-BANKCON0_Val EQU 0x00000700
-BANKCON1_Val EQU 0x00000700
-BANKCON2_Val EQU 0x00000700
-BANKCON3_Val EQU 0x00000700
-BANKCON4_Val EQU 0x00000700
-BANKCON5_Val EQU 0x00000700
-BANKCON6_Val EQU 0x00018005
-BANKCON7_Val EQU 0x00018005
-REFRESH_Val EQU 0x008404F3
-BANKSIZE_Val EQU 0x00000032
-MRSRB6_Val EQU 0x00000020
-MRSRB7_Val EQU 0x00000020
-
-
-;----------------------- I/O Port Definitions ----------------------------------
-
-GPA_BASE EQU 0x56000000 ; GPA Base Address
-GPB_BASE EQU 0x56000010 ; GPB Base Address
-GPC_BASE EQU 0x56000020 ; GPC Base Address
-GPD_BASE EQU 0x56000030 ; GPD Base Address
-GPE_BASE EQU 0x56000040 ; GPE Base Address
-GPF_BASE EQU 0x56000050 ; GPF Base Address
-GPG_BASE EQU 0x56000060 ; GPG Base Address
-GPH_BASE EQU 0x56000070 ; GPH Base Address
-GPJ_BASE EQU 0x560000D0 ; GPJ Base Address
-GPCON_OFS EQU 0x00 ; Control Register Offset
-GPDAT_OFS EQU 0x04 ; Data Register Offset
-GPUP_OFS EQU 0x08 ; Pull-up Disable Register Offset
-
-;// <e> I/O Setup
-GP_SETUP EQU 1
-
-;// <e> Port A Settings
-;// <h> Port A Control Register (GPACON)
-;// <o1.22> GPA22 <0=> Output <1=> nFCE
-;// <o1.21> GPA21 <0=> Output <1=> nRSTOUT
-;// <o1.20> GPA20 <0=> Output <1=> nFRE
-;// <o1.19> GPA19 <0=> Output <1=> nFWE
-;// <o1.18> GPA18 <0=> Output <1=> ALE
-;// <o1.17> GPA17 <0=> Output <1=> CLE
-;// <o1.16> GPA16 <0=> Output <1=> nGCS[5]
-;// <o1.15> GPA15 <0=> Output <1=> nGCS[4]
-;// <o1.14> GPA14 <0=> Output <1=> nGCS[3]
-;// <o1.13> GPA13 <0=> Output <1=> nGCS[2]
-;// <o1.12> GPA12 <0=> Output <1=> nGCS[1]
-;// <o1.11> GPA11 <0=> Output <1=> ADDR26
-;// <o1.10> GPA10 <0=> Output <1=> ADDR25
-;// <o1.9> GPA9 <0=> Output <1=> ADDR24
-;// <o1.8> GPA8 <0=> Output <1=> ADDR23
-;// <o1.7> GPA7 <0=> Output <1=> ADDR22
-;// <o1.6> GPA6 <0=> Output <1=> ADDR21
-;// <o1.5> GPA5 <0=> Output <1=> ADDR20
-;// <o1.4> GPA4 <0=> Output <1=> ADDR19
-;// <o1.3> GPA3 <0=> Output <1=> ADDR18
-;// <o1.2> GPA2 <0=> Output <1=> ADDR17
-;// <o1.1> GPA1 <0=> Output <1=> ADDR16
-;// <o1.0> GPA0 <0=> Output <1=> ADDR0
-;// </h>
-;// </e>
-GPA_SETUP EQU 0
-GPACON_Val EQU 0x000003FF
-
-;// <e> Port B Settings
-;// <h> Port B Control Register (GPBCON)
-;// <o1.20..21> GPB10 <0=> Input <1=> Output <2=> nXDREQ0 <3=> Reserved
-;// <o1.18..19> GPB9 <0=> Input <1=> Output <2=> nXDACK0 <3=> Reserved
-;// <o1.16..17> GPB8 <0=> Input <1=> Output <2=> nXDREQ1 <3=> Reserved
-;// <o1.14..15> GPB7 <0=> Input <1=> Output <2=> nXDACK1 <3=> Reserved
-;// <o1.12..13> GPB6 <0=> Input <1=> Output <2=> nXBREQ <3=> Reserved
-;// <o1.10..11> GPB5 <0=> Input <1=> Output <2=> nXBACK <3=> Reserved
-;// <o1.8..9> GPB4 <0=> Input <1=> Output <2=> TCLK[0] <3=> Reserved
-;// <o1.6..7> GPB3 <0=> Input <1=> Output <2=> TOUT3 <3=> Reserved
-;// <o1.4..5> GPB2 <0=> Input <1=> Output <2=> TOUT2 <3=> Reserved
-;// <o1.2..3> GPB1 <0=> Input <1=> Output <2=> TOUT1 <3=> Reserved
-;// <o1.0..1> GPB0 <0=> Input <1=> Output <2=> TOUT0 <3=> Reserved
-;// </h>
-;// <h> Port B Pull-up Settings Register (GPBUP)
-;// <o2.10> GPB10 Pull-up Disable
-;// <o2.9> GPB9 Pull-up Disable
-;// <o2.8> GPB8 Pull-up Disable
-;// <o2.7> GPB7 Pull-up Disable
-;// <o2.6> GPB6 Pull-up Disable
-;// <o2.5> GPB5 Pull-up Disable
-;// <o2.4> GPB4 Pull-up Disable
-;// <o2.3> GPB3 Pull-up Disable
-;// <o2.2> GPB2 Pull-up Disable
-;// <o2.1> GPB1 Pull-up Disable
-;// <o2.0> GPB0 Pull-up Disable
-;// </h>
-;// </e>
-GPB_SETUP EQU 0
-GPBCON_Val EQU 0x00000000
-GPBUP_Val EQU 0x00000000
-
-;// <e> Port C Settings
-;// <h> Port C Control Register (GPCCON)
-;// <o1.30..31> GPC15 <0=> Input <1=> Output <2=> VD[7] <3=> Reserved
-;// <o1.28..29> GPC14 <0=> Input <1=> Output <2=> VD[6] <3=> Reserved
-;// <o1.26..27> GPC13 <0=> Input <1=> Output <2=> VD[5] <3=> Reserved
-;// <o1.24..25> GPC12 <0=> Input <1=> Output <2=> VD[4] <3=> Reserved
-;// <o1.22..23> GPC11 <0=> Input <1=> Output <2=> VD[3] <3=> Reserved
-;// <o1.20..21> GPC10 <0=> Input <1=> Output <2=> VD[2] <3=> Reserved
-;// <o1.18..19> GPC9 <0=> Input <1=> Output <2=> VD[1] <3=> Reserved
-;// <o1.16..17> GPC8 <0=> Input <1=> Output <2=> VD[0] <3=> Reserved
-;// <o1.14..15> GPC7 <0=> Input <1=> Output <2=> LCD_LPCREVB <3=> Reserved
-;// <o1.12..13> GPC6 <0=> Input <1=> Output <2=> LCD_LPCREV <3=> Reserved
-;// <o1.10..11> GPC5 <0=> Input <1=> Output <2=> LCD_LPCOE <3=> Reserved
-;// <o1.8..9> GPC4 <0=> Input <1=> Output <2=> VM <3=> I2SSDI
-;// <o1.6..7> GPC3 <0=> Input <1=> Output <2=> VFRAME <3=> Reserved
-;// <o1.4..5> GPC2 <0=> Input <1=> Output <2=> VLINE <3=> Reserved
-;// <o1.2..3> GPC1 <0=> Input <1=> Output <2=> VCLK <3=> Reserved
-;// <o1.0..1> GPC0 <0=> Input <1=> Output <2=> LEND <3=> Reserved
-;// </h>
-;// <h> Port C Pull-up Settings Register (GPCUP)
-;// <o2.15> GPC15 Pull-up Disable
-;// <o2.14> GPC14 Pull-up Disable
-;// <o2.13> GPC13 Pull-up Disable
-;// <o2.12> GPC12 Pull-up Disable
-;// <o2.11> GPC11 Pull-up Disable
-;// <o2.10> GPC10 Pull-up Disable
-;// <o2.9> GPC9 Pull-up Disable
-;// <o2.8> GPC8 Pull-up Disable
-;// <o2.7> GPC7 Pull-up Disable
-;// <o2.6> GPC6 Pull-up Disable
-;// <o2.5> GPC5 Pull-up Disable
-;// <o2.4> GPC4 Pull-up Disable
-;// <o2.3> GPC3 Pull-up Disable
-;// <o2.2> GPC2 Pull-up Disable
-;// <o2.1> GPC1 Pull-up Disable
-;// <o2.0> GPC0 Pull-up Disable
-;// </h>
-;// </e>
-GPC_SETUP EQU 0
-GPCCON_Val EQU 0x00000000
-GPCUP_Val EQU 0x00000000
-
-;// <e> Port D Settings
-;// <h> Port D Control Register (GPDCON)
-;// <o1.30..31> GPD15 <0=> Input <1=> Output <2=> VD[23] <3=> nSS0
-;// <o1.28..29> GPD14 <0=> Input <1=> Output <2=> VD[22] <3=> nSS1
-;// <o1.26..27> GPD13 <0=> Input <1=> Output <2=> VD[21] <3=> Reserved
-;// <o1.24..25> GPD12 <0=> Input <1=> Output <2=> VD[20] <3=> Reserved
-;// <o1.22..23> GPD11 <0=> Input <1=> Output <2=> VD[19] <3=> Reserved
-;// <o1.20..21> GPD10 <0=> Input <1=> Output <2=> VD[18] <3=> SPICLK1
-;// <o1.18..19> GPD9 <0=> Input <1=> Output <2=> VD[17] <3=> SPIMOSI1
-;// <o1.16..17> GPD8 <0=> Input <1=> Output <2=> VD[16] <3=> SPIMISO1
-;// <o1.14..15> GPD7 <0=> Input <1=> Output <2=> VD[15] <3=> Reserved
-;// <o1.12..13> GPD6 <0=> Input <1=> Output <2=> VD[14] <3=> Reserved
-;// <o1.10..11> GPD5 <0=> Input <1=> Output <2=> VD[13] <3=> Reserved
-;// <o1.8..9> GPD4 <0=> Input <1=> Output <2=> VD[12] <3=> Reserved
-;// <o1.6..7> GPD3 <0=> Input <1=> Output <2=> VD[11] <3=> Reserved
-;// <o1.4..5> GPD2 <0=> Input <1=> Output <2=> VD[10] <3=> Reserved
-;// <o1.2..3> GPD1 <0=> Input <1=> Output <2=> VD[9] <3=> Reserved
-;// <o1.0..1> GPD0 <0=> Input <1=> Output <2=> VD[8] <3=> Reserved
-;// </h>
-;// <h> Port D Pull-up Settings Register (GPDUP)
-;// <o2.15> GPD15 Pull-up Disable
-;// <o2.14> GPD14 Pull-up Disable
-;// <o2.13> GPD13 Pull-up Disable
-;// <o2.12> GPD12 Pull-up Disable
-;// <o2.11> GPD11 Pull-up Disable
-;// <o2.10> GPD10 Pull-up Disable
-;// <o2.9> GPD9 Pull-up Disable
-;// <o2.8> GPD8 Pull-up Disable
-;// <o2.7> GPD7 Pull-up Disable
-;// <o2.6> GPD6 Pull-up Disable
-;// <o2.5> GPD5 Pull-up Disable
-;// <o2.4> GPD4 Pull-up Disable
-;// <o2.3> GPD3 Pull-up Disable
-;// <o2.2> GPD2 Pull-up Disable
-;// <o2.1> GPD1 Pull-up Disable
-;// <o2.0> GPD0 Pull-up Disable
-;// </h>
-;// </e>
-GPD_SETUP EQU 0
-GPDCON_Val EQU 0x00000000
-GPDUP_Val EQU 0x00000000
-
-;// <e> Port E Settings
-;// <h> Port E Control Register (GPECON)
-;// <o1.30..31> GPE15 <0=> Input <1=> Output <2=> IICSDA <3=> Reserved
-;// <i> This pad is open-drain, and has no pull-up option.
-;// <o1.28..29> GPE14 <0=> Input <1=> Output <2=> IICSCL <3=> Reserved
-;// <i> This pad is open-drain, and has no pull-up option.
-;// <o1.26..27> GPE13 <0=> Input <1=> Output <2=> SPICLK0 <3=> Reserved
-;// <o1.24..25> GPE12 <0=> Input <1=> Output <2=> SPIMOSI0 <3=> Reserved
-;// <o1.22..23> GPE11 <0=> Input <1=> Output <2=> SPIMISO0 <3=> Reserved
-;// <o1.20..21> GPE10 <0=> Input <1=> Output <2=> SDDAT3 <3=> Reserved
-;// <o1.18..19> GPE9 <0=> Input <1=> Output <2=> SDDAT2 <3=> Reserved
-;// <o1.16..17> GPE8 <0=> Input <1=> Output <2=> SDDAT1 <3=> Reserved
-;// <o1.14..15> GPE7 <0=> Input <1=> Output <2=> SDDAT0 <3=> Reserved
-;// <o1.12..13> GPE6 <0=> Input <1=> Output <2=> SDCMD <3=> Reserved
-;// <o1.10..11> GPE5 <0=> Input <1=> Output <2=> SDCLK <3=> Reserved
-;// <o1.8..9> GPE4 <0=> Input <1=> Output <2=> I2SDO <3=> AC_SDATA_OUT
-;// <o1.6..7> GPE3 <0=> Input <1=> Output <2=> I2SDI <3=> AC_SDATA_IN
-;// <o1.4..5> GPE2 <0=> Input <1=> Output <2=> CDCLK <3=> AC_nRESET
-;// <o1.2..3> GPE1 <0=> Input <1=> Output <2=> I2SSCLK <3=> AC_BIT_CLK
-;// <o1.0..1> GPE0 <0=> Input <1=> Output <2=> I2SLRCK <3=> AC_SYNC
-;// </h>
-;// <h> Port E Pull-up Settings Register (GPEUP)
-;// <o2.13> GPE13 Pull-up Disable
-;// <o2.12> GPE12 Pull-up Disable
-;// <o2.11> GPE11 Pull-up Disable
-;// <o2.10> GPE10 Pull-up Disable
-;// <o2.9> GPE9 Pull-up Disable
-;// <o2.8> GPE8 Pull-up Disable
-;// <o2.7> GPE7 Pull-up Disable
-;// <o2.6> GPE6 Pull-up Disable
-;// <o2.5> GPE5 Pull-up Disable
-;// <o2.4> GPE4 Pull-up Disable
-;// <o2.3> GPE3 Pull-up Disable
-;// <o2.2> GPE2 Pull-up Disable
-;// <o2.1> GPE1 Pull-up Disable
-;// <o2.0> GPE0 Pull-up Disable
-;// </h>
-;// </e>
-GPE_SETUP EQU 0
-GPECON_Val EQU 0x00000000
-GPEUP_Val EQU 0x00000000
-
-;// <e> Port F Settings
-;// <h> Port F Control Register (GPFCON)
-;// <o1.14..15> GPF7 <0=> Input <1=> Output <2=> EINT[7] <3=> Reserved
-;// <o1.12..13> GPF6 <0=> Input <1=> Output <2=> EINT[6] <3=> Reserved
-;// <o1.10..11> GPF5 <0=> Input <1=> Output <2=> EINT[5] <3=> Reserved
-;// <o1.8..9> GPF4 <0=> Input <1=> Output <2=> EINT[4] <3=> Reserved
-;// <o1.6..7> GPF3 <0=> Input <1=> Output <2=> EINT[3] <3=> Reserved
-;// <o1.4..5> GPF2 <0=> Input <1=> Output <2=> EINT[2] <3=> Reserved
-;// <o1.2..3> GPF1 <0=> Input <1=> Output <2=> EINT[1] <3=> Reserved
-;// <o1.0..1> GPF0 <0=> Input <1=> Output <2=> EINT[0] <3=> Reserved
-;// </h>
-;// <h> Port F Pull-up Settings Register (GPFUP)
-;// <o2.7> GPF7 Pull-up Disable
-;// <o2.6> GPF6 Pull-up Disable
-;// <o2.5> GPF5 Pull-up Disable
-;// <o2.4> GPF4 Pull-up Disable
-;// <o2.3> GPF3 Pull-up Disable
-;// <o2.2> GPF2 Pull-up Disable
-;// <o2.1> GPF1 Pull-up Disable
-;// <o2.0> GPF0 Pull-up Disable
-;// </h>
-;// </e>
-GPF_SETUP EQU 1
-GPFCON_Val EQU 0x000000AA
-GPFUP_Val EQU 0x0000000F
-
-;// <e> Port G Settings
-;// <h> Port G Control Register (GPGCON)
-;// <o1.30..31> GPG15 <0=> Input <1=> Output <2=> EINT[23] <3=> Reserved
-;// <o1.28..29> GPG14 <0=> Input <1=> Output <2=> EINT[22] <3=> Reserved
-;// <o1.26..27> GPG13 <0=> Input <1=> Output <2=> EINT[21] <3=> Reserved
-;// <o1.24..25> GPG12 <0=> Input <1=> Output <2=> EINT[20] <3=> Reserved
-;// <o1.22..23> GPG11 <0=> Input <1=> Output <2=> EINT[19] <3=> TCLK[1]
-;// <o1.20..21> GPG10 <0=> Input <1=> Output <2=> EINT[18] <3=> nCTS1
-;// <o1.18..19> GPG9 <0=> Input <1=> Output <2=> EINT[17] <3=> nRTS1
-;// <o1.16..17> GPG8 <0=> Input <1=> Output <2=> EINT[16] <3=> Reserved
-;// <o1.14..15> GPG7 <0=> Input <1=> Output <2=> EINT[15] <3=> SPICLK1
-;// <o1.12..13> GPG6 <0=> Input <1=> Output <2=> EINT[14] <3=> SPIMOSI1
-;// <o1.10..11> GPG5 <0=> Input <1=> Output <2=> EINT[13] <3=> SPIMISO1
-;// <o1.8..9> GPG4 <0=> Input <1=> Output <2=> EINT[12] <3=> LCD_PWRDN
-;// <o1.6..7> GPG3 <0=> Input <1=> Output <2=> EINT[11] <3=> nSS1
-;// <o1.4..5> GPG2 <0=> Input <1=> Output <2=> EINT[10] <3=> nSS0
-;// <o1.2..3> GPG1 <0=> Input <1=> Output <2=> EINT[9] <3=> Reserved
-;// <o1.0..1> GPG0 <0=> Input <1=> Output <2=> EINT[8] <3=> Reserved
-;// </h>
-;// <h> Port G Pull-up Settings Register (GPGUP)
-;// <o2.15> GPG15 Pull-up Disable
-;// <o2.14> GPG14 Pull-up Disable
-;// <o2.13> GPG13 Pull-up Disable
-;// <o2.12> GPG12 Pull-up Disable
-;// <o2.11> GPG11 Pull-up Disable
-;// <o2.10> GPG10 Pull-up Disable
-;// <o2.9> GPG9 Pull-up Disable
-;// <o2.8> GPG8 Pull-up Disable
-;// <o2.7> GPG7 Pull-up Disable
-;// <o2.6> GPG6 Pull-up Disable
-;// <o2.5> GPG5 Pull-up Disable
-;// <o2.4> GPG4 Pull-up Disable
-;// <o2.3> GPG3 Pull-up Disable
-;// <o2.2> GPG2 Pull-up Disable
-;// <o2.1> GPG1 Pull-up Disable
-;// <o2.0> GPG0 Pull-up Disable
-;// </h>
-;// </e>
-GPG_SETUP EQU 0
-GPGCON_Val EQU 0x00000000
-GPGUP_Val EQU 0x00000000
-
-;// <e> Port H Settings
-;// <h> Port H Control Register (GPHCON)
-;// <o1.20..21> GPH10 <0=> Input <1=> Output <2=> CLKOUT1 <3=> Reserved
-;// <o1.18..19> GPH9 <0=> Input <1=> Output <2=> CLKOUT0 <3=> Reserved
-;// <o1.16..17> GPH8 <0=> Input <1=> Output <2=> UEXTCLK <3=> Reserved
-;// <o1.14..15> GPH7 <0=> Input <1=> Output <2=> RXD[2] <3=> nCTS1
-;// <o1.12..13> GPH6 <0=> Input <1=> Output <2=> TXD[2] <3=> nRTS1
-;// <o1.10..11> GPH5 <0=> Input <1=> Output <2=> RXD[1] <3=> Reserved
-;// <o1.8..9> GPH4 <0=> Input <1=> Output <2=> TXD[1] <3=> Reserved
-;// <o1.6..7> GPH3 <0=> Input <1=> Output <2=> RXD[0] <3=> Reserved
-;// <o1.4..5> GPH2 <0=> Input <1=> Output <2=> TXD[0] <3=> Reserved
-;// <o1.2..3> GPH1 <0=> Input <1=> Output <2=> nRTS0 <3=> Reserved
-;// <o1.0..1> GPH0 <0=> Input <1=> Output <2=> nCTS0 <3=> Reserved
-;// </h>
-;// <h> Port H Pull-up Settings Register (GPHUP)
-;// <o2.10> GPH10 Pull-up Disable
-;// <o2.9> GPH9 Pull-up Disable
-;// <o2.8> GPH8 Pull-up Disable
-;// <o2.7> GPH7 Pull-up Disable
-;// <o2.6> GPH6 Pull-up Disable
-;// <o2.5> GPH5 Pull-up Disable
-;// <o2.4> GPH4 Pull-up Disable
-;// <o2.3> GPH3 Pull-up Disable
-;// <o2.2> GPH2 Pull-up Disable
-;// <o2.1> GPH1 Pull-up Disable
-;// <o2.0> GPH0 Pull-up Disable
-;// </h>
-;// </e>
-GPH_SETUP EQU 0
-GPHCON_Val EQU 0x00000000
-GPHUP_Val EQU 0x00000000
-
-;// <e> Port J Settings
-;// <h> Port J Control Register (GPJCON)
-;// <o1.24..25> GPJ12 <0=> Input <1=> Output <2=> CAMRESET <3=> Reserved
-;// <o1.22..23> GPJ11 <0=> Input <1=> Output <2=> CAMCLKOUT <3=> Reserved
-;// <o1.20..21> GPJ10 <0=> Input <1=> Output <2=> CAMHREF <3=> Reserved
-;// <o1.18..19> GPJ9 <0=> Input <1=> Output <2=> CAMVSYNC <3=> Reserved
-;// <o1.16..17> GPJ8 <0=> Input <1=> Output <2=> CAMPCLK <3=> Reserved
-;// <o1.14..15> GPJ7 <0=> Input <1=> Output <2=> CAMDATA[7] <3=> Reserved
-;// <o1.12..13> GPJ6 <0=> Input <1=> Output <2=> CAMDATA[6] <3=> Reserved
-;// <o1.10..11> GPJ5 <0=> Input <1=> Output <2=> CAMDATA[5] <3=> Reserved
-;// <o1.8..9> GPJ4 <0=> Input <1=> Output <2=> CAMDATA[4] <3=> Reserved
-;// <o1.6..7> GPJ3 <0=> Input <1=> Output <2=> CAMDATA[3] <3=> Reserved
-;// <o1.4..5> GPJ2 <0=> Input <1=> Output <2=> CAMDATA[2] <3=> Reserved
-;// <o1.2..3> GPJ1 <0=> Input <1=> Output <2=> CAMDATA[1] <3=> Reserved
-;// <o1.0..1> GPJ0 <0=> Input <1=> Output <2=> CAMDATA[0] <3=> Reserved
-;// </h>
-;// <h> Port J Pull-up Settings Register (GPJUP)
-;// <o2.12> GPJ12 Pull-up Disable
-;// <o2.11> GPJ11 Pull-up Disable
-;// <o2.10> GPJ10 Pull-up Disable
-;// <o2.9> GPJ9 Pull-up Disable
-;// <o2.8> GPJ8 Pull-up Disable
-;// <o2.7> GPJ7 Pull-up Disable
-;// <o2.6> GPJ6 Pull-up Disable
-;// <o2.5> GPJ5 Pull-up Disable
-;// <o2.4> GPJ4 Pull-up Disable
-;// <o2.3> GPJ3 Pull-up Disable
-;// <o2.2> GPJ2 Pull-up Disable
-;// <o2.1> GPJ1 Pull-up Disable
-;// <o2.0> GPJ0 Pull-up Disable
-;// </h>
-;// </e>
-GPJ_SETUP EQU 0
-GPJCON_Val EQU 0x00000000
-GPJUP_Val EQU 0x00000000
-
-;// </e> I/O Setup
-
-
-;----------------------- CODE --------------------------------------------------
-
- PRESERVE8
-
-
-; Area Definition and Entry Point
-; Startup Code must be linked first at Address at which it expects to run.
-
- AREA RESET, CODE, READONLY
- ARM
-
-; Exception Vectors
-; Mapped to Address 0.
-; Absolute addressing mode must be used.
-; Dummy Handlers are implemented as infinite loops which can be modified.
-
- EXPORT Entry_Point
-Entry_Point
-Vectors LDR PC, Reset_Addr
- LDR PC, Undef_Addr
- LDR PC, SWI_Addr
- LDR PC, PAbt_Addr
- LDR PC, DAbt_Addr
- NOP
- LDR PC, IRQ_Addr
- LDR PC, FIQ_Addr
-
-Reset_Addr DCD Reset_Handler
-Undef_Addr DCD Undef_Handler
-SWI_Addr DCD SWI_Handler
-PAbt_Addr DCD PAbt_Handler
-DAbt_Addr DCD DAbt_Handler
- DCD 0 ; Reserved Address
-IRQ_Addr DCD IRQ_Handler
-FIQ_Addr DCD FIQ_Handler
-
-Undef_Handler B Undef_Handler
-SWI_Handler B SWI_Handler
-PAbt_Handler B PAbt_Handler
-;DAbt_Handler B DAbt_Handler
-FIQ_Handler B FIQ_Handler
-
-;*
-;*************************************************************************
-;*
-;* Interrupt handling
-;*
-;*************************************************************************
-;*
-; DAbt Handler
-DAbt_Handler
- IMPORT rt_hw_trap_dabt
-
- sub sp, sp, #72
- stmia sp, {r0 - r12} ;/* Calling r0-r12 */
- add r8, sp, #60
- stmdb r8, {sp, lr} ;/* Calling SP, LR */
- str lr, [r8, #0] ;/* Save calling PC */
- mrs r6, spsr
- str r6, [r8, #4] ;/* Save CPSR */
- str r0, [r8, #8] ;/* Save OLD_R0 */
- mov r0, sp
-
- bl rt_hw_trap_dabt
-
-
-;##########################################
-; Reset Handler
-
- EXPORT Reset_Handler
-Reset_Handler
-
-
-; Watchdog Setup ---------------------------------------------------------------
-
- IF WT_SETUP != 0
- LDR R0, =WT_BASE
- LDR R1, =WTCON_Val
- LDR R2, =WTDAT_Val
- STR R2, [R0, #WTCNT_OFS]
- STR R2, [R0, #WTDAT_OFS]
- STR R1, [R0, #WTCON_OFS]
- ENDIF
-
-
-; Clock Setup ------------------------------------------------------------------
-
- IF (:LNOT:(:DEF:NO_CLOCK_SETUP)):LAND:(CLOCK_SETUP != 0)
- LDR R0, =CLOCK_BASE
- LDR R1, =LOCKTIME_Val
- STR R1, [R0, #LOCKTIME_OFS]
- MOV R1, #CLKDIVN_Val
- STR R1, [R0, #CLKDIVN_OFS]
- LDR R1, =CAMDIVN_Val
- STR R1, [R0, #CAMDIVN_OFS]
- LDR R1, =MPLLCON_Val
- STR R1, [R0, #MPLLCON_OFS]
- LDR R1, =UPLLCON_Val
- STR R1, [R0, #UPLLCON_OFS]
- MOV R1, #CLKSLOW_Val
- STR R1, [R0, #CLKSLOW_OFS]
- LDR R1, =CLKCON_Val
- STR R1, [R0, #CLKCON_OFS]
- ENDIF
-
-
-; Memory Controller Setup ------------------------------------------------------
-
- IF (:LNOT:(:DEF:NO_MC_SETUP)):LAND:(CLOCK_SETUP != 0)
- LDR R0, =MC_BASE
- LDR R1, =BWSCON_Val
- STR R1, [R0, #BWSCON_OFS]
- LDR R1, =BANKCON0_Val
- STR R1, [R0, #BANKCON0_OFS]
- LDR R1, =BANKCON1_Val
- STR R1, [R0, #BANKCON1_OFS]
- LDR R1, =BANKCON2_Val
- STR R1, [R0, #BANKCON2_OFS]
- LDR R1, =BANKCON3_Val
- STR R1, [R0, #BANKCON3_OFS]
- LDR R1, =BANKCON4_Val
- STR R1, [R0, #BANKCON4_OFS]
- LDR R1, =BANKCON5_Val
- STR R1, [R0, #BANKCON5_OFS]
- LDR R1, =BANKCON6_Val
- STR R1, [R0, #BANKCON6_OFS]
- LDR R1, =BANKCON7_Val
- STR R1, [R0, #BANKCON7_OFS]
- LDR R1, =REFRESH_Val
- STR R1, [R0, #REFRESH_OFS]
- MOV R1, #BANKSIZE_Val
- STR R1, [R0, #BANKSIZE_OFS]
- MOV R1, #MRSRB6_Val
- STR R1, [R0, #MRSRB6_OFS]
- MOV R1, #MRSRB7_Val
- STR R1, [R0, #MRSRB7_OFS]
- ENDIF
-
-
-; I/O Pins Setup ---------------------------------------------------------------
-
- IF (:LNOT:(:DEF:NO_GP_SETUP)):LAND:(GP_SETUP != 0)
-
- IF GPA_SETUP != 0
- LDR R0, =GPA_BASE
- LDR R1, =GPACON_Val
- STR R1, [R0, #GPCON_OFS]
- ENDIF
-
- IF GPB_SETUP != 0
- LDR R0, =GPB_BASE
- LDR R1, =GPBCON_Val
- STR R1, [R0, #GPCON_OFS]
- LDR R1, =GPBUP_Val
- STR R1, [R0, #GPUP_OFS]
- ENDIF
-
- IF GPC_SETUP != 0
- LDR R0, =GPC_BASE
- LDR R1, =GPCCON_Val
- STR R1, [R0, #GPCON_OFS]
- LDR R1, =GPCUP_Val
- STR R1, [R0, #GPUP_OFS]
- ENDIF
-
- IF GPD_SETUP != 0
- LDR R0, =GPD_BASE
- LDR R1, =GPDCON_Val
- STR R1, [R0, #GPCON_OFS]
- LDR R1, =GPDUP_Val
- STR R1, [R0, #GPUP_OFS]
- ENDIF
-
- IF GPE_SETUP != 0
- LDR R0, =GPE_BASE
- LDR R1, =GPECON_Val
- STR R1, [R0, #GPCON_OFS]
- LDR R1, =GPEUP_Val
- STR R1, [R0, #GPUP_OFS]
- ENDIF
-
- IF GPF_SETUP != 0
- LDR R0, =GPF_BASE
- LDR R1, =GPFCON_Val
- STR R1, [R0, #GPCON_OFS]
- LDR R1, =GPFUP_Val
- STR R1, [R0, #GPUP_OFS]
- ENDIF
-
- IF GPG_SETUP != 0
- LDR R0, =GPG_BASE
- LDR R1, =GPGCON_Val
- STR R1, [R0, #GPCON_OFS]
- LDR R1, =GPGUP_Val
- STR R1, [R0, #GPUP_OFS]
- ENDIF
-
- IF GPH_SETUP != 0
- LDR R0, =GPH_BASE
- LDR R1, =GPHCON_Val
- STR R1, [R0, #GPCON_OFS]
- LDR R1, =GPHUP_Val
- STR R1, [R0, #GPUP_OFS]
- ENDIF
-
- IF GPJ_SETUP != 0
- LDR R0, =GPJ_BASE
- LDR R1, =GPJCON_Val
- STR R1, [R0, #GPCON_OFS]
- LDR R1, =GPJUP_Val
- STR R1, [R0, #GPUP_OFS]
- ENDIF
-
- ENDIF
-
-
-; Copy Exception Vectors to Internal RAM ---------------------------------------
-
- IF :DEF:RAM_INTVEC
- ADR R8, Vectors ; Source
- LDR R9, =IRAM_BASE ; Destination
- LDMIA R8!, {R0-R7} ; Load Vectors
- STMIA R9!, {R0-R7} ; Store Vectors
- LDMIA R8!, {R0-R7} ; Load Handler Addresses
- STMIA R9!, {R0-R7} ; Store Handler Addresses
- ENDIF
-
-
-; Setup Stack for each mode ----------------------------------------------------
-
- LDR R0, =Stack_Top
-
-; Enter Undefined Instruction Mode and set its Stack Pointer
- MSR CPSR_c, #Mode_UND:OR:I_Bit:OR:F_Bit
- MOV SP, R0
- SUB R0, R0, #UND_Stack_Size
-
-; Enter Abort Mode and set its Stack Pointer
- MSR CPSR_c, #Mode_ABT:OR:I_Bit:OR:F_Bit
- MOV SP, R0
- SUB R0, R0, #ABT_Stack_Size
-
-; Enter FIQ Mode and set its Stack Pointer
- MSR CPSR_c, #Mode_FIQ:OR:I_Bit:OR:F_Bit
- MOV SP, R0
- SUB R0, R0, #FIQ_Stack_Size
-
-; Enter IRQ Mode and set its Stack Pointer
- MSR CPSR_c, #Mode_IRQ:OR:I_Bit:OR:F_Bit
- MOV SP, R0
- SUB R0, R0, #IRQ_Stack_Size
-
-; Enter Supervisor Mode and set its Stack Pointer
- MSR CPSR_c, #Mode_SVC:OR:I_Bit:OR:F_Bit
- MOV SP, R0
- SUB R0, R0, #SVC_Stack_Size
-
-; Enter User Mode and set its Stack Pointer
- ; MSR CPSR_c, #Mode_USR
- MOV SP, R0
- SUB SL, SP, #USR_Stack_Size
-
-; Enter the C code -------------------------------------------------------------
-
- IMPORT __main
- LDR R0, =__main
- BX R0
-
- IMPORT rt_interrupt_enter
- IMPORT rt_interrupt_leave
- IMPORT rt_thread_switch_interrupt_flag
- IMPORT rt_interrupt_from_thread
- IMPORT rt_interrupt_to_thread
- IMPORT rt_hw_trap_irq
-
-IRQ_Handler PROC
- EXPORT IRQ_Handler
- STMFD sp!, {r0-r12,lr}
- BL rt_interrupt_enter
- BL rt_hw_trap_irq
- BL rt_interrupt_leave
-
- ; if rt_thread_switch_interrupt_flag set, jump to
- ; rt_hw_context_switch_interrupt_do and don't return
- LDR r0, =rt_thread_switch_interrupt_flag
- LDR r1, [r0]
- CMP r1, #1
- BEQ rt_hw_context_switch_interrupt_do
-
- LDMFD sp!, {r0-r12,lr}
- SUBS pc, lr, #4
- ENDP
-
-; /*
-; * void rt_hw_context_switch_interrupt_do(rt_base_t flag)
-; */
-rt_hw_context_switch_interrupt_do PROC
- EXPORT rt_hw_context_switch_interrupt_do
- MOV r1, #0 ; clear flag
- STR r1, [r0]
-
- LDMFD sp!, {r0-r12,lr}; reload saved registers
- STMFD sp!, {r0-r3} ; save r0-r3
- MOV r1, sp
- ADD sp, sp, #16 ; restore sp
- SUB r2, lr, #4 ; save old task's pc to r2
-
- MRS r3, spsr ; get cpsr of interrupt thread
-
- ; switch to SVC mode and no interrupt
- MSR cpsr_c, #I_Bit:OR:F_Bit:OR:Mode_SVC
-
- STMFD sp!, {r2} ; push old task's pc
- STMFD sp!, {r4-r12,lr}; push old task's lr,r12-r4
- MOV r4, r1 ; Special optimised code below
- MOV r5, r3
- LDMFD r4!, {r0-r3}
- STMFD sp!, {r0-r3} ; push old task's r3-r0
- STMFD sp!, {r5} ; push old task's cpsr
- MRS r4, spsr
- STMFD sp!, {r4} ; push old task's spsr
-
- LDR r4, =rt_interrupt_from_thread
- LDR r5, [r4]
- STR sp, [r5] ; store sp in preempted tasks's TCB
-
- LDR r6, =rt_interrupt_to_thread
- LDR r6, [r6]
- LDR sp, [r6] ; get new task's stack pointer
-
- LDMFD sp!, {r4} ; pop new task's spsr
- MSR spsr_cxsf, r4
- LDMFD sp!, {r4} ; pop new task's psr
- MSR cpsr_cxsf, r4
-
- LDMFD sp!, {r0-r12,lr,pc} ; pop new task's r0-r12,lr & pc
- ENDP
-
- IF :DEF:__MICROLIB
-
- EXPORT __heap_base
- EXPORT __heap_limit
-
- ELSE
-; User Initial Stack & Heap
- AREA |.text|, CODE, READONLY
-
- IMPORT __use_two_region_memory
- EXPORT __user_initial_stackheap
-__user_initial_stackheap
-
- LDR R0, = Heap_Mem
- LDR R1, =(Stack_Mem + USR_Stack_Size)
- LDR R2, = (Heap_Mem + Heap_Size)
- LDR R3, = Stack_Mem
- BX LR
- ENDIF
-
-
- END
-
+;/*****************************************************************************/ +;/* S3C2440.S: Startup file for Samsung S3C440 */ +;/*****************************************************************************/ +;/* <<< Use Configuration Wizard in Context Menu >>> */ +;/*****************************************************************************/ +;/* This file is part of the uVision/ARM development tools. */ +;/* Copyright (c) 2005-2008 Keil Software. All rights reserved. */ +;/* This software may only be used under the terms of a valid, current, */ +;/* end user licence from KEIL for a compatible version of KEIL software */ +;/* development tools. Nothing else gives you the right to use this software. */ +;/*****************************************************************************/ + + +;/* +; * The S3C2440.S code is executed after CPU Reset. This file may be +; * translated with the following SET symbols. In uVision these SET +; * symbols are entered under Options - ASM - Define. +; * +; * NO_CLOCK_SETUP: when set the startup code will not initialize Clock +; * (used mostly when clock is already initialized from script .ini +; * file). +; * +; * NO_MC_SETUP: when set the startup code will not initialize Memory +; * Controller (used mostly when clock is already initialized from script +; * .ini file). +; * +; * NO_GP_SETUP: when set the startup code will not initialize General Ports +; * (used mostly when clock is already initialized from script .ini +; * file). +; * +; * RAM_INTVEC: when set the startup code copies exception vectors +; * from execution address to on-chip RAM. +; */ + + +; Standard definitions of Mode bits and Interrupt (I & F) flags in PSRs + +Mode_USR EQU 0x10 +Mode_FIQ EQU 0x11 +Mode_IRQ EQU 0x12 +Mode_SVC EQU 0x13 +Mode_ABT EQU 0x17 +Mode_UND EQU 0x1B +Mode_SYS EQU 0x1F + +I_Bit EQU 0x80 ; when I bit is set, IRQ is disabled +F_Bit EQU 0x40 ; when F bit is set, FIQ is disabled + + +;----------------------- Stack and Heap Definitions ---------------------------- + +;// <h> Stack Configuration (Stack Sizes in Bytes) +;// <o0> Undefined Mode <0x0-0xFFFFFFFF:8> +;// <o1> Supervisor Mode <0x0-0xFFFFFFFF:8> +;// <o2> Abort Mode <0x0-0xFFFFFFFF:8> +;// <o3> Fast Interrupt Mode <0x0-0xFFFFFFFF:8> +;// <o4> Interrupt Mode <0x0-0xFFFFFFFF:8> +;// <o5> User/System Mode <0x0-0xFFFFFFFF:8> +;// </h> + +UND_Stack_Size EQU 0x00000000 +SVC_Stack_Size EQU 0x00000100 +ABT_Stack_Size EQU 0x00000000 +FIQ_Stack_Size EQU 0x00000000 +IRQ_Stack_Size EQU 0x00000100 +USR_Stack_Size EQU 0x00000100 + +ISR_Stack_Size EQU (UND_Stack_Size + SVC_Stack_Size + ABT_Stack_Size + \ + FIQ_Stack_Size + IRQ_Stack_Size) + + AREA STACK, NOINIT, READWRITE, ALIGN=3 + +Stack_Mem SPACE USR_Stack_Size +__initial_sp SPACE ISR_Stack_Size +Stack_Top + + +;// <h> Heap Configuration +;// <o> Heap Size (in Bytes) <0x0-0xFFFFFFFF> +;// </h> + +Heap_Size EQU 0x00000000 + + AREA HEAP, NOINIT, READWRITE, ALIGN=3 +__heap_base +Heap_Mem SPACE Heap_Size +__heap_limit + + +;----------------------- Memory Definitions ------------------------------------ + +; Internal Memory Base Addresses +IRAM_BASE EQU 0x40000000 + + +;----------------------- Watchdog Timer Definitions ---------------------------- + +WT_BASE EQU 0x53000000 ; Watchdog Timer Base Address +WTCON_OFS EQU 0x00 ; Watchdog Timer Control Register Offset +WTDAT_OFS EQU 0x04 ; Watchdog Timer Data Register Offset +WTCNT_OFS EQU 0x08 ; Watchdog Timer Count Register Offset + +;// <e> Watchdog Timer Setup +;// <h> Watchdog Timer Control Register (WTCON) +;// <o1.8..15> Prescaler Value <0-255> +;// <o1.5> Watchdog Timer Enable +;// <o1.3..4> Clock Division Factor +;// <0=> 16 <1=> 32 <2=> 64 <3=> 128 +;// <o1.2> Interrupt Generation Enable +;// <o1.0> Reset Enable +;// </h> +;// <h> Watchdog Timer Data Register (WTDAT) +;// <o2.0..15> Count Reload Value <0-65535> +;// </h> +;// </e> Watchdog Timer Setup +WT_SETUP EQU 1 +WTCON_Val EQU 0x00000000 +WTDAT_Val EQU 0x00008000 + + +;----------------------- Clock and Power Management Definitions ---------------- + +CLOCK_BASE EQU 0x4C000000 ; Clock Base Address +LOCKTIME_OFS EQU 0x00 ; PLL Lock Time Count Register Offset +MPLLCON_OFS EQU 0x04 ; MPLL Configuration Register Offset +UPLLCON_OFS EQU 0x08 ; UPLL Configuration Register Offset +CLKCON_OFS EQU 0x0C ; Clock Generator Control Reg Offset +CLKSLOW_OFS EQU 0x10 ; Clock Slow Control Register Offset +CLKDIVN_OFS EQU 0x14 ; Clock Divider Control Register Offset +CAMDIVN_OFS EQU 0x18 ; Camera Clock Divider Register Offset + +;// <e> Clock Setup +;// <h> PLL Lock Time Count Register (LOCKTIME) +;// <o1.16..31> U_LTIME: UPLL Lock Time Count Value for UCLK <0x0-0xFFFF> +;// <o1.0..15> M_LTIME: MPLL Lock Time Count Value for FCLK, HCLK and PCLK <0x0-0xFFFF> +;// </h> +;// <h> MPLL Configuration Register (MPLLCON) +;// <i> MPLL = (2 * m * Fin) / (p * 2^s) +;// <o2.12..19> m: Main Divider m Value <9-256><#-8> +;// <i> m = MDIV + 8 +;// <o2.4..9> p: Pre-divider p Value <3-64><#-2> +;// <i> p = PDIV + 2 +;// <o2.0..1> s: Post Divider s Value <0-3> +;// <i> s = SDIV +;// </h> +;// <h> UPLL Configuration Register (UPLLCON) +;// <i> UPLL = ( m * Fin) / (p * 2^s) +;// <o3.12..19> m: Main Divider m Value <8-263><#-8> +;// <i> m = MDIV + 8 +;// <o3.4..9> p: Pre-divider p Value <2-65><#-2> +;// <i> p = PDIV + 2 +;// <o3.0..1> s: Post Divider s Value <0-3> +;// <i> s = SDIV +;// </h> +;// <h> Clock Generation Control Register (CLKCON) +;// <o4.20> AC97 Enable +;// <o4.19> Camera Enable +;// <o4.18> SPI Enable +;// <o4.17> IIS Enable +;// <o4.16> IIC Enable +;// <o4.15> ADC + Touch Screen Enable +;// <o4.14> RTC Enable +;// <o4.13> GPIO Enable +;// <o4.12> UART2 Enable +;// <o4.11> UART1 Enable +;// <o4.10> UART0 Enable +;// <o4.9> SDI Enable +;// <o4.8> PWMTIMER Enable +;// <o4.7> USB Device Enable +;// <o4.6> USB Host Enable +;// <o4.5> LCDC Enable +;// <o4.4> NAND FLASH Controller Enable +;// <o4.3> SLEEP Enable +;// <o4.2> IDLE BIT Enable +;// </h> +;// <h> Clock Slow Control Register (CLKSLOW) +;// <o5.7> UCLK_ON: UCLK ON +;// <o5.5> MPLL_OFF: Turn off PLL +;// <o5.4> SLOW_BIT: Slow Mode Enable +;// <o5.0..2> SLOW_VAL: Slow Clock Divider <0-7> +;// </h> +;// <h> Clock Divider Control Register (CLKDIVN) +;// <o6.3> DIVN_UPLL: UCLK Select +;// <0=> UCLK = UPLL clock +;// <1=> UCLK = UPLL clock / 2 +;// <o6.1..2> HDIVN: HCLK Select +;// <0=> HCLK = FCLK +;// <1=> HCLK = FCLK / 2 +;// <2=> HCLK = FCLK / 4 if HCLK4_HALF = 0 in CAMDIVN, else HCLK = FCLK / 8 +;// <3=> HCLK = FCLK / 3 if HCLK3_HALF = 0 in CAMDIVN, else HCLK = FCLK / 6 +;// <o6.0> PDIVN: PCLK Select +;// <0=> PCLK = HCLK +;// <1=> PCLK = HCLK / 2 +;// </h> +;// <h> Camera Clock Divider Control Register (CAMDIVN) +;// <o7.12> DVS_EN: ARM Core Clock Select +;// <0=> ARM core runs at FCLK +;// <1=> ARM core runs at HCLK +;// <o7.9> HCLK4_HALF: HDIVN Division Rate Change Bit +;// <0=> If HDIVN = 2 in CLKDIVN then HCLK = FCLK / 4 +;// <1=> If HDIVN = 2 in CLKDIVN then HCLK = FCLK / 8 +;// <o7.8> HCLK3_HALF: HDIVN Division Rate Change Bit +;// <0=> If HDIVN = 3 in CLKDIVN then HCLK = FCLK / 3 +;// <1=> If HDIVN = 3 in CLKDIVN then HCLK = FCLK / 6 +;// <o7.4> CAMCLK Select +;// <0=> CAMCLK = UPLL +;// <1=> CAMCLK = UPLL / CAMCLK_DIV +;// <o7.0..3> CAMCLK_DIV: CAMCLK Divider <0-15> +;// <i> Camera Clock = UPLL / (2 * (CAMCLK_DIV + 1)) +;// <i> Divider is used only if CAMCLK_SEL = 1 +;// </h> +;// </e> Clock Setup +CLOCK_SETUP EQU 0 +LOCKTIME_Val EQU 0x0FFF0FFF +MPLLCON_Val EQU 0x00043011 +UPLLCON_Val EQU 0x00038021 +CLKCON_Val EQU 0x001FFFF0 +CLKSLOW_Val EQU 0x00000004 +CLKDIVN_Val EQU 0x0000000F +CAMDIVN_Val EQU 0x00000000 + + +;----------------------- Memory Controller Definitions ------------------------- + +MC_BASE EQU 0x48000000 ; Memory Controller Base Address +BWSCON_OFS EQU 0x00 ; Bus Width and Wait Status Ctrl Offset +BANKCON0_OFS EQU 0x04 ; Bank 0 Control Register Offset +BANKCON1_OFS EQU 0x08 ; Bank 1 Control Register Offset +BANKCON2_OFS EQU 0x0C ; Bank 2 Control Register Offset +BANKCON3_OFS EQU 0x10 ; Bank 3 Control Register Offset +BANKCON4_OFS EQU 0x14 ; Bank 4 Control Register Offset +BANKCON5_OFS EQU 0x18 ; Bank 5 Control Register Offset +BANKCON6_OFS EQU 0x1C ; Bank 6 Control Register Offset +BANKCON7_OFS EQU 0x20 ; Bank 7 Control Register Offset +REFRESH_OFS EQU 0x24 ; SDRAM Refresh Control Register Offset +BANKSIZE_OFS EQU 0x28 ; Flexible Bank Size Register Offset +MRSRB6_OFS EQU 0x2C ; Bank 6 Mode Register Offset +MRSRB7_OFS EQU 0x30 ; Bank 7 Mode Register Offset + +;// <e> Memory Controller Setup +;// <h> Bus Width and Wait Control Register (BWSCON) +;// <o1.31> ST7: Use UB/LB for Bank 7 +;// <o1.30> WS7: Enable Wait Status for Bank 7 +;// <o1.28..29> DW7: Data Bus Width for Bank 7 +;// <0=> 8-bit <1=> 16-bit <2=> 32-bit <3=> Reserved +;// <o1.27> ST6: Use UB/LB for Bank 6 +;// <o1.26> WS6: Enable Wait Status for Bank 6 +;// <o1.24..25> DW6: Data Bus Width for Bank 6 +;// <0=> 8-bit <1=> 16-bit <2=> 32-bit <3=> Reserved +;// <o1.23> ST5: Use UB/LB for Bank 5 +;// <o1.22> WS5: Enable Wait Status for Bank 5 +;// <o1.20..21> DW5: Data Bus Width for Bank 5 +;// <0=> 8-bit <1=> 16-bit <2=> 32-bit <3=> Reserved +;// <o1.19> ST4: Use UB/LB for Bank 4 +;// <o1.18> WS4: Enable Wait Status for Bank 4 +;// <o1.16..17> DW4: Data Bus Width for Bank 4 +;// <0=> 8-bit <1=> 16-bit <2=> 32-bit <3=> Reserved +;// <o1.15> ST3: Use UB/LB for Bank 3 +;// <o1.14> WS3: Enable Wait Status for Bank 3 +;// <o1.12..13> DW3: Data Bus Width for Bank 3 +;// <0=> 8-bit <1=> 16-bit <2=> 32-bit <3=> Reserved +;// <o1.11> ST2: Use UB/LB for Bank 2 +;// <o1.10> WS2: Enable Wait Status for Bank 2 +;// <o1.8..9> DW2: Data Bus Width for Bank 2 +;// <0=> 8-bit <1=> 16-bit <2=> 32-bit <3=> Reserved +;// <o1.7> ST1: Use UB/LB for Bank 1 +;// <o1.6> WS1: Enable Wait Status for Bank 1 +;// <o1.4..5> DW1: Data Bus Width for Bank 1 +;// <0=> 8-bit <1=> 16-bit <2=> 32-bit <3=> Reserved +;// <o1.1..2> DW0: Indicate Data Bus Width for Bank 0 +;// <1=> 16-bit <2=> 32-bit +;// </h> +;// <h> Bank 0 Control Register (BANKCON0) +;// <o2.13..14> Tacs: Address Set-up Time before nGCS +;// <0=> 0 clocks <1=> 1 clocks <2=> 2 clocks <3=> 4 clocks +;// <o2.11..12> Tcos: Chip Selection Set-up Time before nOE +;// <0=> 0 clocks <1=> 1 clocks <2=> 2 clocks <3=> 4 clocks +;// <o2.8..10> Tacc: Access Cycle +;// <0=> 1 clocks <1=> 2 clocks <2=> 3 clocks <3=> 4 clocks +;// <4=> 6 clocks <5=> 8 clocks <6=> 10 clocks <7=> 14 clocks +;// <o2.6..7> Tcoh: Chip Selection Hold Time after nOE +;// <0=> 0 clocks <1=> 1 clocks <2=> 2 clocks <3=> 4 clocks +;// <o2.4..5> Tcah: Address Hold Time after nGCS +;// <0=> 0 clocks <1=> 1 clocks <2=> 2 clocks <3=> 4 clocks +;// <o2.2..3> Tacp: Page Mode Access Cycle at Page Mode +;// <0=> 2 clocks <1=> 3 clocks <2=> 4 clocks <3=> 6 clocks +;// <o2.0..1> PMC: Page Mode Configuration +;// <0=> normal (1 data) <1=> 4 data <2=> 8 data <3=> 16 data +;// </h> +;// <h> Bank 1 Control Register (BANKCON1) +;// <o3.13..14> Tacs: Address Set-up Time before nGCS +;// <0=> 0 clocks <1=> 1 clocks <2=> 2 clocks <3=> 4 clocks +;// <o3.11..12> Tcos: Chip Selection Set-up Time before nOE +;// <0=> 0 clocks <1=> 1 clocks <2=> 2 clocks <3=> 4 clocks +;// <o3.8..10> Tacc: Access Cycle +;// <0=> 1 clocks <1=> 2 clocks <2=> 3 clocks <3=> 4 clocks +;// <4=> 6 clocks <5=> 8 clocks <6=> 10 clocks <7=> 14 clocks +;// <o3.6..7> Tcoh: Chip Selection Hold Time after nOE +;// <0=> 0 clocks <1=> 1 clocks <2=> 2 clocks <3=> 4 clocks +;// <o3.4..5> Tcah: Address Hold Time after nGCS +;// <0=> 0 clocks <1=> 1 clocks <2=> 2 clocks <3=> 4 clocks +;// <o3.2..3> Tacp: Page Mode Access Cycle at Page Mode +;// <0=> 2 clocks <1=> 3 clocks <2=> 4 clocks <3=> 6 clocks +;// <o3.0..1> PMC: Page Mode Configuration +;// <0=> normal (1 data) <1=> 4 data <2=> 8 data <3=> 16 data +;// </h> +;// <h> Bank 2 Control Register (BANKCON2) +;// <o4.13..14> Tacs: Address Set-up Time before nGCS +;// <0=> 0 clocks <1=> 1 clocks <2=> 2 clocks <3=> 4 clocks +;// <o4.11..12> Tcos: Chip Selection Set-up Time before nOE +;// <0=> 0 clocks <1=> 1 clocks <2=> 2 clocks <3=> 4 clocks +;// <o4.8..10> Tacc: Access Cycle +;// <0=> 1 clocks <1=> 2 clocks <2=> 3 clocks <3=> 4 clocks +;// <4=> 6 clocks <5=> 8 clocks <6=> 10 clocks <7=> 14 clocks +;// <o4.6..7> Tcoh: Chip Selection Hold Time after nOE +;// <0=> 0 clocks <1=> 1 clocks <2=> 2 clocks <3=> 4 clocks +;// <o4.4..5> Tcah: Address Hold Time after nGCS +;// <0=> 0 clocks <1=> 1 clocks <2=> 2 clocks <3=> 4 clocks +;// <o4.2..3> Tacp: Page Mode Access Cycle at Page Mode +;// <0=> 2 clocks <1=> 3 clocks <2=> 4 clocks <3=> 6 clocks +;// <o4.0..1> PMC: Page Mode Configuration +;// <0=> normal (1 data) <1=> 4 data <2=> 8 data <3=> 16 data +;// </h> +;// <h> Bank 3 Control Register (BANKCON3) +;// <o5.13..14> Tacs: Address Set-up Time before nGCS +;// <0=> 0 clocks <1=> 1 clocks <2=> 2 clocks <3=> 4 clocks +;// <o5.11..12> Tcos: Chip Selection Set-up Time before nOE +;// <0=> 0 clocks <1=> 1 clocks <2=> 2 clocks <3=> 4 clocks +;// <o5.8..10> Tacc: Access Cycle +;// <0=> 1 clocks <1=> 2 clocks <2=> 3 clocks <3=> 4 clocks +;// <4=> 6 clocks <5=> 8 clocks <6=> 10 clocks <7=> 14 clocks +;// <o5.6..7> Tcoh: Chip Selection Hold Time after nOE +;// <0=> 0 clocks <1=> 1 clocks <2=> 2 clocks <3=> 4 clocks +;// <o5.4..5> Tcah: Address Hold Time after nGCS +;// <0=> 0 clocks <1=> 1 clocks <2=> 2 clocks <3=> 4 clocks +;// <o5.2..3> Tacp: Page Mode Access Cycle at Page Mode +;// <0=> 2 clocks <1=> 3 clocks <2=> 4 clocks <3=> 6 clocks +;// <o5.0..1> PMC: Page Mode Configuration +;// <0=> normal (1 data) <1=> 4 data <2=> 8 data <3=> 16 data +;// </h> +;// <h> Bank 4 Control Register (BANKCON4) +;// <o6.13..14> Tacs: Address Set-up Time before nGCS +;// <0=> 0 clocks <1=> 1 clocks <2=> 2 clocks <3=> 4 clocks +;// <o6.11..12> Tcos: Chip Selection Set-up Time before nOE +;// <0=> 0 clocks <1=> 1 clocks <2=> 2 clocks <3=> 4 clocks +;// <o6.8..10> Tacc: Access Cycle +;// <0=> 1 clocks <1=> 2 clocks <2=> 3 clocks <3=> 4 clocks +;// <4=> 6 clocks <5=> 8 clocks <6=> 10 clocks <7=> 14 clocks +;// <o6.6..7> Tcoh: Chip Selection Hold Time after nOE +;// <0=> 0 clocks <1=> 1 clocks <2=> 2 clocks <3=> 4 clocks +;// <o6.4..5> Tcah: Address Hold Time after nGCS +;// <0=> 0 clocks <1=> 1 clocks <2=> 2 clocks <3=> 4 clocks +;// <o6.2..3> Tacp: Page Mode Access Cycle at Page Mode +;// <0=> 2 clocks <1=> 3 clocks <2=> 4 clocks <3=> 6 clocks +;// <o6.0..1> PMC: Page Mode Configuration +;// <0=> normal (1 data) <1=> 4 data <2=> 8 data <3=> 16 data +;// </h> +;// <h> Bank 5 Control Register (BANKCON5) +;// <o7.13..14> Tacs: Address Set-up Time before nGCS +;// <0=> 0 clocks <1=> 1 clocks <2=> 2 clocks <3=> 4 clocks +;// <o7.11..12> Tcos: Chip Selection Set-up Time before nOE +;// <0=> 0 clocks <1=> 1 clocks <2=> 2 clocks <3=> 4 clocks +;// <o7.8..10> Tacc: Access Cycle +;// <0=> 1 clocks <1=> 2 clocks <2=> 3 clocks <3=> 4 clocks +;// <4=> 6 clocks <5=> 8 clocks <6=> 10 clocks <7=> 14 clocks +;// <o7.6..7> Tcoh: Chip Selection Hold Time after nOE +;// <0=> 0 clocks <1=> 1 clocks <2=> 2 clocks <3=> 4 clocks +;// <o7.4..5> Tcah: Address Hold Time after nGCS +;// <0=> 0 clocks <1=> 1 clocks <2=> 2 clocks <3=> 4 clocks +;// <o7.2..3> Tacp: Page Mode Access Cycle at Page Mode +;// <0=> 2 clocks <1=> 3 clocks <2=> 4 clocks <3=> 6 clocks +;// <o7.0..1> PMC: Page Mode Configuration +;// <0=> normal (1 data) <1=> 4 data <2=> 8 data <3=> 16 data +;// </h> +;// <h> Bank 6 Control Register (BANKCON6) +;// <o8.15..16> Memory Type Selection +;// <0=> ROM or SRAM <3=> SDRAM +;// <o8.13..14> Tacs: Address Set-up Time before nGCS +;// <0=> 0 clocks <1=> 1 clocks <2=> 2 clocks <3=> 4 clocks +;// <o8.11..12> Tcos: Chip Selection Set-up Time before nOE +;// <0=> 0 clocks <1=> 1 clocks <2=> 2 clocks <3=> 4 clocks +;// <o8.8..10> Tacc: Access Cycle +;// <0=> 1 clocks <1=> 2 clocks <2=> 3 clocks <3=> 4 clocks +;// <4=> 6 clocks <5=> 8 clocks <6=> 10 clocks <7=> 14 clocks +;// <o8.6..7> Tcoh: Chip Selection Hold Time after nOE +;// <0=> 0 clocks <1=> 1 clocks <2=> 2 clocks <3=> 4 clocks +;// <o8.4..5> Tcah: Address Hold Time after nGCS +;// <0=> 0 clocks <1=> 1 clocks <2=> 2 clocks <3=> 4 clocks +;// <o8.2..3> Tacp/Trcd: Page Mode Access Cycle at Page Mode / RAS to CAS Delay +;// <i> Parameter depends on Memory Type: if type SRAM then parameter is Tacp, +;// <i> if type is SDRAM then parameter is Trcd +;// <i> For SDRAM 6 cycles setting is not allowed +;// <0=> 2 clocks <1=> 3 clocks <2=> 4 clocks <3=> 6 clocks +;// <o8.0..1> PMC/SCAN: Page Mode Configuration / Column Address Number <0-3> +;// <i> Parameter depends on Memory Type: if type SRAM then parameter is PMC, +;// <i> if type is SDRAM then parameter is SCAN +;// </h> +;// <h> Bank 7 Control Register (BANKCON7) +;// <o9.15..16> Memory Type Selection +;// <0=> ROM or SRAM <3=> SDRAM +;// <o9.13..14> Tacs: Address Set-up Time before nGCS +;// <0=> 0 clocks <1=> 1 clocks <2=> 2 clocks <3=> 4 clocks +;// <o9.11..12> Tcos: Chip Selection Set-up Time before nOE +;// <0=> 0 clocks <1=> 1 clocks <2=> 2 clocks <3=> 4 clocks +;// <o9.8..10> Tacc: Access Cycle +;// <0=> 1 clocks <1=> 2 clocks <2=> 3 clocks <3=> 4 clocks +;// <4=> 6 clocks <5=> 8 clocks <6=> 10 clocks <7=> 14 clocks +;// <o9.6..7> Tcoh: Chip Selection Hold Time after nOE +;// <0=> 0 clocks <1=> 1 clocks <2=> 2 clocks <3=> 4 clocks +;// <o9.4..5> Tcah: Address Hold Time after nGCS +;// <0=> 0 clocks <1=> 1 clocks <2=> 2 clocks <3=> 4 clocks +;// <o9.2..3> Tacp/Trcd: Page Mode Access Cycle at Page Mode / RAS to CAS Delay +;// <i> Parameter depends on Memory Type: if type SRAM then parameter is Tacp, +;// <i> if type is SDRAM then parameter is Trcd +;// <i> For SDRAM 6 cycles setting is not allowed +;// <0=> 2 clocks <1=> 3 clocks <2=> 4 clocks <3=> 6 clocks +;// <o9.0..1> PMC/SCAN: Page Mode Configuration / Column Address Number <0-3> +;// <i> Parameter depends on Memory Type: if type SRAM then parameter is PMC, +;// <i> if type is SDRAM then parameter is SCAN +;// </h> +;// <h> SDRAM Refresh Control Register (REFRESH) +;// <o10.23> REFEN: SDRAM Refresh Enable +;// <o10.22> TREFMD: SDRAM Refresh Mode +;// <0=> CBR/Auto Refresh <1=> Self Refresh +;// <o10.20..21> Trp: SDRAM RAS Pre-charge Time +;// <0=> 2 clocks <1=> 3 clocks <2=> 4 clocks <3=> Reserved +;// <o10.18..19> Tsrc: SDRAM Semi Row Cycle Time +;// <i> SDRAM Row cycle time: Trc = Tsrc + Trp +;// <0=> 4 clocks <1=> 5 clocks <2=> 6 clocks <3=> 7 clocks +;// <o10.0..10> Refresh Counter <0-1023> +;// <i> Refresh Period = (2048 - Refresh Count + 1) / HCLK +;// </h> +;// <h> Flexible Bank Size Register (BANKSIZE) +;// <o11.7> BURST_EN: ARM Core Burst Operation Enable +;// <o11.5> SCKE_EN: SDRAM Power Down Mode Enable +;// <o11.4> SCLK_EN: SCLK Enabled During SDRAM Access Cycle +;// <0=> SCLK is always active <1=> SCLK is active only during the access +;// <o11.0..2> BK76MAP: BANK6 and BANK7 Memory Map +;// <0=> 32MB / 32MB <1=> 64MB / 64MB <2=> 128MB / 128MB +;// <4=> 2MB / 2MB <5=> 4MB / 4MB <6=> 8MB / 8MB <7=> 16MB / 16MB +;// <o11.0..10> Refresh Counter <0-1023> +;// <i> Refresh Period = (2048 - Refresh Count + 1) / HCLK +;// </h> +;// <h> SDRAM Mode Register Set Register 6 (MRSRB6) +;// <o12.7> WBL: Write Burst Length +;// <0=> Burst (Fixed) +;// <o12.7..8> TM: Test Mode +;// <0=> Mode register set (Fixed) +;// <o12.4..6> CL: CAS Latency +;// <0=> 1 clocks <1=> 2 clocks <2=> 3 clocks +;// <o12.3> BT: Burst Type +;// <0=> Sequential (Fixed) +;// <o12.0..2> BL: Burst Length +;// <0=> 1 (Fixed) +;// </h> +;// <h> SDRAM Mode Register Set Register 7 (MRSRB7) +;// <o13.7> WBL: Write Burst Length +;// <0=> Burst (Fixed) +;// <o13.7..8> TM: Test Mode +;// <0=> Mode register set (Fixed) +;// <o13.4..6> CL: CAS Latency +;// <0=> 1 clocks <1=> 2 clocks <2=> 3 clocks +;// <o13.3> BT: Burst Type +;// <0=> Sequential (Fixed) +;// <o13.0..2> BL: Burst Length +;// <0=> 1 (Fixed) +;// </h> +;// </e> Memory Controller Setup +MC_SETUP EQU 0 +BWSCON_Val EQU 0x22000000 +BANKCON0_Val EQU 0x00000700 +BANKCON1_Val EQU 0x00000700 +BANKCON2_Val EQU 0x00000700 +BANKCON3_Val EQU 0x00000700 +BANKCON4_Val EQU 0x00000700 +BANKCON5_Val EQU 0x00000700 +BANKCON6_Val EQU 0x00018005 +BANKCON7_Val EQU 0x00018005 +REFRESH_Val EQU 0x008404F3 +BANKSIZE_Val EQU 0x00000032 +MRSRB6_Val EQU 0x00000020 +MRSRB7_Val EQU 0x00000020 + + +;----------------------- I/O Port Definitions ---------------------------------- + +GPA_BASE EQU 0x56000000 ; GPA Base Address +GPB_BASE EQU 0x56000010 ; GPB Base Address +GPC_BASE EQU 0x56000020 ; GPC Base Address +GPD_BASE EQU 0x56000030 ; GPD Base Address +GPE_BASE EQU 0x56000040 ; GPE Base Address +GPF_BASE EQU 0x56000050 ; GPF Base Address +GPG_BASE EQU 0x56000060 ; GPG Base Address +GPH_BASE EQU 0x56000070 ; GPH Base Address +GPJ_BASE EQU 0x560000D0 ; GPJ Base Address +GPCON_OFS EQU 0x00 ; Control Register Offset +GPDAT_OFS EQU 0x04 ; Data Register Offset +GPUP_OFS EQU 0x08 ; Pull-up Disable Register Offset + +;// <e> I/O Setup +GP_SETUP EQU 1 + +;// <e> Port A Settings +;// <h> Port A Control Register (GPACON) +;// <o1.22> GPA22 <0=> Output <1=> nFCE +;// <o1.21> GPA21 <0=> Output <1=> nRSTOUT +;// <o1.20> GPA20 <0=> Output <1=> nFRE +;// <o1.19> GPA19 <0=> Output <1=> nFWE +;// <o1.18> GPA18 <0=> Output <1=> ALE +;// <o1.17> GPA17 <0=> Output <1=> CLE +;// <o1.16> GPA16 <0=> Output <1=> nGCS[5] +;// <o1.15> GPA15 <0=> Output <1=> nGCS[4] +;// <o1.14> GPA14 <0=> Output <1=> nGCS[3] +;// <o1.13> GPA13 <0=> Output <1=> nGCS[2] +;// <o1.12> GPA12 <0=> Output <1=> nGCS[1] +;// <o1.11> GPA11 <0=> Output <1=> ADDR26 +;// <o1.10> GPA10 <0=> Output <1=> ADDR25 +;// <o1.9> GPA9 <0=> Output <1=> ADDR24 +;// <o1.8> GPA8 <0=> Output <1=> ADDR23 +;// <o1.7> GPA7 <0=> Output <1=> ADDR22 +;// <o1.6> GPA6 <0=> Output <1=> ADDR21 +;// <o1.5> GPA5 <0=> Output <1=> ADDR20 +;// <o1.4> GPA4 <0=> Output <1=> ADDR19 +;// <o1.3> GPA3 <0=> Output <1=> ADDR18 +;// <o1.2> GPA2 <0=> Output <1=> ADDR17 +;// <o1.1> GPA1 <0=> Output <1=> ADDR16 +;// <o1.0> GPA0 <0=> Output <1=> ADDR0 +;// </h> +;// </e> +GPA_SETUP EQU 0 +GPACON_Val EQU 0x000003FF + +;// <e> Port B Settings +;// <h> Port B Control Register (GPBCON) +;// <o1.20..21> GPB10 <0=> Input <1=> Output <2=> nXDREQ0 <3=> Reserved +;// <o1.18..19> GPB9 <0=> Input <1=> Output <2=> nXDACK0 <3=> Reserved +;// <o1.16..17> GPB8 <0=> Input <1=> Output <2=> nXDREQ1 <3=> Reserved +;// <o1.14..15> GPB7 <0=> Input <1=> Output <2=> nXDACK1 <3=> Reserved +;// <o1.12..13> GPB6 <0=> Input <1=> Output <2=> nXBREQ <3=> Reserved +;// <o1.10..11> GPB5 <0=> Input <1=> Output <2=> nXBACK <3=> Reserved +;// <o1.8..9> GPB4 <0=> Input <1=> Output <2=> TCLK[0] <3=> Reserved +;// <o1.6..7> GPB3 <0=> Input <1=> Output <2=> TOUT3 <3=> Reserved +;// <o1.4..5> GPB2 <0=> Input <1=> Output <2=> TOUT2 <3=> Reserved +;// <o1.2..3> GPB1 <0=> Input <1=> Output <2=> TOUT1 <3=> Reserved +;// <o1.0..1> GPB0 <0=> Input <1=> Output <2=> TOUT0 <3=> Reserved +;// </h> +;// <h> Port B Pull-up Settings Register (GPBUP) +;// <o2.10> GPB10 Pull-up Disable +;// <o2.9> GPB9 Pull-up Disable +;// <o2.8> GPB8 Pull-up Disable +;// <o2.7> GPB7 Pull-up Disable +;// <o2.6> GPB6 Pull-up Disable +;// <o2.5> GPB5 Pull-up Disable +;// <o2.4> GPB4 Pull-up Disable +;// <o2.3> GPB3 Pull-up Disable +;// <o2.2> GPB2 Pull-up Disable +;// <o2.1> GPB1 Pull-up Disable +;// <o2.0> GPB0 Pull-up Disable +;// </h> +;// </e> +GPB_SETUP EQU 0 +GPBCON_Val EQU 0x00000000 +GPBUP_Val EQU 0x00000000 + +;// <e> Port C Settings +;// <h> Port C Control Register (GPCCON) +;// <o1.30..31> GPC15 <0=> Input <1=> Output <2=> VD[7] <3=> Reserved +;// <o1.28..29> GPC14 <0=> Input <1=> Output <2=> VD[6] <3=> Reserved +;// <o1.26..27> GPC13 <0=> Input <1=> Output <2=> VD[5] <3=> Reserved +;// <o1.24..25> GPC12 <0=> Input <1=> Output <2=> VD[4] <3=> Reserved +;// <o1.22..23> GPC11 <0=> Input <1=> Output <2=> VD[3] <3=> Reserved +;// <o1.20..21> GPC10 <0=> Input <1=> Output <2=> VD[2] <3=> Reserved +;// <o1.18..19> GPC9 <0=> Input <1=> Output <2=> VD[1] <3=> Reserved +;// <o1.16..17> GPC8 <0=> Input <1=> Output <2=> VD[0] <3=> Reserved +;// <o1.14..15> GPC7 <0=> Input <1=> Output <2=> LCD_LPCREVB <3=> Reserved +;// <o1.12..13> GPC6 <0=> Input <1=> Output <2=> LCD_LPCREV <3=> Reserved +;// <o1.10..11> GPC5 <0=> Input <1=> Output <2=> LCD_LPCOE <3=> Reserved +;// <o1.8..9> GPC4 <0=> Input <1=> Output <2=> VM <3=> I2SSDI +;// <o1.6..7> GPC3 <0=> Input <1=> Output <2=> VFRAME <3=> Reserved +;// <o1.4..5> GPC2 <0=> Input <1=> Output <2=> VLINE <3=> Reserved +;// <o1.2..3> GPC1 <0=> Input <1=> Output <2=> VCLK <3=> Reserved +;// <o1.0..1> GPC0 <0=> Input <1=> Output <2=> LEND <3=> Reserved +;// </h> +;// <h> Port C Pull-up Settings Register (GPCUP) +;// <o2.15> GPC15 Pull-up Disable +;// <o2.14> GPC14 Pull-up Disable +;// <o2.13> GPC13 Pull-up Disable +;// <o2.12> GPC12 Pull-up Disable +;// <o2.11> GPC11 Pull-up Disable +;// <o2.10> GPC10 Pull-up Disable +;// <o2.9> GPC9 Pull-up Disable +;// <o2.8> GPC8 Pull-up Disable +;// <o2.7> GPC7 Pull-up Disable +;// <o2.6> GPC6 Pull-up Disable +;// <o2.5> GPC5 Pull-up Disable +;// <o2.4> GPC4 Pull-up Disable +;// <o2.3> GPC3 Pull-up Disable +;// <o2.2> GPC2 Pull-up Disable +;// <o2.1> GPC1 Pull-up Disable +;// <o2.0> GPC0 Pull-up Disable +;// </h> +;// </e> +GPC_SETUP EQU 0 +GPCCON_Val EQU 0x00000000 +GPCUP_Val EQU 0x00000000 + +;// <e> Port D Settings +;// <h> Port D Control Register (GPDCON) +;// <o1.30..31> GPD15 <0=> Input <1=> Output <2=> VD[23] <3=> nSS0 +;// <o1.28..29> GPD14 <0=> Input <1=> Output <2=> VD[22] <3=> nSS1 +;// <o1.26..27> GPD13 <0=> Input <1=> Output <2=> VD[21] <3=> Reserved +;// <o1.24..25> GPD12 <0=> Input <1=> Output <2=> VD[20] <3=> Reserved +;// <o1.22..23> GPD11 <0=> Input <1=> Output <2=> VD[19] <3=> Reserved +;// <o1.20..21> GPD10 <0=> Input <1=> Output <2=> VD[18] <3=> SPICLK1 +;// <o1.18..19> GPD9 <0=> Input <1=> Output <2=> VD[17] <3=> SPIMOSI1 +;// <o1.16..17> GPD8 <0=> Input <1=> Output <2=> VD[16] <3=> SPIMISO1 +;// <o1.14..15> GPD7 <0=> Input <1=> Output <2=> VD[15] <3=> Reserved +;// <o1.12..13> GPD6 <0=> Input <1=> Output <2=> VD[14] <3=> Reserved +;// <o1.10..11> GPD5 <0=> Input <1=> Output <2=> VD[13] <3=> Reserved +;// <o1.8..9> GPD4 <0=> Input <1=> Output <2=> VD[12] <3=> Reserved +;// <o1.6..7> GPD3 <0=> Input <1=> Output <2=> VD[11] <3=> Reserved +;// <o1.4..5> GPD2 <0=> Input <1=> Output <2=> VD[10] <3=> Reserved +;// <o1.2..3> GPD1 <0=> Input <1=> Output <2=> VD[9] <3=> Reserved +;// <o1.0..1> GPD0 <0=> Input <1=> Output <2=> VD[8] <3=> Reserved +;// </h> +;// <h> Port D Pull-up Settings Register (GPDUP) +;// <o2.15> GPD15 Pull-up Disable +;// <o2.14> GPD14 Pull-up Disable +;// <o2.13> GPD13 Pull-up Disable +;// <o2.12> GPD12 Pull-up Disable +;// <o2.11> GPD11 Pull-up Disable +;// <o2.10> GPD10 Pull-up Disable +;// <o2.9> GPD9 Pull-up Disable +;// <o2.8> GPD8 Pull-up Disable +;// <o2.7> GPD7 Pull-up Disable +;// <o2.6> GPD6 Pull-up Disable +;// <o2.5> GPD5 Pull-up Disable +;// <o2.4> GPD4 Pull-up Disable +;// <o2.3> GPD3 Pull-up Disable +;// <o2.2> GPD2 Pull-up Disable +;// <o2.1> GPD1 Pull-up Disable +;// <o2.0> GPD0 Pull-up Disable +;// </h> +;// </e> +GPD_SETUP EQU 0 +GPDCON_Val EQU 0x00000000 +GPDUP_Val EQU 0x00000000 + +;// <e> Port E Settings +;// <h> Port E Control Register (GPECON) +;// <o1.30..31> GPE15 <0=> Input <1=> Output <2=> IICSDA <3=> Reserved +;// <i> This pad is open-drain, and has no pull-up option. +;// <o1.28..29> GPE14 <0=> Input <1=> Output <2=> IICSCL <3=> Reserved +;// <i> This pad is open-drain, and has no pull-up option. +;// <o1.26..27> GPE13 <0=> Input <1=> Output <2=> SPICLK0 <3=> Reserved +;// <o1.24..25> GPE12 <0=> Input <1=> Output <2=> SPIMOSI0 <3=> Reserved +;// <o1.22..23> GPE11 <0=> Input <1=> Output <2=> SPIMISO0 <3=> Reserved +;// <o1.20..21> GPE10 <0=> Input <1=> Output <2=> SDDAT3 <3=> Reserved +;// <o1.18..19> GPE9 <0=> Input <1=> Output <2=> SDDAT2 <3=> Reserved +;// <o1.16..17> GPE8 <0=> Input <1=> Output <2=> SDDAT1 <3=> Reserved +;// <o1.14..15> GPE7 <0=> Input <1=> Output <2=> SDDAT0 <3=> Reserved +;// <o1.12..13> GPE6 <0=> Input <1=> Output <2=> SDCMD <3=> Reserved +;// <o1.10..11> GPE5 <0=> Input <1=> Output <2=> SDCLK <3=> Reserved +;// <o1.8..9> GPE4 <0=> Input <1=> Output <2=> I2SDO <3=> AC_SDATA_OUT +;// <o1.6..7> GPE3 <0=> Input <1=> Output <2=> I2SDI <3=> AC_SDATA_IN +;// <o1.4..5> GPE2 <0=> Input <1=> Output <2=> CDCLK <3=> AC_nRESET +;// <o1.2..3> GPE1 <0=> Input <1=> Output <2=> I2SSCLK <3=> AC_BIT_CLK +;// <o1.0..1> GPE0 <0=> Input <1=> Output <2=> I2SLRCK <3=> AC_SYNC +;// </h> +;// <h> Port E Pull-up Settings Register (GPEUP) +;// <o2.13> GPE13 Pull-up Disable +;// <o2.12> GPE12 Pull-up Disable +;// <o2.11> GPE11 Pull-up Disable +;// <o2.10> GPE10 Pull-up Disable +;// <o2.9> GPE9 Pull-up Disable +;// <o2.8> GPE8 Pull-up Disable +;// <o2.7> GPE7 Pull-up Disable +;// <o2.6> GPE6 Pull-up Disable +;// <o2.5> GPE5 Pull-up Disable +;// <o2.4> GPE4 Pull-up Disable +;// <o2.3> GPE3 Pull-up Disable +;// <o2.2> GPE2 Pull-up Disable +;// <o2.1> GPE1 Pull-up Disable +;// <o2.0> GPE0 Pull-up Disable +;// </h> +;// </e> +GPE_SETUP EQU 0 +GPECON_Val EQU 0x00000000 +GPEUP_Val EQU 0x00000000 + +;// <e> Port F Settings +;// <h> Port F Control Register (GPFCON) +;// <o1.14..15> GPF7 <0=> Input <1=> Output <2=> EINT[7] <3=> Reserved +;// <o1.12..13> GPF6 <0=> Input <1=> Output <2=> EINT[6] <3=> Reserved +;// <o1.10..11> GPF5 <0=> Input <1=> Output <2=> EINT[5] <3=> Reserved +;// <o1.8..9> GPF4 <0=> Input <1=> Output <2=> EINT[4] <3=> Reserved +;// <o1.6..7> GPF3 <0=> Input <1=> Output <2=> EINT[3] <3=> Reserved +;// <o1.4..5> GPF2 <0=> Input <1=> Output <2=> EINT[2] <3=> Reserved +;// <o1.2..3> GPF1 <0=> Input <1=> Output <2=> EINT[1] <3=> Reserved +;// <o1.0..1> GPF0 <0=> Input <1=> Output <2=> EINT[0] <3=> Reserved +;// </h> +;// <h> Port F Pull-up Settings Register (GPFUP) +;// <o2.7> GPF7 Pull-up Disable +;// <o2.6> GPF6 Pull-up Disable +;// <o2.5> GPF5 Pull-up Disable +;// <o2.4> GPF4 Pull-up Disable +;// <o2.3> GPF3 Pull-up Disable +;// <o2.2> GPF2 Pull-up Disable +;// <o2.1> GPF1 Pull-up Disable +;// <o2.0> GPF0 Pull-up Disable +;// </h> +;// </e> +GPF_SETUP EQU 1 +GPFCON_Val EQU 0x000000AA +GPFUP_Val EQU 0x0000000F + +;// <e> Port G Settings +;// <h> Port G Control Register (GPGCON) +;// <o1.30..31> GPG15 <0=> Input <1=> Output <2=> EINT[23] <3=> Reserved +;// <o1.28..29> GPG14 <0=> Input <1=> Output <2=> EINT[22] <3=> Reserved +;// <o1.26..27> GPG13 <0=> Input <1=> Output <2=> EINT[21] <3=> Reserved +;// <o1.24..25> GPG12 <0=> Input <1=> Output <2=> EINT[20] <3=> Reserved +;// <o1.22..23> GPG11 <0=> Input <1=> Output <2=> EINT[19] <3=> TCLK[1] +;// <o1.20..21> GPG10 <0=> Input <1=> Output <2=> EINT[18] <3=> nCTS1 +;// <o1.18..19> GPG9 <0=> Input <1=> Output <2=> EINT[17] <3=> nRTS1 +;// <o1.16..17> GPG8 <0=> Input <1=> Output <2=> EINT[16] <3=> Reserved +;// <o1.14..15> GPG7 <0=> Input <1=> Output <2=> EINT[15] <3=> SPICLK1 +;// <o1.12..13> GPG6 <0=> Input <1=> Output <2=> EINT[14] <3=> SPIMOSI1 +;// <o1.10..11> GPG5 <0=> Input <1=> Output <2=> EINT[13] <3=> SPIMISO1 +;// <o1.8..9> GPG4 <0=> Input <1=> Output <2=> EINT[12] <3=> LCD_PWRDN +;// <o1.6..7> GPG3 <0=> Input <1=> Output <2=> EINT[11] <3=> nSS1 +;// <o1.4..5> GPG2 <0=> Input <1=> Output <2=> EINT[10] <3=> nSS0 +;// <o1.2..3> GPG1 <0=> Input <1=> Output <2=> EINT[9] <3=> Reserved +;// <o1.0..1> GPG0 <0=> Input <1=> Output <2=> EINT[8] <3=> Reserved +;// </h> +;// <h> Port G Pull-up Settings Register (GPGUP) +;// <o2.15> GPG15 Pull-up Disable +;// <o2.14> GPG14 Pull-up Disable +;// <o2.13> GPG13 Pull-up Disable +;// <o2.12> GPG12 Pull-up Disable +;// <o2.11> GPG11 Pull-up Disable +;// <o2.10> GPG10 Pull-up Disable +;// <o2.9> GPG9 Pull-up Disable +;// <o2.8> GPG8 Pull-up Disable +;// <o2.7> GPG7 Pull-up Disable +;// <o2.6> GPG6 Pull-up Disable +;// <o2.5> GPG5 Pull-up Disable +;// <o2.4> GPG4 Pull-up Disable +;// <o2.3> GPG3 Pull-up Disable +;// <o2.2> GPG2 Pull-up Disable +;// <o2.1> GPG1 Pull-up Disable +;// <o2.0> GPG0 Pull-up Disable +;// </h> +;// </e> +GPG_SETUP EQU 0 +GPGCON_Val EQU 0x00000000 +GPGUP_Val EQU 0x00000000 + +;// <e> Port H Settings +;// <h> Port H Control Register (GPHCON) +;// <o1.20..21> GPH10 <0=> Input <1=> Output <2=> CLKOUT1 <3=> Reserved +;// <o1.18..19> GPH9 <0=> Input <1=> Output <2=> CLKOUT0 <3=> Reserved +;// <o1.16..17> GPH8 <0=> Input <1=> Output <2=> UEXTCLK <3=> Reserved +;// <o1.14..15> GPH7 <0=> Input <1=> Output <2=> RXD[2] <3=> nCTS1 +;// <o1.12..13> GPH6 <0=> Input <1=> Output <2=> TXD[2] <3=> nRTS1 +;// <o1.10..11> GPH5 <0=> Input <1=> Output <2=> RXD[1] <3=> Reserved +;// <o1.8..9> GPH4 <0=> Input <1=> Output <2=> TXD[1] <3=> Reserved +;// <o1.6..7> GPH3 <0=> Input <1=> Output <2=> RXD[0] <3=> Reserved +;// <o1.4..5> GPH2 <0=> Input <1=> Output <2=> TXD[0] <3=> Reserved +;// <o1.2..3> GPH1 <0=> Input <1=> Output <2=> nRTS0 <3=> Reserved +;// <o1.0..1> GPH0 <0=> Input <1=> Output <2=> nCTS0 <3=> Reserved +;// </h> +;// <h> Port H Pull-up Settings Register (GPHUP) +;// <o2.10> GPH10 Pull-up Disable +;// <o2.9> GPH9 Pull-up Disable +;// <o2.8> GPH8 Pull-up Disable +;// <o2.7> GPH7 Pull-up Disable +;// <o2.6> GPH6 Pull-up Disable +;// <o2.5> GPH5 Pull-up Disable +;// <o2.4> GPH4 Pull-up Disable +;// <o2.3> GPH3 Pull-up Disable +;// <o2.2> GPH2 Pull-up Disable +;// <o2.1> GPH1 Pull-up Disable +;// <o2.0> GPH0 Pull-up Disable +;// </h> +;// </e> +GPH_SETUP EQU 0 +GPHCON_Val EQU 0x00000000 +GPHUP_Val EQU 0x00000000 + +;// <e> Port J Settings +;// <h> Port J Control Register (GPJCON) +;// <o1.24..25> GPJ12 <0=> Input <1=> Output <2=> CAMRESET <3=> Reserved +;// <o1.22..23> GPJ11 <0=> Input <1=> Output <2=> CAMCLKOUT <3=> Reserved +;// <o1.20..21> GPJ10 <0=> Input <1=> Output <2=> CAMHREF <3=> Reserved +;// <o1.18..19> GPJ9 <0=> Input <1=> Output <2=> CAMVSYNC <3=> Reserved +;// <o1.16..17> GPJ8 <0=> Input <1=> Output <2=> CAMPCLK <3=> Reserved +;// <o1.14..15> GPJ7 <0=> Input <1=> Output <2=> CAMDATA[7] <3=> Reserved +;// <o1.12..13> GPJ6 <0=> Input <1=> Output <2=> CAMDATA[6] <3=> Reserved +;// <o1.10..11> GPJ5 <0=> Input <1=> Output <2=> CAMDATA[5] <3=> Reserved +;// <o1.8..9> GPJ4 <0=> Input <1=> Output <2=> CAMDATA[4] <3=> Reserved +;// <o1.6..7> GPJ3 <0=> Input <1=> Output <2=> CAMDATA[3] <3=> Reserved +;// <o1.4..5> GPJ2 <0=> Input <1=> Output <2=> CAMDATA[2] <3=> Reserved +;// <o1.2..3> GPJ1 <0=> Input <1=> Output <2=> CAMDATA[1] <3=> Reserved +;// <o1.0..1> GPJ0 <0=> Input <1=> Output <2=> CAMDATA[0] <3=> Reserved +;// </h> +;// <h> Port J Pull-up Settings Register (GPJUP) +;// <o2.12> GPJ12 Pull-up Disable +;// <o2.11> GPJ11 Pull-up Disable +;// <o2.10> GPJ10 Pull-up Disable +;// <o2.9> GPJ9 Pull-up Disable +;// <o2.8> GPJ8 Pull-up Disable +;// <o2.7> GPJ7 Pull-up Disable +;// <o2.6> GPJ6 Pull-up Disable +;// <o2.5> GPJ5 Pull-up Disable +;// <o2.4> GPJ4 Pull-up Disable +;// <o2.3> GPJ3 Pull-up Disable +;// <o2.2> GPJ2 Pull-up Disable +;// <o2.1> GPJ1 Pull-up Disable +;// <o2.0> GPJ0 Pull-up Disable +;// </h> +;// </e> +GPJ_SETUP EQU 0 +GPJCON_Val EQU 0x00000000 +GPJUP_Val EQU 0x00000000 + +;// </e> I/O Setup + + +;----------------------- CODE -------------------------------------------------- + + PRESERVE8 + + +; Area Definition and Entry Point +; Startup Code must be linked first at Address at which it expects to run. + + AREA RESET, CODE, READONLY + ARM + +; Exception Vectors +; Mapped to Address 0. +; Absolute addressing mode must be used. +; Dummy Handlers are implemented as infinite loops which can be modified. + + EXPORT Entry_Point +Entry_Point +Vectors LDR PC, Reset_Addr + LDR PC, Undef_Addr + LDR PC, SWI_Addr + LDR PC, PAbt_Addr + LDR PC, DAbt_Addr + NOP + LDR PC, IRQ_Addr + LDR PC, FIQ_Addr + +Reset_Addr DCD Reset_Handler +Undef_Addr DCD Undef_Handler +SWI_Addr DCD SWI_Handler +PAbt_Addr DCD PAbt_Handler +DAbt_Addr DCD DAbt_Handler + DCD 0 ; Reserved Address +IRQ_Addr DCD IRQ_Handler +FIQ_Addr DCD FIQ_Handler + +Undef_Handler B Undef_Handler +SWI_Handler B SWI_Handler +PAbt_Handler B PAbt_Handler +;DAbt_Handler B DAbt_Handler +FIQ_Handler B FIQ_Handler + +;* +;************************************************************************* +;* +;* Interrupt handling +;* +;************************************************************************* +;* +; DAbt Handler +DAbt_Handler + IMPORT rt_hw_trap_dabt + + sub sp, sp, #72 + stmia sp, {r0 - r12} ;/* Calling r0-r12 */ + add r8, sp, #60 + stmdb r8, {sp, lr} ;/* Calling SP, LR */ + str lr, [r8, #0] ;/* Save calling PC */ + mrs r6, spsr + str r6, [r8, #4] ;/* Save CPSR */ + str r0, [r8, #8] ;/* Save OLD_R0 */ + mov r0, sp + + bl rt_hw_trap_dabt + + +;########################################## +; Reset Handler + + EXPORT Reset_Handler +Reset_Handler + + +; Watchdog Setup --------------------------------------------------------------- + + IF WT_SETUP != 0 + LDR R0, =WT_BASE + LDR R1, =WTCON_Val + LDR R2, =WTDAT_Val + STR R2, [R0, #WTCNT_OFS] + STR R2, [R0, #WTDAT_OFS] + STR R1, [R0, #WTCON_OFS] + ENDIF + + +; Clock Setup ------------------------------------------------------------------ + + IF (:LNOT:(:DEF:NO_CLOCK_SETUP)):LAND:(CLOCK_SETUP != 0) + LDR R0, =CLOCK_BASE + LDR R1, =LOCKTIME_Val + STR R1, [R0, #LOCKTIME_OFS] + MOV R1, #CLKDIVN_Val + STR R1, [R0, #CLKDIVN_OFS] + LDR R1, =CAMDIVN_Val + STR R1, [R0, #CAMDIVN_OFS] + LDR R1, =MPLLCON_Val + STR R1, [R0, #MPLLCON_OFS] + LDR R1, =UPLLCON_Val + STR R1, [R0, #UPLLCON_OFS] + MOV R1, #CLKSLOW_Val + STR R1, [R0, #CLKSLOW_OFS] + LDR R1, =CLKCON_Val + STR R1, [R0, #CLKCON_OFS] + ENDIF + + +; Memory Controller Setup ------------------------------------------------------ + + IF (:LNOT:(:DEF:NO_MC_SETUP)):LAND:(CLOCK_SETUP != 0) + LDR R0, =MC_BASE + LDR R1, =BWSCON_Val + STR R1, [R0, #BWSCON_OFS] + LDR R1, =BANKCON0_Val + STR R1, [R0, #BANKCON0_OFS] + LDR R1, =BANKCON1_Val + STR R1, [R0, #BANKCON1_OFS] + LDR R1, =BANKCON2_Val + STR R1, [R0, #BANKCON2_OFS] + LDR R1, =BANKCON3_Val + STR R1, [R0, #BANKCON3_OFS] + LDR R1, =BANKCON4_Val + STR R1, [R0, #BANKCON4_OFS] + LDR R1, =BANKCON5_Val + STR R1, [R0, #BANKCON5_OFS] + LDR R1, =BANKCON6_Val + STR R1, [R0, #BANKCON6_OFS] + LDR R1, =BANKCON7_Val + STR R1, [R0, #BANKCON7_OFS] + LDR R1, =REFRESH_Val + STR R1, [R0, #REFRESH_OFS] + MOV R1, #BANKSIZE_Val + STR R1, [R0, #BANKSIZE_OFS] + MOV R1, #MRSRB6_Val + STR R1, [R0, #MRSRB6_OFS] + MOV R1, #MRSRB7_Val + STR R1, [R0, #MRSRB7_OFS] + ENDIF + + +; I/O Pins Setup --------------------------------------------------------------- + + IF (:LNOT:(:DEF:NO_GP_SETUP)):LAND:(GP_SETUP != 0) + + IF GPA_SETUP != 0 + LDR R0, =GPA_BASE + LDR R1, =GPACON_Val + STR R1, [R0, #GPCON_OFS] + ENDIF + + IF GPB_SETUP != 0 + LDR R0, =GPB_BASE + LDR R1, =GPBCON_Val + STR R1, [R0, #GPCON_OFS] + LDR R1, =GPBUP_Val + STR R1, [R0, #GPUP_OFS] + ENDIF + + IF GPC_SETUP != 0 + LDR R0, =GPC_BASE + LDR R1, =GPCCON_Val + STR R1, [R0, #GPCON_OFS] + LDR R1, =GPCUP_Val + STR R1, [R0, #GPUP_OFS] + ENDIF + + IF GPD_SETUP != 0 + LDR R0, =GPD_BASE + LDR R1, =GPDCON_Val + STR R1, [R0, #GPCON_OFS] + LDR R1, =GPDUP_Val + STR R1, [R0, #GPUP_OFS] + ENDIF + + IF GPE_SETUP != 0 + LDR R0, =GPE_BASE + LDR R1, =GPECON_Val + STR R1, [R0, #GPCON_OFS] + LDR R1, =GPEUP_Val + STR R1, [R0, #GPUP_OFS] + ENDIF + + IF GPF_SETUP != 0 + LDR R0, =GPF_BASE + LDR R1, =GPFCON_Val + STR R1, [R0, #GPCON_OFS] + LDR R1, =GPFUP_Val + STR R1, [R0, #GPUP_OFS] + ENDIF + + IF GPG_SETUP != 0 + LDR R0, =GPG_BASE + LDR R1, =GPGCON_Val + STR R1, [R0, #GPCON_OFS] + LDR R1, =GPGUP_Val + STR R1, [R0, #GPUP_OFS] + ENDIF + + IF GPH_SETUP != 0 + LDR R0, =GPH_BASE + LDR R1, =GPHCON_Val + STR R1, [R0, #GPCON_OFS] + LDR R1, =GPHUP_Val + STR R1, [R0, #GPUP_OFS] + ENDIF + + IF GPJ_SETUP != 0 + LDR R0, =GPJ_BASE + LDR R1, =GPJCON_Val + STR R1, [R0, #GPCON_OFS] + LDR R1, =GPJUP_Val + STR R1, [R0, #GPUP_OFS] + ENDIF + + ENDIF + + +; Copy Exception Vectors to Internal RAM --------------------------------------- + + IF :DEF:RAM_INTVEC + ADR R8, Vectors ; Source + LDR R9, =IRAM_BASE ; Destination + LDMIA R8!, {R0-R7} ; Load Vectors + STMIA R9!, {R0-R7} ; Store Vectors + LDMIA R8!, {R0-R7} ; Load Handler Addresses + STMIA R9!, {R0-R7} ; Store Handler Addresses + ENDIF + + +; Setup Stack for each mode ---------------------------------------------------- + + LDR R0, =Stack_Top + +; Enter Undefined Instruction Mode and set its Stack Pointer + MSR CPSR_c, #Mode_UND:OR:I_Bit:OR:F_Bit + MOV SP, R0 + SUB R0, R0, #UND_Stack_Size + +; Enter Abort Mode and set its Stack Pointer + MSR CPSR_c, #Mode_ABT:OR:I_Bit:OR:F_Bit + MOV SP, R0 + SUB R0, R0, #ABT_Stack_Size + +; Enter FIQ Mode and set its Stack Pointer + MSR CPSR_c, #Mode_FIQ:OR:I_Bit:OR:F_Bit + MOV SP, R0 + SUB R0, R0, #FIQ_Stack_Size + +; Enter IRQ Mode and set its Stack Pointer + MSR CPSR_c, #Mode_IRQ:OR:I_Bit:OR:F_Bit + MOV SP, R0 + SUB R0, R0, #IRQ_Stack_Size + +; Enter Supervisor Mode and set its Stack Pointer + MSR CPSR_c, #Mode_SVC:OR:I_Bit:OR:F_Bit + MOV SP, R0 + SUB R0, R0, #SVC_Stack_Size + +; Enter User Mode and set its Stack Pointer + ; MSR CPSR_c, #Mode_USR + MOV SP, R0 + SUB SL, SP, #USR_Stack_Size + +; Enter the C code ------------------------------------------------------------- + + IMPORT __main + LDR R0, =__main + BX R0 + + IMPORT rt_interrupt_enter + IMPORT rt_interrupt_leave + IMPORT rt_thread_switch_interrupt_flag + IMPORT rt_interrupt_from_thread + IMPORT rt_interrupt_to_thread + IMPORT rt_hw_trap_irq + +IRQ_Handler PROC + EXPORT IRQ_Handler + STMFD sp!, {r0-r12,lr} + BL rt_interrupt_enter + BL rt_hw_trap_irq + BL rt_interrupt_leave + + ; if rt_thread_switch_interrupt_flag set, jump to + ; rt_hw_context_switch_interrupt_do and don't return + LDR r0, =rt_thread_switch_interrupt_flag + LDR r1, [r0] + CMP r1, #1 + BEQ rt_hw_context_switch_interrupt_do + + LDMFD sp!, {r0-r12,lr} + SUBS pc, lr, #4 + ENDP + +; /* +; * void rt_hw_context_switch_interrupt_do(rt_base_t flag) +; */ +rt_hw_context_switch_interrupt_do PROC + EXPORT rt_hw_context_switch_interrupt_do + MOV r1, #0 ; clear flag + STR r1, [r0] + + LDMFD sp!, {r0-r12,lr}; reload saved registers + STMFD sp!, {r0-r3} ; save r0-r3 + MOV r1, sp + ADD sp, sp, #16 ; restore sp + SUB r2, lr, #4 ; save old task's pc to r2 + + MRS r3, spsr ; get cpsr of interrupt thread + + ; switch to SVC mode and no interrupt + MSR cpsr_c, #I_Bit:OR:F_Bit:OR:Mode_SVC + + STMFD sp!, {r2} ; push old task's pc + STMFD sp!, {r4-r12,lr}; push old task's lr,r12-r4 + MOV r4, r1 ; Special optimised code below + MOV r5, r3 + LDMFD r4!, {r0-r3} + STMFD sp!, {r0-r3} ; push old task's r3-r0 + STMFD sp!, {r5} ; push old task's cpsr + MRS r4, spsr + STMFD sp!, {r4} ; push old task's spsr + + LDR r4, =rt_interrupt_from_thread + LDR r5, [r4] + STR sp, [r5] ; store sp in preempted tasks's TCB + + LDR r6, =rt_interrupt_to_thread + LDR r6, [r6] + LDR sp, [r6] ; get new task's stack pointer + + LDMFD sp!, {r4} ; pop new task's spsr + MSR spsr_cxsf, r4 + LDMFD sp!, {r4} ; pop new task's psr + MSR cpsr_cxsf, r4 + + LDMFD sp!, {r0-r12,lr,pc} ; pop new task's r0-r12,lr & pc + ENDP + + IF :DEF:__MICROLIB + + EXPORT __heap_base + EXPORT __heap_limit + + ELSE +; User Initial Stack & Heap + AREA |.text|, CODE, READONLY + + IMPORT __use_two_region_memory + EXPORT __user_initial_stackheap +__user_initial_stackheap + + LDR R0, = Heap_Mem + LDR R1, =(Stack_Mem + USR_Stack_Size) + LDR R2, = (Heap_Mem + Heap_Size) + LDR R3, = Stack_Mem + BX LR + ENDIF + + + END + diff --git a/libcpu/arm/s3c24x0/system_clock.c b/libcpu/arm/s3c24x0/system_clock.c index bd2a6690db..c87c5966e9 100644 --- a/libcpu/arm/s3c24x0/system_clock.c +++ b/libcpu/arm/s3c24x0/system_clock.c @@ -1,108 +1,108 @@ -/*
- * File : clock.c
- * This file is part of RT-Thread RTOS
- * COPYRIGHT (C) 2006, RT-Thread Development Team
- *
- * The license and distribution terms for this file may be
- * found in the file LICENSE in this distribution or at
- * http://openlab.rt-thread.com/license/LICENSE
- *
- * Change Logs:
- * Date Author Notes
- * 2008-04-25 Yi.qiu first version
- */
-
-#include <rtthread.h>
-#include "s3c24x0.h"
-
-#define CONFIG_SYS_CLK_FREQ 12000000 // Fin = 12.00MHz
-
-#if CONFIG_SYS_CLK_FREQ == 12000000
- /* MPLL=2*12*100/6=400MHz */
- #define MPL_MIDV 92 /* m=MPL_MDIV+8=100 */
- #define MPL_PDIV 4 /* p=MPL_PDIV+2=6 */
- #define MPL_SDIV 0 /* s=MPL_SDIV=0 */
- /* UPLL=12*64/8=96MHz */
- #define UPL_MDIV 56 /* m=UPL_MDIV+8=64 */
- #define UPL_PDIV 2 /* p=UPL_PDIV+2=4 */
- #define UPL_SDIV 1 /* s=UPL_SDIV=1 */
- /* System clock divider FCLK:HCLK:PCLK=1:4:8 */
- #define DIVN_UPLL 0x1 /* UCLK = UPLL clock / 2 */
- #define HDIVN 0x2 /* HCLK = FCLK / 4 */
- #define PDIVN 0x1 /* PCLK = HCLK / 2 */
-#endif
-
-rt_uint32_t PCLK;
-rt_uint32_t FCLK;
-rt_uint32_t HCLK;
-rt_uint32_t UCLK;
-
-void rt_hw_get_clock(void)
-{
- rt_uint32_t val;
- rt_uint8_t m, p, s;
-
- val = MPLLCON;
- m = (val>>12)&0xff;
- p = (val>>4)&0x3f;
- s = val&3;
-
- FCLK = ((m+8)*(CONFIG_SYS_CLK_FREQ/100)*2)/((p+2)*(1<<s))*100;
-
- val = CLKDIVN;
- m = (val>>1)&3;
- p = val&1;
-
- switch (m) {
- case 0:
- HCLK = FCLK;
- break;
- case 1:
- HCLK = FCLK>>1;
- break;
- case 2:
- if(s&2)
- HCLK = FCLK>>3;
- else
- HCLK = FCLK>>2;
- break;
- case 3:
- if(s&1)
- HCLK = FCLK/6;
- else
- HCLK = FCLK/3;
- break;
-}
-
- if(p)
- PCLK = HCLK>>1;
- else
- PCLK = HCLK;
-}
-
-void rt_hw_set_mpll_clock(rt_uint8_t sdiv, rt_uint8_t pdiv, rt_uint8_t mdiv)
-{
- MPLLCON = sdiv | (pdiv<<4) | (mdiv<<12);
-}
-
-void rt_hw_set_upll_clock(rt_uint8_t sdiv, rt_uint8_t pdiv, rt_uint8_t mdiv)
-{
- UPLLCON = (mdiv<<12) | (pdiv<<4) | sdiv;
-}
-
-void rt_hw_set_divider(rt_uint8_t hdivn, rt_uint8_t pdivn)
-{
- CLKDIVN = (hdivn<<1) | pdivn;
-}
-
-/**
- * @brief System Clock Configuration
- */
-void rt_hw_clock_init(void)
-{
- LOCKTIME = 0xFFFFFFFF;
- rt_hw_set_mpll_clock(MPL_SDIV, MPL_PDIV, MPL_MIDV);
- rt_hw_set_upll_clock(UPL_SDIV, UPL_PDIV, UPL_MDIV);
- rt_hw_set_divider(HDIVN, PDIVN);
-}
-
+/* + * File : clock.c + * This file is part of RT-Thread RTOS + * COPYRIGHT (C) 2006, RT-Thread Development Team + * + * The license and distribution terms for this file may be + * found in the file LICENSE in this distribution or at + * http://openlab.rt-thread.com/license/LICENSE + * + * Change Logs: + * Date Author Notes + * 2008-04-25 Yi.qiu first version + */ + +#include <rtthread.h> +#include "s3c24x0.h" + +#define CONFIG_SYS_CLK_FREQ 12000000 // Fin = 12.00MHz + +#if CONFIG_SYS_CLK_FREQ == 12000000 + /* MPLL=2*12*100/6=400MHz */ + #define MPL_MIDV 92 /* m=MPL_MDIV+8=100 */ + #define MPL_PDIV 4 /* p=MPL_PDIV+2=6 */ + #define MPL_SDIV 0 /* s=MPL_SDIV=0 */ + /* UPLL=12*64/8=96MHz */ + #define UPL_MDIV 56 /* m=UPL_MDIV+8=64 */ + #define UPL_PDIV 2 /* p=UPL_PDIV+2=4 */ + #define UPL_SDIV 1 /* s=UPL_SDIV=1 */ + /* System clock divider FCLK:HCLK:PCLK=1:4:8 */ + #define DIVN_UPLL 0x1 /* UCLK = UPLL clock / 2 */ + #define HDIVN 0x2 /* HCLK = FCLK / 4 */ + #define PDIVN 0x1 /* PCLK = HCLK / 2 */ +#endif + +rt_uint32_t PCLK; +rt_uint32_t FCLK; +rt_uint32_t HCLK; +rt_uint32_t UCLK; + +void rt_hw_get_clock(void) +{ + rt_uint32_t val; + rt_uint8_t m, p, s; + + val = MPLLCON; + m = (val>>12)&0xff; + p = (val>>4)&0x3f; + s = val&3; + + FCLK = ((m+8)*(CONFIG_SYS_CLK_FREQ/100)*2)/((p+2)*(1<<s))*100; + + val = CLKDIVN; + m = (val>>1)&3; + p = val&1; + + switch (m) { + case 0: + HCLK = FCLK; + break; + case 1: + HCLK = FCLK>>1; + break; + case 2: + if(s&2) + HCLK = FCLK>>3; + else + HCLK = FCLK>>2; + break; + case 3: + if(s&1) + HCLK = FCLK/6; + else + HCLK = FCLK/3; + break; +} + + if(p) + PCLK = HCLK>>1; + else + PCLK = HCLK; +} + +void rt_hw_set_mpll_clock(rt_uint8_t sdiv, rt_uint8_t pdiv, rt_uint8_t mdiv) +{ + MPLLCON = sdiv | (pdiv<<4) | (mdiv<<12); +} + +void rt_hw_set_upll_clock(rt_uint8_t sdiv, rt_uint8_t pdiv, rt_uint8_t mdiv) +{ + UPLLCON = (mdiv<<12) | (pdiv<<4) | sdiv; +} + +void rt_hw_set_divider(rt_uint8_t hdivn, rt_uint8_t pdivn) +{ + CLKDIVN = (hdivn<<1) | pdivn; +} + +/** + * @brief System Clock Configuration + */ +void rt_hw_clock_init(void) +{ + LOCKTIME = 0xFFFFFFFF; + rt_hw_set_mpll_clock(MPL_SDIV, MPL_PDIV, MPL_MIDV); + rt_hw_set_upll_clock(UPL_SDIV, UPL_PDIV, UPL_MDIV); + rt_hw_set_divider(HDIVN, PDIVN); +} + diff --git a/libcpu/arm/s3c24x0/trap.c b/libcpu/arm/s3c24x0/trap.c index 09f1c88bca..bdeae9aab0 100644 --- a/libcpu/arm/s3c24x0/trap.c +++ b/libcpu/arm/s3c24x0/trap.c @@ -157,7 +157,7 @@ void rt_hw_trap_irq() /* turn to interrupt service routine */ isr_func(intstat); - /* clear pending register */
+ /* clear pending register */ /* note: must be the last, if not, may repeat*/ ClearPending(1 << intstat); } diff --git a/libcpu/arm/s3c44b0/context_rvds.S b/libcpu/arm/s3c44b0/context_rvds.S index e24fa62a3d..641ec7a6b1 100644 --- a/libcpu/arm/s3c44b0/context_rvds.S +++ b/libcpu/arm/s3c44b0/context_rvds.S @@ -12,12 +12,12 @@ ; * 2009-01-20 Bernard first version ; */ -NOINT EQU 0xc0 ; disable interrupt in psr
+NOINT EQU 0xc0 ; disable interrupt in psr - AREA |.text|, CODE, READONLY, ALIGN=2
- ARM
- REQUIRE8
- PRESERVE8
+ AREA |.text|, CODE, READONLY, ALIGN=2 + ARM + REQUIRE8 + PRESERVE8 ;/* ; * rt_base_t rt_hw_interrupt_disable(); @@ -26,16 +26,16 @@ rt_hw_interrupt_disable PROC EXPORT rt_hw_interrupt_disable MRS r0, cpsr ORR r1, r0, #NOINT - MSR cpsr_c, r1
+ MSR cpsr_c, r1 BX lr - ENDP
+ ENDP ;/* ; * void rt_hw_interrupt_enable(rt_base_t level); ; */ rt_hw_interrupt_enable PROC EXPORT rt_hw_interrupt_enable - MSR cpsr_c, r0
+ MSR cpsr_c, r0 BX lr ENDP @@ -63,7 +63,7 @@ rt_hw_context_switch PROC MSR cpsr_cxsf, r4 LDMFD sp!, {r0-r12, lr, pc} ; pop new task r0-r12, lr & pc - ENDP
+ ENDP ;/* ; * void rt_hw_context_switch_to(rt_uint32 to); @@ -79,14 +79,14 @@ rt_hw_context_switch_to PROC MSR cpsr_cxsf, r4 LDMFD sp!, {r0-r12, lr, pc} ; pop new task r0-r12, lr & pc - ENDP
+ ENDP ;/* ; * void rt_hw_context_switch_interrupt(rt_uint32 from, rt_uint32 to); ; */ IMPORT rt_thread_switch_interrupt_flag IMPORT rt_interrupt_from_thread - IMPORT rt_interrupt_to_thread
+ IMPORT rt_interrupt_to_thread rt_hw_context_switch_interrupt PROC EXPORT rt_hw_context_switch_interrupt @@ -100,8 +100,8 @@ rt_hw_context_switch_interrupt PROC STR r0, [r2] _reswitch LDR r2, =rt_interrupt_to_thread ; set rt_interrupt_to_thread - STR r1, [r2]
+ STR r1, [r2] BX lr - ENDP
-
+ ENDP + END
\ No newline at end of file diff --git a/libcpu/arm/s3c44b0/s3c44b0.h b/libcpu/arm/s3c44b0/s3c44b0.h index 36f9f5a1e4..16e8e3a240 100644 --- a/libcpu/arm/s3c44b0/s3c44b0.h +++ b/libcpu/arm/s3c44b0/s3c44b0.h @@ -213,27 +213,27 @@ extern "C" { #define F_ISPR (S3C_REG(0x1e00038)) #define F_ISPC (S3C_REG(0x1e0003c)) -/********************************/
-/* LCD Controller Registers */
-/********************************/
-#define LCDCON1 (S3C_REG(0x300000))
-#define LCDCON2 (S3C_REG(0x300004))
-#define LCDSADDR1 (S3C_REG(0x300008))
-#define LCDSADDR2 (S3C_REG(0x30000c))
-#define LCDSADDR3 (S3C_REG(0x300010))
-#define REDLUT (S3C_REG(0x300014))
-#define GREENLUT (S3C_REG(0x300018))
-#define BLUELUT (S3C_REG(0x30001c))
-#define DP1_2 (S3C_REG(0x300020))
-#define DP4_7 (S3C_REG(0x300024))
-#define DP3_5 (S3C_REG(0x300028))
-#define DP2_3 (S3C_REG(0x30002c))
-#define DP5_7 (S3C_REG(0x300030))
-#define DP3_4 (S3C_REG(0x300034))
-#define DP4_5 (S3C_REG(0x300038))
-#define DP6_7 (S3C_REG(0x30003c))
-#define LCDCON3 (S3C_REG(0x300040))
-#define DITHMODE (S3C_REG(0x300044))
+/********************************/ +/* LCD Controller Registers */ +/********************************/ +#define LCDCON1 (S3C_REG(0x300000)) +#define LCDCON2 (S3C_REG(0x300004)) +#define LCDSADDR1 (S3C_REG(0x300008)) +#define LCDSADDR2 (S3C_REG(0x30000c)) +#define LCDSADDR3 (S3C_REG(0x300010)) +#define REDLUT (S3C_REG(0x300014)) +#define GREENLUT (S3C_REG(0x300018)) +#define BLUELUT (S3C_REG(0x30001c)) +#define DP1_2 (S3C_REG(0x300020)) +#define DP4_7 (S3C_REG(0x300024)) +#define DP3_5 (S3C_REG(0x300028)) +#define DP2_3 (S3C_REG(0x30002c)) +#define DP5_7 (S3C_REG(0x300030)) +#define DP3_4 (S3C_REG(0x300034)) +#define DP4_5 (S3C_REG(0x300038)) +#define DP6_7 (S3C_REG(0x30003c)) +#define LCDCON3 (S3C_REG(0x300040)) +#define DITHMODE (S3C_REG(0x300044)) /* ZDMA0 */ #define ZDCON0 (S3C_REG(0x1e80000)) diff --git a/libcpu/arm/s3c44b0/start_gcc.S b/libcpu/arm/s3c44b0/start_gcc.S index ff9398c0b7..17a3d0da7f 100644 --- a/libcpu/arm/s3c44b0/start_gcc.S +++ b/libcpu/arm/s3c44b0/start_gcc.S @@ -238,20 +238,20 @@ stack_setup: .globl led_on led_on: - ldr r1, =0x1d20014 @ r1<-PDATC
- ldr r0, [r1] @ r0<-[r1]
- orr r0, r0, #0x0e @ r0=r0 or 0x0e
- str r0, [r1] @ r0->[r1]
+ ldr r1, =0x1d20014 @ r1<-PDATC + ldr r0, [r1] @ r0<-[r1] + orr r0, r0, #0x0e @ r0=r0 or 0x0e + str r0, [r1] @ r0->[r1] mov pc, lr .globl led_off led_off: - ldr r1, =0x1d20010 @ r1<-PCONC
- ldr r0, =0x5f555555 @ r0<-0x5f555555
- str r0, [r1] @ r0->[r1]
-
- ldr r1, =0x1d20014 @ r1<-PDATC
- ldr r0, =0x0 @ r0<-00
- str r0, [r1] @ r0->[r1]
-
- mov pc, lr
+ ldr r1, =0x1d20010 @ r1<-PCONC + ldr r0, =0x5f555555 @ r0<-0x5f555555 + str r0, [r1] @ r0->[r1] + + ldr r1, =0x1d20014 @ r1<-PDATC + ldr r0, =0x0 @ r0<-00 + str r0, [r1] @ r0->[r1] + + mov pc, lr diff --git a/libcpu/arm/s3c44b0/start_rvds.S b/libcpu/arm/s3c44b0/start_rvds.S index 192120dff5..b5c9048e12 100644 --- a/libcpu/arm/s3c44b0/start_rvds.S +++ b/libcpu/arm/s3c44b0/start_rvds.S @@ -1,1072 +1,1072 @@ -;/*****************************************************************************/
-;/* S3C44B0X.S: Startup file for Samsung S3C44B0X */
-;/*****************************************************************************/
-;/* <<< Use Configuration Wizard in Context Menu >>> */
-;/*****************************************************************************/
-;/* This file is part of the uVision/ARM development tools. */
-;/* Copyright (c) 2005-2006 Keil Software. All rights reserved. */
-;/* This software may only be used under the terms of a valid, current, */
-;/* end user licence from KEIL for a compatible version of KEIL software */
-;/* development tools. Nothing else gives you the right to use this software. */
-;/*****************************************************************************/
-
-
-; *** Startup Code (executed after Reset) ***
-
-
-; Standard definitions of Mode bits and Interrupt (I & F) flags in PSRs
-
-Mode_USR EQU 0x10
-Mode_FIQ EQU 0x11
-Mode_IRQ EQU 0x12
-Mode_SVC EQU 0x13
-Mode_ABT EQU 0x17
-Mode_UND EQU 0x1B
-Mode_SYS EQU 0x1F
-
-I_Bit EQU 0x80 ; when I bit is set, IRQ is disabled
-F_Bit EQU 0x40 ; when F bit is set, FIQ is disabled
-
-
-;// <h> Stack Configuration (Stack Sizes in Bytes)
-;// <o0> Undefined Mode <0x0-0xFFFFFFFF:8>
-;// <o1> Supervisor Mode <0x0-0xFFFFFFFF:8>
-;// <o2> Abort Mode <0x0-0xFFFFFFFF:8>
-;// <o3> Fast Interrupt Mode <0x0-0xFFFFFFFF:8>
-;// <o4> Interrupt Mode <0x0-0xFFFFFFFF:8>
-;// <o5> User/System Mode <0x0-0xFFFFFFFF:8>
-;// </h>
-
-UND_Stack_Size EQU 0x00000000
-SVC_Stack_Size EQU 0x00000100
-ABT_Stack_Size EQU 0x00000000
-FIQ_Stack_Size EQU 0x00000000
-IRQ_Stack_Size EQU 0x00000100
-USR_Stack_Size EQU 0x00000100
-
-ISR_Stack_Size EQU (UND_Stack_Size + SVC_Stack_Size + ABT_Stack_Size + \
- FIQ_Stack_Size + IRQ_Stack_Size)
-
- AREA STACK, NOINIT, READWRITE, ALIGN=3
-
-Stack_Mem SPACE USR_Stack_Size
-__initial_sp SPACE ISR_Stack_Size
-Stack_Top
-
-
-;// <h> Heap Configuration
-;// <o> Heap Size (in Bytes) <0x0-0xFFFFFFFF>
-;// </h>
-
-Heap_Size EQU 0x00000000
-
- AREA HEAP, NOINIT, READWRITE, ALIGN=3
-__heap_base
-Heap_Mem SPACE Heap_Size
-__heap_limit
-
-
-; CPU Wrapper and Bus Priorities definitions
-CPUW_BASE EQU 0x01C00000 ; CPU Wrapper Base Address
-SYSCFG_OFS EQU 0x00 ; SYSCFG Offset
-NCACHBE0_OFS EQU 0x04 ; NCACHBE0 Offset
-NCACHBE1_OFS EQU 0x08 ; NCACHBE0 Offset
-BUSP_BASE EQU 0x01C40000 ; Bus Priority Base Address
-SBUSCON_OFS EQU 0x00 ; SBUSCON Offset
-
-;// <e> CPU Wrapper and Bus Priorities
-;// <h> CPU Wrapper
-;// <o1.0> SE: Stall Enable
-;// <o1.1..2> CM: Cache Mode
-;// <0=> Disable Cache (8kB SRAM)
-;// <1=> Half Cache Enable (4kB Cache, 4kB SRAM)
-;// <2=> Reserved
-;// <3=> Full Cache Enable (8kB Cache)
-;// <o1.3> WE: Write Buffer Enable
-;// <o1.4> RSE: Read Stall Enable
-;// <o1.5> DA: Data Abort <0=> Enable <1=> Disable
-;// <h> Non-cacheable Area 0
-;// <o2.0..15> Start Address <0x0-0x0FFFF000:0x1000><#/0x1000>
-;// <i> SA = (Start Address) / 4k
-;// <o2.16..31> End Address + 1 <0x0-0x10000000:0x1000><#/0x1000>
-;// <i> SE = (End Address + 1) / 4k
-;// </h>
-;// <h> Non-cacheable Area 1
-;// <o3.0..15> Start Address <0x0-0x0FFFF000:0x1000><#/0x1000>
-;// <i> SA = (Start Address) / 4k
-;// <o3.16..31> End Address + 1 <0x0-0x10000000:0x1000><#/0x1000>
-;// <i> SE = (End Address + 1) / 4k
-;// </h>
-;// </h>
-;// <h> Bus Priorities
-;// <o4.31> FIX: Fixed Priorities
-;// <o4.6..7> LCD_DMA <0=> 1st <1=> 2nd <2=> 3rd <3=> 4th
-;// <o4.4..5> ZDMA <0=> 1st <1=> 2nd <2=> 3rd <3=> 4th
-;// <o4.2..3> BDMA <0=> 1st <1=> 2nd <2=> 3rd <3=> 4th
-;// <o4.0..1> nBREQ <0=> 1st <1=> 2nd <2=> 3rd <3=> 4th
-;// </h>
-;// </e>
-SYS_SETUP EQU 0
-SYSCFG_Val EQU 0x00000001
-NCACHBE0_Val EQU 0x00000000
-NCACHBE1_Val EQU 0x00000000
-SBUSCON_Val EQU 0x80001B1B
-
-
-;// <e> Vectored Interrupt Mode (for IRQ)
-;// <o1.25> EINT0 <i> External Interrupt 0
-;// <o1.24> EINT1 <i> External Interrupt 1
-;// <o1.23> EINT2 <i> External Interrupt 2
-;// <o1.22> EINT3 <i> External Interrupt 3
-;// <o1.21> EINT4567 <i> External Interrupt 4/5/6/7
-;// <o1.20> TICK <i> RTC Time Tick Interrupt
-;// <o1.19> ZDMA0 <i> General DMA0 Interrupt
-;// <o1.18> ZDMA1 <i> General DMA1 Interrupt
-;// <o1.17> BDMA0 <i> Bridge DMA0 Interrupt
-;// <o1.16> BDMA1 <i> Bridge DMA1 Interrupt
-;// <o1.15> WDT <i> Watchdog Timer Interrupt
-;// <o1.14> UERR01 <i> UART0/1 Error Interrupt
-;// <o1.13> TIMER0 <i> Timer0 Interrupt
-;// <o1.12> TIMER1 <i> Timer1 Interrupt
-;// <o1.11> TIMER2 <i> Timer2 Interrupt
-;// <o1.10> TIMER3 <i> Timer3 Interrupt
-;// <o1.9> TIMER4 <i> Timer4 Interrupt
-;// <o1.8> TIMER5 <i> Timer5 Interrupt
-;// <o1.7> URXD0 <i> UART0 Rx Interrupt
-;// <o1.6> URXD1 <i> UART1 Rx Interrupt
-;// <o1.5> IIC <i> IIC Interrupt
-;// <o1.4> SIO <i> SIO Interrupt
-;// <o1.3> UTXD0 <i> UART0 Tx Interrupt
-;// <o1.2> UTXD1 <i> UART1 Tx Interrupt
-;// <o1.1> RTC <i> RTC Alarm Interrupt
-;// <o1.0> ADC <i> ADC EOC Interrupt
-;// </e>
-VIM_SETUP EQU 0
-VIM_CFG EQU 0x00000000
-
-
-; Clock Management definitions
-CLK_BASE EQU 0x01D80000 ; Clock Base Address
-PLLCON_OFS EQU 0x00 ; PLLCON Offset
-CLKCON_OFS EQU 0x04 ; CLKCON Offset
-CLKSLOW_OFS EQU 0x08 ; CLKSLOW Offset
-LOCKTIME_OFS EQU 0x0C ; LOCKTIME Offset
-
-;// <e> Clock Management
-;// <h> PLL Settings
-;// <i> Fpllo = (m * Fin) / (p * 2^s), 20MHz < Fpllo < 66MHz
-;// <o1.12..19> MDIV: Main divider <0x0-0xFF>
-;// <i> m = MDIV + 8
-;// <o1.4..9> PDIV: Pre-divider <0x0-0x3F>
-;// <i> p = PDIV + 2, 1MHz <= Fin/p < 2MHz
-;// <o1.0..1> SDIV: Post Divider <0x0-0x03>
-;// <i> s = SDIV, Fpllo * 2^s < 170MHz
-;// <o4.0..11> LTIME CNT: PLL Lock Time Count <0x0-0x0FFF>
-;// </h>
-;// <h> Master Clock
-;// <i> PLL Clock: Fout = Fpllo
-;// <i> Slow Clock: Fout = Fin / (2 * SLOW_VAL), SLOW_VAL > 0
-;// <i> Slow Clock: Fout = Fin, SLOW_VAL = 0
-;// <o3.5> PLL_OFF: PLL Off
-;// <i> PLL is turned Off only when SLOW_BIT = 1
-;// <o3.4> SLOW_BIT: Slow Clock
-;// <o3.0..3> SLOW_VAL: Slow Clock divider <0x0-0x0F>
-;// </h>
-;// <h> Clock Generation
-;// <o2.14> IIS <0=> Disable <1=> Enable
-;// <o2.13> IIC <0=> Disable <1=> Enable
-;// <o2.12> ADC <0=> Disable <1=> Enable
-;// <o2.11> RTC <0=> Disable <1=> Enable
-;// <o2.10> GPIO <0=> Disable <1=> Enable
-;// <o2.9> UART1 <0=> Disable <1=> Enable
-;// <o2.8> UART0 <0=> Disable <1=> Enable
-;// <o2.7> BDMA0,1 <0=> Disable <1=> Enable
-;// <o2.6> LCDC <0=> Disable <1=> Enable
-;// <o2.5> SIO <0=> Disable <1=> Enable
-;// <o2.4> ZDMA0,1 <0=> Disable <1=> Enable
-;// <o2.3> PWMTIMER <0=> Disable <1=> Enable
-;// </h>
-;// </e>
-CLK_SETUP EQU 1
-PLLCON_Val EQU 0x00038080
-CLKCON_Val EQU 0x00007FF8
-CLKSLOW_Val EQU 0x00000009
-LOCKTIME_Val EQU 0x00000FFF
-
-
-; Watchdog Timer definitions
-WT_BASE EQU 0x01D30000 ; WT Base Address
-WTCON_OFS EQU 0x00 ; WTCON Offset
-WTDAT_OFS EQU 0x04 ; WTDAT Offset
-WTCNT_OFS EQU 0x08 ; WTCNT Offset
-
-;// <e> Watchdog Timer
-;// <o1.5> Watchdog Timer Enable/Disable
-;// <o1.0> Reset Enable/Disable
-;// <o1.2> Interrupt Enable/Disable
-;// <o1.3..4> Clock Select
-;// <0=> 1/16 <1=> 1/32 <2=> 1/64 <3=> 1/128
-;// <i> Clock Division Factor
-;// <o1.8..15> Prescaler Value <0x0-0xFF>
-;// <o2.0..15> Time-out Value <0x0-0xFFFF>
-;// </e>
-WT_SETUP EQU 1
-WTCON_Val EQU 0x00008000
-WTDAT_Val EQU 0x00008000
-
-
-; Memory Controller definitions
-MC_BASE EQU 0x01C80000 ; Memory Controller Base Address
-
-;// <e> Memory Controller
-MC_SETUP EQU 1
-
-;// <h> Bank 0
-;// <o0.0..1> PMC: Page Mode Configuration
-;// <0=> 1 Data <1=> 4 Data <2=> 8 Data <3=> 16 Data
-;// <o0.2..3> Tpac: Page Mode Access Cycle
-;// <0=> 2 clks <1=> 3 clks <2=> 4 clks <3=> 6 clks
-;// <o0.4..5> Tcah: Address Holding Time after nGCSn
-;// <0=> 0 clk <1=> 1 clk <2=> 2 clks <3=> 4 clks
-;// <o0.6..7> Toch: Chip Select Hold on nOE
-;// <0=> 0 clk <1=> 1 clk <2=> 2 clks <3=> 4 clks
-;// <o0.8..10> Tacc: Access Cycle
-;// <0=> 1 clk <1=> 2 clks <2=> 3 clks <3=> 4 clks
-;// <4=> 6 clk <5=> 8 clks <6=> 10 clks <7=> 14 clks
-;// <o0.11..12> Tcos: Chip Select Set-up nOE
-;// <0=> 0 clk <1=> 1 clk <2=> 2 clks <3=> 4 clks
-;// <o0.13..14> Tacs: Address Set-up before nGCSn
-;// <0=> 0 clk <1=> 1 clk <2=> 2 clks <3=> 4 clks
-;// </h>
-;//
-;// <h> Bank 1
-;// <o8.4..5> DW: Data Bus Width
-;// <0=> 8-bit <1=> 16-bit <2=> 32-bit <3=> Rsrvd
-;// <o8.6> WS: WAIT Status
-;// <0=> WAIT Disable
-;// <1=> WAIT Enable
-;// <o8.7> ST: SRAM Type
-;// <0=> Not using UB/LB
-;// <1=> Using UB/LB
-;// <o1.0..1> PMC: Page Mode Configuration
-;// <0=> 1 Data <1=> 4 Data <2=> 8 Data <3=> 16 Data
-;// <o1.2..3> Tpac: Page Mode Access Cycle
-;// <0=> 2 clks <1=> 3 clks <2=> 4 clks <3=> 6 clks
-;// <o1.4..5> Tcah: Address Holding Time after nGCSn
-;// <0=> 0 clk <1=> 1 clk <2=> 2 clks <3=> 4 clks
-;// <o1.6..7> Toch: Chip Select Hold on nOE
-;// <0=> 0 clk <1=> 1 clk <2=> 2 clks <3=> 4 clks
-;// <o1.8..10> Tacc: Access Cycle
-;// <0=> 1 clk <1=> 2 clks <2=> 3 clks <3=> 4 clks
-;// <4=> 6 clk <5=> 8 clks <6=> 10 clks <7=> 14 clks
-;// <o1.11..12> Tcos: Chip Select Set-up nOE
-;// <0=> 0 clk <1=> 1 clk <2=> 2 clks <3=> 4 clks
-;// <o1.13..14> Tacs: Address Set-up before nGCSn
-;// <0=> 0 clk <1=> 1 clk <2=> 2 clks <3=> 4 clks
-;// </h>
-;//
-;// <h> Bank 2
-;// <o8.8..9> DW: Data Bus Width
-;// <0=> 8-bit <1=> 16-bit <2=> 32-bit <3=> Rsrvd
-;// <o8.10> WS: WAIT Status
-;// <0=> WAIT Disable
-;// <1=> WAIT Enable
-;// <o8.11> ST: SRAM Type
-;// <0=> Not using UB/LB
-;// <1=> Using UB/LB
-;// <o2.0..1> PMC: Page Mode Configuration
-;// <0=> 1 Data <1=> 4 Data <2=> 8 Data <3=> 16 Data
-;// <o2.2..3> Tpac: Page Mode Access Cycle
-;// <0=> 2 clks <1=> 3 clks <2=> 4 clks <3=> 6 clks
-;// <o2.4..5> Tcah: Address Holding Time after nGCSn
-;// <0=> 0 clk <1=> 1 clk <2=> 2 clks <3=> 4 clks
-;// <o2.6..7> Toch: Chip Select Hold on nOE
-;// <0=> 0 clk <1=> 1 clk <2=> 2 clks <3=> 4 clks
-;// <o2.8..10> Tacc: Access Cycle
-;// <0=> 1 clk <1=> 2 clks <2=> 3 clks <3=> 4 clks
-;// <4=> 6 clk <5=> 8 clks <6=> 10 clks <7=> 14 clks
-;// <o2.11..12> Tcos: Chip Select Set-up nOE
-;// <0=> 0 clk <1=> 1 clk <2=> 2 clks <3=> 4 clks
-;// <o2.13..14> Tacs: Address Set-up before nGCSn
-;// <0=> 0 clk <1=> 1 clk <2=> 2 clks <3=> 4 clks
-;// </h>
-;//
-;// <h> Bank 3
-;// <o8.12..13> DW: Data Bus Width
-;// <0=> 8-bit <1=> 16-bit <2=> 32-bit <3=> Rsrvd
-;// <o8.14> WS: WAIT Status
-;// <0=> WAIT Disable
-;// <1=> WAIT Enable
-;// <o8.15> ST: SRAM Type
-;// <0=> Not using UB/LB
-;// <1=> Using UB/LB
-;// <o3.0..1> PMC: Page Mode Configuration
-;// <0=> 1 Data <1=> 4 Data <2=> 8 Data <3=> 16 Data
-;// <o3.2..3> Tpac: Page Mode Access Cycle
-;// <0=> 2 clks <1=> 3 clks <2=> 4 clks <3=> 6 clks
-;// <o3.4..5> Tcah: Address Holding Time after nGCSn
-;// <0=> 0 clk <1=> 1 clk <2=> 2 clks <3=> 4 clks
-;// <o3.6..7> Toch: Chip Select Hold on nOE
-;// <0=> 0 clk <1=> 1 clk <2=> 2 clks <3=> 4 clks
-;// <o3.8..10> Tacc: Access Cycle
-;// <0=> 1 clk <1=> 2 clks <2=> 3 clks <3=> 4 clks
-;// <4=> 6 clk <5=> 8 clks <6=> 10 clks <7=> 14 clks
-;// <o3.11..12> Tcos: Chip Select Set-up nOE
-;// <0=> 0 clk <1=> 1 clk <2=> 2 clks <3=> 4 clks
-;// <o3.13..14> Tacs: Address Set-up before nGCSn
-;// <0=> 0 clk <1=> 1 clk <2=> 2 clks <3=> 4 clks
-;// </h>
-;//
-;// <h> Bank 4
-;// <o8.16..17> DW: Data Bus Width
-;// <0=> 8-bit <1=> 16-bit <2=> 32-bit <3=> Rsrvd
-;// <o8.18> WS: WAIT Status
-;// <0=> WAIT Disable
-;// <1=> WAIT Enable
-;// <o8.19> ST: SRAM Type
-;// <0=> Not using UB/LB
-;// <1=> Using UB/LB
-;// <o4.0..1> PMC: Page Mode Configuration
-;// <0=> 1 Data <1=> 4 Data <2=> 8 Data <3=> 16 Data
-;// <o4.2..3> Tpac: Page Mode Access Cycle
-;// <0=> 2 clks <1=> 3 clks <2=> 4 clks <3=> 6 clks
-;// <o4.4..5> Tcah: Address Holding Time after nGCSn
-;// <0=> 0 clk <1=> 1 clk <2=> 2 clks <3=> 4 clks
-;// <o4.6..7> Toch: Chip Select Hold on nOE
-;// <0=> 0 clk <1=> 1 clk <2=> 2 clks <3=> 4 clks
-;// <o4.8..10> Tacc: Access Cycle
-;// <0=> 1 clk <1=> 2 clks <2=> 3 clks <3=> 4 clks
-;// <4=> 6 clk <5=> 8 clks <6=> 10 clks <7=> 14 clks
-;// <o4.11..12> Tcos: Chip Select Set-up nOE
-;// <0=> 0 clk <1=> 1 clk <2=> 2 clks <3=> 4 clks
-;// <o4.13..14> Tacs: Address Set-up before nGCSn
-;// <0=> 0 clk <1=> 1 clk <2=> 2 clks <3=> 4 clks
-;// </h>
-;//
-;// <h> Bank 5
-;// <o8.20..21> DW: Data Bus Width
-;// <0=> 8-bit <1=> 16-bit <2=> 32-bit <3=> Rsrvd
-;// <o8.22> WS: WAIT Status
-;// <0=> WAIT Disable
-;// <1=> WAIT Enable
-;// <o8.23> ST: SRAM Type
-;// <0=> Not using UB/LB
-;// <1=> Using UB/LB
-;// <o5.0..1> PMC: Page Mode Configuration
-;// <0=> 1 Data <1=> 4 Data <2=> 8 Data <3=> 16 Data
-;// <o5.2..3> Tpac: Page Mode Access Cycle
-;// <0=> 2 clks <1=> 3 clks <2=> 4 clks <3=> 6 clks
-;// <o5.4..5> Tcah: Address Holding Time after nGCSn
-;// <0=> 0 clk <1=> 1 clk <2=> 2 clks <3=> 4 clks
-;// <o5.6..7> Toch: Chip Select Hold on nOE
-;// <0=> 0 clk <1=> 1 clk <2=> 2 clks <3=> 4 clks
-;// <o5.8..10> Tacc: Access Cycle
-;// <0=> 1 clk <1=> 2 clks <2=> 3 clks <3=> 4 clks
-;// <4=> 6 clk <5=> 8 clks <6=> 10 clks <7=> 14 clks
-;// <o5.11..12> Tcos: Chip Select Set-up nOE
-;// <0=> 0 clk <1=> 1 clk <2=> 2 clks <3=> 4 clks
-;// <o5.13..14> Tacs: Address Set-up before nGCSn
-;// <0=> 0 clk <1=> 1 clk <2=> 2 clks <3=> 4 clks
-;// </h>
-;//
-;// <h> Bank 6
-;// <o10.0..2> BK76MAP: Bank 6/7 Memory Map
-;// <0=> 32M <4=> 2M <5=> 4M <6=> 8M <7=> 16M
-;// <o8.24..25> DW: Data Bus Width
-;// <0=> 8-bit <1=> 16-bit <2=> 32-bit <3=> Rsrvd
-;// <o8.26> WS: WAIT Status
-;// <0=> WAIT Disable
-;// <1=> WAIT Enable
-;// <o8.27> ST: SRAM Type
-;// <0=> Not using UB/LB
-;// <1=> Using UB/LB
-;// <o6.15..16> MT: Memory Type
-;// <0=> ROM or SRAM
-;// <1=> FP DRAMP
-;// <2=> EDO DRAM
-;// <3=> SDRAM
-;// <h> ROM or SRAM
-;// <o6.0..1> PMC: Page Mode Configuration
-;// <0=> 1 Data <1=> 4 Data <2=> 8 Data <3=> 16 Data
-;// <o6.2..3> Tpac: Page Mode Access Cycle
-;// <0=> 2 clks <1=> 3 clks <2=> 4 clks <3=> 6 clks
-;// <o6.4..5> Tcah: Address Holding Time after nGCSn
-;// <0=> 0 clk <1=> 1 clk <2=> 2 clks <3=> 4 clks
-;// <o6.6..7> Toch: Chip Select Hold on nOE
-;// <0=> 0 clk <1=> 1 clk <2=> 2 clks <3=> 4 clks
-;// <o6.8..10> Tacc: Access Cycle
-;// <0=> 1 clk <1=> 2 clks <2=> 3 clks <3=> 4 clks
-;// <4=> 6 clk <5=> 8 clks <6=> 10 clks <7=> 14 clks
-;// <o6.11..12> Tcos: Chip Select Set-up nOE
-;// <0=> 0 clk <1=> 1 clk <2=> 2 clks <3=> 4 clks
-;// <o6.13..14> Tacs: Address Set-up before nGCSn
-;// <0=> 0 clk <1=> 1 clk <2=> 2 clks <3=> 4 clks
-;// </h>
-;// <h> FP DRAM or EDO DRAM
-;// <o6.0..1> CAN: Columnn Address Number
-;// <0=> 8-bit <1=> 9-bit <2=> 10-bit <3=> 11-bit
-;// <o6.2> Tcp: CAS Pre-charge
-;// <0=> 1 clk <1=> 2 clks
-;// <o6.3> Tcas: CAS Pulse Width
-;// <0=> 1 clk <1=> 2 clks
-;// <o6.4..5> Trcd: RAS to CAS Delay
-;// <0=> 1 clk <1=> 2 clks <2=> 3 clks <3=> 4 clks
-;// </h>
-;// <h> SDRAM
-;// <o6.0..1> SCAN: Columnn Address Number
-;// <0=> 8-bit <1=> 9-bit <2=> 10-bit <3=> Rsrvd
-;// <o6.2..3> Trcd: RAS to CAS Delay
-;// <0=> 2 clks <1=> 3 clks <2=> 4 clks <3=> Rsrvd
-;// <o10.4> SCLKEN: SCLK Selection (Bank 6/7)
-;// <0=> Normal
-;// <1=> Reduced Power
-;// <o11.0..2> BL: Burst Length
-;// <0=> 1
-;// <o11.3> BT: Burst Type
-;// <0=> Sequential
-;// <o11.4..6> CL: CAS Latency
-;// <0=> 1 clk <1=> 2 clks <2=> 3 clks
-;// <o11.7..8> TM: Test Mode
-;// <0=> Mode Register Set
-;// <o11.9> WBL: Write Burst Length
-;// <0=> 0
-;// </h>
-;// </h>
-;//
-;// <h> Bank 7
-;// <o10.0..2> BK76MAP: Bank 6/7 Memory Map
-;// <0=> 32M <4=> 2M <5=> 4M <6=> 8M <7=> 16M
-;// <o8.28..29> DW: Data Bus Width
-;// <0=> 8-bit <1=> 16-bit <2=> 32-bit <3=> Rsrvd
-;// <o8.30> WS: WAIT Status
-;// <0=> WAIT Disable
-;// <1=> WAIT Enable
-;// <o8.31> ST: SRAM Type
-;// <0=> Not using UB/LB
-;// <1=> Using UB/LB
-;// <o7.15..16> MT: Memory Type
-;// <0=> ROM or SRAM
-;// <1=> FP DRAMP
-;// <2=> EDO DRAM
-;// <3=> SDRAM
-;// <h> ROM or SRAM
-;// <o7.0..1> PMC: Page Mode Configuration
-;// <0=> 1 Data <1=> 4 Data <2=> 8 Data <3=> 16 Data
-;// <o7.2..3> Tpac: Page Mode Access Cycle
-;// <0=> 2 clks <1=> 3 clks <2=> 4 clks <3=> 6 clks
-;// <o7.4..5> Tcah: Address Holding Time after nGCSn
-;// <0=> 0 clk <1=> 1 clk <2=> 2 clks <3=> 4 clks
-;// <o7.6..7> Toch: Chip Select Hold on nOE
-;// <0=> 0 clk <1=> 1 clk <2=> 2 clks <3=> 4 clks
-;// <o7.8..10> Tacc: Access Cycle
-;// <0=> 1 clk <1=> 2 clks <2=> 3 clks <3=> 4 clks
-;// <4=> 6 clk <5=> 8 clks <6=> 10 clks <7=> 14 clks
-;// <o7.11..12> Tcos: Chip Select Set-up nOE
-;// <0=> 0 clk <1=> 1 clk <2=> 2 clks <3=> 4 clks
-;// <o7.13..14> Tacs: Address Set-up before nGCSn
-;// <0=> 0 clk <1=> 1 clk <2=> 2 clks <3=> 4 clks
-;// </h>
-;// <h> FP DRAM or EDO DRAM
-;// <o7.0..1> CAN: Columnn Address Number
-;// <0=> 8-bit <1=> 9-bit <2=> 10-bit <3=> 11-bit
-;// <o7.2> Tcp: CAS Pre-charge
-;// <0=> 1 clk <1=> 2 clks
-;// <o7.3> Tcas: CAS Pulse Width
-;// <0=> 1 clk <1=> 2 clks
-;// <o7.4..5> Trcd: RAS to CAS Delay
-;// <0=> 1 clk <1=> 2 clks <2=> 3 clks <3=> 4 clks
-;// </h>
-;// <h> SDRAM
-;// <o7.0..1> SCAN: Columnn Address Number
-;// <0=> 8-bit <1=> 9-bit <2=> 10-bit <3=> Rsrvd
-;// <o7.2..3> Trcd: RAS to CAS Delay
-;// <0=> 2 clks <1=> 3 clks <2=> 4 clks <3=> Rsrvd
-;// <o10.4> SCLKEN: SCLK Selection (Bank 6/7)
-;// <0=> Normal
-;// <1=> Reduced Power
-;// <o12.0..2> BL: Burst Length
-;// <0=> 1
-;// <o12.3> BT: Burst Type
-;// <0=> Sequential
-;// <o12.4..6> CL: CAS Latency
-;// <0=> 1 clk <1=> 2 clks <2=> 3 clks
-;// <o12.7..8> TM: Test Mode
-;// <0=> Mode Register Set
-;// <o12.9> WBL: Write Burst Length
-;// <0=> 0
-;// </h>
-;// </h>
-;//
-;// <h> Refresh
-;// <o9.23> REFEN: DRAM/SDRAM Refresh
-;// <0=> Disable <1=> Enable
-;// <o9.22> TREFMD: DRAM/SDRAM Refresh Mode
-;// <0=> CBR/Auto Refresh
-;// <1=> Self Refresh
-;// <o9.20..21> Trp: DRAM/SDRAM RAS Pre-charge Time
-;// <0=> 1.5 clks (DRAM) / 2 clks (SDRAM)
-;// <1=> 2.5 clks (DRAM) / 3 clks (SDRAM)
-;// <2=> 3.5 clks (DRAM) / 4 clks (SDRAM)
-;// <3=> 4.5 clks (DRAM) / Rsrvd (SDRAM)
-;// <o9.18..19> Trc: SDRAM RC Min Time
-;// <0=> 4 clks <1=> 5 clks <2=> 6 clks <3=> 7 clks
-;// <o9.16..17> Tchr: DRAM CAS Hold Time
-;// <0=> 1 clks <1=> 2 clks <2=> 3 clks <3=> 4 clks
-;// <o9.0..10> Refresh Counter <0x0-0x07FF>
-;// <i> Refresh Period = (2^11 - Refresh Count + 1) / MCLK
-;// </h>
-BANKCON0_Val EQU 0x00000700
-BANKCON1_Val EQU 0x00000700
-BANKCON2_Val EQU 0x00000700
-BANKCON3_Val EQU 0x00000700
-BANKCON4_Val EQU 0x00000700
-BANKCON5_Val EQU 0x00000700
-BANKCON6_Val EQU 0x00018008
-BANKCON7_Val EQU 0x00018008
-BWSCON_Val EQU 0x00000000
-REFRESH_Val EQU 0x00AC0000
-BANKSIZE_Val EQU 0x00000000
-MRSRB6_Val EQU 0x00000000
-MRSRB7_Val EQU 0x00000000
-
-;// </e> End of MC
-
-
-; I/O Ports definitions
-PIO_BASE EQU 0x01D20000 ; PIO Base Address
-PCONA_OFS EQU 0x00 ; PCONA Offset
-PCONB_OFS EQU 0x08 ; PCONB Offset
-PCONC_OFS EQU 0x10 ; PCONC Offset
-PCOND_OFS EQU 0x1C ; PCOND Offset
-PCONE_OFS EQU 0x28 ; PCONE Offset
-PCONF_OFS EQU 0x34 ; PCONF Offset
-PCONG_OFS EQU 0x40 ; PCONG Offset
-PUPC_OFS EQU 0x18 ; PUPC Offset
-PUPD_OFS EQU 0x24 ; PUPD Offset
-PUPE_OFS EQU 0x30 ; PUPE Offset
-PUPF_OFS EQU 0x3C ; PUPF Offset
-PUPG_OFS EQU 0x48 ; PUPG Offset
-SPUCR_OFS EQU 0x4C ; SPUCR Offset
-
-;// <e> I/O Configuration
-PIO_SETUP EQU 0
-
-;// <e> Port A
-;// <o1.0> PA0 <0=> Output <1=> ADDR0
-;// <o1.1> PA1 <0=> Output <1=> ADDR16
-;// <o1.2> PA2 <0=> Output <1=> ADDR17
-;// <o1.3> PA3 <0=> Output <1=> ADDR18
-;// <o1.4> PA4 <0=> Output <1=> ADDR19
-;// <o1.5> PA5 <0=> Output <1=> ADDR20
-;// <o1.6> PA6 <0=> Output <1=> ADDR21
-;// <o1.7> PA7 <0=> Output <1=> ADDR22
-;// <o1.8> PA8 <0=> Output <1=> ADDR23
-;// <o1.9> PA9 <0=> Output <1=> ADDR24
-;// </e>
-PIOA_SETUP EQU 1
-PCONA_Val EQU 0x000003FF
-
-;// <e> Port B
-;// <o1.0> PB0 <0=> Output <1=> SCKE
-;// <o1.1> PB1 <0=> Output <1=> CKLK
-;// <o1.2> PB2 <0=> Output <1=> nSCAS/nCAS2
-;// <o1.3> PB3 <0=> Output <1=> nSRAS/nCAS3
-;// <o1.4> PB4 <0=> Output <1=> nWBE2/nBE2/DQM2
-;// <o1.5> PB5 <0=> Output <1=> nWBE3/nBE3/DQM3
-;// <o1.6> PB6 <0=> Output <1=> nGCS1
-;// <o1.7> PB7 <0=> Output <1=> nGCS2
-;// <o1.8> PB8 <0=> Output <1=> nGCS3
-;// <o1.9> PB9 <0=> Output <1=> nGCS4
-;// <o1.10> PB10 <0=> Output <1=> nGCS5
-;// </e>
-PIOB_SETUP EQU 1
-PCONB_Val EQU 0x000007FF
-
-;// <e> Port C
-;// <o1.0..1> PC0 <0=> Input <1=> Output <2=> DATA16 <3=> IISLRCK
-;// <o1.2..3> PC1 <0=> Input <1=> Output <2=> DATA17 <3=> IISDO
-;// <o1.4..5> PC2 <0=> Input <1=> Output <2=> DATA18 <3=> IISDI
-;// <o1.6..7> PC3 <0=> Input <1=> Output <2=> DATA19 <3=> IISCLK
-;// <o1.8..9> PC4 <0=> Input <1=> Output <2=> DATA20 <3=> VD7
-;// <o1.10..11> PC5 <0=> Input <1=> Output <2=> DATA21 <3=> VD6
-;// <o1.12..13> PC6 <0=> Input <1=> Output <2=> DATA22 <3=> VD5
-;// <o1.14..15> PC7 <0=> Input <1=> Output <2=> DATA23 <3=> VD4
-;// <o1.16..17> PC8 <0=> Input <1=> Output <2=> DATA24 <3=> nXDACK1
-;// <o1.18..19> PC9 <0=> Input <1=> Output <2=> DATA25 <3=> nXDREQ1
-;// <o1.20..21> PC10 <0=> Input <1=> Output <2=> DATA26 <3=> nRTS1
-;// <o1.22..23> PC11 <0=> Input <1=> Output <2=> DATA27 <3=> nCTS1
-;// <o1.24..25> PC12 <0=> Input <1=> Output <2=> DATA28 <3=> TxD1
-;// <o1.26..27> PC13 <0=> Input <1=> Output <2=> DATA29 <3=> RxD1
-;// <o1.28..29> PC14 <0=> Input <1=> Output <2=> DATA30 <3=> nRTS0
-;// <o1.30..31> PC15 <0=> Input <1=> Output <2=> DATA31 <3=> nCTS0
-;// <h> Pull-up Resistors
-;// <o2.0> PC0 Pull-up <0=> Enabled <1=> Disabled
-;// <o2.1> PC1 Pull-up <0=> Enabled <1=> Disabled
-;// <o2.2> PC2 Pull-up <0=> Enabled <1=> Disabled
-;// <o2.3> PC3 Pull-up <0=> Enabled <1=> Disabled
-;// <o2.4> PC4 Pull-up <0=> Enabled <1=> Disabled
-;// <o2.5> PC5 Pull-up <0=> Enabled <1=> Disabled
-;// <o2.6> PC6 Pull-up <0=> Enabled <1=> Disabled
-;// <o2.7> PC7 Pull-up <0=> Enabled <1=> Disabled
-;// <o2.8> PC8 Pull-up <0=> Enabled <1=> Disabled
-;// <o2.9> PC9 Pull-up <0=> Enabled <1=> Disabled
-;// <o2.10> PC10 Pull-up <0=> Enabled <1=> Disabled
-;// <o2.11> PC11 Pull-up <0=> Enabled <1=> Disabled
-;// <o2.12> PC12 Pull-up <0=> Enabled <1=> Disabled
-;// <o2.13> PC13 Pull-up <0=> Enabled <1=> Disabled
-;// <o2.14> PC14 Pull-up <0=> Enabled <1=> Disabled
-;// <o2.15> PC15 Pull-up <0=> Enabled <1=> Disabled
-;// </h>
-;// </e>
-PIOC_SETUP EQU 1
-PCONC_Val EQU 0xAAAAAAAA
-PUPC_Val EQU 0x00000000
-
-;// <e> Port D
-;// <o1.0..1> PD0 <0=> Input <1=> Output <2=> VD0 <3=> Reserved
-;// <o1.2..3> PD1 <0=> Input <1=> Output <2=> VD1 <3=> Reserved
-;// <o1.4..5> PD2 <0=> Input <1=> Output <2=> VD2 <3=> Reserved
-;// <o1.6..7> PD3 <0=> Input <1=> Output <2=> VD3 <3=> Reserved
-;// <o1.8..9> PD4 <0=> Input <1=> Output <2=> VCLK <3=> Reserved
-;// <o1.10..11> PD5 <0=> Input <1=> Output <2=> VLINE <3=> Reserved
-;// <o1.12..13> PD6 <0=> Input <1=> Output <2=> VM <3=> Reserved
-;// <o1.14..15> PD7 <0=> Input <1=> Output <2=> VFRAME <3=> Reserved
-;// <h> Pull-up Resistors
-;// <o2.0> PD0 Pull-up <0=> Enabled <1=> Disabled
-;// <o2.1> PD1 Pull-up <0=> Enabled <1=> Disabled
-;// <o2.2> PD2 Pull-up <0=> Enabled <1=> Disabled
-;// <o2.3> PD3 Pull-up <0=> Enabled <1=> Disabled
-;// <o2.4> PD4 Pull-up <0=> Enabled <1=> Disabled
-;// <o2.5> PD5 Pull-up <0=> Enabled <1=> Disabled
-;// <o2.6> PD6 Pull-up <0=> Enabled <1=> Disabled
-;// <o2.7> PD7 Pull-up <0=> Enabled <1=> Disabled
-;// </h>
-;// </e>
-PIOD_SETUP EQU 1
-PCOND_Val EQU 0x00000000
-PUPD_Val EQU 0x00000000
-
-;// <e> Port E
-;// <o1.0..1> PE0 <0=> Input <1=> Output <2=> Fpllo <3=> Fout
-;// <o1.2..3> PE1 <0=> Input <1=> Output <2=> TxD0 <3=> Reserved
-;// <o1.4..5> PE2 <0=> Input <1=> Output <2=> RxD0 <3=> Reserved
-;// <o1.6..7> PE3 <0=> Input <1=> Output <2=> TOUT0 <3=> Reserved
-;// <o1.8..9> PE4 <0=> Input <1=> Output <2=> TOUT1 <3=> TCLK
-;// <o1.10..11> PE5 <0=> Input <1=> Output <2=> TOUT2 <3=> TCLK
-;// <o1.12..13> PE6 <0=> Input <1=> Output <2=> TOUT3 <3=> VD6
-;// <o1.14..15> PE7 <0=> Input <1=> Output <2=> TOUT4 <3=> VD7
-;// <o1.16..17> PE8 <0=> Input <1=> Output <2=> CODECLK <3=> Reserved
-;// <h> Pull-up Resistors
-;// <o2.0> PE0 Pull-up <0=> Enabled <1=> Disabled
-;// <o2.1> PE1 Pull-up <0=> Enabled <1=> Disabled
-;// <o2.2> PE2 Pull-up <0=> Enabled <1=> Disabled
-;// <o2.3> PE3 Pull-up <0=> Enabled <1=> Disabled
-;// <o2.4> PE4 Pull-up <0=> Enabled <1=> Disabled
-;// <o2.5> PE5 Pull-up <0=> Enabled <1=> Disabled
-;// <o2.6> PE6 Pull-up <0=> Enabled <1=> Disabled
-;// <o2.7> PE7 Pull-up <0=> Enabled <1=> Disabled
-;// <o2.8> PE8 Pull-up <0=> Enabled <1=> Disabled
-;// </h>
-;// </e>
-PIOE_SETUP EQU 1
-PCONE_Val EQU 0x00000000
-PUPE_Val EQU 0x00000000
-
-;// <e> Port F
-;// <o1.0..1> PF0 <0=> Input <1=> Output <2=> IICSCL <3=> Reserved
-;// <o1.2..3> PF1 <0=> Input <1=> Output <2=> IICSDA <3=> Reserved
-;// <o1.4..5> PF2 <0=> Input <1=> Output <2=> nWAIT <3=> Reserved
-;// <o1.6..7> PF3 <0=> Input <1=> Output <2=> nXBACK <3=> nXDACK0
-;// <o1.8..9> PF4 <0=> Input <1=> Output <2=> nXBREQ <3=> nXDREQ0
-;// <o1.10..12> PF5 <0=> Input <1=> Output <2=> nRTS1 <3=> SIOTxD
-;// <4=> IISLRCK <5=> Reserved <6=> Reserved <7=> Reserved
-;// <o1.13..15> PF6 <0=> Input <1=> Output <2=> TxD1 <3=> SIORDY
-;// <4=> IISDO <5=> Reserved <6=> Reserved <7=> Reserved
-;// <o1.16..18> PF7 <0=> Input <1=> Output <2=> RxD1 <3=> SIORxD
-;// <4=> IISDI <5=> Reserved <6=> Reserved <7=> Reserved
-;// <o1.19..21> PF8 <0=> Input <1=> Output <2=> nCTS1 <3=> SIOCLK
-;// <4=> IISCLK <5=> Reserved <6=> Reserved <7=> Reserved
-;// <h> Pull-up Resistors
-;// <o2.0> PF0 Pull-up <0=> Enabled <1=> Disabled
-;// <o2.1> PF1 Pull-up <0=> Enabled <1=> Disabled
-;// <o2.2> PF2 Pull-up <0=> Enabled <1=> Disabled
-;// <o2.3> PF3 Pull-up <0=> Enabled <1=> Disabled
-;// <o2.4> PF4 Pull-up <0=> Enabled <1=> Disabled
-;// <o2.5> PF5 Pull-up <0=> Enabled <1=> Disabled
-;// <o2.6> PF6 Pull-up <0=> Enabled <1=> Disabled
-;// <o2.7> PF7 Pull-up <0=> Enabled <1=> Disabled
-;// <o2.8> PF8 Pull-up <0=> Enabled <1=> Disabled
-;// </h>
-;// </e>
-PIOF_SETUP EQU 1
-PCONF_Val EQU 0x00000000
-PUPF_Val EQU 0x00000000
-
-;// <e> Port G
-;// <o1.0..1> PG0 <0=> Input <1=> Output <2=> VD4 <3=> EINT0
-;// <o1.2..3> PG1 <0=> Input <1=> Output <2=> VD5 <3=> EINT1
-;// <o1.4..5> PG2 <0=> Input <1=> Output <2=> nCTS0 <3=> EINT2
-;// <o1.6..7> PG3 <0=> Input <1=> Output <2=> nRTS0 <3=> EINT3
-;// <o1.8..9> PG4 <0=> Input <1=> Output <2=> IISCLK <3=> EINT4
-;// <o1.10..11> PG5 <0=> Input <1=> Output <2=> IISDI <3=> EINT5
-;// <o1.12..13> PG6 <0=> Input <1=> Output <2=> IISDO <3=> EINT6
-;// <o1.14..15> PG7 <0=> Input <1=> Output <2=> IISLRCK <3=> EINT7
-;// <h> Pull-up Resistors
-;// <o2.0> PG0 Pull-up <0=> Enabled <1=> Disabled
-;// <o2.1> PG1 Pull-up <0=> Enabled <1=> Disabled
-;// <o2.2> PG2 Pull-up <0=> Enabled <1=> Disabled
-;// <o2.3> PG3 Pull-up <0=> Enabled <1=> Disabled
-;// <o2.4> PG4 Pull-up <0=> Enabled <1=> Disabled
-;// <o2.5> PG5 Pull-up <0=> Enabled <1=> Disabled
-;// <o2.6> PG6 Pull-up <0=> Enabled <1=> Disabled
-;// <o2.7> PG7 Pull-up <0=> Enabled <1=> Disabled
-;// </h>
-;// </e>
-PIOG_SETUP EQU 1
-PCONG_Val EQU 0x00000000
-PUPG_Val EQU 0x00000000
-
-;// <e> Special Pull-up
-;// <o1.0> SPUCR0: DATA[7:0] Pull-up Resistor
-;// <0=> Enabled <1=> Disabled
-;// <o1.1> SPUCR1: DATA[15:8] Pull-up Resistor
-;// <0=> Enabled <1=> Disabled
-;// <o1.2> HZ@STOP
-;// <0=> Prevoius state of PAD
-;// <1=> HZ @ Stop
-;// </e>
-PSPU_SETUP EQU 1
-SPUCR_Val EQU 0x00000004
-
-;// </e>
-
-
- PRESERVE8
-
-
-; Area Definition and Entry Point
-; Startup Code must be linked first at Address at which it expects to run.
-
- AREA RESET, CODE, READONLY
- ARM
-
-
-; Exception Vectors
-; Mapped to Address 0.
-; Absolute addressing mode must be used.
-; Dummy Handlers are implemented as infinite loops which can be modified.
-
-Vectors LDR PC, Reset_Addr
- LDR PC, Undef_Addr
- LDR PC, SWI_Addr
- LDR PC, PAbt_Addr
- LDR PC, DAbt_Addr
- NOP ; Reserved Vector
- LDR PC, IRQ_Addr
- LDR PC, FIQ_Addr
-
-Reset_Addr DCD Reset_Handler
-Undef_Addr DCD Undef_Handler
-SWI_Addr DCD SWI_Handler
-PAbt_Addr DCD PAbt_Handler
-DAbt_Addr DCD DAbt_Handler
- DCD 0 ; Reserved Address
-IRQ_Addr DCD IRQ_Handler
-FIQ_Addr DCD FIQ_Handler
-
-Undef_Handler B Undef_Handler
-SWI_Handler B SWI_Handler
-PAbt_Handler B PAbt_Handler
-DAbt_Handler B DAbt_Handler
-FIQ_Handler B FIQ_Handler
-
-
-; CPU Wrapper and Bus Priorities Configuration
- IF SYS_SETUP <> 0
-SYS_CFG
- DCD CPUW_BASE
- DCD BUSP_BASE
- DCD SYSCFG_Val
- DCD NCACHBE0_Val
- DCD NCACHBE1_Val
- DCD SBUSCON_Val
- ENDIF
-
-
-; Memory Controller Configuration
- IF MC_SETUP <> 0
-MC_CFG
- DCD BWSCON_Val
- DCD BANKCON0_Val
- DCD BANKCON1_Val
- DCD BANKCON2_Val
- DCD BANKCON3_Val
- DCD BANKCON4_Val
- DCD BANKCON5_Val
- DCD BANKCON6_Val
- DCD BANKCON7_Val
- DCD REFRESH_Val
- DCD BANKSIZE_Val
- DCD MRSRB6_Val
- DCD MRSRB7_Val
- ENDIF
-
-
-; Clock Management Configuration
- IF CLK_SETUP <> 0
-CLK_CFG
- DCD CLK_BASE
- DCD PLLCON_Val
- DCD CLKCON_Val
- DCD CLKSLOW_Val
- DCD LOCKTIME_Val
- ENDIF
-
-
-; I/O Configuration
- IF PIO_SETUP <> 0
-PIO_CFG
- DCD PCONA_Val
- DCD PCONB_Val
- DCD PCONC_Val
- DCD PCOND_Val
- DCD PCONE_Val
- DCD PCONF_Val
- DCD PCONG_Val
- DCD PUPC_Val
- DCD PUPD_Val
- DCD PUPE_Val
- DCD PUPF_Val
- DCD PUPG_Val
- DCD SPUCR_Val
- ENDIF
-
-
-; Reset Handler
-
- EXPORT Reset_Handler
-Reset_Handler
-
-
- IF SYS_SETUP <> 0
- ADR R8, SYS_CFG
- LDMIA R8, {R0-R5}
- STMIA R0, {R2-R4}
- STR R5, [R1]
- ENDIF
-
-
- IF MC_SETUP <> 0
- ADR R14, MC_CFG
- LDMIA R14, {R0-R12}
- LDR R14, =MC_BASE
- STMIA R14, {R0-R12}
- ENDIF
-
-
- IF CLK_SETUP <> 0
- ADR R8, CLK_CFG
- LDMIA R8, {R0-R4}
- STR R4, [R0, #LOCKTIME_OFS]
- STR R1, [R0, #PLLCON_OFS]
- STR R3, [R0, #CLKSLOW_OFS]
- STR R2, [R0, #CLKCON_OFS]
- ENDIF
-
-
- IF WT_SETUP <> 0
- LDR R0, =WT_BASE
- LDR R1, =WTCON_Val
- LDR R2, =WTDAT_Val
- STR R2, [R0, #WTCNT_OFS]
- STR R2, [R0, #WTDAT_OFS]
- STR R1, [R0, #WTCON_OFS]
- ENDIF
-
-
- IF PIO_SETUP <> 0
- ADR R14, PIO_CFG
- LDMIA R14, {R0-R12}
- LDR R14, =PIO_BASE
-
- IF PIOA_SETUP <> 0
- STR R0, [R14, #PCONA_OFS]
- ENDIF
-
- IF PIOB_SETUP <> 0
- STR R1, [R14, #PCONB_OFS]
- ENDIF
-
- IF PIOC_SETUP <> 0
- STR R2, [R14, #PCONC_OFS]
- STR R7, [R14, #PUPC_OFS]
- ENDIF
-
- IF PIOD_SETUP <> 0
- STR R3, [R14, #PCOND_OFS]
- STR R8, [R14, #PUPD_OFS]
- ENDIF
-
- IF PIOE_SETUP <> 0
- STR R4, [R14, #PCONE_OFS]
- STR R9, [R14, #PUPE_OFS]
- ENDIF
-
- IF PIOF_SETUP <> 0
- STR R5, [R14, #PCONF_OFS]
- STR R10,[R14, #PUPF_OFS]
- ENDIF
-
- IF PIOG_SETUP <> 0
- STR R6, [R14, #PCONG_OFS]
- STR R11,[R14, #PUPG_OFS]
- ENDIF
-
- IF PSPU_SETUP <> 0
- STR R12,[R14, #SPUCR_OFS]
- ENDIF
-
- ENDIF
-
-
-; Setup Stack for each mode
-
- LDR R0, =Stack_Top
-
-; Enter Undefined Instruction Mode and set its Stack Pointer
- MSR CPSR_c, #Mode_UND:OR:I_Bit:OR:F_Bit
- MOV SP, R0
- SUB R0, R0, #UND_Stack_Size
-
-; Enter Abort Mode and set its Stack Pointer
- MSR CPSR_c, #Mode_ABT:OR:I_Bit:OR:F_Bit
- MOV SP, R0
- SUB R0, R0, #ABT_Stack_Size
-
-; Enter FIQ Mode and set its Stack Pointer
- MSR CPSR_c, #Mode_FIQ:OR:I_Bit:OR:F_Bit
- MOV SP, R0
- SUB R0, R0, #FIQ_Stack_Size
-
-; Enter IRQ Mode and set its Stack Pointer
- MSR CPSR_c, #Mode_IRQ:OR:I_Bit:OR:F_Bit
- MOV SP, R0
- SUB R0, R0, #IRQ_Stack_Size
-
-; Enter Supervisor Mode and set its Stack Pointer
- MSR CPSR_c, #Mode_SVC:OR:I_Bit:OR:F_Bit
- MOV SP, R0
- SUB R0, R0, #SVC_Stack_Size
-
-; Enter User Mode and set its Stack Pointer
- ; MSR CPSR_c, #Mode_USR
- IF :DEF:__MICROLIB
-
- EXPORT __initial_sp
-
- ELSE
-
- ; MOV SP, R0
- ; SUB SL, SP, #USR_Stack_Size
-
- ENDIF
-
-
-; Enter the C code
-
- IMPORT __main
- LDR R0, =__main
- BX R0
-
- IMPORT rt_interrupt_enter
- IMPORT rt_interrupt_leave
- IMPORT rt_thread_switch_interrupt_flag
- IMPORT rt_interrupt_from_thread
- IMPORT rt_interrupt_to_thread
- IMPORT rt_hw_trap_irq
-
-IRQ_Handler PROC
- EXPORT IRQ_Handler
- STMFD sp!, {r0-r12,lr}
- BL rt_interrupt_enter
- BL rt_hw_trap_irq
- BL rt_interrupt_leave
-
- ; if rt_thread_switch_interrupt_flag set, jump to
- ; rt_hw_context_switch_interrupt_do and don't return
- LDR r0, =rt_thread_switch_interrupt_flag
- LDR r1, [r0]
- CMP r1, #1
- BEQ rt_hw_context_switch_interrupt_do
-
- LDMFD sp!, {r0-r12,lr}
- SUBS pc, lr, #4
- ENDP
-
-; /*
-; * void rt_hw_context_switch_interrupt_do(rt_base_t flag)
-; */
-rt_hw_context_switch_interrupt_do PROC
- EXPORT rt_hw_context_switch_interrupt_do
- MOV r1, #0 ; clear flag
- STR r1, [r0]
-
- LDMFD sp!, {r0-r12,lr}; reload saved registers
- STMFD sp!, {r0-r3} ; save r0-r3
- MOV r1, sp
- ADD sp, sp, #16 ; restore sp
- SUB r2, lr, #4 ; save old task's pc to r2
-
- MRS r3, spsr ; get cpsr of interrupt thread
-
- ; switch to SVC mode and no interrupt
- MSR cpsr_c, #I_Bit|F_Bit|Mode_SVC
-
- STMFD sp!, {r2} ; push old task's pc
- STMFD sp!, {r4-r12,lr}; push old task's lr,r12-r4
- MOV r4, r1 ; Special optimised code below
- MOV r5, r3
- LDMFD r4!, {r0-r3}
- STMFD sp!, {r0-r3} ; push old task's r3-r0
- STMFD sp!, {r5} ; push old task's cpsr
- MRS r4, spsr
- STMFD sp!, {r4} ; push old task's spsr
-
- LDR r4, =rt_interrupt_from_thread
- LDR r5, [r4]
- STR sp, [r5] ; store sp in preempted tasks's TCB
-
- LDR r6, =rt_interrupt_to_thread
- LDR r6, [r6]
- LDR sp, [r6] ; get new task's stack pointer
-
- LDMFD sp!, {r4} ; pop new task's spsr
- MSR spsr_cxsf, r4
- LDMFD sp!, {r4} ; pop new task's psr
- MSR cpsr_cxsf, r4
-
- LDMFD sp!, {r0-r12,lr,pc} ; pop new task's r0-r12,lr & pc
- ENDP
-
- IF :DEF:__MICROLIB
-
- EXPORT __heap_base
- EXPORT __heap_limit
-
- ELSE
-; User Initial Stack & Heap
- AREA |.text|, CODE, READONLY
-
- IMPORT __use_two_region_memory
- EXPORT __user_initial_stackheap
-__user_initial_stackheap
-
- LDR R0, = Heap_Mem
- LDR R1, =(Stack_Mem + USR_Stack_Size)
- LDR R2, = (Heap_Mem + Heap_Size)
- LDR R3, = Stack_Mem
- BX LR
- ENDIF
-
-
- END
+;/*****************************************************************************/ +;/* S3C44B0X.S: Startup file for Samsung S3C44B0X */ +;/*****************************************************************************/ +;/* <<< Use Configuration Wizard in Context Menu >>> */ +;/*****************************************************************************/ +;/* This file is part of the uVision/ARM development tools. */ +;/* Copyright (c) 2005-2006 Keil Software. All rights reserved. */ +;/* This software may only be used under the terms of a valid, current, */ +;/* end user licence from KEIL for a compatible version of KEIL software */ +;/* development tools. Nothing else gives you the right to use this software. */ +;/*****************************************************************************/ + + +; *** Startup Code (executed after Reset) *** + + +; Standard definitions of Mode bits and Interrupt (I & F) flags in PSRs + +Mode_USR EQU 0x10 +Mode_FIQ EQU 0x11 +Mode_IRQ EQU 0x12 +Mode_SVC EQU 0x13 +Mode_ABT EQU 0x17 +Mode_UND EQU 0x1B +Mode_SYS EQU 0x1F + +I_Bit EQU 0x80 ; when I bit is set, IRQ is disabled +F_Bit EQU 0x40 ; when F bit is set, FIQ is disabled + + +;// <h> Stack Configuration (Stack Sizes in Bytes) +;// <o0> Undefined Mode <0x0-0xFFFFFFFF:8> +;// <o1> Supervisor Mode <0x0-0xFFFFFFFF:8> +;// <o2> Abort Mode <0x0-0xFFFFFFFF:8> +;// <o3> Fast Interrupt Mode <0x0-0xFFFFFFFF:8> +;// <o4> Interrupt Mode <0x0-0xFFFFFFFF:8> +;// <o5> User/System Mode <0x0-0xFFFFFFFF:8> +;// </h> + +UND_Stack_Size EQU 0x00000000 +SVC_Stack_Size EQU 0x00000100 +ABT_Stack_Size EQU 0x00000000 +FIQ_Stack_Size EQU 0x00000000 +IRQ_Stack_Size EQU 0x00000100 +USR_Stack_Size EQU 0x00000100 + +ISR_Stack_Size EQU (UND_Stack_Size + SVC_Stack_Size + ABT_Stack_Size + \ + FIQ_Stack_Size + IRQ_Stack_Size) + + AREA STACK, NOINIT, READWRITE, ALIGN=3 + +Stack_Mem SPACE USR_Stack_Size +__initial_sp SPACE ISR_Stack_Size +Stack_Top + + +;// <h> Heap Configuration +;// <o> Heap Size (in Bytes) <0x0-0xFFFFFFFF> +;// </h> + +Heap_Size EQU 0x00000000 + + AREA HEAP, NOINIT, READWRITE, ALIGN=3 +__heap_base +Heap_Mem SPACE Heap_Size +__heap_limit + + +; CPU Wrapper and Bus Priorities definitions +CPUW_BASE EQU 0x01C00000 ; CPU Wrapper Base Address +SYSCFG_OFS EQU 0x00 ; SYSCFG Offset +NCACHBE0_OFS EQU 0x04 ; NCACHBE0 Offset +NCACHBE1_OFS EQU 0x08 ; NCACHBE0 Offset +BUSP_BASE EQU 0x01C40000 ; Bus Priority Base Address +SBUSCON_OFS EQU 0x00 ; SBUSCON Offset + +;// <e> CPU Wrapper and Bus Priorities +;// <h> CPU Wrapper +;// <o1.0> SE: Stall Enable +;// <o1.1..2> CM: Cache Mode +;// <0=> Disable Cache (8kB SRAM) +;// <1=> Half Cache Enable (4kB Cache, 4kB SRAM) +;// <2=> Reserved +;// <3=> Full Cache Enable (8kB Cache) +;// <o1.3> WE: Write Buffer Enable +;// <o1.4> RSE: Read Stall Enable +;// <o1.5> DA: Data Abort <0=> Enable <1=> Disable +;// <h> Non-cacheable Area 0 +;// <o2.0..15> Start Address <0x0-0x0FFFF000:0x1000><#/0x1000> +;// <i> SA = (Start Address) / 4k +;// <o2.16..31> End Address + 1 <0x0-0x10000000:0x1000><#/0x1000> +;// <i> SE = (End Address + 1) / 4k +;// </h> +;// <h> Non-cacheable Area 1 +;// <o3.0..15> Start Address <0x0-0x0FFFF000:0x1000><#/0x1000> +;// <i> SA = (Start Address) / 4k +;// <o3.16..31> End Address + 1 <0x0-0x10000000:0x1000><#/0x1000> +;// <i> SE = (End Address + 1) / 4k +;// </h> +;// </h> +;// <h> Bus Priorities +;// <o4.31> FIX: Fixed Priorities +;// <o4.6..7> LCD_DMA <0=> 1st <1=> 2nd <2=> 3rd <3=> 4th +;// <o4.4..5> ZDMA <0=> 1st <1=> 2nd <2=> 3rd <3=> 4th +;// <o4.2..3> BDMA <0=> 1st <1=> 2nd <2=> 3rd <3=> 4th +;// <o4.0..1> nBREQ <0=> 1st <1=> 2nd <2=> 3rd <3=> 4th +;// </h> +;// </e> +SYS_SETUP EQU 0 +SYSCFG_Val EQU 0x00000001 +NCACHBE0_Val EQU 0x00000000 +NCACHBE1_Val EQU 0x00000000 +SBUSCON_Val EQU 0x80001B1B + + +;// <e> Vectored Interrupt Mode (for IRQ) +;// <o1.25> EINT0 <i> External Interrupt 0 +;// <o1.24> EINT1 <i> External Interrupt 1 +;// <o1.23> EINT2 <i> External Interrupt 2 +;// <o1.22> EINT3 <i> External Interrupt 3 +;// <o1.21> EINT4567 <i> External Interrupt 4/5/6/7 +;// <o1.20> TICK <i> RTC Time Tick Interrupt +;// <o1.19> ZDMA0 <i> General DMA0 Interrupt +;// <o1.18> ZDMA1 <i> General DMA1 Interrupt +;// <o1.17> BDMA0 <i> Bridge DMA0 Interrupt +;// <o1.16> BDMA1 <i> Bridge DMA1 Interrupt +;// <o1.15> WDT <i> Watchdog Timer Interrupt +;// <o1.14> UERR01 <i> UART0/1 Error Interrupt +;// <o1.13> TIMER0 <i> Timer0 Interrupt +;// <o1.12> TIMER1 <i> Timer1 Interrupt +;// <o1.11> TIMER2 <i> Timer2 Interrupt +;// <o1.10> TIMER3 <i> Timer3 Interrupt +;// <o1.9> TIMER4 <i> Timer4 Interrupt +;// <o1.8> TIMER5 <i> Timer5 Interrupt +;// <o1.7> URXD0 <i> UART0 Rx Interrupt +;// <o1.6> URXD1 <i> UART1 Rx Interrupt +;// <o1.5> IIC <i> IIC Interrupt +;// <o1.4> SIO <i> SIO Interrupt +;// <o1.3> UTXD0 <i> UART0 Tx Interrupt +;// <o1.2> UTXD1 <i> UART1 Tx Interrupt +;// <o1.1> RTC <i> RTC Alarm Interrupt +;// <o1.0> ADC <i> ADC EOC Interrupt +;// </e> +VIM_SETUP EQU 0 +VIM_CFG EQU 0x00000000 + + +; Clock Management definitions +CLK_BASE EQU 0x01D80000 ; Clock Base Address +PLLCON_OFS EQU 0x00 ; PLLCON Offset +CLKCON_OFS EQU 0x04 ; CLKCON Offset +CLKSLOW_OFS EQU 0x08 ; CLKSLOW Offset +LOCKTIME_OFS EQU 0x0C ; LOCKTIME Offset + +;// <e> Clock Management +;// <h> PLL Settings +;// <i> Fpllo = (m * Fin) / (p * 2^s), 20MHz < Fpllo < 66MHz +;// <o1.12..19> MDIV: Main divider <0x0-0xFF> +;// <i> m = MDIV + 8 +;// <o1.4..9> PDIV: Pre-divider <0x0-0x3F> +;// <i> p = PDIV + 2, 1MHz <= Fin/p < 2MHz +;// <o1.0..1> SDIV: Post Divider <0x0-0x03> +;// <i> s = SDIV, Fpllo * 2^s < 170MHz +;// <o4.0..11> LTIME CNT: PLL Lock Time Count <0x0-0x0FFF> +;// </h> +;// <h> Master Clock +;// <i> PLL Clock: Fout = Fpllo +;// <i> Slow Clock: Fout = Fin / (2 * SLOW_VAL), SLOW_VAL > 0 +;// <i> Slow Clock: Fout = Fin, SLOW_VAL = 0 +;// <o3.5> PLL_OFF: PLL Off +;// <i> PLL is turned Off only when SLOW_BIT = 1 +;// <o3.4> SLOW_BIT: Slow Clock +;// <o3.0..3> SLOW_VAL: Slow Clock divider <0x0-0x0F> +;// </h> +;// <h> Clock Generation +;// <o2.14> IIS <0=> Disable <1=> Enable +;// <o2.13> IIC <0=> Disable <1=> Enable +;// <o2.12> ADC <0=> Disable <1=> Enable +;// <o2.11> RTC <0=> Disable <1=> Enable +;// <o2.10> GPIO <0=> Disable <1=> Enable +;// <o2.9> UART1 <0=> Disable <1=> Enable +;// <o2.8> UART0 <0=> Disable <1=> Enable +;// <o2.7> BDMA0,1 <0=> Disable <1=> Enable +;// <o2.6> LCDC <0=> Disable <1=> Enable +;// <o2.5> SIO <0=> Disable <1=> Enable +;// <o2.4> ZDMA0,1 <0=> Disable <1=> Enable +;// <o2.3> PWMTIMER <0=> Disable <1=> Enable +;// </h> +;// </e> +CLK_SETUP EQU 1 +PLLCON_Val EQU 0x00038080 +CLKCON_Val EQU 0x00007FF8 +CLKSLOW_Val EQU 0x00000009 +LOCKTIME_Val EQU 0x00000FFF + + +; Watchdog Timer definitions +WT_BASE EQU 0x01D30000 ; WT Base Address +WTCON_OFS EQU 0x00 ; WTCON Offset +WTDAT_OFS EQU 0x04 ; WTDAT Offset +WTCNT_OFS EQU 0x08 ; WTCNT Offset + +;// <e> Watchdog Timer +;// <o1.5> Watchdog Timer Enable/Disable +;// <o1.0> Reset Enable/Disable +;// <o1.2> Interrupt Enable/Disable +;// <o1.3..4> Clock Select +;// <0=> 1/16 <1=> 1/32 <2=> 1/64 <3=> 1/128 +;// <i> Clock Division Factor +;// <o1.8..15> Prescaler Value <0x0-0xFF> +;// <o2.0..15> Time-out Value <0x0-0xFFFF> +;// </e> +WT_SETUP EQU 1 +WTCON_Val EQU 0x00008000 +WTDAT_Val EQU 0x00008000 + + +; Memory Controller definitions +MC_BASE EQU 0x01C80000 ; Memory Controller Base Address + +;// <e> Memory Controller +MC_SETUP EQU 1 + +;// <h> Bank 0 +;// <o0.0..1> PMC: Page Mode Configuration +;// <0=> 1 Data <1=> 4 Data <2=> 8 Data <3=> 16 Data +;// <o0.2..3> Tpac: Page Mode Access Cycle +;// <0=> 2 clks <1=> 3 clks <2=> 4 clks <3=> 6 clks +;// <o0.4..5> Tcah: Address Holding Time after nGCSn +;// <0=> 0 clk <1=> 1 clk <2=> 2 clks <3=> 4 clks +;// <o0.6..7> Toch: Chip Select Hold on nOE +;// <0=> 0 clk <1=> 1 clk <2=> 2 clks <3=> 4 clks +;// <o0.8..10> Tacc: Access Cycle +;// <0=> 1 clk <1=> 2 clks <2=> 3 clks <3=> 4 clks +;// <4=> 6 clk <5=> 8 clks <6=> 10 clks <7=> 14 clks +;// <o0.11..12> Tcos: Chip Select Set-up nOE +;// <0=> 0 clk <1=> 1 clk <2=> 2 clks <3=> 4 clks +;// <o0.13..14> Tacs: Address Set-up before nGCSn +;// <0=> 0 clk <1=> 1 clk <2=> 2 clks <3=> 4 clks +;// </h> +;// +;// <h> Bank 1 +;// <o8.4..5> DW: Data Bus Width +;// <0=> 8-bit <1=> 16-bit <2=> 32-bit <3=> Rsrvd +;// <o8.6> WS: WAIT Status +;// <0=> WAIT Disable +;// <1=> WAIT Enable +;// <o8.7> ST: SRAM Type +;// <0=> Not using UB/LB +;// <1=> Using UB/LB +;// <o1.0..1> PMC: Page Mode Configuration +;// <0=> 1 Data <1=> 4 Data <2=> 8 Data <3=> 16 Data +;// <o1.2..3> Tpac: Page Mode Access Cycle +;// <0=> 2 clks <1=> 3 clks <2=> 4 clks <3=> 6 clks +;// <o1.4..5> Tcah: Address Holding Time after nGCSn +;// <0=> 0 clk <1=> 1 clk <2=> 2 clks <3=> 4 clks +;// <o1.6..7> Toch: Chip Select Hold on nOE +;// <0=> 0 clk <1=> 1 clk <2=> 2 clks <3=> 4 clks +;// <o1.8..10> Tacc: Access Cycle +;// <0=> 1 clk <1=> 2 clks <2=> 3 clks <3=> 4 clks +;// <4=> 6 clk <5=> 8 clks <6=> 10 clks <7=> 14 clks +;// <o1.11..12> Tcos: Chip Select Set-up nOE +;// <0=> 0 clk <1=> 1 clk <2=> 2 clks <3=> 4 clks +;// <o1.13..14> Tacs: Address Set-up before nGCSn +;// <0=> 0 clk <1=> 1 clk <2=> 2 clks <3=> 4 clks +;// </h> +;// +;// <h> Bank 2 +;// <o8.8..9> DW: Data Bus Width +;// <0=> 8-bit <1=> 16-bit <2=> 32-bit <3=> Rsrvd +;// <o8.10> WS: WAIT Status +;// <0=> WAIT Disable +;// <1=> WAIT Enable +;// <o8.11> ST: SRAM Type +;// <0=> Not using UB/LB +;// <1=> Using UB/LB +;// <o2.0..1> PMC: Page Mode Configuration +;// <0=> 1 Data <1=> 4 Data <2=> 8 Data <3=> 16 Data +;// <o2.2..3> Tpac: Page Mode Access Cycle +;// <0=> 2 clks <1=> 3 clks <2=> 4 clks <3=> 6 clks +;// <o2.4..5> Tcah: Address Holding Time after nGCSn +;// <0=> 0 clk <1=> 1 clk <2=> 2 clks <3=> 4 clks +;// <o2.6..7> Toch: Chip Select Hold on nOE +;// <0=> 0 clk <1=> 1 clk <2=> 2 clks <3=> 4 clks +;// <o2.8..10> Tacc: Access Cycle +;// <0=> 1 clk <1=> 2 clks <2=> 3 clks <3=> 4 clks +;// <4=> 6 clk <5=> 8 clks <6=> 10 clks <7=> 14 clks +;// <o2.11..12> Tcos: Chip Select Set-up nOE +;// <0=> 0 clk <1=> 1 clk <2=> 2 clks <3=> 4 clks +;// <o2.13..14> Tacs: Address Set-up before nGCSn +;// <0=> 0 clk <1=> 1 clk <2=> 2 clks <3=> 4 clks +;// </h> +;// +;// <h> Bank 3 +;// <o8.12..13> DW: Data Bus Width +;// <0=> 8-bit <1=> 16-bit <2=> 32-bit <3=> Rsrvd +;// <o8.14> WS: WAIT Status +;// <0=> WAIT Disable +;// <1=> WAIT Enable +;// <o8.15> ST: SRAM Type +;// <0=> Not using UB/LB +;// <1=> Using UB/LB +;// <o3.0..1> PMC: Page Mode Configuration +;// <0=> 1 Data <1=> 4 Data <2=> 8 Data <3=> 16 Data +;// <o3.2..3> Tpac: Page Mode Access Cycle +;// <0=> 2 clks <1=> 3 clks <2=> 4 clks <3=> 6 clks +;// <o3.4..5> Tcah: Address Holding Time after nGCSn +;// <0=> 0 clk <1=> 1 clk <2=> 2 clks <3=> 4 clks +;// <o3.6..7> Toch: Chip Select Hold on nOE +;// <0=> 0 clk <1=> 1 clk <2=> 2 clks <3=> 4 clks +;// <o3.8..10> Tacc: Access Cycle +;// <0=> 1 clk <1=> 2 clks <2=> 3 clks <3=> 4 clks +;// <4=> 6 clk <5=> 8 clks <6=> 10 clks <7=> 14 clks +;// <o3.11..12> Tcos: Chip Select Set-up nOE +;// <0=> 0 clk <1=> 1 clk <2=> 2 clks <3=> 4 clks +;// <o3.13..14> Tacs: Address Set-up before nGCSn +;// <0=> 0 clk <1=> 1 clk <2=> 2 clks <3=> 4 clks +;// </h> +;// +;// <h> Bank 4 +;// <o8.16..17> DW: Data Bus Width +;// <0=> 8-bit <1=> 16-bit <2=> 32-bit <3=> Rsrvd +;// <o8.18> WS: WAIT Status +;// <0=> WAIT Disable +;// <1=> WAIT Enable +;// <o8.19> ST: SRAM Type +;// <0=> Not using UB/LB +;// <1=> Using UB/LB +;// <o4.0..1> PMC: Page Mode Configuration +;// <0=> 1 Data <1=> 4 Data <2=> 8 Data <3=> 16 Data +;// <o4.2..3> Tpac: Page Mode Access Cycle +;// <0=> 2 clks <1=> 3 clks <2=> 4 clks <3=> 6 clks +;// <o4.4..5> Tcah: Address Holding Time after nGCSn +;// <0=> 0 clk <1=> 1 clk <2=> 2 clks <3=> 4 clks +;// <o4.6..7> Toch: Chip Select Hold on nOE +;// <0=> 0 clk <1=> 1 clk <2=> 2 clks <3=> 4 clks +;// <o4.8..10> Tacc: Access Cycle +;// <0=> 1 clk <1=> 2 clks <2=> 3 clks <3=> 4 clks +;// <4=> 6 clk <5=> 8 clks <6=> 10 clks <7=> 14 clks +;// <o4.11..12> Tcos: Chip Select Set-up nOE +;// <0=> 0 clk <1=> 1 clk <2=> 2 clks <3=> 4 clks +;// <o4.13..14> Tacs: Address Set-up before nGCSn +;// <0=> 0 clk <1=> 1 clk <2=> 2 clks <3=> 4 clks +;// </h> +;// +;// <h> Bank 5 +;// <o8.20..21> DW: Data Bus Width +;// <0=> 8-bit <1=> 16-bit <2=> 32-bit <3=> Rsrvd +;// <o8.22> WS: WAIT Status +;// <0=> WAIT Disable +;// <1=> WAIT Enable +;// <o8.23> ST: SRAM Type +;// <0=> Not using UB/LB +;// <1=> Using UB/LB +;// <o5.0..1> PMC: Page Mode Configuration +;// <0=> 1 Data <1=> 4 Data <2=> 8 Data <3=> 16 Data +;// <o5.2..3> Tpac: Page Mode Access Cycle +;// <0=> 2 clks <1=> 3 clks <2=> 4 clks <3=> 6 clks +;// <o5.4..5> Tcah: Address Holding Time after nGCSn +;// <0=> 0 clk <1=> 1 clk <2=> 2 clks <3=> 4 clks +;// <o5.6..7> Toch: Chip Select Hold on nOE +;// <0=> 0 clk <1=> 1 clk <2=> 2 clks <3=> 4 clks +;// <o5.8..10> Tacc: Access Cycle +;// <0=> 1 clk <1=> 2 clks <2=> 3 clks <3=> 4 clks +;// <4=> 6 clk <5=> 8 clks <6=> 10 clks <7=> 14 clks +;// <o5.11..12> Tcos: Chip Select Set-up nOE +;// <0=> 0 clk <1=> 1 clk <2=> 2 clks <3=> 4 clks +;// <o5.13..14> Tacs: Address Set-up before nGCSn +;// <0=> 0 clk <1=> 1 clk <2=> 2 clks <3=> 4 clks +;// </h> +;// +;// <h> Bank 6 +;// <o10.0..2> BK76MAP: Bank 6/7 Memory Map +;// <0=> 32M <4=> 2M <5=> 4M <6=> 8M <7=> 16M +;// <o8.24..25> DW: Data Bus Width +;// <0=> 8-bit <1=> 16-bit <2=> 32-bit <3=> Rsrvd +;// <o8.26> WS: WAIT Status +;// <0=> WAIT Disable +;// <1=> WAIT Enable +;// <o8.27> ST: SRAM Type +;// <0=> Not using UB/LB +;// <1=> Using UB/LB +;// <o6.15..16> MT: Memory Type +;// <0=> ROM or SRAM +;// <1=> FP DRAMP +;// <2=> EDO DRAM +;// <3=> SDRAM +;// <h> ROM or SRAM +;// <o6.0..1> PMC: Page Mode Configuration +;// <0=> 1 Data <1=> 4 Data <2=> 8 Data <3=> 16 Data +;// <o6.2..3> Tpac: Page Mode Access Cycle +;// <0=> 2 clks <1=> 3 clks <2=> 4 clks <3=> 6 clks +;// <o6.4..5> Tcah: Address Holding Time after nGCSn +;// <0=> 0 clk <1=> 1 clk <2=> 2 clks <3=> 4 clks +;// <o6.6..7> Toch: Chip Select Hold on nOE +;// <0=> 0 clk <1=> 1 clk <2=> 2 clks <3=> 4 clks +;// <o6.8..10> Tacc: Access Cycle +;// <0=> 1 clk <1=> 2 clks <2=> 3 clks <3=> 4 clks +;// <4=> 6 clk <5=> 8 clks <6=> 10 clks <7=> 14 clks +;// <o6.11..12> Tcos: Chip Select Set-up nOE +;// <0=> 0 clk <1=> 1 clk <2=> 2 clks <3=> 4 clks +;// <o6.13..14> Tacs: Address Set-up before nGCSn +;// <0=> 0 clk <1=> 1 clk <2=> 2 clks <3=> 4 clks +;// </h> +;// <h> FP DRAM or EDO DRAM +;// <o6.0..1> CAN: Columnn Address Number +;// <0=> 8-bit <1=> 9-bit <2=> 10-bit <3=> 11-bit +;// <o6.2> Tcp: CAS Pre-charge +;// <0=> 1 clk <1=> 2 clks +;// <o6.3> Tcas: CAS Pulse Width +;// <0=> 1 clk <1=> 2 clks +;// <o6.4..5> Trcd: RAS to CAS Delay +;// <0=> 1 clk <1=> 2 clks <2=> 3 clks <3=> 4 clks +;// </h> +;// <h> SDRAM +;// <o6.0..1> SCAN: Columnn Address Number +;// <0=> 8-bit <1=> 9-bit <2=> 10-bit <3=> Rsrvd +;// <o6.2..3> Trcd: RAS to CAS Delay +;// <0=> 2 clks <1=> 3 clks <2=> 4 clks <3=> Rsrvd +;// <o10.4> SCLKEN: SCLK Selection (Bank 6/7) +;// <0=> Normal +;// <1=> Reduced Power +;// <o11.0..2> BL: Burst Length +;// <0=> 1 +;// <o11.3> BT: Burst Type +;// <0=> Sequential +;// <o11.4..6> CL: CAS Latency +;// <0=> 1 clk <1=> 2 clks <2=> 3 clks +;// <o11.7..8> TM: Test Mode +;// <0=> Mode Register Set +;// <o11.9> WBL: Write Burst Length +;// <0=> 0 +;// </h> +;// </h> +;// +;// <h> Bank 7 +;// <o10.0..2> BK76MAP: Bank 6/7 Memory Map +;// <0=> 32M <4=> 2M <5=> 4M <6=> 8M <7=> 16M +;// <o8.28..29> DW: Data Bus Width +;// <0=> 8-bit <1=> 16-bit <2=> 32-bit <3=> Rsrvd +;// <o8.30> WS: WAIT Status +;// <0=> WAIT Disable +;// <1=> WAIT Enable +;// <o8.31> ST: SRAM Type +;// <0=> Not using UB/LB +;// <1=> Using UB/LB +;// <o7.15..16> MT: Memory Type +;// <0=> ROM or SRAM +;// <1=> FP DRAMP +;// <2=> EDO DRAM +;// <3=> SDRAM +;// <h> ROM or SRAM +;// <o7.0..1> PMC: Page Mode Configuration +;// <0=> 1 Data <1=> 4 Data <2=> 8 Data <3=> 16 Data +;// <o7.2..3> Tpac: Page Mode Access Cycle +;// <0=> 2 clks <1=> 3 clks <2=> 4 clks <3=> 6 clks +;// <o7.4..5> Tcah: Address Holding Time after nGCSn +;// <0=> 0 clk <1=> 1 clk <2=> 2 clks <3=> 4 clks +;// <o7.6..7> Toch: Chip Select Hold on nOE +;// <0=> 0 clk <1=> 1 clk <2=> 2 clks <3=> 4 clks +;// <o7.8..10> Tacc: Access Cycle +;// <0=> 1 clk <1=> 2 clks <2=> 3 clks <3=> 4 clks +;// <4=> 6 clk <5=> 8 clks <6=> 10 clks <7=> 14 clks +;// <o7.11..12> Tcos: Chip Select Set-up nOE +;// <0=> 0 clk <1=> 1 clk <2=> 2 clks <3=> 4 clks +;// <o7.13..14> Tacs: Address Set-up before nGCSn +;// <0=> 0 clk <1=> 1 clk <2=> 2 clks <3=> 4 clks +;// </h> +;// <h> FP DRAM or EDO DRAM +;// <o7.0..1> CAN: Columnn Address Number +;// <0=> 8-bit <1=> 9-bit <2=> 10-bit <3=> 11-bit +;// <o7.2> Tcp: CAS Pre-charge +;// <0=> 1 clk <1=> 2 clks +;// <o7.3> Tcas: CAS Pulse Width +;// <0=> 1 clk <1=> 2 clks +;// <o7.4..5> Trcd: RAS to CAS Delay +;// <0=> 1 clk <1=> 2 clks <2=> 3 clks <3=> 4 clks +;// </h> +;// <h> SDRAM +;// <o7.0..1> SCAN: Columnn Address Number +;// <0=> 8-bit <1=> 9-bit <2=> 10-bit <3=> Rsrvd +;// <o7.2..3> Trcd: RAS to CAS Delay +;// <0=> 2 clks <1=> 3 clks <2=> 4 clks <3=> Rsrvd +;// <o10.4> SCLKEN: SCLK Selection (Bank 6/7) +;// <0=> Normal +;// <1=> Reduced Power +;// <o12.0..2> BL: Burst Length +;// <0=> 1 +;// <o12.3> BT: Burst Type +;// <0=> Sequential +;// <o12.4..6> CL: CAS Latency +;// <0=> 1 clk <1=> 2 clks <2=> 3 clks +;// <o12.7..8> TM: Test Mode +;// <0=> Mode Register Set +;// <o12.9> WBL: Write Burst Length +;// <0=> 0 +;// </h> +;// </h> +;// +;// <h> Refresh +;// <o9.23> REFEN: DRAM/SDRAM Refresh +;// <0=> Disable <1=> Enable +;// <o9.22> TREFMD: DRAM/SDRAM Refresh Mode +;// <0=> CBR/Auto Refresh +;// <1=> Self Refresh +;// <o9.20..21> Trp: DRAM/SDRAM RAS Pre-charge Time +;// <0=> 1.5 clks (DRAM) / 2 clks (SDRAM) +;// <1=> 2.5 clks (DRAM) / 3 clks (SDRAM) +;// <2=> 3.5 clks (DRAM) / 4 clks (SDRAM) +;// <3=> 4.5 clks (DRAM) / Rsrvd (SDRAM) +;// <o9.18..19> Trc: SDRAM RC Min Time +;// <0=> 4 clks <1=> 5 clks <2=> 6 clks <3=> 7 clks +;// <o9.16..17> Tchr: DRAM CAS Hold Time +;// <0=> 1 clks <1=> 2 clks <2=> 3 clks <3=> 4 clks +;// <o9.0..10> Refresh Counter <0x0-0x07FF> +;// <i> Refresh Period = (2^11 - Refresh Count + 1) / MCLK +;// </h> +BANKCON0_Val EQU 0x00000700 +BANKCON1_Val EQU 0x00000700 +BANKCON2_Val EQU 0x00000700 +BANKCON3_Val EQU 0x00000700 +BANKCON4_Val EQU 0x00000700 +BANKCON5_Val EQU 0x00000700 +BANKCON6_Val EQU 0x00018008 +BANKCON7_Val EQU 0x00018008 +BWSCON_Val EQU 0x00000000 +REFRESH_Val EQU 0x00AC0000 +BANKSIZE_Val EQU 0x00000000 +MRSRB6_Val EQU 0x00000000 +MRSRB7_Val EQU 0x00000000 + +;// </e> End of MC + + +; I/O Ports definitions +PIO_BASE EQU 0x01D20000 ; PIO Base Address +PCONA_OFS EQU 0x00 ; PCONA Offset +PCONB_OFS EQU 0x08 ; PCONB Offset +PCONC_OFS EQU 0x10 ; PCONC Offset +PCOND_OFS EQU 0x1C ; PCOND Offset +PCONE_OFS EQU 0x28 ; PCONE Offset +PCONF_OFS EQU 0x34 ; PCONF Offset +PCONG_OFS EQU 0x40 ; PCONG Offset +PUPC_OFS EQU 0x18 ; PUPC Offset +PUPD_OFS EQU 0x24 ; PUPD Offset +PUPE_OFS EQU 0x30 ; PUPE Offset +PUPF_OFS EQU 0x3C ; PUPF Offset +PUPG_OFS EQU 0x48 ; PUPG Offset +SPUCR_OFS EQU 0x4C ; SPUCR Offset + +;// <e> I/O Configuration +PIO_SETUP EQU 0 + +;// <e> Port A +;// <o1.0> PA0 <0=> Output <1=> ADDR0 +;// <o1.1> PA1 <0=> Output <1=> ADDR16 +;// <o1.2> PA2 <0=> Output <1=> ADDR17 +;// <o1.3> PA3 <0=> Output <1=> ADDR18 +;// <o1.4> PA4 <0=> Output <1=> ADDR19 +;// <o1.5> PA5 <0=> Output <1=> ADDR20 +;// <o1.6> PA6 <0=> Output <1=> ADDR21 +;// <o1.7> PA7 <0=> Output <1=> ADDR22 +;// <o1.8> PA8 <0=> Output <1=> ADDR23 +;// <o1.9> PA9 <0=> Output <1=> ADDR24 +;// </e> +PIOA_SETUP EQU 1 +PCONA_Val EQU 0x000003FF + +;// <e> Port B +;// <o1.0> PB0 <0=> Output <1=> SCKE +;// <o1.1> PB1 <0=> Output <1=> CKLK +;// <o1.2> PB2 <0=> Output <1=> nSCAS/nCAS2 +;// <o1.3> PB3 <0=> Output <1=> nSRAS/nCAS3 +;// <o1.4> PB4 <0=> Output <1=> nWBE2/nBE2/DQM2 +;// <o1.5> PB5 <0=> Output <1=> nWBE3/nBE3/DQM3 +;// <o1.6> PB6 <0=> Output <1=> nGCS1 +;// <o1.7> PB7 <0=> Output <1=> nGCS2 +;// <o1.8> PB8 <0=> Output <1=> nGCS3 +;// <o1.9> PB9 <0=> Output <1=> nGCS4 +;// <o1.10> PB10 <0=> Output <1=> nGCS5 +;// </e> +PIOB_SETUP EQU 1 +PCONB_Val EQU 0x000007FF + +;// <e> Port C +;// <o1.0..1> PC0 <0=> Input <1=> Output <2=> DATA16 <3=> IISLRCK +;// <o1.2..3> PC1 <0=> Input <1=> Output <2=> DATA17 <3=> IISDO +;// <o1.4..5> PC2 <0=> Input <1=> Output <2=> DATA18 <3=> IISDI +;// <o1.6..7> PC3 <0=> Input <1=> Output <2=> DATA19 <3=> IISCLK +;// <o1.8..9> PC4 <0=> Input <1=> Output <2=> DATA20 <3=> VD7 +;// <o1.10..11> PC5 <0=> Input <1=> Output <2=> DATA21 <3=> VD6 +;// <o1.12..13> PC6 <0=> Input <1=> Output <2=> DATA22 <3=> VD5 +;// <o1.14..15> PC7 <0=> Input <1=> Output <2=> DATA23 <3=> VD4 +;// <o1.16..17> PC8 <0=> Input <1=> Output <2=> DATA24 <3=> nXDACK1 +;// <o1.18..19> PC9 <0=> Input <1=> Output <2=> DATA25 <3=> nXDREQ1 +;// <o1.20..21> PC10 <0=> Input <1=> Output <2=> DATA26 <3=> nRTS1 +;// <o1.22..23> PC11 <0=> Input <1=> Output <2=> DATA27 <3=> nCTS1 +;// <o1.24..25> PC12 <0=> Input <1=> Output <2=> DATA28 <3=> TxD1 +;// <o1.26..27> PC13 <0=> Input <1=> Output <2=> DATA29 <3=> RxD1 +;// <o1.28..29> PC14 <0=> Input <1=> Output <2=> DATA30 <3=> nRTS0 +;// <o1.30..31> PC15 <0=> Input <1=> Output <2=> DATA31 <3=> nCTS0 +;// <h> Pull-up Resistors +;// <o2.0> PC0 Pull-up <0=> Enabled <1=> Disabled +;// <o2.1> PC1 Pull-up <0=> Enabled <1=> Disabled +;// <o2.2> PC2 Pull-up <0=> Enabled <1=> Disabled +;// <o2.3> PC3 Pull-up <0=> Enabled <1=> Disabled +;// <o2.4> PC4 Pull-up <0=> Enabled <1=> Disabled +;// <o2.5> PC5 Pull-up <0=> Enabled <1=> Disabled +;// <o2.6> PC6 Pull-up <0=> Enabled <1=> Disabled +;// <o2.7> PC7 Pull-up <0=> Enabled <1=> Disabled +;// <o2.8> PC8 Pull-up <0=> Enabled <1=> Disabled +;// <o2.9> PC9 Pull-up <0=> Enabled <1=> Disabled +;// <o2.10> PC10 Pull-up <0=> Enabled <1=> Disabled +;// <o2.11> PC11 Pull-up <0=> Enabled <1=> Disabled +;// <o2.12> PC12 Pull-up <0=> Enabled <1=> Disabled +;// <o2.13> PC13 Pull-up <0=> Enabled <1=> Disabled +;// <o2.14> PC14 Pull-up <0=> Enabled <1=> Disabled +;// <o2.15> PC15 Pull-up <0=> Enabled <1=> Disabled +;// </h> +;// </e> +PIOC_SETUP EQU 1 +PCONC_Val EQU 0xAAAAAAAA +PUPC_Val EQU 0x00000000 + +;// <e> Port D +;// <o1.0..1> PD0 <0=> Input <1=> Output <2=> VD0 <3=> Reserved +;// <o1.2..3> PD1 <0=> Input <1=> Output <2=> VD1 <3=> Reserved +;// <o1.4..5> PD2 <0=> Input <1=> Output <2=> VD2 <3=> Reserved +;// <o1.6..7> PD3 <0=> Input <1=> Output <2=> VD3 <3=> Reserved +;// <o1.8..9> PD4 <0=> Input <1=> Output <2=> VCLK <3=> Reserved +;// <o1.10..11> PD5 <0=> Input <1=> Output <2=> VLINE <3=> Reserved +;// <o1.12..13> PD6 <0=> Input <1=> Output <2=> VM <3=> Reserved +;// <o1.14..15> PD7 <0=> Input <1=> Output <2=> VFRAME <3=> Reserved +;// <h> Pull-up Resistors +;// <o2.0> PD0 Pull-up <0=> Enabled <1=> Disabled +;// <o2.1> PD1 Pull-up <0=> Enabled <1=> Disabled +;// <o2.2> PD2 Pull-up <0=> Enabled <1=> Disabled +;// <o2.3> PD3 Pull-up <0=> Enabled <1=> Disabled +;// <o2.4> PD4 Pull-up <0=> Enabled <1=> Disabled +;// <o2.5> PD5 Pull-up <0=> Enabled <1=> Disabled +;// <o2.6> PD6 Pull-up <0=> Enabled <1=> Disabled +;// <o2.7> PD7 Pull-up <0=> Enabled <1=> Disabled +;// </h> +;// </e> +PIOD_SETUP EQU 1 +PCOND_Val EQU 0x00000000 +PUPD_Val EQU 0x00000000 + +;// <e> Port E +;// <o1.0..1> PE0 <0=> Input <1=> Output <2=> Fpllo <3=> Fout +;// <o1.2..3> PE1 <0=> Input <1=> Output <2=> TxD0 <3=> Reserved +;// <o1.4..5> PE2 <0=> Input <1=> Output <2=> RxD0 <3=> Reserved +;// <o1.6..7> PE3 <0=> Input <1=> Output <2=> TOUT0 <3=> Reserved +;// <o1.8..9> PE4 <0=> Input <1=> Output <2=> TOUT1 <3=> TCLK +;// <o1.10..11> PE5 <0=> Input <1=> Output <2=> TOUT2 <3=> TCLK +;// <o1.12..13> PE6 <0=> Input <1=> Output <2=> TOUT3 <3=> VD6 +;// <o1.14..15> PE7 <0=> Input <1=> Output <2=> TOUT4 <3=> VD7 +;// <o1.16..17> PE8 <0=> Input <1=> Output <2=> CODECLK <3=> Reserved +;// <h> Pull-up Resistors +;// <o2.0> PE0 Pull-up <0=> Enabled <1=> Disabled +;// <o2.1> PE1 Pull-up <0=> Enabled <1=> Disabled +;// <o2.2> PE2 Pull-up <0=> Enabled <1=> Disabled +;// <o2.3> PE3 Pull-up <0=> Enabled <1=> Disabled +;// <o2.4> PE4 Pull-up <0=> Enabled <1=> Disabled +;// <o2.5> PE5 Pull-up <0=> Enabled <1=> Disabled +;// <o2.6> PE6 Pull-up <0=> Enabled <1=> Disabled +;// <o2.7> PE7 Pull-up <0=> Enabled <1=> Disabled +;// <o2.8> PE8 Pull-up <0=> Enabled <1=> Disabled +;// </h> +;// </e> +PIOE_SETUP EQU 1 +PCONE_Val EQU 0x00000000 +PUPE_Val EQU 0x00000000 + +;// <e> Port F +;// <o1.0..1> PF0 <0=> Input <1=> Output <2=> IICSCL <3=> Reserved +;// <o1.2..3> PF1 <0=> Input <1=> Output <2=> IICSDA <3=> Reserved +;// <o1.4..5> PF2 <0=> Input <1=> Output <2=> nWAIT <3=> Reserved +;// <o1.6..7> PF3 <0=> Input <1=> Output <2=> nXBACK <3=> nXDACK0 +;// <o1.8..9> PF4 <0=> Input <1=> Output <2=> nXBREQ <3=> nXDREQ0 +;// <o1.10..12> PF5 <0=> Input <1=> Output <2=> nRTS1 <3=> SIOTxD +;// <4=> IISLRCK <5=> Reserved <6=> Reserved <7=> Reserved +;// <o1.13..15> PF6 <0=> Input <1=> Output <2=> TxD1 <3=> SIORDY +;// <4=> IISDO <5=> Reserved <6=> Reserved <7=> Reserved +;// <o1.16..18> PF7 <0=> Input <1=> Output <2=> RxD1 <3=> SIORxD +;// <4=> IISDI <5=> Reserved <6=> Reserved <7=> Reserved +;// <o1.19..21> PF8 <0=> Input <1=> Output <2=> nCTS1 <3=> SIOCLK +;// <4=> IISCLK <5=> Reserved <6=> Reserved <7=> Reserved +;// <h> Pull-up Resistors +;// <o2.0> PF0 Pull-up <0=> Enabled <1=> Disabled +;// <o2.1> PF1 Pull-up <0=> Enabled <1=> Disabled +;// <o2.2> PF2 Pull-up <0=> Enabled <1=> Disabled +;// <o2.3> PF3 Pull-up <0=> Enabled <1=> Disabled +;// <o2.4> PF4 Pull-up <0=> Enabled <1=> Disabled +;// <o2.5> PF5 Pull-up <0=> Enabled <1=> Disabled +;// <o2.6> PF6 Pull-up <0=> Enabled <1=> Disabled +;// <o2.7> PF7 Pull-up <0=> Enabled <1=> Disabled +;// <o2.8> PF8 Pull-up <0=> Enabled <1=> Disabled +;// </h> +;// </e> +PIOF_SETUP EQU 1 +PCONF_Val EQU 0x00000000 +PUPF_Val EQU 0x00000000 + +;// <e> Port G +;// <o1.0..1> PG0 <0=> Input <1=> Output <2=> VD4 <3=> EINT0 +;// <o1.2..3> PG1 <0=> Input <1=> Output <2=> VD5 <3=> EINT1 +;// <o1.4..5> PG2 <0=> Input <1=> Output <2=> nCTS0 <3=> EINT2 +;// <o1.6..7> PG3 <0=> Input <1=> Output <2=> nRTS0 <3=> EINT3 +;// <o1.8..9> PG4 <0=> Input <1=> Output <2=> IISCLK <3=> EINT4 +;// <o1.10..11> PG5 <0=> Input <1=> Output <2=> IISDI <3=> EINT5 +;// <o1.12..13> PG6 <0=> Input <1=> Output <2=> IISDO <3=> EINT6 +;// <o1.14..15> PG7 <0=> Input <1=> Output <2=> IISLRCK <3=> EINT7 +;// <h> Pull-up Resistors +;// <o2.0> PG0 Pull-up <0=> Enabled <1=> Disabled +;// <o2.1> PG1 Pull-up <0=> Enabled <1=> Disabled +;// <o2.2> PG2 Pull-up <0=> Enabled <1=> Disabled +;// <o2.3> PG3 Pull-up <0=> Enabled <1=> Disabled +;// <o2.4> PG4 Pull-up <0=> Enabled <1=> Disabled +;// <o2.5> PG5 Pull-up <0=> Enabled <1=> Disabled +;// <o2.6> PG6 Pull-up <0=> Enabled <1=> Disabled +;// <o2.7> PG7 Pull-up <0=> Enabled <1=> Disabled +;// </h> +;// </e> +PIOG_SETUP EQU 1 +PCONG_Val EQU 0x00000000 +PUPG_Val EQU 0x00000000 + +;// <e> Special Pull-up +;// <o1.0> SPUCR0: DATA[7:0] Pull-up Resistor +;// <0=> Enabled <1=> Disabled +;// <o1.1> SPUCR1: DATA[15:8] Pull-up Resistor +;// <0=> Enabled <1=> Disabled +;// <o1.2> HZ@STOP +;// <0=> Prevoius state of PAD +;// <1=> HZ @ Stop +;// </e> +PSPU_SETUP EQU 1 +SPUCR_Val EQU 0x00000004 + +;// </e> + + + PRESERVE8 + + +; Area Definition and Entry Point +; Startup Code must be linked first at Address at which it expects to run. + + AREA RESET, CODE, READONLY + ARM + + +; Exception Vectors +; Mapped to Address 0. +; Absolute addressing mode must be used. +; Dummy Handlers are implemented as infinite loops which can be modified. + +Vectors LDR PC, Reset_Addr + LDR PC, Undef_Addr + LDR PC, SWI_Addr + LDR PC, PAbt_Addr + LDR PC, DAbt_Addr + NOP ; Reserved Vector + LDR PC, IRQ_Addr + LDR PC, FIQ_Addr + +Reset_Addr DCD Reset_Handler +Undef_Addr DCD Undef_Handler +SWI_Addr DCD SWI_Handler +PAbt_Addr DCD PAbt_Handler +DAbt_Addr DCD DAbt_Handler + DCD 0 ; Reserved Address +IRQ_Addr DCD IRQ_Handler +FIQ_Addr DCD FIQ_Handler + +Undef_Handler B Undef_Handler +SWI_Handler B SWI_Handler +PAbt_Handler B PAbt_Handler +DAbt_Handler B DAbt_Handler +FIQ_Handler B FIQ_Handler + + +; CPU Wrapper and Bus Priorities Configuration + IF SYS_SETUP <> 0 +SYS_CFG + DCD CPUW_BASE + DCD BUSP_BASE + DCD SYSCFG_Val + DCD NCACHBE0_Val + DCD NCACHBE1_Val + DCD SBUSCON_Val + ENDIF + + +; Memory Controller Configuration + IF MC_SETUP <> 0 +MC_CFG + DCD BWSCON_Val + DCD BANKCON0_Val + DCD BANKCON1_Val + DCD BANKCON2_Val + DCD BANKCON3_Val + DCD BANKCON4_Val + DCD BANKCON5_Val + DCD BANKCON6_Val + DCD BANKCON7_Val + DCD REFRESH_Val + DCD BANKSIZE_Val + DCD MRSRB6_Val + DCD MRSRB7_Val + ENDIF + + +; Clock Management Configuration + IF CLK_SETUP <> 0 +CLK_CFG + DCD CLK_BASE + DCD PLLCON_Val + DCD CLKCON_Val + DCD CLKSLOW_Val + DCD LOCKTIME_Val + ENDIF + + +; I/O Configuration + IF PIO_SETUP <> 0 +PIO_CFG + DCD PCONA_Val + DCD PCONB_Val + DCD PCONC_Val + DCD PCOND_Val + DCD PCONE_Val + DCD PCONF_Val + DCD PCONG_Val + DCD PUPC_Val + DCD PUPD_Val + DCD PUPE_Val + DCD PUPF_Val + DCD PUPG_Val + DCD SPUCR_Val + ENDIF + + +; Reset Handler + + EXPORT Reset_Handler +Reset_Handler + + + IF SYS_SETUP <> 0 + ADR R8, SYS_CFG + LDMIA R8, {R0-R5} + STMIA R0, {R2-R4} + STR R5, [R1] + ENDIF + + + IF MC_SETUP <> 0 + ADR R14, MC_CFG + LDMIA R14, {R0-R12} + LDR R14, =MC_BASE + STMIA R14, {R0-R12} + ENDIF + + + IF CLK_SETUP <> 0 + ADR R8, CLK_CFG + LDMIA R8, {R0-R4} + STR R4, [R0, #LOCKTIME_OFS] + STR R1, [R0, #PLLCON_OFS] + STR R3, [R0, #CLKSLOW_OFS] + STR R2, [R0, #CLKCON_OFS] + ENDIF + + + IF WT_SETUP <> 0 + LDR R0, =WT_BASE + LDR R1, =WTCON_Val + LDR R2, =WTDAT_Val + STR R2, [R0, #WTCNT_OFS] + STR R2, [R0, #WTDAT_OFS] + STR R1, [R0, #WTCON_OFS] + ENDIF + + + IF PIO_SETUP <> 0 + ADR R14, PIO_CFG + LDMIA R14, {R0-R12} + LDR R14, =PIO_BASE + + IF PIOA_SETUP <> 0 + STR R0, [R14, #PCONA_OFS] + ENDIF + + IF PIOB_SETUP <> 0 + STR R1, [R14, #PCONB_OFS] + ENDIF + + IF PIOC_SETUP <> 0 + STR R2, [R14, #PCONC_OFS] + STR R7, [R14, #PUPC_OFS] + ENDIF + + IF PIOD_SETUP <> 0 + STR R3, [R14, #PCOND_OFS] + STR R8, [R14, #PUPD_OFS] + ENDIF + + IF PIOE_SETUP <> 0 + STR R4, [R14, #PCONE_OFS] + STR R9, [R14, #PUPE_OFS] + ENDIF + + IF PIOF_SETUP <> 0 + STR R5, [R14, #PCONF_OFS] + STR R10,[R14, #PUPF_OFS] + ENDIF + + IF PIOG_SETUP <> 0 + STR R6, [R14, #PCONG_OFS] + STR R11,[R14, #PUPG_OFS] + ENDIF + + IF PSPU_SETUP <> 0 + STR R12,[R14, #SPUCR_OFS] + ENDIF + + ENDIF + + +; Setup Stack for each mode + + LDR R0, =Stack_Top + +; Enter Undefined Instruction Mode and set its Stack Pointer + MSR CPSR_c, #Mode_UND:OR:I_Bit:OR:F_Bit + MOV SP, R0 + SUB R0, R0, #UND_Stack_Size + +; Enter Abort Mode and set its Stack Pointer + MSR CPSR_c, #Mode_ABT:OR:I_Bit:OR:F_Bit + MOV SP, R0 + SUB R0, R0, #ABT_Stack_Size + +; Enter FIQ Mode and set its Stack Pointer + MSR CPSR_c, #Mode_FIQ:OR:I_Bit:OR:F_Bit + MOV SP, R0 + SUB R0, R0, #FIQ_Stack_Size + +; Enter IRQ Mode and set its Stack Pointer + MSR CPSR_c, #Mode_IRQ:OR:I_Bit:OR:F_Bit + MOV SP, R0 + SUB R0, R0, #IRQ_Stack_Size + +; Enter Supervisor Mode and set its Stack Pointer + MSR CPSR_c, #Mode_SVC:OR:I_Bit:OR:F_Bit + MOV SP, R0 + SUB R0, R0, #SVC_Stack_Size + +; Enter User Mode and set its Stack Pointer + ; MSR CPSR_c, #Mode_USR + IF :DEF:__MICROLIB + + EXPORT __initial_sp + + ELSE + + ; MOV SP, R0 + ; SUB SL, SP, #USR_Stack_Size + + ENDIF + + +; Enter the C code + + IMPORT __main + LDR R0, =__main + BX R0 + + IMPORT rt_interrupt_enter + IMPORT rt_interrupt_leave + IMPORT rt_thread_switch_interrupt_flag + IMPORT rt_interrupt_from_thread + IMPORT rt_interrupt_to_thread + IMPORT rt_hw_trap_irq + +IRQ_Handler PROC + EXPORT IRQ_Handler + STMFD sp!, {r0-r12,lr} + BL rt_interrupt_enter + BL rt_hw_trap_irq + BL rt_interrupt_leave + + ; if rt_thread_switch_interrupt_flag set, jump to + ; rt_hw_context_switch_interrupt_do and don't return + LDR r0, =rt_thread_switch_interrupt_flag + LDR r1, [r0] + CMP r1, #1 + BEQ rt_hw_context_switch_interrupt_do + + LDMFD sp!, {r0-r12,lr} + SUBS pc, lr, #4 + ENDP + +; /* +; * void rt_hw_context_switch_interrupt_do(rt_base_t flag) +; */ +rt_hw_context_switch_interrupt_do PROC + EXPORT rt_hw_context_switch_interrupt_do + MOV r1, #0 ; clear flag + STR r1, [r0] + + LDMFD sp!, {r0-r12,lr}; reload saved registers + STMFD sp!, {r0-r3} ; save r0-r3 + MOV r1, sp + ADD sp, sp, #16 ; restore sp + SUB r2, lr, #4 ; save old task's pc to r2 + + MRS r3, spsr ; get cpsr of interrupt thread + + ; switch to SVC mode and no interrupt + MSR cpsr_c, #I_Bit|F_Bit|Mode_SVC + + STMFD sp!, {r2} ; push old task's pc + STMFD sp!, {r4-r12,lr}; push old task's lr,r12-r4 + MOV r4, r1 ; Special optimised code below + MOV r5, r3 + LDMFD r4!, {r0-r3} + STMFD sp!, {r0-r3} ; push old task's r3-r0 + STMFD sp!, {r5} ; push old task's cpsr + MRS r4, spsr + STMFD sp!, {r4} ; push old task's spsr + + LDR r4, =rt_interrupt_from_thread + LDR r5, [r4] + STR sp, [r5] ; store sp in preempted tasks's TCB + + LDR r6, =rt_interrupt_to_thread + LDR r6, [r6] + LDR sp, [r6] ; get new task's stack pointer + + LDMFD sp!, {r4} ; pop new task's spsr + MSR spsr_cxsf, r4 + LDMFD sp!, {r4} ; pop new task's psr + MSR cpsr_cxsf, r4 + + LDMFD sp!, {r0-r12,lr,pc} ; pop new task's r0-r12,lr & pc + ENDP + + IF :DEF:__MICROLIB + + EXPORT __heap_base + EXPORT __heap_limit + + ELSE +; User Initial Stack & Heap + AREA |.text|, CODE, READONLY + + IMPORT __use_two_region_memory + EXPORT __user_initial_stackheap +__user_initial_stackheap + + LDR R0, = Heap_Mem + LDR R1, =(Stack_Mem + USR_Stack_Size) + LDR R2, = (Heap_Mem + Heap_Size) + LDR R3, = Stack_Mem + BX LR + ENDIF + + + END diff --git a/libcpu/arm/sep4020/clk.c b/libcpu/arm/sep4020/clk.c index 7ed3bb8043..9de17b3077 100644 --- a/libcpu/arm/sep4020/clk.c +++ b/libcpu/arm/sep4020/clk.c @@ -1,112 +1,112 @@ -/*
- * File : clock.c
- * This file is part of RT-Thread RTOS
- * COPYRIGHT (C) 2006, RT-Thread Development Team
- *
- * The license and distribution terms for this file may be
- * found in the file LICENSE in this distribution or at
- * http://openlab.rt-thread.com/license/LICENSE
- *
- * Change Logs:
- * Date Author Notes
- * 2010-03-20 zchong first version
- */
-
-#include <rtthread.h>
-#include "sep4020.h"
-
-#define CLK_IN 4000000 /* Fin = 4.00MHz */
-#define SYSCLK 72000000 /* system clock we want */
-
-#define CLK_ESRAM 0
-#define CLK_LCDC 1
-#define CLK_PWM 2
-#define CLK_DMAC 3
-#define CLK_EMI 4
-#define CLK_MMCSD 5
-#define CLK_SSI 7
-#define CLK_UART0 8
-#define CLK_UART1 9
-#define CLK_UART2 10
-#define CLK_UART3 11
-#define CLK_USB 12
-#define CLK_MAC 13
-#define CLK_SMC 14
-#define CLK_I2C 15
-#define CLK_GPT 16
-
-static void rt_hw_set_system_clock(void)
-{
- rt_uint8_t pv;
-
- /* pv value*/
- pv = SYSCLK/2/CLK_IN;
- /* go to normal mode*/
- *(RP)PMU_PMDR = 0x01;
- /* set the clock */
- *(RP)PMU_PMCR = 0x4000 | pv;
- /* trige configurate*/
- *(RP)PMU_PMCR = 0xc000 | pv;
-}
-
-static void rt_hw_set_usb_clock(void)
-{
- /* set the clock */
- *(RP)PMU_PUCR = 0x000c;
- /* trige configurate*/
- *(RP)PMU_PMCR = 0x800c;
-
-}
-
-/**
- * @brief System Clock Configuration
- */
-void rt_hw_clock_init(void)
-{
- /* set system clock */
- rt_hw_set_system_clock();
- /* set usb clock */
- rt_hw_set_usb_clock();
-}
-
-/**
- * @brief Get system clock
- */
-rt_uint32_t rt_hw_get_clock(void)
-{
- rt_uint32_t val;
- rt_uint8_t pv, pd, npd;
-
- /* get PMCR value */
- val =*(RP) PMU_PMCR;
- /* get NPD */
- npd = (val >> 14) & 0x01;
- /* get PD */
- pd = (val >> 10) & 0x0f;
- /* get PV */
- pv = val & 0x7f;
- /* caculate the system clock */
- if(npd)
- val = 2 * CLK_IN * pv;
- else
- val = CLK_IN * pv / (pd + 1);
-
- return(val);
-}
-
-/**
- * @brief Enable module clock
- */
- void rt_hw_enable_module_clock(rt_uint8_t module)
- {
-
- }
-
-/**
- * @brief Disable module clock
- */
- void rt_hw_disable_module_clock(rt_uint8_t module)
- {
-
- }
-
+/* + * File : clock.c + * This file is part of RT-Thread RTOS + * COPYRIGHT (C) 2006, RT-Thread Development Team + * + * The license and distribution terms for this file may be + * found in the file LICENSE in this distribution or at + * http://openlab.rt-thread.com/license/LICENSE + * + * Change Logs: + * Date Author Notes + * 2010-03-20 zchong first version + */ + +#include <rtthread.h> +#include "sep4020.h" + +#define CLK_IN 4000000 /* Fin = 4.00MHz */ +#define SYSCLK 72000000 /* system clock we want */ + +#define CLK_ESRAM 0 +#define CLK_LCDC 1 +#define CLK_PWM 2 +#define CLK_DMAC 3 +#define CLK_EMI 4 +#define CLK_MMCSD 5 +#define CLK_SSI 7 +#define CLK_UART0 8 +#define CLK_UART1 9 +#define CLK_UART2 10 +#define CLK_UART3 11 +#define CLK_USB 12 +#define CLK_MAC 13 +#define CLK_SMC 14 +#define CLK_I2C 15 +#define CLK_GPT 16 + +static void rt_hw_set_system_clock(void) +{ + rt_uint8_t pv; + + /* pv value*/ + pv = SYSCLK/2/CLK_IN; + /* go to normal mode*/ + *(RP)PMU_PMDR = 0x01; + /* set the clock */ + *(RP)PMU_PMCR = 0x4000 | pv; + /* trige configurate*/ + *(RP)PMU_PMCR = 0xc000 | pv; +} + +static void rt_hw_set_usb_clock(void) +{ + /* set the clock */ + *(RP)PMU_PUCR = 0x000c; + /* trige configurate*/ + *(RP)PMU_PMCR = 0x800c; + +} + +/** + * @brief System Clock Configuration + */ +void rt_hw_clock_init(void) +{ + /* set system clock */ + rt_hw_set_system_clock(); + /* set usb clock */ + rt_hw_set_usb_clock(); +} + +/** + * @brief Get system clock + */ +rt_uint32_t rt_hw_get_clock(void) +{ + rt_uint32_t val; + rt_uint8_t pv, pd, npd; + + /* get PMCR value */ + val =*(RP) PMU_PMCR; + /* get NPD */ + npd = (val >> 14) & 0x01; + /* get PD */ + pd = (val >> 10) & 0x0f; + /* get PV */ + pv = val & 0x7f; + /* caculate the system clock */ + if(npd) + val = 2 * CLK_IN * pv; + else + val = CLK_IN * pv / (pd + 1); + + return(val); +} + +/** + * @brief Enable module clock + */ + void rt_hw_enable_module_clock(rt_uint8_t module) + { + + } + +/** + * @brief Disable module clock + */ + void rt_hw_disable_module_clock(rt_uint8_t module) + { + + } + diff --git a/libcpu/arm/sep4020/context_rvds.S b/libcpu/arm/sep4020/context_rvds.S index e24fa62a3d..641ec7a6b1 100644 --- a/libcpu/arm/sep4020/context_rvds.S +++ b/libcpu/arm/sep4020/context_rvds.S @@ -12,12 +12,12 @@ ; * 2009-01-20 Bernard first version ; */ -NOINT EQU 0xc0 ; disable interrupt in psr
+NOINT EQU 0xc0 ; disable interrupt in psr - AREA |.text|, CODE, READONLY, ALIGN=2
- ARM
- REQUIRE8
- PRESERVE8
+ AREA |.text|, CODE, READONLY, ALIGN=2 + ARM + REQUIRE8 + PRESERVE8 ;/* ; * rt_base_t rt_hw_interrupt_disable(); @@ -26,16 +26,16 @@ rt_hw_interrupt_disable PROC EXPORT rt_hw_interrupt_disable MRS r0, cpsr ORR r1, r0, #NOINT - MSR cpsr_c, r1
+ MSR cpsr_c, r1 BX lr - ENDP
+ ENDP ;/* ; * void rt_hw_interrupt_enable(rt_base_t level); ; */ rt_hw_interrupt_enable PROC EXPORT rt_hw_interrupt_enable - MSR cpsr_c, r0
+ MSR cpsr_c, r0 BX lr ENDP @@ -63,7 +63,7 @@ rt_hw_context_switch PROC MSR cpsr_cxsf, r4 LDMFD sp!, {r0-r12, lr, pc} ; pop new task r0-r12, lr & pc - ENDP
+ ENDP ;/* ; * void rt_hw_context_switch_to(rt_uint32 to); @@ -79,14 +79,14 @@ rt_hw_context_switch_to PROC MSR cpsr_cxsf, r4 LDMFD sp!, {r0-r12, lr, pc} ; pop new task r0-r12, lr & pc - ENDP
+ ENDP ;/* ; * void rt_hw_context_switch_interrupt(rt_uint32 from, rt_uint32 to); ; */ IMPORT rt_thread_switch_interrupt_flag IMPORT rt_interrupt_from_thread - IMPORT rt_interrupt_to_thread
+ IMPORT rt_interrupt_to_thread rt_hw_context_switch_interrupt PROC EXPORT rt_hw_context_switch_interrupt @@ -100,8 +100,8 @@ rt_hw_context_switch_interrupt PROC STR r0, [r2] _reswitch LDR r2, =rt_interrupt_to_thread ; set rt_interrupt_to_thread - STR r1, [r2]
+ STR r1, [r2] BX lr - ENDP
-
+ ENDP + END
\ No newline at end of file diff --git a/libcpu/arm/sep4020/cpu.c b/libcpu/arm/sep4020/cpu.c index b497c6a0ae..093f3c1b14 100644 --- a/libcpu/arm/sep4020/cpu.c +++ b/libcpu/arm/sep4020/cpu.c @@ -1,190 +1,190 @@ -/*
- * File : cpu.c
- * This file is part of RT-Thread RTOS
- * COPYRIGHT (C) 2006, RT-Thread Develop Team
- *
- * The license and distribution terms for this file may be
- * found in the file LICENSE in this distribution or at
- * http://openlab.rt-thread.com/license/LICENSE
- *
- * Change Logs:
- * Date Author Notes
- * 2006-03-13 Bernard first version
- */
-
-#include <rtthread.h>
-#include <sep4020.h>
-
-extern rt_uint32_t rt_hw_interrupt_disable(void);
-
-//TODO
-#warning I DON'T KNOW IF THE MMU OPERATION WORKS ON SEP4020
-
-/**
- * @addtogroup S3C24X0
- */
-/*@{*/
-
-#define ICACHE_MASK (rt_uint32_t)(1 << 12)
-#define DCACHE_MASK (rt_uint32_t)(1 << 2)
-
-#ifdef __GNUC__
-rt_inline rt_uint32_t cp15_rd(void)
-{
- rt_uint32_t i;
-
- asm ("mrc p15, 0, %0, c1, c0, 0":"=r" (i));
- return i;
-}
-
-rt_inline void cache_enable(rt_uint32_t bit)
-{
- __asm__ __volatile__( \
- "mrc p15,0,r0,c1,c0,0\n\t" \
- "orr r0,r0,%0\n\t" \
- "mcr p15,0,r0,c1,c0,0" \
- : \
- :"r" (bit) \
- :"memory");
-}
-
-rt_inline void cache_disable(rt_uint32_t bit)
-{
- __asm__ __volatile__( \
- "mrc p15,0,r0,c1,c0,0\n\t" \
- "bic r0,r0,%0\n\t" \
- "mcr p15,0,r0,c1,c0,0" \
- : \
- :"r" (bit) \
- :"memory");
-}
-#endif
-
-#ifdef __CC_ARM
-rt_inline rt_uint32_t cp15_rd(void)
-{
- rt_uint32_t i;
-
- __asm
- {
- mrc p15, 0, i, c1, c0, 0
- }
-
- return i;
-}
-
-rt_inline void cache_enable(rt_uint32_t bit)
-{
- rt_uint32_t value;
-
- __asm
- {
- mrc p15, 0, value, c1, c0, 0
- orr value, value, bit
- mcr p15, 0, value, c1, c0, 0
- }
-}
-
-rt_inline void cache_disable(rt_uint32_t bit)
-{
- rt_uint32_t value;
-
- __asm
- {
- mrc p15, 0, value, c1, c0, 0
- bic value, value, bit
- mcr p15, 0, value, c1, c0, 0
- }
-}
-#endif
-
-/**
- * enable I-Cache
- *
- */
-void rt_hw_cpu_icache_enable()
-{
- cache_enable(ICACHE_MASK);
-}
-
-/**
- * disable I-Cache
- *
- */
-void rt_hw_cpu_icache_disable()
-{
- cache_disable(ICACHE_MASK);
-}
-
-/**
- * return the status of I-Cache
- *
- */
-rt_base_t rt_hw_cpu_icache_status()
-{
- return (cp15_rd() & ICACHE_MASK);
-}
-
-/**
- * enable D-Cache
- *
- */
-void rt_hw_cpu_dcache_enable()
-{
- cache_enable(DCACHE_MASK);
-}
-
-/**
- * disable D-Cache
- *
- */
-void rt_hw_cpu_dcache_disable()
-{
- cache_disable(DCACHE_MASK);
-}
-
-/**
- * return the status of D-Cache
- *
- */
-rt_base_t rt_hw_cpu_dcache_status()
-{
- return (cp15_rd() & DCACHE_MASK);
-}
-
-/**
- * reset cpu by dog's time-out
- *
- */
-void rt_hw_cpu_reset()
-{
-
- /* enable watchdog */
- *(RP)(RTC_CTR) = 0x02;
-
- /*Enable watchdog reset*/
- *(RP)(RTC_INT_EN) = 0x20;
-
- /* Initialize watchdog timer count register */
- *(RP)(RTC_WD_CNT) = 0x0001;
-
- while(1); /* loop forever and wait for reset to happen */
-
- /* NEVER REACHED */
-}
-
-/**
- * shutdown CPU
- *
- */
-void rt_hw_cpu_shutdown()
-{
- rt_uint32_t UNUSED level;
- rt_kprintf("shutdown...\n");
-
- level = rt_hw_interrupt_disable();
-
- RT_ASSERT(RT_NULL);
-}
-
-/*@}*/
+/* + * File : cpu.c + * This file is part of RT-Thread RTOS + * COPYRIGHT (C) 2006, RT-Thread Develop Team + * + * The license and distribution terms for this file may be + * found in the file LICENSE in this distribution or at + * http://openlab.rt-thread.com/license/LICENSE + * + * Change Logs: + * Date Author Notes + * 2006-03-13 Bernard first version + */ + +#include <rtthread.h> +#include <sep4020.h> + +extern rt_uint32_t rt_hw_interrupt_disable(void); + +//TODO +#warning I DON'T KNOW IF THE MMU OPERATION WORKS ON SEP4020 + +/** + * @addtogroup S3C24X0 + */ +/*@{*/ + +#define ICACHE_MASK (rt_uint32_t)(1 << 12) +#define DCACHE_MASK (rt_uint32_t)(1 << 2) + +#ifdef __GNUC__ +rt_inline rt_uint32_t cp15_rd(void) +{ + rt_uint32_t i; + + asm ("mrc p15, 0, %0, c1, c0, 0":"=r" (i)); + return i; +} + +rt_inline void cache_enable(rt_uint32_t bit) +{ + __asm__ __volatile__( \ + "mrc p15,0,r0,c1,c0,0\n\t" \ + "orr r0,r0,%0\n\t" \ + "mcr p15,0,r0,c1,c0,0" \ + : \ + :"r" (bit) \ + :"memory"); +} + +rt_inline void cache_disable(rt_uint32_t bit) +{ + __asm__ __volatile__( \ + "mrc p15,0,r0,c1,c0,0\n\t" \ + "bic r0,r0,%0\n\t" \ + "mcr p15,0,r0,c1,c0,0" \ + : \ + :"r" (bit) \ + :"memory"); +} +#endif + +#ifdef __CC_ARM +rt_inline rt_uint32_t cp15_rd(void) +{ + rt_uint32_t i; + + __asm + { + mrc p15, 0, i, c1, c0, 0 + } + + return i; +} + +rt_inline void cache_enable(rt_uint32_t bit) +{ + rt_uint32_t value; + + __asm + { + mrc p15, 0, value, c1, c0, 0 + orr value, value, bit + mcr p15, 0, value, c1, c0, 0 + } +} + +rt_inline void cache_disable(rt_uint32_t bit) +{ + rt_uint32_t value; + + __asm + { + mrc p15, 0, value, c1, c0, 0 + bic value, value, bit + mcr p15, 0, value, c1, c0, 0 + } +} +#endif + +/** + * enable I-Cache + * + */ +void rt_hw_cpu_icache_enable() +{ + cache_enable(ICACHE_MASK); +} + +/** + * disable I-Cache + * + */ +void rt_hw_cpu_icache_disable() +{ + cache_disable(ICACHE_MASK); +} + +/** + * return the status of I-Cache + * + */ +rt_base_t rt_hw_cpu_icache_status() +{ + return (cp15_rd() & ICACHE_MASK); +} + +/** + * enable D-Cache + * + */ +void rt_hw_cpu_dcache_enable() +{ + cache_enable(DCACHE_MASK); +} + +/** + * disable D-Cache + * + */ +void rt_hw_cpu_dcache_disable() +{ + cache_disable(DCACHE_MASK); +} + +/** + * return the status of D-Cache + * + */ +rt_base_t rt_hw_cpu_dcache_status() +{ + return (cp15_rd() & DCACHE_MASK); +} + +/** + * reset cpu by dog's time-out + * + */ +void rt_hw_cpu_reset() +{ + + /* enable watchdog */ + *(RP)(RTC_CTR) = 0x02; + + /*Enable watchdog reset*/ + *(RP)(RTC_INT_EN) = 0x20; + + /* Initialize watchdog timer count register */ + *(RP)(RTC_WD_CNT) = 0x0001; + + while(1); /* loop forever and wait for reset to happen */ + + /* NEVER REACHED */ +} + +/** + * shutdown CPU + * + */ +void rt_hw_cpu_shutdown() +{ + rt_uint32_t UNUSED level; + rt_kprintf("shutdown...\n"); + + level = rt_hw_interrupt_disable(); + + RT_ASSERT(RT_NULL); +} + +/*@}*/ diff --git a/libcpu/arm/sep4020/interrupt.c b/libcpu/arm/sep4020/interrupt.c index 7126e5acc2..8ed22dc816 100644 --- a/libcpu/arm/sep4020/interrupt.c +++ b/libcpu/arm/sep4020/interrupt.c @@ -40,30 +40,30 @@ rt_isr_handler_t rt_hw_interrupt_handle(rt_uint32_t vector) */ void rt_hw_interrupt_init() { - register rt_uint32_t idx;
-
- /*Make sure all intc registers in proper state*/
-
- /*mask all the irq*/
- *(RP)(INTC_IMR) = 0xFFFFFFFF;
-
- /*enable all the irq*/
- *(RP)(INTC_IER) = 0XFFFFFFFF;
-
- /*Dont use any forced irq*/
- *(RP)(INTC_IFR) = 0x0;
-
- /*Disable all the fiq*/
- *(RP)(INTC_FIER) = 0x0;
-
- /*Mask all the fiq*/
- *(RP)(INTC_FIMR) = 0x0F;
-
- /*Dont use forced fiq*/
- *(RP)(INTC_FIFR) = 0x0;
-
- /*Intrrupt priority register*/
- *(RP)(INTC_IPLR) = 0x0;
+ register rt_uint32_t idx; + + /*Make sure all intc registers in proper state*/ + + /*mask all the irq*/ + *(RP)(INTC_IMR) = 0xFFFFFFFF; + + /*enable all the irq*/ + *(RP)(INTC_IER) = 0XFFFFFFFF; + + /*Dont use any forced irq*/ + *(RP)(INTC_IFR) = 0x0; + + /*Disable all the fiq*/ + *(RP)(INTC_FIER) = 0x0; + + /*Mask all the fiq*/ + *(RP)(INTC_FIMR) = 0x0F; + + /*Dont use forced fiq*/ + *(RP)(INTC_FIFR) = 0x0; + + /*Intrrupt priority register*/ + *(RP)(INTC_IPLR) = 0x0; /* init exceptions table */ for(idx=0; idx < MAX_HANDLERS; idx++) @@ -92,15 +92,15 @@ void rt_hw_interrupt_mask(rt_uint32_t vector) * @param vector the interrupt number */ void rt_hw_interrupt_umask(rt_uint32_t vector) -{
- if(vector == 16)
- {
- rt_kprintf("Interrupt vec %d is not used!\n", vector);
- }
- else
+{ + if(vector == 16) + { + rt_kprintf("Interrupt vec %d is not used!\n", vector); + } + else *(RP)(INTC_IMR) &= ~(1 << vector); -}
-
+} + /** * This function will install a interrupt service routine to a interrupt. @@ -112,9 +112,9 @@ void rt_hw_interrupt_install(rt_uint32_t vector, rt_isr_handler_t new_handler, r { if(vector < MAX_HANDLERS) { - if (*old_handler != RT_NULL)
+ if (*old_handler != RT_NULL) *old_handler = isr_table[vector]; - if (new_handler != RT_NULL)
+ if (new_handler != RT_NULL) isr_table[vector] = new_handler; } } diff --git a/libcpu/arm/sep4020/sep4020.h b/libcpu/arm/sep4020/sep4020.h index b4590c2ef0..022fddcc19 100644 --- a/libcpu/arm/sep4020/sep4020.h +++ b/libcpu/arm/sep4020/sep4020.h @@ -1,867 +1,867 @@ -#ifndef __SEP4020_H
-#define __SEP4020_H
-
-#include <rtthread.h>
-
-/*Core definations*/
-#define SVCMODE
-#define Mode_USR 0x10
-#define Mode_FIQ 0x11
-#define Mode_IRQ 0x12
-#define Mode_SVC 0x13
-#define Mode_ABT 0x17
-#define Mode_UND 0x1B
-#define Mode_SYS 0x1F
-
-
-
-/*
- * ��ģ��Ĵ�����ֵ
- */
-
-#define ESRAM_BASE 0x04000000
-#define INTC_BASE 0x10000000
-#define PMU_BASE 0x10001000
-#define RTC_BASE 0x10002000
-#define WD_BASE 0x10002000
-#define TIMER_BASE 0x10003000
-#define PWM_BASE 0x10004000
-#define UART0_BASE 0X10005000
-#define UART1_BASE 0X10006000
-#define UART2_BASE 0X10007000
-#define UART3_BASE 0X10008000
-#define SSI_BASE 0X10009000
-#define I2S_BASE 0x1000A000
-#define MMC_BASE 0x1000B000
-#define SD_BASE 0x1000B000
-#define SMC0_BASE 0x1000C000
-#define SMC1_BASE 0x1000D000
-#define USBD_BASE 0x1000E000
-#define GPIO_BASE 0x1000F000
-#define EMI_BASE 0x11000000
-#define DMAC_BASE 0x11001000
-#define LCDC_BASE 0x11002000
-#define MAC_BASE 0x11003000
-#define AMBA_BASE 0x11005000
-
-
-/*
- * INTCģ��
- * ��ַ: 0x10000000
- */
-
-#define INTC_IER (INTC_BASE+0X000) /* IRQ�ж������Ĵ��� */
-#define INTC_IMR (INTC_BASE+0X008) /* IRQ�ж����μĴ��� */
-#define INTC_IFR (INTC_BASE+0X010) /* IRQ����ǿ���жϼĴ��� */
-#define INTC_IRSR (INTC_BASE+0X018) /* IRQδ�����ж�״̬�Ĵ��� */
-#define INTC_ISR (INTC_BASE+0X020) /* IRQ�ж�״̬�Ĵ��� */
-#define INTC_IMSR (INTC_BASE+0X028) /* IRQ�����ж�״̬�Ĵ��� */
-#define INTC_IFSR (INTC_BASE+0X030) /* IRQ�ж�����״̬�Ĵ��� */
-#define INTC_FIER (INTC_BASE+0X0C0) /* FIQ�ж������Ĵ��� */
-#define INTC_FIMR (INTC_BASE+0X0C4) /* FIQ�ж����μĴ��� */
-#define INTC_FIFR (INTC_BASE+0X0C8) /* FIQ����ǿ���жϼĴ��� */
-#define INTC_FIRSR (INTC_BASE+0X0CC) /* FIQδ�����ж�״̬�Ĵ��� */
-#define INTC_FISR (INTC_BASE+0X0D0) /* FIQ�ж�״̬�Ĵ��� */
-#define INTC_FIFSR (INTC_BASE+0X0D4) /* FIQ�ж�����״̬�Ĵ��� */
-#define INTC_IPLR (INTC_BASE+0X0D8) /* IRQ�ж����ȼ��Ĵ��� */
-#define INTC_ICR1 (INTC_BASE+0X0DC) /* IRQ�ڲ��ж����ȼ����ƼĴ���1 */
-#define INTC_ICR2 (INTC_BASE+0X0E0) /* IRQ�ڲ��ж����ȼ����ƼĴ���2 */
-#define INTC_EXICR1 (INTC_BASE+0X0E4) /* IRQ�ⲿ�ж����ȼ����ƼĴ���1 */
-#define INTC_EXICR2 (INTC_BASE+0X0E8) /* IRQ�ⲿ�ж����ȼ����ƼĴ���2 */
-
-
-/*
- * PMUģ��
- * ��ַ: 0x10001000
- */
-
-#define PMU_PLTR (PMU_BASE+0X000) /* PLL���ȶ�����ʱ�� */
-#define PMU_PMCR (PMU_BASE+0X004) /* ϵͳ��ʱ��PLL�Ŀ��ƼĴ��� */
-#define PMU_PUCR (PMU_BASE+0X008) /* USBʱ��PLL�Ŀ��ƼĴ��� */
-#define PMU_PCSR (PMU_BASE+0X00C) /* �ڲ�ģ��ʱ��Դ�����Ŀ��ƼĴ��� */
-#define PMU_PDSLOW (PMU_BASE+0X010) /* SLOW״̬��ʱ�ӵķ�Ƶ���� */
-#define PMU_PMDR (PMU_BASE+0X014) /* оƬ����ģʽ�Ĵ��� */
-#define PMU_RCTR (PMU_BASE+0X018) /* Reset���ƼĴ��� */
-#define PMU_CLRWAKUP (PMU_BASE+0X01C) /* WakeUp����Ĵ��� */
-
-
-/*
- * RTCģ��
- * ��ַ: 0x10002000
- */
-
-#define RTC_STA_YMD (RTC_BASE+0X000) /* ��, ��, �ռ����Ĵ��� */
-#define RTC_STA_HMS (RTC_BASE+0X004) /* Сʱ, ����, ��Ĵ��� */
-#define RTC_ALARM_ALL (RTC_BASE+0X008) /* ��ʱ��, ��, ʱ, �ּĴ��� */
-#define RTC_CTR (RTC_BASE+0X00C) /* ���ƼĴ��� */
-#define RTC_INT_EN (RTC_BASE+0X010) /* �ж�ʹ�ܼĴ��� */
-#define RTC_INT_STS (RTC_BASE+0X014) /* �ж�״̬�Ĵ��� */
-#define RTC_SAMP (RTC_BASE+0X018) /* �������ڼĴ��� */
-#define RTC_WD_CNT (RTC_BASE+0X01C) /* Watch-Dog����ֵ�Ĵ��� */
-#define RTC_WD_SEV (RTC_BASE+0X020) /* Watch-Dog����Ĵ��� */
-#define RTC_CONFIG_CHECK (RTC_BASE+0X024) /* ����ʱ��ȷ�ϼĴ��� (������ʱ��֮ǰ��д0xaaaaaaaa) */
-#define RTC_KEY0 (RTC_BASE+0X02C) /* ��Կ�Ĵ��� */
-
-/*
- * TIMERģ��
- * ��ַ: 0x10003000
- */
-
-#define TIMER_T1LCR (TIMER_BASE+0X000) /* ͨ��1���ؼ����Ĵ��� */
-#define TIMER_T1CCR (TIMER_BASE+0X004) /* ͨ��1��ǰ����ֵ�Ĵ��� */
-#define TIMER_T1CR (TIMER_BASE+0X008) /* ͨ��1���ƼĴ��� */
-#define TIMER_T1ISCR (TIMER_BASE+0X00C) /* ͨ��1�ж�״̬����Ĵ��� */
-#define TIMER_T1IMSR (TIMER_BASE+0X010) /* ͨ��1�ж�����״̬�Ĵ��� */
-#define TIMER_T2LCR (TIMER_BASE+0X020) /* ͨ��2���ؼ����Ĵ��� */
-#define TIMER_T2CCR (TIMER_BASE+0X024) /* ͨ��2��ǰ����ֵ�Ĵ��� */
-#define TIMER_T2CR (TIMER_BASE+0X028) /* ͨ��2���ƼĴ��� */
-#define TIMER_T2ISCR (TIMER_BASE+0X02C) /* ͨ��2�ж�״̬����Ĵ��� */
-#define TIMER_T2IMSR (TIMER_BASE+0X030) /* ͨ��2�ж�����״̬�Ĵ��� */
-#define TIMER_T3LCR (TIMER_BASE+0X040) /* ͨ��3���ؼ����Ĵ��� */
-#define TIMER_T3CCR (TIMER_BASE+0X044) /* ͨ��3��ǰ����ֵ�Ĵ��� */
-#define TIMER_T3CR (TIMER_BASE+0X048) /* ͨ��3���ƼĴ��� */
-#define TIMER_T3ISCR (TIMER_BASE+0X04C) /* ͨ��3�ж�״̬����Ĵ��� */
-#define TIMER_T3IMSR (TIMER_BASE+0X050) /* ͨ��3�ж�����״̬�Ĵ��� */
-#define TIMER_T3CAPR (TIMER_BASE+0X054) /* ͨ��3����Ĵ��� */
-#define TIMER_T4LCR (TIMER_BASE+0X060) /* ͨ��4���ؼ����Ĵ��� */
-#define TIMER_T4CCR (TIMER_BASE+0X064) /* ͨ��4��ǰ����ֵ�Ĵ��� */
-#define TIMER_T4CR (TIMER_BASE+0X068) /* ͨ��4���ƼĴ��� */
-#define TIMER_T4ISCR (TIMER_BASE+0X06C) /* ͨ��4�ж�״̬����Ĵ��� */
-#define TIMER_T4IMSR (TIMER_BASE+0X070) /* ͨ��4�ж�����״̬�Ĵ��� */
-#define TIMER_T4CAPR (TIMER_BASE+0X074) /* ͨ��4����Ĵ��� */
-#define TIMER_T5LCR (TIMER_BASE+0X080) /* ͨ��5���ؼ����Ĵ��� */
-#define TIMER_T5CCR (TIMER_BASE+0X084) /* ͨ��5��ǰ����ֵ�Ĵ��� */
-#define TIMER_T5CR (TIMER_BASE+0X088) /* ͨ��5���ƼĴ��� */
-#define TIMER_T5ISCR (TIMER_BASE+0X08C) /* ͨ��5�ж�״̬����Ĵ��� */
-#define TIMER_T5IMSR (TIMER_BASE+0X090) /* ͨ��5�ж�����״̬�Ĵ��� */
-#define TIMER_T5CAPR (TIMER_BASE+0X094) /* ͨ��5����Ĵ��� */
-#define TIMER_T6LCR (TIMER_BASE+0X0A0) /* ͨ��6���ؼ����Ĵ��� */
-#define TIMER_T6CCR (TIMER_BASE+0X0A4) /* ͨ��6��ǰ����ֵ�Ĵ��� */
-#define TIMER_T6CR (TIMER_BASE+0X0A8) /* ͨ��6���ƼĴ��� */
-#define TIMER_T6ISCR (TIMER_BASE+0X0AC) /* ͨ��6�ж�״̬����Ĵ��� */
-#define TIMER_T6IMSR (TIMER_BASE+0X0B0) /* ͨ��6�ж�����״̬�Ĵ��� */
-#define TIMER_T6CAPR (TIMER_BASE+0X0B4) /* ͨ��6����Ĵ��� */
-#define TIMER_T7LCR (TIMER_BASE+0X0C0) /* ͨ��7���ؼ����Ĵ��� */
-#define TIMER_T7CCR (TIMER_BASE+0X0C4) /* ͨ��7��ǰ����ֵ�Ĵ��� */
-#define TIMER_T7CR (TIMER_BASE+0X0C8) /* ͨ��7���ƼĴ��� */
-#define TIMER_T7ISCR (TIMER_BASE+0X0CC) /* ͨ��7�ж�״̬����Ĵ��� */
-#define TIMER_T7IMSR (TIMER_BASE+0X0D0) /* ͨ��7�ж�����״̬�Ĵ��� */
-#define TIMER_T8LCR (TIMER_BASE+0X0E0) /* ͨ��8���ؼ����Ĵ��� */
-#define TIMER_T8CCR (TIMER_BASE+0X0E4) /* ͨ��8��ǰ����ֵ�Ĵ��� */
-#define TIMER_T8CR (TIMER_BASE+0X0E8) /* ͨ��8���ƼĴ��� */
-#define TIMER_T8ISCR (TIMER_BASE+0X0EC) /* ͨ��8�ж�״̬����Ĵ��� */
-#define TIMER_T8IMSR (TIMER_BASE+0X0F0) /* ͨ��8�ж�����״̬�Ĵ��� */
-#define TIMER_T9LCR (TIMER_BASE+0X100) /* ͨ��9���ؼ����Ĵ��� */
-#define TIMER_T9CCR (TIMER_BASE+0X104) /* ͨ��9��ǰ����ֵ�Ĵ��� */
-#define TIMER_T9CR (TIMER_BASE+0X108) /* ͨ��9���ƼĴ��� */
-#define TIMER_T9ISCR (TIMER_BASE+0X10C) /* ͨ��9�ж�״̬����Ĵ��� */
-#define TIMER_T9IMSR (TIMER_BASE+0X110) /* ͨ��9�ж�����״̬�Ĵ��� */
-#define TIMER_T10LCR (TIMER_BASE+0X120) /* ͨ��10���ؼ����Ĵ��� */
-#define TIMER_T10CCR (TIMER_BASE+0X124) /* ͨ��10��ǰ����ֵ�Ĵ��� */
-#define TIMER_T10CR (TIMER_BASE+0X128) /* ͨ��10���ƼĴ��� */
-#define TIMER_T10ISCR (TIMER_BASE+0X12C) /* ͨ��10�ж�״̬����Ĵ��� */
-#define TIMER_T10IMSR (TIMER_BASE+0X130) /* ͨ��10�ж�����״̬�Ĵ��� */
-#define TIMER_TIMSR (TIMER_BASE+0X140) /* TIMER�ж�����״̬�Ĵ��� */
-#define TIMER_TISCR (TIMER_BASE+0X144) /* TIMER�ж�״̬����Ĵ��� */
-#define TIMER_TISR (TIMER_BASE+0X148) /* TIMER�ж�״̬�Ĵ��� */
-
-
-
-/*
- * PWMģ��
- * ��ַ: 0x10004000
- */
-
-#define PWM0_CTRL (PWM_BASE+0X000) /* PWM0���ƼĴ��� */
-#define PWM0_DIV (PWM_BASE+0X004) /* PWM0��Ƶ�Ĵ��� */
-#define PWM0_PERIOD (PWM_BASE+0X008) /* PWM0���ڼĴ��� */
-#define PWM0_DATA (PWM_BASE+0X00C) /* PWM0���ݼĴ��� */
-#define PWM0_CNT (PWM_BASE+0X010) /* PWM0�����Ĵ��� */
-#define PWM0_STATUS (PWM_BASE+0X014) /* PWM0״̬�Ĵ��� */
-#define PWM1_CTRL (PWM_BASE+0X020) /* PWM1���ƼĴ��� */
-#define PWM1_DIV (PWM_BASE+0X024) /* PWM1��Ƶ�Ĵ��� */
-#define PWM1_PERIOD (PWM_BASE+0X028) /* PWM1���ڼĴ��� */
-#define PWM1_DATA (PWM_BASE+0X02C) /* PWM1���ݼĴ��� */
-#define PWM1_CNT (PWM_BASE+0X030) /* PWM1�����Ĵ��� */
-#define PWM1_STATUS (PWM_BASE+0X034) /* PWM1״̬�Ĵ��� */
-#define PWM2_CTRL (PWM_BASE+0X040) /* PWM2���ƼĴ��� */
-#define PWM2_DIV (PWM_BASE+0X044) /* PWM2��Ƶ�Ĵ��� */
-#define PWM2_PERIOD (PWM_BASE+0X048) /* PWM2���ڼĴ��� */
-#define PWM2_DATA (PWM_BASE+0X04C) /* PWM2���ݼĴ��� */
-#define PWM2_CNT (PWM_BASE+0X050) /* PWM2�����Ĵ��� */
-#define PWM2_STATUS (PWM_BASE+0X054) /* PWM2״̬�Ĵ��� */
-#define PWM3_CTRL (PWM_BASE+0X060) /* PWM3���ƼĴ��� */
-#define PWM3_DIV (PWM_BASE+0X064) /* PWM3��Ƶ�Ĵ��� */
-#define PWM3_PERIOD (PWM_BASE+0X068) /* PWM3���ڼĴ��� */
-#define PWM3_DATA (PWM_BASE+0X06C) /* PWM3���ݼĴ��� */
-#define PWM3_CNT (PWM_BASE+0X070) /* PWM3�����Ĵ��� */
-#define PWM3_STATUS (PWM_BASE+0X074) /* PWM3״̬�Ĵ��� */
-#define PWM_INTMASK (PWM_BASE+0X080) /* PWM�ж����μĴ��� */
-#define PWM_INT (PWM_BASE+0X084) /* PWM�жϼĴ��� */
-#define PWM_ENABLE (PWM_BASE+0X088) /* PWMʹ�ܼĴ��� */
-
-
-/*
- * UART0ģ��
- * ��ַ: 0x10005000
- */
-
-#define UART0_DLBL (UART0_BASE+0X000) /* ���������õͰ�λ�Ĵ��� */
-#define UART0_RXFIFO (UART0_BASE+0X000) /* ����FIFO */
-#define UART0_TXFIFO (UART0_BASE+0X000) /* ����FIFO */
-#define UART0_DLBH (UART0_BASE+0X004) /* ���������ø߰�λ�Ĵ��� */
-#define UART0_IER (UART0_BASE+0X004) /* �ж�ʹ�ܼĴ��� */
-#define UART0_IIR (UART0_BASE+0X008) /* �ж�ʶ��Ĵ��� */
-#define UART0_FCR (UART0_BASE+0X008) /* FIFO���ƼĴ��� */
-#define UART0_LCR (UART0_BASE+0X00C) /* �п��ƼĴ��� */
-#define UART0_MCR (UART0_BASE+0X010) /* Modem���ƼĴ��� */
-#define UART0_LSR (UART0_BASE+0X014) /* ��״̬�Ĵ��� */
-#define UART0_MSR (UART0_BASE+0X018) /* Modem״̬�Ĵ��� */
-
-
-/*
- * UART1ģ��
- * ��ַ: 0x10006000
- */
-
-#define UART1_DLBL (UART1_BASE+0X000) /* ���������õͰ�λ�Ĵ��� */
-#define UART1_RXFIFO (UART1_BASE+0X000) /* ����FIFO */
-#define UART1_TXFIFO (UART1_BASE+0X000) /* ����FIFO */
-#define UART1_DLBH (UART1_BASE+0X004) /* ���������ø߰�λ�Ĵ��� */
-#define UART1_IER (UART1_BASE+0X004) /* �ж�ʹ�ܼĴ��� */
-#define UART1_IIR (UART1_BASE+0X008) /* �ж�ʶ��Ĵ��� */
-#define UART1_FCR (UART1_BASE+0X008) /* FIFO���ƼĴ��� */
-#define UART1_LCR (UART1_BASE+0X00C) /* �п��ƼĴ��� */
-#define UART1_MCR (UART1_BASE+0X010) /* Modem���ƼĴ��� */
-#define UART1_LSR (UART1_BASE+0X014) /* ��״̬�Ĵ��� */
-#define UART1_MSR (UART1_BASE+0X018) /* Modem״̬�Ĵ��� */
-
-
-/*
- * UART2ģ��
- * ��ַ: 0x10007000
- */
-
-#define UART2_DLBL (UART2_BASE+0X000) /* ���������õͰ�λ�Ĵ��� */
-#define UART2_RXFIFO (UART2_BASE+0X000) /* ����FIFO */
-#define UART2_TXFIFO (UART2_BASE+0X000) /* ����FIFO */
-#define UART2_DLBH (UART2_BASE+0X004) /* ���������ø߰�λ�Ĵ��� */
-#define UART2_IER (UART2_BASE+0X004) /* �ж�ʹ�ܼĴ��� */
-#define UART2_IIR (UART2_BASE+0X008) /* �ж�ʶ��Ĵ��� */
-#define UART2_FCR (UART2_BASE+0X008) /* FIFO���ƼĴ��� */
-#define UART2_LCR (UART2_BASE+0X00C) /* �п��ƼĴ��� */
-#define UART2_MCR (UART2_BASE+0X010) /* Modem���ƼĴ��� */
-#define UART2_LSR (UART2_BASE+0X014) /* ��״̬�Ĵ��� */
-#define UART2_MSR (UART2_BASE+0X018) /* Modem״̬�Ĵ��� */
-
-
-/*
- * UART3ģ��
- * ��ַ: 0x10008000
- */
-
-#define UART3_DLBL (UART3_BASE+0X000) /* ���������õͰ�λ�Ĵ��� */
-#define UART3_RXFIFO (UART3_BASE+0X000) /* ����FIFO */
-#define UART3_TXFIFO (UART3_BASE+0X000) /* ����FIFO */
-#define UART3_DLBH (UART3_BASE+0X004) /* ���������ø߰�λ�Ĵ��� */
-#define UART3_IER (UART3_BASE+0X004) /* �ж�ʹ�ܼĴ��� */
-#define UART3_IIR (UART3_BASE+0X008) /* �ж�ʶ��Ĵ��� */
-#define UART3_FCR (UART3_BASE+0X008) /* FIFO���ƼĴ��� */
-#define UART3_LCR (UART3_BASE+0X00C) /* �п��ƼĴ��� */
-#define UART3_MCR (UART3_BASE+0X010) /* Modem���ƼĴ��� */
-#define UART3_LSR (UART3_BASE+0X014) /* ��״̬�Ĵ��� */
-#define UART3_MSR (UART3_BASE+0X018) /* Modem״̬�Ĵ��� */
-
-
-/*
- * SSIģ��
- * ��ַ: 0x10009000
- */
-
-#define SSI_CONTROL0 (SSI_BASE+0X000) /* ���ƼĴ���0 */
-#define SSI_CONTROL1 (SSI_BASE+0X004) /* ���ƼĴ���1 */
-#define SSI_SSIENR (SSI_BASE+0X008) /* SSIʹ�ܼĴ��� */
-#define SSI_MWCR (SSI_BASE+0X00C) /* Microwire���ƼĴ��� */
-#define SSI_SER (SSI_BASE+0X010) /* ���豸ʹ�ܼĴ��� */
-#define SSI_BAUDR (SSI_BASE+0X014) /* ���������üĴ��� */
-#define SSI_TXFTLR (SSI_BASE+0X018) /* ����FIFO��ֵ�Ĵ��� */
-#define SSI_RXFTLR (SSI_BASE+0X01C) /* ����FIFO��ֵ�Ĵ��� */
-#define SSI_TXFLR (SSI_BASE+0X020) /* ����FIFO״̬�Ĵ��� */
-#define SSI_RXFLR (SSI_BASE+0X024) /* ����FIFO״̬�Ĵ��� */
-#define SSI_SR (SSI_BASE+0X028) /* ״̬�Ĵ��� */
-#define SSI_IMR (SSI_BASE+0X02C) /* �ж����μĴ��� */
-#define SSI_ISR (SSI_BASE+0X030) /* �ж�����״̬�Ĵ��� */
-#define SSI_RISR (SSI_BASE+0X034) /* �ж�Ôʼ״̬�Ĵ��� */
-#define SSI_TXOICR (SSI_BASE+0X038) /* ����FIFO�����ж�����Ĵ��� */
-#define SSI_RXOICR (SSI_BASE+0X03C) /* ����FIFO�����ж�����Ĵ��� */
-#define SSI_RXUICR (SSI_BASE+0X040) /* ����FIFO�����ж�����Ĵ��� */
-#define SSI_ICR (SSI_BASE+0X02C) /* �ж�����Ĵ��� */
-#define SSI_DMACR (SSI_BASE+0X04C) /* DMA���ƼĴ��� */
-#define SSI_DMATDLR (SSI_BASE+0X050) /* DMA����״̬�Ĵ��� */
-#define SSI_DMARDLR (SSI_BASE+0X054) /* DMA����״̬�Ĵ��� */
-#define SSI_DR (SSI_BASE+0X060) /* ���ݼĴ��� */
-
-
-/*
- * I2Sģ��
- * ��ַ: 0x1000A000
- */
-
-#define I2S_CTRL (I2S_BASE+0X000) /* I2S���ƼĴ��� */
-#define I2S_DATA (I2S_BASE+0X004) /* I2S���ݼĴ��� */
-#define I2S_INT (I2S_BASE+0X008) /* I2S�жϼĴ��� */
-#define I2S_STATUS (I2S_BASE+0X00C) /* I2S״̬�Ĵ��� */
-
-
-/*
- * SDģ��
- * ��ַ: 0x1000B000
- */
-
-#define SDC_CLOCK_CONTROL (SD_BASE+0x00) /* SDIOʱ�ӿ��ƼĴ��� */
-#define SDC_SOFTWARE_RESET (SD_BASE+0X04) /* SDIO������λ�Ĵ��� */
-#define SDC_ARGUMENT (SD_BASE+0X08) /* SDIO��������Ĵ��� */
-#define SDC_COMMAND (SD_BASE+0X0C) /* SDIO������ƼĴ��� */
-#define SDC_BLOCK_SIZE (SD_BASE+0X10) /* SDIO���ݿ鳤�ȼĴ��� */
-#define SDC_BLOCK_COUNT (SD_BASE+0X14) /* SDIO���ݿ���Ŀ�Ĵ��� */
-#define SDC_TRANSFER_MODE (SD_BASE+0X18) /* SDIO����ģʽѡ��Ĵ��� */
-#define SDC_RESPONSE0 (SD_BASE+0X1c) /* SDIO��Ӧ�Ĵ���0 */
-#define SDC_RESPONSE1 (SD_BASE+0X20) /* SDIO��Ӧ�Ĵ���1 */
-#define SDC_RESPONSE2 (SD_BASE+0X24) /* SDIO��Ӧ�Ĵ���2 */
-#define SDC_RESPONSE3 (SD_BASE+0X28) /* SDIO��Ӧ�Ĵ���3 */
-#define SDC_READ_TIMEOUT_CONTROL (SD_BASE+0X2c) /* SDIO����ʱ���ƼĴ��� */
-#define SDC_INTERRUPT_STATUS (SD_BASE+0X30) /* SDIO�ж�״̬�Ĵ��� */
-#define SDC_INTERRUPT_STATUS_MASK (SD_BASE+0X34) /* SDIO�ж�״̬���μĴ��� */
-#define SDC_READ_BUFER_ACCESS (SD_BASE+0X38) /* SDIO����FIFO */
-#define SDC_WRITE_BUFER_ACCESS (SD_BASE+0X3c) /* SDIO����FIFO */
-
-
-
-/*
- * SMC0ģ��
- * ��ַ: 0x1000C000
- */
-
-#define SMC0_CTRL (SMC0_BASE+0X000) /* SMC0���ƼĴ��� */
-#define SMC0_INT (SMC0_BASE+0X004) /* SMC0�жϼĴ��� */
-#define SMC0_FD (SMC0_BASE+0X008) /* SMC0������Ԫʱ��Ĵ��� */
-#define SMC0_CT (SMC0_BASE+0X00C) /* SMC0�ַ�����ʱ��Ĵ��� */
-#define SMC0_BT (SMC0_BASE+0X010) /* SMC0�鴫��ʱ��Ĵ��� */
-
-
-
-/*
- * SMC1ģ��
- * ��ַ: 0x1000D000
- */
-
-#define SMC1_CTRL (SMC1_BASE+0X000) /* SMC1���ƼĴ��� */
-#define SMC1_INT (SMC1_BASE+0X004) /* SMC1�жϼĴ��� */
-#define SMC1_FD (SMC1_BASE+0X008) /* SMC1������Ԫʱ��Ĵ��� */
-#define SMC1_CT (SMC1_BASE+0X00C) /* SMC1�ַ�����ʱ��Ĵ��� */
-#define SMC1_BT (SMC1_BASE+0X010) /* SMC1�鴫��ʱ��Ĵ��� */
-
-
-
-/*
- * USBDģ��
- * ��ַ: 0x1000E000
- */
-
-#define USBD_PROTOCOLINTR (USBD_BASE+0X000) /* USBÐ���жϼĴ��� */
-#define USBD_INTRMASK (USBD_BASE+0X004) /* USB�ж����μĴ��� */
-#define USBD_INTRCTRL (USBD_BASE+0X008) /* USB�ж����Ϳ��ƼĴ��� */
-#define USBD_EPINFO (USBD_BASE+0X00C) /* USB��˵�״̬�Ĵ��� */
-#define USBD_BCONFIGURATIONVALUE (USBD_BASE+0X010) /* SET_CCONFIGURATION��¼ */
-#define USBD_BMATTRIBUTES (USBD_BASE+0X014) /* ��ǰ�������ԼĴ��� */
-#define USBD_DEVSPEED (USBD_BASE+0X018) /* ��ǰ�豸�����ٶȼĴ��� */
-#define USBD_FRAMENUMBER (USBD_BASE+0X01C) /* ��¼��ǰSOF���ڵ�֡�� */
-#define USBD_EPTRANSACTIONS0 (USBD_BASE+0X020) /* ��¼�´�Ҫ��Ĵ������ */
-#define USBD_EPTRANSACTIONS1 (USBD_BASE+0X024) /* ��¼�´�Ҫ��Ĵ������ */
-#define USBD_APPIFUPDATE (USBD_BASE+0X028) /* �ӿںſ��ٸ��¼Ĵ��� */
-#define USBD_CFGINTERFACE0 (USBD_BASE+0X02C) /* ��¼�ӿڵ�ֵ */
-#define USBD_CFGINTERFACE1 (USBD_BASE+0X030) /* ��¼�ӿڵ�ֵ */
-#define USBD_CFGINTERFACE2 (USBD_BASE+0X034) /* ��¼�ӿڵ�ֵ */
-#define USBD_CFGINTERFACE3 (USBD_BASE+0X038) /* ��¼�ӿڵ�ֵ */
-#define USBD_CFGINTERFACE4 (USBD_BASE+0X03C) /* ��¼�ӿڵ�ֵ */
-#define USBD_CFGINTERFACE5 (USBD_BASE+0X040) /* ��¼�ӿڵ�ֵ */
-#define USBD_CFGINTERFACE6 (USBD_BASE+0X044) /* ��¼�ӿڵ�ֵ */
-#define USBD_CFGINTERFACE7 (USBD_BASE+0X048) /* ��¼�ӿڵ�ֵ */
-#define USBD_CFGINTERFACE8 (USBD_BASE+0X04C) /* ��¼�ӿڵ�ֵ */
-#define USBD_CFGINTERFACE9 (USBD_BASE+0X050) /* ��¼�ӿڵ�ֵ */
-#define USBD_CFGINTERFACE10 (USBD_BASE+0X054) /* ��¼�ӿڵ�ֵ */
-#define USBD_CFGINTERFACE11 (USBD_BASE+0X058) /* ��¼�ӿڵ�ֵ */
-#define USBD_CFGINTERFACE12 (USBD_BASE+0X05C) /* ��¼�ӿڵ�ֵ */
-#define USBD_CFGINTERFACE13 (USBD_BASE+0X060) /* ��¼�ӿڵ�ֵ */
-#define USBD_CFGINTERFACE14 (USBD_BASE+0X064) /* ��¼�ӿڵ�ֵ */
-#define USBD_CFGINTERFACE15 (USBD_BASE+0X068) /* ��¼�ӿڵ�ֵ */
-#define USBD_CFGINTERFACE16 (USBD_BASE+0X06C) /* ��¼�ӿڵ�ֵ */
-#define USBD_CFGINTERFACE17 (USBD_BASE+0X070) /* ��¼�ӿڵ�ֵ */
-#define USBD_CFGINTERFACE18 (USBD_BASE+0X074) /* ��¼�ӿڵ�ֵ */
-#define USBD_CFGINTERFACE19 (USBD_BASE+0X078) /* ��¼�ӿڵ�ֵ */
-#define USBD_CFGINTERFACE20 (USBD_BASE+0X07C) /* ��¼�ӿڵ�ֵ */
-#define USBD_CFGINTERFACE21 (USBD_BASE+0X080) /* ��¼�ӿڵ�ֵ */
-#define USBD_CFGINTERFACE22 (USBD_BASE+0X084) /* ��¼�ӿڵ�ֵ */
-#define USBD_CFGINTERFACE23 (USBD_BASE+0X088) /* ��¼�ӿڵ�ֵ */
-#define USBD_CFGINTERFACE24 (USBD_BASE+0X08C) /* ��¼�ӿڵ�ֵ */
-#define USBD_CFGINTERFACE25 (USBD_BASE+0X090) /* ��¼�ӿڵ�ֵ */
-#define USBD_CFGINTERFACE26 (USBD_BASE+0X094) /* ��¼�ӿڵ�ֵ */
-#define USBD_CFGINTERFACE27 (USBD_BASE+0X098) /* ��¼�ӿڵ�ֵ */
-#define USBD_CFGINTERFACE28 (USBD_BASE+0X09C) /* ��¼�ӿڵ�ֵ */
-#define USBD_CFGINTERFACE29 (USBD_BASE+0X0A0) /* ��¼�ӿڵ�ֵ */
-#define USBD_CFGINTERFACE30 (USBD_BASE+0X0A4) /* ��¼�ӿڵ�ֵ */
-#define USBD_CFGINTERFACE31 (USBD_BASE+0X0A8) /* ��¼�ӿڵ�ֵ */
-#define USBD_PKTPASSEDCTRL (USBD_BASE+0X0AC) /* ��¼�ɹ����յİ��� */
-#define USBD_PKTDROPPEDCTRL (USBD_BASE+0X0B0) /* ��¼��ʧ�İ��� */
-#define USBD_CRCERRCTRL (USBD_BASE+0X0B4) /* ��¼CRC����İ��� */
-#define USBD_BITSTUFFERRCTRL (USBD_BASE+0X0B8) /* ��¼λ������İ��� */
-#define USBD_PIDERRCTRL (USBD_BASE+0X0BC) /* ��¼PID����İ��� */
-#define USBD_FRAMINGERRCTL (USBD_BASE+0X0C0) /* ��¼��SYNC��EOP�İ��� */
-#define USBD_TXPKTCTRL (USBD_BASE+0X0C4) /* ��¼���Ͱ������� */
-#define USBD_STATCTRLOV (USBD_BASE+0X0C8) /* ��¼ͳ�ƼĴ��������� */
-#define USBD_TXLENGTH (USBD_BASE+0X0CC) /* ��¼ÿ��IN������������� */
-#define USBD_RXLENGTH (USBD_BASE+0X0D0) /* ��¼OUT������������� */
-#define USBD_RESUME (USBD_BASE+0X0D4) /* USB���ѼĴ��� */
-#define USBD_READFLAG (USBD_BASE+0X0D8) /* ���첽״̬�Ĵ�����־ */
-#define USBD_RECEIVETYPE (USBD_BASE+0X0DC) /* ����״̬�Ĵ��� */
-#define USBD_APPLOCK (USBD_BASE+0X0E0) /* ���źżĴ��� */
-#define USBD_EP0OUTADDR (USBD_BASE+0X100) /* �˵�0�˵�źͷ��� */
-#define USBD_EP0OUTBMATTR (USBD_BASE+0X104) /* �˵�0���ͼĴ��� */
-#define USBD_EP0OUTMAXPKTSIZE (USBD_BASE+0X108) /* �˵�0�����ߴ�Ĵ��� */
-#define USBD_EP0OUTIFNUM (USBD_BASE+0X10C) /* �˵�0�ӿںżĴ��� */
-#define USBD_EP0OUTSTAT (USBD_BASE+0X110) /* �˵�0״̬�Ĵ��� */
-#define USBD_EP0OUTBMREQTYPE (USBD_BASE+0X114) /* �˵�0 SETUP���������� */
-#define USBD_EP0OUTBREQUEST (USBD_BASE+0X118) /* �˵�0 SETUP������������ */
-#define USBD_EP0OUTWVALUE (USBD_BASE+0X11C) /* �˵�0 SETUP��������ֵ */
-#define USBD_EP0OUTWINDEX (USBD_BASE+0X120) /* �˵�0 SETUP������������ */
-#define USBD_EP0OUTWLENGTH (USBD_BASE+0X120) /* �˵�0 SETUP�������󳤶� */
-#define USBD_EP0OUTSYNCHFRAME (USBD_BASE+0X128) /* �˵�0ͬ����֡�� */
-#define USBD_EP1OUTADDR (USBD_BASE+0X12C) /* �˵�1����˵�źͷ��� */
-#define USBD_EP1OUTBMATTR (USBD_BASE+0X130) /* �˵�1������ͼĴ��� */
-#define USBD_EP1OUTMAXPKTSIZE (USBD_BASE+0X134) /* �˵�1��������ߴ�Ĵ��� */
-#define USBD_EP1OUTIFNUM (USBD_BASE+0X138) /* �˵�1����ӿںżĴ��� */
-#define USBD_EP1OUTSTAT (USBD_BASE+0X13C) /* �˵�1���״̬�Ĵ��� */
-#define USBD_EP1OUTBMREQTYPE (USBD_BASE+0X140) /* �˵�1���SETUP������������ */
-#define USBD_EP1OUTBREQUEST (USBD_BASE+0X144) /* �˵�1���SETUP������������ */
-#define USBD_EP1OUTWVALUE (USBD_BASE+0X148) /* �˵�1���SETUP��������ֵ */
-#define USBD_EP1OUTWINDX (USBD_BASE+0X14C) /* �˵�1���SETUP������������ */
-#define USBD_EP1OUTWLENGH (USBD_BASE+0X150) /* �˵�1���SETUP���������򳤶� */
-#define USBD_EP1OUTSYNCHFRAME (USBD_BASE+0X154) /* �˵�1���ͬ����֡�� */
-#define USBD_EP1INADDR (USBD_BASE+0X158) /* �˵�1����˵�źͷ��� */
-#define USBD_EP1INBMATTR (USBD_BASE+0X15C) /* �˵�1�������ͼĴ��� */
-#define USBD_EP1INMAXPKTSIZE (USBD_BASE+0X160) /* �˵�1���������ߴ�Ĵ��� */
-#define USBD_EP1INIFNUM (USBD_BASE+0X164) /* �˵�1����ӿںżĴ��� */
-#define USBD_EP1INSTAT (USBD_BASE+0X168) /* �˵�1����״̬�Ĵ��� */
-#define USBD_EP1INBMREQTYPE (USBD_BASE+0X16C) /* �˵�1����SETUP������������ */
-#define USBD_EP1INBREQUEST (USBD_BASE+0X170) /* �˵�1����SETUP������������ */
-#define USBD_EP1INWVALUE (USBD_BASE+0X174) /* �˵�1����SETUP��������ֵ */
-#define USBD_EP1INWINDEX (USBD_BASE+0X178) /* �˵�1����SETUP������������ */
-#define USBD_EP1INWLENGTH (USBD_BASE+0X17C) /* �˵�1����SETUP���������򳤶� */
-#define USBD_EP1INSYNCHFRAME (USBD_BASE+0X180) /* �˵�1����ͬ����֡�� */
-#define USBD_EP2OUTADDR (USBD_BASE+0X184) /* �˵�2����˵�źͷ��� */
-#define USBD_EP2OUTBMATTR (USBD_BASE+0X188) /* �˵�2������ͼĴ��� */
-#define USBD_EP2OUTMAXPKTSIZE (USBD_BASE+0X18C) /* �˵�2��������ߴ�Ĵ��� */
-#define USBD_EP2OUTIFNUM (USBD_BASE+0X190) /* �˵�2����ӿںżĴ��� */
-#define USBD_EP2OUTSTAT (USBD_BASE+0X194) /* �˵�2���״̬�Ĵ��� */
-#define USBD_EP2OUTBMREQTYPE (USBD_BASE+0X198) /* �˵�2���SETUP������������ */
-#define USBD_EP2OUTBREQUEST (USBD_BASE+0X19C) /* �˵�2���SETUP������������ */
-#define USBD_EP2OUTWVALUE (USBD_BASE+0X1A0) /* �˵�2���SETUP��������ֵ */
-#define USBD_EP2OUTWINDEX (USBD_BASE+0X1A4) /* �˵�2���SETUP������������ */
-#define USBD_EP2OUTWLENGTH (USBD_BASE+0X1A8) /* �˵�2���SETUP���������򳤶� */
-#define USBD_EP2OUTSYNCHFRAME (USBD_BASE+0X1AC) /* �˵�2���ͬ����֡�� */
-#define USBD_EP2INADDR (USBD_BASE+0X1B0) /* �˵�2����˵�źͷ��� */
-#define USBD_EP2INBMATTR (USBD_BASE+0X1B4) /* �˵�2�������ͼĴ��� */
-#define USBD_EP2INMAXPKTSIZE (USBD_BASE+0X1B8) /* �˵�2���������ߴ�Ĵ��� */
-#define USBD_EP2INIFNUM (USBD_BASE+0X1BC) /* �˵�2����ӿںżĴ��� */
-#define USBD_EP2INSTAT (USBD_BASE+0X1C0) /* �˵�2����״̬�Ĵ��� */
-#define USBD_EP2INBMREQTYPE (USBD_BASE+0X1C4) /* �˵�2����SETUP������������ */
-#define USBD_EP2INBREQUEST (USBD_BASE+0X1C8) /* �˵�2����SETUP������������ */
-#define USBD_EP2INWVALUE (USBD_BASE+0X1CC) /* �˵�2����SETUP��������ֵ */
-#define USBD_EP2INWINDEX (USBD_BASE+0X1D0) /* �˵�2����SETUP������������ */
-#define USBD_EP2INWLENGTH (USBD_BASE+0X1D4) /* �˵�2����SETUP���������򳤶� */
-#define USBD_EP2INSYNCHFRAME (USBD_BASE+0X1D8) /* �˵�2����ͬ����֡�� */
-#define USBD_RXFIFO (USBD_BASE+0X200) /* ����FIFO */
-#define USBD_TXFIFO (USBD_BASE+0X300) /* ����FIFO */
-
-
-/*
- * GPIOģ��
- * ��ַ: 0x1000F000
- */
-
-#define GPIO_DBCLK_DIV (GPIO_BASE+0X000) /* ȥë�̲���ʱ�ӷ�Ƶ�����üĴ��� */
-#define GPIO_PORTA_DIR (GPIO_BASE+0X004) /* A��˿���������������üĴ��� */
-#define GPIO_PORTA_SEL (GPIO_BASE+0X008) /* A��˿�ͨ����;ѡ�����üĴ��� */
-#define GPIO_PORTA_INCTL (GPIO_BASE+0X00C) /* A��˿�ͨ����;����ʱ�������üĴ��� */
-#define GPIO_PORTA_INTRCTL (GPIO_BASE+0X010) /* A��˿��жϴ����������üĴ��� */
-#define GPIO_PORTA_INTRCLR (GPIO_BASE+0X014) /* A��˿�ͨ����;�ж�������üĴ��� */
-#define GPIO_PORTA_DATA (GPIO_BASE+0X018) /* A��˿�ͨ����;�������üĴ��� */
-#define GPIO_PORTB_DIR (GPIO_BASE+0X01C) /* B��˿���������������üĴ��� */
-#define GPIO_PORTB_SEL (GPIO_BASE+0X020) /* B��˿�ͨ����;ѡ�����üĴ��� */
-#define GPIO_PORTB_DATA (GPIO_BASE+0X024) /* B��˿�ͨ����;�������üĴ��� */
-#define GPIO_PORTC_DIR (GPIO_BASE+0X028) /* C��˿���������������üĴ��� */
-#define GPIO_PORTC_SEL (GPIO_BASE+0X02C) /* C��˿�ͨ����;ѡ�����üĴ��� */
-#define GPIO_PORTC_DATA (GPIO_BASE+0X030) /* C��˿�ͨ����;�������üĴ��� */
-#define GPIO_PORTD_DIR (GPIO_BASE+0X034) /* D��˿���������������üĴ��� */
-#define GPIO_PORTD_SEL (GPIO_BASE+0X038) /* D��˿�ͨ����;ѡ�����üĴ��� */
-#define GPIO_PORTD_SPECII (GPIO_BASE+0X03C) /* D��˿�ר����;2ѡ�����üĴ��� */
-#define GPIO_PORTD_DATA (GPIO_BASE+0X040) /* D��˿�ͨ����;�������üĴ��� */
-#define GPIO_PORTE_DIR (GPIO_BASE+0X044) /* E��˿���������������üĴ��� */
-#define GPIO_PORTE_SEL (GPIO_BASE+0X048) /* E��˿�ͨ����;ѡ�����üĴ��� */
-#define GPIO_PORTE_DATA (GPIO_BASE+0X04C) /* E��˿�ͨ����;�������üĴ��� */
-#define GPIO_PORTF_DIR (GPIO_BASE+0X050) /* F��˿���������������üĴ��� */
-#define GPIO_PORTF_SEL (GPIO_BASE+0X054) /* F��˿�ͨ����;ѡ�����üĴ��� */
-#define GPIO_PORTF_INCTL (GPIO_BASE+0X058) /* F��˿�ͨ����;����ʱ�������üĴ��� */
-#define GPIO_PORTF_INTRCTL (GPIO_BASE+0X05C) /* F��˿��жϴ����������üĴ��� */
-#define GPIO_PORTF_INTRCLR (GPIO_BASE+0X060) /* F��˿�ͨ����;�ж�������üĴ��� */
-#define GPIO_PORTF_DATA (GPIO_BASE+0X064) /* F��˿�ͨ����;�������üĴ��� */
-#define GPIO_PORTG_DIR (GPIO_BASE+0X068) /* G��˿���������������üĴ��� */
-#define GPIO_PORTG_SEL (GPIO_BASE+0X06C) /* G��˿�ͨ����;ѡ�����üĴ��� */
-#define GPIO_PORTG_DATA (GPIO_BASE+0X070) /* G��˿�ͨ����;�������üĴ��� */
-#define GPIO_PORTH_DIR (GPIO_BASE+0X07C) /* H��˿���������������üĴ��� */
-#define GPIO_PORTH_SEL (GPIO_BASE+0X078) /* H��˿�ͨ����;ѡ�����üĴ��� */
-#define GPIO_PORTH_DATA (GPIO_BASE+0X07C) /* H��˿�ͨ����;�������üĴ��� */
-#define GPIO_PORTI_DIR (GPIO_BASE+0X080) /* I��˿���������������üĴ��� */
-#define GPIO_PORTI_SEL (GPIO_BASE+0X084) /* I��˿�ͨ����;ѡ�����üĴ��� */
-#define GPIO_PORTI_DATA (GPIO_BASE+0X088) /* I��˿�ͨ����;�������üĴ��� */
-
-
-
-/*
- * EMIģ��
- * ��ַ: 0x11000000
- */
-
-#define EMI_CSACONF (EMI_BASE+0X000) /* CSA�������üĴ��� */
-#define EMI_CSBCONF (EMI_BASE+0X004) /* CSB�������üĴ��� */
-#define EMI_CSCCONF (EMI_BASE+0X008) /* CSC�������üĴ��� */
-#define EMI_CSDCONF (EMI_BASE+0X00C) /* CSD�������üĴ��� */
-#define EMI_CSECONF (EMI_BASE+0X010) /* CSE�������üĴ��� */
-#define EMI_CSFCONF (EMI_BASE+0X014) /* CSF�������üĴ��� */
-#define EMI_SDCONF1 (EMI_BASE+0X018) /* SDRAMʱ�����üĴ���1 */
-#define EMI_SDCONF2 (EMI_BASE+0X01C) /* SDRAMʱ�����üĴ���2, SDRAM��ʼ���õ���������Ϣ */
-#define EMI_REMAPCONF (EMI_BASE+0X020) /* Ƭѡ�ռ估��ַӳ��REMAP���üĴ��� */
-#define EMI_NAND_ADDR1 (EMI_BASE+0X100) /* NAND FLASH�ĵ�ַ�Ĵ���1 */
-#define EMI_NAND_COM (EMI_BASE+0X104) /* NAND FLASH�Ŀ����ּĴ��� */
-#define EMI_NAND_STA (EMI_BASE+0X10C) /* NAND FLASH��״̬�Ĵ��� */
-#define EMI_ERR_ADDR1 (EMI_BASE+0X110) /* �����������ĵ�ַ�Ĵ���1 */
-#define EMI_ERR_ADDR2 (EMI_BASE+0X114) /* �����������ĵ�ַ�Ĵ���2 */
-#define EMI_NAND_CONF1 (EMI_BASE+0X118) /* NAND FLASH������������1 */
-#define EMI_NAND_INTR (EMI_BASE+0X11C) /* NAND FLASH�жϼĴ��� */
-#define EMI_NAND_ECC (EMI_BASE+0X120) /* ECCУ����ɼĴ��� */
-#define EMI_NAND_IDLE (EMI_BASE+0X124) /* NAND FLASH���мĴ��� */
-#define EMI_NAND_CONF2 (EMI_BASE+0X128) /* NAND FLASH������������2 */
-#define EMI_NAND_ADDR2 (EMI_BASE+0X12C) /* NAND FLASH�ĵ�ַ�Ĵ���2 */
-#define EMI_NAND_DATA (EMI_BASE+0X200) /* NAND FLASH�����ݼĴ��� */
-
-
-/*
- * DMACģ��
- * ��ַ: 0x11001000
- */
-
-#define DMAC_INTSTATUS (DMAC_BASE+0X020) /* DAMC�ж�״̬�Ĵ����� */
-#define DMAC_INTTCSTATUS (DMAC_BASE+0X050) /* DMAC��������ж�״̬�Ĵ��� */
-#define DMAC_INTTCCLEAR (DMAC_BASE+0X060) /* DMAC��������ж�״̬����Ĵ��� */
-#define DMAC_INTERRORSTATUS (DMAC_BASE+0X080) /* DMAC��������ж�״̬�Ĵ��� */
-#define DMAC_INTINTERRCLR (DMAC_BASE+0X090) /* DMAC��������ж�״̬����Ĵ��� */
-#define DMAC_ENBLDCHNS (DMAC_BASE+0X0B0) /* DMACͨ��ʹ��״̬�Ĵ��� */
-#define DMAC_C0SRCADDR (DMAC_BASE+0X000) /* DMAC��0Դ��ַ�Ĵ��� */
-#define DMAC_C0DESTADD (DMAC_BASE+0X004) /* DMAC��0Ŀ�ĵ�ַ�Ĵ��� */
-#define DMAC_C0CONTROL (DMAC_BASE+0X00C) /* DMAC��0���ƼĴ��� */
-#define DMAC_C0CONFIGURATION (DMAC_BASE+0X010) /* DMAC��0���üĴ��� */
-#define DMAC_C0DESCRIPTOR (DMAC_BASE+0X01C) /* DMAC��0������ַ�Ĵ��� */
-#define DMAC_C1SRCADDR (DMAC_BASE+0X100) /* DMAC��1Դ��ַ�Ĵ��� */
-#define DMAC_C1DESTADDR (DMAC_BASE+0X104) /* DMAC��1Ŀ�ĵ�ַ�Ĵ��� */
-#define DMAC_C1CONTROL (DMAC_BASE+0X10C) /* DMAC��1���ƼĴ��� */
-#define DMAC_C1CONFIGURATION (DMAC_BASE+0X110) /* DMAC��1���üĴ��� */
-#define DMAC_C1DESCRIPTOR (DMAC_BASE+0X114) /* DMAC��1������ַ�Ĵ��� */
-#define DMAC_C2SRCADDR (DMAC_BASE+0X200) /* DMAC��2Դ��ַ�Ĵ��� */
-#define DMAC_C2DESTADDR (DMAC_BASE+0X204) /* DMAC��2Ŀ�ĵ�ַ�Ĵ��� */
-#define DMAC_C2CONTROL (DMAC_BASE+0X20C) /* DMAC��2���ƼĴ��� */
-#define DMAC_C2CONFIGURATION (DMAC_BASE+0X210) /* DMAC��2���üĴ��� */
-#define DMAC_C2DESCRIPTOR (DMAC_BASE+0X214) /* DMAC��2������ַ�Ĵ��� */
-#define DMAC_C3SRCADDR (DMAC_BASE+0X300) /* DMAC��3Դ��ַ�Ĵ��� */
-#define DMAC_C3DESTADDR (DMAC_BASE+0X304) /* DMAC��3Ŀ�ĵ�ַ�Ĵ��� */
-#define DMAC_C3CONTROL (DMAC_BASE+0X30C) /* DMAC��3���ƼĴ��� */
-#define DMAC_C3CONFIGURATION (DMAC_BASE+0X310) /* DMAC��3���üĴ��� */
-#define DMAC_C3DESCRIPTOR (DMAC_BASE+0X314) /* DMAC��3������ַ�Ĵ��� */
-#define DMAC_C4SRCADDR (DMAC_BASE+0X400) /* DMAC��4Դ��ַ�Ĵ��� */
-#define DMAC_C4DESTADDR (DMAC_BASE+0X404) /* DMAC��4Ŀ�ĵ�ַ�Ĵ��� */
-#define DMAC_C4CONTROL (DMAC_BASE+0X40C) /* DMAC��4���ƼĴ��� */
-#define DMAC_C4CONFIGURATION (DMAC_BASE+0X410) /* DMAC��4���üĴ��� */
-#define DMAC_C4DESCRIPTOR (DMAC_BASE+0X414) /* DMAC��4������ַ�Ĵ��� */
-#define DMAC_C5SRCADDR (DMAC_BASE+0X500) /* DMAC��5Դ��ַ�Ĵ��� */
-#define DMAC_C5DESTADDR (DMAC_BASE+0X504) /* DMAC��5Ŀ�ĵ�ַ�Ĵ��� */
-#define DMAC_C5CONTROL (DMAC_BASE+0X50C) /* DMAC��5���ƼĴ��� */
-#define DMAC_C5CONFIGURATION (DMAC_BASE+0X510) /* DMAC��5���üĴ��� */
-#define DMAC_C5DESCRIPTOR (DMAC_BASE+0X514) /* DMAC��5������ַ�Ĵ��� */
-
-
-/*
- * LCDCģ��
- * ��ַ: 0x11002000
- */
-
-#define LCDC_SSA (LCDC_BASE+0X000) /* ��Ļ��ʼ��ַ�Ĵ��� */
-#define LCDC_SIZE (LCDC_BASE+0X004) /* ��Ļ�ߴ�Ĵ��� */
-#define LCDC_PCR (LCDC_BASE+0X008) /* ������üĴ��� */
-#define LCDC_HCR (LCDC_BASE+0X00C) /* ˮƽ���üĴ��� */
-#define LCDC_VCR (LCDC_BASE+0X010) /* ��ֱ���üĴ��� */
-#define LCDC_PWMR (LCDC_BASE+0X014) /* PWM�Աȶȿ��ƼĴ��� */
-#define LCDC_LECR (LCDC_BASE+0X018) /* ʹ�ܿ��ƼĴ��� */
-#define LCDC_DMACR (LCDC_BASE+0X01C) /* DMA���ƼĴ��� */
-#define LCDC_LCDISREN (LCDC_BASE+0X020) /* �ж�ʹ�ܼĴ��� */
-#define LCDC_LCDISR (LCDC_BASE+0X024) /* �ж�״̬�Ĵ��� */
-#define LCDC_LGPMR (LCDC_BASE+0X040) /* �Ҷȵ�ɫӳ��Ĵ����� (16��32bit�Ĵ���) */
-
-
-/*
- * MACģ��
- * ��ַ: 0x11003000
- */
-
-#define MAC_CTRL (MAC_BASE+0X000) /* MAC���ƼĴ��� */
-#define MAC_INTSRC (MAC_BASE+0X004) /* MAC�ж�Դ�Ĵ��� */
-#define MAC_INTMASK (MAC_BASE+0X008) /* MAC�ж����μĴ��� */
-#define MAC_IPGT (MAC_BASE+0X00C) /* ����֡����Ĵ��� */
-#define MAC_IPGR1 (MAC_BASE+0X010) /* �ȴ����ڼĴ��� */
-#define MAC_IPGR2 (MAC_BASE+0X014) /* �ȴ����ڼĴ��� */
-#define MAC_PACKETLEN (MAC_BASE+0X018) /* ֡���ȼĴ��� */
-#define MAC_COLLCONF (MAC_BASE+0X01C) /* ��ײ�ط��Ĵ��� */
-#define MAC_TXBD_NUM (MAC_BASE+0X020) /* �����������Ĵ��� */
-#define MAC_FLOWCTRL (MAC_BASE+0X024) /* ���ؼĴ��� */
-#define MAC_MII_CTRL (MAC_BASE+0X028) /* PHY���ƼĴ��� */
-#define MAC_MII_CMD (MAC_BASE+0X02C) /* PHY����Ĵ��� */
-#define MAC_MII_ADDRESS (MAC_BASE+0X030) /* PHY��ַ�Ĵ��� */
-#define MAC_MII_TXDATA (MAC_BASE+0X034) /* PHYд���ݼĴ��� */
-#define MAC_MII_RXDATA (MAC_BASE+0X038) /* PHY�����ݼĴ��� */
-#define MAC_MII_STATUS (MAC_BASE+0X03C) /* PHY״̬�Ĵ��� */
-#define MAC_ADDR0 (MAC_BASE+0X040) /* MAC��ַ�Ĵ��� */
-#define MAC_ADDR1 (MAC_BASE+0X044) /* MAC��ַ�Ĵ��� */
-#define MAC_HASH0 (MAC_BASE+0X048) /* MAC HASH�Ĵ��� */
-#define MAC_HASH1 (MAC_BASE+0X04C) /* MAC HASH�Ĵ��� */
-#define MAC_TXPAUSE (MAC_BASE+0X050) /* MAC����֡�Ĵ��� */
-#define MAC_TX_BD (MAC_BASE+0X400)
-#define MAC_RX_BD (MAC_BASE+0X600)
-
-
-/*
- **************************************
- * Error Codes:
- * IF SUCCESS RETURN 0, ELSE RETURN OTHER ERROR CODE,
- * parameter error return (-33)/E_PAR,
- * hardware error reture (-99)/E_HA
- **************************************
- */
-
-#define E_OK 0 /* Normal completion */
-#define E_SYS (-5) /* System error */
-#define E_NOMEM (-10) /* Insufficient memory */
-#define E_NOSPT (-17) /* Feature not supported */
-#define E_INOSPT (-18) /* Feature not supported by ITRON/FILE specification */
-#define E_RSFN (-20) /* Reserved function code number */
-#define E_RSATR (-24) /* Reserved attribute */
-#define E_PAR (-33) /* Parameter error */
-#define E_ID (-35) /* Invalid ID number */
-#define E_NOEXS (-52) /* Object does not exist */
-#define E_OBJ (-63) /* Invalid object state */
-#define E_MACV (-65) /* Memory access disabled or memory access violation */
-#define E_OACV (-66) /* Object access violation */
-#define E_CTX (-69) /* Context error */
-#define E_QOVR (-73) /* Queuing or nesting overflow */
-#define E_DLT (-81) /* Object being waited for was deleted */
-#define E_TMOUT (-85) /* Polling failure or timeout exceeded */
-#define E_RLWAI (-86) /* WAIT state was forcibly released */
-
-#define E_HA (-99) /* HARD WARE ERROR */
-
-
-/*
- **************************************
- * PMU ģ��ʱ��
- **************************************
- */
-
-#define CLK_SGPT (1 << 16)
-#define CLK_SI2S (1 << 15)
-#define CLK_SSMC (1 << 14)
-#define CLK_SMAC (1 << 13)
-#define CLK_SUSB (1 << 12)
-#define CLK_SUART3 (1 << 11)
-#define CLK_SUART2 (1 << 10)
-#define CLK_SUART1 (1 << 9)
-#define CLK_SUART0 (1 << 8)
-#define CLK_SSSI (1 << 7)
-#define CLK_SAC97 (1 << 6)
-#define CLK_SMMCSD (1 << 5)
-#define CLK_SEMI (1 << 4)
-#define CLK_SDMAC (1 << 3)
-#define CLK_SPWM (1 << 2)
-#define CLK_SLCDC (1 << 1)
-#define CLK_SESRAM (1)
-
-
-/*Interrupt Sources*/
-
-
-#define INTSRC_RTC 31
-#define INTSRC_DMAC 30
-#define INTSRC_EMI 29
-#define INTSRC_MAC 28
-#define INTSRC_TIMER1 27
-#define INTSRC_TIMER2 26
-#define INTSRC_TIMER3 25
-#define INTSRC_UART0 24
-#define INTSRC_UART1 23
-#define INTSRC_UART2 22
-#define INTSRC_UART3 21
-#define INTSRC_PWM 20
-#define INTSRC_LCDC 19
-#define INTSRC_I2S 18
-#define INTSRC_SSI 17
-
-#define INTSRC_USB 15
-#define INTSRC_SMC0 14
-#define INTSRC_SMC1 13
-#define INTSRC_SDIO 12
-#define INTSRC_EXINT10 11
-#define INTSRC_EXINT9 10
-#define INTSRC_EXINT8 9
-#define INTSRC_EXINT7 8
-#define INTSRC_EXINT6 7
-#define INTSRC_EXINT5 6
-#define INTSRC_EXINT4 5
-#define INTSRC_EXINT3 4
-#define INTSRC_EXINT2 3
-#define INTSRC_EXINT1 2
-#define INTSRC_EXINT0 1
-#define INTSRC_NULL 0
-
-
-/*Sereral useful macros*/
-#define set_plevel(plevel) *(RP)INTC_IPLR = plevel //������ͨ�жϵ����ȼ����ޣ�ֻ�����ȼ����ڴ�ֵ���жϲ���ͨ��
-#define set_int_force(intnum) *(RP)INTC_IFR = (1 << intnum) //��1������ǿ�Ƹ�λ��Ӧ���ж�Դ�����ж��ź�
-#define enable_irq(intnum) *(RP)INTC_IER |= (1 << intnum) //��1�������ж�Դ��IRQ �ж��ź�
-#define disable_irq( intnum) *(RP)INTC_IER &= ~(1<< intnum) //��0�󣬲������ж�Դ��IRQ �ж��ź�
-#define mask_irq(intnum) *(RP)INTC_IMR |= (1 << intnum) //��1�����ζ�Ӧ��IRQ �ж��ź�
-#define unmask_irq(intnum) *(RP)INTC_IMR &= ~(1 << intnum) //��0��ͨ����Ӧ��IRQ �ж��ź�
-#define mask_all_irq() *(RP)INTC_IMR = 0xFFFFFFFF //���ζ�Ӧ��IRQ �ж��ź�
-#define unmask_all_irq() *(RP)INTC_IMR = 0x00000000 //ͨ����Ӧ��IRQ �ж��ź�
-#define enable_all_irq() *(RP)INTC_IER = 0XFFFFFFFF //�����ж�Դ��IRQ �ж��ź�
-#define disable_all_irq() *(RP)INTC_IER = 0X00000000 //�������ж�Դ��IRQ �ж��ź�
-#define InitInt() do{mask_all_irq(); enable_all_irq();}while(0)
-
-/*
- **************************************
- * ���г������õ���Typedef
- **************************************
- */
-
-typedef char S8; /* signed 8-bit integer */
-typedef short S16; /* signed 16-bit integer */
-typedef long S32; /* signed 32-bit integer */
-typedef unsigned char U8; /* unsigned 8-bit integer */
-typedef unsigned short U16; /* unsigned 16-bit integer */
-typedef unsigned long U32; /* unsigned 32-bit integer */
-
-typedef volatile U32 * RP;
-typedef volatile U16 * RP16;
-typedef volatile U8 * RP8;
-
-typedef void *VP; /* pointer to an unpredictable data type */
-typedef void (*FP)(); /* program start address */
-
-#ifndef _BOOL_TYPE_
-#define _BOOL_TYPE_
-typedef int BOOL; /* Boolean value. TRUE (1) or FALSE (0). */
-#endif
-
-typedef int ER; /* Error code. A signed integer. */
-
-/**
- * IO definitions
- *
- * define access restrictions to peripheral registers
- */
-
-#define __I volatile const /*!< defines 'read only' permissions */
-#define __O volatile /*!< defines 'write only' permissions */
-#define __IO volatile /*!< defines 'read / write' permissions */
-#define __iomem volatile
-
-
-/*Macros for debug*/
-
-#define EOUT(fmt,...) \
- do \
- { \
- rt_kprintf("EOUT:(%s:%i) ",__FILE__,__LINE__); \
- rt_kprintf(fmt,##__VA_ARGS__); \
- }while(0)
-
-#define RT_DEBUG
-#ifdef RT_DEBUG
- #define DBOUT(fmt,...) \
- do \
- { \
- rt_kprintf("DBOUT:(%s:%i) ",__FILE__,__LINE__); \
- rt_kprintf(fmt,##__VA_ARGS__); \
- }while(0)
-#else
- #define DBOUT(fmt,...) \
- do{}while(0)
-#endif
-
-#ifdef RT_DEBUG
- #define ASSERT(arg) \
- if((arg) == 0) \
- { \
- while(1) \
- { \
- rt_kprintf("have a assert failure\n"); \
- } \
- }
-#else
- #define ASSERT(arg) \
- do \
- { \
- }while(0)
-#endif
-
-
-#define write_reg(reg,value) \
- do \
- { \
- *(RP)(reg) = value; \
- }while(0)
-
-#define read_reg(reg) (*(RP)reg)
-
-
-struct rt_hw_register
-{
- rt_uint32_t r0;
- rt_uint32_t r1;
- rt_uint32_t r2;
- rt_uint32_t r3;
- rt_uint32_t r4;
- rt_uint32_t r5;
- rt_uint32_t r6;
- rt_uint32_t r7;
- rt_uint32_t r8;
- rt_uint32_t r9;
- rt_uint32_t r10;
- rt_uint32_t fp;
- rt_uint32_t ip;
- rt_uint32_t sp;
- rt_uint32_t lr;
- rt_uint32_t pc;
- rt_uint32_t cpsr;
- rt_uint32_t ORIG_r0;
-};
-
-
-/*@}*/
-
-#endif
+#ifndef __SEP4020_H +#define __SEP4020_H + +#include <rtthread.h> + +/*Core definations*/ +#define SVCMODE +#define Mode_USR 0x10 +#define Mode_FIQ 0x11 +#define Mode_IRQ 0x12 +#define Mode_SVC 0x13 +#define Mode_ABT 0x17 +#define Mode_UND 0x1B +#define Mode_SYS 0x1F + + + +/* + * ��ģ��Ĵ�����ֵ + */ + +#define ESRAM_BASE 0x04000000 +#define INTC_BASE 0x10000000 +#define PMU_BASE 0x10001000 +#define RTC_BASE 0x10002000 +#define WD_BASE 0x10002000 +#define TIMER_BASE 0x10003000 +#define PWM_BASE 0x10004000 +#define UART0_BASE 0X10005000 +#define UART1_BASE 0X10006000 +#define UART2_BASE 0X10007000 +#define UART3_BASE 0X10008000 +#define SSI_BASE 0X10009000 +#define I2S_BASE 0x1000A000 +#define MMC_BASE 0x1000B000 +#define SD_BASE 0x1000B000 +#define SMC0_BASE 0x1000C000 +#define SMC1_BASE 0x1000D000 +#define USBD_BASE 0x1000E000 +#define GPIO_BASE 0x1000F000 +#define EMI_BASE 0x11000000 +#define DMAC_BASE 0x11001000 +#define LCDC_BASE 0x11002000 +#define MAC_BASE 0x11003000 +#define AMBA_BASE 0x11005000 + + +/* + * INTCģ�� + * ��ַ: 0x10000000 + */ + +#define INTC_IER (INTC_BASE+0X000) /* IRQ�ж������Ĵ��� */ +#define INTC_IMR (INTC_BASE+0X008) /* IRQ�ж����μĴ��� */ +#define INTC_IFR (INTC_BASE+0X010) /* IRQ����ǿ���жϼĴ��� */ +#define INTC_IRSR (INTC_BASE+0X018) /* IRQδ�����ж�״̬�Ĵ��� */ +#define INTC_ISR (INTC_BASE+0X020) /* IRQ�ж�״̬�Ĵ��� */ +#define INTC_IMSR (INTC_BASE+0X028) /* IRQ�����ж�״̬�Ĵ��� */ +#define INTC_IFSR (INTC_BASE+0X030) /* IRQ�ж�����״̬�Ĵ��� */ +#define INTC_FIER (INTC_BASE+0X0C0) /* FIQ�ж������Ĵ��� */ +#define INTC_FIMR (INTC_BASE+0X0C4) /* FIQ�ж����μĴ��� */ +#define INTC_FIFR (INTC_BASE+0X0C8) /* FIQ����ǿ���жϼĴ��� */ +#define INTC_FIRSR (INTC_BASE+0X0CC) /* FIQδ�����ж�״̬�Ĵ��� */ +#define INTC_FISR (INTC_BASE+0X0D0) /* FIQ�ж�״̬�Ĵ��� */ +#define INTC_FIFSR (INTC_BASE+0X0D4) /* FIQ�ж�����״̬�Ĵ��� */ +#define INTC_IPLR (INTC_BASE+0X0D8) /* IRQ�ж����ȼ��Ĵ��� */ +#define INTC_ICR1 (INTC_BASE+0X0DC) /* IRQ�ڲ��ж����ȼ����ƼĴ���1 */ +#define INTC_ICR2 (INTC_BASE+0X0E0) /* IRQ�ڲ��ж����ȼ����ƼĴ���2 */ +#define INTC_EXICR1 (INTC_BASE+0X0E4) /* IRQ�ⲿ�ж����ȼ����ƼĴ���1 */ +#define INTC_EXICR2 (INTC_BASE+0X0E8) /* IRQ�ⲿ�ж����ȼ����ƼĴ���2 */ + + +/* + * PMUģ�� + * ��ַ: 0x10001000 + */ + +#define PMU_PLTR (PMU_BASE+0X000) /* PLL���ȶ�����ʱ�� */ +#define PMU_PMCR (PMU_BASE+0X004) /* ϵͳ��ʱ��PLL�Ŀ��ƼĴ��� */ +#define PMU_PUCR (PMU_BASE+0X008) /* USBʱ��PLL�Ŀ��ƼĴ��� */ +#define PMU_PCSR (PMU_BASE+0X00C) /* �ڲ�ģ��ʱ��Դ�����Ŀ��ƼĴ��� */ +#define PMU_PDSLOW (PMU_BASE+0X010) /* SLOW״̬��ʱ�ӵķ�Ƶ���� */ +#define PMU_PMDR (PMU_BASE+0X014) /* оƬ����ģʽ�Ĵ��� */ +#define PMU_RCTR (PMU_BASE+0X018) /* Reset���ƼĴ��� */ +#define PMU_CLRWAKUP (PMU_BASE+0X01C) /* WakeUp����Ĵ��� */ + + +/* + * RTCģ�� + * ��ַ: 0x10002000 + */ + +#define RTC_STA_YMD (RTC_BASE+0X000) /* ��, ��, �ռ����Ĵ��� */ +#define RTC_STA_HMS (RTC_BASE+0X004) /* Сʱ, ����, ��Ĵ��� */ +#define RTC_ALARM_ALL (RTC_BASE+0X008) /* ��ʱ��, ��, ʱ, �ּĴ��� */ +#define RTC_CTR (RTC_BASE+0X00C) /* ���ƼĴ��� */ +#define RTC_INT_EN (RTC_BASE+0X010) /* �ж�ʹ�ܼĴ��� */ +#define RTC_INT_STS (RTC_BASE+0X014) /* �ж�״̬�Ĵ��� */ +#define RTC_SAMP (RTC_BASE+0X018) /* �������ڼĴ��� */ +#define RTC_WD_CNT (RTC_BASE+0X01C) /* Watch-Dog����ֵ�Ĵ��� */ +#define RTC_WD_SEV (RTC_BASE+0X020) /* Watch-Dog����Ĵ��� */ +#define RTC_CONFIG_CHECK (RTC_BASE+0X024) /* ����ʱ��ȷ�ϼĴ��� (������ʱ��֮ǰ��д0xaaaaaaaa) */ +#define RTC_KEY0 (RTC_BASE+0X02C) /* ��Կ�Ĵ��� */ + +/* + * TIMERģ�� + * ��ַ: 0x10003000 + */ + +#define TIMER_T1LCR (TIMER_BASE+0X000) /* ͨ��1���ؼ����Ĵ��� */ +#define TIMER_T1CCR (TIMER_BASE+0X004) /* ͨ��1��ǰ����ֵ�Ĵ��� */ +#define TIMER_T1CR (TIMER_BASE+0X008) /* ͨ��1���ƼĴ��� */ +#define TIMER_T1ISCR (TIMER_BASE+0X00C) /* ͨ��1�ж�״̬����Ĵ��� */ +#define TIMER_T1IMSR (TIMER_BASE+0X010) /* ͨ��1�ж�����״̬�Ĵ��� */ +#define TIMER_T2LCR (TIMER_BASE+0X020) /* ͨ��2���ؼ����Ĵ��� */ +#define TIMER_T2CCR (TIMER_BASE+0X024) /* ͨ��2��ǰ����ֵ�Ĵ��� */ +#define TIMER_T2CR (TIMER_BASE+0X028) /* ͨ��2���ƼĴ��� */ +#define TIMER_T2ISCR (TIMER_BASE+0X02C) /* ͨ��2�ж�״̬����Ĵ��� */ +#define TIMER_T2IMSR (TIMER_BASE+0X030) /* ͨ��2�ж�����״̬�Ĵ��� */ +#define TIMER_T3LCR (TIMER_BASE+0X040) /* ͨ��3���ؼ����Ĵ��� */ +#define TIMER_T3CCR (TIMER_BASE+0X044) /* ͨ��3��ǰ����ֵ�Ĵ��� */ +#define TIMER_T3CR (TIMER_BASE+0X048) /* ͨ��3���ƼĴ��� */ +#define TIMER_T3ISCR (TIMER_BASE+0X04C) /* ͨ��3�ж�״̬����Ĵ��� */ +#define TIMER_T3IMSR (TIMER_BASE+0X050) /* ͨ��3�ж�����״̬�Ĵ��� */ +#define TIMER_T3CAPR (TIMER_BASE+0X054) /* ͨ��3����Ĵ��� */ +#define TIMER_T4LCR (TIMER_BASE+0X060) /* ͨ��4���ؼ����Ĵ��� */ +#define TIMER_T4CCR (TIMER_BASE+0X064) /* ͨ��4��ǰ����ֵ�Ĵ��� */ +#define TIMER_T4CR (TIMER_BASE+0X068) /* ͨ��4���ƼĴ��� */ +#define TIMER_T4ISCR (TIMER_BASE+0X06C) /* ͨ��4�ж�״̬����Ĵ��� */ +#define TIMER_T4IMSR (TIMER_BASE+0X070) /* ͨ��4�ж�����״̬�Ĵ��� */ +#define TIMER_T4CAPR (TIMER_BASE+0X074) /* ͨ��4����Ĵ��� */ +#define TIMER_T5LCR (TIMER_BASE+0X080) /* ͨ��5���ؼ����Ĵ��� */ +#define TIMER_T5CCR (TIMER_BASE+0X084) /* ͨ��5��ǰ����ֵ�Ĵ��� */ +#define TIMER_T5CR (TIMER_BASE+0X088) /* ͨ��5���ƼĴ��� */ +#define TIMER_T5ISCR (TIMER_BASE+0X08C) /* ͨ��5�ж�״̬����Ĵ��� */ +#define TIMER_T5IMSR (TIMER_BASE+0X090) /* ͨ��5�ж�����״̬�Ĵ��� */ +#define TIMER_T5CAPR (TIMER_BASE+0X094) /* ͨ��5����Ĵ��� */ +#define TIMER_T6LCR (TIMER_BASE+0X0A0) /* ͨ��6���ؼ����Ĵ��� */ +#define TIMER_T6CCR (TIMER_BASE+0X0A4) /* ͨ��6��ǰ����ֵ�Ĵ��� */ +#define TIMER_T6CR (TIMER_BASE+0X0A8) /* ͨ��6���ƼĴ��� */ +#define TIMER_T6ISCR (TIMER_BASE+0X0AC) /* ͨ��6�ж�״̬����Ĵ��� */ +#define TIMER_T6IMSR (TIMER_BASE+0X0B0) /* ͨ��6�ж�����״̬�Ĵ��� */ +#define TIMER_T6CAPR (TIMER_BASE+0X0B4) /* ͨ��6����Ĵ��� */ +#define TIMER_T7LCR (TIMER_BASE+0X0C0) /* ͨ��7���ؼ����Ĵ��� */ +#define TIMER_T7CCR (TIMER_BASE+0X0C4) /* ͨ��7��ǰ����ֵ�Ĵ��� */ +#define TIMER_T7CR (TIMER_BASE+0X0C8) /* ͨ��7���ƼĴ��� */ +#define TIMER_T7ISCR (TIMER_BASE+0X0CC) /* ͨ��7�ж�״̬����Ĵ��� */ +#define TIMER_T7IMSR (TIMER_BASE+0X0D0) /* ͨ��7�ж�����״̬�Ĵ��� */ +#define TIMER_T8LCR (TIMER_BASE+0X0E0) /* ͨ��8���ؼ����Ĵ��� */ +#define TIMER_T8CCR (TIMER_BASE+0X0E4) /* ͨ��8��ǰ����ֵ�Ĵ��� */ +#define TIMER_T8CR (TIMER_BASE+0X0E8) /* ͨ��8���ƼĴ��� */ +#define TIMER_T8ISCR (TIMER_BASE+0X0EC) /* ͨ��8�ж�״̬����Ĵ��� */ +#define TIMER_T8IMSR (TIMER_BASE+0X0F0) /* ͨ��8�ж�����״̬�Ĵ��� */ +#define TIMER_T9LCR (TIMER_BASE+0X100) /* ͨ��9���ؼ����Ĵ��� */ +#define TIMER_T9CCR (TIMER_BASE+0X104) /* ͨ��9��ǰ����ֵ�Ĵ��� */ +#define TIMER_T9CR (TIMER_BASE+0X108) /* ͨ��9���ƼĴ��� */ +#define TIMER_T9ISCR (TIMER_BASE+0X10C) /* ͨ��9�ж�״̬����Ĵ��� */ +#define TIMER_T9IMSR (TIMER_BASE+0X110) /* ͨ��9�ж�����״̬�Ĵ��� */ +#define TIMER_T10LCR (TIMER_BASE+0X120) /* ͨ��10���ؼ����Ĵ��� */ +#define TIMER_T10CCR (TIMER_BASE+0X124) /* ͨ��10��ǰ����ֵ�Ĵ��� */ +#define TIMER_T10CR (TIMER_BASE+0X128) /* ͨ��10���ƼĴ��� */ +#define TIMER_T10ISCR (TIMER_BASE+0X12C) /* ͨ��10�ж�״̬����Ĵ��� */ +#define TIMER_T10IMSR (TIMER_BASE+0X130) /* ͨ��10�ж�����״̬�Ĵ��� */ +#define TIMER_TIMSR (TIMER_BASE+0X140) /* TIMER�ж�����״̬�Ĵ��� */ +#define TIMER_TISCR (TIMER_BASE+0X144) /* TIMER�ж�״̬����Ĵ��� */ +#define TIMER_TISR (TIMER_BASE+0X148) /* TIMER�ж�״̬�Ĵ��� */ + + + +/* + * PWMģ�� + * ��ַ: 0x10004000 + */ + +#define PWM0_CTRL (PWM_BASE+0X000) /* PWM0���ƼĴ��� */ +#define PWM0_DIV (PWM_BASE+0X004) /* PWM0��Ƶ�Ĵ��� */ +#define PWM0_PERIOD (PWM_BASE+0X008) /* PWM0���ڼĴ��� */ +#define PWM0_DATA (PWM_BASE+0X00C) /* PWM0���ݼĴ��� */ +#define PWM0_CNT (PWM_BASE+0X010) /* PWM0�����Ĵ��� */ +#define PWM0_STATUS (PWM_BASE+0X014) /* PWM0״̬�Ĵ��� */ +#define PWM1_CTRL (PWM_BASE+0X020) /* PWM1���ƼĴ��� */ +#define PWM1_DIV (PWM_BASE+0X024) /* PWM1��Ƶ�Ĵ��� */ +#define PWM1_PERIOD (PWM_BASE+0X028) /* PWM1���ڼĴ��� */ +#define PWM1_DATA (PWM_BASE+0X02C) /* PWM1���ݼĴ��� */ +#define PWM1_CNT (PWM_BASE+0X030) /* PWM1�����Ĵ��� */ +#define PWM1_STATUS (PWM_BASE+0X034) /* PWM1״̬�Ĵ��� */ +#define PWM2_CTRL (PWM_BASE+0X040) /* PWM2���ƼĴ��� */ +#define PWM2_DIV (PWM_BASE+0X044) /* PWM2��Ƶ�Ĵ��� */ +#define PWM2_PERIOD (PWM_BASE+0X048) /* PWM2���ڼĴ��� */ +#define PWM2_DATA (PWM_BASE+0X04C) /* PWM2���ݼĴ��� */ +#define PWM2_CNT (PWM_BASE+0X050) /* PWM2�����Ĵ��� */ +#define PWM2_STATUS (PWM_BASE+0X054) /* PWM2״̬�Ĵ��� */ +#define PWM3_CTRL (PWM_BASE+0X060) /* PWM3���ƼĴ��� */ +#define PWM3_DIV (PWM_BASE+0X064) /* PWM3��Ƶ�Ĵ��� */ +#define PWM3_PERIOD (PWM_BASE+0X068) /* PWM3���ڼĴ��� */ +#define PWM3_DATA (PWM_BASE+0X06C) /* PWM3���ݼĴ��� */ +#define PWM3_CNT (PWM_BASE+0X070) /* PWM3�����Ĵ��� */ +#define PWM3_STATUS (PWM_BASE+0X074) /* PWM3״̬�Ĵ��� */ +#define PWM_INTMASK (PWM_BASE+0X080) /* PWM�ж����μĴ��� */ +#define PWM_INT (PWM_BASE+0X084) /* PWM�жϼĴ��� */ +#define PWM_ENABLE (PWM_BASE+0X088) /* PWMʹ�ܼĴ��� */ + + +/* + * UART0ģ�� + * ��ַ: 0x10005000 + */ + +#define UART0_DLBL (UART0_BASE+0X000) /* ���������õͰ�λ�Ĵ��� */ +#define UART0_RXFIFO (UART0_BASE+0X000) /* ����FIFO */ +#define UART0_TXFIFO (UART0_BASE+0X000) /* ����FIFO */ +#define UART0_DLBH (UART0_BASE+0X004) /* ���������ø߰�λ�Ĵ��� */ +#define UART0_IER (UART0_BASE+0X004) /* �ж�ʹ�ܼĴ��� */ +#define UART0_IIR (UART0_BASE+0X008) /* �ж�ʶ��Ĵ��� */ +#define UART0_FCR (UART0_BASE+0X008) /* FIFO���ƼĴ��� */ +#define UART0_LCR (UART0_BASE+0X00C) /* �п��ƼĴ��� */ +#define UART0_MCR (UART0_BASE+0X010) /* Modem���ƼĴ��� */ +#define UART0_LSR (UART0_BASE+0X014) /* ��״̬�Ĵ��� */ +#define UART0_MSR (UART0_BASE+0X018) /* Modem״̬�Ĵ��� */ + + +/* + * UART1ģ�� + * ��ַ: 0x10006000 + */ + +#define UART1_DLBL (UART1_BASE+0X000) /* ���������õͰ�λ�Ĵ��� */ +#define UART1_RXFIFO (UART1_BASE+0X000) /* ����FIFO */ +#define UART1_TXFIFO (UART1_BASE+0X000) /* ����FIFO */ +#define UART1_DLBH (UART1_BASE+0X004) /* ���������ø߰�λ�Ĵ��� */ +#define UART1_IER (UART1_BASE+0X004) /* �ж�ʹ�ܼĴ��� */ +#define UART1_IIR (UART1_BASE+0X008) /* �ж�ʶ��Ĵ��� */ +#define UART1_FCR (UART1_BASE+0X008) /* FIFO���ƼĴ��� */ +#define UART1_LCR (UART1_BASE+0X00C) /* �п��ƼĴ��� */ +#define UART1_MCR (UART1_BASE+0X010) /* Modem���ƼĴ��� */ +#define UART1_LSR (UART1_BASE+0X014) /* ��״̬�Ĵ��� */ +#define UART1_MSR (UART1_BASE+0X018) /* Modem״̬�Ĵ��� */ + + +/* + * UART2ģ�� + * ��ַ: 0x10007000 + */ + +#define UART2_DLBL (UART2_BASE+0X000) /* ���������õͰ�λ�Ĵ��� */ +#define UART2_RXFIFO (UART2_BASE+0X000) /* ����FIFO */ +#define UART2_TXFIFO (UART2_BASE+0X000) /* ����FIFO */ +#define UART2_DLBH (UART2_BASE+0X004) /* ���������ø߰�λ�Ĵ��� */ +#define UART2_IER (UART2_BASE+0X004) /* �ж�ʹ�ܼĴ��� */ +#define UART2_IIR (UART2_BASE+0X008) /* �ж�ʶ��Ĵ��� */ +#define UART2_FCR (UART2_BASE+0X008) /* FIFO���ƼĴ��� */ +#define UART2_LCR (UART2_BASE+0X00C) /* �п��ƼĴ��� */ +#define UART2_MCR (UART2_BASE+0X010) /* Modem���ƼĴ��� */ +#define UART2_LSR (UART2_BASE+0X014) /* ��״̬�Ĵ��� */ +#define UART2_MSR (UART2_BASE+0X018) /* Modem״̬�Ĵ��� */ + + +/* + * UART3ģ�� + * ��ַ: 0x10008000 + */ + +#define UART3_DLBL (UART3_BASE+0X000) /* ���������õͰ�λ�Ĵ��� */ +#define UART3_RXFIFO (UART3_BASE+0X000) /* ����FIFO */ +#define UART3_TXFIFO (UART3_BASE+0X000) /* ����FIFO */ +#define UART3_DLBH (UART3_BASE+0X004) /* ���������ø߰�λ�Ĵ��� */ +#define UART3_IER (UART3_BASE+0X004) /* �ж�ʹ�ܼĴ��� */ +#define UART3_IIR (UART3_BASE+0X008) /* �ж�ʶ��Ĵ��� */ +#define UART3_FCR (UART3_BASE+0X008) /* FIFO���ƼĴ��� */ +#define UART3_LCR (UART3_BASE+0X00C) /* �п��ƼĴ��� */ +#define UART3_MCR (UART3_BASE+0X010) /* Modem���ƼĴ��� */ +#define UART3_LSR (UART3_BASE+0X014) /* ��״̬�Ĵ��� */ +#define UART3_MSR (UART3_BASE+0X018) /* Modem״̬�Ĵ��� */ + + +/* + * SSIģ�� + * ��ַ: 0x10009000 + */ + +#define SSI_CONTROL0 (SSI_BASE+0X000) /* ���ƼĴ���0 */ +#define SSI_CONTROL1 (SSI_BASE+0X004) /* ���ƼĴ���1 */ +#define SSI_SSIENR (SSI_BASE+0X008) /* SSIʹ�ܼĴ��� */ +#define SSI_MWCR (SSI_BASE+0X00C) /* Microwire���ƼĴ��� */ +#define SSI_SER (SSI_BASE+0X010) /* ���豸ʹ�ܼĴ��� */ +#define SSI_BAUDR (SSI_BASE+0X014) /* ���������üĴ��� */ +#define SSI_TXFTLR (SSI_BASE+0X018) /* ����FIFO��ֵ�Ĵ��� */ +#define SSI_RXFTLR (SSI_BASE+0X01C) /* ����FIFO��ֵ�Ĵ��� */ +#define SSI_TXFLR (SSI_BASE+0X020) /* ����FIFO״̬�Ĵ��� */ +#define SSI_RXFLR (SSI_BASE+0X024) /* ����FIFO״̬�Ĵ��� */ +#define SSI_SR (SSI_BASE+0X028) /* ״̬�Ĵ��� */ +#define SSI_IMR (SSI_BASE+0X02C) /* �ж����μĴ��� */ +#define SSI_ISR (SSI_BASE+0X030) /* �ж�����״̬�Ĵ��� */ +#define SSI_RISR (SSI_BASE+0X034) /* �ж�Ôʼ״̬�Ĵ��� */ +#define SSI_TXOICR (SSI_BASE+0X038) /* ����FIFO�����ж�����Ĵ��� */ +#define SSI_RXOICR (SSI_BASE+0X03C) /* ����FIFO�����ж�����Ĵ��� */ +#define SSI_RXUICR (SSI_BASE+0X040) /* ����FIFO�����ж�����Ĵ��� */ +#define SSI_ICR (SSI_BASE+0X02C) /* �ж�����Ĵ��� */ +#define SSI_DMACR (SSI_BASE+0X04C) /* DMA���ƼĴ��� */ +#define SSI_DMATDLR (SSI_BASE+0X050) /* DMA����״̬�Ĵ��� */ +#define SSI_DMARDLR (SSI_BASE+0X054) /* DMA����״̬�Ĵ��� */ +#define SSI_DR (SSI_BASE+0X060) /* ���ݼĴ��� */ + + +/* + * I2Sģ�� + * ��ַ: 0x1000A000 + */ + +#define I2S_CTRL (I2S_BASE+0X000) /* I2S���ƼĴ��� */ +#define I2S_DATA (I2S_BASE+0X004) /* I2S���ݼĴ��� */ +#define I2S_INT (I2S_BASE+0X008) /* I2S�жϼĴ��� */ +#define I2S_STATUS (I2S_BASE+0X00C) /* I2S״̬�Ĵ��� */ + + +/* + * SDģ�� + * ��ַ: 0x1000B000 + */ + +#define SDC_CLOCK_CONTROL (SD_BASE+0x00) /* SDIOʱ�ӿ��ƼĴ��� */ +#define SDC_SOFTWARE_RESET (SD_BASE+0X04) /* SDIO������λ�Ĵ��� */ +#define SDC_ARGUMENT (SD_BASE+0X08) /* SDIO��������Ĵ��� */ +#define SDC_COMMAND (SD_BASE+0X0C) /* SDIO������ƼĴ��� */ +#define SDC_BLOCK_SIZE (SD_BASE+0X10) /* SDIO���ݿ鳤�ȼĴ��� */ +#define SDC_BLOCK_COUNT (SD_BASE+0X14) /* SDIO���ݿ���Ŀ�Ĵ��� */ +#define SDC_TRANSFER_MODE (SD_BASE+0X18) /* SDIO����ģʽѡ��Ĵ��� */ +#define SDC_RESPONSE0 (SD_BASE+0X1c) /* SDIO��Ӧ�Ĵ���0 */ +#define SDC_RESPONSE1 (SD_BASE+0X20) /* SDIO��Ӧ�Ĵ���1 */ +#define SDC_RESPONSE2 (SD_BASE+0X24) /* SDIO��Ӧ�Ĵ���2 */ +#define SDC_RESPONSE3 (SD_BASE+0X28) /* SDIO��Ӧ�Ĵ���3 */ +#define SDC_READ_TIMEOUT_CONTROL (SD_BASE+0X2c) /* SDIO����ʱ���ƼĴ��� */ +#define SDC_INTERRUPT_STATUS (SD_BASE+0X30) /* SDIO�ж�״̬�Ĵ��� */ +#define SDC_INTERRUPT_STATUS_MASK (SD_BASE+0X34) /* SDIO�ж�״̬���μĴ��� */ +#define SDC_READ_BUFER_ACCESS (SD_BASE+0X38) /* SDIO����FIFO */ +#define SDC_WRITE_BUFER_ACCESS (SD_BASE+0X3c) /* SDIO����FIFO */ + + + +/* + * SMC0ģ�� + * ��ַ: 0x1000C000 + */ + +#define SMC0_CTRL (SMC0_BASE+0X000) /* SMC0���ƼĴ��� */ +#define SMC0_INT (SMC0_BASE+0X004) /* SMC0�жϼĴ��� */ +#define SMC0_FD (SMC0_BASE+0X008) /* SMC0������Ԫʱ��Ĵ��� */ +#define SMC0_CT (SMC0_BASE+0X00C) /* SMC0�ַ�����ʱ��Ĵ��� */ +#define SMC0_BT (SMC0_BASE+0X010) /* SMC0�鴫��ʱ��Ĵ��� */ + + + +/* + * SMC1ģ�� + * ��ַ: 0x1000D000 + */ + +#define SMC1_CTRL (SMC1_BASE+0X000) /* SMC1���ƼĴ��� */ +#define SMC1_INT (SMC1_BASE+0X004) /* SMC1�жϼĴ��� */ +#define SMC1_FD (SMC1_BASE+0X008) /* SMC1������Ԫʱ��Ĵ��� */ +#define SMC1_CT (SMC1_BASE+0X00C) /* SMC1�ַ�����ʱ��Ĵ��� */ +#define SMC1_BT (SMC1_BASE+0X010) /* SMC1�鴫��ʱ��Ĵ��� */ + + + +/* + * USBDģ�� + * ��ַ: 0x1000E000 + */ + +#define USBD_PROTOCOLINTR (USBD_BASE+0X000) /* USBÐ���жϼĴ��� */ +#define USBD_INTRMASK (USBD_BASE+0X004) /* USB�ж����μĴ��� */ +#define USBD_INTRCTRL (USBD_BASE+0X008) /* USB�ж����Ϳ��ƼĴ��� */ +#define USBD_EPINFO (USBD_BASE+0X00C) /* USB��˵�״̬�Ĵ��� */ +#define USBD_BCONFIGURATIONVALUE (USBD_BASE+0X010) /* SET_CCONFIGURATION��¼ */ +#define USBD_BMATTRIBUTES (USBD_BASE+0X014) /* ��ǰ�������ԼĴ��� */ +#define USBD_DEVSPEED (USBD_BASE+0X018) /* ��ǰ�豸�����ٶȼĴ��� */ +#define USBD_FRAMENUMBER (USBD_BASE+0X01C) /* ��¼��ǰSOF���ڵ�֡�� */ +#define USBD_EPTRANSACTIONS0 (USBD_BASE+0X020) /* ��¼�´�Ҫ��Ĵ������ */ +#define USBD_EPTRANSACTIONS1 (USBD_BASE+0X024) /* ��¼�´�Ҫ��Ĵ������ */ +#define USBD_APPIFUPDATE (USBD_BASE+0X028) /* �ӿںſ��ٸ��¼Ĵ��� */ +#define USBD_CFGINTERFACE0 (USBD_BASE+0X02C) /* ��¼�ӿڵ�ֵ */ +#define USBD_CFGINTERFACE1 (USBD_BASE+0X030) /* ��¼�ӿڵ�ֵ */ +#define USBD_CFGINTERFACE2 (USBD_BASE+0X034) /* ��¼�ӿڵ�ֵ */ +#define USBD_CFGINTERFACE3 (USBD_BASE+0X038) /* ��¼�ӿڵ�ֵ */ +#define USBD_CFGINTERFACE4 (USBD_BASE+0X03C) /* ��¼�ӿڵ�ֵ */ +#define USBD_CFGINTERFACE5 (USBD_BASE+0X040) /* ��¼�ӿڵ�ֵ */ +#define USBD_CFGINTERFACE6 (USBD_BASE+0X044) /* ��¼�ӿڵ�ֵ */ +#define USBD_CFGINTERFACE7 (USBD_BASE+0X048) /* ��¼�ӿڵ�ֵ */ +#define USBD_CFGINTERFACE8 (USBD_BASE+0X04C) /* ��¼�ӿڵ�ֵ */ +#define USBD_CFGINTERFACE9 (USBD_BASE+0X050) /* ��¼�ӿڵ�ֵ */ +#define USBD_CFGINTERFACE10 (USBD_BASE+0X054) /* ��¼�ӿڵ�ֵ */ +#define USBD_CFGINTERFACE11 (USBD_BASE+0X058) /* ��¼�ӿڵ�ֵ */ +#define USBD_CFGINTERFACE12 (USBD_BASE+0X05C) /* ��¼�ӿڵ�ֵ */ +#define USBD_CFGINTERFACE13 (USBD_BASE+0X060) /* ��¼�ӿڵ�ֵ */ +#define USBD_CFGINTERFACE14 (USBD_BASE+0X064) /* ��¼�ӿڵ�ֵ */ +#define USBD_CFGINTERFACE15 (USBD_BASE+0X068) /* ��¼�ӿڵ�ֵ */ +#define USBD_CFGINTERFACE16 (USBD_BASE+0X06C) /* ��¼�ӿڵ�ֵ */ +#define USBD_CFGINTERFACE17 (USBD_BASE+0X070) /* ��¼�ӿڵ�ֵ */ +#define USBD_CFGINTERFACE18 (USBD_BASE+0X074) /* ��¼�ӿڵ�ֵ */ +#define USBD_CFGINTERFACE19 (USBD_BASE+0X078) /* ��¼�ӿڵ�ֵ */ +#define USBD_CFGINTERFACE20 (USBD_BASE+0X07C) /* ��¼�ӿڵ�ֵ */ +#define USBD_CFGINTERFACE21 (USBD_BASE+0X080) /* ��¼�ӿڵ�ֵ */ +#define USBD_CFGINTERFACE22 (USBD_BASE+0X084) /* ��¼�ӿڵ�ֵ */ +#define USBD_CFGINTERFACE23 (USBD_BASE+0X088) /* ��¼�ӿڵ�ֵ */ +#define USBD_CFGINTERFACE24 (USBD_BASE+0X08C) /* ��¼�ӿڵ�ֵ */ +#define USBD_CFGINTERFACE25 (USBD_BASE+0X090) /* ��¼�ӿڵ�ֵ */ +#define USBD_CFGINTERFACE26 (USBD_BASE+0X094) /* ��¼�ӿڵ�ֵ */ +#define USBD_CFGINTERFACE27 (USBD_BASE+0X098) /* ��¼�ӿڵ�ֵ */ +#define USBD_CFGINTERFACE28 (USBD_BASE+0X09C) /* ��¼�ӿڵ�ֵ */ +#define USBD_CFGINTERFACE29 (USBD_BASE+0X0A0) /* ��¼�ӿڵ�ֵ */ +#define USBD_CFGINTERFACE30 (USBD_BASE+0X0A4) /* ��¼�ӿڵ�ֵ */ +#define USBD_CFGINTERFACE31 (USBD_BASE+0X0A8) /* ��¼�ӿڵ�ֵ */ +#define USBD_PKTPASSEDCTRL (USBD_BASE+0X0AC) /* ��¼�ɹ����յİ��� */ +#define USBD_PKTDROPPEDCTRL (USBD_BASE+0X0B0) /* ��¼��ʧ�İ��� */ +#define USBD_CRCERRCTRL (USBD_BASE+0X0B4) /* ��¼CRC������� */ +#define USBD_BITSTUFFERRCTRL (USBD_BASE+0X0B8) /* ��¼λ������İ��� */ +#define USBD_PIDERRCTRL (USBD_BASE+0X0BC) /* ��¼PID������� */ +#define USBD_FRAMINGERRCTL (USBD_BASE+0X0C0) /* ��¼��SYNC��EOP���� */ +#define USBD_TXPKTCTRL (USBD_BASE+0X0C4) /* ��¼���Ͱ������� */ +#define USBD_STATCTRLOV (USBD_BASE+0X0C8) /* ��¼ͳ�ƼĴ��������� */ +#define USBD_TXLENGTH (USBD_BASE+0X0CC) /* ��¼ÿ��IN������������� */ +#define USBD_RXLENGTH (USBD_BASE+0X0D0) /* ��¼OUT������������� */ +#define USBD_RESUME (USBD_BASE+0X0D4) /* USB���ѼĴ��� */ +#define USBD_READFLAG (USBD_BASE+0X0D8) /* ���첽״̬�Ĵ�����־ */ +#define USBD_RECEIVETYPE (USBD_BASE+0X0DC) /* ����״̬�Ĵ��� */ +#define USBD_APPLOCK (USBD_BASE+0X0E0) /* ���źżĴ��� */ +#define USBD_EP0OUTADDR (USBD_BASE+0X100) /* �˵�0�˵�źͷ��� */ +#define USBD_EP0OUTBMATTR (USBD_BASE+0X104) /* �˵�0���ͼĴ��� */ +#define USBD_EP0OUTMAXPKTSIZE (USBD_BASE+0X108) /* �˵�0�����ߴ�Ĵ��� */ +#define USBD_EP0OUTIFNUM (USBD_BASE+0X10C) /* �˵�0�ӿںżĴ��� */ +#define USBD_EP0OUTSTAT (USBD_BASE+0X110) /* �˵�0״̬�Ĵ��� */ +#define USBD_EP0OUTBMREQTYPE (USBD_BASE+0X114) /* �˵�0 SETUP���������� */ +#define USBD_EP0OUTBREQUEST (USBD_BASE+0X118) /* �˵�0 SETUP������������ */ +#define USBD_EP0OUTWVALUE (USBD_BASE+0X11C) /* �˵�0 SETUP��������ֵ */ +#define USBD_EP0OUTWINDEX (USBD_BASE+0X120) /* �˵�0 SETUP������������ */ +#define USBD_EP0OUTWLENGTH (USBD_BASE+0X120) /* �˵�0 SETUP�������󳤶� */ +#define USBD_EP0OUTSYNCHFRAME (USBD_BASE+0X128) /* �˵�0ͬ����֡�� */ +#define USBD_EP1OUTADDR (USBD_BASE+0X12C) /* �˵�1����˵�źͷ��� */ +#define USBD_EP1OUTBMATTR (USBD_BASE+0X130) /* �˵�1������ͼĴ��� */ +#define USBD_EP1OUTMAXPKTSIZE (USBD_BASE+0X134) /* �˵�1��������ߴ�Ĵ��� */ +#define USBD_EP1OUTIFNUM (USBD_BASE+0X138) /* �˵�1����ӿںżĴ��� */ +#define USBD_EP1OUTSTAT (USBD_BASE+0X13C) /* �˵�1���״̬�Ĵ��� */ +#define USBD_EP1OUTBMREQTYPE (USBD_BASE+0X140) /* �˵�1���SETUP������������ */ +#define USBD_EP1OUTBREQUEST (USBD_BASE+0X144) /* �˵�1���SETUP������������ */ +#define USBD_EP1OUTWVALUE (USBD_BASE+0X148) /* �˵�1���SETUP��������ֵ */ +#define USBD_EP1OUTWINDX (USBD_BASE+0X14C) /* �˵�1���SETUP������������ */ +#define USBD_EP1OUTWLENGH (USBD_BASE+0X150) /* �˵�1���SETUP���������ò³¤¶ï¿½ */ +#define USBD_EP1OUTSYNCHFRAME (USBD_BASE+0X154) /* �˵�1���ͬ����֡�� */ +#define USBD_EP1INADDR (USBD_BASE+0X158) /* �˵�1����˵�źͷ��� */ +#define USBD_EP1INBMATTR (USBD_BASE+0X15C) /* �˵�1�������ͼĴ��� */ +#define USBD_EP1INMAXPKTSIZE (USBD_BASE+0X160) /* �˵�1���������ߴ�Ĵ��� */ +#define USBD_EP1INIFNUM (USBD_BASE+0X164) /* �˵�1����ӿںżĴ��� */ +#define USBD_EP1INSTAT (USBD_BASE+0X168) /* �˵�1����״̬�Ĵ��� */ +#define USBD_EP1INBMREQTYPE (USBD_BASE+0X16C) /* �˵�1����SETUP������������ */ +#define USBD_EP1INBREQUEST (USBD_BASE+0X170) /* �˵�1����SETUP������������ */ +#define USBD_EP1INWVALUE (USBD_BASE+0X174) /* �˵�1����SETUP��������ֵ */ +#define USBD_EP1INWINDEX (USBD_BASE+0X178) /* �˵�1����SETUP������������ */ +#define USBD_EP1INWLENGTH (USBD_BASE+0X17C) /* �˵�1����SETUP���������ò³¤¶ï¿½ */ +#define USBD_EP1INSYNCHFRAME (USBD_BASE+0X180) /* �˵�1����ͬ����֡�� */ +#define USBD_EP2OUTADDR (USBD_BASE+0X184) /* �˵�2����˵�źͷ��� */ +#define USBD_EP2OUTBMATTR (USBD_BASE+0X188) /* �˵�2������ͼĴ��� */ +#define USBD_EP2OUTMAXPKTSIZE (USBD_BASE+0X18C) /* �˵�2��������ߴ�Ĵ��� */ +#define USBD_EP2OUTIFNUM (USBD_BASE+0X190) /* �˵�2����ӿںżĴ��� */ +#define USBD_EP2OUTSTAT (USBD_BASE+0X194) /* �˵�2���״̬�Ĵ��� */ +#define USBD_EP2OUTBMREQTYPE (USBD_BASE+0X198) /* �˵�2���SETUP������������ */ +#define USBD_EP2OUTBREQUEST (USBD_BASE+0X19C) /* �˵�2���SETUP������������ */ +#define USBD_EP2OUTWVALUE (USBD_BASE+0X1A0) /* �˵�2���SETUP��������ֵ */ +#define USBD_EP2OUTWINDEX (USBD_BASE+0X1A4) /* �˵�2���SETUP������������ */ +#define USBD_EP2OUTWLENGTH (USBD_BASE+0X1A8) /* �˵�2���SETUP���������ò³¤¶ï¿½ */ +#define USBD_EP2OUTSYNCHFRAME (USBD_BASE+0X1AC) /* �˵�2���ͬ����֡�� */ +#define USBD_EP2INADDR (USBD_BASE+0X1B0) /* �˵�2����˵�źͷ��� */ +#define USBD_EP2INBMATTR (USBD_BASE+0X1B4) /* �˵�2�������ͼĴ��� */ +#define USBD_EP2INMAXPKTSIZE (USBD_BASE+0X1B8) /* �˵�2���������ߴ�Ĵ��� */ +#define USBD_EP2INIFNUM (USBD_BASE+0X1BC) /* �˵�2����ӿںżĴ��� */ +#define USBD_EP2INSTAT (USBD_BASE+0X1C0) /* �˵�2����״̬�Ĵ��� */ +#define USBD_EP2INBMREQTYPE (USBD_BASE+0X1C4) /* �˵�2����SETUP������������ */ +#define USBD_EP2INBREQUEST (USBD_BASE+0X1C8) /* �˵�2����SETUP������������ */ +#define USBD_EP2INWVALUE (USBD_BASE+0X1CC) /* �˵�2����SETUP��������ֵ */ +#define USBD_EP2INWINDEX (USBD_BASE+0X1D0) /* �˵�2����SETUP������������ */ +#define USBD_EP2INWLENGTH (USBD_BASE+0X1D4) /* �˵�2����SETUP���������ò³¤¶ï¿½ */ +#define USBD_EP2INSYNCHFRAME (USBD_BASE+0X1D8) /* �˵�2����ͬ����֡�� */ +#define USBD_RXFIFO (USBD_BASE+0X200) /* ����FIFO */ +#define USBD_TXFIFO (USBD_BASE+0X300) /* ����FIFO */ + + +/* + * GPIOģ�� + * ��ַ: 0x1000F000 + */ + +#define GPIO_DBCLK_DIV (GPIO_BASE+0X000) /* ȥë�̲���ʱ�ӷ�Ƶ�����üĴ��� */ +#define GPIO_PORTA_DIR (GPIO_BASE+0X004) /* A��˿���������������üĴ��� */ +#define GPIO_PORTA_SEL (GPIO_BASE+0X008) /* A��˿�ͨ����;ѡ�����üĴ��� */ +#define GPIO_PORTA_INCTL (GPIO_BASE+0X00C) /* A��˿�ͨ����;����ʱ�������üĴ��� */ +#define GPIO_PORTA_INTRCTL (GPIO_BASE+0X010) /* A��˿��жϴ����������üĴ��� */ +#define GPIO_PORTA_INTRCLR (GPIO_BASE+0X014) /* A��˿�ͨ����;�ж�������üĴ��� */ +#define GPIO_PORTA_DATA (GPIO_BASE+0X018) /* A��˿�ͨ����;�������üĴ��� */ +#define GPIO_PORTB_DIR (GPIO_BASE+0X01C) /* B��˿���������������üĴ��� */ +#define GPIO_PORTB_SEL (GPIO_BASE+0X020) /* B��˿�ͨ����;ѡ�����üĴ��� */ +#define GPIO_PORTB_DATA (GPIO_BASE+0X024) /* B��˿�ͨ����;�������üĴ��� */ +#define GPIO_PORTC_DIR (GPIO_BASE+0X028) /* C��˿���������������üĴ��� */ +#define GPIO_PORTC_SEL (GPIO_BASE+0X02C) /* C��˿�ͨ����;ѡ�����üĴ��� */ +#define GPIO_PORTC_DATA (GPIO_BASE+0X030) /* C��˿�ͨ����;�������üĴ��� */ +#define GPIO_PORTD_DIR (GPIO_BASE+0X034) /* D��˿���������������üĴ��� */ +#define GPIO_PORTD_SEL (GPIO_BASE+0X038) /* D��˿�ͨ����;ѡ�����üĴ��� */ +#define GPIO_PORTD_SPECII (GPIO_BASE+0X03C) /* D��˿�ר����;2ѡ�����üĴ��� */ +#define GPIO_PORTD_DATA (GPIO_BASE+0X040) /* D��˿�ͨ����;�������üĴ��� */ +#define GPIO_PORTE_DIR (GPIO_BASE+0X044) /* E��˿���������������üĴ��� */ +#define GPIO_PORTE_SEL (GPIO_BASE+0X048) /* E��˿�ͨ����;ѡ�����üĴ��� */ +#define GPIO_PORTE_DATA (GPIO_BASE+0X04C) /* E��˿�ͨ����;�������üĴ��� */ +#define GPIO_PORTF_DIR (GPIO_BASE+0X050) /* F��˿���������������üĴ��� */ +#define GPIO_PORTF_SEL (GPIO_BASE+0X054) /* F��˿�ͨ����;ѡ�����üĴ��� */ +#define GPIO_PORTF_INCTL (GPIO_BASE+0X058) /* F��˿�ͨ����;����ʱ�������üĴ��� */ +#define GPIO_PORTF_INTRCTL (GPIO_BASE+0X05C) /* F��˿��жϴ����������üĴ��� */ +#define GPIO_PORTF_INTRCLR (GPIO_BASE+0X060) /* F��˿�ͨ����;�ж�������üĴ��� */ +#define GPIO_PORTF_DATA (GPIO_BASE+0X064) /* F��˿�ͨ����;�������üĴ��� */ +#define GPIO_PORTG_DIR (GPIO_BASE+0X068) /* G��˿���������������üĴ��� */ +#define GPIO_PORTG_SEL (GPIO_BASE+0X06C) /* G��˿�ͨ����;ѡ�����üĴ��� */ +#define GPIO_PORTG_DATA (GPIO_BASE+0X070) /* G��˿�ͨ����;�������üĴ��� */ +#define GPIO_PORTH_DIR (GPIO_BASE+0X07C) /* H��˿���������������üĴ��� */ +#define GPIO_PORTH_SEL (GPIO_BASE+0X078) /* H��˿�ͨ����;ѡ�����üĴ��� */ +#define GPIO_PORTH_DATA (GPIO_BASE+0X07C) /* H��˿�ͨ����;�������üĴ��� */ +#define GPIO_PORTI_DIR (GPIO_BASE+0X080) /* I��˿���������������üĴ��� */ +#define GPIO_PORTI_SEL (GPIO_BASE+0X084) /* I��˿�ͨ����;ѡ�����üĴ��� */ +#define GPIO_PORTI_DATA (GPIO_BASE+0X088) /* I��˿�ͨ����;�������üĴ��� */ + + + +/* + * EMIģ�� + * ��ַ: 0x11000000 + */ + +#define EMI_CSACONF (EMI_BASE+0X000) /* CSA�������üĴ��� */ +#define EMI_CSBCONF (EMI_BASE+0X004) /* CSB�������üĴ��� */ +#define EMI_CSCCONF (EMI_BASE+0X008) /* CSC�������üĴ��� */ +#define EMI_CSDCONF (EMI_BASE+0X00C) /* CSD�������üĴ��� */ +#define EMI_CSECONF (EMI_BASE+0X010) /* CSE�������üĴ��� */ +#define EMI_CSFCONF (EMI_BASE+0X014) /* CSF�������üĴ��� */ +#define EMI_SDCONF1 (EMI_BASE+0X018) /* SDRAMʱ�����üĴ���1 */ +#define EMI_SDCONF2 (EMI_BASE+0X01C) /* SDRAMʱ�����üĴ���2, SDRAM��ʼ���õ���������Ϣ */ +#define EMI_REMAPCONF (EMI_BASE+0X020) /* Ƭѡ�ռ估��ַӳ��REMAP���üĴ��� */ +#define EMI_NAND_ADDR1 (EMI_BASE+0X100) /* NAND FLASH�ĵ�ַ�Ĵ���1 */ +#define EMI_NAND_COM (EMI_BASE+0X104) /* NAND FLASH�Ŀ����ּĴ��� */ +#define EMI_NAND_STA (EMI_BASE+0X10C) /* NAND FLASH��״̬�Ĵ��� */ +#define EMI_ERR_ADDR1 (EMI_BASE+0X110) /* �����������ĵ�ַ�Ĵ���1 */ +#define EMI_ERR_ADDR2 (EMI_BASE+0X114) /* �����������ĵ�ַ�Ĵ���2 */ +#define EMI_NAND_CONF1 (EMI_BASE+0X118) /* NAND FLASH������������1 */ +#define EMI_NAND_INTR (EMI_BASE+0X11C) /* NAND FLASH�жϼĴ��� */ +#define EMI_NAND_ECC (EMI_BASE+0X120) /* ECCУ����ɼĴ��� */ +#define EMI_NAND_IDLE (EMI_BASE+0X124) /* NAND FLASH���мĴ��� */ +#define EMI_NAND_CONF2 (EMI_BASE+0X128) /* NAND FLASH������������2 */ +#define EMI_NAND_ADDR2 (EMI_BASE+0X12C) /* NAND FLASH�ĵ�ַ�Ĵ���2 */ +#define EMI_NAND_DATA (EMI_BASE+0X200) /* NAND FLASH�����ݼĴ��� */ + + +/* + * DMACģ�� + * ��ַ: 0x11001000 + */ + +#define DMAC_INTSTATUS (DMAC_BASE+0X020) /* DAMC�ж�״̬�Ĵ����� */ +#define DMAC_INTTCSTATUS (DMAC_BASE+0X050) /* DMAC��������ж�״̬�Ĵ��� */ +#define DMAC_INTTCCLEAR (DMAC_BASE+0X060) /* DMAC��������ж�״̬����Ĵ��� */ +#define DMAC_INTERRORSTATUS (DMAC_BASE+0X080) /* DMAC��������ж�״̬�Ĵ��� */ +#define DMAC_INTINTERRCLR (DMAC_BASE+0X090) /* DMAC��������ж�״̬����Ĵ��� */ +#define DMAC_ENBLDCHNS (DMAC_BASE+0X0B0) /* DMACͨ��ʹ��״̬�Ĵ��� */ +#define DMAC_C0SRCADDR (DMAC_BASE+0X000) /* DMAC��0Դ��ַ�Ĵ��� */ +#define DMAC_C0DESTADD (DMAC_BASE+0X004) /* DMAC��0Ŀ�ĵ�ַ�Ĵ��� */ +#define DMAC_C0CONTROL (DMAC_BASE+0X00C) /* DMAC��0���ƼĴ��� */ +#define DMAC_C0CONFIGURATION (DMAC_BASE+0X010) /* DMAC��0���üĴ��� */ +#define DMAC_C0DESCRIPTOR (DMAC_BASE+0X01C) /* DMAC��0������ַ�Ĵ��� */ +#define DMAC_C1SRCADDR (DMAC_BASE+0X100) /* DMAC��1Դ��ַ�Ĵ��� */ +#define DMAC_C1DESTADDR (DMAC_BASE+0X104) /* DMAC��1Ŀ�ĵ�ַ�Ĵ��� */ +#define DMAC_C1CONTROL (DMAC_BASE+0X10C) /* DMAC��1���ƼĴ��� */ +#define DMAC_C1CONFIGURATION (DMAC_BASE+0X110) /* DMAC��1���üĴ��� */ +#define DMAC_C1DESCRIPTOR (DMAC_BASE+0X114) /* DMAC��1������ַ�Ĵ��� */ +#define DMAC_C2SRCADDR (DMAC_BASE+0X200) /* DMAC��2Դ��ַ�Ĵ��� */ +#define DMAC_C2DESTADDR (DMAC_BASE+0X204) /* DMAC��2Ŀ�ĵ�ַ�Ĵ��� */ +#define DMAC_C2CONTROL (DMAC_BASE+0X20C) /* DMAC��2���ƼĴ��� */ +#define DMAC_C2CONFIGURATION (DMAC_BASE+0X210) /* DMAC��2���üĴ��� */ +#define DMAC_C2DESCRIPTOR (DMAC_BASE+0X214) /* DMAC��2������ַ�Ĵ��� */ +#define DMAC_C3SRCADDR (DMAC_BASE+0X300) /* DMAC��3Դ��ַ�Ĵ��� */ +#define DMAC_C3DESTADDR (DMAC_BASE+0X304) /* DMAC��3Ŀ�ĵ�ַ�Ĵ��� */ +#define DMAC_C3CONTROL (DMAC_BASE+0X30C) /* DMAC��3���ƼĴ��� */ +#define DMAC_C3CONFIGURATION (DMAC_BASE+0X310) /* DMAC��3���üĴ��� */ +#define DMAC_C3DESCRIPTOR (DMAC_BASE+0X314) /* DMAC��3������ַ�Ĵ��� */ +#define DMAC_C4SRCADDR (DMAC_BASE+0X400) /* DMAC��4Դ��ַ�Ĵ��� */ +#define DMAC_C4DESTADDR (DMAC_BASE+0X404) /* DMAC��4Ŀ�ĵ�ַ�Ĵ��� */ +#define DMAC_C4CONTROL (DMAC_BASE+0X40C) /* DMAC��4���ƼĴ��� */ +#define DMAC_C4CONFIGURATION (DMAC_BASE+0X410) /* DMAC��4���üĴ��� */ +#define DMAC_C4DESCRIPTOR (DMAC_BASE+0X414) /* DMAC��4������ַ�Ĵ��� */ +#define DMAC_C5SRCADDR (DMAC_BASE+0X500) /* DMAC��5Դ��ַ�Ĵ��� */ +#define DMAC_C5DESTADDR (DMAC_BASE+0X504) /* DMAC��5Ŀ�ĵ�ַ�Ĵ��� */ +#define DMAC_C5CONTROL (DMAC_BASE+0X50C) /* DMAC��5���ƼĴ��� */ +#define DMAC_C5CONFIGURATION (DMAC_BASE+0X510) /* DMAC��5���üĴ��� */ +#define DMAC_C5DESCRIPTOR (DMAC_BASE+0X514) /* DMAC��5������ַ�Ĵ��� */ + + +/* + * LCDCģ�� + * ��ַ: 0x11002000 + */ + +#define LCDC_SSA (LCDC_BASE+0X000) /* ��Ļ��ʼ��ַ�Ĵ��� */ +#define LCDC_SIZE (LCDC_BASE+0X004) /* ��Ļ�ߴ�Ĵ��� */ +#define LCDC_PCR (LCDC_BASE+0X008) /* ������üĴ��� */ +#define LCDC_HCR (LCDC_BASE+0X00C) /* ˮƽ���üĴ��� */ +#define LCDC_VCR (LCDC_BASE+0X010) /* ��ֱ���üĴ��� */ +#define LCDC_PWMR (LCDC_BASE+0X014) /* PWM�Աȶȿ��ƼĴ��� */ +#define LCDC_LECR (LCDC_BASE+0X018) /* ʹ�ܿ��ƼĴ��� */ +#define LCDC_DMACR (LCDC_BASE+0X01C) /* DMA���ƼĴ��� */ +#define LCDC_LCDISREN (LCDC_BASE+0X020) /* �ж�ʹ�ܼĴ��� */ +#define LCDC_LCDISR (LCDC_BASE+0X024) /* �ж�״̬�Ĵ��� */ +#define LCDC_LGPMR (LCDC_BASE+0X040) /* �Ҷȵ�ɫӳ��Ĵ����� (16��32bit�Ĵ���) */ + + +/* + * MACģ�� + * ��ַ: 0x11003000 + */ + +#define MAC_CTRL (MAC_BASE+0X000) /* MAC���ƼĴ��� */ +#define MAC_INTSRC (MAC_BASE+0X004) /* MAC�ж�Դ�Ĵ��� */ +#define MAC_INTMASK (MAC_BASE+0X008) /* MAC�ж����μĴ��� */ +#define MAC_IPGT (MAC_BASE+0X00C) /* ����֡����Ĵ��� */ +#define MAC_IPGR1 (MAC_BASE+0X010) /* �ȴ����ڼĴ��� */ +#define MAC_IPGR2 (MAC_BASE+0X014) /* �ȴ����ڼĴ��� */ +#define MAC_PACKETLEN (MAC_BASE+0X018) /* ֡���ȼĴ��� */ +#define MAC_COLLCONF (MAC_BASE+0X01C) /* ��ײ�ط��Ĵ��� */ +#define MAC_TXBD_NUM (MAC_BASE+0X020) /* �����������Ĵ��� */ +#define MAC_FLOWCTRL (MAC_BASE+0X024) /* ���ؼĴ��� */ +#define MAC_MII_CTRL (MAC_BASE+0X028) /* PHY���ƼĴ��� */ +#define MAC_MII_CMD (MAC_BASE+0X02C) /* PHY����Ĵ��� */ +#define MAC_MII_ADDRESS (MAC_BASE+0X030) /* PHY��ַ�Ĵ��� */ +#define MAC_MII_TXDATA (MAC_BASE+0X034) /* PHYд���ݼĴ��� */ +#define MAC_MII_RXDATA (MAC_BASE+0X038) /* PHY�����ݼĴ��� */ +#define MAC_MII_STATUS (MAC_BASE+0X03C) /* PHY״̬�Ĵ��� */ +#define MAC_ADDR0 (MAC_BASE+0X040) /* MAC��ַ�Ĵ��� */ +#define MAC_ADDR1 (MAC_BASE+0X044) /* MAC��ַ�Ĵ��� */ +#define MAC_HASH0 (MAC_BASE+0X048) /* MAC HASH�Ĵ��� */ +#define MAC_HASH1 (MAC_BASE+0X04C) /* MAC HASH�Ĵ��� */ +#define MAC_TXPAUSE (MAC_BASE+0X050) /* MAC����֡�Ĵ��� */ +#define MAC_TX_BD (MAC_BASE+0X400) +#define MAC_RX_BD (MAC_BASE+0X600) + + +/* + ************************************** + * Error Codes: + * IF SUCCESS RETURN 0, ELSE RETURN OTHER ERROR CODE, + * parameter error return (-33)/E_PAR, + * hardware error reture (-99)/E_HA + ************************************** + */ + +#define E_OK 0 /* Normal completion */ +#define E_SYS (-5) /* System error */ +#define E_NOMEM (-10) /* Insufficient memory */ +#define E_NOSPT (-17) /* Feature not supported */ +#define E_INOSPT (-18) /* Feature not supported by ITRON/FILE specification */ +#define E_RSFN (-20) /* Reserved function code number */ +#define E_RSATR (-24) /* Reserved attribute */ +#define E_PAR (-33) /* Parameter error */ +#define E_ID (-35) /* Invalid ID number */ +#define E_NOEXS (-52) /* Object does not exist */ +#define E_OBJ (-63) /* Invalid object state */ +#define E_MACV (-65) /* Memory access disabled or memory access violation */ +#define E_OACV (-66) /* Object access violation */ +#define E_CTX (-69) /* Context error */ +#define E_QOVR (-73) /* Queuing or nesting overflow */ +#define E_DLT (-81) /* Object being waited for was deleted */ +#define E_TMOUT (-85) /* Polling failure or timeout exceeded */ +#define E_RLWAI (-86) /* WAIT state was forcibly released */ + +#define E_HA (-99) /* HARD WARE ERROR */ + + +/* + ************************************** + * PMU ģ��ʱ�� + ************************************** + */ + +#define CLK_SGPT (1 << 16) +#define CLK_SI2S (1 << 15) +#define CLK_SSMC (1 << 14) +#define CLK_SMAC (1 << 13) +#define CLK_SUSB (1 << 12) +#define CLK_SUART3 (1 << 11) +#define CLK_SUART2 (1 << 10) +#define CLK_SUART1 (1 << 9) +#define CLK_SUART0 (1 << 8) +#define CLK_SSSI (1 << 7) +#define CLK_SAC97 (1 << 6) +#define CLK_SMMCSD (1 << 5) +#define CLK_SEMI (1 << 4) +#define CLK_SDMAC (1 << 3) +#define CLK_SPWM (1 << 2) +#define CLK_SLCDC (1 << 1) +#define CLK_SESRAM (1) + + +/*Interrupt Sources*/ + + +#define INTSRC_RTC 31 +#define INTSRC_DMAC 30 +#define INTSRC_EMI 29 +#define INTSRC_MAC 28 +#define INTSRC_TIMER1 27 +#define INTSRC_TIMER2 26 +#define INTSRC_TIMER3 25 +#define INTSRC_UART0 24 +#define INTSRC_UART1 23 +#define INTSRC_UART2 22 +#define INTSRC_UART3 21 +#define INTSRC_PWM 20 +#define INTSRC_LCDC 19 +#define INTSRC_I2S 18 +#define INTSRC_SSI 17 + +#define INTSRC_USB 15 +#define INTSRC_SMC0 14 +#define INTSRC_SMC1 13 +#define INTSRC_SDIO 12 +#define INTSRC_EXINT10 11 +#define INTSRC_EXINT9 10 +#define INTSRC_EXINT8 9 +#define INTSRC_EXINT7 8 +#define INTSRC_EXINT6 7 +#define INTSRC_EXINT5 6 +#define INTSRC_EXINT4 5 +#define INTSRC_EXINT3 4 +#define INTSRC_EXINT2 3 +#define INTSRC_EXINT1 2 +#define INTSRC_EXINT0 1 +#define INTSRC_NULL 0 + + +/*Sereral useful macros*/ +#define set_plevel(plevel) *(RP)INTC_IPLR = plevel //������ͨ�жϵ����ȼ����ޣ�ֻ�����ȼ����ڴ�ֵ���жϲ���ͨ�� +#define set_int_force(intnum) *(RP)INTC_IFR = (1 << intnum) //��1������ǿ�Ƹ�λ��Ӧ���ж�Դ�����ж��ź� +#define enable_irq(intnum) *(RP)INTC_IER |= (1 << intnum) //��1�������ж�Դ��IRQ �ж��ź� +#define disable_irq( intnum) *(RP)INTC_IER &= ~(1<< intnum) //��0�󣬲������ж�Դ��IRQ �ж��ź� +#define mask_irq(intnum) *(RP)INTC_IMR |= (1 << intnum) //��1�����ζ�Ӧ��IRQ �ж��ź� +#define unmask_irq(intnum) *(RP)INTC_IMR &= ~(1 << intnum) //��0��ͨ����Ӧ��IRQ �ж��ź� +#define mask_all_irq() *(RP)INTC_IMR = 0xFFFFFFFF //���ζ�Ӧ��IRQ �ж��ź� +#define unmask_all_irq() *(RP)INTC_IMR = 0x00000000 //ͨ����Ӧ��IRQ �ж��ź� +#define enable_all_irq() *(RP)INTC_IER = 0XFFFFFFFF //�����ж�Դ��IRQ �ж��ź� +#define disable_all_irq() *(RP)INTC_IER = 0X00000000 //�������ж�Դ��IRQ �ж��ź� +#define InitInt() do{mask_all_irq(); enable_all_irq();}while(0) + +/* + ************************************** + * ���г������õ���Typedef + ************************************** + */ + +typedef char S8; /* signed 8-bit integer */ +typedef short S16; /* signed 16-bit integer */ +typedef long S32; /* signed 32-bit integer */ +typedef unsigned char U8; /* unsigned 8-bit integer */ +typedef unsigned short U16; /* unsigned 16-bit integer */ +typedef unsigned long U32; /* unsigned 32-bit integer */ + +typedef volatile U32 * RP; +typedef volatile U16 * RP16; +typedef volatile U8 * RP8; + +typedef void *VP; /* pointer to an unpredictable data type */ +typedef void (*FP)(); /* program start address */ + +#ifndef _BOOL_TYPE_ +#define _BOOL_TYPE_ +typedef int BOOL; /* Boolean value. TRUE (1) or FALSE (0). */ +#endif + +typedef int ER; /* Error code. A signed integer. */ + +/** + * IO definitions + * + * define access restrictions to peripheral registers + */ + +#define __I volatile const /*!< defines 'read only' permissions */ +#define __O volatile /*!< defines 'write only' permissions */ +#define __IO volatile /*!< defines 'read / write' permissions */ +#define __iomem volatile + + +/*Macros for debug*/ + +#define EOUT(fmt,...) \ + do \ + { \ + rt_kprintf("EOUT:(%s:%i) ",__FILE__,__LINE__); \ + rt_kprintf(fmt,##__VA_ARGS__); \ + }while(0) + +#define RT_DEBUG +#ifdef RT_DEBUG + #define DBOUT(fmt,...) \ + do \ + { \ + rt_kprintf("DBOUT:(%s:%i) ",__FILE__,__LINE__); \ + rt_kprintf(fmt,##__VA_ARGS__); \ + }while(0) +#else + #define DBOUT(fmt,...) \ + do{}while(0) +#endif + +#ifdef RT_DEBUG + #define ASSERT(arg) \ + if((arg) == 0) \ + { \ + while(1) \ + { \ + rt_kprintf("have a assert failure\n"); \ + } \ + } +#else + #define ASSERT(arg) \ + do \ + { \ + }while(0) +#endif + + +#define write_reg(reg,value) \ + do \ + { \ + *(RP)(reg) = value; \ + }while(0) + +#define read_reg(reg) (*(RP)reg) + + +struct rt_hw_register +{ + rt_uint32_t r0; + rt_uint32_t r1; + rt_uint32_t r2; + rt_uint32_t r3; + rt_uint32_t r4; + rt_uint32_t r5; + rt_uint32_t r6; + rt_uint32_t r7; + rt_uint32_t r8; + rt_uint32_t r9; + rt_uint32_t r10; + rt_uint32_t fp; + rt_uint32_t ip; + rt_uint32_t sp; + rt_uint32_t lr; + rt_uint32_t pc; + rt_uint32_t cpsr; + rt_uint32_t ORIG_r0; +}; + + +/*@}*/ + +#endif diff --git a/libcpu/arm/sep4020/serial.c b/libcpu/arm/sep4020/serial.c index c9dbc3c025..728f7dc1ed 100644 --- a/libcpu/arm/sep4020/serial.c +++ b/libcpu/arm/sep4020/serial.c @@ -1,282 +1,282 @@ -/*
- * File : serial.c
- * This file is part of RT-Thread RTOS
- * COPYRIGHT (C) 2006, RT-Thread Development Team
- *
- * The license and distribution terms for this file may be
- * found in the file LICENSE in this distribution or at
- * http://openlab.rt-thread.com/license/LICENSE
- *
- * Change Logs:
- * Date Author Notes
- * 2006-03-13 Bernard first version
- * 2009-04-20 yi.qiu modified according bernard's stm32 version
- * 2010-10-6 wangmeng added sep4020 surpport
- */
-#include <rtthread.h>
-#include <rthw.h>
-#include "serial.h"
-
-/**
- * @addtogroup SEP4020
- */
-/*@{*/
-
-/* RT-Thread Device Interface */
-/**
- * This function initializes serial
- */
-static rt_err_t rt_serial_init (rt_device_t dev)
-{
- struct serial_device* uart = (struct serial_device*) dev->user_data;
-
- if (!(dev->flag & RT_DEVICE_FLAG_ACTIVATED))
- {
-
- if (dev->flag & RT_DEVICE_FLAG_INT_RX)
- {
- rt_memset(uart->int_rx->rx_buffer, 0,
- sizeof(uart->int_rx->rx_buffer));
- uart->int_rx->read_index = uart->int_rx->save_index = 0;
- }
-
- if (dev->flag & RT_DEVICE_FLAG_INT_TX)
- {
- rt_memset(uart->int_tx->tx_buffer, 0,
- sizeof(uart->int_tx->tx_buffer));
- uart->int_tx->write_index = uart->int_tx->save_index = 0;
- }
-
- dev->flag |= RT_DEVICE_FLAG_ACTIVATED;
- }
-
- return RT_EOK;
-}
-
-/* save a char to serial buffer */
-static void rt_serial_savechar(struct serial_device* uart, char ch)
-{
- rt_base_t level;
-
- /* disable interrupt */
- level = rt_hw_interrupt_disable();
-
- uart->int_rx->rx_buffer[uart->int_rx->save_index] = ch;
- uart->int_rx->save_index ++;
- if (uart->int_rx->save_index >= UART_RX_BUFFER_SIZE)
- uart->int_rx->save_index = 0;
-
- /* if the next position is read index, discard this 'read char' */
- if (uart->int_rx->save_index == uart->int_rx->read_index)
- {
- uart->int_rx->read_index ++;
- if (uart->int_rx->read_index >= UART_RX_BUFFER_SIZE)
- uart->int_rx->read_index = 0;
- }
-
- /* enable interrupt */
- rt_hw_interrupt_enable(level);
-}
-
-static rt_err_t rt_serial_open(rt_device_t dev, rt_uint16_t oflag)
-{
- RT_ASSERT(dev != RT_NULL);
- return RT_EOK;
-}
-
-static rt_err_t rt_serial_close(rt_device_t dev)
-{
- RT_ASSERT(dev != RT_NULL);
- return RT_EOK;
-}
-
-static rt_size_t rt_serial_read (rt_device_t dev, rt_off_t pos, void* buffer, rt_size_t size)
-{
- rt_uint8_t* ptr;
- rt_err_t err_code;
- struct serial_device* uart;
-
- ptr = buffer;
- err_code = RT_EOK;
- uart = (struct serial_device*)dev->user_data;
-
- if (dev->flag & RT_DEVICE_FLAG_INT_RX)
- {
- rt_base_t level;
-
- /* interrupt mode Rx */
- while (size)
- {
- if (uart->int_rx->read_index != uart->int_rx->save_index)
- {
- *ptr++ = uart->int_rx->rx_buffer[uart->int_rx->read_index];
- size --;
-
- /* disable interrupt */
- level = rt_hw_interrupt_disable();
-
- uart->int_rx->read_index ++;
- if (uart->int_rx->read_index >= UART_RX_BUFFER_SIZE)
- uart->int_rx->read_index = 0;
-
- /* enable interrupt */
- rt_hw_interrupt_enable(level);
- }
- else
- {
- /* set error code */
- err_code = -RT_EEMPTY;
- break;
- }
- }
- }
- else
- {
- /* polling mode */
- while ((rt_uint32_t)ptr - (rt_uint32_t)buffer < size)
- {
- while (uart->uart_device->lsr & USTAT_RCV_READY)
- {
- *ptr = uart->uart_device->dlbl_fifo.txfifo & 0xff;
- ptr ++;
- }
- }
- }
-
- /* set error code */
- rt_set_errno(err_code);
- return (rt_uint32_t)ptr - (rt_uint32_t)buffer;
-}
-
-static rt_size_t rt_serial_write (rt_device_t dev, rt_off_t pos, const void* buffer, rt_size_t size)
-{
- rt_uint8_t* ptr;
- rt_err_t err_code;
- struct serial_device* uart;
-
- err_code = RT_EOK;
- ptr = (rt_uint8_t*)buffer;
- uart = (struct serial_device*)dev->user_data;
-
- if (dev->flag & RT_DEVICE_FLAG_INT_TX)
- {
- /* interrupt mode Tx */
- while (uart->int_tx->save_index != uart->int_tx->write_index)
- {
- /* save on tx buffer */
- uart->int_tx->tx_buffer[uart->int_tx->save_index] = *ptr++;
-
- -- size;
-
- /* move to next position */
- uart->int_tx->save_index ++;
-
- /* wrap save index */
- if (uart->int_tx->save_index >= UART_TX_BUFFER_SIZE)
- uart->int_tx->save_index = 0;
- }
-
- /* set error code */
- if (size > 0)
- err_code = -RT_EFULL;
- }
- else
- {
- /* polling mode */
- while (size)
- {
- /*
- * to be polite with serial console add a line feed
- * to the carriage return character
- */
- if (*ptr == '\n' && (dev->flag & RT_DEVICE_FLAG_STREAM))
- {
- while (!(uart->uart_device->lsr & USTAT_TXB_EMPTY));
- uart->uart_device->dlbl_fifo.txfifo = '\r';
- }
-
- while (!(uart->uart_device->lsr & USTAT_TXB_EMPTY));
- uart->uart_device->dlbl_fifo.txfifo = (*ptr & 0x1FF);
-
- ++ptr; --size;
- }
- }
-
- /* set error code */
- rt_set_errno(err_code);
-
- return (rt_uint32_t)ptr - (rt_uint32_t)buffer;
-}
-
-static rt_err_t rt_serial_control (rt_device_t dev, rt_uint8_t cmd, void *args)
-{
- RT_ASSERT(dev != RT_NULL);
-
- switch (cmd)
- {
- case RT_DEVICE_CTRL_SUSPEND:
- /* suspend device */
- dev->flag |= RT_DEVICE_FLAG_SUSPENDED;
- break;
-
- case RT_DEVICE_CTRL_RESUME:
- /* resume device */
- dev->flag &= ~RT_DEVICE_FLAG_SUSPENDED;
- break;
- }
-
- return RT_EOK;
-}
-
-/*
- * serial register
- */
-rt_err_t rt_hw_serial_register(rt_device_t device, const char* name, rt_uint32_t flag, struct serial_device *serial)
-{
- RT_ASSERT(device != RT_NULL);
-
- device->type = RT_Device_Class_Char;
- device->rx_indicate = RT_NULL;
- device->tx_complete = RT_NULL;
- device->init = rt_serial_init;
- device->open = rt_serial_open;
- device->close = rt_serial_close;
- device->read = rt_serial_read;
- device->write = rt_serial_write;
- device->control = rt_serial_control;
- device->user_data = serial;
-
- /* register a character device */
- return rt_device_register(device, name, RT_DEVICE_FLAG_RDWR | flag);
-}
-
-/* ISR for serial interrupt */
-void rt_hw_serial_isr(rt_device_t device)
-{
- struct serial_device* uart = (struct serial_device*) device->user_data;
-
- /* interrupt mode receive */
- RT_ASSERT(device->flag & RT_DEVICE_FLAG_INT_RX);
-
- /* save on rx buffer */
- while (uart->uart_device->lsr & USTAT_RCV_READY)
- {
- rt_serial_savechar(uart, uart->uart_device->dlbl_fifo.rxfifo & 0xff);
- }
-
- /* invoke callback */
- if (device->rx_indicate != RT_NULL)
- {
- rt_size_t rx_length;
-
- /* get rx length */
- rx_length = uart->int_rx->read_index > uart->int_rx->save_index ?
- UART_RX_BUFFER_SIZE - uart->int_rx->read_index + uart->int_rx->save_index :
- uart->int_rx->save_index - uart->int_rx->read_index;
-
- device->rx_indicate(device, rx_length);
- }
-}
-
-/*@}*/
-
+/* + * File : serial.c + * This file is part of RT-Thread RTOS + * COPYRIGHT (C) 2006, RT-Thread Development Team + * + * The license and distribution terms for this file may be + * found in the file LICENSE in this distribution or at + * http://openlab.rt-thread.com/license/LICENSE + * + * Change Logs: + * Date Author Notes + * 2006-03-13 Bernard first version + * 2009-04-20 yi.qiu modified according bernard's stm32 version + * 2010-10-6 wangmeng added sep4020 surpport + */ +#include <rtthread.h> +#include <rthw.h> +#include "serial.h" + +/** + * @addtogroup SEP4020 + */ +/*@{*/ + +/* RT-Thread Device Interface */ +/** + * This function initializes serial + */ +static rt_err_t rt_serial_init (rt_device_t dev) +{ + struct serial_device* uart = (struct serial_device*) dev->user_data; + + if (!(dev->flag & RT_DEVICE_FLAG_ACTIVATED)) + { + + if (dev->flag & RT_DEVICE_FLAG_INT_RX) + { + rt_memset(uart->int_rx->rx_buffer, 0, + sizeof(uart->int_rx->rx_buffer)); + uart->int_rx->read_index = uart->int_rx->save_index = 0; + } + + if (dev->flag & RT_DEVICE_FLAG_INT_TX) + { + rt_memset(uart->int_tx->tx_buffer, 0, + sizeof(uart->int_tx->tx_buffer)); + uart->int_tx->write_index = uart->int_tx->save_index = 0; + } + + dev->flag |= RT_DEVICE_FLAG_ACTIVATED; + } + + return RT_EOK; +} + +/* save a char to serial buffer */ +static void rt_serial_savechar(struct serial_device* uart, char ch) +{ + rt_base_t level; + + /* disable interrupt */ + level = rt_hw_interrupt_disable(); + + uart->int_rx->rx_buffer[uart->int_rx->save_index] = ch; + uart->int_rx->save_index ++; + if (uart->int_rx->save_index >= UART_RX_BUFFER_SIZE) + uart->int_rx->save_index = 0; + + /* if the next position is read index, discard this 'read char' */ + if (uart->int_rx->save_index == uart->int_rx->read_index) + { + uart->int_rx->read_index ++; + if (uart->int_rx->read_index >= UART_RX_BUFFER_SIZE) + uart->int_rx->read_index = 0; + } + + /* enable interrupt */ + rt_hw_interrupt_enable(level); +} + +static rt_err_t rt_serial_open(rt_device_t dev, rt_uint16_t oflag) +{ + RT_ASSERT(dev != RT_NULL); + return RT_EOK; +} + +static rt_err_t rt_serial_close(rt_device_t dev) +{ + RT_ASSERT(dev != RT_NULL); + return RT_EOK; +} + +static rt_size_t rt_serial_read (rt_device_t dev, rt_off_t pos, void* buffer, rt_size_t size) +{ + rt_uint8_t* ptr; + rt_err_t err_code; + struct serial_device* uart; + + ptr = buffer; + err_code = RT_EOK; + uart = (struct serial_device*)dev->user_data; + + if (dev->flag & RT_DEVICE_FLAG_INT_RX) + { + rt_base_t level; + + /* interrupt mode Rx */ + while (size) + { + if (uart->int_rx->read_index != uart->int_rx->save_index) + { + *ptr++ = uart->int_rx->rx_buffer[uart->int_rx->read_index]; + size --; + + /* disable interrupt */ + level = rt_hw_interrupt_disable(); + + uart->int_rx->read_index ++; + if (uart->int_rx->read_index >= UART_RX_BUFFER_SIZE) + uart->int_rx->read_index = 0; + + /* enable interrupt */ + rt_hw_interrupt_enable(level); + } + else + { + /* set error code */ + err_code = -RT_EEMPTY; + break; + } + } + } + else + { + /* polling mode */ + while ((rt_uint32_t)ptr - (rt_uint32_t)buffer < size) + { + while (uart->uart_device->lsr & USTAT_RCV_READY) + { + *ptr = uart->uart_device->dlbl_fifo.txfifo & 0xff; + ptr ++; + } + } + } + + /* set error code */ + rt_set_errno(err_code); + return (rt_uint32_t)ptr - (rt_uint32_t)buffer; +} + +static rt_size_t rt_serial_write (rt_device_t dev, rt_off_t pos, const void* buffer, rt_size_t size) +{ + rt_uint8_t* ptr; + rt_err_t err_code; + struct serial_device* uart; + + err_code = RT_EOK; + ptr = (rt_uint8_t*)buffer; + uart = (struct serial_device*)dev->user_data; + + if (dev->flag & RT_DEVICE_FLAG_INT_TX) + { + /* interrupt mode Tx */ + while (uart->int_tx->save_index != uart->int_tx->write_index) + { + /* save on tx buffer */ + uart->int_tx->tx_buffer[uart->int_tx->save_index] = *ptr++; + + -- size; + + /* move to next position */ + uart->int_tx->save_index ++; + + /* wrap save index */ + if (uart->int_tx->save_index >= UART_TX_BUFFER_SIZE) + uart->int_tx->save_index = 0; + } + + /* set error code */ + if (size > 0) + err_code = -RT_EFULL; + } + else + { + /* polling mode */ + while (size) + { + /* + * to be polite with serial console add a line feed + * to the carriage return character + */ + if (*ptr == '\n' && (dev->flag & RT_DEVICE_FLAG_STREAM)) + { + while (!(uart->uart_device->lsr & USTAT_TXB_EMPTY)); + uart->uart_device->dlbl_fifo.txfifo = '\r'; + } + + while (!(uart->uart_device->lsr & USTAT_TXB_EMPTY)); + uart->uart_device->dlbl_fifo.txfifo = (*ptr & 0x1FF); + + ++ptr; --size; + } + } + + /* set error code */ + rt_set_errno(err_code); + + return (rt_uint32_t)ptr - (rt_uint32_t)buffer; +} + +static rt_err_t rt_serial_control (rt_device_t dev, rt_uint8_t cmd, void *args) +{ + RT_ASSERT(dev != RT_NULL); + + switch (cmd) + { + case RT_DEVICE_CTRL_SUSPEND: + /* suspend device */ + dev->flag |= RT_DEVICE_FLAG_SUSPENDED; + break; + + case RT_DEVICE_CTRL_RESUME: + /* resume device */ + dev->flag &= ~RT_DEVICE_FLAG_SUSPENDED; + break; + } + + return RT_EOK; +} + +/* + * serial register + */ +rt_err_t rt_hw_serial_register(rt_device_t device, const char* name, rt_uint32_t flag, struct serial_device *serial) +{ + RT_ASSERT(device != RT_NULL); + + device->type = RT_Device_Class_Char; + device->rx_indicate = RT_NULL; + device->tx_complete = RT_NULL; + device->init = rt_serial_init; + device->open = rt_serial_open; + device->close = rt_serial_close; + device->read = rt_serial_read; + device->write = rt_serial_write; + device->control = rt_serial_control; + device->user_data = serial; + + /* register a character device */ + return rt_device_register(device, name, RT_DEVICE_FLAG_RDWR | flag); +} + +/* ISR for serial interrupt */ +void rt_hw_serial_isr(rt_device_t device) +{ + struct serial_device* uart = (struct serial_device*) device->user_data; + + /* interrupt mode receive */ + RT_ASSERT(device->flag & RT_DEVICE_FLAG_INT_RX); + + /* save on rx buffer */ + while (uart->uart_device->lsr & USTAT_RCV_READY) + { + rt_serial_savechar(uart, uart->uart_device->dlbl_fifo.rxfifo & 0xff); + } + + /* invoke callback */ + if (device->rx_indicate != RT_NULL) + { + rt_size_t rx_length; + + /* get rx length */ + rx_length = uart->int_rx->read_index > uart->int_rx->save_index ? + UART_RX_BUFFER_SIZE - uart->int_rx->read_index + uart->int_rx->save_index : + uart->int_rx->save_index - uart->int_rx->read_index; + + device->rx_indicate(device, rx_length); + } +} + +/*@}*/ + diff --git a/libcpu/arm/sep4020/serial.h b/libcpu/arm/sep4020/serial.h index f903c1e1a5..f0357aacfb 100644 --- a/libcpu/arm/sep4020/serial.h +++ b/libcpu/arm/sep4020/serial.h @@ -1,90 +1,90 @@ -/*
- * File : serial.c
- * This file is part of RT-Thread RTOS
- * COPYRIGHT (C) 2006, RT-Thread Development Team
- *
- * The license and distribution terms for this file may be
- * found in the file LICENSE in this distribution or at
- * http://openlab.rt-thread.com/license/LICENSE
- *
- * Change Logs:
- * Date Author Notes
- * 2006-03-13 Bernard first version
- * 2009-04-20 yi.qiu modified according bernard's stm32 version
- * 2010-10-6 wangmeng added sep4020 surpport
- */
-
-#ifndef __SERIAL_H__
-#define __SERIAL_H__
-
-#include <sep4020.h>
-
-#define USTAT_RCV_READY 0x01 /* receive data ready */
-#define USTAT_TXB_EMPTY 0x40 /* tx buffer empty */
-#define BPS 115200 /* serial baudrate */
-
-#define UART_RX_BUFFER_SIZE 64
-#define UART_TX_BUFFER_SIZE 64
-
-/*For sep4020's uart have several secondary function*/
-/*we use union to decribe it*/
-
-union dlbl_fifo
-{
- rt_uint32_t dlbl;
- rt_uint32_t rxfifo;
- rt_uint32_t txfifo;
-};
-
-union dlbh_ier
-{
- rt_uint32_t dlbh;
- rt_uint32_t ier;
-};
-
-union iir_fcr
-{
- rt_uint32_t iir;
- rt_uint32_t fcr;
-};
-
-struct serial_int_rx
-{
- rt_uint8_t rx_buffer[UART_RX_BUFFER_SIZE];
- rt_uint32_t read_index, save_index;
-};
-
-struct serial_int_tx
-{
- rt_uint8_t tx_buffer[UART_TX_BUFFER_SIZE];
- rt_uint32_t write_index, save_index;
-};
-
-typedef struct uartport
-{
- union dlbl_fifo dlbl_fifo;
- union dlbh_ier dlbh_ier;
- union iir_fcr iir_fcr;
- rt_uint32_t lcr;
- rt_uint32_t mcr;
- rt_uint32_t lsr;
- rt_uint32_t msr;
-}uartport;
-
-struct serial_device
-{
- uartport* uart_device;
-
- /* rx structure */
- struct serial_int_rx* int_rx;
-
- /* tx structure */
- struct serial_int_tx* int_tx;
-};
-
-rt_err_t rt_hw_serial_register(rt_device_t device, const char* name, rt_uint32_t flag, struct serial_device *serial);
-
-void rt_hw_serial_isr(rt_device_t device);
-
-
-#endif
+/* + * File : serial.c + * This file is part of RT-Thread RTOS + * COPYRIGHT (C) 2006, RT-Thread Development Team + * + * The license and distribution terms for this file may be + * found in the file LICENSE in this distribution or at + * http://openlab.rt-thread.com/license/LICENSE + * + * Change Logs: + * Date Author Notes + * 2006-03-13 Bernard first version + * 2009-04-20 yi.qiu modified according bernard's stm32 version + * 2010-10-6 wangmeng added sep4020 surpport + */ + +#ifndef __SERIAL_H__ +#define __SERIAL_H__ + +#include <sep4020.h> + +#define USTAT_RCV_READY 0x01 /* receive data ready */ +#define USTAT_TXB_EMPTY 0x40 /* tx buffer empty */ +#define BPS 115200 /* serial baudrate */ + +#define UART_RX_BUFFER_SIZE 64 +#define UART_TX_BUFFER_SIZE 64 + +/*For sep4020's uart have several secondary function*/ +/*we use union to decribe it*/ + +union dlbl_fifo +{ + rt_uint32_t dlbl; + rt_uint32_t rxfifo; + rt_uint32_t txfifo; +}; + +union dlbh_ier +{ + rt_uint32_t dlbh; + rt_uint32_t ier; +}; + +union iir_fcr +{ + rt_uint32_t iir; + rt_uint32_t fcr; +}; + +struct serial_int_rx +{ + rt_uint8_t rx_buffer[UART_RX_BUFFER_SIZE]; + rt_uint32_t read_index, save_index; +}; + +struct serial_int_tx +{ + rt_uint8_t tx_buffer[UART_TX_BUFFER_SIZE]; + rt_uint32_t write_index, save_index; +}; + +typedef struct uartport +{ + union dlbl_fifo dlbl_fifo; + union dlbh_ier dlbh_ier; + union iir_fcr iir_fcr; + rt_uint32_t lcr; + rt_uint32_t mcr; + rt_uint32_t lsr; + rt_uint32_t msr; +}uartport; + +struct serial_device +{ + uartport* uart_device; + + /* rx structure */ + struct serial_int_rx* int_rx; + + /* tx structure */ + struct serial_int_tx* int_tx; +}; + +rt_err_t rt_hw_serial_register(rt_device_t device, const char* name, rt_uint32_t flag, struct serial_device *serial); + +void rt_hw_serial_isr(rt_device_t device); + + +#endif diff --git a/libcpu/arm/sep4020/start_rvds.S b/libcpu/arm/sep4020/start_rvds.S index bb4d20595c..bf5431e03c 100644 --- a/libcpu/arm/sep4020/start_rvds.S +++ b/libcpu/arm/sep4020/start_rvds.S @@ -1,385 +1,385 @@ -;==============================================================================================
-; star_rvds.s for Keil MDK 4.10
-;
-; SEP4020 start up code
-;
-; Change Logs:
-; Date Author Notes
-; 2010-03-17 zchong
-;=============================================================================================
-
-PMU_PLTR EQU 0x10001000 ; PLL���ȶ�����ʱ��
-PMU_PMCR EQU 0x10001004 ; ϵͳ��ʱ��PLL�Ŀ��ƼĴ���
-PMU_PUCR EQU 0x10001008 ; USBʱ��PLL�Ŀ��ƼĴ���
-PMU_PCSR EQU 0x1000100C ; �ڲ�ģ��ʱ��Դ�����Ŀ��ƼĴ���
-PMU_PDSLOW EQU 0x10001010 ; SLOW״̬��ʱ�ӵķ�Ƶ����
-PMU_PMDR EQU 0x10001014 ; оƬ����ģʽ�Ĵ���
-PMU_RCTR EQU 0x10001018 ; Reset���ƼĴ���
-PMU_CLRWAKUP EQU 0x1000101C ; WakeUp����Ĵ���
-
-RTC_CTR EQU 0x1000200C ; RTC���ƼĴ���
-
-INTC_IER EQU 0x10000000 ; IRQ�ж������Ĵ���
-INTC_IMR EQU 0x10000008 ; IRQ�ж����μĴ���
-INTC_IFSR EQU 0x10000030 ; IRQ�ж�����״̬�Ĵ���
-INTC_FIER EQU 0x100000C0 ; FIQ�ж������Ĵ���
-INTC_FIMR EQU 0x100000C4 ; FIQ�ж����μĴ���
-
-EMI_CSACONF EQU 0x11000000 ; CSA�������üĴ���
-EMI_CSECONF EQU 0x11000010 ; CSE�������üĴ���
-EMI_CSFCONF EQU 0x11000014 ; CSF�������üĴ���
-EMI_SDCONF1 EQU 0x11000018 ; SDRAMʱ�����üĴ���1
-EMI_SDCONF2 EQU 0x1100001C ; SDRAMʱ�����üĴ���2, SDRAM��ʼ���õ���������Ϣ
-EMI_REMAPCONF EQU 0x11000020 ; Ƭѡ�ռ估��ַӳ��REMAP���üĴ���
-
-Mode_USR EQU 0x10
-Mode_FIQ EQU 0x11
-Mode_IRQ EQU 0x12
-Mode_SVC EQU 0x13
-Mode_ABT EQU 0x17
-Mode_UND EQU 0x1B
-Mode_SYS EQU 0x1F
-
-I_Bit EQU 0x80 ; when I bit is set, IRQ is disabled
-F_Bit EQU 0x40 ; when F bit is set, FIQ is disabled
-NOINT EQU 0xc0
-MASK_MODE EQU 0x0000003F
-MODE_SVC32 EQU 0x00000013
-
-; Internal Memory Base Addresses
-FLASH_BASE EQU 0x20000000
-RAM_BASE EQU 0x04000000
-SDRAM_BASE EQU 0x30000000
-
-; Stack
-Unused_Stack_Size EQU 0x00000100
-Svc_Stack_Size EQU 0x00001000
-Abt_Stack_Size EQU 0x00000000
-Fiq_Stack_Size EQU 0x00000000
-Irq_Stack_Size EQU 0x00001000
-Usr_Stack_Size EQU 0x00000000
-
-;SVC STACK
- AREA STACK, NOINIT, READWRITE, ALIGN=3
-Svc_Stack SPACE Svc_Stack_Size
-__initial_sp
-Svc_Stack_Top
-
-;IRQ STACK
- AREA STACK, NOINIT, READWRITE, ALIGN=3
-Irq_Stack SPACE Irq_Stack_Size
-Irq_Stack_Top
-
-;UNUSED STACK
- AREA STACK, NOINIT, READWRITE, ALIGN=3
-Unused_Stack SPACE Unused_Stack_Size
-Unused_Stack_Top
-
-
-; Heap
-Heap_Size EQU 0x0000100
-
- AREA HEAP, NOINIT, READWRITE, ALIGN=3
- EXPORT Heap_Mem
-__heap_base
-Heap_Mem SPACE Heap_Size
-__heap_limit
-
- PRESERVE8
-
-; Area Definition and Entry Point
-; Startup Code must be linked first at Address at which it expects to run.
-
- AREA RESET, CODE, READONLY
- ARM
-
-; Exception Vectors
-; Mapped to Address 0.
-; Absolute addressing mode must be used.
-; Dummy Handlers are implemented as infinite loops which can be modified.
- EXPORT Entry_Point
-Entry_Point
-Vectors LDR PC,Reset_Addr
- LDR PC,Undef_Addr
- LDR PC,SWI_Addr
- LDR PC,PAbt_Addr
- LDR PC,DAbt_Addr
- NOP ; Reserved Vector
- LDR PC,IRQ_Addr
- LDR PC,FIQ_Addr
-
-Reset_Addr DCD Reset_Handler
-Undef_Addr DCD Undef_Handler
-SWI_Addr DCD SWI_Handler
-PAbt_Addr DCD PAbt_Handler
-DAbt_Addr DCD DAbt_Handler
- DCD 0 ; Reserved Address
-IRQ_Addr DCD IRQ_Handler
-FIQ_Addr DCD FIQ_Handler
-
-Undef_Handler B Undef_Handler
-SWI_Handler B SWI_Handler
-PAbt_Handler B Abort_Handler
-DAbt_Handler B Abort_Handler
-FIQ_Handler B FIQ_Handler
-
-Abort_Handler PROC
- ARM
- EXPORT Abort_Handler
-DeadLoop BHI DeadLoop ; Abort happened in irq mode, halt system.
- ENDP
-
-
-; Reset Handler
- ;IMPORT __user_initial_stackheap
- EXPORT Reset_Handler
-Reset_Handler
-
-;****************************************************************
-;* Shutdown watchdog
-;****************************************************************
- LDR R0,=RTC_CTR
- LDR R1,=0x0
- STR R1,[R0]
-
-;****************************************************************
-;* shutdown interrupts
-;****************************************************************
- MRS R0, CPSR
- BIC R0, R0, #MASK_MODE
- ORR R0, R0, #MODE_SVC32
- ORR R0, R0, #I_Bit
- ORR R0, R0, #F_Bit
- MSR CPSR_c, r0
-
- LDR R0,=INTC_IER
- LDR R1,=0x0
- STR R1,[R0]
- LDR R0,=INTC_IMR
- LDR R1,=0xFFFFFFFF
- STR R1,[R0]
-
- LDR R0,=INTC_FIER
- LDR R1,=0x0
- STR R1,[R0]
- LDR R0,=INTC_FIMR
- LDR R1,=0x0F
- STR R1,[R0]
-
-;****************************************************************
-;* Initialize Stack Pointer
-;****************************************************************
-
- LDR SP, =Svc_Stack_Top ;init SP_svc
-
- MOV R4, #0xD2 ;chmod to irq and init SP_irq
- MSR cpsr_c, R4
- LDR SP, =Irq_Stack_Top
-
- MOV R4, #0XD1 ;chomod to fiq and init SP_fiq
- MSR cpsr_c, R4
- LDR SP, =Unused_Stack_Top
-
- MOV R4, #0XD7 ;chomod to abt and init SP_ABT
- MSR cpsr_c, R4
- LDR SP, =Unused_Stack_Top
-
- MOV R4, #0XDB ;chomod to undf and init SP_UNDF
- MSR cpsr_c, R4
- LDR SP, =Unused_Stack_Top
-
- ;chomod to abt and init SP_sys
- MOV R4, #0xDF ;all interrupts disabled
- MSR cpsr_c, R4 ;SYSTEM mode, @32-bit code mode
- LDR SP, =Unused_Stack_Top
-
- MOV R4, #0XD3 ;chmod to svc modle, CPSR IRQ bit is disable
- MSR cpsr_c, R4
-
-
-
-;****************************************************************
-;* Initialize PMU & System Clock
-;****************************************************************
-
- LDR R4, =PMU_PCSR ; ������ģ��ʱ��
- LDR R5, =0x0001ffff
- STR R5, [ R4 ]
-
- LDR R4, =PMU_PLTR ; ����PLL�ȶ�����ʱ��Ϊ����ֵ50us*100M.
- LDR R5, =0x00fa00fa
- STR R5, [ R4 ]
-
- LDR R4, =PMU_PMDR ; ��SLOWģʽ����NORMALģʽ
- LDR R5, =0x00000001
- STR R5, [ R4 ]
-
- LDR R4, =PMU_PMCR ; ����ϵͳʱ��Ϊ80MHz
- LDR R5, =0x00004009 ; 400b -- 88M
- STR R5, [ R4 ]
-
- ;PMU_PMCR�Ĵ�����15λ��Ҫ�дӵ͵��ߵķ�ת�����ܴ���PLL��ʱ������
- LDR R4, =PMU_PMCR
- LDR R5, =0x0000c009
- STR R5, [ R4 ]
-
-;****************************************************************
-;* ��ʼ��EMI
-;****************************************************************
-
- IF :DEF:INIT_EMI
-
- LDR R4, =EMI_CSACONF ; CSAƬѡʱ���������
- LDR R5, =0x08a6a6a1
- STR R5, [ R4 ]
-
- LDR R4, =EMI_CSECONF ; CSEƬѡʱ���������,�������
- LDR R5, =0x8cfffff1
- STR R5, [ R4 ]
-
- LDR R4, =EMI_SDCONF1 ; SDRAM��������1
- LDR R5, =0x1E104177
- STR R5, [ R4 ]
-
- LDR R4, =EMI_SDCONF2 ; SDRAM��������2
- LDR R5, =0x80001860
- STR R5, [ R4 ]
-
- ENDIF
-
-; Copy Exception Vectors to Internal RAM
-
- IF :DEF:RAM_INTVEC
-
- ADR R8, Vectors ; Source
- LDR R9, =RAM_BASE ; Destination
- LDMIA R8!, {R0-R7} ; Load Vectors
- STMIA R9!, {R0-R7} ; Store Vectors
- LDMIA R8!, {R0-R7} ; Load Handler Addresses
- STMIA R9!, {R0-R7} ; Store Handler Addresses
-
- ENDIF
-
-; Remap on-chip RAM to address 0
-
- IF :DEF:REMAP
-
- LDR R0, =EMI_REMAPCONF
- IF :DEF:RAM_INTVEC
- MOV R1, #0x80000000
- ELSE
- MOV R1, #0x0000000b
- ENDIF
- STR R1, [R0, #0] ; Remap
-
- ENDIF
-
-;***************************************************************
-;* Open irq interrupt
-;***************************************************************
-
- MRS R4, cpsr
- BIC R4, R4, #0x80 ; set bit7 to zero
- MSR cpsr_c, R4
-
-; Enter the C code
- IMPORT __main
- LDR R0,=__main
- BX R0
-
-
- IMPORT rt_interrupt_enter
- IMPORT rt_interrupt_leave
- IMPORT rt_thread_switch_interrupt_flag
- IMPORT rt_interrupt_from_thread
- IMPORT rt_interrupt_to_thread
- IMPORT rt_hw_trap_irq
-
-IRQ_Handler PROC
- EXPORT IRQ_Handler
- STMFD sp!, {r0-r12,lr}
- BL rt_interrupt_enter
- BL rt_hw_trap_irq
- BL rt_interrupt_leave
-
- ; if rt_thread_switch_interrupt_flag set, jump to
- ; rt_hw_context_switch_interrupt_do and don't return
- LDR r0, =rt_thread_switch_interrupt_flag
- LDR r1, [r0]
- CMP r1, #1
- BEQ rt_hw_context_switch_interrupt_do
-
- LDMFD sp!, {r0-r12,lr}
- SUBS pc, lr, #4
- ENDP
-
-; /*
-; * void rt_hw_context_switch_interrupt_do(rt_base_t flag)
-; */
-rt_hw_context_switch_interrupt_do PROC
- EXPORT rt_hw_context_switch_interrupt_do
- MOV r1, #0 ; clear flag
- STR r1, [r0]
-
- LDMFD sp!, {r0-r12,lr}; reload saved registers
- STMFD sp!, {r0-r3} ; save r0-r3
- MOV r1, sp
- ADD sp, sp, #16 ; restore sp
- SUB r2, lr, #4 ; save old task's pc to r2
-
- MRS r3, spsr ; get cpsr of interrupt thread
-
- ; switch to SVC mode and no interrupt
- MSR cpsr_c, #I_Bit :OR F_Bit :OR Mode_SVC
-
- STMFD sp!, {r2} ; push old task's pc
- STMFD sp!, {r4-r12,lr}; push old task's lr,r12-r4
- MOV r4, r1 ; Special optimised code below
- MOV r5, r3
- LDMFD r4!, {r0-r3}
- STMFD sp!, {r0-r3} ; push old task's r3-r0
- STMFD sp!, {r5} ; push old task's cpsr
- MRS r4, spsr
- STMFD sp!, {r4} ; push old task's spsr
-
- LDR r4, =rt_interrupt_from_thread
- LDR r5, [r4]
- STR sp, [r5] ; store sp in preempted tasks's TCB
-
- LDR r6, =rt_interrupt_to_thread
- LDR r6, [r6]
- LDR sp, [r6] ; get new task's stack pointer
-
- LDMFD sp!, {r4} ; pop new task's spsr
- MSR spsr_cxsf, r4
- LDMFD sp!, {r4} ; pop new task's psr
- MSR cpsr_cxsf, r4
-
- LDMFD sp!, {r0-r12,lr,pc} ; pop new task's r0-r12,lr & pc
- ENDP
-
-
-
- ALIGN
- IF :DEF:__MICROLIB
-
- EXPORT __heap_base
- EXPORT __heap_limit
- EXPORT __initial_sp
-
- ELSE ;__MICROLIB
-; User Initial Stack & Heap
- AREA |.text|, CODE, READONLY
-
- IMPORT __use_two_region_memory
- EXPORT __user_initial_stackheap
-__user_initial_stackheap
-
- LDR R0, = Heap_Mem
- LDR R1, = (Svc_Stack + Svc_Stack_Size)
- LDR R2, = (Heap_Mem + Heap_Size)
- LDR R3, = Svc_Stack
- BX LR
- ALIGN
- ENDIF
- END
+;============================================================================================== +; star_rvds.s for Keil MDK 4.10 +; +; SEP4020 start up code +; +; Change Logs: +; Date Author Notes +; 2010-03-17 zchong +;============================================================================================= + +PMU_PLTR EQU 0x10001000 ; PLL���ȶ�����ʱ�� +PMU_PMCR EQU 0x10001004 ; ϵͳ��ʱ��PLL�Ŀ��ƼĴ��� +PMU_PUCR EQU 0x10001008 ; USBʱ��PLL�Ŀ��ƼĴ��� +PMU_PCSR EQU 0x1000100C ; �ڲ�ģ��ʱ��Դ�����Ŀ��ƼĴ��� +PMU_PDSLOW EQU 0x10001010 ; SLOW״̬��ʱ�ӵķ�Ƶ���� +PMU_PMDR EQU 0x10001014 ; оƬ����ģʽ�Ĵ��� +PMU_RCTR EQU 0x10001018 ; Reset���ƼĴ��� +PMU_CLRWAKUP EQU 0x1000101C ; WakeUp����Ĵ��� + +RTC_CTR EQU 0x1000200C ; RTC���ƼĴ��� + +INTC_IER EQU 0x10000000 ; IRQ�ж������Ĵ��� +INTC_IMR EQU 0x10000008 ; IRQ�ж����μĴ��� +INTC_IFSR EQU 0x10000030 ; IRQ�ж�����״̬�Ĵ��� +INTC_FIER EQU 0x100000C0 ; FIQ�ж������Ĵ��� +INTC_FIMR EQU 0x100000C4 ; FIQ�ж����μĴ��� + +EMI_CSACONF EQU 0x11000000 ; CSA�������üĴ��� +EMI_CSECONF EQU 0x11000010 ; CSE�������üĴ��� +EMI_CSFCONF EQU 0x11000014 ; CSF�������üĴ��� +EMI_SDCONF1 EQU 0x11000018 ; SDRAMʱ�����üĴ���1 +EMI_SDCONF2 EQU 0x1100001C ; SDRAMʱ�����üĴ���2, SDRAM��ʼ���õ���������Ϣ +EMI_REMAPCONF EQU 0x11000020 ; Ƭѡ�ռ估��ַӳ��REMAP���üĴ��� + +Mode_USR EQU 0x10 +Mode_FIQ EQU 0x11 +Mode_IRQ EQU 0x12 +Mode_SVC EQU 0x13 +Mode_ABT EQU 0x17 +Mode_UND EQU 0x1B +Mode_SYS EQU 0x1F + +I_Bit EQU 0x80 ; when I bit is set, IRQ is disabled +F_Bit EQU 0x40 ; when F bit is set, FIQ is disabled +NOINT EQU 0xc0 +MASK_MODE EQU 0x0000003F +MODE_SVC32 EQU 0x00000013 + +; Internal Memory Base Addresses +FLASH_BASE EQU 0x20000000 +RAM_BASE EQU 0x04000000 +SDRAM_BASE EQU 0x30000000 + +; Stack +Unused_Stack_Size EQU 0x00000100 +Svc_Stack_Size EQU 0x00001000 +Abt_Stack_Size EQU 0x00000000 +Fiq_Stack_Size EQU 0x00000000 +Irq_Stack_Size EQU 0x00001000 +Usr_Stack_Size EQU 0x00000000 + +;SVC STACK + AREA STACK, NOINIT, READWRITE, ALIGN=3 +Svc_Stack SPACE Svc_Stack_Size +__initial_sp +Svc_Stack_Top + +;IRQ STACK + AREA STACK, NOINIT, READWRITE, ALIGN=3 +Irq_Stack SPACE Irq_Stack_Size +Irq_Stack_Top + +;UNUSED STACK + AREA STACK, NOINIT, READWRITE, ALIGN=3 +Unused_Stack SPACE Unused_Stack_Size +Unused_Stack_Top + + +; Heap +Heap_Size EQU 0x0000100 + + AREA HEAP, NOINIT, READWRITE, ALIGN=3 + EXPORT Heap_Mem +__heap_base +Heap_Mem SPACE Heap_Size +__heap_limit + + PRESERVE8 + +; Area Definition and Entry Point +; Startup Code must be linked first at Address at which it expects to run. + + AREA RESET, CODE, READONLY + ARM + +; Exception Vectors +; Mapped to Address 0. +; Absolute addressing mode must be used. +; Dummy Handlers are implemented as infinite loops which can be modified. + EXPORT Entry_Point +Entry_Point +Vectors LDR PC,Reset_Addr + LDR PC,Undef_Addr + LDR PC,SWI_Addr + LDR PC,PAbt_Addr + LDR PC,DAbt_Addr + NOP ; Reserved Vector + LDR PC,IRQ_Addr + LDR PC,FIQ_Addr + +Reset_Addr DCD Reset_Handler +Undef_Addr DCD Undef_Handler +SWI_Addr DCD SWI_Handler +PAbt_Addr DCD PAbt_Handler +DAbt_Addr DCD DAbt_Handler + DCD 0 ; Reserved Address +IRQ_Addr DCD IRQ_Handler +FIQ_Addr DCD FIQ_Handler + +Undef_Handler B Undef_Handler +SWI_Handler B SWI_Handler +PAbt_Handler B Abort_Handler +DAbt_Handler B Abort_Handler +FIQ_Handler B FIQ_Handler + +Abort_Handler PROC + ARM + EXPORT Abort_Handler +DeadLoop BHI DeadLoop ; Abort happened in irq mode, halt system. + ENDP + + +; Reset Handler + ;IMPORT __user_initial_stackheap + EXPORT Reset_Handler +Reset_Handler + +;**************************************************************** +;* Shutdown watchdog +;**************************************************************** + LDR R0,=RTC_CTR + LDR R1,=0x0 + STR R1,[R0] + +;**************************************************************** +;* shutdown interrupts +;**************************************************************** + MRS R0, CPSR + BIC R0, R0, #MASK_MODE + ORR R0, R0, #MODE_SVC32 + ORR R0, R0, #I_Bit + ORR R0, R0, #F_Bit + MSR CPSR_c, r0 + + LDR R0,=INTC_IER + LDR R1,=0x0 + STR R1,[R0] + LDR R0,=INTC_IMR + LDR R1,=0xFFFFFFFF + STR R1,[R0] + + LDR R0,=INTC_FIER + LDR R1,=0x0 + STR R1,[R0] + LDR R0,=INTC_FIMR + LDR R1,=0x0F + STR R1,[R0] + +;**************************************************************** +;* Initialize Stack Pointer +;**************************************************************** + + LDR SP, =Svc_Stack_Top ;init SP_svc + + MOV R4, #0xD2 ;chmod to irq and init SP_irq + MSR cpsr_c, R4 + LDR SP, =Irq_Stack_Top + + MOV R4, #0XD1 ;chomod to fiq and init SP_fiq + MSR cpsr_c, R4 + LDR SP, =Unused_Stack_Top + + MOV R4, #0XD7 ;chomod to abt and init SP_ABT + MSR cpsr_c, R4 + LDR SP, =Unused_Stack_Top + + MOV R4, #0XDB ;chomod to undf and init SP_UNDF + MSR cpsr_c, R4 + LDR SP, =Unused_Stack_Top + + ;chomod to abt and init SP_sys + MOV R4, #0xDF ;all interrupts disabled + MSR cpsr_c, R4 ;SYSTEM mode, @32-bit code mode + LDR SP, =Unused_Stack_Top + + MOV R4, #0XD3 ;chmod to svc modle, CPSR IRQ bit is disable + MSR cpsr_c, R4 + + + +;**************************************************************** +;* Initialize PMU & System Clock +;**************************************************************** + + LDR R4, =PMU_PCSR ; ������ģ��ʱ�� + LDR R5, =0x0001ffff + STR R5, [ R4 ] + + LDR R4, =PMU_PLTR ; ����PLL�ȶ�����ʱ��Ϊ����ֵ50us*100M. + LDR R5, =0x00fa00fa + STR R5, [ R4 ] + + LDR R4, =PMU_PMDR ; ��SLOWģʽ����NORMALģʽ + LDR R5, =0x00000001 + STR R5, [ R4 ] + + LDR R4, =PMU_PMCR ; ����ϵͳʱ��Ϊ80MHz + LDR R5, =0x00004009 ; 400b -- 88M + STR R5, [ R4 ] + + ;PMU_PMCR�Ĵ�����15λ��Ҫ�дӵ͵��ߵķ�ת�����ܴ���PLL��ʱ������ + LDR R4, =PMU_PMCR + LDR R5, =0x0000c009 + STR R5, [ R4 ] + +;**************************************************************** +;* ��ʼ��EMI +;**************************************************************** + + IF :DEF:INIT_EMI + + LDR R4, =EMI_CSACONF ; CSAƬѡʱ��������� + LDR R5, =0x08a6a6a1 + STR R5, [ R4 ] + + LDR R4, =EMI_CSECONF ; CSEƬѡʱ���������,������� + LDR R5, =0x8cfffff1 + STR R5, [ R4 ] + + LDR R4, =EMI_SDCONF1 ; SDRAM��������1 + LDR R5, =0x1E104177 + STR R5, [ R4 ] + + LDR R4, =EMI_SDCONF2 ; SDRAM��������2 + LDR R5, =0x80001860 + STR R5, [ R4 ] + + ENDIF + +; Copy Exception Vectors to Internal RAM + + IF :DEF:RAM_INTVEC + + ADR R8, Vectors ; Source + LDR R9, =RAM_BASE ; Destination + LDMIA R8!, {R0-R7} ; Load Vectors + STMIA R9!, {R0-R7} ; Store Vectors + LDMIA R8!, {R0-R7} ; Load Handler Addresses + STMIA R9!, {R0-R7} ; Store Handler Addresses + + ENDIF + +; Remap on-chip RAM to address 0 + + IF :DEF:REMAP + + LDR R0, =EMI_REMAPCONF + IF :DEF:RAM_INTVEC + MOV R1, #0x80000000 + ELSE + MOV R1, #0x0000000b + ENDIF + STR R1, [R0, #0] ; Remap + + ENDIF + +;*************************************************************** +;* Open irq interrupt +;*************************************************************** + + MRS R4, cpsr + BIC R4, R4, #0x80 ; set bit7 to zero + MSR cpsr_c, R4 + +; Enter the C code + IMPORT __main + LDR R0,=__main + BX R0 + + + IMPORT rt_interrupt_enter + IMPORT rt_interrupt_leave + IMPORT rt_thread_switch_interrupt_flag + IMPORT rt_interrupt_from_thread + IMPORT rt_interrupt_to_thread + IMPORT rt_hw_trap_irq + +IRQ_Handler PROC + EXPORT IRQ_Handler + STMFD sp!, {r0-r12,lr} + BL rt_interrupt_enter + BL rt_hw_trap_irq + BL rt_interrupt_leave + + ; if rt_thread_switch_interrupt_flag set, jump to + ; rt_hw_context_switch_interrupt_do and don't return + LDR r0, =rt_thread_switch_interrupt_flag + LDR r1, [r0] + CMP r1, #1 + BEQ rt_hw_context_switch_interrupt_do + + LDMFD sp!, {r0-r12,lr} + SUBS pc, lr, #4 + ENDP + +; /* +; * void rt_hw_context_switch_interrupt_do(rt_base_t flag) +; */ +rt_hw_context_switch_interrupt_do PROC + EXPORT rt_hw_context_switch_interrupt_do + MOV r1, #0 ; clear flag + STR r1, [r0] + + LDMFD sp!, {r0-r12,lr}; reload saved registers + STMFD sp!, {r0-r3} ; save r0-r3 + MOV r1, sp + ADD sp, sp, #16 ; restore sp + SUB r2, lr, #4 ; save old task's pc to r2 + + MRS r3, spsr ; get cpsr of interrupt thread + + ; switch to SVC mode and no interrupt + MSR cpsr_c, #I_Bit :OR F_Bit :OR Mode_SVC + + STMFD sp!, {r2} ; push old task's pc + STMFD sp!, {r4-r12,lr}; push old task's lr,r12-r4 + MOV r4, r1 ; Special optimised code below + MOV r5, r3 + LDMFD r4!, {r0-r3} + STMFD sp!, {r0-r3} ; push old task's r3-r0 + STMFD sp!, {r5} ; push old task's cpsr + MRS r4, spsr + STMFD sp!, {r4} ; push old task's spsr + + LDR r4, =rt_interrupt_from_thread + LDR r5, [r4] + STR sp, [r5] ; store sp in preempted tasks's TCB + + LDR r6, =rt_interrupt_to_thread + LDR r6, [r6] + LDR sp, [r6] ; get new task's stack pointer + + LDMFD sp!, {r4} ; pop new task's spsr + MSR spsr_cxsf, r4 + LDMFD sp!, {r4} ; pop new task's psr + MSR cpsr_cxsf, r4 + + LDMFD sp!, {r0-r12,lr,pc} ; pop new task's r0-r12,lr & pc + ENDP + + + + ALIGN + IF :DEF:__MICROLIB + + EXPORT __heap_base + EXPORT __heap_limit + EXPORT __initial_sp + + ELSE ;__MICROLIB +; User Initial Stack & Heap + AREA |.text|, CODE, READONLY + + IMPORT __use_two_region_memory + EXPORT __user_initial_stackheap +__user_initial_stackheap + + LDR R0, = Heap_Mem + LDR R1, = (Svc_Stack + Svc_Stack_Size) + LDR R2, = (Heap_Mem + Heap_Size) + LDR R3, = Svc_Stack + BX LR + ALIGN + ENDIF + END diff --git a/libcpu/arm/sep4020/trap.c b/libcpu/arm/sep4020/trap.c index f471fb2471..e7a6e369f9 100644 --- a/libcpu/arm/sep4020/trap.c +++ b/libcpu/arm/sep4020/trap.c @@ -135,18 +135,18 @@ extern rt_isr_handler_t isr_table[]; void rt_hw_trap_irq() { - unsigned long intstat;
+ unsigned long intstat; rt_uint32_t i = 0; - rt_isr_handler_t isr_func;
+ rt_isr_handler_t isr_func; /*Get the final intrrupt source*/ - intstat = *(RP)(INTC_IFSR);;
+ intstat = *(RP)(INTC_IFSR);; - /*Shift to get the intrrupt number*/
- while(intstat != 1)
- {
- intstat = intstat >> 1;
- i++;
+ /*Shift to get the intrrupt number*/ + while(intstat != 1) + { + intstat = intstat >> 1; + i++; } /* get interrupt service routine */ isr_func = isr_table[i]; diff --git a/libcpu/avr32/uc3/context_gcc.S b/libcpu/avr32/uc3/context_gcc.S index 1201626ba8..cbc08e24b2 100644 --- a/libcpu/avr32/uc3/context_gcc.S +++ b/libcpu/avr32/uc3/context_gcc.S @@ -1,97 +1,97 @@ -/*
- * File : context.S
- * This file is part of RT-Thread RTOS
- * COPYRIGHT (C) 2010, RT-Thread Development Team
- *
- * The license and distribution terms for this file may be
- * found in the file LICENSE in this distribution or at
- * http://www.rt-thread.org/license/LICENSE
- *
- * Change Logs:
- * Date Author Notes
- * 2010-03-27 Kyle First version
- */
-
-#define AVR32_SR 0
-#define AVR32_SR_GM_OFFSET 16
-
-.text
-
-/*
- * rt_base_t rt_hw_interrupt_disable()
- */
-.globl rt_hw_interrupt_disable
-.type rt_hw_interrupt_disable, %function
-rt_hw_interrupt_disable:
- ssrf AVR32_SR_GM_OFFSET
- mov pc, lr
-
-/*
- * void rt_hw_interrupt_enable(rt_base_t level)
- */
-.globl rt_hw_interrupt_enable
-.type rt_hw_interrupt_enable, %function
-rt_hw_interrupt_enable:
- csrf AVR32_SR_GM_OFFSET
- mov pc, lr
-
-/*
- * void rt_hw_context_switch(rt_uint32 from, rt_uint32 to)/*
- * r8 --> from
- * r9 --> to
- */
-.globl rt_hw_context_switch
-.type rt_hw_context_switch, %function
-rt_hw_context_switch:
- ssrf AVR32_SR_GM_OFFSET /* Disable global interrupt */
- stm --sp, r8-r12, lr /* Push R8-R12, LR */
- st.w --sp, lr /* Push LR (instead of PC) */
- mfsr r8, AVR32_SR /* Read Status Register */
- cbr r8, AVR32_SR_GM_OFFSET /* Clear GM bit */
- st.w --sp, r8 /* Push SR */
- stm --sp, r0-r7 /* Push R0-R7 */
- /* Stack layout: R8-R12, LR, PC, SR, R0-R7 */
-
- st.w r12[0], sp /* Store SP in preempted tasks TCB */
- ld.w sp, r11[0] /* Get new task stack pointer */
-
- ldm sp++, r0-r7 /* pop R0-R7 */
- ld.w r8, sp++ /* pop SR */
- mtsr AVR32_SR, r8 /* Restore SR */
- ldm sp++, r8-r12, lr, pc/* Pop R8-R12, LR, PC and resume to thread */
-
-/*
- * void rt_hw_context_switch_to(rt_uint32 to)/*
- * r0 --> to
- */
-.globl rt_hw_context_switch_to
-.type rt_hw_context_switch_to, %function
-rt_hw_context_switch_to:
- ld.w sp, r12[0] /* Get new task stack pointer */
-
- ldm sp++, r0-r7 /* pop R0-R7 */
- ld.w r8, sp++ /* pop SR */
- mtsr AVR32_SR, r8 /* Restore SR */
- ldm sp++, r8-r12, lr, pc/* Pop R8-R12, LR, PC and resume execution */
-
-/*
- * void rt_hw_context_switch_interrupt(rt_uint32 from, rt_uint32 to)/*
- */
-.globl rt_thread_switch_interrupt_flag
-.globl rt_interrupt_from_thread
-.globl rt_interrupt_to_thread
-.globl rt_hw_context_switch_interrupt
-.type rt_hw_context_switch_interrupt, %function
-rt_hw_context_switch_interrupt:
- lda.w r8, rt_thread_switch_interrupt_flag
- ld.w r9, r8[0]
- cp.w r9, 1
- breq _reswitch
- mov r9, 1
- st.w r8[0], r9
- lda.w r8, rt_interrupt_from_thread
- st.w r8[0], r12
-_reswitch:
- lda.w r8, rt_interrupt_to_thread
- st.w r8[0], r11
- mov pc, lr
+/* + * File : context.S + * This file is part of RT-Thread RTOS + * COPYRIGHT (C) 2010, RT-Thread Development Team + * + * The license and distribution terms for this file may be + * found in the file LICENSE in this distribution or at + * http://www.rt-thread.org/license/LICENSE + * + * Change Logs: + * Date Author Notes + * 2010-03-27 Kyle First version + */ + +#define AVR32_SR 0 +#define AVR32_SR_GM_OFFSET 16 + +.text + +/* + * rt_base_t rt_hw_interrupt_disable() + */ +.globl rt_hw_interrupt_disable +.type rt_hw_interrupt_disable, %function +rt_hw_interrupt_disable: + ssrf AVR32_SR_GM_OFFSET + mov pc, lr + +/* + * void rt_hw_interrupt_enable(rt_base_t level) + */ +.globl rt_hw_interrupt_enable +.type rt_hw_interrupt_enable, %function +rt_hw_interrupt_enable: + csrf AVR32_SR_GM_OFFSET + mov pc, lr + +/* + * void rt_hw_context_switch(rt_uint32 from, rt_uint32 to)/* + * r8 --> from + * r9 --> to + */ +.globl rt_hw_context_switch +.type rt_hw_context_switch, %function +rt_hw_context_switch: + ssrf AVR32_SR_GM_OFFSET /* Disable global interrupt */ + stm --sp, r8-r12, lr /* Push R8-R12, LR */ + st.w --sp, lr /* Push LR (instead of PC) */ + mfsr r8, AVR32_SR /* Read Status Register */ + cbr r8, AVR32_SR_GM_OFFSET /* Clear GM bit */ + st.w --sp, r8 /* Push SR */ + stm --sp, r0-r7 /* Push R0-R7 */ + /* Stack layout: R8-R12, LR, PC, SR, R0-R7 */ + + st.w r12[0], sp /* Store SP in preempted tasks TCB */ + ld.w sp, r11[0] /* Get new task stack pointer */ + + ldm sp++, r0-r7 /* pop R0-R7 */ + ld.w r8, sp++ /* pop SR */ + mtsr AVR32_SR, r8 /* Restore SR */ + ldm sp++, r8-r12, lr, pc/* Pop R8-R12, LR, PC and resume to thread */ + +/* + * void rt_hw_context_switch_to(rt_uint32 to)/* + * r0 --> to + */ +.globl rt_hw_context_switch_to +.type rt_hw_context_switch_to, %function +rt_hw_context_switch_to: + ld.w sp, r12[0] /* Get new task stack pointer */ + + ldm sp++, r0-r7 /* pop R0-R7 */ + ld.w r8, sp++ /* pop SR */ + mtsr AVR32_SR, r8 /* Restore SR */ + ldm sp++, r8-r12, lr, pc/* Pop R8-R12, LR, PC and resume execution */ + +/* + * void rt_hw_context_switch_interrupt(rt_uint32 from, rt_uint32 to)/* + */ +.globl rt_thread_switch_interrupt_flag +.globl rt_interrupt_from_thread +.globl rt_interrupt_to_thread +.globl rt_hw_context_switch_interrupt +.type rt_hw_context_switch_interrupt, %function +rt_hw_context_switch_interrupt: + lda.w r8, rt_thread_switch_interrupt_flag + ld.w r9, r8[0] + cp.w r9, 1 + breq _reswitch + mov r9, 1 + st.w r8[0], r9 + lda.w r8, rt_interrupt_from_thread + st.w r8[0], r12 +_reswitch: + lda.w r8, rt_interrupt_to_thread + st.w r8[0], r11 + mov pc, lr diff --git a/libcpu/avr32/uc3/cpu.c b/libcpu/avr32/uc3/cpu.c index 503f2737b7..b77e78dc5b 100644 --- a/libcpu/avr32/uc3/cpu.c +++ b/libcpu/avr32/uc3/cpu.c @@ -1,42 +1,42 @@ -/*
- * File : cpu.c
- * This file is part of RT-Thread RTOS
- * COPYRIGHT (C) 2010, RT-Thread Development Team
- *
- * The license and distribution terms for this file may be
- * found in the file LICENSE in this distribution or at
- * http://www.rt-thread.org/license/LICENSE
- *
- * Change Logs:
- * Date Author Notes
- * 2010-03-30 Kyle First version
- */
-
-#include <rtthread.h>
-
-/**
- * @addtogroup AVR32UC3
- */
-/*@{*/
-
-/**
- * reset cpu by dog's time-out
- *
- */
-void rt_hw_cpu_reset()
-{
- /*NOTREACHED*/
-}
-
-/**
- * shutdown CPU
- *
- */
-void rt_hw_cpu_shutdown()
-{
- rt_kprintf("shutdown...\n");
-
- RT_ASSERT(0);
-}
-
-/*@}*/
+/* + * File : cpu.c + * This file is part of RT-Thread RTOS + * COPYRIGHT (C) 2010, RT-Thread Development Team + * + * The license and distribution terms for this file may be + * found in the file LICENSE in this distribution or at + * http://www.rt-thread.org/license/LICENSE + * + * Change Logs: + * Date Author Notes + * 2010-03-30 Kyle First version + */ + +#include <rtthread.h> + +/** + * @addtogroup AVR32UC3 + */ +/*@{*/ + +/** + * reset cpu by dog's time-out + * + */ +void rt_hw_cpu_reset() +{ + /*NOTREACHED*/ +} + +/** + * shutdown CPU + * + */ +void rt_hw_cpu_shutdown() +{ + rt_kprintf("shutdown...\n"); + + RT_ASSERT(0); +} + +/*@}*/ diff --git a/libcpu/avr32/uc3/exception_gcc.S b/libcpu/avr32/uc3/exception_gcc.S index 1a36606f3b..d5051af253 100644 --- a/libcpu/avr32/uc3/exception_gcc.S +++ b/libcpu/avr32/uc3/exception_gcc.S @@ -1,4 +1,4 @@ -/* This file is part of the ATMEL AVR32-UC3-SoftwareFramework-1.6.0 Release */
+/* This file is part of the ATMEL AVR32-UC3-SoftwareFramework-1.6.0 Release */ /*This file is prepared for Doxygen automatic documentation generation.*/ /*! \file ********************************************************************* @@ -71,7 +71,7 @@ // Export symbol. .global _evba .type _evba, @function -_evba:
+_evba: .org 0x000 // Unrecoverable Exception. @@ -193,107 +193,107 @@ _handle_Supervisor_Call: .balign 4 -_int0:
+_int0: mov r12, 0 // Pass the int_level parameter to the _get_interrupt_handler function. call _get_interrupt_handler - cp.w r12, 0 // Get the pointer to the interrupt handler returned by the function.
- breq _spint0 // If this was not a spurious interrupt (R12 != NULL), jump to the handler.
- call rt_interrupt_enter
- icall r12
- call rt_interrupt_leave
- ssrf AVR32_SR_GM_OFFSET /* Disable global interrupt */
- lda.w r12, rt_interrupt_nest /* Is nested interrupt? */
- ld.w r11, r12[0]
- cp.w r11, 0
- brne _spint0
- lda.w r12, rt_thread_switch_interrupt_flag /* Is thread switch required? */
- ld.w r11, r12[0]
- cp.w r11, 1
- breq rt_hw_context_switch_interrupt_do
-_spint0:
- csrf AVR32_SR_GM_OFFSET /* Enable global interrupt */
+ cp.w r12, 0 // Get the pointer to the interrupt handler returned by the function. + breq _spint0 // If this was not a spurious interrupt (R12 != NULL), jump to the handler. + call rt_interrupt_enter + icall r12 + call rt_interrupt_leave + ssrf AVR32_SR_GM_OFFSET /* Disable global interrupt */ + lda.w r12, rt_interrupt_nest /* Is nested interrupt? */ + ld.w r11, r12[0] + cp.w r11, 0 + brne _spint0 + lda.w r12, rt_thread_switch_interrupt_flag /* Is thread switch required? */ + ld.w r11, r12[0] + cp.w r11, 1 + breq rt_hw_context_switch_interrupt_do +_spint0: + csrf AVR32_SR_GM_OFFSET /* Enable global interrupt */ rete // If this was a spurious interrupt (R12 == NULL), return from event handler. -
-
-_int1:
- mov r12, 1 // Pass the int_level parameter to the _get_interrupt_handler function.
- call _get_interrupt_handler
- cp.w r12, 0 // Get the pointer to the interrupt handler returned by the function.
- breq _spint1 // If this was not a spurious interrupt (R12 != NULL), jump to the handler.
- call rt_interrupt_enter
- icall r12
- call rt_interrupt_leave
- ssrf AVR32_SR_GM_OFFSET /* Disable global interrupt */
- lda.w r12, rt_interrupt_nest /* Is nested interrupt? */
- ld.w r11, r12[0]
- cp.w r11, 0
- brne _spint1
- lda.w r12, rt_thread_switch_interrupt_flag /* Is thread switch required? */
- ld.w r11, r12[0]
- cp.w r11, 1
- breq rt_hw_context_switch_interrupt_do
-_spint1:
- csrf AVR32_SR_GM_OFFSET /* Enable global interrupt */
- rete // If this was a spurious interrupt (R12 == NULL), return from event handler.
-
-
-_int2:
- mov r12, 2 // Pass the int_level parameter to the _get_interrupt_handler function.
- call _get_interrupt_handler
- cp.w r12, 0 // Get the pointer to the interrupt handler returned by the function.
- breq _spint2 // If this was not a spurious interrupt (R12 != NULL), jump to the handler.
- call rt_interrupt_enter
- icall r12
- call rt_interrupt_leave
- ssrf AVR32_SR_GM_OFFSET /* Disable global interrupt */
- lda.w r12, rt_interrupt_nest /* Is nested interrupt? */
- ld.w r11, r12[0]
- cp.w r11, 0
- brne _spint2
- lda.w r12, rt_thread_switch_interrupt_flag /* Is thread switch required? */
- ld.w r11, r12[0]
- cp.w r11, 1
- breq rt_hw_context_switch_interrupt_do
-_spint2:
- csrf AVR32_SR_GM_OFFSET /* Enable global interrupt */
- rete // If this was a spurious interrupt (R12 == NULL), return from event handler.
-
-
-_int3:
- mov r12, 3 // Pass the int_level parameter to the _get_interrupt_handler function.
- call _get_interrupt_handler
- cp.w r12, 0 // Get the pointer to the interrupt handler returned by the function.
- breq _spint3 // If this was not a spurious interrupt (R12 != NULL), jump to the handler.
- call rt_interrupt_enter
- icall r12
- call rt_interrupt_leave
- ssrf AVR32_SR_GM_OFFSET /* Disable global interrupt */
- lda.w r12, rt_interrupt_nest /* Is nested interrupt? */
- ld.w r11, r12[0]
- cp.w r11, 0
- brne _spint3
- lda.w r12, rt_thread_switch_interrupt_flag /* Is thread switch required? */
- ld.w r11, r12[0]
- cp.w r11, 1
- breq rt_hw_context_switch_interrupt_do
-_spint3:
- csrf AVR32_SR_GM_OFFSET /* Enable global interrupt */
- rete // If this was a spurious interrupt (R12 == NULL), return from event handler.
-
-
-rt_hw_context_switch_interrupt_do:
- mov r11, 0
- st.w r12[0], r11 /* Clear rt_thread_switch_interrupt_flag */
- stm --sp, r0-r7 /* Push R0-R7 */
- lda.w r12, rt_interrupt_from_thread /* Get old thread SP */
- ld.w r12, r12[0]
- lda.w r11, rt_interrupt_to_thread /* Get new thread SP */
- ld.w r11, r11[0]
- st.w r12[0], sp /* Store old thead SP */
- ld.w sp, r11[0] /* Load new thread SP */
- ldm sp++, r0-r7 /* Pop R0-R7 (new thread) */
+ + +_int1: + mov r12, 1 // Pass the int_level parameter to the _get_interrupt_handler function. + call _get_interrupt_handler + cp.w r12, 0 // Get the pointer to the interrupt handler returned by the function. + breq _spint1 // If this was not a spurious interrupt (R12 != NULL), jump to the handler. + call rt_interrupt_enter + icall r12 + call rt_interrupt_leave + ssrf AVR32_SR_GM_OFFSET /* Disable global interrupt */ + lda.w r12, rt_interrupt_nest /* Is nested interrupt? */ + ld.w r11, r12[0] + cp.w r11, 0 + brne _spint1 + lda.w r12, rt_thread_switch_interrupt_flag /* Is thread switch required? */ + ld.w r11, r12[0] + cp.w r11, 1 + breq rt_hw_context_switch_interrupt_do +_spint1: + csrf AVR32_SR_GM_OFFSET /* Enable global interrupt */ + rete // If this was a spurious interrupt (R12 == NULL), return from event handler. + + +_int2: + mov r12, 2 // Pass the int_level parameter to the _get_interrupt_handler function. + call _get_interrupt_handler + cp.w r12, 0 // Get the pointer to the interrupt handler returned by the function. + breq _spint2 // If this was not a spurious interrupt (R12 != NULL), jump to the handler. + call rt_interrupt_enter + icall r12 + call rt_interrupt_leave + ssrf AVR32_SR_GM_OFFSET /* Disable global interrupt */ + lda.w r12, rt_interrupt_nest /* Is nested interrupt? */ + ld.w r11, r12[0] + cp.w r11, 0 + brne _spint2 + lda.w r12, rt_thread_switch_interrupt_flag /* Is thread switch required? */ + ld.w r11, r12[0] + cp.w r11, 1 + breq rt_hw_context_switch_interrupt_do +_spint2: + csrf AVR32_SR_GM_OFFSET /* Enable global interrupt */ + rete // If this was a spurious interrupt (R12 == NULL), return from event handler. + + +_int3: + mov r12, 3 // Pass the int_level parameter to the _get_interrupt_handler function. + call _get_interrupt_handler + cp.w r12, 0 // Get the pointer to the interrupt handler returned by the function. + breq _spint3 // If this was not a spurious interrupt (R12 != NULL), jump to the handler. + call rt_interrupt_enter + icall r12 + call rt_interrupt_leave + ssrf AVR32_SR_GM_OFFSET /* Disable global interrupt */ + lda.w r12, rt_interrupt_nest /* Is nested interrupt? */ + ld.w r11, r12[0] + cp.w r11, 0 + brne _spint3 + lda.w r12, rt_thread_switch_interrupt_flag /* Is thread switch required? */ + ld.w r11, r12[0] + cp.w r11, 1 + breq rt_hw_context_switch_interrupt_do +_spint3: + csrf AVR32_SR_GM_OFFSET /* Enable global interrupt */ + rete // If this was a spurious interrupt (R12 == NULL), return from event handler. + + +rt_hw_context_switch_interrupt_do: + mov r11, 0 + st.w r12[0], r11 /* Clear rt_thread_switch_interrupt_flag */ + stm --sp, r0-r7 /* Push R0-R7 */ + lda.w r12, rt_interrupt_from_thread /* Get old thread SP */ + ld.w r12, r12[0] + lda.w r11, rt_interrupt_to_thread /* Get new thread SP */ + ld.w r11, r11[0] + st.w r12[0], sp /* Store old thead SP */ + ld.w sp, r11[0] /* Load new thread SP */ + ldm sp++, r0-r7 /* Pop R0-R7 (new thread) */ rete /* RETE pops R8-R12, LR, PC, SR automatically */ -
+ // Constant data area. diff --git a/libcpu/avr32/uc3/interrupt.c b/libcpu/avr32/uc3/interrupt.c index 7cfa71d50e..588ce9ae3d 100644 --- a/libcpu/avr32/uc3/interrupt.c +++ b/libcpu/avr32/uc3/interrupt.c @@ -1,19 +1,19 @@ -/*
- * File : interrupt.c
- * This file is part of RT-Thread RTOS
- * COPYRIGHT (C) 2010, RT-Thread Development Team
- *
- * The license and distribution terms for this file may be
- * found in the file LICENSE in this distribution or at
- * http://www.rt-thread.org/license/LICENSE
- *
- * Change Logs:
- * Date Author Notes
- * 2010-03-30 Kyle Ported from STM32 to AVR32.
- */
-
-#include <rtthread.h>
-#include "compiler.h"
-
-rt_uint32_t rt_interrupt_from_thread, rt_interrupt_to_thread;
-rt_uint32_t rt_thread_switch_interrupt_flag;
+/* + * File : interrupt.c + * This file is part of RT-Thread RTOS + * COPYRIGHT (C) 2010, RT-Thread Development Team + * + * The license and distribution terms for this file may be + * found in the file LICENSE in this distribution or at + * http://www.rt-thread.org/license/LICENSE + * + * Change Logs: + * Date Author Notes + * 2010-03-30 Kyle Ported from STM32 to AVR32. + */ + +#include <rtthread.h> +#include "compiler.h" + +rt_uint32_t rt_interrupt_from_thread, rt_interrupt_to_thread; +rt_uint32_t rt_thread_switch_interrupt_flag; diff --git a/libcpu/avr32/uc3/serial.c b/libcpu/avr32/uc3/serial.c index d5ce9defe8..4deac6b4ab 100644 --- a/libcpu/avr32/uc3/serial.c +++ b/libcpu/avr32/uc3/serial.c @@ -1,277 +1,277 @@ -/*
- * File : serial.c
- * This file is part of RT-Thread RTOS
- * COPYRIGHT (C) 2010, RT-Thread Development Team
- *
- * The license and distribution terms for this file may be
- * found in the file LICENSE in this distribution or at
- * http://www.rt-thread.org/license/LICENSE
- *
- * Change Logs:
- * Date Author Notes
- * 2009-02-05 Bernard first version
- * 2009-10-25 Bernard fix rt_serial_read bug when there is no data
- * in the buffer.
- * 2010-03-29 Bernard cleanup code.
- * 2010-03-30 Kyle Ported from STM32 to AVR32.
- */
-
-#include "serial.h"
-#include "compiler.h"
-#include "usart.h"
-
-struct rt_device _rt_usart_device;
-struct avr32_serial_int_rx _rt_usart_rx;
-struct avr32_serial_device uart =
-{
- .uart_device = (avr32_usart_t *) &AVR32_USART1,
- .int_rx = &_rt_usart_rx
-};
-
-/**
- * @addtogroup AVR32UC3
- */
-/*@{*/
-
-/* RT-Thread Device Interface */
-static rt_err_t rt_serial_init (rt_device_t dev)
-{
- struct avr32_serial_device* uart = (struct avr32_serial_device*) dev->user_data;
-
- if (!(dev->flag & RT_DEVICE_FLAG_ACTIVATED))
- {
- if (dev->flag & RT_DEVICE_FLAG_INT_RX)
- {
- rt_memset(uart->int_rx->rx_buffer, 0, sizeof(uart->int_rx->rx_buffer));
- uart->int_rx->read_index = 0;
- uart->int_rx->save_index = 0;
- }
-
- dev->flag |= RT_DEVICE_FLAG_ACTIVATED;
- }
-
- return RT_EOK;
-}
-
-static rt_err_t rt_serial_open(rt_device_t dev, rt_uint16_t oflag)
-{
- return RT_EOK;
-}
-
-static rt_err_t rt_serial_close(rt_device_t dev)
-{
- return RT_EOK;
-}
-
-static rt_size_t rt_serial_read (rt_device_t dev, rt_off_t pos, void* buffer, rt_size_t size)
-{
- rt_uint8_t* ptr;
- rt_err_t err_code;
- struct avr32_serial_device* uart;
-
- ptr = buffer;
- err_code = RT_EOK;
- uart = (struct avr32_serial_device*)dev->user_data;
-
- if (dev->flag & RT_DEVICE_FLAG_INT_RX)
- {
- /* interrupt mode Rx */
- while (size)
- {
- rt_base_t level;
-
- /* disable interrupt */
- level = rt_hw_interrupt_disable();
-
- if (uart->int_rx->read_index != uart->int_rx->save_index)
- {
- /* read a character */
- *ptr++ = uart->int_rx->rx_buffer[uart->int_rx->read_index];
- size--;
-
- /* move to next position */
- uart->int_rx->read_index ++;
- if (uart->int_rx->read_index >= UART_RX_BUFFER_SIZE)
- uart->int_rx->read_index = 0;
- }
- else
- {
- /* set error code */
- err_code = -RT_EEMPTY;
-
- /* enable interrupt */
- rt_hw_interrupt_enable(level);
- break;
- }
-
- /* enable interrupt */
- rt_hw_interrupt_enable(level);
- }
- }
- else
- {
- /* polling mode */
- while ((rt_uint32_t)ptr - (rt_uint32_t)buffer < size)
- {
- while (usart_test_hit(uart->uart_device))
- {
- *ptr = uart->uart_device->rhr & 0xff;
- ptr ++;
- }
- }
- }
-
- /* set error code */
- rt_set_errno(err_code);
- return (rt_uint32_t)ptr - (rt_uint32_t)buffer;
-}
-
-static rt_size_t rt_serial_write (rt_device_t dev, rt_off_t pos, const void* buffer, rt_size_t size)
-{
- rt_uint8_t* ptr;
- rt_err_t err_code;
- struct avr32_serial_device* uart;
-
- err_code = RT_EOK;
- ptr = (rt_uint8_t*)buffer;
- uart = (struct avr32_serial_device*)dev->user_data;
-
- if (dev->flag & RT_DEVICE_FLAG_INT_TX)
- {
- /* interrupt mode Tx, does not support */
- RT_ASSERT(0);
- }
- else
- {
- /* polling mode */
- if (dev->flag & RT_DEVICE_FLAG_STREAM)
- {
- /* stream mode */
- while (size)
- {
- usart_putchar(uart->uart_device, (int) *ptr);
-
- ++ptr; --size;
- }
- }
- else
- {
- /* write data directly */
- while (size)
- {
- usart_bw_write_char(uart->uart_device, (int) *ptr);
-
- ++ptr; --size;
- }
- }
- }
-
- /* set error code */
- rt_set_errno(err_code);
-
- return (rt_uint32_t)ptr - (rt_uint32_t)buffer;
-}
-
-static rt_err_t rt_serial_control (rt_device_t dev, rt_uint8_t cmd, void *args)
-{
- struct avr32_serial_device* uart;
-
- RT_ASSERT(dev != RT_NULL);
-
- uart = (struct avr32_serial_device*)dev->user_data;
- switch (cmd)
- {
- case RT_DEVICE_CTRL_SUSPEND:
- /* suspend device */
- dev->flag |= RT_DEVICE_FLAG_SUSPENDED;
- break;
-
- case RT_DEVICE_CTRL_RESUME:
- /* resume device */
- dev->flag &= ~RT_DEVICE_FLAG_SUSPENDED;
- break;
- }
-
- return RT_EOK;
-}
-
-/*
- * serial register for STM32
- * support STM32F103VB and STM32F103ZE
- */
-rt_err_t rt_hw_serial_register(rt_device_t device, const char* name, rt_uint32_t flag, struct avr32_serial_device *serial)
-{
- RT_ASSERT(device != RT_NULL);
-
- if ((flag & RT_DEVICE_FLAG_DMA_RX) ||
- (flag & RT_DEVICE_FLAG_INT_TX))
- {
- RT_ASSERT(0);
- }
-
- device->type = RT_Device_Class_Char;
- device->rx_indicate = RT_NULL;
- device->tx_complete = RT_NULL;
- device->init = rt_serial_init;
- device->open = rt_serial_open;
- device->close = rt_serial_close;
- device->read = rt_serial_read;
- device->write = rt_serial_write;
- device->control = rt_serial_control;
- device->user_data = serial;
-
- /* register a character device */
- return rt_device_register(device, name, RT_DEVICE_FLAG_RDWR | flag);
-}
-
-/* ISR for serial interrupt */
-void rt_hw_serial_isr(void)
-{
- struct avr32_serial_device* uart = (struct avr32_serial_device*) _rt_usart_device.user_data;
- rt_base_t level;
-
- if (usart_test_hit(uart->uart_device))
- {
- /* interrupt mode receive */
- RT_ASSERT(device->flag & RT_DEVICE_FLAG_INT_RX);
-
- /* disable interrupt */
- level = rt_hw_interrupt_disable();
-
- /* save character */
- uart->int_rx->rx_buffer[uart->int_rx->save_index] = uart->uart_device->rhr & 0xff;
- uart->int_rx->save_index ++;
- if (uart->int_rx->save_index >= UART_RX_BUFFER_SIZE)
- uart->int_rx->save_index = 0;
-
- /* if the next position is read index, discard this 'read char' */
- if (uart->int_rx->save_index == uart->int_rx->read_index)
- {
- uart->int_rx->read_index ++;
- if (uart->int_rx->read_index >= UART_RX_BUFFER_SIZE)
- uart->int_rx->read_index = 0;
- }
-
- /* enable interrupt */
- rt_hw_interrupt_enable(level);
-
- /* invoke callback */
- if (_rt_usart_device.rx_indicate != RT_NULL)
- {
- rt_size_t rx_length;
-
- /* get rx length */
- rx_length = uart->int_rx->read_index > uart->int_rx->save_index ?
- UART_RX_BUFFER_SIZE - uart->int_rx->read_index + uart->int_rx->save_index :
- uart->int_rx->save_index - uart->int_rx->read_index;
-
- _rt_usart_device.rx_indicate(&_rt_usart_device, rx_length);
- }
- }
- else
- {
- usart_reset_status(uart->uart_device);
- }
-}
-
-/*@}*/
+/* + * File : serial.c + * This file is part of RT-Thread RTOS + * COPYRIGHT (C) 2010, RT-Thread Development Team + * + * The license and distribution terms for this file may be + * found in the file LICENSE in this distribution or at + * http://www.rt-thread.org/license/LICENSE + * + * Change Logs: + * Date Author Notes + * 2009-02-05 Bernard first version + * 2009-10-25 Bernard fix rt_serial_read bug when there is no data + * in the buffer. + * 2010-03-29 Bernard cleanup code. + * 2010-03-30 Kyle Ported from STM32 to AVR32. + */ + +#include "serial.h" +#include "compiler.h" +#include "usart.h" + +struct rt_device _rt_usart_device; +struct avr32_serial_int_rx _rt_usart_rx; +struct avr32_serial_device uart = +{ + .uart_device = (avr32_usart_t *) &AVR32_USART1, + .int_rx = &_rt_usart_rx +}; + +/** + * @addtogroup AVR32UC3 + */ +/*@{*/ + +/* RT-Thread Device Interface */ +static rt_err_t rt_serial_init (rt_device_t dev) +{ + struct avr32_serial_device* uart = (struct avr32_serial_device*) dev->user_data; + + if (!(dev->flag & RT_DEVICE_FLAG_ACTIVATED)) + { + if (dev->flag & RT_DEVICE_FLAG_INT_RX) + { + rt_memset(uart->int_rx->rx_buffer, 0, sizeof(uart->int_rx->rx_buffer)); + uart->int_rx->read_index = 0; + uart->int_rx->save_index = 0; + } + + dev->flag |= RT_DEVICE_FLAG_ACTIVATED; + } + + return RT_EOK; +} + +static rt_err_t rt_serial_open(rt_device_t dev, rt_uint16_t oflag) +{ + return RT_EOK; +} + +static rt_err_t rt_serial_close(rt_device_t dev) +{ + return RT_EOK; +} + +static rt_size_t rt_serial_read (rt_device_t dev, rt_off_t pos, void* buffer, rt_size_t size) +{ + rt_uint8_t* ptr; + rt_err_t err_code; + struct avr32_serial_device* uart; + + ptr = buffer; + err_code = RT_EOK; + uart = (struct avr32_serial_device*)dev->user_data; + + if (dev->flag & RT_DEVICE_FLAG_INT_RX) + { + /* interrupt mode Rx */ + while (size) + { + rt_base_t level; + + /* disable interrupt */ + level = rt_hw_interrupt_disable(); + + if (uart->int_rx->read_index != uart->int_rx->save_index) + { + /* read a character */ + *ptr++ = uart->int_rx->rx_buffer[uart->int_rx->read_index]; + size--; + + /* move to next position */ + uart->int_rx->read_index ++; + if (uart->int_rx->read_index >= UART_RX_BUFFER_SIZE) + uart->int_rx->read_index = 0; + } + else + { + /* set error code */ + err_code = -RT_EEMPTY; + + /* enable interrupt */ + rt_hw_interrupt_enable(level); + break; + } + + /* enable interrupt */ + rt_hw_interrupt_enable(level); + } + } + else + { + /* polling mode */ + while ((rt_uint32_t)ptr - (rt_uint32_t)buffer < size) + { + while (usart_test_hit(uart->uart_device)) + { + *ptr = uart->uart_device->rhr & 0xff; + ptr ++; + } + } + } + + /* set error code */ + rt_set_errno(err_code); + return (rt_uint32_t)ptr - (rt_uint32_t)buffer; +} + +static rt_size_t rt_serial_write (rt_device_t dev, rt_off_t pos, const void* buffer, rt_size_t size) +{ + rt_uint8_t* ptr; + rt_err_t err_code; + struct avr32_serial_device* uart; + + err_code = RT_EOK; + ptr = (rt_uint8_t*)buffer; + uart = (struct avr32_serial_device*)dev->user_data; + + if (dev->flag & RT_DEVICE_FLAG_INT_TX) + { + /* interrupt mode Tx, does not support */ + RT_ASSERT(0); + } + else + { + /* polling mode */ + if (dev->flag & RT_DEVICE_FLAG_STREAM) + { + /* stream mode */ + while (size) + { + usart_putchar(uart->uart_device, (int) *ptr); + + ++ptr; --size; + } + } + else + { + /* write data directly */ + while (size) + { + usart_bw_write_char(uart->uart_device, (int) *ptr); + + ++ptr; --size; + } + } + } + + /* set error code */ + rt_set_errno(err_code); + + return (rt_uint32_t)ptr - (rt_uint32_t)buffer; +} + +static rt_err_t rt_serial_control (rt_device_t dev, rt_uint8_t cmd, void *args) +{ + struct avr32_serial_device* uart; + + RT_ASSERT(dev != RT_NULL); + + uart = (struct avr32_serial_device*)dev->user_data; + switch (cmd) + { + case RT_DEVICE_CTRL_SUSPEND: + /* suspend device */ + dev->flag |= RT_DEVICE_FLAG_SUSPENDED; + break; + + case RT_DEVICE_CTRL_RESUME: + /* resume device */ + dev->flag &= ~RT_DEVICE_FLAG_SUSPENDED; + break; + } + + return RT_EOK; +} + +/* + * serial register for STM32 + * support STM32F103VB and STM32F103ZE + */ +rt_err_t rt_hw_serial_register(rt_device_t device, const char* name, rt_uint32_t flag, struct avr32_serial_device *serial) +{ + RT_ASSERT(device != RT_NULL); + + if ((flag & RT_DEVICE_FLAG_DMA_RX) || + (flag & RT_DEVICE_FLAG_INT_TX)) + { + RT_ASSERT(0); + } + + device->type = RT_Device_Class_Char; + device->rx_indicate = RT_NULL; + device->tx_complete = RT_NULL; + device->init = rt_serial_init; + device->open = rt_serial_open; + device->close = rt_serial_close; + device->read = rt_serial_read; + device->write = rt_serial_write; + device->control = rt_serial_control; + device->user_data = serial; + + /* register a character device */ + return rt_device_register(device, name, RT_DEVICE_FLAG_RDWR | flag); +} + +/* ISR for serial interrupt */ +void rt_hw_serial_isr(void) +{ + struct avr32_serial_device* uart = (struct avr32_serial_device*) _rt_usart_device.user_data; + rt_base_t level; + + if (usart_test_hit(uart->uart_device)) + { + /* interrupt mode receive */ + RT_ASSERT(device->flag & RT_DEVICE_FLAG_INT_RX); + + /* disable interrupt */ + level = rt_hw_interrupt_disable(); + + /* save character */ + uart->int_rx->rx_buffer[uart->int_rx->save_index] = uart->uart_device->rhr & 0xff; + uart->int_rx->save_index ++; + if (uart->int_rx->save_index >= UART_RX_BUFFER_SIZE) + uart->int_rx->save_index = 0; + + /* if the next position is read index, discard this 'read char' */ + if (uart->int_rx->save_index == uart->int_rx->read_index) + { + uart->int_rx->read_index ++; + if (uart->int_rx->read_index >= UART_RX_BUFFER_SIZE) + uart->int_rx->read_index = 0; + } + + /* enable interrupt */ + rt_hw_interrupt_enable(level); + + /* invoke callback */ + if (_rt_usart_device.rx_indicate != RT_NULL) + { + rt_size_t rx_length; + + /* get rx length */ + rx_length = uart->int_rx->read_index > uart->int_rx->save_index ? + UART_RX_BUFFER_SIZE - uart->int_rx->read_index + uart->int_rx->save_index : + uart->int_rx->save_index - uart->int_rx->read_index; + + _rt_usart_device.rx_indicate(&_rt_usart_device, rx_length); + } + } + else + { + usart_reset_status(uart->uart_device); + } +} + +/*@}*/ diff --git a/libcpu/avr32/uc3/serial.h b/libcpu/avr32/uc3/serial.h index cadbfd1850..a17338701b 100644 --- a/libcpu/avr32/uc3/serial.h +++ b/libcpu/avr32/uc3/serial.h @@ -1,53 +1,53 @@ -/*
- * File : serial.h
- * This file is part of RT-Thread RTOS
- * COPYRIGHT (C) 2009 - 2010, RT-Thread Development Team
- *
- * The license and distribution terms for this file may be
- * found in the file LICENSE in this distribution or at
- * http://www.rt-thread.org/license/LICENSE
- *
- * Change Logs:
- * Date Author Notes
- * 2009-01-05 Bernard first version
- * 2010-03-29 Bernard remove interrupt tx and DMA rx mode.
- * 2010-03-30 Kyle Ported from STM32 to AVR32.
- */
-#ifndef __RT_HW_SERIAL_H__
-#define __RT_HW_SERIAL_H__
-
-#include <rthw.h>
-#include <rtthread.h>
-#include "compiler.h"
-#include "usart.h"
-
-#define UART_RX_BUFFER_SIZE 64
-#define UART_TX_DMA_NODE_SIZE 4
-
-/* data node for Tx Mode */
-struct avr32_serial_data_node
-{
- rt_uint8_t *data_ptr;
- rt_size_t data_size;
- struct avr32_serial_data_node *next, *prev;
-};
-
-struct avr32_serial_int_rx
-{
- rt_uint8_t rx_buffer[UART_RX_BUFFER_SIZE];
- rt_uint32_t read_index, save_index;
-};
-
-struct avr32_serial_device
-{
- avr32_usart_t *uart_device;
-
- /* rx structure */
- struct avr32_serial_int_rx* int_rx;
-};
-
-rt_err_t rt_hw_serial_register(rt_device_t device, const char* name, rt_uint32_t flag, struct avr32_serial_device *serial);
-
-void rt_hw_serial_isr();
-
-#endif
+/* + * File : serial.h + * This file is part of RT-Thread RTOS + * COPYRIGHT (C) 2009 - 2010, RT-Thread Development Team + * + * The license and distribution terms for this file may be + * found in the file LICENSE in this distribution or at + * http://www.rt-thread.org/license/LICENSE + * + * Change Logs: + * Date Author Notes + * 2009-01-05 Bernard first version + * 2010-03-29 Bernard remove interrupt tx and DMA rx mode. + * 2010-03-30 Kyle Ported from STM32 to AVR32. + */ +#ifndef __RT_HW_SERIAL_H__ +#define __RT_HW_SERIAL_H__ + +#include <rthw.h> +#include <rtthread.h> +#include "compiler.h" +#include "usart.h" + +#define UART_RX_BUFFER_SIZE 64 +#define UART_TX_DMA_NODE_SIZE 4 + +/* data node for Tx Mode */ +struct avr32_serial_data_node +{ + rt_uint8_t *data_ptr; + rt_size_t data_size; + struct avr32_serial_data_node *next, *prev; +}; + +struct avr32_serial_int_rx +{ + rt_uint8_t rx_buffer[UART_RX_BUFFER_SIZE]; + rt_uint32_t read_index, save_index; +}; + +struct avr32_serial_device +{ + avr32_usart_t *uart_device; + + /* rx structure */ + struct avr32_serial_int_rx* int_rx; +}; + +rt_err_t rt_hw_serial_register(rt_device_t device, const char* name, rt_uint32_t flag, struct avr32_serial_device *serial); + +void rt_hw_serial_isr(); + +#endif diff --git a/libcpu/avr32/uc3/stack.c b/libcpu/avr32/uc3/stack.c index e187f84ce6..dd43b5edbc 100644 --- a/libcpu/avr32/uc3/stack.c +++ b/libcpu/avr32/uc3/stack.c @@ -1,57 +1,57 @@ -/*
- * File : stack.c
- * This file is part of RT-Thread RTOS
- * COPYRIGHT (C) 2010, RT-Thread Development Team
- *
- * The license and distribution terms for this file may be
- * found in the file LICENSE in this distribution or at
- * http://www.rt-thread.org/license/LICENSE
- *
- * Change Logs:
- * Date Author Notes
- * 2010-03-30 Kyle First version
- */
-#include <rtthread.h>
-
-/**
- * @addtogroup AVR32UC3
- */
-/*@{*/
-
-/**
- * This function will initialize thread stack
- *
- * @param tentry the entry of thread
- * @param parameter the parameter of entry
- * @param stack_addr the beginning stack address
- * @param texit the function will be called when thread exit
- *
- * @return stack address
- */
-rt_uint8_t *rt_hw_stack_init(void *tentry, void *parameter, rt_uint8_t *stack_addr, void *texit)
-{
- unsigned long *stk;
-
- stk = (unsigned long *)stack_addr;
- *(stk) = 0; /* r8 */
- *(--stk) = 0; /* r9 */
- *(--stk) = 0; /* r10 */
- *(--stk) = 0; /* r11 */
- *(--stk) = 0; /* r12 */
- *(--stk) = (unsigned long)texit; /* lr */
- *(--stk) = (unsigned long)tentry; /* entry point, pc */
- *(--stk) = 0x00600000; /* sr */
- *(--stk) = 0; /* r0 */
- *(--stk) = 0; /* r1 */
- *(--stk) = 0; /* r2 */
- *(--stk) = 0; /* r3 */
- *(--stk) = 0; /* r4 */
- *(--stk) = 0; /* r5 */
- *(--stk) = 0; /* r6 */
- *(--stk) = 0; /* r7 */
-
- /* return task's current stack address */
- return (rt_uint8_t *)stk;
-}
-
-/*@}*/
+/* + * File : stack.c + * This file is part of RT-Thread RTOS + * COPYRIGHT (C) 2010, RT-Thread Development Team + * + * The license and distribution terms for this file may be + * found in the file LICENSE in this distribution or at + * http://www.rt-thread.org/license/LICENSE + * + * Change Logs: + * Date Author Notes + * 2010-03-30 Kyle First version + */ +#include <rtthread.h> + +/** + * @addtogroup AVR32UC3 + */ +/*@{*/ + +/** + * This function will initialize thread stack + * + * @param tentry the entry of thread + * @param parameter the parameter of entry + * @param stack_addr the beginning stack address + * @param texit the function will be called when thread exit + * + * @return stack address + */ +rt_uint8_t *rt_hw_stack_init(void *tentry, void *parameter, rt_uint8_t *stack_addr, void *texit) +{ + unsigned long *stk; + + stk = (unsigned long *)stack_addr; + *(stk) = 0; /* r8 */ + *(--stk) = 0; /* r9 */ + *(--stk) = 0; /* r10 */ + *(--stk) = 0; /* r11 */ + *(--stk) = 0; /* r12 */ + *(--stk) = (unsigned long)texit; /* lr */ + *(--stk) = (unsigned long)tentry; /* entry point, pc */ + *(--stk) = 0x00600000; /* sr */ + *(--stk) = 0; /* r0 */ + *(--stk) = 0; /* r1 */ + *(--stk) = 0; /* r2 */ + *(--stk) = 0; /* r3 */ + *(--stk) = 0; /* r4 */ + *(--stk) = 0; /* r5 */ + *(--stk) = 0; /* r6 */ + *(--stk) = 0; /* r7 */ + + /* return task's current stack address */ + return (rt_uint8_t *)stk; +} + +/*@}*/ diff --git a/libcpu/blackfin/bf53x/context_vdsp.S b/libcpu/blackfin/bf53x/context_vdsp.S index b955d9ded7..e9cbdda0f1 100644 --- a/libcpu/blackfin/bf53x/context_vdsp.S +++ b/libcpu/blackfin/bf53x/context_vdsp.S @@ -1,165 +1,165 @@ -/*
- * File : context_vdsp.S
- * This file is part of RT-Thread RTOS
- * COPYRIGHT (C) 2009 - 2012, RT-Thread Development Team
- *
- * The license and distribution terms for this file may be
- * found in the file LICENSE in this distribution or at
- * http://www.rt-thread.org/license/LICENSE
- *
- * Change Logs:
- * Date Author Notes
- * 2012-02-13 mojingxian First version
- */
-
-.global _rt_hw_interrupt_disable;
-.global _rt_hw_interrupt_enable;
-.global _interrupt_thread_switch;
-
-.extern _rt_interrupt_from_thread;
-.extern _rt_interrupt_to_thread;
-.extern _rt_thread_switch_interrupt_flag;
-
-.section/DOUBLE64 program;
-
-/*
- * rt_base_t rt_hw_interrupt_disable();
- * return value in R0.
- */
-_rt_hw_interrupt_disable:
- CLI R0;
-
-_rt_hw_interrupt_disable.end:
- NOP;
- NOP;
- NOP;
- RTS;
-
-/*
- * void rt_hw_interrupt_enable(rt_base_t level);
- * R0->level
- */
-_rt_hw_interrupt_enable:
- STI R0;
-
-_rt_hw_interrupt_enable.end:
- NOP;
- NOP;
- NOP;
- RTS;
-
-_interrupt_thread_switch:
- /* Save context, interrupts disabled by IPEND[4] bit */
- [ -- SP ] = R0;
- [ -- SP ] = P1;
- [ -- SP ] = RETS;
- [ -- SP ] = R1;
- [ -- SP ] = R2;
- [ -- SP ] = P0;
- [ -- SP ] = P2;
- [ -- SP ] = ASTAT;
- R1 = RETI; /* IPEND[4] is currently set, globally disabling interrupts */
- /* IPEND[4] will stay set when RETI is saved through R1 */
-
- [ -- SP ] = R1;
- [ -- SP ] = (R7:3, P5:3);
- [ -- SP ] = FP;
- [ -- SP ] = I0;
- [ -- SP ] = I1;
- [ -- SP ] = I2;
- [ -- SP ] = I3;
- [ -- SP ] = B0;
- [ -- SP ] = B1;
- [ -- SP ] = B2;
- [ -- SP ] = B3;
- [ -- SP ] = L0;
- [ -- SP ] = L1;
- [ -- SP ] = L2;
- [ -- SP ] = L3;
- [ -- SP ] = M0;
- [ -- SP ] = M1;
- [ -- SP ] = M2;
- [ -- SP ] = M3;
- R1.L = A0.x;
- [ -- SP ] = R1;
- R1 = A0.w;
- [ -- SP ] = R1;
- R1.L = A1.x;
- [ -- SP ] = R1;
- R1 = A1.w;
- [ -- SP ] = R1;
- [ -- SP ] = LC0;
- R3 = 0;
- LC0 = R3;
- [ -- SP ] = LC1;
- R3 = 0;
- LC1 = R3;
- [ -- SP ] = LT0;
- [ -- SP ] = LT1;
- [ -- SP ] = LB0;
- [ -- SP ] = LB1;
-
- /* Context save done so save SP in the TCB */
- P1.h = _rt_interrupt_from_thread;
- P1.l = _rt_interrupt_from_thread;
- P2 = [ P1 ];
- [ P2 ] = SP;
-
- /* clear rt_thread_switch_interrupt_flag to 0 */
- P1.h = _rt_thread_switch_interrupt_flag;
- P1.l = _rt_thread_switch_interrupt_flag;
- R0 = 0;
- [ P1 ] = R0;
-
- /* Get a pointer to the high ready task's TCB */
- P1.h = _rt_interrupt_to_thread;
- P1.l = _rt_interrupt_to_thread;
- P2 = [ P1 ];
- SP = [ P2 ];
-
- /* Restoring CPU context and return to task */
- LB1 = [ SP ++ ];
- LB0 = [ SP ++ ];
- LT1 = [ SP ++ ];
- LT0 = [ SP ++ ];
- LC1 = [ SP ++ ];
- LC0 = [ SP ++ ];
- R0 = [ SP ++ ];
- A1 = R0;
- R0 = [ SP ++ ];
- A1.x = R0.L;
- R0 = [ SP ++ ];
- A0 = R0;
- R0 = [ SP ++ ];
- A0.x = R0.L;
- M3 = [ SP ++ ];
- M2 = [ SP ++ ];
- M1 = [ SP ++ ];
- M0 = [ SP ++ ];
- L3 = [ SP ++ ];
- L2 = [ SP ++ ];
- L1 = [ SP ++ ];
- L0 = [ SP ++ ];
- B3 = [ SP ++ ];
- B2 = [ SP ++ ];
- B1 = [ SP ++ ];
- B0 = [ SP ++ ];
- I3 = [ SP ++ ];
- I2 = [ SP ++ ];
- I1 = [ SP ++ ];
- I0 = [ SP ++ ];
- FP = [ SP ++ ];
- (R7:3, P5:3) = [ SP ++ ];
- RETI = [ SP ++ ]; /* IPEND[4] will stay set when RETI popped from stack */
- ASTAT = [ SP ++ ];
- P2 = [ SP ++ ];
- P0 = [ SP ++ ];
- R2 = [ SP ++ ];
- R1 = [ SP ++ ];
- RETS = [ SP ++ ];
- P1 = [ SP ++ ];
- R0 = [ SP ++ ];
-
-_interrupt_thread_switch.end:
- RTI;
-
+/* + * File : context_vdsp.S + * This file is part of RT-Thread RTOS + * COPYRIGHT (C) 2009 - 2012, RT-Thread Development Team + * + * The license and distribution terms for this file may be + * found in the file LICENSE in this distribution or at + * http://www.rt-thread.org/license/LICENSE + * + * Change Logs: + * Date Author Notes + * 2012-02-13 mojingxian First version + */ + +.global _rt_hw_interrupt_disable; +.global _rt_hw_interrupt_enable; +.global _interrupt_thread_switch; + +.extern _rt_interrupt_from_thread; +.extern _rt_interrupt_to_thread; +.extern _rt_thread_switch_interrupt_flag; + +.section/DOUBLE64 program; + +/* + * rt_base_t rt_hw_interrupt_disable(); + * return value in R0. + */ +_rt_hw_interrupt_disable: + CLI R0; + +_rt_hw_interrupt_disable.end: + NOP; + NOP; + NOP; + RTS; + +/* + * void rt_hw_interrupt_enable(rt_base_t level); + * R0->level + */ +_rt_hw_interrupt_enable: + STI R0; + +_rt_hw_interrupt_enable.end: + NOP; + NOP; + NOP; + RTS; + +_interrupt_thread_switch: + /* Save context, interrupts disabled by IPEND[4] bit */ + [ -- SP ] = R0; + [ -- SP ] = P1; + [ -- SP ] = RETS; + [ -- SP ] = R1; + [ -- SP ] = R2; + [ -- SP ] = P0; + [ -- SP ] = P2; + [ -- SP ] = ASTAT; + R1 = RETI; /* IPEND[4] is currently set, globally disabling interrupts */ + /* IPEND[4] will stay set when RETI is saved through R1 */ + + [ -- SP ] = R1; + [ -- SP ] = (R7:3, P5:3); + [ -- SP ] = FP; + [ -- SP ] = I0; + [ -- SP ] = I1; + [ -- SP ] = I2; + [ -- SP ] = I3; + [ -- SP ] = B0; + [ -- SP ] = B1; + [ -- SP ] = B2; + [ -- SP ] = B3; + [ -- SP ] = L0; + [ -- SP ] = L1; + [ -- SP ] = L2; + [ -- SP ] = L3; + [ -- SP ] = M0; + [ -- SP ] = M1; + [ -- SP ] = M2; + [ -- SP ] = M3; + R1.L = A0.x; + [ -- SP ] = R1; + R1 = A0.w; + [ -- SP ] = R1; + R1.L = A1.x; + [ -- SP ] = R1; + R1 = A1.w; + [ -- SP ] = R1; + [ -- SP ] = LC0; + R3 = 0; + LC0 = R3; + [ -- SP ] = LC1; + R3 = 0; + LC1 = R3; + [ -- SP ] = LT0; + [ -- SP ] = LT1; + [ -- SP ] = LB0; + [ -- SP ] = LB1; + + /* Context save done so save SP in the TCB */ + P1.h = _rt_interrupt_from_thread; + P1.l = _rt_interrupt_from_thread; + P2 = [ P1 ]; + [ P2 ] = SP; + + /* clear rt_thread_switch_interrupt_flag to 0 */ + P1.h = _rt_thread_switch_interrupt_flag; + P1.l = _rt_thread_switch_interrupt_flag; + R0 = 0; + [ P1 ] = R0; + + /* Get a pointer to the high ready task's TCB */ + P1.h = _rt_interrupt_to_thread; + P1.l = _rt_interrupt_to_thread; + P2 = [ P1 ]; + SP = [ P2 ]; + + /* Restoring CPU context and return to task */ + LB1 = [ SP ++ ]; + LB0 = [ SP ++ ]; + LT1 = [ SP ++ ]; + LT0 = [ SP ++ ]; + LC1 = [ SP ++ ]; + LC0 = [ SP ++ ]; + R0 = [ SP ++ ]; + A1 = R0; + R0 = [ SP ++ ]; + A1.x = R0.L; + R0 = [ SP ++ ]; + A0 = R0; + R0 = [ SP ++ ]; + A0.x = R0.L; + M3 = [ SP ++ ]; + M2 = [ SP ++ ]; + M1 = [ SP ++ ]; + M0 = [ SP ++ ]; + L3 = [ SP ++ ]; + L2 = [ SP ++ ]; + L1 = [ SP ++ ]; + L0 = [ SP ++ ]; + B3 = [ SP ++ ]; + B2 = [ SP ++ ]; + B1 = [ SP ++ ]; + B0 = [ SP ++ ]; + I3 = [ SP ++ ]; + I2 = [ SP ++ ]; + I1 = [ SP ++ ]; + I0 = [ SP ++ ]; + FP = [ SP ++ ]; + (R7:3, P5:3) = [ SP ++ ]; + RETI = [ SP ++ ]; /* IPEND[4] will stay set when RETI popped from stack */ + ASTAT = [ SP ++ ]; + P2 = [ SP ++ ]; + P0 = [ SP ++ ]; + R2 = [ SP ++ ]; + R1 = [ SP ++ ]; + RETS = [ SP ++ ]; + P1 = [ SP ++ ]; + R0 = [ SP ++ ]; + +_interrupt_thread_switch.end: + RTI; + diff --git a/libcpu/blackfin/bf53x/serial.h b/libcpu/blackfin/bf53x/serial.h index 8eef14546b..8d85193634 100644 --- a/libcpu/blackfin/bf53x/serial.h +++ b/libcpu/blackfin/bf53x/serial.h @@ -1,56 +1,56 @@ -#ifndef __RT_HW_SERIAL_H__
-#define __RT_HW_SERIAL_H__
-
-#include <rthw.h>
-#include <rtthread.h>
-
-#define USTAT_RCV_READY 0x01 /* receive data ready */
-#define USTAT_TXB_EMPTY 0x02 /* tx buffer empty */
-#define BPS 115200 /* serial baudrate */
-
-#define UART_RX_BUFFER_SIZE 64
-#define UART_TX_BUFFER_SIZE 64
-
-struct serial_int_rx
-{
- rt_uint8_t rx_buffer[UART_RX_BUFFER_SIZE];
- rt_uint32_t read_index, save_index;
-};
-
-struct serial_int_tx
-{
- rt_uint8_t tx_buffer[UART_TX_BUFFER_SIZE];
- rt_uint32_t write_index, save_index;
-};
-
-typedef struct uartport
-{
- volatile rt_uint16_t rbr_thr; //receive buffer register and transmit hold register
- volatile rt_uint16_t reserved0;
- volatile rt_uint16_t reserved1;
- volatile rt_uint16_t reserved2;
- volatile rt_uint16_t reserved3;
- volatile rt_uint16_t reserved4;
- volatile rt_uint16_t reserved5;
- volatile rt_uint16_t reserved6;
- volatile rt_uint16_t reserved7;
- volatile rt_uint16_t reserved8;
- volatile rt_uint16_t lsr; //line status register
-}uartport;
-
-struct serial_device
-{
- uartport* uart_device;
-
- /* rx structure */
- struct serial_int_rx* int_rx;
-
- /* tx structure */
- struct serial_int_tx* int_tx;
-};
-
-rt_err_t rt_hw_serial_register(rt_device_t device, const char* name, rt_uint32_t flag, struct serial_device *serial);
-
-void rt_hw_serial_isr(rt_device_t device);
-
-#endif
+#ifndef __RT_HW_SERIAL_H__ +#define __RT_HW_SERIAL_H__ + +#include <rthw.h> +#include <rtthread.h> + +#define USTAT_RCV_READY 0x01 /* receive data ready */ +#define USTAT_TXB_EMPTY 0x02 /* tx buffer empty */ +#define BPS 115200 /* serial baudrate */ + +#define UART_RX_BUFFER_SIZE 64 +#define UART_TX_BUFFER_SIZE 64 + +struct serial_int_rx +{ + rt_uint8_t rx_buffer[UART_RX_BUFFER_SIZE]; + rt_uint32_t read_index, save_index; +}; + +struct serial_int_tx +{ + rt_uint8_t tx_buffer[UART_TX_BUFFER_SIZE]; + rt_uint32_t write_index, save_index; +}; + +typedef struct uartport +{ + volatile rt_uint16_t rbr_thr; //receive buffer register and transmit hold register + volatile rt_uint16_t reserved0; + volatile rt_uint16_t reserved1; + volatile rt_uint16_t reserved2; + volatile rt_uint16_t reserved3; + volatile rt_uint16_t reserved4; + volatile rt_uint16_t reserved5; + volatile rt_uint16_t reserved6; + volatile rt_uint16_t reserved7; + volatile rt_uint16_t reserved8; + volatile rt_uint16_t lsr; //line status register +}uartport; + +struct serial_device +{ + uartport* uart_device; + + /* rx structure */ + struct serial_int_rx* int_rx; + + /* tx structure */ + struct serial_int_tx* int_tx; +}; + +rt_err_t rt_hw_serial_register(rt_device_t device, const char* name, rt_uint32_t flag, struct serial_device *serial); + +void rt_hw_serial_isr(rt_device_t device); + +#endif diff --git a/libcpu/ia32/backtrace.c b/libcpu/ia32/backtrace.c index d7a152469b..b8f094d90f 100644 --- a/libcpu/ia32/backtrace.c +++ b/libcpu/ia32/backtrace.c @@ -1,20 +1,20 @@ -/*
- * File : backtrace.c
- * This file is part of RT-Thread RTOS
- * COPYRIGHT (C) 2006, 2008 RT-Thread Development Team
- *
- * The license and distribution terms for this file may be
- * found in the file LICENSE in this distribution or at
- * http://openlab.rt-thread.com/license/LICENSE
- *
- * Change Logs:
- * Date Author Notes
- * 2008-07-29 Bernard first version
- */
-
-#include <rtthread.h>
-
-void rt_hw_backtrace(rt_uint32_t *fp, rt_uint32_t thread_entry)
-{
- /* no implementation */
-}
+/* + * File : backtrace.c + * This file is part of RT-Thread RTOS + * COPYRIGHT (C) 2006, 2008 RT-Thread Development Team + * + * The license and distribution terms for this file may be + * found in the file LICENSE in this distribution or at + * http://openlab.rt-thread.com/license/LICENSE + * + * Change Logs: + * Date Author Notes + * 2008-07-29 Bernard first version + */ + +#include <rtthread.h> + +void rt_hw_backtrace(rt_uint32_t *fp, rt_uint32_t thread_entry) +{ + /* no implementation */ +} diff --git a/libcpu/ia32/hdisr_gcc.S b/libcpu/ia32/hdisr_gcc.S index cc622ff52c..29f200772f 100644 --- a/libcpu/ia32/hdisr_gcc.S +++ b/libcpu/ia32/hdisr_gcc.S @@ -59,7 +59,7 @@ HDINTERRUPTFNC(irq15, 15) .globl _hdinterrupts .type _hdinterrupts,@function .globl rt_interrupt_enter -.globl rt_interrupt_leave
+.globl rt_interrupt_leave .globl isr_table .globl rt_thread_switch_interrupt_flag .globl rt_interrupt_from_thread @@ -73,9 +73,9 @@ _hdinterrupts: movw %ax, %ds movw %ax, %es pushl %esp -
+ call rt_interrupt_enter -
+ movl %esp, %eax /* copy esp to eax */ addl $0x2c, %eax /* move to vector address */ movl (%eax), %eax /* vector(eax) = *eax */ diff --git a/libcpu/ia32/interrupt.c b/libcpu/ia32/interrupt.c index 91df04c0ce..01086a6266 100644 --- a/libcpu/ia32/interrupt.c +++ b/libcpu/ia32/interrupt.c @@ -1,118 +1,118 @@ -/*
- * File : interrupt.c
- * This file is part of RT-Thread RTOS
- * COPYRIGHT (C) 2006, RT-Thread Development Team
- *
- * The license and distribution terms for this file may be
- * found in the file LICENSE in this distribution or at
- * http://openlab.rt-thread.com/license/LICENSE
- *
- * Change Logs:
- * Date Author Notes
- */
-
-#include <rtthread.h>
-#include <rthw.h>
-
-#include <bsp.h>
-
-extern rt_uint32_t rt_interrupt_nest;
-extern void rt_hw_idt_init(void);
-
-rt_uint32_t rt_interrupt_from_thread, rt_interrupt_to_thread;
-rt_uint32_t rt_thread_switch_interrupt_flag;
-
-/* exception and interrupt handler table */
-rt_isr_handler_t isr_table[MAX_HANDLERS];
-rt_uint16_t irq_mask_8259A = 0xFFFF;
-
-/**
- * @addtogroup I386
- */
-/*@{*/
-
-/**
- * This function initializes 8259 interrupt controller
- */
-void rt_hw_pic_init()
-{
- outb(IO_PIC1, 0x11);
- outb(IO_PIC1+1, IRQ_OFFSET);
- outb(IO_PIC1+1, 1<<IRQ_SLAVE);
- outb(IO_PIC1+1, 0x3);
- outb(IO_PIC1+1, 0xff);
- outb(IO_PIC1, 0x68);
- outb(IO_PIC1, 0x0a);
- outb(IO_PIC2, 0x11);
- outb(IO_PIC2+1, IRQ_OFFSET + 8);
- outb(IO_PIC2+1, IRQ_SLAVE);
- outb(IO_PIC2+1, 0x3);
- outb(IO_PIC2+1, 0xff);
- outb(IO_PIC2, 0x68);
- outb(IO_PIC2, 0x0a);
-
- if (irq_mask_8259A != 0xFFFF)
- {
- outb(IO_PIC1+1, (char)irq_mask_8259A);
- outb(IO_PIC2+1, (char)(irq_mask_8259A >> 8));
- }
-
- /* init interrupt nest, and context */
- rt_interrupt_nest = 0;
- rt_interrupt_from_thread = 0;
- rt_interrupt_to_thread = 0;
- rt_thread_switch_interrupt_flag = 0;
-}
-
-void rt_hw_interrupt_handle(int vector)
-{
- rt_kprintf("Unhandled interrupt %d occured!!!\n", vector);
-}
-
-/**
- * This function initializes interrupt descript table and 8259 interrupt controller
- *
- */
-void rt_hw_interrupt_init(void)
-{
- rt_hw_idt_init();
- rt_hw_pic_init();
-}
-
-void rt_hw_interrupt_umask(int vector)
-{
- irq_mask_8259A = irq_mask_8259A&~(1<<vector);
- outb(IO_PIC1+1, (char)irq_mask_8259A);
- outb(IO_PIC2+1, (char)(irq_mask_8259A >> 8));
-}
-
-void rt_hw_interrupt_mask(int vector)
-{
- irq_mask_8259A = irq_mask_8259A | (1<<vector);
- outb(IO_PIC1+1, (char)irq_mask_8259A);
- outb(IO_PIC2+1, (char)(irq_mask_8259A >> 8));
-}
-
-void rt_hw_interrupt_install(int vector, rt_isr_handler_t new_handler, rt_isr_handler_t *old_handler)
-{
- if(vector < MAX_HANDLERS)
- {
- if (*old_handler != RT_NULL) *old_handler = isr_table[vector];
- if (new_handler != RT_NULL) isr_table[vector] = new_handler;
- }
-}
-
-rt_base_t rt_hw_interrupt_disable(void)
-{
- rt_base_t level;
-
- __asm__ __volatile__("pushfl ; popl %0 ; cli":"=g" (level): :"memory");
- return level;
-}
-
-void rt_hw_interrupt_enable(rt_base_t level)
-{
- __asm__ __volatile__("pushl %0 ; popfl": :"g" (level):"memory", "cc");
-}
-
-/*@}*/
+/* + * File : interrupt.c + * This file is part of RT-Thread RTOS + * COPYRIGHT (C) 2006, RT-Thread Development Team + * + * The license and distribution terms for this file may be + * found in the file LICENSE in this distribution or at + * http://openlab.rt-thread.com/license/LICENSE + * + * Change Logs: + * Date Author Notes + */ + +#include <rtthread.h> +#include <rthw.h> + +#include <bsp.h> + +extern rt_uint32_t rt_interrupt_nest; +extern void rt_hw_idt_init(void); + +rt_uint32_t rt_interrupt_from_thread, rt_interrupt_to_thread; +rt_uint32_t rt_thread_switch_interrupt_flag; + +/* exception and interrupt handler table */ +rt_isr_handler_t isr_table[MAX_HANDLERS]; +rt_uint16_t irq_mask_8259A = 0xFFFF; + +/** + * @addtogroup I386 + */ +/*@{*/ + +/** + * This function initializes 8259 interrupt controller + */ +void rt_hw_pic_init() +{ + outb(IO_PIC1, 0x11); + outb(IO_PIC1+1, IRQ_OFFSET); + outb(IO_PIC1+1, 1<<IRQ_SLAVE); + outb(IO_PIC1+1, 0x3); + outb(IO_PIC1+1, 0xff); + outb(IO_PIC1, 0x68); + outb(IO_PIC1, 0x0a); + outb(IO_PIC2, 0x11); + outb(IO_PIC2+1, IRQ_OFFSET + 8); + outb(IO_PIC2+1, IRQ_SLAVE); + outb(IO_PIC2+1, 0x3); + outb(IO_PIC2+1, 0xff); + outb(IO_PIC2, 0x68); + outb(IO_PIC2, 0x0a); + + if (irq_mask_8259A != 0xFFFF) + { + outb(IO_PIC1+1, (char)irq_mask_8259A); + outb(IO_PIC2+1, (char)(irq_mask_8259A >> 8)); + } + + /* init interrupt nest, and context */ + rt_interrupt_nest = 0; + rt_interrupt_from_thread = 0; + rt_interrupt_to_thread = 0; + rt_thread_switch_interrupt_flag = 0; +} + +void rt_hw_interrupt_handle(int vector) +{ + rt_kprintf("Unhandled interrupt %d occured!!!\n", vector); +} + +/** + * This function initializes interrupt descript table and 8259 interrupt controller + * + */ +void rt_hw_interrupt_init(void) +{ + rt_hw_idt_init(); + rt_hw_pic_init(); +} + +void rt_hw_interrupt_umask(int vector) +{ + irq_mask_8259A = irq_mask_8259A&~(1<<vector); + outb(IO_PIC1+1, (char)irq_mask_8259A); + outb(IO_PIC2+1, (char)(irq_mask_8259A >> 8)); +} + +void rt_hw_interrupt_mask(int vector) +{ + irq_mask_8259A = irq_mask_8259A | (1<<vector); + outb(IO_PIC1+1, (char)irq_mask_8259A); + outb(IO_PIC2+1, (char)(irq_mask_8259A >> 8)); +} + +void rt_hw_interrupt_install(int vector, rt_isr_handler_t new_handler, rt_isr_handler_t *old_handler) +{ + if(vector < MAX_HANDLERS) + { + if (*old_handler != RT_NULL) *old_handler = isr_table[vector]; + if (new_handler != RT_NULL) isr_table[vector] = new_handler; + } +} + +rt_base_t rt_hw_interrupt_disable(void) +{ + rt_base_t level; + + __asm__ __volatile__("pushfl ; popl %0 ; cli":"=g" (level): :"memory"); + return level; +} + +void rt_hw_interrupt_enable(rt_base_t level) +{ + __asm__ __volatile__("pushl %0 ; popfl": :"g" (level):"memory", "cc"); +} + +/*@}*/ diff --git a/libcpu/ia32/showmem.c b/libcpu/ia32/showmem.c index c171a9bcd7..38f037f83d 100644 --- a/libcpu/ia32/showmem.c +++ b/libcpu/ia32/showmem.c @@ -1,42 +1,42 @@ -/*
- * File : showmem.c
- * This file is part of RT-Thread RTOS
- * COPYRIGHT (C) 2006, 2008 RT-Thread Development Team
- *
- * The license and distribution terms for this file may be
- * found in the file LICENSE in this distribution or at
- * http://openlab.rt-thread.com/license/LICENSE
- *
- * Change Logs:
- * Date Author Notes
- * 2008-07-29 Bernard first version from QiuYi implementation
- */
-
-#include <rtthread.h>
-
-void rt_hw_show_memory(rt_uint32_t addr, rt_uint32_t size)
-{
- int i = 0, j =0;
-
- RT_ASSERT(addr);
-
- addr = addr & ~0xF;
- size = 4*((size + 3)/4);
-
- while(i < size)
- {
- rt_kprintf("0x%08x: ", addr );
-
- for(j=0; j<4; j++)
- {
- rt_kprintf("0x%08x ", *(rt_uint32_t *)addr);
-
- addr += 4;
- i++;
- }
-
- rt_kprintf("\n");
- }
-
- return;
-}
+/* + * File : showmem.c + * This file is part of RT-Thread RTOS + * COPYRIGHT (C) 2006, 2008 RT-Thread Development Team + * + * The license and distribution terms for this file may be + * found in the file LICENSE in this distribution or at + * http://openlab.rt-thread.com/license/LICENSE + * + * Change Logs: + * Date Author Notes + * 2008-07-29 Bernard first version from QiuYi implementation + */ + +#include <rtthread.h> + +void rt_hw_show_memory(rt_uint32_t addr, rt_uint32_t size) +{ + int i = 0, j =0; + + RT_ASSERT(addr); + + addr = addr & ~0xF; + size = 4*((size + 3)/4); + + while(i < size) + { + rt_kprintf("0x%08x: ", addr ); + + for(j=0; j<4; j++) + { + rt_kprintf("0x%08x ", *(rt_uint32_t *)addr); + + addr += 4; + i++; + } + + rt_kprintf("\n"); + } + + return; +} diff --git a/libcpu/ia32/stack.c b/libcpu/ia32/stack.c index 0331819f71..9d656a73d6 100644 --- a/libcpu/ia32/stack.c +++ b/libcpu/ia32/stack.c @@ -1,59 +1,59 @@ -/*
- * File : stack.c
- * This file is part of RT-Thread RTOS
- * COPYRIGHT (C) 2006, RT-Thread Development Team
- *
- * The license and distribution terms for this file may be
- * found in the file LICENSE in this distribution or at
- * http://openlab.rt-thread.com/license/LICENSE
- *
- * Change Logs:
- * Date Author Notes
- */
-
-#include <rtthread.h>
-
-#include <i386.h>
-
-/**
- * @addtogroup I386
- */
-/*@{*/
-
-/**
- * This function will initialize thread stack
- *
- * @param tentry the entry of thread
- * @param parameter the parameter of entry
- * @param stack_addr the beginning stack address
- * @param texit the function will be called when thread exit
- *
- * @return stack address
- */
-rt_uint8_t *rt_hw_stack_init(void *tentry, void *parameter,
- rt_uint8_t *stack_addr, void *texit)
-{
- unsigned long *stk;
-
- stk = (unsigned long *)stack_addr;
- *(--stk) = (unsigned long)parameter;
- *(--stk) = (unsigned long)texit;
- *(--stk) = 0x200; /*flags*/
- *(--stk) = 0x08; /*cs*/
- *(--stk) = (unsigned long)tentry; /*eip*/
- *(--stk) = 0; /*irqno*/
- *(--stk) = 0x10; /*ds*/
- *(--stk) = 0x10; /*es*/
- *(--stk) = 0; /*eax*/
- *(--stk) = 0; /*ecx*/
- *(--stk) = 0; /*edx*/
- *(--stk) = 0; /*ebx*/
- *(--stk) = 0; /*esp*/
- *(--stk) = 0; /*ebp*/
- *(--stk) = 0; /*esi*/
- *(--stk) = 0; /*edi*/
-
- /* return task's current stack address */
- return (rt_uint8_t *)stk;
-}
-/*@}*/
+/* + * File : stack.c + * This file is part of RT-Thread RTOS + * COPYRIGHT (C) 2006, RT-Thread Development Team + * + * The license and distribution terms for this file may be + * found in the file LICENSE in this distribution or at + * http://openlab.rt-thread.com/license/LICENSE + * + * Change Logs: + * Date Author Notes + */ + +#include <rtthread.h> + +#include <i386.h> + +/** + * @addtogroup I386 + */ +/*@{*/ + +/** + * This function will initialize thread stack + * + * @param tentry the entry of thread + * @param parameter the parameter of entry + * @param stack_addr the beginning stack address + * @param texit the function will be called when thread exit + * + * @return stack address + */ +rt_uint8_t *rt_hw_stack_init(void *tentry, void *parameter, + rt_uint8_t *stack_addr, void *texit) +{ + unsigned long *stk; + + stk = (unsigned long *)stack_addr; + *(--stk) = (unsigned long)parameter; + *(--stk) = (unsigned long)texit; + *(--stk) = 0x200; /*flags*/ + *(--stk) = 0x08; /*cs*/ + *(--stk) = (unsigned long)tentry; /*eip*/ + *(--stk) = 0; /*irqno*/ + *(--stk) = 0x10; /*ds*/ + *(--stk) = 0x10; /*es*/ + *(--stk) = 0; /*eax*/ + *(--stk) = 0; /*ecx*/ + *(--stk) = 0; /*edx*/ + *(--stk) = 0; /*ebx*/ + *(--stk) = 0; /*esp*/ + *(--stk) = 0; /*ebp*/ + *(--stk) = 0; /*esi*/ + *(--stk) = 0; /*edi*/ + + /* return task's current stack address */ + return (rt_uint8_t *)stk; +} +/*@}*/ diff --git a/libcpu/ia32/start_gcc.S b/libcpu/ia32/start_gcc.S index 650309a7f3..84adc83fe2 100644 --- a/libcpu/ia32/start_gcc.S +++ b/libcpu/ia32/start_gcc.S @@ -1,97 +1,97 @@ -/*
- * File : start.S
- * This file is part of RT-Thread RTOS
- * COPYRIGHT (C) 2006 - 2012, RT-Thread Development Team
- *
- * The license and distribution terms for this file may be
- * found in the file LICENSE in this distribution or at
- * http://www.rt-thread.org/license/LICENSE
- *
- * Change Logs:
- * Date Author Notes
- * 2006-09-15 QiuYi The first version.
- * 2012-02-15 aozima update.
- */
-
-/* the magic number for the multiboot header. */
-#define MULTIBOOT_HEADER_MAGIC 0x1BADB002
-
-/* the flags for the multiboot header. */
-#define MULTIBOOT_HEADER_FLAGS 0x00000003
-
-#define CONFIG_STACKSIZE 8192
-
-/**
- * @addtogroup I386
- */
-/*@{*/
-
-.section .init, "ax"
-
-/* the system entry */
-.globl _start
-_start:
- jmp multiboot_entry
-
- /* Align 32 bits boundary. */
- .align 4
-
- /* multiboot header. */
-multiboot_header:
- /* magic */
- .long MULTIBOOT_HEADER_MAGIC
- /* flags */
- .long MULTIBOOT_HEADER_FLAGS
- /* checksum */
- .long -(MULTIBOOT_HEADER_MAGIC + MULTIBOOT_HEADER_FLAGS)
-
-multiboot_entry:
- movl $(_end + 0x1000),%esp
-
- /* reset eflags. */
- pushl $0
- popf
-
- /*rebuild globe describe table*/
- lgdt mygdtdesc
-
- movl $0x10,%eax
- movw %ax,%ds
- movw %ax,%es
- movw %ax,%ss
- ljmp $0x08, $relocated
-
-relocated:
- /* push the pointer to the multiboot information structure. */
- pushl %ebx
-
- /* push the magic value. */
- pushl %eax
-
- call rtthread_startup
-
- /* never get here */
-spin:
- hlt
- jmp spin
-
-.data
-.p2align 2
-mygdt:
- .word 0,0,0,0
-
- .word 0x07FF /* 8Mb - limit=2047 */
- .word 0x0000
- .word 0x9A00 /* code read/exec */
- .word 0x00C0
-
- .word 0x07FF /* 8Mb - limit=2047 */
- .word 0x0000
- .word 0x9200 /* data read/write */
- .word 0x00C0
-
-mygdtdesc:
- .word 0x17
- .long mygdt
-
-/*@}*/
+/* + * File : start.S + * This file is part of RT-Thread RTOS + * COPYRIGHT (C) 2006 - 2012, RT-Thread Development Team + * + * The license and distribution terms for this file may be + * found in the file LICENSE in this distribution or at + * http://www.rt-thread.org/license/LICENSE + * + * Change Logs: + * Date Author Notes + * 2006-09-15 QiuYi The first version. + * 2012-02-15 aozima update. + */ + +/* the magic number for the multiboot header. */ +#define MULTIBOOT_HEADER_MAGIC 0x1BADB002 + +/* the flags for the multiboot header. */ +#define MULTIBOOT_HEADER_FLAGS 0x00000003 + +#define CONFIG_STACKSIZE 8192 + +/** + * @addtogroup I386 + */ +/*@{*/ + +.section .init, "ax" + +/* the system entry */ +.globl _start +_start: + jmp multiboot_entry + + /* Align 32 bits boundary. */ + .align 4 + + /* multiboot header. */ +multiboot_header: + /* magic */ + .long MULTIBOOT_HEADER_MAGIC + /* flags */ + .long MULTIBOOT_HEADER_FLAGS + /* checksum */ + .long -(MULTIBOOT_HEADER_MAGIC + MULTIBOOT_HEADER_FLAGS) + +multiboot_entry: + movl $(_end + 0x1000),%esp + + /* reset eflags. */ + pushl $0 + popf + + /*rebuild globe describe table*/ + lgdt mygdtdesc + + movl $0x10,%eax + movw %ax,%ds + movw %ax,%es + movw %ax,%ss + ljmp $0x08, $relocated + +relocated: + /* push the pointer to the multiboot information structure. */ + pushl %ebx + + /* push the magic value. */ + pushl %eax + + call rtthread_startup + + /* never get here */ +spin: + hlt + jmp spin + +.data +.p2align 2 +mygdt: + .word 0,0,0,0 + + .word 0x07FF /* 8Mb - limit=2047 */ + .word 0x0000 + .word 0x9A00 /* code read/exec */ + .word 0x00C0 + + .word 0x07FF /* 8Mb - limit=2047 */ + .word 0x0000 + .word 0x9200 /* data read/write */ + .word 0x00C0 + +mygdtdesc: + .word 0x17 + .long mygdt + +/*@}*/ diff --git a/libcpu/ia32/trap.c b/libcpu/ia32/trap.c index 10595dc5a1..52b9e65ea3 100644 --- a/libcpu/ia32/trap.c +++ b/libcpu/ia32/trap.c @@ -1,108 +1,108 @@ -/*
- * File : trap.c
- * This file is part of RT-Thread RTOS
- * COPYRIGHT (C) 2006, RT-Thread Development Team
- *
- * The license and distribution terms for this file may be
- * found in the file LICENSE in this distribution or at
- * http://openlab.rt-thread.com/license/LICENSE
- *
- * Change Logs:
- * Date Author Notes
- */
-
-#include <rtthread.h>
-#include <rthw.h>
-
-#include <bsp.h>
-
-/* Interrupt descriptor table. (Must be built at run time because
- * shifted function addresses can't be represented in relocation records.)
- */
-struct Gatedesc idt[256] = { {0}, };
-struct Pseudodesc idt_pd =
-{
- 0, sizeof(idt) - 1, (unsigned long) idt,
-};
-
-/* exception and interrupt handler table */
-extern rt_isr_handler_t isr_table[];
-extern rt_isr_handler_t trap_func[];
-extern rt_isr_handler_t hdinterrupt_func[];
-
-/**
- * @addtogroup I386
- */
-/*@{*/
-
-/**
- * this function initializes the interrupt descript table
- *
- */
-void rt_hw_idt_init(void)
-{
- extern void Xdefault;
- int i, j, func;
-
- for(i=0; i<MAX_HANDLERS; i++)
- {
- isr_table[i] = rt_hw_interrupt_handle;
- }
-
- // install a default handler
- for (i = 0; i < sizeof(idt)/sizeof(idt[0]); i++)
- SETGATE(idt[i], 0, GD_KT, &Xdefault, 0);
-
- /*install trap handler*/
- for(i = 0; i < 16; i++)
- {
- func = (int)trap_func[i];
- SETGATE(idt[i], 0, GD_KT, func, 0);
- }
-
- func = (int)trap_func[3];
- SETGATE(idt[3], 0, GD_KT, func, 3);
-
- i = 0;
-
- /*install exteral interrupt handler*/
- for(j = IRQ_OFFSET; j < IRQ_OFFSET + MAX_HANDLERS; j++)
- {
- func = (int)hdinterrupt_func[i];
- SETGATE(idt[j], 0, GD_KT, func, 0);
- i++;
- }
-
- // Load the IDT
- asm volatile("lidt idt_pd + 2");
-}
-
-/**
- * this function will deal with all kinds of kernel trap
- *
- *@param trapno the trap number
- *
- */
-void rt_hw_trap_irq(int trapno)
-{
- switch(trapno)
- {
- case T_DIVIDE:
- rt_kprintf("Divide error interrupt\n");
- RT_ASSERT(0);
- case T_PGFLT:
- rt_kprintf("Page fault interrupt\n");
- RT_ASSERT(0);
- case T_GPFLT:
- rt_kprintf("General protection interrupt\n");
- RT_ASSERT(0);
- case T_DEFAULT:
- rt_hw_interrupt_handle(T_DEFAULT);
- return;
- }
-
- /*kernel bug if run here*/
- RT_ASSERT(0);
-}
-
-/*@}*/
+/* + * File : trap.c + * This file is part of RT-Thread RTOS + * COPYRIGHT (C) 2006, RT-Thread Development Team + * + * The license and distribution terms for this file may be + * found in the file LICENSE in this distribution or at + * http://openlab.rt-thread.com/license/LICENSE + * + * Change Logs: + * Date Author Notes + */ + +#include <rtthread.h> +#include <rthw.h> + +#include <bsp.h> + +/* Interrupt descriptor table. (Must be built at run time because + * shifted function addresses can't be represented in relocation records.) + */ +struct Gatedesc idt[256] = { {0}, }; +struct Pseudodesc idt_pd = +{ + 0, sizeof(idt) - 1, (unsigned long) idt, +}; + +/* exception and interrupt handler table */ +extern rt_isr_handler_t isr_table[]; +extern rt_isr_handler_t trap_func[]; +extern rt_isr_handler_t hdinterrupt_func[]; + +/** + * @addtogroup I386 + */ +/*@{*/ + +/** + * this function initializes the interrupt descript table + * + */ +void rt_hw_idt_init(void) +{ + extern void Xdefault; + int i, j, func; + + for(i=0; i<MAX_HANDLERS; i++) + { + isr_table[i] = rt_hw_interrupt_handle; + } + + // install a default handler + for (i = 0; i < sizeof(idt)/sizeof(idt[0]); i++) + SETGATE(idt[i], 0, GD_KT, &Xdefault, 0); + + /*install trap handler*/ + for(i = 0; i < 16; i++) + { + func = (int)trap_func[i]; + SETGATE(idt[i], 0, GD_KT, func, 0); + } + + func = (int)trap_func[3]; + SETGATE(idt[3], 0, GD_KT, func, 3); + + i = 0; + + /*install exteral interrupt handler*/ + for(j = IRQ_OFFSET; j < IRQ_OFFSET + MAX_HANDLERS; j++) + { + func = (int)hdinterrupt_func[i]; + SETGATE(idt[j], 0, GD_KT, func, 0); + i++; + } + + // Load the IDT + asm volatile("lidt idt_pd + 2"); +} + +/** + * this function will deal with all kinds of kernel trap + * + *@param trapno the trap number + * + */ +void rt_hw_trap_irq(int trapno) +{ + switch(trapno) + { + case T_DIVIDE: + rt_kprintf("Divide error interrupt\n"); + RT_ASSERT(0); + case T_PGFLT: + rt_kprintf("Page fault interrupt\n"); + RT_ASSERT(0); + case T_GPFLT: + rt_kprintf("General protection interrupt\n"); + RT_ASSERT(0); + case T_DEFAULT: + rt_hw_interrupt_handle(T_DEFAULT); + return; + } + + /*kernel bug if run here*/ + RT_ASSERT(0); +} + +/*@}*/ diff --git a/libcpu/ia32/trapisr_gcc.S b/libcpu/ia32/trapisr_gcc.S index d4cda4db7f..be7e97a5fb 100644 --- a/libcpu/ia32/trapisr_gcc.S +++ b/libcpu/ia32/trapisr_gcc.S @@ -1,98 +1,98 @@ -/*
- * File : trapisr_gcc.S
- * This file is part of RT-Thread RTOS
- * COPYRIGHT (C) 2006, RT-Thread Development Team
- *
- * The license and distribution terms for this file may be
- * found in the file LICENSE in this distribution or at
- * http://www.rt-thread.org/license/LICENSE
- *
- * Change Logs:
- * Date Author Notes
- * 2006-09-15 QiuYi The first version.
- */
-
-/**
- * @addtogroup I386
- */
-/*@{*/
-
-#define ENTRY(proc)\
- .align 2;\
- .globl proc;\
- .type proc,@function;\
- proc:
-#define TRAPFNC(name,num)\
- ENTRY(name)\
- pushl $(num);\
- jmp _traps;\
- .data;\
- .long name;\
- .text
-#define TRAPFNC_NOEC(name,num)\
- ENTRY(name)\
- pushl $0;\
- pushl $(num);\
- jmp _traps;\
- .data;\
- .long name;\
- .text
-
-.globl trap_func
- .data
- .align 4
- .type trap_func,@object
- trap_func :
-.text
-
-/* CPU traps */
-TRAPFNC_NOEC(Xdivide, 0)
-TRAPFNC_NOEC(Xdebug, 1)
-TRAPFNC_NOEC(Xnmi, 2)
-TRAPFNC_NOEC(Xbrkpt, 3)
-TRAPFNC_NOEC(Xoflow, 4)
-TRAPFNC_NOEC(Xbound, 5)
-TRAPFNC_NOEC(Xillop, 6)
-TRAPFNC_NOEC(Xdevice, 7)
-TRAPFNC (Xdblflt, 8)
-TRAPFNC (Xtss, 9)
-TRAPFNC (Xsegnp, 10)
-TRAPFNC (Xstack, 11)
-TRAPFNC (Xgpflt, 12)
-TRAPFNC (Xpgflt, 13)
-TRAPFNC_NOEC(Xfperr, 14)
-TRAPFNC (Xalign, 15)
-
-/* default handler -- not for any specific trap */
-TRAPFNC (Xdefault, 500)
-
-.p2align 4,0x90
-.globl _traps
-.type _traps,@function
-.globl rt_interrupt_enter
-.globl rt_interrupt_leave
-
-_traps:
- push %ds
- push %es
- pushal
- movw $0x10,%ax
- movw %ax,%ds
- movw %ax,%es
- pushl %esp
- call rt_interrupt_enter
- movl %esp, %eax
- addl $0x2c,%eax /*get trapno*/
- movl (%eax),%eax
- pushl %eax /*push trapno*/
- call rt_hw_trap_irq
- addl $4,%esp
- call rt_interrupt_leave
- popl %esp
- popal
- pop %es
- pop %ds
- add $8,%esp
- iret
-
-/*@}*/
+/* + * File : trapisr_gcc.S + * This file is part of RT-Thread RTOS + * COPYRIGHT (C) 2006, RT-Thread Development Team + * + * The license and distribution terms for this file may be + * found in the file LICENSE in this distribution or at + * http://www.rt-thread.org/license/LICENSE + * + * Change Logs: + * Date Author Notes + * 2006-09-15 QiuYi The first version. + */ + +/** + * @addtogroup I386 + */ +/*@{*/ + +#define ENTRY(proc)\ + .align 2;\ + .globl proc;\ + .type proc,@function;\ + proc: +#define TRAPFNC(name,num)\ + ENTRY(name)\ + pushl $(num);\ + jmp _traps;\ + .data;\ + .long name;\ + .text +#define TRAPFNC_NOEC(name,num)\ + ENTRY(name)\ + pushl $0;\ + pushl $(num);\ + jmp _traps;\ + .data;\ + .long name;\ + .text + +.globl trap_func + .data + .align 4 + .type trap_func,@object + trap_func : +.text + +/* CPU traps */ +TRAPFNC_NOEC(Xdivide, 0) +TRAPFNC_NOEC(Xdebug, 1) +TRAPFNC_NOEC(Xnmi, 2) +TRAPFNC_NOEC(Xbrkpt, 3) +TRAPFNC_NOEC(Xoflow, 4) +TRAPFNC_NOEC(Xbound, 5) +TRAPFNC_NOEC(Xillop, 6) +TRAPFNC_NOEC(Xdevice, 7) +TRAPFNC (Xdblflt, 8) +TRAPFNC (Xtss, 9) +TRAPFNC (Xsegnp, 10) +TRAPFNC (Xstack, 11) +TRAPFNC (Xgpflt, 12) +TRAPFNC (Xpgflt, 13) +TRAPFNC_NOEC(Xfperr, 14) +TRAPFNC (Xalign, 15) + +/* default handler -- not for any specific trap */ +TRAPFNC (Xdefault, 500) + +.p2align 4,0x90 +.globl _traps +.type _traps,@function +.globl rt_interrupt_enter +.globl rt_interrupt_leave + +_traps: + push %ds + push %es + pushal + movw $0x10,%ax + movw %ax,%ds + movw %ax,%es + pushl %esp + call rt_interrupt_enter + movl %esp, %eax + addl $0x2c,%eax /*get trapno*/ + movl (%eax),%eax + pushl %eax /*push trapno*/ + call rt_hw_trap_irq + addl $4,%esp + call rt_interrupt_leave + popl %esp + popal + pop %es + pop %ds + add $8,%esp + iret + +/*@}*/ diff --git a/libcpu/m16c/m16c62p/context_gcc.S b/libcpu/m16c/m16c62p/context_gcc.S index e19b4743d3..45a2080800 100644 --- a/libcpu/m16c/m16c62p/context_gcc.S +++ b/libcpu/m16c/m16c62p/context_gcc.S @@ -1,47 +1,47 @@ -/*
- * File : context.asm
- * This file is part of RT-Thread RTOS
- * COPYRIGHT (C) 2009, RT-Thread Development Team
- *
- * The license and distribution terms for this file may be
- * found in the file LICENSE in this distribution or at
- * http://www.rt-thread.org/license/LICENSE
- *
- * Change Logs:
- * Date Author Notes
- * 2010-04-09 fify the first version
- * 2010-04-19 fify rewrite rt_hw_interrupt_disable/enable fuction
- * 2010-04-20 fify move peripheral ISR to bsp/interrupts.s34
- */
-
- .section .text
-
- .globl _rt_interrupt_from_thread
- .globl _rt_interrupt_to_thread
- .global _os_context_switch
- .type _os_context_switch, @function
-_os_context_switch:
- PUSHM R0,R1,R2,R3,A0,A1,SB,FB
-
- MOV.W _rt_interrupt_from_thread, A0
- STC ISP, [A0]
- MOV.W _rt_interrupt_to_thread, A0
- LDC [A0], ISP
-
- POPM R0,R1,R2,R3,A0,A1,SB,FB ; Restore registers from the new task's stack
- REIT ; Return from interrup
-
-/*
- * void rt_hw_context_switch_to(rt_uint32 to);
- * this fucntion is used to perform the first thread switch
- */
- .global _rt_hw_context_switch_to
- .type _rt_hw_context_switch_to, @function
-_rt_hw_context_switch_to:
- ENTER #0x0
- MOV.W 0x5[FB], A0
- LDC [A0], ISP
- POPM R0,R1,R2,R3,A0,A1,SB,FB
- REIT
-
- .end
+/* + * File : context.asm + * This file is part of RT-Thread RTOS + * COPYRIGHT (C) 2009, RT-Thread Development Team + * + * The license and distribution terms for this file may be + * found in the file LICENSE in this distribution or at + * http://www.rt-thread.org/license/LICENSE + * + * Change Logs: + * Date Author Notes + * 2010-04-09 fify the first version + * 2010-04-19 fify rewrite rt_hw_interrupt_disable/enable fuction + * 2010-04-20 fify move peripheral ISR to bsp/interrupts.s34 + */ + + .section .text + + .globl _rt_interrupt_from_thread + .globl _rt_interrupt_to_thread + .global _os_context_switch + .type _os_context_switch, @function +_os_context_switch: + PUSHM R0,R1,R2,R3,A0,A1,SB,FB + + MOV.W _rt_interrupt_from_thread, A0 + STC ISP, [A0] + MOV.W _rt_interrupt_to_thread, A0 + LDC [A0], ISP + + POPM R0,R1,R2,R3,A0,A1,SB,FB ; Restore registers from the new task's stack + REIT ; Return from interrup + +/* + * void rt_hw_context_switch_to(rt_uint32 to); + * this fucntion is used to perform the first thread switch + */ + .global _rt_hw_context_switch_to + .type _rt_hw_context_switch_to, @function +_rt_hw_context_switch_to: + ENTER #0x0 + MOV.W 0x5[FB], A0 + LDC [A0], ISP + POPM R0,R1,R2,R3,A0,A1,SB,FB + REIT + + .end diff --git a/libcpu/m16c/m16c62p/context_iar.S b/libcpu/m16c/m16c62p/context_iar.S index bd75341f4b..9415b2bdea 100644 --- a/libcpu/m16c/m16c62p/context_iar.S +++ b/libcpu/m16c/m16c62p/context_iar.S @@ -1,66 +1,66 @@ -/*
- * File : context.asm
- * This file is part of RT-Thread RTOS
- * COPYRIGHT (C) 2009, RT-Thread Development Team
- *
- * The license and distribution terms for this file may be
- * found in the file LICENSE in this distribution or at
- * http://www.rt-thread.org/license/LICENSE
- *
- * Change Logs:
- * Date Author Notes
- * 2010-04-09 fify the first version
- * 2010-04-19 fify rewrite rt_hw_interrupt_disable/enable fuction
- * 2010-04-20 fify move peripheral ISR to bsp/interrupts.s34
- *
- * For : Renesas M16C
- * Toolchain : IAR's EW for M16C v3.401
- */
-
- RSEG CSTACK
-
- RSEG ISTACK
-
- RSEG CODE(1)
-
- EXTERN rt_interrupt_from_thread
- EXTERN rt_interrupt_to_thread
-
- PUBLIC rt_hw_interrupt_disable
- PUBLIC rt_hw_interrupt_enable
- PUBLIC rt_hw_context_switch_to
- PUBLIC os_context_switch
-
-rt_hw_interrupt_disable:
- STC FLG, R0 ;fify 20100419
- FCLR I
- RTS
-
-rt_hw_interrupt_enable:
- LDC R0, FLG ;fify 20100419
- RTS
-
- .EVEN
-os_context_switch:
- PUSHM R0,R1,R2,R3,A0,A1,SB,FB
-
- MOV.W rt_interrupt_from_thread, A0
- STC ISP, [A0]
- MOV.W rt_interrupt_to_thread, A0
- LDC [A0], ISP
-
- POPM R0,R1,R2,R3,A0,A1,SB,FB ; Restore registers from the new task's stack
- REIT ; Return from interrup
-
-/*
- * void rt_hw_context_switch_to(rt_uint32 to);
- * r0 --> to
- * this fucntion is used to perform the first thread switch
- */
-rt_hw_context_switch_to:
- MOV.W R0, A0
- LDC [A0], ISP
- POPM R0,R1,R2,R3,A0,A1,SB,FB
- REIT
-
- END
+/* + * File : context.asm + * This file is part of RT-Thread RTOS + * COPYRIGHT (C) 2009, RT-Thread Development Team + * + * The license and distribution terms for this file may be + * found in the file LICENSE in this distribution or at + * http://www.rt-thread.org/license/LICENSE + * + * Change Logs: + * Date Author Notes + * 2010-04-09 fify the first version + * 2010-04-19 fify rewrite rt_hw_interrupt_disable/enable fuction + * 2010-04-20 fify move peripheral ISR to bsp/interrupts.s34 + * + * For : Renesas M16C + * Toolchain : IAR's EW for M16C v3.401 + */ + + RSEG CSTACK + + RSEG ISTACK + + RSEG CODE(1) + + EXTERN rt_interrupt_from_thread + EXTERN rt_interrupt_to_thread + + PUBLIC rt_hw_interrupt_disable + PUBLIC rt_hw_interrupt_enable + PUBLIC rt_hw_context_switch_to + PUBLIC os_context_switch + +rt_hw_interrupt_disable: + STC FLG, R0 ;fify 20100419 + FCLR I + RTS + +rt_hw_interrupt_enable: + LDC R0, FLG ;fify 20100419 + RTS + + .EVEN +os_context_switch: + PUSHM R0,R1,R2,R3,A0,A1,SB,FB + + MOV.W rt_interrupt_from_thread, A0 + STC ISP, [A0] + MOV.W rt_interrupt_to_thread, A0 + LDC [A0], ISP + + POPM R0,R1,R2,R3,A0,A1,SB,FB ; Restore registers from the new task's stack + REIT ; Return from interrup + +/* + * void rt_hw_context_switch_to(rt_uint32 to); + * r0 --> to + * this fucntion is used to perform the first thread switch + */ +rt_hw_context_switch_to: + MOV.W R0, A0 + LDC [A0], ISP + POPM R0,R1,R2,R3,A0,A1,SB,FB + REIT + + END diff --git a/libcpu/m16c/m16c62p/context_iar.asm b/libcpu/m16c/m16c62p/context_iar.asm index bd75341f4b..9415b2bdea 100644 --- a/libcpu/m16c/m16c62p/context_iar.asm +++ b/libcpu/m16c/m16c62p/context_iar.asm @@ -1,66 +1,66 @@ -/*
- * File : context.asm
- * This file is part of RT-Thread RTOS
- * COPYRIGHT (C) 2009, RT-Thread Development Team
- *
- * The license and distribution terms for this file may be
- * found in the file LICENSE in this distribution or at
- * http://www.rt-thread.org/license/LICENSE
- *
- * Change Logs:
- * Date Author Notes
- * 2010-04-09 fify the first version
- * 2010-04-19 fify rewrite rt_hw_interrupt_disable/enable fuction
- * 2010-04-20 fify move peripheral ISR to bsp/interrupts.s34
- *
- * For : Renesas M16C
- * Toolchain : IAR's EW for M16C v3.401
- */
-
- RSEG CSTACK
-
- RSEG ISTACK
-
- RSEG CODE(1)
-
- EXTERN rt_interrupt_from_thread
- EXTERN rt_interrupt_to_thread
-
- PUBLIC rt_hw_interrupt_disable
- PUBLIC rt_hw_interrupt_enable
- PUBLIC rt_hw_context_switch_to
- PUBLIC os_context_switch
-
-rt_hw_interrupt_disable:
- STC FLG, R0 ;fify 20100419
- FCLR I
- RTS
-
-rt_hw_interrupt_enable:
- LDC R0, FLG ;fify 20100419
- RTS
-
- .EVEN
-os_context_switch:
- PUSHM R0,R1,R2,R3,A0,A1,SB,FB
-
- MOV.W rt_interrupt_from_thread, A0
- STC ISP, [A0]
- MOV.W rt_interrupt_to_thread, A0
- LDC [A0], ISP
-
- POPM R0,R1,R2,R3,A0,A1,SB,FB ; Restore registers from the new task's stack
- REIT ; Return from interrup
-
-/*
- * void rt_hw_context_switch_to(rt_uint32 to);
- * r0 --> to
- * this fucntion is used to perform the first thread switch
- */
-rt_hw_context_switch_to:
- MOV.W R0, A0
- LDC [A0], ISP
- POPM R0,R1,R2,R3,A0,A1,SB,FB
- REIT
-
- END
+/* + * File : context.asm + * This file is part of RT-Thread RTOS + * COPYRIGHT (C) 2009, RT-Thread Development Team + * + * The license and distribution terms for this file may be + * found in the file LICENSE in this distribution or at + * http://www.rt-thread.org/license/LICENSE + * + * Change Logs: + * Date Author Notes + * 2010-04-09 fify the first version + * 2010-04-19 fify rewrite rt_hw_interrupt_disable/enable fuction + * 2010-04-20 fify move peripheral ISR to bsp/interrupts.s34 + * + * For : Renesas M16C + * Toolchain : IAR's EW for M16C v3.401 + */ + + RSEG CSTACK + + RSEG ISTACK + + RSEG CODE(1) + + EXTERN rt_interrupt_from_thread + EXTERN rt_interrupt_to_thread + + PUBLIC rt_hw_interrupt_disable + PUBLIC rt_hw_interrupt_enable + PUBLIC rt_hw_context_switch_to + PUBLIC os_context_switch + +rt_hw_interrupt_disable: + STC FLG, R0 ;fify 20100419 + FCLR I + RTS + +rt_hw_interrupt_enable: + LDC R0, FLG ;fify 20100419 + RTS + + .EVEN +os_context_switch: + PUSHM R0,R1,R2,R3,A0,A1,SB,FB + + MOV.W rt_interrupt_from_thread, A0 + STC ISP, [A0] + MOV.W rt_interrupt_to_thread, A0 + LDC [A0], ISP + + POPM R0,R1,R2,R3,A0,A1,SB,FB ; Restore registers from the new task's stack + REIT ; Return from interrup + +/* + * void rt_hw_context_switch_to(rt_uint32 to); + * r0 --> to + * this fucntion is used to perform the first thread switch + */ +rt_hw_context_switch_to: + MOV.W R0, A0 + LDC [A0], ISP + POPM R0,R1,R2,R3,A0,A1,SB,FB + REIT + + END diff --git a/libcpu/m16c/m16c62p/cpuport.c b/libcpu/m16c/m16c62p/cpuport.c index 2957bd3d2c..c66f73b727 100644 --- a/libcpu/m16c/m16c62p/cpuport.c +++ b/libcpu/m16c/m16c62p/cpuport.c @@ -1,116 +1,116 @@ -/*
- * File : cpuport.c
- * This file is part of RT-Thread RTOS
- * COPYRIGHT (C) 2009 - 2012, RT-Thread Development Team
- *
- * The license and distribution terms for this file may be
- * found in the file LICENSE in this distribution or at
- * http://www.rt-thread.org/license/LICENSE
- *
- * Change Logs:
- * Date Author Notes
- * 2011-02-23 Bernard the first version
- * 2012-09-25 lgnq save texit address in to thread stack
- */
-
-#include <rtthread.h>
-
-extern volatile rt_uint8_t rt_interrupt_nest;
-
-/* switch flag on interrupt and thread pointer to save switch record */
-rt_uint32_t rt_interrupt_from_thread;
-rt_uint32_t rt_interrupt_to_thread;
-rt_uint8_t rt_thread_switch_interrupt_flag;
-
-/**
- * This function will initialize hardware interrupt
- */
-void rt_hw_interrupt_init(void)
-{
- /* init interrupt nest, and context in thread sp */
- rt_interrupt_nest = 0;
- rt_interrupt_from_thread = 0;
- rt_interrupt_to_thread = 0;
- rt_thread_switch_interrupt_flag = 0;
-}
-
-/**
- * This function will initialize thread stack
- *
- * @param tentry the entry of thread
- * @param parameter the parameter of entry
- * @param stack_addr the beginning stack address
- * @param texit the function will be called when thread exit
- *
- * @return stack address
- */
-rt_uint8_t *rt_hw_stack_init(void *tentry,
- void *parameter,
- rt_uint8_t *stack_addr,
- void *texit)
-{
- rt_uint16_t *pstk16;
- rt_uint16_t flag;
-
- flag = 0x0040;
- pstk16 = (rt_uint16_t *)stack_addr;
-
- *pstk16-- = (rt_uint32_t)texit >> 16L;
- *pstk16-- = (rt_uint32_t)texit & 0x0000FFFFL;
-
- /* Simulate ISR entry */
- *pstk16-- = (flag&0x00FF) | /* The lowest byte of the FLAG register */
- (((rt_uint32_t)tentry>>8)&0x00000F00) | /* The highest nibble of the PC register */
- ((flag<<4)&0xF000); /* The highest nibble of the FLAG register */
- *pstk16-- = (((rt_uint32_t)tentry)&0x0000FFFF); /* The lowest bytes of the PC register */
-
- /* Save registers onto stack frame */
- *pstk16-- = (rt_uint16_t)0xFBFB; /* FB register */
- *pstk16-- = (rt_uint16_t)0x3B3B; /* SB register */
- *pstk16-- = (rt_uint16_t)0xA1A1; /* A1 register */
- *pstk16-- = (rt_uint16_t)0xA0A0; /* A0 register */
- *pstk16-- = (rt_uint16_t)0x3333; /* R3 register */
- *pstk16-- = (rt_uint32_t)parameter >> 16L; /* Pass argument in R2 register */
- *pstk16-- = (rt_uint32_t)parameter & 0x0000FFFFL; /* Pass argument in R1 register */
- *pstk16 = (rt_uint16_t)0x0000; /* R0 register */
-
- /* return task's current stack address */
- return (rt_uint8_t *)pstk16;
-}
-
-void rt_hw_context_switch(rt_uint32_t from, rt_uint32_t to)
-{
- rt_interrupt_from_thread = from;
- rt_interrupt_to_thread = to;
- asm("INT #0");
-}
-
-void rt_hw_context_switch_interrupt(rt_uint32_t from, rt_uint32_t to)
-{
- if (rt_thread_switch_interrupt_flag != 1)
- {
- rt_thread_switch_interrupt_flag = 1;
- rt_interrupt_from_thread = from;
- }
- rt_interrupt_to_thread = to;
-}
-
-#if defined(__GNUC__)
-rt_base_t rt_hw_interrupt_disable(void)
-{
- register rt_uint16_t temp;
-
- asm("STC FLG, %0":"=r" (temp));
- asm("FCLR I");
-
- return (rt_base_t)temp;
-}
-
-void rt_hw_interrupt_enable(rt_base_t level)
-{
- register rt_uint16_t temp;
-
- temp = level & 0xffff;
- asm("LDC %0, FLG": :"r" (temp));
-}
+/* + * File : cpuport.c + * This file is part of RT-Thread RTOS + * COPYRIGHT (C) 2009 - 2012, RT-Thread Development Team + * + * The license and distribution terms for this file may be + * found in the file LICENSE in this distribution or at + * http://www.rt-thread.org/license/LICENSE + * + * Change Logs: + * Date Author Notes + * 2011-02-23 Bernard the first version + * 2012-09-25 lgnq save texit address in to thread stack + */ + +#include <rtthread.h> + +extern volatile rt_uint8_t rt_interrupt_nest; + +/* switch flag on interrupt and thread pointer to save switch record */ +rt_uint32_t rt_interrupt_from_thread; +rt_uint32_t rt_interrupt_to_thread; +rt_uint8_t rt_thread_switch_interrupt_flag; + +/** + * This function will initialize hardware interrupt + */ +void rt_hw_interrupt_init(void) +{ + /* init interrupt nest, and context in thread sp */ + rt_interrupt_nest = 0; + rt_interrupt_from_thread = 0; + rt_interrupt_to_thread = 0; + rt_thread_switch_interrupt_flag = 0; +} + +/** + * This function will initialize thread stack + * + * @param tentry the entry of thread + * @param parameter the parameter of entry + * @param stack_addr the beginning stack address + * @param texit the function will be called when thread exit + * + * @return stack address + */ +rt_uint8_t *rt_hw_stack_init(void *tentry, + void *parameter, + rt_uint8_t *stack_addr, + void *texit) +{ + rt_uint16_t *pstk16; + rt_uint16_t flag; + + flag = 0x0040; + pstk16 = (rt_uint16_t *)stack_addr; + + *pstk16-- = (rt_uint32_t)texit >> 16L; + *pstk16-- = (rt_uint32_t)texit & 0x0000FFFFL; + + /* Simulate ISR entry */ + *pstk16-- = (flag&0x00FF) | /* The lowest byte of the FLAG register */ + (((rt_uint32_t)tentry>>8)&0x00000F00) | /* The highest nibble of the PC register */ + ((flag<<4)&0xF000); /* The highest nibble of the FLAG register */ + *pstk16-- = (((rt_uint32_t)tentry)&0x0000FFFF); /* The lowest bytes of the PC register */ + + /* Save registers onto stack frame */ + *pstk16-- = (rt_uint16_t)0xFBFB; /* FB register */ + *pstk16-- = (rt_uint16_t)0x3B3B; /* SB register */ + *pstk16-- = (rt_uint16_t)0xA1A1; /* A1 register */ + *pstk16-- = (rt_uint16_t)0xA0A0; /* A0 register */ + *pstk16-- = (rt_uint16_t)0x3333; /* R3 register */ + *pstk16-- = (rt_uint32_t)parameter >> 16L; /* Pass argument in R2 register */ + *pstk16-- = (rt_uint32_t)parameter & 0x0000FFFFL; /* Pass argument in R1 register */ + *pstk16 = (rt_uint16_t)0x0000; /* R0 register */ + + /* return task's current stack address */ + return (rt_uint8_t *)pstk16; +} + +void rt_hw_context_switch(rt_uint32_t from, rt_uint32_t to) +{ + rt_interrupt_from_thread = from; + rt_interrupt_to_thread = to; + asm("INT #0"); +} + +void rt_hw_context_switch_interrupt(rt_uint32_t from, rt_uint32_t to) +{ + if (rt_thread_switch_interrupt_flag != 1) + { + rt_thread_switch_interrupt_flag = 1; + rt_interrupt_from_thread = from; + } + rt_interrupt_to_thread = to; +} + +#if defined(__GNUC__) +rt_base_t rt_hw_interrupt_disable(void) +{ + register rt_uint16_t temp; + + asm("STC FLG, %0":"=r" (temp)); + asm("FCLR I"); + + return (rt_base_t)temp; +} + +void rt_hw_interrupt_enable(rt_base_t level) +{ + register rt_uint16_t temp; + + temp = level & 0xffff; + asm("LDC %0, FLG": :"r" (temp)); +} #endif
\ No newline at end of file diff --git a/libcpu/mips/common/asm.h b/libcpu/mips/common/asm.h index 7a4fb81398..190e8b110e 100644 --- a/libcpu/mips/common/asm.h +++ b/libcpu/mips/common/asm.h @@ -1,220 +1,220 @@ -/*
- * This file is subject to the terms and conditions of the GNU General Public
- * License. See the file "COPYING" in the main directory of this archive
- * for more details.
- *
- * Copyright (C) 1995, 1996, 1997, 1999, 2001 by Ralf Baechle
- * Copyright (C) 1999 by Silicon Graphics, Inc.
- * Copyright (C) 2001 MIPS Technologies, Inc.
- * Copyright (C) 2002 Maciej W. Rozycki
- *
- * Some useful macros for MIPS assembler code
- *
- * Some of the routines below contain useless nops that will be optimized
- * away by gas in -O mode. These nops are however required to fill delay
- * slots in noreorder mode.
- */
-#ifndef __ASM_H__
-#define __ASM_H__
-
-/*
- * LEAF - declare leaf routine
- */
-#define LEAF(symbol) \
- .globl symbol; \
- .align 2; \
- .type symbol,@function; \
- .ent symbol,0; \
-symbol: .frame sp,0,ra
-
-/*
- * NESTED - declare nested routine entry point
- */
-#define NESTED(symbol, framesize, rpc) \
- .globl symbol; \
- .align 2; \
- .type symbol,@function; \
- .ent symbol,0; \
-symbol: .frame sp, framesize, rpc
-
-/*
- * END - mark end of function
- */
-#define END(function) \
- .end function; \
- .size function,.-function
-
-/*
- * EXPORT - export definition of symbol
- */
-#define EXPORT(symbol) \
- .globl symbol; \
-symbol:
-
-/*
- * FEXPORT - export definition of a function symbol
- */
-#define FEXPORT(symbol) \
- .globl symbol; \
- .type symbol,@function; \
-symbol:
-
-/*
- * Global data declaration with size.
- */
-#define EXPORTS(name,sz) \
- .globl name; \
- .type name,@object; \
- .size name,sz; \
-name:
-
-/*
- * Weak data declaration with size.
- */
-#define WEXPORT(name,sz) \
- .weakext name; \
- .type name,@object; \
- .size name,sz; \
-name:
-
-/*
- * Global data reference with size.
- */
-#define IMPORT(name, size) \
- .extern name,size
-
-/*
- * Global zeroed data.
- */
-#define BSS(name,size) \
- .type name,@object; \
- .comm name,size
-
-/*
- * Local zeroed data.
- */
-#define LBSS(name,size) \
- .lcomm name,size
-
-
-/*
- * ABS - export absolute symbol
- */
-#define ABS(symbol,value) \
- .globl symbol; \
-symbol = value
-
-
-#define TEXT(msg) \
- .pushsection .data; \
-8: .asciiz msg; \
- .popsection;
-
-
-#define ENTRY(name) \
- .globl name; \
- .align 2; \
- .ent name,0; \
- name##:
-
-/*
- * Macros to handle different pointer/register sizes for 32/64-bit code
- */
-
-/*
- * Size of a register
- */
-#define SZREG 4
-
-
-/*
- * Use the following macros in assemblercode to load/store registers,
- * pointers etc.
- */
-#define REG_S sw
-#define REG_L lw
-#define REG_SUBU subu
-#define REG_ADDU addu
-
-
-/*
- * How to add/sub/load/store/shift C int variables.
- */
-#define INT_ADD add
-#define INT_ADDU addu
-#define INT_ADDI addi
-#define INT_ADDIU addiu
-#define INT_SUB sub
-#define INT_SUBU subu
-#define INT_L lw
-#define INT_S sw
-#define INT_SLL sll
-#define INT_SLLV sllv
-#define INT_SRL srl
-#define INT_SRLV srlv
-#define INT_SRA sra
-#define INT_SRAV srav
-
-
-
-/*
- * How to add/sub/load/store/shift C long variables.
- */
-#define LONG_ADD add
-#define LONG_ADDU addu
-#define LONG_ADDI addi
-#define LONG_ADDIU addiu
-#define LONG_SUB sub
-#define LONG_SUBU subu
-#define LONG_L lw
-#define LONG_S sw
-#define LONG_SLL sll
-#define LONG_SLLV sllv
-#define LONG_SRL srl
-#define LONG_SRLV srlv
-#define LONG_SRA sra
-#define LONG_SRAV srav
-
-#define LONG .word
-#define LONGSIZE 4
-#define LONGMASK 3
-#define LONGLOG 2
-
-
-
-/*
- * How to add/sub/load/store/shift pointers.
- */
-#define PTR_ADD add
-#define PTR_ADDU addu
-#define PTR_ADDI addi
-#define PTR_ADDIU addiu
-#define PTR_SUB sub
-#define PTR_SUBU subu
-#define PTR_L lw
-#define PTR_S sw
-#define PTR_LA la
-#define PTR_SLL sll
-#define PTR_SLLV sllv
-#define PTR_SRL srl
-#define PTR_SRLV srlv
-#define PTR_SRA sra
-#define PTR_SRAV srav
-
-#define PTR_SCALESHIFT 2
-
-#define PTR .word
-#define PTRSIZE 4
-#define PTRLOG 2
-
-
-/*
- * Some cp0 registers were extended to 64bit for MIPS III.
- */
-#define MFC0 mfc0
-#define MTC0 mtc0
-
-
-#define SSNOP sll zero, zero, 1
-
-#endif /* end of __ASM_H__ */
+/* + * This file is subject to the terms and conditions of the GNU General Public + * License. See the file "COPYING" in the main directory of this archive + * for more details. + * + * Copyright (C) 1995, 1996, 1997, 1999, 2001 by Ralf Baechle + * Copyright (C) 1999 by Silicon Graphics, Inc. + * Copyright (C) 2001 MIPS Technologies, Inc. + * Copyright (C) 2002 Maciej W. Rozycki + * + * Some useful macros for MIPS assembler code + * + * Some of the routines below contain useless nops that will be optimized + * away by gas in -O mode. These nops are however required to fill delay + * slots in noreorder mode. + */ +#ifndef __ASM_H__ +#define __ASM_H__ + +/* + * LEAF - declare leaf routine + */ +#define LEAF(symbol) \ + .globl symbol; \ + .align 2; \ + .type symbol,@function; \ + .ent symbol,0; \ +symbol: .frame sp,0,ra + +/* + * NESTED - declare nested routine entry point + */ +#define NESTED(symbol, framesize, rpc) \ + .globl symbol; \ + .align 2; \ + .type symbol,@function; \ + .ent symbol,0; \ +symbol: .frame sp, framesize, rpc + +/* + * END - mark end of function + */ +#define END(function) \ + .end function; \ + .size function,.-function + +/* + * EXPORT - export definition of symbol + */ +#define EXPORT(symbol) \ + .globl symbol; \ +symbol: + +/* + * FEXPORT - export definition of a function symbol + */ +#define FEXPORT(symbol) \ + .globl symbol; \ + .type symbol,@function; \ +symbol: + +/* + * Global data declaration with size. + */ +#define EXPORTS(name,sz) \ + .globl name; \ + .type name,@object; \ + .size name,sz; \ +name: + +/* + * Weak data declaration with size. + */ +#define WEXPORT(name,sz) \ + .weakext name; \ + .type name,@object; \ + .size name,sz; \ +name: + +/* + * Global data reference with size. + */ +#define IMPORT(name, size) \ + .extern name,size + +/* + * Global zeroed data. + */ +#define BSS(name,size) \ + .type name,@object; \ + .comm name,size + +/* + * Local zeroed data. + */ +#define LBSS(name,size) \ + .lcomm name,size + + +/* + * ABS - export absolute symbol + */ +#define ABS(symbol,value) \ + .globl symbol; \ +symbol = value + + +#define TEXT(msg) \ + .pushsection .data; \ +8: .asciiz msg; \ + .popsection; + + +#define ENTRY(name) \ + .globl name; \ + .align 2; \ + .ent name,0; \ + name##: + +/* + * Macros to handle different pointer/register sizes for 32/64-bit code + */ + +/* + * Size of a register + */ +#define SZREG 4 + + +/* + * Use the following macros in assemblercode to load/store registers, + * pointers etc. + */ +#define REG_S sw +#define REG_L lw +#define REG_SUBU subu +#define REG_ADDU addu + + +/* + * How to add/sub/load/store/shift C int variables. + */ +#define INT_ADD add +#define INT_ADDU addu +#define INT_ADDI addi +#define INT_ADDIU addiu +#define INT_SUB sub +#define INT_SUBU subu +#define INT_L lw +#define INT_S sw +#define INT_SLL sll +#define INT_SLLV sllv +#define INT_SRL srl +#define INT_SRLV srlv +#define INT_SRA sra +#define INT_SRAV srav + + + +/* + * How to add/sub/load/store/shift C long variables. + */ +#define LONG_ADD add +#define LONG_ADDU addu +#define LONG_ADDI addi +#define LONG_ADDIU addiu +#define LONG_SUB sub +#define LONG_SUBU subu +#define LONG_L lw +#define LONG_S sw +#define LONG_SLL sll +#define LONG_SLLV sllv +#define LONG_SRL srl +#define LONG_SRLV srlv +#define LONG_SRA sra +#define LONG_SRAV srav + +#define LONG .word +#define LONGSIZE 4 +#define LONGMASK 3 +#define LONGLOG 2 + + + +/* + * How to add/sub/load/store/shift pointers. + */ +#define PTR_ADD add +#define PTR_ADDU addu +#define PTR_ADDI addi +#define PTR_ADDIU addiu +#define PTR_SUB sub +#define PTR_SUBU subu +#define PTR_L lw +#define PTR_S sw +#define PTR_LA la +#define PTR_SLL sll +#define PTR_SLLV sllv +#define PTR_SRL srl +#define PTR_SRLV srlv +#define PTR_SRA sra +#define PTR_SRAV srav + +#define PTR_SCALESHIFT 2 + +#define PTR .word +#define PTRSIZE 4 +#define PTRLOG 2 + + +/* + * Some cp0 registers were extended to 64bit for MIPS III. + */ +#define MFC0 mfc0 +#define MTC0 mtc0 + + +#define SSNOP sll zero, zero, 1 + +#endif /* end of __ASM_H__ */ diff --git a/libcpu/mips/common/cache.c b/libcpu/mips/common/cache.c index de9a112f50..e5a9945e3e 100644 --- a/libcpu/mips/common/cache.c +++ b/libcpu/mips/common/cache.c @@ -1,114 +1,114 @@ -/*
- * File : cache.c
- * This file is part of RT-Thread RTOS
- * COPYRIGHT (C) 2010, RT-Thread Development Team
- *
- * The license and distribution terms for this file may be
- * found in the file LICENSE in this distribution or at
- * http://www.rt-thread.org/license/LICENSE
- *
- * Change Logs:
- * Date Author Notes
- * 2010-05-17 swkyer first version
- */
-#include <rtthread.h>
-#include "mipscfg.h"
-#include "cache.h"
-
-
-extern void cache_init(rt_ubase_t cache_size, rt_ubase_t cache_line_size);
-void r4k_cache_init(void)
-{
- cache_init(dcache_size, cpu_dcache_line_size());
-}
-
-void r4k_cache_flush_all(void)
-{
- blast_dcache16();
- blast_icache16();
-}
-
-void r4k_icache_flush_all(void)
-{
- blast_icache16();
-}
-
-void r4k_icache_flush_range(rt_ubase_t addr, rt_ubase_t size)
-{
- rt_ubase_t end, a;
-
- if (size > icache_size)
- {
- blast_icache16();
- }
- else
- {
- rt_ubase_t ic_lsize = cpu_icache_line_size();
-
- a = addr & ~(ic_lsize - 1);
- end = ((addr + size) - 1) & ~(ic_lsize - 1);
- while (1)
- {
- flush_icache_line(a);
- if (a == end)
- break;
- a += ic_lsize;
- }
- }
-}
-
-void r4k_icache_lock_range(rt_ubase_t addr, rt_ubase_t size)
-{
- rt_ubase_t end, a;
- rt_ubase_t ic_lsize = cpu_icache_line_size();
-
- a = addr & ~(ic_lsize - 1);
- end = ((addr + size) - 1) & ~(ic_lsize - 1);
- while (1)
- {
- lock_icache_line(a);
- if (a == end)
- break;
- a += ic_lsize;
- }
-}
-
-void r4k_dcache_inv(rt_ubase_t addr, rt_ubase_t size)
-{
- rt_ubase_t end, a;
- rt_ubase_t dc_lsize = cpu_dcache_line_size();
-
- a = addr & ~(dc_lsize - 1);
- end = ((addr + size) - 1) & ~(dc_lsize - 1);
- while (1)
- {
- invalidate_dcache_line(a);
- if (a == end)
- break;
- a += dc_lsize;
- }
-}
-
-void r4k_dcache_wback_inv(rt_ubase_t addr, rt_ubase_t size)
-{
- rt_ubase_t end, a;
-
- if (size >= dcache_size)
- {
- blast_dcache16();
- }
- else
- {
- rt_ubase_t dc_lsize = cpu_dcache_line_size();
-
- a = addr & ~(dc_lsize - 1);
- end = ((addr + size) - 1) & ~(dc_lsize - 1);
- while (1)
- {
- flush_dcache_line(a);
- if (a == end)
- break;
- a += dc_lsize;
- }
- }
-}
+/* + * File : cache.c + * This file is part of RT-Thread RTOS + * COPYRIGHT (C) 2010, RT-Thread Development Team + * + * The license and distribution terms for this file may be + * found in the file LICENSE in this distribution or at + * http://www.rt-thread.org/license/LICENSE + * + * Change Logs: + * Date Author Notes + * 2010-05-17 swkyer first version + */ +#include <rtthread.h> +#include "mipscfg.h" +#include "cache.h" + + +extern void cache_init(rt_ubase_t cache_size, rt_ubase_t cache_line_size); +void r4k_cache_init(void) +{ + cache_init(dcache_size, cpu_dcache_line_size()); +} + +void r4k_cache_flush_all(void) +{ + blast_dcache16(); + blast_icache16(); +} + +void r4k_icache_flush_all(void) +{ + blast_icache16(); +} + +void r4k_icache_flush_range(rt_ubase_t addr, rt_ubase_t size) +{ + rt_ubase_t end, a; + + if (size > icache_size) + { + blast_icache16(); + } + else + { + rt_ubase_t ic_lsize = cpu_icache_line_size(); + + a = addr & ~(ic_lsize - 1); + end = ((addr + size) - 1) & ~(ic_lsize - 1); + while (1) + { + flush_icache_line(a); + if (a == end) + break; + a += ic_lsize; + } + } +} + +void r4k_icache_lock_range(rt_ubase_t addr, rt_ubase_t size) +{ + rt_ubase_t end, a; + rt_ubase_t ic_lsize = cpu_icache_line_size(); + + a = addr & ~(ic_lsize - 1); + end = ((addr + size) - 1) & ~(ic_lsize - 1); + while (1) + { + lock_icache_line(a); + if (a == end) + break; + a += ic_lsize; + } +} + +void r4k_dcache_inv(rt_ubase_t addr, rt_ubase_t size) +{ + rt_ubase_t end, a; + rt_ubase_t dc_lsize = cpu_dcache_line_size(); + + a = addr & ~(dc_lsize - 1); + end = ((addr + size) - 1) & ~(dc_lsize - 1); + while (1) + { + invalidate_dcache_line(a); + if (a == end) + break; + a += dc_lsize; + } +} + +void r4k_dcache_wback_inv(rt_ubase_t addr, rt_ubase_t size) +{ + rt_ubase_t end, a; + + if (size >= dcache_size) + { + blast_dcache16(); + } + else + { + rt_ubase_t dc_lsize = cpu_dcache_line_size(); + + a = addr & ~(dc_lsize - 1); + end = ((addr + size) - 1) & ~(dc_lsize - 1); + while (1) + { + flush_dcache_line(a); + if (a == end) + break; + a += dc_lsize; + } + } +} diff --git a/libcpu/mips/common/cache.h b/libcpu/mips/common/cache.h index 579be8ff9b..1c7cf41324 100644 --- a/libcpu/mips/common/cache.h +++ b/libcpu/mips/common/cache.h @@ -1,232 +1,232 @@ -/*
- * Cache operations for the cache instruction.
- *
- * This file is subject to the terms and conditions of the GNU General Public
- * License. See the file "COPYING" in the main directory of this archive
- * for more details.
- *
- * (C) Copyright 1996, 97, 99, 2002, 03 Ralf Baechle
- * (C) Copyright 1999 Silicon Graphics, Inc.
- */
-#ifndef __CACHE_H__
-#define __CACHE_H__
-
-
-#define KUSEG 0x00000000
-#define KSEG0 0x80000000
-#define KSEG1 0xa0000000
-#define KSEG2 0xc0000000
-#define KSEG3 0xe0000000
-
-/*
- * Cache Operations available on all MIPS processors with R4000-style caches
- */
-#define Index_Invalidate_I 0x00
-#define Index_Writeback_Inv_D 0x01
-#define Index_Load_Tag_I 0x04
-#define Index_Load_Tag_D 0x05
-#define Index_Store_Tag_I 0x08
-#define Index_Store_Tag_D 0x09
-
-#define Hit_Invalidate_I 0x10
-#define Hit_Invalidate_D 0x11
-#define Hit_Writeback_Inv_D 0x15
-#define Hit_Writeback_I 0x18
-#define Hit_Writeback_D 0x19
-
-/*
- *The lock state is cleared by executing an Index
-Invalidate, Index Writeback Invalidate, Hit
-Invalidate, or Hit Writeback Invalidate
-operation to the locked line, or via an Index
-Store Tag operation with the lock bit reset in
-the TagLo register.
- */
-#define Fetch_And_Lock_I 0x1c
-#define Fetch_And_Lock_D 0x1d
-/*
- * R4000-specific cacheops
- */
-#define Create_Dirty_Excl_D 0x0d
-#define Fill 0x14
-
-/*
- * R4000SC and R4400SC-specific cacheops
- */
-#define Index_Invalidate_SI 0x02
-#define Index_Writeback_Inv_SD 0x03
-#define Index_Load_Tag_SI 0x06
-#define Index_Load_Tag_SD 0x07
-#define Index_Store_Tag_SI 0x0A
-#define Index_Store_Tag_SD 0x0B
-#define Create_Dirty_Excl_SD 0x0f
-#define Hit_Invalidate_SI 0x12
-#define Hit_Invalidate_SD 0x13
-#define Hit_Writeback_Inv_SD 0x17
-#define Hit_Writeback_SD 0x1b
-#define Hit_Set_Virtual_SI 0x1e
-#define Hit_Set_Virtual_SD 0x1f
-
-/*
- * R5000-specific cacheops
- */
-#define R5K_Page_Invalidate_S 0x17
-
-/*
- * RM7000-specific cacheops
- */
-#define Page_Invalidate_T 0x16
-
-/*
- * R1000-specific cacheops
- *
- * Cacheops 0x02, 0x06, 0x0a, 0x0c-0x0e, 0x16, 0x1a and 0x1e are unused.
- * Most of the _S cacheops are identical to the R4000SC _SD cacheops.
- */
-#define Index_Writeback_Inv_S 0x03
-#define Index_Load_Tag_S 0x07
-#define Index_Store_Tag_S 0x0B
-#define Hit_Invalidate_S 0x13
-#define Cache_Barrier 0x14
-#define Hit_Writeback_Inv_S 0x17
-#define Index_Load_Data_I 0x18
-#define Index_Load_Data_D 0x19
-#define Index_Load_Data_S 0x1b
-#define Index_Store_Data_I 0x1c
-#define Index_Store_Data_D 0x1d
-#define Index_Store_Data_S 0x1f
-
-
-#ifndef __ASSEMBLER__
-
-#ifndef dcache_size
-#define dcache_size (g_mips_core.dcache_ways * g_mips_core.dcache_lines_per_way * g_mips_core.dcache_line_size)
-#endif
-
-#ifndef icache_size
-#define icache_size (g_mips_core.dcache_ways * g_mips_core.dcache_lines_per_way * g_mips_core.dcache_line_size)
-#endif
-
-#ifndef cpu_dcache_line_size
-#define cpu_dcache_line_size() g_mips_core.icache_line_size
-#endif
-
-#ifndef cpu_icache_line_size
-#define cpu_icache_line_size() g_mips_core.icache_line_size
-#endif
-
-#define cache_op(op, addr) \
- __asm__ __volatile__( \
- " .set noreorder \n" \
- " .set mips3\n\t \n" \
- " cache %0, %1 \n" \
- " .set mips0 \n" \
- " .set reorder" \
- : \
- : "i" (op), "m" (*(unsigned char *)(addr)))
-
-#define cache16_unroll32(base, op) \
- __asm__ __volatile__( \
- " .set noreorder \n" \
- " .set mips3 \n" \
- " cache %1, 0x000(%0); cache %1, 0x010(%0) \n" \
- " cache %1, 0x020(%0); cache %1, 0x030(%0) \n" \
- " cache %1, 0x040(%0); cache %1, 0x050(%0) \n" \
- " cache %1, 0x060(%0); cache %1, 0x070(%0) \n" \
- " cache %1, 0x080(%0); cache %1, 0x090(%0) \n" \
- " cache %1, 0x0a0(%0); cache %1, 0x0b0(%0) \n" \
- " cache %1, 0x0c0(%0); cache %1, 0x0d0(%0) \n" \
- " cache %1, 0x0e0(%0); cache %1, 0x0f0(%0) \n" \
- " cache %1, 0x100(%0); cache %1, 0x110(%0) \n" \
- " cache %1, 0x120(%0); cache %1, 0x130(%0) \n" \
- " cache %1, 0x140(%0); cache %1, 0x150(%0) \n" \
- " cache %1, 0x160(%0); cache %1, 0x170(%0) \n" \
- " cache %1, 0x180(%0); cache %1, 0x190(%0) \n" \
- " cache %1, 0x1a0(%0); cache %1, 0x1b0(%0) \n" \
- " cache %1, 0x1c0(%0); cache %1, 0x1d0(%0) \n" \
- " cache %1, 0x1e0(%0); cache %1, 0x1f0(%0) \n" \
- " .set mips0 \n" \
- " .set reorder \n" \
- : \
- : "r" (base), \
- "i" (op));
-
-
-static inline void flush_icache_line_indexed(rt_ubase_t addr)
-{
- cache_op(Index_Invalidate_I, addr);
-}
-
-static inline void flush_dcache_line_indexed(rt_ubase_t addr)
-{
- cache_op(Index_Writeback_Inv_D, addr);
-}
-
-static inline void flush_icache_line(rt_ubase_t addr)
-{
- cache_op(Hit_Invalidate_I, addr);
-}
-
-static inline void lock_icache_line(rt_ubase_t addr)
-{
- cache_op(Fetch_And_Lock_I, addr);
-}
-
-static inline void lock_dcache_line(rt_ubase_t addr)
-{
- cache_op(Fetch_And_Lock_D, addr);
-}
-
-static inline void flush_dcache_line(rt_ubase_t addr)
-{
- cache_op(Hit_Writeback_Inv_D, addr);
-}
-
-static inline void invalidate_dcache_line(rt_ubase_t addr)
-{
- cache_op(Hit_Invalidate_D, addr);
-}
-
-static inline void blast_dcache16(void)
-{
- rt_ubase_t start = KSEG0;
- rt_ubase_t end = start + dcache_size;
- rt_ubase_t addr;
-
- for (addr = start; addr < end; addr += 0x200)
- cache16_unroll32(addr, Index_Writeback_Inv_D);
-}
-
-static inline void inv_dcache16(void)
-{
- rt_ubase_t start = KSEG0;
- rt_ubase_t end = start + dcache_size;
- rt_ubase_t addr;
-
- for (addr = start; addr < end; addr += 0x200)
- cache16_unroll32(addr, Hit_Invalidate_D);
-}
-
-static inline void blast_icache16(void)
-{
- rt_ubase_t start = KSEG0;
- rt_ubase_t end = start + icache_size;
- rt_ubase_t addr;
-
- for (addr = start; addr < end; addr += 0x200)
- cache16_unroll32(addr, Index_Invalidate_I);
-}
-
-
-
-void r4k_cache_init(void);
-void r4k_cache_flush_all(void);
-void r4k_icache_flush_all(void);
-void r4k_icache_flush_range(rt_ubase_t addr, rt_ubase_t size);
-void r4k_icache_lock_range(rt_ubase_t addr, rt_ubase_t size);
-void r4k_dcache_inv(rt_ubase_t addr, rt_ubase_t size);
-void r4k_dcache_wback_inv(rt_ubase_t addr, rt_ubase_t size);
-
-#endif /*end of __ASSEMBLER__ */
-
-#endif /* end of __CACHE_H__ */
+/* + * Cache operations for the cache instruction. + * + * This file is subject to the terms and conditions of the GNU General Public + * License. See the file "COPYING" in the main directory of this archive + * for more details. + * + * (C) Copyright 1996, 97, 99, 2002, 03 Ralf Baechle + * (C) Copyright 1999 Silicon Graphics, Inc. + */ +#ifndef __CACHE_H__ +#define __CACHE_H__ + + +#define KUSEG 0x00000000 +#define KSEG0 0x80000000 +#define KSEG1 0xa0000000 +#define KSEG2 0xc0000000 +#define KSEG3 0xe0000000 + +/* + * Cache Operations available on all MIPS processors with R4000-style caches + */ +#define Index_Invalidate_I 0x00 +#define Index_Writeback_Inv_D 0x01 +#define Index_Load_Tag_I 0x04 +#define Index_Load_Tag_D 0x05 +#define Index_Store_Tag_I 0x08 +#define Index_Store_Tag_D 0x09 + +#define Hit_Invalidate_I 0x10 +#define Hit_Invalidate_D 0x11 +#define Hit_Writeback_Inv_D 0x15 +#define Hit_Writeback_I 0x18 +#define Hit_Writeback_D 0x19 + +/* + *The lock state is cleared by executing an Index +Invalidate, Index Writeback Invalidate, Hit +Invalidate, or Hit Writeback Invalidate +operation to the locked line, or via an Index +Store Tag operation with the lock bit reset in +the TagLo register. + */ +#define Fetch_And_Lock_I 0x1c +#define Fetch_And_Lock_D 0x1d +/* + * R4000-specific cacheops + */ +#define Create_Dirty_Excl_D 0x0d +#define Fill 0x14 + +/* + * R4000SC and R4400SC-specific cacheops + */ +#define Index_Invalidate_SI 0x02 +#define Index_Writeback_Inv_SD 0x03 +#define Index_Load_Tag_SI 0x06 +#define Index_Load_Tag_SD 0x07 +#define Index_Store_Tag_SI 0x0A +#define Index_Store_Tag_SD 0x0B +#define Create_Dirty_Excl_SD 0x0f +#define Hit_Invalidate_SI 0x12 +#define Hit_Invalidate_SD 0x13 +#define Hit_Writeback_Inv_SD 0x17 +#define Hit_Writeback_SD 0x1b +#define Hit_Set_Virtual_SI 0x1e +#define Hit_Set_Virtual_SD 0x1f + +/* + * R5000-specific cacheops + */ +#define R5K_Page_Invalidate_S 0x17 + +/* + * RM7000-specific cacheops + */ +#define Page_Invalidate_T 0x16 + +/* + * R1000-specific cacheops + * + * Cacheops 0x02, 0x06, 0x0a, 0x0c-0x0e, 0x16, 0x1a and 0x1e are unused. + * Most of the _S cacheops are identical to the R4000SC _SD cacheops. + */ +#define Index_Writeback_Inv_S 0x03 +#define Index_Load_Tag_S 0x07 +#define Index_Store_Tag_S 0x0B +#define Hit_Invalidate_S 0x13 +#define Cache_Barrier 0x14 +#define Hit_Writeback_Inv_S 0x17 +#define Index_Load_Data_I 0x18 +#define Index_Load_Data_D 0x19 +#define Index_Load_Data_S 0x1b +#define Index_Store_Data_I 0x1c +#define Index_Store_Data_D 0x1d +#define Index_Store_Data_S 0x1f + + +#ifndef __ASSEMBLER__ + +#ifndef dcache_size +#define dcache_size (g_mips_core.dcache_ways * g_mips_core.dcache_lines_per_way * g_mips_core.dcache_line_size) +#endif + +#ifndef icache_size +#define icache_size (g_mips_core.dcache_ways * g_mips_core.dcache_lines_per_way * g_mips_core.dcache_line_size) +#endif + +#ifndef cpu_dcache_line_size +#define cpu_dcache_line_size() g_mips_core.icache_line_size +#endif + +#ifndef cpu_icache_line_size +#define cpu_icache_line_size() g_mips_core.icache_line_size +#endif + +#define cache_op(op, addr) \ + __asm__ __volatile__( \ + " .set noreorder \n" \ + " .set mips3\n\t \n" \ + " cache %0, %1 \n" \ + " .set mips0 \n" \ + " .set reorder" \ + : \ + : "i" (op), "m" (*(unsigned char *)(addr))) + +#define cache16_unroll32(base, op) \ + __asm__ __volatile__( \ + " .set noreorder \n" \ + " .set mips3 \n" \ + " cache %1, 0x000(%0); cache %1, 0x010(%0) \n" \ + " cache %1, 0x020(%0); cache %1, 0x030(%0) \n" \ + " cache %1, 0x040(%0); cache %1, 0x050(%0) \n" \ + " cache %1, 0x060(%0); cache %1, 0x070(%0) \n" \ + " cache %1, 0x080(%0); cache %1, 0x090(%0) \n" \ + " cache %1, 0x0a0(%0); cache %1, 0x0b0(%0) \n" \ + " cache %1, 0x0c0(%0); cache %1, 0x0d0(%0) \n" \ + " cache %1, 0x0e0(%0); cache %1, 0x0f0(%0) \n" \ + " cache %1, 0x100(%0); cache %1, 0x110(%0) \n" \ + " cache %1, 0x120(%0); cache %1, 0x130(%0) \n" \ + " cache %1, 0x140(%0); cache %1, 0x150(%0) \n" \ + " cache %1, 0x160(%0); cache %1, 0x170(%0) \n" \ + " cache %1, 0x180(%0); cache %1, 0x190(%0) \n" \ + " cache %1, 0x1a0(%0); cache %1, 0x1b0(%0) \n" \ + " cache %1, 0x1c0(%0); cache %1, 0x1d0(%0) \n" \ + " cache %1, 0x1e0(%0); cache %1, 0x1f0(%0) \n" \ + " .set mips0 \n" \ + " .set reorder \n" \ + : \ + : "r" (base), \ + "i" (op)); + + +static inline void flush_icache_line_indexed(rt_ubase_t addr) +{ + cache_op(Index_Invalidate_I, addr); +} + +static inline void flush_dcache_line_indexed(rt_ubase_t addr) +{ + cache_op(Index_Writeback_Inv_D, addr); +} + +static inline void flush_icache_line(rt_ubase_t addr) +{ + cache_op(Hit_Invalidate_I, addr); +} + +static inline void lock_icache_line(rt_ubase_t addr) +{ + cache_op(Fetch_And_Lock_I, addr); +} + +static inline void lock_dcache_line(rt_ubase_t addr) +{ + cache_op(Fetch_And_Lock_D, addr); +} + +static inline void flush_dcache_line(rt_ubase_t addr) +{ + cache_op(Hit_Writeback_Inv_D, addr); +} + +static inline void invalidate_dcache_line(rt_ubase_t addr) +{ + cache_op(Hit_Invalidate_D, addr); +} + +static inline void blast_dcache16(void) +{ + rt_ubase_t start = KSEG0; + rt_ubase_t end = start + dcache_size; + rt_ubase_t addr; + + for (addr = start; addr < end; addr += 0x200) + cache16_unroll32(addr, Index_Writeback_Inv_D); +} + +static inline void inv_dcache16(void) +{ + rt_ubase_t start = KSEG0; + rt_ubase_t end = start + dcache_size; + rt_ubase_t addr; + + for (addr = start; addr < end; addr += 0x200) + cache16_unroll32(addr, Hit_Invalidate_D); +} + +static inline void blast_icache16(void) +{ + rt_ubase_t start = KSEG0; + rt_ubase_t end = start + icache_size; + rt_ubase_t addr; + + for (addr = start; addr < end; addr += 0x200) + cache16_unroll32(addr, Index_Invalidate_I); +} + + + +void r4k_cache_init(void); +void r4k_cache_flush_all(void); +void r4k_icache_flush_all(void); +void r4k_icache_flush_range(rt_ubase_t addr, rt_ubase_t size); +void r4k_icache_lock_range(rt_ubase_t addr, rt_ubase_t size); +void r4k_dcache_inv(rt_ubase_t addr, rt_ubase_t size); +void r4k_dcache_wback_inv(rt_ubase_t addr, rt_ubase_t size); + +#endif /*end of __ASSEMBLER__ */ + +#endif /* end of __CACHE_H__ */ diff --git a/libcpu/mips/common/exception.h b/libcpu/mips/common/exception.h index cd776a77cb..2cb03d20e7 100644 --- a/libcpu/mips/common/exception.h +++ b/libcpu/mips/common/exception.h @@ -1,166 +1,166 @@ -/*
- * File : cpu.c
- * This file is part of RT-Thread RTOS
- * COPYRIGHT (C) 2010, RT-Thread Development Team
- *
- * The license and distribution terms for this file may be
- * found in the file LICENSE in this distribution or at
- * http://www.rt-thread.org/license/LICENSE
- *
- * Change Logs:
- * Date Author Notes
- * 2010-05-17 swkyer first version
- */
-#ifndef __EXCEPTION_H__
-#define __EXCEPTION_H__
-
-
-/*
- * important register numbers
- */
-#define REG_EPC 37
-#define REG_FP 72
-#define REG_SP 29
-
-/*
- * Stack layout for the GDB exception handler
- * Derived from the stack layout described in asm-mips/stackframe.h
- *
- * The first PTRSIZE*6 bytes are argument save space for C subroutines.
- */
-#define NUMREGS 90
-
-#define GDB_FR_REG0 (PTRSIZE*6) /* 0 */
-#define GDB_FR_REG1 ((GDB_FR_REG0) + LONGSIZE) /* 1 */
-#define GDB_FR_REG2 ((GDB_FR_REG1) + LONGSIZE) /* 2 */
-#define GDB_FR_REG3 ((GDB_FR_REG2) + LONGSIZE) /* 3 */
-#define GDB_FR_REG4 ((GDB_FR_REG3) + LONGSIZE) /* 4 */
-#define GDB_FR_REG5 ((GDB_FR_REG4) + LONGSIZE) /* 5 */
-#define GDB_FR_REG6 ((GDB_FR_REG5) + LONGSIZE) /* 6 */
-#define GDB_FR_REG7 ((GDB_FR_REG6) + LONGSIZE) /* 7 */
-#define GDB_FR_REG8 ((GDB_FR_REG7) + LONGSIZE) /* 8 */
-#define GDB_FR_REG9 ((GDB_FR_REG8) + LONGSIZE) /* 9 */
-#define GDB_FR_REG10 ((GDB_FR_REG9) + LONGSIZE) /* 10 */
-#define GDB_FR_REG11 ((GDB_FR_REG10) + LONGSIZE) /* 11 */
-#define GDB_FR_REG12 ((GDB_FR_REG11) + LONGSIZE) /* 12 */
-#define GDB_FR_REG13 ((GDB_FR_REG12) + LONGSIZE) /* 13 */
-#define GDB_FR_REG14 ((GDB_FR_REG13) + LONGSIZE) /* 14 */
-#define GDB_FR_REG15 ((GDB_FR_REG14) + LONGSIZE) /* 15 */
-#define GDB_FR_REG16 ((GDB_FR_REG15) + LONGSIZE) /* 16 */
-#define GDB_FR_REG17 ((GDB_FR_REG16) + LONGSIZE) /* 17 */
-#define GDB_FR_REG18 ((GDB_FR_REG17) + LONGSIZE) /* 18 */
-#define GDB_FR_REG19 ((GDB_FR_REG18) + LONGSIZE) /* 19 */
-#define GDB_FR_REG20 ((GDB_FR_REG19) + LONGSIZE) /* 20 */
-#define GDB_FR_REG21 ((GDB_FR_REG20) + LONGSIZE) /* 21 */
-#define GDB_FR_REG22 ((GDB_FR_REG21) + LONGSIZE) /* 22 */
-#define GDB_FR_REG23 ((GDB_FR_REG22) + LONGSIZE) /* 23 */
-#define GDB_FR_REG24 ((GDB_FR_REG23) + LONGSIZE) /* 24 */
-#define GDB_FR_REG25 ((GDB_FR_REG24) + LONGSIZE) /* 25 */
-#define GDB_FR_REG26 ((GDB_FR_REG25) + LONGSIZE) /* 26 */
-#define GDB_FR_REG27 ((GDB_FR_REG26) + LONGSIZE) /* 27 */
-#define GDB_FR_REG28 ((GDB_FR_REG27) + LONGSIZE) /* 28 */
-#define GDB_FR_REG29 ((GDB_FR_REG28) + LONGSIZE) /* 29 */
-#define GDB_FR_REG30 ((GDB_FR_REG29) + LONGSIZE) /* 30 */
-#define GDB_FR_REG31 ((GDB_FR_REG30) + LONGSIZE) /* 31 */
-
-/*
- * Saved special registers
- */
-#define GDB_FR_STATUS ((GDB_FR_REG31) + LONGSIZE) /* 32 */
-#define GDB_FR_LO ((GDB_FR_STATUS) + LONGSIZE) /* 33 */
-#define GDB_FR_HI ((GDB_FR_LO) + LONGSIZE) /* 34 */
-#define GDB_FR_BADVADDR ((GDB_FR_HI) + LONGSIZE) /* 35 */
-#define GDB_FR_CAUSE ((GDB_FR_BADVADDR) + LONGSIZE) /* 36 */
-#define GDB_FR_EPC ((GDB_FR_CAUSE) + LONGSIZE) /* 37 */
-
-///*
-// * Saved floating point registers
-// */
-//#define GDB_FR_FPR0 ((GDB_FR_EPC) + LONGSIZE) /* 38 */
-//#define GDB_FR_FPR1 ((GDB_FR_FPR0) + LONGSIZE) /* 39 */
-//#define GDB_FR_FPR2 ((GDB_FR_FPR1) + LONGSIZE) /* 40 */
-//#define GDB_FR_FPR3 ((GDB_FR_FPR2) + LONGSIZE) /* 41 */
-//#define GDB_FR_FPR4 ((GDB_FR_FPR3) + LONGSIZE) /* 42 */
-//#define GDB_FR_FPR5 ((GDB_FR_FPR4) + LONGSIZE) /* 43 */
-//#define GDB_FR_FPR6 ((GDB_FR_FPR5) + LONGSIZE) /* 44 */
-//#define GDB_FR_FPR7 ((GDB_FR_FPR6) + LONGSIZE) /* 45 */
-//#define GDB_FR_FPR8 ((GDB_FR_FPR7) + LONGSIZE) /* 46 */
-//#define GDB_FR_FPR9 ((GDB_FR_FPR8) + LONGSIZE) /* 47 */
-//#define GDB_FR_FPR10 ((GDB_FR_FPR9) + LONGSIZE) /* 48 */
-//#define GDB_FR_FPR11 ((GDB_FR_FPR10) + LONGSIZE) /* 49 */
-//#define GDB_FR_FPR12 ((GDB_FR_FPR11) + LONGSIZE) /* 50 */
-//#define GDB_FR_FPR13 ((GDB_FR_FPR12) + LONGSIZE) /* 51 */
-//#define GDB_FR_FPR14 ((GDB_FR_FPR13) + LONGSIZE) /* 52 */
-//#define GDB_FR_FPR15 ((GDB_FR_FPR14) + LONGSIZE) /* 53 */
-//#define GDB_FR_FPR16 ((GDB_FR_FPR15) + LONGSIZE) /* 54 */
-//#define GDB_FR_FPR17 ((GDB_FR_FPR16) + LONGSIZE) /* 55 */
-//#define GDB_FR_FPR18 ((GDB_FR_FPR17) + LONGSIZE) /* 56 */
-//#define GDB_FR_FPR19 ((GDB_FR_FPR18) + LONGSIZE) /* 57 */
-//#define GDB_FR_FPR20 ((GDB_FR_FPR19) + LONGSIZE) /* 58 */
-//#define GDB_FR_FPR21 ((GDB_FR_FPR20) + LONGSIZE) /* 59 */
-//#define GDB_FR_FPR22 ((GDB_FR_FPR21) + LONGSIZE) /* 60 */
-//#define GDB_FR_FPR23 ((GDB_FR_FPR22) + LONGSIZE) /* 61 */
-//#define GDB_FR_FPR24 ((GDB_FR_FPR23) + LONGSIZE) /* 62 */
-//#define GDB_FR_FPR25 ((GDB_FR_FPR24) + LONGSIZE) /* 63 */
-//#define GDB_FR_FPR26 ((GDB_FR_FPR25) + LONGSIZE) /* 64 */
-//#define GDB_FR_FPR27 ((GDB_FR_FPR26) + LONGSIZE) /* 65 */
-//#define GDB_FR_FPR28 ((GDB_FR_FPR27) + LONGSIZE) /* 66 */
-//#define GDB_FR_FPR29 ((GDB_FR_FPR28) + LONGSIZE) /* 67 */
-//#define GDB_FR_FPR30 ((GDB_FR_FPR29) + LONGSIZE) /* 68 */
-//#define GDB_FR_FPR31 ((GDB_FR_FPR30) + LONGSIZE) /* 69 */
-//
-//#define GDB_FR_FSR ((GDB_FR_FPR31) + LONGSIZE) /* 70 */
-//#define GDB_FR_FIR ((GDB_FR_FSR) + LONGSIZE) /* 71 */
-//#define GDB_FR_FRP ((GDB_FR_FIR) + LONGSIZE) /* 72 */
-//
-//#define GDB_FR_DUMMY ((GDB_FR_FRP) + LONGSIZE) /* 73, unused ??? */
-//
-///*
-// * Again, CP0 registers
-// */
-//#define GDB_FR_CP0_INDEX ((GDB_FR_DUMMY) + LONGSIZE) /* 74 */
-#define GDB_FR_FRP ((GDB_FR_EPC) + LONGSIZE) /* 72 */
-#define GDB_FR_CP0_INDEX ((GDB_FR_FRP) + LONGSIZE) /* 74 */
-
-#define GDB_FR_CP0_RANDOM ((GDB_FR_CP0_INDEX) + LONGSIZE) /* 75 */
-#define GDB_FR_CP0_ENTRYLO0 ((GDB_FR_CP0_RANDOM) + LONGSIZE)/* 76 */
-#define GDB_FR_CP0_ENTRYLO1 ((GDB_FR_CP0_ENTRYLO0) + LONGSIZE)/* 77 */
-#define GDB_FR_CP0_CONTEXT ((GDB_FR_CP0_ENTRYLO1) + LONGSIZE)/* 78 */
-#define GDB_FR_CP0_PAGEMASK ((GDB_FR_CP0_CONTEXT) + LONGSIZE)/* 79 */
-#define GDB_FR_CP0_WIRED ((GDB_FR_CP0_PAGEMASK) + LONGSIZE)/* 80 */
-#define GDB_FR_CP0_REG7 ((GDB_FR_CP0_WIRED) + LONGSIZE) /* 81 */
-#define GDB_FR_CP0_REG8 ((GDB_FR_CP0_REG7) + LONGSIZE) /* 82 */
-#define GDB_FR_CP0_REG9 ((GDB_FR_CP0_REG8) + LONGSIZE) /* 83 */
-#define GDB_FR_CP0_ENTRYHI ((GDB_FR_CP0_REG9) + LONGSIZE) /* 84 */
-#define GDB_FR_CP0_REG11 ((GDB_FR_CP0_ENTRYHI) + LONGSIZE)/* 85 */
-#define GDB_FR_CP0_REG12 ((GDB_FR_CP0_REG11) + LONGSIZE) /* 86 */
-#define GDB_FR_CP0_REG13 ((GDB_FR_CP0_REG12) + LONGSIZE) /* 87 */
-#define GDB_FR_CP0_REG14 ((GDB_FR_CP0_REG13) + LONGSIZE) /* 88 */
-#define GDB_FR_CP0_PRID ((GDB_FR_CP0_REG14) + LONGSIZE) /* 89 */
-
-#define GDB_FR_SIZE ((((GDB_FR_CP0_PRID) + LONGSIZE) + (PTRSIZE-1)) & ~(PTRSIZE-1))
-
-/*
- * This is the same as above, but for the high-level
- * part of the INT stub.
- */
-typedef struct pt_regs_s
-{
- /* Saved main processor registers. */
- rt_base_t regs[32];
- /* Saved special registers. */
- rt_base_t cp0_status;
- rt_base_t hi;
- rt_base_t lo;
- rt_base_t cp0_badvaddr;
- rt_base_t cp0_cause;
- rt_base_t cp0_epc;
-} pt_regs_t;
-
-typedef void (* exception_func_t)(pt_regs_t *regs);
-
-extern exception_func_t sys_exception_handlers[];
-exception_func_t rt_set_except_vector(int n, exception_func_t func);
-void install_default_execpt_handle(void);
-
-#endif /* end of __EXCEPTION_H__ */
+/* + * File : cpu.c + * This file is part of RT-Thread RTOS + * COPYRIGHT (C) 2010, RT-Thread Development Team + * + * The license and distribution terms for this file may be + * found in the file LICENSE in this distribution or at + * http://www.rt-thread.org/license/LICENSE + * + * Change Logs: + * Date Author Notes + * 2010-05-17 swkyer first version + */ +#ifndef __EXCEPTION_H__ +#define __EXCEPTION_H__ + + +/* + * important register numbers + */ +#define REG_EPC 37 +#define REG_FP 72 +#define REG_SP 29 + +/* + * Stack layout for the GDB exception handler + * Derived from the stack layout described in asm-mips/stackframe.h + * + * The first PTRSIZE*6 bytes are argument save space for C subroutines. + */ +#define NUMREGS 90 + +#define GDB_FR_REG0 (PTRSIZE*6) /* 0 */ +#define GDB_FR_REG1 ((GDB_FR_REG0) + LONGSIZE) /* 1 */ +#define GDB_FR_REG2 ((GDB_FR_REG1) + LONGSIZE) /* 2 */ +#define GDB_FR_REG3 ((GDB_FR_REG2) + LONGSIZE) /* 3 */ +#define GDB_FR_REG4 ((GDB_FR_REG3) + LONGSIZE) /* 4 */ +#define GDB_FR_REG5 ((GDB_FR_REG4) + LONGSIZE) /* 5 */ +#define GDB_FR_REG6 ((GDB_FR_REG5) + LONGSIZE) /* 6 */ +#define GDB_FR_REG7 ((GDB_FR_REG6) + LONGSIZE) /* 7 */ +#define GDB_FR_REG8 ((GDB_FR_REG7) + LONGSIZE) /* 8 */ +#define GDB_FR_REG9 ((GDB_FR_REG8) + LONGSIZE) /* 9 */ +#define GDB_FR_REG10 ((GDB_FR_REG9) + LONGSIZE) /* 10 */ +#define GDB_FR_REG11 ((GDB_FR_REG10) + LONGSIZE) /* 11 */ +#define GDB_FR_REG12 ((GDB_FR_REG11) + LONGSIZE) /* 12 */ +#define GDB_FR_REG13 ((GDB_FR_REG12) + LONGSIZE) /* 13 */ +#define GDB_FR_REG14 ((GDB_FR_REG13) + LONGSIZE) /* 14 */ +#define GDB_FR_REG15 ((GDB_FR_REG14) + LONGSIZE) /* 15 */ +#define GDB_FR_REG16 ((GDB_FR_REG15) + LONGSIZE) /* 16 */ +#define GDB_FR_REG17 ((GDB_FR_REG16) + LONGSIZE) /* 17 */ +#define GDB_FR_REG18 ((GDB_FR_REG17) + LONGSIZE) /* 18 */ +#define GDB_FR_REG19 ((GDB_FR_REG18) + LONGSIZE) /* 19 */ +#define GDB_FR_REG20 ((GDB_FR_REG19) + LONGSIZE) /* 20 */ +#define GDB_FR_REG21 ((GDB_FR_REG20) + LONGSIZE) /* 21 */ +#define GDB_FR_REG22 ((GDB_FR_REG21) + LONGSIZE) /* 22 */ +#define GDB_FR_REG23 ((GDB_FR_REG22) + LONGSIZE) /* 23 */ +#define GDB_FR_REG24 ((GDB_FR_REG23) + LONGSIZE) /* 24 */ +#define GDB_FR_REG25 ((GDB_FR_REG24) + LONGSIZE) /* 25 */ +#define GDB_FR_REG26 ((GDB_FR_REG25) + LONGSIZE) /* 26 */ +#define GDB_FR_REG27 ((GDB_FR_REG26) + LONGSIZE) /* 27 */ +#define GDB_FR_REG28 ((GDB_FR_REG27) + LONGSIZE) /* 28 */ +#define GDB_FR_REG29 ((GDB_FR_REG28) + LONGSIZE) /* 29 */ +#define GDB_FR_REG30 ((GDB_FR_REG29) + LONGSIZE) /* 30 */ +#define GDB_FR_REG31 ((GDB_FR_REG30) + LONGSIZE) /* 31 */ + +/* + * Saved special registers + */ +#define GDB_FR_STATUS ((GDB_FR_REG31) + LONGSIZE) /* 32 */ +#define GDB_FR_LO ((GDB_FR_STATUS) + LONGSIZE) /* 33 */ +#define GDB_FR_HI ((GDB_FR_LO) + LONGSIZE) /* 34 */ +#define GDB_FR_BADVADDR ((GDB_FR_HI) + LONGSIZE) /* 35 */ +#define GDB_FR_CAUSE ((GDB_FR_BADVADDR) + LONGSIZE) /* 36 */ +#define GDB_FR_EPC ((GDB_FR_CAUSE) + LONGSIZE) /* 37 */ + +///* +// * Saved floating point registers +// */ +//#define GDB_FR_FPR0 ((GDB_FR_EPC) + LONGSIZE) /* 38 */ +//#define GDB_FR_FPR1 ((GDB_FR_FPR0) + LONGSIZE) /* 39 */ +//#define GDB_FR_FPR2 ((GDB_FR_FPR1) + LONGSIZE) /* 40 */ +//#define GDB_FR_FPR3 ((GDB_FR_FPR2) + LONGSIZE) /* 41 */ +//#define GDB_FR_FPR4 ((GDB_FR_FPR3) + LONGSIZE) /* 42 */ +//#define GDB_FR_FPR5 ((GDB_FR_FPR4) + LONGSIZE) /* 43 */ +//#define GDB_FR_FPR6 ((GDB_FR_FPR5) + LONGSIZE) /* 44 */ +//#define GDB_FR_FPR7 ((GDB_FR_FPR6) + LONGSIZE) /* 45 */ +//#define GDB_FR_FPR8 ((GDB_FR_FPR7) + LONGSIZE) /* 46 */ +//#define GDB_FR_FPR9 ((GDB_FR_FPR8) + LONGSIZE) /* 47 */ +//#define GDB_FR_FPR10 ((GDB_FR_FPR9) + LONGSIZE) /* 48 */ +//#define GDB_FR_FPR11 ((GDB_FR_FPR10) + LONGSIZE) /* 49 */ +//#define GDB_FR_FPR12 ((GDB_FR_FPR11) + LONGSIZE) /* 50 */ +//#define GDB_FR_FPR13 ((GDB_FR_FPR12) + LONGSIZE) /* 51 */ +//#define GDB_FR_FPR14 ((GDB_FR_FPR13) + LONGSIZE) /* 52 */ +//#define GDB_FR_FPR15 ((GDB_FR_FPR14) + LONGSIZE) /* 53 */ +//#define GDB_FR_FPR16 ((GDB_FR_FPR15) + LONGSIZE) /* 54 */ +//#define GDB_FR_FPR17 ((GDB_FR_FPR16) + LONGSIZE) /* 55 */ +//#define GDB_FR_FPR18 ((GDB_FR_FPR17) + LONGSIZE) /* 56 */ +//#define GDB_FR_FPR19 ((GDB_FR_FPR18) + LONGSIZE) /* 57 */ +//#define GDB_FR_FPR20 ((GDB_FR_FPR19) + LONGSIZE) /* 58 */ +//#define GDB_FR_FPR21 ((GDB_FR_FPR20) + LONGSIZE) /* 59 */ +//#define GDB_FR_FPR22 ((GDB_FR_FPR21) + LONGSIZE) /* 60 */ +//#define GDB_FR_FPR23 ((GDB_FR_FPR22) + LONGSIZE) /* 61 */ +//#define GDB_FR_FPR24 ((GDB_FR_FPR23) + LONGSIZE) /* 62 */ +//#define GDB_FR_FPR25 ((GDB_FR_FPR24) + LONGSIZE) /* 63 */ +//#define GDB_FR_FPR26 ((GDB_FR_FPR25) + LONGSIZE) /* 64 */ +//#define GDB_FR_FPR27 ((GDB_FR_FPR26) + LONGSIZE) /* 65 */ +//#define GDB_FR_FPR28 ((GDB_FR_FPR27) + LONGSIZE) /* 66 */ +//#define GDB_FR_FPR29 ((GDB_FR_FPR28) + LONGSIZE) /* 67 */ +//#define GDB_FR_FPR30 ((GDB_FR_FPR29) + LONGSIZE) /* 68 */ +//#define GDB_FR_FPR31 ((GDB_FR_FPR30) + LONGSIZE) /* 69 */ +// +//#define GDB_FR_FSR ((GDB_FR_FPR31) + LONGSIZE) /* 70 */ +//#define GDB_FR_FIR ((GDB_FR_FSR) + LONGSIZE) /* 71 */ +//#define GDB_FR_FRP ((GDB_FR_FIR) + LONGSIZE) /* 72 */ +// +//#define GDB_FR_DUMMY ((GDB_FR_FRP) + LONGSIZE) /* 73, unused ??? */ +// +///* +// * Again, CP0 registers +// */ +//#define GDB_FR_CP0_INDEX ((GDB_FR_DUMMY) + LONGSIZE) /* 74 */ +#define GDB_FR_FRP ((GDB_FR_EPC) + LONGSIZE) /* 72 */ +#define GDB_FR_CP0_INDEX ((GDB_FR_FRP) + LONGSIZE) /* 74 */ + +#define GDB_FR_CP0_RANDOM ((GDB_FR_CP0_INDEX) + LONGSIZE) /* 75 */ +#define GDB_FR_CP0_ENTRYLO0 ((GDB_FR_CP0_RANDOM) + LONGSIZE)/* 76 */ +#define GDB_FR_CP0_ENTRYLO1 ((GDB_FR_CP0_ENTRYLO0) + LONGSIZE)/* 77 */ +#define GDB_FR_CP0_CONTEXT ((GDB_FR_CP0_ENTRYLO1) + LONGSIZE)/* 78 */ +#define GDB_FR_CP0_PAGEMASK ((GDB_FR_CP0_CONTEXT) + LONGSIZE)/* 79 */ +#define GDB_FR_CP0_WIRED ((GDB_FR_CP0_PAGEMASK) + LONGSIZE)/* 80 */ +#define GDB_FR_CP0_REG7 ((GDB_FR_CP0_WIRED) + LONGSIZE) /* 81 */ +#define GDB_FR_CP0_REG8 ((GDB_FR_CP0_REG7) + LONGSIZE) /* 82 */ +#define GDB_FR_CP0_REG9 ((GDB_FR_CP0_REG8) + LONGSIZE) /* 83 */ +#define GDB_FR_CP0_ENTRYHI ((GDB_FR_CP0_REG9) + LONGSIZE) /* 84 */ +#define GDB_FR_CP0_REG11 ((GDB_FR_CP0_ENTRYHI) + LONGSIZE)/* 85 */ +#define GDB_FR_CP0_REG12 ((GDB_FR_CP0_REG11) + LONGSIZE) /* 86 */ +#define GDB_FR_CP0_REG13 ((GDB_FR_CP0_REG12) + LONGSIZE) /* 87 */ +#define GDB_FR_CP0_REG14 ((GDB_FR_CP0_REG13) + LONGSIZE) /* 88 */ +#define GDB_FR_CP0_PRID ((GDB_FR_CP0_REG14) + LONGSIZE) /* 89 */ + +#define GDB_FR_SIZE ((((GDB_FR_CP0_PRID) + LONGSIZE) + (PTRSIZE-1)) & ~(PTRSIZE-1)) + +/* + * This is the same as above, but for the high-level + * part of the INT stub. + */ +typedef struct pt_regs_s +{ + /* Saved main processor registers. */ + rt_base_t regs[32]; + /* Saved special registers. */ + rt_base_t cp0_status; + rt_base_t hi; + rt_base_t lo; + rt_base_t cp0_badvaddr; + rt_base_t cp0_cause; + rt_base_t cp0_epc; +} pt_regs_t; + +typedef void (* exception_func_t)(pt_regs_t *regs); + +extern exception_func_t sys_exception_handlers[]; +exception_func_t rt_set_except_vector(int n, exception_func_t func); +void install_default_execpt_handle(void); + +#endif /* end of __EXCEPTION_H__ */ diff --git a/libcpu/mips/common/mips.inc b/libcpu/mips/common/mips.inc index c1e3e2d418..a4cd55911e 100644 --- a/libcpu/mips/common/mips.inc +++ b/libcpu/mips/common/mips.inc @@ -1,52 +1,52 @@ -/*
- * File : mips.inc
- * This file is part of RT-Thread RTOS
- * COPYRIGHT (C) 2010, RT-Thread Development Team
- *
- * The license and distribution terms for this file may be
- * found in the file LICENSE in this distribution or at
- * http://www.rt-thread.org/license/LICENSE
- *
- * Change Logs:
- * Date Author Notes
- * 2010-05-17 sangwei first version
- */
-#ifndef __MIPS_INC__
-#define __MIPS_INC__
-
-#define zero $0 /* wired zero */
-// #define at $1
-#define v0 $2 /* return value */
-#define v1 $3
-#define a0 $4 /* argument registers */
-#define a1 $5
-#define a2 $6
-#define a3 $7
-#define t0 $8 /* caller saved */
-#define t1 $9
-#define t2 $10
-#define t3 $11
-#define t4 $12
-#define t5 $13
-#define t6 $14
-#define t7 $15
-#define s0 $16 /* callee saved */
-#define s1 $17
-#define s2 $18
-#define s3 $19
-#define s4 $20
-#define s5 $21
-#define s6 $22
-#define s7 $23
-#define t8 $24 /* caller saved */
-#define t9 $25
-#define jp $25 /* PIC jump register */
-#define k0 $26 /* kernel scratch */
-#define k1 $27
-#define gp $28 /* global pointer */
-#define sp $29 /* stack pointer */
-#define fp $30 /* frame pointer */
-#define s8 $30 /* same like fp! */
-#define ra $31 /* return address */
-
-#endif /* end of __MIPS_INC__ */
+/* + * File : mips.inc + * This file is part of RT-Thread RTOS + * COPYRIGHT (C) 2010, RT-Thread Development Team + * + * The license and distribution terms for this file may be + * found in the file LICENSE in this distribution or at + * http://www.rt-thread.org/license/LICENSE + * + * Change Logs: + * Date Author Notes + * 2010-05-17 sangwei first version + */ +#ifndef __MIPS_INC__ +#define __MIPS_INC__ + +#define zero $0 /* wired zero */ +// #define at $1 +#define v0 $2 /* return value */ +#define v1 $3 +#define a0 $4 /* argument registers */ +#define a1 $5 +#define a2 $6 +#define a3 $7 +#define t0 $8 /* caller saved */ +#define t1 $9 +#define t2 $10 +#define t3 $11 +#define t4 $12 +#define t5 $13 +#define t6 $14 +#define t7 $15 +#define s0 $16 /* callee saved */ +#define s1 $17 +#define s2 $18 +#define s3 $19 +#define s4 $20 +#define s5 $21 +#define s6 $22 +#define s7 $23 +#define t8 $24 /* caller saved */ +#define t9 $25 +#define jp $25 /* PIC jump register */ +#define k0 $26 /* kernel scratch */ +#define k1 $27 +#define gp $28 /* global pointer */ +#define sp $29 /* stack pointer */ +#define fp $30 /* frame pointer */ +#define s8 $30 /* same like fp! */ +#define ra $31 /* return address */ + +#endif /* end of __MIPS_INC__ */ diff --git a/libcpu/mips/common/mipscfg.h b/libcpu/mips/common/mipscfg.h index 1e64d99db9..b4f30615f8 100644 --- a/libcpu/mips/common/mipscfg.h +++ b/libcpu/mips/common/mipscfg.h @@ -1,32 +1,32 @@ -/*
- * File : mipscfg.h
- * This file is part of RT-Thread RTOS
- * COPYRIGHT (C) 2010, RT-Thread Development Team
- *
- * The license and distribution terms for this file may be
- * found in the file LICENSE in this distribution or at
- * http://www.rt-thread.org/license/LICENSE
- *
- * Change Logs:
- * Date Author Notes
- * 2010-05-27 swkyer first version
- */
-#ifndef __MIPSCFG_H__
-#define __MIPSCFG_H__
-
-
-typedef struct mips32_core_cfg
-{
- rt_uint16_t icache_line_size;
- rt_uint16_t icache_lines_per_way;
- rt_uint16_t icache_ways;
- rt_uint16_t dcache_line_size;
- rt_uint16_t dcache_lines_per_way;
- rt_uint16_t dcache_ways;
-
- rt_uint16_t max_tlb_entries; /* number of tlb entry */
-} mips32_core_cfg_t;
-
-extern mips32_core_cfg_t g_mips_core;
-
-#endif /* end of __MIPSCFG_H__ */
+/* + * File : mipscfg.h + * This file is part of RT-Thread RTOS + * COPYRIGHT (C) 2010, RT-Thread Development Team + * + * The license and distribution terms for this file may be + * found in the file LICENSE in this distribution or at + * http://www.rt-thread.org/license/LICENSE + * + * Change Logs: + * Date Author Notes + * 2010-05-27 swkyer first version + */ +#ifndef __MIPSCFG_H__ +#define __MIPSCFG_H__ + + +typedef struct mips32_core_cfg +{ + rt_uint16_t icache_line_size; + rt_uint16_t icache_lines_per_way; + rt_uint16_t icache_ways; + rt_uint16_t dcache_line_size; + rt_uint16_t dcache_lines_per_way; + rt_uint16_t dcache_ways; + + rt_uint16_t max_tlb_entries; /* number of tlb entry */ +} mips32_core_cfg_t; + +extern mips32_core_cfg_t g_mips_core; + +#endif /* end of __MIPSCFG_H__ */ diff --git a/libcpu/mips/common/mipsregs.h b/libcpu/mips/common/mipsregs.h index d29b59d237..888d4b13b5 100644 --- a/libcpu/mips/common/mipsregs.h +++ b/libcpu/mips/common/mipsregs.h @@ -1,616 +1,616 @@ -/*
- * This file is subject to the terms and conditions of the GNU General Public
- * License. See the file "COPYING" in the main directory of this archive
- * for more details.
- *
- * Copyright (C) 1994, 1995, 1996, 1997, 2000, 2001 by Ralf Baechle
- * Copyright (C) 2000 Silicon Graphics, Inc.
- * Modified for further R[236]000 support by Paul M. Antoine, 1996.
- * Kevin D. Kissell, [email protected] and Carsten Langgaard, [email protected]
- * Copyright (C) 2000, 07 MIPS Technologies, Inc.
- * Copyright (C) 2003, 2004 Maciej W. Rozycki
- *
- * Change Logs:
- * Date Author Notes
- *
- */
-#ifndef __MIPSREGS_H__
-#define __MIPSREGS_H__
-
-/*
- * The following macros are especially useful for __asm__
- * inline assembler.
- */
-#ifndef __STR
-#define __STR(x) #x
-#endif
-#ifndef STR
-#define STR(x) __STR(x)
-#endif
-
-/*
- * Configure language
- */
-#ifdef __ASSEMBLY__
-#define _ULCAST_
-#else
-#define _ULCAST_ (unsigned long)
-#endif
-
-/*
- * Coprocessor 0 register names
- */
-#define CP0_INDEX $0
-#define CP0_RANDOM $1
-#define CP0_ENTRYLO0 $2
-#define CP0_ENTRYLO1 $3
-#define CP0_CONF $3
-#define CP0_CONTEXT $4
-#define CP0_PAGEMASK $5
-#define CP0_WIRED $6
-#define CP0_INFO $7
-#define CP0_BADVADDR $8
-#define CP0_COUNT $9
-#define CP0_ENTRYHI $10
-#define CP0_COMPARE $11
-#define CP0_STATUS $12
-#define CP0_CAUSE $13
-#define CP0_EPC $14
-#define CP0_PRID $15
-#define CP0_CONFIG $16
-#define CP0_LLADDR $17
-#define CP0_WATCHLO $18
-#define CP0_WATCHHI $19
-#define CP0_XCONTEXT $20
-#define CP0_FRAMEMASK $21
-#define CP0_DIAGNOSTIC $22
-#define CP0_DEBUG $23
-#define CP0_DEPC $24
-#define CP0_PERFORMANCE $25
-#define CP0_ECC $26
-#define CP0_CACHEERR $27
-#define CP0_TAGLO $28
-#define CP0_TAGHI $29
-#define CP0_ERROREPC $30
-#define CP0_DESAVE $31
-
-/*
- * R4640/R4650 cp0 register names. These registers are listed
- * here only for completeness; without MMU these CPUs are not useable
- * by Linux. A future ELKS port might take make Linux run on them
- * though ...
- */
-#define CP0_IBASE $0
-#define CP0_IBOUND $1
-#define CP0_DBASE $2
-#define CP0_DBOUND $3
-#define CP0_CALG $17
-#define CP0_IWATCH $18
-#define CP0_DWATCH $19
-
-/*
- * Coprocessor 0 Set 1 register names
- */
-#define CP0_S1_DERRADDR0 $26
-#define CP0_S1_DERRADDR1 $27
-#define CP0_S1_INTCONTROL $20
-
-/*
- * Coprocessor 0 Set 2 register names
- */
-#define CP0_S2_SRSCTL $12 /* MIPSR2 */
-
-/*
- * Coprocessor 0 Set 3 register names
- */
-#define CP0_S3_SRSMAP $12 /* MIPSR2 */
-
-/*
- * TX39 Series
- */
-#define CP0_TX39_CACHE $7
-
-/*
- * Coprocessor 1 (FPU) register names
- */
-#define CP1_REVISION $0
-#define CP1_STATUS $31
-
-
-/*
- * R4x00 interrupt enable / cause bits
- */
-#define IE_SW0 (_ULCAST_(1) << 8)
-#define IE_SW1 (_ULCAST_(1) << 9)
-#define IE_IRQ0 (_ULCAST_(1) << 10)
-#define IE_IRQ1 (_ULCAST_(1) << 11)
-#define IE_IRQ2 (_ULCAST_(1) << 12)
-#define IE_IRQ3 (_ULCAST_(1) << 13)
-#define IE_IRQ4 (_ULCAST_(1) << 14)
-#define IE_IRQ5 (_ULCAST_(1) << 15)
-
-/*
- * R4x00 interrupt cause bits
- */
-#define C_SW0 (_ULCAST_(1) << 8)
-#define C_SW1 (_ULCAST_(1) << 9)
-#define C_IRQ0 (_ULCAST_(1) << 10)
-#define C_IRQ1 (_ULCAST_(1) << 11)
-#define C_IRQ2 (_ULCAST_(1) << 12)
-#define C_IRQ3 (_ULCAST_(1) << 13)
-#define C_IRQ4 (_ULCAST_(1) << 14)
-#define C_IRQ5 (_ULCAST_(1) << 15)
-
-/*
- * Bitfields in the R4xx0 cp0 status register
- */
-#define ST0_IE 0x00000001
-#define ST0_EXL 0x00000002
-#define ST0_ERL 0x00000004
-#define ST0_KSU 0x00000018
-# define KSU_USER 0x00000010
-# define KSU_SUPERVISOR 0x00000008
-# define KSU_KERNEL 0x00000000
-#define ST0_UX 0x00000020
-#define ST0_SX 0x00000040
-#define ST0_KX 0x00000080
-#define ST0_DE 0x00010000
-#define ST0_CE 0x00020000
-
-/*
- * Setting c0_status.co enables Hit_Writeback and Hit_Writeback_Invalidate
- * cacheops in userspace. This bit exists only on RM7000 and RM9000
- * processors.
- */
-#define ST0_CO 0x08000000
-
-/*
- * Bitfields in the R[23]000 cp0 status register.
- */
-#define ST0_IEC 0x00000001
-#define ST0_KUC 0x00000002
-#define ST0_IEP 0x00000004
-#define ST0_KUP 0x00000008
-#define ST0_IEO 0x00000010
-#define ST0_KUO 0x00000020
-/* bits 6 & 7 are reserved on R[23]000 */
-#define ST0_ISC 0x00010000
-#define ST0_SWC 0x00020000
-#define ST0_CM 0x00080000
-
-/*
- * Bits specific to the R4640/R4650
- */
-#define ST0_UM (_ULCAST_(1) << 4)
-#define ST0_IL (_ULCAST_(1) << 23)
-#define ST0_DL (_ULCAST_(1) << 24)
-
-/*
- * Enable the MIPS DSP ASE
- */
-#define ST0_MX 0x01000000
-
-/*
- * Bitfields in the TX39 family CP0 Configuration Register 3
- */
-#define TX39_CONF_ICS_SHIFT 19
-#define TX39_CONF_ICS_MASK 0x00380000
-#define TX39_CONF_ICS_1KB 0x00000000
-#define TX39_CONF_ICS_2KB 0x00080000
-#define TX39_CONF_ICS_4KB 0x00100000
-#define TX39_CONF_ICS_8KB 0x00180000
-#define TX39_CONF_ICS_16KB 0x00200000
-
-#define TX39_CONF_DCS_SHIFT 16
-#define TX39_CONF_DCS_MASK 0x00070000
-#define TX39_CONF_DCS_1KB 0x00000000
-#define TX39_CONF_DCS_2KB 0x00010000
-#define TX39_CONF_DCS_4KB 0x00020000
-#define TX39_CONF_DCS_8KB 0x00030000
-#define TX39_CONF_DCS_16KB 0x00040000
-
-#define TX39_CONF_CWFON 0x00004000
-#define TX39_CONF_WBON 0x00002000
-#define TX39_CONF_RF_SHIFT 10
-#define TX39_CONF_RF_MASK 0x00000c00
-#define TX39_CONF_DOZE 0x00000200
-#define TX39_CONF_HALT 0x00000100
-#define TX39_CONF_LOCK 0x00000080
-#define TX39_CONF_ICE 0x00000020
-#define TX39_CONF_DCE 0x00000010
-#define TX39_CONF_IRSIZE_SHIFT 2
-#define TX39_CONF_IRSIZE_MASK 0x0000000c
-#define TX39_CONF_DRSIZE_SHIFT 0
-#define TX39_CONF_DRSIZE_MASK 0x00000003
-
-/*
- * Status register bits available in all MIPS CPUs.
- */
-#define ST0_IM 0x0000ff00
-#define STATUSB_IP0 8
-#define STATUSF_IP0 (_ULCAST_(1) << 8)
-#define STATUSB_IP1 9
-#define STATUSF_IP1 (_ULCAST_(1) << 9)
-#define STATUSB_IP2 10
-#define STATUSF_IP2 (_ULCAST_(1) << 10)
-#define STATUSB_IP3 11
-#define STATUSF_IP3 (_ULCAST_(1) << 11)
-#define STATUSB_IP4 12
-#define STATUSF_IP4 (_ULCAST_(1) << 12)
-#define STATUSB_IP5 13
-#define STATUSF_IP5 (_ULCAST_(1) << 13)
-#define STATUSB_IP6 14
-#define STATUSF_IP6 (_ULCAST_(1) << 14)
-#define STATUSB_IP7 15
-#define STATUSF_IP7 (_ULCAST_(1) << 15)
-#define STATUSB_IP8 0
-#define STATUSF_IP8 (_ULCAST_(1) << 0)
-#define STATUSB_IP9 1
-#define STATUSF_IP9 (_ULCAST_(1) << 1)
-#define STATUSB_IP10 2
-#define STATUSF_IP10 (_ULCAST_(1) << 2)
-#define STATUSB_IP11 3
-#define STATUSF_IP11 (_ULCAST_(1) << 3)
-#define STATUSB_IP12 4
-#define STATUSF_IP12 (_ULCAST_(1) << 4)
-#define STATUSB_IP13 5
-#define STATUSF_IP13 (_ULCAST_(1) << 5)
-#define STATUSB_IP14 6
-#define STATUSF_IP14 (_ULCAST_(1) << 6)
-#define STATUSB_IP15 7
-#define STATUSF_IP15 (_ULCAST_(1) << 7)
-#define ST0_CH 0x00040000
-#define ST0_SR 0x00100000
-#define ST0_TS 0x00200000
-#define ST0_BEV 0x00400000
-#define ST0_RE 0x02000000
-#define ST0_FR 0x04000000
-#define ST0_CU 0xf0000000
-#define ST0_CU0 0x10000000
-#define ST0_CU1 0x20000000
-#define ST0_CU2 0x40000000
-#define ST0_CU3 0x80000000
-#define ST0_XX 0x80000000 /* MIPS IV naming */
-
-/*
- * Bitfields and bit numbers in the coprocessor 0 cause register.
- *
- * Refer to your MIPS R4xx0 manual, chapter 5 for explanation.
- */
-#define CAUSEB_EXCCODE 2
-#define CAUSEF_EXCCODE (_ULCAST_(31) << 2)
-#define CAUSEB_IP 8
-#define CAUSEF_IP (_ULCAST_(255) << 8)
-#define CAUSEB_IP0 8
-#define CAUSEF_IP0 (_ULCAST_(1) << 8)
-#define CAUSEB_IP1 9
-#define CAUSEF_IP1 (_ULCAST_(1) << 9)
-#define CAUSEB_IP2 10
-#define CAUSEF_IP2 (_ULCAST_(1) << 10)
-#define CAUSEB_IP3 11
-#define CAUSEF_IP3 (_ULCAST_(1) << 11)
-#define CAUSEB_IP4 12
-#define CAUSEF_IP4 (_ULCAST_(1) << 12)
-#define CAUSEB_IP5 13
-#define CAUSEF_IP5 (_ULCAST_(1) << 13)
-#define CAUSEB_IP6 14
-#define CAUSEF_IP6 (_ULCAST_(1) << 14)
-#define CAUSEB_IP7 15
-#define CAUSEF_IP7 (_ULCAST_(1) << 15)
-#define CAUSEB_IV 23
-#define CAUSEF_IV (_ULCAST_(1) << 23)
-#define CAUSEB_CE 28
-#define CAUSEF_CE (_ULCAST_(3) << 28)
-#define CAUSEB_BD 31
-#define CAUSEF_BD (_ULCAST_(1) << 31)
-
-/*
- * Bits in the coprocessor 0 config register.
- */
-/* Generic bits. */
-#define CONF_CM_CACHABLE_NO_WA 0
-#define CONF_CM_CACHABLE_WA 1
-#define CONF_CM_UNCACHED 2
-#define CONF_CM_CACHABLE_NONCOHERENT 3
-#define CONF_CM_CACHABLE_CE 4
-#define CONF_CM_CACHABLE_COW 5
-#define CONF_CM_CACHABLE_CUW 6
-#define CONF_CM_CACHABLE_ACCELERATED 7
-#define CONF_CM_CMASK 7
-#define CONF_BE (_ULCAST_(1) << 15)
-
-/* Bits common to various processors. */
-#define CONF_CU (_ULCAST_(1) << 3)
-#define CONF_DB (_ULCAST_(1) << 4)
-#define CONF_IB (_ULCAST_(1) << 5)
-#define CONF_DC (_ULCAST_(7) << 6)
-#define CONF_IC (_ULCAST_(7) << 9)
-#define CONF_EB (_ULCAST_(1) << 13)
-#define CONF_EM (_ULCAST_(1) << 14)
-#define CONF_SM (_ULCAST_(1) << 16)
-#define CONF_SC (_ULCAST_(1) << 17)
-#define CONF_EW (_ULCAST_(3) << 18)
-#define CONF_EP (_ULCAST_(15)<< 24)
-#define CONF_EC (_ULCAST_(7) << 28)
-#define CONF_CM (_ULCAST_(1) << 31)
-
-/* Bits specific to the R4xx0. */
-#define R4K_CONF_SW (_ULCAST_(1) << 20)
-#define R4K_CONF_SS (_ULCAST_(1) << 21)
-#define R4K_CONF_SB (_ULCAST_(3) << 22)
-
-/* Bits specific to the R5000. */
-#define R5K_CONF_SE (_ULCAST_(1) << 12)
-#define R5K_CONF_SS (_ULCAST_(3) << 20)
-
-/* Bits specific to the RM7000. */
-#define RM7K_CONF_SE (_ULCAST_(1) << 3)
-#define RM7K_CONF_TE (_ULCAST_(1) << 12)
-#define RM7K_CONF_CLK (_ULCAST_(1) << 16)
-#define RM7K_CONF_TC (_ULCAST_(1) << 17)
-#define RM7K_CONF_SI (_ULCAST_(3) << 20)
-#define RM7K_CONF_SC (_ULCAST_(1) << 31)
-
-/* Bits specific to the R10000. */
-#define R10K_CONF_DN (_ULCAST_(3) << 3)
-#define R10K_CONF_CT (_ULCAST_(1) << 5)
-#define R10K_CONF_PE (_ULCAST_(1) << 6)
-#define R10K_CONF_PM (_ULCAST_(3) << 7)
-#define R10K_CONF_EC (_ULCAST_(15)<< 9)
-#define R10K_CONF_SB (_ULCAST_(1) << 13)
-#define R10K_CONF_SK (_ULCAST_(1) << 14)
-#define R10K_CONF_SS (_ULCAST_(7) << 16)
-#define R10K_CONF_SC (_ULCAST_(7) << 19)
-#define R10K_CONF_DC (_ULCAST_(7) << 26)
-#define R10K_CONF_IC (_ULCAST_(7) << 29)
-
-/* Bits specific to the VR41xx. */
-#define VR41_CONF_CS (_ULCAST_(1) << 12)
-#define VR41_CONF_M16 (_ULCAST_(1) << 20)
-#define VR41_CONF_AD (_ULCAST_(1) << 23)
-
-/* Bits specific to the R30xx. */
-#define R30XX_CONF_FDM (_ULCAST_(1) << 19)
-#define R30XX_CONF_REV (_ULCAST_(1) << 22)
-#define R30XX_CONF_AC (_ULCAST_(1) << 23)
-#define R30XX_CONF_RF (_ULCAST_(1) << 24)
-#define R30XX_CONF_HALT (_ULCAST_(1) << 25)
-#define R30XX_CONF_FPINT (_ULCAST_(7) << 26)
-#define R30XX_CONF_DBR (_ULCAST_(1) << 29)
-#define R30XX_CONF_SB (_ULCAST_(1) << 30)
-#define R30XX_CONF_LOCK (_ULCAST_(1) << 31)
-
-/* Bits specific to the TX49. */
-#define TX49_CONF_DC (_ULCAST_(1) << 16)
-#define TX49_CONF_IC (_ULCAST_(1) << 17) /* conflict with CONF_SC */
-#define TX49_CONF_HALT (_ULCAST_(1) << 18)
-#define TX49_CONF_CWFON (_ULCAST_(1) << 27)
-
-/* Bits specific to the MIPS32/64 PRA. */
-#define MIPS_CONF_MT (_ULCAST_(7) << 7)
-#define MIPS_CONF_AR (_ULCAST_(7) << 10)
-#define MIPS_CONF_AT (_ULCAST_(3) << 13)
-#define MIPS_CONF_M (_ULCAST_(1) << 31)
-
-/*
- * Bits in the MIPS32/64 PRA coprocessor 0 config registers 1 and above.
- */
-#define MIPS_CONF1_FP (_ULCAST_(1) << 0)
-#define MIPS_CONF1_EP (_ULCAST_(1) << 1)
-#define MIPS_CONF1_CA (_ULCAST_(1) << 2)
-#define MIPS_CONF1_WR (_ULCAST_(1) << 3)
-#define MIPS_CONF1_PC (_ULCAST_(1) << 4)
-#define MIPS_CONF1_MD (_ULCAST_(1) << 5)
-#define MIPS_CONF1_C2 (_ULCAST_(1) << 6)
-#define MIPS_CONF1_DA (_ULCAST_(7) << 7)
-#define MIPS_CONF1_DL (_ULCAST_(7) << 10)
-#define MIPS_CONF1_DS (_ULCAST_(7) << 13)
-#define MIPS_CONF1_IA (_ULCAST_(7) << 16)
-#define MIPS_CONF1_IL (_ULCAST_(7) << 19)
-#define MIPS_CONF1_IS (_ULCAST_(7) << 22)
-#define MIPS_CONF1_TLBS (_ULCAST_(63)<< 25)
-
-#define MIPS_CONF2_SA (_ULCAST_(15)<< 0)
-#define MIPS_CONF2_SL (_ULCAST_(15)<< 4)
-#define MIPS_CONF2_SS (_ULCAST_(15)<< 8)
-#define MIPS_CONF2_SU (_ULCAST_(15)<< 12)
-#define MIPS_CONF2_TA (_ULCAST_(15)<< 16)
-#define MIPS_CONF2_TL (_ULCAST_(15)<< 20)
-#define MIPS_CONF2_TS (_ULCAST_(15)<< 24)
-#define MIPS_CONF2_TU (_ULCAST_(7) << 28)
-
-#define MIPS_CONF3_TL (_ULCAST_(1) << 0)
-#define MIPS_CONF3_SM (_ULCAST_(1) << 1)
-#define MIPS_CONF3_MT (_ULCAST_(1) << 2)
-#define MIPS_CONF3_SP (_ULCAST_(1) << 4)
-#define MIPS_CONF3_VINT (_ULCAST_(1) << 5)
-#define MIPS_CONF3_VEIC (_ULCAST_(1) << 6)
-#define MIPS_CONF3_LPA (_ULCAST_(1) << 7)
-#define MIPS_CONF3_DSP (_ULCAST_(1) << 10)
-
-/*
- * Bits in the MIPS32/64 coprocessor 1 (FPU) revision register.
- */
-#define MIPS_FPIR_S (_ULCAST_(1) << 16)
-#define MIPS_FPIR_D (_ULCAST_(1) << 17)
-#define MIPS_FPIR_PS (_ULCAST_(1) << 18)
-#define MIPS_FPIR_3D (_ULCAST_(1) << 19)
-#define MIPS_FPIR_W (_ULCAST_(1) << 20)
-#define MIPS_FPIR_L (_ULCAST_(1) << 21)
-#define MIPS_FPIR_F64 (_ULCAST_(1) << 22)
-
-/*
- * R10000 performance counter definitions.
- *
- * FIXME: The R10000 performance counter opens a nice way to implement CPU
- * time accounting with a precission of one cycle. I don't have
- * R10000 silicon but just a manual, so ...
- */
-
-/*
- * Events counted by counter #0
- */
-#define CE0_CYCLES 0
-#define CE0_INSN_ISSUED 1
-#define CE0_LPSC_ISSUED 2
-#define CE0_S_ISSUED 3
-#define CE0_SC_ISSUED 4
-#define CE0_SC_FAILED 5
-#define CE0_BRANCH_DECODED 6
-#define CE0_QW_WB_SECONDARY 7
-#define CE0_CORRECTED_ECC_ERRORS 8
-#define CE0_ICACHE_MISSES 9
-#define CE0_SCACHE_I_MISSES 10
-#define CE0_SCACHE_I_WAY_MISSPREDICTED 11
-#define CE0_EXT_INTERVENTIONS_REQ 12
-#define CE0_EXT_INVALIDATE_REQ 13
-#define CE0_VIRTUAL_COHERENCY_COND 14
-#define CE0_INSN_GRADUATED 15
-
-/*
- * Events counted by counter #1
- */
-#define CE1_CYCLES 0
-#define CE1_INSN_GRADUATED 1
-#define CE1_LPSC_GRADUATED 2
-#define CE1_S_GRADUATED 3
-#define CE1_SC_GRADUATED 4
-#define CE1_FP_INSN_GRADUATED 5
-#define CE1_QW_WB_PRIMARY 6
-#define CE1_TLB_REFILL 7
-#define CE1_BRANCH_MISSPREDICTED 8
-#define CE1_DCACHE_MISS 9
-#define CE1_SCACHE_D_MISSES 10
-#define CE1_SCACHE_D_WAY_MISSPREDICTED 11
-#define CE1_EXT_INTERVENTION_HITS 12
-#define CE1_EXT_INVALIDATE_REQ 13
-#define CE1_SP_HINT_TO_CEXCL_SC_BLOCKS 14
-#define CE1_SP_HINT_TO_SHARED_SC_BLOCKS 15
-
-/*
- * These flags define in which privilege mode the counters count events
- */
-#define CEB_USER 8 /* Count events in user mode, EXL = ERL = 0 */
-#define CEB_SUPERVISOR 4 /* Count events in supvervisor mode EXL = ERL = 0 */
-#define CEB_KERNEL 2 /* Count events in kernel mode EXL = ERL = 0 */
-#define CEB_EXL 1 /* Count events with EXL = 1, ERL = 0 */
-
-
-#ifndef __ASSEMBLY__
-
-/*
- * Macros to access the system control coprocessor
- */
-#define __read_32bit_c0_register(source, sel) \
-({ int __res; \
- if (sel == 0) \
- __asm__ __volatile__( \
- "mfc0\t%0, " #source "\n\t" \
- : "=r" (__res)); \
- else \
- __asm__ __volatile__( \
- ".set\tmips32\n\t" \
- "mfc0\t%0, " #source ", " #sel "\n\t" \
- ".set\tmips0\n\t" \
- : "=r" (__res)); \
- __res; \
-})
-
-#define __write_32bit_c0_register(register, sel, value) \
-do { \
- if (sel == 0) \
- __asm__ __volatile__( \
- "mtc0\t%z0, " #register "\n\t" \
- : : "Jr" ((unsigned int)(value))); \
- else \
- __asm__ __volatile__( \
- ".set\tmips32\n\t" \
- "mtc0\t%z0, " #register ", " #sel "\n\t" \
- ".set\tmips0" \
- : : "Jr" ((unsigned int)(value))); \
-} while (0)
-
-#define read_c0_index() __read_32bit_c0_register($0, 0)
-#define write_c0_index(val) __write_32bit_c0_register($0, 0, val)
-
-#define read_c0_random() __read_32bit_c0_register($1, 0)
-#define write_c0_random(val) __write_32bit_c0_register($1, 0, val)
-
-#define read_c0_entrylo0() __read_32bit_c0_register($2, 0)
-#define write_c0_entrylo0(val) __write_32bit_c0_register($2, 0, val)
-
-#define read_c0_entrylo1() __read_32bit_c0_register($3, 0)
-#define write_c0_entrylo1(val) __write_32bit_c0_register($3, 0, val)
-
-#define read_c0_conf() __read_32bit_c0_register($3, 0)
-#define write_c0_conf(val) __write_32bit_c0_register($3, 0, val)
-
-#define read_c0_context() __read_32bit_c0_register($4, 0)
-#define write_c0_context(val) __write_32bit_c0_register($4, 0, val)
-
-#define read_c0_userlocal() __read_32bit_c0_register($4, 2)
-#define write_c0_userlocal(val) __write_32bit_c0_register($4, 2, val)
-
-#define read_c0_pagemask() __read_32bit_c0_register($5, 0)
-#define write_c0_pagemask(val) __write_32bit_c0_register($5, 0, val)
-
-#define read_c0_wired() __read_32bit_c0_register($6, 0)
-#define write_c0_wired(val) __write_32bit_c0_register($6, 0, val)
-
-#define read_c0_info() __read_32bit_c0_register($7, 0)
-
-#define read_c0_cache() __read_32bit_c0_register($7, 0) /* TX39xx */
-#define write_c0_cache(val) __write_32bit_c0_register($7, 0, val)
-
-#define read_c0_badvaddr() __read_32bit_c0_register($8, 0)
-#define write_c0_badvaddr(val) __write_32bit_c0_register($8, 0, val)
-
-#define read_c0_count() __read_32bit_c0_register($9, 0)
-#define write_c0_count(val) __write_32bit_c0_register($9, 0, val)
-
-#define read_c0_count2() __read_32bit_c0_register($9, 6) /* pnx8550 */
-#define write_c0_count2(val) __write_32bit_c0_register($9, 6, val)
-
-#define read_c0_count3() __read_32bit_c0_register($9, 7) /* pnx8550 */
-#define write_c0_count3(val) __write_32bit_c0_register($9, 7, val)
-
-#define read_c0_entryhi() __read_32bit_c0_register($10, 0)
-#define write_c0_entryhi(val) __write_32bit_c0_register($10, 0, val)
-
-#define read_c0_compare() __read_32bit_c0_register($11, 0)
-#define write_c0_compare(val) __write_32bit_c0_register($11, 0, val)
-
-#define read_c0_compare2() __read_32bit_c0_register($11, 6) /* pnx8550 */
-#define write_c0_compare2(val) __write_32bit_c0_register($11, 6, val)
-
-#define read_c0_compare3() __read_32bit_c0_register($11, 7) /* pnx8550 */
-#define write_c0_compare3(val) __write_32bit_c0_register($11, 7, val)
-
-#define read_c0_status() __read_32bit_c0_register($12, 0)
-#define write_c0_status(val) __write_32bit_c0_register($12, 0, val)
-
-#define read_c0_cause() __read_32bit_c0_register($13, 0)
-#define write_c0_cause(val) __write_32bit_c0_register($13, 0, val)
-
-#define read_c0_epc() __read_32bit_c0_register($14, 0)
-#define write_c0_epc(val) __write_32bit_c0_register($14, 0, val)
-
-#define read_c0_prid() __read_32bit_c0_register($15, 0)
-
-#define read_c0_ebase() __read_32bit_c0_register($15, 1)
-#define write_c0_ebase(val) __write_32bit_c0_register($15, 1, val)
-
-#define read_c0_config() __read_32bit_c0_register($16, 0)
-#define read_c0_config1() __read_32bit_c0_register($16, 1)
-#define read_c0_config2() __read_32bit_c0_register($16, 2)
-#define read_c0_config3() __read_32bit_c0_register($16, 3)
-#define write_c0_config(val) __write_32bit_c0_register($16, 0, val)
-#define write_c0_config1(val) __write_32bit_c0_register($16, 1, val)
-#define write_c0_config2(val) __write_32bit_c0_register($16, 2, val)
-#define write_c0_config3(val) __write_32bit_c0_register($16, 3, val)
-
-
-#endif /* end of __ASSEMBLY__ */
-
-#endif /* end of __MIPSREGS_H__ */
-
+/* + * This file is subject to the terms and conditions of the GNU General Public + * License. See the file "COPYING" in the main directory of this archive + * for more details. + * + * Copyright (C) 1994, 1995, 1996, 1997, 2000, 2001 by Ralf Baechle + * Copyright (C) 2000 Silicon Graphics, Inc. + * Modified for further R[236]000 support by Paul M. Antoine, 1996. + * Kevin D. Kissell, [email protected] and Carsten Langgaard, [email protected] + * Copyright (C) 2000, 07 MIPS Technologies, Inc. + * Copyright (C) 2003, 2004 Maciej W. Rozycki + * + * Change Logs: + * Date Author Notes + * + */ +#ifndef __MIPSREGS_H__ +#define __MIPSREGS_H__ + +/* + * The following macros are especially useful for __asm__ + * inline assembler. + */ +#ifndef __STR +#define __STR(x) #x +#endif +#ifndef STR +#define STR(x) __STR(x) +#endif + +/* + * Configure language + */ +#ifdef __ASSEMBLY__ +#define _ULCAST_ +#else +#define _ULCAST_ (unsigned long) +#endif + +/* + * Coprocessor 0 register names + */ +#define CP0_INDEX $0 +#define CP0_RANDOM $1 +#define CP0_ENTRYLO0 $2 +#define CP0_ENTRYLO1 $3 +#define CP0_CONF $3 +#define CP0_CONTEXT $4 +#define CP0_PAGEMASK $5 +#define CP0_WIRED $6 +#define CP0_INFO $7 +#define CP0_BADVADDR $8 +#define CP0_COUNT $9 +#define CP0_ENTRYHI $10 +#define CP0_COMPARE $11 +#define CP0_STATUS $12 +#define CP0_CAUSE $13 +#define CP0_EPC $14 +#define CP0_PRID $15 +#define CP0_CONFIG $16 +#define CP0_LLADDR $17 +#define CP0_WATCHLO $18 +#define CP0_WATCHHI $19 +#define CP0_XCONTEXT $20 +#define CP0_FRAMEMASK $21 +#define CP0_DIAGNOSTIC $22 +#define CP0_DEBUG $23 +#define CP0_DEPC $24 +#define CP0_PERFORMANCE $25 +#define CP0_ECC $26 +#define CP0_CACHEERR $27 +#define CP0_TAGLO $28 +#define CP0_TAGHI $29 +#define CP0_ERROREPC $30 +#define CP0_DESAVE $31 + +/* + * R4640/R4650 cp0 register names. These registers are listed + * here only for completeness; without MMU these CPUs are not useable + * by Linux. A future ELKS port might take make Linux run on them + * though ... + */ +#define CP0_IBASE $0 +#define CP0_IBOUND $1 +#define CP0_DBASE $2 +#define CP0_DBOUND $3 +#define CP0_CALG $17 +#define CP0_IWATCH $18 +#define CP0_DWATCH $19 + +/* + * Coprocessor 0 Set 1 register names + */ +#define CP0_S1_DERRADDR0 $26 +#define CP0_S1_DERRADDR1 $27 +#define CP0_S1_INTCONTROL $20 + +/* + * Coprocessor 0 Set 2 register names + */ +#define CP0_S2_SRSCTL $12 /* MIPSR2 */ + +/* + * Coprocessor 0 Set 3 register names + */ +#define CP0_S3_SRSMAP $12 /* MIPSR2 */ + +/* + * TX39 Series + */ +#define CP0_TX39_CACHE $7 + +/* + * Coprocessor 1 (FPU) register names + */ +#define CP1_REVISION $0 +#define CP1_STATUS $31 + + +/* + * R4x00 interrupt enable / cause bits + */ +#define IE_SW0 (_ULCAST_(1) << 8) +#define IE_SW1 (_ULCAST_(1) << 9) +#define IE_IRQ0 (_ULCAST_(1) << 10) +#define IE_IRQ1 (_ULCAST_(1) << 11) +#define IE_IRQ2 (_ULCAST_(1) << 12) +#define IE_IRQ3 (_ULCAST_(1) << 13) +#define IE_IRQ4 (_ULCAST_(1) << 14) +#define IE_IRQ5 (_ULCAST_(1) << 15) + +/* + * R4x00 interrupt cause bits + */ +#define C_SW0 (_ULCAST_(1) << 8) +#define C_SW1 (_ULCAST_(1) << 9) +#define C_IRQ0 (_ULCAST_(1) << 10) +#define C_IRQ1 (_ULCAST_(1) << 11) +#define C_IRQ2 (_ULCAST_(1) << 12) +#define C_IRQ3 (_ULCAST_(1) << 13) +#define C_IRQ4 (_ULCAST_(1) << 14) +#define C_IRQ5 (_ULCAST_(1) << 15) + +/* + * Bitfields in the R4xx0 cp0 status register + */ +#define ST0_IE 0x00000001 +#define ST0_EXL 0x00000002 +#define ST0_ERL 0x00000004 +#define ST0_KSU 0x00000018 +# define KSU_USER 0x00000010 +# define KSU_SUPERVISOR 0x00000008 +# define KSU_KERNEL 0x00000000 +#define ST0_UX 0x00000020 +#define ST0_SX 0x00000040 +#define ST0_KX 0x00000080 +#define ST0_DE 0x00010000 +#define ST0_CE 0x00020000 + +/* + * Setting c0_status.co enables Hit_Writeback and Hit_Writeback_Invalidate + * cacheops in userspace. This bit exists only on RM7000 and RM9000 + * processors. + */ +#define ST0_CO 0x08000000 + +/* + * Bitfields in the R[23]000 cp0 status register. + */ +#define ST0_IEC 0x00000001 +#define ST0_KUC 0x00000002 +#define ST0_IEP 0x00000004 +#define ST0_KUP 0x00000008 +#define ST0_IEO 0x00000010 +#define ST0_KUO 0x00000020 +/* bits 6 & 7 are reserved on R[23]000 */ +#define ST0_ISC 0x00010000 +#define ST0_SWC 0x00020000 +#define ST0_CM 0x00080000 + +/* + * Bits specific to the R4640/R4650 + */ +#define ST0_UM (_ULCAST_(1) << 4) +#define ST0_IL (_ULCAST_(1) << 23) +#define ST0_DL (_ULCAST_(1) << 24) + +/* + * Enable the MIPS DSP ASE + */ +#define ST0_MX 0x01000000 + +/* + * Bitfields in the TX39 family CP0 Configuration Register 3 + */ +#define TX39_CONF_ICS_SHIFT 19 +#define TX39_CONF_ICS_MASK 0x00380000 +#define TX39_CONF_ICS_1KB 0x00000000 +#define TX39_CONF_ICS_2KB 0x00080000 +#define TX39_CONF_ICS_4KB 0x00100000 +#define TX39_CONF_ICS_8KB 0x00180000 +#define TX39_CONF_ICS_16KB 0x00200000 + +#define TX39_CONF_DCS_SHIFT 16 +#define TX39_CONF_DCS_MASK 0x00070000 +#define TX39_CONF_DCS_1KB 0x00000000 +#define TX39_CONF_DCS_2KB 0x00010000 +#define TX39_CONF_DCS_4KB 0x00020000 +#define TX39_CONF_DCS_8KB 0x00030000 +#define TX39_CONF_DCS_16KB 0x00040000 + +#define TX39_CONF_CWFON 0x00004000 +#define TX39_CONF_WBON 0x00002000 +#define TX39_CONF_RF_SHIFT 10 +#define TX39_CONF_RF_MASK 0x00000c00 +#define TX39_CONF_DOZE 0x00000200 +#define TX39_CONF_HALT 0x00000100 +#define TX39_CONF_LOCK 0x00000080 +#define TX39_CONF_ICE 0x00000020 +#define TX39_CONF_DCE 0x00000010 +#define TX39_CONF_IRSIZE_SHIFT 2 +#define TX39_CONF_IRSIZE_MASK 0x0000000c +#define TX39_CONF_DRSIZE_SHIFT 0 +#define TX39_CONF_DRSIZE_MASK 0x00000003 + +/* + * Status register bits available in all MIPS CPUs. + */ +#define ST0_IM 0x0000ff00 +#define STATUSB_IP0 8 +#define STATUSF_IP0 (_ULCAST_(1) << 8) +#define STATUSB_IP1 9 +#define STATUSF_IP1 (_ULCAST_(1) << 9) +#define STATUSB_IP2 10 +#define STATUSF_IP2 (_ULCAST_(1) << 10) +#define STATUSB_IP3 11 +#define STATUSF_IP3 (_ULCAST_(1) << 11) +#define STATUSB_IP4 12 +#define STATUSF_IP4 (_ULCAST_(1) << 12) +#define STATUSB_IP5 13 +#define STATUSF_IP5 (_ULCAST_(1) << 13) +#define STATUSB_IP6 14 +#define STATUSF_IP6 (_ULCAST_(1) << 14) +#define STATUSB_IP7 15 +#define STATUSF_IP7 (_ULCAST_(1) << 15) +#define STATUSB_IP8 0 +#define STATUSF_IP8 (_ULCAST_(1) << 0) +#define STATUSB_IP9 1 +#define STATUSF_IP9 (_ULCAST_(1) << 1) +#define STATUSB_IP10 2 +#define STATUSF_IP10 (_ULCAST_(1) << 2) +#define STATUSB_IP11 3 +#define STATUSF_IP11 (_ULCAST_(1) << 3) +#define STATUSB_IP12 4 +#define STATUSF_IP12 (_ULCAST_(1) << 4) +#define STATUSB_IP13 5 +#define STATUSF_IP13 (_ULCAST_(1) << 5) +#define STATUSB_IP14 6 +#define STATUSF_IP14 (_ULCAST_(1) << 6) +#define STATUSB_IP15 7 +#define STATUSF_IP15 (_ULCAST_(1) << 7) +#define ST0_CH 0x00040000 +#define ST0_SR 0x00100000 +#define ST0_TS 0x00200000 +#define ST0_BEV 0x00400000 +#define ST0_RE 0x02000000 +#define ST0_FR 0x04000000 +#define ST0_CU 0xf0000000 +#define ST0_CU0 0x10000000 +#define ST0_CU1 0x20000000 +#define ST0_CU2 0x40000000 +#define ST0_CU3 0x80000000 +#define ST0_XX 0x80000000 /* MIPS IV naming */ + +/* + * Bitfields and bit numbers in the coprocessor 0 cause register. + * + * Refer to your MIPS R4xx0 manual, chapter 5 for explanation. + */ +#define CAUSEB_EXCCODE 2 +#define CAUSEF_EXCCODE (_ULCAST_(31) << 2) +#define CAUSEB_IP 8 +#define CAUSEF_IP (_ULCAST_(255) << 8) +#define CAUSEB_IP0 8 +#define CAUSEF_IP0 (_ULCAST_(1) << 8) +#define CAUSEB_IP1 9 +#define CAUSEF_IP1 (_ULCAST_(1) << 9) +#define CAUSEB_IP2 10 +#define CAUSEF_IP2 (_ULCAST_(1) << 10) +#define CAUSEB_IP3 11 +#define CAUSEF_IP3 (_ULCAST_(1) << 11) +#define CAUSEB_IP4 12 +#define CAUSEF_IP4 (_ULCAST_(1) << 12) +#define CAUSEB_IP5 13 +#define CAUSEF_IP5 (_ULCAST_(1) << 13) +#define CAUSEB_IP6 14 +#define CAUSEF_IP6 (_ULCAST_(1) << 14) +#define CAUSEB_IP7 15 +#define CAUSEF_IP7 (_ULCAST_(1) << 15) +#define CAUSEB_IV 23 +#define CAUSEF_IV (_ULCAST_(1) << 23) +#define CAUSEB_CE 28 +#define CAUSEF_CE (_ULCAST_(3) << 28) +#define CAUSEB_BD 31 +#define CAUSEF_BD (_ULCAST_(1) << 31) + +/* + * Bits in the coprocessor 0 config register. + */ +/* Generic bits. */ +#define CONF_CM_CACHABLE_NO_WA 0 +#define CONF_CM_CACHABLE_WA 1 +#define CONF_CM_UNCACHED 2 +#define CONF_CM_CACHABLE_NONCOHERENT 3 +#define CONF_CM_CACHABLE_CE 4 +#define CONF_CM_CACHABLE_COW 5 +#define CONF_CM_CACHABLE_CUW 6 +#define CONF_CM_CACHABLE_ACCELERATED 7 +#define CONF_CM_CMASK 7 +#define CONF_BE (_ULCAST_(1) << 15) + +/* Bits common to various processors. */ +#define CONF_CU (_ULCAST_(1) << 3) +#define CONF_DB (_ULCAST_(1) << 4) +#define CONF_IB (_ULCAST_(1) << 5) +#define CONF_DC (_ULCAST_(7) << 6) +#define CONF_IC (_ULCAST_(7) << 9) +#define CONF_EB (_ULCAST_(1) << 13) +#define CONF_EM (_ULCAST_(1) << 14) +#define CONF_SM (_ULCAST_(1) << 16) +#define CONF_SC (_ULCAST_(1) << 17) +#define CONF_EW (_ULCAST_(3) << 18) +#define CONF_EP (_ULCAST_(15)<< 24) +#define CONF_EC (_ULCAST_(7) << 28) +#define CONF_CM (_ULCAST_(1) << 31) + +/* Bits specific to the R4xx0. */ +#define R4K_CONF_SW (_ULCAST_(1) << 20) +#define R4K_CONF_SS (_ULCAST_(1) << 21) +#define R4K_CONF_SB (_ULCAST_(3) << 22) + +/* Bits specific to the R5000. */ +#define R5K_CONF_SE (_ULCAST_(1) << 12) +#define R5K_CONF_SS (_ULCAST_(3) << 20) + +/* Bits specific to the RM7000. */ +#define RM7K_CONF_SE (_ULCAST_(1) << 3) +#define RM7K_CONF_TE (_ULCAST_(1) << 12) +#define RM7K_CONF_CLK (_ULCAST_(1) << 16) +#define RM7K_CONF_TC (_ULCAST_(1) << 17) +#define RM7K_CONF_SI (_ULCAST_(3) << 20) +#define RM7K_CONF_SC (_ULCAST_(1) << 31) + +/* Bits specific to the R10000. */ +#define R10K_CONF_DN (_ULCAST_(3) << 3) +#define R10K_CONF_CT (_ULCAST_(1) << 5) +#define R10K_CONF_PE (_ULCAST_(1) << 6) +#define R10K_CONF_PM (_ULCAST_(3) << 7) +#define R10K_CONF_EC (_ULCAST_(15)<< 9) +#define R10K_CONF_SB (_ULCAST_(1) << 13) +#define R10K_CONF_SK (_ULCAST_(1) << 14) +#define R10K_CONF_SS (_ULCAST_(7) << 16) +#define R10K_CONF_SC (_ULCAST_(7) << 19) +#define R10K_CONF_DC (_ULCAST_(7) << 26) +#define R10K_CONF_IC (_ULCAST_(7) << 29) + +/* Bits specific to the VR41xx. */ +#define VR41_CONF_CS (_ULCAST_(1) << 12) +#define VR41_CONF_M16 (_ULCAST_(1) << 20) +#define VR41_CONF_AD (_ULCAST_(1) << 23) + +/* Bits specific to the R30xx. */ +#define R30XX_CONF_FDM (_ULCAST_(1) << 19) +#define R30XX_CONF_REV (_ULCAST_(1) << 22) +#define R30XX_CONF_AC (_ULCAST_(1) << 23) +#define R30XX_CONF_RF (_ULCAST_(1) << 24) +#define R30XX_CONF_HALT (_ULCAST_(1) << 25) +#define R30XX_CONF_FPINT (_ULCAST_(7) << 26) +#define R30XX_CONF_DBR (_ULCAST_(1) << 29) +#define R30XX_CONF_SB (_ULCAST_(1) << 30) +#define R30XX_CONF_LOCK (_ULCAST_(1) << 31) + +/* Bits specific to the TX49. */ +#define TX49_CONF_DC (_ULCAST_(1) << 16) +#define TX49_CONF_IC (_ULCAST_(1) << 17) /* conflict with CONF_SC */ +#define TX49_CONF_HALT (_ULCAST_(1) << 18) +#define TX49_CONF_CWFON (_ULCAST_(1) << 27) + +/* Bits specific to the MIPS32/64 PRA. */ +#define MIPS_CONF_MT (_ULCAST_(7) << 7) +#define MIPS_CONF_AR (_ULCAST_(7) << 10) +#define MIPS_CONF_AT (_ULCAST_(3) << 13) +#define MIPS_CONF_M (_ULCAST_(1) << 31) + +/* + * Bits in the MIPS32/64 PRA coprocessor 0 config registers 1 and above. + */ +#define MIPS_CONF1_FP (_ULCAST_(1) << 0) +#define MIPS_CONF1_EP (_ULCAST_(1) << 1) +#define MIPS_CONF1_CA (_ULCAST_(1) << 2) +#define MIPS_CONF1_WR (_ULCAST_(1) << 3) +#define MIPS_CONF1_PC (_ULCAST_(1) << 4) +#define MIPS_CONF1_MD (_ULCAST_(1) << 5) +#define MIPS_CONF1_C2 (_ULCAST_(1) << 6) +#define MIPS_CONF1_DA (_ULCAST_(7) << 7) +#define MIPS_CONF1_DL (_ULCAST_(7) << 10) +#define MIPS_CONF1_DS (_ULCAST_(7) << 13) +#define MIPS_CONF1_IA (_ULCAST_(7) << 16) +#define MIPS_CONF1_IL (_ULCAST_(7) << 19) +#define MIPS_CONF1_IS (_ULCAST_(7) << 22) +#define MIPS_CONF1_TLBS (_ULCAST_(63)<< 25) + +#define MIPS_CONF2_SA (_ULCAST_(15)<< 0) +#define MIPS_CONF2_SL (_ULCAST_(15)<< 4) +#define MIPS_CONF2_SS (_ULCAST_(15)<< 8) +#define MIPS_CONF2_SU (_ULCAST_(15)<< 12) +#define MIPS_CONF2_TA (_ULCAST_(15)<< 16) +#define MIPS_CONF2_TL (_ULCAST_(15)<< 20) +#define MIPS_CONF2_TS (_ULCAST_(15)<< 24) +#define MIPS_CONF2_TU (_ULCAST_(7) << 28) + +#define MIPS_CONF3_TL (_ULCAST_(1) << 0) +#define MIPS_CONF3_SM (_ULCAST_(1) << 1) +#define MIPS_CONF3_MT (_ULCAST_(1) << 2) +#define MIPS_CONF3_SP (_ULCAST_(1) << 4) +#define MIPS_CONF3_VINT (_ULCAST_(1) << 5) +#define MIPS_CONF3_VEIC (_ULCAST_(1) << 6) +#define MIPS_CONF3_LPA (_ULCAST_(1) << 7) +#define MIPS_CONF3_DSP (_ULCAST_(1) << 10) + +/* + * Bits in the MIPS32/64 coprocessor 1 (FPU) revision register. + */ +#define MIPS_FPIR_S (_ULCAST_(1) << 16) +#define MIPS_FPIR_D (_ULCAST_(1) << 17) +#define MIPS_FPIR_PS (_ULCAST_(1) << 18) +#define MIPS_FPIR_3D (_ULCAST_(1) << 19) +#define MIPS_FPIR_W (_ULCAST_(1) << 20) +#define MIPS_FPIR_L (_ULCAST_(1) << 21) +#define MIPS_FPIR_F64 (_ULCAST_(1) << 22) + +/* + * R10000 performance counter definitions. + * + * FIXME: The R10000 performance counter opens a nice way to implement CPU + * time accounting with a precission of one cycle. I don't have + * R10000 silicon but just a manual, so ... + */ + +/* + * Events counted by counter #0 + */ +#define CE0_CYCLES 0 +#define CE0_INSN_ISSUED 1 +#define CE0_LPSC_ISSUED 2 +#define CE0_S_ISSUED 3 +#define CE0_SC_ISSUED 4 +#define CE0_SC_FAILED 5 +#define CE0_BRANCH_DECODED 6 +#define CE0_QW_WB_SECONDARY 7 +#define CE0_CORRECTED_ECC_ERRORS 8 +#define CE0_ICACHE_MISSES 9 +#define CE0_SCACHE_I_MISSES 10 +#define CE0_SCACHE_I_WAY_MISSPREDICTED 11 +#define CE0_EXT_INTERVENTIONS_REQ 12 +#define CE0_EXT_INVALIDATE_REQ 13 +#define CE0_VIRTUAL_COHERENCY_COND 14 +#define CE0_INSN_GRADUATED 15 + +/* + * Events counted by counter #1 + */ +#define CE1_CYCLES 0 +#define CE1_INSN_GRADUATED 1 +#define CE1_LPSC_GRADUATED 2 +#define CE1_S_GRADUATED 3 +#define CE1_SC_GRADUATED 4 +#define CE1_FP_INSN_GRADUATED 5 +#define CE1_QW_WB_PRIMARY 6 +#define CE1_TLB_REFILL 7 +#define CE1_BRANCH_MISSPREDICTED 8 +#define CE1_DCACHE_MISS 9 +#define CE1_SCACHE_D_MISSES 10 +#define CE1_SCACHE_D_WAY_MISSPREDICTED 11 +#define CE1_EXT_INTERVENTION_HITS 12 +#define CE1_EXT_INVALIDATE_REQ 13 +#define CE1_SP_HINT_TO_CEXCL_SC_BLOCKS 14 +#define CE1_SP_HINT_TO_SHARED_SC_BLOCKS 15 + +/* + * These flags define in which privilege mode the counters count events + */ +#define CEB_USER 8 /* Count events in user mode, EXL = ERL = 0 */ +#define CEB_SUPERVISOR 4 /* Count events in supvervisor mode EXL = ERL = 0 */ +#define CEB_KERNEL 2 /* Count events in kernel mode EXL = ERL = 0 */ +#define CEB_EXL 1 /* Count events with EXL = 1, ERL = 0 */ + + +#ifndef __ASSEMBLY__ + +/* + * Macros to access the system control coprocessor + */ +#define __read_32bit_c0_register(source, sel) \ +({ int __res; \ + if (sel == 0) \ + __asm__ __volatile__( \ + "mfc0\t%0, " #source "\n\t" \ + : "=r" (__res)); \ + else \ + __asm__ __volatile__( \ + ".set\tmips32\n\t" \ + "mfc0\t%0, " #source ", " #sel "\n\t" \ + ".set\tmips0\n\t" \ + : "=r" (__res)); \ + __res; \ +}) + +#define __write_32bit_c0_register(register, sel, value) \ +do { \ + if (sel == 0) \ + __asm__ __volatile__( \ + "mtc0\t%z0, " #register "\n\t" \ + : : "Jr" ((unsigned int)(value))); \ + else \ + __asm__ __volatile__( \ + ".set\tmips32\n\t" \ + "mtc0\t%z0, " #register ", " #sel "\n\t" \ + ".set\tmips0" \ + : : "Jr" ((unsigned int)(value))); \ +} while (0) + +#define read_c0_index() __read_32bit_c0_register($0, 0) +#define write_c0_index(val) __write_32bit_c0_register($0, 0, val) + +#define read_c0_random() __read_32bit_c0_register($1, 0) +#define write_c0_random(val) __write_32bit_c0_register($1, 0, val) + +#define read_c0_entrylo0() __read_32bit_c0_register($2, 0) +#define write_c0_entrylo0(val) __write_32bit_c0_register($2, 0, val) + +#define read_c0_entrylo1() __read_32bit_c0_register($3, 0) +#define write_c0_entrylo1(val) __write_32bit_c0_register($3, 0, val) + +#define read_c0_conf() __read_32bit_c0_register($3, 0) +#define write_c0_conf(val) __write_32bit_c0_register($3, 0, val) + +#define read_c0_context() __read_32bit_c0_register($4, 0) +#define write_c0_context(val) __write_32bit_c0_register($4, 0, val) + +#define read_c0_userlocal() __read_32bit_c0_register($4, 2) +#define write_c0_userlocal(val) __write_32bit_c0_register($4, 2, val) + +#define read_c0_pagemask() __read_32bit_c0_register($5, 0) +#define write_c0_pagemask(val) __write_32bit_c0_register($5, 0, val) + +#define read_c0_wired() __read_32bit_c0_register($6, 0) +#define write_c0_wired(val) __write_32bit_c0_register($6, 0, val) + +#define read_c0_info() __read_32bit_c0_register($7, 0) + +#define read_c0_cache() __read_32bit_c0_register($7, 0) /* TX39xx */ +#define write_c0_cache(val) __write_32bit_c0_register($7, 0, val) + +#define read_c0_badvaddr() __read_32bit_c0_register($8, 0) +#define write_c0_badvaddr(val) __write_32bit_c0_register($8, 0, val) + +#define read_c0_count() __read_32bit_c0_register($9, 0) +#define write_c0_count(val) __write_32bit_c0_register($9, 0, val) + +#define read_c0_count2() __read_32bit_c0_register($9, 6) /* pnx8550 */ +#define write_c0_count2(val) __write_32bit_c0_register($9, 6, val) + +#define read_c0_count3() __read_32bit_c0_register($9, 7) /* pnx8550 */ +#define write_c0_count3(val) __write_32bit_c0_register($9, 7, val) + +#define read_c0_entryhi() __read_32bit_c0_register($10, 0) +#define write_c0_entryhi(val) __write_32bit_c0_register($10, 0, val) + +#define read_c0_compare() __read_32bit_c0_register($11, 0) +#define write_c0_compare(val) __write_32bit_c0_register($11, 0, val) + +#define read_c0_compare2() __read_32bit_c0_register($11, 6) /* pnx8550 */ +#define write_c0_compare2(val) __write_32bit_c0_register($11, 6, val) + +#define read_c0_compare3() __read_32bit_c0_register($11, 7) /* pnx8550 */ +#define write_c0_compare3(val) __write_32bit_c0_register($11, 7, val) + +#define read_c0_status() __read_32bit_c0_register($12, 0) +#define write_c0_status(val) __write_32bit_c0_register($12, 0, val) + +#define read_c0_cause() __read_32bit_c0_register($13, 0) +#define write_c0_cause(val) __write_32bit_c0_register($13, 0, val) + +#define read_c0_epc() __read_32bit_c0_register($14, 0) +#define write_c0_epc(val) __write_32bit_c0_register($14, 0, val) + +#define read_c0_prid() __read_32bit_c0_register($15, 0) + +#define read_c0_ebase() __read_32bit_c0_register($15, 1) +#define write_c0_ebase(val) __write_32bit_c0_register($15, 1, val) + +#define read_c0_config() __read_32bit_c0_register($16, 0) +#define read_c0_config1() __read_32bit_c0_register($16, 1) +#define read_c0_config2() __read_32bit_c0_register($16, 2) +#define read_c0_config3() __read_32bit_c0_register($16, 3) +#define write_c0_config(val) __write_32bit_c0_register($16, 0, val) +#define write_c0_config1(val) __write_32bit_c0_register($16, 1, val) +#define write_c0_config2(val) __write_32bit_c0_register($16, 2, val) +#define write_c0_config3(val) __write_32bit_c0_register($16, 3, val) + + +#endif /* end of __ASSEMBLY__ */ + +#endif /* end of __MIPSREGS_H__ */ + diff --git a/libcpu/mips/common/stackframe.h b/libcpu/mips/common/stackframe.h index ab4eccb2bc..96b69ab14f 100644 --- a/libcpu/mips/common/stackframe.h +++ b/libcpu/mips/common/stackframe.h @@ -1,228 +1,228 @@ -/*
- * This file is subject to the terms and conditions of the GNU General Public
- * License. See the file "COPYING" in the main directory of this archive
- * for more details.
- *
- * Copyright (C) 1994, 95, 96, 99, 2001 Ralf Baechle
- * Copyright (C) 1994, 1995, 1996 Paul M. Antoine.
- * Copyright (C) 1999 Silicon Graphics, Inc.
- * Copyright (C) 2007 Maciej W. Rozycki
- */
-#ifndef __STACKFRAME_H__
-#define __STACKFRAME_H__
-
-#include "asm.h"
-#include "mipsregs.h"
-
-/*
- * Stack layout for the INT exception handler
- * Derived from the stack layout described in asm-mips/stackframe.h
- *
- * The first PTRSIZE*6 bytes are argument save space for C subroutines.
- */
-
-//#define PT_R0 (PTRSIZE*6) /* 0 */
-#define PT_R0 (0) /* 0 */
-#define PT_R1 ((PT_R0) + LONGSIZE) /* 1 */
-#define PT_R2 ((PT_R1) + LONGSIZE) /* 2 */
-#define PT_R3 ((PT_R2) + LONGSIZE) /* 3 */
-#define PT_R4 ((PT_R3) + LONGSIZE) /* 4 */
-#define PT_R5 ((PT_R4) + LONGSIZE) /* 5 */
-#define PT_R6 ((PT_R5) + LONGSIZE) /* 6 */
-#define PT_R7 ((PT_R6) + LONGSIZE) /* 7 */
-#define PT_R8 ((PT_R7) + LONGSIZE) /* 8 */
-#define PT_R9 ((PT_R8) + LONGSIZE) /* 9 */
-#define PT_R10 ((PT_R9) + LONGSIZE) /* 10 */
-#define PT_R11 ((PT_R10) + LONGSIZE) /* 11 */
-#define PT_R12 ((PT_R11) + LONGSIZE) /* 12 */
-#define PT_R13 ((PT_R12) + LONGSIZE) /* 13 */
-#define PT_R14 ((PT_R13) + LONGSIZE) /* 14 */
-#define PT_R15 ((PT_R14) + LONGSIZE) /* 15 */
-#define PT_R16 ((PT_R15) + LONGSIZE) /* 16 */
-#define PT_R17 ((PT_R16) + LONGSIZE) /* 17 */
-#define PT_R18 ((PT_R17) + LONGSIZE) /* 18 */
-#define PT_R19 ((PT_R18) + LONGSIZE) /* 19 */
-#define PT_R20 ((PT_R19) + LONGSIZE) /* 20 */
-#define PT_R21 ((PT_R20) + LONGSIZE) /* 21 */
-#define PT_R22 ((PT_R21) + LONGSIZE) /* 22 */
-#define PT_R23 ((PT_R22) + LONGSIZE) /* 23 */
-#define PT_R24 ((PT_R23) + LONGSIZE) /* 24 */
-#define PT_R25 ((PT_R24) + LONGSIZE) /* 25 */
-#define PT_R26 ((PT_R25) + LONGSIZE) /* 26 */
-#define PT_R27 ((PT_R26) + LONGSIZE) /* 27 */
-#define PT_R28 ((PT_R27) + LONGSIZE) /* 28 */
-#define PT_R29 ((PT_R28) + LONGSIZE) /* 29 */
-#define PT_R30 ((PT_R29) + LONGSIZE) /* 30 */
-#define PT_R31 ((PT_R30) + LONGSIZE) /* 31 */
-
-/*
- * Saved special registers
- */
-#define PT_STATUS ((PT_R31) + LONGSIZE) /* 32 */
-#define PT_HI ((PT_STATUS) + LONGSIZE) /* 33 */
-#define PT_LO ((PT_HI) + LONGSIZE) /* 34 */
-#define PT_BADVADDR ((PT_LO) + LONGSIZE) /* 35 */
-#define PT_CAUSE ((PT_BADVADDR) + LONGSIZE) /* 36 */
-#define PT_EPC ((PT_CAUSE) + LONGSIZE) /* 37 */
-
-#define PT_SIZE ((((PT_EPC) + LONGSIZE) + (PTRSIZE-1)) & ~(PTRSIZE-1))
-
-
- .macro SAVE_AT
- .set push
- .set noat
- LONG_S $1, PT_R1(sp)
- .set pop
- .endm
-
- .macro SAVE_TEMP
- mfhi v1
- LONG_S $8, PT_R8(sp)
- LONG_S $9, PT_R9(sp)
- LONG_S v1, PT_HI(sp)
- mflo v1
- LONG_S $10, PT_R10(sp)
- LONG_S $11, PT_R11(sp)
- LONG_S v1, PT_LO(sp)
- LONG_S $12, PT_R12(sp)
- LONG_S $13, PT_R13(sp)
- LONG_S $14, PT_R14(sp)
- LONG_S $15, PT_R15(sp)
- LONG_S $24, PT_R24(sp)
- .endm
-
- .macro SAVE_STATIC
- LONG_S $16, PT_R16(sp)
- LONG_S $17, PT_R17(sp)
- LONG_S $18, PT_R18(sp)
- LONG_S $19, PT_R19(sp)
- LONG_S $20, PT_R20(sp)
- LONG_S $21, PT_R21(sp)
- LONG_S $22, PT_R22(sp)
- LONG_S $23, PT_R23(sp)
- LONG_S $30, PT_R30(sp)
- .endm
-
- .macro get_saved_sp
- nop
- .endm
-
- .macro SAVE_SOME
- .set push
- .set noat
- .set reorder
- move k1, sp
-8: move k0, sp
- PTR_SUBU sp, k1, PT_SIZE
- LONG_S k0, PT_R29(sp)
- LONG_S $3, PT_R3(sp)
- LONG_S $0, PT_R0(sp)
- mfc0 v1, CP0_STATUS
- LONG_S $2, PT_R2(sp)
- LONG_S v1, PT_STATUS(sp)
- LONG_S $4, PT_R4(sp)
- mfc0 v1, CP0_CAUSE
- LONG_S $5, PT_R5(sp)
- LONG_S v1, PT_CAUSE(sp)
- LONG_S $6, PT_R6(sp)
- MFC0 v1, CP0_EPC
- LONG_S $7, PT_R7(sp)
- LONG_S v1, PT_EPC(sp)
- LONG_S $25, PT_R25(sp)
- LONG_S $28, PT_R28(sp)
- LONG_S $31, PT_R31(sp)
- .set pop
- .endm
-
- .macro SAVE_ALL
- SAVE_SOME
- SAVE_AT
- SAVE_TEMP
- SAVE_STATIC
- .endm
-
- .macro RESTORE_AT
- .set push
- .set noat
- LONG_L $1, PT_R1(sp)
- .set pop
- .endm
-
- .macro RESTORE_TEMP
- LONG_L $24, PT_LO(sp)
- LONG_L $8, PT_R8(sp)
- LONG_L $9, PT_R9(sp)
- mtlo $24
- LONG_L $24, PT_HI(sp)
- LONG_L $10, PT_R10(sp)
- LONG_L $11, PT_R11(sp)
- mthi $24
- LONG_L $12, PT_R12(sp)
- LONG_L $13, PT_R13(sp)
- LONG_L $14, PT_R14(sp)
- LONG_L $15, PT_R15(sp)
- LONG_L $24, PT_R24(sp)
- .endm
-
- .macro RESTORE_STATIC
- LONG_L $16, PT_R16(sp)
- LONG_L $17, PT_R17(sp)
- LONG_L $18, PT_R18(sp)
- LONG_L $19, PT_R19(sp)
- LONG_L $20, PT_R20(sp)
- LONG_L $21, PT_R21(sp)
- LONG_L $22, PT_R22(sp)
- LONG_L $23, PT_R23(sp)
- LONG_L $30, PT_R30(sp)
- .endm
-
- .macro RESTORE_SOME
- .set push
- .set reorder
- .set noat
- LONG_L v0, PT_STATUS(sp)
- mtc0 v0, CP0_STATUS
- LONG_L v1, PT_EPC(sp)
- MTC0 v1, CP0_EPC
- LONG_L $31, PT_R31(sp)
- LONG_L $28, PT_R28(sp)
- LONG_L $25, PT_R25(sp)
- LONG_L $7, PT_R7(sp)
- LONG_L $6, PT_R6(sp)
- LONG_L $5, PT_R5(sp)
- LONG_L $4, PT_R4(sp)
- LONG_L $3, PT_R3(sp)
- LONG_L $2, PT_R2(sp)
- .set pop
- .endm
-
- .macro RESTORE_SP_AND_RET
- LONG_L sp, PT_R29(sp)
- .set mips3
- eret
- .set mips0
- .endm
-
-
- .macro RESTORE_SP
- LONG_L sp, PT_R29(sp)
- .endm
-
- .macro RESTORE_ALL
- RESTORE_TEMP
- RESTORE_STATIC
- RESTORE_AT
- RESTORE_SOME
- RESTORE_SP
- .endm
-
- .macro RESTORE_ALL_AND_RET
- RESTORE_TEMP
- RESTORE_STATIC
- RESTORE_AT
- RESTORE_SOME
- RESTORE_SP_AND_RET
- .endm
-
-#endif /* end of __STACKFRAME_H__ */
-
+/* + * This file is subject to the terms and conditions of the GNU General Public + * License. See the file "COPYING" in the main directory of this archive + * for more details. + * + * Copyright (C) 1994, 95, 96, 99, 2001 Ralf Baechle + * Copyright (C) 1994, 1995, 1996 Paul M. Antoine. + * Copyright (C) 1999 Silicon Graphics, Inc. + * Copyright (C) 2007 Maciej W. Rozycki + */ +#ifndef __STACKFRAME_H__ +#define __STACKFRAME_H__ + +#include "asm.h" +#include "mipsregs.h" + +/* + * Stack layout for the INT exception handler + * Derived from the stack layout described in asm-mips/stackframe.h + * + * The first PTRSIZE*6 bytes are argument save space for C subroutines. + */ + +//#define PT_R0 (PTRSIZE*6) /* 0 */ +#define PT_R0 (0) /* 0 */ +#define PT_R1 ((PT_R0) + LONGSIZE) /* 1 */ +#define PT_R2 ((PT_R1) + LONGSIZE) /* 2 */ +#define PT_R3 ((PT_R2) + LONGSIZE) /* 3 */ +#define PT_R4 ((PT_R3) + LONGSIZE) /* 4 */ +#define PT_R5 ((PT_R4) + LONGSIZE) /* 5 */ +#define PT_R6 ((PT_R5) + LONGSIZE) /* 6 */ +#define PT_R7 ((PT_R6) + LONGSIZE) /* 7 */ +#define PT_R8 ((PT_R7) + LONGSIZE) /* 8 */ +#define PT_R9 ((PT_R8) + LONGSIZE) /* 9 */ +#define PT_R10 ((PT_R9) + LONGSIZE) /* 10 */ +#define PT_R11 ((PT_R10) + LONGSIZE) /* 11 */ +#define PT_R12 ((PT_R11) + LONGSIZE) /* 12 */ +#define PT_R13 ((PT_R12) + LONGSIZE) /* 13 */ +#define PT_R14 ((PT_R13) + LONGSIZE) /* 14 */ +#define PT_R15 ((PT_R14) + LONGSIZE) /* 15 */ +#define PT_R16 ((PT_R15) + LONGSIZE) /* 16 */ +#define PT_R17 ((PT_R16) + LONGSIZE) /* 17 */ +#define PT_R18 ((PT_R17) + LONGSIZE) /* 18 */ +#define PT_R19 ((PT_R18) + LONGSIZE) /* 19 */ +#define PT_R20 ((PT_R19) + LONGSIZE) /* 20 */ +#define PT_R21 ((PT_R20) + LONGSIZE) /* 21 */ +#define PT_R22 ((PT_R21) + LONGSIZE) /* 22 */ +#define PT_R23 ((PT_R22) + LONGSIZE) /* 23 */ +#define PT_R24 ((PT_R23) + LONGSIZE) /* 24 */ +#define PT_R25 ((PT_R24) + LONGSIZE) /* 25 */ +#define PT_R26 ((PT_R25) + LONGSIZE) /* 26 */ +#define PT_R27 ((PT_R26) + LONGSIZE) /* 27 */ +#define PT_R28 ((PT_R27) + LONGSIZE) /* 28 */ +#define PT_R29 ((PT_R28) + LONGSIZE) /* 29 */ +#define PT_R30 ((PT_R29) + LONGSIZE) /* 30 */ +#define PT_R31 ((PT_R30) + LONGSIZE) /* 31 */ + +/* + * Saved special registers + */ +#define PT_STATUS ((PT_R31) + LONGSIZE) /* 32 */ +#define PT_HI ((PT_STATUS) + LONGSIZE) /* 33 */ +#define PT_LO ((PT_HI) + LONGSIZE) /* 34 */ +#define PT_BADVADDR ((PT_LO) + LONGSIZE) /* 35 */ +#define PT_CAUSE ((PT_BADVADDR) + LONGSIZE) /* 36 */ +#define PT_EPC ((PT_CAUSE) + LONGSIZE) /* 37 */ + +#define PT_SIZE ((((PT_EPC) + LONGSIZE) + (PTRSIZE-1)) & ~(PTRSIZE-1)) + + + .macro SAVE_AT + .set push + .set noat + LONG_S $1, PT_R1(sp) + .set pop + .endm + + .macro SAVE_TEMP + mfhi v1 + LONG_S $8, PT_R8(sp) + LONG_S $9, PT_R9(sp) + LONG_S v1, PT_HI(sp) + mflo v1 + LONG_S $10, PT_R10(sp) + LONG_S $11, PT_R11(sp) + LONG_S v1, PT_LO(sp) + LONG_S $12, PT_R12(sp) + LONG_S $13, PT_R13(sp) + LONG_S $14, PT_R14(sp) + LONG_S $15, PT_R15(sp) + LONG_S $24, PT_R24(sp) + .endm + + .macro SAVE_STATIC + LONG_S $16, PT_R16(sp) + LONG_S $17, PT_R17(sp) + LONG_S $18, PT_R18(sp) + LONG_S $19, PT_R19(sp) + LONG_S $20, PT_R20(sp) + LONG_S $21, PT_R21(sp) + LONG_S $22, PT_R22(sp) + LONG_S $23, PT_R23(sp) + LONG_S $30, PT_R30(sp) + .endm + + .macro get_saved_sp + nop + .endm + + .macro SAVE_SOME + .set push + .set noat + .set reorder + move k1, sp +8: move k0, sp + PTR_SUBU sp, k1, PT_SIZE + LONG_S k0, PT_R29(sp) + LONG_S $3, PT_R3(sp) + LONG_S $0, PT_R0(sp) + mfc0 v1, CP0_STATUS + LONG_S $2, PT_R2(sp) + LONG_S v1, PT_STATUS(sp) + LONG_S $4, PT_R4(sp) + mfc0 v1, CP0_CAUSE + LONG_S $5, PT_R5(sp) + LONG_S v1, PT_CAUSE(sp) + LONG_S $6, PT_R6(sp) + MFC0 v1, CP0_EPC + LONG_S $7, PT_R7(sp) + LONG_S v1, PT_EPC(sp) + LONG_S $25, PT_R25(sp) + LONG_S $28, PT_R28(sp) + LONG_S $31, PT_R31(sp) + .set pop + .endm + + .macro SAVE_ALL + SAVE_SOME + SAVE_AT + SAVE_TEMP + SAVE_STATIC + .endm + + .macro RESTORE_AT + .set push + .set noat + LONG_L $1, PT_R1(sp) + .set pop + .endm + + .macro RESTORE_TEMP + LONG_L $24, PT_LO(sp) + LONG_L $8, PT_R8(sp) + LONG_L $9, PT_R9(sp) + mtlo $24 + LONG_L $24, PT_HI(sp) + LONG_L $10, PT_R10(sp) + LONG_L $11, PT_R11(sp) + mthi $24 + LONG_L $12, PT_R12(sp) + LONG_L $13, PT_R13(sp) + LONG_L $14, PT_R14(sp) + LONG_L $15, PT_R15(sp) + LONG_L $24, PT_R24(sp) + .endm + + .macro RESTORE_STATIC + LONG_L $16, PT_R16(sp) + LONG_L $17, PT_R17(sp) + LONG_L $18, PT_R18(sp) + LONG_L $19, PT_R19(sp) + LONG_L $20, PT_R20(sp) + LONG_L $21, PT_R21(sp) + LONG_L $22, PT_R22(sp) + LONG_L $23, PT_R23(sp) + LONG_L $30, PT_R30(sp) + .endm + + .macro RESTORE_SOME + .set push + .set reorder + .set noat + LONG_L v0, PT_STATUS(sp) + mtc0 v0, CP0_STATUS + LONG_L v1, PT_EPC(sp) + MTC0 v1, CP0_EPC + LONG_L $31, PT_R31(sp) + LONG_L $28, PT_R28(sp) + LONG_L $25, PT_R25(sp) + LONG_L $7, PT_R7(sp) + LONG_L $6, PT_R6(sp) + LONG_L $5, PT_R5(sp) + LONG_L $4, PT_R4(sp) + LONG_L $3, PT_R3(sp) + LONG_L $2, PT_R2(sp) + .set pop + .endm + + .macro RESTORE_SP_AND_RET + LONG_L sp, PT_R29(sp) + .set mips3 + eret + .set mips0 + .endm + + + .macro RESTORE_SP + LONG_L sp, PT_R29(sp) + .endm + + .macro RESTORE_ALL + RESTORE_TEMP + RESTORE_STATIC + RESTORE_AT + RESTORE_SOME + RESTORE_SP + .endm + + .macro RESTORE_ALL_AND_RET + RESTORE_TEMP + RESTORE_STATIC + RESTORE_AT + RESTORE_SOME + RESTORE_SP_AND_RET + .endm + +#endif /* end of __STACKFRAME_H__ */ + diff --git a/libcpu/mips/jz47xx/cache.c b/libcpu/mips/jz47xx/cache.c index e00292675e..8a502cdb12 100644 --- a/libcpu/mips/jz47xx/cache.c +++ b/libcpu/mips/jz47xx/cache.c @@ -1,93 +1,93 @@ -#include "jz47xx.h"
-#include "cache.h"
-
-#define CACHE_SIZE 16*1024
-#define CACHE_LINE_SIZE 32
-#define KSEG0 0x80000000
-
-
-#define K0_TO_K1() \
-do { \
- unsigned long __k0_addr; \
- \
- __asm__ __volatile__( \
- "la %0, 1f\n\t" \
- "or %0, %0, %1\n\t" \
- "jr %0\n\t" \
- "nop\n\t" \
- "1: nop\n" \
- : "=&r"(__k0_addr) \
- : "r" (0x20000000) ); \
-} while(0)
-
-#define K1_TO_K0() \
-do { \
- unsigned long __k0_addr; \
- __asm__ __volatile__( \
- "nop;nop;nop;nop;nop;nop;nop\n\t" \
- "la %0, 1f\n\t" \
- "jr %0\n\t" \
- "nop\n\t" \
- "1: nop\n" \
- : "=&r" (__k0_addr)); \
-} while (0)
-
-#define INVALIDATE_BTB() \
-do { \
- unsigned long tmp; \
- __asm__ __volatile__( \
- ".set mips32\n\t" \
- "mfc0 %0, $16, 7\n\t" \
- "nop\n\t" \
- "ori %0, 2\n\t" \
- "mtc0 %0, $16, 7\n\t" \
- "nop\n\t" \
- ".set mips2\n\t" \
- : "=&r" (tmp)); \
-} while (0)
-
-#define SYNC_WB() __asm__ __volatile__ ("sync")
-
-#define cache_op(op,addr) \
- __asm__ __volatile__( \
- " .set noreorder \n" \
- " .set mips32\n\t \n" \
- " cache %0, %1 \n" \
- " .set mips0 \n" \
- " .set reorder" \
- : \
- : "i" (op), "m" (*(unsigned char *)(addr)))
-
-void __icache_invalidate_all(void)
-{
- unsigned int i;
-
- K0_TO_K1();
-
- asm volatile (".set noreorder\n"
- ".set mips32\n\t"
- "mtc0\t$0,$28\n\t"
- "mtc0\t$0,$29\n"
- ".set mips0\n"
- ".set reorder\n");
- for (i=KSEG0;i<KSEG0+CACHE_SIZE;i+=CACHE_LINE_SIZE)
- cache_op(Index_Store_Tag_I, i);
-
- K1_TO_K0();
-
- INVALIDATE_BTB();
-}
-
-void __dcache_writeback_all(void)
-{
- unsigned int i;
- for (i=KSEG0;i<KSEG0+CACHE_SIZE;i+=CACHE_LINE_SIZE)
- cache_op(Index_Writeback_Inv_D, i);
- SYNC_WB();
-}
-
-void rt_hw_cache_init(void)
-{
- __dcache_writeback_all();
- __icache_invalidate_all();
-}
+#include "jz47xx.h" +#include "cache.h" + +#define CACHE_SIZE 16*1024 +#define CACHE_LINE_SIZE 32 +#define KSEG0 0x80000000 + + +#define K0_TO_K1() \ +do { \ + unsigned long __k0_addr; \ + \ + __asm__ __volatile__( \ + "la %0, 1f\n\t" \ + "or %0, %0, %1\n\t" \ + "jr %0\n\t" \ + "nop\n\t" \ + "1: nop\n" \ + : "=&r"(__k0_addr) \ + : "r" (0x20000000) ); \ +} while(0) + +#define K1_TO_K0() \ +do { \ + unsigned long __k0_addr; \ + __asm__ __volatile__( \ + "nop;nop;nop;nop;nop;nop;nop\n\t" \ + "la %0, 1f\n\t" \ + "jr %0\n\t" \ + "nop\n\t" \ + "1: nop\n" \ + : "=&r" (__k0_addr)); \ +} while (0) + +#define INVALIDATE_BTB() \ +do { \ + unsigned long tmp; \ + __asm__ __volatile__( \ + ".set mips32\n\t" \ + "mfc0 %0, $16, 7\n\t" \ + "nop\n\t" \ + "ori %0, 2\n\t" \ + "mtc0 %0, $16, 7\n\t" \ + "nop\n\t" \ + ".set mips2\n\t" \ + : "=&r" (tmp)); \ +} while (0) + +#define SYNC_WB() __asm__ __volatile__ ("sync") + +#define cache_op(op,addr) \ + __asm__ __volatile__( \ + " .set noreorder \n" \ + " .set mips32\n\t \n" \ + " cache %0, %1 \n" \ + " .set mips0 \n" \ + " .set reorder" \ + : \ + : "i" (op), "m" (*(unsigned char *)(addr))) + +void __icache_invalidate_all(void) +{ + unsigned int i; + + K0_TO_K1(); + + asm volatile (".set noreorder\n" + ".set mips32\n\t" + "mtc0\t$0,$28\n\t" + "mtc0\t$0,$29\n" + ".set mips0\n" + ".set reorder\n"); + for (i=KSEG0;i<KSEG0+CACHE_SIZE;i+=CACHE_LINE_SIZE) + cache_op(Index_Store_Tag_I, i); + + K1_TO_K0(); + + INVALIDATE_BTB(); +} + +void __dcache_writeback_all(void) +{ + unsigned int i; + for (i=KSEG0;i<KSEG0+CACHE_SIZE;i+=CACHE_LINE_SIZE) + cache_op(Index_Writeback_Inv_D, i); + SYNC_WB(); +} + +void rt_hw_cache_init(void) +{ + __dcache_writeback_all(); + __icache_invalidate_all(); +} diff --git a/libcpu/mips/jz47xx/cache.h b/libcpu/mips/jz47xx/cache.h index ad4b57defa..d1f3e25493 100644 --- a/libcpu/mips/jz47xx/cache.h +++ b/libcpu/mips/jz47xx/cache.h @@ -1,40 +1,40 @@ -#ifndef __CACHE_H__
-#define __CACHE_H__
-
-/*
- * Cache Operations
- */
-#define Index_Invalidate_I 0x00
-#define Index_Writeback_Inv_D 0x01
-#define Index_Invalidate_SI 0x02
-#define Index_Writeback_Inv_SD 0x03
-#define Index_Load_Tag_I 0x04
-#define Index_Load_Tag_D 0x05
-#define Index_Load_Tag_SI 0x06
-#define Index_Load_Tag_SD 0x07
-#define Index_Store_Tag_I 0x08
-#define Index_Store_Tag_D 0x09
-#define Index_Store_Tag_SI 0x0A
-#define Index_Store_Tag_SD 0x0B
-#define Create_Dirty_Excl_D 0x0d
-#define Create_Dirty_Excl_SD 0x0f
-#define Hit_Invalidate_I 0x10
-#define Hit_Invalidate_D 0x11
-#define Hit_Invalidate_SI 0x12
-#define Hit_Invalidate_SD 0x13
-#define Fill 0x14
-#define Hit_Writeback_Inv_D 0x15
-/* 0x16 is unused */
-#define Hit_Writeback_Inv_SD 0x17
-#define Hit_Writeback_I 0x18
-#define Hit_Writeback_D 0x19
-/* 0x1a is unused */
-#define Hit_Writeback_SD 0x1b
-/* 0x1c is unused */
-/* 0x1e is unused */
-#define Hit_Set_Virtual_SI 0x1e
-#define Hit_Set_Virtual_SD 0x1f
-
-void rt_hw_cache_init(void);
-
-#endif
+#ifndef __CACHE_H__ +#define __CACHE_H__ + +/* + * Cache Operations + */ +#define Index_Invalidate_I 0x00 +#define Index_Writeback_Inv_D 0x01 +#define Index_Invalidate_SI 0x02 +#define Index_Writeback_Inv_SD 0x03 +#define Index_Load_Tag_I 0x04 +#define Index_Load_Tag_D 0x05 +#define Index_Load_Tag_SI 0x06 +#define Index_Load_Tag_SD 0x07 +#define Index_Store_Tag_I 0x08 +#define Index_Store_Tag_D 0x09 +#define Index_Store_Tag_SI 0x0A +#define Index_Store_Tag_SD 0x0B +#define Create_Dirty_Excl_D 0x0d +#define Create_Dirty_Excl_SD 0x0f +#define Hit_Invalidate_I 0x10 +#define Hit_Invalidate_D 0x11 +#define Hit_Invalidate_SI 0x12 +#define Hit_Invalidate_SD 0x13 +#define Fill 0x14 +#define Hit_Writeback_Inv_D 0x15 +/* 0x16 is unused */ +#define Hit_Writeback_Inv_SD 0x17 +#define Hit_Writeback_I 0x18 +#define Hit_Writeback_D 0x19 +/* 0x1a is unused */ +#define Hit_Writeback_SD 0x1b +/* 0x1c is unused */ +/* 0x1e is unused */ +#define Hit_Set_Virtual_SI 0x1e +#define Hit_Set_Virtual_SD 0x1f + +void rt_hw_cache_init(void); + +#endif diff --git a/libcpu/mips/jz47xx/cache_gcc.S b/libcpu/mips/jz47xx/cache_gcc.S index 3b1e430753..76552698d0 100644 --- a/libcpu/mips/jz47xx/cache_gcc.S +++ b/libcpu/mips/jz47xx/cache_gcc.S @@ -1,42 +1,42 @@ -/*
- * File : cache_init.S
- * Change Logs:
- * Date Author Notes
- * 2010-05-17 swkyer first version
- */
-#include "../common/mips.inc"
-#include "../common/mipsregs.h"
-#include "../common/stackframe.h"
-
- .text
- .set noreorder
-
- .globl cache_init
- .ent cache_init
-cache_init:
- .set noreorder
- mtc0 zero, CP0_TAGLO
- move t0, a0 // cache total size
- move t1, a1 // cache line size
- li t2, 0x80000000
- addu t3, t0, t2
-
-_cache_init_loop:
- cache 8, 0(t2) // icache_index_store_tag
- cache 9, 0(t2) // dcache_index_store_tag
- addu t2, t1
- bne t2, t3, _cache_init_loop
- nop
-
- mfc0 t0, CP0_CONFIG
- li t1, 0x7
- not t1
- and t0, t0, t1
- or t0, 0x3 // cacheable, noncoherent, write-back, write allocate
- mtc0 t0, CP0_CONFIG
-
- jr ra
- nop
-
- .set reorder
- .end cache_init
+/* + * File : cache_init.S + * Change Logs: + * Date Author Notes + * 2010-05-17 swkyer first version + */ +#include "../common/mips.inc" +#include "../common/mipsregs.h" +#include "../common/stackframe.h" + + .text + .set noreorder + + .globl cache_init + .ent cache_init +cache_init: + .set noreorder + mtc0 zero, CP0_TAGLO + move t0, a0 // cache total size + move t1, a1 // cache line size + li t2, 0x80000000 + addu t3, t0, t2 + +_cache_init_loop: + cache 8, 0(t2) // icache_index_store_tag + cache 9, 0(t2) // dcache_index_store_tag + addu t2, t1 + bne t2, t3, _cache_init_loop + nop + + mfc0 t0, CP0_CONFIG + li t1, 0x7 + not t1 + and t0, t0, t1 + or t0, 0x3 // cacheable, noncoherent, write-back, write allocate + mtc0 t0, CP0_CONFIG + + jr ra + nop + + .set reorder + .end cache_init diff --git a/libcpu/mips/jz47xx/context_gcc.S b/libcpu/mips/jz47xx/context_gcc.S index 42b0d13033..b480a10219 100644 --- a/libcpu/mips/jz47xx/context_gcc.S +++ b/libcpu/mips/jz47xx/context_gcc.S @@ -1,146 +1,146 @@ -/*
- * File : context_gcc.S
- * Change Logs:
- * Date Author Notes
- * 2010-05-17 swkyer first version
- * 2010-09-11 bernard port to Jz4755
- */
-#include "../common/mips.inc"
-#include "../common/stackframe.h"
-#include "jz47xx.h"
-
- .section ".text", "ax"
- .set noreorder
-
-/*
- * rt_base_t rt_hw_interrupt_disable()
- */
- .globl rt_hw_interrupt_disable
-rt_hw_interrupt_disable:
- mfc0 v0, CP0_STATUS
- and v1, v0, 0xfffffffe
- mtc0 v1, CP0_STATUS
- jr ra
- nop
-
-/*
- * void rt_hw_interrupt_enable(rt_base_t level)
- */
- .globl rt_hw_interrupt_enable
-rt_hw_interrupt_enable:
- mtc0 a0, CP0_STATUS
- jr ra
- nop
-
-/*
- * void rt_hw_context_switch(rt_uint32 from, rt_uint32 to)
- * a0 --> from
- * a1 --> to
- */
- .globl rt_hw_context_switch
-rt_hw_context_switch:
- mtc0 ra, CP0_EPC
- SAVE_ALL
-
- sw sp, 0(a0) /* store sp in preempted tasks TCB */
- lw sp, 0(a1) /* get new task stack pointer */
-
- RESTORE_ALL_AND_RET
-
-/*
- * void rt_hw_context_switch_to(rt_uint32 to)/*
- * a0 --> to
- */
- .globl rt_hw_context_switch_to
-rt_hw_context_switch_to:
- lw sp, 0(a0) /* get new task stack pointer */
-
- RESTORE_ALL_AND_RET
-
-/*
- * void rt_hw_context_switch_interrupt(rt_uint32 from, rt_uint32 to)/*
- */
- .globl rt_thread_switch_interrupt_flag
- .globl rt_interrupt_from_thread
- .globl rt_interrupt_to_thread
- .globl rt_hw_context_switch_interrupt
-rt_hw_context_switch_interrupt:
- la t0, rt_thread_switch_interrupt_flag
- lw t1, 0(t0)
- nop
- bnez t1, _reswitch
- nop
- li t1, 0x01 /* set rt_thread_switch_interrupt_flag to 1 */
- sw t1, 0(t0)
- la t0, rt_interrupt_from_thread /* set rt_interrupt_from_thread */
- sw a0, 0(t0)
-_reswitch:
- la t0, rt_interrupt_to_thread /* set rt_interrupt_to_thread */
- sw a1, 0(t0)
- jr ra
- nop
-
- .globl system_dump
-
-/*
- * void rt_hw_context_switch_interrupt_do(rt_base_t flag)
- */
- .globl rt_interrupt_enter
- .globl rt_interrupt_leave
- .globl mips_irq_handle
-mips_irq_handle:
- SAVE_ALL
-
- mfc0 t0, CP0_CAUSE
- mfc0 t1, CP0_STATUS
- and t0, t1
-
- andi t0, 0xff00
- beqz t0, spurious_interrupt
- nop
-
- /* let k0 keep the current context sp */
- move k0, sp
- /* switch to kernel stack */
- li sp, SYSTEM_STACK
-
- jal rt_interrupt_enter
- nop
- jal rt_interrupt_dispatch
- nop
- jal rt_interrupt_leave
- nop
-
- /* switch sp back to thread's context */
- move sp, k0
-
- /*
- * if rt_thread_switch_interrupt_flag set, jump to
- * rt_hw_context_switch_interrupt_do and don't return
- */
- la k0, rt_thread_switch_interrupt_flag
- lw k1, 0(k0)
- beqz k1, spurious_interrupt
- nop
- sw zero, 0(k0) /* clear flag */
- nop
-
- /*
- * switch to the new thread
- */
- la k0, rt_interrupt_from_thread
- lw k1, 0(k0)
- nop
- sw sp, 0(k1) /* store sp in preempted tasks's TCB */
-
- la k0, rt_interrupt_to_thread
- lw k1, 0(k0)
- nop
- lw sp, 0(k1) /* get new task's stack pointer */
- j spurious_interrupt
- nop
-
-spurious_interrupt:
- RESTORE_ALL_AND_RET
-
- .set reorder
+/* + * File : context_gcc.S + * Change Logs: + * Date Author Notes + * 2010-05-17 swkyer first version + * 2010-09-11 bernard port to Jz4755 + */ +#include "../common/mips.inc" +#include "../common/stackframe.h" +#include "jz47xx.h" + + .section ".text", "ax" + .set noreorder + +/* + * rt_base_t rt_hw_interrupt_disable() + */ + .globl rt_hw_interrupt_disable +rt_hw_interrupt_disable: + mfc0 v0, CP0_STATUS + and v1, v0, 0xfffffffe + mtc0 v1, CP0_STATUS + jr ra + nop + +/* + * void rt_hw_interrupt_enable(rt_base_t level) + */ + .globl rt_hw_interrupt_enable +rt_hw_interrupt_enable: + mtc0 a0, CP0_STATUS + jr ra + nop + +/* + * void rt_hw_context_switch(rt_uint32 from, rt_uint32 to) + * a0 --> from + * a1 --> to + */ + .globl rt_hw_context_switch +rt_hw_context_switch: + mtc0 ra, CP0_EPC + SAVE_ALL + + sw sp, 0(a0) /* store sp in preempted tasks TCB */ + lw sp, 0(a1) /* get new task stack pointer */ + + RESTORE_ALL_AND_RET + +/* + * void rt_hw_context_switch_to(rt_uint32 to)/* + * a0 --> to + */ + .globl rt_hw_context_switch_to +rt_hw_context_switch_to: + lw sp, 0(a0) /* get new task stack pointer */ + + RESTORE_ALL_AND_RET + +/* + * void rt_hw_context_switch_interrupt(rt_uint32 from, rt_uint32 to)/* + */ + .globl rt_thread_switch_interrupt_flag + .globl rt_interrupt_from_thread + .globl rt_interrupt_to_thread + .globl rt_hw_context_switch_interrupt +rt_hw_context_switch_interrupt: + la t0, rt_thread_switch_interrupt_flag + lw t1, 0(t0) + nop + bnez t1, _reswitch + nop + li t1, 0x01 /* set rt_thread_switch_interrupt_flag to 1 */ + sw t1, 0(t0) + la t0, rt_interrupt_from_thread /* set rt_interrupt_from_thread */ + sw a0, 0(t0) +_reswitch: + la t0, rt_interrupt_to_thread /* set rt_interrupt_to_thread */ + sw a1, 0(t0) + jr ra + nop + + .globl system_dump + +/* + * void rt_hw_context_switch_interrupt_do(rt_base_t flag) + */ + .globl rt_interrupt_enter + .globl rt_interrupt_leave + .globl mips_irq_handle +mips_irq_handle: + SAVE_ALL + + mfc0 t0, CP0_CAUSE + mfc0 t1, CP0_STATUS + and t0, t1 + + andi t0, 0xff00 + beqz t0, spurious_interrupt + nop + + /* let k0 keep the current context sp */ + move k0, sp + /* switch to kernel stack */ + li sp, SYSTEM_STACK + + jal rt_interrupt_enter + nop + jal rt_interrupt_dispatch + nop + jal rt_interrupt_leave + nop + + /* switch sp back to thread's context */ + move sp, k0 + + /* + * if rt_thread_switch_interrupt_flag set, jump to + * rt_hw_context_switch_interrupt_do and don't return + */ + la k0, rt_thread_switch_interrupt_flag + lw k1, 0(k0) + beqz k1, spurious_interrupt + nop + sw zero, 0(k0) /* clear flag */ + nop + + /* + * switch to the new thread + */ + la k0, rt_interrupt_from_thread + lw k1, 0(k0) + nop + sw sp, 0(k1) /* store sp in preempted tasks's TCB */ + + la k0, rt_interrupt_to_thread + lw k1, 0(k0) + nop + lw sp, 0(k1) /* get new task's stack pointer */ + j spurious_interrupt + nop + +spurious_interrupt: + RESTORE_ALL_AND_RET + + .set reorder diff --git a/libcpu/mips/jz47xx/cpu.c b/libcpu/mips/jz47xx/cpu.c index 1db6a97c02..f44a44e020 100644 --- a/libcpu/mips/jz47xx/cpu.c +++ b/libcpu/mips/jz47xx/cpu.c @@ -1,68 +1,68 @@ -/*
- * File : cpu.c
- * This file is part of RT-Thread RTOS
- * COPYRIGHT (C) 2006 - 2010, RT-Thread Development Team
- *
- * The license and distribution terms for this file may be
- * found in the file LICENSE in this distribution or at
- * http://www.rt-thread.org/license/LICENSE
- *
- * Change Logs:
- * Date Author Notes
- * 2010-07-09 Bernard first version
- * 2010-09-11 Bernard add CPU reset implementation
- */
-#include <rtthread.h>
-#include <jz4755.h>
-
-/* Watchdog definitions */
-#define WDT_CLK_PRESCALE_CLK1 ( 0x0 << 3)
-#define WDT_CLK_PRESCALE_CLK4 ( 0x1 << 3)
-#define WDT_CLK_PRESCALE_CLK16 ( 0x2 << 3)
-#define WDT_CLK_PRESCALE_CLK64 ( 0x3 << 3)
-#define WDT_CLK_PRESCALE_CLK256 ( 0x4 << 3)
-#define WDT_CLK_PRESCALE_CLK1024 ( 0x5 << 3)
-#define WDT_CLK_PRESCALE_MASK ( 0x3F << 3)
-
-#define WDT_CLK_EXTAL ( 0x1 << 2)
-#define WDT_CLK_RTC ( 0x1 << 1)
-#define WDT_CLK_PCLK ( 0x1 << 0)
-#define WDT_CLK_MASK ( 7 )
-
-#define WDT_ENABLE ( 1 << 0 )
-
-/**
- * @addtogroup Jz47xx
- */
-/*@{*/
-
-/**
- * this function will reset CPU
- *
- */
-void rt_hw_cpu_reset()
-{
- /* open the watch-dog */
- WDT_TCSR = WDT_CLK_EXTAL;
- WDT_TCSR |= WDT_CLK_PRESCALE_CLK1024;
- WDT_TDR = 0x03;
- WDT_TCNT = 0x00;
- WDT_TCER |= WDT_ENABLE;
-
- rt_kprintf("reboot system...\n");
- while (1);
-}
-
-/**
- * this function will shutdown CPU
- *
- */
-void rt_hw_cpu_shutdown()
-{
- rt_kprintf("shutdown...\n");
-
- while (1);
-}
-
-/*@}*/
-
+/* + * File : cpu.c + * This file is part of RT-Thread RTOS + * COPYRIGHT (C) 2006 - 2010, RT-Thread Development Team + * + * The license and distribution terms for this file may be + * found in the file LICENSE in this distribution or at + * http://www.rt-thread.org/license/LICENSE + * + * Change Logs: + * Date Author Notes + * 2010-07-09 Bernard first version + * 2010-09-11 Bernard add CPU reset implementation + */ +#include <rtthread.h> +#include <jz4755.h> + +/* Watchdog definitions */ +#define WDT_CLK_PRESCALE_CLK1 ( 0x0 << 3) +#define WDT_CLK_PRESCALE_CLK4 ( 0x1 << 3) +#define WDT_CLK_PRESCALE_CLK16 ( 0x2 << 3) +#define WDT_CLK_PRESCALE_CLK64 ( 0x3 << 3) +#define WDT_CLK_PRESCALE_CLK256 ( 0x4 << 3) +#define WDT_CLK_PRESCALE_CLK1024 ( 0x5 << 3) +#define WDT_CLK_PRESCALE_MASK ( 0x3F << 3) + +#define WDT_CLK_EXTAL ( 0x1 << 2) +#define WDT_CLK_RTC ( 0x1 << 1) +#define WDT_CLK_PCLK ( 0x1 << 0) +#define WDT_CLK_MASK ( 7 ) + +#define WDT_ENABLE ( 1 << 0 ) + +/** + * @addtogroup Jz47xx + */ +/*@{*/ + +/** + * this function will reset CPU + * + */ +void rt_hw_cpu_reset() +{ + /* open the watch-dog */ + WDT_TCSR = WDT_CLK_EXTAL; + WDT_TCSR |= WDT_CLK_PRESCALE_CLK1024; + WDT_TDR = 0x03; + WDT_TCNT = 0x00; + WDT_TCER |= WDT_ENABLE; + + rt_kprintf("reboot system...\n"); + while (1); +} + +/** + * this function will shutdown CPU + * + */ +void rt_hw_cpu_shutdown() +{ + rt_kprintf("shutdown...\n"); + + while (1); +} + +/*@}*/ + diff --git a/libcpu/mips/jz47xx/exception.c b/libcpu/mips/jz47xx/exception.c index de14c0969c..6d47d3ca4e 100644 --- a/libcpu/mips/jz47xx/exception.c +++ b/libcpu/mips/jz47xx/exception.c @@ -1,65 +1,65 @@ -/*
- * File : exception.c
- * Change Logs:
- * Date Author Notes
- * 2010-05-17 swkyer first version
- */
-#include <rtthread.h>
-#include <rthw.h>
-#include "../common/exception.h"
-#include "../common/mipsregs.h"
-
-/**
- * @addtogroup Jz47xx
- */
-/*@{*/
-
-/**
- * exception handle table
- */
-exception_func_t sys_exception_handlers[33];
-
-/**
- * setup the exception handle
- */
-exception_func_t rt_set_except_vector(int n, exception_func_t func)
-{
- exception_func_t old_handler = sys_exception_handlers[n];
-
- if ((n == 0) || (n > 32) || (!func))
- {
- return 0;
- }
-
- sys_exception_handlers[n] = func;
-
- return old_handler;
-}
-
-void tlb_refill_handler(void)
-{
- rt_kprintf("tlb-miss happens, epc: 0x%08x\n", read_c0_epc());
- rt_hw_cpu_shutdown();
-}
-
-void cache_error_handler(void)
-{
- rt_kprintf("cache exception happens, epc: 0x%08x\n", read_c0_epc());
- rt_hw_cpu_shutdown();
-}
-
-static void unhandled_exception_handle(pt_regs_t *regs)
-{
- rt_kprintf("exception happens, epc: 0x%08x\n", regs->cp0_epc);
-}
-
-void install_default_execpt_handle(void)
-{
- rt_int32_t i;
-
- for (i=0; i<33; i++)
- sys_exception_handlers[i] = (exception_func_t)unhandled_exception_handle;
-}
-
-/*@}*/
-
+/* + * File : exception.c + * Change Logs: + * Date Author Notes + * 2010-05-17 swkyer first version + */ +#include <rtthread.h> +#include <rthw.h> +#include "../common/exception.h" +#include "../common/mipsregs.h" + +/** + * @addtogroup Jz47xx + */ +/*@{*/ + +/** + * exception handle table + */ +exception_func_t sys_exception_handlers[33]; + +/** + * setup the exception handle + */ +exception_func_t rt_set_except_vector(int n, exception_func_t func) +{ + exception_func_t old_handler = sys_exception_handlers[n]; + + if ((n == 0) || (n > 32) || (!func)) + { + return 0; + } + + sys_exception_handlers[n] = func; + + return old_handler; +} + +void tlb_refill_handler(void) +{ + rt_kprintf("tlb-miss happens, epc: 0x%08x\n", read_c0_epc()); + rt_hw_cpu_shutdown(); +} + +void cache_error_handler(void) +{ + rt_kprintf("cache exception happens, epc: 0x%08x\n", read_c0_epc()); + rt_hw_cpu_shutdown(); +} + +static void unhandled_exception_handle(pt_regs_t *regs) +{ + rt_kprintf("exception happens, epc: 0x%08x\n", regs->cp0_epc); +} + +void install_default_execpt_handle(void) +{ + rt_int32_t i; + + for (i=0; i<33; i++) + sys_exception_handlers[i] = (exception_func_t)unhandled_exception_handle; +} + +/*@}*/ + diff --git a/libcpu/mips/jz47xx/interrupt.c b/libcpu/mips/jz47xx/interrupt.c index 78ba87c2e9..7d531cbd71 100644 --- a/libcpu/mips/jz47xx/interrupt.c +++ b/libcpu/mips/jz47xx/interrupt.c @@ -1,116 +1,116 @@ -/*
- * File : interrupt.c
- * This file is part of RT-Thread RTOS
- * COPYRIGHT (C) 2006 - 2010, RT-Thread Development Team
- *
- * The license and distribution terms for this file may be
- * found in the file LICENSE in this distribution or at
- * http://www.rt-thread.org/license/LICENSE
- *
- * Change Logs:
- * Date Author Notes
- * 2010-07-09 Bernard first version
- */
-#include <rtthread.h>
-#include "jz47xx.h"
-
-#define JZ47XX_MAX_INTR 32
-
-extern rt_uint32_t rt_interrupt_nest;
-rt_uint32_t rt_interrupt_from_thread, rt_interrupt_to_thread;
-rt_uint32_t rt_thread_switch_interrupt_flag;
-
-static rt_isr_handler_t irq_handle_table[JZ47XX_MAX_INTR];
-
-/**
- * @addtogroup Jz47xx
- */
-/*@{*/
-
-void rt_hw_interrupt_handler(int vector)
-{
- rt_kprintf("Unhandled interrupt %d occured!!!\n", vector);
-}
-
-/**
- * This function will initialize hardware interrupt
- */
-void rt_hw_interrupt_init()
-{
- rt_int32_t index;
-
- for (index = 0; index < JZ47XX_MAX_INTR; index ++)
- {
- irq_handle_table[index] = (rt_isr_handler_t)rt_hw_interrupt_handler;
- }
-
- /* init interrupt nest, and context in thread sp */
- rt_interrupt_nest = 0;
- rt_interrupt_from_thread = 0;
- rt_interrupt_to_thread = 0;
- rt_thread_switch_interrupt_flag = 0;
-}
-
-/**
- * This function will mask a interrupt.
- * @param vector the interrupt number
- */
-void rt_hw_interrupt_mask(int vector)
-{
- /* mask interrupt */
- INTC_IMSR = (1 << vector);
-}
-
-/**
- * This function will un-mask a interrupt.
- * @param vector the interrupt number
- */
-void rt_hw_interrupt_umask(int vector)
-{
- INTC_IMCR = (1 << vector);
-}
-
-/**
- * This function will install a interrupt service routine to a interrupt.
- * @param vector the interrupt number
- * @param new_handler the interrupt service routine to be installed
- * @param old_handler the old interrupt service routine
- */
-void rt_hw_interrupt_install(int vector, rt_isr_handler_t new_handler, rt_isr_handler_t *old_handler)
-{
- if (vector >= 0 && vector < JZ47XX_MAX_INTR)
- {
- if (old_handler != RT_NULL)
- *old_handler = irq_handle_table[vector];
- if (new_handler != RT_NULL)
- irq_handle_table[vector] = (rt_isr_handler_t)new_handler;
- }
-}
-
-void rt_interrupt_dispatch(void *ptreg)
-{
- int i;
- rt_isr_handler_t irq_func;
- static rt_uint32_t pending = 0;
-
- /* the hardware interrupt */
- pending |= INTC_IPR;
- if (!pending) return;
-
- for (i = JZ47XX_MAX_INTR; i > 0; --i)
- {
- if ((pending & (1<<i)))
- {
- pending &= ~(1<<i);
- irq_func = irq_handle_table[i];
-
- /* do interrupt */
- (*irq_func)(i);
-
- /* ack interrupt */
- INTC_IPR = (1 << i);
- }
- }
-}
-
-/*@}*/
+/* + * File : interrupt.c + * This file is part of RT-Thread RTOS + * COPYRIGHT (C) 2006 - 2010, RT-Thread Development Team + * + * The license and distribution terms for this file may be + * found in the file LICENSE in this distribution or at + * http://www.rt-thread.org/license/LICENSE + * + * Change Logs: + * Date Author Notes + * 2010-07-09 Bernard first version + */ +#include <rtthread.h> +#include "jz47xx.h" + +#define JZ47XX_MAX_INTR 32 + +extern rt_uint32_t rt_interrupt_nest; +rt_uint32_t rt_interrupt_from_thread, rt_interrupt_to_thread; +rt_uint32_t rt_thread_switch_interrupt_flag; + +static rt_isr_handler_t irq_handle_table[JZ47XX_MAX_INTR]; + +/** + * @addtogroup Jz47xx + */ +/*@{*/ + +void rt_hw_interrupt_handler(int vector) +{ + rt_kprintf("Unhandled interrupt %d occured!!!\n", vector); +} + +/** + * This function will initialize hardware interrupt + */ +void rt_hw_interrupt_init() +{ + rt_int32_t index; + + for (index = 0; index < JZ47XX_MAX_INTR; index ++) + { + irq_handle_table[index] = (rt_isr_handler_t)rt_hw_interrupt_handler; + } + + /* init interrupt nest, and context in thread sp */ + rt_interrupt_nest = 0; + rt_interrupt_from_thread = 0; + rt_interrupt_to_thread = 0; + rt_thread_switch_interrupt_flag = 0; +} + +/** + * This function will mask a interrupt. + * @param vector the interrupt number + */ +void rt_hw_interrupt_mask(int vector) +{ + /* mask interrupt */ + INTC_IMSR = (1 << vector); +} + +/** + * This function will un-mask a interrupt. + * @param vector the interrupt number + */ +void rt_hw_interrupt_umask(int vector) +{ + INTC_IMCR = (1 << vector); +} + +/** + * This function will install a interrupt service routine to a interrupt. + * @param vector the interrupt number + * @param new_handler the interrupt service routine to be installed + * @param old_handler the old interrupt service routine + */ +void rt_hw_interrupt_install(int vector, rt_isr_handler_t new_handler, rt_isr_handler_t *old_handler) +{ + if (vector >= 0 && vector < JZ47XX_MAX_INTR) + { + if (old_handler != RT_NULL) + *old_handler = irq_handle_table[vector]; + if (new_handler != RT_NULL) + irq_handle_table[vector] = (rt_isr_handler_t)new_handler; + } +} + +void rt_interrupt_dispatch(void *ptreg) +{ + int i; + rt_isr_handler_t irq_func; + static rt_uint32_t pending = 0; + + /* the hardware interrupt */ + pending |= INTC_IPR; + if (!pending) return; + + for (i = JZ47XX_MAX_INTR; i > 0; --i) + { + if ((pending & (1<<i))) + { + pending &= ~(1<<i); + irq_func = irq_handle_table[i]; + + /* do interrupt */ + (*irq_func)(i); + + /* ack interrupt */ + INTC_IPR = (1 << i); + } + } +} + +/*@}*/ diff --git a/libcpu/mips/jz47xx/jz4740.h b/libcpu/mips/jz47xx/jz4740.h index 42137a5dad..a6fdd34c83 100644 --- a/libcpu/mips/jz47xx/jz4740.h +++ b/libcpu/mips/jz47xx/jz4740.h @@ -1,55 +1,55 @@ -#ifndef __JZ4740_H__
-#define __JZ4740_H__
-
-#include "jz47xx.h"
-
-#define WDT_BASE 0xB0002000
-
-/* Watchdog */
-#define WDT_TDR __REG16(WDT_BASE + 0x00) /* Watchdog Timer Data Register */
-#define WDT_TCER __REG8(WDT_BASE + 0x04) /* Watchdog Counter Enable Register */
-#define WDT_TCNT __REG16(WDT_BASE + 0x08) /* Watchdog Timer Counter Register */
-#define WDT_TCSR __REG16(WDT_BASE + 0x0C) /* Watchdog Timer Control Register */
-
-/* Clock Gate Register Definitions */
-#define CPM_CLKGR_UART1 (1 << 15)
-#define CPM_CLKGR_UHC (1 << 14)
-#define CPM_CLKGR_IPU (1 << 13)
-#define CPM_CLKGR_DMAC (1 << 12)
-#define CPM_CLKGR_UDC (1 << 11)
-#define CPM_CLKGR_LCD (1 << 10)
-#define CPM_CLKGR_CIM (1 << 9)
-#define CPM_CLKGR_SADC (1 << 8)
-#define CPM_CLKGR_MSC (1 << 7)
-#define CPM_CLKGR_AIC1 (1 << 6)
-#define CPM_CLKGR_AIC2 (1 << 5)
-#define CPM_CLKGR_SSI (1 << 4)
-#define CPM_CLKGR_I2C (1 << 3)
-#define CPM_CLKGR_RTC (1 << 2)
-#define CPM_CLKGR_TCU (1 << 1)
-#define CPM_CLKGR_UART0 (1 << 0)
-
-/* Interrupt Definitions */
-#define IRQ_I2C 1
-#define IRQ_UHC 3
-#define IRQ_UART0 9
-#define IRQ_SADC 12
-#define IRQ_MSC 14
-#define IRQ_RTC 15
-#define IRQ_SSI 16
-#define IRQ_CIM 17
-#define IRQ_AIC 18
-#define IRQ_ETH 19
-#define IRQ_DMAC 20
-#define IRQ_TCU2 21
-#define IRQ_TCU1 22
-#define IRQ_TCU0 23
-#define IRQ_UDC 24
-#define IRQ_GPIO3 25
-#define IRQ_GPIO2 26
-#define IRQ_GPIO1 27
-#define IRQ_GPIO0 28
-#define IRQ_IPU 29
-#define IRQ_LCD 30
-
-#endif
+#ifndef __JZ4740_H__ +#define __JZ4740_H__ + +#include "jz47xx.h" + +#define WDT_BASE 0xB0002000 + +/* Watchdog */ +#define WDT_TDR __REG16(WDT_BASE + 0x00) /* Watchdog Timer Data Register */ +#define WDT_TCER __REG8(WDT_BASE + 0x04) /* Watchdog Counter Enable Register */ +#define WDT_TCNT __REG16(WDT_BASE + 0x08) /* Watchdog Timer Counter Register */ +#define WDT_TCSR __REG16(WDT_BASE + 0x0C) /* Watchdog Timer Control Register */ + +/* Clock Gate Register Definitions */ +#define CPM_CLKGR_UART1 (1 << 15) +#define CPM_CLKGR_UHC (1 << 14) +#define CPM_CLKGR_IPU (1 << 13) +#define CPM_CLKGR_DMAC (1 << 12) +#define CPM_CLKGR_UDC (1 << 11) +#define CPM_CLKGR_LCD (1 << 10) +#define CPM_CLKGR_CIM (1 << 9) +#define CPM_CLKGR_SADC (1 << 8) +#define CPM_CLKGR_MSC (1 << 7) +#define CPM_CLKGR_AIC1 (1 << 6) +#define CPM_CLKGR_AIC2 (1 << 5) +#define CPM_CLKGR_SSI (1 << 4) +#define CPM_CLKGR_I2C (1 << 3) +#define CPM_CLKGR_RTC (1 << 2) +#define CPM_CLKGR_TCU (1 << 1) +#define CPM_CLKGR_UART0 (1 << 0) + +/* Interrupt Definitions */ +#define IRQ_I2C 1 +#define IRQ_UHC 3 +#define IRQ_UART0 9 +#define IRQ_SADC 12 +#define IRQ_MSC 14 +#define IRQ_RTC 15 +#define IRQ_SSI 16 +#define IRQ_CIM 17 +#define IRQ_AIC 18 +#define IRQ_ETH 19 +#define IRQ_DMAC 20 +#define IRQ_TCU2 21 +#define IRQ_TCU1 22 +#define IRQ_TCU0 23 +#define IRQ_UDC 24 +#define IRQ_GPIO3 25 +#define IRQ_GPIO2 26 +#define IRQ_GPIO1 27 +#define IRQ_GPIO0 28 +#define IRQ_IPU 29 +#define IRQ_LCD 30 + +#endif diff --git a/libcpu/mips/jz47xx/jz4755.h b/libcpu/mips/jz47xx/jz4755.h index c91fb3b8b9..847f657f4e 100644 --- a/libcpu/mips/jz47xx/jz4755.h +++ b/libcpu/mips/jz47xx/jz4755.h @@ -1,83 +1,83 @@ -#ifndef __JZ4755_H__
-#define __JZ4755_H__
-
-#include "jz47xx.h"
-
-#define WDT_BASE 0xB0002000
-#define OST_BASE 0xB00020e0
-
-/* Watchdog */
-#define WDT_TDR __REG16(WDT_BASE + 0x00) /* Watchdog Timer Data Register */
-#define WDT_TCER __REG8(WDT_BASE + 0x04) /* Watchdog Counter Enable Register */
-#define WDT_TCNT __REG16(WDT_BASE + 0x08) /* Watchdog Timer Counter Register */
-#define WDT_TCSR __REG16(WDT_BASE + 0x0C) /* Watchdog Timer Control Register */
-
-/* OS Timer */
-#define OST_DR __REG32(OST_BASE + 0x00) /* OS Timer Data Register */
-#define OST_CNT __REG32(OST_BASE + 0x08) /* OS Timer Counter Register */
-#define OST_CSR __REG16(OST_BASE + 0x0C) /* OS Timer Control Register */
-
-/* OST Register Definitions */
-#define OST_TCSR_EXT_EN ( 0x1 << 2)
-#define OST_TCSR_RTC_EN ( 0x1 << 1)
-#define OST_TCSR_PCLK_EN ( 0x1 << 0)
-
-/* Clock Gate Register Definitions */
-#define CPM_CLKGR_AUX_CPU ( 1 << 24 )
-#define CPM_CLKGR_AHB1 ( 1 << 23 )
-#define CPM_CLKGR_IDCT ( 1 << 22 )
-#define CPM_CLKGR_DB ( 1 << 21 )
-#define CPM_CLKGR_ME ( 1 << 20 )
-#define CPM_CLKGR_MC ( 1 << 19 )
-#define CPM_CLKGR_TVE ( 1 << 18 )
-#define CPM_CLKGR_TSSI ( 1 << 17 )
-#define CPM_CLKGR_MSC1 ( 1 << 16 )
-#define CPM_CLKGR_UART2 ( 1 << 15 )
-#define CPM_CLKGR_UART1 ( 1 << 14 )
-#define CPM_CLKGR_IPU ( 1 << 13 )
-#define CPM_CLKGR_DMAC ( 1 << 12 )
-#define CPM_CLKGR_BCH ( 1 << 11 )
-#define CPM_CLKGR_UDC ( 1 << 10 )
-#define CPM_CLKGR_LCD ( 1 << 9 )
-#define CPM_CLKGR_CIM ( 1 << 8 )
-#define CPM_CLKGR_SADC ( 1 << 7 )
-#define CPM_CLKGR_MSC0 ( 1 << 6 )
-#define CPM_CLKGR_AIC ( 1 << 5 )
-#define CPM_CLKGR_SSI1 ( 1 << 4 )
-#define CPM_CLKGR_I2C ( 1 << 3 )
-#define CPM_CLKGR_RTC ( 1 << 2 )
-#define CPM_CLKGR_TCU ( 1 << 1 )
-#define CPM_CLKGR_UART0 ( 1 << 0 )
-
-/* Interrupt Definitions */
-#define IRQ_ETH 0
-#define IRQ_SFT 4
-#define IRQ_I2C 5
-#define IRQ_RTC 6
-#define IRQ_UART2 7
-#define IRQ_UART1 8
-#define IRQ_UART0 9
-#define IRQ_AIC 10
-#define IRQ_GPIO5 11
-#define IRQ_GPIO4 12
-#define IRQ_GPIO3 13
-#define IRQ_GPIO2 14
-#define IRQ_GPIO1 15
-#define IRQ_GPIO0 16
-#define IRQ_BCH 17
-#define IRQ_SADC 18
-#define IRQ_CIM 19
-#define IRQ_TSSI 20
-#define IRQ_TCU2 21
-#define IRQ_TCU1 22
-#define IRQ_TCU0 23
-#define IRQ_MSC1 24
-#define IRQ_MSC0 25
-#define IRQ_SSI 26
-#define IRQ_UDC 27
-#define IRQ_DMA1 28 /* Used for DMA channel 4-7 */
-#define IRQ_DMA0 29 /* Used for DMA channel 0-3 */
-#define IRQ_IPU 30
-#define IRQ_LCD 31
-
-#endif
+#ifndef __JZ4755_H__ +#define __JZ4755_H__ + +#include "jz47xx.h" + +#define WDT_BASE 0xB0002000 +#define OST_BASE 0xB00020e0 + +/* Watchdog */ +#define WDT_TDR __REG16(WDT_BASE + 0x00) /* Watchdog Timer Data Register */ +#define WDT_TCER __REG8(WDT_BASE + 0x04) /* Watchdog Counter Enable Register */ +#define WDT_TCNT __REG16(WDT_BASE + 0x08) /* Watchdog Timer Counter Register */ +#define WDT_TCSR __REG16(WDT_BASE + 0x0C) /* Watchdog Timer Control Register */ + +/* OS Timer */ +#define OST_DR __REG32(OST_BASE + 0x00) /* OS Timer Data Register */ +#define OST_CNT __REG32(OST_BASE + 0x08) /* OS Timer Counter Register */ +#define OST_CSR __REG16(OST_BASE + 0x0C) /* OS Timer Control Register */ + +/* OST Register Definitions */ +#define OST_TCSR_EXT_EN ( 0x1 << 2) +#define OST_TCSR_RTC_EN ( 0x1 << 1) +#define OST_TCSR_PCLK_EN ( 0x1 << 0) + +/* Clock Gate Register Definitions */ +#define CPM_CLKGR_AUX_CPU ( 1 << 24 ) +#define CPM_CLKGR_AHB1 ( 1 << 23 ) +#define CPM_CLKGR_IDCT ( 1 << 22 ) +#define CPM_CLKGR_DB ( 1 << 21 ) +#define CPM_CLKGR_ME ( 1 << 20 ) +#define CPM_CLKGR_MC ( 1 << 19 ) +#define CPM_CLKGR_TVE ( 1 << 18 ) +#define CPM_CLKGR_TSSI ( 1 << 17 ) +#define CPM_CLKGR_MSC1 ( 1 << 16 ) +#define CPM_CLKGR_UART2 ( 1 << 15 ) +#define CPM_CLKGR_UART1 ( 1 << 14 ) +#define CPM_CLKGR_IPU ( 1 << 13 ) +#define CPM_CLKGR_DMAC ( 1 << 12 ) +#define CPM_CLKGR_BCH ( 1 << 11 ) +#define CPM_CLKGR_UDC ( 1 << 10 ) +#define CPM_CLKGR_LCD ( 1 << 9 ) +#define CPM_CLKGR_CIM ( 1 << 8 ) +#define CPM_CLKGR_SADC ( 1 << 7 ) +#define CPM_CLKGR_MSC0 ( 1 << 6 ) +#define CPM_CLKGR_AIC ( 1 << 5 ) +#define CPM_CLKGR_SSI1 ( 1 << 4 ) +#define CPM_CLKGR_I2C ( 1 << 3 ) +#define CPM_CLKGR_RTC ( 1 << 2 ) +#define CPM_CLKGR_TCU ( 1 << 1 ) +#define CPM_CLKGR_UART0 ( 1 << 0 ) + +/* Interrupt Definitions */ +#define IRQ_ETH 0 +#define IRQ_SFT 4 +#define IRQ_I2C 5 +#define IRQ_RTC 6 +#define IRQ_UART2 7 +#define IRQ_UART1 8 +#define IRQ_UART0 9 +#define IRQ_AIC 10 +#define IRQ_GPIO5 11 +#define IRQ_GPIO4 12 +#define IRQ_GPIO3 13 +#define IRQ_GPIO2 14 +#define IRQ_GPIO1 15 +#define IRQ_GPIO0 16 +#define IRQ_BCH 17 +#define IRQ_SADC 18 +#define IRQ_CIM 19 +#define IRQ_TSSI 20 +#define IRQ_TCU2 21 +#define IRQ_TCU1 22 +#define IRQ_TCU0 23 +#define IRQ_MSC1 24 +#define IRQ_MSC0 25 +#define IRQ_SSI 26 +#define IRQ_UDC 27 +#define IRQ_DMA1 28 /* Used for DMA channel 4-7 */ +#define IRQ_DMA0 29 /* Used for DMA channel 0-3 */ +#define IRQ_IPU 30 +#define IRQ_LCD 31 + +#endif diff --git a/libcpu/mips/jz47xx/jz47xx.h b/libcpu/mips/jz47xx/jz47xx.h index 8f06bd369e..3d1b7cee1f 100644 --- a/libcpu/mips/jz47xx/jz47xx.h +++ b/libcpu/mips/jz47xx/jz47xx.h @@ -1,263 +1,263 @@ -#ifndef __JZ47XX_H__
-#define __JZ47XX_H__
-
-#include "../common/mipsregs.h"
-
-#define __REG8(addr) *((volatile unsigned char *)(addr))
-#define __REG16(addr) *((volatile unsigned short *)(addr))
-#define __REG32(addr) *((volatile unsigned int *)(addr))
-
-#define HARB_BASE 0xB3000000
-#define EMC_BASE 0xB3010000
-#define DMAC_BASE 0xB3020000
-#define UHC_BASE 0xB3030000
-#define UDC_BASE 0xB3040000
-#define LCD_BASE 0xB3050000
-#define CIM_BASE 0xB3060000
-#define ETH_BASE 0xB3100000
-#define NBM_BASE 0xB3F00000
-
-#define CPM_BASE 0xB0000000
-#define INTC_BASE 0xB0001000
-#define TCU_BASE 0xB0002000
-#define RTC_BASE 0xB0003000
-#define GPIO_BASE 0xB0010000
-#define AIC_BASE 0xB0020000
-#define MSC_BASE 0xB0021000
-#define UART0_BASE 0xB0030000
-#define UART1_BASE 0xB0031000
-#define UART2_BASE 0xB0032000
-#define UART3_BASE 0xB0033000
-#define FIR_BASE 0xB0040000
-#define SCC_BASE 0xB0041000
-#define SCC0_BASE 0xB0041000
-#define I2C_BASE 0xB0042000
-#define SSI_BASE 0xB0043000
-#define SCC1_BASE 0xB0044000
-#define PWM0_BASE 0xB0050000
-#define PWM1_BASE 0xB0051000
-#define DES_BASE 0xB0060000
-#define UPRT_BASE 0xB0061000
-#define KBC_BASE 0xB0062000
-
-/* CPM Register */
-#define CPM_CPCCR __REG32(CPM_BASE + 0x00) /* Clock Control Register */
-#define CPM_LCR __REG32(CPM_BASE + 0x04) /* Low Power Control Register */
-#define CPM_RSR __REG32(CPM_BASE + 0x08) /* Reset Status Register */
-#define CPM_CPPCR __REG32(CPM_BASE + 0x10) /* PLL Control Register */
-#define CPM_CPPSR __REG32(CPM_BASE + 0x14) /* PLL Switch and Status Register */
-#define CPM_CLKGR __REG32(CPM_BASE + 0x20) /* Clock Gate Register */
-#define CPM_OPCR __REG32(CPM_BASE + 0x24) /* Osillator and Power Control Register */
-#define CPM_I2SCDR __REG32(CPM_BASE + 0x60) /* I2S Device Clock Divider Register */
-#define CPM_LPCDR __REG32(CPM_BASE + 0x64) /* LCD Pixel Clock Divider Register */
-#define CPM_MSCCDR __REG32(CPM_BASE + 0x68) /* MSC Clock Divider Register */
-#define CPM_SSICDR __REG32(CPM_BASE + 0x74) /* SSI Clock Divider Register */
-#define CPM_CIMCDR __REG32(CPM_BASE + 0x7C) /* CIM MCLK Clock Divider Register */
-
-/* Interrupt Controller Regester */
-#define INTC_ISR __REG32(INTC_BASE + 0x00)
-#define INTC_IMR __REG32(INTC_BASE + 0x04)
-#define INTC_IMSR __REG32(INTC_BASE + 0x08)
-#define INTC_IMCR __REG32(INTC_BASE + 0x0c)
-#define INTC_IPR __REG32(INTC_BASE + 0x10)
-
-/* TCU Register */
-#define TCU_TSTR __REG32(TCU_BASE + 0xF0)
-#define TCU_TSTSR __REG32(TCU_BASE + 0xF4)
-#define TCU_TSTCR __REG32(TCU_BASE + 0xF8)
-#define TCU_TSR __REG32(TCU_BASE + 0x1C)
-#define TCU_TSSR __REG32(TCU_BASE + 0x2C)
-#define TCU_TSCR __REG32(TCU_BASE + 0x3C)
-#define TCU_TER __REG32(TCU_BASE + 0x10)
-#define TCU_TESR __REG32(TCU_BASE + 0x14)
-#define TCU_TECR __REG32(TCU_BASE + 0x18)
-#define TCU_TFR __REG32(TCU_BASE + 0x20)
-#define TCU_TFSR __REG32(TCU_BASE + 0x24)
-#define TCU_TFCR __REG32(TCU_BASE + 0x28)
-#define TCU_TMR __REG32(TCU_BASE + 0x30)
-#define TCU_TMSR __REG32(TCU_BASE + 0x34)
-#define TCU_TMCR __REG32(TCU_BASE + 0x38)
-#define TCU_TDFR0_OFFSET 0x40
-#define TCU_TDFR(x) __REG16(TCU_BASE + (x) * 0x10 + TCU_TDFR0_OFFSET)
-#define TCU_TDHR0_OFFSET 0x44
-#define TCU_TDHR(x) __REG16(TCU_BASE + (x) * 0x10 + TCU_TDHR0_OFFSET)
-#define TCU_TCNT0_OFFSET 0x48
-#define TCU_TCNT(x) __REG16(TCU_BASE + (x) * 0x10 + TCU_TCNT0_OFFSET)
-#define TCU_TCSR0_OFFSET 0x4C
-#define TCU_TCSR(x) __REG16(TCU_BASE + (x) * 0x10 + TCU_TCSR0_OFFSET)
-
-/* TCU Register Definitions */
-#define TCU_TCSR_PWM_SD (1 << 9)
-#define TCU_TCSR_PWM_INITL_HIGH (1 << 8)
-#define TCU_TCSR_PWM_EN (1 << 7)
-#define TCU_TCSR_PRESCALE_BIT 3
-#define TCU_TCSR_PRESCALE_MASK (0x7 << TCU_TCSR_PRESCALE_BIT)
-#define TCU_TCSR_PRESCALE1 (0x0 << TCU_TCSR_PRESCALE_BIT)
-#define TCU_TCSR_PRESCALE4 (0x1 << TCU_TCSR_PRESCALE_BIT)
-#define TCU_TCSR_PRESCALE16 (0x2 << TCU_TCSR_PRESCALE_BIT)
-#define TCU_TCSR_PRESCALE64 (0x3 << TCU_TCSR_PRESCALE_BIT)
-#define TCU_TCSR_PRESCALE256 (0x4 << TCU_TCSR_PRESCALE_BIT)
-#define TCU_TCSR_PRESCALE1024 (0x5 << TCU_TCSR_PRESCALE_BIT)
-#define TCU_TCSR_EXT_EN (1 << 2)
-#define TCU_TCSR_RTC_EN (1 << 1)
-#define TCU_TCSR_PCK_EN (1 << 0)
-
-#define TCU_TER_OSTEN (1 << 15)
-#define TCU_TER_TCEN5 (1 << 5)
-#define TCU_TER_TCEN4 (1 << 4)
-#define TCU_TER_TCEN3 (1 << 3)
-#define TCU_TER_TCEN2 (1 << 2)
-#define TCU_TER_TCEN1 (1 << 1)
-#define TCU_TER_TCEN0 (1 << 0)
-
-#define TCU_TESR_OSTST (1 << 15)
-#define TCU_TESR_TCST5 (1 << 5)
-#define TCU_TESR_TCST4 (1 << 4)
-#define TCU_TESR_TCST3 (1 << 3)
-#define TCU_TESR_TCST2 (1 << 2)
-#define TCU_TESR_TCST1 (1 << 1)
-#define TCU_TESR_TCST0 (1 << 0)
-
-#define TCU_TECR_OSTCL (1 << 15)
-#define TCU_TECR_TCCL5 (1 << 5)
-#define TCU_TECR_TCCL4 (1 << 4)
-#define TCU_TECR_TCCL3 (1 << 3)
-#define TCU_TECR_TCCL2 (1 << 2)
-#define TCU_TECR_TCCL1 (1 << 1)
-#define TCU_TECR_TCCL0 (1 << 0)
-
-#define TCU_TFR_HFLAG5 (1 << 21)
-#define TCU_TFR_HFLAG4 (1 << 20)
-#define TCU_TFR_HFLAG3 (1 << 19)
-#define TCU_TFR_HFLAG2 (1 << 18)
-#define TCU_TFR_HFLAG1 (1 << 17)
-#define TCU_TFR_HFLAG0 (1 << 16)
-#define TCU_TFR_FFLAG5 (1 << 5)
-#define TCU_TFR_FFLAG4 (1 << 4)
-#define TCU_TFR_FFLAG3 (1 << 3)
-#define TCU_TFR_FFLAG2 (1 << 2)
-#define TCU_TFR_FFLAG1 (1 << 1)
-#define TCU_TFR_FFLAG0 (1 << 0)
-
-#define TCU_TFSR_HFLAG5 (1 << 21)
-#define TCU_TFSR_HFLAG4 (1 << 20)
-#define TCU_TFSR_HFLAG3 (1 << 19)
-#define TCU_TFSR_HFLAG2 (1 << 18)
-#define TCU_TFSR_HFLAG1 (1 << 17)
-#define TCU_TFSR_HFLAG0 (1 << 16)
-#define TCU_TFSR_OSTFLAG (1 << 15)
-#define TCU_TFSR_FFLAG5 (1 << 5)
-#define TCU_TFSR_FFLAG4 (1 << 4)
-#define TCU_TFSR_FFLAG3 (1 << 3)
-#define TCU_TFSR_FFLAG2 (1 << 2)
-#define TCU_TFSR_FFLAG1 (1 << 1)
-#define TCU_TFSR_FFLAG0 (1 << 0)
-
-#define TCU_TFCR_HFLAG5 (1 << 21)
-#define TCU_TFCR_HFLAG4 (1 << 20)
-#define TCU_TFCR_HFLAG3 (1 << 19)
-#define TCU_TFCR_HFLAG2 (1 << 18)
-#define TCU_TFCR_HFLAG1 (1 << 17)
-#define TCU_TFCR_HFLAG0 (1 << 16)
-#define TCU_TFCR_OSTFLAG (1 << 15)
-#define TCU_TFCR_FFLAG5 (1 << 5)
-#define TCU_TFCR_FFLAG4 (1 << 4)
-#define TCU_TFCR_FFLAG3 (1 << 3)
-#define TCU_TFCR_FFLAG2 (1 << 2)
-#define TCU_TFCR_FFLAG1 (1 << 1)
-#define TCU_TFCR_FFLAG0 (1 << 0)
-
-#define TCU_TMR_HMASK5 (1 << 21)
-#define TCU_TMR_HMASK4 (1 << 20)
-#define TCU_TMR_HMASK3 (1 << 19)
-#define TCU_TMR_HMASK2 (1 << 18)
-#define TCU_TMR_HMASK1 (1 << 17)
-#define TCU_TMR_HMASK0 (1 << 16)
-#define TCU_TMR_OSTMASK (1 << 15)
-#define TCU_TMR_FMASK5 (1 << 5)
-#define TCU_TMR_FMASK4 (1 << 4)
-#define TCU_TMR_FMASK3 (1 << 3)
-#define TCU_TMR_FMASK2 (1 << 2)
-#define TCU_TMR_FMASK1 (1 << 1)
-#define TCU_TMR_FMASK0 (1 << 0)
-
-#define TCU_TMSR_HMST5 (1 << 21)
-#define TCU_TMSR_HMST4 (1 << 20)
-#define TCU_TMSR_HMST3 (1 << 19)
-#define TCU_TMSR_HMST2 (1 << 18)
-#define TCU_TMSR_HMST1 (1 << 17)
-#define TCU_TMSR_HMST0 (1 << 16)
-#define TCU_TMSR_OSTMST (1 << 15)
-#define TCU_TMSR_FMST5 (1 << 5)
-#define TCU_TMSR_FMST4 (1 << 4)
-#define TCU_TMSR_FMST3 (1 << 3)
-#define TCU_TMSR_FMST2 (1 << 2)
-#define TCU_TMSR_FMST1 (1 << 1)
-#define TCU_TMSR_FMST0 (1 << 0)
-
-#define TCU_TMCR_HMCL5 (1 << 21)
-#define TCU_TMCR_HMCL4 (1 << 20)
-#define TCU_TMCR_HMCL3 (1 << 19)
-#define TCU_TMCR_HMCL2 (1 << 18)
-#define TCU_TMCR_HMCL1 (1 << 17)
-#define TCU_TMCR_HMCL0 (1 << 16)
-#define TCU_TMCR_OSTMCL (1 << 15)
-#define TCU_TMCR_FMCL5 (1 << 5)
-#define TCU_TMCR_FMCL4 (1 << 4)
-#define TCU_TMCR_FMCL3 (1 << 3)
-#define TCU_TMCR_FMCL2 (1 << 2)
-#define TCU_TMCR_FMCL1 (1 << 1)
-#define TCU_TMCR_FMCL0 (1 << 0)
-
-#define TCU_TSR_WDTS (1 << 16)
-#define TCU_TSR_STOP5 (1 << 5)
-#define TCU_TSR_STOP4 (1 << 4)
-#define TCU_TSR_STOP3 (1 << 3)
-#define TCU_TSR_STOP2 (1 << 2)
-#define TCU_TSR_STOP1 (1 << 1)
-#define TCU_TSR_STOP0 (1 << 0)
-
-#define TCU_TSSR_WDTSS (1 << 16)
-#define TCU_TSSR_STPS5 (1 << 5)
-#define TCU_TSSR_STPS4 (1 << 4)
-#define TCU_TSSR_STPS3 (1 << 3)
-#define TCU_TSSR_STPS2 (1 << 2)
-#define TCU_TSSR_STPS1 (1 << 1)
-#define TCU_TSSR_STPS0 (1 << 0)
-
-#define TCU_TSSR_WDTSC (1 << 16)
-#define TCU_TSSR_STPC5 (1 << 5)
-#define TCU_TSSR_STPC4 (1 << 4)
-#define TCU_TSSR_STPC3 (1 << 3)
-#define TCU_TSSR_STPC2 (1 << 2)
-#define TCU_TSSR_STPC1 (1 << 1)
-#define TCU_TSSR_STPC0 (1 << 0)
-
-#define OST_TCSR_CNT_MD ( 1 << 15 )
-#define OST_TCSR_PWM_SHUT_ABRUPT ( 1 << 9 )
-#define OST_TCSR_PRESCALE1 ( 0x0 << 3)
-#define OST_TCSR_PRESCALE4 ( 0x1 << 3)
-#define OST_TCSR_PRESCALE16 ( 0x2 << 3)
-#define OST_TCSR_PRESCALE64 ( 0x3 << 3)
-#define OST_TCSR_PRESCALE256 ( 0x4 << 3)
-#define OST_TCSR_PRESCALE1024 ( 0x5 << 3)
-
-/* Uart Register */
-#define UART_RDR(base) __REG8((base) + 0x00) /* R 8b H'xx */
-#define UART_TDR(base) __REG8((base) + 0x00) /* W 8b H'xx */
-#define UART_DLLR(base) __REG8((base) + 0x00) /* RW 8b H'00 */
-#define UART_DLHR(base) __REG8((base) + 0x04) /* RW 8b H'00 */
-#define UART_IER(base) __REG8((base) + 0x04) /* RW 8b H'00 */
-#define UART_ISR(base) __REG8((base) + 0x08) /* R 8b H'01 */
-#define UART_FCR(base) __REG8((base) + 0x08) /* W 8b H'00 */
-#define UART_LCR(base) __REG8((base) + 0x0C) /* RW 8b H'00 */
-#define UART_MCR(base) __REG8((base) + 0x10) /* RW 8b H'00 */
-#define UART_LSR(base) __REG8((base) + 0x14) /* R 8b H'00 */
-#define UART_MSR(base) __REG8((base) + 0x18) /* R 8b H'00 */
-#define UART_SPR(base) __REG8((base) + 0x1C) /* RW 8b H'00 */
-#define UART_MCR(base) __REG8((base) + 0x10) /* RW 8b H'00 */
-#define UART_SIRCR(base) __REG8((base) + 0x20) /* RW 8b H'00 */
-
-#define SYSTEM_STACK 0x80003fe8 /* the kernel system stack address */
-
-#endif
+#ifndef __JZ47XX_H__ +#define __JZ47XX_H__ + +#include "../common/mipsregs.h" + +#define __REG8(addr) *((volatile unsigned char *)(addr)) +#define __REG16(addr) *((volatile unsigned short *)(addr)) +#define __REG32(addr) *((volatile unsigned int *)(addr)) + +#define HARB_BASE 0xB3000000 +#define EMC_BASE 0xB3010000 +#define DMAC_BASE 0xB3020000 +#define UHC_BASE 0xB3030000 +#define UDC_BASE 0xB3040000 +#define LCD_BASE 0xB3050000 +#define CIM_BASE 0xB3060000 +#define ETH_BASE 0xB3100000 +#define NBM_BASE 0xB3F00000 + +#define CPM_BASE 0xB0000000 +#define INTC_BASE 0xB0001000 +#define TCU_BASE 0xB0002000 +#define RTC_BASE 0xB0003000 +#define GPIO_BASE 0xB0010000 +#define AIC_BASE 0xB0020000 +#define MSC_BASE 0xB0021000 +#define UART0_BASE 0xB0030000 +#define UART1_BASE 0xB0031000 +#define UART2_BASE 0xB0032000 +#define UART3_BASE 0xB0033000 +#define FIR_BASE 0xB0040000 +#define SCC_BASE 0xB0041000 +#define SCC0_BASE 0xB0041000 +#define I2C_BASE 0xB0042000 +#define SSI_BASE 0xB0043000 +#define SCC1_BASE 0xB0044000 +#define PWM0_BASE 0xB0050000 +#define PWM1_BASE 0xB0051000 +#define DES_BASE 0xB0060000 +#define UPRT_BASE 0xB0061000 +#define KBC_BASE 0xB0062000 + +/* CPM Register */ +#define CPM_CPCCR __REG32(CPM_BASE + 0x00) /* Clock Control Register */ +#define CPM_LCR __REG32(CPM_BASE + 0x04) /* Low Power Control Register */ +#define CPM_RSR __REG32(CPM_BASE + 0x08) /* Reset Status Register */ +#define CPM_CPPCR __REG32(CPM_BASE + 0x10) /* PLL Control Register */ +#define CPM_CPPSR __REG32(CPM_BASE + 0x14) /* PLL Switch and Status Register */ +#define CPM_CLKGR __REG32(CPM_BASE + 0x20) /* Clock Gate Register */ +#define CPM_OPCR __REG32(CPM_BASE + 0x24) /* Osillator and Power Control Register */ +#define CPM_I2SCDR __REG32(CPM_BASE + 0x60) /* I2S Device Clock Divider Register */ +#define CPM_LPCDR __REG32(CPM_BASE + 0x64) /* LCD Pixel Clock Divider Register */ +#define CPM_MSCCDR __REG32(CPM_BASE + 0x68) /* MSC Clock Divider Register */ +#define CPM_SSICDR __REG32(CPM_BASE + 0x74) /* SSI Clock Divider Register */ +#define CPM_CIMCDR __REG32(CPM_BASE + 0x7C) /* CIM MCLK Clock Divider Register */ + +/* Interrupt Controller Regester */ +#define INTC_ISR __REG32(INTC_BASE + 0x00) +#define INTC_IMR __REG32(INTC_BASE + 0x04) +#define INTC_IMSR __REG32(INTC_BASE + 0x08) +#define INTC_IMCR __REG32(INTC_BASE + 0x0c) +#define INTC_IPR __REG32(INTC_BASE + 0x10) + +/* TCU Register */ +#define TCU_TSTR __REG32(TCU_BASE + 0xF0) +#define TCU_TSTSR __REG32(TCU_BASE + 0xF4) +#define TCU_TSTCR __REG32(TCU_BASE + 0xF8) +#define TCU_TSR __REG32(TCU_BASE + 0x1C) +#define TCU_TSSR __REG32(TCU_BASE + 0x2C) +#define TCU_TSCR __REG32(TCU_BASE + 0x3C) +#define TCU_TER __REG32(TCU_BASE + 0x10) +#define TCU_TESR __REG32(TCU_BASE + 0x14) +#define TCU_TECR __REG32(TCU_BASE + 0x18) +#define TCU_TFR __REG32(TCU_BASE + 0x20) +#define TCU_TFSR __REG32(TCU_BASE + 0x24) +#define TCU_TFCR __REG32(TCU_BASE + 0x28) +#define TCU_TMR __REG32(TCU_BASE + 0x30) +#define TCU_TMSR __REG32(TCU_BASE + 0x34) +#define TCU_TMCR __REG32(TCU_BASE + 0x38) +#define TCU_TDFR0_OFFSET 0x40 +#define TCU_TDFR(x) __REG16(TCU_BASE + (x) * 0x10 + TCU_TDFR0_OFFSET) +#define TCU_TDHR0_OFFSET 0x44 +#define TCU_TDHR(x) __REG16(TCU_BASE + (x) * 0x10 + TCU_TDHR0_OFFSET) +#define TCU_TCNT0_OFFSET 0x48 +#define TCU_TCNT(x) __REG16(TCU_BASE + (x) * 0x10 + TCU_TCNT0_OFFSET) +#define TCU_TCSR0_OFFSET 0x4C +#define TCU_TCSR(x) __REG16(TCU_BASE + (x) * 0x10 + TCU_TCSR0_OFFSET) + +/* TCU Register Definitions */ +#define TCU_TCSR_PWM_SD (1 << 9) +#define TCU_TCSR_PWM_INITL_HIGH (1 << 8) +#define TCU_TCSR_PWM_EN (1 << 7) +#define TCU_TCSR_PRESCALE_BIT 3 +#define TCU_TCSR_PRESCALE_MASK (0x7 << TCU_TCSR_PRESCALE_BIT) +#define TCU_TCSR_PRESCALE1 (0x0 << TCU_TCSR_PRESCALE_BIT) +#define TCU_TCSR_PRESCALE4 (0x1 << TCU_TCSR_PRESCALE_BIT) +#define TCU_TCSR_PRESCALE16 (0x2 << TCU_TCSR_PRESCALE_BIT) +#define TCU_TCSR_PRESCALE64 (0x3 << TCU_TCSR_PRESCALE_BIT) +#define TCU_TCSR_PRESCALE256 (0x4 << TCU_TCSR_PRESCALE_BIT) +#define TCU_TCSR_PRESCALE1024 (0x5 << TCU_TCSR_PRESCALE_BIT) +#define TCU_TCSR_EXT_EN (1 << 2) +#define TCU_TCSR_RTC_EN (1 << 1) +#define TCU_TCSR_PCK_EN (1 << 0) + +#define TCU_TER_OSTEN (1 << 15) +#define TCU_TER_TCEN5 (1 << 5) +#define TCU_TER_TCEN4 (1 << 4) +#define TCU_TER_TCEN3 (1 << 3) +#define TCU_TER_TCEN2 (1 << 2) +#define TCU_TER_TCEN1 (1 << 1) +#define TCU_TER_TCEN0 (1 << 0) + +#define TCU_TESR_OSTST (1 << 15) +#define TCU_TESR_TCST5 (1 << 5) +#define TCU_TESR_TCST4 (1 << 4) +#define TCU_TESR_TCST3 (1 << 3) +#define TCU_TESR_TCST2 (1 << 2) +#define TCU_TESR_TCST1 (1 << 1) +#define TCU_TESR_TCST0 (1 << 0) + +#define TCU_TECR_OSTCL (1 << 15) +#define TCU_TECR_TCCL5 (1 << 5) +#define TCU_TECR_TCCL4 (1 << 4) +#define TCU_TECR_TCCL3 (1 << 3) +#define TCU_TECR_TCCL2 (1 << 2) +#define TCU_TECR_TCCL1 (1 << 1) +#define TCU_TECR_TCCL0 (1 << 0) + +#define TCU_TFR_HFLAG5 (1 << 21) +#define TCU_TFR_HFLAG4 (1 << 20) +#define TCU_TFR_HFLAG3 (1 << 19) +#define TCU_TFR_HFLAG2 (1 << 18) +#define TCU_TFR_HFLAG1 (1 << 17) +#define TCU_TFR_HFLAG0 (1 << 16) +#define TCU_TFR_FFLAG5 (1 << 5) +#define TCU_TFR_FFLAG4 (1 << 4) +#define TCU_TFR_FFLAG3 (1 << 3) +#define TCU_TFR_FFLAG2 (1 << 2) +#define TCU_TFR_FFLAG1 (1 << 1) +#define TCU_TFR_FFLAG0 (1 << 0) + +#define TCU_TFSR_HFLAG5 (1 << 21) +#define TCU_TFSR_HFLAG4 (1 << 20) +#define TCU_TFSR_HFLAG3 (1 << 19) +#define TCU_TFSR_HFLAG2 (1 << 18) +#define TCU_TFSR_HFLAG1 (1 << 17) +#define TCU_TFSR_HFLAG0 (1 << 16) +#define TCU_TFSR_OSTFLAG (1 << 15) +#define TCU_TFSR_FFLAG5 (1 << 5) +#define TCU_TFSR_FFLAG4 (1 << 4) +#define TCU_TFSR_FFLAG3 (1 << 3) +#define TCU_TFSR_FFLAG2 (1 << 2) +#define TCU_TFSR_FFLAG1 (1 << 1) +#define TCU_TFSR_FFLAG0 (1 << 0) + +#define TCU_TFCR_HFLAG5 (1 << 21) +#define TCU_TFCR_HFLAG4 (1 << 20) +#define TCU_TFCR_HFLAG3 (1 << 19) +#define TCU_TFCR_HFLAG2 (1 << 18) +#define TCU_TFCR_HFLAG1 (1 << 17) +#define TCU_TFCR_HFLAG0 (1 << 16) +#define TCU_TFCR_OSTFLAG (1 << 15) +#define TCU_TFCR_FFLAG5 (1 << 5) +#define TCU_TFCR_FFLAG4 (1 << 4) +#define TCU_TFCR_FFLAG3 (1 << 3) +#define TCU_TFCR_FFLAG2 (1 << 2) +#define TCU_TFCR_FFLAG1 (1 << 1) +#define TCU_TFCR_FFLAG0 (1 << 0) + +#define TCU_TMR_HMASK5 (1 << 21) +#define TCU_TMR_HMASK4 (1 << 20) +#define TCU_TMR_HMASK3 (1 << 19) +#define TCU_TMR_HMASK2 (1 << 18) +#define TCU_TMR_HMASK1 (1 << 17) +#define TCU_TMR_HMASK0 (1 << 16) +#define TCU_TMR_OSTMASK (1 << 15) +#define TCU_TMR_FMASK5 (1 << 5) +#define TCU_TMR_FMASK4 (1 << 4) +#define TCU_TMR_FMASK3 (1 << 3) +#define TCU_TMR_FMASK2 (1 << 2) +#define TCU_TMR_FMASK1 (1 << 1) +#define TCU_TMR_FMASK0 (1 << 0) + +#define TCU_TMSR_HMST5 (1 << 21) +#define TCU_TMSR_HMST4 (1 << 20) +#define TCU_TMSR_HMST3 (1 << 19) +#define TCU_TMSR_HMST2 (1 << 18) +#define TCU_TMSR_HMST1 (1 << 17) +#define TCU_TMSR_HMST0 (1 << 16) +#define TCU_TMSR_OSTMST (1 << 15) +#define TCU_TMSR_FMST5 (1 << 5) +#define TCU_TMSR_FMST4 (1 << 4) +#define TCU_TMSR_FMST3 (1 << 3) +#define TCU_TMSR_FMST2 (1 << 2) +#define TCU_TMSR_FMST1 (1 << 1) +#define TCU_TMSR_FMST0 (1 << 0) + +#define TCU_TMCR_HMCL5 (1 << 21) +#define TCU_TMCR_HMCL4 (1 << 20) +#define TCU_TMCR_HMCL3 (1 << 19) +#define TCU_TMCR_HMCL2 (1 << 18) +#define TCU_TMCR_HMCL1 (1 << 17) +#define TCU_TMCR_HMCL0 (1 << 16) +#define TCU_TMCR_OSTMCL (1 << 15) +#define TCU_TMCR_FMCL5 (1 << 5) +#define TCU_TMCR_FMCL4 (1 << 4) +#define TCU_TMCR_FMCL3 (1 << 3) +#define TCU_TMCR_FMCL2 (1 << 2) +#define TCU_TMCR_FMCL1 (1 << 1) +#define TCU_TMCR_FMCL0 (1 << 0) + +#define TCU_TSR_WDTS (1 << 16) +#define TCU_TSR_STOP5 (1 << 5) +#define TCU_TSR_STOP4 (1 << 4) +#define TCU_TSR_STOP3 (1 << 3) +#define TCU_TSR_STOP2 (1 << 2) +#define TCU_TSR_STOP1 (1 << 1) +#define TCU_TSR_STOP0 (1 << 0) + +#define TCU_TSSR_WDTSS (1 << 16) +#define TCU_TSSR_STPS5 (1 << 5) +#define TCU_TSSR_STPS4 (1 << 4) +#define TCU_TSSR_STPS3 (1 << 3) +#define TCU_TSSR_STPS2 (1 << 2) +#define TCU_TSSR_STPS1 (1 << 1) +#define TCU_TSSR_STPS0 (1 << 0) + +#define TCU_TSSR_WDTSC (1 << 16) +#define TCU_TSSR_STPC5 (1 << 5) +#define TCU_TSSR_STPC4 (1 << 4) +#define TCU_TSSR_STPC3 (1 << 3) +#define TCU_TSSR_STPC2 (1 << 2) +#define TCU_TSSR_STPC1 (1 << 1) +#define TCU_TSSR_STPC0 (1 << 0) + +#define OST_TCSR_CNT_MD ( 1 << 15 ) +#define OST_TCSR_PWM_SHUT_ABRUPT ( 1 << 9 ) +#define OST_TCSR_PRESCALE1 ( 0x0 << 3) +#define OST_TCSR_PRESCALE4 ( 0x1 << 3) +#define OST_TCSR_PRESCALE16 ( 0x2 << 3) +#define OST_TCSR_PRESCALE64 ( 0x3 << 3) +#define OST_TCSR_PRESCALE256 ( 0x4 << 3) +#define OST_TCSR_PRESCALE1024 ( 0x5 << 3) + +/* Uart Register */ +#define UART_RDR(base) __REG8((base) + 0x00) /* R 8b H'xx */ +#define UART_TDR(base) __REG8((base) + 0x00) /* W 8b H'xx */ +#define UART_DLLR(base) __REG8((base) + 0x00) /* RW 8b H'00 */ +#define UART_DLHR(base) __REG8((base) + 0x04) /* RW 8b H'00 */ +#define UART_IER(base) __REG8((base) + 0x04) /* RW 8b H'00 */ +#define UART_ISR(base) __REG8((base) + 0x08) /* R 8b H'01 */ +#define UART_FCR(base) __REG8((base) + 0x08) /* W 8b H'00 */ +#define UART_LCR(base) __REG8((base) + 0x0C) /* RW 8b H'00 */ +#define UART_MCR(base) __REG8((base) + 0x10) /* RW 8b H'00 */ +#define UART_LSR(base) __REG8((base) + 0x14) /* R 8b H'00 */ +#define UART_MSR(base) __REG8((base) + 0x18) /* R 8b H'00 */ +#define UART_SPR(base) __REG8((base) + 0x1C) /* RW 8b H'00 */ +#define UART_MCR(base) __REG8((base) + 0x10) /* RW 8b H'00 */ +#define UART_SIRCR(base) __REG8((base) + 0x20) /* RW 8b H'00 */ + +#define SYSTEM_STACK 0x80003fe8 /* the kernel system stack address */ + +#endif diff --git a/libcpu/mips/jz47xx/mipscfg.c b/libcpu/mips/jz47xx/mipscfg.c index 89bb321c8c..8a96f458ab 100644 --- a/libcpu/mips/jz47xx/mipscfg.c +++ b/libcpu/mips/jz47xx/mipscfg.c @@ -1,82 +1,82 @@ -/*
- * File : mipscfg.c
- * This file is part of RT-Thread RTOS
- * COPYRIGHT (C) 2010, RT-Thread Development Team
- *
- * The license and distribution terms for this file may be
- * found in the file LICENSE in this distribution or at
- * http://www.rt-thread.org/license/LICENSE
- *
- * Change Logs:
- * Date Author Notes
- * 2010-05-27 swkyer first version
- */
-#include <rtthread.h>
-#include "../common/mipsregs.h"
-#include "../common/mipscfg.h"
-
-mips32_core_cfg_t g_mips_core =
-{
- 16, /* icache_line_size */
- 256, /* icache_lines_per_way */
- 4, /* icache_ways */
- 16, /* dcache_line_size */
- 256, /* dcache_lines_per_way */
- 4, /* dcache_ways */
- 16, /* max_tlb_entries */
-};
-
-static rt_uint16_t m_pow(rt_uint16_t b, rt_uint16_t n)
-{
- rt_uint16_t rets = 1;
-
- while (n--)
- rets *= b;
-
- return rets;
-}
-
-static rt_uint16_t m_log2(rt_uint16_t b)
-{
- rt_uint16_t rets = 0;
-
- while (b != 1)
- {
- b /= 2;
- rets++;
- }
-
- return rets;
-}
-
-/**
+/* + * File : mipscfg.c + * This file is part of RT-Thread RTOS + * COPYRIGHT (C) 2010, RT-Thread Development Team + * + * The license and distribution terms for this file may be + * found in the file LICENSE in this distribution or at + * http://www.rt-thread.org/license/LICENSE + * + * Change Logs: + * Date Author Notes + * 2010-05-27 swkyer first version + */ +#include <rtthread.h> +#include "../common/mipsregs.h" +#include "../common/mipscfg.h" + +mips32_core_cfg_t g_mips_core = +{ + 16, /* icache_line_size */ + 256, /* icache_lines_per_way */ + 4, /* icache_ways */ + 16, /* dcache_line_size */ + 256, /* dcache_lines_per_way */ + 4, /* dcache_ways */ + 16, /* max_tlb_entries */ +}; + +static rt_uint16_t m_pow(rt_uint16_t b, rt_uint16_t n) +{ + rt_uint16_t rets = 1; + + while (n--) + rets *= b; + + return rets; +} + +static rt_uint16_t m_log2(rt_uint16_t b) +{ + rt_uint16_t rets = 0; + + while (b != 1) + { + b /= 2; + rets++; + } + + return rets; +} + +/** * read core attribute - */
-void mips32_cfg_init(void)
-{
- rt_uint16_t val;
- rt_uint32_t cp0_config1;
-
- cp0_config1 = read_c0_config();
- if (cp0_config1 & 0x80000000)
- {
- cp0_config1 = read_c0_config1();
-
- val = (cp0_config1 & (7<<22))>>22;
- g_mips_core.icache_lines_per_way = 64 * m_pow(2, val);
- val = (cp0_config1 & (7<<19))>>19;
- g_mips_core.icache_line_size = 2 * m_pow(2, val);
- val = (cp0_config1 & (7<<16))>>16;
- g_mips_core.icache_ways = val + 1;
-
- val = (cp0_config1 & (7<<13))>>13;
- g_mips_core.dcache_lines_per_way = 64 * m_pow(2, val);
- val = (cp0_config1 & (7<<10))>>10;
- g_mips_core.dcache_line_size = 2 * m_pow(2, val);
- val = (cp0_config1 & (7<<7))>>7;
- g_mips_core.dcache_ways = val + 1;
-
- val = (cp0_config1 & (0x3F<<25))>>25;
- g_mips_core.max_tlb_entries = val + 1;
- }
-}
+ */ +void mips32_cfg_init(void) +{ + rt_uint16_t val; + rt_uint32_t cp0_config1; + + cp0_config1 = read_c0_config(); + if (cp0_config1 & 0x80000000) + { + cp0_config1 = read_c0_config1(); + + val = (cp0_config1 & (7<<22))>>22; + g_mips_core.icache_lines_per_way = 64 * m_pow(2, val); + val = (cp0_config1 & (7<<19))>>19; + g_mips_core.icache_line_size = 2 * m_pow(2, val); + val = (cp0_config1 & (7<<16))>>16; + g_mips_core.icache_ways = val + 1; + + val = (cp0_config1 & (7<<13))>>13; + g_mips_core.dcache_lines_per_way = 64 * m_pow(2, val); + val = (cp0_config1 & (7<<10))>>10; + g_mips_core.dcache_line_size = 2 * m_pow(2, val); + val = (cp0_config1 & (7<<7))>>7; + g_mips_core.dcache_ways = val + 1; + + val = (cp0_config1 & (0x3F<<25))>>25; + g_mips_core.max_tlb_entries = val + 1; + } +} diff --git a/libcpu/mips/jz47xx/stack.c b/libcpu/mips/jz47xx/stack.c index 33dbaf5b64..1d408bbff1 100644 --- a/libcpu/mips/jz47xx/stack.c +++ b/libcpu/mips/jz47xx/stack.c @@ -1,94 +1,94 @@ -/*
- * File : stack.c
- * This file is part of RT-Thread RTOS
- * COPYRIGHT (C) 2006, RT-Thread Development Team
- *
- * The license and distribution terms for this file may be
- * found in the file LICENSE in this distribution or at
- * http://www.rt-thread.org/license/LICENSE
- *
- * Change Logs:
- * Date Author Notes
- * 2010-05-17 swkyer first version
- * 2010-07-07 Bernard porting to Jz47xx
- */
-#include <rtthread.h>
-
-/**
- * @addtogroup Jz47xx
- */
-/*@{*/
-
-extern rt_uint32_t cp0_get_cause(void);
-extern rt_uint32_t cp0_get_status(void);
-extern rt_uint32_t cp0_get_hi(void);
-extern rt_uint32_t cp0_get_lo(void);
-
-/**
- * This function will initialize thread stack
- *
- * @param tentry the entry of thread
- * @param parameter the parameter of entry
- * @param stack_addr the beginning stack address
- * @param texit the function will be called when thread exit
- *
- * @return stack address
- */
-rt_uint8_t *rt_hw_stack_init(void *tentry, void *parameter, rt_uint8_t *stack_addr, void *texit)
-{
- rt_uint32_t *stk;
- static rt_uint32_t g_sr = 0;
-
- if (g_sr == 0)
- {
- g_sr = cp0_get_status();
- g_sr &= 0xfffffffe;
- g_sr |= 0x0403;
- }
-
- /** Start at stack top */
- stk = (rt_uint32_t *)stack_addr;
- *(stk) = (rt_uint32_t) tentry; /* pc: Entry Point */
- *(--stk) = (rt_uint32_t) 0xeeee; /* c0_cause */
- *(--stk) = (rt_uint32_t) 0xffff; /* c0_badvaddr */
- *(--stk) = (rt_uint32_t) cp0_get_lo(); /* lo */
- *(--stk) = (rt_uint32_t) cp0_get_hi(); /* hi */
- *(--stk) = (rt_uint32_t) g_sr; /* C0_SR: HW2 = En, IE = En */
- *(--stk) = (rt_uint32_t) texit; /* ra */
- *(--stk) = (rt_uint32_t) 0x0000001e; /* s8 */
- *(--stk) = (rt_uint32_t) stack_addr; /* sp */
- *(--stk) = (rt_uint32_t) 0x0000001c; /* gp */
- *(--stk) = (rt_uint32_t) 0x0000001b; /* k1 */
- *(--stk) = (rt_uint32_t) 0x0000001a; /* k0 */
- *(--stk) = (rt_uint32_t) 0x00000019; /* t9 */
- *(--stk) = (rt_uint32_t) 0x00000018; /* t8 */
- *(--stk) = (rt_uint32_t) 0x00000017; /* s7 */
- *(--stk) = (rt_uint32_t) 0x00000016; /* s6 */
- *(--stk) = (rt_uint32_t) 0x00000015; /* s5 */
- *(--stk) = (rt_uint32_t) 0x00000014; /* s4 */
- *(--stk) = (rt_uint32_t) 0x00000013; /* s3 */
- *(--stk) = (rt_uint32_t) 0x00000012; /* s2 */
- *(--stk) = (rt_uint32_t) 0x00000011; /* s1 */
- *(--stk) = (rt_uint32_t) 0x00000010; /* s0 */
- *(--stk) = (rt_uint32_t) 0x0000000f; /* t7 */
- *(--stk) = (rt_uint32_t) 0x0000000e; /* t6 */
- *(--stk) = (rt_uint32_t) 0x0000000d; /* t5 */
- *(--stk) = (rt_uint32_t) 0x0000000c; /* t4 */
- *(--stk) = (rt_uint32_t) 0x0000000b; /* t3 */
- *(--stk) = (rt_uint32_t) 0x0000000a; /* t2 */
- *(--stk) = (rt_uint32_t) 0x00000009; /* t1 */
- *(--stk) = (rt_uint32_t) 0x00000008; /* t0 */
- *(--stk) = (rt_uint32_t) 0x00000007; /* a3 */
- *(--stk) = (rt_uint32_t) 0x00000006; /* a2 */
- *(--stk) = (rt_uint32_t) 0x00000005; /* a1 */
- *(--stk) = (rt_uint32_t) parameter; /* a0 */
- *(--stk) = (rt_uint32_t) 0x00000003; /* v1 */
- *(--stk) = (rt_uint32_t) 0x00000002; /* v0 */
- *(--stk) = (rt_uint32_t) 0x00000001; /* at */
- *(--stk) = (rt_uint32_t) 0x00000000; /* zero */
-
- /* return task's current stack address */
- return (rt_uint8_t *)stk;
-}
-
-/*@}*/
+/* + * File : stack.c + * This file is part of RT-Thread RTOS + * COPYRIGHT (C) 2006, RT-Thread Development Team + * + * The license and distribution terms for this file may be + * found in the file LICENSE in this distribution or at + * http://www.rt-thread.org/license/LICENSE + * + * Change Logs: + * Date Author Notes + * 2010-05-17 swkyer first version + * 2010-07-07 Bernard porting to Jz47xx + */ +#include <rtthread.h> + +/** + * @addtogroup Jz47xx + */ +/*@{*/ + +extern rt_uint32_t cp0_get_cause(void); +extern rt_uint32_t cp0_get_status(void); +extern rt_uint32_t cp0_get_hi(void); +extern rt_uint32_t cp0_get_lo(void); + +/** + * This function will initialize thread stack + * + * @param tentry the entry of thread + * @param parameter the parameter of entry + * @param stack_addr the beginning stack address + * @param texit the function will be called when thread exit + * + * @return stack address + */ +rt_uint8_t *rt_hw_stack_init(void *tentry, void *parameter, rt_uint8_t *stack_addr, void *texit) +{ + rt_uint32_t *stk; + static rt_uint32_t g_sr = 0; + + if (g_sr == 0) + { + g_sr = cp0_get_status(); + g_sr &= 0xfffffffe; + g_sr |= 0x0403; + } + + /** Start at stack top */ + stk = (rt_uint32_t *)stack_addr; + *(stk) = (rt_uint32_t) tentry; /* pc: Entry Point */ + *(--stk) = (rt_uint32_t) 0xeeee; /* c0_cause */ + *(--stk) = (rt_uint32_t) 0xffff; /* c0_badvaddr */ + *(--stk) = (rt_uint32_t) cp0_get_lo(); /* lo */ + *(--stk) = (rt_uint32_t) cp0_get_hi(); /* hi */ + *(--stk) = (rt_uint32_t) g_sr; /* C0_SR: HW2 = En, IE = En */ + *(--stk) = (rt_uint32_t) texit; /* ra */ + *(--stk) = (rt_uint32_t) 0x0000001e; /* s8 */ + *(--stk) = (rt_uint32_t) stack_addr; /* sp */ + *(--stk) = (rt_uint32_t) 0x0000001c; /* gp */ + *(--stk) = (rt_uint32_t) 0x0000001b; /* k1 */ + *(--stk) = (rt_uint32_t) 0x0000001a; /* k0 */ + *(--stk) = (rt_uint32_t) 0x00000019; /* t9 */ + *(--stk) = (rt_uint32_t) 0x00000018; /* t8 */ + *(--stk) = (rt_uint32_t) 0x00000017; /* s7 */ + *(--stk) = (rt_uint32_t) 0x00000016; /* s6 */ + *(--stk) = (rt_uint32_t) 0x00000015; /* s5 */ + *(--stk) = (rt_uint32_t) 0x00000014; /* s4 */ + *(--stk) = (rt_uint32_t) 0x00000013; /* s3 */ + *(--stk) = (rt_uint32_t) 0x00000012; /* s2 */ + *(--stk) = (rt_uint32_t) 0x00000011; /* s1 */ + *(--stk) = (rt_uint32_t) 0x00000010; /* s0 */ + *(--stk) = (rt_uint32_t) 0x0000000f; /* t7 */ + *(--stk) = (rt_uint32_t) 0x0000000e; /* t6 */ + *(--stk) = (rt_uint32_t) 0x0000000d; /* t5 */ + *(--stk) = (rt_uint32_t) 0x0000000c; /* t4 */ + *(--stk) = (rt_uint32_t) 0x0000000b; /* t3 */ + *(--stk) = (rt_uint32_t) 0x0000000a; /* t2 */ + *(--stk) = (rt_uint32_t) 0x00000009; /* t1 */ + *(--stk) = (rt_uint32_t) 0x00000008; /* t0 */ + *(--stk) = (rt_uint32_t) 0x00000007; /* a3 */ + *(--stk) = (rt_uint32_t) 0x00000006; /* a2 */ + *(--stk) = (rt_uint32_t) 0x00000005; /* a1 */ + *(--stk) = (rt_uint32_t) parameter; /* a0 */ + *(--stk) = (rt_uint32_t) 0x00000003; /* v1 */ + *(--stk) = (rt_uint32_t) 0x00000002; /* v0 */ + *(--stk) = (rt_uint32_t) 0x00000001; /* at */ + *(--stk) = (rt_uint32_t) 0x00000000; /* zero */ + + /* return task's current stack address */ + return (rt_uint8_t *)stk; +} + +/*@}*/ diff --git a/libcpu/mips/jz47xx/start_gcc.S b/libcpu/mips/jz47xx/start_gcc.S index d496b54e92..162c491b1d 100644 --- a/libcpu/mips/jz47xx/start_gcc.S +++ b/libcpu/mips/jz47xx/start_gcc.S @@ -1,151 +1,151 @@ -/*
- * File : start_gcc.S
- * Change Logs:
- * Date Author Notes
- * 2010-05-17 swkyer first version
- * 2010-09-04 bernard porting to Jz47xx
- */
-
-#include "../common/mips.inc"
-#include "../common/stackframe.h"
-#include "jz47xx.h"
-
- .section ".start", "ax"
- .set noreorder
-
- /* the program entry */
- .globl _start
-_start:
- .set noreorder
- la ra, _start
-
- /* init cp0 registers. */
- li t0, 0x0000FC00 /* BEV = 0 and mask all interrupt */
- mtc0 t0, CP0_STATUS
-
- li t1, 0x00800000
- mtc0 t1, CP0_CAUSE
-
- /* setup stack pointer */
- li sp, SYSTEM_STACK
- la gp, _gp
-
- /* init caches, assumes a 4way * 128set * 32byte I/D cache */
- li t0, 3 /* enable cache for kseg0 accesses */
- mtc0 t0, CP0_CONFIG /* CONFIG reg */
- la t0, 0x80000000 /* an idx op should use an unmappable address */
- ori t1, t0, 0x4000 /* 16kB cache */
- mtc0 zero, CP0_TAGLO /* TAGLO reg */
- mtc0 zero, CP0_TAGHI /* TAGHI reg */
-
-_cache_loop:
- cache 0x8, 0(t0) /* index store icache tag */
- cache 0x9, 0(t0) /* index store dcache tag */
- bne t0, t1, _cache_loop
- addiu t0, t0, 0x20 /* 32 bytes per cache line */
- nop
-
- /* invalidate BTB */
- mfc0 t0, CP0_CONFIG
- nop
- ori t0, 2
- mtc0 t0, CP0_CONFIG
- nop
-
- /* copy IRAM section */
- la t0, _iramcopy
- la t1, _iramstart
- la t2, _iramend
-_iram_loop:
- lw t3, 0(t0)
- sw t3, 0(t1)
- addiu t1, 4
- bne t1, t2, _iram_loop
- addiu t0, 4
-
- /* clear bss */
- la t0, __bss_start
- la t1, __bss_end
-_clr_bss_loop:
- sw zero, 0(t0)
- bne t0, t1, _clr_bss_loop
- addiu t0, t0, 4
-
- /* jump to RT-Thread RTOS */
- jal rtthread_startup
- nop
-
- /* restart, never die */
- j _start
- nop
- .set reorder
-
- .globl cp0_get_cause
-cp0_get_cause:
- mfc0 v0, CP0_CAUSE
- jr ra
- nop
-
- .globl cp0_get_status
-cp0_get_status:
- mfc0 v0, CP0_STATUS
- jr ra
- nop
-
- .globl cp0_get_hi
-cp0_get_hi:
- mfhi v0
- jr ra
- nop
-
- .globl cp0_get_lo
-cp0_get_lo:
- mflo v0
- jr ra
- nop
-
- .extern tlb_refill_handler
- .extern cache_error_handler
-
- /* Exception Handler */
- /* 0x0 - TLB refill handler */
- .section .vectors.1, "ax", %progbits
- j tlb_refill_handler
- nop
-
- /* 0x100 - Cache error handler */
- .section .vectors.2, "ax", %progbits
- j cache_error_handler
- nop
-
- /* 0x180 - Exception/Interrupt handler */
- .section .vectors.3, "ax", %progbits
- j _general_exception_handler
- nop
-
- /* 0x200 - Special Exception Interrupt handler (when IV is set in CP0_CAUSE) */
- .section .vectors.4, "ax", %progbits
- j _irq_handler
- nop
-
- .section .vectors, "ax", %progbits
- .extern mips_irq_handle
-
- /* general exception handler */
-_general_exception_handler:
- .set noreorder
- mfc0 k1, CP0_CAUSE
- andi k1, k1, 0x7c
- srl k1, k1, 2
- lw k0, sys_exception_handlers(k1)
- jr k0
- nop
- .set reorder
-
- /* interrupt handler */
-_irq_handler:
- .set noreorder
- la k0, mips_irq_handle
- jr k0
- nop
- .set reorder
+/* + * File : start_gcc.S + * Change Logs: + * Date Author Notes + * 2010-05-17 swkyer first version + * 2010-09-04 bernard porting to Jz47xx + */ + +#include "../common/mips.inc" +#include "../common/stackframe.h" +#include "jz47xx.h" + + .section ".start", "ax" + .set noreorder + + /* the program entry */ + .globl _start +_start: + .set noreorder + la ra, _start + + /* init cp0 registers. */ + li t0, 0x0000FC00 /* BEV = 0 and mask all interrupt */ + mtc0 t0, CP0_STATUS + + li t1, 0x00800000 + mtc0 t1, CP0_CAUSE + + /* setup stack pointer */ + li sp, SYSTEM_STACK + la gp, _gp + + /* init caches, assumes a 4way * 128set * 32byte I/D cache */ + li t0, 3 /* enable cache for kseg0 accesses */ + mtc0 t0, CP0_CONFIG /* CONFIG reg */ + la t0, 0x80000000 /* an idx op should use an unmappable address */ + ori t1, t0, 0x4000 /* 16kB cache */ + mtc0 zero, CP0_TAGLO /* TAGLO reg */ + mtc0 zero, CP0_TAGHI /* TAGHI reg */ + +_cache_loop: + cache 0x8, 0(t0) /* index store icache tag */ + cache 0x9, 0(t0) /* index store dcache tag */ + bne t0, t1, _cache_loop + addiu t0, t0, 0x20 /* 32 bytes per cache line */ + nop + + /* invalidate BTB */ + mfc0 t0, CP0_CONFIG + nop + ori t0, 2 + mtc0 t0, CP0_CONFIG + nop + + /* copy IRAM section */ + la t0, _iramcopy + la t1, _iramstart + la t2, _iramend +_iram_loop: + lw t3, 0(t0) + sw t3, 0(t1) + addiu t1, 4 + bne t1, t2, _iram_loop + addiu t0, 4 + + /* clear bss */ + la t0, __bss_start + la t1, __bss_end +_clr_bss_loop: + sw zero, 0(t0) + bne t0, t1, _clr_bss_loop + addiu t0, t0, 4 + + /* jump to RT-Thread RTOS */ + jal rtthread_startup + nop + + /* restart, never die */ + j _start + nop + .set reorder + + .globl cp0_get_cause +cp0_get_cause: + mfc0 v0, CP0_CAUSE + jr ra + nop + + .globl cp0_get_status +cp0_get_status: + mfc0 v0, CP0_STATUS + jr ra + nop + + .globl cp0_get_hi +cp0_get_hi: + mfhi v0 + jr ra + nop + + .globl cp0_get_lo +cp0_get_lo: + mflo v0 + jr ra + nop + + .extern tlb_refill_handler + .extern cache_error_handler + + /* Exception Handler */ + /* 0x0 - TLB refill handler */ + .section .vectors.1, "ax", %progbits + j tlb_refill_handler + nop + + /* 0x100 - Cache error handler */ + .section .vectors.2, "ax", %progbits + j cache_error_handler + nop + + /* 0x180 - Exception/Interrupt handler */ + .section .vectors.3, "ax", %progbits + j _general_exception_handler + nop + + /* 0x200 - Special Exception Interrupt handler (when IV is set in CP0_CAUSE) */ + .section .vectors.4, "ax", %progbits + j _irq_handler + nop + + .section .vectors, "ax", %progbits + .extern mips_irq_handle + + /* general exception handler */ +_general_exception_handler: + .set noreorder + mfc0 k1, CP0_CAUSE + andi k1, k1, 0x7c + srl k1, k1, 2 + lw k0, sys_exception_handlers(k1) + jr k0 + nop + .set reorder + + /* interrupt handler */ +_irq_handler: + .set noreorder + la k0, mips_irq_handle + jr k0 + nop + .set reorder diff --git a/libcpu/mips/loongson/cache.c b/libcpu/mips/loongson/cache.c index bca01a61f4..6b3ad84b0e 100644 --- a/libcpu/mips/loongson/cache.c +++ b/libcpu/mips/loongson/cache.c @@ -1,188 +1,188 @@ -#include "../common/mipsregs.h"
-#include "cache.h"
-
-#define K0BASE 0x80000000
-#define PRID_3210I 0x4200
-
-typedef struct cacheinfo_t {
- unsigned int icache_size;
- unsigned int dcache_size;
- unsigned int icacheline_size;
- unsigned int dcacheline_size;
-} cacheinfo_t ;
-
-typedef struct cacheop_t {
- void (*Clear_TagLo) (void);
- void (*Invalidate_Icache) (unsigned int);
- void (*Invalidate_Dcache_Fill) (unsigned int);
- void (*Invalidate_Dcache_ClearTag) (unsigned int);
- void (*Init_Cache)(void);
-} cacheop_t ;
-
-static cacheop_t cacheop, *pcacheop;
-static cacheinfo_t cacheinfo, *pcacheinfo;
-
-int identify_cpu (void)
-{
- unsigned int cpu_id;
- void invalidate_cache (void);
-
- pcacheop = &cacheop;
- pcacheinfo = &cacheinfo;
-
- rt_kprintf("CPU configure: 0x%08x\n", read_c0_config());
- cpu_id = read_c0_prid();
- switch (cpu_id)
- {
- case PRID_3210I:
- rt_kprintf ("CPU:SoC3210\n");
- pcacheop->Clear_TagLo = Clear_TagLo;
- pcacheop->Invalidate_Icache = Invalidate_Icache_Gc3210I;
- pcacheop->Invalidate_Dcache_Fill = Invalidate_Dcache_Fill_Gc3210I;
- pcacheop->Invalidate_Dcache_ClearTag = Invalidate_Dcache_ClearTag_Gc3210I;
- break;
- default:
- rt_kprintf ("Unknown CPU type, system halted!\n");
- while (1) {}
- break;
- }
-
- return 0;
-}
-
-void probe_cache(void)
-{
- unsigned int config = read_c0_config ();
- unsigned int icache_size, ic_lsize;
- unsigned int dcache_size, dc_lsize;
-
- icache_size = 1 << (12 + ((config >> 9) & 7));
- dcache_size = 1 << (12 + ((config >> 6) & 7));
- ic_lsize = 16 << ((config >> 5) & 1);
- dc_lsize = 16 << ((config >> 4) & 1);
-
- rt_kprintf("DCache %2dkb, linesize %d bytes.\n",
- dcache_size >> 10, dc_lsize);
- rt_kprintf("ICache %2dkb, linesize %d bytes.\n",
- icache_size >> 10, ic_lsize);
-
- pcacheinfo->icache_size = icache_size;
- pcacheinfo->dcache_size = dcache_size;
- pcacheinfo->icacheline_size = ic_lsize;
- pcacheinfo->dcacheline_size = dc_lsize;
-
- return ;
-}
-
-void invalidate_writeback_dcache_all(void)
-{
- unsigned int start = K0BASE;
- unsigned int end = (start + pcacheinfo->dcache_size);
-
- start = K0BASE;
- while(start < end) {
- Writeback_Invalidate_Dcache(start); //hit writeback invalidate
- start += pcacheinfo->dcacheline_size;
- }
-}
-
-void invalidate_writeback_dcache(unsigned long addr, int size)
-{
- unsigned long start, end;
-
- start = (addr +pcacheinfo->dcacheline_size -1) & (- pcacheinfo->dcacheline_size);
- end = (end + size + pcacheinfo->dcacheline_size -1) & ( -pcacheinfo->dcacheline_size);
-
- while(start <end){
- Writeback_Invalidate_Dcache(start);
- start += pcacheinfo->dcacheline_size;
- }
-}
-
-
-void invalidate_icache_all(void)
-{
- unsigned int start = K0BASE;
- unsigned int end = (start + pcacheinfo->icache_size);
-
- while(start < end) {
- pcacheop->Invalidate_Icache(start);
- start += pcacheinfo->icacheline_size;
- }
-}
-
-void invalidate_dcache_all()
-{
- unsigned int start = K0BASE;
- unsigned int end = (start + pcacheinfo->dcache_size);
- while(start <end){
- Invalidate_Dcache_Fill_Gc3210I(start);
- start += pcacheinfo->icacheline_size;
- }
-}
-
-//with cache disabled
-void init_dcache(void)
-{
- unsigned int start = K0BASE;
- unsigned int end = (start + pcacheinfo->dcache_size);
-
- while(start < end){
- pcacheop->Invalidate_Dcache_ClearTag(start);
- start += pcacheinfo->dcacheline_size;
- }
-
-}
-
-void rt_hw_cache_init(void)
-{
- unsigned int start, end;
-
- /* 1. identify cpu and probe cache */
- identify_cpu();
- probe_cache();
-
- start = K0BASE;
- end = (start + pcacheinfo->icache_size);
-
- /*
- * 2. clear CP0 taglo/taghi register;
- */
- pcacheop->Clear_TagLo();
-
- /*
- * 3. invalidate instruction cache;
- */
- while(start < end) {
- pcacheop->Invalidate_Icache(start); //index invalidate icache
- start += pcacheinfo->icacheline_size;
- }
-
- /*
- * 4. invalidate data cache;
- */
- start = K0BASE;
- end = (start + pcacheinfo->dcache_size);
- while(start < end) {
- pcacheop->Invalidate_Dcache_ClearTag(start);
- start += pcacheinfo->dcacheline_size;
- }
-
- start = K0BASE;
- while(start < end) {
- pcacheop->Invalidate_Dcache_Fill(start); //index invalidate dcache
- start += pcacheinfo->dcacheline_size;
- }
-
- start = K0BASE;
- while(start < end) {
- pcacheop->Invalidate_Dcache_ClearTag(start);
- start += pcacheinfo->dcacheline_size;
- }
-
- /* enable cache */
- enable_cpu_cache();
- rt_kprintf("enable cpu cache done\n");
-
- return ;
-}
+#include "../common/mipsregs.h" +#include "cache.h" + +#define K0BASE 0x80000000 +#define PRID_3210I 0x4200 + +typedef struct cacheinfo_t { + unsigned int icache_size; + unsigned int dcache_size; + unsigned int icacheline_size; + unsigned int dcacheline_size; +} cacheinfo_t ; + +typedef struct cacheop_t { + void (*Clear_TagLo) (void); + void (*Invalidate_Icache) (unsigned int); + void (*Invalidate_Dcache_Fill) (unsigned int); + void (*Invalidate_Dcache_ClearTag) (unsigned int); + void (*Init_Cache)(void); +} cacheop_t ; + +static cacheop_t cacheop, *pcacheop; +static cacheinfo_t cacheinfo, *pcacheinfo; + +int identify_cpu (void) +{ + unsigned int cpu_id; + void invalidate_cache (void); + + pcacheop = &cacheop; + pcacheinfo = &cacheinfo; + + rt_kprintf("CPU configure: 0x%08x\n", read_c0_config()); + cpu_id = read_c0_prid(); + switch (cpu_id) + { + case PRID_3210I: + rt_kprintf ("CPU:SoC3210\n"); + pcacheop->Clear_TagLo = Clear_TagLo; + pcacheop->Invalidate_Icache = Invalidate_Icache_Gc3210I; + pcacheop->Invalidate_Dcache_Fill = Invalidate_Dcache_Fill_Gc3210I; + pcacheop->Invalidate_Dcache_ClearTag = Invalidate_Dcache_ClearTag_Gc3210I; + break; + default: + rt_kprintf ("Unknown CPU type, system halted!\n"); + while (1) {} + break; + } + + return 0; +} + +void probe_cache(void) +{ + unsigned int config = read_c0_config (); + unsigned int icache_size, ic_lsize; + unsigned int dcache_size, dc_lsize; + + icache_size = 1 << (12 + ((config >> 9) & 7)); + dcache_size = 1 << (12 + ((config >> 6) & 7)); + ic_lsize = 16 << ((config >> 5) & 1); + dc_lsize = 16 << ((config >> 4) & 1); + + rt_kprintf("DCache %2dkb, linesize %d bytes.\n", + dcache_size >> 10, dc_lsize); + rt_kprintf("ICache %2dkb, linesize %d bytes.\n", + icache_size >> 10, ic_lsize); + + pcacheinfo->icache_size = icache_size; + pcacheinfo->dcache_size = dcache_size; + pcacheinfo->icacheline_size = ic_lsize; + pcacheinfo->dcacheline_size = dc_lsize; + + return ; +} + +void invalidate_writeback_dcache_all(void) +{ + unsigned int start = K0BASE; + unsigned int end = (start + pcacheinfo->dcache_size); + + start = K0BASE; + while(start < end) { + Writeback_Invalidate_Dcache(start); //hit writeback invalidate + start += pcacheinfo->dcacheline_size; + } +} + +void invalidate_writeback_dcache(unsigned long addr, int size) +{ + unsigned long start, end; + + start = (addr +pcacheinfo->dcacheline_size -1) & (- pcacheinfo->dcacheline_size); + end = (end + size + pcacheinfo->dcacheline_size -1) & ( -pcacheinfo->dcacheline_size); + + while(start <end){ + Writeback_Invalidate_Dcache(start); + start += pcacheinfo->dcacheline_size; + } +} + + +void invalidate_icache_all(void) +{ + unsigned int start = K0BASE; + unsigned int end = (start + pcacheinfo->icache_size); + + while(start < end) { + pcacheop->Invalidate_Icache(start); + start += pcacheinfo->icacheline_size; + } +} + +void invalidate_dcache_all() +{ + unsigned int start = K0BASE; + unsigned int end = (start + pcacheinfo->dcache_size); + while(start <end){ + Invalidate_Dcache_Fill_Gc3210I(start); + start += pcacheinfo->icacheline_size; + } +} + +//with cache disabled +void init_dcache(void) +{ + unsigned int start = K0BASE; + unsigned int end = (start + pcacheinfo->dcache_size); + + while(start < end){ + pcacheop->Invalidate_Dcache_ClearTag(start); + start += pcacheinfo->dcacheline_size; + } + +} + +void rt_hw_cache_init(void) +{ + unsigned int start, end; + + /* 1. identify cpu and probe cache */ + identify_cpu(); + probe_cache(); + + start = K0BASE; + end = (start + pcacheinfo->icache_size); + + /* + * 2. clear CP0 taglo/taghi register; + */ + pcacheop->Clear_TagLo(); + + /* + * 3. invalidate instruction cache; + */ + while(start < end) { + pcacheop->Invalidate_Icache(start); //index invalidate icache + start += pcacheinfo->icacheline_size; + } + + /* + * 4. invalidate data cache; + */ + start = K0BASE; + end = (start + pcacheinfo->dcache_size); + while(start < end) { + pcacheop->Invalidate_Dcache_ClearTag(start); + start += pcacheinfo->dcacheline_size; + } + + start = K0BASE; + while(start < end) { + pcacheop->Invalidate_Dcache_Fill(start); //index invalidate dcache + start += pcacheinfo->dcacheline_size; + } + + start = K0BASE; + while(start < end) { + pcacheop->Invalidate_Dcache_ClearTag(start); + start += pcacheinfo->dcacheline_size; + } + + /* enable cache */ + enable_cpu_cache(); + rt_kprintf("enable cpu cache done\n"); + + return ; +} diff --git a/libcpu/mips/loongson/cache.h b/libcpu/mips/loongson/cache.h index fb4899a6b2..26f7649b42 100644 --- a/libcpu/mips/loongson/cache.h +++ b/libcpu/mips/loongson/cache.h @@ -1,47 +1,47 @@ -#ifndef __CACHE_H__
-#define __CACHE_H__
-
-/*
- * Cache Operations
- */
-#define Index_Invalidate_I 0x00
-#define Index_Writeback_Inv_D 0x01
-#define Index_Invalidate_SI 0x02
-#define Index_Writeback_Inv_SD 0x03
-#define Index_Load_Tag_I 0x04
-#define Index_Load_Tag_D 0x05
-#define Index_Load_Tag_SI 0x06
-#define Index_Load_Tag_SD 0x07
-#define Index_Store_Tag_I 0x08
-#define Index_Store_Tag_D 0x09
-#define Index_Store_Tag_SI 0x0A
-#define Index_Store_Tag_SD 0x0B
-#define Create_Dirty_Excl_D 0x0d
-#define Create_Dirty_Excl_SD 0x0f
-#define Hit_Invalidate_I 0x10
-#define Hit_Invalidate_D 0x11
-#define Hit_Invalidate_SI 0x12
-#define Hit_Invalidate_SD 0x13
-#define Fill 0x14
-#define Hit_Writeback_Inv_D 0x15
-/* 0x16 is unused */
-#define Hit_Writeback_Inv_SD 0x17
-#define Hit_Writeback_I 0x18
-#define Hit_Writeback_D 0x19
-/* 0x1a is unused */
-#define Hit_Writeback_SD 0x1b
-/* 0x1c is unused */
-/* 0x1e is unused */
-#define Hit_Set_Virtual_SI 0x1e
-#define Hit_Set_Virtual_SD 0x1f
-
-extern void Clear_TagLo (void);
-
-extern void Invalidate_Icache_Gc3210I (unsigned int);
-extern void Invalidate_Dcache_ClearTag_Gc3210I (unsigned int);
-extern void Invalidate_Dcache_Fill_Gc3210I(unsigned int);
-extern void Writeback_Invalidate_Dcache(unsigned int);
-
-void rt_hw_cache_init(void);
-
-#endif
+#ifndef __CACHE_H__ +#define __CACHE_H__ + +/* + * Cache Operations + */ +#define Index_Invalidate_I 0x00 +#define Index_Writeback_Inv_D 0x01 +#define Index_Invalidate_SI 0x02 +#define Index_Writeback_Inv_SD 0x03 +#define Index_Load_Tag_I 0x04 +#define Index_Load_Tag_D 0x05 +#define Index_Load_Tag_SI 0x06 +#define Index_Load_Tag_SD 0x07 +#define Index_Store_Tag_I 0x08 +#define Index_Store_Tag_D 0x09 +#define Index_Store_Tag_SI 0x0A +#define Index_Store_Tag_SD 0x0B +#define Create_Dirty_Excl_D 0x0d +#define Create_Dirty_Excl_SD 0x0f +#define Hit_Invalidate_I 0x10 +#define Hit_Invalidate_D 0x11 +#define Hit_Invalidate_SI 0x12 +#define Hit_Invalidate_SD 0x13 +#define Fill 0x14 +#define Hit_Writeback_Inv_D 0x15 +/* 0x16 is unused */ +#define Hit_Writeback_Inv_SD 0x17 +#define Hit_Writeback_I 0x18 +#define Hit_Writeback_D 0x19 +/* 0x1a is unused */ +#define Hit_Writeback_SD 0x1b +/* 0x1c is unused */ +/* 0x1e is unused */ +#define Hit_Set_Virtual_SI 0x1e +#define Hit_Set_Virtual_SD 0x1f + +extern void Clear_TagLo (void); + +extern void Invalidate_Icache_Gc3210I (unsigned int); +extern void Invalidate_Dcache_ClearTag_Gc3210I (unsigned int); +extern void Invalidate_Dcache_Fill_Gc3210I(unsigned int); +extern void Writeback_Invalidate_Dcache(unsigned int); + +void rt_hw_cache_init(void); + +#endif diff --git a/libcpu/mips/loongson/cache.inc b/libcpu/mips/loongson/cache.inc index 6adac65857..815abb7f92 100644 --- a/libcpu/mips/loongson/cache.inc +++ b/libcpu/mips/loongson/cache.inc @@ -1,38 +1,38 @@ -#ifndef __CACHE_H__
-#define __CACHE_H__
-
-/*
- * Cache Operations
- */
-#define Index_Invalidate_I 0x00
-#define Index_Writeback_Inv_D 0x01
-#define Index_Invalidate_SI 0x02
-#define Index_Writeback_Inv_SD 0x03
-#define Index_Load_Tag_I 0x04
-#define Index_Load_Tag_D 0x05
-#define Index_Load_Tag_SI 0x06
-#define Index_Load_Tag_SD 0x07
-#define Index_Store_Tag_I 0x08
-#define Index_Store_Tag_D 0x09
-#define Index_Store_Tag_SI 0x0A
-#define Index_Store_Tag_SD 0x0B
-#define Create_Dirty_Excl_D 0x0d
-#define Create_Dirty_Excl_SD 0x0f
-#define Hit_Invalidate_I 0x10
-#define Hit_Invalidate_D 0x11
-#define Hit_Invalidate_SI 0x12
-#define Hit_Invalidate_SD 0x13
-#define Fill 0x14
-#define Hit_Writeback_Inv_D 0x15
-/* 0x16 is unused */
-#define Hit_Writeback_Inv_SD 0x17
-#define Hit_Writeback_I 0x18
-#define Hit_Writeback_D 0x19
-/* 0x1a is unused */
-#define Hit_Writeback_SD 0x1b
-/* 0x1c is unused */
-/* 0x1e is unused */
-#define Hit_Set_Virtual_SI 0x1e
-#define Hit_Set_Virtual_SD 0x1f
-
-#endif
+#ifndef __CACHE_H__ +#define __CACHE_H__ + +/* + * Cache Operations + */ +#define Index_Invalidate_I 0x00 +#define Index_Writeback_Inv_D 0x01 +#define Index_Invalidate_SI 0x02 +#define Index_Writeback_Inv_SD 0x03 +#define Index_Load_Tag_I 0x04 +#define Index_Load_Tag_D 0x05 +#define Index_Load_Tag_SI 0x06 +#define Index_Load_Tag_SD 0x07 +#define Index_Store_Tag_I 0x08 +#define Index_Store_Tag_D 0x09 +#define Index_Store_Tag_SI 0x0A +#define Index_Store_Tag_SD 0x0B +#define Create_Dirty_Excl_D 0x0d +#define Create_Dirty_Excl_SD 0x0f +#define Hit_Invalidate_I 0x10 +#define Hit_Invalidate_D 0x11 +#define Hit_Invalidate_SI 0x12 +#define Hit_Invalidate_SD 0x13 +#define Fill 0x14 +#define Hit_Writeback_Inv_D 0x15 +/* 0x16 is unused */ +#define Hit_Writeback_Inv_SD 0x17 +#define Hit_Writeback_I 0x18 +#define Hit_Writeback_D 0x19 +/* 0x1a is unused */ +#define Hit_Writeback_SD 0x1b +/* 0x1c is unused */ +/* 0x1e is unused */ +#define Hit_Set_Virtual_SI 0x1e +#define Hit_Set_Virtual_SD 0x1f + +#endif diff --git a/libcpu/mips/loongson/context_gcc.S b/libcpu/mips/loongson/context_gcc.S index 65cab6e147..1bb953fe8c 100644 --- a/libcpu/mips/loongson/context_gcc.S +++ b/libcpu/mips/loongson/context_gcc.S @@ -1,141 +1,141 @@ -/*
- * File : context_gcc.S
- * Change Logs:
- * Date Author Notes
- * 2010-05-17 swkyer first version
- * 2010-09-11 bernard port to Loongson SoC3210
- */
-#include "../common/mips.inc"
-#include "../common/stackframe.h"
-#include "soc3210.h"
-
- .section ".text", "ax"
- .set noreorder
-
-/*
- * rt_base_t rt_hw_interrupt_disable()
- */
- .globl rt_hw_interrupt_disable
-rt_hw_interrupt_disable:
- mfc0 v0, CP0_STATUS
- and v1, v0, 0xfffffffe
- mtc0 v1, CP0_STATUS
- jr ra
- nop
-
-/*
- * void rt_hw_interrupt_enable(rt_base_t level)
- */
- .globl rt_hw_interrupt_enable
-rt_hw_interrupt_enable:
- mtc0 a0, CP0_STATUS
- jr ra
- nop
-
-/*
- * void rt_hw_context_switch(rt_uint32 from, rt_uint32 to)
- * a0 --> from
- * a1 --> to
- */
- .globl rt_hw_context_switch
-rt_hw_context_switch:
- mtc0 ra, CP0_EPC
- SAVE_ALL
-
- sw sp, 0(a0) /* store sp in preempted tasks TCB */
- lw sp, 0(a1) /* get new task stack pointer */
-
- RESTORE_ALL_AND_RET
-
-/*
- * void rt_hw_context_switch_to(rt_uint32 to)/*
- * a0 --> to
- */
- .globl rt_hw_context_switch_to
-rt_hw_context_switch_to:
- lw sp, 0(a0) /* get new task stack pointer */
-
- RESTORE_ALL_AND_RET
-
-/*
- * void rt_hw_context_switch_interrupt(rt_uint32 from, rt_uint32 to)/*
- */
- .globl rt_thread_switch_interrupt_flag
- .globl rt_interrupt_from_thread
- .globl rt_interrupt_to_thread
- .globl rt_hw_context_switch_interrupt
-rt_hw_context_switch_interrupt:
- la t0, rt_thread_switch_interrupt_flag
- lw t1, 0(t0)
- nop
- bnez t1, _reswitch
- nop
- li t1, 0x01 /* set rt_thread_switch_interrupt_flag to 1 */
- sw t1, 0(t0)
- la t0, rt_interrupt_from_thread /* set rt_interrupt_from_thread */
- sw a0, 0(t0)
-_reswitch:
- la t0, rt_interrupt_to_thread /* set rt_interrupt_to_thread */
- sw a1, 0(t0)
- jr ra
- nop
-
-/*
- * void rt_hw_context_switch_interrupt_do(rt_base_t flag)
- */
- .globl rt_interrupt_enter
- .globl rt_interrupt_leave
- .globl mips_irq_handle
-mips_irq_handle:
- SAVE_ALL
-
- mfc0 t0, CP0_CAUSE
- and t1, t0, 0xff
- bnez t1, spurious_interrupt /* check exception */
- nop
-
- /* let k0 keep the current context sp */
- move k0, sp
- /* switch to kernel stack */
- li sp, SYSTEM_STACK
-
- jal rt_interrupt_enter
- nop
- jal rt_interrupt_dispatch
- nop
- jal rt_interrupt_leave
- nop
-
- /* switch sp back to thread's context */
- move sp, k0
-
- /*
- * if rt_thread_switch_interrupt_flag set, jump to
- * rt_hw_context_switch_interrupt_do and don't return
- */
- la k0, rt_thread_switch_interrupt_flag
- lw k1, 0(k0)
- beqz k1, spurious_interrupt
- nop
- sw zero, 0(k0) /* clear flag */
- nop
-
- /*
- * switch to the new thread
- */
- la k0, rt_interrupt_from_thread
- lw k1, 0(k0)
- nop
- sw sp, 0(k1) /* store sp in preempted tasks's TCB */
-
- la k0, rt_interrupt_to_thread
- lw k1, 0(k0)
- nop
- lw sp, 0(k1) /* get new task's stack pointer */
- j spurious_interrupt
- nop
-
-spurious_interrupt:
- RESTORE_ALL_AND_RET
-
- .set reorder
+/* + * File : context_gcc.S + * Change Logs: + * Date Author Notes + * 2010-05-17 swkyer first version + * 2010-09-11 bernard port to Loongson SoC3210 + */ +#include "../common/mips.inc" +#include "../common/stackframe.h" +#include "soc3210.h" + + .section ".text", "ax" + .set noreorder + +/* + * rt_base_t rt_hw_interrupt_disable() + */ + .globl rt_hw_interrupt_disable +rt_hw_interrupt_disable: + mfc0 v0, CP0_STATUS + and v1, v0, 0xfffffffe + mtc0 v1, CP0_STATUS + jr ra + nop + +/* + * void rt_hw_interrupt_enable(rt_base_t level) + */ + .globl rt_hw_interrupt_enable +rt_hw_interrupt_enable: + mtc0 a0, CP0_STATUS + jr ra + nop + +/* + * void rt_hw_context_switch(rt_uint32 from, rt_uint32 to) + * a0 --> from + * a1 --> to + */ + .globl rt_hw_context_switch +rt_hw_context_switch: + mtc0 ra, CP0_EPC + SAVE_ALL + + sw sp, 0(a0) /* store sp in preempted tasks TCB */ + lw sp, 0(a1) /* get new task stack pointer */ + + RESTORE_ALL_AND_RET + +/* + * void rt_hw_context_switch_to(rt_uint32 to)/* + * a0 --> to + */ + .globl rt_hw_context_switch_to +rt_hw_context_switch_to: + lw sp, 0(a0) /* get new task stack pointer */ + + RESTORE_ALL_AND_RET + +/* + * void rt_hw_context_switch_interrupt(rt_uint32 from, rt_uint32 to)/* + */ + .globl rt_thread_switch_interrupt_flag + .globl rt_interrupt_from_thread + .globl rt_interrupt_to_thread + .globl rt_hw_context_switch_interrupt +rt_hw_context_switch_interrupt: + la t0, rt_thread_switch_interrupt_flag + lw t1, 0(t0) + nop + bnez t1, _reswitch + nop + li t1, 0x01 /* set rt_thread_switch_interrupt_flag to 1 */ + sw t1, 0(t0) + la t0, rt_interrupt_from_thread /* set rt_interrupt_from_thread */ + sw a0, 0(t0) +_reswitch: + la t0, rt_interrupt_to_thread /* set rt_interrupt_to_thread */ + sw a1, 0(t0) + jr ra + nop + +/* + * void rt_hw_context_switch_interrupt_do(rt_base_t flag) + */ + .globl rt_interrupt_enter + .globl rt_interrupt_leave + .globl mips_irq_handle +mips_irq_handle: + SAVE_ALL + + mfc0 t0, CP0_CAUSE + and t1, t0, 0xff + bnez t1, spurious_interrupt /* check exception */ + nop + + /* let k0 keep the current context sp */ + move k0, sp + /* switch to kernel stack */ + li sp, SYSTEM_STACK + + jal rt_interrupt_enter + nop + jal rt_interrupt_dispatch + nop + jal rt_interrupt_leave + nop + + /* switch sp back to thread's context */ + move sp, k0 + + /* + * if rt_thread_switch_interrupt_flag set, jump to + * rt_hw_context_switch_interrupt_do and don't return + */ + la k0, rt_thread_switch_interrupt_flag + lw k1, 0(k0) + beqz k1, spurious_interrupt + nop + sw zero, 0(k0) /* clear flag */ + nop + + /* + * switch to the new thread + */ + la k0, rt_interrupt_from_thread + lw k1, 0(k0) + nop + sw sp, 0(k1) /* store sp in preempted tasks's TCB */ + + la k0, rt_interrupt_to_thread + lw k1, 0(k0) + nop + lw sp, 0(k1) /* get new task's stack pointer */ + j spurious_interrupt + nop + +spurious_interrupt: + RESTORE_ALL_AND_RET + + .set reorder diff --git a/libcpu/mips/loongson/cpu.c b/libcpu/mips/loongson/cpu.c index 49b310d01c..c459061f0a 100644 --- a/libcpu/mips/loongson/cpu.c +++ b/libcpu/mips/loongson/cpu.c @@ -1,50 +1,50 @@ -/*
- * File : cpu.c
- * This file is part of RT-Thread RTOS
- * COPYRIGHT (C) 2006 - 2010, RT-Thread Development Team
- *
- * The license and distribution terms for this file may be
- * found in the file LICENSE in this distribution or at
- * http://www.rt-thread.org/license/LICENSE
- *
- * Change Logs:
- * Date Author Notes
- * 2010-07-09 Bernard first version
- * 2010-09-11 Bernard add CPU reset implementation
- */
-#include <rtthread.h>
-#include <soc3210.h>
-
-/**
- * @addtogroup Loongson SoC3210
- */
-
-/*@{*/
-
-/**
- * this function will reset CPU
- *
- */
-void rt_hw_cpu_reset(void)
-{
- /* open the watch-dog */
- WD_TIMER = 0x01; /* watch dog will be timeout after 1 tick */
- WD_CTRL |= 0x01;
-
- rt_kprintf("reboot system...\n");
- while (1);
-}
-
-/**
- * this function will shutdown CPU
- *
- */
-void rt_hw_cpu_shutdown(void)
-{
- rt_kprintf("shutdown...\n");
-
- while (1);
-}
-
-/*@}*/
-
+/* + * File : cpu.c + * This file is part of RT-Thread RTOS + * COPYRIGHT (C) 2006 - 2010, RT-Thread Development Team + * + * The license and distribution terms for this file may be + * found in the file LICENSE in this distribution or at + * http://www.rt-thread.org/license/LICENSE + * + * Change Logs: + * Date Author Notes + * 2010-07-09 Bernard first version + * 2010-09-11 Bernard add CPU reset implementation + */ +#include <rtthread.h> +#include <soc3210.h> + +/** + * @addtogroup Loongson SoC3210 + */ + +/*@{*/ + +/** + * this function will reset CPU + * + */ +void rt_hw_cpu_reset(void) +{ + /* open the watch-dog */ + WD_TIMER = 0x01; /* watch dog will be timeout after 1 tick */ + WD_CTRL |= 0x01; + + rt_kprintf("reboot system...\n"); + while (1); +} + +/** + * this function will shutdown CPU + * + */ +void rt_hw_cpu_shutdown(void) +{ + rt_kprintf("shutdown...\n"); + + while (1); +} + +/*@}*/ + diff --git a/libcpu/mips/loongson/exception.c b/libcpu/mips/loongson/exception.c index 77d1414a29..1c6aec53ac 100644 --- a/libcpu/mips/loongson/exception.c +++ b/libcpu/mips/loongson/exception.c @@ -1,83 +1,83 @@ -/*
- * File : exception.c
- * Change Logs:
- * Date Author Notes
- * 2010-05-17 swkyer first version
- */
-#include <rtthread.h>
-#include <rthw.h>
-#include "../common/exception.h"
-#include "../common/mipsregs.h"
-
-/**
- * @addtogroup SoC3210
- */
-/*@{*/
-
-/**
- * exception handle table
- */
-#define RT_EXCEPTION_MAX 8
-exception_func_t sys_exception_handlers[RT_EXCEPTION_MAX];
-
-/**
- * setup the exception handle
- */
-exception_func_t rt_set_except_vector(int n, exception_func_t func)
-{
- exception_func_t old_handler = sys_exception_handlers[n];
-
- if ((n == 0) || (n > RT_EXCEPTION_MAX) || (!func))
- {
- return 0;
- }
-
- sys_exception_handlers[n] = func;
-
- return old_handler;
-}
-
-void tlb_refill_handler(void)
-{
- rt_kprintf("tlb-miss happens, epc: 0x%08x\n", read_c0_epc());
- rt_hw_cpu_shutdown();
-}
-
-void cache_error_handler(void)
-{
- rt_kprintf("cache exception happens, epc: 0x%08x\n", read_c0_epc());
- rt_hw_cpu_shutdown();
-}
-
-static void unhandled_exception_handle(pt_regs_t *regs)
-{
- rt_kprintf("exception happens, epc: 0x%08x, cause: 0x%08x\n", regs->cp0_epc, read_c0_cause());
-}
-
-void install_default_execpt_handle(void)
-{
- rt_int32_t i;
-
- for (i=0; i<RT_EXCEPTION_MAX; i++)
- sys_exception_handlers[i] = (exception_func_t)unhandled_exception_handle;
-}
-
-void exception_handler(pt_regs_t *regs)
-{
- rt_uint32_t cause;
- rt_uint32_t index;
-
- cause = (read_c0_cause() & read_c0_config());
- cause = (cause & 0xfc00) >> 8;
-
- for (index = RT_EXCEPTION_MAX; index > 0; index --)
- {
- if (cause & (1 << index))
- {
- sys_exception_handlers[index](regs);
- cause &= ~(1 << index);
- }
- }
-}
-
-/*@}*/
+/* + * File : exception.c + * Change Logs: + * Date Author Notes + * 2010-05-17 swkyer first version + */ +#include <rtthread.h> +#include <rthw.h> +#include "../common/exception.h" +#include "../common/mipsregs.h" + +/** + * @addtogroup SoC3210 + */ +/*@{*/ + +/** + * exception handle table + */ +#define RT_EXCEPTION_MAX 8 +exception_func_t sys_exception_handlers[RT_EXCEPTION_MAX]; + +/** + * setup the exception handle + */ +exception_func_t rt_set_except_vector(int n, exception_func_t func) +{ + exception_func_t old_handler = sys_exception_handlers[n]; + + if ((n == 0) || (n > RT_EXCEPTION_MAX) || (!func)) + { + return 0; + } + + sys_exception_handlers[n] = func; + + return old_handler; +} + +void tlb_refill_handler(void) +{ + rt_kprintf("tlb-miss happens, epc: 0x%08x\n", read_c0_epc()); + rt_hw_cpu_shutdown(); +} + +void cache_error_handler(void) +{ + rt_kprintf("cache exception happens, epc: 0x%08x\n", read_c0_epc()); + rt_hw_cpu_shutdown(); +} + +static void unhandled_exception_handle(pt_regs_t *regs) +{ + rt_kprintf("exception happens, epc: 0x%08x, cause: 0x%08x\n", regs->cp0_epc, read_c0_cause()); +} + +void install_default_execpt_handle(void) +{ + rt_int32_t i; + + for (i=0; i<RT_EXCEPTION_MAX; i++) + sys_exception_handlers[i] = (exception_func_t)unhandled_exception_handle; +} + +void exception_handler(pt_regs_t *regs) +{ + rt_uint32_t cause; + rt_uint32_t index; + + cause = (read_c0_cause() & read_c0_config()); + cause = (cause & 0xfc00) >> 8; + + for (index = RT_EXCEPTION_MAX; index > 0; index --) + { + if (cause & (1 << index)) + { + sys_exception_handlers[index](regs); + cause &= ~(1 << index); + } + } +} + +/*@}*/ diff --git a/libcpu/mips/loongson/interrupt.c b/libcpu/mips/loongson/interrupt.c index d70b58da97..4b97068a70 100644 --- a/libcpu/mips/loongson/interrupt.c +++ b/libcpu/mips/loongson/interrupt.c @@ -1,130 +1,130 @@ -/*
- * File : interrupt.c
- * This file is part of RT-Thread RTOS
- * COPYRIGHT (C) 2006 - 2010, RT-Thread Development Team
- *
- * The license and distribution terms for this file may be
- * found in the file LICENSE in this distribution or at
- * http://www.rt-thread.org/license/LICENSE
- *
- * Change Logs:
- * Date Author Notes
- * 2010-10-15 Bernard first version
- */
-#include <rtthread.h>
-#include "soc3210.h"
-
-#define MAX_INTR 32
-
-extern rt_uint32_t rt_interrupt_nest;
-rt_uint32_t rt_interrupt_from_thread, rt_interrupt_to_thread;
-rt_uint32_t rt_thread_switch_interrupt_flag;
-
-static rt_isr_handler_t irq_handle_table[MAX_INTR];
-void rt_interrupt_dispatch(void *ptreg);
-void rt_hw_timer_handler();
-
-/**
- * @addtogroup Loongson SoC3210
- */
-
-/*@{*/
-
-void rt_hw_interrupt_handler(int vector)
-{
- rt_kprintf("Unhandled interrupt %d occured!!!\n", vector);
-}
-
-/**
- * This function will initialize hardware interrupt
- */
-void rt_hw_interrupt_init(void)
-{
- rt_int32_t index;
-
- for (index = 0; index < MAX_INTR; index ++)
- {
- irq_handle_table[index] = (rt_isr_handler_t)rt_hw_interrupt_handler;
- }
-
- /* init interrupt nest, and context in thread sp */
- rt_interrupt_nest = 0;
- rt_interrupt_from_thread = 0;
- rt_interrupt_to_thread = 0;
- rt_thread_switch_interrupt_flag = 0;
-}
-
-/**
- * This function will mask a interrupt.
- * @param vector the interrupt number
- */
-void rt_hw_interrupt_mask(int vector)
-{
- /* mask interrupt */
- INT_EN &= ~(1 << vector);
-}
-
-/**
- * This function will un-mask a interrupt.
- * @param vector the interrupt number
- */
-void rt_hw_interrupt_umask(int vector)
-{
- INT_EN |= (1 << vector);
-}
-
-/**
- * This function will install a interrupt service routine to a interrupt.
- * @param vector the interrupt number
- * @param new_handler the interrupt service routine to be installed
- * @param old_handler the old interrupt service routine
- */
-void rt_hw_interrupt_install(int vector, rt_isr_handler_t new_handler, rt_isr_handler_t *old_handler)
-{
- if (vector >= 0 && vector < MAX_INTR)
- {
- if (old_handler != RT_NULL)
- *old_handler = irq_handle_table[vector];
- if (new_handler != RT_NULL)
- irq_handle_table[vector] = (rt_isr_handler_t)new_handler;
- }
-}
-
-void rt_interrupt_dispatch(void *ptreg)
-{
- int i;
- rt_isr_handler_t irq_func;
- static rt_uint32_t status = 0;
- rt_uint32_t c0_status;
-
- /* check os timer */
- c0_status = read_c0_status();
- if (c0_status & 0x8000)
- {
- rt_hw_timer_handler();
- }
-
- if (c0_status & 0x0400)
- {
- /* the hardware interrupt */
- status |= INT_ISR;
- if (!status) return;
-
- for (i = MAX_INTR; i > 0; --i)
- {
- if ((status & (1<<i)))
- {
- status &= ~(1<<i);
- irq_func = irq_handle_table[i];
-
- /* do interrupt */
- (*irq_func)(i);
-
- /* ack interrupt */
- INT_CLR = (1 << i);
- }
- }
- }
-}
-
-/*@}*/
+/* + * File : interrupt.c + * This file is part of RT-Thread RTOS + * COPYRIGHT (C) 2006 - 2010, RT-Thread Development Team + * + * The license and distribution terms for this file may be + * found in the file LICENSE in this distribution or at + * http://www.rt-thread.org/license/LICENSE + * + * Change Logs: + * Date Author Notes + * 2010-10-15 Bernard first version + */ +#include <rtthread.h> +#include "soc3210.h" + +#define MAX_INTR 32 + +extern rt_uint32_t rt_interrupt_nest; +rt_uint32_t rt_interrupt_from_thread, rt_interrupt_to_thread; +rt_uint32_t rt_thread_switch_interrupt_flag; + +static rt_isr_handler_t irq_handle_table[MAX_INTR]; +void rt_interrupt_dispatch(void *ptreg); +void rt_hw_timer_handler(); + +/** + * @addtogroup Loongson SoC3210 + */ + +/*@{*/ + +void rt_hw_interrupt_handler(int vector) +{ + rt_kprintf("Unhandled interrupt %d occured!!!\n", vector); +} + +/** + * This function will initialize hardware interrupt + */ +void rt_hw_interrupt_init(void) +{ + rt_int32_t index; + + for (index = 0; index < MAX_INTR; index ++) + { + irq_handle_table[index] = (rt_isr_handler_t)rt_hw_interrupt_handler; + } + + /* init interrupt nest, and context in thread sp */ + rt_interrupt_nest = 0; + rt_interrupt_from_thread = 0; + rt_interrupt_to_thread = 0; + rt_thread_switch_interrupt_flag = 0; +} + +/** + * This function will mask a interrupt. + * @param vector the interrupt number + */ +void rt_hw_interrupt_mask(int vector) +{ + /* mask interrupt */ + INT_EN &= ~(1 << vector); +} + +/** + * This function will un-mask a interrupt. + * @param vector the interrupt number + */ +void rt_hw_interrupt_umask(int vector) +{ + INT_EN |= (1 << vector); +} + +/** + * This function will install a interrupt service routine to a interrupt. + * @param vector the interrupt number + * @param new_handler the interrupt service routine to be installed + * @param old_handler the old interrupt service routine + */ +void rt_hw_interrupt_install(int vector, rt_isr_handler_t new_handler, rt_isr_handler_t *old_handler) +{ + if (vector >= 0 && vector < MAX_INTR) + { + if (old_handler != RT_NULL) + *old_handler = irq_handle_table[vector]; + if (new_handler != RT_NULL) + irq_handle_table[vector] = (rt_isr_handler_t)new_handler; + } +} + +void rt_interrupt_dispatch(void *ptreg) +{ + int i; + rt_isr_handler_t irq_func; + static rt_uint32_t status = 0; + rt_uint32_t c0_status; + + /* check os timer */ + c0_status = read_c0_status(); + if (c0_status & 0x8000) + { + rt_hw_timer_handler(); + } + + if (c0_status & 0x0400) + { + /* the hardware interrupt */ + status |= INT_ISR; + if (!status) return; + + for (i = MAX_INTR; i > 0; --i) + { + if ((status & (1<<i))) + { + status &= ~(1<<i); + irq_func = irq_handle_table[i]; + + /* do interrupt */ + (*irq_func)(i); + + /* ack interrupt */ + INT_CLR = (1 << i); + } + } + } +} + +/*@}*/ diff --git a/libcpu/mips/loongson/mipscfg.c b/libcpu/mips/loongson/mipscfg.c index 89bb321c8c..8a96f458ab 100644 --- a/libcpu/mips/loongson/mipscfg.c +++ b/libcpu/mips/loongson/mipscfg.c @@ -1,82 +1,82 @@ -/*
- * File : mipscfg.c
- * This file is part of RT-Thread RTOS
- * COPYRIGHT (C) 2010, RT-Thread Development Team
- *
- * The license and distribution terms for this file may be
- * found in the file LICENSE in this distribution or at
- * http://www.rt-thread.org/license/LICENSE
- *
- * Change Logs:
- * Date Author Notes
- * 2010-05-27 swkyer first version
- */
-#include <rtthread.h>
-#include "../common/mipsregs.h"
-#include "../common/mipscfg.h"
-
-mips32_core_cfg_t g_mips_core =
-{
- 16, /* icache_line_size */
- 256, /* icache_lines_per_way */
- 4, /* icache_ways */
- 16, /* dcache_line_size */
- 256, /* dcache_lines_per_way */
- 4, /* dcache_ways */
- 16, /* max_tlb_entries */
-};
-
-static rt_uint16_t m_pow(rt_uint16_t b, rt_uint16_t n)
-{
- rt_uint16_t rets = 1;
-
- while (n--)
- rets *= b;
-
- return rets;
-}
-
-static rt_uint16_t m_log2(rt_uint16_t b)
-{
- rt_uint16_t rets = 0;
-
- while (b != 1)
- {
- b /= 2;
- rets++;
- }
-
- return rets;
-}
-
-/**
+/* + * File : mipscfg.c + * This file is part of RT-Thread RTOS + * COPYRIGHT (C) 2010, RT-Thread Development Team + * + * The license and distribution terms for this file may be + * found in the file LICENSE in this distribution or at + * http://www.rt-thread.org/license/LICENSE + * + * Change Logs: + * Date Author Notes + * 2010-05-27 swkyer first version + */ +#include <rtthread.h> +#include "../common/mipsregs.h" +#include "../common/mipscfg.h" + +mips32_core_cfg_t g_mips_core = +{ + 16, /* icache_line_size */ + 256, /* icache_lines_per_way */ + 4, /* icache_ways */ + 16, /* dcache_line_size */ + 256, /* dcache_lines_per_way */ + 4, /* dcache_ways */ + 16, /* max_tlb_entries */ +}; + +static rt_uint16_t m_pow(rt_uint16_t b, rt_uint16_t n) +{ + rt_uint16_t rets = 1; + + while (n--) + rets *= b; + + return rets; +} + +static rt_uint16_t m_log2(rt_uint16_t b) +{ + rt_uint16_t rets = 0; + + while (b != 1) + { + b /= 2; + rets++; + } + + return rets; +} + +/** * read core attribute - */
-void mips32_cfg_init(void)
-{
- rt_uint16_t val;
- rt_uint32_t cp0_config1;
-
- cp0_config1 = read_c0_config();
- if (cp0_config1 & 0x80000000)
- {
- cp0_config1 = read_c0_config1();
-
- val = (cp0_config1 & (7<<22))>>22;
- g_mips_core.icache_lines_per_way = 64 * m_pow(2, val);
- val = (cp0_config1 & (7<<19))>>19;
- g_mips_core.icache_line_size = 2 * m_pow(2, val);
- val = (cp0_config1 & (7<<16))>>16;
- g_mips_core.icache_ways = val + 1;
-
- val = (cp0_config1 & (7<<13))>>13;
- g_mips_core.dcache_lines_per_way = 64 * m_pow(2, val);
- val = (cp0_config1 & (7<<10))>>10;
- g_mips_core.dcache_line_size = 2 * m_pow(2, val);
- val = (cp0_config1 & (7<<7))>>7;
- g_mips_core.dcache_ways = val + 1;
-
- val = (cp0_config1 & (0x3F<<25))>>25;
- g_mips_core.max_tlb_entries = val + 1;
- }
-}
+ */ +void mips32_cfg_init(void) +{ + rt_uint16_t val; + rt_uint32_t cp0_config1; + + cp0_config1 = read_c0_config(); + if (cp0_config1 & 0x80000000) + { + cp0_config1 = read_c0_config1(); + + val = (cp0_config1 & (7<<22))>>22; + g_mips_core.icache_lines_per_way = 64 * m_pow(2, val); + val = (cp0_config1 & (7<<19))>>19; + g_mips_core.icache_line_size = 2 * m_pow(2, val); + val = (cp0_config1 & (7<<16))>>16; + g_mips_core.icache_ways = val + 1; + + val = (cp0_config1 & (7<<13))>>13; + g_mips_core.dcache_lines_per_way = 64 * m_pow(2, val); + val = (cp0_config1 & (7<<10))>>10; + g_mips_core.dcache_line_size = 2 * m_pow(2, val); + val = (cp0_config1 & (7<<7))>>7; + g_mips_core.dcache_ways = val + 1; + + val = (cp0_config1 & (0x3F<<25))>>25; + g_mips_core.max_tlb_entries = val + 1; + } +} diff --git a/libcpu/mips/loongson/soc3210.h b/libcpu/mips/loongson/soc3210.h index fe394ce012..c4d2c3926f 100644 --- a/libcpu/mips/loongson/soc3210.h +++ b/libcpu/mips/loongson/soc3210.h @@ -1,172 +1,172 @@ -#ifndef __SOC3210_H__
-#define __SOC3210_H__
-
-#include "../common/mipsregs.h"
-
-/* registers */
-#define __REG8(addr) *((volatile unsigned char *)(addr))
-#define __REG16(addr) *((volatile unsigned short *)(addr))
-#define __REG32(addr) *((volatile unsigned int *)(addr))
-
-#define EMI_BASE 0xBF000000
-#define NN_BASE 0xBF000040
-#define LCD_BASE 0xBF001000
-#define HSB_MISC_BASE 0xBF003200
-#define SPI_BASE 0xBF004000
-#define PS2_BASE 0xBF004040
-#define UART0_BASE 0xBF004080
-#define UART1_BASE 0xBF004090
-#define I2C_BASE 0xBF0040D0
-#define LPB_MISC_BASE 0xBF004100
-#define AC97_BASE 0xBF004200
-#define AC97_DMA_BASE 0xBF004280
-#define CAN1_BASE 0xBF004300
-#define CAN0_BASE 0xBF004400
-#define MAC0_BASE 0xBF005200
-#define MAC1_BASE 0xBF005300
-
-/* LCD registers */
-#define LCD_CTRL __REG32(LCD_BASE + 0x000)
-#define LCD_STAT __REG32(LCD_BASE + 0x004)
-#define LCD_HTIM __REG32(LCD_BASE + 0x008)
-#define LCD_VTIM __REG32(LCD_BASE + 0x00C)
-#define LCD_HVLEN __REG32(LCD_BASE + 0x010)
-#define LCD_VBARA __REG32(LCD_BASE + 0x014)
-#define LCD_VBARB __REG32(LCD_BASE + 0x018)
-#define LCD_PCLT __REG32(LCD_BASE + 0x800)
-
-/* HSB misc registers */
-#define HSB_MISC_REG __REG32(HSB_MISC_BASE + 0x00)
-#define INT_EDGE __REG32(HSB_MISC_BASE + 0x04)
-#define INT_STEER __REG32(HSB_MISC_BASE + 0x08)
-#define INT_POL __REG32(HSB_MISC_BASE + 0x0C)
-#define INT_SET __REG32(HSB_MISC_BASE + 0x10)
-#define INT_CLR __REG32(HSB_MISC_BASE + 0x14)
-#define INT_EN __REG32(HSB_MISC_BASE + 0x18)
-#define INT_ISR __REG32(HSB_MISC_BASE + 0x1C)
-#define GPIO_OE_60_29 __REG32(HSB_MISC_BASE + 0x20)
-#define GPIO_I_60_29 __REG32(HSB_MISC_BASE + 0x24)
-#define GPIO_O_60_29 __REG32(HSB_MISC_BASE + 0x28)
-#define HSB_ARB_CFG __REG32(HSB_MISC_BASE + 0x2C)
-#define WD_TIMER __REG32(HSB_MISC_BASE + 0x30)
-#define WD_CTRL __REG32(HSB_MISC_BASE + 0x34)
-
-/* SPI registers */
-#define SPI_SPCR __REG8(SPI_BASE + 0x00)
-#define SPI_SPSR __REG8(SPI_BASE + 0x01)
-#define SPI_TX_FIFO __REG8(SPI_BASE + 0x02)
-#define SPI_SPER __REG8(SPI_BASE + 0x03)
-
-/* PS/2 registers */
-#define PS2_RIBUF __REG8(PS2_BASE + 0x00)
-#define PS2_WOBUF __REG8(PS2_BASE + 0x00)
-#define PS2_RSR __REG8(PS2_BASE + 0x04)
-#define PS2_WSC __REG8(PS2_BASE + 0x04)
-#define PS2_DLL __REG8(PS2_BASE + 0x08)
-#define PS2_DLH __REG8(PS2_BASE + 0x09)
-#define PS2_DL_KBD __REG8(PS2_BASE + 0x0A)
-#define PS2_DL_AUX __REG8(PS2_BASE + 0x0B)
-
-/* UART registers */
-#define UART_DAT(base) __REG8(base + 0x00)
-#define UART_IER(base) __REG8(base + 0x01)
-#define UART_IIR(base) __REG8(base + 0x02)
-#define UART_FCR(base) __REG8(base + 0x02)
-#define UART_LCR(base) __REG8(base + 0x03)
-#define UART_MCR(base) __REG8(base + 0x04)
-#define UART_LSR(base) __REG8(base + 0x05)
-#define UART_MSR(base) __REG8(base + 0x06)
-
-#define UART_LSB(base) __REG8(base + 0x00)
-#define UART_MSB(base) __REG8(base + 0x01)
-
-/* UART0 registers */
-#define UART0_DAT __REG8(UART0_BASE + 0x00)
-#define UART0_IER __REG8(UART0_BASE + 0x01)
-#define UART0_IIR __REG8(UART0_BASE + 0x02)
-#define UART0_FCR __REG8(UART0_BASE + 0x02)
-#define UART0_LCR __REG8(UART0_BASE + 0x03)
-#define UART0_MCR __REG8(UART0_BASE + 0x04)
-#define UART0_LSR __REG8(UART0_BASE + 0x05)
-#define UART0_MSR __REG8(UART0_BASE + 0x06)
-
-#define UART0_LSB __REG8(UART0_BASE + 0x00)
-#define UART0_MSB __REG8(UART0_BASE + 0x01)
-
-/* UART1 registers */
-#define UART1_DAT __REG8(UART1_BASE + 0x00)
-#define UART1_IER __REG8(UART1_BASE + 0x01)
-#define UART1_IIR __REG8(UART1_BASE + 0x02)
-#define UART1_FCR __REG8(UART1_BASE + 0x02)
-#define UART1_LCR __REG8(UART1_BASE + 0x03)
-#define UART1_MCR __REG8(UART1_BASE + 0x04)
-#define UART1_LSR __REG8(UART1_BASE + 0x05)
-#define UART1_MSR __REG8(UART1_BASE + 0x06)
-
-#define UART1_LSB __REG8(UART1_BASE + 0x00)
-#define UART1_MSB __REG8(UART1_BASE + 0x01)
-
-/* LPB misc registers */
-#define GPIO_OE_7_0 __REG8(LPB_MISC_BASE + 0x00)
-#define GPIO_OE_15_8 __REG8(LPB_MISC_BASE + 0x01)
-#define GPIO_OE_23_16 __REG8(LPB_MISC_BASE + 0x02)
-#define GPIO_OE_28_24 __REG8(LPB_MISC_BASE + 0x03)
-#define GPIO_I_7_0 __REG8(LPB_MISC_BASE + 0x10)
-#define GPIO_I_15_8 __REG8(LPB_MISC_BASE + 0x11)
-#define GPIO_I_23_16 __REG8(LPB_MISC_BASE + 0x12)
-#define GPIO_I_28_24 __REG8(LPB_MISC_BASE + 0x13)
-#define GPIO_O_7_0 __REG8(LPB_MISC_BASE + 0x20)
-#define GPIO_O_15_8 __REG8(LPB_MISC_BASE + 0x21)
-#define GPIO_O_23_16 __REG8(LPB_MISC_BASE + 0x22)
-#define GPIO_O_28_24 __REG8(LPB_MISC_BASE + 0x23)
-#define LPB_MISC_CFG __REG8(LPB_MISC_BASE + 0x40)
-
-/* MAC0 registers */
-#define MAC0_BUS_MODE __REG32(MAC0_BASE + 0x00)
-#define MAC0_TX_POLL_REQ __REG32(MAC0_BASE + 0x08)
-#define MAC0_RX_POLL_REQ __REG32(MAC0_BASE + 0x10)
-#define MAC0_RX_LIST_BASE_ADDR __REG32(MAC0_BASE + 0x18)
-#define MAC0_TX_LIST_BASE_ADDR __REG32(MAC0_BASE + 0x20)
-#define MAC0_STATUS __REG32(MAC0_BASE + 0x28)
-#define MAC0_OP_MODE __REG32(MAC0_BASE + 0x30)
-#define MAC0_INTERRUPT_EN __REG32(MAC0_BASE + 0x38)
-#define MAC0_MISSED_FRAME_STATISTIC __REG32(MAC0_BASE + 0x40)
-#define MAC0_SMI_EEPROM_CTL __REG32(MAC0_BASE + 0x48)
-#define MAC0_BYTE_ALIGN __REG32(MAC0_BASE + 0x50)
-#define MAC0_GPT_IM_CTL __REG32(MAC0_BASE + 0x58)
-
-/* MAC1 registers */
-#define MAC1_BUS_MODE __REG32(MAC1_BASE + 0x00)
-#define MAC1_TX_POLL_REQ __REG32(MAC1_BASE + 0x08)
-#define MAC1_RX_POLL_REQ __REG32(MAC1_BASE + 0x10)
-#define MAC1_RX_LIST_BASE_ADDR __REG32(MAC1_BASE + 0x18)
-#define MAC1_TX_LIST_BASE_ADDR __REG32(MAC1_BASE + 0x20)
-#define MAC1_STATUS __REG32(MAC1_BASE + 0x28)
-#define MAC1_OP_MODE __REG32(MAC1_BASE + 0x30)
-#define MAC1_INTERRUPT_EN __REG32(MAC1_BASE + 0x38)
-#define MAC1_MISSED_FRAME_STATISTIC __REG32(MAC1_BASE + 0x40)
-#define MAC1_SMI_EEPROM_CTL __REG32(MAC1_BASE + 0x48)
-#define MAC1_BYTE_ALIGN __REG32(MAC1_BASE + 0x50)
-#define MAC1_GPT_IM_CTL __REG32(MAC1_BASE + 0x58)
-
-/* Peripheral Interrupt Number */
-#define IRQ_LCD 0
-#define IRQ_MAC1 1
-#define IRQ_MAC2 2
-#define IRQ_AC97 3
-#define IRQ_SPI 8
-#define IRQ_KEY 9
-#define IRQ_MOUSE 10
-#define IRQ_UART0 11
-#define IRQ_UART1 12
-#define IRQ_I2C 13
-#define IRQ_CAN0 14
-#define IRQ_CAN1 15
-#define IRQ_GPIO15 20
-#define IRQ_GPIO14 21
-#define IRQ_GPIO13 22
-#define IRQ_GPIO12 23
-
-#define SYSTEM_STACK 0x80003fe8 /* the kernel system stack address */
-
-#endif
+#ifndef __SOC3210_H__ +#define __SOC3210_H__ + +#include "../common/mipsregs.h" + +/* registers */ +#define __REG8(addr) *((volatile unsigned char *)(addr)) +#define __REG16(addr) *((volatile unsigned short *)(addr)) +#define __REG32(addr) *((volatile unsigned int *)(addr)) + +#define EMI_BASE 0xBF000000 +#define NN_BASE 0xBF000040 +#define LCD_BASE 0xBF001000 +#define HSB_MISC_BASE 0xBF003200 +#define SPI_BASE 0xBF004000 +#define PS2_BASE 0xBF004040 +#define UART0_BASE 0xBF004080 +#define UART1_BASE 0xBF004090 +#define I2C_BASE 0xBF0040D0 +#define LPB_MISC_BASE 0xBF004100 +#define AC97_BASE 0xBF004200 +#define AC97_DMA_BASE 0xBF004280 +#define CAN1_BASE 0xBF004300 +#define CAN0_BASE 0xBF004400 +#define MAC0_BASE 0xBF005200 +#define MAC1_BASE 0xBF005300 + +/* LCD registers */ +#define LCD_CTRL __REG32(LCD_BASE + 0x000) +#define LCD_STAT __REG32(LCD_BASE + 0x004) +#define LCD_HTIM __REG32(LCD_BASE + 0x008) +#define LCD_VTIM __REG32(LCD_BASE + 0x00C) +#define LCD_HVLEN __REG32(LCD_BASE + 0x010) +#define LCD_VBARA __REG32(LCD_BASE + 0x014) +#define LCD_VBARB __REG32(LCD_BASE + 0x018) +#define LCD_PCLT __REG32(LCD_BASE + 0x800) + +/* HSB misc registers */ +#define HSB_MISC_REG __REG32(HSB_MISC_BASE + 0x00) +#define INT_EDGE __REG32(HSB_MISC_BASE + 0x04) +#define INT_STEER __REG32(HSB_MISC_BASE + 0x08) +#define INT_POL __REG32(HSB_MISC_BASE + 0x0C) +#define INT_SET __REG32(HSB_MISC_BASE + 0x10) +#define INT_CLR __REG32(HSB_MISC_BASE + 0x14) +#define INT_EN __REG32(HSB_MISC_BASE + 0x18) +#define INT_ISR __REG32(HSB_MISC_BASE + 0x1C) +#define GPIO_OE_60_29 __REG32(HSB_MISC_BASE + 0x20) +#define GPIO_I_60_29 __REG32(HSB_MISC_BASE + 0x24) +#define GPIO_O_60_29 __REG32(HSB_MISC_BASE + 0x28) +#define HSB_ARB_CFG __REG32(HSB_MISC_BASE + 0x2C) +#define WD_TIMER __REG32(HSB_MISC_BASE + 0x30) +#define WD_CTRL __REG32(HSB_MISC_BASE + 0x34) + +/* SPI registers */ +#define SPI_SPCR __REG8(SPI_BASE + 0x00) +#define SPI_SPSR __REG8(SPI_BASE + 0x01) +#define SPI_TX_FIFO __REG8(SPI_BASE + 0x02) +#define SPI_SPER __REG8(SPI_BASE + 0x03) + +/* PS/2 registers */ +#define PS2_RIBUF __REG8(PS2_BASE + 0x00) +#define PS2_WOBUF __REG8(PS2_BASE + 0x00) +#define PS2_RSR __REG8(PS2_BASE + 0x04) +#define PS2_WSC __REG8(PS2_BASE + 0x04) +#define PS2_DLL __REG8(PS2_BASE + 0x08) +#define PS2_DLH __REG8(PS2_BASE + 0x09) +#define PS2_DL_KBD __REG8(PS2_BASE + 0x0A) +#define PS2_DL_AUX __REG8(PS2_BASE + 0x0B) + +/* UART registers */ +#define UART_DAT(base) __REG8(base + 0x00) +#define UART_IER(base) __REG8(base + 0x01) +#define UART_IIR(base) __REG8(base + 0x02) +#define UART_FCR(base) __REG8(base + 0x02) +#define UART_LCR(base) __REG8(base + 0x03) +#define UART_MCR(base) __REG8(base + 0x04) +#define UART_LSR(base) __REG8(base + 0x05) +#define UART_MSR(base) __REG8(base + 0x06) + +#define UART_LSB(base) __REG8(base + 0x00) +#define UART_MSB(base) __REG8(base + 0x01) + +/* UART0 registers */ +#define UART0_DAT __REG8(UART0_BASE + 0x00) +#define UART0_IER __REG8(UART0_BASE + 0x01) +#define UART0_IIR __REG8(UART0_BASE + 0x02) +#define UART0_FCR __REG8(UART0_BASE + 0x02) +#define UART0_LCR __REG8(UART0_BASE + 0x03) +#define UART0_MCR __REG8(UART0_BASE + 0x04) +#define UART0_LSR __REG8(UART0_BASE + 0x05) +#define UART0_MSR __REG8(UART0_BASE + 0x06) + +#define UART0_LSB __REG8(UART0_BASE + 0x00) +#define UART0_MSB __REG8(UART0_BASE + 0x01) + +/* UART1 registers */ +#define UART1_DAT __REG8(UART1_BASE + 0x00) +#define UART1_IER __REG8(UART1_BASE + 0x01) +#define UART1_IIR __REG8(UART1_BASE + 0x02) +#define UART1_FCR __REG8(UART1_BASE + 0x02) +#define UART1_LCR __REG8(UART1_BASE + 0x03) +#define UART1_MCR __REG8(UART1_BASE + 0x04) +#define UART1_LSR __REG8(UART1_BASE + 0x05) +#define UART1_MSR __REG8(UART1_BASE + 0x06) + +#define UART1_LSB __REG8(UART1_BASE + 0x00) +#define UART1_MSB __REG8(UART1_BASE + 0x01) + +/* LPB misc registers */ +#define GPIO_OE_7_0 __REG8(LPB_MISC_BASE + 0x00) +#define GPIO_OE_15_8 __REG8(LPB_MISC_BASE + 0x01) +#define GPIO_OE_23_16 __REG8(LPB_MISC_BASE + 0x02) +#define GPIO_OE_28_24 __REG8(LPB_MISC_BASE + 0x03) +#define GPIO_I_7_0 __REG8(LPB_MISC_BASE + 0x10) +#define GPIO_I_15_8 __REG8(LPB_MISC_BASE + 0x11) +#define GPIO_I_23_16 __REG8(LPB_MISC_BASE + 0x12) +#define GPIO_I_28_24 __REG8(LPB_MISC_BASE + 0x13) +#define GPIO_O_7_0 __REG8(LPB_MISC_BASE + 0x20) +#define GPIO_O_15_8 __REG8(LPB_MISC_BASE + 0x21) +#define GPIO_O_23_16 __REG8(LPB_MISC_BASE + 0x22) +#define GPIO_O_28_24 __REG8(LPB_MISC_BASE + 0x23) +#define LPB_MISC_CFG __REG8(LPB_MISC_BASE + 0x40) + +/* MAC0 registers */ +#define MAC0_BUS_MODE __REG32(MAC0_BASE + 0x00) +#define MAC0_TX_POLL_REQ __REG32(MAC0_BASE + 0x08) +#define MAC0_RX_POLL_REQ __REG32(MAC0_BASE + 0x10) +#define MAC0_RX_LIST_BASE_ADDR __REG32(MAC0_BASE + 0x18) +#define MAC0_TX_LIST_BASE_ADDR __REG32(MAC0_BASE + 0x20) +#define MAC0_STATUS __REG32(MAC0_BASE + 0x28) +#define MAC0_OP_MODE __REG32(MAC0_BASE + 0x30) +#define MAC0_INTERRUPT_EN __REG32(MAC0_BASE + 0x38) +#define MAC0_MISSED_FRAME_STATISTIC __REG32(MAC0_BASE + 0x40) +#define MAC0_SMI_EEPROM_CTL __REG32(MAC0_BASE + 0x48) +#define MAC0_BYTE_ALIGN __REG32(MAC0_BASE + 0x50) +#define MAC0_GPT_IM_CTL __REG32(MAC0_BASE + 0x58) + +/* MAC1 registers */ +#define MAC1_BUS_MODE __REG32(MAC1_BASE + 0x00) +#define MAC1_TX_POLL_REQ __REG32(MAC1_BASE + 0x08) +#define MAC1_RX_POLL_REQ __REG32(MAC1_BASE + 0x10) +#define MAC1_RX_LIST_BASE_ADDR __REG32(MAC1_BASE + 0x18) +#define MAC1_TX_LIST_BASE_ADDR __REG32(MAC1_BASE + 0x20) +#define MAC1_STATUS __REG32(MAC1_BASE + 0x28) +#define MAC1_OP_MODE __REG32(MAC1_BASE + 0x30) +#define MAC1_INTERRUPT_EN __REG32(MAC1_BASE + 0x38) +#define MAC1_MISSED_FRAME_STATISTIC __REG32(MAC1_BASE + 0x40) +#define MAC1_SMI_EEPROM_CTL __REG32(MAC1_BASE + 0x48) +#define MAC1_BYTE_ALIGN __REG32(MAC1_BASE + 0x50) +#define MAC1_GPT_IM_CTL __REG32(MAC1_BASE + 0x58) + +/* Peripheral Interrupt Number */ +#define IRQ_LCD 0 +#define IRQ_MAC1 1 +#define IRQ_MAC2 2 +#define IRQ_AC97 3 +#define IRQ_SPI 8 +#define IRQ_KEY 9 +#define IRQ_MOUSE 10 +#define IRQ_UART0 11 +#define IRQ_UART1 12 +#define IRQ_I2C 13 +#define IRQ_CAN0 14 +#define IRQ_CAN1 15 +#define IRQ_GPIO15 20 +#define IRQ_GPIO14 21 +#define IRQ_GPIO13 22 +#define IRQ_GPIO12 23 + +#define SYSTEM_STACK 0x80003fe8 /* the kernel system stack address */ + +#endif diff --git a/libcpu/mips/loongson/stack.c b/libcpu/mips/loongson/stack.c index 60e9aa4fb4..dbfcf7ea91 100644 --- a/libcpu/mips/loongson/stack.c +++ b/libcpu/mips/loongson/stack.c @@ -1,96 +1,96 @@ -/*
- * File : stack.c
- * This file is part of RT-Thread RTOS
- * COPYRIGHT (C) 2006, RT-Thread Development Team
- *
- * The license and distribution terms for this file may be
- * found in the file LICENSE in this distribution or at
- * http://www.rt-thread.org/license/LICENSE
- *
- * Change Logs:
- * Date Author Notes
- * 2010-05-17 swkyer first version
- * 2010-07-07 Bernard porting to Jz47xx
- */
-
-#include <rtthread.h>
-
-/**
- * @addtogroup Loongson SoC3210
- */
-
-/*@{*/
-
-extern rt_uint32_t cp0_get_cause(void);
-extern rt_uint32_t cp0_get_status(void);
-extern rt_uint32_t cp0_get_hi(void);
-extern rt_uint32_t cp0_get_lo(void);
-
-/**
- * This function will initialize thread stack
- *
- * @param tentry the entry of thread
- * @param parameter the parameter of entry
- * @param stack_addr the beginning stack address
- * @param texit the function will be called when thread exit
- *
- * @return stack address
- */
-rt_uint8_t *rt_hw_stack_init(void *tentry, void *parameter, rt_uint8_t *stack_addr, void *texit)
-{
- rt_uint32_t *stk;
- static rt_uint32_t g_sr = 0;
-
- if (g_sr == 0)
- {
- g_sr = cp0_get_status();
- g_sr &= 0xfffffffe;
- g_sr |= 0x8401;
- }
-
- /** Start at stack top */
- stk = (rt_uint32_t *)stack_addr;
- *(stk) = (rt_uint32_t) tentry; /* pc: Entry Point */
- *(--stk) = (rt_uint32_t) 0xeeee; /* c0_cause */
- *(--stk) = (rt_uint32_t) 0xffff; /* c0_badvaddr */
- *(--stk) = (rt_uint32_t) cp0_get_lo(); /* lo */
- *(--stk) = (rt_uint32_t) cp0_get_hi(); /* hi */
- *(--stk) = (rt_uint32_t) g_sr; /* C0_SR: HW2 = En, IE = En */
- *(--stk) = (rt_uint32_t) texit; /* ra */
- *(--stk) = (rt_uint32_t) 0x0000001e; /* s8 */
- *(--stk) = (rt_uint32_t) stack_addr; /* sp */
- *(--stk) = (rt_uint32_t) 0x0000001c; /* gp */
- *(--stk) = (rt_uint32_t) 0x0000001b; /* k1 */
- *(--stk) = (rt_uint32_t) 0x0000001a; /* k0 */
- *(--stk) = (rt_uint32_t) 0x00000019; /* t9 */
- *(--stk) = (rt_uint32_t) 0x00000018; /* t8 */
- *(--stk) = (rt_uint32_t) 0x00000017; /* s7 */
- *(--stk) = (rt_uint32_t) 0x00000016; /* s6 */
- *(--stk) = (rt_uint32_t) 0x00000015; /* s5 */
- *(--stk) = (rt_uint32_t) 0x00000014; /* s4 */
- *(--stk) = (rt_uint32_t) 0x00000013; /* s3 */
- *(--stk) = (rt_uint32_t) 0x00000012; /* s2 */
- *(--stk) = (rt_uint32_t) 0x00000011; /* s1 */
- *(--stk) = (rt_uint32_t) 0x00000010; /* s0 */
- *(--stk) = (rt_uint32_t) 0x0000000f; /* t7 */
- *(--stk) = (rt_uint32_t) 0x0000000e; /* t6 */
- *(--stk) = (rt_uint32_t) 0x0000000d; /* t5 */
- *(--stk) = (rt_uint32_t) 0x0000000c; /* t4 */
- *(--stk) = (rt_uint32_t) 0x0000000b; /* t3 */
- *(--stk) = (rt_uint32_t) 0x0000000a; /* t2 */
- *(--stk) = (rt_uint32_t) 0x00000009; /* t1 */
- *(--stk) = (rt_uint32_t) 0x00000008; /* t0 */
- *(--stk) = (rt_uint32_t) 0x00000007; /* a3 */
- *(--stk) = (rt_uint32_t) 0x00000006; /* a2 */
- *(--stk) = (rt_uint32_t) 0x00000005; /* a1 */
- *(--stk) = (rt_uint32_t) parameter; /* a0 */
- *(--stk) = (rt_uint32_t) 0x00000003; /* v1 */
- *(--stk) = (rt_uint32_t) 0x00000002; /* v0 */
- *(--stk) = (rt_uint32_t) 0x00000001; /* at */
- *(--stk) = (rt_uint32_t) 0x00000000; /* zero */
-
- /* return task's current stack address */
- return (rt_uint8_t *)stk;
-}
-
-/*@}*/
+/* + * File : stack.c + * This file is part of RT-Thread RTOS + * COPYRIGHT (C) 2006, RT-Thread Development Team + * + * The license and distribution terms for this file may be + * found in the file LICENSE in this distribution or at + * http://www.rt-thread.org/license/LICENSE + * + * Change Logs: + * Date Author Notes + * 2010-05-17 swkyer first version + * 2010-07-07 Bernard porting to Jz47xx + */ + +#include <rtthread.h> + +/** + * @addtogroup Loongson SoC3210 + */ + +/*@{*/ + +extern rt_uint32_t cp0_get_cause(void); +extern rt_uint32_t cp0_get_status(void); +extern rt_uint32_t cp0_get_hi(void); +extern rt_uint32_t cp0_get_lo(void); + +/** + * This function will initialize thread stack + * + * @param tentry the entry of thread + * @param parameter the parameter of entry + * @param stack_addr the beginning stack address + * @param texit the function will be called when thread exit + * + * @return stack address + */ +rt_uint8_t *rt_hw_stack_init(void *tentry, void *parameter, rt_uint8_t *stack_addr, void *texit) +{ + rt_uint32_t *stk; + static rt_uint32_t g_sr = 0; + + if (g_sr == 0) + { + g_sr = cp0_get_status(); + g_sr &= 0xfffffffe; + g_sr |= 0x8401; + } + + /** Start at stack top */ + stk = (rt_uint32_t *)stack_addr; + *(stk) = (rt_uint32_t) tentry; /* pc: Entry Point */ + *(--stk) = (rt_uint32_t) 0xeeee; /* c0_cause */ + *(--stk) = (rt_uint32_t) 0xffff; /* c0_badvaddr */ + *(--stk) = (rt_uint32_t) cp0_get_lo(); /* lo */ + *(--stk) = (rt_uint32_t) cp0_get_hi(); /* hi */ + *(--stk) = (rt_uint32_t) g_sr; /* C0_SR: HW2 = En, IE = En */ + *(--stk) = (rt_uint32_t) texit; /* ra */ + *(--stk) = (rt_uint32_t) 0x0000001e; /* s8 */ + *(--stk) = (rt_uint32_t) stack_addr; /* sp */ + *(--stk) = (rt_uint32_t) 0x0000001c; /* gp */ + *(--stk) = (rt_uint32_t) 0x0000001b; /* k1 */ + *(--stk) = (rt_uint32_t) 0x0000001a; /* k0 */ + *(--stk) = (rt_uint32_t) 0x00000019; /* t9 */ + *(--stk) = (rt_uint32_t) 0x00000018; /* t8 */ + *(--stk) = (rt_uint32_t) 0x00000017; /* s7 */ + *(--stk) = (rt_uint32_t) 0x00000016; /* s6 */ + *(--stk) = (rt_uint32_t) 0x00000015; /* s5 */ + *(--stk) = (rt_uint32_t) 0x00000014; /* s4 */ + *(--stk) = (rt_uint32_t) 0x00000013; /* s3 */ + *(--stk) = (rt_uint32_t) 0x00000012; /* s2 */ + *(--stk) = (rt_uint32_t) 0x00000011; /* s1 */ + *(--stk) = (rt_uint32_t) 0x00000010; /* s0 */ + *(--stk) = (rt_uint32_t) 0x0000000f; /* t7 */ + *(--stk) = (rt_uint32_t) 0x0000000e; /* t6 */ + *(--stk) = (rt_uint32_t) 0x0000000d; /* t5 */ + *(--stk) = (rt_uint32_t) 0x0000000c; /* t4 */ + *(--stk) = (rt_uint32_t) 0x0000000b; /* t3 */ + *(--stk) = (rt_uint32_t) 0x0000000a; /* t2 */ + *(--stk) = (rt_uint32_t) 0x00000009; /* t1 */ + *(--stk) = (rt_uint32_t) 0x00000008; /* t0 */ + *(--stk) = (rt_uint32_t) 0x00000007; /* a3 */ + *(--stk) = (rt_uint32_t) 0x00000006; /* a2 */ + *(--stk) = (rt_uint32_t) 0x00000005; /* a1 */ + *(--stk) = (rt_uint32_t) parameter; /* a0 */ + *(--stk) = (rt_uint32_t) 0x00000003; /* v1 */ + *(--stk) = (rt_uint32_t) 0x00000002; /* v0 */ + *(--stk) = (rt_uint32_t) 0x00000001; /* at */ + *(--stk) = (rt_uint32_t) 0x00000000; /* zero */ + + /* return task's current stack address */ + return (rt_uint8_t *)stk; +} + +/*@}*/ diff --git a/libcpu/mips/loongson/start_gcc.S b/libcpu/mips/loongson/start_gcc.S index f558622df6..2b0ef3a39b 100644 --- a/libcpu/mips/loongson/start_gcc.S +++ b/libcpu/mips/loongson/start_gcc.S @@ -1,130 +1,130 @@ -/*
- * File : start_gcc.S
- * Change Logs:
- * Date Author Notes
- * 2010-05-17 swkyer first version
- * 2010-09-04 bernard porting to Jz47xx
- */
-
-#include "../common/mips.inc"
-#include "../common/stackframe.h"
-#include "soc3210.h"
-
- .section ".start", "ax"
- .set noreorder
-
- /* the program entry */
- .globl _start
-_start:
- .set noreorder
- la ra, _start
-
- /* disable interrupt */
- mfc0 t0, CP0_STATUS
- and t0, 0xfffffffe # By default it will be disabled.
- mtc0 t0, CP0_STATUS # Set CPU to disable interrupt.
- nop
-
- /* disable cache */
- mfc0 t0, CP0_CONFIG
- and t0, 0xfffffff8
- or t0, 0x2 # disable,!default value is not it!
- mtc0 t0, CP0_CONFIG # Set CPU to disable cache.
- nop
-
- /* setup stack pointer */
- li sp, SYSTEM_STACK
- la gp, _gp
-
- /* clear bss */
- la t0, __bss_start
- la t1, __bss_end
-_clr_bss_loop:
- sw zero, 0(t0)
- bne t0, t1, _clr_bss_loop
- addiu t0, t0, 4
-
- /* jump to RT-Thread RTOS */
- jal rtthread_startup
- nop
-
- /* restart, never die */
- j _start
- nop
- .set reorder
-
- .globl cp0_get_cause
-cp0_get_cause:
- mfc0 v0, CP0_CAUSE
- jr ra
- nop
-
- .globl cp0_get_status
-cp0_get_status:
- mfc0 v0, CP0_STATUS
- jr ra
- nop
-
- .globl cp0_get_hi
-cp0_get_hi:
- mfhi v0
- jr ra
- nop
-
- .globl cp0_get_lo
-cp0_get_lo:
- mflo v0
- jr ra
- nop
-
- .extern tlb_refill_handler
- .extern cache_error_handler
-
- /* Exception Handler */
- /* 0x0 - TLB refill handler */
- .section .vectors.1, "ax", %progbits
- .global tlb_refill_exception
- .type tlb_refill_exception,@function
-tlb_refill_exception:
- j tlb_refill_handler
- nop
-
- /* 0x100 - Cache error handler */
- .section .vectors.2, "ax", %progbits
- j cache_error_handler
- nop
-
- /* 0x180 - Exception/Interrupt handler */
- .section .vectors.3, "ax", %progbits
- .global general_exception
- .type general_exception,@function
-general_exception:
- j _general_exception_handler
- nop
-
- /* 0x200 - Special Exception Interrupt handler (when IV is set in CP0_CAUSE) */
- .section .vectors.4, "ax", %progbits
- .global irq_exception
- .type irq_exception,@function
-irq_exception:
- j _irq_handler
- nop
-
- .section .vectors, "ax", %progbits
- .extern mips_irq_handle
-
- /* general exception handler */
-_general_exception_handler:
- .set noreorder
- la k0, mips_irq_handle
- jr k0
- nop
- .set reorder
-
- /* interrupt handler */
-_irq_handler:
- .set noreorder
- la k0, mips_irq_handle
- jr k0
- nop
- .set reorder
+/* + * File : start_gcc.S + * Change Logs: + * Date Author Notes + * 2010-05-17 swkyer first version + * 2010-09-04 bernard porting to Jz47xx + */ + +#include "../common/mips.inc" +#include "../common/stackframe.h" +#include "soc3210.h" + + .section ".start", "ax" + .set noreorder + + /* the program entry */ + .globl _start +_start: + .set noreorder + la ra, _start + + /* disable interrupt */ + mfc0 t0, CP0_STATUS + and t0, 0xfffffffe # By default it will be disabled. + mtc0 t0, CP0_STATUS # Set CPU to disable interrupt. + nop + + /* disable cache */ + mfc0 t0, CP0_CONFIG + and t0, 0xfffffff8 + or t0, 0x2 # disable,!default value is not it! + mtc0 t0, CP0_CONFIG # Set CPU to disable cache. + nop + + /* setup stack pointer */ + li sp, SYSTEM_STACK + la gp, _gp + + /* clear bss */ + la t0, __bss_start + la t1, __bss_end +_clr_bss_loop: + sw zero, 0(t0) + bne t0, t1, _clr_bss_loop + addiu t0, t0, 4 + + /* jump to RT-Thread RTOS */ + jal rtthread_startup + nop + + /* restart, never die */ + j _start + nop + .set reorder + + .globl cp0_get_cause +cp0_get_cause: + mfc0 v0, CP0_CAUSE + jr ra + nop + + .globl cp0_get_status +cp0_get_status: + mfc0 v0, CP0_STATUS + jr ra + nop + + .globl cp0_get_hi +cp0_get_hi: + mfhi v0 + jr ra + nop + + .globl cp0_get_lo +cp0_get_lo: + mflo v0 + jr ra + nop + + .extern tlb_refill_handler + .extern cache_error_handler + + /* Exception Handler */ + /* 0x0 - TLB refill handler */ + .section .vectors.1, "ax", %progbits + .global tlb_refill_exception + .type tlb_refill_exception,@function +tlb_refill_exception: + j tlb_refill_handler + nop + + /* 0x100 - Cache error handler */ + .section .vectors.2, "ax", %progbits + j cache_error_handler + nop + + /* 0x180 - Exception/Interrupt handler */ + .section .vectors.3, "ax", %progbits + .global general_exception + .type general_exception,@function +general_exception: + j _general_exception_handler + nop + + /* 0x200 - Special Exception Interrupt handler (when IV is set in CP0_CAUSE) */ + .section .vectors.4, "ax", %progbits + .global irq_exception + .type irq_exception,@function +irq_exception: + j _irq_handler + nop + + .section .vectors, "ax", %progbits + .extern mips_irq_handle + + /* general exception handler */ +_general_exception_handler: + .set noreorder + la k0, mips_irq_handle + jr k0 + nop + .set reorder + + /* interrupt handler */ +_irq_handler: + .set noreorder + la k0, mips_irq_handle + jr k0 + nop + .set reorder diff --git a/libcpu/mips/loongson_1b/cache.c b/libcpu/mips/loongson_1b/cache.c index 550d4160ff..9b3dfde44d 100644 --- a/libcpu/mips/loongson_1b/cache.c +++ b/libcpu/mips/loongson_1b/cache.c @@ -1,228 +1,228 @@ -/*
- * File : cache.c
- * This file is part of RT-Thread RTOS
- * COPYRIGHT (C) 2006 - 2011, RT-Thread Development Team
- *
- * The license and distribution terms for this file may be
- * found in the file LICENSE in this distribution or at
- * http://www.rt-thread.org/license/LICENSE
- *
- * Change Logs:
- * Date Author Notes
- * 2010-07-09 Bernard first version
- * 2011-08-08 lgnq modified for LS1B
- */
-
-#include "../common/mipsregs.h"
-
-#define K0BASE 0x80000000
-#define PRID_LS1B 0x4220
-
-extern void Clear_TagLo (void);
-extern void Invalidate_Icache_Ls1b(unsigned int);
-extern void Invalidate_Dcache_ClearTag_Ls1b(unsigned int);
-extern void Invalidate_Dcache_Fill_Ls1b(unsigned int);
-extern void Writeback_Invalidate_Dcache(unsigned int);
-
-typedef struct cacheinfo_t
-{
- unsigned int icache_size;
- unsigned int dcache_size;
- unsigned int icacheline_size;
- unsigned int dcacheline_size;
-} cacheinfo_t ;
-
-typedef struct cacheop_t
-{
- void (*Clear_TagLo) (void);
- void (*Invalidate_Icache) (unsigned int);
- void (*Invalidate_Dcache_Fill) (unsigned int);
- void (*Invalidate_Dcache_ClearTag) (unsigned int);
- void (*Init_Cache)(void);
-} cacheop_t ;
-
-static cacheop_t cacheop, *pcacheop;
-static cacheinfo_t cacheinfo, *pcacheinfo;
-
-int identify_cpu(void)
-{
- unsigned int cpu_id;
-
- pcacheop = &cacheop;
- pcacheinfo = &cacheinfo;
-
- rt_kprintf("CPU configure: 0x%08x\n", read_c0_config());
- cpu_id = read_c0_prid();
- switch (cpu_id)
- {
- case PRID_LS1B:
- rt_kprintf("CPU:LS1B\n");
- pcacheop->Clear_TagLo = Clear_TagLo;
- pcacheop->Invalidate_Icache = Invalidate_Icache_Ls1b;
- pcacheop->Invalidate_Dcache_Fill = Invalidate_Dcache_Fill_Ls1b;
- pcacheop->Invalidate_Dcache_ClearTag = Invalidate_Dcache_ClearTag_Ls1b;
- break;
- default:
- rt_kprintf("Unknown CPU type, system halted!\n");
- while (1)
- {
- ;
- }
- break;
- }
-
- return 0;
-}
-
-void probe_cache(void)
-{
- unsigned int config1 = read_c0_config1();
- unsigned int icache_size, icache_line_size, icache_sets, icache_ways;
- unsigned int dcache_size, dcache_line_size, dcache_sets, dcache_ways;
-
- if ((icache_line_size = ((config1 >> 19) & 7)))
- icache_line_size = 2 << icache_line_size;
- else
- icache_line_size = icache_line_size;
- icache_sets = 64 << ((config1 >> 22) & 7);
- icache_ways = 1 + ((config1 >> 16) & 7);
- icache_size = icache_sets * icache_ways * icache_line_size;
-
- if ((dcache_line_size = ((config1 >> 10) & 7)))
- dcache_line_size = 2 << dcache_line_size;
- else
- dcache_line_size = dcache_line_size;
- dcache_sets = 64 << ((config1 >> 13) & 7);
- dcache_ways = 1 + ((config1 >> 7) & 7);
- dcache_size = dcache_sets * dcache_ways * dcache_line_size;
-
- rt_kprintf("DCache %2dkb, linesize %d bytes.\n", dcache_size >> 10, dcache_line_size);
- rt_kprintf("ICache %2dkb, linesize %d bytes.\n", icache_size >> 10, icache_line_size);
-
- pcacheinfo->icache_size = icache_size;
- pcacheinfo->dcache_size = dcache_size;
- pcacheinfo->icacheline_size = icache_line_size;
- pcacheinfo->dcacheline_size = dcache_line_size;
-
- return ;
-}
-
-void invalidate_writeback_dcache_all(void)
-{
- unsigned int start = K0BASE;
- unsigned int end = (start + pcacheinfo->dcache_size);
-
- while (start < end)
- {
- Writeback_Invalidate_Dcache(start); //hit writeback invalidate
- start += pcacheinfo->dcacheline_size;
- }
-}
-
-void invalidate_writeback_dcache(unsigned long addr, int size)
-{
- unsigned long start, end;
-
- start = (addr +pcacheinfo->dcacheline_size -1) & (- pcacheinfo->dcacheline_size);
- end = (end + size + pcacheinfo->dcacheline_size -1) & ( -pcacheinfo->dcacheline_size);
-
- while (start <end)
- {
- Writeback_Invalidate_Dcache(start);
- start += pcacheinfo->dcacheline_size;
- }
-}
-
-void invalidate_icache_all(void)
-{
- unsigned int start = K0BASE;
- unsigned int end = (start + pcacheinfo->icache_size);
-
- while (start < end)
- {
- pcacheop->Invalidate_Icache(start);
- start += pcacheinfo->icacheline_size;
- }
-}
-
-void invalidate_dcache_all(void)
-{
- unsigned int start = K0BASE;
- unsigned int end = (start + pcacheinfo->dcache_size);
- while (start <end)
- {
- Invalidate_Dcache_Fill_Gc3210I(start);
- start += pcacheinfo->icacheline_size;
- }
-}
-
-//with cache disabled
-void init_dcache(void)
-{
- unsigned int start = K0BASE;
- unsigned int end = (start + pcacheinfo->dcache_size);
-
- while (start < end)
- {
- pcacheop->Invalidate_Dcache_ClearTag(start);
- start += pcacheinfo->dcacheline_size;
- }
-
-}
-
-void rt_hw_cache_init(void)
-{
- unsigned int start, end;
-
- /* 1. identify cpu and probe cache */
- identify_cpu();
- probe_cache();
-
- start = K0BASE;
- end = (start + pcacheinfo->icache_size);
-
- /*
- * 2. clear CP0 taglo/taghi register;
- */
- pcacheop->Clear_TagLo();
-
- /*
- * 3. invalidate instruction cache;
- */
- while (start < end)
- {
- pcacheop->Invalidate_Icache(start); //index invalidate icache
- start += pcacheinfo->icacheline_size;
- }
-
- /*
- * 4. invalidate data cache;
- */
- start = K0BASE;
- end = (start + pcacheinfo->dcache_size);
- while(start < end)
- {
- pcacheop->Invalidate_Dcache_ClearTag(start);
- start += pcacheinfo->dcacheline_size;
- }
-
- start = K0BASE;
- while(start < end)
- {
- pcacheop->Invalidate_Dcache_Fill(start); //index invalidate dcache
- start += pcacheinfo->dcacheline_size;
- }
-
- start = K0BASE;
- while(start < end)
- {
- pcacheop->Invalidate_Dcache_ClearTag(start);
- start += pcacheinfo->dcacheline_size;
- }
-
- /* enable cache */
- enable_cpu_cache();
- rt_kprintf("enable cpu cache done\n");
-
- return ;
-}
+/* + * File : cache.c + * This file is part of RT-Thread RTOS + * COPYRIGHT (C) 2006 - 2011, RT-Thread Development Team + * + * The license and distribution terms for this file may be + * found in the file LICENSE in this distribution or at + * http://www.rt-thread.org/license/LICENSE + * + * Change Logs: + * Date Author Notes + * 2010-07-09 Bernard first version + * 2011-08-08 lgnq modified for LS1B + */ + +#include "../common/mipsregs.h" + +#define K0BASE 0x80000000 +#define PRID_LS1B 0x4220 + +extern void Clear_TagLo (void); +extern void Invalidate_Icache_Ls1b(unsigned int); +extern void Invalidate_Dcache_ClearTag_Ls1b(unsigned int); +extern void Invalidate_Dcache_Fill_Ls1b(unsigned int); +extern void Writeback_Invalidate_Dcache(unsigned int); + +typedef struct cacheinfo_t +{ + unsigned int icache_size; + unsigned int dcache_size; + unsigned int icacheline_size; + unsigned int dcacheline_size; +} cacheinfo_t ; + +typedef struct cacheop_t +{ + void (*Clear_TagLo) (void); + void (*Invalidate_Icache) (unsigned int); + void (*Invalidate_Dcache_Fill) (unsigned int); + void (*Invalidate_Dcache_ClearTag) (unsigned int); + void (*Init_Cache)(void); +} cacheop_t ; + +static cacheop_t cacheop, *pcacheop; +static cacheinfo_t cacheinfo, *pcacheinfo; + +int identify_cpu(void) +{ + unsigned int cpu_id; + + pcacheop = &cacheop; + pcacheinfo = &cacheinfo; + + rt_kprintf("CPU configure: 0x%08x\n", read_c0_config()); + cpu_id = read_c0_prid(); + switch (cpu_id) + { + case PRID_LS1B: + rt_kprintf("CPU:LS1B\n"); + pcacheop->Clear_TagLo = Clear_TagLo; + pcacheop->Invalidate_Icache = Invalidate_Icache_Ls1b; + pcacheop->Invalidate_Dcache_Fill = Invalidate_Dcache_Fill_Ls1b; + pcacheop->Invalidate_Dcache_ClearTag = Invalidate_Dcache_ClearTag_Ls1b; + break; + default: + rt_kprintf("Unknown CPU type, system halted!\n"); + while (1) + { + ; + } + break; + } + + return 0; +} + +void probe_cache(void) +{ + unsigned int config1 = read_c0_config1(); + unsigned int icache_size, icache_line_size, icache_sets, icache_ways; + unsigned int dcache_size, dcache_line_size, dcache_sets, dcache_ways; + + if ((icache_line_size = ((config1 >> 19) & 7))) + icache_line_size = 2 << icache_line_size; + else + icache_line_size = icache_line_size; + icache_sets = 64 << ((config1 >> 22) & 7); + icache_ways = 1 + ((config1 >> 16) & 7); + icache_size = icache_sets * icache_ways * icache_line_size; + + if ((dcache_line_size = ((config1 >> 10) & 7))) + dcache_line_size = 2 << dcache_line_size; + else + dcache_line_size = dcache_line_size; + dcache_sets = 64 << ((config1 >> 13) & 7); + dcache_ways = 1 + ((config1 >> 7) & 7); + dcache_size = dcache_sets * dcache_ways * dcache_line_size; + + rt_kprintf("DCache %2dkb, linesize %d bytes.\n", dcache_size >> 10, dcache_line_size); + rt_kprintf("ICache %2dkb, linesize %d bytes.\n", icache_size >> 10, icache_line_size); + + pcacheinfo->icache_size = icache_size; + pcacheinfo->dcache_size = dcache_size; + pcacheinfo->icacheline_size = icache_line_size; + pcacheinfo->dcacheline_size = dcache_line_size; + + return ; +} + +void invalidate_writeback_dcache_all(void) +{ + unsigned int start = K0BASE; + unsigned int end = (start + pcacheinfo->dcache_size); + + while (start < end) + { + Writeback_Invalidate_Dcache(start); //hit writeback invalidate + start += pcacheinfo->dcacheline_size; + } +} + +void invalidate_writeback_dcache(unsigned long addr, int size) +{ + unsigned long start, end; + + start = (addr +pcacheinfo->dcacheline_size -1) & (- pcacheinfo->dcacheline_size); + end = (end + size + pcacheinfo->dcacheline_size -1) & ( -pcacheinfo->dcacheline_size); + + while (start <end) + { + Writeback_Invalidate_Dcache(start); + start += pcacheinfo->dcacheline_size; + } +} + +void invalidate_icache_all(void) +{ + unsigned int start = K0BASE; + unsigned int end = (start + pcacheinfo->icache_size); + + while (start < end) + { + pcacheop->Invalidate_Icache(start); + start += pcacheinfo->icacheline_size; + } +} + +void invalidate_dcache_all(void) +{ + unsigned int start = K0BASE; + unsigned int end = (start + pcacheinfo->dcache_size); + while (start <end) + { + Invalidate_Dcache_Fill_Gc3210I(start); + start += pcacheinfo->icacheline_size; + } +} + +//with cache disabled +void init_dcache(void) +{ + unsigned int start = K0BASE; + unsigned int end = (start + pcacheinfo->dcache_size); + + while (start < end) + { + pcacheop->Invalidate_Dcache_ClearTag(start); + start += pcacheinfo->dcacheline_size; + } + +} + +void rt_hw_cache_init(void) +{ + unsigned int start, end; + + /* 1. identify cpu and probe cache */ + identify_cpu(); + probe_cache(); + + start = K0BASE; + end = (start + pcacheinfo->icache_size); + + /* + * 2. clear CP0 taglo/taghi register; + */ + pcacheop->Clear_TagLo(); + + /* + * 3. invalidate instruction cache; + */ + while (start < end) + { + pcacheop->Invalidate_Icache(start); //index invalidate icache + start += pcacheinfo->icacheline_size; + } + + /* + * 4. invalidate data cache; + */ + start = K0BASE; + end = (start + pcacheinfo->dcache_size); + while(start < end) + { + pcacheop->Invalidate_Dcache_ClearTag(start); + start += pcacheinfo->dcacheline_size; + } + + start = K0BASE; + while(start < end) + { + pcacheop->Invalidate_Dcache_Fill(start); //index invalidate dcache + start += pcacheinfo->dcacheline_size; + } + + start = K0BASE; + while(start < end) + { + pcacheop->Invalidate_Dcache_ClearTag(start); + start += pcacheinfo->dcacheline_size; + } + + /* enable cache */ + enable_cpu_cache(); + rt_kprintf("enable cpu cache done\n"); + + return ; +} diff --git a/libcpu/mips/loongson_1b/cache.h b/libcpu/mips/loongson_1b/cache.h index b1ce646857..b5c2d4501e 100644 --- a/libcpu/mips/loongson_1b/cache.h +++ b/libcpu/mips/loongson_1b/cache.h @@ -1,52 +1,52 @@ -/*
- * File : cache.h
- * This file is part of RT-Thread RTOS
- * COPYRIGHT (C) 2006 - 2011, RT-Thread Development Team
- *
- * The license and distribution terms for this file may be
- * found in the file LICENSE in this distribution or at
- * http://www.rt-thread.org/license/LICENSE
- *
- * Change Logs:
- * Date Author Notes
- * 2010-07-09 Bernard first version
- * 2011-08-08 lgnq modified for LS1B
- */
-#ifndef __CACHE_H__
-#define __CACHE_H__
-
-/*
- * Cache Operations
- */
-#define Index_Invalidate_I 0x00
-#define Index_Writeback_Inv_D 0x01
-#define Index_Invalidate_SI 0x02
-#define Index_Writeback_Inv_SD 0x03
-#define Index_Load_Tag_I 0x04
-#define Index_Load_Tag_D 0x05
-#define Index_Load_Tag_SI 0x06
-#define Index_Load_Tag_SD 0x07
-#define Index_Store_Tag_I 0x08
-#define Index_Store_Tag_D 0x09
-#define Index_Store_Tag_SI 0x0A
-#define Index_Store_Tag_SD 0x0B
-#define Create_Dirty_Excl_D 0x0d
-#define Create_Dirty_Excl_SD 0x0f
-#define Hit_Invalidate_I 0x10
-#define Hit_Invalidate_D 0x11
-#define Hit_Invalidate_SI 0x12
-#define Hit_Invalidate_SD 0x13
-#define Fill 0x14
-#define Hit_Writeback_Inv_D 0x15
-/* 0x16 is unused */
-#define Hit_Writeback_Inv_SD 0x17
-#define Hit_Writeback_I 0x18
-#define Hit_Writeback_D 0x19
-/* 0x1a is unused */
-#define Hit_Writeback_SD 0x1b
-/* 0x1c is unused */
-/* 0x1e is unused */
-#define Hit_Set_Virtual_SI 0x1e
-#define Hit_Set_Virtual_SD 0x1f
-
-#endif
+/* + * File : cache.h + * This file is part of RT-Thread RTOS + * COPYRIGHT (C) 2006 - 2011, RT-Thread Development Team + * + * The license and distribution terms for this file may be + * found in the file LICENSE in this distribution or at + * http://www.rt-thread.org/license/LICENSE + * + * Change Logs: + * Date Author Notes + * 2010-07-09 Bernard first version + * 2011-08-08 lgnq modified for LS1B + */ +#ifndef __CACHE_H__ +#define __CACHE_H__ + +/* + * Cache Operations + */ +#define Index_Invalidate_I 0x00 +#define Index_Writeback_Inv_D 0x01 +#define Index_Invalidate_SI 0x02 +#define Index_Writeback_Inv_SD 0x03 +#define Index_Load_Tag_I 0x04 +#define Index_Load_Tag_D 0x05 +#define Index_Load_Tag_SI 0x06 +#define Index_Load_Tag_SD 0x07 +#define Index_Store_Tag_I 0x08 +#define Index_Store_Tag_D 0x09 +#define Index_Store_Tag_SI 0x0A +#define Index_Store_Tag_SD 0x0B +#define Create_Dirty_Excl_D 0x0d +#define Create_Dirty_Excl_SD 0x0f +#define Hit_Invalidate_I 0x10 +#define Hit_Invalidate_D 0x11 +#define Hit_Invalidate_SI 0x12 +#define Hit_Invalidate_SD 0x13 +#define Fill 0x14 +#define Hit_Writeback_Inv_D 0x15 +/* 0x16 is unused */ +#define Hit_Writeback_Inv_SD 0x17 +#define Hit_Writeback_I 0x18 +#define Hit_Writeback_D 0x19 +/* 0x1a is unused */ +#define Hit_Writeback_SD 0x1b +/* 0x1c is unused */ +/* 0x1e is unused */ +#define Hit_Set_Virtual_SI 0x1e +#define Hit_Set_Virtual_SD 0x1f + +#endif diff --git a/libcpu/mips/loongson_1b/context_gcc.S b/libcpu/mips/loongson_1b/context_gcc.S index ec8e0b1258..ce004dc716 100644 --- a/libcpu/mips/loongson_1b/context_gcc.S +++ b/libcpu/mips/loongson_1b/context_gcc.S @@ -1,149 +1,149 @@ -/*
- * File : context_gcc.S
- * This file is part of RT-Thread RTOS
- * COPYRIGHT (C) 2006 - 2011, RT-Thread Development Team
- *
- * The license and distribution terms for this file may be
- * found in the file LICENSE in this distribution or at
- * http://www.rt-thread.org/license/LICENSE
- *
- * Change Logs:
- * Date Author Notes
- * 2010-05-17 swkyer first version
- * 2010-09-11 bernard port to Loongson SoC3210
- * 2011-08-08 lgnq port to Loongson LS1B
- */
-
-#include "../common/mips.inc"
-#include "../common/stackframe.h"
-
- .section ".text", "ax"
- .set noreorder
-
-/*
- * rt_base_t rt_hw_interrupt_disable()
- */
- .globl rt_hw_interrupt_disable
-rt_hw_interrupt_disable:
- mfc0 v0, CP0_STATUS
- and v1, v0, 0xfffffffe
- mtc0 v1, CP0_STATUS
- jr ra
- nop
-
-/*
- * void rt_hw_interrupt_enable(rt_base_t level)
- */
- .globl rt_hw_interrupt_enable
-rt_hw_interrupt_enable:
- mtc0 a0, CP0_STATUS
- jr ra
- nop
-
-/*
- * void rt_hw_context_switch(rt_uint32 from, rt_uint32 to)
- * a0 --> from
- * a1 --> to
- */
- .globl rt_hw_context_switch
-rt_hw_context_switch:
- mtc0 ra, CP0_EPC
- SAVE_ALL
-
- sw sp, 0(a0) /* store sp in preempted tasks TCB */
- lw sp, 0(a1) /* get new task stack pointer */
-
- RESTORE_ALL_AND_RET
-
-/*
- * void rt_hw_context_switch_to(rt_uint32 to)/*
- * a0 --> to
- */
- .globl rt_hw_context_switch_to
-rt_hw_context_switch_to:
- lw sp, 0(a0) /* get new task stack pointer */
-
- RESTORE_ALL_AND_RET
-
-/*
- * void rt_hw_context_switch_interrupt(rt_uint32 from, rt_uint32 to)/*
- */
- .globl rt_thread_switch_interrupt_flag
- .globl rt_interrupt_from_thread
- .globl rt_interrupt_to_thread
- .globl rt_hw_context_switch_interrupt
-rt_hw_context_switch_interrupt:
- la t0, rt_thread_switch_interrupt_flag
- lw t1, 0(t0)
- nop
- bnez t1, _reswitch
- nop
- li t1, 0x01 /* set rt_thread_switch_interrupt_flag to 1 */
- sw t1, 0(t0)
- la t0, rt_interrupt_from_thread /* set rt_interrupt_from_thread */
- sw a0, 0(t0)
-_reswitch:
- la t0, rt_interrupt_to_thread /* set rt_interrupt_to_thread */
- sw a1, 0(t0)
- jr ra
- nop
-
-/*
- * void rt_hw_context_switch_interrupt_do(rt_base_t flag)
- */
- .globl rt_interrupt_enter
- .globl rt_interrupt_leave
- .globl mips_irq_handle
-mips_irq_handle:
- SAVE_ALL
-
- mfc0 t0, CP0_CAUSE
- and t1, t0, 0xff
- bnez t1, spurious_interrupt /* check exception */
- nop
-
- /* let k0 keep the current context sp */
- move k0, sp
- /* switch to kernel stack */
- li sp, SYSTEM_STACK
-
- jal rt_interrupt_enter
- nop
- jal rt_interrupt_dispatch
- nop
- jal rt_interrupt_leave
- nop
-
- /* switch sp back to thread's context */
- move sp, k0
-
- /*
- * if rt_thread_switch_interrupt_flag set, jump to
- * rt_hw_context_switch_interrupt_do and don't return
- */
- la k0, rt_thread_switch_interrupt_flag
- lw k1, 0(k0)
- beqz k1, spurious_interrupt
- nop
- sw zero, 0(k0) /* clear flag */
- nop
-
- /*
- * switch to the new thread
- */
- la k0, rt_interrupt_from_thread
- lw k1, 0(k0)
- nop
- sw sp, 0(k1) /* store sp in preempted tasks's TCB */
-
- la k0, rt_interrupt_to_thread
- lw k1, 0(k0)
- nop
- lw sp, 0(k1) /* get new task's stack pointer */
- j spurious_interrupt
- nop
-
-spurious_interrupt:
- RESTORE_ALL_AND_RET
-
- .set reorder
+/* + * File : context_gcc.S + * This file is part of RT-Thread RTOS + * COPYRIGHT (C) 2006 - 2011, RT-Thread Development Team + * + * The license and distribution terms for this file may be + * found in the file LICENSE in this distribution or at + * http://www.rt-thread.org/license/LICENSE + * + * Change Logs: + * Date Author Notes + * 2010-05-17 swkyer first version + * 2010-09-11 bernard port to Loongson SoC3210 + * 2011-08-08 lgnq port to Loongson LS1B + */ + +#include "../common/mips.inc" +#include "../common/stackframe.h" + + .section ".text", "ax" + .set noreorder + +/* + * rt_base_t rt_hw_interrupt_disable() + */ + .globl rt_hw_interrupt_disable +rt_hw_interrupt_disable: + mfc0 v0, CP0_STATUS + and v1, v0, 0xfffffffe + mtc0 v1, CP0_STATUS + jr ra + nop + +/* + * void rt_hw_interrupt_enable(rt_base_t level) + */ + .globl rt_hw_interrupt_enable +rt_hw_interrupt_enable: + mtc0 a0, CP0_STATUS + jr ra + nop + +/* + * void rt_hw_context_switch(rt_uint32 from, rt_uint32 to) + * a0 --> from + * a1 --> to + */ + .globl rt_hw_context_switch +rt_hw_context_switch: + mtc0 ra, CP0_EPC + SAVE_ALL + + sw sp, 0(a0) /* store sp in preempted tasks TCB */ + lw sp, 0(a1) /* get new task stack pointer */ + + RESTORE_ALL_AND_RET + +/* + * void rt_hw_context_switch_to(rt_uint32 to)/* + * a0 --> to + */ + .globl rt_hw_context_switch_to +rt_hw_context_switch_to: + lw sp, 0(a0) /* get new task stack pointer */ + + RESTORE_ALL_AND_RET + +/* + * void rt_hw_context_switch_interrupt(rt_uint32 from, rt_uint32 to)/* + */ + .globl rt_thread_switch_interrupt_flag + .globl rt_interrupt_from_thread + .globl rt_interrupt_to_thread + .globl rt_hw_context_switch_interrupt +rt_hw_context_switch_interrupt: + la t0, rt_thread_switch_interrupt_flag + lw t1, 0(t0) + nop + bnez t1, _reswitch + nop + li t1, 0x01 /* set rt_thread_switch_interrupt_flag to 1 */ + sw t1, 0(t0) + la t0, rt_interrupt_from_thread /* set rt_interrupt_from_thread */ + sw a0, 0(t0) +_reswitch: + la t0, rt_interrupt_to_thread /* set rt_interrupt_to_thread */ + sw a1, 0(t0) + jr ra + nop + +/* + * void rt_hw_context_switch_interrupt_do(rt_base_t flag) + */ + .globl rt_interrupt_enter + .globl rt_interrupt_leave + .globl mips_irq_handle +mips_irq_handle: + SAVE_ALL + + mfc0 t0, CP0_CAUSE + and t1, t0, 0xff + bnez t1, spurious_interrupt /* check exception */ + nop + + /* let k0 keep the current context sp */ + move k0, sp + /* switch to kernel stack */ + li sp, SYSTEM_STACK + + jal rt_interrupt_enter + nop + jal rt_interrupt_dispatch + nop + jal rt_interrupt_leave + nop + + /* switch sp back to thread's context */ + move sp, k0 + + /* + * if rt_thread_switch_interrupt_flag set, jump to + * rt_hw_context_switch_interrupt_do and don't return + */ + la k0, rt_thread_switch_interrupt_flag + lw k1, 0(k0) + beqz k1, spurious_interrupt + nop + sw zero, 0(k0) /* clear flag */ + nop + + /* + * switch to the new thread + */ + la k0, rt_interrupt_from_thread + lw k1, 0(k0) + nop + sw sp, 0(k1) /* store sp in preempted tasks's TCB */ + + la k0, rt_interrupt_to_thread + lw k1, 0(k0) + nop + lw sp, 0(k1) /* get new task's stack pointer */ + j spurious_interrupt + nop + +spurious_interrupt: + RESTORE_ALL_AND_RET + + .set reorder diff --git a/libcpu/mips/loongson_1b/cpuport.c b/libcpu/mips/loongson_1b/cpuport.c index 9917b0cce0..c095c04814 100644 --- a/libcpu/mips/loongson_1b/cpuport.c +++ b/libcpu/mips/loongson_1b/cpuport.c @@ -1,124 +1,124 @@ -/*
- * File : cpuport.c
- * This file is part of RT-Thread RTOS
- * COPYRIGHT (C) 2006 - 2011, RT-Thread Development Team
- *
- * The license and distribution terms for this file may be
- * found in the file LICENSE in this distribution or at
- * http://www.rt-thread.org/license/LICENSE
- *
- * Change Logs:
- * Date Author Notes
- * 2010-07-09 Bernard first version
- * 2010-09-11 Bernard add CPU reset implementation
- */
-
-#include <rtthread.h>
-#include "ls1b.h"
-
-/**
- * @addtogroup Loongson LS1B
- */
-
-/*@{*/
-
-/**
- * this function will reset CPU
- *
- */
-void rt_hw_cpu_reset(void)
-{
- /* open the watch-dog */
- WDT_EN = 0x01; /* watch dog enable */
- WDT_TIMER = 0x01; /* watch dog will be timeout after 1 tick */
- WDT_SET = 0x01; /* watch dog start */
-
- rt_kprintf("reboot system...\n");
- while (1);
-}
-
-/**
- * this function will shutdown CPU
- *
- */
-void rt_hw_cpu_shutdown(void)
-{
- rt_kprintf("shutdown...\n");
-
- while (1);
-}
-
-extern rt_uint32_t cp0_get_cause(void);
-extern rt_uint32_t cp0_get_status(void);
-extern rt_uint32_t cp0_get_hi(void);
-extern rt_uint32_t cp0_get_lo(void);
-
-/**
- * This function will initialize thread stack
- *
- * @param tentry the entry of thread
- * @param parameter the parameter of entry
- * @param stack_addr the beginning stack address
- * @param texit the function will be called when thread exit
- *
- * @return stack address
- */
-rt_uint8_t *rt_hw_stack_init(void *tentry, void *parameter, rt_uint8_t *stack_addr, void *texit)
-{
- rt_uint32_t *stk;
- static rt_uint32_t g_sr = 0;
-
- if (g_sr == 0)
- {
- g_sr = cp0_get_status();
- g_sr &= 0xfffffffe;
- g_sr |= 0x8401;
- }
-
- /** Start at stack top */
- stk = (rt_uint32_t *)stack_addr;
- *(stk) = (rt_uint32_t) tentry; /* pc: Entry Point */
- *(--stk) = (rt_uint32_t) 0xeeee; /* c0_cause */
- *(--stk) = (rt_uint32_t) 0xffff; /* c0_badvaddr */
- *(--stk) = (rt_uint32_t) cp0_get_lo(); /* lo */
- *(--stk) = (rt_uint32_t) cp0_get_hi(); /* hi */
- *(--stk) = (rt_uint32_t) g_sr; /* C0_SR: HW2 = En, IE = En */
- *(--stk) = (rt_uint32_t) texit; /* ra */
- *(--stk) = (rt_uint32_t) 0x0000001e; /* s8 */
- *(--stk) = (rt_uint32_t) stack_addr; /* sp */
- *(--stk) = (rt_uint32_t) 0x0000001c; /* gp */
- *(--stk) = (rt_uint32_t) 0x0000001b; /* k1 */
- *(--stk) = (rt_uint32_t) 0x0000001a; /* k0 */
- *(--stk) = (rt_uint32_t) 0x00000019; /* t9 */
- *(--stk) = (rt_uint32_t) 0x00000018; /* t8 */
- *(--stk) = (rt_uint32_t) 0x00000017; /* s7 */
- *(--stk) = (rt_uint32_t) 0x00000016; /* s6 */
- *(--stk) = (rt_uint32_t) 0x00000015; /* s5 */
- *(--stk) = (rt_uint32_t) 0x00000014; /* s4 */
- *(--stk) = (rt_uint32_t) 0x00000013; /* s3 */
- *(--stk) = (rt_uint32_t) 0x00000012; /* s2 */
- *(--stk) = (rt_uint32_t) 0x00000011; /* s1 */
- *(--stk) = (rt_uint32_t) 0x00000010; /* s0 */
- *(--stk) = (rt_uint32_t) 0x0000000f; /* t7 */
- *(--stk) = (rt_uint32_t) 0x0000000e; /* t6 */
- *(--stk) = (rt_uint32_t) 0x0000000d; /* t5 */
- *(--stk) = (rt_uint32_t) 0x0000000c; /* t4 */
- *(--stk) = (rt_uint32_t) 0x0000000b; /* t3 */
- *(--stk) = (rt_uint32_t) 0x0000000a; /* t2 */
- *(--stk) = (rt_uint32_t) 0x00000009; /* t1 */
- *(--stk) = (rt_uint32_t) 0x00000008; /* t0 */
- *(--stk) = (rt_uint32_t) 0x00000007; /* a3 */
- *(--stk) = (rt_uint32_t) 0x00000006; /* a2 */
- *(--stk) = (rt_uint32_t) 0x00000005; /* a1 */
- *(--stk) = (rt_uint32_t) parameter; /* a0 */
- *(--stk) = (rt_uint32_t) 0x00000003; /* v1 */
- *(--stk) = (rt_uint32_t) 0x00000002; /* v0 */
- *(--stk) = (rt_uint32_t) 0x00000001; /* at */
- *(--stk) = (rt_uint32_t) 0x00000000; /* zero */
-
- /* return task's current stack address */
- return (rt_uint8_t *)stk;
-}
-
-/*@}*/
-
+/* + * File : cpuport.c + * This file is part of RT-Thread RTOS + * COPYRIGHT (C) 2006 - 2011, RT-Thread Development Team + * + * The license and distribution terms for this file may be + * found in the file LICENSE in this distribution or at + * http://www.rt-thread.org/license/LICENSE + * + * Change Logs: + * Date Author Notes + * 2010-07-09 Bernard first version + * 2010-09-11 Bernard add CPU reset implementation + */ + +#include <rtthread.h> +#include "ls1b.h" + +/** + * @addtogroup Loongson LS1B + */ + +/*@{*/ + +/** + * this function will reset CPU + * + */ +void rt_hw_cpu_reset(void) +{ + /* open the watch-dog */ + WDT_EN = 0x01; /* watch dog enable */ + WDT_TIMER = 0x01; /* watch dog will be timeout after 1 tick */ + WDT_SET = 0x01; /* watch dog start */ + + rt_kprintf("reboot system...\n"); + while (1); +} + +/** + * this function will shutdown CPU + * + */ +void rt_hw_cpu_shutdown(void) +{ + rt_kprintf("shutdown...\n"); + + while (1); +} + +extern rt_uint32_t cp0_get_cause(void); +extern rt_uint32_t cp0_get_status(void); +extern rt_uint32_t cp0_get_hi(void); +extern rt_uint32_t cp0_get_lo(void); + +/** + * This function will initialize thread stack + * + * @param tentry the entry of thread + * @param parameter the parameter of entry + * @param stack_addr the beginning stack address + * @param texit the function will be called when thread exit + * + * @return stack address + */ +rt_uint8_t *rt_hw_stack_init(void *tentry, void *parameter, rt_uint8_t *stack_addr, void *texit) +{ + rt_uint32_t *stk; + static rt_uint32_t g_sr = 0; + + if (g_sr == 0) + { + g_sr = cp0_get_status(); + g_sr &= 0xfffffffe; + g_sr |= 0x8401; + } + + /** Start at stack top */ + stk = (rt_uint32_t *)stack_addr; + *(stk) = (rt_uint32_t) tentry; /* pc: Entry Point */ + *(--stk) = (rt_uint32_t) 0xeeee; /* c0_cause */ + *(--stk) = (rt_uint32_t) 0xffff; /* c0_badvaddr */ + *(--stk) = (rt_uint32_t) cp0_get_lo(); /* lo */ + *(--stk) = (rt_uint32_t) cp0_get_hi(); /* hi */ + *(--stk) = (rt_uint32_t) g_sr; /* C0_SR: HW2 = En, IE = En */ + *(--stk) = (rt_uint32_t) texit; /* ra */ + *(--stk) = (rt_uint32_t) 0x0000001e; /* s8 */ + *(--stk) = (rt_uint32_t) stack_addr; /* sp */ + *(--stk) = (rt_uint32_t) 0x0000001c; /* gp */ + *(--stk) = (rt_uint32_t) 0x0000001b; /* k1 */ + *(--stk) = (rt_uint32_t) 0x0000001a; /* k0 */ + *(--stk) = (rt_uint32_t) 0x00000019; /* t9 */ + *(--stk) = (rt_uint32_t) 0x00000018; /* t8 */ + *(--stk) = (rt_uint32_t) 0x00000017; /* s7 */ + *(--stk) = (rt_uint32_t) 0x00000016; /* s6 */ + *(--stk) = (rt_uint32_t) 0x00000015; /* s5 */ + *(--stk) = (rt_uint32_t) 0x00000014; /* s4 */ + *(--stk) = (rt_uint32_t) 0x00000013; /* s3 */ + *(--stk) = (rt_uint32_t) 0x00000012; /* s2 */ + *(--stk) = (rt_uint32_t) 0x00000011; /* s1 */ + *(--stk) = (rt_uint32_t) 0x00000010; /* s0 */ + *(--stk) = (rt_uint32_t) 0x0000000f; /* t7 */ + *(--stk) = (rt_uint32_t) 0x0000000e; /* t6 */ + *(--stk) = (rt_uint32_t) 0x0000000d; /* t5 */ + *(--stk) = (rt_uint32_t) 0x0000000c; /* t4 */ + *(--stk) = (rt_uint32_t) 0x0000000b; /* t3 */ + *(--stk) = (rt_uint32_t) 0x0000000a; /* t2 */ + *(--stk) = (rt_uint32_t) 0x00000009; /* t1 */ + *(--stk) = (rt_uint32_t) 0x00000008; /* t0 */ + *(--stk) = (rt_uint32_t) 0x00000007; /* a3 */ + *(--stk) = (rt_uint32_t) 0x00000006; /* a2 */ + *(--stk) = (rt_uint32_t) 0x00000005; /* a1 */ + *(--stk) = (rt_uint32_t) parameter; /* a0 */ + *(--stk) = (rt_uint32_t) 0x00000003; /* v1 */ + *(--stk) = (rt_uint32_t) 0x00000002; /* v0 */ + *(--stk) = (rt_uint32_t) 0x00000001; /* at */ + *(--stk) = (rt_uint32_t) 0x00000000; /* zero */ + + /* return task's current stack address */ + return (rt_uint8_t *)stk; +} + +/*@}*/ + diff --git a/libcpu/mips/loongson_1b/exception.c b/libcpu/mips/loongson_1b/exception.c index f46ddfa14a..4a3745cbc5 100644 --- a/libcpu/mips/loongson_1b/exception.c +++ b/libcpu/mips/loongson_1b/exception.c @@ -1,91 +1,91 @@ -/*
- * File : cpu.c
- * This file is part of RT-Thread RTOS
- * COPYRIGHT (C) 2006 - 2011, RT-Thread Development Team
- *
- * The license and distribution terms for this file may be
- * found in the file LICENSE in this distribution or at
- * http://www.rt-thread.org/license/LICENSE
- *
- * Change Logs:
- * Date Author Notes
- * 2010-05-17 swkyer first version
- */
-#include <rtthread.h>
-#include <rthw.h>
-#include "../common/exception.h"
-#include "../common/mipsregs.h"
-
-/**
- * @addtogroup Loongson
- */
-
-/*@{*/
-
-/**
- * exception handle table
- */
-#define RT_EXCEPTION_MAX 8
-exception_func_t sys_exception_handlers[RT_EXCEPTION_MAX];
-
-/**
- * setup the exception handle
- */
-exception_func_t rt_set_except_vector(int n, exception_func_t func)
-{
- exception_func_t old_handler = sys_exception_handlers[n];
-
- if ((n == 0) || (n > RT_EXCEPTION_MAX) || (!func))
- {
- return 0;
- }
-
- sys_exception_handlers[n] = func;
-
- return old_handler;
-}
-
-void tlb_refill_handler(void)
-{
- rt_kprintf("tlb-miss happens, epc: 0x%08x\n", read_c0_epc());
- rt_hw_cpu_shutdown();
-}
-
-void cache_error_handler(void)
-{
- rt_kprintf("cache exception happens, epc: 0x%08x\n", read_c0_epc());
- rt_hw_cpu_shutdown();
-}
-
-static void unhandled_exception_handle(pt_regs_t *regs)
-{
- rt_kprintf("exception happens, epc: 0x%08x, cause: 0x%08x\n", regs->cp0_epc, read_c0_cause());
-}
-
-void install_default_execpt_handle(void)
-{
- rt_int32_t i;
-
- for (i=0; i<RT_EXCEPTION_MAX; i++)
- sys_exception_handlers[i] = (exception_func_t)unhandled_exception_handle;
-}
-
-void exception_handler(pt_regs_t *regs)
-{
- rt_uint32_t cause;
- rt_uint32_t index;
-
- cause = (read_c0_cause() & read_c0_config());
- cause = (cause & 0xfc00) >> 8;
-
- for (index = RT_EXCEPTION_MAX; index > 0; index --)
- {
- if (cause & (1 << index))
- {
- sys_exception_handlers[index](regs);
- cause &= ~(1 << index);
- }
- }
-}
-
-/*@}*/
+/* + * File : cpu.c + * This file is part of RT-Thread RTOS + * COPYRIGHT (C) 2006 - 2011, RT-Thread Development Team + * + * The license and distribution terms for this file may be + * found in the file LICENSE in this distribution or at + * http://www.rt-thread.org/license/LICENSE + * + * Change Logs: + * Date Author Notes + * 2010-05-17 swkyer first version + */ +#include <rtthread.h> +#include <rthw.h> +#include "../common/exception.h" +#include "../common/mipsregs.h" + +/** + * @addtogroup Loongson + */ + +/*@{*/ + +/** + * exception handle table + */ +#define RT_EXCEPTION_MAX 8 +exception_func_t sys_exception_handlers[RT_EXCEPTION_MAX]; + +/** + * setup the exception handle + */ +exception_func_t rt_set_except_vector(int n, exception_func_t func) +{ + exception_func_t old_handler = sys_exception_handlers[n]; + + if ((n == 0) || (n > RT_EXCEPTION_MAX) || (!func)) + { + return 0; + } + + sys_exception_handlers[n] = func; + + return old_handler; +} + +void tlb_refill_handler(void) +{ + rt_kprintf("tlb-miss happens, epc: 0x%08x\n", read_c0_epc()); + rt_hw_cpu_shutdown(); +} + +void cache_error_handler(void) +{ + rt_kprintf("cache exception happens, epc: 0x%08x\n", read_c0_epc()); + rt_hw_cpu_shutdown(); +} + +static void unhandled_exception_handle(pt_regs_t *regs) +{ + rt_kprintf("exception happens, epc: 0x%08x, cause: 0x%08x\n", regs->cp0_epc, read_c0_cause()); +} + +void install_default_execpt_handle(void) +{ + rt_int32_t i; + + for (i=0; i<RT_EXCEPTION_MAX; i++) + sys_exception_handlers[i] = (exception_func_t)unhandled_exception_handle; +} + +void exception_handler(pt_regs_t *regs) +{ + rt_uint32_t cause; + rt_uint32_t index; + + cause = (read_c0_cause() & read_c0_config()); + cause = (cause & 0xfc00) >> 8; + + for (index = RT_EXCEPTION_MAX; index > 0; index --) + { + if (cause & (1 << index)) + { + sys_exception_handlers[index](regs); + cause &= ~(1 << index); + } + } +} + +/*@}*/ diff --git a/libcpu/mips/loongson_1b/interrupt.c b/libcpu/mips/loongson_1b/interrupt.c index ddba29f489..63240053a8 100644 --- a/libcpu/mips/loongson_1b/interrupt.c +++ b/libcpu/mips/loongson_1b/interrupt.c @@ -1,170 +1,170 @@ -/*
- * File : interrupt.c
- * This file is part of RT-Thread RTOS
- * COPYRIGHT (C) 2006 - 2011, RT-Thread Development Team
- *
- * The license and distribution terms for this file may be
- * found in the file LICENSE in this distribution or at
- * http://www.rt-thread.org/license/LICENSE
- *
- * Change Logs:
- * Date Author Notes
- * 2010-10-15 Bernard first version
- * 2010-10-15 lgnq modified for LS1B
- */
-
-#include <rtthread.h>
-#include "ls1b.h"
-
-#define MAX_INTR 32
-
-extern rt_uint32_t rt_interrupt_nest;
-rt_uint32_t rt_interrupt_from_thread;
-rt_uint32_t rt_interrupt_to_thread;
-rt_uint32_t rt_thread_switch_interrupt_flag;
-
-static rt_isr_handler_t irq_handle_table[MAX_INTR];
-void rt_interrupt_dispatch(void *ptreg);
-void rt_hw_timer_handler();
-
-static struct ls1b_intc_regs volatile *ls1b_hw0_icregs
- = (struct ls1b_intc_regs volatile *)(LS1B_INTREG_BASE);
-
-/**
- * @addtogroup Loongson LS1B
- */
-
-/*@{*/
-
-void rt_hw_interrupt_handler(int vector)
-{
- rt_kprintf("Unhandled interrupt %d occured!!!\n", vector);
-}
-
-/**
- * This function will initialize hardware interrupt
- */
-void rt_hw_interrupt_init(void)
-{
- rt_int32_t index;
-
- /* pci active low */
- ls1b_hw0_icregs->int_pol = -1; //must be done here 20110802 lgnq
- /* make all interrupts level triggered */
- (ls1b_hw0_icregs+0)->int_edge = 0x0000e000;
- /* mask all interrupts */
- (ls1b_hw0_icregs+0)->int_clr = 0xffffffff;
-
- for (index = 0; index < MAX_INTR; index ++)
- {
- irq_handle_table[index] = (rt_isr_handler_t)rt_hw_interrupt_handler;
- }
-
- /* init interrupt nest, and context in thread sp */
- rt_interrupt_nest = 0;
- rt_interrupt_from_thread = 0;
- rt_interrupt_to_thread = 0;
- rt_thread_switch_interrupt_flag = 0;
-}
-
-/**
- * This function will mask a interrupt.
- * @param vector the interrupt number
- */
-void rt_hw_interrupt_mask(int vector)
-{
- /* mask interrupt */
- (ls1b_hw0_icregs+(vector>>5))->int_en &= ~(1 << (vector&0x1f));
-}
-
-/**
- * This function will un-mask a interrupt.
- * @param vector the interrupt number
- */
-void rt_hw_interrupt_umask(int vector)
-{
- (ls1b_hw0_icregs+(vector>>5))->int_en |= (1 << (vector&0x1f));
-}
-
-/**
- * This function will install a interrupt service routine to a interrupt.
- * @param vector the interrupt number
- * @param new_handler the interrupt service routine to be installed
- * @param old_handler the old interrupt service routine
- */
-void rt_hw_interrupt_install(int vector, rt_isr_handler_t new_handler, rt_isr_handler_t *old_handler)
-{
- if (vector >= 0 && vector < MAX_INTR)
- {
- if (old_handler != RT_NULL)
- *old_handler = irq_handle_table[vector];
- if (new_handler != RT_NULL)
- irq_handle_table[vector] = (rt_isr_handler_t)new_handler;
- }
-}
-
-void rt_interrupt_dispatch(void *ptreg)
-{
- int i;
- rt_isr_handler_t irq_func;
- static rt_uint32_t status = 0;
- rt_uint32_t c0_status;
- rt_uint32_t c0_cause;
- volatile rt_uint32_t cause_im;
- volatile rt_uint32_t status_im;
- rt_uint32_t pending_im;
-
- /* check os timer */
- c0_status = read_c0_status();
- c0_cause = read_c0_cause();
-
- cause_im = c0_cause & ST0_IM;
- status_im = c0_status & ST0_IM;
- pending_im = cause_im & status_im;
-
- if (pending_im & CAUSEF_IP7)
- {
- rt_hw_timer_handler();
- }
-
- if (pending_im & CAUSEF_IP2)
- {
- /* the hardware interrupt */
- status = ls1b_hw0_icregs->int_isr;
- if (!status)
- return;
-
- for (i = MAX_INTR; i > 0; --i)
- {
- if ((status & (1<<i)))
- {
- status &= ~(1<<i);
- irq_func = irq_handle_table[i];
-
- /* do interrupt */
- (*irq_func)(i);
-
- /* ack interrupt */
- ls1b_hw0_icregs->int_clr |= (1 << i);
- }
- }
- }
- else if (pending_im & CAUSEF_IP3)
- {
- rt_kprintf("%s %d\r\n", __FUNCTION__, __LINE__);
- }
- else if (pending_im & CAUSEF_IP4)
- {
- rt_kprintf("%s %d\r\n", __FUNCTION__, __LINE__);
- }
- else if (pending_im & CAUSEF_IP5)
- {
- rt_kprintf("%s %d\r\n", __FUNCTION__, __LINE__);
- }
- else if (pending_im & CAUSEF_IP6)
- {
- rt_kprintf("%s %d\r\n", __FUNCTION__, __LINE__);
- }
-}
-
-/*@}*/
+/* + * File : interrupt.c + * This file is part of RT-Thread RTOS + * COPYRIGHT (C) 2006 - 2011, RT-Thread Development Team + * + * The license and distribution terms for this file may be + * found in the file LICENSE in this distribution or at + * http://www.rt-thread.org/license/LICENSE + * + * Change Logs: + * Date Author Notes + * 2010-10-15 Bernard first version + * 2010-10-15 lgnq modified for LS1B + */ + +#include <rtthread.h> +#include "ls1b.h" + +#define MAX_INTR 32 + +extern rt_uint32_t rt_interrupt_nest; +rt_uint32_t rt_interrupt_from_thread; +rt_uint32_t rt_interrupt_to_thread; +rt_uint32_t rt_thread_switch_interrupt_flag; + +static rt_isr_handler_t irq_handle_table[MAX_INTR]; +void rt_interrupt_dispatch(void *ptreg); +void rt_hw_timer_handler(); + +static struct ls1b_intc_regs volatile *ls1b_hw0_icregs + = (struct ls1b_intc_regs volatile *)(LS1B_INTREG_BASE); + +/** + * @addtogroup Loongson LS1B + */ + +/*@{*/ + +void rt_hw_interrupt_handler(int vector) +{ + rt_kprintf("Unhandled interrupt %d occured!!!\n", vector); +} + +/** + * This function will initialize hardware interrupt + */ +void rt_hw_interrupt_init(void) +{ + rt_int32_t index; + + /* pci active low */ + ls1b_hw0_icregs->int_pol = -1; //must be done here 20110802 lgnq + /* make all interrupts level triggered */ + (ls1b_hw0_icregs+0)->int_edge = 0x0000e000; + /* mask all interrupts */ + (ls1b_hw0_icregs+0)->int_clr = 0xffffffff; + + for (index = 0; index < MAX_INTR; index ++) + { + irq_handle_table[index] = (rt_isr_handler_t)rt_hw_interrupt_handler; + } + + /* init interrupt nest, and context in thread sp */ + rt_interrupt_nest = 0; + rt_interrupt_from_thread = 0; + rt_interrupt_to_thread = 0; + rt_thread_switch_interrupt_flag = 0; +} + +/** + * This function will mask a interrupt. + * @param vector the interrupt number + */ +void rt_hw_interrupt_mask(int vector) +{ + /* mask interrupt */ + (ls1b_hw0_icregs+(vector>>5))->int_en &= ~(1 << (vector&0x1f)); +} + +/** + * This function will un-mask a interrupt. + * @param vector the interrupt number + */ +void rt_hw_interrupt_umask(int vector) +{ + (ls1b_hw0_icregs+(vector>>5))->int_en |= (1 << (vector&0x1f)); +} + +/** + * This function will install a interrupt service routine to a interrupt. + * @param vector the interrupt number + * @param new_handler the interrupt service routine to be installed + * @param old_handler the old interrupt service routine + */ +void rt_hw_interrupt_install(int vector, rt_isr_handler_t new_handler, rt_isr_handler_t *old_handler) +{ + if (vector >= 0 && vector < MAX_INTR) + { + if (old_handler != RT_NULL) + *old_handler = irq_handle_table[vector]; + if (new_handler != RT_NULL) + irq_handle_table[vector] = (rt_isr_handler_t)new_handler; + } +} + +void rt_interrupt_dispatch(void *ptreg) +{ + int i; + rt_isr_handler_t irq_func; + static rt_uint32_t status = 0; + rt_uint32_t c0_status; + rt_uint32_t c0_cause; + volatile rt_uint32_t cause_im; + volatile rt_uint32_t status_im; + rt_uint32_t pending_im; + + /* check os timer */ + c0_status = read_c0_status(); + c0_cause = read_c0_cause(); + + cause_im = c0_cause & ST0_IM; + status_im = c0_status & ST0_IM; + pending_im = cause_im & status_im; + + if (pending_im & CAUSEF_IP7) + { + rt_hw_timer_handler(); + } + + if (pending_im & CAUSEF_IP2) + { + /* the hardware interrupt */ + status = ls1b_hw0_icregs->int_isr; + if (!status) + return; + + for (i = MAX_INTR; i > 0; --i) + { + if ((status & (1<<i))) + { + status &= ~(1<<i); + irq_func = irq_handle_table[i]; + + /* do interrupt */ + (*irq_func)(i); + + /* ack interrupt */ + ls1b_hw0_icregs->int_clr |= (1 << i); + } + } + } + else if (pending_im & CAUSEF_IP3) + { + rt_kprintf("%s %d\r\n", __FUNCTION__, __LINE__); + } + else if (pending_im & CAUSEF_IP4) + { + rt_kprintf("%s %d\r\n", __FUNCTION__, __LINE__); + } + else if (pending_im & CAUSEF_IP5) + { + rt_kprintf("%s %d\r\n", __FUNCTION__, __LINE__); + } + else if (pending_im & CAUSEF_IP6) + { + rt_kprintf("%s %d\r\n", __FUNCTION__, __LINE__); + } +} + +/*@}*/ diff --git a/libcpu/mips/loongson_1b/mipscfg.c b/libcpu/mips/loongson_1b/mipscfg.c index 12907f023c..10dd3fee9e 100644 --- a/libcpu/mips/loongson_1b/mipscfg.c +++ b/libcpu/mips/loongson_1b/mipscfg.c @@ -1,82 +1,82 @@ -/*
- * File : mipscfg.c
- * This file is part of RT-Thread RTOS
- * COPYRIGHT (C) 2006 - 2011, RT-Thread Development Team
- *
- * The license and distribution terms for this file may be
- * found in the file LICENSE in this distribution or at
- * http://www.rt-thread.org/license/LICENSE
- *
- * Change Logs:
- * Date Author Notes
- * 2010-05-27 swkyer first version
- */
-#include <rtthread.h>
-#include "../common/mipsregs.h"
-#include "../common/mipscfg.h"
-
-mips32_core_cfg_t g_mips_core =
-{
- 16, /* icache_line_size */
- 256, /* icache_lines_per_way */
- 4, /* icache_ways */
- 16, /* dcache_line_size */
- 256, /* dcache_lines_per_way */
- 4, /* dcache_ways */
- 16, /* max_tlb_entries */
-};
-
-static rt_uint16_t m_pow(rt_uint16_t b, rt_uint16_t n)
-{
- rt_uint16_t rets = 1;
-
- while (n--)
- rets *= b;
-
- return rets;
-}
-
-static rt_uint16_t m_log2(rt_uint16_t b)
-{
- rt_uint16_t rets = 0;
-
- while (b != 1)
- {
- b /= 2;
- rets++;
- }
-
- return rets;
-}
-
-/**
- * read core attribute
- */
-void mips32_cfg_init(void)
-{
- rt_uint16_t val;
- rt_uint32_t cp0_config1;
-
- cp0_config1 = read_c0_config();
- if (cp0_config1 & 0x80000000)
- {
- cp0_config1 = read_c0_config1();
-
- val = (cp0_config1 & (7<<22))>>22;
- g_mips_core.icache_lines_per_way = 64 * m_pow(2, val);
- val = (cp0_config1 & (7<<19))>>19;
- g_mips_core.icache_line_size = 2 * m_pow(2, val);
- val = (cp0_config1 & (7<<16))>>16;
- g_mips_core.icache_ways = val + 1;
-
- val = (cp0_config1 & (7<<13))>>13;
- g_mips_core.dcache_lines_per_way = 64 * m_pow(2, val);
- val = (cp0_config1 & (7<<10))>>10;
- g_mips_core.dcache_line_size = 2 * m_pow(2, val);
- val = (cp0_config1 & (7<<7))>>7;
- g_mips_core.dcache_ways = val + 1;
-
- val = (cp0_config1 & (0x3F<<25))>>25;
- g_mips_core.max_tlb_entries = val + 1;
- }
-}
+/* + * File : mipscfg.c + * This file is part of RT-Thread RTOS + * COPYRIGHT (C) 2006 - 2011, RT-Thread Development Team + * + * The license and distribution terms for this file may be + * found in the file LICENSE in this distribution or at + * http://www.rt-thread.org/license/LICENSE + * + * Change Logs: + * Date Author Notes + * 2010-05-27 swkyer first version + */ +#include <rtthread.h> +#include "../common/mipsregs.h" +#include "../common/mipscfg.h" + +mips32_core_cfg_t g_mips_core = +{ + 16, /* icache_line_size */ + 256, /* icache_lines_per_way */ + 4, /* icache_ways */ + 16, /* dcache_line_size */ + 256, /* dcache_lines_per_way */ + 4, /* dcache_ways */ + 16, /* max_tlb_entries */ +}; + +static rt_uint16_t m_pow(rt_uint16_t b, rt_uint16_t n) +{ + rt_uint16_t rets = 1; + + while (n--) + rets *= b; + + return rets; +} + +static rt_uint16_t m_log2(rt_uint16_t b) +{ + rt_uint16_t rets = 0; + + while (b != 1) + { + b /= 2; + rets++; + } + + return rets; +} + +/** + * read core attribute + */ +void mips32_cfg_init(void) +{ + rt_uint16_t val; + rt_uint32_t cp0_config1; + + cp0_config1 = read_c0_config(); + if (cp0_config1 & 0x80000000) + { + cp0_config1 = read_c0_config1(); + + val = (cp0_config1 & (7<<22))>>22; + g_mips_core.icache_lines_per_way = 64 * m_pow(2, val); + val = (cp0_config1 & (7<<19))>>19; + g_mips_core.icache_line_size = 2 * m_pow(2, val); + val = (cp0_config1 & (7<<16))>>16; + g_mips_core.icache_ways = val + 1; + + val = (cp0_config1 & (7<<13))>>13; + g_mips_core.dcache_lines_per_way = 64 * m_pow(2, val); + val = (cp0_config1 & (7<<10))>>10; + g_mips_core.dcache_line_size = 2 * m_pow(2, val); + val = (cp0_config1 & (7<<7))>>7; + g_mips_core.dcache_ways = val + 1; + + val = (cp0_config1 & (0x3F<<25))>>25; + g_mips_core.max_tlb_entries = val + 1; + } +} diff --git a/libcpu/mips/loongson_1b/start_gcc.S b/libcpu/mips/loongson_1b/start_gcc.S index dc6e51849a..fd98335671 100644 --- a/libcpu/mips/loongson_1b/start_gcc.S +++ b/libcpu/mips/loongson_1b/start_gcc.S @@ -1,137 +1,137 @@ -/*
- * File : start_gcc.S
- * This file is part of RT-Thread RTOS
- * COPYRIGHT (C) 2006 - 2011, RT-Thread Development Team
- *
- * The license and distribution terms for this file may be
- * found in the file LICENSE in this distribution or at
- * http://www.rt-thread.org/license/LICENSE
- *
- * Change Logs:
- * Date Author Notes
- * 2010-05-17 swkyer first version
- * 2010-09-04 bernard porting to Jz47xx
- */
-
-#include "../common/mips.inc"
-#include "../common/stackframe.h"
-
- .section ".start", "ax"
- .set noreorder
-
- /* the program entry */
- .globl _start
-_start:
- .set noreorder
- la ra, _start
-
- /* disable interrupt */
- mfc0 t0, CP0_STATUS
- and t0, 0xfffffffe # By default it will be disabled.
- mtc0 t0, CP0_STATUS # Set CPU to disable interrupt.
- nop
-
- /* disable cache */
- mfc0 t0, CP0_CONFIG
- and t0, 0xfffffff8
- or t0, 0x2 # disable,!default value is not it!
- mtc0 t0, CP0_CONFIG # Set CPU to disable cache.
- nop
-
- /* setup stack pointer */
- li sp, SYSTEM_STACK
- la gp, _gp
-
- /* clear bss */
- la t0, __bss_start
- la t1, __bss_end
-_clr_bss_loop:
- sw zero, 0(t0)
- bne t0, t1, _clr_bss_loop
- addiu t0, t0, 4
-
- /* jump to RT-Thread RTOS */
- jal rtthread_startup
- nop
-
- /* restart, never die */
- j _start
- nop
- .set reorder
-
- .globl cp0_get_cause
-cp0_get_cause:
- mfc0 v0, CP0_CAUSE
- jr ra
- nop
-
- .globl cp0_get_status
-cp0_get_status:
- mfc0 v0, CP0_STATUS
- jr ra
- nop
-
- .globl cp0_get_hi
-cp0_get_hi:
- mfhi v0
- jr ra
- nop
-
- .globl cp0_get_lo
-cp0_get_lo:
- mflo v0
- jr ra
- nop
-
- .extern tlb_refill_handler
- .extern cache_error_handler
-
- /* Exception Handler */
-
- /* 0x0 - TLB refill handler */
- .section .vectors.1, "ax", %progbits
- .global tlb_refill_exception
- .type tlb_refill_exception,@function
-tlb_refill_exception:
- j tlb_refill_handler
- nop
-
- /* 0x100 - Cache error handler */
- .section .vectors.2, "ax", %progbits
- j cache_error_handler
- nop
-
- /* 0x180 - Exception/Interrupt handler */
- .section .vectors.3, "ax", %progbits
- .global general_exception
- .type general_exception,@function
-general_exception:
- j _general_exception_handler
- nop
-
- /* 0x200 - Special Exception Interrupt handler (when IV is set in CP0_CAUSE) */
- .section .vectors.4, "ax", %progbits
- .global irq_exception
- .type irq_exception,@function
-irq_exception:
- j _irq_handler
- nop
-
- .section .vectors, "ax", %progbits
- .extern mips_irq_handle
-
- /* general exception handler */
-_general_exception_handler:
- .set noreorder
- la k0, mips_irq_handle
- jr k0
- nop
- .set reorder
-
- /* interrupt handler */
-_irq_handler:
- .set noreorder
- la k0, mips_irq_handle
- jr k0
- nop
- .set reorder
+/* + * File : start_gcc.S + * This file is part of RT-Thread RTOS + * COPYRIGHT (C) 2006 - 2011, RT-Thread Development Team + * + * The license and distribution terms for this file may be + * found in the file LICENSE in this distribution or at + * http://www.rt-thread.org/license/LICENSE + * + * Change Logs: + * Date Author Notes + * 2010-05-17 swkyer first version + * 2010-09-04 bernard porting to Jz47xx + */ + +#include "../common/mips.inc" +#include "../common/stackframe.h" + + .section ".start", "ax" + .set noreorder + + /* the program entry */ + .globl _start +_start: + .set noreorder + la ra, _start + + /* disable interrupt */ + mfc0 t0, CP0_STATUS + and t0, 0xfffffffe # By default it will be disabled. + mtc0 t0, CP0_STATUS # Set CPU to disable interrupt. + nop + + /* disable cache */ + mfc0 t0, CP0_CONFIG + and t0, 0xfffffff8 + or t0, 0x2 # disable,!default value is not it! + mtc0 t0, CP0_CONFIG # Set CPU to disable cache. + nop + + /* setup stack pointer */ + li sp, SYSTEM_STACK + la gp, _gp + + /* clear bss */ + la t0, __bss_start + la t1, __bss_end +_clr_bss_loop: + sw zero, 0(t0) + bne t0, t1, _clr_bss_loop + addiu t0, t0, 4 + + /* jump to RT-Thread RTOS */ + jal rtthread_startup + nop + + /* restart, never die */ + j _start + nop + .set reorder + + .globl cp0_get_cause +cp0_get_cause: + mfc0 v0, CP0_CAUSE + jr ra + nop + + .globl cp0_get_status +cp0_get_status: + mfc0 v0, CP0_STATUS + jr ra + nop + + .globl cp0_get_hi +cp0_get_hi: + mfhi v0 + jr ra + nop + + .globl cp0_get_lo +cp0_get_lo: + mflo v0 + jr ra + nop + + .extern tlb_refill_handler + .extern cache_error_handler + + /* Exception Handler */ + + /* 0x0 - TLB refill handler */ + .section .vectors.1, "ax", %progbits + .global tlb_refill_exception + .type tlb_refill_exception,@function +tlb_refill_exception: + j tlb_refill_handler + nop + + /* 0x100 - Cache error handler */ + .section .vectors.2, "ax", %progbits + j cache_error_handler + nop + + /* 0x180 - Exception/Interrupt handler */ + .section .vectors.3, "ax", %progbits + .global general_exception + .type general_exception,@function +general_exception: + j _general_exception_handler + nop + + /* 0x200 - Special Exception Interrupt handler (when IV is set in CP0_CAUSE) */ + .section .vectors.4, "ax", %progbits + .global irq_exception + .type irq_exception,@function +irq_exception: + j _irq_handler + nop + + .section .vectors, "ax", %progbits + .extern mips_irq_handle + + /* general exception handler */ +_general_exception_handler: + .set noreorder + la k0, mips_irq_handle + jr k0 + nop + .set reorder + + /* interrupt handler */ +_irq_handler: + .set noreorder + la k0, mips_irq_handle + jr k0 + nop + .set reorder diff --git a/libcpu/mips/pic32/context_gcc.S b/libcpu/mips/pic32/context_gcc.S index 924f60f910..3e820fb9d8 100644 --- a/libcpu/mips/pic32/context_gcc.S +++ b/libcpu/mips/pic32/context_gcc.S @@ -1,121 +1,121 @@ -#include <p32xxxx.h>
-#include "../common/mips.inc"
-#include "../common/stackframe.h"
-
- .section ".text", "ax"
- .set noat
- .set noreorder
-
-/*
- * rt_base_t rt_hw_interrupt_disable()
- */
- .globl rt_hw_interrupt_disable
-rt_hw_interrupt_disable:
- mfc0 v0, CP0_STATUS /* v0 = status */
- addiu v1, zero, -2 /* v1 = 0-2 = 0xFFFFFFFE */
- and v1, v0, v1 /* v1 = v0 & 0xFFFFFFFE */
- mtc0 v1, CP0_STATUS /* status = v1 */
- jr ra
- nop
-
-/*
- * void rt_hw_interrupt_enable(rt_base_t level)
- */
- .globl rt_hw_interrupt_enable
-rt_hw_interrupt_enable:
- mtc0 a0, CP0_STATUS
- jr ra
- nop
-
-/*
- * void rt_hw_context_switch_to(rt_uint32 to)/*
- * a0 --> to
- */
- .globl rt_hw_context_switch_to
-rt_hw_context_switch_to:
- lw sp, 0(a0) /* get new task stack pointer */
-
- RESTORE_ALL_AND_RET
-
-/*
- * void rt_hw_context_switch(rt_uint32 from, rt_uint32 to)
- * a0 --> from
- * a1 --> to
- */
- .globl rt_hw_context_switch
-rt_hw_context_switch:
- mtc0 ra, CP0_EPC
- SAVE_ALL
-
- sw sp, 0(a0) /* store sp in preempted tasks TCB */
- lw sp, 0(a1) /* get new task stack pointer */
-
- RESTORE_ALL_AND_RET
-
-/*
- * void rt_hw_context_switch_interrupt(rt_uint32 from, rt_uint32 to)/*
- */
- .globl rt_thread_switch_interrupt_flag
- .globl rt_interrupt_from_thread
- .globl rt_interrupt_to_thread
- .globl rt_hw_context_switch_interrupt
-rt_hw_context_switch_interrupt:
- la t0, rt_thread_switch_interrupt_flag
- lw t1, 0(t0)
- nop
- bnez t1, _reswitch
- nop
- li t1, 0x01 /* set rt_thread_switch_interrupt_flag to 1 */
- sw t1, 0(t0)
- la t0, rt_interrupt_from_thread /* set rt_interrupt_from_thread */
- sw a0, 0(t0)
-_reswitch:
- la t0, rt_interrupt_to_thread /* set rt_interrupt_to_thread */
- sw a1, 0(t0)
-
- /* trigger the soft exception (causes context switch) */
- mfc0 t0, CP0_CAUSE /* t0 = Cause */
- ori t0, t0, (1<<8) /* t0 |= (1<<8) */
- mtc0 t0, CP0_CAUSE /* cause = t0 */
- addiu t1, zero, -257 /* t1 = ~(1<<8) */
- and t0, t0, t1 /* t0 &= t1 */
- mtc0 t0, CP0_CAUSE /* cause = t0 */
- jr ra
- nop
-
-/*
- * void __ISR(_CORE_SOFTWARE_0_VECTOR, ipl2) CoreSW0Handler(void)
- */
- .section ".text", "ax"
- .set noreorder
- .set noat
- .ent CoreSW0Handler
-
- .globl CoreSW0Handler
-CoreSW0Handler:
- SAVE_ALL
-
- /* mCS0ClearIntFlag(); */
- la t0, IFS0CLR /* t0 = IFS0CLR */
- addiu t1,zero,0x02 /* t1 = (1<<2) */
- sw t1, 0(t0) /* IFS0CLR = t1 */
-
- la k0, rt_thread_switch_interrupt_flag
- sw zero, 0(k0) /* clear flag */
-
- /*
- * switch to the new thread
- */
- la k0, rt_interrupt_from_thread
- lw k1, 0(k0)
- nop
- sw sp, 0(k1) /* store sp in preempted tasks's TCB */
-
- la k0, rt_interrupt_to_thread
- lw k1, 0(k0)
- nop
- lw sp, 0(k1) /* get new task's stack pointer */
-
- RESTORE_ALL_AND_RET
-
- .end CoreSW0Handler
+#include <p32xxxx.h> +#include "../common/mips.inc" +#include "../common/stackframe.h" + + .section ".text", "ax" + .set noat + .set noreorder + +/* + * rt_base_t rt_hw_interrupt_disable() + */ + .globl rt_hw_interrupt_disable +rt_hw_interrupt_disable: + mfc0 v0, CP0_STATUS /* v0 = status */ + addiu v1, zero, -2 /* v1 = 0-2 = 0xFFFFFFFE */ + and v1, v0, v1 /* v1 = v0 & 0xFFFFFFFE */ + mtc0 v1, CP0_STATUS /* status = v1 */ + jr ra + nop + +/* + * void rt_hw_interrupt_enable(rt_base_t level) + */ + .globl rt_hw_interrupt_enable +rt_hw_interrupt_enable: + mtc0 a0, CP0_STATUS + jr ra + nop + +/* + * void rt_hw_context_switch_to(rt_uint32 to)/* + * a0 --> to + */ + .globl rt_hw_context_switch_to +rt_hw_context_switch_to: + lw sp, 0(a0) /* get new task stack pointer */ + + RESTORE_ALL_AND_RET + +/* + * void rt_hw_context_switch(rt_uint32 from, rt_uint32 to) + * a0 --> from + * a1 --> to + */ + .globl rt_hw_context_switch +rt_hw_context_switch: + mtc0 ra, CP0_EPC + SAVE_ALL + + sw sp, 0(a0) /* store sp in preempted tasks TCB */ + lw sp, 0(a1) /* get new task stack pointer */ + + RESTORE_ALL_AND_RET + +/* + * void rt_hw_context_switch_interrupt(rt_uint32 from, rt_uint32 to)/* + */ + .globl rt_thread_switch_interrupt_flag + .globl rt_interrupt_from_thread + .globl rt_interrupt_to_thread + .globl rt_hw_context_switch_interrupt +rt_hw_context_switch_interrupt: + la t0, rt_thread_switch_interrupt_flag + lw t1, 0(t0) + nop + bnez t1, _reswitch + nop + li t1, 0x01 /* set rt_thread_switch_interrupt_flag to 1 */ + sw t1, 0(t0) + la t0, rt_interrupt_from_thread /* set rt_interrupt_from_thread */ + sw a0, 0(t0) +_reswitch: + la t0, rt_interrupt_to_thread /* set rt_interrupt_to_thread */ + sw a1, 0(t0) + + /* trigger the soft exception (causes context switch) */ + mfc0 t0, CP0_CAUSE /* t0 = Cause */ + ori t0, t0, (1<<8) /* t0 |= (1<<8) */ + mtc0 t0, CP0_CAUSE /* cause = t0 */ + addiu t1, zero, -257 /* t1 = ~(1<<8) */ + and t0, t0, t1 /* t0 &= t1 */ + mtc0 t0, CP0_CAUSE /* cause = t0 */ + jr ra + nop + +/* + * void __ISR(_CORE_SOFTWARE_0_VECTOR, ipl2) CoreSW0Handler(void) + */ + .section ".text", "ax" + .set noreorder + .set noat + .ent CoreSW0Handler + + .globl CoreSW0Handler +CoreSW0Handler: + SAVE_ALL + + /* mCS0ClearIntFlag(); */ + la t0, IFS0CLR /* t0 = IFS0CLR */ + addiu t1,zero,0x02 /* t1 = (1<<2) */ + sw t1, 0(t0) /* IFS0CLR = t1 */ + + la k0, rt_thread_switch_interrupt_flag + sw zero, 0(k0) /* clear flag */ + + /* + * switch to the new thread + */ + la k0, rt_interrupt_from_thread + lw k1, 0(k0) + nop + sw sp, 0(k1) /* store sp in preempted tasks's TCB */ + + la k0, rt_interrupt_to_thread + lw k1, 0(k0) + nop + lw sp, 0(k1) /* get new task's stack pointer */ + + RESTORE_ALL_AND_RET + + .end CoreSW0Handler diff --git a/libcpu/mips/pic32/cpuport.c b/libcpu/mips/pic32/cpuport.c index 0425004de1..3f08d57167 100644 --- a/libcpu/mips/pic32/cpuport.c +++ b/libcpu/mips/pic32/cpuport.c @@ -1,96 +1,96 @@ -/*
- * File : cpuport.c
- * This file is part of RT-Thread RTOS
- * COPYRIGHT (C) 2009 - 2011, RT-Thread Development Team
- *
- * The license and distribution terms for this file may be
- * found in the file LICENSE in this distribution or at
- * http://www.rt-thread.org/license/LICENSE
- *
- * Change Logs:
- * Date Author Notes
- * 20011-05-23 aozima the first version for PIC32.
- * 20011-09-05 aozima merge all of C source code into cpuport.c.
- */
-#include <rtthread.h>
-
-/**
- * @addtogroup PIC32
- */
-/*@{*/
-
-/* exception and interrupt handler table */
-rt_uint32_t rt_interrupt_from_thread, rt_interrupt_to_thread;
-rt_uint32_t rt_thread_switch_interrupt_flag;
-
-rt_uint32_t __attribute__((nomips16)) _get_gp(void)
-{
- rt_uint32_t result;
-
- // get the gp reg
- asm volatile("move %0, $28" : "=r"(result));
-
- return result;
-}
-
-/**
- * This function will initialize thread stack
- *
- * @param tentry the entry of thread
- * @param parameter the parameter of entry
- * @param stack_addr the beginning stack address
- * @param texit the function will be called when thread exit
- *
- * @return stack address
- */
-rt_uint8_t *rt_hw_stack_init(void *tentry, void *parameter, rt_uint8_t *stack_addr, void *texit)
-{
- rt_uint32_t *stk;
-
- /** Start at stack top */
- stk = (rt_uint32_t *)stack_addr;
- *(stk) = (rt_uint32_t) tentry; /* pc: Entry Point */
- *(--stk) = (rt_uint32_t) 0x00800000; /* c0_cause: IV=1, */
- *(--stk) = (rt_uint32_t) 0; /* c0_badvaddr */
- *(--stk) = (rt_uint32_t) 0; /* lo */
- *(--stk) = (rt_uint32_t) 0; /* hi */
- *(--stk) = (rt_uint32_t) 1; /* C0_SR: IE = En, */
- *(--stk) = (rt_uint32_t) texit; /* 31 ra */
- *(--stk) = (rt_uint32_t) 0x0000001e; /* 30 s8 */
- *(--stk) = (rt_uint32_t) stack_addr; /* 29 sp */
- *(--stk) = (rt_uint32_t) _get_gp(); /* 28 gp */
- *(--stk) = (rt_uint32_t) 0x0000001b; /* 27 k1 */
- *(--stk) = (rt_uint32_t) 0x0000001a; /* 26 k0 */
- *(--stk) = (rt_uint32_t) 0x00000019; /* 25 t9 */
- *(--stk) = (rt_uint32_t) 0x00000018; /* 24 t8 */
- *(--stk) = (rt_uint32_t) 0x00000017; /* 23 s7 */
- *(--stk) = (rt_uint32_t) 0x00000016; /* 22 s6 */
- *(--stk) = (rt_uint32_t) 0x00000015; /* 21 s5 */
- *(--stk) = (rt_uint32_t) 0x00000014; /* 20 s4 */
- *(--stk) = (rt_uint32_t) 0x00000013; /* 19 s3 */
- *(--stk) = (rt_uint32_t) 0x00000012; /* 18 s2 */
- *(--stk) = (rt_uint32_t) 0x00000011; /* 17 s1 */
- *(--stk) = (rt_uint32_t) 0x00000010; /* 16 s0 */
- *(--stk) = (rt_uint32_t) 0x0000000f; /* 15 t7 */
- *(--stk) = (rt_uint32_t) 0x0000000e; /* 14 t6 */
- *(--stk) = (rt_uint32_t) 0x0000000d; /* 13 t5 */
- *(--stk) = (rt_uint32_t) 0x0000000c; /* 12 t4 */
- *(--stk) = (rt_uint32_t) 0x0000000b; /* 11 t3 */
- *(--stk) = (rt_uint32_t) 0x0000000a; /* 10 t2 */
- *(--stk) = (rt_uint32_t) 0x00000009; /* 9 t1 */
- *(--stk) = (rt_uint32_t) 0x00000008; /* 8 t0 */
- *(--stk) = (rt_uint32_t) 0x00000007; /* 7 a3 */
- *(--stk) = (rt_uint32_t) 0x00000006; /* 6 a2 */
- *(--stk) = (rt_uint32_t) 0x00000005; /* 5 a1 */
- *(--stk) = (rt_uint32_t) parameter; /* 4 a0 */
- *(--stk) = (rt_uint32_t) 0x00000003; /* 3 v1 */
- *(--stk) = (rt_uint32_t) 0x00000002; /* 2 v0 */
- *(--stk) = (rt_uint32_t) 0x00000001; /* 1 at */
- *(--stk) = (rt_uint32_t) 0x00000000; /* 0 zero */
-
- /* return task's current stack address */
- return (rt_uint8_t *)stk;
-}
-
-
-/*@}*/
+/* + * File : cpuport.c + * This file is part of RT-Thread RTOS + * COPYRIGHT (C) 2009 - 2011, RT-Thread Development Team + * + * The license and distribution terms for this file may be + * found in the file LICENSE in this distribution or at + * http://www.rt-thread.org/license/LICENSE + * + * Change Logs: + * Date Author Notes + * 20011-05-23 aozima the first version for PIC32. + * 20011-09-05 aozima merge all of C source code into cpuport.c. + */ +#include <rtthread.h> + +/** + * @addtogroup PIC32 + */ +/*@{*/ + +/* exception and interrupt handler table */ +rt_uint32_t rt_interrupt_from_thread, rt_interrupt_to_thread; +rt_uint32_t rt_thread_switch_interrupt_flag; + +rt_uint32_t __attribute__((nomips16)) _get_gp(void) +{ + rt_uint32_t result; + + // get the gp reg + asm volatile("move %0, $28" : "=r"(result)); + + return result; +} + +/** + * This function will initialize thread stack + * + * @param tentry the entry of thread + * @param parameter the parameter of entry + * @param stack_addr the beginning stack address + * @param texit the function will be called when thread exit + * + * @return stack address + */ +rt_uint8_t *rt_hw_stack_init(void *tentry, void *parameter, rt_uint8_t *stack_addr, void *texit) +{ + rt_uint32_t *stk; + + /** Start at stack top */ + stk = (rt_uint32_t *)stack_addr; + *(stk) = (rt_uint32_t) tentry; /* pc: Entry Point */ + *(--stk) = (rt_uint32_t) 0x00800000; /* c0_cause: IV=1, */ + *(--stk) = (rt_uint32_t) 0; /* c0_badvaddr */ + *(--stk) = (rt_uint32_t) 0; /* lo */ + *(--stk) = (rt_uint32_t) 0; /* hi */ + *(--stk) = (rt_uint32_t) 1; /* C0_SR: IE = En, */ + *(--stk) = (rt_uint32_t) texit; /* 31 ra */ + *(--stk) = (rt_uint32_t) 0x0000001e; /* 30 s8 */ + *(--stk) = (rt_uint32_t) stack_addr; /* 29 sp */ + *(--stk) = (rt_uint32_t) _get_gp(); /* 28 gp */ + *(--stk) = (rt_uint32_t) 0x0000001b; /* 27 k1 */ + *(--stk) = (rt_uint32_t) 0x0000001a; /* 26 k0 */ + *(--stk) = (rt_uint32_t) 0x00000019; /* 25 t9 */ + *(--stk) = (rt_uint32_t) 0x00000018; /* 24 t8 */ + *(--stk) = (rt_uint32_t) 0x00000017; /* 23 s7 */ + *(--stk) = (rt_uint32_t) 0x00000016; /* 22 s6 */ + *(--stk) = (rt_uint32_t) 0x00000015; /* 21 s5 */ + *(--stk) = (rt_uint32_t) 0x00000014; /* 20 s4 */ + *(--stk) = (rt_uint32_t) 0x00000013; /* 19 s3 */ + *(--stk) = (rt_uint32_t) 0x00000012; /* 18 s2 */ + *(--stk) = (rt_uint32_t) 0x00000011; /* 17 s1 */ + *(--stk) = (rt_uint32_t) 0x00000010; /* 16 s0 */ + *(--stk) = (rt_uint32_t) 0x0000000f; /* 15 t7 */ + *(--stk) = (rt_uint32_t) 0x0000000e; /* 14 t6 */ + *(--stk) = (rt_uint32_t) 0x0000000d; /* 13 t5 */ + *(--stk) = (rt_uint32_t) 0x0000000c; /* 12 t4 */ + *(--stk) = (rt_uint32_t) 0x0000000b; /* 11 t3 */ + *(--stk) = (rt_uint32_t) 0x0000000a; /* 10 t2 */ + *(--stk) = (rt_uint32_t) 0x00000009; /* 9 t1 */ + *(--stk) = (rt_uint32_t) 0x00000008; /* 8 t0 */ + *(--stk) = (rt_uint32_t) 0x00000007; /* 7 a3 */ + *(--stk) = (rt_uint32_t) 0x00000006; /* 6 a2 */ + *(--stk) = (rt_uint32_t) 0x00000005; /* 5 a1 */ + *(--stk) = (rt_uint32_t) parameter; /* 4 a0 */ + *(--stk) = (rt_uint32_t) 0x00000003; /* 3 v1 */ + *(--stk) = (rt_uint32_t) 0x00000002; /* 2 v0 */ + *(--stk) = (rt_uint32_t) 0x00000001; /* 1 at */ + *(--stk) = (rt_uint32_t) 0x00000000; /* 0 zero */ + + /* return task's current stack address */ + return (rt_uint8_t *)stk; +} + + +/*@}*/ diff --git a/libcpu/mips/pic32/exceptions.c b/libcpu/mips/pic32/exceptions.c index ca3c0ae7b5..de5f70b7e1 100644 --- a/libcpu/mips/pic32/exceptions.c +++ b/libcpu/mips/pic32/exceptions.c @@ -60,7 +60,7 @@ static enum { static unsigned int _epc_code; static unsigned int _excep_addr; -
+ #include <rtthread.h> // this function overrides the normal _weak_ generic handler void _general_exception_handler(void) @@ -68,27 +68,27 @@ void _general_exception_handler(void) asm volatile("mfc0 %0,$13" : "=r" (_excep_code)); asm volatile("mfc0 %0,$14" : "=r" (_excep_addr)); - _excep_code = (_excep_code & 0x0000007C) >> 2;
-
- rt_kprintf("\r\n_excep_code : %08X\r\n",_excep_code);
- rt_kprintf("_excep_addr : %08X\r\n",_excep_addr);
- switch(_excep_code)
- {
- case EXCEP_IRQ:rt_kprintf("interrupt\r\n");break;
- case EXCEP_AdEL:rt_kprintf("address error exception (load or ifetch)\r\n");break;
- case EXCEP_AdES:rt_kprintf("address error exception (store)\r\n");break;
- case EXCEP_IBE:rt_kprintf("bus error (ifetch)\r\n");break;
- case EXCEP_DBE:rt_kprintf("bus error (load/store)\r\n");break;
- case EXCEP_Sys:rt_kprintf("syscall\r\n");break;
- case EXCEP_Bp:rt_kprintf("breakpoint\r\n");break;
- case EXCEP_RI:rt_kprintf("reserved instruction\r\n");break;
- case EXCEP_CpU:rt_kprintf("coprocessor unusable\r\n");break;
- case EXCEP_Overflow:rt_kprintf("arithmetic overflow\r\n");break;
- case EXCEP_Trap:rt_kprintf("trap (possible divide by zero)\r\n");break;
- case EXCEP_IS1:rt_kprintf("implementation specfic 1\r\n");break;
- case EXCEP_CEU:rt_kprintf("CorExtend Unuseable\r\n");break;
- case EXCEP_C2E:rt_kprintf("coprocessor 2\r\n");break;
- default : rt_kprintf("unkown exception\r\n");break;
+ _excep_code = (_excep_code & 0x0000007C) >> 2; + + rt_kprintf("\r\n_excep_code : %08X\r\n",_excep_code); + rt_kprintf("_excep_addr : %08X\r\n",_excep_addr); + switch(_excep_code) + { + case EXCEP_IRQ:rt_kprintf("interrupt\r\n");break; + case EXCEP_AdEL:rt_kprintf("address error exception (load or ifetch)\r\n");break; + case EXCEP_AdES:rt_kprintf("address error exception (store)\r\n");break; + case EXCEP_IBE:rt_kprintf("bus error (ifetch)\r\n");break; + case EXCEP_DBE:rt_kprintf("bus error (load/store)\r\n");break; + case EXCEP_Sys:rt_kprintf("syscall\r\n");break; + case EXCEP_Bp:rt_kprintf("breakpoint\r\n");break; + case EXCEP_RI:rt_kprintf("reserved instruction\r\n");break; + case EXCEP_CpU:rt_kprintf("coprocessor unusable\r\n");break; + case EXCEP_Overflow:rt_kprintf("arithmetic overflow\r\n");break; + case EXCEP_Trap:rt_kprintf("trap (possible divide by zero)\r\n");break; + case EXCEP_IS1:rt_kprintf("implementation specfic 1\r\n");break; + case EXCEP_CEU:rt_kprintf("CorExtend Unuseable\r\n");break; + case EXCEP_C2E:rt_kprintf("coprocessor 2\r\n");break; + default : rt_kprintf("unkown exception\r\n");break; } while (1) { diff --git a/libcpu/nios/nios_ii/context_gcc.S b/libcpu/nios/nios_ii/context_gcc.S index 3ccaff3b20..72746f457c 100644 --- a/libcpu/nios/nios_ii/context_gcc.S +++ b/libcpu/nios/nios_ii/context_gcc.S @@ -1,280 +1,280 @@ -/*
- * File : context_gcc.S
- * This file is part of RT-Thread RTOS
- * COPYRIGHT (C) 2006-2011, RT-Thread Development Team
- *
- * The license and distribution terms for this file may be
- * found in the file LICENSE in this distribution or at
- * http://www.rt-thread.org/license/LICENSE
- *
- * Change Logs:
- * Date Author Notes
- * 2011-02-14 aozima first implementation for Nios II.
- * 2011-02-20 aozima fix context&switch bug.
- */
-
-/**
- * @addtogroup NIOS_II
- */
-/*@{*/
-
-.text
-
-.set noat
-
-/*
- * rt_base_t rt_hw_interrupt_disable();
- */
-.global rt_hw_interrupt_disable
-.type rt_hw_interrupt_disable, %function
-rt_hw_interrupt_disable:
- rdctl r2, status /* return status */
- wrctl status, zero /* disable interrupt */
- ret
-
-/*
- * void rt_hw_interrupt_enable(rt_base_t level);
- */
-.global rt_hw_interrupt_enable
-.type rt_hw_interrupt_enable, %function
-rt_hw_interrupt_enable:
- wrctl status, r4 /* enable interrupt by argument */
- ret
-
-/* void rt_hw_context_switch_interrupt_do(void) */
-.global rt_hw_context_switch_interrupt_do
-.type rt_hw_context_switch_interrupt_do, %function
-rt_hw_context_switch_interrupt_do:
- /* save from thread */
- addi sp,sp,-72
-
- /* frist save r2,so that save status */
- stw r2, 4(sp)
-
- /* save status */
- /* when the interrupt happen,the interrupt is enable */
- movi r2, 1
- stw r2, 68(sp) /* status */
-
- stw r3, 8(sp)
- stw r4, 12(sp)
-
- /* get & save from thread pc */
- ldw r4,%gprel(rt_current_thread_entry)(gp)
- stw r4, 0(sp) /* thread pc */
-
- stw r5, 16(sp)
- stw r6, 20(sp)
- stw r7, 24(sp)
-
- stw r16, 28(sp)
- stw r17, 32(sp)
- stw r18, 36(sp)
- stw r19, 40(sp)
- stw r20, 44(sp)
- stw r21, 48(sp)
- stw r22, 52(sp)
- stw r23, 56(sp)
-
- stw fp, 60(sp)
- stw ra, 64(sp)
-
- /* save from thread sp */
- /* rt_interrupt_from_thread = &from_thread->sp */
- ldw r4, %gprel(rt_interrupt_from_thread)(gp)
- /* *r4(from_thread->sp) = sp */
- stw sp, (r4)
-
- /* clear rt_thread_switch_interrupt_flag */
- /* rt_thread_switch_interrupt_flag = 0 */
- stw zero,%gprel(rt_thread_switch_interrupt_flag)(gp)
-
- /* load to thread sp */
- /* r4 = rt_interrupt_to_thread(&to_thread->sp) */
- ldw r4, %gprel(rt_interrupt_to_thread)(gp)
- /* sp = to_thread->sp */
- ldw sp, (r4)
-
- ldw r2, 68(sp) /* status */
- wrctl estatus, r2
-
- ldw ea, 0(sp) /* thread pc */
- ldw r2, 4(sp)
- ldw r3, 8(sp)
- ldw r4, 12(sp)
- ldw r5, 16(sp)
- ldw r6, 20(sp)
- ldw r7, 24(sp)
-
- ldw r16, 28(sp)
- ldw r17, 32(sp)
- ldw r18, 36(sp)
- ldw r19, 40(sp)
- ldw r20, 44(sp)
- ldw r21, 48(sp)
- ldw r22, 52(sp)
- ldw r23, 56(sp)
-
- ldw fp, 60(sp)
- ldw ra, 64(sp)
-
- addi sp, sp, 72
-
- /* estatus --> status,ea --> pc */
- eret
-
-/*
- * void rt_hw_context_switch(rt_uint32 from, rt_uint32 to);
- * r4: from
- * r5: to
- */
-.global rt_hw_context_switch
-.type rt_hw_context_switch, %function
-rt_hw_context_switch:
- /* save from thread */
- addi sp,sp,-72
-
- /* frist save r2,so that save status */
- stw r2, 4(sp)
-
- /* save status */
- rdctl r2, status
- stw r2, 68(sp) /* status */
-
- stw ra, 0(sp) /* return from rt_hw_context_switch */
- stw r3, 8(sp)
- stw r4, 12(sp)
- stw r5, 16(sp)
- stw r6, 20(sp)
- stw r7, 24(sp)
-
- stw r16, 28(sp)
- stw r17, 32(sp)
- stw r18, 36(sp)
- stw r19, 40(sp)
- stw r20, 44(sp)
- stw r21, 48(sp)
- stw r22, 52(sp)
- stw r23, 56(sp)
-
- stw fp, 60(sp)
- stw ra, 64(sp)
-
- /* save form thread sp */
- /* from_thread->sp(r4) = sp */
- stw sp, (r4)
-
- /* update rt_interrupt_from_thread */
- /* rt_interrupt_from_thread = r4(from_thread->sp) */
- stw r4,%gprel(rt_interrupt_from_thread)(gp)
-
- /* update rt_interrupt_to_thread */
- /* rt_interrupt_to_thread = r5 */
- stw r5,%gprel(rt_interrupt_to_thread)(gp)
-
- /* get to thread sp */
- /* sp = rt_interrupt_to_thread(r5:to_thread->sp) */
- ldw sp, (r5)
-
- ldw r2, 68(sp) /* status */
- wrctl estatus, r2
-
- ldw ea, 0(sp) /* thread pc */
-
- ldw r2, 4(sp)
- ldw r3, 8(sp)
- ldw r4, 12(sp)
- ldw r5, 16(sp)
- ldw r6, 20(sp)
- ldw r7, 24(sp)
-
- ldw r16, 28(sp)
- ldw r17, 32(sp)
- ldw r18, 36(sp)
- ldw r19, 40(sp)
- ldw r20, 44(sp)
- ldw r21, 48(sp)
- ldw r22, 52(sp)
- ldw r23, 56(sp)
-
- ldw fp, 60(sp)
- ldw ra, 64(sp)
-
- addi sp, sp, 72
-
- /* estatus --> status,ea --> pc */
- eret
-
-/*
- * void rt_hw_context_switch_interrupt(rt_uint32 from, rt_uint32 to);
- * r4: from
- * r5: to
- */
-.global rt_hw_context_switch_interrupt
-.type rt_hw_context_switch_interrupt, %function
-rt_hw_context_switch_interrupt:
- /* if( rt_thread_switch_interrupt_flag != 0 ) _from_thread_not_change */
- ldw r2,%gprel(rt_thread_switch_interrupt_flag)(gp)
- bne r2,zero,_from_thread_not_change
-
-_from_thread_change:
- /* save ea -> rt_current_thread_entry */
- addi ea,ea,-4
- stw ea,%gprel(rt_current_thread_entry)(gp)
-
- /* set rt_thread_switch_interrupt_flag to 1 */
- movi r2, 1
- stw r2,%gprel(rt_thread_switch_interrupt_flag)(gp)
-
- /* update rt_interrupt_from_thread */
- stw r4,%gprel(rt_interrupt_from_thread)(gp)
-
-_from_thread_not_change:
- /* update rt_interrupt_to_thread */
- stw r5,%gprel(rt_interrupt_to_thread)(gp)
-
- ret
-
-/*
- * void rt_hw_context_switch_to(rt_uint32 to);
- * r4: to
- */
-.global rt_hw_context_switch_to
-.type rt_hw_context_switch_to, %function
-rt_hw_context_switch_to:
- /* save to thread */
- stw r4,%gprel(rt_interrupt_to_thread)(gp)
-
- /* get sp */
- ldw sp, (r4) // sp = *r4
-
- ldw r2, 68(sp) /* status */
- wrctl estatus, r2
-
- ldw ea, 0(sp) /* thread entry */
-
- ldw r2, 4(sp)
- ldw r3, 8(sp)
- ldw r4, 12(sp)
- ldw r5, 16(sp)
- ldw r6, 20(sp)
- ldw r7, 24(sp)
-
- ldw r16, 28(sp)
- ldw r17, 32(sp)
- ldw r18, 36(sp)
- ldw r19, 40(sp)
- ldw r20, 44(sp)
- ldw r21, 48(sp)
- ldw r22, 52(sp)
- ldw r23, 56(sp)
-
- ldw fp, 60(sp)
- ldw ra, 64(sp)
-
- addi sp, sp, 72
-
- /* estatus --> status,ea --> pc */
- eret
-
-/*@}*/
+/* + * File : context_gcc.S + * This file is part of RT-Thread RTOS + * COPYRIGHT (C) 2006-2011, RT-Thread Development Team + * + * The license and distribution terms for this file may be + * found in the file LICENSE in this distribution or at + * http://www.rt-thread.org/license/LICENSE + * + * Change Logs: + * Date Author Notes + * 2011-02-14 aozima first implementation for Nios II. + * 2011-02-20 aozima fix context&switch bug. + */ + +/** + * @addtogroup NIOS_II + */ +/*@{*/ + +.text + +.set noat + +/* + * rt_base_t rt_hw_interrupt_disable(); + */ +.global rt_hw_interrupt_disable +.type rt_hw_interrupt_disable, %function +rt_hw_interrupt_disable: + rdctl r2, status /* return status */ + wrctl status, zero /* disable interrupt */ + ret + +/* + * void rt_hw_interrupt_enable(rt_base_t level); + */ +.global rt_hw_interrupt_enable +.type rt_hw_interrupt_enable, %function +rt_hw_interrupt_enable: + wrctl status, r4 /* enable interrupt by argument */ + ret + +/* void rt_hw_context_switch_interrupt_do(void) */ +.global rt_hw_context_switch_interrupt_do +.type rt_hw_context_switch_interrupt_do, %function +rt_hw_context_switch_interrupt_do: + /* save from thread */ + addi sp,sp,-72 + + /* frist save r2,so that save status */ + stw r2, 4(sp) + + /* save status */ + /* when the interrupt happen,the interrupt is enable */ + movi r2, 1 + stw r2, 68(sp) /* status */ + + stw r3, 8(sp) + stw r4, 12(sp) + + /* get & save from thread pc */ + ldw r4,%gprel(rt_current_thread_entry)(gp) + stw r4, 0(sp) /* thread pc */ + + stw r5, 16(sp) + stw r6, 20(sp) + stw r7, 24(sp) + + stw r16, 28(sp) + stw r17, 32(sp) + stw r18, 36(sp) + stw r19, 40(sp) + stw r20, 44(sp) + stw r21, 48(sp) + stw r22, 52(sp) + stw r23, 56(sp) + + stw fp, 60(sp) + stw ra, 64(sp) + + /* save from thread sp */ + /* rt_interrupt_from_thread = &from_thread->sp */ + ldw r4, %gprel(rt_interrupt_from_thread)(gp) + /* *r4(from_thread->sp) = sp */ + stw sp, (r4) + + /* clear rt_thread_switch_interrupt_flag */ + /* rt_thread_switch_interrupt_flag = 0 */ + stw zero,%gprel(rt_thread_switch_interrupt_flag)(gp) + + /* load to thread sp */ + /* r4 = rt_interrupt_to_thread(&to_thread->sp) */ + ldw r4, %gprel(rt_interrupt_to_thread)(gp) + /* sp = to_thread->sp */ + ldw sp, (r4) + + ldw r2, 68(sp) /* status */ + wrctl estatus, r2 + + ldw ea, 0(sp) /* thread pc */ + ldw r2, 4(sp) + ldw r3, 8(sp) + ldw r4, 12(sp) + ldw r5, 16(sp) + ldw r6, 20(sp) + ldw r7, 24(sp) + + ldw r16, 28(sp) + ldw r17, 32(sp) + ldw r18, 36(sp) + ldw r19, 40(sp) + ldw r20, 44(sp) + ldw r21, 48(sp) + ldw r22, 52(sp) + ldw r23, 56(sp) + + ldw fp, 60(sp) + ldw ra, 64(sp) + + addi sp, sp, 72 + + /* estatus --> status,ea --> pc */ + eret + +/* + * void rt_hw_context_switch(rt_uint32 from, rt_uint32 to); + * r4: from + * r5: to + */ +.global rt_hw_context_switch +.type rt_hw_context_switch, %function +rt_hw_context_switch: + /* save from thread */ + addi sp,sp,-72 + + /* frist save r2,so that save status */ + stw r2, 4(sp) + + /* save status */ + rdctl r2, status + stw r2, 68(sp) /* status */ + + stw ra, 0(sp) /* return from rt_hw_context_switch */ + stw r3, 8(sp) + stw r4, 12(sp) + stw r5, 16(sp) + stw r6, 20(sp) + stw r7, 24(sp) + + stw r16, 28(sp) + stw r17, 32(sp) + stw r18, 36(sp) + stw r19, 40(sp) + stw r20, 44(sp) + stw r21, 48(sp) + stw r22, 52(sp) + stw r23, 56(sp) + + stw fp, 60(sp) + stw ra, 64(sp) + + /* save form thread sp */ + /* from_thread->sp(r4) = sp */ + stw sp, (r4) + + /* update rt_interrupt_from_thread */ + /* rt_interrupt_from_thread = r4(from_thread->sp) */ + stw r4,%gprel(rt_interrupt_from_thread)(gp) + + /* update rt_interrupt_to_thread */ + /* rt_interrupt_to_thread = r5 */ + stw r5,%gprel(rt_interrupt_to_thread)(gp) + + /* get to thread sp */ + /* sp = rt_interrupt_to_thread(r5:to_thread->sp) */ + ldw sp, (r5) + + ldw r2, 68(sp) /* status */ + wrctl estatus, r2 + + ldw ea, 0(sp) /* thread pc */ + + ldw r2, 4(sp) + ldw r3, 8(sp) + ldw r4, 12(sp) + ldw r5, 16(sp) + ldw r6, 20(sp) + ldw r7, 24(sp) + + ldw r16, 28(sp) + ldw r17, 32(sp) + ldw r18, 36(sp) + ldw r19, 40(sp) + ldw r20, 44(sp) + ldw r21, 48(sp) + ldw r22, 52(sp) + ldw r23, 56(sp) + + ldw fp, 60(sp) + ldw ra, 64(sp) + + addi sp, sp, 72 + + /* estatus --> status,ea --> pc */ + eret + +/* + * void rt_hw_context_switch_interrupt(rt_uint32 from, rt_uint32 to); + * r4: from + * r5: to + */ +.global rt_hw_context_switch_interrupt +.type rt_hw_context_switch_interrupt, %function +rt_hw_context_switch_interrupt: + /* if( rt_thread_switch_interrupt_flag != 0 ) _from_thread_not_change */ + ldw r2,%gprel(rt_thread_switch_interrupt_flag)(gp) + bne r2,zero,_from_thread_not_change + +_from_thread_change: + /* save ea -> rt_current_thread_entry */ + addi ea,ea,-4 + stw ea,%gprel(rt_current_thread_entry)(gp) + + /* set rt_thread_switch_interrupt_flag to 1 */ + movi r2, 1 + stw r2,%gprel(rt_thread_switch_interrupt_flag)(gp) + + /* update rt_interrupt_from_thread */ + stw r4,%gprel(rt_interrupt_from_thread)(gp) + +_from_thread_not_change: + /* update rt_interrupt_to_thread */ + stw r5,%gprel(rt_interrupt_to_thread)(gp) + + ret + +/* + * void rt_hw_context_switch_to(rt_uint32 to); + * r4: to + */ +.global rt_hw_context_switch_to +.type rt_hw_context_switch_to, %function +rt_hw_context_switch_to: + /* save to thread */ + stw r4,%gprel(rt_interrupt_to_thread)(gp) + + /* get sp */ + ldw sp, (r4) // sp = *r4 + + ldw r2, 68(sp) /* status */ + wrctl estatus, r2 + + ldw ea, 0(sp) /* thread entry */ + + ldw r2, 4(sp) + ldw r3, 8(sp) + ldw r4, 12(sp) + ldw r5, 16(sp) + ldw r6, 20(sp) + ldw r7, 24(sp) + + ldw r16, 28(sp) + ldw r17, 32(sp) + ldw r18, 36(sp) + ldw r19, 40(sp) + ldw r20, 44(sp) + ldw r21, 48(sp) + ldw r22, 52(sp) + ldw r23, 56(sp) + + ldw fp, 60(sp) + ldw ra, 64(sp) + + addi sp, sp, 72 + + /* estatus --> status,ea --> pc */ + eret + +/*@}*/ diff --git a/libcpu/nios/nios_ii/interrupt.c b/libcpu/nios/nios_ii/interrupt.c index 15c574901b..112eaa9223 100644 --- a/libcpu/nios/nios_ii/interrupt.c +++ b/libcpu/nios/nios_ii/interrupt.c @@ -1,22 +1,22 @@ -/*
- * File : interrupt.c
- * This file is part of RT-Thread RTOS
- * COPYRIGHT (C) 2009, RT-Thread Development Team
- *
- * The license and distribution terms for this file may be
- * found in the file LICENSE in this distribution or at
- * http://www.rt-thread.org/license/LICENSE
- *
- * Change Logs:
- * Date Author Notes
- * 2009-01-05 Bernard first version
- */
-
-#include <rtthread.h>
-
-/* exception and interrupt handler table */
-rt_uint32_t rt_interrupt_from_thread, rt_interrupt_to_thread;
-rt_uint32_t rt_thread_switch_interrupt_flag;
-rt_uint32_t rt_current_thread_entry;
-
-/*@}*/
+/* + * File : interrupt.c + * This file is part of RT-Thread RTOS + * COPYRIGHT (C) 2009, RT-Thread Development Team + * + * The license and distribution terms for this file may be + * found in the file LICENSE in this distribution or at + * http://www.rt-thread.org/license/LICENSE + * + * Change Logs: + * Date Author Notes + * 2009-01-05 Bernard first version + */ + +#include <rtthread.h> + +/* exception and interrupt handler table */ +rt_uint32_t rt_interrupt_from_thread, rt_interrupt_to_thread; +rt_uint32_t rt_thread_switch_interrupt_flag; +rt_uint32_t rt_current_thread_entry; + +/*@}*/ diff --git a/libcpu/nios/nios_ii/stack.c b/libcpu/nios/nios_ii/stack.c index 01fbb2c468..125bf2c578 100644 --- a/libcpu/nios/nios_ii/stack.c +++ b/libcpu/nios/nios_ii/stack.c @@ -1,22 +1,22 @@ -/*
- * File : stack.c
- * This file is part of RT-Thread RTOS
- * COPYRIGHT (C) 2006-2011, RT-Thread Development Team
- *
- * The license and distribution terms for this file may be
- * found in the file LICENSE in this distribution or at
- * http://www.rt-thread.org/license/LICENSE
- *
- * Change Logs:
- * Date Author Notes
- * 2011-02-14 aozima first implementation for Nios II.
- */
+/* + * File : stack.c + * This file is part of RT-Thread RTOS + * COPYRIGHT (C) 2006-2011, RT-Thread Development Team + * + * The license and distribution terms for this file may be + * found in the file LICENSE in this distribution or at + * http://www.rt-thread.org/license/LICENSE + * + * Change Logs: + * Date Author Notes + * 2011-02-14 aozima first implementation for Nios II. + */ #include <rtthread.h> -/**
- * @addtogroup NIOS_II
- */
+/** + * @addtogroup NIOS_II + */ /*@{*/ /** @@ -34,33 +34,33 @@ rt_uint8_t *rt_hw_stack_init(void *tentry, void *parameter, { unsigned long *stk; - stk = (unsigned long *)stack_addr;
- *(stk) = 0x01; /* status */
- *(--stk) = (unsigned long)texit; /* ra */
- *(--stk) = 0xdeadbeef; /* fp */
- *(--stk) = 0xdeadbeef; /* r23 */
- *(--stk) = 0xdeadbeef; /* r22 */
- *(--stk) = 0xdeadbeef; /* r21 */
- *(--stk) = 0xdeadbeef; /* r20 */
- *(--stk) = 0xdeadbeef; /* r19 */
- *(--stk) = 0xdeadbeef; /* r18 */
- *(--stk) = 0xdeadbeef; /* r17 */
- *(--stk) = 0xdeadbeef; /* r16 */
-// *(--stk) = 0xdeadbeef; /* r15 */
-// *(--stk) = 0xdeadbeef; /* r14 */
-// *(--stk) = 0xdeadbeef; /* r13 */
-// *(--stk) = 0xdeadbeef; /* r12 */
-// *(--stk) = 0xdeadbeef; /* r11 */
-// *(--stk) = 0xdeadbeef; /* r10 */
-// *(--stk) = 0xdeadbeef; /* r9 */
-// *(--stk) = 0xdeadbeef; /* r8 */
- *(--stk) = 0xdeadbeef; /* r7 */
- *(--stk) = 0xdeadbeef; /* r6 */
- *(--stk) = 0xdeadbeef; /* r5 */
- *(--stk) = (unsigned long)parameter; /* r4 argument */
- *(--stk) = 0xdeadbeef; /* r3 */
- *(--stk) = 0xdeadbeef; /* r2 */
- *(--stk) = (unsigned long)tentry; /* pc */
+ stk = (unsigned long *)stack_addr; + *(stk) = 0x01; /* status */ + *(--stk) = (unsigned long)texit; /* ra */ + *(--stk) = 0xdeadbeef; /* fp */ + *(--stk) = 0xdeadbeef; /* r23 */ + *(--stk) = 0xdeadbeef; /* r22 */ + *(--stk) = 0xdeadbeef; /* r21 */ + *(--stk) = 0xdeadbeef; /* r20 */ + *(--stk) = 0xdeadbeef; /* r19 */ + *(--stk) = 0xdeadbeef; /* r18 */ + *(--stk) = 0xdeadbeef; /* r17 */ + *(--stk) = 0xdeadbeef; /* r16 */ +// *(--stk) = 0xdeadbeef; /* r15 */ +// *(--stk) = 0xdeadbeef; /* r14 */ +// *(--stk) = 0xdeadbeef; /* r13 */ +// *(--stk) = 0xdeadbeef; /* r12 */ +// *(--stk) = 0xdeadbeef; /* r11 */ +// *(--stk) = 0xdeadbeef; /* r10 */ +// *(--stk) = 0xdeadbeef; /* r9 */ +// *(--stk) = 0xdeadbeef; /* r8 */ + *(--stk) = 0xdeadbeef; /* r7 */ + *(--stk) = 0xdeadbeef; /* r6 */ + *(--stk) = 0xdeadbeef; /* r5 */ + *(--stk) = (unsigned long)parameter; /* r4 argument */ + *(--stk) = 0xdeadbeef; /* r3 */ + *(--stk) = 0xdeadbeef; /* r2 */ + *(--stk) = (unsigned long)tentry; /* pc */ // *(stk) = (unsigned long)tentry; /* thread entry (ra) */ // *(--stk) = (unsigned long)parameter; /* thread argument, r4 */ diff --git a/libcpu/nios/nios_ii/vector.S b/libcpu/nios/nios_ii/vector.S index f8d43425b8..c3ed721bef 100644 --- a/libcpu/nios/nios_ii/vector.S +++ b/libcpu/nios/nios_ii/vector.S @@ -1,51 +1,51 @@ -.set noat
-
-.globl .Lexception_exit
-
-.section .exceptions.exit.label
-.Lexception_exit:
-.section .exceptions.exit, "xa"
- ldw r5, 68(sp)
-
- /* get exception back */
- ldw ea, 72(sp)
-
- /* if(rt_thread_switch_interrupt_flag == 0) goto no_need_context */
- ldw r4,%gprel(rt_thread_switch_interrupt_flag)(gp)
- beq r4,zero,no_need_context
-
-need_context:
- movia ea, rt_hw_context_switch_interrupt_do
- /* disable interrupt */
- mov r5, zero
-
-no_need_context:
- ldw ra, 0(sp)
-
- wrctl estatus, r5
-
- /*
- * Leave a gap in the stack frame at 4(sp) for the muldiv handler to
- * store zero into.
- */
-
- ldw r1, 8(sp)
- ldw r2, 12(sp)
- ldw r3, 16(sp)
- ldw r4, 20(sp)
- ldw r5, 24(sp)
- ldw r6, 28(sp)
- ldw r7, 32(sp)
- ldw r8, 36(sp)
- ldw r9, 40(sp)
- ldw r10, 44(sp)
- ldw r11, 48(sp)
- ldw r12, 52(sp)
- ldw r13, 56(sp)
- ldw r14, 60(sp)
- ldw r15, 64(sp)
-
- addi sp, sp, 76
-
- eret
-
+.set noat + +.globl .Lexception_exit + +.section .exceptions.exit.label +.Lexception_exit: +.section .exceptions.exit, "xa" + ldw r5, 68(sp) + + /* get exception back */ + ldw ea, 72(sp) + + /* if(rt_thread_switch_interrupt_flag == 0) goto no_need_context */ + ldw r4,%gprel(rt_thread_switch_interrupt_flag)(gp) + beq r4,zero,no_need_context + +need_context: + movia ea, rt_hw_context_switch_interrupt_do + /* disable interrupt */ + mov r5, zero + +no_need_context: + ldw ra, 0(sp) + + wrctl estatus, r5 + + /* + * Leave a gap in the stack frame at 4(sp) for the muldiv handler to + * store zero into. + */ + + ldw r1, 8(sp) + ldw r2, 12(sp) + ldw r3, 16(sp) + ldw r4, 20(sp) + ldw r5, 24(sp) + ldw r6, 28(sp) + ldw r7, 32(sp) + ldw r8, 36(sp) + ldw r9, 40(sp) + ldw r10, 44(sp) + ldw r11, 48(sp) + ldw r12, 52(sp) + ldw r13, 56(sp) + ldw r14, 60(sp) + ldw r15, 64(sp) + + addi sp, sp, 76 + + eret + diff --git a/libcpu/ppc/common/ptrace.h b/libcpu/ppc/common/ptrace.h index 860d1a7c60..d60e7fdcef 100644 --- a/libcpu/ppc/common/ptrace.h +++ b/libcpu/ppc/common/ptrace.h @@ -1,100 +1,100 @@ -#ifndef _PPC_PTRACE_H
-#define _PPC_PTRACE_H
-
-/*
- * This struct defines the way the registers are stored on the
- * kernel stack during a system call or other kernel entry.
- *
- * this should only contain volatile regs
- * since we can keep non-volatile in the thread_struct
- * should set this up when only volatiles are saved
- * by intr code.
- *
- * Since this is going on the stack, *CARE MUST BE TAKEN* to insure
- * that the overall structure is a multiple of 16 bytes in length.
- *
- * Note that the offsets of the fields in this struct correspond with
- * the PT_* values below. This simplifies arch/ppc/kernel/ptrace.c.
- */
-
-#ifndef __ASSEMBLY__
-#define PPC_REG unsigned long
-
-struct pt_regs {
- PPC_REG gpr[32];
- PPC_REG nip;
- PPC_REG msr;
- PPC_REG orig_gpr3; /* Used for restarting system calls */
- PPC_REG ctr;
- PPC_REG link;
- PPC_REG xer;
- PPC_REG ccr;
- PPC_REG mq; /* 601 only (not used at present) */
- /* Used on APUS to hold IPL value. */
- PPC_REG trap; /* Reason for being here */
- PPC_REG dar; /* Fault registers */
- PPC_REG dsisr;
- PPC_REG result; /* Result of a system call */
-}__attribute__((packed)) CELL_STACK_FRAME_t;
-#endif
-
-#define STACK_FRAME_OVERHEAD 16 /* size of minimum stack frame */
-
-/* Size of stack frame allocated when calling signal handler. */
-#define __SIGNAL_FRAMESIZE 64
-
-#define instruction_pointer(regs) ((regs)->nip)
-#define user_mode(regs) (((regs)->msr & MSR_PR) != 0)
-
-/*
- * Offsets used by 'ptrace' system call interface.
- * These can't be changed without breaking binary compatibility
- * with MkLinux, etc.
- */
-#define PT_R0 0
-#define PT_R1 1
-#define PT_R2 2
-#define PT_R3 3
-#define PT_R4 4
-#define PT_R5 5
-#define PT_R6 6
-#define PT_R7 7
-#define PT_R8 8
-#define PT_R9 9
-#define PT_R10 10
-#define PT_R11 11
-#define PT_R12 12
-#define PT_R13 13
-#define PT_R14 14
-#define PT_R15 15
-#define PT_R16 16
-#define PT_R17 17
-#define PT_R18 18
-#define PT_R19 19
-#define PT_R20 20
-#define PT_R21 21
-#define PT_R22 22
-#define PT_R23 23
-#define PT_R24 24
-#define PT_R25 25
-#define PT_R26 26
-#define PT_R27 27
-#define PT_R28 28
-#define PT_R29 29
-#define PT_R30 30
-#define PT_R31 31
-
-#define PT_NIP 32
-#define PT_MSR 33
-#define PT_ORIG_R3 34
-#define PT_CTR 35
-#define PT_LNK 36
-#define PT_XER 37
-#define PT_CCR 38
-#define PT_MQ 39
-
-#define PT_FPR0 48 /* each FP reg occupies 2 slots in this space */
-#define PT_FPR31 (PT_FPR0 + 2*31)
-#define PT_FPSCR (PT_FPR0 + 2*32 + 1)
-
-#endif
+#ifndef _PPC_PTRACE_H +#define _PPC_PTRACE_H + +/* + * This struct defines the way the registers are stored on the + * kernel stack during a system call or other kernel entry. + * + * this should only contain volatile regs + * since we can keep non-volatile in the thread_struct + * should set this up when only volatiles are saved + * by intr code. + * + * Since this is going on the stack, *CARE MUST BE TAKEN* to insure + * that the overall structure is a multiple of 16 bytes in length. + * + * Note that the offsets of the fields in this struct correspond with + * the PT_* values below. This simplifies arch/ppc/kernel/ptrace.c. + */ + +#ifndef __ASSEMBLY__ +#define PPC_REG unsigned long + +struct pt_regs { + PPC_REG gpr[32]; + PPC_REG nip; + PPC_REG msr; + PPC_REG orig_gpr3; /* Used for restarting system calls */ + PPC_REG ctr; + PPC_REG link; + PPC_REG xer; + PPC_REG ccr; + PPC_REG mq; /* 601 only (not used at present) */ + /* Used on APUS to hold IPL value. */ + PPC_REG trap; /* Reason for being here */ + PPC_REG dar; /* Fault registers */ + PPC_REG dsisr; + PPC_REG result; /* Result of a system call */ +}__attribute__((packed)) CELL_STACK_FRAME_t; +#endif + +#define STACK_FRAME_OVERHEAD 16 /* size of minimum stack frame */ + +/* Size of stack frame allocated when calling signal handler. */ +#define __SIGNAL_FRAMESIZE 64 + +#define instruction_pointer(regs) ((regs)->nip) +#define user_mode(regs) (((regs)->msr & MSR_PR) != 0) + +/* + * Offsets used by 'ptrace' system call interface. + * These can't be changed without breaking binary compatibility + * with MkLinux, etc. + */ +#define PT_R0 0 +#define PT_R1 1 +#define PT_R2 2 +#define PT_R3 3 +#define PT_R4 4 +#define PT_R5 5 +#define PT_R6 6 +#define PT_R7 7 +#define PT_R8 8 +#define PT_R9 9 +#define PT_R10 10 +#define PT_R11 11 +#define PT_R12 12 +#define PT_R13 13 +#define PT_R14 14 +#define PT_R15 15 +#define PT_R16 16 +#define PT_R17 17 +#define PT_R18 18 +#define PT_R19 19 +#define PT_R20 20 +#define PT_R21 21 +#define PT_R22 22 +#define PT_R23 23 +#define PT_R24 24 +#define PT_R25 25 +#define PT_R26 26 +#define PT_R27 27 +#define PT_R28 28 +#define PT_R29 29 +#define PT_R30 30 +#define PT_R31 31 + +#define PT_NIP 32 +#define PT_MSR 33 +#define PT_ORIG_R3 34 +#define PT_CTR 35 +#define PT_LNK 36 +#define PT_XER 37 +#define PT_CCR 38 +#define PT_MQ 39 + +#define PT_FPR0 48 /* each FP reg occupies 2 slots in this space */ +#define PT_FPR31 (PT_FPR0 + 2*31) +#define PT_FPSCR (PT_FPR0 + 2*32 + 1) + +#endif diff --git a/libcpu/ppc/common/stack.c b/libcpu/ppc/common/stack.c index 05ae5abb80..570e9ba046 100644 --- a/libcpu/ppc/common/stack.c +++ b/libcpu/ppc/common/stack.c @@ -1,88 +1,88 @@ -/*
- * File : stack.c
- * This file is part of RT-Thread RTOS
- * COPYRIGHT (C) 2006-2011, RT-Thread Development Team
- *
- * The license and distribution terms for this file may be
- * found in the file LICENSE in this distribution or at
- * http://www.rt-thread.org/license/LICENSE
- *
- * Change Logs:
- * Date Author Notes
- * 2011-02-14 Fred first implementation for
- */
-
-#include <rtthread.h>
-
-/**
- * @addtogroup PowerPC
- */
-/*@{*/
-
-/**
- * This function will initialize thread stack
- *
- * @param tentry the entry of thread
- * @param parameter the parameter of entry
- * @param stack_addr the beginning stack address
- * @param texit the function will be called when thread exit
- *
- * @return stack address
- */
-rt_uint8_t *rt_hw_stack_init(void *tentry, void *parameter,
- rt_uint8_t *stack_addr, void *texit)
-{
- unsigned long *stk;
- rt_uint32_t msr;
-
- __asm__ __volatile__("mfmsr %0\n" : "=r" (msr));
- msr |= 0x00028000;
-
- stk = (unsigned long *)stack_addr;
- --stk;
- *(--stk) = msr; /* srr0: machine status register */
- *(--stk) = (rt_uint32_t)tentry; /* srr1: entry point */
- *(--stk) = (rt_uint32_t)texit; /* lr: link register */
- *(--stk) = 0x0F0F0F0F; /* ctr: counter register */
- *(--stk) = 0x0F0F0F0F; /* xer: fixed-point exception register */
- *(--stk) = 0x0F0F0F0F; /* cr : condition register */
- *(--stk) = 0x00; /* usprg0 */
-
- *(--stk) = 0x31; /* r31 */
- *(--stk) = 0x30; /* r30 */
- *(--stk) = 0x29; /* r29 */
- *(--stk) = 0x28; /* r28 */
- *(--stk) = 0x27; /* r27 */
- *(--stk) = 0x26; /* r26 */
- *(--stk) = 0x25; /* r25 */
- *(--stk) = 0x24; /* r24 */
- *(--stk) = 0x23; /* r23 */
- *(--stk) = 0x22; /* r22 */
- *(--stk) = 0x21; /* r21 */
- *(--stk) = 0x20; /* r20 */
- *(--stk) = 0x19; /* r19 */
- *(--stk) = 0x18; /* r18 */
- *(--stk) = 0x17; /* r17 */
- *(--stk) = 0x16; /* r16 */
- *(--stk) = 0x15; /* r15 */
- *(--stk) = 0x14; /* r14 */
- *(--stk) = 0x13; /* r13: thread id */
- *(--stk) = 0x12; /* r12 */
- *(--stk) = 0x11; /* r11 */
- *(--stk) = 0x10; /* r10 */
- *(--stk) = 0x09; /* r09 */
- *(--stk) = 0x08; /* r08 */
- *(--stk) = 0x07; /* r07 */
- *(--stk) = 0x06; /* r06 */
- *(--stk) = 0x05; /* r05 */
- *(--stk) = 0x04; /* r04 */
- *(--stk) = (rt_uint32_t)parameter; /* r03: parameter and return */
- *(--stk) = 0x02; /* r02: toc */
- /* r01: sp */
- *(--stk) = 0x0; /* r00 */
-
- /* return task's current stack address */
- return (rt_uint8_t *)stk;
-}
-
-/*@}*/
+/* + * File : stack.c + * This file is part of RT-Thread RTOS + * COPYRIGHT (C) 2006-2011, RT-Thread Development Team + * + * The license and distribution terms for this file may be + * found in the file LICENSE in this distribution or at + * http://www.rt-thread.org/license/LICENSE + * + * Change Logs: + * Date Author Notes + * 2011-02-14 Fred first implementation for + */ + +#include <rtthread.h> + +/** + * @addtogroup PowerPC + */ +/*@{*/ + +/** + * This function will initialize thread stack + * + * @param tentry the entry of thread + * @param parameter the parameter of entry + * @param stack_addr the beginning stack address + * @param texit the function will be called when thread exit + * + * @return stack address + */ +rt_uint8_t *rt_hw_stack_init(void *tentry, void *parameter, + rt_uint8_t *stack_addr, void *texit) +{ + unsigned long *stk; + rt_uint32_t msr; + + __asm__ __volatile__("mfmsr %0\n" : "=r" (msr)); + msr |= 0x00028000; + + stk = (unsigned long *)stack_addr; + --stk; + *(--stk) = msr; /* srr0: machine status register */ + *(--stk) = (rt_uint32_t)tentry; /* srr1: entry point */ + *(--stk) = (rt_uint32_t)texit; /* lr: link register */ + *(--stk) = 0x0F0F0F0F; /* ctr: counter register */ + *(--stk) = 0x0F0F0F0F; /* xer: fixed-point exception register */ + *(--stk) = 0x0F0F0F0F; /* cr : condition register */ + *(--stk) = 0x00; /* usprg0 */ + + *(--stk) = 0x31; /* r31 */ + *(--stk) = 0x30; /* r30 */ + *(--stk) = 0x29; /* r29 */ + *(--stk) = 0x28; /* r28 */ + *(--stk) = 0x27; /* r27 */ + *(--stk) = 0x26; /* r26 */ + *(--stk) = 0x25; /* r25 */ + *(--stk) = 0x24; /* r24 */ + *(--stk) = 0x23; /* r23 */ + *(--stk) = 0x22; /* r22 */ + *(--stk) = 0x21; /* r21 */ + *(--stk) = 0x20; /* r20 */ + *(--stk) = 0x19; /* r19 */ + *(--stk) = 0x18; /* r18 */ + *(--stk) = 0x17; /* r17 */ + *(--stk) = 0x16; /* r16 */ + *(--stk) = 0x15; /* r15 */ + *(--stk) = 0x14; /* r14 */ + *(--stk) = 0x13; /* r13: thread id */ + *(--stk) = 0x12; /* r12 */ + *(--stk) = 0x11; /* r11 */ + *(--stk) = 0x10; /* r10 */ + *(--stk) = 0x09; /* r09 */ + *(--stk) = 0x08; /* r08 */ + *(--stk) = 0x07; /* r07 */ + *(--stk) = 0x06; /* r06 */ + *(--stk) = 0x05; /* r05 */ + *(--stk) = 0x04; /* r04 */ + *(--stk) = (rt_uint32_t)parameter; /* r03: parameter and return */ + *(--stk) = 0x02; /* r02: toc */ + /* r01: sp */ + *(--stk) = 0x0; /* r00 */ + + /* return task's current stack address */ + return (rt_uint8_t *)stk; +} + +/*@}*/ diff --git a/libcpu/ppc/ppc405/cache.h b/libcpu/ppc/ppc405/cache.h index 8157591373..930124547b 100644 --- a/libcpu/ppc/ppc405/cache.h +++ b/libcpu/ppc/ppc405/cache.h @@ -1,23 +1,23 @@ -#ifndef __CACHE_H__
-#define __CACHE_H__
-
-#include <asm/processor.h>
-
-#if !defined(__ASSEMBLY__)
-void flush_dcache_range(unsigned long start, unsigned long stop);
-void clean_dcache_range(unsigned long start, unsigned long stop);
-void invalidate_dcache_range(unsigned long start, unsigned long stop);
-void flush_dcache(void);
-void invalidate_dcache(void);
-void invalidate_icache(void);
-
-void icache_enable(void);
-void icache_disable(void);
-unsigned long icache_status(void);
-
-void dcache_enable(void);
-void dcache_disable(void);
-unsigned long dcache_status(void);
-#endif
-
-#endif
+#ifndef __CACHE_H__ +#define __CACHE_H__ + +#include <asm/processor.h> + +#if !defined(__ASSEMBLY__) +void flush_dcache_range(unsigned long start, unsigned long stop); +void clean_dcache_range(unsigned long start, unsigned long stop); +void invalidate_dcache_range(unsigned long start, unsigned long stop); +void flush_dcache(void); +void invalidate_dcache(void); +void invalidate_icache(void); + +void icache_enable(void); +void icache_disable(void); +unsigned long icache_status(void); + +void dcache_enable(void); +void dcache_disable(void); +unsigned long dcache_status(void); +#endif + +#endif diff --git a/libcpu/ppc/ppc405/context.h b/libcpu/ppc/ppc405/context.h index 54dadbc215..8b4d55d698 100644 --- a/libcpu/ppc/ppc405/context.h +++ b/libcpu/ppc/ppc405/context.h @@ -1,48 +1,48 @@ -#ifndef __CONTEXT_H__
-#define __CONTEXT_H__
-
-#define MSR_ME (1<<12) /* Machine Check Enable */
-#define MSR_EE (1<<15) /* External Interrupt Enable */
-#define MSR_CE (1<<17) /* Critical Interrupt Enable */
-
-#define GPR0 0
-#define GPR2 4
-#define GPR3 8
-#define GPR4 12
-#define GPR5 16
-#define GPR6 20
-#define GPR7 24
-#define GPR8 28
-#define GPR9 32
-#define GPR10 36
-#define GPR11 40
-#define GPR12 44
-#define GPR13 48
-#define GPR14 52
-#define GPR15 56
-#define GPR16 60
-#define GPR17 64
-#define GPR18 68
-#define GPR19 72
-#define GPR20 76
-#define GPR21 80
-#define GPR22 84
-#define GPR23 88
-#define GPR24 92
-#define GPR25 96
-#define GPR26 100
-#define GPR27 104
-#define GPR28 108
-#define GPR29 112
-#define GPR30 116
-#define GPR31 120
-#define USPRG0 (GPR31 + 4)
-#define CR (USPRG0 + 4)
-#define XER (CR + 4)
-#define CTR (XER + 4)
-#define LR (CTR + 4)
-#define SRR0 (LR + 4)
-#define SRR1 (SRR0 + 4)
-#define STACK_FRAME_SIZE (SRR1 + 4)
-
-#endif
+#ifndef __CONTEXT_H__ +#define __CONTEXT_H__ + +#define MSR_ME (1<<12) /* Machine Check Enable */ +#define MSR_EE (1<<15) /* External Interrupt Enable */ +#define MSR_CE (1<<17) /* Critical Interrupt Enable */ + +#define GPR0 0 +#define GPR2 4 +#define GPR3 8 +#define GPR4 12 +#define GPR5 16 +#define GPR6 20 +#define GPR7 24 +#define GPR8 28 +#define GPR9 32 +#define GPR10 36 +#define GPR11 40 +#define GPR12 44 +#define GPR13 48 +#define GPR14 52 +#define GPR15 56 +#define GPR16 60 +#define GPR17 64 +#define GPR18 68 +#define GPR19 72 +#define GPR20 76 +#define GPR21 80 +#define GPR22 84 +#define GPR23 88 +#define GPR24 92 +#define GPR25 96 +#define GPR26 100 +#define GPR27 104 +#define GPR28 108 +#define GPR29 112 +#define GPR30 116 +#define GPR31 120 +#define USPRG0 (GPR31 + 4) +#define CR (USPRG0 + 4) +#define XER (CR + 4) +#define CTR (XER + 4) +#define LR (CTR + 4) +#define SRR0 (LR + 4) +#define SRR1 (SRR0 + 4) +#define STACK_FRAME_SIZE (SRR1 + 4) + +#endif diff --git a/libcpu/ppc/ppc405/context_gcc.S b/libcpu/ppc/ppc405/context_gcc.S index e43f96d801..f6a53dce3d 100644 --- a/libcpu/ppc/ppc405/context_gcc.S +++ b/libcpu/ppc/ppc405/context_gcc.S @@ -1,210 +1,210 @@ -#include "context.h"
-#define SPRG0 0x110 /* Special Purpose Register General 0 */
-#define SPRG1 0x111 /* Special Purpose Register General 1 */
-
- .globl rt_hw_interrupt_disable
- .globl rt_hw_interrupt_enable
- .globl rt_hw_context_switch
- .globl rt_hw_context_switch_to
- .globl rt_hw_context_switch_interrupt
- .globl rt_hw_systemcall_entry
-
-/*
- * rt_base_t rt_hw_interrupt_disable();
- * return the interrupt status and disable interrupt
- */
-#if 0
-rt_hw_interrupt_disable:
- mfmsr r3 /* Disable interrupts */
- li r4,0
- ori r4,r4,MSR_EE
- andc r4,r4,r3
- SYNC /* Some chip revs need this... */
- mtmsr r4
- SYNC
- blr
-#else
-rt_hw_interrupt_disable:
- addis r4, r0, 0xFFFD
- ori r4, r4, 0x7FFF
- mfmsr r3
- and r4, r4, 3 /* Clear bits 14 and 16, corresponding to... */
- mtmsr r4 /* ...critical and non-critical interrupts */
- blr
-#endif
-
-/*
- * void rt_hw_interrupt_enable(rt_base_t level);
- * restore interrupt
- */
-rt_hw_interrupt_enable:
- mtmsr r3
- SYNC
- blr
-
-/*
- * void rt_hw_context_switch(rt_uint32 from, rt_uint32 to);
- * r3 --> from
- * r4 --> to
- *
- * r1: stack pointer
- */
-rt_hw_systemcall_entry:
- mtspr SPRG0,r3 /* save r3 to SPRG0 */
- mtspr SPRG1,r4 /* save r4 to SPRG1 */
-
- lis r3,rt_thread_switch_interrput_flag@h
- ori r3,r3,rt_thread_switch_interrput_flag@l
- lwz r4,0(r3)
- cmpi cr0,0,r4,0x0 /* whether is 0 */
- beq _no_switch /* no switch, exit */
- li r4,0x0 /* set rt_thread_switch_interrput_flag to 0 */
- stw r4,0(r3)
-
- /* load from thread to r3 */
- lis r3,rt_interrupt_from_thread@h /* set rt_interrupt_from_thread */
- ori r3,r3,rt_interrupt_from_thread@l
- lwz r3,0(r3)
-
- cmpi cr0,0,r3,0x0 /* whether is 0 */
- beq _restore /* it's first switch, goto _restore */
-
- /* save r1:sp to thread[from] stack pointer */
- subi r1, r1, STACK_FRAME_SIZE
- stw r1, 0(r3)
-
- /* restore r3, r4 from SPRG */
- mfspr r3,SPRG0
- mfspr r4,SPRG0
-
- /* save registers */
- stw r0,GPR0(r1) /* save general purpose registers 0 */
- stmw r2,GPR2(r1) /* save general purpose registers 2-31 */
-
- mfusprg0 r0 /* save usprg0 */
- stw r0,USPRG0(r1)
- mfcr r0, /* save cr */
- stw r0,CR(r1)
- mfxer r0 /* save xer */
- stw r0,XER(r1)
- mfctr r0 /* save ctr */
- stw r0,CTR(r1)
- mflr r0 /* save lr */
- stw r0, LR(r1)
-
- mfsrr0 r0 /* save SRR0 and SRR1 */
- stw r0,SRR0(r1)
- mfsrr1 r0
- stw r0,SRR1(r1)
-
-_restore:
- /* get thread[to] stack pointer */
- lis r4,rt_interrupt_to_thread@h
- ori r4,r4,rt_interrupt_to_thread@l
- lwz r1,0(r4)
- lwz r1,0(r1)
-
- lwz r0,SRR1(r1) /* restore SRR1 and SRR0 */
- mtsrr1 r0
- lwz r0,SRR0(r1)
- mtsrr0 r0
-
- lwz r0,LR(r1) /* restore lr */
- mtlr r0
- lwz r0,CTR(r1) /* restore ctr */
- mtctr r0
- lwz r0,XER(r1) /* restore xer */
- mtxer r0
- lwz r0,CR(r1) /* restore cr */
- mtcr r0
- lwz r0,USPRG0(r1) /* restore usprg0 */
- // mtusprg0 r0
-
- lmw r2, GPR2(r1) /* restore general register */
- lwz r0,GPR0(r1)
- addi r1, r1, STACK_FRAME_SIZE
- /* RFI will restore status register and thus the correct priority*/
- rfi
-
-_no_switch:
- /* restore r3, r4 from SPRG */
- mfspr r3,SPRG0
- mfspr r4,SPRG0
- rfi
-
- /* void rt_hw_context_switch_to(to); */
- .globl rt_hw_context_switch_to
-rt_hw_context_switch_to:
- /* set rt_thread_switch_interrput_flag = 1 */
- lis r5,rt_thread_switch_interrput_flag@h
- ori r5,r5,rt_thread_switch_interrput_flag@l
- li r6, 0x01
- stw r6,0(r5)
-
- /* set rt_interrupt_from_thread = 0 */
- lis r5,rt_interrupt_from_thread@h
- ori r5,r5,rt_interrupt_from_thread@l
- li r6, 0x00
- stw r6,0(r5)
-
- /* set rt_interrupt_from_thread = to */
- lis r5,rt_interrupt_to_thread@h
- ori r5,r5,rt_interrupt_to_thread@l
- stw r3,0(r5)
-
- /* trigger a system call */
- sc
-
- blr
-
- /* void rt_hw_context_switch(from, to); */
- .globl rt_hw_context_switch
-rt_hw_context_switch:
- /* compare rt_thread_switch_interrupt_flag and set it */
- lis r5,rt_thread_switch_interrput_flag@h
- ori r5,r5,rt_thread_switch_interrput_flag@l
- lwz r6,0(r5)
- cmpi cr0,0,r6,0x1 /* whether is 1 */
- beq _reswitch /* set already, goto _reswitch */
- li r6,0x1 /* set rt_thread_switch_interrput_flag to 1*/
- stw r6,0(r5)
-
- /* set rt_interrupt_from_thread to 'from' */
- lis r5,rt_interrupt_from_thread@h
- ori r5,r5,rt_interrupt_from_thread@l
- stw r3,0(r5)
-
-_reswitch:
- /* set rt_interrupt_to_thread to 'to' */
- lis r6,rt_interrupt_to_thread@h
- ori r6,r6,rt_interrupt_to_thread@l
- stw r4,0(r6)
-
- /* trigger a system call */
- sc
-
- blr
-
- .globl rt_hw_context_switch_interrupt
-rt_hw_context_switch_interrupt:
- /* compare rt_thread_switch_interrupt_flag and set it */
- lis r5,rt_thread_switch_interrput_flag@h
- ori r5,r5,rt_thread_switch_interrput_flag@l
- lwz r6,0(r5)
- cmpi cr0,0,r6,0x1 /* whether is 1 */
- beq _int_reswitch /* set already, goto _reswitch */
- li r6,0x1 /* set rt_thread_switch_interrput_flag to 1*/
- stw r6,0(r5)
-
- /* set rt_interrupt_from_thread to 'from' */
- lis r5,rt_interrupt_from_thread@h
- ori r5,r5,rt_interrupt_from_thread@l
- stw r3,0(r5)
-
-_int_reswitch:
- /* set rt_interrupt_to_thread to 'to' */
- lis r6,rt_interrupt_to_thread@h
- ori r6,r6,rt_interrupt_to_thread@l
- stw r4,0(r6)
-
- blr
+#include "context.h" +#define SPRG0 0x110 /* Special Purpose Register General 0 */ +#define SPRG1 0x111 /* Special Purpose Register General 1 */ + + .globl rt_hw_interrupt_disable + .globl rt_hw_interrupt_enable + .globl rt_hw_context_switch + .globl rt_hw_context_switch_to + .globl rt_hw_context_switch_interrupt + .globl rt_hw_systemcall_entry + +/* + * rt_base_t rt_hw_interrupt_disable(); + * return the interrupt status and disable interrupt + */ +#if 0 +rt_hw_interrupt_disable: + mfmsr r3 /* Disable interrupts */ + li r4,0 + ori r4,r4,MSR_EE + andc r4,r4,r3 + SYNC /* Some chip revs need this... */ + mtmsr r4 + SYNC + blr +#else +rt_hw_interrupt_disable: + addis r4, r0, 0xFFFD + ori r4, r4, 0x7FFF + mfmsr r3 + and r4, r4, 3 /* Clear bits 14 and 16, corresponding to... */ + mtmsr r4 /* ...critical and non-critical interrupts */ + blr +#endif + +/* + * void rt_hw_interrupt_enable(rt_base_t level); + * restore interrupt + */ +rt_hw_interrupt_enable: + mtmsr r3 + SYNC + blr + +/* + * void rt_hw_context_switch(rt_uint32 from, rt_uint32 to); + * r3 --> from + * r4 --> to + * + * r1: stack pointer + */ +rt_hw_systemcall_entry: + mtspr SPRG0,r3 /* save r3 to SPRG0 */ + mtspr SPRG1,r4 /* save r4 to SPRG1 */ + + lis r3,rt_thread_switch_interrput_flag@h + ori r3,r3,rt_thread_switch_interrput_flag@l + lwz r4,0(r3) + cmpi cr0,0,r4,0x0 /* whether is 0 */ + beq _no_switch /* no switch, exit */ + li r4,0x0 /* set rt_thread_switch_interrput_flag to 0 */ + stw r4,0(r3) + + /* load from thread to r3 */ + lis r3,rt_interrupt_from_thread@h /* set rt_interrupt_from_thread */ + ori r3,r3,rt_interrupt_from_thread@l + lwz r3,0(r3) + + cmpi cr0,0,r3,0x0 /* whether is 0 */ + beq _restore /* it's first switch, goto _restore */ + + /* save r1:sp to thread[from] stack pointer */ + subi r1, r1, STACK_FRAME_SIZE + stw r1, 0(r3) + + /* restore r3, r4 from SPRG */ + mfspr r3,SPRG0 + mfspr r4,SPRG0 + + /* save registers */ + stw r0,GPR0(r1) /* save general purpose registers 0 */ + stmw r2,GPR2(r1) /* save general purpose registers 2-31 */ + + mfusprg0 r0 /* save usprg0 */ + stw r0,USPRG0(r1) + mfcr r0, /* save cr */ + stw r0,CR(r1) + mfxer r0 /* save xer */ + stw r0,XER(r1) + mfctr r0 /* save ctr */ + stw r0,CTR(r1) + mflr r0 /* save lr */ + stw r0, LR(r1) + + mfsrr0 r0 /* save SRR0 and SRR1 */ + stw r0,SRR0(r1) + mfsrr1 r0 + stw r0,SRR1(r1) + +_restore: + /* get thread[to] stack pointer */ + lis r4,rt_interrupt_to_thread@h + ori r4,r4,rt_interrupt_to_thread@l + lwz r1,0(r4) + lwz r1,0(r1) + + lwz r0,SRR1(r1) /* restore SRR1 and SRR0 */ + mtsrr1 r0 + lwz r0,SRR0(r1) + mtsrr0 r0 + + lwz r0,LR(r1) /* restore lr */ + mtlr r0 + lwz r0,CTR(r1) /* restore ctr */ + mtctr r0 + lwz r0,XER(r1) /* restore xer */ + mtxer r0 + lwz r0,CR(r1) /* restore cr */ + mtcr r0 + lwz r0,USPRG0(r1) /* restore usprg0 */ + // mtusprg0 r0 + + lmw r2, GPR2(r1) /* restore general register */ + lwz r0,GPR0(r1) + addi r1, r1, STACK_FRAME_SIZE + /* RFI will restore status register and thus the correct priority*/ + rfi + +_no_switch: + /* restore r3, r4 from SPRG */ + mfspr r3,SPRG0 + mfspr r4,SPRG0 + rfi + + /* void rt_hw_context_switch_to(to); */ + .globl rt_hw_context_switch_to +rt_hw_context_switch_to: + /* set rt_thread_switch_interrput_flag = 1 */ + lis r5,rt_thread_switch_interrput_flag@h + ori r5,r5,rt_thread_switch_interrput_flag@l + li r6, 0x01 + stw r6,0(r5) + + /* set rt_interrupt_from_thread = 0 */ + lis r5,rt_interrupt_from_thread@h + ori r5,r5,rt_interrupt_from_thread@l + li r6, 0x00 + stw r6,0(r5) + + /* set rt_interrupt_from_thread = to */ + lis r5,rt_interrupt_to_thread@h + ori r5,r5,rt_interrupt_to_thread@l + stw r3,0(r5) + + /* trigger a system call */ + sc + + blr + + /* void rt_hw_context_switch(from, to); */ + .globl rt_hw_context_switch +rt_hw_context_switch: + /* compare rt_thread_switch_interrupt_flag and set it */ + lis r5,rt_thread_switch_interrput_flag@h + ori r5,r5,rt_thread_switch_interrput_flag@l + lwz r6,0(r5) + cmpi cr0,0,r6,0x1 /* whether is 1 */ + beq _reswitch /* set already, goto _reswitch */ + li r6,0x1 /* set rt_thread_switch_interrput_flag to 1*/ + stw r6,0(r5) + + /* set rt_interrupt_from_thread to 'from' */ + lis r5,rt_interrupt_from_thread@h + ori r5,r5,rt_interrupt_from_thread@l + stw r3,0(r5) + +_reswitch: + /* set rt_interrupt_to_thread to 'to' */ + lis r6,rt_interrupt_to_thread@h + ori r6,r6,rt_interrupt_to_thread@l + stw r4,0(r6) + + /* trigger a system call */ + sc + + blr + + .globl rt_hw_context_switch_interrupt +rt_hw_context_switch_interrupt: + /* compare rt_thread_switch_interrupt_flag and set it */ + lis r5,rt_thread_switch_interrput_flag@h + ori r5,r5,rt_thread_switch_interrput_flag@l + lwz r6,0(r5) + cmpi cr0,0,r6,0x1 /* whether is 1 */ + beq _int_reswitch /* set already, goto _reswitch */ + li r6,0x1 /* set rt_thread_switch_interrput_flag to 1*/ + stw r6,0(r5) + + /* set rt_interrupt_from_thread to 'from' */ + lis r5,rt_interrupt_from_thread@h + ori r5,r5,rt_interrupt_from_thread@l + stw r3,0(r5) + +_int_reswitch: + /* set rt_interrupt_to_thread to 'to' */ + lis r6,rt_interrupt_to_thread@h + ori r6,r6,rt_interrupt_to_thread@l + stw r4,0(r6) + + blr diff --git a/libcpu/ppc/ppc405/include/asm/ppc405.h b/libcpu/ppc/ppc405/include/asm/ppc405.h index c15f2e3cf2..c2562047cb 100644 --- a/libcpu/ppc/ppc405/include/asm/ppc405.h +++ b/libcpu/ppc/ppc405/include/asm/ppc405.h @@ -1,980 +1,980 @@ -/*----------------------------------------------------------------------------+
-|
-| This source code has been made available to you by IBM on an AS-IS
-| basis. Anyone receiving this source is licensed under IBM
-| copyrights to use it in any way he or she deems fit, including
-| copying it, modifying it, compiling it, and redistributing it either
-| with or without modifications. No license under IBM patents or
-| patent applications is to be implied by the copyright license.
-|
-| Any user of this software should understand that IBM cannot provide
-| technical support for this software and will not be responsible for
-| any consequences resulting from the use of this software.
-|
-| Any person who transfers this source code or any derivative work
-| must include the IBM copyright notice, this paragraph, and the
-| preceding two paragraphs in the transferred software.
-|
-| COPYRIGHT I B M CORPORATION 1999
-| LICENSED MATERIAL - PROGRAM PROPERTY OF I B M
-+----------------------------------------------------------------------------*/
-
-#ifndef __PPC405_H__
-#define __PPC405_H__
-
-/* Define bits and masks for real-mode storage attribute control registers */
-#define PPC_128MB_SACR_BIT(addr) ((addr) >> 27)
-#define PPC_128MB_SACR_VALUE(addr) PPC_REG_VAL(PPC_128MB_SACR_BIT(addr),1)
-
-/******************************************************************************
- * Special for PPC405GP
- ******************************************************************************/
-
-/******************************************************************************
- * DMA
- ******************************************************************************/
-#define DMA_DCR_BASE 0x100
-#define dmacr0 (DMA_DCR_BASE+0x00) /* DMA channel control register 0 */
-#define dmact0 (DMA_DCR_BASE+0x01) /* DMA count register 0 */
-#define dmada0 (DMA_DCR_BASE+0x02) /* DMA destination address register 0 */
-#define dmasa0 (DMA_DCR_BASE+0x03) /* DMA source address register 0 */
-#define dmasb0 (DMA_DCR_BASE+0x04) /* DMA scatter/gather descriptor addr 0 */
-#define dmacr1 (DMA_DCR_BASE+0x08) /* DMA channel control register 1 */
-#define dmact1 (DMA_DCR_BASE+0x09) /* DMA count register 1 */
-#define dmada1 (DMA_DCR_BASE+0x0a) /* DMA destination address register 1 */
-#define dmasa1 (DMA_DCR_BASE+0x0b) /* DMA source address register 1 */
-#define dmasb1 (DMA_DCR_BASE+0x0c) /* DMA scatter/gather descriptor addr 1 */
-#define dmacr2 (DMA_DCR_BASE+0x10) /* DMA channel control register 2 */
-#define dmact2 (DMA_DCR_BASE+0x11) /* DMA count register 2 */
-#define dmada2 (DMA_DCR_BASE+0x12) /* DMA destination address register 2 */
-#define dmasa2 (DMA_DCR_BASE+0x13) /* DMA source address register 2 */
-#define dmasb2 (DMA_DCR_BASE+0x14) /* DMA scatter/gather descriptor addr 2 */
-#define dmacr3 (DMA_DCR_BASE+0x18) /* DMA channel control register 3 */
-#define dmact3 (DMA_DCR_BASE+0x19) /* DMA count register 3 */
-#define dmada3 (DMA_DCR_BASE+0x1a) /* DMA destination address register 3 */
-#define dmasa3 (DMA_DCR_BASE+0x1b) /* DMA source address register 3 */
-#define dmasb3 (DMA_DCR_BASE+0x1c) /* DMA scatter/gather descriptor addr 3 */
-#define dmasr (DMA_DCR_BASE+0x20) /* DMA status register */
-#define dmasgc (DMA_DCR_BASE+0x23) /* DMA scatter/gather command register */
-#define dmaadr (DMA_DCR_BASE+0x24) /* DMA address decode register */
-
-#ifndef CONFIG_405EP
-/******************************************************************************
- * Decompression Controller
- ******************************************************************************/
-#define DECOMP_DCR_BASE 0x14
-#define kiar (DECOMP_DCR_BASE+0x0) /* Decompression controller addr reg */
-#define kidr (DECOMP_DCR_BASE+0x1) /* Decompression controller data reg */
- /* values for kiar register - indirect addressing of these regs */
- #define kitor0 0x00 /* index table origin register 0 */
- #define kitor1 0x01 /* index table origin register 1 */
- #define kitor2 0x02 /* index table origin register 2 */
- #define kitor3 0x03 /* index table origin register 3 */
- #define kaddr0 0x04 /* address decode definition regsiter 0 */
- #define kaddr1 0x05 /* address decode definition regsiter 1 */
- #define kconf 0x40 /* decompression core config register */
- #define kid 0x41 /* decompression core ID register */
- #define kver 0x42 /* decompression core version # reg */
- #define kpear 0x50 /* bus error addr reg (PLB addr) */
- #define kbear 0x51 /* bus error addr reg (DCP to EBIU addr)*/
- #define kesr0 0x52 /* bus error status reg 0 (R/clear) */
- #define kesr0s 0x53 /* bus error status reg 0 (set) */
- /* There are 0x400 of the following registers, from krom0 to krom3ff*/
- /* Only the first one is given here. */
- #define krom0 0x400 /* SRAM/ROM read/write */
-#endif
-
-/******************************************************************************
- * Power Management
- ******************************************************************************/
-#ifdef CONFIG_405EX
-#define POWERMAN_DCR_BASE 0xb0
-#else
-#define POWERMAN_DCR_BASE 0xb8
-#endif
-#define cpmsr (POWERMAN_DCR_BASE+0x0) /* Power management status */
-#define cpmer (POWERMAN_DCR_BASE+0x1) /* Power management enable */
-#define cpmfr (POWERMAN_DCR_BASE+0x2) /* Power management force */
-
-/******************************************************************************
- * Extrnal Bus Controller
- ******************************************************************************/
- /* values for ebccfga register - indirect addressing of these regs */
- #define pb0cr 0x00 /* periph bank 0 config reg */
- #define pb1cr 0x01 /* periph bank 1 config reg */
- #define pb2cr 0x02 /* periph bank 2 config reg */
- #define pb3cr 0x03 /* periph bank 3 config reg */
- #define pb4cr 0x04 /* periph bank 4 config reg */
-#ifndef CONFIG_405EP
- #define pb5cr 0x05 /* periph bank 5 config reg */
- #define pb6cr 0x06 /* periph bank 6 config reg */
- #define pb7cr 0x07 /* periph bank 7 config reg */
-#endif
- #define pb0ap 0x10 /* periph bank 0 access parameters */
- #define pb1ap 0x11 /* periph bank 1 access parameters */
- #define pb2ap 0x12 /* periph bank 2 access parameters */
- #define pb3ap 0x13 /* periph bank 3 access parameters */
- #define pb4ap 0x14 /* periph bank 4 access parameters */
-#ifndef CONFIG_405EP
- #define pb5ap 0x15 /* periph bank 5 access parameters */
- #define pb6ap 0x16 /* periph bank 6 access parameters */
- #define pb7ap 0x17 /* periph bank 7 access parameters */
-#endif
- #define pbear 0x20 /* periph bus error addr reg */
- #define pbesr0 0x21 /* periph bus error status reg 0 */
- #define pbesr1 0x22 /* periph bus error status reg 1 */
- #define epcr 0x23 /* external periph control reg */
-#define EBC0_CFG 0x23 /* external bus configuration reg */
-
-#ifdef CONFIG_405EP
-/******************************************************************************
- * Control
- ******************************************************************************/
-#define CNTRL_DCR_BASE 0x0f0
-#define cpc0_pllmr0 (CNTRL_DCR_BASE+0x0) /* PLL mode register 0 */
-#define cpc0_boot (CNTRL_DCR_BASE+0x1) /* Clock status register */
-#define cpc0_epctl (CNTRL_DCR_BASE+0x3) /* EMAC to PHY control register */
-#define cpc0_pllmr1 (CNTRL_DCR_BASE+0x4) /* PLL mode register 1 */
-#define cpc0_ucr (CNTRL_DCR_BASE+0x5) /* UART control register */
-#define cpc0_pci (CNTRL_DCR_BASE+0x9) /* PCI control register */
-
-#define CPC0_PLLMR0 (CNTRL_DCR_BASE+0x0) /* PLL mode 0 register */
-#define CPC0_BOOT (CNTRL_DCR_BASE+0x1) /* Chip Clock Status register */
-#define CPC0_CR1 (CNTRL_DCR_BASE+0x2) /* Chip Control 1 register */
-#define CPC0_EPRCSR (CNTRL_DCR_BASE+0x3) /* EMAC PHY Rcv Clk Src register*/
-#define CPC0_PLLMR1 (CNTRL_DCR_BASE+0x4) /* PLL mode 1 register */
-#define CPC0_UCR (CNTRL_DCR_BASE+0x5) /* UART Control register */
-#define CPC0_SRR (CNTRL_DCR_BASE+0x6) /* Soft Reset register */
-#define CPC0_JTAGID (CNTRL_DCR_BASE+0x7) /* JTAG ID register */
-#define CPC0_SPARE (CNTRL_DCR_BASE+0x8) /* Spare DCR */
-#define CPC0_PCI (CNTRL_DCR_BASE+0x9) /* PCI Control register */
-
-/* Bit definitions */
-#define PLLMR0_CPU_DIV_MASK 0x00300000 /* CPU clock divider */
-#define PLLMR0_CPU_DIV_BYPASS 0x00000000
-#define PLLMR0_CPU_DIV_2 0x00100000
-#define PLLMR0_CPU_DIV_3 0x00200000
-#define PLLMR0_CPU_DIV_4 0x00300000
-
-#define PLLMR0_CPU_TO_PLB_MASK 0x00030000 /* CPU:PLB Frequency Divisor */
-#define PLLMR0_CPU_PLB_DIV_1 0x00000000
-#define PLLMR0_CPU_PLB_DIV_2 0x00010000
-#define PLLMR0_CPU_PLB_DIV_3 0x00020000
-#define PLLMR0_CPU_PLB_DIV_4 0x00030000
-
-#define PLLMR0_OPB_TO_PLB_MASK 0x00003000 /* OPB:PLB Frequency Divisor */
-#define PLLMR0_OPB_PLB_DIV_1 0x00000000
-#define PLLMR0_OPB_PLB_DIV_2 0x00001000
-#define PLLMR0_OPB_PLB_DIV_3 0x00002000
-#define PLLMR0_OPB_PLB_DIV_4 0x00003000
-
-#define PLLMR0_EXB_TO_PLB_MASK 0x00000300 /* External Bus:PLB Divisor */
-#define PLLMR0_EXB_PLB_DIV_2 0x00000000
-#define PLLMR0_EXB_PLB_DIV_3 0x00000100
-#define PLLMR0_EXB_PLB_DIV_4 0x00000200
-#define PLLMR0_EXB_PLB_DIV_5 0x00000300
-
-#define PLLMR0_MAL_TO_PLB_MASK 0x00000030 /* MAL:PLB Divisor */
-#define PLLMR0_MAL_PLB_DIV_1 0x00000000
-#define PLLMR0_MAL_PLB_DIV_2 0x00000010
-#define PLLMR0_MAL_PLB_DIV_3 0x00000020
-#define PLLMR0_MAL_PLB_DIV_4 0x00000030
-
-#define PLLMR0_PCI_TO_PLB_MASK 0x00000003 /* PCI:PLB Frequency Divisor */
-#define PLLMR0_PCI_PLB_DIV_1 0x00000000
-#define PLLMR0_PCI_PLB_DIV_2 0x00000001
-#define PLLMR0_PCI_PLB_DIV_3 0x00000002
-#define PLLMR0_PCI_PLB_DIV_4 0x00000003
-
-#define PLLMR1_SSCS_MASK 0x80000000 /* Select system clock source */
-#define PLLMR1_PLLR_MASK 0x40000000 /* PLL reset */
-#define PLLMR1_FBMUL_MASK 0x00F00000 /* PLL feedback multiplier value */
-#define PLLMR1_FBMUL_DIV_16 0x00000000
-#define PLLMR1_FBMUL_DIV_1 0x00100000
-#define PLLMR1_FBMUL_DIV_2 0x00200000
-#define PLLMR1_FBMUL_DIV_3 0x00300000
-#define PLLMR1_FBMUL_DIV_4 0x00400000
-#define PLLMR1_FBMUL_DIV_5 0x00500000
-#define PLLMR1_FBMUL_DIV_6 0x00600000
-#define PLLMR1_FBMUL_DIV_7 0x00700000
-#define PLLMR1_FBMUL_DIV_8 0x00800000
-#define PLLMR1_FBMUL_DIV_9 0x00900000
-#define PLLMR1_FBMUL_DIV_10 0x00A00000
-#define PLLMR1_FBMUL_DIV_11 0x00B00000
-#define PLLMR1_FBMUL_DIV_12 0x00C00000
-#define PLLMR1_FBMUL_DIV_13 0x00D00000
-#define PLLMR1_FBMUL_DIV_14 0x00E00000
-#define PLLMR1_FBMUL_DIV_15 0x00F00000
-
-#define PLLMR1_FWDVA_MASK 0x00070000 /* PLL forward divider A value */
-#define PLLMR1_FWDVA_DIV_8 0x00000000
-#define PLLMR1_FWDVA_DIV_7 0x00010000
-#define PLLMR1_FWDVA_DIV_6 0x00020000
-#define PLLMR1_FWDVA_DIV_5 0x00030000
-#define PLLMR1_FWDVA_DIV_4 0x00040000
-#define PLLMR1_FWDVA_DIV_3 0x00050000
-#define PLLMR1_FWDVA_DIV_2 0x00060000
-#define PLLMR1_FWDVA_DIV_1 0x00070000
-#define PLLMR1_FWDVB_MASK 0x00007000 /* PLL forward divider B value */
-#define PLLMR1_TUNING_MASK 0x000003FF /* PLL tune bits */
-
-/* Defines for CPC0_EPRCSR register */
-#define CPC0_EPRCSR_E0NFE 0x80000000
-#define CPC0_EPRCSR_E1NFE 0x40000000
-#define CPC0_EPRCSR_E1RPP 0x00000080
-#define CPC0_EPRCSR_E0RPP 0x00000040
-#define CPC0_EPRCSR_E1ERP 0x00000020
-#define CPC0_EPRCSR_E0ERP 0x00000010
-#define CPC0_EPRCSR_E1PCI 0x00000002
-#define CPC0_EPRCSR_E0PCI 0x00000001
-
-/* Defines for CPC0_PCI Register */
-#define CPC0_PCI_SPE 0x00000010 /* PCIINT/WE select */
-#define CPC0_PCI_HOST_CFG_EN 0x00000008 /* PCI host config Enable */
-#define CPC0_PCI_ARBIT_EN 0x00000001 /* PCI Internal Arb Enabled*/
-
-/* Defines for CPC0_BOOR Register */
-#define CPC0_BOOT_SEP 0x00000002 /* serial EEPROM present */
-
-/* Defines for CPC0_PLLMR1 Register fields */
-#define PLL_ACTIVE 0x80000000
-#define CPC0_PLLMR1_SSCS 0x80000000
-#define PLL_RESET 0x40000000
-#define CPC0_PLLMR1_PLLR 0x40000000
- /* Feedback multiplier */
-#define PLL_FBKDIV 0x00F00000
-#define CPC0_PLLMR1_FBDV 0x00F00000
-#define PLL_FBKDIV_16 0x00000000
-#define PLL_FBKDIV_1 0x00100000
-#define PLL_FBKDIV_2 0x00200000
-#define PLL_FBKDIV_3 0x00300000
-#define PLL_FBKDIV_4 0x00400000
-#define PLL_FBKDIV_5 0x00500000
-#define PLL_FBKDIV_6 0x00600000
-#define PLL_FBKDIV_7 0x00700000
-#define PLL_FBKDIV_8 0x00800000
-#define PLL_FBKDIV_9 0x00900000
-#define PLL_FBKDIV_10 0x00A00000
-#define PLL_FBKDIV_11 0x00B00000
-#define PLL_FBKDIV_12 0x00C00000
-#define PLL_FBKDIV_13 0x00D00000
-#define PLL_FBKDIV_14 0x00E00000
-#define PLL_FBKDIV_15 0x00F00000
- /* Forward A divisor */
-#define PLL_FWDDIVA 0x00070000
-#define CPC0_PLLMR1_FWDVA 0x00070000
-#define PLL_FWDDIVA_8 0x00000000
-#define PLL_FWDDIVA_7 0x00010000
-#define PLL_FWDDIVA_6 0x00020000
-#define PLL_FWDDIVA_5 0x00030000
-#define PLL_FWDDIVA_4 0x00040000
-#define PLL_FWDDIVA_3 0x00050000
-#define PLL_FWDDIVA_2 0x00060000
-#define PLL_FWDDIVA_1 0x00070000
- /* Forward B divisor */
-#define PLL_FWDDIVB 0x00007000
-#define CPC0_PLLMR1_FWDVB 0x00007000
-#define PLL_FWDDIVB_8 0x00000000
-#define PLL_FWDDIVB_7 0x00001000
-#define PLL_FWDDIVB_6 0x00002000
-#define PLL_FWDDIVB_5 0x00003000
-#define PLL_FWDDIVB_4 0x00004000
-#define PLL_FWDDIVB_3 0x00005000
-#define PLL_FWDDIVB_2 0x00006000
-#define PLL_FWDDIVB_1 0x00007000
- /* PLL tune bits */
-#define PLL_TUNE_MASK 0x000003FF
-#define PLL_TUNE_2_M_3 0x00000133 /* 2 <= M <= 3 */
-#define PLL_TUNE_4_M_6 0x00000134 /* 3 < M <= 6 */
-#define PLL_TUNE_7_M_10 0x00000138 /* 6 < M <= 10 */
-#define PLL_TUNE_11_M_14 0x0000013C /* 10 < M <= 14 */
-#define PLL_TUNE_15_M_40 0x0000023E /* 14 < M <= 40 */
-#define PLL_TUNE_VCO_LOW 0x00000000 /* 500MHz <= VCO <= 800MHz */
-#define PLL_TUNE_VCO_HI 0x00000080 /* 800MHz < VCO <= 1000MHz */
-
-/* Defines for CPC0_PLLMR0 Register fields */
- /* CPU divisor */
-#define PLL_CPUDIV 0x00300000
-#define CPC0_PLLMR0_CCDV 0x00300000
-#define PLL_CPUDIV_1 0x00000000
-#define PLL_CPUDIV_2 0x00100000
-#define PLL_CPUDIV_3 0x00200000
-#define PLL_CPUDIV_4 0x00300000
- /* PLB divisor */
-#define PLL_PLBDIV 0x00030000
-#define CPC0_PLLMR0_CBDV 0x00030000
-#define PLL_PLBDIV_1 0x00000000
-#define PLL_PLBDIV_2 0x00010000
-#define PLL_PLBDIV_3 0x00020000
-#define PLL_PLBDIV_4 0x00030000
- /* OPB divisor */
-#define PLL_OPBDIV 0x00003000
-#define CPC0_PLLMR0_OPDV 0x00003000
-#define PLL_OPBDIV_1 0x00000000
-#define PLL_OPBDIV_2 0x00001000
-#define PLL_OPBDIV_3 0x00002000
-#define PLL_OPBDIV_4 0x00003000
- /* EBC divisor */
-#define PLL_EXTBUSDIV 0x00000300
-#define CPC0_PLLMR0_EPDV 0x00000300
-#define PLL_EXTBUSDIV_2 0x00000000
-#define PLL_EXTBUSDIV_3 0x00000100
-#define PLL_EXTBUSDIV_4 0x00000200
-#define PLL_EXTBUSDIV_5 0x00000300
- /* MAL divisor */
-#define PLL_MALDIV 0x00000030
-#define CPC0_PLLMR0_MPDV 0x00000030
-#define PLL_MALDIV_1 0x00000000
-#define PLL_MALDIV_2 0x00000010
-#define PLL_MALDIV_3 0x00000020
-#define PLL_MALDIV_4 0x00000030
- /* PCI divisor */
-#define PLL_PCIDIV 0x00000003
-#define CPC0_PLLMR0_PPFD 0x00000003
-#define PLL_PCIDIV_1 0x00000000
-#define PLL_PCIDIV_2 0x00000001
-#define PLL_PCIDIV_3 0x00000002
-#define PLL_PCIDIV_4 0x00000003
-
-/*
- *-------------------------------------------------------------------------------
- * PLL settings for 266MHz CPU, 133MHz PLB/SDRAM, 66MHz EBC, 33MHz PCI,
- * assuming a 33.3MHz input clock to the 405EP.
- *-------------------------------------------------------------------------------
- */
-#define PLLMR0_266_133_66 (PLL_CPUDIV_1 | PLL_PLBDIV_2 | \
- PLL_OPBDIV_2 | PLL_EXTBUSDIV_2 | \
- PLL_MALDIV_1 | PLL_PCIDIV_4)
-#define PLLMR1_266_133_66 (PLL_FBKDIV_8 | \
- PLL_FWDDIVA_3 | PLL_FWDDIVB_3 | \
- PLL_TUNE_15_M_40 | PLL_TUNE_VCO_LOW)
-
-#define PLLMR0_133_66_66_33 (PLL_CPUDIV_1 | PLL_PLBDIV_1 | \
- PLL_OPBDIV_2 | PLL_EXTBUSDIV_4 | \
- PLL_MALDIV_1 | PLL_PCIDIV_4)
-#define PLLMR1_133_66_66_33 (PLL_FBKDIV_4 | \
- PLL_FWDDIVA_6 | PLL_FWDDIVB_6 | \
- PLL_TUNE_15_M_40 | PLL_TUNE_VCO_LOW)
-#define PLLMR0_200_100_50_33 (PLL_CPUDIV_1 | PLL_PLBDIV_2 | \
- PLL_OPBDIV_2 | PLL_EXTBUSDIV_3 | \
- PLL_MALDIV_1 | PLL_PCIDIV_4)
-#define PLLMR1_200_100_50_33 (PLL_FBKDIV_6 | \
- PLL_FWDDIVA_4 | PLL_FWDDIVB_4 | \
- PLL_TUNE_15_M_40 | PLL_TUNE_VCO_LOW)
-#define PLLMR0_266_133_66_33 (PLL_CPUDIV_1 | PLL_PLBDIV_2 | \
- PLL_OPBDIV_2 | PLL_EXTBUSDIV_4 | \
- PLL_MALDIV_1 | PLL_PCIDIV_4)
-#define PLLMR1_266_133_66_33 (PLL_FBKDIV_8 | \
- PLL_FWDDIVA_3 | PLL_FWDDIVB_3 | \
- PLL_TUNE_15_M_40 | PLL_TUNE_VCO_LOW)
-#define PLLMR0_266_66_33_33 (PLL_CPUDIV_1 | PLL_PLBDIV_4 | \
- PLL_OPBDIV_2 | PLL_EXTBUSDIV_2 | \
- PLL_MALDIV_1 | PLL_PCIDIV_2)
-#define PLLMR1_266_66_33_33 (PLL_FBKDIV_8 | \
- PLL_FWDDIVA_3 | PLL_FWDDIVB_3 | \
- PLL_TUNE_15_M_40 | PLL_TUNE_VCO_LOW)
-#define PLLMR0_333_111_55_37 (PLL_CPUDIV_1 | PLL_PLBDIV_3 | \
- PLL_OPBDIV_2 | PLL_EXTBUSDIV_2 | \
- PLL_MALDIV_1 | PLL_PCIDIV_3)
-#define PLLMR1_333_111_55_37 (PLL_FBKDIV_10 | \
- PLL_FWDDIVA_3 | PLL_FWDDIVB_3 | \
- PLL_TUNE_15_M_40 | PLL_TUNE_VCO_HI)
-#define PLLMR0_333_111_55_111 (PLL_CPUDIV_1 | PLL_PLBDIV_3 | \
- PLL_OPBDIV_2 | PLL_EXTBUSDIV_2 | \
- PLL_MALDIV_1 | PLL_PCIDIV_1)
-#define PLLMR1_333_111_55_111 (PLL_FBKDIV_10 | \
- PLL_FWDDIVA_3 | PLL_FWDDIVB_3 | \
- PLL_TUNE_15_M_40 | PLL_TUNE_VCO_HI)
-
-/*
- * PLL Voltage Controlled Oscillator (VCO) definitions
- * Maximum and minimum values (in MHz) for correct PLL operation.
- */
-#define VCO_MIN 500
-#define VCO_MAX 1000
-#elif defined(CONFIG_405EZ)
-#define sdrnand0 0x4000
-#define sdrultra0 0x4040
-#define sdrultra1 0x4050
-#define sdricintstat 0x4510
-
-#define SDR_NAND0_NDEN 0x80000000
-#define SDR_NAND0_NDBTEN 0x40000000
-#define SDR_NAND0_NDBADR_MASK 0x30000000
-#define SDR_NAND0_NDBPG_MASK 0x0f000000
-#define SDR_NAND0_NDAREN 0x00800000
-#define SDR_NAND0_NDRBEN 0x00400000
-
-#define SDR_ULTRA0_NDGPIOBP 0x80000000
-#define SDR_ULTRA0_CSN_MASK 0x78000000
-#define SDR_ULTRA0_CSNSEL0 0x40000000
-#define SDR_ULTRA0_CSNSEL1 0x20000000
-#define SDR_ULTRA0_CSNSEL2 0x10000000
-#define SDR_ULTRA0_CSNSEL3 0x08000000
-#define SDR_ULTRA0_EBCRDYEN 0x04000000
-#define SDR_ULTRA0_SPISSINEN 0x02000000
-#define SDR_ULTRA0_NFSRSTEN 0x01000000
-
-#define SDR_ULTRA1_LEDNENABLE 0x40000000
-
-#define SDR_ICRX_STAT 0x80000000
-#define SDR_ICTX0_STAT 0x40000000
-#define SDR_ICTX1_STAT 0x20000000
-
-#define SDR_PINSTP 0x40
-
-/******************************************************************************
- * Control
- ******************************************************************************/
-/* CPR Registers */
-#define cprclkupd 0x020 /* CPR_CLKUPD */
-#define cprpllc 0x040 /* CPR_PLLC */
-#define cprplld 0x060 /* CPR_PLLD */
-#define cprprimad 0x080 /* CPR_PRIMAD */
-#define cprperd0 0x0e0 /* CPR_PERD0 */
-#define cprperd1 0x0e1 /* CPR_PERD1 */
-#define cprperc0 0x180 /* CPR_PERC0 */
-#define cprmisc0 0x181 /* CPR_MISC0 */
-#define cprmisc1 0x182 /* CPR_MISC1 */
-
-#define CPR_CLKUPD_ENPLLCH_EN 0x40000000 /* Enable CPR PLL Changes */
-#define CPR_CLKUPD_ENDVCH_EN 0x20000000 /* Enable CPR Sys. Div. Changes */
-#define CPR_PERD0_SPIDV_MASK 0x000F0000 /* SPI Clock Divider */
-
-#define PLLC_SRC_MASK 0x20000000 /* PLL feedback source */
-
-#define PLLD_FBDV_MASK 0x1F000000 /* PLL feedback divider value */
-#define PLLD_FWDVA_MASK 0x000F0000 /* PLL forward divider A value */
-#define PLLD_FWDVB_MASK 0x00000700 /* PLL forward divider B value */
-
-#define PRIMAD_CPUDV_MASK 0x0F000000 /* CPU Clock Divisor Mask */
-#define PRIMAD_PLBDV_MASK 0x000F0000 /* PLB Clock Divisor Mask */
-#define PRIMAD_OPBDV_MASK 0x00000F00 /* OPB Clock Divisor Mask */
-#define PRIMAD_EBCDV_MASK 0x0000000F /* EBC Clock Divisor Mask */
-
-#define PERD0_PWMDV_MASK 0xFF000000 /* PWM Divider Mask */
-#define PERD0_SPIDV_MASK 0x000F0000 /* SPI Divider Mask */
-#define PERD0_U0DV_MASK 0x0000FF00 /* UART 0 Divider Mask */
-#define PERD0_U1DV_MASK 0x000000FF /* UART 1 Divider Mask */
-
-#else /* #ifdef CONFIG_405EP */
-/******************************************************************************
- * Control
- ******************************************************************************/
-#define CNTRL_DCR_BASE 0x0b0
-#define pllmd (CNTRL_DCR_BASE+0x0) /* PLL mode register */
-#define cntrl0 (CNTRL_DCR_BASE+0x1) /* Control 0 register */
-#define cntrl1 (CNTRL_DCR_BASE+0x2) /* Control 1 register */
-#define reset (CNTRL_DCR_BASE+0x3) /* reset register */
-#define strap (CNTRL_DCR_BASE+0x4) /* strap register */
-
-#define CPC0_CR0 (CNTRL_DCR_BASE+0x1) /* chip control register 0 */
-#define CPC0_CR1 (CNTRL_DCR_BASE+0x2) /* chip control register 1 */
-#define CPC0_PSR (CNTRL_DCR_BASE+0x4) /* chip pin strapping register */
-
-/* CPC0_ECR/CPC0_EIRR: PPC405GPr only */
-#define CPC0_EIRR (CNTRL_DCR_BASE+0x6) /* external interrupt routing register */
-#define CPC0_ECR (0xaa) /* edge conditioner register */
-
-#define ecr (0xaa) /* edge conditioner register (405gpr) */
-
-/* Bit definitions */
-#define PLLMR_FWD_DIV_MASK 0xE0000000 /* Forward Divisor */
-#define PLLMR_FWD_DIV_BYPASS 0xE0000000
-#define PLLMR_FWD_DIV_3 0xA0000000
-#define PLLMR_FWD_DIV_4 0x80000000
-#define PLLMR_FWD_DIV_6 0x40000000
-
-#define PLLMR_FB_DIV_MASK 0x1E000000 /* Feedback Divisor */
-#define PLLMR_FB_DIV_1 0x02000000
-#define PLLMR_FB_DIV_2 0x04000000
-#define PLLMR_FB_DIV_3 0x06000000
-#define PLLMR_FB_DIV_4 0x08000000
-
-#define PLLMR_TUNING_MASK 0x01F80000
-
-#define PLLMR_CPU_TO_PLB_MASK 0x00060000 /* CPU:PLB Frequency Divisor */
-#define PLLMR_CPU_PLB_DIV_1 0x00000000
-#define PLLMR_CPU_PLB_DIV_2 0x00020000
-#define PLLMR_CPU_PLB_DIV_3 0x00040000
-#define PLLMR_CPU_PLB_DIV_4 0x00060000
-
-#define PLLMR_OPB_TO_PLB_MASK 0x00018000 /* OPB:PLB Frequency Divisor */
-#define PLLMR_OPB_PLB_DIV_1 0x00000000
-#define PLLMR_OPB_PLB_DIV_2 0x00008000
-#define PLLMR_OPB_PLB_DIV_3 0x00010000
-#define PLLMR_OPB_PLB_DIV_4 0x00018000
-
-#define PLLMR_PCI_TO_PLB_MASK 0x00006000 /* PCI:PLB Frequency Divisor */
-#define PLLMR_PCI_PLB_DIV_1 0x00000000
-#define PLLMR_PCI_PLB_DIV_2 0x00002000
-#define PLLMR_PCI_PLB_DIV_3 0x00004000
-#define PLLMR_PCI_PLB_DIV_4 0x00006000
-
-#define PLLMR_EXB_TO_PLB_MASK 0x00001800 /* External Bus:PLB Divisor */
-#define PLLMR_EXB_PLB_DIV_2 0x00000000
-#define PLLMR_EXB_PLB_DIV_3 0x00000800
-#define PLLMR_EXB_PLB_DIV_4 0x00001000
-#define PLLMR_EXB_PLB_DIV_5 0x00001800
-
-/* definitions for PPC405GPr (new mode strapping) */
-#define PLLMR_FWDB_DIV_MASK 0x00000007 /* Forward Divisor B */
-
-#define PSR_PLL_FWD_MASK 0xC0000000
-#define PSR_PLL_FDBACK_MASK 0x30000000
-#define PSR_PLL_TUNING_MASK 0x0E000000
-#define PSR_PLB_CPU_MASK 0x01800000
-#define PSR_OPB_PLB_MASK 0x00600000
-#define PSR_PCI_PLB_MASK 0x00180000
-#define PSR_EB_PLB_MASK 0x00060000
-#define PSR_ROM_WIDTH_MASK 0x00018000
-#define PSR_ROM_LOC 0x00004000
-#define PSR_PCI_ASYNC_EN 0x00001000
-#define PSR_PERCLK_SYNC_MODE_EN 0x00000800 /* PPC405GPr only */
-#define PSR_PCI_ARBIT_EN 0x00000400
-#define PSR_NEW_MODE_EN 0x00000020 /* PPC405GPr only */
-
-#ifndef CONFIG_IOP480
-/*
- * PLL Voltage Controlled Oscillator (VCO) definitions
- * Maximum and minimum values (in MHz) for correct PLL operation.
- */
-#define VCO_MIN 400
-#define VCO_MAX 800
-#endif /* #ifndef CONFIG_IOP480 */
-#endif /* #ifdef CONFIG_405EP */
-
-/******************************************************************************
- * Memory Access Layer
- ******************************************************************************/
-#if defined(CONFIG_405EZ)
-#define MAL_DCR_BASE 0x380
-#define malmcr (MAL_DCR_BASE+0x00) /* MAL Config reg */
-#define malesr (MAL_DCR_BASE+0x01) /* Err Status reg (Read/Clear)*/
-#define malier (MAL_DCR_BASE+0x02) /* Interrupt enable reg */
-#define maldbr (MAL_DCR_BASE+0x03) /* Mal Debug reg (Read only) */
-#define maltxcasr (MAL_DCR_BASE+0x04) /* TX Channel active reg (set)*/
-#define maltxcarr (MAL_DCR_BASE+0x05) /* TX Channel active reg (Reset) */
-#define maltxeobisr (MAL_DCR_BASE+0x06) /* TX End of buffer int status reg */
-#define maltxdeir (MAL_DCR_BASE+0x07) /* TX Descr. Error Int reg */
-/* 0x08-0x0F Reserved */
-#define malrxcasr (MAL_DCR_BASE+0x10) /* RX Channel active reg (set)*/
-#define malrxcarr (MAL_DCR_BASE+0x11) /* RX Channel active reg (Reset) */
-#define malrxeobisr (MAL_DCR_BASE+0x12) /* RX End of buffer int status reg */
-#define malrxdeir (MAL_DCR_BASE+0x13) /* RX Descr. Error Int reg */
-/* 0x14-0x1F Reserved */
-#define maltxctp0r (MAL_DCR_BASE+0x20) /* TX 0 Channel table ptr reg */
-#define maltxctp1r (MAL_DCR_BASE+0x21) /* TX 1 Channel table ptr reg */
-#define maltxctp2r (MAL_DCR_BASE+0x22) /* TX 2 Channel table ptr reg */
-#define maltxctp3r (MAL_DCR_BASE+0x23) /* TX 3 Channel table ptr reg */
-#define maltxctp4r (MAL_DCR_BASE+0x24) /* TX 4 Channel table ptr reg */
-#define maltxctp5r (MAL_DCR_BASE+0x25) /* TX 5 Channel table ptr reg */
-#define maltxctp6r (MAL_DCR_BASE+0x26) /* TX 6 Channel table ptr reg */
-#define maltxctp7r (MAL_DCR_BASE+0x27) /* TX 7 Channel table ptr reg */
-#define maltxctp8r (MAL_DCR_BASE+0x28) /* TX 8 Channel table ptr reg */
-#define maltxctp9r (MAL_DCR_BASE+0x29) /* TX 9 Channel table ptr reg */
-#define maltxctp10r (MAL_DCR_BASE+0x2A) /* TX 10 Channel table ptr reg */
-#define maltxctp11r (MAL_DCR_BASE+0x2B) /* TX 11 Channel table ptr reg */
-#define maltxctp12r (MAL_DCR_BASE+0x2C) /* TX 12 Channel table ptr reg */
-#define maltxctp13r (MAL_DCR_BASE+0x2D) /* TX 13 Channel table ptr reg */
-#define maltxctp14r (MAL_DCR_BASE+0x2E) /* TX 14 Channel table ptr reg */
-#define maltxctp15r (MAL_DCR_BASE+0x2F) /* TX 15 Channel table ptr reg */
-#define maltxctp16r (MAL_DCR_BASE+0x30) /* TX 16 Channel table ptr reg */
-#define maltxctp17r (MAL_DCR_BASE+0x31) /* TX 17 Channel table ptr reg */
-#define maltxctp18r (MAL_DCR_BASE+0x32) /* TX 18 Channel table ptr reg */
-#define maltxctp19r (MAL_DCR_BASE+0x33) /* TX 19 Channel table ptr reg */
-#define maltxctp20r (MAL_DCR_BASE+0x34) /* TX 20 Channel table ptr reg */
-#define maltxctp21r (MAL_DCR_BASE+0x35) /* TX 21 Channel table ptr reg */
-#define maltxctp22r (MAL_DCR_BASE+0x36) /* TX 22 Channel table ptr reg */
-#define maltxctp23r (MAL_DCR_BASE+0x37) /* TX 23 Channel table ptr reg */
-#define maltxctp24r (MAL_DCR_BASE+0x38) /* TX 24 Channel table ptr reg */
-#define maltxctp25r (MAL_DCR_BASE+0x39) /* TX 25 Channel table ptr reg */
-#define maltxctp26r (MAL_DCR_BASE+0x3A) /* TX 26 Channel table ptr reg */
-#define maltxctp27r (MAL_DCR_BASE+0x3B) /* TX 27 Channel table ptr reg */
-#define maltxctp28r (MAL_DCR_BASE+0x3C) /* TX 28 Channel table ptr reg */
-#define maltxctp29r (MAL_DCR_BASE+0x3D) /* TX 29 Channel table ptr reg */
-#define maltxctp30r (MAL_DCR_BASE+0x3E) /* TX 30 Channel table ptr reg */
-#define maltxctp31r (MAL_DCR_BASE+0x3F) /* TX 31 Channel table ptr reg */
-#define malrxctp0r (MAL_DCR_BASE+0x40) /* RX 0 Channel table ptr reg */
-#define malrxctp1r (MAL_DCR_BASE+0x41) /* RX 1 Channel table ptr reg */
-#define malrxctp2r (MAL_DCR_BASE+0x42) /* RX 2 Channel table ptr reg */
-#define malrxctp3r (MAL_DCR_BASE+0x43) /* RX 3 Channel table ptr reg */
-#define malrxctp4r (MAL_DCR_BASE+0x44) /* RX 4 Channel table ptr reg */
-#define malrxctp5r (MAL_DCR_BASE+0x45) /* RX 5 Channel table ptr reg */
-#define malrxctp6r (MAL_DCR_BASE+0x46) /* RX 6 Channel table ptr reg */
-#define malrxctp7r (MAL_DCR_BASE+0x47) /* RX 7 Channel table ptr reg */
-#define malrxctp8r (MAL_DCR_BASE+0x48) /* RX 8 Channel table ptr reg */
-#define malrxctp9r (MAL_DCR_BASE+0x49) /* RX 9 Channel table ptr reg */
-#define malrxctp10r (MAL_DCR_BASE+0x4A) /* RX 10 Channel table ptr reg */
-#define malrxctp11r (MAL_DCR_BASE+0x4B) /* RX 11 Channel table ptr reg */
-#define malrxctp12r (MAL_DCR_BASE+0x4C) /* RX 12 Channel table ptr reg */
-#define malrxctp13r (MAL_DCR_BASE+0x4D) /* RX 13 Channel table ptr reg */
-#define malrxctp14r (MAL_DCR_BASE+0x4E) /* RX 14 Channel table ptr reg */
-#define malrxctp15r (MAL_DCR_BASE+0x4F) /* RX 15 Channel table ptr reg */
-#define malrxctp16r (MAL_DCR_BASE+0x50) /* RX 16 Channel table ptr reg */
-#define malrxctp17r (MAL_DCR_BASE+0x51) /* RX 17 Channel table ptr reg */
-#define malrxctp18r (MAL_DCR_BASE+0x52) /* RX 18 Channel table ptr reg */
-#define malrxctp19r (MAL_DCR_BASE+0x53) /* RX 19 Channel table ptr reg */
-#define malrxctp20r (MAL_DCR_BASE+0x54) /* RX 20 Channel table ptr reg */
-#define malrxctp21r (MAL_DCR_BASE+0x55) /* RX 21 Channel table ptr reg */
-#define malrxctp22r (MAL_DCR_BASE+0x56) /* RX 22 Channel table ptr reg */
-#define malrxctp23r (MAL_DCR_BASE+0x57) /* RX 23 Channel table ptr reg */
-#define malrxctp24r (MAL_DCR_BASE+0x58) /* RX 24 Channel table ptr reg */
-#define malrxctp25r (MAL_DCR_BASE+0x59) /* RX 25 Channel table ptr reg */
-#define malrxctp26r (MAL_DCR_BASE+0x5A) /* RX 26 Channel table ptr reg */
-#define malrxctp27r (MAL_DCR_BASE+0x5B) /* RX 27 Channel table ptr reg */
-#define malrxctp28r (MAL_DCR_BASE+0x5C) /* RX 28 Channel table ptr reg */
-#define malrxctp29r (MAL_DCR_BASE+0x5D) /* RX 29 Channel table ptr reg */
-#define malrxctp30r (MAL_DCR_BASE+0x5E) /* RX 30 Channel table ptr reg */
-#define malrxctp31r (MAL_DCR_BASE+0x5F) /* RX 31 Channel table ptr reg */
-#define malrcbs0 (MAL_DCR_BASE+0x60) /* RX 0 Channel buffer size reg */
-#define malrcbs1 (MAL_DCR_BASE+0x61) /* RX 1 Channel buffer size reg */
-#define malrcbs2 (MAL_DCR_BASE+0x62) /* RX 2 Channel buffer size reg */
-#define malrcbs3 (MAL_DCR_BASE+0x63) /* RX 3 Channel buffer size reg */
-#define malrcbs4 (MAL_DCR_BASE+0x64) /* RX 4 Channel buffer size reg */
-#define malrcbs5 (MAL_DCR_BASE+0x65) /* RX 5 Channel buffer size reg */
-#define malrcbs6 (MAL_DCR_BASE+0x66) /* RX 6 Channel buffer size reg */
-#define malrcbs7 (MAL_DCR_BASE+0x67) /* RX 7 Channel buffer size reg */
-#define malrcbs8 (MAL_DCR_BASE+0x68) /* RX 8 Channel buffer size reg */
-#define malrcbs9 (MAL_DCR_BASE+0x69) /* RX 9 Channel buffer size reg */
-#define malrcbs10 (MAL_DCR_BASE+0x6A) /* RX 10 Channel buffer size reg */
-#define malrcbs11 (MAL_DCR_BASE+0x6B) /* RX 11 Channel buffer size reg */
-#define malrcbs12 (MAL_DCR_BASE+0x6C) /* RX 12 Channel buffer size reg */
-#define malrcbs13 (MAL_DCR_BASE+0x6D) /* RX 13 Channel buffer size reg */
-#define malrcbs14 (MAL_DCR_BASE+0x6E) /* RX 14 Channel buffer size reg */
-#define malrcbs15 (MAL_DCR_BASE+0x6F) /* RX 15 Channel buffer size reg */
-#define malrcbs16 (MAL_DCR_BASE+0x70) /* RX 16 Channel buffer size reg */
-#define malrcbs17 (MAL_DCR_BASE+0x71) /* RX 17 Channel buffer size reg */
-#define malrcbs18 (MAL_DCR_BASE+0x72) /* RX 18 Channel buffer size reg */
-#define malrcbs19 (MAL_DCR_BASE+0x73) /* RX 19 Channel buffer size reg */
-#define malrcbs20 (MAL_DCR_BASE+0x74) /* RX 20 Channel buffer size reg */
-#define malrcbs21 (MAL_DCR_BASE+0x75) /* RX 21 Channel buffer size reg */
-#define malrcbs22 (MAL_DCR_BASE+0x76) /* RX 22 Channel buffer size reg */
-#define malrcbs23 (MAL_DCR_BASE+0x77) /* RX 23 Channel buffer size reg */
-#define malrcbs24 (MAL_DCR_BASE+0x78) /* RX 24 Channel buffer size reg */
-#define malrcbs25 (MAL_DCR_BASE+0x79) /* RX 25 Channel buffer size reg */
-#define malrcbs26 (MAL_DCR_BASE+0x7A) /* RX 26 Channel buffer size reg */
-#define malrcbs27 (MAL_DCR_BASE+0x7B) /* RX 27 Channel buffer size reg */
-#define malrcbs28 (MAL_DCR_BASE+0x7C) /* RX 28 Channel buffer size reg */
-#define malrcbs29 (MAL_DCR_BASE+0x7D) /* RX 29 Channel buffer size reg */
-#define malrcbs30 (MAL_DCR_BASE+0x7E) /* RX 30 Channel buffer size reg */
-#define malrcbs31 (MAL_DCR_BASE+0x7F) /* RX 31 Channel buffer size reg */
-
-#else /* !defined(CONFIG_405EZ) */
-
-#define MAL_DCR_BASE 0x180
-#define malmcr (MAL_DCR_BASE+0x00) /* MAL Config reg */
-#define malesr (MAL_DCR_BASE+0x01) /* Error Status reg (Read/Clear) */
-#define malier (MAL_DCR_BASE+0x02) /* Interrupt enable reg */
-#define maldbr (MAL_DCR_BASE+0x03) /* Mal Debug reg (Read only) */
-#define maltxcasr (MAL_DCR_BASE+0x04) /* TX Channel active reg (set) */
-#define maltxcarr (MAL_DCR_BASE+0x05) /* TX Channel active reg (Reset) */
-#define maltxeobisr (MAL_DCR_BASE+0x06) /* TX End of buffer int status reg */
-#define maltxdeir (MAL_DCR_BASE+0x07) /* TX Descr. Error Int reg */
-#define malrxcasr (MAL_DCR_BASE+0x10) /* RX Channel active reg (set) */
-#define malrxcarr (MAL_DCR_BASE+0x11) /* RX Channel active reg (Reset) */
-#define malrxeobisr (MAL_DCR_BASE+0x12) /* RX End of buffer int status reg */
-#define malrxdeir (MAL_DCR_BASE+0x13) /* RX Descr. Error Int reg */
-#define maltxctp0r (MAL_DCR_BASE+0x20) /* TX 0 Channel table pointer reg */
-#define maltxctp1r (MAL_DCR_BASE+0x21) /* TX 1 Channel table pointer reg */
-#define maltxctp2r (MAL_DCR_BASE+0x22) /* TX 2 Channel table pointer reg */
-#define malrxctp0r (MAL_DCR_BASE+0x40) /* RX 0 Channel table pointer reg */
-#define malrxctp1r (MAL_DCR_BASE+0x41) /* RX 1 Channel table pointer reg */
-#define malrcbs0 (MAL_DCR_BASE+0x60) /* RX 0 Channel buffer size reg */
-#define malrcbs1 (MAL_DCR_BASE+0x61) /* RX 1 Channel buffer size reg */
-#endif /* defined(CONFIG_405EZ) */
-
-/*-----------------------------------------------------------------------------
-| IIC Register Offsets
-'----------------------------------------------------------------------------*/
-#define IICMDBUF 0x00
-#define IICSDBUF 0x02
-#define IICLMADR 0x04
-#define IICHMADR 0x05
-#define IICCNTL 0x06
-#define IICMDCNTL 0x07
-#define IICSTS 0x08
-#define IICEXTSTS 0x09
-#define IICLSADR 0x0A
-#define IICHSADR 0x0B
-#define IICCLKDIV 0x0C
-#define IICINTRMSK 0x0D
-#define IICXFRCNT 0x0E
-#define IICXTCNTLSS 0x0F
-#define IICDIRECTCNTL 0x10
-
-/*-----------------------------------------------------------------------------
-| UART Register Offsets
-'----------------------------------------------------------------------------*/
-#define DATA_REG 0x00
-#define DL_LSB 0x00
-#define DL_MSB 0x01
-#define INT_ENABLE 0x01
-#define FIFO_CONTROL 0x02
-#define LINE_CONTROL 0x03
-#define MODEM_CONTROL 0x04
-#define LINE_STATUS 0x05
-#define MODEM_STATUS 0x06
-#define SCRATCH 0x07
-
-/******************************************************************************
- * On Chip Memory
- ******************************************************************************/
-#if defined(CONFIG_405EZ)
-#define OCM_DCR_BASE 0x020
-#define ocmplb3cr1 (OCM_DCR_BASE+0x00) /* OCM PLB3 Bank 1 Config Reg */
-#define ocmplb3cr2 (OCM_DCR_BASE+0x01) /* OCM PLB3 Bank 2 Config Reg */
-#define ocmplb3bear (OCM_DCR_BASE+0x02) /* OCM PLB3 Bus Error Add Reg */
-#define ocmplb3besr0 (OCM_DCR_BASE+0x03) /* OCM PLB3 Bus Error Stat Reg 0 */
-#define ocmplb3besr1 (OCM_DCR_BASE+0x04) /* OCM PLB3 Bus Error Stat Reg 1 */
-#define ocmcid (OCM_DCR_BASE+0x05) /* OCM Core ID */
-#define ocmrevid (OCM_DCR_BASE+0x06) /* OCM Revision ID */
-#define ocmplb3dpc (OCM_DCR_BASE+0x07) /* OCM PLB3 Data Parity Check */
-#define ocmdscr1 (OCM_DCR_BASE+0x08) /* OCM D-side Bank 1 Config Reg */
-#define ocmdscr2 (OCM_DCR_BASE+0x09) /* OCM D-side Bank 2 Config Reg */
-#define ocmiscr1 (OCM_DCR_BASE+0x0A) /* OCM I-side Bank 1 Config Reg */
-#define ocmiscr2 (OCM_DCR_BASE+0x0B) /* OCM I-side Bank 2 Config Reg */
-#define ocmdsisdpc (OCM_DCR_BASE+0x0C) /* OCM D-side/I-side Data Par Chk*/
-#define ocmdsisbear (OCM_DCR_BASE+0x0D) /* OCM D-side/I-side Bus Err Addr*/
-#define ocmdsisbesr (OCM_DCR_BASE+0x0E) /* OCM D-side/I-side Bus Err Stat*/
-#else
-#define OCM_DCR_BASE 0x018
-#define ocmisarc (OCM_DCR_BASE+0x00) /* OCM I-side address compare reg */
-#define ocmiscntl (OCM_DCR_BASE+0x01) /* OCM I-side control reg */
-#define ocmdsarc (OCM_DCR_BASE+0x02) /* OCM D-side address compare reg */
-#define ocmdscntl (OCM_DCR_BASE+0x03) /* OCM D-side control reg */
-#endif /* CONFIG_405EZ */
-
-/******************************************************************************
- * GPIO macro register defines
- ******************************************************************************/
-#if defined(CONFIG_405EZ)
-/* Only the 405EZ has 2 GPIOs */
-#define GPIO_BASE 0xEF600700
-#define GPIO0_OR (GPIO_BASE+0x0)
-#define GPIO0_TCR (GPIO_BASE+0x4)
-#define GPIO0_OSRL (GPIO_BASE+0x8)
-#define GPIO0_OSRH (GPIO_BASE+0xC)
-#define GPIO0_TSRL (GPIO_BASE+0x10)
-#define GPIO0_TSRH (GPIO_BASE+0x14)
-#define GPIO0_ODR (GPIO_BASE+0x18)
-#define GPIO0_IR (GPIO_BASE+0x1C)
-#define GPIO0_RR1 (GPIO_BASE+0x20)
-#define GPIO0_RR2 (GPIO_BASE+0x24)
-#define GPIO0_RR3 (GPIO_BASE+0x28)
-#define GPIO0_ISR1L (GPIO_BASE+0x30)
-#define GPIO0_ISR1H (GPIO_BASE+0x34)
-#define GPIO0_ISR2L (GPIO_BASE+0x38)
-#define GPIO0_ISR2H (GPIO_BASE+0x3C)
-#define GPIO0_ISR3L (GPIO_BASE+0x40)
-#define GPIO0_ISR3H (GPIO_BASE+0x44)
-
-#define GPIO1_BASE 0xEF600800
-#define GPIO1_OR (GPIO1_BASE+0x0)
-#define GPIO1_TCR (GPIO1_BASE+0x4)
-#define GPIO1_OSRL (GPIO1_BASE+0x8)
-#define GPIO1_OSRH (GPIO1_BASE+0xC)
-#define GPIO1_TSRL (GPIO1_BASE+0x10)
-#define GPIO1_TSRH (GPIO1_BASE+0x14)
-#define GPIO1_ODR (GPIO1_BASE+0x18)
-#define GPIO1_IR (GPIO1_BASE+0x1C)
-#define GPIO1_RR1 (GPIO1_BASE+0x20)
-#define GPIO1_RR2 (GPIO1_BASE+0x24)
-#define GPIO1_RR3 (GPIO1_BASE+0x28)
-#define GPIO1_ISR1L (GPIO1_BASE+0x30)
-#define GPIO1_ISR1H (GPIO1_BASE+0x34)
-#define GPIO1_ISR2L (GPIO1_BASE+0x38)
-#define GPIO1_ISR2H (GPIO1_BASE+0x3C)
-#define GPIO1_ISR3L (GPIO1_BASE+0x40)
-#define GPIO1_ISR3H (GPIO1_BASE+0x44)
-
-#elif defined(CONFIG_405EX)
-#define GPIO_BASE 0xEF600800
-#define GPIO0_OR (GPIO_BASE+0x0)
-#define GPIO0_TCR (GPIO_BASE+0x4)
-#define GPIO0_OSRL (GPIO_BASE+0x8)
-#define GPIO0_OSRH (GPIO_BASE+0xC)
-#define GPIO0_TSRL (GPIO_BASE+0x10)
-#define GPIO0_TSRH (GPIO_BASE+0x14)
-#define GPIO0_ODR (GPIO_BASE+0x18)
-#define GPIO0_IR (GPIO_BASE+0x1C)
-#define GPIO0_RR1 (GPIO_BASE+0x20)
-#define GPIO0_RR2 (GPIO_BASE+0x24)
-#define GPIO0_ISR1L (GPIO_BASE+0x30)
-#define GPIO0_ISR1H (GPIO_BASE+0x34)
-#define GPIO0_ISR2L (GPIO_BASE+0x38)
-#define GPIO0_ISR2H (GPIO_BASE+0x3C)
-#define GPIO0_ISR3L (GPIO_BASE+0x40)
-#define GPIO0_ISR3H (GPIO_BASE+0x44)
-
-#else /* !405EZ */
-
-#define GPIO_BASE 0xEF600700
-#define GPIO0_OR (GPIO_BASE+0x0)
-#define GPIO0_TCR (GPIO_BASE+0x4)
-#define GPIO0_OSRH (GPIO_BASE+0x8)
-#define GPIO0_OSRL (GPIO_BASE+0xC)
-#define GPIO0_TSRH (GPIO_BASE+0x10)
-#define GPIO0_TSRL (GPIO_BASE+0x14)
-#define GPIO0_ODR (GPIO_BASE+0x18)
-#define GPIO0_IR (GPIO_BASE+0x1C)
-#define GPIO0_RR1 (GPIO_BASE+0x20)
-#define GPIO0_RR2 (GPIO_BASE+0x24)
-#define GPIO0_ISR1H (GPIO_BASE+0x30)
-#define GPIO0_ISR1L (GPIO_BASE+0x34)
-#define GPIO0_ISR2H (GPIO_BASE+0x38)
-#define GPIO0_ISR2L (GPIO_BASE+0x3C)
-
-#endif /* CONFIG_405EZ */
-
-#define GPIO0_BASE GPIO_BASE
-
-#if defined(CONFIG_405EX)
-#define SDR0_SRST 0x0200
-
-/*
- * Software Reset Register
- */
-#define SDR0_SRST_BGO PPC_REG_VAL(0, 1)
-#define SDR0_SRST_PLB4 PPC_REG_VAL(1, 1)
-#define SDR0_SRST_EBC PPC_REG_VAL(2, 1)
-#define SDR0_SRST_OPB PPC_REG_VAL(3, 1)
-#define SDR0_SRST_UART0 PPC_REG_VAL(4, 1)
-#define SDR0_SRST_UART1 PPC_REG_VAL(5, 1)
-#define SDR0_SRST_IIC0 PPC_REG_VAL(6, 1)
-#define SDR0_SRST_BGI PPC_REG_VAL(7, 1)
-#define SDR0_SRST_GPIO PPC_REG_VAL(8, 1)
-#define SDR0_SRST_GPT PPC_REG_VAL(9, 1)
-#define SDR0_SRST_DMC PPC_REG_VAL(10, 1)
-#define SDR0_SRST_RGMII PPC_REG_VAL(11, 1)
-#define SDR0_SRST_EMAC0 PPC_REG_VAL(12, 1)
-#define SDR0_SRST_EMAC1 PPC_REG_VAL(13, 1)
-#define SDR0_SRST_CPM PPC_REG_VAL(14, 1)
-#define SDR0_SRST_EPLL PPC_REG_VAL(15, 1)
-#define SDR0_SRST_UIC PPC_REG_VAL(16, 1)
-#define SDR0_SRST_UPRST PPC_REG_VAL(17, 1)
-#define SDR0_SRST_IIC1 PPC_REG_VAL(18, 1)
-#define SDR0_SRST_SCP PPC_REG_VAL(19, 1)
-#define SDR0_SRST_UHRST PPC_REG_VAL(20, 1)
-#define SDR0_SRST_DMA PPC_REG_VAL(21, 1)
-#define SDR0_SRST_DMAC PPC_REG_VAL(22, 1)
-#define SDR0_SRST_MAL PPC_REG_VAL(23, 1)
-#define SDR0_SRST_EBM PPC_REG_VAL(24, 1)
-#define SDR0_SRST_GPTR PPC_REG_VAL(25, 1)
-#define SDR0_SRST_PE0 PPC_REG_VAL(26, 1)
-#define SDR0_SRST_PE1 PPC_REG_VAL(27, 1)
-#define SDR0_SRST_CRYP PPC_REG_VAL(28, 1)
-#define SDR0_SRST_PKP PPC_REG_VAL(29, 1)
-#define SDR0_SRST_AHB PPC_REG_VAL(30, 1)
-#define SDR0_SRST_NDFC PPC_REG_VAL(31, 1)
-
-#define sdr_uart0 0x0120 /* UART0 Config */
-#define sdr_uart1 0x0121 /* UART1 Config */
-#define sdr_mfr 0x4300 /* SDR0_MFR reg */
-
-/* Defines for CPC0_EPRCSR register */
-#define CPC0_EPRCSR_E0NFE 0x80000000
-#define CPC0_EPRCSR_E1NFE 0x40000000
-#define CPC0_EPRCSR_E1RPP 0x00000080
-#define CPC0_EPRCSR_E0RPP 0x00000040
-#define CPC0_EPRCSR_E1ERP 0x00000020
-#define CPC0_EPRCSR_E0ERP 0x00000010
-#define CPC0_EPRCSR_E1PCI 0x00000002
-#define CPC0_EPRCSR_E0PCI 0x00000001
-
-#define cpr0_clkupd 0x020
-#define cpr0_pllc 0x040
-#define cpr0_plld 0x060
-#define cpr0_cpud 0x080
-#define cpr0_plbd 0x0a0
-#define cpr0_opbd 0x0c0
-#define cpr0_perd 0x0e0
-#define cpr0_ahbd 0x100
-#define cpr0_icfg 0x140
-
-#define SDR_PINSTP 0x0040
-#define sdr_sdcs 0x0060
-
-#define SDR0_SDCS_SDD (0x80000000 >> 31)
-
-/* CUST0 Customer Configuration Register0 */
-#define SDR0_CUST0 0x4000
-#define SDR0_CUST0_MUX_E_N_G_MASK 0xC0000000 /* Mux_Emac_NDFC_GPIO */
-#define SDR0_CUST0_MUX_EMAC_SEL 0x40000000 /* Emac Selection */
-#define SDR0_CUST0_MUX_NDFC_SEL 0x80000000 /* NDFC Selection */
-#define SDR0_CUST0_MUX_GPIO_SEL 0xC0000000 /* GPIO Selection */
-
-#define SDR0_CUST0_NDFC_EN_MASK 0x20000000 /* NDFC Enable Mask */
-#define SDR0_CUST0_NDFC_ENABLE 0x20000000 /* NDFC Enable */
-#define SDR0_CUST0_NDFC_DISABLE 0x00000000 /* NDFC Disable */
-
-#define SDR0_CUST0_NDFC_BW_MASK 0x10000000 /* NDFC Boot Width */
-#define SDR0_CUST0_NDFC_BW_16_BIT 0x10000000 /* NDFC Boot Width = 16 Bit */
-#define SDR0_CUST0_NDFC_BW_8_BIT 0x00000000 /* NDFC Boot Width = 8 Bit */
-
-#define SDR0_CUST0_NDFC_BP_MASK 0x0F000000 /* NDFC Boot Page */
-#define SDR0_CUST0_NDFC_BP_ENCODE(n) ((((unsigned long)(n))&0xF)<<24)
-#define SDR0_CUST0_NDFC_BP_DECODE(n) ((((unsigned long)(n))>>24)&0x0F)
-
-#define SDR0_CUST0_NDFC_BAC_MASK 0x00C00000 /* NDFC Boot Address Cycle */
-#define SDR0_CUST0_NDFC_BAC_ENCODE(n) ((((unsigned long)(n))&0x3)<<22)
-#define SDR0_CUST0_NDFC_BAC_DECODE(n) ((((unsigned long)(n))>>22)&0x03)
-
-#define SDR0_CUST0_NDFC_ARE_MASK 0x00200000 /* NDFC Auto Read Enable */
-#define SDR0_CUST0_NDFC_ARE_ENABLE 0x00200000 /* NDFC Auto Read Enable */
-#define SDR0_CUST0_NDFC_ARE_DISABLE 0x00000000 /* NDFC Auto Read Disable */
-
-#define SDR0_CUST0_NRB_MASK 0x00100000 /* NDFC Ready / Busy */
-#define SDR0_CUST0_NRB_BUSY 0x00100000 /* Busy */
-#define SDR0_CUST0_NRB_READY 0x00000000 /* Ready */
-
-#define SDR0_CUST0_NDRSC_MASK 0x0000FFF0 /* NDFC Device Reset Count Mask */
-#define SDR0_CUST0_NDRSC_ENCODE(n) ((((unsigned long)(n))&0xFFF)<<4)
-#define SDR0_CUST0_NDRSC_DECODE(n) ((((unsigned long)(n))>>4)&0xFFF)
-
-#define SDR0_CUST0_CHIPSELGAT_MASK 0x0000000F /* Chip Select Gating Mask */
-#define SDR0_CUST0_CHIPSELGAT_DIS 0x00000000 /* Chip Select Gating Disable */
-#define SDR0_CUST0_CHIPSELGAT_ENALL 0x0000000F /* All Chip Select Gating Enable */
-#define SDR0_CUST0_CHIPSELGAT_EN0 0x00000008 /* Chip Select0 Gating Enable */
-#define SDR0_CUST0_CHIPSELGAT_EN1 0x00000004 /* Chip Select1 Gating Enable */
-#define SDR0_CUST0_CHIPSELGAT_EN2 0x00000002 /* Chip Select2 Gating Enable */
-#define SDR0_CUST0_CHIPSELGAT_EN3 0x00000001 /* Chip Select3 Gating Enable */
-
-#define SDR0_PFC0 0x4100
-#define SDR0_PFC1 0x4101
-#define SDR0_PFC1_U1ME 0x02000000
-#define SDR0_PFC1_U0ME 0x00080000
-#define SDR0_PFC1_U0IM 0x00040000
-#define SDR0_PFC1_SIS 0x00020000
-#define SDR0_PFC1_DMAAEN 0x00010000
-#define SDR0_PFC1_DMADEN 0x00008000
-#define SDR0_PFC1_USBEN 0x00004000
-#define SDR0_PFC1_AHBSWAP 0x00000020
-#define SDR0_PFC1_USBBIGEN 0x00000010
-#define SDR0_PFC1_GPT_FREQ 0x0000000f
-#endif
-
-/* General Purpose Timer (GPT) Register Offsets */
-#define GPT0_TBC 0x00000000
-#define GPT0_IM 0x00000018
-#define GPT0_ISS 0x0000001C
-#define GPT0_ISC 0x00000020
-#define GPT0_IE 0x00000024
-#define GPT0_COMP0 0x00000080
-#define GPT0_COMP1 0x00000084
-#define GPT0_COMP2 0x00000088
-#define GPT0_COMP3 0x0000008C
-#define GPT0_COMP4 0x00000090
-#define GPT0_COMP5 0x00000094
-#define GPT0_COMP6 0x00000098
-#define GPT0_MASK0 0x000000C0
-#define GPT0_MASK1 0x000000C4
-#define GPT0_MASK2 0x000000C8
-#define GPT0_MASK3 0x000000CC
-#define GPT0_MASK4 0x000000D0
-#define GPT0_MASK5 0x000000D4
-#define GPT0_MASK6 0x000000D8
-#define GPT0_DCT0 0x00000110
-#define GPT0_DCIS 0x0000011C
-
-#endif /* __PPC405_H__ */
+/*----------------------------------------------------------------------------+ +| +| This source code has been made available to you by IBM on an AS-IS +| basis. Anyone receiving this source is licensed under IBM +| copyrights to use it in any way he or she deems fit, including +| copying it, modifying it, compiling it, and redistributing it either +| with or without modifications. No license under IBM patents or +| patent applications is to be implied by the copyright license. +| +| Any user of this software should understand that IBM cannot provide +| technical support for this software and will not be responsible for +| any consequences resulting from the use of this software. +| +| Any person who transfers this source code or any derivative work +| must include the IBM copyright notice, this paragraph, and the +| preceding two paragraphs in the transferred software. +| +| COPYRIGHT I B M CORPORATION 1999 +| LICENSED MATERIAL - PROGRAM PROPERTY OF I B M ++----------------------------------------------------------------------------*/ + +#ifndef __PPC405_H__ +#define __PPC405_H__ + +/* Define bits and masks for real-mode storage attribute control registers */ +#define PPC_128MB_SACR_BIT(addr) ((addr) >> 27) +#define PPC_128MB_SACR_VALUE(addr) PPC_REG_VAL(PPC_128MB_SACR_BIT(addr),1) + +/****************************************************************************** + * Special for PPC405GP + ******************************************************************************/ + +/****************************************************************************** + * DMA + ******************************************************************************/ +#define DMA_DCR_BASE 0x100 +#define dmacr0 (DMA_DCR_BASE+0x00) /* DMA channel control register 0 */ +#define dmact0 (DMA_DCR_BASE+0x01) /* DMA count register 0 */ +#define dmada0 (DMA_DCR_BASE+0x02) /* DMA destination address register 0 */ +#define dmasa0 (DMA_DCR_BASE+0x03) /* DMA source address register 0 */ +#define dmasb0 (DMA_DCR_BASE+0x04) /* DMA scatter/gather descriptor addr 0 */ +#define dmacr1 (DMA_DCR_BASE+0x08) /* DMA channel control register 1 */ +#define dmact1 (DMA_DCR_BASE+0x09) /* DMA count register 1 */ +#define dmada1 (DMA_DCR_BASE+0x0a) /* DMA destination address register 1 */ +#define dmasa1 (DMA_DCR_BASE+0x0b) /* DMA source address register 1 */ +#define dmasb1 (DMA_DCR_BASE+0x0c) /* DMA scatter/gather descriptor addr 1 */ +#define dmacr2 (DMA_DCR_BASE+0x10) /* DMA channel control register 2 */ +#define dmact2 (DMA_DCR_BASE+0x11) /* DMA count register 2 */ +#define dmada2 (DMA_DCR_BASE+0x12) /* DMA destination address register 2 */ +#define dmasa2 (DMA_DCR_BASE+0x13) /* DMA source address register 2 */ +#define dmasb2 (DMA_DCR_BASE+0x14) /* DMA scatter/gather descriptor addr 2 */ +#define dmacr3 (DMA_DCR_BASE+0x18) /* DMA channel control register 3 */ +#define dmact3 (DMA_DCR_BASE+0x19) /* DMA count register 3 */ +#define dmada3 (DMA_DCR_BASE+0x1a) /* DMA destination address register 3 */ +#define dmasa3 (DMA_DCR_BASE+0x1b) /* DMA source address register 3 */ +#define dmasb3 (DMA_DCR_BASE+0x1c) /* DMA scatter/gather descriptor addr 3 */ +#define dmasr (DMA_DCR_BASE+0x20) /* DMA status register */ +#define dmasgc (DMA_DCR_BASE+0x23) /* DMA scatter/gather command register */ +#define dmaadr (DMA_DCR_BASE+0x24) /* DMA address decode register */ + +#ifndef CONFIG_405EP +/****************************************************************************** + * Decompression Controller + ******************************************************************************/ +#define DECOMP_DCR_BASE 0x14 +#define kiar (DECOMP_DCR_BASE+0x0) /* Decompression controller addr reg */ +#define kidr (DECOMP_DCR_BASE+0x1) /* Decompression controller data reg */ + /* values for kiar register - indirect addressing of these regs */ + #define kitor0 0x00 /* index table origin register 0 */ + #define kitor1 0x01 /* index table origin register 1 */ + #define kitor2 0x02 /* index table origin register 2 */ + #define kitor3 0x03 /* index table origin register 3 */ + #define kaddr0 0x04 /* address decode definition regsiter 0 */ + #define kaddr1 0x05 /* address decode definition regsiter 1 */ + #define kconf 0x40 /* decompression core config register */ + #define kid 0x41 /* decompression core ID register */ + #define kver 0x42 /* decompression core version # reg */ + #define kpear 0x50 /* bus error addr reg (PLB addr) */ + #define kbear 0x51 /* bus error addr reg (DCP to EBIU addr)*/ + #define kesr0 0x52 /* bus error status reg 0 (R/clear) */ + #define kesr0s 0x53 /* bus error status reg 0 (set) */ + /* There are 0x400 of the following registers, from krom0 to krom3ff*/ + /* Only the first one is given here. */ + #define krom0 0x400 /* SRAM/ROM read/write */ +#endif + +/****************************************************************************** + * Power Management + ******************************************************************************/ +#ifdef CONFIG_405EX +#define POWERMAN_DCR_BASE 0xb0 +#else +#define POWERMAN_DCR_BASE 0xb8 +#endif +#define cpmsr (POWERMAN_DCR_BASE+0x0) /* Power management status */ +#define cpmer (POWERMAN_DCR_BASE+0x1) /* Power management enable */ +#define cpmfr (POWERMAN_DCR_BASE+0x2) /* Power management force */ + +/****************************************************************************** + * Extrnal Bus Controller + ******************************************************************************/ + /* values for ebccfga register - indirect addressing of these regs */ + #define pb0cr 0x00 /* periph bank 0 config reg */ + #define pb1cr 0x01 /* periph bank 1 config reg */ + #define pb2cr 0x02 /* periph bank 2 config reg */ + #define pb3cr 0x03 /* periph bank 3 config reg */ + #define pb4cr 0x04 /* periph bank 4 config reg */ +#ifndef CONFIG_405EP + #define pb5cr 0x05 /* periph bank 5 config reg */ + #define pb6cr 0x06 /* periph bank 6 config reg */ + #define pb7cr 0x07 /* periph bank 7 config reg */ +#endif + #define pb0ap 0x10 /* periph bank 0 access parameters */ + #define pb1ap 0x11 /* periph bank 1 access parameters */ + #define pb2ap 0x12 /* periph bank 2 access parameters */ + #define pb3ap 0x13 /* periph bank 3 access parameters */ + #define pb4ap 0x14 /* periph bank 4 access parameters */ +#ifndef CONFIG_405EP + #define pb5ap 0x15 /* periph bank 5 access parameters */ + #define pb6ap 0x16 /* periph bank 6 access parameters */ + #define pb7ap 0x17 /* periph bank 7 access parameters */ +#endif + #define pbear 0x20 /* periph bus error addr reg */ + #define pbesr0 0x21 /* periph bus error status reg 0 */ + #define pbesr1 0x22 /* periph bus error status reg 1 */ + #define epcr 0x23 /* external periph control reg */ +#define EBC0_CFG 0x23 /* external bus configuration reg */ + +#ifdef CONFIG_405EP +/****************************************************************************** + * Control + ******************************************************************************/ +#define CNTRL_DCR_BASE 0x0f0 +#define cpc0_pllmr0 (CNTRL_DCR_BASE+0x0) /* PLL mode register 0 */ +#define cpc0_boot (CNTRL_DCR_BASE+0x1) /* Clock status register */ +#define cpc0_epctl (CNTRL_DCR_BASE+0x3) /* EMAC to PHY control register */ +#define cpc0_pllmr1 (CNTRL_DCR_BASE+0x4) /* PLL mode register 1 */ +#define cpc0_ucr (CNTRL_DCR_BASE+0x5) /* UART control register */ +#define cpc0_pci (CNTRL_DCR_BASE+0x9) /* PCI control register */ + +#define CPC0_PLLMR0 (CNTRL_DCR_BASE+0x0) /* PLL mode 0 register */ +#define CPC0_BOOT (CNTRL_DCR_BASE+0x1) /* Chip Clock Status register */ +#define CPC0_CR1 (CNTRL_DCR_BASE+0x2) /* Chip Control 1 register */ +#define CPC0_EPRCSR (CNTRL_DCR_BASE+0x3) /* EMAC PHY Rcv Clk Src register*/ +#define CPC0_PLLMR1 (CNTRL_DCR_BASE+0x4) /* PLL mode 1 register */ +#define CPC0_UCR (CNTRL_DCR_BASE+0x5) /* UART Control register */ +#define CPC0_SRR (CNTRL_DCR_BASE+0x6) /* Soft Reset register */ +#define CPC0_JTAGID (CNTRL_DCR_BASE+0x7) /* JTAG ID register */ +#define CPC0_SPARE (CNTRL_DCR_BASE+0x8) /* Spare DCR */ +#define CPC0_PCI (CNTRL_DCR_BASE+0x9) /* PCI Control register */ + +/* Bit definitions */ +#define PLLMR0_CPU_DIV_MASK 0x00300000 /* CPU clock divider */ +#define PLLMR0_CPU_DIV_BYPASS 0x00000000 +#define PLLMR0_CPU_DIV_2 0x00100000 +#define PLLMR0_CPU_DIV_3 0x00200000 +#define PLLMR0_CPU_DIV_4 0x00300000 + +#define PLLMR0_CPU_TO_PLB_MASK 0x00030000 /* CPU:PLB Frequency Divisor */ +#define PLLMR0_CPU_PLB_DIV_1 0x00000000 +#define PLLMR0_CPU_PLB_DIV_2 0x00010000 +#define PLLMR0_CPU_PLB_DIV_3 0x00020000 +#define PLLMR0_CPU_PLB_DIV_4 0x00030000 + +#define PLLMR0_OPB_TO_PLB_MASK 0x00003000 /* OPB:PLB Frequency Divisor */ +#define PLLMR0_OPB_PLB_DIV_1 0x00000000 +#define PLLMR0_OPB_PLB_DIV_2 0x00001000 +#define PLLMR0_OPB_PLB_DIV_3 0x00002000 +#define PLLMR0_OPB_PLB_DIV_4 0x00003000 + +#define PLLMR0_EXB_TO_PLB_MASK 0x00000300 /* External Bus:PLB Divisor */ +#define PLLMR0_EXB_PLB_DIV_2 0x00000000 +#define PLLMR0_EXB_PLB_DIV_3 0x00000100 +#define PLLMR0_EXB_PLB_DIV_4 0x00000200 +#define PLLMR0_EXB_PLB_DIV_5 0x00000300 + +#define PLLMR0_MAL_TO_PLB_MASK 0x00000030 /* MAL:PLB Divisor */ +#define PLLMR0_MAL_PLB_DIV_1 0x00000000 +#define PLLMR0_MAL_PLB_DIV_2 0x00000010 +#define PLLMR0_MAL_PLB_DIV_3 0x00000020 +#define PLLMR0_MAL_PLB_DIV_4 0x00000030 + +#define PLLMR0_PCI_TO_PLB_MASK 0x00000003 /* PCI:PLB Frequency Divisor */ +#define PLLMR0_PCI_PLB_DIV_1 0x00000000 +#define PLLMR0_PCI_PLB_DIV_2 0x00000001 +#define PLLMR0_PCI_PLB_DIV_3 0x00000002 +#define PLLMR0_PCI_PLB_DIV_4 0x00000003 + +#define PLLMR1_SSCS_MASK 0x80000000 /* Select system clock source */ +#define PLLMR1_PLLR_MASK 0x40000000 /* PLL reset */ +#define PLLMR1_FBMUL_MASK 0x00F00000 /* PLL feedback multiplier value */ +#define PLLMR1_FBMUL_DIV_16 0x00000000 +#define PLLMR1_FBMUL_DIV_1 0x00100000 +#define PLLMR1_FBMUL_DIV_2 0x00200000 +#define PLLMR1_FBMUL_DIV_3 0x00300000 +#define PLLMR1_FBMUL_DIV_4 0x00400000 +#define PLLMR1_FBMUL_DIV_5 0x00500000 +#define PLLMR1_FBMUL_DIV_6 0x00600000 +#define PLLMR1_FBMUL_DIV_7 0x00700000 +#define PLLMR1_FBMUL_DIV_8 0x00800000 +#define PLLMR1_FBMUL_DIV_9 0x00900000 +#define PLLMR1_FBMUL_DIV_10 0x00A00000 +#define PLLMR1_FBMUL_DIV_11 0x00B00000 +#define PLLMR1_FBMUL_DIV_12 0x00C00000 +#define PLLMR1_FBMUL_DIV_13 0x00D00000 +#define PLLMR1_FBMUL_DIV_14 0x00E00000 +#define PLLMR1_FBMUL_DIV_15 0x00F00000 + +#define PLLMR1_FWDVA_MASK 0x00070000 /* PLL forward divider A value */ +#define PLLMR1_FWDVA_DIV_8 0x00000000 +#define PLLMR1_FWDVA_DIV_7 0x00010000 +#define PLLMR1_FWDVA_DIV_6 0x00020000 +#define PLLMR1_FWDVA_DIV_5 0x00030000 +#define PLLMR1_FWDVA_DIV_4 0x00040000 +#define PLLMR1_FWDVA_DIV_3 0x00050000 +#define PLLMR1_FWDVA_DIV_2 0x00060000 +#define PLLMR1_FWDVA_DIV_1 0x00070000 +#define PLLMR1_FWDVB_MASK 0x00007000 /* PLL forward divider B value */ +#define PLLMR1_TUNING_MASK 0x000003FF /* PLL tune bits */ + +/* Defines for CPC0_EPRCSR register */ +#define CPC0_EPRCSR_E0NFE 0x80000000 +#define CPC0_EPRCSR_E1NFE 0x40000000 +#define CPC0_EPRCSR_E1RPP 0x00000080 +#define CPC0_EPRCSR_E0RPP 0x00000040 +#define CPC0_EPRCSR_E1ERP 0x00000020 +#define CPC0_EPRCSR_E0ERP 0x00000010 +#define CPC0_EPRCSR_E1PCI 0x00000002 +#define CPC0_EPRCSR_E0PCI 0x00000001 + +/* Defines for CPC0_PCI Register */ +#define CPC0_PCI_SPE 0x00000010 /* PCIINT/WE select */ +#define CPC0_PCI_HOST_CFG_EN 0x00000008 /* PCI host config Enable */ +#define CPC0_PCI_ARBIT_EN 0x00000001 /* PCI Internal Arb Enabled*/ + +/* Defines for CPC0_BOOR Register */ +#define CPC0_BOOT_SEP 0x00000002 /* serial EEPROM present */ + +/* Defines for CPC0_PLLMR1 Register fields */ +#define PLL_ACTIVE 0x80000000 +#define CPC0_PLLMR1_SSCS 0x80000000 +#define PLL_RESET 0x40000000 +#define CPC0_PLLMR1_PLLR 0x40000000 + /* Feedback multiplier */ +#define PLL_FBKDIV 0x00F00000 +#define CPC0_PLLMR1_FBDV 0x00F00000 +#define PLL_FBKDIV_16 0x00000000 +#define PLL_FBKDIV_1 0x00100000 +#define PLL_FBKDIV_2 0x00200000 +#define PLL_FBKDIV_3 0x00300000 +#define PLL_FBKDIV_4 0x00400000 +#define PLL_FBKDIV_5 0x00500000 +#define PLL_FBKDIV_6 0x00600000 +#define PLL_FBKDIV_7 0x00700000 +#define PLL_FBKDIV_8 0x00800000 +#define PLL_FBKDIV_9 0x00900000 +#define PLL_FBKDIV_10 0x00A00000 +#define PLL_FBKDIV_11 0x00B00000 +#define PLL_FBKDIV_12 0x00C00000 +#define PLL_FBKDIV_13 0x00D00000 +#define PLL_FBKDIV_14 0x00E00000 +#define PLL_FBKDIV_15 0x00F00000 + /* Forward A divisor */ +#define PLL_FWDDIVA 0x00070000 +#define CPC0_PLLMR1_FWDVA 0x00070000 +#define PLL_FWDDIVA_8 0x00000000 +#define PLL_FWDDIVA_7 0x00010000 +#define PLL_FWDDIVA_6 0x00020000 +#define PLL_FWDDIVA_5 0x00030000 +#define PLL_FWDDIVA_4 0x00040000 +#define PLL_FWDDIVA_3 0x00050000 +#define PLL_FWDDIVA_2 0x00060000 +#define PLL_FWDDIVA_1 0x00070000 + /* Forward B divisor */ +#define PLL_FWDDIVB 0x00007000 +#define CPC0_PLLMR1_FWDVB 0x00007000 +#define PLL_FWDDIVB_8 0x00000000 +#define PLL_FWDDIVB_7 0x00001000 +#define PLL_FWDDIVB_6 0x00002000 +#define PLL_FWDDIVB_5 0x00003000 +#define PLL_FWDDIVB_4 0x00004000 +#define PLL_FWDDIVB_3 0x00005000 +#define PLL_FWDDIVB_2 0x00006000 +#define PLL_FWDDIVB_1 0x00007000 + /* PLL tune bits */ +#define PLL_TUNE_MASK 0x000003FF +#define PLL_TUNE_2_M_3 0x00000133 /* 2 <= M <= 3 */ +#define PLL_TUNE_4_M_6 0x00000134 /* 3 < M <= 6 */ +#define PLL_TUNE_7_M_10 0x00000138 /* 6 < M <= 10 */ +#define PLL_TUNE_11_M_14 0x0000013C /* 10 < M <= 14 */ +#define PLL_TUNE_15_M_40 0x0000023E /* 14 < M <= 40 */ +#define PLL_TUNE_VCO_LOW 0x00000000 /* 500MHz <= VCO <= 800MHz */ +#define PLL_TUNE_VCO_HI 0x00000080 /* 800MHz < VCO <= 1000MHz */ + +/* Defines for CPC0_PLLMR0 Register fields */ + /* CPU divisor */ +#define PLL_CPUDIV 0x00300000 +#define CPC0_PLLMR0_CCDV 0x00300000 +#define PLL_CPUDIV_1 0x00000000 +#define PLL_CPUDIV_2 0x00100000 +#define PLL_CPUDIV_3 0x00200000 +#define PLL_CPUDIV_4 0x00300000 + /* PLB divisor */ +#define PLL_PLBDIV 0x00030000 +#define CPC0_PLLMR0_CBDV 0x00030000 +#define PLL_PLBDIV_1 0x00000000 +#define PLL_PLBDIV_2 0x00010000 +#define PLL_PLBDIV_3 0x00020000 +#define PLL_PLBDIV_4 0x00030000 + /* OPB divisor */ +#define PLL_OPBDIV 0x00003000 +#define CPC0_PLLMR0_OPDV 0x00003000 +#define PLL_OPBDIV_1 0x00000000 +#define PLL_OPBDIV_2 0x00001000 +#define PLL_OPBDIV_3 0x00002000 +#define PLL_OPBDIV_4 0x00003000 + /* EBC divisor */ +#define PLL_EXTBUSDIV 0x00000300 +#define CPC0_PLLMR0_EPDV 0x00000300 +#define PLL_EXTBUSDIV_2 0x00000000 +#define PLL_EXTBUSDIV_3 0x00000100 +#define PLL_EXTBUSDIV_4 0x00000200 +#define PLL_EXTBUSDIV_5 0x00000300 + /* MAL divisor */ +#define PLL_MALDIV 0x00000030 +#define CPC0_PLLMR0_MPDV 0x00000030 +#define PLL_MALDIV_1 0x00000000 +#define PLL_MALDIV_2 0x00000010 +#define PLL_MALDIV_3 0x00000020 +#define PLL_MALDIV_4 0x00000030 + /* PCI divisor */ +#define PLL_PCIDIV 0x00000003 +#define CPC0_PLLMR0_PPFD 0x00000003 +#define PLL_PCIDIV_1 0x00000000 +#define PLL_PCIDIV_2 0x00000001 +#define PLL_PCIDIV_3 0x00000002 +#define PLL_PCIDIV_4 0x00000003 + +/* + *------------------------------------------------------------------------------- + * PLL settings for 266MHz CPU, 133MHz PLB/SDRAM, 66MHz EBC, 33MHz PCI, + * assuming a 33.3MHz input clock to the 405EP. + *------------------------------------------------------------------------------- + */ +#define PLLMR0_266_133_66 (PLL_CPUDIV_1 | PLL_PLBDIV_2 | \ + PLL_OPBDIV_2 | PLL_EXTBUSDIV_2 | \ + PLL_MALDIV_1 | PLL_PCIDIV_4) +#define PLLMR1_266_133_66 (PLL_FBKDIV_8 | \ + PLL_FWDDIVA_3 | PLL_FWDDIVB_3 | \ + PLL_TUNE_15_M_40 | PLL_TUNE_VCO_LOW) + +#define PLLMR0_133_66_66_33 (PLL_CPUDIV_1 | PLL_PLBDIV_1 | \ + PLL_OPBDIV_2 | PLL_EXTBUSDIV_4 | \ + PLL_MALDIV_1 | PLL_PCIDIV_4) +#define PLLMR1_133_66_66_33 (PLL_FBKDIV_4 | \ + PLL_FWDDIVA_6 | PLL_FWDDIVB_6 | \ + PLL_TUNE_15_M_40 | PLL_TUNE_VCO_LOW) +#define PLLMR0_200_100_50_33 (PLL_CPUDIV_1 | PLL_PLBDIV_2 | \ + PLL_OPBDIV_2 | PLL_EXTBUSDIV_3 | \ + PLL_MALDIV_1 | PLL_PCIDIV_4) +#define PLLMR1_200_100_50_33 (PLL_FBKDIV_6 | \ + PLL_FWDDIVA_4 | PLL_FWDDIVB_4 | \ + PLL_TUNE_15_M_40 | PLL_TUNE_VCO_LOW) +#define PLLMR0_266_133_66_33 (PLL_CPUDIV_1 | PLL_PLBDIV_2 | \ + PLL_OPBDIV_2 | PLL_EXTBUSDIV_4 | \ + PLL_MALDIV_1 | PLL_PCIDIV_4) +#define PLLMR1_266_133_66_33 (PLL_FBKDIV_8 | \ + PLL_FWDDIVA_3 | PLL_FWDDIVB_3 | \ + PLL_TUNE_15_M_40 | PLL_TUNE_VCO_LOW) +#define PLLMR0_266_66_33_33 (PLL_CPUDIV_1 | PLL_PLBDIV_4 | \ + PLL_OPBDIV_2 | PLL_EXTBUSDIV_2 | \ + PLL_MALDIV_1 | PLL_PCIDIV_2) +#define PLLMR1_266_66_33_33 (PLL_FBKDIV_8 | \ + PLL_FWDDIVA_3 | PLL_FWDDIVB_3 | \ + PLL_TUNE_15_M_40 | PLL_TUNE_VCO_LOW) +#define PLLMR0_333_111_55_37 (PLL_CPUDIV_1 | PLL_PLBDIV_3 | \ + PLL_OPBDIV_2 | PLL_EXTBUSDIV_2 | \ + PLL_MALDIV_1 | PLL_PCIDIV_3) +#define PLLMR1_333_111_55_37 (PLL_FBKDIV_10 | \ + PLL_FWDDIVA_3 | PLL_FWDDIVB_3 | \ + PLL_TUNE_15_M_40 | PLL_TUNE_VCO_HI) +#define PLLMR0_333_111_55_111 (PLL_CPUDIV_1 | PLL_PLBDIV_3 | \ + PLL_OPBDIV_2 | PLL_EXTBUSDIV_2 | \ + PLL_MALDIV_1 | PLL_PCIDIV_1) +#define PLLMR1_333_111_55_111 (PLL_FBKDIV_10 | \ + PLL_FWDDIVA_3 | PLL_FWDDIVB_3 | \ + PLL_TUNE_15_M_40 | PLL_TUNE_VCO_HI) + +/* + * PLL Voltage Controlled Oscillator (VCO) definitions + * Maximum and minimum values (in MHz) for correct PLL operation. + */ +#define VCO_MIN 500 +#define VCO_MAX 1000 +#elif defined(CONFIG_405EZ) +#define sdrnand0 0x4000 +#define sdrultra0 0x4040 +#define sdrultra1 0x4050 +#define sdricintstat 0x4510 + +#define SDR_NAND0_NDEN 0x80000000 +#define SDR_NAND0_NDBTEN 0x40000000 +#define SDR_NAND0_NDBADR_MASK 0x30000000 +#define SDR_NAND0_NDBPG_MASK 0x0f000000 +#define SDR_NAND0_NDAREN 0x00800000 +#define SDR_NAND0_NDRBEN 0x00400000 + +#define SDR_ULTRA0_NDGPIOBP 0x80000000 +#define SDR_ULTRA0_CSN_MASK 0x78000000 +#define SDR_ULTRA0_CSNSEL0 0x40000000 +#define SDR_ULTRA0_CSNSEL1 0x20000000 +#define SDR_ULTRA0_CSNSEL2 0x10000000 +#define SDR_ULTRA0_CSNSEL3 0x08000000 +#define SDR_ULTRA0_EBCRDYEN 0x04000000 +#define SDR_ULTRA0_SPISSINEN 0x02000000 +#define SDR_ULTRA0_NFSRSTEN 0x01000000 + +#define SDR_ULTRA1_LEDNENABLE 0x40000000 + +#define SDR_ICRX_STAT 0x80000000 +#define SDR_ICTX0_STAT 0x40000000 +#define SDR_ICTX1_STAT 0x20000000 + +#define SDR_PINSTP 0x40 + +/****************************************************************************** + * Control + ******************************************************************************/ +/* CPR Registers */ +#define cprclkupd 0x020 /* CPR_CLKUPD */ +#define cprpllc 0x040 /* CPR_PLLC */ +#define cprplld 0x060 /* CPR_PLLD */ +#define cprprimad 0x080 /* CPR_PRIMAD */ +#define cprperd0 0x0e0 /* CPR_PERD0 */ +#define cprperd1 0x0e1 /* CPR_PERD1 */ +#define cprperc0 0x180 /* CPR_PERC0 */ +#define cprmisc0 0x181 /* CPR_MISC0 */ +#define cprmisc1 0x182 /* CPR_MISC1 */ + +#define CPR_CLKUPD_ENPLLCH_EN 0x40000000 /* Enable CPR PLL Changes */ +#define CPR_CLKUPD_ENDVCH_EN 0x20000000 /* Enable CPR Sys. Div. Changes */ +#define CPR_PERD0_SPIDV_MASK 0x000F0000 /* SPI Clock Divider */ + +#define PLLC_SRC_MASK 0x20000000 /* PLL feedback source */ + +#define PLLD_FBDV_MASK 0x1F000000 /* PLL feedback divider value */ +#define PLLD_FWDVA_MASK 0x000F0000 /* PLL forward divider A value */ +#define PLLD_FWDVB_MASK 0x00000700 /* PLL forward divider B value */ + +#define PRIMAD_CPUDV_MASK 0x0F000000 /* CPU Clock Divisor Mask */ +#define PRIMAD_PLBDV_MASK 0x000F0000 /* PLB Clock Divisor Mask */ +#define PRIMAD_OPBDV_MASK 0x00000F00 /* OPB Clock Divisor Mask */ +#define PRIMAD_EBCDV_MASK 0x0000000F /* EBC Clock Divisor Mask */ + +#define PERD0_PWMDV_MASK 0xFF000000 /* PWM Divider Mask */ +#define PERD0_SPIDV_MASK 0x000F0000 /* SPI Divider Mask */ +#define PERD0_U0DV_MASK 0x0000FF00 /* UART 0 Divider Mask */ +#define PERD0_U1DV_MASK 0x000000FF /* UART 1 Divider Mask */ + +#else /* #ifdef CONFIG_405EP */ +/****************************************************************************** + * Control + ******************************************************************************/ +#define CNTRL_DCR_BASE 0x0b0 +#define pllmd (CNTRL_DCR_BASE+0x0) /* PLL mode register */ +#define cntrl0 (CNTRL_DCR_BASE+0x1) /* Control 0 register */ +#define cntrl1 (CNTRL_DCR_BASE+0x2) /* Control 1 register */ +#define reset (CNTRL_DCR_BASE+0x3) /* reset register */ +#define strap (CNTRL_DCR_BASE+0x4) /* strap register */ + +#define CPC0_CR0 (CNTRL_DCR_BASE+0x1) /* chip control register 0 */ +#define CPC0_CR1 (CNTRL_DCR_BASE+0x2) /* chip control register 1 */ +#define CPC0_PSR (CNTRL_DCR_BASE+0x4) /* chip pin strapping register */ + +/* CPC0_ECR/CPC0_EIRR: PPC405GPr only */ +#define CPC0_EIRR (CNTRL_DCR_BASE+0x6) /* external interrupt routing register */ +#define CPC0_ECR (0xaa) /* edge conditioner register */ + +#define ecr (0xaa) /* edge conditioner register (405gpr) */ + +/* Bit definitions */ +#define PLLMR_FWD_DIV_MASK 0xE0000000 /* Forward Divisor */ +#define PLLMR_FWD_DIV_BYPASS 0xE0000000 +#define PLLMR_FWD_DIV_3 0xA0000000 +#define PLLMR_FWD_DIV_4 0x80000000 +#define PLLMR_FWD_DIV_6 0x40000000 + +#define PLLMR_FB_DIV_MASK 0x1E000000 /* Feedback Divisor */ +#define PLLMR_FB_DIV_1 0x02000000 +#define PLLMR_FB_DIV_2 0x04000000 +#define PLLMR_FB_DIV_3 0x06000000 +#define PLLMR_FB_DIV_4 0x08000000 + +#define PLLMR_TUNING_MASK 0x01F80000 + +#define PLLMR_CPU_TO_PLB_MASK 0x00060000 /* CPU:PLB Frequency Divisor */ +#define PLLMR_CPU_PLB_DIV_1 0x00000000 +#define PLLMR_CPU_PLB_DIV_2 0x00020000 +#define PLLMR_CPU_PLB_DIV_3 0x00040000 +#define PLLMR_CPU_PLB_DIV_4 0x00060000 + +#define PLLMR_OPB_TO_PLB_MASK 0x00018000 /* OPB:PLB Frequency Divisor */ +#define PLLMR_OPB_PLB_DIV_1 0x00000000 +#define PLLMR_OPB_PLB_DIV_2 0x00008000 +#define PLLMR_OPB_PLB_DIV_3 0x00010000 +#define PLLMR_OPB_PLB_DIV_4 0x00018000 + +#define PLLMR_PCI_TO_PLB_MASK 0x00006000 /* PCI:PLB Frequency Divisor */ +#define PLLMR_PCI_PLB_DIV_1 0x00000000 +#define PLLMR_PCI_PLB_DIV_2 0x00002000 +#define PLLMR_PCI_PLB_DIV_3 0x00004000 +#define PLLMR_PCI_PLB_DIV_4 0x00006000 + +#define PLLMR_EXB_TO_PLB_MASK 0x00001800 /* External Bus:PLB Divisor */ +#define PLLMR_EXB_PLB_DIV_2 0x00000000 +#define PLLMR_EXB_PLB_DIV_3 0x00000800 +#define PLLMR_EXB_PLB_DIV_4 0x00001000 +#define PLLMR_EXB_PLB_DIV_5 0x00001800 + +/* definitions for PPC405GPr (new mode strapping) */ +#define PLLMR_FWDB_DIV_MASK 0x00000007 /* Forward Divisor B */ + +#define PSR_PLL_FWD_MASK 0xC0000000 +#define PSR_PLL_FDBACK_MASK 0x30000000 +#define PSR_PLL_TUNING_MASK 0x0E000000 +#define PSR_PLB_CPU_MASK 0x01800000 +#define PSR_OPB_PLB_MASK 0x00600000 +#define PSR_PCI_PLB_MASK 0x00180000 +#define PSR_EB_PLB_MASK 0x00060000 +#define PSR_ROM_WIDTH_MASK 0x00018000 +#define PSR_ROM_LOC 0x00004000 +#define PSR_PCI_ASYNC_EN 0x00001000 +#define PSR_PERCLK_SYNC_MODE_EN 0x00000800 /* PPC405GPr only */ +#define PSR_PCI_ARBIT_EN 0x00000400 +#define PSR_NEW_MODE_EN 0x00000020 /* PPC405GPr only */ + +#ifndef CONFIG_IOP480 +/* + * PLL Voltage Controlled Oscillator (VCO) definitions + * Maximum and minimum values (in MHz) for correct PLL operation. + */ +#define VCO_MIN 400 +#define VCO_MAX 800 +#endif /* #ifndef CONFIG_IOP480 */ +#endif /* #ifdef CONFIG_405EP */ + +/****************************************************************************** + * Memory Access Layer + ******************************************************************************/ +#if defined(CONFIG_405EZ) +#define MAL_DCR_BASE 0x380 +#define malmcr (MAL_DCR_BASE+0x00) /* MAL Config reg */ +#define malesr (MAL_DCR_BASE+0x01) /* Err Status reg (Read/Clear)*/ +#define malier (MAL_DCR_BASE+0x02) /* Interrupt enable reg */ +#define maldbr (MAL_DCR_BASE+0x03) /* Mal Debug reg (Read only) */ +#define maltxcasr (MAL_DCR_BASE+0x04) /* TX Channel active reg (set)*/ +#define maltxcarr (MAL_DCR_BASE+0x05) /* TX Channel active reg (Reset) */ +#define maltxeobisr (MAL_DCR_BASE+0x06) /* TX End of buffer int status reg */ +#define maltxdeir (MAL_DCR_BASE+0x07) /* TX Descr. Error Int reg */ +/* 0x08-0x0F Reserved */ +#define malrxcasr (MAL_DCR_BASE+0x10) /* RX Channel active reg (set)*/ +#define malrxcarr (MAL_DCR_BASE+0x11) /* RX Channel active reg (Reset) */ +#define malrxeobisr (MAL_DCR_BASE+0x12) /* RX End of buffer int status reg */ +#define malrxdeir (MAL_DCR_BASE+0x13) /* RX Descr. Error Int reg */ +/* 0x14-0x1F Reserved */ +#define maltxctp0r (MAL_DCR_BASE+0x20) /* TX 0 Channel table ptr reg */ +#define maltxctp1r (MAL_DCR_BASE+0x21) /* TX 1 Channel table ptr reg */ +#define maltxctp2r (MAL_DCR_BASE+0x22) /* TX 2 Channel table ptr reg */ +#define maltxctp3r (MAL_DCR_BASE+0x23) /* TX 3 Channel table ptr reg */ +#define maltxctp4r (MAL_DCR_BASE+0x24) /* TX 4 Channel table ptr reg */ +#define maltxctp5r (MAL_DCR_BASE+0x25) /* TX 5 Channel table ptr reg */ +#define maltxctp6r (MAL_DCR_BASE+0x26) /* TX 6 Channel table ptr reg */ +#define maltxctp7r (MAL_DCR_BASE+0x27) /* TX 7 Channel table ptr reg */ +#define maltxctp8r (MAL_DCR_BASE+0x28) /* TX 8 Channel table ptr reg */ +#define maltxctp9r (MAL_DCR_BASE+0x29) /* TX 9 Channel table ptr reg */ +#define maltxctp10r (MAL_DCR_BASE+0x2A) /* TX 10 Channel table ptr reg */ +#define maltxctp11r (MAL_DCR_BASE+0x2B) /* TX 11 Channel table ptr reg */ +#define maltxctp12r (MAL_DCR_BASE+0x2C) /* TX 12 Channel table ptr reg */ +#define maltxctp13r (MAL_DCR_BASE+0x2D) /* TX 13 Channel table ptr reg */ +#define maltxctp14r (MAL_DCR_BASE+0x2E) /* TX 14 Channel table ptr reg */ +#define maltxctp15r (MAL_DCR_BASE+0x2F) /* TX 15 Channel table ptr reg */ +#define maltxctp16r (MAL_DCR_BASE+0x30) /* TX 16 Channel table ptr reg */ +#define maltxctp17r (MAL_DCR_BASE+0x31) /* TX 17 Channel table ptr reg */ +#define maltxctp18r (MAL_DCR_BASE+0x32) /* TX 18 Channel table ptr reg */ +#define maltxctp19r (MAL_DCR_BASE+0x33) /* TX 19 Channel table ptr reg */ +#define maltxctp20r (MAL_DCR_BASE+0x34) /* TX 20 Channel table ptr reg */ +#define maltxctp21r (MAL_DCR_BASE+0x35) /* TX 21 Channel table ptr reg */ +#define maltxctp22r (MAL_DCR_BASE+0x36) /* TX 22 Channel table ptr reg */ +#define maltxctp23r (MAL_DCR_BASE+0x37) /* TX 23 Channel table ptr reg */ +#define maltxctp24r (MAL_DCR_BASE+0x38) /* TX 24 Channel table ptr reg */ +#define maltxctp25r (MAL_DCR_BASE+0x39) /* TX 25 Channel table ptr reg */ +#define maltxctp26r (MAL_DCR_BASE+0x3A) /* TX 26 Channel table ptr reg */ +#define maltxctp27r (MAL_DCR_BASE+0x3B) /* TX 27 Channel table ptr reg */ +#define maltxctp28r (MAL_DCR_BASE+0x3C) /* TX 28 Channel table ptr reg */ +#define maltxctp29r (MAL_DCR_BASE+0x3D) /* TX 29 Channel table ptr reg */ +#define maltxctp30r (MAL_DCR_BASE+0x3E) /* TX 30 Channel table ptr reg */ +#define maltxctp31r (MAL_DCR_BASE+0x3F) /* TX 31 Channel table ptr reg */ +#define malrxctp0r (MAL_DCR_BASE+0x40) /* RX 0 Channel table ptr reg */ +#define malrxctp1r (MAL_DCR_BASE+0x41) /* RX 1 Channel table ptr reg */ +#define malrxctp2r (MAL_DCR_BASE+0x42) /* RX 2 Channel table ptr reg */ +#define malrxctp3r (MAL_DCR_BASE+0x43) /* RX 3 Channel table ptr reg */ +#define malrxctp4r (MAL_DCR_BASE+0x44) /* RX 4 Channel table ptr reg */ +#define malrxctp5r (MAL_DCR_BASE+0x45) /* RX 5 Channel table ptr reg */ +#define malrxctp6r (MAL_DCR_BASE+0x46) /* RX 6 Channel table ptr reg */ +#define malrxctp7r (MAL_DCR_BASE+0x47) /* RX 7 Channel table ptr reg */ +#define malrxctp8r (MAL_DCR_BASE+0x48) /* RX 8 Channel table ptr reg */ +#define malrxctp9r (MAL_DCR_BASE+0x49) /* RX 9 Channel table ptr reg */ +#define malrxctp10r (MAL_DCR_BASE+0x4A) /* RX 10 Channel table ptr reg */ +#define malrxctp11r (MAL_DCR_BASE+0x4B) /* RX 11 Channel table ptr reg */ +#define malrxctp12r (MAL_DCR_BASE+0x4C) /* RX 12 Channel table ptr reg */ +#define malrxctp13r (MAL_DCR_BASE+0x4D) /* RX 13 Channel table ptr reg */ +#define malrxctp14r (MAL_DCR_BASE+0x4E) /* RX 14 Channel table ptr reg */ +#define malrxctp15r (MAL_DCR_BASE+0x4F) /* RX 15 Channel table ptr reg */ +#define malrxctp16r (MAL_DCR_BASE+0x50) /* RX 16 Channel table ptr reg */ +#define malrxctp17r (MAL_DCR_BASE+0x51) /* RX 17 Channel table ptr reg */ +#define malrxctp18r (MAL_DCR_BASE+0x52) /* RX 18 Channel table ptr reg */ +#define malrxctp19r (MAL_DCR_BASE+0x53) /* RX 19 Channel table ptr reg */ +#define malrxctp20r (MAL_DCR_BASE+0x54) /* RX 20 Channel table ptr reg */ +#define malrxctp21r (MAL_DCR_BASE+0x55) /* RX 21 Channel table ptr reg */ +#define malrxctp22r (MAL_DCR_BASE+0x56) /* RX 22 Channel table ptr reg */ +#define malrxctp23r (MAL_DCR_BASE+0x57) /* RX 23 Channel table ptr reg */ +#define malrxctp24r (MAL_DCR_BASE+0x58) /* RX 24 Channel table ptr reg */ +#define malrxctp25r (MAL_DCR_BASE+0x59) /* RX 25 Channel table ptr reg */ +#define malrxctp26r (MAL_DCR_BASE+0x5A) /* RX 26 Channel table ptr reg */ +#define malrxctp27r (MAL_DCR_BASE+0x5B) /* RX 27 Channel table ptr reg */ +#define malrxctp28r (MAL_DCR_BASE+0x5C) /* RX 28 Channel table ptr reg */ +#define malrxctp29r (MAL_DCR_BASE+0x5D) /* RX 29 Channel table ptr reg */ +#define malrxctp30r (MAL_DCR_BASE+0x5E) /* RX 30 Channel table ptr reg */ +#define malrxctp31r (MAL_DCR_BASE+0x5F) /* RX 31 Channel table ptr reg */ +#define malrcbs0 (MAL_DCR_BASE+0x60) /* RX 0 Channel buffer size reg */ +#define malrcbs1 (MAL_DCR_BASE+0x61) /* RX 1 Channel buffer size reg */ +#define malrcbs2 (MAL_DCR_BASE+0x62) /* RX 2 Channel buffer size reg */ +#define malrcbs3 (MAL_DCR_BASE+0x63) /* RX 3 Channel buffer size reg */ +#define malrcbs4 (MAL_DCR_BASE+0x64) /* RX 4 Channel buffer size reg */ +#define malrcbs5 (MAL_DCR_BASE+0x65) /* RX 5 Channel buffer size reg */ +#define malrcbs6 (MAL_DCR_BASE+0x66) /* RX 6 Channel buffer size reg */ +#define malrcbs7 (MAL_DCR_BASE+0x67) /* RX 7 Channel buffer size reg */ +#define malrcbs8 (MAL_DCR_BASE+0x68) /* RX 8 Channel buffer size reg */ +#define malrcbs9 (MAL_DCR_BASE+0x69) /* RX 9 Channel buffer size reg */ +#define malrcbs10 (MAL_DCR_BASE+0x6A) /* RX 10 Channel buffer size reg */ +#define malrcbs11 (MAL_DCR_BASE+0x6B) /* RX 11 Channel buffer size reg */ +#define malrcbs12 (MAL_DCR_BASE+0x6C) /* RX 12 Channel buffer size reg */ +#define malrcbs13 (MAL_DCR_BASE+0x6D) /* RX 13 Channel buffer size reg */ +#define malrcbs14 (MAL_DCR_BASE+0x6E) /* RX 14 Channel buffer size reg */ +#define malrcbs15 (MAL_DCR_BASE+0x6F) /* RX 15 Channel buffer size reg */ +#define malrcbs16 (MAL_DCR_BASE+0x70) /* RX 16 Channel buffer size reg */ +#define malrcbs17 (MAL_DCR_BASE+0x71) /* RX 17 Channel buffer size reg */ +#define malrcbs18 (MAL_DCR_BASE+0x72) /* RX 18 Channel buffer size reg */ +#define malrcbs19 (MAL_DCR_BASE+0x73) /* RX 19 Channel buffer size reg */ +#define malrcbs20 (MAL_DCR_BASE+0x74) /* RX 20 Channel buffer size reg */ +#define malrcbs21 (MAL_DCR_BASE+0x75) /* RX 21 Channel buffer size reg */ +#define malrcbs22 (MAL_DCR_BASE+0x76) /* RX 22 Channel buffer size reg */ +#define malrcbs23 (MAL_DCR_BASE+0x77) /* RX 23 Channel buffer size reg */ +#define malrcbs24 (MAL_DCR_BASE+0x78) /* RX 24 Channel buffer size reg */ +#define malrcbs25 (MAL_DCR_BASE+0x79) /* RX 25 Channel buffer size reg */ +#define malrcbs26 (MAL_DCR_BASE+0x7A) /* RX 26 Channel buffer size reg */ +#define malrcbs27 (MAL_DCR_BASE+0x7B) /* RX 27 Channel buffer size reg */ +#define malrcbs28 (MAL_DCR_BASE+0x7C) /* RX 28 Channel buffer size reg */ +#define malrcbs29 (MAL_DCR_BASE+0x7D) /* RX 29 Channel buffer size reg */ +#define malrcbs30 (MAL_DCR_BASE+0x7E) /* RX 30 Channel buffer size reg */ +#define malrcbs31 (MAL_DCR_BASE+0x7F) /* RX 31 Channel buffer size reg */ + +#else /* !defined(CONFIG_405EZ) */ + +#define MAL_DCR_BASE 0x180 +#define malmcr (MAL_DCR_BASE+0x00) /* MAL Config reg */ +#define malesr (MAL_DCR_BASE+0x01) /* Error Status reg (Read/Clear) */ +#define malier (MAL_DCR_BASE+0x02) /* Interrupt enable reg */ +#define maldbr (MAL_DCR_BASE+0x03) /* Mal Debug reg (Read only) */ +#define maltxcasr (MAL_DCR_BASE+0x04) /* TX Channel active reg (set) */ +#define maltxcarr (MAL_DCR_BASE+0x05) /* TX Channel active reg (Reset) */ +#define maltxeobisr (MAL_DCR_BASE+0x06) /* TX End of buffer int status reg */ +#define maltxdeir (MAL_DCR_BASE+0x07) /* TX Descr. Error Int reg */ +#define malrxcasr (MAL_DCR_BASE+0x10) /* RX Channel active reg (set) */ +#define malrxcarr (MAL_DCR_BASE+0x11) /* RX Channel active reg (Reset) */ +#define malrxeobisr (MAL_DCR_BASE+0x12) /* RX End of buffer int status reg */ +#define malrxdeir (MAL_DCR_BASE+0x13) /* RX Descr. Error Int reg */ +#define maltxctp0r (MAL_DCR_BASE+0x20) /* TX 0 Channel table pointer reg */ +#define maltxctp1r (MAL_DCR_BASE+0x21) /* TX 1 Channel table pointer reg */ +#define maltxctp2r (MAL_DCR_BASE+0x22) /* TX 2 Channel table pointer reg */ +#define malrxctp0r (MAL_DCR_BASE+0x40) /* RX 0 Channel table pointer reg */ +#define malrxctp1r (MAL_DCR_BASE+0x41) /* RX 1 Channel table pointer reg */ +#define malrcbs0 (MAL_DCR_BASE+0x60) /* RX 0 Channel buffer size reg */ +#define malrcbs1 (MAL_DCR_BASE+0x61) /* RX 1 Channel buffer size reg */ +#endif /* defined(CONFIG_405EZ) */ + +/*----------------------------------------------------------------------------- +| IIC Register Offsets +'----------------------------------------------------------------------------*/ +#define IICMDBUF 0x00 +#define IICSDBUF 0x02 +#define IICLMADR 0x04 +#define IICHMADR 0x05 +#define IICCNTL 0x06 +#define IICMDCNTL 0x07 +#define IICSTS 0x08 +#define IICEXTSTS 0x09 +#define IICLSADR 0x0A +#define IICHSADR 0x0B +#define IICCLKDIV 0x0C +#define IICINTRMSK 0x0D +#define IICXFRCNT 0x0E +#define IICXTCNTLSS 0x0F +#define IICDIRECTCNTL 0x10 + +/*----------------------------------------------------------------------------- +| UART Register Offsets +'----------------------------------------------------------------------------*/ +#define DATA_REG 0x00 +#define DL_LSB 0x00 +#define DL_MSB 0x01 +#define INT_ENABLE 0x01 +#define FIFO_CONTROL 0x02 +#define LINE_CONTROL 0x03 +#define MODEM_CONTROL 0x04 +#define LINE_STATUS 0x05 +#define MODEM_STATUS 0x06 +#define SCRATCH 0x07 + +/****************************************************************************** + * On Chip Memory + ******************************************************************************/ +#if defined(CONFIG_405EZ) +#define OCM_DCR_BASE 0x020 +#define ocmplb3cr1 (OCM_DCR_BASE+0x00) /* OCM PLB3 Bank 1 Config Reg */ +#define ocmplb3cr2 (OCM_DCR_BASE+0x01) /* OCM PLB3 Bank 2 Config Reg */ +#define ocmplb3bear (OCM_DCR_BASE+0x02) /* OCM PLB3 Bus Error Add Reg */ +#define ocmplb3besr0 (OCM_DCR_BASE+0x03) /* OCM PLB3 Bus Error Stat Reg 0 */ +#define ocmplb3besr1 (OCM_DCR_BASE+0x04) /* OCM PLB3 Bus Error Stat Reg 1 */ +#define ocmcid (OCM_DCR_BASE+0x05) /* OCM Core ID */ +#define ocmrevid (OCM_DCR_BASE+0x06) /* OCM Revision ID */ +#define ocmplb3dpc (OCM_DCR_BASE+0x07) /* OCM PLB3 Data Parity Check */ +#define ocmdscr1 (OCM_DCR_BASE+0x08) /* OCM D-side Bank 1 Config Reg */ +#define ocmdscr2 (OCM_DCR_BASE+0x09) /* OCM D-side Bank 2 Config Reg */ +#define ocmiscr1 (OCM_DCR_BASE+0x0A) /* OCM I-side Bank 1 Config Reg */ +#define ocmiscr2 (OCM_DCR_BASE+0x0B) /* OCM I-side Bank 2 Config Reg */ +#define ocmdsisdpc (OCM_DCR_BASE+0x0C) /* OCM D-side/I-side Data Par Chk*/ +#define ocmdsisbear (OCM_DCR_BASE+0x0D) /* OCM D-side/I-side Bus Err Addr*/ +#define ocmdsisbesr (OCM_DCR_BASE+0x0E) /* OCM D-side/I-side Bus Err Stat*/ +#else +#define OCM_DCR_BASE 0x018 +#define ocmisarc (OCM_DCR_BASE+0x00) /* OCM I-side address compare reg */ +#define ocmiscntl (OCM_DCR_BASE+0x01) /* OCM I-side control reg */ +#define ocmdsarc (OCM_DCR_BASE+0x02) /* OCM D-side address compare reg */ +#define ocmdscntl (OCM_DCR_BASE+0x03) /* OCM D-side control reg */ +#endif /* CONFIG_405EZ */ + +/****************************************************************************** + * GPIO macro register defines + ******************************************************************************/ +#if defined(CONFIG_405EZ) +/* Only the 405EZ has 2 GPIOs */ +#define GPIO_BASE 0xEF600700 +#define GPIO0_OR (GPIO_BASE+0x0) +#define GPIO0_TCR (GPIO_BASE+0x4) +#define GPIO0_OSRL (GPIO_BASE+0x8) +#define GPIO0_OSRH (GPIO_BASE+0xC) +#define GPIO0_TSRL (GPIO_BASE+0x10) +#define GPIO0_TSRH (GPIO_BASE+0x14) +#define GPIO0_ODR (GPIO_BASE+0x18) +#define GPIO0_IR (GPIO_BASE+0x1C) +#define GPIO0_RR1 (GPIO_BASE+0x20) +#define GPIO0_RR2 (GPIO_BASE+0x24) +#define GPIO0_RR3 (GPIO_BASE+0x28) +#define GPIO0_ISR1L (GPIO_BASE+0x30) +#define GPIO0_ISR1H (GPIO_BASE+0x34) +#define GPIO0_ISR2L (GPIO_BASE+0x38) +#define GPIO0_ISR2H (GPIO_BASE+0x3C) +#define GPIO0_ISR3L (GPIO_BASE+0x40) +#define GPIO0_ISR3H (GPIO_BASE+0x44) + +#define GPIO1_BASE 0xEF600800 +#define GPIO1_OR (GPIO1_BASE+0x0) +#define GPIO1_TCR (GPIO1_BASE+0x4) +#define GPIO1_OSRL (GPIO1_BASE+0x8) +#define GPIO1_OSRH (GPIO1_BASE+0xC) +#define GPIO1_TSRL (GPIO1_BASE+0x10) +#define GPIO1_TSRH (GPIO1_BASE+0x14) +#define GPIO1_ODR (GPIO1_BASE+0x18) +#define GPIO1_IR (GPIO1_BASE+0x1C) +#define GPIO1_RR1 (GPIO1_BASE+0x20) +#define GPIO1_RR2 (GPIO1_BASE+0x24) +#define GPIO1_RR3 (GPIO1_BASE+0x28) +#define GPIO1_ISR1L (GPIO1_BASE+0x30) +#define GPIO1_ISR1H (GPIO1_BASE+0x34) +#define GPIO1_ISR2L (GPIO1_BASE+0x38) +#define GPIO1_ISR2H (GPIO1_BASE+0x3C) +#define GPIO1_ISR3L (GPIO1_BASE+0x40) +#define GPIO1_ISR3H (GPIO1_BASE+0x44) + +#elif defined(CONFIG_405EX) +#define GPIO_BASE 0xEF600800 +#define GPIO0_OR (GPIO_BASE+0x0) +#define GPIO0_TCR (GPIO_BASE+0x4) +#define GPIO0_OSRL (GPIO_BASE+0x8) +#define GPIO0_OSRH (GPIO_BASE+0xC) +#define GPIO0_TSRL (GPIO_BASE+0x10) +#define GPIO0_TSRH (GPIO_BASE+0x14) +#define GPIO0_ODR (GPIO_BASE+0x18) +#define GPIO0_IR (GPIO_BASE+0x1C) +#define GPIO0_RR1 (GPIO_BASE+0x20) +#define GPIO0_RR2 (GPIO_BASE+0x24) +#define GPIO0_ISR1L (GPIO_BASE+0x30) +#define GPIO0_ISR1H (GPIO_BASE+0x34) +#define GPIO0_ISR2L (GPIO_BASE+0x38) +#define GPIO0_ISR2H (GPIO_BASE+0x3C) +#define GPIO0_ISR3L (GPIO_BASE+0x40) +#define GPIO0_ISR3H (GPIO_BASE+0x44) + +#else /* !405EZ */ + +#define GPIO_BASE 0xEF600700 +#define GPIO0_OR (GPIO_BASE+0x0) +#define GPIO0_TCR (GPIO_BASE+0x4) +#define GPIO0_OSRH (GPIO_BASE+0x8) +#define GPIO0_OSRL (GPIO_BASE+0xC) +#define GPIO0_TSRH (GPIO_BASE+0x10) +#define GPIO0_TSRL (GPIO_BASE+0x14) +#define GPIO0_ODR (GPIO_BASE+0x18) +#define GPIO0_IR (GPIO_BASE+0x1C) +#define GPIO0_RR1 (GPIO_BASE+0x20) +#define GPIO0_RR2 (GPIO_BASE+0x24) +#define GPIO0_ISR1H (GPIO_BASE+0x30) +#define GPIO0_ISR1L (GPIO_BASE+0x34) +#define GPIO0_ISR2H (GPIO_BASE+0x38) +#define GPIO0_ISR2L (GPIO_BASE+0x3C) + +#endif /* CONFIG_405EZ */ + +#define GPIO0_BASE GPIO_BASE + +#if defined(CONFIG_405EX) +#define SDR0_SRST 0x0200 + +/* + * Software Reset Register + */ +#define SDR0_SRST_BGO PPC_REG_VAL(0, 1) +#define SDR0_SRST_PLB4 PPC_REG_VAL(1, 1) +#define SDR0_SRST_EBC PPC_REG_VAL(2, 1) +#define SDR0_SRST_OPB PPC_REG_VAL(3, 1) +#define SDR0_SRST_UART0 PPC_REG_VAL(4, 1) +#define SDR0_SRST_UART1 PPC_REG_VAL(5, 1) +#define SDR0_SRST_IIC0 PPC_REG_VAL(6, 1) +#define SDR0_SRST_BGI PPC_REG_VAL(7, 1) +#define SDR0_SRST_GPIO PPC_REG_VAL(8, 1) +#define SDR0_SRST_GPT PPC_REG_VAL(9, 1) +#define SDR0_SRST_DMC PPC_REG_VAL(10, 1) +#define SDR0_SRST_RGMII PPC_REG_VAL(11, 1) +#define SDR0_SRST_EMAC0 PPC_REG_VAL(12, 1) +#define SDR0_SRST_EMAC1 PPC_REG_VAL(13, 1) +#define SDR0_SRST_CPM PPC_REG_VAL(14, 1) +#define SDR0_SRST_EPLL PPC_REG_VAL(15, 1) +#define SDR0_SRST_UIC PPC_REG_VAL(16, 1) +#define SDR0_SRST_UPRST PPC_REG_VAL(17, 1) +#define SDR0_SRST_IIC1 PPC_REG_VAL(18, 1) +#define SDR0_SRST_SCP PPC_REG_VAL(19, 1) +#define SDR0_SRST_UHRST PPC_REG_VAL(20, 1) +#define SDR0_SRST_DMA PPC_REG_VAL(21, 1) +#define SDR0_SRST_DMAC PPC_REG_VAL(22, 1) +#define SDR0_SRST_MAL PPC_REG_VAL(23, 1) +#define SDR0_SRST_EBM PPC_REG_VAL(24, 1) +#define SDR0_SRST_GPTR PPC_REG_VAL(25, 1) +#define SDR0_SRST_PE0 PPC_REG_VAL(26, 1) +#define SDR0_SRST_PE1 PPC_REG_VAL(27, 1) +#define SDR0_SRST_CRYP PPC_REG_VAL(28, 1) +#define SDR0_SRST_PKP PPC_REG_VAL(29, 1) +#define SDR0_SRST_AHB PPC_REG_VAL(30, 1) +#define SDR0_SRST_NDFC PPC_REG_VAL(31, 1) + +#define sdr_uart0 0x0120 /* UART0 Config */ +#define sdr_uart1 0x0121 /* UART1 Config */ +#define sdr_mfr 0x4300 /* SDR0_MFR reg */ + +/* Defines for CPC0_EPRCSR register */ +#define CPC0_EPRCSR_E0NFE 0x80000000 +#define CPC0_EPRCSR_E1NFE 0x40000000 +#define CPC0_EPRCSR_E1RPP 0x00000080 +#define CPC0_EPRCSR_E0RPP 0x00000040 +#define CPC0_EPRCSR_E1ERP 0x00000020 +#define CPC0_EPRCSR_E0ERP 0x00000010 +#define CPC0_EPRCSR_E1PCI 0x00000002 +#define CPC0_EPRCSR_E0PCI 0x00000001 + +#define cpr0_clkupd 0x020 +#define cpr0_pllc 0x040 +#define cpr0_plld 0x060 +#define cpr0_cpud 0x080 +#define cpr0_plbd 0x0a0 +#define cpr0_opbd 0x0c0 +#define cpr0_perd 0x0e0 +#define cpr0_ahbd 0x100 +#define cpr0_icfg 0x140 + +#define SDR_PINSTP 0x0040 +#define sdr_sdcs 0x0060 + +#define SDR0_SDCS_SDD (0x80000000 >> 31) + +/* CUST0 Customer Configuration Register0 */ +#define SDR0_CUST0 0x4000 +#define SDR0_CUST0_MUX_E_N_G_MASK 0xC0000000 /* Mux_Emac_NDFC_GPIO */ +#define SDR0_CUST0_MUX_EMAC_SEL 0x40000000 /* Emac Selection */ +#define SDR0_CUST0_MUX_NDFC_SEL 0x80000000 /* NDFC Selection */ +#define SDR0_CUST0_MUX_GPIO_SEL 0xC0000000 /* GPIO Selection */ + +#define SDR0_CUST0_NDFC_EN_MASK 0x20000000 /* NDFC Enable Mask */ +#define SDR0_CUST0_NDFC_ENABLE 0x20000000 /* NDFC Enable */ +#define SDR0_CUST0_NDFC_DISABLE 0x00000000 /* NDFC Disable */ + +#define SDR0_CUST0_NDFC_BW_MASK 0x10000000 /* NDFC Boot Width */ +#define SDR0_CUST0_NDFC_BW_16_BIT 0x10000000 /* NDFC Boot Width = 16 Bit */ +#define SDR0_CUST0_NDFC_BW_8_BIT 0x00000000 /* NDFC Boot Width = 8 Bit */ + +#define SDR0_CUST0_NDFC_BP_MASK 0x0F000000 /* NDFC Boot Page */ +#define SDR0_CUST0_NDFC_BP_ENCODE(n) ((((unsigned long)(n))&0xF)<<24) +#define SDR0_CUST0_NDFC_BP_DECODE(n) ((((unsigned long)(n))>>24)&0x0F) + +#define SDR0_CUST0_NDFC_BAC_MASK 0x00C00000 /* NDFC Boot Address Cycle */ +#define SDR0_CUST0_NDFC_BAC_ENCODE(n) ((((unsigned long)(n))&0x3)<<22) +#define SDR0_CUST0_NDFC_BAC_DECODE(n) ((((unsigned long)(n))>>22)&0x03) + +#define SDR0_CUST0_NDFC_ARE_MASK 0x00200000 /* NDFC Auto Read Enable */ +#define SDR0_CUST0_NDFC_ARE_ENABLE 0x00200000 /* NDFC Auto Read Enable */ +#define SDR0_CUST0_NDFC_ARE_DISABLE 0x00000000 /* NDFC Auto Read Disable */ + +#define SDR0_CUST0_NRB_MASK 0x00100000 /* NDFC Ready / Busy */ +#define SDR0_CUST0_NRB_BUSY 0x00100000 /* Busy */ +#define SDR0_CUST0_NRB_READY 0x00000000 /* Ready */ + +#define SDR0_CUST0_NDRSC_MASK 0x0000FFF0 /* NDFC Device Reset Count Mask */ +#define SDR0_CUST0_NDRSC_ENCODE(n) ((((unsigned long)(n))&0xFFF)<<4) +#define SDR0_CUST0_NDRSC_DECODE(n) ((((unsigned long)(n))>>4)&0xFFF) + +#define SDR0_CUST0_CHIPSELGAT_MASK 0x0000000F /* Chip Select Gating Mask */ +#define SDR0_CUST0_CHIPSELGAT_DIS 0x00000000 /* Chip Select Gating Disable */ +#define SDR0_CUST0_CHIPSELGAT_ENALL 0x0000000F /* All Chip Select Gating Enable */ +#define SDR0_CUST0_CHIPSELGAT_EN0 0x00000008 /* Chip Select0 Gating Enable */ +#define SDR0_CUST0_CHIPSELGAT_EN1 0x00000004 /* Chip Select1 Gating Enable */ +#define SDR0_CUST0_CHIPSELGAT_EN2 0x00000002 /* Chip Select2 Gating Enable */ +#define SDR0_CUST0_CHIPSELGAT_EN3 0x00000001 /* Chip Select3 Gating Enable */ + +#define SDR0_PFC0 0x4100 +#define SDR0_PFC1 0x4101 +#define SDR0_PFC1_U1ME 0x02000000 +#define SDR0_PFC1_U0ME 0x00080000 +#define SDR0_PFC1_U0IM 0x00040000 +#define SDR0_PFC1_SIS 0x00020000 +#define SDR0_PFC1_DMAAEN 0x00010000 +#define SDR0_PFC1_DMADEN 0x00008000 +#define SDR0_PFC1_USBEN 0x00004000 +#define SDR0_PFC1_AHBSWAP 0x00000020 +#define SDR0_PFC1_USBBIGEN 0x00000010 +#define SDR0_PFC1_GPT_FREQ 0x0000000f +#endif + +/* General Purpose Timer (GPT) Register Offsets */ +#define GPT0_TBC 0x00000000 +#define GPT0_IM 0x00000018 +#define GPT0_ISS 0x0000001C +#define GPT0_ISC 0x00000020 +#define GPT0_IE 0x00000024 +#define GPT0_COMP0 0x00000080 +#define GPT0_COMP1 0x00000084 +#define GPT0_COMP2 0x00000088 +#define GPT0_COMP3 0x0000008C +#define GPT0_COMP4 0x00000090 +#define GPT0_COMP5 0x00000094 +#define GPT0_COMP6 0x00000098 +#define GPT0_MASK0 0x000000C0 +#define GPT0_MASK1 0x000000C4 +#define GPT0_MASK2 0x000000C8 +#define GPT0_MASK3 0x000000CC +#define GPT0_MASK4 0x000000D0 +#define GPT0_MASK5 0x000000D4 +#define GPT0_MASK6 0x000000D8 +#define GPT0_DCT0 0x00000110 +#define GPT0_DCIS 0x0000011C + +#endif /* __PPC405_H__ */ diff --git a/libcpu/ppc/ppc405/include/asm/ppc4xx-uic.h b/libcpu/ppc/ppc405/include/asm/ppc4xx-uic.h index e70b99bda6..cdb542c2da 100644 --- a/libcpu/ppc/ppc405/include/asm/ppc4xx-uic.h +++ b/libcpu/ppc/ppc405/include/asm/ppc4xx-uic.h @@ -1,61 +1,61 @@ -#ifndef _PPC4xx_UIC_H_
-#define _PPC4xx_UIC_H_
-
-/*
- * Define the number of UIC's
- */
-#define UIC_MAX 1
-#define IRQ_MAX UIC_MAX * 32
-
-/* UIC0 dcr base address */
-#define UIC0_DCR_BASE 0xc0
-
-/*
- * UIC register
- */
-#define UIC_SR 0x0 /* UIC status */
-#define UIC_ER 0x2 /* UIC enable */
-#define UIC_CR 0x3 /* UIC critical */
-#define UIC_PR 0x4 /* UIC polarity */
-#define UIC_TR 0x5 /* UIC triggering */
-#define UIC_MSR 0x6 /* UIC masked status */
-#define UIC_VR 0x7 /* UIC vector */
-#define UIC_VCR 0x8 /* UIC vector configuration */
-
-#define uic0sr (UIC0_DCR_BASE+0x0) /* UIC0 status */
-#define uic0er (UIC0_DCR_BASE+0x2) /* UIC0 enable */
-#define uic0cr (UIC0_DCR_BASE+0x3) /* UIC0 critical */
-#define uic0pr (UIC0_DCR_BASE+0x4) /* UIC0 polarity */
-#define uic0tr (UIC0_DCR_BASE+0x5) /* UIC0 triggering */
-#define uic0msr (UIC0_DCR_BASE+0x6) /* UIC0 masked status */
-#define uic0vr (UIC0_DCR_BASE+0x7) /* UIC0 vector */
-#define uic0vcr (UIC0_DCR_BASE+0x8) /* UIC0 vector configuration */
-
-/* The following is for compatibility with 405 code */
-#define uicsr uic0sr
-#define uicer uic0er
-#define uiccr uic0cr
-#define uicpr uic0pr
-#define uictr uic0tr
-#define uicmsr uic0msr
-#define uicvr uic0vr
-#define uicvcr uic0vcr
-
-/* the interrupt vector definitions */
-#define VECNUM_MAL_SERR 10
-#define VECNUM_MAL_TXEOB 11
-#define VECNUM_MAL_RXEOB 12
-#define VECNUM_MAL_TXDE 13
-#define VECNUM_MAL_RXDE 14
-#define VECNUM_ETH0 15
-#define VECNUM_ETH1_OFFS 2
-#define VECNUM_EIRQ6 29
-
-/*
- * Mask definitions (used for example in 4xx_enet.c)
- */
-#define UIC_MASK(vec) (0x80000000 >> ((vec) & 0x1f))
-/* UIC_NR won't work for 440GX because of its specific UIC DCR addresses */
-#define UIC_NR(vec) ((vec) >> 5)
-
-#endif /* _PPC4xx_UIC_H_ */
+#ifndef _PPC4xx_UIC_H_ +#define _PPC4xx_UIC_H_ + +/* + * Define the number of UIC's + */ +#define UIC_MAX 1 +#define IRQ_MAX UIC_MAX * 32 + +/* UIC0 dcr base address */ +#define UIC0_DCR_BASE 0xc0 + +/* + * UIC register + */ +#define UIC_SR 0x0 /* UIC status */ +#define UIC_ER 0x2 /* UIC enable */ +#define UIC_CR 0x3 /* UIC critical */ +#define UIC_PR 0x4 /* UIC polarity */ +#define UIC_TR 0x5 /* UIC triggering */ +#define UIC_MSR 0x6 /* UIC masked status */ +#define UIC_VR 0x7 /* UIC vector */ +#define UIC_VCR 0x8 /* UIC vector configuration */ + +#define uic0sr (UIC0_DCR_BASE+0x0) /* UIC0 status */ +#define uic0er (UIC0_DCR_BASE+0x2) /* UIC0 enable */ +#define uic0cr (UIC0_DCR_BASE+0x3) /* UIC0 critical */ +#define uic0pr (UIC0_DCR_BASE+0x4) /* UIC0 polarity */ +#define uic0tr (UIC0_DCR_BASE+0x5) /* UIC0 triggering */ +#define uic0msr (UIC0_DCR_BASE+0x6) /* UIC0 masked status */ +#define uic0vr (UIC0_DCR_BASE+0x7) /* UIC0 vector */ +#define uic0vcr (UIC0_DCR_BASE+0x8) /* UIC0 vector configuration */ + +/* The following is for compatibility with 405 code */ +#define uicsr uic0sr +#define uicer uic0er +#define uiccr uic0cr +#define uicpr uic0pr +#define uictr uic0tr +#define uicmsr uic0msr +#define uicvr uic0vr +#define uicvcr uic0vcr + +/* the interrupt vector definitions */ +#define VECNUM_MAL_SERR 10 +#define VECNUM_MAL_TXEOB 11 +#define VECNUM_MAL_RXEOB 12 +#define VECNUM_MAL_TXDE 13 +#define VECNUM_MAL_RXDE 14 +#define VECNUM_ETH0 15 +#define VECNUM_ETH1_OFFS 2 +#define VECNUM_EIRQ6 29 + +/* + * Mask definitions (used for example in 4xx_enet.c) + */ +#define UIC_MASK(vec) (0x80000000 >> ((vec) & 0x1f)) +/* UIC_NR won't work for 440GX because of its specific UIC DCR addresses */ +#define UIC_NR(vec) ((vec) >> 5) + +#endif /* _PPC4xx_UIC_H_ */ diff --git a/libcpu/ppc/ppc405/include/asm/ppc4xx.h b/libcpu/ppc/ppc405/include/asm/ppc4xx.h index bf055f0879..57fe7ab221 100644 --- a/libcpu/ppc/ppc405/include/asm/ppc4xx.h +++ b/libcpu/ppc/ppc405/include/asm/ppc4xx.h @@ -1,134 +1,134 @@ -/*----------------------------------------------------------------------------+
-|
-| This source code has been made available to you by IBM on an AS-IS
-| basis. Anyone receiving this source is licensed under IBM
-| copyrights to use it in any way he or she deems fit, including
-| copying it, modifying it, compiling it, and redistributing it either
-| with or without modifications. No license under IBM patents or
-| patent applications is to be implied by the copyright license.
-|
-| Any user of this software should understand that IBM cannot provide
-| technical support for this software and will not be responsible for
-| any consequences resulting from the use of this software.
-|
-| Any person who transfers this source code or any derivative work
-| must include the IBM copyright notice, this paragraph, and the
-| preceding two paragraphs in the transferred software.
-|
-| COPYRIGHT I B M CORPORATION 1999
-| LICENSED MATERIAL - PROGRAM PROPERTY OF I B M
-+----------------------------------------------------------------------------*/
-
-#ifndef __PPC4XX_H__
-#define __PPC4XX_H__
-
-/*
- * Configure which SDRAM/DDR/DDR2 controller is equipped
- */
-#define CONFIG_SDRAM_PPC4xx_IBM_SDRAM /* IBM SDRAM controller */
-
-#include <asm/ppc405.h>
-#include <asm/ppc4xx-uic.h>
-
-/*
- * Macro for generating register field mnemonics
- */
-#define PPC_REG_BITS 32
-#define PPC_REG_VAL(bit, value) ((value) << ((PPC_REG_BITS - 1) - (bit)))
-
-/*
- * Elide casts when assembling register mnemonics
- */
-#ifndef __ASSEMBLY__
-#define static_cast(type, val) (type)(val)
-#else
-#define static_cast(type, val) (val)
-#endif
-
-/*
- * Common stuff for 4xx (405 and 440)
- */
-
-#define EXC_OFF_SYS_RESET 0x0100 /* System reset */
-#define _START_OFFSET (EXC_OFF_SYS_RESET + 0x2000)
-
-#define RESET_VECTOR 0xfffffffc
-#define CACHELINE_MASK (CONFIG_SYS_CACHELINE_SIZE - 1) /* Address mask for cache
- line aligned data. */
-
-#define CPR0_DCR_BASE 0x0C
-#define cprcfga (CPR0_DCR_BASE+0x0)
-#define cprcfgd (CPR0_DCR_BASE+0x1)
-
-#define SDR_DCR_BASE 0x0E
-#define sdrcfga (SDR_DCR_BASE+0x0)
-#define sdrcfgd (SDR_DCR_BASE+0x1)
-
-#define SDRAM_DCR_BASE 0x10
-#define memcfga (SDRAM_DCR_BASE+0x0)
-#define memcfgd (SDRAM_DCR_BASE+0x1)
-
-#define EBC_DCR_BASE 0x12
-#define ebccfga (EBC_DCR_BASE+0x0)
-#define ebccfgd (EBC_DCR_BASE+0x1)
-
-/*
- * Macros for indirect DCR access
- */
-#define mtcpr(reg, d) do { mtdcr(cprcfga,reg);mtdcr(cprcfgd,d); } while (0)
-#define mfcpr(reg, d) do { mtdcr(cprcfga,reg);d = mfdcr(cprcfgd); } while (0)
-
-#define mtebc(reg, d) do { mtdcr(ebccfga,reg);mtdcr(ebccfgd,d); } while (0)
-#define mfebc(reg, d) do { mtdcr(ebccfga,reg);d = mfdcr(ebccfgd); } while (0)
-
-#define mtsdram(reg, d) do { mtdcr(memcfga,reg);mtdcr(memcfgd,d); } while (0)
-#define mfsdram(reg, d) do { mtdcr(memcfga,reg);d = mfdcr(memcfgd); } while (0)
-
-#define mtsdr(reg, d) do { mtdcr(sdrcfga,reg);mtdcr(sdrcfgd,d); } while (0)
-#define mfsdr(reg, d) do { mtdcr(sdrcfga,reg);d = mfdcr(sdrcfgd); } while (0)
-
-#ifndef __ASSEMBLY__
-
-typedef struct
-{
- unsigned long freqDDR;
- unsigned long freqEBC;
- unsigned long freqOPB;
- unsigned long freqPCI;
- unsigned long freqPLB;
- unsigned long freqTmrClk;
- unsigned long freqUART;
- unsigned long freqProcessor;
- unsigned long freqVCOHz;
- unsigned long freqVCOMhz; /* in MHz */
- unsigned long pciClkSync; /* PCI clock is synchronous */
- unsigned long pciIntArbEn; /* Internal PCI arbiter is enabled */
- unsigned long pllExtBusDiv;
- unsigned long pllFbkDiv;
- unsigned long pllFwdDiv;
- unsigned long pllFwdDivA;
- unsigned long pllFwdDivB;
- unsigned long pllOpbDiv;
- unsigned long pllPciDiv;
- unsigned long pllPlbDiv;
-} PPC4xx_SYS_INFO;
-
-static inline rt_uint32_t get_mcsr(void)
-{
- rt_uint32_t val;
-
- asm volatile("mfspr %0, 0x23c" : "=r" (val) :);
- return val;
-}
-
-static inline void set_mcsr(rt_uint32_t val)
-{
- asm volatile("mtspr 0x23c, %0" : "=r" (val) :);
-}
-
-#endif /* __ASSEMBLY__ */
-
-/* for multi-cpu support */
-#define NA_OR_UNKNOWN_CPU -1
-
-#endif /* __PPC4XX_H__ */
+/*----------------------------------------------------------------------------+ +| +| This source code has been made available to you by IBM on an AS-IS +| basis. Anyone receiving this source is licensed under IBM +| copyrights to use it in any way he or she deems fit, including +| copying it, modifying it, compiling it, and redistributing it either +| with or without modifications. No license under IBM patents or +| patent applications is to be implied by the copyright license. +| +| Any user of this software should understand that IBM cannot provide +| technical support for this software and will not be responsible for +| any consequences resulting from the use of this software. +| +| Any person who transfers this source code or any derivative work +| must include the IBM copyright notice, this paragraph, and the +| preceding two paragraphs in the transferred software. +| +| COPYRIGHT I B M CORPORATION 1999 +| LICENSED MATERIAL - PROGRAM PROPERTY OF I B M ++----------------------------------------------------------------------------*/ + +#ifndef __PPC4XX_H__ +#define __PPC4XX_H__ + +/* + * Configure which SDRAM/DDR/DDR2 controller is equipped + */ +#define CONFIG_SDRAM_PPC4xx_IBM_SDRAM /* IBM SDRAM controller */ + +#include <asm/ppc405.h> +#include <asm/ppc4xx-uic.h> + +/* + * Macro for generating register field mnemonics + */ +#define PPC_REG_BITS 32 +#define PPC_REG_VAL(bit, value) ((value) << ((PPC_REG_BITS - 1) - (bit))) + +/* + * Elide casts when assembling register mnemonics + */ +#ifndef __ASSEMBLY__ +#define static_cast(type, val) (type)(val) +#else +#define static_cast(type, val) (val) +#endif + +/* + * Common stuff for 4xx (405 and 440) + */ + +#define EXC_OFF_SYS_RESET 0x0100 /* System reset */ +#define _START_OFFSET (EXC_OFF_SYS_RESET + 0x2000) + +#define RESET_VECTOR 0xfffffffc +#define CACHELINE_MASK (CONFIG_SYS_CACHELINE_SIZE - 1) /* Address mask for cache + line aligned data. */ + +#define CPR0_DCR_BASE 0x0C +#define cprcfga (CPR0_DCR_BASE+0x0) +#define cprcfgd (CPR0_DCR_BASE+0x1) + +#define SDR_DCR_BASE 0x0E +#define sdrcfga (SDR_DCR_BASE+0x0) +#define sdrcfgd (SDR_DCR_BASE+0x1) + +#define SDRAM_DCR_BASE 0x10 +#define memcfga (SDRAM_DCR_BASE+0x0) +#define memcfgd (SDRAM_DCR_BASE+0x1) + +#define EBC_DCR_BASE 0x12 +#define ebccfga (EBC_DCR_BASE+0x0) +#define ebccfgd (EBC_DCR_BASE+0x1) + +/* + * Macros for indirect DCR access + */ +#define mtcpr(reg, d) do { mtdcr(cprcfga,reg);mtdcr(cprcfgd,d); } while (0) +#define mfcpr(reg, d) do { mtdcr(cprcfga,reg);d = mfdcr(cprcfgd); } while (0) + +#define mtebc(reg, d) do { mtdcr(ebccfga,reg);mtdcr(ebccfgd,d); } while (0) +#define mfebc(reg, d) do { mtdcr(ebccfga,reg);d = mfdcr(ebccfgd); } while (0) + +#define mtsdram(reg, d) do { mtdcr(memcfga,reg);mtdcr(memcfgd,d); } while (0) +#define mfsdram(reg, d) do { mtdcr(memcfga,reg);d = mfdcr(memcfgd); } while (0) + +#define mtsdr(reg, d) do { mtdcr(sdrcfga,reg);mtdcr(sdrcfgd,d); } while (0) +#define mfsdr(reg, d) do { mtdcr(sdrcfga,reg);d = mfdcr(sdrcfgd); } while (0) + +#ifndef __ASSEMBLY__ + +typedef struct +{ + unsigned long freqDDR; + unsigned long freqEBC; + unsigned long freqOPB; + unsigned long freqPCI; + unsigned long freqPLB; + unsigned long freqTmrClk; + unsigned long freqUART; + unsigned long freqProcessor; + unsigned long freqVCOHz; + unsigned long freqVCOMhz; /* in MHz */ + unsigned long pciClkSync; /* PCI clock is synchronous */ + unsigned long pciIntArbEn; /* Internal PCI arbiter is enabled */ + unsigned long pllExtBusDiv; + unsigned long pllFbkDiv; + unsigned long pllFwdDiv; + unsigned long pllFwdDivA; + unsigned long pllFwdDivB; + unsigned long pllOpbDiv; + unsigned long pllPciDiv; + unsigned long pllPlbDiv; +} PPC4xx_SYS_INFO; + +static inline rt_uint32_t get_mcsr(void) +{ + rt_uint32_t val; + + asm volatile("mfspr %0, 0x23c" : "=r" (val) :); + return val; +} + +static inline void set_mcsr(rt_uint32_t val) +{ + asm volatile("mtspr 0x23c, %0" : "=r" (val) :); +} + +#endif /* __ASSEMBLY__ */ + +/* for multi-cpu support */ +#define NA_OR_UNKNOWN_CPU -1 + +#endif /* __PPC4XX_H__ */ diff --git a/libcpu/ppc/ppc405/include/asm/ppc_defs.h b/libcpu/ppc/ppc405/include/asm/ppc_defs.h index dd1e42a925..88aed26009 100644 --- a/libcpu/ppc/ppc405/include/asm/ppc_defs.h +++ b/libcpu/ppc/ppc405/include/asm/ppc_defs.h @@ -1,73 +1,73 @@ -/*
- * (C) Copyright 2000
- * Wolfgang Denk, DENX Software Engineering, [email protected].
- *
- * See file CREDITS for list of people who contributed to this
- * project.
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License as
- * published by the Free Software Foundation; either version 2 of
- * the License, or (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
- * MA 02111-1307 USA
- */
-
-/*
- * WARNING! This file is automatically generated - DO NOT EDIT!
- */
-#define STACK_FRAME_OVERHEAD 16
-#define INT_FRAME_SIZE 192
-#define GPR0 16
-#define GPR1 20
-#define GPR2 24
-#define GPR3 28
-#define GPR4 32
-#define GPR5 36
-#define GPR6 40
-#define GPR7 44
-#define GPR8 48
-#define GPR9 52
-#define GPR10 56
-#define GPR11 60
-#define GPR12 64
-#define GPR13 68
-#define GPR14 72
-#define GPR15 76
-#define GPR16 80
-#define GPR17 84
-#define GPR18 88
-#define GPR19 92
-#define GPR20 96
-#define GPR21 100
-#define GPR22 104
-#define GPR23 108
-#define GPR24 112
-#define GPR25 116
-#define GPR26 120
-#define GPR27 124
-#define GPR28 128
-#define GPR29 132
-#define GPR30 136
-#define GPR31 140
-#define _NIP 144
-#define _MSR 148
-#define ORIG_GPR3 152
-#define _CTR 156
-#define _LINK 160
-#define _XER 164
-#define _CCR 168
-#define _MQ 172
-#define TRAP 176
-#define _DAR 180
-#define _DSISR 184
-#define RESULT 188
-
+/* + * (C) Copyright 2000 + * Wolfgang Denk, DENX Software Engineering, [email protected]. + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +/* + * WARNING! This file is automatically generated - DO NOT EDIT! + */ +#define STACK_FRAME_OVERHEAD 16 +#define INT_FRAME_SIZE 192 +#define GPR0 16 +#define GPR1 20 +#define GPR2 24 +#define GPR3 28 +#define GPR4 32 +#define GPR5 36 +#define GPR6 40 +#define GPR7 44 +#define GPR8 48 +#define GPR9 52 +#define GPR10 56 +#define GPR11 60 +#define GPR12 64 +#define GPR13 68 +#define GPR14 72 +#define GPR15 76 +#define GPR16 80 +#define GPR17 84 +#define GPR18 88 +#define GPR19 92 +#define GPR20 96 +#define GPR21 100 +#define GPR22 104 +#define GPR23 108 +#define GPR24 112 +#define GPR25 116 +#define GPR26 120 +#define GPR27 124 +#define GPR28 128 +#define GPR29 132 +#define GPR30 136 +#define GPR31 140 +#define _NIP 144 +#define _MSR 148 +#define ORIG_GPR3 152 +#define _CTR 156 +#define _LINK 160 +#define _XER 164 +#define _CCR 168 +#define _MQ 172 +#define TRAP 176 +#define _DAR 180 +#define _DSISR 184 +#define RESULT 188 + diff --git a/libcpu/ppc/ppc405/include/asm/processor.h b/libcpu/ppc/ppc405/include/asm/processor.h index fead870558..7aeeb01dc5 100644 --- a/libcpu/ppc/ppc405/include/asm/processor.h +++ b/libcpu/ppc/ppc405/include/asm/processor.h @@ -1,1238 +1,1238 @@ -#ifndef __ASM_PPC_PROCESSOR_H
-#define __ASM_PPC_PROCESSOR_H
-
-/*
- * Default implementation of macro that returns current
- * instruction pointer ("program counter").
- */
-#define current_text_addr() ({ __label__ _l; _l: &&_l;})
-
-#include <config.h>
-
-#include <asm/ptrace.h>
-#include <asm/types.h>
-
-/* Machine State Register (MSR) Fields */
-
-#ifdef CONFIG_PPC64BRIDGE
-#define MSR_SF (1<<63)
-#define MSR_ISF (1<<61)
-#endif /* CONFIG_PPC64BRIDGE */
-#define MSR_UCLE (1<<26) /* User-mode cache lock enable (e500) */
-#define MSR_VEC (1<<25) /* Enable AltiVec(74xx) */
-#define MSR_SPE (1<<25) /* Enable SPE(e500) */
-#define MSR_POW (1<<18) /* Enable Power Management */
-#define MSR_WE (1<<18) /* Wait State Enable */
-#define MSR_TGPR (1<<17) /* TLB Update registers in use */
-#define MSR_CE (1<<17) /* Critical Interrupt Enable */
-#define MSR_ILE (1<<16) /* Interrupt Little Endian */
-#define MSR_EE (1<<15) /* External Interrupt Enable */
-#define MSR_PR (1<<14) /* Problem State / Privilege Level */
-#define MSR_FP (1<<13) /* Floating Point enable */
-#define MSR_ME (1<<12) /* Machine Check Enable */
-#define MSR_FE0 (1<<11) /* Floating Exception mode 0 */
-#define MSR_SE (1<<10) /* Single Step */
-#define MSR_DWE (1<<10) /* Debug Wait Enable (4xx) */
-#define MSR_UBLE (1<<10) /* BTB lock enable (e500) */
-#define MSR_BE (1<<9) /* Branch Trace */
-#define MSR_DE (1<<9) /* Debug Exception Enable */
-#define MSR_FE1 (1<<8) /* Floating Exception mode 1 */
-#define MSR_IP (1<<6) /* Exception prefix 0x000/0xFFF */
-#define MSR_IR (1<<5) /* Instruction Relocate */
-#define MSR_IS (1<<5) /* Book E Instruction space */
-#define MSR_DR (1<<4) /* Data Relocate */
-#define MSR_DS (1<<4) /* Book E Data space */
-#define MSR_PE (1<<3) /* Protection Enable */
-#define MSR_PX (1<<2) /* Protection Exclusive Mode */
-#define MSR_PMM (1<<2) /* Performance monitor mark bit (e500) */
-#define MSR_RI (1<<1) /* Recoverable Exception */
-#define MSR_LE (1<<0) /* Little Endian */
-
-#ifdef CONFIG_APUS_FAST_EXCEPT
-#define MSR_ MSR_ME|MSR_IP|MSR_RI
-#else
-#define MSR_ MSR_ME|MSR_RI
-#endif
-
-#ifndef CONFIG_E500
-#define MSR_KERNEL MSR_|MSR_IR|MSR_DR
-#else
-#define MSR_KERNEL MSR_ME
-#endif
-
-/* Floating Point Status and Control Register (FPSCR) Fields */
-
-#define FPSCR_FX 0x80000000 /* FPU exception summary */
-#define FPSCR_FEX 0x40000000 /* FPU enabled exception summary */
-#define FPSCR_VX 0x20000000 /* Invalid operation summary */
-#define FPSCR_OX 0x10000000 /* Overflow exception summary */
-#define FPSCR_UX 0x08000000 /* Underflow exception summary */
-#define FPSCR_ZX 0x04000000 /* Zero-devide exception summary */
-#define FPSCR_XX 0x02000000 /* Inexact exception summary */
-#define FPSCR_VXSNAN 0x01000000 /* Invalid op for SNaN */
-#define FPSCR_VXISI 0x00800000 /* Invalid op for Inv - Inv */
-#define FPSCR_VXIDI 0x00400000 /* Invalid op for Inv / Inv */
-#define FPSCR_VXZDZ 0x00200000 /* Invalid op for Zero / Zero */
-#define FPSCR_VXIMZ 0x00100000 /* Invalid op for Inv * Zero */
-#define FPSCR_VXVC 0x00080000 /* Invalid op for Compare */
-#define FPSCR_FR 0x00040000 /* Fraction rounded */
-#define FPSCR_FI 0x00020000 /* Fraction inexact */
-#define FPSCR_FPRF 0x0001f000 /* FPU Result Flags */
-#define FPSCR_FPCC 0x0000f000 /* FPU Condition Codes */
-#define FPSCR_VXSOFT 0x00000400 /* Invalid op for software request */
-#define FPSCR_VXSQRT 0x00000200 /* Invalid op for square root */
-#define FPSCR_VXCVI 0x00000100 /* Invalid op for integer convert */
-#define FPSCR_VE 0x00000080 /* Invalid op exception enable */
-#define FPSCR_OE 0x00000040 /* IEEE overflow exception enable */
-#define FPSCR_UE 0x00000020 /* IEEE underflow exception enable */
-#define FPSCR_ZE 0x00000010 /* IEEE zero divide exception enable */
-#define FPSCR_XE 0x00000008 /* FP inexact exception enable */
-#define FPSCR_NI 0x00000004 /* FPU non IEEE-Mode */
-#define FPSCR_RN 0x00000003 /* FPU rounding control */
-
-/* Special Purpose Registers (SPRNs)*/
-
-/* PPC440 Architecture is BOOK-E */
-#ifdef CONFIG_440
-#define CONFIG_BOOKE
-#endif
-
-#define SPRN_CCR0 0x3B3 /* Core Configuration Register 0 */
-#ifdef CONFIG_BOOKE
-#define SPRN_CCR1 0x378 /* Core Configuration Register for 440 only */
-#endif
-#define SPRN_CDBCR 0x3D7 /* Cache Debug Control Register */
-#define SPRN_CTR 0x009 /* Count Register */
-#define SPRN_DABR 0x3F5 /* Data Address Breakpoint Register */
-#ifndef CONFIG_BOOKE
-#define SPRN_DAC1 0x3F6 /* Data Address Compare 1 */
-#define SPRN_DAC2 0x3F7 /* Data Address Compare 2 */
-#else
-#define SPRN_DAC1 0x13C /* Book E Data Address Compare 1 */
-#define SPRN_DAC2 0x13D /* Book E Data Address Compare 2 */
-#endif /* CONFIG_BOOKE */
-#define SPRN_DAR 0x013 /* Data Address Register */
-#define SPRN_DBAT0L 0x219 /* Data BAT 0 Lower Register */
-#define SPRN_DBAT0U 0x218 /* Data BAT 0 Upper Register */
-#define SPRN_DBAT1L 0x21B /* Data BAT 1 Lower Register */
-#define SPRN_DBAT1U 0x21A /* Data BAT 1 Upper Register */
-#define SPRN_DBAT2L 0x21D /* Data BAT 2 Lower Register */
-#define SPRN_DBAT2U 0x21C /* Data BAT 2 Upper Register */
-#define SPRN_DBAT3L 0x21F /* Data BAT 3 Lower Register */
-#define SPRN_DBAT3U 0x21E /* Data BAT 3 Upper Register */
-#define SPRN_DBAT4L 0x239 /* Data BAT 4 Lower Register */
-#define SPRN_DBAT4U 0x238 /* Data BAT 4 Upper Register */
-#define SPRN_DBAT5L 0x23B /* Data BAT 5 Lower Register */
-#define SPRN_DBAT5U 0x23A /* Data BAT 5 Upper Register */
-#define SPRN_DBAT6L 0x23D /* Data BAT 6 Lower Register */
-#define SPRN_DBAT6U 0x23C /* Data BAT 6 Upper Register */
-#define SPRN_DBAT7L 0x23F /* Data BAT 7 Lower Register */
-#define SPRN_DBAT7U 0x23E /* Data BAT 7 Lower Register */
-#define SPRN_DBCR 0x3F2 /* Debug Control Regsiter */
-#define DBCR_EDM 0x80000000
-#define DBCR_IDM 0x40000000
-#define DBCR_RST(x) (((x) & 0x3) << 28)
-#define DBCR_RST_NONE 0
-#define DBCR_RST_CORE 1
-#define DBCR_RST_CHIP 2
-#define DBCR_RST_SYSTEM 3
-#define DBCR_IC 0x08000000 /* Instruction Completion Debug Evnt */
-#define DBCR_BT 0x04000000 /* Branch Taken Debug Event */
-#define DBCR_EDE 0x02000000 /* Exception Debug Event */
-#define DBCR_TDE 0x01000000 /* TRAP Debug Event */
-#define DBCR_FER 0x00F80000 /* First Events Remaining Mask */
-#define DBCR_FT 0x00040000 /* Freeze Timers on Debug Event */
-#define DBCR_IA1 0x00020000 /* Instr. Addr. Compare 1 Enable */
-#define DBCR_IA2 0x00010000 /* Instr. Addr. Compare 2 Enable */
-#define DBCR_D1R 0x00008000 /* Data Addr. Compare 1 Read Enable */
-#define DBCR_D1W 0x00004000 /* Data Addr. Compare 1 Write Enable */
-#define DBCR_D1S(x) (((x) & 0x3) << 12) /* Data Adrr. Compare 1 Size */
-#define DAC_BYTE 0
-#define DAC_HALF 1
-#define DAC_WORD 2
-#define DAC_QUAD 3
-#define DBCR_D2R 0x00000800 /* Data Addr. Compare 2 Read Enable */
-#define DBCR_D2W 0x00000400 /* Data Addr. Compare 2 Write Enable */
-#define DBCR_D2S(x) (((x) & 0x3) << 8) /* Data Addr. Compare 2 Size */
-#define DBCR_SBT 0x00000040 /* Second Branch Taken Debug Event */
-#define DBCR_SED 0x00000020 /* Second Exception Debug Event */
-#define DBCR_STD 0x00000010 /* Second Trap Debug Event */
-#define DBCR_SIA 0x00000008 /* Second IAC Enable */
-#define DBCR_SDA 0x00000004 /* Second DAC Enable */
-#define DBCR_JOI 0x00000002 /* JTAG Serial Outbound Int. Enable */
-#define DBCR_JII 0x00000001 /* JTAG Serial Inbound Int. Enable */
-#ifndef CONFIG_BOOKE
-#define SPRN_DBCR0 0x3F2 /* Debug Control Register 0 */
-#else
-#define SPRN_DBCR0 0x134 /* Book E Debug Control Register 0 */
-#endif /* CONFIG_BOOKE */
-#ifndef CONFIG_BOOKE
-#define SPRN_DBCR1 0x3BD /* Debug Control Register 1 */
-#define SPRN_DBSR 0x3F0 /* Debug Status Register */
-#else
-#define SPRN_DBCR1 0x135 /* Book E Debug Control Register 1 */
-#ifdef CONFIG_BOOKE
-#define SPRN_DBDR 0x3f3 /* Debug Data Register */
-#endif
-#define SPRN_DBSR 0x130 /* Book E Debug Status Register */
-#define DBSR_IC 0x08000000 /* Book E Instruction Completion */
-#define DBSR_TIE 0x01000000 /* Book E Trap Instruction Event */
-#endif /* CONFIG_BOOKE */
-#define SPRN_DCCR 0x3FA /* Data Cache Cacheability Register */
-#define DCCR_NOCACHE 0 /* Noncacheable */
-#define DCCR_CACHE 1 /* Cacheable */
-#ifndef CONFIG_BOOKE
-#define SPRN_DCDBTRL 0x39c /* Data Cache Debug Tag Register Low */
-#define SPRN_DCDBTRH 0x39d /* Data Cache Debug Tag Register High */
-#endif
-#define SPRN_DCMP 0x3D1 /* Data TLB Compare Register */
-#define SPRN_DCWR 0x3BA /* Data Cache Write-thru Register */
-#define DCWR_COPY 0 /* Copy-back */
-#define DCWR_WRITE 1 /* Write-through */
-#ifndef CONFIG_BOOKE
-#define SPRN_DEAR 0x3D5 /* Data Error Address Register */
-#else
-#define SPRN_DEAR 0x03D /* Book E Data Error Address Register */
-#endif /* CONFIG_BOOKE */
-#define SPRN_DEC 0x016 /* Decrement Register */
-#define SPRN_DMISS 0x3D0 /* Data TLB Miss Register */
-#ifdef CONFIG_BOOKE
-#define SPRN_DNV0 0x390 /* Data Cache Normal Victim 0 */
-#define SPRN_DNV1 0x391 /* Data Cache Normal Victim 1 */
-#define SPRN_DNV2 0x392 /* Data Cache Normal Victim 2 */
-#define SPRN_DNV3 0x393 /* Data Cache Normal Victim 3 */
-#endif
-#define SPRN_DSISR 0x012 /* Data Storage Interrupt Status Register */
-#ifdef CONFIG_BOOKE
-#define SPRN_DTV0 0x394 /* Data Cache Transient Victim 0 */
-#define SPRN_DTV1 0x395 /* Data Cache Transient Victim 1 */
-#define SPRN_DTV2 0x396 /* Data Cache Transient Victim 2 */
-#define SPRN_DTV3 0x397 /* Data Cache Transient Victim 3 */
-#define SPRN_DVLIM 0x398 /* Data Cache Victim Limit */
-#endif
-#define SPRN_EAR 0x11A /* External Address Register */
-#ifndef CONFIG_BOOKE
-#define SPRN_ESR 0x3D4 /* Exception Syndrome Register */
-#else
-#define SPRN_ESR 0x03E /* Book E Exception Syndrome Register */
-#endif /* CONFIG_BOOKE */
-#define ESR_IMCP 0x80000000 /* Instr. Machine Check - Protection */
-#define ESR_IMCN 0x40000000 /* Instr. Machine Check - Non-config */
-#define ESR_IMCB 0x20000000 /* Instr. Machine Check - Bus error */
-#define ESR_IMCT 0x10000000 /* Instr. Machine Check - Timeout */
-#define ESR_PIL 0x08000000 /* Program Exception - Illegal */
-#define ESR_PPR 0x04000000 /* Program Exception - Priveleged */
-#define ESR_PTR 0x02000000 /* Program Exception - Trap */
-#define ESR_DST 0x00800000 /* Storage Exception - Data miss */
-#define ESR_DIZ 0x00400000 /* Storage Exception - Zone fault */
-#define SPRN_EVPR 0x3D6 /* Exception Vector Prefix Register */
-#define SPRN_HASH1 0x3D2 /* Primary Hash Address Register */
-#define SPRN_HASH2 0x3D3 /* Secondary Hash Address Resgister */
-#define SPRN_HID0 0x3F0 /* Hardware Implementation Register 0 */
-
-#define HID0_ICE_SHIFT 15
-#define HID0_DCE_SHIFT 14
-#define HID0_DLOCK_SHIFT 12
-
-#define HID0_EMCP (1<<31) /* Enable Machine Check pin */
-#define HID0_EBA (1<<29) /* Enable Bus Address Parity */
-#define HID0_EBD (1<<28) /* Enable Bus Data Parity */
-#define HID0_SBCLK (1<<27)
-#define HID0_EICE (1<<26)
-#define HID0_ECLK (1<<25)
-#define HID0_PAR (1<<24)
-#define HID0_DOZE (1<<23)
-#define HID0_NAP (1<<22)
-#define HID0_SLEEP (1<<21)
-#define HID0_DPM (1<<20)
-#define HID0_ICE (1<<HID0_ICE_SHIFT) /* Instruction Cache Enable */
-#define HID0_DCE (1<<HID0_DCE_SHIFT) /* Data Cache Enable */
-#define HID0_TBEN (1<<14) /* Time Base Enable */
-#define HID0_ILOCK (1<<13) /* Instruction Cache Lock */
-#define HID0_DLOCK (1<<HID0_DLOCK_SHIFT) /* Data Cache Lock */
-#define HID0_ICFI (1<<11) /* Instr. Cache Flash Invalidate */
-#define HID0_DCFI (1<<10) /* Data Cache Flash Invalidate */
-#define HID0_DCI HID0_DCFI
-#define HID0_SPD (1<<9) /* Speculative disable */
-#define HID0_ENMAS7 (1<<7) /* Enable MAS7 Update for 36-bit phys */
-#define HID0_SGE (1<<7) /* Store Gathering Enable */
-#define HID0_SIED HID_SGE /* Serial Instr. Execution [Disable] */
-#define HID0_DCFA (1<<6) /* Data Cache Flush Assist */
-#define HID0_BTIC (1<<5) /* Branch Target Instruction Cache Enable */
-#define HID0_ABE (1<<3) /* Address Broadcast Enable */
-#define HID0_BHTE (1<<2) /* Branch History Table Enable */
-#define HID0_BTCD (1<<1) /* Branch target cache disable */
-#define SPRN_HID1 0x3F1 /* Hardware Implementation Register 1 */
-#define HID1_RFXE (1<<17) /* Read Fault Exception Enable */
-#define HID1_ASTME (1<<13) /* Address bus streaming mode */
-#define HID1_ABE (1<<12) /* Address broadcast enable */
-#define SPRN_IABR 0x3F2 /* Instruction Address Breakpoint Register */
-#ifndef CONFIG_BOOKE
-#define SPRN_IAC1 0x3F4 /* Instruction Address Compare 1 */
-#define SPRN_IAC2 0x3F5 /* Instruction Address Compare 2 */
-#else
-#define SPRN_IAC1 0x138 /* Book E Instruction Address Compare 1 */
-#define SPRN_IAC2 0x139 /* Book E Instruction Address Compare 2 */
-#endif /* CONFIG_BOOKE */
-#define SPRN_IBAT0L 0x211 /* Instruction BAT 0 Lower Register */
-#define SPRN_IBAT0U 0x210 /* Instruction BAT 0 Upper Register */
-#define SPRN_IBAT1L 0x213 /* Instruction BAT 1 Lower Register */
-#define SPRN_IBAT1U 0x212 /* Instruction BAT 1 Upper Register */
-#define SPRN_IBAT2L 0x215 /* Instruction BAT 2 Lower Register */
-#define SPRN_IBAT2U 0x214 /* Instruction BAT 2 Upper Register */
-#define SPRN_IBAT3L 0x217 /* Instruction BAT 3 Lower Register */
-#define SPRN_IBAT3U 0x216 /* Instruction BAT 3 Upper Register */
-#define SPRN_IBAT4L 0x231 /* Instruction BAT 4 Lower Register */
-#define SPRN_IBAT4U 0x230 /* Instruction BAT 4 Upper Register */
-#define SPRN_IBAT5L 0x233 /* Instruction BAT 5 Lower Register */
-#define SPRN_IBAT5U 0x232 /* Instruction BAT 5 Upper Register */
-#define SPRN_IBAT6L 0x235 /* Instruction BAT 6 Lower Register */
-#define SPRN_IBAT6U 0x234 /* Instruction BAT 6 Upper Register */
-#define SPRN_IBAT7L 0x237 /* Instruction BAT 7 Lower Register */
-#define SPRN_IBAT7U 0x236 /* Instruction BAT 7 Upper Register */
-#define SPRN_ICCR 0x3FB /* Instruction Cache Cacheability Register */
-#define ICCR_NOCACHE 0 /* Noncacheable */
-#define ICCR_CACHE 1 /* Cacheable */
-#define SPRN_ICDBDR 0x3D3 /* Instruction Cache Debug Data Register */
-#ifdef CONFIG_BOOKE
-#define SPRN_ICDBTRL 0x39e /* instruction cache debug tag register low */
-#define SPRN_ICDBTRH 0x39f /* instruction cache debug tag register high */
-#endif
-#define SPRN_ICMP 0x3D5 /* Instruction TLB Compare Register */
-#define SPRN_ICTC 0x3FB /* Instruction Cache Throttling Control Reg */
-#define SPRN_IMISS 0x3D4 /* Instruction TLB Miss Register */
-#define SPRN_IMMR 0x27E /* Internal Memory Map Register */
-#ifdef CONFIG_BOOKE
-#define SPRN_INV0 0x370 /* Instruction Cache Normal Victim 0 */
-#define SPRN_INV1 0x371 /* Instruction Cache Normal Victim 1 */
-#define SPRN_INV2 0x372 /* Instruction Cache Normal Victim 2 */
-#define SPRN_INV3 0x373 /* Instruction Cache Normal Victim 3 */
-#define SPRN_ITV0 0x374 /* Instruction Cache Transient Victim 0 */
-#define SPRN_ITV1 0x375 /* Instruction Cache Transient Victim 1 */
-#define SPRN_ITV2 0x376 /* Instruction Cache Transient Victim 2 */
-#define SPRN_ITV3 0x377 /* Instruction Cache Transient Victim 3 */
-#define SPRN_IVLIM 0x399 /* Instruction Cache Victim Limit */
-#endif
-#define SPRN_LDSTCR 0x3F8 /* Load/Store Control Register */
-#define SPRN_L2CR 0x3F9 /* Level 2 Cache Control Regsiter */
-#define SPRN_LR 0x008 /* Link Register */
-#define SPRN_MBAR 0x137 /* System memory base address */
-#define SPRN_MMCR0 0x3B8 /* Monitor Mode Control Register 0 */
-#define SPRN_MMCR1 0x3BC /* Monitor Mode Control Register 1 */
-#ifdef CONFIG_BOOKE
-#define SPRN_MMUCR 0x3b2 /* MMU Control Register */
-#endif
-#define SPRN_PBL1 0x3FC /* Protection Bound Lower 1 */
-#define SPRN_PBL2 0x3FE /* Protection Bound Lower 2 */
-#define SPRN_PBU1 0x3FD /* Protection Bound Upper 1 */
-#define SPRN_PBU2 0x3FF /* Protection Bound Upper 2 */
-#ifndef CONFIG_BOOKE
-#define SPRN_PID 0x3B1 /* Process ID */
-#define SPRN_PIR 0x3FF /* Processor Identification Register */
-#else
-#define SPRN_PID 0x030 /* Book E Process ID */
-#define SPRN_PIR 0x11E /* Book E Processor Identification Register */
-#endif /* CONFIG_BOOKE */
-#define SPRN_PIT 0x3DB /* Programmable Interval Timer */
-#define SPRN_PMC1 0x3B9 /* Performance Counter Register 1 */
-#define SPRN_PMC2 0x3BA /* Performance Counter Register 2 */
-#define SPRN_PMC3 0x3BD /* Performance Counter Register 3 */
-#define SPRN_PMC4 0x3BE /* Performance Counter Register 4 */
-#define SPRN_PVR 0x11F /* Processor Version Register */
-#define SPRN_RPA 0x3D6 /* Required Physical Address Register */
-#ifdef CONFIG_BOOKE
-#define SPRN_RSTCFG 0x39b /* Reset Configuration */
-#endif
-#define SPRN_SDA 0x3BF /* Sampled Data Address Register */
-#define SPRN_SDR1 0x019 /* MMU Hash Base Register */
-#define SPRN_SGR 0x3B9 /* Storage Guarded Register */
-#define SGR_NORMAL 0
-#define SGR_GUARDED 1
-#define SPRN_SIA 0x3BB /* Sampled Instruction Address Register */
-#define SPRN_SPRG0 0x110 /* Special Purpose Register General 0 */
-#define SPRN_SPRG1 0x111 /* Special Purpose Register General 1 */
-#define SPRN_SPRG2 0x112 /* Special Purpose Register General 2 */
-#define SPRN_SPRG3 0x113 /* Special Purpose Register General 3 */
-#define SPRN_SPRG4 0x114 /* Special Purpose Register General 4 */
-#define SPRN_SPRG5 0x115 /* Special Purpose Register General 5 */
-#define SPRN_SPRG6 0x116 /* Special Purpose Register General 6 */
-#define SPRN_SPRG7 0x117 /* Special Purpose Register General 7 */
-#define SPRN_SRR0 0x01A /* Save/Restore Register 0 */
-#define SPRN_SRR1 0x01B /* Save/Restore Register 1 */
-#define SPRN_SRR2 0x3DE /* Save/Restore Register 2 */
-#define SPRN_SRR3 0x3DF /* Save/Restore Register 3 */
-
-#ifdef CONFIG_BOOKE
-#define SPRN_SVR 0x3FF /* System Version Register */
-#else
-#define SPRN_SVR 0x11E /* System Version Register */
-#endif
-#define SPRN_TBHI 0x3DC /* Time Base High */
-#define SPRN_TBHU 0x3CC /* Time Base High User-mode */
-#define SPRN_TBLO 0x3DD /* Time Base Low */
-#define SPRN_TBLU 0x3CD /* Time Base Low User-mode */
-#define SPRN_TBRL 0x10C /* Time Base Read Lower Register */
-#define SPRN_TBRU 0x10D /* Time Base Read Upper Register */
-#define SPRN_TBWL 0x11C /* Time Base Write Lower Register */
-#define SPRN_TBWU 0x11D /* Time Base Write Upper Register */
-#ifndef CONFIG_BOOKE
-#define SPRN_TCR 0x3DA /* Timer Control Register */
-#else
-#define SPRN_TCR 0x154 /* Book E Timer Control Register */
-#endif /* CONFIG_BOOKE */
-#define TCR_WP(x) (((x)&0x3)<<30) /* WDT Period */
-#define WP_2_17 0 /* 2^17 clocks */
-#define WP_2_21 1 /* 2^21 clocks */
-#define WP_2_25 2 /* 2^25 clocks */
-#define WP_2_29 3 /* 2^29 clocks */
-#define TCR_WRC(x) (((x)&0x3)<<28) /* WDT Reset Control */
-#define WRC_NONE 0 /* No reset will occur */
-#define WRC_CORE 1 /* Core reset will occur */
-#define WRC_CHIP 2 /* Chip reset will occur */
-#define WRC_SYSTEM 3 /* System reset will occur */
-#define TCR_WIE 0x08000000 /* WDT Interrupt Enable */
-#define TCR_PIE 0x04000000 /* PIT Interrupt Enable */
-#define TCR_FP(x) (((x)&0x3)<<24) /* FIT Period */
-#define FP_2_9 0 /* 2^9 clocks */
-#define FP_2_13 1 /* 2^13 clocks */
-#define FP_2_17 2 /* 2^17 clocks */
-#define FP_2_21 3 /* 2^21 clocks */
-#define TCR_FIE 0x00800000 /* FIT Interrupt Enable */
-#define TCR_ARE 0x00400000 /* Auto Reload Enable */
-#define SPRN_THRM1 0x3FC /* Thermal Management Register 1 */
-#define THRM1_TIN (1<<0)
-#define THRM1_TIV (1<<1)
-#define THRM1_THRES (0x7f<<2)
-#define THRM1_TID (1<<29)
-#define THRM1_TIE (1<<30)
-#define THRM1_V (1<<31)
-#define SPRN_THRM2 0x3FD /* Thermal Management Register 2 */
-#define SPRN_THRM3 0x3FE /* Thermal Management Register 3 */
-#define THRM3_E (1<<31)
-#define SPRN_TLBMISS 0x3D4 /* 980 7450 TLB Miss Register */
-#ifndef CONFIG_BOOKE
-#define SPRN_TSR 0x3D8 /* Timer Status Register */
-#else
-#define SPRN_TSR 0x150 /* Book E Timer Status Register */
-#endif /* CONFIG_BOOKE */
-#define TSR_ENW 0x80000000 /* Enable Next Watchdog */
-#define TSR_WIS 0x40000000 /* WDT Interrupt Status */
-#define TSR_WRS(x) (((x)&0x3)<<28) /* WDT Reset Status */
-#define WRS_NONE 0 /* No WDT reset occurred */
-#define WRS_CORE 1 /* WDT forced core reset */
-#define WRS_CHIP 2 /* WDT forced chip reset */
-#define WRS_SYSTEM 3 /* WDT forced system reset */
-#define TSR_PIS 0x08000000 /* PIT Interrupt Status */
-#define TSR_FIS 0x04000000 /* FIT Interrupt Status */
-#define SPRN_UMMCR0 0x3A8 /* User Monitor Mode Control Register 0 */
-#define SPRN_UMMCR1 0x3AC /* User Monitor Mode Control Register 0 */
-#define SPRN_UPMC1 0x3A9 /* User Performance Counter Register 1 */
-#define SPRN_UPMC2 0x3AA /* User Performance Counter Register 2 */
-#define SPRN_UPMC3 0x3AD /* User Performance Counter Register 3 */
-#define SPRN_UPMC4 0x3AE /* User Performance Counter Register 4 */
-#define SPRN_USIA 0x3AB /* User Sampled Instruction Address Register */
-#define SPRN_XER 0x001 /* Fixed Point Exception Register */
-#define SPRN_ZPR 0x3B0 /* Zone Protection Register */
-
-/* Book E definitions */
-#define SPRN_DECAR 0x036 /* Decrementer Auto Reload Register */
-#define SPRN_CSRR0 0x03A /* Critical SRR0 */
-#define SPRN_CSRR1 0x03B /* Critical SRR0 */
-#define SPRN_IVPR 0x03F /* Interrupt Vector Prefix Register */
-#define SPRN_USPRG0 0x100 /* User Special Purpose Register General 0 */
-#define SPRN_SPRG4R 0x104 /* Special Purpose Register General 4 Read */
-#define SPRN_SPRG5R 0x105 /* Special Purpose Register General 5 Read */
-#define SPRN_SPRG6R 0x106 /* Special Purpose Register General 6 Read */
-#define SPRN_SPRG7R 0x107 /* Special Purpose Register General 7 Read */
-#define SPRN_SPRG4W 0x114 /* Special Purpose Register General 4 Write */
-#define SPRN_SPRG5W 0x115 /* Special Purpose Register General 5 Write */
-#define SPRN_SPRG6W 0x116 /* Special Purpose Register General 6 Write */
-#define SPRN_SPRG7W 0x117 /* Special Purpose Register General 7 Write */
-#define SPRN_DBCR2 0x136 /* Debug Control Register 2 */
-#define SPRN_IAC3 0x13A /* Instruction Address Compare 3 */
-#define SPRN_IAC4 0x13B /* Instruction Address Compare 4 */
-#define SPRN_DVC1 0x13E /* Data Value Compare Register 1 */
-#define SPRN_DVC2 0x13F /* Data Value Compare Register 2 */
-#define SPRN_IVOR0 0x190 /* Interrupt Vector Offset Register 0 */
-#define SPRN_IVOR1 0x191 /* Interrupt Vector Offset Register 1 */
-#define SPRN_IVOR2 0x192 /* Interrupt Vector Offset Register 2 */
-#define SPRN_IVOR3 0x193 /* Interrupt Vector Offset Register 3 */
-#define SPRN_IVOR4 0x194 /* Interrupt Vector Offset Register 4 */
-#define SPRN_IVOR5 0x195 /* Interrupt Vector Offset Register 5 */
-#define SPRN_IVOR6 0x196 /* Interrupt Vector Offset Register 6 */
-#define SPRN_IVOR7 0x197 /* Interrupt Vector Offset Register 7 */
-#define SPRN_IVOR8 0x198 /* Interrupt Vector Offset Register 8 */
-#define SPRN_IVOR9 0x199 /* Interrupt Vector Offset Register 9 */
-#define SPRN_IVOR10 0x19a /* Interrupt Vector Offset Register 10 */
-#define SPRN_IVOR11 0x19b /* Interrupt Vector Offset Register 11 */
-#define SPRN_IVOR12 0x19c /* Interrupt Vector Offset Register 12 */
-#define SPRN_IVOR13 0x19d /* Interrupt Vector Offset Register 13 */
-#define SPRN_IVOR14 0x19e /* Interrupt Vector Offset Register 14 */
-#define SPRN_IVOR15 0x19f /* Interrupt Vector Offset Register 15 */
-
-/* e500 definitions */
-#define SPRN_L1CFG0 0x203 /* L1 Cache Configuration Register 0 */
-#define SPRN_L1CFG1 0x204 /* L1 Cache Configuration Register 1 */
-#define SPRN_L2CFG0 0x207 /* L2 Cache Configuration Register 0 */
-#define SPRN_L1CSR0 0x3f2 /* L1 Data Cache Control and Status Register 0 */
-#define L1CSR0_CPE 0x00010000 /* Data Cache Parity Enable */
-#define L1CSR0_DCFI 0x00000002 /* Data Cache Flash Invalidate */
-#define L1CSR0_DCE 0x00000001 /* Data Cache Enable */
-#define SPRN_L1CSR1 0x3f3 /* L1 Instruction Cache Control and Status Register 1 */
-#define L1CSR1_CPE 0x00010000 /* Instruction Cache Parity Enable */
-#define L1CSR1_ICFI 0x00000002 /* Instruction Cache Flash Invalidate */
-#define L1CSR1_ICE 0x00000001 /* Instruction Cache Enable */
-#define SPRN_L1CSR2 0x25e /* L1 Data Cache Control and Status Register 2 */
-#define SPRN_L2CSR0 0x3f9 /* L2 Data Cache Control and Status Register 0 */
-#define L2CSR0_L2E 0x80000000 /* L2 Cache Enable */
-#define L2CSR0_L2PE 0x40000000 /* L2 Cache Parity/ECC Enable */
-#define L2CSR0_L2WP 0x1c000000 /* L2 I/D Way Partioning */
-#define L2CSR0_L2CM 0x03000000 /* L2 Cache Coherency Mode */
-#define L2CSR0_L2FI 0x00200000 /* L2 Cache Flash Invalidate */
-#define L2CSR0_L2IO 0x00100000 /* L2 Cache Instruction Only */
-#define L2CSR0_L2DO 0x00010000 /* L2 Cache Data Only */
-#define L2CSR0_L2REP 0x00003000 /* L2 Line Replacement Algo */
-#define L2CSR0_L2FL 0x00000800 /* L2 Cache Flush */
-#define L2CSR0_L2LFC 0x00000400 /* L2 Cache Lock Flash Clear */
-#define L2CSR0_L2LOA 0x00000080 /* L2 Cache Lock Overflow Allocate */
-#define L2CSR0_L2LO 0x00000020 /* L2 Cache Lock Overflow */
-#define SPRN_L2CSR1 0x3fa /* L2 Data Cache Control and Status Register 1 */
-
-#define SPRN_TLB0CFG 0x2B0 /* TLB 0 Config Register */
-#define SPRN_TLB1CFG 0x2B1 /* TLB 1 Config Register */
-#define SPRN_MMUCSR0 0x3f4 /* MMU control and status register 0 */
-#define SPRN_MAS0 0x270 /* MMU Assist Register 0 */
-#define SPRN_MAS1 0x271 /* MMU Assist Register 1 */
-#define SPRN_MAS2 0x272 /* MMU Assist Register 2 */
-#define SPRN_MAS3 0x273 /* MMU Assist Register 3 */
-#define SPRN_MAS4 0x274 /* MMU Assist Register 4 */
-#define SPRN_MAS5 0x275 /* MMU Assist Register 5 */
-#define SPRN_MAS6 0x276 /* MMU Assist Register 6 */
-#define SPRN_MAS7 0x3B0 /* MMU Assist Register 7 */
-
-#define SPRN_IVOR32 0x210 /* Interrupt Vector Offset Register 32 */
-#define SPRN_IVOR33 0x211 /* Interrupt Vector Offset Register 33 */
-#define SPRN_IVOR34 0x212 /* Interrupt Vector Offset Register 34 */
-#define SPRN_IVOR35 0x213 /* Interrupt Vector Offset Register 35 */
-#define SPRN_SPEFSCR 0x200 /* SPE & Embedded FP Status & Control */
-
-#define SPRN_MCSRR0 0x23a /* Machine Check Save and Restore Register 0 */
-#define SPRN_MCSRR1 0x23b /* Machine Check Save and Restore Register 1 */
-#define SPRN_BUCSR 0x3f5 /* Branch Control and Status Register */
-#define SPRN_BBEAR 0x201 /* Branch Buffer Entry Address Register */
-#define SPRN_BBTAR 0x202 /* Branch Buffer Target Address Register */
-#define SPRN_PID1 0x279 /* Process ID Register 1 */
-#define SPRN_PID2 0x27a /* Process ID Register 2 */
-#define SPRN_MCSR 0x23c /* Machine Check Syndrome register */
-#define SPRN_MCAR 0x23d /* Machine Check Address register */
-#define MCSR_MCS 0x80000000 /* Machine Check Summary */
-#define MCSR_IB 0x40000000 /* Instruction PLB Error */
-#if defined(CONFIG_440)
-#define MCSR_DRB 0x20000000 /* Data Read PLB Error */
-#define MCSR_DWB 0x10000000 /* Data Write PLB Error */
-#else
-#define MCSR_DB 0x20000000 /* Data PLB Error */
-#endif /* defined(CONFIG_440) */
-#define MCSR_TLBP 0x08000000 /* TLB Parity Error */
-#define MCSR_ICP 0x04000000 /* I-Cache Parity Error */
-#define MCSR_DCSP 0x02000000 /* D-Cache Search Parity Error */
-#define MCSR_DCFP 0x01000000 /* D-Cache Flush Parity Error */
-#define MCSR_IMPE 0x00800000 /* Imprecise Machine Check Exception */
-#define ESR_ST 0x00800000 /* Store Operation */
-
-#if defined(CONFIG_MPC86xx)
-#define SPRN_MSSCR0 0x3f6
-#define SPRN_MSSSR0 0x3f7
-#endif
-
-/* Short-hand versions for a number of the above SPRNs */
-
-#define CTR SPRN_CTR /* Counter Register */
-#define DAR SPRN_DAR /* Data Address Register */
-#define DABR SPRN_DABR /* Data Address Breakpoint Register */
-#define DAC1 SPRN_DAC1 /* Data Address Register 1 */
-#define DAC2 SPRN_DAC2 /* Data Address Register 2 */
-#define DBAT0L SPRN_DBAT0L /* Data BAT 0 Lower Register */
-#define DBAT0U SPRN_DBAT0U /* Data BAT 0 Upper Register */
-#define DBAT1L SPRN_DBAT1L /* Data BAT 1 Lower Register */
-#define DBAT1U SPRN_DBAT1U /* Data BAT 1 Upper Register */
-#define DBAT2L SPRN_DBAT2L /* Data BAT 2 Lower Register */
-#define DBAT2U SPRN_DBAT2U /* Data BAT 2 Upper Register */
-#define DBAT3L SPRN_DBAT3L /* Data BAT 3 Lower Register */
-#define DBAT3U SPRN_DBAT3U /* Data BAT 3 Upper Register */
-#define DBAT4L SPRN_DBAT4L /* Data BAT 4 Lower Register */
-#define DBAT4U SPRN_DBAT4U /* Data BAT 4 Upper Register */
-#define DBAT5L SPRN_DBAT5L /* Data BAT 5 Lower Register */
-#define DBAT5U SPRN_DBAT5U /* Data BAT 5 Upper Register */
-#define DBAT6L SPRN_DBAT6L /* Data BAT 6 Lower Register */
-#define DBAT6U SPRN_DBAT6U /* Data BAT 6 Upper Register */
-#define DBAT7L SPRN_DBAT7L /* Data BAT 7 Lower Register */
-#define DBAT7U SPRN_DBAT7U /* Data BAT 7 Upper Register */
-#define DBCR0 SPRN_DBCR0 /* Debug Control Register 0 */
-#define DBCR1 SPRN_DBCR1 /* Debug Control Register 1 */
-#define DBSR SPRN_DBSR /* Debug Status Register */
-#define DCMP SPRN_DCMP /* Data TLB Compare Register */
-#define DEC SPRN_DEC /* Decrement Register */
-#define DMISS SPRN_DMISS /* Data TLB Miss Register */
-#define DSISR SPRN_DSISR /* Data Storage Interrupt Status Register */
-#define EAR SPRN_EAR /* External Address Register */
-#define ESR SPRN_ESR /* Exception Syndrome Register */
-#define HASH1 SPRN_HASH1 /* Primary Hash Address Register */
-#define HASH2 SPRN_HASH2 /* Secondary Hash Address Register */
-#define HID0 SPRN_HID0 /* Hardware Implementation Register 0 */
-#define HID1 SPRN_HID1 /* Hardware Implementation Register 1 */
-#define IABR SPRN_IABR /* Instruction Address Breakpoint Register */
-#define IAC1 SPRN_IAC1 /* Instruction Address Register 1 */
-#define IAC2 SPRN_IAC2 /* Instruction Address Register 2 */
-#define IBAT0L SPRN_IBAT0L /* Instruction BAT 0 Lower Register */
-#define IBAT0U SPRN_IBAT0U /* Instruction BAT 0 Upper Register */
-#define IBAT1L SPRN_IBAT1L /* Instruction BAT 1 Lower Register */
-#define IBAT1U SPRN_IBAT1U /* Instruction BAT 1 Upper Register */
-#define IBAT2L SPRN_IBAT2L /* Instruction BAT 2 Lower Register */
-#define IBAT2U SPRN_IBAT2U /* Instruction BAT 2 Upper Register */
-#define IBAT3L SPRN_IBAT3L /* Instruction BAT 3 Lower Register */
-#define IBAT3U SPRN_IBAT3U /* Instruction BAT 3 Upper Register */
-#define IBAT4L SPRN_IBAT4L /* Instruction BAT 4 Lower Register */
-#define IBAT4U SPRN_IBAT4U /* Instruction BAT 4 Upper Register */
-#define IBAT5L SPRN_IBAT5L /* Instruction BAT 5 Lower Register */
-#define IBAT5U SPRN_IBAT5U /* Instruction BAT 5 Upper Register */
-#define IBAT6L SPRN_IBAT6L /* Instruction BAT 6 Lower Register */
-#define IBAT6U SPRN_IBAT6U /* Instruction BAT 6 Upper Register */
-#define IBAT7L SPRN_IBAT7L /* Instruction BAT 7 Lower Register */
-#define IBAT7U SPRN_IBAT7U /* Instruction BAT 7 Lower Register */
-#define ICMP SPRN_ICMP /* Instruction TLB Compare Register */
-#define IMISS SPRN_IMISS /* Instruction TLB Miss Register */
-#define IMMR SPRN_IMMR /* PPC 860/821 Internal Memory Map Register */
-#define LDSTCR SPRN_LDSTCR /* Load/Store Control Register */
-#define L2CR SPRN_L2CR /* PPC 750 L2 control register */
-#define LR SPRN_LR
-#define MBAR SPRN_MBAR /* System memory base address */
-#if defined(CONFIG_MPC86xx)
-#define MSSCR0 SPRN_MSSCR0
-#endif
-#if defined(CONFIG_E500) || defined(CONFIG_MPC86xx)
-#define PIR SPRN_PIR
-#endif
-#define SVR SPRN_SVR /* System-On-Chip Version Register */
-#define PVR SPRN_PVR /* Processor Version */
-#define RPA SPRN_RPA /* Required Physical Address Register */
-#define SDR1 SPRN_SDR1 /* MMU hash base register */
-#define SPR0 SPRN_SPRG0 /* Supervisor Private Registers */
-#define SPR1 SPRN_SPRG1
-#define SPR2 SPRN_SPRG2
-#define SPR3 SPRN_SPRG3
-#define SPRG0 SPRN_SPRG0
-#define SPRG1 SPRN_SPRG1
-#define SPRG2 SPRN_SPRG2
-#define SPRG3 SPRN_SPRG3
-#define SPRG4 SPRN_SPRG4
-#define SPRG5 SPRN_SPRG5
-#define SPRG6 SPRN_SPRG6
-#define SPRG7 SPRN_SPRG7
-#define SRR0 SPRN_SRR0 /* Save and Restore Register 0 */
-#define SRR1 SPRN_SRR1 /* Save and Restore Register 1 */
-#define SRR2 SPRN_SRR2 /* Save and Restore Register 2 */
-#define SRR3 SPRN_SRR3 /* Save and Restore Register 3 */
-#define SVR SPRN_SVR /* System Version Register */
-#define TBRL SPRN_TBRL /* Time Base Read Lower Register */
-#define TBRU SPRN_TBRU /* Time Base Read Upper Register */
-#define TBWL SPRN_TBWL /* Time Base Write Lower Register */
-#define TBWU SPRN_TBWU /* Time Base Write Upper Register */
-#define TCR SPRN_TCR /* Timer Control Register */
-#define TSR SPRN_TSR /* Timer Status Register */
-#define ICTC 1019
-#define THRM1 SPRN_THRM1 /* Thermal Management Register 1 */
-#define THRM2 SPRN_THRM2 /* Thermal Management Register 2 */
-#define THRM3 SPRN_THRM3 /* Thermal Management Register 3 */
-#define XER SPRN_XER
-
-#define DECAR SPRN_DECAR
-#define CSRR0 SPRN_CSRR0
-#define CSRR1 SPRN_CSRR1
-#define IVPR SPRN_IVPR
-#define USPRG0 SPRN_USPRG
-#define SPRG4R SPRN_SPRG4R
-#define SPRG5R SPRN_SPRG5R
-#define SPRG6R SPRN_SPRG6R
-#define SPRG7R SPRN_SPRG7R
-#define SPRG4W SPRN_SPRG4W
-#define SPRG5W SPRN_SPRG5W
-#define SPRG6W SPRN_SPRG6W
-#define SPRG7W SPRN_SPRG7W
-#define DEAR SPRN_DEAR
-#define DBCR2 SPRN_DBCR2
-#define IAC3 SPRN_IAC3
-#define IAC4 SPRN_IAC4
-#define DVC1 SPRN_DVC1
-#define DVC2 SPRN_DVC2
-#define IVOR0 SPRN_IVOR0
-#define IVOR1 SPRN_IVOR1
-#define IVOR2 SPRN_IVOR2
-#define IVOR3 SPRN_IVOR3
-#define IVOR4 SPRN_IVOR4
-#define IVOR5 SPRN_IVOR5
-#define IVOR6 SPRN_IVOR6
-#define IVOR7 SPRN_IVOR7
-#define IVOR8 SPRN_IVOR8
-#define IVOR9 SPRN_IVOR9
-#define IVOR10 SPRN_IVOR10
-#define IVOR11 SPRN_IVOR11
-#define IVOR12 SPRN_IVOR12
-#define IVOR13 SPRN_IVOR13
-#define IVOR14 SPRN_IVOR14
-#define IVOR15 SPRN_IVOR15
-#define IVOR32 SPRN_IVOR32
-#define IVOR33 SPRN_IVOR33
-#define IVOR34 SPRN_IVOR34
-#define IVOR35 SPRN_IVOR35
-#define MCSRR0 SPRN_MCSRR0
-#define MCSRR1 SPRN_MCSRR1
-#define L1CSR0 SPRN_L1CSR0
-#define L1CSR1 SPRN_L1CSR1
-#define L1CSR2 SPRN_L1CSR2
-#define L1CFG0 SPRN_L1CFG0
-#define L1CFG1 SPRN_L1CFG1
-#define L2CFG0 SPRN_L2CFG0
-#define L2CSR0 SPRN_L2CSR0
-#define L2CSR1 SPRN_L2CSR1
-#define MCSR SPRN_MCSR
-#define MMUCSR0 SPRN_MMUCSR0
-#define BUCSR SPRN_BUCSR
-#define PID0 SPRN_PID
-#define PID1 SPRN_PID1
-#define PID2 SPRN_PID2
-#define MAS0 SPRN_MAS0
-#define MAS1 SPRN_MAS1
-#define MAS2 SPRN_MAS2
-#define MAS3 SPRN_MAS3
-#define MAS4 SPRN_MAS4
-#define MAS5 SPRN_MAS5
-#define MAS6 SPRN_MAS6
-#define MAS7 SPRN_MAS7
-
-#if defined(CONFIG_4xx) || defined(CONFIG_44x) || defined(CONFIG_MPC85xx)
-#define DAR_DEAR DEAR
-#else
-#define DAR_DEAR DAR
-#endif
-
-/* Device Control Registers */
-
-#define DCRN_BEAR 0x090 /* Bus Error Address Register */
-#define DCRN_BESR 0x091 /* Bus Error Syndrome Register */
-#define BESR_DSES 0x80000000 /* Data-Side Error Status */
-#define BESR_DMES 0x40000000 /* DMA Error Status */
-#define BESR_RWS 0x20000000 /* Read/Write Status */
-#define BESR_ETMASK 0x1C000000 /* Error Type */
-#define ET_PROT 0
-#define ET_PARITY 1
-#define ET_NCFG 2
-#define ET_BUSERR 4
-#define ET_BUSTO 6
-#define DCRN_DMACC0 0x0C4 /* DMA Chained Count Register 0 */
-#define DCRN_DMACC1 0x0CC /* DMA Chained Count Register 1 */
-#define DCRN_DMACC2 0x0D4 /* DMA Chained Count Register 2 */
-#define DCRN_DMACC3 0x0DC /* DMA Chained Count Register 3 */
-#define DCRN_DMACR0 0x0C0 /* DMA Channel Control Register 0 */
-#define DCRN_DMACR1 0x0C8 /* DMA Channel Control Register 1 */
-#define DCRN_DMACR2 0x0D0 /* DMA Channel Control Register 2 */
-#define DCRN_DMACR3 0x0D8 /* DMA Channel Control Register 3 */
-#define DCRN_DMACT0 0x0C1 /* DMA Count Register 0 */
-#define DCRN_DMACT1 0x0C9 /* DMA Count Register 1 */
-#define DCRN_DMACT2 0x0D1 /* DMA Count Register 2 */
-#define DCRN_DMACT3 0x0D9 /* DMA Count Register 3 */
-#define DCRN_DMADA0 0x0C2 /* DMA Destination Address Register 0 */
-#define DCRN_DMADA1 0x0CA /* DMA Destination Address Register 1 */
-#define DCRN_DMADA2 0x0D2 /* DMA Destination Address Register 2 */
-#define DCRN_DMADA3 0x0DA /* DMA Destination Address Register 3 */
-#define DCRN_DMASA0 0x0C3 /* DMA Source Address Register 0 */
-#define DCRN_DMASA1 0x0CB /* DMA Source Address Register 1 */
-#define DCRN_DMASA2 0x0D3 /* DMA Source Address Register 2 */
-#define DCRN_DMASA3 0x0DB /* DMA Source Address Register 3 */
-#define DCRN_DMASR 0x0E0 /* DMA Status Register */
-#define DCRN_EXIER 0x042 /* External Interrupt Enable Register */
-#define EXIER_CIE 0x80000000 /* Critical Interrupt Enable */
-#define EXIER_SRIE 0x08000000 /* Serial Port Rx Int. Enable */
-#define EXIER_STIE 0x04000000 /* Serial Port Tx Int. Enable */
-#define EXIER_JRIE 0x02000000 /* JTAG Serial Port Rx Int. Enable */
-#define EXIER_JTIE 0x01000000 /* JTAG Serial Port Tx Int. Enable */
-#define EXIER_D0IE 0x00800000 /* DMA Channel 0 Interrupt Enable */
-#define EXIER_D1IE 0x00400000 /* DMA Channel 1 Interrupt Enable */
-#define EXIER_D2IE 0x00200000 /* DMA Channel 2 Interrupt Enable */
-#define EXIER_D3IE 0x00100000 /* DMA Channel 3 Interrupt Enable */
-#define EXIER_E0IE 0x00000010 /* External Interrupt 0 Enable */
-#define EXIER_E1IE 0x00000008 /* External Interrupt 1 Enable */
-#define EXIER_E2IE 0x00000004 /* External Interrupt 2 Enable */
-#define EXIER_E3IE 0x00000002 /* External Interrupt 3 Enable */
-#define EXIER_E4IE 0x00000001 /* External Interrupt 4 Enable */
-#define DCRN_EXISR 0x040 /* External Interrupt Status Register */
-#define DCRN_IOCR 0x0A0 /* Input/Output Configuration Register */
-#define IOCR_E0TE 0x80000000
-#define IOCR_E0LP 0x40000000
-#define IOCR_E1TE 0x20000000
-#define IOCR_E1LP 0x10000000
-#define IOCR_E2TE 0x08000000
-#define IOCR_E2LP 0x04000000
-#define IOCR_E3TE 0x02000000
-#define IOCR_E3LP 0x01000000
-#define IOCR_E4TE 0x00800000
-#define IOCR_E4LP 0x00400000
-#define IOCR_EDT 0x00080000
-#define IOCR_SOR 0x00040000
-#define IOCR_EDO 0x00008000
-#define IOCR_2XC 0x00004000
-#define IOCR_ATC 0x00002000
-#define IOCR_SPD 0x00001000
-#define IOCR_BEM 0x00000800
-#define IOCR_PTD 0x00000400
-#define IOCR_ARE 0x00000080
-#define IOCR_DRC 0x00000020
-#define IOCR_RDM(x) (((x) & 0x3) << 3)
-#define IOCR_TCS 0x00000004
-#define IOCR_SCS 0x00000002
-#define IOCR_SPC 0x00000001
-
-/* System-On-Chip Version Register */
-
-/* System-On-Chip Version Register (SVR) field extraction */
-
-#define SVR_VER(svr) (((svr) >> 16) & 0xFFFF) /* Version field */
-#define SVR_REV(svr) (((svr) >> 0) & 0xFFFF) /* Revision field */
-
-#define SVR_CID(svr) (((svr) >> 28) & 0x0F) /* Company or manufacturer ID */
-#define SVR_SOCOP(svr) (((svr) >> 22) & 0x3F) /* SOC integration options */
-#define SVR_SID(svr) (((svr) >> 16) & 0x3F) /* SOC ID */
-#define SVR_PROC(svr) (((svr) >> 12) & 0x0F) /* Process revision field */
-#define SVR_MFG(svr) (((svr) >> 8) & 0x0F) /* Manufacturing revision */
-#define SVR_MJREV(svr) (((svr) >> 4) & 0x0F) /* Major SOC design revision indicator */
-#define SVR_MNREV(svr) (((svr) >> 0) & 0x0F) /* Minor SOC design revision indicator */
-
-/* Processor Version Register */
-
-/* Processor Version Register (PVR) field extraction */
-
-#define PVR_VER(pvr) (((pvr) >> 16) & 0xFFFF) /* Version field */
-#define PVR_REV(pvr) (((pvr) >> 0) & 0xFFFF) /* Revison field */
-
-/*
- * AMCC has further subdivided the standard PowerPC 16-bit version and
- * revision subfields of the PVR for the PowerPC 403s into the following:
- */
-
-#define PVR_FAM(pvr) (((pvr) >> 20) & 0xFFF) /* Family field */
-#define PVR_MEM(pvr) (((pvr) >> 16) & 0xF) /* Member field */
-#define PVR_CORE(pvr) (((pvr) >> 12) & 0xF) /* Core field */
-#define PVR_CFG(pvr) (((pvr) >> 8) & 0xF) /* Configuration field */
-#define PVR_MAJ(pvr) (((pvr) >> 4) & 0xF) /* Major revision field */
-#define PVR_MIN(pvr) (((pvr) >> 0) & 0xF) /* Minor revision field */
-
-/* e600 core PVR fields */
-
-#define PVR_E600_VER(pvr) (((pvr) >> 15) & 0xFFFF) /* Version/type */
-#define PVR_E600_TECH(pvr) (((pvr) >> 12) & 0xF) /* Technology */
-#define PVR_E600_MAJ(pvr) (((pvr) >> 8) & 0xF) /* Major revision */
-#define PVR_E600_MIN(pvr) (((pvr) >> 0) & 0xFF) /* Minor revision */
-
-/* Processor Version Numbers */
-
-#define PVR_403GA 0x00200000
-#define PVR_403GB 0x00200100
-#define PVR_403GC 0x00200200
-#define PVR_403GCX 0x00201400
-#define PVR_405GP 0x40110000
-#define PVR_405GP_RB 0x40110040
-#define PVR_405GP_RC 0x40110082
-#define PVR_405GP_RD 0x401100C4
-#define PVR_405GP_RE 0x40110145 /* same as pc405cr rev c */
-#define PVR_405CR_RA 0x40110041
-#define PVR_405CR_RB 0x401100C5
-#define PVR_405CR_RC 0x40110145 /* same as pc405gp rev e */
-#define PVR_405EP_RA 0x51210950
-#define PVR_405GPR_RB 0x50910951
-#define PVR_405EZ_RA 0x41511460
-#define PVR_405EXR1_RA 0x12911473 /* 405EXr rev A/B with Security */
-#define PVR_405EXR2_RA 0x12911471 /* 405EXr rev A/B without Security */
-#define PVR_405EX1_RA 0x12911477 /* 405EX rev A/B with Security */
-#define PVR_405EX2_RA 0x12911475 /* 405EX rev A/B without Security */
-#define PVR_405EXR1_RC 0x1291147B /* 405EXr rev C with Security */
-#define PVR_405EXR2_RC 0x12911479 /* 405EXr rev C without Security */
-#define PVR_405EX1_RC 0x1291147F /* 405EX rev C with Security */
-#define PVR_405EX2_RC 0x1291147D /* 405EX rev C without Security */
-#define PVR_440GP_RB 0x40120440
-#define PVR_440GP_RC 0x40120481
-#define PVR_440EP_RA 0x42221850
-#define PVR_440EP_RB 0x422218D3 /* 440EP rev B and 440GR rev A have same PVR */
-#define PVR_440EP_RC 0x422218D4 /* 440EP rev C and 440GR rev B have same PVR */
-#define PVR_440GR_RA 0x422218D3 /* 440EP rev B and 440GR rev A have same PVR */
-#define PVR_440GR_RB 0x422218D4 /* 440EP rev C and 440GR rev B have same PVR */
-#define PVR_440EPX1_RA 0x216218D0 /* 440EPX rev A with Security / Kasumi */
-#define PVR_440EPX2_RA 0x216218D4 /* 440EPX rev A without Security / Kasumi */
-#define PVR_440GRX1_RA 0x216218D0 /* 440GRX rev A with Security / Kasumi */
-#define PVR_440GRX2_RA 0x216218D4 /* 440GRX rev A without Security / Kasumi */
-#define PVR_440GX_RA 0x51B21850
-#define PVR_440GX_RB 0x51B21851
-#define PVR_440GX_RC 0x51B21892
-#define PVR_440GX_RF 0x51B21894
-#define PVR_405EP_RB 0x51210950
-#define PVR_440SP_6_RAB 0x53221850 /* 440SP rev A&B with RAID 6 support enabled */
-#define PVR_440SP_RAB 0x53321850 /* 440SP rev A&B without RAID 6 support */
-#define PVR_440SP_6_RC 0x53221891 /* 440SP rev C with RAID 6 support enabled */
-#define PVR_440SP_RC 0x53321891 /* 440SP rev C without RAID 6 support */
-#define PVR_440SPe_6_RA 0x53421890 /* 440SPe rev A with RAID 6 support enabled */
-#define PVR_440SPe_RA 0x53521890 /* 440SPe rev A without RAID 6 support */
-#define PVR_440SPe_6_RB 0x53421891 /* 440SPe rev B with RAID 6 support enabled */
-#define PVR_440SPe_RB 0x53521891 /* 440SPe rev B without RAID 6 support */
-#define PVR_460EX_SE_RA 0x130218A2 /* 460EX rev A with Security Engine */
-#define PVR_460EX_RA 0x130218A3 /* 460EX rev A without Security Engine */
-#define PVR_460GT_SE_RA 0x130218A0 /* 460GT rev A with Security Engine */
-#define PVR_460GT_RA 0x130218A1 /* 460GT rev A without Security Engine */
-#define PVR_460SX_RA 0x13541800 /* 460SX rev A */
-#define PVR_460SX_RA_V1 0x13541801 /* 460SX rev A Variant 1 Security disabled */
-#define PVR_460GX_RA 0x13541802 /* 460GX rev A */
-#define PVR_460GX_RA_V1 0x13541803 /* 460GX rev A Variant 1 Security disabled */
-#define PVR_601 0x00010000
-#define PVR_602 0x00050000
-#define PVR_603 0x00030000
-#define PVR_603e 0x00060000
-#define PVR_603ev 0x00070000
-#define PVR_603r 0x00071000
-#define PVR_604 0x00040000
-#define PVR_604e 0x00090000
-#define PVR_604r 0x000A0000
-#define PVR_620 0x00140000
-#define PVR_740 0x00080000
-#define PVR_750 PVR_740
-#define PVR_740P 0x10080000
-#define PVR_750P PVR_740P
-#define PVR_7400 0x000C0000
-#define PVR_7410 0x800C0000
-#define PVR_7450 0x80000000
-
-#define PVR_85xx 0x80200000
-#define PVR_85xx_REV1 (PVR_85xx | 0x0010)
-#define PVR_85xx_REV2 (PVR_85xx | 0x0020)
-
-#define PVR_86xx 0x80040000
-
-#define PVR_VIRTEX5 0x7ff21912
-
-/*
- * For the 8xx processors, all of them report the same PVR family for
- * the PowerPC core. The various versions of these processors must be
- * differentiated by the version number in the Communication Processor
- * Module (CPM).
- */
-#define PVR_821 0x00500000
-#define PVR_823 PVR_821
-#define PVR_850 PVR_821
-#define PVR_860 PVR_821
-#define PVR_7400 0x000C0000
-#define PVR_8240 0x00810100
-
-/*
- * PowerQUICC II family processors report different PVR values depending
- * on silicon process (HiP3, HiP4, HiP7, etc.)
- */
-#define PVR_8260 PVR_8240
-#define PVR_8260_HIP3 0x00810101
-#define PVR_8260_HIP4 0x80811014
-#define PVR_8260_HIP7 0x80822011
-#define PVR_8260_HIP7R1 0x80822013
-#define PVR_8260_HIP7RA 0x80822014
-
-/*
- * MPC 52xx
- */
-#define PVR_5200 0x80822011
-#define PVR_5200B 0x80822014
-
-/*
- * System Version Register
- */
-
-/* System Version Register (SVR) field extraction */
-
-#define SVR_VER(svr) (((svr) >> 16) & 0xFFFF) /* Version field */
-#define SVR_REV(svr) (((svr) >> 0) & 0xFFFF) /* Revison field */
-
-#define SVR_SUBVER(svr) (((svr) >> 8) & 0xFF) /* Process/MFG sub-version */
-
-#define SVR_FAM(svr) (((svr) >> 20) & 0xFFF) /* Family field */
-#define SVR_MEM(svr) (((svr) >> 16) & 0xF) /* Member field */
-
-#define SVR_MAJ(svr) (((svr) >> 4) & 0xF) /* Major revision field*/
-#define SVR_MIN(svr) (((svr) >> 0) & 0xF) /* Minor revision field*/
-
-/* Some parts define SVR[0:23] as the SOC version */
-#define SVR_SOC_VER(svr) (((svr) >> 8) & 0xFFFFFF) /* SOC Version fields */
-
-/* whether MPC8xxxE (i.e. has SEC) */
-#if defined(CONFIG_MPC85xx)
-#define IS_E_PROCESSOR(svr) (svr & 0x80000)
-#else
-#if defined(CONFIG_MPC83xx)
-#define IS_E_PROCESSOR(spridr) (!(spridr & 0x00010000))
-#endif
-#endif
-
-/*
- * SVR_SOC_VER() Version Values
- */
-
-#define SVR_8533 0x803400
-#define SVR_8533_E 0x803C00
-#define SVR_8535 0x803701
-#define SVR_8535_E 0x803F01
-#define SVR_8536 0x803700
-#define SVR_8536_E 0x803F00
-#define SVR_8540 0x803000
-#define SVR_8541 0x807200
-#define SVR_8541_E 0x807A00
-#define SVR_8543 0x803200
-#define SVR_8543_E 0x803A00
-#define SVR_8544 0x803401
-#define SVR_8544_E 0x803C01
-#define SVR_8545 0x803102
-#define SVR_8545_E 0x803902
-#define SVR_8547_E 0x803901
-#define SVR_8548 0x803100
-#define SVR_8548_E 0x803900
-#define SVR_8555 0x807100
-#define SVR_8555_E 0x807900
-#define SVR_8560 0x807000
-#define SVR_8567 0x807600
-#define SVR_8567_E 0x807E00
-#define SVR_8568 0x807500
-#define SVR_8568_E 0x807D00
-#define SVR_8569 0x808000
-#define SVR_8569_E 0x808800
-#define SVR_8572 0x80E000
-#define SVR_8572_E 0x80E800
-#define SVR_P2020 0x80E200
-#define SVR_P2020_E 0x80EA00
-
-#define SVR_8610 0x80A000
-#define SVR_8641 0x809000
-#define SVR_8641D 0x809001
-
-#define _GLOBAL(n)\
- .globl n;\
-n:
-
-/* Macros for setting and retrieving special purpose registers */
-
-#define stringify(s) tostring(s)
-#define tostring(s) #s
-
-#define mfdcr(rn) ({unsigned int rval; \
- asm volatile("mfdcr %0," stringify(rn) \
- : "=r" (rval)); rval;})
-#define mtdcr(rn, v) asm volatile("mtdcr " stringify(rn) ",%0" : : "r" (v))
-
-#define mfmsr() ({unsigned int rval; \
- asm volatile("mfmsr %0" : "=r" (rval)); rval;})
-#define mtmsr(v) asm volatile("mtmsr %0" : : "r" (v))
-
-#define mfspr(rn) ({unsigned int rval; \
- asm volatile("mfspr %0," stringify(rn) \
- : "=r" (rval)); rval;})
-#define mtspr(rn, v) asm volatile("mtspr " stringify(rn) ",%0" : : "r" (v))
-
-#define tlbie(v) asm volatile("tlbie %0 \n sync" : : "r" (v))
-
-/* Segment Registers */
-
-#define SR0 0
-#define SR1 1
-#define SR2 2
-#define SR3 3
-#define SR4 4
-#define SR5 5
-#define SR6 6
-#define SR7 7
-#define SR8 8
-#define SR9 9
-#define SR10 10
-#define SR11 11
-#define SR12 12
-#define SR13 13
-#define SR14 14
-#define SR15 15
-
-#ifndef __ASSEMBLY__
-
-struct cpu_type {
- char name[15];
- u32 soc_ver;
-};
-
-struct cpu_type *identify_cpu(u32 ver);
-
-#if defined(CONFIG_MPC85xx) || defined(CONFIG_MPC86xx)
-#define CPU_TYPE_ENTRY(n, v) \
- { .name = #n, .soc_ver = SVR_##v, }
-#else
-#if defined(CONFIG_MPC83xx)
-#define CPU_TYPE_ENTRY(x) {#x, SPR_##x}
-#endif
-#endif
-
-
-#ifndef CONFIG_MACH_SPECIFIC
-extern int _machine;
-extern int have_of;
-#endif /* CONFIG_MACH_SPECIFIC */
-
-/* what kind of prep workstation we are */
-extern int _prep_type;
-/*
- * This is used to identify the board type from a given PReP board
- * vendor. Board revision is also made available.
- */
-extern unsigned char ucSystemType;
-extern unsigned char ucBoardRev;
-extern unsigned char ucBoardRevMaj, ucBoardRevMin;
-
-struct task_struct;
-void start_thread(struct pt_regs *regs, unsigned long nip, unsigned long sp);
-void release_thread(struct task_struct *);
-
-/*
- * Create a new kernel thread.
- */
-extern long kernel_thread(int (*fn)(void *), void *arg, unsigned long flags);
-
-/*
- * Bus types
- */
-#define EISA_bus 0
-#define EISA_bus__is_a_macro /* for versions in ksyms.c */
-#define MCA_bus 0
-#define MCA_bus__is_a_macro /* for versions in ksyms.c */
-
-/* Lazy FPU handling on uni-processor */
-extern struct task_struct *last_task_used_math;
-extern struct task_struct *last_task_used_altivec;
-
-/*
- * this is the minimum allowable io space due to the location
- * of the io areas on prep (first one at 0x80000000) but
- * as soon as I get around to remapping the io areas with the BATs
- * to match the mac we can raise this. -- Cort
- */
-#define TASK_SIZE (0x80000000UL)
-
-/* This decides where the kernel will search for a free chunk of vm
- * space during mmap's.
- */
-#define TASK_UNMAPPED_BASE (TASK_SIZE / 8 * 3)
-
-typedef struct {
- unsigned long seg;
-} mm_segment_t;
-
-struct thread_struct {
- unsigned long ksp; /* Kernel stack pointer */
- unsigned long wchan; /* Event task is sleeping on */
- struct pt_regs *regs; /* Pointer to saved register state */
- mm_segment_t fs; /* for get_fs() validation */
- void *pgdir; /* root of page-table tree */
- signed long last_syscall;
- double fpr[32]; /* Complete floating point set */
- unsigned long fpscr_pad; /* fpr ... fpscr must be contiguous */
- unsigned long fpscr; /* Floating point status */
-#ifdef CONFIG_ALTIVEC
- vector128 vr[32]; /* Complete AltiVec set */
- vector128 vscr; /* AltiVec status */
- unsigned long vrsave;
-#endif /* CONFIG_ALTIVEC */
-};
-
-#define INIT_SP (sizeof(init_stack) + (unsigned long) &init_stack)
-
-#define INIT_THREAD { \
- INIT_SP, /* ksp */ \
- 0, /* wchan */ \
- (struct pt_regs *)INIT_SP - 1, /* regs */ \
- KERNEL_DS, /*fs*/ \
- swapper_pg_dir, /* pgdir */ \
- 0, /* last_syscall */ \
- {0}, 0, 0 \
-}
-
-/*
- * Note: the vm_start and vm_end fields here should *not*
- * be in kernel space. (Could vm_end == vm_start perhaps?)
- */
-#define INIT_MMAP { &init_mm, 0, 0x1000, NULL, \
- PAGE_SHARED, VM_READ | VM_WRITE | VM_EXEC, \
- 1, NULL, NULL }
-
-/*
- * Return saved PC of a blocked thread. For now, this is the "user" PC
- */
-static inline unsigned long thread_saved_pc(struct thread_struct *t)
-{
- return (t->regs) ? t->regs->nip : 0;
-}
-
-#define copy_segments(tsk, mm) do { } while (0)
-#define release_segments(mm) do { } while (0)
-#define forget_segments() do { } while (0)
-
-unsigned long get_wchan(struct task_struct *p);
-
-#define KSTK_EIP(tsk) ((tsk)->thread.regs->nip)
-#define KSTK_ESP(tsk) ((tsk)->thread.regs->gpr[1])
-
-/*
- * NOTE! The task struct and the stack go together
- */
-#define THREAD_SIZE (2*PAGE_SIZE)
-#define alloc_task_struct() \
- ((struct task_struct *) __get_free_pages(GFP_KERNEL,1))
-#define free_task_struct(p) free_pages((unsigned long)(p),1)
-#define get_task_struct(tsk) atomic_inc(&mem_map[MAP_NR(tsk)].count)
-
-/* in process.c - for early bootup debug -- Cort */
-int ll_printk(const char *, ...);
-void ll_puts(const char *);
-
-#define init_task (init_task_union.task)
-#define init_stack (init_task_union.stack)
-
-/* In misc.c */
-void _nmask_and_or_msr(unsigned long nmask, unsigned long or_val);
-
-#endif /* ndef ASSEMBLY*/
-
-#ifdef CONFIG_MACH_SPECIFIC
-#if defined(CONFIG_8xx)
-#define _machine _MACH_8xx
-#define have_of 0
-#elif defined(CONFIG_OAK)
-#define _machine _MACH_oak
-#define have_of 0
-#elif defined(CONFIG_WALNUT)
-#define _machine _MACH_walnut
-#define have_of 0
-#elif defined(CONFIG_APUS)
-#define _machine _MACH_apus
-#define have_of 0
-#elif defined(CONFIG_GEMINI)
-#define _machine _MACH_gemini
-#define have_of 0
-#elif defined(CONFIG_8260)
-#define _machine _MACH_8260
-#define have_of 0
-#elif defined(CONFIG_SANDPOINT)
-#define _machine _MACH_sandpoint
-#elif defined(CONFIG_HIDDEN_DRAGON)
-#define _machine _MACH_hidden_dragon
-#define have_of 0
-#else
-#error "Machine not defined correctly"
-#endif
-#endif /* CONFIG_MACH_SPECIFIC */
-
-#endif /* __ASM_PPC_PROCESSOR_H */
+#ifndef __ASM_PPC_PROCESSOR_H +#define __ASM_PPC_PROCESSOR_H + +/* + * Default implementation of macro that returns current + * instruction pointer ("program counter"). + */ +#define current_text_addr() ({ __label__ _l; _l: &&_l;}) + +#include <config.h> + +#include <asm/ptrace.h> +#include <asm/types.h> + +/* Machine State Register (MSR) Fields */ + +#ifdef CONFIG_PPC64BRIDGE +#define MSR_SF (1<<63) +#define MSR_ISF (1<<61) +#endif /* CONFIG_PPC64BRIDGE */ +#define MSR_UCLE (1<<26) /* User-mode cache lock enable (e500) */ +#define MSR_VEC (1<<25) /* Enable AltiVec(74xx) */ +#define MSR_SPE (1<<25) /* Enable SPE(e500) */ +#define MSR_POW (1<<18) /* Enable Power Management */ +#define MSR_WE (1<<18) /* Wait State Enable */ +#define MSR_TGPR (1<<17) /* TLB Update registers in use */ +#define MSR_CE (1<<17) /* Critical Interrupt Enable */ +#define MSR_ILE (1<<16) /* Interrupt Little Endian */ +#define MSR_EE (1<<15) /* External Interrupt Enable */ +#define MSR_PR (1<<14) /* Problem State / Privilege Level */ +#define MSR_FP (1<<13) /* Floating Point enable */ +#define MSR_ME (1<<12) /* Machine Check Enable */ +#define MSR_FE0 (1<<11) /* Floating Exception mode 0 */ +#define MSR_SE (1<<10) /* Single Step */ +#define MSR_DWE (1<<10) /* Debug Wait Enable (4xx) */ +#define MSR_UBLE (1<<10) /* BTB lock enable (e500) */ +#define MSR_BE (1<<9) /* Branch Trace */ +#define MSR_DE (1<<9) /* Debug Exception Enable */ +#define MSR_FE1 (1<<8) /* Floating Exception mode 1 */ +#define MSR_IP (1<<6) /* Exception prefix 0x000/0xFFF */ +#define MSR_IR (1<<5) /* Instruction Relocate */ +#define MSR_IS (1<<5) /* Book E Instruction space */ +#define MSR_DR (1<<4) /* Data Relocate */ +#define MSR_DS (1<<4) /* Book E Data space */ +#define MSR_PE (1<<3) /* Protection Enable */ +#define MSR_PX (1<<2) /* Protection Exclusive Mode */ +#define MSR_PMM (1<<2) /* Performance monitor mark bit (e500) */ +#define MSR_RI (1<<1) /* Recoverable Exception */ +#define MSR_LE (1<<0) /* Little Endian */ + +#ifdef CONFIG_APUS_FAST_EXCEPT +#define MSR_ MSR_ME|MSR_IP|MSR_RI +#else +#define MSR_ MSR_ME|MSR_RI +#endif + +#ifndef CONFIG_E500 +#define MSR_KERNEL MSR_|MSR_IR|MSR_DR +#else +#define MSR_KERNEL MSR_ME +#endif + +/* Floating Point Status and Control Register (FPSCR) Fields */ + +#define FPSCR_FX 0x80000000 /* FPU exception summary */ +#define FPSCR_FEX 0x40000000 /* FPU enabled exception summary */ +#define FPSCR_VX 0x20000000 /* Invalid operation summary */ +#define FPSCR_OX 0x10000000 /* Overflow exception summary */ +#define FPSCR_UX 0x08000000 /* Underflow exception summary */ +#define FPSCR_ZX 0x04000000 /* Zero-devide exception summary */ +#define FPSCR_XX 0x02000000 /* Inexact exception summary */ +#define FPSCR_VXSNAN 0x01000000 /* Invalid op for SNaN */ +#define FPSCR_VXISI 0x00800000 /* Invalid op for Inv - Inv */ +#define FPSCR_VXIDI 0x00400000 /* Invalid op for Inv / Inv */ +#define FPSCR_VXZDZ 0x00200000 /* Invalid op for Zero / Zero */ +#define FPSCR_VXIMZ 0x00100000 /* Invalid op for Inv * Zero */ +#define FPSCR_VXVC 0x00080000 /* Invalid op for Compare */ +#define FPSCR_FR 0x00040000 /* Fraction rounded */ +#define FPSCR_FI 0x00020000 /* Fraction inexact */ +#define FPSCR_FPRF 0x0001f000 /* FPU Result Flags */ +#define FPSCR_FPCC 0x0000f000 /* FPU Condition Codes */ +#define FPSCR_VXSOFT 0x00000400 /* Invalid op for software request */ +#define FPSCR_VXSQRT 0x00000200 /* Invalid op for square root */ +#define FPSCR_VXCVI 0x00000100 /* Invalid op for integer convert */ +#define FPSCR_VE 0x00000080 /* Invalid op exception enable */ +#define FPSCR_OE 0x00000040 /* IEEE overflow exception enable */ +#define FPSCR_UE 0x00000020 /* IEEE underflow exception enable */ +#define FPSCR_ZE 0x00000010 /* IEEE zero divide exception enable */ +#define FPSCR_XE 0x00000008 /* FP inexact exception enable */ +#define FPSCR_NI 0x00000004 /* FPU non IEEE-Mode */ +#define FPSCR_RN 0x00000003 /* FPU rounding control */ + +/* Special Purpose Registers (SPRNs)*/ + +/* PPC440 Architecture is BOOK-E */ +#ifdef CONFIG_440 +#define CONFIG_BOOKE +#endif + +#define SPRN_CCR0 0x3B3 /* Core Configuration Register 0 */ +#ifdef CONFIG_BOOKE +#define SPRN_CCR1 0x378 /* Core Configuration Register for 440 only */ +#endif +#define SPRN_CDBCR 0x3D7 /* Cache Debug Control Register */ +#define SPRN_CTR 0x009 /* Count Register */ +#define SPRN_DABR 0x3F5 /* Data Address Breakpoint Register */ +#ifndef CONFIG_BOOKE +#define SPRN_DAC1 0x3F6 /* Data Address Compare 1 */ +#define SPRN_DAC2 0x3F7 /* Data Address Compare 2 */ +#else +#define SPRN_DAC1 0x13C /* Book E Data Address Compare 1 */ +#define SPRN_DAC2 0x13D /* Book E Data Address Compare 2 */ +#endif /* CONFIG_BOOKE */ +#define SPRN_DAR 0x013 /* Data Address Register */ +#define SPRN_DBAT0L 0x219 /* Data BAT 0 Lower Register */ +#define SPRN_DBAT0U 0x218 /* Data BAT 0 Upper Register */ +#define SPRN_DBAT1L 0x21B /* Data BAT 1 Lower Register */ +#define SPRN_DBAT1U 0x21A /* Data BAT 1 Upper Register */ +#define SPRN_DBAT2L 0x21D /* Data BAT 2 Lower Register */ +#define SPRN_DBAT2U 0x21C /* Data BAT 2 Upper Register */ +#define SPRN_DBAT3L 0x21F /* Data BAT 3 Lower Register */ +#define SPRN_DBAT3U 0x21E /* Data BAT 3 Upper Register */ +#define SPRN_DBAT4L 0x239 /* Data BAT 4 Lower Register */ +#define SPRN_DBAT4U 0x238 /* Data BAT 4 Upper Register */ +#define SPRN_DBAT5L 0x23B /* Data BAT 5 Lower Register */ +#define SPRN_DBAT5U 0x23A /* Data BAT 5 Upper Register */ +#define SPRN_DBAT6L 0x23D /* Data BAT 6 Lower Register */ +#define SPRN_DBAT6U 0x23C /* Data BAT 6 Upper Register */ +#define SPRN_DBAT7L 0x23F /* Data BAT 7 Lower Register */ +#define SPRN_DBAT7U 0x23E /* Data BAT 7 Lower Register */ +#define SPRN_DBCR 0x3F2 /* Debug Control Regsiter */ +#define DBCR_EDM 0x80000000 +#define DBCR_IDM 0x40000000 +#define DBCR_RST(x) (((x) & 0x3) << 28) +#define DBCR_RST_NONE 0 +#define DBCR_RST_CORE 1 +#define DBCR_RST_CHIP 2 +#define DBCR_RST_SYSTEM 3 +#define DBCR_IC 0x08000000 /* Instruction Completion Debug Evnt */ +#define DBCR_BT 0x04000000 /* Branch Taken Debug Event */ +#define DBCR_EDE 0x02000000 /* Exception Debug Event */ +#define DBCR_TDE 0x01000000 /* TRAP Debug Event */ +#define DBCR_FER 0x00F80000 /* First Events Remaining Mask */ +#define DBCR_FT 0x00040000 /* Freeze Timers on Debug Event */ +#define DBCR_IA1 0x00020000 /* Instr. Addr. Compare 1 Enable */ +#define DBCR_IA2 0x00010000 /* Instr. Addr. Compare 2 Enable */ +#define DBCR_D1R 0x00008000 /* Data Addr. Compare 1 Read Enable */ +#define DBCR_D1W 0x00004000 /* Data Addr. Compare 1 Write Enable */ +#define DBCR_D1S(x) (((x) & 0x3) << 12) /* Data Adrr. Compare 1 Size */ +#define DAC_BYTE 0 +#define DAC_HALF 1 +#define DAC_WORD 2 +#define DAC_QUAD 3 +#define DBCR_D2R 0x00000800 /* Data Addr. Compare 2 Read Enable */ +#define DBCR_D2W 0x00000400 /* Data Addr. Compare 2 Write Enable */ +#define DBCR_D2S(x) (((x) & 0x3) << 8) /* Data Addr. Compare 2 Size */ +#define DBCR_SBT 0x00000040 /* Second Branch Taken Debug Event */ +#define DBCR_SED 0x00000020 /* Second Exception Debug Event */ +#define DBCR_STD 0x00000010 /* Second Trap Debug Event */ +#define DBCR_SIA 0x00000008 /* Second IAC Enable */ +#define DBCR_SDA 0x00000004 /* Second DAC Enable */ +#define DBCR_JOI 0x00000002 /* JTAG Serial Outbound Int. Enable */ +#define DBCR_JII 0x00000001 /* JTAG Serial Inbound Int. Enable */ +#ifndef CONFIG_BOOKE +#define SPRN_DBCR0 0x3F2 /* Debug Control Register 0 */ +#else +#define SPRN_DBCR0 0x134 /* Book E Debug Control Register 0 */ +#endif /* CONFIG_BOOKE */ +#ifndef CONFIG_BOOKE +#define SPRN_DBCR1 0x3BD /* Debug Control Register 1 */ +#define SPRN_DBSR 0x3F0 /* Debug Status Register */ +#else +#define SPRN_DBCR1 0x135 /* Book E Debug Control Register 1 */ +#ifdef CONFIG_BOOKE +#define SPRN_DBDR 0x3f3 /* Debug Data Register */ +#endif +#define SPRN_DBSR 0x130 /* Book E Debug Status Register */ +#define DBSR_IC 0x08000000 /* Book E Instruction Completion */ +#define DBSR_TIE 0x01000000 /* Book E Trap Instruction Event */ +#endif /* CONFIG_BOOKE */ +#define SPRN_DCCR 0x3FA /* Data Cache Cacheability Register */ +#define DCCR_NOCACHE 0 /* Noncacheable */ +#define DCCR_CACHE 1 /* Cacheable */ +#ifndef CONFIG_BOOKE +#define SPRN_DCDBTRL 0x39c /* Data Cache Debug Tag Register Low */ +#define SPRN_DCDBTRH 0x39d /* Data Cache Debug Tag Register High */ +#endif +#define SPRN_DCMP 0x3D1 /* Data TLB Compare Register */ +#define SPRN_DCWR 0x3BA /* Data Cache Write-thru Register */ +#define DCWR_COPY 0 /* Copy-back */ +#define DCWR_WRITE 1 /* Write-through */ +#ifndef CONFIG_BOOKE +#define SPRN_DEAR 0x3D5 /* Data Error Address Register */ +#else +#define SPRN_DEAR 0x03D /* Book E Data Error Address Register */ +#endif /* CONFIG_BOOKE */ +#define SPRN_DEC 0x016 /* Decrement Register */ +#define SPRN_DMISS 0x3D0 /* Data TLB Miss Register */ +#ifdef CONFIG_BOOKE +#define SPRN_DNV0 0x390 /* Data Cache Normal Victim 0 */ +#define SPRN_DNV1 0x391 /* Data Cache Normal Victim 1 */ +#define SPRN_DNV2 0x392 /* Data Cache Normal Victim 2 */ +#define SPRN_DNV3 0x393 /* Data Cache Normal Victim 3 */ +#endif +#define SPRN_DSISR 0x012 /* Data Storage Interrupt Status Register */ +#ifdef CONFIG_BOOKE +#define SPRN_DTV0 0x394 /* Data Cache Transient Victim 0 */ +#define SPRN_DTV1 0x395 /* Data Cache Transient Victim 1 */ +#define SPRN_DTV2 0x396 /* Data Cache Transient Victim 2 */ +#define SPRN_DTV3 0x397 /* Data Cache Transient Victim 3 */ +#define SPRN_DVLIM 0x398 /* Data Cache Victim Limit */ +#endif +#define SPRN_EAR 0x11A /* External Address Register */ +#ifndef CONFIG_BOOKE +#define SPRN_ESR 0x3D4 /* Exception Syndrome Register */ +#else +#define SPRN_ESR 0x03E /* Book E Exception Syndrome Register */ +#endif /* CONFIG_BOOKE */ +#define ESR_IMCP 0x80000000 /* Instr. Machine Check - Protection */ +#define ESR_IMCN 0x40000000 /* Instr. Machine Check - Non-config */ +#define ESR_IMCB 0x20000000 /* Instr. Machine Check - Bus error */ +#define ESR_IMCT 0x10000000 /* Instr. Machine Check - Timeout */ +#define ESR_PIL 0x08000000 /* Program Exception - Illegal */ +#define ESR_PPR 0x04000000 /* Program Exception - Priveleged */ +#define ESR_PTR 0x02000000 /* Program Exception - Trap */ +#define ESR_DST 0x00800000 /* Storage Exception - Data miss */ +#define ESR_DIZ 0x00400000 /* Storage Exception - Zone fault */ +#define SPRN_EVPR 0x3D6 /* Exception Vector Prefix Register */ +#define SPRN_HASH1 0x3D2 /* Primary Hash Address Register */ +#define SPRN_HASH2 0x3D3 /* Secondary Hash Address Resgister */ +#define SPRN_HID0 0x3F0 /* Hardware Implementation Register 0 */ + +#define HID0_ICE_SHIFT 15 +#define HID0_DCE_SHIFT 14 +#define HID0_DLOCK_SHIFT 12 + +#define HID0_EMCP (1<<31) /* Enable Machine Check pin */ +#define HID0_EBA (1<<29) /* Enable Bus Address Parity */ +#define HID0_EBD (1<<28) /* Enable Bus Data Parity */ +#define HID0_SBCLK (1<<27) +#define HID0_EICE (1<<26) +#define HID0_ECLK (1<<25) +#define HID0_PAR (1<<24) +#define HID0_DOZE (1<<23) +#define HID0_NAP (1<<22) +#define HID0_SLEEP (1<<21) +#define HID0_DPM (1<<20) +#define HID0_ICE (1<<HID0_ICE_SHIFT) /* Instruction Cache Enable */ +#define HID0_DCE (1<<HID0_DCE_SHIFT) /* Data Cache Enable */ +#define HID0_TBEN (1<<14) /* Time Base Enable */ +#define HID0_ILOCK (1<<13) /* Instruction Cache Lock */ +#define HID0_DLOCK (1<<HID0_DLOCK_SHIFT) /* Data Cache Lock */ +#define HID0_ICFI (1<<11) /* Instr. Cache Flash Invalidate */ +#define HID0_DCFI (1<<10) /* Data Cache Flash Invalidate */ +#define HID0_DCI HID0_DCFI +#define HID0_SPD (1<<9) /* Speculative disable */ +#define HID0_ENMAS7 (1<<7) /* Enable MAS7 Update for 36-bit phys */ +#define HID0_SGE (1<<7) /* Store Gathering Enable */ +#define HID0_SIED HID_SGE /* Serial Instr. Execution [Disable] */ +#define HID0_DCFA (1<<6) /* Data Cache Flush Assist */ +#define HID0_BTIC (1<<5) /* Branch Target Instruction Cache Enable */ +#define HID0_ABE (1<<3) /* Address Broadcast Enable */ +#define HID0_BHTE (1<<2) /* Branch History Table Enable */ +#define HID0_BTCD (1<<1) /* Branch target cache disable */ +#define SPRN_HID1 0x3F1 /* Hardware Implementation Register 1 */ +#define HID1_RFXE (1<<17) /* Read Fault Exception Enable */ +#define HID1_ASTME (1<<13) /* Address bus streaming mode */ +#define HID1_ABE (1<<12) /* Address broadcast enable */ +#define SPRN_IABR 0x3F2 /* Instruction Address Breakpoint Register */ +#ifndef CONFIG_BOOKE +#define SPRN_IAC1 0x3F4 /* Instruction Address Compare 1 */ +#define SPRN_IAC2 0x3F5 /* Instruction Address Compare 2 */ +#else +#define SPRN_IAC1 0x138 /* Book E Instruction Address Compare 1 */ +#define SPRN_IAC2 0x139 /* Book E Instruction Address Compare 2 */ +#endif /* CONFIG_BOOKE */ +#define SPRN_IBAT0L 0x211 /* Instruction BAT 0 Lower Register */ +#define SPRN_IBAT0U 0x210 /* Instruction BAT 0 Upper Register */ +#define SPRN_IBAT1L 0x213 /* Instruction BAT 1 Lower Register */ +#define SPRN_IBAT1U 0x212 /* Instruction BAT 1 Upper Register */ +#define SPRN_IBAT2L 0x215 /* Instruction BAT 2 Lower Register */ +#define SPRN_IBAT2U 0x214 /* Instruction BAT 2 Upper Register */ +#define SPRN_IBAT3L 0x217 /* Instruction BAT 3 Lower Register */ +#define SPRN_IBAT3U 0x216 /* Instruction BAT 3 Upper Register */ +#define SPRN_IBAT4L 0x231 /* Instruction BAT 4 Lower Register */ +#define SPRN_IBAT4U 0x230 /* Instruction BAT 4 Upper Register */ +#define SPRN_IBAT5L 0x233 /* Instruction BAT 5 Lower Register */ +#define SPRN_IBAT5U 0x232 /* Instruction BAT 5 Upper Register */ +#define SPRN_IBAT6L 0x235 /* Instruction BAT 6 Lower Register */ +#define SPRN_IBAT6U 0x234 /* Instruction BAT 6 Upper Register */ +#define SPRN_IBAT7L 0x237 /* Instruction BAT 7 Lower Register */ +#define SPRN_IBAT7U 0x236 /* Instruction BAT 7 Upper Register */ +#define SPRN_ICCR 0x3FB /* Instruction Cache Cacheability Register */ +#define ICCR_NOCACHE 0 /* Noncacheable */ +#define ICCR_CACHE 1 /* Cacheable */ +#define SPRN_ICDBDR 0x3D3 /* Instruction Cache Debug Data Register */ +#ifdef CONFIG_BOOKE +#define SPRN_ICDBTRL 0x39e /* instruction cache debug tag register low */ +#define SPRN_ICDBTRH 0x39f /* instruction cache debug tag register high */ +#endif +#define SPRN_ICMP 0x3D5 /* Instruction TLB Compare Register */ +#define SPRN_ICTC 0x3FB /* Instruction Cache Throttling Control Reg */ +#define SPRN_IMISS 0x3D4 /* Instruction TLB Miss Register */ +#define SPRN_IMMR 0x27E /* Internal Memory Map Register */ +#ifdef CONFIG_BOOKE +#define SPRN_INV0 0x370 /* Instruction Cache Normal Victim 0 */ +#define SPRN_INV1 0x371 /* Instruction Cache Normal Victim 1 */ +#define SPRN_INV2 0x372 /* Instruction Cache Normal Victim 2 */ +#define SPRN_INV3 0x373 /* Instruction Cache Normal Victim 3 */ +#define SPRN_ITV0 0x374 /* Instruction Cache Transient Victim 0 */ +#define SPRN_ITV1 0x375 /* Instruction Cache Transient Victim 1 */ +#define SPRN_ITV2 0x376 /* Instruction Cache Transient Victim 2 */ +#define SPRN_ITV3 0x377 /* Instruction Cache Transient Victim 3 */ +#define SPRN_IVLIM 0x399 /* Instruction Cache Victim Limit */ +#endif +#define SPRN_LDSTCR 0x3F8 /* Load/Store Control Register */ +#define SPRN_L2CR 0x3F9 /* Level 2 Cache Control Regsiter */ +#define SPRN_LR 0x008 /* Link Register */ +#define SPRN_MBAR 0x137 /* System memory base address */ +#define SPRN_MMCR0 0x3B8 /* Monitor Mode Control Register 0 */ +#define SPRN_MMCR1 0x3BC /* Monitor Mode Control Register 1 */ +#ifdef CONFIG_BOOKE +#define SPRN_MMUCR 0x3b2 /* MMU Control Register */ +#endif +#define SPRN_PBL1 0x3FC /* Protection Bound Lower 1 */ +#define SPRN_PBL2 0x3FE /* Protection Bound Lower 2 */ +#define SPRN_PBU1 0x3FD /* Protection Bound Upper 1 */ +#define SPRN_PBU2 0x3FF /* Protection Bound Upper 2 */ +#ifndef CONFIG_BOOKE +#define SPRN_PID 0x3B1 /* Process ID */ +#define SPRN_PIR 0x3FF /* Processor Identification Register */ +#else +#define SPRN_PID 0x030 /* Book E Process ID */ +#define SPRN_PIR 0x11E /* Book E Processor Identification Register */ +#endif /* CONFIG_BOOKE */ +#define SPRN_PIT 0x3DB /* Programmable Interval Timer */ +#define SPRN_PMC1 0x3B9 /* Performance Counter Register 1 */ +#define SPRN_PMC2 0x3BA /* Performance Counter Register 2 */ +#define SPRN_PMC3 0x3BD /* Performance Counter Register 3 */ +#define SPRN_PMC4 0x3BE /* Performance Counter Register 4 */ +#define SPRN_PVR 0x11F /* Processor Version Register */ +#define SPRN_RPA 0x3D6 /* Required Physical Address Register */ +#ifdef CONFIG_BOOKE +#define SPRN_RSTCFG 0x39b /* Reset Configuration */ +#endif +#define SPRN_SDA 0x3BF /* Sampled Data Address Register */ +#define SPRN_SDR1 0x019 /* MMU Hash Base Register */ +#define SPRN_SGR 0x3B9 /* Storage Guarded Register */ +#define SGR_NORMAL 0 +#define SGR_GUARDED 1 +#define SPRN_SIA 0x3BB /* Sampled Instruction Address Register */ +#define SPRN_SPRG0 0x110 /* Special Purpose Register General 0 */ +#define SPRN_SPRG1 0x111 /* Special Purpose Register General 1 */ +#define SPRN_SPRG2 0x112 /* Special Purpose Register General 2 */ +#define SPRN_SPRG3 0x113 /* Special Purpose Register General 3 */ +#define SPRN_SPRG4 0x114 /* Special Purpose Register General 4 */ +#define SPRN_SPRG5 0x115 /* Special Purpose Register General 5 */ +#define SPRN_SPRG6 0x116 /* Special Purpose Register General 6 */ +#define SPRN_SPRG7 0x117 /* Special Purpose Register General 7 */ +#define SPRN_SRR0 0x01A /* Save/Restore Register 0 */ +#define SPRN_SRR1 0x01B /* Save/Restore Register 1 */ +#define SPRN_SRR2 0x3DE /* Save/Restore Register 2 */ +#define SPRN_SRR3 0x3DF /* Save/Restore Register 3 */ + +#ifdef CONFIG_BOOKE +#define SPRN_SVR 0x3FF /* System Version Register */ +#else +#define SPRN_SVR 0x11E /* System Version Register */ +#endif +#define SPRN_TBHI 0x3DC /* Time Base High */ +#define SPRN_TBHU 0x3CC /* Time Base High User-mode */ +#define SPRN_TBLO 0x3DD /* Time Base Low */ +#define SPRN_TBLU 0x3CD /* Time Base Low User-mode */ +#define SPRN_TBRL 0x10C /* Time Base Read Lower Register */ +#define SPRN_TBRU 0x10D /* Time Base Read Upper Register */ +#define SPRN_TBWL 0x11C /* Time Base Write Lower Register */ +#define SPRN_TBWU 0x11D /* Time Base Write Upper Register */ +#ifndef CONFIG_BOOKE +#define SPRN_TCR 0x3DA /* Timer Control Register */ +#else +#define SPRN_TCR 0x154 /* Book E Timer Control Register */ +#endif /* CONFIG_BOOKE */ +#define TCR_WP(x) (((x)&0x3)<<30) /* WDT Period */ +#define WP_2_17 0 /* 2^17 clocks */ +#define WP_2_21 1 /* 2^21 clocks */ +#define WP_2_25 2 /* 2^25 clocks */ +#define WP_2_29 3 /* 2^29 clocks */ +#define TCR_WRC(x) (((x)&0x3)<<28) /* WDT Reset Control */ +#define WRC_NONE 0 /* No reset will occur */ +#define WRC_CORE 1 /* Core reset will occur */ +#define WRC_CHIP 2 /* Chip reset will occur */ +#define WRC_SYSTEM 3 /* System reset will occur */ +#define TCR_WIE 0x08000000 /* WDT Interrupt Enable */ +#define TCR_PIE 0x04000000 /* PIT Interrupt Enable */ +#define TCR_FP(x) (((x)&0x3)<<24) /* FIT Period */ +#define FP_2_9 0 /* 2^9 clocks */ +#define FP_2_13 1 /* 2^13 clocks */ +#define FP_2_17 2 /* 2^17 clocks */ +#define FP_2_21 3 /* 2^21 clocks */ +#define TCR_FIE 0x00800000 /* FIT Interrupt Enable */ +#define TCR_ARE 0x00400000 /* Auto Reload Enable */ +#define SPRN_THRM1 0x3FC /* Thermal Management Register 1 */ +#define THRM1_TIN (1<<0) +#define THRM1_TIV (1<<1) +#define THRM1_THRES (0x7f<<2) +#define THRM1_TID (1<<29) +#define THRM1_TIE (1<<30) +#define THRM1_V (1<<31) +#define SPRN_THRM2 0x3FD /* Thermal Management Register 2 */ +#define SPRN_THRM3 0x3FE /* Thermal Management Register 3 */ +#define THRM3_E (1<<31) +#define SPRN_TLBMISS 0x3D4 /* 980 7450 TLB Miss Register */ +#ifndef CONFIG_BOOKE +#define SPRN_TSR 0x3D8 /* Timer Status Register */ +#else +#define SPRN_TSR 0x150 /* Book E Timer Status Register */ +#endif /* CONFIG_BOOKE */ +#define TSR_ENW 0x80000000 /* Enable Next Watchdog */ +#define TSR_WIS 0x40000000 /* WDT Interrupt Status */ +#define TSR_WRS(x) (((x)&0x3)<<28) /* WDT Reset Status */ +#define WRS_NONE 0 /* No WDT reset occurred */ +#define WRS_CORE 1 /* WDT forced core reset */ +#define WRS_CHIP 2 /* WDT forced chip reset */ +#define WRS_SYSTEM 3 /* WDT forced system reset */ +#define TSR_PIS 0x08000000 /* PIT Interrupt Status */ +#define TSR_FIS 0x04000000 /* FIT Interrupt Status */ +#define SPRN_UMMCR0 0x3A8 /* User Monitor Mode Control Register 0 */ +#define SPRN_UMMCR1 0x3AC /* User Monitor Mode Control Register 0 */ +#define SPRN_UPMC1 0x3A9 /* User Performance Counter Register 1 */ +#define SPRN_UPMC2 0x3AA /* User Performance Counter Register 2 */ +#define SPRN_UPMC3 0x3AD /* User Performance Counter Register 3 */ +#define SPRN_UPMC4 0x3AE /* User Performance Counter Register 4 */ +#define SPRN_USIA 0x3AB /* User Sampled Instruction Address Register */ +#define SPRN_XER 0x001 /* Fixed Point Exception Register */ +#define SPRN_ZPR 0x3B0 /* Zone Protection Register */ + +/* Book E definitions */ +#define SPRN_DECAR 0x036 /* Decrementer Auto Reload Register */ +#define SPRN_CSRR0 0x03A /* Critical SRR0 */ +#define SPRN_CSRR1 0x03B /* Critical SRR0 */ +#define SPRN_IVPR 0x03F /* Interrupt Vector Prefix Register */ +#define SPRN_USPRG0 0x100 /* User Special Purpose Register General 0 */ +#define SPRN_SPRG4R 0x104 /* Special Purpose Register General 4 Read */ +#define SPRN_SPRG5R 0x105 /* Special Purpose Register General 5 Read */ +#define SPRN_SPRG6R 0x106 /* Special Purpose Register General 6 Read */ +#define SPRN_SPRG7R 0x107 /* Special Purpose Register General 7 Read */ +#define SPRN_SPRG4W 0x114 /* Special Purpose Register General 4 Write */ +#define SPRN_SPRG5W 0x115 /* Special Purpose Register General 5 Write */ +#define SPRN_SPRG6W 0x116 /* Special Purpose Register General 6 Write */ +#define SPRN_SPRG7W 0x117 /* Special Purpose Register General 7 Write */ +#define SPRN_DBCR2 0x136 /* Debug Control Register 2 */ +#define SPRN_IAC3 0x13A /* Instruction Address Compare 3 */ +#define SPRN_IAC4 0x13B /* Instruction Address Compare 4 */ +#define SPRN_DVC1 0x13E /* Data Value Compare Register 1 */ +#define SPRN_DVC2 0x13F /* Data Value Compare Register 2 */ +#define SPRN_IVOR0 0x190 /* Interrupt Vector Offset Register 0 */ +#define SPRN_IVOR1 0x191 /* Interrupt Vector Offset Register 1 */ +#define SPRN_IVOR2 0x192 /* Interrupt Vector Offset Register 2 */ +#define SPRN_IVOR3 0x193 /* Interrupt Vector Offset Register 3 */ +#define SPRN_IVOR4 0x194 /* Interrupt Vector Offset Register 4 */ +#define SPRN_IVOR5 0x195 /* Interrupt Vector Offset Register 5 */ +#define SPRN_IVOR6 0x196 /* Interrupt Vector Offset Register 6 */ +#define SPRN_IVOR7 0x197 /* Interrupt Vector Offset Register 7 */ +#define SPRN_IVOR8 0x198 /* Interrupt Vector Offset Register 8 */ +#define SPRN_IVOR9 0x199 /* Interrupt Vector Offset Register 9 */ +#define SPRN_IVOR10 0x19a /* Interrupt Vector Offset Register 10 */ +#define SPRN_IVOR11 0x19b /* Interrupt Vector Offset Register 11 */ +#define SPRN_IVOR12 0x19c /* Interrupt Vector Offset Register 12 */ +#define SPRN_IVOR13 0x19d /* Interrupt Vector Offset Register 13 */ +#define SPRN_IVOR14 0x19e /* Interrupt Vector Offset Register 14 */ +#define SPRN_IVOR15 0x19f /* Interrupt Vector Offset Register 15 */ + +/* e500 definitions */ +#define SPRN_L1CFG0 0x203 /* L1 Cache Configuration Register 0 */ +#define SPRN_L1CFG1 0x204 /* L1 Cache Configuration Register 1 */ +#define SPRN_L2CFG0 0x207 /* L2 Cache Configuration Register 0 */ +#define SPRN_L1CSR0 0x3f2 /* L1 Data Cache Control and Status Register 0 */ +#define L1CSR0_CPE 0x00010000 /* Data Cache Parity Enable */ +#define L1CSR0_DCFI 0x00000002 /* Data Cache Flash Invalidate */ +#define L1CSR0_DCE 0x00000001 /* Data Cache Enable */ +#define SPRN_L1CSR1 0x3f3 /* L1 Instruction Cache Control and Status Register 1 */ +#define L1CSR1_CPE 0x00010000 /* Instruction Cache Parity Enable */ +#define L1CSR1_ICFI 0x00000002 /* Instruction Cache Flash Invalidate */ +#define L1CSR1_ICE 0x00000001 /* Instruction Cache Enable */ +#define SPRN_L1CSR2 0x25e /* L1 Data Cache Control and Status Register 2 */ +#define SPRN_L2CSR0 0x3f9 /* L2 Data Cache Control and Status Register 0 */ +#define L2CSR0_L2E 0x80000000 /* L2 Cache Enable */ +#define L2CSR0_L2PE 0x40000000 /* L2 Cache Parity/ECC Enable */ +#define L2CSR0_L2WP 0x1c000000 /* L2 I/D Way Partioning */ +#define L2CSR0_L2CM 0x03000000 /* L2 Cache Coherency Mode */ +#define L2CSR0_L2FI 0x00200000 /* L2 Cache Flash Invalidate */ +#define L2CSR0_L2IO 0x00100000 /* L2 Cache Instruction Only */ +#define L2CSR0_L2DO 0x00010000 /* L2 Cache Data Only */ +#define L2CSR0_L2REP 0x00003000 /* L2 Line Replacement Algo */ +#define L2CSR0_L2FL 0x00000800 /* L2 Cache Flush */ +#define L2CSR0_L2LFC 0x00000400 /* L2 Cache Lock Flash Clear */ +#define L2CSR0_L2LOA 0x00000080 /* L2 Cache Lock Overflow Allocate */ +#define L2CSR0_L2LO 0x00000020 /* L2 Cache Lock Overflow */ +#define SPRN_L2CSR1 0x3fa /* L2 Data Cache Control and Status Register 1 */ + +#define SPRN_TLB0CFG 0x2B0 /* TLB 0 Config Register */ +#define SPRN_TLB1CFG 0x2B1 /* TLB 1 Config Register */ +#define SPRN_MMUCSR0 0x3f4 /* MMU control and status register 0 */ +#define SPRN_MAS0 0x270 /* MMU Assist Register 0 */ +#define SPRN_MAS1 0x271 /* MMU Assist Register 1 */ +#define SPRN_MAS2 0x272 /* MMU Assist Register 2 */ +#define SPRN_MAS3 0x273 /* MMU Assist Register 3 */ +#define SPRN_MAS4 0x274 /* MMU Assist Register 4 */ +#define SPRN_MAS5 0x275 /* MMU Assist Register 5 */ +#define SPRN_MAS6 0x276 /* MMU Assist Register 6 */ +#define SPRN_MAS7 0x3B0 /* MMU Assist Register 7 */ + +#define SPRN_IVOR32 0x210 /* Interrupt Vector Offset Register 32 */ +#define SPRN_IVOR33 0x211 /* Interrupt Vector Offset Register 33 */ +#define SPRN_IVOR34 0x212 /* Interrupt Vector Offset Register 34 */ +#define SPRN_IVOR35 0x213 /* Interrupt Vector Offset Register 35 */ +#define SPRN_SPEFSCR 0x200 /* SPE & Embedded FP Status & Control */ + +#define SPRN_MCSRR0 0x23a /* Machine Check Save and Restore Register 0 */ +#define SPRN_MCSRR1 0x23b /* Machine Check Save and Restore Register 1 */ +#define SPRN_BUCSR 0x3f5 /* Branch Control and Status Register */ +#define SPRN_BBEAR 0x201 /* Branch Buffer Entry Address Register */ +#define SPRN_BBTAR 0x202 /* Branch Buffer Target Address Register */ +#define SPRN_PID1 0x279 /* Process ID Register 1 */ +#define SPRN_PID2 0x27a /* Process ID Register 2 */ +#define SPRN_MCSR 0x23c /* Machine Check Syndrome register */ +#define SPRN_MCAR 0x23d /* Machine Check Address register */ +#define MCSR_MCS 0x80000000 /* Machine Check Summary */ +#define MCSR_IB 0x40000000 /* Instruction PLB Error */ +#if defined(CONFIG_440) +#define MCSR_DRB 0x20000000 /* Data Read PLB Error */ +#define MCSR_DWB 0x10000000 /* Data Write PLB Error */ +#else +#define MCSR_DB 0x20000000 /* Data PLB Error */ +#endif /* defined(CONFIG_440) */ +#define MCSR_TLBP 0x08000000 /* TLB Parity Error */ +#define MCSR_ICP 0x04000000 /* I-Cache Parity Error */ +#define MCSR_DCSP 0x02000000 /* D-Cache Search Parity Error */ +#define MCSR_DCFP 0x01000000 /* D-Cache Flush Parity Error */ +#define MCSR_IMPE 0x00800000 /* Imprecise Machine Check Exception */ +#define ESR_ST 0x00800000 /* Store Operation */ + +#if defined(CONFIG_MPC86xx) +#define SPRN_MSSCR0 0x3f6 +#define SPRN_MSSSR0 0x3f7 +#endif + +/* Short-hand versions for a number of the above SPRNs */ + +#define CTR SPRN_CTR /* Counter Register */ +#define DAR SPRN_DAR /* Data Address Register */ +#define DABR SPRN_DABR /* Data Address Breakpoint Register */ +#define DAC1 SPRN_DAC1 /* Data Address Register 1 */ +#define DAC2 SPRN_DAC2 /* Data Address Register 2 */ +#define DBAT0L SPRN_DBAT0L /* Data BAT 0 Lower Register */ +#define DBAT0U SPRN_DBAT0U /* Data BAT 0 Upper Register */ +#define DBAT1L SPRN_DBAT1L /* Data BAT 1 Lower Register */ +#define DBAT1U SPRN_DBAT1U /* Data BAT 1 Upper Register */ +#define DBAT2L SPRN_DBAT2L /* Data BAT 2 Lower Register */ +#define DBAT2U SPRN_DBAT2U /* Data BAT 2 Upper Register */ +#define DBAT3L SPRN_DBAT3L /* Data BAT 3 Lower Register */ +#define DBAT3U SPRN_DBAT3U /* Data BAT 3 Upper Register */ +#define DBAT4L SPRN_DBAT4L /* Data BAT 4 Lower Register */ +#define DBAT4U SPRN_DBAT4U /* Data BAT 4 Upper Register */ +#define DBAT5L SPRN_DBAT5L /* Data BAT 5 Lower Register */ +#define DBAT5U SPRN_DBAT5U /* Data BAT 5 Upper Register */ +#define DBAT6L SPRN_DBAT6L /* Data BAT 6 Lower Register */ +#define DBAT6U SPRN_DBAT6U /* Data BAT 6 Upper Register */ +#define DBAT7L SPRN_DBAT7L /* Data BAT 7 Lower Register */ +#define DBAT7U SPRN_DBAT7U /* Data BAT 7 Upper Register */ +#define DBCR0 SPRN_DBCR0 /* Debug Control Register 0 */ +#define DBCR1 SPRN_DBCR1 /* Debug Control Register 1 */ +#define DBSR SPRN_DBSR /* Debug Status Register */ +#define DCMP SPRN_DCMP /* Data TLB Compare Register */ +#define DEC SPRN_DEC /* Decrement Register */ +#define DMISS SPRN_DMISS /* Data TLB Miss Register */ +#define DSISR SPRN_DSISR /* Data Storage Interrupt Status Register */ +#define EAR SPRN_EAR /* External Address Register */ +#define ESR SPRN_ESR /* Exception Syndrome Register */ +#define HASH1 SPRN_HASH1 /* Primary Hash Address Register */ +#define HASH2 SPRN_HASH2 /* Secondary Hash Address Register */ +#define HID0 SPRN_HID0 /* Hardware Implementation Register 0 */ +#define HID1 SPRN_HID1 /* Hardware Implementation Register 1 */ +#define IABR SPRN_IABR /* Instruction Address Breakpoint Register */ +#define IAC1 SPRN_IAC1 /* Instruction Address Register 1 */ +#define IAC2 SPRN_IAC2 /* Instruction Address Register 2 */ +#define IBAT0L SPRN_IBAT0L /* Instruction BAT 0 Lower Register */ +#define IBAT0U SPRN_IBAT0U /* Instruction BAT 0 Upper Register */ +#define IBAT1L SPRN_IBAT1L /* Instruction BAT 1 Lower Register */ +#define IBAT1U SPRN_IBAT1U /* Instruction BAT 1 Upper Register */ +#define IBAT2L SPRN_IBAT2L /* Instruction BAT 2 Lower Register */ +#define IBAT2U SPRN_IBAT2U /* Instruction BAT 2 Upper Register */ +#define IBAT3L SPRN_IBAT3L /* Instruction BAT 3 Lower Register */ +#define IBAT3U SPRN_IBAT3U /* Instruction BAT 3 Upper Register */ +#define IBAT4L SPRN_IBAT4L /* Instruction BAT 4 Lower Register */ +#define IBAT4U SPRN_IBAT4U /* Instruction BAT 4 Upper Register */ +#define IBAT5L SPRN_IBAT5L /* Instruction BAT 5 Lower Register */ +#define IBAT5U SPRN_IBAT5U /* Instruction BAT 5 Upper Register */ +#define IBAT6L SPRN_IBAT6L /* Instruction BAT 6 Lower Register */ +#define IBAT6U SPRN_IBAT6U /* Instruction BAT 6 Upper Register */ +#define IBAT7L SPRN_IBAT7L /* Instruction BAT 7 Lower Register */ +#define IBAT7U SPRN_IBAT7U /* Instruction BAT 7 Lower Register */ +#define ICMP SPRN_ICMP /* Instruction TLB Compare Register */ +#define IMISS SPRN_IMISS /* Instruction TLB Miss Register */ +#define IMMR SPRN_IMMR /* PPC 860/821 Internal Memory Map Register */ +#define LDSTCR SPRN_LDSTCR /* Load/Store Control Register */ +#define L2CR SPRN_L2CR /* PPC 750 L2 control register */ +#define LR SPRN_LR +#define MBAR SPRN_MBAR /* System memory base address */ +#if defined(CONFIG_MPC86xx) +#define MSSCR0 SPRN_MSSCR0 +#endif +#if defined(CONFIG_E500) || defined(CONFIG_MPC86xx) +#define PIR SPRN_PIR +#endif +#define SVR SPRN_SVR /* System-On-Chip Version Register */ +#define PVR SPRN_PVR /* Processor Version */ +#define RPA SPRN_RPA /* Required Physical Address Register */ +#define SDR1 SPRN_SDR1 /* MMU hash base register */ +#define SPR0 SPRN_SPRG0 /* Supervisor Private Registers */ +#define SPR1 SPRN_SPRG1 +#define SPR2 SPRN_SPRG2 +#define SPR3 SPRN_SPRG3 +#define SPRG0 SPRN_SPRG0 +#define SPRG1 SPRN_SPRG1 +#define SPRG2 SPRN_SPRG2 +#define SPRG3 SPRN_SPRG3 +#define SPRG4 SPRN_SPRG4 +#define SPRG5 SPRN_SPRG5 +#define SPRG6 SPRN_SPRG6 +#define SPRG7 SPRN_SPRG7 +#define SRR0 SPRN_SRR0 /* Save and Restore Register 0 */ +#define SRR1 SPRN_SRR1 /* Save and Restore Register 1 */ +#define SRR2 SPRN_SRR2 /* Save and Restore Register 2 */ +#define SRR3 SPRN_SRR3 /* Save and Restore Register 3 */ +#define SVR SPRN_SVR /* System Version Register */ +#define TBRL SPRN_TBRL /* Time Base Read Lower Register */ +#define TBRU SPRN_TBRU /* Time Base Read Upper Register */ +#define TBWL SPRN_TBWL /* Time Base Write Lower Register */ +#define TBWU SPRN_TBWU /* Time Base Write Upper Register */ +#define TCR SPRN_TCR /* Timer Control Register */ +#define TSR SPRN_TSR /* Timer Status Register */ +#define ICTC 1019 +#define THRM1 SPRN_THRM1 /* Thermal Management Register 1 */ +#define THRM2 SPRN_THRM2 /* Thermal Management Register 2 */ +#define THRM3 SPRN_THRM3 /* Thermal Management Register 3 */ +#define XER SPRN_XER + +#define DECAR SPRN_DECAR +#define CSRR0 SPRN_CSRR0 +#define CSRR1 SPRN_CSRR1 +#define IVPR SPRN_IVPR +#define USPRG0 SPRN_USPRG +#define SPRG4R SPRN_SPRG4R +#define SPRG5R SPRN_SPRG5R +#define SPRG6R SPRN_SPRG6R +#define SPRG7R SPRN_SPRG7R +#define SPRG4W SPRN_SPRG4W +#define SPRG5W SPRN_SPRG5W +#define SPRG6W SPRN_SPRG6W +#define SPRG7W SPRN_SPRG7W +#define DEAR SPRN_DEAR +#define DBCR2 SPRN_DBCR2 +#define IAC3 SPRN_IAC3 +#define IAC4 SPRN_IAC4 +#define DVC1 SPRN_DVC1 +#define DVC2 SPRN_DVC2 +#define IVOR0 SPRN_IVOR0 +#define IVOR1 SPRN_IVOR1 +#define IVOR2 SPRN_IVOR2 +#define IVOR3 SPRN_IVOR3 +#define IVOR4 SPRN_IVOR4 +#define IVOR5 SPRN_IVOR5 +#define IVOR6 SPRN_IVOR6 +#define IVOR7 SPRN_IVOR7 +#define IVOR8 SPRN_IVOR8 +#define IVOR9 SPRN_IVOR9 +#define IVOR10 SPRN_IVOR10 +#define IVOR11 SPRN_IVOR11 +#define IVOR12 SPRN_IVOR12 +#define IVOR13 SPRN_IVOR13 +#define IVOR14 SPRN_IVOR14 +#define IVOR15 SPRN_IVOR15 +#define IVOR32 SPRN_IVOR32 +#define IVOR33 SPRN_IVOR33 +#define IVOR34 SPRN_IVOR34 +#define IVOR35 SPRN_IVOR35 +#define MCSRR0 SPRN_MCSRR0 +#define MCSRR1 SPRN_MCSRR1 +#define L1CSR0 SPRN_L1CSR0 +#define L1CSR1 SPRN_L1CSR1 +#define L1CSR2 SPRN_L1CSR2 +#define L1CFG0 SPRN_L1CFG0 +#define L1CFG1 SPRN_L1CFG1 +#define L2CFG0 SPRN_L2CFG0 +#define L2CSR0 SPRN_L2CSR0 +#define L2CSR1 SPRN_L2CSR1 +#define MCSR SPRN_MCSR +#define MMUCSR0 SPRN_MMUCSR0 +#define BUCSR SPRN_BUCSR +#define PID0 SPRN_PID +#define PID1 SPRN_PID1 +#define PID2 SPRN_PID2 +#define MAS0 SPRN_MAS0 +#define MAS1 SPRN_MAS1 +#define MAS2 SPRN_MAS2 +#define MAS3 SPRN_MAS3 +#define MAS4 SPRN_MAS4 +#define MAS5 SPRN_MAS5 +#define MAS6 SPRN_MAS6 +#define MAS7 SPRN_MAS7 + +#if defined(CONFIG_4xx) || defined(CONFIG_44x) || defined(CONFIG_MPC85xx) +#define DAR_DEAR DEAR +#else +#define DAR_DEAR DAR +#endif + +/* Device Control Registers */ + +#define DCRN_BEAR 0x090 /* Bus Error Address Register */ +#define DCRN_BESR 0x091 /* Bus Error Syndrome Register */ +#define BESR_DSES 0x80000000 /* Data-Side Error Status */ +#define BESR_DMES 0x40000000 /* DMA Error Status */ +#define BESR_RWS 0x20000000 /* Read/Write Status */ +#define BESR_ETMASK 0x1C000000 /* Error Type */ +#define ET_PROT 0 +#define ET_PARITY 1 +#define ET_NCFG 2 +#define ET_BUSERR 4 +#define ET_BUSTO 6 +#define DCRN_DMACC0 0x0C4 /* DMA Chained Count Register 0 */ +#define DCRN_DMACC1 0x0CC /* DMA Chained Count Register 1 */ +#define DCRN_DMACC2 0x0D4 /* DMA Chained Count Register 2 */ +#define DCRN_DMACC3 0x0DC /* DMA Chained Count Register 3 */ +#define DCRN_DMACR0 0x0C0 /* DMA Channel Control Register 0 */ +#define DCRN_DMACR1 0x0C8 /* DMA Channel Control Register 1 */ +#define DCRN_DMACR2 0x0D0 /* DMA Channel Control Register 2 */ +#define DCRN_DMACR3 0x0D8 /* DMA Channel Control Register 3 */ +#define DCRN_DMACT0 0x0C1 /* DMA Count Register 0 */ +#define DCRN_DMACT1 0x0C9 /* DMA Count Register 1 */ +#define DCRN_DMACT2 0x0D1 /* DMA Count Register 2 */ +#define DCRN_DMACT3 0x0D9 /* DMA Count Register 3 */ +#define DCRN_DMADA0 0x0C2 /* DMA Destination Address Register 0 */ +#define DCRN_DMADA1 0x0CA /* DMA Destination Address Register 1 */ +#define DCRN_DMADA2 0x0D2 /* DMA Destination Address Register 2 */ +#define DCRN_DMADA3 0x0DA /* DMA Destination Address Register 3 */ +#define DCRN_DMASA0 0x0C3 /* DMA Source Address Register 0 */ +#define DCRN_DMASA1 0x0CB /* DMA Source Address Register 1 */ +#define DCRN_DMASA2 0x0D3 /* DMA Source Address Register 2 */ +#define DCRN_DMASA3 0x0DB /* DMA Source Address Register 3 */ +#define DCRN_DMASR 0x0E0 /* DMA Status Register */ +#define DCRN_EXIER 0x042 /* External Interrupt Enable Register */ +#define EXIER_CIE 0x80000000 /* Critical Interrupt Enable */ +#define EXIER_SRIE 0x08000000 /* Serial Port Rx Int. Enable */ +#define EXIER_STIE 0x04000000 /* Serial Port Tx Int. Enable */ +#define EXIER_JRIE 0x02000000 /* JTAG Serial Port Rx Int. Enable */ +#define EXIER_JTIE 0x01000000 /* JTAG Serial Port Tx Int. Enable */ +#define EXIER_D0IE 0x00800000 /* DMA Channel 0 Interrupt Enable */ +#define EXIER_D1IE 0x00400000 /* DMA Channel 1 Interrupt Enable */ +#define EXIER_D2IE 0x00200000 /* DMA Channel 2 Interrupt Enable */ +#define EXIER_D3IE 0x00100000 /* DMA Channel 3 Interrupt Enable */ +#define EXIER_E0IE 0x00000010 /* External Interrupt 0 Enable */ +#define EXIER_E1IE 0x00000008 /* External Interrupt 1 Enable */ +#define EXIER_E2IE 0x00000004 /* External Interrupt 2 Enable */ +#define EXIER_E3IE 0x00000002 /* External Interrupt 3 Enable */ +#define EXIER_E4IE 0x00000001 /* External Interrupt 4 Enable */ +#define DCRN_EXISR 0x040 /* External Interrupt Status Register */ +#define DCRN_IOCR 0x0A0 /* Input/Output Configuration Register */ +#define IOCR_E0TE 0x80000000 +#define IOCR_E0LP 0x40000000 +#define IOCR_E1TE 0x20000000 +#define IOCR_E1LP 0x10000000 +#define IOCR_E2TE 0x08000000 +#define IOCR_E2LP 0x04000000 +#define IOCR_E3TE 0x02000000 +#define IOCR_E3LP 0x01000000 +#define IOCR_E4TE 0x00800000 +#define IOCR_E4LP 0x00400000 +#define IOCR_EDT 0x00080000 +#define IOCR_SOR 0x00040000 +#define IOCR_EDO 0x00008000 +#define IOCR_2XC 0x00004000 +#define IOCR_ATC 0x00002000 +#define IOCR_SPD 0x00001000 +#define IOCR_BEM 0x00000800 +#define IOCR_PTD 0x00000400 +#define IOCR_ARE 0x00000080 +#define IOCR_DRC 0x00000020 +#define IOCR_RDM(x) (((x) & 0x3) << 3) +#define IOCR_TCS 0x00000004 +#define IOCR_SCS 0x00000002 +#define IOCR_SPC 0x00000001 + +/* System-On-Chip Version Register */ + +/* System-On-Chip Version Register (SVR) field extraction */ + +#define SVR_VER(svr) (((svr) >> 16) & 0xFFFF) /* Version field */ +#define SVR_REV(svr) (((svr) >> 0) & 0xFFFF) /* Revision field */ + +#define SVR_CID(svr) (((svr) >> 28) & 0x0F) /* Company or manufacturer ID */ +#define SVR_SOCOP(svr) (((svr) >> 22) & 0x3F) /* SOC integration options */ +#define SVR_SID(svr) (((svr) >> 16) & 0x3F) /* SOC ID */ +#define SVR_PROC(svr) (((svr) >> 12) & 0x0F) /* Process revision field */ +#define SVR_MFG(svr) (((svr) >> 8) & 0x0F) /* Manufacturing revision */ +#define SVR_MJREV(svr) (((svr) >> 4) & 0x0F) /* Major SOC design revision indicator */ +#define SVR_MNREV(svr) (((svr) >> 0) & 0x0F) /* Minor SOC design revision indicator */ + +/* Processor Version Register */ + +/* Processor Version Register (PVR) field extraction */ + +#define PVR_VER(pvr) (((pvr) >> 16) & 0xFFFF) /* Version field */ +#define PVR_REV(pvr) (((pvr) >> 0) & 0xFFFF) /* Revison field */ + +/* + * AMCC has further subdivided the standard PowerPC 16-bit version and + * revision subfields of the PVR for the PowerPC 403s into the following: + */ + +#define PVR_FAM(pvr) (((pvr) >> 20) & 0xFFF) /* Family field */ +#define PVR_MEM(pvr) (((pvr) >> 16) & 0xF) /* Member field */ +#define PVR_CORE(pvr) (((pvr) >> 12) & 0xF) /* Core field */ +#define PVR_CFG(pvr) (((pvr) >> 8) & 0xF) /* Configuration field */ +#define PVR_MAJ(pvr) (((pvr) >> 4) & 0xF) /* Major revision field */ +#define PVR_MIN(pvr) (((pvr) >> 0) & 0xF) /* Minor revision field */ + +/* e600 core PVR fields */ + +#define PVR_E600_VER(pvr) (((pvr) >> 15) & 0xFFFF) /* Version/type */ +#define PVR_E600_TECH(pvr) (((pvr) >> 12) & 0xF) /* Technology */ +#define PVR_E600_MAJ(pvr) (((pvr) >> 8) & 0xF) /* Major revision */ +#define PVR_E600_MIN(pvr) (((pvr) >> 0) & 0xFF) /* Minor revision */ + +/* Processor Version Numbers */ + +#define PVR_403GA 0x00200000 +#define PVR_403GB 0x00200100 +#define PVR_403GC 0x00200200 +#define PVR_403GCX 0x00201400 +#define PVR_405GP 0x40110000 +#define PVR_405GP_RB 0x40110040 +#define PVR_405GP_RC 0x40110082 +#define PVR_405GP_RD 0x401100C4 +#define PVR_405GP_RE 0x40110145 /* same as pc405cr rev c */ +#define PVR_405CR_RA 0x40110041 +#define PVR_405CR_RB 0x401100C5 +#define PVR_405CR_RC 0x40110145 /* same as pc405gp rev e */ +#define PVR_405EP_RA 0x51210950 +#define PVR_405GPR_RB 0x50910951 +#define PVR_405EZ_RA 0x41511460 +#define PVR_405EXR1_RA 0x12911473 /* 405EXr rev A/B with Security */ +#define PVR_405EXR2_RA 0x12911471 /* 405EXr rev A/B without Security */ +#define PVR_405EX1_RA 0x12911477 /* 405EX rev A/B with Security */ +#define PVR_405EX2_RA 0x12911475 /* 405EX rev A/B without Security */ +#define PVR_405EXR1_RC 0x1291147B /* 405EXr rev C with Security */ +#define PVR_405EXR2_RC 0x12911479 /* 405EXr rev C without Security */ +#define PVR_405EX1_RC 0x1291147F /* 405EX rev C with Security */ +#define PVR_405EX2_RC 0x1291147D /* 405EX rev C without Security */ +#define PVR_440GP_RB 0x40120440 +#define PVR_440GP_RC 0x40120481 +#define PVR_440EP_RA 0x42221850 +#define PVR_440EP_RB 0x422218D3 /* 440EP rev B and 440GR rev A have same PVR */ +#define PVR_440EP_RC 0x422218D4 /* 440EP rev C and 440GR rev B have same PVR */ +#define PVR_440GR_RA 0x422218D3 /* 440EP rev B and 440GR rev A have same PVR */ +#define PVR_440GR_RB 0x422218D4 /* 440EP rev C and 440GR rev B have same PVR */ +#define PVR_440EPX1_RA 0x216218D0 /* 440EPX rev A with Security / Kasumi */ +#define PVR_440EPX2_RA 0x216218D4 /* 440EPX rev A without Security / Kasumi */ +#define PVR_440GRX1_RA 0x216218D0 /* 440GRX rev A with Security / Kasumi */ +#define PVR_440GRX2_RA 0x216218D4 /* 440GRX rev A without Security / Kasumi */ +#define PVR_440GX_RA 0x51B21850 +#define PVR_440GX_RB 0x51B21851 +#define PVR_440GX_RC 0x51B21892 +#define PVR_440GX_RF 0x51B21894 +#define PVR_405EP_RB 0x51210950 +#define PVR_440SP_6_RAB 0x53221850 /* 440SP rev A&B with RAID 6 support enabled */ +#define PVR_440SP_RAB 0x53321850 /* 440SP rev A&B without RAID 6 support */ +#define PVR_440SP_6_RC 0x53221891 /* 440SP rev C with RAID 6 support enabled */ +#define PVR_440SP_RC 0x53321891 /* 440SP rev C without RAID 6 support */ +#define PVR_440SPe_6_RA 0x53421890 /* 440SPe rev A with RAID 6 support enabled */ +#define PVR_440SPe_RA 0x53521890 /* 440SPe rev A without RAID 6 support */ +#define PVR_440SPe_6_RB 0x53421891 /* 440SPe rev B with RAID 6 support enabled */ +#define PVR_440SPe_RB 0x53521891 /* 440SPe rev B without RAID 6 support */ +#define PVR_460EX_SE_RA 0x130218A2 /* 460EX rev A with Security Engine */ +#define PVR_460EX_RA 0x130218A3 /* 460EX rev A without Security Engine */ +#define PVR_460GT_SE_RA 0x130218A0 /* 460GT rev A with Security Engine */ +#define PVR_460GT_RA 0x130218A1 /* 460GT rev A without Security Engine */ +#define PVR_460SX_RA 0x13541800 /* 460SX rev A */ +#define PVR_460SX_RA_V1 0x13541801 /* 460SX rev A Variant 1 Security disabled */ +#define PVR_460GX_RA 0x13541802 /* 460GX rev A */ +#define PVR_460GX_RA_V1 0x13541803 /* 460GX rev A Variant 1 Security disabled */ +#define PVR_601 0x00010000 +#define PVR_602 0x00050000 +#define PVR_603 0x00030000 +#define PVR_603e 0x00060000 +#define PVR_603ev 0x00070000 +#define PVR_603r 0x00071000 +#define PVR_604 0x00040000 +#define PVR_604e 0x00090000 +#define PVR_604r 0x000A0000 +#define PVR_620 0x00140000 +#define PVR_740 0x00080000 +#define PVR_750 PVR_740 +#define PVR_740P 0x10080000 +#define PVR_750P PVR_740P +#define PVR_7400 0x000C0000 +#define PVR_7410 0x800C0000 +#define PVR_7450 0x80000000 + +#define PVR_85xx 0x80200000 +#define PVR_85xx_REV1 (PVR_85xx | 0x0010) +#define PVR_85xx_REV2 (PVR_85xx | 0x0020) + +#define PVR_86xx 0x80040000 + +#define PVR_VIRTEX5 0x7ff21912 + +/* + * For the 8xx processors, all of them report the same PVR family for + * the PowerPC core. The various versions of these processors must be + * differentiated by the version number in the Communication Processor + * Module (CPM). + */ +#define PVR_821 0x00500000 +#define PVR_823 PVR_821 +#define PVR_850 PVR_821 +#define PVR_860 PVR_821 +#define PVR_7400 0x000C0000 +#define PVR_8240 0x00810100 + +/* + * PowerQUICC II family processors report different PVR values depending + * on silicon process (HiP3, HiP4, HiP7, etc.) + */ +#define PVR_8260 PVR_8240 +#define PVR_8260_HIP3 0x00810101 +#define PVR_8260_HIP4 0x80811014 +#define PVR_8260_HIP7 0x80822011 +#define PVR_8260_HIP7R1 0x80822013 +#define PVR_8260_HIP7RA 0x80822014 + +/* + * MPC 52xx + */ +#define PVR_5200 0x80822011 +#define PVR_5200B 0x80822014 + +/* + * System Version Register + */ + +/* System Version Register (SVR) field extraction */ + +#define SVR_VER(svr) (((svr) >> 16) & 0xFFFF) /* Version field */ +#define SVR_REV(svr) (((svr) >> 0) & 0xFFFF) /* Revison field */ + +#define SVR_SUBVER(svr) (((svr) >> 8) & 0xFF) /* Process/MFG sub-version */ + +#define SVR_FAM(svr) (((svr) >> 20) & 0xFFF) /* Family field */ +#define SVR_MEM(svr) (((svr) >> 16) & 0xF) /* Member field */ + +#define SVR_MAJ(svr) (((svr) >> 4) & 0xF) /* Major revision field*/ +#define SVR_MIN(svr) (((svr) >> 0) & 0xF) /* Minor revision field*/ + +/* Some parts define SVR[0:23] as the SOC version */ +#define SVR_SOC_VER(svr) (((svr) >> 8) & 0xFFFFFF) /* SOC Version fields */ + +/* whether MPC8xxxE (i.e. has SEC) */ +#if defined(CONFIG_MPC85xx) +#define IS_E_PROCESSOR(svr) (svr & 0x80000) +#else +#if defined(CONFIG_MPC83xx) +#define IS_E_PROCESSOR(spridr) (!(spridr & 0x00010000)) +#endif +#endif + +/* + * SVR_SOC_VER() Version Values + */ + +#define SVR_8533 0x803400 +#define SVR_8533_E 0x803C00 +#define SVR_8535 0x803701 +#define SVR_8535_E 0x803F01 +#define SVR_8536 0x803700 +#define SVR_8536_E 0x803F00 +#define SVR_8540 0x803000 +#define SVR_8541 0x807200 +#define SVR_8541_E 0x807A00 +#define SVR_8543 0x803200 +#define SVR_8543_E 0x803A00 +#define SVR_8544 0x803401 +#define SVR_8544_E 0x803C01 +#define SVR_8545 0x803102 +#define SVR_8545_E 0x803902 +#define SVR_8547_E 0x803901 +#define SVR_8548 0x803100 +#define SVR_8548_E 0x803900 +#define SVR_8555 0x807100 +#define SVR_8555_E 0x807900 +#define SVR_8560 0x807000 +#define SVR_8567 0x807600 +#define SVR_8567_E 0x807E00 +#define SVR_8568 0x807500 +#define SVR_8568_E 0x807D00 +#define SVR_8569 0x808000 +#define SVR_8569_E 0x808800 +#define SVR_8572 0x80E000 +#define SVR_8572_E 0x80E800 +#define SVR_P2020 0x80E200 +#define SVR_P2020_E 0x80EA00 + +#define SVR_8610 0x80A000 +#define SVR_8641 0x809000 +#define SVR_8641D 0x809001 + +#define _GLOBAL(n)\ + .globl n;\ +n: + +/* Macros for setting and retrieving special purpose registers */ + +#define stringify(s) tostring(s) +#define tostring(s) #s + +#define mfdcr(rn) ({unsigned int rval; \ + asm volatile("mfdcr %0," stringify(rn) \ + : "=r" (rval)); rval;}) +#define mtdcr(rn, v) asm volatile("mtdcr " stringify(rn) ",%0" : : "r" (v)) + +#define mfmsr() ({unsigned int rval; \ + asm volatile("mfmsr %0" : "=r" (rval)); rval;}) +#define mtmsr(v) asm volatile("mtmsr %0" : : "r" (v)) + +#define mfspr(rn) ({unsigned int rval; \ + asm volatile("mfspr %0," stringify(rn) \ + : "=r" (rval)); rval;}) +#define mtspr(rn, v) asm volatile("mtspr " stringify(rn) ",%0" : : "r" (v)) + +#define tlbie(v) asm volatile("tlbie %0 \n sync" : : "r" (v)) + +/* Segment Registers */ + +#define SR0 0 +#define SR1 1 +#define SR2 2 +#define SR3 3 +#define SR4 4 +#define SR5 5 +#define SR6 6 +#define SR7 7 +#define SR8 8 +#define SR9 9 +#define SR10 10 +#define SR11 11 +#define SR12 12 +#define SR13 13 +#define SR14 14 +#define SR15 15 + +#ifndef __ASSEMBLY__ + +struct cpu_type { + char name[15]; + u32 soc_ver; +}; + +struct cpu_type *identify_cpu(u32 ver); + +#if defined(CONFIG_MPC85xx) || defined(CONFIG_MPC86xx) +#define CPU_TYPE_ENTRY(n, v) \ + { .name = #n, .soc_ver = SVR_##v, } +#else +#if defined(CONFIG_MPC83xx) +#define CPU_TYPE_ENTRY(x) {#x, SPR_##x} +#endif +#endif + + +#ifndef CONFIG_MACH_SPECIFIC +extern int _machine; +extern int have_of; +#endif /* CONFIG_MACH_SPECIFIC */ + +/* what kind of prep workstation we are */ +extern int _prep_type; +/* + * This is used to identify the board type from a given PReP board + * vendor. Board revision is also made available. + */ +extern unsigned char ucSystemType; +extern unsigned char ucBoardRev; +extern unsigned char ucBoardRevMaj, ucBoardRevMin; + +struct task_struct; +void start_thread(struct pt_regs *regs, unsigned long nip, unsigned long sp); +void release_thread(struct task_struct *); + +/* + * Create a new kernel thread. + */ +extern long kernel_thread(int (*fn)(void *), void *arg, unsigned long flags); + +/* + * Bus types + */ +#define EISA_bus 0 +#define EISA_bus__is_a_macro /* for versions in ksyms.c */ +#define MCA_bus 0 +#define MCA_bus__is_a_macro /* for versions in ksyms.c */ + +/* Lazy FPU handling on uni-processor */ +extern struct task_struct *last_task_used_math; +extern struct task_struct *last_task_used_altivec; + +/* + * this is the minimum allowable io space due to the location + * of the io areas on prep (first one at 0x80000000) but + * as soon as I get around to remapping the io areas with the BATs + * to match the mac we can raise this. -- Cort + */ +#define TASK_SIZE (0x80000000UL) + +/* This decides where the kernel will search for a free chunk of vm + * space during mmap's. + */ +#define TASK_UNMAPPED_BASE (TASK_SIZE / 8 * 3) + +typedef struct { + unsigned long seg; +} mm_segment_t; + +struct thread_struct { + unsigned long ksp; /* Kernel stack pointer */ + unsigned long wchan; /* Event task is sleeping on */ + struct pt_regs *regs; /* Pointer to saved register state */ + mm_segment_t fs; /* for get_fs() validation */ + void *pgdir; /* root of page-table tree */ + signed long last_syscall; + double fpr[32]; /* Complete floating point set */ + unsigned long fpscr_pad; /* fpr ... fpscr must be contiguous */ + unsigned long fpscr; /* Floating point status */ +#ifdef CONFIG_ALTIVEC + vector128 vr[32]; /* Complete AltiVec set */ + vector128 vscr; /* AltiVec status */ + unsigned long vrsave; +#endif /* CONFIG_ALTIVEC */ +}; + +#define INIT_SP (sizeof(init_stack) + (unsigned long) &init_stack) + +#define INIT_THREAD { \ + INIT_SP, /* ksp */ \ + 0, /* wchan */ \ + (struct pt_regs *)INIT_SP - 1, /* regs */ \ + KERNEL_DS, /*fs*/ \ + swapper_pg_dir, /* pgdir */ \ + 0, /* last_syscall */ \ + {0}, 0, 0 \ +} + +/* + * Note: the vm_start and vm_end fields here should *not* + * be in kernel space. (Could vm_end == vm_start perhaps?) + */ +#define INIT_MMAP { &init_mm, 0, 0x1000, NULL, \ + PAGE_SHARED, VM_READ | VM_WRITE | VM_EXEC, \ + 1, NULL, NULL } + +/* + * Return saved PC of a blocked thread. For now, this is the "user" PC + */ +static inline unsigned long thread_saved_pc(struct thread_struct *t) +{ + return (t->regs) ? t->regs->nip : 0; +} + +#define copy_segments(tsk, mm) do { } while (0) +#define release_segments(mm) do { } while (0) +#define forget_segments() do { } while (0) + +unsigned long get_wchan(struct task_struct *p); + +#define KSTK_EIP(tsk) ((tsk)->thread.regs->nip) +#define KSTK_ESP(tsk) ((tsk)->thread.regs->gpr[1]) + +/* + * NOTE! The task struct and the stack go together + */ +#define THREAD_SIZE (2*PAGE_SIZE) +#define alloc_task_struct() \ + ((struct task_struct *) __get_free_pages(GFP_KERNEL,1)) +#define free_task_struct(p) free_pages((unsigned long)(p),1) +#define get_task_struct(tsk) atomic_inc(&mem_map[MAP_NR(tsk)].count) + +/* in process.c - for early bootup debug -- Cort */ +int ll_printk(const char *, ...); +void ll_puts(const char *); + +#define init_task (init_task_union.task) +#define init_stack (init_task_union.stack) + +/* In misc.c */ +void _nmask_and_or_msr(unsigned long nmask, unsigned long or_val); + +#endif /* ndef ASSEMBLY*/ + +#ifdef CONFIG_MACH_SPECIFIC +#if defined(CONFIG_8xx) +#define _machine _MACH_8xx +#define have_of 0 +#elif defined(CONFIG_OAK) +#define _machine _MACH_oak +#define have_of 0 +#elif defined(CONFIG_WALNUT) +#define _machine _MACH_walnut +#define have_of 0 +#elif defined(CONFIG_APUS) +#define _machine _MACH_apus +#define have_of 0 +#elif defined(CONFIG_GEMINI) +#define _machine _MACH_gemini +#define have_of 0 +#elif defined(CONFIG_8260) +#define _machine _MACH_8260 +#define have_of 0 +#elif defined(CONFIG_SANDPOINT) +#define _machine _MACH_sandpoint +#elif defined(CONFIG_HIDDEN_DRAGON) +#define _machine _MACH_hidden_dragon +#define have_of 0 +#else +#error "Machine not defined correctly" +#endif +#endif /* CONFIG_MACH_SPECIFIC */ + +#endif /* __ASM_PPC_PROCESSOR_H */ diff --git a/libcpu/ppc/ppc405/include/asm/ptrace.h b/libcpu/ppc/ppc405/include/asm/ptrace.h index 8019543ab1..d531de889b 100644 --- a/libcpu/ppc/ppc405/include/asm/ptrace.h +++ b/libcpu/ppc/ppc405/include/asm/ptrace.h @@ -1,107 +1,107 @@ -#ifndef _PPC_PTRACE_H
-#define _PPC_PTRACE_H
-
-/*
- * This struct defines the way the registers are stored on the
- * kernel stack during a system call or other kernel entry.
- *
- * this should only contain volatile regs
- * since we can keep non-volatile in the thread_struct
- * should set this up when only volatiles are saved
- * by intr code.
- *
- * Since this is going on the stack, *CARE MUST BE TAKEN* to insure
- * that the overall structure is a multiple of 16 bytes in length.
- *
- * Note that the offsets of the fields in this struct correspond with
- * the PT_* values below. This simplifies arch/ppc/kernel/ptrace.c.
- */
-
-#include <config.h>
-
-#ifndef __ASSEMBLY__
-#ifdef CONFIG_PPC64BRIDGE
-#define PPC_REG unsigned long /*long*/
-#else
-#define PPC_REG unsigned long
-#endif
-struct pt_regs {
- PPC_REG gpr[32];
- PPC_REG nip;
- PPC_REG msr;
- PPC_REG orig_gpr3; /* Used for restarting system calls */
- PPC_REG ctr;
- PPC_REG link;
- PPC_REG xer;
- PPC_REG ccr;
- PPC_REG mq; /* 601 only (not used at present) */
- /* Used on APUS to hold IPL value. */
- PPC_REG trap; /* Reason for being here */
- PPC_REG dar; /* Fault registers */
- PPC_REG dsisr;
- PPC_REG result; /* Result of a system call */
-}__attribute__((packed)) CELL_STACK_FRAME_t;
-#endif
-
-#define STACK_FRAME_OVERHEAD 16 /* size of minimum stack frame */
-
-/* Size of stack frame allocated when calling signal handler. */
-#define __SIGNAL_FRAMESIZE 64
-
-#define instruction_pointer(regs) ((regs)->nip)
-#define user_mode(regs) (((regs)->msr & MSR_PR) != 0)
-
-/*
- * Offsets used by 'ptrace' system call interface.
- * These can't be changed without breaking binary compatibility
- * with MkLinux, etc.
- */
-#define PT_R0 0
-#define PT_R1 1
-#define PT_R2 2
-#define PT_R3 3
-#define PT_R4 4
-#define PT_R5 5
-#define PT_R6 6
-#define PT_R7 7
-#define PT_R8 8
-#define PT_R9 9
-#define PT_R10 10
-#define PT_R11 11
-#define PT_R12 12
-#define PT_R13 13
-#define PT_R14 14
-#define PT_R15 15
-#define PT_R16 16
-#define PT_R17 17
-#define PT_R18 18
-#define PT_R19 19
-#define PT_R20 20
-#define PT_R21 21
-#define PT_R22 22
-#define PT_R23 23
-#define PT_R24 24
-#define PT_R25 25
-#define PT_R26 26
-#define PT_R27 27
-#define PT_R28 28
-#define PT_R29 29
-#define PT_R30 30
-#define PT_R31 31
-
-#define PT_NIP 32
-#define PT_MSR 33
-#ifdef __KERNEL__
-#define PT_ORIG_R3 34
-#endif
-#define PT_CTR 35
-#define PT_LNK 36
-#define PT_XER 37
-#define PT_CCR 38
-#define PT_MQ 39
-
-#define PT_FPR0 48 /* each FP reg occupies 2 slots in this space */
-#define PT_FPR31 (PT_FPR0 + 2*31)
-#define PT_FPSCR (PT_FPR0 + 2*32 + 1)
-
-#endif
+#ifndef _PPC_PTRACE_H +#define _PPC_PTRACE_H + +/* + * This struct defines the way the registers are stored on the + * kernel stack during a system call or other kernel entry. + * + * this should only contain volatile regs + * since we can keep non-volatile in the thread_struct + * should set this up when only volatiles are saved + * by intr code. + * + * Since this is going on the stack, *CARE MUST BE TAKEN* to insure + * that the overall structure is a multiple of 16 bytes in length. + * + * Note that the offsets of the fields in this struct correspond with + * the PT_* values below. This simplifies arch/ppc/kernel/ptrace.c. + */ + +#include <config.h> + +#ifndef __ASSEMBLY__ +#ifdef CONFIG_PPC64BRIDGE +#define PPC_REG unsigned long /*long*/ +#else +#define PPC_REG unsigned long +#endif +struct pt_regs { + PPC_REG gpr[32]; + PPC_REG nip; + PPC_REG msr; + PPC_REG orig_gpr3; /* Used for restarting system calls */ + PPC_REG ctr; + PPC_REG link; + PPC_REG xer; + PPC_REG ccr; + PPC_REG mq; /* 601 only (not used at present) */ + /* Used on APUS to hold IPL value. */ + PPC_REG trap; /* Reason for being here */ + PPC_REG dar; /* Fault registers */ + PPC_REG dsisr; + PPC_REG result; /* Result of a system call */ +}__attribute__((packed)) CELL_STACK_FRAME_t; +#endif + +#define STACK_FRAME_OVERHEAD 16 /* size of minimum stack frame */ + +/* Size of stack frame allocated when calling signal handler. */ +#define __SIGNAL_FRAMESIZE 64 + +#define instruction_pointer(regs) ((regs)->nip) +#define user_mode(regs) (((regs)->msr & MSR_PR) != 0) + +/* + * Offsets used by 'ptrace' system call interface. + * These can't be changed without breaking binary compatibility + * with MkLinux, etc. + */ +#define PT_R0 0 +#define PT_R1 1 +#define PT_R2 2 +#define PT_R3 3 +#define PT_R4 4 +#define PT_R5 5 +#define PT_R6 6 +#define PT_R7 7 +#define PT_R8 8 +#define PT_R9 9 +#define PT_R10 10 +#define PT_R11 11 +#define PT_R12 12 +#define PT_R13 13 +#define PT_R14 14 +#define PT_R15 15 +#define PT_R16 16 +#define PT_R17 17 +#define PT_R18 18 +#define PT_R19 19 +#define PT_R20 20 +#define PT_R21 21 +#define PT_R22 22 +#define PT_R23 23 +#define PT_R24 24 +#define PT_R25 25 +#define PT_R26 26 +#define PT_R27 27 +#define PT_R28 28 +#define PT_R29 29 +#define PT_R30 30 +#define PT_R31 31 + +#define PT_NIP 32 +#define PT_MSR 33 +#ifdef __KERNEL__ +#define PT_ORIG_R3 34 +#endif +#define PT_CTR 35 +#define PT_LNK 36 +#define PT_XER 37 +#define PT_CCR 38 +#define PT_MQ 39 + +#define PT_FPR0 48 /* each FP reg occupies 2 slots in this space */ +#define PT_FPR31 (PT_FPR0 + 2*31) +#define PT_FPSCR (PT_FPR0 + 2*32 + 1) + +#endif diff --git a/libcpu/ppc/ppc405/include/asm/types.h b/libcpu/ppc/ppc405/include/asm/types.h index ac4133ffd4..6413895325 100644 --- a/libcpu/ppc/ppc405/include/asm/types.h +++ b/libcpu/ppc/ppc405/include/asm/types.h @@ -1,74 +1,74 @@ -#ifndef _PPC_TYPES_H
-#define _PPC_TYPES_H
-
-
-#ifndef __ASSEMBLY__
-
-typedef enum bool
- {
- FALSE = 0,
- TRUE = 1
- }BOOL;
-
-typedef unsigned short umode_t;
-
-typedef __signed__ char __s8;
-typedef unsigned char __u8;
-
-typedef __signed__ short __s16;
-typedef unsigned short __u16;
-
-typedef __signed__ int __s32;
-typedef unsigned int __u32;
-
-#if defined(__GNUC__)
-__extension__ typedef __signed__ long long __s64;
-__extension__ typedef unsigned long long __u64;
-#endif
-
-typedef struct {
- __u32 u[4];
-} __attribute__((aligned(16))) vector128;
-
-#ifdef __KERNEL__
-/*
- * These aren't exported outside the kernel to avoid name space clashes
- */
-typedef signed char s8;
-typedef unsigned char u8;
-
-typedef signed short s16;
-typedef unsigned short u16;
-
-typedef signed int s32;
-typedef unsigned int u32;
-
-typedef signed long long s64;
-typedef unsigned long long u64;
-
-typedef char INT8;
-typedef short INT16;
-typedef int INT32;
-typedef long long INT64;
-typedef unsigned char UINT8;
-typedef unsigned short UINT16;
-typedef unsigned int UINT32;
-typedef unsigned long long UINT64;
-
-#define BITS_PER_LONG 32
-
-/* DMA addresses are 32-bits wide */
-typedef u32 dma_addr_t;
-
-#ifdef CONFIG_PHYS_64BIT
-typedef unsigned long long phys_addr_t;
-typedef unsigned long long phys_size_t;
-#else
-typedef unsigned long phys_addr_t;
-typedef unsigned long phys_size_t;
-#endif
-
-#endif /* __KERNEL__ */
-#endif /* __ASSEMBLY__ */
-
-#endif
+#ifndef _PPC_TYPES_H +#define _PPC_TYPES_H + + +#ifndef __ASSEMBLY__ + +typedef enum bool + { + FALSE = 0, + TRUE = 1 + }BOOL; + +typedef unsigned short umode_t; + +typedef __signed__ char __s8; +typedef unsigned char __u8; + +typedef __signed__ short __s16; +typedef unsigned short __u16; + +typedef __signed__ int __s32; +typedef unsigned int __u32; + +#if defined(__GNUC__) +__extension__ typedef __signed__ long long __s64; +__extension__ typedef unsigned long long __u64; +#endif + +typedef struct { + __u32 u[4]; +} __attribute__((aligned(16))) vector128; + +#ifdef __KERNEL__ +/* + * These aren't exported outside the kernel to avoid name space clashes + */ +typedef signed char s8; +typedef unsigned char u8; + +typedef signed short s16; +typedef unsigned short u16; + +typedef signed int s32; +typedef unsigned int u32; + +typedef signed long long s64; +typedef unsigned long long u64; + +typedef char INT8; +typedef short INT16; +typedef int INT32; +typedef long long INT64; +typedef unsigned char UINT8; +typedef unsigned short UINT16; +typedef unsigned int UINT32; +typedef unsigned long long UINT64; + +#define BITS_PER_LONG 32 + +/* DMA addresses are 32-bits wide */ +typedef u32 dma_addr_t; + +#ifdef CONFIG_PHYS_64BIT +typedef unsigned long long phys_addr_t; +typedef unsigned long long phys_size_t; +#else +typedef unsigned long phys_addr_t; +typedef unsigned long phys_size_t; +#endif + +#endif /* __KERNEL__ */ +#endif /* __ASSEMBLY__ */ + +#endif diff --git a/libcpu/ppc/ppc405/include/config.h b/libcpu/ppc/ppc405/include/config.h index 55a930aa89..dc01549b01 100644 --- a/libcpu/ppc/ppc405/include/config.h +++ b/libcpu/ppc/ppc405/include/config.h @@ -1,58 +1,58 @@ -#ifndef __CONFIG_H
-#define __CONFIG_H
-
-#define CONFIG_405EP 1 /* this is a PPC405 CPU */
-#define CONFIG_4xx 1 /* member of PPC4xx family */
-
-#define CONFIG_SYS_DCACHE_SIZE (16 << 10)/* For AMCC 405 CPUs */
-#define CONFIG_SYS_SDRAM_BASE 0x00000000 /* _must_ be 0 */
-
-#define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */
-#define CONFIG_SYS_PROMPT "=> " /* Monitor Command Prompt */
-#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16)
-
-#define CONFIG_SYS_CLK_RECFG 0 /* Config the sys clks */
-#define CONFIG_SYS_CLK_FREQ 33333333 /*3300000*//* external frequency to pll */
-#define CONFIG_SYS_HZ 100
-#define CONFIG_SYS_PIT_RELOAD (CONFIG_SYS_CLK_FREQ / CONFIG_SYS_HZ)
-
-/*
- * UART
- */
-#define CONFIG_BAUDRATE 115200
-#define CONFIG_SERIAL_MULTI
-#define CONFIG_SYS_BAUDRATE_TABLE \
- {300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 57600, 115200, 230400}
-
-/*
- * If CONFIG_SYS_EXT_SERIAL_CLOCK, then the UART divisor is 1.
- * If CONFIG_SYS_405_UART_ERRATA_59, then UART divisor is 31.
- * Otherwise, UART divisor is determined by CPU Clock and CONFIG_SYS_BASE_BAUD value.
- * The Linux BASE_BAUD define should match this configuration.
- * baseBaud = cpuClock/(uartDivisor*16)
- * If CONFIG_SYS_405_UART_ERRATA_59 and 200MHz CPU clock,
- * set Linux BASE_BAUD to 403200.
- */
-#define CONFIG_SYS_BASE_BAUD 691200
-#define CONFIG_UART1_CONSOLE 1
-
-/*-----------------------------------------------------------------------
- * Start addresses for the final memory configuration
- * (Set up by the startup code)
- */
-#define CONFIG_SYS_FLASH_BASE 0xFFE00000
-
-/*-----------------------------------------------------------------------
- * FLASH organization
- */
-#define CONFIG_SYS_MAX_FLASH_BANKS 2 /* max number of memory banks */
-#define CONFIG_SYS_MAX_FLASH_SECT 256 /* max number of sectors on one chip */
-
-#define CONFIG_SYS_FLASH_ERASE_TOUT 120000 /* Timeout for Flash Erase (in ms) */
-#define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Timeout for Flash Write (in ms) */
-
-#define CONFIG_SYS_FLASH_ADDR0 0x555
-#define CONFIG_SYS_FLASH_ADDR1 0x2aa
-#define CONFIG_SYS_FLASH_WORD_SIZE unsigned short
-
-#endif /* __CONFIG_H */
+#ifndef __CONFIG_H +#define __CONFIG_H + +#define CONFIG_405EP 1 /* this is a PPC405 CPU */ +#define CONFIG_4xx 1 /* member of PPC4xx family */ + +#define CONFIG_SYS_DCACHE_SIZE (16 << 10)/* For AMCC 405 CPUs */ +#define CONFIG_SYS_SDRAM_BASE 0x00000000 /* _must_ be 0 */ + +#define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */ +#define CONFIG_SYS_PROMPT "=> " /* Monitor Command Prompt */ +#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) + +#define CONFIG_SYS_CLK_RECFG 0 /* Config the sys clks */ +#define CONFIG_SYS_CLK_FREQ 33333333 /*3300000*//* external frequency to pll */ +#define CONFIG_SYS_HZ 100 +#define CONFIG_SYS_PIT_RELOAD (CONFIG_SYS_CLK_FREQ / CONFIG_SYS_HZ) + +/* + * UART + */ +#define CONFIG_BAUDRATE 115200 +#define CONFIG_SERIAL_MULTI +#define CONFIG_SYS_BAUDRATE_TABLE \ + {300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 57600, 115200, 230400} + +/* + * If CONFIG_SYS_EXT_SERIAL_CLOCK, then the UART divisor is 1. + * If CONFIG_SYS_405_UART_ERRATA_59, then UART divisor is 31. + * Otherwise, UART divisor is determined by CPU Clock and CONFIG_SYS_BASE_BAUD value. + * The Linux BASE_BAUD define should match this configuration. + * baseBaud = cpuClock/(uartDivisor*16) + * If CONFIG_SYS_405_UART_ERRATA_59 and 200MHz CPU clock, + * set Linux BASE_BAUD to 403200. + */ +#define CONFIG_SYS_BASE_BAUD 691200 +#define CONFIG_UART1_CONSOLE 1 + +/*----------------------------------------------------------------------- + * Start addresses for the final memory configuration + * (Set up by the startup code) + */ +#define CONFIG_SYS_FLASH_BASE 0xFFE00000 + +/*----------------------------------------------------------------------- + * FLASH organization + */ +#define CONFIG_SYS_MAX_FLASH_BANKS 2 /* max number of memory banks */ +#define CONFIG_SYS_MAX_FLASH_SECT 256 /* max number of sectors on one chip */ + +#define CONFIG_SYS_FLASH_ERASE_TOUT 120000 /* Timeout for Flash Erase (in ms) */ +#define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Timeout for Flash Write (in ms) */ + +#define CONFIG_SYS_FLASH_ADDR0 0x555 +#define CONFIG_SYS_FLASH_ADDR1 0x2aa +#define CONFIG_SYS_FLASH_WORD_SIZE unsigned short + +#endif /* __CONFIG_H */ diff --git a/libcpu/ppc/ppc405/interrupt.c b/libcpu/ppc/ppc405/interrupt.c index 6edb81739f..d0e174612c 100644 --- a/libcpu/ppc/ppc405/interrupt.c +++ b/libcpu/ppc/ppc405/interrupt.c @@ -1,133 +1,133 @@ -/*
- * File : interrupt.c
- * This file is part of RT-Thread RTOS
- * COPYRIGHT (C) 2009, RT-Thread Development Team
- *
- * The license and distribution terms for this file may be
- * found in the file LICENSE in this distribution or at
- * http://www.rt-thread.org/license/LICENSE
- *
- * Change Logs:
- * Date Author Notes
- * 2009-01-05 Bernard first version
- */
-
-#include <rtthread.h>
-#include <asm/ppc4xx.h>
-#include <asm/processor.h>
-
-/* interrupt nest */
-extern volatile rt_uint8_t rt_interrupt_nest;
-
-/* exception and interrupt handler table */
-#define MAX_HANDLERS 32
-rt_isr_handler_t isr_table[MAX_HANDLERS];
-
-rt_uint32_t rt_interrupt_from_thread, rt_interrupt_to_thread;
-rt_uint32_t rt_thread_switch_interrput_flag;
-
-rt_isr_handler_t rt_hw_interrupt_handle(rt_uint32_t vector)
-{
- rt_kprintf("Unhandled interrupt %d occured!!!\n", vector);
- return RT_NULL;
-}
-
-void uic_irq_ack(unsigned int vec)
-{
- mtdcr(uic0sr, UIC_MASK(vec));
-}
-
-void uic_int_handler (unsigned int vec)
-{
- rt_interrupt_enter();
-
- /* Allow external interrupts to the CPU. */
- if (isr_table [vec] != 0)
- {
- (*isr_table[vec])(vec);
- }
- uic_irq_ack(vec);
-
- rt_interrupt_leave();
-}
-
-/* handler for UIC interrupt */
-void uic_interrupt(rt_uint32_t uic_base, int vec_base)
-{
- int vec;
- rt_uint32_t uic_msr;
- rt_uint32_t msr_shift;
-
- /*
- * Read masked interrupt status register to determine interrupt source
- */
- uic_msr = get_dcr(uic_base + UIC_MSR);
- msr_shift = uic_msr;
- vec = vec_base;
-
- while (msr_shift != 0)
- {
- if (msr_shift & 0x80000000)
- uic_int_handler(vec);
-
- /*
- * Shift msr to next position and increment vector
- */
- msr_shift <<= 1;
- vec++;
- }
-}
-
-void rt_hw_interrupt_install(int vector, rt_isr_handler_t new_handler, rt_isr_handler_t *old_handler)
-{
- int intVal;
-
- if (((int)vector < 0) || ((int) vector >= MAX_HANDLERS))
- {
- return; /* out of range */
- }
-
- /* install the handler in the system interrupt table */
- intVal = rt_hw_interrupt_disable (); /* lock interrupts to prevent races */
-
- if (*old_handler != RT_NULL) *old_handler = isr_table[vector];
- if (new_handler != RT_NULL) isr_table[vector] = new_handler;
-
- rt_hw_interrupt_enable (intVal);
-}
-
-void rt_hw_interrupt_mask(int vector)
-{
- mtdcr(uic0er, mfdcr(uic0er) & ~UIC_MASK(vector));
-}
-
-void rt_hw_interrupt_unmask(int vector)
-{
- mtdcr(uic0er, mfdcr(uic0er) | UIC_MASK(vector));
-}
-
-void rt_hw_interrupt_init()
-{
- int vector;
- rt_uint32_t pit_value;
-
- pit_value = RT_TICK_PER_SECOND * (100000000 / RT_CPU_FREQ);
-
- /* enable pit */
- mtspr(SPRN_PIT, pit_value);
- mtspr(SPRN_TCR, 0x4400000);
-
- /* set default interrupt handler */
- for (vector = 0; vector < MAX_HANDLERS; vector++)
- {
- isr_table [vector] = (rt_isr_handler_t)rt_hw_interrupt_handle;
- }
-
- /* initialize interrupt nest, and context in thread sp */
- rt_interrupt_nest = 0;
- rt_interrupt_from_thread = 0;
- rt_interrupt_to_thread = 0;
- rt_thread_switch_interrput_flag = 0;
-}
-
-/*@}*/
+/* + * File : interrupt.c + * This file is part of RT-Thread RTOS + * COPYRIGHT (C) 2009, RT-Thread Development Team + * + * The license and distribution terms for this file may be + * found in the file LICENSE in this distribution or at + * http://www.rt-thread.org/license/LICENSE + * + * Change Logs: + * Date Author Notes + * 2009-01-05 Bernard first version + */ + +#include <rtthread.h> +#include <asm/ppc4xx.h> +#include <asm/processor.h> + +/* interrupt nest */ +extern volatile rt_uint8_t rt_interrupt_nest; + +/* exception and interrupt handler table */ +#define MAX_HANDLERS 32 +rt_isr_handler_t isr_table[MAX_HANDLERS]; + +rt_uint32_t rt_interrupt_from_thread, rt_interrupt_to_thread; +rt_uint32_t rt_thread_switch_interrput_flag; + +rt_isr_handler_t rt_hw_interrupt_handle(rt_uint32_t vector) +{ + rt_kprintf("Unhandled interrupt %d occured!!!\n", vector); + return RT_NULL; +} + +void uic_irq_ack(unsigned int vec) +{ + mtdcr(uic0sr, UIC_MASK(vec)); +} + +void uic_int_handler (unsigned int vec) +{ + rt_interrupt_enter(); + + /* Allow external interrupts to the CPU. */ + if (isr_table [vec] != 0) + { + (*isr_table[vec])(vec); + } + uic_irq_ack(vec); + + rt_interrupt_leave(); +} + +/* handler for UIC interrupt */ +void uic_interrupt(rt_uint32_t uic_base, int vec_base) +{ + int vec; + rt_uint32_t uic_msr; + rt_uint32_t msr_shift; + + /* + * Read masked interrupt status register to determine interrupt source + */ + uic_msr = get_dcr(uic_base + UIC_MSR); + msr_shift = uic_msr; + vec = vec_base; + + while (msr_shift != 0) + { + if (msr_shift & 0x80000000) + uic_int_handler(vec); + + /* + * Shift msr to next position and increment vector + */ + msr_shift <<= 1; + vec++; + } +} + +void rt_hw_interrupt_install(int vector, rt_isr_handler_t new_handler, rt_isr_handler_t *old_handler) +{ + int intVal; + + if (((int)vector < 0) || ((int) vector >= MAX_HANDLERS)) + { + return; /* out of range */ + } + + /* install the handler in the system interrupt table */ + intVal = rt_hw_interrupt_disable (); /* lock interrupts to prevent races */ + + if (*old_handler != RT_NULL) *old_handler = isr_table[vector]; + if (new_handler != RT_NULL) isr_table[vector] = new_handler; + + rt_hw_interrupt_enable (intVal); +} + +void rt_hw_interrupt_mask(int vector) +{ + mtdcr(uic0er, mfdcr(uic0er) & ~UIC_MASK(vector)); +} + +void rt_hw_interrupt_unmask(int vector) +{ + mtdcr(uic0er, mfdcr(uic0er) | UIC_MASK(vector)); +} + +void rt_hw_interrupt_init() +{ + int vector; + rt_uint32_t pit_value; + + pit_value = RT_TICK_PER_SECOND * (100000000 / RT_CPU_FREQ); + + /* enable pit */ + mtspr(SPRN_PIT, pit_value); + mtspr(SPRN_TCR, 0x4400000); + + /* set default interrupt handler */ + for (vector = 0; vector < MAX_HANDLERS; vector++) + { + isr_table [vector] = (rt_isr_handler_t)rt_hw_interrupt_handle; + } + + /* initialize interrupt nest, and context in thread sp */ + rt_interrupt_nest = 0; + rt_interrupt_from_thread = 0; + rt_interrupt_to_thread = 0; + rt_thread_switch_interrput_flag = 0; +} + +/*@}*/ diff --git a/libcpu/ppc/ppc405/io.h b/libcpu/ppc/ppc405/io.h index 917cb5e3df..32fcd56307 100644 --- a/libcpu/ppc/ppc405/io.h +++ b/libcpu/ppc/ppc405/io.h @@ -1,93 +1,93 @@ -#ifndef __IO_H__
-#define __IO_H__
-
-#define __iomem
-
-/*
- * 8, 16 and 32 bit, big and little endian I/O operations, with barrier.
- *
- * Read operations have additional twi & isync to make sure the read
- * is actually performed (i.e. the data has come back) before we start
- * executing any following instructions.
- */
-static inline int in_8(const volatile unsigned char __iomem *addr)
-{
- int ret;
-
- __asm__ __volatile__(
- "sync; lbz%U1%X1 %0,%1;\n"
- "twi 0,%0,0;\n"
- "isync" : "=r" (ret) : "m" (*addr));
- return ret;
-}
-
-static inline void out_8(volatile unsigned char __iomem *addr, int val)
-{
- __asm__ __volatile__("stb%U0%X0 %1,%0; eieio" : "=m" (*addr) : "r" (val));
-}
-
-extern inline int in_le16(const volatile unsigned short __iomem *addr)
-{
- int ret;
-
- __asm__ __volatile__("sync; lhbrx %0,0,%1;\n"
- "twi 0,%0,0;\n"
- "isync" : "=r" (ret) :
- "r" (addr), "m" (*addr));
- return ret;
-}
-
-extern inline int in_be16(const volatile unsigned short __iomem *addr)
-{
- int ret;
-
- __asm__ __volatile__("sync; lhz%U1%X1 %0,%1;\n"
- "twi 0,%0,0;\n"
- "isync" : "=r" (ret) : "m" (*addr));
- return ret;
-}
-
-extern inline void out_le16(volatile unsigned short __iomem *addr, int val)
-{
- __asm__ __volatile__("sync; sthbrx %1,0,%2" : "=m" (*addr) :
- "r" (val), "r" (addr));
-}
-
-extern inline void out_be16(volatile unsigned short __iomem *addr, int val)
-{
- __asm__ __volatile__("sync; sth%U0%X0 %1,%0" : "=m" (*addr) : "r" (val));
-}
-
-extern inline unsigned in_le32(const volatile unsigned __iomem *addr)
-{
- unsigned ret;
-
- __asm__ __volatile__("sync; lwbrx %0,0,%1;\n"
- "twi 0,%0,0;\n"
- "isync" : "=r" (ret) :
- "r" (addr), "m" (*addr));
- return ret;
-}
-
-extern inline unsigned in_be32(const volatile unsigned __iomem *addr)
-{
- unsigned ret;
-
- __asm__ __volatile__("sync; lwz%U1%X1 %0,%1;\n"
- "twi 0,%0,0;\n"
- "isync" : "=r" (ret) : "m" (*addr));
- return ret;
-}
-
-extern inline void out_le32(volatile unsigned __iomem *addr, int val)
-{
- __asm__ __volatile__("sync; stwbrx %1,0,%2" : "=m" (*addr) :
- "r" (val), "r" (addr));
-}
-
-extern inline void out_be32(volatile unsigned __iomem *addr, int val)
-{
- __asm__ __volatile__("sync; stw%U0%X0 %1,%0" : "=m" (*addr) : "r" (val));
-}
-
-#endif
+#ifndef __IO_H__ +#define __IO_H__ + +#define __iomem + +/* + * 8, 16 and 32 bit, big and little endian I/O operations, with barrier. + * + * Read operations have additional twi & isync to make sure the read + * is actually performed (i.e. the data has come back) before we start + * executing any following instructions. + */ +static inline int in_8(const volatile unsigned char __iomem *addr) +{ + int ret; + + __asm__ __volatile__( + "sync; lbz%U1%X1 %0,%1;\n" + "twi 0,%0,0;\n" + "isync" : "=r" (ret) : "m" (*addr)); + return ret; +} + +static inline void out_8(volatile unsigned char __iomem *addr, int val) +{ + __asm__ __volatile__("stb%U0%X0 %1,%0; eieio" : "=m" (*addr) : "r" (val)); +} + +extern inline int in_le16(const volatile unsigned short __iomem *addr) +{ + int ret; + + __asm__ __volatile__("sync; lhbrx %0,0,%1;\n" + "twi 0,%0,0;\n" + "isync" : "=r" (ret) : + "r" (addr), "m" (*addr)); + return ret; +} + +extern inline int in_be16(const volatile unsigned short __iomem *addr) +{ + int ret; + + __asm__ __volatile__("sync; lhz%U1%X1 %0,%1;\n" + "twi 0,%0,0;\n" + "isync" : "=r" (ret) : "m" (*addr)); + return ret; +} + +extern inline void out_le16(volatile unsigned short __iomem *addr, int val) +{ + __asm__ __volatile__("sync; sthbrx %1,0,%2" : "=m" (*addr) : + "r" (val), "r" (addr)); +} + +extern inline void out_be16(volatile unsigned short __iomem *addr, int val) +{ + __asm__ __volatile__("sync; sth%U0%X0 %1,%0" : "=m" (*addr) : "r" (val)); +} + +extern inline unsigned in_le32(const volatile unsigned __iomem *addr) +{ + unsigned ret; + + __asm__ __volatile__("sync; lwbrx %0,0,%1;\n" + "twi 0,%0,0;\n" + "isync" : "=r" (ret) : + "r" (addr), "m" (*addr)); + return ret; +} + +extern inline unsigned in_be32(const volatile unsigned __iomem *addr) +{ + unsigned ret; + + __asm__ __volatile__("sync; lwz%U1%X1 %0,%1;\n" + "twi 0,%0,0;\n" + "isync" : "=r" (ret) : "m" (*addr)); + return ret; +} + +extern inline void out_le32(volatile unsigned __iomem *addr, int val) +{ + __asm__ __volatile__("sync; stwbrx %1,0,%2" : "=m" (*addr) : + "r" (val), "r" (addr)); +} + +extern inline void out_be32(volatile unsigned __iomem *addr, int val) +{ + __asm__ __volatile__("sync; stw%U0%X0 %1,%0" : "=m" (*addr) : "r" (val)); +} + +#endif diff --git a/libcpu/ppc/ppc405/serial.c b/libcpu/ppc/ppc405/serial.c index 4c1a605adc..ca935fafdd 100644 --- a/libcpu/ppc/ppc405/serial.c +++ b/libcpu/ppc/ppc405/serial.c @@ -1,319 +1,319 @@ -#include <rthw.h>
-#include <rtthread.h>
-
-#include "io.h"
-#include <asm/ppc4xx-intvec.h>
-
-#define UART0_BASE 0xef600300
-#define UART1_BASE 0xef600400
-#define UCR0_MASK 0x0000007f
-#define UCR1_MASK 0x00007f00
-#define UCR0_UDIV_POS 0
-#define UCR1_UDIV_POS 8
-#define UDIV_MAX 127
-
-#define UART_RBR 0x00
-#define UART_THR 0x00
-#define UART_IER 0x01
-#define UART_IIR 0x02
-#define UART_FCR 0x02
-#define UART_LCR 0x03
-#define UART_MCR 0x04
-#define UART_LSR 0x05
-#define UART_MSR 0x06
-#define UART_SCR 0x07
-#define UART_DLL 0x00
-#define UART_DLM 0x01
-
-/*-----------------------------------------------------------------------------+
- | Line Status Register.
- +-----------------------------------------------------------------------------*/
-#define asyncLSRDataReady1 0x01
-#define asyncLSROverrunError1 0x02
-#define asyncLSRParityError1 0x04
-#define asyncLSRFramingError1 0x08
-#define asyncLSRBreakInterrupt1 0x10
-#define asyncLSRTxHoldEmpty1 0x20
-#define asyncLSRTxShiftEmpty1 0x40
-#define asyncLSRRxFifoError1 0x80
-
-/* PPC405 serial device */
-struct rt_ppc405_serial
-{
- /* inherit from device */
- struct rt_device parent;
-
- rt_uint32_t hw_base;
- rt_uint32_t irqno;
- rt_uint32_t baudrate;
-
- /* reception field */
- rt_uint16_t save_index, read_index;
- rt_uint8_t rx_buffer[RT_UART_RX_BUFFER_SIZE];
-};
-struct rt_ppc405_serial ppc405_serial;
-
-/* serial character device */
-static rt_err_t rt_serial_init (rt_device_t dev)
-{
- return RT_EOK;
-}
-
-static rt_err_t rt_serial_open(rt_device_t dev, rt_uint16_t oflag)
-{
- struct rt_ppc405_serial* device;
- device = (struct rt_ppc405_serial*) dev;
-
- RT_ASSERT(device != RT_NULL);
- if (dev->flag & RT_DEVICE_FLAG_INT_RX)
- {
- /* Enable "RX Data Available" Interrupt on UART */
- out_8((rt_uint8_t*)device->hw_base + UART_IER, 0x01);
- /* Setup UART FIFO: RX trigger level: 1 byte, Enable FIFO */
- out_8((rt_uint8_t*)device->hw_base + UART_FCR, 1);
-
- /* init UART rx interrupt */
- rt_hw_interrupt_unmask(device->irqno);
- }
-
- return RT_EOK;
-}
-
-static rt_err_t rt_serial_close(rt_device_t dev)
-{
- struct rt_ppc405_serial* device;
- device = (struct rt_ppc405_serial*) dev;
-
- RT_ASSERT(device != RT_NULL);
- if (dev->flag & RT_DEVICE_FLAG_INT_RX)
- {
- /* mask UART rx interrupt */
- rt_hw_interrupt_mask(device->irqno);
- }
-
- return RT_EOK;
-}
-
-static rt_err_t rt_serial_control(rt_device_t dev, rt_uint8_t cmd, void *args)
-{
- return RT_EOK;
-}
-
-static rt_size_t rt_serial_read(rt_device_t dev, rt_off_t pos, void* buffer, rt_size_t size)
-{
- rt_uint8_t* ptr;
- struct rt_ppc405_serial* device;
-
- device = (struct rt_ppc405_serial*) dev;
- RT_ASSERT(device != RT_NULL);
-
- /* point to buffer */
- ptr = (rt_uint8_t*) buffer;
-
- if (dev->flag & RT_DEVICE_FLAG_INT_RX)
- {
- while (size)
- {
- /* interrupt receive */
- rt_base_t level;
-
- /* disable interrupt */
- level = rt_hw_interrupt_disable();
- if (device->read_index != device->save_index)
- {
- *ptr = device->rx_buffer[device->read_index];
-
- device->read_index ++;
- if (device->read_index >= RT_UART_RX_BUFFER_SIZE)
- device->read_index = 0;
- }
- else
- {
- /* no data in rx buffer */
-
- /* enable interrupt */
- rt_hw_interrupt_enable(level);
- break;
- }
-
- /* enable interrupt */
- rt_hw_interrupt_enable(level);
-
- ptr ++; size --;
- }
-
- return (rt_uint32_t)ptr - (rt_uint32_t)buffer;
- }
- else if (dev->flag & RT_DEVICE_FLAG_DMA_RX)
- {
- /* not support right now */
- RT_ASSERT(0);
- }
-
- /* polling mode */
- RT_ASSERT(0);
-
- return (rt_size_t)ptr - (rt_size_t)buffer;
-}
-
-static rt_size_t rt_serial_write(rt_device_t dev, rt_off_t pos, const void* buffer, rt_size_t size)
-{
- char *ptr;
- struct rt_ppc405_serial* device;
-
- device = (struct rt_ppc405_serial*) dev;
- RT_ASSERT(device != RT_NULL);
-
- if (dev->flag & RT_DEVICE_FLAG_INT_TX)
- {
- /* not support */
- RT_ASSERT(0);
- }
- else if (dev->flag & RT_DEVICE_FLAG_DMA_TX)
- {
- /* not support */
- RT_ASSERT(0);
- }
-
- /* polling write */
- ptr = (char *)buffer;
-
- if (dev->flag & RT_DEVICE_FLAG_STREAM)
- {
- /* stream mode */
- while (size)
- {
- if (*ptr == '\n')
- {
- while ((in_8((rt_uint8_t*)device->hw_base + UART_LSR) & 0x20) != 0x20);
- out_8((rt_uint8_t*)device->hw_base + UART_THR, '\r');
- }
-
- while ((in_8((rt_uint8_t*)device->hw_base + UART_LSR) & 0x20) != 0x20);
- out_8((rt_uint8_t*)device->hw_base + UART_THR, *ptr);
-
- ptr ++;
- size --;
- }
- }
- else
- {
- while (size)
- {
- while ((in_8((rt_uint8_t*)device->hw_base + UART_LSR) & 0x20) != 0x20);
- out_8((rt_uint8_t*)device->hw_base + UART_THR, *ptr);
-
- ptr ++;
- size --;
- }
- }
-
- return (rt_size_t) ptr - (rt_size_t) buffer;
-}
-
-void rt_serial_set_baudrate(struct rt_ppc405_serial* device)
-{
- rt_uint32_t bdiv;
-
- bdiv = 115200;
- out_8((rt_uint8_t *)device->hw_base + UART_DLL, bdiv); /* set baudrate divisor */
- out_8((rt_uint8_t *)device->hw_base + UART_DLM, bdiv >> 8); /* set baudrate divisor */
-}
-
-void rt_serial_isr(int irqno)
-{
- unsigned char status;
- struct rt_ppc405_serial *device;
-
- device = (struct rt_ppc405_serial*) &ppc405_serial;
- status = in_8((rt_uint8_t *)device->hw_base + UART_LSR);
-
- if (status & 0x01)
- {
- rt_base_t level;
-
- while (status & 0x01)
- {
- /* disable interrupt */
- level = rt_hw_interrupt_disable();
-
- /* read character */
- device->rx_buffer[device->save_index] = (0xff & (int) in_8((rt_uint8_t *)device->hw_base));
- device->save_index ++;
- if (device->save_index >= RT_UART_RX_BUFFER_SIZE)
- device->save_index = 0;
-
- /* if the next position is read index, discard this 'read char' */
- if (device->save_index == device->read_index)
- {
- device->read_index ++;
- if (device->read_index >= RT_UART_RX_BUFFER_SIZE)
- device->read_index = 0;
- }
-
- /* enable interrupt */
- rt_hw_interrupt_enable(level);
-
- /* check error */
- if ((status & ( asyncLSRFramingError1 |
- asyncLSROverrunError1 |
- asyncLSRParityError1 |
- asyncLSRBreakInterrupt1 )) != 0)
- {
- out_8((rt_uint8_t *)device->hw_base + UART_LSR,
- asyncLSRFramingError1 |
- asyncLSROverrunError1 |
- asyncLSRParityError1 |
- asyncLSRBreakInterrupt1);
- }
-
- status = in_8((rt_uint8_t *)device->hw_base + UART_LSR);
- }
-
- /* invoke callback */
- if(device->parent.rx_indicate != RT_NULL)
- {
- device->parent.rx_indicate(&device->parent, 1);
- }
- }
-}
-
-void rt_hw_serial_init(void)
-{
- volatile rt_uint8_t val;
- struct rt_ppc405_serial* device;
-
- device = (struct rt_ppc405_serial*) &ppc405_serial;
- device->parent.type = RT_Device_Class_Char;
-
- device->hw_base = UART0_BASE;
- device->baudrate = 115200;
- device->irqno = VECNUM_U0;
- rt_hw_interrupt_install(device->irqno, rt_serial_isr, RT_NULL); /* install isr */
-
- rt_memset(device->rx_buffer, 0, sizeof(device->rx_buffer));
- device->read_index = device->save_index = 0;
-
- out_8((rt_uint8_t *)device->hw_base + UART_LCR, 0x80); /* set DLAB bit */
- /* setup baudrate */
- rt_serial_set_baudrate(device);
- out_8((rt_uint8_t *)device->hw_base + UART_LCR, 0x03); /* clear DLAB; set 8 bits, no parity */
- out_8((rt_uint8_t *)device->hw_base + UART_FCR, 0x00); /* disable FIFO */
- out_8((rt_uint8_t *)device->hw_base + UART_MCR, 0x00); /* no modem control DTR RTS */
- val = in_8((rt_uint8_t *)device->hw_base + UART_LSR); /* clear line status */
- val = in_8((rt_uint8_t *)device->hw_base + UART_RBR); /* read receive buffer */
- out_8((rt_uint8_t *)device->hw_base + UART_SCR, 0x00); /* set scratchpad */
- out_8((rt_uint8_t *)device->hw_base + UART_IER, 0x00); /* set interrupt enable reg */
-
- device->parent.type = RT_Device_Class_Char;
- device->parent.init = rt_serial_init;
- device->parent.open = rt_serial_open;
- device->parent.close = rt_serial_close;
- device->parent.read = rt_serial_read;
- device->parent.write = rt_serial_write;
- device->parent.control = rt_serial_control;
- device->parent.user_data = RT_NULL;
-
- rt_device_register(&device->parent,
- "uart1", RT_DEVICE_FLAG_RDWR | RT_DEVICE_FLAG_INT_RX | RT_DEVICE_FLAG_STREAM);
-}
+#include <rthw.h> +#include <rtthread.h> + +#include "io.h" +#include <asm/ppc4xx-intvec.h> + +#define UART0_BASE 0xef600300 +#define UART1_BASE 0xef600400 +#define UCR0_MASK 0x0000007f +#define UCR1_MASK 0x00007f00 +#define UCR0_UDIV_POS 0 +#define UCR1_UDIV_POS 8 +#define UDIV_MAX 127 + +#define UART_RBR 0x00 +#define UART_THR 0x00 +#define UART_IER 0x01 +#define UART_IIR 0x02 +#define UART_FCR 0x02 +#define UART_LCR 0x03 +#define UART_MCR 0x04 +#define UART_LSR 0x05 +#define UART_MSR 0x06 +#define UART_SCR 0x07 +#define UART_DLL 0x00 +#define UART_DLM 0x01 + +/*-----------------------------------------------------------------------------+ + | Line Status Register. + +-----------------------------------------------------------------------------*/ +#define asyncLSRDataReady1 0x01 +#define asyncLSROverrunError1 0x02 +#define asyncLSRParityError1 0x04 +#define asyncLSRFramingError1 0x08 +#define asyncLSRBreakInterrupt1 0x10 +#define asyncLSRTxHoldEmpty1 0x20 +#define asyncLSRTxShiftEmpty1 0x40 +#define asyncLSRRxFifoError1 0x80 + +/* PPC405 serial device */ +struct rt_ppc405_serial +{ + /* inherit from device */ + struct rt_device parent; + + rt_uint32_t hw_base; + rt_uint32_t irqno; + rt_uint32_t baudrate; + + /* reception field */ + rt_uint16_t save_index, read_index; + rt_uint8_t rx_buffer[RT_UART_RX_BUFFER_SIZE]; +}; +struct rt_ppc405_serial ppc405_serial; + +/* serial character device */ +static rt_err_t rt_serial_init (rt_device_t dev) +{ + return RT_EOK; +} + +static rt_err_t rt_serial_open(rt_device_t dev, rt_uint16_t oflag) +{ + struct rt_ppc405_serial* device; + device = (struct rt_ppc405_serial*) dev; + + RT_ASSERT(device != RT_NULL); + if (dev->flag & RT_DEVICE_FLAG_INT_RX) + { + /* Enable "RX Data Available" Interrupt on UART */ + out_8((rt_uint8_t*)device->hw_base + UART_IER, 0x01); + /* Setup UART FIFO: RX trigger level: 1 byte, Enable FIFO */ + out_8((rt_uint8_t*)device->hw_base + UART_FCR, 1); + + /* init UART rx interrupt */ + rt_hw_interrupt_unmask(device->irqno); + } + + return RT_EOK; +} + +static rt_err_t rt_serial_close(rt_device_t dev) +{ + struct rt_ppc405_serial* device; + device = (struct rt_ppc405_serial*) dev; + + RT_ASSERT(device != RT_NULL); + if (dev->flag & RT_DEVICE_FLAG_INT_RX) + { + /* mask UART rx interrupt */ + rt_hw_interrupt_mask(device->irqno); + } + + return RT_EOK; +} + +static rt_err_t rt_serial_control(rt_device_t dev, rt_uint8_t cmd, void *args) +{ + return RT_EOK; +} + +static rt_size_t rt_serial_read(rt_device_t dev, rt_off_t pos, void* buffer, rt_size_t size) +{ + rt_uint8_t* ptr; + struct rt_ppc405_serial* device; + + device = (struct rt_ppc405_serial*) dev; + RT_ASSERT(device != RT_NULL); + + /* point to buffer */ + ptr = (rt_uint8_t*) buffer; + + if (dev->flag & RT_DEVICE_FLAG_INT_RX) + { + while (size) + { + /* interrupt receive */ + rt_base_t level; + + /* disable interrupt */ + level = rt_hw_interrupt_disable(); + if (device->read_index != device->save_index) + { + *ptr = device->rx_buffer[device->read_index]; + + device->read_index ++; + if (device->read_index >= RT_UART_RX_BUFFER_SIZE) + device->read_index = 0; + } + else + { + /* no data in rx buffer */ + + /* enable interrupt */ + rt_hw_interrupt_enable(level); + break; + } + + /* enable interrupt */ + rt_hw_interrupt_enable(level); + + ptr ++; size --; + } + + return (rt_uint32_t)ptr - (rt_uint32_t)buffer; + } + else if (dev->flag & RT_DEVICE_FLAG_DMA_RX) + { + /* not support right now */ + RT_ASSERT(0); + } + + /* polling mode */ + RT_ASSERT(0); + + return (rt_size_t)ptr - (rt_size_t)buffer; +} + +static rt_size_t rt_serial_write(rt_device_t dev, rt_off_t pos, const void* buffer, rt_size_t size) +{ + char *ptr; + struct rt_ppc405_serial* device; + + device = (struct rt_ppc405_serial*) dev; + RT_ASSERT(device != RT_NULL); + + if (dev->flag & RT_DEVICE_FLAG_INT_TX) + { + /* not support */ + RT_ASSERT(0); + } + else if (dev->flag & RT_DEVICE_FLAG_DMA_TX) + { + /* not support */ + RT_ASSERT(0); + } + + /* polling write */ + ptr = (char *)buffer; + + if (dev->flag & RT_DEVICE_FLAG_STREAM) + { + /* stream mode */ + while (size) + { + if (*ptr == '\n') + { + while ((in_8((rt_uint8_t*)device->hw_base + UART_LSR) & 0x20) != 0x20); + out_8((rt_uint8_t*)device->hw_base + UART_THR, '\r'); + } + + while ((in_8((rt_uint8_t*)device->hw_base + UART_LSR) & 0x20) != 0x20); + out_8((rt_uint8_t*)device->hw_base + UART_THR, *ptr); + + ptr ++; + size --; + } + } + else + { + while (size) + { + while ((in_8((rt_uint8_t*)device->hw_base + UART_LSR) & 0x20) != 0x20); + out_8((rt_uint8_t*)device->hw_base + UART_THR, *ptr); + + ptr ++; + size --; + } + } + + return (rt_size_t) ptr - (rt_size_t) buffer; +} + +void rt_serial_set_baudrate(struct rt_ppc405_serial* device) +{ + rt_uint32_t bdiv; + + bdiv = 115200; + out_8((rt_uint8_t *)device->hw_base + UART_DLL, bdiv); /* set baudrate divisor */ + out_8((rt_uint8_t *)device->hw_base + UART_DLM, bdiv >> 8); /* set baudrate divisor */ +} + +void rt_serial_isr(int irqno) +{ + unsigned char status; + struct rt_ppc405_serial *device; + + device = (struct rt_ppc405_serial*) &ppc405_serial; + status = in_8((rt_uint8_t *)device->hw_base + UART_LSR); + + if (status & 0x01) + { + rt_base_t level; + + while (status & 0x01) + { + /* disable interrupt */ + level = rt_hw_interrupt_disable(); + + /* read character */ + device->rx_buffer[device->save_index] = (0xff & (int) in_8((rt_uint8_t *)device->hw_base)); + device->save_index ++; + if (device->save_index >= RT_UART_RX_BUFFER_SIZE) + device->save_index = 0; + + /* if the next position is read index, discard this 'read char' */ + if (device->save_index == device->read_index) + { + device->read_index ++; + if (device->read_index >= RT_UART_RX_BUFFER_SIZE) + device->read_index = 0; + } + + /* enable interrupt */ + rt_hw_interrupt_enable(level); + + /* check error */ + if ((status & ( asyncLSRFramingError1 | + asyncLSROverrunError1 | + asyncLSRParityError1 | + asyncLSRBreakInterrupt1 )) != 0) + { + out_8((rt_uint8_t *)device->hw_base + UART_LSR, + asyncLSRFramingError1 | + asyncLSROverrunError1 | + asyncLSRParityError1 | + asyncLSRBreakInterrupt1); + } + + status = in_8((rt_uint8_t *)device->hw_base + UART_LSR); + } + + /* invoke callback */ + if(device->parent.rx_indicate != RT_NULL) + { + device->parent.rx_indicate(&device->parent, 1); + } + } +} + +void rt_hw_serial_init(void) +{ + volatile rt_uint8_t val; + struct rt_ppc405_serial* device; + + device = (struct rt_ppc405_serial*) &ppc405_serial; + device->parent.type = RT_Device_Class_Char; + + device->hw_base = UART0_BASE; + device->baudrate = 115200; + device->irqno = VECNUM_U0; + rt_hw_interrupt_install(device->irqno, rt_serial_isr, RT_NULL); /* install isr */ + + rt_memset(device->rx_buffer, 0, sizeof(device->rx_buffer)); + device->read_index = device->save_index = 0; + + out_8((rt_uint8_t *)device->hw_base + UART_LCR, 0x80); /* set DLAB bit */ + /* setup baudrate */ + rt_serial_set_baudrate(device); + out_8((rt_uint8_t *)device->hw_base + UART_LCR, 0x03); /* clear DLAB; set 8 bits, no parity */ + out_8((rt_uint8_t *)device->hw_base + UART_FCR, 0x00); /* disable FIFO */ + out_8((rt_uint8_t *)device->hw_base + UART_MCR, 0x00); /* no modem control DTR RTS */ + val = in_8((rt_uint8_t *)device->hw_base + UART_LSR); /* clear line status */ + val = in_8((rt_uint8_t *)device->hw_base + UART_RBR); /* read receive buffer */ + out_8((rt_uint8_t *)device->hw_base + UART_SCR, 0x00); /* set scratchpad */ + out_8((rt_uint8_t *)device->hw_base + UART_IER, 0x00); /* set interrupt enable reg */ + + device->parent.type = RT_Device_Class_Char; + device->parent.init = rt_serial_init; + device->parent.open = rt_serial_open; + device->parent.close = rt_serial_close; + device->parent.read = rt_serial_read; + device->parent.write = rt_serial_write; + device->parent.control = rt_serial_control; + device->parent.user_data = RT_NULL; + + rt_device_register(&device->parent, + "uart1", RT_DEVICE_FLAG_RDWR | RT_DEVICE_FLAG_INT_RX | RT_DEVICE_FLAG_STREAM); +} diff --git a/libcpu/ppc/ppc405/traps.c b/libcpu/ppc/ppc405/traps.c index 292927b328..1deecbc92b 100644 --- a/libcpu/ppc/ppc405/traps.c +++ b/libcpu/ppc/ppc405/traps.c @@ -1,208 +1,208 @@ -#include <rtthread.h>
-#include <asm/processor.h>
-#include <asm/ppc4xx-uic.h>
-
-/* Returns 0 if exception not found and fixup otherwise. */
-extern unsigned long search_exception_table(unsigned long);
-
-/* THIS NEEDS CHANGING to use the board info structure.
- */
-#define END_OF_MEM 0x800000
-#define UICB0_ALL 0
-
-#define ESR_MCI 0x80000000
-#define ESR_PIL 0x08000000
-#define ESR_PPR 0x04000000
-#define ESR_PTR 0x02000000
-#define ESR_DST 0x00800000
-#define ESR_DIZ 0x00400000
-#define ESR_U0F 0x00008000
-
-rt_inline void set_tsr(unsigned long val)
-{
- mtspr(SPRN_TSR, val);
-}
-
-rt_inline rt_uint32_t get_esr(void)
-{
- rt_uint32_t val;
-
- val = mfspr(SPRN_ESR);
- return val;
-}
-
-/*
- * Trap & Exception support
- */
-
-void print_backtrace(unsigned long *sp)
-{
- int cnt = 0;
- unsigned long i;
-
- rt_kprintf("Call backtrace: ");
- while (sp) {
- if ((rt_uint32_t)sp > END_OF_MEM)
- break;
-
- i = sp[1];
- if (cnt++ % 7 == 0)
- rt_kprintf("\n");
- rt_kprintf("%08lX ", i);
- if (cnt > 32) break;
- sp = (unsigned long *)*sp;
- }
- rt_kprintf("\n");
-}
-
-void show_regs(struct pt_regs * regs)
-{
- int i;
-
- rt_kprintf("NIP: %08lX XER: %08lX LR: %08lX REGS: %p TRAP: %04lx DEAR: %08lX\n",
- regs->nip, regs->xer, regs->link, regs, regs->trap, regs->dar);
- rt_kprintf("MSR: %08lx EE: %01x PR: %01x FP: %01x ME: %01x IR/DR: %01x%01x\n",
- regs->msr, regs->msr&MSR_EE ? 1 : 0, regs->msr&MSR_PR ? 1 : 0,
- regs->msr & MSR_FP ? 1 : 0,regs->msr&MSR_ME ? 1 : 0,
- regs->msr&MSR_IR ? 1 : 0,
- regs->msr&MSR_DR ? 1 : 0);
-
- rt_kprintf("\n");
- for (i = 0; i < 32; i++) {
- if ((i % 8) == 0) {
- rt_kprintf("GPR%02d: ", i);
- }
-
- rt_kprintf("%08lX ", regs->gpr[i]);
- if ((i % 8) == 7) {
- rt_kprintf("\n");
- }
- }
-}
-
-void panic(const char *fmt, ...)
-{
- while(1);
-}
-
-void
-_exception(int signr, struct pt_regs *regs)
-{
- show_regs(regs);
- print_backtrace((unsigned long *)regs->gpr[1]);
- panic("Exception");
-}
-
-unsigned long
-search_exception_table(unsigned long addr)
-{
- unsigned long ret = 0;
-
- /* There is only the kernel to search. */
- // ret = search_one_table(__start___ex_table, __stop___ex_table-1, addr);
- /* if the serial port does not hang in exception, rt_kprintf can be used */
- if (ret) return ret;
-
- return 0;
-}
-
-/*
- * Handle external interrupts
- */
-void external_interrupt(struct pt_regs *regs)
-{
- u32 uic_msr;
-
- /*
- * Read masked interrupt status register to determine interrupt source
- */
- uic_msr = mfdcr(uic0msr);
-
- mtdcr(uic0sr, (uic_msr & UICB0_ALL));
-
- if (uic_msr & ~(UICB0_ALL))
- {
- uic_interrupt(UIC0_DCR_BASE, 0);
- }
-
- return;
-}
-
-void MachineCheckException(struct pt_regs *regs)
-{
- unsigned long fixup, val;
-
- if ((fixup = search_exception_table(regs->nip)) != 0) {
- regs->nip = fixup;
- val = mfspr(MCSR);
- /* Clear MCSR */
- mtspr(SPRN_MCSR, val);
- return;
- }
-
- rt_kprintf("Machine Check Exception.\n");
- rt_kprintf("Caused by (from msr): ");
- rt_kprintf("regs %p ", regs);
-
- val = get_esr();
-
- if (val& ESR_IMCP) {
- rt_kprintf("Instruction");
- mtspr(ESR, val & ~ESR_IMCP);
- } else {
- rt_kprintf("Data");
- }
- rt_kprintf(" machine check.\n");
-
- show_regs(regs);
- print_backtrace((unsigned long *)regs->gpr[1]);
- panic("machine check");
-}
-
-void AlignmentException(struct pt_regs *regs)
-{
- show_regs(regs);
- print_backtrace((unsigned long *)regs->gpr[1]);
- panic("Alignment Exception");
-}
-
-void ProgramCheckException(struct pt_regs *regs)
-{
- long esr_val;
-
- show_regs(regs);
-
- esr_val = get_esr();
- if( esr_val & ESR_PIL )
- rt_kprintf( "** Illegal Instruction **\n" );
- else if( esr_val & ESR_PPR )
- rt_kprintf( "** Privileged Instruction **\n" );
- else if( esr_val & ESR_PTR )
- rt_kprintf( "** Trap Instruction **\n" );
-
- print_backtrace((unsigned long *)regs->gpr[1]);
- panic("Program Check Exception");
-}
-
-void DecrementerPITException(struct pt_regs *regs)
-{
- /* reset PIT interrupt */
- set_tsr(0x08000000);
-
- /* increase a OS Tick */
- rt_tick_increase();
-}
-
-void UnknownException(struct pt_regs *regs)
-{
-
- rt_kprintf("Bad trap at PC: %lx, SR: %lx, vector=%lx\n",
- regs->nip, regs->msr, regs->trap);
- _exception(0, regs);
-}
-
-void DebugException(struct pt_regs *regs)
-{
- rt_kprintf("Debugger trap at @ %lx @regs %lx\n", regs->nip, (rt_uint32_t)regs );
- show_regs(regs);
-}
+#include <rtthread.h> +#include <asm/processor.h> +#include <asm/ppc4xx-uic.h> + +/* Returns 0 if exception not found and fixup otherwise. */ +extern unsigned long search_exception_table(unsigned long); + +/* THIS NEEDS CHANGING to use the board info structure. + */ +#define END_OF_MEM 0x800000 +#define UICB0_ALL 0 + +#define ESR_MCI 0x80000000 +#define ESR_PIL 0x08000000 +#define ESR_PPR 0x04000000 +#define ESR_PTR 0x02000000 +#define ESR_DST 0x00800000 +#define ESR_DIZ 0x00400000 +#define ESR_U0F 0x00008000 + +rt_inline void set_tsr(unsigned long val) +{ + mtspr(SPRN_TSR, val); +} + +rt_inline rt_uint32_t get_esr(void) +{ + rt_uint32_t val; + + val = mfspr(SPRN_ESR); + return val; +} + +/* + * Trap & Exception support + */ + +void print_backtrace(unsigned long *sp) +{ + int cnt = 0; + unsigned long i; + + rt_kprintf("Call backtrace: "); + while (sp) { + if ((rt_uint32_t)sp > END_OF_MEM) + break; + + i = sp[1]; + if (cnt++ % 7 == 0) + rt_kprintf("\n"); + rt_kprintf("%08lX ", i); + if (cnt > 32) break; + sp = (unsigned long *)*sp; + } + rt_kprintf("\n"); +} + +void show_regs(struct pt_regs * regs) +{ + int i; + + rt_kprintf("NIP: %08lX XER: %08lX LR: %08lX REGS: %p TRAP: %04lx DEAR: %08lX\n", + regs->nip, regs->xer, regs->link, regs, regs->trap, regs->dar); + rt_kprintf("MSR: %08lx EE: %01x PR: %01x FP: %01x ME: %01x IR/DR: %01x%01x\n", + regs->msr, regs->msr&MSR_EE ? 1 : 0, regs->msr&MSR_PR ? 1 : 0, + regs->msr & MSR_FP ? 1 : 0,regs->msr&MSR_ME ? 1 : 0, + regs->msr&MSR_IR ? 1 : 0, + regs->msr&MSR_DR ? 1 : 0); + + rt_kprintf("\n"); + for (i = 0; i < 32; i++) { + if ((i % 8) == 0) { + rt_kprintf("GPR%02d: ", i); + } + + rt_kprintf("%08lX ", regs->gpr[i]); + if ((i % 8) == 7) { + rt_kprintf("\n"); + } + } +} + +void panic(const char *fmt, ...) +{ + while(1); +} + +void +_exception(int signr, struct pt_regs *regs) +{ + show_regs(regs); + print_backtrace((unsigned long *)regs->gpr[1]); + panic("Exception"); +} + +unsigned long +search_exception_table(unsigned long addr) +{ + unsigned long ret = 0; + + /* There is only the kernel to search. */ + // ret = search_one_table(__start___ex_table, __stop___ex_table-1, addr); + /* if the serial port does not hang in exception, rt_kprintf can be used */ + if (ret) return ret; + + return 0; +} + +/* + * Handle external interrupts + */ +void external_interrupt(struct pt_regs *regs) +{ + u32 uic_msr; + + /* + * Read masked interrupt status register to determine interrupt source + */ + uic_msr = mfdcr(uic0msr); + + mtdcr(uic0sr, (uic_msr & UICB0_ALL)); + + if (uic_msr & ~(UICB0_ALL)) + { + uic_interrupt(UIC0_DCR_BASE, 0); + } + + return; +} + +void MachineCheckException(struct pt_regs *regs) +{ + unsigned long fixup, val; + + if ((fixup = search_exception_table(regs->nip)) != 0) { + regs->nip = fixup; + val = mfspr(MCSR); + /* Clear MCSR */ + mtspr(SPRN_MCSR, val); + return; + } + + rt_kprintf("Machine Check Exception.\n"); + rt_kprintf("Caused by (from msr): "); + rt_kprintf("regs %p ", regs); + + val = get_esr(); + + if (val& ESR_IMCP) { + rt_kprintf("Instruction"); + mtspr(ESR, val & ~ESR_IMCP); + } else { + rt_kprintf("Data"); + } + rt_kprintf(" machine check.\n"); + + show_regs(regs); + print_backtrace((unsigned long *)regs->gpr[1]); + panic("machine check"); +} + +void AlignmentException(struct pt_regs *regs) +{ + show_regs(regs); + print_backtrace((unsigned long *)regs->gpr[1]); + panic("Alignment Exception"); +} + +void ProgramCheckException(struct pt_regs *regs) +{ + long esr_val; + + show_regs(regs); + + esr_val = get_esr(); + if( esr_val & ESR_PIL ) + rt_kprintf( "** Illegal Instruction **\n" ); + else if( esr_val & ESR_PPR ) + rt_kprintf( "** Privileged Instruction **\n" ); + else if( esr_val & ESR_PTR ) + rt_kprintf( "** Trap Instruction **\n" ); + + print_backtrace((unsigned long *)regs->gpr[1]); + panic("Program Check Exception"); +} + +void DecrementerPITException(struct pt_regs *regs) +{ + /* reset PIT interrupt */ + set_tsr(0x08000000); + + /* increase a OS Tick */ + rt_tick_increase(); +} + +void UnknownException(struct pt_regs *regs) +{ + + rt_kprintf("Bad trap at PC: %lx, SR: %lx, vector=%lx\n", + regs->nip, regs->msr, regs->trap); + _exception(0, regs); +} + +void DebugException(struct pt_regs *regs) +{ + rt_kprintf("Debugger trap at @ %lx @regs %lx\n", regs->nip, (rt_uint32_t)regs ); + show_regs(regs); +} diff --git a/libcpu/sim/win32/cpu_port.c b/libcpu/sim/win32/cpu_port.c index 5969d2e8d1..38c387b196 100644 --- a/libcpu/sim/win32/cpu_port.c +++ b/libcpu/sim/win32/cpu_port.c @@ -1,677 +1,677 @@ -/*
-************************************************************************************************************************
-* File : cpu_port.c
-* By : xyou
-* Version : V1.00.00
-*
-* By : prife
-* Version : V1.00.01
-************************************************************************************************************************
-*/
-
-/*
-*********************************************************************************************************
-* INCLUDE FILES
-*********************************************************************************************************
-*/
-#include <rtthread.h>
-#include <windows.h>
-#include <mmsystem.h>
-#include <stdio.h>
-#include "cpu_port.h"
-
-/*
-*********************************************************************************************************
-* WinThread STRUCTURE
-* Windows runs each task in a thread.
-* The context switch is managed by the threads.So the task stack does not have to be managed directly,
-* although the stack stack is still used to hold an WinThreadState structure this is the only thing it
-* will be ever hold.
-* the structure indirectly maps the task handle to a thread handle
-*********************************************************************************************************
-*/
-typedef struct
-{
- void *Param; //Thread param
- void (*Entry)(void *); //Thread entry
- void (*Exit)(void); //Thread exit
- HANDLE ThreadHandle;
- DWORD ThreadID;
-}win_thread_t;
-
-const DWORD MS_VC_EXCEPTION=0x406D1388;
-
-#pragma pack(push,8)
-typedef struct tagTHREADNAME_INFO
-{
- DWORD dwType; // Must be 0x1000.
- LPCSTR szName; // Pointer to name (in user addr space).
- DWORD dwThreadID; // Thread ID (-1=caller thread).
- DWORD dwFlags; // Reserved for future use, must be zero.
-} THREADNAME_INFO;
-#pragma pack(pop)
-
-/*
-*********************************************************************************************************
-* LOCAL DEFINES
-*********************************************************************************************************
-*/
-#define MAX_INTERRUPT_NUM ((rt_uint32_t)sizeof(rt_uint32_t) * 8)
-
-/*
- * Simulated interrupt waiting to be processed.this is a bit mask where each bit represent one interrupt
- * so a maximum of 32 interrupts can be simulated
- */
-static volatile rt_uint32_t CpuPendingInterrupts = 0;
-
-/*
- * An event used to inform the simulated interrupt processing thread (a high priority thread
- * that simulated interrupt processing) that an interrupt is pending
- */
-static HANDLE hInterruptEventHandle = NULL;
-
-/*
- * Mutex used to protect all the simulated interrupt variables that are accessed by multiple threads
- */
-static HANDLE hInterruptEventMutex = NULL;
-
-/*
- * Handler for all the simulate software interrupts.
- * The first two positions are used the Yield and Tick interrupt so are handled slightly differently
- * all the other interrupts can be user defined
-*/
-static rt_uint32_t (*CpuIsrHandler[MAX_INTERRUPT_NUM])(void) = {0};
-
-/*
- * Handler for OSTick Thread
- */
-static HANDLE OSTick_Thread;
-static DWORD OSTick_ThreadID;
-static HANDLE OSTick_SignalPtr;
-static TIMECAPS OSTick_TimerCap;
-static MMRESULT OSTick_TimerID;
-
-/*
- * flag in interrupt handling
- */
-rt_uint32_t rt_interrupt_from_thread, rt_interrupt_to_thread;
-rt_uint32_t rt_thread_switch_interrupt_flag;
-
-/*
-*********************************************************************************************************
-* PRIVATE FUNCTION PROTOTYPES
-*********************************************************************************************************
-*/
-//static void WinThreadScheduler(void);
-void WinThreadScheduler(void);
-rt_uint32_t YieldInterruptHandle(void);
-rt_uint32_t SysTickInterruptHandle(void);
-static DWORD WINAPI ThreadforSysTickTimer(LPVOID lpParam);
-static DWORD WINAPI ThreadforKeyGet(LPVOID lpParam);
-
-static void SetThreadName(DWORD dwThreadID, char* threadName)
-{
- THREADNAME_INFO info;
- info.dwType = 0x1000;
- info.szName = threadName;
- info.dwThreadID = dwThreadID;
- info.dwFlags = 0;
-
- __try
- {
- RaiseException( MS_VC_EXCEPTION, 0, sizeof(info)/sizeof(ULONG_PTR), (ULONG_PTR*)&info );
- }
- __except(EXCEPTION_EXECUTE_HANDLER)
- {
- }
-}
-
-/*
-*********************************************************************************************************
-* rt_hw_stack_init()
-* Description : Initialize stack of thread
-* Argument(s) : void *pvEntry,void *pvParam,rt_uint8_t *pStackAddr,void *pvExit
-* Return(s) : rt_uint8_t*
-* Caller(s) : rt_thread_init or rt_thread_create
-* Note(s) : none
-*********************************************************************************************************
-*/
-
-static DWORD WINAPI thread_run( LPVOID lpThreadParameter )
-{
- rt_thread_t tid = rt_thread_self();
- win_thread_t *pWinThread = (win_thread_t *)lpThreadParameter;
-
- SetThreadName(GetCurrentThreadId(), tid->name);
-
- pWinThread->Entry(pWinThread->Param);
-
- pWinThread->Exit();
- return 0;
-}
-
-rt_uint8_t* rt_hw_stack_init(void *pEntry,void *pParam,rt_uint8_t *pStackAddr,void *pExit)
-{
- win_thread_t *pWinThread = NULL;
-
- /*
- * In this simulated case a stack is not initialized
- * The thread handles the context switching itself. The WinThreadState object is placed onto the stack
- * that was created for the task
- * so the stack buffer is still used,just not in the conventional way.
- */
- pWinThread = (win_thread_t *)(pStackAddr - sizeof(win_thread_t));
-
- pWinThread->Entry = pEntry;
- pWinThread->Param = pParam;
- pWinThread->Exit = pExit;
-
- pWinThread->ThreadHandle = NULL;
- pWinThread->ThreadID = 0;
-
- /* Create the winthread */
- pWinThread->ThreadHandle = CreateThread(NULL,
- 0,
- (LPTHREAD_START_ROUTINE) thread_run,
- pWinThread,
- CREATE_SUSPENDED,
- &(pWinThread->ThreadID));
- SetThreadAffinityMask(pWinThread->ThreadHandle,
- 0x01);
- SetThreadPriorityBoost(pWinThread->ThreadHandle,
- TRUE);
- SetThreadPriority(pWinThread->ThreadHandle,
- THREAD_PRIORITY_IDLE);
-
- return (rt_uint8_t*)pWinThread;
-} /*** rt_hw_stack_init ***/
-
-/*
-*********************************************************************************************************
-* rt_hw_interrupt_disable()
-* Description : disable cpu interrupts
-* Argument(s) : void
-* Return(s) : rt_base_t
-* Caller(s) : Applicatios or os_kernel
-* Note(s) : none
-*********************************************************************************************************
-*/
-rt_base_t rt_hw_interrupt_disable(void)
-{
- if(hInterruptEventMutex != NULL)
- {
- WaitForSingleObject(hInterruptEventMutex,INFINITE);
- }
-
- return 0;
-} /*** rt_hw_interrupt_disable ***/
-
-
-/*
-*********************************************************************************************************
-* rt_hw_interrupt_enable()
-* Description : enable cpu interrupts
-* Argument(s) : rt_base_t level
-* Return(s) : void
-* Caller(s) : Applications or os_kernel
-* Note(s) : none
-*********************************************************************************************************
-*/
-void rt_hw_interrupt_enable(rt_base_t level)
-{
- level = level;
-
- if (hInterruptEventMutex != NULL)
- {
- ReleaseMutex(hInterruptEventMutex);
- }
-
-} /*** rt_hw_interrupt_enable ***/
-
-/*
-*********************************************************************************************************
-* rt_hw_context_switch_interrupt()
-* Description : switch thread's contex
-* Argument(s) : void
-* Return(s) : void
-* Caller(s) : os kernel
-* Note(s) : none
-*********************************************************************************************************
-*/
-void rt_hw_context_switch_interrupt(rt_uint32_t from,
- rt_uint32_t to)
-{
- if(rt_thread_switch_interrupt_flag != 1)
- {
- rt_thread_switch_interrupt_flag = 1;
-
- // set rt_interrupt_from_thread
- rt_interrupt_from_thread = *((rt_uint32_t *)(from));
- }
-
- rt_interrupt_to_thread = *((rt_uint32_t *)(to));
-
- //trigger YIELD exception(cause context switch)
- TriggerSimulateInterrupt(CPU_INTERRUPT_YIELD);
-} /*** rt_hw_context_switch_interrupt ***/
-
-
-
-void rt_hw_context_switch(rt_uint32_t from,
- rt_uint32_t to)
-{
- if(rt_thread_switch_interrupt_flag != 1)
- {
- rt_thread_switch_interrupt_flag = 1;
-
- // set rt_interrupt_from_thread
- rt_interrupt_from_thread = *((rt_uint32_t *)(from));
-
- }
-
- // set rt_interrupt_to_thread
- rt_interrupt_to_thread = *((rt_uint32_t *)(to));
-
- //trigger YIELD exception(cause contex switch)
- TriggerSimulateInterrupt(CPU_INTERRUPT_YIELD);
-
-} /*** rt_hw_context_switch ***/
-
-/*
-*********************************************************************************************************
-* rt_hw_context_switch_to()
-* Description : switch to new thread
-* Argument(s) : rt_uint32_t to //the stack address of the thread which will switch to
-* Return(s) : void
-* Caller(s) : rt_thread schecale
-* Note(s) : this function is used to perform the first thread switch
-*********************************************************************************************************
-*/
-void rt_hw_context_switch_to(rt_uint32_t to)
-{
- //set to thread
- rt_interrupt_to_thread = *((rt_uint32_t *)(to));
-
- //clear from thread
- rt_interrupt_from_thread = 0;
-
- //set interrupt to 1
- rt_thread_switch_interrupt_flag = 1;
-
- //start WinThreadScheduler
- WinThreadScheduler();
-
- //never reach here!
- return;
-
-} /*** rt_hw_context_switch_to ***/
-
-
-
-/*
-*********************************************************************************************************
-* TriggerSimulateInterrupt()
-* Description : Trigger a simulated interrupts handle
-* Argument(s) : t_uint32_t IntIndex
-* Return(s) : void
-* Caller(s) : Applications
-* Note(s) : none
-*********************************************************************************************************
-*/
-void TriggerSimulateInterrupt(rt_uint32_t IntIndex)
-{
- if((IntIndex < MAX_INTERRUPT_NUM) && (hInterruptEventMutex != NULL))
- {
- /* Yield interrupts are processed even when critical nesting is non-zero */
- WaitForSingleObject(hInterruptEventMutex,
- INFINITE);
-
- CpuPendingInterrupts |= (1 << IntIndex);
-
- SetEvent(hInterruptEventHandle);
-
- ReleaseMutex(hInterruptEventMutex);
- }
-} /*** TriggerSimulateInterrupt ***/
-
-/*
-*********************************************************************************************************
-* RegisterSimulateInterrupt()
-* Description : Register a interrupt handle to simulate paltform
-* Argument(s) : rt_uint32_t IntIndex,rt_uint32_t (*IntHandler)(void)
-* Return(s) : void
-* Caller(s) : Applications
-* Note(s) : none
-*********************************************************************************************************
-*/
-void RegisterSimulateInterrupt(rt_uint32_t IntIndex,rt_uint32_t (*IntHandler)(void))
-{
- if(IntIndex < MAX_INTERRUPT_NUM)
- {
- if (hInterruptEventMutex != NULL)
- {
- WaitForSingleObject(hInterruptEventMutex,
- INFINITE);
-
- CpuIsrHandler[IntIndex] = IntHandler;
-
- ReleaseMutex(hInterruptEventMutex);
- }
- else
- {
- CpuIsrHandler[IntIndex] = IntHandler;
- }
- }
-
-} /*** RegisterSimulateInterrupt ***/
-
-
-
-/*
-*********************************************************************************************************
-* PRIVATE FUNCTION
-*********************************************************************************************************
-*/
-
-/*
-*********************************************************************************************************
-* WinThreadScheduler()
-* Description : Handle all simulate interrupts
-* Argument(s) : void
-* Return(s) : static void
-* Caller(s) : os scachle
-* Note(s) : none
-*********************************************************************************************************
-*/
-#define WIN_WM_MIN_RES (1)
- void WinThreadScheduler(void)
-{
- HANDLE hInterruptObjectList[2];
- HANDLE hThreadHandle;
- rt_uint32_t SwitchRequiredMask;
- rt_uint32_t i;
-
- win_thread_t *WinThreadFrom;
- win_thread_t *WinThreadTo;
-
- /*
- * Install the interrupt handlers used bye scheduler itself
- */
- RegisterSimulateInterrupt(CPU_INTERRUPT_YIELD,
- YieldInterruptHandle);
- RegisterSimulateInterrupt(CPU_INTERRUPT_TICK,
- SysTickInterruptHandle);
-
- /*
- * Create the events and mutex that are used to synchronise all the WinThreads
- */
- hInterruptEventMutex = CreateMutex(NULL,
- FALSE,
- NULL);
- hInterruptEventHandle = CreateEvent(NULL,
- FALSE,
- FALSE,
- NULL);
-
- if((hInterruptEventMutex == NULL) || (hInterruptEventHandle == NULL))
- {
- return;
- }
-
- /*
- * Set the priority of this WinThread such that it is above the priority of the WinThreads
- * that run rt-threads.
- * This is higher priority is required to ensure simulate interrupts take priority over rt-threads
- */
- hThreadHandle = GetCurrentThread();
- if(hThreadHandle == NULL)
- {
- return;
- }
-
- if (SetThreadPriority(hThreadHandle,
- THREAD_PRIORITY_HIGHEST) == 0)
- {
- return;
- }
- SetThreadPriorityBoost(hThreadHandle,
- TRUE);
- SetThreadAffinityMask(hThreadHandle,
- 0x01);
-
- /*
- * Start the thread that simulates the timer peripheral to generate tick interrupts.
- */
- OSTick_Thread = CreateThread(NULL,
- 0,
- ThreadforSysTickTimer,
- 0,
- CREATE_SUSPENDED,
- &OSTick_ThreadID);
- if(OSTick_Thread == NULL)
- {
- //Display Error Message
-
-
- return;
- }
- SetThreadPriority(OSTick_Thread,
- THREAD_PRIORITY_NORMAL);
- SetThreadPriorityBoost(OSTick_Thread,
- TRUE);
- SetThreadAffinityMask(OSTick_Thread,
- 0x01);
-
- /*
- * Set timer Caps
- */
- if (timeGetDevCaps(&OSTick_TimerCap,
- sizeof(OSTick_TimerCap)) != TIMERR_NOERROR)
- {
-
- CloseHandle(OSTick_Thread);
-
- return;
- }
- if (OSTick_TimerCap.wPeriodMin < WIN_WM_MIN_RES)
- {
- OSTick_TimerCap.wPeriodMin = WIN_WM_MIN_RES;
- }
-
- if(timeBeginPeriod(OSTick_TimerCap.wPeriodMin) != TIMERR_NOERROR)
- {
- CloseHandle(OSTick_Thread);
-
- return;
- }
-
- OSTick_SignalPtr = CreateEvent(NULL,TRUE,FALSE,NULL);
- if(OSTick_SignalPtr == NULL)
- {
- // disp error message
-
- timeEndPeriod(OSTick_TimerCap.wPeriodMin);
- CloseHandle(OSTick_Thread);
-
- return;
- }
-
- OSTick_TimerID = timeSetEvent((UINT ) (1000 / RT_TICK_PER_SECOND) ,
- (UINT ) OSTick_TimerCap.wPeriodMin,
- (LPTIMECALLBACK ) OSTick_SignalPtr,
- (DWORD_PTR ) NULL,
- (UINT ) (TIME_PERIODIC | TIME_CALLBACK_EVENT_SET));
-
- if(OSTick_TimerID == 0)
- {
- //disp
-
- CloseHandle(OSTick_SignalPtr);
- timeEndPeriod(OSTick_TimerCap.wPeriodMin);
- CloseHandle(OSTick_Thread);
-
- return;
- }
-
- /*
- * Start OS Tick Thread an release Interrupt Mutex
- */
- ResumeThread(OSTick_Thread);
- ReleaseMutex( hInterruptEventMutex );
-
- //trigger YEILD INTERRUPT
- TriggerSimulateInterrupt(CPU_INTERRUPT_YIELD);
-
- /*
- * block on the mutex that ensure exclusive access to the simulated interrupt objects
- * and the events that signals that a simulated interrupt should be processed.
- */
-
- hInterruptObjectList[0] = hInterruptEventHandle;
- hInterruptObjectList[1] = hInterruptEventMutex;
-
-
- while (1)
- {
- WaitForMultipleObjects(sizeof(hInterruptObjectList) / sizeof(HANDLE),
- hInterruptObjectList,
- TRUE,
- INFINITE);
-
- /*
- * Used to indicate whether the simulate interrupt processing has necessitated a contex
- * switch to another thread
- */
- SwitchRequiredMask = 0;
-
- /*
- * For each interrupt we are interested in processing ,each of which is represented
- * by a bit in the 32bit CpuPendingInterrupts variable.
- */
- for (i = 0; i < MAX_INTERRUPT_NUM; ++i)
- {
- /* is the simulated interrupt pending ? */
- if (CpuPendingInterrupts & (1UL << i))
- {
- /* Is a handler installed ?*/
- if (CpuIsrHandler[i] != NULL)
- {
- /* Run the actual handler */
- if (CpuIsrHandler[i]() != 0)
- {
- SwitchRequiredMask |= (1UL << i);
- }
- }
-
- /* Clear the interrupt pending bit */
- CpuPendingInterrupts &= ~(1UL << i);
- }
- }
-
- if(SwitchRequiredMask != 0)
- {
- WinThreadFrom = (win_thread_t *)rt_interrupt_from_thread;
- WinThreadTo = (win_thread_t *)rt_interrupt_to_thread;
-
- if ((WinThreadFrom != NULL) && (WinThreadFrom->ThreadHandle != NULL))
- {
- SuspendThread(WinThreadFrom->ThreadHandle);
- }
-
- ResumeThread(WinThreadTo->ThreadHandle);
-
- }
-
- ReleaseMutex(hInterruptEventMutex);
- }
-} /*** WinThreadScheduler ***/
-
-
-
-/*
-*********************************************************************************************************
-* ThreadforSysTickTimer()
-* Description : win thread to simulate a systick timer
-* Argument(s) : LPVOID lpParam
-* Return(s) : static DWORD WINAPI
-* Caller(s) : none
-* Note(s) : This is not a real time way of generating tick events as the next wake time should be relative
-* to the previous wake time,not the time Sleep() is called.
-* It is done this way to prevent overruns in this very non real time simulated/emulated environment
-*********************************************************************************************************
-*/
-static DWORD WINAPI ThreadforSysTickTimer(LPVOID lpParam)
-{
-
- (void)lpParam; //prevent compiler warnings
-
- for(;;)
- {
- /*
- * Wait until the timer expires and we can access the simulated interrupt variables.
- */
- WaitForSingleObject(OSTick_SignalPtr,INFINITE);
-
- ResetEvent(OSTick_SignalPtr);
-
- /*
- * Trigger a systick interrupt
- */
- TriggerSimulateInterrupt(CPU_INTERRUPT_TICK);
-
- }
-
- return 0;
-
-} /*** prvThreadforSysTickTimer ***/
-
-/*
-*********************************************************************************************************
-* SysTickInterruptHandle()
-* Description : Interrupt handle for systick
-* Argument(s) : void
-* Return(s) : rt_uint32_t
-* Caller(s) : none
-* Note(s) : none
-*********************************************************************************************************
-*/
-rt_uint32_t SysTickInterruptHandle(void)
-{
-
- /* enter interrupt */
- rt_interrupt_enter();
-
- rt_tick_increase();
-
- /* leave interrupt */
- rt_interrupt_leave();
-
- return 0;
-} /*** SysTickInterruptHandle ***/
-
-/*
-*********************************************************************************************************
-* YieldInterruptHandle()
-* Description : Interrupt handle for Yield
-* Argument(s) : void
-* Return(s) : rt_uint32_t
-* Caller(s) : none
-* Note(s) : none
-*********************************************************************************************************
-*/
-rt_uint32_t YieldInterruptHandle(void)
-{
-
- /*
- * if rt_thread_switch_interrupt_flag = 1 yield already handled
- */
- if(rt_thread_switch_interrupt_flag != 0)
- {
- rt_thread_switch_interrupt_flag = 0;
-
- /* return thread switch request = 1 */
- return 1;
- }
-
- return 0;
-} /*** YieldInterruptHandle ***/
+/* +************************************************************************************************************************ +* File : cpu_port.c +* By : xyou +* Version : V1.00.00 +* +* By : prife +* Version : V1.00.01 +************************************************************************************************************************ +*/ + +/* +********************************************************************************************************* +* INCLUDE FILES +********************************************************************************************************* +*/ +#include <rtthread.h> +#include <windows.h> +#include <mmsystem.h> +#include <stdio.h> +#include "cpu_port.h" + +/* +********************************************************************************************************* +* WinThread STRUCTURE +* Windows runs each task in a thread. +* The context switch is managed by the threads.So the task stack does not have to be managed directly, +* although the stack stack is still used to hold an WinThreadState structure this is the only thing it +* will be ever hold. +* the structure indirectly maps the task handle to a thread handle +********************************************************************************************************* +*/ +typedef struct +{ + void *Param; //Thread param + void (*Entry)(void *); //Thread entry + void (*Exit)(void); //Thread exit + HANDLE ThreadHandle; + DWORD ThreadID; +}win_thread_t; + +const DWORD MS_VC_EXCEPTION=0x406D1388; + +#pragma pack(push,8) +typedef struct tagTHREADNAME_INFO +{ + DWORD dwType; // Must be 0x1000. + LPCSTR szName; // Pointer to name (in user addr space). + DWORD dwThreadID; // Thread ID (-1=caller thread). + DWORD dwFlags; // Reserved for future use, must be zero. +} THREADNAME_INFO; +#pragma pack(pop) + +/* +********************************************************************************************************* +* LOCAL DEFINES +********************************************************************************************************* +*/ +#define MAX_INTERRUPT_NUM ((rt_uint32_t)sizeof(rt_uint32_t) * 8) + +/* + * Simulated interrupt waiting to be processed.this is a bit mask where each bit represent one interrupt + * so a maximum of 32 interrupts can be simulated + */ +static volatile rt_uint32_t CpuPendingInterrupts = 0; + +/* + * An event used to inform the simulated interrupt processing thread (a high priority thread + * that simulated interrupt processing) that an interrupt is pending + */ +static HANDLE hInterruptEventHandle = NULL; + +/* + * Mutex used to protect all the simulated interrupt variables that are accessed by multiple threads + */ +static HANDLE hInterruptEventMutex = NULL; + +/* + * Handler for all the simulate software interrupts. + * The first two positions are used the Yield and Tick interrupt so are handled slightly differently + * all the other interrupts can be user defined +*/ +static rt_uint32_t (*CpuIsrHandler[MAX_INTERRUPT_NUM])(void) = {0}; + +/* + * Handler for OSTick Thread + */ +static HANDLE OSTick_Thread; +static DWORD OSTick_ThreadID; +static HANDLE OSTick_SignalPtr; +static TIMECAPS OSTick_TimerCap; +static MMRESULT OSTick_TimerID; + +/* + * flag in interrupt handling + */ +rt_uint32_t rt_interrupt_from_thread, rt_interrupt_to_thread; +rt_uint32_t rt_thread_switch_interrupt_flag; + +/* +********************************************************************************************************* +* PRIVATE FUNCTION PROTOTYPES +********************************************************************************************************* +*/ +//static void WinThreadScheduler(void); +void WinThreadScheduler(void); +rt_uint32_t YieldInterruptHandle(void); +rt_uint32_t SysTickInterruptHandle(void); +static DWORD WINAPI ThreadforSysTickTimer(LPVOID lpParam); +static DWORD WINAPI ThreadforKeyGet(LPVOID lpParam); + +static void SetThreadName(DWORD dwThreadID, char* threadName) +{ + THREADNAME_INFO info; + info.dwType = 0x1000; + info.szName = threadName; + info.dwThreadID = dwThreadID; + info.dwFlags = 0; + + __try + { + RaiseException( MS_VC_EXCEPTION, 0, sizeof(info)/sizeof(ULONG_PTR), (ULONG_PTR*)&info ); + } + __except(EXCEPTION_EXECUTE_HANDLER) + { + } +} + +/* +********************************************************************************************************* +* rt_hw_stack_init() +* Description : Initialize stack of thread +* Argument(s) : void *pvEntry,void *pvParam,rt_uint8_t *pStackAddr,void *pvExit +* Return(s) : rt_uint8_t* +* Caller(s) : rt_thread_init or rt_thread_create +* Note(s) : none +********************************************************************************************************* +*/ + +static DWORD WINAPI thread_run( LPVOID lpThreadParameter ) +{ + rt_thread_t tid = rt_thread_self(); + win_thread_t *pWinThread = (win_thread_t *)lpThreadParameter; + + SetThreadName(GetCurrentThreadId(), tid->name); + + pWinThread->Entry(pWinThread->Param); + + pWinThread->Exit(); + return 0; +} + +rt_uint8_t* rt_hw_stack_init(void *pEntry,void *pParam,rt_uint8_t *pStackAddr,void *pExit) +{ + win_thread_t *pWinThread = NULL; + + /* + * In this simulated case a stack is not initialized + * The thread handles the context switching itself. The WinThreadState object is placed onto the stack + * that was created for the task + * so the stack buffer is still used,just not in the conventional way. + */ + pWinThread = (win_thread_t *)(pStackAddr - sizeof(win_thread_t)); + + pWinThread->Entry = pEntry; + pWinThread->Param = pParam; + pWinThread->Exit = pExit; + + pWinThread->ThreadHandle = NULL; + pWinThread->ThreadID = 0; + + /* Create the winthread */ + pWinThread->ThreadHandle = CreateThread(NULL, + 0, + (LPTHREAD_START_ROUTINE) thread_run, + pWinThread, + CREATE_SUSPENDED, + &(pWinThread->ThreadID)); + SetThreadAffinityMask(pWinThread->ThreadHandle, + 0x01); + SetThreadPriorityBoost(pWinThread->ThreadHandle, + TRUE); + SetThreadPriority(pWinThread->ThreadHandle, + THREAD_PRIORITY_IDLE); + + return (rt_uint8_t*)pWinThread; +} /*** rt_hw_stack_init ***/ + +/* +********************************************************************************************************* +* rt_hw_interrupt_disable() +* Description : disable cpu interrupts +* Argument(s) : void +* Return(s) : rt_base_t +* Caller(s) : Applicatios or os_kernel +* Note(s) : none +********************************************************************************************************* +*/ +rt_base_t rt_hw_interrupt_disable(void) +{ + if(hInterruptEventMutex != NULL) + { + WaitForSingleObject(hInterruptEventMutex,INFINITE); + } + + return 0; +} /*** rt_hw_interrupt_disable ***/ + + +/* +********************************************************************************************************* +* rt_hw_interrupt_enable() +* Description : enable cpu interrupts +* Argument(s) : rt_base_t level +* Return(s) : void +* Caller(s) : Applications or os_kernel +* Note(s) : none +********************************************************************************************************* +*/ +void rt_hw_interrupt_enable(rt_base_t level) +{ + level = level; + + if (hInterruptEventMutex != NULL) + { + ReleaseMutex(hInterruptEventMutex); + } + +} /*** rt_hw_interrupt_enable ***/ + +/* +********************************************************************************************************* +* rt_hw_context_switch_interrupt() +* Description : switch thread's contex +* Argument(s) : void +* Return(s) : void +* Caller(s) : os kernel +* Note(s) : none +********************************************************************************************************* +*/ +void rt_hw_context_switch_interrupt(rt_uint32_t from, + rt_uint32_t to) +{ + if(rt_thread_switch_interrupt_flag != 1) + { + rt_thread_switch_interrupt_flag = 1; + + // set rt_interrupt_from_thread + rt_interrupt_from_thread = *((rt_uint32_t *)(from)); + } + + rt_interrupt_to_thread = *((rt_uint32_t *)(to)); + + //trigger YIELD exception(cause context switch) + TriggerSimulateInterrupt(CPU_INTERRUPT_YIELD); +} /*** rt_hw_context_switch_interrupt ***/ + + + +void rt_hw_context_switch(rt_uint32_t from, + rt_uint32_t to) +{ + if(rt_thread_switch_interrupt_flag != 1) + { + rt_thread_switch_interrupt_flag = 1; + + // set rt_interrupt_from_thread + rt_interrupt_from_thread = *((rt_uint32_t *)(from)); + + } + + // set rt_interrupt_to_thread + rt_interrupt_to_thread = *((rt_uint32_t *)(to)); + + //trigger YIELD exception(cause contex switch) + TriggerSimulateInterrupt(CPU_INTERRUPT_YIELD); + +} /*** rt_hw_context_switch ***/ + +/* +********************************************************************************************************* +* rt_hw_context_switch_to() +* Description : switch to new thread +* Argument(s) : rt_uint32_t to //the stack address of the thread which will switch to +* Return(s) : void +* Caller(s) : rt_thread schecale +* Note(s) : this function is used to perform the first thread switch +********************************************************************************************************* +*/ +void rt_hw_context_switch_to(rt_uint32_t to) +{ + //set to thread + rt_interrupt_to_thread = *((rt_uint32_t *)(to)); + + //clear from thread + rt_interrupt_from_thread = 0; + + //set interrupt to 1 + rt_thread_switch_interrupt_flag = 1; + + //start WinThreadScheduler + WinThreadScheduler(); + + //never reach here! + return; + +} /*** rt_hw_context_switch_to ***/ + + + +/* +********************************************************************************************************* +* TriggerSimulateInterrupt() +* Description : Trigger a simulated interrupts handle +* Argument(s) : t_uint32_t IntIndex +* Return(s) : void +* Caller(s) : Applications +* Note(s) : none +********************************************************************************************************* +*/ +void TriggerSimulateInterrupt(rt_uint32_t IntIndex) +{ + if((IntIndex < MAX_INTERRUPT_NUM) && (hInterruptEventMutex != NULL)) + { + /* Yield interrupts are processed even when critical nesting is non-zero */ + WaitForSingleObject(hInterruptEventMutex, + INFINITE); + + CpuPendingInterrupts |= (1 << IntIndex); + + SetEvent(hInterruptEventHandle); + + ReleaseMutex(hInterruptEventMutex); + } +} /*** TriggerSimulateInterrupt ***/ + +/* +********************************************************************************************************* +* RegisterSimulateInterrupt() +* Description : Register a interrupt handle to simulate paltform +* Argument(s) : rt_uint32_t IntIndex,rt_uint32_t (*IntHandler)(void) +* Return(s) : void +* Caller(s) : Applications +* Note(s) : none +********************************************************************************************************* +*/ +void RegisterSimulateInterrupt(rt_uint32_t IntIndex,rt_uint32_t (*IntHandler)(void)) +{ + if(IntIndex < MAX_INTERRUPT_NUM) + { + if (hInterruptEventMutex != NULL) + { + WaitForSingleObject(hInterruptEventMutex, + INFINITE); + + CpuIsrHandler[IntIndex] = IntHandler; + + ReleaseMutex(hInterruptEventMutex); + } + else + { + CpuIsrHandler[IntIndex] = IntHandler; + } + } + +} /*** RegisterSimulateInterrupt ***/ + + + +/* +********************************************************************************************************* +* PRIVATE FUNCTION +********************************************************************************************************* +*/ + +/* +********************************************************************************************************* +* WinThreadScheduler() +* Description : Handle all simulate interrupts +* Argument(s) : void +* Return(s) : static void +* Caller(s) : os scachle +* Note(s) : none +********************************************************************************************************* +*/ +#define WIN_WM_MIN_RES (1) + void WinThreadScheduler(void) +{ + HANDLE hInterruptObjectList[2]; + HANDLE hThreadHandle; + rt_uint32_t SwitchRequiredMask; + rt_uint32_t i; + + win_thread_t *WinThreadFrom; + win_thread_t *WinThreadTo; + + /* + * Install the interrupt handlers used bye scheduler itself + */ + RegisterSimulateInterrupt(CPU_INTERRUPT_YIELD, + YieldInterruptHandle); + RegisterSimulateInterrupt(CPU_INTERRUPT_TICK, + SysTickInterruptHandle); + + /* + * Create the events and mutex that are used to synchronise all the WinThreads + */ + hInterruptEventMutex = CreateMutex(NULL, + FALSE, + NULL); + hInterruptEventHandle = CreateEvent(NULL, + FALSE, + FALSE, + NULL); + + if((hInterruptEventMutex == NULL) || (hInterruptEventHandle == NULL)) + { + return; + } + + /* + * Set the priority of this WinThread such that it is above the priority of the WinThreads + * that run rt-threads. + * This is higher priority is required to ensure simulate interrupts take priority over rt-threads + */ + hThreadHandle = GetCurrentThread(); + if(hThreadHandle == NULL) + { + return; + } + + if (SetThreadPriority(hThreadHandle, + THREAD_PRIORITY_HIGHEST) == 0) + { + return; + } + SetThreadPriorityBoost(hThreadHandle, + TRUE); + SetThreadAffinityMask(hThreadHandle, + 0x01); + + /* + * Start the thread that simulates the timer peripheral to generate tick interrupts. + */ + OSTick_Thread = CreateThread(NULL, + 0, + ThreadforSysTickTimer, + 0, + CREATE_SUSPENDED, + &OSTick_ThreadID); + if(OSTick_Thread == NULL) + { + //Display Error Message + + + return; + } + SetThreadPriority(OSTick_Thread, + THREAD_PRIORITY_NORMAL); + SetThreadPriorityBoost(OSTick_Thread, + TRUE); + SetThreadAffinityMask(OSTick_Thread, + 0x01); + + /* + * Set timer Caps + */ + if (timeGetDevCaps(&OSTick_TimerCap, + sizeof(OSTick_TimerCap)) != TIMERR_NOERROR) + { + + CloseHandle(OSTick_Thread); + + return; + } + if (OSTick_TimerCap.wPeriodMin < WIN_WM_MIN_RES) + { + OSTick_TimerCap.wPeriodMin = WIN_WM_MIN_RES; + } + + if(timeBeginPeriod(OSTick_TimerCap.wPeriodMin) != TIMERR_NOERROR) + { + CloseHandle(OSTick_Thread); + + return; + } + + OSTick_SignalPtr = CreateEvent(NULL,TRUE,FALSE,NULL); + if(OSTick_SignalPtr == NULL) + { + // disp error message + + timeEndPeriod(OSTick_TimerCap.wPeriodMin); + CloseHandle(OSTick_Thread); + + return; + } + + OSTick_TimerID = timeSetEvent((UINT ) (1000 / RT_TICK_PER_SECOND) , + (UINT ) OSTick_TimerCap.wPeriodMin, + (LPTIMECALLBACK ) OSTick_SignalPtr, + (DWORD_PTR ) NULL, + (UINT ) (TIME_PERIODIC | TIME_CALLBACK_EVENT_SET)); + + if(OSTick_TimerID == 0) + { + //disp + + CloseHandle(OSTick_SignalPtr); + timeEndPeriod(OSTick_TimerCap.wPeriodMin); + CloseHandle(OSTick_Thread); + + return; + } + + /* + * Start OS Tick Thread an release Interrupt Mutex + */ + ResumeThread(OSTick_Thread); + ReleaseMutex( hInterruptEventMutex ); + + //trigger YEILD INTERRUPT + TriggerSimulateInterrupt(CPU_INTERRUPT_YIELD); + + /* + * block on the mutex that ensure exclusive access to the simulated interrupt objects + * and the events that signals that a simulated interrupt should be processed. + */ + + hInterruptObjectList[0] = hInterruptEventHandle; + hInterruptObjectList[1] = hInterruptEventMutex; + + + while (1) + { + WaitForMultipleObjects(sizeof(hInterruptObjectList) / sizeof(HANDLE), + hInterruptObjectList, + TRUE, + INFINITE); + + /* + * Used to indicate whether the simulate interrupt processing has necessitated a contex + * switch to another thread + */ + SwitchRequiredMask = 0; + + /* + * For each interrupt we are interested in processing ,each of which is represented + * by a bit in the 32bit CpuPendingInterrupts variable. + */ + for (i = 0; i < MAX_INTERRUPT_NUM; ++i) + { + /* is the simulated interrupt pending ? */ + if (CpuPendingInterrupts & (1UL << i)) + { + /* Is a handler installed ?*/ + if (CpuIsrHandler[i] != NULL) + { + /* Run the actual handler */ + if (CpuIsrHandler[i]() != 0) + { + SwitchRequiredMask |= (1UL << i); + } + } + + /* Clear the interrupt pending bit */ + CpuPendingInterrupts &= ~(1UL << i); + } + } + + if(SwitchRequiredMask != 0) + { + WinThreadFrom = (win_thread_t *)rt_interrupt_from_thread; + WinThreadTo = (win_thread_t *)rt_interrupt_to_thread; + + if ((WinThreadFrom != NULL) && (WinThreadFrom->ThreadHandle != NULL)) + { + SuspendThread(WinThreadFrom->ThreadHandle); + } + + ResumeThread(WinThreadTo->ThreadHandle); + + } + + ReleaseMutex(hInterruptEventMutex); + } +} /*** WinThreadScheduler ***/ + + + +/* +********************************************************************************************************* +* ThreadforSysTickTimer() +* Description : win thread to simulate a systick timer +* Argument(s) : LPVOID lpParam +* Return(s) : static DWORD WINAPI +* Caller(s) : none +* Note(s) : This is not a real time way of generating tick events as the next wake time should be relative +* to the previous wake time,not the time Sleep() is called. +* It is done this way to prevent overruns in this very non real time simulated/emulated environment +********************************************************************************************************* +*/ +static DWORD WINAPI ThreadforSysTickTimer(LPVOID lpParam) +{ + + (void)lpParam; //prevent compiler warnings + + for(;;) + { + /* + * Wait until the timer expires and we can access the simulated interrupt variables. + */ + WaitForSingleObject(OSTick_SignalPtr,INFINITE); + + ResetEvent(OSTick_SignalPtr); + + /* + * Trigger a systick interrupt + */ + TriggerSimulateInterrupt(CPU_INTERRUPT_TICK); + + } + + return 0; + +} /*** prvThreadforSysTickTimer ***/ + +/* +********************************************************************************************************* +* SysTickInterruptHandle() +* Description : Interrupt handle for systick +* Argument(s) : void +* Return(s) : rt_uint32_t +* Caller(s) : none +* Note(s) : none +********************************************************************************************************* +*/ +rt_uint32_t SysTickInterruptHandle(void) +{ + + /* enter interrupt */ + rt_interrupt_enter(); + + rt_tick_increase(); + + /* leave interrupt */ + rt_interrupt_leave(); + + return 0; +} /*** SysTickInterruptHandle ***/ + +/* +********************************************************************************************************* +* YieldInterruptHandle() +* Description : Interrupt handle for Yield +* Argument(s) : void +* Return(s) : rt_uint32_t +* Caller(s) : none +* Note(s) : none +********************************************************************************************************* +*/ +rt_uint32_t YieldInterruptHandle(void) +{ + + /* + * if rt_thread_switch_interrupt_flag = 1 yield already handled + */ + if(rt_thread_switch_interrupt_flag != 0) + { + rt_thread_switch_interrupt_flag = 0; + + /* return thread switch request = 1 */ + return 1; + } + + return 0; +} /*** YieldInterruptHandle ***/ diff --git a/libcpu/sim/win32/cpu_port.h b/libcpu/sim/win32/cpu_port.h index 9d43d61c6d..8ab8ae23bd 100644 --- a/libcpu/sim/win32/cpu_port.h +++ b/libcpu/sim/win32/cpu_port.h @@ -1,33 +1,33 @@ -/*
-************************************************************************************************************************
-* File : cpu_port.h
-* By : xyou
-* Version : V1.00.00
-************************************************************************************************************************
-*/
-
-
-
-#ifndef _CPU_PORT_H_
-#define _CPU_PORT_H_
-
-
-/*
-*********************************************************************************************************
-* CPU INTERRUPT PRIORITY
-*********************************************************************************************************
-*/
-#define CPU_INTERRUPT_YIELD 0x00
-#define CPU_INTERRUPT_TICK 0x01
-
-
-
-/*
-*********************************************************************************************************
-* FUNCTION PROTOTYPES
-*********************************************************************************************************
-*/
-void TriggerSimulateInterrupt(rt_uint32_t IntIndex);
-
-void WinThreadScheduler(void);
-#endif /* _CPU_PORT_H_ */
+/* +************************************************************************************************************************ +* File : cpu_port.h +* By : xyou +* Version : V1.00.00 +************************************************************************************************************************ +*/ + + + +#ifndef _CPU_PORT_H_ +#define _CPU_PORT_H_ + + +/* +********************************************************************************************************* +* CPU INTERRUPT PRIORITY +********************************************************************************************************* +*/ +#define CPU_INTERRUPT_YIELD 0x00 +#define CPU_INTERRUPT_TICK 0x01 + + + +/* +********************************************************************************************************* +* FUNCTION PROTOTYPES +********************************************************************************************************* +*/ +void TriggerSimulateInterrupt(rt_uint32_t IntIndex); + +void WinThreadScheduler(void); +#endif /* _CPU_PORT_H_ */ diff --git a/libcpu/v850/70f34/context_iar.S b/libcpu/v850/70f34/context_iar.S index a384c2f065..5a8c1da41a 100644 --- a/libcpu/v850/70f34/context_iar.S +++ b/libcpu/v850/70f34/context_iar.S @@ -1,174 +1,174 @@ -#include "macdefs.inc"
-
- name OS_Core
-
- COMMON INTVEC:CODE
-
-;********************************************************************
-;
-; function:
-; description: Trap 0x10 vector used for context switch
-; Right now, all TRAPs to $1x are trated the same way
-;
- org 50h
- jr OSCtxSW
-
-
-;********************************************************************
-;
-; function:
-; description: Timer 40 compare match interrupt used for system
-; tick interrupt
-;
- org 0x220
- jr OSTickIntr
-
- org 0x0520
- jr uarta1_int_r
-
- RSEG CODE(1)
-
- EXTERN rt_thread_switch_interrupt_flag
- EXTERN rt_interrupt_from_thread
- EXTERN rt_interrupt_to_thread
-
- EXTERN rt_interrupt_enter
- EXTERN rt_interrupt_leave
- EXTERN rt_tick_increase
- EXTERN uarta1_receive_handler
-
- PUBLIC rt_hw_interrupt_disable
- PUBLIC rt_hw_interrupt_enable
- PUBLIC rt_hw_context_switch_to
- PUBLIC OSCtxSW
- PUBLIC OS_Restore_CPU_Context
-
-rt_hw_interrupt_disable:
- stsr psw, r1
- di
- jmp [lp]
-
-rt_hw_interrupt_enable:
- ldsr r1, psw
- jmp [lp]
-
-OS_Restore_CPU_Context:
- mov sp, ep
- sld.w 4[ep], r2
- sld.w 8[ep], r5
- sld.w 12[ep],r6
- sld.w 16[ep],r7
- sld.w 20[ep],r8
- sld.w 24[ep],r9
- sld.w 28[ep],r10
- sld.w 32[ep],r11
- sld.w 36[ep],r12
- sld.w 40[ep],r13
- sld.w 44[ep],r14
- sld.w 48[ep],r15
- sld.w 52[ep],r16
-
- ;See what was the latest interruption (trap or interrupt)
- stsr ecr, r17 ;Move ecr to r17
- mov 0x050,r1
- cmp r1, r17 ;If latest break was due to TRAP, set EP
- be _SetEP
-
-_ClrEP:
- mov 0x20, r17 ;Set only ID
- ldsr r17, psw
-
- ;Restore caller address
- sld.w 56[ep], r1
- ldsr r1, EIPC
- ;Restore PSW
- sld.w 60[ep], r1
- andi 0xffdf,r1,r1
- ldsr r1, EIPSW
- sld.w 0[ep], r1
- dispose (8+(4*14)),{r23,r24,r25,r26,r27,r28,r29,r30,r31}
-
- ;Return from interrupt starts new task!
- reti
-
-_SetEP:
- mov 0x60, r17 ;Set both EIPC and ID bits
- ldsr r17, psw
-
- ;Restore caller address
- sld.w 56[ep], r1
- ldsr r1, EIPC
- ;Restore PSW
- sld.w 60[ep], r1
- andi 0xffdf,r1,r1
- ldsr r1, EIPSW
- sld.w 0[ep], r1
- dispose (8+(4*14)),{r23,r24,r25,r26,r27,r28,r29,r30,r31}
-
- ;Return from interrupt starts new task!
- reti
-
-//rseg CODE:CODE
-//public rt_hw_context_switch_to
-rt_hw_context_switch_to:
- ;Load stack pointer of the task to run
- ld.w 0[r1], sp ;load sp from struct
-
- ;Restore all Processor registers from stack and return from interrupt
- jr OS_Restore_CPU_Context
-
-OSCtxSW:
- SAVE_CPU_CTX ;Save all CPU registers
-
- mov rt_interrupt_from_thread, r21
- ld.w 0[r21], r21
- st.w sp, 0[r21]
-
- mov rt_interrupt_to_thread, r1
- ld.w 0[r1], r1
- ld.w 0[r1], sp
-
- ;Restore all Processor registers from stack and return from interrupt
- jr OS_Restore_CPU_Context
-
-rt_hw_context_switch_interrupt_do:
- mov rt_thread_switch_interrupt_flag, r8
- mov 0, r9
- st.b r9, 0[r8]
-
- mov rt_interrupt_from_thread, r21
- ld.w 0[r21], r21
- st.w sp, 0[r21]
-
- mov rt_interrupt_to_thread, r1
- ld.w 0[r1], r1
- ld.w 0[r1], sp
- jr OS_Restore_CPU_Context
-
-OSTickIntr:
- SAVE_CPU_CTX ;Save current task's registers
- jarl rt_interrupt_enter,lp
- jarl rt_tick_increase,lp
- jarl rt_interrupt_leave,lp
-
- mov rt_thread_switch_interrupt_flag, r8
- ld.w 0[r8],r9
- cmp 1, r9
- be rt_hw_context_switch_interrupt_do
-
- jr OS_Restore_CPU_Context
-
-uarta1_int_r:
- SAVE_CPU_CTX ;Save current task's registers
- jarl rt_interrupt_enter,lp
- jarl uarta1_receive_handler,lp
- jarl rt_interrupt_leave,lp
-
- mov rt_thread_switch_interrupt_flag, r8
- ld.w 0[r8],r9
- cmp 1, r9
- be rt_hw_context_switch_interrupt_do
-
- jr OS_Restore_CPU_Context
-
- END
+#include "macdefs.inc" + + name OS_Core + + COMMON INTVEC:CODE + +;******************************************************************** +; +; function: +; description: Trap 0x10 vector used for context switch +; Right now, all TRAPs to $1x are trated the same way +; + org 50h + jr OSCtxSW + + +;******************************************************************** +; +; function: +; description: Timer 40 compare match interrupt used for system +; tick interrupt +; + org 0x220 + jr OSTickIntr + + org 0x0520 + jr uarta1_int_r + + RSEG CODE(1) + + EXTERN rt_thread_switch_interrupt_flag + EXTERN rt_interrupt_from_thread + EXTERN rt_interrupt_to_thread + + EXTERN rt_interrupt_enter + EXTERN rt_interrupt_leave + EXTERN rt_tick_increase + EXTERN uarta1_receive_handler + + PUBLIC rt_hw_interrupt_disable + PUBLIC rt_hw_interrupt_enable + PUBLIC rt_hw_context_switch_to + PUBLIC OSCtxSW + PUBLIC OS_Restore_CPU_Context + +rt_hw_interrupt_disable: + stsr psw, r1 + di + jmp [lp] + +rt_hw_interrupt_enable: + ldsr r1, psw + jmp [lp] + +OS_Restore_CPU_Context: + mov sp, ep + sld.w 4[ep], r2 + sld.w 8[ep], r5 + sld.w 12[ep],r6 + sld.w 16[ep],r7 + sld.w 20[ep],r8 + sld.w 24[ep],r9 + sld.w 28[ep],r10 + sld.w 32[ep],r11 + sld.w 36[ep],r12 + sld.w 40[ep],r13 + sld.w 44[ep],r14 + sld.w 48[ep],r15 + sld.w 52[ep],r16 + + ;See what was the latest interruption (trap or interrupt) + stsr ecr, r17 ;Move ecr to r17 + mov 0x050,r1 + cmp r1, r17 ;If latest break was due to TRAP, set EP + be _SetEP + +_ClrEP: + mov 0x20, r17 ;Set only ID + ldsr r17, psw + + ;Restore caller address + sld.w 56[ep], r1 + ldsr r1, EIPC + ;Restore PSW + sld.w 60[ep], r1 + andi 0xffdf,r1,r1 + ldsr r1, EIPSW + sld.w 0[ep], r1 + dispose (8+(4*14)),{r23,r24,r25,r26,r27,r28,r29,r30,r31} + + ;Return from interrupt starts new task! + reti + +_SetEP: + mov 0x60, r17 ;Set both EIPC and ID bits + ldsr r17, psw + + ;Restore caller address + sld.w 56[ep], r1 + ldsr r1, EIPC + ;Restore PSW + sld.w 60[ep], r1 + andi 0xffdf,r1,r1 + ldsr r1, EIPSW + sld.w 0[ep], r1 + dispose (8+(4*14)),{r23,r24,r25,r26,r27,r28,r29,r30,r31} + + ;Return from interrupt starts new task! + reti + +//rseg CODE:CODE +//public rt_hw_context_switch_to +rt_hw_context_switch_to: + ;Load stack pointer of the task to run + ld.w 0[r1], sp ;load sp from struct + + ;Restore all Processor registers from stack and return from interrupt + jr OS_Restore_CPU_Context + +OSCtxSW: + SAVE_CPU_CTX ;Save all CPU registers + + mov rt_interrupt_from_thread, r21 + ld.w 0[r21], r21 + st.w sp, 0[r21] + + mov rt_interrupt_to_thread, r1 + ld.w 0[r1], r1 + ld.w 0[r1], sp + + ;Restore all Processor registers from stack and return from interrupt + jr OS_Restore_CPU_Context + +rt_hw_context_switch_interrupt_do: + mov rt_thread_switch_interrupt_flag, r8 + mov 0, r9 + st.b r9, 0[r8] + + mov rt_interrupt_from_thread, r21 + ld.w 0[r21], r21 + st.w sp, 0[r21] + + mov rt_interrupt_to_thread, r1 + ld.w 0[r1], r1 + ld.w 0[r1], sp + jr OS_Restore_CPU_Context + +OSTickIntr: + SAVE_CPU_CTX ;Save current task's registers + jarl rt_interrupt_enter,lp + jarl rt_tick_increase,lp + jarl rt_interrupt_leave,lp + + mov rt_thread_switch_interrupt_flag, r8 + ld.w 0[r8],r9 + cmp 1, r9 + be rt_hw_context_switch_interrupt_do + + jr OS_Restore_CPU_Context + +uarta1_int_r: + SAVE_CPU_CTX ;Save current task's registers + jarl rt_interrupt_enter,lp + jarl uarta1_receive_handler,lp + jarl rt_interrupt_leave,lp + + mov rt_thread_switch_interrupt_flag, r8 + ld.w 0[r8],r9 + cmp 1, r9 + be rt_hw_context_switch_interrupt_do + + jr OS_Restore_CPU_Context + + END diff --git a/libcpu/v850/70f34/context_iar.asm b/libcpu/v850/70f34/context_iar.asm index a384c2f065..5a8c1da41a 100644 --- a/libcpu/v850/70f34/context_iar.asm +++ b/libcpu/v850/70f34/context_iar.asm @@ -1,174 +1,174 @@ -#include "macdefs.inc"
-
- name OS_Core
-
- COMMON INTVEC:CODE
-
-;********************************************************************
-;
-; function:
-; description: Trap 0x10 vector used for context switch
-; Right now, all TRAPs to $1x are trated the same way
-;
- org 50h
- jr OSCtxSW
-
-
-;********************************************************************
-;
-; function:
-; description: Timer 40 compare match interrupt used for system
-; tick interrupt
-;
- org 0x220
- jr OSTickIntr
-
- org 0x0520
- jr uarta1_int_r
-
- RSEG CODE(1)
-
- EXTERN rt_thread_switch_interrupt_flag
- EXTERN rt_interrupt_from_thread
- EXTERN rt_interrupt_to_thread
-
- EXTERN rt_interrupt_enter
- EXTERN rt_interrupt_leave
- EXTERN rt_tick_increase
- EXTERN uarta1_receive_handler
-
- PUBLIC rt_hw_interrupt_disable
- PUBLIC rt_hw_interrupt_enable
- PUBLIC rt_hw_context_switch_to
- PUBLIC OSCtxSW
- PUBLIC OS_Restore_CPU_Context
-
-rt_hw_interrupt_disable:
- stsr psw, r1
- di
- jmp [lp]
-
-rt_hw_interrupt_enable:
- ldsr r1, psw
- jmp [lp]
-
-OS_Restore_CPU_Context:
- mov sp, ep
- sld.w 4[ep], r2
- sld.w 8[ep], r5
- sld.w 12[ep],r6
- sld.w 16[ep],r7
- sld.w 20[ep],r8
- sld.w 24[ep],r9
- sld.w 28[ep],r10
- sld.w 32[ep],r11
- sld.w 36[ep],r12
- sld.w 40[ep],r13
- sld.w 44[ep],r14
- sld.w 48[ep],r15
- sld.w 52[ep],r16
-
- ;See what was the latest interruption (trap or interrupt)
- stsr ecr, r17 ;Move ecr to r17
- mov 0x050,r1
- cmp r1, r17 ;If latest break was due to TRAP, set EP
- be _SetEP
-
-_ClrEP:
- mov 0x20, r17 ;Set only ID
- ldsr r17, psw
-
- ;Restore caller address
- sld.w 56[ep], r1
- ldsr r1, EIPC
- ;Restore PSW
- sld.w 60[ep], r1
- andi 0xffdf,r1,r1
- ldsr r1, EIPSW
- sld.w 0[ep], r1
- dispose (8+(4*14)),{r23,r24,r25,r26,r27,r28,r29,r30,r31}
-
- ;Return from interrupt starts new task!
- reti
-
-_SetEP:
- mov 0x60, r17 ;Set both EIPC and ID bits
- ldsr r17, psw
-
- ;Restore caller address
- sld.w 56[ep], r1
- ldsr r1, EIPC
- ;Restore PSW
- sld.w 60[ep], r1
- andi 0xffdf,r1,r1
- ldsr r1, EIPSW
- sld.w 0[ep], r1
- dispose (8+(4*14)),{r23,r24,r25,r26,r27,r28,r29,r30,r31}
-
- ;Return from interrupt starts new task!
- reti
-
-//rseg CODE:CODE
-//public rt_hw_context_switch_to
-rt_hw_context_switch_to:
- ;Load stack pointer of the task to run
- ld.w 0[r1], sp ;load sp from struct
-
- ;Restore all Processor registers from stack and return from interrupt
- jr OS_Restore_CPU_Context
-
-OSCtxSW:
- SAVE_CPU_CTX ;Save all CPU registers
-
- mov rt_interrupt_from_thread, r21
- ld.w 0[r21], r21
- st.w sp, 0[r21]
-
- mov rt_interrupt_to_thread, r1
- ld.w 0[r1], r1
- ld.w 0[r1], sp
-
- ;Restore all Processor registers from stack and return from interrupt
- jr OS_Restore_CPU_Context
-
-rt_hw_context_switch_interrupt_do:
- mov rt_thread_switch_interrupt_flag, r8
- mov 0, r9
- st.b r9, 0[r8]
-
- mov rt_interrupt_from_thread, r21
- ld.w 0[r21], r21
- st.w sp, 0[r21]
-
- mov rt_interrupt_to_thread, r1
- ld.w 0[r1], r1
- ld.w 0[r1], sp
- jr OS_Restore_CPU_Context
-
-OSTickIntr:
- SAVE_CPU_CTX ;Save current task's registers
- jarl rt_interrupt_enter,lp
- jarl rt_tick_increase,lp
- jarl rt_interrupt_leave,lp
-
- mov rt_thread_switch_interrupt_flag, r8
- ld.w 0[r8],r9
- cmp 1, r9
- be rt_hw_context_switch_interrupt_do
-
- jr OS_Restore_CPU_Context
-
-uarta1_int_r:
- SAVE_CPU_CTX ;Save current task's registers
- jarl rt_interrupt_enter,lp
- jarl uarta1_receive_handler,lp
- jarl rt_interrupt_leave,lp
-
- mov rt_thread_switch_interrupt_flag, r8
- ld.w 0[r8],r9
- cmp 1, r9
- be rt_hw_context_switch_interrupt_do
-
- jr OS_Restore_CPU_Context
-
- END
+#include "macdefs.inc" + + name OS_Core + + COMMON INTVEC:CODE + +;******************************************************************** +; +; function: +; description: Trap 0x10 vector used for context switch +; Right now, all TRAPs to $1x are trated the same way +; + org 50h + jr OSCtxSW + + +;******************************************************************** +; +; function: +; description: Timer 40 compare match interrupt used for system +; tick interrupt +; + org 0x220 + jr OSTickIntr + + org 0x0520 + jr uarta1_int_r + + RSEG CODE(1) + + EXTERN rt_thread_switch_interrupt_flag + EXTERN rt_interrupt_from_thread + EXTERN rt_interrupt_to_thread + + EXTERN rt_interrupt_enter + EXTERN rt_interrupt_leave + EXTERN rt_tick_increase + EXTERN uarta1_receive_handler + + PUBLIC rt_hw_interrupt_disable + PUBLIC rt_hw_interrupt_enable + PUBLIC rt_hw_context_switch_to + PUBLIC OSCtxSW + PUBLIC OS_Restore_CPU_Context + +rt_hw_interrupt_disable: + stsr psw, r1 + di + jmp [lp] + +rt_hw_interrupt_enable: + ldsr r1, psw + jmp [lp] + +OS_Restore_CPU_Context: + mov sp, ep + sld.w 4[ep], r2 + sld.w 8[ep], r5 + sld.w 12[ep],r6 + sld.w 16[ep],r7 + sld.w 20[ep],r8 + sld.w 24[ep],r9 + sld.w 28[ep],r10 + sld.w 32[ep],r11 + sld.w 36[ep],r12 + sld.w 40[ep],r13 + sld.w 44[ep],r14 + sld.w 48[ep],r15 + sld.w 52[ep],r16 + + ;See what was the latest interruption (trap or interrupt) + stsr ecr, r17 ;Move ecr to r17 + mov 0x050,r1 + cmp r1, r17 ;If latest break was due to TRAP, set EP + be _SetEP + +_ClrEP: + mov 0x20, r17 ;Set only ID + ldsr r17, psw + + ;Restore caller address + sld.w 56[ep], r1 + ldsr r1, EIPC + ;Restore PSW + sld.w 60[ep], r1 + andi 0xffdf,r1,r1 + ldsr r1, EIPSW + sld.w 0[ep], r1 + dispose (8+(4*14)),{r23,r24,r25,r26,r27,r28,r29,r30,r31} + + ;Return from interrupt starts new task! + reti + +_SetEP: + mov 0x60, r17 ;Set both EIPC and ID bits + ldsr r17, psw + + ;Restore caller address + sld.w 56[ep], r1 + ldsr r1, EIPC + ;Restore PSW + sld.w 60[ep], r1 + andi 0xffdf,r1,r1 + ldsr r1, EIPSW + sld.w 0[ep], r1 + dispose (8+(4*14)),{r23,r24,r25,r26,r27,r28,r29,r30,r31} + + ;Return from interrupt starts new task! + reti + +//rseg CODE:CODE +//public rt_hw_context_switch_to +rt_hw_context_switch_to: + ;Load stack pointer of the task to run + ld.w 0[r1], sp ;load sp from struct + + ;Restore all Processor registers from stack and return from interrupt + jr OS_Restore_CPU_Context + +OSCtxSW: + SAVE_CPU_CTX ;Save all CPU registers + + mov rt_interrupt_from_thread, r21 + ld.w 0[r21], r21 + st.w sp, 0[r21] + + mov rt_interrupt_to_thread, r1 + ld.w 0[r1], r1 + ld.w 0[r1], sp + + ;Restore all Processor registers from stack and return from interrupt + jr OS_Restore_CPU_Context + +rt_hw_context_switch_interrupt_do: + mov rt_thread_switch_interrupt_flag, r8 + mov 0, r9 + st.b r9, 0[r8] + + mov rt_interrupt_from_thread, r21 + ld.w 0[r21], r21 + st.w sp, 0[r21] + + mov rt_interrupt_to_thread, r1 + ld.w 0[r1], r1 + ld.w 0[r1], sp + jr OS_Restore_CPU_Context + +OSTickIntr: + SAVE_CPU_CTX ;Save current task's registers + jarl rt_interrupt_enter,lp + jarl rt_tick_increase,lp + jarl rt_interrupt_leave,lp + + mov rt_thread_switch_interrupt_flag, r8 + ld.w 0[r8],r9 + cmp 1, r9 + be rt_hw_context_switch_interrupt_do + + jr OS_Restore_CPU_Context + +uarta1_int_r: + SAVE_CPU_CTX ;Save current task's registers + jarl rt_interrupt_enter,lp + jarl uarta1_receive_handler,lp + jarl rt_interrupt_leave,lp + + mov rt_thread_switch_interrupt_flag, r8 + ld.w 0[r8],r9 + cmp 1, r9 + be rt_hw_context_switch_interrupt_do + + jr OS_Restore_CPU_Context + + END diff --git a/libcpu/v850/70f34/cpuport.c b/libcpu/v850/70f34/cpuport.c index 806fe6426b..f3c7624ee5 100644 --- a/libcpu/v850/70f34/cpuport.c +++ b/libcpu/v850/70f34/cpuport.c @@ -1,100 +1,100 @@ -/*
- * File : cpuport.c
- * This file is part of RT-Thread RTOS
- * COPYRIGHT (C) 2009 - 2012, RT-Thread Development Team
- *
- * The license and distribution terms for this file may be
- * found in the file LICENSE in this distribution or at
- * http://www.rt-thread.org/license/LICENSE
- *
- * Change Logs:
- * Date Author Notes
- * 2011-02-23 Bernard the first version
- * 2012-09-23 lgnq set the texit to R31
- */
-
-#include <rtthread.h>
-
-extern volatile rt_uint8_t rt_interrupt_nest;
-
-/* switch flag on interrupt and thread pointer to save switch record */
-rt_uint32_t rt_interrupt_from_thread;
-rt_uint32_t rt_interrupt_to_thread;
-rt_uint32_t rt_thread_switch_interrupt_flag;
-
-/**
- * This function will initialize hardware interrupt
- */
-void rt_hw_interrupt_init(void)
-{
- /* init interrupt nest, and context in thread sp */
- rt_interrupt_nest = 0;
- rt_interrupt_from_thread = 0;
- rt_interrupt_to_thread = 0;
- rt_thread_switch_interrupt_flag = 0;
-}
-
-/**
- * This function will initialize thread stack
- *
- * @param tentry the entry of thread
- * @param parameter the parameter of entry
- * @param stack_addr the beginning stack address
- * @param texit the function will be called when thread exit
- *
- * @return stack address
- */
-rt_uint8_t *rt_hw_stack_init(void *tentry,
- void *parameter,
- rt_uint8_t *stack_addr,
- void *texit)
-{
- rt_uint32_t *stk;
-
- stk = (rt_uint32_t *)stack_addr; /* Load stack pointer */
-
- *(--stk) = (rt_uint32_t)0x23232323; /* r23 */
- *(--stk) = (rt_uint32_t)0x24242424; /* r24 */
- *(--stk) = (rt_uint32_t)0x25252525; /* r25 */
- *(--stk) = (rt_uint32_t)0x26262626; /* r26 */
- *(--stk) = (rt_uint32_t)0x27272727; /* r27 */
- *(--stk) = (rt_uint32_t)0x28282828; /* r28 */
- *(--stk) = (rt_uint32_t)0x29292929; /* r29 */
- *(--stk) = (rt_uint32_t)0x30303030; /* r30 */
- *(--stk) = (rt_uint32_t)texit; /* r31 */
- *(--stk) = (rt_uint32_t)0x00000000; /* Task PSW = Interrupts enabled */
- *(--stk) = (rt_uint32_t)tentry; /* Task's PC */
- *(--stk) = (rt_uint32_t)0x16161616; /* r16 */
- *(--stk) = (rt_uint32_t)0x15151515; /* r15 */
- *(--stk) = (rt_uint32_t)0x14141414; /* r14 */
- *(--stk) = (rt_uint32_t)0x13131313; /* r13 */
- *(--stk) = (rt_uint32_t)0x12121212; /* r12 */
- *(--stk) = (rt_uint32_t)0x11111111; /* r11 */
- *(--stk) = (rt_uint32_t)0x10101010; /* r10 */
- *(--stk) = (rt_uint32_t)0x09090909; /* r9 */
- *(--stk) = (rt_uint32_t)0x08080808; /* r8 */
- *(--stk) = (rt_uint32_t)0x07070707; /* r7 */
- *(--stk) = (rt_uint32_t)0x06060606; /* r6 */
- *(--stk) = (rt_uint32_t)0x05050505; /* r5 */
- *(--stk) = (rt_uint32_t)0x02020202; /* r2 */
- *(--stk) = (rt_uint32_t)parameter; /* r1 */
-
- return ((rt_uint8_t *)stk);
-}
-
-void rt_hw_context_switch(rt_uint32_t from, rt_uint32_t to)
-{
- rt_interrupt_from_thread = from;
- rt_interrupt_to_thread = to;
- asm("trap 0x10");
-}
-
-void rt_hw_context_switch_interrupt(rt_uint32_t from, rt_uint32_t to)
-{
- if (rt_thread_switch_interrupt_flag != 1)
- {
- rt_thread_switch_interrupt_flag = 1;
- rt_interrupt_from_thread = from;
- }
- rt_interrupt_to_thread = to;
-}
+/* + * File : cpuport.c + * This file is part of RT-Thread RTOS + * COPYRIGHT (C) 2009 - 2012, RT-Thread Development Team + * + * The license and distribution terms for this file may be + * found in the file LICENSE in this distribution or at + * http://www.rt-thread.org/license/LICENSE + * + * Change Logs: + * Date Author Notes + * 2011-02-23 Bernard the first version + * 2012-09-23 lgnq set the texit to R31 + */ + +#include <rtthread.h> + +extern volatile rt_uint8_t rt_interrupt_nest; + +/* switch flag on interrupt and thread pointer to save switch record */ +rt_uint32_t rt_interrupt_from_thread; +rt_uint32_t rt_interrupt_to_thread; +rt_uint32_t rt_thread_switch_interrupt_flag; + +/** + * This function will initialize hardware interrupt + */ +void rt_hw_interrupt_init(void) +{ + /* init interrupt nest, and context in thread sp */ + rt_interrupt_nest = 0; + rt_interrupt_from_thread = 0; + rt_interrupt_to_thread = 0; + rt_thread_switch_interrupt_flag = 0; +} + +/** + * This function will initialize thread stack + * + * @param tentry the entry of thread + * @param parameter the parameter of entry + * @param stack_addr the beginning stack address + * @param texit the function will be called when thread exit + * + * @return stack address + */ +rt_uint8_t *rt_hw_stack_init(void *tentry, + void *parameter, + rt_uint8_t *stack_addr, + void *texit) +{ + rt_uint32_t *stk; + + stk = (rt_uint32_t *)stack_addr; /* Load stack pointer */ + + *(--stk) = (rt_uint32_t)0x23232323; /* r23 */ + *(--stk) = (rt_uint32_t)0x24242424; /* r24 */ + *(--stk) = (rt_uint32_t)0x25252525; /* r25 */ + *(--stk) = (rt_uint32_t)0x26262626; /* r26 */ + *(--stk) = (rt_uint32_t)0x27272727; /* r27 */ + *(--stk) = (rt_uint32_t)0x28282828; /* r28 */ + *(--stk) = (rt_uint32_t)0x29292929; /* r29 */ + *(--stk) = (rt_uint32_t)0x30303030; /* r30 */ + *(--stk) = (rt_uint32_t)texit; /* r31 */ + *(--stk) = (rt_uint32_t)0x00000000; /* Task PSW = Interrupts enabled */ + *(--stk) = (rt_uint32_t)tentry; /* Task's PC */ + *(--stk) = (rt_uint32_t)0x16161616; /* r16 */ + *(--stk) = (rt_uint32_t)0x15151515; /* r15 */ + *(--stk) = (rt_uint32_t)0x14141414; /* r14 */ + *(--stk) = (rt_uint32_t)0x13131313; /* r13 */ + *(--stk) = (rt_uint32_t)0x12121212; /* r12 */ + *(--stk) = (rt_uint32_t)0x11111111; /* r11 */ + *(--stk) = (rt_uint32_t)0x10101010; /* r10 */ + *(--stk) = (rt_uint32_t)0x09090909; /* r9 */ + *(--stk) = (rt_uint32_t)0x08080808; /* r8 */ + *(--stk) = (rt_uint32_t)0x07070707; /* r7 */ + *(--stk) = (rt_uint32_t)0x06060606; /* r6 */ + *(--stk) = (rt_uint32_t)0x05050505; /* r5 */ + *(--stk) = (rt_uint32_t)0x02020202; /* r2 */ + *(--stk) = (rt_uint32_t)parameter; /* r1 */ + + return ((rt_uint8_t *)stk); +} + +void rt_hw_context_switch(rt_uint32_t from, rt_uint32_t to) +{ + rt_interrupt_from_thread = from; + rt_interrupt_to_thread = to; + asm("trap 0x10"); +} + +void rt_hw_context_switch_interrupt(rt_uint32_t from, rt_uint32_t to) +{ + if (rt_thread_switch_interrupt_flag != 1) + { + rt_thread_switch_interrupt_flag = 1; + rt_interrupt_from_thread = from; + } + rt_interrupt_to_thread = to; +} diff --git a/libcpu/v850/70f34/macdefs.inc b/libcpu/v850/70f34/macdefs.inc index 4a0c4d4823..e42b20e3d6 100644 --- a/libcpu/v850/70f34/macdefs.inc +++ b/libcpu/v850/70f34/macdefs.inc @@ -1,125 +1,125 @@ -;
-; These are the macros used by the v850 port of the uCOS/II.
-;
-
-
-
-
-
-;********************************************************************
-; function:
-; description:
-; --- Modifies ----------------------------------------------
-; IO :
-; Mem:
-; CPU:
-; --- Uses --------------------------------------------------
-; IO :
-; Mem:
-; --- Input -------------------------------------------------
-; --- Output ------------------------------------------------
-; --- Notes -------------------------------------------------
-;====================================================================
-
-SAVE_CPU_CTX MACRO
- ;Save all registers on entry (r3 is the stack pointer)
- prepare {r23,r24,r25,r26,r27,r28,r29,r30,r31},(8+(4*14)) ;Add 8 bytes for 2 more registers
- mov sp, ep
- sst.w r1, 0[ep]
- sst.w r2, 4[ep]
- sst.w r5, 8[ep]
- sst.w r6, 12[ep]
- sst.w r7, 16[ep]
- sst.w r8, 20[ep]
- sst.w r9, 24[ep]
- sst.w r10, 28[ep]
- sst.w r11, 32[ep]
- sst.w r12, 36[ep]
- sst.w r13, 40[ep]
- sst.w r14, 44[ep]
- sst.w r15, 48[ep]
- sst.w r16, 52[ep]
- ;Save caller's PC
- stsr EIPC, r1
- sst.w r1, 56[ep]
- ;Save caller's PSW
- stsr EIPSW, r1
- sst.w r1, 60[ep]
-
- ENDMAC
-
-
-
-
-
-;********************************************************************
-; function:
-; description:
-; --- Modifies ----------------------------------------------
-; IO :
-; Mem:
-; CPU:
-; --- Uses --------------------------------------------------
-; IO :
-; Mem:
-; --- Input -------------------------------------------------
-; --- Output ------------------------------------------------
-; --- Notes -------------------------------------------------
-;====================================================================
-SAVE_SP MACRO
- ;Save stack pointer on OSTCBCur->OSTCBStkPtr (OSTCBStkPtr=0)
- mov OSTCBCur, r21
- ld.w 0[r21], r21
- st.w sp, 0[r21]
- ENDMAC
-
-
-
-;********************************************************************
-; function:
-; description:
-; --- Modifies ----------------------------------------------
-; IO :
-; Mem:
-; CPU:
-; --- Uses --------------------------------------------------
-; IO :
-; Mem:
-; --- Input -------------------------------------------------
-; --- Output ------------------------------------------------
-; --- Notes -------------------------------------------------
-;====================================================================
-ISR_ENTRY MACRO
- LOCAL _DontSaveSP
-
- ;Save all CPU registers according to the standard stack frame
- SAVE_CPU_CTX
-
- mov OSIntNesting, r1 ;Increment OSNesting by one
- LD.BU 0[r1],r2
- add 1, r2
- ST.B r2, 0[r1]
- cmp 1, r2 ;If OSNesting==1 save SP in current TCB
- bne _DontSaveSP
- SAVE_SP
-_DontSaveSP:
- ENDMAC
-
-;********************************************************************
-; function:
-; description:
-; --- Modifies ----------------------------------------------
-; IO :
-; Mem:
-; CPU:
-; --- Uses --------------------------------------------------
-; IO :
-; Mem:
-; --- Input -------------------------------------------------
-; --- Output ------------------------------------------------
-; --- Notes -------------------------------------------------
-;====================================================================
-ISR_EXIT MACRO
- jarl OSIntExit, lp ;Call OSIntExit()
- jr OS_Restore_CPU_Context ;Restore processors registers and execute RETI
- ENDMAC
+; +; These are the macros used by the v850 port of the uCOS/II. +; + + + + + +;******************************************************************** +; function: +; description: +; --- Modifies ---------------------------------------------- +; IO : +; Mem: +; CPU: +; --- Uses -------------------------------------------------- +; IO : +; Mem: +; --- Input ------------------------------------------------- +; --- Output ------------------------------------------------ +; --- Notes ------------------------------------------------- +;==================================================================== + +SAVE_CPU_CTX MACRO + ;Save all registers on entry (r3 is the stack pointer) + prepare {r23,r24,r25,r26,r27,r28,r29,r30,r31},(8+(4*14)) ;Add 8 bytes for 2 more registers + mov sp, ep + sst.w r1, 0[ep] + sst.w r2, 4[ep] + sst.w r5, 8[ep] + sst.w r6, 12[ep] + sst.w r7, 16[ep] + sst.w r8, 20[ep] + sst.w r9, 24[ep] + sst.w r10, 28[ep] + sst.w r11, 32[ep] + sst.w r12, 36[ep] + sst.w r13, 40[ep] + sst.w r14, 44[ep] + sst.w r15, 48[ep] + sst.w r16, 52[ep] + ;Save caller's PC + stsr EIPC, r1 + sst.w r1, 56[ep] + ;Save caller's PSW + stsr EIPSW, r1 + sst.w r1, 60[ep] + + ENDMAC + + + + + +;******************************************************************** +; function: +; description: +; --- Modifies ---------------------------------------------- +; IO : +; Mem: +; CPU: +; --- Uses -------------------------------------------------- +; IO : +; Mem: +; --- Input ------------------------------------------------- +; --- Output ------------------------------------------------ +; --- Notes ------------------------------------------------- +;==================================================================== +SAVE_SP MACRO + ;Save stack pointer on OSTCBCur->OSTCBStkPtr (OSTCBStkPtr=0) + mov OSTCBCur, r21 + ld.w 0[r21], r21 + st.w sp, 0[r21] + ENDMAC + + + +;******************************************************************** +; function: +; description: +; --- Modifies ---------------------------------------------- +; IO : +; Mem: +; CPU: +; --- Uses -------------------------------------------------- +; IO : +; Mem: +; --- Input ------------------------------------------------- +; --- Output ------------------------------------------------ +; --- Notes ------------------------------------------------- +;==================================================================== +ISR_ENTRY MACRO + LOCAL _DontSaveSP + + ;Save all CPU registers according to the standard stack frame + SAVE_CPU_CTX + + mov OSIntNesting, r1 ;Increment OSNesting by one + LD.BU 0[r1],r2 + add 1, r2 + ST.B r2, 0[r1] + cmp 1, r2 ;If OSNesting==1 save SP in current TCB + bne _DontSaveSP + SAVE_SP +_DontSaveSP: + ENDMAC + +;******************************************************************** +; function: +; description: +; --- Modifies ---------------------------------------------- +; IO : +; Mem: +; CPU: +; --- Uses -------------------------------------------------- +; IO : +; Mem: +; --- Input ------------------------------------------------- +; --- Output ------------------------------------------------ +; --- Notes ------------------------------------------------- +;==================================================================== +ISR_EXIT MACRO + jarl OSIntExit, lp ;Call OSIntExit() + jr OS_Restore_CPU_Context ;Restore processors registers and execute RETI + ENDMAC diff --git a/libcpu/xilinx/microblaze/serial.h b/libcpu/xilinx/microblaze/serial.h index 090efa84e5..976138bbf8 100755 --- a/libcpu/xilinx/microblaze/serial.h +++ b/libcpu/xilinx/microblaze/serial.h @@ -1,6 +1,6 @@ -#ifndef __RT_SERIAL_H__
-#define __RT_SERIAL_H__
-#include "xuartlite_l.h"
-#include "xparameters.h"
-
-#endif
+#ifndef __RT_SERIAL_H__ +#define __RT_SERIAL_H__ +#include "xuartlite_l.h" +#include "xparameters.h" + +#endif |