[bsp] add bl808 lp core (#7069)

* Add riscv_32e support

* add bl808 lp core

* update README.md

4 files changed, 38 insertions, 12 deletions

diff --git a/libcpu/risc-v/common/context_gcc.S b/libcpu/risc-v/common/context_gcc.S
index fb232cbba1..2e4651391a 100644
--- a/libcpu/risc-v/common/context_gcc.S
+++ b/libcpu/risc-v/common/context_gcc.S
@@ -9,6 +9,7 @@
  * 2018/12/27     Jesven       Add SMP support
  * 2020/11/20     BalanceTWK   Add FPU support
  * 2022/12/28     WangShun     Add macro to distinguish whether FPU is supported
+ * 2023/03/19     Flyingcys    Add riscv_32e support
  */
 
 #define __ASSEMBLY__
@@ -115,7 +116,12 @@ rt_hw_context_switch:
     FSTORE  f31, 31 * FREGBYTES(sp)
 
 #endif
+#ifndef __riscv_32e
     addi  sp,  sp, -32 * REGBYTES
+#else
+    addi  sp,  sp, -16 * REGBYTES
+#endif
+
     STORE sp,  (a0)
 
     STORE x1,   0 * REGBYTES(sp)
@@ -140,6 +146,7 @@ save_mpie:
     STORE x13, 13 * REGBYTES(sp)
     STORE x14, 14 * REGBYTES(sp)
     STORE x15, 15 * REGBYTES(sp)
+#ifndef __riscv_32e
     STORE x16, 16 * REGBYTES(sp)
     STORE x17, 17 * REGBYTES(sp)
     STORE x18, 18 * REGBYTES(sp)
@@ -156,7 +163,7 @@ save_mpie:
     STORE x29, 29 * REGBYTES(sp)
     STORE x30, 30 * REGBYTES(sp)
     STORE x31, 31 * REGBYTES(sp)
-
+#endif
     /* restore to thread context
      * sp(0) -> epc;
      * sp(1) -> ra;
@@ -237,6 +244,7 @@ rt_hw_context_switch_exit:
     LOAD x13, 13 * REGBYTES(sp)
     LOAD x14, 14 * REGBYTES(sp)
     LOAD x15, 15 * REGBYTES(sp)
+#ifndef __riscv_32e
     LOAD x16, 16 * REGBYTES(sp)
     LOAD x17, 17 * REGBYTES(sp)
     LOAD x18, 18 * REGBYTES(sp)
@@ -255,6 +263,9 @@ rt_hw_context_switch_exit:
     LOAD x31, 31 * REGBYTES(sp)
 
     addi sp,  sp, 32 * REGBYTES
+#else
+    addi sp,  sp, 16 * REGBYTES
+#endif
 
 #ifdef ARCH_RISCV_FPU
     FLOAD   f0, 0 * FREGBYTES(sp)
diff --git a/libcpu/risc-v/common/interrupt_gcc.S b/libcpu/risc-v/common/interrupt_gcc.S
index 1af6c9d1e9..a887199ca8 100644
--- a/libcpu/risc-v/common/interrupt_gcc.S
+++ b/libcpu/risc-v/common/interrupt_gcc.S
@@ -6,6 +6,7 @@
  * Change Logs:
  * Date           Author       Notes
  * 2023/01/17     WangShun    The first version
+ * 2023/03/19     Flyingcys    Add riscv_32e support
  */
 #define __ASSEMBLY__
 #include "cpuport.h"
@@ -58,7 +59,11 @@ SW_handler:
     FSTORE  f31, 31 * FREGBYTES(sp)
 #endif
     /* save all from thread context */
+#ifndef __riscv_32e
     addi sp, sp, -32 * REGBYTES
+#else
+    addi sp, sp, -16 * REGBYTES
+#endif
     STORE x5,   5 * REGBYTES(sp)
     STORE x1,   1 * REGBYTES(sp)
     /* Mandatory set the MPIE of mstatus */
@@ -75,6 +80,7 @@ SW_handler:
     STORE x13, 13 * REGBYTES(sp)
     STORE x14, 14 * REGBYTES(sp)
     STORE x15, 15 * REGBYTES(sp)
+#ifndef __riscv_32e
     STORE x16, 16 * REGBYTES(sp)
     STORE x17, 17 * REGBYTES(sp)
     STORE x18, 18 * REGBYTES(sp)
@@ -91,7 +97,7 @@ SW_handler:
     STORE x29, 29 * REGBYTES(sp)
     STORE x30, 30 * REGBYTES(sp)
     STORE x31, 31 * REGBYTES(sp)
-
+#endif
     /* switch to interrupt stack */
     csrrw sp,mscratch,sp
     /* interrupt handle */
@@ -104,22 +110,22 @@ SW_handler:
     csrrw sp,mscratch,sp
 
     /* Determine whether to trigger scheduling at the interrupt function */
-    la    s0, rt_thread_switch_interrupt_flag
-    lw    s2, 0(s0)
-    beqz  s2, 1f
+    la    t0, rt_thread_switch_interrupt_flag
+    lw    t2, 0(t0)
+    beqz  t2, 1f
     /* clear the flag of rt_thread_switch_interrupt_flag */
-    sw    zero, 0(s0)
+    sw    zero, 0(t0)
 
     csrr  a0, mepc
     STORE a0, 0 * REGBYTES(sp)
 
-    la    s0, rt_interrupt_from_thread
-    LOAD  s1, 0(s0)
-    STORE sp, 0(s1)
+    la    t0, rt_interrupt_from_thread
+    LOAD  t1, 0(t0)
+    STORE sp, 0(t1)
 
-    la    s0, rt_interrupt_to_thread
-    LOAD  s1, 0(s0)
-    LOAD  sp, 0(s1)
+    la    t0, rt_interrupt_to_thread
+    LOAD  t1, 0(t0)
+    LOAD  sp, 0(t1)
 
     LOAD  a0,  0 * REGBYTES(sp)
     csrw  mepc, a0
@@ -145,6 +151,7 @@ SW_handler:
     LOAD  x13, 13 * REGBYTES(sp)
     LOAD  x14, 14 * REGBYTES(sp)
     LOAD  x15, 15 * REGBYTES(sp)
+#ifndef __riscv_32e
     LOAD  x16, 16 * REGBYTES(sp)
     LOAD  x17, 17 * REGBYTES(sp)
     LOAD  x18, 18 * REGBYTES(sp)
@@ -163,6 +170,10 @@ SW_handler:
     LOAD  x31, 31 * REGBYTES(sp)
 
     addi  sp, sp, 32 * REGBYTES
+#else
+    addi  sp, sp, 16 * REGBYTES
+#endif
+
 #ifdef ARCH_RISCV_FPU
     FLOAD   f0, 0 * FREGBYTES(sp)
     FLOAD   f1, 1 * FREGBYTES(sp)
diff --git a/libcpu/risc-v/common/rt_hw_stack_frame.h b/libcpu/risc-v/common/rt_hw_stack_frame.h
index 6ec24cdc04..75a9c2d45a 100644
--- a/libcpu/risc-v/common/rt_hw_stack_frame.h
+++ b/libcpu/risc-v/common/rt_hw_stack_frame.h
@@ -31,6 +31,7 @@ typedef struct rt_hw_stack_frame
     rt_ubase_t a3;         /* x13 - a3     - function argument 3                 */
     rt_ubase_t a4;         /* x14 - a4     - function argument 4                 */
     rt_ubase_t a5;         /* x15 - a5     - function argument 5                 */
+#ifndef __riscv_32e
     rt_ubase_t a6;         /* x16 - a6     - function argument 6                 */
     rt_ubase_t a7;         /* x17 - a7     - function argument 7                 */
     rt_ubase_t s2;         /* x18 - s2     - saved register 2                    */
@@ -47,6 +48,7 @@ typedef struct rt_hw_stack_frame
     rt_ubase_t t4;         /* x29 - t4     - temporary register 4                */
     rt_ubase_t t5;         /* x30 - t5     - temporary register 5                */
     rt_ubase_t t6;         /* x31 - t6     - temporary register 6                */
+#endif
 #ifdef ARCH_RISCV_FPU
     rv_floatreg_t f0;      /* f0  */
     rv_floatreg_t f1;      /* f1  */
diff --git a/libcpu/risc-v/common/trap_common.c b/libcpu/risc-v/common/trap_common.c
index f8a87e530f..2e978f2aed 100644
--- a/libcpu/risc-v/common/trap_common.c
+++ b/libcpu/risc-v/common/trap_common.c
@@ -96,10 +96,12 @@ rt_weak void rt_show_stack_frame(void)
     rt_kprintf("a3      : 0x%08x\r\n", s_stack_frame->a3);
     rt_kprintf("a4      : 0x%08x\r\n", s_stack_frame->a4);
     rt_kprintf("a5      : 0x%08x\r\n", s_stack_frame->a5);
+#ifndef __riscv_32e
     rt_kprintf("a6      : 0x%08x\r\n", s_stack_frame->a6);
     rt_kprintf("a7      : 0x%08x\r\n", s_stack_frame->a7);
     rt_kprintf("t3      : 0x%08x\r\n", s_stack_frame->t3);
     rt_kprintf("t4      : 0x%08x\r\n", s_stack_frame->t4);
     rt_kprintf("t5      : 0x%08x\r\n", s_stack_frame->t5);
     rt_kprintf("t6      : 0x%08x\r\n", s_stack_frame->t6);
+#endif
 }