diff options
| author | wirano <[email protected]> | 2024-04-18 20:37:48 -0400 |
|---|---|---|
| committer | Rbb666 <[email protected]> | 2024-04-19 15:36:08 +0800 |
| commit | 2d18f033a496aafff8d8c398588a51bb3119d86a (patch) | |
| tree | 4c0a2020cbe80fd00177d4cc37d2e5b5c00b1fe7 /libcpu | |
| parent | 5012edfcdc5e68d7576d6eb88bf21882b7aa375b (diff) | |
[cpu_cache] fix function replaced by macro
Diffstat (limited to 'libcpu')
| -rw-r--r-- | libcpu/arm/cortex-m7/cpu_cache.c | 5 |
1 files changed, 5 insertions, 0 deletions
diff --git a/libcpu/arm/cortex-m7/cpu_cache.c b/libcpu/arm/cortex-m7/cpu_cache.c index fe7acce2a1..6ec4c826d5 100644 --- a/libcpu/arm/cortex-m7/cpu_cache.c +++ b/libcpu/arm/cortex-m7/cpu_cache.c @@ -17,6 +17,8 @@ /* The L1-caches on all Cortex®-M7s are divided into lines of 32 bytes. */ #define L1CACHE_LINESIZE_BYTE (32) +#ifdef RT_USING_CACHE + void rt_hw_cpu_icache_enable(void) { SCB_EnableICache(); @@ -89,3 +91,6 @@ void rt_hw_cpu_dcache_ops(int ops, void* addr, int size) RT_ASSERT(0); } } + +#endif /* RT_USING_CACHE */ + |