diff options
| author | Bernard Xiong <[email protected]> | 2019-06-19 11:41:05 +0800 |
|---|---|---|
| committer | GitHub <[email protected]> | 2019-06-19 11:41:05 +0800 |
| commit | 38d5c2aa725bb0ca31302348cceada846f4ffb5f (patch) | |
| tree | f0e2298e81920ea2ba581002bed2fa6e85af4573 /libcpu | |
| parent | d855d381ae40872cf4d31a0086c807aa702b469b (diff) | |
| parent | fc155f88107ca347fb2d306793476786e544f993 (diff) | |
Merge pull request #2796 from lymzzyh/cache
修复cortex-a 中cache操作没有 dsb isb
Diffstat (limited to 'libcpu')
| -rw-r--r-- | libcpu/arm/cortex-a/cache.c | 6 |
1 files changed, 6 insertions, 0 deletions
diff --git a/libcpu/arm/cortex-a/cache.c b/libcpu/arm/cortex-a/cache.c index 6d28d9e9f9..30af86baa1 100644 --- a/libcpu/arm/cortex-a/cache.c +++ b/libcpu/arm/cortex-a/cache.c @@ -30,6 +30,7 @@ void rt_hw_cpu_icache_invalidate(void *addr, int size) rt_uint32_t start_addr = (rt_uint32_t)addr; rt_uint32_t end_addr = (rt_uint32_t) addr + size + line_size - 1; + asm volatile ("dmb":::"memory"); start_addr &= ~(line_size-1); end_addr &= ~(line_size-1); while (start_addr < end_addr) @@ -37,6 +38,7 @@ void rt_hw_cpu_icache_invalidate(void *addr, int size) asm volatile ("mcr p15, 0, %0, c7, c5, 1" :: "r"(start_addr)); /* icimvau */ start_addr += line_size; } + asm volatile ("dsb\n\tisb":::"memory"); } void rt_hw_cpu_dcache_invalidate(void *addr, int size) @@ -45,6 +47,7 @@ void rt_hw_cpu_dcache_invalidate(void *addr, int size) rt_uint32_t start_addr = (rt_uint32_t)addr; rt_uint32_t end_addr = (rt_uint32_t) addr + size + line_size - 1; + asm volatile ("dmb":::"memory"); start_addr &= ~(line_size-1); end_addr &= ~(line_size-1); while (start_addr < end_addr) @@ -52,6 +55,7 @@ void rt_hw_cpu_dcache_invalidate(void *addr, int size) asm volatile ("mcr p15, 0, %0, c7, c6, 1" :: "r"(start_addr)); /* dcimvac */ start_addr += line_size; } + asm volatile ("dsb":::"memory"); } void rt_hw_cpu_dcache_clean(void *addr, int size) @@ -60,6 +64,7 @@ void rt_hw_cpu_dcache_clean(void *addr, int size) rt_uint32_t start_addr = (rt_uint32_t)addr; rt_uint32_t end_addr = (rt_uint32_t) addr + size + line_size - 1; + asm volatile ("dmb":::"memory"); start_addr &= ~(line_size-1); end_addr &= ~(line_size-1); while (start_addr < end_addr) @@ -67,6 +72,7 @@ void rt_hw_cpu_dcache_clean(void *addr, int size) asm volatile ("mcr p15, 0, %0, c7, c10, 1" :: "r"(start_addr)); /* dccmvac */ start_addr += line_size; } + asm volatile ("dsb":::"memory"); } void rt_hw_cpu_icache_ops(int ops, void *addr, int size) |