diff options
| author | Huang bo <[email protected]> | 2021-12-15 10:43:06 +0800 |
|---|---|---|
| committer | Huang bo <[email protected]> | 2021-12-15 10:43:06 +0800 |
| commit | 466f9ad4e32873008eb6bbd97b4d2ac65e87c7ee (patch) | |
| tree | 1bdc33f87d852cba8cafc3bf44b5ddd55ead0610 /libcpu | |
| parent | c37fcb6049de1ba0c39265a261cc07fad78e6cf6 (diff) | |
删除依赖TI的KeyStone_common.c文件
Diffstat (limited to 'libcpu')
| -rw-r--r-- | libcpu/ti-dsp/c6x/c66xx.h | 28 | ||||
| -rw-r--r-- | libcpu/ti-dsp/c6x/interrupt.c | 5 |
2 files changed, 24 insertions, 9 deletions
diff --git a/libcpu/ti-dsp/c6x/c66xx.h b/libcpu/ti-dsp/c6x/c66xx.h index 903edbfaf1..b69561c163 100644 --- a/libcpu/ti-dsp/c6x/c66xx.h +++ b/libcpu/ti-dsp/c6x/c66xx.h @@ -11,15 +11,25 @@ #ifndef __C66XX_H__ #define __C66XX_H__ -extern cregister volatile unsigned int IERR; /* Internal Exception Report Register */ -extern cregister volatile unsigned int ECR; /* Exception Clear Register */ -extern cregister volatile unsigned int EFR; /* Exception Flag Register */ -extern cregister volatile unsigned int TSR; /* Task State Register */ -extern cregister volatile unsigned int ITSR; /* Interrupt Task State Register */ -extern cregister volatile unsigned int NTSR; /* NMI/exception Task State Register */ -extern cregister volatile unsigned int TSCL; /* Time Stamp Counter Register - Low Half */ -extern cregister volatile unsigned int TSCH; /* Time Stamp Counter Register - High Half */ -extern cregister volatile unsigned int DNUM; /* Core number */ +extern __cregister volatile unsigned int IERR; /* Internal Exception Report Register */ +extern __cregister volatile unsigned int ECR; /* Exception Clear Register */ +extern __cregister volatile unsigned int EFR; /* Exception Flag Register */ +extern __cregister volatile unsigned int TSR; /* Task State Register */ +extern __cregister volatile unsigned int ITSR; /* Interrupt Task State Register */ +extern __cregister volatile unsigned int NTSR; /* NMI/exception Task State Register */ +extern __cregister volatile unsigned int TSCL; /* Time Stamp Counter Register - Low Half */ +extern __cregister volatile unsigned int TSCH; /* Time Stamp Counter Register - High Half */ +extern __cregister volatile unsigned int DNUM; /* Core number */ + +extern __cregister volatile unsigned int AMR; +extern __cregister volatile unsigned int CSR; +extern __cregister volatile unsigned int IFR; +extern __cregister volatile unsigned int ISR; +extern __cregister volatile unsigned int ICR; +extern __cregister volatile unsigned int IER; +extern __cregister volatile unsigned int ISTP; +extern __cregister volatile unsigned int IRP; +extern __cregister volatile unsigned int NRP; #ifdef _BIG_ENDIAN #define RT_REG_PAIR(odd, even) unsigned long odd; unsigned long even diff --git a/libcpu/ti-dsp/c6x/interrupt.c b/libcpu/ti-dsp/c6x/interrupt.c index 1f532f6c32..6e48cb8efa 100644 --- a/libcpu/ti-dsp/c6x/interrupt.c +++ b/libcpu/ti-dsp/c6x/interrupt.c @@ -60,6 +60,11 @@ void rt_hw_interrupt_umask(int vector) { return; } + ICR = vector; + IER |= vector; + + //enable GIE + TSR = TSR | 1; } /** |