diff options
| author | Bernard Xiong <[email protected]> | 2018-12-23 15:24:03 +0800 |
|---|---|---|
| committer | GitHub <[email protected]> | 2018-12-23 15:24:03 +0800 |
| commit | 6db31e30c7ea5ebc33efe294736ae2da6e7e6daa (patch) | |
| tree | 565e96a6ffb71d470ac7f05055a1eed989973b2b /libcpu | |
| parent | 2defcb753ce9db576ea56dbb22c32b709b29a449 (diff) | |
| parent | 597d71cc032bf30098c2a5f890eec48ce5ff418d (diff) | |
Merge pull request #2098 from RT-Thread/bsp_k210
[bsp][k210] Add get_free_heap_size function.
Diffstat (limited to 'libcpu')
| -rw-r--r-- | libcpu/risc-v/k210/interrupt.c | 14 | ||||
| -rw-r--r-- | libcpu/risc-v/k210/startup_gcc.S | 5 |
2 files changed, 18 insertions, 1 deletions
diff --git a/libcpu/risc-v/k210/interrupt.c b/libcpu/risc-v/k210/interrupt.c index 6d8866c3f0..f9c3eb5a67 100644 --- a/libcpu/risc-v/k210/interrupt.c +++ b/libcpu/risc-v/k210/interrupt.c @@ -114,6 +114,13 @@ rt_isr_handler_t rt_hw_interrupt_install(int vector, rt_isr_handler_t handler, return old_handler; } +RT_WEAK +void plic_irq_handle(plic_irq_t irq) +{ + rt_kprintf("UN-handled interrupt %d occurred!!!\n", irq); + return ; +} + uintptr_t handle_irq_m_ext(uintptr_t cause, uintptr_t epc) { /* @@ -142,7 +149,12 @@ uintptr_t handle_irq_m_ext(uintptr_t cause, uintptr_t epc) /* Disable software interrupt and timer interrupt */ clear_csr(mie, MIP_MTIP | MIP_MSIP); - if (irq_desc[core_id][int_num].handler) + if (irq_desc[core_id][int_num].handler == (rt_isr_handler_t)rt_hw_interrupt_handle) + { + /* default handler, route to kendryte bsp plic driver */ + plic_irq_handle(int_num); + } + else if (irq_desc[core_id][int_num].handler) { irq_desc[core_id][int_num].handler(int_num, irq_desc[core_id][int_num].param); } diff --git a/libcpu/risc-v/k210/startup_gcc.S b/libcpu/risc-v/k210/startup_gcc.S index bc73f51e03..2e69c5021e 100644 --- a/libcpu/risc-v/k210/startup_gcc.S +++ b/libcpu/risc-v/k210/startup_gcc.S @@ -16,6 +16,11 @@ _start: j 1f .word 0xdeadbeef + .align 3 + .global g_wake_up + g_wake_up: + .dword 1 + .dword 0 1: csrw mideleg, 0 csrw medeleg, 0 |