update mini2440 bsp.

git-svn-id: https://rt-thread.googlecode.com/svn/trunk@206 bbd45198-f89e-11dd-88c7-29a3b14d5316

3 files changed, 137 insertions, 11 deletions

diff --git a/libcpu/arm/s3c24x0/cpu.c b/libcpu/arm/s3c24x0/cpu.c
index 356254a9db..8a31ed80d2 100644
--- a/libcpu/arm/s3c24x0/cpu.c
+++ b/libcpu/arm/s3c24x0/cpu.c
@@ -23,7 +23,8 @@
 #define ICACHE_MASK	(rt_uint32_t)(1 << 12)

 #define DCACHE_MASK	(rt_uint32_t)(1 << 2)

 

-static rt_uint32_t cp15_rd(void)

+#ifdef __GNU_C__

+rt_inline rt_uint32_t cp15_rd(void)

 {

 	rt_uint32_t i;

 

@@ -41,16 +42,56 @@ rt_inline void cache_enable(rt_uint32_t bit)
 		:"r" (bit)					\

 		:"memory");

 }

+

 rt_inline void cache_disable(rt_uint32_t bit)

 {

 	__asm__ __volatile__(			\

 		"mrc  p15,0,r0,c1,c0,0\n\t"	\

 		"bic  r0,r0,%0\n\t"			\

-		"mcr  p15,0,%0,c1,c0,0"		\

+		"mcr  p15,0,r0,c1,c0,0"		\

 		:							\

 		:"r" (bit)					\

 		:"memory");

 }

+#endif

+

+#ifdef __CC_ARM

+rt_inline rt_uint32_t cp15_rd(void)

+{

+	rt_uint32_t i;

+

+	__asm

+	{

+		mrc p15, 0, i, c1, c0, 0

+	}

+

+	return i;

+}

+

+rt_inline void cache_enable(rt_uint32_t bit)

+{

+	rt_uint32_t value;

+

+	__asm

+	{

+		mrc p15, 0, value, c1, c0, 0

+		orr value, value, bit

+		mcr p15, 0, value, c1, c0, 0

+	}

+}

+

+rt_inline void cache_disable(rt_uint32_t bit)

+{

+	rt_uint32_t value;

+

+	__asm

+	{

+		mrc p15, 0, value, c1, c0, 0

+		bic value, value, bit

+		mcr p15, 0, value, c1, c0, 0

+	}

+}

+#endif

 

 /**

  * enable I-Cache

@@ -126,7 +167,7 @@ void rt_hw_cpu_reset()
 

 	while(1);	/* loop forever and wait for reset to happen */

 

-	/*NOTREACHED*/

+	/* NEVER REACHED */

 }

 

 /**

diff --git a/libcpu/arm/s3c24x0/mmu.c b/libcpu/arm/s3c24x0/mmu.c
index d86621fc53..9f972c6322 100644
--- a/libcpu/arm/s3c24x0/mmu.c
+++ b/libcpu/arm/s3c24x0/mmu.c
@@ -40,8 +40,7 @@
 #define RW_NCNB		(AP_RW|DOMAIN0|NCNB|DESC_SEC)

 #define RW_FAULT	(AP_RW|DOMAIN1|NCNB|DESC_SEC)

 

-void rt_hw_mmu_init(void);

-

+#ifdef __GNU_C__

 void mmu_setttbase(register rt_uint32_t i)

 {

 	asm ("mcr p15, 0, %0, c2, c2, 0": :"r" (i));

@@ -170,6 +169,92 @@ void mmu_invalidateicache()
 {

 	asm ("mcr p15, 0, %0, c7, c5, 0": :"r" (0));

 }

+#endif

+

+#ifdef __CC_ARM

+__asm void mmu_setttbase(rt_uint32_t i)

+{

+	mcr p15, 0, r0, c2, c2, 0

+}

+

+__asm void mmu_setdomain(rt_uint32_t i)

+{

+	mcr p15,0, r0, c3, c0,  0

+}

+

+__asm void mmu_enablemmu()

+{

+	mrc p15, 0, r0, c1, c0, 0

+	orr r0, r0, #0x01

+	mcr p15, 0, r0, c1, c0, 0

+}

+

+__asm void mmu_disablemmu()

+{

+	mrc p15, 0, r0, c1, c0, 0

+	bic r0, r0, #0x01

+	mcr p15, 0, r0, c1, c0, 0

+}

+

+__asm void mmu_enableicache()

+{

+	mrc p15, 0, r0, c1, c0, 0

+	orr r0, r0, #0x100

+	mcr p15, 0, r0, c1, c0, 0

+}

+

+__asm void mmu_enabledcache()

+{

+	mrc p15, 0, r0, c1, c0, 0

+	orr r0, r0, #0x02

+	mcr p15, 0, r0, c1, c0, 0

+}

+

+__asm void mmu_disableicache()

+{

+	mrc p15, 0, r0, c1, c0, 0

+	bic r0, r0, #0x100

+	mcr p15, 0, r0, c1, c0, 0

+}

+

+__asm void mmu_disabledcache()

+{

+	mrc p15, 0, r0, c1, c0, 0

+	bic r0, r0, #0x100

+	mcr p15, 0, r0, c1, c0, 0

+}

+

+__asm void mmu_enablealignfault()

+{

+	mrc p15, 0, r0, c1, c0, 0

+	bic r0, r0, #0x01

+	mcr p15, 0, r0, c1, c0, 0

+}

+

+__asm void mmu_disablealignfault()

+{

+	mrc p15, 0, r0, c1, c0, 0

+	bic r0, r0, #0x02

+	mcr p15, 0, r0, c1, c0, 0

+}

+

+__asm void mmu_cleaninvalidatedcacheindex(int index)

+{

+	mcr p15, 0, r0, c7, c14, 2

+}

+

+__asm void mmu_invalidatetlb()

+{

+	mov r0, #0x0

+	mcr p15, 0, r0, c8, c7, 0

+}

+

+__asm void mmu_invalidateicache()

+{

+	mov r0, #0

+	mcr p15, 0, r0, c7, c5, 0

+}

+#endif

 

 void mmu_setmtt(int vaddrStart,int vaddrEnd,int paddrStart,int attr)

 {

diff --git a/libcpu/arm/s3c24x0/rtc.c b/libcpu/arm/s3c24x0/rtc.c
index 6f69840569..b49292ce7c 100644
--- a/libcpu/arm/s3c24x0/rtc.c
+++ b/libcpu/arm/s3c24x0/rtc.c
@@ -17,26 +17,26 @@
 /**

  * This function access to rtc

  */

-static inline void rt_hw_rtc_access(int a)

+rt_inline void rt_hw_rtc_access(int a)

 {

 	switch (a)

 	{

 	case RTC_ENABLE:

-		RTCCON |= 0x01; 

+		RTCCON |= 0x01;

 		break;

 

 	case RTC_DISABLE:

-		RTCCON &= ~0x01; 

+		RTCCON &= ~0x01;

 		break;

 	}

 }

 

-static inline rt_uint32_t BCD2BIN(rt_uint8_t n)

+rt_inline rt_uint32_t BCD2BIN(rt_uint8_t n)

 {

         return ((((n >> 4) & 0x0F) * 10) + (n & 0x0F));

 }

 

-static inline rt_uint8_t BIN2BCD(rt_uint32_t n)

+rt_inline rt_uint8_t BIN2BCD(rt_uint32_t n)

 {

         return (((n / 10) << 4) | (n % 10));

 }

@@ -53,7 +53,7 @@ void rt_hw_rtc_get (struct rtc_time *tmp)
 	rt_hw_rtc_access(RTC_ENABLE);

 

 	/* read RTC registers */

-	do 

+	do

 	{

 		sec = BCDSEC;

 		min = BCDMIN;