diff options
| author | Meco Man <[email protected]> | 2021-02-05 20:44:25 +0800 |
|---|---|---|
| committer | GitHub <[email protected]> | 2021-02-05 20:44:25 +0800 |
| commit | 852d7d7552bd3fe898115ea16ba401970b0d1fad (patch) | |
| tree | f7c13c061ecaa47e70f0f856cc685bba25866429 /libcpu | |
| parent | 97cc8a8f72838deb0273a3e60ae29319edd7e4f7 (diff) | |
| parent | 7fc236dddb14bcf5dba8e304efde9c3a518a117c (diff) | |
Merge pull request #15 from RT-Thread/master
pr
Diffstat (limited to 'libcpu')
| -rw-r--r-- | libcpu/mips/gs232/gs232.h | 9 | ||||
| -rw-r--r-- | libcpu/mips/gs232/interrupt.c | 1 | ||||
| -rw-r--r-- | libcpu/mips/gs232/ls1b.h | 11 |
3 files changed, 18 insertions, 3 deletions
diff --git a/libcpu/mips/gs232/gs232.h b/libcpu/mips/gs232/gs232.h index 6e90f7ba66..95c81cf93e 100644 --- a/libcpu/mips/gs232/gs232.h +++ b/libcpu/mips/gs232/gs232.h @@ -17,7 +17,14 @@ #define INTC_BASE 0xBFD01040 +#ifdef SOC_LS1B +#define GS232_INTC_CELLS 4 +#endif + +#ifdef SOC_LS1C300 #define GS232_INTC_CELLS 5 +#endif + #define GS232_NR_IRQS (32 * GS232_INTC_CELLS) #define GMAC0_BASE 0xBFE10000 @@ -64,4 +71,4 @@ extern void rt_hw_timer_init(void); #endif -#endif
\ No newline at end of file +#endif diff --git a/libcpu/mips/gs232/interrupt.c b/libcpu/mips/gs232/interrupt.c index f3e0f80763..66abea379d 100644 --- a/libcpu/mips/gs232/interrupt.c +++ b/libcpu/mips/gs232/interrupt.c @@ -22,7 +22,6 @@ #define MAX_INTR (GS232_NR_IRQS) static struct rt_irq_desc irq_handle_table[MAX_INTR]; -void rt_interrupt_dispatch(void *ptreg); void rt_hw_timer_handler(); static struct gs232_intc_regs volatile *gs232_hw0_icregs diff --git a/libcpu/mips/gs232/ls1b.h b/libcpu/mips/gs232/ls1b.h index 071a4aeb82..a6f244ef4f 100644 --- a/libcpu/mips/gs232/ls1b.h +++ b/libcpu/mips/gs232/ls1b.h @@ -19,6 +19,15 @@ #define LS1B_UART1_IRQ 3 #define LS1B_UART2_IRQ 4 #define LS1B_UART3_IRQ 5 +#define LS1B_UART4_IRQ 29 +#define LS1B_UART5_IRQ 30 +#define LS1B_UART6_IRQ 2 //共享LS1B_UART0_IRQ +#define LS1B_UART7_IRQ 2 +#define LS1B_UART8_IRQ 2 +#define LS1B_UART9_IRQ 3 //共享LS1B_UART1_IRQ +#define LS1B_UART10_IRQ 3 +#define LS1B_UART11_IRQ 3 + #define LS1B_CAN0_IRQ 6 #define LS1B_CAN1_IRQ 7 #define LS1B_SPI0_IRQ 8 @@ -49,7 +58,7 @@ #define LS1B_GPIO_IRQ 64 #define LS1B_GPIO_FIRST_IRQ 64 -#define LS1B_GPIO_IRQ_COUNT 96 +#define LS1B_GPIO_IRQ_COUNT 64 #define LS1B_GPIO_LAST_IRQ (LS1B_GPIO_FIRST_IRQ + LS1B_GPIO_IRQ_COUNT-1) #define INT_PCI_INTA (1<<6) |