Merge pull request #3468 from bigmagic123/aarch64_cache_api

Aarch64 cache api

9 files changed, 292 insertions, 652 deletions

diff --git a/libcpu/aarch64/cortex-a53/SConscript b/libcpu/aarch64/cortex-a53/SConscript
index 57a5accc5c..75e170a0cf 100644
--- a/libcpu/aarch64/cortex-a53/SConscript
+++ b/libcpu/aarch64/cortex-a53/SConscript
@@ -7,6 +7,7 @@ context_gcc.S
 vector_gcc.S
 entry_point.S
 cpu_gcc.S
+cache.S
 ''')
 CPPPATH = [cwd]
 
diff --git a/libcpu/aarch64/cortex-a53/cache.S b/libcpu/aarch64/cortex-a53/cache.S
new file mode 100644
index 0000000000..7f295a2b02
--- /dev/null
+++ b/libcpu/aarch64/cortex-a53/cache.S
@@ -0,0 +1,151 @@
+/*
+ * Copyright (c) 2006-2020, RT-Thread Development Team
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Change Logs:
+ * Date           Author             Notes
+ * 2020-03-17     bigmagic           first version
+ */
+
+/*
+ * void __asm_dcache_level(level)
+ *
+ * flush or invalidate one level cache.
+ *
+ * x0: cache level
+ * x1: 0 clean & invalidate, 1 invalidate only
+ * x2~x9: clobbered
+ */
+.globl __asm_dcache_level
+__asm_dcache_level:
+    lsl    x12, x0, #1
+    msr    csselr_el1, x12        /* select cache level */
+    isb                /* sync change of cssidr_el1 */
+    mrs    x6, ccsidr_el1        /* read the new cssidr_el1 */
+    and    x2, x6, #7        /* x2 <- log2(cache line size)-4 */
+    add    x2, x2, #4        /* x2 <- log2(cache line size) */
+    mov    x3, #0x3ff
+    and    x3, x3, x6, lsr #3    /* x3 <- max number of #ways */
+    clz    w5, w3            /* bit position of #ways */
+    mov    x4, #0x7fff
+    and    x4, x4, x6, lsr #13    /* x4 <- max number of #sets */
+    /* x12 <- cache level << 1 */
+    /* x2 <- line length offset */
+    /* x3 <- number of cache ways - 1 */
+    /* x4 <- number of cache sets - 1 */
+    /* x5 <- bit position of #ways */
+
+loop_set:
+    mov    x6, x3            /* x6 <- working copy of #ways */
+loop_way:
+    lsl    x7, x6, x5
+    orr    x9, x12, x7        /* map way and level to cisw value */
+    lsl    x7, x4, x2
+    orr    x9, x9, x7        /* map set number to cisw value */
+    tbz    w1, #0, 1f
+    dc    isw, x9
+    b    2f
+1:    dc    cisw, x9        /* clean & invalidate by set/way */
+2:    subs    x6, x6, #1        /* decrement the way */
+    b.ge    loop_way
+    subs    x4, x4, #1        /* decrement the set */
+    b.ge    loop_set
+
+    ret
+
+/*
+ * void __asm_flush_dcache_all(int invalidate_only)
+ *
+ * x0: 0 clean & invalidate, 1 invalidate only
+ *
+ * flush or invalidate all data cache by SET/WAY.
+ */
+.globl __asm_dcache_all
+__asm_dcache_all:
+    mov    x1, x0
+    dsb    sy
+    mrs    x10, clidr_el1        /* read clidr_el1 */
+    lsr    x11, x10, #24
+    and    x11, x11, #0x7        /* x11 <- loc */
+    cbz    x11, finished        /* if loc is 0, exit */
+    mov    x15, lr
+    mov    x0, #0            /* start flush at cache level 0 */
+    /* x0  <- cache level */
+    /* x10 <- clidr_el1 */
+    /* x11 <- loc */
+    /* x15 <- return address */
+
+loop_level:
+    lsl    x12, x0, #1
+    add    x12, x12, x0        /* x0 <- tripled cache level */
+    lsr    x12, x10, x12
+    and    x12, x12, #7        /* x12 <- cache type */
+    cmp    x12, #2
+    b.lt    skip            /* skip if no cache or icache */
+    bl    __asm_dcache_level    /* x1 = 0 flush, 1 invalidate */
+skip:
+    add    x0, x0, #1        /* increment cache level */
+    cmp    x11, x0
+    b.gt    loop_level
+
+    mov    x0, #0
+    msr    csselr_el1, x0        /* restore csselr_el1 */
+    dsb    sy
+    isb
+    mov    lr, x15
+
+finished:
+    ret
+
+.globl __asm_flush_dcache_all
+__asm_flush_dcache_all:
+    mov    x0, #0
+    b    __asm_dcache_all
+
+.globl __asm_invalidate_dcache_all
+__asm_invalidate_dcache_all:
+    mov    x0, #0x1
+    b    __asm_dcache_all
+
+/*
+ * void __asm_flush_dcache_range(start, end)
+ *
+ * clean & invalidate data cache in the range
+ *
+ * x0: start address
+ * x1: end address
+ */
+.globl __asm_flush_dcache_range
+__asm_flush_dcache_range:
+    mrs    x3, ctr_el0
+    lsr    x3, x3, #16
+    and    x3, x3, #0xf
+    mov    x2, #4
+    lsl    x2, x2, x3        /* cache line size */
+
+    /* x2 <- minimal cache line size in cache system */
+    sub    x3, x2, #1
+    bic    x0, x0, x3
+1:    dc    civac, x0    /* clean & invalidate data or unified cache */
+    add    x0, x0, x2
+    cmp    x0, x1
+    b.lo    1b
+    dsb    sy
+    ret
+
+/*
+ * void __asm_invalidate_icache_all(void)
+ *
+ * invalidate all tlb entries.
+ */
+.globl __asm_invalidate_icache_all
+__asm_invalidate_icache_all:
+    ic    ialluis
+    isb    sy
+    ret
+
+.globl __asm_flush_l3_cache
+__asm_flush_l3_cache:
+    mov    x0, #0            /* return status as success */
+    ret
\ No newline at end of file
diff --git a/libcpu/aarch64/cortex-a53/mmu.c b/libcpu/aarch64/cortex-a53/mmu.c
index aab6bf9ebe..b799143084 100644
--- a/libcpu/aarch64/cortex-a53/mmu.c
+++ b/libcpu/aarch64/cortex-a53/mmu.c
@@ -9,6 +9,7 @@
  */
 #include <mmu.h>
 #include <stddef.h>
+#include <rthw.h>
 
 #define TTBR_CNP    1
 
@@ -35,6 +36,13 @@ static unsigned long main_tbl[512 * 20] __attribute__((aligned (4096)));
 
 int free_idx = 1;
 
+void __asm_invalidate_icache_all(void);
+void __asm_flush_dcache_all(void);
+int __asm_flush_l3_cache(void);
+void __asm_flush_dcache_range(unsigned long long start, unsigned long long end);
+void __asm_invalidate_dcache_all(void);
+void __asm_invalidate_icache_all(void);
+
 void mmu_memset(char *dst, char v,  size_t len)
 {
     while (len--)
@@ -50,6 +58,20 @@ static unsigned long get_free_page(void)
     return (unsigned long)(main_tbl + __page_off);
 }
 
+
+static inline unsigned int get_sctlr(void)
+{
+    unsigned int val;
+    asm volatile("mrs %0, sctlr_el1" : "=r" (val) : : "cc");
+    return val;
+}
+
+static inline void set_sctlr(unsigned int val)
+{
+    asm volatile("msr sctlr_el1, %0" : : "r" (val) : "cc");
+    asm volatile("isb");
+}
+
 void mmu_init(void)
 {
     unsigned long val64;
@@ -101,6 +123,9 @@ void mmu_enable(void)
     __asm__ volatile("mrs %0, SCTLR_EL1\n":"=r"(val32));
     val32 |= 0x1005; //enable mmu, I C M
     __asm__ volatile("dmb sy\n msr SCTLR_EL1, %0\nisb sy\n"::"r"(val32));
+    rt_hw_icache_enable();
+    rt_hw_dcache_enable();
+
 }
 
 static int map_single_page_2M(unsigned long* lv0_tbl, unsigned long va, unsigned long pa, unsigned long attr) 
@@ -271,3 +296,72 @@ void armv8_map(unsigned long va, unsigned long pa, unsigned long size, unsigned
     map_region(va, pa, size, attr);
 }
 
+void rt_hw_dcache_enable(void)
+{
+    if (!(get_sctlr() & CR_M)) 
+    {
+        rt_kprintf("please init mmu!\n");
+    }
+    else
+    {
+        set_sctlr(get_sctlr() | CR_C);
+    }
+}
+
+void rt_hw_dcache_flush_all(void)
+{
+    int ret;
+
+    __asm_flush_dcache_all();
+    ret = __asm_flush_l3_cache();
+    if (ret)
+    {
+        rt_kprintf("flushing dcache returns 0x%x\n", ret);
+    }
+    else
+    {
+        rt_kprintf("flushing dcache successfully.\n");
+    }
+}
+
+void rt_hw_dcache_flush_range(unsigned long start_addr, unsigned long size)
+{
+    __asm_flush_dcache_range(start_addr, start_addr + size);
+}
+void rt_hw_dcache_invalidate_range(unsigned long start_addr,unsigned long size)
+{
+    __asm_flush_dcache_range(start_addr, start_addr + size);
+}
+
+void rt_hw_dcache_invalidate_all(void)
+{
+    __asm_invalidate_dcache_all();
+}
+
+void rt_hw_dcache_disable(void)
+{
+    /* if cache isn't enabled no need to disable */
+    if(!(get_sctlr() & CR_C))
+    {
+        rt_kprintf("need enable cache!\n");
+        return;
+    }
+    set_sctlr(get_sctlr() & ~CR_C);
+}
+
+//icache
+void rt_hw_icache_enable(void)
+{
+    __asm_invalidate_icache_all();
+    set_sctlr(get_sctlr() | CR_I);
+}
+
+void rt_hw_icache_invalidate_all(void)
+{
+    __asm_invalidate_icache_all();
+}
+
+void rt_hw_icache_disable(void)
+{
+    set_sctlr(get_sctlr() & ~CR_I);
+}
\ No newline at end of file
diff --git a/libcpu/aarch64/cortex-a53/mmu.h b/libcpu/aarch64/cortex-a53/mmu.h
index 61d64164b1..6a66472c79 100644
--- a/libcpu/aarch64/cortex-a53/mmu.h
+++ b/libcpu/aarch64/cortex-a53/mmu.h
@@ -11,6 +11,37 @@
 #ifndef  __MMU_H__
 #define  __MMU_H__
 
+/*
+ * CR1 bits (CP#15 CR1)
+ */
+#define CR_M    (1 << 0)    /* MMU enable                */
+#define CR_A    (1 << 1)    /* Alignment abort enable        */
+#define CR_C    (1 << 2)    /* Dcache enable            */
+#define CR_W    (1 << 3)    /* Write buffer enable            */
+#define CR_P    (1 << 4)    /* 32-bit exception handler        */
+#define CR_D    (1 << 5)    /* 32-bit data address range        */
+#define CR_L    (1 << 6)    /* Implementation defined        */
+#define CR_B    (1 << 7)    /* Big endian                */
+#define CR_S    (1 << 8)    /* System MMU protection        */
+#define CR_R    (1 << 9)    /* ROM MMU protection            */
+#define CR_F    (1 << 10)    /* Implementation defined        */
+#define CR_Z    (1 << 11)    /* Implementation defined        */
+#define CR_I    (1 << 12)    /* Icache enable            */
+#define CR_V    (1 << 13)    /* Vectors relocated to 0xffff0000    */
+#define CR_RR   (1 << 14)    /* Round Robin cache replacement    */
+#define CR_L4   (1 << 15)    /* LDR pc can set T bit            */
+#define CR_DT   (1 << 16)
+#define CR_IT   (1 << 18)
+#define CR_ST   (1 << 19)
+#define CR_FI   (1 << 21)    /* Fast interrupt (lower latency mode)    */
+#define CR_U    (1 << 22)    /* Unaligned access operation        */
+#define CR_XP   (1 << 23)    /* Extended page tables            */
+#define CR_VE   (1 << 24)    /* Vectored interrupts            */
+#define CR_EE   (1 << 25)    /* Exception (Big) Endian        */
+#define CR_TRE  (1 << 28)    /* TEX remap enable            */
+#define CR_AFE  (1 << 29)    /* Access flag enable            */
+#define CR_TE   (1 << 30)    /* Thumb exception enable        */
+
 #define MMU_LEVEL_MASK 0x1ffUL
 #define MMU_MAP_ERROR_VANOTALIGN  -1
 #define MMU_MAP_ERROR_PANOTALIGN  -2
@@ -20,7 +51,7 @@
 #define MEM_ATTR_MEMORY ((0x1UL << 10) | (0x2UL << 8) | (0x0UL << 6) | (0x1UL << 2))
 #define MEM_ATTR_IO     ((0x1UL << 10) | (0x2UL << 8) | (0x0UL << 6) | (0x2UL << 2))
 
-#define BUS_ADDRESS(phys)	(((phys) & ~0xC0000000)  |  0xC0000000)
+#define BUS_ADDRESS(phys)    (((phys) & ~0xC0000000)  |  0xC0000000)
 
 void mmu_init(void);
 
@@ -30,4 +61,18 @@ int armv8_map_2M(unsigned long va, unsigned long pa, int count, unsigned long at
 
 void armv8_map(unsigned long va, unsigned long pa, unsigned long size, unsigned long attr);
 
+//dcache
+void rt_hw_dcache_enable(void);
+void rt_hw_dcache_flush_all(void);
+void rt_hw_dcache_flush_range(unsigned long start_addr, unsigned long size);
+void rt_hw_dcache_invalidate_range(unsigned long start_addr,unsigned long size);
+void rt_hw_dcache_invalidate_all(void);
+void rt_hw_dcache_disable(void);
+
+//icache
+void rt_hw_icache_enable(void);
+void rt_hw_icache_invalidate_all(void);
+void rt_hw_icache_disable(void);
+
+
 #endif  /*__MMU_H__*/
diff --git a/libcpu/arm/cortex-a53/cp15.h b/libcpu/arm/cortex-a53/cp15.h
deleted file mode 100644
index 14b85b7e64..0000000000
--- a/libcpu/arm/cortex-a53/cp15.h
+++ /dev/null
@@ -1,168 +0,0 @@
-/*
- * Copyright (c) 2006-2019, RT-Thread Development Team
- *
- * SPDX-License-Identifier: Apache-2.0
- *
- * Change Logs:
- * Date           Author       Notes
- * 2011-09-15     Bernard      first version
- */
-#include "raspi.h"
-#ifndef __CP15_H__
-#define __CP15_H__
-
-#ifndef   __STATIC_FORCEINLINE
-#define __STATIC_FORCEINLINE     __attribute__((always_inline)) static inline
-#endif
-
-#define __WFI()    __asm__ volatile ("wfi":::"memory")
-
-#define __WFE()    __asm__ volatile ("wfe":::"memory")
-
-#define __SEV()    __asm__ volatile ("sev")
-
-__STATIC_FORCEINLINE  void __ISB(void)
-{
-    __asm__ volatile ("isb 0xF":::"memory");
-}
-
-
-/**
-  \brief   Data Synchronization Barrier
-  \details Acts as a special kind of Data Memory Barrier.
-           It completes when all explicit memory accesses before this instruction complete.
- */
-__STATIC_FORCEINLINE  void __DSB(void)
-{
-    __asm__ volatile ("dsb 0xF":::"memory");
-}
-
-/**
-  \brief   Data Memory Barrier
-  \details Ensures the apparent order of the explicit memory operations before
-           and after the instruction, without ensuring their completion.
- */
-
-__STATIC_FORCEINLINE  void __DMB(void)
-{
-    __asm__ volatile ("dmb 0xF":::"memory");
-}
-
-
-#ifdef RT_USING_SMP
-static inline void send_ipi_msg(int cpu, int ipi_vector)
-{
-    IPI_MAILBOX_SET(cpu) = 1 << ipi_vector;
-}
-
-static inline void setup_bootstrap_addr(int cpu, int addr)
-{
-	CORE_MAILBOX3_SET(cpu) = addr;
-}
-
-static inline void enable_cpu_ipi_intr(int cpu)
-{
-    COREMB_INTCTL(cpu) = IPI_MAILBOX_INT_MASK;
-}
-
-static inline void enable_cpu_timer_intr(int cpu)
-{
-	CORETIMER_INTCTL(cpu) = 0x8;
-}
-
-static inline void enable_cntv(void)
-{
-    rt_uint32_t cntv_ctl;
-    cntv_ctl = 1;
-    asm volatile ("mcr p15, 0, %0, c14, c3, 1" :: "r"(cntv_ctl)); // write CNTV_CTL
-}
-
-static inline void disable_cntv(void)
-{
-    rt_uint32_t cntv_ctl;
-    cntv_ctl = 0;
-    asm volatile ("mcr p15, 0, %0, c14, c3, 1" :: "r"(cntv_ctl)); // write CNTV_CTL
-}
-
-static inline  void mask_cntv(void)
-{
-    rt_uint32_t cntv_ctl;
-    cntv_ctl = 2;
-    asm volatile ("mcr p15, 0, %0, c14, c3, 1" :: "r"(cntv_ctl)); // write CNTV_CTL
-}
-
-static inline void unmask_cntv(void)
-{
-    rt_uint32_t cntv_ctl;
-    cntv_ctl = 1;
-    asm volatile ("mcr p15, 0, %0, c14, c3, 1" :: "r"(cntv_ctl)); // write CNTV_CTL
-}
-
-static inline rt_uint64_t read_cntvct(void)
-{
-    rt_uint32_t val,val1;
-    asm volatile ("mrrc p15, 1, %0, %1, c14" : "=r" (val),"=r" (val1));
-    return (val);
-}
-
-static inline rt_uint64_t read_cntvoff(void)
-{
-
-    rt_uint64_t val;
-    asm volatile ("mrrc p15, 4, %Q0, %R0, c14" : "=r" (val));
-    return (val);
-}
-
-static inline rt_uint32_t read_cntv_tval(void)
-{
-    rt_uint32_t val;
-    asm volatile ("mrc p15, 0, %0, c14, c3, 0" : "=r"(val));
-    return val;
-}
-
-
-static inline  void write_cntv_tval(rt_uint32_t val)
-{
-    asm volatile ("mcr p15, 0, %0, c14, c3, 0" :: "r"(val));
-    return;
-}
-
-static inline rt_uint32_t read_cntfrq(void)
-{
-    rt_uint32_t val;
-    asm volatile ("mrc p15, 0, %0, c14, c0, 0" : "=r"(val));
-    return val;
-}
-
-
-static inline  rt_uint32_t read_cntctrl(void)
-{
-    rt_uint32_t val;
-    asm volatile ("mrc p15, 0, %0, c14, c1, 0" : "=r"(val));
-    return val;
-}
-
-static inline uint32_t write_cntctrl(uint32_t val)
-{
-
-    asm volatile ("mcr p15, 0, %0, c14, c1, 0" : :"r"(val));
-    return val;
-}
-#endif
-
-unsigned long rt_cpu_get_smp_id(void);
-
-void rt_cpu_mmu_disable(void);
-void rt_cpu_mmu_enable(void);
-void rt_cpu_tlb_set(volatile unsigned long*);
-
-void rt_cpu_dcache_clean_flush(void);
-void rt_cpu_icache_flush(void);
-
-void rt_cpu_vector_set_base(unsigned int addr);
-void rt_hw_mmu_init(void);
-void rt_hw_vector_init(void);
-
-void set_timer_counter(unsigned int counter);
-void set_timer_control(unsigned int control);
-#endif
diff --git a/libcpu/arm/cortex-a53/cpu.c b/libcpu/arm/cortex-a53/cpu.c
deleted file mode 100644
index 4d02ca35e1..0000000000
--- a/libcpu/arm/cortex-a53/cpu.c
+++ /dev/null
@@ -1,91 +0,0 @@
-/*
- * Copyright (c) 2006-2019, RT-Thread Development Team
- *
- * SPDX-License-Identifier: Apache-2.0
- *
- * Change Logs:
- * Date           Author       Notes
- * 2011-09-15     Bernard      first version
- * 2019-07-28     zdzn         add smp support
- */
-
-#include <rthw.h>
-#include <rtthread.h>
-#include <board.h>
-#include "cp15.h"
-
-int rt_hw_cpu_id(void)
-{
-    int cpu_id;
-    __asm__ volatile (
-            "mrc p15, 0, %0, c0, c0, 5"
-            :"=r"(cpu_id)
-            );
-    cpu_id &= 0xf;
-    return cpu_id;
-};
-
-
-#ifdef RT_USING_SMP
-void rt_hw_spin_lock_init(rt_hw_spinlock_t *lock)
-{
-    lock->slock = 0;
-}
-
-void rt_hw_spin_lock(rt_hw_spinlock_t *lock)
-{
-    unsigned long tmp;
-    unsigned long newval;
-    rt_hw_spinlock_t lockval;
-    __asm__ __volatile__(
-            "pld [%0]"
-            ::"r"(&lock->slock)
-            );
-
-    __asm__ __volatile__(
-            "1: ldrex   %0, [%3]\n"
-            "   add %1, %0, %4\n"
-            "   strex   %2, %1, [%3]\n"
-            "   teq %2, #0\n"
-            "   bne 1b"
-            : "=&r" (lockval), "=&r" (newval), "=&r" (tmp)
-            : "r" (&lock->slock), "I" (1 << 16)
-            : "cc");
-
-    while (lockval.tickets.next != lockval.tickets.owner) 
-    {
-        __WFE();
-        lockval.tickets.owner = *(volatile unsigned short *)(&lock->tickets.owner);
-    }
-
-    __DMB();
-}
-
-void rt_hw_spin_unlock(rt_hw_spinlock_t *lock)
-{
-    __DMB();
-    lock->tickets.owner++;
-    __DSB();
-    __SEV();
-}
-#endif /*RT_USING_SMP*/
-
-/**
- * @addtogroup ARM CPU
- */
-/*@{*/
-
-/** shutdown CPU */
-void rt_hw_cpu_shutdown()
-{
-    rt_uint32_t level;
-    rt_kprintf("shutdown...\n");
-
-    level = rt_hw_interrupt_disable();
-    while (level)
-    {
-        RT_ASSERT(0);
-    }
-}
-
-/*@}*/
diff --git a/libcpu/arm/cortex-a53/interrupt.c b/libcpu/arm/cortex-a53/interrupt.c
deleted file mode 100644
index c9e7c17f8f..0000000000
--- a/libcpu/arm/cortex-a53/interrupt.c
+++ /dev/null
@@ -1,186 +0,0 @@
-/*
- * Copyright (c) 2006-2019, RT-Thread Development Team
- *
- * SPDX-License-Identifier: Apache-2.0
- *
- * Change Logs:
- * Date           Author       Notes
- * 2018/5/3       Bernard      first version
- * 2019-07-28     zdzn         add smp support
- * 2019-08-09     zhangjun     fixup the problem of smp startup and scheduling issues, 
- *                             write addr to mailbox3 to startup smp, and we use mailbox0 for ipi
- */
-
-#include <rthw.h>
-#include <rtthread.h>
-
-#include "cp15.h"
-#include <board.h>
-
-#define MAX_HANDLERS                72
-
-#ifdef RT_USING_SMP
-#define rt_interrupt_nest rt_cpu_self()->irq_nest
-#else
-extern volatile rt_uint8_t rt_interrupt_nest;
-#endif
-
-const unsigned int VECTOR_BASE = 0x00;
-extern void rt_cpu_vector_set_base(unsigned int addr);
-extern int system_vectors;
-
-void rt_hw_vector_init(void)
-{
-    rt_cpu_vector_set_base((unsigned int)&system_vectors);
-}
-
-/* exception and interrupt handler table */
-struct rt_irq_desc isr_table[MAX_HANDLERS];
-
-rt_uint32_t rt_interrupt_from_thread;
-rt_uint32_t rt_interrupt_to_thread;
-rt_uint32_t rt_thread_switch_interrupt_flag;
-
-extern int system_vectors;
-
-static void default_isr_handler(int vector, void *param)
-{
-#ifdef RT_USING_SMP
-    rt_kprintf("cpu %d unhandled irq: %d\n", rt_hw_cpu_id(),vector);
-#else
-    rt_kprintf("unhandled irq: %d\n",vector);
-#endif
-}
-
-/**
- * This function will initialize hardware interrupt
- */
-void rt_hw_interrupt_init(void)
-{
-    rt_uint32_t index;
-
-    /* mask all of interrupts */
-    IRQ_DISABLE_BASIC = 0x000000ff;
-    IRQ_DISABLE1      = 0xffffffff;
-    IRQ_DISABLE2      = 0xffffffff;
-    for (index = 0; index < MAX_HANDLERS; index ++)
-    {
-        isr_table[index].handler = default_isr_handler;
-        isr_table[index].param = NULL;
-#ifdef RT_USING_INTERRUPT_INFO
-        rt_strncpy(isr_table[index].name, "unknown", RT_NAME_MAX);
-        isr_table[index].counter = 0;
-#endif
-    }
-
-    /* init interrupt nest, and context in thread sp */
-    rt_interrupt_nest = 0;
-    rt_interrupt_from_thread = 0;
-    rt_interrupt_to_thread = 0;
-    rt_thread_switch_interrupt_flag = 0;
-}
-
-/**
- * This function will mask a interrupt.
- * @param vector the interrupt number
- */
-void rt_hw_interrupt_mask(int vector)
-{
-
-    if (vector < 32)
-    {
-        IRQ_DISABLE1 = (1 << vector);
-    }
-    else if (vector < 64)
-    {
-        vector = vector % 32;
-        IRQ_DISABLE2 = (1 << vector);
-    }
-    else
-    {
-        vector = vector - 64;
-        IRQ_DISABLE_BASIC = (1 << vector);
-    }
-}
-
-/**
- * This function will un-mask a interrupt.
- * @param vector the interrupt number
- */
-void rt_hw_interrupt_umask(int vector)
-{
-    if (vector < 32)
-    {
-        IRQ_ENABLE1 = (1 << vector);
-    }
-    else if (vector < 64)
-    {
-        vector = vector % 32;
-        IRQ_ENABLE2 = (1 << vector);
-    }
-    else
-    {
-        vector = vector - 64;
-        IRQ_ENABLE_BASIC = (1 << vector);
-    }
-}
-
-/**
- * This function will install a interrupt service routine to a interrupt.
- * @param vector the interrupt number
- * @param new_handler the interrupt service routine to be installed
- * @param old_handler the old interrupt service routine
- */
-rt_isr_handler_t rt_hw_interrupt_install(int vector, rt_isr_handler_t handler,
-        void *param, const char *name)
-{
-    rt_isr_handler_t old_handler = RT_NULL;
-
-    if (vector < MAX_HANDLERS)
-    {
-        old_handler = isr_table[vector].handler;
-
-        if (handler != RT_NULL)
-        {
-#ifdef RT_USING_INTERRUPT_INFO
-            rt_strncpy(isr_table[vector].name, name, RT_NAME_MAX);
-#endif /* RT_USING_INTERRUPT_INFO */
-            isr_table[vector].handler = handler;
-            isr_table[vector].param = param;
-        }
-    }
-
-    return old_handler;
-}
-
-#ifdef RT_USING_SMP
-void rt_hw_ipi_send(int ipi_vector, unsigned int cpu_mask)
-{
-    __DSB();
-    if (cpu_mask & 0x1)
-    {
-        send_ipi_msg(0, ipi_vector);
-    }
-    if (cpu_mask & 0x2)
-    {
-    	send_ipi_msg(1, ipi_vector);
-    }
-    if (cpu_mask & 0x4)
-    {
-    	send_ipi_msg(2, ipi_vector);
-    }
-    if (cpu_mask & 0x8)
-    {
-    	send_ipi_msg(3, ipi_vector);
-    }
-    __DSB();
-}
-#endif
-
-#ifdef RT_USING_SMP
-void rt_hw_ipi_handler_install(int ipi_vector, rt_isr_handler_t ipi_isr_handler)
-{
-    /* note: ipi_vector maybe different with irq_vector */
-    rt_hw_interrupt_install(ipi_vector, ipi_isr_handler, 0, "IPI_HANDLER");
-}
-#endif
diff --git a/libcpu/arm/cortex-a53/interrupt.h b/libcpu/arm/cortex-a53/interrupt.h
deleted file mode 100644
index 9aae0f556a..0000000000
--- a/libcpu/arm/cortex-a53/interrupt.h
+++ /dev/null
@@ -1,18 +0,0 @@
-
-#ifndef __INTERRUPT_H__
-#define __INTERRUPT_H__
-
-#include <rthw.h>
-#include <board.h>
-
-#define INT_IRQ     0x00
-#define INT_FIQ     0x01
-
-void rt_hw_interrupt_init(void);
-void rt_hw_interrupt_mask(int vector);
-void rt_hw_interrupt_umask(int vector);
-
-rt_isr_handler_t rt_hw_interrupt_install(int vector, rt_isr_handler_t handler,
-        void *param, const char *name);
-
-#endif
diff --git a/libcpu/arm/cortex-a53/mmu.c b/libcpu/arm/cortex-a53/mmu.c
deleted file mode 100644
index b3541d2ad4..0000000000
--- a/libcpu/arm/cortex-a53/mmu.c
+++ /dev/null
@@ -1,188 +0,0 @@
-/*
- * Copyright (c) 2006-2019, RT-Thread Development Team
- *
- * SPDX-License-Identifier: Apache-2.0
- *
- * Change Logs:
- * Date           Author       Notes
- * 2012-01-10     bernard      porting to AM1808
- * 2019-07-28     zdzn         add smp support
- */
-
-#include "mmu.h"
-
-/* dump 2nd level page table */
-void rt_hw_cpu_dump_page_table_2nd(rt_uint32_t *ptb)
-{
-    int i;
-    int fcnt = 0;
-
-    for (i = 0; i < 256; i++)
-    {
-        rt_uint32_t pte2 = ptb[i];
-        if ((pte2 & 0x3) == 0)
-        {
-            if (fcnt == 0)
-                rt_kprintf("    ");
-            rt_kprintf("%04x: ", i);
-            fcnt++;
-            if (fcnt == 16)
-            {
-                rt_kprintf("fault\n");
-                fcnt = 0;
-            }
-            continue;
-        }
-        if (fcnt != 0)
-        {
-            rt_kprintf("fault\n");
-            fcnt = 0;
-        }
-
-        rt_kprintf("    %04x: %x: ", i, pte2);
-        if ((pte2 & 0x3) == 0x1)
-        {
-            rt_kprintf("L,ap:%x,xn:%d,texcb:%02x\n",
-                       ((pte2 >> 7) | (pte2 >> 4))& 0xf,
-                       (pte2 >> 15) & 0x1,
-                       ((pte2 >> 10) | (pte2 >> 2)) & 0x1f);
-        }
-        else
-        {
-            rt_kprintf("S,ap:%x,xn:%d,texcb:%02x\n",
-                       ((pte2 >> 7) | (pte2 >> 4))& 0xf, pte2 & 0x1,
-                       ((pte2 >> 4) | (pte2 >> 2)) & 0x1f);
-        }
-    }
-}
-
-void rt_hw_cpu_dump_page_table(rt_uint32_t *ptb)
-{
-    int i;
-    int fcnt = 0;
-
-    rt_kprintf("page table@%p\n", ptb);
-    for (i = 0; i < 1024*4; i++)
-    {
-        rt_uint32_t pte1 = ptb[i];
-        if ((pte1 & 0x3) == 0)
-        {
-            rt_kprintf("%03x: ", i);
-            fcnt++;
-            if (fcnt == 16)
-            {
-                rt_kprintf("fault\n");
-                fcnt = 0;
-            }
-            continue;
-        }
-        if (fcnt != 0)
-        {
-            rt_kprintf("fault\n");
-            fcnt = 0;
-        }
-
-        rt_kprintf("%03x: %08x: ", i, pte1);
-        if ((pte1 & 0x3) == 0x3)
-        {
-            rt_kprintf("LPAE\n");
-        }
-        else if ((pte1 & 0x3) == 0x1)
-        {
-            rt_kprintf("pte,ns:%d,domain:%d\n",
-                       (pte1 >> 3) & 0x1, (pte1 >> 5) & 0xf);
-            /*
-             *rt_hw_cpu_dump_page_table_2nd((void*)((pte1 & 0xfffffc000)
-             *                               - 0x80000000 + 0xC0000000));
-             */
-        }
-        else if (pte1 & (1 << 18))
-        {
-            rt_kprintf("super section,ns:%d,ap:%x,xn:%d,texcb:%02x\n",
-                       (pte1 >> 19) & 0x1,
-                       ((pte1 >> 13) | (pte1 >> 10))& 0xf,
-                       (pte1 >> 4) & 0x1,
-                       ((pte1 >> 10) | (pte1 >> 2)) & 0x1f);
-        }
-        else
-        {
-            rt_kprintf("section,ns:%d,ap:%x,"
-                       "xn:%d,texcb:%02x,domain:%d\n",
-                       (pte1 >> 19) & 0x1,
-                       ((pte1 >> 13) | (pte1 >> 10))& 0xf,
-                       (pte1 >> 4) & 0x1,
-                       (((pte1 & (0x7 << 12)) >> 10) |
-                        ((pte1 &        0x0c) >>  2)) & 0x1f,
-                       (pte1 >> 5) & 0xf);
-        }
-    }
-}
-
-/* level1 page table, each entry for 1MB memory. */
-volatile static unsigned long MMUTable[4*1024] __attribute__((aligned(16*1024)));
-void rt_hw_mmu_setmtt(rt_uint32_t vaddrStart,
-                      rt_uint32_t vaddrEnd,
-                      rt_uint32_t paddrStart,
-                      rt_uint32_t attr)
-{
-    volatile rt_uint32_t *pTT;
-    volatile int i, nSec;
-    pTT  = (rt_uint32_t *)MMUTable + (vaddrStart >> 20);
-    nSec = (vaddrEnd >> 20) - (vaddrStart >> 20);
-    for (i = 0; i <= nSec; i++)
-    {
-        *pTT = attr | (((paddrStart >> 20) + i) << 20);
-        pTT++;
-    }
-}
-
-unsigned long rt_hw_set_domain_register(unsigned long domain_val)
-{
-    unsigned long old_domain;
-
-    asm volatile ("mrc p15, 0, %0, c3, c0\n" : "=r" (old_domain));
-    asm volatile ("mcr p15, 0, %0, c3, c0\n" : :"r" (domain_val) : "memory");
-
-    return old_domain;
-}
-
-void rt_hw_init_mmu_table()
-{
-    /* set page table */
-    /* 4G 1:1 memory */
-    rt_hw_mmu_setmtt(0x00000000, 0x3effffff, 0x00000000, NORMAL_MEM);
-    /* IO memory region */
-    rt_hw_mmu_setmtt(0x3f000000, 0x40010000, 0x3f000000, DEVICE_MEM);
-}
-
-void rt_hw_change_mmu_table(rt_uint32_t vaddrStart,
-                      rt_uint32_t size,
-                      rt_uint32_t paddrStart, rt_uint32_t attr)
-{
-    rt_hw_mmu_setmtt(vaddrStart, vaddrStart+size-1, paddrStart, attr);
-#ifndef RT_USING_SMP
-    rt_cpu_dcache_clean_flush();
-    rt_cpu_icache_flush();
-#endif
-}
-
-
-void rt_hw_mmu_init(void)
-{
-    rt_cpu_dcache_clean_flush();
-    rt_cpu_icache_flush();
-    rt_hw_cpu_dcache_disable();
-    rt_hw_cpu_icache_disable();
-    rt_cpu_mmu_disable();
-
-    /*rt_hw_cpu_dump_page_table(MMUTable);*/
-    rt_hw_set_domain_register(0x55555555);
-
-    rt_cpu_tlb_set(MMUTable);
-
-    rt_cpu_mmu_enable();
-
-    rt_hw_cpu_icache_enable();
-    rt_hw_cpu_dcache_enable();
-}
-