diff options
| author | [email protected] <[email protected]> | 2012-04-14 07:04:27 +0000 |
|---|---|---|
| committer | [email protected] <[email protected]> | 2012-04-14 07:04:27 +0000 |
| commit | a321f3da64987acd1d1f83eba0528a2653dfc6c7 (patch) | |
| tree | 3076a7fd85e6c9dffac9f225e1bd512afc2f1181 /libcpu | |
| parent | 87195cf84ebc323b813899b19ff95b60ef8bc589 (diff) | |
support GNUC cross compiler(GNUM16CM32Cv1101-ELF) for renesas M16C porting
git-svn-id: https://rt-thread.googlecode.com/svn/trunk@2047 bbd45198-f89e-11dd-88c7-29a3b14d5316
Diffstat (limited to 'libcpu')
| -rw-r--r-- | libcpu/m16c/m16c62p/context_gcc.S | 47 | ||||
| -rw-r--r-- | libcpu/m16c/m16c62p/cpuport.c | 22 |
2 files changed, 68 insertions, 1 deletions
diff --git a/libcpu/m16c/m16c62p/context_gcc.S b/libcpu/m16c/m16c62p/context_gcc.S new file mode 100644 index 0000000000..e19b4743d3 --- /dev/null +++ b/libcpu/m16c/m16c62p/context_gcc.S @@ -0,0 +1,47 @@ +/*
+ * File : context.asm
+ * This file is part of RT-Thread RTOS
+ * COPYRIGHT (C) 2009, RT-Thread Development Team
+ *
+ * The license and distribution terms for this file may be
+ * found in the file LICENSE in this distribution or at
+ * http://www.rt-thread.org/license/LICENSE
+ *
+ * Change Logs:
+ * Date Author Notes
+ * 2010-04-09 fify the first version
+ * 2010-04-19 fify rewrite rt_hw_interrupt_disable/enable fuction
+ * 2010-04-20 fify move peripheral ISR to bsp/interrupts.s34
+ */
+
+ .section .text
+
+ .globl _rt_interrupt_from_thread
+ .globl _rt_interrupt_to_thread
+ .global _os_context_switch
+ .type _os_context_switch, @function
+_os_context_switch:
+ PUSHM R0,R1,R2,R3,A0,A1,SB,FB
+
+ MOV.W _rt_interrupt_from_thread, A0
+ STC ISP, [A0]
+ MOV.W _rt_interrupt_to_thread, A0
+ LDC [A0], ISP
+
+ POPM R0,R1,R2,R3,A0,A1,SB,FB ; Restore registers from the new task's stack
+ REIT ; Return from interrup
+
+/*
+ * void rt_hw_context_switch_to(rt_uint32 to);
+ * this fucntion is used to perform the first thread switch
+ */
+ .global _rt_hw_context_switch_to
+ .type _rt_hw_context_switch_to, @function
+_rt_hw_context_switch_to:
+ ENTER #0x0
+ MOV.W 0x5[FB], A0
+ LDC [A0], ISP
+ POPM R0,R1,R2,R3,A0,A1,SB,FB
+ REIT
+
+ .end
diff --git a/libcpu/m16c/m16c62p/cpuport.c b/libcpu/m16c/m16c62p/cpuport.c index e1a36b9cdf..f392097a5d 100644 --- a/libcpu/m16c/m16c62p/cpuport.c +++ b/libcpu/m16c/m16c62p/cpuport.c @@ -87,4 +87,24 @@ void rt_hw_context_switch_interrupt(rt_uint32_t from, rt_uint32_t to) rt_interrupt_from_thread = from;
}
rt_interrupt_to_thread = to;
-}
\ No newline at end of file +}
+
+#if defined(__GNUC__)
+rt_base_t rt_hw_interrupt_disable(void)
+{
+ register rt_uint16_t temp;
+
+ asm("STC FLG, %0":"=r" (temp));
+ asm("FCLR I");
+
+ return (rt_base_t)temp;
+}
+
+void rt_hw_interrupt_enable(rt_base_t level)
+{
+ register rt_uint16_t temp;
+
+ temp = level & 0xffff;
+ asm("LDC %0, FLG": :"r" (temp));
+}
+#endif
\ No newline at end of file |