diff options
| author | Bernard Xiong <[email protected]> | 2017-08-25 11:07:34 +0800 |
|---|---|---|
| committer | GitHub <[email protected]> | 2017-08-25 11:07:34 +0800 |
| commit | b9ebd183ae1e2baf9fdfae34edba7c92285b3577 (patch) | |
| tree | f68e154bfd89e64c86100ced57e3b6e0d518274f /libcpu | |
| parent | 4812729c61e0d5b5b87615bc281088cbd07be1ab (diff) | |
| parent | 2da0eae89c43e1ebd3514dc85fd1d04e0aa4c23f (diff) | |
Merge pull request #827 from caogos/master
[BSP] Add EMAC driver in loongson1C (ported by chinesebear, https://github.com/chinesebear/rtt-net)
Diffstat (limited to 'libcpu')
| -rw-r--r-- | libcpu/mips/loongson_1c/cpuport.c | 36 |
1 files changed, 36 insertions, 0 deletions
diff --git a/libcpu/mips/loongson_1c/cpuport.c b/libcpu/mips/loongson_1c/cpuport.c index 6cdae024c4..f4914dfec4 100644 --- a/libcpu/mips/loongson_1c/cpuport.c +++ b/libcpu/mips/loongson_1c/cpuport.c @@ -121,5 +121,41 @@ rt_uint8_t *rt_hw_stack_init(void *tentry, void *parameter, rt_uint8_t *stack_ad return (rt_uint8_t *)stk; } +#define cache_op(op,addr) \ + __asm__ __volatile__( \ + " .set push \n" \ + " .set noreorder \n" \ + " .set mips3\n\t \n" \ + " cache %0, %1 \n" \ + " .set pop \n" \ + : \ + : "i" (op), "R" (*(unsigned char *)(addr))) + +#if defined(CONFIG_CPU_LOONGSON2) +#define Hit_Invalidate_I 0x00 +#else +#define Hit_Invalidate_I 0x10 +#endif +#define Hit_Invalidate_D 0x11 +#define CONFIG_SYS_CACHELINE_SIZE 32 +#define Hit_Writeback_Inv_D 0x15 + + +void flush_cache(unsigned long start_addr, unsigned long size) +{ + unsigned long lsize = CONFIG_SYS_CACHELINE_SIZE; + unsigned long addr = start_addr & ~(lsize - 1); + unsigned long aend = (start_addr + size - 1) & ~(lsize - 1); + + while (1) { + cache_op(Hit_Writeback_Inv_D, addr); + cache_op(Hit_Invalidate_I, addr); + if (addr == aend) + break; + addr += lsize; + } +} + + /*@}*/ |