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authoraozima <[email protected]>2017-09-01 10:22:55 +0800
committeraozima <[email protected]>2017-09-01 10:22:55 +0800
commitcb247e913f1b21967b89a0e9724c5f1325e598c4 (patch)
tree4572af3fcf6b592a714e2ec76b25dae27a1ecea6 /libcpu
parent7ff28e6ff1aec484f203f3abfdef464374cbbc1a (diff)
update libcpu: cortex-m0 fault handlers always enable.
Diffstat (limited to 'libcpu')
-rw-r--r--libcpu/arm/cortex-m0/context_gcc.S1
-rw-r--r--libcpu/arm/cortex-m0/context_iar.S1
-rw-r--r--libcpu/arm/cortex-m0/context_rvds.S1
3 files changed, 0 insertions, 3 deletions
diff --git a/libcpu/arm/cortex-m0/context_gcc.S b/libcpu/arm/cortex-m0/context_gcc.S
index c95582630a..227a9aac2d 100644
--- a/libcpu/arm/cortex-m0/context_gcc.S
+++ b/libcpu/arm/cortex-m0/context_gcc.S
@@ -182,7 +182,6 @@ rt_hw_context_switch_to:
MSR MSP, R0
/* enable interrupts at processor level */
- CPSIE F
CPSIE I
/* never reach here! */
diff --git a/libcpu/arm/cortex-m0/context_iar.S b/libcpu/arm/cortex-m0/context_iar.S
index e7d680867a..67ea808d8c 100644
--- a/libcpu/arm/cortex-m0/context_iar.S
+++ b/libcpu/arm/cortex-m0/context_iar.S
@@ -188,7 +188,6 @@ rt_hw_context_switch_to:
MSR msp, r0
; enable interrupts at processor level
- CPSIE F
CPSIE I
; never reach here!
diff --git a/libcpu/arm/cortex-m0/context_rvds.S b/libcpu/arm/cortex-m0/context_rvds.S
index 5411162e56..bf68592e63 100644
--- a/libcpu/arm/cortex-m0/context_rvds.S
+++ b/libcpu/arm/cortex-m0/context_rvds.S
@@ -191,7 +191,6 @@ rt_hw_context_switch_to PROC
MSR msp, r0
; enable interrupts at processor level
- CPSIE F
CPSIE I
; never reach here!