diff options
| author | prife <[email protected]> | 2013-03-15 16:58:04 +0800 |
|---|---|---|
| committer | prife <[email protected]> | 2013-03-15 16:58:04 +0800 |
| commit | ce612157daaad107ea670e942d9daf50c2710513 (patch) | |
| tree | 85e34e2165935c8e6a0ec25182afc54a548e20d0 /libcpu | |
| parent | 9a80044a55b7eab10b7616dc726ddbd314b52665 (diff) | |
| parent | be59c9287fdcb47984ae0d6b45dbc55bf9719b67 (diff) | |
Merge branch 'master' of github.com:RT-Thread/rt-thread
Diffstat (limited to 'libcpu')
| -rw-r--r-- | libcpu/mips/jz47xx/start_gcc.S | 10 |
1 files changed, 5 insertions, 5 deletions
diff --git a/libcpu/mips/jz47xx/start_gcc.S b/libcpu/mips/jz47xx/start_gcc.S index 162c491b1d..418a68d0f8 100644 --- a/libcpu/mips/jz47xx/start_gcc.S +++ b/libcpu/mips/jz47xx/start_gcc.S @@ -19,24 +19,24 @@ _start: .set noreorder la ra, _start + li t1, 0x00800000 + mtc0 t1, CP0_CAUSE + /* init cp0 registers. */ li t0, 0x0000FC00 /* BEV = 0 and mask all interrupt */ mtc0 t0, CP0_STATUS - li t1, 0x00800000 - mtc0 t1, CP0_CAUSE - /* setup stack pointer */ li sp, SYSTEM_STACK la gp, _gp /* init caches, assumes a 4way * 128set * 32byte I/D cache */ + mtc0 zero, CP0_TAGLO /* TAGLO reg */ + mtc0 zero, CP0_TAGHI /* TAGHI reg */ li t0, 3 /* enable cache for kseg0 accesses */ mtc0 t0, CP0_CONFIG /* CONFIG reg */ la t0, 0x80000000 /* an idx op should use an unmappable address */ ori t1, t0, 0x4000 /* 16kB cache */ - mtc0 zero, CP0_TAGLO /* TAGLO reg */ - mtc0 zero, CP0_TAGHI /* TAGHI reg */ _cache_loop: cache 0x8, 0(t0) /* index store icache tag */ |