diff options
| author | weety <[email protected]> | 2013-04-08 21:57:24 +0800 |
|---|---|---|
| committer | weety <[email protected]> | 2013-04-08 21:57:24 +0800 |
| commit | d9d39a8d21c925d1bfb8284687f96c5810911428 (patch) | |
| tree | 161f402bd73ffb5919cb741cb8e5fbbe2caf9307 /libcpu | |
| parent | aaba8680fb1065d5949b49cc1de38416d533b552 (diff) | |
Use SRAM as EMAC transmit buffer, to avoid the underrun error, especially in the large amount of data communication.
Diffstat (limited to 'libcpu')
| -rw-r--r-- | libcpu/arm/at91sam926x/mmu.c | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/libcpu/arm/at91sam926x/mmu.c b/libcpu/arm/at91sam926x/mmu.c index d2db9d5d73..5b88eee27c 100644 --- a/libcpu/arm/at91sam926x/mmu.c +++ b/libcpu/arm/at91sam926x/mmu.c @@ -471,7 +471,7 @@ void rt_hw_mmu_init(void) mmu_setmtt(0x00000000, 0xFFFFFFFF, 0x00000000, RW_NCNB); /* None cached for 4G memory */ mmu_setmtt(0x20000000, 0x24000000-1, 0x20000000, RW_CB); /* 64M cached SDRAM memory */ mmu_setmtt(0x00000000, 0x100000, 0x20000000, RW_CB); /* isr vector table */ - mmu_setmtt(0x90000000, 0x100000, 0x00000000, RW_CB); /* 4K cached internal memory */ + mmu_setmtt(0x90000000, 0x90400000 - 1, 0x00200000, RW_NCNB); /* 4K SRAM0 + 4k SRAM1 */ mmu_setmtt(0xA0000000, 0xA4000000-1, 0x20000000, RW_NCNB); /* 64M none-cached SDRAM memory */ /* set MMU table address */ |