added bsp/lpc122x & libcpu/arm/lpc122x

git-svn-id: https://rt-thread.googlecode.com/svn/trunk@1234 bbd45198-f89e-11dd-88c7-29a3b14d5316
author: [email protected] <[email protected]> 2011-01-05 06:23:40 +0000
committer: [email protected] <[email protected]> 2011-01-05 06:23:40 +0000
commit: eb5e940df5bfe0869e2b4918e705566a90eeb6ee (patch)
tree: ba158dc89bf41933bb197ec896f8c09f617281ed /libcpu
parent: ba507951956707c8a46b75df06070980551888a8 (diff)
13 files changed, 3220 insertions, 0 deletions
diff --git a/libcpu/arm/lpc122x/CMSIS/LPC122x.h b/libcpu/arm/lpc122x/CMSIS/LPC122x.h
new file mode 100644
index 0000000000..f09dc379e6
--- /dev/null
+++ b/libcpu/arm/lpc122x/CMSIS/LPC122x.h
@@ -0,0 +1,668 @@
+/****************************************************************************
+ *   $Id:: LPC122x.h 5637 2010-11-18 00:02:05Z nxp28433                     $
+ *   Project: NXP LPC122x software example  
+ *
+ *   Description:
+ *     CMSIS Cortex-M0 Core Peripheral Access Layer Header File for 
+ *     NXP LPC122x Device Series 
+ *
+ ****************************************************************************
+ * Software that is described herein is for illustrative purposes only
+ * which provides customers with programming information regarding the
+ * products. This software is supplied "AS IS" without any warranties.
+ * NXP Semiconductors assumes no responsibility or liability for the
+ * use of the software, conveys no license or title under any patent,
+ * copyright, or mask work right to the product. NXP Semiconductors
+ * reserves the right to make changes in the software without
+ * notification. NXP Semiconductors also make no representation or
+ * warranty that such application will be suitable for the specified
+ * use without further testing or modification.
+****************************************************************************/
+#ifndef __LPC122x_H__
+#define __LPC122x_H__
+
+#ifdef __cplusplus
+ extern "C" {
+#endif 
+
+/** @addtogroup LPC122x_Definitions LPC122x Definitions
+  This file defines all structures and symbols for LPC122x:
+    - Registers and bitfields
+    - peripheral base address
+    - peripheral ID
+    - PIO definitions
+  @{
+*/
+
+
+/******************************************************************************/
+/*                Processor and Core Peripherals                              */
+/******************************************************************************/
+/** @addtogroup LPC122x_CMSIS LPC122x CMSIS Definitions
+  Configuration of the Cortex-M0 Processor and Core Peripherals
+  @{
+*/
+
+/*
+ * ==========================================================================
+ * ---------- Interrupt Number Definition -----------------------------------
+ * ==========================================================================
+ */
+
+typedef enum IRQn
+{
+/******  Cortex-M0 Processor Exceptions Numbers ***************************************************/
+  NonMaskableInt_IRQn           = -14,      /*!< 2 Non Maskable Interrupt                         */
+  MemoryManagement_IRQn         = -12,      /*!< 4 Cortex-M0 Memory Management Interrupt          */
+  BusFault_IRQn                 = -11,      /*!< 5 Cortex-M0 Bus Fault Interrupt                  */
+  UsageFault_IRQn               = -10,      /*!< 6 Cortex-M0 Usage Fault Interrupt                */
+  SVCall_IRQn                   = -5,       /*!< 11 Cortex-M0 SV Call Interrupt                   */
+  DebugMonitor_IRQn             = -4,       /*!< 12 Cortex-M0 Debug Monitor Interrupt             */
+  PendSV_IRQn                   = -2,       /*!< 14 Cortex-M0 Pend SV Interrupt                   */
+  SysTick_IRQn                  = -1,       /*!< 15 Cortex-M0 System Tick Interrupt               */
+
+/******  LPC122x Specific Interrupt Numbers *******************************************************/
+  WAKEUP0_IRQn                  = 0,        /*!< The I/O pins can be used as wakeup source.       */
+  WAKEUP1_IRQn                  = 1,
+  WAKEUP2_IRQn                  = 2,
+  WAKEUP3_IRQn                  = 3,
+  WAKEUP4_IRQn                  = 4,   
+  WAKEUP5_IRQn                  = 5,        
+  WAKEUP6_IRQn                  = 6,        
+  WAKEUP7_IRQn                  = 7,        
+  WAKEUP8_IRQn                  = 8,        
+  WAKEUP9_IRQn                  = 9,        
+  WAKEUP10_IRQn                 = 10,       
+  WAKEUP11_IRQn                 = 11,       /*!< 0 through 11 are WAKEUP interrupts               */
+  I2C_IRQn                      = 12,       /*!< I2C Interrupt                                    */
+  TIMER_16_0_IRQn               = 13,       /*!< 16-bit Timer0 Interrupt                          */
+  TIMER_16_1_IRQn               = 14,       /*!< 16-bit Timer1 Interrupt                          */
+  TIMER_32_0_IRQn               = 15,       /*!< 32-bit Timer0 Interrupt                          */
+  TIMER_32_1_IRQn               = 16,       /*!< 32-bit Timer1 Interrupt                          */
+  SSP_IRQn                      = 17,       /*!< SSP Interrupt                                    */
+  UART0_IRQn                    = 18,       /*!< UART0 Interrupt                                  */
+  UART1_IRQn                    = 19,       /*!< UART1 Interrupt                                  */
+  CMP_IRQn                      = 20,       /*!< Comparator Interrupt                             */
+  ADC_IRQn                      = 21,       /*!< A/D Converter Interrupt                          */
+  WDT_IRQn                      = 22,       /*!< Watchdog timer Interrupt                         */  
+  BOD_IRQn                      = 23,       /*!< Brown Out Detect(BOD) Interrupt                  */
+  FLASH_IRQn                    = 24,       /*!< Flash Interrupt                                  */
+  EINT0_IRQn                    = 25,       /*!< External Interrupt 0 Interrupt                   */
+  EINT1_IRQn                    = 26,       /*!< External Interrupt 1 Interrupt                   */
+  EINT2_IRQn                    = 27,       /*!< External Interrupt 2 Interrupt                   */
+  PMU_IRQn                      = 28,       /*!< PMU Interrupt                                    */
+  DMA_IRQn                      = 29,       /*!< DMA Interrupt                                    */
+  RTC_IRQn                      = 30,       /*!< RTC Interrupt                                    */
+  EDM_IRQn                      = 31,       /*!< EDT Interrupt                                    */
+} IRQn_Type;
+
+
+/*
+ * ==========================================================================
+ * ----------- Processor and Core Peripheral Section ------------------------
+ * ==========================================================================
+ */
+
+/* Configuration of the Cortex-M3 Processor and Core Peripherals */
+#define __MPU_PRESENT             1         /*!< MPU present or not                               */
+#define __NVIC_PRIO_BITS          2         /*!< Number of Bits used for Priority Levels          */
+#define __Vendor_SysTickConfig    0         /*!< Set to 1 if different SysTick Config is used     */
+
+/*@}*/ /* end of group LPC122x_CMSIS */
+
+
+#include "core_cm0.h"                       /* Cortex-M0 processor and core peripherals           */
+#include "system_LPC122x.h"                 /* System Header                                      */
+
+
+/******************************************************************************/
+/*                Device Specific Peripheral Registers structures             */
+/******************************************************************************/
+
+#if defined ( __CC_ARM   )
+#pragma anon_unions
+#endif
+
+/*------------- System Control (SYSCON) --------------------------------------*/
+/** @addtogroup LPC122x_SYSCON LPC122x System Control Block 
+  @{
+*/
+typedef struct
+{
+  __IO uint32_t SYSMEMREMAP;     /* Sys mem. Remap, Offset 0x0   */
+  __IO uint32_t PRESETCTRL;
+  __IO uint32_t SYSPLLCTRL;      /* Sys PLL control              */
+  __IO uint32_t SYSPLLSTAT;
+       uint32_t RESERVED0[4];
+
+  __IO uint32_t SYSOSCCTRL;      /* Offset 0x20 */
+  __IO uint32_t WDTOSCCTRL;
+  __IO uint32_t IRCCTRL;
+       uint32_t RESERVED0b;
+  __IO uint32_t SYSRESSTAT;      /* Offset 0x30 */
+       uint32_t RESERVED1[3];
+  __IO uint32_t SYSPLLCLKSEL;    /* Offset 0x40 */	
+  __IO uint32_t SYSPLLCLKUEN;
+       uint32_t RESERVED2[10];
+
+  __IO uint32_t MAINCLKSEL;      /* Offset 0x70 */
+  __IO uint32_t MAINCLKUEN;
+  __IO uint32_t SYSAHBCLKDIV;
+       uint32_t RESERVED3[1];
+
+  __IO uint32_t SYSAHBCLKCTRL;   /* Offset 0x80 */
+       uint32_t RESERVED4[4];
+  __IO uint32_t SSPCLKDIV;                 
+  __IO uint32_t UART0CLKDIV;
+  __IO uint32_t UART1CLKDIV;
+  __IO uint32_t RTCCLKDIV;
+       uint32_t RESERVED5[2];
+  __IO uint32_t TRACECLKDIV;
+
+  __IO uint32_t SYSTICKCLKDIV;   /* Offset 0xB0 */
+  __IO uint32_t I2CCLKDIV;           
+       uint32_t RESERVED6[10];
+
+  __IO uint32_t CLKOUTCLKSEL;    /* Offset 0xE0 */
+  __IO uint32_t CLKOUTUEN;
+  __IO uint32_t CLKOUTDIV;              
+       uint32_t RESERVED7[5];
+  
+  __IO uint32_t PIOPORCAP0;      /* Offset 0x100 */           
+  __IO uint32_t PIOPORCAP1;
+       uint32_t RESERVED8[11];
+  __IO uint32_t FILTERCLKCFG6;
+  __IO uint32_t FILTERCLKCFG5;
+  __IO uint32_t FILTERCLKCFG4;
+  __IO uint32_t FILTERCLKCFG3;   /* Offset 0x140 */
+  __IO uint32_t FILTERCLKCFG2;
+  __IO uint32_t FILTERCLKCFG1;
+  __IO uint32_t FILTERCLKCFG0;	  	  	            
+  __IO uint32_t BODCTRL;         /* Offset 0x150 */
+       uint32_t RESERVED9[1];
+  __IO uint32_t SYSTCKCAL;
+ 	   uint32_t RESERVED10[5];
+  __IO uint32_t INT_IRQ_LATENCY; /* Offset 0x170 */
+  __IO uint32_t INTNMI;
+       uint32_t RESERVED11[34];          
+
+  __IO uint32_t STARTAPRP0;      /* Offset 0x200 */     
+  __IO uint32_t STARTERP0;             
+  __IO uint32_t STARTRSRP0CLR;
+  __IO uint32_t STARTSRP0;
+  __IO uint32_t STARTAPRP1;           
+  __IO uint32_t STARTERP1;             
+  __IO uint32_t STARTRSRP1CLR;
+  __IO uint32_t STARTSRP1;
+       uint32_t RESERVED12[4];
+
+  __IO uint32_t PDSLEEPCFG;      /* Offset 0x230 */
+  __IO uint32_t PDAWAKECFG;              
+  __IO uint32_t PDRUNCFG;
+	   uint32_t RESERVED13;
+  __IO uint32_t EZHBOOT;
+  __IO uint32_t EZHCTRL;
+  __IO uint32_t EZHMUXSEL;
+  __IO uint32_t EZHARM2EZH;
+  __IO uint32_t EZHEZH2ARM;
+  __IO uint32_t EZHEZHPC;
+  __IO uint32_t EZHEZHSP;
+  __IO uint32_t EZHINTERRUPT;
+       uint32_t RESERVED14[101];
+
+  __I  uint32_t DEVICE_ID;
+} LPC_SYSCON_TypeDef;
+
+
+/*------------- Pin Connect Block (IOCON) --------------------------------*/
+/** @addtogroup LPC122x_IOCON LPC122x I/O Configuration Block 
+  @{
+*/
+typedef struct
+{
+  __IO uint32_t PIO2_28;		/* 0x00 */
+  __IO uint32_t PIO2_29;
+  __IO uint32_t PIO0_19;
+  __IO uint32_t PIO0_20;
+  __IO uint32_t PIO0_21;
+  __IO uint32_t PIO0_22;
+  __IO uint32_t PIO0_23;
+  __IO uint32_t PIO0_24;
+
+  __IO uint32_t SWDIO_PIO0_25;	/* 0x20 */
+  __IO uint32_t SWCLK_PIO0_26;
+  __IO uint32_t PIO0_27;
+  __IO uint32_t PIO2_12;
+  __IO uint32_t PIO2_13;
+  __IO uint32_t PIO2_14;
+  __IO uint32_t PIO2_15;
+  __IO uint32_t PIO0_28;
+
+  __IO uint32_t PIO0_29;		/* 0x40 */
+  __IO uint32_t PIO0_0;
+  __IO uint32_t PIO0_1;
+  __IO uint32_t PIO0_2;
+       uint32_t RESERVED0;
+  __IO uint32_t PIO0_3;
+  __IO uint32_t PIO0_4;
+  __IO uint32_t PIO0_5;
+
+  __IO uint32_t PIO0_6;			/* 0x60 */
+  __IO uint32_t PIO0_7;
+  __IO uint32_t PIO0_8;
+  __IO uint32_t PIO0_9;
+  __IO uint32_t PIO2_0;
+  __IO uint32_t PIO2_1;
+  __IO uint32_t PIO2_2;
+  __IO uint32_t PIO2_3;
+
+  __IO uint32_t PIO2_4;			/* 0x80 */
+  __IO uint32_t PIO2_5;
+  __IO uint32_t PIO2_6;
+  __IO uint32_t PIO2_7;
+  __IO uint32_t PIO0_10;
+  __IO uint32_t PIO0_11;
+  __IO uint32_t PIO0_12;
+  __IO uint32_t RESET_P0_13;
+
+  __IO uint32_t PIO0_14;		/* 0xA0 */
+  __IO uint32_t PIO0_15;
+  __IO uint32_t PIO0_16;
+  __IO uint32_t PIO0_17;
+  __IO uint32_t PIO0_18;
+  __IO uint32_t PIO0_30;
+  __IO uint32_t PIO0_31;
+  __IO uint32_t PIO1_0;
+
+  __IO uint32_t PIO1_1;			/* 0xC0 */
+  __IO uint32_t PIO1_2;
+  __IO uint32_t PIO1_3;
+  __IO uint32_t PIO1_4;
+  __IO uint32_t PIO1_5;
+  __IO uint32_t PIO1_6;
+       uint32_t RESERVED1[2];
+
+  __IO uint32_t PIO2_8;				/* 0xE0 */
+  __IO uint32_t PIO2_9;
+  __IO uint32_t PIO2_10;
+  __IO uint32_t PIO2_11;
+#if 0
+  /* LOC registers are no longer needed on LPC122x V1. */
+  __IO uint32_t EZH0_LOC;
+  __IO uint32_t EZH1_LOC;
+  __IO uint32_t CT32B0_0_LOC;
+  __IO uint32_t EZH2_LOC;
+ 
+  __IO uint32_t CT32B0_1_LOC;		/* 0x100 */
+  __IO uint32_t EZH3_LOC;
+  __IO uint32_t CT32B0_2_LOC;
+  __IO uint32_t EZH4_LOC;
+  __IO uint32_t CT32B0_3_LOC;
+  __IO uint32_t EZH5_LOC;
+  __IO uint32_t EZH6_LOC;
+  __IO uint32_t CT32B1_0_LOC;
+
+  __IO uint32_t EZH7_LOC;			/* 0x120 */
+  __IO uint32_t CT32B1_1_LOC;
+  __IO uint32_t EZH8_LOC;
+  __IO uint32_t CT32B1_2_LOC;
+  __IO uint32_t EZH9_LOC;
+  __IO uint32_t CT32B1_3_LOC;
+  __IO uint32_t EZH10_LOC;
+  __IO uint32_t EZH11_LOC;
+
+  __IO uint32_t CT16B0_0_LOC;		/* 0x140 */
+  __IO uint32_t EZH12_LOC;
+  __IO uint32_t CT16B0_1_LOC;
+  __IO uint32_t EZH13_LOC;
+  __IO uint32_t EZH14_LOC;
+  __IO uint32_t EZH15_LOC;
+  __IO uint32_t CT16B1_0_LOC;
+  __IO uint32_t CT16B1_1_LOC;
+#endif
+} LPC_IOCON_TypeDef;
+
+/*------------- microDMA (DMA) --------------------------*/
+/** @addtogroup LPC122x_DMA LPC122x microDMA
+  @{
+*/
+typedef struct
+{
+  __I  uint32_t STATUS;
+  __O  uint32_t CFG;
+  __IO uint32_t CTRL_BASE_PTR;
+  __I  uint32_t ALT_CTRL_BASE_PTR;
+  __I  uint32_t WAITONREQ_STATUS;
+  __O  uint32_t CHNL_SW_REQUEST;
+  __IO uint32_t CHNL_USEBURST_SET;
+  __O  uint32_t CHNL_USEBURST_CLR;
+  __IO uint32_t CHNL_REQ_MASK_SET;
+  __O  uint32_t CHNL_REQ_MASK_CLR;
+  __IO uint32_t CHNL_ENABLE_SET;
+  __O  uint32_t CHNL_ENABLE_CLR;
+  __IO uint32_t CHNL_PRI_ALT_SET;
+  __O  uint32_t CHNL_PRI_ALT_CLR;
+  __IO uint32_t CHNL_PRIORITY_SET;
+  __O  uint32_t CHNL_PRIORITY_CLR;
+	   uint32_t RESERVE0[3];
+  __IO uint32_t ERR_CLR;					/* 0x4C */
+  	   uint32_t RESERVE1[12];
+  __IO uint32_t CHNL_IRQ_STATUS;			/* 0x80 */
+  __IO uint32_t IRQ_ERR_ENABLE;
+  __IO uint32_t CHNL_IRQ_ENABLE;
+} LPC_DMA_TypeDef;
+/*@}*/ /* end of group LPC122x_DMA */
+
+/*------------- Comparator (CMP) --------------------------------*/
+/** @addtogroup LPC122x_CMD LPC122x Comparator
+  @{
+*/
+typedef struct
+{
+  __IO uint32_t CMP;
+  __IO uint32_t VLAD;
+} LPC_COMP_TypeDef;
+/*@}*/ /* end of group LPC122x_CMD */
+
+/*------------- Real Timer Clock (RTC) --------------------------*/
+/** @addtogroup LPC122x_RTC LPC122x Real-time Clock
+  @{
+*/
+typedef struct
+{
+  __I  uint32_t DR;
+  __IO uint32_t MR;
+  __IO uint32_t LR;
+  __IO uint32_t CR;
+  __IO uint32_t IMSC;
+  __I  uint32_t IRS;
+  __I  uint32_t MIS;
+  __IO uint32_t ICR;
+} LPC_RTC_TypeDef;
+/*@}*/ /* end of group LPC122x_RTC */
+
+/*------------- Power Management Unit (PMU) --------------------------*/
+/** @addtogroup LPC122x_PMU LPC122x Power Management Unit
+  @{
+*/
+typedef struct
+{
+  __IO uint32_t PCON;
+  __IO uint32_t GPREG0;
+  __IO uint32_t GPREG1;
+  __IO uint32_t GPREG2;
+  __IO uint32_t GPREG3;
+  __IO uint32_t GPREG4;
+} LPC_PMU_TypeDef;
+/*@}*/ /* end of group LPC122x_PMU */
+
+/*------------- General Purpose Input/Output (GPIO) --------------------------*/
+/** @addtogroup LPC122x_GPIO LPC122x General Purpose Input/Output 
+  @{
+*/
+typedef struct
+{
+  __IO uint32_t MASK;
+  __I  uint32_t PIN;
+  __IO uint32_t OUT;
+  __O  uint32_t SET;
+  __O  uint32_t CLR;
+  __O  uint32_t NOT;
+  	   uint32_t RESERVE[2];
+  __IO uint32_t DIR;
+  __IO uint32_t IS;
+  __IO uint32_t IBE;
+  __IO uint32_t IEV;
+  __IO uint32_t IE;
+  __I  uint32_t RIS;
+  __I  uint32_t MIS;
+  __O  uint32_t IC;
+} LPC_GPIO_TypeDef;
+/*@}*/ /* end of group LPC122x_GPIO */
+
+
+/*------------- Timer (TMR) --------------------------------------------------*/
+/** @addtogroup LPC122x_TMR LPC122x 16/32-bit Counter/Timer 
+  @{
+*/
+typedef struct
+{
+  __IO uint32_t IR;
+  __IO uint32_t TCR;
+  __IO uint32_t TC;
+  __IO uint32_t PR;
+  __IO uint32_t PC;
+  __IO uint32_t MCR;
+  __IO uint32_t MR0;
+  __IO uint32_t MR1;
+  __IO uint32_t MR2;
+  __IO uint32_t MR3;
+  __IO uint32_t CCR;
+  __I  uint32_t CR0;
+  __I  uint32_t CR1;
+  __I  uint32_t CR2;
+  __I  uint32_t CR3;
+  __IO uint32_t EMR;
+       uint32_t RESERVED2[12];
+  __IO uint32_t CTCR;
+  __IO uint32_t PWMC;
+} LPC_TMR_TypeDef;
+/*@}*/ /* end of group LPC122x_TMR */
+
+/*------------- Universal Asynchronous Receiver Transmitter (UART) -----------*/
+/** @addtogroup LPC122x_UART LPC122x Universal Asynchronous Receiver/Transmitter 
+  @{
+*/
+typedef struct
+{
+  union {
+  __I  uint32_t  RBR;
+  __O  uint32_t  THR;
+  __IO uint32_t  DLL;
+  };
+  union {
+  __IO uint32_t  DLM;
+  __IO uint32_t  IER;
+  };
+  union {
+  __I  uint32_t  IIR;
+  __O  uint32_t  FCR;
+  };
+  __IO uint32_t  LCR;
+  __IO uint32_t  MCR;
+  __I  uint32_t  LSR;
+  __I  uint32_t  MSR;
+  __IO uint32_t  SCR;
+  __IO uint32_t  ACR;
+  __IO uint32_t  ICR;
+  __IO uint32_t  FDR;
+       uint32_t  RESERVED0;
+  __IO uint32_t  TER;
+       uint32_t  RESERVED1[6];
+  __IO uint32_t  RS485CTRL;
+  __IO uint32_t  ADRMATCH;
+  __IO uint32_t  RS485DLY;
+  __I  uint32_t  FIFOLVL;
+} LPC_UART_TypeDef;
+/*@}*/ /* end of group LPC122x_UART */
+
+/*------------- Synchronous Serial Communication (SSP) -----------------------*/
+/** @addtogroup LPC122x_SSP LPC122x Synchronous Serial Port 
+  @{
+*/
+typedef struct
+{
+  __IO uint32_t CR0;
+  __IO uint32_t CR1;
+  __IO uint32_t DR;
+  __I  uint32_t SR;
+  __IO uint32_t CPSR;
+  __IO uint32_t IMSC;
+  __IO uint32_t RIS;
+  __IO uint32_t MIS;
+  __IO uint32_t ICR;
+} LPC_SSP_TypeDef;
+/*@}*/ /* end of group LPC122x_SSP */
+
+/*------------- Inter-Integrated Circuit (I2C) -------------------------------*/
+/** @addtogroup LPC122x_I2C LPC122x I2C-Bus Interface 
+  @{
+*/
+typedef struct
+{
+  __IO uint32_t CONSET;
+  __I  uint32_t STAT;
+  __IO uint32_t DAT;
+  __IO uint32_t ADR0;
+  __IO uint32_t SCLH;
+  __IO uint32_t SCLL;
+  __O  uint32_t CONCLR;
+  __IO uint32_t MMCTRL;
+  __IO uint32_t ADR1;
+  __IO uint32_t ADR2;
+  __IO uint32_t ADR3;
+  __I  uint32_t DATA_BUFFER;
+  __IO uint32_t MASK0;
+  __IO uint32_t MASK1;
+  __IO uint32_t MASK2;
+  __IO uint32_t MASK3;
+} LPC_I2C_TypeDef;
+/*@}*/ /* end of group LPC122x_I2C */
+
+/*------------- Watchdog Timer (WDT) -----------------------------------------*/
+/** @addtogroup LPC122x_WDT LPC122x WatchDog Timer 
+  @{
+*/
+typedef struct
+{
+  __IO uint32_t MOD;
+  __IO uint32_t TC;
+  __O  uint32_t FEED;
+  __I  uint32_t TV;
+  __IO uint32_t CLKSEL;
+  __IO uint32_t WARNINT;
+  __IO uint32_t WINDOW;
+} LPC_WDT_TypeDef;
+/*@}*/ /* end of group LPC122x_WDT */
+
+/*------------- Analog-to-Digital Converter (ADC) ----------------------------*/
+/** @addtogroup LPC122x_ADC LPC122x Analog-to-Digital Converter 
+  @{
+*/
+typedef struct
+{
+  __IO uint32_t CR;
+  __IO uint32_t GDR;
+       uint32_t RESERVED0;
+  __IO uint32_t INTEN;
+  __IO uint32_t DR[8];
+  __I  uint32_t STAT;
+} LPC_ADC_TypeDef;
+/*@}*/ /* end of group LPC122x_ADC */
+
+/*------------- Flash Memory Controller (FMC) -----------------------------------*/
+typedef struct
+{
+  __IO uint32_t TBCFG;            /* Time Base Config register  */
+  __IO uint32_t FINSTR;           /* Flash Instruction register */
+  __I  uint32_t INSSTA;           /* Raw Instruction Status register */
+  __IO uint32_t INSSCLR;          /* Raw Instruction Clear register */
+  __IO uint32_t INT_EN;           /* Interrupt Enable register */
+  __I  uint32_t INT_STA;          /* Interrupt Status register */
+       uint32_t RESERVED0;
+  __IO uint32_t ADDRLAT;          /* Address Latch registers */
+  __IO uint32_t DATALAT;          /* Data Latch register */
+  __IO uint32_t FIMC;             /* Flash Manaul Operation register */
+  __IO uint32_t RDCFG;            /* Read Configuration register */
+  __IO uint32_t EPPCFG;           /* Flash Programming Permission Cofig register */
+  __IO uint32_t EPPAA;            /* Flash Programming Permission Address A register */
+  __IO uint32_t EPPAB;            /* Flash Programming Permission Address B register */
+} LPC_FMC_TypeDef;
+
+/*------------- CRC Engine (CRC) -----------------------------------------*/
+typedef struct
+{
+  __IO uint32_t MODE;
+  __IO uint32_t SEED;
+  union {
+  __I  uint32_t SUM;
+  __O  uint32_t WR_DATA_DWORD;
+  __O  uint16_t WR_DATA_WORD;
+       uint16_t RESERVED_WORD;
+  __O  uint8_t WR_DATA_BYTE;
+       uint8_t RESERVED_BYTE[3];
+  };
+  __I  uint32_t ID;
+} LPC_CRC_TypeDef;
+
+#if defined ( __CC_ARM   )
+#pragma no_anon_unions
+#endif
+
+/******************************************************************************/
+/*                         Peripheral memory map                              */
+/******************************************************************************/
+/* Base addresses                                                             */
+#define LPC_FLASH_BASE        (0x00000000)
+#define LPC_RAM_BASE          (0x10000000)
+#define LPC_APB0_BASE         (0x40000000)
+#define LPC_AHB_BASE          (0x50000000)
+
+/* APB0 peripherals                                                          */
+#define LPC_I2C_BASE          (LPC_APB0_BASE + 0x00000)
+#define LPC_WDT_BASE          (LPC_APB0_BASE + 0x04000)
+#define LPC_UART0_BASE        (LPC_APB0_BASE + 0x08000)
+#define LPC_UART1_BASE        (LPC_APB0_BASE + 0x0C000)
+#define LPC_CT16B0_BASE       (LPC_APB0_BASE + 0x10000)
+#define LPC_CT16B1_BASE       (LPC_APB0_BASE + 0x14000)
+#define LPC_CT32B0_BASE       (LPC_APB0_BASE + 0x18000)
+#define LPC_CT32B1_BASE       (LPC_APB0_BASE + 0x1C000)
+#define LPC_ADC_BASE          (LPC_APB0_BASE + 0x20000)
+
+#define LPC_PMU_BASE          (LPC_APB0_BASE + 0x38000)
+#define LPC_SSP_BASE          (LPC_APB0_BASE + 0x40000)
+#define LPC_IOCON_BASE        (LPC_APB0_BASE + 0x44000)
+#define LPC_SYSCON_BASE       (LPC_APB0_BASE + 0x48000)
+#define LPC_DMA_BASE          (LPC_APB0_BASE + 0x4C000)
+#define LPC_RTC_BASE          (LPC_APB0_BASE + 0x50000)
+#define LPC_COMP_BASE         (LPC_APB0_BASE + 0x54000)
+
+/* AHB peripherals */	
+#define LPC_GPIO_BASE         (LPC_AHB_BASE  + 0x00000)
+#define LPC_GPIO0_BASE        (LPC_AHB_BASE  + 0x00000)
+#define LPC_GPIO1_BASE        (LPC_AHB_BASE  + 0x10000)
+#define LPC_GPIO2_BASE        (LPC_AHB_BASE  + 0x20000)
+#define LPC_FMC_BASE          (LPC_AHB_BASE  + 0x60000)
+#define LPC_CRC_BASE          (LPC_AHB_BASE  + 0x70000)
+
+/******************************************************************************/
+/*                         Peripheral declaration                             */
+/******************************************************************************/
+#define LPC_I2C               ((LPC_I2C_TypeDef    *) LPC_I2C_BASE   )
+#define LPC_WDT               ((LPC_WDT_TypeDef    *) LPC_WDT_BASE   )
+#define LPC_UART0             ((LPC_UART_TypeDef   *) LPC_UART0_BASE )
+#define LPC_UART1             ((LPC_UART_TypeDef   *) LPC_UART1_BASE )
+#define LPC_TMR16B0           ((LPC_TMR_TypeDef    *) LPC_CT16B0_BASE)
+#define LPC_TMR16B1           ((LPC_TMR_TypeDef    *) LPC_CT16B1_BASE)
+#define LPC_TMR32B0           ((LPC_TMR_TypeDef    *) LPC_CT32B0_BASE)
+#define LPC_TMR32B1           ((LPC_TMR_TypeDef    *) LPC_CT32B1_BASE)
+#define LPC_ADC               ((LPC_ADC_TypeDef    *) LPC_ADC_BASE   )
+#define LPC_PMU               ((LPC_PMU_TypeDef    *) LPC_PMU_BASE   )
+#define LPC_SSP               ((LPC_SSP_TypeDef    *) LPC_SSP_BASE   )
+#define LPC_IOCON             ((LPC_IOCON_TypeDef  *) LPC_IOCON_BASE )
+#define LPC_SYSCON            ((LPC_SYSCON_TypeDef *) LPC_SYSCON_BASE)
+#define LPC_DMA               ((LPC_DMA_TypeDef    *) LPC_DMA_BASE   )
+#define LPC_RTC               ((LPC_RTC_TypeDef    *) LPC_RTC_BASE   )
+#define LPC_COMP              ((LPC_COMP_TypeDef   *) LPC_COMP_BASE  )
+
+#define LPC_GPIO0             ((LPC_GPIO_TypeDef   *) LPC_GPIO0_BASE )
+#define LPC_GPIO1             ((LPC_GPIO_TypeDef   *) LPC_GPIO1_BASE )
+#define LPC_GPIO2             ((LPC_GPIO_TypeDef   *) LPC_GPIO2_BASE )
+#define LPC_FMC               ((LPC_FMC_TypeDef    *) LPC_FMC_BASE   )
+#define LPC_CRC               ((LPC_CRC_TypeDef    *) LPC_CRC_BASE   )
+
+#ifdef __cplusplus
+ }
+#endif 
+
+#endif  // __LPC122x_H__
diff --git a/libcpu/arm/lpc122x/CMSIS/core_cm0.c b/libcpu/arm/lpc122x/CMSIS/core_cm0.c
new file mode 100644
index 0000000000..c08a7b6c6e
--- /dev/null
+++ b/libcpu/arm/lpc122x/CMSIS/core_cm0.c
@@ -0,0 +1,455 @@
+/**************************************************************************//**
+ * @file     core_cm0.c
+ * @brief    CMSIS Cortex-M0 Core Peripheral Access Layer Source File
+ * @version  V1.30
+ * @date     30. October 2009
+ *
+ * @note
+ * Copyright (C) 2009 ARM Limited. All rights reserved.
+ *
+ * @par
+ * ARM Limited (ARM) is supplying this software for use with Cortex-M 
+ * processor based microcontrollers.  This file can be freely distributed 
+ * within development tools that are supporting such ARM based processors. 
+ *
+ * @par
+ * THIS SOFTWARE IS PROVIDED "AS IS".  NO WARRANTIES, WHETHER EXPRESS, IMPLIED
+ * OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE.
+ * ARM SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR
+ * CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER.
+ *
+ ******************************************************************************/
+
+#include <stdint.h>
+
+/* define compiler specific symbols */
+#if defined ( __CC_ARM   )
+  #define __ASM            __asm                                      /*!< asm keyword for ARM Compiler          */
+  #define __INLINE         __inline                                   /*!< inline keyword for ARM Compiler       */
+
+#elif defined ( __ICCARM__ )
+  #define __ASM           __asm                                       /*!< asm keyword for IAR Compiler          */
+  #define __INLINE        inline                                      /*!< inline keyword for IAR Compiler. Only avaiable in High optimization mode! */
+
+#elif defined   (  __GNUC__  )
+  #define __ASM            __asm                                      /*!< asm keyword for GNU Compiler          */
+  #define __INLINE         inline                                     /*!< inline keyword for GNU Compiler       */
+
+#elif defined   (  __TASKING__  )
+  #define __ASM            __asm                                      /*!< asm keyword for TASKING Compiler      */
+  #define __INLINE         inline                                     /*!< inline keyword for TASKING Compiler   */
+
+#endif
+
+
+/* ###################  Compiler specific Intrinsics  ########################### */
+
+#if defined ( __CC_ARM   ) /*------------------RealView Compiler -----------------*/
+/* ARM armcc specific functions */
+
+/**
+ * @brief  Return the Process Stack Pointer
+ *
+ * @return ProcessStackPointer
+ *
+ * Return the actual process stack pointer
+ */
+__ASM uint32_t __get_PSP(void)
+{
+  mrs r0, psp
+  bx lr
+}
+
+/**
+ * @brief  Set the Process Stack Pointer
+ *
+ * @param  topOfProcStack  Process Stack Pointer
+ *
+ * Assign the value ProcessStackPointer to the MSP 
+ * (process stack pointer) Cortex processor register
+ */
+__ASM void __set_PSP(uint32_t topOfProcStack)
+{
+  msr psp, r0
+  bx lr
+}
+
+/**
+ * @brief  Return the Main Stack Pointer
+ *
+ * @return Main Stack Pointer
+ *
+ * Return the current value of the MSP (main stack pointer)
+ * Cortex processor register
+ */
+__ASM uint32_t __get_MSP(void)
+{
+  mrs r0, msp
+  bx lr
+}
+
+/**
+ * @brief  Set the Main Stack Pointer
+ *
+ * @param  topOfMainStack  Main Stack Pointer
+ *
+ * Assign the value mainStackPointer to the MSP 
+ * (main stack pointer) Cortex processor register
+ */
+__ASM void __set_MSP(uint32_t mainStackPointer)
+{
+  msr msp, r0
+  bx lr
+}
+
+/**
+ * @brief  Reverse byte order in unsigned short value
+ *
+ * @param   value  value to reverse
+ * @return         reversed value
+ *
+ * Reverse byte order in unsigned short value
+ */
+__ASM uint32_t __REV16(uint16_t value)
+{
+  rev16 r0, r0
+  bx lr
+}
+
+/**
+ * @brief  Reverse byte order in signed short value with sign extension to integer
+ *
+ * @param   value  value to reverse
+ * @return         reversed value
+ *
+ * Reverse byte order in signed short value with sign extension to integer
+ */
+__ASM int32_t __REVSH(int16_t value)
+{
+  revsh r0, r0
+  bx lr
+}
+
+
+#if (__ARMCC_VERSION < 400000)
+
+
+/**
+ * @brief  Return the Priority Mask value
+ *
+ * @return PriMask
+ *
+ * Return state of the priority mask bit from the priority mask register
+ */
+__ASM uint32_t __get_PRIMASK(void)
+{
+  mrs r0, primask
+  bx lr
+}
+
+/**
+ * @brief  Set the Priority Mask value
+ *
+ * @param  priMask  PriMask
+ *
+ * Set the priority mask bit in the priority mask register
+ */
+__ASM void __set_PRIMASK(uint32_t priMask)
+{
+  msr primask, r0
+  bx lr
+}
+
+/**
+ * @brief  Return the Control Register value
+ * 
+ * @return Control value
+ *
+ * Return the content of the control register
+ */
+__ASM uint32_t __get_CONTROL(void)
+{
+  mrs r0, control
+  bx lr
+}
+
+/**
+ * @brief  Set the Control Register value
+ *
+ * @param  control  Control value
+ *
+ * Set the control register
+ */
+__ASM void __set_CONTROL(uint32_t control)
+{
+  msr control, r0
+  bx lr
+}
+
+#endif /* __ARMCC_VERSION  */ 
+
+
+
+#elif (defined (__ICCARM__)) /*------------------ ICC Compiler -------------------*/
+/* IAR iccarm specific functions */
+#pragma diag_suppress=Pe940
+
+/**
+ * @brief  Return the Process Stack Pointer
+ *
+ * @return ProcessStackPointer
+ *
+ * Return the actual process stack pointer
+ */
+uint32_t __get_PSP(void)
+{
+  __ASM("mrs r0, psp");
+  __ASM("bx lr");
+}
+
+/**
+ * @brief  Set the Process Stack Pointer
+ *
+ * @param  topOfProcStack  Process Stack Pointer
+ *
+ * Assign the value ProcessStackPointer to the MSP 
+ * (process stack pointer) Cortex processor register
+ */
+void __set_PSP(uint32_t topOfProcStack)
+{
+  __ASM("msr psp, r0");
+  __ASM("bx lr");
+}
+
+/**
+ * @brief  Return the Main Stack Pointer
+ *
+ * @return Main Stack Pointer
+ *
+ * Return the current value of the MSP (main stack pointer)
+ * Cortex processor register
+ */
+uint32_t __get_MSP(void)
+{
+  __ASM("mrs r0, msp");
+  __ASM("bx lr");
+}
+
+/**
+ * @brief  Set the Main Stack Pointer
+ *
+ * @param  topOfMainStack  Main Stack Pointer
+ *
+ * Assign the value mainStackPointer to the MSP 
+ * (main stack pointer) Cortex processor register
+ */
+void __set_MSP(uint32_t topOfMainStack)
+{
+  __ASM("msr msp, r0");
+  __ASM("bx lr");
+}
+
+/**
+ * @brief  Reverse byte order in unsigned short value
+ *
+ * @param  value  value to reverse
+ * @return        reversed value
+ *
+ * Reverse byte order in unsigned short value
+ */
+uint32_t __REV16(uint16_t value)
+{
+  __ASM("rev16 r0, r0");
+  __ASM("bx lr");
+}
+
+
+#pragma diag_default=Pe940
+
+
+#elif (defined (__GNUC__)) /*------------------ GNU Compiler ---------------------*/
+/* GNU gcc specific functions */
+
+/**
+ * @brief  Return the Process Stack Pointer
+ *
+ * @return ProcessStackPointer
+ *
+ * Return the actual process stack pointer
+ */
+uint32_t __get_PSP(void) __attribute__( ( naked ) );
+uint32_t __get_PSP(void)
+{
+  uint32_t result=0;
+
+  __ASM volatile ("MRS %0, psp\n\t" 
+                  "MOV r0, %0 \n\t"
+                  "BX  lr     \n\t"  : "=r" (result) );
+  return(result);
+}
+
+/**
+ * @brief  Set the Process Stack Pointer
+ *
+ * @param  topOfProcStack  Process Stack Pointer
+ *
+ * Assign the value ProcessStackPointer to the MSP 
+ * (process stack pointer) Cortex processor register
+ */
+void __set_PSP(uint32_t topOfProcStack) __attribute__( ( naked ) );
+void __set_PSP(uint32_t topOfProcStack)
+{
+  __ASM volatile ("MSR psp, %0\n\t"
+                  "BX  lr     \n\t" : : "r" (topOfProcStack) );
+}
+
+/**
+ * @brief  Return the Main Stack Pointer
+ *
+ * @return Main Stack Pointer
+ *
+ * Return the current value of the MSP (main stack pointer)
+ * Cortex processor register
+ */
+uint32_t __get_MSP(void) __attribute__( ( naked ) );
+uint32_t __get_MSP(void)
+{
+  uint32_t result=0;
+
+  __ASM volatile ("MRS %0, msp\n\t" 
+                  "MOV r0, %0 \n\t"
+                  "BX  lr     \n\t"  : "=r" (result) );
+  return(result);
+}
+
+/**
+ * @brief  Set the Main Stack Pointer
+ *
+ * @param  topOfMainStack  Main Stack Pointer
+ *
+ * Assign the value mainStackPointer to the MSP 
+ * (main stack pointer) Cortex processor register
+ */
+void __set_MSP(uint32_t topOfMainStack) __attribute__( ( naked ) );
+void __set_MSP(uint32_t topOfMainStack)
+{
+  __ASM volatile ("MSR msp, %0\n\t"
+                  "BX  lr     \n\t" : : "r" (topOfMainStack) );
+}
+
+
+/**
+ * @brief  Return the Priority Mask value
+ *
+ * @return PriMask
+ *
+ * Return state of the priority mask bit from the priority mask register
+ */
+uint32_t __get_PRIMASK(void)
+{
+  uint32_t result=0;
+
+  __ASM volatile ("MRS %0, primask" : "=r" (result) );
+  return(result);
+}
+
+/**
+ * @brief  Set the Priority Mask value
+ *
+ * @param  priMask  PriMask
+ *
+ * Set the priority mask bit in the priority mask register
+ */
+void __set_PRIMASK(uint32_t priMask)
+{
+  __ASM volatile ("MSR primask, %0" : : "r" (priMask) );
+}
+
+/**
+ * @brief  Return the Control Register value
+* 
+*  @return Control value
+ *
+ * Return the content of the control register
+ */
+uint32_t __get_CONTROL(void)
+{
+  uint32_t result=0;
+
+  __ASM volatile ("MRS %0, control" : "=r" (result) );
+  return(result);
+}
+
+/**
+ * @brief  Set the Control Register value
+ *
+ * @param  control  Control value
+ *
+ * Set the control register
+ */
+void __set_CONTROL(uint32_t control)
+{
+  __ASM volatile ("MSR control, %0" : : "r" (control) );
+}
+
+
+/**
+ * @brief  Reverse byte order in integer value
+ *
+ * @param  value  value to reverse
+ * @return        reversed value
+ *
+ * Reverse byte order in integer value
+ */
+uint32_t __REV(uint32_t value)
+{
+  uint32_t result=0;
+  
+  __ASM volatile ("rev %0, %1" : "=r" (result) : "r" (value) );
+  return(result);
+}
+
+/**
+ * @brief  Reverse byte order in unsigned short value
+ *
+ * @param  value  value to reverse
+ * @return        reversed value
+ *
+ * Reverse byte order in unsigned short value
+ */
+uint32_t __REV16(uint16_t value)
+{
+  uint32_t result=0;
+  
+  __ASM volatile ("rev16 %0, %1" : "=r" (result) : "r" (value) );
+  return(result);
+}
+
+/**
+ * @brief  Reverse byte order in signed short value with sign extension to integer
+ *
+ * @param  value  value to reverse
+ * @return        reversed value
+ *
+ * Reverse byte order in signed short value with sign extension to integer
+ */
+int32_t __REVSH(int16_t value)
+{
+  uint32_t result=0;
+  
+  __ASM volatile ("revsh %0, %1" : "=r" (result) : "r" (value) );
+  return(result);
+}
+
+
+#elif (defined (__TASKING__)) /*------------------ TASKING Compiler ---------------------*/
+/* TASKING carm specific functions */
+
+/*
+ * The CMSIS functions have been implemented as intrinsics in the compiler.
+ * Please use "carm -?i" to get an up to date list of all instrinsics,
+ * Including the CMSIS ones.
+ */
+
+#endif
diff --git a/libcpu/arm/lpc122x/CMSIS/core_cm0.h b/libcpu/arm/lpc122x/CMSIS/core_cm0.h
new file mode 100644
index 0000000000..f148b8fad5
--- /dev/null
+++ b/libcpu/arm/lpc122x/CMSIS/core_cm0.h
@@ -0,0 +1,960 @@
+/**************************************************************************//**
+ * @file     core_cm0.h
+ * @brief    CMSIS Cortex-M0 Core Peripheral Access Layer Header File
+ * @version  V1.30
+ * @date     30. October 2009
+ *
+ * @note
+ * Copyright (C) 2009 ARM Limited. All rights reserved.
+ *
+ * @par
+ * ARM Limited (ARM) is supplying this software for use with Cortex-M 
+ * processor based microcontrollers.  This file can be freely distributed 
+ * within development tools that are supporting such ARM based processors. 
+ *
+ * @par
+ * THIS SOFTWARE IS PROVIDED "AS IS".  NO WARRANTIES, WHETHER EXPRESS, IMPLIED
+ * OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE.
+ * ARM SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR
+ * CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER.
+ *
+ ******************************************************************************/
+
+#ifndef __CM0_CORE_H__
+#define __CM0_CORE_H__
+
+/** @addtogroup CMSIS_CM0_core_LintCinfiguration CMSIS CM0 Core Lint Configuration
+ *
+ * List of Lint messages which will be suppressed and not shown:
+ *   - not yet checked
+ * .
+ * Note:  To re-enable a Message, insert a space before 'lint' *
+ *
+ */
+
+
+/** @addtogroup CMSIS_CM0_core_definitions CM0 Core Definitions
+  This file defines all structures and symbols for CMSIS core:
+    - CMSIS version number
+    - Cortex-M core registers and bitfields
+    - Cortex-M core peripheral base address
+  @{
+ */
+
+#ifdef __cplusplus
+ extern "C" {
+#endif 
+
+#define __CM0_CMSIS_VERSION_MAIN  (0x01)                                                       /*!< [31:16] CMSIS HAL main version */
+#define __CM0_CMSIS_VERSION_SUB   (0x30)                                                       /*!< [15:0]  CMSIS HAL sub version  */
+#define __CM0_CMSIS_VERSION       ((__CM0_CMSIS_VERSION_MAIN << 16) | __CM0_CMSIS_VERSION_SUB) /*!< CMSIS HAL version number       */
+
+#define __CORTEX_M                (0x00)                                                       /*!< Cortex core                    */
+
+#include <stdint.h>                           /* Include standard types */
+
+#if defined (__ICCARM__)
+  #include <intrinsics.h>                     /* IAR Intrinsics   */
+#endif
+
+
+#ifndef __NVIC_PRIO_BITS
+  #define __NVIC_PRIO_BITS    2               /*!< standard definition for NVIC Priority Bits */
+#endif
+
+
+
+
+/**
+ * IO definitions
+ *
+ * define access restrictions to peripheral registers
+ */
+
+#ifdef __cplusplus
+  #define     __I     volatile                /*!< defines 'read only' permissions      */
+#else
+  #define     __I     volatile const          /*!< defines 'read only' permissions      */
+#endif
+#define     __O     volatile                  /*!< defines 'write only' permissions     */
+#define     __IO    volatile                  /*!< defines 'read / write' permissions   */
+
+
+
+/*******************************************************************************
+ *                 Register Abstraction
+ ******************************************************************************/
+/** @addtogroup CMSIS_CM0_core_register CMSIS CM0 Core Register
+ @{
+*/
+
+
+/** @addtogroup CMSIS_CM0_NVIC CMSIS CM0 NVIC
+  memory mapped structure for Nested Vectored Interrupt Controller (NVIC)
+  @{
+ */
+typedef struct
+{
+  __IO uint32_t ISER[1];                      /*!< (Offset: 0x000) Interrupt Set Enable Register            */
+       uint32_t RESERVED0[31];
+  __IO uint32_t ICER[1];                      /*!< (Offset: 0x080) Interrupt Clear Enable Register          */
+       uint32_t RSERVED1[31];
+  __IO uint32_t ISPR[1];                      /*!< (Offset: 0x100) Interrupt Set Pending Register           */
+       uint32_t RESERVED2[31];
+  __IO uint32_t ICPR[1];                      /*!< (Offset: 0x180) Interrupt Clear Pending Register         */
+       uint32_t RESERVED3[31];
+       uint32_t RESERVED4[64];
+  __IO uint32_t IPR[8];                       /*!< (Offset: 0x3EC) Interrupt Priority Register              */
+}  NVIC_Type;
+/*@}*/ /* end of group CMSIS_CM0_NVIC */
+
+
+/** @addtogroup CMSIS_CM0_SCB CMSIS CM0 SCB
+  memory mapped structure for System Control Block (SCB)
+  @{
+ */
+typedef struct
+{
+  __I  uint32_t CPUID;                        /*!< Offset: 0x00  CPU ID Base Register                                  */
+  __IO uint32_t ICSR;                         /*!< Offset: 0x04  Interrupt Control State Register                      */
+       uint32_t RESERVED0;                                      
+  __IO uint32_t AIRCR;                        /*!< Offset: 0x0C  Application Interrupt / Reset Control Register        */
+  __IO uint32_t SCR;                          /*!< Offset: 0x10  System Control Register                               */
+  __IO uint32_t CCR;                          /*!< Offset: 0x14  Configuration Control Register                        */
+       uint32_t RESERVED1;                                      
+  __IO uint32_t SHP[2];                       /*!< Offset: 0x1C  System Handlers Priority Registers. [0] is RESERVED   */
+  __IO uint32_t SHCSR;                        /*!< Offset: 0x24  System Handler Control and State Register             */
+       uint32_t RESERVED2[2];                                   
+  __IO uint32_t DFSR;                         /*!< Offset: 0x30  Debug Fault Status Register                           */
+} SCB_Type;                                                
+
+/* SCB CPUID Register Definitions */
+#define SCB_CPUID_IMPLEMENTER_Pos          24                                             /*!< SCB CPUID: IMPLEMENTER Position */
+#define SCB_CPUID_IMPLEMENTER_Msk          (0xFFul << SCB_CPUID_IMPLEMENTER_Pos)          /*!< SCB CPUID: IMPLEMENTER Mask */
+
+#define SCB_CPUID_VARIANT_Pos              20                                             /*!< SCB CPUID: VARIANT Position */
+#define SCB_CPUID_VARIANT_Msk              (0xFul << SCB_CPUID_VARIANT_Pos)               /*!< SCB CPUID: VARIANT Mask */
+
+#define SCB_CPUID_ARCHITECTURE_Pos         16                                             /*!< SCB CPUID: ARCHITECTURE Position */
+#define SCB_CPUID_ARCHITECTURE_Msk         (0xFul << SCB_CPUID_ARCHITECTURE_Pos)          /*!< SCB CPUID: ARCHITECTURE Mask */
+
+#define SCB_CPUID_PARTNO_Pos                4                                             /*!< SCB CPUID: PARTNO Position */
+#define SCB_CPUID_PARTNO_Msk               (0xFFFul << SCB_CPUID_PARTNO_Pos)              /*!< SCB CPUID: PARTNO Mask */
+
+#define SCB_CPUID_REVISION_Pos              0                                             /*!< SCB CPUID: REVISION Position */
+#define SCB_CPUID_REVISION_Msk             (0xFul << SCB_CPUID_REVISION_Pos)              /*!< SCB CPUID: REVISION Mask */
+
+/* SCB Interrupt Control State Register Definitions */
+#define SCB_ICSR_NMIPENDSET_Pos            31                                             /*!< SCB ICSR: NMIPENDSET Position */
+#define SCB_ICSR_NMIPENDSET_Msk            (1ul << SCB_ICSR_NMIPENDSET_Pos)               /*!< SCB ICSR: NMIPENDSET Mask */
+
+#define SCB_ICSR_PENDSVSET_Pos             28                                             /*!< SCB ICSR: PENDSVSET Position */
+#define SCB_ICSR_PENDSVSET_Msk             (1ul << SCB_ICSR_PENDSVSET_Pos)                /*!< SCB ICSR: PENDSVSET Mask */
+
+#define SCB_ICSR_PENDSVCLR_Pos             27                                             /*!< SCB ICSR: PENDSVCLR Position */
+#define SCB_ICSR_PENDSVCLR_Msk             (1ul << SCB_ICSR_PENDSVCLR_Pos)                /*!< SCB ICSR: PENDSVCLR Mask */
+
+#define SCB_ICSR_PENDSTSET_Pos             26                                             /*!< SCB ICSR: PENDSTSET Position */
+#define SCB_ICSR_PENDSTSET_Msk             (1ul << SCB_ICSR_PENDSTSET_Pos)                /*!< SCB ICSR: PENDSTSET Mask */
+
+#define SCB_ICSR_PENDSTCLR_Pos             25                                             /*!< SCB ICSR: PENDSTCLR Position */
+#define SCB_ICSR_PENDSTCLR_Msk             (1ul << SCB_ICSR_PENDSTCLR_Pos)                /*!< SCB ICSR: PENDSTCLR Mask */
+
+#define SCB_ICSR_ISRPREEMPT_Pos            23                                             /*!< SCB ICSR: ISRPREEMPT Position */
+#define SCB_ICSR_ISRPREEMPT_Msk            (1ul << SCB_ICSR_ISRPREEMPT_Pos)               /*!< SCB ICSR: ISRPREEMPT Mask */
+
+#define SCB_ICSR_ISRPENDING_Pos            22                                             /*!< SCB ICSR: ISRPENDING Position */
+#define SCB_ICSR_ISRPENDING_Msk            (1ul << SCB_ICSR_ISRPENDING_Pos)               /*!< SCB ICSR: ISRPENDING Mask */
+
+#define SCB_ICSR_VECTPENDING_Pos           12                                             /*!< SCB ICSR: VECTPENDING Position */
+#define SCB_ICSR_VECTPENDING_Msk           (0x1FFul << SCB_ICSR_VECTPENDING_Pos)          /*!< SCB ICSR: VECTPENDING Mask */
+
+#define SCB_ICSR_VECTACTIVE_Pos             0                                             /*!< SCB ICSR: VECTACTIVE Position */
+#define SCB_ICSR_VECTACTIVE_Msk            (0x1FFul << SCB_ICSR_VECTACTIVE_Pos)           /*!< SCB ICSR: VECTACTIVE Mask */
+
+/* SCB Application Interrupt and Reset Control Register Definitions */
+#define SCB_AIRCR_VECTKEY_Pos              16                                             /*!< SCB AIRCR: VECTKEY Position */
+#define SCB_AIRCR_VECTKEY_Msk              (0xFFFFul << SCB_AIRCR_VECTKEY_Pos)            /*!< SCB AIRCR: VECTKEY Mask */
+
+#define SCB_AIRCR_VECTKEYSTAT_Pos          16                                             /*!< SCB AIRCR: VECTKEYSTAT Position */
+#define SCB_AIRCR_VECTKEYSTAT_Msk          (0xFFFFul << SCB_AIRCR_VECTKEYSTAT_Pos)        /*!< SCB AIRCR: VECTKEYSTAT Mask */
+
+#define SCB_AIRCR_ENDIANESS_Pos            15                                             /*!< SCB AIRCR: ENDIANESS Position */
+#define SCB_AIRCR_ENDIANESS_Msk            (1ul << SCB_AIRCR_ENDIANESS_Pos)               /*!< SCB AIRCR: ENDIANESS Mask */
+
+#define SCB_AIRCR_SYSRESETREQ_Pos           2                                             /*!< SCB AIRCR: SYSRESETREQ Position */
+#define SCB_AIRCR_SYSRESETREQ_Msk          (1ul << SCB_AIRCR_SYSRESETREQ_Pos)             /*!< SCB AIRCR: SYSRESETREQ Mask */
+
+#define SCB_AIRCR_VECTCLRACTIVE_Pos         1                                             /*!< SCB AIRCR: VECTCLRACTIVE Position */
+#define SCB_AIRCR_VECTCLRACTIVE_Msk        (1ul << SCB_AIRCR_VECTCLRACTIVE_Pos)           /*!< SCB AIRCR: VECTCLRACTIVE Mask */
+
+/* SCB System Control Register Definitions */
+#define SCB_SCR_SEVONPEND_Pos               4                                             /*!< SCB SCR: SEVONPEND Position */
+#define SCB_SCR_SEVONPEND_Msk              (1ul << SCB_SCR_SEVONPEND_Pos)                 /*!< SCB SCR: SEVONPEND Mask */
+
+#define SCB_SCR_SLEEPDEEP_Pos               2                                             /*!< SCB SCR: SLEEPDEEP Position */
+#define SCB_SCR_SLEEPDEEP_Msk              (1ul << SCB_SCR_SLEEPDEEP_Pos)                 /*!< SCB SCR: SLEEPDEEP Mask */
+
+#define SCB_SCR_SLEEPONEXIT_Pos             1                                             /*!< SCB SCR: SLEEPONEXIT Position */
+#define SCB_SCR_SLEEPONEXIT_Msk            (1ul << SCB_SCR_SLEEPONEXIT_Pos)               /*!< SCB SCR: SLEEPONEXIT Mask */
+
+/* SCB Configuration Control Register Definitions */
+#define SCB_CCR_STKALIGN_Pos                9                                             /*!< SCB CCR: STKALIGN Position */
+#define SCB_CCR_STKALIGN_Msk               (1ul << SCB_CCR_STKALIGN_Pos)                  /*!< SCB CCR: STKALIGN Mask */
+
+#define SCB_CCR_UNALIGN_TRP_Pos             3                                             /*!< SCB CCR: UNALIGN_TRP Position */
+#define SCB_CCR_UNALIGN_TRP_Msk            (1ul << SCB_CCR_UNALIGN_TRP_Pos)               /*!< SCB CCR: UNALIGN_TRP Mask */
+
+/* SCB System Handler Control and State Register Definitions */
+#define SCB_SHCSR_SVCALLPENDED_Pos         15                                             /*!< SCB SHCSR: SVCALLPENDED Position */
+#define SCB_SHCSR_SVCALLPENDED_Msk         (1ul << SCB_SHCSR_SVCALLPENDED_Pos)            /*!< SCB SHCSR: SVCALLPENDED Mask */
+
+/* SCB Debug Fault Status Register Definitions */
+#define SCB_DFSR_EXTERNAL_Pos               4                                             /*!< SCB DFSR: EXTERNAL Position */
+#define SCB_DFSR_EXTERNAL_Msk              (1ul << SCB_DFSR_EXTERNAL_Pos)                 /*!< SCB DFSR: EXTERNAL Mask */
+
+#define SCB_DFSR_VCATCH_Pos                 3                                             /*!< SCB DFSR: VCATCH Position */
+#define SCB_DFSR_VCATCH_Msk                (1ul << SCB_DFSR_VCATCH_Pos)                   /*!< SCB DFSR: VCATCH Mask */
+
+#define SCB_DFSR_DWTTRAP_Pos                2                                             /*!< SCB DFSR: DWTTRAP Position */
+#define SCB_DFSR_DWTTRAP_Msk               (1ul << SCB_DFSR_DWTTRAP_Pos)                  /*!< SCB DFSR: DWTTRAP Mask */
+
+#define SCB_DFSR_BKPT_Pos                   1                                             /*!< SCB DFSR: BKPT Position */
+#define SCB_DFSR_BKPT_Msk                  (1ul << SCB_DFSR_BKPT_Pos)                     /*!< SCB DFSR: BKPT Mask */
+
+#define SCB_DFSR_HALTED_Pos                 0                                             /*!< SCB DFSR: HALTED Position */
+#define SCB_DFSR_HALTED_Msk                (1ul << SCB_DFSR_HALTED_Pos)                   /*!< SCB DFSR: HALTED Mask */
+/*@}*/ /* end of group CMSIS_CM0_SCB */
+
+
+/** @addtogroup CMSIS_CM0_SysTick CMSIS CM0 SysTick
+  memory mapped structure for SysTick
+  @{
+ */
+typedef struct
+{
+  __IO uint32_t CTRL;                         /*!< Offset: 0x00  SysTick Control and Status Register */
+  __IO uint32_t LOAD;                         /*!< Offset: 0x04  SysTick Reload Value Register       */
+  __IO uint32_t VAL;                          /*!< Offset: 0x08  SysTick Current Value Register      */
+  __I  uint32_t CALIB;                        /*!< Offset: 0x0C  SysTick Calibration Register        */
+} SysTick_Type;
+
+/* SysTick Control / Status Register Definitions */
+#define SysTick_CTRL_COUNTFLAG_Pos         16                                             /*!< SysTick CTRL: COUNTFLAG Position */
+#define SysTick_CTRL_COUNTFLAG_Msk         (1ul << SysTick_CTRL_COUNTFLAG_Pos)            /*!< SysTick CTRL: COUNTFLAG Mask */
+
+#define SysTick_CTRL_CLKSOURCE_Pos          2                                             /*!< SysTick CTRL: CLKSOURCE Position */
+#define SysTick_CTRL_CLKSOURCE_Msk         (1ul << SysTick_CTRL_CLKSOURCE_Pos)            /*!< SysTick CTRL: CLKSOURCE Mask */
+
+#define SysTick_CTRL_TICKINT_Pos            1                                             /*!< SysTick CTRL: TICKINT Position */
+#define SysTick_CTRL_TICKINT_Msk           (1ul << SysTick_CTRL_TICKINT_Pos)              /*!< SysTick CTRL: TICKINT Mask */
+
+#define SysTick_CTRL_ENABLE_Pos             0                                             /*!< SysTick CTRL: ENABLE Position */
+#define SysTick_CTRL_ENABLE_Msk            (1ul << SysTick_CTRL_ENABLE_Pos)               /*!< SysTick CTRL: ENABLE Mask */
+
+/* SysTick Reload Register Definitions */
+#define SysTick_LOAD_RELOAD_Pos             0                                             /*!< SysTick LOAD: RELOAD Position */
+#define SysTick_LOAD_RELOAD_Msk            (0xFFFFFFul << SysTick_LOAD_RELOAD_Pos)        /*!< SysTick LOAD: RELOAD Mask */
+
+/* SysTick Current Register Definitions */
+#define SysTick_VAL_CURRENT_Pos             0                                             /*!< SysTick VAL: CURRENT Position */
+#define SysTick_VAL_CURRENT_Msk            (0xFFFFFFul << SysTick_VAL_CURRENT_Pos)        /*!< SysTick VAL: CURRENT Mask */
+
+/* SysTick Calibration Register Definitions */
+#define SysTick_CALIB_NOREF_Pos            31                                             /*!< SysTick CALIB: NOREF Position */
+#define SysTick_CALIB_NOREF_Msk            (1ul << SysTick_CALIB_NOREF_Pos)               /*!< SysTick CALIB: NOREF Mask */
+
+#define SysTick_CALIB_SKEW_Pos             30                                             /*!< SysTick CALIB: SKEW Position */
+#define SysTick_CALIB_SKEW_Msk             (1ul << SysTick_CALIB_SKEW_Pos)                /*!< SysTick CALIB: SKEW Mask */
+
+#define SysTick_CALIB_TENMS_Pos             0                                             /*!< SysTick CALIB: TENMS Position */
+#define SysTick_CALIB_TENMS_Msk            (0xFFFFFFul << SysTick_VAL_CURRENT_Pos)        /*!< SysTick CALIB: TENMS Mask */
+/*@}*/ /* end of group CMSIS_CM0_SysTick */
+
+
+/** @addtogroup CMSIS_CM0_CoreDebug CMSIS CM0 Core Debug
+  memory mapped structure for Core Debug Register
+  @{
+ */
+typedef struct
+{
+  __IO uint32_t DHCSR;                        /*!< Offset: 0x00  Debug Halting Control and Status Register    */
+  __O  uint32_t DCRSR;                        /*!< Offset: 0x04  Debug Core Register Selector Register        */
+  __IO uint32_t DCRDR;                        /*!< Offset: 0x08  Debug Core Register Data Register            */
+  __IO uint32_t DEMCR;                        /*!< Offset: 0x0C  Debug Exception and Monitor Control Register */
+} CoreDebug_Type;
+
+/* Debug Halting Control and Status Register */
+#define CoreDebug_DHCSR_DBGKEY_Pos         16                                             /*!< CoreDebug DHCSR: DBGKEY Position */
+#define CoreDebug_DHCSR_DBGKEY_Msk         (0xFFFFul << CoreDebug_DHCSR_DBGKEY_Pos)       /*!< CoreDebug DHCSR: DBGKEY Mask */
+
+#define CoreDebug_DHCSR_S_RESET_ST_Pos     25                                             /*!< CoreDebug DHCSR: S_RESET_ST Position */
+#define CoreDebug_DHCSR_S_RESET_ST_Msk     (1ul << CoreDebug_DHCSR_S_RESET_ST_Pos)        /*!< CoreDebug DHCSR: S_RESET_ST Mask */
+
+#define CoreDebug_DHCSR_S_RETIRE_ST_Pos    24                                             /*!< CoreDebug DHCSR: S_RETIRE_ST Position */
+#define CoreDebug_DHCSR_S_RETIRE_ST_Msk    (1ul << CoreDebug_DHCSR_S_RETIRE_ST_Pos)       /*!< CoreDebug DHCSR: S_RETIRE_ST Mask */
+
+#define CoreDebug_DHCSR_S_LOCKUP_Pos       19                                             /*!< CoreDebug DHCSR: S_LOCKUP Position */
+#define CoreDebug_DHCSR_S_LOCKUP_Msk       (1ul << CoreDebug_DHCSR_S_LOCKUP_Pos)          /*!< CoreDebug DHCSR: S_LOCKUP Mask */
+
+#define CoreDebug_DHCSR_S_SLEEP_Pos        18                                             /*!< CoreDebug DHCSR: S_SLEEP Position */
+#define CoreDebug_DHCSR_S_SLEEP_Msk        (1ul << CoreDebug_DHCSR_S_SLEEP_Pos)           /*!< CoreDebug DHCSR: S_SLEEP Mask */
+
+#define CoreDebug_DHCSR_S_HALT_Pos         17                                             /*!< CoreDebug DHCSR: S_HALT Position */
+#define CoreDebug_DHCSR_S_HALT_Msk         (1ul << CoreDebug_DHCSR_S_HALT_Pos)            /*!< CoreDebug DHCSR: S_HALT Mask */
+
+#define CoreDebug_DHCSR_S_REGRDY_Pos       16                                             /*!< CoreDebug DHCSR: S_REGRDY Position */
+#define CoreDebug_DHCSR_S_REGRDY_Msk       (1ul << CoreDebug_DHCSR_S_REGRDY_Pos)          /*!< CoreDebug DHCSR: S_REGRDY Mask */
+
+#define CoreDebug_DHCSR_C_MASKINTS_Pos      3                                             /*!< CoreDebug DHCSR: C_MASKINTS Position */
+#define CoreDebug_DHCSR_C_MASKINTS_Msk     (1ul << CoreDebug_DHCSR_C_MASKINTS_Pos)        /*!< CoreDebug DHCSR: C_MASKINTS Mask */
+
+#define CoreDebug_DHCSR_C_STEP_Pos          2                                             /*!< CoreDebug DHCSR: C_STEP Position */
+#define CoreDebug_DHCSR_C_STEP_Msk         (1ul << CoreDebug_DHCSR_C_STEP_Pos)            /*!< CoreDebug DHCSR: C_STEP Mask */
+
+#define CoreDebug_DHCSR_C_HALT_Pos          1                                             /*!< CoreDebug DHCSR: C_HALT Position */
+#define CoreDebug_DHCSR_C_HALT_Msk         (1ul << CoreDebug_DHCSR_C_HALT_Pos)            /*!< CoreDebug DHCSR: C_HALT Mask */
+
+#define CoreDebug_DHCSR_C_DEBUGEN_Pos       0                                             /*!< CoreDebug DHCSR: C_DEBUGEN Position */
+#define CoreDebug_DHCSR_C_DEBUGEN_Msk      (1ul << CoreDebug_DHCSR_C_DEBUGEN_Pos)         /*!< CoreDebug DHCSR: C_DEBUGEN Mask */
+
+/* Debug Core Register Selector Register */
+#define CoreDebug_DCRSR_REGWnR_Pos         16                                             /*!< CoreDebug DCRSR: REGWnR Position */
+#define CoreDebug_DCRSR_REGWnR_Msk         (1ul << CoreDebug_DCRSR_REGWnR_Pos)            /*!< CoreDebug DCRSR: REGWnR Mask */
+
+#define CoreDebug_DCRSR_REGSEL_Pos          0                                             /*!< CoreDebug DCRSR: REGSEL Position */
+#define CoreDebug_DCRSR_REGSEL_Msk         (0x1Ful << CoreDebug_DCRSR_REGSEL_Pos)         /*!< CoreDebug DCRSR: REGSEL Mask */
+
+/* Debug Exception and Monitor Control Register */
+#define CoreDebug_DEMCR_DWTENA_Pos         24                                             /*!< CoreDebug DEMCR: DWTENA Position */
+#define CoreDebug_DEMCR_DWTENA_Msk         (1ul << CoreDebug_DEMCR_DWTENA_Pos)            /*!< CoreDebug DEMCR: DWTENA Mask */
+
+#define CoreDebug_DEMCR_VC_HARDERR_Pos     10                                             /*!< CoreDebug DEMCR: VC_HARDERR Position */
+#define CoreDebug_DEMCR_VC_HARDERR_Msk     (1ul << CoreDebug_DEMCR_VC_HARDERR_Pos)        /*!< CoreDebug DEMCR: VC_HARDERR Mask */
+
+#define CoreDebug_DEMCR_VC_CORERESET_Pos    0                                             /*!< CoreDebug DEMCR: VC_CORERESET Position */
+#define CoreDebug_DEMCR_VC_CORERESET_Msk   (1ul << CoreDebug_DEMCR_VC_CORERESET_Pos)      /*!< CoreDebug DEMCR: VC_CORERESET Mask */
+/*@}*/ /* end of group CMSIS_CM0_CoreDebug */
+
+
+/* Memory mapping of Cortex-M0 Hardware */
+#define SCS_BASE            (0xE000E000)                              /*!< System Control Space Base Address */
+#define CoreDebug_BASE      (0xE000EDF0)                              /*!< Core Debug Base Address           */
+#define SysTick_BASE        (SCS_BASE +  0x0010)                      /*!< SysTick Base Address              */
+#define NVIC_BASE           (SCS_BASE +  0x0100)                      /*!< NVIC Base Address                 */
+#define SCB_BASE            (SCS_BASE +  0x0D00)                      /*!< System Control Block Base Address */
+
+#define SCB                 ((SCB_Type *)           SCB_BASE)         /*!< SCB configuration struct          */
+#define SysTick             ((SysTick_Type *)       SysTick_BASE)     /*!< SysTick configuration struct      */
+#define NVIC                ((NVIC_Type *)          NVIC_BASE)        /*!< NVIC configuration struct         */
+#define CoreDebug           ((CoreDebug_Type *)     CoreDebug_BASE)   /*!< Core Debug configuration struct   */
+
+/*@}*/ /* end of group CMSIS_CM0_core_register */
+
+
+/*******************************************************************************
+ *                Hardware Abstraction Layer
+ ******************************************************************************/
+
+#if defined ( __CC_ARM   )
+  #define __ASM            __asm                                      /*!< asm keyword for ARM Compiler          */
+  #define __INLINE         __inline                                   /*!< inline keyword for ARM Compiler       */
+
+#elif defined ( __ICCARM__ )
+  #define __ASM           __asm                                       /*!< asm keyword for IAR Compiler          */
+  #define __INLINE        inline                                      /*!< inline keyword for IAR Compiler. Only avaiable in High optimization mode! */
+
+#elif defined   (  __GNUC__  )
+  #define __ASM            __asm                                      /*!< asm keyword for GNU Compiler          */
+  #define __INLINE         inline                                     /*!< inline keyword for GNU Compiler       */
+
+#elif defined   (  __TASKING__  )
+  #define __ASM            __asm                                      /*!< asm keyword for TASKING Compiler      */
+  #define __INLINE         inline                                     /*!< inline keyword for TASKING Compiler   */
+
+#endif
+
+
+/* ###################  Compiler specific Intrinsics  ########################### */
+
+#if defined ( __CC_ARM   ) /*------------------RealView Compiler -----------------*/
+/* ARM armcc specific functions */
+
+#define __enable_fault_irq                __enable_fiq
+#define __disable_fault_irq               __disable_fiq
+
+#define __NOP                             __nop
+#define __WFI                             __wfi
+#define __WFE                             __wfe
+#define __SEV                             __sev
+#define __ISB()                           __isb(0)
+#define __DSB()                           __dsb(0)
+#define __DMB()                           __dmb(0)
+#define __REV                             __rev
+
+
+/* intrinsic void __enable_irq();     */
+/* intrinsic void __disable_irq();    */
+
+
+/**
+ * @brief  Return the Process Stack Pointer
+ *
+ * @return ProcessStackPointer
+ *
+ * Return the actual process stack pointer
+ */
+extern uint32_t __get_PSP(void);
+
+/**
+ * @brief  Set the Process Stack Pointer
+ *
+ * @param  topOfProcStack  Process Stack Pointer
+ *
+ * Assign the value ProcessStackPointer to the MSP 
+ * (process stack pointer) Cortex processor register
+ */
+extern void __set_PSP(uint32_t topOfProcStack);
+
+/**
+ * @brief  Return the Main Stack Pointer
+ *
+ * @return Main Stack Pointer
+ *
+ * Return the current value of the MSP (main stack pointer)
+ * Cortex processor register
+ */
+extern uint32_t __get_MSP(void);
+
+/**
+ * @brief  Set the Main Stack Pointer
+ *
+ * @param  topOfMainStack  Main Stack Pointer
+ *
+ * Assign the value mainStackPointer to the MSP 
+ * (main stack pointer) Cortex processor register
+ */
+extern void __set_MSP(uint32_t topOfMainStack);
+
+/**
+ * @brief  Reverse byte order in unsigned short value
+ *
+ * @param   value  value to reverse
+ * @return         reversed value
+ *
+ * Reverse byte order in unsigned short value
+ */
+extern uint32_t __REV16(uint16_t value);
+
+/**
+ * @brief  Reverse byte order in signed short value with sign extension to integer
+ *
+ * @param   value  value to reverse
+ * @return         reversed value
+ *
+ * Reverse byte order in signed short value with sign extension to integer
+ */
+extern int32_t __REVSH(int16_t value);
+
+
+#if (__ARMCC_VERSION < 400000)
+
+/**
+ * @brief  Return the Priority Mask value
+ *
+ * @return PriMask
+ *
+ * Return state of the priority mask bit from the priority mask register
+ */
+extern uint32_t __get_PRIMASK(void);
+
+/**
+ * @brief  Set the Priority Mask value
+ *
+ * @param   priMask  PriMask
+ *
+ * Set the priority mask bit in the priority mask register
+ */
+extern void __set_PRIMASK(uint32_t priMask);
+
+/**
+ * @brief  Return the Control Register value
+ * 
+ * @return Control value
+ *
+ * Return the content of the control register
+ */
+extern uint32_t __get_CONTROL(void);
+
+/**
+ * @brief  Set the Control Register value
+ *
+ * @param  control  Control value
+ *
+ * Set the control register
+ */
+extern void __set_CONTROL(uint32_t control);
+
+#else  /* (__ARMCC_VERSION >= 400000)  */
+
+
+/**
+ * @brief  Return the Priority Mask value
+ *
+ * @return PriMask
+ *
+ * Return state of the priority mask bit from the priority mask register
+ */
+static __INLINE uint32_t __get_PRIMASK(void)
+{
+  register uint32_t __regPriMask         __ASM("primask");
+  return(__regPriMask);
+}
+
+/**
+ * @brief  Set the Priority Mask value
+ *
+ * @param  priMask  PriMask
+ *
+ * Set the priority mask bit in the priority mask register
+ */
+static __INLINE void __set_PRIMASK(uint32_t priMask)
+{
+  register uint32_t __regPriMask         __ASM("primask");
+  __regPriMask = (priMask);
+}
+
+/**
+ * @brief  Return the Control Register value
+ * 
+ * @return Control value
+ *
+ * Return the content of the control register
+ */
+static __INLINE uint32_t __get_CONTROL(void)
+{
+  register uint32_t __regControl         __ASM("control");
+  return(__regControl);
+}
+
+/**
+ * @brief  Set the Control Register value
+ *
+ * @param  control  Control value
+ *
+ * Set the control register
+ */
+static __INLINE void __set_CONTROL(uint32_t control)
+{
+  register uint32_t __regControl         __ASM("control");
+  __regControl = control;
+}
+
+#endif /* __ARMCC_VERSION  */ 
+
+
+
+#elif (defined (__ICCARM__)) /*------------------ ICC Compiler -------------------*/
+/* IAR iccarm specific functions */
+
+#define __enable_irq                              __enable_interrupt        /*!< global Interrupt enable */
+#define __disable_irq                             __disable_interrupt       /*!< global Interrupt disable */
+
+static __INLINE void __enable_fault_irq()         { __ASM ("cpsie f"); }
+static __INLINE void __disable_fault_irq()        { __ASM ("cpsid f"); }
+
+#define __NOP                                     __no_operation            /*!< no operation intrinsic in IAR Compiler */ 
+static __INLINE  void __WFI()                     { __ASM ("wfi"); }
+static __INLINE  void __WFE()                     { __ASM ("wfe"); }
+static __INLINE  void __SEV()                     { __ASM ("sev"); }
+
+/* intrinsic void __ISB(void)                                     */
+/* intrinsic void __DSB(void)                                     */
+/* intrinsic void __DMB(void)                                     */
+/* intrinsic void __set_PRIMASK();                                */
+/* intrinsic void __get_PRIMASK();                                */
+
+
+/* intrinsic uint32_t __REV(uint32_t value);                      */
+/* intrinsic uint32_t __REVSH(uint32_t value);                    */
+
+
+/**
+ * @brief  Return the Process Stack Pointer
+ *
+ * @return ProcessStackPointer
+ *
+ * Return the actual process stack pointer
+ */
+extern uint32_t __get_PSP(void);
+
+/**
+ * @brief  Set the Process Stack Pointer
+ *
+ * @param  topOfProcStack  Process Stack Pointer
+ *
+ * Assign the value ProcessStackPointer to the MSP 
+ * (process stack pointer) Cortex processor register
+ */
+extern void __set_PSP(uint32_t topOfProcStack);
+
+/**
+ * @brief  Return the Main Stack Pointer
+ *
+ * @return Main Stack Pointer
+ *
+ * Return the current value of the MSP (main stack pointer)
+ * Cortex processor register
+ */
+extern uint32_t __get_MSP(void);
+
+/**
+ * @brief  Set the Main Stack Pointer
+ *
+ * @param  topOfMainStack  Main Stack Pointer
+ *
+ * Assign the value mainStackPointer to the MSP 
+ * (main stack pointer) Cortex processor register
+ */
+extern void __set_MSP(uint32_t topOfMainStack);
+
+/**
+ * @brief  Reverse byte order in unsigned short value
+ *
+ * @param  value  value to reverse
+ * @return        reversed value
+ *
+ * Reverse byte order in unsigned short value
+ */
+extern uint32_t __REV16(uint16_t value);
+
+
+
+
+
+#elif (defined (__GNUC__)) /*------------------ GNU Compiler ---------------------*/
+/* GNU gcc specific functions */
+
+static __INLINE void __enable_irq()               { __ASM volatile ("cpsie i"); }
+static __INLINE void __disable_irq()              { __ASM volatile ("cpsid i"); }
+
+static __INLINE void __enable_fault_irq()         { __ASM volatile ("cpsie f"); }
+static __INLINE void __disable_fault_irq()        { __ASM volatile ("cpsid f"); }
+
+static __INLINE void __NOP()                      { __ASM volatile ("nop"); }
+static __INLINE void __WFI()                      { __ASM volatile ("wfi"); }
+static __INLINE void __WFE()                      { __ASM volatile ("wfe"); }
+static __INLINE void __SEV()                      { __ASM volatile ("sev"); }
+static __INLINE void __ISB()                      { __ASM volatile ("isb"); }
+static __INLINE void __DSB()                      { __ASM volatile ("dsb"); }
+static __INLINE void __DMB()                      { __ASM volatile ("dmb"); }
+
+
+/**
+ * @brief  Return the Process Stack Pointer
+ *
+ * @return ProcessStackPointer
+ *
+ * Return the actual process stack pointer
+ */
+extern uint32_t __get_PSP(void);
+
+/**
+ * @brief  Set the Process Stack Pointer
+ *
+ * @param  topOfProcStack  Process Stack Pointer
+ *
+ * Assign the value ProcessStackPointer to the MSP 
+ * (process stack pointer) Cortex processor register
+ */
+extern void __set_PSP(uint32_t topOfProcStack);
+
+/**
+ * @brief  Return the Main Stack Pointer
+ *
+ * @return Main Stack Pointer
+ *
+ * Return the current value of the MSP (main stack pointer)
+ * Cortex processor register
+ */
+extern uint32_t __get_MSP(void);
+
+/**
+ * @brief  Set the Main Stack Pointer
+ *
+ * @param  topOfMainStack  Main Stack Pointer
+ *
+ * Assign the value mainStackPointer to the MSP 
+ * (main stack pointer) Cortex processor register
+ */
+extern void __set_MSP(uint32_t topOfMainStack);
+
+/**
+ * @brief  Return the Priority Mask value
+ *
+ * @return PriMask
+ *
+ * Return state of the priority mask bit from the priority mask register
+ */
+extern uint32_t  __get_PRIMASK(void);
+
+/**
+ * @brief  Set the Priority Mask value
+ *
+ * @param  priMask  PriMask
+ *
+ * Set the priority mask bit in the priority mask register
+ */
+extern void __set_PRIMASK(uint32_t priMask);
+
+/**
+ * @brief  Return the Control Register value
+* 
+*  @return Control value
+ *
+ * Return the content of the control register
+ */
+extern uint32_t __get_CONTROL(void);
+
+/**
+ * @brief  Set the Control Register value
+ *
+ * @param  control  Control value
+ *
+ * Set the control register
+ */
+extern void __set_CONTROL(uint32_t control);
+
+/**
+ * @brief  Reverse byte order in integer value
+ *
+ * @param  value  value to reverse
+ * @return        reversed value
+ *
+ * Reverse byte order in integer value
+ */
+extern uint32_t __REV(uint32_t value);
+
+/**
+ * @brief  Reverse byte order in unsigned short value
+ *
+ * @param  value  value to reverse
+ * @return        reversed value
+ *
+ * Reverse byte order in unsigned short value
+ */
+extern uint32_t __REV16(uint16_t value);
+
+/**
+ * @brief  Reverse byte order in signed short value with sign extension to integer
+ *
+ * @param  value  value to reverse
+ * @return        reversed value
+ *
+ * Reverse byte order in signed short value with sign extension to integer
+ */
+extern int32_t __REVSH(int16_t value);
+
+
+#elif (defined (__TASKING__)) /*------------------ TASKING Compiler ---------------------*/
+/* TASKING carm specific functions */
+
+/*
+ * The CMSIS functions have been implemented as intrinsics in the compiler.
+ * Please use "carm -?i" to get an up to date list of all instrinsics,
+ * Including the CMSIS ones.
+ */
+
+#endif
+
+
+/** @addtogroup CMSIS_CM0_Core_FunctionInterface CMSIS CM0 Core Function Interface
+  Core  Function Interface containing:
+  - Core NVIC Functions
+  - Core SysTick Functions
+  - Core Reset Functions
+*/
+/*@{*/
+
+/* ##########################   NVIC functions  #################################### */
+
+/* Interrupt Priorities are WORD accessible only under ARMv6M                   */
+/* The following MACROS handle generation of the register offset and byte masks */
+#define _BIT_SHIFT(IRQn)         (  (((uint32_t)(IRQn)       )    &  0x03) * 8 )
+#define _SHP_IDX(IRQn)           ( ((((uint32_t)(IRQn) & 0x0F)-8) >>    2)     )
+#define _IP_IDX(IRQn)            (   ((uint32_t)(IRQn)            >>    2)     )
+
+
+/**
+ * @brief  Enable Interrupt in NVIC Interrupt Controller
+ *
+ * @param  IRQn   The positive number of the external interrupt to enable
+ *
+ * Enable a device specific interupt in the NVIC interrupt controller.
+ * The interrupt number cannot be a negative value.
+ */
+static __INLINE void NVIC_EnableIRQ(IRQn_Type IRQn)
+{
+  NVIC->ISER[0] = (1 << ((uint32_t)(IRQn) & 0x1F)); /* enable interrupt */
+}
+
+/**
+ * @brief  Disable the interrupt line for external interrupt specified
+ * 
+ * @param  IRQn   The positive number of the external interrupt to disable
+ * 
+ * Disable a device specific interupt in the NVIC interrupt controller.
+ * The interrupt number cannot be a negative value.
+ */
+static __INLINE void NVIC_DisableIRQ(IRQn_Type IRQn)
+{
+  NVIC->ICER[0] = (1 << ((uint32_t)(IRQn) & 0x1F)); /* disable interrupt */
+}
+
+/**
+ * @brief  Read the interrupt pending bit for a device specific interrupt source
+ * 
+ * @param  IRQn    The number of the device specifc interrupt
+ * @return         1 = interrupt pending, 0 = interrupt not pending
+ *
+ * Read the pending register in NVIC and return 1 if its status is pending, 
+ * otherwise it returns 0
+ */
+static __INLINE uint32_t NVIC_GetPendingIRQ(IRQn_Type IRQn)
+{
+  return((uint32_t) ((NVIC->ISPR[0] & (1 << ((uint32_t)(IRQn) & 0x1F)))?1:0)); /* Return 1 if pending else 0 */
+}
+
+/**
+ * @brief  Set the pending bit for an external interrupt
+ * 
+ * @param  IRQn    The number of the interrupt for set pending
+ *
+ * Set the pending bit for the specified interrupt.
+ * The interrupt number cannot be a negative value.
+ */
+static __INLINE void NVIC_SetPendingIRQ(IRQn_Type IRQn)
+{
+  NVIC->ISPR[0] = (1 << ((uint32_t)(IRQn) & 0x1F)); /* set interrupt pending */
+}
+
+/**
+ * @brief  Clear the pending bit for an external interrupt
+ *
+ * @param  IRQn    The number of the interrupt for clear pending
+ *
+ * Clear the pending bit for the specified interrupt. 
+ * The interrupt number cannot be a negative value.
+ */
+static __INLINE void NVIC_ClearPendingIRQ(IRQn_Type IRQn)
+{
+  NVIC->ICPR[0] = (1 << ((uint32_t)(IRQn) & 0x1F)); /* Clear pending interrupt */
+}
+
+/**
+ * @brief  Set the priority for an interrupt
+ *
+ * @param  IRQn      The number of the interrupt for set priority
+ * @param  priority  The priority to set
+ *
+ * Set the priority for the specified interrupt. The interrupt 
+ * number can be positive to specify an external (device specific) 
+ * interrupt, or negative to specify an internal (core) interrupt.
+ *
+ * Note: The priority cannot be set for every core interrupt.
+ */
+static __INLINE void NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority)
+{
+  if(IRQn < 0) {
+    SCB->SHP[_SHP_IDX(IRQn)] = (SCB->SHP[_SHP_IDX(IRQn)] & ~(0xFF << _BIT_SHIFT(IRQn))) | 
+        (((priority << (8 - __NVIC_PRIO_BITS)) & 0xFF) << _BIT_SHIFT(IRQn)); }
+  else {
+    NVIC->IPR[_IP_IDX(IRQn)] = (NVIC->IPR[_IP_IDX(IRQn)] & ~(0xFF << _BIT_SHIFT(IRQn))) |
+        (((priority << (8 - __NVIC_PRIO_BITS)) & 0xFF) << _BIT_SHIFT(IRQn)); }
+}
+
+/**
+ * @brief  Read the priority for an interrupt
+ *
+ * @param  IRQn      The number of the interrupt for get priority
+ * @return           The priority for the interrupt
+ *
+ * Read the priority for the specified interrupt. The interrupt 
+ * number can be positive to specify an external (device specific) 
+ * interrupt, or negative to specify an internal (core) interrupt.
+ *
+ * The returned priority value is automatically aligned to the implemented
+ * priority bits of the microcontroller.
+ *
+ * Note: The priority cannot be set for every core interrupt.
+ */
+static __INLINE uint32_t NVIC_GetPriority(IRQn_Type IRQn)
+{
+
+  if(IRQn < 0) {
+    return((uint32_t)((SCB->SHP[_SHP_IDX(IRQn)] >> _BIT_SHIFT(IRQn) ) >> (8 - __NVIC_PRIO_BITS)));  } /* get priority for Cortex-M0 system interrupts */
+  else {
+    return((uint32_t)((NVIC->IPR[_IP_IDX(IRQn)] >> _BIT_SHIFT(IRQn) ) >> (8 - __NVIC_PRIO_BITS)));  } /* get priority for device specific interrupts  */
+}
+
+
+
+/* ##################################    SysTick function  ############################################ */
+
+#if (!defined (__Vendor_SysTickConfig)) || (__Vendor_SysTickConfig == 0)
+
+/**
+ * @brief  Initialize and start the SysTick counter and its interrupt.
+ *
+ * @param   ticks   number of ticks between two interrupts
+ * @return  1 = failed, 0 = successful
+ *
+ * Initialise the system tick timer and its interrupt and start the
+ * system tick timer / counter in free running mode to generate 
+ * periodical interrupts.
+ */
+static __INLINE uint32_t SysTick_Config(uint32_t ticks)
+{ 
+  if (ticks > SysTick_LOAD_RELOAD_Msk)  return (1);            /* Reload value impossible */
+                                                               
+  SysTick->LOAD  = (ticks & SysTick_LOAD_RELOAD_Msk) - 1;      /* set reload register */
+  NVIC_SetPriority (SysTick_IRQn, (1<<__NVIC_PRIO_BITS) - 1);  /* set Priority for Cortex-M0 System Interrupts */
+  SysTick->VAL   = 0;                                          /* Load the SysTick Counter Value */
+  SysTick->CTRL  = SysTick_CTRL_CLKSOURCE_Msk | 
+                   SysTick_CTRL_TICKINT_Msk   | 
+                   SysTick_CTRL_ENABLE_Msk;                    /* Enable SysTick IRQ and SysTick Timer */
+  return (0);                                                  /* Function successful */
+}
+
+#endif
+
+
+
+
+/* ##################################    Reset function  ############################################ */
+
+/**
+ * @brief  Initiate a system reset request.
+ *
+ * Initiate a system reset request to reset the MCU
+ */
+static __INLINE void NVIC_SystemReset(void)
+{
+  SCB->AIRCR  = ((0x5FA << SCB_AIRCR_VECTKEY_Pos)      | 
+                 SCB_AIRCR_SYSRESETREQ_Msk);
+  __DSB();                                                                             /* Ensure completion of memory access */              
+  while(1);                                                                            /* wait until reset */
+}
+
+/*@}*/ /* end of group CMSIS_CM0_Core_FunctionInterface */
+
+#ifdef __cplusplus
+}
+#endif
+
+/*@}*/ /* end of group CMSIS_CM0_core_definitions */
+
+#endif /* __CM0_CORE_H__ */
+
+/*lint -restore */
diff --git a/libcpu/arm/lpc122x/CMSIS/startup_LPC122x.s b/libcpu/arm/lpc122x/CMSIS/startup_LPC122x.s
new file mode 100644
index 0000000000..fe2fdee3ef
--- /dev/null
+++ b/libcpu/arm/lpc122x/CMSIS/startup_LPC122x.s
@@ -0,0 +1,254 @@
+;/*****************************************************************************
+; * @file:    startup_LPC122x.s
+; * @purpose: CMSIS Cortex-M0 Core Device Startup File 
+; *           for the NXP LPC122x Device Series 
+; * @version: V1.0
+; * @date:    25. Nov. 2008
+; *------- <<< Use Configuration Wizard in Context Menu >>> ------------------
+; *
+; * Copyright (C) 2008 ARM Limited. All rights reserved.
+; * ARM Limited (ARM) is supplying this software for use with Cortex-M0 
+; * processor based microcontrollers.  This file can be freely distributed 
+; * within development tools that are supporting such ARM based processors. 
+; *
+; * THIS SOFTWARE IS PROVIDED "AS IS".  NO WARRANTIES, WHETHER EXPRESS, IMPLIED
+; * OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF
+; * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE.
+; * ARM SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR
+; * CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER.
+; *
+; *****************************************************************************/
+
+
+; <h> Stack Configuration
+;   <o> Stack Size (in Bytes) <0x0-0xFFFFFFFF:8>
+; </h>
+
+Stack_Size      EQU     0x00000200
+
+                AREA    STACK, NOINIT, READWRITE, ALIGN=3
+Stack_Mem       SPACE   Stack_Size
+__initial_sp
+
+
+; <h> Heap Configuration
+;   <o>  Heap Size (in Bytes) <0x0-0xFFFFFFFF:8>
+; </h>
+
+Heap_Size       EQU     0x00000000
+
+                AREA    HEAP, NOINIT, READWRITE, ALIGN=3
+__heap_base
+Heap_Mem        SPACE   Heap_Size
+__heap_limit
+
+
+                PRESERVE8
+                THUMB
+
+
+; Vector Table Mapped to Address 0 at Reset
+
+                AREA    RESET, DATA, READONLY
+                EXPORT  __Vectors
+
+__Vectors       DCD     __initial_sp              ; Top of Stack
+                DCD     Reset_Handler             ; Reset Handler
+                DCD     NMI_Handler               ; NMI Handler
+                DCD     HardFault_Handler         ; Hard Fault Handler
+                DCD     MemManage_Handler         ; MPU Fault Handler
+                DCD     BusFault_Handler          ; Bus Fault Handler
+                DCD     UsageFault_Handler        ; Usage Fault Handler
+                DCD     0                         ; Reserved
+                DCD     0                         ; Reserved
+                DCD     0                         ; Reserved
+                DCD     0                         ; Reserved
+                DCD     SVC_Handler               ; SVCall Handler
+                DCD     DebugMon_Handler          ; Debug Monitor Handler
+                DCD     0                         ; Reserved
+                DCD     PendSV_Handler            ; PendSV Handler
+                DCD     SysTick_Handler           ; SysTick Handler
+
+                ; External Interrupts
+                DCD     WAKEUP_IRQHandler         ; 12 wakeup sources for all the
+                DCD     WAKEUP_IRQHandler         ; I/O pins starting from PIO0 (0:11)
+                DCD     WAKEUP_IRQHandler         ; all 40 are routed to the same ISR                       
+                DCD     WAKEUP_IRQHandler                         
+                DCD     WAKEUP_IRQHandler                        
+                DCD     WAKEUP_IRQHandler
+                DCD     WAKEUP_IRQHandler
+                DCD     WAKEUP_IRQHandler                       
+                DCD     WAKEUP_IRQHandler                         
+                DCD     WAKEUP_IRQHandler                        
+                DCD     WAKEUP_IRQHandler
+                DCD     WAKEUP_IRQHandler        
+                DCD     I2C_IRQHandler            ; I2C
+                DCD     TIMER16_0_IRQHandler      ; 16-bit Timer0
+                DCD     TIMER16_1_IRQHandler      ; 16-bit Timer1
+                DCD     TIMER32_0_IRQHandler      ; 32-bit Timer0
+                DCD     TIMER32_1_IRQHandler      ; 32-bit Timer1
+                DCD     SSP_IRQHandler            ; SSP
+                DCD     UART0_IRQHandler          ; UART0
+                DCD     UART1_IRQHandler          ; UART1
+                DCD     COMP_IRQHandler           ; Comparator
+                DCD     ADC_IRQHandler            ; A/D Converter
+                DCD     WDT_IRQHandler            ; Watchdog timer
+                DCD     BOD_IRQHandler            ; Brown Out Detect
+                DCD     FMC_IRQHandler            ; IP2111 Flash Memory Controller
+                DCD     PIOINT0_IRQHandler        ; PIO INT0
+                DCD     PIOINT1_IRQHandler        ; PIO INT1
+                DCD     PIOINT2_IRQHandler        ; PIO INT2
+                DCD     PMU_IRQHandler            ; PMU/Wakeup
+                DCD     DMA_IRQHandler            ; DMA
+                DCD     RTC_IRQHandler            ; RTC
+                DCD     EDM_IRQHandler            ; Event Driven Micro 
+
+
+                IF      :LNOT::DEF:NO_CRP
+                AREA    |.ARM.__at_0x02FC|, CODE, READONLY
+CRP_Key         DCD     0xFFFFFFFF
+                ENDIF
+
+
+                AREA    |.text|, CODE, READONLY
+
+
+; Reset Handler
+
+Reset_Handler   PROC
+                EXPORT  Reset_Handler             [WEAK]
+                IMPORT  __main
+                LDR     R0, =__main
+                BX      R0
+                ENDP
+
+
+; Dummy Exception Handlers (infinite loops which can be modified)                
+
+; now, under COMMON NMI.c and NMI.h, a real NMI handler is created if NMI is enabled 
+; for particular peripheral.
+;NMI_Handler     PROC
+;                EXPORT  NMI_Handler               [WEAK]
+;                B       .
+;                ENDP
+HardFault_Handler\
+                PROC
+                EXPORT  HardFault_Handler         [WEAK]
+                B       .
+                ENDP
+MemManage_Handler\
+                PROC
+                EXPORT  MemManage_Handler         [WEAK]
+                B       .
+                ENDP
+BusFault_Handler\
+                PROC
+                EXPORT  BusFault_Handler          [WEAK]
+                B       .
+                ENDP
+UsageFault_Handler\
+                PROC
+                EXPORT  UsageFault_Handler        [WEAK]
+                B       .
+                ENDP
+SVC_Handler     PROC
+                EXPORT  SVC_Handler               [WEAK]
+                B       .
+                ENDP
+DebugMon_Handler\
+                PROC
+                EXPORT  DebugMon_Handler          [WEAK]
+                B       .
+                ENDP
+PendSV_Handler  PROC
+                EXPORT  PendSV_Handler            [WEAK]
+                B       .
+                ENDP
+SysTick_Handler PROC
+                EXPORT  SysTick_Handler           [WEAK]
+                B       .
+                ENDP
+
+Default_Handler PROC
+
+                EXPORT  NMI_Handler               [WEAK]
+                EXPORT  WAKEUP_IRQHandler         [WEAK]
+                EXPORT  I2C_IRQHandler            [WEAK]
+                EXPORT  TIMER16_0_IRQHandler      [WEAK]
+                EXPORT  TIMER16_1_IRQHandler      [WEAK]
+                EXPORT  TIMER32_0_IRQHandler      [WEAK]
+                EXPORT  TIMER32_1_IRQHandler      [WEAK]
+                EXPORT  SSP_IRQHandler            [WEAK]
+                EXPORT  UART0_IRQHandler          [WEAK]
+                EXPORT  UART1_IRQHandler          [WEAK]
+
+                EXPORT  COMP_IRQHandler           [WEAK]
+                EXPORT  ADC_IRQHandler            [WEAK]
+                EXPORT  WDT_IRQHandler            [WEAK]
+                EXPORT  BOD_IRQHandler            [WEAK]
+                EXPORT  FMC_IRQHandler            [WEAK]
+                EXPORT	PIOINT0_IRQHandler        [WEAK]
+                EXPORT	PIOINT1_IRQHandler        [WEAK]
+                EXPORT  PIOINT2_IRQHandler        [WEAK]
+                EXPORT  PMU_IRQHandler            [WEAK]
+                EXPORT  DMA_IRQHandler            [WEAK]
+                EXPORT  RTC_IRQHandler            [WEAK]
+                EXPORT  EDM_IRQHandler            [WEAK]
+
+NMI_Handler
+WAKEUP_IRQHandler
+I2C_IRQHandler
+TIMER16_0_IRQHandler
+TIMER16_1_IRQHandler
+TIMER32_0_IRQHandler
+TIMER32_1_IRQHandler
+SSP_IRQHandler
+UART0_IRQHandler
+UART1_IRQHandler
+COMP_IRQHandler
+ADC_IRQHandler
+WDT_IRQHandler
+BOD_IRQHandler
+FMC_IRQHandler
+PIOINT0_IRQHandler  
+PIOINT1_IRQHandler 
+PIOINT2_IRQHandler
+PMU_IRQHandler
+DMA_IRQHandler
+RTC_IRQHandler
+EDM_IRQHandler
+
+                B       .
+
+                ENDP
+
+
+                ALIGN
+
+
+; User Initial Stack & Heap
+
+                IF      :DEF:__MICROLIB
+                
+                EXPORT  __initial_sp
+                EXPORT  __heap_base
+                EXPORT  __heap_limit
+                
+                ELSE
+                
+                IMPORT  __use_two_region_memory
+                EXPORT  __user_initial_stackheap
+__user_initial_stackheap
+
+                LDR     R0, =  Heap_Mem
+                LDR     R1, =(Stack_Mem + Stack_Size)
+                LDR     R2, = (Heap_Mem +  Heap_Size)
+                LDR     R3, = Stack_Mem
+                BX      LR
+
+                ALIGN
+
+                ENDIF
+
+
+                END
diff --git a/libcpu/arm/lpc122x/CMSIS/system_LPC122x.c b/libcpu/arm/lpc122x/CMSIS/system_LPC122x.c
new file mode 100644
index 0000000000..9e9a210709
--- /dev/null
+++ b/libcpu/arm/lpc122x/CMSIS/system_LPC122x.c
@@ -0,0 +1,213 @@
+/******************************************************************************
+ * @file:    system_LPC122x.c
+ * @purpose: CMSIS Cortex-M0 Device Peripheral Access Layer Source File
+ *           for the NXP LPC122x Device Series 
+ * @version: V1.0
+ * @date:    26. Nov. 2008
+ *----------------------------------------------------------------------------
+ *
+ * Copyright (C) 2008 ARM Limited. All rights reserved.
+ *
+ * ARM Limited (ARM) is supplying this software for use with Cortex-M3 
+ * processor based microcontrollers.  This file can be freely distributed 
+ * within development tools that are supporting such ARM based processors. 
+ *
+ * THIS SOFTWARE IS PROVIDED "AS IS".  NO WARRANTIES, WHETHER EXPRESS, IMPLIED
+ * OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE.
+ * ARM SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR
+ * CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER.
+ *
+ ******************************************************************************/
+#include <stdint.h>
+#include "LPC122x.h"
+
+/*
+//-------- <<< Use Configuration Wizard in Context Menu >>> ------------------
+*/
+
+/*--------------------- Clock Configuration ----------------------------------
+//
+// <e> Clock Configuration
+//   <h> System Controls and Status Register (SCS)
+//     <o1.4>    OSCRANGE: Main Oscillator Range Select
+//                     <0=>  1 MHz to 20 MHz
+//                     <1=> 15 MHz to 24 MHz
+//     <e1.5>       OSCEN: Main Oscillator Enable
+//     </e>
+//   </h>
+//
+//   <h> Clock Source Select Register (CLKSRCSEL)
+//     <o2.0..1>   CLKSRC: PLL Clock Source Selection
+//                     <0=> Internal RC oscillator
+//                     <1=> Main oscillator
+//                     <2=> RTC oscillator
+//   </h>
+//
+//   <e3> PLL0 Configuration (Main PLL)
+//     <h> PLL0 Configuration Register (PLL0CFG)
+//                     <i> F_cco0 = (2 * M * F_in) / N
+//                     <i> F_in must be in the range of 32 kHz to 50 MHz
+//                     <i> F_cco0 must be in the range of 275 MHz to 550 MHz
+//       <o4.0..14>  MSEL: PLL Multiplier Selection
+//                     <6-32768><#-1>
+//                     <i> M Value
+//       <o4.16..23> NSEL: PLL Divider Selection
+//                     <1-256><#-1>
+//                     <i> N Value
+//     </h>
+//   </e>
+//
+//
+//   <h> CPU Clock Configuration Register (CCLKCFG)
+//     <o7.0..7>  CCLKSEL: Divide Value for CPU Clock from PLL0
+//                     <0-255>
+//                     <i> Divide is CCLKSEL + 1. Only 0 and odd values are valid.
+//   </h>
+//
+//
+// </e>
+*/
+#define CLOCK_SETUP           1
+
+#define SYS_PLL_SETUP         1
+#define SYS_PLLSRCSEL_Val     0x00000001
+#define SYS_PLL_M_Val         0x00000003
+#define SYS_PLL_P_Val         0x00000001
+#define MAIN_CLKSRCSEL_Val    0x00000003
+#define SYS_AHB_DIV_Val       0x01			/* 1 through 255, 0 will disable the output. */
+
+/*
+//-------- <<< end of configuration section >>> ------------------------------
+*/
+
+/*----------------------------------------------------------------------------
+  DEFINES
+ *----------------------------------------------------------------------------*/
+    
+/*----------------------------------------------------------------------------
+  Define clocks
+ *----------------------------------------------------------------------------*/
+#define XTAL        (12000000UL)        /* Oscillator frequency               */
+#define OSC_CLK     (      XTAL)        /* Main oscillator frequency          */
+#define IRC_OSC     ( 4000000UL)        /* Internal RC oscillator frequency   */
+#define WDT_OSC     (  250000UL)        /* WDT oscillator frequency           */
+
+/*----------------------------------------------------------------------------
+  Clock Variable definitions
+ *----------------------------------------------------------------------------*/
+uint32_t ClockSource = IRC_OSC;
+uint32_t SystemFrequency = IRC_OSC; /*!< System Clock Frequency (Core Clock)  */
+uint32_t SystemAHBFrequency = IRC_OSC;
+
+/**
+ * Misc. clock generation modules
+ *
+ * @param  none
+ * @return none
+ *
+ * @brief  Setup the microcontroller system.
+ *         Initialize the System and update the SystemFrequency variable.
+ */
+void SystemPLL_Setup ( void )
+{
+  uint32_t regVal;
+
+  LPC_SYSCON->PRESETCTRL  &= ~0x00008000;		  /* Disable 1-Cycle Read Mode */
+
+  ClockSource = OSC_CLK;
+  LPC_SYSCON->SYSPLLCLKSEL = SYS_PLLSRCSEL_Val;    /* Select system OSC */
+  LPC_SYSCON->SYSPLLCLKUEN = 0x01;                 /* Update clock source */
+  LPC_SYSCON->SYSPLLCLKUEN = 0x00;                 /* toggle Update register once */
+  LPC_SYSCON->SYSPLLCLKUEN = 0x01;
+  while ( !(LPC_SYSCON->SYSPLLCLKUEN & 0x01) ); /* Wait until updated */
+
+  regVal = LPC_SYSCON->SYSPLLCTRL;
+  regVal &= ~0x1FF;
+  LPC_SYSCON->SYSPLLCTRL = (regVal | (SYS_PLL_P_Val<<5) | SYS_PLL_M_Val);
+  
+  /* Enable main system clock, main system clock bit 7 in PDRUNCFG. */
+  LPC_SYSCON->PDRUNCFG &= ~(0x1<<7);
+  while ( !(LPC_SYSCON->SYSPLLSTAT & 0x01) );	/* Wait until it's locked */
+
+  LPC_SYSCON->MAINCLKSEL = MAIN_CLKSRCSEL_Val;	/* Select PLL clock output */
+  LPC_SYSCON->MAINCLKUEN = 0x01;		/* Update MCLK clock source */
+  LPC_SYSCON->MAINCLKUEN = 0x00;		/* Toggle update register once */
+  LPC_SYSCON->MAINCLKUEN = 0x01;
+  while ( !(LPC_SYSCON->MAINCLKUEN & 0x01) );	/* Wait until updated */
+
+  LPC_SYSCON->SYSAHBCLKDIV = SYS_AHB_DIV_Val;	/* SYS AHB clock, 0 will disable output */
+
+#if SYS_PLL_SETUP
+  /* If the SYS PLL output is selected as the main clock. Even if SYS PLL is 
+  configured and enabled, it doesn't mean it will be selected as the MAIN clock 
+  source. Be careful with MAINCLKSEL value. If SYS PLL is not selected, System
+  Frequence should be the same as either IRC, external OSC(SYS), or WDT OSC clock. */
+  SystemFrequency = ClockSource * (SYS_PLL_M_Val+1);
+#else
+  SystemFrequency = ClockSource;
+#endif
+  SystemAHBFrequency = (uint32_t)(SystemFrequency/SYS_AHB_DIV_Val);
+  return;
+}
+
+/**
+ * Initialize the system
+ *
+ * @param  none
+ * @return none
+ *
+ * @brief  Setup the microcontroller system.
+ *         Initialize the System and update the SystemFrequency variable.
+ */
+void SystemInit (void)
+{
+  uint32_t i;
+
+#ifdef __DEBUG_RAM    
+  LPC_SYSCON->SYSMEMREMAP = 0x1;		/* remap to internal RAM */ 
+#else
+#ifdef __DEBUG_FLASH    
+  LPC_SYSCON->SYSMEMREMAP = 0x2;		/* remap to internal flash */
+#endif
+#endif
+
+#if 1
+  /* First, below lines are for debugging only. For future release, WDT is 
+  enabled by bootrom, thus, unless a feed to WDT continuously, or WDT timeout 
+  will occur. If it's happen, WDT interrupt will be pending until a INT_CLEAR
+  is applied. Below logic is to prevent system from going to the WDT interrupt
+  during debugging. 
+  Second, all the peripheral clocks seem to be enabled by bootrom, it's
+  not consistent with the UM. In below lines, only SYS, ROM, RAM, FLASHREG,
+  FLASHARRAY, and I2C are enabled per UM dated July 14th. */
+  LPC_WDT->MOD = 0x00;  
+  LPC_WDT->FEED = 0xAA;		/* Feeding sequence */
+  LPC_WDT->FEED = 0x55;
+  
+  NVIC->ICPR[0] |= 0xFFFFFFFF; 
+  LPC_SYSCON->SYSAHBCLKCTRL = 0x00000001F;
+#endif   
+
+#if (CLOCK_SETUP)                       /* Clock Setup */
+  /* bit 0 default is crystal bypass, 
+  bit1 0=0~20Mhz crystal input, 1=15~50Mhz crystal input. */
+  LPC_SYSCON->SYSOSCCTRL = 0x00;
+
+  /* main system OSC run is cleared, bit 5 in PDRUNCFG register */
+  LPC_SYSCON->PDRUNCFG &= ~(0x1<<5);
+  /* Wait 200us for OSC to be stablized, no status 
+  indication, dummy wait. */
+  for ( i = 0; i < 0x100; i++ );
+
+#if (SYS_PLL_SETUP)
+  SystemPLL_Setup();  
+#endif
+
+#endif	/* endif CLOCK_SETUP */
+
+  /* System clock to the IOCON needs to be enabled or
+  most of the I/O related peripherals won't work. */
+  LPC_SYSCON->SYSAHBCLKCTRL |= (1<<16);
+  return;
+}
diff --git a/libcpu/arm/lpc122x/CMSIS/system_LPC122x.h b/libcpu/arm/lpc122x/CMSIS/system_LPC122x.h
new file mode 100644
index 0000000000..38c6d84e4a
--- /dev/null
+++ b/libcpu/arm/lpc122x/CMSIS/system_LPC122x.h
@@ -0,0 +1,45 @@
+/******************************************************************************
+ * @file:    system_LPC122x.h
+ * @purpose: CMSIS Cortex-M0 Device Peripheral Access Layer Header File
+ *           for the NXP LPC122x Device Series 
+ * @version: V1.0
+ * @date:    25. Nov. 2008
+ *----------------------------------------------------------------------------
+ *
+ * Copyright (C) 2008 ARM Limited. All rights reserved.
+ *
+ * ARM Limited (ARM) is supplying this software for use with Cortex-M0 
+ * processor based microcontrollers.  This file can be freely distributed 
+ * within development tools that are supporting such ARM based processors. 
+ *
+ * THIS SOFTWARE IS PROVIDED "AS IS".  NO WARRANTIES, WHETHER EXPRESS, IMPLIED
+ * OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE.
+ * ARM SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR
+ * CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER.
+ *
+ ******************************************************************************/
+
+
+#ifndef __SYSTEM_LPC122x_H
+#define __SYSTEM_LPC122x_H
+
+/* Vector Table Base ---------------------------------------------------------*/
+#define NVIC_VectTab_RAM             (0x10000000)
+#define NVIC_VectTab_FLASH           (0x00000000)
+
+extern uint32_t ClockSource;
+extern uint32_t SystemFrequency;    /*!< System Clock Frequency (Core Clock)  */
+extern uint32_t SystemAHBFrequency;
+
+/**
+ * Initialize the system
+ *
+ * @param  none
+ * @return none
+ *
+ * @brief  Setup the microcontroller system.
+ *         Initialize the System and update the SystemFrequency variable.
+ */
+extern void SystemInit (void);
+#endif
diff --git a/libcpu/arm/lpc122x/context_rvds.S b/libcpu/arm/lpc122x/context_rvds.S
new file mode 100644
index 0000000000..9eb913f27a
--- /dev/null
+++ b/libcpu/arm/lpc122x/context_rvds.S
@@ -0,0 +1,175 @@
+;/*
+; * File      : context_rvds.S
+; * This file is part of RT-Thread RTOS
+; * COPYRIGHT (C) 2009, RT-Thread Development Team
+; *
+; * The license and distribution terms for this file may be
+; * found in the file LICENSE in this distribution or at
+; * http://www.rt-thread.org/license/LICENSE
+; *
+; * Change Logs:
+; * Date           Author       Notes
+; * 2010-01-25     Bernard      first version
+; */
+
+;/**
+; * @addtogroup LPC1100
+; */
+;/*@{*/
+
+NVIC_INT_CTRL   EQU     0xE000ED04               ; interrupt control state register
+NVIC_SYSPRI2    EQU     0xE000ED20               ; system priority register (2)
+NVIC_PENDSV_PRI EQU     0x00FF0000               ; PendSV priority value (lowest)
+NVIC_PENDSVSET  EQU     0x10000000               ; value to trigger PendSV exception
+
+	AREA |.text|, CODE, READONLY, ALIGN=2
+	THUMB
+	REQUIRE8
+	PRESERVE8
+
+	IMPORT rt_thread_switch_interrput_flag
+	IMPORT rt_interrupt_from_thread
+	IMPORT rt_interrupt_to_thread
+
+;/*
+; * rt_base_t rt_hw_interrupt_disable();
+; */
+rt_hw_interrupt_disable    PROC
+	EXPORT  rt_hw_interrupt_disable
+	MRS		r0, PRIMASK
+	CPSID   I
+	BX		LR
+	ENDP
+
+;/*
+; * void rt_hw_interrupt_enable(rt_base_t level);
+; */
+rt_hw_interrupt_enable    PROC
+	EXPORT  rt_hw_interrupt_enable
+	MSR		PRIMASK, r0
+	BX      LR
+	ENDP
+
+;/*
+; * void rt_hw_context_switch(rt_uint32 from, rt_uint32 to);
+; * r0 --> from
+; * r1 --> to
+; */
+rt_hw_context_switch_interrupt
+	EXPORT rt_hw_context_switch_interrupt
+rt_hw_context_switch    PROC
+	EXPORT rt_hw_context_switch
+
+	; set rt_thread_switch_interrput_flag to 1
+	LDR 	r2, =rt_thread_switch_interrput_flag
+	LDR 	r3, [r2]
+	CMP 	r3, #1
+	BEQ 	_reswitch
+	MOVS 	r3, #0x1
+	STR 	r3, [r2]
+
+	LDR 	r2, =rt_interrupt_from_thread	; set rt_interrupt_from_thread
+	STR 	r0, [r2]
+
+_reswitch
+	LDR 	r2, =rt_interrupt_to_thread		; set rt_interrupt_to_thread
+	STR 	r1, [r2]
+
+    LDR     r0, =NVIC_INT_CTRL      		; trigger the PendSV exception (causes context switch)
+    LDR     r1, =NVIC_PENDSVSET
+	STR     r1, [r0]
+	BX      LR
+	ENDP
+
+; r0 --> swith from thread stack
+; r1 --> swith to thread stack
+; psr, pc, lr, r12, r3, r2, r1, r0 are pushed into [from] stack
+rt_hw_pend_sv	PROC
+	EXPORT rt_hw_pend_sv
+
+	; disable interrupt to protect context switch
+	MRS		r2, PRIMASK
+	CPSID   I
+
+	; get rt_thread_switch_interrupt_flag
+	LDR		r0, =rt_thread_switch_interrput_flag
+	LDR		r1, [r0]
+	CMP		r1, #0x00
+	BEQ		pendsv_exit				; pendsv already handled
+
+	; clear rt_thread_switch_interrput_flag to 0
+	MOVS	r1, #0x00
+	STR		r1, [r0]
+
+	LDR		r0, =rt_interrupt_from_thread
+	LDR		r1, [r0]
+	CMP		r1, #0x00
+	BEQ		swtich_to_thread    	; skip register save at the first time
+
+	MRS     r1, psp                 ; get from thread stack pointer
+	SUBS	r1, r1, #0x10
+	LDR		r0, [r0]
+	STR		r1, [r0]				; update from thread stack pointer
+	STMIA	r1!, {r4 - r7}			; push r4 - r7 register
+
+swtich_to_thread
+	LDR		r1, =rt_interrupt_to_thread
+	LDR		r1, [r1]
+	LDR		r1, [r1]				; load thread stack pointer
+
+	LDMIA	r1!, {r4 - r7}			; pop r4 - r7 register
+	MSR		psp, r1					; update stack pointer
+
+pendsv_exit
+	; restore interrupt
+	MSR		PRIMASK, r2
+
+	MOVS	r0, #0x04
+	RSBS	r0, #0
+	BX		r0
+	ENDP
+
+;/*
+; * void rt_hw_context_switch_to(rt_uint32 to);
+; * r0 --> to
+; * this fucntion is used to perform the first thread switch
+; */
+rt_hw_context_switch_to    PROC
+	EXPORT rt_hw_context_switch_to
+	; set to thread
+	LDR		r1, =rt_interrupt_to_thread
+	STR		r0, [r1]
+
+	; set from thread to 0
+	LDR		r1, =rt_interrupt_from_thread
+	MOVS	r0, #0x0
+	STR		r0, [r1]
+
+	; set interrupt flag to 1
+	LDR 	r1, =rt_thread_switch_interrput_flag
+	MOVS 	r0, #1
+	STR 	r0, [r1]
+
+	; set the PendSV exception priority
+    ; LDR     r0, =NVIC_SYSPRI2
+    ; LDR     r1, =NVIC_PENDSV_PRI
+    ; STR     r1, [r0]
+
+	; trigger the PendSV exception (causes context switch)
+    LDR     r0, =NVIC_INT_CTRL
+    LDR     r1, =NVIC_PENDSVSET
+    STR     r1, [r0]
+
+	; enable interrupts at processor level
+    CPSIE   I
+
+	; never reach here!
+	ENDP
+
+; compatible with old version
+rt_hw_interrupt_thread_switch PROC
+	EXPORT rt_hw_interrupt_thread_switch
+	BX		lr
+	ENDP
+
+	END
diff --git a/libcpu/arm/lpc122x/cpu.c b/libcpu/arm/lpc122x/cpu.c
new file mode 100644
index 0000000000..7efd166a3f
--- /dev/null
+++ b/libcpu/arm/lpc122x/cpu.c
@@ -0,0 +1,42 @@
+/*
+ * File      : cpu.c
+ * This file is part of RT-Thread RTOS
+ * COPYRIGHT (C) 2009, RT-Thread Development Team
+ *
+ * The license and distribution terms for this file may be
+ * found in the file LICENSE in this distribution or at
+ * http://www.rt-thread.org/license/LICENSE
+ *
+ * Change Logs:
+ * Date           Author       Notes
+ * 2010-01-25     Bernard      first version
+ */
+
+#include <rtthread.h>
+
+/**
+ * @addtogroup LPC1100
+ */
+/*@{*/
+
+/**
+ * reset cpu by dog's time-out
+ *
+ */
+void rt_hw_cpu_reset()
+{
+	/*NOTREACHED*/
+}
+
+/**
+ *  shutdown CPU
+ *
+ */
+void rt_hw_cpu_shutdown()
+{
+	rt_kprintf("shutdown...\n");
+
+	RT_ASSERT(0);
+}
+
+/*@}*/
diff --git a/libcpu/arm/lpc122x/fault.c b/libcpu/arm/lpc122x/fault.c
new file mode 100644
index 0000000000..5b8dc6b62f
--- /dev/null
+++ b/libcpu/arm/lpc122x/fault.c
@@ -0,0 +1,47 @@
+/*
+ * File      : fault.c
+ * This file is part of RT-Thread RTOS
+ * COPYRIGHT (C) 2009, RT-Thread Development Team
+ *
+ * The license and distribution terms for this file may be
+ * found in the file LICENSE in this distribution or at
+ * http://www.rt-thread.org/license/LICENSE
+ *
+ * Change Logs:
+ * Date           Author       Notes
+ * 2010-01-25     Bernard      first version
+ */
+#include <rtthread.h>
+
+struct stack_contex
+{
+	rt_uint32_t r0;
+	rt_uint32_t r1;
+	rt_uint32_t r2;
+	rt_uint32_t r3;
+	rt_uint32_t r12;
+	rt_uint32_t lr;
+	rt_uint32_t pc;
+	rt_uint32_t psr;
+};
+
+extern void rt_hw_interrupt_thread_switch(void);
+extern void list_thread(void);
+extern rt_thread_t rt_current_thread;
+void rt_hw_hard_fault_exception(struct stack_contex* contex)
+{
+	rt_kprintf("psr: 0x%08x\n", contex->psr);
+	rt_kprintf(" pc: 0x%08x\n", contex->pc);
+	rt_kprintf(" lr: 0x%08x\n", contex->lr);
+	rt_kprintf("r12: 0x%08x\n", contex->r12);
+	rt_kprintf("r03: 0x%08x\n", contex->r3);
+	rt_kprintf("r02: 0x%08x\n", contex->r2);
+	rt_kprintf("r01: 0x%08x\n", contex->r1);
+	rt_kprintf("r00: 0x%08x\n", contex->r0);
+
+	rt_kprintf("hard fault on thread: %s\n", rt_current_thread->name);
+#ifdef RT_USING_FINSH
+	list_thread();
+#endif
+	while (1);
+}
diff --git a/libcpu/arm/lpc122x/fault_rvds.S b/libcpu/arm/lpc122x/fault_rvds.S
new file mode 100644
index 0000000000..4029306400
--- /dev/null
+++ b/libcpu/arm/lpc122x/fault_rvds.S
@@ -0,0 +1,32 @@
+;/*
+; * File      : fault_rvds.S
+; * This file is part of RT-Thread RTOS
+; * COPYRIGHT (C) 2006, RT-Thread Development Team
+; *
+; * The license and distribution terms for this file may be
+; * found in the file LICENSE in this distribution or at
+; * http://www.rt-thread.org/license/LICENSE
+; *
+; * Change Logs:
+; * Date           Author       Notes
+; * 2010-01-25     Bernard      first version
+; */
+
+    AREA |.text|, CODE, READONLY, ALIGN=2
+    THUMB
+    REQUIRE8
+    PRESERVE8
+
+    IMPORT rt_hw_hard_fault_exception
+
+rt_hw_hard_fault    PROC
+    EXPORT rt_hw_hard_fault
+
+    ; get current context
+    MRS     r0, psp                 ; get fault thread stack pointer
+    PUSH    {lr}
+    BL      rt_hw_hard_fault_exception
+    POP     {pc}
+    ENDP
+
+    END
diff --git a/libcpu/arm/lpc122x/interrupt.c b/libcpu/arm/lpc122x/interrupt.c
new file mode 100644
index 0000000000..a1a3eb2441
--- /dev/null
+++ b/libcpu/arm/lpc122x/interrupt.c
@@ -0,0 +1,21 @@
+/*
+ * File      : interrupt.c
+ * This file is part of RT-Thread RTOS
+ * COPYRIGHT (C) 2009, RT-Thread Development Team
+ *
+ * The license and distribution terms for this file may be
+ * found in the file LICENSE in this distribution or at
+ * http://www.rt-thread.org/license/LICENSE
+ *
+ * Change Logs:
+ * Date           Author       Notes
+ * 2010-01-25     Bernard      first version
+ */
+
+#include <rtthread.h>
+
+/* exception and interrupt handler table */
+rt_uint32_t rt_interrupt_from_thread, rt_interrupt_to_thread;
+rt_uint8_t rt_thread_switch_interrput_flag;
+
+/*@}*/
diff --git a/libcpu/arm/lpc122x/stack.c b/libcpu/arm/lpc122x/stack.c
new file mode 100644
index 0000000000..6bfa26b08a
--- /dev/null
+++ b/libcpu/arm/lpc122x/stack.c
@@ -0,0 +1,54 @@
+/*
+ * File      : stack.c
+ * This file is part of RT-Thread RTOS
+ * COPYRIGHT (C) 2009, RT-Thread Development Team
+ *
+ * The license and distribution terms for this file may be
+ * found in the file LICENSE in this distribution or at
+ * http://www.rt-thread.org/license/LICENSE
+ *
+ * Change Logs:
+ * Date           Author       Notes
+ * 2010-01-25     Bernard      first version
+ */
+#include <rtthread.h>
+
+/**
+ * @addtogroup LPC1100
+ */
+/*@{*/
+
+/**
+ * This function will initialize thread stack
+ *
+ * @param tentry the entry of thread
+ * @param parameter the parameter of entry
+ * @param stack_addr the beginning stack address
+ * @param texit the function will be called when thread exit
+ *
+ * @return stack address
+ */
+rt_uint8_t *rt_hw_stack_init(void *tentry, void *parameter,
+	rt_uint8_t *stack_addr, void *texit)
+{
+	unsigned long *stk;
+
+	stk 	 = (unsigned long *)stack_addr;
+	*(stk)   = 0x01000000L;					/* PSR */
+	*(--stk) = (unsigned long)tentry;		/* entry point, pc */
+	*(--stk) = (unsigned long)texit;		/* lr */
+	*(--stk) = 0;							/* r12 */
+	*(--stk) = 0;							/* r3 */
+	*(--stk) = 0;							/* r2 */
+	*(--stk) = 0;							/* r1 */
+	*(--stk) = (unsigned long)parameter;	/* r0 : argument */
+	*(--stk) = 0;							/* r7 */
+	*(--stk) = 0;							/* r6 */
+	*(--stk) = 0;							/* r5 */
+	*(--stk) = 0;							/* r4 */
+
+	/* return task's current stack address */
+	return (rt_uint8_t *)stk;
+}
+
+/*@}*/
diff --git a/libcpu/arm/lpc122x/start_rvds.S b/libcpu/arm/lpc122x/start_rvds.S
new file mode 100644
index 0000000000..de4cc263eb
--- /dev/null
+++ b/libcpu/arm/lpc122x/start_rvds.S
@@ -0,0 +1,254 @@
+;/*****************************************************************************
+; * @file:    startup_LPC11xx.s
+; * @purpose: CMSIS Cortex-M0 Core Device Startup File 
+; *           for the NXP LPC11xx Device Series 
+; * @version: V1.0
+; * @date:    25. Nov. 2008
+; *------- <<< Use Configuration Wizard in Context Menu >>> ------------------
+; *
+; * Copyright (C) 2008 ARM Limited. All rights reserved.
+; * ARM Limited (ARM) is supplying this software for use with Cortex-M0 
+; * processor based microcontrollers.  This file can be freely distributed 
+; * within development tools that are supporting such ARM based processors. 
+; *
+; * THIS SOFTWARE IS PROVIDED "AS IS".  NO WARRANTIES, WHETHER EXPRESS, IMPLIED
+; * OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF
+; * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE.
+; * ARM SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR
+; * CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER.
+; *
+; *****************************************************************************/
+
+
+; <h> Stack Configuration
+;   <o> Stack Size (in Bytes) <0x0-0xFFFFFFFF:8>
+; </h>
+
+Stack_Size      EQU     0x00000200
+
+                AREA    STACK, NOINIT, READWRITE, ALIGN=3
+Stack_Mem       SPACE   Stack_Size
+__initial_sp
+
+
+; <h> Heap Configuration
+;   <o>  Heap Size (in Bytes) <0x0-0xFFFFFFFF:8>
+; </h>
+
+Heap_Size       EQU     0x00000000
+
+                AREA    HEAP, NOINIT, READWRITE, ALIGN=3
+__heap_base
+Heap_Mem        SPACE   Heap_Size
+__heap_limit
+
+
+                PRESERVE8
+                THUMB
+
+				IMPORT rt_hw_hard_fault
+				IMPORT rt_hw_pend_sv
+				IMPORT rt_hw_timer_handler
+
+; Vector Table Mapped to Address 0 at Reset
+
+                AREA    RESET, DATA, READONLY
+                EXPORT  __Vectors
+
+__Vectors       DCD     __initial_sp              ; Top of Stack
+                DCD     Reset_Handler             ; Reset Handler
+                DCD     NMI_Handler               ; NMI Handler
+                DCD     rt_hw_hard_fault          ; Hard Fault Handler
+                DCD     MemManage_Handler         ; MPU Fault Handler
+                DCD     BusFault_Handler          ; Bus Fault Handler
+                DCD     UsageFault_Handler        ; Usage Fault Handler
+                DCD     0                         ; Reserved
+                DCD     0                         ; Reserved
+                DCD     0                         ; Reserved
+                DCD     0                         ; Reserved
+                DCD     SVC_Handler               ; SVCall Handler
+                DCD     DebugMon_Handler          ; Debug Monitor Handler
+                DCD     0                         ; Reserved
+                DCD     rt_hw_pend_sv             ; PendSV Handler
+                DCD     rt_hw_timer_handler       ; SysTick Handler
+
+                ; External Interrupts
+                DCD     WAKEUP_IRQHandler         ; 12 wakeup sources for all the
+                DCD     WAKEUP_IRQHandler         ; I/O pins starting from PIO0 (0:11)
+                DCD     WAKEUP_IRQHandler         ; all 40 are routed to the same ISR                       
+                DCD     WAKEUP_IRQHandler                         
+                DCD     WAKEUP_IRQHandler                        
+                DCD     WAKEUP_IRQHandler
+                DCD     WAKEUP_IRQHandler
+                DCD     WAKEUP_IRQHandler                       
+                DCD     WAKEUP_IRQHandler                         
+                DCD     WAKEUP_IRQHandler                        
+                DCD     WAKEUP_IRQHandler
+                DCD     WAKEUP_IRQHandler        
+                DCD     I2C_IRQHandler            ; I2C
+                DCD     TIMER16_0_IRQHandler      ; 16-bit Timer0
+                DCD     TIMER16_1_IRQHandler      ; 16-bit Timer1
+                DCD     TIMER32_0_IRQHandler      ; 32-bit Timer0
+                DCD     TIMER32_1_IRQHandler      ; 32-bit Timer1
+                DCD     SSP_IRQHandler            ; SSP
+                DCD     UART0_IRQHandler          ; UART0
+                DCD     UART1_IRQHandler          ; UART1
+                DCD     COMP_IRQHandler           ; Comparator
+                DCD     ADC_IRQHandler            ; A/D Converter
+                DCD     WDT_IRQHandler            ; Watchdog timer
+                DCD     BOD_IRQHandler            ; Brown Out Detect
+                DCD     FMC_IRQHandler            ; IP2111 Flash Memory Controller
+                DCD     PIOINT0_IRQHandler        ; PIO INT0
+                DCD     PIOINT1_IRQHandler        ; PIO INT1
+                DCD     PIOINT2_IRQHandler        ; PIO INT2
+                DCD     PMU_IRQHandler            ; PMU/Wakeup
+                DCD     DMA_IRQHandler            ; DMA
+                DCD     RTC_IRQHandler            ; RTC
+                DCD     EDM_IRQHandler            ; Event Driven Micro 
+
+                IF      :LNOT::DEF:NO_CRP
+                AREA    |.ARM.__at_0x02FC|, CODE, READONLY
+CRP_Key         DCD     0xFFFFFFFF
+                ENDIF
+
+
+                AREA    |.text|, CODE, READONLY
+
+
+; Reset Handler
+
+Reset_Handler   PROC
+                EXPORT  Reset_Handler             [WEAK]
+                IMPORT  __main
+                LDR     R0, =__main
+                BX      R0
+                ENDP
+
+
+; Dummy Exception Handlers (infinite loops which can be modified)                
+
+NMI_Handler     PROC
+                EXPORT  NMI_Handler               [WEAK]
+                B       .
+                ENDP
+HardFault_Handler\
+                PROC
+                EXPORT  HardFault_Handler         [WEAK]
+                B       .
+                ENDP
+MemManage_Handler\
+                PROC
+                EXPORT  MemManage_Handler         [WEAK]
+                B       .
+                ENDP
+BusFault_Handler\
+                PROC
+                EXPORT  BusFault_Handler          [WEAK]
+                B       .
+                ENDP
+UsageFault_Handler\
+                PROC
+                EXPORT  UsageFault_Handler        [WEAK]
+                B       .
+                ENDP
+SVC_Handler     PROC
+                EXPORT  SVC_Handler               [WEAK]
+                B       .
+                ENDP
+DebugMon_Handler\
+                PROC
+                EXPORT  DebugMon_Handler          [WEAK]
+                B       .
+                ENDP
+PendSV_Handler  PROC
+                EXPORT  PendSV_Handler            [WEAK]
+                B       .
+                ENDP
+SysTick_Handler PROC
+                EXPORT  SysTick_Handler           [WEAK]
+                B       .
+                ENDP
+
+Default_Handler PROC
+
+                EXPORT  NMI_Handler               [WEAK]
+                EXPORT  WAKEUP_IRQHandler         [WEAK]
+                EXPORT  I2C_IRQHandler            [WEAK]
+                EXPORT  TIMER16_0_IRQHandler      [WEAK]
+                EXPORT  TIMER16_1_IRQHandler      [WEAK]
+                EXPORT  TIMER32_0_IRQHandler      [WEAK]
+                EXPORT  TIMER32_1_IRQHandler      [WEAK]
+                EXPORT  SSP_IRQHandler            [WEAK]
+                EXPORT  UART0_IRQHandler          [WEAK]
+                EXPORT  UART1_IRQHandler          [WEAK]
+
+                EXPORT  COMP_IRQHandler           [WEAK]
+                EXPORT  ADC_IRQHandler            [WEAK]
+                EXPORT  WDT_IRQHandler            [WEAK]
+                EXPORT  BOD_IRQHandler            [WEAK]
+                EXPORT  FMC_IRQHandler            [WEAK]
+                EXPORT	PIOINT0_IRQHandler        [WEAK]
+                EXPORT	PIOINT1_IRQHandler        [WEAK]
+                EXPORT  PIOINT2_IRQHandler        [WEAK]
+                EXPORT  PMU_IRQHandler            [WEAK]
+                EXPORT  DMA_IRQHandler            [WEAK]
+                EXPORT  RTC_IRQHandler            [WEAK]
+                EXPORT  EDM_IRQHandler            [WEAK]
+
+
+WAKEUP_IRQHandler
+I2C_IRQHandler
+TIMER16_0_IRQHandler
+TIMER16_1_IRQHandler
+TIMER32_0_IRQHandler
+TIMER32_1_IRQHandler
+SSP_IRQHandler
+UART0_IRQHandler
+UART1_IRQHandler
+COMP_IRQHandler
+ADC_IRQHandler
+WDT_IRQHandler
+BOD_IRQHandler
+FMC_IRQHandler
+PIOINT0_IRQHandler  
+PIOINT1_IRQHandler 
+PIOINT2_IRQHandler
+PMU_IRQHandler
+DMA_IRQHandler
+RTC_IRQHandler
+EDM_IRQHandler
+
+                B       .
+
+                ENDP
+
+
+                ALIGN
+
+
+; User Initial Stack & Heap
+
+                IF      :DEF:__MICROLIB
+                
+                EXPORT  __initial_sp
+                EXPORT  __heap_base
+                EXPORT  __heap_limit
+                
+                ELSE
+                
+                IMPORT  __use_two_region_memory
+                EXPORT  __user_initial_stackheap
+__user_initial_stackheap
+
+                LDR     R0, =  Heap_Mem
+                LDR     R1, =(Stack_Mem + Stack_Size)
+                LDR     R2, = (Heap_Mem +  Heap_Size)
+                LDR     R3, = Stack_Mem
+                BX      LR
+
+                ALIGN
+
+                ENDIF
+
+
+                END
author	[email protected] <[email protected]>	2011-01-05 06:23:40 +0000
committer	[email protected] <[email protected]>	2011-01-05 06:23:40 +0000
commit	eb5e940df5bfe0869e2b4918e705566a90eeb6ee (patch)
tree	ba158dc89bf41933bb197ec896f8c09f617281ed /libcpu
parent	ba507951956707c8a46b75df06070980551888a8 (diff)