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author勤为本 <[email protected]>2017-07-18 17:04:32 +0800
committer勤为本 <[email protected]>2017-07-18 17:04:32 +0800
commitf39164203e4d1e19b628b43878592ff905907ae2 (patch)
tree132979d01808e6d68a41be15f9b109723bfb62ea /libcpu
parent878b222741dd2b628240d1b19401c04ae507860f (diff)
修正龙芯1c的中断号
Diffstat (limited to 'libcpu')
-rw-r--r--libcpu/mips/loongson_1c/ls1c.h61
1 files changed, 35 insertions, 26 deletions
diff --git a/libcpu/mips/loongson_1c/ls1c.h b/libcpu/mips/loongson_1c/ls1c.h
index 8b50da5ac9..c47b9a42bb 100644
--- a/libcpu/mips/loongson_1c/ls1c.h
+++ b/libcpu/mips/loongson_1c/ls1c.h
@@ -20,7 +20,7 @@
#define LS1C_ACPI_IRQ 0
#define LS1C_HPET_IRQ 1
-#define LS1C_UART0_IRQ 2
+//#define LS1C_UART0_IRQ 3 // linux����3��v1.4�汾��1c�ֲ�����2�������Σ���ȷ��
#define LS1C_UART1_IRQ 4
#define LS1C_UART2_IRQ 5
#define LS1C_CAN0_IRQ 6
@@ -32,41 +32,50 @@
#define LS1C_KB_IRQ 12
#define LS1C_DMA0_IRQ 13
#define LS1C_DMA1_IRQ 14
-#define LS1C_NAND_IRQ 15
-#define LS1C_I2C0_IRQ 16
-#define LS1C_I2C1_IRQ 17
-#define LS1C_PWM0_IRQ 18
-#define LS1C_PWM1_IRQ 19
-#define LS1C_PWM2_IRQ 20
-#define LS1C_PWM3_IRQ 21
-#define LS1C_LPC_IRQ 22
-#define LS1C_EHCI_IRQ 32
-#define LS1C_OHCI_IRQ 33
-#define LS1C_GMAC1_IRQ 34
-#define LS1C_GMAC2_IRQ 35
-#define LS1C_SATA_IRQ 36
-#define LS1C_GPU_IRQ 37
-#define LS1C_PCI_INTA_IRQ 38
-#define LS1C_PCI_INTB_IRQ 39
-#define LS1C_PCI_INTC_IRQ 40
-#define LS1C_PCI_INTD_IRQ 41
+#define LS1C_DMA2_IRQ 15
+#define LS1C_NAND_IRQ 16
+#define LS1C_PWM0_IRQ 17
+#define LS1C_PWM1_IRQ 18
+#define LS1C_PWM2_IRQ 19
+#define LS1C_PWM3_IRQ 20
+#define LS1C_RTC_INT0_IRQ 21
+#define LS1C_RTC_INT1_IRQ 22
+#define LS1C_RTC_INT2_IRQ 23
+#define LS1C_UART3_IRQ 29
+#define LS1C_ADC_IRQ 30
+#define LS1C_SDIO_IRQ 31
+
+
+#define LS1C_EHCI_IRQ (32+0)
+#define LS1C_OHCI_IRQ (32+1)
+#define LS1C_OTG_IRQ (32+2)
+#define LS1C_MAC_IRQ (32+3)
+#define LS1C_CAM_IRQ (32+4)
+#define LS1C_UART4_IRQ (32+5)
+#define LS1C_UART5_IRQ (32+6)
+#define LS1C_UART6_IRQ (32+7)
+#define LS1C_UART7_IRQ (32+8)
+#define LS1C_UART8_IRQ (32+9)
+#define LS1C_UART9_IRQ (32+13)
+#define LS1C_UART10_IRQ (32+14)
+#define LS1C_UART11_IRQ (32+15)
+#define LS1C_I2C2_IRQ (32+17)
+#define LS1C_I2C1_IRQ (32+18)
+#define LS1C_I2C0_IRQ (32+19)
+
#define LS1C_GPIO_IRQ 64
#define LS1C_GPIO_FIRST_IRQ 64
#define LS1C_GPIO_IRQ_COUNT 96
#define LS1C_GPIO_LAST_IRQ (LS1C_GPIO_FIRST_IRQ + LS1C_GPIO_IRQ_COUNT-1)
-#define INT_PCI_INTA (1<<6)
-#define INT_PCI_INTB (1<<7)
-#define INT_PCI_INTC (1<<8)
-#define INT_PCI_INTD (1<<9)
#define LS1C_LAST_IRQ 159
-#define MIPS_CPU_TIMER_IRQ 167
#define LS1C_INTREG_BASE 0xbfd01040
-#define LS1C_DMA_IRQ_BASE 168
-#define LS1C_DMA_IRQ_COUNT 16
+// ��о1c���жϷ�Ϊ���飬ÿ��32��
+#define LS1C_NR_IRQS (32*5)
+
struct ls1c_intc_regs
{