diff options
| author | Shell <[email protected]> | 2024-03-28 23:32:05 +0800 |
|---|---|---|
| committer | Meco Man <[email protected]> | 2024-04-16 22:31:47 -0400 |
| commit | f4c7d4630095f18710550e89165bfa37f7bd4aa7 (patch) | |
| tree | 2e1c13db2418304a75be63c2ee067ac3e0812af9 /libcpu | |
| parent | 8881f0eea17229affb031205f90dc1007194d61b (diff) | |
[libcpu/aarch64] improve performance of IRQ dis/en-able (#8687)
Signed-off-by: Shell <[email protected]>
Diffstat (limited to 'libcpu')
| -rw-r--r-- | libcpu/aarch64/common/context_gcc.S | 14 |
1 files changed, 13 insertions, 1 deletions
diff --git a/libcpu/aarch64/common/context_gcc.S b/libcpu/aarch64/common/context_gcc.S index bbd7e72371..39a516dc59 100644 --- a/libcpu/aarch64/common/context_gcc.S +++ b/libcpu/aarch64/common/context_gcc.S @@ -314,6 +314,12 @@ rt_hw_interrupt_is_disabled: .globl rt_hw_interrupt_disable rt_hw_interrupt_disable: MRS X0, DAIF + AND X0, X0, #0xc0 + CMP X0, #0xc0 + /* branch if bits not both set(zero) */ + BNE 1f + RET +1: MSR DAIFSet, #3 DSB NSH ISB @@ -324,6 +330,12 @@ rt_hw_interrupt_disable: */ .globl rt_hw_interrupt_enable rt_hw_interrupt_enable: + AND X0, X0, #0xc0 + CMP X0, #0xc0 + /* branch if one of the bits not set(zero) */ + BNE 1f + RET +1: ISB DSB NSH AND X0, X0, #0xc0 @@ -439,7 +451,7 @@ rt_hw_context_switch_exit: MOV X0, SP RESTORE_CONTEXT -#else /* RT_USING_SMP */ +#else /* !RT_USING_SMP */ /* * void rt_hw_context_switch_to(rt_ubase_t to); |