diff options
| author | [email protected] <[email protected]> | 2010-10-15 23:40:44 +0000 |
|---|---|---|
| committer | [email protected] <[email protected]> | 2010-10-15 23:40:44 +0000 |
| commit | 67eff19969ec715ce8dd7465f6cb0baf94b03323 (patch) | |
| tree | 22d07358356e106fb229b038f0595daaa4af6ad2 /libcpu | |
| parent | 0395886e11624982aac4c103733ff95e86148559 (diff) | |
add init loongson soc3210 porting.
git-svn-id: https://rt-thread.googlecode.com/svn/trunk@1012 bbd45198-f89e-11dd-88c7-29a3b14d5316
Diffstat (limited to 'libcpu')
| -rw-r--r-- | libcpu/SConscript | 2 | ||||
| -rw-r--r-- | libcpu/mips/common/exception.h | 4 | ||||
| -rw-r--r-- | libcpu/mips/common/mips.inc | 27 | ||||
| -rw-r--r-- | libcpu/mips/loongson/cache.c | 188 | ||||
| -rw-r--r-- | libcpu/mips/loongson/cache.h | 47 | ||||
| -rw-r--r-- | libcpu/mips/loongson/cache_gcc.S | 202 | ||||
| -rw-r--r-- | libcpu/mips/loongson/context_gcc.S | 141 | ||||
| -rw-r--r-- | libcpu/mips/loongson/cpu.c | 49 | ||||
| -rw-r--r-- | libcpu/mips/loongson/exception.c | 83 | ||||
| -rw-r--r-- | libcpu/mips/loongson/interrupt.c | 129 | ||||
| -rw-r--r-- | libcpu/mips/loongson/mipscfg.c | 82 | ||||
| -rw-r--r-- | libcpu/mips/loongson/soc3210.h | 172 | ||||
| -rw-r--r-- | libcpu/mips/loongson/stack.c | 94 | ||||
| -rw-r--r-- | libcpu/mips/loongson/start_gcc.S | 132 |
14 files changed, 1335 insertions, 17 deletions
diff --git a/libcpu/SConscript b/libcpu/SConscript index 19487d7f81..bd854aa5f7 100644 --- a/libcpu/SConscript +++ b/libcpu/SConscript @@ -21,7 +21,7 @@ group = {} group['name'] = rtconfig.CPU.upper() group['src'] = File(src_local) group['CCFLAGS'] = '' -group['CPPPATH'] = [RTT_ROOT + '/libcpu/' + rtconfig.ARCH + '/' + rtconfig.CPU] +group['CPPPATH'] = [RTT_ROOT + '/libcpu/' + rtconfig.ARCH + '/' + rtconfig.CPU, RTT_ROOT + '/libcpu/' + rtconfig.ARCH + '/common'] group['CPPDEFINES'] = '' group['LINKFLAGS'] = '' diff --git a/libcpu/mips/common/exception.h b/libcpu/mips/common/exception.h index 07ffcd7a29..cd776a77cb 100644 --- a/libcpu/mips/common/exception.h +++ b/libcpu/mips/common/exception.h @@ -140,8 +140,6 @@ #define GDB_FR_SIZE ((((GDB_FR_CP0_PRID) + LONGSIZE) + (PTRSIZE-1)) & ~(PTRSIZE-1))
-
-
/*
* This is the same as above, but for the high-level
* part of the INT stub.
@@ -161,7 +159,7 @@ typedef struct pt_regs_s typedef void (* exception_func_t)(pt_regs_t *regs);
-extern exception_func_t sys_exception_handlers[33];
+extern exception_func_t sys_exception_handlers[];
exception_func_t rt_set_except_vector(int n, exception_func_t func);
void install_default_execpt_handle(void);
diff --git a/libcpu/mips/common/mips.inc b/libcpu/mips/common/mips.inc index 59388fd7f1..c1e3e2d418 100644 --- a/libcpu/mips/common/mips.inc +++ b/libcpu/mips/common/mips.inc @@ -14,15 +14,15 @@ #ifndef __MIPS_INC__
#define __MIPS_INC__
-#define zero $0
-#define at $1
-#define v0 $2
+#define zero $0 /* wired zero */
+// #define at $1
+#define v0 $2 /* return value */
#define v1 $3
-#define a0 $4
+#define a0 $4 /* argument registers */
#define a1 $5
#define a2 $6
#define a3 $7
-#define t0 $8
+#define t0 $8 /* caller saved */
#define t1 $9
#define t2 $10
#define t3 $11
@@ -30,7 +30,7 @@ #define t5 $13
#define t6 $14
#define t7 $15
-#define s0 $16
+#define s0 $16 /* callee saved */
#define s1 $17
#define s2 $18
#define s3 $19
@@ -38,14 +38,15 @@ #define s5 $21
#define s6 $22
#define s7 $23
-#define t8 $24
+#define t8 $24 /* caller saved */
#define t9 $25
-#define k0 $26
+#define jp $25 /* PIC jump register */
+#define k0 $26 /* kernel scratch */
#define k1 $27
-#define gp $28
-#define sp $29
-#define fp $30
-#define ra $31
-
+#define gp $28 /* global pointer */
+#define sp $29 /* stack pointer */
+#define fp $30 /* frame pointer */
+#define s8 $30 /* same like fp! */
+#define ra $31 /* return address */
#endif /* end of __MIPS_INC__ */
diff --git a/libcpu/mips/loongson/cache.c b/libcpu/mips/loongson/cache.c new file mode 100644 index 0000000000..bca01a61f4 --- /dev/null +++ b/libcpu/mips/loongson/cache.c @@ -0,0 +1,188 @@ +#include "../common/mipsregs.h"
+#include "cache.h"
+
+#define K0BASE 0x80000000
+#define PRID_3210I 0x4200
+
+typedef struct cacheinfo_t {
+ unsigned int icache_size;
+ unsigned int dcache_size;
+ unsigned int icacheline_size;
+ unsigned int dcacheline_size;
+} cacheinfo_t ;
+
+typedef struct cacheop_t {
+ void (*Clear_TagLo) (void);
+ void (*Invalidate_Icache) (unsigned int);
+ void (*Invalidate_Dcache_Fill) (unsigned int);
+ void (*Invalidate_Dcache_ClearTag) (unsigned int);
+ void (*Init_Cache)(void);
+} cacheop_t ;
+
+static cacheop_t cacheop, *pcacheop;
+static cacheinfo_t cacheinfo, *pcacheinfo;
+
+int identify_cpu (void)
+{
+ unsigned int cpu_id;
+ void invalidate_cache (void);
+
+ pcacheop = &cacheop;
+ pcacheinfo = &cacheinfo;
+
+ rt_kprintf("CPU configure: 0x%08x\n", read_c0_config());
+ cpu_id = read_c0_prid();
+ switch (cpu_id)
+ {
+ case PRID_3210I:
+ rt_kprintf ("CPU:SoC3210\n");
+ pcacheop->Clear_TagLo = Clear_TagLo;
+ pcacheop->Invalidate_Icache = Invalidate_Icache_Gc3210I;
+ pcacheop->Invalidate_Dcache_Fill = Invalidate_Dcache_Fill_Gc3210I;
+ pcacheop->Invalidate_Dcache_ClearTag = Invalidate_Dcache_ClearTag_Gc3210I;
+ break;
+ default:
+ rt_kprintf ("Unknown CPU type, system halted!\n");
+ while (1) {}
+ break;
+ }
+
+ return 0;
+}
+
+void probe_cache(void)
+{
+ unsigned int config = read_c0_config ();
+ unsigned int icache_size, ic_lsize;
+ unsigned int dcache_size, dc_lsize;
+
+ icache_size = 1 << (12 + ((config >> 9) & 7));
+ dcache_size = 1 << (12 + ((config >> 6) & 7));
+ ic_lsize = 16 << ((config >> 5) & 1);
+ dc_lsize = 16 << ((config >> 4) & 1);
+
+ rt_kprintf("DCache %2dkb, linesize %d bytes.\n",
+ dcache_size >> 10, dc_lsize);
+ rt_kprintf("ICache %2dkb, linesize %d bytes.\n",
+ icache_size >> 10, ic_lsize);
+
+ pcacheinfo->icache_size = icache_size;
+ pcacheinfo->dcache_size = dcache_size;
+ pcacheinfo->icacheline_size = ic_lsize;
+ pcacheinfo->dcacheline_size = dc_lsize;
+
+ return ;
+}
+
+void invalidate_writeback_dcache_all(void)
+{
+ unsigned int start = K0BASE;
+ unsigned int end = (start + pcacheinfo->dcache_size);
+
+ start = K0BASE;
+ while(start < end) {
+ Writeback_Invalidate_Dcache(start); //hit writeback invalidate
+ start += pcacheinfo->dcacheline_size;
+ }
+}
+
+void invalidate_writeback_dcache(unsigned long addr, int size)
+{
+ unsigned long start, end;
+
+ start = (addr +pcacheinfo->dcacheline_size -1) & (- pcacheinfo->dcacheline_size);
+ end = (end + size + pcacheinfo->dcacheline_size -1) & ( -pcacheinfo->dcacheline_size);
+
+ while(start <end){
+ Writeback_Invalidate_Dcache(start);
+ start += pcacheinfo->dcacheline_size;
+ }
+}
+
+
+void invalidate_icache_all(void)
+{
+ unsigned int start = K0BASE;
+ unsigned int end = (start + pcacheinfo->icache_size);
+
+ while(start < end) {
+ pcacheop->Invalidate_Icache(start);
+ start += pcacheinfo->icacheline_size;
+ }
+}
+
+void invalidate_dcache_all()
+{
+ unsigned int start = K0BASE;
+ unsigned int end = (start + pcacheinfo->dcache_size);
+ while(start <end){
+ Invalidate_Dcache_Fill_Gc3210I(start);
+ start += pcacheinfo->icacheline_size;
+ }
+}
+
+//with cache disabled
+void init_dcache(void)
+{
+ unsigned int start = K0BASE;
+ unsigned int end = (start + pcacheinfo->dcache_size);
+
+ while(start < end){
+ pcacheop->Invalidate_Dcache_ClearTag(start);
+ start += pcacheinfo->dcacheline_size;
+ }
+
+}
+
+void rt_hw_cache_init(void)
+{
+ unsigned int start, end;
+
+ /* 1. identify cpu and probe cache */
+ identify_cpu();
+ probe_cache();
+
+ start = K0BASE;
+ end = (start + pcacheinfo->icache_size);
+
+ /*
+ * 2. clear CP0 taglo/taghi register;
+ */
+ pcacheop->Clear_TagLo();
+
+ /*
+ * 3. invalidate instruction cache;
+ */
+ while(start < end) {
+ pcacheop->Invalidate_Icache(start); //index invalidate icache
+ start += pcacheinfo->icacheline_size;
+ }
+
+ /*
+ * 4. invalidate data cache;
+ */
+ start = K0BASE;
+ end = (start + pcacheinfo->dcache_size);
+ while(start < end) {
+ pcacheop->Invalidate_Dcache_ClearTag(start);
+ start += pcacheinfo->dcacheline_size;
+ }
+
+ start = K0BASE;
+ while(start < end) {
+ pcacheop->Invalidate_Dcache_Fill(start); //index invalidate dcache
+ start += pcacheinfo->dcacheline_size;
+ }
+
+ start = K0BASE;
+ while(start < end) {
+ pcacheop->Invalidate_Dcache_ClearTag(start);
+ start += pcacheinfo->dcacheline_size;
+ }
+
+ /* enable cache */
+ enable_cpu_cache();
+ rt_kprintf("enable cpu cache done\n");
+
+ return ;
+}
diff --git a/libcpu/mips/loongson/cache.h b/libcpu/mips/loongson/cache.h new file mode 100644 index 0000000000..fb4899a6b2 --- /dev/null +++ b/libcpu/mips/loongson/cache.h @@ -0,0 +1,47 @@ +#ifndef __CACHE_H__
+#define __CACHE_H__
+
+/*
+ * Cache Operations
+ */
+#define Index_Invalidate_I 0x00
+#define Index_Writeback_Inv_D 0x01
+#define Index_Invalidate_SI 0x02
+#define Index_Writeback_Inv_SD 0x03
+#define Index_Load_Tag_I 0x04
+#define Index_Load_Tag_D 0x05
+#define Index_Load_Tag_SI 0x06
+#define Index_Load_Tag_SD 0x07
+#define Index_Store_Tag_I 0x08
+#define Index_Store_Tag_D 0x09
+#define Index_Store_Tag_SI 0x0A
+#define Index_Store_Tag_SD 0x0B
+#define Create_Dirty_Excl_D 0x0d
+#define Create_Dirty_Excl_SD 0x0f
+#define Hit_Invalidate_I 0x10
+#define Hit_Invalidate_D 0x11
+#define Hit_Invalidate_SI 0x12
+#define Hit_Invalidate_SD 0x13
+#define Fill 0x14
+#define Hit_Writeback_Inv_D 0x15
+/* 0x16 is unused */
+#define Hit_Writeback_Inv_SD 0x17
+#define Hit_Writeback_I 0x18
+#define Hit_Writeback_D 0x19
+/* 0x1a is unused */
+#define Hit_Writeback_SD 0x1b
+/* 0x1c is unused */
+/* 0x1e is unused */
+#define Hit_Set_Virtual_SI 0x1e
+#define Hit_Set_Virtual_SD 0x1f
+
+extern void Clear_TagLo (void);
+
+extern void Invalidate_Icache_Gc3210I (unsigned int);
+extern void Invalidate_Dcache_ClearTag_Gc3210I (unsigned int);
+extern void Invalidate_Dcache_Fill_Gc3210I(unsigned int);
+extern void Writeback_Invalidate_Dcache(unsigned int);
+
+void rt_hw_cache_init(void);
+
+#endif
diff --git a/libcpu/mips/loongson/cache_gcc.S b/libcpu/mips/loongson/cache_gcc.S new file mode 100644 index 0000000000..00fd861eec --- /dev/null +++ b/libcpu/mips/loongson/cache_gcc.S @@ -0,0 +1,202 @@ +#include "../common/mipsregs.h" +#include "../common/mips.inc" +#include "../common/asm.h" +#include "cache.inc" + + .ent cache_init + .global cache_init + .set noreorder +cache_init: + move t1,ra +####part 2#### +cache_detect_4way: + mfc0 t4, CP0_CONFIG + andi t5, t4, 0x0e00 + srl t5, t5, 9 #ic + andi t6, t4, 0x01c0 + srl t6, t6, 6 #dc + addiu t8, $0, 1 + addiu t9, $0, 2 + #set dcache way + beq t6, $0, cache_d1way + addiu t7, $0, 1 #1 way + beq t6, t8, cache_d2way + addiu t7, $0, 2 #2 way + beq $0, $0, cache_d4way + addiu t7, $0, 4 #4 way +cache_d1way: + beq $0, $0, 1f + addiu t6, t6, 12 #1 way +cache_d2way: + beq $0, $0, 1f + addiu t6, t6, 11 #2 way +cache_d4way: + addiu t6, t6, 10 #4 way (10), 2 way(11), 1 way(12) +1: #set icache way + beq t5, $0, cache_i1way + addiu t3, $0, 1 #1 way + beq t5, t8, cache_i2way + addiu t3, $0, 2 #2 way + beq $0, $0, cache_i4way + addiu t3, $0, 4 #4 way +cache_i1way: + beq $0, $0, 1f + addiu t5, t5, 12 +cache_i2way: + beq $0, $0, 1f + addiu t5, t5, 11 +cache_i4way: + addiu t5, t5, 10 #4 way (10), 2 way(11), 1 way(12) + +1: addiu t4, $0, 1 + sllv t6, t4, t6 + sllv t5, t4, t5 +#if 0 + la t0, memvar + sw t7, 0x0(t0) #ways + sw t5, 0x4(t0) #icache size + sw t6, 0x8(t0) #dcache size +#endif +####part 3#### + .set mips3 + lui a0, 0x8000 + addu a1, $0, t5 + addu a2, $0, t6 +cache_init_d2way: +#a0=0x80000000, a1=icache_size, a2=dcache_size +#a3, v0 and v1 used as local registers + mtc0 $0, CP0_TAGHI + addu v0, $0, a0 + addu v1, a0, a2 +1: slt a3, v0, v1 + beq a3, $0, 1f + nop + mtc0 $0, CP0_TAGLO + beq t7, 1, 4f + cache Index_Store_Tag_D, 0x0(v0) # 1 way + beq t7, 2 ,4f + cache Index_Store_Tag_D, 0x1(v0) # 2 way + cache Index_Store_Tag_D, 0x2(v0) # 4 way + cache Index_Store_Tag_D, 0x3(v0) +4: beq $0, $0, 1b + addiu v0, v0, 0x20 +1: +cache_flush_i2way: + addu v0, $0, a0 + addu v1, a0, a1 +1: slt a3, v0, v1 + beq a3, $0, 1f + nop + beq t3, 1, 4f + cache Index_Invalidate_I, 0x0(v0) # 1 way + beq t3, 2, 4f + cache Index_Invalidate_I, 0x1(v0) # 2 way + cache Index_Invalidate_I, 0x2(v0) + cache Index_Invalidate_I, 0x3(v0) # 4 way +4: beq $0, $0, 1b + addiu v0, v0, 0x20 +1: +cache_flush_d2way: + addu v0, $0, a0 + addu v1, a0, a2 +1: slt a3, v0, v1 + beq a3, $0, 1f + nop + beq t7, 1, 4f + cache Index_Writeback_Inv_D, 0x0(v0) #1 way + beq t7, 2, 4f + cache Index_Writeback_Inv_D, 0x1(v0) # 2 way + cache Index_Writeback_Inv_D, 0x2(v0) + cache Index_Writeback_Inv_D, 0x3(v0) # 4 way +4: beq $0, $0, 1b + addiu v0, v0, 0x20 +1: +cache_init_finish: + jr t1 + nop + .set reorder + .end cache_init + +########################### +# Enable CPU cache # +########################### + +LEAF(enable_cpu_cache) + .set noreorder + mfc0 t0, CP0_CONFIG + nop + and t0, ~0x03 + or t0, 0x03 + mtc0 t0, CP0_CONFIG + nop + .set reorder + j ra +END (enable_cpu_cache) + +########################### +# disable CPU cache # +########################### + +LEAF(disable_cpu_cache) + .set noreorder + mfc0 t0, CP0_CONFIG + nop + and t0, ~0x03 + or t0, 0x2 + mtc0 t0, CP0_CONFIG + nop + .set reorder + j ra +END (disable_cpu_cache) + +/**********************************/ +/* Invalidate Instruction Cache */ +/**********************************/ +LEAF(Clear_TagLo) + .set noreorder + mtc0 zero, CP0_TAGLO + nop + .set reorder + j ra +END(Clear_TagLo) + + .set mips3 +/**********************************/ +/* Invalidate Instruction Cache */ +/**********************************/ +LEAF(Invalidate_Icache_Gc3210I) + .set noreorder + cache Index_Invalidate_I,0(a0) + cache Index_Invalidate_I,1(a0) + cache Index_Invalidate_I,2(a0) + cache Index_Invalidate_I,3(a0) + .set reorder + j ra +END(Invalidate_Icache_Gc3210I) + +/**********************************/ +/* Invalidate Data Cache */ +/**********************************/ +LEAF(Invalidate_Dcache_ClearTag_Gc3210I) + .set noreorder + cache Index_Store_Tag_D, 0(a0) # BDSLOT: clear tag + cache Index_Store_Tag_D, 1(a0) # BDSLOT: clear tag + .set reorder + j ra +END(Invalidate_Dcache_ClearTag_Gc3210I) + +LEAF(Invalidate_Dcache_Fill_Gc3210I) + .set noreorder + cache Index_Writeback_Inv_D, 0(a0) # BDSLOT: clear tag + cache Index_Writeback_Inv_D, 1(a0) # BDSLOT: clear tag + .set reorder + j ra +END(Invalidate_Dcache_Fill_Gc3210I) + +LEAF(Writeback_Invalidate_Dcache) + .set noreorder + cache Hit_Writeback_Inv_D, (a0) + .set reorder + j ra +END(Writeback_Invalidate_Dcache) + .set mips0 diff --git a/libcpu/mips/loongson/context_gcc.S b/libcpu/mips/loongson/context_gcc.S new file mode 100644 index 0000000000..1611f1cd86 --- /dev/null +++ b/libcpu/mips/loongson/context_gcc.S @@ -0,0 +1,141 @@ +/*
+ * File : context_gcc.S
+ * Change Logs:
+ * Date Author Notes
+ * 2010-05-17 swkyer first version
+ * 2010-09-11 bernard port to Loongson SoC3210
+ */
+#include "../common/mips.inc"
+#include "../common/stackframe.h"
+#include "soc3210.h"
+
+ .section ".text", "ax"
+ .set noreorder
+
+/*
+ * rt_base_t rt_hw_interrupt_disable()
+ */
+ .globl rt_hw_interrupt_disable
+rt_hw_interrupt_disable:
+ mfc0 v0, CP0_STATUS
+ and v1, v0, 0xfffffffe
+ mtc0 v1, CP0_STATUS
+ jr ra
+ nop
+
+/*
+ * void rt_hw_interrupt_enable(rt_base_t level)
+ */
+ .globl rt_hw_interrupt_enable
+rt_hw_interrupt_enable:
+ mtc0 a0, CP0_STATUS
+ jr ra
+ nop
+
+/*
+ * void rt_hw_context_switch(rt_uint32 from, rt_uint32 to)
+ * a0 --> from
+ * a1 --> to
+ */
+ .globl rt_hw_context_switch
+rt_hw_context_switch:
+ mtc0 ra, CP0_EPC
+ SAVE_ALL
+
+ sw sp, 0(a0) /* store sp in preempted tasks TCB */
+ lw sp, 0(a1) /* get new task stack pointer */
+
+ RESTORE_ALL_AND_RET
+
+/*
+ * void rt_hw_context_switch_to(rt_uint32 to)/*
+ * a0 --> to
+ */
+ .globl rt_hw_context_switch_to
+rt_hw_context_switch_to:
+ lw sp, 0(a0) /* get new task stack pointer */
+
+ RESTORE_ALL_AND_RET
+
+/*
+ * void rt_hw_context_switch_interrupt(rt_uint32 from, rt_uint32 to)/*
+ */
+ .globl rt_thread_switch_interrput_flag
+ .globl rt_interrupt_from_thread
+ .globl rt_interrupt_to_thread
+ .globl rt_hw_context_switch_interrupt
+rt_hw_context_switch_interrupt:
+ la t0, rt_thread_switch_interrput_flag
+ lw t1, 0(t0)
+ nop
+ bnez t1, _reswitch
+ nop
+ li t1, 0x01 /* set rt_thread_switch_interrput_flag to 1 */
+ sw t1, 0(t0)
+ la t0, rt_interrupt_from_thread /* set rt_interrupt_from_thread */
+ sw a0, 0(t0)
+_reswitch:
+ la t0, rt_interrupt_to_thread /* set rt_interrupt_to_thread */
+ sw a1, 0(t0)
+ jr ra
+ nop
+
+/*
+ * void rt_hw_context_switch_interrupt_do(rt_base_t flag)
+ */
+ .globl rt_interrupt_enter
+ .globl rt_interrupt_leave
+ .globl mips_irq_handle
+mips_irq_handle:
+ SAVE_ALL
+
+ mfc0 t0, CP0_CAUSE
+ and t1, t0, 0xff
+ bnez t1, spurious_interrupt /* check exception */
+ nop
+
+ /* let k0 keep the current context sp */
+ move k0, sp
+ /* switch to kernel stack */
+ li sp, SYSTEM_STACK
+
+ jal rt_interrupt_enter
+ nop
+ jal rt_interrupt_dispatch
+ nop
+ jal rt_interrupt_leave
+ nop
+
+ /* switch sp back to thread's context */
+ move sp, k0
+
+ /*
+ * if rt_thread_switch_interrput_flag set, jump to
+ * rt_hw_context_switch_interrupt_do and don't return
+ */
+ la k0, rt_thread_switch_interrput_flag
+ lw k1, 0(k0)
+ beqz k1, spurious_interrupt
+ nop
+ sw zero, 0(k0) /* clear flag */
+ nop
+
+ /*
+ * switch to the new thread
+ */
+ la k0, rt_interrupt_from_thread
+ lw k1, 0(k0)
+ nop
+ sw sp, 0(k1) /* store sp in preempted tasks's TCB */
+
+ la k0, rt_interrupt_to_thread
+ lw k1, 0(k0)
+ nop
+ lw sp, 0(k1) /* get new task's stack pointer */
+ j spurious_interrupt
+ nop
+
+spurious_interrupt:
+ RESTORE_ALL_AND_RET
+
+ .set reorder
diff --git a/libcpu/mips/loongson/cpu.c b/libcpu/mips/loongson/cpu.c new file mode 100644 index 0000000000..06673bcbb9 --- /dev/null +++ b/libcpu/mips/loongson/cpu.c @@ -0,0 +1,49 @@ +/*
+ * File : cpu.c
+ * This file is part of RT-Thread RTOS
+ * COPYRIGHT (C) 2006 - 2010, RT-Thread Development Team
+ *
+ * The license and distribution terms for this file may be
+ * found in the file LICENSE in this distribution or at
+ * http://www.rt-thread.org/license/LICENSE
+ *
+ * Change Logs:
+ * Date Author Notes
+ * 2010-07-09 Bernard first version
+ * 2010-09-11 Bernard add CPU reset implementation
+ */
+#include <rtthread.h>
+#include <soc3210.h>
+
+/**
+ * @addtogroup Loogonson SoC3210
+ */
+/*@{*/
+
+/**
+ * this function will reset CPU
+ *
+ */
+void rt_hw_cpu_reset()
+{
+ /* open the watch-dog */
+ WD_TIMER = 0x01; /* watch dog will be timeout after 1 tick */
+ WD_CTRL |= 0x01;
+
+ rt_kprintf("reboot system...\n");
+ while (1);
+}
+
+/**
+ * this function will shutdown CPU
+ *
+ */
+void rt_hw_cpu_shutdown()
+{
+ rt_kprintf("shutdown...\n");
+
+ while (1);
+}
+
+/*@}*/
+
diff --git a/libcpu/mips/loongson/exception.c b/libcpu/mips/loongson/exception.c new file mode 100644 index 0000000000..77d1414a29 --- /dev/null +++ b/libcpu/mips/loongson/exception.c @@ -0,0 +1,83 @@ +/*
+ * File : exception.c
+ * Change Logs:
+ * Date Author Notes
+ * 2010-05-17 swkyer first version
+ */
+#include <rtthread.h>
+#include <rthw.h>
+#include "../common/exception.h"
+#include "../common/mipsregs.h"
+
+/**
+ * @addtogroup SoC3210
+ */
+/*@{*/
+
+/**
+ * exception handle table
+ */
+#define RT_EXCEPTION_MAX 8
+exception_func_t sys_exception_handlers[RT_EXCEPTION_MAX];
+
+/**
+ * setup the exception handle
+ */
+exception_func_t rt_set_except_vector(int n, exception_func_t func)
+{
+ exception_func_t old_handler = sys_exception_handlers[n];
+
+ if ((n == 0) || (n > RT_EXCEPTION_MAX) || (!func))
+ {
+ return 0;
+ }
+
+ sys_exception_handlers[n] = func;
+
+ return old_handler;
+}
+
+void tlb_refill_handler(void)
+{
+ rt_kprintf("tlb-miss happens, epc: 0x%08x\n", read_c0_epc());
+ rt_hw_cpu_shutdown();
+}
+
+void cache_error_handler(void)
+{
+ rt_kprintf("cache exception happens, epc: 0x%08x\n", read_c0_epc());
+ rt_hw_cpu_shutdown();
+}
+
+static void unhandled_exception_handle(pt_regs_t *regs)
+{
+ rt_kprintf("exception happens, epc: 0x%08x, cause: 0x%08x\n", regs->cp0_epc, read_c0_cause());
+}
+
+void install_default_execpt_handle(void)
+{
+ rt_int32_t i;
+
+ for (i=0; i<RT_EXCEPTION_MAX; i++)
+ sys_exception_handlers[i] = (exception_func_t)unhandled_exception_handle;
+}
+
+void exception_handler(pt_regs_t *regs)
+{
+ rt_uint32_t cause;
+ rt_uint32_t index;
+
+ cause = (read_c0_cause() & read_c0_config());
+ cause = (cause & 0xfc00) >> 8;
+
+ for (index = RT_EXCEPTION_MAX; index > 0; index --)
+ {
+ if (cause & (1 << index))
+ {
+ sys_exception_handlers[index](regs);
+ cause &= ~(1 << index);
+ }
+ }
+}
+
+/*@}*/
diff --git a/libcpu/mips/loongson/interrupt.c b/libcpu/mips/loongson/interrupt.c new file mode 100644 index 0000000000..2d354269aa --- /dev/null +++ b/libcpu/mips/loongson/interrupt.c @@ -0,0 +1,129 @@ +/*
+ * File : interrupt.c
+ * This file is part of RT-Thread RTOS
+ * COPYRIGHT (C) 2006 - 2010, RT-Thread Development Team
+ *
+ * The license and distribution terms for this file may be
+ * found in the file LICENSE in this distribution or at
+ * http://www.rt-thread.org/license/LICENSE
+ *
+ * Change Logs:
+ * Date Author Notes
+ * 2010-10-15 Bernard first version
+ */
+#include <rtthread.h>
+#include "soc3210.h"
+
+#define MAX_INTR 32
+
+extern rt_uint32_t rt_interrupt_nest;
+rt_uint32_t rt_interrupt_from_thread, rt_interrupt_to_thread;
+rt_uint32_t rt_thread_switch_interrput_flag;
+
+static rt_isr_handler_t irq_handle_table[MAX_INTR];
+void rt_interrupt_dispatch(void *ptreg);
+void rt_hw_timer_handler();
+
+/**
+ * @addtogroup Loogonson SoC3210
+ */
+/*@{*/
+
+void rt_hw_interrupt_handler(int vector)
+{
+ rt_kprintf("Unhandled interrupt %d occured!!!\n", vector);
+}
+
+/**
+ * This function will initialize hardware interrupt
+ */
+void rt_hw_interrupt_init()
+{
+ rt_int32_t index;
+
+ for (index = 0; index < MAX_INTR; index ++)
+ {
+ irq_handle_table[index] = (rt_isr_handler_t)rt_hw_interrupt_handler;
+ }
+
+ /* init interrupt nest, and context in thread sp */
+ rt_interrupt_nest = 0;
+ rt_interrupt_from_thread = 0;
+ rt_interrupt_to_thread = 0;
+ rt_thread_switch_interrput_flag = 0;
+}
+
+/**
+ * This function will mask a interrupt.
+ * @param vector the interrupt number
+ */
+void rt_hw_interrupt_mask(int vector)
+{
+ /* mask interrupt */
+ INT_EN &= ~(1 << vector);
+}
+
+/**
+ * This function will un-mask a interrupt.
+ * @param vector the interrupt number
+ */
+void rt_hw_interrupt_umask(int vector)
+{
+ INT_EN |= (1 << vector);
+}
+
+/**
+ * This function will install a interrupt service routine to a interrupt.
+ * @param vector the interrupt number
+ * @param new_handler the interrupt service routine to be installed
+ * @param old_handler the old interrupt service routine
+ */
+void rt_hw_interrupt_install(int vector, rt_isr_handler_t new_handler, rt_isr_handler_t *old_handler)
+{
+ if (vector >= 0 && vector < MAX_INTR)
+ {
+ if (old_handler != RT_NULL)
+ *old_handler = irq_handle_table[vector];
+ if (new_handler != RT_NULL)
+ irq_handle_table[vector] = (rt_isr_handler_t)new_handler;
+ }
+}
+
+void rt_interrupt_dispatch(void *ptreg)
+{
+ int i;
+ rt_isr_handler_t irq_func;
+ static rt_uint32_t status = 0;
+ rt_uint32_t c0_status;
+
+ /* check os timer */
+ c0_status = read_c0_status();
+ if (c0_status & 0x8000)
+ {
+ rt_hw_timer_handler();
+ }
+
+ if (c0_status & 0x0400)
+ {
+ /* the hardware interrupt */
+ status |= INT_ISR;
+ if (!status) return;
+
+ for (i = MAX_INTR; i > 0; --i)
+ {
+ if ((status & (1<<i)))
+ {
+ status &= ~(1<<i);
+ irq_func = irq_handle_table[i];
+
+ /* do interrupt */
+ (*irq_func)(i);
+
+ /* ack interrupt */
+ INT_CLR = (1 << i);
+ }
+ }
+ }
+}
+
+/*@}*/
diff --git a/libcpu/mips/loongson/mipscfg.c b/libcpu/mips/loongson/mipscfg.c new file mode 100644 index 0000000000..89bb321c8c --- /dev/null +++ b/libcpu/mips/loongson/mipscfg.c @@ -0,0 +1,82 @@ +/*
+ * File : mipscfg.c
+ * This file is part of RT-Thread RTOS
+ * COPYRIGHT (C) 2010, RT-Thread Development Team
+ *
+ * The license and distribution terms for this file may be
+ * found in the file LICENSE in this distribution or at
+ * http://www.rt-thread.org/license/LICENSE
+ *
+ * Change Logs:
+ * Date Author Notes
+ * 2010-05-27 swkyer first version
+ */
+#include <rtthread.h>
+#include "../common/mipsregs.h"
+#include "../common/mipscfg.h"
+
+mips32_core_cfg_t g_mips_core =
+{
+ 16, /* icache_line_size */
+ 256, /* icache_lines_per_way */
+ 4, /* icache_ways */
+ 16, /* dcache_line_size */
+ 256, /* dcache_lines_per_way */
+ 4, /* dcache_ways */
+ 16, /* max_tlb_entries */
+};
+
+static rt_uint16_t m_pow(rt_uint16_t b, rt_uint16_t n)
+{
+ rt_uint16_t rets = 1;
+
+ while (n--)
+ rets *= b;
+
+ return rets;
+}
+
+static rt_uint16_t m_log2(rt_uint16_t b)
+{
+ rt_uint16_t rets = 0;
+
+ while (b != 1)
+ {
+ b /= 2;
+ rets++;
+ }
+
+ return rets;
+}
+
+/**
+ * read core attribute + */
+void mips32_cfg_init(void)
+{
+ rt_uint16_t val;
+ rt_uint32_t cp0_config1;
+
+ cp0_config1 = read_c0_config();
+ if (cp0_config1 & 0x80000000)
+ {
+ cp0_config1 = read_c0_config1();
+
+ val = (cp0_config1 & (7<<22))>>22;
+ g_mips_core.icache_lines_per_way = 64 * m_pow(2, val);
+ val = (cp0_config1 & (7<<19))>>19;
+ g_mips_core.icache_line_size = 2 * m_pow(2, val);
+ val = (cp0_config1 & (7<<16))>>16;
+ g_mips_core.icache_ways = val + 1;
+
+ val = (cp0_config1 & (7<<13))>>13;
+ g_mips_core.dcache_lines_per_way = 64 * m_pow(2, val);
+ val = (cp0_config1 & (7<<10))>>10;
+ g_mips_core.dcache_line_size = 2 * m_pow(2, val);
+ val = (cp0_config1 & (7<<7))>>7;
+ g_mips_core.dcache_ways = val + 1;
+
+ val = (cp0_config1 & (0x3F<<25))>>25;
+ g_mips_core.max_tlb_entries = val + 1;
+ }
+}
diff --git a/libcpu/mips/loongson/soc3210.h b/libcpu/mips/loongson/soc3210.h new file mode 100644 index 0000000000..fe394ce012 --- /dev/null +++ b/libcpu/mips/loongson/soc3210.h @@ -0,0 +1,172 @@ +#ifndef __SOC3210_H__
+#define __SOC3210_H__
+
+#include "../common/mipsregs.h"
+
+/* registers */
+#define __REG8(addr) *((volatile unsigned char *)(addr))
+#define __REG16(addr) *((volatile unsigned short *)(addr))
+#define __REG32(addr) *((volatile unsigned int *)(addr))
+
+#define EMI_BASE 0xBF000000
+#define NN_BASE 0xBF000040
+#define LCD_BASE 0xBF001000
+#define HSB_MISC_BASE 0xBF003200
+#define SPI_BASE 0xBF004000
+#define PS2_BASE 0xBF004040
+#define UART0_BASE 0xBF004080
+#define UART1_BASE 0xBF004090
+#define I2C_BASE 0xBF0040D0
+#define LPB_MISC_BASE 0xBF004100
+#define AC97_BASE 0xBF004200
+#define AC97_DMA_BASE 0xBF004280
+#define CAN1_BASE 0xBF004300
+#define CAN0_BASE 0xBF004400
+#define MAC0_BASE 0xBF005200
+#define MAC1_BASE 0xBF005300
+
+/* LCD registers */
+#define LCD_CTRL __REG32(LCD_BASE + 0x000)
+#define LCD_STAT __REG32(LCD_BASE + 0x004)
+#define LCD_HTIM __REG32(LCD_BASE + 0x008)
+#define LCD_VTIM __REG32(LCD_BASE + 0x00C)
+#define LCD_HVLEN __REG32(LCD_BASE + 0x010)
+#define LCD_VBARA __REG32(LCD_BASE + 0x014)
+#define LCD_VBARB __REG32(LCD_BASE + 0x018)
+#define LCD_PCLT __REG32(LCD_BASE + 0x800)
+
+/* HSB misc registers */
+#define HSB_MISC_REG __REG32(HSB_MISC_BASE + 0x00)
+#define INT_EDGE __REG32(HSB_MISC_BASE + 0x04)
+#define INT_STEER __REG32(HSB_MISC_BASE + 0x08)
+#define INT_POL __REG32(HSB_MISC_BASE + 0x0C)
+#define INT_SET __REG32(HSB_MISC_BASE + 0x10)
+#define INT_CLR __REG32(HSB_MISC_BASE + 0x14)
+#define INT_EN __REG32(HSB_MISC_BASE + 0x18)
+#define INT_ISR __REG32(HSB_MISC_BASE + 0x1C)
+#define GPIO_OE_60_29 __REG32(HSB_MISC_BASE + 0x20)
+#define GPIO_I_60_29 __REG32(HSB_MISC_BASE + 0x24)
+#define GPIO_O_60_29 __REG32(HSB_MISC_BASE + 0x28)
+#define HSB_ARB_CFG __REG32(HSB_MISC_BASE + 0x2C)
+#define WD_TIMER __REG32(HSB_MISC_BASE + 0x30)
+#define WD_CTRL __REG32(HSB_MISC_BASE + 0x34)
+
+/* SPI registers */
+#define SPI_SPCR __REG8(SPI_BASE + 0x00)
+#define SPI_SPSR __REG8(SPI_BASE + 0x01)
+#define SPI_TX_FIFO __REG8(SPI_BASE + 0x02)
+#define SPI_SPER __REG8(SPI_BASE + 0x03)
+
+/* PS/2 registers */
+#define PS2_RIBUF __REG8(PS2_BASE + 0x00)
+#define PS2_WOBUF __REG8(PS2_BASE + 0x00)
+#define PS2_RSR __REG8(PS2_BASE + 0x04)
+#define PS2_WSC __REG8(PS2_BASE + 0x04)
+#define PS2_DLL __REG8(PS2_BASE + 0x08)
+#define PS2_DLH __REG8(PS2_BASE + 0x09)
+#define PS2_DL_KBD __REG8(PS2_BASE + 0x0A)
+#define PS2_DL_AUX __REG8(PS2_BASE + 0x0B)
+
+/* UART registers */
+#define UART_DAT(base) __REG8(base + 0x00)
+#define UART_IER(base) __REG8(base + 0x01)
+#define UART_IIR(base) __REG8(base + 0x02)
+#define UART_FCR(base) __REG8(base + 0x02)
+#define UART_LCR(base) __REG8(base + 0x03)
+#define UART_MCR(base) __REG8(base + 0x04)
+#define UART_LSR(base) __REG8(base + 0x05)
+#define UART_MSR(base) __REG8(base + 0x06)
+
+#define UART_LSB(base) __REG8(base + 0x00)
+#define UART_MSB(base) __REG8(base + 0x01)
+
+/* UART0 registers */
+#define UART0_DAT __REG8(UART0_BASE + 0x00)
+#define UART0_IER __REG8(UART0_BASE + 0x01)
+#define UART0_IIR __REG8(UART0_BASE + 0x02)
+#define UART0_FCR __REG8(UART0_BASE + 0x02)
+#define UART0_LCR __REG8(UART0_BASE + 0x03)
+#define UART0_MCR __REG8(UART0_BASE + 0x04)
+#define UART0_LSR __REG8(UART0_BASE + 0x05)
+#define UART0_MSR __REG8(UART0_BASE + 0x06)
+
+#define UART0_LSB __REG8(UART0_BASE + 0x00)
+#define UART0_MSB __REG8(UART0_BASE + 0x01)
+
+/* UART1 registers */
+#define UART1_DAT __REG8(UART1_BASE + 0x00)
+#define UART1_IER __REG8(UART1_BASE + 0x01)
+#define UART1_IIR __REG8(UART1_BASE + 0x02)
+#define UART1_FCR __REG8(UART1_BASE + 0x02)
+#define UART1_LCR __REG8(UART1_BASE + 0x03)
+#define UART1_MCR __REG8(UART1_BASE + 0x04)
+#define UART1_LSR __REG8(UART1_BASE + 0x05)
+#define UART1_MSR __REG8(UART1_BASE + 0x06)
+
+#define UART1_LSB __REG8(UART1_BASE + 0x00)
+#define UART1_MSB __REG8(UART1_BASE + 0x01)
+
+/* LPB misc registers */
+#define GPIO_OE_7_0 __REG8(LPB_MISC_BASE + 0x00)
+#define GPIO_OE_15_8 __REG8(LPB_MISC_BASE + 0x01)
+#define GPIO_OE_23_16 __REG8(LPB_MISC_BASE + 0x02)
+#define GPIO_OE_28_24 __REG8(LPB_MISC_BASE + 0x03)
+#define GPIO_I_7_0 __REG8(LPB_MISC_BASE + 0x10)
+#define GPIO_I_15_8 __REG8(LPB_MISC_BASE + 0x11)
+#define GPIO_I_23_16 __REG8(LPB_MISC_BASE + 0x12)
+#define GPIO_I_28_24 __REG8(LPB_MISC_BASE + 0x13)
+#define GPIO_O_7_0 __REG8(LPB_MISC_BASE + 0x20)
+#define GPIO_O_15_8 __REG8(LPB_MISC_BASE + 0x21)
+#define GPIO_O_23_16 __REG8(LPB_MISC_BASE + 0x22)
+#define GPIO_O_28_24 __REG8(LPB_MISC_BASE + 0x23)
+#define LPB_MISC_CFG __REG8(LPB_MISC_BASE + 0x40)
+
+/* MAC0 registers */
+#define MAC0_BUS_MODE __REG32(MAC0_BASE + 0x00)
+#define MAC0_TX_POLL_REQ __REG32(MAC0_BASE + 0x08)
+#define MAC0_RX_POLL_REQ __REG32(MAC0_BASE + 0x10)
+#define MAC0_RX_LIST_BASE_ADDR __REG32(MAC0_BASE + 0x18)
+#define MAC0_TX_LIST_BASE_ADDR __REG32(MAC0_BASE + 0x20)
+#define MAC0_STATUS __REG32(MAC0_BASE + 0x28)
+#define MAC0_OP_MODE __REG32(MAC0_BASE + 0x30)
+#define MAC0_INTERRUPT_EN __REG32(MAC0_BASE + 0x38)
+#define MAC0_MISSED_FRAME_STATISTIC __REG32(MAC0_BASE + 0x40)
+#define MAC0_SMI_EEPROM_CTL __REG32(MAC0_BASE + 0x48)
+#define MAC0_BYTE_ALIGN __REG32(MAC0_BASE + 0x50)
+#define MAC0_GPT_IM_CTL __REG32(MAC0_BASE + 0x58)
+
+/* MAC1 registers */
+#define MAC1_BUS_MODE __REG32(MAC1_BASE + 0x00)
+#define MAC1_TX_POLL_REQ __REG32(MAC1_BASE + 0x08)
+#define MAC1_RX_POLL_REQ __REG32(MAC1_BASE + 0x10)
+#define MAC1_RX_LIST_BASE_ADDR __REG32(MAC1_BASE + 0x18)
+#define MAC1_TX_LIST_BASE_ADDR __REG32(MAC1_BASE + 0x20)
+#define MAC1_STATUS __REG32(MAC1_BASE + 0x28)
+#define MAC1_OP_MODE __REG32(MAC1_BASE + 0x30)
+#define MAC1_INTERRUPT_EN __REG32(MAC1_BASE + 0x38)
+#define MAC1_MISSED_FRAME_STATISTIC __REG32(MAC1_BASE + 0x40)
+#define MAC1_SMI_EEPROM_CTL __REG32(MAC1_BASE + 0x48)
+#define MAC1_BYTE_ALIGN __REG32(MAC1_BASE + 0x50)
+#define MAC1_GPT_IM_CTL __REG32(MAC1_BASE + 0x58)
+
+/* Peripheral Interrupt Number */
+#define IRQ_LCD 0
+#define IRQ_MAC1 1
+#define IRQ_MAC2 2
+#define IRQ_AC97 3
+#define IRQ_SPI 8
+#define IRQ_KEY 9
+#define IRQ_MOUSE 10
+#define IRQ_UART0 11
+#define IRQ_UART1 12
+#define IRQ_I2C 13
+#define IRQ_CAN0 14
+#define IRQ_CAN1 15
+#define IRQ_GPIO15 20
+#define IRQ_GPIO14 21
+#define IRQ_GPIO13 22
+#define IRQ_GPIO12 23
+
+#define SYSTEM_STACK 0x80003fe8 /* the kernel system stack address */
+
+#endif
diff --git a/libcpu/mips/loongson/stack.c b/libcpu/mips/loongson/stack.c new file mode 100644 index 0000000000..187845da58 --- /dev/null +++ b/libcpu/mips/loongson/stack.c @@ -0,0 +1,94 @@ +/*
+ * File : stack.c
+ * This file is part of RT-Thread RTOS
+ * COPYRIGHT (C) 2006, RT-Thread Development Team
+ *
+ * The license and distribution terms for this file may be
+ * found in the file LICENSE in this distribution or at
+ * http://www.rt-thread.org/license/LICENSE
+ *
+ * Change Logs:
+ * Date Author Notes
+ * 2010-05-17 swkyer first version
+ * 2010-07-07 Bernard porting to Jz47xx
+ */
+#include <rtthread.h>
+
+/**
+ * @addtogroup Loogonson SoC3210
+ */
+/*@{*/
+
+extern rt_uint32_t cp0_get_cause(void);
+extern rt_uint32_t cp0_get_status(void);
+extern rt_uint32_t cp0_get_hi(void);
+extern rt_uint32_t cp0_get_lo(void);
+
+/**
+ * This function will initialize thread stack
+ *
+ * @param tentry the entry of thread
+ * @param parameter the parameter of entry
+ * @param stack_addr the beginning stack address
+ * @param texit the function will be called when thread exit
+ *
+ * @return stack address
+ */
+rt_uint8_t *rt_hw_stack_init(void *tentry, void *parameter, rt_uint8_t *stack_addr, void *texit)
+{
+ rt_uint32_t *stk;
+ static rt_uint32_t g_sr = 0;
+
+ if (g_sr == 0)
+ {
+ g_sr = cp0_get_status();
+ g_sr &= 0xfffffffe;
+ g_sr |= 0x8401;
+ }
+
+ /** Start at stack top */
+ stk = (rt_uint32_t *)stack_addr;
+ *(stk) = (rt_uint32_t) tentry; /* pc: Entry Point */
+ *(--stk) = (rt_uint32_t) 0xeeee; /* c0_cause */
+ *(--stk) = (rt_uint32_t) 0xffff; /* c0_badvaddr */
+ *(--stk) = (rt_uint32_t) cp0_get_lo(); /* lo */
+ *(--stk) = (rt_uint32_t) cp0_get_hi(); /* hi */
+ *(--stk) = (rt_uint32_t) g_sr; /* C0_SR: HW2 = En, IE = En */
+ *(--stk) = (rt_uint32_t) texit; /* ra */
+ *(--stk) = (rt_uint32_t) 0x0000001e; /* s8 */
+ *(--stk) = (rt_uint32_t) stack_addr; /* sp */
+ *(--stk) = (rt_uint32_t) 0x0000001c; /* gp */
+ *(--stk) = (rt_uint32_t) 0x0000001b; /* k1 */
+ *(--stk) = (rt_uint32_t) 0x0000001a; /* k0 */
+ *(--stk) = (rt_uint32_t) 0x00000019; /* t9 */
+ *(--stk) = (rt_uint32_t) 0x00000018; /* t8 */
+ *(--stk) = (rt_uint32_t) 0x00000017; /* s7 */
+ *(--stk) = (rt_uint32_t) 0x00000016; /* s6 */
+ *(--stk) = (rt_uint32_t) 0x00000015; /* s5 */
+ *(--stk) = (rt_uint32_t) 0x00000014; /* s4 */
+ *(--stk) = (rt_uint32_t) 0x00000013; /* s3 */
+ *(--stk) = (rt_uint32_t) 0x00000012; /* s2 */
+ *(--stk) = (rt_uint32_t) 0x00000011; /* s1 */
+ *(--stk) = (rt_uint32_t) 0x00000010; /* s0 */
+ *(--stk) = (rt_uint32_t) 0x0000000f; /* t7 */
+ *(--stk) = (rt_uint32_t) 0x0000000e; /* t6 */
+ *(--stk) = (rt_uint32_t) 0x0000000d; /* t5 */
+ *(--stk) = (rt_uint32_t) 0x0000000c; /* t4 */
+ *(--stk) = (rt_uint32_t) 0x0000000b; /* t3 */
+ *(--stk) = (rt_uint32_t) 0x0000000a; /* t2 */
+ *(--stk) = (rt_uint32_t) 0x00000009; /* t1 */
+ *(--stk) = (rt_uint32_t) 0x00000008; /* t0 */
+ *(--stk) = (rt_uint32_t) 0x00000007; /* a3 */
+ *(--stk) = (rt_uint32_t) 0x00000006; /* a2 */
+ *(--stk) = (rt_uint32_t) 0x00000005; /* a1 */
+ *(--stk) = (rt_uint32_t) parameter; /* a0 */
+ *(--stk) = (rt_uint32_t) 0x00000003; /* v1 */
+ *(--stk) = (rt_uint32_t) 0x00000002; /* v0 */
+ *(--stk) = (rt_uint32_t) 0x00000001; /* at */
+ *(--stk) = (rt_uint32_t) 0x00000000; /* zero */
+
+ /* return task's current stack address */
+ return (rt_uint8_t *)stk;
+}
+
+/*@}*/
diff --git a/libcpu/mips/loongson/start_gcc.S b/libcpu/mips/loongson/start_gcc.S new file mode 100644 index 0000000000..42e19b5d99 --- /dev/null +++ b/libcpu/mips/loongson/start_gcc.S @@ -0,0 +1,132 @@ +/*
+ * File : start_gcc.S
+ * Change Logs:
+ * Date Author Notes
+ * 2010-05-17 swkyer first version
+ * 2010-09-04 bernard porting to Jz47xx
+ */
+
+#include "../common/mips.inc"
+#include "../common/stackframe.h"
+#include "soc3210.h"
+
+ .section ".start", "ax"
+ .set noreorder
+
+ /* the program entry */
+ .globl _start
+_start:
+ .set noreorder
+ la ra, _start
+
+ /* disable interrupt */
+ mfc0 t0, CP0_STATUS
+ and t0, 0xfffffffe # By default it will be disabled.
+ mtc0 t0, CP0_STATUS # Set CPU to disable interrupt.
+ nop
+
+ /* disable cache */
+ mfc0 t0, CP0_CONFIG
+ and t0, 0xfffffff8
+ or t0, 0x2 # disable,!default value is not it!
+ mtc0 t0, CP0_CONFIG # Set CPU to disable cache.
+ nop
+
+ /* setup stack pointer */
+ li sp, SYSTEM_STACK
+ la gp, _gp
+
+ /* copy IRAM section */
+ la t0, _iramcopy
+ la t1, _iramstart
+ la t2, _iramend
+_iram_loop:
+ lw t3, 0(t0)
+ sw t3, 0(t1)
+ addiu t1, 4
+ bne t1, t2, _iram_loop
+ addiu t0, 4
+
+ /* clear bss */
+ la t0, __bss_start
+ la t1, __bss_end
+_clr_bss_loop:
+ sw zero, 0(t0)
+ bne t0, t1, _clr_bss_loop
+ addiu t0, t0, 4
+
+ /* jump to RT-Thread RTOS */
+ jal rtthread_startup
+ nop
+
+ /* restart, never die */
+ j _start
+ nop
+ .set reorder
+
+ .globl cp0_get_cause
+cp0_get_cause:
+ mfc0 v0, CP0_CAUSE
+ jr ra
+ nop
+
+ .globl cp0_get_status
+cp0_get_status:
+ mfc0 v0, CP0_STATUS
+ jr ra
+ nop
+
+ .globl cp0_get_hi
+cp0_get_hi:
+ mfhi v0
+ jr ra
+ nop
+
+ .globl cp0_get_lo
+cp0_get_lo:
+ mflo v0
+ jr ra
+ nop
+
+ .extern tlb_refill_handler
+ .extern cache_error_handler
+
+ /* Exception Handler */
+ /* 0x0 - TLB refill handler */
+ .section .vectors.1, "ax", %progbits
+ j tlb_refill_handler
+ nop
+
+ /* 0x100 - Cache error handler */
+ .section .vectors.2, "ax", %progbits
+ j cache_error_handler
+ nop
+
+ /* 0x180 - Exception/Interrupt handler */
+ .section .vectors.3, "ax", %progbits
+ j _general_exception_handler
+ nop
+
+ /* 0x200 - Special Exception Interrupt handler (when IV is set in CP0_CAUSE) */
+ .section .vectors.4, "ax", %progbits
+ j _irq_handler
+ nop
+
+ .section .vectors, "ax", %progbits
+ .extern mips_irq_handle
+
+ /* general exception handler */
+_general_exception_handler:
+ .set noreorder
+ la k0, mips_irq_handle
+ jr k0
+ nop
+ .set reorder
+
+ /* interrupt handler */
+_irq_handler:
+ .set noreorder
+ la k0, mips_irq_handle
+ jr k0
+ nop
+ .set reorder
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