Merge branch 'master' of https://github.com/RT-Thread/rt-thread

add new bsp for risc-v

2 files changed, 113 insertions, 64 deletions

diff --git a/libcpu/mips/loongson_1c/interrupt.c b/libcpu/mips/loongson_1c/interrupt.c
index b39b579731..cc0b8e4e9c 100644
--- a/libcpu/mips/loongson_1c/interrupt.c
+++ b/libcpu/mips/loongson_1c/interrupt.c
@@ -18,8 +18,10 @@
 #include <rtthread.h>
 #include <rthw.h>
 #include "ls1c.h"
+#include "ls1c_public.h"
 
-#define MAX_INTR 32
+
+#define MAX_INTR            (LS1C_NR_IRQS)
 
 extern rt_uint32_t rt_interrupt_nest;
 rt_uint32_t rt_interrupt_from_thread;
@@ -50,13 +52,26 @@ static void rt_hw_interrupt_handler(int vector, void *param)
 void rt_hw_interrupt_init(void)
 {
     rt_int32_t idx;
+    rt_int32_t i;
+    rt_uint32_t c0_status = 0;
+
+    // ����Э������0��״̬�Ĵ���SR��IM7-2�������ж�
+    c0_status = read_c0_status();
+    c0_status |= 0xFC00;
+    write_c0_status(c0_status);
 
-    /* pci active low */
-    ls1c_hw0_icregs->int_pol = -1;	   //must be done here 20110802 lgnq
-    /* make all interrupts level triggered */
-    (ls1c_hw0_icregs+0)->int_edge = 0x0000e000;
-    /* mask all interrupts */
-    (ls1c_hw0_icregs+0)->int_clr = 0xffffffff;
+    // ��о1c���жϷ�Ϊ����
+    for (i=0; i<5; i++)
+    {
+        /* disable */
+        (ls1c_hw0_icregs+i)->int_en = 0x0;
+        /* pci active low */
+        (ls1c_hw0_icregs+i)->int_pol = -1;	   //must be done here 20110802 lgnq
+        /* make all interrupts level triggered */
+        (ls1c_hw0_icregs+i)->int_edge = 0x00000000;
+        /* mask all interrupts */
+        (ls1c_hw0_icregs+i)->int_clr = 0xffffffff;
+    }
 
     rt_memset(irq_handle_table, 0x00, sizeof(irq_handle_table));
     for (idx = 0; idx < MAX_INTR; idx ++)
@@ -115,6 +130,51 @@ rt_isr_handler_t rt_hw_interrupt_install(int vector, rt_isr_handler_t handler,
     return old_handler;
 }
 
+
+/**
+ * ִ���жϴ�������
+ * @IRQn �жϺ�
+ */
+void ls1c_do_IRQ(int IRQn)
+{
+    rt_isr_handler_t irq_func;
+    void *param;
+
+    // �ҵ��жϴ�������
+    irq_func = irq_handle_table[IRQn].handler;
+    param    = irq_handle_table[IRQn].param;
+
+    // ִ���жϴ�������
+    irq_func(IRQn, param);
+    
+#ifdef RT_USING_INTERRUPT_INFO
+    irq_handle_table[IRQn].counter++;
+#endif
+
+    return ;
+}
+
+
+void ls1c_irq_dispatch(int n)
+{
+    rt_uint32_t intstatus, irq;
+
+    /* Receive interrupt signal, compute the irq */
+    intstatus = (ls1c_hw0_icregs+n)->int_isr & (ls1c_hw0_icregs+n)->int_en;
+    if (0 == intstatus)
+        return ;
+
+    // ִ���жϴ�������
+    irq = ls1c_ffs(intstatus) - 1;
+    ls1c_do_IRQ((n<<5) + irq);
+
+    /* ack interrupt */
+    (ls1c_hw0_icregs+n)->int_clr |= (1 << irq);
+
+    return ;
+}
+
+
 void rt_interrupt_dispatch(void *ptreg)
 {
     int irq;
@@ -139,50 +199,25 @@ void rt_interrupt_dispatch(void *ptreg)
     {
         rt_hw_timer_handler();
     }
-
-    if (pending_im & CAUSEF_IP2)
+    else if (pending_im & CAUSEF_IP2)
     {
-        /* the hardware interrupt */
-        status = ls1c_hw0_icregs->int_isr;
-        if (!status)
-            return;
-
-        for (irq = MAX_INTR; irq > 0; --irq)
-        {
-            if ((status & (1 << irq)))
-            {
-                status &= ~(1 << irq);
-
-                irq_func = irq_handle_table[irq].handler;
-                param = irq_handle_table[irq].param;
-
-                /* do interrupt */
-                irq_func(irq, param);
-
-#ifdef RT_USING_INTERRUPT_INFO
-                irq_handle_table[irq].counter++;
-#endif /* RT_USING_INTERRUPT_INFO */
-
-                /* ack interrupt */
-                ls1c_hw0_icregs->int_clr |= (1 << irq);
-            }
-        }
+        ls1c_irq_dispatch(0);
     }
     else if (pending_im & CAUSEF_IP3)
     {
-        rt_kprintf("%s %d\r\n", __FUNCTION__, __LINE__);
+        ls1c_irq_dispatch(1);
     }
     else if (pending_im & CAUSEF_IP4)
     {
-        rt_kprintf("%s %d\r\n", __FUNCTION__, __LINE__);
+        ls1c_irq_dispatch(2);
     }
     else if (pending_im & CAUSEF_IP5)
     {
-        rt_kprintf("%s %d\r\n", __FUNCTION__, __LINE__);
+        ls1c_irq_dispatch(3);
     }
     else if (pending_im & CAUSEF_IP6)
     {
-        rt_kprintf("%s %d\r\n", __FUNCTION__, __LINE__);
+        ls1c_irq_dispatch(4);
     }
 }
 
diff --git a/libcpu/mips/loongson_1c/ls1c.h b/libcpu/mips/loongson_1c/ls1c.h
index 8b50da5ac9..a203810c37 100644
--- a/libcpu/mips/loongson_1c/ls1c.h
+++ b/libcpu/mips/loongson_1c/ls1c.h
@@ -20,7 +20,7 @@
 
 #define LS1C_ACPI_IRQ	0
 #define LS1C_HPET_IRQ	1
-#define LS1C_UART0_IRQ	2
+//#define LS1C_UART0_IRQ	3  // linux����3��v1.4�汾��1c�ֲ�����2�������Σ���ȷ��
 #define LS1C_UART1_IRQ	4
 #define LS1C_UART2_IRQ	5
 #define LS1C_CAN0_IRQ	6
@@ -32,41 +32,55 @@
 #define LS1C_KB_IRQ		12
 #define LS1C_DMA0_IRQ	13
 #define LS1C_DMA1_IRQ	14
-#define LS1C_NAND_IRQ	15
-#define LS1C_I2C0_IRQ	16
-#define LS1C_I2C1_IRQ	17
-#define LS1C_PWM0_IRQ	18
-#define LS1C_PWM1_IRQ	19
-#define LS1C_PWM2_IRQ	20
-#define LS1C_PWM3_IRQ	21
-#define LS1C_LPC_IRQ	22
-#define LS1C_EHCI_IRQ	32
-#define LS1C_OHCI_IRQ	33
-#define LS1C_GMAC1_IRQ	34
-#define LS1C_GMAC2_IRQ	35
-#define LS1C_SATA_IRQ	36
-#define LS1C_GPU_IRQ	37
-#define LS1C_PCI_INTA_IRQ 38
-#define LS1C_PCI_INTB_IRQ 39
-#define LS1C_PCI_INTC_IRQ 40
-#define LS1C_PCI_INTD_IRQ 41
+#define LS1C_DMA2_IRQ   15
+#define LS1C_NAND_IRQ	16
+#define LS1C_PWM0_IRQ	17
+#define LS1C_PWM1_IRQ	18
+#define LS1C_PWM2_IRQ	19
+#define LS1C_PWM3_IRQ	20
+#define LS1C_RTC_INT0_IRQ  21
+#define LS1C_RTC_INT1_IRQ  22
+#define LS1C_RTC_INT2_IRQ  23
+#define LS1C_UART3_IRQ  29
+#define LS1C_ADC_IRQ    30
+#define LS1C_SDIO_IRQ   31
+
+
+#define LS1C_EHCI_IRQ	(32+0)
+#define LS1C_OHCI_IRQ	(32+1)
+#define LS1C_OTG_IRQ    (32+2)
+#define LS1C_MAC_IRQ    (32+3)
+#define LS1C_CAM_IRQ    (32+4)
+#define LS1C_UART4_IRQ  (32+5)
+#define LS1C_UART5_IRQ  (32+6)
+#define LS1C_UART6_IRQ  (32+7)
+#define LS1C_UART7_IRQ  (32+8)
+#define LS1C_UART8_IRQ  (32+9)
+#define LS1C_UART9_IRQ  (32+13)
+#define LS1C_UART10_IRQ (32+14)
+#define LS1C_UART11_IRQ (32+15)
+#define LS1C_I2C2_IRQ   (32+17)
+#define LS1C_I2C1_IRQ   (32+18)
+#define LS1C_I2C0_IRQ   (32+19)
+
 
 #define LS1C_GPIO_IRQ 64
 #define LS1C_GPIO_FIRST_IRQ 64
 #define LS1C_GPIO_IRQ_COUNT 96
 #define LS1C_GPIO_LAST_IRQ  (LS1C_GPIO_FIRST_IRQ + LS1C_GPIO_IRQ_COUNT-1)
 
-#define INT_PCI_INTA	(1<<6)
-#define INT_PCI_INTB	(1<<7)
-#define INT_PCI_INTC	(1<<8)
-#define INT_PCI_INTD	(1<<9)
 
 #define LS1C_LAST_IRQ 159
-#define MIPS_CPU_TIMER_IRQ	167
 #define LS1C_INTREG_BASE 0xbfd01040
 
-#define LS1C_DMA_IRQ_BASE 168
-#define LS1C_DMA_IRQ_COUNT 16
+// ��о1c���жϷ�Ϊ���飬ÿ��32��
+#define LS1C_NR_IRQS    (32*5)
+
+
+// GPIO��ź��жϺ�֮��Ļ���ת��
+#define LS1C_GPIO_TO_IRQ(GPIOn)     (LS1C_GPIO_FIRST_IRQ + (GPIOn))
+#define LS1C_IRQ_TO_GPIO(IRQn)      ((IRQn) - LS1C_GPIO_FIRST_IRQ)
+
 
 struct ls1c_intc_regs
 {