SEP6200 Support

11 files changed, 2205 insertions, 0 deletions

diff --git a/libcpu/unicore32/sep6200/clk.c b/libcpu/unicore32/sep6200/clk.c
new file mode 100644
index 0000000000..f31bd6b694
--- /dev/null
+++ b/libcpu/unicore32/sep6200/clk.c
@@ -0,0 +1,164 @@
+/*
+ * File      : clock.c
+ * This file is part of RT-Thread RTOS
+ * COPYRIGHT (C) 2006, RT-Thread Development Team
+ *
+ * The license and distribution terms for this file may be
+ * found in the file LICENSE in this distribution or at
+ * http://openlab.rt-thread.com/license/LICENSE
+ *
+ * Change Logs:
+ * Date           Author       Notes
+ * 2013-7-16      Peng Fan     Just put the file here, should be implemented in
+ *                             future
+ */
+
+#include <rtthread.h>
+#include <sep6200.h>
+
+#define PLL_CFG(_f, _r) {.f = _f, .r = _r} /*f(frequency, MHz); r(config register value)*/
+#define MHz	1000000UL
+/*
+*SEP0611_CLOCK
+*├── APLL
+*│   └── CPU
+*├── DPLL
+*│   └── DDR
+*└── MPLL
+*    └── BUS1
+*        ├── BUS2
+*        │   ├── DMAC1
+*        │   ├── ESRAM
+*        │   ├── LCDC
+*        │   ├── NAND
+*        │   ├── NOR
+*        │   ├── SDIO1
+*        │   ├── SDIO2
+*        │   └── VPU
+*        ├── BUS3
+*        │   ├── BUS5
+*        │   │   ├── I2C1
+*        │   │   ├── I2C2
+*        │   │   ├── I2C3
+*        │   │   ├── I2S
+*        │   │   ├── SPI1
+*        │   │   ├── SPI2
+*        │   │   ├── SPI3
+*        │   │   ├── UART1
+*        │   │   ├── UART2
+*        │   │   ├── UART3
+*        │   │   └── UART4
+*        │   ├── DMAC2
+*        │   ├── GPU
+*        │   └── USB
+*        ├── BUS4
+*        │   ├── GPIO
+*        │   ├── GPSCTRL
+*        │   ├── PWM
+*        │   ├── RTC
+*        │   ├── SYSCTRL
+*        │   ├── TIMER
+*        │   └── VIC
+*        ├── DS1_2
+*        ├── DS1_3
+*        └── GPS
+*/
+
+enum sep0611_clk_gate{
+  DDRC = 0, BUS1, BUS2, BUS3, DS1_2,
+  DS1_3, USBC, DMAC1, NAND, DMAC2,
+  ESRAM, SDIO1, SDIO2, GPU, VPU,
+  BUS4, BUS5, VIC_, SYSCTRL, PRTC,
+  TIMER, GPSCTRL, GPIO, LCDC2HDMI, DDRPHY,
+  UART1, UART2, UART3, UART4, SPI1,
+  SPI2, SPI3,
+
+  I2C1 = 32, I2C2, I2C3, I2S, PWM,
+  H2X, LCDC, NOR, GPSHCLK, GPS,
+};
+
+typedef struct {
+	unsigned long f;
+	unsigned long r;
+}pll_t;
+
+static pll_t apll_tab[] = {
+  PLL_CFG(800*MHz, 0x00010810),
+};
+
+static pll_t mpll_tab[] = {
+  PLL_CFG(480*MHz, 0x00013C12),   // 480MHz
+};
+
+static pll_t dpll_tab[] = {
+  PLL_CFG(400*MHz, 0x00010812),   // 402MHz
+};
+
+static void rt_hw_set_system_clock(void)
+{
+  /*apll, mpll, dpll is set in uboot when system boots up*/
+}
+
+static void rt_hw_set_usb_clock(void)
+{
+
+}
+
+static void rt_hw_set_peripheral_clock(void)
+{
+
+}
+/**
+ * @brief System Clock Configuration
+ */
+/* apll mpll dpll should be set in u-boot, Here just set clock
+ * of the pherial
+ */
+void rt_hw_set_apll_clock(void)
+{
+
+}
+void rt_hw_set_mpll_clock(void)
+{
+
+}
+void rt_hw_set_dpll_clock(void)
+{
+
+}
+void rt_hw_clock_init(void)
+{
+	/* set system clock */
+	rt_hw_set_system_clock();
+}
+
+/**
+ * @brief Get system clock
+ */
+rt_uint32_t rt_hw_get_clock(void)
+{
+}
+
+/**
+ * @brief Enable module clock
+ */
+void rt_hw_enable_module_clock(rt_uint8_t module)
+{
+  if (module >= 32) {
+    write_reg(SEP6200_PMU_CLK_GT_CFG2, (1 << (module - 32)) | read_reg(SEP6200_PMU_CLK_GT_CFG2));
+  } else {
+    write_reg(SEP6200_PMU_CLK_GT_CFG1, (1 << module) | read_reg(SEP6200_PMU_CLK_GT_CFG1));
+  }
+}
+
+/**
+ * @brief Disable module clock
+ */
+void rt_hw_disable_module_clock(rt_uint8_t module)
+{
+  if (module >= 32) {
+    write_reg(SEP6200_PMU_CLK_GT_CFG2, ~(1 << (module - 32)) & read_reg(SEP6200_PMU_CLK_GT_CFG2));
+  } else {
+    write_reg(SEP6200_PMU_CLK_GT_CFG1, ~(1 << module) & read_reg(SEP6200_PMU_CLK_GT_CFG1));
+  }
+}
diff --git a/libcpu/unicore32/sep6200/context_gcc.S b/libcpu/unicore32/sep6200/context_gcc.S
new file mode 100644
index 0000000000..dd75084061
--- /dev/null
+++ b/libcpu/unicore32/sep6200/context_gcc.S
@@ -0,0 +1,104 @@
+/*
+ * File      : context.S
+ * This file is part of RT-Thread RTOS
+ * COPYRIGHT (C) 2006, RT-Thread Development Team
+ *
+ * The license and distribution terms for this file may be
+ * found in the file LICENSE in this distribution or at
+ * http://openlab.rt-thread.com/license/LICENSE
+ *
+ * Change Logs:
+ * Date           Author       Notes
+ * 2013-7-14      Peng Fan     First implementation
+ */
+
+/*!
+ * \addtogroup sep6200
+ */
+/*@{*/
+
+#define NOINT			0xc0
+
+/*
+ * rt_base_t rt_hw_interrupt_disable();
+ */
+.globl rt_hw_interrupt_disable
+.type rt_hw_interrupt_disable, %function
+rt_hw_interrupt_disable:
+  stw.w   r1, [sp-], #4
+	mov    	r0, asr
+	or    	r1, r0, #NOINT
+	mov.a 	asr, r1
+  ldw.w   r1, [sp]+, #4
+	mov	    pc, lr
+
+/*
+ * void rt_hw_interrupt_enable(rt_base_t level);
+ */
+.globl rt_hw_interrupt_enable
+.type rt_hw_interrupt_disable, %function
+rt_hw_interrupt_enable:
+	mov.a asr, r0
+	mov pc, lr
+
+/*
+ * void rt_hw_context_switch(rt_uint32 from, rt_uint32 to);
+ * r0 --> from
+ * r1 --> to
+ */
+.globl rt_hw_context_switch
+.type rt_hw_interrupt_disable, %function
+rt_hw_context_switch:
+	stm.w   (lr), [sp-]
+	stm.w	(r16, r17, r18, r19, r20, r21, r22, r23, r24, r25, r26, r27, r28, lr), [sp-]
+	stm.w	(r0, r1, r2, r3, r4, r5, r6, r7, r8, r9, r10, r11, r12, r13, r14, r15),  [sp-]
+	mov	r4, asr
+	stm.w	(r4), [sp-]
+	mov 	r4, bsr
+	stm.w	(r4), [sp-]
+
+	stw	sp, [r0+]
+	ldw	sp, [r1+]
+
+	ldm.w	(r4), [sp]+
+	mov.a	bsr,r4
+	ldm.w	(r4), [sp]+
+	mov.a	asr, r4
+
+	ldm.w	(r0, r1, r2, r3, r4, r5, r6, r7, r8, r9, r10, r11, r12, r13, r14, r15), [sp]+
+	ldm.w	(r16, r17, r18, r19, r20, r21, r22, r23, r24, r25, r26, r27, r28, lr, pc), [sp]+
+
+/*
+ * void rt_hw_context_switch_to(rt_uint32 to);
+ * r0 --> to
+ */
+.globl rt_hw_context_switch_to
+rt_hw_context_switch_to:
+	ldw	sp, [r0+]
+	ldm.w	(r4), [sp]+
+	mov.a	bsr, r4
+	ldm.w	(r4), [sp]+
+	mov.a	asr, r4
+	ldm.w	(r0, r1, r2, r3, r4, r5, r6, r7, r8, r9, r10, r11, r12, r13, r14, r15), [sp]+
+	ldm.w	(r16, r17, r18, r19, r20, r21, r22, r23, r24, r25, r26, r27, r28, lr, pc), [sp]+
+
+/*
+ * void rt_hw_context_switch_interrupt(rt_uint32 from, rt_uint32 to);
+ */
+.globl rt_thread_switch_interrupt_flag
+.globl rt_interrupt_from_thread
+.globl rt_interrupt_to_thread
+.globl rt_hw_context_switch_interrupt
+rt_hw_context_switch_interrupt:
+	ldw r2, =rt_thread_switch_interrupt_flag
+	ldw r3, [r2+]
+	cmpsub.a r3, #1
+	beq _reswitch
+	mov r3, #1
+	stw r3, [r2+]
+	ldw r2, =rt_interrupt_from_thread
+	stw r0, [r2+]
+_reswitch:
+	ldw r2, =rt_interrupt_to_thread
+	stw r1, [r2+]
+	mov pc, lr
diff --git a/libcpu/unicore32/sep6200/cpu.c b/libcpu/unicore32/sep6200/cpu.c
new file mode 100644
index 0000000000..969a804169
--- /dev/null
+++ b/libcpu/unicore32/sep6200/cpu.c
@@ -0,0 +1,280 @@
+/*
+ * File      : cpu.c
+ * This file is part of RT-Thread RTOS
+ * COPYRIGHT (C) 2006, RT-Thread Develop Team
+ *
+ * The license and distribution terms for this file may be
+ * found in the file LICENSE in this distribution or at
+ * http://openlab.rt-thread.com/license/LICENSE
+ *
+ * Change Logs:
+ * Date           Author       Notes
+ * 2013-7-14      Peng Fan     first implementation
+ */
+
+#include <rthw.h>
+#include <rtthread.h>
+#include <sep6200.h>
+
+/**
+ * @addtogroup sep6200
+ */
+/*@{*/
+
+#ifdef __GNUC__
+rt_inline void cache_invalid(void)
+{
+	__asm__ volatile ("movc	p0.c5, r1, #28\n"
+			"nop;nop;nop;nop;nop;nop;nop;nop;\n"
+			:
+			:
+			:"memory", "cc"
+			);
+}
+
+rt_inline void cache_enable(void)
+{
+	__asm__ volatile ( "movc r1, p0.c1, #0\n"
+			"or r1, r1, #0xc\n"
+			"movc p0.c1, r1, #0\n"
+			"nop;nop;nop;nop;nop;nop;nop;nop;\n"
+			:
+			:
+			:"r0", "memory", "cc");
+}
+
+rt_inline void clean_dcache(void)
+{
+    __asm__ volatile ( "mov ip, #0\n"
+               "movc p0.c5, ip, #10\n"
+               "nop; nop; nop; nop; nop; nop; nop; nop\n"
+               :
+	       :
+	       :"ip", "memory", "cc");
+}
+
+rt_inline rt_uint32_t icache_status(void)
+{
+    rt_uint32_t ret;
+
+     __asm__ volatile ( "movc %0, p0.c1, #0\n"
+                "and %0, %0, #8\n"
+                : "=&r" (ret)
+                :
+                :"memory", "cc");
+
+    return ret;
+}
+
+rt_inline rt_uint32_t dcache_status(void)
+{
+    rt_uint32_t ret;
+
+    __asm__ volatile ( "movc %0, p0.c1, #0\n"
+               "and %0, %0, #4\n"
+               : "=&r" (ret)
+               :
+               :"memory", "cc");
+
+     return ret;
+}
+
+rt_inline void dcache_flush(void)
+{
+	__asm__ volatile ( "mov ip, #0\n"
+              "movc p0.c5, ip, #14\n"
+              "nop; nop; nop; nop; nop; nop; nop; nop\n"
+              :
+              :
+              : "ip" );
+}
+
+rt_inline void icache_invalid(void)
+{
+	 __asm__ volatile ( "mov r0, #0\n"
+               "movc p0.c5, r0, #20\n"
+               "nop; nop; nop; nop; nop; nop; nop; nop\n"
+               :
+               :
+               :"r0", "memory", "cc");
+}
+
+rt_inline void dcache_invalid(void)
+{
+    __asm__ volatile ( "mov r0, #0\n"
+                "movc p0.c5, r0, #12\n"
+               "nop; nop; nop; nop; nop; nop; nop; nop\n"
+               :
+               :
+               :"r0", "memory", "cc");
+}
+
+rt_inline void icache_disable(void)
+{
+	icache_invalid();
+	__asm__ volatile ( "movc r0, p0.c1, #0\n"
+               "andn r0, r0, #8\n"
+               "movc p0.c1, r0, #0\n"
+               :
+               :
+               :"r0", "memory", "cc");
+}
+
+rt_inline void dcache_disable(void)
+{
+	dcache_flush();
+	__asm__ volatile ( "movc r0, p0.c1, #0\n"
+               "andn r0, r0, #20\n"
+               "movc p0.c1, r0, #0\n"
+               :
+               :
+               :"r0", "memory", "cc");
+
+}
+
+rt_inline void icache_enable(void)
+{
+    __asm__ volatile ( "mov r0, #0\n"
+               "movc p0.c5, r0, #20\n"
+               "nop; nop; nop; nop; nop; nop; nop; nop\n"
+               :
+               :
+               :"r0", "memory", "cc");
+
+    __asm__ volatile ( "movc r0, p0.c1, #0\n"
+               "or r0, r0, #8\n"
+               "movc p0.c1, r0, #0\n"
+               :
+               :
+               :"r0", "memory", "cc");
+}
+
+rt_inline void dcache_enable(void)
+{
+    __asm__ volatile ( "mov r0, #0\n"
+           "movc p0.c5, r0, #12\n"
+           "nop; nop; nop; nop; nop; nop; nop; nop\n"
+           :
+           :
+           :"r0", "memory", "cc");
+
+    __asm__ volatile ( "movc r0, p0.c1, #0\n"
+           "or r0, r0, #20\n"
+           "movc p0.c1, r0, #0\n"
+           :
+           :
+           :"r0", "memory", "cc");
+}
+#endif
+
+
+/**
+ * enable I-Cache
+ *
+ */
+void rt_hw_cpu_icache_enable()
+{
+	icache_enable();
+}
+
+/**
+ * disable I-Cache
+ *
+ */
+void rt_hw_cpu_icache_disable()
+{
+	icache_disable();
+}
+
+/**
+ * return the status of I-Cache
+ *
+ */
+rt_base_t rt_hw_cpu_icache_status()
+{
+	return icache_status();
+}
+
+/**
+ * enable D-Cache
+ *
+ */
+void rt_hw_cpu_dcache_enable()
+{
+	dcache_enable();
+}
+
+/**
+ * disable D-Cache
+ *
+ */
+void rt_hw_cpu_dcache_disable()
+{
+	dcache_disable();
+}
+
+/**
+ * return the status of D-Cache
+ *
+ */
+rt_base_t rt_hw_cpu_dcache_status()
+{
+	return dcache_status();
+}
+
+static void sep6200_reset(rt_uint32_t addr)
+{
+     __asm__ volatile ( "mov ip, #0\n"
+		     "movc p0.c5, ip, #28\n" /*Cache invalidate all*/
+		     "movc p0.c6, ip, #6\n" /*TLB invalidate all*/
+		     "nop;nop;nop;nop;nop;nop;nop;nop;\n"
+		     "movc ip, p0.c1, #0\n" /*ctrl register*/
+		     "andn ip, ip, #0x000f\n" /*disable caches and mmu*/
+		     "movc p0.c1, ip, #0\n"
+		     "nop\n"
+		     "mov pc, %0\n"
+		     "nop;nop;nop;nop;nop;nop;nop;nop;\n"
+		      : "=&r" (addr)
+		      :
+		      :"memory", "cc");
+}
+
+static void sep6200_poweroff(void)
+{
+	rt_kprintf("sep6200 power off not implemented\n");
+  while(1);
+}
+
+/**
+ * reset cpu by dog's time-out
+ *
+ */
+void rt_hw_cpu_reset()
+{
+
+	rt_kprintf("Soft reset, Restarting system...\n");
+	sep6200_reset(0);
+
+	while(1);	/* loop forever and wait for reset to happen */
+
+	/* NEVER REACHED */
+}
+
+/**
+ *  shutdown CPU
+ *
+ */
+void rt_hw_cpu_shutdown()
+{
+	rt_uint32_t level;
+	rt_kprintf("shutdown...\n");
+
+	level = rt_hw_interrupt_disable();
+	sep6200_poweroff();
+	while (level)
+	{
+		RT_ASSERT(0);
+	}
+}
+
+/*@}*/
diff --git a/libcpu/unicore32/sep6200/interrupt.c b/libcpu/unicore32/sep6200/interrupt.c
new file mode 100644
index 0000000000..dbfd529786
--- /dev/null
+++ b/libcpu/unicore32/sep6200/interrupt.c
@@ -0,0 +1,213 @@
+/*
+ * File      : interrupt.c
+ * This file is part of RT-Thread RTOS
+ * COPYRIGHT (C) 2006, RT-Thread Development Team
+ *
+ * The license and distribution terms for this file may be
+ * found in the file LICENSE in this distribution or at
+ * http://openlab.rt-thread.com/license/LICENSE
+ *
+ * Change Logs:
+ * Date           Author       Notes
+ * 2013-7-14      Peng Fan     First implementation
+ */
+
+#include <rtthread.h>
+#include <rthw.h>
+#include <sep6200.h>
+
+#define MAX_HANDLERS	64
+
+
+#define SEP6200_IRQ_TYPE 0
+#define SEP6200_FIQ_TYPE 1
+
+#define int_enable_all() 					  \
+	do {							  \
+		*(volatile unsigned long*)SEP6200_VIC_INT_EN_L = ~0x0;\
+		*(volatile unsigned long*)SEP6200_VIC_INT_EN_H = ~0x0;\
+	}while(0)
+#define int_disable_all() 					 \
+	do {							 \
+		*(volatile unsigned long*)SEP6200_VIC_INT_EN_L = 0x0;\
+		*(volatile unsigned long*)SEP6200_VIC_INT_EN_H = 0x0;\
+	}while(0)
+#define mask_all_int(int_type)					 \
+	do {							 \
+		if (int_type == SEP6200_IRQ_TYPE){		 \
+		*(volatile unsigned long*)SEP6200_VIC_INT_MSK_ALL = 0x1;\
+		} else if (int_type == SEP6200_FIQ_TYPE) {\
+		*(volatile unsigned long*)SEP6200_VIC_INT_MSK_ALL = 0x2;\
+		}\
+	}while(0)
+#define unmask_all_int(int_type)\
+	do {							 \
+		if (int_type == SEP6200_IRQ_TYPE){		 \
+		*(volatile unsigned long*)SEP6200_VIC_INT_MSK_ALL = ~0x1;\
+		} else if (int_type == SEP6200_FIQ_TYPE) {\
+		*(volatile unsigned long*)SEP6200_VIC_INT_MSK_ALL = ~0x2;\
+		}\
+	}while(0)
+
+#define SEP6200_INT_SET(intnum)                                     \
+do{                                                                 \
+    if(intnum < 32)                                                 \
+        *(volatile unsigned long*)SEP6200_VIC_SFT_INT_L |= (1 << intnum); \
+    else                                                            \
+        *(volatile unsigned long*)SEP6200_VIC_SFT_INT_H |= (1 << (intnum - 32));  \
+}while(0)
+
+#define SEP6200_INT_CLR(intnum)   \
+do{                               \
+    if(intnum < 32)               \
+        *(volatile unsigned long*)SEP6200_VIC_SFT_INT_L &= ~(1 << intnum);\
+    else                          \
+        *(volatile unsigned long*)SEP6200_VIC_SFT_INT_H &= ~(1 << (intnum - 32)); \
+}while(0)
+
+#define SEP6200_INT_ENABLE(intnum)\
+do{                               \
+    if(intnum < 32)               \
+        *(volatile unsigned long*)SEP6200_VIC_INT_EN_L |= (1 << intnum);  \
+    else                          \
+        *(volatile unsigned long*)SEP6200_VIC_INT_EN_H |= (1 << (intnum - 32));   \
+}while(0)
+
+#define SEP6200_INT_DISABLE(intnum)                                 \
+do{                                                                 \
+    if(intnum < 32)                                                 \
+        *(volatile unsigned long*)SEP6200_VIC_INT_EN_L &= ~(1 << intnum); \
+    else                                                            \
+        *(volatile unsigned long*)SEP6200_VIC_INT_EN_H &= ~(1 << (intnum - 32));  \
+}while(0)
+
+
+extern rt_uint32_t rt_interrupt_nest;
+/* exception and interrupt handler table */
+struct rt_irq_desc isr_table[MAX_HANDLERS];
+rt_uint32_t rt_interrupt_from_thread, rt_interrupt_to_thread;
+rt_uint32_t rt_thread_switch_interrupt_flag;
+
+
+/* --------------------------------------------------------------------
+ *  Interrupt initialization
+ * -------------------------------------------------------------------- */
+
+/**
+ * @addtogroup sep6200
+ */
+/*@{*/
+
+void rt_hw_interrupt_mask(int irq);
+void rt_hw_interrupt_umask(int irq);
+
+rt_inline void sep6200_irq_enable(rt_uint32_t irq)
+{
+	SEP6200_INT_ENABLE(irq);
+}
+
+rt_inline void sep6200_irq_disable(rt_uint32_t irq)
+{
+	SEP6200_INT_DISABLE(irq);
+}
+
+rt_inline void sep6200_irq_unmask(rt_uint32_t irq)
+{
+	SEP6200_INT_ENABLE(irq);
+}
+
+rt_inline void sep6200_irq_mask(rt_uint32_t irq)
+{
+	SEP6200_INT_DISABLE(irq);
+}
+rt_isr_handler_t rt_hw_interrupt_handle(rt_uint32_t vector)
+{
+	rt_kprintf("Unhandled interrupt %d occured!!!\n", vector);
+	return RT_NULL;
+}
+
+/**
+ * This function will initialize hardware interrupt
+ */
+void rt_hw_interrupt_init(void)
+{
+	rt_int32_t i;
+	register rt_uint32_t idx;
+
+
+	/* init exceptions table */
+	for(idx=0; idx < MAX_HANDLERS; idx++)
+	{
+		isr_table[idx].handler = (rt_isr_handler_t)rt_hw_interrupt_handle;
+	}
+	int_disable_all();
+	mask_all_int(SEP6200_FIQ_TYPE);
+
+	//int_enable_all();
+	unmask_all_int(SEP6200_IRQ_TYPE);
+
+	/* init interrupt nest, and context in thread sp */
+	rt_interrupt_nest = 0;
+	rt_interrupt_from_thread = 0;
+	rt_interrupt_to_thread = 0;
+	rt_thread_switch_interrupt_flag = 0;
+}
+
+
+
+/**
+ * This function will mask a interrupt.
+ * @param vector the interrupt number
+ */
+void rt_hw_interrupt_mask(int irq)
+{
+	if (irq >= MAX_HANDLERS) {
+		rt_kprintf("Wrong irq num to mask\n");
+	} else {
+		sep6200_irq_mask(irq);
+	}
+
+}
+
+/**
+ * This function will un-mask a interrupt.
+ * @param vector the interrupt number
+ */
+void rt_hw_interrupt_umask(int irq)
+{
+	if (irq >= MAX_HANDLERS) {
+		rt_kprintf("Wrong irq num to unmask\n");
+	} else {
+		sep6200_irq_unmask(irq);
+	}
+}
+
+/**
+ * This function will install a interrupt service routine to a interrupt.
+ * @param vector the interrupt number
+ * @param new_handler the interrupt service routine to be installed
+ * @param old_handler the old interrupt service routine
+ */
+rt_isr_handler_t rt_hw_interrupt_install(int vector, rt_isr_handler_t handler,
+                                        void *param, char *name)
+{
+    rt_isr_handler_t old_handler = RT_NULL;
+
+    if(vector < MAX_HANDLERS)
+    {
+        old_handler = isr_table[vector].handler;
+
+        if (handler != RT_NULL)
+        {
+#ifdef RT_USING_INTERRUPT_INFO
+		    rt_strncpy(isr_table[vector].name, name, RT_NAME_MAX);
+#endif /* RT_USING_INTERRUPT_INFO */
+            isr_table[vector].handler = handler;
+            isr_table[vector].param = param;
+        }
+    }
+
+    return old_handler;
+}
+
+/*@}*/
diff --git a/libcpu/unicore32/sep6200/sep6200.h b/libcpu/unicore32/sep6200/sep6200.h
new file mode 100644
index 0000000000..01c6b8b548
--- /dev/null
+++ b/libcpu/unicore32/sep6200/sep6200.h
@@ -0,0 +1,447 @@
+#ifndef __SEP6200_H
+#define __SEP6200_H
+
+#include <rtthread.h>
+
+/*Core definations*/
+#define PRIVMODE  0x13
+#define	Mode_USR	0x10
+#define	Mode_REAL	0x11
+#define	Mode_IRQ	0x12
+#define	Mode_PRIV	0x13
+#define	Mode_TRAP	0x17
+#define	Mode_EXT	0x1B
+#define	Mode_SUSR	0x1F
+
+/*
+ *  Address
+ */
+
+#define	 SEP6200_VIC_BASE	0xb0000000
+#define  SEP6200_PMU_BASE	0xb0001000
+#define  SEP6200_RTC_BASE	0xb0002000
+#define	 SEP6200_TIMER_BASE 0xb0003000
+#define  SEP6200_PWM_BASE	0xb0004000
+#define  SEP6200_GPIO_BASE	0xb0006000
+#define  SEP6200_TOUCH_ADC	0xb0007000
+#define  SEP6200_SYSCTL_BASE	0xb0008000
+#define  SEP6200_UART0_BASE	0xb1000000
+#define  SEP6200_UART1_BASE	0xb1001000
+#define  SEP6200_UART2_BASE	0xb1002000
+#define  SEP6200_UART3_BASE	0xb1003000
+#define	 SEP6200_SSI1_BASE	0xb1004000
+#define	 SEP6200_SSI2_BASE	0xb1005000
+#define	 SEP6200_SSI3_BASE	0xb1006000
+#define  SEP6200_I2C_BASE	0xb1007000
+#define  SEP6200_I2S_BASE	0xb1008000
+#define  SEP6200_USB_BASE    0xb1010000
+#define  SEP6200_DMAC2_BASE  0xb1011000
+#define  SEP6200_ESRAM_BASE  0xb2000000
+#define	 SEP6200_NORREG_BASE0xb2020000
+#define	 SEP6200_SDIO1_BASE	0xb2022000
+#define	 SEP6200_SDIO2_BASE	0xb2023000
+#define	 SEP6200_LCDC_BASE	0xb2025000
+#define	 SEP6200_VPU_BASE	0xb2026000
+#define	 SEP6200_DMAC1_BASE	0xb2027000
+#define	 SEP6200_DDR2_REG	0xb3000000
+#define	 SEP6200_DDR_MEM	0x40000000
+
+#define SEP6200_UART0_DLBL	(SEP6200_UART0_BASE+0x00)
+#define SEP6200_UART0_RXFIFO	(SEP6200_UART0_BASE+0x00)
+#define SEP6200_UART0_TXFIFO	(SEP6200_UART0_BASE+0x00)
+#define SEP6200_UART0_DLBH	(SEP6200_UART0_BASE+0x04)
+#define SEP6200_UART0_IER	(SEP6200_UART0_BASE+0x04)
+#define SEP6200_UART0_IIR	(SEP6200_UART0_BASE+0x08)
+#define SEP6200_UART0_FCR	(SEP6200_UART0_BASE+0x08)
+#define SEP6200_UART0_LCR	(SEP6200_UART0_BASE+0x0c)
+#define SEP6200_UART0_MCR	(SEP6200_UART0_BASE+0x10)
+#define SEP6200_UART0_LSR	(SEP6200_UART0_BASE+0x14)
+#define SEP6200_UART0_MSR	(SEP6200_UART0_BASE+0x18)
+
+
+#define    SEP6200_TIMER_T1LCR              (SEP6200_TIMER_BASE + 0X000)
+#define    SEP6200_TIMER_T1CCR              (SEP6200_TIMER_BASE + 0X004)
+#define    SEP6200_TIMER_T1CR               (SEP6200_TIMER_BASE + 0X008)
+#define    SEP6200_TIMER_T1ISCR             (SEP6200_TIMER_BASE + 0X00C)
+#define    SEP6200_TIMER_T1IMSR             (SEP6200_TIMER_BASE + 0X010)
+#define    SEP6200_TIMER_T2LCR              (SEP6200_TIMER_BASE + 0X020)
+#define    SEP6200_TIMER_T2CCR              (SEP6200_TIMER_BASE + 0X024)
+#define    SEP6200_TIMER_T2CR               (SEP6200_TIMER_BASE + 0X028)
+#define    SEP6200_TIMER_T2ISCR             (SEP6200_TIMER_BASE + 0X02C)
+#define    SEP6200_TIMER_T2IMSR             (SEP6200_TIMER_BASE + 0X030)
+#define    SEP6200_TIMER_T3LCR              (SEP6200_TIMER_BASE + 0X040)
+#define    SEP6200_TIMER_T3CCR              (SEP6200_TIMER_BASE + 0X044)
+#define    SEP6200_TIMER_T3CR               (SEP6200_TIMER_BASE + 0X048)
+#define    SEP6200_TIMER_T3ISCR             (SEP6200_TIMER_BASE + 0X04C)
+#define    SEP6200_TIMER_T3IMSR             (SEP6200_TIMER_BASE + 0X050)
+#define    SEP6200_TIMER_T3CAPR             (SEP6200_TIMER_BASE + 0X054)
+#define    SEP6200_TIMER_T4LCR              (SEP6200_TIMER_BASE + 0X060)
+#define    SEP6200_TIMER_T4CCR              (SEP6200_TIMER_BASE + 0X064)
+#define    SEP6200_TIMER_T4CR               (SEP6200_TIMER_BASE + 0X068)
+#define    SEP6200_TIMER_T4ISCR             (SEP6200_TIMER_BASE + 0X06C)
+#define    SEP6200_TIMER_T4IMSR             (SEP6200_TIMER_BASE + 0X070)
+#define    SEP6200_TIMER_T4CAPR             (SEP6200_TIMER_BASE + 0X074)
+#define    SEP6200_TIMER_T5LCR              (SEP6200_TIMER_BASE + 0X080)
+#define    SEP6200_TIMER_T5CCR              (SEP6200_TIMER_BASE + 0X084)
+#define    SEP6200_TIMER_T5CR               (SEP6200_TIMER_BASE + 0X088)
+#define    SEP6200_TIMER_T5ISCR             (SEP6200_TIMER_BASE + 0X08C)
+#define    SEP6200_TIMER_T5IMSR             (SEP6200_TIMER_BASE + 0X090)
+#define    SEP6200_TIMER_T5CAPR             (SEP6200_TIMER_BASE + 0X094)
+#define    SEP6200_TIMER_T6LCR              (SEP6200_TIMER_BASE + 0X0A0)
+#define    SEP6200_TIMER_T6CCR              (SEP6200_TIMER_BASE + 0X0A4)
+#define    SEP6200_TIMER_T6CR               (SEP6200_TIMER_BASE + 0X0A8)
+#define    SEP6200_TIMER_T6ISCR             (SEP6200_TIMER_BASE + 0X0AC)
+#define    SEP6200_TIMER_T6IMSR             (SEP6200_TIMER_BASE + 0X0B0)
+#define    SEP6200_TIMER_T6CAPR             (SEP6200_TIMER_BASE + 0X0B4)
+#define    SEP6200_TIMER_T7LCR              (SEP6200_TIMER_BASE + 0X0C0)
+#define    SEP6200_TIMER_T7CCR              (SEP6200_TIMER_BASE + 0X0C4)
+#define    SEP6200_TIMER_T7CR               (SEP6200_TIMER_BASE + 0X0C8)
+#define    SEP6200_TIMER_T7ISCR             (SEP6200_TIMER_BASE + 0X0CC)
+#define    SEP6200_TIMER_T7IMSR             (SEP6200_TIMER_BASE + 0X0D0)
+#define    SEP6200_TIMER_T8LCR              (SEP6200_TIMER_BASE + 0X0E0)
+#define    SEP6200_TIMER_T8CCR              (SEP6200_TIMER_BASE + 0X0E4)
+#define    SEP6200_TIMER_T8CR               (SEP6200_TIMER_BASE + 0X0E8)
+#define    SEP6200_TIMER_T8ISCR             (SEP6200_TIMER_BASE + 0X0EC)
+#define    SEP6200_TIMER_T8IMSR             (SEP6200_TIMER_BASE + 0X0F0)
+#define    SEP6200_TIMER_T9LCR              (SEP6200_TIMER_BASE + 0X100)
+#define    SEP6200_TIMER_T9CCR              (SEP6200_TIMER_BASE + 0X104)
+#define    SEP6200_TIMER_T9CR               (SEP6200_TIMER_BASE + 0X108)
+#define    SEP6200_TIMER_T9ISCR             (SEP6200_TIMER_BASE + 0X10C)
+#define    SEP6200_TIMER_T9IMSR             (SEP6200_TIMER_BASE + 0X110)
+#define    SEP6200_TIMER_T10LCR             (SEP6200_TIMER_BASE + 0X120)
+#define    SEP6200_TIMER_T10CCR             (SEP6200_TIMER_BASE + 0X124)
+#define    SEP6200_TIMER_T10CR              (SEP6200_TIMER_BASE + 0X128)
+#define    SEP6200_TIMER_T10ISCR            (SEP6200_TIMER_BASE + 0X12C)
+#define    SEP6200_TIMER_T10IMSR            (SEP6200_TIMER_BASE + 0X130)
+#define    SEP6200_TIMER_TIMSR              (SEP6200_TIMER_BASE + 0X140)
+#define    SEP6200_TIMER_TISCR              (SEP6200_TIMER_BASE + 0X144)
+#define    SEP6200_TIMER_TISR               (SEP6200_TIMER_BASE + 0X148)
+
+#define    SEP6200_VIC_INT_SLT_L            (SEP6200_VIC_BASE + 0x000)
+#define    SEP6200_VIC_INT_SLT_H            (SEP6200_VIC_BASE + 0x004)
+#define    SEP6200_VIC_INT_EN_L             (SEP6200_VIC_BASE + 0x008)
+#define    SEP6200_VIC_INT_EN_H             (SEP6200_VIC_BASE + 0x00C)
+#define    SEP6200_VIC_INT_EN_CLR_L         (SEP6200_VIC_BASE + 0x010)
+#define    SEP6200_VIC_INT_EN_CLR_H         (SEP6200_VIC_BASE + 0x014)
+#define    SEP6200_VIC_SFT_INT_L            (SEP6200_VIC_BASE + 0x018)
+#define    SEP6200_VIC_SFT_INT_H            (SEP6200_VIC_BASE + 0x01C)
+#define    SEP6200_VIC_SFT_INT_CLR_L        (SEP6200_VIC_BASE + 0x020)
+#define    SEP6200_VIC_SFT_INT_CLR_H        (SEP6200_VIC_BASE + 0x024)
+#define    SEP6200_VIC_INT_MSK_ALL          (SEP6200_VIC_BASE + 0x028)
+#define    SEP6200_VIC_RAW_INT_SRC_L        (SEP6200_VIC_BASE + 0x030)
+#define    SEP6200_VIC_RAW_INT_SRC_H        (SEP6200_VIC_BASE + 0x034)
+#define    SEP6200_VIC_RAW_IRQ_STS_L        (SEP6200_VIC_BASE + 0x038)
+#define    SEP6200_VIC_RAW_IRQ_STS_H        (SEP6200_VIC_BASE + 0x03C)
+#define    SEP6200_VIC_RAW_FIQ_STS_L        (SEP6200_VIC_BASE + 0x040)
+#define    SEP6200_VIC_RAW_FIQ_STS_H        (SEP6200_VIC_BASE + 0x044)
+#define    SEP6200_VIC_MSK_IRQ_STS_L        (SEP6200_VIC_BASE + 0x048)
+#define    SEP6200_VIC_MSK_IRQ_STS_H        (SEP6200_VIC_BASE + 0x04C)
+#define    SEP6200_VIC_MSK_FIQ_STS_L        (SEP6200_VIC_BASE + 0x050)
+#define    SEP6200_VIC_MSK_FIQ_STS_H        (SEP6200_VIC_BASE + 0x054)
+#define    SEP6200_VIC_IRQ_PENDING_L        (SEP6200_VIC_BASE + 0x058)
+#define    SEP6200_VIC_IRQ_PENDING_H        (SEP6200_VIC_BASE + 0x05C)
+#define    SEP6200_VIC_FIQ_PENDING_L        (SEP6200_VIC_BASE + 0x060)
+#define    SEP6200_VIC_FIQ_PENDING_H        (SEP6200_VIC_BASE + 0x064)
+#define    SEP6200_VIC_IRQ_VECTOR_BASE      (SEP6200_VIC_BASE + 0x070)
+#define    SEP6200_VIC_FIQ_VECTOR_BASE      (SEP6200_VIC_BASE + 0x074)
+#define    SEP6200_VIC_IRQ_VECTOR_NUM       (SEP6200_VIC_BASE + 0x078)
+#define    SEP6200_VIC_FIQ_VECTOR_NUM       (SEP6200_VIC_BASE + 0x07C)
+#define    SEP6200_VIC_IRQ_VECTOR_ADDR      (SEP6200_VIC_BASE + 0x080)
+#define    SEP6200_VIC_FIQ_VECTOR_ADDR      (SEP6200_VIC_BASE + 0x084)
+#define    SEP6200_VIC_PROIRTY_MASK         (SEP6200_VIC_BASE + 0x090)
+#define    SEP6200_VIC_VECTOR_PROIRTY00     (SEP6200_VIC_BASE + 0x100)
+#define    SEP6200_VIC_VECTOR_PROIRTY01     (SEP6200_VIC_BASE + 0x104)
+#define    SEP6200_VIC_VECTOR_PROIRTY02     (SEP6200_VIC_BASE + 0x108)
+#define    SEP6200_VIC_VECTOR_PROIRTY03     (SEP6200_VIC_BASE + 0x10C)
+#define    SEP6200_VIC_VECTOR_PROIRTY04     (SEP6200_VIC_BASE + 0x110)
+#define    SEP6200_VIC_VECTOR_PROIRTY05     (SEP6200_VIC_BASE + 0x114)
+#define    SEP6200_VIC_VECTOR_PROIRTY06     (SEP6200_VIC_BASE + 0x118)
+#define    SEP6200_VIC_VECTOR_PROIRTY07     (SEP6200_VIC_BASE + 0x11C)
+#define    SEP6200_VIC_VECTOR_PROIRTY08     (SEP6200_VIC_BASE + 0x120)
+#define    SEP6200_VIC_VECTOR_PROIRTY09     (SEP6200_VIC_BASE + 0x124)
+#define    SEP6200_VIC_VECTOR_PROIRTY10     (SEP6200_VIC_BASE + 0x128)
+#define    SEP6200_VIC_VECTOR_PROIRTY11     (SEP6200_VIC_BASE + 0x12C)
+#define    SEP6200_VIC_VECTOR_PROIRTY12     (SEP6200_VIC_BASE + 0x130)
+#define    SEP6200_VIC_VECTOR_PROIRTY13     (SEP6200_VIC_BASE + 0x134)
+#define    SEP6200_VIC_VECTOR_PROIRTY14     (SEP6200_VIC_BASE + 0x138)
+#define    SEP6200_VIC_VECTOR_PROIRTY15     (SEP6200_VIC_BASE + 0x13C)
+#define    SEP6200_VIC_VECTOR_PROIRTY16     (SEP6200_VIC_BASE + 0x140)
+#define    SEP6200_VIC_VECTOR_PROIRTY17     (SEP6200_VIC_BASE + 0x144)
+#define    SEP6200_VIC_VECTOR_PROIRTY18     (SEP6200_VIC_BASE + 0x148)
+#define    SEP6200_VIC_VECTOR_PROIRTY19     (SEP6200_VIC_BASE + 0x14C)
+#define    SEP6200_VIC_VECTOR_PROIRTY20     (SEP6200_VIC_BASE + 0x150)
+#define    SEP6200_VIC_VECTOR_PROIRTY21     (SEP6200_VIC_BASE + 0x154)
+#define    SEP6200_VIC_VECTOR_PROIRTY22     (SEP6200_VIC_BASE + 0x158)
+#define    SEP6200_VIC_VECTOR_PROIRTY23     (SEP6200_VIC_BASE + 0x15C)
+#define    SEP6200_VIC_VECTOR_PROIRTY24     (SEP6200_VIC_BASE + 0x160)
+#define    SEP6200_VIC_VECTOR_PROIRTY25     (SEP6200_VIC_BASE + 0x164)
+#define    SEP6200_VIC_VECTOR_PROIRTY26     (SEP6200_VIC_BASE + 0x168)
+#define    SEP6200_VIC_VECTOR_PROIRTY27     (SEP6200_VIC_BASE + 0x16C)
+#define    SEP6200_VIC_VECTOR_PROIRTY28     (SEP6200_VIC_BASE + 0x170)
+#define    SEP6200_VIC_VECTOR_PROIRTY29     (SEP6200_VIC_BASE + 0x174)
+#define    SEP6200_VIC_VECTOR_PROIRTY30     (SEP6200_VIC_BASE + 0x178)
+#define    SEP6200_VIC_VECTOR_PROIRTY31     (SEP6200_VIC_BASE + 0x17C)
+#define    SEP6200_VIC_VECTOR_PROIRTY32     (SEP6200_VIC_BASE + 0x180)
+#define    SEP6200_VIC_VECTOR_PROIRTY33     (SEP6200_VIC_BASE + 0x184)
+#define    SEP6200_VIC_VECTOR_PROIRTY34     (SEP6200_VIC_BASE + 0x188)
+#define    SEP6200_VIC_VECTOR_PROIRTY35     (SEP6200_VIC_BASE + 0x18C)
+#define    SEP6200_VIC_VECTOR_PROIRTY36     (SEP6200_VIC_BASE + 0x190)
+#define    SEP6200_VIC_VECTOR_PROIRTY37     (SEP6200_VIC_BASE + 0x194)
+#define    SEP6200_VIC_VECTOR_PROIRTY38     (SEP6200_VIC_BASE + 0x198)
+#define    SEP6200_VIC_VECTOR_PROIRTY39     (SEP6200_VIC_BASE + 0x19C)
+#define    SEP6200_VIC_VECTOR_PROIRTY40     (SEP6200_VIC_BASE + 0x1A0)
+#define    SEP6200_VIC_VECTOR_PROIRTY41     (SEP6200_VIC_BASE + 0x1A4)
+#define    SEP6200_VIC_VECTOR_PROIRTY42     (SEP6200_VIC_BASE + 0x1A8)
+#define    SEP6200_VIC_VECTOR_PROIRTY43     (SEP6200_VIC_BASE + 0x1AC)
+#define    SEP6200_VIC_VECTOR_PROIRTY44     (SEP6200_VIC_BASE + 0x1B0)
+#define    SEP6200_VIC_VECTOR_PROIRTY45     (SEP6200_VIC_BASE + 0x1B4)
+#define    SEP6200_VIC_VECTOR_PROIRTY46     (SEP6200_VIC_BASE + 0x1B8)
+#define    SEP6200_VIC_VECTOR_PROIRTY47     (SEP6200_VIC_BASE + 0x1BC)
+#define    SEP6200_VIC_VECTOR_PROIRTY48     (SEP6200_VIC_BASE + 0x1C0)
+#define    SEP6200_VIC_VECTOR_PROIRTY49     (SEP6200_VIC_BASE + 0x1C4)
+#define    SEP6200_VIC_VECTOR_PROIRTY50     (SEP6200_VIC_BASE + 0x1C8)
+#define    SEP6200_VIC_VECTOR_PROIRTY51     (SEP6200_VIC_BASE + 0x1CC)
+#define    SEP6200_VIC_VECTOR_PROIRTY52     (SEP6200_VIC_BASE + 0x1D0)
+#define    SEP6200_VIC_VECTOR_PROIRTY53     (SEP6200_VIC_BASE + 0x1D4)
+#define    SEP6200_VIC_VECTOR_PROIRTY54     (SEP6200_VIC_BASE + 0x1D8)
+#define    SEP6200_VIC_VECTOR_PROIRTY55     (SEP6200_VIC_BASE + 0x1DC)
+#define    SEP6200_VIC_VECTOR_PROIRTY56     (SEP6200_VIC_BASE + 0x1E0)
+#define    SEP6200_VIC_VECTOR_PROIRTY57     (SEP6200_VIC_BASE + 0x1E4)
+#define    SEP6200_VIC_VECTOR_PROIRTY58     (SEP6200_VIC_BASE + 0x1E8)
+#define    SEP6200_VIC_VECTOR_PROIRTY59     (SEP6200_VIC_BASE + 0x1EC)
+#define    SEP6200_VIC_VECTOR_PROIRTY60     (SEP6200_VIC_BASE + 0x1F0)
+#define    SEP6200_VIC_VECTOR_PROIRTY61     (SEP6200_VIC_BASE + 0x1F4)
+#define    SEP6200_VIC_VECTOR_PROIRTY62     (SEP6200_VIC_BASE + 0x1F8)
+#define    SEP6200_VIC_VECTOR_PROIRTY63     (SEP6200_VIC_BASE + 0x1FC)
+
+#define    SEP6200_PMU_PLL_SET              (SEP6200_PMU_BASE + 0x000)
+#define    SEP6200_PMU_APLL_CFG             (SEP6200_PMU_BASE + 0x004)
+#define    SEP6200_PMU_MPLL_GFG             (SEP6200_PMU_BASE + 0x008)
+#define    SEP6200_PMU_DPLL_CFG             (SEP6200_PMU_BASE + 0x00C)
+#define    SEP6200_PMU_PMDR                 (SEP6200_PMU_BASE + 0x010)
+#define    SEP6200_PMU_CLK_GT_CFG1          (SEP6200_PMU_BASE + 0x014)
+#define    SEP6200_PMU_CLK_GT_CFG2          (SEP6200_PMU_BASE + 0x018)
+#define    SEP6200_PMU_PWR_GT_CFG           (SEP6200_PMU_BASE + 0x01C)
+#define    SEP6200_PMU_AHB_CLK_CFG          (SEP6200_PMU_BASE + 0x020)
+#define    SEP6200_PMU_ARM_CLK_CFG          (SEP6200_PMU_BASE + 0x024)
+#define    SEP6200_PMU_DDR_CLK_CFG          (SEP6200_PMU_BASE + 0x028)
+#define    SEP6200_PMU_PIX_CLK_CFG          (SEP6200_PMU_BASE + 0x02C)
+#define    SEP6200_PMU_GPU_CLK2X_CFG        (SEP6200_PMU_BASE + 0x030)
+#define    SEP6200_PMU_DIV_SET              (SEP6200_PMU_BASE + 0x034)
+#define    SEP6200_PMU_CRYSTAL_CFG          (SEP6200_PMU_BASE + 0x038)
+#define    SEP6200_PMU_MSK_WAKEUP           (SEP6200_PMU_BASE + 0x03C)
+#define    SEP6200_PMU_RTCR                 (SEP6200_PMU_BASE + 0x040)
+#define    SEP6200_PMU_CLR_WAKEUP           (SEP6200_PMU_BASE + 0x044)
+#define    SEP6200_PMU_WAKEUP_TIME          (SEP6200_PMU_BASE + 0x048)
+#define    SEP6200_PMU_SLEEP_FLAG           (SEP6200_PMU_BASE + 0x04C)
+#define    SEP6200_PMU_WAIT_PWR_SWITCH      (SEP6200_PMU_BASE + 0x050)
+#define    SEP6200_PMU_PWR_STATE            (SEP6200_PMU_BASE + 0x054)
+#define    SEP6200_PMU_INT_POL_SEL          (SEP6200_PMU_BASE + 0x058)
+#define    SEP6200_PMU_PLLLD                (SEP6200_PMU_BASE + 0x05C)
+#define    SEP6200_PMU_IC_ENABLE            (SEP6200_PMU_BASE + 0x060)
+#define    SEP6200_PMU_IC_TAR               (SEP6200_PMU_BASE + 0x064)
+#define    SEP6200_PMU_IC_SCL_LCNT          (SEP6200_PMU_BASE + 0x068)
+#define    SEP6200_PMU_IC_SCL_HCNT          (SEP6200_PMU_BASE + 0x06C)
+#define    SEP6200_PMU_IC_DATA_CMD          (SEP6200_PMU_BASE + 0x070)
+#define    SEP6200_PMU_IC_STATE             (SEP6200_PMU_BASE + 0x074)
+#define    SEP6200_PMU_IC_SET               (SEP6200_PMU_BASE + 0x078)
+#define    SEP6200_PMU_HA_PWR_OFF_DAT       (SEP6200_PMU_BASE + 0x07C)
+#define    SEP6200_PMU_HA_PWR_ON_DAT        (SEP6200_PMU_BASE + 0x080)
+#define    SEP6200_PMU_HA_PWR_OFF_DAT_CNT   (SEP6200_PMU_BASE + 0x084)
+#define    SEP6200_PMU_HA_PWR_ON_DAT_CNT    (SEP6200_PMU_BASE + 0x088)
+#define    SEP6200_PMU_PWR_OFF_TIME         (SEP6200_PMU_BASE + 0x08C)
+#define    SEP6200_PMU_PWR_ON_TIME          (SEP6200_PMU_BASE + 0x090)
+#define    SEP6200_PMU_PWR_ON_POL_SEL       (SEP6200_PMU_BASE + 0x094)
+#define    SEP6200_PMU_RETURN_ADDR          (SEP6200_PMU_BASE + 0x098)
+#define    SEP6200_PMU_INT                  (SEP6200_PMU_BASE + 0x09C)
+
+/* define the interrupt source number */
+#define    INTSRC_RESERVE2      63
+#define    INTSRC_RESERVE1      62
+#define    INTSRC_LCDC          61
+#define    INTSRC_GPU           60
+#define    INTSRC_VPU           59
+#define    INTSRC_TIMER3        58
+#define    INTSRC_TIMER2        57
+#define    INTSRC_TIMER1        56
+#define    INTSRC_NAND          55
+#define    INTSRC_I2S           54
+#define    INTSRC_I2C3          53
+#define    INTSRC_I2C2          52
+#define    INTSRC_I2C1          51
+#define    INTSRC_SSI3          50
+#define    INTSRC_SSI2          49
+#define    INTSRC_SSI1          48
+#define    INTSRC_SDIO2         47
+#define    INTSRC_SDIO1         46
+#define    INTSRC_UART3         45
+#define    INTSRC_UART2         44
+#define    INTSRC_UART1         43
+#define    INTSRC_UART0         42
+#define    INTSRC_PWM           41
+#define    INTSRC_USB           40
+#define    INTSRC_USBDMA        39
+#define    INTSRC_DMAC2         38
+#define    INTSRC_DMAC1         37
+#define    INTSRC_PMUIRQ_A11    36
+#define    INTSRC_DMAIRQ_A11    35
+#define    INTSRC_GPS           34
+#define    INTSRC_RTC           33
+#define    INTSRC_RESERVED16    32
+#define    INTSRC_PORTE12       31
+#define    INTSRC_PORTE11       30
+#define    INTSRC_PORTE10       29
+#define    INTSRC_PORTE9        28
+#define    INTSRC_PORTE5        27
+#define    INTSRC_PORTE4        26
+#define    INTSRC_PORTD9        25
+#define    INTSRC_PORTD8        24
+#define    INTSRC_PORTD3        23
+#define    INTSRC_PORTD2        22
+#define    INTSRC_PORTD1        21
+#define    INTSRC_PORTD0        20
+#define    INTSRC_PORTC3        19
+#define    INTSRC_PORTC2        18
+#define    INTSRC_PORTC1        17
+#define    INTSRC_PORTC0        16
+#define    INTSRC_EXT15         15
+#define    INTSRC_EXT14         14
+#define    INTSRC_EXT13         13
+#define    INTSRC_EXT12         12
+#define    INTSRC_EXT11         11
+#define    INTSRC_EXT10         10
+#define    INTSRC_EXT9          9
+#define    INTSRC_EXT8          8
+#define    INTSRC_EXT7          7
+#define    INTSRC_EXT6          6
+#define    INTSRC_EXT5          5
+#define    INTSRC_EXT4          4
+#define    INTSRC_AO_EXT3       3
+#define    INTSRC_AO_EXT2       2
+#define    INTSRC_AO_EXT1       1
+#define    INTSRC_AO_EXT0       0
+
+
+typedef    char                 S8;        /* signed 8-bit integer */
+typedef    short                S16;       /* signed 16-bit integer */
+typedef    long                 S32;       /* signed 32-bit integer */
+typedef    unsigned char        U8;        /* unsigned 8-bit integer */
+typedef    unsigned short       U16;       /* unsigned 16-bit integer */
+typedef    unsigned long        U32;       /* unsigned 32-bit integer */
+
+typedef    volatile U32 *       RP;
+typedef    volatile U16 *       RP16;
+typedef    volatile U8  *       RP8;
+
+typedef    void                 *VP;       /* pointer to an unpredictable data type */
+typedef    void                 (*FP)();   /* program start address */
+
+#ifndef    _BOOL_TYPE_
+#define    _BOOL_TYPE_
+typedef    int                  BOOL;	     /* Boolean value.  TRUE (1) or FALSE (0). */
+#endif
+
+typedef    int                  ER;         /* Error code.  A signed integer. */
+
+/**
+ * IO definitions
+ *
+ * define access restrictions to peripheral registers
+ */
+
+#define     __I     volatile const            /*!< defines 'read only' permissions      */
+#define     __O     volatile                  /*!< defines 'write only' permissions     */
+#define     __IO    volatile                  /*!< defines 'read / write' permissions   */
+#define     __iomem volatile
+
+
+/*Macros for debug*/
+
+#define EOUT(fmt,...) \
+	do \
+	{ 	\
+		rt_kprintf("EOUT:(%s:%i)  ",__FILE__,__LINE__); \
+		rt_kprintf(fmt,##__VA_ARGS__); \
+	}while(0)
+
+#define RT_DEBUG
+#ifdef RT_DEBUG
+	#define DBOUT(fmt,...) \
+	do \
+	{ 	\
+		rt_kprintf("DBOUT:(%s:%i)  ",__FILE__,__LINE__); \
+		rt_kprintf(fmt,##__VA_ARGS__); \
+	}while(0)
+#else
+	#define DBOUT(fmt,...) \
+	do{}while(0)
+#endif
+
+#ifdef	RT_DEBUG
+	#define ASSERT(arg) \
+	if((arg) == 0) \
+	{		\
+		while(1) \
+		{		  \
+			rt_kprintf("have a assert failure\n"); \
+		}										 \
+	}
+#else
+	#define ASSERT(arg) \
+	do		\
+	{		 \
+	}while(0)
+#endif
+
+
+#define write_reg(reg,value) \
+	do \
+	{ \
+		*(RP)(reg) = value; \
+	}while(0)
+
+#define read_reg(reg) (*(RP)reg)
+
+
+struct rt_hw_register
+{
+	rt_uint32_t r0;
+	rt_uint32_t r1;
+	rt_uint32_t r2;
+	rt_uint32_t r3;
+	rt_uint32_t r4;
+	rt_uint32_t r5;
+	rt_uint32_t r6;
+	rt_uint32_t r7;
+	rt_uint32_t r8;
+	rt_uint32_t r9;
+	rt_uint32_t r10;
+	rt_uint32_t r11;
+	rt_uint32_t r12;
+	rt_uint32_t r13;
+	rt_uint32_t r14;
+	rt_uint32_t r15;
+	rt_uint32_t r16;
+	rt_uint32_t r17;
+	rt_uint32_t r18;
+	rt_uint32_t r19;
+	rt_uint32_t r20;
+	rt_uint32_t r21;
+	rt_uint32_t r22;
+	rt_uint32_t r23;
+	rt_uint32_t r24;
+	rt_uint32_t sb;
+	rt_uint32_t sl;
+	rt_uint32_t fp;
+	rt_uint32_t ip;
+	rt_uint32_t sp;
+	rt_uint32_t lr;
+	rt_uint32_t pc;
+	rt_uint32_t asr;
+	rt_uint32_t bsr;
+	rt_uint32_t ORIG_r0;
+};
+
+/*@}*/
+
+#endif
diff --git a/libcpu/unicore32/sep6200/serial.c b/libcpu/unicore32/sep6200/serial.c
new file mode 100644
index 0000000000..aeb9d69490
--- /dev/null
+++ b/libcpu/unicore32/sep6200/serial.c
@@ -0,0 +1,279 @@
+/*
+ * File      : serial.c
+ * This file is part of RT-Thread RTOS
+ * COPYRIGHT (C) 2006, RT-Thread Development Team
+ *
+ * The license and distribution terms for this file may be
+ * found in the file LICENSE in this distribution or at
+ * http://openlab.rt-thread.com/license/LICENSE
+ *
+ * Change Logs:
+ * Date           Author       Notes
+ * 2013-03-16	    Peng Fan     Modified from sep4020
+ */
+#include <rtthread.h>
+#include <rthw.h>
+#include "serial.h"
+
+/**
+ * @addtogroup SEP6200
+ */
+/*@{*/
+
+/* RT-Thread Device Interface */
+/**
+ * This function initializes serial
+ */
+static rt_err_t rt_serial_init (rt_device_t dev)
+{
+	struct serial_device* uart = (struct serial_device*) dev->user_data;
+
+	if (!(dev->flag & RT_DEVICE_FLAG_ACTIVATED))
+	{
+
+		if (dev->flag & RT_DEVICE_FLAG_INT_RX)
+		{
+			rt_memset(uart->int_rx->rx_buffer, 0,
+				sizeof(uart->int_rx->rx_buffer));
+			uart->int_rx->read_index = uart->int_rx->save_index = 0;
+		}
+
+		if (dev->flag & RT_DEVICE_FLAG_INT_TX)
+		{
+			rt_memset(uart->int_tx->tx_buffer, 0,
+				sizeof(uart->int_tx->tx_buffer));
+			uart->int_tx->write_index = uart->int_tx->save_index = 0;
+		}
+
+		dev->flag |= RT_DEVICE_FLAG_ACTIVATED;
+	}
+
+	return RT_EOK;
+}
+
+/* save a char to serial buffer */
+static void rt_serial_savechar(struct serial_device* uart, char ch)
+{
+	rt_base_t level;
+
+	/* disable interrupt */
+	level = rt_hw_interrupt_disable();
+
+	uart->int_rx->rx_buffer[uart->int_rx->save_index] = ch;
+	uart->int_rx->save_index ++;
+	if (uart->int_rx->save_index >= UART_RX_BUFFER_SIZE)
+		uart->int_rx->save_index = 0;
+
+	/* if the next position is read index, discard this 'read char' */
+	if (uart->int_rx->save_index == uart->int_rx->read_index)
+	{
+		uart->int_rx->read_index ++;
+		if (uart->int_rx->read_index >= UART_RX_BUFFER_SIZE)
+			uart->int_rx->read_index = 0;
+	}
+
+	/* enable interrupt */
+	rt_hw_interrupt_enable(level);
+}
+
+static rt_err_t rt_serial_open(rt_device_t dev, rt_uint16_t oflag)
+{
+	RT_ASSERT(dev != RT_NULL);
+	return RT_EOK;
+}
+
+static rt_err_t rt_serial_close(rt_device_t dev)
+{
+	RT_ASSERT(dev != RT_NULL);
+	return RT_EOK;
+}
+
+static rt_size_t rt_serial_read (rt_device_t dev, rt_off_t pos, void* buffer, rt_size_t size)
+{
+	rt_uint8_t* ptr;
+	rt_err_t err_code;
+	struct serial_device* uart;
+
+	ptr = buffer;
+	err_code = RT_EOK;
+	uart = (struct serial_device*)dev->user_data;
+
+	if (dev->flag & RT_DEVICE_FLAG_INT_RX)
+	{
+		rt_base_t level;
+
+		/* interrupt mode Rx */
+		while (size)
+		{
+			if (uart->int_rx->read_index != uart->int_rx->save_index)
+			{
+				*ptr++ = uart->int_rx->rx_buffer[uart->int_rx->read_index];
+				size --;
+
+				/* disable interrupt */
+				level = rt_hw_interrupt_disable();
+
+				uart->int_rx->read_index ++;
+				if (uart->int_rx->read_index >= UART_RX_BUFFER_SIZE)
+					uart->int_rx->read_index = 0;
+
+				/* enable interrupt */
+				rt_hw_interrupt_enable(level);
+			}
+			else
+			{
+				/* set error code */
+				err_code = -RT_EEMPTY;
+				break;
+			}
+		}
+	}
+	else
+	{
+		/* polling mode */
+		while ((rt_uint32_t)ptr - (rt_uint32_t)buffer < size)
+		{
+			while (uart->uart_device->lsr & USTAT_RCV_READY)
+			{
+				*ptr = uart->uart_device->dlbl_fifo.txfifo & 0xff;
+				ptr ++;
+			}
+		}
+	}
+
+	/* set error code */
+	rt_set_errno(err_code);
+	return (rt_uint32_t)ptr - (rt_uint32_t)buffer;
+}
+
+static rt_size_t rt_serial_write (rt_device_t dev, rt_off_t pos, const void* buffer, rt_size_t size)
+{
+	rt_uint8_t* ptr;
+	rt_err_t err_code;
+	struct serial_device* uart;
+
+	err_code = RT_EOK;
+	ptr = (rt_uint8_t*)buffer;
+	uart = (struct serial_device*)dev->user_data;
+
+	if (dev->flag & RT_DEVICE_FLAG_INT_TX)
+	{
+		/* interrupt mode Tx */
+		while (uart->int_tx->save_index != uart->int_tx->write_index)
+		{
+			/* save on tx buffer */
+			uart->int_tx->tx_buffer[uart->int_tx->save_index] = *ptr++;
+
+			-- size;
+
+			/* move to next position */
+			uart->int_tx->save_index ++;
+
+			/* wrap save index */
+			if (uart->int_tx->save_index >= UART_TX_BUFFER_SIZE)
+				uart->int_tx->save_index = 0;
+		}
+
+		/* set error code */
+		if (size > 0)
+			err_code = -RT_EFULL;
+	}
+	else
+	{
+		/* polling mode */
+		while (size)
+		{
+			/*
+			 * to be polite with serial console add a line feed
+			 * to the carriage return character
+			 */
+			if (*ptr == '\n' && (dev->flag & RT_DEVICE_FLAG_STREAM))
+			{
+				while (!(uart->uart_device->lsr & USTAT_TXB_EMPTY));
+				uart->uart_device->dlbl_fifo.txfifo = '\r';
+			}
+
+			while (!(uart->uart_device->lsr & USTAT_TXB_EMPTY));
+			uart->uart_device->dlbl_fifo.txfifo = (*ptr & 0x1FF);
+
+			++ptr; --size;
+		}
+	}
+
+	/* set error code */
+	rt_set_errno(err_code);
+
+	return (rt_uint32_t)ptr - (rt_uint32_t)buffer;
+}
+
+static rt_err_t rt_serial_control (rt_device_t dev, rt_uint8_t cmd, void *args)
+{
+	RT_ASSERT(dev != RT_NULL);
+
+	switch (cmd)
+	{
+	case RT_DEVICE_CTRL_SUSPEND:
+		/* suspend device */
+		dev->flag |= RT_DEVICE_FLAG_SUSPENDED;
+		break;
+
+	case RT_DEVICE_CTRL_RESUME:
+		/* resume device */
+		dev->flag &= ~RT_DEVICE_FLAG_SUSPENDED;
+		break;
+	}
+
+	return RT_EOK;
+}
+
+/*
+ * serial register
+ */
+rt_err_t rt_hw_serial_register(rt_device_t device, const char* name, rt_uint32_t flag, struct serial_device *serial)
+{
+	RT_ASSERT(device != RT_NULL);
+
+	device->type 		= RT_Device_Class_Char;
+	device->rx_indicate = RT_NULL;
+	device->tx_complete = RT_NULL;
+	device->init 		= rt_serial_init;
+	device->open		= rt_serial_open;
+	device->close		= rt_serial_close;
+	device->read 		= rt_serial_read;
+	device->write 		= rt_serial_write;
+	device->control 	= rt_serial_control;
+	device->user_data   = serial;
+
+	/* register a character device */
+	return rt_device_register(device, name, RT_DEVICE_FLAG_RDWR | flag);
+}
+
+/* ISR for serial interrupt */
+void rt_hw_serial_isr(rt_device_t device)
+{
+	struct serial_device* uart = (struct serial_device*) device->user_data;
+
+	/* interrupt mode receive */
+	RT_ASSERT(device->flag & RT_DEVICE_FLAG_INT_RX);
+
+	/* save on rx buffer */
+	while (uart->uart_device->lsr & USTAT_RCV_READY)
+	{
+		rt_serial_savechar(uart, uart->uart_device->dlbl_fifo.rxfifo & 0xff);
+	}
+
+	/* invoke callback */
+	if (device->rx_indicate != RT_NULL)
+	{
+		rt_size_t rx_length;
+
+		/* get rx length */
+		rx_length = uart->int_rx->read_index > uart->int_rx->save_index ?
+			UART_RX_BUFFER_SIZE - uart->int_rx->read_index + uart->int_rx->save_index :
+			uart->int_rx->save_index - uart->int_rx->read_index;
+
+		device->rx_indicate(device, rx_length);
+	}
+}
+
+/*@}*/
diff --git a/libcpu/unicore32/sep6200/serial.h b/libcpu/unicore32/sep6200/serial.h
new file mode 100644
index 0000000000..7d06741a56
--- /dev/null
+++ b/libcpu/unicore32/sep6200/serial.h
@@ -0,0 +1,96 @@
+/*
+ * File      : serial.c
+ * This file is part of RT-Thread RTOS
+ * COPYRIGHT (C) 2006, RT-Thread Development Team
+ *
+ * The license and distribution terms for this file may be
+ * found in the file LICENSE in this distribution or at
+ * http://openlab.rt-thread.com/license/LICENSE
+ *
+ * Change Logs:
+ * Date           Author       Notes
+ * 2006-03-13     Bernard      first version
+ * 2009-04-20     yi.qiu       modified according bernard's stm32 version
+ * 2010-10-6      wangmeng     added sep4020 surpport
+ * 2013-7-15      Peng Fan     Modified from sep4020
+ */
+
+#ifndef __SERIAL_H__
+#define __SERIAL_H__
+
+#include <sep6200.h>
+
+#define	USTAT_RCV_READY		0x01   	/* receive data ready */
+#define USTAT_OVERRUN		0x02	/* overrun */
+#define USTAT_PARITY_ERR	0x04	/* parity error */
+#define USTAT_FRAME_ERROR	0x08	/* frame error */
+#define USTAT_BREAK		0x10	/* break */
+#define	USTAT_TXB_EMPTY		0x40   	/* tx buffer empty */
+#define USTAT_RCV_ERR		0x80	/* receive error */
+
+#define BPS					115200	/* serial baudrate */
+
+#define UART_RX_BUFFER_SIZE		64
+#define UART_TX_BUFFER_SIZE		64
+
+/*For sep6200's uart have several secondary function*/
+/*we use union to decribe it*/
+
+union dlbl_fifo
+{
+	rt_uint32_t dlbl;
+	rt_uint32_t rxfifo;
+	rt_uint32_t txfifo;
+};
+
+union dlbh_ier
+{
+	rt_uint32_t dlbh;
+	rt_uint32_t ier;
+};
+
+union iir_fcr
+{
+	rt_uint32_t iir;
+	rt_uint32_t fcr;
+};
+
+struct serial_int_rx
+{
+	rt_uint8_t  rx_buffer[UART_RX_BUFFER_SIZE];
+	rt_uint32_t read_index, save_index;
+};
+
+struct serial_int_tx
+{
+	rt_uint8_t  tx_buffer[UART_TX_BUFFER_SIZE];
+	rt_uint32_t write_index, save_index;
+};
+
+typedef struct uartport
+{
+	union dlbl_fifo dlbl_fifo;
+	union dlbh_ier	dlbh_ier;
+	union iir_fcr	iir_fcr;
+	rt_uint32_t lcr;
+	rt_uint32_t mcr;
+	rt_uint32_t lsr;
+	rt_uint32_t msr;
+}uartport;
+
+struct serial_device
+{
+	uartport* uart_device;
+
+	/* rx structure */
+	struct serial_int_rx* int_rx;
+
+	/* tx structure */
+	struct serial_int_tx* int_tx;
+};
+
+rt_err_t rt_hw_serial_register(rt_device_t device, const char* name, rt_uint32_t flag, struct serial_device *serial);
+
+void rt_hw_serial_isr(rt_device_t device);
+
+#endif
diff --git a/libcpu/unicore32/sep6200/stack.c b/libcpu/unicore32/sep6200/stack.c
new file mode 100644
index 0000000000..f6e6399674
--- /dev/null
+++ b/libcpu/unicore32/sep6200/stack.c
@@ -0,0 +1,78 @@
+/*
+ * File      : stack.c
+ * This file is part of RT-Thread RTOS
+ * COPYRIGHT (C) 2006, RT-Thread Development Team
+ *
+ * The license and distribution terms for this file may be
+ * found in the file LICENSE in this distribution or at
+ * http://openlab.rt-thread.com/license/LICENSE
+ *
+ * Change Logs:
+ * Date           Author       Notes
+ * 2013-7-14      Peng Fan     Modifiled from sep4020
+ */
+
+#include <rtthread.h>
+#include <sep6200.h>
+
+/**
+ * @addtogroup sep6200
+ */
+/*@{*/
+
+/**
+ * This function will initialize thread stack
+ *
+ * @param tentry the entry of thread
+ * @param parameter the parameter of entry
+ * @param stack_addr the beginning stack address
+ * @param texit the function will be called when thread exit
+ *
+ * @return stack address
+ */
+
+rt_uint8_t *rt_hw_stack_init(void *tentry, void *parameter,
+	rt_uint8_t *stack_addr, void *texit)
+{
+	rt_uint32_t *stk;
+
+	stk 	 = (rt_uint32_t*)stack_addr;
+	*(stk) 	 = (rt_uint32_t)tentry;			/* entry point */
+	*(--stk) = (rt_uint32_t)texit;			/* lr */
+	*(--stk) = 0;							/* r28 */
+	*(--stk) = 0;							/* r27 */
+	*(--stk) = 0;							/* r26 */
+	*(--stk) = 0;							/* r25 */
+	*(--stk) = 0;							/* r24 */
+	*(--stk) = 0;							/* r23 */
+	*(--stk) = 0;							/* r22 */
+	*(--stk) = 0;							/* r21 */
+	*(--stk) = 0;							/* r20 */
+	*(--stk) = 0;							/* r19 */
+	*(--stk) = 0;							/* r18 */
+	*(--stk) = 0;							/* r17 */
+	*(--stk) = 0;							/* r16 */
+	*(--stk) = 0;							/* r15 */
+	*(--stk) = 0;							/* r14 */
+	*(--stk) = 0;							/* r13 */
+	*(--stk) = 0;							/* r12 */
+	*(--stk) = 0;							/* r11 */
+	*(--stk) = 0;							/* r10 */
+	*(--stk) = 0;							/* r9 */
+	*(--stk) = 0;							/* r8 */
+	*(--stk) = 0;							/* r7 */
+	*(--stk) = 0;							/* r6 */
+	*(--stk) = 0;							/* r5 */
+	*(--stk) = 0;							/* r4 */
+	*(--stk) = 0;							/* r3 */
+	*(--stk) = 0;							/* r2 */
+	*(--stk) = 0;							/* r1 */
+	*(--stk) = (rt_uint32_t)parameter; /* r0 : argument */
+	*(--stk) = Mode_PRIV;					/* asr */
+	*(--stk) = Mode_PRIV;					/* bsr */ /*why both PRIV do not need switch?*/
+
+	/* return task's current stack address */
+	return (rt_uint8_t *)stk;
+}
+
+/*@}*/
diff --git a/libcpu/unicore32/sep6200/start_gcc.S b/libcpu/unicore32/sep6200/start_gcc.S
new file mode 100644
index 0000000000..c7aeaa135a
--- /dev/null
+++ b/libcpu/unicore32/sep6200/start_gcc.S
@@ -0,0 +1,374 @@
+/*
+ * File      : start.S
+ * This file is part of RT-Thread RTOS
+ * COPYRIGHT (C) 2006, RT-Thread Development Team
+ *
+ * The license and distribution terms for this file may be
+ * found in the file LICENSE in this distribution or at
+ * http:/*openlab.rt-thread.com/license/LICENSE
+ *
+ * Change Logs:
+ * Date           Author       Notes
+ * 2013-07-13     Peng Fan     First implementation
+ */
+
+
+#define CONFIG_STACKSIZE 	1024
+#define S_FRAME_SIZE 		132
+
+#define S_OLD_R0 			132
+#define S_PSR  				128
+#define S_PC  				124
+#define S_LR  				120
+#define S_SP  				116
+
+#define S_IP  				112
+#define S_FP  				108
+#define S_R26  				104
+#define S_R25  				100
+#define S_R24  				96
+#define S_R23  				92
+#define S_R22  				88
+#define S_R21  				84
+#define S_R20 				80
+#define S_R19  				76
+#define S_R18  				72
+#define S_R17  				68
+#define S_R16  				64
+#define S_R15  				60
+#define S_R14  				56
+#define S_R13  				52
+#define S_R12  				48
+#define S_R11  				44
+#define S_R10  				40
+#define S_R9  				36
+#define S_R8  				32
+#define S_R7  				28
+#define S_R6  				24
+#define S_R5  				20
+#define S_R4  				16
+#define S_R3  				12
+#define S_R2  				8
+#define S_R1  				4
+#define S_R0 				0
+
+.equ 	USERMODE,			0x10
+.equ 	REALMODE,			0x11
+.equ 	IRQMODE,			0x12
+.equ 	PRIVMODE,			0x13
+.equ 	TRAPMODE,			0x17
+.equ 	EXTNMODE,			0x1b
+.equ 	MODEMASK,			0x1f
+.equ 	NOINT,				0xc0
+
+.equ 	RAM_BASE,			0x00000000	/*Start address of RAM		*/
+
+
+
+/*
+ *************************************************************************
+ *
+ * Jump vector table
+ *
+ *************************************************************************
+ */
+
+.section .init, "ax"
+.code 32
+.globl _start
+_start:
+     b   reset
+     ldw pc, _extend_handle
+     ldw pc, _swi_handle
+     ldw pc, _iabort_handle
+     ldw pc, _dabort_handle
+     ldw pc, _reserve_handle
+     ldw pc, _IRQ_handle
+     ldw pc, _FIQ_handle
+
+_extend_handle:     .word extend_handle
+_swi_handle:        .word swi_handle
+_iabort_handle:     .word iabort_handle
+_dabort_handle:     .word dabort_handle
+_reserve_handle:    .word reserve_handle
+_IRQ_handle:        .word IRQ_handle
+_FIQ_handle:        .word FIQ_handle
+    .balignl 16,0xdeadbeef
+
+/*
+ *************************************************************************
+ *
+ * Startup Code (reset vector)
+ * relocate armboot to ram
+ * setup stack
+ * jump to second stage
+ *
+ *************************************************************************
+ */
+.global _TEXT_BASE
+_TEXT_BASE:
+     .word   TEXT_BASE
+
+.globl _rtthread_start
+_rtthread_start:
+     .word   _start
+
+.globl _rtthread_end
+_rtthread_end:
+     .word   _end
+
+.globl _bss_start
+_bss_start:
+     .word   __bss_start     @ load end address
+
+.globl _bss_end
+_bss_end:
+    .word   __bss_end
+
+.globl IRQ_STACK_START
+IRQ_STACK_START:
+    .word   _irq_stack_start + 10240 - 4
+
+.globl FIQ_STACK_START
+FIQ_STACK_START:
+     .word   _fiq_stack_start +1024
+
+/*peng not sure*/
+.globl UNDEFINED_STACK_START
+UNDEFINED_STACK_START:
+	.word _undefined_stack_start + CONFIG_STACKSIZE
+
+.globl ABORT_STACK_START
+ABORT_STACK_START:
+	.word _abort_stack_start + CONFIG_STACKSIZE
+
+.globl _STACK_START
+_STACK_START:
+	.word _priv_stack_start + 40960 - 4
+
+.equ  SEP6200_VIC_BASE,		 0xb0000000
+.equ  SEP6200_SYSCTL_BASE,	 0xb0008000
+/* ----------------------------------entry------------------------------*/
+reset:
+	/* set the cpu to PRIV mode and disable cpu interrupt */
+	mov		r0, asr
+	andn		r0, r0, #0xff
+	or		r0, r0, #PRIVMODE|NOINT
+	mov.a		asr, r0
+
+	/* mask all IRQs by clearing all bits in the INTMRs */
+	ldw	r1, =SEP6200_VIC_BASE
+	ldw 	r0, =0xffffffff
+	stw	r0, [r1+], #0x20 /*interrupt enable clear*/
+	stw	r0, [r1+], #0x24
+
+
+	/*remap ddr to 0x00000000 address*/
+	ldw	r1, =SEP6200_SYSCTL_BASE
+	ldw	r0, [r1+]
+	ldw	r2, =0x80000000
+	or	r0, r0, r2
+	stw	r2, [r1+]
+
+	/* set interrupt vector */
+	/*do nothing here for vector*/
+
+	/* setup stack */
+	b.l		stack_setup
+
+	ldw	r12, =0x100
+	ldw	r0, = 0x40000000
+	ldw	r1, = 0x00000000
+copy_vetor:
+	ldw	r2, [r0]
+	stw	r2, [r1]
+	add	r0, r0, #4
+	add	r1, r1, #4
+	sub	r12, r12, #4
+	cmpsub.a	r12, #0
+	bne	copy_vetor
+
+	/* clear .bss */
+	ldw   	r0, _bss_start         /* bss start   */
+	ldw   	r1, _bss_end           /* bss end     */
+	mov   	r2,#0                  /* get a zero  */
+
+
+bss_loop:
+	stw r2, [r0]            @ clear loop...
+	add r0, r0, #4
+	cmpsub.a    r0, r1
+	bel bss_loop
+
+	/* call C++ constructors of global objects 							*/
+	ldw	r0, =__ctors_start__
+	ldw	r1, =__ctors_end__
+
+ctor_loop:
+	cmpsub.a	r0, r1
+	beq	ctor_end
+	ldw.w	r2, [r0]+, #4
+	stm.w	(r0, r1), [sp-]
+	add	lr, pc, #4
+	mov	pc, r2
+	ldm.w	(r0, r1), [sp]+
+	b ctor_loop
+ctor_end:
+
+  /*enable interrupt*/
+	mov 	r0, asr
+	andn 	r1, r0, #NOINT
+	mov.a 	asr, r1
+
+	/* start RT-Thread Kernel 		*/
+	ldw		pc, _rtthread_startup
+
+_rtthread_startup:
+	.word rtthread_startup
+
+/*
+ *************************************************************************
+ *
+ * Interrupt handling
+ *
+ *************************************************************************
+ */
+
+/* exception handlers */
+/*Just simple implementation here peng*/
+	.align  5
+extend_handle:
+    b extend_handle
+swi_handle:
+    b swi_handle
+iabort_handle:
+    b iabort_handle
+dabort_handle:
+    b dabort_handle
+reserve_handle:
+    b reserve_handle
+
+.globl 		rt_interrupt_enter
+.globl 		rt_interrupt_leave
+.globl 		rt_thread_switch_interrupt_flag
+.globl 		rt_interrupt_from_thread
+.globl 		rt_interrupt_to_thread
+IRQ_handle:
+
+  stm.w (lr), [sp-]
+  stm.w (r16 - r28), [sp-]
+  stm.w (r0 - r15), [sp-]
+
+	b.l		rt_interrupt_enter
+	b.l		rt_hw_trap_irq
+	b.l		rt_interrupt_leave
+
+	/* if rt_thread_switch_interrupt_flag set, jump to _interrupt_thread_switch and don't return */
+	ldw		r0, =rt_thread_switch_interrupt_flag
+	ldw		r1, [r0+]
+	cmpsub.a	r1, #1
+	beq		_interrupt_thread_switch
+
+  ldm.w (r0 - r15), [sp]+
+  ldm.w (r16 - r28), [sp]+
+  ldm.w (lr), [sp]+
+  mov.a pc, lr
+
+	.align	5
+FIQ_handle:
+    mov r0, #0x44
+    b.l printhex
+	mov pc, lr
+
+_interrupt_thread_switch:
+
+	mov		r1,  #0	/* clear rt_thread_switch_interrupt_flag*/
+	stw		r1,  [r0+]
+
+	/*reload register*/
+  ldm.w (r0 - r15), [sp]+
+  ldm.w (r16 - r28), [sp]+
+  ldm.w (lr), [sp]+
+
+	stm.w	(r0-r3), [sp-] /*save r0-r3*/
+
+	mov		r1,  sp
+	add		sp,  sp, #16 /* restore sp */
+	mov		r2,  lr	/* save old task's pc to r2 */
+
+#if 0
+	mov		r3,  bsr /* disable interrupt */
+	/*or		r0,  r3, #NOINT*/
+	mov.a		bsr, r3
+
+	ldw	r0,  =.+8 /* switch to interrupted task's stack */
+	mov.a	pc,  r0 /*switch bsr to asr, irq to priv mode*/
+
+#endif
+  mov r3, bsr
+  mov r0, #0xd3 /*I:F:0:PRIV*/
+  mov.a asr, r0
+
+	stm.w	(r2), [sp-] /* push old task's pc */
+
+	/* push old task's registers */
+	stm.w	(r16, r17, r18, r19, r20, r21, r22, r23, r24, r25, r26, r27, r28, lr), [sp-]
+	stm.w	(r4, r5, r6, r7, r8, r9, r10, r11, r12, r13, r14, r15), [sp-]
+	mov		r4,  r1	/* Special optimised code below		*/
+  mov		r5,  r3 /*pengpengpengpeng*/
+	ldm.w	(r0,r1, r2, r3), [r4]+
+	stm.w	(r0, r1, r2, r3), [sp-] /*push old task's r3-r0*/
+	stm.w	(r5),	 [sp-] /* push old task's asr */
+	mov	r4,  bsr
+	stm.w   (r4), [sp-]	/* push old task's bsr I am not sure peng*/
+
+	ldw		r4,  =rt_interrupt_from_thread
+	ldw		r5,  [r4+]
+	stw		sp,  [r5+]				/* store sp in preempted tasks's TCB*/
+
+	ldw	r6,  =rt_interrupt_to_thread
+	ldw	r6,  [r6+]
+	ldw	sp,  [r6+]	/* get new task's stack pointer	*/
+
+	ldm.w	(r4), [sp]+	/* pop new task's spsr				*/
+	mov.a	bsr, r4
+	ldm.w	(r4), [sp]+	/* pop new task's psr				*/
+	mov.a	asr, r4
+
+	/* pop new task's r0-r28,lr & pc */
+
+  ldm.w (r0 - r15), [sp]+
+  ldm.w (r16 - r28), [sp]+
+  ldm.w (lr), [sp]+
+  /*peng*/
+  ldm.w (pc), [sp]+
+#if 0
+  mov r0, lr
+  b.l printhex
+  ldm.w (r0), [sp]+
+  b.l printhex
+#endif
+
+stack_setup:
+	/*irq*/
+  mov ip, lr
+	mov		r0, asr
+	andn  r0, r0, #0x1f
+	or		r0, r0, #IRQMODE|NOINT
+	mov.a		asr, r0 /*IRQMODE*/
+  ldw   r0, =IRQ_STACK_START
+  ldw   sp, [r0+]
+	/*ldw		sp, IRQ_STACK_START*/
+
+	/*priv*/
+	mov		r0, asr
+	andn    	r0, r0, #0x1f
+	or		r0, r0, #PRIVMODE|NOINT
+	mov.a		asr, r0 /*PRIVMODE*/
+  ldw   r0, =_STACK_START
+  ldw   sp, [r0+]
+	/*ldw		sp, _STACK_START*/
+  mov lr, ip
+	/*fiq and other mode is not implemented in code here*/
+	mov 		pc, lr /*lr may not be valid for the mode changes*/
+/*/*}*/
diff --git a/libcpu/unicore32/sep6200/trace.c b/libcpu/unicore32/sep6200/trace.c
new file mode 100644
index 0000000000..b842e5dd56
--- /dev/null
+++ b/libcpu/unicore32/sep6200/trace.c
@@ -0,0 +1,6 @@
+#include <rtthread.h>
+
+void rt_hw_backtrace(rt_uint32_t *fp, rt_uint32_t thread_entry)
+{
+
+}
diff --git a/libcpu/unicore32/sep6200/trap.c b/libcpu/unicore32/sep6200/trap.c
new file mode 100644
index 0000000000..22689c42eb
--- /dev/null
+++ b/libcpu/unicore32/sep6200/trap.c
@@ -0,0 +1,164 @@
+/*
+ * File      : trap.c
+ * This file is part of RT-Thread RTOS
+ * COPYRIGHT (C) 2006, RT-Thread Development Team
+ *
+ * The license and distribution terms for this file may be
+ * found in the file LICENSE in this distribution or at
+ * http://openlab.rt-thread.com/license/LICENSE
+ *
+ * Change Logs:
+ * Date           Author       Notes
+ * 2013-03-16     Peng Fan     Modifiled from sep4020
+ */
+
+#include <rtthread.h>
+#include <rthw.h>
+
+#include <sep6200.h>
+
+/**
+ * @addtogroup sep6200
+ */
+/*@{*/
+
+extern struct rt_thread *rt_current_thread;
+
+/**
+ * this function will show registers of CPU
+ *
+ * @param regs the registers point
+ */
+
+void rt_hw_show_register (struct rt_hw_register *regs)
+{
+	rt_kprintf("Execption:\n");
+	rt_kprintf("r00:0x%08x r01:0x%08x r02:0x%08x r03:0x%08x\n", regs->r0, regs->r1, regs->r2, regs->r3);
+	rt_kprintf("r04:0x%08x r05:0x%08x r06:0x%08x r07:0x%08x\n", regs->r4, regs->r5, regs->r6, regs->r7);
+	rt_kprintf("r08:0x%08x r09:0x%08x r10:0x%08x r11:0x%08x\n", regs->r8, regs->r9, regs->r10,regs->r11);
+	rt_kprintf("r12:0x%08x r13:0x%08x r14:0x%08x r15:0x%08x\n", regs->r12,regs->r13,regs->r14,regs->r15);
+	rt_kprintf("r16:0x%08x r17:0x%08x r18:0x%08x r19:0x%08x\n", regs->r16,regs->r17,regs->r18,regs->r19);
+	rt_kprintf("r20:0x%08x r21:0x%08x r22:0x%08x r23:0x%08x\n", regs->r20,regs->r21,regs->r22,regs->r23);
+	rt_kprintf("r24:0x%08x sb:0x%08x  sl:0x%08xfp :0x%08x ip :0x%08x\n",regs->r24,regs->sb,regs->sl,regs->fp,regs->ip);
+	rt_kprintf("sp :0x%08x lr :0x%08x pc :0x%08x\n", regs->sp, regs->lr, regs->pc);
+	rt_kprintf("asr:0x%08x bsr:0x%08x\n", regs->asr,regs->bsr);
+}
+
+/**
+ * When unicore comes across an instruction which it cannot handle,
+ * it takes the extn instruction trap.
+ *
+ * @param regs system registers
+ *
+ * @note never invoke this function in application
+ */
+void rt_hw_trap_extn(struct rt_hw_register *regs)
+{
+	rt_hw_show_register(regs);
+
+	rt_kprintf("extn instruction\n");
+	rt_kprintf("thread - %s stack:\n", rt_current_thread->name);
+	rt_hw_backtrace((rt_uint32_t *)regs->fp, (rt_uint32_t)rt_current_thread->entry);
+
+	rt_hw_cpu_shutdown();
+}
+
+/**
+ * The software interrupt instruction (SWI) is used for entering
+ * Supervisor mode, usually to request a particular supervisor
+ * function.
+ *
+ * @param regs system registers
+ *
+ * @note never invoke this function in application
+ */
+void rt_hw_trap_swi(struct rt_hw_register *regs)
+{
+	rt_hw_show_register(regs);
+
+	rt_kprintf("software interrupt\n");
+	rt_hw_cpu_shutdown();
+}
+
+/**
+ * An abort indicates that the current memory access cannot be completed,
+ * which occurs during an instruction prefetch.
+ *
+ * @param regs system registers
+ *
+ * @note never invoke this function in application
+ */
+void rt_hw_trap_pabt(struct rt_hw_register *regs)
+{
+	rt_hw_show_register(regs);
+
+	rt_kprintf("prefetch abort\n");
+	rt_kprintf("thread - %s stack:\n", rt_current_thread->name);
+	rt_hw_backtrace((rt_uint32_t *)regs->fp, (rt_uint32_t)rt_current_thread->entry);
+
+	rt_hw_cpu_shutdown();
+}
+
+/**
+ * An abort indicates that the current memory access cannot be completed,
+ * which occurs during a data access.
+ *
+ * @param regs system registers
+ *
+ * @note never invoke this function in application
+ */
+void rt_hw_trap_dabt(struct rt_hw_register *regs)
+{
+	rt_hw_show_register(regs);
+
+	rt_kprintf("data abort\n");
+	rt_kprintf("thread - %s stack:\n", rt_current_thread->name);
+	rt_hw_backtrace((rt_uint32_t *)regs->fp, (rt_uint32_t)rt_current_thread->entry);
+
+	rt_hw_cpu_shutdown();
+}
+
+/**
+ * Normally, system will never reach here
+ *
+ * @param regs system registers
+ *
+ * @note never invoke this function in application
+ */
+void rt_hw_trap_resv(struct rt_hw_register *regs)
+{
+	rt_kprintf("not used\n");
+	rt_hw_show_register(regs);
+	rt_hw_cpu_shutdown();
+}
+
+extern struct rt_irq_desc isr_table[];
+
+void rt_hw_trap_irq(void)
+{
+  unsigned long intstat;
+  rt_uint32_t irq = 0;
+  rt_isr_handler_t isr_func;
+  void *param;
+
+  /* get the interrupt number */
+	irq = *(RP)(SEP6200_VIC_IRQ_VECTOR_NUM);
+
+  /* get interrupt service routine */
+  isr_func = isr_table[irq].handler;
+  param = isr_table[irq].param;
+
+  /* turn to interrupt service routine */
+  isr_func(irq, param);
+
+#ifdef RT_USING_INTERRUPT_INFO
+	isr_table[irq].counter++;
+#endif /* RT_USING_INTERRUPT_INFO */
+}
+
+void rt_hw_trap_fiq()
+{
+	rt_kprintf("fast interrupt request\n");
+}
+
+/*@}*/