diff options
| author | Grissiom <[email protected]> | 2013-10-20 04:06:56 +0800 |
|---|---|---|
| committer | Grissiom <[email protected]> | 2013-10-20 18:51:45 +0800 |
| commit | 9568669109ffcb3aa6de8d07959795de71d505ae (patch) | |
| tree | 248a5837cad06c061d924b99788a984885cd3494 /libcpu | |
| parent | 2f4329430d548daa0c7b0b3f758c3b3c6776de8d (diff) | |
rm48x50: add GCC support
Diffstat (limited to 'libcpu')
| -rw-r--r-- | libcpu/arm/cortex-r4/cpu.c | 7 | ||||
| -rw-r--r-- | libcpu/arm/cortex-r4/stack.c | 2 |
2 files changed, 7 insertions, 2 deletions
diff --git a/libcpu/arm/cortex-r4/cpu.c b/libcpu/arm/cortex-r4/cpu.c index d1b5c9df54..89369d5209 100644 --- a/libcpu/arm/cortex-r4/cpu.c +++ b/libcpu/arm/cortex-r4/cpu.c @@ -39,6 +39,7 @@ void rt_hw_cpu_shutdown() while (1); } +#ifdef __TI_COMPILER_VERSION__ #ifdef RT_USING_CPU_FFS int __rt_ffs(int value) { @@ -52,7 +53,6 @@ int __rt_ffs(int value) } #endif -#ifdef __TI_COMPILER_VERSION__ void rt_hw_cpu_icache_enable() { __asm(" MRC p15, #0, r1, c1, c0, #0 ; Read SCTLR configuration data"); @@ -90,5 +90,10 @@ void rt_hw_cpu_dcache_disable() __asm(" MCR p15, #0, r1, c1, c0, #0 ; disabled data cache"); } +#elif __GNUC__ +int __rt_ffs(int value) +{ + return __builtin_ffs(value); +} #endif /*@}*/ diff --git a/libcpu/arm/cortex-r4/stack.c b/libcpu/arm/cortex-r4/stack.c index 02dc84e6f1..769e3360ed 100644 --- a/libcpu/arm/cortex-r4/stack.c +++ b/libcpu/arm/cortex-r4/stack.c @@ -57,7 +57,7 @@ rt_uint8_t *rt_hw_stack_init(void *tentry, void *parameter, else *(--stk) = SVCMODE; /* arm mode */ -#ifdef __TI_VFP_SUPPORT__ +#if defined(__TI_VFP_SUPPORT__) || (defined (__VFP_FP__) && !defined(__SOFTFP__)) #ifndef RT_VFP_LAZY_STACKING { #define VFP_DATA_NR 32 |