diff options
27 files changed, 2962 insertions, 1 deletions
diff --git a/bsp/nuclei/.gitignore b/bsp/nuclei/.gitignore new file mode 100644 index 0000000000..975dcc6995 --- /dev/null +++ b/bsp/nuclei/.gitignore @@ -0,0 +1,26 @@ +*.i +*.o +*.d +*.elf +*.diss +*.map +*.bin +*.log +.vscode + +*.dump +*.verilog + +*.swp +*.swo + +prebuilt_tools/ +setup_config.sh +setup_config.bat + +tags +TAGS +TAG +CTAGS +Makefile.local +Makefile.global diff --git a/bsp/nuclei/gd32vf103_rvstar/.config b/bsp/nuclei/gd32vf103_rvstar/.config new file mode 100644 index 0000000000..c68135acc4 --- /dev/null +++ b/bsp/nuclei/gd32vf103_rvstar/.config @@ -0,0 +1,453 @@ +# +# Automatically generated file; DO NOT EDIT. +# RT-Thread Configuration +# + +# +# RT-Thread Kernel +# +CONFIG_RT_NAME_MAX=8 +# CONFIG_RT_USING_ARCH_DATA_TYPE is not set +# CONFIG_RT_USING_SMP is not set +CONFIG_RT_ALIGN_SIZE=4 +# CONFIG_RT_THREAD_PRIORITY_8 is not set +CONFIG_RT_THREAD_PRIORITY_32=y +# CONFIG_RT_THREAD_PRIORITY_256 is not set +CONFIG_RT_THREAD_PRIORITY_MAX=32 +CONFIG_RT_TICK_PER_SECOND=100 +CONFIG_RT_USING_OVERFLOW_CHECK=y +CONFIG_RT_USING_HOOK=y +CONFIG_RT_USING_IDLE_HOOK=y +CONFIG_RT_IDLE_HOOK_LIST_SIZE=4 +CONFIG_IDLE_THREAD_STACK_SIZE=396 +CONFIG_RT_USING_TIMER_SOFT=y +CONFIG_RT_TIMER_THREAD_PRIO=4 +CONFIG_RT_TIMER_THREAD_STACK_SIZE=512 +CONFIG_RT_DEBUG=y +CONFIG_RT_DEBUG_COLOR=y +CONFIG_RT_DEBUG_INIT_CONFIG=y +CONFIG_RT_DEBUG_INIT=1 +# CONFIG_RT_DEBUG_THREAD_CONFIG is not set +# CONFIG_RT_DEBUG_SCHEDULER_CONFIG is not set +# CONFIG_RT_DEBUG_IPC_CONFIG is not set +# CONFIG_RT_DEBUG_TIMER_CONFIG is not set +# CONFIG_RT_DEBUG_IRQ_CONFIG is not set +# CONFIG_RT_DEBUG_MEM_CONFIG is not set +# CONFIG_RT_DEBUG_SLAB_CONFIG is not set +# CONFIG_RT_DEBUG_MEMHEAP_CONFIG is not set +# CONFIG_RT_DEBUG_MODULE_CONFIG is not set + +# +# Inter-Thread communication +# +CONFIG_RT_USING_SEMAPHORE=y +CONFIG_RT_USING_MUTEX=y +CONFIG_RT_USING_EVENT=y +CONFIG_RT_USING_MAILBOX=y +CONFIG_RT_USING_MESSAGEQUEUE=y +# CONFIG_RT_USING_SIGNALS is not set + +# +# Memory Management +# +CONFIG_RT_USING_MEMPOOL=y +# CONFIG_RT_USING_MEMHEAP is not set +# CONFIG_RT_USING_NOHEAP is not set +CONFIG_RT_USING_SMALL_MEM=y +# CONFIG_RT_USING_SLAB is not set +# CONFIG_RT_USING_MEMTRACE is not set +CONFIG_RT_USING_HEAP=y + +# +# Kernel Device Object +# +CONFIG_RT_USING_DEVICE=y +# CONFIG_RT_USING_DEVICE_OPS is not set +# CONFIG_RT_USING_INTERRUPT_INFO is not set +CONFIG_RT_USING_CONSOLE=y +CONFIG_RT_CONSOLEBUF_SIZE=128 +CONFIG_RT_CONSOLE_DEVICE_NAME="uart4" +CONFIG_RT_VER_NUM=0x40003 +# CONFIG_RT_USING_CPU_FFS is not set +CONFIG_ARCH_RISCV=y +CONFIG_ARCH_RISCV32=y +# CONFIG_ARCH_CPU_STACK_GROWS_UPWARD is not set + +# +# RT-Thread Components +# +CONFIG_RT_USING_COMPONENTS_INIT=y +CONFIG_RT_USING_USER_MAIN=y +CONFIG_RT_MAIN_THREAD_STACK_SIZE=2048 +CONFIG_RT_MAIN_THREAD_PRIORITY=10 + +# +# C++ features +# +# CONFIG_RT_USING_CPLUSPLUS is not set + +# +# Command shell +# +CONFIG_RT_USING_FINSH=y +CONFIG_FINSH_THREAD_NAME="tshell" +CONFIG_FINSH_USING_HISTORY=y +CONFIG_FINSH_HISTORY_LINES=5 +CONFIG_FINSH_USING_SYMTAB=y +CONFIG_FINSH_USING_DESCRIPTION=y +# CONFIG_FINSH_ECHO_DISABLE_DEFAULT is not set +CONFIG_FINSH_THREAD_PRIORITY=20 +CONFIG_FINSH_THREAD_STACK_SIZE=4096 +CONFIG_FINSH_CMD_SIZE=80 +# CONFIG_FINSH_USING_AUTH is not set +CONFIG_FINSH_USING_MSH=y +CONFIG_FINSH_USING_MSH_DEFAULT=y +# CONFIG_FINSH_USING_MSH_ONLY is not set +CONFIG_FINSH_ARG_MAX=10 + +# +# Device virtual file system +# +CONFIG_RT_USING_DFS=y +CONFIG_DFS_USING_WORKDIR=y +CONFIG_DFS_FILESYSTEMS_MAX=2 +CONFIG_DFS_FILESYSTEM_TYPES_MAX=2 +CONFIG_DFS_FD_MAX=16 +# CONFIG_RT_USING_DFS_MNTTABLE is not set +# CONFIG_RT_USING_DFS_ELMFAT is not set +CONFIG_RT_USING_DFS_DEVFS=y +# CONFIG_RT_USING_DFS_ROMFS is not set +# CONFIG_RT_USING_DFS_RAMFS is not set +# CONFIG_RT_USING_DFS_UFFS is not set +# CONFIG_RT_USING_DFS_JFFS2 is not set + +# +# Device Drivers +# +CONFIG_RT_USING_DEVICE_IPC=y +CONFIG_RT_PIPE_BUFSZ=512 +# CONFIG_RT_USING_SYSTEM_WORKQUEUE is not set +CONFIG_RT_USING_SERIAL=y +CONFIG_RT_SERIAL_USING_DMA=y +CONFIG_RT_SERIAL_RB_BUFSZ=64 +# CONFIG_RT_USING_CAN is not set +# CONFIG_RT_USING_HWTIMER is not set +# CONFIG_RT_USING_CPUTIME is not set +# CONFIG_RT_USING_I2C is not set +CONFIG_RT_USING_PIN=y +# CONFIG_RT_USING_ADC is not set +# CONFIG_RT_USING_PWM is not set +# CONFIG_RT_USING_MTD_NOR is not set +# CONFIG_RT_USING_MTD_NAND is not set +# CONFIG_RT_USING_PM is not set +# CONFIG_RT_USING_RTC is not set +# CONFIG_RT_USING_SDIO is not set +# CONFIG_RT_USING_SPI is not set +# CONFIG_RT_USING_WDT is not set +# CONFIG_RT_USING_AUDIO is not set +# CONFIG_RT_USING_SENSOR is not set +# CONFIG_RT_USING_TOUCH is not set +# CONFIG_RT_USING_HWCRYPTO is not set +# CONFIG_RT_USING_PULSE_ENCODER is not set +# CONFIG_RT_USING_INPUT_CAPTURE is not set +# CONFIG_RT_USING_WIFI is not set + +# +# Using USB +# +# CONFIG_RT_USING_USB_HOST is not set +# CONFIG_RT_USING_USB_DEVICE is not set + +# +# POSIX layer and C standard library +# +CONFIG_RT_USING_LIBC=y +# CONFIG_RT_USING_PTHREADS is not set +CONFIG_RT_USING_POSIX=y +# CONFIG_RT_USING_POSIX_MMAP is not set +# CONFIG_RT_USING_POSIX_TERMIOS is not set +# CONFIG_RT_USING_POSIX_AIO is not set +# CONFIG_RT_USING_MODULE is not set + +# +# Network +# + +# +# Socket abstraction layer +# +# CONFIG_RT_USING_SAL is not set + +# +# Network interface device +# +# CONFIG_RT_USING_NETDEV is not set + +# +# light weight TCP/IP stack +# +# CONFIG_RT_USING_LWIP is not set + +# +# AT commands +# +# CONFIG_RT_USING_AT is not set + +# +# VBUS(Virtual Software BUS) +# +# CONFIG_RT_USING_VBUS is not set + +# +# Utilities +# +# CONFIG_RT_USING_RYM is not set +# CONFIG_RT_USING_ULOG is not set +# CONFIG_RT_USING_UTEST is not set + +# +# RT-Thread online packages +# + +# +# IoT - internet of things +# +# CONFIG_PKG_USING_PAHOMQTT is not set +# CONFIG_PKG_USING_WEBCLIENT is not set +# CONFIG_PKG_USING_WEBNET is not set +# CONFIG_PKG_USING_MONGOOSE is not set +# CONFIG_PKG_USING_MYMQTT is not set +# CONFIG_PKG_USING_KAWAII_MQTT is not set +# CONFIG_PKG_USING_WEBTERMINAL is not set +# CONFIG_PKG_USING_CJSON is not set +# CONFIG_PKG_USING_JSMN is not set +# CONFIG_PKG_USING_LIBMODBUS is not set +# CONFIG_PKG_USING_FREEMODBUS is not set +# CONFIG_PKG_USING_LJSON is not set +# CONFIG_PKG_USING_EZXML is not set +# CONFIG_PKG_USING_NANOPB is not set + +# +# Wi-Fi +# + +# +# Marvell WiFi +# +# CONFIG_PKG_USING_WLANMARVELL is not set + +# +# Wiced WiFi +# +# CONFIG_PKG_USING_WLAN_WICED is not set +# CONFIG_PKG_USING_RW007 is not set +# CONFIG_PKG_USING_COAP is not set +# CONFIG_PKG_USING_NOPOLL is not set +# CONFIG_PKG_USING_NETUTILS is not set +# CONFIG_PKG_USING_PPP_DEVICE is not set +# CONFIG_PKG_USING_AT_DEVICE is not set +# CONFIG_PKG_USING_ATSRV_SOCKET is not set +# CONFIG_PKG_USING_WIZNET is not set + +# +# IoT Cloud +# +# CONFIG_PKG_USING_ONENET is not set +# CONFIG_PKG_USING_GAGENT_CLOUD is not set +# CONFIG_PKG_USING_ALI_IOTKIT is not set +# CONFIG_PKG_USING_AZURE is not set +# CONFIG_PKG_USING_TENCENT_IOTHUB is not set +# CONFIG_PKG_USING_JIOT-C-SDK is not set +# CONFIG_PKG_USING_UCLOUD_IOT_SDK is not set +# CONFIG_PKG_USING_JOYLINK is not set +# CONFIG_PKG_USING_NIMBLE is not set +# CONFIG_PKG_USING_OTA_DOWNLOADER is not set +# CONFIG_PKG_USING_IPMSG is not set +# CONFIG_PKG_USING_LSSDP is not set +# CONFIG_PKG_USING_AIRKISS_OPEN is not set +# CONFIG_PKG_USING_LIBRWS is not set +# CONFIG_PKG_USING_TCPSERVER is not set +# CONFIG_PKG_USING_PROTOBUF_C is not set +# CONFIG_PKG_USING_ONNX_PARSER is not set +# CONFIG_PKG_USING_ONNX_BACKEND is not set +# CONFIG_PKG_USING_DLT645 is not set +# CONFIG_PKG_USING_QXWZ is not set +# CONFIG_PKG_USING_SMTP_CLIENT is not set +# CONFIG_PKG_USING_ABUP_FOTA is not set +# CONFIG_PKG_USING_LIBCURL2RTT is not set +# CONFIG_PKG_USING_CAPNP is not set +# CONFIG_PKG_USING_RT_CJSON_TOOLS is not set +# CONFIG_PKG_USING_AGILE_TELNET is not set + +# +# security packages +# +# CONFIG_PKG_USING_MBEDTLS is not set +# CONFIG_PKG_USING_libsodium is not set +# CONFIG_PKG_USING_TINYCRYPT is not set +# CONFIG_PKG_USING_TFM is not set + +# +# language packages +# +# CONFIG_PKG_USING_LUA is not set +# CONFIG_PKG_USING_JERRYSCRIPT is not set +# CONFIG_PKG_USING_MICROPYTHON is not set + +# +# multimedia packages +# +# CONFIG_PKG_USING_OPENMV is not set +# CONFIG_PKG_USING_MUPDF is not set +# CONFIG_PKG_USING_STEMWIN is not set +# CONFIG_PKG_USING_WAVPLAYER is not set +# CONFIG_PKG_USING_TJPGD is not set + +# +# tools packages +# +# CONFIG_PKG_USING_CMBACKTRACE is not set +# CONFIG_PKG_USING_EASYFLASH is not set +# CONFIG_PKG_USING_EASYLOGGER is not set +# CONFIG_PKG_USING_SYSTEMVIEW is not set +# CONFIG_PKG_USING_RDB is not set +# CONFIG_PKG_USING_QRCODE is not set +# CONFIG_PKG_USING_ULOG_EASYFLASH is not set +# CONFIG_PKG_USING_ADBD is not set +# CONFIG_PKG_USING_COREMARK is not set +# CONFIG_PKG_USING_DHRYSTONE is not set +# CONFIG_PKG_USING_NR_MICRO_SHELL is not set +# CONFIG_PKG_USING_CHINESE_FONT_LIBRARY is not set +# CONFIG_PKG_USING_LUNAR_CALENDAR is not set +# CONFIG_PKG_USING_BS8116A is not set + +# +# system packages +# +# CONFIG_PKG_USING_GUIENGINE is not set +# CONFIG_PKG_USING_CAIRO is not set +# CONFIG_PKG_USING_PIXMAN is not set +# CONFIG_PKG_USING_LWEXT4 is not set +# CONFIG_PKG_USING_PARTITION is not set +# CONFIG_PKG_USING_FAL is not set +# CONFIG_PKG_USING_SQLITE is not set +# CONFIG_PKG_USING_RTI is not set +# CONFIG_PKG_USING_LITTLEVGL2RTT is not set +# CONFIG_PKG_USING_CMSIS is not set +# CONFIG_PKG_USING_DFS_YAFFS is not set +# CONFIG_PKG_USING_LITTLEFS is not set +# CONFIG_PKG_USING_THREAD_POOL is not set +# CONFIG_PKG_USING_ROBOTS is not set +# CONFIG_PKG_USING_EV is not set +# CONFIG_PKG_USING_SYSWATCH is not set +# CONFIG_PKG_USING_SYS_LOAD_MONITOR is not set +# CONFIG_PKG_USING_PLCCORE is not set + +# +# peripheral libraries and drivers +# +# CONFIG_PKG_USING_SENSORS_DRIVERS is not set +# CONFIG_PKG_USING_REALTEK_AMEBA is not set +# CONFIG_PKG_USING_SHT2X is not set +# CONFIG_PKG_USING_SHT3X is not set +# CONFIG_PKG_USING_STM32_SDIO is not set +# CONFIG_PKG_USING_ICM20608 is not set +# CONFIG_PKG_USING_U8G2 is not set +# CONFIG_PKG_USING_BUTTON is not set +# CONFIG_PKG_USING_PCF8574 is not set +# CONFIG_PKG_USING_SX12XX is not set +# CONFIG_PKG_USING_SIGNAL_LED is not set +# CONFIG_PKG_USING_LEDBLINK is not set +# CONFIG_PKG_USING_LITTLED is not set +# CONFIG_PKG_USING_LKDGUI is not set +# CONFIG_PKG_USING_NRF5X_SDK is not set +# CONFIG_PKG_USING_WM_LIBRARIES is not set +# CONFIG_PKG_USING_KENDRYTE_SDK is not set +# CONFIG_PKG_USING_INFRARED is not set +# CONFIG_PKG_USING_ROSSERIAL is not set +# CONFIG_PKG_USING_AGILE_BUTTON is not set +# CONFIG_PKG_USING_AGILE_LED is not set +# CONFIG_PKG_USING_AT24CXX is not set +# CONFIG_PKG_USING_MOTIONDRIVER2RTT is not set +# CONFIG_PKG_USING_AD7746 is not set +# CONFIG_PKG_USING_PCA9685 is not set +# CONFIG_PKG_USING_I2C_TOOLS is not set +# CONFIG_PKG_USING_NRF24L01 is not set +# CONFIG_PKG_USING_TOUCH_DRIVERS is not set +# CONFIG_PKG_USING_MAX17048 is not set +# CONFIG_PKG_USING_RPLIDAR is not set +# CONFIG_PKG_USING_AS608 is not set +# CONFIG_PKG_USING_RC522 is not set +# CONFIG_PKG_USING_EMBARC_BSP is not set +# CONFIG_PKG_USING_EXTERN_RTC_DRIVERS is not set +# CONFIG_PKG_USING_MULTI_RTIMER is not set +# CONFIG_PKG_USING_MAX7219 is not set +# CONFIG_PKG_USING_BEEP is not set +# CONFIG_PKG_USING_EASYBLINK is not set +# CONFIG_PKG_USING_PMS_SERIES is not set +CONFIG_PKG_USING_NUCLEI_SDK=y +CONFIG_PKG_NUCLEI_SDK_PATH="/packages/peripherals/nuclei_sdk" +# CONFIG_PKG_USING_NUCLEI_SDK_V023 is not set +CONFIG_PKG_USING_NUCLEI_SDK_LATEST_VERSION=y +CONFIG_PKG_NUCLEI_SDK_VER="latest" + +# +# miscellaneous packages +# +# CONFIG_PKG_USING_LIBCSV is not set +# CONFIG_PKG_USING_OPTPARSE is not set +# CONFIG_PKG_USING_FASTLZ is not set +# CONFIG_PKG_USING_MINILZO is not set +# CONFIG_PKG_USING_QUICKLZ is not set +# CONFIG_PKG_USING_MULTIBUTTON is not set +# CONFIG_PKG_USING_FLEXIBLE_BUTTON is not set +# CONFIG_PKG_USING_CANFESTIVAL is not set +# CONFIG_PKG_USING_ZLIB is not set +# CONFIG_PKG_USING_DSTR is not set +# CONFIG_PKG_USING_TINYFRAME is not set +# CONFIG_PKG_USING_KENDRYTE_DEMO is not set +# CONFIG_PKG_USING_DIGITALCTRL is not set +# CONFIG_PKG_USING_UPACKER is not set +# CONFIG_PKG_USING_UPARAM is not set + +# +# samples: kernel and components samples +# +# CONFIG_PKG_USING_KERNEL_SAMPLES is not set +# CONFIG_PKG_USING_FILESYSTEM_SAMPLES is not set +# CONFIG_PKG_USING_NETWORK_SAMPLES is not set +# CONFIG_PKG_USING_PERIPHERAL_SAMPLES is not set +# CONFIG_PKG_USING_HELLO is not set +# CONFIG_PKG_USING_VI is not set +# CONFIG_PKG_USING_NNOM is not set +# CONFIG_PKG_USING_LIBANN is not set +# CONFIG_PKG_USING_ELAPACK is not set +# CONFIG_PKG_USING_ARMv7M_DWT is not set +# CONFIG_PKG_USING_VT100 is not set +# CONFIG_PKG_USING_ULAPACK is not set +# CONFIG_PKG_USING_UKAL is not set + +# +# Hardware Drivers Config +# +CONFIG_SOC_GD32VF103V=y + +# +# Onboard Peripheral Drivers +# +CONFIG_BSP_USING_UART_CONSOLE=y + +# +# On-chip Peripheral Drivers +# +CONFIG_BSP_USING_UART=y +# CONFIG_BSP_USING_UART0 is not set +# CONFIG_BSP_USING_UART1 is not set +# CONFIG_BSP_USING_UART2 is not set +# CONFIG_BSP_USING_UART3 is not set +CONFIG_BSP_USING_UART4=y + +# +# Board extended module Drivers +# +CONFIG_SOC_GD32VF103=y diff --git a/bsp/nuclei/gd32vf103_rvstar/Kconfig b/bsp/nuclei/gd32vf103_rvstar/Kconfig new file mode 100644 index 0000000000..fb1ab0ffd5 --- /dev/null +++ b/bsp/nuclei/gd32vf103_rvstar/Kconfig @@ -0,0 +1,28 @@ +mainmenu "RT-Thread Configuration" + +config BSP_DIR + string + option env="BSP_ROOT" + default "." + +config RTT_DIR + string + option env="RTT_ROOT" + default "../../.." + +config PKGS_DIR + string + option env="PKGS_ROOT" + default "packages" + +source "$RTT_DIR/Kconfig" +source "$PKGS_DIR/Kconfig" +source "board/Kconfig" + +config SOC_GD32VF103 + bool + select ARCH_RISCV32 + select PKG_USING_NUCLEI_SDK + select RT_USING_COMPONENTS_INIT + select RT_USING_USER_MAIN + default y diff --git a/bsp/nuclei/gd32vf103_rvstar/README.md b/bsp/nuclei/gd32vf103_rvstar/README.md new file mode 100644 index 0000000000..f9575aa2ee --- /dev/null +++ b/bsp/nuclei/gd32vf103_rvstar/README.md @@ -0,0 +1,209 @@ +# 芯来科技RVSTAR开发板 # + +## 简介 + +**RVSTAR开发板** 是由芯来科技公司推出的基于采用芯来科技RISC-V架构处理器芯片的GD32VF103的开发板。 + +更多关于 **RVSTAR开发板** 开发板的详细资料请参见 [RVSTAR开发板快速入门](https://www.rvmcu.com/quickstart-quickstart-index-u-RV_STAR.html) + +### 板载资源 + +| 硬件 | 描述 | +| --- | --- | +| 内核 | Nuclei N205 | +| 架构 | 32-bit RV32IMAC | +| 主频 | 108 MHz | + +## 工具安装 + +### 安装工具链 + +请根据[安装Nuclei RISC-V GCC Toolchain和OpenOCD](https://doc.nucleisys.com/nuclei_sdk/quickstart.html#setup-tools-and-environment) 来安装依赖的工具。 + +### 添加环境变量 + +将Nuclei RISC-V GCC Toolchain和OpenOCD的环境变量进行设置。 + +#### Windows + +假设工具安装在 **D:\Software\Nuclei**目录下, 则可以修改系统环境变量**PATH**, +将**D:\Software\Nuclei\gcc\bin;D:\Software\Nuclei\openocd\bin;**增加到**PATH**中。 + +或者在ENV工具命令行中运行 + +~~~cmd +set PATH=D:\Software\Nuclei\gcc\bin;D:\Software\Nuclei\openocd\bin;%PATH% +~~~ + +#### Linux + +假设工具安装在 **~/Software/Nuclei**目录下, 通过在Linux的``.bashrc``增加如下一行代码 +来添加环境变量。 + +~~~bash +export PATH=~/Software/Nuclei/gcc/bin:~/Software/Nuclei/openocd/bin:$PATH +~~~ + +或者在ENV工具命令行中运行 + +~~~bash +export PATH=~/Software/Nuclei/gcc/bin:~/Software/Nuclei/openocd/bin:$PATH +~~~ + +**注意**: 对应的RISC-V GCC和OPENOCD的路径请替换成自己安装的路径。 + +## 烧写及执行 + +### [驱动设置](https://doc.nucleisys.com/nuclei_board_labs/hw/hw.html#on-board-debugger-driver) + +### 编译程序 + +下载好[RT-Thread](https://github.com/RT-Thread/rt-thread)的代码和[ENV工具](https://www.rt-thread.org/document/site/tutorial/env-video/)以后。 + +按照ENV工具的教程, 在**rt-thread\bsp\nuclei\gd32vf103_rvstar**目录打开ENV工具命令行。 + +**注意**: 请确保Nuclei GCC和Nuclei OpenOCD的路径设置正确无误。 + +1. 运行 ``pkgs --update``来下载最新的依赖的**Nuclei SDK**开发包 +2. **可选**: 运行 ``menuconfig``来进行内核配置 +3. 运行 ``scons -c``清理之前的编译结果 +4. 运行 ``scons``来进行代码的编译 + +### 下载程序 + +在保证程序能够正常编译后, 在相同ENV终端执行``scons --run upload``进行代码的下载。 + +正常下载的输出如下: + +~~~ +scons: Reading SConscript files ... +Supported downloaded modes for board gd32vf103v_rvstar are flashxip, chosen downloaded mode is flashxip +Upload application rtthread.elf using openocd and gdb +riscv-nuclei-elf-gdb rtthread.elf -ex "set remotetimeout 240" -ex "target remote | openocd --pipe -f D:/workspace/Sourcecode/rt-thread/bsp/nuclei/gd32vf103_rvstar/packages/nuclei_sdk-latest/SoC/gd32vf103/Board/gd32vf103v_rvstar/openocd_gd32vf103.cfg" --batch -ex "monitor halt" -ex "monitor flash protect 0 0 last off" -ex "load" -ex "monitor resume" -ex "monitor shutdown" -ex "quit" +D:\Software\Nuclei\gcc\bin\riscv-nuclei-elf-gdb.exe: warning: Couldn't determine a path for the index cache directory. + +Nuclei OpenOCD, 64-bit Open On-Chip Debugger 0.10.0+dev-00014-g0eae03214 (2019-12-12-07:43) +Licensed under GNU GPL v2 +For bug reports, read + http://openocd.org/doc/doxygen/bugs.html +rt_thread_idle_entry (parameter=0x0) at D:\workspace\Sourcecode\rt-thread\src\idle.c:251 +251 if (idle_hook_list[i] != RT_NULL) +cleared protection for sectors 0 through 127 on flash bank 0 + +Loading section .init, size 0x264 lma 0x8000000 +Loading section .text, size 0x140de lma 0x8000280 +Loading section .rodata, size 0x37c0 lma 0x8014360 +Loading section .data, size 0x404 lma 0x8017b20 +Start address 0x800015c, load size 98054 +Transfer rate: 8 KB/sec, 10894 bytes/write. +shutdown command invoked +A debugging session is active. + + Inferior 1 [Remote target] will be detached. + +Quit anyway? (y or n) [answered Y; input not from terminal] +Remote communication error. Target disconnected.: Success. +~~~ + +下载程序之后, 连接串口(115200-N-8-1), 可以看到 RT-Thread 的输出信息： + +``` +initialize rti_board_start:0 done + + \ | / +- RT - Thread Operating System + / | \ 4.0.3 build Apr 9 2020 + 2006 - 2020 Copyright by rt-thread team +do components initialization. +initialize rti_board_end:0 done +initialize dfs_init:0 done +initialize libc_system_init:0 done +initialize finsh_system_init:0 done +msh /> +``` + +在串口终端(我这里使用的是TeraTerm)输入``ps``即可查看当前线程工作情况: + +~~~ +msh />ps +thread pri status sp stack size max used left tick error +-------- --- ------- ---------- ---------- ------ ---------- --- +thread01 19 suspend 0x00000158 0x0000018c 87% 0x00000005 000 +thread00 19 suspend 0x00000158 0x0000018c 87% 0x00000005 000 +tshell 20 running 0x00000258 0x00001000 18% 0x00000004 000 +tidle0 31 ready 0x000000a8 0x0000018c 59% 0x0000000e 000 +timer 4 suspend 0x000000f8 0x00000200 49% 0x00000009 000 +main 10 suspend 0x00000168 0x00000800 36% 0x00000006 000 +msh /> +~~~ + +### 调试程序 + +在保证程序编译成功后, 在相同ENV终端执行``scons --run debug``进行代码在命令行下进行GDB调试。 + +正常的调试输出如下： + +~~~ +scons: Reading SConscript files ... +Supported downloaded modes for board gd32vf103v_rvstar are flashxip, chosen downloaded mode is flashxip +Debug application rtthread.elf using openocd and gdb +riscv-nuclei-elf-gdb rtthread.elf -ex "set remotetimeout 240" -ex "target remote | openocd --pipe -f D:/workspace/Sourcecode/rt-thread/bsp/nuclei/gd32vf103_rvstar/packages/nuclei_sdk-latest/SoC/gd32vf103/Board/gd32vf103v_rvstar/openocd_gd32vf103.cfg" +D:\Software\Nuclei\gcc\bin\riscv-nuclei-elf-gdb.exe: warning: Couldn't determine a path for the index cache directory. +GNU gdb (GDB) 8.3.0.20190516-git +Copyright (C) 2019 Free Software Foundation, Inc. +License GPLv3+: GNU GPL version 3 or later <http://gnu.org/licenses/gpl.html> +This is free software: you are free to change and redistribute it. +There is NO WARRANTY, to the extent permitted by law. +Type "show copying" and "show warranty" for details. +This GDB was configured as "--host=i686-w64-mingw32 --target=riscv-nuclei-elf". +Type "show configuration" for configuration details. +For bug reporting instructions, please see: +<http://www.gnu.org/software/gdb/bugs/>. +Find the GDB manual and other documentation resources online at: + <http://www.gnu.org/software/gdb/documentation/>. + +For help, type "help". +Type "apropos word" to search for commands related to "word"... +Reading symbols from rtthread.elf... +Remote debugging using | openocd --pipe -f D:/workspace/Sourcecode/rt-thread/bsp/nuclei/gd32vf103_rvstar/packages/nuclei_sdk-latest/SoC/gd32vf103/Board/gd32vf103v_rvstar/openocd_gd32vf103.cfg Nuclei OpenOCD, 64-bit Open On-Chip Debugger 0.10.0+dev-00014-g0eae03214 (2019-12-12-07:43) +Licensed under GNU GPL v2 +For bug reports, read + http://openocd.org/doc/doxygen/bugs.html +rt_thread_idle_entry (parameter=0x0) at D:\workspace\Sourcecode\rt-thread\src\idle.c:249 +249 for (i = 0; i < RT_IDLE_HOOK_LIST_SIZE; i++) +(gdb) +(gdb) b main.c:35 +Breakpoint 1 at 0x8000290: file applications\main.c, line 35. +(gdb) c +Continuing. +Note: automatically using hardware breakpoints for read-only addresses. + +Breakpoint 1, thread_entry (parameter=0x0) at applications\main.c:35 +35 rt_thread_mdelay(500); +(gdb) +~~~ + +调试例子参见如下文档: + +* https://doc.nucleisys.com/nuclei_sdk/quickstart.html#debug-application + +为了更方便的进行调试, 也可以下载**Nuclei Studio**集成开发环境, 创建一个Debug Configuration, 选择编译好的 +ELF文件, 然后配置OPENOCD和GDB即可, OPENOCD配置文件路径为**bsp\nuclei\gd32vf103_rvstar\packages\nuclei_sdk-latest\SoC\gd32vf103\Board\gd32vf103v_rvstar\openocd_gd32vf103.cfg** + + +## 驱动支持情况 + +| 驱动 | 支持情况 | 备注 | +| ------ | ---- | :------: | +| UART | 支持 | RV-STAR板载串口是UART4 | + +**注:** + +- 适配RT-Thread的驱动框架的代码在 [../libraries/gd32vf103/HAL_Drivers](../libraries/gd32vf103/HAL_Drivers)目录下。 +- 如果有开发者想适配更多的驱动, 请在对应目录下增加驱动适配支持。 + +## 联系人信息 + +维护人： +- [fanghuaqi](https://github.com/fanghuaqi) + diff --git a/bsp/nuclei/gd32vf103_rvstar/SConscript b/bsp/nuclei/gd32vf103_rvstar/SConscript new file mode 100644 index 0000000000..014c428d0a --- /dev/null +++ b/bsp/nuclei/gd32vf103_rvstar/SConscript @@ -0,0 +1,17 @@ +# for module compiling +import os +Import('RTT_ROOT') +from building import * + +cwd = GetCurrentDir() +objs = [] +list = os.listdir(cwd) + +ASFLAGS = ' -I' + cwd + +for d in list: + path = os.path.join(cwd, d) + if os.path.isfile(os.path.join(path, 'SConscript')): + objs = objs + SConscript(os.path.join(d, 'SConscript')) + +Return('objs') diff --git a/bsp/nuclei/gd32vf103_rvstar/SConstruct b/bsp/nuclei/gd32vf103_rvstar/SConstruct new file mode 100644 index 0000000000..7adcd69070 --- /dev/null +++ b/bsp/nuclei/gd32vf103_rvstar/SConstruct @@ -0,0 +1,85 @@ +import os +import sys +import rtconfig + +if os.getenv('RTT_ROOT'): + RTT_ROOT = os.getenv('RTT_ROOT') +else: + RTT_ROOT = os.path.normpath(os.getcwd() + '/../../..') + +sys.path = sys.path + [os.path.join(RTT_ROOT, 'tools')] +from building import * + +TARGET = 'rtthread.' + rtconfig.TARGET_EXT + +AddOption('--run', + dest = 'run', + type='string', + nargs=1, + action = 'store', + default = "", + help = 'Upload or debug application using openocd') + +DefaultEnvironment(tools=[]) +env = Environment(tools = ['mingw'], + AS = rtconfig.AS, ASFLAGS = rtconfig.AFLAGS, + CC = rtconfig.CC, CCFLAGS = rtconfig.CFLAGS, + AR = rtconfig.AR, ARFLAGS = '-rc', + LINK = rtconfig.LINK, LINKFLAGS = rtconfig.LFLAGS) +env.PrependENVPath('PATH', rtconfig.EXEC_PATH) +env['ASCOM'] = env['ASPPCOM'] + +Export('RTT_ROOT') +Export('rtconfig') + +SDK_ROOT = os.path.abspath('./') + +if os.path.exists(SDK_ROOT + '/libraries'): + libraries_path_prefix = SDK_ROOT + '/libraries' +else: + libraries_path_prefix = os.path.dirname(SDK_ROOT) + '/libraries' + +SDK_LIB = libraries_path_prefix +Export('SDK_LIB') + +GDB = rtconfig.GDB + +# prepare building environment +objs = PrepareBuilding(env, RTT_ROOT) + +bsp_library_type = rtconfig.NUCLEI_SDK_SOC +rtconfig.BSP_LIBRARY_TYPE = bsp_library_type + +openocd_cfg = rtconfig.NUCLEI_SDK_OPENOCD_CFG.replace('\\', '/') + +# include hal drivers +hal_sconscript = os.path.join(libraries_path_prefix, bsp_library_type, 'HAL_Drivers', 'SConscript') + +if os.path.isfile(hal_sconscript): + objs.extend(SConscript(hal_sconscript)) + +# make a building +DoBuilding(TARGET, objs) + +# Run upload or debug if --run=upload or --upload=debug +run_target = GetOption('run') +SUPPORT_RUN_TARGETS = ["upload", "debug"] +if run_target in SUPPORT_RUN_TARGETS: + if os.path.isfile(TARGET): + if run_target == "upload": + upload_cmd = '{} {} -ex "set remotetimeout 240" \ + -ex "target remote | openocd --pipe -f {}" \ + --batch -ex "monitor halt" -ex "monitor flash protect 0 0 last off" -ex "load" \ + -ex "monitor resume" -ex "monitor shutdown" -ex "quit"'.format(GDB, TARGET, openocd_cfg) + print("Upload application {} using openocd and gdb".format(TARGET)) + print(upload_cmd) + os.system(upload_cmd) + elif run_target == "debug": + debug_cmd = '{} {} -ex "set remotetimeout 240" \ + -ex "target remote | openocd --pipe -f {}"'.format(GDB, TARGET, openocd_cfg) + print("Debug application {} using openocd and gdb".format(TARGET)) + print(debug_cmd) + os.system(debug_cmd) + else: + print(TARGET + ' not exist, please run scons first!!') + exit(0) diff --git a/bsp/nuclei/gd32vf103_rvstar/applications/SConscript b/bsp/nuclei/gd32vf103_rvstar/applications/SConscript new file mode 100644 index 0000000000..ef1c39fd83 --- /dev/null +++ b/bsp/nuclei/gd32vf103_rvstar/applications/SConscript @@ -0,0 +1,11 @@ +Import('RTT_ROOT') +Import('rtconfig') +from building import * + +cwd = GetCurrentDir() +src = Glob('*.c') +CPPPATH = [cwd, ] + +group = DefineGroup('Applications', src, depend = [''], CPPPATH = CPPPATH) + +Return('group') diff --git a/bsp/nuclei/gd32vf103_rvstar/applications/main.c b/bsp/nuclei/gd32vf103_rvstar/applications/main.c new file mode 100644 index 0000000000..7da5f0da45 --- /dev/null +++ b/bsp/nuclei/gd32vf103_rvstar/applications/main.c @@ -0,0 +1,19 @@ +/* + * Copyright (c) 2006-2020, RT-Thread Development Team + * + * SPDX-License-Identifier: Apache-2.0 + * + * Change Logs: + * Date Author Notes + * 2020-04-15 hqfang first version + */ + +#include <rtthread.h> +#include <rtdevice.h> + +int main(int argc, char *argv[]) +{ + return RT_EOK; +} + +/******************** end of file *******************/
\ No newline at end of file diff --git a/bsp/nuclei/gd32vf103_rvstar/board/Kconfig b/bsp/nuclei/gd32vf103_rvstar/board/Kconfig new file mode 100644 index 0000000000..5165ac7629 --- /dev/null +++ b/bsp/nuclei/gd32vf103_rvstar/board/Kconfig @@ -0,0 +1,47 @@ +menu "Hardware Drivers Config" + +config SOC_GD32VF103V + bool + select SOC_SERIES_GD32VF103V + default y + +menu "Onboard Peripheral Drivers" + + config BSP_USING_UART_CONSOLE + bool "Enable UART CONSOLE" + select BSP_USING_UART + select BSP_USING_UART4 + default y +endmenu + +menu "On-chip Peripheral Drivers" + + menuconfig BSP_USING_UART + bool "Enable UART" + default y + select RT_USING_SERIAL + if BSP_USING_UART + config BSP_USING_UART0 + bool "Enable UART0" + default n + config BSP_USING_UART1 + bool "Enable UART1" + default n + config BSP_USING_UART2 + bool "Enable UART2" + default n + config BSP_USING_UART3 + bool "Enable UART3" + default n + config BSP_USING_UART4 + bool "Enable UART4" + default n + endif + +endmenu + +menu "Board extended module Drivers" + +endmenu + +endmenu diff --git a/bsp/nuclei/gd32vf103_rvstar/board/SConscript b/bsp/nuclei/gd32vf103_rvstar/board/SConscript new file mode 100644 index 0000000000..148c99f42c --- /dev/null +++ b/bsp/nuclei/gd32vf103_rvstar/board/SConscript @@ -0,0 +1,11 @@ +# RT-Thread building script for component + +from building import * + +cwd = GetCurrentDir() +src = Glob('*.c') +CPPPATH = [cwd] + +group = DefineGroup('Drivers', src, depend = [''], CPPPATH = CPPPATH) + +Return('group') diff --git a/bsp/nuclei/gd32vf103_rvstar/board/board.c b/bsp/nuclei/gd32vf103_rvstar/board/board.c new file mode 100644 index 0000000000..7dad875006 --- /dev/null +++ b/bsp/nuclei/gd32vf103_rvstar/board/board.c @@ -0,0 +1,67 @@ +/* + * Copyright (c) 2006-2020, RT-Thread Development Team + * + * SPDX-License-Identifier: Apache-2.0 + * + * Change Logs: + * Date Author Notes + * 2020-04-02 hqfang first version + * + */ + +#include <rtthread.h> +#include <rtdevice.h> +#include "board.h" +#include "cpuport.h" + +#ifdef RT_USING_SERIAL + #include <drv_usart.h> +#endif + +/** _end symbol defined in linker script of Nuclei SDK */ +extern void *_end; + +/** _heap_end symbol defined in linker script of Nuclei SDK */ +extern void *_heap_end; +#define HEAP_BEGIN &_end +#define HEAP_END &_heap_end + +/* + * - Implemented and defined in Nuclei SDK system_<Device>.c file + * - Required macro NUCLEI_BANNER set to 0 + */ +extern void _init(void); + +/** + * @brief Setup hardware board for rt-thread + * + */ +void rt_hw_board_init(void) +{ + /* OS Tick Configuration */ + rt_hw_ticksetup(); + +#ifdef RT_USING_HEAP + rt_system_heap_init((void *) HEAP_BEGIN, (void *) HEAP_END); +#endif + + _init(); // __libc_init_array is not used in RT-Thread + + /* USART driver initialization is open by default */ +#ifdef RT_USING_SERIAL + rt_hw_usart_init(); +#endif + + /* Set the shell console output device */ +#ifdef RT_USING_CONSOLE + rt_console_set_device(RT_CONSOLE_DEVICE_NAME); +#endif + + /* Board underlying hardware initialization */ +#ifdef RT_USING_COMPONENTS_INIT + rt_components_board_init(); +#endif +} + +/******************** end of file *******************/ + diff --git a/bsp/nuclei/gd32vf103_rvstar/board/board.h b/bsp/nuclei/gd32vf103_rvstar/board/board.h new file mode 100644 index 0000000000..4e571e3ee2 --- /dev/null +++ b/bsp/nuclei/gd32vf103_rvstar/board/board.h @@ -0,0 +1,21 @@ +/* + * Copyright (c) 2006-2020, RT-Thread Development Team + * + * SPDX-License-Identifier: Apache-2.0 + * + * Change Logs: + * Date Author Notes + * 2020-04-02 hqfang first version + * + */ + +#ifndef __BOARD__ +#define __BOARD__ + +#include "nuclei_sdk_hal.h" + +void rt_hw_board_init(void); + +#endif /* __BOARD__ */ + +/******************** end of file *******************/ diff --git a/bsp/nuclei/gd32vf103_rvstar/rtconfig.h b/bsp/nuclei/gd32vf103_rvstar/rtconfig.h new file mode 100644 index 0000000000..2498e39e9d --- /dev/null +++ b/bsp/nuclei/gd32vf103_rvstar/rtconfig.h @@ -0,0 +1,181 @@ +#ifndef RT_CONFIG_H__ +#define RT_CONFIG_H__ + +/* Automatically generated file; DO NOT EDIT. */ +/* RT-Thread Configuration */ + +/* RT-Thread Kernel */ + +#define RT_NAME_MAX 8 +#define RT_ALIGN_SIZE 4 +#define RT_THREAD_PRIORITY_32 +#define RT_THREAD_PRIORITY_MAX 32 +#define RT_TICK_PER_SECOND 100 +#define RT_USING_OVERFLOW_CHECK +#define RT_USING_HOOK +#define RT_USING_IDLE_HOOK +#define RT_IDLE_HOOK_LIST_SIZE 4 +#define IDLE_THREAD_STACK_SIZE 396 +#define RT_USING_TIMER_SOFT +#define RT_TIMER_THREAD_PRIO 4 +#define RT_TIMER_THREAD_STACK_SIZE 512 +#define RT_DEBUG +#define RT_DEBUG_COLOR +#define RT_DEBUG_INIT_CONFIG +#define RT_DEBUG_INIT 1 + +/* Inter-Thread communication */ + +#define RT_USING_SEMAPHORE +#define RT_USING_MUTEX +#define RT_USING_EVENT +#define RT_USING_MAILBOX +#define RT_USING_MESSAGEQUEUE + +/* Memory Management */ + +#define RT_USING_MEMPOOL +#define RT_USING_SMALL_MEM +#define RT_USING_HEAP + +/* Kernel Device Object */ + +#define RT_USING_DEVICE +#define RT_USING_CONSOLE +#define RT_CONSOLEBUF_SIZE 128 +#define RT_CONSOLE_DEVICE_NAME "uart4" +#define RT_VER_NUM 0x40003 +#define ARCH_RISCV +#define ARCH_RISCV32 + +/* RT-Thread Components */ + +#define RT_USING_COMPONENTS_INIT +#define RT_USING_USER_MAIN +#define RT_MAIN_THREAD_STACK_SIZE 2048 +#define RT_MAIN_THREAD_PRIORITY 10 + +/* C++ features */ + + +/* Command shell */ + +#define RT_USING_FINSH +#define FINSH_THREAD_NAME "tshell" +#define FINSH_USING_HISTORY +#define FINSH_HISTORY_LINES 5 +#define FINSH_USING_SYMTAB +#define FINSH_USING_DESCRIPTION +#define FINSH_THREAD_PRIORITY 20 +#define FINSH_THREAD_STACK_SIZE 4096 +#define FINSH_CMD_SIZE 80 +#define FINSH_USING_MSH +#define FINSH_USING_MSH_DEFAULT +#define FINSH_ARG_MAX 10 + +/* Device virtual file system */ + +#define RT_USING_DFS +#define DFS_USING_WORKDIR +#define DFS_FILESYSTEMS_MAX 2 +#define DFS_FILESYSTEM_TYPES_MAX 2 +#define DFS_FD_MAX 16 +#define RT_USING_DFS_DEVFS + +/* Device Drivers */ + +#define RT_USING_DEVICE_IPC +#define RT_PIPE_BUFSZ 512 +#define RT_USING_SERIAL +#define RT_SERIAL_USING_DMA +#define RT_SERIAL_RB_BUFSZ 64 +#define RT_USING_PIN + +/* Using USB */ + + +/* POSIX layer and C standard library */ + +#define RT_USING_LIBC +#define RT_USING_POSIX + +/* Network */ + +/* Socket abstraction layer */ + + +/* Network interface device */ + + +/* light weight TCP/IP stack */ + + +/* AT commands */ + + +/* VBUS(Virtual Software BUS) */ + + +/* Utilities */ + + +/* RT-Thread online packages */ + +/* IoT - internet of things */ + + +/* Wi-Fi */ + +/* Marvell WiFi */ + + +/* Wiced WiFi */ + + +/* IoT Cloud */ + + +/* security packages */ + + +/* language packages */ + + +/* multimedia packages */ + + +/* tools packages */ + + +/* system packages */ + + +/* peripheral libraries and drivers */ + +#define PKG_USING_NUCLEI_SDK +#define PKG_USING_NUCLEI_SDK_LATEST_VERSION + +/* miscellaneous packages */ + + +/* samples: kernel and components samples */ + + +/* Hardware Drivers Config */ + +#define SOC_GD32VF103V + +/* Onboard Peripheral Drivers */ + +#define BSP_USING_UART_CONSOLE + +/* On-chip Peripheral Drivers */ + +#define BSP_USING_UART +#define BSP_USING_UART4 + +/* Board extended module Drivers */ + +#define SOC_GD32VF103 + +#endif diff --git a/bsp/nuclei/gd32vf103_rvstar/rtconfig.py b/bsp/nuclei/gd32vf103_rvstar/rtconfig.py new file mode 100644 index 0000000000..8136b392f8 --- /dev/null +++ b/bsp/nuclei/gd32vf103_rvstar/rtconfig.py @@ -0,0 +1,58 @@ +import os + +# toolchains options +ARCH='risc-v' +CPU='nuclei' +CROSS_TOOL='gcc' + +if os.getenv('RTT_CC'): + CROSS_TOOL = os.getenv('RTT_CC') + +if CROSS_TOOL == 'gcc': + PLATFORM = 'gcc' + EXEC_PATH = 'D:/Software/Nuclei/gcc/bin' +else: + print("CROSS_TOOL = {} not yet supported" % CROSS_TOOL) + +# if os.getenv('RTT_EXEC_PATH'): +# EXEC_PATH = os.getenv('RTT_EXEC_PATH') + +BUILD = 'debug' +# Fixed configurations below +NUCLEI_SDK_SOC = "gd32vf103" +NUCLEI_SDK_BOARD = "gd32vf103v_rvstar" +NUCLEI_SDK_DOWNLOAD = "flashxip" +NUCLEI_SDK_CORE = "n205" + +if PLATFORM == 'gcc': + # toolchains + PREFIX = 'riscv-nuclei-elf-' + CC = PREFIX + 'gcc' + CXX = PREFIX + 'g++' + AS = PREFIX + 'gcc' + AR = PREFIX + 'ar' + LINK = PREFIX + 'gcc' + GDB = PREFIX + 'gdb' + TARGET_EXT = 'elf' + SIZE = PREFIX + 'size' + OBJDUMP = PREFIX + 'objdump' + OBJCPY = PREFIX + 'objcopy' + + CFLAGS = ' -ffunction-sections -fdata-sections -fno-common ' + AFLAGS = CFLAGS + LFLAGS = ' --specs=nano.specs --specs=nosys.specs -nostartfiles -Wl,--gc-sections ' + LFLAGS += ' -Wl,-cref,-Map=rtthread.map' + LFLAGS += ' -u _isatty -u _write -u _sbrk -u _read -u _close -u _fstat -u _lseek ' + CPATH = '' + LPATH = '' + + if BUILD == 'debug': + CFLAGS += ' -O0 -ggdb' + AFLAGS += ' -ggdb' + else: + CFLAGS += ' -O2 -Os' + + CXXFLAGS = CFLAGS + +DUMP_ACTION = OBJDUMP + ' -D -S $TARGET > rtt.asm\n' +POST_ACTION = OBJCPY + ' -O binary $TARGET rtthread.bin\n' + SIZE + ' $TARGET \n' diff --git a/bsp/nuclei/libraries/gd32vf103/HAL_Drivers/SConscript b/bsp/nuclei/libraries/gd32vf103/HAL_Drivers/SConscript new file mode 100644 index 0000000000..4761127102 --- /dev/null +++ b/bsp/nuclei/libraries/gd32vf103/HAL_Drivers/SConscript @@ -0,0 +1,21 @@ +Import('RTT_ROOT') +Import('rtconfig') +from building import * + +cwd = GetCurrentDir() + +# add the general drivers. +src = Split(""" +""") + +if GetDepend(['RT_USING_PIN']): + src += ['drv_gpio.c'] + +if GetDepend(['RT_USING_SERIAL']): + src += ['drv_usart.c'] + +path = [cwd] + +group = DefineGroup('Drivers', src, depend = [''], CPPPATH = path) + +Return('group') diff --git a/bsp/nuclei/libraries/gd32vf103/HAL_Drivers/drv_config.h b/bsp/nuclei/libraries/gd32vf103/HAL_Drivers/drv_config.h new file mode 100644 index 0000000000..bb24afa19e --- /dev/null +++ b/bsp/nuclei/libraries/gd32vf103/HAL_Drivers/drv_config.h @@ -0,0 +1,26 @@ +/* + * Copyright (c) 2006-2020, RT-Thread Development Team + * + * SPDX-License-Identifier: Apache-2.0 + * + * Change Logs: + * Date Author Notes + * 2020-04-08 hqfang first version + */ + +#ifndef __DRV_CONFIG_H__ +#define __DRV_CONFIG_H__ + +#include <board.h> +#include <rtthread.h> + +#ifdef __cplusplus +extern "C" { +#endif + + +#ifdef __cplusplus +} +#endif + +#endif diff --git a/bsp/nuclei/libraries/gd32vf103/HAL_Drivers/drv_gpio.c b/bsp/nuclei/libraries/gd32vf103/HAL_Drivers/drv_gpio.c new file mode 100644 index 0000000000..75ab81f18e --- /dev/null +++ b/bsp/nuclei/libraries/gd32vf103/HAL_Drivers/drv_gpio.c @@ -0,0 +1,520 @@ +/* + * Copyright (c) 2006-2020, RT-Thread Development Team + * + * SPDX-License-Identifier: Apache-2.0 + * + * Change Logs: + * Date Author Notes + * 2020-04-09 hqfang first version + */ + +#include "drv_gpio.h" + +#ifdef RT_USING_PIN + +static const struct pin_index pins[] = +{ + + __GD32_PIN(0, A, 0), + __GD32_PIN(1, A, 1), + __GD32_PIN(2, A, 2), + __GD32_PIN(3, A, 3), + __GD32_PIN(4, A, 4), + __GD32_PIN(5, A, 5), + __GD32_PIN(6, A, 6), + __GD32_PIN(7, A, 7), + __GD32_PIN(8, A, 8), + __GD32_PIN(9, A, 9), + __GD32_PIN(10, A, 10), + __GD32_PIN(11, A, 11), + __GD32_PIN(12, A, 12), + __GD32_PIN(13, A, 13), + __GD32_PIN(14, A, 14), + __GD32_PIN(15, A, 15), + + __GD32_PIN(16, B, 0), + __GD32_PIN(17, B, 1), + __GD32_PIN(18, B, 2), + __GD32_PIN(19, B, 3), + __GD32_PIN(20, B, 4), + __GD32_PIN(21, B, 5), + __GD32_PIN(22, B, 6), + __GD32_PIN(23, B, 7), + __GD32_PIN(24, B, 8), + __GD32_PIN(25, B, 9), + __GD32_PIN(26, B, 10), + __GD32_PIN(27, B, 11), + __GD32_PIN(28, B, 12), + __GD32_PIN(29, B, 13), + __GD32_PIN(30, B, 14), + __GD32_PIN(31, B, 15), + + __GD32_PIN(32, C, 0), + __GD32_PIN(33, C, 1), + __GD32_PIN(34, C, 2), + __GD32_PIN(35, C, 3), + __GD32_PIN(36, C, 4), + __GD32_PIN(37, C, 5), + __GD32_PIN(38, C, 6), + __GD32_PIN(39, C, 7), + __GD32_PIN(40, C, 8), + __GD32_PIN(41, C, 9), + __GD32_PIN(42, C, 10), + __GD32_PIN(43, C, 11), + __GD32_PIN(44, C, 12), + __GD32_PIN(45, C, 13), + __GD32_PIN(46, C, 14), + __GD32_PIN(47, C, 15), + + __GD32_PIN(48, D, 0), + __GD32_PIN(49, D, 1), + __GD32_PIN(50, D, 2), + __GD32_PIN(51, D, 3), + __GD32_PIN(52, D, 4), + __GD32_PIN(53, D, 5), + __GD32_PIN(54, D, 6), + __GD32_PIN(55, D, 7), + __GD32_PIN(56, D, 8), + __GD32_PIN(57, D, 9), + __GD32_PIN(58, D, 10), + __GD32_PIN(59, D, 11), + __GD32_PIN(60, D, 12), + __GD32_PIN(61, D, 13), + __GD32_PIN(62, D, 14), + __GD32_PIN(63, D, 15), + + __GD32_PIN(64, E, 0), + __GD32_PIN(65, E, 1), + __GD32_PIN(66, E, 2), + __GD32_PIN(67, E, 3), + __GD32_PIN(68, E, 4), + __GD32_PIN(69, E, 5), + __GD32_PIN(70, E, 6), + __GD32_PIN(71, E, 7), + __GD32_PIN(72, E, 8), + __GD32_PIN(73, E, 9), + __GD32_PIN(74, E, 10), + __GD32_PIN(75, E, 11), + __GD32_PIN(76, E, 12), + __GD32_PIN(77, E, 13), + __GD32_PIN(78, E, 14), + __GD32_PIN(79, E, 15), +}; + +static const struct pin_irq_map pin_irq_map[] = +{ + {GPIO_PIN_0, EXTI0_IRQn}, + {GPIO_PIN_1, EXTI1_IRQn}, + {GPIO_PIN_2, EXTI2_IRQn}, + {GPIO_PIN_3, EXTI3_IRQn}, + {GPIO_PIN_4, EXTI4_IRQn}, + {GPIO_PIN_5, EXTI5_9_IRQn}, + {GPIO_PIN_6, EXTI5_9_IRQn}, + {GPIO_PIN_7, EXTI5_9_IRQn}, + {GPIO_PIN_8, EXTI5_9_IRQn}, + {GPIO_PIN_9, EXTI5_9_IRQn}, + {GPIO_PIN_10, EXTI10_15_IRQn}, + {GPIO_PIN_11, EXTI10_15_IRQn}, + {GPIO_PIN_12, EXTI10_15_IRQn}, + {GPIO_PIN_13, EXTI10_15_IRQn}, + {GPIO_PIN_14, EXTI10_15_IRQn}, + {GPIO_PIN_15, EXTI10_15_IRQn}, +}; + +static struct rt_pin_irq_hdr pin_irq_hdr_tab[] = +{ + {-1, 0, RT_NULL, RT_NULL}, + {-1, 0, RT_NULL, RT_NULL}, + {-1, 0, RT_NULL, RT_NULL}, + {-1, 0, RT_NULL, RT_NULL}, + {-1, 0, RT_NULL, RT_NULL}, + {-1, 0, RT_NULL, RT_NULL}, + {-1, 0, RT_NULL, RT_NULL}, + {-1, 0, RT_NULL, RT_NULL}, + {-1, 0, RT_NULL, RT_NULL}, + {-1, 0, RT_NULL, RT_NULL}, + {-1, 0, RT_NULL, RT_NULL}, + {-1, 0, RT_NULL, RT_NULL}, + {-1, 0, RT_NULL, RT_NULL}, + {-1, 0, RT_NULL, RT_NULL}, + {-1, 0, RT_NULL, RT_NULL}, + {-1, 0, RT_NULL, RT_NULL}, +}; +static uint32_t pin_irq_enable_mask = 0; + +#define ITEM_NUM(items) sizeof(items) / sizeof(items[0]) +static const struct pin_index *get_pin(uint8_t pin) +{ + const struct pin_index *index; + + if (pin < ITEM_NUM(pins)) + { + index = &pins[pin]; + if (index->index == -1) + index = RT_NULL; + } + else + { + index = RT_NULL; + } + + return index; +}; + +static void gd32_pin_write(rt_device_t dev, rt_base_t pin, rt_base_t value) +{ + const struct pin_index *index; + + index = get_pin(pin); + if (index == RT_NULL) + { + return; + } + + gpio_bit_write(index->gpio, index->pin, (bit_status)value); +} + +static int gd32_pin_read(rt_device_t dev, rt_base_t pin) +{ + int value; + const struct pin_index *index; + + value = PIN_LOW; + + index = get_pin(pin); + if (index == RT_NULL) + { + return value; + } + + value = gpio_input_bit_get(index->gpio, index->pin); + + return value; +} + +static void gd32_pin_mode(rt_device_t dev, rt_base_t pin, rt_base_t mode) +{ + const struct pin_index *index; + rt_uint32_t pin_mode; + + index = get_pin(pin); + if (index == RT_NULL) + { + return; + } + + pin_mode = GPIO_MODE_OUT_PP; + + switch (mode) + { + case PIN_MODE_OUTPUT: + /* output setting */ + pin_mode = GPIO_MODE_OUT_PP; + break; + case PIN_MODE_OUTPUT_OD: + /* output setting: od. */ + pin_mode = GPIO_MODE_OUT_OD; + break; + case PIN_MODE_INPUT: + /* input setting: not pull. */ + pin_mode = GPIO_MODE_IN_FLOATING; + break; + case PIN_MODE_INPUT_PULLUP: + /* input setting: pull up. */ + pin_mode = GPIO_MODE_IPU; + break; + case PIN_MODE_INPUT_PULLDOWN: + /* input setting: pull down. */ + pin_mode = GPIO_MODE_IPD; + break; + default: + break; + } + + gpio_init(index->gpio, pin_mode, GPIO_OSPEED_50MHZ, index->pin); +} + +rt_inline rt_int32_t bit2bitno(rt_uint32_t bit) +{ + int i; + for (i = 0; i < 32; i++) + { + if ((0x01 << i) == bit) + { + return i; + } + } + return -1; +} + +rt_inline const struct pin_irq_map *get_pin_irq_map(uint32_t pinbit) +{ + rt_int32_t mapindex = bit2bitno(pinbit); + if (mapindex < 0 || mapindex >= ITEM_NUM(pin_irq_map)) + { + return RT_NULL; + } + return &pin_irq_map[mapindex]; +}; + +static rt_err_t gd32_pin_attach_irq(struct rt_device *device, rt_int32_t pin, + rt_uint32_t mode, void (*hdr)(void *args), void *args) +{ + const struct pin_index *index; + rt_base_t level; + rt_int32_t irqindex = -1; + + index = get_pin(pin); + if (index == RT_NULL) + { + return RT_ENOSYS; + } + irqindex = bit2bitno(index->pin); + if (irqindex < 0 || irqindex >= ITEM_NUM(pin_irq_map)) + { + return RT_ENOSYS; + } + + level = rt_hw_interrupt_disable(); + if (pin_irq_hdr_tab[irqindex].pin == pin && + pin_irq_hdr_tab[irqindex].hdr == hdr && + pin_irq_hdr_tab[irqindex].mode == mode && + pin_irq_hdr_tab[irqindex].args == args) + { + rt_hw_interrupt_enable(level); + return RT_EOK; + } + if (pin_irq_hdr_tab[irqindex].pin != -1) + { + rt_hw_interrupt_enable(level); + return RT_EBUSY; + } + pin_irq_hdr_tab[irqindex].pin = pin; + pin_irq_hdr_tab[irqindex].hdr = hdr; + pin_irq_hdr_tab[irqindex].mode = mode; + pin_irq_hdr_tab[irqindex].args = args; + rt_hw_interrupt_enable(level); + + return RT_EOK; +} + +static rt_err_t gd32_pin_dettach_irq(struct rt_device *device, rt_int32_t pin) +{ + const struct pin_index *index; + rt_base_t level; + rt_int32_t irqindex = -1; + + index = get_pin(pin); + if (index == RT_NULL) + { + return RT_ENOSYS; + } + irqindex = bit2bitno(index->pin); + if (irqindex < 0 || irqindex >= ITEM_NUM(pin_irq_map)) + { + return RT_ENOSYS; + } + + level = rt_hw_interrupt_disable(); + if (pin_irq_hdr_tab[irqindex].pin == -1) + { + rt_hw_interrupt_enable(level); + return RT_EOK; + } + pin_irq_hdr_tab[irqindex].pin = -1; + pin_irq_hdr_tab[irqindex].hdr = RT_NULL; + pin_irq_hdr_tab[irqindex].mode = 0; + pin_irq_hdr_tab[irqindex].args = RT_NULL; + rt_hw_interrupt_enable(level); + + return RT_EOK; +} + +static rt_err_t gd32_pin_irq_enable(struct rt_device *device, rt_base_t pin, + rt_uint32_t enabled) +{ + const struct pin_index *index; + const struct pin_irq_map *irqmap; + rt_base_t level; + rt_int32_t irqindex = -1; + exti_trig_type_enum trigger_mode; + + index = get_pin(pin); + if (index == RT_NULL) + { + return RT_ENOSYS; + } + + if (enabled == PIN_IRQ_ENABLE) + { + irqindex = bit2bitno(index->pin); + if (irqindex < 0 || irqindex >= ITEM_NUM(pin_irq_map)) + { + return RT_ENOSYS; + } + + level = rt_hw_interrupt_disable(); + + if (pin_irq_hdr_tab[irqindex].pin == -1) + { + rt_hw_interrupt_enable(level); + return RT_ENOSYS; + } + + irqmap = &pin_irq_map[irqindex]; + + switch (pin_irq_hdr_tab[irqindex].mode) + { + case PIN_IRQ_MODE_RISING: + trigger_mode = EXTI_TRIG_RISING; + break; + case PIN_IRQ_MODE_FALLING: + trigger_mode = EXTI_TRIG_FALLING; + break; + case PIN_IRQ_MODE_RISING_FALLING: + trigger_mode = EXTI_TRIG_BOTH; + break; + default: + rt_hw_interrupt_enable(level); + return RT_EINVAL; + } + /* connect EXTI line to GPIO pin */ + gpio_exti_source_select(index->gpio, index->pin); + + /* configure EXTI line */ + exti_init((exti_line_enum)(index->pin), EXTI_INTERRUPT, trigger_mode); + exti_interrupt_flag_clear((exti_line_enum)(index->pin)); + + /* enable and set interrupt priority */ + ECLIC_SetShvIRQ(irqmap->irqno, ECLIC_NON_VECTOR_INTERRUPT); + ECLIC_SetLevelIRQ(irqmap->irqno, 1); + ECLIC_EnableIRQ(irqmap->irqno); + pin_irq_enable_mask |= irqmap->pinbit; + + rt_hw_interrupt_enable(level); + } + else if (enabled == PIN_IRQ_DISABLE) + { + irqmap = get_pin_irq_map(index->pin); + if (irqmap == RT_NULL) + { + return RT_EINVAL; + } + if ((irqmap->pinbit >= GPIO_PIN_5) && (irqmap->pinbit <= GPIO_PIN_9)) + { + if (!(pin_irq_enable_mask & (GPIO_PIN_5 | GPIO_PIN_6 | GPIO_PIN_7 | GPIO_PIN_8 | GPIO_PIN_9))) + { + ECLIC_DisableIRQ(irqmap->irqno); + } + } + else if ((irqmap->pinbit >= GPIO_PIN_10) && (irqmap->pinbit <= GPIO_PIN_15)) + { + if (!(pin_irq_enable_mask & (GPIO_PIN_10 | GPIO_PIN_11 | GPIO_PIN_12 | GPIO_PIN_13 | GPIO_PIN_14 | GPIO_PIN_15))) + { + ECLIC_DisableIRQ(irqmap->irqno); + } + } + else + { + ECLIC_DisableIRQ(irqmap->irqno); + } + } + else + { + return -RT_ENOSYS; + } + + return RT_EOK; +} +const static struct rt_pin_ops _gd32_pin_ops = +{ + gd32_pin_mode, + gd32_pin_write, + gd32_pin_read, + gd32_pin_attach_irq, + gd32_pin_dettach_irq, + gd32_pin_irq_enable, +}; + +rt_inline void pin_irq_hdr(int irqno) +{ + if (pin_irq_hdr_tab[irqno].hdr) + { + pin_irq_hdr_tab[irqno].hdr(pin_irq_hdr_tab[irqno].args); + } +} + +void GD32_GPIO_EXTI_IRQHandler(rt_int8_t exti_line) +{ + if (RESET != exti_interrupt_flag_get((exti_line_enum)(1 << exti_line))) + { + pin_irq_hdr(exti_line); + exti_interrupt_flag_clear((exti_line_enum)(1 << exti_line)); + } +} + +void EXTI0_IRQHandler(void) +{ + rt_interrupt_enter(); + GD32_GPIO_EXTI_IRQHandler(0); + rt_interrupt_leave(); +} +void EXTI1_IRQHandler(void) +{ + rt_interrupt_enter(); + GD32_GPIO_EXTI_IRQHandler(1); + rt_interrupt_leave(); +} +void EXTI2_IRQHandler(void) +{ + rt_interrupt_enter(); + GD32_GPIO_EXTI_IRQHandler(2); + rt_interrupt_leave(); +} +void EXTI3_IRQHandler(void) +{ + rt_interrupt_enter(); + GD32_GPIO_EXTI_IRQHandler(3); + rt_interrupt_leave(); +} +void EXTI4_IRQHandler(void) +{ + rt_interrupt_enter(); + GD32_GPIO_EXTI_IRQHandler(4); + rt_interrupt_leave(); +} +void EXTI5_9_IRQHandler(void) +{ + rt_interrupt_enter(); + GD32_GPIO_EXTI_IRQHandler(5); + GD32_GPIO_EXTI_IRQHandler(6); + GD32_GPIO_EXTI_IRQHandler(7); + GD32_GPIO_EXTI_IRQHandler(8); + GD32_GPIO_EXTI_IRQHandler(9); + rt_interrupt_leave(); +} +void EXTI10_15_IRQHandler(void) +{ + rt_interrupt_enter(); + GD32_GPIO_EXTI_IRQHandler(10); + GD32_GPIO_EXTI_IRQHandler(11); + GD32_GPIO_EXTI_IRQHandler(12); + GD32_GPIO_EXTI_IRQHandler(13); + GD32_GPIO_EXTI_IRQHandler(14); + GD32_GPIO_EXTI_IRQHandler(15); + rt_interrupt_leave(); +} + +int rt_hw_pin_init(void) +{ + rcu_periph_clock_enable(RCU_GPIOA); + rcu_periph_clock_enable(RCU_GPIOB); + rcu_periph_clock_enable(RCU_GPIOC); + rcu_periph_clock_enable(RCU_GPIOD); + rcu_periph_clock_enable(RCU_GPIOE); + rcu_periph_clock_enable(RCU_AF); + return rt_device_pin_register("pin", &_gd32_pin_ops, RT_NULL); +} +INIT_BOARD_EXPORT(rt_hw_pin_init); + +#endif /* RT_USING_PIN */ diff --git a/bsp/nuclei/libraries/gd32vf103/HAL_Drivers/drv_gpio.h b/bsp/nuclei/libraries/gd32vf103/HAL_Drivers/drv_gpio.h new file mode 100644 index 0000000000..93d24a8317 --- /dev/null +++ b/bsp/nuclei/libraries/gd32vf103/HAL_Drivers/drv_gpio.h @@ -0,0 +1,51 @@ +/* + * Copyright (c) 2006-2020, RT-Thread Development Team + * + * SPDX-License-Identifier: Apache-2.0 + * + * Change Logs: + * Date Author Notes + * 2018-11-06 balanceTWK first version + * 2020-04-15 hqfang Modify for gd32vf103 + */ + +#ifndef __DRV_GPIO_H__ +#define __DRV_GPIO_H__ + +#include <rtthread.h> +#include <rtdevice.h> +#include <rthw.h> +#include <drv_config.h> + +#define __GD32_PORT(port) GPIO##port + +#define GET_PIN(PORTx,PIN) (rt_base_t)((16 * ( ((rt_base_t)__GD32_PORT(PORTx) - (rt_base_t)GPIOA)/(0x0400UL) )) + PIN) + +#define __GD32_PIN(index, gpio, gpio_index) \ + { \ + index, GPIO##gpio, GPIO_PIN_##gpio_index \ + } + +#define __GD32_PIN_RESERVE \ + { \ + -1, 0, 0 \ + } + +/* GD32 GPIO driver */ +struct pin_index +{ + int index; + uint32_t gpio; + uint32_t pin; +}; + +struct pin_irq_map +{ + rt_uint16_t pinbit; + IRQn_Type irqno; +}; + +int rt_hw_pin_init(void); + +#endif /* __DRV_GPIO_H__ */ + diff --git a/bsp/nuclei/libraries/gd32vf103/HAL_Drivers/drv_usart.c b/bsp/nuclei/libraries/gd32vf103/HAL_Drivers/drv_usart.c new file mode 100644 index 0000000000..00fac33b3e --- /dev/null +++ b/bsp/nuclei/libraries/gd32vf103/HAL_Drivers/drv_usart.c @@ -0,0 +1,347 @@ +/* + * Copyright (c) 2006-2020, RT-Thread Development Team + * + * SPDX-License-Identifier: Apache-2.0 + * + * Change Logs: + * Date Author Notes + * 2019-07-23 tyustli first version + * 2020-04-02 hqfang modified for Nuclei + */ + +#include <drv_usart.h> + +#ifdef RT_USING_SERIAL + +#if !defined(BSP_USING_UART0) && !defined(BSP_USING_UART1) && !defined(BSP_USING_UART2) \ + && !defined(BSP_USING_UART3) && !defined(BSP_USING_UART4) + #error "Please define at least one BSP_USING_UARTx" + /* this driver can be disabled at menuconfig -> RT-Thread Components -> Device Drivers */ +#endif + +enum +{ +#ifdef BSP_USING_UART0 + GDUART0_INDEX, +#endif +#ifdef BSP_USING_UART1 + GDUART1_INDEX, +#endif +#ifdef BSP_USING_UART2 + GDUART2_INDEX, +#endif +#ifdef BSP_USING_UART3 + GDUART3_INDEX, +#endif +#ifdef BSP_USING_UART4 + GDUART4_INDEX, +#endif +}; + +static struct gd32_uart_config uart_config[] = +{ +#ifdef BSP_USING_UART0 + { + "uart0", + USART0, + USART0_IRQn, + }, +#endif +#ifdef BSP_USING_UART1 + { + "uart1", + USART1, + USART1_IRQn, + }, +#endif +#ifdef BSP_USING_UART2 + { + "uart2", + USART2, + USART2_IRQn, + }, +#endif +#ifdef BSP_USING_UART3 + { + "uart3", + USART3, + USART3_IRQn, + }, +#endif +#ifdef BSP_USING_UART4 + { + "uart4", + UART4, + UART4_IRQn, + }, +#endif +}; + +static struct gd32_uart uart_obj[sizeof(uart_config) / sizeof(uart_config[0])] = {0}; + +static rt_err_t gd32_configure(struct rt_serial_device *serial, + struct serial_configure *cfg) +{ + struct gd32_uart *usart_obj; + struct gd32_uart_config *usart; + RT_ASSERT(serial != RT_NULL); + RT_ASSERT(cfg != RT_NULL); + + usart_obj = (struct gd32_uart *) serial->parent.user_data; + usart = usart_obj->config; + RT_ASSERT(usart != RT_NULL); + + usart_deinit(usart->uart_base); + usart_baudrate_set(usart->uart_base, cfg->baud_rate); + + switch (cfg->data_bits) + { + case DATA_BITS_8: + usart_word_length_set(usart->uart_base, USART_WL_8BIT); + break; + + case DATA_BITS_9: + usart_word_length_set(usart->uart_base, USART_WL_9BIT); + break; + default: + usart_word_length_set(usart->uart_base, USART_WL_8BIT); + break; + } + + switch (cfg->stop_bits) + { + case STOP_BITS_1: + usart_stop_bit_set(usart->uart_base, USART_STB_1BIT); + break; + case STOP_BITS_2: + usart_stop_bit_set(usart->uart_base, USART_STB_2BIT); + break; + default: + usart_stop_bit_set(usart->uart_base, USART_STB_1BIT); + break; + } + + switch (cfg->parity) + { + case PARITY_NONE: + usart_parity_config(usart->uart_base, USART_PM_NONE); + break; + case PARITY_ODD: + usart_parity_config(usart->uart_base, USART_PM_ODD); + break; + case PARITY_EVEN: + usart_parity_config(usart->uart_base, USART_PM_EVEN); + break; + default: + usart_parity_config(usart->uart_base, USART_PM_NONE); + break; + } + usart_hardware_flow_rts_config(usart->uart_base, USART_RTS_DISABLE); + usart_hardware_flow_cts_config(usart->uart_base, USART_RTS_DISABLE); + usart_receive_config(usart->uart_base, USART_RECEIVE_ENABLE); + usart_transmit_config(usart->uart_base, USART_TRANSMIT_ENABLE); + usart_enable(usart->uart_base); + + return RT_EOK; +} + +static rt_err_t gd32_control(struct rt_serial_device *serial, int cmd, + void *arg) +{ + struct gd32_uart *usart_obj; + struct gd32_uart_config *usart; + + RT_ASSERT(serial != RT_NULL); + usart_obj = (struct gd32_uart *) serial->parent.user_data; + usart = usart_obj->config; + RT_ASSERT(usart != RT_NULL); + + switch (cmd) + { + case RT_DEVICE_CTRL_CLR_INT: + ECLIC_DisableIRQ(usart->irqn); + usart_interrupt_disable(usart->uart_base, USART_INT_RBNE); + break; + case RT_DEVICE_CTRL_SET_INT: + ECLIC_EnableIRQ(usart->irqn); + /* enable USART0 receive interrupt */ + usart_interrupt_enable(usart->uart_base, USART_INT_RBNE); + break; + } + + return RT_EOK; +} + +static int gd32_putc(struct rt_serial_device *serial, char ch) +{ + struct gd32_uart *usart_obj; + struct gd32_uart_config *usart; + + RT_ASSERT(serial != RT_NULL); + usart_obj = (struct gd32_uart *) serial->parent.user_data; + usart = usart_obj->config; + RT_ASSERT(usart != RT_NULL); + + usart_data_transmit(usart->uart_base, (uint8_t) ch); + while (usart_flag_get(usart->uart_base, USART_FLAG_TBE) == RESET); + + return 1; +} + +static int gd32_getc(struct rt_serial_device *serial) +{ + int ch; + struct gd32_uart *usart_obj; + struct gd32_uart_config *usart; + + RT_ASSERT(serial != RT_NULL); + usart_obj = (struct gd32_uart *) serial->parent.user_data; + usart = usart_obj->config; + RT_ASSERT(usart != RT_NULL); + + ch = -1; + if (RESET != usart_flag_get(usart->uart_base, USART_FLAG_RBNE)) + { + ch = usart_data_receive(usart->uart_base) & 0xff; + } + + return ch; +} + +static const struct rt_uart_ops gd32_uart_ops = { gd32_configure, gd32_control, + gd32_putc, gd32_getc, + RT_NULL +}; + +static void usart_isr(struct rt_serial_device *serial) +{ + struct gd32_uart *usart_obj; + struct gd32_uart_config *usart; + + RT_ASSERT(serial != RT_NULL); + usart_obj = (struct gd32_uart *) serial->parent.user_data; + usart = usart_obj->config; + RT_ASSERT(usart != RT_NULL); + + if ((usart_interrupt_flag_get(usart->uart_base, USART_INT_FLAG_RBNE) + != RESET) + && (RESET != usart_flag_get(usart->uart_base, USART_FLAG_RBNE))) + { + rt_hw_serial_isr(serial, RT_SERIAL_EVENT_RX_IND); + usart_interrupt_flag_clear(usart->uart_base, USART_INT_FLAG_RBNE); + usart_flag_clear(usart->uart_base, USART_FLAG_RBNE); + } + else + { + if (usart_flag_get(usart->uart_base, USART_FLAG_CTSF) != RESET) + { + usart_flag_clear(usart->uart_base, USART_FLAG_CTSF); + } + + if (usart_flag_get(usart->uart_base, USART_FLAG_LBDF) != RESET) + { + usart_flag_clear(usart->uart_base, USART_FLAG_LBDF); + } + + if (usart_flag_get(usart->uart_base, USART_FLAG_TC) != RESET) + { + usart_flag_clear(usart->uart_base, USART_FLAG_TC); + } + } +} + +#ifdef BSP_USING_UART0 + +void USART0_IRQHandler(void) +{ + rt_interrupt_enter(); + + usart_isr(&uart_obj[GDUART0_INDEX].serial); + + rt_interrupt_leave(); +} + +#endif + +#ifdef BSP_USING_UART1 + +void USART1_IRQHandler(void) +{ + rt_interrupt_enter(); + + usart_isr(&uart_obj[GDUART1_INDEX].serial); + + rt_interrupt_leave(); +} + +#endif + +#ifdef BSP_USING_UART2 + +void USART2_IRQHandler(void) +{ + rt_interrupt_enter(); + + usart_isr(&uart_obj[GDUART2_INDEX].serial); + + rt_interrupt_leave(); +} + +#endif + +#ifdef BSP_USING_UART3 + +void UART3_IRQHandler(void) +{ + rt_interrupt_enter(); + + usart_isr(&uart_obj[GDUART3_INDEX].serial); + + rt_interrupt_leave(); +} + +#endif + +#ifdef BSP_USING_UART4 + +void UART4_IRQHandler(void) +{ + rt_interrupt_enter(); + + usart_isr(&uart_obj[GDUART4_INDEX].serial); + + rt_interrupt_leave(); +} + +#endif + +int rt_hw_usart_init(void) +{ + rt_size_t obj_num; + int index; + + obj_num = sizeof(uart_obj) / sizeof(struct gd32_uart); + struct serial_configure config = RT_SERIAL_CONFIG_DEFAULT; + rt_err_t result = 0; + + for (index = 0; index < obj_num; index++) + { + /* init UART object */ + uart_obj[index].config = &uart_config[index]; + uart_obj[index].serial.ops = &gd32_uart_ops; + uart_obj[index].serial.config = config; + + /* register UART device */ + result = rt_hw_serial_register(&uart_obj[index].serial, + uart_obj[index].config->name, + RT_DEVICE_FLAG_RDWR | RT_DEVICE_FLAG_INT_RX + | RT_DEVICE_FLAG_INT_TX, &uart_obj[index]); + RT_ASSERT(result == RT_EOK); + } + + return result; +} + +#endif /* RT_USING_SERIAL */ + +/******************** end of file *******************/ diff --git a/bsp/nuclei/libraries/gd32vf103/HAL_Drivers/drv_usart.h b/bsp/nuclei/libraries/gd32vf103/HAL_Drivers/drv_usart.h new file mode 100644 index 0000000000..176720c4a2 --- /dev/null +++ b/bsp/nuclei/libraries/gd32vf103/HAL_Drivers/drv_usart.h @@ -0,0 +1,36 @@ +/* + * Copyright (c) 2006-2020, RT-Thread Development Team + * + * SPDX-License-Identifier: Apache-2.0 + * + * Change Logs: + * Date Author Notes + * 2020-04-15 hqfang first version + */ +#ifndef __DRV_UART_H__ +#define __DRV_UART_H__ + +#include <rtthread.h> +#include <rtdevice.h> +#include <drv_config.h> + +/* gd32 config class */ +struct gd32_uart_config +{ + const char *name; + uint32_t uart_base; + IRQn_Type irqn; +}; + +/* gd32 uart dirver class */ +struct gd32_uart +{ + struct gd32_uart_config *config; + struct rt_serial_device serial; +}; + +int rt_hw_usart_init(void); + +#endif /* __DRV_USART_H__ */ + +/******************* end of file *******************/ diff --git a/libcpu/risc-v/SConscript b/libcpu/risc-v/SConscript index 640e46a4fb..024cc5ba44 100644 --- a/libcpu/risc-v/SConscript +++ b/libcpu/risc-v/SConscript @@ -10,7 +10,8 @@ group = [] list = os.listdir(cwd) # add common code files -group = group + SConscript(os.path.join('common', 'SConscript')) +if rtconfig.CPU != "nuclei": + group = group + SConscript(os.path.join('common', 'SConscript')) # cpu porting code files group = group + SConscript(os.path.join(rtconfig.CPU, 'SConscript')) diff --git a/libcpu/risc-v/nuclei/SConscript b/libcpu/risc-v/nuclei/SConscript new file mode 100644 index 0000000000..b0ae20ba02 --- /dev/null +++ b/libcpu/risc-v/nuclei/SConscript @@ -0,0 +1,14 @@ +# RT-Thread building script for component + +from building import * + +Import('rtconfig') + +cwd = GetCurrentDir() +src = Glob('*.c') + Glob('*.cpp') + Glob('*_gcc.S') +CPPPATH = [cwd] +ASFLAGS = '' + +group = DefineGroup('cpu', src, depend = [''], CPPPATH = CPPPATH, ASFLAGS = ASFLAGS) + +Return('group') diff --git a/libcpu/risc-v/nuclei/context_gcc.S b/libcpu/risc-v/nuclei/context_gcc.S new file mode 100644 index 0000000000..fda453940d --- /dev/null +++ b/libcpu/risc-v/nuclei/context_gcc.S @@ -0,0 +1,188 @@ +/* + * Copyright (c) 2019-Present Nuclei Limited. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Change Logs: + * Date Author Notes + * 2020/03/26 Huaqi First Nuclei RISC-V porting implementation + */ + +#include "riscv_encoding.h" + +#ifndef __riscv_32e +#define RT_SAVED_REGNUM 30 +#else +#define RT_SAVED_REGNUM 14 +#endif + +#define RT_CONTEXT_SIZE (RT_SAVED_REGNUM * REGBYTES) + + .extern rt_interrupt_from_thread + .extern rt_interrupt_to_thread + + +.section .text + + +/* + * void rt_hw_context_switch_to(rt_ubase_t to); + * a0 --> to_thread + */ + .globl rt_hw_context_switch_to + +/* Start the first task. This also clears the bit that indicates the FPU is + in use in case the FPU was used before the scheduler was started - which + would otherwise result in the unnecessary leaving of space in the stack + for lazy saving of FPU registers. */ +.align 3 +rt_hw_context_switch_to: + /* Setup Interrupt Stack using + The stack that was used by main() + before the scheduler is started is + no longer required after the scheduler is started. + Interrupt stack pointer is stored in CSR_MSCRATCH */ + la t0, _sp + csrw CSR_MSCRATCH, t0 + LOAD sp, 0x0(a0) /* Read sp from first TCB member(a0) */ + + /* Pop PC from stack and set MEPC */ + LOAD t0, 0 * REGBYTES(sp) + csrw CSR_MEPC, t0 + /* Pop mstatus from stack and set it */ + LOAD t0, (RT_SAVED_REGNUM - 1) * REGBYTES(sp) + csrw CSR_MSTATUS, t0 + /* Interrupt still disable here */ + /* Restore Registers from Stack */ + LOAD x1, 1 * REGBYTES(sp) /* RA */ + LOAD x5, 2 * REGBYTES(sp) + LOAD x6, 3 * REGBYTES(sp) + LOAD x7, 4 * REGBYTES(sp) + LOAD x8, 5 * REGBYTES(sp) + LOAD x9, 6 * REGBYTES(sp) + LOAD x10, 7 * REGBYTES(sp) + LOAD x11, 8 * REGBYTES(sp) + LOAD x12, 9 * REGBYTES(sp) + LOAD x13, 10 * REGBYTES(sp) + LOAD x14, 11 * REGBYTES(sp) + LOAD x15, 12 * REGBYTES(sp) +#ifndef __riscv_32e + LOAD x16, 13 * REGBYTES(sp) + LOAD x17, 14 * REGBYTES(sp) + LOAD x18, 15 * REGBYTES(sp) + LOAD x19, 16 * REGBYTES(sp) + LOAD x20, 17 * REGBYTES(sp) + LOAD x21, 18 * REGBYTES(sp) + LOAD x22, 19 * REGBYTES(sp) + LOAD x23, 20 * REGBYTES(sp) + LOAD x24, 21 * REGBYTES(sp) + LOAD x25, 22 * REGBYTES(sp) + LOAD x26, 23 * REGBYTES(sp) + LOAD x27, 24 * REGBYTES(sp) + LOAD x28, 25 * REGBYTES(sp) + LOAD x29, 26 * REGBYTES(sp) + LOAD x30, 27 * REGBYTES(sp) + LOAD x31, 28 * REGBYTES(sp) +#endif + + addi sp, sp, RT_CONTEXT_SIZE + + mret + +.align 2 +.global eclic_msip_handler +eclic_msip_handler: + addi sp, sp, -RT_CONTEXT_SIZE + STORE x1, 1 * REGBYTES(sp) /* RA */ + STORE x5, 2 * REGBYTES(sp) + STORE x6, 3 * REGBYTES(sp) + STORE x7, 4 * REGBYTES(sp) + STORE x8, 5 * REGBYTES(sp) + STORE x9, 6 * REGBYTES(sp) + STORE x10, 7 * REGBYTES(sp) + STORE x11, 8 * REGBYTES(sp) + STORE x12, 9 * REGBYTES(sp) + STORE x13, 10 * REGBYTES(sp) + STORE x14, 11 * REGBYTES(sp) + STORE x15, 12 * REGBYTES(sp) +#ifndef __riscv_32e + STORE x16, 13 * REGBYTES(sp) + STORE x17, 14 * REGBYTES(sp) + STORE x18, 15 * REGBYTES(sp) + STORE x19, 16 * REGBYTES(sp) + STORE x20, 17 * REGBYTES(sp) + STORE x21, 18 * REGBYTES(sp) + STORE x22, 19 * REGBYTES(sp) + STORE x23, 20 * REGBYTES(sp) + STORE x24, 21 * REGBYTES(sp) + STORE x25, 22 * REGBYTES(sp) + STORE x26, 23 * REGBYTES(sp) + STORE x27, 24 * REGBYTES(sp) + STORE x28, 25 * REGBYTES(sp) + STORE x29, 26 * REGBYTES(sp) + STORE x30, 27 * REGBYTES(sp) + STORE x31, 28 * REGBYTES(sp) +#endif + /* Push mstatus to stack */ + csrr t0, CSR_MSTATUS + STORE t0, (RT_SAVED_REGNUM - 1) * REGBYTES(sp) + + /* Push additional registers */ + + /* Store sp to task stack */ + LOAD t0, rt_interrupt_from_thread + STORE sp, 0(t0) + + csrr t0, CSR_MEPC + STORE t0, 0(sp) + + jal rt_hw_taskswitch + + /* Switch task context */ + LOAD t0, rt_interrupt_to_thread + LOAD sp, 0x0(t0) + + /* Pop PC from stack and set MEPC */ + LOAD t0, 0 * REGBYTES(sp) + csrw CSR_MEPC, t0 + + /* Pop additional registers */ + + /* Pop mstatus from stack and set it */ + LOAD t0, (RT_SAVED_REGNUM - 1) * REGBYTES(sp) + csrw CSR_MSTATUS, t0 + /* Interrupt still disable here */ + /* Restore Registers from Stack */ + LOAD x1, 1 * REGBYTES(sp) /* RA */ + LOAD x5, 2 * REGBYTES(sp) + LOAD x6, 3 * REGBYTES(sp) + LOAD x7, 4 * REGBYTES(sp) + LOAD x8, 5 * REGBYTES(sp) + LOAD x9, 6 * REGBYTES(sp) + LOAD x10, 7 * REGBYTES(sp) + LOAD x11, 8 * REGBYTES(sp) + LOAD x12, 9 * REGBYTES(sp) + LOAD x13, 10 * REGBYTES(sp) + LOAD x14, 11 * REGBYTES(sp) + LOAD x15, 12 * REGBYTES(sp) +#ifndef __riscv_32e + LOAD x16, 13 * REGBYTES(sp) + LOAD x17, 14 * REGBYTES(sp) + LOAD x18, 15 * REGBYTES(sp) + LOAD x19, 16 * REGBYTES(sp) + LOAD x20, 17 * REGBYTES(sp) + LOAD x21, 18 * REGBYTES(sp) + LOAD x22, 19 * REGBYTES(sp) + LOAD x23, 20 * REGBYTES(sp) + LOAD x24, 21 * REGBYTES(sp) + LOAD x25, 22 * REGBYTES(sp) + LOAD x26, 23 * REGBYTES(sp) + LOAD x27, 24 * REGBYTES(sp) + LOAD x28, 25 * REGBYTES(sp) + LOAD x29, 26 * REGBYTES(sp) + LOAD x30, 27 * REGBYTES(sp) + LOAD x31, 28 * REGBYTES(sp) +#endif + + addi sp, sp, RT_CONTEXT_SIZE + mret diff --git a/libcpu/risc-v/nuclei/cpuport.c b/libcpu/risc-v/nuclei/cpuport.c new file mode 100644 index 0000000000..fad9afdf4c --- /dev/null +++ b/libcpu/risc-v/nuclei/cpuport.c @@ -0,0 +1,259 @@ +/* + * Copyright (c) 2006-2018, RT-Thread Development Team + * Copyright (c) 2019-Present Nuclei Limited. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Change Logs: + * Date Author Notes + * 2020/03/26 Huaqi Nuclei RISC-V Core porting code. + */ + +#include <rthw.h> +#include <rtthread.h> +#include <sys/types.h> +#include <unistd.h> + +#include "cpuport.h" + +#define SYSTICK_TICK_CONST (SOC_TIMER_FREQ / RT_TICK_PER_SECOND) + +/* Interrupt level for kernel systimer interrupt and software timer interrupt */ +#define RT_KERNEL_INTERRUPT_LEVEL 1 + +/* Initial CSR MSTATUS value when thread created */ +#define RT_INITIAL_MSTATUS (MSTATUS_MPP | MSTATUS_MPIE | MSTATUS_FS_INITIAL) + +/** + * @brief from thread used interrupt context switch + * + */ +volatile rt_ubase_t rt_interrupt_from_thread = 0; +/** + * @brief to thread used interrupt context switch + * + */ +volatile rt_ubase_t rt_interrupt_to_thread = 0; +/** + * @brief flag to indicate context switch in interrupt or not + * + */ +volatile rt_ubase_t rt_thread_switch_interrupt_flag = 0; + +/** + * @brief thread stack frame of saved context + * + */ +struct rt_hw_stack_frame +{ + rt_ubase_t epc; /*!< epc - epc - program counter */ + rt_ubase_t ra; /*!< x1 - ra - return address for jumps */ + rt_ubase_t t0; /*!< x5 - t0 - temporary register 0 */ + rt_ubase_t t1; /*!< x6 - t1 - temporary register 1 */ + rt_ubase_t t2; /*!< x7 - t2 - temporary register 2 */ + rt_ubase_t s0_fp; /*!< x8 - s0/fp - saved register 0 or frame pointer */ + rt_ubase_t s1; /*!< x9 - s1 - saved register 1 */ + rt_ubase_t a0; /*!< x10 - a0 - return value or function argument 0 */ + rt_ubase_t a1; /*!< x11 - a1 - return value or function argument 1 */ + rt_ubase_t a2; /*!< x12 - a2 - function argument 2 */ + rt_ubase_t a3; /*!< x13 - a3 - function argument 3 */ + rt_ubase_t a4; /*!< x14 - a4 - function argument 4 */ + rt_ubase_t a5; /*!< x15 - a5 - function argument 5 */ +#ifndef __riscv_32e + rt_ubase_t a6; /*!< x16 - a6 - function argument 6 */ + rt_ubase_t a7; /*!< x17 - s7 - function argument 7 */ + rt_ubase_t s2; /*!< x18 - s2 - saved register 2 */ + rt_ubase_t s3; /*!< x19 - s3 - saved register 3 */ + rt_ubase_t s4; /*!< x20 - s4 - saved register 4 */ + rt_ubase_t s5; /*!< x21 - s5 - saved register 5 */ + rt_ubase_t s6; /*!< x22 - s6 - saved register 6 */ + rt_ubase_t s7; /*!< x23 - s7 - saved register 7 */ + rt_ubase_t s8; /*!< x24 - s8 - saved register 8 */ + rt_ubase_t s9; /*!< x25 - s9 - saved register 9 */ + rt_ubase_t s10; /*!< x26 - s10 - saved register 10 */ + rt_ubase_t s11; /*!< x27 - s11 - saved register 11 */ + rt_ubase_t t3; /*!< x28 - t3 - temporary register 3 */ + rt_ubase_t t4; /*!< x29 - t4 - temporary register 4 */ + rt_ubase_t t5; /*!< x30 - t5 - temporary register 5 */ + rt_ubase_t t6; /*!< x31 - t6 - temporary register 6 */ +#endif + rt_ubase_t mstatus; /*!< - machine status register */ +}; + +/** + * This function will initialize thread stack + * + * @param tentry the entry of thread + * @param parameter the parameter of entry + * @param stack_addr the beginning stack address + * @param texit the function will be called when thread exit + * + * @return stack address + */ +rt_uint8_t *rt_hw_stack_init(void *tentry, + void *parameter, + rt_uint8_t *stack_addr, + void *texit) +{ + struct rt_hw_stack_frame *frame; + rt_uint8_t *stk; + int i; + + stk = stack_addr + sizeof(rt_ubase_t); + stk = (rt_uint8_t *)RT_ALIGN_DOWN((rt_ubase_t)stk, REGBYTES); + stk -= sizeof(struct rt_hw_stack_frame); + + frame = (struct rt_hw_stack_frame *)stk; + + for (i = 0; i < sizeof(struct rt_hw_stack_frame) / sizeof(rt_ubase_t); i++) + { + ((rt_ubase_t *)frame)[i] = 0xdeadbeef; + } + + frame->ra = (rt_ubase_t)texit; + frame->a0 = (rt_ubase_t)parameter; + frame->epc = (rt_ubase_t)tentry; + + frame->mstatus = RT_INITIAL_MSTATUS; + + return stk; +} + +/** + * @brief Do rt-thread context switch in interrupt context + * + * @param from thread sp of from thread + * @param to thread sp of to thread + */ +void rt_hw_context_switch_interrupt(rt_ubase_t from, rt_ubase_t to) +{ + if (rt_thread_switch_interrupt_flag == 0) + rt_interrupt_from_thread = from; + + rt_interrupt_to_thread = to; + rt_thread_switch_interrupt_flag = 1; + RT_YIELD(); +} + +/** + * @brief Do rt-thread context switch in task context + * + * @param from thread sp of from thread + * @param to thread sp of to thread + */ +void rt_hw_context_switch(rt_ubase_t from, rt_ubase_t to) +{ + rt_interrupt_from_thread = from; + rt_interrupt_to_thread = to; + RT_YIELD(); +} + +/** + * @brief shutdown CPU + * + */ +void rt_hw_cpu_shutdown() +{ + rt_uint32_t level; + rt_kprintf("shutdown...\n"); + + level = rt_hw_interrupt_disable(); + while (level) + { + RT_ASSERT(0); + } +} + +/** + * @brief Do extra task switch code + * + * @details + * + * - Clear software timer interrupt request flag + * - clear rt_thread_switch_interrupt_flag to 0 + */ +void rt_hw_taskswitch(void) +{ + /* Clear Software IRQ, A MUST */ + SysTimer_ClearSWIRQ(); + rt_thread_switch_interrupt_flag = 0; +} + +/** + * @brief Setup systimer and software timer interrupt + * + * @details + * + * - Set Systimer interrupt as NON-VECTOR interrupt with lowest interrupt level + * - Set software timer interrupt as VECTOR interrupt with lowest interrupt level + * - Enable these two interrupts + */ +void rt_hw_ticksetup(void) +{ + uint64_t ticks = SYSTICK_TICK_CONST; + + /* Make SWI and SysTick the lowest priority interrupts. */ + /* Stop and clear the SysTimer. SysTimer as Non-Vector Interrupt */ + SysTick_Config(ticks); + ECLIC_DisableIRQ(SysTimer_IRQn); + ECLIC_SetLevelIRQ(SysTimer_IRQn, RT_KERNEL_INTERRUPT_LEVEL); + ECLIC_SetShvIRQ(SysTimer_IRQn, ECLIC_NON_VECTOR_INTERRUPT); + ECLIC_EnableIRQ(SysTimer_IRQn); + + /* Set SWI interrupt level to lowest level/priority, SysTimerSW as Vector Interrupt */ + ECLIC_SetShvIRQ(SysTimerSW_IRQn, ECLIC_VECTOR_INTERRUPT); + ECLIC_SetLevelIRQ(SysTimerSW_IRQn, RT_KERNEL_INTERRUPT_LEVEL); + ECLIC_EnableIRQ(SysTimerSW_IRQn); +} + +/** + * systimer interrupt handler eclic_mtip_handler + * is hard coded in startup_<Device>.S + * We define SysTick_Handler as eclic_mtip_handler + * for easy understanding + */ +#define SysTick_Handler eclic_mtip_handler + +/** + * @brief This is the timer interrupt service routine. + * + */ +void SysTick_Handler(void) +{ + /* Reload systimer */ + SysTick_Reload(SYSTICK_TICK_CONST); + + /* enter interrupt */ + rt_interrupt_enter(); + + /* tick increase */ + rt_tick_increase(); + + /* leave interrupt */ + rt_interrupt_leave(); +} + +/** + * @brief Disable cpu interrupt + * + * @details + * + * - Disable cpu interrupt by clear MIE bit in MSTATUS + * - Return the previous value in MSTATUS before clear MIE bit + * + * @return the previous value in MSTATUS before clear MIE bit + */ +rt_base_t rt_hw_interrupt_disable(void) +{ + return __RV_CSR_READ_CLEAR(CSR_MSTATUS, MSTATUS_MIE); +} + +/** + * @brief Restore previous saved interrupt status + * + * @param level previous saved MSTATUS value + */ +void rt_hw_interrupt_enable(rt_base_t level) +{ + __RV_CSR_WRITE(CSR_MSTATUS, level); +} diff --git a/libcpu/risc-v/nuclei/cpuport.h b/libcpu/risc-v/nuclei/cpuport.h new file mode 100644 index 0000000000..3736f0078a --- /dev/null +++ b/libcpu/risc-v/nuclei/cpuport.h @@ -0,0 +1,40 @@ +/* + * Copyright (c) 2006-2018, RT-Thread Development Team + * Copyright (c) 2019-Present Nuclei Limited. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Change Logs: + * Date Author Notes + * 2020/03/26 hqfang Nuclei RISC-V Core porting code. + */ + +#ifndef __CPUPORT_H__ +#define __CPUPORT_H__ + +#include <rtconfig.h> +#include <nuclei_sdk_soc.h> + +#ifdef __cplusplus +extern "C" { +#endif + +/* Scheduler utilities. */ +#define RT_YIELD() \ +{ \ + /* Set a software interrupt(SWI) request to request a context switch. */ \ + SysTimer_SetSWIRQ(); \ + /* Barriers are normally not required but do ensure the code is completely \ + within the specified behaviour for the architecture. */ \ + __RWMB(); \ + __FENCE_I(); \ +} + +extern void rt_hw_ticksetup(void); +extern void rt_hw_taskswitch(void); + +#ifdef __cplusplus +} +#endif + +#endif diff --git a/libcpu/risc-v/nuclei/interrupt_gcc.S b/libcpu/risc-v/nuclei/interrupt_gcc.S new file mode 100644 index 0000000000..02a3e3e760 --- /dev/null +++ b/libcpu/risc-v/nuclei/interrupt_gcc.S @@ -0,0 +1,218 @@ +/* + * Copyright (c) 2019-Present Nuclei Limited. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Change Logs: + * Date Author Notes + * 2020/03/26 hqfang First Nuclei RISC-V porting implementation + */ + +#include "riscv_encoding.h" + +.section .text.entry +.align 8 + +/** + * \brief Global interrupt disabled + * \details + * This function disable global interrupt. + * \remarks + * - All the interrupt requests will be ignored by CPU. + */ +.macro DISABLE_MIE + csrc CSR_MSTATUS, MSTATUS_MIE +.endm + +/** + * \brief Macro for context save + * \details + * This macro save ABI defined caller saved registers in the stack. + * \remarks + * - This Macro could use to save context when you enter to interrupt + * or exception +*/ +/* Save caller registers */ +.macro SAVE_CONTEXT + csrrw sp, CSR_MSCRATCHCSWL, sp + /* Allocate stack space for context saving */ +#ifndef __riscv_32e + addi sp, sp, -20*REGBYTES +#else + addi sp, sp, -14*REGBYTES +#endif /* __riscv_32e */ + + STORE x1, 0*REGBYTES(sp) + STORE x4, 1*REGBYTES(sp) + STORE x5, 2*REGBYTES(sp) + STORE x6, 3*REGBYTES(sp) + STORE x7, 4*REGBYTES(sp) + STORE x10, 5*REGBYTES(sp) + STORE x11, 6*REGBYTES(sp) + STORE x12, 7*REGBYTES(sp) + STORE x13, 8*REGBYTES(sp) + STORE x14, 9*REGBYTES(sp) + STORE x15, 10*REGBYTES(sp) +#ifndef __riscv_32e + STORE x16, 14*REGBYTES(sp) + STORE x17, 15*REGBYTES(sp) + STORE x28, 16*REGBYTES(sp) + STORE x29, 17*REGBYTES(sp) + STORE x30, 18*REGBYTES(sp) + STORE x31, 19*REGBYTES(sp) +#endif /* __riscv_32e */ +.endm + +/** + * \brief Macro for restore caller registers + * \details + * This macro restore ABI defined caller saved registers from stack. + * \remarks + * - You could use this macro to restore context before you want return + * from interrupt or exeception + */ +/* Restore caller registers */ +.macro RESTORE_CONTEXT + LOAD x1, 0*REGBYTES(sp) + LOAD x4, 1*REGBYTES(sp) + LOAD x5, 2*REGBYTES(sp) + LOAD x6, 3*REGBYTES(sp) + LOAD x7, 4*REGBYTES(sp) + LOAD x10, 5*REGBYTES(sp) + LOAD x11, 6*REGBYTES(sp) + LOAD x12, 7*REGBYTES(sp) + LOAD x13, 8*REGBYTES(sp) + LOAD x14, 9*REGBYTES(sp) + LOAD x15, 10*REGBYTES(sp) +#ifndef __riscv_32e + LOAD x16, 14*REGBYTES(sp) + LOAD x17, 15*REGBYTES(sp) + LOAD x28, 16*REGBYTES(sp) + LOAD x29, 17*REGBYTES(sp) + LOAD x30, 18*REGBYTES(sp) + LOAD x31, 19*REGBYTES(sp) + + /* De-allocate the stack space */ + addi sp, sp, 20*REGBYTES +#else + /* De-allocate the stack space */ + addi sp, sp, 14*REGBYTES +#endif /* __riscv_32e */ + csrrw sp, CSR_MSCRATCHCSWL, sp +.endm + +/** + * \brief Macro for save necessary CSRs to stack + * \details + * This macro store MCAUSE, MEPC, MSUBM to stack. + */ +.macro SAVE_CSR_CONTEXT + /* Store CSR mcause to stack using pushmcause */ + csrrwi x0, CSR_PUSHMCAUSE, 11 + /* Store CSR mepc to stack using pushmepc */ + csrrwi x0, CSR_PUSHMEPC, 12 + /* Store CSR msub to stack using pushmsub */ + csrrwi x0, CSR_PUSHMSUBM, 13 +.endm + +/** + * \brief Macro for restore necessary CSRs from stack + * \details + * This macro restore MSUBM, MEPC, MCAUSE from stack. + */ +.macro RESTORE_CSR_CONTEXT + LOAD x5, 13*REGBYTES(sp) + csrw CSR_MSUBM, x5 + LOAD x5, 12*REGBYTES(sp) + csrw CSR_MEPC, x5 + LOAD x5, 11*REGBYTES(sp) + csrw CSR_MCAUSE, x5 +.endm + +/** + * \brief Exception/NMI Entry + * \details + * This function provide common entry functions for exception/nmi. + * \remarks + * This function provide a default exception/nmi entry. + * ABI defined caller save register and some CSR registers + * to be saved before enter interrupt handler and be restored before return. + */ +.section .text.trap +/* In CLIC mode, the exeception entry must be 64bytes aligned */ +.align 6 +.global exc_entry +exc_entry: + /* Save the caller saving registers (context) */ + SAVE_CONTEXT + /* Save the necessary CSR registers */ + SAVE_CSR_CONTEXT + + /* + * Set the exception handler function arguments + * argument 1: mcause value + * argument 2: current stack point(SP) value + */ + csrr a0, mcause + mv a1, sp + /* + * TODO: Call the exception handler function + * By default, the function template is provided in + * system_Device.c, you can adjust it as you want + */ + call core_exception_handler + + /* Restore the necessary CSR registers */ + RESTORE_CSR_CONTEXT + /* Restore the caller saving registers (context) */ + RESTORE_CONTEXT + + /* Return to regular code */ + mret + +/** + * \brief Non-Vector Interrupt Entry + * \details + * This function provide common entry functions for handling + * non-vector interrupts + * \remarks + * This function provide a default non-vector interrupt entry. + * ABI defined caller save register and some CSR registers need + * to be saved before enter interrupt handler and be restored before return. + */ +.section .text.irq +/* In CLIC mode, the interrupt entry must be 4bytes aligned */ +.align 2 +.global irq_entry +/* This label will be set to MTVT2 register */ +irq_entry: + /* Save the caller saving registers (context) */ + SAVE_CONTEXT + /* Save the necessary CSR registers */ + SAVE_CSR_CONTEXT + + /* This special CSR read/write operation, which is actually + * claim the CLIC to find its pending highest ID, if the ID + * is not 0, then automatically enable the mstatus.MIE, and + * jump to its vector-entry-label, and update the link register + */ + csrrw ra, CSR_JALMNXTI, ra + + /* Critical section with interrupts disabled */ + DISABLE_MIE + + /* Restore the necessary CSR registers */ + RESTORE_CSR_CONTEXT + /* Restore the caller saving registers (context) */ + RESTORE_CONTEXT + + /* Return to regular code */ + mret + +/* Default Handler for Exceptions / Interrupts */ +.global default_intexc_handler +Undef_Handler: +default_intexc_handler: +1: + j 1b + diff --git a/tools/mkdist.py b/tools/mkdist.py index 7e4b9a8bbe..ec527d87e1 100644 --- a/tools/mkdist.py +++ b/tools/mkdist.py @@ -345,6 +345,13 @@ def MkDist(program, BSP_ROOT, RTT_ROOT, Env, rttide = None): bsp_copy_files(os.path.join(library_path, Env['bsp_lib_type']), os.path.join(library_dir, Env['bsp_lib_type'])) shutil.copyfile(os.path.join(library_path, 'Kconfig'), os.path.join(library_dir, 'Kconfig')) + # copy nuclei bsp libiary files + if os.path.basename(os.path.dirname(BSP_ROOT)) == 'nuclei': + print("=> copy nuclei bsp library") + library_path = os.path.join(os.path.dirname(BSP_ROOT), 'libraries') + library_dir = os.path.join(dist_dir, 'libraries') + bsp_copy_files(os.path.join(library_path, Env['bsp_lib_type']), os.path.join(library_dir, Env['bsp_lib_type'])) + # do bsp special dist handle if 'dist_handle' in Env: print("=> start dist handle") |