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-rw-r--r--bsp/hpmicro/libraries/hpm_sdk/arch/riscv/riscv_core.h12
1 files changed, 12 insertions, 0 deletions
diff --git a/bsp/hpmicro/libraries/hpm_sdk/arch/riscv/riscv_core.h b/bsp/hpmicro/libraries/hpm_sdk/arch/riscv/riscv_core.h
index 4f95f4db9e..8cdaf95094 100644
--- a/bsp/hpmicro/libraries/hpm_sdk/arch/riscv/riscv_core.h
+++ b/bsp/hpmicro/libraries/hpm_sdk/arch/riscv/riscv_core.h
@@ -88,6 +88,18 @@ extern "C" {
#define fencei() __asm volatile("fence.i")
/**
+ * @brief execute fence rw
+ *
+ */
+#define fencerw() __asm volatile("fence rw, rw")
+
+/**
+ * @brief execute fence iorw
+ *
+ */
+#define fenceiorw() __asm volatile("fence iorw, iorw")
+
+/**
* @brief enable fpu
*/
#define enable_fpu() read_set_csr(CSR_MSTATUS, CSR_MSTATUS_FS_MASK)