diff options
87 files changed, 192 insertions, 41843 deletions
diff --git a/bsp/gd32/gd32103c-eval/board/Kconfig b/bsp/gd32/gd32103c-eval/board/Kconfig index 01d1240fce..354d212994 100644 --- a/bsp/gd32/gd32103c-eval/board/Kconfig +++ b/bsp/gd32/gd32103c-eval/board/Kconfig @@ -74,12 +74,66 @@ menu "On-chip Peripheral Drivers" range 1 216 default 25 endif + + config BSP_USING_WDT + bool "Enable Watchdog Timer" + select RT_USING_WDT + default n + + config BSP_USING_RTC + bool "Enable Internal RTC" + select RT_USING_RTC + default n + + menuconfig BSP_USING_HWTIMER + bool "Enable hwtimer" + default n + select RT_USING_HWTIMER + if BSP_USING_HWTIMER + config BSP_USING_HWTIMER0 + bool "using hwtimer0" + default n + config BSP_USING_HWTIMER1 + bool "using hwtimer1" + default n + config BSP_USING_HWTIMER2 + bool "using hwtimer2" + default n + config BSP_USING_HWTIMER3 + bool "using hwtimer3" + default n + config BSP_USING_HWTIMER4 + bool "using hwtimer4" + default n + config BSP_USING_HWTIMER5 + bool "using hwtimer5" + default n + config BSP_USING_HWTIMER6 + bool "using hwtimer6" + default n + config BSP_USING_HWTIMER7 + bool "using hwtimer7" + default n + endif + + menuconfig BSP_USING_ADC + bool "Enable ADC" + default n + select RT_USING_ADC + if BSP_USING_ADC + config BSP_USING_ADC0 + bool "using adc0" + default n + config BSP_USING_ADC1 + bool "using adc1" + default n + endif source "../libraries/gd32_drivers/Kconfig" - + endmenu menu "Board extended module Drivers" endmenu - + endmenu diff --git a/bsp/gd32/libraries/GD32F10x_Firmware_Library/SConscript b/bsp/gd32/libraries/GD32F10x_Firmware_Library/SConscript index f5004445c0..889e33dd2a 100644 --- a/bsp/gd32/libraries/GD32F10x_Firmware_Library/SConscript +++ b/bsp/gd32/libraries/GD32F10x_Firmware_Library/SConscript @@ -40,6 +40,7 @@ if GetDepend(['RT_USING_HWTIMER']): if GetDepend(['RT_USING_RTC']): src += ['GD32F10x_standard_peripheral/Source/gd32f10x_rtc.c'] + src += ['GD32F10x_standard_peripheral/Source/gd32f10x_pmu.c'] if GetDepend(['RT_USING_WDT']): src += ['GD32F10x_standard_peripheral/Source/gd32f10x_wwdgt.c'] diff --git a/bsp/gd32/libraries/gd32_drivers/SConscript b/bsp/gd32/libraries/gd32_drivers/SConscript index b33b2c5768..16a76e2b0b 100644 --- a/bsp/gd32/libraries/gd32_drivers/SConscript +++ b/bsp/gd32/libraries/gd32_drivers/SConscript @@ -27,9 +27,21 @@ if GetDepend('RT_USING_SPI'): # add spi flash drivers. if GetDepend('RT_USING_SFUD'): - src += ['drv_spi_flash.c', 'drv_spi.c'] + src += ['drv_spi_flash.c', 'drv_spi.c'] -path = [cwd] +if GetDepend('RT_USING_WDT'): + src += ['drv_wdt.c'] + +if GetDepend('RT_USING_RTC'): + src += ['drv_rtc.c'] + +if GetDepend('RT_USING_HWTIMER'): + src += ['drv_hwtimer.c'] + +if GetDepend('RT_USING_ADC'): + src += ['drv_adc.c'] + +path = [cwd] group = DefineGroup('Drivers', src, depend = [''], CPPPATH = path) diff --git a/bsp/gd32103c-eval/drivers/drv_adc.c b/bsp/gd32/libraries/gd32_drivers/drv_adc.c index 65e781e40c..bd3b2d6b63 100644 --- a/bsp/gd32103c-eval/drivers/drv_adc.c +++ b/bsp/gd32/libraries/gd32_drivers/drv_adc.c @@ -1,15 +1,14 @@ /* - * Copyright (c) 2006-2021, RT-Thread Development Team + * Copyright (c) 2006-2022, RT-Thread Development Team * * SPDX-License-Identifier: Apache-2.0 * * Change Logs: * Date Author Notes - * 2021-01-03 iysheng first version + * 2021-02-25 iysheng first version */ #include <board.h> -#include <drivers/drv_comm.h> #include <drivers/adc.h> #define DBG_TAG "drv.adc" @@ -39,7 +38,7 @@ static gd32_adc_device g_gd32_devs[] = { GET_PIN(B, 0), GET_PIN(B, 1), GET_PIN(C, 0), GET_PIN(C, 1), GET_PIN(C, 2), GET_PIN(C, 3), GET_PIN(C, 4), GET_PIN(C, 5), }, - ADC0, + (void *)ADC0, }, #endif @@ -53,7 +52,7 @@ static gd32_adc_device g_gd32_devs[] = { GET_PIN(B, 0), GET_PIN(B, 1), GET_PIN(C, 0), GET_PIN(C, 1), GET_PIN(C, 2), GET_PIN(C, 3), GET_PIN(C, 4), GET_PIN(C, 5), }, - ADC1, + (void *)ADC1, }, #endif }; @@ -61,53 +60,41 @@ static gd32_adc_device g_gd32_devs[] = { /* * static void init_pin4adc * - * 初始化指定的管腳爲 analog 模式 * @ rt_uint32_t pin: pin information * return: N/A */ static void init_pin4adc(rt_base_t pin) { - GPIO_InitPara GPIO_InitStruct = {0}; - - GPIO_InitStruct.GPIO_Pin = PIN_GDPIN(pin); - GPIO_InitStruct.GPIO_Speed = GPIO_SPEED_50MHZ; - GPIO_InitStruct.GPIO_Mode = GPIO_MODE_AIN; - GPIO_Init(PIN_GDPORT(pin), &GPIO_InitStruct); + gpio_init(PIN_GDPORT(pin), GPIO_MODE_AIN, GPIO_OSPEED_50MHZ, PIN_GDPIN(pin)); } static rt_err_t gd32_adc_enabled(struct rt_adc_device *device, rt_uint32_t channel, rt_bool_t enabled) { - ADC_TypeDef *ADCx; - ADC_InitPara ADC_InitParaStruct = {0}; + uint32_t adc_periph; gd32_adc_device * gd32_adc = (gd32_adc_device *)device; if (channel >= MAX_EXTERN_ADC_CHANNEL) { LOG_E("invalid channel"); - return -E2BIG; + return -RT_EINVAL; } - ADCx = (ADC_TypeDef *)(device->parent.user_data); + adc_periph = (uint32_t )(device->parent.user_data); if (enabled == ENABLE) { init_pin4adc(gd32_adc->adc_pins[channel]); - ADC_InitParaStruct.ADC_Trig_External = ADC_EXTERNAL_TRIGGER_MODE_NONE; - /* Fix the channel number to fit the firmware library */ - ADC_InitParaStruct.ADC_Channel_Number = 1 + channel; - ADC_InitParaStruct.ADC_Data_Align = ADC_DATAALIGN_RIGHT; - ADC_InitParaStruct.ADC_Mode_Scan = DISABLE; - ADC_InitParaStruct.ADC_Mode = ADC_MODE_INDEPENDENT; - ADC_InitParaStruct.ADC_Mode_Continuous = ENABLE; - ADC_Init(ADCx, &ADC_InitParaStruct); - - ADC_RegularChannel_Config(ADCx, channel, 1, ADC_SAMPLETIME_13POINT5); - ADC_Enable(ADCx, ENABLE); - ADC_SoftwareStartConv_Enable(ADCx, ENABLE); + adc_deinit(adc_periph); + adc_channel_length_config(adc_periph, ADC_REGULAR_CHANNEL, 1); + adc_data_alignment_config(adc_periph, ADC_DATAALIGN_RIGHT); + adc_external_trigger_source_config(adc_periph, ADC_REGULAR_CHANNEL, ADC0_1_2_EXTTRIG_INSERTED_NONE); + adc_external_trigger_config(adc_periph, ADC_REGULAR_CHANNEL, ENABLE); + adc_regular_channel_config(adc_periph, 0, channel, ADC_SAMPLETIME_13POINT5); + adc_enable(adc_periph); } else { - ADC_Enable(ADCx, DISABLE); + adc_disable(adc_periph); } return 0; @@ -115,16 +102,17 @@ static rt_err_t gd32_adc_enabled(struct rt_adc_device *device, rt_uint32_t chann static rt_err_t gd32_adc_convert(struct rt_adc_device *device, rt_uint32_t channel, rt_uint32_t *value) { - ADC_TypeDef *ADCx; + uint32_t adc_periph; if (!value) { LOG_E("invalid param"); - return -EINVAL; + return -RT_EINVAL; } - ADCx = (ADC_TypeDef *)(device->parent.user_data); - *value = ADC_GetConversionValue(ADCx); + adc_periph = (uint32_t )(device->parent.user_data); + adc_software_trigger_enable(adc_periph, ADC_REGULAR_CHANNEL); + *value = adc_regular_data_read(adc_periph); return 0; } @@ -148,11 +136,11 @@ static int rt_hw_adc_init(void) rcu_periph_clock_enable(RCU_ADC1); #endif - for (; i < ARRAY_SIZE(g_gd32_devs); i++) + for (; i < sizeof(g_gd32_devs) / sizeof(g_gd32_devs[0]); i++) { ret = rt_hw_adc_register(&g_gd32_devs[i].adc_dev, \ (const char *)g_gd32_devs[i].name, \ - &g_gd32_adc_ops, g_gd32_devs[i].private_data); + &g_gd32_adc_ops, (void *)g_gd32_devs[i].private_data); if (ret != RT_EOK) { /* TODO err handler */ diff --git a/bsp/gd32/libraries/gd32_drivers/drv_gpio.h b/bsp/gd32/libraries/gd32_drivers/drv_gpio.h index 9300191198..5258a4f5ac 100644 --- a/bsp/gd32/libraries/gd32_drivers/drv_gpio.h +++ b/bsp/gd32/libraries/gd32_drivers/drv_gpio.h @@ -38,7 +38,7 @@ extern "C" { EXTI_SOURCE_PIN##pin} #else #define GD32_PIN(index, port, pin) {index, RCU_GPIO##port, \ - GPIO##port, GPIO_PIN_##pin, \ + GPIO##port, GPIO_PIN_##pin, \ GPIO_PORT_SOURCE_GPIO##port, \ GPIO_PIN_SOURCE_##pin} @@ -48,6 +48,12 @@ extern "C" { #define GET_PIN(PORTx,PIN) (rt_base_t)((16 * ( ((rt_base_t)__GD32_PORT(PORTx) - (rt_base_t)GPIO_BASE)/(0x0400UL) )) + PIN) +#define PIN_PORT(pin) ((uint8_t)(((pin) >> 4) & 0xFu)) +#define PIN_NO(pin) ((uint8_t)((pin) & 0xFu)) + +#define PIN_GDPORT(pin) (GPIO_BASE + (0x400u * PIN_PORT(pin))) +#define PIN_GDPIN(pin) ((uint16_t)(1u << PIN_NO(pin))) + struct pin_index { rt_int16_t index; diff --git a/bsp/gd32103c-eval/drivers/drv_hwtimer.c b/bsp/gd32/libraries/gd32_drivers/drv_hwtimer.c index 8b5f5010e6..1c22b10467 100644 --- a/bsp/gd32103c-eval/drivers/drv_hwtimer.c +++ b/bsp/gd32/libraries/gd32_drivers/drv_hwtimer.c @@ -1,19 +1,32 @@ /* - * Copyright (c) 2006-2021, RT-Thread Development Team + * Copyright (c) 2006-2022, RT-Thread Development Team * * SPDX-License-Identifier: Apache-2.0 * * Change Logs: * Date Author Notes - * 2021-01-28 iysheng first version + * 2021-02-25 iysheng first version */ #include <board.h> -#include <drivers/drv_comm.h> -#include <drivers/drv_hwtimer.h> +#include <rtdevice.h> +#include <drivers/hwtimer.h> #ifdef BSP_USING_HWTIMER +typedef struct { + uint32_t reg_base; + IRQn_Type irqn; + rcu_periph_enum rcu; +} gd32_hwtimer_data; + +typedef struct { + char dev_name[RT_NAME_MAX]; + const gd32_hwtimer_data hw_data; + rt_hwtimer_t hwtimer_dev; + const struct rt_hwtimer_info hwtimer_info; +} gd32_hwtimer_device; + enum timer_index_E { #ifdef BSP_USING_HWTIMER0 TIM0_INDEX, @@ -67,49 +80,48 @@ enum timer_index_E { * @param freq of the timer clock * @retval None */ -static void __set_timerx_freq(TIMER_TypeDef *timerx, uint32_t freq) +static void __set_timerx_freq(uint32_t timerx, uint32_t freq) { - RCC_ClocksPara RCC_Clocks = {0}; + uint32_t ap1freq, ap2freq; uint16_t prescaler; uint32_t temp; - RCC_GetClocksFreq(&RCC_Clocks); if (timerx == TIMER0 || timerx == TIMER7 || timerx == TIMER8 \ || timerx == TIMER9 || timerx == TIMER10) { - temp = RCC->GCFGR & RCC_GCFGR_APB2PS; + ap2freq = rcu_clock_freq_get(CK_APB2); + temp = RCU_CFG0 & RCU_CFG0_APB2PSC; temp >>= 11; /* whether should frequency doubling */ temp = (temp < 4) ? 0 : 1; - prescaler = (RCC_Clocks.APB2_Frequency << temp) / freq - 1; + prescaler = (ap2freq << temp) / freq - 1; } else { - temp = RCC->GCFGR & RCC_GCFGR_APB1PS; + ap1freq = rcu_clock_freq_get(CK_APB1); + temp = RCU_CFG0 & RCU_CFG0_APB1PSC; temp >>= 8; /* whether should frequency doubling */ temp = (temp < 4) ? 0 : 1; - prescaler = (RCC_Clocks.APB1_Frequency << temp) / freq - 1; + prescaler = (ap1freq << temp) / freq - 1; } - TIMER_PrescalerConfig(timerx, prescaler, TIMER_PSC_RELOAD_NOW); + timer_prescaler_config(timerx, prescaler, TIMER_PSC_RELOAD_NOW); } static void gd32_hwtimer_init(struct rt_hwtimer_device *timer, rt_uint32_t state) { - TIMER_TypeDef * timer_base = timer->parent.user_data; - TIMER_BaseInitPara TIMER_Init; - - RT_ASSERT(timer_base); + uint32_t timer_base = (uint32_t)timer->parent.user_data; + timer_parameter_struct initpara; if (state) { - TIMER_InternalClockConfig(timer_base); - TIMER_BaseStructInit(&TIMER_Init); - TIMER_Init.TIMER_Period = timer->info->maxcnt; - TIMER_BaseInit(timer_base, &TIMER_Init); + timer_internal_clock_config(timer_base); + timer_struct_para_init(&initpara); + initpara.period = timer->info->maxcnt; + timer_init(timer_base, &initpara); __set_timerx_freq(timer_base, timer->info->maxfreq); } } @@ -117,37 +129,37 @@ static void gd32_hwtimer_init(struct rt_hwtimer_device *timer, rt_uint32_t state static rt_err_t gd32_hwtimer_start(struct rt_hwtimer_device *timer, \ rt_uint32_t cnt, rt_hwtimer_mode_t mode) { - TIMER_TypeDef * timer_base = timer->parent.user_data; + uint32_t timer_base = (uint32_t)timer->parent.user_data; if (mode == HWTIMER_MODE_ONESHOT) { - TIMER_SinglePulseMode(timer_base, TIMER_SP_MODE_SINGLE); + timer_single_pulse_mode_config(timer_base, TIMER_SP_MODE_SINGLE); } else if (mode == HWTIMER_MODE_PERIOD) { - TIMER_SinglePulseMode(timer_base, TIMER_SP_MODE_REPETITIVE); + timer_single_pulse_mode_config(timer_base, TIMER_SP_MODE_REPETITIVE); } - TIMER_SetCounter(timer_base, 0); - TIMER_SetAutoreload(timer_base, cnt - 1); - TIMER_Enable(timer_base, ENABLE); + timer_counter_value_config(timer_base, 0); + timer_autoreload_value_config(timer_base, cnt - 1); + timer_enable(timer_base); return 0; } static void gd32_hwtimer_stop(struct rt_hwtimer_device *timer) { - TIMER_TypeDef * timer_base = timer->parent.user_data; + uint32_t timer_base = (uint32_t)timer->parent.user_data; - TIMER_Enable(timer_base, DISABLE); + timer_disable(timer_base); } static rt_uint32_t gd32_hwtimer_count_get(struct rt_hwtimer_device *timer) { - TIMER_TypeDef * timer_base = timer->parent.user_data; + uint32_t timer_base = (uint32_t)timer->parent.user_data; rt_uint32_t count; - count = TIMER_GetCounter(timer_base); + count = timer_counter_read(timer_base); return count; } @@ -163,11 +175,11 @@ static rt_err_t gd32_hwtimer_control(struct rt_hwtimer_device *timer, rt_uint32_ { case HWTIMER_CTRL_FREQ_SET: freq = *(rt_uint32_t *)args; - __set_timerx_freq(timer->parent.user_data, freq); + __set_timerx_freq((uint32_t)timer->parent.user_data, freq); break; default: rt_kprintf("invalid cmd:%x\n", cmd); - ret = -EINVAL; + ret = -RT_EINVAL; break; } @@ -428,8 +440,8 @@ void TIMER0_UP_IRQHandler(void) { rt_interrupt_enter(); rt_device_hwtimer_isr(&g_gd32_hwtimer[TIM0_INDEX].hwtimer_dev); - TIMER_ClearIntBitState(g_gd32_hwtimer[TIM0_INDEX].hwtimer_dev.parent.user_data, \ - TIMER_INT_UPDATE); + timer_flag_clear((uint32_t)g_gd32_hwtimer[TIM0_INDEX].hwtimer_dev.parent.user_data, \ + TIMER_INT_UP); rt_interrupt_leave(); } #endif @@ -439,8 +451,8 @@ void TIMER1_IRQHandler(void) { rt_interrupt_enter(); rt_device_hwtimer_isr(&g_gd32_hwtimer[TIM1_INDEX].hwtimer_dev); - TIMER_ClearIntBitState(g_gd32_hwtimer[TIM1_INDEX].hwtimer_dev.parent.user_data, \ - TIMER_INT_UPDATE); + timer_flag_clear((uint32_t)g_gd32_hwtimer[TIM1_INDEX].hwtimer_dev.parent.user_data, \ + TIMER_INT_UP); rt_interrupt_leave(); } #endif @@ -450,8 +462,8 @@ void TIMER2_IRQHandler(void) { rt_interrupt_enter(); rt_device_hwtimer_isr(&g_gd32_hwtimer[TIM2_INDEX].hwtimer_dev); - TIMER_ClearIntBitState(g_gd32_hwtimer[TIM2_INDEX].hwtimer_dev.parent.user_data, \ - TIMER_INT_UPDATE); + timer_flag_clear((uint32_t)g_gd32_hwtimer[TIM2_INDEX].hwtimer_dev.parent.user_data, \ + TIMER_INT_UP); rt_interrupt_leave(); } #endif @@ -461,8 +473,8 @@ void TIMER3_IRQHandler(void) { rt_interrupt_enter(); rt_device_hwtimer_isr(&g_gd32_hwtimer[TIM3_INDEX].hwtimer_dev); - TIMER_ClearIntBitState(g_gd32_hwtimer[TIM3_INDEX].hwtimer_dev.parent.user_data, \ - TIMER_INT_UPDATE); + timer_flag_clear((uint32_t)g_gd32_hwtimer[TIM3_INDEX].hwtimer_dev.parent.user_data, \ + TIMER_INT_UP); rt_interrupt_leave(); } #endif @@ -472,8 +484,8 @@ void TIMER4_IRQHandler(void) { rt_interrupt_enter(); rt_device_hwtimer_isr(&g_gd32_hwtimer[TIM4_INDEX].hwtimer_dev); - TIMER_ClearIntBitState(g_gd32_hwtimer[TIM4_INDEX].hwtimer_dev.parent.user_data, \ - TIMER_INT_UPDATE); + timer_flag_clear((uint32_t)g_gd32_hwtimer[TIM4_INDEX].hwtimer_dev.parent.user_data, \ + TIMER_INT_UP); rt_interrupt_leave(); } #endif @@ -483,8 +495,8 @@ void TIMER5_IRQHandler(void) { rt_interrupt_enter(); rt_device_hwtimer_isr(&g_gd32_hwtimer[TIM5_INDEX].hwtimer_dev); - TIMER_ClearIntBitState(g_gd32_hwtimer[TIM5_INDEX].hwtimer_dev.parent.user_data, \ - TIMER_INT_UPDATE); + timer_flag_clear((uint32_t)g_gd32_hwtimer[TIM5_INDEX].hwtimer_dev.parent.user_data, \ + TIMER_INT_UP); rt_interrupt_leave(); } #endif @@ -494,8 +506,8 @@ void TIMER6_IRQHandler(void) { rt_interrupt_enter(); rt_device_hwtimer_isr(&g_gd32_hwtimer[TIM6_INDEX].hwtimer_dev); - TIMER_ClearIntBitState(g_gd32_hwtimer[TIM6_INDEX].hwtimer_dev.parent.user_data, \ - TIMER_INT_UPDATE); + timer_flag_clear((uint32_t)g_gd32_hwtimer[TIM6_INDEX].hwtimer_dev.parent.user_data, \ + TIMER_INT_UP); rt_interrupt_leave(); } #endif @@ -505,8 +517,8 @@ void TIMER7_UP_IRQHandler(void) { rt_interrupt_enter(); rt_device_hwtimer_isr(&g_gd32_hwtimer[TIM7_INDEX].hwtimer_dev); - TIMER_ClearIntBitState(g_gd32_hwtimer[TIM7_INDEX].hwtimer_dev.parent.user_data, \ - TIMER_INT_UPDATE); + timer_flag_clear((uint32_t)g_gd32_hwtimer[TIM7_INDEX].hwtimer_dev.parent.user_data, \ + TIMER_INT_UP); rt_interrupt_leave(); } #endif @@ -515,7 +527,7 @@ static int rt_hwtimer_init(void) { int ret = 0, i = 0; - for (; i < ARRAY_SIZE(g_gd32_hwtimer); i++) + for (; i < sizeof(g_gd32_hwtimer) / sizeof(g_gd32_hwtimer[0]); i++) { g_gd32_hwtimer[i].hwtimer_dev.ops = &g_gd32_hwtimer_ops; g_gd32_hwtimer[i].hwtimer_dev.info = &g_gd32_hwtimer[i].hwtimer_info; @@ -523,9 +535,9 @@ static int rt_hwtimer_init(void) rcu_periph_clock_enable(g_gd32_hwtimer[i].hw_data.rcu); NVIC_SetPriority(g_gd32_hwtimer[i].hw_data.irqn, 0); NVIC_EnableIRQ(g_gd32_hwtimer[i].hw_data.irqn); - TIMER_INTConfig(g_gd32_hwtimer[i].hw_data.reg_base, TIMER_INT_UPDATE, ENABLE); + timer_interrupt_enable(g_gd32_hwtimer[i].hw_data.reg_base, TIMER_INT_UP); ret = rt_device_hwtimer_register(&g_gd32_hwtimer[i].hwtimer_dev, \ - g_gd32_hwtimer[i].dev_name, g_gd32_hwtimer[i].hw_data.reg_base); + g_gd32_hwtimer[i].dev_name, (void *)g_gd32_hwtimer[i].hw_data.reg_base); if (RT_EOK != ret) { rt_kprintf("failed register %s, err=%d\n", g_gd32_hwtimer[i].dev_name, \ diff --git a/bsp/gd32103c-eval/drivers/drv_rtc.c b/bsp/gd32/libraries/gd32_drivers/drv_rtc.c index 95c6e56e9d..4ed2a31f38 100644 --- a/bsp/gd32103c-eval/drivers/drv_rtc.c +++ b/bsp/gd32/libraries/gd32_drivers/drv_rtc.c @@ -1,16 +1,15 @@ /* - * Copyright (c) 2006-2021, RT-Thread Development Team + * Copyright (c) 2006-2022, RT-Thread Development Team * * SPDX-License-Identifier: Apache-2.0 * * Change Logs: * Date Author Notes - * 2021-02-20 iysheng first version + * 2022-01-25 iysheng first version */ #include <board.h> #include <sys/time.h> -#include <drivers/drv_comm.h> #define DBG_TAG "drv.rtc" #define DBG_LVL DBG_INFO @@ -29,7 +28,7 @@ static time_t get_rtc_timestamp(void) { time_t rtc_counter; - rtc_counter = (time_t)RTC_GetCounter(); + rtc_counter = (time_t)rtc_counter_get(); return rtc_counter; } @@ -41,15 +40,15 @@ static rt_err_t set_rtc_timestamp(time_t time_stamp) rtc_counter = (uint32_t)time_stamp; /* wait until LWOFF bit in RTC_CTL to 1 */ - RTC_WaitLWOFF(); + rtc_lwoff_wait(); /* enter configure mode */ - RTC_EnterConfigMode(); + rtc_configuration_mode_enter(); /* write data to rtc register */ - RTC_SetCounter(rtc_counter); + rtc_counter_set(rtc_counter); /* exit configure mode */ - RTC_ExitConfigMode(); + rtc_configuration_mode_exit(); /* wait until LWOFF bit in RTC_CTL to 1 */ - RTC_WaitLWOFF(); + rtc_lwoff_wait(); return RT_EOK; } @@ -94,7 +93,7 @@ static int rt_hw_rtc_init(void) time_t rtc_counter; rcu_periph_clock_enable(RCU_PMU); - PWR_BackupAccess_Enable(ENABLE); + pmu_backup_write_enable(); rcu_periph_clock_enable(RCU_BKPI); rtc_counter = get_rtc_timestamp(); diff --git a/bsp/gd32103c-eval/drivers/drv_iwdt.c b/bsp/gd32/libraries/gd32_drivers/drv_wdt.c index f218f46104..8ef5096caf 100644 --- a/bsp/gd32103c-eval/drivers/drv_iwdt.c +++ b/bsp/gd32/libraries/gd32_drivers/drv_wdt.c @@ -1,11 +1,11 @@ /* - * Copyright (c) 2006-2021, RT-Thread Development Team + * Copyright (c) 2006-2022, RT-Thread Development Team * * SPDX-License-Identifier: Apache-2.0 * * Change Logs: * Date Author Notes - * 2021-03-03 iysheng first version + * 2022-01-25 iysheng first version */ #include <board.h> @@ -25,13 +25,13 @@ typedef struct { static gd32_wdt_device_t g_wdt_dev; -static rt_err_t gd32_iwdt_init(rt_watchdog_t *wdt) +static rt_err_t gd32_wdt_init(rt_watchdog_t *wdt) { rcu_osci_on(RCU_IRC40K); if (ERROR == rcu_osci_stab_wait(RCU_IRC40K)) { LOG_E("failed init IRC40K clock for free watchdog."); - return -EINVAL; + return -RT_EINVAL; } g_wdt_dev.min_threshold_s = 1; @@ -39,22 +39,21 @@ static rt_err_t gd32_iwdt_init(rt_watchdog_t *wdt) LOG_I("threshold section [%u, %d]", \ g_wdt_dev.min_threshold_s, g_wdt_dev.max_threshold_s); - IWDG_Write_Enable(IWDG_WRITEACCESS_ENABLE); - IWDG_SetPrescaler(IWDG_PRESCALER_256); - IWDG_SetReloadValue(0xfff); - IWDG_Write_Enable(IWDG_WRITEACCESS_DISABLE); + fwdgt_write_enable(); + fwdgt_config(0xfff, FWDGT_PSC_DIV256); + fwdgt_enable(); return 0; } -static rt_err_t gd32_iwdt_control(rt_watchdog_t *wdt, int cmd, void *arg) +static rt_err_t gd32_wdt_control(rt_watchdog_t *wdt, int cmd, void *arg) { rt_uint32_t param; switch (cmd) { case RT_DEVICE_CTRL_WDT_KEEPALIVE: - IWDG_ReloadCounter(); + fwdgt_counter_reload(); break; case RT_DEVICE_CTRL_WDT_SET_TIMEOUT: param = *(rt_uint32_t *) arg; @@ -62,21 +61,21 @@ static rt_err_t gd32_iwdt_control(rt_watchdog_t *wdt, int cmd, void *arg) (param < g_wdt_dev.min_threshold_s)) { LOG_E("invalid param@%u.", param); - return -E2BIG; + return -RT_EINVAL; } else { g_wdt_dev.current_threshold_s = param; } - IWDG_Write_Enable(IWDG_WRITEACCESS_ENABLE); - IWDG_SetReloadValue(param * 40000 >> 8); - IWDG_Write_Enable(IWDG_WRITEACCESS_DISABLE); + fwdgt_write_enable(); + fwdgt_config(param * 40000 >> 8, FWDGT_PSC_DIV256); + fwdgt_write_disable(); break; case RT_DEVICE_CTRL_WDT_GET_TIMEOUT: *(rt_uint32_t *)arg = g_wdt_dev.current_threshold_s; break; case RT_DEVICE_CTRL_WDT_START: - IWDG_Enable(); + fwdgt_enable(); break; default: LOG_W("This command is not supported."); @@ -87,17 +86,17 @@ static rt_err_t gd32_iwdt_control(rt_watchdog_t *wdt, int cmd, void *arg) } static struct rt_watchdog_ops g_wdt_ops = { - gd32_iwdt_init, - gd32_iwdt_control, + gd32_wdt_init, + gd32_wdt_control, }; -static int rt_hw_iwdt_init(void) +static int rt_hw_wdt_init(void) { rt_err_t ret; g_wdt_dev.wdt.ops = &g_wdt_ops; /* register watchdog device */ - if (rt_hw_watchdog_register(&g_wdt_dev.wdt, "iwdt", \ + if (rt_hw_watchdog_register(&g_wdt_dev.wdt, "wdt", \ RT_DEVICE_FLAG_DEACTIVATE, RT_NULL) != RT_EOK) { LOG_E("wdt device register failed."); @@ -107,5 +106,5 @@ static int rt_hw_iwdt_init(void) return ret; } -INIT_BOARD_EXPORT(rt_hw_iwdt_init); +INIT_PREV_EXPORT(rt_hw_wdt_init); #endif diff --git a/bsp/gd32103c-eval/.config b/bsp/gd32103c-eval/.config deleted file mode 100644 index de1ea1ac0c..0000000000 --- a/bsp/gd32103c-eval/.config +++ /dev/null @@ -1,672 +0,0 @@ -# -# Automatically generated file; DO NOT EDIT. -# RT-Thread Configuration -# - -# -# RT-Thread Kernel -# -CONFIG_RT_NAME_MAX=8 -# CONFIG_RT_USING_BIG_ENDIAN is not set -# CONFIG_RT_USING_ARCH_DATA_TYPE is not set -# CONFIG_RT_USING_SMP is not set -CONFIG_RT_ALIGN_SIZE=4 -# CONFIG_RT_THREAD_PRIORITY_8 is not set -CONFIG_RT_THREAD_PRIORITY_32=y -# CONFIG_RT_THREAD_PRIORITY_256 is not set -CONFIG_RT_THREAD_PRIORITY_MAX=32 -CONFIG_RT_TICK_PER_SECOND=100 -CONFIG_RT_USING_OVERFLOW_CHECK=y -CONFIG_RT_USING_HOOK=y -CONFIG_RT_HOOK_USING_FUNC_PTR=y -CONFIG_RT_USING_IDLE_HOOK=y -CONFIG_RT_IDLE_HOOK_LIST_SIZE=4 -CONFIG_IDLE_THREAD_STACK_SIZE=256 -CONFIG_RT_USING_TIMER_SOFT=y -CONFIG_RT_TIMER_THREAD_PRIO=4 -CONFIG_RT_TIMER_THREAD_STACK_SIZE=512 - -# -# kservice optimization -# -# CONFIG_RT_KSERVICE_USING_STDLIB is not set -# CONFIG_RT_KSERVICE_USING_TINY_SIZE is not set -# CONFIG_RT_USING_TINY_FFS is not set -# CONFIG_RT_PRINTF_LONGLONG is not set -CONFIG_RT_DEBUG=y -# CONFIG_RT_DEBUG_COLOR is not set -# CONFIG_RT_DEBUG_INIT_CONFIG is not set -# CONFIG_RT_DEBUG_THREAD_CONFIG is not set -# CONFIG_RT_DEBUG_SCHEDULER_CONFIG is not set -# CONFIG_RT_DEBUG_IPC_CONFIG is not set -# CONFIG_RT_DEBUG_TIMER_CONFIG is not set -# CONFIG_RT_DEBUG_IRQ_CONFIG is not set -# CONFIG_RT_DEBUG_MEM_CONFIG is not set -# CONFIG_RT_DEBUG_SLAB_CONFIG is not set -# CONFIG_RT_DEBUG_MEMHEAP_CONFIG is not set -# CONFIG_RT_DEBUG_MODULE_CONFIG is not set - -# -# Inter-Thread communication -# -CONFIG_RT_USING_SEMAPHORE=y -CONFIG_RT_USING_MUTEX=y -CONFIG_RT_USING_EVENT=y -CONFIG_RT_USING_MAILBOX=y -CONFIG_RT_USING_MESSAGEQUEUE=y -# CONFIG_RT_USING_SIGNALS is not set - -# -# Memory Management -# -CONFIG_RT_USING_MEMPOOL=y -CONFIG_RT_USING_SMALL_MEM=y -# CONFIG_RT_USING_SLAB is not set -# CONFIG_RT_USING_MEMHEAP is not set -CONFIG_RT_USING_SMALL_MEM_AS_HEAP=y -# CONFIG_RT_USING_MEMHEAP_AS_HEAP is not set -# CONFIG_RT_USING_SLAB_AS_HEAP is not set -# CONFIG_RT_USING_USERHEAP is not set -# CONFIG_RT_USING_NOHEAP is not set -# CONFIG_RT_USING_MEMTRACE is not set -# CONFIG_RT_USING_HEAP_ISR is not set -CONFIG_RT_USING_HEAP=y - -# -# Kernel Device Object -# -CONFIG_RT_USING_DEVICE=y -# CONFIG_RT_USING_DEVICE_OPS is not set -# CONFIG_RT_USING_INTERRUPT_INFO is not set -CONFIG_RT_USING_CONSOLE=y -CONFIG_RT_CONSOLEBUF_SIZE=128 -CONFIG_RT_CONSOLE_DEVICE_NAME="uart0" -CONFIG_RT_VER_NUM=0x40100 -# CONFIG_RT_USING_CPU_FFS is not set -# CONFIG_ARCH_CPU_STACK_GROWS_UPWARD is not set - -# -# RT-Thread Components -# -CONFIG_RT_USING_COMPONENTS_INIT=y -CONFIG_RT_USING_USER_MAIN=y -CONFIG_RT_MAIN_THREAD_STACK_SIZE=2048 -CONFIG_RT_MAIN_THREAD_PRIORITY=10 -# CONFIG_RT_USING_LEGACY is not set - -# -# C++ features -# -# CONFIG_RT_USING_CPLUSPLUS is not set - -# -# Command shell -# -CONFIG_RT_USING_FINSH=y -CONFIG_RT_USING_MSH=y -CONFIG_FINSH_USING_MSH=y -CONFIG_FINSH_THREAD_NAME="tshell" -CONFIG_FINSH_THREAD_PRIORITY=20 -CONFIG_FINSH_THREAD_STACK_SIZE=4096 -CONFIG_FINSH_USING_HISTORY=y -CONFIG_FINSH_HISTORY_LINES=5 -CONFIG_FINSH_USING_SYMTAB=y -CONFIG_FINSH_CMD_SIZE=80 -CONFIG_MSH_USING_BUILT_IN_COMMANDS=y -CONFIG_FINSH_USING_DESCRIPTION=y -# CONFIG_FINSH_ECHO_DISABLE_DEFAULT is not set -# CONFIG_FINSH_USING_AUTH is not set -CONFIG_FINSH_ARG_MAX=10 - -# -# Device virtual file system -# -CONFIG_RT_USING_DFS=y -CONFIG_DFS_USING_POSIX=y -CONFIG_DFS_USING_WORKDIR=y -CONFIG_DFS_FILESYSTEMS_MAX=2 -CONFIG_DFS_FILESYSTEM_TYPES_MAX=2 -CONFIG_DFS_FD_MAX=16 -# CONFIG_RT_USING_DFS_MNTTABLE is not set -# CONFIG_RT_USING_DFS_ELMFAT is not set -CONFIG_RT_USING_DFS_DEVFS=y -# CONFIG_RT_USING_DFS_ROMFS is not set -# CONFIG_RT_USING_DFS_RAMFS is not set - -# -# Device Drivers -# -CONFIG_RT_USING_DEVICE_IPC=y -# CONFIG_RT_USING_SYSTEM_WORKQUEUE is not set -CONFIG_RT_USING_SERIAL=y -CONFIG_RT_USING_SERIAL_V1=y -# CONFIG_RT_USING_SERIAL_V2 is not set -CONFIG_RT_SERIAL_USING_DMA=y -CONFIG_RT_SERIAL_RB_BUFSZ=64 -# CONFIG_RT_USING_CAN is not set -# CONFIG_RT_USING_HWTIMER is not set -# CONFIG_RT_USING_CPUTIME is not set -# CONFIG_RT_USING_I2C is not set -# CONFIG_RT_USING_PHY is not set -CONFIG_RT_USING_PIN=y -# CONFIG_RT_USING_ADC is not set -# CONFIG_RT_USING_DAC is not set -# CONFIG_RT_USING_PWM is not set -# CONFIG_RT_USING_MTD_NOR is not set -# CONFIG_RT_USING_MTD_NAND is not set -# CONFIG_RT_USING_PM is not set -# CONFIG_RT_USING_RTC is not set -# CONFIG_RT_USING_SDIO is not set -# CONFIG_RT_USING_SPI is not set -# CONFIG_RT_USING_WDT is not set -# CONFIG_RT_USING_AUDIO is not set -# CONFIG_RT_USING_SENSOR is not set -# CONFIG_RT_USING_TOUCH is not set -# CONFIG_RT_USING_HWCRYPTO is not set -# CONFIG_RT_USING_PULSE_ENCODER is not set -# CONFIG_RT_USING_INPUT_CAPTURE is not set -# CONFIG_RT_USING_WIFI is not set - -# -# Using USB -# -# CONFIG_RT_USING_USB is not set -# CONFIG_RT_USING_USB_HOST is not set -# CONFIG_RT_USING_USB_DEVICE is not set - -# -# POSIX layer and C standard library -# -# CONFIG_RT_USING_MODULE is not set -CONFIG_RT_LIBC_DEFAULT_TIMEZONE=8 - -# -# POSIX (Portable Operating System Interface) layer -# -# CONFIG_RT_USING_POSIX_FS is not set -# CONFIG_RT_USING_POSIX_DELAY is not set -# CONFIG_RT_USING_POSIX_CLOCK is not set -# CONFIG_RT_USING_PTHREADS is not set - -# -# Interprocess Communication (IPC) -# -# CONFIG_RT_USING_POSIX_PIPE is not set -# CONFIG_RT_USING_POSIX_MESSAGE_QUEUE is not set -# CONFIG_RT_USING_POSIX_MESSAGE_SEMAPHORE is not set - -# -# Socket is in the 'Network' category -# - -# -# Network -# - -# -# Socket abstraction layer -# -# CONFIG_RT_USING_SAL is not set - -# -# Network interface device -# -# CONFIG_RT_USING_NETDEV is not set - -# -# light weight TCP/IP stack -# -# CONFIG_RT_USING_LWIP is not set - -# -# AT commands -# -# CONFIG_RT_USING_AT is not set - -# -# VBUS(Virtual Software BUS) -# -# CONFIG_RT_USING_VBUS is not set - -# -# Utilities -# -# CONFIG_RT_USING_RYM is not set -# CONFIG_RT_USING_ULOG is not set -# CONFIG_RT_USING_UTEST is not set -# CONFIG_RT_USING_VAR_EXPORT is not set -# CONFIG_RT_USING_RT_LINK is not set - -# -# RT-Thread Utestcases -# -# CONFIG_RT_USING_UTESTCASES is not set - -# -# RT-Thread online packages -# - -# -# IoT - internet of things -# -# CONFIG_PKG_USING_LORAWAN_DRIVER is not set -# CONFIG_PKG_USING_PAHOMQTT is not set -# CONFIG_PKG_USING_UMQTT is not set -# CONFIG_PKG_USING_WEBCLIENT is not set -# CONFIG_PKG_USING_WEBNET is not set -# CONFIG_PKG_USING_MONGOOSE is not set -# CONFIG_PKG_USING_MYMQTT is not set -# CONFIG_PKG_USING_KAWAII_MQTT is not set -# CONFIG_PKG_USING_BC28_MQTT is not set -# CONFIG_PKG_USING_WEBTERMINAL is not set -# CONFIG_PKG_USING_CJSON is not set -# CONFIG_PKG_USING_JSMN is not set -# CONFIG_PKG_USING_LIBMODBUS is not set -# CONFIG_PKG_USING_FREEMODBUS is not set -# CONFIG_PKG_USING_LJSON is not set -# CONFIG_PKG_USING_EZXML is not set -# CONFIG_PKG_USING_NANOPB is not set - -# -# Wi-Fi -# - -# -# Marvell WiFi -# -# CONFIG_PKG_USING_WLANMARVELL is not set - -# -# Wiced WiFi -# -# CONFIG_PKG_USING_WLAN_WICED is not set -# CONFIG_PKG_USING_RW007 is not set -# CONFIG_PKG_USING_COAP is not set -# CONFIG_PKG_USING_NOPOLL is not set -# CONFIG_PKG_USING_NETUTILS is not set -# CONFIG_PKG_USING_CMUX is not set -# CONFIG_PKG_USING_PPP_DEVICE is not set -# CONFIG_PKG_USING_AT_DEVICE is not set -# CONFIG_PKG_USING_ATSRV_SOCKET is not set -# CONFIG_PKG_USING_WIZNET is not set -# CONFIG_PKG_USING_ZB_COORDINATOR is not set - -# -# IoT Cloud -# -# CONFIG_PKG_USING_ONENET is not set -# CONFIG_PKG_USING_GAGENT_CLOUD is not set -# CONFIG_PKG_USING_ALI_IOTKIT is not set -# CONFIG_PKG_USING_AZURE is not set -# CONFIG_PKG_USING_TENCENT_IOT_EXPLORER is not set -# CONFIG_PKG_USING_JIOT-C-SDK is not set -# CONFIG_PKG_USING_UCLOUD_IOT_SDK is not set -# CONFIG_PKG_USING_JOYLINK is not set -# CONFIG_PKG_USING_EZ_IOT_OS is not set -# CONFIG_PKG_USING_NIMBLE is not set -# CONFIG_PKG_USING_OTA_DOWNLOADER is not set -# CONFIG_PKG_USING_IPMSG is not set -# CONFIG_PKG_USING_LSSDP is not set -# CONFIG_PKG_USING_AIRKISS_OPEN is not set -# CONFIG_PKG_USING_LIBRWS is not set -# CONFIG_PKG_USING_TCPSERVER is not set -# CONFIG_PKG_USING_PROTOBUF_C is not set -# CONFIG_PKG_USING_DLT645 is not set -# CONFIG_PKG_USING_QXWZ is not set -# CONFIG_PKG_USING_SMTP_CLIENT is not set -# CONFIG_PKG_USING_ABUP_FOTA is not set -# CONFIG_PKG_USING_LIBCURL2RTT is not set -# CONFIG_PKG_USING_CAPNP is not set -# CONFIG_PKG_USING_RT_CJSON_TOOLS is not set -# CONFIG_PKG_USING_AGILE_TELNET is not set -# CONFIG_PKG_USING_NMEALIB is not set -# CONFIG_PKG_USING_AGILE_JSMN is not set -# CONFIG_PKG_USING_PDULIB is not set -# CONFIG_PKG_USING_BTSTACK is not set -# CONFIG_PKG_USING_LORAWAN_ED_STACK is not set -# CONFIG_PKG_USING_WAYZ_IOTKIT is not set -# CONFIG_PKG_USING_MAVLINK is not set -# CONFIG_PKG_USING_RAPIDJSON is not set -# CONFIG_PKG_USING_BSAL is not set -# CONFIG_PKG_USING_AGILE_MODBUS is not set -# CONFIG_PKG_USING_AGILE_FTP is not set -# CONFIG_PKG_USING_EMBEDDEDPROTO is not set -# CONFIG_PKG_USING_RT_LINK_HW is not set -# CONFIG_PKG_USING_LORA_PKT_FWD is not set -# CONFIG_PKG_USING_LORA_GW_DRIVER_LIB is not set -# CONFIG_PKG_USING_LORA_PKT_SNIFFER is not set -# CONFIG_PKG_USING_HM is not set -# CONFIG_PKG_USING_SMALL_MODBUS is not set -# CONFIG_PKG_USING_NET_SERVER is not set - -# -# security packages -# -# CONFIG_PKG_USING_MBEDTLS is not set -# CONFIG_PKG_USING_LIBSODIUM is not set -# CONFIG_PKG_USING_TINYCRYPT is not set -# CONFIG_PKG_USING_TFM is not set -# CONFIG_PKG_USING_YD_CRYPTO is not set - -# -# language packages -# -# CONFIG_PKG_USING_LUATOS_SOC is not set -# CONFIG_PKG_USING_LUA is not set -# CONFIG_PKG_USING_JERRYSCRIPT is not set -# CONFIG_PKG_USING_MICROPYTHON is not set -# CONFIG_PKG_USING_PIKASCRIPT is not set - -# -# multimedia packages -# - -# -# LVGL: powerful and easy-to-use embedded GUI library -# -# CONFIG_PKG_USING_LVGL is not set -# CONFIG_PKG_USING_LITTLEVGL2RTT is not set -# CONFIG_PKG_USING_LV_MUSIC_DEMO is not set - -# -# u8g2: a monochrome graphic library -# -# CONFIG_PKG_USING_U8G2_OFFICIAL is not set -# CONFIG_PKG_USING_U8G2 is not set -# CONFIG_PKG_USING_OPENMV is not set -# CONFIG_PKG_USING_MUPDF is not set -# CONFIG_PKG_USING_STEMWIN is not set -# CONFIG_PKG_USING_WAVPLAYER is not set -# CONFIG_PKG_USING_TJPGD is not set -# CONFIG_PKG_USING_PDFGEN is not set -# CONFIG_PKG_USING_HELIX is not set -# CONFIG_PKG_USING_AZUREGUIX is not set -# CONFIG_PKG_USING_TOUCHGFX2RTT is not set -# CONFIG_PKG_USING_NUEMWIN is not set -# CONFIG_PKG_USING_MP3PLAYER is not set -# CONFIG_PKG_USING_TINYJPEG is not set -# CONFIG_PKG_USING_UGUI is not set - -# -# PainterEngine: A cross-platform graphics application framework written in C language -# -# CONFIG_PKG_USING_PAINTERENGINE is not set -# CONFIG_PKG_USING_PAINTERENGINE_AUX is not set -# CONFIG_PKG_USING_MCURSES is not set -# CONFIG_PKG_USING_TERMBOX is not set -# CONFIG_PKG_USING_VT100 is not set - -# -# tools packages -# -# CONFIG_PKG_USING_CMBACKTRACE is not set -# CONFIG_PKG_USING_EASYFLASH is not set -# CONFIG_PKG_USING_EASYLOGGER is not set -# CONFIG_PKG_USING_SYSTEMVIEW is not set -# CONFIG_PKG_USING_SEGGER_RTT is not set -# CONFIG_PKG_USING_RDB is not set -# CONFIG_PKG_USING_QRCODE is not set -# CONFIG_PKG_USING_ULOG_EASYFLASH is not set -# CONFIG_PKG_USING_ULOG_FILE is not set -# CONFIG_PKG_USING_LOGMGR is not set -# CONFIG_PKG_USING_ADBD is not set -# CONFIG_PKG_USING_COREMARK is not set -# CONFIG_PKG_USING_DHRYSTONE is not set -# CONFIG_PKG_USING_MEMORYPERF is not set -# CONFIG_PKG_USING_NR_MICRO_SHELL is not set -# CONFIG_PKG_USING_CHINESE_FONT_LIBRARY is not set -# CONFIG_PKG_USING_LUNAR_CALENDAR is not set -# CONFIG_PKG_USING_BS8116A is not set -# CONFIG_PKG_USING_GPS_RMC is not set -# CONFIG_PKG_USING_URLENCODE is not set -# CONFIG_PKG_USING_UMCN is not set -# CONFIG_PKG_USING_LWRB2RTT is not set -# CONFIG_PKG_USING_CPU_USAGE is not set -# CONFIG_PKG_USING_GBK2UTF8 is not set -# CONFIG_PKG_USING_VCONSOLE is not set -# CONFIG_PKG_USING_KDB is not set -# CONFIG_PKG_USING_WAMR is not set -# CONFIG_PKG_USING_MICRO_XRCE_DDS_CLIENT is not set -# CONFIG_PKG_USING_LWLOG is not set -# CONFIG_PKG_USING_ANV_TRACE is not set -# CONFIG_PKG_USING_ANV_MEMLEAK is not set -# CONFIG_PKG_USING_ANV_TESTSUIT is not set -# CONFIG_PKG_USING_ANV_BENCH is not set -# CONFIG_PKG_USING_DEVMEM is not set -# CONFIG_PKG_USING_REGEX is not set -# CONFIG_PKG_USING_MEM_SANDBOX is not set -# CONFIG_PKG_USING_SOLAR_TERMS is not set -# CONFIG_PKG_USING_GAN_ZHI is not set -# CONFIG_PKG_USING_FDT is not set - -# -# system packages -# - -# -# enhanced kernel services -# -# CONFIG_PKG_USING_RT_MEMCPY_CM is not set -# CONFIG_PKG_USING_RT_KPRINTF_THREADSAFE is not set -# CONFIG_PKG_USING_RT_VSNPRINTF_FULL is not set - -# -# POSIX extension functions -# -# CONFIG_PKG_USING_POSIX_GETLINE is not set -# CONFIG_PKG_USING_POSIX_WCWIDTH is not set -# CONFIG_PKG_USING_POSIX_ITOA is not set - -# -# acceleration: Assembly language or algorithmic acceleration packages -# -# CONFIG_PKG_USING_QFPLIB_M0_FULL is not set -# CONFIG_PKG_USING_QFPLIB_M0_TINY is not set -# CONFIG_PKG_USING_QFPLIB_M3 is not set - -# -# CMSIS: ARM Cortex-M Microcontroller Software Interface Standard -# -# CONFIG_PKG_USING_CMSIS_5 is not set -# CONFIG_PKG_USING_CMSIS_RTOS2 is not set - -# -# Micrium: Micrium software products porting for RT-Thread -# -# CONFIG_PKG_USING_UCOSIII_WRAPPER is not set -# CONFIG_PKG_USING_UCOSII_WRAPPER is not set -# CONFIG_PKG_USING_UC_CRC is not set -# CONFIG_PKG_USING_UC_CLK is not set -# CONFIG_PKG_USING_UC_COMMON is not set -# CONFIG_PKG_USING_UC_MODBUS is not set -# CONFIG_RT_USING_ARDUINO is not set -# CONFIG_PKG_USING_GUIENGINE is not set -# CONFIG_PKG_USING_CAIRO is not set -# CONFIG_PKG_USING_PIXMAN is not set -# CONFIG_PKG_USING_PARTITION is not set -# CONFIG_PKG_USING_FAL is not set -# CONFIG_PKG_USING_FLASHDB is not set -# CONFIG_PKG_USING_SQLITE is not set -# CONFIG_PKG_USING_RTI is not set -# CONFIG_PKG_USING_DFS_YAFFS is not set -# CONFIG_PKG_USING_LITTLEFS is not set -# CONFIG_PKG_USING_DFS_JFFS2 is not set -# CONFIG_PKG_USING_DFS_UFFS is not set -# CONFIG_PKG_USING_LWEXT4 is not set -# CONFIG_PKG_USING_THREAD_POOL is not set -# CONFIG_PKG_USING_ROBOTS is not set -# CONFIG_PKG_USING_EV is not set -# CONFIG_PKG_USING_SYSWATCH is not set -# CONFIG_PKG_USING_SYS_LOAD_MONITOR is not set -# CONFIG_PKG_USING_PLCCORE is not set -# CONFIG_PKG_USING_RAMDISK is not set -# CONFIG_PKG_USING_MININI is not set -# CONFIG_PKG_USING_QBOOT is not set -# CONFIG_PKG_USING_PPOOL is not set -# CONFIG_PKG_USING_OPENAMP is not set -# CONFIG_PKG_USING_LPM is not set -# CONFIG_PKG_USING_TLSF is not set -# CONFIG_PKG_USING_EVENT_RECORDER is not set -# CONFIG_PKG_USING_ARM_2D is not set -# CONFIG_PKG_USING_MCUBOOT is not set -# CONFIG_PKG_USING_TINYUSB is not set -# CONFIG_PKG_USING_USB_STACK is not set - -# -# peripheral libraries and drivers -# -# CONFIG_PKG_USING_SENSORS_DRIVERS is not set -# CONFIG_PKG_USING_REALTEK_AMEBA is not set -# CONFIG_PKG_USING_SHT2X is not set -# CONFIG_PKG_USING_SHT3X is not set -# CONFIG_PKG_USING_AS7341 is not set -# CONFIG_PKG_USING_STM32_SDIO is not set -# CONFIG_PKG_USING_ICM20608 is not set -# CONFIG_PKG_USING_BUTTON is not set -# CONFIG_PKG_USING_PCF8574 is not set -# CONFIG_PKG_USING_SX12XX is not set -# CONFIG_PKG_USING_SIGNAL_LED is not set -# CONFIG_PKG_USING_LEDBLINK is not set -# CONFIG_PKG_USING_LITTLED is not set -# CONFIG_PKG_USING_LKDGUI is not set -# CONFIG_PKG_USING_NRF5X_SDK is not set -# CONFIG_PKG_USING_NRFX is not set -# CONFIG_PKG_USING_WM_LIBRARIES is not set -# CONFIG_PKG_USING_KENDRYTE_SDK is not set -# CONFIG_PKG_USING_INFRARED is not set -# CONFIG_PKG_USING_AGILE_BUTTON is not set -# CONFIG_PKG_USING_AGILE_LED is not set -# CONFIG_PKG_USING_AT24CXX is not set -# CONFIG_PKG_USING_MOTIONDRIVER2RTT is not set -# CONFIG_PKG_USING_AD7746 is not set -# CONFIG_PKG_USING_PCA9685 is not set -# CONFIG_PKG_USING_I2C_TOOLS is not set -# CONFIG_PKG_USING_NRF24L01 is not set -# CONFIG_PKG_USING_TOUCH_DRIVERS is not set -# CONFIG_PKG_USING_MAX17048 is not set -# CONFIG_PKG_USING_RPLIDAR is not set -# CONFIG_PKG_USING_AS608 is not set -# CONFIG_PKG_USING_RC522 is not set -# CONFIG_PKG_USING_WS2812B is not set -# CONFIG_PKG_USING_EMBARC_BSP is not set -# CONFIG_PKG_USING_EXTERN_RTC_DRIVERS is not set -# CONFIG_PKG_USING_MULTI_RTIMER is not set -# CONFIG_PKG_USING_MAX7219 is not set -# CONFIG_PKG_USING_BEEP is not set -# CONFIG_PKG_USING_EASYBLINK is not set -# CONFIG_PKG_USING_PMS_SERIES is not set -# CONFIG_PKG_USING_CAN_YMODEM is not set -# CONFIG_PKG_USING_LORA_RADIO_DRIVER is not set -# CONFIG_PKG_USING_QLED is not set -# CONFIG_PKG_USING_PAJ7620 is not set -# CONFIG_PKG_USING_AGILE_CONSOLE is not set -# CONFIG_PKG_USING_LD3320 is not set -# CONFIG_PKG_USING_WK2124 is not set -# CONFIG_PKG_USING_LY68L6400 is not set -# CONFIG_PKG_USING_DM9051 is not set -# CONFIG_PKG_USING_SSD1306 is not set -# CONFIG_PKG_USING_QKEY is not set -# CONFIG_PKG_USING_RS485 is not set -# CONFIG_PKG_USING_NES is not set -# CONFIG_PKG_USING_VIRTUAL_SENSOR is not set -# CONFIG_PKG_USING_VDEVICE is not set -# CONFIG_PKG_USING_SGM706 is not set -# CONFIG_PKG_USING_STM32WB55_SDK is not set -# CONFIG_PKG_USING_RDA58XX is not set -# CONFIG_PKG_USING_LIBNFC is not set -# CONFIG_PKG_USING_MFOC is not set -# CONFIG_PKG_USING_TMC51XX is not set -# CONFIG_PKG_USING_TCA9534 is not set -# CONFIG_PKG_USING_KOBUKI is not set -# CONFIG_PKG_USING_ROSSERIAL is not set -# CONFIG_PKG_USING_MICRO_ROS is not set -# CONFIG_PKG_USING_MCP23008 is not set -# CONFIG_PKG_USING_BLUETRUM_SDK is not set -# CONFIG_PKG_USING_MISAKA_AT24CXX is not set -# CONFIG_PKG_USING_MISAKA_RGB_BLING is not set -# CONFIG_PKG_USING_LORA_MODEM_DRIVER is not set -# CONFIG_PKG_USING_BL_MCU_SDK is not set -# CONFIG_PKG_USING_SOFT_SERIAL is not set -# CONFIG_PKG_USING_MB85RS16 is not set -# CONFIG_PKG_USING_CW2015 is not set - -# -# AI packages -# -# CONFIG_PKG_USING_LIBANN is not set -# CONFIG_PKG_USING_NNOM is not set -# CONFIG_PKG_USING_ONNX_BACKEND is not set -# CONFIG_PKG_USING_ONNX_PARSER is not set -# CONFIG_PKG_USING_TENSORFLOWLITEMICRO is not set -# CONFIG_PKG_USING_ELAPACK is not set -# CONFIG_PKG_USING_ULAPACK is not set -# CONFIG_PKG_USING_QUEST is not set -# CONFIG_PKG_USING_NAXOS is not set - -# -# miscellaneous packages -# - -# -# samples: kernel and components samples -# -# CONFIG_PKG_USING_KERNEL_SAMPLES is not set -# CONFIG_PKG_USING_FILESYSTEM_SAMPLES is not set -# CONFIG_PKG_USING_NETWORK_SAMPLES is not set -# CONFIG_PKG_USING_PERIPHERAL_SAMPLES is not set - -# -# entertainment: terminal games and other interesting software packages -# -# CONFIG_PKG_USING_CMATRIX is not set -# CONFIG_PKG_USING_SL is not set -# CONFIG_PKG_USING_CAL is not set -# CONFIG_PKG_USING_ACLOCK is not set -# CONFIG_PKG_USING_THREES is not set -# CONFIG_PKG_USING_2048 is not set -# CONFIG_PKG_USING_SNAKE is not set -# CONFIG_PKG_USING_TETRIS is not set -# CONFIG_PKG_USING_DONUT is not set -# CONFIG_PKG_USING_COWSAY is not set -# CONFIG_PKG_USING_LIBCSV is not set -# CONFIG_PKG_USING_OPTPARSE is not set -# CONFIG_PKG_USING_FASTLZ is not set -# CONFIG_PKG_USING_MINILZO is not set -# CONFIG_PKG_USING_QUICKLZ is not set -# CONFIG_PKG_USING_LZMA is not set -# CONFIG_PKG_USING_MULTIBUTTON is not set -# CONFIG_PKG_USING_FLEXIBLE_BUTTON is not set -# CONFIG_PKG_USING_CANFESTIVAL is not set -# CONFIG_PKG_USING_ZLIB is not set -# CONFIG_PKG_USING_MINIZIP is not set -# CONFIG_PKG_USING_DSTR is not set -# CONFIG_PKG_USING_TINYFRAME is not set -# CONFIG_PKG_USING_KENDRYTE_DEMO is not set -# CONFIG_PKG_USING_DIGITALCTRL is not set -# CONFIG_PKG_USING_UPACKER is not set -# CONFIG_PKG_USING_UPARAM is not set -# CONFIG_PKG_USING_HELLO is not set -# CONFIG_PKG_USING_VI is not set -# CONFIG_PKG_USING_KI is not set -# CONFIG_PKG_USING_ARMv7M_DWT is not set -# CONFIG_PKG_USING_UKAL is not set -# CONFIG_PKG_USING_CRCLIB is not set -# CONFIG_PKG_USING_LWGPS is not set -# CONFIG_PKG_USING_STATE_MACHINE is not set -# CONFIG_PKG_USING_DESIGN_PATTERN is not set -CONFIG_SOC_SERIES_GD32F1=y -CONFIG_SOC_GD32103C=y - -# -# On-chip Peripheral Drivers -# -CONFIG_BSP_USING_UART=y -CONFIG_BSP_USING_UART0=y -# CONFIG_BSP_USING_UART1 is not set -# CONFIG_BSP_USING_UART2 is not set -# CONFIG_BSP_USING_UART3 is not set -# CONFIG_BSP_USING_UART4 is not set -# CONFIG_BSP_USING_ADC is not set -# CONFIG_BSP_USING_HWTIMER is not set -# CONFIG_BSP_USING_WDT is not set -# CONFIG_BSP_USING_RTC is not set diff --git a/bsp/gd32103c-eval/Kconfig b/bsp/gd32103c-eval/Kconfig deleted file mode 100644 index 97fb8f2b2c..0000000000 --- a/bsp/gd32103c-eval/Kconfig +++ /dev/null @@ -1,109 +0,0 @@ -mainmenu "RT-Thread Configuration" - -config BSP_DIR - string - option env="BSP_ROOT" - default "." - -config RTT_DIR - string - option env="RTT_ROOT" - default "../.." - -# you can change the RTT_ROOT default: "rt-thread" -# example : default "F:/git_repositories/rt-thread" - -config PKGS_DIR - string - option env="PKGS_ROOT" - default "packages" - -source "$RTT_DIR/Kconfig" -source "$PKGS_DIR/Kconfig" - -config SOC_SERIES_GD32F1 - bool - default y - -config SOC_GD32103C - bool - select RT_USING_COMPONENTS_INIT - select RT_USING_USER_MAIN - select SOC_SERIES_GD32F1 - default y - -menu "On-chip Peripheral Drivers" - menuconfig BSP_USING_UART - bool "Enable UART" - default y - select RT_USING_SERIAL - if BSP_USING_UART - config BSP_USING_UART0 - bool "using uart0" - default n - config BSP_USING_UART1 - bool "using uart1" - default n - config BSP_USING_UART2 - bool "using uart2" - default y - config BSP_USING_UART3 - bool "using uart3" - default n - config BSP_USING_UART4 - bool "using uart4" - default n - endif - menuconfig BSP_USING_ADC - bool "Enable ADC" - default n - select RT_USING_ADC - if BSP_USING_ADC - config BSP_USING_ADC0 - bool "using adc0" - default n - config BSP_USING_ADC1 - bool "using adc1" - default n - endif - menuconfig BSP_USING_HWTIMER - bool "Enable hwtimer" - default n - select RT_USING_HWTIMER - if BSP_USING_HWTIMER - config BSP_USING_HWTIMER0 - bool "using hwtimer0" - default n - config BSP_USING_HWTIMER1 - bool "using hwtimer1" - default n - config BSP_USING_HWTIMER2 - bool "using hwtimer2" - default n - config BSP_USING_HWTIMER3 - bool "using hwtimer3" - default n - config BSP_USING_HWTIMER4 - bool "using hwtimer4" - default n - config BSP_USING_HWTIMER5 - bool "using hwtimer5" - default n - config BSP_USING_HWTIMER6 - bool "using hwtimer6" - default n - config BSP_USING_HWTIMER7 - bool "using hwtimer7" - default n - endif - config BSP_USING_WDT - bool "Enable Watchdog Timer" - select RT_USING_WDT - default n - - config BSP_USING_RTC - bool "using internal rtc" - default n - select RT_USING_RTC - -endmenu diff --git a/bsp/gd32103c-eval/Libraries/CMSIS/GD/GD32F1xx/Include/gd32f10x.h b/bsp/gd32103c-eval/Libraries/CMSIS/GD/GD32F1xx/Include/gd32f10x.h deleted file mode 100644 index 1dde2fb596..0000000000 --- a/bsp/gd32103c-eval/Libraries/CMSIS/GD/GD32F1xx/Include/gd32f10x.h +++ /dev/null @@ -1,8033 +0,0 @@ -/** - ****************************************************************************** - * @brief CMSIS Cortex-M3 Device Peripheral Access Layer Header File.. - ****************************************************************************** - */ - -/** @addtogroup CMSIS - * @{ - */ - -/** @addtogroup GD32f10X - * @{ - */ - -/* Define to prevent recursive inclusion -------------------------------------*/ -#ifndef __GD32F10X_H -#define __GD32F10X_H - -#ifdef __cplusplus -extern "C" { -#endif - -/** @addtogroup Library_configuration_section - * @{ - */ - -/* Uncomment the line below according to the target gd32f10x device used in your - application - */ - -#if !defined (GD32F10X_MD)&&!defined (GD32F10X_HD)&&!defined (GD32F10X_XD)&&!defined (GD32F10X_CL) -/* #define GD32F10X_MD */ /*!< GD32F10X_MD: GD32 Medium density devices */ -#define GD32F10X_HD /*!< GD32F10X_HD: GD32 High density Value Line devices */ -/* #define GD32F10X_XD */ /*!< GD32F10X_XD: GD32 Extra density devices */ -/* #define GD32F10X_CL */ /*!< GD32F10X_CL: GD32 Connectivity line devices */ -#endif - - -#if !defined (GD32F10X_MD)&&!defined (GD32F10X_HD)&&!defined (GD32F10X_XD)&&!defined (GD32F10X_CL) -#error "Please select first the target gd32f10x device used in your application (in gd32f10x.h file)" -#endif /* GD32F10X */ - -#if !defined USE_STDPERIPH_DRIVER -/** - * @brief Comment the line below if you will not use the peripherals drivers. - In this case, these drivers will not be included and the application code will - be based on direct access to peripherals registers - */ -/*#define USE_STDPERIPH_DRIVER*/ -#endif /* USE_STDPERIPH_DRIVER */ - -/** - * @brief In the following line adjust the value of External High Speed oscillator (HSE) - used in your application - - Tip: To avoid modifying this file each time you need to use different HSE, you - can define the HSE value in your toolchain compiler preprocessor. - */ -#if !defined HSE_VALUE -#ifdef GD32F10X_CL -#define HSE_VALUE ((uint32_t)25000000) /*!< Value of the External oscillator in Hz */ -#else -#define HSE_VALUE ((uint32_t)8000000) /* !< From 4M to 16M *!< Value of the External oscillator in Hz*/ -#endif /* HSE_VALUE */ -#endif - -#define HSE_STARTUP_TIMEOUT ((uint16_t)0xFFFF) /*!< Time out for HSI start up */ - -/* define value of high speed crystal oscillator (HXTAL) in Hz */ -#if !defined HXTAL_VALUE -#define HXTAL_VALUE ((uint32_t)8000000) /* !< from 4M to 16M *!< value of the external oscillator in Hz*/ -#endif /* high speed crystal oscillator value */ - -/* define startup timeout value of high speed crystal oscillator (HXTAL) */ -#if !defined (HXTAL_STARTUP_TIMEOUT) -#define HXTAL_STARTUP_TIMEOUT ((uint16_t)0x0800) -#endif /* high speed crystal oscillator startup timeout */ - -/* define startup timeout value of internal 8MHz RC oscillator (IRC8M) */ -#if !defined (IRC8M_STARTUP_TIMEOUT) -#define IRC8M_STARTUP_TIMEOUT ((uint16_t)0x0500) -#endif /* internal 8MHz RC oscillator startup timeout */ - -#if !defined (HSI_VALUE) -#define HSI_VALUE ((uint32_t)8000000) /*!< Value of the Internal High Speed oscillator in Hz. - The real value may vary depending on the variations - in voltage and temperature. */ -#endif /* HSI_VALUE */ - -/* define value of internal 48MHz RC oscillator (IRC48M) in Hz */ -#if !defined (IRC48M_VALUE) -#define IRC48M_VALUE ((uint32_t)48000000) -#endif /* internal 48MHz RC oscillator value */ - -/* define value of internal 8MHz RC oscillator (IRC8M) in Hz */ -#if !defined (IRC8M_VALUE) -#define IRC8M_VALUE ((uint32_t)8000000) -#endif /* internal 8MHz RC oscillator value */ - -#if !defined (LSI_VALUE) -#define LSI_VALUE ((uint32_t)40000) /*!< Value of the Internal Low Speed oscillator in Hz - The real value may vary depending on the variations - in voltage and temperature. */ -#endif /* LSI_VALUE */ - -#if !defined (LSE_VALUE) -#define LSE_VALUE ((uint32_t)32768) /*!< Value of the External Low Speed oscillator in Hz */ -#endif /* LSE_VALUE */ - -/** - * @brief GD32F10X Firmware Library version number V1.0 - */ -#define __GD32F10X_STDPERIPH_VERSION_MAIN (0x01) /*!< [31:24] main version */ -#define __GD32F10X_STDPERIPH_VERSION_SUB1 (0x00) /*!< [23:16] sub1 version */ -#define __GD32F10X_STDPERIPH_VERSION_SUB2 (0x01) /*!< [15:8] sub2 version */ -#define __GD32F10X_STDPERIPH_VERSION_RC (0x00) /*!< [7:0] release candidate */ -#define __GD32F10X_STDPERIPH_VERSION ((__GD32F10X_STDPERIPH_VERSION_MAIN << 24)\ - |(__GD32F10X_STDPERIPH_VERSION_SUB1 << 16)\ - |(__GD32F10X_STDPERIPH_VERSION_SUB2 << 8)\ - |(__GD32F10X_STDPERIPH_VERSION_RC)) - -/** - * @} - */ - -/** @addtogroup Configuration_section_for_CMSIS - * @{ - */ - -/** - * @brief Configuration of the Cortex-M3 Processor and Core Peripherals - */ -#define __MPU_PRESENT 0 /*!< GD32 devices does not provide an MPU */ -#define __NVIC_PRIO_BITS 4 /*!< GD32F10X uses 4 Bits for the Priority Levels */ -#define __VENDOR_SYSTICKCONFIG 0 /*!< Set to 1 if different SysTick Config is used */ - -/*!< Interrupt Number Definition */ -typedef enum IRQn { - /****** Cortex-M3 Processor Exceptions Numbers ***************************************************/ - NonMaskableInt_IRQn = -14, /*!< 2 Non Maskable Interrupt */ - MemoryManagement_IRQn = -12, /*!< 4 Cortex-M3 Memory Management Interrupt */ - BusFault_IRQn = -11, /*!< 5 Cortex-M3 Bus Fault Interrupt */ - UsageFault_IRQn = -10, /*!< 6 Cortex-M3 Usage Fault Interrupt */ - SVCall_IRQn = -5, /*!< 11 Cortex-M3 SV Call Interrupt */ - DebugMonitor_IRQn = -4, /*!< 12 Cortex-M3 Debug Monitor Interrupt */ - PendSV_IRQn = -2, /*!< 14 Cortex-M3 Pend SV Interrupt */ - SysTick_IRQn = -1, /*!< 15 Cortex-M3 System Tick Interrupt */ - - /****** GD32 specific Interrupt Numbers *********************************************************/ - WWDG_IRQn = 0, /*!< Window WatchDog Interrupt */ - LVD_IRQn = 1, /*!< PVD through EXTI Line detection Interrupt */ - TAMPER_IRQn = 2, /*!< Tamper Interrupt */ - RTC_IRQn = 3, /*!< RTC global Interrupt */ - FLASH_IRQn = 4, /*!< FLASH global Interrupt */ - RCC_IRQn = 5, /*!< RCC global Interrupt */ - EXTI0_IRQn = 6, /*!< EXTI Line0 Interrupt */ - EXTI1_IRQn = 7, /*!< EXTI Line1 Interrupt */ - EXTI2_IRQn = 8, /*!< EXTI Line2 Interrupt */ - EXTI3_IRQn = 9, /*!< EXTI Line3 Interrupt */ - EXTI4_IRQn = 10, /*!< EXTI Line4 Interrupt */ - DMA1_Channel1_IRQn = 11, /*!< DMA1 Channel 1 global Interrupt */ - DMA1_Channel2_IRQn = 12, /*!< DMA1 Channel 2 global Interrupt */ - DMA1_Channel3_IRQn = 13, /*!< DMA1 Channel 3 global Interrupt */ - DMA1_Channel4_IRQn = 14, /*!< DMA1 Channel 4 global Interrupt */ - DMA1_Channel5_IRQn = 15, /*!< DMA1 Channel 5 global Interrupt */ - DMA1_Channel6_IRQn = 16, /*!< DMA1 Channel 6 global Interrupt */ - DMA1_Channel7_IRQn = 17, /*!< DMA1 Channel 7 global Interrupt */ - -#ifdef GD32F10X_MD - ADC0_1_IRQn = 18, /*!< ADC0 and ADC1 global Interrupt */ - USB_HP_CAN1_TX_IRQn = 19, /*!< USB Device High Priority or CAN1 TX Interrupts */ - USB_LP_CAN1_RX0_IRQn = 20, /*!< USB Device Low Priority or CAN1 RX0 Interrupts */ - CAN1_RX1_IRQn = 21, /*!< CAN1 RX1 Interrupt */ - CAN1_SCE_IRQn = 22, /*!< CAN1 SCE Interrupt */ - EXTI9_5_IRQn = 23, /*!< External Line[9:5] Interrupts */ - TIMER0_BRK_IRQn = 24, /*!< TIMER0 Break Interrupt */ - TIMER0_UP_IRQn = 25, /*!< TIMER0 Update Interrupt */ - TIMER0_TRG_COM_IRQn = 26, /*!< TIMER0 Trigger and Commutation Interrupt */ - TIMER0_CC_IRQn = 27, /*!< TIMER0 Capture Compare Interrupt */ - TIMER1_IRQn = 28, /*!< TIMER1 global Interrupt */ - TIMER2_IRQn = 29, /*!< TIMER2 global Interrupt */ - TIMER3_IRQn = 30, /*!< TIMER3 global Interrupt */ - I2C1_EV_IRQn = 31, /*!< I2C1 Event Interrupt */ - I2C1_ER_IRQn = 32, /*!< I2C1 Error Interrupt */ - I2C2_EV_IRQn = 33, /*!< I2C2 Event Interrupt */ - I2C2_ER_IRQn = 34, /*!< I2C2 Error Interrupt */ - SPI1_IRQn = 35, /*!< SPI1 global Interrupt */ - SPI2_IRQn = 36, /*!< SPI2 global Interrupt */ - USART1_IRQn = 37, /*!< USART1 global Interrupt */ - USART2_IRQn = 38, /*!< USART2 global Interrupt */ - USART3_IRQn = 39, /*!< USART3 global Interrupt */ - EXTI15_10_IRQn = 40, /*!< External Line[15:10] Interrupts */ - RTCAlarm_IRQn = 41, /*!< RTC Alarm through EXTI Line Interrupt */ - USBWakeUp_IRQn = 42, /*!< USB Device WakeUp from suspend through EXTI Line Interrupt */ - EXMC_IRQn = 48 /*!< EXMC global Interrupt */ -#endif /* GD32F10X_MD */ - -#ifdef GD32F10X_HD - ADC0_1_IRQn = 18, /*!< ADC0 and ADC1 global Interrupt */ - USB_HP_CAN1_TX_IRQn = 19, /*!< USB Device High Priority or CAN1 TX Interrupts */ - USB_LP_CAN1_RX0_IRQn = 20, /*!< USB Device Low Priority or CAN1 RX0 Interrupts */ - CAN1_RX1_IRQn = 21, /*!< CAN1 RX1 Interrupt */ - CAN1_SCE_IRQn = 22, /*!< CAN1 SCE Interrupt */ - EXTI9_5_IRQn = 23, /*!< External Line[9:5] Interrupts */ - TIMER0_BRK_IRQn = 24, /*!< TIMER0 Break Interrupt */ - TIMER0_UP_IRQn = 25, /*!< TIMER0 Update Interrupt */ - TIMER0_TRG_COM_IRQn = 26, /*!< TIMER0 Trigger and Commutation Interrupt */ - TIMER0_CC_IRQn = 27, /*!< TIMER0 Capture Compare Interrupt */ - TIMER1_IRQn = 28, /*!< TIMER1 global Interrupt */ - TIMER2_IRQn = 29, /*!< TIMER2 global Interrupt */ - TIMER3_IRQn = 30, /*!< TIMER3 global Interrupt */ - I2C1_EV_IRQn = 31, /*!< I2C1 Event Interrupt */ - I2C1_ER_IRQn = 32, /*!< I2C1 Error Interrupt */ - I2C2_EV_IRQn = 33, /*!< I2C2 Event Interrupt */ - I2C2_ER_IRQn = 34, /*!< I2C2 Error Interrupt */ - SPI1_IRQn = 35, /*!< SPI1 global Interrupt */ - SPI2_IRQn = 36, /*!< SPI2 global Interrupt */ - USART0_IRQn = 37, /*!< USART1 global Interrupt */ - USART1_IRQn = 38, /*!< USART2 global Interrupt */ - USART2_IRQn = 39, /*!< USART3 global Interrupt */ - EXTI15_10_IRQn = 40, /*!< External Line[15:10] Interrupts */ - RTCAlarm_IRQn = 41, /*!< RTC Alarm through EXTI Line Interrupt */ - USBWakeUp_IRQn = 42, /*!< USB Device WakeUp from suspend through EXTI Line Interrupt */ - TIMER7_BRK_IRQn = 43, /*!< TIMER7 Break Interrupt */ - TIMER7_UP_IRQn = 44, /*!< TIMER7 Update Interrupt */ - TIMER7_TRG_COM_IRQn = 45, /*!< TIMER7 Trigger and Commutation Interrupt */ - TIMER7_CC_IRQn = 46, /*!< TIMER7 Capture Compare Interrupt */ - ADC3_IRQn = 47, /*!< ADC3 global Interrupt */ - EXMC_IRQn = 48, /*!< EXMC global Interrupt */ - SDIO_IRQn = 49, /*!< SDIO global Interrupt */ - TIMER4_IRQn = 50, /*!< TIMER4 global Interrupt */ - SPI3_IRQn = 51, /*!< SPI3 global Interrupt */ - UART3_IRQn = 52, /*!< UART4 global Interrupt */ - UART4_IRQn = 53, /*!< UART5 global Interrupt */ - TIMER5_IRQn = 54, /*!< TIMER5 global Interrupt */ - TIMER6_IRQn = 55, /*!< TIMER6 global Interrupt */ - DMA2_Channel1_IRQn = 56, /*!< DMA2 Channel 1 global Interrupt */ - DMA2_Channel2_IRQn = 57, /*!< DMA2 Channel 2 global Interrupt */ - DMA2_Channel3_IRQn = 58, /*!< DMA2 Channel 3 global Interrupt */ - DMA2_Channel4_5_IRQn = 59 /*!< DMA2 Channel 4 and Channel 5 global Interrupt */ -#endif /* GD32F10X_HD */ - -#ifdef GD32F10X_XD - ADC0_1_IRQn = 18, /*!< ADC0 and ADC1 global Interrupt */ - USB_HP_CAN1_TX_IRQn = 19, /*!< USB Device High Priority or CAN1 TX Interrupts */ - USB_LP_CAN1_RX0_IRQn = 20, /*!< USB Device Low Priority or CAN1 RX0 Interrupts */ - CAN1_RX1_IRQn = 21, /*!< CAN1 RX1 Interrupt */ - CAN1_SCE_IRQn = 22, /*!< CAN1 SCE Interrupt */ - EXTI9_5_IRQn = 23, /*!< External Line[9:5] Interrupts */ - TIMER0_BRK_TIMER8_IRQn = 24, /*!< TIMER0 Break Interrupt and TIMER8 global Interrupt */ - TIMER0_UP_TIMER9_IRQn = 25, /*!< TIMER0 Update Interrupt and TIMER9 global Interrupt */ - TIMER0_TRG_COM_TIMER10_IRQn = 26, /*!< TIMER0 Trigger and Commutation Interrupt and TIMER10 global interrupt */ - TIMER0_CC_IRQn = 27, /*!< TIMER0 Capture Compare Interrupt */ - TIMER1_IRQn = 28, /*!< TIMER1 global Interrupt */ - TIMER2_IRQn = 29, /*!< TIMER2 global Interrupt */ - TIMER3_IRQn = 30, /*!< TIMER3 global Interrupt */ - I2C1_EV_IRQn = 31, /*!< I2C1 Event Interrupt */ - I2C1_ER_IRQn = 32, /*!< I2C1 Error Interrupt */ - I2C2_EV_IRQn = 33, /*!< I2C2 Event Interrupt */ - I2C2_ER_IRQn = 34, /*!< I2C2 Error Interrupt */ - SPI1_IRQn = 35, /*!< SPI1 global Interrupt */ - SPI2_IRQn = 36, /*!< SPI2 global Interrupt */ - USART1_IRQn = 37, /*!< USART1 global Interrupt */ - USART2_IRQn = 38, /*!< USART2 global Interrupt */ - USART3_IRQn = 39, /*!< USART3 global Interrupt */ - EXTI15_10_IRQn = 40, /*!< External Line[15:10] Interrupts */ - RTCAlarm_IRQn = 41, /*!< RTC Alarm through EXTI Line Interrupt */ - USBWakeUp_IRQn = 42, /*!< USB Device WakeUp from suspend through EXTI Line Interrupt */ - TIMER7_BRK_TIMER11_IRQn = 43, /*!< TIMER7 Break Interrupt and TIMER11 global Interrupt */ - TIMER7_UP_TIMER12_IRQn = 44, /*!< TIMER7 Update Interrupt and TIMER12 global Interrupt */ - TIMER7_TRG_COM_TIMER13_IRQn = 45, /*!< TIMER7 Trigger and Commutation Interrupt and TIMER13 global interrupt */ - TIMER7_CC_IRQn = 46, /*!< TIMER7 Capture Compare Interrupt */ - ADC3_IRQn = 47, /*!< ADC3 global Interrupt */ - EXMC_IRQn = 48, /*!< EXMC global Interrupt */ - SDIO_IRQn = 49, /*!< SDIO global Interrupt */ - TIMER4_IRQn = 50, /*!< TIMER4 global Interrupt */ - SPI3_IRQn = 51, /*!< SPI3 global Interrupt */ - UART4_IRQn = 52, /*!< UART4 global Interrupt */ - UART5_IRQn = 53, /*!< UART5 global Interrupt */ - TIMER5_IRQn = 54, /*!< TIMER5 global Interrupt */ - TIMER6_IRQn = 55, /*!< TIMER6 global Interrupt */ - DMA2_Channel1_IRQn = 56, /*!< DMA2 Channel 1 global Interrupt */ - DMA2_Channel2_IRQn = 57, /*!< DMA2 Channel 2 global Interrupt */ - DMA2_Channel3_IRQn = 58, /*!< DMA2 Channel 3 global Interrupt */ - DMA2_Channel4_5_IRQn = 59 /*!< DMA2 Channel 4 and Channel 5 global Interrupt */ -#endif /* GD32F10X_XD */ - -#ifdef GD32F10X_CL - ADC0_1_IRQn = 18, /*!< ADC0 and ADC1 global Interrupt */ - CAN1_TX_IRQn = 19, /*!< CAN1 TX Interrupts */ - CAN1_RX0_IRQn = 20, /*!< CAN1 RX0 Interrupts */ - CAN1_RX1_IRQn = 21, /*!< CAN1 RX1 Interrupt */ - CAN1_SCE_IRQn = 22, /*!< CAN1 SCE Interrupt */ - EXTI9_5_IRQn = 23, /*!< External Line[9:5] Interrupts */ - TIMER0_BRK_TIMER8_IRQn = 24, /*!< TIMER0 Break Interrupt and TIMER8 global Interrupt */ - TIMER0_UP_TIMER9_IRQn = 25, /*!< TIMER0 Update Interrupt and TIMER9 global Interrupt */ - TIMER0_TRG_COM_TIMER10_IRQn = 26, /*!< TIMER0 Trigger and Commutation Interrupt and TIMER10 global interrupt */ - TIMER0_CC_IRQn = 27, /*!< TIMER0 Capture Compare Interrupt */ - TIMER1_IRQn = 28, /*!< TIMER1 global Interrupt */ - TIMER2_IRQn = 29, /*!< TIMER2 global Interrupt */ - TIMER3_IRQn = 30, /*!< TIMER3 global Interrupt */ - I2C1_EV_IRQn = 31, /*!< I2C1 Event Interrupt */ - I2C1_ER_IRQn = 32, /*!< I2C1 Error Interrupt */ - I2C2_EV_IRQn = 33, /*!< I2C2 Event Interrupt */ - I2C2_ER_IRQn = 34, /*!< I2C2 Error Interrupt */ - SPI1_IRQn = 35, /*!< SPI1 global Interrupt */ - SPI2_IRQn = 36, /*!< SPI2 global Interrupt */ - USART1_IRQn = 37, /*!< USART1 global Interrupt */ - USART2_IRQn = 38, /*!< USART2 global Interrupt */ - USART3_IRQn = 39, /*!< USART3 global Interrupt */ - EXTI15_10_IRQn = 40, /*!< External Line[15:10] Interrupts */ - RTCAlarm_IRQn = 41, /*!< RTC Alarm through EXTI Line Interrupt */ - OTG_FS_WKUP_IRQn = 42, /*!< USB OTG FS WakeUp from suspend through EXTI Line Interrupt */ - TIMER7_BRK_TIMER11_IRQn = 43, /*!< TIMER7 Break Interrupt and TIMER11 global Interrupt */ - TIMER7_UP_TIMER12_IRQn = 44, /*!< TIMER7 Update Interrupt and TIMER12 global Interrupt */ - TIMER7_TRG_COM_TIMER13_IRQn = 45, /*!< TIMER7 Trigger and Commutation Interrupt and TIMER13 global interrupt */ - TIMER7_CC_IRQn = 46, /*!< TIMER7 Capture Compare Interrupt */ - ADC3_IRQn = 47, /*!< ADC3 global Interrupt */ - EXMC_IRQn = 48, /*!< EXMC global Interrupt */ - TIMER4_IRQn = 50, /*!< TIMER4 global Interrupt */ - SPI3_IRQn = 51, /*!< SPI3 global Interrupt */ - UART4_IRQn = 52, /*!< UART4 global Interrupt */ - UART5_IRQn = 53, /*!< UART5 global Interrupt */ - TIMER5_IRQn = 54, /*!< TIMER5 global Interrupt */ - TIMER6_IRQn = 55, /*!< TIMER6 global Interrupt */ - DMA2_Channel1_IRQn = 56, /*!< DMA2 Channel 1 global Interrupt */ - DMA2_Channel2_IRQn = 57, /*!< DMA2 Channel 2 global Interrupt */ - DMA2_Channel3_IRQn = 58, /*!< DMA2 Channel 3 global Interrupt */ - DMA2_Channel4_IRQn = 59, /*!< DMA2 Channel 4 global Interrupt */ - DMA2_Channel5_IRQn = 60, /*!< DMA2 Channel 5 global Interrupt */ - ETH_IRQn = 61, /*!< Ethernet global Interrupt */ - ETH_WKUP_IRQn = 62, /*!< Ethernet Wakeup through EXTI line Interrupt */ - CAN2_TX_IRQn = 63, /*!< CAN2 TX Interrupt */ - CAN2_RX0_IRQn = 64, /*!< CAN2 RX0 Interrupt */ - CAN2_RX1_IRQn = 65, /*!< CAN2 RX1 Interrupt */ - CAN2_SCE_IRQn = 66, /*!< CAN2 SCE Interrupt */ - OTG_FS_IRQn = 67 /*!< USB OTG FS global Interrupt */ -#endif /* GD32F10X_CL */ -} IRQn_Type; - - -/** - * @} - */ - -/* Includes ------------------------------------------------------------------*/ -#include "core_cm3.h" -#include "system_gd32f10x.h" -#include <stdint.h> - -/** @addtogroup Exported_types - * @{ - */ -typedef enum {ERROR = 0, SUCCESS = !ERROR, RESET = 0, SET = !RESET, DISABLE = 0, ENABLE = !DISABLE} TypeState, EventStatus, ControlStatus, FlagStatus, ErrStatus; - -#define REG32(addr) (*(volatile uint32_t *)(uint32_t)(addr)) -#define REG16(addr) (*(volatile uint16_t *)(uint32_t)(addr)) -#define REG8(addr) (*(volatile uint8_t *)(uint32_t)(addr)) -#define BIT(x) ((uint32_t)((uint32_t)0x01U<<(x))) -#define BITS(start, end) ((0xFFFFFFFFUL << (start)) & (0xFFFFFFFFUL >> (31U - (uint32_t)(end)))) -#define GET_BITS(regval, start, end) (((regval) & BITS((start),(end))) >> (start)) - -typedef int32_t s32; -typedef int16_t s16; -typedef int8_t s8; - -typedef const int32_t sc32; /*!< Read Only */ -typedef const int16_t sc16; /*!< Read Only */ -typedef const int8_t sc8; /*!< Read Only */ - -typedef __IO int32_t vs32; -typedef __IO int16_t vs16; -typedef __IO int8_t vs8; - -typedef __I int32_t vsc32; /*!< Read Only */ -typedef __I int16_t vsc16; /*!< Read Only */ -typedef __I int8_t vsc8; /*!< Read Only */ - -typedef uint32_t u32; -typedef uint16_t u16; -typedef uint8_t u8; - -typedef const uint32_t uc32; /*!< Read Only */ -typedef const uint16_t uc16; /*!< Read Only */ -typedef const uint8_t uc8; /*!< Read Only */ - -typedef __IO uint32_t vu32; -typedef __IO uint16_t vu16; -typedef __IO uint8_t vu8; - -typedef __I uint32_t vuc32; /*!< Read Only */ -typedef __I uint16_t vuc16; /*!< Read Only */ -typedef __I uint8_t vuc8; /*!< Read Only */ - -/** @addtogroup Peripheral_registers_structures - * @{ - */ - -/** - * @brief Analog to Digital Converter - */ -typedef struct { - __IO uint32_t STR; - __IO uint32_t CTLR1; - __IO uint32_t CTLR2; - __IO uint32_t SPT1; - __IO uint32_t SPT2; - __IO uint32_t ICOS1; - __IO uint32_t ICOS2; - __IO uint32_t ICOS3; - __IO uint32_t ICOS4; - __IO uint32_t AWHT; - __IO uint32_t AWLT; - __IO uint32_t RSQ1; - __IO uint32_t RSQ2; - __IO uint32_t RSQ3; - __IO uint32_t ISQ; - __IO uint32_t IDTR1; - __IO uint32_t IDTR2; - __IO uint32_t IDTR3; - __IO uint32_t IDTR4; - __IO uint32_t RDTR; -} ADC_TypeDef; - -/** - * @brief Backup Registers - */ -typedef struct { - uint32_t RESERVED0; - __IO uint16_t DR1; - uint16_t RESERVED1; - __IO uint16_t DR2; - uint16_t RESERVED2; - __IO uint16_t DR3; - uint16_t RESERVED3; - __IO uint16_t DR4; - uint16_t RESERVED4; - __IO uint16_t DR5; - uint16_t RESERVED5; - __IO uint16_t DR6; - uint16_t RESERVED6; - __IO uint16_t DR7; - uint16_t RESERVED7; - __IO uint16_t DR8; - uint16_t RESERVED8; - __IO uint16_t DR9; - uint16_t RESERVED9; - __IO uint16_t DR10; - uint16_t RESERVED10; - __IO uint16_t RCCR; - uint16_t RESERVED11; - __IO uint16_t TPCR; - uint16_t RESERVED12; - __IO uint16_t TIER; - uint16_t RESERVED13[5]; - __IO uint16_t DR11; - uint16_t RESERVED14; - __IO uint16_t DR12; - uint16_t RESERVED15; - __IO uint16_t DR13; - uint16_t RESERVED16; - __IO uint16_t DR14; - uint16_t RESERVED17; - __IO uint16_t DR15; - uint16_t RESERVED18; - __IO uint16_t DR16; - uint16_t RESERVED19; - __IO uint16_t DR17; - uint16_t RESERVED20; - __IO uint16_t DR18; - uint16_t RESERVED21; - __IO uint16_t DR19; - uint16_t RESERVED22; - __IO uint16_t DR20; - uint16_t RESERVED23; - __IO uint16_t DR21; - uint16_t RESERVED24; - __IO uint16_t DR22; - uint16_t RESERVED25; - __IO uint16_t DR23; - uint16_t RESERVED26; - __IO uint16_t DR24; - uint16_t RESERVED27; - __IO uint16_t DR25; - uint16_t RESERVED28; - __IO uint16_t DR26; - uint16_t RESERVED29; - __IO uint16_t DR27; - uint16_t RESERVED30; - __IO uint16_t DR28; - uint16_t RESERVED31; - __IO uint16_t DR29; - uint16_t RESERVED32; - __IO uint16_t DR30; - uint16_t RESERVED33; - __IO uint16_t DR31; - uint16_t RESERVED34; - __IO uint16_t DR32; - uint16_t RESERVED35; - __IO uint16_t DR33; - uint16_t RESERVED36; - __IO uint16_t DR34; - uint16_t RESERVED37; - __IO uint16_t DR35; - uint16_t RESERVED38; - __IO uint16_t DR36; - uint16_t RESERVED39; - __IO uint16_t DR37; - uint16_t RESERVED40; - __IO uint16_t DR38; - uint16_t RESERVED41; - __IO uint16_t DR39; - uint16_t RESERVED42; - __IO uint16_t DR40; - uint16_t RESERVED43; - __IO uint16_t DR41; - uint16_t RESERVED44; - __IO uint16_t DR42; - uint16_t RESERVED45; -} BKP_TypeDef; - - -/** - * @brief Controller Area Network TxMailBox - */ - -typedef struct { - __IO uint32_t TMIR; /*!< CAN transmit mailbox identifier register, Address offset: 0x180, 0x190, 0x1A0 */ - __IO uint32_t TMPR; /*!< CAN transmit mailbox property register, Address offset: 0x184, 0x194, 0x1A4 */ - __IO uint32_t TMD0R; /*!< CAN transmit mailbox data0 register, Address offset: 0x188, 0x198, 0x1A8 */ - __IO uint32_t TMD1R; /*!< CAN transmit mailbox data1 register, Address offset: 0x18C, 0x19C, 0x1AC */ -} CAN_TxMailBox_TypeDef; - -/** - * @brief Controller Area Network FIFOMailBox - */ - -typedef struct { - __IO uint32_t RFMIR; /*!< CAN receive FIFO mailbox identifier register, Address offset: 0x1B0, 0x1C0 */ - __IO uint32_t RFMPR; /*!< CAN receive FIFO mailbox property register, Address offset: 0x1B4, 0x1C4 */ - __IO uint32_t RFMD0R; /*!< CAN receive FIFO mailbox data0 register, Address offset: 0x1B8, 0x1C8 */ - __IO uint32_t RFMD1R; /*!< CAN receive FIFO mailbox data1 register, Address offset: 0x1BC, 0x1CC */ -} CAN_FIFOMailBox_TypeDef; - -/** - * @brief Controller Area Network FilterRegister - */ - -typedef struct { - __IO uint32_t FD0R; /*!< CAN filter x data 0 register */ - __IO uint32_t FD1R; /*!< CAN filter x data 1 register */ -} CAN_FilterRegister_TypeDef; - -/** - * @brief Controller Area Network - */ - -typedef struct { - __IO uint32_t CTLR; /*!< CAN control register, Address offset: 0x00 */ - __IO uint32_t STR; /*!< CAN status register, Address offset: 0x04 */ - __IO uint32_t TSTR; /*!< CAN transmit status register, Address offset: 0x08 */ - __IO uint32_t RFR0; /*!< CAN receive FIFO0 register, Address offset: 0x0C */ - __IO uint32_t RFR1; /*!< CAN receive FIFO0 register, Address offset: 0x10 */ - __IO uint32_t IER; /*!< CAN interrupt enable register, Address offset: 0x14 */ - __IO uint32_t ER; /*!< CAN error register, Address offset: 0x18 */ - __IO uint32_t BTR; /*!< CAN bit timing register, Address offset: 0x1C */ - uint32_t RESERVED0[88]; - CAN_TxMailBox_TypeDef TxMailBox[3]; - CAN_FIFOMailBox_TypeDef FIFOMailBox[2]; - uint32_t RESERVED1[12]; - __IO uint32_t FCTLR; /*!< CAN filter control register, Address offset: 0x200 */ - __IO uint32_t FMR; /*!< CAN filter mode register, Address offset: 0x204 */ - uint32_t RESERVED2; - __IO uint32_t FSR; /*!< CAN filter scale register, Address offset: 0x20C */ - uint32_t RESERVED3; - __IO uint32_t FAFR; /*!< CAN filter associated FIFO register, Address offset: 0x214 */ - uint32_t RESERVED4; - __IO uint32_t FWR; /*!< CAN filter working register, Address offset: 0x21C */ - uint32_t RESERVED5[8]; -#ifndef GD32F10X_CL - CAN_FilterRegister_TypeDef FilterRegister[14]; -#else - CAN_FilterRegister_TypeDef FilterRegister[28]; -#endif /* GD32F10X_CL */ -} CAN_TypeDef; - - -/** - * @brief CRC calculation unit - */ -typedef struct { - __IO uint32_t DTR; /*!< CRC Data register, Address offset: 0x00 */ - __IO uint8_t FDTR; /*!< CRC Independent data register, Address offset: 0x04 */ - uint8_t RESERVED0; /*!< Reserved, 0x05 */ - uint16_t RESERVED1; /*!< Reserved, 0x06 */ - __IO uint32_t CTLR; /*!< CRC Control register, Address offset: 0x08 */ -} CRC_TypeDef; -/** - * @brief Digital to Analog Converter - */ -typedef struct { - __IO uint32_t CTLR; - __IO uint32_t SWTR; - __IO uint32_t C1R12DHR; - __IO uint32_t C1L12DHR; - __IO uint32_t C1R8DHR; - - __IO uint32_t C2R12DHR; - __IO uint32_t C2L12DHR; - __IO uint32_t C2R8DHR; - - __IO uint32_t DCR12DHR; - __IO uint32_t DCL12DHR; - __IO uint32_t DCR8RD; - - __IO uint32_t C1ODR; - __IO uint32_t C2ODR; -} DAC_TypeDef; -/** - * @brief Debug MCU - */ -typedef struct { - __IO uint32_t IDR; /*!< MCU device ID code, Address offset: 0x00 */ - __IO uint32_t CTLR; /*!< Debug MCU CTLR freeze register, Address offset: 0x04 */ -} MCUDBG_TypeDef; - -/** - * @brief DMA Controller - */ - -typedef struct { - __IO uint32_t CTLR; /*!< DMA channel x configuration register */ - __IO uint32_t RCNT; /*!< DMA channel x number of data register */ - __IO uint32_t PBAR; /*!< DMA channel x peripheral address register */ - __IO uint32_t MBAR; /*!< DMA channel x memory address register */ -} DMA_Channel_TypeDef; - -typedef struct { - __IO uint32_t IFR; /*!< DMA interrupt status register, Address offset: 0x00 */ - __IO uint32_t ICR; /*!< DMA interrupt flag clear register,Address offset: 0x04 */ -} DMA_TypeDef; - -typedef struct { - __IO uint32_t CFR; /*!< Ethernet MAC configuration register, Address offset: 0x00 */ - __IO uint32_t FRMFR; /*!< Ethernet MAC frame filter register, Address offset: 0x04 */ - __IO uint32_t HLHR; /*!< Ethernet MAC hash list high register, Address offset: 0x08 */ - __IO uint32_t HLLR; /*!< Ethernet MAC hash list low register, Address offset: 0x0C */ - __IO uint32_t PHYAR; /*!< Ethernet MAC PHY address register, Address offset: 0x10 */ - __IO uint32_t PHYDR; /*!< Ethernet MAC PHY data register, Address offset: 0x14 */ - __IO uint32_t FCTLR; /*!< Ethernet MAC flow control register, Address offset: 0x18 */ - __IO uint32_t VLTR; /*!< Ethernet MAC VLAN tag register, Address offset: 0x1C */ - uint32_t RESERVED0[2]; /*!< Reserved, 0x24 */ - __IO uint32_t RWFFR; /*!< Ethernet MAC remote wakeup frame filter register, Address offset: 0x28 */ - __IO uint32_t WUMR; /*!< Ethernet MAC wake up management register, Address offset: 0x2C */ - uint32_t RESERVED1[2]; /*!< Reserved, 0x34 */ - __IO uint32_t ISR; /*!< Ethernet MAC interrupt status register, Address offset: 0x38 */ - __IO uint32_t IMR; /*!< Ethernet MAC interrupt mask register, Address offset: 0x3C */ - __IO uint32_t ADDR0HR; /*!< Ethernet MAC address 0 high register, Address offset: 0x40 */ - __IO uint32_t ADDR0LR; /*!< Ethernet MAC address 0 low register, Address offset: 0x44 */ - __IO uint32_t ADDR1HR; /*!< Ethernet MAC address 1 high register, Address offset: 0x48 */ - __IO uint32_t ADDR1LR; /*!< Ethernet MAC address 1 low register, Address offset: 0x4C */ - __IO uint32_t ADDR2HR; /*!< Ethernet MAC address 2 high register, Address offset: 0x50 */ - __IO uint32_t ADDR2LR; /*!< Ethernet MAC address 2 low register, Address offset: 0x54 */ - __IO uint32_t ADDR3HR; /*!< Ethernet MAC address 3 high register, Address offset: 0x58 */ - __IO uint32_t ADDR3LR; /*!< Ethernet MAC address 3 low register, Address offset: 0x5C */ - uint32_t RESERVED2[1032]; /*!< Reserved, 0x107C */ - __IO uint32_t FCTHR; /*!< Ethernet MAC flow control threshold register, Address offset: 0x1080 */ -} ETH_MAC_TypeDef; - -typedef struct { - __IO uint32_t CTLR; /*!< Ethernet MSC control register, Address offset: 0x100 */ - __IO uint32_t RISR; /*!< Ethernet MSC receive interrupt status register, Address offset: 0x104 */ - __IO uint32_t TISR; /*!< Ethernet MSC transmit interrupt status register, Address offset: 0x108 */ - __IO uint32_t RIMR; /*!< Ethernet MSC receive interrupt mask register, Address offset: 0x10C */ - __IO uint32_t TIMR; /*!< Ethernet MSC transmit interrupt mask register, Address offset: 0x110 */ - uint32_t RESERVED3[14]; /*!< Reserved, 0x148 */ - __IO uint32_t SCCNT; /*!< Ethernet MSC transmitted good frames after a single collision counterregister, Address offset: 0x14C */ - __IO uint32_t MSCCNT; /*!< Ethernet MSC transmitted good frames after more than a single collision counterregister, Address offset: 0x150 */ - uint32_t RESERVED4[5]; /*!< Reserved, 0x164 */ - __IO uint32_t TGFCNT; /*!< Ethernet MSC transmitted good frames counter register, Address offset: 0x168 */ - uint32_t RESERVED5[10]; /*!< Reserved, 0x190 */ - __IO uint32_t RFCECNT; /*!< Ethernet MSC received frames with CRC error counter register, Address offset: 0x194 */ - __IO uint32_t RFAECNT; /*!< Ethernet MSC received frames with alignment error counter register, Address offset: 0x198 */ - uint32_t RESERVED6[10]; /*!< Reserved, 0x1C0 */ - __IO uint32_t RGUFCNT; /*!< Ethernet MSC received good unicast frames counter register, Address offset: 0x1C4 */ -} ETH_MSC_TypeDef; - -typedef struct { - __IO uint32_t TSCTLR; /*!< Ethernet PTP time stamp control register, Address offset: 0x700 */ - __IO uint32_t SSINCR; /*!< Ethernet PTP subsecond increment register, Address offset: 0x704 */ - __IO uint32_t TMSHR; /*!< Ethernet PTP time stamp high register, Address offset: 0x708 */ - __IO uint32_t TMSLR; /*!< Ethernet PTP time stamp low register, Address offset: 0x70C */ - __IO uint32_t TMSHUR; /*!< Ethernet PTP time stamp high update register, Address offset: 0x710 */ - __IO uint32_t TMSLUR; /*!< Ethernet PTP time stamp low update register, Address offset: 0x714 */ - __IO uint32_t TSACNT; /*!< Ethernet PTP time stamp addend register, Address offset: 0x718 */ - __IO uint32_t ETHR; /*!< Ethernet PTP expected time high register, Address offset: 0x71C */ - __IO uint32_t ETLR; /*!< Ethernet PTP expected time low register, Address offset: 0x720 */ -} ETH_PTP_TypeDef; - -typedef struct { - __IO uint32_t BCR; /*!< Ethernet DMA bus control register, Address offset: 0x1000 */ - __IO uint32_t TPER; /*!< Ethernet DMA transmit poll enable register, Address offset: 0x1004 */ - __IO uint32_t RPER; /*!< Ethernet DMA receive poll enable register, Address offset: 0x1008 */ - __IO uint32_t RDTAR; /*!< Ethernet DMA receive descriptor tab address register, Address offset: 0x100C */ - __IO uint32_t TDTAR; /*!< Ethernet DMA transmit descriptor tab address register, Address offset: 0x1010 */ - __IO uint32_t STR; /*!< Ethernet DMA status register, Address offset: 0x1014 */ - __IO uint32_t CTLR; /*!< Ethernet DMA control register, Address offset: 0x1018 */ - __IO uint32_t IER; /*!< Ethernet DMA interrupt enable register, Address offset: 0x1018 */ - __IO uint32_t MFBOCNT; /*!< Ethernet DMA missed frame and buffer overflow counter register, Address offset: 0x101C */ - uint32_t RESERVED7[9]; /*!< Reserved, 0x1044 */ - __IO uint32_t CTDAR; /*!< Ethernet DMA current transmit descriptor address register, Address offset: 0x1048 */ - __IO uint32_t CRDAR; /*!< Ethernet DMA current receive descriptor address register, Address offset: 0x104C */ - __IO uint32_t CTBAR; /*!< Ethernet DMA current transmit buffer address register, Address offset: 0x1050 */ - __IO uint32_t CRBAR; /*!< Ethernet DMA current receive buffer address register, Address offset: 0x1054 */ -} ETH_DMA_Typedef; -/** - * @brief External Interrupt/Event Controller - */ -typedef struct { - __IO uint32_t IER; /*!<EXTI Interrupt enable register, Address offset: 0x00 */ - __IO uint32_t EER; /*!<EXTI Event enable register, Address offset: 0x04 */ - __IO uint32_t RTE; /*!<EXTI Rising edge trigger enable register, Address offset: 0x08 */ - __IO uint32_t FTE; /*!<EXTI Falling edge trigger enable register, Address offset: 0x0C */ - __IO uint32_t SIE; /*!<EXTI Software interrupt event register, Address offset: 0x10 */ - __IO uint32_t PD; /*!<EXTI Pending register, Address offset: 0x14 */ -} EXTI_TypeDef; - - -/** - * @brief FMC Registers - */ -typedef struct { - __IO uint32_t RESR; /*!<FMC access control register, Address offset: 0x00 */ - __IO uint32_t UKEYR; /*!<FMC key register, Address offset: 0x04 */ - __IO uint32_t OBKEYR; /*!<FMC OBKEYR register, Address offset: 0x08 */ - __IO uint32_t CSR; /*!<FMC status register, Address offset: 0x0C */ - __IO uint32_t CMR; /*!<FMC control register, Address offset: 0x10 */ - __IO uint32_t AR; /*!<FMC address register, Address offset: 0x14 */ - __IO uint32_t RESERVED; /*!< Reserved, 0x18 */ - __IO uint32_t OPTR; /*!<FMC option bytes register, Address offset: 0x1C */ - __IO uint32_t WPR; /*!<FMC option bytes register, Address offset: 0x20 */ - uint32_t RESERVED1[8]; - __IO uint32_t UKEYR2; - uint32_t RESERVED2; - __IO uint32_t CSR2; - __IO uint32_t CMR2; - __IO uint32_t AR2; - uint32_t RESERVED3[41]; - __IO uint32_t WSCR; - __IO uint32_t RES_ID1; - __IO uint32_t RES_ID2; - -} FMC_TypeDef; - -/** - * @brief Option Bytes Registers - */ -typedef struct { - __IO uint16_t RDP; /*!<FMC option byte Read protection, Address offset: 0x00 */ - __IO uint16_t USER; /*!<FMC option byte user options, Address offset: 0x02 */ - uint16_t RESERVED0; /*!< Reserved, 0x04 */ - uint16_t RESERVED1; /*!< Reserved, 0x06 */ - __IO uint16_t WRP0; /*!<FMC option byte write protection 0, Address offset: 0x08 */ - __IO uint16_t WRP1; /*!<FMC option byte write protection 1, Address offset: 0x0C */ - __IO uint16_t WRP2; /*!<FMC option byte write protection 2, Address offset: 0x10 */ - __IO uint16_t WRP3; /*!<FMC option byte write protection 3, Address offset: 0x14 */ -} OB_TypeDef; -/** - * @brief External Memory Controller Bank1 - */ -typedef struct { - __IO uint32_t SCTLR1; - __IO uint32_t STR1; - __IO uint32_t SCTLR2; - __IO uint32_t STR2; - __IO uint32_t SCTLR3; - __IO uint32_t STR3; - __IO uint32_t SCTLR4; - __IO uint32_t STR4; -} EXMC_Bank1_TypeDef; - -/** - * @brief External Memory Controller Bank1_WT - */ -typedef struct { - __IO uint32_t SWTR1; - uint32_t RESERVED0; - __IO uint32_t SWTR2; - uint32_t RESERVED1; - __IO uint32_t SWTR3; - uint32_t RESERVED2; - __IO uint32_t SWTR4; -} EXMC_Bank1_WT_TypeDef; - -/** - * @brief External Memory Controller Bank2 - */ -typedef struct { - __IO uint32_t CTLR2; - __IO uint32_t SIR2; - __IO uint32_t COMTR2; - __IO uint32_t ATTR2; - uint32_t RESERVED; - __IO uint32_t ECCR2; -} EXMC_Bank2_TypeDef; - -/** - * @brief External Memory Controller Bank3 - */ -typedef struct { - __IO uint32_t CTLR3; - __IO uint32_t SIR3; - __IO uint32_t COMTR3; - __IO uint32_t ATTR3; - uint32_t RESERVED; - __IO uint32_t ECCR3; -} EXMC_Bank3_TypeDef; - -/** - * @brief External Memory Controller Bank4 - */ -typedef struct { - __IO uint32_t CTLR4; - __IO uint32_t SIR4; - __IO uint32_t COMTR4; - __IO uint32_t ATTR4; - __IO uint32_t IOTR4; -} EXMC_Bank4_TypeDef; - -typedef struct { - __IO uint32_t CTLR1; - __IO uint32_t CTLR2; - __IO uint32_t DIR; - __IO uint32_t DOR; - __IO uint32_t BOR; - __IO uint32_t BCR; - __IO uint32_t LOCKR; -} GPIO_TypeDef; - - -typedef struct { - __IO uint32_t AFIO_EVR; - __IO uint32_t AFIO_PCFR1; - __IO uint32_t AFIO_ESSR1; - __IO uint32_t AFIO_ESSR2; - __IO uint32_t AFIO_ESSR3; - __IO uint32_t AFIO_ESSR4; - uint32_t RESERVED0; - __IO uint32_t AFIO_PCFR2; -} AFIO_TypeDef; - - -/** - * @brief Inter Integrated Circuit Interface - */ -typedef struct { - __IO uint16_t CTLR1; - uint16_t RESERVED0; - __IO uint16_t CTLR2; - uint16_t RESERVED1; - __IO uint16_t AR1; - uint16_t RESERVED2; - __IO uint16_t AR2; - uint16_t RESERVED3; - __IO uint16_t DTR; - uint16_t RESERVED4; - __IO uint16_t STR1; - uint16_t RESERVED5; - __IO uint16_t STR2; - uint16_t RESERVED6; - __IO uint16_t CLKR; - uint16_t RESERVED7; - __IO uint16_t RTR; - uint16_t RESERVED8; -} I2C_TypeDef; - - -/** - * @brief Independent WATCHDOG - */ -typedef struct { - __IO uint32_t CTLR; /*!< IWDG Key register, Address offset: 0x00 */ - __IO uint32_t PSR; /*!< IWDG Prescaler register, Address offset: 0x04 */ - __IO uint32_t RLDR; /*!< IWDG Reload register, Address offset: 0x08 */ - __IO uint32_t STR; /*!< IWDG Status register, Address offset: 0x0C */ -} IWDG_TypeDef; - -/** - * @brief Power Control - */ -typedef struct { - __IO uint32_t CTLR; /*!< PWR power control register, Address offset: 0x00 */ - __IO uint32_t STR; /*!< PWR power status register, Address offset: 0x04 */ -} PWR_TypeDef; - -/** - * @brief Reset and Clock Control - */ -/** - * @brief Reset and Clock Control - */ - -typedef struct { - __IO uint32_t GCCR; /*!< RCC clock control register, Address offset: 0x00 */ - __IO uint32_t GCFGR; /*!< RCC clock configuration register, Address offset: 0x04 */ - __IO uint32_t GCIR; /*!< RCC clock interrupt register, Address offset: 0x08 */ - __IO uint32_t APB2RCR; /*!< RCC APB2 peripheral reset register, Address offset: 0x0C */ - __IO uint32_t APB1RCR; /*!< RCC APB1 peripheral reset register, Address offset: 0x10 */ - __IO uint32_t AHBCCR; /*!< RCC AHB peripheral clock register, Address offset: 0x14 */ - __IO uint32_t APB2CCR; /*!< RCC APB2 peripheral clock enable register, Address offset: 0x18 */ - __IO uint32_t APB1CCR; /*!< RCC APB1 peripheral clock enable register, Address offset: 0x1C */ - __IO uint32_t BDCR; /*!< RCC Backup domain control register, Address offset: 0x20 */ - __IO uint32_t GCSR; /*!< RCC clock control & status register, Address offset: 0x24 */ -#ifdef GD32F10X_CL - __IO uint32_t AHBRCR; /*!< RCC AHB peripheral reset register, Address offset: 0x28 */ - __IO uint32_t GCFGR2; /*!< RCC clock configuration register 2, Address offset: 0x2C */ - __IO uint32_t RESERVED[ 1 ]; - __IO uint32_t RCC_DEEPSLEEP_VC; /*!< RCC deep-sleep mode voltage register , Address offset: 0x34 */ -#else - __IO uint32_t RESERVED[ 3 ]; - __IO uint32_t RCC_DEEPSLEEP_VC; /*!< RCC deep-sleep mode voltage register , Address offset: 0x34 */ -#endif /* GD32F10X_CL */ - -} RCC_TypeDef; - -/** - * @brief Real-Time Clock - */ -typedef struct { - __IO uint16_t CTLR1; /*!< RTC Control register1, Address offset: 0x00 */ - uint16_t RESERVED0; - __IO uint16_t CTLR2; /*!< RTC Control register2, Address offset: 0x04 */ - uint16_t RESERVED1; - __IO uint16_t PLR1; /*!< RTC Prescaler Load register1, Address offset: 0x08 */ - uint16_t RESERVED2; - __IO uint16_t PLR2; /*!< RTC Prescaler Load register2, Address offset: 0x0C */ - uint16_t RESERVED3; - __IO uint16_t PREDIV1; /*!< RTC Prescaler Divider register1, Address offset: 0x10 */ - uint16_t RESERVED4; - __IO uint16_t PREDIV2; /*!< RTC Prescaler Divider register2, Address offset: 0x14 */ - uint16_t RESERVED5; - __IO uint16_t CNT1; /*!< RTC Counter register1, Address offset: 0x18 */ - uint16_t RESERVED6; - __IO uint16_t CNT2; /*!< RTC Counter register2, Address offset: 0x1C */ - uint16_t RESERVED7; - __IO uint16_t ALRMR1; /*!< RTC Alarm register1, Address offset: 0x20 */ - uint16_t RESERVED8; - __IO uint16_t ALRMR2; /*!< RTC Alarm register2, Address offset: 0x24 */ - uint16_t RESERVED9; -} RTC_TypeDef; -/** - * @brief SD host Interface - */ - -typedef struct { - __IO uint32_t POWER; - __IO uint32_t CLKCTLR; - __IO uint32_t PARA; - __IO uint32_t CMD; - __I uint32_t RESPCMD; - __I uint32_t RESP1; - __I uint32_t RESP2; - __I uint32_t RESP3; - __I uint32_t RESP4; - __IO uint32_t DTTR; - __IO uint32_t DTLEN; - __IO uint32_t DTCTLR; - __I uint32_t DTCNT; - __I uint32_t STR; - __IO uint32_t ICR; - __IO uint32_t IER; - uint32_t RESERVED0[2]; - __I uint32_t FIFOCNT; - uint32_t RESERVED1[13]; - __IO uint32_t FIFO; -} SDIO_TypeDef; -/** - * @brief Serial Peripheral Interface - */ -typedef struct { - __IO uint16_t CTLR1; /*!< SPI Control register 1 (not used in I2S mode), Address offset: 0x00 */ - uint16_t RESERVED0; /*!< Reserved, 0x02 */ - __IO uint16_t CTLR2; /*!< SPI Control register 2, Address offset: 0x04 */ - uint16_t RESERVED1; /*!< Reserved, 0x06 */ - __IO uint16_t STR; /*!< SPI Status register, Address offset: 0x08 */ - uint16_t RESERVED2; /*!< Reserved, 0x0A */ - __IO uint16_t DTR; /*!< SPI data register, Address offset: 0x0C */ - uint16_t RESERVED3; /*!< Reserved, 0x0E */ - __IO uint16_t CPR; /*!< SPI CRC polynomial register (not used in I2S mode), Address offset: 0x10 */ - uint16_t RESERVED4; /*!< Reserved, 0x12 */ - __IO uint16_t RCR; /*!< SPI Rx CRC register (not used in I2S mode), Address offset: 0x14 */ - uint16_t RESERVED5; /*!< Reserved, 0x16 */ - __IO uint16_t TCR; /*!< SPI Tx CRC register (not used in I2S mode), Address offset: 0x18 */ - uint16_t RESERVED6; /*!< Reserved, 0x1A */ - __IO uint16_t I2SCTLR; /*!< SPI_I2S configuration register, Address offset: 0x1C */ - uint16_t RESERVED7; /*!< Reserved, 0x1E */ - __IO uint16_t I2SCKP; /*!< SPI_I2S prescaler register, Address offset: 0x20 */ - uint16_t RESERVED8; /*!< Reserved, 0x22 */ -} SPI_TypeDef; - -/** - * @brief TIMER - */ -typedef struct { - __IO uint16_t CTLR1; /*!< TIMER control register 1, Address offset: 0x00 */ - uint16_t RESERVED0; /*!< Reserved, 0x02 */ - __IO uint16_t CTLR2; /*!< TIMER control register 2, Address offset: 0x04 */ - uint16_t RESERVED1; /*!< Reserved, 0x06 */ - __IO uint16_t SMC; /*!< TIMER slave Mode Control register, Address offset: 0x08 */ - uint16_t RESERVED2; /*!< Reserved, 0x0A */ - __IO uint16_t DIE; /*!< TIMER DMA/interrupt enable register, Address offset: 0x0C */ - uint16_t RESERVED3; /*!< Reserved, 0x0E */ - __IO uint16_t STR; /*!< TIMER status register, Address offset: 0x10 */ - uint16_t RESERVED4; /*!< Reserved, 0x12 */ - __IO uint16_t EVG; /*!< TIMER event generation register, Address offset: 0x14 */ - uint16_t RESERVED5; /*!< Reserved, 0x16 */ - __IO uint16_t CHCTLR1; /*!< TIMER capture/compare mode register 1, Address offset: 0x18 */ - uint16_t RESERVED6; /*!< Reserved, 0x1A */ - __IO uint16_t CHCTLR2; /*!< TIMER capture/compare mode register 2, Address offset: 0x1C */ - uint16_t RESERVED7; /*!< Reserved, 0x1E */ - __IO uint16_t CHE; /*!< TIMER capture/compare enable register, Address offset: 0x20 */ - uint16_t RESERVED8; /*!< Reserved, 0x22 */ - __IO uint16_t CNT; /*!< TIMER counter register, Address offset: 0x24 */ - uint16_t RESERVED9; /*!< Reserved, 0x26 */ - __IO uint16_t PSC; /*!< TIMER prescaler register, Address offset: 0x28 */ - uint16_t RESERVED10; /*!< Reserved, 0x2A */ - __IO uint16_t CARL; /*!< TIMER auto-reload register, Address offset: 0x2C */ - uint16_t RESERVED11; /*!< Reserved, 0x2E */ - __IO uint16_t CREP; /*!< TIMER repetition counter register, Address offset: 0x30 */ - uint16_t RESERVED12; /*!< Reserved, 0x32 */ - __IO uint16_t CHCC1; /*!< TIMER capture/compare register 1, Address offset: 0x34 */ - uint16_t RESERVED13; /*!< Reserved, 0x36 */ - __IO uint16_t CHCC2; /*!< TIMER capture/compare register 2, Address offset: 0x38 */ - uint16_t RESERVED14; /*!< Reserved, 0x3A */ - __IO uint16_t CHCC3; /*!< TIMER capture/compare register 3, Address offset: 0x3C */ - uint16_t RESERVED15; /*!< Reserved, 0x3E */ - __IO uint16_t CHCC4; /*!< TIMER capture/compare register 4, Address offset: 0x40 */ - uint16_t RESERVED16; /*!< Reserved, 0x42 */ - __IO uint16_t BKDT; /*!< TIMER break and dead-time register, Address offset: 0x44 */ - uint16_t RESERVED17; /*!< Reserved, 0x46 */ - __IO uint16_t DCTLR; /*!< TIMER DMA control register, Address offset: 0x48 */ - uint16_t RESERVED18; /*!< Reserved, 0x4A */ - __IO uint16_t DTRSF; /*!< TIMER DMA address for full transfer register, Address offset: 0x4C */ - uint16_t RESERVED19; /*!< Reserved, 0x4E */ -} TIMER_TypeDef; - - -typedef struct { - __IO uint16_t STR; - uint16_t RESERVED0; - __IO uint16_t DR; - uint16_t RESERVED1; - __IO uint16_t BRR; - uint16_t RESERVED2; - __IO uint16_t CTLR1; - uint16_t RESERVED3; - __IO uint16_t CTLR2; - uint16_t RESERVED4; - __IO uint16_t CTLR3; - uint16_t RESERVED5; - __IO uint16_t GTPR; - uint16_t RESERVED6; -} USART_TypeDef; - -/** - * @brief Window WATCHDOG - */ -typedef struct { - __IO uint32_t CTLR; /*!< WWDG Control register, Address offset: 0x00 */ - __IO uint32_t CFR; /*!< WWDG Configuration register, Address offset: 0x04 */ - __IO uint32_t STR; /*!< WWDG Status register, Address offset: 0x08 */ -} WWDG_TypeDef; - -/** @addtogroup Peripheral_memory_map - * @{ - */ - - -#define FLASH_BASE ((uint32_t)0x08000000) /*!< FLASH base address in the alias region */ -#define SRAM_BASE ((uint32_t)0x20000000) /*!< SRAM base address in the alias region */ -#define PERIPH_BASE ((uint32_t)0x40000000) /*!< Peripheral base address in the alias region */ - -#define SRAM_BB_BASE ((uint32_t)0x22000000) /*!< SRAM base address in the bit-band region */ -#define PERIPH_BB_BASE ((uint32_t)0x42000000) /*!< Peripheral base address in the bit-band region */ - -#define EXMC_R_BASE ((uint32_t)0xA0000000) /*!< EXMC registers base address */ - -/*!< Peripheral memory map */ -#define APB1PERIPH_BASE PERIPH_BASE -#define APB2PERIPH_BASE (PERIPH_BASE + 0x10000) -#define AHBPERIPH_BASE (PERIPH_BASE + 0x20000) - -#define TIMER1_BASE (APB1PERIPH_BASE + 0x0000) -#define TIMER2_BASE (APB1PERIPH_BASE + 0x0400) -#define TIMER3_BASE (APB1PERIPH_BASE + 0x0800) -#define TIMER4_BASE (APB1PERIPH_BASE + 0x0C00) -#define TIMER5_BASE (APB1PERIPH_BASE + 0x1000) -#define TIMER6_BASE (APB1PERIPH_BASE + 0x1400) -#define TIMER11_BASE (APB1PERIPH_BASE + 0x1800) -#define TIMER12_BASE (APB1PERIPH_BASE + 0x1C00) -#define TIMER13_BASE (APB1PERIPH_BASE + 0x2000) -#define RTC_BASE (APB1PERIPH_BASE + 0x2800) -#define WWDG_BASE (APB1PERIPH_BASE + 0x2C00) -#define IWDG_BASE (APB1PERIPH_BASE + 0x3000) -#define SPI2_BASE (APB1PERIPH_BASE + 0x3800) -#define SPI3_BASE (APB1PERIPH_BASE + 0x3C00) -#define USART1_BASE (APB1PERIPH_BASE + 0x4400) -#define USART2_BASE (APB1PERIPH_BASE + 0x4800) -#define UART3_BASE (APB1PERIPH_BASE + 0x4C00) -#define UART4_BASE (APB1PERIPH_BASE + 0x5000) -#define I2C1_BASE (APB1PERIPH_BASE + 0x5400) -#define I2C2_BASE (APB1PERIPH_BASE + 0x5800) -#define CAN1_BASE (APB1PERIPH_BASE + 0x6400) -#define CAN2_BASE (APB1PERIPH_BASE + 0x6800) -#define BKP_BASE (APB1PERIPH_BASE + 0x6C00) -#define PWR_BASE (APB1PERIPH_BASE + 0x7000) -#define DAC_BASE (APB1PERIPH_BASE + 0x7400) -#define AFIO_BASE (APB2PERIPH_BASE + 0x0000) -#define EXTI_BASE (APB2PERIPH_BASE + 0x0400) -#define GPIOA_BASE (APB2PERIPH_BASE + 0x0800) -#define GPIOB_BASE (APB2PERIPH_BASE + 0x0C00) -#define GPIOC_BASE (APB2PERIPH_BASE + 0x1000) -#define GPIOD_BASE (APB2PERIPH_BASE + 0x1400) -#define GPIOE_BASE (APB2PERIPH_BASE + 0x1800) -#define GPIOF_BASE (APB2PERIPH_BASE + 0x1C00) -#define GPIOG_BASE (APB2PERIPH_BASE + 0x2000) -#define ADC0_BASE (APB2PERIPH_BASE + 0x2400) -#define ADC1_BASE (APB2PERIPH_BASE + 0x2800) -#define TIMER0_BASE (APB2PERIPH_BASE + 0x2C00) -#define SPI1_BASE (APB2PERIPH_BASE + 0x3000) -#define TIMER7_BASE (APB2PERIPH_BASE + 0x3400) -#define USART0_BASE (APB2PERIPH_BASE + 0x3800) -#define ADC3_BASE (APB2PERIPH_BASE + 0x3C00) -#define TIMER14_BASE (APB2PERIPH_BASE + 0x4000) -#define TIMER15_BASE (APB2PERIPH_BASE + 0x4400) -#define TIMER16_BASE (APB2PERIPH_BASE + 0x4800) -#define TIMER8_BASE (APB2PERIPH_BASE + 0x4C00) -#define TIMER9_BASE (APB2PERIPH_BASE + 0x5000) -#define TIMER10_BASE (APB2PERIPH_BASE + 0x5400) - -#define SDIO_BASE (PERIPH_BASE + 0x18000) - -#define DMA1_BASE (AHBPERIPH_BASE + 0x0000) -#define DMA1_CHANNEL1_BASE (AHBPERIPH_BASE + 0x0008) -#define DMA1_CHANNEL2_BASE (AHBPERIPH_BASE + 0x001C) -#define DMA1_CHANNEL3_BASE (AHBPERIPH_BASE + 0x0030) -#define DMA1_CHANNEL4_BASE (AHBPERIPH_BASE + 0x0044) -#define DMA1_CHANNEL5_BASE (AHBPERIPH_BASE + 0x0058) -#define DMA1_CHANNEL6_BASE (AHBPERIPH_BASE + 0x006C) -#define DMA1_CHANNEL7_BASE (AHBPERIPH_BASE + 0x0080) -#define DMA2_BASE (AHBPERIPH_BASE + 0x0400) -#define DMA2_CHANNEL1_BASE (AHBPERIPH_BASE + 0x0408) -#define DMA2_CHANNEL2_BASE (AHBPERIPH_BASE + 0x041C) -#define DMA2_CHANNEL3_BASE (AHBPERIPH_BASE + 0x0430) -#define DMA2_CHANNEL4_BASE (AHBPERIPH_BASE + 0x0444) -#define DMA2_CHANNEL5_BASE (AHBPERIPH_BASE + 0x0458) -#define RCC_BASE (AHBPERIPH_BASE + 0x1000) -#define RCU_BASE (AHBPERIPH_BASE + 0x1000) -#define CRC_BASE (AHBPERIPH_BASE + 0x3000) - -#define FMC_R_BASE (AHBPERIPH_BASE + 0x2000) /*!< FMC registers base address */ -#define OB_BASE ((uint32_t)0x1FFFF800) /*!< FMC Option Bytes base address */ - -#define ETH_BASE (AHBPERIPH_BASE + 0x8000) -#define ETH_MAC_BASE (ETH_BASE) -#define ETH_MSC_BASE (ETH_BASE + 0x0100) -#define ETH_PTP_BASE (ETH_BASE + 0x0700) -#define ETH_DMA_BASE (ETH_BASE + 0x1000) - -#define EXMC_BANK1_R_BASE (EXMC_R_BASE + 0x0000) /*!< EXMC Bank1 registers base address */ -#define EXMC_BANK1_WT_R_BASE (EXMC_R_BASE + 0x0104) /*!< EXMC Bank1WT registers base address */ -#define EXMC_BANK2_R_BASE (EXMC_R_BASE + 0x0060) /*!< EXMC Bank2 registers base address */ -#define EXMC_BANK3_R_BASE (EXMC_R_BASE + 0x0080) /*!< EXMC Bank3 registers base address */ -#define EXMC_BANK4_R_BASE (EXMC_R_BASE + 0x00A0) /*!< EXMC Bank4 registers base address */ - -#define MCUDBG_BASE ((uint32_t)0xE0042000) /*!< Debug MCU registers base address */ - -/** - * @} - */ - -/** @addtogroup Peripheral_declaration - * @{ - */ - -#define TIMER1 ((TIMER_TypeDef *) TIMER1_BASE) -#define TIMER2 ((TIMER_TypeDef *) TIMER2_BASE) -#define TIMER3 ((TIMER_TypeDef *) TIMER3_BASE) -#define TIMER4 ((TIMER_TypeDef *) TIMER4_BASE) -#define TIMER5 ((TIMER_TypeDef *) TIMER5_BASE) -#define TIMER6 ((TIMER_TypeDef *) TIMER6_BASE) -#define TIMER11 ((TIMER_TypeDef *) TIMER11_BASE) -#define TIMER12 ((TIMER_TypeDef *) TIMER12_BASE) -#define TIMER13 ((TIMER_TypeDef *) TIMER13_BASE) -#define RTC ((RTC_TypeDef *) RTC_BASE) -#define WWDG ((WWDG_TypeDef *) WWDG_BASE) -#define IWDG ((IWDG_TypeDef *) IWDG_BASE) -#define SPI2 ((SPI_TypeDef *) SPI2_BASE) -#define SPI3 ((SPI_TypeDef *) SPI3_BASE) -#define USART1 ((USART_TypeDef *) USART1_BASE) -#define USART2 ((USART_TypeDef *) USART2_BASE) -#define UART3 ((USART_TypeDef *) UART3_BASE) -#define UART4 ((USART_TypeDef *) UART4_BASE) -#define I2C1 ((I2C_TypeDef *) I2C1_BASE) -#define I2C2 ((I2C_TypeDef *) I2C2_BASE) -#define CAN1 ((CAN_TypeDef *) CAN1_BASE) -#define CAN2 ((CAN_TypeDef *) CAN2_BASE) -#define BKP ((BKP_TypeDef *) BKP_BASE) -#define PWR ((PWR_TypeDef *) PWR_BASE) -#define DAC ((DAC_TypeDef *) DAC_BASE) -#define CEC ((CEC_TypeDef *) CEC_BASE) -#define AFIO ((AFIO_TypeDef *) AFIO_BASE) -#define EXTI ((EXTI_TypeDef *) EXTI_BASE) -#define GPIOA ((GPIO_TypeDef *) GPIOA_BASE) -#define GPIOB ((GPIO_TypeDef *) GPIOB_BASE) -#define GPIOC ((GPIO_TypeDef *) GPIOC_BASE) -#define GPIOD ((GPIO_TypeDef *) GPIOD_BASE) -#define GPIOE ((GPIO_TypeDef *) GPIOE_BASE) -#define GPIOF ((GPIO_TypeDef *) GPIOF_BASE) -#define GPIOG ((GPIO_TypeDef *) GPIOG_BASE) -#define ADC0 ((ADC_TypeDef *) ADC0_BASE) -#define ADC1 ((ADC_TypeDef *) ADC1_BASE) -#define TIMER0 ((TIMER_TypeDef *) TIMER0_BASE) -#define SPI1 ((SPI_TypeDef *) SPI1_BASE) -#define TIMER7 ((TIMER_TypeDef *) TIMER7_BASE) -#define USART0 ((USART_TypeDef *) USART0_BASE) -#define USART1 ((USART_TypeDef *) USART1_BASE) -#define ADC3 ((ADC_TypeDef *) ADC3_BASE) -#define TIMER14 ((TIMER_TypeDef *) TIMER14_BASE) -#define TIMER15 ((TIMER_TypeDef *) TIMER15_BASE) -#define TIMER16 ((TIMER_TypeDef *) TIMER16_BASE) -#define TIMER8 ((TIMER_TypeDef *) TIMER8_BASE) -#define TIMER9 ((TIMER_TypeDef *) TIMER9_BASE) -#define TIMER10 ((TIMER_TypeDef *) TIMER10_BASE) -#define SDIO ((SDIO_TypeDef *) SDIO_BASE) -#define DMA1 ((DMA_TypeDef *) DMA1_BASE) -#define DMA2 ((DMA_TypeDef *) DMA2_BASE) -#define DMA1_CHANNEL1 ((DMA_Channel_TypeDef *) DMA1_CHANNEL1_BASE) -#define DMA1_CHANNEL2 ((DMA_Channel_TypeDef *) DMA1_CHANNEL2_BASE) -#define DMA1_CHANNEL3 ((DMA_Channel_TypeDef *) DMA1_CHANNEL3_BASE) -#define DMA1_CHANNEL4 ((DMA_Channel_TypeDef *) DMA1_CHANNEL4_BASE) -#define DMA1_CHANNEL5 ((DMA_Channel_TypeDef *) DMA1_CHANNEL5_BASE) -#define DMA1_CHANNEL6 ((DMA_Channel_TypeDef *) DMA1_CHANNEL6_BASE) -#define DMA1_CHANNEL7 ((DMA_Channel_TypeDef *) DMA1_CHANNEL7_BASE) -#define DMA2_CHANNEL1 ((DMA_Channel_TypeDef *) DMA2_CHANNEL1_BASE) -#define DMA2_CHANNEL2 ((DMA_Channel_TypeDef *) DMA2_CHANNEL2_BASE) -#define DMA2_CHANNEL3 ((DMA_Channel_TypeDef *) DMA2_CHANNEL3_BASE) -#define DMA2_CHANNEL4 ((DMA_Channel_TypeDef *) DMA2_CHANNEL4_BASE) -#define DMA2_CHANNEL5 ((DMA_Channel_TypeDef *) DMA2_CHANNEL5_BASE) -#define RCC ((RCC_TypeDef *) RCC_BASE) -#define CRC ((CRC_TypeDef *) CRC_BASE) -#define FMC ((FMC_TypeDef *) FMC_R_BASE) -#define OB ((OB_TypeDef *) OB_BASE) -#define EXMC_BANK1 ((EXMC_Bank1_TypeDef *) EXMC_BANK1_R_BASE) -#define EXMC_BANK1_WT ((EXMC_Bank1_WT_TypeDef *) EXMC_BANK1_WT_R_BASE) -#define EXMC_BANK2 ((EXMC_Bank2_TypeDef *) EXMC_BANK2_R_BASE) -#define EXMC_BANK3 ((EXMC_Bank3_TypeDef *) EXMC_BANK3_R_BASE) -#define EXMC_BANK4 ((EXMC_Bank4_TypeDef *) EXMC_BANK4_R_BASE) -#define MCUDBG ((MCUDBG_TypeDef *) MCUDBG_BASE) -#define ETH_MAC ((ETH_MAC_TypeDef *) ETH_MAC_BASE) -#define ETH_MSC ((ETH_MSC_TypeDef *) ETH_MSC_BASE) -#define ETH_PTP ((ETH_PTP_TypeDef *) ETH_PTP_BASE) -#define ETH_DMA ((ETH_DMA_Typedef *) ETH_DMA_BASE) -/** - * @} - */ - -/** @addtogroup Exported_constants - * @{ - */ - -/** @addtogroup Peripheral_Registers_Bits_Definition -* @{ -*/ - -/******************************************************************************/ -/* Peripheral Registers Bits Definition */ -/******************************************************************************/ -/******************************************************************************/ -/* */ -/* Analog to Digital Converter */ -/* */ -/******************************************************************************/ - -/******************** Bit definition for ADC_STR register ********************/ -#define ADC_STR_AWE ((uint8_t)0x01) /*!< Analog watchdog flag */ -#define ADC_STR_EOC ((uint8_t)0x02) /*!< End of conversion */ -#define ADC_STR_EOIC ((uint8_t)0x04) /*!< Injected channel end of conversion */ -#define ADC_STR_STIC ((uint8_t)0x08) /*!< Injected channel Start flag */ -#define ADC_STR_STRC ((uint8_t)0x10) /*!< Regular channel Start flag */ - -/******************* Bit definition for ADC_CTLR1 register ********************/ -#define ADC_CTLR1_AWCS ((uint32_t)0x0000001F) /*!< AWCS[4:0] bits (Analog watchdog channel select bits) */ -#define ADC_CTLR1_AWCS_0 ((uint32_t)0x00000001) /*!< Bit 0 */ -#define ADC_CTLR1_AWCS_1 ((uint32_t)0x00000002) /*!< Bit 1 */ -#define ADC_CTLR1_AWCS_2 ((uint32_t)0x00000004) /*!< Bit 2 */ -#define ADC_CTLR1_AWCS_3 ((uint32_t)0x00000008) /*!< Bit 3 */ -#define ADC_CTLR1_AWCS_4 ((uint32_t)0x00000010) /*!< Bit 4 */ - -#define ADC_CTLR1_EOCIE ((uint32_t)0x00000020) /*!< Interrupt enable for EOC */ -#define ADC_CTLR1_AWEIE ((uint32_t)0x00000040) /*!< Analog Watchdog interrupt enable */ -#define ADC_CTLR1_EOICIE ((uint32_t)0x00000080) /*!< Interrupt enable for injected channels */ -#define ADC_CTLR1_SM ((uint32_t)0x00000100) /*!< Scan mode */ -#define ADC_CTLR1_AWSSM ((uint32_t)0x00000200) /*!< Enable the watchdog on a single channel in scan mode */ -#define ADC_CTLR1_ICA ((uint32_t)0x00000400) /*!< Automatic injected group conversion */ -#define ADC_CTLR1_DISRC ((uint32_t)0x00000800) /*!< Discontinuous mode on regular channels */ -#define ADC_CTLR1_DISIC ((uint32_t)0x00001000) /*!< Discontinuous mode on injected channels */ - -#define ADC_CTLR1_DISNUM ((uint32_t)0x0000E000) /*!< DISNUM[2:0] bits (Discontinuous mode channel count) */ -#define ADC_CTLR1_DISNUM_0 ((uint32_t)0x00002000) /*!< Bit 0 */ -#define ADC_CTLR1_DISNUM_1 ((uint32_t)0x00004000) /*!< Bit 1 */ -#define ADC_CTLR1_DISNUM_2 ((uint32_t)0x00008000) /*!< Bit 2 */ - -#define ADC_CTLR1_AWIEN ((uint32_t)0x00400000) /*!< Analog watchdog enable on injected channels */ -#define ADC_CTLR1_AWREN ((uint32_t)0x00800000) /*!< Analog watchdog enable on regular channels */ - -/******************* Bit definition for ADC_CTLR2 register ********************/ -#define ADC_CTLR2_ADCON ((uint32_t)0x00000001) /*!< A/D Converter ON / OFF */ -#define ADC_CTLR2_CTN ((uint32_t)0x00000002) /*!< Continuous Conversion */ -#define ADC_CTLR2_CLB ((uint32_t)0x00000004) /*!< A/D Calibration */ -#define ADC_CTLR2_RSTCLB ((uint32_t)0x00000008) /*!< Reset Calibration */ -#define ADC_CTLR2_DMA ((uint32_t)0x00000100) /*!< Direct Memory access mode */ -#define ADC_CTLR2_DAL ((uint32_t)0x00000800) /*!< Data Alignment */ - -#define ADC_CTLR2_ETSIC ((uint32_t)0x00007000) /*!< ETSIC[2:0] bits (External event select for injected group) */ -#define ADC_CTLR2_ETSIC_0 ((uint32_t)0x00001000) /*!< Bit 0 */ -#define ADC_CTLR2_ETSIC_1 ((uint32_t)0x00002000) /*!< Bit 1 */ -#define ADC_CTLR2_ETSIC_2 ((uint32_t)0x00004000) /*!< Bit 2 */ - -#define ADC_CTLR2_ETEIC ((uint32_t)0x00008000) /*!< External Trigger Conversion mode for injected channels */ - -#define ADC_CTLR2_ETSRC ((uint32_t)0x000E0000) /*!< ETSRC[2:0] bits (External Event Select for regular group) */ -#define ADC_CTLR2_ETSRC_0 ((uint32_t)0x00020000) /*!< Bit 0 */ -#define ADC_CTLR2_ETSRC_1 ((uint32_t)0x00040000) /*!< Bit 1 */ -#define ADC_CTLR2_ETSRC_2 ((uint32_t)0x00080000) /*!< Bit 2 */ - -#define ADC_CTLR2_ETERC ((uint32_t)0x00100000) /*!< External Trigger Conversion mode for regular channels */ -#define ADC_CTLR2_SWICST ((uint32_t)0x00200000) /*!< Start Conversion of injected channels */ -#define ADC_CTLR2_SWRCST ((uint32_t)0x00400000) /*!< Start Conversion of regular channels */ -#define ADC_CTLR2_TSVREN ((uint32_t)0x00800000) /*!< Temperature Sensor and VREFINT Enable */ -#define ADC_CTLR2_VBATEN ((uint32_t)0x00C00000) /*!< VBAT Enable */ -/****************** Bit definition for ADC_SPT1 register *******************/ -#define ADC_SPT1_SPT10 ((uint32_t)0x00000007) /*!< SPT10[2:0] bits (Channel 10 Sample time selection) */ -#define ADC_SPT1_SPT10_0 ((uint32_t)0x00000001) /*!< Bit 0 */ -#define ADC_SPT1_SPT10_1 ((uint32_t)0x00000002) /*!< Bit 1 */ -#define ADC_SPT1_SPT10_2 ((uint32_t)0x00000004) /*!< Bit 2 */ - -#define ADC_SPT1_SPT11 ((uint32_t)0x00000038) /*!< SPT11[2:0] bits (Channel 11 Sample time selection) */ -#define ADC_SPT1_SPT11_0 ((uint32_t)0x00000008) /*!< Bit 0 */ -#define ADC_SPT1_SPT11_1 ((uint32_t)0x00000010) /*!< Bit 1 */ -#define ADC_SPT1_SPT11_2 ((uint32_t)0x00000020) /*!< Bit 2 */ - -#define ADC_SPT1_SPT12 ((uint32_t)0x000001C0) /*!< SPT12[2:0] bits (Channel 12 Sample time selection) */ -#define ADC_SPT1_SPT12_0 ((uint32_t)0x00000040) /*!< Bit 0 */ -#define ADC_SPT1_SPT12_1 ((uint32_t)0x00000080) /*!< Bit 1 */ -#define ADC_SPT1_SPT12_2 ((uint32_t)0x00000100) /*!< Bit 2 */ - -#define ADC_SPT1_SPT13 ((uint32_t)0x00000E00) /*!< SPT13[2:0] bits (Channel 13 Sample time selection) */ -#define ADC_SPT1_SPT13_0 ((uint32_t)0x00000200) /*!< Bit 0 */ -#define ADC_SPT1_SPT13_1 ((uint32_t)0x00000400) /*!< Bit 1 */ -#define ADC_SPT1_SPT13_2 ((uint32_t)0x00000800) /*!< Bit 2 */ - -#define ADC_SPT1_SPT14 ((uint32_t)0x00007000) /*!< SPT14[2:0] bits (Channel 14 Sample time selection) */ -#define ADC_SPT1_SPT14_0 ((uint32_t)0x00001000) /*!< Bit 0 */ -#define ADC_SPT1_SPT14_1 ((uint32_t)0x00002000) /*!< Bit 1 */ -#define ADC_SPT1_SPT14_2 ((uint32_t)0x00004000) /*!< Bit 2 */ - -#define ADC_SPT1_SPT15 ((uint32_t)0x00038000) /*!< SPT15[2:0] bits (Channel 15 Sample time selection) */ -#define ADC_SPT1_SPT15_0 ((uint32_t)0x00008000) /*!< Bit 0 */ -#define ADC_SPT1_SPT15_1 ((uint32_t)0x00010000) /*!< Bit 1 */ -#define ADC_SPT1_SPT15_2 ((uint32_t)0x00020000) /*!< Bit 2 */ - -#define ADC_SPT1_SPT16 ((uint32_t)0x001C0000) /*!< SPT16[2:0] bits (Channel 16 Sample time selection) */ -#define ADC_SPT1_SPT16_0 ((uint32_t)0x00040000) /*!< Bit 0 */ -#define ADC_SPT1_SPT16_1 ((uint32_t)0x00080000) /*!< Bit 1 */ -#define ADC_SPT1_SPT16_2 ((uint32_t)0x00100000) /*!< Bit 2 */ - -#define ADC_SPT1_SPT17 ((uint32_t)0x00E00000) /*!< SPT17[2:0] bits (Channel 17 Sample time selection) */ -#define ADC_SPT1_SPT17_0 ((uint32_t)0x00200000) /*!< Bit 0 */ -#define ADC_SPT1_SPT17_1 ((uint32_t)0x00400000) /*!< Bit 1 */ -#define ADC_SPT1_SPT17_2 ((uint32_t)0x00800000) /*!< Bit 2 */ - -/****************** Bit definition for ADC_SPT2 register *******************/ -#define ADC_SPT2_SPT0 ((uint32_t)0x00000007) /*!< SPT0[2:0] bits (Channel 0 Sample time selection) */ -#define ADC_SPT2_SPT0_0 ((uint32_t)0x00000001) /*!< Bit 0 */ -#define ADC_SPT2_SPT0_1 ((uint32_t)0x00000002) /*!< Bit 1 */ -#define ADC_SPT2_SPT0_2 ((uint32_t)0x00000004) /*!< Bit 2 */ - -#define ADC_SPT2_SPT1 ((uint32_t)0x00000038) /*!< SPT1[2:0] bits (Channel 1 Sample time selection) */ -#define ADC_SPT2_SPT1_0 ((uint32_t)0x00000008) /*!< Bit 0 */ -#define ADC_SPT2_SPT1_1 ((uint32_t)0x00000010) /*!< Bit 1 */ -#define ADC_SPT2_SPT1_2 ((uint32_t)0x00000020) /*!< Bit 2 */ - -#define ADC_SPT2_SPT2 ((uint32_t)0x000001C0) /*!< SPT2[2:0] bits (Channel 2 Sample time selection) */ -#define ADC_SPT2_SPT2_0 ((uint32_t)0x00000040) /*!< Bit 0 */ -#define ADC_SPT2_SPT2_1 ((uint32_t)0x00000080) /*!< Bit 1 */ -#define ADC_SPT2_SPT2_2 ((uint32_t)0x00000100) /*!< Bit 2 */ - -#define ADC_SPT2_SPT3 ((uint32_t)0x00000E00) /*!< SPT3[2:0] bits (Channel 3 Sample time selection) */ -#define ADC_SPT2_SPT3_0 ((uint32_t)0x00000200) /*!< Bit 0 */ -#define ADC_SPT2_SPT3_1 ((uint32_t)0x00000400) /*!< Bit 1 */ -#define ADC_SPT2_SPT3_2 ((uint32_t)0x00000800) /*!< Bit 2 */ - -#define ADC_SPT2_SPT4 ((uint32_t)0x00007000) /*!< SPT4[2:0] bits (Channel 4 Sample time selection) */ -#define ADC_SPT2_SPT4_0 ((uint32_t)0x00001000) /*!< Bit 0 */ -#define ADC_SPT2_SPT4_1 ((uint32_t)0x00002000) /*!< Bit 1 */ -#define ADC_SPT2_SPT4_2 ((uint32_t)0x00004000) /*!< Bit 2 */ - -#define ADC_SPT2_SPT5 ((uint32_t)0x00038000) /*!< SPT5[2:0] bits (Channel 5 Sample time selection) */ -#define ADC_SPT2_SPT5_0 ((uint32_t)0x00008000) /*!< Bit 0 */ -#define ADC_SPT2_SPT5_1 ((uint32_t)0x00010000) /*!< Bit 1 */ -#define ADC_SPT2_SPT5_2 ((uint32_t)0x00020000) /*!< Bit 2 */ - -#define ADC_SPT2_SPT6 ((uint32_t)0x001C0000) /*!< SPT6[2:0] bits (Channel 6 Sample time selection) */ -#define ADC_SPT2_SPT6_0 ((uint32_t)0x00040000) /*!< Bit 0 */ -#define ADC_SPT2_SPT6_1 ((uint32_t)0x00080000) /*!< Bit 1 */ -#define ADC_SPT2_SPT6_2 ((uint32_t)0x00100000) /*!< Bit 2 */ - -#define ADC_SPT2_SPT7 ((uint32_t)0x00E00000) /*!< SPT7[2:0] bits (Channel 7 Sample time selection) */ -#define ADC_SPT2_SPT7_0 ((uint32_t)0x00200000) /*!< Bit 0 */ -#define ADC_SPT2_SPT7_1 ((uint32_t)0x00400000) /*!< Bit 1 */ -#define ADC_SPT2_SPT7_2 ((uint32_t)0x00800000) /*!< Bit 2 */ - -#define ADC_SPT2_SPT8 ((uint32_t)0x07000000) /*!< SPT8[2:0] bits (Channel 8 Sample time selection) */ -#define ADC_SPT2_SPT8_0 ((uint32_t)0x01000000) /*!< Bit 0 */ -#define ADC_SPT2_SPT8_1 ((uint32_t)0x02000000) /*!< Bit 1 */ -#define ADC_SPT2_SPT8_2 ((uint32_t)0x04000000) /*!< Bit 2 */ - -#define ADC_SPT2_SPT9 ((uint32_t)0x38000000) /*!< SPT9[2:0] bits (Channel 9 Sample time selection) */ -#define ADC_SPT2_SPT9_0 ((uint32_t)0x08000000) /*!< Bit 0 */ -#define ADC_SPT2_SPT9_1 ((uint32_t)0x10000000) /*!< Bit 1 */ -#define ADC_SPT2_SPT9_2 ((uint32_t)0x20000000) /*!< Bit 2 */ - -/****************** Bit definition for ADC_ICOS1 register *******************/ -#define ADC_ICOS1_ICOS1 ((uint16_t)0x0FFF) /*!< Data offset for injected channel 1 */ - -/****************** Bit definition for ADC_ICOS2 register *******************/ -#define ADC_ICOS2_ICOS2 ((uint16_t)0x0FFF) /*!< Data offset for injected channel 2 */ - -/****************** Bit definition for ADC_ICOS3 register *******************/ -#define ADC_ICOS3_ICOS3 ((uint16_t)0x0FFF) /*!< Data offset for injected channel 3 */ - -/****************** Bit definition for ADC_ICOS4 register *******************/ -#define ADC_ICOS4_ICOS4 ((uint16_t)0x0FFF) /*!< Data offset for injected channel 4 */ - -/******************* Bit definition for ADC_AWHT register ********************/ -#define ADC_AWHT_AWHT ((uint16_t)0x0FFF) /*!< Analog watchdog high threshold */ - -/******************* Bit definition for ADC_AWLT register ********************/ -#define ADC_AWLT_AWLT ((uint16_t)0x0FFF) /*!< Analog watchdog low threshold */ - -/******************* Bit definition for ADC_RSQ1 register *******************/ -#define ADC_RSQ1_RSQ13 ((uint32_t)0x0000001F) /*!< RSQ13[4:0] bits (13th conversion in regular sequence) */ -#define ADC_RSQ1_RSQ13_0 ((uint32_t)0x00000001) /*!< Bit 0 */ -#define ADC_RSQ1_RSQ13_1 ((uint32_t)0x00000002) /*!< Bit 1 */ -#define ADC_RSQ1_RSQ13_2 ((uint32_t)0x00000004) /*!< Bit 2 */ -#define ADC_RSQ1_RSQ13_3 ((uint32_t)0x00000008) /*!< Bit 3 */ -#define ADC_RSQ1_RSQ13_4 ((uint32_t)0x00000010) /*!< Bit 4 */ - -#define ADC_RSQ1_RSQ14 ((uint32_t)0x000003E0) /*!< RSQ14[4:0] bits (14th conversion in regular sequence) */ -#define ADC_RSQ1_RSQ14_0 ((uint32_t)0x00000020) /*!< Bit 0 */ -#define ADC_RSQ1_RSQ14_1 ((uint32_t)0x00000040) /*!< Bit 1 */ -#define ADC_RSQ1_RSQ14_2 ((uint32_t)0x00000080) /*!< Bit 2 */ -#define ADC_RSQ1_RSQ14_3 ((uint32_t)0x00000100) /*!< Bit 3 */ -#define ADC_RSQ1_RSQ14_4 ((uint32_t)0x00000200) /*!< Bit 4 */ - -#define ADC_RSQ1_RSQ15 ((uint32_t)0x00007C00) /*!< RSQ15[4:0] bits (15th conversion in regular sequence) */ -#define ADC_RSQ1_RSQ15_0 ((uint32_t)0x00000400) /*!< Bit 0 */ -#define ADC_RSQ1_RSQ15_1 ((uint32_t)0x00000800) /*!< Bit 1 */ -#define ADC_RSQ1_RSQ15_2 ((uint32_t)0x00001000) /*!< Bit 2 */ -#define ADC_RSQ1_RSQ15_3 ((uint32_t)0x00002000) /*!< Bit 3 */ -#define ADC_RSQ1_RSQ15_4 ((uint32_t)0x00004000) /*!< Bit 4 */ - -#define ADC_RSQ1_RSQ16 ((uint32_t)0x000F8000) /*!< RSQ16[4:0] bits (16th conversion in regular sequence) */ -#define ADC_RSQ1_RSQ16_0 ((uint32_t)0x00008000) /*!< Bit 0 */ -#define ADC_RSQ1_RSQ16_1 ((uint32_t)0x00010000) /*!< Bit 1 */ -#define ADC_RSQ1_RSQ16_2 ((uint32_t)0x00020000) /*!< Bit 2 */ -#define ADC_RSQ1_RSQ16_3 ((uint32_t)0x00040000) /*!< Bit 3 */ -#define ADC_RSQ1_RSQ16_4 ((uint32_t)0x00080000) /*!< Bit 4 */ - -#define ADC_RSQ1_RL ((uint32_t)0x00F00000) /*!< RL[3:0] bits (Regular channel sequence length) */ -#define ADC_RSQ1_RL_0 ((uint32_t)0x00100000) /*!< Bit 0 */ -#define ADC_RSQ1_RL_1 ((uint32_t)0x00200000) /*!< Bit 1 */ -#define ADC_RSQ1_RL_2 ((uint32_t)0x00400000) /*!< Bit 2 */ -#define ADC_RSQ1_RL_3 ((uint32_t)0x00800000) /*!< Bit 3 */ - -/******************* Bit definition for ADC_RSQ2 register *******************/ -#define ADC_RSQ2_RSQ7 ((uint32_t)0x0000001F) /*!< RSQ7[4:0] bits (7th conversion in regular sequence) */ -#define ADC_RSQ2_RSQ7_0 ((uint32_t)0x00000001) /*!< Bit 0 */ -#define ADC_RSQ2_RSQ7_1 ((uint32_t)0x00000002) /*!< Bit 1 */ -#define ADC_RSQ2_RSQ7_2 ((uint32_t)0x00000004) /*!< Bit 2 */ -#define ADC_RSQ2_RSQ7_3 ((uint32_t)0x00000008) /*!< Bit 3 */ -#define ADC_RSQ2_RSQ7_4 ((uint32_t)0x00000010) /*!< Bit 4 */ - -#define ADC_RSQ2_RSQ8 ((uint32_t)0x000003E0) /*!< RSQ8[4:0] bits (8th conversion in regular sequence) */ -#define ADC_RSQ2_RSQ8_0 ((uint32_t)0x00000020) /*!< Bit 0 */ -#define ADC_RSQ2_RSQ8_1 ((uint32_t)0x00000040) /*!< Bit 1 */ -#define ADC_RSQ2_RSQ8_2 ((uint32_t)0x00000080) /*!< Bit 2 */ -#define ADC_RSQ2_RSQ8_3 ((uint32_t)0x00000100) /*!< Bit 3 */ -#define ADC_RSQ2_RSQ8_4 ((uint32_t)0x00000200) /*!< Bit 4 */ - -#define ADC_RSQ2_RSQ9 ((uint32_t)0x00007C00) /*!< RSQ9[4:0] bits (9th conversion in regular sequence) */ -#define ADC_RSQ2_RSQ9_0 ((uint32_t)0x00000400) /*!< Bit 0 */ -#define ADC_RSQ2_RSQ9_1 ((uint32_t)0x00000800) /*!< Bit 1 */ -#define ADC_RSQ2_RSQ9_2 ((uint32_t)0x00001000) /*!< Bit 2 */ -#define ADC_RSQ2_RSQ9_3 ((uint32_t)0x00002000) /*!< Bit 3 */ -#define ADC_RSQ2_RSQ9_4 ((uint32_t)0x00004000) /*!< Bit 4 */ - -#define ADC_RSQ2_RSQ10 ((uint32_t)0x000F8000) /*!< RSQ10[4:0] bits (10th conversion in regular sequence) */ -#define ADC_RSQ2_RSQ10_0 ((uint32_t)0x00008000) /*!< Bit 0 */ -#define ADC_RSQ2_RSQ10_1 ((uint32_t)0x00010000) /*!< Bit 1 */ -#define ADC_RSQ2_RSQ10_2 ((uint32_t)0x00020000) /*!< Bit 2 */ -#define ADC_RSQ2_RSQ10_3 ((uint32_t)0x00040000) /*!< Bit 3 */ -#define ADC_RSQ2_RSQ10_4 ((uint32_t)0x00080000) /*!< Bit 4 */ - -#define ADC_RSQ2_RSQ11 ((uint32_t)0x01F00000) /*!< RSQ11[4:0] bits (11th conversion in regular sequence) */ -#define ADC_RSQ2_RSQ11_0 ((uint32_t)0x00100000) /*!< Bit 0 */ -#define ADC_RSQ2_RSQ11_1 ((uint32_t)0x00200000) /*!< Bit 1 */ -#define ADC_RSQ2_RSQ11_2 ((uint32_t)0x00400000) /*!< Bit 2 */ -#define ADC_RSQ2_RSQ11_3 ((uint32_t)0x00800000) /*!< Bit 3 */ -#define ADC_RSQ2_RSQ11_4 ((uint32_t)0x01000000) /*!< Bit 4 */ - -#define ADC_RSQ2_RSQ12 ((uint32_t)0x3E000000) /*!< RSQ12[4:0] bits (12th conversion in regular sequence) */ -#define ADC_RSQ2_RSQ12_0 ((uint32_t)0x02000000) /*!< Bit 0 */ -#define ADC_RSQ2_RSQ12_1 ((uint32_t)0x04000000) /*!< Bit 1 */ -#define ADC_RSQ2_RSQ12_2 ((uint32_t)0x08000000) /*!< Bit 2 */ -#define ADC_RSQ2_RSQ12_3 ((uint32_t)0x10000000) /*!< Bit 3 */ -#define ADC_RSQ2_RSQ12_4 ((uint32_t)0x20000000) /*!< Bit 4 */ - -/******************* Bit definition for ADC_RSQ3 register *******************/ -#define ADC_RSQ3_RSQ1 ((uint32_t)0x0000001F) /*!< RSQ1[4:0] bits (1st conversion in regular sequence) */ -#define ADC_RSQ3_RSQ1_0 ((uint32_t)0x00000001) /*!< Bit 0 */ -#define ADC_RSQ3_RSQ1_1 ((uint32_t)0x00000002) /*!< Bit 1 */ -#define ADC_RSQ3_RSQ1_2 ((uint32_t)0x00000004) /*!< Bit 2 */ -#define ADC_RSQ3_RSQ1_3 ((uint32_t)0x00000008) /*!< Bit 3 */ -#define ADC_RSQ3_RSQ1_4 ((uint32_t)0x00000010) /*!< Bit 4 */ - -#define ADC_RSQ3_RSQ2 ((uint32_t)0x000003E0) /*!< RSQ2[4:0] bits (2nd conversion in regular sequence) */ -#define ADC_RSQ3_RSQ2_0 ((uint32_t)0x00000020) /*!< Bit 0 */ -#define ADC_RSQ3_RSQ2_1 ((uint32_t)0x00000040) /*!< Bit 1 */ -#define ADC_RSQ3_RSQ2_2 ((uint32_t)0x00000080) /*!< Bit 2 */ -#define ADC_RSQ3_RSQ2_3 ((uint32_t)0x00000100) /*!< Bit 3 */ -#define ADC_RSQ3_RSQ2_4 ((uint32_t)0x00000200) /*!< Bit 4 */ - -#define ADC_RSQ3_RSQ3 ((uint32_t)0x00007C00) /*!< RSQ3[4:0] bits (3rd conversion in regular sequence) */ -#define ADC_RSQ3_RSQ3_0 ((uint32_t)0x00000400) /*!< Bit 0 */ -#define ADC_RSQ3_RSQ3_1 ((uint32_t)0x00000800) /*!< Bit 1 */ -#define ADC_RSQ3_RSQ3_2 ((uint32_t)0x00001000) /*!< Bit 2 */ -#define ADC_RSQ3_RSQ3_3 ((uint32_t)0x00002000) /*!< Bit 3 */ -#define ADC_RSQ3_RSQ3_4 ((uint32_t)0x00004000) /*!< Bit 4 */ - -#define ADC_RSQ3_RSQ4 ((uint32_t)0x000F8000) /*!< RSQ4[4:0] bits (4th conversion in regular sequence) */ -#define ADC_RSQ3_RSQ4_0 ((uint32_t)0x00008000) /*!< Bit 0 */ -#define ADC_RSQ3_RSQ4_1 ((uint32_t)0x00010000) /*!< Bit 1 */ -#define ADC_RSQ3_RSQ4_2 ((uint32_t)0x00020000) /*!< Bit 2 */ -#define ADC_RSQ3_RSQ4_3 ((uint32_t)0x00040000) /*!< Bit 3 */ -#define ADC_RSQ3_RSQ4_4 ((uint32_t)0x00080000) /*!< Bit 4 */ - -#define ADC_RSQ3_RSQ5 ((uint32_t)0x01F00000) /*!< RSQ5[4:0] bits (5th conversion in regular sequence) */ -#define ADC_RSQ3_RSQ5_0 ((uint32_t)0x00100000) /*!< Bit 0 */ -#define ADC_RSQ3_RSQ5_1 ((uint32_t)0x00200000) /*!< Bit 1 */ -#define ADC_RSQ3_RSQ5_2 ((uint32_t)0x00400000) /*!< Bit 2 */ -#define ADC_RSQ3_RSQ5_3 ((uint32_t)0x00800000) /*!< Bit 3 */ -#define ADC_RSQ3_RSQ5_4 ((uint32_t)0x01000000) /*!< Bit 4 */ - -#define ADC_RSQ3_RSQ6 ((uint32_t)0x3E000000) /*!< RSQ6[4:0] bits (6th conversion in regular sequence) */ -#define ADC_RSQ3_RSQ6_0 ((uint32_t)0x02000000) /*!< Bit 0 */ -#define ADC_RSQ3_RSQ6_1 ((uint32_t)0x04000000) /*!< Bit 1 */ -#define ADC_RSQ3_RSQ6_2 ((uint32_t)0x08000000) /*!< Bit 2 */ -#define ADC_RSQ3_RSQ6_3 ((uint32_t)0x10000000) /*!< Bit 3 */ -#define ADC_RSQ3_RSQ6_4 ((uint32_t)0x20000000) /*!< Bit 4 */ - -/******************* Bit definition for ADC_ISQ register *******************/ -#define ADC_ISQ_ISQ1 ((uint32_t)0x0000001F) /*!< ISQ1[4:0] bits (1st conversion in injected sequence) */ -#define ADC_ISQ_ISQ1_0 ((uint32_t)0x00000001) /*!< Bit 0 */ -#define ADC_ISQ_ISQ1_1 ((uint32_t)0x00000002) /*!< Bit 1 */ -#define ADC_ISQ_ISQ1_2 ((uint32_t)0x00000004) /*!< Bit 2 */ -#define ADC_ISQ_ISQ1_3 ((uint32_t)0x00000008) /*!< Bit 3 */ -#define ADC_ISQ_ISQ1_4 ((uint32_t)0x00000010) /*!< Bit 4 */ - -#define ADC_ISQ_ISQ2 ((uint32_t)0x000003E0) /*!< ISQ2[4:0] bits (2nd conversion in injected sequence) */ -#define ADC_ISQ_ISQ2_0 ((uint32_t)0x00000020) /*!< Bit 0 */ -#define ADC_ISQ_ISQ2_1 ((uint32_t)0x00000040) /*!< Bit 1 */ -#define ADC_ISQ_ISQ2_2 ((uint32_t)0x00000080) /*!< Bit 2 */ -#define ADC_ISQ_ISQ2_3 ((uint32_t)0x00000100) /*!< Bit 3 */ -#define ADC_ISQ_ISQ2_4 ((uint32_t)0x00000200) /*!< Bit 4 */ - -#define ADC_ISQ_ISQ3 ((uint32_t)0x00007C00) /*!< ISQ3[4:0] bits (3rd conversion in injected sequence) */ -#define ADC_ISQ_ISQ3_0 ((uint32_t)0x00000400) /*!< Bit 0 */ -#define ADC_ISQ_ISQ3_1 ((uint32_t)0x00000800) /*!< Bit 1 */ -#define ADC_ISQ_ISQ3_2 ((uint32_t)0x00001000) /*!< Bit 2 */ -#define ADC_ISQ_ISQ3_3 ((uint32_t)0x00002000) /*!< Bit 3 */ -#define ADC_ISQ_ISQ3_4 ((uint32_t)0x00004000) /*!< Bit 4 */ - -#define ADC_ISQ_ISQ4 ((uint32_t)0x000F8000) /*!< ISQ4[4:0] bits (4th conversion in injected sequence) */ -#define ADC_ISQ_ISQ4_0 ((uint32_t)0x00008000) /*!< Bit 0 */ -#define ADC_ISQ_ISQ4_1 ((uint32_t)0x00010000) /*!< Bit 1 */ -#define ADC_ISQ_ISQ4_2 ((uint32_t)0x00020000) /*!< Bit 2 */ -#define ADC_ISQ_ISQ4_3 ((uint32_t)0x00040000) /*!< Bit 3 */ -#define ADC_ISQ_ISQ4_4 ((uint32_t)0x00080000) /*!< Bit 4 */ - -#define ADC_ISQ_IL ((uint32_t)0x00300000) /*!< IL[1:0] bits (Injected Sequence length) */ -#define ADC_ISQ_IL_0 ((uint32_t)0x00100000) /*!< Bit 0 */ -#define ADC_ISQ_IL_1 ((uint32_t)0x00200000) /*!< Bit 1 */ - -/******************* Bit definition for ADC_IDTR1 register *******************/ -#define ADC_IDTR1_IDTR ((uint16_t)0xFFFF) /*!< Injected data */ - -/******************* Bit definition for ADC_IDTR2 register *******************/ -#define ADC_IDTR2_IDTR ((uint16_t)0xFFFF) /*!< Injected data */ - -/******************* Bit definition for ADC_IDTR3 register *******************/ -#define ADC_IDTR3_IDTR ((uint16_t)0xFFFF) /*!< Injected data */ - -/******************* Bit definition for ADC_IDTR4 register *******************/ -#define ADC_IDTR4_IDTR ((uint16_t)0xFFFF) /*!< Injected data */ - -/******************** Bit definition for ADC_RDTR register ********************/ -#define ADC_RDTR_RDTR ((uint32_t)0x0000FFFF) /*!< Regular data */ - -/******************************************************************************/ -/* */ -/* Backup registers */ -/* */ -/******************************************************************************/ - -/******************* Bit definition for BKP_DRx register ********************/ -#define BKP_DR1_BKD ((uint16_t)0xFFFF) /*!< Backup data */ -#define BKP_DR2_BKD ((uint16_t)0xFFFF) /*!< Backup data */ -#define BKP_DR3_BKD ((uint16_t)0xFFFF) /*!< Backup data */ -#define BKP_DR4_BKD ((uint16_t)0xFFFF) /*!< Backup data */ -#define BKP_DR5_BKD ((uint16_t)0xFFFF) /*!< Backup data */ -#define BKP_DR6_BKD ((uint16_t)0xFFFF) /*!< Backup data */ -#define BKP_DR7_BKD ((uint16_t)0xFFFF) /*!< Backup data */ -#define BKP_DR8_BKD ((uint16_t)0xFFFF) /*!< Backup data */ -#define BKP_DR9_BKD ((uint16_t)0xFFFF) /*!< Backup data */ -#define BKP_DR10_BKD ((uint16_t)0xFFFF) /*!< Backup data */ -#define BKP_DR11_BKD ((uint16_t)0xFFFF) /*!< Backup data */ -#define BKP_DR12_BKD ((uint16_t)0xFFFF) /*!< Backup data */ -#define BKP_DR13_BKD ((uint16_t)0xFFFF) /*!< Backup data */ -#define BKP_DR14_BKD ((uint16_t)0xFFFF) /*!< Backup data */ -#define BKP_DR15_BKD ((uint16_t)0xFFFF) /*!< Backup data */ -#define BKP_DR16_BKD ((uint16_t)0xFFFF) /*!< Backup data */ -#define BKP_DR17_BKD ((uint16_t)0xFFFF) /*!< Backup data */ -#define BKP_DR18_BKD ((uint16_t)0xFFFF) /*!< Backup data */ -#define BKP_DR19_BKD ((uint16_t)0xFFFF) /*!< Backup data */ -#define BKP_DR20_BKD ((uint16_t)0xFFFF) /*!< Backup data */ -#define BKP_DR21_BKD ((uint16_t)0xFFFF) /*!< Backup data */ -#define BKP_DR22_BKD ((uint16_t)0xFFFF) /*!< Backup data */ -#define BKP_DR23_BKD ((uint16_t)0xFFFF) /*!< Backup data */ -#define BKP_DR24_BKD ((uint16_t)0xFFFF) /*!< Backup data */ -#define BKP_DR25_BKD ((uint16_t)0xFFFF) /*!< Backup data */ -#define BKP_DR26_BKD ((uint16_t)0xFFFF) /*!< Backup data */ -#define BKP_DR27_BKD ((uint16_t)0xFFFF) /*!< Backup data */ -#define BKP_DR28_BKD ((uint16_t)0xFFFF) /*!< Backup data */ -#define BKP_DR29_BKD ((uint16_t)0xFFFF) /*!< Backup data */ -#define BKP_DR30_BKD ((uint16_t)0xFFFF) /*!< Backup data */ -#define BKP_DR31_BKD ((uint16_t)0xFFFF) /*!< Backup data */ -#define BKP_DR32_BKD ((uint16_t)0xFFFF) /*!< Backup data */ -#define BKP_DR33_BKD ((uint16_t)0xFFFF) /*!< Backup data */ -#define BKP_DR34_BKD ((uint16_t)0xFFFF) /*!< Backup data */ -#define BKP_DR35_BKD ((uint16_t)0xFFFF) /*!< Backup data */ -#define BKP_DR36_BKD ((uint16_t)0xFFFF) /*!< Backup data */ -#define BKP_DR37_BKD ((uint16_t)0xFFFF) /*!< Backup data */ -#define BKP_DR38_BKD ((uint16_t)0xFFFF) /*!< Backup data */ -#define BKP_DR39_BKD ((uint16_t)0xFFFF) /*!< Backup data */ -#define BKP_DR40_BKD ((uint16_t)0xFFFF) /*!< Backup data */ -#define BKP_DR41_BKD ((uint16_t)0xFFFF) /*!< Backup data */ -#define BKP_DR42_BKD ((uint16_t)0xFFFF) /*!< Backup data */ - -/****************** Bit definition for BKP_RCCR register *******************/ -#define BKP_RCCR_RCCV ((uint16_t)0x007F) /*!< RTC Clock Calibration Value */ -#define BKP_RCCR_RCCOE ((uint16_t)0x0080) /*!< RTC Clock Calibration Output Enable */ -#define BKP_RCCR_ROE ((uint16_t)0x0100) /*!< RTC Output Enable */ -#define BKP_RCCR_ROS ((uint16_t)0x0200) /*!< RTC Output Selection */ - -/******************** Bit definition for BKP_TPCR register ********************/ -#define BKP_TPCR_TPE ((uint8_t)0x01) /*!< TAMPER Pin Enable */ -#define BKP_TPCR_TPAL ((uint8_t)0x02) /*!< TAMPER Pin Active Level */ - -/******************* Bit definition for BKP_TIER register ********************/ -#define BKP_TIER_TER ((uint16_t)0x0001) /*!< Tamper Event Reset */ -#define BKP_TIER_TIR ((uint16_t)0x0002) /*!< Tamper Interrupt Reset */ -#define BKP_TIER_TIE ((uint16_t)0x0004) /*!< Tamper Interrupt Enable */ -#define BKP_TIER_TEF ((uint16_t)0x0100) /*!< Tamper Event Flag */ -#define BKP_TIER_TIF ((uint16_t)0x0200) /*!< Tamper Interrupt Flag */ - - -/******************************************************************************/ -/* */ -/* Controller Area Network */ -/* */ -/******************************************************************************/ -/*!< CAN control and status registers */ -/******************* Bit definition for CAN_CTLR register ********************/ -#define CAN_CTLR_IWM ((uint16_t)0x0001) /*!< Initial working mode */ -#define CAN_CTLR_SWM ((uint16_t)0x0002) /*!< Sleep working mode */ -#define CAN_CTLR_TFO ((uint16_t)0x0004) /*!< Transmit FIFO order */ -#define CAN_CTLR_RFOD ((uint16_t)0x0008) /*!< Receive FIFO overwrite disable */ -#define CAN_CTLR_ARD ((uint16_t)0x0010) /*!< Automatic retransmission disable */ -#define CAN_CTLR_AWK ((uint16_t)0x0020) /*!< Automatic Wakeup */ -#define CAN_CTLR_ABOR ((uint16_t)0x0040) /*!< Automatic Bus-Off recovery */ -#define CAN_CTLR_TTC ((uint16_t)0x0080) /*!< Time Triggered Communication */ -#define CAN_CTLR_SR ((uint16_t)0x8000) /*!< CAN software reset */ -#define CAN_CTLR_DFZ ((uint32_t)0x00010000) /*!< CAN Debug freeze */ - -/******************* Bit definition for CAN_STR register ********************/ -#define CAN_STR_IWS ((uint16_t)0x0001) /*!< Initial working state */ -#define CAN_STR_SWS ((uint16_t)0x0002) /*!< Sleep working state */ -#define CAN_STR_EIF ((uint16_t)0x0004) /*!< Error Interrupt Flag*/ -#define CAN_STR_WIF ((uint16_t)0x0008) /*!< Status change interrupt flag of wakeup from sleep working mode */ -#define CAN_STR_SEIF ((uint16_t)0x0010) /*!< Status change interrupt flag of sleep working mode entering */ -#define CAN_STR_TS ((uint16_t)0x0100) /*!< Transmitting state */ -#define CAN_STR_RS ((uint16_t)0x0200) /*!< Receiving state */ -#define CAN_STR_LASTRX ((uint16_t)0x0400) /*!< Last sample value of Rx pin */ -#define CAN_STR_RX ((uint16_t)0x0800) /*!< CAN Rx Signal */ - -/******************* Bit definition for CAN_TSTR register ********************/ -#define CAN_TSTR_MTF0 ((uint32_t)0x00000001) /*!< Mailbox 0 transmit finished */ -#define CAN_TSTR_MTFNE0 ((uint32_t)0x00000002) /*!< Mailbox 0 transmit finished and no error */ -#define CAN_TSTR_MAL0 ((uint32_t)0x00000004) /*!< Mailbox 0 arbitration lost */ -#define CAN_TSTR_MTE0 ((uint32_t)0x00000008) /*!< Mailbox 0 transmit error */ -#define CAN_TSTR_MST0 ((uint32_t)0x00000080) /*!< Mailbox 0 stop transmitting */ - -#define CAN_TSTR_MTF1 ((uint32_t)0x00000100) /*!< Mailbox 1 transmit finished */ -#define CAN_TSTR_MTFNE1 ((uint32_t)0x00000200) /*!< Mailbox 1 transmit finished and no error */ -#define CAN_TSTR_MAL1 ((uint32_t)0x00000400) /*!< Mailbox 1 arbitration lost */ -#define CAN_TSTR_MTE1 ((uint32_t)0x00000800) /*!< Mailbox 1 transmit error */ -#define CAN_TSTR_MST1 ((uint32_t)0x00008000) /*!< Mailbox 1 stop transmitting */ - -#define CAN_TSTR_MTF2 ((uint32_t)0x00010000) /*!< Mailbox 2 transmit finished */ -#define CAN_TSTR_MTFNE2 ((uint32_t)0x00020000) /*!< Mailbox 2 transmit finished and no error */ -#define CAN_TSTR_MAL2 ((uint32_t)0x00040000) /*!< Mailbox 2 arbitration lost */ -#define CAN_TSTR_MTE2 ((uint32_t)0x00080000) /*!< Mailbox 2 transmit error */ -#define CAN_TSTR_MST2 ((uint32_t)0x00800000) /*!< Mailbox 2 stop transmitting */ - -#define CAN_TSTR_NUM ((uint32_t)0x03000000) /*!< Mailbox number */ - -#define CAN_TSTR_TME ((uint32_t)0x1C000000) /*!< TME[2:0] bits */ -#define CAN_TSTR_TME0 ((uint32_t)0x04000000) /*!< Transmit mailbox 0 empty */ -#define CAN_TSTR_TME1 ((uint32_t)0x08000000) /*!< Transmit mailbox 1 empty */ -#define CAN_TSTR_TME2 ((uint32_t)0x10000000) /*!< Transmit mailbox 2 empty */ - -#define CAN_TSTR_TMLS ((uint32_t)0xE0000000) /*!< TMLS[2:0] bits */ -#define CAN_TSTR_TMLS0 ((uint32_t)0x20000000) /*!< Last sending Priority Flag for Mailbox 0 */ -#define CAN_TSTR_TMLS1 ((uint32_t)0x40000000) /*!< Last sending Priority Flag for Mailbox 1 */ -#define CAN_TSTR_TMLS2 ((uint32_t)0x80000000) /*!< Last sending Priority Flag for Mailbox 2 */ - -/******************* Bit definition for CAN_RFR0 register *******************/ -#define CAN_RFR0_RFL0 ((uint8_t)0x03) /*!< Receive FIFO 0 length */ -#define CAN_RFR0_RFF0 ((uint8_t)0x08) /*!< Receive FIFO 0 full */ -#define CAN_RFR0_RFO0 ((uint8_t)0x10) /*!< Receive FIFO 0 overfull */ -#define CAN_RFR0_RFD0 ((uint8_t)0x20) /*!< Receive FIFO 0 dequeue */ - -/******************* Bit definition for CAN_RFR1 register *******************/ -#define CAN_RFR1_RFL1 ((uint8_t)0x03) /*!< Receive FIFO 1 length */ -#define CAN_RFR1_RFF1 ((uint8_t)0x08) /*!< Receive FIFO 1 full */ -#define CAN_RFR1_RFO1 ((uint8_t)0x10) /*!< Receive FIFO 1 overfull */ -#define CAN_RFR1_RFD1 ((uint8_t)0x20) /*!< Receive FIFO 1 dequeue */ - -/******************** Bit definition for CAN_IER register *******************/ -#define CAN_IER_TMEIE ((uint32_t)0x00000001) /*!< Transmit mailbox empty interrupt enable */ -#define CAN_IER_RFNEIE0 ((uint32_t)0x00000002) /*!< Receive FIFO0 not empty interrupt enable */ -#define CAN_IER_RFFIE0 ((uint32_t)0x00000004) /*!< Receive FIFO0 full interrupt enable */ -#define CAN_IER_RFOIE0 ((uint32_t)0x00000008) /*!< Receive FIFO0 overfull interrupt enable */ -#define CAN_IER_RFNEIE1 ((uint32_t)0x00000010) /*!< Receive FIFO1 not empty interrupt enable */ -#define CAN_IER_RFFIE1 ((uint32_t)0x00000020) /*!< Receive FIFO1 full interrupt enable */ -#define CAN_IER_RFOIE1 ((uint32_t)0x00000040) /*!< Receive FIFO1 overfull interrupt enable */ -#define CAN_IER_WEIE ((uint32_t)0x00000100) /*!< Warning error interrupt enable */ -#define CAN_IER_PEIE ((uint32_t)0x00000200) /*!< Passive error interrupt enable */ -#define CAN_IER_BOIE ((uint32_t)0x00000400) /*!< Bus-off interrupt enable */ -#define CAN_IER_ENIE ((uint32_t)0x00000800) /*!< Error number interrupt enable */ -#define CAN_IER_EIE ((uint32_t)0x00008000) /*!< Error Interrupt enable */ -#define CAN_IER_WIE ((uint32_t)0x00010000) /*!< Wakeup Interrupt enable */ -#define CAN_IER_SWIE ((uint32_t)0x00020000) /*!< Sleep working interrupt enable */ - -/******************** Bit definition for CAN_ER register *******************/ -#define CAN_ER_WE ((uint32_t)0x00000001) /*!< Warning error */ -#define CAN_ER_PE ((uint32_t)0x00000002) /*!< Passive error */ -#define CAN_ER_BOE ((uint32_t)0x00000004) /*!< Bus-off error */ - -#define CAN_ER_ET ((uint32_t)0x00000070) /*!< ET[2:0] bits (Error type) */ -#define CAN_ER_ET_0 ((uint32_t)0x00000010) /*!< Bit 0 */ -#define CAN_ER_ET_1 ((uint32_t)0x00000020) /*!< Bit 1 */ -#define CAN_ER_ET_2 ((uint32_t)0x00000040) /*!< Bit 2 */ - -#define CAN_ER_TEC ((uint32_t)0x00FF0000) /*!< Transmit Error Count */ -#define CAN_ER_REC ((uint32_t)0xFF000000) /*!< Receive Error Count */ - -/******************* Bit definition for CAN_BTR register ********************/ -#define CAN_BTR_BRP ((uint32_t)0x000003FF) /*!< Baud rate prescaler */ -#define CAN_BTR_BS1 ((uint32_t)0x000F0000) /*!< Bit Segment 1 */ -#define CAN_BTR_BS2 ((uint32_t)0x00700000) /*!< Bit Segment 2 */ -#define CAN_BTR_SJW ((uint32_t)0x03000000) /*!< Resynchronization jump width */ -#define CAN_BTR_LCM ((uint32_t)0x40000000) /*!< Loopback communication mode */ -#define CAN_BTR_SCM ((uint32_t)0x80000000) /*!< Silent communication mode */ - -/*!< Mailbox registers */ -/****************** Bit definition for CAN_TMIR0 register ********************/ -#define CAN_TMIR0_TE ((uint32_t)0x00000001) /*!< Transmit enable */ -#define CAN_TMIR0_FT ((uint32_t)0x00000002) /*!< Frame type */ -#define CAN_TMIR0_FF ((uint32_t)0x00000004) /*!< Frame format */ -#define CAN_TMIR0_EFID ((uint32_t)0x001FFFF8) /*!< The frame identifier */ -#define CAN_TMIR0_SFID ((uint32_t)0xFFE00000) /*!< The frame identifier */ - -/****************** Bit definition for CAN_TMPR0 register *******************/ -#define CAN_TMPR0_DLC ((uint32_t)0x0000000F) /*!< Data length code */ -#define CAN_TMPR0_TSE ((uint32_t)0x00000100) /*!< Time stamp enable */ -#define CAN_TMPR0_TS ((uint32_t)0xFFFF0000) /*!< Time stamp */ - -/****************** Bit definition for CAN_TMD0R0 register *******************/ -#define CAN_TMD0R0_DB0 ((uint32_t)0x000000FF) /*!< Data byte 0 */ -#define CAN_TMD0R0_DB1 ((uint32_t)0x0000FF00) /*!< Data byte 1 */ -#define CAN_TMD0R0_DB2 ((uint32_t)0x00FF0000) /*!< Data byte 2 */ -#define CAN_TMD0R0_DB3 ((uint32_t)0xFF000000) /*!< Data byte 3 */ - -/****************** Bit for CAN_TMD1R0 register *******************/ -#define CAN_TMD1R0_DB4 ((uint32_t)0x000000FF) /*!< Data byte 4 */ -#define CAN_TMD1R0_DB5 ((uint32_t)0x0000FF00) /*!< Data byte 5 */ -#define CAN_TMD1R0_DB6 ((uint32_t)0x00FF0000) /*!< Data byte 6 */ -#define CAN_TMD1R0_DB7 ((uint32_t)0xFF000000) /*!< Data byte 7 */ - -/****************** Bit definition for CAN_TMIR1 register ********************/ -#define CAN_TMIR1_TE ((uint32_t)0x00000001) /*!< Transmit enable */ -#define CAN_TMIR1_FT ((uint32_t)0x00000002) /*!< Frame type */ -#define CAN_TMIR1_FF ((uint32_t)0x00000004) /*!< Frame format */ -#define CAN_TMIR1_EFID ((uint32_t)0x001FFFF8) /*!< The frame identifier */ -#define CAN_TMIR1_SFID ((uint32_t)0xFFE00000) /*!< The frame identifier */ - -/****************** Bit definition for CAN_TMPR1 register *******************/ -#define CAN_TMPR1_DLC ((uint32_t)0x0000000F) /*!< Data length code */ -#define CAN_TMPR1_TSE ((uint32_t)0x00000100) /*!< Time stamp enable */ -#define CAN_TMPR1_TS ((uint32_t)0xFFFF0000) /*!< Time stamp */ - -/****************** Bit definition for CAN_TMD0R1 register *******************/ -#define CAN_TMD0R1_DB0 ((uint32_t)0x000000FF) /*!< Data byte 0 */ -#define CAN_TMD0R1_DB1 ((uint32_t)0x0000FF00) /*!< Data byte 1 */ -#define CAN_TMD0R1_DB2 ((uint32_t)0x00FF0000) /*!< Data byte 2 */ -#define CAN_TMD0R1_DB3 ((uint32_t)0xFF000000) /*!< Data byte 3 */ - -/****************** Bit definition for CAN_TMD1R1 register *******************/ -#define CAN_TMD1R1_DB4 ((uint32_t)0x000000FF) /*!< Data byte 4 */ -#define CAN_TMD1R1_DB5 ((uint32_t)0x0000FF00) /*!< Data byte 5 */ -#define CAN_TMD1R1_DB6 ((uint32_t)0x00FF0000) /*!< Data byte 6 */ -#define CAN_TMD1R1_DB7 ((uint32_t)0xFF000000) /*!< Data byte 7 */ - -/****************** Bit definition for CAN_TMIR2 register ********************/ -#define CAN_TMIR2_TE ((uint32_t)0x00000001) /*!< Transmit enable */ -#define CAN_TMIR2_FT ((uint32_t)0x00000002) /*!< Frame type */ -#define CAN_TMIR2_FF ((uint32_t)0x00000004) /*!< Frame format */ -#define CAN_TMIR2_EFID ((uint32_t)0x001FFFF8) /*!< The frame identifier */ -#define CAN_TMIR2_SFID ((uint32_t)0xFFE00000) /*!< The frame identifier */ - -/****************** Bit definition for CAN_TMPR2 register *******************/ -#define CAN_TMPR2_DLC ((uint32_t)0x0000000F) /*!< Data length code */ -#define CAN_TMPR2_TSE ((uint32_t)0x00000100) /*!< Time stamp enable */ -#define CAN_TMPR2_TS ((uint32_t)0xFFFF0000) /*!< Time stamp */ - -/****************** Bit definition for CAN_TMD0R2 register *******************/ -#define CAN_TMD0R2_DB0 ((uint32_t)0x000000FF) /*!< Data byte 0 */ -#define CAN_TMD0R2_DB1 ((uint32_t)0x0000FF00) /*!< Data byte 1 */ -#define CAN_TMD0R2_DB2 ((uint32_t)0x00FF0000) /*!< Data byte 2 */ -#define CAN_TMD0R2_DB3 ((uint32_t)0xFF000000) /*!< Data byte 3 */ - -/****************** Bit definition for CAN_TMD1R2 register *******************/ -#define CAN_TMD1R2_DB4 ((uint32_t)0x000000FF) /*!< Data byte 4 */ -#define CAN_TMD1R2_DB5 ((uint32_t)0x0000FF00) /*!< Data byte 5 */ -#define CAN_TMD1R2_DB6 ((uint32_t)0x00FF0000) /*!< Data byte 6 */ -#define CAN_TMD1R2_DB7 ((uint32_t)0xFF000000) /*!< Data byte 7 */ - -/****************** Bit definition for CAN_RFMIR0 register ********************/ -#define CAN_RFMIR0_FT ((uint32_t)0x00000002) /*!< Frame type */ -#define CAN_RFMIR0_FF ((uint32_t)0x00000004) /*!< Frame format */ -#define CAN_RFMIR0_EFID ((uint32_t)0x001FFFF8) /*!< The frame identifier */ -#define CAN_RFMIR0_SFID ((uint32_t)0xFFE00000) /*!< The frame identifier */ - -/****************** Bit definition for CAN_RFMPR0 register *******************/ -#define CAN_RFMPR0_DLC ((uint32_t)0x0000000F) /*!< Data length code */ -#define CAN_RFMPR0_TSE ((uint32_t)0x00000100) /*!< Time stamp enable */ -#define CAN_RFMPR0_TS ((uint32_t)0xFFFF0000) /*!< Time stamp */ - -/****************** Bit definition for CAN_RFMD0R0 register *******************/ -#define CAN_RFMD0R0_DB0 ((uint32_t)0x000000FF) /*!< Data byte 0 */ -#define CAN_RFMD0R0_DB1 ((uint32_t)0x0000FF00) /*!< Data byte 1 */ -#define CAN_RFMD0R0_DB2 ((uint32_t)0x00FF0000) /*!< Data byte 2 */ -#define CAN_RFMD0R0_DB3 ((uint32_t)0xFF000000) /*!< Data byte 3 */ - -/****************** Bit definition for CAN_RFMD1R0 register *******************/ -#define CAN_RFMD1R0_DB4 ((uint32_t)0x000000FF) /*!< Data byte 4 */ -#define CAN_RFMD1R0_DB5 ((uint32_t)0x0000FF00) /*!< Data byte 5 */ -#define CAN_RFMD1R0_DB6 ((uint32_t)0x00FF0000) /*!< Data byte 6 */ -#define CAN_RFMD1R0_DB7 ((uint32_t)0xFF000000) /*!< Data byte 7 */ - -/****************** Bit definition for CAN_RFMIR1 register ********************/ -#define CAN_RFMIR1_FT ((uint32_t)0x00000002) /*!< Frame type */ -#define CAN_RFMIR1_FF ((uint32_t)0x00000004) /*!< Frame format */ -#define CAN_RFMIR1_EFID ((uint32_t)0x001FFFF8) /*!< The frame identifier */ -#define CAN_RFMIR1_SFID ((uint32_t)0xFFE00000) /*!< The frame identifier */ - -/****************** Bit definition for CAN_RFMPR1 register *******************/ -#define CAN_RFMPR1_DLC ((uint32_t)0x0000000F) /*!< Data length code */ -#define CAN_RFMPR1_TSE ((uint32_t)0x00000100) /*!< Time stamp enable */ -#define CAN_RFMPR1_TS ((uint32_t)0xFFFF0000) /*!< Time stamp */ - -/****************** Bit definition for CAN_RFMD0R1 register *******************/ -#define CAN_RFMD0R1_DB0 ((uint32_t)0x000000FF) /*!< Data byte 0 */ -#define CAN_RFMD0R1_DB1 ((uint32_t)0x0000FF00) /*!< Data byte 1 */ -#define CAN_RFMD0R1_DB2 ((uint32_t)0x00FF0000) /*!< Data byte 2 */ -#define CAN_RFMD0R1_DB3 ((uint32_t)0xFF000000) /*!< Data byte 3 */ - -/****************** Bit definition for CAN_RFMD1R1 register *******************/ -#define CAN_RFMD1R1_DB4 ((uint32_t)0x000000FF) /*!< Data byte 4 */ -#define CAN_RFMD1R1_DB5 ((uint32_t)0x0000FF00) /*!< Data byte 5 */ -#define CAN_RFMD1R1_DB6 ((uint32_t)0x00FF0000) /*!< Data byte 6 */ -#define CAN_RFMD1R1_DB7 ((uint32_t)0xFF000000) /*!< Data byte 7 */ - -/*!< CAN filter registers */ -/******************* Bit definition for CAN_FCTLR register ********************/ -#define CAN_FCTLR_FLD ((uint8_t)0x00000001) /*!< Filter lock disable */ - -#ifdef GD32F10X_CL -#define CAN_FCTLR_HBC2F ((uint32_t)0x003F0000) /*!< Header bank of CAN2 filter */ -#endif /* GD32F10X_CL */ - -/******************* Bit definition for CAN_FMR register *******************/ -#define CAN_FMR_FM ((uint32_t)0x0FFFFFFF) /*!< Filter Mode */ -#define CAN_FMR_FM0 ((uint32_t)0x00000001) /*!< Filter Init Mode bit 0 */ -#define CAN_FMR_FM1 ((uint32_t)0x00000002) /*!< Filter Init Mode bit 1 */ -#define CAN_FMR_FM2 ((uint32_t)0x00000004) /*!< Filter Init Mode bit 2 */ -#define CAN_FMR_FM3 ((uint32_t)0x00000008) /*!< Filter Init Mode bit 3 */ -#define CAN_FMR_FM4 ((uint32_t)0x00000010) /*!< Filter Init Mode bit 4 */ -#define CAN_FMR_FM5 ((uint32_t)0x00000020) /*!< Filter Init Mode bit 5 */ -#define CAN_FMR_FM6 ((uint32_t)0x00000040) /*!< Filter Init Mode bit 6 */ -#define CAN_FMR_FM7 ((uint32_t)0x00000080) /*!< Filter Init Mode bit 7 */ -#define CAN_FMR_FM8 ((uint32_t)0x00000100) /*!< Filter Init Mode bit 8 */ -#define CAN_FMR_FM9 ((uint32_t)0x00000200) /*!< Filter Init Mode bit 9 */ -#define CAN_FMR_FM10 ((uint32_t)0x00000400) /*!< Filter Init Mode bit 10 */ -#define CAN_FMR_FM11 ((uint32_t)0x00000800) /*!< Filter Init Mode bit 11 */ -#define CAN_FMR_FM12 ((uint32_t)0x00001000) /*!< Filter Init Mode bit 12 */ -#define CAN_FMR_FM13 ((uint32_t)0x00002000) /*!< Filter Init Mode bit 13 */ -#define CAN_FMR_FM14 ((uint32_t)0x00004000) /*!< Filter Init Mode bit 14 */ -#define CAN_FMR_FM15 ((uint32_t)0x00008000) /*!< Filter Init Mode bit 15 */ -#define CAN_FMR_FM16 ((uint32_t)0x00010000) /*!< Filter Init Mode bit 16 */ -#define CAN_FMR_FM17 ((uint32_t)0x00020000) /*!< Filter Init Mode bit 17 */ -#define CAN_FMR_FM18 ((uint32_t)0x00040000) /*!< Filter Init Mode bit 18 */ -#define CAN_FMR_FM19 ((uint32_t)0x00080000) /*!< Filter Init Mode bit 19 */ -#define CAN_FMR_FM20 ((uint32_t)0x00100000) /*!< Filter Init Mode bit 20 */ -#define CAN_FMR_FM21 ((uint32_t)0x00200000) /*!< Filter Init Mode bit 21 */ -#define CAN_FMR_FM22 ((uint32_t)0x00400000) /*!< Filter Init Mode bit 22 */ -#define CAN_FMR_FM23 ((uint32_t)0x00800000) /*!< Filter Init Mode bit 23 */ -#define CAN_FMR_FM24 ((uint32_t)0x01000000) /*!< Filter Init Mode bit 24 */ -#define CAN_FMR_FM25 ((uint32_t)0x02000000) /*!< Filter Init Mode bit 25 */ -#define CAN_FMR_FM26 ((uint32_t)0x04000000) /*!< Filter Init Mode bit 26 */ -#define CAN_FMR_FM27 ((uint32_t)0x08000000) /*!< Filter Init Mode bit 27 */ - -/******************* Bit definition for CAN_FSR register *******************/ -#define CAN_FSR_FS ((uint32_t)0x0FFFFFFF) /*!< Filter Scale */ -#define CAN_FSR_FS0 ((uint32_t)0x00000001) /*!< Filter Scale bit 0 */ -#define CAN_FSR_FS1 ((uint32_t)0x00000002) /*!< Filter Scale bit 1 */ -#define CAN_FSR_FS2 ((uint32_t)0x00000004) /*!< Filter Scale bit 2 */ -#define CAN_FSR_FS3 ((uint32_t)0x00000008) /*!< Filter Scale bit 3 */ -#define CAN_FSR_FS4 ((uint32_t)0x00000010) /*!< Filter Scale bit 4 */ -#define CAN_FSR_FS5 ((uint32_t)0x00000020) /*!< Filter Scale bit 5 */ -#define CAN_FSR_FS6 ((uint32_t)0x00000040) /*!< Filter Scale bit 6 */ -#define CAN_FSR_FS7 ((uint32_t)0x00000080) /*!< Filter Scale bit 7 */ -#define CAN_FSR_FS8 ((uint32_t)0x00000100) /*!< Filter Scale bit 8 */ -#define CAN_FSR_FS9 ((uint32_t)0x00000200) /*!< Filter Scale bit 9 */ -#define CAN_FSR_FS10 ((uint32_t)0x00000400) /*!< Filter Scale bit 10 */ -#define CAN_FSR_FS11 ((uint32_t)0x00000800) /*!< Filter Scale bit 11 */ -#define CAN_FSR_FS12 ((uint32_t)0x00001000) /*!< Filter Scale bit 12 */ -#define CAN_FSR_FS13 ((uint32_t)0x00002000) /*!< Filter Scale bit 13 */ -#define CAN_FSR_FS14 ((uint32_t)0x00004000) /*!< Filter Scale bit 14 */ -#define CAN_FSR_FS15 ((uint32_t)0x00008000) /*!< Filter Scale bit 15 */ -#define CAN_FSR_FS16 ((uint32_t)0x00010000) /*!< Filter Scale bit 16 */ -#define CAN_FSR_FS17 ((uint32_t)0x00020000) /*!< Filter Scale bit 17 */ -#define CAN_FSR_FS18 ((uint32_t)0x00040000) /*!< Filter Scale bit 18 */ -#define CAN_FSR_FS19 ((uint32_t)0x00080000) /*!< Filter Scale bit 19 */ -#define CAN_FSR_FS20 ((uint32_t)0x00100000) /*!< Filter Scale bit 20 */ -#define CAN_FSR_FS21 ((uint32_t)0x00200000) /*!< Filter Scale bit 21 */ -#define CAN_FSR_FS22 ((uint32_t)0x00400000) /*!< Filter Scale bit 22 */ -#define CAN_FSR_FS23 ((uint32_t)0x00800000) /*!< Filter Scale bit 23*/ -#define CAN_FSR_FS24 ((uint32_t)0x01000000) /*!< Filter Scale bit 24 */ -#define CAN_FSR_FS25 ((uint32_t)0x02000000) /*!< Filter Scale bit 25 */ -#define CAN_FSR_FS26 ((uint32_t)0x04000000) /*!< Filter Scale bit 26 */ -#define CAN_FSR_FS27 ((uint32_t)0x08000000) /*!< Filter Scale bit 27 */ - -/****************** Bit definition for CAN_FAFR register *******************/ -#define CAN_FAFR_FAF ((uint32_t)0x0FFFFFFF) /*!< Filter associated with FIFO */ -#define CAN_FAFR_FAF0 ((uint32_t)0x00000001) /*!< Filter 0 associated with FIFO */ -#define CAN_FAFR_FAF1 ((uint32_t)0x00000002) /*!< Filter 1 associated with FIFO */ -#define CAN_FAFR_FAF2 ((uint32_t)0x00000004) /*!< Filter 2 associated with FIFO */ -#define CAN_FAFR_FAF3 ((uint32_t)0x00000008) /*!< Filter 3 associated with FIFO */ -#define CAN_FAFR_FAF4 ((uint32_t)0x00000010) /*!< Filter 4 associated with FIFO */ -#define CAN_FAFR_FAF5 ((uint32_t)0x00000020) /*!< Filter 5 associated with FIFO */ -#define CAN_FAFR_FAF6 ((uint32_t)0x00000040) /*!< Filter 6 associated with FIFO */ -#define CAN_FAFR_FAF7 ((uint32_t)0x00000080) /*!< Filter 7 associated with FIFO */ -#define CAN_FAFR_FAF8 ((uint32_t)0x00000100) /*!< Filter 8 associated with FIFO */ -#define CAN_FAFR_FAF9 ((uint32_t)0x00000200) /*!< Filter 9 associated with FIFO */ -#define CAN_FAFR_FAF10 ((uint32_t)0x00000400) /*!< Filter 10 associated with FIFO */ -#define CAN_FAFR_FAF11 ((uint32_t)0x00000800) /*!< Filter 11 associated with FIFO */ -#define CAN_FAFR_FAF12 ((uint32_t)0x00001000) /*!< Filter 12 associated with FIFO */ -#define CAN_FAFR_FAF13 ((uint32_t)0x00002000) /*!< Filter 13 associated with FIFO */ -#define CAN_FAFR_FAF14 ((uint32_t)0x00004000) /*!< Filter 14 associated with FIFO */ -#define CAN_FAFR_FAF15 ((uint32_t)0x00008000) /*!< Filter 15 associated with FIFO */ -#define CAN_FAFR_FAF16 ((uint32_t)0x00010000) /*!< Filter 16 associated with FIFO */ -#define CAN_FAFR_FAF17 ((uint32_t)0x00020000) /*!< Filter 17 associated with FIFO */ -#define CAN_FAFR_FAF18 ((uint32_t)0x00040000) /*!< Filter 18 associated with FIFO */ -#define CAN_FAFR_FAF19 ((uint32_t)0x00080000) /*!< Filter 19 associated with FIFO */ -#define CAN_FAFR_FAF20 ((uint32_t)0x00100000) /*!< Filter 20 associated with FIFO */ -#define CAN_FAFR_FAF21 ((uint32_t)0x00200000) /*!< Filter 21 associated with FIFO */ -#define CAN_FAFR_FAF22 ((uint32_t)0x00400000) /*!< Filter 22 associated with FIFO */ -#define CAN_FAFR_FAF23 ((uint32_t)0x00800000) /*!< Filter 23 associated with FIFO */ -#define CAN_FAFR_FAF24 ((uint32_t)0x01000000) /*!< Filter 24 associated with FIFO */ -#define CAN_FAFR_FAF25 ((uint32_t)0x02000000) /*!< Filter 25 associated with FIFO */ -#define CAN_FAFR_FAF26 ((uint32_t)0x04000000) /*!< Filter 26 associated with FIFO */ -#define CAN_FAFR_FAF27 ((uint32_t)0x08000000) /*!< Filter 27 associated with FIFO */ - -/******************* Bit definition for CAN_FWR register *******************/ -#define CAN_FWR_FW ((uint32_t)0x0FFFFFFF) /*!< Filter working */ -#define CAN_FWR_FW0 ((uint32_t)0x00000001) /*!< Filter 0 working */ -#define CAN_FWR_FW1 ((uint32_t)0x00000002) /*!< Filter 1 working */ -#define CAN_FWR_FW2 ((uint32_t)0x00000004) /*!< Filter 2 working */ -#define CAN_FWR_FW3 ((uint32_t)0x00000008) /*!< Filter 3 working */ -#define CAN_FWR_FW4 ((uint32_t)0x00000010) /*!< Filter 4 working */ -#define CAN_FWR_FW5 ((uint32_t)0x00000020) /*!< Filter 5 working */ -#define CAN_FWR_FW6 ((uint32_t)0x00000040) /*!< Filter 6 working */ -#define CAN_FWR_FW7 ((uint32_t)0x00000080) /*!< Filter 7 working */ -#define CAN_FWR_FW8 ((uint32_t)0x00000100) /*!< Filter 8 working */ -#define CAN_FWR_FW9 ((uint32_t)0x00000200) /*!< Filter 9 working */ -#define CAN_FWR_FW10 ((uint32_t)0x00000400) /*!< Filter 10 working */ -#define CAN_FWR_FW11 ((uint32_t)0x00000800) /*!< Filter 11 working */ -#define CAN_FWR_FW12 ((uint32_t)0x00001000) /*!< Filter 12 working */ -#define CAN_FWR_FW13 ((uint32_t)0x00002000) /*!< Filter 13 working */ -#define CAN_FWR_FW14 ((uint32_t)0x00004000) /*!< Filter 14 working */ -#define CAN_FWR_FW15 ((uint32_t)0x00008000) /*!< Filter 15 working */ -#define CAN_FWR_FW16 ((uint32_t)0x00010000) /*!< Filter 16 working */ -#define CAN_FWR_FW17 ((uint32_t)0x00020000) /*!< Filter 17 working */ -#define CAN_FWR_FW18 ((uint32_t)0x00040000) /*!< Filter 18 working */ -#define CAN_FWR_FW19 ((uint32_t)0x00080000) /*!< Filter 19 working */ -#define CAN_FWR_FW20 ((uint32_t)0x00100000) /*!< Filter 20 working */ -#define CAN_FWR_FW21 ((uint32_t)0x00200000) /*!< Filter 21 working */ -#define CAN_FWR_FW22 ((uint32_t)0x00400000) /*!< Filter 22 working */ -#define CAN_FWR_FW23 ((uint32_t)0x00800000) /*!< Filter 23 working */ -#define CAN_FWR_FW24 ((uint32_t)0x01000000) /*!< Filter 24 working */ -#define CAN_FWR_FW25 ((uint32_t)0x02000000) /*!< Filter 25 working */ -#define CAN_FWR_FW26 ((uint32_t)0x04000000) /*!< Filter 26 working */ -#define CAN_FWR_FW27 ((uint32_t)0x08000000) /*!< Filter 27 working */ - -/******************* Bit definition for CAN_F0D0R register *******************/ -#define CAN_F0D0R_FD0 ((uint32_t)0x00000001) /*!< Filter bit 0 */ -#define CAN_F0D0R_FD1 ((uint32_t)0x00000002) /*!< Filter bit 1 */ -#define CAN_F0D0R_FD2 ((uint32_t)0x00000004) /*!< Filter bit 2 */ -#define CAN_F0D0R_FD3 ((uint32_t)0x00000008) /*!< Filter bit 3 */ -#define CAN_F0D0R_FD4 ((uint32_t)0x00000010) /*!< Filter bit 4 */ -#define CAN_F0D0R_FD5 ((uint32_t)0x00000020) /*!< Filter bit 5 */ -#define CAN_F0D0R_FD6 ((uint32_t)0x00000040) /*!< Filter bit 6 */ -#define CAN_F0D0R_FD7 ((uint32_t)0x00000080) /*!< Filter bit 7 */ -#define CAN_F0D0R_FD8 ((uint32_t)0x00000100) /*!< Filter bit 8 */ -#define CAN_F0D0R_FD9 ((uint32_t)0x00000200) /*!< Filter bit 9 */ -#define CAN_F0D0R_FD10 ((uint32_t)0x00000400) /*!< Filter bit 10 */ -#define CAN_F0D0R_FD11 ((uint32_t)0x00000800) /*!< Filter bit 11 */ -#define CAN_F0D0R_FD12 ((uint32_t)0x00001000) /*!< Filter bit 12 */ -#define CAN_F0D0R_FD13 ((uint32_t)0x00002000) /*!< Filter bit 13 */ -#define CAN_F0D0R_FD14 ((uint32_t)0x00004000) /*!< Filter bit 14 */ -#define CAN_F0D0R_FD15 ((uint32_t)0x00008000) /*!< Filter bit 15 */ -#define CAN_F0D0R_FD16 ((uint32_t)0x00010000) /*!< Filter bit 16 */ -#define CAN_F0D0R_FD17 ((uint32_t)0x00020000) /*!< Filter bit 17 */ -#define CAN_F0D0R_FD18 ((uint32_t)0x00040000) /*!< Filter bit 18 */ -#define CAN_F0D0R_FD19 ((uint32_t)0x00080000) /*!< Filter bit 19 */ -#define CAN_F0D0R_FD20 ((uint32_t)0x00100000) /*!< Filter bit 20 */ -#define CAN_F0D0R_FD21 ((uint32_t)0x00200000) /*!< Filter bit 21 */ -#define CAN_F0D0R_FD22 ((uint32_t)0x00400000) /*!< Filter bit 22 */ -#define CAN_F0D0R_FD23 ((uint32_t)0x00800000) /*!< Filter bit 23 */ -#define CAN_F0D0R_FD24 ((uint32_t)0x01000000) /*!< Filter bit 24 */ -#define CAN_F0D0R_FD25 ((uint32_t)0x02000000) /*!< Filter bit 25 */ -#define CAN_F0D0R_FD26 ((uint32_t)0x04000000) /*!< Filter bit 26 */ -#define CAN_F0D0R_FD27 ((uint32_t)0x08000000) /*!< Filter bit 27 */ -#define CAN_F0D0R_FD28 ((uint32_t)0x10000000) /*!< Filter bit 28 */ -#define CAN_F0D0R_FD29 ((uint32_t)0x20000000) /*!< Filter bit 29 */ -#define CAN_F0D0R_FD30 ((uint32_t)0x40000000) /*!< Filter bit 30 */ -#define CAN_F0D0R_FD31 ((uint32_t)0x80000000) /*!< Filter bit 31 */ - -/******************* Bit definition for CAN_F1D0R register *******************/ -#define CAN_F1D0R_FD0 ((uint32_t)0x00000001) /*!< Filter bit 0 */ -#define CAN_F1D0R_FD1 ((uint32_t)0x00000002) /*!< Filter bit 1 */ -#define CAN_F1D0R_FD2 ((uint32_t)0x00000004) /*!< Filter bit 2 */ -#define CAN_F1D0R_FD3 ((uint32_t)0x00000008) /*!< Filter bit 3 */ -#define CAN_F1D0R_FD4 ((uint32_t)0x00000010) /*!< Filter bit 4 */ -#define CAN_F1D0R_FD5 ((uint32_t)0x00000020) /*!< Filter bit 5 */ -#define CAN_F1D0R_FD6 ((uint32_t)0x00000040) /*!< Filter bit 6 */ -#define CAN_F1D0R_FD7 ((uint32_t)0x00000080) /*!< Filter bit 7 */ -#define CAN_F1D0R_FD8 ((uint32_t)0x00000100) /*!< Filter bit 8 */ -#define CAN_F1D0R_FD9 ((uint32_t)0x00000200) /*!< Filter bit 9 */ -#define CAN_F1D0R_FD10 ((uint32_t)0x00000400) /*!< Filter bit 10 */ -#define CAN_F1D0R_FD11 ((uint32_t)0x00000800) /*!< Filter bit 11 */ -#define CAN_F1D0R_FD12 ((uint32_t)0x00001000) /*!< Filter bit 12 */ -#define CAN_F1D0R_FD13 ((uint32_t)0x00002000) /*!< Filter bit 13 */ -#define CAN_F1D0R_FD14 ((uint32_t)0x00004000) /*!< Filter bit 14 */ -#define CAN_F1D0R_FD15 ((uint32_t)0x00008000) /*!< Filter bit 15 */ -#define CAN_F1D0R_FD16 ((uint32_t)0x00010000) /*!< Filter bit 16 */ -#define CAN_F1D0R_FD17 ((uint32_t)0x00020000) /*!< Filter bit 17 */ -#define CAN_F1D0R_FD18 ((uint32_t)0x00040000) /*!< Filter bit 18 */ -#define CAN_F1D0R_FD19 ((uint32_t)0x00080000) /*!< Filter bit 19 */ -#define CAN_F1D0R_FD20 ((uint32_t)0x00100000) /*!< Filter bit 20 */ -#define CAN_F1D0R_FD21 ((uint32_t)0x00200000) /*!< Filter bit 21 */ -#define CAN_F1D0R_FD22 ((uint32_t)0x00400000) /*!< Filter bit 22 */ -#define CAN_F1D0R_FD23 ((uint32_t)0x00800000) /*!< Filter bit 23 */ -#define CAN_F1D0R_FD24 ((uint32_t)0x01000000) /*!< Filter bit 24 */ -#define CAN_F1D0R_FD25 ((uint32_t)0x02000000) /*!< Filter bit 25 */ -#define CAN_F1D0R_FD26 ((uint32_t)0x04000000) /*!< Filter bit 26 */ -#define CAN_F1D0R_FD27 ((uint32_t)0x08000000) /*!< Filter bit 27 */ -#define CAN_F1D0R_FD28 ((uint32_t)0x10000000) /*!< Filter bit 28 */ -#define CAN_F1D0R_FD29 ((uint32_t)0x20000000) /*!< Filter bit 29 */ -#define CAN_F1D0R_FD30 ((uint32_t)0x40000000) /*!< Filter bit 30 */ -#define CAN_F1D0R_FD31 ((uint32_t)0x80000000) /*!< Filter bit 31 */ - -/******************* Bit definition for CAN_F2D0R register *******************/ -#define CAN_F2D0R_FD0 ((uint32_t)0x00000001) /*!< Filter bit 0 */ -#define CAN_F2D0R_FD1 ((uint32_t)0x00000002) /*!< Filter bit 1 */ -#define CAN_F2D0R_FD2 ((uint32_t)0x00000004) /*!< Filter bit 2 */ -#define CAN_F2D0R_FD3 ((uint32_t)0x00000008) /*!< Filter bit 3 */ -#define CAN_F2D0R_FD4 ((uint32_t)0x00000010) /*!< Filter bit 4 */ -#define CAN_F2D0R_FD5 ((uint32_t)0x00000020) /*!< Filter bit 5 */ -#define CAN_F2D0R_FD6 ((uint32_t)0x00000040) /*!< Filter bit 6 */ -#define CAN_F2D0R_FD7 ((uint32_t)0x00000080) /*!< Filter bit 7 */ -#define CAN_F2D0R_FD8 ((uint32_t)0x00000100) /*!< Filter bit 8 */ -#define CAN_F2D0R_FD9 ((uint32_t)0x00000200) /*!< Filter bit 9 */ -#define CAN_F2D0R_FD10 ((uint32_t)0x00000400) /*!< Filter bit 10 */ -#define CAN_F2D0R_FD11 ((uint32_t)0x00000800) /*!< Filter bit 11 */ -#define CAN_F2D0R_FD12 ((uint32_t)0x00001000) /*!< Filter bit 12 */ -#define CAN_F2D0R_FD13 ((uint32_t)0x00002000) /*!< Filter bit 13 */ -#define CAN_F2D0R_FD14 ((uint32_t)0x00004000) /*!< Filter bit 14 */ -#define CAN_F2D0R_FD15 ((uint32_t)0x00008000) /*!< Filter bit 15 */ -#define CAN_F2D0R_FD16 ((uint32_t)0x00010000) /*!< Filter bit 16 */ -#define CAN_F2D0R_FD17 ((uint32_t)0x00020000) /*!< Filter bit 17 */ -#define CAN_F2D0R_FD18 ((uint32_t)0x00040000) /*!< Filter bit 18 */ -#define CAN_F2D0R_FD19 ((uint32_t)0x00080000) /*!< Filter bit 19 */ -#define CAN_F2D0R_FD20 ((uint32_t)0x00100000) /*!< Filter bit 20 */ -#define CAN_F2D0R_FD21 ((uint32_t)0x00200000) /*!< Filter bit 21 */ -#define CAN_F2D0R_FD22 ((uint32_t)0x00400000) /*!< Filter bit 22 */ -#define CAN_F2D0R_FD23 ((uint32_t)0x00800000) /*!< Filter bit 23 */ -#define CAN_F2D0R_FD24 ((uint32_t)0x01000000) /*!< Filter bit 24 */ -#define CAN_F2D0R_FD25 ((uint32_t)0x02000000) /*!< Filter bit 25 */ -#define CAN_F2D0R_FD26 ((uint32_t)0x04000000) /*!< Filter bit 26 */ -#define CAN_F2D0R_FD27 ((uint32_t)0x08000000) /*!< Filter bit 27 */ -#define CAN_F2D0R_FD28 ((uint32_t)0x10000000) /*!< Filter bit 28 */ -#define CAN_F2D0R_FD29 ((uint32_t)0x20000000) /*!< Filter bit 29 */ -#define CAN_F2D0R_FD30 ((uint32_t)0x40000000) /*!< Filter bit 30 */ -#define CAN_F2D0R_FD31 ((uint32_t)0x80000000) /*!< Filter bit 31 */ - -/******************* Bit definition for CAN_F3D0R register *******************/ -#define CAN_F3D0R_FD0 ((uint32_t)0x00000001) /*!< Filter bit 0 */ -#define CAN_F3D0R_FD1 ((uint32_t)0x00000002) /*!< Filter bit 1 */ -#define CAN_F3D0R_FD2 ((uint32_t)0x00000004) /*!< Filter bit 2 */ -#define CAN_F3D0R_FD3 ((uint32_t)0x00000008) /*!< Filter bit 3 */ -#define CAN_F3D0R_FD4 ((uint32_t)0x00000010) /*!< Filter bit 4 */ -#define CAN_F3D0R_FD5 ((uint32_t)0x00000020) /*!< Filter bit 5 */ -#define CAN_F3D0R_FD6 ((uint32_t)0x00000040) /*!< Filter bit 6 */ -#define CAN_F3D0R_FD7 ((uint32_t)0x00000080) /*!< Filter bit 7 */ -#define CAN_F3D0R_FD8 ((uint32_t)0x00000100) /*!< Filter bit 8 */ -#define CAN_F3D0R_FD9 ((uint32_t)0x00000200) /*!< Filter bit 9 */ -#define CAN_F3D0R_FD10 ((uint32_t)0x00000400) /*!< Filter bit 10 */ -#define CAN_F3D0R_FD11 ((uint32_t)0x00000800) /*!< Filter bit 11 */ -#define CAN_F3D0R_FD12 ((uint32_t)0x00001000) /*!< Filter bit 12 */ -#define CAN_F3D0R_FD13 ((uint32_t)0x00002000) /*!< Filter bit 13 */ -#define CAN_F3D0R_FD14 ((uint32_t)0x00004000) /*!< Filter bit 14 */ -#define CAN_F3D0R_FD15 ((uint32_t)0x00008000) /*!< Filter bit 15 */ -#define CAN_F3D0R_FD16 ((uint32_t)0x00010000) /*!< Filter bit 16 */ -#define CAN_F3D0R_FD17 ((uint32_t)0x00020000) /*!< Filter bit 17 */ -#define CAN_F3D0R_FD18 ((uint32_t)0x00040000) /*!< Filter bit 18 */ -#define CAN_F3D0R_FD19 ((uint32_t)0x00080000) /*!< Filter bit 19 */ -#define CAN_F3D0R_FD20 ((uint32_t)0x00100000) /*!< Filter bit 20 */ -#define CAN_F3D0R_FD21 ((uint32_t)0x00200000) /*!< Filter bit 21 */ -#define CAN_F3D0R_FD22 ((uint32_t)0x00400000) /*!< Filter bit 22 */ -#define CAN_F3D0R_FD23 ((uint32_t)0x00800000) /*!< Filter bit 23 */ -#define CAN_F3D0R_FD24 ((uint32_t)0x01000000) /*!< Filter bit 24 */ -#define CAN_F3D0R_FD25 ((uint32_t)0x02000000) /*!< Filter bit 25 */ -#define CAN_F3D0R_FD26 ((uint32_t)0x04000000) /*!< Filter bit 26 */ -#define CAN_F3D0R_FD27 ((uint32_t)0x08000000) /*!< Filter bit 27 */ -#define CAN_F3D0R_FD28 ((uint32_t)0x10000000) /*!< Filter bit 28 */ -#define CAN_F3D0R_FD29 ((uint32_t)0x20000000) /*!< Filter bit 29 */ -#define CAN_F3D0R_FD30 ((uint32_t)0x40000000) /*!< Filter bit 30 */ -#define CAN_F3D0R_FD31 ((uint32_t)0x80000000) /*!< Filter bit 31 */ - -/******************* Bit definition for CAN_F4D0R register *******************/ -#define CAN_F4D0R_FD0 ((uint32_t)0x00000001) /*!< Filter bit 0 */ -#define CAN_F4D0R_FD1 ((uint32_t)0x00000002) /*!< Filter bit 1 */ -#define CAN_F4D0R_FD2 ((uint32_t)0x00000004) /*!< Filter bit 2 */ -#define CAN_F4D0R_FD3 ((uint32_t)0x00000008) /*!< Filter bit 3 */ -#define CAN_F4D0R_FD4 ((uint32_t)0x00000010) /*!< Filter bit 4 */ -#define CAN_F4D0R_FD5 ((uint32_t)0x00000020) /*!< Filter bit 5 */ -#define CAN_F4D0R_FD6 ((uint32_t)0x00000040) /*!< Filter bit 6 */ -#define CAN_F4D0R_FD7 ((uint32_t)0x00000080) /*!< Filter bit 7 */ -#define CAN_F4D0R_FD8 ((uint32_t)0x00000100) /*!< Filter bit 8 */ -#define CAN_F4D0R_FD9 ((uint32_t)0x00000200) /*!< Filter bit 9 */ -#define CAN_F4D0R_FD10 ((uint32_t)0x00000400) /*!< Filter bit 10 */ -#define CAN_F4D0R_FD11 ((uint32_t)0x00000800) /*!< Filter bit 11 */ -#define CAN_F4D0R_FD12 ((uint32_t)0x00001000) /*!< Filter bit 12 */ -#define CAN_F4D0R_FD13 ((uint32_t)0x00002000) /*!< Filter bit 13 */ -#define CAN_F4D0R_FD14 ((uint32_t)0x00004000) /*!< Filter bit 14 */ -#define CAN_F4D0R_FD15 ((uint32_t)0x00008000) /*!< Filter bit 15 */ -#define CAN_F4D0R_FD16 ((uint32_t)0x00010000) /*!< Filter bit 16 */ -#define CAN_F4D0R_FD17 ((uint32_t)0x00020000) /*!< Filter bit 17 */ -#define CAN_F4D0R_FD18 ((uint32_t)0x00040000) /*!< Filter bit 18 */ -#define CAN_F4D0R_FD19 ((uint32_t)0x00080000) /*!< Filter bit 19 */ -#define CAN_F4D0R_FD20 ((uint32_t)0x00100000) /*!< Filter bit 20 */ -#define CAN_F4D0R_FD21 ((uint32_t)0x00200000) /*!< Filter bit 21 */ -#define CAN_F4D0R_FD22 ((uint32_t)0x00400000) /*!< Filter bit 22 */ -#define CAN_F4D0R_FD23 ((uint32_t)0x00800000) /*!< Filter bit 23 */ -#define CAN_F4D0R_FD24 ((uint32_t)0x01000000) /*!< Filter bit 24 */ -#define CAN_F4D0R_FD25 ((uint32_t)0x02000000) /*!< Filter bit 25 */ -#define CAN_F4D0R_FD26 ((uint32_t)0x04000000) /*!< Filter bit 26 */ -#define CAN_F4D0R_FD27 ((uint32_t)0x08000000) /*!< Filter bit 27 */ -#define CAN_F4D0R_FD28 ((uint32_t)0x10000000) /*!< Filter bit 28 */ -#define CAN_F4D0R_FD29 ((uint32_t)0x20000000) /*!< Filter bit 29 */ -#define CAN_F4D0R_FD30 ((uint32_t)0x40000000) /*!< Filter bit 30 */ -#define CAN_F4D0R_FD31 ((uint32_t)0x80000000) /*!< Filter bit 31 */ - -/******************* Bit definition for CAN_F5D0R register *******************/ -#define CAN_F5D0R_FD0 ((uint32_t)0x00000001) /*!< Filter bit 0 */ -#define CAN_F5D0R_FD1 ((uint32_t)0x00000002) /*!< Filter bit 1 */ -#define CAN_F5D0R_FD2 ((uint32_t)0x00000004) /*!< Filter bit 2 */ -#define CAN_F5D0R_FD3 ((uint32_t)0x00000008) /*!< Filter bit 3 */ -#define CAN_F5D0R_FD4 ((uint32_t)0x00000010) /*!< Filter bit 4 */ -#define CAN_F5D0R_FD5 ((uint32_t)0x00000020) /*!< Filter bit 5 */ -#define CAN_F5D0R_FD6 ((uint32_t)0x00000040) /*!< Filter bit 6 */ -#define CAN_F5D0R_FD7 ((uint32_t)0x00000080) /*!< Filter bit 7 */ -#define CAN_F5D0R_FD8 ((uint32_t)0x00000100) /*!< Filter bit 8 */ -#define CAN_F5D0R_FD9 ((uint32_t)0x00000200) /*!< Filter bit 9 */ -#define CAN_F5D0R_FD10 ((uint32_t)0x00000400) /*!< Filter bit 10 */ -#define CAN_F5D0R_FD11 ((uint32_t)0x00000800) /*!< Filter bit 11 */ -#define CAN_F5D0R_FD12 ((uint32_t)0x00001000) /*!< Filter bit 12 */ -#define CAN_F5D0R_FD13 ((uint32_t)0x00002000) /*!< Filter bit 13 */ -#define CAN_F5D0R_FD14 ((uint32_t)0x00004000) /*!< Filter bit 14 */ -#define CAN_F5D0R_FD15 ((uint32_t)0x00008000) /*!< Filter bit 15 */ -#define CAN_F5D0R_FD16 ((uint32_t)0x00010000) /*!< Filter bit 16 */ -#define CAN_F5D0R_FD17 ((uint32_t)0x00020000) /*!< Filter bit 17 */ -#define CAN_F5D0R_FD18 ((uint32_t)0x00040000) /*!< Filter bit 18 */ -#define CAN_F5D0R_FD19 ((uint32_t)0x00080000) /*!< Filter bit 19 */ -#define CAN_F5D0R_FD20 ((uint32_t)0x00100000) /*!< Filter bit 20 */ -#define CAN_F5D0R_FD21 ((uint32_t)0x00200000) /*!< Filter bit 21 */ -#define CAN_F5D0R_FD22 ((uint32_t)0x00400000) /*!< Filter bit 22 */ -#define CAN_F5D0R_FD23 ((uint32_t)0x00800000) /*!< Filter bit 23 */ -#define CAN_F5D0R_FD24 ((uint32_t)0x01000000) /*!< Filter bit 24 */ -#define CAN_F5D0R_FD25 ((uint32_t)0x02000000) /*!< Filter bit 25 */ -#define CAN_F5D0R_FD26 ((uint32_t)0x04000000) /*!< Filter bit 26 */ -#define CAN_F5D0R_FD27 ((uint32_t)0x08000000) /*!< Filter bit 27 */ -#define CAN_F5D0R_FD28 ((uint32_t)0x10000000) /*!< Filter bit 28 */ -#define CAN_F5D0R_FD29 ((uint32_t)0x20000000) /*!< Filter bit 29 */ -#define CAN_F5D0R_FD30 ((uint32_t)0x40000000) /*!< Filter bit 30 */ -#define CAN_F5D0R_FD31 ((uint32_t)0x80000000) /*!< Filter bit 31 */ - -/******************* Bit definition for CAN_F6D0R register *******************/ -#define CAN_F6D0R_FD0 ((uint32_t)0x00000001) /*!< Filter bit 0 */ -#define CAN_F6D0R_FD1 ((uint32_t)0x00000002) /*!< Filter bit 1 */ -#define CAN_F6D0R_FD2 ((uint32_t)0x00000004) /*!< Filter bit 2 */ -#define CAN_F6D0R_FD3 ((uint32_t)0x00000008) /*!< Filter bit 3 */ -#define CAN_F6D0R_FD4 ((uint32_t)0x00000010) /*!< Filter bit 4 */ -#define CAN_F6D0R_FD5 ((uint32_t)0x00000020) /*!< Filter bit 5 */ -#define CAN_F6D0R_FD6 ((uint32_t)0x00000040) /*!< Filter bit 6 */ -#define CAN_F6D0R_FD7 ((uint32_t)0x00000080) /*!< Filter bit 7 */ -#define CAN_F6D0R_FD8 ((uint32_t)0x00000100) /*!< Filter bit 8 */ -#define CAN_F6D0R_FD9 ((uint32_t)0x00000200) /*!< Filter bit 9 */ -#define CAN_F6D0R_FD10 ((uint32_t)0x00000400) /*!< Filter bit 10 */ -#define CAN_F6D0R_FD11 ((uint32_t)0x00000800) /*!< Filter bit 11 */ -#define CAN_F6D0R_FD12 ((uint32_t)0x00001000) /*!< Filter bit 12 */ -#define CAN_F6D0R_FD13 ((uint32_t)0x00002000) /*!< Filter bit 13 */ -#define CAN_F6D0R_FD14 ((uint32_t)0x00004000) /*!< Filter bit 14 */ -#define CAN_F6D0R_FD15 ((uint32_t)0x00008000) /*!< Filter bit 15 */ -#define CAN_F6D0R_FD16 ((uint32_t)0x00010000) /*!< Filter bit 16 */ -#define CAN_F6D0R_FD17 ((uint32_t)0x00020000) /*!< Filter bit 17 */ -#define CAN_F6D0R_FD18 ((uint32_t)0x00040000) /*!< Filter bit 18 */ -#define CAN_F6D0R_FD19 ((uint32_t)0x00080000) /*!< Filter bit 19 */ -#define CAN_F6D0R_FD20 ((uint32_t)0x00100000) /*!< Filter bit 20 */ -#define CAN_F6D0R_FD21 ((uint32_t)0x00200000) /*!< Filter bit 21 */ -#define CAN_F6D0R_FD22 ((uint32_t)0x00400000) /*!< Filter bit 22 */ -#define CAN_F6D0R_FD23 ((uint32_t)0x00800000) /*!< Filter bit 23 */ -#define CAN_F6D0R_FD24 ((uint32_t)0x01000000) /*!< Filter bit 24 */ -#define CAN_F6D0R_FD25 ((uint32_t)0x02000000) /*!< Filter bit 25 */ -#define CAN_F6D0R_FD26 ((uint32_t)0x04000000) /*!< Filter bit 26 */ -#define CAN_F6D0R_FD27 ((uint32_t)0x08000000) /*!< Filter bit 27 */ -#define CAN_F6D0R_FD28 ((uint32_t)0x10000000) /*!< Filter bit 28 */ -#define CAN_F6D0R_FD29 ((uint32_t)0x20000000) /*!< Filter bit 29 */ -#define CAN_F6D0R_FD30 ((uint32_t)0x40000000) /*!< Filter bit 30 */ -#define CAN_F6D0R_FD31 ((uint32_t)0x80000000) /*!< Filter bit 31 */ - -/******************* Bit definition for CAN_F7D0R register *******************/ -#define CAN_F7D0R_FD0 ((uint32_t)0x00000001) /*!< Filter bit 0 */ -#define CAN_F7D0R_FD1 ((uint32_t)0x00000002) /*!< Filter bit 1 */ -#define CAN_F7D0R_FD2 ((uint32_t)0x00000004) /*!< Filter bit 2 */ -#define CAN_F7D0R_FD3 ((uint32_t)0x00000008) /*!< Filter bit 3 */ -#define CAN_F7D0R_FD4 ((uint32_t)0x00000010) /*!< Filter bit 4 */ -#define CAN_F7D0R_FD5 ((uint32_t)0x00000020) /*!< Filter bit 5 */ -#define CAN_F7D0R_FD6 ((uint32_t)0x00000040) /*!< Filter bit 6 */ -#define CAN_F7D0R_FD7 ((uint32_t)0x00000080) /*!< Filter bit 7 */ -#define CAN_F7D0R_FD8 ((uint32_t)0x00000100) /*!< Filter bit 8 */ -#define CAN_F7D0R_FD9 ((uint32_t)0x00000200) /*!< Filter bit 9 */ -#define CAN_F7D0R_FD10 ((uint32_t)0x00000400) /*!< Filter bit 10 */ -#define CAN_F7D0R_FD11 ((uint32_t)0x00000800) /*!< Filter bit 11 */ -#define CAN_F7D0R_FD12 ((uint32_t)0x00001000) /*!< Filter bit 12 */ -#define CAN_F7D0R_FD13 ((uint32_t)0x00002000) /*!< Filter bit 13 */ -#define CAN_F7D0R_FD14 ((uint32_t)0x00004000) /*!< Filter bit 14 */ -#define CAN_F7D0R_FD15 ((uint32_t)0x00008000) /*!< Filter bit 15 */ -#define CAN_F7D0R_FD16 ((uint32_t)0x00010000) /*!< Filter bit 16 */ -#define CAN_F7D0R_FD17 ((uint32_t)0x00020000) /*!< Filter bit 17 */ -#define CAN_F7D0R_FD18 ((uint32_t)0x00040000) /*!< Filter bit 18 */ -#define CAN_F7D0R_FD19 ((uint32_t)0x00080000) /*!< Filter bit 19 */ -#define CAN_F7D0R_FD20 ((uint32_t)0x00100000) /*!< Filter bit 20 */ -#define CAN_F7D0R_FD21 ((uint32_t)0x00200000) /*!< Filter bit 21 */ -#define CAN_F7D0R_FD22 ((uint32_t)0x00400000) /*!< Filter bit 22 */ -#define CAN_F7D0R_FD23 ((uint32_t)0x00800000) /*!< Filter bit 23 */ -#define CAN_F7D0R_FD24 ((uint32_t)0x01000000) /*!< Filter bit 24 */ -#define CAN_F7D0R_FD25 ((uint32_t)0x02000000) /*!< Filter bit 25 */ -#define CAN_F7D0R_FD26 ((uint32_t)0x04000000) /*!< Filter bit 26 */ -#define CAN_F7D0R_FD27 ((uint32_t)0x08000000) /*!< Filter bit 27 */ -#define CAN_F7D0R_FD28 ((uint32_t)0x10000000) /*!< Filter bit 28 */ -#define CAN_F7D0R_FD29 ((uint32_t)0x20000000) /*!< Filter bit 29 */ -#define CAN_F7D0R_FD30 ((uint32_t)0x40000000) /*!< Filter bit 30 */ -#define CAN_F7D0R_FD31 ((uint32_t)0x80000000) /*!< Filter bit 31 */ - -/******************* Bit definition for CAN_F8D0R register *******************/ -#define CAN_F8D0R_FD0 ((uint32_t)0x00000001) /*!< Filter bit 0 */ -#define CAN_F8D0R_FD1 ((uint32_t)0x00000002) /*!< Filter bit 1 */ -#define CAN_F8D0R_FD2 ((uint32_t)0x00000004) /*!< Filter bit 2 */ -#define CAN_F8D0R_FD3 ((uint32_t)0x00000008) /*!< Filter bit 3 */ -#define CAN_F8D0R_FD4 ((uint32_t)0x00000010) /*!< Filter bit 4 */ -#define CAN_F8D0R_FD5 ((uint32_t)0x00000020) /*!< Filter bit 5 */ -#define CAN_F8D0R_FD6 ((uint32_t)0x00000040) /*!< Filter bit 6 */ -#define CAN_F8D0R_FD7 ((uint32_t)0x00000080) /*!< Filter bit 7 */ -#define CAN_F8D0R_FD8 ((uint32_t)0x00000100) /*!< Filter bit 8 */ -#define CAN_F8D0R_FD9 ((uint32_t)0x00000200) /*!< Filter bit 9 */ -#define CAN_F8D0R_FD10 ((uint32_t)0x00000400) /*!< Filter bit 10 */ -#define CAN_F8D0R_FD11 ((uint32_t)0x00000800) /*!< Filter bit 11 */ -#define CAN_F8D0R_FD12 ((uint32_t)0x00001000) /*!< Filter bit 12 */ -#define CAN_F8D0R_FD13 ((uint32_t)0x00002000) /*!< Filter bit 13 */ -#define CAN_F8D0R_FD14 ((uint32_t)0x00004000) /*!< Filter bit 14 */ -#define CAN_F8D0R_FD15 ((uint32_t)0x00008000) /*!< Filter bit 15 */ -#define CAN_F8D0R_FD16 ((uint32_t)0x00010000) /*!< Filter bit 16 */ -#define CAN_F8D0R_FD17 ((uint32_t)0x00020000) /*!< Filter bit 17 */ -#define CAN_F8D0R_FD18 ((uint32_t)0x00040000) /*!< Filter bit 18 */ -#define CAN_F8D0R_FD19 ((uint32_t)0x00080000) /*!< Filter bit 19 */ -#define CAN_F8D0R_FD20 ((uint32_t)0x00100000) /*!< Filter bit 20 */ -#define CAN_F8D0R_FD21 ((uint32_t)0x00200000) /*!< Filter bit 21 */ -#define CAN_F8D0R_FD22 ((uint32_t)0x00400000) /*!< Filter bit 22 */ -#define CAN_F8D0R_FD23 ((uint32_t)0x00800000) /*!< Filter bit 23 */ -#define CAN_F8D0R_FD24 ((uint32_t)0x01000000) /*!< Filter bit 24 */ -#define CAN_F8D0R_FD25 ((uint32_t)0x02000000) /*!< Filter bit 25 */ -#define CAN_F8D0R_FD26 ((uint32_t)0x04000000) /*!< Filter bit 26 */ -#define CAN_F8D0R_FD27 ((uint32_t)0x08000000) /*!< Filter bit 27 */ -#define CAN_F8D0R_FD28 ((uint32_t)0x10000000) /*!< Filter bit 28 */ -#define CAN_F8D0R_FD29 ((uint32_t)0x20000000) /*!< Filter bit 29 */ -#define CAN_F8D0R_FD30 ((uint32_t)0x40000000) /*!< Filter bit 30 */ -#define CAN_F8D0R_FD31 ((uint32_t)0x80000000) /*!< Filter bit 31 */ - -/******************* Bit definition for CAN_F9D0R register *******************/ -#define CAN_F9D0R_FD0 ((uint32_t)0x00000001) /*!< Filter bit 0 */ -#define CAN_F9D0R_FD1 ((uint32_t)0x00000002) /*!< Filter bit 1 */ -#define CAN_F9D0R_FD2 ((uint32_t)0x00000004) /*!< Filter bit 2 */ -#define CAN_F9D0R_FD3 ((uint32_t)0x00000008) /*!< Filter bit 3 */ -#define CAN_F9D0R_FD4 ((uint32_t)0x00000010) /*!< Filter bit 4 */ -#define CAN_F9D0R_FD5 ((uint32_t)0x00000020) /*!< Filter bit 5 */ -#define CAN_F9D0R_FD6 ((uint32_t)0x00000040) /*!< Filter bit 6 */ -#define CAN_F9D0R_FD7 ((uint32_t)0x00000080) /*!< Filter bit 7 */ -#define CAN_F9D0R_FD8 ((uint32_t)0x00000100) /*!< Filter bit 8 */ -#define CAN_F9D0R_FD9 ((uint32_t)0x00000200) /*!< Filter bit 9 */ -#define CAN_F9D0R_FD10 ((uint32_t)0x00000400) /*!< Filter bit 10 */ -#define CAN_F9D0R_FD11 ((uint32_t)0x00000800) /*!< Filter bit 11 */ -#define CAN_F9D0R_FD12 ((uint32_t)0x00001000) /*!< Filter bit 12 */ -#define CAN_F9D0R_FD13 ((uint32_t)0x00002000) /*!< Filter bit 13 */ -#define CAN_F9D0R_FD14 ((uint32_t)0x00004000) /*!< Filter bit 14 */ -#define CAN_F9D0R_FD15 ((uint32_t)0x00008000) /*!< Filter bit 15 */ -#define CAN_F9D0R_FD16 ((uint32_t)0x00010000) /*!< Filter bit 16 */ -#define CAN_F9D0R_FD17 ((uint32_t)0x00020000) /*!< Filter bit 17 */ -#define CAN_F9D0R_FD18 ((uint32_t)0x00040000) /*!< Filter bit 18 */ -#define CAN_F9D0R_FD19 ((uint32_t)0x00080000) /*!< Filter bit 19 */ -#define CAN_F9D0R_FD20 ((uint32_t)0x00100000) /*!< Filter bit 20 */ -#define CAN_F9D0R_FD21 ((uint32_t)0x00200000) /*!< Filter bit 21 */ -#define CAN_F9D0R_FD22 ((uint32_t)0x00400000) /*!< Filter bit 22 */ -#define CAN_F9D0R_FD23 ((uint32_t)0x00800000) /*!< Filter bit 23 */ -#define CAN_F9D0R_FD24 ((uint32_t)0x01000000) /*!< Filter bit 24 */ -#define CAN_F9D0R_FD25 ((uint32_t)0x02000000) /*!< Filter bit 25 */ -#define CAN_F9D0R_FD26 ((uint32_t)0x04000000) /*!< Filter bit 26 */ -#define CAN_F9D0R_FD27 ((uint32_t)0x08000000) /*!< Filter bit 27 */ -#define CAN_F9D0R_FD28 ((uint32_t)0x10000000) /*!< Filter bit 28 */ -#define CAN_F9D0R_FD29 ((uint32_t)0x20000000) /*!< Filter bit 29 */ -#define CAN_F9D0R_FD30 ((uint32_t)0x40000000) /*!< Filter bit 30 */ -#define CAN_F9D0R_FD31 ((uint32_t)0x80000000) /*!< Filter bit 31 */ - -/******************* Bit definition for CAN_F10D0R register ******************/ -#define CAN_F10D0R_FD0 ((uint32_t)0x00000001) /*!< Filter bit 0 */ -#define CAN_F10D0R_FD1 ((uint32_t)0x00000002) /*!< Filter bit 1 */ -#define CAN_F10D0R_FD2 ((uint32_t)0x00000004) /*!< Filter bit 2 */ -#define CAN_F10D0R_FD3 ((uint32_t)0x00000008) /*!< Filter bit 3 */ -#define CAN_F10D0R_FD4 ((uint32_t)0x00000010) /*!< Filter bit 4 */ -#define CAN_F10D0R_FD5 ((uint32_t)0x00000020) /*!< Filter bit 5 */ -#define CAN_F10D0R_FD6 ((uint32_t)0x00000040) /*!< Filter bit 6 */ -#define CAN_F10D0R_FD7 ((uint32_t)0x00000080) /*!< Filter bit 7 */ -#define CAN_F10D0R_FD8 ((uint32_t)0x00000100) /*!< Filter bit 8 */ -#define CAN_F10D0R_FD9 ((uint32_t)0x00000200) /*!< Filter bit 9 */ -#define CAN_F10D0R_FD10 ((uint32_t)0x00000400) /*!< Filter bit 10 */ -#define CAN_F10D0R_FD11 ((uint32_t)0x00000800) /*!< Filter bit 11 */ -#define CAN_F10D0R_FD12 ((uint32_t)0x00001000) /*!< Filter bit 12 */ -#define CAN_F10D0R_FD13 ((uint32_t)0x00002000) /*!< Filter bit 13 */ -#define CAN_F10D0R_FD14 ((uint32_t)0x00004000) /*!< Filter bit 14 */ -#define CAN_F10D0R_FD15 ((uint32_t)0x00008000) /*!< Filter bit 15 */ -#define CAN_F10D0R_FD16 ((uint32_t)0x00010000) /*!< Filter bit 16 */ -#define CAN_F10D0R_FD17 ((uint32_t)0x00020000) /*!< Filter bit 17 */ -#define CAN_F10D0R_FD18 ((uint32_t)0x00040000) /*!< Filter bit 18 */ -#define CAN_F10D0R_FD19 ((uint32_t)0x00080000) /*!< Filter bit 19 */ -#define CAN_F10D0R_FD20 ((uint32_t)0x00100000) /*!< Filter bit 20 */ -#define CAN_F10D0R_FD21 ((uint32_t)0x00200000) /*!< Filter bit 21 */ -#define CAN_F10D0R_FD22 ((uint32_t)0x00400000) /*!< Filter bit 22 */ -#define CAN_F10D0R_FD23 ((uint32_t)0x00800000) /*!< Filter bit 23 */ -#define CAN_F10D0R_FD24 ((uint32_t)0x01000000) /*!< Filter bit 24 */ -#define CAN_F10D0R_FD25 ((uint32_t)0x02000000) /*!< Filter bit 25 */ -#define CAN_F10D0R_FD26 ((uint32_t)0x04000000) /*!< Filter bit 26 */ -#define CAN_F10D0R_FD27 ((uint32_t)0x08000000) /*!< Filter bit 27 */ -#define CAN_F10D0R_FD28 ((uint32_t)0x10000000) /*!< Filter bit 28 */ -#define CAN_F10D0R_FD29 ((uint32_t)0x20000000) /*!< Filter bit 29 */ -#define CAN_F10D0R_FD30 ((uint32_t)0x40000000) /*!< Filter bit 30 */ -#define CAN_F10D0R_FD31 ((uint32_t)0x80000000) /*!< Filter bit 31 */ - -/******************* Bit definition for CAN_F11D0R register ******************/ -#define CAN_F11D0R_FD0 ((uint32_t)0x00000001) /*!< Filter bit 0 */ -#define CAN_F11D0R_FD1 ((uint32_t)0x00000002) /*!< Filter bit 1 */ -#define CAN_F11D0R_FD2 ((uint32_t)0x00000004) /*!< Filter bit 2 */ -#define CAN_F11D0R_FD3 ((uint32_t)0x00000008) /*!< Filter bit 3 */ -#define CAN_F11D0R_FD4 ((uint32_t)0x00000010) /*!< Filter bit 4 */ -#define CAN_F11D0R_FD5 ((uint32_t)0x00000020) /*!< Filter bit 5 */ -#define CAN_F11D0R_FD6 ((uint32_t)0x00000040) /*!< Filter bit 6 */ -#define CAN_F11D0R_FD7 ((uint32_t)0x00000080) /*!< Filter bit 7 */ -#define CAN_F11D0R_FD8 ((uint32_t)0x00000100) /*!< Filter bit 8 */ -#define CAN_F11D0R_FD9 ((uint32_t)0x00000200) /*!< Filter bit 9 */ -#define CAN_F11D0R_FD10 ((uint32_t)0x00000400) /*!< Filter bit 10 */ -#define CAN_F11D0R_FD11 ((uint32_t)0x00000800) /*!< Filter bit 11 */ -#define CAN_F11D0R_FD12 ((uint32_t)0x00001000) /*!< Filter bit 12 */ -#define CAN_F11D0R_FD13 ((uint32_t)0x00002000) /*!< Filter bit 13 */ -#define CAN_F11D0R_FD14 ((uint32_t)0x00004000) /*!< Filter bit 14 */ -#define CAN_F11D0R_FD15 ((uint32_t)0x00008000) /*!< Filter bit 15 */ -#define CAN_F11D0R_FD16 ((uint32_t)0x00010000) /*!< Filter bit 16 */ -#define CAN_F11D0R_FD17 ((uint32_t)0x00020000) /*!< Filter bit 17 */ -#define CAN_F11D0R_FD18 ((uint32_t)0x00040000) /*!< Filter bit 18 */ -#define CAN_F11D0R_FD19 ((uint32_t)0x00080000) /*!< Filter bit 19 */ -#define CAN_F11D0R_FD20 ((uint32_t)0x00100000) /*!< Filter bit 20 */ -#define CAN_F11D0R_FD21 ((uint32_t)0x00200000) /*!< Filter bit 21 */ -#define CAN_F11D0R_FD22 ((uint32_t)0x00400000) /*!< Filter bit 22 */ -#define CAN_F11D0R_FD23 ((uint32_t)0x00800000) /*!< Filter bit 23 */ -#define CAN_F11D0R_FD24 ((uint32_t)0x01000000) /*!< Filter bit 24 */ -#define CAN_F11D0R_FD25 ((uint32_t)0x02000000) /*!< Filter bit 25 */ -#define CAN_F11D0R_FD26 ((uint32_t)0x04000000) /*!< Filter bit 26 */ -#define CAN_F11D0R_FD27 ((uint32_t)0x08000000) /*!< Filter bit 27 */ -#define CAN_F11D0R_FD28 ((uint32_t)0x10000000) /*!< Filter bit 28 */ -#define CAN_F11D0R_FD29 ((uint32_t)0x20000000) /*!< Filter bit 29 */ -#define CAN_F11D0R_FD30 ((uint32_t)0x40000000) /*!< Filter bit 30 */ -#define CAN_F11D0R_FD31 ((uint32_t)0x80000000) /*!< Filter bit 31 */ - -/******************* Bit definition for CAN_F12D0R register ******************/ -#define CAN_F12D0R_FD0 ((uint32_t)0x00000001) /*!< Filter bit 0 */ -#define CAN_F12D0R_FD1 ((uint32_t)0x00000002) /*!< Filter bit 1 */ -#define CAN_F12D0R_FD2 ((uint32_t)0x00000004) /*!< Filter bit 2 */ -#define CAN_F12D0R_FD3 ((uint32_t)0x00000008) /*!< Filter bit 3 */ -#define CAN_F12D0R_FD4 ((uint32_t)0x00000010) /*!< Filter bit 4 */ -#define CAN_F12D0R_FD5 ((uint32_t)0x00000020) /*!< Filter bit 5 */ -#define CAN_F12D0R_FD6 ((uint32_t)0x00000040) /*!< Filter bit 6 */ -#define CAN_F12D0R_FD7 ((uint32_t)0x00000080) /*!< Filter bit 7 */ -#define CAN_F12D0R_FD8 ((uint32_t)0x00000100) /*!< Filter bit 8 */ -#define CAN_F12D0R_FD9 ((uint32_t)0x00000200) /*!< Filter bit 9 */ -#define CAN_F12D0R_FD10 ((uint32_t)0x00000400) /*!< Filter bit 10 */ -#define CAN_F12D0R_FD11 ((uint32_t)0x00000800) /*!< Filter bit 11 */ -#define CAN_F12D0R_FD12 ((uint32_t)0x00001000) /*!< Filter bit 12 */ -#define CAN_F12D0R_FD13 ((uint32_t)0x00002000) /*!< Filter bit 13 */ -#define CAN_F12D0R_FD14 ((uint32_t)0x00004000) /*!< Filter bit 14 */ -#define CAN_F12D0R_FD15 ((uint32_t)0x00008000) /*!< Filter bit 15 */ -#define CAN_F12D0R_FD16 ((uint32_t)0x00010000) /*!< Filter bit 16 */ -#define CAN_F12D0R_FD17 ((uint32_t)0x00020000) /*!< Filter bit 17 */ -#define CAN_F12D0R_FD18 ((uint32_t)0x00040000) /*!< Filter bit 18 */ -#define CAN_F12D0R_FD19 ((uint32_t)0x00080000) /*!< Filter bit 19 */ -#define CAN_F12D0R_FD20 ((uint32_t)0x00100000) /*!< Filter bit 20 */ -#define CAN_F12D0R_FD21 ((uint32_t)0x00200000) /*!< Filter bit 21 */ -#define CAN_F12D0R_FD22 ((uint32_t)0x00400000) /*!< Filter bit 22 */ -#define CAN_F12D0R_FD23 ((uint32_t)0x00800000) /*!< Filter bit 23 */ -#define CAN_F12D0R_FD24 ((uint32_t)0x01000000) /*!< Filter bit 24 */ -#define CAN_F12D0R_FD25 ((uint32_t)0x02000000) /*!< Filter bit 25 */ -#define CAN_F12D0R_FD26 ((uint32_t)0x04000000) /*!< Filter bit 26 */ -#define CAN_F12D0R_FD27 ((uint32_t)0x08000000) /*!< Filter bit 27 */ -#define CAN_F12D0R_FD28 ((uint32_t)0x10000000) /*!< Filter bit 28 */ -#define CAN_F12D0R_FD29 ((uint32_t)0x20000000) /*!< Filter bit 29 */ -#define CAN_F12D0R_FD30 ((uint32_t)0x40000000) /*!< Filter bit 30 */ -#define CAN_F12D0R_FD31 ((uint32_t)0x80000000) /*!< Filter bit 31 */ - -/******************* Bit definition for CAN_F13D0R register ******************/ -#define CAN_F13D0R_FD0 ((uint32_t)0x00000001) /*!< Filter bit 0 */ -#define CAN_F13D0R_FD1 ((uint32_t)0x00000002) /*!< Filter bit 1 */ -#define CAN_F13D0R_FD2 ((uint32_t)0x00000004) /*!< Filter bit 2 */ -#define CAN_F13D0R_FD3 ((uint32_t)0x00000008) /*!< Filter bit 3 */ -#define CAN_F13D0R_FD4 ((uint32_t)0x00000010) /*!< Filter bit 4 */ -#define CAN_F13D0R_FD5 ((uint32_t)0x00000020) /*!< Filter bit 5 */ -#define CAN_F13D0R_FD6 ((uint32_t)0x00000040) /*!< Filter bit 6 */ -#define CAN_F13D0R_FD7 ((uint32_t)0x00000080) /*!< Filter bit 7 */ -#define CAN_F13D0R_FD8 ((uint32_t)0x00000100) /*!< Filter bit 8 */ -#define CAN_F13D0R_FD9 ((uint32_t)0x00000200) /*!< Filter bit 9 */ -#define CAN_F13D0R_FD10 ((uint32_t)0x00000400) /*!< Filter bit 10 */ -#define CAN_F13D0R_FD11 ((uint32_t)0x00000800) /*!< Filter bit 11 */ -#define CAN_F13D0R_FD12 ((uint32_t)0x00001000) /*!< Filter bit 12 */ -#define CAN_F13D0R_FD13 ((uint32_t)0x00002000) /*!< Filter bit 13 */ -#define CAN_F13D0R_FD14 ((uint32_t)0x00004000) /*!< Filter bit 14 */ -#define CAN_F13D0R_FD15 ((uint32_t)0x00008000) /*!< Filter bit 15 */ -#define CAN_F13D0R_FD16 ((uint32_t)0x00010000) /*!< Filter bit 16 */ -#define CAN_F13D0R_FD17 ((uint32_t)0x00020000) /*!< Filter bit 17 */ -#define CAN_F13D0R_FD18 ((uint32_t)0x00040000) /*!< Filter bit 18 */ -#define CAN_F13D0R_FD19 ((uint32_t)0x00080000) /*!< Filter bit 19 */ -#define CAN_F13D0R_FD20 ((uint32_t)0x00100000) /*!< Filter bit 20 */ -#define CAN_F13D0R_FD21 ((uint32_t)0x00200000) /*!< Filter bit 21 */ -#define CAN_F13D0R_FD22 ((uint32_t)0x00400000) /*!< Filter bit 22 */ -#define CAN_F13D0R_FD23 ((uint32_t)0x00800000) /*!< Filter bit 23 */ -#define CAN_F13D0R_FD24 ((uint32_t)0x01000000) /*!< Filter bit 24 */ -#define CAN_F13D0R_FD25 ((uint32_t)0x02000000) /*!< Filter bit 25 */ -#define CAN_F13D0R_FD26 ((uint32_t)0x04000000) /*!< Filter bit 26 */ -#define CAN_F13D0R_FD27 ((uint32_t)0x08000000) /*!< Filter bit 27 */ -#define CAN_F13D0R_FD28 ((uint32_t)0x10000000) /*!< Filter bit 28 */ -#define CAN_F13D0R_FD29 ((uint32_t)0x20000000) /*!< Filter bit 29 */ -#define CAN_F13D0R_FD30 ((uint32_t)0x40000000) /*!< Filter bit 30 */ -#define CAN_F13D0R_FD31 ((uint32_t)0x80000000) /*!< Filter bit 31 */ - -/******************* Bit definition for CAN_F14D0R register ******************/ -#define CAN_F14D0R_FD0 ((uint32_t)0x00000001) /*!< Filter bit 0 */ -#define CAN_F14D0R_FD1 ((uint32_t)0x00000002) /*!< Filter bit 1 */ -#define CAN_F14D0R_FD2 ((uint32_t)0x00000004) /*!< Filter bit 2 */ -#define CAN_F14D0R_FD3 ((uint32_t)0x00000008) /*!< Filter bit 3 */ -#define CAN_F14D0R_FD4 ((uint32_t)0x00000010) /*!< Filter bit 4 */ -#define CAN_F14D0R_FD5 ((uint32_t)0x00000020) /*!< Filter bit 5 */ -#define CAN_F14D0R_FD6 ((uint32_t)0x00000040) /*!< Filter bit 6 */ -#define CAN_F14D0R_FD7 ((uint32_t)0x00000080) /*!< Filter bit 7 */ -#define CAN_F14D0R_FD8 ((uint32_t)0x00000100) /*!< Filter bit 8 */ -#define CAN_F14D0R_FD9 ((uint32_t)0x00000200) /*!< Filter bit 9 */ -#define CAN_F14D0R_FD10 ((uint32_t)0x00000400) /*!< Filter bit 10 */ -#define CAN_F14D0R_FD11 ((uint32_t)0x00000800) /*!< Filter bit 11 */ -#define CAN_F14D0R_FD12 ((uint32_t)0x00001000) /*!< Filter bit 12 */ -#define CAN_F14D0R_FD13 ((uint32_t)0x00002000) /*!< Filter bit 13 */ -#define CAN_F14D0R_FD14 ((uint32_t)0x00004000) /*!< Filter bit 14 */ -#define CAN_F14D0R_FD15 ((uint32_t)0x00008000) /*!< Filter bit 15 */ -#define CAN_F14D0R_FD16 ((uint32_t)0x00010000) /*!< Filter bit 16 */ -#define CAN_F14D0R_FD17 ((uint32_t)0x00020000) /*!< Filter bit 17 */ -#define CAN_F14D0R_FD18 ((uint32_t)0x00040000) /*!< Filter bit 18 */ -#define CAN_F14D0R_FD19 ((uint32_t)0x00080000) /*!< Filter bit 19 */ -#define CAN_F14D0R_FD20 ((uint32_t)0x00100000) /*!< Filter bit 20 */ -#define CAN_F14D0R_FD21 ((uint32_t)0x00200000) /*!< Filter bit 21 */ -#define CAN_F14D0R_FD22 ((uint32_t)0x00400000) /*!< Filter bit 22 */ -#define CAN_F14D0R_FD23 ((uint32_t)0x00800000) /*!< Filter bit 23 */ -#define CAN_F14D0R_FD24 ((uint32_t)0x01000000) /*!< Filter bit 24 */ -#define CAN_F14D0R_FD25 ((uint32_t)0x02000000) /*!< Filter bit 25 */ -#define CAN_F14D0R_FD26 ((uint32_t)0x04000000) /*!< Filter bit 26 */ -#define CAN_F14D0R_FD27 ((uint32_t)0x08000000) /*!< Filter bit 27 */ -#define CAN_F14D0R_FD28 ((uint32_t)0x10000000) /*!< Filter bit 28 */ -#define CAN_F14D0R_FD29 ((uint32_t)0x20000000) /*!< Filter bit 29 */ -#define CAN_F14D0R_FD30 ((uint32_t)0x40000000) /*!< Filter bit 30 */ -#define CAN_F14D0R_FD31 ((uint32_t)0x80000000) /*!< Filter bit 31 */ - -/******************* Bit definition for CAN_F15D0R register ******************/ -#define CAN_F15D0R_FD0 ((uint32_t)0x00000001) /*!< Filter bit 0 */ -#define CAN_F15D0R_FD1 ((uint32_t)0x00000002) /*!< Filter bit 1 */ -#define CAN_F15D0R_FD2 ((uint32_t)0x00000004) /*!< Filter bit 2 */ -#define CAN_F15D0R_FD3 ((uint32_t)0x00000008) /*!< Filter bit 3 */ -#define CAN_F15D0R_FD4 ((uint32_t)0x00000010) /*!< Filter bit 4 */ -#define CAN_F15D0R_FD5 ((uint32_t)0x00000020) /*!< Filter bit 5 */ -#define CAN_F15D0R_FD6 ((uint32_t)0x00000040) /*!< Filter bit 6 */ -#define CAN_F15D0R_FD7 ((uint32_t)0x00000080) /*!< Filter bit 7 */ -#define CAN_F15D0R_FD8 ((uint32_t)0x00000100) /*!< Filter bit 8 */ -#define CAN_F15D0R_FD9 ((uint32_t)0x00000200) /*!< Filter bit 9 */ -#define CAN_F15D0R_FD10 ((uint32_t)0x00000400) /*!< Filter bit 10 */ -#define CAN_F15D0R_FD11 ((uint32_t)0x00000800) /*!< Filter bit 11 */ -#define CAN_F15D0R_FD12 ((uint32_t)0x00001000) /*!< Filter bit 12 */ -#define CAN_F15D0R_FD13 ((uint32_t)0x00002000) /*!< Filter bit 13 */ -#define CAN_F15D0R_FD14 ((uint32_t)0x00004000) /*!< Filter bit 14 */ -#define CAN_F15D0R_FD15 ((uint32_t)0x00008000) /*!< Filter bit 15 */ -#define CAN_F15D0R_FD16 ((uint32_t)0x00010000) /*!< Filter bit 16 */ -#define CAN_F15D0R_FD17 ((uint32_t)0x00020000) /*!< Filter bit 17 */ -#define CAN_F15D0R_FD18 ((uint32_t)0x00040000) /*!< Filter bit 18 */ -#define CAN_F15D0R_FD19 ((uint32_t)0x00080000) /*!< Filter bit 19 */ -#define CAN_F15D0R_FD20 ((uint32_t)0x00100000) /*!< Filter bit 20 */ -#define CAN_F15D0R_FD21 ((uint32_t)0x00200000) /*!< Filter bit 21 */ -#define CAN_F15D0R_FD22 ((uint32_t)0x00400000) /*!< Filter bit 22 */ -#define CAN_F15D0R_FD23 ((uint32_t)0x00800000) /*!< Filter bit 23 */ -#define CAN_F15D0R_FD24 ((uint32_t)0x01000000) /*!< Filter bit 24 */ -#define CAN_F15D0R_FD25 ((uint32_t)0x02000000) /*!< Filter bit 25 */ -#define CAN_F15D0R_FD26 ((uint32_t)0x04000000) /*!< Filter bit 26 */ -#define CAN_F15D0R_FD27 ((uint32_t)0x08000000) /*!< Filter bit 27 */ -#define CAN_F15D0R_FD28 ((uint32_t)0x10000000) /*!< Filter bit 28 */ -#define CAN_F15D0R_FD29 ((uint32_t)0x20000000) /*!< Filter bit 29 */ -#define CAN_F15D0R_FD30 ((uint32_t)0x40000000) /*!< Filter bit 30 */ -#define CAN_F15D0R_FD31 ((uint32_t)0x80000000) /*!< Filter bit 31 */ - -/******************* Bit definition for CAN_F16D0R register ******************/ -#define CAN_F16D0R_FD0 ((uint32_t)0x00000001) /*!< Filter bit 0 */ -#define CAN_F16D0R_FD1 ((uint32_t)0x00000002) /*!< Filter bit 1 */ -#define CAN_F16D0R_FD2 ((uint32_t)0x00000004) /*!< Filter bit 2 */ -#define CAN_F16D0R_FD3 ((uint32_t)0x00000008) /*!< Filter bit 3 */ -#define CAN_F16D0R_FD4 ((uint32_t)0x00000010) /*!< Filter bit 4 */ -#define CAN_F16D0R_FD5 ((uint32_t)0x00000020) /*!< Filter bit 5 */ -#define CAN_F16D0R_FD6 ((uint32_t)0x00000040) /*!< Filter bit 6 */ -#define CAN_F16D0R_FD7 ((uint32_t)0x00000080) /*!< Filter bit 7 */ -#define CAN_F16D0R_FD8 ((uint32_t)0x00000100) /*!< Filter bit 8 */ -#define CAN_F16D0R_FD9 ((uint32_t)0x00000200) /*!< Filter bit 9 */ -#define CAN_F16D0R_FD10 ((uint32_t)0x00000400) /*!< Filter bit 10 */ -#define CAN_F16D0R_FD11 ((uint32_t)0x00000800) /*!< Filter bit 11 */ -#define CAN_F16D0R_FD12 ((uint32_t)0x00001000) /*!< Filter bit 12 */ -#define CAN_F16D0R_FD13 ((uint32_t)0x00002000) /*!< Filter bit 13 */ -#define CAN_F16D0R_FD14 ((uint32_t)0x00004000) /*!< Filter bit 14 */ -#define CAN_F16D0R_FD15 ((uint32_t)0x00008000) /*!< Filter bit 15 */ -#define CAN_F16D0R_FD16 ((uint32_t)0x00010000) /*!< Filter bit 16 */ -#define CAN_F16D0R_FD17 ((uint32_t)0x00020000) /*!< Filter bit 17 */ -#define CAN_F16D0R_FD18 ((uint32_t)0x00040000) /*!< Filter bit 18 */ -#define CAN_F16D0R_FD19 ((uint32_t)0x00080000) /*!< Filter bit 19 */ -#define CAN_F16D0R_FD20 ((uint32_t)0x00100000) /*!< Filter bit 20 */ -#define CAN_F16D0R_FD21 ((uint32_t)0x00200000) /*!< Filter bit 21 */ -#define CAN_F16D0R_FD22 ((uint32_t)0x00400000) /*!< Filter bit 22 */ -#define CAN_F16D0R_FD23 ((uint32_t)0x00800000) /*!< Filter bit 23 */ -#define CAN_F16D0R_FD24 ((uint32_t)0x01000000) /*!< Filter bit 24 */ -#define CAN_F16D0R_FD25 ((uint32_t)0x02000000) /*!< Filter bit 25 */ -#define CAN_F16D0R_FD26 ((uint32_t)0x04000000) /*!< Filter bit 26 */ -#define CAN_F16D0R_FD27 ((uint32_t)0x08000000) /*!< Filter bit 27 */ -#define CAN_F16D0R_FD28 ((uint32_t)0x10000000) /*!< Filter bit 28 */ -#define CAN_F16D0R_FD29 ((uint32_t)0x20000000) /*!< Filter bit 29 */ -#define CAN_F16D0R_FD30 ((uint32_t)0x40000000) /*!< Filter bit 30 */ -#define CAN_F16D0R_FD31 ((uint32_t)0x80000000) /*!< Filter bit 31 */ - -/******************* Bit definition for CAN_F17D0R register ******************/ -#define CAN_F17D0R_FD0 ((uint32_t)0x00000001) /*!< Filter bit 0 */ -#define CAN_F17D0R_FD1 ((uint32_t)0x00000002) /*!< Filter bit 1 */ -#define CAN_F17D0R_FD2 ((uint32_t)0x00000004) /*!< Filter bit 2 */ -#define CAN_F17D0R_FD3 ((uint32_t)0x00000008) /*!< Filter bit 3 */ -#define CAN_F17D0R_FD4 ((uint32_t)0x00000010) /*!< Filter bit 4 */ -#define CAN_F17D0R_FD5 ((uint32_t)0x00000020) /*!< Filter bit 5 */ -#define CAN_F17D0R_FD6 ((uint32_t)0x00000040) /*!< Filter bit 6 */ -#define CAN_F17D0R_FD7 ((uint32_t)0x00000080) /*!< Filter bit 7 */ -#define CAN_F17D0R_FD8 ((uint32_t)0x00000100) /*!< Filter bit 8 */ -#define CAN_F17D0R_FD9 ((uint32_t)0x00000200) /*!< Filter bit 9 */ -#define CAN_F17D0R_FD10 ((uint32_t)0x00000400) /*!< Filter bit 10 */ -#define CAN_F17D0R_FD11 ((uint32_t)0x00000800) /*!< Filter bit 11 */ -#define CAN_F17D0R_FD12 ((uint32_t)0x00001000) /*!< Filter bit 12 */ -#define CAN_F17D0R_FD13 ((uint32_t)0x00002000) /*!< Filter bit 13 */ -#define CAN_F17D0R_FD14 ((uint32_t)0x00004000) /*!< Filter bit 14 */ -#define CAN_F17D0R_FD15 ((uint32_t)0x00008000) /*!< Filter bit 15 */ -#define CAN_F17D0R_FD16 ((uint32_t)0x00010000) /*!< Filter bit 16 */ -#define CAN_F17D0R_FD17 ((uint32_t)0x00020000) /*!< Filter bit 17 */ -#define CAN_F17D0R_FD18 ((uint32_t)0x00040000) /*!< Filter bit 18 */ -#define CAN_F17D0R_FD19 ((uint32_t)0x00080000) /*!< Filter bit 19 */ -#define CAN_F17D0R_FD20 ((uint32_t)0x00100000) /*!< Filter bit 20 */ -#define CAN_F17D0R_FD21 ((uint32_t)0x00200000) /*!< Filter bit 21 */ -#define CAN_F17D0R_FD22 ((uint32_t)0x00400000) /*!< Filter bit 22 */ -#define CAN_F17D0R_FD23 ((uint32_t)0x00800000) /*!< Filter bit 23 */ -#define CAN_F17D0R_FD24 ((uint32_t)0x01000000) /*!< Filter bit 24 */ -#define CAN_F17D0R_FD25 ((uint32_t)0x02000000) /*!< Filter bit 25 */ -#define CAN_F17D0R_FD26 ((uint32_t)0x04000000) /*!< Filter bit 26 */ -#define CAN_F17D0R_FD27 ((uint32_t)0x08000000) /*!< Filter bit 27 */ -#define CAN_F17D0R_FD28 ((uint32_t)0x10000000) /*!< Filter bit 28 */ -#define CAN_F17D0R_FD29 ((uint32_t)0x20000000) /*!< Filter bit 29 */ -#define CAN_F17D0R_FD30 ((uint32_t)0x40000000) /*!< Filter bit 30 */ -#define CAN_F17D0R_FD31 ((uint32_t)0x80000000) /*!< Filter bit 31 */ - -/******************* Bit definition for CAN_F18D0R register ******************/ -#define CAN_F18D0R_FD0 ((uint32_t)0x00000001) /*!< Filter bit 0 */ -#define CAN_F18D0R_FD1 ((uint32_t)0x00000002) /*!< Filter bit 1 */ -#define CAN_F18D0R_FD2 ((uint32_t)0x00000004) /*!< Filter bit 2 */ -#define CAN_F18D0R_FD3 ((uint32_t)0x00000008) /*!< Filter bit 3 */ -#define CAN_F18D0R_FD4 ((uint32_t)0x00000010) /*!< Filter bit 4 */ -#define CAN_F18D0R_FD5 ((uint32_t)0x00000020) /*!< Filter bit 5 */ -#define CAN_F18D0R_FD6 ((uint32_t)0x00000040) /*!< Filter bit 6 */ -#define CAN_F18D0R_FD7 ((uint32_t)0x00000080) /*!< Filter bit 7 */ -#define CAN_F18D0R_FD8 ((uint32_t)0x00000100) /*!< Filter bit 8 */ -#define CAN_F18D0R_FD9 ((uint32_t)0x00000200) /*!< Filter bit 9 */ -#define CAN_F18D0R_FD10 ((uint32_t)0x00000400) /*!< Filter bit 10 */ -#define CAN_F18D0R_FD11 ((uint32_t)0x00000800) /*!< Filter bit 11 */ -#define CAN_F18D0R_FD12 ((uint32_t)0x00001000) /*!< Filter bit 12 */ -#define CAN_F18D0R_FD13 ((uint32_t)0x00002000) /*!< Filter bit 13 */ -#define CAN_F18D0R_FD14 ((uint32_t)0x00004000) /*!< Filter bit 14 */ -#define CAN_F18D0R_FD15 ((uint32_t)0x00008000) /*!< Filter bit 15 */ -#define CAN_F18D0R_FD16 ((uint32_t)0x00010000) /*!< Filter bit 16 */ -#define CAN_F18D0R_FD17 ((uint32_t)0x00020000) /*!< Filter bit 17 */ -#define CAN_F18D0R_FD18 ((uint32_t)0x00040000) /*!< Filter bit 18 */ -#define CAN_F18D0R_FD19 ((uint32_t)0x00080000) /*!< Filter bit 19 */ -#define CAN_F18D0R_FD20 ((uint32_t)0x00100000) /*!< Filter bit 20 */ -#define CAN_F18D0R_FD21 ((uint32_t)0x00200000) /*!< Filter bit 21 */ -#define CAN_F18D0R_FD22 ((uint32_t)0x00400000) /*!< Filter bit 22 */ -#define CAN_F18D0R_FD23 ((uint32_t)0x00800000) /*!< Filter bit 23 */ -#define CAN_F18D0R_FD24 ((uint32_t)0x01000000) /*!< Filter bit 24 */ -#define CAN_F18D0R_FD25 ((uint32_t)0x02000000) /*!< Filter bit 25 */ -#define CAN_F18D0R_FD26 ((uint32_t)0x04000000) /*!< Filter bit 26 */ -#define CAN_F18D0R_FD27 ((uint32_t)0x08000000) /*!< Filter bit 27 */ -#define CAN_F18D0R_FD28 ((uint32_t)0x10000000) /*!< Filter bit 28 */ -#define CAN_F18D0R_FD29 ((uint32_t)0x20000000) /*!< Filter bit 29 */ -#define CAN_F18D0R_FD30 ((uint32_t)0x40000000) /*!< Filter bit 30 */ -#define CAN_F18D0R_FD31 ((uint32_t)0x80000000) /*!< Filter bit 31 */ - -/******************* Bit definition for CAN_F19D0R register ******************/ -#define CAN_F19D0R_FD0 ((uint32_t)0x00000001) /*!< Filter bit 0 */ -#define CAN_F19D0R_FD1 ((uint32_t)0x00000002) /*!< Filter bit 1 */ -#define CAN_F19D0R_FD2 ((uint32_t)0x00000004) /*!< Filter bit 2 */ -#define CAN_F19D0R_FD3 ((uint32_t)0x00000008) /*!< Filter bit 3 */ -#define CAN_F19D0R_FD4 ((uint32_t)0x00000010) /*!< Filter bit 4 */ -#define CAN_F19D0R_FD5 ((uint32_t)0x00000020) /*!< Filter bit 5 */ -#define CAN_F19D0R_FD6 ((uint32_t)0x00000040) /*!< Filter bit 6 */ -#define CAN_F19D0R_FD7 ((uint32_t)0x00000080) /*!< Filter bit 7 */ -#define CAN_F19D0R_FD8 ((uint32_t)0x00000100) /*!< Filter bit 8 */ -#define CAN_F19D0R_FD9 ((uint32_t)0x00000200) /*!< Filter bit 9 */ -#define CAN_F19D0R_FD10 ((uint32_t)0x00000400) /*!< Filter bit 10 */ -#define CAN_F19D0R_FD11 ((uint32_t)0x00000800) /*!< Filter bit 11 */ -#define CAN_F19D0R_FD12 ((uint32_t)0x00001000) /*!< Filter bit 12 */ -#define CAN_F19D0R_FD13 ((uint32_t)0x00002000) /*!< Filter bit 13 */ -#define CAN_F19D0R_FD14 ((uint32_t)0x00004000) /*!< Filter bit 14 */ -#define CAN_F19D0R_FD15 ((uint32_t)0x00008000) /*!< Filter bit 15 */ -#define CAN_F19D0R_FD16 ((uint32_t)0x00010000) /*!< Filter bit 16 */ -#define CAN_F19D0R_FD17 ((uint32_t)0x00020000) /*!< Filter bit 17 */ -#define CAN_F19D0R_FD18 ((uint32_t)0x00040000) /*!< Filter bit 18 */ -#define CAN_F19D0R_FD19 ((uint32_t)0x00080000) /*!< Filter bit 19 */ -#define CAN_F19D0R_FD20 ((uint32_t)0x00100000) /*!< Filter bit 20 */ -#define CAN_F19D0R_FD21 ((uint32_t)0x00200000) /*!< Filter bit 21 */ -#define CAN_F19D0R_FD22 ((uint32_t)0x00400000) /*!< Filter bit 22 */ -#define CAN_F19D0R_FD23 ((uint32_t)0x00800000) /*!< Filter bit 23 */ -#define CAN_F19D0R_FD24 ((uint32_t)0x01000000) /*!< Filter bit 24 */ -#define CAN_F19D0R_FD25 ((uint32_t)0x02000000) /*!< Filter bit 25 */ -#define CAN_F19D0R_FD26 ((uint32_t)0x04000000) /*!< Filter bit 26 */ -#define CAN_F19D0R_FD27 ((uint32_t)0x08000000) /*!< Filter bit 27 */ -#define CAN_F19D0R_FD28 ((uint32_t)0x10000000) /*!< Filter bit 28 */ -#define CAN_F19D0R_FD29 ((uint32_t)0x20000000) /*!< Filter bit 29 */ -#define CAN_F19D0R_FD30 ((uint32_t)0x40000000) /*!< Filter bit 30 */ -#define CAN_F19D0R_FD31 ((uint32_t)0x80000000) /*!< Filter bit 31 */ - -/******************* Bit definition for CAN_F20D0R register ******************/ -#define CAN_F20D0R_FD0 ((uint32_t)0x00000001) /*!< Filter bit 0 */ -#define CAN_F20D0R_FD1 ((uint32_t)0x00000002) /*!< Filter bit 1 */ -#define CAN_F20D0R_FD2 ((uint32_t)0x00000004) /*!< Filter bit 2 */ -#define CAN_F20D0R_FD3 ((uint32_t)0x00000008) /*!< Filter bit 3 */ -#define CAN_F20D0R_FD4 ((uint32_t)0x00000010) /*!< Filter bit 4 */ -#define CAN_F20D0R_FD5 ((uint32_t)0x00000020) /*!< Filter bit 5 */ -#define CAN_F20D0R_FD6 ((uint32_t)0x00000040) /*!< Filter bit 6 */ -#define CAN_F20D0R_FD7 ((uint32_t)0x00000080) /*!< Filter bit 7 */ -#define CAN_F20D0R_FD8 ((uint32_t)0x00000100) /*!< Filter bit 8 */ -#define CAN_F20D0R_FD9 ((uint32_t)0x00000200) /*!< Filter bit 9 */ -#define CAN_F20D0R_FD10 ((uint32_t)0x00000400) /*!< Filter bit 10 */ -#define CAN_F20D0R_FD11 ((uint32_t)0x00000800) /*!< Filter bit 11 */ -#define CAN_F20D0R_FD12 ((uint32_t)0x00001000) /*!< Filter bit 12 */ -#define CAN_F20D0R_FD13 ((uint32_t)0x00002000) /*!< Filter bit 13 */ -#define CAN_F20D0R_FD14 ((uint32_t)0x00004000) /*!< Filter bit 14 */ -#define CAN_F20D0R_FD15 ((uint32_t)0x00008000) /*!< Filter bit 15 */ -#define CAN_F20D0R_FD16 ((uint32_t)0x00010000) /*!< Filter bit 16 */ -#define CAN_F20D0R_FD17 ((uint32_t)0x00020000) /*!< Filter bit 17 */ -#define CAN_F20D0R_FD18 ((uint32_t)0x00040000) /*!< Filter bit 18 */ -#define CAN_F20D0R_FD19 ((uint32_t)0x00080000) /*!< Filter bit 19 */ -#define CAN_F20D0R_FD20 ((uint32_t)0x00100000) /*!< Filter bit 20 */ -#define CAN_F20D0R_FD21 ((uint32_t)0x00200000) /*!< Filter bit 21 */ -#define CAN_F20D0R_FD22 ((uint32_t)0x00400000) /*!< Filter bit 22 */ -#define CAN_F20D0R_FD23 ((uint32_t)0x00800000) /*!< Filter bit 23 */ -#define CAN_F20D0R_FD24 ((uint32_t)0x01000000) /*!< Filter bit 24 */ -#define CAN_F20D0R_FD25 ((uint32_t)0x02000000) /*!< Filter bit 25 */ -#define CAN_F20D0R_FD26 ((uint32_t)0x04000000) /*!< Filter bit 26 */ -#define CAN_F20D0R_FD27 ((uint32_t)0x08000000) /*!< Filter bit 27 */ -#define CAN_F20D0R_FD28 ((uint32_t)0x10000000) /*!< Filter bit 28 */ -#define CAN_F20D0R_FD29 ((uint32_t)0x20000000) /*!< Filter bit 29 */ -#define CAN_F20D0R_FD30 ((uint32_t)0x40000000) /*!< Filter bit 30 */ -#define CAN_F20D0R_FD31 ((uint32_t)0x80000000) /*!< Filter bit 31 */ - -/******************* Bit definition for CAN_F21D0R register ******************/ -#define CAN_F21D0R_FD0 ((uint32_t)0x00000001) /*!< Filter bit 0 */ -#define CAN_F21D0R_FD1 ((uint32_t)0x00000002) /*!< Filter bit 1 */ -#define CAN_F21D0R_FD2 ((uint32_t)0x00000004) /*!< Filter bit 2 */ -#define CAN_F21D0R_FD3 ((uint32_t)0x00000008) /*!< Filter bit 3 */ -#define CAN_F21D0R_FD4 ((uint32_t)0x00000010) /*!< Filter bit 4 */ -#define CAN_F21D0R_FD5 ((uint32_t)0x00000020) /*!< Filter bit 5 */ -#define CAN_F21D0R_FD6 ((uint32_t)0x00000040) /*!< Filter bit 6 */ -#define CAN_F21D0R_FD7 ((uint32_t)0x00000080) /*!< Filter bit 7 */ -#define CAN_F21D0R_FD8 ((uint32_t)0x00000100) /*!< Filter bit 8 */ -#define CAN_F21D0R_FD9 ((uint32_t)0x00000200) /*!< Filter bit 9 */ -#define CAN_F21D0R_FD10 ((uint32_t)0x00000400) /*!< Filter bit 10 */ -#define CAN_F21D0R_FD11 ((uint32_t)0x00000800) /*!< Filter bit 11 */ -#define CAN_F21D0R_FD12 ((uint32_t)0x00001000) /*!< Filter bit 12 */ -#define CAN_F21D0R_FD13 ((uint32_t)0x00002000) /*!< Filter bit 13 */ -#define CAN_F21D0R_FD14 ((uint32_t)0x00004000) /*!< Filter bit 14 */ -#define CAN_F21D0R_FD15 ((uint32_t)0x00008000) /*!< Filter bit 15 */ -#define CAN_F21D0R_FD16 ((uint32_t)0x00010000) /*!< Filter bit 16 */ -#define CAN_F21D0R_FD17 ((uint32_t)0x00020000) /*!< Filter bit 17 */ -#define CAN_F21D0R_FD18 ((uint32_t)0x00040000) /*!< Filter bit 18 */ -#define CAN_F21D0R_FD19 ((uint32_t)0x00080000) /*!< Filter bit 19 */ -#define CAN_F21D0R_FD20 ((uint32_t)0x00100000) /*!< Filter bit 20 */ -#define CAN_F21D0R_FD21 ((uint32_t)0x00200000) /*!< Filter bit 21 */ -#define CAN_F21D0R_FD22 ((uint32_t)0x00400000) /*!< Filter bit 22 */ -#define CAN_F21D0R_FD23 ((uint32_t)0x00800000) /*!< Filter bit 23 */ -#define CAN_F21D0R_FD24 ((uint32_t)0x01000000) /*!< Filter bit 24 */ -#define CAN_F21D0R_FD25 ((uint32_t)0x02000000) /*!< Filter bit 25 */ -#define CAN_F21D0R_FD26 ((uint32_t)0x04000000) /*!< Filter bit 26 */ -#define CAN_F21D0R_FD27 ((uint32_t)0x08000000) /*!< Filter bit 27 */ -#define CAN_F21D0R_FD28 ((uint32_t)0x10000000) /*!< Filter bit 28 */ -#define CAN_F21D0R_FD29 ((uint32_t)0x20000000) /*!< Filter bit 29 */ -#define CAN_F21D0R_FD30 ((uint32_t)0x40000000) /*!< Filter bit 30 */ -#define CAN_F21D0R_FD31 ((uint32_t)0x80000000) /*!< Filter bit 31 */ - -/******************* Bit definition for CAN_F22D0R register ******************/ -#define CAN_F22D0R_FD0 ((uint32_t)0x00000001) /*!< Filter bit 0 */ -#define CAN_F22D0R_FD1 ((uint32_t)0x00000002) /*!< Filter bit 1 */ -#define CAN_F22D0R_FD2 ((uint32_t)0x00000004) /*!< Filter bit 2 */ -#define CAN_F22D0R_FD3 ((uint32_t)0x00000008) /*!< Filter bit 3 */ -#define CAN_F22D0R_FD4 ((uint32_t)0x00000010) /*!< Filter bit 4 */ -#define CAN_F22D0R_FD5 ((uint32_t)0x00000020) /*!< Filter bit 5 */ -#define CAN_F22D0R_FD6 ((uint32_t)0x00000040) /*!< Filter bit 6 */ -#define CAN_F22D0R_FD7 ((uint32_t)0x00000080) /*!< Filter bit 7 */ -#define CAN_F22D0R_FD8 ((uint32_t)0x00000100) /*!< Filter bit 8 */ -#define CAN_F22D0R_FD9 ((uint32_t)0x00000200) /*!< Filter bit 9 */ -#define CAN_F22D0R_FD10 ((uint32_t)0x00000400) /*!< Filter bit 10 */ -#define CAN_F22D0R_FD11 ((uint32_t)0x00000800) /*!< Filter bit 11 */ -#define CAN_F22D0R_FD12 ((uint32_t)0x00001000) /*!< Filter bit 12 */ -#define CAN_F22D0R_FD13 ((uint32_t)0x00002000) /*!< Filter bit 13 */ -#define CAN_F22D0R_FD14 ((uint32_t)0x00004000) /*!< Filter bit 14 */ -#define CAN_F22D0R_FD15 ((uint32_t)0x00008000) /*!< Filter bit 15 */ -#define CAN_F22D0R_FD16 ((uint32_t)0x00010000) /*!< Filter bit 16 */ -#define CAN_F22D0R_FD17 ((uint32_t)0x00020000) /*!< Filter bit 17 */ -#define CAN_F22D0R_FD18 ((uint32_t)0x00040000) /*!< Filter bit 18 */ -#define CAN_F22D0R_FD19 ((uint32_t)0x00080000) /*!< Filter bit 19 */ -#define CAN_F22D0R_FD20 ((uint32_t)0x00100000) /*!< Filter bit 20 */ -#define CAN_F22D0R_FD21 ((uint32_t)0x00200000) /*!< Filter bit 21 */ -#define CAN_F22D0R_FD22 ((uint32_t)0x00400000) /*!< Filter bit 22 */ -#define CAN_F22D0R_FD23 ((uint32_t)0x00800000) /*!< Filter bit 23 */ -#define CAN_F22D0R_FD24 ((uint32_t)0x01000000) /*!< Filter bit 24 */ -#define CAN_F22D0R_FD25 ((uint32_t)0x02000000) /*!< Filter bit 25 */ -#define CAN_F22D0R_FD26 ((uint32_t)0x04000000) /*!< Filter bit 26 */ -#define CAN_F22D0R_FD27 ((uint32_t)0x08000000) /*!< Filter bit 27 */ -#define CAN_F22D0R_FD28 ((uint32_t)0x10000000) /*!< Filter bit 28 */ -#define CAN_F22D0R_FD29 ((uint32_t)0x20000000) /*!< Filter bit 29 */ -#define CAN_F22D0R_FD30 ((uint32_t)0x40000000) /*!< Filter bit 30 */ -#define CAN_F22D0R_FD31 ((uint32_t)0x80000000) /*!< Filter bit 31 */ - -/******************* Bit definition for CAN_F23D0R register ******************/ -#define CAN_F23D0R_FD0 ((uint32_t)0x00000001) /*!< Filter bit 0 */ -#define CAN_F23D0R_FD1 ((uint32_t)0x00000002) /*!< Filter bit 1 */ -#define CAN_F23D0R_FD2 ((uint32_t)0x00000004) /*!< Filter bit 2 */ -#define CAN_F23D0R_FD3 ((uint32_t)0x00000008) /*!< Filter bit 3 */ -#define CAN_F23D0R_FD4 ((uint32_t)0x00000010) /*!< Filter bit 4 */ -#define CAN_F23D0R_FD5 ((uint32_t)0x00000020) /*!< Filter bit 5 */ -#define CAN_F23D0R_FD6 ((uint32_t)0x00000040) /*!< Filter bit 6 */ -#define CAN_F23D0R_FD7 ((uint32_t)0x00000080) /*!< Filter bit 7 */ -#define CAN_F23D0R_FD8 ((uint32_t)0x00000100) /*!< Filter bit 8 */ -#define CAN_F23D0R_FD9 ((uint32_t)0x00000200) /*!< Filter bit 9 */ -#define CAN_F23D0R_FD10 ((uint32_t)0x00000400) /*!< Filter bit 10 */ -#define CAN_F23D0R_FD11 ((uint32_t)0x00000800) /*!< Filter bit 11 */ -#define CAN_F23D0R_FD12 ((uint32_t)0x00001000) /*!< Filter bit 12 */ -#define CAN_F23D0R_FD13 ((uint32_t)0x00002000) /*!< Filter bit 13 */ -#define CAN_F23D0R_FD14 ((uint32_t)0x00004000) /*!< Filter bit 14 */ -#define CAN_F23D0R_FD15 ((uint32_t)0x00008000) /*!< Filter bit 15 */ -#define CAN_F23D0R_FD16 ((uint32_t)0x00010000) /*!< Filter bit 16 */ -#define CAN_F23D0R_FD17 ((uint32_t)0x00020000) /*!< Filter bit 17 */ -#define CAN_F23D0R_FD18 ((uint32_t)0x00040000) /*!< Filter bit 18 */ -#define CAN_F23D0R_FD19 ((uint32_t)0x00080000) /*!< Filter bit 19 */ -#define CAN_F23D0R_FD20 ((uint32_t)0x00100000) /*!< Filter bit 20 */ -#define CAN_F23D0R_FD21 ((uint32_t)0x00200000) /*!< Filter bit 21 */ -#define CAN_F23D0R_FD22 ((uint32_t)0x00400000) /*!< Filter bit 22 */ -#define CAN_F23D0R_FD23 ((uint32_t)0x00800000) /*!< Filter bit 23 */ -#define CAN_F23D0R_FD24 ((uint32_t)0x01000000) /*!< Filter bit 24 */ -#define CAN_F23D0R_FD25 ((uint32_t)0x02000000) /*!< Filter bit 25 */ -#define CAN_F23D0R_FD26 ((uint32_t)0x04000000) /*!< Filter bit 26 */ -#define CAN_F23D0R_FD27 ((uint32_t)0x08000000) /*!< Filter bit 27 */ -#define CAN_F23D0R_FD28 ((uint32_t)0x10000000) /*!< Filter bit 28 */ -#define CAN_F23D0R_FD29 ((uint32_t)0x20000000) /*!< Filter bit 29 */ -#define CAN_F23D0R_FD30 ((uint32_t)0x40000000) /*!< Filter bit 30 */ -#define CAN_F23D0R_FD31 ((uint32_t)0x80000000) /*!< Filter bit 31 */ - -/******************* Bit definition for CAN_F24D0R register ******************/ -#define CAN_F24D0R_FD0 ((uint32_t)0x00000001) /*!< Filter bit 0 */ -#define CAN_F24D0R_FD1 ((uint32_t)0x00000002) /*!< Filter bit 1 */ -#define CAN_F24D0R_FD2 ((uint32_t)0x00000004) /*!< Filter bit 2 */ -#define CAN_F24D0R_FD3 ((uint32_t)0x00000008) /*!< Filter bit 3 */ -#define CAN_F24D0R_FD4 ((uint32_t)0x00000010) /*!< Filter bit 4 */ -#define CAN_F24D0R_FD5 ((uint32_t)0x00000020) /*!< Filter bit 5 */ -#define CAN_F24D0R_FD6 ((uint32_t)0x00000040) /*!< Filter bit 6 */ -#define CAN_F24D0R_FD7 ((uint32_t)0x00000080) /*!< Filter bit 7 */ -#define CAN_F24D0R_FD8 ((uint32_t)0x00000100) /*!< Filter bit 8 */ -#define CAN_F24D0R_FD9 ((uint32_t)0x00000200) /*!< Filter bit 9 */ -#define CAN_F24D0R_FD10 ((uint32_t)0x00000400) /*!< Filter bit 10 */ -#define CAN_F24D0R_FD11 ((uint32_t)0x00000800) /*!< Filter bit 11 */ -#define CAN_F24D0R_FD12 ((uint32_t)0x00001000) /*!< Filter bit 12 */ -#define CAN_F24D0R_FD13 ((uint32_t)0x00002000) /*!< Filter bit 13 */ -#define CAN_F24D0R_FD14 ((uint32_t)0x00004000) /*!< Filter bit 14 */ -#define CAN_F24D0R_FD15 ((uint32_t)0x00008000) /*!< Filter bit 15 */ -#define CAN_F24D0R_FD16 ((uint32_t)0x00010000) /*!< Filter bit 16 */ -#define CAN_F24D0R_FD17 ((uint32_t)0x00020000) /*!< Filter bit 17 */ -#define CAN_F24D0R_FD18 ((uint32_t)0x00040000) /*!< Filter bit 18 */ -#define CAN_F24D0R_FD19 ((uint32_t)0x00080000) /*!< Filter bit 19 */ -#define CAN_F24D0R_FD20 ((uint32_t)0x00100000) /*!< Filter bit 20 */ -#define CAN_F24D0R_FD21 ((uint32_t)0x00200000) /*!< Filter bit 21 */ -#define CAN_F24D0R_FD22 ((uint32_t)0x00400000) /*!< Filter bit 22 */ -#define CAN_F24D0R_FD23 ((uint32_t)0x00800000) /*!< Filter bit 23 */ -#define CAN_F24D0R_FD24 ((uint32_t)0x01000000) /*!< Filter bit 24 */ -#define CAN_F24D0R_FD25 ((uint32_t)0x02000000) /*!< Filter bit 25 */ -#define CAN_F24D0R_FD26 ((uint32_t)0x04000000) /*!< Filter bit 26 */ -#define CAN_F24D0R_FD27 ((uint32_t)0x08000000) /*!< Filter bit 27 */ -#define CAN_F24D0R_FD28 ((uint32_t)0x10000000) /*!< Filter bit 28 */ -#define CAN_F24D0R_FD29 ((uint32_t)0x20000000) /*!< Filter bit 29 */ -#define CAN_F24D0R_FD30 ((uint32_t)0x40000000) /*!< Filter bit 30 */ -#define CAN_F24D0R_FD31 ((uint32_t)0x80000000) /*!< Filter bit 31 */ - -/******************* Bit definition for CAN_F25D0R register ******************/ -#define CAN_F25D0R_FD0 ((uint32_t)0x00000001) /*!< Filter bit 0 */ -#define CAN_F25D0R_FD1 ((uint32_t)0x00000002) /*!< Filter bit 1 */ -#define CAN_F25D0R_FD2 ((uint32_t)0x00000004) /*!< Filter bit 2 */ -#define CAN_F25D0R_FD3 ((uint32_t)0x00000008) /*!< Filter bit 3 */ -#define CAN_F25D0R_FD4 ((uint32_t)0x00000010) /*!< Filter bit 4 */ -#define CAN_F25D0R_FD5 ((uint32_t)0x00000020) /*!< Filter bit 5 */ -#define CAN_F25D0R_FD6 ((uint32_t)0x00000040) /*!< Filter bit 6 */ -#define CAN_F25D0R_FD7 ((uint32_t)0x00000080) /*!< Filter bit 7 */ -#define CAN_F25D0R_FD8 ((uint32_t)0x00000100) /*!< Filter bit 8 */ -#define CAN_F25D0R_FD9 ((uint32_t)0x00000200) /*!< Filter bit 9 */ -#define CAN_F25D0R_FD10 ((uint32_t)0x00000400) /*!< Filter bit 10 */ -#define CAN_F25D0R_FD11 ((uint32_t)0x00000800) /*!< Filter bit 11 */ -#define CAN_F25D0R_FD12 ((uint32_t)0x00001000) /*!< Filter bit 12 */ -#define CAN_F25D0R_FD13 ((uint32_t)0x00002000) /*!< Filter bit 13 */ -#define CAN_F25D0R_FD14 ((uint32_t)0x00004000) /*!< Filter bit 14 */ -#define CAN_F25D0R_FD15 ((uint32_t)0x00008000) /*!< Filter bit 15 */ -#define CAN_F25D0R_FD16 ((uint32_t)0x00010000) /*!< Filter bit 16 */ -#define CAN_F25D0R_FD17 ((uint32_t)0x00020000) /*!< Filter bit 17 */ -#define CAN_F25D0R_FD18 ((uint32_t)0x00040000) /*!< Filter bit 18 */ -#define CAN_F25D0R_FD19 ((uint32_t)0x00080000) /*!< Filter bit 19 */ -#define CAN_F25D0R_FD20 ((uint32_t)0x00100000) /*!< Filter bit 20 */ -#define CAN_F25D0R_FD21 ((uint32_t)0x00200000) /*!< Filter bit 21 */ -#define CAN_F25D0R_FD22 ((uint32_t)0x00400000) /*!< Filter bit 22 */ -#define CAN_F25D0R_FD23 ((uint32_t)0x00800000) /*!< Filter bit 23 */ -#define CAN_F25D0R_FD24 ((uint32_t)0x01000000) /*!< Filter bit 24 */ -#define CAN_F25D0R_FD25 ((uint32_t)0x02000000) /*!< Filter bit 25 */ -#define CAN_F25D0R_FD26 ((uint32_t)0x04000000) /*!< Filter bit 26 */ -#define CAN_F25D0R_FD27 ((uint32_t)0x08000000) /*!< Filter bit 27 */ -#define CAN_F25D0R_FD28 ((uint32_t)0x10000000) /*!< Filter bit 28 */ -#define CAN_F25D0R_FD29 ((uint32_t)0x20000000) /*!< Filter bit 29 */ -#define CAN_F25D0R_FD30 ((uint32_t)0x40000000) /*!< Filter bit 30 */ -#define CAN_F25D0R_FD31 ((uint32_t)0x80000000) /*!< Filter bit 31 */ - -/******************* Bit definition for CAN_F26D0R register ******************/ -#define CAN_F26D0R_FD0 ((uint32_t)0x00000001) /*!< Filter bit 0 */ -#define CAN_F26D0R_FD1 ((uint32_t)0x00000002) /*!< Filter bit 1 */ -#define CAN_F26D0R_FD2 ((uint32_t)0x00000004) /*!< Filter bit 2 */ -#define CAN_F26D0R_FD3 ((uint32_t)0x00000008) /*!< Filter bit 3 */ -#define CAN_F26D0R_FD4 ((uint32_t)0x00000010) /*!< Filter bit 4 */ -#define CAN_F26D0R_FD5 ((uint32_t)0x00000020) /*!< Filter bit 5 */ -#define CAN_F26D0R_FD6 ((uint32_t)0x00000040) /*!< Filter bit 6 */ -#define CAN_F26D0R_FD7 ((uint32_t)0x00000080) /*!< Filter bit 7 */ -#define CAN_F26D0R_FD8 ((uint32_t)0x00000100) /*!< Filter bit 8 */ -#define CAN_F26D0R_FD9 ((uint32_t)0x00000200) /*!< Filter bit 9 */ -#define CAN_F26D0R_FD10 ((uint32_t)0x00000400) /*!< Filter bit 10 */ -#define CAN_F26D0R_FD11 ((uint32_t)0x00000800) /*!< Filter bit 11 */ -#define CAN_F26D0R_FD12 ((uint32_t)0x00001000) /*!< Filter bit 12 */ -#define CAN_F26D0R_FD13 ((uint32_t)0x00002000) /*!< Filter bit 13 */ -#define CAN_F26D0R_FD14 ((uint32_t)0x00004000) /*!< Filter bit 14 */ -#define CAN_F26D0R_FD15 ((uint32_t)0x00008000) /*!< Filter bit 15 */ -#define CAN_F26D0R_FD16 ((uint32_t)0x00010000) /*!< Filter bit 16 */ -#define CAN_F26D0R_FD17 ((uint32_t)0x00020000) /*!< Filter bit 17 */ -#define CAN_F26D0R_FD18 ((uint32_t)0x00040000) /*!< Filter bit 18 */ -#define CAN_F26D0R_FD19 ((uint32_t)0x00080000) /*!< Filter bit 19 */ -#define CAN_F26D0R_FD20 ((uint32_t)0x00100000) /*!< Filter bit 20 */ -#define CAN_F26D0R_FD21 ((uint32_t)0x00200000) /*!< Filter bit 21 */ -#define CAN_F26D0R_FD22 ((uint32_t)0x00400000) /*!< Filter bit 22 */ -#define CAN_F26D0R_FD23 ((uint32_t)0x00800000) /*!< Filter bit 23 */ -#define CAN_F26D0R_FD24 ((uint32_t)0x01000000) /*!< Filter bit 24 */ -#define CAN_F26D0R_FD25 ((uint32_t)0x02000000) /*!< Filter bit 25 */ -#define CAN_F26D0R_FD26 ((uint32_t)0x04000000) /*!< Filter bit 26 */ -#define CAN_F26D0R_FD27 ((uint32_t)0x08000000) /*!< Filter bit 27 */ -#define CAN_F26D0R_FD28 ((uint32_t)0x10000000) /*!< Filter bit 28 */ -#define CAN_F26D0R_FD29 ((uint32_t)0x20000000) /*!< Filter bit 29 */ -#define CAN_F26D0R_FD30 ((uint32_t)0x40000000) /*!< Filter bit 30 */ -#define CAN_F26D0R_FD31 ((uint32_t)0x80000000) /*!< Filter bit 31 */ - -/******************* Bit definition for CAN_F27D0R register ******************/ -#define CAN_F27D0R_FD0 ((uint32_t)0x00000001) /*!< Filter bit 0 */ -#define CAN_F27D0R_FD1 ((uint32_t)0x00000002) /*!< Filter bit 1 */ -#define CAN_F27D0R_FD2 ((uint32_t)0x00000004) /*!< Filter bit 2 */ -#define CAN_F27D0R_FD3 ((uint32_t)0x00000008) /*!< Filter bit 3 */ -#define CAN_F27D0R_FD4 ((uint32_t)0x00000010) /*!< Filter bit 4 */ -#define CAN_F27D0R_FD5 ((uint32_t)0x00000020) /*!< Filter bit 5 */ -#define CAN_F27D0R_FD6 ((uint32_t)0x00000040) /*!< Filter bit 6 */ -#define CAN_F27D0R_FD7 ((uint32_t)0x00000080) /*!< Filter bit 7 */ -#define CAN_F27D0R_FD8 ((uint32_t)0x00000100) /*!< Filter bit 8 */ -#define CAN_F27D0R_FD9 ((uint32_t)0x00000200) /*!< Filter bit 9 */ -#define CAN_F27D0R_FD10 ((uint32_t)0x00000400) /*!< Filter bit 10 */ -#define CAN_F27D0R_FD11 ((uint32_t)0x00000800) /*!< Filter bit 11 */ -#define CAN_F27D0R_FD12 ((uint32_t)0x00001000) /*!< Filter bit 12 */ -#define CAN_F27D0R_FD13 ((uint32_t)0x00002000) /*!< Filter bit 13 */ -#define CAN_F27D0R_FD14 ((uint32_t)0x00004000) /*!< Filter bit 14 */ -#define CAN_F27D0R_FD15 ((uint32_t)0x00008000) /*!< Filter bit 15 */ -#define CAN_F27D0R_FD16 ((uint32_t)0x00010000) /*!< Filter bit 16 */ -#define CAN_F27D0R_FD17 ((uint32_t)0x00020000) /*!< Filter bit 17 */ -#define CAN_F27D0R_FD18 ((uint32_t)0x00040000) /*!< Filter bit 18 */ -#define CAN_F27D0R_FD19 ((uint32_t)0x00080000) /*!< Filter bit 19 */ -#define CAN_F27D0R_FD20 ((uint32_t)0x00100000) /*!< Filter bit 20 */ -#define CAN_F27D0R_FD21 ((uint32_t)0x00200000) /*!< Filter bit 21 */ -#define CAN_F27D0R_FD22 ((uint32_t)0x00400000) /*!< Filter bit 22 */ -#define CAN_F27D0R_FD23 ((uint32_t)0x00800000) /*!< Filter bit 23 */ -#define CAN_F27D0R_FD24 ((uint32_t)0x01000000) /*!< Filter bit 24 */ -#define CAN_F27D0R_FD25 ((uint32_t)0x02000000) /*!< Filter bit 25 */ -#define CAN_F27D0R_FD26 ((uint32_t)0x04000000) /*!< Filter bit 26 */ -#define CAN_F27D0R_FD27 ((uint32_t)0x08000000) /*!< Filter bit 27 */ -#define CAN_F27D0R_FD28 ((uint32_t)0x10000000) /*!< Filter bit 28 */ -#define CAN_F27D0R_FD29 ((uint32_t)0x20000000) /*!< Filter bit 29 */ -#define CAN_F27D0R_FD30 ((uint32_t)0x40000000) /*!< Filter bit 30 */ -#define CAN_F27D0R_FD31 ((uint32_t)0x80000000) /*!< Filter bit 31 */ - -/******************* Bit definition for CAN_F0D1R register *******************/ -#define CAN_F0D1R_FD0 ((uint32_t)0x00000001) /*!< Filter bit 0 */ -#define CAN_F0D1R_FD1 ((uint32_t)0x00000002) /*!< Filter bit 1 */ -#define CAN_F0D1R_FD2 ((uint32_t)0x00000004) /*!< Filter bit 2 */ -#define CAN_F0D1R_FD3 ((uint32_t)0x00000008) /*!< Filter bit 3 */ -#define CAN_F0D1R_FD4 ((uint32_t)0x00000010) /*!< Filter bit 4 */ -#define CAN_F0D1R_FD5 ((uint32_t)0x00000020) /*!< Filter bit 5 */ -#define CAN_F0D1R_FD6 ((uint32_t)0x00000040) /*!< Filter bit 6 */ -#define CAN_F0D1R_FD7 ((uint32_t)0x00000080) /*!< Filter bit 7 */ -#define CAN_F0D1R_FD8 ((uint32_t)0x00000100) /*!< Filter bit 8 */ -#define CAN_F0D1R_FD9 ((uint32_t)0x00000200) /*!< Filter bit 9 */ -#define CAN_F0D1R_FD10 ((uint32_t)0x00000400) /*!< Filter bit 10 */ -#define CAN_F0D1R_FD11 ((uint32_t)0x00000800) /*!< Filter bit 11 */ -#define CAN_F0D1R_FD12 ((uint32_t)0x00001000) /*!< Filter bit 12 */ -#define CAN_F0D1R_FD13 ((uint32_t)0x00002000) /*!< Filter bit 13 */ -#define CAN_F0D1R_FD14 ((uint32_t)0x00004000) /*!< Filter bit 14 */ -#define CAN_F0D1R_FD15 ((uint32_t)0x00008000) /*!< Filter bit 15 */ -#define CAN_F0D1R_FD16 ((uint32_t)0x00010000) /*!< Filter bit 16 */ -#define CAN_F0D1R_FD17 ((uint32_t)0x00020000) /*!< Filter bit 17 */ -#define CAN_F0D1R_FD18 ((uint32_t)0x00040000) /*!< Filter bit 18 */ -#define CAN_F0D1R_FD19 ((uint32_t)0x00080000) /*!< Filter bit 19 */ -#define CAN_F0D1R_FD20 ((uint32_t)0x00100000) /*!< Filter bit 20 */ -#define CAN_F0D1R_FD21 ((uint32_t)0x00200000) /*!< Filter bit 21 */ -#define CAN_F0D1R_FD22 ((uint32_t)0x00400000) /*!< Filter bit 22 */ -#define CAN_F0D1R_FD23 ((uint32_t)0x00800000) /*!< Filter bit 23 */ -#define CAN_F0D1R_FD24 ((uint32_t)0x01000000) /*!< Filter bit 24 */ -#define CAN_F0D1R_FD25 ((uint32_t)0x02000000) /*!< Filter bit 25 */ -#define CAN_F0D1R_FD26 ((uint32_t)0x04000000) /*!< Filter bit 26 */ -#define CAN_F0D1R_FD27 ((uint32_t)0x08000000) /*!< Filter bit 27 */ -#define CAN_F0D1R_FD28 ((uint32_t)0x10000000) /*!< Filter bit 28 */ -#define CAN_F0D1R_FD29 ((uint32_t)0x20000000) /*!< Filter bit 29 */ -#define CAN_F0D1R_FD30 ((uint32_t)0x40000000) /*!< Filter bit 30 */ -#define CAN_F0D1R_FD31 ((uint32_t)0x80000000) /*!< Filter bit 31 */ - -/******************* Bit definition for CAN_F1D1R register *******************/ -#define CAN_F1D1R_FD0 ((uint32_t)0x00000001) /*!< Filter bit 0 */ -#define CAN_F1D1R_FD1 ((uint32_t)0x00000002) /*!< Filter bit 1 */ -#define CAN_F1D1R_FD2 ((uint32_t)0x00000004) /*!< Filter bit 2 */ -#define CAN_F1D1R_FD3 ((uint32_t)0x00000008) /*!< Filter bit 3 */ -#define CAN_F1D1R_FD4 ((uint32_t)0x00000010) /*!< Filter bit 4 */ -#define CAN_F1D1R_FD5 ((uint32_t)0x00000020) /*!< Filter bit 5 */ -#define CAN_F1D1R_FD6 ((uint32_t)0x00000040) /*!< Filter bit 6 */ -#define CAN_F1D1R_FD7 ((uint32_t)0x00000080) /*!< Filter bit 7 */ -#define CAN_F1D1R_FD8 ((uint32_t)0x00000100) /*!< Filter bit 8 */ -#define CAN_F1D1R_FD9 ((uint32_t)0x00000200) /*!< Filter bit 9 */ -#define CAN_F1D1R_FD10 ((uint32_t)0x00000400) /*!< Filter bit 10 */ -#define CAN_F1D1R_FD11 ((uint32_t)0x00000800) /*!< Filter bit 11 */ -#define CAN_F1D1R_FD12 ((uint32_t)0x00001000) /*!< Filter bit 12 */ -#define CAN_F1D1R_FD13 ((uint32_t)0x00002000) /*!< Filter bit 13 */ -#define CAN_F1D1R_FD14 ((uint32_t)0x00004000) /*!< Filter bit 14 */ -#define CAN_F1D1R_FD15 ((uint32_t)0x00008000) /*!< Filter bit 15 */ -#define CAN_F1D1R_FD16 ((uint32_t)0x00010000) /*!< Filter bit 16 */ -#define CAN_F1D1R_FD17 ((uint32_t)0x00020000) /*!< Filter bit 17 */ -#define CAN_F1D1R_FD18 ((uint32_t)0x00040000) /*!< Filter bit 18 */ -#define CAN_F1D1R_FD19 ((uint32_t)0x00080000) /*!< Filter bit 19 */ -#define CAN_F1D1R_FD20 ((uint32_t)0x00100000) /*!< Filter bit 20 */ -#define CAN_F1D1R_FD21 ((uint32_t)0x00200000) /*!< Filter bit 21 */ -#define CAN_F1D1R_FD22 ((uint32_t)0x00400000) /*!< Filter bit 22 */ -#define CAN_F1D1R_FD23 ((uint32_t)0x00800000) /*!< Filter bit 23 */ -#define CAN_F1D1R_FD24 ((uint32_t)0x01000000) /*!< Filter bit 24 */ -#define CAN_F1D1R_FD25 ((uint32_t)0x02000000) /*!< Filter bit 25 */ -#define CAN_F1D1R_FD26 ((uint32_t)0x04000000) /*!< Filter bit 26 */ -#define CAN_F1D1R_FD27 ((uint32_t)0x08000000) /*!< Filter bit 27 */ -#define CAN_F1D1R_FD28 ((uint32_t)0x10000000) /*!< Filter bit 28 */ -#define CAN_F1D1R_FD29 ((uint32_t)0x20000000) /*!< Filter bit 29 */ -#define CAN_F1D1R_FD30 ((uint32_t)0x40000000) /*!< Filter bit 30 */ -#define CAN_F1D1R_FD31 ((uint32_t)0x80000000) /*!< Filter bit 31 */ - -/******************* Bit definition for CAN_F2D1R register *******************/ -#define CAN_F2D1R_FD0 ((uint32_t)0x00000001) /*!< Filter bit 0 */ -#define CAN_F2D1R_FD1 ((uint32_t)0x00000002) /*!< Filter bit 1 */ -#define CAN_F2D1R_FD2 ((uint32_t)0x00000004) /*!< Filter bit 2 */ -#define CAN_F2D1R_FD3 ((uint32_t)0x00000008) /*!< Filter bit 3 */ -#define CAN_F2D1R_FD4 ((uint32_t)0x00000010) /*!< Filter bit 4 */ -#define CAN_F2D1R_FD5 ((uint32_t)0x00000020) /*!< Filter bit 5 */ -#define CAN_F2D1R_FD6 ((uint32_t)0x00000040) /*!< Filter bit 6 */ -#define CAN_F2D1R_FD7 ((uint32_t)0x00000080) /*!< Filter bit 7 */ -#define CAN_F2D1R_FD8 ((uint32_t)0x00000100) /*!< Filter bit 8 */ -#define CAN_F2D1R_FD9 ((uint32_t)0x00000200) /*!< Filter bit 9 */ -#define CAN_F2D1R_FD10 ((uint32_t)0x00000400) /*!< Filter bit 10 */ -#define CAN_F2D1R_FD11 ((uint32_t)0x00000800) /*!< Filter bit 11 */ -#define CAN_F2D1R_FD12 ((uint32_t)0x00001000) /*!< Filter bit 12 */ -#define CAN_F2D1R_FD13 ((uint32_t)0x00002000) /*!< Filter bit 13 */ -#define CAN_F2D1R_FD14 ((uint32_t)0x00004000) /*!< Filter bit 14 */ -#define CAN_F2D1R_FD15 ((uint32_t)0x00008000) /*!< Filter bit 15 */ -#define CAN_F2D1R_FD16 ((uint32_t)0x00010000) /*!< Filter bit 16 */ -#define CAN_F2D1R_FD17 ((uint32_t)0x00020000) /*!< Filter bit 17 */ -#define CAN_F2D1R_FD18 ((uint32_t)0x00040000) /*!< Filter bit 18 */ -#define CAN_F2D1R_FD19 ((uint32_t)0x00080000) /*!< Filter bit 19 */ -#define CAN_F2D1R_FD20 ((uint32_t)0x00100000) /*!< Filter bit 20 */ -#define CAN_F2D1R_FD21 ((uint32_t)0x00200000) /*!< Filter bit 21 */ -#define CAN_F2D1R_FD22 ((uint32_t)0x00400000) /*!< Filter bit 22 */ -#define CAN_F2D1R_FD23 ((uint32_t)0x00800000) /*!< Filter bit 23 */ -#define CAN_F2D1R_FD24 ((uint32_t)0x01000000) /*!< Filter bit 24 */ -#define CAN_F2D1R_FD25 ((uint32_t)0x02000000) /*!< Filter bit 25 */ -#define CAN_F2D1R_FD26 ((uint32_t)0x04000000) /*!< Filter bit 26 */ -#define CAN_F2D1R_FD27 ((uint32_t)0x08000000) /*!< Filter bit 27 */ -#define CAN_F2D1R_FD28 ((uint32_t)0x10000000) /*!< Filter bit 28 */ -#define CAN_F2D1R_FD29 ((uint32_t)0x20000000) /*!< Filter bit 29 */ -#define CAN_F2D1R_FD30 ((uint32_t)0x40000000) /*!< Filter bit 30 */ -#define CAN_F2D1R_FD31 ((uint32_t)0x80000000) /*!< Filter bit 31 */ - -/******************* Bit definition for CAN_F3D1R register *******************/ -#define CAN_F3D1R_FD0 ((uint32_t)0x00000001) /*!< Filter bit 0 */ -#define CAN_F3D1R_FD1 ((uint32_t)0x00000002) /*!< Filter bit 1 */ -#define CAN_F3D1R_FD2 ((uint32_t)0x00000004) /*!< Filter bit 2 */ -#define CAN_F3D1R_FD3 ((uint32_t)0x00000008) /*!< Filter bit 3 */ -#define CAN_F3D1R_FD4 ((uint32_t)0x00000010) /*!< Filter bit 4 */ -#define CAN_F3D1R_FD5 ((uint32_t)0x00000020) /*!< Filter bit 5 */ -#define CAN_F3D1R_FD6 ((uint32_t)0x00000040) /*!< Filter bit 6 */ -#define CAN_F3D1R_FD7 ((uint32_t)0x00000080) /*!< Filter bit 7 */ -#define CAN_F3D1R_FD8 ((uint32_t)0x00000100) /*!< Filter bit 8 */ -#define CAN_F3D1R_FD9 ((uint32_t)0x00000200) /*!< Filter bit 9 */ -#define CAN_F3D1R_FD10 ((uint32_t)0x00000400) /*!< Filter bit 10 */ -#define CAN_F3D1R_FD11 ((uint32_t)0x00000800) /*!< Filter bit 11 */ -#define CAN_F3D1R_FD12 ((uint32_t)0x00001000) /*!< Filter bit 12 */ -#define CAN_F3D1R_FD13 ((uint32_t)0x00002000) /*!< Filter bit 13 */ -#define CAN_F3D1R_FD14 ((uint32_t)0x00004000) /*!< Filter bit 14 */ -#define CAN_F3D1R_FD15 ((uint32_t)0x00008000) /*!< Filter bit 15 */ -#define CAN_F3D1R_FD16 ((uint32_t)0x00010000) /*!< Filter bit 16 */ -#define CAN_F3D1R_FD17 ((uint32_t)0x00020000) /*!< Filter bit 17 */ -#define CAN_F3D1R_FD18 ((uint32_t)0x00040000) /*!< Filter bit 18 */ -#define CAN_F3D1R_FD19 ((uint32_t)0x00080000) /*!< Filter bit 19 */ -#define CAN_F3D1R_FD20 ((uint32_t)0x00100000) /*!< Filter bit 20 */ -#define CAN_F3D1R_FD21 ((uint32_t)0x00200000) /*!< Filter bit 21 */ -#define CAN_F3D1R_FD22 ((uint32_t)0x00400000) /*!< Filter bit 22 */ -#define CAN_F3D1R_FD23 ((uint32_t)0x00800000) /*!< Filter bit 23 */ -#define CAN_F3D1R_FD24 ((uint32_t)0x01000000) /*!< Filter bit 24 */ -#define CAN_F3D1R_FD25 ((uint32_t)0x02000000) /*!< Filter bit 25 */ -#define CAN_F3D1R_FD26 ((uint32_t)0x04000000) /*!< Filter bit 26 */ -#define CAN_F3D1R_FD27 ((uint32_t)0x08000000) /*!< Filter bit 27 */ -#define CAN_F3D1R_FD28 ((uint32_t)0x10000000) /*!< Filter bit 28 */ -#define CAN_F3D1R_FD29 ((uint32_t)0x20000000) /*!< Filter bit 29 */ -#define CAN_F3D1R_FD30 ((uint32_t)0x40000000) /*!< Filter bit 30 */ -#define CAN_F3D1R_FD31 ((uint32_t)0x80000000) /*!< Filter bit 31 */ - -/******************* Bit definition for CAN_F4D1R register *******************/ -#define CAN_F4D1R_FD0 ((uint32_t)0x00000001) /*!< Filter bit 0 */ -#define CAN_F4D1R_FD1 ((uint32_t)0x00000002) /*!< Filter bit 1 */ -#define CAN_F4D1R_FD2 ((uint32_t)0x00000004) /*!< Filter bit 2 */ -#define CAN_F4D1R_FD3 ((uint32_t)0x00000008) /*!< Filter bit 3 */ -#define CAN_F4D1R_FD4 ((uint32_t)0x00000010) /*!< Filter bit 4 */ -#define CAN_F4D1R_FD5 ((uint32_t)0x00000020) /*!< Filter bit 5 */ -#define CAN_F4D1R_FD6 ((uint32_t)0x00000040) /*!< Filter bit 6 */ -#define CAN_F4D1R_FD7 ((uint32_t)0x00000080) /*!< Filter bit 7 */ -#define CAN_F4D1R_FD8 ((uint32_t)0x00000100) /*!< Filter bit 8 */ -#define CAN_F4D1R_FD9 ((uint32_t)0x00000200) /*!< Filter bit 9 */ -#define CAN_F4D1R_FD10 ((uint32_t)0x00000400) /*!< Filter bit 10 */ -#define CAN_F4D1R_FD11 ((uint32_t)0x00000800) /*!< Filter bit 11 */ -#define CAN_F4D1R_FD12 ((uint32_t)0x00001000) /*!< Filter bit 12 */ -#define CAN_F4D1R_FD13 ((uint32_t)0x00002000) /*!< Filter bit 13 */ -#define CAN_F4D1R_FD14 ((uint32_t)0x00004000) /*!< Filter bit 14 */ -#define CAN_F4D1R_FD15 ((uint32_t)0x00008000) /*!< Filter bit 15 */ -#define CAN_F4D1R_FD16 ((uint32_t)0x00010000) /*!< Filter bit 16 */ -#define CAN_F4D1R_FD17 ((uint32_t)0x00020000) /*!< Filter bit 17 */ -#define CAN_F4D1R_FD18 ((uint32_t)0x00040000) /*!< Filter bit 18 */ -#define CAN_F4D1R_FD19 ((uint32_t)0x00080000) /*!< Filter bit 19 */ -#define CAN_F4D1R_FD20 ((uint32_t)0x00100000) /*!< Filter bit 20 */ -#define CAN_F4D1R_FD21 ((uint32_t)0x00200000) /*!< Filter bit 21 */ -#define CAN_F4D1R_FD22 ((uint32_t)0x00400000) /*!< Filter bit 22 */ -#define CAN_F4D1R_FD23 ((uint32_t)0x00800000) /*!< Filter bit 23 */ -#define CAN_F4D1R_FD24 ((uint32_t)0x01000000) /*!< Filter bit 24 */ -#define CAN_F4D1R_FD25 ((uint32_t)0x02000000) /*!< Filter bit 25 */ -#define CAN_F4D1R_FD26 ((uint32_t)0x04000000) /*!< Filter bit 26 */ -#define CAN_F4D1R_FD27 ((uint32_t)0x08000000) /*!< Filter bit 27 */ -#define CAN_F4D1R_FD28 ((uint32_t)0x10000000) /*!< Filter bit 28 */ -#define CAN_F4D1R_FD29 ((uint32_t)0x20000000) /*!< Filter bit 29 */ -#define CAN_F4D1R_FD30 ((uint32_t)0x40000000) /*!< Filter bit 30 */ -#define CAN_F4D1R_FD31 ((uint32_t)0x80000000) /*!< Filter bit 31 */ - -/******************* Bit definition for CAN_F5D1R register *******************/ -#define CAN_F5D1R_FD0 ((uint32_t)0x00000001) /*!< Filter bit 0 */ -#define CAN_F5D1R_FD1 ((uint32_t)0x00000002) /*!< Filter bit 1 */ -#define CAN_F5D1R_FD2 ((uint32_t)0x00000004) /*!< Filter bit 2 */ -#define CAN_F5D1R_FD3 ((uint32_t)0x00000008) /*!< Filter bit 3 */ -#define CAN_F5D1R_FD4 ((uint32_t)0x00000010) /*!< Filter bit 4 */ -#define CAN_F5D1R_FD5 ((uint32_t)0x00000020) /*!< Filter bit 5 */ -#define CAN_F5D1R_FD6 ((uint32_t)0x00000040) /*!< Filter bit 6 */ -#define CAN_F5D1R_FD7 ((uint32_t)0x00000080) /*!< Filter bit 7 */ -#define CAN_F5D1R_FD8 ((uint32_t)0x00000100) /*!< Filter bit 8 */ -#define CAN_F5D1R_FD9 ((uint32_t)0x00000200) /*!< Filter bit 9 */ -#define CAN_F5D1R_FD10 ((uint32_t)0x00000400) /*!< Filter bit 10 */ -#define CAN_F5D1R_FD11 ((uint32_t)0x00000800) /*!< Filter bit 11 */ -#define CAN_F5D1R_FD12 ((uint32_t)0x00001000) /*!< Filter bit 12 */ -#define CAN_F5D1R_FD13 ((uint32_t)0x00002000) /*!< Filter bit 13 */ -#define CAN_F5D1R_FD14 ((uint32_t)0x00004000) /*!< Filter bit 14 */ -#define CAN_F5D1R_FD15 ((uint32_t)0x00008000) /*!< Filter bit 15 */ -#define CAN_F5D1R_FD16 ((uint32_t)0x00010000) /*!< Filter bit 16 */ -#define CAN_F5D1R_FD17 ((uint32_t)0x00020000) /*!< Filter bit 17 */ -#define CAN_F5D1R_FD18 ((uint32_t)0x00040000) /*!< Filter bit 18 */ -#define CAN_F5D1R_FD19 ((uint32_t)0x00080000) /*!< Filter bit 19 */ -#define CAN_F5D1R_FD20 ((uint32_t)0x00100000) /*!< Filter bit 20 */ -#define CAN_F5D1R_FD21 ((uint32_t)0x00200000) /*!< Filter bit 21 */ -#define CAN_F5D1R_FD22 ((uint32_t)0x00400000) /*!< Filter bit 22 */ -#define CAN_F5D1R_FD23 ((uint32_t)0x00800000) /*!< Filter bit 23 */ -#define CAN_F5D1R_FD24 ((uint32_t)0x01000000) /*!< Filter bit 24 */ -#define CAN_F5D1R_FD25 ((uint32_t)0x02000000) /*!< Filter bit 25 */ -#define CAN_F5D1R_FD26 ((uint32_t)0x04000000) /*!< Filter bit 26 */ -#define CAN_F5D1R_FD27 ((uint32_t)0x08000000) /*!< Filter bit 27 */ -#define CAN_F5D1R_FD28 ((uint32_t)0x10000000) /*!< Filter bit 28 */ -#define CAN_F5D1R_FD29 ((uint32_t)0x20000000) /*!< Filter bit 29 */ -#define CAN_F5D1R_FD30 ((uint32_t)0x40000000) /*!< Filter bit 30 */ -#define CAN_F5D1R_FD31 ((uint32_t)0x80000000) /*!< Filter bit 31 */ - -/******************* Bit definition for CAN_F6D1R register *******************/ -#define CAN_F6D1R_FD0 ((uint32_t)0x00000001) /*!< Filter bit 0 */ -#define CAN_F6D1R_FD1 ((uint32_t)0x00000002) /*!< Filter bit 1 */ -#define CAN_F6D1R_FD2 ((uint32_t)0x00000004) /*!< Filter bit 2 */ -#define CAN_F6D1R_FD3 ((uint32_t)0x00000008) /*!< Filter bit 3 */ -#define CAN_F6D1R_FD4 ((uint32_t)0x00000010) /*!< Filter bit 4 */ -#define CAN_F6D1R_FD5 ((uint32_t)0x00000020) /*!< Filter bit 5 */ -#define CAN_F6D1R_FD6 ((uint32_t)0x00000040) /*!< Filter bit 6 */ -#define CAN_F6D1R_FD7 ((uint32_t)0x00000080) /*!< Filter bit 7 */ -#define CAN_F6D1R_FD8 ((uint32_t)0x00000100) /*!< Filter bit 8 */ -#define CAN_F6D1R_FD9 ((uint32_t)0x00000200) /*!< Filter bit 9 */ -#define CAN_F6D1R_FD10 ((uint32_t)0x00000400) /*!< Filter bit 10 */ -#define CAN_F6D1R_FD11 ((uint32_t)0x00000800) /*!< Filter bit 11 */ -#define CAN_F6D1R_FD12 ((uint32_t)0x00001000) /*!< Filter bit 12 */ -#define CAN_F6D1R_FD13 ((uint32_t)0x00002000) /*!< Filter bit 13 */ -#define CAN_F6D1R_FD14 ((uint32_t)0x00004000) /*!< Filter bit 14 */ -#define CAN_F6D1R_FD15 ((uint32_t)0x00008000) /*!< Filter bit 15 */ -#define CAN_F6D1R_FD16 ((uint32_t)0x00010000) /*!< Filter bit 16 */ -#define CAN_F6D1R_FD17 ((uint32_t)0x00020000) /*!< Filter bit 17 */ -#define CAN_F6D1R_FD18 ((uint32_t)0x00040000) /*!< Filter bit 18 */ -#define CAN_F6D1R_FD19 ((uint32_t)0x00080000) /*!< Filter bit 19 */ -#define CAN_F6D1R_FD20 ((uint32_t)0x00100000) /*!< Filter bit 20 */ -#define CAN_F6D1R_FD21 ((uint32_t)0x00200000) /*!< Filter bit 21 */ -#define CAN_F6D1R_FD22 ((uint32_t)0x00400000) /*!< Filter bit 22 */ -#define CAN_F6D1R_FD23 ((uint32_t)0x00800000) /*!< Filter bit 23 */ -#define CAN_F6D1R_FD24 ((uint32_t)0x01000000) /*!< Filter bit 24 */ -#define CAN_F6D1R_FD25 ((uint32_t)0x02000000) /*!< Filter bit 25 */ -#define CAN_F6D1R_FD26 ((uint32_t)0x04000000) /*!< Filter bit 26 */ -#define CAN_F6D1R_FD27 ((uint32_t)0x08000000) /*!< Filter bit 27 */ -#define CAN_F6D1R_FD28 ((uint32_t)0x10000000) /*!< Filter bit 28 */ -#define CAN_F6D1R_FD29 ((uint32_t)0x20000000) /*!< Filter bit 29 */ -#define CAN_F6D1R_FD30 ((uint32_t)0x40000000) /*!< Filter bit 30 */ -#define CAN_F6D1R_FD31 ((uint32_t)0x80000000) /*!< Filter bit 31 */ - -/******************* Bit definition for CAN_F7D1R register *******************/ -#define CAN_F7D1R_FD0 ((uint32_t)0x00000001) /*!< Filter bit 0 */ -#define CAN_F7D1R_FD1 ((uint32_t)0x00000002) /*!< Filter bit 1 */ -#define CAN_F7D1R_FD2 ((uint32_t)0x00000004) /*!< Filter bit 2 */ -#define CAN_F7D1R_FD3 ((uint32_t)0x00000008) /*!< Filter bit 3 */ -#define CAN_F7D1R_FD4 ((uint32_t)0x00000010) /*!< Filter bit 4 */ -#define CAN_F7D1R_FD5 ((uint32_t)0x00000020) /*!< Filter bit 5 */ -#define CAN_F7D1R_FD6 ((uint32_t)0x00000040) /*!< Filter bit 6 */ -#define CAN_F7D1R_FD7 ((uint32_t)0x00000080) /*!< Filter bit 7 */ -#define CAN_F7D1R_FD8 ((uint32_t)0x00000100) /*!< Filter bit 8 */ -#define CAN_F7D1R_FD9 ((uint32_t)0x00000200) /*!< Filter bit 9 */ -#define CAN_F7D1R_FD10 ((uint32_t)0x00000400) /*!< Filter bit 10 */ -#define CAN_F7D1R_FD11 ((uint32_t)0x00000800) /*!< Filter bit 11 */ -#define CAN_F7D1R_FD12 ((uint32_t)0x00001000) /*!< Filter bit 12 */ -#define CAN_F7D1R_FD13 ((uint32_t)0x00002000) /*!< Filter bit 13 */ -#define CAN_F7D1R_FD14 ((uint32_t)0x00004000) /*!< Filter bit 14 */ -#define CAN_F7D1R_FD15 ((uint32_t)0x00008000) /*!< Filter bit 15 */ -#define CAN_F7D1R_FD16 ((uint32_t)0x00010000) /*!< Filter bit 16 */ -#define CAN_F7D1R_FD17 ((uint32_t)0x00020000) /*!< Filter bit 17 */ -#define CAN_F7D1R_FD18 ((uint32_t)0x00040000) /*!< Filter bit 18 */ -#define CAN_F7D1R_FD19 ((uint32_t)0x00080000) /*!< Filter bit 19 */ -#define CAN_F7D1R_FD20 ((uint32_t)0x00100000) /*!< Filter bit 20 */ -#define CAN_F7D1R_FD21 ((uint32_t)0x00200000) /*!< Filter bit 21 */ -#define CAN_F7D1R_FD22 ((uint32_t)0x00400000) /*!< Filter bit 22 */ -#define CAN_F7D1R_FD23 ((uint32_t)0x00800000) /*!< Filter bit 23 */ -#define CAN_F7D1R_FD24 ((uint32_t)0x01000000) /*!< Filter bit 24 */ -#define CAN_F7D1R_FD25 ((uint32_t)0x02000000) /*!< Filter bit 25 */ -#define CAN_F7D1R_FD26 ((uint32_t)0x04000000) /*!< Filter bit 26 */ -#define CAN_F7D1R_FD27 ((uint32_t)0x08000000) /*!< Filter bit 27 */ -#define CAN_F7D1R_FD28 ((uint32_t)0x10000000) /*!< Filter bit 28 */ -#define CAN_F7D1R_FD29 ((uint32_t)0x20000000) /*!< Filter bit 29 */ -#define CAN_F7D1R_FD30 ((uint32_t)0x40000000) /*!< Filter bit 30 */ -#define CAN_F7D1R_FD31 ((uint32_t)0x80000000) /*!< Filter bit 31 */ - -/******************* Bit definition for CAN_F8D1R register *******************/ -#define CAN_F8D1R_FD0 ((uint32_t)0x00000001) /*!< Filter bit 0 */ -#define CAN_F8D1R_FD1 ((uint32_t)0x00000002) /*!< Filter bit 1 */ -#define CAN_F8D1R_FD2 ((uint32_t)0x00000004) /*!< Filter bit 2 */ -#define CAN_F8D1R_FD3 ((uint32_t)0x00000008) /*!< Filter bit 3 */ -#define CAN_F8D1R_FD4 ((uint32_t)0x00000010) /*!< Filter bit 4 */ -#define CAN_F8D1R_FD5 ((uint32_t)0x00000020) /*!< Filter bit 5 */ -#define CAN_F8D1R_FD6 ((uint32_t)0x00000040) /*!< Filter bit 6 */ -#define CAN_F8D1R_FD7 ((uint32_t)0x00000080) /*!< Filter bit 7 */ -#define CAN_F8D1R_FD8 ((uint32_t)0x00000100) /*!< Filter bit 8 */ -#define CAN_F8D1R_FD9 ((uint32_t)0x00000200) /*!< Filter bit 9 */ -#define CAN_F8D1R_FD10 ((uint32_t)0x00000400) /*!< Filter bit 10 */ -#define CAN_F8D1R_FD11 ((uint32_t)0x00000800) /*!< Filter bit 11 */ -#define CAN_F8D1R_FD12 ((uint32_t)0x00001000) /*!< Filter bit 12 */ -#define CAN_F8D1R_FD13 ((uint32_t)0x00002000) /*!< Filter bit 13 */ -#define CAN_F8D1R_FD14 ((uint32_t)0x00004000) /*!< Filter bit 14 */ -#define CAN_F8D1R_FD15 ((uint32_t)0x00008000) /*!< Filter bit 15 */ -#define CAN_F8D1R_FD16 ((uint32_t)0x00010000) /*!< Filter bit 16 */ -#define CAN_F8D1R_FD17 ((uint32_t)0x00020000) /*!< Filter bit 17 */ -#define CAN_F8D1R_FD18 ((uint32_t)0x00040000) /*!< Filter bit 18 */ -#define CAN_F8D1R_FD19 ((uint32_t)0x00080000) /*!< Filter bit 19 */ -#define CAN_F8D1R_FD20 ((uint32_t)0x00100000) /*!< Filter bit 20 */ -#define CAN_F8D1R_FD21 ((uint32_t)0x00200000) /*!< Filter bit 21 */ -#define CAN_F8D1R_FD22 ((uint32_t)0x00400000) /*!< Filter bit 22 */ -#define CAN_F8D1R_FD23 ((uint32_t)0x00800000) /*!< Filter bit 23 */ -#define CAN_F8D1R_FD24 ((uint32_t)0x01000000) /*!< Filter bit 24 */ -#define CAN_F8D1R_FD25 ((uint32_t)0x02000000) /*!< Filter bit 25 */ -#define CAN_F8D1R_FD26 ((uint32_t)0x04000000) /*!< Filter bit 26 */ -#define CAN_F8D1R_FD27 ((uint32_t)0x08000000) /*!< Filter bit 27 */ -#define CAN_F8D1R_FD28 ((uint32_t)0x10000000) /*!< Filter bit 28 */ -#define CAN_F8D1R_FD29 ((uint32_t)0x20000000) /*!< Filter bit 29 */ -#define CAN_F8D1R_FD30 ((uint32_t)0x40000000) /*!< Filter bit 30 */ -#define CAN_F8D1R_FD31 ((uint32_t)0x80000000) /*!< Filter bit 31 */ - -/******************* Bit definition for CAN_F9D1R register *******************/ -#define CAN_F9D1R_FD0 ((uint32_t)0x00000001) /*!< Filter bit 0 */ -#define CAN_F9D1R_FD1 ((uint32_t)0x00000002) /*!< Filter bit 1 */ -#define CAN_F9D1R_FD2 ((uint32_t)0x00000004) /*!< Filter bit 2 */ -#define CAN_F9D1R_FD3 ((uint32_t)0x00000008) /*!< Filter bit 3 */ -#define CAN_F9D1R_FD4 ((uint32_t)0x00000010) /*!< Filter bit 4 */ -#define CAN_F9D1R_FD5 ((uint32_t)0x00000020) /*!< Filter bit 5 */ -#define CAN_F9D1R_FD6 ((uint32_t)0x00000040) /*!< Filter bit 6 */ -#define CAN_F9D1R_FD7 ((uint32_t)0x00000080) /*!< Filter bit 7 */ -#define CAN_F9D1R_FD8 ((uint32_t)0x00000100) /*!< Filter bit 8 */ -#define CAN_F9D1R_FD9 ((uint32_t)0x00000200) /*!< Filter bit 9 */ -#define CAN_F9D1R_FD10 ((uint32_t)0x00000400) /*!< Filter bit 10 */ -#define CAN_F9D1R_FD11 ((uint32_t)0x00000800) /*!< Filter bit 11 */ -#define CAN_F9D1R_FD12 ((uint32_t)0x00001000) /*!< Filter bit 12 */ -#define CAN_F9D1R_FD13 ((uint32_t)0x00002000) /*!< Filter bit 13 */ -#define CAN_F9D1R_FD14 ((uint32_t)0x00004000) /*!< Filter bit 14 */ -#define CAN_F9D1R_FD15 ((uint32_t)0x00008000) /*!< Filter bit 15 */ -#define CAN_F9D1R_FD16 ((uint32_t)0x00010000) /*!< Filter bit 16 */ -#define CAN_F9D1R_FD17 ((uint32_t)0x00020000) /*!< Filter bit 17 */ -#define CAN_F9D1R_FD18 ((uint32_t)0x00040000) /*!< Filter bit 18 */ -#define CAN_F9D1R_FD19 ((uint32_t)0x00080000) /*!< Filter bit 19 */ -#define CAN_F9D1R_FD20 ((uint32_t)0x00100000) /*!< Filter bit 20 */ -#define CAN_F9D1R_FD21 ((uint32_t)0x00200000) /*!< Filter bit 21 */ -#define CAN_F9D1R_FD22 ((uint32_t)0x00400000) /*!< Filter bit 22 */ -#define CAN_F9D1R_FD23 ((uint32_t)0x00800000) /*!< Filter bit 23 */ -#define CAN_F9D1R_FD24 ((uint32_t)0x01000000) /*!< Filter bit 24 */ -#define CAN_F9D1R_FD25 ((uint32_t)0x02000000) /*!< Filter bit 25 */ -#define CAN_F9D1R_FD26 ((uint32_t)0x04000000) /*!< Filter bit 26 */ -#define CAN_F9D1R_FD27 ((uint32_t)0x08000000) /*!< Filter bit 27 */ -#define CAN_F9D1R_FD28 ((uint32_t)0x10000000) /*!< Filter bit 28 */ -#define CAN_F9D1R_FD29 ((uint32_t)0x20000000) /*!< Filter bit 29 */ -#define CAN_F9D1R_FD30 ((uint32_t)0x40000000) /*!< Filter bit 30 */ -#define CAN_F9D1R_FD31 ((uint32_t)0x80000000) /*!< Filter bit 31 */ - -/******************* Bit definition for CAN_F10D1R register *******************/ -#define CAN_F10D1R_FD0 ((uint32_t)0x00000001) /*!< Filter bit 0 */ -#define CAN_F10D1R_FD1 ((uint32_t)0x00000002) /*!< Filter bit 1 */ -#define CAN_F10D1R_FD2 ((uint32_t)0x00000004) /*!< Filter bit 2 */ -#define CAN_F10D1R_FD3 ((uint32_t)0x00000008) /*!< Filter bit 3 */ -#define CAN_F10D1R_FD4 ((uint32_t)0x00000010) /*!< Filter bit 4 */ -#define CAN_F10D1R_FD5 ((uint32_t)0x00000020) /*!< Filter bit 5 */ -#define CAN_F10D1R_FD6 ((uint32_t)0x00000040) /*!< Filter bit 6 */ -#define CAN_F10D1R_FD7 ((uint32_t)0x00000080) /*!< Filter bit 7 */ -#define CAN_F10D1R_FD8 ((uint32_t)0x00000100) /*!< Filter bit 8 */ -#define CAN_F10D1R_FD9 ((uint32_t)0x00000200) /*!< Filter bit 9 */ -#define CAN_F10D1R_FD10 ((uint32_t)0x00000400) /*!< Filter bit 10 */ -#define CAN_F10D1R_FD11 ((uint32_t)0x00000800) /*!< Filter bit 11 */ -#define CAN_F10D1R_FD12 ((uint32_t)0x00001000) /*!< Filter bit 12 */ -#define CAN_F10D1R_FD13 ((uint32_t)0x00002000) /*!< Filter bit 13 */ -#define CAN_F10D1R_FD14 ((uint32_t)0x00004000) /*!< Filter bit 14 */ -#define CAN_F10D1R_FD15 ((uint32_t)0x00008000) /*!< Filter bit 15 */ -#define CAN_F10D1R_FD16 ((uint32_t)0x00010000) /*!< Filter bit 16 */ -#define CAN_F10D1R_FD17 ((uint32_t)0x00020000) /*!< Filter bit 17 */ -#define CAN_F10D1R_FD18 ((uint32_t)0x00040000) /*!< Filter bit 18 */ -#define CAN_F10D1R_FD19 ((uint32_t)0x00080000) /*!< Filter bit 19 */ -#define CAN_F10D1R_FD20 ((uint32_t)0x00100000) /*!< Filter bit 20 */ -#define CAN_F10D1R_FD21 ((uint32_t)0x00200000) /*!< Filter bit 21 */ -#define CAN_F10D1R_FD22 ((uint32_t)0x00400000) /*!< Filter bit 22 */ -#define CAN_F10D1R_FD23 ((uint32_t)0x00800000) /*!< Filter bit 23 */ -#define CAN_F10D1R_FD24 ((uint32_t)0x01000000) /*!< Filter bit 24 */ -#define CAN_F10D1R_FD25 ((uint32_t)0x02000000) /*!< Filter bit 25 */ -#define CAN_F10D1R_FD26 ((uint32_t)0x04000000) /*!< Filter bit 26 */ -#define CAN_F10D1R_FD27 ((uint32_t)0x08000000) /*!< Filter bit 27 */ -#define CAN_F10D1R_FD28 ((uint32_t)0x10000000) /*!< Filter bit 28 */ -#define CAN_F10D1R_FD29 ((uint32_t)0x20000000) /*!< Filter bit 29 */ -#define CAN_F10D1R_FD30 ((uint32_t)0x40000000) /*!< Filter bit 30 */ -#define CAN_F10D1R_FD31 ((uint32_t)0x80000000) /*!< Filter bit 31 */ - -/******************* Bit definition for CAN_F11D1R register *******************/ -#define CAN_F11D1R_FD0 ((uint32_t)0x00000001) /*!< Filter bit 0 */ -#define CAN_F11D1R_FD1 ((uint32_t)0x00000002) /*!< Filter bit 1 */ -#define CAN_F11D1R_FD2 ((uint32_t)0x00000004) /*!< Filter bit 2 */ -#define CAN_F11D1R_FD3 ((uint32_t)0x00000008) /*!< Filter bit 3 */ -#define CAN_F11D1R_FD4 ((uint32_t)0x00000010) /*!< Filter bit 4 */ -#define CAN_F11D1R_FD5 ((uint32_t)0x00000020) /*!< Filter bit 5 */ -#define CAN_F11D1R_FD6 ((uint32_t)0x00000040) /*!< Filter bit 6 */ -#define CAN_F11D1R_FD7 ((uint32_t)0x00000080) /*!< Filter bit 7 */ -#define CAN_F11D1R_FD8 ((uint32_t)0x00000100) /*!< Filter bit 8 */ -#define CAN_F11D1R_FD9 ((uint32_t)0x00000200) /*!< Filter bit 9 */ -#define CAN_F11D1R_FD10 ((uint32_t)0x00000400) /*!< Filter bit 10 */ -#define CAN_F11D1R_FD11 ((uint32_t)0x00000800) /*!< Filter bit 11 */ -#define CAN_F11D1R_FD12 ((uint32_t)0x00001000) /*!< Filter bit 12 */ -#define CAN_F11D1R_FD13 ((uint32_t)0x00002000) /*!< Filter bit 13 */ -#define CAN_F11D1R_FD14 ((uint32_t)0x00004000) /*!< Filter bit 14 */ -#define CAN_F11D1R_FD15 ((uint32_t)0x00008000) /*!< Filter bit 15 */ -#define CAN_F11D1R_FD16 ((uint32_t)0x00010000) /*!< Filter bit 16 */ -#define CAN_F11D1R_FD17 ((uint32_t)0x00020000) /*!< Filter bit 17 */ -#define CAN_F11D1R_FD18 ((uint32_t)0x00040000) /*!< Filter bit 18 */ -#define CAN_F11D1R_FD19 ((uint32_t)0x00080000) /*!< Filter bit 19 */ -#define CAN_F11D1R_FD20 ((uint32_t)0x00100000) /*!< Filter bit 20 */ -#define CAN_F11D1R_FD21 ((uint32_t)0x00200000) /*!< Filter bit 21 */ -#define CAN_F11D1R_FD22 ((uint32_t)0x00400000) /*!< Filter bit 22 */ -#define CAN_F11D1R_FD23 ((uint32_t)0x00800000) /*!< Filter bit 23 */ -#define CAN_F11D1R_FD24 ((uint32_t)0x01000000) /*!< Filter bit 24 */ -#define CAN_F11D1R_FD25 ((uint32_t)0x02000000) /*!< Filter bit 25 */ -#define CAN_F11D1R_FD26 ((uint32_t)0x04000000) /*!< Filter bit 26 */ -#define CAN_F11D1R_FD27 ((uint32_t)0x08000000) /*!< Filter bit 27 */ -#define CAN_F11D1R_FD28 ((uint32_t)0x10000000) /*!< Filter bit 28 */ -#define CAN_F11D1R_FD29 ((uint32_t)0x20000000) /*!< Filter bit 29 */ -#define CAN_F11D1R_FD30 ((uint32_t)0x40000000) /*!< Filter bit 30 */ -#define CAN_F11D1R_FD31 ((uint32_t)0x80000000) /*!< Filter bit 31 */ - -/******************* Bit definition for CAN_F12D1R register *******************/ -#define CAN_F12D1R_FD0 ((uint32_t)0x00000001) /*!< Filter bit 0 */ -#define CAN_F12D1R_FD1 ((uint32_t)0x00000002) /*!< Filter bit 1 */ -#define CAN_F12D1R_FD2 ((uint32_t)0x00000004) /*!< Filter bit 2 */ -#define CAN_F12D1R_FD3 ((uint32_t)0x00000008) /*!< Filter bit 3 */ -#define CAN_F12D1R_FD4 ((uint32_t)0x00000010) /*!< Filter bit 4 */ -#define CAN_F12D1R_FD5 ((uint32_t)0x00000020) /*!< Filter bit 5 */ -#define CAN_F12D1R_FD6 ((uint32_t)0x00000040) /*!< Filter bit 6 */ -#define CAN_F12D1R_FD7 ((uint32_t)0x00000080) /*!< Filter bit 7 */ -#define CAN_F12D1R_FD8 ((uint32_t)0x00000100) /*!< Filter bit 8 */ -#define CAN_F12D1R_FD9 ((uint32_t)0x00000200) /*!< Filter bit 9 */ -#define CAN_F12D1R_FD10 ((uint32_t)0x00000400) /*!< Filter bit 10 */ -#define CAN_F12D1R_FD11 ((uint32_t)0x00000800) /*!< Filter bit 11 */ -#define CAN_F12D1R_FD12 ((uint32_t)0x00001000) /*!< Filter bit 12 */ -#define CAN_F12D1R_FD13 ((uint32_t)0x00002000) /*!< Filter bit 13 */ -#define CAN_F12D1R_FD14 ((uint32_t)0x00004000) /*!< Filter bit 14 */ -#define CAN_F12D1R_FD15 ((uint32_t)0x00008000) /*!< Filter bit 15 */ -#define CAN_F12D1R_FD16 ((uint32_t)0x00010000) /*!< Filter bit 16 */ -#define CAN_F12D1R_FD17 ((uint32_t)0x00020000) /*!< Filter bit 17 */ -#define CAN_F12D1R_FD18 ((uint32_t)0x00040000) /*!< Filter bit 18 */ -#define CAN_F12D1R_FD19 ((uint32_t)0x00080000) /*!< Filter bit 19 */ -#define CAN_F12D1R_FD20 ((uint32_t)0x00100000) /*!< Filter bit 20 */ -#define CAN_F12D1R_FD21 ((uint32_t)0x00200000) /*!< Filter bit 21 */ -#define CAN_F12D1R_FD22 ((uint32_t)0x00400000) /*!< Filter bit 22 */ -#define CAN_F12D1R_FD23 ((uint32_t)0x00800000) /*!< Filter bit 23 */ -#define CAN_F12D1R_FD24 ((uint32_t)0x01000000) /*!< Filter bit 24 */ -#define CAN_F12D1R_FD25 ((uint32_t)0x02000000) /*!< Filter bit 25 */ -#define CAN_F12D1R_FD26 ((uint32_t)0x04000000) /*!< Filter bit 26 */ -#define CAN_F12D1R_FD27 ((uint32_t)0x08000000) /*!< Filter bit 27 */ -#define CAN_F12D1R_FD28 ((uint32_t)0x10000000) /*!< Filter bit 28 */ -#define CAN_F12D1R_FD29 ((uint32_t)0x20000000) /*!< Filter bit 29 */ -#define CAN_F12D1R_FD30 ((uint32_t)0x40000000) /*!< Filter bit 30 */ -#define CAN_F12D1R_FD31 ((uint32_t)0x80000000) /*!< Filter bit 31 */ - -/******************* Bit definition for CAN_F13D1R register *******************/ -#define CAN_F13D1R_FD0 ((uint32_t)0x00000001) /*!< Filter bit 0 */ -#define CAN_F13D1R_FD1 ((uint32_t)0x00000002) /*!< Filter bit 1 */ -#define CAN_F13D1R_FD2 ((uint32_t)0x00000004) /*!< Filter bit 2 */ -#define CAN_F13D1R_FD3 ((uint32_t)0x00000008) /*!< Filter bit 3 */ -#define CAN_F13D1R_FD4 ((uint32_t)0x00000010) /*!< Filter bit 4 */ -#define CAN_F13D1R_FD5 ((uint32_t)0x00000020) /*!< Filter bit 5 */ -#define CAN_F13D1R_FD6 ((uint32_t)0x00000040) /*!< Filter bit 6 */ -#define CAN_F13D1R_FD7 ((uint32_t)0x00000080) /*!< Filter bit 7 */ -#define CAN_F13D1R_FD8 ((uint32_t)0x00000100) /*!< Filter bit 8 */ -#define CAN_F13D1R_FD9 ((uint32_t)0x00000200) /*!< Filter bit 9 */ -#define CAN_F13D1R_FD10 ((uint32_t)0x00000400) /*!< Filter bit 10 */ -#define CAN_F13D1R_FD11 ((uint32_t)0x00000800) /*!< Filter bit 11 */ -#define CAN_F13D1R_FD12 ((uint32_t)0x00001000) /*!< Filter bit 12 */ -#define CAN_F13D1R_FD13 ((uint32_t)0x00002000) /*!< Filter bit 13 */ -#define CAN_F13D1R_FD14 ((uint32_t)0x00004000) /*!< Filter bit 14 */ -#define CAN_F13D1R_FD15 ((uint32_t)0x00008000) /*!< Filter bit 15 */ -#define CAN_F13D1R_FD16 ((uint32_t)0x00010000) /*!< Filter bit 16 */ -#define CAN_F13D1R_FD17 ((uint32_t)0x00020000) /*!< Filter bit 17 */ -#define CAN_F13D1R_FD18 ((uint32_t)0x00040000) /*!< Filter bit 18 */ -#define CAN_F13D1R_FD19 ((uint32_t)0x00080000) /*!< Filter bit 19 */ -#define CAN_F13D1R_FD20 ((uint32_t)0x00100000) /*!< Filter bit 20 */ -#define CAN_F13D1R_FD21 ((uint32_t)0x00200000) /*!< Filter bit 21 */ -#define CAN_F13D1R_FD22 ((uint32_t)0x00400000) /*!< Filter bit 22 */ -#define CAN_F13D1R_FD23 ((uint32_t)0x00800000) /*!< Filter bit 23 */ -#define CAN_F13D1R_FD24 ((uint32_t)0x01000000) /*!< Filter bit 24 */ -#define CAN_F13D1R_FD25 ((uint32_t)0x02000000) /*!< Filter bit 25 */ -#define CAN_F13D1R_FD26 ((uint32_t)0x04000000) /*!< Filter bit 26 */ -#define CAN_F13D1R_FD27 ((uint32_t)0x08000000) /*!< Filter bit 27 */ -#define CAN_F13D1R_FD28 ((uint32_t)0x10000000) /*!< Filter bit 28 */ -#define CAN_F13D1R_FD29 ((uint32_t)0x20000000) /*!< Filter bit 29 */ -#define CAN_F13D1R_FD30 ((uint32_t)0x40000000) /*!< Filter bit 30 */ -#define CAN_F13D1R_FD31 ((uint32_t)0x80000000) /*!< Filter bit 31 */ - -/******************* Bit definition for CAN_F14D1R register *******************/ -#define CAN_F14D1R_FD0 ((uint32_t)0x00000001) /*!< Filter bit 0 */ -#define CAN_F14D1R_FD1 ((uint32_t)0x00000002) /*!< Filter bit 1 */ -#define CAN_F14D1R_FD2 ((uint32_t)0x00000004) /*!< Filter bit 2 */ -#define CAN_F14D1R_FD3 ((uint32_t)0x00000008) /*!< Filter bit 3 */ -#define CAN_F14D1R_FD4 ((uint32_t)0x00000010) /*!< Filter bit 4 */ -#define CAN_F14D1R_FD5 ((uint32_t)0x00000020) /*!< Filter bit 5 */ -#define CAN_F14D1R_FD6 ((uint32_t)0x00000040) /*!< Filter bit 6 */ -#define CAN_F14D1R_FD7 ((uint32_t)0x00000080) /*!< Filter bit 7 */ -#define CAN_F14D1R_FD8 ((uint32_t)0x00000100) /*!< Filter bit 8 */ -#define CAN_F14D1R_FD9 ((uint32_t)0x00000200) /*!< Filter bit 9 */ -#define CAN_F14D1R_FD10 ((uint32_t)0x00000400) /*!< Filter bit 10 */ -#define CAN_F14D1R_FD11 ((uint32_t)0x00000800) /*!< Filter bit 11 */ -#define CAN_F14D1R_FD12 ((uint32_t)0x00001000) /*!< Filter bit 12 */ -#define CAN_F14D1R_FD13 ((uint32_t)0x00002000) /*!< Filter bit 13 */ -#define CAN_F14D1R_FD14 ((uint32_t)0x00004000) /*!< Filter bit 14 */ -#define CAN_F14D1R_FD15 ((uint32_t)0x00008000) /*!< Filter bit 15 */ -#define CAN_F14D1R_FD16 ((uint32_t)0x00010000) /*!< Filter bit 16 */ -#define CAN_F14D1R_FD17 ((uint32_t)0x00020000) /*!< Filter bit 17 */ -#define CAN_F14D1R_FD18 ((uint32_t)0x00040000) /*!< Filter bit 18 */ -#define CAN_F14D1R_FD19 ((uint32_t)0x00080000) /*!< Filter bit 19 */ -#define CAN_F14D1R_FD20 ((uint32_t)0x00100000) /*!< Filter bit 20 */ -#define CAN_F14D1R_FD21 ((uint32_t)0x00200000) /*!< Filter bit 21 */ -#define CAN_F14D1R_FD22 ((uint32_t)0x00400000) /*!< Filter bit 22 */ -#define CAN_F14D1R_FD23 ((uint32_t)0x00800000) /*!< Filter bit 23 */ -#define CAN_F14D1R_FD24 ((uint32_t)0x01000000) /*!< Filter bit 24 */ -#define CAN_F14D1R_FD25 ((uint32_t)0x02000000) /*!< Filter bit 25 */ -#define CAN_F14D1R_FD26 ((uint32_t)0x04000000) /*!< Filter bit 26 */ -#define CAN_F14D1R_FD27 ((uint32_t)0x08000000) /*!< Filter bit 27 */ -#define CAN_F14D1R_FD28 ((uint32_t)0x10000000) /*!< Filter bit 28 */ -#define CAN_F14D1R_FD29 ((uint32_t)0x20000000) /*!< Filter bit 29 */ -#define CAN_F14D1R_FD30 ((uint32_t)0x40000000) /*!< Filter bit 30 */ -#define CAN_F14D1R_FD31 ((uint32_t)0x80000000) /*!< Filter bit 31 */ - -/******************* Bit for CAN_F15D1R register *******************/ -#define CAN_F15D1R_FD0 ((uint32_t)0x00000001) /*!< Filter bit 0 */ -#define CAN_F15D1R_FD1 ((uint32_t)0x00000002) /*!< Filter bit 1 */ -#define CAN_F15D1R_FD2 ((uint32_t)0x00000004) /*!< Filter bit 2 */ -#define CAN_F15D1R_FD3 ((uint32_t)0x00000008) /*!< Filter bit 3 */ -#define CAN_F15D1R_FD4 ((uint32_t)0x00000010) /*!< Filter bit 4 */ -#define CAN_F15D1R_FD5 ((uint32_t)0x00000020) /*!< Filter bit 5 */ -#define CAN_F15D1R_FD6 ((uint32_t)0x00000040) /*!< Filter bit 6 */ -#define CAN_F15D1R_FD7 ((uint32_t)0x00000080) /*!< Filter bit 7 */ -#define CAN_F15D1R_FD8 ((uint32_t)0x00000100) /*!< Filter bit 8 */ -#define CAN_F15D1R_FD9 ((uint32_t)0x00000200) /*!< Filter bit 9 */ -#define CAN_F15D1R_FD10 ((uint32_t)0x00000400) /*!< Filter bit 10 */ -#define CAN_F15D1R_FD11 ((uint32_t)0x00000800) /*!< Filter bit 11 */ -#define CAN_F15D1R_FD12 ((uint32_t)0x00001000) /*!< Filter bit 12 */ -#define CAN_F15D1R_FD13 ((uint32_t)0x00002000) /*!< Filter bit 13 */ -#define CAN_F15D1R_FD14 ((uint32_t)0x00004000) /*!< Filter bit 14 */ -#define CAN_F15D1R_FD15 ((uint32_t)0x00008000) /*!< Filter bit 15 */ -#define CAN_F15D1R_FD16 ((uint32_t)0x00010000) /*!< Filter bit 16 */ -#define CAN_F15D1R_FD17 ((uint32_t)0x00020000) /*!< Filter bit 17 */ -#define CAN_F15D1R_FD18 ((uint32_t)0x00040000) /*!< Filter bit 18 */ -#define CAN_F15D1R_FD19 ((uint32_t)0x00080000) /*!< Filter bit 19 */ -#define CAN_F15D1R_FD20 ((uint32_t)0x00100000) /*!< Filter bit 20 */ -#define CAN_F15D1R_FD21 ((uint32_t)0x00200000) /*!< Filter bit 21 */ -#define CAN_F15D1R_FD22 ((uint32_t)0x00400000) /*!< Filter bit 22 */ -#define CAN_F15D1R_FD23 ((uint32_t)0x00800000) /*!< Filter bit 23 */ -#define CAN_F15D1R_FD24 ((uint32_t)0x01000000) /*!< Filter bit 24 */ -#define CAN_F15D1R_FD25 ((uint32_t)0x02000000) /*!< Filter bit 25 */ -#define CAN_F15D1R_FD26 ((uint32_t)0x04000000) /*!< Filter bit 26 */ -#define CAN_F15D1R_FD27 ((uint32_t)0x08000000) /*!< Filter bit 27 */ -#define CAN_F15D1R_FD28 ((uint32_t)0x10000000) /*!< Filter bit 28 */ -#define CAN_F15D1R_FD29 ((uint32_t)0x20000000) /*!< Filter bit 29 */ -#define CAN_F15D1R_FD30 ((uint32_t)0x40000000) /*!< Filter bit 30 */ -#define CAN_F15D1R_FD31 ((uint32_t)0x80000000) /*!< Filter bit 31 */ - -/******************* Bit definition for CAN_F16D1R register *******************/ -#define CAN_F16D1R_FD0 ((uint32_t)0x00000001) /*!< Filter bit 0 */ -#define CAN_F16D1R_FD1 ((uint32_t)0x00000002) /*!< Filter bit 1 */ -#define CAN_F16D1R_FD2 ((uint32_t)0x00000004) /*!< Filter bit 2 */ -#define CAN_F16D1R_FD3 ((uint32_t)0x00000008) /*!< Filter bit 3 */ -#define CAN_F16D1R_FD4 ((uint32_t)0x00000010) /*!< Filter bit 4 */ -#define CAN_F16D1R_FD5 ((uint32_t)0x00000020) /*!< Filter bit 5 */ -#define CAN_F16D1R_FD6 ((uint32_t)0x00000040) /*!< Filter bit 6 */ -#define CAN_F16D1R_FD7 ((uint32_t)0x00000080) /*!< Filter bit 7 */ -#define CAN_F16D1R_FD8 ((uint32_t)0x00000100) /*!< Filter bit 8 */ -#define CAN_F16D1R_FD9 ((uint32_t)0x00000200) /*!< Filter bit 9 */ -#define CAN_F16D1R_FD10 ((uint32_t)0x00000400) /*!< Filter bit 10 */ -#define CAN_F16D1R_FD11 ((uint32_t)0x00000800) /*!< Filter bit 11 */ -#define CAN_F16D1R_FD12 ((uint32_t)0x00001000) /*!< Filter bit 12 */ -#define CAN_F16D1R_FD13 ((uint32_t)0x00002000) /*!< Filter bit 13 */ -#define CAN_F16D1R_FD14 ((uint32_t)0x00004000) /*!< Filter bit 14 */ -#define CAN_F16D1R_FD15 ((uint32_t)0x00008000) /*!< Filter bit 15 */ -#define CAN_F16D1R_FD16 ((uint32_t)0x00010000) /*!< Filter bit 16 */ -#define CAN_F16D1R_FD17 ((uint32_t)0x00020000) /*!< Filter bit 17 */ -#define CAN_F16D1R_FD18 ((uint32_t)0x00040000) /*!< Filter bit 18 */ -#define CAN_F16D1R_FD19 ((uint32_t)0x00080000) /*!< Filter bit 19 */ -#define CAN_F16D1R_FD20 ((uint32_t)0x00100000) /*!< Filter bit 20 */ -#define CAN_F16D1R_FD21 ((uint32_t)0x00200000) /*!< Filter bit 21 */ -#define CAN_F16D1R_FD22 ((uint32_t)0x00400000) /*!< Filter bit 22 */ -#define CAN_F16D1R_FD23 ((uint32_t)0x00800000) /*!< Filter bit 23 */ -#define CAN_F16D1R_FD24 ((uint32_t)0x01000000) /*!< Filter bit 24 */ -#define CAN_F16D1R_FD25 ((uint32_t)0x02000000) /*!< Filter bit 25 */ -#define CAN_F16D1R_FD26 ((uint32_t)0x04000000) /*!< Filter bit 26 */ -#define CAN_F16D1R_FD27 ((uint32_t)0x08000000) /*!< Filter bit 27 */ -#define CAN_F16D1R_FD28 ((uint32_t)0x10000000) /*!< Filter bit 28 */ -#define CAN_F16D1R_FD29 ((uint32_t)0x20000000) /*!< Filter bit 29 */ -#define CAN_F16D1R_FD30 ((uint32_t)0x40000000) /*!< Filter bit 30 */ -#define CAN_F16D1R_FD31 ((uint32_t)0x80000000) /*!< Filter bit 31 */ - -/******************* Bit definition for CAN_F17D1R register *******************/ -#define CAN_F17D1R_FD0 ((uint32_t)0x00000001) /*!< Filter bit 0 */ -#define CAN_F17D1R_FD1 ((uint32_t)0x00000002) /*!< Filter bit 1 */ -#define CAN_F17D1R_FD2 ((uint32_t)0x00000004) /*!< Filter bit 2 */ -#define CAN_F17D1R_FD3 ((uint32_t)0x00000008) /*!< Filter bit 3 */ -#define CAN_F17D1R_FD4 ((uint32_t)0x00000010) /*!< Filter bit 4 */ -#define CAN_F17D1R_FD5 ((uint32_t)0x00000020) /*!< Filter bit 5 */ -#define CAN_F17D1R_FD6 ((uint32_t)0x00000040) /*!< Filter bit 6 */ -#define CAN_F17D1R_FD7 ((uint32_t)0x00000080) /*!< Filter bit 7 */ -#define CAN_F17D1R_FD8 ((uint32_t)0x00000100) /*!< Filter bit 8 */ -#define CAN_F17D1R_FD9 ((uint32_t)0x00000200) /*!< Filter bit 9 */ -#define CAN_F17D1R_FD10 ((uint32_t)0x00000400) /*!< Filter bit 10 */ -#define CAN_F17D1R_FD11 ((uint32_t)0x00000800) /*!< Filter bit 11 */ -#define CAN_F17D1R_FD12 ((uint32_t)0x00001000) /*!< Filter bit 12 */ -#define CAN_F17D1R_FD13 ((uint32_t)0x00002000) /*!< Filter bit 13 */ -#define CAN_F17D1R_FD14 ((uint32_t)0x00004000) /*!< Filter bit 14 */ -#define CAN_F17D1R_FD15 ((uint32_t)0x00008000) /*!< Filter bit 15 */ -#define CAN_F17D1R_FD16 ((uint32_t)0x00010000) /*!< Filter bit 16 */ -#define CAN_F17D1R_FD17 ((uint32_t)0x00020000) /*!< Filter bit 17 */ -#define CAN_F17D1R_FD18 ((uint32_t)0x00040000) /*!< Filter bit 18 */ -#define CAN_F17D1R_FD19 ((uint32_t)0x00080000) /*!< Filter bit 19 */ -#define CAN_F17D1R_FD20 ((uint32_t)0x00100000) /*!< Filter bit 20 */ -#define CAN_F17D1R_FD21 ((uint32_t)0x00200000) /*!< Filter bit 21 */ -#define CAN_F17D1R_FD22 ((uint32_t)0x00400000) /*!< Filter bit 22 */ -#define CAN_F17D1R_FD23 ((uint32_t)0x00800000) /*!< Filter bit 23 */ -#define CAN_F17D1R_FD24 ((uint32_t)0x01000000) /*!< Filter bit 24 */ -#define CAN_F17D1R_FD25 ((uint32_t)0x02000000) /*!< Filter bit 25 */ -#define CAN_F17D1R_FD26 ((uint32_t)0x04000000) /*!< Filter bit 26 */ -#define CAN_F17D1R_FD27 ((uint32_t)0x08000000) /*!< Filter bit 27 */ -#define CAN_F17D1R_FD28 ((uint32_t)0x10000000) /*!< Filter bit 28 */ -#define CAN_F17D1R_FD29 ((uint32_t)0x20000000) /*!< Filter bit 29 */ -#define CAN_F17D1R_FD30 ((uint32_t)0x40000000) /*!< Filter bit 30 */ -#define CAN_F17D1R_FD31 ((uint32_t)0x80000000) /*!< Filter bit 31 */ - -/******************* Bit definition for CAN_F18D1R register *******************/ -#define CAN_F18D1R_FD0 ((uint32_t)0x00000001) /*!< Filter bit 0 */ -#define CAN_F18D1R_FD1 ((uint32_t)0x00000002) /*!< Filter bit 1 */ -#define CAN_F18D1R_FD2 ((uint32_t)0x00000004) /*!< Filter bit 2 */ -#define CAN_F18D1R_FD3 ((uint32_t)0x00000008) /*!< Filter bit 3 */ -#define CAN_F18D1R_FD4 ((uint32_t)0x00000010) /*!< Filter bit 4 */ -#define CAN_F18D1R_FD5 ((uint32_t)0x00000020) /*!< Filter bit 5 */ -#define CAN_F18D1R_FD6 ((uint32_t)0x00000040) /*!< Filter bit 6 */ -#define CAN_F18D1R_FD7 ((uint32_t)0x00000080) /*!< Filter bit 7 */ -#define CAN_F18D1R_FD8 ((uint32_t)0x00000100) /*!< Filter bit 8 */ -#define CAN_F18D1R_FD9 ((uint32_t)0x00000200) /*!< Filter bit 9 */ -#define CAN_F18D1R_FD10 ((uint32_t)0x00000400) /*!< Filter bit 10 */ -#define CAN_F18D1R_FD11 ((uint32_t)0x00000800) /*!< Filter bit 11 */ -#define CAN_F18D1R_FD12 ((uint32_t)0x00001000) /*!< Filter bit 12 */ -#define CAN_F18D1R_FD13 ((uint32_t)0x00002000) /*!< Filter bit 13 */ -#define CAN_F18D1R_FD14 ((uint32_t)0x00004000) /*!< Filter bit 14 */ -#define CAN_F18D1R_FD15 ((uint32_t)0x00008000) /*!< Filter bit 15 */ -#define CAN_F18D1R_FD16 ((uint32_t)0x00010000) /*!< Filter bit 16 */ -#define CAN_F18D1R_FD17 ((uint32_t)0x00020000) /*!< Filter bit 17 */ -#define CAN_F18D1R_FD18 ((uint32_t)0x00040000) /*!< Filter bit 18 */ -#define CAN_F18D1R_FD19 ((uint32_t)0x00080000) /*!< Filter bit 19 */ -#define CAN_F18D1R_FD20 ((uint32_t)0x00100000) /*!< Filter bit 20 */ -#define CAN_F18D1R_FD21 ((uint32_t)0x00200000) /*!< Filter bit 21 */ -#define CAN_F18D1R_FD22 ((uint32_t)0x00400000) /*!< Filter bit 22 */ -#define CAN_F18D1R_FD23 ((uint32_t)0x00800000) /*!< Filter bit 23 */ -#define CAN_F18D1R_FD24 ((uint32_t)0x01000000) /*!< Filter bit 24 */ -#define CAN_F18D1R_FD25 ((uint32_t)0x02000000) /*!< Filter bit 25 */ -#define CAN_F18D1R_FD26 ((uint32_t)0x04000000) /*!< Filter bit 26 */ -#define CAN_F18D1R_FD27 ((uint32_t)0x08000000) /*!< Filter bit 27 */ -#define CAN_F18D1R_FD28 ((uint32_t)0x10000000) /*!< Filter bit 28 */ -#define CAN_F18D1R_FD29 ((uint32_t)0x20000000) /*!< Filter bit 29 */ -#define CAN_F18D1R_FD30 ((uint32_t)0x40000000) /*!< Filter bit 30 */ -#define CAN_F18D1R_FD31 ((uint32_t)0x80000000) /*!< Filter bit 31 */ - -/******************* Bit definition for CAN_F19D1R register *******************/ -#define CAN_F19D1R_FD0 ((uint32_t)0x00000001) /*!< Filter bit 0 */ -#define CAN_F19D1R_FD1 ((uint32_t)0x00000002) /*!< Filter bit 1 */ -#define CAN_F19D1R_FD2 ((uint32_t)0x00000004) /*!< Filter bit 2 */ -#define CAN_F19D1R_FD3 ((uint32_t)0x00000008) /*!< Filter bit 3 */ -#define CAN_F19D1R_FD4 ((uint32_t)0x00000010) /*!< Filter bit 4 */ -#define CAN_F19D1R_FD5 ((uint32_t)0x00000020) /*!< Filter bit 5 */ -#define CAN_F19D1R_FD6 ((uint32_t)0x00000040) /*!< Filter bit 6 */ -#define CAN_F19D1R_FD7 ((uint32_t)0x00000080) /*!< Filter bit 7 */ -#define CAN_F19D1R_FD8 ((uint32_t)0x00000100) /*!< Filter bit 8 */ -#define CAN_F19D1R_FD9 ((uint32_t)0x00000200) /*!< Filter bit 9 */ -#define CAN_F19D1R_FD10 ((uint32_t)0x00000400) /*!< Filter bit 10 */ -#define CAN_F19D1R_FD11 ((uint32_t)0x00000800) /*!< Filter bit 11 */ -#define CAN_F19D1R_FD12 ((uint32_t)0x00001000) /*!< Filter bit 12 */ -#define CAN_F19D1R_FD13 ((uint32_t)0x00002000) /*!< Filter bit 13 */ -#define CAN_F19D1R_FD14 ((uint32_t)0x00004000) /*!< Filter bit 14 */ -#define CAN_F19D1R_FD15 ((uint32_t)0x00008000) /*!< Filter bit 15 */ -#define CAN_F19D1R_FD16 ((uint32_t)0x00010000) /*!< Filter bit 16 */ -#define CAN_F19D1R_FD17 ((uint32_t)0x00020000) /*!< Filter bit 17 */ -#define CAN_F19D1R_FD18 ((uint32_t)0x00040000) /*!< Filter bit 18 */ -#define CAN_F19D1R_FD19 ((uint32_t)0x00080000) /*!< Filter bit 19 */ -#define CAN_F19D1R_FD20 ((uint32_t)0x00100000) /*!< Filter bit 20 */ -#define CAN_F19D1R_FD21 ((uint32_t)0x00200000) /*!< Filter bit 21 */ -#define CAN_F19D1R_FD22 ((uint32_t)0x00400000) /*!< Filter bit 22 */ -#define CAN_F19D1R_FD23 ((uint32_t)0x00800000) /*!< Filter bit 23 */ -#define CAN_F19D1R_FD24 ((uint32_t)0x01000000) /*!< Filter bit 24 */ -#define CAN_F19D1R_FD25 ((uint32_t)0x02000000) /*!< Filter bit 25 */ -#define CAN_F19D1R_FD26 ((uint32_t)0x04000000) /*!< Filter bit 26 */ -#define CAN_F19D1R_FD27 ((uint32_t)0x08000000) /*!< Filter bit 27 */ -#define CAN_F19D1R_FD28 ((uint32_t)0x10000000) /*!< Filter bit 28 */ -#define CAN_F19D1R_FD29 ((uint32_t)0x20000000) /*!< Filter bit 29 */ -#define CAN_F19D1R_FD30 ((uint32_t)0x40000000) /*!< Filter bit 30 */ -#define CAN_F19D1R_FD31 ((uint32_t)0x80000000) /*!< Filter bit 31 */ - -/******************* Bit definition for CAN_F20D1R register *******************/ -#define CAN_F20D1R_FD0 ((uint32_t)0x00000001) /*!< Filter bit 0 */ -#define CAN_F20D1R_FD1 ((uint32_t)0x00000002) /*!< Filter bit 1 */ -#define CAN_F20D1R_FD2 ((uint32_t)0x00000004) /*!< Filter bit 2 */ -#define CAN_F20D1R_FD3 ((uint32_t)0x00000008) /*!< Filter bit 3 */ -#define CAN_F20D1R_FD4 ((uint32_t)0x00000010) /*!< Filter bit 4 */ -#define CAN_F20D1R_FD5 ((uint32_t)0x00000020) /*!< Filter bit 5 */ -#define CAN_F20D1R_FD6 ((uint32_t)0x00000040) /*!< Filter bit 6 */ -#define CAN_F20D1R_FD7 ((uint32_t)0x00000080) /*!< Filter bit 7 */ -#define CAN_F20D1R_FD8 ((uint32_t)0x00000100) /*!< Filter bit 8 */ -#define CAN_F20D1R_FD9 ((uint32_t)0x00000200) /*!< Filter bit 9 */ -#define CAN_F20D1R_FD10 ((uint32_t)0x00000400) /*!< Filter bit 10 */ -#define CAN_F20D1R_FD11 ((uint32_t)0x00000800) /*!< Filter bit 11 */ -#define CAN_F20D1R_FD12 ((uint32_t)0x00001000) /*!< Filter bit 12 */ -#define CAN_F20D1R_FD13 ((uint32_t)0x00002000) /*!< Filter bit 13 */ -#define CAN_F20D1R_FD14 ((uint32_t)0x00004000) /*!< Filter bit 14 */ -#define CAN_F20D1R_FD15 ((uint32_t)0x00008000) /*!< Filter bit 15 */ -#define CAN_F20D1R_FD16 ((uint32_t)0x00010000) /*!< Filter bit 16 */ -#define CAN_F20D1R_FD17 ((uint32_t)0x00020000) /*!< Filter bit 17 */ -#define CAN_F20D1R_FD18 ((uint32_t)0x00040000) /*!< Filter bit 18 */ -#define CAN_F20D1R_FD19 ((uint32_t)0x00080000) /*!< Filter bit 19 */ -#define CAN_F20D1R_FD20 ((uint32_t)0x00100000) /*!< Filter bit 20 */ -#define CAN_F20D1R_FD21 ((uint32_t)0x00200000) /*!< Filter bit 21 */ -#define CAN_F20D1R_FD22 ((uint32_t)0x00400000) /*!< Filter bit 22 */ -#define CAN_F20D1R_FD23 ((uint32_t)0x00800000) /*!< Filter bit 23 */ -#define CAN_F20D1R_FD24 ((uint32_t)0x01000000) /*!< Filter bit 24 */ -#define CAN_F20D1R_FD25 ((uint32_t)0x02000000) /*!< Filter bit 25 */ -#define CAN_F20D1R_FD26 ((uint32_t)0x04000000) /*!< Filter bit 26 */ -#define CAN_F20D1R_FD27 ((uint32_t)0x08000000) /*!< Filter bit 27 */ -#define CAN_F20D1R_FD28 ((uint32_t)0x10000000) /*!< Filter bit 28 */ -#define CAN_F20D1R_FD29 ((uint32_t)0x20000000) /*!< Filter bit 29 */ -#define CAN_F20D1R_FD30 ((uint32_t)0x40000000) /*!< Filter bit 30 */ -#define CAN_F20D1R_FD31 ((uint32_t)0x80000000) /*!< Filter bit 31 */ - -/******************* Bit definition for CAN_F21D1R register *******************/ -#define CAN_F21D1R_FD0 ((uint32_t)0x00000001) /*!< Filter bit 0 */ -#define CAN_F21D1R_FD1 ((uint32_t)0x00000002) /*!< Filter bit 1 */ -#define CAN_F21D1R_FD2 ((uint32_t)0x00000004) /*!< Filter bit 2 */ -#define CAN_F21D1R_FD3 ((uint32_t)0x00000008) /*!< Filter bit 3 */ -#define CAN_F21D1R_FD4 ((uint32_t)0x00000010) /*!< Filter bit 4 */ -#define CAN_F21D1R_FD5 ((uint32_t)0x00000020) /*!< Filter bit 5 */ -#define CAN_F21D1R_FD6 ((uint32_t)0x00000040) /*!< Filter bit 6 */ -#define CAN_F21D1R_FD7 ((uint32_t)0x00000080) /*!< Filter bit 7 */ -#define CAN_F21D1R_FD8 ((uint32_t)0x00000100) /*!< Filter bit 8 */ -#define CAN_F21D1R_FD9 ((uint32_t)0x00000200) /*!< Filter bit 9 */ -#define CAN_F21D1R_FD10 ((uint32_t)0x00000400) /*!< Filter bit 10 */ -#define CAN_F21D1R_FD11 ((uint32_t)0x00000800) /*!< Filter bit 11 */ -#define CAN_F21D1R_FD12 ((uint32_t)0x00001000) /*!< Filter bit 12 */ -#define CAN_F21D1R_FD13 ((uint32_t)0x00002000) /*!< Filter bit 13 */ -#define CAN_F21D1R_FD14 ((uint32_t)0x00004000) /*!< Filter bit 14 */ -#define CAN_F21D1R_FD15 ((uint32_t)0x00008000) /*!< Filter bit 15 */ -#define CAN_F21D1R_FD16 ((uint32_t)0x00010000) /*!< Filter bit 16 */ -#define CAN_F21D1R_FD17 ((uint32_t)0x00020000) /*!< Filter bit 17 */ -#define CAN_F21D1R_FD18 ((uint32_t)0x00040000) /*!< Filter bit 18 */ -#define CAN_F21D1R_FD19 ((uint32_t)0x00080000) /*!< Filter bit 19 */ -#define CAN_F21D1R_FD20 ((uint32_t)0x00100000) /*!< Filter bit 20 */ -#define CAN_F21D1R_FD21 ((uint32_t)0x00200000) /*!< Filter bit 21 */ -#define CAN_F21D1R_FD22 ((uint32_t)0x00400000) /*!< Filter bit 22 */ -#define CAN_F21D1R_FD23 ((uint32_t)0x00800000) /*!< Filter bit 23 */ -#define CAN_F21D1R_FD24 ((uint32_t)0x01000000) /*!< Filter bit 24 */ -#define CAN_F21D1R_FD25 ((uint32_t)0x02000000) /*!< Filter bit 25 */ -#define CAN_F21D1R_FD26 ((uint32_t)0x04000000) /*!< Filter bit 26 */ -#define CAN_F21D1R_FD27 ((uint32_t)0x08000000) /*!< Filter bit 27 */ -#define CAN_F21D1R_FD28 ((uint32_t)0x10000000) /*!< Filter bit 28 */ -#define CAN_F21D1R_FD29 ((uint32_t)0x20000000) /*!< Filter bit 29 */ -#define CAN_F21D1R_FD30 ((uint32_t)0x40000000) /*!< Filter bit 30 */ -#define CAN_F21D1R_FD31 ((uint32_t)0x80000000) /*!< Filter bit 31 */ - -/******************* Bit definition for CAN_F22D1R register *******************/ -#define CAN_F22D1R_FD0 ((uint32_t)0x00000001) /*!< Filter bit 0 */ -#define CAN_F22D1R_FD1 ((uint32_t)0x00000002) /*!< Filter bit 1 */ -#define CAN_F22D1R_FD2 ((uint32_t)0x00000004) /*!< Filter bit 2 */ -#define CAN_F22D1R_FD3 ((uint32_t)0x00000008) /*!< Filter bit 3 */ -#define CAN_F22D1R_FD4 ((uint32_t)0x00000010) /*!< Filter bit 4 */ -#define CAN_F22D1R_FD5 ((uint32_t)0x00000020) /*!< Filter bit 5 */ -#define CAN_F22D1R_FD6 ((uint32_t)0x00000040) /*!< Filter bit 6 */ -#define CAN_F22D1R_FD7 ((uint32_t)0x00000080) /*!< Filter bit 7 */ -#define CAN_F22D1R_FD8 ((uint32_t)0x00000100) /*!< Filter bit 8 */ -#define CAN_F22D1R_FD9 ((uint32_t)0x00000200) /*!< Filter bit 9 */ -#define CAN_F22D1R_FD10 ((uint32_t)0x00000400) /*!< Filter bit 10 */ -#define CAN_F22D1R_FD11 ((uint32_t)0x00000800) /*!< Filter bit 11 */ -#define CAN_F22D1R_FD12 ((uint32_t)0x00001000) /*!< Filter bit 12 */ -#define CAN_F22D1R_FD13 ((uint32_t)0x00002000) /*!< Filter bit 13 */ -#define CAN_F22D1R_FD14 ((uint32_t)0x00004000) /*!< Filter bit 14 */ -#define CAN_F22D1R_FD15 ((uint32_t)0x00008000) /*!< Filter bit 15 */ -#define CAN_F22D1R_FD16 ((uint32_t)0x00010000) /*!< Filter bit 16 */ -#define CAN_F22D1R_FD17 ((uint32_t)0x00020000) /*!< Filter bit 17 */ -#define CAN_F22D1R_FD18 ((uint32_t)0x00040000) /*!< Filter bit 18 */ -#define CAN_F22D1R_FD19 ((uint32_t)0x00080000) /*!< Filter bit 19 */ -#define CAN_F22D1R_FD20 ((uint32_t)0x00100000) /*!< Filter bit 20 */ -#define CAN_F22D1R_FD21 ((uint32_t)0x00200000) /*!< Filter bit 21 */ -#define CAN_F22D1R_FD22 ((uint32_t)0x00400000) /*!< Filter bit 22 */ -#define CAN_F22D1R_FD23 ((uint32_t)0x00800000) /*!< Filter bit 23 */ -#define CAN_F22D1R_FD24 ((uint32_t)0x01000000) /*!< Filter bit 24 */ -#define CAN_F22D1R_FD25 ((uint32_t)0x02000000) /*!< Filter bit 25 */ -#define CAN_F22D1R_FD26 ((uint32_t)0x04000000) /*!< Filter bit 26 */ -#define CAN_F22D1R_FD27 ((uint32_t)0x08000000) /*!< Filter bit 27 */ -#define CAN_F22D1R_FD28 ((uint32_t)0x10000000) /*!< Filter bit 28 */ -#define CAN_F22D1R_FD29 ((uint32_t)0x20000000) /*!< Filter bit 29 */ -#define CAN_F22D1R_FD30 ((uint32_t)0x40000000) /*!< Filter bit 30 */ -#define CAN_F22D1R_FD31 ((uint32_t)0x80000000) /*!< Filter bit 31 */ - -/******************* Bit definition for CAN_F23D1R register *******************/ -#define CAN_F23D1R_FD0 ((uint32_t)0x00000001) /*!< Filter bit 0 */ -#define CAN_F23D1R_FD1 ((uint32_t)0x00000002) /*!< Filter bit 1 */ -#define CAN_F23D1R_FD2 ((uint32_t)0x00000004) /*!< Filter bit 2 */ -#define CAN_F23D1R_FD3 ((uint32_t)0x00000008) /*!< Filter bit 3 */ -#define CAN_F23D1R_FD4 ((uint32_t)0x00000010) /*!< Filter bit 4 */ -#define CAN_F23D1R_FD5 ((uint32_t)0x00000020) /*!< Filter bit 5 */ -#define CAN_F23D1R_FD6 ((uint32_t)0x00000040) /*!< Filter bit 6 */ -#define CAN_F23D1R_FD7 ((uint32_t)0x00000080) /*!< Filter bit 7 */ -#define CAN_F23D1R_FD8 ((uint32_t)0x00000100) /*!< Filter bit 8 */ -#define CAN_F23D1R_FD9 ((uint32_t)0x00000200) /*!< Filter bit 9 */ -#define CAN_F23D1R_FD10 ((uint32_t)0x00000400) /*!< Filter bit 10 */ -#define CAN_F23D1R_FD11 ((uint32_t)0x00000800) /*!< Filter bit 11 */ -#define CAN_F23D1R_FD12 ((uint32_t)0x00001000) /*!< Filter bit 12 */ -#define CAN_F23D1R_FD13 ((uint32_t)0x00002000) /*!< Filter bit 13 */ -#define CAN_F23D1R_FD14 ((uint32_t)0x00004000) /*!< Filter bit 14 */ -#define CAN_F23D1R_FD15 ((uint32_t)0x00008000) /*!< Filter bit 15 */ -#define CAN_F23D1R_FD16 ((uint32_t)0x00010000) /*!< Filter bit 16 */ -#define CAN_F23D1R_FD17 ((uint32_t)0x00020000) /*!< Filter bit 17 */ -#define CAN_F23D1R_FD18 ((uint32_t)0x00040000) /*!< Filter bit 18 */ -#define CAN_F23D1R_FD19 ((uint32_t)0x00080000) /*!< Filter bit 19 */ -#define CAN_F23D1R_FD20 ((uint32_t)0x00100000) /*!< Filter bit 20 */ -#define CAN_F23D1R_FD21 ((uint32_t)0x00200000) /*!< Filter bit 21 */ -#define CAN_F23D1R_FD22 ((uint32_t)0x00400000) /*!< Filter bit 22 */ -#define CAN_F23D1R_FD23 ((uint32_t)0x00800000) /*!< Filter bit 23 */ -#define CAN_F23D1R_FD24 ((uint32_t)0x01000000) /*!< Filter bit 24 */ -#define CAN_F23D1R_FD25 ((uint32_t)0x02000000) /*!< Filter bit 25 */ -#define CAN_F23D1R_FD26 ((uint32_t)0x04000000) /*!< Filter bit 26 */ -#define CAN_F23D1R_FD27 ((uint32_t)0x08000000) /*!< Filter bit 27 */ -#define CAN_F23D1R_FD28 ((uint32_t)0x10000000) /*!< Filter bit 28 */ -#define CAN_F23D1R_FD29 ((uint32_t)0x20000000) /*!< Filter bit 29 */ -#define CAN_F23D1R_FD30 ((uint32_t)0x40000000) /*!< Filter bit 30 */ -#define CAN_F23D1R_FD31 ((uint32_t)0x80000000) /*!< Filter bit 31 */ - -/******************* Bit definition for CAN_F24D1R register *******************/ -#define CAN_F24D1R_FD0 ((uint32_t)0x00000001) /*!< Filter bit 0 */ -#define CAN_F24D1R_FD1 ((uint32_t)0x00000002) /*!< Filter bit 1 */ -#define CAN_F24D1R_FD2 ((uint32_t)0x00000004) /*!< Filter bit 2 */ -#define CAN_F24D1R_FD3 ((uint32_t)0x00000008) /*!< Filter bit 3 */ -#define CAN_F24D1R_FD4 ((uint32_t)0x00000010) /*!< Filter bit 4 */ -#define CAN_F24D1R_FD5 ((uint32_t)0x00000020) /*!< Filter bit 5 */ -#define CAN_F24D1R_FD6 ((uint32_t)0x00000040) /*!< Filter bit 6 */ -#define CAN_F24D1R_FD7 ((uint32_t)0x00000080) /*!< Filter bit 7 */ -#define CAN_F24D1R_FD8 ((uint32_t)0x00000100) /*!< Filter bit 8 */ -#define CAN_F24D1R_FD9 ((uint32_t)0x00000200) /*!< Filter bit 9 */ -#define CAN_F24D1R_FD10 ((uint32_t)0x00000400) /*!< Filter bit 10 */ -#define CAN_F24D1R_FD11 ((uint32_t)0x00000800) /*!< Filter bit 11 */ -#define CAN_F24D1R_FD12 ((uint32_t)0x00001000) /*!< Filter bit 12 */ -#define CAN_F24D1R_FD13 ((uint32_t)0x00002000) /*!< Filter bit 13 */ -#define CAN_F24D1R_FD14 ((uint32_t)0x00004000) /*!< Filter bit 14 */ -#define CAN_F24D1R_FD15 ((uint32_t)0x00008000) /*!< Filter bit 15 */ -#define CAN_F24D1R_FD16 ((uint32_t)0x00010000) /*!< Filter bit 16 */ -#define CAN_F24D1R_FD17 ((uint32_t)0x00020000) /*!< Filter bit 17 */ -#define CAN_F24D1R_FD18 ((uint32_t)0x00040000) /*!< Filter bit 18 */ -#define CAN_F24D1R_FD19 ((uint32_t)0x00080000) /*!< Filter bit 19 */ -#define CAN_F24D1R_FD20 ((uint32_t)0x00100000) /*!< Filter bit 20 */ -#define CAN_F24D1R_FD21 ((uint32_t)0x00200000) /*!< Filter bit 21 */ -#define CAN_F24D1R_FD22 ((uint32_t)0x00400000) /*!< Filter bit 22 */ -#define CAN_F24D1R_FD23 ((uint32_t)0x00800000) /*!< Filter bit 23 */ -#define CAN_F24D1R_FD24 ((uint32_t)0x01000000) /*!< Filter bit 24 */ -#define CAN_F24D1R_FD25 ((uint32_t)0x02000000) /*!< Filter bit 25 */ -#define CAN_F24D1R_FD26 ((uint32_t)0x04000000) /*!< Filter bit 26 */ -#define CAN_F24D1R_FD27 ((uint32_t)0x08000000) /*!< Filter bit 27 */ -#define CAN_F24D1R_FD28 ((uint32_t)0x10000000) /*!< Filter bit 28 */ -#define CAN_F24D1R_FD29 ((uint32_t)0x20000000) /*!< Filter bit 29 */ -#define CAN_F24D1R_FD30 ((uint32_t)0x40000000) /*!< Filter bit 30 */ -#define CAN_F24D1R_FD31 ((uint32_t)0x80000000) /*!< Filter bit 31 */ - -/******************* Bit definition for CAN_F25D1R register *******************/ -#define CAN_F25D1R_FD0 ((uint32_t)0x00000001) /*!< Filter bit 0 */ -#define CAN_F25D1R_FD1 ((uint32_t)0x00000002) /*!< Filter bit 1 */ -#define CAN_F25D1R_FD2 ((uint32_t)0x00000004) /*!< Filter bit 2 */ -#define CAN_F25D1R_FD3 ((uint32_t)0x00000008) /*!< Filter bit 3 */ -#define CAN_F25D1R_FD4 ((uint32_t)0x00000010) /*!< Filter bit 4 */ -#define CAN_F25D1R_FD5 ((uint32_t)0x00000020) /*!< Filter bit 5 */ -#define CAN_F25D1R_FD6 ((uint32_t)0x00000040) /*!< Filter bit 6 */ -#define CAN_F25D1R_FD7 ((uint32_t)0x00000080) /*!< Filter bit 7 */ -#define CAN_F25D1R_FD8 ((uint32_t)0x00000100) /*!< Filter bit 8 */ -#define CAN_F25D1R_FD9 ((uint32_t)0x00000200) /*!< Filter bit 9 */ -#define CAN_F25D1R_FD10 ((uint32_t)0x00000400) /*!< Filter bit 10 */ -#define CAN_F25D1R_FD11 ((uint32_t)0x00000800) /*!< Filter bit 11 */ -#define CAN_F25D1R_FD12 ((uint32_t)0x00001000) /*!< Filter bit 12 */ -#define CAN_F25D1R_FD13 ((uint32_t)0x00002000) /*!< Filter bit 13 */ -#define CAN_F25D1R_FD14 ((uint32_t)0x00004000) /*!< Filter bit 14 */ -#define CAN_F25D1R_FD15 ((uint32_t)0x00008000) /*!< Filter bit 15 */ -#define CAN_F25D1R_FD16 ((uint32_t)0x00010000) /*!< Filter bit 16 */ -#define CAN_F25D1R_FD17 ((uint32_t)0x00020000) /*!< Filter bit 17 */ -#define CAN_F25D1R_FD18 ((uint32_t)0x00040000) /*!< Filter bit 18 */ -#define CAN_F25D1R_FD19 ((uint32_t)0x00080000) /*!< Filter bit 19 */ -#define CAN_F25D1R_FD20 ((uint32_t)0x00100000) /*!< Filter bit 20 */ -#define CAN_F25D1R_FD21 ((uint32_t)0x00200000) /*!< Filter bit 21 */ -#define CAN_F25D1R_FD22 ((uint32_t)0x00400000) /*!< Filter bit 22 */ -#define CAN_F25D1R_FD23 ((uint32_t)0x00800000) /*!< Filter bit 23 */ -#define CAN_F25D1R_FD24 ((uint32_t)0x01000000) /*!< Filter bit 24 */ -#define CAN_F25D1R_FD25 ((uint32_t)0x02000000) /*!< Filter bit 25 */ -#define CAN_F25D1R_FD26 ((uint32_t)0x04000000) /*!< Filter bit 26 */ -#define CAN_F25D1R_FD27 ((uint32_t)0x08000000) /*!< Filter bit 27 */ -#define CAN_F25D1R_FD28 ((uint32_t)0x10000000) /*!< Filter bit 28 */ -#define CAN_F25D1R_FD29 ((uint32_t)0x20000000) /*!< Filter bit 29 */ -#define CAN_F25D1R_FD30 ((uint32_t)0x40000000) /*!< Filter bit 30 */ -#define CAN_F25D1R_FD31 ((uint32_t)0x80000000) /*!< Filter bit 31 */ - -/******************* Bit definition for CAN_F26D1R register *******************/ -#define CAN_F26D1R_FD0 ((uint32_t)0x00000001) /*!< Filter bit 0 */ -#define CAN_F26D1R_FD1 ((uint32_t)0x00000002) /*!< Filter bit 1 */ -#define CAN_F26D1R_FD2 ((uint32_t)0x00000004) /*!< Filter bit 2 */ -#define CAN_F26D1R_FD3 ((uint32_t)0x00000008) /*!< Filter bit 3 */ -#define CAN_F26D1R_FD4 ((uint32_t)0x00000010) /*!< Filter bit 4 */ -#define CAN_F26D1R_FD5 ((uint32_t)0x00000020) /*!< Filter bit 5 */ -#define CAN_F26D1R_FD6 ((uint32_t)0x00000040) /*!< Filter bit 6 */ -#define CAN_F26D1R_FD7 ((uint32_t)0x00000080) /*!< Filter bit 7 */ -#define CAN_F26D1R_FD8 ((uint32_t)0x00000100) /*!< Filter bit 8 */ -#define CAN_F26D1R_FD9 ((uint32_t)0x00000200) /*!< Filter bit 9 */ -#define CAN_F26D1R_FD10 ((uint32_t)0x00000400) /*!< Filter bit 10 */ -#define CAN_F26D1R_FD11 ((uint32_t)0x00000800) /*!< Filter bit 11 */ -#define CAN_F26D1R_FD12 ((uint32_t)0x00001000) /*!< Filter bit 12 */ -#define CAN_F26D1R_FD13 ((uint32_t)0x00002000) /*!< Filter bit 13 */ -#define CAN_F26D1R_FD14 ((uint32_t)0x00004000) /*!< Filter bit 14 */ -#define CAN_F26D1R_FD15 ((uint32_t)0x00008000) /*!< Filter bit 15 */ -#define CAN_F26D1R_FD16 ((uint32_t)0x00010000) /*!< Filter bit 16 */ -#define CAN_F26D1R_FD17 ((uint32_t)0x00020000) /*!< Filter bit 17 */ -#define CAN_F26D1R_FD18 ((uint32_t)0x00040000) /*!< Filter bit 18 */ -#define CAN_F26D1R_FD19 ((uint32_t)0x00080000) /*!< Filter bit 19 */ -#define CAN_F26D1R_FD20 ((uint32_t)0x00100000) /*!< Filter bit 20 */ -#define CAN_F26D1R_FD21 ((uint32_t)0x00200000) /*!< Filter bit 21 */ -#define CAN_F26D1R_FD22 ((uint32_t)0x00400000) /*!< Filter bit 22 */ -#define CAN_F26D1R_FD23 ((uint32_t)0x00800000) /*!< Filter bit 23 */ -#define CAN_F26D1R_FD24 ((uint32_t)0x01000000) /*!< Filter bit 24 */ -#define CAN_F26D1R_FD25 ((uint32_t)0x02000000) /*!< Filter bit 25 */ -#define CAN_F26D1R_FD26 ((uint32_t)0x04000000) /*!< Filter bit 26 */ -#define CAN_F26D1R_FD27 ((uint32_t)0x08000000) /*!< Filter bit 27 */ -#define CAN_F26D1R_FD28 ((uint32_t)0x10000000) /*!< Filter bit 28 */ -#define CAN_F26D1R_FD29 ((uint32_t)0x20000000) /*!< Filter bit 29 */ -#define CAN_F26D1R_FD30 ((uint32_t)0x40000000) /*!< Filter bit 30 */ -#define CAN_F26D1R_FD31 ((uint32_t)0x80000000) /*!< Filter bit 31 */ - -/******************* Bit definition for CAN_F27D1R register *******************/ -#define CAN_F27D1R_FD0 ((uint32_t)0x00000001) /*!< Filter bit 0 */ -#define CAN_F27D1R_FD1 ((uint32_t)0x00000002) /*!< Filter bit 1 */ -#define CAN_F27D1R_FD2 ((uint32_t)0x00000004) /*!< Filter bit 2 */ -#define CAN_F27D1R_FD3 ((uint32_t)0x00000008) /*!< Filter bit 3 */ -#define CAN_F27D1R_FD4 ((uint32_t)0x00000010) /*!< Filter bit 4 */ -#define CAN_F27D1R_FD5 ((uint32_t)0x00000020) /*!< Filter bit 5 */ -#define CAN_F27D1R_FD6 ((uint32_t)0x00000040) /*!< Filter bit 6 */ -#define CAN_F27D1R_FD7 ((uint32_t)0x00000080) /*!< Filter bit 7 */ -#define CAN_F27D1R_FD8 ((uint32_t)0x00000100) /*!< Filter bit 8 */ -#define CAN_F27D1R_FD9 ((uint32_t)0x00000200) /*!< Filter bit 9 */ -#define CAN_F27D1R_FD10 ((uint32_t)0x00000400) /*!< Filter bit 10 */ -#define CAN_F27D1R_FD11 ((uint32_t)0x00000800) /*!< Filter bit 11 */ -#define CAN_F27D1R_FD12 ((uint32_t)0x00001000) /*!< Filter bit 12 */ -#define CAN_F27D1R_FD13 ((uint32_t)0x00002000) /*!< Filter bit 13 */ -#define CAN_F27D1R_FD14 ((uint32_t)0x00004000) /*!< Filter bit 14 */ -#define CAN_F27D1R_FD15 ((uint32_t)0x00008000) /*!< Filter bit 15 */ -#define CAN_F27D1R_FD16 ((uint32_t)0x00010000) /*!< Filter bit 16 */ -#define CAN_F27D1R_FD17 ((uint32_t)0x00020000) /*!< Filter bit 17 */ -#define CAN_F27D1R_FD18 ((uint32_t)0x00040000) /*!< Filter bit 18 */ -#define CAN_F27D1R_FD19 ((uint32_t)0x00080000) /*!< Filter bit 19 */ -#define CAN_F27D1R_FD20 ((uint32_t)0x00100000) /*!< Filter bit 20 */ -#define CAN_F27D1R_FD21 ((uint32_t)0x00200000) /*!< Filter bit 21 */ -#define CAN_F27D1R_FD22 ((uint32_t)0x00400000) /*!< Filter bit 22 */ -#define CAN_F27D1R_FD23 ((uint32_t)0x00800000) /*!< Filter bit 23 */ -#define CAN_F27D1R_FD24 ((uint32_t)0x01000000) /*!< Filter bit 24 */ -#define CAN_F27D1R_FD25 ((uint32_t)0x02000000) /*!< Filter bit 25 */ -#define CAN_F27D1R_FD26 ((uint32_t)0x04000000) /*!< Filter bit 26 */ -#define CAN_F27D1R_FD27 ((uint32_t)0x08000000) /*!< Filter bit 27 */ -#define CAN_F27D1R_FD28 ((uint32_t)0x10000000) /*!< Filter bit 28 */ -#define CAN_F27D1R_FD29 ((uint32_t)0x20000000) /*!< Filter bit 29 */ -#define CAN_F27D1R_FD30 ((uint32_t)0x40000000) /*!< Filter bit 30 */ -#define CAN_F27D1R_FD31 ((uint32_t)0x80000000) /*!< Filter bit 31 */ - -/******************************************************************************/ -/* */ -/* CRC calculation unit (CRC) */ -/* */ -/******************************************************************************/ -/******************* Bit definition for CRC_DTR register *********************/ -#define CRC_DTR_DATA ((uint32_t)0xFFFFFFFF) /*!< Data register bits */ - -/******************* Bit definition for CRC_FDTR register ********************/ -#define CRC_FDTR_FDR ((uint8_t)0xFF) /*!< General-purpose 8-bit data register bits */ - -/******************** Bit definition for CRC_CTLR register ********************/ -#define CRC_CTLR_RESET ((uint32_t)0x00000001) /*!< RESET the CRC computation unit bit */ - -/******************************************************************************/ -/* */ -/* Digital to Analog Converter (DAC) */ -/* */ -/******************************************************************************/ - -/******************** Bit definition for DAC_CTLR register ********************/ -#define DAC_CTLR_DEN1 ((uint32_t)0x00000001) /*!< DAC channel1 enable */ -#define DAC_CTLR_DBOFF1 ((uint32_t)0x00000002) /*!< DAC channel1 output buffer disable */ -#define DAC_CTLR_DTEN1 ((uint32_t)0x00000004) /*!< DAC channel1 Trigger enable */ - -#define DAC_CTLR_DTSEL1 ((uint32_t)0x00000038) /*!< TSEL1[2:0] (DAC channel1 Trigger selection) */ -#define DAC_CTLR_DTSEL1_0 ((uint32_t)0x00000008) /*!< Bit 0 */ -#define DAC_CTLR_DTSEL1_1 ((uint32_t)0x00000010) /*!< Bit 1 */ -#define DAC_CTLR_DTSEL1_2 ((uint32_t)0x00000020) /*!< Bit 2 */ - -#define DAC_CTLR_DWAVE1 ((uint32_t)0x000000C0) /*!< WAVE1[1:0] (DAC channel1 noise/triangle wave generation enable) */ -#define DAC_CTLR_DWAVE1_0 ((uint32_t)0x00000040) /*!< Bit 0 */ -#define DAC_CTLR_DWAVE1_1 ((uint32_t)0x00000080) /*!< Bit 1 */ - -#define DAC_CTLR_DMAMP1 ((uint32_t)0x00000F00) /*!< MAMP1[3:0] (DAC channel1 Mask/Amplitude selector) */ -#define DAC_CTLR_DMAMP1_0 ((uint32_t)0x00000100) /*!< Bit 0 */ -#define DAC_CTLR_DMAMP1_1 ((uint32_t)0x00000200) /*!< Bit 1 */ -#define DAC_CTLR_DMAMP1_2 ((uint32_t)0x00000400) /*!< Bit 2 */ -#define DAC_CTLR_DMAMP1_3 ((uint32_t)0x00000800) /*!< Bit 3 */ - -#define DAC_CTLR_DDMAEN1 ((uint32_t)0x00001000) /*!< DAC channel1 DMA enable */ -#define DAC_CTLR_DEN2 ((uint32_t)0x00010000) /*!< DAC channel2 enable */ -#define DAC_CTLR_DBOFF2 ((uint32_t)0x00020000) /*!< DAC channel2 output buffer disable */ -#define DAC_CTLR_DTEN2 ((uint32_t)0x00040000) /*!< DAC channel2 Trigger enable */ - -#define DAC_CTLR_DTSEL2 ((uint32_t)0x00380000) /*!< TSEL2[2:0] (DAC channel2 Trigger selection) */ -#define DAC_CTLR_DTSEL2_0 ((uint32_t)0x00080000) /*!< Bit 0 */ -#define DAC_CTLR_DTSEL2_1 ((uint32_t)0x00100000) /*!< Bit 1 */ -#define DAC_CTLR_DTSEL2_2 ((uint32_t)0x00200000) /*!< Bit 2 */ - -#define DAC_CTLR_DWAVE2 ((uint32_t)0x00C00000) /*!< WAVE2[1:0] (DAC channel2 noise/triangle wave generation enable) */ -#define DAC_CTLR_DWAVE2_0 ((uint32_t)0x00400000) /*!< Bit 0 */ -#define DAC_CTLR_DWAVE2_1 ((uint32_t)0x00800000) /*!< Bit 1 */ - -#define DAC_CTLR_DMAMP2 ((uint32_t)0x0F000000) /*!< MAMP2[3:0] (DAC channel2 Mask/Amplitude selector) */ -#define DAC_CTLR_DMAMP2_0 ((uint32_t)0x01000000) /*!< Bit 0 */ -#define DAC_CTLR_DMAMP2_1 ((uint32_t)0x02000000) /*!< Bit 1 */ -#define DAC_CTLR_DMAMP2_2 ((uint32_t)0x04000000) /*!< Bit 2 */ -#define DAC_CTLR_DMAMP2_3 ((uint32_t)0x08000000) /*!< Bit 3 */ - -#define DAC_CTLR_DDMAEN2 ((uint32_t)0x10000000) /*!< DAC channel2 DMA enabled */ - - -/***************** Bit definition for DAC_SWTR register ******************/ -#define DAC_SWTR_SWTR1 ((uint8_t)0x01) /*!< DAC channel1 software trigger */ -#define DAC_SWTR_SWTR2 ((uint8_t)0x02) /*!< DAC channel2 software trigger */ - -/***************** Bit definition for DAC_C1R12DHR register ******************/ -#define DAC_C1R12DHR_DAC_C1DHR ((uint16_t)0x0FFF) /*!< DAC channel1 12-bit Right aligned data */ - -/***************** Bit definition for DAC_C1L12DHR register ******************/ -#define DAC_C1L12DHR_DAC_C1DHR ((uint16_t)0xFFF0) /*!< DAC channel1 12-bit Left aligned data */ - -/****************** Bit definition for DAC_C1R8DHR register ******************/ -#define DAC_C1R8DHR_DAC_C1DHR ((uint8_t)0xFF) /*!< DAC channel1 8-bit Right aligned data */ - - -/***************** Bit definition for DAC_C2R12DHR register ******************/ -#define DAC_C2R12DHR_DAC_C2DHR ((uint16_t)0x0FFF) /*!< DAC channel2 12-bit Right aligned data */ - -/***************** Bit definition for DAC_C2L12DHR register ******************/ -#define DAC_C2L12DHR_DAC_C2DHR ((uint16_t)0xFFF0) /*!< DAC channel2 12-bit Left aligned data */ - -/****************** Bit definition for DAC_C2R8DHR register ******************/ -#define DAC_C2R8DHR_DAC_C2DHR ((uint8_t)0xFF) /*!< DAC channel2 8-bit Right aligned data */ - - -/***************** Bit definition for DAC_DCR12DHR register ******************/ -#define DAC_DCR12DHR_DAC_C1DHR ((uint32_t)0x00000FFF) /*!< DAC channel1 12-bit Right aligned data */ -#define DAC_DCR12DHR_DAC_C2DHR ((uint32_t)0x0FFF0000) /*!< DAC channel2 12-bit Right aligned data */ - - -/***************** Bit definition for DAC_DCL12DHR register ******************/ -#define DAC_DCL12DHR_DAC_C1DHR ((uint32_t)0x0000FFF0) /*!< DAC channel1 12-bit Left aligned data */ -#define DAC_DCL12DHR_DAC_C2DHR ((uint32_t)0xFFF00000) /*!< DAC channel2 12-bit Left aligned data */ - -/****************** Bit definition for DAC_DCR8DHR register ******************/ -#define DAC_DCR8DHR_DAC_C1DHR ((uint16_t)0x00FF) /*!< DAC channel1 8-bit Right aligned data */ -#define DAC_DCR8DHR_DAC_C2DHR ((uint16_t)0xFF00) /*!< DAC channel2 8-bit Right aligned data */ - -/******************* Bit definition for DAC_C1ODR register *******************/ -#define DAC_C1ODR_DAC_ODR1 ((uint16_t)0x0FFF) /*!< DAC channel1 data output */ - -/******************* Bit definition for DAC_C2ODR register *******************/ -#define DAC_C2ODR_DAC_ODR2 ((uint16_t)0x0FFF) /*!< DAC channel2 data output */ - - -/******************************************************************************/ -/* */ -/* Debug MCU (MCUDBG) */ -/* */ -/******************************************************************************/ - -/**************** Bit definition for MCUDBG_IDR register *****************/ -#define MCUDBG_IDR_ID_CODE ((uint32_t)0xFFFFFFFF) /*!< Device Identifier */ - -/****************** Bit definition for MCUDBG_CTLR register *******************/ -#define MCUDBG_CTLR_SLEEP_HOLD ((uint32_t)0x00000001) /*!< Sleep mode hold register */ -#define MCUDBG_CTLR_DEEPSLEEP_HOLD ((uint32_t)0x00000002) /*!< Deep-sleep mode hold register */ -#define MCUDBG_CTLR_STDBY_HOLD ((uint32_t)0x00000004) /*!< Standby mode hold register */ -#define MCUDBG_CTLR_TRACE_IOEN ((uint32_t)0x00000020) /*!< Trace Pin Allocation Enable */ - -#define MCUDBG_CTLR_TRACE_MODE ((uint32_t)0x00000C00) /*!< TRACE_MODE[1:0] bits(Trace Pin Allocation Mode) */ -#define MCUDBG_CTLR_TRACE_MODE_0 ((uint32_t)0x00000400) /*!< Bit 0 */ -#define MCUDBG_CTLR_TRACE_MODE_1 ((uint32_t)0x00000800) /*!< Bit 1 */ - -#define MCUDBG_CTLR_IWDG_HOLD ((uint32_t)0x00000100) /*!< IWDG hold register */ -#define MCUDBG_CTLR_WWDG_HOLD ((uint32_t)0x00000200) /*!< WWDG hold register */ -#define MCUDBG_CTLR_TM1_HOLD ((uint32_t)0x00000400) /*!< Timer 1 hold register */ -#define MCUDBG_CTLR_TM2_HOLD ((uint32_t)0x00000800) /*!< Timer 2 hold register */ -#define MCUDBG_CTLR_TM3_HOLD ((uint32_t)0x00001000) /*!< Timer 3 hold register */ -#define MCUDBG_CTLR_TM4_HOLD ((uint32_t)0x00002000) /*!< Timer 4 hold register */ -#define MCUDBG_CTLR_CAN1_HOLD ((uint32_t)0x00004000) /*!< CAN 1 hold register */ -#define MCUDBG_CTLR_I2C1_HOLD ((uint32_t)0x00008000) /*!< I2C1 hold register */ -#define MCUDBG_CTLR_I2C2_HOLD ((uint32_t)0x00010000) /*!< I2C2 hold register */ -#define MCUDBG_CTLR_TM5_HOLD ((uint32_t)0x00020000) /*!< Timer 5 hold register */ -#define MCUDBG_CTLR_TM6_HOLD ((uint32_t)0x00040000) /*!< Timer 6 hold register */ -#define MCUDBG_CTLR_TM7_HOLD ((uint32_t)0x00080000) /*!< Timer 7 hold register */ -#define MCUDBG_CTLR_TM8_HOLD ((uint32_t)0x00100000) /*!< Timer 8 hold register */ -#define MCUDBG_CTLR_CAN2_HOLD ((uint32_t)0x00200000) /*!< CAN 2 hold register */ -#define MCUDBG_CTLR_TM12_HOLD ((uint32_t)0x02000000) /*!< Timer 12 hold register */ -#define MCUDBG_CTLR_TM13_HOLD ((uint32_t)0x04000000) /*!< Timer 13 hold register */ -#define MCUDBG_CTLR_TM14_HOLD ((uint32_t)0x08000000) /*!< Timer 14 hold register */ -#define MCUDBG_CTLR_TM9_HOLD ((uint32_t)0x10000000) /*!< Timer 9 hold register */ -#define MCUDBG_CTLR_TM10_HOLD ((uint32_t)0x20000000) /*!< Timer 10 hold register */ -#define MCUDBG_CTLR_TM11_HOLD ((uint32_t)0x40000000) /*!< Timer 11 hold register */ - -/******************************************************************************/ -/* */ -/* DMA Controller (DMA) */ -/* */ -/******************************************************************************/ - -/******************* Bit definition for DMA_IFR register ********************/ -#define DMA_IFR_GIF1 ((uint32_t)0x00000001) /*!< Channel 1 Global interrupt flag */ -#define DMA_IFR_TCIF1 ((uint32_t)0x00000002) /*!< Channel 1 Transfer Complete flag */ -#define DMA_IFR_HTIF1 ((uint32_t)0x00000004) /*!< Channel 1 Half Transfer flag */ -#define DMA_IFR_ERRIF1 ((uint32_t)0x00000008) /*!< Channel 1 Transfer Error flag */ -#define DMA_IFR_GIF2 ((uint32_t)0x00000010) /*!< Channel 2 Global interrupt flag */ -#define DMA_IFR_TCIF2 ((uint32_t)0x00000020) /*!< Channel 2 Transfer Complete flag */ -#define DMA_IFR_HTIF2 ((uint32_t)0x00000040) /*!< Channel 2 Half Transfer flag */ -#define DMA_IFR_ERRIF2 ((uint32_t)0x00000080) /*!< Channel 2 Transfer Error flag */ -#define DMA_IFR_GIF3 ((uint32_t)0x00000100) /*!< Channel 3 Global interrupt flag */ -#define DMA_IFR_TCIF3 ((uint32_t)0x00000200) /*!< Channel 3 Transfer Complete flag */ -#define DMA_IFR_HTIF3 ((uint32_t)0x00000400) /*!< Channel 3 Half Transfer flag */ -#define DMA_IFR_ERRIF3 ((uint32_t)0x00000800) /*!< Channel 3 Transfer Error flag */ -#define DMA_IFR_GIF4 ((uint32_t)0x00001000) /*!< Channel 4 Global interrupt flag */ -#define DMA_IFR_TCIF4 ((uint32_t)0x00002000) /*!< Channel 4 Transfer Complete flag */ -#define DMA_IFR_HTIF4 ((uint32_t)0x00004000) /*!< Channel 4 Half Transfer flag */ -#define DMA_IFR_ERRIF4 ((uint32_t)0x00008000) /*!< Channel 4 Transfer Error flag */ -#define DMA_IFR_GIF5 ((uint32_t)0x00010000) /*!< Channel 5 Global interrupt flag */ -#define DMA_IFR_TCIF5 ((uint32_t)0x00020000) /*!< Channel 5 Transfer Complete flag */ -#define DMA_IFR_HTIF5 ((uint32_t)0x00040000) /*!< Channel 5 Half Transfer flag */ -#define DMA_IFR_ERRIF5 ((uint32_t)0x00080000) /*!< Channel 5 Transfer Error flag */ -#define DMA_IFR_GIF6 ((uint32_t)0x00100000) /*!< Channel 6 Global interrupt flag */ -#define DMA_IFR_TCIF6 ((uint32_t)0x00200000) /*!< Channel 6 Transfer Complete flag */ -#define DMA_IFR_HTIF6 ((uint32_t)0x00400000) /*!< Channel 6 Half Transfer flag */ -#define DMA_IFR_ERRIF6 ((uint32_t)0x00800000) /*!< Channel 6 Transfer Error flag */ -#define DMA_IFR_GIF7 ((uint32_t)0x01000000) /*!< Channel 7 Global interrupt flag */ -#define DMA_IFR_TCIF7 ((uint32_t)0x02000000) /*!< Channel 7 Transfer Complete flag */ -#define DMA_IFR_HTIF7 ((uint32_t)0x04000000) /*!< Channel 7 Half Transfer flag */ -#define DMA_IFR_ERRIF7 ((uint32_t)0x08000000) /*!< Channel 7 Transfer Error flag */ - -/******************* Bit definition for DMA_ICR register *******************/ -#define DMA_ICR_GIC1 ((uint32_t)0x00000001) /*!< Channel 1 Global interrupt clear */ -#define DMA_ICR_TCIC1 ((uint32_t)0x00000002) /*!< Channel 1 Transfer Complete clear */ -#define DMA_ICR_HTIC1 ((uint32_t)0x00000004) /*!< Channel 1 Half Transfer clear */ -#define DMA_ICR_ERRIC1 ((uint32_t)0x00000008) /*!< Channel 1 Transfer Error clear */ -#define DMA_ICR_GIC2 ((uint32_t)0x00000010) /*!< Channel 2 Global interrupt clear */ -#define DMA_ICR_TCIC2 ((uint32_t)0x00000020) /*!< Channel 2 Transfer Complete clear */ -#define DMA_ICR_HTIC2 ((uint32_t)0x00000040) /*!< Channel 2 Half Transfer clear */ -#define DMA_ICR_ERRIC2 ((uint32_t)0x00000080) /*!< Channel 2 Transfer Error clear */ -#define DMA_ICR_GIC3 ((uint32_t)0x00000100) /*!< Channel 3 Global interrupt clear */ -#define DMA_ICR_TCIC3 ((uint32_t)0x00000200) /*!< Channel 3 Transfer Complete clear */ -#define DMA_ICR_HTIC3 ((uint32_t)0x00000400) /*!< Channel 3 Half Transfer clear */ -#define DMA_ICR_ERRIC3 ((uint32_t)0x00000800) /*!< Channel 3 Transfer Error clear */ -#define DMA_ICR_GIC4 ((uint32_t)0x00001000) /*!< Channel 4 Global interrupt clear */ -#define DMA_ICR_TCIC4 ((uint32_t)0x00002000) /*!< Channel 4 Transfer Complete clear */ -#define DMA_ICR_HTIC4 ((uint32_t)0x00004000) /*!< Channel 4 Half Transfer clear */ -#define DMA_ICR_ERRIC4 ((uint32_t)0x00008000) /*!< Channel 4 Transfer Error clear */ -#define DMA_ICR_GIC5 ((uint32_t)0x00010000) /*!< Channel 5 Global interrupt clear */ -#define DMA_ICR_TCIC5 ((uint32_t)0x00020000) /*!< Channel 5 Transfer Complete clear */ -#define DMA_ICR_HTIC5 ((uint32_t)0x00040000) /*!< Channel 5 Half Transfer clear */ -#define DMA_ICR_ERRIC5 ((uint32_t)0x00080000) /*!< Channel 5 Transfer Error clear */ -#define DMA_ICR_GIC6 ((uint32_t)0x00100000) /*!< Channel 6 Global interrupt clear */ -#define DMA_ICR_TCIC6 ((uint32_t)0x00200000) /*!< Channel 6 Transfer Complete clear */ -#define DMA_ICR_HTIC6 ((uint32_t)0x00400000) /*!< Channel 6 Half Transfer clear */ -#define DMA_ICR_ERRIC6 ((uint32_t)0x00800000) /*!< Channel 6 Transfer Error clear */ -#define DMA_ICR_GIC7 ((uint32_t)0x01000000) /*!< Channel 7 Global interrupt clear */ -#define DMA_ICR_TCIC7 ((uint32_t)0x02000000) /*!< Channel 7 Transfer Complete clear */ -#define DMA_ICR_HTIC7 ((uint32_t)0x04000000) /*!< Channel 6 Half Transfer clear */ -#define DMA_ICR_ERRIC7 ((uint32_t)0x08000000) /*!< Channel 7 Transfer Error clear */ - -/******************* Bit definition for DMA_CTLRx register ********************/ -#define DMA_CTLR_CHEN ((uint32_t)0x00000001) /*!< Channel enable */ -#define DMA_CTLR_TCIE ((uint32_t)0x00000002) /*!< Transfer complete interrupt enable */ -#define DMA_CTLR_HTIE ((uint32_t)0x00000004) /*!< Half Transfer interrupt enable */ -#define DMA_CTLR_ERRIE ((uint32_t)0x00000008) /*!< Transfer error interrupt enable */ -#define DMA_CTLR_DIR ((uint32_t)0x00000010) /*!< Data transfer direction */ -#define DMA_CTLR_CIRC ((uint32_t)0x00000020) /*!< Circular mode */ -#define DMA_CTLR_PNAGA ((uint32_t)0x00000040) /*!< Peripheral increment mode */ -#define DMA_CTLR_MNAGA ((uint32_t)0x00000080) /*!< Memory increment mode */ - -#define DMA_CTLR_PSIZE ((uint32_t)0x00000300) /*!< PSIZE[1:0] bits (Peripheral size) */ -#define DMA_CTLR_PSIZE_0 ((uint32_t)0x00000100) /*!< Bit 0 */ -#define DMA_CTLR_PSIZE_1 ((uint32_t)0x00000200) /*!< Bit 1 */ - -#define DMA_CTLR_MSIZE ((uint32_t)0x00000C00) /*!< MSIZE[1:0] bits (Memory size) */ -#define DMA_CTLR_MSIZE_0 ((uint32_t)0x00000400) /*!< Bit 0 */ -#define DMA_CTLR_MSIZE_1 ((uint32_t)0x00000800) /*!< Bit 1 */ - -#define DMA_CTLR_PRIO ((uint32_t)0x00003000) /*!< PRIO[1:0] bits(Channel Priority level)*/ -#define DMA_CTLR_PRIO_0 ((uint32_t)0x00001000) /*!< Bit 0 */ -#define DMA_CTLR_PRIO_1 ((uint32_t)0x00002000) /*!< Bit 1 */ - -#define DMA_CTLR_MEMTOMEM ((uint32_t)0x00004000) /*!< Memory to memory mode */ - -/******************************************************************************/ -/* Peripheral Registers_Bits_Definition */ -/******************************************************************************/ -/******************************************************************************/ -/* Ethernet MAC Registers bits definitions */ -/******************************************************************************/ - -/* Bit definition for Ethernet MAC Configuration register */ -#define ETH_MAC_CFR_WDD ((uint32_t)0x00800000) /* Watchdog disable */ -#define ETH_MAC_CFR_JBD ((uint32_t)0x00400000) /* Jabber disable */ -#define ETH_MAC_CFR_IG ((uint32_t)0x000E0000) /* Inter-frame gap */ -#define ETH_MAC_CFR_IG_96BIT ((uint32_t)0x00000000) /* Minimum IG 96Bit */ -#define ETH_MAC_CFR_IG_88BIT ((uint32_t)0x00020000) /* Minimum IG 88Bit */ -#define ETH_MAC_CFR_IG_80BIT ((uint32_t)0x00040000) /* Minimum IG 80Bit */ -#define ETH_MAC_CFR_IG_72BIT ((uint32_t)0x00060000) /* Minimum IG 72Bit */ -#define ETH_MAC_CFR_IG_64BIT ((uint32_t)0x00080000) /* Minimum IG 64Bit */ -#define ETH_MAC_CFR_IG_56BIT ((uint32_t)0x000A0000) /* Minimum IG 56Bit */ -#define ETH_MAC_CFR_IG_48BIT ((uint32_t)0x000C0000) /* Minimum IG 48Bit */ -#define ETH_MAC_CFR_IG_40BIT ((uint32_t)0x000E0000) /* Minimum IG 40Bit */ -#define ETH_MAC_CFR_CSD ((uint32_t)0x00010000) /* Carrier sense disable */ -#define ETH_MAC_CFR_SPD ((uint32_t)0x00004000) /* Ethernet speed */ -#define ETH_MAC_CFR_ROD ((uint32_t)0x00002000) /* Receive own disable */ -#define ETH_MAC_CFR_LBM ((uint32_t)0x00001000) /* loopback mode */ -#define ETH_MAC_CFR_DPM ((uint32_t)0x00000800) /* Duplex mode */ -#define ETH_MAC_CFR_IP4CO ((uint32_t)0x00000400) /* IP Checksum offload */ -#define ETH_MAC_CFR_RTD ((uint32_t)0x00000200) /* Retry disable */ -#define ETH_MAC_CFR_APCD ((uint32_t)0x00000080) /* automatic pad/CRC drop */ -#define ETH_MAC_CFR_BOL ((uint32_t)0x00000060) /* Back-off limit */ -#define ETH_MAC_CFR_BOL_10 ((uint32_t)0x00000000) /* min (n, 10) */ -#define ETH_MAC_CFR_BOL_8 ((uint32_t)0x00000020) /* min (n, 8) */ -#define ETH_MAC_CFR_BOL_4 ((uint32_t)0x00000040) /* min (n, 4) */ -#define ETH_MAC_CFR_BOL_1 ((uint32_t)0x00000060) /* min (n, 1) */ -#define ETH_MAC_CFR_DFC ((uint32_t)0x00000010) /* Defferal check */ -#define ETH_MAC_CFR_TEN ((uint32_t)0x00000008) /* Transmitter enable */ -#define ETH_MAC_CFR_REN ((uint32_t)0x00000004) /* Receiver enable */ - -/* Bit definition for Ethernet MAC Frame Filter Register */ -#define ETH_MAC_FRMFR_FD ((uint32_t)0x80000000) /* Filter disable */ -#define ETH_MAC_FRMFR_HPFLT ((uint32_t)0x00000400) /* Hash or perfect filter */ -#define ETH_MAC_FRMFR_SAFLT ((uint32_t)0x00000200) /* Source address filter enable */ -#define ETH_MAC_FRMFR_SAIFLT ((uint32_t)0x00000100) /* SA inverse filtering enable */ -#define ETH_MAC_FRMFR_PCFRM ((uint32_t)0x000000C0) /* Pass control frames */ -#define ETH_MAC_FRMFR_PCF_BLOCKALL ((uint32_t)0x00000040) /* Prevent all control frames received */ -#define ETH_MAC_FRMFR_PCF_FORWARDALL ((uint32_t)0x00000080) /* Accept all control frames received */ -#define ETH_MAC_FRMFR_PCF_FORWARDPASSEDADDRFILTER ((uint32_t)0x000000C0) /* Accept control frames that pass the Address Filter */ -#define ETH_MAC_FRMFR_BFRMD ((uint32_t)0x00000020) /* Broadcast frame disable */ -#define ETH_MAC_FRMFR_MFD ((uint32_t)0x00000010) /* Multicast filter disable */ -#define ETH_MAC_FRMFR_DAIFLT ((uint32_t)0x00000008) /* DA Inverse filtering enable */ -#define ETH_MAC_FRMFR_HMF ((uint32_t)0x00000004) /* Hash multicast filter enable */ -#define ETH_MAC_FRMFR_HUF ((uint32_t)0x00000002) /* Hash unicast filter enable */ -#define ETH_MAC_FRMFR_PM ((uint32_t)0x00000001) /* Promiscuous mode */ - -/* Bit definition for Ethernet MAC Hash List High Register */ -#define ETH_MAC_HLHR_HLH ((uint32_t)0xFFFFFFFF) /* Hash list high */ - -/* Bit definition for Ethernet MAC Hash List Low Register */ -#define ETH_MAC_HLLR_HLL ((uint32_t)0xFFFFFFFF) /* Hash list low */ - -/* Bit definition for Ethernet MAC PHY Address Register */ -#define ETH_MAC_PHYAR_PA ((uint32_t)0x0000F800) /* PHY address */ -#define ETH_MAC_PHYAR_PR ((uint32_t)0x000007C0) /* PHY register address */ -#define ETH_MAC_PHYAR_CLR ((uint32_t)0x0000001C) /* MDC clock range */ -#define ETH_MAC_PHYAR_CLR_DIV42 ((uint32_t)0x00000000) /* HCLK:60-90 MHz; MDC clock= HCLK/42 */ -#define ETH_MAC_PHYAR_CLR_DIV64 ((uint32_t)0x00000004) /* HCLK:90-108 MHz; MDC clock= HCLK/64 */ -#define ETH_MAC_PHYAR_CLR_DIV16 ((uint32_t)0x00000008) /* HCLK:20-35 MHz; MDC clock= HCLK/16 */ -#define ETH_MAC_PHYAR_CLR_DIV26 ((uint32_t)0x0000000C) /* HCLK:35-60 MHz; MDC clock= HCLK/26 */ -#define ETH_MAC_PHYAR_PW ((uint32_t)0x00000002) /* PHY write */ -#define ETH_MAC_PHYAR_PB ((uint32_t)0x00000001) /* PHY busy */ - -/* Bit definition for Ethernet PHY Data Register */ -#define ETH_MAC_PHYDR_PD ((uint32_t)0x0000FFFF) /* PHY data: read/write data from/to PHY */ - -/* Bit definition for Ethernet MAC Flow Control Register */ -#define ETH_MAC_FCTLR_PTM ((uint32_t)0xFFFF0000) /* Pause time */ -#define ETH_MAC_FCTLR_ZQPD ((uint32_t)0x00000080) /* Zero-quanta pause disable */ -#define ETH_MAC_FCTLR_PLTS ((uint32_t)0x00000030) /* Pause low threshold */ -#define ETH_MAC_FCTLR_PLTS_MINUS4 ((uint32_t)0x00000000) /* Pause time minus 4 slot times */ -#define ETH_MAC_FCTLR_PLTS_MINUS28 ((uint32_t)0x00000010) /* Pause time minus 28 slot times */ -#define ETH_MAC_FCTLR_PLTS_MINUS144 ((uint32_t)0x00000020) /* Pause time minus 144 slot times */ -#define ETH_MAC_FCTLR_PLTS_MINUS256 ((uint32_t)0x00000030) /* Pause time minus 256 slot times */ -#define ETH_MAC_FCTLR_UPFDT ((uint32_t)0x00000008) /* Unicast pause frame detect enable*/ -#define ETH_MAC_FCTLR_RFCEN ((uint32_t)0x00000004) /* Receive flow control enable */ -#define ETH_MAC_FCTLR_TFCEN ((uint32_t)0x00000002) /* Transmit flow control enable */ -#define ETH_MAC_FCTLR_FLCBBKPA ((uint32_t)0x00000001) /* Flow control busy(in full duplex mode)/backpressure activate(in half duplex mode) */ - -/* Bit definition for Ethernet MAC VLAN Tag Register */ -#define ETH_MAC_VLTR_VLTC ((uint32_t)0x00010000) /* 12-bit VLAN tag comparison enable*/ -#define ETH_MAC_VLTR_VLTI ((uint32_t)0x0000FFFF) /* VLAN tag identifier */ - -/* Bit definition for Ethernet MAC Remote Wake-UpFrame Filter Register */ -#define ETH_MAC_RWUFFR_D ((uint32_t)0xFFFFFFFF) /* Wake-up frame filter register data */ -/* Eight sequential Writes to this address (offset 0x28) will write all Wake-UpFrame Filter Registers. - Eight sequential Reads from this address (offset 0x28) will read all Wake-UpFrame Filter Registers. */ -/* Wake-UpFrame Filter Reg0 : Filter 0 Byte Mask - Wake-UpFrame Filter Reg1 : Filter 1 Byte Mask - Wake-UpFrame Filter Reg2 : Filter 2 Byte Mask - Wake-UpFrame Filter Reg3 : Filter 3 Byte Mask - Wake-UpFrame Filter Reg4 : RSVD - Filter3 Command - RSVD - Filter2 Command - - RSVD - Filter1 Command - RSVD - Filter0 Command - Wake-UpFrame Filter Re5 : Filter3 Offset - Filter2 Offset - Filter1 Offset - Filter0 Offset - Wake-UpFrame Filter Re6 : Filter1 CRC16 - Filter0 CRC16 - Wake-UpFrame Filter Re7 : Filter3 CRC16 - Filter2 CRC16 */ - -/* Bit definition for Ethernet MAC WUM Register */ -#define ETH_MAC_WUMR_WUFFRPR ((uint32_t)0x80000000) /* Wake-Up Frame Filter Register Pointer Reset */ -#define ETH_MAC_WUMR_GU ((uint32_t)0x00000200) /* Global Unicast */ -#define ETH_MAC_WUMR_WUFR ((uint32_t)0x00000040) /* Wake-Up Frame Received */ -#define ETH_MAC_WUMR_MPKR ((uint32_t)0x00000020) /* Magic Packet Received */ -#define ETH_MAC_WUMR_WFEN ((uint32_t)0x00000004) /* Wake-Up Frame Enable */ -#define ETH_MAC_WUMR_MPEN ((uint32_t)0x00000002) /* Magic Packet Enable */ -#define ETH_MAC_WUMR_PWD ((uint32_t)0x00000001) /* Power Down */ - -/* Bit definition for Ethernet MAC Status Register */ -#define ETH_MAC_ISR_TMST ((uint32_t)0x00000200) /* Time stamp trigger status */ -#define ETH_MAC_ISR_MSCT ((uint32_t)0x00000040) /* MSC transmit status */ -#define ETH_MAC_ISR_MSCR ((uint32_t)0x00000020) /* MSC receive status */ -#define ETH_MAC_ISR_MSC ((uint32_t)0x00000010) /* MSC status */ -#define ETH_MAC_ISR_WUM ((uint32_t)0x00000008) /* WUM status */ - -/* Bit definition for Ethernet MAC Interrupt Mask Register */ -#define ETH_MAC_IMR_TMSTIM ((uint32_t)0x00000200) /* Time stamp trigger interrupt mask */ -#define ETH_MAC_IMR_WUMIM ((uint32_t)0x00000008) /* WUM interrupt mask */ - -/* Bit definition for Ethernet MAC Address0 High Register */ -#define ETH_MAC_A0HR_ADDR0H ((uint32_t)0x0000FFFF) /* MAC address0 high */ - -/* Bit definition for Ethernet MAC Address0 Low Register */ -#define ETH_MAC_A0HR_ADDR0L ((uint32_t)0xFFFFFFFF) /* MAC address0 low */ - -/* Bit definition for Ethernet MAC Address1 High Register */ -#define ETH_MAC_A1HR_AFE ((uint32_t)0x80000000) /* Address filter enable */ -#define ETH_MAC_A1HR_SAF ((uint32_t)0x40000000) /* Source address filter */ -#define ETH_MAC_A1HR_MB ((uint32_t)0x3F000000) /* Mask byte control */ -#define ETH_MAC_A1HR_MB_HBITS15_8 ((uint32_t)0x20000000) /* High register bits [15:8] */ -#define ETH_MAC_A1HR_MB_HBITS7_0 ((uint32_t)0x10000000) /* High register bits [7:0] */ -#define ETH_MAC_A1HR_MB_LBITS31_24 ((uint32_t)0x08000000) /* Low register bits [31:24] */ -#define ETH_MAC_A1HR_MB_LBITS23_16 ((uint32_t)0x04000000) /* Low register bits [23:16] */ -#define ETH_MAC_A1HR_MB_LBITS15_8 ((uint32_t)0x02000000) /* Low register bits [15:8] */ -#define ETH_MAC_A1HR_MB_LBITS7_0 ((uint32_t)0x01000000) /* Low register bits [7:0] */ -#define ETH_MAC_A1HR_ADDR1H ((uint32_t)0x0000FFFF) /* MAC address1 high */ - -/* Bit definition for Ethernet MAC Address1 Low Register */ -#define ETH_MAC_A1LR_ADDR1L ((uint32_t)0xFFFFFFFF) /* MAC address1 low */ - -/* Bit definition for Ethernet MAC Address2 High Register */ -#define ETH_MAC_A2HR_AFE ((uint32_t)0x80000000) /* Address filter enable */ -#define ETH_MAC_A2HR_SAF ((uint32_t)0x40000000) /* Source address filter */ -#define ETH_MAC_A2HR_MB ((uint32_t)0x3F000000) /* Mask byte control */ -#define ETH_MAC_A2HR_MB_HBITS15_8 ((uint32_t)0x20000000) /* High register bits [15:8] */ -#define ETH_MAC_A2HR_MB_HBITS7_0 ((uint32_t)0x10000000) /* High register bits [7:0] */ -#define ETH_MAC_A2HR_MB_LBITS31_24 ((uint32_t)0x08000000) /* Low register bits [31:24] */ -#define ETH_MAC_A2HR_MB_LBITS23_16 ((uint32_t)0x04000000) /* Low register bits [23:16] */ -#define ETH_MAC_A2HR_MB_LBITS15_8 ((uint32_t)0x02000000) /* Low register bits [15:8] */ -#define ETH_MAC_A2HR_MB_LBITS7_0 ((uint32_t)0x01000000) /* Low register bits [7:0] */ -#define ETH_MAC_A2HR_ADDR2H ((uint32_t)0x0000FFFF) /* MAC address2 high */ - -/* Bit definition for Ethernet MAC Address2 Low Register */ -#define ETH_MAC_A2LR_ADDR2L ((uint32_t)0xFFFFFFFF) /* MAC address2 low */ - -/* Bit definition for Ethernet MAC Address3 High Register */ -#define ETH_MAC_A3HR_AFE ((uint32_t)0x80000000) /* Address filter enable */ -#define ETH_MAC_A3HR_SAF ((uint32_t)0x40000000) /* Source address filter */ -#define ETH_MAC_A3HR_MB ((uint32_t)0x3F000000) /* Mask byte control */ -#define ETH_MAC_A3HR_MB_HBITS15_8 ((uint32_t)0x20000000) /* High register bits [15:8] */ -#define ETH_MAC_A3HR_MB_HBITS7_0 ((uint32_t)0x10000000) /* High register bits [7:0] */ -#define ETH_MAC_A3HR_MB_LBITS31_24 ((uint32_t)0x08000000) /* Low register bits [31:24] */ -#define ETH_MAC_A3HR_MB_LBITS23_16 ((uint32_t)0x04000000) /* Low register bits [23:16] */ -#define ETH_MAC_A3HR_MB_LBITS15_8 ((uint32_t)0x02000000) /* Low register bits [15:8] */ -#define ETH_MAC_A3HR_MB_LBITS7_0 ((uint32_t)0x01000000) /* Low register bits [7:0] */ -#define ETH_MAC_A3HR_ADDR3H ((uint32_t)0x0000FFFF) /* MAC address3 high */ - -/* Bit definition for Ethernet MAC Address3 Low Register */ -#define ETH_MAC_A3LR_ADDR3L ((uint32_t)0xFFFFFFFF) /* MAC address3 low */ - -/* Bit definition for Ethernet MAC Flow Control threshold Register */ -#define ETH_MAC_FCTHR_RFD ((uint32_t)0x00000070) /* Threshold of deactive flow control */ -#define ETH_MAC_FCTHR_RFD_256BYTES ((uint32_t)0x00000000) /* Threshold level is 256 bytes */ -#define ETH_MAC_FCTHR_RFD_512BYTES ((uint32_t)0x00000010) /* Threshold level is 512 bytes */ -#define ETH_MAC_FCTHR_RFD_768BYTES ((uint32_t)0x00000020) /* Threshold level is 768 bytes */ -#define ETH_MAC_FCTHR_RFD_1024BYTES ((uint32_t)0x00000030) /* Threshold level is 1024 bytes */ -#define ETH_MAC_FCTHR_RFD_1280BYTES ((uint32_t)0x00000040) /* Threshold level is 1280 bytes */ -#define ETH_MAC_FCTHR_RFD_1536BYTES ((uint32_t)0x00000050) /* Threshold level is 1536 bytes */ -#define ETH_MAC_FCTHR_RFD_1792BYTES ((uint32_t)0x00000060) /* Threshold level is 1792 bytes */ -#define ETH_MAC_FCTHR_RFA ((uint32_t)0x00000007) /* Threshold of active flow control */ -#define ETH_MAC_FCTHR_RFA_256BYTES ((uint32_t)0x00000000) /* Threshold level is 256 bytes */ -#define ETH_MAC_FCTHR_RFA_512BYTES ((uint32_t)0x00000001) /* Threshold level is 512 bytes */ -#define ETH_MAC_FCTHR_RFA_768BYTES ((uint32_t)0x00000002) /* Threshold level is 768 bytes */ -#define ETH_MAC_FCTHR_RFA_1024BYTES ((uint32_t)0x00000003) /* Threshold level is 1024 bytes */ -#define ETH_MAC_FCTHR_RFA_1280BYTES ((uint32_t)0x00000004) /* Threshold level is 1280 bytes */ -#define ETH_MAC_FCTHR_RFA_1536BYTES ((uint32_t)0x00000005) /* Threshold level is 1536 bytes */ -#define ETH_MAC_FCTHR_RFA_1792BYTES ((uint32_t)0x00000006) /* Threshold level is 1792 bytes */ -/******************************************************************************/ -/* Ethernet MSC Registers bits definition */ -/******************************************************************************/ - -/* Bit definition for Ethernet MSC Contol Register */ -#define ETH_MSC_CTLR_MCFZ ((uint32_t)0x00000008) /* MSC Counter Freeze */ -#define ETH_MSC_CTLR_RTOR ((uint32_t)0x00000004) /* Reset on Read */ -#define ETH_MSC_CTLR_CTSR ((uint32_t)0x00000002) /* Counter Stop Rollover */ -#define ETH_MSC_CTLR_CTR ((uint32_t)0x00000001) /* Counters Reset */ - -/* Bit definition for Ethernet MSC Receive Interrupt Status Register */ -#define ETH_MSC_RISR_RGUF ((uint32_t)0x00020000) /* receive good unicast frames counter reaches half the maximum value */ -#define ETH_MSC_RISR_RFAE ((uint32_t)0x00000040) /* receive alignment error counter reaches half the maximum value */ -#define ETH_MSC_RISR_RFCE ((uint32_t)0x00000020) /* receive crc error counter reaches half the maximum value */ - -/* Bit definition for Ethernet MSC Transmit Interrupt Status Register */ -#define ETH_MSC_TISR_TGF ((uint32_t)0x00200000) /* Transmit good frame count counter reaches half the maximum value */ -#define ETH_MSC_TISR_TGFMSC ((uint32_t)0x00008000) /* Transmit good multi col counter reaches half the maximum value */ -#define ETH_MSC_TISR_TGFSC ((uint32_t)0x00004000) /* Transmit good single col counter reaches half the maximum value */ - -/* Bit definition for Ethernet MSC Receive Interrupt Mask Register */ -#define ETH_MSC_RIMR_RGUFIM ((uint32_t)0x00020000) /* RGUF interrupt Mask */ -#define ETH_MSC_RIMR_RFAEIM ((uint32_t)0x00000040) /* RFAE interrupt Mask */ -#define ETH_MSC_RIMR_RFCEIM ((uint32_t)0x00000020) /* RFCE interrupt Mask */ - -/* Bit definition for Ethernet MSC Transmit Interrupt Mask Register */ -#define ETH_MSC_TIMR_TGFIM ((uint32_t)0x00200000) /* TGF interrupt Mask */ -#define ETH_MSC_TIMR_TGFMSCIM ((uint32_t)0x00008000) /* TGFMSC interrupt Mask */ -#define ETH_MSC_TIMR_TGFSCIM ((uint32_t)0x00004000) /* TGFSC interrupt Mask */ - -/* Bit definition for Ethernet MSC Transmitted Good Frames after Single Collision Counter Register */ -#define ETH_MSC_SCCNT_SCC ((uint32_t)0xFFFFFFFF) /* Transmitted good frames single collision counter */ - -/* Bit definition for Ethernet MSC Transmitted Good Frames after More than a Single Collision Counter Register */ -#define ETH_MSC_MSCCNT_MSCC ((uint32_t)0xFFFFFFFF) /* Transmitted good frames after more single collision counter */ - -/* Bit definition for Ethernet MSC Transmitted Good Frames Counter Register */ -#define ETH_MSC_TGFCNT_TGF ((uint32_t)0xFFFFFFFF) /* Transmitted good frames counter */ - -/* Bit definition for Ethernet MSC Received Frames with CRC Error Counter Register */ -#define ETH_MSC_RFCECNT_RFCER ((uint32_t)0xFFFFFFFF) /* Received frames CRC error counter */ - -/* Bit definition for Ethernet MSC Received Frames with Alignement Error Counter Register */ -#define ETH_MSC_RFAECNT_RFAER ((uint32_t)0xFFFFFFFF) /* Received frames alignment error counter */ - -/* Bit definition for Ethernet MSC Received Good Unicast Frames Counter Register */ -#define ETH_MSC_RGUFCNT_RGUF ((uint32_t)0xFFFFFFFF) /* Received good unicast frames counter */ - -/******************************************************************************/ -/* Ethernet PTP Registers bits definition */ -/******************************************************************************/ - -/* Bit definition for Ethernet PTP Time Stamp Contol Register */ -#define ETH_PTP_TSCTLR_TMSARU ((uint32_t)0x00000020) /* Time stamp addend register update */ -#define ETH_PTP_TSCTLR_TMSITEN ((uint32_t)0x00000010) /* Time stamp interrupt trigger enable */ -#define ETH_PTP_TSCTLR_TMSSTU ((uint32_t)0x00000008) /* Time stamp system time update */ -#define ETH_PTP_TSCTLR_TMSSTI ((uint32_t)0x00000004) /* Time stamp system time initialize */ -#define ETH_PTP_TSCTLR_TMSFCU ((uint32_t)0x00000002) /* Time stamp fine or coarse update */ -#define ETH_PTP_TSCTLR_TMSEN ((uint32_t)0x00000001) /* Time stamp enable */ - -/* Bit definition for Ethernet PTP Sub-Second Increment Register */ -#define ETH_PTP_SSINCR_STMSSI ((uint32_t)0x000000FF) /* System time Subsecond increment */ - -/* Bit definition for Ethernet PTP Time Stamp High Register */ -#define ETH_PTP_TMSHR_STMS ((uint32_t)0xFFFFFFFF) /* System Time second */ - -/* Bit definition for Ethernet PTP Time Stamp Low Register */ -#define ETH_PTP_TMSLR_STS ((uint32_t)0x80000000) /* System Time Positive or negative time */ -#define ETH_PTP_TMSLR_STMSS ((uint32_t)0x7FFFFFFF) /* System Time subseconds */ - -/* Bit definition for Ethernet PTP Time Stamp High Update Register */ -#define ETH_PTP_TMSHUR_TMSUS ((uint32_t)0xFFFFFFFF) /* Time stamp update seconds */ - -/* Bit definition for Ethernet PTP Time Stamp Low Update Register */ -#define ETH_PTP_TMSLUR_TMSUPNS ((uint32_t)0x80000000) /* Time stamp update Positive or negative time */ -#define ETH_PTP_TMSLUR_TMSUSS ((uint32_t)0x7FFFFFFF) /* Time stamp update subseconds */ - -/* Bit definition for Ethernet PTP Time Stamp Addend Register */ -#define ETH_PTP_TSACNT_TMSA ((uint32_t)0xFFFFFFFF) /* Time stamp addend */ - -/* Bit definition for Ethernet PTP Expected Time High Register */ -#define ETH_PTP_ETHR_ETSH ((uint32_t)0xFFFFFFFF) /* Expected time stamp high */ - -/* Bit definition for Ethernet PTP Expected Time Low Register */ -#define ETH_PTP_ETLR_ETSL ((uint32_t)0xFFFFFFFF) /* Expected time stamp low */ - -/******************************************************************************/ -/* Ethernet DMA Registers bits definition */ -/******************************************************************************/ - -/* Bit definition for Ethernet DMA Bus Control Register */ -#define ETH_DMA_BCR_AA ((uint32_t)0x02000000) /* Address-aligned */ -#define ETH_DMA_BCR_FPBL ((uint32_t)0x01000000) /* four x PBL mode */ -#define ETH_DMA_BCR_UIP ((uint32_t)0x00800000) /* Use Independent PBL */ -#define ETH_DMA_BCR_RXDP ((uint32_t)0x007E0000) /* receive DMA PBL */ -#define ETH_DMA_BCR_RXDP_1BEAT ((uint32_t)0x00020000) /* maximum number of beats 1 */ -#define ETH_DMA_BCR_RXDP_2BEAT ((uint32_t)0x00040000) /* maximum number of beats 2 */ -#define ETH_DMA_BCR_RXDP_4BEAT ((uint32_t)0x00080000) /* maximum number of beats 4 */ -#define ETH_DMA_BCR_RXDP_8BEAT ((uint32_t)0x00100000) /* maximum number of beats 8 */ -#define ETH_DMA_BCR_RXDP_16BEAT ((uint32_t)0x00200000) /* maximum number of beats 16 */ -#define ETH_DMA_BCR_RXDP_32BEAT ((uint32_t)0x00400000) /* maximum number of beats 32 */ -#define ETH_DMA_BCR_RXDP_4xPBL_4BEAT ((uint32_t)0x01020000) /* maximum number of beats 4 */ -#define ETH_DMA_BCR_RXDP_4xPBL_8BEAT ((uint32_t)0x01040000) /* maximum number of beats 8 */ -#define ETH_DMA_BCR_RXDP_4xPBL_16BEAT ((uint32_t)0x01080000) /* maximum number of beats 16 */ -#define ETH_DMA_BCR_RXDP_4xPBL_32BEAT ((uint32_t)0x01100000) /* maximum number of beats 32 */ -#define ETH_DMA_BCR_RXDP_4xPBL_64BEAT ((uint32_t)0x01200000) /* maximum number of beats 64 */ -#define ETH_DMA_BCR_RXDP_4xPBL_128BEAT ((uint32_t)0x01400000) /* maximum number of beats 128 */ -#define ETH_DMA_BCR_FB ((uint32_t)0x00010000) /* Fixed Burst */ -#define ETH_DMA_BCR_RTPR ((uint32_t)0x0000C000) /* receive and transmit priority ratio */ -#define ETH_DMA_BCR_RTPR_1_1 ((uint32_t)0x00000000) /* receive and transmit priority ratio */ -#define ETH_DMA_BCR_RTPR_2_1 ((uint32_t)0x00004000) /* receive and transmit priority ratio */ -#define ETH_DMA_BCR_RTPR_3_1 ((uint32_t)0x00008000) /* receive and transmit priority ratio */ -#define ETH_DMA_BCR_RTPR_4_1 ((uint32_t)0x0000C000) /* receive and transmit priority ratio */ -#define ETH_DMA_BCR_PGBL ((uint32_t)0x00003F00) /* Programmable burst length */ -#define ETH_DMA_BCR_PBL_1BEAT ((uint32_t)0x00000100) /* maximum number of beats is 1 */ -#define ETH_DMA_BCR_PBL_2BEAT ((uint32_t)0x00000200) /* maximum number of beats is 2 */ -#define ETH_DMA_BCR_PBL_4BEAT ((uint32_t)0x00000400) /* maximum number of beats is 4 */ -#define ETH_DMA_BCR_PBL_8BEAT ((uint32_t)0x00000800) /* maximum number of beats is 8 */ -#define ETH_DMA_BCR_PBL_16BEAT ((uint32_t)0x00001000) /* maximum number of beats is 16 */ -#define ETH_DMA_BCR_PBL_32BEAT ((uint32_t)0x00002000) /* maximum number of beats is 32 */ -#define ETH_DMA_BCR_PBL_4xPBL_4BEAT ((uint32_t)0x01000100) /* maximum number of beats is 4 */ -#define ETH_DMA_BCR_PBL_4xPBL_8BEAT ((uint32_t)0x01000200) /* maximum number of beats is 8 */ -#define ETH_DMA_BCR_PBL_4xPBL_16BEAT ((uint32_t)0x01000400) /* maximum number of beats is 16 */ -#define ETH_DMA_BCR_PBL_4xPBL_32BEAT ((uint32_t)0x01000800) /* maximum number of beats is 32 */ -#define ETH_DMA_BCR_PBL_4xPBL_64BEAT ((uint32_t)0x01001000) /* maximum number of beats is 64 */ -#define ETH_DMA_BCR_PBL_4xPBL_128BEAT ((uint32_t)0x01002000) /* maximum number of beats is 128 */ -#define ETH_DMA_BCR_DPSL ((uint32_t)0x0000007C) /* Descriptor Skip Length */ -#define ETH_DMA_BCR_DAB ((uint32_t)0x00000002) /* DMA arbitration */ -#define ETH_DMA_BCR_SWR ((uint32_t)0x00000001) /* Software reset */ - -/* Bit definition for Ethernet DMA Transmit Poll Enable Register */ -#define ETH_DMA_TPER_TPE ((uint32_t)0xFFFFFFFF) /* Transmit poll enable */ - -/* Bit definition for Ethernet DMA Receive Poll Enable Register */ -#define ETH_DMA_RPER_RPE ((uint32_t)0xFFFFFFFF) /* Receive poll enable */ - -/* Bit definition for Ethernet DMA Receive Descriptor Tab Address Register */ -#define ETH_DMA_RDTAR_SRT ((uint32_t)0xFFFFFFFF) /* Start of receive tab */ - -/* Bit definition for Ethernet DMA Transmit Descriptor Tab Address Register */ -#define ETH_DMA_TDTAR_STT ((uint32_t)0xFFFFFFFF) /* Start of transmit tab */ - -/* Bit definition for Ethernet DMA Status Register */ -#define ETH_DMA_STR_TST ((uint32_t)0x20000000) /* Time-stamp trigger status */ -#define ETH_DMA_STR_WUM ((uint32_t)0x10000000) /* WUM status */ -#define ETH_DMA_STR_MSC ((uint32_t)0x08000000) /* MSC status */ -#define ETH_DMA_STR_EB ((uint32_t)0x03800000) /* Error bits status */ -/* combination with EB[2:0] for GetBitState function */ -#define ETH_DMA_STR_EB_DESCACCESS ((uint32_t)0x02000000) /* Error during descriptor or buffer access */ -#define ETH_DMA_STR_EB_READTRANSF ((uint32_t)0x01000000) /* Error during write trnsf of read transfr */ -#define ETH_DMA_STR_EB_DATATRANSFTX ((uint32_t)0x00800000) /* Error during data transfer by TxDMA or RxDMA */ -#define ETH_DMA_STR_TP ((uint32_t)0x00700000) /* Transmit process state */ -#define ETH_DMA_STR_TP_STOPPED ((uint32_t)0x00000000) /* Reset or Stop Tx Command issued */ -#define ETH_DMA_STR_TP_FETCHING ((uint32_t)0x00100000) /* fetching the Tx descriptor */ -#define ETH_DMA_STR_TP_WAITING ((uint32_t)0x00200000) /* waiting for status */ -#define ETH_DMA_STR_TP_READING ((uint32_t)0x00300000) /* reading the data from host memory buffer and queuing it to transmit buffer */ -#define ETH_DMA_STR_TP_SUSPENDED ((uint32_t)0x00600000) /* Tx Descriptor unavailabe or transmit buffer underflow */ -#define ETH_DMA_STR_TP_CLOSING ((uint32_t)0x00700000) /* closing Tx descriptor */ -#define ETH_DMA_STR_RP ((uint32_t)0x000E0000) /* Receive process state */ -#define ETH_DMA_STR_RP_STOPPED ((uint32_t)0x00000000) /* Reset or Stop Rx Command issued */ -#define ETH_DMA_STR_RP_FETCHING ((uint32_t)0x00020000) /* fetching the Rx descriptor */ -#define ETH_DMA_STR_RP_WAITING ((uint32_t)0x00060000) /* waiting for receive packet */ -#define ETH_DMA_STR_RP_SUSPENDED ((uint32_t)0x00080000) /* Rx Descriptor unavailable */ -#define ETH_DMA_STR_RP_CLOSING ((uint32_t)0x000A0000) /* closing receive descriptor */ -#define ETH_DMA_STR_RP_QUEUING ((uint32_t)0x000E0000) /* transferring the receive packet data from recevie buffer to host memory */ -#define ETH_DMA_STR_NI ((uint32_t)0x00010000) /* Normal interrupt summary */ -#define ETH_DMA_STR_AI ((uint32_t)0x00008000) /* Abnormal interrupt summary */ -#define ETH_DMA_STR_ER ((uint32_t)0x00004000) /* Early receive status */ -#define ETH_DMA_STR_FBE ((uint32_t)0x00002000) /* Fatal bus error status */ -#define ETH_DMA_STR_ET ((uint32_t)0x00000400) /* Early transmit status */ -#define ETH_DMA_STR_RWT ((uint32_t)0x00000200) /* Receive watchdog timeout status */ -#define ETH_DMA_STR_RPS ((uint32_t)0x00000100) /* Receive process stopped status */ -#define ETH_DMA_STR_RBU ((uint32_t)0x00000080) /* Receive buffer unavailable status */ -#define ETH_DMA_STR_RS ((uint32_t)0x00000040) /* Receive status */ -#define ETH_DMA_STR_TU ((uint32_t)0x00000020) /* Transmit underflow status */ -#define ETH_DMA_STR_RO ((uint32_t)0x00000010) /* Receive overflow status */ -#define ETH_DMA_STR_TJT ((uint32_t)0x00000008) /* Transmit jabber timeout status */ -#define ETH_DMA_STR_TBU ((uint32_t)0x00000004) /* Transmit buffer unavailable status */ -#define ETH_DMA_STR_TPS ((uint32_t)0x00000002) /* Transmit process stopped status */ -#define ETH_DMA_STR_TS ((uint32_t)0x00000001) /* Transmit status */ - -/* Bit definition for Ethernet DMA Control Register */ -#define ETH_DMA_CTLR_DTCERFD ((uint32_t)0x04000000) /* Dropping of TCP/IP checksum error frames disable */ -#define ETH_DMA_CTLR_RSFD ((uint32_t)0x02000000) /* Receive store and forward */ -#define ETH_DMA_CTLR_DAFRF ((uint32_t)0x01000000) /* Disable flushing of received frames */ -#define ETH_DMA_CTLR_TSFD ((uint32_t)0x00200000) /* Transmit store and forward */ -#define ETH_DMA_CTLR_FTF ((uint32_t)0x00100000) /* Flush transmit FIFO */ -#define ETH_DMA_CTLR_TTHC ((uint32_t)0x0001C000) /* Transmit threshold control */ -#define ETH_DMAOMR_TTHC_64BYTES ((uint32_t)0x00000000) /* threshold level is 64 Bytes */ -#define ETH_DMAOMR_TTHC_128BYTES ((uint32_t)0x00004000) /* threshold level is 128 Bytes */ -#define ETH_DMAOMR_TTHC_192BYTES ((uint32_t)0x00008000) /* threshold level is 192 Bytes */ -#define ETH_DMAOMR_TTHC_256BYTES ((uint32_t)0x0000C000) /* threshold level is 256 Bytes */ -#define ETH_DMAOMR_TTHC_40BYTES ((uint32_t)0x00010000) /* threshold level is 40 Bytes */ -#define ETH_DMAOMR_TTHC_32BYTES ((uint32_t)0x00014000) /* threshold level is 32 Bytes */ -#define ETH_DMAOMR_TTHC_24BYTES ((uint32_t)0x00018000) /* threshold level is 24 Bytes */ -#define ETH_DMAOMR_TTHC_16BYTES ((uint32_t)0x0001C000) /* threshold level is 16 Bytes */ -#define ETH_DMA_CTLR_STE ((uint32_t)0x00002000) /* Start/stop transmission */ -#define ETH_DMA_CTLR_FERF ((uint32_t)0x00000080) /* Forward error frames */ -#define ETH_DMA_CTLR_FUF ((uint32_t)0x00000040) /* Forward undersized good frames */ -#define ETH_DMA_CTLR_RTHC ((uint32_t)0x00000018) /* receive threshold control */ -#define ETH_DMAOMR_RTHC_64BYTES ((uint32_t)0x00000000) /* threshold level is 64 Bytes */ -#define ETH_DMAOMR_RTHC_32BYTES ((uint32_t)0x00000008) /* threshold level is 32 Bytes */ -#define ETH_DMAOMR_RTHC_96BYTES ((uint32_t)0x00000010) /* threshold level is 96 Bytes */ -#define ETH_DMAOMR_RTHC_128BYTES ((uint32_t)0x00000018) /* threshold level is 128 Bytes */ -#define ETH_DMA_CTLR_OSF ((uint32_t)0x00000004) /* operate on second frame */ -#define ETH_DMA_CTLR_SRE ((uint32_t)0x00000002) /* Start/stop receive */ - -/* Bit definition for Ethernet DMA Interrupt Enable Register */ -#define ETH_DMA_IER_NISEN ((uint32_t)0x00010000) /* Normal interrupt summary enable */ -#define ETH_DMA_IER_AISEN ((uint32_t)0x00008000) /* Abnormal interrupt summary enable */ -#define ETH_DMA_IER_ERIEN ((uint32_t)0x00004000) /* Early receive interrupt enable */ -#define ETH_DMA_IER_FBEIEN ((uint32_t)0x00002000) /* Fatal bus error interrupt enable */ -#define ETH_DMA_IER_ETIEN ((uint32_t)0x00000400) /* Early transmit interrupt enable */ -#define ETH_DMA_IER_RWTIEN ((uint32_t)0x00000200) /* Receive watchdog timeout interrupt enable */ -#define ETH_DMA_IER_RPSIEN ((uint32_t)0x00000100) /* Receive process stopped interrupt enable */ -#define ETH_DMA_IER_RBUIEN ((uint32_t)0x00000080) /* Receive buffer unavailable interrupt enable */ -#define ETH_DMA_IER_RIEN ((uint32_t)0x00000040) /* Receive interrupt enable */ -#define ETH_DMA_IER_TUIEN ((uint32_t)0x00000020) /* Transmit Underflow interrupt enable */ -#define ETH_DMA_IER_ROIEN ((uint32_t)0x00000010) /* Receive Overflow interrupt enable */ -#define ETH_DMA_IER_TJTIEN ((uint32_t)0x00000008) /* Transmit jabber timeout interrupt enable */ -#define ETH_DMA_IER_TBUIEN ((uint32_t)0x00000004) /* Transmit buffer unavailable interrupt enable */ -#define ETH_DMA_IER_TPSIEN ((uint32_t)0x00000002) /* Transmit process stopped interrupt enable */ -#define ETH_DMA_IER_TIEN ((uint32_t)0x00000001) /* Transmit interrupt enable */ - -/* Bit definition for Ethernet DMA Missed Frame and Buffer Overflow Counter Register */ -#define ETH_DMA_MFBOCNT_OBFOC ((uint32_t)0x10000000) /* Overflow bit for FIFO overflow counter */ -#define ETH_DMA_MFBOCNT_MSFA ((uint32_t)0x0FFE0000) /* Missed frames by the application */ -#define ETH_DMA_MFBOCNT_OBMFC ((uint32_t)0x00010000) /* Overflow bit for missed frame counter */ -#define ETH_DMA_MFBOCNT_MSFC ((uint32_t)0x0000FFFF) /* missed frames by the controller */ - -/* Bit definition for Ethernet DMA Current Transmit Descriptor Address Register */ -#define ETH_DMA_CTDAR_TDAP ((uint32_t)0xFFFFFFFF) /* Transmit descriptor address pointer */ - -/* Bit definition for Ethernet DMA Current Receive Descriptor Address Register */ -#define ETH_DMA_CRDAR_RDAP ((uint32_t)0xFFFFFFFF) /* Receive descriptor address pointer */ - -/* Bit definition for Ethernet DMA Current Transmit Buffer Address Register */ -#define ETH_DMA_CTBAR_TBAP ((uint32_t)0xFFFFFFFF) /* Transmit buffer address pointer */ - -/* Bit definition for Ethernet DMA Current Receive Buffer Address Register */ -#define ETH_DMA_CRBAR_RBAP ((uint32_t)0xFFFFFFFF) /* Receive buffer address pointer */ -/******************************************************************************/ -/* */ -/* External Memory Controller */ -/* */ -/******************************************************************************/ -/****************** Bit definition for EXMC_SCTLR1 register *******************/ -#define EXMC_SCTLR1_BAKEN ((uint32_t)0x00000001) /*!< Memory bank enable */ -#define EXMC_SCTLR1_MULEN ((uint32_t)0x00000002) /*!< Address/data multiplexing enable */ - -#define EXMC_SCTLR1_EMTYP ((uint32_t)0x0000000C) /*!< EMTYP[1:0] bits (Memory type) */ -#define EXMC_SCTLR1_EMTYP_0 ((uint32_t)0x00000004) /*!< Bit 0 */ -#define EXMC_SCTLR1_EMTYP_1 ((uint32_t)0x00000008) /*!< Bit 1 */ - -#define EXMC_SCTLR1_EMWID ((uint32_t)0x00000030) /*!< EMWID[1:0] bits (Memory data bus width) */ -#define EXMC_SCTLR1_EMWID_0 ((uint32_t)0x00000010) /*!< Bit 0 */ -#define EXMC_SCTLR1_EMWID_1 ((uint32_t)0x00000020) /*!< Bit 1 */ - -#define EXMC_SCTLR1_NOREN ((uint32_t)0x00000040) /*!< NOR Flash access enable */ -#define EXMC_SCTLR1_BMODEN ((uint32_t)0x00000100) /*!< Synchronous burst mode enable */ -#define EXMC_SCTLR1_WSIGP ((uint32_t)0x00000200) /*!< NWAIT signal polarity bit */ -#define EXMC_SCTLR1_WRAPEN ((uint32_t)0x00000400) /*!< Wrapped burst mode enable */ -#define EXMC_SCTLR1_WSIGCFG ((uint32_t)0x00000800) /*!< NWAIT signal timing configuration */ -#define EXMC_SCTLR1_WREN ((uint32_t)0x00001000) /*!< Write enable */ -#define EXMC_SCTLR1_WSIGEN ((uint32_t)0x00002000) /*!< NWAIT signal enable */ -#define EXMC_SCTLR1_EXMODEN ((uint32_t)0x00004000) /*!< Extended mode enable */ -#define EXMC_SCTLR1_ASYNCWAIT ((uint32_t)0x00008000) /*!< Asynchronous wait feature enable */ -#define EXMC_SCTLR1_WRMOD ((uint32_t)0x00080000) /*!< write mode select */ - -/****************** Bit definition for EXMC_SCTLR2 register *******************/ -#define EXMC_SCTLR2_BAKEN ((uint32_t)0x00000001) /*!< Memory bank enable */ -#define EXMC_SCTLR2_MULEN ((uint32_t)0x00000002) /*!< Address/data multiplexing enable */ - -#define EXMC_SCTLR2_EMTYP ((uint32_t)0x0000000C) /*!< EMTYP[1:0] bits (Memory type) */ -#define EXMC_SCTLR2_EMTYP_0 ((uint32_t)0x00000004) /*!< Bit 0 */ -#define EXMC_SCTLR2_EMTYP_1 ((uint32_t)0x00000008) /*!< Bit 1 */ - -#define EXMC_SCTLR2_EMWID ((uint32_t)0x00000030) /*!< EMWID[1:0] bits (Memory data bus width) */ -#define EXMC_SCTLR2_EMWID_0 ((uint32_t)0x00000010) /*!< Bit 0 */ -#define EXMC_SCTLR2_EMWID_1 ((uint32_t)0x00000020) /*!< Bit 1 */ - -#define EXMC_SCTLR2_NOREN ((uint32_t)0x00000040) /*!< NOR Flash access enable */ -#define EXMC_SCTLR2_BMODEN ((uint32_t)0x00000100) /*!< Synchronous burst mode enable */ -#define EXMC_SCTLR2_WSIGP ((uint32_t)0x00000200) /*!< NWAIT signal polarity */ -#define EXMC_SCTLR2_WRAPEN ((uint32_t)0x00000400) /*!< Wrapped burst mode enable */ -#define EXMC_SCTLR2_WSIGCFG ((uint32_t)0x00000800) /*!< NWAIT signal timing configuration */ -#define EXMC_SCTLR2_WREN ((uint32_t)0x00001000) /*!< Write enable */ -#define EXMC_SCTLR2_WSIGEN ((uint32_t)0x00002000) /*!< NWAIT signal enable */ -#define EXMC_SCTLR2_EXMODEN ((uint32_t)0x00004000) /*!< Extended mode enable */ -#define EXMC_SCTLR2_ASYNCWAIT ((uint32_t)0x00008000) /*!< Asynchronous wait feature enable */ -#define EXMC_SCTLR2_WRMOD ((uint32_t)0x00080000) /*!< write mode select */ - -/****************** Bit definition for EXMC_SCTLR3 register *******************/ -#define EXMC_SCTLR3_BAKEN ((uint32_t)0x00000001) /*!< Memory bank enable */ -#define EXMC_SCTLR3_MULEN ((uint32_t)0x00000002) /*!< Address/data multiplexing enable */ - -#define EXMC_SCTLR3_EMTYP ((uint32_t)0x0000000C) /*!< EMTYP[1:0] bits (Memory type) */ -#define EXMC_SCTLR3_EMTYP_0 ((uint32_t)0x00000004) /*!< Bit 0 */ -#define EXMC_SCTLR3_EMTYP_1 ((uint32_t)0x00000008) /*!< Bit 1 */ - -#define EXMC_SCTLR3_EMWID ((uint32_t)0x00000030) /*!< EMWID[1:0] bits (Memory data bus width) */ -#define EXMC_SCTLR3_EMWID_0 ((uint32_t)0x00000010) /*!< Bit 0 */ -#define EXMC_SCTLR3_EMWID_1 ((uint32_t)0x00000020) /*!< Bit 1 */ - -#define EXMC_SCTLR3_NOREN ((uint32_t)0x00000040) /*!< NOR Flash access enable */ -#define EXMC_SCTLR3_BMODEN ((uint32_t)0x00000100) /*!< Synchronous burst mode enable */ -#define EXMC_SCTLR3_WSIGP ((uint32_t)0x00000200) /*!< NWAIT signal polarity */ -#define EXMC_SCTLR3_WRAPEN ((uint32_t)0x00000400) /*!< Wrapped burst mode enable */ -#define EXMC_SCTLR3_WSIGCFG ((uint32_t)0x00000800) /*!< NWAIT signal timing configuration */ -#define EXMC_SCTLR3_WREN ((uint32_t)0x00001000) /*!< Write enable */ -#define EXMC_SCTLR3_WSIGEN ((uint32_t)0x00002000) /*!< NWAIT signal enable */ -#define EXMC_SCTLR3_EXMODEN ((uint32_t)0x00004000) /*!< Extended mode enable */ -#define EXMC_SCTLR3_ASYNCWAIT ((uint32_t)0x00008000) /*!< Asynchronous wait feature enable */ -#define EXMC_SCTLR3_WRMOD ((uint32_t)0x00080000) /*!< write mode select */ - -/****************** Bit definition for EXMC_SCTLR4 register *******************/ -#define EXMC_SCTLR4_BAKEN ((uint32_t)0x00000001) /*!< Memory bank enable */ -#define EXMC_SCTLR4_MULEN ((uint32_t)0x00000002) /*!< Address/data multiplexing enable */ - -#define EXMC_SCTLR4_EMTYP ((uint32_t)0x0000000C) /*!< EMTYP[1:0] bits (Memory type) */ -#define EXMC_SCTLR4_EMTYP_0 ((uint32_t)0x00000004) /*!< Bit 0 */ -#define EXMC_SCTLR4_EMTYP_1 ((uint32_t)0x00000008) /*!< Bit 1 */ - -#define EXMC_SCTLR4_EMWID ((uint32_t)0x00000030) /*!< EMWID[1:0] bits (Memory data bus width) */ -#define EXMC_SCTLR4_EMWID_0 ((uint32_t)0x00000010) /*!< Bit 0 */ -#define EXMC_SCTLR4_EMWID_1 ((uint32_t)0x00000020) /*!< Bit 1 */ - -#define EXMC_SCTLR4_NOREN ((uint32_t)0x00000040) /*!< NOR Flash access enable */ -#define EXMC_SCTLR4_BMODEN ((uint32_t)0x00000100) /*!< Synchronous burst mode enable */ -#define EXMC_SCTLR4_WSIGP ((uint32_t)0x00000200) /*!< NWAIT signal polarity */ -#define EXMC_SCTLR4_WRAPEN ((uint32_t)0x00000400) /*!< Wrapped burst mode enable */ -#define EXMC_SCTLR4_WSIGCFG ((uint32_t)0x00000800) /*!< NWAIT signal timing configuration */ -#define EXMC_SCTLR4_WREN ((uint32_t)0x00001000) /*!< Write enable */ -#define EXMC_SCTLR4_WSIGEN ((uint32_t)0x00002000) /*!< NWAIT signal enable */ -#define EXMC_SCTLR4_EXMODEN ((uint32_t)0x00004000) /*!< Extended mode enable */ -#define EXMC_SCTLR4_ASYNCWAIT ((uint32_t)0x00008000) /*!< Asynchronous wait feature enable */ -#define EXMC_SCTLR4_WRMOD ((uint32_t)0x00080000) /*!< write mode select */ - -/****************** Bit definition for EXMC_STR1 register ******************/ -#define EXMC_STR1_AST ((uint32_t)0x0000000F) /*!< AST[3:0] bits (Address setup time) */ -#define EXMC_STR1_AST_0 ((uint32_t)0x00000001) /*!< Bit 0 */ -#define EXMC_STR1_AST_1 ((uint32_t)0x00000002) /*!< Bit 1 */ -#define EXMC_STR1_AST_2 ((uint32_t)0x00000004) /*!< Bit 2 */ -#define EXMC_STR1_AST_3 ((uint32_t)0x00000008) /*!< Bit 3 */ - -#define EXMC_STR1_AHT ((uint32_t)0x000000F0) /*!< AHT[3:0] bits (Address hold time) */ -#define EXMC_STR1_AHT_0 ((uint32_t)0x00000010) /*!< Bit 0 */ -#define EXMC_STR1_AHT_1 ((uint32_t)0x00000020) /*!< Bit 1 */ -#define EXMC_STR1_AHT_2 ((uint32_t)0x00000040) /*!< Bit 2 */ -#define EXMC_STR1_AHT_3 ((uint32_t)0x00000080) /*!< Bit 3 */ - -#define EXMC_STR1_DST ((uint32_t)0x0000FF00) /*!< DST [3:0] bits (Data setup time) */ -#define EXMC_STR1_DST_0 ((uint32_t)0x00000100) /*!< Bit 0 */ -#define EXMC_STR1_DST_1 ((uint32_t)0x00000200) /*!< Bit 1 */ -#define EXMC_STR1_DST_2 ((uint32_t)0x00000400) /*!< Bit 2 */ -#define EXMC_STR1_DST_3 ((uint32_t)0x00000800) /*!< Bit 3 */ - -#define EXMC_STR1_BUSLAT ((uint32_t)0x000F0000) /*!< BUSLAT[3:0] bits (Bus latency) */ -#define EXMC_STR1_BUSLAT_0 ((uint32_t)0x00010000) /*!< Bit 0 */ -#define EXMC_STR1_BUSLAT_1 ((uint32_t)0x00020000) /*!< Bit 1 */ -#define EXMC_STR1_BUSLAT_2 ((uint32_t)0x00040000) /*!< Bit 2 */ -#define EXMC_STR1_BUSLAT_3 ((uint32_t)0x00080000) /*!< Bit 3 */ - -#define EXMC_STR1_CDIV ((uint32_t)0x00F00000) /*!< CDIV[3:0] bits (Synchronous clock divide ratio) */ -#define EXMC_STR1_CDIV_0 ((uint32_t)0x00100000) /*!< Bit 0 */ -#define EXMC_STR1_CDIV_1 ((uint32_t)0x00200000) /*!< Bit 1 */ -#define EXMC_STR1_CDIV_2 ((uint32_t)0x00400000) /*!< Bit 2 */ -#define EXMC_STR1_CDIV_3 ((uint32_t)0x00800000) /*!< Bit 3 */ - -#define EXMC_STR1_DLAT ((uint32_t)0x0F000000) /*!< DLAT[3:0] bits (Data latency for nor flash) */ -#define EXMC_STR1_DLAT_0 ((uint32_t)0x01000000) /*!< Bit 0 */ -#define EXMC_STR1_DLAT_1 ((uint32_t)0x02000000) /*!< Bit 1 */ -#define EXMC_STR1_DLAT_2 ((uint32_t)0x04000000) /*!< Bit 2 */ -#define EXMC_STR1_DLAT_3 ((uint32_t)0x08000000) /*!< Bit 3 */ - -#define EXMC_STR1_ASYNMOD ((uint32_t)0x30000000) /*!< ASYNMOD[1:0] bits (Asynchronous access mode) */ -#define EXMC_STR1_ASYNMOD_0 ((uint32_t)0x10000000) /*!< Bit 0 */ -#define EXMC_STR1_ASYNMOD_1 ((uint32_t)0x20000000) /*!< Bit 1 */ - -/****************** Bit definition for EXMC_STR2 register *******************/ -#define EXMC_STR2_AST ((uint32_t)0x0000000F) /*!< AST[3:0] bits (Address setup time) */ -#define EXMC_STR2_AST_0 ((uint32_t)0x00000001) /*!< Bit 0 */ -#define EXMC_STR2_AST_1 ((uint32_t)0x00000002) /*!< Bit 1 */ -#define EXMC_STR2_AST_2 ((uint32_t)0x00000004) /*!< Bit 2 */ -#define EXMC_STR2_AST_3 ((uint32_t)0x00000008) /*!< Bit 3 */ - -#define EXMC_STR2_AHT ((uint32_t)0x000000F0) /*!< AHT[3:0] bits (Address hold time) */ -#define EXMC_STR2_AHT_0 ((uint32_t)0x00000010) /*!< Bit 0 */ -#define EXMC_STR2_AHT_1 ((uint32_t)0x00000020) /*!< Bit 1 */ -#define EXMC_STR2_AHT_2 ((uint32_t)0x00000040) /*!< Bit 2 */ -#define EXMC_STR2_AHT_3 ((uint32_t)0x00000080) /*!< Bit 3 */ - -#define EXMC_STR2_DST ((uint32_t)0x0000FF00) /*!< DST [3:0] bits (Data setup time) */ -#define EXMC_STR2_DST_0 ((uint32_t)0x00000100) /*!< Bit 0 */ -#define EXMC_STR2_DST_1 ((uint32_t)0x00000200) /*!< Bit 1 */ -#define EXMC_STR2_DST_2 ((uint32_t)0x00000400) /*!< Bit 2 */ -#define EXMC_STR2_DST_3 ((uint32_t)0x00000800) /*!< Bit 3 */ - -#define EXMC_STR2_BUSLAT ((uint32_t)0x000F0000) /*!< BUSLAT[3:0] bits (Bus latency) */ -#define EXMC_STR2_BUSLAT_0 ((uint32_t)0x00010000) /*!< Bit 0 */ -#define EXMC_STR2_BUSLAT_1 ((uint32_t)0x00020000) /*!< Bit 1 */ -#define EXMC_STR2_BUSLAT_2 ((uint32_t)0x00040000) /*!< Bit 2 */ -#define EXMC_STR2_BUSLAT_3 ((uint32_t)0x00080000) /*!< Bit 3 */ - -#define EXMC_STR2_CDIV ((uint32_t)0x00F00000) /*!< CDIV[3:0] bits (Synchronous clock divide ratio) */ -#define EXMC_STR2_CDIV_0 ((uint32_t)0x00100000) /*!< Bit 0 */ -#define EXMC_STR2_CDIV_1 ((uint32_t)0x00200000) /*!< Bit 1 */ -#define EXMC_STR2_CDIV_2 ((uint32_t)0x00400000) /*!< Bit 2 */ -#define EXMC_STR2_CDIV_3 ((uint32_t)0x00800000) /*!< Bit 3 */ - -#define EXMC_STR2_DLAT ((uint32_t)0x0F000000) /*!< DLAT[3:0] bits (Data latency for nor flash) */ -#define EXMC_STR2_DLAT_0 ((uint32_t)0x01000000) /*!< Bit 0 */ -#define EXMC_STR2_DLAT_1 ((uint32_t)0x02000000) /*!< Bit 1 */ -#define EXMC_STR2_DLAT_2 ((uint32_t)0x04000000) /*!< Bit 2 */ -#define EXMC_STR2_DLAT_3 ((uint32_t)0x08000000) /*!< Bit 3 */ - -#define EXMC_STR2_ASYNMOD ((uint32_t)0x30000000) /*!< ASYNMOD[1:0] bits (Asynchronous access mode) */ -#define EXMC_STR2_ASYNMOD_0 ((uint32_t)0x10000000) /*!< Bit 0 */ -#define EXMC_STR2_ASYNMOD_1 ((uint32_t)0x20000000) /*!< Bit 1 */ - -/******************* Bit definition for EXMC_STR3 register *******************/ -#define EXMC_STR3_AST ((uint32_t)0x0000000F) /*!< AST[3:0] bits (Address setup time) */ -#define EXMC_STR3_AST_0 ((uint32_t)0x00000001) /*!< Bit 0 */ -#define EXMC_STR3_AST_1 ((uint32_t)0x00000002) /*!< Bit 1 */ -#define EXMC_STR3_AST_2 ((uint32_t)0x00000004) /*!< Bit 2 */ -#define EXMC_STR3_AST_3 ((uint32_t)0x00000008) /*!< Bit 3 */ - -#define EXMC_STR3_AHT ((uint32_t)0x000000F0) /*!< AHT[3:0] bits (Address hold time) */ -#define EXMC_STR3_AHT_0 ((uint32_t)0x00000010) /*!< Bit 0 */ -#define EXMC_STR3_AHT_1 ((uint32_t)0x00000020) /*!< Bit 1 */ -#define EXMC_STR3_AHT_2 ((uint32_t)0x00000040) /*!< Bit 2 */ -#define EXMC_STR3_AHT_3 ((uint32_t)0x00000080) /*!< Bit 3 */ - -#define EXMC_STR3_DST ((uint32_t)0x0000FF00) /*!< DST [3:0] bits (Data setup time) */ -#define EXMC_STR3_DST_0 ((uint32_t)0x00000100) /*!< Bit 0 */ -#define EXMC_STR3_DST_1 ((uint32_t)0x00000200) /*!< Bit 1 */ -#define EXMC_STR3_DST_2 ((uint32_t)0x00000400) /*!< Bit 2 */ -#define EXMC_STR3_DST_3 ((uint32_t)0x00000800) /*!< Bit 3 */ - -#define EXMC_STR3_BUSLAT ((uint32_t)0x000F0000) /*!< BUSLAT[3:0] bits (Bus latency) */ -#define EXMC_STR3_BUSLAT_0 ((uint32_t)0x00010000) /*!< Bit 0 */ -#define EXMC_STR3_BUSLAT_1 ((uint32_t)0x00020000) /*!< Bit 1 */ -#define EXMC_STR3_BUSLAT_2 ((uint32_t)0x00040000) /*!< Bit 2 */ -#define EXMC_STR3_BUSLAT_3 ((uint32_t)0x00080000) /*!< Bit 3 */ - -#define EXMC_STR3_CDIV ((uint32_t)0x00F00000) /*!< CDIV[3:0] bits (Synchronous clock divide ratio) */ -#define EXMC_STR3_CDIV_0 ((uint32_t)0x00100000) /*!< Bit 0 */ -#define EXMC_STR3_CDIV_1 ((uint32_t)0x00200000) /*!< Bit 1 */ -#define EXMC_STR3_CDIV_2 ((uint32_t)0x00400000) /*!< Bit 2 */ -#define EXMC_STR3_CDIV_3 ((uint32_t)0x00800000) /*!< Bit 3 */ - -#define EXMC_STR3_DLAT ((uint32_t)0x0F000000) /*!< DLAT[3:0] bits (Data latency for nor flash) */ -#define EXMC_STR3_DLAT_0 ((uint32_t)0x01000000) /*!< Bit 0 */ -#define EXMC_STR3_DLAT_1 ((uint32_t)0x02000000) /*!< Bit 1 */ -#define EXMC_STR3_DLAT_2 ((uint32_t)0x04000000) /*!< Bit 2 */ -#define EXMC_STR3_DLAT_3 ((uint32_t)0x08000000) /*!< Bit 3 */ - -#define EXMC_STR3_ASYNMOD ((uint32_t)0x30000000) /*!< ASYNMOD[1:0] bits (Asynchronous access mode) */ -#define EXMC_STR3_ASYNMOD_0 ((uint32_t)0x10000000) /*!< Bit 0 */ -#define EXMC_STR3_ASYNMOD_1 ((uint32_t)0x20000000) /*!< Bit 1 */ - -/****************** Bit definition for EXMC_STR4 register *******************/ -#define EXMC_STR4_AST ((uint32_t)0x0000000F) /*!< AST[3:0] bits (Address setup time) */ -#define EXMC_STR4_AST_0 ((uint32_t)0x00000001) /*!< Bit 0 */ -#define EXMC_STR4_AST_1 ((uint32_t)0x00000002) /*!< Bit 1 */ -#define EXMC_STR4_AST_2 ((uint32_t)0x00000004) /*!< Bit 2 */ -#define EXMC_STR4_AST_3 ((uint32_t)0x00000008) /*!< Bit 3 */ - -#define EXMC_STR4_AHT ((uint32_t)0x000000F0) /*!< AHT[3:0] bits (Address hold time) */ -#define EXMC_STR4_AHT_0 ((uint32_t)0x00000010) /*!< Bit 0 */ -#define EXMC_STR4_AHT_1 ((uint32_t)0x00000020) /*!< Bit 1 */ -#define EXMC_STR4_AHT_2 ((uint32_t)0x00000040) /*!< Bit 2 */ -#define EXMC_STR4_AHT_3 ((uint32_t)0x00000080) /*!< Bit 3 */ - -#define EXMC_STR4_DST ((uint32_t)0x0000FF00) /*!< DST [3:0] bits (Data setup time) */ -#define EXMC_STR4_DST_0 ((uint32_t)0x00000100) /*!< Bit 0 */ -#define EXMC_STR4_DST_1 ((uint32_t)0x00000200) /*!< Bit 1 */ -#define EXMC_STR4_DST_2 ((uint32_t)0x00000400) /*!< Bit 2 */ -#define EXMC_STR4_DST_3 ((uint32_t)0x00000800) /*!< Bit 3 */ - -#define EXMC_STR4_BUSLAT ((uint32_t)0x000F0000) /*!< BUSLAT[3:0] bits (Bus latency) */ -#define EXMC_STR4_BUSLAT_0 ((uint32_t)0x00010000) /*!< Bit 0 */ -#define EXMC_STR4_BUSLAT_1 ((uint32_t)0x00020000) /*!< Bit 1 */ -#define EXMC_STR4_BUSLAT_2 ((uint32_t)0x00040000) /*!< Bit 2 */ -#define EXMC_STR4_BUSLAT_3 ((uint32_t)0x00080000) /*!< Bit 3 */ - -#define EXMC_STR4_CDIV ((uint32_t)0x00F00000) /*!< CDIV[3:0] bits (Synchronous clock divide ratio) */ -#define EXMC_STR4_CDIV_0 ((uint32_t)0x00100000) /*!< Bit 0 */ -#define EXMC_STR4_CDIV_1 ((uint32_t)0x00200000) /*!< Bit 1 */ -#define EXMC_STR4_CDIV_2 ((uint32_t)0x00400000) /*!< Bit 2 */ -#define EXMC_STR4_CDIV_3 ((uint32_t)0x00800000) /*!< Bit 3 */ - -#define EXMC_STR4_DLAT ((uint32_t)0x0F000000) /*!< DLAT[3:0] bits (Data latency for nor flash) */ -#define EXMC_STR4_DLAT_0 ((uint32_t)0x01000000) /*!< Bit 0 */ -#define EXMC_STR4_DLAT_1 ((uint32_t)0x02000000) /*!< Bit 1 */ -#define EXMC_STR4_DLAT_2 ((uint32_t)0x04000000) /*!< Bit 2 */ -#define EXMC_STR4_DLAT_3 ((uint32_t)0x08000000) /*!< Bit 3 */ - -#define EXMC_STR4_ASYNMOD ((uint32_t)0x30000000) /*!< ASYNMOD[1:0] bits (Asynchronous access mode) */ -#define EXMC_STR4_ASYNMOD_0 ((uint32_t)0x10000000) /*!< Bit 0 */ -#define EXMC_STR4_ASYNMOD_1 ((uint32_t)0x20000000) /*!< Bit 1 */ - -/****************** Bit definition for EXMC_SWTR1 register ******************/ -#define EXMC_SWTR1_AST ((uint32_t)0x0000000F) /*!< AST[3:0] bits (Address setup time) */ -#define EXMC_SWTR1_AST_0 ((uint32_t)0x00000001) /*!< Bit 0 */ -#define EXMC_SWTR1_AST_1 ((uint32_t)0x00000002) /*!< Bit 1 */ -#define EXMC_SWTR1_AST_2 ((uint32_t)0x00000004) /*!< Bit 2 */ -#define EXMC_SWTR1_AST_3 ((uint32_t)0x00000008) /*!< Bit 3 */ - -#define EXMC_SWTR1_AHT ((uint32_t)0x000000F0) /*!< AHT[3:0] bits (Address hold time) */ -#define EXMC_SWTR1_AHT_0 ((uint32_t)0x00000010) /*!< Bit 0 */ -#define EXMC_SWTR1_AHT_1 ((uint32_t)0x00000020) /*!< Bit 1 */ -#define EXMC_SWTR1_AHT_2 ((uint32_t)0x00000040) /*!< Bit 2 */ -#define EXMC_SWTR1_AHT_3 ((uint32_t)0x00000080) /*!< Bit 3 */ - -#define EXMC_SWTR1_DST ((uint32_t)0x0000FF00) /*!< DST [3:0] bits (Data setup time) */ -#define EXMC_SWTR1_DST_0 ((uint32_t)0x00000100) /*!< Bit 0 */ -#define EXMC_SWTR1_DST_1 ((uint32_t)0x00000200) /*!< Bit 1 */ -#define EXMC_SWTR1_DST_2 ((uint32_t)0x00000400) /*!< Bit 2 */ -#define EXMC_SWTR1_DST_3 ((uint32_t)0x00000800) /*!< Bit 3 */ - -#define EXMC_SWTR1_CDIV ((uint32_t)0x00F00000) /*!< CDIV[3:0] bits (Synchronous clock divide ratio) */ -#define EXMC_SWTR1_CDIV_0 ((uint32_t)0x00100000) /*!< Bit 0 */ -#define EXMC_SWTR1_CDIV_1 ((uint32_t)0x00200000) /*!< Bit 1 */ -#define EXMC_SWTR1_CDIV_2 ((uint32_t)0x00400000) /*!< Bit 2 */ -#define EXMC_SWTR1_CDIV_3 ((uint32_t)0x00800000) /*!< Bit 3 */ - -#define EXMC_SWTR1_DLAT ((uint32_t)0x0F000000) /*!< DLAT[3:0] bits (Data latency for nor flash) */ -#define EXMC_SWTR1_DLAT_0 ((uint32_t)0x01000000) /*!< Bit 0 */ -#define EXMC_SWTR1_DLAT_1 ((uint32_t)0x02000000) /*!< Bit 1 */ -#define EXMC_SWTR1_DLAT_2 ((uint32_t)0x04000000) /*!< Bit 2 */ -#define EXMC_SWTR1_DLAT_3 ((uint32_t)0x08000000) /*!< Bit 3 */ - -#define EXMC_SWTR1_ASYNMOD ((uint32_t)0x30000000) /*!< ASYNMOD[1:0] bits (Asynchronous access mode) */ -#define EXMC_SWTR1_ASYNMOD_0 ((uint32_t)0x10000000) /*!< Bit 0 */ -#define EXMC_SWTR1_ASYNMOD_1 ((uint32_t)0x20000000) /*!< Bit 1 */ - -/****************** Bit definition for EXMC_SWTR2 register ******************/ -#define EXMC_SWTR2_AST ((uint32_t)0x0000000F) /*!< AST[3:0] bits (Address setup time) */ -#define EXMC_SWTR2_AST_0 ((uint32_t)0x00000001) /*!< Bit 0 */ -#define EXMC_SWTR2_AST_1 ((uint32_t)0x00000002) /*!< Bit 1 */ -#define EXMC_SWTR2_AST_2 ((uint32_t)0x00000004) /*!< Bit 2 */ -#define EXMC_SWTR2_AST_3 ((uint32_t)0x00000008) /*!< Bit 3 */ - -#define EXMC_SWTR2_AHT ((uint32_t)0x000000F0) /*!< AHT[3:0] bits (Address hold time) */ -#define EXMC_SWTR2_AHT_0 ((uint32_t)0x00000010) /*!< Bit 0 */ -#define EXMC_SWTR2_AHT_1 ((uint32_t)0x00000020) /*!< Bit 1 */ -#define EXMC_SWTR2_AHT_2 ((uint32_t)0x00000040) /*!< Bit 2 */ -#define EXMC_SWTR2_AHT_3 ((uint32_t)0x00000080) /*!< Bit 3 */ - -#define EXMC_SWTR2_DST ((uint32_t)0x0000FF00) /*!< DST [3:0] bits (Data setup time) */ -#define EXMC_SWTR2_DST_0 ((uint32_t)0x00000100) /*!< Bit 0 */ -#define EXMC_SWTR2_DST_1 ((uint32_t)0x00000200) /*!< Bit 1 */ -#define EXMC_SWTR2_DST_2 ((uint32_t)0x00000400) /*!< Bit 2 */ -#define EXMC_SWTR2_DST_3 ((uint32_t)0x00000800) /*!< Bit 3 */ - -#define EXMC_SWTR2_CDIV ((uint32_t)0x00F00000) /*!< CDIV[3:0] bits (Synchronous clock divide ratio) */ -#define EXMC_SWTR2_CDIV_0 ((uint32_t)0x00100000) /*!< Bit 0 */ -#define EXMC_SWTR2_CDIV_1 ((uint32_t)0x00200000) /*!< Bit 1 */ -#define EXMC_SWTR2_CDIV_2 ((uint32_t)0x00400000) /*!< Bit 2 */ -#define EXMC_SWTR2_CDIV_3 ((uint32_t)0x00800000) /*!< Bit 3 */ - -#define EXMC_SWTR2_DLAT ((uint32_t)0x0F000000) /*!< DLAT[3:0] bits (Data latency for nor flash) */ -#define EXMC_SWTR2_DLAT_0 ((uint32_t)0x01000000) /*!< Bit 0 */ -#define EXMC_SWTR2_DLAT_1 ((uint32_t)0x02000000) /*!< Bit 1 */ -#define EXMC_SWTR2_DLAT_2 ((uint32_t)0x04000000) /*!< Bit 2 */ -#define EXMC_SWTR2_DLAT_3 ((uint32_t)0x08000000) /*!< Bit 3 */ - -#define EXMC_SWTR2_ASYNMOD ((uint32_t)0x30000000) /*!< ASYNMOD[1:0] bits (Asynchronous access mode) */ -#define EXMC_SWTR2_ASYNMOD_0 ((uint32_t)0x10000000) /*!< Bit 0 */ -#define EXMC_SWTR2_ASYNMOD_1 ((uint32_t)0x20000000) /*!< Bit 1 */ - -/****************** Bit definition for EXMC_SWTR3 register ******************/ -#define EXMC_SWTR3_AST ((uint32_t)0x0000000F) /*!< AST[3:0] bits (Address setup time) */ -#define EXMC_SWTR3_AST_0 ((uint32_t)0x00000001) /*!< Bit 0 */ -#define EXMC_SWTR3_AST_1 ((uint32_t)0x00000002) /*!< Bit 1 */ -#define EXMC_SWTR3_AST_2 ((uint32_t)0x00000004) /*!< Bit 2 */ -#define EXMC_SWTR3_AST_3 ((uint32_t)0x00000008) /*!< Bit 3 */ - -#define EXMC_SWTR3_AHT ((uint32_t)0x000000F0) /*!< AHT[3:0] bits (Address hold time) */ -#define EXMC_SWTR3_AHT_0 ((uint32_t)0x00000010) /*!< Bit 0 */ -#define EXMC_SWTR3_AHT_1 ((uint32_t)0x00000020) /*!< Bit 1 */ -#define EXMC_SWTR3_AHT_2 ((uint32_t)0x00000040) /*!< Bit 2 */ -#define EXMC_SWTR3_AHT_3 ((uint32_t)0x00000080) /*!< Bit 3 */ - -#define EXMC_SWTR3_DST ((uint32_t)0x0000FF00) /*!< DST [3:0] bits (Data setup time) */ -#define EXMC_SWTR3_DST_0 ((uint32_t)0x00000100) /*!< Bit 0 */ -#define EXMC_SWTR3_DST_1 ((uint32_t)0x00000200) /*!< Bit 1 */ -#define EXMC_SWTR3_DST_2 ((uint32_t)0x00000400) /*!< Bit 2 */ -#define EXMC_SWTR3_DST_3 ((uint32_t)0x00000800) /*!< Bit 3 */ - -#define EXMC_SWTR3_CDIV ((uint32_t)0x00F00000) /*!< CDIV[3:0] bits (Synchronous clock divide ratio) */ -#define EXMC_SWTR3_CDIV_0 ((uint32_t)0x00100000) /*!< Bit 0 */ -#define EXMC_SWTR3_CDIV_1 ((uint32_t)0x00200000) /*!< Bit 1 */ -#define EXMC_SWTR3_CDIV_2 ((uint32_t)0x00400000) /*!< Bit 2 */ -#define EXMC_SWTR3_CDIV_3 ((uint32_t)0x00800000) /*!< Bit 3 */ - -#define EXMC_SWTR3_DLAT ((uint32_t)0x0F000000) /*!< DLAT[3:0] bits (Data latency for nor flash) */ -#define EXMC_SWTR3_DLAT_0 ((uint32_t)0x01000000) /*!< Bit 0 */ -#define EXMC_SWTR3_DLAT_1 ((uint32_t)0x02000000) /*!< Bit 1 */ -#define EXMC_SWTR3_DLAT_2 ((uint32_t)0x04000000) /*!< Bit 2 */ -#define EXMC_SWTR3_DLAT_3 ((uint32_t)0x08000000) /*!< Bit 3 */ - -#define EXMC_SWTR3_ASYNMOD ((uint32_t)0x30000000) /*!< ASYNMOD[1:0] bits (Asynchronous access mode) */ -#define EXMC_SWTR3_ASYNMOD_0 ((uint32_t)0x10000000) /*!< Bit 0 */ -#define EXMC_SWTR3_ASYNMOD_1 ((uint32_t)0x20000000) /*!< Bit 1 */ - -/****************** Bit definition for EXMC_SWTR4 register ******************/ -#define EXMC_SWTR4_AST ((uint32_t)0x0000000F) /*!< AST[3:0] bits (Address setup time) */ -#define EXMC_SWTR4_AST_0 ((uint32_t)0x00000001) /*!< Bit 0 */ -#define EXMC_SWTR4_AST_1 ((uint32_t)0x00000002) /*!< Bit 1 */ -#define EXMC_SWTR4_AST_2 ((uint32_t)0x00000004) /*!< Bit 2 */ -#define EXMC_SWTR4_AST_3 ((uint32_t)0x00000008) /*!< Bit 3 */ - -#define EXMC_SWTR4_AHT ((uint32_t)0x000000F0) /*!< AHT[3:0] bits (Address hold time) */ -#define EXMC_SWTR4_AHT_0 ((uint32_t)0x00000010) /*!< Bit 0 */ -#define EXMC_SWTR4_AHT_1 ((uint32_t)0x00000020) /*!< Bit 1 */ -#define EXMC_SWTR4_AHT_2 ((uint32_t)0x00000040) /*!< Bit 2 */ -#define EXMC_SWTR4_AHT_3 ((uint32_t)0x00000080) /*!< Bit 3 */ - -#define EXMC_SWTR4_DST ((uint32_t)0x0000FF00) /*!< DST [3:0] bits (Data setup time) */ -#define EXMC_SWTR4_DST_0 ((uint32_t)0x00000100) /*!< Bit 0 */ -#define EXMC_SWTR4_DST_1 ((uint32_t)0x00000200) /*!< Bit 1 */ -#define EXMC_SWTR4_DST_2 ((uint32_t)0x00000400) /*!< Bit 2 */ -#define EXMC_SWTR4_DST_3 ((uint32_t)0x00000800) /*!< Bit 3 */ - -#define EXMC_SWTR4_CDIV ((uint32_t)0x00F00000) /*!< CDIV[3:0] bits (Synchronous clock divide ratio) */ -#define EXMC_SWTR4_CDIV_0 ((uint32_t)0x00100000) /*!< Bit 0 */ -#define EXMC_SWTR4_CDIV_1 ((uint32_t)0x00200000) /*!< Bit 1 */ -#define EXMC_SWTR4_CDIV_2 ((uint32_t)0x00400000) /*!< Bit 2 */ -#define EXMC_SWTR4_CDIV_3 ((uint32_t)0x00800000) /*!< Bit 3 */ - -#define EXMC_SWTR4_DLAT ((uint32_t)0x0F000000) /*!< DLAT[3:0] bits (Data latency for nor flash) */ -#define EXMC_SWTR4_DLAT_0 ((uint32_t)0x01000000) /*!< Bit 0 */ -#define EXMC_SWTR4_DLAT_1 ((uint32_t)0x02000000) /*!< Bit 1 */ -#define EXMC_SWTR4_DLAT_2 ((uint32_t)0x04000000) /*!< Bit 2 */ -#define EXMC_SWTR4_DLAT_3 ((uint32_t)0x08000000) /*!< Bit 3 */ - -#define EXMC_SWTR4_ASYNMOD ((uint32_t)0x30000000) /*!< ASYNMOD[1:0] bits (Asynchronous access mode) */ -#define EXMC_SWTR4_ASYNMOD_0 ((uint32_t)0x10000000) /*!< Bit 0 */ -#define EXMC_SWTR4_ASYNMOD_1 ((uint32_t)0x20000000) /*!< Bit 1 */ - -/****************** Bit definition for EXMC_CTLR2 register *******************/ -#define EXMC_CTLR2_WSIGEN ((uint32_t)0x00000002) /*!< Wait feature enable */ -#define EXMC_CTLR2_BAKEN ((uint32_t)0x00000004) /*!< Memory bank enable */ -#define EXMC_CTLR2_EMTYP ((uint32_t)0x00000008) /*!< Memory type */ - -#define EXMC_CTLR2_EMWID ((uint32_t)0x00000030) /*!< EMWID[1:0] bits (external memory databus width) */ -#define EXMC_CTLR2_EMWID_0 ((uint32_t)0x00000010) /*!< Bit 0 */ -#define EXMC_CTLR2_EMWID_1 ((uint32_t)0x00000020) /*!< Bit 1 */ - -#define EXMC_CTLR2_ECCEN ((uint32_t)0x00000040) /*!< ECC enable */ - -#define EXMC_CTLR2_CTR ((uint32_t)0x00001E00) /*!< CTR[3:0] bits (CLE to RE delay) */ -#define EXMC_CTLR2_CTR_0 ((uint32_t)0x00000200) /*!< Bit 0 */ -#define EXMC_CTLR2_CTR_1 ((uint32_t)0x00000400) /*!< Bit 1 */ -#define EXMC_CTLR2_CTR_2 ((uint32_t)0x00000800) /*!< Bit 2 */ -#define EXMC_CTLR2_CTR_3 ((uint32_t)0x00001000) /*!< Bit 3 */ - -#define EXMC_CTLR2_ATR ((uint32_t)0x0001E000) /*!< ATR[3:0] bits (ALE to RE delay) */ -#define EXMC_CTLR2_ATR_0 ((uint32_t)0x00002000) /*!< Bit 0 */ -#define EXMC_CTLR2_ATR_1 ((uint32_t)0x00004000) /*!< Bit 1 */ -#define EXMC_CTLR2_ATR_2 ((uint32_t)0x00008000) /*!< Bit 2 */ -#define EXMC_CTLR2_ATR_3 ((uint32_t)0x00010000) /*!< Bit 3 */ - -#define EXMC_CTLR2_ECCSZ ((uint32_t)0x000E0000) /*!< ECCSZ[1:0] bits (ECC size) */ -#define EXMC_CTLR2_ECCSZ_0 ((uint32_t)0x00020000) /*!< Bit 0 */ -#define EXMC_CTLR2_ECCSZ_1 ((uint32_t)0x00040000) /*!< Bit 1 */ -#define EXMC_CTLR2_ECCSZ_2 ((uint32_t)0x00080000) /*!< Bit 2 */ - -/****************** Bit definition for EXMC_CTLR3 register *******************/ -#define EXMC_CTLR3_WSIGEN ((uint32_t)0x00000002) /*!< Wait feature enable */ -#define EXMC_CTLR3_BAKEN ((uint32_t)0x00000004) /*!< Memory bank enable */ -#define EXMC_CTLR3_EMTYP ((uint32_t)0x00000008) /*!< Memory type */ - -#define EXMC_CTLR3_EMWID ((uint32_t)0x00000030) /*!< EMWID[1:0] bits (external memory databus width) */ -#define EXMC_CTLR3_EMWID_0 ((uint32_t)0x00000010) /*!< Bit 0 */ -#define EXMC_CTLR3_EMWID_1 ((uint32_t)0x00000020) /*!< Bit 1 */ - -#define EXMC_CTLR3_ECCEN ((uint32_t)0x00000040) /*!< ECC enable */ - -#define EXMC_CTLR3_CTR ((uint32_t)0x00001E00) /*!< CTR[3:0] bits (CLE to RE delay) */ -#define EXMC_CTLR3_CTR_0 ((uint32_t)0x00000200) /*!< Bit 0 */ -#define EXMC_CTLR3_CTR_1 ((uint32_t)0x00000400) /*!< Bit 1 */ -#define EXMC_CTLR3_CTR_2 ((uint32_t)0x00000800) /*!< Bit 2 */ -#define EXMC_CTLR3_CTR_3 ((uint32_t)0x00001000) /*!< Bit 3 */ - -#define EXMC_CTLR3_ATR ((uint32_t)0x0001E000) /*!< ATR[3:0] bits (ALE to RE delay) */ -#define EXMC_CTLR3_ATR_0 ((uint32_t)0x00002000) /*!< Bit 0 */ -#define EXMC_CTLR3_ATR_1 ((uint32_t)0x00004000) /*!< Bit 1 */ -#define EXMC_CTLR3_ATR_2 ((uint32_t)0x00008000) /*!< Bit 2 */ -#define EXMC_CTLR3_ATR_3 ((uint32_t)0x00010000) /*!< Bit 3 */ - -#define EXMC_CTLR3_ECCSZ ((uint32_t)0x000E0000) /*!< ECCSZ[1:0] bits (ECC size) */ -#define EXMC_CTLR3_ECCSZ_0 ((uint32_t)0x00020000) /*!< Bit 0 */ -#define EXMC_CTLR3_ECCSZ_1 ((uint32_t)0x00040000) /*!< Bit 1 */ -#define EXMC_CTLR3_ECCSZ_2 ((uint32_t)0x00080000) /*!< Bit 2 */ - -/****************** Bit definition for EXMC_CTLR4 register *******************/ -#define EXMC_CTLR4_WSIGEN ((uint32_t)0x00000002) /*!< Wait feature enable */ -#define EXMC_CTLR4_BAKEN ((uint32_t)0x00000004) /*!< Memory bank enable */ -#define EXMC_CTLR4_EMTYP ((uint32_t)0x00000008) /*!< Memory type */ - -#define EXMC_CTLR4_EMWID ((uint32_t)0x00000030) /*!< EMWID[1:0] bits (external memory databus width) */ -#define EXMC_CTLR4_EMWID_0 ((uint32_t)0x00000010) /*!< Bit 0 */ -#define EXMC_CTLR4_EMWID_1 ((uint32_t)0x00000020) /*!< Bit 1 */ - -#define EXMC_CTLR4_ECCEN ((uint32_t)0x00000040) /*!< ECC enable */ - -#define EXMC_CTLR4_CTR ((uint32_t)0x00001E00) /*!< CTR[3:0] bits (CLE to RE delay) */ -#define EXMC_CTLR4_CTR_0 ((uint32_t)0x00000200) /*!< Bit 0 */ -#define EXMC_CTLR4_CTR_1 ((uint32_t)0x00000400) /*!< Bit 1 */ -#define EXMC_CTLR4_CTR_2 ((uint32_t)0x00000800) /*!< Bit 2 */ -#define EXMC_CTLR4_CTR_3 ((uint32_t)0x00001000) /*!< Bit 3 */ - -#define EXMC_CTLR4_ATR ((uint32_t)0x0001E000) /*!< ATR[3:0] bits (ALE to RE delay) */ -#define EXMC_CTLR4_ATR_0 ((uint32_t)0x00002000) /*!< Bit 0 */ -#define EXMC_CTLR4_ATR_1 ((uint32_t)0x00004000) /*!< Bit 1 */ -#define EXMC_CTLR4_ATR_2 ((uint32_t)0x00008000) /*!< Bit 2 */ -#define EXMC_CTLR4_ATR_3 ((uint32_t)0x00010000) /*!< Bit 3 */ - -#define EXMC_CTLR4_ECCSZ ((uint32_t)0x000E0000) /*!< ECCSZ[1:0] bits (ECC size) */ -#define EXMC_CTLR4_ECCSZ_0 ((uint32_t)0x00020000) /*!< Bit 0 */ -#define EXMC_CTLR4_ECCSZ_1 ((uint32_t)0x00040000) /*!< Bit 1 */ -#define EXMC_CTLR4_ECCSZ_2 ((uint32_t)0x00080000) /*!< Bit 2 */ - -/******************* Bit definition for EXMC_SIR2 register *******************/ -#define EXMC_SIR2_ITRS ((uint8_t)0x01) /*!< Interrupt rising edge status */ -#define EXMC_SIR2_ITHS ((uint8_t)0x02) /*!< Interrupt high-level status */ -#define EXMC_SIR2_ITFS ((uint8_t)0x04) /*!< Interrupt falling edge status */ -#define EXMC_SIR2_ITREN ((uint8_t)0x08) /*!< Interrupt rising edge detection Enable bit */ -#define EXMC_SIR2_ITHEN ((uint8_t)0x10) /*!< Interrupt high level detection Enable bit */ -#define EXMC_SIR2_ITFEN ((uint8_t)0x20) /*!< Interrupt falling edge detection Enable bit */ -#define EXMC_SIR2_FIFOE ((uint8_t)0x40) /*!< FIFO empty flag */ - -/******************* Bit definition for EXMC_SIR3 register *******************/ -#define EXMC_SIR3_ITRS ((uint8_t)0x01) /*!< Interrupt rising edge status */ -#define EXMC_SIR3_ITHS ((uint8_t)0x02) /*!< Interrupt high-level status */ -#define EXMC_SIR3_ITFS ((uint8_t)0x04) /*!< Interrupt falling edge status */ -#define EXMC_SIR3_ITREN ((uint8_t)0x08) /*!< Interrupt rising edge detection Enable bit */ -#define EXMC_SIR3_ITHEN ((uint8_t)0x10) /*!< Interrupt high level detection Enable bit */ -#define EXMC_SIR3_ITFEN ((uint8_t)0x20) /*!< Interrupt falling edge detection Enable bit */ -#define EXMC_SIR3_FIFOE ((uint8_t)0x40) /*!< FIFO empty flag */ - -/******************* Bit definition for EXMC_SIR4 register *******************/ -#define EXMC_SIR4_ITRS ((uint8_t)0x01) /*!< Interrupt rising edge status */ -#define EXMC_SIR4_ITHS ((uint8_t)0x02) /*!< Interrupt high-level status */ -#define EXMC_SIR4_ITFS ((uint8_t)0x04) /*!< Interrupt falling edge status */ -#define EXMC_SIR4_ITREN ((uint8_t)0x08) /*!< Interrupt rising edge detection Enable bit */ -#define EXMC_SIR4_ITHEN ((uint8_t)0x10) /*!< Interrupt high level detection Enable bit */ -#define EXMC_SIR4_ITFEN ((uint8_t)0x20) /*!< Interrupt falling edge detection Enable bit */ -#define EXMC_SIR4_FIFOE ((uint8_t)0x40) /*!< FIFO empty flag */ - -/****************** Bit definition for EXMC_COMTR2 register ******************/ -#define EXMC_COMTR2_COMST ((uint32_t)0x000000FF) /*!< COMST[7:0] bits (Common memory 2 setup time) */ -#define EXMC_COMTR2_COMST_0 ((uint32_t)0x00000001) /*!< Bit 0 */ -#define EXMC_COMTR2_COMST_1 ((uint32_t)0x00000002) /*!< Bit 1 */ -#define EXMC_COMTR2_COMST_2 ((uint32_t)0x00000004) /*!< Bit 2 */ -#define EXMC_COMTR2_COMST_3 ((uint32_t)0x00000008) /*!< Bit 3 */ -#define EXMC_COMTR2_COMST_4 ((uint32_t)0x00000010) /*!< Bit 4 */ -#define EXMC_COMTR2_COMST_5 ((uint32_t)0x00000020) /*!< Bit 5 */ -#define EXMC_COMTR2_COMST_6 ((uint32_t)0x00000040) /*!< Bit 6 */ -#define EXMC_COMTR2_COMST_7 ((uint32_t)0x00000080) /*!< Bit 7 */ - -#define EXMC_COMTR2_COMWT ((uint32_t)0x0000FF00) /*!< COMWT[7:0] bits (Common memory 2 wait time) */ -#define EXMC_COMTR2_COMWT_0 ((uint32_t)0x00000100) /*!< Bit 0 */ -#define EXMC_COMTR2_COMWT_1 ((uint32_t)0x00000200) /*!< Bit 1 */ -#define EXMC_COMTR2_COMWT_2 ((uint32_t)0x00000400) /*!< Bit 2 */ -#define EXMC_COMTR2_COMWT_3 ((uint32_t)0x00000800) /*!< Bit 3 */ -#define EXMC_COMTR2_COMWT_4 ((uint32_t)0x00001000) /*!< Bit 4 */ -#define EXMC_COMTR2_COMWT_5 ((uint32_t)0x00002000) /*!< Bit 5 */ -#define EXMC_COMTR2_COMWT_6 ((uint32_t)0x00004000) /*!< Bit 6 */ -#define EXMC_COMTR2_COMWT_7 ((uint32_t)0x00008000) /*!< Bit 7 */ - -#define EXMC_COMTR2_COMHT ((uint32_t)0x00FF0000) /*!< COMHT[7:0] bits (Common memory 2 hold time) */ -#define EXMC_COMTR2_COMHT_0 ((uint32_t)0x00010000) /*!< Bit 0 */ -#define EXMC_COMTR2_COMHT_1 ((uint32_t)0x00020000) /*!< Bit 1 */ -#define EXMC_COMTR2_COMHT_2 ((uint32_t)0x00040000) /*!< Bit 2 */ -#define EXMC_COMTR2_COMHT_3 ((uint32_t)0x00080000) /*!< Bit 3 */ -#define EXMC_COMTR2_COMHT_4 ((uint32_t)0x00100000) /*!< Bit 4 */ -#define EXMC_COMTR2_COMHT_5 ((uint32_t)0x00200000) /*!< Bit 5 */ -#define EXMC_COMTR2_COMHT_6 ((uint32_t)0x00400000) /*!< Bit 6 */ -#define EXMC_COMTR2_COMHT_7 ((uint32_t)0x00800000) /*!< Bit 7 */ - -#define EXMC_COMTR2_COMHIZT ((uint32_t)0xFF000000) /*!< COMHIZ[7:0] bits (Common memory 2 databus HiZ time) */ -#define EXMC_COMTR2_COMHIZT_0 ((uint32_t)0x01000000) /*!< Bit 0 */ -#define EXMC_COMTR2_COMHIZT_1 ((uint32_t)0x02000000) /*!< Bit 1 */ -#define EXMC_COMTR2_COMHIZT_2 ((uint32_t)0x04000000) /*!< Bit 2 */ -#define EXMC_COMTR2_COMHIZT_3 ((uint32_t)0x08000000) /*!< Bit 3 */ -#define EXMC_COMTR2_COMHIZT_4 ((uint32_t)0x10000000) /*!< Bit 4 */ -#define EXMC_COMTR2_COMHIZT_5 ((uint32_t)0x20000000) /*!< Bit 5 */ -#define EXMC_COMTR2_COMHIZT_6 ((uint32_t)0x40000000) /*!< Bit 6 */ -#define EXMC_COMTR2_COMHIZT_7 ((uint32_t)0x80000000) /*!< Bit 7 */ - -/****************** Bit definition for EXMC_COMTR3 register ******************/ -#define EXMC_COMTR3_COMST ((uint32_t)0x000000FF) /*!< COMST[7:0] bits (Common memory 3 setup time) */ -#define EXMC_COMTR3_COMST_0 ((uint32_t)0x00000001) /*!< Bit 0 */ -#define EXMC_COMTR3_COMST_1 ((uint32_t)0x00000002) /*!< Bit 1 */ -#define EXMC_COMTR3_COMST_2 ((uint32_t)0x00000004) /*!< Bit 2 */ -#define EXMC_COMTR3_COMST_3 ((uint32_t)0x00000008) /*!< Bit 3 */ -#define EXMC_COMTR3_COMST_4 ((uint32_t)0x00000010) /*!< Bit 4 */ -#define EXMC_COMTR3_COMST_5 ((uint32_t)0x00000020) /*!< Bit 5 */ -#define EXMC_COMTR3_COMST_6 ((uint32_t)0x00000040) /*!< Bit 6 */ -#define EXMC_COMTR3_COMST_7 ((uint32_t)0x00000080) /*!< Bit 7 */ - -#define EXMC_COMTR3_COMWT ((uint32_t)0x0000FF00) /*!< COMWT[7:0] bits (Common memory 3 wait time) */ -#define EXMC_COMTR3_COMWT_0 ((uint32_t)0x00000100) /*!< Bit 0 */ -#define EXMC_COMTR3_COMWT_1 ((uint32_t)0x00000200) /*!< Bit 1 */ -#define EXMC_COMTR3_COMWT_2 ((uint32_t)0x00000400) /*!< Bit 2 */ -#define EXMC_COMTR3_COMWT_3 ((uint32_t)0x00000800) /*!< Bit 3 */ -#define EXMC_COMTR3_COMWT_4 ((uint32_t)0x00001000) /*!< Bit 4 */ -#define EXMC_COMTR3_COMWT_5 ((uint32_t)0x00002000) /*!< Bit 5 */ -#define EXMC_COMTR3_COMWT_6 ((uint32_t)0x00004000) /*!< Bit 6 */ -#define EXMC_COMTR3_COMWT_7 ((uint32_t)0x00008000) /*!< Bit 7 */ - -#define EXMC_COMTR3_COMHT ((uint32_t)0x00FF0000) /*!< COMHT[7:0] bits (Common memory 3 hold time) */ -#define EXMC_COMTR3_COMHT_0 ((uint32_t)0x00010000) /*!< Bit 0 */ -#define EXMC_COMTR3_COMHT_1 ((uint32_t)0x00020000) /*!< Bit 1 */ -#define EXMC_COMTR3_COMHT_2 ((uint32_t)0x00040000) /*!< Bit 2 */ -#define EXMC_COMTR3_COMHT_3 ((uint32_t)0x00080000) /*!< Bit 3 */ -#define EXMC_COMTR3_COMHT_4 ((uint32_t)0x00100000) /*!< Bit 4 */ -#define EXMC_COMTR3_COMHT_5 ((uint32_t)0x00200000) /*!< Bit 5 */ -#define EXMC_COMTR3_COMHT_6 ((uint32_t)0x00400000) /*!< Bit 6 */ -#define EXMC_COMTR3_COMHT_7 ((uint32_t)0x00800000) /*!< Bit 7 */ - -#define EXMC_COMTR3_COMHIZT ((uint32_t)0xFF000000) /*!< COMHIZ[7:0] bits (Common memory 3 databus HiZ time) */ -#define EXMC_COMTR3_COMHIZT_0 ((uint32_t)0x01000000) /*!< Bit 0 */ -#define EXMC_COMTR3_COMHIZT_1 ((uint32_t)0x02000000) /*!< Bit 1 */ -#define EXMC_COMTR3_COMHIZT_2 ((uint32_t)0x04000000) /*!< Bit 2 */ -#define EXMC_COMTR3_COMHIZT_3 ((uint32_t)0x08000000) /*!< Bit 3 */ -#define EXMC_COMTR3_COMHIZT_4 ((uint32_t)0x10000000) /*!< Bit 4 */ -#define EXMC_COMTR3_COMHIZT_5 ((uint32_t)0x20000000) /*!< Bit 5 */ -#define EXMC_COMTR3_COMHIZT_6 ((uint32_t)0x40000000) /*!< Bit 6 */ -#define EXMC_COMTR3_COMHIZT_7 ((uint32_t)0x80000000) /*!< Bit 7 */ - -/****************** Bit definition for EXMC_COMTR4 register ******************/ -#define EXMC_COMTR4_COMST ((uint32_t)0x000000FF) /*!< COMST[7:0] bits (Common memory 4 setup time) */ -#define EXMC_COMTR4_COMST_0 ((uint32_t)0x00000001) /*!< Bit 0 */ -#define EXMC_COMTR4_COMST_1 ((uint32_t)0x00000002) /*!< Bit 1 */ -#define EXMC_COMTR4_COMST_2 ((uint32_t)0x00000004) /*!< Bit 2 */ -#define EXMC_COMTR4_COMST_3 ((uint32_t)0x00000008) /*!< Bit 3 */ -#define EXMC_COMTR4_COMST_4 ((uint32_t)0x00000010) /*!< Bit 4 */ -#define EXMC_COMTR4_COMST_5 ((uint32_t)0x00000020) /*!< Bit 5 */ -#define EXMC_COMTR4_COMST_6 ((uint32_t)0x00000040) /*!< Bit 6 */ -#define EXMC_COMTR4_COMST_7 ((uint32_t)0x00000080) /*!< Bit 7 */ - -#define EXMC_COMTR4_COMWT ((uint32_t)0x0000FF00) /*!< COMWT[7:0] bits (Common memory 4 wait time) */ -#define EXMC_COMTR4_COMWT_0 ((uint32_t)0x00000100) /*!< Bit 0 */ -#define EXMC_COMTR4_COMWT_1 ((uint32_t)0x00000200) /*!< Bit 1 */ -#define EXMC_COMTR4_COMWT_2 ((uint32_t)0x00000400) /*!< Bit 2 */ -#define EXMC_COMTR4_COMWT_3 ((uint32_t)0x00000800) /*!< Bit 3 */ -#define EXMC_COMTR4_COMWT_4 ((uint32_t)0x00001000) /*!< Bit 4 */ -#define EXMC_COMTR4_COMWT_5 ((uint32_t)0x00002000) /*!< Bit 5 */ -#define EXMC_COMTR4_COMWT_6 ((uint32_t)0x00004000) /*!< Bit 6 */ -#define EXMC_COMTR4_COMWT_7 ((uint32_t)0x00008000) /*!< Bit 7 */ - -#define EXMC_COMTR4_COMHT ((uint32_t)0x00FF0000) /*!< COMHT[7:0] bits (Common memory 4 hold time) */ -#define EXMC_COMTR4_COMHT_0 ((uint32_t)0x00010000) /*!< Bit 0 */ -#define EXMC_COMTR4_COMHT_1 ((uint32_t)0x00020000) /*!< Bit 1 */ -#define EXMC_COMTR4_COMHT_2 ((uint32_t)0x00040000) /*!< Bit 2 */ -#define EXMC_COMTR4_COMHT_3 ((uint32_t)0x00080000) /*!< Bit 3 */ -#define EXMC_COMTR4_COMHT_4 ((uint32_t)0x00100000) /*!< Bit 4 */ -#define EXMC_COMTR4_COMHT_5 ((uint32_t)0x00200000) /*!< Bit 5 */ -#define EXMC_COMTR4_COMHT_6 ((uint32_t)0x00400000) /*!< Bit 6 */ -#define EXMC_COMTR4_COMHT_7 ((uint32_t)0x00800000) /*!< Bit 7 */ - -#define EXMC_COMTR4_COMHIZT ((uint32_t)0xFF000000) /*!< COMHIZ[7:0] bits (Common memory 4 databus HiZ time) */ -#define EXMC_COMTR4_COMHIZT_0 ((uint32_t)0x01000000) /*!< Bit 0 */ -#define EXMC_COMTR4_COMHIZT_1 ((uint32_t)0x02000000) /*!< Bit 1 */ -#define EXMC_COMTR4_COMHIZT_2 ((uint32_t)0x04000000) /*!< Bit 2 */ -#define EXMC_COMTR4_COMHIZT_3 ((uint32_t)0x08000000) /*!< Bit 3 */ -#define EXMC_COMTR4_COMHIZT_4 ((uint32_t)0x10000000) /*!< Bit 4 */ -#define EXMC_COMTR4_COMHIZT_5 ((uint32_t)0x20000000) /*!< Bit 5 */ -#define EXMC_COMTR4_COMHIZT_6 ((uint32_t)0x40000000) /*!< Bit 6 */ -#define EXMC_COMTR4_COMHIZT_7 ((uint32_t)0x80000000) /*!< Bit 7 */ - -/****************** Bit definition for EXMC_ATTR2 register ******************/ -#define EXMC_ATTR2_ATTST ((uint32_t)0x000000FF) /*!< ATTST[7:0] bits (Attribute memory 2 setup time) */ -#define EXMC_ATTR2_ATTST_0 ((uint32_t)0x00000001) /*!< Bit 0 */ -#define EXMC_ATTR2_ATTST_1 ((uint32_t)0x00000002) /*!< Bit 1 */ -#define EXMC_ATTR2_ATTST_2 ((uint32_t)0x00000004) /*!< Bit 2 */ -#define EXMC_ATTR2_ATTST_3 ((uint32_t)0x00000008) /*!< Bit 3 */ -#define EXMC_ATTR2_ATTST_4 ((uint32_t)0x00000010) /*!< Bit 4 */ -#define EXMC_ATTR2_ATTST_5 ((uint32_t)0x00000020) /*!< Bit 5 */ -#define EXMC_ATTR2_ATTST_6 ((uint32_t)0x00000040) /*!< Bit 6 */ -#define EXMC_ATTR2_ATTST_7 ((uint32_t)0x00000080) /*!< Bit 7 */ - -#define EXMC_ATTR2_ATTWT ((uint32_t)0x0000FF00) /*!< ATTWT[7:0] bits (Attribute memory 2 wait time) */ -#define EXMC_ATTR2_ATTWT_0 ((uint32_t)0x00000100) /*!< Bit 0 */ -#define EXMC_ATTR2_ATTWT_1 ((uint32_t)0x00000200) /*!< Bit 1 */ -#define EXMC_ATTR2_ATTWT_2 ((uint32_t)0x00000400) /*!< Bit 2 */ -#define EXMC_ATTR2_ATTWT_3 ((uint32_t)0x00000800) /*!< Bit 3 */ -#define EXMC_ATTR2_ATTWT_4 ((uint32_t)0x00001000) /*!< Bit 4 */ -#define EXMC_ATTR2_ATTWT_5 ((uint32_t)0x00002000) /*!< Bit 5 */ -#define EXMC_ATTR2_ATTWT_6 ((uint32_t)0x00004000) /*!< Bit 6 */ -#define EXMC_ATTR2_ATTWT_7 ((uint32_t)0x00008000) /*!< Bit 7 */ - -#define EXMC_ATTR2_ATTHT ((uint32_t)0x00FF0000) /*!< ATTHT[7:0] bits (Attribute memory 2 hold time) */ -#define EXMC_ATTR2_ATTHT_0 ((uint32_t)0x00010000) /*!< Bit 0 */ -#define EXMC_ATTR2_ATTHT_1 ((uint32_t)0x00020000) /*!< Bit 1 */ -#define EXMC_ATTR2_ATTHT_2 ((uint32_t)0x00040000) /*!< Bit 2 */ -#define EXMC_ATTR2_ATTHT_3 ((uint32_t)0x00080000) /*!< Bit 3 */ -#define EXMC_ATTR2_ATTHT_4 ((uint32_t)0x00100000) /*!< Bit 4 */ -#define EXMC_ATTR2_ATTHT_5 ((uint32_t)0x00200000) /*!< Bit 5 */ -#define EXMC_ATTR2_ATTHT_6 ((uint32_t)0x00400000) /*!< Bit 6 */ -#define EXMC_ATTR2_ATTHT_7 ((uint32_t)0x00800000) /*!< Bit 7 */ - -#define EXMC_ATTR2_ATTHIZT ((uint32_t)0xFF000000) /*!< ATTHIZ[7:0] bits (Attribute memory 2 databus HiZ time) */ -#define EXMC_ATTR2_ATTHIZT_0 ((uint32_t)0x01000000) /*!< Bit 0 */ -#define EXMC_ATTR2_ATTHIZT_1 ((uint32_t)0x02000000) /*!< Bit 1 */ -#define EXMC_ATTR2_ATTHIZT_2 ((uint32_t)0x04000000) /*!< Bit 2 */ -#define EXMC_ATTR2_ATTHIZT_3 ((uint32_t)0x08000000) /*!< Bit 3 */ -#define EXMC_ATTR2_ATTHIZT_4 ((uint32_t)0x10000000) /*!< Bit 4 */ -#define EXMC_ATTR2_ATTHIZT_5 ((uint32_t)0x20000000) /*!< Bit 5 */ -#define EXMC_ATTR2_ATTHIZT_6 ((uint32_t)0x40000000) /*!< Bit 6 */ -#define EXMC_ATTR2_ATTHIZT_7 ((uint32_t)0x80000000) /*!< Bit 7 */ - -/****************** Bit definition for EXMC_ATTR3 register ******************/ -#define EXMC_ATTR3_ATTST ((uint32_t)0x000000FF) /*!< ATTST[7:0] bits (Attribute memory 3 setup time) */ -#define EXMC_ATTR3_ATTST_0 ((uint32_t)0x00000001) /*!< Bit 0 */ -#define EXMC_ATTR3_ATTST_1 ((uint32_t)0x00000002) /*!< Bit 1 */ -#define EXMC_ATTR3_ATTST_2 ((uint32_t)0x00000004) /*!< Bit 2 */ -#define EXMC_ATTR3_ATTST_3 ((uint32_t)0x00000008) /*!< Bit 3 */ -#define EXMC_ATTR3_ATTST_4 ((uint32_t)0x00000010) /*!< Bit 4 */ -#define EXMC_ATTR3_ATTST_5 ((uint32_t)0x00000020) /*!< Bit 5 */ -#define EXMC_ATTR3_ATTST_6 ((uint32_t)0x00000040) /*!< Bit 6 */ -#define EXMC_ATTR3_ATTST_7 ((uint32_t)0x00000080) /*!< Bit 7 */ - -#define EXMC_ATTR3_ATTWT ((uint32_t)0x0000FF00) /*!< ATTWT[7:0] bits (Attribute memory 3 wait time) */ -#define EXMC_ATTR3_ATTWT_0 ((uint32_t)0x00000100) /*!< Bit 0 */ -#define EXMC_ATTR3_ATTWT_1 ((uint32_t)0x00000200) /*!< Bit 1 */ -#define EXMC_ATTR3_ATTWT_2 ((uint32_t)0x00000400) /*!< Bit 2 */ -#define EXMC_ATTR3_ATTWT_3 ((uint32_t)0x00000800) /*!< Bit 3 */ -#define EXMC_ATTR3_ATTWT_4 ((uint32_t)0x00001000) /*!< Bit 4 */ -#define EXMC_ATTR3_ATTWT_5 ((uint32_t)0x00002000) /*!< Bit 5 */ -#define EXMC_ATTR3_ATTWT_6 ((uint32_t)0x00004000) /*!< Bit 6 */ -#define EXMC_ATTR3_ATTWT_7 ((uint32_t)0x00008000) /*!< Bit 7 */ - -#define EXMC_ATTR3_ATTHT ((uint32_t)0x00FF0000) /*!< ATTHT[7:0] bits (Attribute memory 3 hold time) */ -#define EXMC_ATTR3_ATTHT_0 ((uint32_t)0x00010000) /*!< Bit 0 */ -#define EXMC_ATTR3_ATTHT_1 ((uint32_t)0x00020000) /*!< Bit 1 */ -#define EXMC_ATTR3_ATTHT_2 ((uint32_t)0x00040000) /*!< Bit 2 */ -#define EXMC_ATTR3_ATTHT_3 ((uint32_t)0x00080000) /*!< Bit 3 */ -#define EXMC_ATTR3_ATTHT_4 ((uint32_t)0x00100000) /*!< Bit 4 */ -#define EXMC_ATTR3_ATTHT_5 ((uint32_t)0x00200000) /*!< Bit 5 */ -#define EXMC_ATTR3_ATTHT_6 ((uint32_t)0x00400000) /*!< Bit 6 */ -#define EXMC_ATTR3_ATTHT_7 ((uint32_t)0x00800000) /*!< Bit 7 */ - -#define EXMC_ATTR3_ATTHIZT ((uint32_t)0xFF000000) /*!< ATTHIZ[7:0] bits (Attribute memory 3 databus HiZ time) */ -#define EXMC_ATTR3_ATTHIZT_0 ((uint32_t)0x01000000) /*!< Bit 0 */ -#define EXMC_ATTR3_ATTHIZT_1 ((uint32_t)0x02000000) /*!< Bit 1 */ -#define EXMC_ATTR3_ATTHIZT_2 ((uint32_t)0x04000000) /*!< Bit 2 */ -#define EXMC_ATTR3_ATTHIZT_3 ((uint32_t)0x08000000) /*!< Bit 3 */ -#define EXMC_ATTR3_ATTHIZT_4 ((uint32_t)0x10000000) /*!< Bit 4 */ -#define EXMC_ATTR3_ATTHIZT_5 ((uint32_t)0x20000000) /*!< Bit 5 */ -#define EXMC_ATTR3_ATTHIZT_6 ((uint32_t)0x40000000) /*!< Bit 6 */ -#define EXMC_ATTR3_ATTHIZT_7 ((uint32_t)0x80000000) /*!< Bit 7 */ - -/****************** Bit definition for EXMC_ATTR4 register ******************/ -#define EXMC_ATTR4_ATTST ((uint32_t)0x000000FF) /*!< ATTST[7:0] bits (Attribute memory 4 setup time) */ -#define EXMC_ATTR4_ATTST_0 ((uint32_t)0x00000001) /*!< Bit 0 */ -#define EXMC_ATTR4_ATTST_1 ((uint32_t)0x00000002) /*!< Bit 1 */ -#define EXMC_ATTR4_ATTST_2 ((uint32_t)0x00000004) /*!< Bit 2 */ -#define EXMC_ATTR4_ATTST_3 ((uint32_t)0x00000008) /*!< Bit 3 */ -#define EXMC_ATTR4_ATTST_4 ((uint32_t)0x00000010) /*!< Bit 4 */ -#define EXMC_ATTR4_ATTST_5 ((uint32_t)0x00000020) /*!< Bit 5 */ -#define EXMC_ATTR4_ATTST_6 ((uint32_t)0x00000040) /*!< Bit 6 */ -#define EXMC_ATTR4_ATTST_7 ((uint32_t)0x00000080) /*!< Bit 7 */ - -#define EXMC_ATTR4_ATTWT ((uint32_t)0x0000FF00) /*!< ATTWT[7:0] bits (Attribute memory 4 wait time) */ -#define EXMC_ATTR4_ATTWT_0 ((uint32_t)0x00000100) /*!< Bit 0 */ -#define EXMC_ATTR4_ATTWT_1 ((uint32_t)0x00000200) /*!< Bit 1 */ -#define EXMC_ATTR4_ATTWT_2 ((uint32_t)0x00000400) /*!< Bit 2 */ -#define EXMC_ATTR4_ATTWT_3 ((uint32_t)0x00000800) /*!< Bit 3 */ -#define EXMC_ATTR4_ATTWT_4 ((uint32_t)0x00001000) /*!< Bit 4 */ -#define EXMC_ATTR4_ATTWT_5 ((uint32_t)0x00002000) /*!< Bit 5 */ -#define EXMC_ATTR4_ATTWT_6 ((uint32_t)0x00004000) /*!< Bit 6 */ -#define EXMC_ATTR4_ATTWT_7 ((uint32_t)0x00008000) /*!< Bit 7 */ - -#define EXMC_ATTR4_ATTHT ((uint32_t)0x00FF0000) /*!< ATTHT[7:0] bits (Attribute memory 4 hold time) */ -#define EXMC_ATTR4_ATTHT_0 ((uint32_t)0x00010000) /*!< Bit 0 */ -#define EXMC_ATTR4_ATTHT_1 ((uint32_t)0x00020000) /*!< Bit 1 */ -#define EXMC_ATTR4_ATTHT_2 ((uint32_t)0x00040000) /*!< Bit 2 */ -#define EXMC_ATTR4_ATTHT_3 ((uint32_t)0x00080000) /*!< Bit 3 */ -#define EXMC_ATTR4_ATTHT_4 ((uint32_t)0x00100000) /*!< Bit 4 */ -#define EXMC_ATTR4_ATTHT_5 ((uint32_t)0x00200000) /*!< Bit 5 */ -#define EXMC_ATTR4_ATTHT_6 ((uint32_t)0x00400000) /*!< Bit 6 */ -#define EXMC_ATTR4_ATTHT_7 ((uint32_t)0x00800000) /*!< Bit 7 */ - -#define EXMC_ATTR4_ATTHIZT ((uint32_t)0xFF000000) /*!< ATTHIZ[7:0] bits (Attribute memory 4 databus HiZ time) */ -#define EXMC_ATTR4_ATTHIZT_0 ((uint32_t)0x01000000) /*!< Bit 0 */ -#define EXMC_ATTR4_ATTHIZT_1 ((uint32_t)0x02000000) /*!< Bit 1 */ -#define EXMC_ATTR4_ATTHIZT_2 ((uint32_t)0x04000000) /*!< Bit 2 */ -#define EXMC_ATTR4_ATTHIZT_3 ((uint32_t)0x08000000) /*!< Bit 3 */ -#define EXMC_ATTR4_ATTHIZT_4 ((uint32_t)0x10000000) /*!< Bit 4 */ -#define EXMC_ATTR4_ATTHIZT_5 ((uint32_t)0x20000000) /*!< Bit 5 */ -#define EXMC_ATTR4_ATTHIZT_6 ((uint32_t)0x40000000) /*!< Bit 6 */ -#define EXMC_ATTR3_ATTHIZT_7 ((uint32_t)0x80000000) /*!< Bit 7 */ - -/****************** Bit definition for EXMC_IOTR4 register ******************/ -#define EXMC_IOTR4_IOST ((uint32_t)0x000000FF) /*!< IOST[7:0] bits (I/O memory 4 setup time) */ -#define EXMC_IOTR4_IOST_0 ((uint32_t)0x00000001) /*!< Bit 0 */ -#define EXMC_IOTR4_IOST_1 ((uint32_t)0x00000002) /*!< Bit 1 */ -#define EXMC_IOTR4_IOST_2 ((uint32_t)0x00000004) /*!< Bit 2 */ -#define EXMC_IOTR4_IOST_3 ((uint32_t)0x00000008) /*!< Bit 3 */ -#define EXMC_IOTR4_IOST_4 ((uint32_t)0x00000010) /*!< Bit 4 */ -#define EXMC_IOTR4_IOST_5 ((uint32_t)0x00000020) /*!< Bit 5 */ -#define EXMC_IOTR4_IOST_6 ((uint32_t)0x00000040) /*!< Bit 6 */ -#define EXMC_IOTR4_IOST_7 ((uint32_t)0x00000080) /*!< Bit 7 */ - -#define EXMC_IOTR4_IOWT ((uint32_t)0x0000FF00) /*!< IOWT[7:0] bits (I/O memory 4 wait time) */ -#define EXMC_IOTR4_IOWT_0 ((uint32_t)0x00000100) /*!< Bit 0 */ -#define EXMC_IOTR4_IOWT_1 ((uint32_t)0x00000200) /*!< Bit 1 */ -#define EXMC_IOTR4_IOWT_2 ((uint32_t)0x00000400) /*!< Bit 2 */ -#define EXMC_IOTR4_IOWT_3 ((uint32_t)0x00000800) /*!< Bit 3 */ -#define EXMC_IOTR4_IOWT_4 ((uint32_t)0x00001000) /*!< Bit 4 */ -#define EXMC_IOTR4_IOWT_5 ((uint32_t)0x00002000) /*!< Bit 5 */ -#define EXMC_IOTR4_IOWT_6 ((uint32_t)0x00004000) /*!< Bit 6 */ -#define EXMC_IOTR4_IOWT_7 ((uint32_t)0x00008000) /*!< Bit 7 */ - -#define EXMC_IOTR4_IOHT ((uint32_t)0x00FF0000) /*!< IOHT[7:0] bits (I/O memory 4 hold time) */ -#define EXMC_IOTR4_IOHT_0 ((uint32_t)0x00010000) /*!< Bit 0 */ -#define EXMC_IOTR4_IOHT_1 ((uint32_t)0x00020000) /*!< Bit 1 */ -#define EXMC_IOTR4_IOHT_2 ((uint32_t)0x00040000) /*!< Bit 2 */ -#define EXMC_IOTR4_IOHT_3 ((uint32_t)0x00080000) /*!< Bit 3 */ -#define EXMC_IOTR4_IOHT_4 ((uint32_t)0x00100000) /*!< Bit 4 */ -#define EXMC_IOTR4_IOHT_5 ((uint32_t)0x00200000) /*!< Bit 5 */ -#define EXMC_IOTR4_IOHT_6 ((uint32_t)0x00400000) /*!< Bit 6 */ -#define EXMC_IOTR4_IOHT_7 ((uint32_t)0x00800000) /*!< Bit 7 */ - -#define EXMC_IOTR4_IOHIZT ((uint32_t)0xFF000000) /*!< IOHIZ[7:0] bits (I/O memory 4 databus HiZ time) */ -#define EXMC_IOTR4_IOHIZT_0 ((uint32_t)0x01000000) /*!< Bit 0 */ -#define EXMC_IOTR4_IOHIZT_1 ((uint32_t)0x02000000) /*!< Bit 1 */ -#define EXMC_IOTR4_IOHIZT_2 ((uint32_t)0x04000000) /*!< Bit 2 */ -#define EXMC_IOTR4_IOHIZT_3 ((uint32_t)0x08000000) /*!< Bit 3 */ -#define EXMC_IOTR4_IOHIZT_4 ((uint32_t)0x10000000) /*!< Bit 4 */ -#define EXMC_IOTR4_IOHIZT_5 ((uint32_t)0x20000000) /*!< Bit 5 */ -#define EXMC_IOTR4_IOHIZT_6 ((uint32_t)0x40000000) /*!< Bit 6 */ -#define EXMC_IOTR4_IOHIZT_7 ((uint32_t)0x80000000) /*!< Bit 7 */ - -/****************** Bit definition for EXMC_ECCR2 register ******************/ -#define EXMC_ECCR2_ECC ((uint32_t)0xFFFFFFFF) /*!< ECC result */ - -/****************** Bit definition for EXMC_ECCR3 register ******************/ -#define EXMC_ECCR3_ECC ((uint32_t)0xFFFFFFFF) /*!< ECC result */ - - -/******************************************************************************/ -/* */ -/* SystemTick */ -/* */ -/******************************************************************************/ - -/***************** Bit definition for SysTick_CTRL register *****************/ -#define SYSTICK_CTRL_ENABLE ((uint32_t)0x00000001) /*!< Counter enable */ -#define SYSTICK_CTRL_TICKINT ((uint32_t)0x00000002) /*!< Counting down to 0 pends the SysTick handler */ -#define SYSTICK_CTRL_CLKSOURCE ((uint32_t)0x00000004) /*!< Clock source */ -#define SYSTICK_CTRL_COUNTFLAG ((uint32_t)0x00010000) /*!< Count Flag */ - -/***************** Bit definition for SysTick_LOAD register *****************/ -#define SYSTICK_LOAD_RELOAD ((uint32_t)0x00FFFFFF) /*!< Value to load into the SysTick Current Value Register when the counter reaches 0 */ - -/***************** Bit definition for SysTick_VAL register ******************/ -#define SYSTICK_VAL_CURRENT ((uint32_t)0x00FFFFFF) /*!< Current value at the time the register is accessed */ - -/***************** Bit definition for SysTick_CALIB register ****************/ -#define SYSTICK_CALIB_TENMS ((uint32_t)0x00FFFFFF) /*!< Reload value to use for 10ms timing */ -#define SYSTICK_CALIB_SKEW ((uint32_t)0x40000000) /*!< Calibration value is not exactly 10 ms */ -#define SYSTICK_CALIB_NOREF ((uint32_t)0x80000000) /*!< The reference clock is not provided */ - -/******************************************************************************/ -/* */ -/* Nested Vectored Interrupt Controller */ -/* */ -/******************************************************************************/ - -/****************** Bit definition for NVIC_ISER register *******************/ -#define NVIC_ISER_SETENA ((uint32_t)0xFFFFFFFF) /*!< Interrupt set enable bits */ -#define NVIC_ISER_SETENA_0 ((uint32_t)0x00000001) /*!< bit 0 */ -#define NVIC_ISER_SETENA_1 ((uint32_t)0x00000002) /*!< bit 1 */ -#define NVIC_ISER_SETENA_2 ((uint32_t)0x00000004) /*!< bit 2 */ -#define NVIC_ISER_SETENA_3 ((uint32_t)0x00000008) /*!< bit 3 */ -#define NVIC_ISER_SETENA_4 ((uint32_t)0x00000010) /*!< bit 4 */ -#define NVIC_ISER_SETENA_5 ((uint32_t)0x00000020) /*!< bit 5 */ -#define NVIC_ISER_SETENA_6 ((uint32_t)0x00000040) /*!< bit 6 */ -#define NVIC_ISER_SETENA_7 ((uint32_t)0x00000080) /*!< bit 7 */ -#define NVIC_ISER_SETENA_8 ((uint32_t)0x00000100) /*!< bit 8 */ -#define NVIC_ISER_SETENA_9 ((uint32_t)0x00000200) /*!< bit 9 */ -#define NVIC_ISER_SETENA_10 ((uint32_t)0x00000400) /*!< bit 10 */ -#define NVIC_ISER_SETENA_11 ((uint32_t)0x00000800) /*!< bit 11 */ -#define NVIC_ISER_SETENA_12 ((uint32_t)0x00001000) /*!< bit 12 */ -#define NVIC_ISER_SETENA_13 ((uint32_t)0x00002000) /*!< bit 13 */ -#define NVIC_ISER_SETENA_14 ((uint32_t)0x00004000) /*!< bit 14 */ -#define NVIC_ISER_SETENA_15 ((uint32_t)0x00008000) /*!< bit 15 */ -#define NVIC_ISER_SETENA_16 ((uint32_t)0x00010000) /*!< bit 16 */ -#define NVIC_ISER_SETENA_17 ((uint32_t)0x00020000) /*!< bit 17 */ -#define NVIC_ISER_SETENA_18 ((uint32_t)0x00040000) /*!< bit 18 */ -#define NVIC_ISER_SETENA_19 ((uint32_t)0x00080000) /*!< bit 19 */ -#define NVIC_ISER_SETENA_20 ((uint32_t)0x00100000) /*!< bit 20 */ -#define NVIC_ISER_SETENA_21 ((uint32_t)0x00200000) /*!< bit 21 */ -#define NVIC_ISER_SETENA_22 ((uint32_t)0x00400000) /*!< bit 22 */ -#define NVIC_ISER_SETENA_23 ((uint32_t)0x00800000) /*!< bit 23 */ -#define NVIC_ISER_SETENA_24 ((uint32_t)0x01000000) /*!< bit 24 */ -#define NVIC_ISER_SETENA_25 ((uint32_t)0x02000000) /*!< bit 25 */ -#define NVIC_ISER_SETENA_26 ((uint32_t)0x04000000) /*!< bit 26 */ -#define NVIC_ISER_SETENA_27 ((uint32_t)0x08000000) /*!< bit 27 */ -#define NVIC_ISER_SETENA_28 ((uint32_t)0x10000000) /*!< bit 28 */ -#define NVIC_ISER_SETENA_29 ((uint32_t)0x20000000) /*!< bit 29 */ -#define NVIC_ISER_SETENA_30 ((uint32_t)0x40000000) /*!< bit 30 */ -#define NVIC_ISER_SETENA_31 ((uint32_t)0x80000000) /*!< bit 31 */ - -/****************** Bit definition for NVIC_ICER register *******************/ -#define NVIC_ICER_CLRENA ((uint32_t)0xFFFFFFFF) /*!< Interrupt clear-enable bits */ -#define NVIC_ICER_CLRENA_0 ((uint32_t)0x00000001) /*!< bit 0 */ -#define NVIC_ICER_CLRENA_1 ((uint32_t)0x00000002) /*!< bit 1 */ -#define NVIC_ICER_CLRENA_2 ((uint32_t)0x00000004) /*!< bit 2 */ -#define NVIC_ICER_CLRENA_3 ((uint32_t)0x00000008) /*!< bit 3 */ -#define NVIC_ICER_CLRENA_4 ((uint32_t)0x00000010) /*!< bit 4 */ -#define NVIC_ICER_CLRENA_5 ((uint32_t)0x00000020) /*!< bit 5 */ -#define NVIC_ICER_CLRENA_6 ((uint32_t)0x00000040) /*!< bit 6 */ -#define NVIC_ICER_CLRENA_7 ((uint32_t)0x00000080) /*!< bit 7 */ -#define NVIC_ICER_CLRENA_8 ((uint32_t)0x00000100) /*!< bit 8 */ -#define NVIC_ICER_CLRENA_9 ((uint32_t)0x00000200) /*!< bit 9 */ -#define NVIC_ICER_CLRENA_10 ((uint32_t)0x00000400) /*!< bit 10 */ -#define NVIC_ICER_CLRENA_11 ((uint32_t)0x00000800) /*!< bit 11 */ -#define NVIC_ICER_CLRENA_12 ((uint32_t)0x00001000) /*!< bit 12 */ -#define NVIC_ICER_CLRENA_13 ((uint32_t)0x00002000) /*!< bit 13 */ -#define NVIC_ICER_CLRENA_14 ((uint32_t)0x00004000) /*!< bit 14 */ -#define NVIC_ICER_CLRENA_15 ((uint32_t)0x00008000) /*!< bit 15 */ -#define NVIC_ICER_CLRENA_16 ((uint32_t)0x00010000) /*!< bit 16 */ -#define NVIC_ICER_CLRENA_17 ((uint32_t)0x00020000) /*!< bit 17 */ -#define NVIC_ICER_CLRENA_18 ((uint32_t)0x00040000) /*!< bit 18 */ -#define NVIC_ICER_CLRENA_19 ((uint32_t)0x00080000) /*!< bit 19 */ -#define NVIC_ICER_CLRENA_20 ((uint32_t)0x00100000) /*!< bit 20 */ -#define NVIC_ICER_CLRENA_21 ((uint32_t)0x00200000) /*!< bit 21 */ -#define NVIC_ICER_CLRENA_22 ((uint32_t)0x00400000) /*!< bit 22 */ -#define NVIC_ICER_CLRENA_23 ((uint32_t)0x00800000) /*!< bit 23 */ -#define NVIC_ICER_CLRENA_24 ((uint32_t)0x01000000) /*!< bit 24 */ -#define NVIC_ICER_CLRENA_25 ((uint32_t)0x02000000) /*!< bit 25 */ -#define NVIC_ICER_CLRENA_26 ((uint32_t)0x04000000) /*!< bit 26 */ -#define NVIC_ICER_CLRENA_27 ((uint32_t)0x08000000) /*!< bit 27 */ -#define NVIC_ICER_CLRENA_28 ((uint32_t)0x10000000) /*!< bit 28 */ -#define NVIC_ICER_CLRENA_29 ((uint32_t)0x20000000) /*!< bit 29 */ -#define NVIC_ICER_CLRENA_30 ((uint32_t)0x40000000) /*!< bit 30 */ -#define NVIC_ICER_CLRENA_31 ((uint32_t)0x80000000) /*!< bit 31 */ - -/****************** Bit definition for NVIC_ISPR register *******************/ -#define NVIC_ISPR_SETPEND ((uint32_t)0xFFFFFFFF) /*!< Interrupt set-pending bits */ -#define NVIC_ISPR_SETPEND_0 ((uint32_t)0x00000001) /*!< bit 0 */ -#define NVIC_ISPR_SETPEND_1 ((uint32_t)0x00000002) /*!< bit 1 */ -#define NVIC_ISPR_SETPEND_2 ((uint32_t)0x00000004) /*!< bit 2 */ -#define NVIC_ISPR_SETPEND_3 ((uint32_t)0x00000008) /*!< bit 3 */ -#define NVIC_ISPR_SETPEND_4 ((uint32_t)0x00000010) /*!< bit 4 */ -#define NVIC_ISPR_SETPEND_5 ((uint32_t)0x00000020) /*!< bit 5 */ -#define NVIC_ISPR_SETPEND_6 ((uint32_t)0x00000040) /*!< bit 6 */ -#define NVIC_ISPR_SETPEND_7 ((uint32_t)0x00000080) /*!< bit 7 */ -#define NVIC_ISPR_SETPEND_8 ((uint32_t)0x00000100) /*!< bit 8 */ -#define NVIC_ISPR_SETPEND_9 ((uint32_t)0x00000200) /*!< bit 9 */ -#define NVIC_ISPR_SETPEND_10 ((uint32_t)0x00000400) /*!< bit 10 */ -#define NVIC_ISPR_SETPEND_11 ((uint32_t)0x00000800) /*!< bit 11 */ -#define NVIC_ISPR_SETPEND_12 ((uint32_t)0x00001000) /*!< bit 12 */ -#define NVIC_ISPR_SETPEND_13 ((uint32_t)0x00002000) /*!< bit 13 */ -#define NVIC_ISPR_SETPEND_14 ((uint32_t)0x00004000) /*!< bit 14 */ -#define NVIC_ISPR_SETPEND_15 ((uint32_t)0x00008000) /*!< bit 15 */ -#define NVIC_ISPR_SETPEND_16 ((uint32_t)0x00010000) /*!< bit 16 */ -#define NVIC_ISPR_SETPEND_17 ((uint32_t)0x00020000) /*!< bit 17 */ -#define NVIC_ISPR_SETPEND_18 ((uint32_t)0x00040000) /*!< bit 18 */ -#define NVIC_ISPR_SETPEND_19 ((uint32_t)0x00080000) /*!< bit 19 */ -#define NVIC_ISPR_SETPEND_20 ((uint32_t)0x00100000) /*!< bit 20 */ -#define NVIC_ISPR_SETPEND_21 ((uint32_t)0x00200000) /*!< bit 21 */ -#define NVIC_ISPR_SETPEND_22 ((uint32_t)0x00400000) /*!< bit 22 */ -#define NVIC_ISPR_SETPEND_23 ((uint32_t)0x00800000) /*!< bit 23 */ -#define NVIC_ISPR_SETPEND_24 ((uint32_t)0x01000000) /*!< bit 24 */ -#define NVIC_ISPR_SETPEND_25 ((uint32_t)0x02000000) /*!< bit 25 */ -#define NVIC_ISPR_SETPEND_26 ((uint32_t)0x04000000) /*!< bit 26 */ -#define NVIC_ISPR_SETPEND_27 ((uint32_t)0x08000000) /*!< bit 27 */ -#define NVIC_ISPR_SETPEND_28 ((uint32_t)0x10000000) /*!< bit 28 */ -#define NVIC_ISPR_SETPEND_29 ((uint32_t)0x20000000) /*!< bit 29 */ -#define NVIC_ISPR_SETPEND_30 ((uint32_t)0x40000000) /*!< bit 30 */ -#define NVIC_ISPR_SETPEND_31 ((uint32_t)0x80000000) /*!< bit 31 */ - -/****************** Bit definition for NVIC_ICPR register *******************/ -#define NVIC_ICPR_CLRPEND ((uint32_t)0xFFFFFFFF) /*!< Interrupt clear-pending bits */ -#define NVIC_ICPR_CLRPEND_0 ((uint32_t)0x00000001) /*!< bit 0 */ -#define NVIC_ICPR_CLRPEND_1 ((uint32_t)0x00000002) /*!< bit 1 */ -#define NVIC_ICPR_CLRPEND_2 ((uint32_t)0x00000004) /*!< bit 2 */ -#define NVIC_ICPR_CLRPEND_3 ((uint32_t)0x00000008) /*!< bit 3 */ -#define NVIC_ICPR_CLRPEND_4 ((uint32_t)0x00000010) /*!< bit 4 */ -#define NVIC_ICPR_CLRPEND_5 ((uint32_t)0x00000020) /*!< bit 5 */ -#define NVIC_ICPR_CLRPEND_6 ((uint32_t)0x00000040) /*!< bit 6 */ -#define NVIC_ICPR_CLRPEND_7 ((uint32_t)0x00000080) /*!< bit 7 */ -#define NVIC_ICPR_CLRPEND_8 ((uint32_t)0x00000100) /*!< bit 8 */ -#define NVIC_ICPR_CLRPEND_9 ((uint32_t)0x00000200) /*!< bit 9 */ -#define NVIC_ICPR_CLRPEND_10 ((uint32_t)0x00000400) /*!< bit 10 */ -#define NVIC_ICPR_CLRPEND_11 ((uint32_t)0x00000800) /*!< bit 11 */ -#define NVIC_ICPR_CLRPEND_12 ((uint32_t)0x00001000) /*!< bit 12 */ -#define NVIC_ICPR_CLRPEND_13 ((uint32_t)0x00002000) /*!< bit 13 */ -#define NVIC_ICPR_CLRPEND_14 ((uint32_t)0x00004000) /*!< bit 14 */ -#define NVIC_ICPR_CLRPEND_15 ((uint32_t)0x00008000) /*!< bit 15 */ -#define NVIC_ICPR_CLRPEND_16 ((uint32_t)0x00010000) /*!< bit 16 */ -#define NVIC_ICPR_CLRPEND_17 ((uint32_t)0x00020000) /*!< bit 17 */ -#define NVIC_ICPR_CLRPEND_18 ((uint32_t)0x00040000) /*!< bit 18 */ -#define NVIC_ICPR_CLRPEND_19 ((uint32_t)0x00080000) /*!< bit 19 */ -#define NVIC_ICPR_CLRPEND_20 ((uint32_t)0x00100000) /*!< bit 20 */ -#define NVIC_ICPR_CLRPEND_21 ((uint32_t)0x00200000) /*!< bit 21 */ -#define NVIC_ICPR_CLRPEND_22 ((uint32_t)0x00400000) /*!< bit 22 */ -#define NVIC_ICPR_CLRPEND_23 ((uint32_t)0x00800000) /*!< bit 23 */ -#define NVIC_ICPR_CLRPEND_24 ((uint32_t)0x01000000) /*!< bit 24 */ -#define NVIC_ICPR_CLRPEND_25 ((uint32_t)0x02000000) /*!< bit 25 */ -#define NVIC_ICPR_CLRPEND_26 ((uint32_t)0x04000000) /*!< bit 26 */ -#define NVIC_ICPR_CLRPEND_27 ((uint32_t)0x08000000) /*!< bit 27 */ -#define NVIC_ICPR_CLRPEND_28 ((uint32_t)0x10000000) /*!< bit 28 */ -#define NVIC_ICPR_CLRPEND_29 ((uint32_t)0x20000000) /*!< bit 29 */ -#define NVIC_ICPR_CLRPEND_30 ((uint32_t)0x40000000) /*!< bit 30 */ -#define NVIC_ICPR_CLRPEND_31 ((uint32_t)0x80000000) /*!< bit 31 */ - -/****************** Bit definition for NVIC_IABR register *******************/ -#define NVIC_IABR_ACTIVE ((uint32_t)0xFFFFFFFF) /*!< Interrupt active flags */ -#define NVIC_IABR_ACTIVE_0 ((uint32_t)0x00000001) /*!< bit 0 */ -#define NVIC_IABR_ACTIVE_1 ((uint32_t)0x00000002) /*!< bit 1 */ -#define NVIC_IABR_ACTIVE_2 ((uint32_t)0x00000004) /*!< bit 2 */ -#define NVIC_IABR_ACTIVE_3 ((uint32_t)0x00000008) /*!< bit 3 */ -#define NVIC_IABR_ACTIVE_4 ((uint32_t)0x00000010) /*!< bit 4 */ -#define NVIC_IABR_ACTIVE_5 ((uint32_t)0x00000020) /*!< bit 5 */ -#define NVIC_IABR_ACTIVE_6 ((uint32_t)0x00000040) /*!< bit 6 */ -#define NVIC_IABR_ACTIVE_7 ((uint32_t)0x00000080) /*!< bit 7 */ -#define NVIC_IABR_ACTIVE_8 ((uint32_t)0x00000100) /*!< bit 8 */ -#define NVIC_IABR_ACTIVE_9 ((uint32_t)0x00000200) /*!< bit 9 */ -#define NVIC_IABR_ACTIVE_10 ((uint32_t)0x00000400) /*!< bit 10 */ -#define NVIC_IABR_ACTIVE_11 ((uint32_t)0x00000800) /*!< bit 11 */ -#define NVIC_IABR_ACTIVE_12 ((uint32_t)0x00001000) /*!< bit 12 */ -#define NVIC_IABR_ACTIVE_13 ((uint32_t)0x00002000) /*!< bit 13 */ -#define NVIC_IABR_ACTIVE_14 ((uint32_t)0x00004000) /*!< bit 14 */ -#define NVIC_IABR_ACTIVE_15 ((uint32_t)0x00008000) /*!< bit 15 */ -#define NVIC_IABR_ACTIVE_16 ((uint32_t)0x00010000) /*!< bit 16 */ -#define NVIC_IABR_ACTIVE_17 ((uint32_t)0x00020000) /*!< bit 17 */ -#define NVIC_IABR_ACTIVE_18 ((uint32_t)0x00040000) /*!< bit 18 */ -#define NVIC_IABR_ACTIVE_19 ((uint32_t)0x00080000) /*!< bit 19 */ -#define NVIC_IABR_ACTIVE_20 ((uint32_t)0x00100000) /*!< bit 20 */ -#define NVIC_IABR_ACTIVE_21 ((uint32_t)0x00200000) /*!< bit 21 */ -#define NVIC_IABR_ACTIVE_22 ((uint32_t)0x00400000) /*!< bit 22 */ -#define NVIC_IABR_ACTIVE_23 ((uint32_t)0x00800000) /*!< bit 23 */ -#define NVIC_IABR_ACTIVE_24 ((uint32_t)0x01000000) /*!< bit 24 */ -#define NVIC_IABR_ACTIVE_25 ((uint32_t)0x02000000) /*!< bit 25 */ -#define NVIC_IABR_ACTIVE_26 ((uint32_t)0x04000000) /*!< bit 26 */ -#define NVIC_IABR_ACTIVE_27 ((uint32_t)0x08000000) /*!< bit 27 */ -#define NVIC_IABR_ACTIVE_28 ((uint32_t)0x10000000) /*!< bit 28 */ -#define NVIC_IABR_ACTIVE_29 ((uint32_t)0x20000000) /*!< bit 29 */ -#define NVIC_IABR_ACTIVE_30 ((uint32_t)0x40000000) /*!< bit 30 */ -#define NVIC_IABR_ACTIVE_31 ((uint32_t)0x80000000) /*!< bit 31 */ - -/****************** Bit definition for NVIC_PRI0 register *******************/ -#define NVIC_IPR0_PRI_0 ((uint32_t)0x000000FF) /*!< Priority of interrupt 0 */ -#define NVIC_IPR0_PRI_1 ((uint32_t)0x0000FF00) /*!< Priority of interrupt 1 */ -#define NVIC_IPR0_PRI_2 ((uint32_t)0x00FF0000) /*!< Priority of interrupt 2 */ -#define NVIC_IPR0_PRI_3 ((uint32_t)0xFF000000) /*!< Priority of interrupt 3 */ - -/****************** Bit definition for NVIC_PRI1 register *******************/ -#define NVIC_IPR1_PRI_4 ((uint32_t)0x000000FF) /*!< Priority of interrupt 4 */ -#define NVIC_IPR1_PRI_5 ((uint32_t)0x0000FF00) /*!< Priority of interrupt 5 */ -#define NVIC_IPR1_PRI_6 ((uint32_t)0x00FF0000) /*!< Priority of interrupt 6 */ -#define NVIC_IPR1_PRI_7 ((uint32_t)0xFF000000) /*!< Priority of interrupt 7 */ - -/****************** Bit definition for NVIC_PRI2 register *******************/ -#define NVIC_IPR2_PRI_8 ((uint32_t)0x000000FF) /*!< Priority of interrupt 8 */ -#define NVIC_IPR2_PRI_9 ((uint32_t)0x0000FF00) /*!< Priority of interrupt 9 */ -#define NVIC_IPR2_PRI_10 ((uint32_t)0x00FF0000) /*!< Priority of interrupt 10 */ -#define NVIC_IPR2_PRI_11 ((uint32_t)0xFF000000) /*!< Priority of interrupt 11 */ - -/****************** Bit definition for NVIC_PRI3 register *******************/ -#define NVIC_IPR3_PRI_12 ((uint32_t)0x000000FF) /*!< Priority of interrupt 12 */ -#define NVIC_IPR3_PRI_13 ((uint32_t)0x0000FF00) /*!< Priority of interrupt 13 */ -#define NVIC_IPR3_PRI_14 ((uint32_t)0x00FF0000) /*!< Priority of interrupt 14 */ -#define NVIC_IPR3_PRI_15 ((uint32_t)0xFF000000) /*!< Priority of interrupt 15 */ - -/****************** Bit definition for NVIC_PRI4 register *******************/ -#define NVIC_IPR4_PRI_16 ((uint32_t)0x000000FF) /*!< Priority of interrupt 16 */ -#define NVIC_IPR4_PRI_17 ((uint32_t)0x0000FF00) /*!< Priority of interrupt 17 */ -#define NVIC_IPR4_PRI_18 ((uint32_t)0x00FF0000) /*!< Priority of interrupt 18 */ -#define NVIC_IPR4_PRI_19 ((uint32_t)0xFF000000) /*!< Priority of interrupt 19 */ - -/****************** Bit definition for NVIC_PRI5 register *******************/ -#define NVIC_IPR5_PRI_20 ((uint32_t)0x000000FF) /*!< Priority of interrupt 20 */ -#define NVIC_IPR5_PRI_21 ((uint32_t)0x0000FF00) /*!< Priority of interrupt 21 */ -#define NVIC_IPR5_PRI_22 ((uint32_t)0x00FF0000) /*!< Priority of interrupt 22 */ -#define NVIC_IPR5_PRI_23 ((uint32_t)0xFF000000) /*!< Priority of interrupt 23 */ - -/****************** Bit definition for NVIC_PRI6 register *******************/ -#define NVIC_IPR6_PRI_24 ((uint32_t)0x000000FF) /*!< Priority of interrupt 24 */ -#define NVIC_IPR6_PRI_25 ((uint32_t)0x0000FF00) /*!< Priority of interrupt 25 */ -#define NVIC_IPR6_PRI_26 ((uint32_t)0x00FF0000) /*!< Priority of interrupt 26 */ -#define NVIC_IPR6_PRI_27 ((uint32_t)0xFF000000) /*!< Priority of interrupt 27 */ - -/****************** Bit definition for NVIC_PRI7 register *******************/ -#define NVIC_IPR7_PRI_28 ((uint32_t)0x000000FF) /*!< Priority of interrupt 28 */ -#define NVIC_IPR7_PRI_29 ((uint32_t)0x0000FF00) /*!< Priority of interrupt 29 */ -#define NVIC_IPR7_PRI_30 ((uint32_t)0x00FF0000) /*!< Priority of interrupt 30 */ -#define NVIC_IPR7_PRI_31 ((uint32_t)0xFF000000) /*!< Priority of interrupt 31 */ - -/****************** Bit definition for SCB_CPUID register *******************/ -#define SCB_CPUID_REVISION ((uint32_t)0x0000000F) /*!< Implementation defined revision number */ -#define SCB_CPUID_PARTNO ((uint32_t)0x0000FFF0) /*!< Number of processor within family */ -#define SCB_CPUID_Constant ((uint32_t)0x000F0000) /*!< Reads as 0x0F */ -#define SCB_CPUID_VARIANT ((uint32_t)0x00F00000) /*!< Implementation defined variant number */ -#define SCB_CPUID_IMPLEMENTER ((uint32_t)0xFF000000) /*!< Implementer code. ARM is 0x41 */ - -/******************* Bit definition for SCB_ICSR register *******************/ -#define SCB_ICSR_VECTACTIVE ((uint32_t)0x000001FF) /*!< Active ISR number field */ -#define SCB_ICSR_RETTOBASE ((uint32_t)0x00000800) /*!< All active exceptions minus the IPSR_current_exception yields the empty set */ -#define SCB_ICSR_VECTPENDING ((uint32_t)0x003FF000) /*!< Pending ISR number field */ -#define SCB_ICSR_ISRPENDING ((uint32_t)0x00400000) /*!< Interrupt pending flag */ -#define SCB_ICSR_ISRPREEMPT ((uint32_t)0x00800000) /*!< It indicates that a pending interrupt becomes active in the next running cycle */ -#define SCB_ICSR_PENDSTCLR ((uint32_t)0x02000000) /*!< Clear pending SysTick bit */ -#define SCB_ICSR_PENDSTSET ((uint32_t)0x04000000) /*!< Set pending SysTick bit */ -#define SCB_ICSR_PENDSVCLR ((uint32_t)0x08000000) /*!< Clear pending pendSV bit */ -#define SCB_ICSR_PENDSVSET ((uint32_t)0x10000000) /*!< Set pending pendSV bit */ -#define SCB_ICSR_NMIPENDSET ((uint32_t)0x80000000) /*!< Set pending NMI bit */ - -/******************* Bit definition for SCB_VTOR register *******************/ -#define SCB_VTOR_TBLOFF ((uint32_t)0x1FFFFF80) /*!< Vector table base offset field */ -#define SCB_VTOR_TBLBASE ((uint32_t)0x20000000) /*!< Table base in code(0) or RAM(1) */ - -/*!<***************** Bit definition for SCB_AIRCR register *******************/ -#define SCB_AIRCR_VECTRESET ((uint32_t)0x00000001) /*!< System Reset bit */ -#define SCB_AIRCR_VECTCLRACTIVE ((uint32_t)0x00000002) /*!< Clear active vector bit */ -#define SCB_AIRCR_SYSRESETREQ ((uint32_t)0x00000004) /*!< Requests chip control logic to generate a reset */ - -#define SCB_AIRCR_PRIGROUP ((uint32_t)0x00000700) /*!< PRIGROUP[2:0] bits (Priority group) */ -#define SCB_AIRCR_PRIGROUP_0 ((uint32_t)0x00000100) /*!< Bit 0 */ -#define SCB_AIRCR_PRIGROUP_1 ((uint32_t)0x00000200) /*!< Bit 1 */ -#define SCB_AIRCR_PRIGROUP_2 ((uint32_t)0x00000400) /*!< Bit 2 */ - -/* prority group configuration */ -#define SCB_AIRCR_PRIGROUP0 ((uint32_t)0x00000000) /*!< Priority group=0 (7 bits of pre-emption priority, 1 bit of subpriority) */ -#define SCB_AIRCR_PRIGROUP1 ((uint32_t)0x00000100) /*!< Priority group=1 (6 bits of pre-emption priority, 2 bits of subpriority) */ -#define SCB_AIRCR_PRIGROUP2 ((uint32_t)0x00000200) /*!< Priority group=2 (5 bits of pre-emption priority, 3 bits of subpriority) */ -#define SCB_AIRCR_PRIGROUP3 ((uint32_t)0x00000300) /*!< Priority group=3 (4 bits of pre-emption priority, 4 bits of subpriority) */ -#define SCB_AIRCR_PRIGROUP4 ((uint32_t)0x00000400) /*!< Priority group=4 (3 bits of pre-emption priority, 5 bits of subpriority) */ -#define SCB_AIRCR_PRIGROUP5 ((uint32_t)0x00000500) /*!< Priority group=5 (2 bits of pre-emption priority, 6 bits of subpriority) */ -#define SCB_AIRCR_PRIGROUP6 ((uint32_t)0x00000600) /*!< Priority group=6 (1 bit of pre-emption priority, 7 bits of subpriority) */ -#define SCB_AIRCR_PRIGROUP7 ((uint32_t)0x00000700) /*!< Priority group=7 (no pre-emption priority, 8 bits of subpriority) */ - -#define SCB_AIRCR_ENDIANESS ((uint32_t)0x00008000) /*!< Data endianness bit */ -#define SCB_AIRCR_VECTKEY ((uint32_t)0xFFFF0000) /*!< Register key (VECTKEY) - Reads as 0xFA05 (VECTKEYSTAT) */ - -/******************* Bit definition for SCB_SCR register ********************/ -#define SCB_SCR_SLEEPONEXIT ((uint8_t)0x02) /*!< Sleep on exit bit */ -#define SCB_SCR_SLEEPDEEP ((uint8_t)0x04) /*!< Sleep deep bit */ -#define SCB_SCR_SEVONPEND ((uint8_t)0x10) /*!< Wake up from WFE */ - -/******************** Bit definition for SCB_CCR register *******************/ -#define SCB_CCR_NONBASETHRDENA ((uint16_t)0x0001) /*!< Thread mode can be entered from any level in Handler mode by controlled return value */ -#define SCB_CCR_USERSETMPEND ((uint16_t)0x0002) /*!< Enables user code to write the Software Trigger Interrupt register to trigger (pend) a Main exception */ -#define SCB_CCR_UNALIGN_TRP ((uint16_t)0x0008) /*!< Trap for unaligned access */ -#define SCB_CCR_DIV_0_TRP ((uint16_t)0x0010) /*!< Trap on Divide by 0 */ -#define SCB_CCR_BFHFNMIGN ((uint16_t)0x0100) /*!< Handlers running at priority -1 and -2 */ -#define SCB_CCR_STKALIGN ((uint16_t)0x0200) /*!< On exception entry, the SP used prior to the exception is adjusted to be 8-byte aligned */ - -/******************* Bit definition for SCB_SHPR register ********************/ -#define SCB_SHPR_PRI_N ((uint32_t)0x000000FF) /*!< Priority of system handler 4,8, and 12. Mem Manage, reserved and Debug Monitor */ -#define SCB_SHPR_PRI_N1 ((uint32_t)0x0000FF00) /*!< Priority of system handler 5,9, and 13. Bus Fault, reserved and reserved */ -#define SCB_SHPR_PRI_N2 ((uint32_t)0x00FF0000) /*!< Priority of system handler 6,10, and 14. Usage Fault, reserved and PendSV */ -#define SCB_SHPR_PRI_N3 ((uint32_t)0xFF000000) /*!< Priority of system handler 7,11, and 15. Reserved, SVCall and SysTick */ - -/****************** Bit definition for SCB_SHCSR register *******************/ -#define SCB_SHCSR_MEMFAULTACT ((uint32_t)0x00000001) /*!< MemManage is active */ -#define SCB_SHCSR_BUSFAULTACT ((uint32_t)0x00000002) /*!< BusFault is active */ -#define SCB_SHCSR_USGFAULTACT ((uint32_t)0x00000008) /*!< UsageFault is active */ -#define SCB_SHCSR_SVCALLACT ((uint32_t)0x00000080) /*!< SVCall is active */ -#define SCB_SHCSR_MONITORACT ((uint32_t)0x00000100) /*!< Monitor is active */ -#define SCB_SHCSR_PENDSVACT ((uint32_t)0x00000400) /*!< PendSV is active */ -#define SCB_SHCSR_SYSTICKACT ((uint32_t)0x00000800) /*!< SysTick is active */ -#define SCB_SHCSR_USGFAULTPENDED ((uint32_t)0x00001000) /*!< Usage Fault is pended */ -#define SCB_SHCSR_MEMFAULTPENDED ((uint32_t)0x00002000) /*!< MemManage is pended */ -#define SCB_SHCSR_BUSFAULTPENDED ((uint32_t)0x00004000) /*!< Bus Fault is pended */ -#define SCB_SHCSR_SVCALLPENDED ((uint32_t)0x00008000) /*!< SVCall is pended */ -#define SCB_SHCSR_MEMFAULTENA ((uint32_t)0x00010000) /*!< MemManage enable */ -#define SCB_SHCSR_BUSFAULTENA ((uint32_t)0x00020000) /*!< Bus Fault enable */ -#define SCB_SHCSR_USGFAULTENA ((uint32_t)0x00040000) /*!< UsageFault enable */ - -/******************* Bit definition for SCB_CFSR register *******************/ -/*!< MFSR */ -#define SCB_CFSR_IACCVIOL ((uint32_t)0x00000001) /*!< Instruction access violation */ -#define SCB_CFSR_DACCVIOL ((uint32_t)0x00000002) /*!< Data access violation */ -#define SCB_CFSR_MUNSTKERR ((uint32_t)0x00000008) /*!< Unstacking error */ -#define SCB_CFSR_MSTKERR ((uint32_t)0x00000010) /*!< Stacking error */ -#define SCB_CFSR_MMARVALID ((uint32_t)0x00000080) /*!< Memory Manage Address Register address valid flag */ -/*!< BFSR */ -#define SCB_CFSR_IBUSERR ((uint32_t)0x00000100) /*!< Instruction bus error flag */ -#define SCB_CFSR_PRECISERR ((uint32_t)0x00000200) /*!< Precise data bus error */ -#define SCB_CFSR_IMPRECISERR ((uint32_t)0x00000400) /*!< Imprecise data bus error */ -#define SCB_CFSR_UNSTKERR ((uint32_t)0x00000800) /*!< Unstacking error */ -#define SCB_CFSR_STKERR ((uint32_t)0x00001000) /*!< Stacking error */ -#define SCB_CFSR_BFARVALID ((uint32_t)0x00008000) /*!< Bus Fault Address Register address valid flag */ -/*!< UFSR */ -#define SCB_CFSR_UNDEFINSTR ((uint32_t)0x00010000) /*!< The processor attempt to execute an undefined instruction */ -#define SCB_CFSR_INVSTATE ((uint32_t)0x00020000) /*!< Invalid combination of EPSR and instruction */ -#define SCB_CFSR_INVPC ((uint32_t)0x00040000) /*!< Attempt to load EXC_RETURN into pc illegally */ -#define SCB_CFSR_NOCP ((uint32_t)0x00080000) /*!< Attempt to use a coprocessor instruction */ -#define SCB_CFSR_UNALIGNED ((uint32_t)0x01000000) /*!< Fault occurs when there is an attempt to make an unaligned memory access */ -#define SCB_CFSR_DIVBYZERO ((uint32_t)0x02000000) /*!< Fault occurs when SDIV or DIV instruction is used with a divisor of 0 */ - -/******************* Bit definition for SCB_HFSR register *******************/ -#define SCB_HFSR_VECTTBL ((uint32_t)0x00000002) /*!< Fault occurs because of vector table read on exception processing */ -#define SCB_HFSR_FORCED ((uint32_t)0x40000000) /*!< Hard Fault activated when a configurable Fault was received and cannot activate */ -#define SCB_HFSR_DEBUGEVT ((uint32_t)0x80000000) /*!< Fault related to debug */ - -/******************* Bit definition for SCB_DFSR register *******************/ -#define SCB_DFSR_HALTED ((uint8_t)0x01) /*!< Halt request flag */ -#define SCB_DFSR_BKPT ((uint8_t)0x02) /*!< BKPT flag */ -#define SCB_DFSR_DWTTRAP ((uint8_t)0x04) /*!< Data Watchpoint and Trace (DWT) flag */ -#define SCB_DFSR_VCATCH ((uint8_t)0x08) /*!< Vector catch flag */ -#define SCB_DFSR_EXTERNAL ((uint8_t)0x10) /*!< External debug request flag */ - -/******************* Bit definition for SCB_MMFAR register ******************/ -#define SCB_MMFAR_ADDRESS ((uint32_t)0xFFFFFFFF) /*!< Mem Manage fault address field */ - -/******************* Bit definition for SCB_BFAR register *******************/ -#define SCB_BFAR_ADDRESS ((uint32_t)0xFFFFFFFF) /*!< Bus fault address field */ - -/******************* Bit definition for SCB_afsr register *******************/ -#define SCB_AFSR_IMPDEF ((uint32_t)0xFFFFFFFF) /*!< Implementation defined */ - - -/******************************************************************************/ -/* */ -/* External Interrupt/Event Controller (EXTI) */ -/* */ -/******************************************************************************/ - -/******************* Bit definition for EXTI_IER register *******************/ -#define EXTI_IER_IER0 ((uint32_t)0x00000001) /*!< Interrupt Enable Control on line 0 */ -#define EXTI_IER_IER1 ((uint32_t)0x00000002) /*!< Interrupt Enable Control on line 1 */ -#define EXTI_IER_IER2 ((uint32_t)0x00000004) /*!< Interrupt Enable Control on line 2 */ -#define EXTI_IER_IER3 ((uint32_t)0x00000008) /*!< Interrupt Enable Control on line 3 */ -#define EXTI_IER_IER4 ((uint32_t)0x00000010) /*!< Interrupt Enable Control on line 4 */ -#define EXTI_IER_IER5 ((uint32_t)0x00000020) /*!< Interrupt Enable Control on line 5 */ -#define EXTI_IER_IER6 ((uint32_t)0x00000040) /*!< Interrupt Enable Control on line 6 */ -#define EXTI_IER_IER7 ((uint32_t)0x00000080) /*!< Interrupt Enable Control on line 7 */ -#define EXTI_IER_IER8 ((uint32_t)0x00000100) /*!< Interrupt Enable Control on line 8 */ -#define EXTI_IER_IER9 ((uint32_t)0x00000200) /*!< Interrupt Enable Control on line 9 */ -#define EXTI_IER_IER10 ((uint32_t)0x00000400) /*!< Interrupt Enable Control on line 10 */ -#define EXTI_IER_IER11 ((uint32_t)0x00000800) /*!< Interrupt Enable Control on line 11 */ -#define EXTI_IER_IER12 ((uint32_t)0x00001000) /*!< Interrupt Enable Control on line 12 */ -#define EXTI_IER_IER13 ((uint32_t)0x00002000) /*!< Interrupt Enable Control on line 13 */ -#define EXTI_IER_IER14 ((uint32_t)0x00004000) /*!< Interrupt Enable Control on line 14 */ -#define EXTI_IER_IER15 ((uint32_t)0x00008000) /*!< Interrupt Enable Control on line 15 */ -#define EXTI_IER_IER16 ((uint32_t)0x00010000) /*!< Interrupt Enable Control on line 16 */ -#define EXTI_IER_IER17 ((uint32_t)0x00020000) /*!< Interrupt Enable Control on line 17 */ -#define EXTI_IER_IER18 ((uint32_t)0x00040000) /*!< Interrupt Enable Control on line 18 */ - -#define EXTI_IER_IER19 ((uint32_t)0x00080000) /*!< Interrupt Enable Control on line 19 */ - -/****************** Bit definition for EXTI_EER register ********************/ -#define EXTI_EER_EER0 ((uint32_t)0x00000001) /*!< Event Enable Control on line 0 */ -#define EXTI_EER_EER1 ((uint32_t)0x00000002) /*!< Event Enable Control on line 1 */ -#define EXTI_EER_EER2 ((uint32_t)0x00000004) /*!< Event Enable Control on line 2 */ -#define EXTI_EER_EER3 ((uint32_t)0x00000008) /*!< Event Enable Control on line 3 */ -#define EXTI_EER_EER4 ((uint32_t)0x00000010) /*!< Event Enable Control on line 4 */ -#define EXTI_EER_EER5 ((uint32_t)0x00000020) /*!< Event Enable Control on line 5 */ -#define EXTI_EER_EER6 ((uint32_t)0x00000040) /*!< Event Enable Control on line 6 */ -#define EXTI_EER_EER7 ((uint32_t)0x00000080) /*!< Event Enable Control on line 7 */ -#define EXTI_EER_EER8 ((uint32_t)0x00000100) /*!< Event Enable Control on line 8 */ -#define EXTI_EER_EER9 ((uint32_t)0x00000200) /*!< Event Enable Control on line 9 */ -#define EXTI_EER_EER10 ((uint32_t)0x00000400) /*!< Event Enable Control on line 10 */ -#define EXTI_EER_EER11 ((uint32_t)0x00000800) /*!< Event Enable Control on line 11 */ -#define EXTI_EER_EER12 ((uint32_t)0x00001000) /*!< Event Enable Control on line 12 */ -#define EXTI_EER_EER13 ((uint32_t)0x00002000) /*!< Event Enable Control on line 13 */ -#define EXTI_EER_EER14 ((uint32_t)0x00004000) /*!< Event Enable Control on line 14 */ -#define EXTI_EER_EER15 ((uint32_t)0x00008000) /*!< Event Enable Control on line 15 */ -#define EXTI_EER_EER16 ((uint32_t)0x00010000) /*!< Event Enable Control on line 16 */ -#define EXTI_EER_EER17 ((uint32_t)0x00020000) /*!< Event Enable Control on line 17 */ -#define EXTI_EER_EER18 ((uint32_t)0x00040000) /*!< Event Enable Control on line 18 */ - -#define EXTI_EER_EER19 ((uint32_t)0x00080000) /*!< Event Enable Control on line 19 */ - -/******************* Bit definition for EXTI_RTE register ******************/ -#define EXTI_RTE_RTE0 ((uint32_t)0x00000001) /*!< Rising Edge Trigger Enabled for line 0 */ -#define EXTI_RTE_RTE1 ((uint32_t)0x00000002) /*!< Rising Edge Trigger Enabled for line 1 */ -#define EXTI_RTE_RTE2 ((uint32_t)0x00000004) /*!< Rising Edge Trigger Enabled for line 2 */ -#define EXTI_RTE_RTE3 ((uint32_t)0x00000008) /*!< Rising Edge Trigger Enabled for line 3 */ -#define EXTI_RTE_RTE4 ((uint32_t)0x00000010) /*!< Rising Edge Trigger Enabled for line 4 */ -#define EXTI_RTE_RTE5 ((uint32_t)0x00000020) /*!< Rising Edge Trigger Enabled for line 5 */ -#define EXTI_RTE_RTE6 ((uint32_t)0x00000040) /*!< Rising Edge Trigger Enabled for line 6 */ -#define EXTI_RTE_RTE7 ((uint32_t)0x00000080) /*!< Rising Edge Trigger Enabled for line 7 */ -#define EXTI_RTE_RTE8 ((uint32_t)0x00000100) /*!< Rising Edge Trigger Enabled for line 8 */ -#define EXTI_RTE_RTE9 ((uint32_t)0x00000200) /*!< Rising Edge Trigger Enabled for line 9 */ -#define EXTI_RTE_RTE10 ((uint32_t)0x00000400) /*!< Rising Edge Trigger Enabled for line 10 */ -#define EXTI_RTE_RTE11 ((uint32_t)0x00000800) /*!< Rising Edge Trigger Enabled for line 11 */ -#define EXTI_RTE_RTE12 ((uint32_t)0x00001000) /*!< Rising Edge Trigger Enabled for line 12 */ -#define EXTI_RTE_RTE13 ((uint32_t)0x00002000) /*!< Rising Edge Trigger Enabled for line 13 */ -#define EXTI_RTE_RTE14 ((uint32_t)0x00004000) /*!< Rising Edge Trigger Enabled for line 14 */ -#define EXTI_RTE_RTE15 ((uint32_t)0x00008000) /*!< Rising Edge Trigger Enabled for line 15 */ -#define EXTI_RTE_RTE16 ((uint32_t)0x00010000) /*!< Rising Edge Trigger Enabled for line 16 */ -#define EXTI_RTE_RTE17 ((uint32_t)0x00020000) /*!< Rising Edge Trigger Enabled for line 17 */ -#define EXTI_RTE_RTE18 ((uint32_t)0x00040000) /*!< Rising Edge Trigger Enabled for line 18 */ - -#define EXTI_RTE_RTE19 ((uint32_t)0x00080000) /*!< Rising Edge Trigger Enabled for line 19 */ - -/******************* Bit definition for EXTI_FTE register *******************/ -#define EXTI_FTE_FTE0 ((uint32_t)0x00000001) /*!< Falling Edge Trigger Enabled for line 0 */ -#define EXTI_FTE_FTE1 ((uint32_t)0x00000002) /*!< Falling Edge Trigger Enabled for line 1 */ -#define EXTI_FTE_FTE2 ((uint32_t)0x00000004) /*!< Falling Edge Trigger Enabled for line 2 */ -#define EXTI_FTE_FTE3 ((uint32_t)0x00000008) /*!< Falling Edge Trigger Enabled for line 3 */ -#define EXTI_FTE_FTE4 ((uint32_t)0x00000010) /*!< Falling Edge Trigger Enabled for line 4 */ -#define EXTI_FTE_FTE5 ((uint32_t)0x00000020) /*!< Falling Edge Trigger Enabled for line 5 */ -#define EXTI_FTE_FTE6 ((uint32_t)0x00000040) /*!< Falling Edge Trigger Enabled for line 6 */ -#define EXTI_FTE_FTE7 ((uint32_t)0x00000080) /*!< Falling Edge Trigger Enabled for line 7 */ -#define EXTI_FTE_FTE8 ((uint32_t)0x00000100) /*!< Falling Edge Trigger Enabled for line 8 */ -#define EXTI_FTE_FTE9 ((uint32_t)0x00000200) /*!< Falling Edge Trigger Enabled for line 9 */ -#define EXTI_FTE_FTE10 ((uint32_t)0x00000400) /*!< Falling Edge Trigger Enabled for line 10 */ -#define EXTI_FTE_FTE11 ((uint32_t)0x00000800) /*!< Falling Edge Trigger Enabled for line 11 */ -#define EXTI_FTE_FTE12 ((uint32_t)0x00001000) /*!< Falling Edge Trigger Enabled for line 12 */ -#define EXTI_FTE_FTE13 ((uint32_t)0x00002000) /*!< Falling Edge Trigger Enabled for line 13 */ -#define EXTI_FTE_FTE14 ((uint32_t)0x00004000) /*!< Falling Edge Trigger Enabled for line 14 */ -#define EXTI_FTE_FTE15 ((uint32_t)0x00008000) /*!< Falling Edge Trigger Enabled for line 15 */ -#define EXTI_FTE_FTE16 ((uint32_t)0x00010000) /*!< Falling Edge Trigger Enabled for line 16 */ -#define EXTI_FTE_FTE17 ((uint32_t)0x00020000) /*!< Falling Edge Trigger Enabled for line 17 */ -#define EXTI_FTE_FTE18 ((uint32_t)0x00040000) /*!< Falling Edge Trigger Enabled for line 18 */ - -#define EXTI_FTE_FTE19 ((uint32_t)0x00080000) /*!< Falling Edge Trigger Enabled for line 19 */ - -/******************* Bit definition for EXTI_SIE register *******************/ -#define EXTI_SIE_SIE0 ((uint32_t)0x00000001) /*!< Interrupt/Event Software Trigger on line 0 */ -#define EXTI_SIE_SIE1 ((uint32_t)0x00000002) /*!< Interrupt/Event Software Trigger on line 1 */ -#define EXTI_SIE_SIE2 ((uint32_t)0x00000004) /*!< Interrupt/Event Software Trigger on line 2 */ -#define EXTI_SIE_SIE3 ((uint32_t)0x00000008) /*!< Interrupt/Event Software Trigger on line 3 */ -#define EXTI_SIE_SIE4 ((uint32_t)0x00000010) /*!< Interrupt/Event Software Trigger on line 4 */ -#define EXTI_SIE_SIE5 ((uint32_t)0x00000020) /*!< Interrupt/Event Software Trigger on line 5 */ -#define EXTI_SIE_SIE6 ((uint32_t)0x00000040) /*!< Interrupt/Event Software Trigger on line 6 */ -#define EXTI_SIE_SIE7 ((uint32_t)0x00000080) /*!< Interrupt/Event Software Trigger on line 7 */ -#define EXTI_SIE_SIE8 ((uint32_t)0x00000100) /*!< Interrupt/Event Software Trigger on line 8 */ -#define EXTI_SIE_SIE9 ((uint32_t)0x00000200) /*!< Interrupt/Event Software Trigger on line 9 */ -#define EXTI_SIE_SIE10 ((uint32_t)0x00000400) /*!< Interrupt/Event Software Trigger on line 10 */ -#define EXTI_SIE_SIE11 ((uint32_t)0x00000800) /*!< Interrupt/Event Software Trigger on line 11 */ -#define EXTI_SIE_SIE12 ((uint32_t)0x00001000) /*!< Interrupt/Event Software Trigger on line 12 */ -#define EXTI_SIE_SIE13 ((uint32_t)0x00002000) /*!< Interrupt/Event Software Trigger on line 13 */ -#define EXTI_SIE_SIE14 ((uint32_t)0x00004000) /*!< Interrupt/Event Software Trigger on line 14 */ -#define EXTI_SIE_SIE15 ((uint32_t)0x00008000) /*!< Interrupt/Event Software Trigger on line 15 */ -#define EXTI_SIE_SIE16 ((uint32_t)0x00010000) /*!< Interrupt/Event Software Trigger on line 16 */ -#define EXTI_SIE_SIE17 ((uint32_t)0x00020000) /*!< Interrupt/Event Software Trigger on line 17 */ -#define EXTI_SIE_SIE18 ((uint32_t)0x00040000) /*!< Interrupt/Event Software Trigger on line 18 */ - -#define EXTI_SIE_SIE19 ((uint32_t)0x00080000) /*!< Interrupt/Event Software Trigger on line 19 */ - -/****************** Bit definition for EXTI_PD register *********************/ -#define EXTI_PD_PD0 ((uint32_t)0x00000001) /*!< Interrupt/Event Pending Status on line 0 */ -#define EXTI_PD_PD1 ((uint32_t)0x00000002) /*!< Interrupt/Event Pending Status on line 1 */ -#define EXTI_PD_PD2 ((uint32_t)0x00000004) /*!< Interrupt/Event Pending Status on line 2 */ -#define EXTI_PD_PD3 ((uint32_t)0x00000008) /*!< Interrupt/Event Pending Status on line 3 */ -#define EXTI_PD_PD4 ((uint32_t)0x00000010) /*!< Interrupt/Event Pending Status on line 4 */ -#define EXTI_PD_PD5 ((uint32_t)0x00000020) /*!< Interrupt/Event Pending Status on line 5 */ -#define EXTI_PD_PD6 ((uint32_t)0x00000040) /*!< Interrupt/Event Pending Status on line 6 */ -#define EXTI_PD_PD7 ((uint32_t)0x00000080) /*!< Interrupt/Event Pending Status on line 7 */ -#define EXTI_PD_PD8 ((uint32_t)0x00000100) /*!< Interrupt/Event Pending Status on line 8 */ -#define EXTI_PD_PD9 ((uint32_t)0x00000200) /*!< Interrupt/Event Pending Status on line 9 */ -#define EXTI_PD_PD10 ((uint32_t)0x00000400) /*!< Interrupt/Event Pending Status on line 10 */ -#define EXTI_PD_PD11 ((uint32_t)0x00000800) /*!< Interrupt/Event Pending Status on line 11 */ -#define EXTI_PD_PD12 ((uint32_t)0x00001000) /*!< Interrupt/Event Pending Status on line 12 */ -#define EXTI_PD_PD13 ((uint32_t)0x00002000) /*!< Interrupt/Event Pending Status on line 13 */ -#define EXTI_PD_PD14 ((uint32_t)0x00004000) /*!< Interrupt/Event Pending Status on line 14 */ -#define EXTI_PD_PD15 ((uint32_t)0x00008000) /*!< Interrupt/Event Pending Status on line 15 */ -#define EXTI_PD_PD16 ((uint32_t)0x00010000) /*!< Interrupt/Event Pending Status on line 16 */ -#define EXTI_PD_PD17 ((uint32_t)0x00020000) /*!< Interrupt/Event Pending Status on line 17 */ -#define EXTI_PD_PD18 ((uint32_t)0x00040000) /*!< Interrupt/Event Pending Status on line 18 */ - -#define EXTI_PD_PD19 ((uint32_t)0x00080000) /*!< Interrupt/Event Pending Status on line 19 */ - -/******************************************************************************/ -/* */ -/* FMC Registers */ -/* */ -/******************************************************************************/ - -/******************* Bit definition for FMC_RESR register ******************/ -#define FMC_RESR_WSCNT ((uint32_t)0x00000007) /*!< LATENCY bit (Latency) */ - -/****************** Bit definition for FMC_UKEYR register ******************/ -#define FMC_UKEYR_UKEY ((uint32_t)0xFFFFFFFF) /*!< FPEC Key */ - -/***************** Bit definition for FMC_OBKEYR register ****************/ -#define FMC_OBKEYR_OBKEY ((uint32_t)0xFFFFFFFF) /*!< Option Byte Key */ - -/****************** FMC Keys **********************************************/ -#define FMC_KEY1 ((uint32_t)0x45670123) /*!< Flash program erase key1 */ -#define FMC_KEY2 ((uint32_t)0xCDEF89AB) /*!< Flash program erase key2 */ - -/****************** Bit definition for FMC_CSR register *******************/ -#define FMC_CSR_BUSY ((uint32_t)0x00000001) /*!< Busy */ -#define FMC_CSR_PGEF ((uint32_t)0x00000004) /*!< Programming Error */ -#define FMC_CSR_WPEF ((uint32_t)0x00000010) /*!< Write Protection Error */ -#define FMC_CSR_ENDF ((uint32_t)0x00000020) /*!< End of operation */ -#define FMC_CSR2_BUSY ((uint32_t)0x80000001) /*!< Busy For Bank2 */ -#define FMC_CSR2_PGEF ((uint32_t)0x80000004) /*!< Programming Error For Bank2*/ -#define FMC_CSR2_WPEF ((uint32_t)0x80000010) /*!< Write Protection Error For Bank2*/ -#define FMC_CSR2_ENDF ((uint32_t)0x80000020) /*!< End of operation For Bank2*/ - -/******************* Bit definition for FMC_CMR register *******************/ -#define FMC_CMR_PG ((uint32_t)0x00000001) /*!< Programming */ -#define FMC_CMR_PE ((uint32_t)0x00000002) /*!< Page Erase */ -#define FMC_CMR_ME ((uint32_t)0x00000004) /*!< Mass Erase */ -#define FMC_CMR_OBPG ((uint32_t)0x00000010) /*!< Option Byte Programming */ -#define FMC_CMR_OBER ((uint32_t)0x00000020) /*!< Option Byte Erase */ -#define FMC_CMR_START ((uint32_t)0x00000040) /*!< Start */ -#define FMC_CMR_LK ((uint32_t)0x00000080) /*!< Lock */ -#define FMC_CMR_OBWE ((uint32_t)0x00000200) /*!< Option Bytes Write Enable */ -#define FMC_CMR_ERIE ((uint32_t)0x00000400) /*!< Error Interrupt Enable */ -#define FMC_CMR_ENDIE ((uint32_t)0x00001000) /*!< End of operation interrupt enable */ -#define FMC_CMR_OPTR ((uint32_t)0x00002000) /*!< Option Bytes Loader Launch */ - -/******************* Bit definition for FMC_AR register *******************/ -#define FMC_AR_AR ((uint32_t)0xFFFFFFFF) /*!< Flash Address */ - -/****************** Bit definition for FMC_OPTR register *******************/ -#define FMC_OPTR_OBER ((uint32_t)0x00000001) /*!< Option Byte Error */ -#define FMC_OPTR_PLEVEL1 ((uint32_t)0x00000002) /*!< Read protection Level 1 */ -#define FMC_OPTR_OB_USER ((uint32_t)0x00003700) /*!< User Option Bytes */ - -/****************** Bit definition for FMC_WPR register ******************/ -#define FMC_WPR_WRP ((uint32_t)0xFFFFFFFF) /*!< Write Protect */ - -/*----------------------------------------------------------------------------*/ - -/****************** Bit definition for OB_RDP register **********************/ -#define OB_RDP_RDP ((uint32_t)0x000000FF) /*!< Read protection option byte */ -#define OB_RDP_nRDP ((uint32_t)0x0000FF00) /*!< Read protection complemented option byte */ - -/****************** Bit definition for OB_USER register *********************/ -#define OB_USER_USER ((uint32_t)0x00FF0000) /*!< User option byte */ -#define OB_USER_nUSER ((uint32_t)0xFF000000) /*!< User complemented option byte */ - -/****************** Bit definition for OB_WRP0 register *********************/ -#define OB_WRP0_WRP0 ((uint32_t)0x000000FF) /*!< Flash memory write protection option bytes */ -#define OB_WRP0_nWRP0 ((uint32_t)0x0000FF00) /*!< Flash memory write protection complemented option bytes */ - -/****************** Bit definition for OB_WRP1 register *********************/ -#define OB_WRP1_WRP1 ((uint32_t)0x00FF0000) /*!< Flash memory write protection option bytes */ -#define OB_WRP1_nWRP1 ((uint32_t)0xFF000000) /*!< Flash memory write protection complemented option bytes */ - -/****************** Bit definition for OB_WRP2 register *********************/ -#define OB_WRP2_WRP2 ((uint32_t)0x000000FF) /*!< Flash memory write protection option bytes */ -#define OB_WRP2_nWRP2 ((uint32_t)0x0000FF00) /*!< Flash memory write protection complemented option bytes */ - -/****************** Bit definition for OB_WRP3 register *********************/ -#define OB_WRP3_WRP3 ((uint32_t)0x00FF0000) /*!< Flash memory write protection option bytes */ -#define OB_WRP3_nWRP3 ((uint32_t)0xFF000000) /*!< Flash memory write protection complemented option bytes */ - -/******************************************************************************/ -/* */ -/* General Purpose IOs (GPIO) */ -/* */ -/******************************************************************************/ - -/******************* Bit definition for GPIO_CTLR1 register *******************/ -#define GPIO_CTLR1_MD ((uint32_t)0x33333333) /*!< Port x mode bits */ - -#define GPIO_CTLR1_MD0 ((uint32_t)0x00000003) /*!< MODE0[1:0] bits (Port x mode bits, pin 0) */ -#define GPIO_CTLR1_MD0_0 ((uint32_t)0x00000001) /*!< Bit 0 */ -#define GPIO_CTLR1_MD0_1 ((uint32_t)0x00000002) /*!< Bit 1 */ - -#define GPIO_CTLR1_MD1 ((uint32_t)0x00000030) /*!< MODE1[1:0] bits (Port x mode bits, pin 1) */ -#define GPIO_CTLR1_MD1_0 ((uint32_t)0x00000010) /*!< Bit 0 */ -#define GPIO_CTLR1_MD1_1 ((uint32_t)0x00000020) /*!< Bit 1 */ - -#define GPIO_CTLR1_MD2 ((uint32_t)0x00000300) /*!< MODE2[1:0] bits (Port x mode bits, pin 2) */ -#define GPIO_CTLR1_MD2_0 ((uint32_t)0x00000100) /*!< Bit 0 */ -#define GPIO_CTLR1_MD2_1 ((uint32_t)0x00000200) /*!< Bit 1 */ - -#define GPIO_CTLR1_MD3 ((uint32_t)0x00003000) /*!< MODE3[1:0] bits (Port x mode bits, pin 3) */ -#define GPIO_CTLR1_MD3_0 ((uint32_t)0x00001000) /*!< Bit 0 */ -#define GPIO_CTLR1_MD3_1 ((uint32_t)0x00002000) /*!< Bit 1 */ - -#define GPIO_CTLR1_MD4 ((uint32_t)0x00030000) /*!< MODE4[1:0] bits (Port x mode bits, pin 4) */ -#define GPIO_CTLR1_MD4_0 ((uint32_t)0x00010000) /*!< Bit 0 */ -#define GPIO_CTLR1_MD4_1 ((uint32_t)0x00020000) /*!< Bit 1 */ - -#define GPIO_CTLR1_MD5 ((uint32_t)0x00300000) /*!< MODE5[1:0] bits (Port x mode bits, pin 5) */ -#define GPIO_CTLR1_MD5_0 ((uint32_t)0x00100000) /*!< Bit 0 */ -#define GPIO_CTLR1_MD5_1 ((uint32_t)0x00200000) /*!< Bit 1 */ - -#define GPIO_CTLR1_MD6 ((uint32_t)0x03000000) /*!< MODE6[1:0] bits (Port x mode bits, pin 6) */ -#define GPIO_CTLR1_MD6_0 ((uint32_t)0x01000000) /*!< Bit 0 */ -#define GPIO_CTLR1_MD6_1 ((uint32_t)0x02000000) /*!< Bit 1 */ - -#define GPIO_CTLR1_MD7 ((uint32_t)0x30000000) /*!< MODE7[1:0] bits (Port x mode bits, pin 7) */ -#define GPIO_CTLR1_MD7_0 ((uint32_t)0x10000000) /*!< Bit 0 */ -#define GPIO_CTLR1_MD7_1 ((uint32_t)0x20000000) /*!< Bit 1 */ - -#define GPIO_CTLR1_CF ((uint32_t)0xCCCCCCCC) /*!< Port x configuration bits */ - -#define GPIO_CTLR1_CF0 ((uint32_t)0x0000000C) /*!< CNF0[1:0] bits (Port x configuration bits, pin 0) */ -#define GPIO_CTLR1_CF0_0 ((uint32_t)0x00000004) /*!< Bit 0 */ -#define GPIO_CTLR1_CF0_1 ((uint32_t)0x00000008) /*!< Bit 1 */ - -#define GPIO_CTLR1_CF1 ((uint32_t)0x000000C0) /*!< CNF1[1:0] bits (Port x configuration bits, pin 1) */ -#define GPIO_CTLR1_CF1_0 ((uint32_t)0x00000040) /*!< Bit 0 */ -#define GPIO_CTLR1_CF1_1 ((uint32_t)0x00000080) /*!< Bit 1 */ - -#define GPIO_CTLR1_CF2 ((uint32_t)0x00000C00) /*!< CNF2[1:0] bits (Port x configuration bits, pin 2) */ -#define GPIO_CTLR1_CF2_0 ((uint32_t)0x00000400) /*!< Bit 0 */ -#define GPIO_CTLR1_CF2_1 ((uint32_t)0x00000800) /*!< Bit 1 */ - -#define GPIO_CTLR1_CF3 ((uint32_t)0x0000C000) /*!< CNF3[1:0] bits (Port x configuration bits, pin 3) */ -#define GPIO_CTLR1_CF3_0 ((uint32_t)0x00004000) /*!< Bit 0 */ -#define GPIO_CTLR1_CF3_1 ((uint32_t)0x00008000) /*!< Bit 1 */ - -#define GPIO_CTLR1_CF4 ((uint32_t)0x000C0000) /*!< CNF4[1:0] bits (Port x configuration bits, pin 4) */ -#define GPIO_CTLR1_CF4_0 ((uint32_t)0x00040000) /*!< Bit 0 */ -#define GPIO_CTLR1_CF4_1 ((uint32_t)0x00080000) /*!< Bit 1 */ - -#define GPIO_CTLR1_CF5 ((uint32_t)0x00C00000) /*!< CNF5[1:0] bits (Port x configuration bits, pin 5) */ -#define GPIO_CTLR1_CF5_0 ((uint32_t)0x00400000) /*!< Bit 0 */ -#define GPIO_CTLR1_CF5_1 ((uint32_t)0x00800000) /*!< Bit 1 */ - -#define GPIO_CTLR1_CF6 ((uint32_t)0x0C000000) /*!< CNF6[1:0] bits (Port x configuration bits, pin 6) */ -#define GPIO_CTLR1_CF6_0 ((uint32_t)0x04000000) /*!< Bit 0 */ -#define GPIO_CTLR1_CF6_1 ((uint32_t)0x08000000) /*!< Bit 1 */ - -#define GPIO_CTLR1_CF7 ((uint32_t)0xC0000000) /*!< CNF7[1:0] bits (Port x configuration bits, pin 7) */ -#define GPIO_CTLR1_CF7_0 ((uint32_t)0x40000000) /*!< Bit 0 */ -#define GPIO_CTLR1_CF7_1 ((uint32_t)0x80000000) /*!< Bit 1 */ - -/******************* Bit definition for GPIO_CRH register *******************/ -#define GPIO_CTLR2_MD ((uint32_t)0x33333333) /*!< Port x mode bits */ - -#define GPIO_CTLR2_MD8 ((uint32_t)0x00000003) /*!< MODE8[1:0] bits (Port x mode bits, pin 8) */ -#define GPIO_CTLR2_MD8_0 ((uint32_t)0x00000001) /*!< Bit 0 */ -#define GPIO_CTLR2_MD8_1 ((uint32_t)0x00000002) /*!< Bit 1 */ - -#define GPIO_CTLR2_MD9 ((uint32_t)0x00000030) /*!< MODE9[1:0] bits (Port x mode bits, pin 9) */ -#define GPIO_CTLR2_MD9_0 ((uint32_t)0x00000010) /*!< Bit 0 */ -#define GPIO_CTLR2_MD9_1 ((uint32_t)0x00000020) /*!< Bit 1 */ - -#define GPIO_CTLR2_MD10 ((uint32_t)0x00000300) /*!< MODE10[1:0] bits (Port x mode bits, pin 10) */ -#define GPIO_CTLR2_MD10_0 ((uint32_t)0x00000100) /*!< Bit 0 */ -#define GPIO_CTLR2_MD10_1 ((uint32_t)0x00000200) /*!< Bit 1 */ - -#define GPIO_CTLR2_MD11 ((uint32_t)0x00003000) /*!< MODE11[1:0] bits (Port x mode bits, pin 11) */ -#define GPIO_CTLR2_MD11_0 ((uint32_t)0x00001000) /*!< Bit 0 */ -#define GPIO_CTLR2_MD11_1 ((uint32_t)0x00002000) /*!< Bit 1 */ - -#define GPIO_CTLR2_MD12 ((uint32_t)0x00030000) /*!< MODE12[1:0] bits (Port x mode bits, pin 12) */ -#define GPIO_CTLR2_MD12_0 ((uint32_t)0x00010000) /*!< Bit 0 */ -#define GPIO_CTLR2_MD12_1 ((uint32_t)0x00020000) /*!< Bit 1 */ - -#define GPIO_CTLR2_MD13 ((uint32_t)0x00300000) /*!< MODE13[1:0] bits (Port x mode bits, pin 13) */ -#define GPIO_CTLR2_MD13_0 ((uint32_t)0x00100000) /*!< Bit 0 */ -#define GPIO_CTLR2_MD13_1 ((uint32_t)0x00200000) /*!< Bit 1 */ - -#define GPIO_CTLR2_MD14 ((uint32_t)0x03000000) /*!< MODE14[1:0] bits (Port x mode bits, pin 14) */ -#define GPIO_CTLR2_MD14_0 ((uint32_t)0x01000000) /*!< Bit 0 */ -#define GPIO_CTLR2_MD14_1 ((uint32_t)0x02000000) /*!< Bit 1 */ - -#define GPIO_CTLR2_MD15 ((uint32_t)0x30000000) /*!< MODE15[1:0] bits (Port x mode bits, pin 15) */ -#define GPIO_CTLR2_MD15_0 ((uint32_t)0x10000000) /*!< Bit 0 */ -#define GPIO_CTLR2_MD15_1 ((uint32_t)0x20000000) /*!< Bit 1 */ - - -#define GPIO_CTLR2_CF ((uint32_t)0xCCCCCCCC) /*!< Port x configuration bits */ - -#define GPIO_CTLR2_CF8 ((uint32_t)0x0000000C) /*!< CNF8[1:0] bits (Port x configuration bits, pin 8) */ -#define GPIO_CTLR2_CF8_0 ((uint32_t)0x00000004) /*!< Bit 0 */ -#define GPIO_CTLR2_CF8_1 ((uint32_t)0x00000008) /*!< Bit 1 */ - -#define GPIO_CTLR2_CF9 ((uint32_t)0x000000C0) /*!< CNF9[1:0] bits (Port x configuration bits, pin 9) */ -#define GPIO_CTLR2_CF9_0 ((uint32_t)0x00000040) /*!< Bit 0 */ -#define GPIO_CTLR2_CF9_1 ((uint32_t)0x00000080) /*!< Bit 1 */ - -#define GPIO_CTLR2_CF10 ((uint32_t)0x00000C00) /*!< CNF10[1:0] bits (Port x configuration bits, pin 10) */ -#define GPIO_CTLR2_CF10_0 ((uint32_t)0x00000400) /*!< Bit 0 */ -#define GPIO_CTLR2_CF10_1 ((uint32_t)0x00000800) /*!< Bit 1 */ - -#define GPIO_CTLR2_CF11 ((uint32_t)0x0000C000) /*!< CNF11[1:0] bits (Port x configuration bits, pin 11) */ -#define GPIO_CTLR2_CF11_0 ((uint32_t)0x00004000) /*!< Bit 0 */ -#define GPIO_CTLR2_CF11_1 ((uint32_t)0x00008000) /*!< Bit 1 */ - -#define GPIO_CTLR2_CF12 ((uint32_t)0x000C0000) /*!< CNF12[1:0] bits (Port x configuration bits, pin 12) */ -#define GPIO_CTLR2_CF12_0 ((uint32_t)0x00040000) /*!< Bit 0 */ -#define GPIO_CTLR2_CF12_1 ((uint32_t)0x00080000) /*!< Bit 1 */ - -#define GPIO_CTLR2_CF13 ((uint32_t)0x00C00000) /*!< CNF13[1:0] bits (Port x configuration bits, pin 13) */ -#define GPIO_CTLR2_CF13_0 ((uint32_t)0x00400000) /*!< Bit 0 */ -#define GPIO_CTLR2_CF13_1 ((uint32_t)0x00800000) /*!< Bit 1 */ - -#define GPIO_CTLR2_CF14 ((uint32_t)0x0C000000) /*!< CNF14[1:0] bits (Port x configuration bits, pin 14) */ -#define GPIO_CTLR2_CF14_0 ((uint32_t)0x04000000) /*!< Bit 0 */ -#define GPIO_CTLR2_CF14_1 ((uint32_t)0x08000000) /*!< Bit 1 */ - -#define GPIO_CTLR2_CF15 ((uint32_t)0xC0000000) /*!< CNF15[1:0] bits (Port x configuration bits, pin 15) */ -#define GPIO_CTLR2_CF15_0 ((uint32_t)0x40000000) /*!< Bit 0 */ -#define GPIO_CTLR2_CF15_1 ((uint32_t)0x80000000) /*!< Bit 1 */ - -/*!<****************** Bit definition for GPIO_DIR register *******************/ -#define GPIO_DIR_DIR0 ((uint16_t)0x0001) /*!< Port input data, bit 0 */ -#define GPIO_DIR_DIR1 ((uint16_t)0x0002) /*!< Port input data, bit 1 */ -#define GPIO_DIR_DIR2 ((uint16_t)0x0004) /*!< Port input data, bit 2 */ -#define GPIO_DIR_DIR3 ((uint16_t)0x0008) /*!< Port input data, bit 3 */ -#define GPIO_DIR_DIR4 ((uint16_t)0x0010) /*!< Port input data, bit 4 */ -#define GPIO_DIR_DIR5 ((uint16_t)0x0020) /*!< Port input data, bit 5 */ -#define GPIO_DIR_DIR6 ((uint16_t)0x0040) /*!< Port input data, bit 6 */ -#define GPIO_DIR_DIR7 ((uint16_t)0x0080) /*!< Port input data, bit 7 */ -#define GPIO_DIR_DIR8 ((uint16_t)0x0100) /*!< Port input data, bit 8 */ -#define GPIO_DIR_DIR9 ((uint16_t)0x0200) /*!< Port input data, bit 9 */ -#define GPIO_DIR_DIR10 ((uint16_t)0x0400) /*!< Port input data, bit 10 */ -#define GPIO_DIR_DIR11 ((uint16_t)0x0800) /*!< Port input data, bit 11 */ -#define GPIO_DIR_DIR12 ((uint16_t)0x1000) /*!< Port input data, bit 12 */ -#define GPIO_DIR_DIR13 ((uint16_t)0x2000) /*!< Port input data, bit 13 */ -#define GPIO_DIR_DIR14 ((uint16_t)0x4000) /*!< Port input data, bit 14 */ -#define GPIO_DIR_DIR15 ((uint16_t)0x8000) /*!< Port input data, bit 15 */ - -/******************* Bit definition for GPIO_DOR register *******************/ -#define GPIO_DOR_DOR0 ((uint16_t)0x0001) /*!< Port output data, bit 0 */ -#define GPIO_DOR_DOR1 ((uint16_t)0x0002) /*!< Port output data, bit 1 */ -#define GPIO_DOR_DOR2 ((uint16_t)0x0004) /*!< Port output data, bit 2 */ -#define GPIO_DOR_DOR3 ((uint16_t)0x0008) /*!< Port output data, bit 3 */ -#define GPIO_DOR_DOR4 ((uint16_t)0x0010) /*!< Port output data, bit 4 */ -#define GPIO_DOR_DOR5 ((uint16_t)0x0020) /*!< Port output data, bit 5 */ -#define GPIO_DOR_DOR6 ((uint16_t)0x0040) /*!< Port output data, bit 6 */ -#define GPIO_DOR_DOR7 ((uint16_t)0x0080) /*!< Port output data, bit 7 */ -#define GPIO_DOR_DOR8 ((uint16_t)0x0100) /*!< Port output data, bit 8 */ -#define GPIO_DOR_DOR9 ((uint16_t)0x0200) /*!< Port output data, bit 9 */ -#define GPIO_DOR_DOR10 ((uint16_t)0x0400) /*!< Port output data, bit 10 */ -#define GPIO_DOR_DOR11 ((uint16_t)0x0800) /*!< Port output data, bit 11 */ -#define GPIO_DOR_DOR12 ((uint16_t)0x1000) /*!< Port output data, bit 12 */ -#define GPIO_DOR_DOR13 ((uint16_t)0x2000) /*!< Port output data, bit 13 */ -#define GPIO_DOR_DOR14 ((uint16_t)0x4000) /*!< Port output data, bit 14 */ -#define GPIO_DOR_DOR15 ((uint16_t)0x8000) /*!< Port output data, bit 15 */ - -/****************** Bit definition for GPIO_BOR register *******************/ -#define GPIO_BOR_BOR0 ((uint32_t)0x00000001) /*!< Port x Set bit 0 */ -#define GPIO_BOR_BOR1 ((uint32_t)0x00000002) /*!< Port x Set bit 1 */ -#define GPIO_BOR_BOR2 ((uint32_t)0x00000004) /*!< Port x Set bit 2 */ -#define GPIO_BOR_BOR3 ((uint32_t)0x00000008) /*!< Port x Set bit 3 */ -#define GPIO_BOR_BOR4 ((uint32_t)0x00000010) /*!< Port x Set bit 4 */ -#define GPIO_BOR_BOR5 ((uint32_t)0x00000020) /*!< Port x Set bit 5 */ -#define GPIO_BOR_BOR6 ((uint32_t)0x00000040) /*!< Port x Set bit 6 */ -#define GPIO_BOR_BOR7 ((uint32_t)0x00000080) /*!< Port x Set bit 7 */ -#define GPIO_BOR_BOR8 ((uint32_t)0x00000100) /*!< Port x Set bit 8 */ -#define GPIO_BOR_BOR9 ((uint32_t)0x00000200) /*!< Port x Set bit 9 */ -#define GPIO_BOR_BOR10 ((uint32_t)0x00000400) /*!< Port x Set bit 10 */ -#define GPIO_BOR_BOR11 ((uint32_t)0x00000800) /*!< Port x Set bit 11 */ -#define GPIO_BOR_BOR12 ((uint32_t)0x00001000) /*!< Port x Set bit 12 */ -#define GPIO_BOR_BOR13 ((uint32_t)0x00002000) /*!< Port x Set bit 13 */ -#define GPIO_BOR_BOR14 ((uint32_t)0x00004000) /*!< Port x Set bit 14 */ -#define GPIO_BOR_BOR15 ((uint32_t)0x00008000) /*!< Port x Set bit 15 */ - -#define GPIO_BOR_COR0 ((uint32_t)0x00010000) /*!< Port x Reset bit 0 */ -#define GPIO_BOR_COR1 ((uint32_t)0x00020000) /*!< Port x Reset bit 1 */ -#define GPIO_BOR_COR2 ((uint32_t)0x00040000) /*!< Port x Reset bit 2 */ -#define GPIO_BOR_COR3 ((uint32_t)0x00080000) /*!< Port x Reset bit 3 */ -#define GPIO_BOR_COR4 ((uint32_t)0x00100000) /*!< Port x Reset bit 4 */ -#define GPIO_BOR_COR5 ((uint32_t)0x00200000) /*!< Port x Reset bit 5 */ -#define GPIO_BOR_COR6 ((uint32_t)0x00400000) /*!< Port x Reset bit 6 */ -#define GPIO_BOR_COR7 ((uint32_t)0x00800000) /*!< Port x Reset bit 7 */ -#define GPIO_BOR_COR8 ((uint32_t)0x01000000) /*!< Port x Reset bit 8 */ -#define GPIO_BOR_COR9 ((uint32_t)0x02000000) /*!< Port x Reset bit 9 */ -#define GPIO_BOR_COR10 ((uint32_t)0x04000000) /*!< Port x Reset bit 10 */ -#define GPIO_BOR_COR11 ((uint32_t)0x08000000) /*!< Port x Reset bit 11 */ -#define GPIO_BOR_COR12 ((uint32_t)0x10000000) /*!< Port x Reset bit 12 */ -#define GPIO_BOR_COR13 ((uint32_t)0x20000000) /*!< Port x Reset bit 13 */ -#define GPIO_BOR_COR14 ((uint32_t)0x40000000) /*!< Port x Reset bit 14 */ -#define GPIO_BOR_COR15 ((uint32_t)0x80000000) /*!< Port x Reset bit 15 */ - -/******************* Bit definition for GPIO_BCR register *******************/ -#define GPIO_BCR_BR0 ((uint16_t)0x0001) /*!< Port x Reset bit 0 */ -#define GPIO_BCR_BR1 ((uint16_t)0x0002) /*!< Port x Reset bit 1 */ -#define GPIO_BCR_BR2 ((uint16_t)0x0004) /*!< Port x Reset bit 2 */ -#define GPIO_BCR_BR3 ((uint16_t)0x0008) /*!< Port x Reset bit 3 */ -#define GPIO_BCR_BR4 ((uint16_t)0x0010) /*!< Port x Reset bit 4 */ -#define GPIO_BCR_BR5 ((uint16_t)0x0020) /*!< Port x Reset bit 5 */ -#define GPIO_BCR_BR6 ((uint16_t)0x0040) /*!< Port x Reset bit 6 */ -#define GPIO_BCR_BR7 ((uint16_t)0x0080) /*!< Port x Reset bit 7 */ -#define GPIO_BCR_BR8 ((uint16_t)0x0100) /*!< Port x Reset bit 8 */ -#define GPIO_BCR_BR9 ((uint16_t)0x0200) /*!< Port x Reset bit 9 */ -#define GPIO_BCR_BR10 ((uint16_t)0x0400) /*!< Port x Reset bit 10 */ -#define GPIO_BCR_BR11 ((uint16_t)0x0800) /*!< Port x Reset bit 11 */ -#define GPIO_BCR_BR12 ((uint16_t)0x1000) /*!< Port x Reset bit 12 */ -#define GPIO_BCR_BR13 ((uint16_t)0x2000) /*!< Port x Reset bit 13 */ -#define GPIO_BCR_BR14 ((uint16_t)0x4000) /*!< Port x Reset bit 14 */ -#define GPIO_BCR_BR15 ((uint16_t)0x8000) /*!< Port x Reset bit 15 */ - -/****************** Bit definition for GPIO_LOCKR register *******************/ -#define GPIO_LOCKR_LK0 ((uint32_t)0x00000001) /*!< Port x Lock bit 0 */ -#define GPIO_LOCKR_LK1 ((uint32_t)0x00000002) /*!< Port x Lock bit 1 */ -#define GPIO_LOCKR_LK2 ((uint32_t)0x00000004) /*!< Port x Lock bit 2 */ -#define GPIO_LOCKR_LK3 ((uint32_t)0x00000008) /*!< Port x Lock bit 3 */ -#define GPIO_LOCKR_LK4 ((uint32_t)0x00000010) /*!< Port x Lock bit 4 */ -#define GPIO_LOCKR_LK5 ((uint32_t)0x00000020) /*!< Port x Lock bit 5 */ -#define GPIO_LOCKR_LK6 ((uint32_t)0x00000040) /*!< Port x Lock bit 6 */ -#define GPIO_LOCKR_LK7 ((uint32_t)0x00000080) /*!< Port x Lock bit 7 */ -#define GPIO_LOCKR_LK8 ((uint32_t)0x00000100) /*!< Port x Lock bit 8 */ -#define GPIO_LOCKR_LK9 ((uint32_t)0x00000200) /*!< Port x Lock bit 9 */ -#define GPIO_LOCKR_LK10 ((uint32_t)0x00000400) /*!< Port x Lock bit 10 */ -#define GPIO_LOCKR_LK11 ((uint32_t)0x00000800) /*!< Port x Lock bit 11 */ -#define GPIO_LOCKR_LK12 ((uint32_t)0x00001000) /*!< Port x Lock bit 12 */ -#define GPIO_LOCKR_LK13 ((uint32_t)0x00002000) /*!< Port x Lock bit 13 */ -#define GPIO_LOCKR_LK14 ((uint32_t)0x00004000) /*!< Port x Lock bit 14 */ -#define GPIO_LOCKR_LK15 ((uint32_t)0x00008000) /*!< Port x Lock bit 15 */ -#define GPIO_LOCKR_LKK ((uint32_t)0x00010000) /*!< Lock key */ - -/*----------------------------------------------------------------------------*/ - -/****************** Bit definition for AFIO_ECR register *******************/ -#define AFIO_ECR_PIN ((uint8_t)0x0F) /*!< PIN[3:0] bits (Pin selection) */ -#define AFIO_ECR_PIN_0 ((uint8_t)0x01) /*!< Bit 0 */ -#define AFIO_ECR_PIN_1 ((uint8_t)0x02) /*!< Bit 1 */ -#define AFIO_ECR_PIN_2 ((uint8_t)0x04) /*!< Bit 2 */ -#define AFIO_ECR_PIN_3 ((uint8_t)0x08) /*!< Bit 3 */ - -/*!< PIN configuration */ -#define AFIO_ECR_PIN_PX0 ((uint8_t)0x00) /*!< Pin 0 selected */ -#define AFIO_ECR_PIN_PX1 ((uint8_t)0x01) /*!< Pin 1 selected */ -#define AFIO_ECR_PIN_PX2 ((uint8_t)0x02) /*!< Pin 2 selected */ -#define AFIO_ECR_PIN_PX3 ((uint8_t)0x03) /*!< Pin 3 selected */ -#define AFIO_ECR_PIN_PX4 ((uint8_t)0x04) /*!< Pin 4 selected */ -#define AFIO_ECR_PIN_PX5 ((uint8_t)0x05) /*!< Pin 5 selected */ -#define AFIO_ECR_PIN_PX6 ((uint8_t)0x06) /*!< Pin 6 selected */ -#define AFIO_ECR_PIN_PX7 ((uint8_t)0x07) /*!< Pin 7 selected */ -#define AFIO_ECR_PIN_PX8 ((uint8_t)0x08) /*!< Pin 8 selected */ -#define AFIO_ECR_PIN_PX9 ((uint8_t)0x09) /*!< Pin 9 selected */ -#define AFIO_ECR_PIN_PX10 ((uint8_t)0x0A) /*!< Pin 10 selected */ -#define AFIO_ECR_PIN_PX11 ((uint8_t)0x0B) /*!< Pin 11 selected */ -#define AFIO_ECR_PIN_PX12 ((uint8_t)0x0C) /*!< Pin 12 selected */ -#define AFIO_ECR_PIN_PX13 ((uint8_t)0x0D) /*!< Pin 13 selected */ -#define AFIO_ECR_PIN_PX14 ((uint8_t)0x0E) /*!< Pin 14 selected */ -#define AFIO_ECR_PIN_PX15 ((uint8_t)0x0F) /*!< Pin 15 selected */ - -#define AFIO_ECR_PORT ((uint8_t)0x70) /*!< PORT[2:0] bits (Port selection) */ -#define AFIO_ECR_PORT_0 ((uint8_t)0x10) /*!< Bit 0 */ -#define AFIO_ECR_PORT_1 ((uint8_t)0x20) /*!< Bit 1 */ -#define AFIO_ECR_PORT_2 ((uint8_t)0x40) /*!< Bit 2 */ - -/*!< PORT configuration */ -#define AFIO_ECR_PORT_PA ((uint8_t)0x00) /*!< Port A selected */ -#define AFIO_ECR_PORT_PB ((uint8_t)0x10) /*!< Port B selected */ -#define AFIO_ECR_PORT_PC ((uint8_t)0x20) /*!< Port C selected */ -#define AFIO_ECR_PORT_PD ((uint8_t)0x30) /*!< Port D selected */ -#define AFIO_ECR_PORT_PE ((uint8_t)0x40) /*!< Port E selected */ - -#define AFIO_ECR_EOE ((uint8_t)0x80) /*!< Event Output Enable */ - -/****************** Bit definition for AFIO_MAPR register *******************/ -#define AFIO_PCFR1_SPI1_REMAP ((uint32_t)0x00000001) /*!< SPI1 remapping */ -#define AFIO_PCFR1_I2C1_REMAP ((uint32_t)0x00000002) /*!< I2C1 remapping */ -#define AFIO_PCFR1_USART1_REMAP ((uint32_t)0x00000004) /*!< USART1 remapping */ -#define AFIO_PCFR1_USART2_REMAP ((uint32_t)0x00000008) /*!< USART2 remapping */ - -#define AFIO_PCFR1_USART3_REMAP ((uint32_t)0x00000030) /*!< USART3_REMAP[1:0] bits (USART3 remapping) */ -#define AFIO_PCFR1_USART3_REMAP_0 ((uint32_t)0x00000010) /*!< Bit 0 */ -#define AFIO_PCFR1_USART3_REMAP_1 ((uint32_t)0x00000020) /*!< Bit 1 */ - -/* USART3_REMAP configuration */ -#define AFIO_PCFR1_USART3_REMAP_NOREMAP ((uint32_t)0x00000000) /*!< No remap (TX/PB10, RX/PB11, CK/PB12, CTS/PB13, RTS/PB14) */ -#define AFIO_PCFR1_USART3_REMAP_PARTIALREMAP ((uint32_t)0x00000010) /*!< Partial remap (TX/PC10, RX/PC11, CK/PC12, CTS/PB13, RTS/PB14) */ -#define AFIO_PCFR1_USART3_REMAP_FULLREMAP ((uint32_t)0x00000030) /*!< Full remap (TX/PD8, RX/PD9, CK/PD10, CTS/PD11, RTS/PD12) */ - -#define AFIO_PCFR1_TIM1_REMAP ((uint32_t)0x000000C0) /*!< TIM1_REMAP[1:0] bits (TIM1 remapping) */ -#define AFIO_PCFR1_TIM1_REMAP_0 ((uint32_t)0x00000040) /*!< Bit 0 */ -#define AFIO_PCFR1_TIM1_REMAP_1 ((uint32_t)0x00000080) /*!< Bit 1 */ - -/*!< TIM1_REMAP configuration */ -#define AFIO_PCFR1_TIM1_REMAP_NOREMAP ((uint32_t)0x00000000) /*!< No remap (ETR/PA12, CH1/PA8, CH2/PA9, CH3/PA10, CH4/PA11, BKIN/PB12, CH1N/PB13, CH2N/PB14, CH3N/PB15) */ -#define AFIO_PCFR1_TIM1_REMAP_PARTIALREMAP ((uint32_t)0x00000040) /*!< Partial remap (ETR/PA12, CH1/PA8, CH2/PA9, CH3/PA10, CH4/PA11, BKIN/PA6, CH1N/PA7, CH2N/PB0, CH3N/PB1) */ -#define AFIO_PCFR1_TIM1_REMAP_FULLREMAP ((uint32_t)0x000000C0) /*!< Full remap (ETR/PE7, CH1/PE9, CH2/PE11, CH3/PE13, CH4/PE14, BKIN/PE15, CH1N/PE8, CH2N/PE10, CH3N/PE12) */ - -#define AFIO_PCFR1_TIM2_REMAP ((uint32_t)0x00000300) /*!< TIM2_REMAP[1:0] bits (TIM2 remapping) */ -#define AFIO_PCFR1_TIM2_REMAP_0 ((uint32_t)0x00000100) /*!< Bit 0 */ -#define AFIO_PCFR1_TIM2_REMAP_1 ((uint32_t)0x00000200) /*!< Bit 1 */ - -/*!< TIM2_REMAP configuration */ -#define AFIO_PCFR1_TIM2_REMAP_NOREMAP ((uint32_t)0x00000000) /*!< No remap (CH1/ETR/PA0, CH2/PA1, CH3/PA2, CH4/PA3) */ -#define AFIO_PCFR1_TIM2_REMAP_PARTIALREMAP1 ((uint32_t)0x00000100) /*!< Partial remap (CH1/ETR/PA15, CH2/PB3, CH3/PA2, CH4/PA3) */ -#define AFIO_PCFR1_TIM2_REMAP_PARTIALREMAP2 ((uint32_t)0x00000200) /*!< Partial remap (CH1/ETR/PA0, CH2/PA1, CH3/PB10, CH4/PB11) */ -#define AFIO_PCFR1_TIM2_REMAP_FULLREMAP ((uint32_t)0x00000300) /*!< Full remap (CH1/ETR/PA15, CH2/PB3, CH3/PB10, CH4/PB11) */ - -#define AFIO_PCFR1_TIM3_REMAP ((uint32_t)0x00000C00) /*!< TIM3_REMAP[1:0] bits (TIM3 remapping) */ -#define AFIO_PCFR1_TIM3_REMAP_0 ((uint32_t)0x00000400) /*!< Bit 0 */ -#define AFIO_PCFR1_TIM3_REMAP_1 ((uint32_t)0x00000800) /*!< Bit 1 */ - -/*!< TIM3_REMAP configuration */ -#define AFIO_PCFR1_TIM3_REMAP_NOREMAP ((uint32_t)0x00000000) /*!< No remap (CH1/PA6, CH2/PA7, CH3/PB0, CH4/PB1) */ -#define AFIO_PCFR1_TIM3_REMAP_PARTIALREMAP ((uint32_t)0x00000800) /*!< Partial remap (CH1/PB4, CH2/PB5, CH3/PB0, CH4/PB1) */ -#define AFIO_PCFR1_TIM3_REMAP_FULLREMAP ((uint32_t)0x00000C00) /*!< Full remap (CH1/PC6, CH2/PC7, CH3/PC8, CH4/PC9) */ - -#define AFIO_PCFR1_TIM4_REMAP ((uint32_t)0x00001000) /*!< TIM4_REMAP bit (TIM4 remapping) */ - -#define AFIO_PCFR1_CAN_REMAP ((uint32_t)0x00006000) /*!< CAN_REMAP[1:0] bits (CAN Alternate function remapping) */ -#define AFIO_PCFR1_CAN_REMAP_0 ((uint32_t)0x00002000) /*!< Bit 0 */ -#define AFIO_PCFR1_CAN_REMAP_1 ((uint32_t)0x00004000) /*!< Bit 1 */ - -/*!< CAN_REMAP configuration */ -#define AFIO_PCFR1_CAN_REMAP_REMAP1 ((uint32_t)0x00000000) /*!< CANRX mapped to PA11, CANTX mapped to PA12 */ -#define AFIO_PCFR1_CAN_REMAP_REMAP2 ((uint32_t)0x00004000) /*!< CANRX mapped to PB8, CANTX mapped to PB9 */ -#define AFIO_PCFR1_CAN_REMAP_REMAP3 ((uint32_t)0x00006000) /*!< CANRX mapped to PD0, CANTX mapped to PD1 */ - -#define AFIO_PCFR1_PD01_REMAP ((uint32_t)0x00008000) /*!< Port D0/Port D1 mapping on OSC_IN/OSC_OUT */ -#define AFIO_PCFR1_TIM5CH4_IREMAP ((uint32_t)0x00010000) /*!< TIM5 Channel4 Internal Remap */ -#define AFIO_PCFR1_ADC0_ETRGINJ_REMAP ((uint32_t)0x00020000) /*!< ADC 1 External Trigger Injected Conversion remapping */ -#define AFIO_PCFR1_ADC0_ETRGREG_REMAP ((uint32_t)0x00040000) /*!< ADC 1 External Trigger Regular Conversion remapping */ -#define AFIO_PCFR1_ADC1_ETRGINJ_REMAP ((uint32_t)0x00080000) /*!< ADC 2 External Trigger Injected Conversion remapping */ -#define AFIO_PCFR1_ADC1_ETRGREG_REMAP ((uint32_t)0x00100000) /*!< ADC 2 External Trigger Regular Conversion remapping */ - -/*!< SWJ_CFG configuration */ -#define AFIO_PCFR1_SWJ_CFG ((uint32_t)0x07000000) /*!< SWJ_CFG[2:0] bits (Serial Wire JTAG configuration) */ -#define AFIO_PCFR1_SWJ_CFG_0 ((uint32_t)0x01000000) /*!< Bit 0 */ -#define AFIO_PCFR1_SWJ_CFG_1 ((uint32_t)0x02000000) /*!< Bit 1 */ -#define AFIO_PCFR1_SWJ_CFG_2 ((uint32_t)0x04000000) /*!< Bit 2 */ - -#define AFIO_PCFR1_SWJ_CFG_RESET ((uint32_t)0x00000000) /*!< Full SWJ (JTAG-DP + SW-DP) : Reset State */ -#define AFIO_PCFR1_SWJ_CFG_NOJNTRST ((uint32_t)0x01000000) /*!< Full SWJ (JTAG-DP + SW-DP) but without JNTRST */ -#define AFIO_PCFR1_SWJ_CFG_JTAGDISABLE ((uint32_t)0x02000000) /*!< JTAG-DP Disabled and SW-DP Enabled */ -#define AFIO_PCFR1_SWJ_CFG_DISABLE ((uint32_t)0x04000000) /*!< JTAG-DP Disabled and SW-DP Disabled */ - -#ifdef GD32F10X_CL -/*!< ETH_REMAP configuration */ -#define AFIO_PCFR1_ETH_REMAP ((uint32_t)0x00200000) /*!< SPI3_REMAP bit (Ethernet MAC I/O remapping) */ - -/*!< CAN2_REMAP configuration */ -#define AFIO_PCFR1_CAN2_REMAP ((uint32_t)0x00400000) /*!< CAN2_REMAP bit (CAN2 I/O remapping) */ - -/*!< MII_RMII_SEL configuration */ -#define AFIO_PCFR1_MII_RMII_SEL ((uint32_t)0x00800000) /*!< MII_RMII_SEL bit (Ethernet MII or RMII selection) */ - -/*!< SPI3_REMAP configuration */ -#define AFIO_PCFR1_SPI3_REMAP ((uint32_t)0x10000000) /*!< SPI3_REMAP bit (SPI3 remapping) */ - -/*!< TIM2ITR1_IREMAP configuration */ -#define AFIO_PCFR1_TIM2ITR1_IREMAP ((uint32_t)0x20000000) /*!< TIM2ITR1_IREMAP bit (TIM2 internal trigger 1 remapping) */ - -/*!< PTP_PPS_REMAP configuration */ -#define AFIO_PCFR1_PTP_PPS_REMAP ((uint32_t)0x40000000) /*!< PTP_PPS_REMAP bit (Ethernet PTP PPS remapping) */ -#endif - -/***************** Bit definition for AFIO_EXTICR1 register *****************/ -#define AFIO_ESSR1_EXTI0 ((uint16_t)0x000F) /*!< EXTI 0 configuration */ -#define AFIO_ESSR1_EXTI1 ((uint16_t)0x00F0) /*!< EXTI 1 configuration */ -#define AFIO_ESSR1_EXTI2 ((uint16_t)0x0F00) /*!< EXTI 2 configuration */ -#define AFIO_ESSR1_EXTI3 ((uint16_t)0xF000) /*!< EXTI 3 configuration */ - -/*!< EXTI0 configuration */ -#define AFIO_ESSR1_EXTI0_PA ((uint16_t)0x0000) /*!< PA[0] pin */ -#define AFIO_ESSR1_EXTI0_PB ((uint16_t)0x0001) /*!< PB[0] pin */ -#define AFIO_ESSR1_EXTI0_PC ((uint16_t)0x0002) /*!< PC[0] pin */ -#define AFIO_ESSR1_EXTI0_PD ((uint16_t)0x0003) /*!< PD[0] pin */ -#define AFIO_ESSR1_EXTI0_PE ((uint16_t)0x0004) /*!< PE[0] pin */ -#define AFIO_ESSR1_EXTI0_PF ((uint16_t)0x0005) /*!< PF[0] pin */ -#define AFIO_ESSR1_EXTI0_PG ((uint16_t)0x0006) /*!< PG[0] pin */ - -/*!< EXTI1 configuration */ -#define AFIO_ESSR1_EXTI1_PA ((uint16_t)0x0000) /*!< PA[1] pin */ -#define AFIO_ESSR1_EXTI1_PB ((uint16_t)0x0010) /*!< PB[1] pin */ -#define AFIO_ESSR1_EXTI1_PC ((uint16_t)0x0020) /*!< PC[1] pin */ -#define AFIO_ESSR1_EXTI1_PD ((uint16_t)0x0030) /*!< PD[1] pin */ -#define AFIO_ESSR1_EXTI1_PE ((uint16_t)0x0040) /*!< PE[1] pin */ -#define AFIO_ESSR1_EXTI1_PF ((uint16_t)0x0050) /*!< PF[1] pin */ -#define AFIO_ESSR1_EXTI1_PG ((uint16_t)0x0060) /*!< PG[1] pin */ - -/*!< EXTI2 configuration */ -#define AFIO_ESSR1_EXTI2_PA ((uint16_t)0x0000) /*!< PA[2] pin */ -#define AFIO_ESSR1_EXTI2_PB ((uint16_t)0x0100) /*!< PB[2] pin */ -#define AFIO_ESSR1_EXTI2_PC ((uint16_t)0x0200) /*!< PC[2] pin */ -#define AFIO_ESSR1_EXTI2_PD ((uint16_t)0x0300) /*!< PD[2] pin */ -#define AFIO_ESSR1_EXTI2_PE ((uint16_t)0x0400) /*!< PE[2] pin */ -#define AFIO_ESSR1_EXTI2_PF ((uint16_t)0x0500) /*!< PF[2] pin */ -#define AFIO_ESSR1_EXTI2_PG ((uint16_t)0x0600) /*!< PG[2] pin */ - -/*!< EXTI3 configuration */ -#define AFIO_ESSR1_EXTI3_PA ((uint16_t)0x0000) /*!< PA[3] pin */ -#define AFIO_ESSR1_EXTI3_PB ((uint16_t)0x1000) /*!< PB[3] pin */ -#define AFIO_ESSR1_EXTI3_PC ((uint16_t)0x2000) /*!< PC[3] pin */ -#define AFIO_ESSR1_EXTI3_PD ((uint16_t)0x3000) /*!< PD[3] pin */ -#define AFIO_ESSR1_EXTI3_PE ((uint16_t)0x4000) /*!< PE[3] pin */ -#define AFIO_ESSR1_EXTI3_PF ((uint16_t)0x5000) /*!< PF[3] pin */ -#define AFIO_ESSR1_EXTI3_PG ((uint16_t)0x6000) /*!< PG[3] pin */ - -/***************** Bit definition for AFIO_EXTICR2 register *****************/ -#define AFIO_ESSR2_EXTI4 ((uint16_t)0x000F) /*!< EXTI 4 configuration */ -#define AFIO_ESSR2_EXTI5 ((uint16_t)0x00F0) /*!< EXTI 5 configuration */ -#define AFIO_ESSR2_EXTI6 ((uint16_t)0x0F00) /*!< EXTI 6 configuration */ -#define AFIO_ESSR2_EXTI7 ((uint16_t)0xF000) /*!< EXTI 7 configuration */ - -/*!< EXTI4 configuration */ -#define AFIO_ESSR2_EXTI4_PA ((uint16_t)0x0000) /*!< PA[4] pin */ -#define AFIO_ESSR2_EXTI4_PB ((uint16_t)0x0001) /*!< PB[4] pin */ -#define AFIO_ESSR2_EXTI4_PC ((uint16_t)0x0002) /*!< PC[4] pin */ -#define AFIO_ESSR2_EXTI4_PD ((uint16_t)0x0003) /*!< PD[4] pin */ -#define AFIO_ESSR2_EXTI4_PE ((uint16_t)0x0004) /*!< PE[4] pin */ -#define AFIO_ESSR2_EXTI4_PF ((uint16_t)0x0005) /*!< PF[4] pin */ -#define AFIO_ESSR2_EXTI4_PG ((uint16_t)0x0006) /*!< PG[4] pin */ - -/* EXTI5 configuration */ -#define AFIO_ESSR2_EXTI5_PA ((uint16_t)0x0000) /*!< PA[5] pin */ -#define AFIO_ESSR2_EXTI5_PB ((uint16_t)0x0010) /*!< PB[5] pin */ -#define AFIO_ESSR2_EXTI5_PC ((uint16_t)0x0020) /*!< PC[5] pin */ -#define AFIO_ESSR2_EXTI5_PD ((uint16_t)0x0030) /*!< PD[5] pin */ -#define AFIO_ESSR2_EXTI5_PE ((uint16_t)0x0040) /*!< PE[5] pin */ -#define AFIO_ESSR2_EXTI5_PF ((uint16_t)0x0050) /*!< PF[5] pin */ -#define AFIO_ESSR2_EXTI5_PG ((uint16_t)0x0060) /*!< PG[5] pin */ - -/*!< EXTI6 configuration */ -#define AFIO_ESSR2_EXTI6_PA ((uint16_t)0x0000) /*!< PA[6] pin */ -#define AFIO_ESSR2_EXTI6_PB ((uint16_t)0x0100) /*!< PB[6] pin */ -#define AFIO_ESSR2_EXTI6_PC ((uint16_t)0x0200) /*!< PC[6] pin */ -#define AFIO_ESSR2_EXTI6_PD ((uint16_t)0x0300) /*!< PD[6] pin */ -#define AFIO_ESSR2_EXTI6_PE ((uint16_t)0x0400) /*!< PE[6] pin */ -#define AFIO_ESSR2_EXTI6_PF ((uint16_t)0x0500) /*!< PF[6] pin */ -#define AFIO_ESSR2_EXTI6_PG ((uint16_t)0x0600) /*!< PG[6] pin */ - -/*!< EXTI7 configuration */ -#define AFIO_ESSR2_EXTI7_PA ((uint16_t)0x0000) /*!< PA[7] pin */ -#define AFIO_ESSR2_EXTI7_PB ((uint16_t)0x1000) /*!< PB[7] pin */ -#define AFIO_ESSR2_EXTI7_PC ((uint16_t)0x2000) /*!< PC[7] pin */ -#define AFIO_ESSR2_EXTI7_PD ((uint16_t)0x3000) /*!< PD[7] pin */ -#define AFIO_ESSR2_EXTI7_PE ((uint16_t)0x4000) /*!< PE[7] pin */ -#define AFIO_ESSR2_EXTI7_PF ((uint16_t)0x5000) /*!< PF[7] pin */ -#define AFIO_ESSR2_EXTI7_PG ((uint16_t)0x6000) /*!< PG[7] pin */ - -/***************** Bit definition for AFIO_EXTICR3 register *****************/ -#define AFIO_ESSR3_EXTI8 ((uint16_t)0x000F) /*!< EXTI 8 configuration */ -#define AFIO_ESSR3_EXTI9 ((uint16_t)0x00F0) /*!< EXTI 9 configuration */ -#define AFIO_ESSR3_EXTI10 ((uint16_t)0x0F00) /*!< EXTI 10 configuration */ -#define AFIO_ESSR3_EXTI11 ((uint16_t)0xF000) /*!< EXTI 11 configuration */ - -/*!< EXTI8 configuration */ -#define AFIO_ESSR3_EXTI8_PA ((uint16_t)0x0000) /*!< PA[8] pin */ -#define AFIO_ESSR3_EXTI8_PB ((uint16_t)0x0001) /*!< PB[8] pin */ -#define AFIO_ESSR3_EXTI8_PC ((uint16_t)0x0002) /*!< PC[8] pin */ -#define AFIO_ESSR3_EXTI8_PD ((uint16_t)0x0003) /*!< PD[8] pin */ -#define AFIO_ESSR3_EXTI8_PE ((uint16_t)0x0004) /*!< PE[8] pin */ -#define AFIO_ESSR3_EXTI8_PF ((uint16_t)0x0005) /*!< PF[8] pin */ -#define AFIO_ESSR3_EXTI8_PG ((uint16_t)0x0006) /*!< PG[8] pin */ - -/*!< EXTI9 configuration */ -#define AFIO_ESSR3_EXTI9_PA ((uint16_t)0x0000) /*!< PA[9] pin */ -#define AFIO_ESSR3_EXTI9_PB ((uint16_t)0x0010) /*!< PB[9] pin */ -#define AFIO_ESSR3_EXTI9_PC ((uint16_t)0x0020) /*!< PC[9] pin */ -#define AFIO_ESSR3_EXTI9_PD ((uint16_t)0x0030) /*!< PD[9] pin */ -#define AFIO_ESSR3_EXTI9_PE ((uint16_t)0x0040) /*!< PE[9] pin */ -#define AFIO_ESSR3_EXTI9_PF ((uint16_t)0x0050) /*!< PF[9] pin */ -#define AFIO_ESSR3_EXTI9_PG ((uint16_t)0x0060) /*!< PG[9] pin */ - -/*!< EXTI10 configuration */ -#define AFIO_ESSR3_EXTI10_PA ((uint16_t)0x0000) /*!< PA[10] pin */ -#define AFIO_ESSR3_EXTI10_PB ((uint16_t)0x0100) /*!< PB[10] pin */ -#define AFIO_ESSR3_EXTI10_PC ((uint16_t)0x0200) /*!< PC[10] pin */ -#define AFIO_ESSR3_EXTI10_PD ((uint16_t)0x0300) /*!< PD[10] pin */ -#define AFIO_ESSR3_EXTI10_PE ((uint16_t)0x0400) /*!< PE[10] pin */ -#define AFIO_ESSR3_EXTI10_PF ((uint16_t)0x0500) /*!< PF[10] pin */ -#define AFIO_ESSR3_EXTI10_PG ((uint16_t)0x0600) /*!< PG[10] pin */ - -/*!< EXTI11 configuration */ -#define AFIO_ESSR3_EXTI11_PA ((uint16_t)0x0000) /*!< PA[11] pin */ -#define AFIO_ESSR3_EXTI11_PB ((uint16_t)0x1000) /*!< PB[11] pin */ -#define AFIO_ESSR3_EXTI11_PC ((uint16_t)0x2000) /*!< PC[11] pin */ -#define AFIO_ESSR3_EXTI11_PD ((uint16_t)0x3000) /*!< PD[11] pin */ -#define AFIO_ESSR3_EXTI11_PE ((uint16_t)0x4000) /*!< PE[11] pin */ -#define AFIO_ESSR3_EXTI11_PF ((uint16_t)0x5000) /*!< PF[11] pin */ -#define AFIO_ESSR3_EXTI11_PG ((uint16_t)0x6000) /*!< PG[11] pin */ - -/***************** Bit definition for AFIO_EXTICR4 register *****************/ -#define AFIO_ESSR4_EXTI12 ((uint16_t)0x000F) /*!< EXTI 12 configuration */ -#define AFIO_ESSR4_EXTI13 ((uint16_t)0x00F0) /*!< EXTI 13 configuration */ -#define AFIO_ESSR4_EXTI14 ((uint16_t)0x0F00) /*!< EXTI 14 configuration */ -#define AFIO_ESSR4_EXTI15 ((uint16_t)0xF000) /*!< EXTI 15 configuration */ - -/* EXTI12 configuration */ -#define AFIO_ESSR4_EXTI12_PA ((uint16_t)0x0000) /*!< PA[12] pin */ -#define AFIO_ESSR4_EXTI12_PB ((uint16_t)0x0001) /*!< PB[12] pin */ -#define AFIO_ESSR4_EXTI12_PC ((uint16_t)0x0002) /*!< PC[12] pin */ -#define AFIO_ESSR4_EXTI12_PD ((uint16_t)0x0003) /*!< PD[12] pin */ -#define AFIO_ESSR4_EXTI12_PE ((uint16_t)0x0004) /*!< PE[12] pin */ -#define AFIO_ESSR4_EXTI12_PF ((uint16_t)0x0005) /*!< PF[12] pin */ -#define AFIO_ESSR4_EXTI12_PG ((uint16_t)0x0006) /*!< PG[12] pin */ - -/* EXTI13 configuration */ -#define AFIO_ESSR4_EXTI13_PA ((uint16_t)0x0000) /*!< PA[13] pin */ -#define AFIO_ESSR4_EXTI13_PB ((uint16_t)0x0010) /*!< PB[13] pin */ -#define AFIO_ESSR4_EXTI13_PC ((uint16_t)0x0020) /*!< PC[13] pin */ -#define AFIO_ESSR4_EXTI13_PD ((uint16_t)0x0030) /*!< PD[13] pin */ -#define AFIO_ESSR4_EXTI13_PE ((uint16_t)0x0040) /*!< PE[13] pin */ -#define AFIO_ESSR4_EXTI13_PF ((uint16_t)0x0050) /*!< PF[13] pin */ -#define AFIO_ESSR4_EXTI13_PG ((uint16_t)0x0060) /*!< PG[13] pin */ - -/*!< EXTI14 configuration */ -#define AFIO_ESSR4_EXTI14_PA ((uint16_t)0x0000) /*!< PA[14] pin */ -#define AFIO_ESSR4_EXTI14_PB ((uint16_t)0x0100) /*!< PB[14] pin */ -#define AFIO_ESSR4_EXTI14_PC ((uint16_t)0x0200) /*!< PC[14] pin */ -#define AFIO_ESSR4_EXTI14_PD ((uint16_t)0x0300) /*!< PD[14] pin */ -#define AFIO_ESSR4_EXTI14_PE ((uint16_t)0x0400) /*!< PE[14] pin */ -#define AFIO_ESSR4_EXTI14_PF ((uint16_t)0x0500) /*!< PF[14] pin */ -#define AFIO_ESSR4_EXTI14_PG ((uint16_t)0x0600) /*!< PG[14] pin */ - -/*!< EXTI15 configuration */ -#define AFIO_ESSR4_EXTI15_PA ((uint16_t)0x0000) /*!< PA[15] pin */ -#define AFIO_ESSR4_EXTI15_PB ((uint16_t)0x1000) /*!< PB[15] pin */ -#define AFIO_ESSR4_EXTI15_PC ((uint16_t)0x2000) /*!< PC[15] pin */ -#define AFIO_ESSR4_EXTI15_PD ((uint16_t)0x3000) /*!< PD[15] pin */ -#define AFIO_ESSR4_EXTI15_PE ((uint16_t)0x4000) /*!< PE[15] pin */ -#define AFIO_ESSR4_EXTI15_PF ((uint16_t)0x5000) /*!< PF[15] pin */ -#define AFIO_ESSR4_EXTI15_PG ((uint16_t)0x6000) /*!< PG[15] pin */ - - -#if defined (GD32F10X_MD) || defined (GD32F10X_HD) -/****************** Bit definition for AFIO_MAPR2 register ******************/ -#define AFIO_PCFR2_TIM15_REMAP ((uint32_t)0x00000001) /*!< TIM15 remapping */ -#define AFIO_PCFR2_TIM16_REMAP ((uint32_t)0x00000002) /*!< TIM16 remapping */ -#define AFIO_PCFR2_TIM17_REMAP ((uint32_t)0x00000004) /*!< TIM17 remapping */ -#define AFIO_PCFR2_CEC_REMAP ((uint32_t)0x00000008) /*!< CEC remapping */ -#define AFIO_PCFR2_TIM1_DMA_REMAP ((uint32_t)0x00000010) /*!< TIM1_DMA remapping */ -#endif - -#ifdef GD32F10X_HD -#define AFIO_PCFR2_TIM13_REMAP ((uint32_t)0x00000100) /*!< TIM13 remapping */ -#define AFIO_PCFR2_TIM14_REMAP ((uint32_t)0x00000200) /*!< TIM14 remapping */ -#define AFIO_PCFR2_EXMC_NADV_REMAP ((uint32_t)0x00000400) /*!< EXMC NADV remapping */ -#define AFIO_PCFR2_TIM67_DAC_DMA_REMAP ((uint32_t)0x00000800) /*!< TIM6/TIM7 and DAC DMA remapping */ -#define AFIO_PCFR2_TIM12_REMAP ((uint32_t)0x00001000) /*!< TIM12 remapping */ -#define AFIO_PCFR2_MISC_REMAP ((uint32_t)0x00002000) /*!< Miscellaneous remapping */ -#endif - -#ifdef GD32F10X_XD -/****************** Bit definition for AFIO_MAPR2 register ******************/ -#define AFIO_PCFR2_TIM9_REMAP ((uint32_t)0x00000020) /*!< TIM9 remapping */ -#define AFIO_PCFR2_TIM10_REMAP ((uint32_t)0x00000040) /*!< TIM10 remapping */ -#define AFIO_PCFR2_TIM11_REMAP ((uint32_t)0x00000080) /*!< TIM11 remapping */ -#define AFIO_PCFR2_TIM13_REMAP ((uint32_t)0x00000100) /*!< TIM13 remapping */ -#define AFIO_PCFR2_TIM14_REMAP ((uint32_t)0x00000200) /*!< TIM14 remapping */ -#define AFIO_PCFR2_EXMC_NADV_REMAP ((uint32_t)0x00000400) /*!< EXMC NADV remapping */ -#endif -/******************************************************************************/ -/* */ -/* Inter-integrated Circuit Interface */ -/* */ -/******************************************************************************/ - -/******************* Bit definition for I2C_CTLR1 register *******************/ -#define I2C_CTLR1_I2CEN ((uint16_t)0x0001) /*!< Peripheral Enable */ -#define I2C_CTLR1_SMBEN ((uint16_t)0x0002) /*!< SMBus Mode */ -#define I2C_CTLR1_SMBSEL ((uint16_t)0x0008) /*!< SMBus Type */ -#define I2C_CTLR1_ARPEN ((uint16_t)0x0010) /*!< ARP Enable */ -#define I2C_CTLR1_PECEN ((uint16_t)0x0020) /*!< PEC Enable */ -#define I2C_CTLR1_GCEN ((uint16_t)0x0040) /*!< General Call Enable */ -#define I2C_CTLR1_DISSTRC ((uint16_t)0x0080) /*!< Clock Stretching Disable (Slave mode) */ -#define I2C_CTLR1_GENSTA ((uint16_t)0x0100) /*!< Start Generation */ -#define I2C_CTLR1_GENSTP ((uint16_t)0x0200) /*!< Stop Generation */ -#define I2C_CTLR1_ACKEN ((uint16_t)0x0400) /*!< Acknowledge Enable */ -#define I2C_CTLR1_POAP ((uint16_t)0x0800) /*!< Acknowledge/PEC Position (for data reception) */ -#define I2C_CTLR1_PECTRANS ((uint16_t)0x1000) /*!< Packet Error Checking */ -#define I2C_CTLR1_SALT ((uint16_t)0x2000) /*!< SMBus Alert */ -#define I2C_CTLR1_SRESET ((uint16_t)0x8000) /*!< Software Reset */ - -/******************* Bit definition for I2C_CTLR2 register ********************/ -#define I2C_CTLR2_I2CCLK ((uint16_t)0x003F) /*!< I2CCLK[5:0] bits (Peripheral Clock Frequency) */ -#define I2C_CTLR2_I2CCLK_0 ((uint16_t)0x0001) /*!< Bit 0 */ -#define I2C_CTLR2_I2CCLK_1 ((uint16_t)0x0002) /*!< Bit 1 */ -#define I2C_CTLR2_I2CCLK_2 ((uint16_t)0x0004) /*!< Bit 2 */ -#define I2C_CTLR2_I2CCLK_3 ((uint16_t)0x0008) /*!< Bit 3 */ -#define I2C_CTLR2_I2CCLK_4 ((uint16_t)0x0010) /*!< Bit 4 */ -#define I2C_CTLR2_I2CCLK_5 ((uint16_t)0x0020) /*!< Bit 5 */ - -#define I2C_CTLR2_EIE ((uint16_t)0x0100) /*!< Error Interrupt Enable */ -#define I2C_CTLR2_EE ((uint16_t)0x0200) /*!< Event Interrupt Enable */ -#define I2C_CTLR2_BIE ((uint16_t)0x0400) /*!< Buffer Interrupt Enable */ -#define I2C_CTLR2_DMAON ((uint16_t)0x0800) /*!< DMA Requests Enable */ -#define I2C_CTLR2_DMALST ((uint16_t)0x1000) /*!< DMA Last Transfer */ - -/******************* Bit definition for I2C_AR1 register *******************/ -#define I2C_AR1_ADDRESS1_7 ((uint16_t)0x00FE) /*!< Interface Address */ -#define I2C_AR1_ADDRESS8_9 ((uint16_t)0x0300) /*!< Interface Address */ - -#define I2C_AR1_ADDRESS0 ((uint16_t)0x0001) /*!< Bit 0 */ -#define I2C_AR1_ADDRESS1 ((uint16_t)0x0002) /*!< Bit 1 */ -#define I2C_AR1_ADDRESS2 ((uint16_t)0x0004) /*!< Bit 2 */ -#define I2C_AR1_ADDRESS3 ((uint16_t)0x0008) /*!< Bit 3 */ -#define I2C_AR1_ADDRESS4 ((uint16_t)0x0010) /*!< Bit 4 */ -#define I2C_AR1_ADDRESS5 ((uint16_t)0x0020) /*!< Bit 5 */ -#define I2C_AR1_ADDRESS6 ((uint16_t)0x0040) /*!< Bit 6 */ -#define I2C_AR1_ADDRESS7 ((uint16_t)0x0080) /*!< Bit 7 */ -#define I2C_AR1_ADDRESS8 ((uint16_t)0x0100) /*!< Bit 8 */ -#define I2C_AR1_ADDRESS9 ((uint16_t)0x0200) /*!< Bit 9 */ - -#define I2C_AR1_ADDFORMAT ((uint16_t)0x8000) /*!< Addressing Mode (Slave mode) */ - -/******************* Bit definition for I2C_AR2 register *******************/ -#define I2C_AR2_DUADEN ((uint8_t)0x01) /*!< Dual addressing mode enable */ -#define I2C_AR2_ADDRESS2 ((uint8_t)0xFE) /*!< Interface address */ - -/******************** Bit definition for I2C_DTR register ********************/ -#define I2C_DTR_TRB ((uint8_t)0xFF) /*!< 8-bit Data Register */ - -/******************* Bit definition for I2C_STR1 register ********************/ -#define I2C_STR1_SBSEND ((uint16_t)0x0001) /*!< Start Bit (Master mode) */ -#define I2C_STR1_ADDSEND ((uint16_t)0x0002) /*!< Address sent (master mode)/matched (slave mode) */ -#define I2C_STR1_BTC ((uint16_t)0x0004) /*!< Byte Transfer Finished */ -#define I2C_STR1_ADD10SEND ((uint16_t)0x0008) /*!< 10-bit header sent (Master mode) */ -#define I2C_STR1_STPDET ((uint16_t)0x0010) /*!< Stop detection (Slave mode) */ -#define I2C_STR1_RBNE ((uint16_t)0x0040) /*!< Data Register not Empty (receivers) */ -#define I2C_STR1_TBE ((uint16_t)0x0080) /*!< Data Register Empty (transmitters) */ -#define I2C_STR1_BE ((uint16_t)0x0100) /*!< Bus Error */ -#define I2C_STR1_LOSTARB ((uint16_t)0x0200) /*!< Arbitration Lost (master mode) */ -#define I2C_STR1_AE ((uint16_t)0x0400) /*!< Acknowledge Failure */ -#define I2C_STR1_RXORE ((uint16_t)0x0800) /*!< Overrun/Underrun */ -#define I2C_STR1_PECE ((uint16_t)0x1000) /*!< PEC Error in reception */ -#define I2C_STR1_SMBTO ((uint16_t)0x4000) /*!< Timeout or Tlow Error */ -#define I2C_STR1_SMBALTS ((uint16_t)0x8000) /*!< SMBus Alert */ - -/******************* Bit definition for I2C_STR2 register ********************/ -#define I2C_STR2_MASTER ((uint16_t)0x0001) /*!< Master/Slave */ -#define I2C_STR2_I2CBSY ((uint16_t)0x0002) /*!< Bus Busy */ -#define I2C_STR2_TRS ((uint16_t)0x0004) /*!< Transmitter/Receiver */ -#define I2C_STR2_RXGC ((uint16_t)0x0010) /*!< General Call Address (Slave mode) */ -#define I2C_STR2_DEFSMB ((uint16_t)0x0020) /*!< SMBus Device Default Address (Slave mode) */ -#define I2C_STR2_HSTSMB ((uint16_t)0x0040) /*!< SMBus Host Header (Slave mode) */ -#define I2C_STR2_DUMODF ((uint16_t)0x0080) /*!< Dual Flag (Slave mode) */ -#define I2C_STR2_ECV ((uint16_t)0xFF00) /*!< Packet Error Checking Register */ - -/******************* Bit definition for I2C_CLKR register ********************/ -#define I2C_CLKR_CLKC ((uint16_t)0x0FFF) /*!< Clock Control Register in Fast/Standard mode (Master mode) */ -#define I2C_CLKR_DTCY ((uint16_t)0x4000) /*!< Fast Mode Duty Cycle */ -#define I2C_CLKR_FAST ((uint16_t)0x8000) /*!< I2C speed selection in master mode */ - -/****************** Bit definition for I2C_RTR register *******************/ -#define I2C_RTR_RISETIME ((uint8_t)0x3F) /*!< Maximum Rise Time in Fast/Standard mode (Master mode) */ - -/******************************************************************************/ -/* */ -/* Independent WATCHDOG (IWDG) */ -/* */ -/******************************************************************************/ - -/******************* Bit definition for IWDG_CTLR register ******************/ -#define IWDG_CTLR_CT ((uint16_t)0xFFFF) /*!< Key value (write only, read 0000h) */ - -/******************* Bit definition for IWDG_PSR register ********************/ -#define IWDG_PSR_PS ((uint8_t)0x07) /*!< PS[2:0] (Prescaler divider) */ -#define IWDG_PSR_PS_0 ((uint8_t)0x01) /*!< Bit 0 */ -#define IWDG_PSR_PS_1 ((uint8_t)0x02) /*!< Bit 1 */ -#define IWDG_PSR_PS_2 ((uint8_t)0x04) /*!< Bit 2 */ - -/******************* Bit definition for IWDG_RLDR register *******************/ -#define IWDG_RLDR_RLD ((uint16_t)0x0FFF) /*!< Watchdog counter reload value */ - -/******************* Bit definition for IWDG_STR register ********************/ -#define IWDG_STR_PUD ((uint8_t)0x01) /*!< Watchdog prescaler value update */ -#define IWDG_STR_RUD ((uint8_t)0x02) /*!< Watchdog counter reload value update */ -#define IWDG_STR_WUD ((uint8_t)0x04) /*!< Watchdog counter window value update */ - - -/******************************************************************************/ -/* */ -/* Power Control */ -/* */ -/******************************************************************************/ - -/******************** Bit definition for PWR_CTLR register ********************/ -#define PWR_CTLR_LDOLP ((uint16_t)0x0001) /*!< LDO Low Power Mode */ -#define PWR_CTLR_SDBM ((uint16_t)0x0002) /*!< Standby Mode */ -#define PWR_CTLR_WUFR ((uint16_t)0x0004) /*!< Wakeup Flag Reset */ -#define PWR_CTLR_SBFR ((uint16_t)0x0008) /*!< Standby Flag Reset */ -#define PWR_CTLR_LVDE ((uint16_t)0x0010) /*!< Low Voltage Detector Enable */ - -#define PWR_CTLR_LVDT ((uint16_t)0x00E0) /*!< LVDT[2:0] bits (Low Voltage Detector Threshold) */ -#define PWR_CTLR_LVDT_0 ((uint16_t)0x0020) /*!< Bit 0 */ -#define PWR_CTLR_LVDT_1 ((uint16_t)0x0040) /*!< Bit 1 */ -#define PWR_CTLR_LVDT_2 ((uint16_t)0x0080) /*!< Bit 2 */ - -/*!< LVDT configuration */ -#define PWR_CTLR_LVDT_2V2 ((uint16_t)0x0000) /*!< LVDT is 2.2V */ -#define PWR_CTLR_LVDT_2V3 ((uint16_t)0x0020) /*!< LVDT is 2.3V */ -#define PWR_CTLR_LVDT_2V4 ((uint16_t)0x0040) /*!< LVDT is 2.4V */ -#define PWR_CTLR_LVDT_2V5 ((uint16_t)0x0060) /*!< LVDT is 2.5V */ -#define PWR_CTLR_LVDT_2V6 ((uint16_t)0x0080) /*!< LVDT is 2.6V */ -#define PWR_CTLR_LVDT_2V7 ((uint16_t)0x00A0) /*!< LVDT is 2.7V */ -#define PWR_CTLR_LVDT_2V8 ((uint16_t)0x00C0) /*!< LVDT is 2.8V */ -#define PWR_CTLR_LVDT_2V9 ((uint16_t)0x00E0) /*!< LVDT is 2.9V */ - -#define PWR_CTLR_BKPWE ((uint16_t)0x0100) /*!< Backup Domain Write Enable */ - -/******************* Bit definition for PWR_STR register ********************/ -#define PWR_STR_WUF ((uint16_t)0x0001) /*!< Wakeup Flag */ -#define PWR_STR_SBF ((uint16_t)0x0002) /*!< Standby Flag */ -#define PWR_STR_LVDF ((uint16_t)0x0004) /*!< Low Voltage Detector Status Flag */ -#define PWR_STR_WUPE ((uint16_t)0x0100) /*!< WKUP Pin Enable */ - -/******************************************************************************/ -/* */ -/* Reset and Clock Control */ -/* */ -/******************************************************************************/ - -/******************** Bit definition for RCC_GCCR register ********************/ -#define RCC_GCCR_HSIEN ((uint32_t)0x00000001) /*!< Internal High Speed clock enable */ -#define RCC_GCCR_HSISTB ((uint32_t)0x00000002) /*!< Internal High Speed clock ready flag */ -#define RCC_GCCR_HSIADJ ((uint32_t)0x000000F8) /*!< Internal High Speed clock trimming */ -#define RCC_GCCR_HSICALIB ((uint32_t)0x0000FF00) /*!< Internal High Speed clock Calibration */ -#define RCC_GCCR_HSEEN ((uint32_t)0x00010000) /*!< External High Speed clock enable */ -#define RCC_GCCR_HSESTB ((uint32_t)0x00020000) /*!< External High Speed clock ready flag */ -#define RCC_GCCR_HSEBPS ((uint32_t)0x00040000) /*!< External High Speed clock Bypass */ -#define RCC_GCCR_CKMEN ((uint32_t)0x00080000) /*!< Clock Security System enable */ -#define RCC_GCCR_PLLEN ((uint32_t)0x01000000) /*!< PLL enable */ -#define RCC_GCCR_PLLSTB ((uint32_t)0x02000000) /*!< PLL clock ready flag */ - -#ifdef GD32F10X_CL -#define RCC_GCCR_PLL2EN ((uint32_t)0x04000000) /*!< PLL2 enable */ -#define RCC_GCCR_PLL2STB ((uint32_t)0x08000000) /*!< PLL2 clock ready flag */ -#define RCC_GCCR_PLL3EN ((uint32_t)0x10000000) /*!< PLL3 enable */ -#define RCC_GCCR_PLL3STB ((uint32_t)0x20000000) /*!< PLL3 clock ready flag */ -#endif /* GD32F10X_CL */ - -/******************* Bit definition for RCC_GCFGR register *******************/ -/*!< SW configuration */ -#define RCC_GCFGR_SCS ((uint32_t)0x00000003) /*!< SCS[1:0] bits (System clock Switch) */ -#define RCC_GCFGR_SCS_0 ((uint32_t)0x00000001) /*!< Bit 0 */ -#define RCC_GCFGR_SCS_1 ((uint32_t)0x00000002) /*!< Bit 1 */ - -#define RCC_GCFGR_SCS_HSI ((uint32_t)0x00000000) /*!< HSI selected as system clock */ -#define RCC_GCFGR_SCS_HSE ((uint32_t)0x00000001) /*!< HSE selected as system clock */ -#define RCC_GCFGR_SCS_PLL ((uint32_t)0x00000002) /*!< PLL selected as system clock */ - -/*!< SWS configuration */ -#define RCC_GCFGR_SCSS ((uint32_t)0x0000000C) /*!< SCSS[1:0] bits (System Clock Switch Status) */ -#define RCC_GCFGR_SCSS_0 ((uint32_t)0x00000004) /*!< Bit 0 */ -#define RCC_GCFGR_SCSS_1 ((uint32_t)0x00000008) /*!< Bit 1 */ - -#define RCC_GCFGR_SCSS_HSI ((uint32_t)0x00000000) /*!< HSI oscillator used as system clock */ -#define RCC_GCFGR_SCSS_HSE ((uint32_t)0x00000004) /*!< HSE oscillator used as system clock */ -#define RCC_GCFGR_SCSS_PLL ((uint32_t)0x00000008) /*!< PLL used as system clock */ - -/*!< AHBPS configuration */ -#define RCC_GCFGR_AHBPS ((uint32_t)0x000000F0) /*!< AHBPS[3:0] bits (AHB prescaler) */ -#define RCC_GCFGR_AHBPS_0 ((uint32_t)0x00000010) /*!< Bit 0 */ -#define RCC_GCFGR_AHBPS_1 ((uint32_t)0x00000020) /*!< Bit 1 */ -#define RCC_GCFGR_AHBPS_2 ((uint32_t)0x00000040) /*!< Bit 2 */ -#define RCC_GCFGR_AHBPS_3 ((uint32_t)0x00000080) /*!< Bit 3 */ - -#define RCC_GCFGR_AHBPS_DIV1 ((uint32_t)0x00000000) /*!< SYSCLK not divided */ -#define RCC_GCFGR_AHBPS_DIV2 ((uint32_t)0x00000080) /*!< SYSCLK divided by 2 */ -#define RCC_GCFGR_AHBPS_DIV4 ((uint32_t)0x00000090) /*!< SYSCLK divided by 4 */ -#define RCC_GCFGR_AHBPS_DIV8 ((uint32_t)0x000000A0) /*!< SYSCLK divided by 8 */ -#define RCC_GCFGR_AHBPS_DIV16 ((uint32_t)0x000000B0) /*!< SYSCLK divided by 16 */ -#define RCC_GCFGR_AHBPS_DIV64 ((uint32_t)0x000000C0) /*!< SYSCLK divided by 64 */ -#define RCC_GCFGR_AHBPS_DIV128 ((uint32_t)0x000000D0) /*!< SYSCLK divided by 128 */ -#define RCC_GCFGR_AHBPS_DIV256 ((uint32_t)0x000000E0) /*!< SYSCLK divided by 256 */ -#define RCC_GCFGR_AHBPS_DIV512 ((uint32_t)0x000000F0) /*!< SYSCLK divided by 512 */ - -/*!< APB1PS configuration */ -#define RCC_GCFGR_APB1PS ((uint32_t)0x00000700) /*!< APB1PS[2:0] bits (APB1 prescaler) */ -#define RCC_GCFGR_APB1PS_0 ((uint32_t)0x00000100) /*!< Bit 0 */ -#define RCC_GCFGR_APB1PS_1 ((uint32_t)0x00000200) /*!< Bit 1 */ -#define RCC_GCFGR_APB1PS_2 ((uint32_t)0x00000400) /*!< Bit 2 */ - -#define RCC_GCFGR_APB1PS_DIV1 ((uint32_t)0x00000000) /*!< AHB not divided */ -#define RCC_GCFGR_APB1PS_DIV2 ((uint32_t)0x00000400) /*!< AHB divided by 2 */ -#define RCC_GCFGR_APB1PS_DIV4 ((uint32_t)0x00000500) /*!< AHB divided by 4 */ -#define RCC_GCFGR_APB1PS_DIV8 ((uint32_t)0x00000600) /*!< AHB divided by 8 */ -#define RCC_GCFGR_APB1PS_DIV16 ((uint32_t)0x00000700) /*!< AHB divided by 16 */ - -/*!< APB2PS configuration */ -#define RCC_GCFGR_APB2PS ((uint32_t)0x00003800) /*!< APB2PS[2:0] bits (APB2 prescaler) */ -#define RCC_GCFGR_APB2PS_0 ((uint32_t)0x00000800) /*!< Bit 0 */ -#define RCC_GCFGR_APB2PS_1 ((uint32_t)0x00001000) /*!< Bit 1 */ -#define RCC_GCFGR_APB2PS_2 ((uint32_t)0x00002000) /*!< Bit 2 */ - -#define RCC_GCFGR_APB2PS_DIV1 ((uint32_t)0x00000000) /*!< AHB not divided */ -#define RCC_GCFGR_APB2PS_DIV2 ((uint32_t)0x00002000) /*!< AHB divided by 2 */ -#define RCC_GCFGR_APB2PS_DIV4 ((uint32_t)0x00002800) /*!< AHB divided by 4 */ -#define RCC_GCFGR_APB2PS_DIV8 ((uint32_t)0x00003000) /*!< AHB divided by 8 */ -#define RCC_GCFGR_APB2PS_DIV16 ((uint32_t)0x00003800) /*!< AHB divided by 16 */ - -/*!< ADCPS configuration */ -#define RCC_GCFGR_ADCPS ((uint32_t)0x1000C000) /*!< ADCPS[2:0] bits (ADC prescaler) */ -#define RCC_GCFGR_ADCPS_0 ((uint32_t)0x00004000) /*!< Bit 0 */ -#define RCC_GCFGR_ADCPS_1 ((uint32_t)0x00008000) /*!< Bit 1 */ -#define RCC_GCFGR_ADCPS_2 ((uint32_t)0x10000000) /*!< Bit 2 */ - -#define RCC_GCFGR_ADCPS_DIV2 ((uint32_t)0x00000000) /*!< APB2 divided by 2 */ -#define RCC_GCFGR_ADCPS_DIV4 ((uint32_t)0x00004000) /*!< APB2 divided by 4 */ -#define RCC_GCFGR_ADCPS_DIV6 ((uint32_t)0x00008000) /*!< APB2 divided by 6 */ -#define RCC_GCFGR_ADCPS_DIV8 ((uint32_t)0x0000C000) /*!< APB2 divided by 8 */ -#define RCC_GCFGR_ADCPS_DIV12 ((uint32_t)0x10004000) /*!< APB2 divided by 12 */ -#define RCC_GCFGR_ADCPS_DIV16 ((uint32_t)0x1000C000) /*!< APB2 divided by 16 */ - -#ifdef GD32F10X_CL -/*!< PLLSEL configuration */ -#define RCC_GCFGR_PLLSEL ((uint32_t)0x00010000) /*!< PLLSEL bit for entry clock source */ -#define RCC_GCFGR_PLLSEL_HSI_DIV2 ((uint32_t)0x00000000) /*!< HSI clock divided by 2 selected as PLL entry clock source */ -#define RCC_GCFGR_PLLSEL_PREDIV1 ((uint32_t)0x00010000) /*!< PREDIV1 clock selected as PLL entry clock source */ - -/*!< PLLPREDV configuration */ -#define RCC_GCFGR_PLLPREDV ((uint32_t)0x00020000) /*!< PLLPREDV bit for PLL entry */ -#define RCC_GCFGR_PLLPREDV_PREDIV1 ((uint32_t)0x00000000) /*!< PREDIV1 clock not divided for PLL entry */ -#define RCC_GCFGR_PLLPREDV_PREDIV1_DIV2 ((uint32_t)0x00020000) /*!< PREDIV1 clock divided by 2 for PLL entry */ - -/*!< PLLMF configuration */ -#define RCC_GCFGR_PLLMF ((uint32_t)0x203C0000) /*!< PLLMF[4:0] bits (PLL multiplication factor) */ -#define RCC_GCFGR_PLLMF_0 ((uint32_t)0x00040000) /*!< Bit 0 */ -#define RCC_GCFGR_PLLMF_1 ((uint32_t)0x00080000) /*!< Bit 1 */ -#define RCC_GCFGR_PLLMF_2 ((uint32_t)0x00100000) /*!< Bit 2 */ -#define RCC_GCFGR_PLLMF_3 ((uint32_t)0x00200000) /*!< Bit 3 */ -#define RCC_GCFGR_PLLMF_4 ((uint32_t)0x20000000) /*!< Bit 4 */ - -#define RCC_GCFGR_PLLMF2 ((uint32_t)0x00000000) /*!< PLL input clock*2 */ -#define RCC_GCFGR_PLLMF3 ((uint32_t)0x00040000) /*!< PLL input clock*3 */ -#define RCC_GCFGR_PLLMF4 ((uint32_t)0x00080000) /*!< PLL input clock*4 */ -#define RCC_GCFGR_PLLMF5 ((uint32_t)0x000C0000) /*!< PLL input clock*5 */ -#define RCC_GCFGR_PLLMF6 ((uint32_t)0x00100000) /*!< PLL input clock*6 */ -#define RCC_GCFGR_PLLMF7 ((uint32_t)0x00140000) /*!< PLL input clock*7 */ -#define RCC_GCFGR_PLLMF8 ((uint32_t)0x00180000) /*!< PLL input clock*8 */ -#define RCC_GCFGR_PLLMF9 ((uint32_t)0x001C0000) /*!< PLL input clock*9 */ -#define RCC_GCFGR_PLLMF10 ((uint32_t)0x00200000) /*!< PLL input clock10 */ -#define RCC_GCFGR_PLLMF11 ((uint32_t)0x00240000) /*!< PLL input clock*11 */ -#define RCC_GCFGR_PLLMF12 ((uint32_t)0x00280000) /*!< PLL input clock*12 */ -#define RCC_GCFGR_PLLMF13 ((uint32_t)0x002C0000) /*!< PLL input clock*13 */ -#define RCC_GCFGR_PLLMF14 ((uint32_t)0x00300000) /*!< PLL input clock*14 */ -#define RCC_GCFGR_PLLMF6_5 ((uint32_t)0x00340000) /*!< PLL input clock*6.5 */ -#define RCC_GCFGR_PLLMF16 ((uint32_t)0x00380000) /*!< PLL input clock*16 */ -#define RCC_GCFGR_PLLMF17 ((uint32_t)0x20000000) /*!< PLL input clock*17 */ -#define RCC_GCFGR_PLLMF18 ((uint32_t)0x20040000) /*!< PLL input clock*18 */ -#define RCC_GCFGR_PLLMF19 ((uint32_t)0x20080000) /*!< PLL input clock*19 */ -#define RCC_GCFGR_PLLMF20 ((uint32_t)0x200C0000) /*!< PLL input clock*20 */ -#define RCC_GCFGR_PLLMF21 ((uint32_t)0x20100000) /*!< PLL input clock*21 */ -#define RCC_GCFGR_PLLMF22 ((uint32_t)0x20140000) /*!< PLL input clock*22 */ -#define RCC_GCFGR_PLLMF23 ((uint32_t)0x20180000) /*!< PLL input clock*23 */ -#define RCC_GCFGR_PLLMF24 ((uint32_t)0x201C0000) /*!< PLL input clock*24 */ -#define RCC_GCFGR_PLLMF25 ((uint32_t)0x20200000) /*!< PLL input clock*25 */ -#define RCC_GCFGR_PLLMF26 ((uint32_t)0x20240000) /*!< PLL input clock*26 */ -#define RCC_GCFGR_PLLMF27 ((uint32_t)0x20280000) /*!< PLL input clock*27 */ -#define RCC_GCFGR_PLLMF28 ((uint32_t)0x202C0000) /*!< PLL input clock*28 */ -#define RCC_GCFGR_PLLMF29 ((uint32_t)0x20300000) /*!< PLL input clock*29 */ -#define RCC_GCFGR_PLLMF30 ((uint32_t)0x20340000) /*!< PLL input clock*30 */ -#define RCC_GCFGR_PLLMF31 ((uint32_t)0x20380000) /*!< PLL input clock*31 */ -#define RCC_GCFGR_PLLMF32 ((uint32_t)0x203C0000) /*!< PLL input clock*32 */ - -#define RCC_GCFGR_OTGFSPS ((uint32_t)0x00C00000) /*!< OTGFSPS[1:0] bits USB OTGDevice prescaler */ -#define RCC_GCFGR_OTGFSPS_0 ((uint32_t)0x00400000) /*!< Bit 0 */ -#define RCC_GCFGR_OTGFSPS_1 ((uint32_t)0x00800000) /*!< Bit 1 */ - -#define RCC_GCFGR_OTGFSPS_Div1_5 ((uint32_t)0x00000000) /*!< PLL divided by 1.5 */ -#define RCC_GCFGR_OTGFSPS_Div1 ((uint32_t)0x00400000) /*!< PLL not divided */ -#define RCC_GCFGR_OTGFSPS_Div2_5 ((uint32_t)0x00800000) /*!< PLL divided by 2.5 */ -#define RCC_GCFGR_OTGFSPS_Div2 ((uint32_t)0x00C00000) /*!< PLL divided by 2 */ - -/*!< CKOUTSEL configuration */ -#define RCC_GCFGR_CKOUTSEL ((uint32_t)0x0F000000) /*!< CKOUTSEL[3:0] bits (Microcontroller Clock Output) */ -#define RCC_GCFGR_CKOUTSEL_0 ((uint32_t)0x01000000) /*!< Bit 0 */ -#define RCC_GCFGR_CKOUTSEL_1 ((uint32_t)0x02000000) /*!< Bit 1 */ -#define RCC_GCFGR_CKOUTSEL_2 ((uint32_t)0x04000000) /*!< Bit 2 */ -#define RCC_GCFGR_CKOUTSEL_3 ((uint32_t)0x08000000) /*!< Bit 3 */ - -#define RCC_GCFGR_CKOUTSEL_NOCLOCK ((uint32_t)0x00000000) /*!< No clock */ -#define RCC_GCFGR_CKOUTSEL_SYSCLK ((uint32_t)0x04000000) /*!< System clock selected as CKOUTSEL source */ -#define RCC_GCFGR_CKOUTSEL_HSI ((uint32_t)0x05000000) /*!< HSI clock selected as CKOUTSEL source */ -#define RCC_GCFGR_CKOUTSEL_HSE ((uint32_t)0x06000000) /*!< HSE clock selected as CKOUTSEL source */ -#define RCC_GCFGR_CKOUTSEL_PLL_DIV2 ((uint32_t)0x07000000) /*!< PLL clock divided by 2 selected as CKOUTSEL source */ -#define RCC_GCFGR_CKOUTSEL_PLL2 ((uint32_t)0x08000000) /*!< PLL2 clock selected as CKOUTSEL source */ -#define RCC_GCFGR_CKOUTSEL_PLL3_DIV2 ((uint32_t)0x09000000) /*!< PLL3 clock divided by 2 selected as CKOUTSEL source */ -#define RCC_GCFGR_CKOUTSEL_EXT1 ((uint32_t)0x0A000000) /*!< EXT1 external 3-25 MHz oscillator clock selected as CKOUTSEL source */ -#define RCC_GCFGR_CKOUTSEL_PLL3 ((uint32_t)0x0B000000) /*!< PLL3 clock selected as CKOUTSEL source */ - -#else -#define RCC_GCFGR_PLLSEL ((uint32_t)0x00010000) /*!< PLLSEL bit for entry clock source */ -#define RCC_GCFGR_PLLSEL_HSI_DIV2 ((uint32_t)0x00000000) /*!< HSI clock divided by 2 selected as PLL entry clock source */ -#define RCC_GCFGR_PLLSEL_HSE ((uint32_t)0x00010000) /*!< HSE clock selected as PLL entry clock source */ - -/*!< PLLPREDV configuration */ -#define RCC_GCFGR_PLLPREDV ((uint32_t)0x00020000) /*!< PLLPREDV bit for PLL entry */ -#define RCC_GCFGR_PLLPREDV_HSE ((uint32_t)0x00000000) /*!< HSE clock not divided for PLL entry */ -#define RCC_GCFGR_PLLPREDV_HSE_DIV2 ((uint32_t)0x00020000) /*!< HSE clock divided by 2 for PLL entry */ - -/*!< PLLMF configuration */ -#define RCC_GCFGR_PLLMF ((uint32_t)0x083C0000) /*!< PLLMF[4:0] bits (PLL multiplication factor) */ -#define RCC_GCFGR_PLLMF_0 ((uint32_t)0x00040000) /*!< Bit 0 */ -#define RCC_GCFGR_PLLMF_1 ((uint32_t)0x00080000) /*!< Bit 1 */ -#define RCC_GCFGR_PLLMF_2 ((uint32_t)0x00100000) /*!< Bit 2 */ -#define RCC_GCFGR_PLLMF_3 ((uint32_t)0x00200000) /*!< Bit 3 */ -#define RCC_GCFGR_PLLMF_4 ((uint32_t)0x08000000) /*!< Bit 4 */ - -#define RCC_GCFGR_PLLMF2 ((uint32_t)0x00000000) /*!< PLL input clock*2 */ -#define RCC_GCFGR_PLLMF3 ((uint32_t)0x00040000) /*!< PLL input clock*3 */ -#define RCC_GCFGR_PLLMF4 ((uint32_t)0x00080000) /*!< PLL input clock*4 */ -#define RCC_GCFGR_PLLMF5 ((uint32_t)0x000C0000) /*!< PLL input clock*5 */ -#define RCC_GCFGR_PLLMF6 ((uint32_t)0x00100000) /*!< PLL input clock*6 */ -#define RCC_GCFGR_PLLMF7 ((uint32_t)0x00140000) /*!< PLL input clock*7 */ -#define RCC_GCFGR_PLLMF8 ((uint32_t)0x00180000) /*!< PLL input clock*8 */ -#define RCC_GCFGR_PLLMF9 ((uint32_t)0x001C0000) /*!< PLL input clock*9 */ -#define RCC_GCFGR_PLLMF10 ((uint32_t)0x00200000) /*!< PLL input clock10 */ -#define RCC_GCFGR_PLLMF11 ((uint32_t)0x00240000) /*!< PLL input clock*11 */ -#define RCC_GCFGR_PLLMF12 ((uint32_t)0x00280000) /*!< PLL input clock*12 */ -#define RCC_GCFGR_PLLMF13 ((uint32_t)0x002C0000) /*!< PLL input clock*13 */ -#define RCC_GCFGR_PLLMF14 ((uint32_t)0x00300000) /*!< PLL input clock*14 */ -#define RCC_GCFGR_PLLMF15 ((uint32_t)0x00340000) /*!< PLL input clock*15 */ -#define RCC_GCFGR_PLLMF16 ((uint32_t)0x00380000) /*!< PLL input clock*16 */ -#define RCC_GCFGR_PLLMF17 ((uint32_t)0x08000000) /*!< PLL input clock*17 */ -#define RCC_GCFGR_PLLMF18 ((uint32_t)0x08040000) /*!< PLL input clock*18 */ -#define RCC_GCFGR_PLLMF19 ((uint32_t)0x08080000) /*!< PLL input clock*19 */ -#define RCC_GCFGR_PLLMF20 ((uint32_t)0x080C0000) /*!< PLL input clock*20 */ -#define RCC_GCFGR_PLLMF21 ((uint32_t)0x08100000) /*!< PLL input clock*21 */ -#define RCC_GCFGR_PLLMF22 ((uint32_t)0x08140000) /*!< PLL input clock*22 */ -#define RCC_GCFGR_PLLMF23 ((uint32_t)0x08180000) /*!< PLL input clock*23 */ -#define RCC_GCFGR_PLLMF24 ((uint32_t)0x081C0000) /*!< PLL input clock*24 */ -#define RCC_GCFGR_PLLMF25 ((uint32_t)0x08200000) /*!< PLL input clock*25 */ -#define RCC_GCFGR_PLLMF26 ((uint32_t)0x08240000) /*!< PLL input clock*26 */ -#define RCC_GCFGR_PLLMF27 ((uint32_t)0x08280000) /*!< PLL input clock*27 */ -#define RCC_GCFGR_PLLMF28 ((uint32_t)0x082C0000) /*!< PLL input clock*28 */ -#define RCC_GCFGR_PLLMF29 ((uint32_t)0x08300000) /*!< PLL input clock*29 */ -#define RCC_GCFGR_PLLMF30 ((uint32_t)0x08340000) /*!< PLL input clock*30 */ -#define RCC_GCFGR_PLLMF31 ((uint32_t)0x08380000) /*!< PLL input clock*31 */ -#define RCC_GCFGR_PLLMF32 ((uint32_t)0x083C0000) /*!< PLL input clock*32 */ - -#define RCC_GCFGR_USBPS ((uint32_t)0x00C00000) /*!< USB Device prescaler */ -#define RCC_GCFGR_USBPS_0 ((uint32_t)0x00400000) /*!< Bit 0 */ -#define RCC_GCFGR_USBPS_1 ((uint32_t)0x00800000) /*!< Bit 1 */ - -#define RCC_GCFGR_USBPS_Div1_5 ((uint32_t)0x00000000) /*!< PLL divided by 1.5 */ -#define RCC_GCFGR_USBPS_Div1 ((uint32_t)0x00400000) /*!< PLL not divided */ -#define RCC_GCFGR_USBPS_Div2_5 ((uint32_t)0x00800000) /*!< PLL divided by 2.5 */ -#define RCC_GCFGR_USBPS_Div2 ((uint32_t)0x00C00000) /*!< PLL divided by 2 */ - -/*!< CKOUTSEL configuration */ -#define RCC_GCFGR_CKOUTSEL ((uint32_t)0x07000000) /*!< CKOUTSRC[2:0] bits (Microcontroller Clock Output) */ -#define RCC_GCFGR_CKOUTSEL_0 ((uint32_t)0x01000000) /*!< Bit 0 */ -#define RCC_GCFGR_CKOUTSEL_1 ((uint32_t)0x02000000) /*!< Bit 1 */ -#define RCC_GCFGR_CKOUTSEL_2 ((uint32_t)0x04000000) /*!< Bit 2 */ - -#define RCC_GCFGR_CKOUTSEL_NOCLOCK ((uint32_t)0x00000000) /*!< No clock */ -#define RCC_GCFGR_CKOUTSEL_SYSCLK ((uint32_t)0x04000000) /*!< System clock selected as CKOUTSRC source */ -#define RCC_GCFGR_CKOUTSEL_HSI ((uint32_t)0x05000000) /*!< HSI clock selected as CKOUTSRC source */ -#define RCC_GCFGR_CKOUTSEL_HSE ((uint32_t)0x06000000) /*!< HSE clock selected as CKOUTSRC source */ -#define RCC_GCFGR_CKOUTSEL_PLL_DIV2 ((uint32_t)0x07000000) /*!< PLL clock divided by 2 selected as CKOUTSRC source */ - -#endif /* GD32F10X_CL */ - -/*!<****************** Bit definition for RCC_GCIR register ********************/ -#define RCC_GCIR_LSISTBF ((uint32_t)0x00000001) /*!< LSI Ready Interrupt flag */ -#define RCC_GCIR_LSESTBF ((uint32_t)0x00000002) /*!< LSE Ready Interrupt flag */ -#define RCC_GCIR_HSISTBF ((uint32_t)0x00000004) /*!< HSI Ready Interrupt flag */ -#define RCC_GCIR_HSESTBF ((uint32_t)0x00000008) /*!< HSE Ready Interrupt flag */ -#define RCC_GCIR_PLLSTBF ((uint32_t)0x00000010) /*!< PLL Ready Interrupt flag */ -#define RCC_GCIR_CKMF ((uint32_t)0x00000080) /*!< Clock Security System Interrupt flag */ -#define RCC_GCIR_LSISTBIE ((uint32_t)0x00000100) /*!< LSI Ready Interrupt Enable */ -#define RCC_GCIR_LSESTBIE ((uint32_t)0x00000200) /*!< LSE Ready Interrupt Enable */ -#define RCC_GCIR_HSISTBIE ((uint32_t)0x00000400) /*!< HSI Ready Interrupt Enable */ -#define RCC_GCIR_HSESTBIE ((uint32_t)0x00000800) /*!< HSE Ready Interrupt Enable */ -#define RCC_GCIR_PLLSTBIE ((uint32_t)0x00001000) /*!< PLL Ready Interrupt Enable */ -#define RCC_GCIR_LSISTBR ((uint32_t)0x00010000) /*!< LSI Ready Interrupt Clear */ -#define RCC_GCIR_LSESTBR ((uint32_t)0x00020000) /*!< LSE Ready Interrupt Clear */ -#define RCC_GCIR_HSISTBR ((uint32_t)0x00040000) /*!< HSI Ready Interrupt Clear */ -#define RCC_GCIR_HSESTBR ((uint32_t)0x00080000) /*!< HSE Ready Interrupt Clear */ -#define RCC_GCIR_PLLSTBR ((uint32_t)0x00100000) /*!< PLL Ready Interrupt Clear */ -#define RCC_GCIR_CKMC ((uint32_t)0x00800000) /*!< Clock Security System Interrupt Clear */ - -#ifdef GD32F10X_CL -#define RCC_GCIR_PLL2STBF ((uint32_t)0x00000020) /*!< PLL2 Ready Interrupt flag */ -#define RCC_GCIR_PLL3STBF ((uint32_t)0x00000040) /*!< PLL3 Ready Interrupt flag */ -#define RCC_GCIR_PLL2STBIE ((uint32_t)0x00002000) /*!< PLL2 Ready Interrupt Enable */ -#define RCC_GCIR_PLL3STBIE ((uint32_t)0x00004000) /*!< PLL3 Ready Interrupt Enable */ -#define RCC_GCIR_PLL2STBR ((uint32_t)0x00200000) /*!< PLL2 Ready Interrupt Clear */ -#define RCC_GCIR_PLL3STBR ((uint32_t)0x00400000) /*!< PLL3 Ready Interrupt Clear */ -#endif /* GD32F10X_CL */ - -/***************** Bit definition for RCC_APB2RCR register *****************/ - -#define RCC_APB2RCR_AFRST ((uint32_t)0x00000001) /*!< Alternate Function I/O clock reset */ -#define RCC_APB2RCR_PARST ((uint32_t)0x00000004) /*!< GPIOA clock reset */ -#define RCC_APB2RCR_PBRST ((uint32_t)0x00000008) /*!< GPIOB clock reset */ -#define RCC_APB2RCR_PCRST ((uint32_t)0x00000010) /*!< GPIOC clock reset */ -#define RCC_APB2RCR_PDRST ((uint32_t)0x00000020) /*!< GPIOD clock reset */ -#define RCC_APB2RCR_PERST ((uint32_t)0x00000040) /*!< GPIOE clock reset */ -#define RCC_APB2RCR_PFRST ((uint32_t)0x00000080) /*!< GPIOF clock reset */ -#define RCC_APB2RCR_PGRST ((uint32_t)0x00000100) /*!< GPIOF clock reset */ -#define RCC_APB2RCR_ADC0RST ((uint32_t)0x00000200) /*!< ADC0 clock reset */ -#define RCC_APB2RCR_ADC1RST ((uint32_t)0x00000400) /*!< ADC1 clock reset */ -#define RCC_APB2RCR_TIMER0RST ((uint32_t)0x00000800) /*!< TIMER0 clock reset */ -#define RCC_APB2RCR_SPI1RST ((uint32_t)0x00001000) /*!< SPI1 clock reset */ -#define RCC_APB2RCR_TIMER7RST ((uint32_t)0x00002000) /*!< TIMER7 clock reset */ -#define RCC_APB2RCR_USART0RST ((uint32_t)0x00004000) /*!< USART1 clock reset */ -#define RCC_APB2RCR_ADC3RST ((uint32_t)0x00008000) /*!< ADC3 clock reset */ -#define RCC_APB2RCR_TIMER8RST ((uint32_t)0x00080000) /*!< TIMER8 clock reset */ -#define RCC_APB2RCR_TIMER9RST ((uint32_t)0x00100000) /*!< TIMER9 clock reset */ -#define RCC_APB2RCR_TIMER10RST ((uint32_t)0x00200000) /*!< TIMER10 clock reset */ - -/***************** Bit definition for RCC_APB1RCR register *****************/ - -#define RCC_APB1RCR_TIMER1RST ((uint32_t)0x00000001) /*!< TIMER1 clock reset */ -#define RCC_APB1RCR_TIMER2RST ((uint32_t)0x00000002) /*!< TIMER2 clock reset */ -#define RCC_APB1RCR_TIMER3RST ((uint32_t)0x00000004) /*!< TIMER3 clock reset */ -#define RCC_APB1RCR_TIMER4RST ((uint32_t)0x00000008) /*!< TIMER7 clock reset */ -#define RCC_APB1RCR_TIMER5RST ((uint32_t)0x00000010) /*!< TIMER5 clock reset */ -#define RCC_APB1RCR_TIMER6RST ((uint32_t)0x00000020) /*!< TIMER6 clock reset */ -#define RCC_APB1RCR_TIMER11RST ((uint32_t)0x00000040) /*!< TIMER11 clock reset */ -#define RCC_APB1RCR_TIMER12RST ((uint32_t)0x00000080) /*!< TIMER12 clock reset */ -#define RCC_APB1RCR_TIMER13RST ((uint32_t)0x00000100) /*!< TIMER13 clock reset */ -#define RCC_APB1RCR_WWDGRST ((uint32_t)0x00000800) /*!< Window Watchdog clock reset */ -#define RCC_APB1RCR_SPI2RST ((uint32_t)0x00004000) /*!< SPI2 clock reset */ -#define RCC_APB1RCR_SPI3RST ((uint32_t)0x00008000) /*!< SPI3 clock reset */ -#define RCC_APB1RCR_USART1RST ((uint32_t)0x00020000) /*!< USART 2 clock reset */ -#define RCC_APB1RCR_USART2RST ((uint32_t)0x00040000) /*!< USART 3 clock reset */ -#define RCC_APB1RCR_UART3RST ((uint32_t)0x00080000) /*!< UART 4 clock reset */ -#define RCC_APB1RCR_UART4RST ((uint32_t)0x00100000) /*!< UART 5 clock reset */ -#define RCC_APB1RCR_I2C1RST ((uint32_t)0x00200000) /*!< I2C 1 clock reset */ -#define RCC_APB1RCR_I2C2RST ((uint32_t)0x00400000) /*!< I2C 2 clock reset */ -#define RCC_APB1RCR_USBRST ((uint32_t)0x00800000) /*!< USB Device reset */ -#define RCC_APB1RCR_CAN1RST ((uint32_t)0x02000000) /*!< CAN1 Device reset */ -#define RCC_APB1RCR_CAN2RST ((uint32_t)0x04000000) /*!< CAN2 Device reset */ -#define RCC_APB1RCR_BKPRST ((uint32_t)0x08000000) /*!< BKP Device reset */ -#define RCC_APB1RCR_PWRRST ((uint32_t)0x10000000) /*!< PWR clock reset */ -#define RCC_APB1RCR_DACRST ((uint32_t)0x20000000) /*!< DAC clock reset */ - -/****************** Bit definition for RCC_AHBCCR register ******************/ -#define RCC_AHBCCR_DMA1EN ((uint32_t)0x00000001) /*!< DMA1 clock enable */ -#define RCC_AHBCCR_DMA2EN ((uint32_t)0x00000002) /*!< DMA2 clock enable */ -#define RCC_AHBCCR_SRAMEN ((uint32_t)0x00000004) /*!< SRAM interface clock enable */ -#define RCC_AHBCCR_FMCEN ((uint32_t)0x00000010) /*!< FMC clock enable */ -#define RCC_AHBCCR_CRCEN ((uint32_t)0x00000040) /*!< CRC clock enable */ -#define RCC_AHBCCR_EXMCEN ((uint32_t)0x00000100) /*!< EXMC clock enable */ - -#ifdef GD32F10X_CL -#define RCC_AHBCCR_OTGFSEN ((uint32_t)0x00001000) /*!< OTGFS clock enable */ -#define RCC_AHBCCR_ETHMACEN ((uint32_t)0x00004000) /*!< ETHMAC clock enable */ -#define RCC_AHBCCR_ETHMACRXEN ((uint32_t)0x00008000) /*!< ETHMACRX clock enable */ -#define RCC_AHBCCR_ETHMACTXEN ((uint32_t)0x00010000) /*!< ETHMACTX clock enable */ - -#else -#define RCC_AHBCCR_SDIOEN ((uint32_t)0x00000400) /*!< SDIO clock enable */ -#endif/* GD32F10X_CL */ - -/***************** Bit definition for RCC_APB2CCR register ******************/ -#define RCC_APB2CCR_AFEN ((uint32_t)0x00000001) /*!< Alternate Function I/O clock enable */ -#define RCC_APB2CCR_PAEN ((uint32_t)0x00000004) /*!< GPIOA clock enable */ -#define RCC_APB2CCR_PBEN ((uint32_t)0x00000008) /*!< GPIOB clock enable */ -#define RCC_APB2CCR_PCEN ((uint32_t)0x00000010) /*!< GPIOC clock enable */ -#define RCC_APB2CCR_PDEN ((uint32_t)0x00000020) /*!< GPIOD clock enable */ -#define RCC_APB2CCR_PEEN ((uint32_t)0x00000040) /*!< GPIOE clock enable */ -#define RCC_APB2CCR_PFEN ((uint32_t)0x00000080) /*!< GPIOF clock enable */ -#define RCC_APB2CCR_PGEN ((uint32_t)0x00000100) /*!< GPIOF clock enable */ -#define RCC_APB2CCR_ADC0EN ((uint32_t)0x00000200) /*!< ADC0 clock enable */ -#define RCC_APB2CCR_ADC1EN ((uint32_t)0x00000400) /*!< ADC1 clock enable */ -#define RCC_APB2CCR_TIMER0EN ((uint32_t)0x00000800) /*!< TIMER0 clock enable */ -#define RCC_APB2CCR_SPI1EN ((uint32_t)0x00001000) /*!< SPI1 clock enable */ -#define RCC_APB2CCR_TIMER7EN ((uint32_t)0x00002000) /*!< TIMER7 clock enable */ -#define RCC_APB2CCR_USART1EN ((uint32_t)0x00004000) /*!< USART1 clock enable */ -#define RCC_APB2CCR_ADC3EN ((uint32_t)0x00008000) /*!< ADC3 clock enable */ -#define RCC_APB2CCR_TIMER8EN ((uint32_t)0x00080000) /*!< TIMER8 clock enable */ -#define RCC_APB2CCR_TIMER9EN ((uint32_t)0x00100000) /*!< TIMER9 clock enable */ -#define RCC_APB2CCR_TIMER10EN ((uint32_t)0x00200000) /*!< TIMER10 clock enable */ - -/***************** Bit definition for RCC_APB1CCR register ******************/ - -#define RCC_APB1CCR_TIMER1EN ((uint32_t)0x00000001) /*!< TIMER1 clock enable */ -#define RCC_APB1CCR_TIMER2EN ((uint32_t)0x00000002) /*!< TIMER2 clock enable */ -#define RCC_APB1CCR_TIMER3EN ((uint32_t)0x00000004) /*!< TIMER3 clock enable */ -#define RCC_APB1CCR_TIMER4EN ((uint32_t)0x00000008) /*!< TIMER7 clock enable */ -#define RCC_APB1CCR_TIMER5EN ((uint32_t)0x00000010) /*!< TIMER5 clock enable */ -#define RCC_APB1CCR_TIMER6EN ((uint32_t)0x00000020) /*!< TIMER6 clock enable */ -#define RCC_APB1CCR_TIMER11EN ((uint32_t)0x00000040) /*!< TIMER11 clock enable */ -#define RCC_APB1CCR_TIMER12EN ((uint32_t)0x00000080) /*!< TIMER12 clock enable */ -#define RCC_APB1CCR_TIMER13EN ((uint32_t)0x00000100) /*!< TIMER13 clock enable */ -#define RCC_APB1CCR_WWDGEN ((uint32_t)0x00000800) /*!< Window Watchdog clock enable */ -#define RCC_APB1CCR_SPI2EN ((uint32_t)0x00004000) /*!< SPI2 clock enable */ -#define RCC_APB1CCR_SPI3EN ((uint32_t)0x00008000) /*!< SPI3 clock enable*/ -#define RCC_APB1CCR_USART2EN ((uint32_t)0x00020000) /*!< USART 2 clock enable */ -#define RCC_APB1CCR_USART3EN ((uint32_t)0x00040000) /*!< USART 3 clock enable */ -#define RCC_APB1CCR_UART4EN ((uint32_t)0x00080000) /*!< UART 4 clock enable */ -#define RCC_APB1CCR_UART5EN ((uint32_t)0x00100000) /*!< UART 5 clock enable */ -#define RCC_APB1CCR_I2C1EN ((uint32_t)0x00200000) /*!< I2C 1 clock enable */ -#define RCC_APB1CCR_I2C2EN ((uint32_t)0x00400000) /*!< I2C 2 clock enable */ -#define RCC_APB1CCR_USBEN ((uint32_t)0x00800000) /*!< USB Device enable */ -#define RCC_APB1CCR_CAN1EN ((uint32_t)0x02000000) /*!< CAN1 Device enable */ -#define RCC_APB1CCR_CAN2EN ((uint32_t)0x04000000) /*!< CAN2 Device enable */ -#define RCC_APB1CCR_BKPEN ((uint32_t)0x08000000) /*!< BKP Device enable */ -#define RCC_APB1CCR_PWREN ((uint32_t)0x10000000) /*!< PWR clock enable */ -#define RCC_APB1CCR_DACEN ((uint32_t)0x20000000) /*!< DAC clock enable */ - -/******************* Bit definition for RCC_BDCR register *******************/ -#define RCC_BDCR_LSEEN ((uint32_t)0x00000001) /*!< External Low Speed oscillator enable */ -#define RCC_BDCR_LSESTB ((uint32_t)0x00000002) /*!< External Low Speed oscillator Ready */ -#define RCC_BDCR_LSEBPS ((uint32_t)0x00000004) /*!< External Low Speed oscillator Bypass */ - -#define RCC_BDCR_RTCSEL ((uint32_t)0x00000300) /*!< RTCSEL[1:0] bits (RTC clock source selection) */ -#define RCC_BDCR_RTCSEL_0 ((uint32_t)0x00000100) /*!< Bit 0 */ -#define RCC_BDCR_RTCSEL_1 ((uint32_t)0x00000200) /*!< Bit 1 */ - -/*!< RTC congiguration */ -#define RCC_BDCR_RTCSEL_NOCLOCK ((uint32_t)0x00000000) /*!< No clock */ -#define RCC_BDCR_RTCSEL_LSE ((uint32_t)0x00000100) /*!< LSE oscillator clock used as RTC clock */ -#define RCC_BDCR_RTCSEL_LSI ((uint32_t)0x00000200) /*!< LSI oscillator clock used as RTC clock */ -#define RCC_BDCR_RTCSEL_HSE128 ((uint32_t)0x00000300) /*!< HSE oscillator clock divided by 128 used as RTC clock */ - -#define RCC_BDCR_RTCEN ((uint32_t)0x00008000) /*!< RTC clock enable */ -#define RCC_BDCR_BKPRST ((uint32_t)0x00010000) /*!< Backup domain software reset */ - -/******************* Bit definition for RCC_GCSR register ********************/ -#define RCC_GCSR_LSIEN ((uint32_t)0x00000001) /*!< Internal Low Speed oscillator enable */ -#define RCC_GCSR_LSISTB ((uint32_t)0x00000002) /*!< Internal Low Speed oscillator Ready */ -#define RCC_GCSR_RSTFC ((uint32_t)0x01000000) /*!< Remove reset flag */ -#define RCC_GCSR_EPRSTF ((uint32_t)0x04000000) /*!< PIN reset flag */ -#define RCC_GCSR_POPDRSTF ((uint32_t)0x08000000) /*!< POR/PDR reset flag */ -#define RCC_GCSR_SWRSTF ((uint32_t)0x10000000) /*!< Software Reset flag */ -#define RCC_GCSR_IWDGRSTF ((uint32_t)0x20000000) /*!< Independent Watchdog reset flag */ -#define RCC_GCSR_WWDGRSTF ((uint32_t)0x40000000) /*!< Window watchdog reset flag */ -#define RCC_GCSR_LPRSTF ((uint32_t)0x80000000) /*!< Low-Power reset flag */ - -/***************** Bit definition for RCC_DEEPSLEEP_VC register *****************/ -#define RCC_DEEPSLEEP_VC_CLEAR ((uint32_t)0x00000003) /*!< RCC_DEEPSLEEP_VC[2:0] bits */ -#define RCC_DEEPSLEEP_VC_0 ((uint32_t)0x00000000) /*!< Bit 0 bits */ -#define RCC_DEEPSLEEP_VC_1 ((uint32_t)0x00000002) /*!< Bit 1 bits */ -#define RCC_DEEPSLEEP_VC_2 ((uint32_t)0x00000004) /*!< Bit 2 bits */ -#define RCC_DEEPSLEEP_VC1_2 ((uint32_t)0x00000000) /*!< The kernel voltage in Deep-sleep mode is 1.2V */ -#define RCC_DEEPSLEEP_VC1_1 ((uint32_t)0x00000001) /*!< The kernel voltage in Deep-sleep is 1.1V */ -#define RCC_DEEPSLEEP_VC1_0 ((uint32_t)0x00000002) /*!< The kernel voltage in Deep-sleep is 1.0V */ -#define RCC_DEEPSLEEP_VC0_9 ((uint32_t)0x00000003) /*!< The kernel voltage in Deep-sleep is 0.9V */ - - -#ifdef GD32F10X_CL -/******************* Bit definition for RCC_AHBRCR register ****************/ -#define RCC_AHBRCR_OTGFSRST ((uint32_t)0x00001000) /*!< OTGFS clock reset */ -#define RCC_AHBRCR_ETHMACRST ((uint32_t)0x00004000) /*!< ETHMAC clock reset */ - -/******************* Bit definition for RCC_GCFGR2 register ******************/ -/*!< PREDIV1 configuration */ -#define RCC_GCFGR2_PREDV1 ((uint32_t)0x0000000F) /*!< PREDIV1[3:0] bits */ -#define RCC_GCFGR2_PREDV1_0 ((uint32_t)0x00000001) /*!< Bit 0 */ -#define RCC_GCFGR2_PREDV1_1 ((uint32_t)0x00000002) /*!< Bit 1 */ -#define RCC_GCFGR2_PREDV1_2 ((uint32_t)0x00000004) /*!< Bit 2 */ -#define RCC_GCFGR2_PREDV1_3 ((uint32_t)0x00000008) /*!< Bit 3 */ - -#define RCC_GCFGR2_PREDV1_DIV1 ((uint32_t)0x00000000) /*!< PREDV1 input clock not divided */ -#define RCC_GCFGR2_PREDV1_DIV2 ((uint32_t)0x00000001) /*!< PREDV1 input clock divided by 2 */ -#define RCC_GCFGR2_PREDV1_DIV3 ((uint32_t)0x00000002) /*!< PREDV1 input clock divided by 3 */ -#define RCC_GCFGR2_PREDV1_DIV4 ((uint32_t)0x00000003) /*!< PREDV1 input clock divided by 4 */ -#define RCC_GCFGR2_PREDV1_DIV5 ((uint32_t)0x00000004) /*!< PREDV1 input clock divided by 5 */ -#define RCC_GCFGR2_PREDV1_DIV6 ((uint32_t)0x00000005) /*!< PREDV1 input clock divided by 6 */ -#define RCC_GCFGR2_PREDV1_DIV7 ((uint32_t)0x00000006) /*!< PREDV1 input clock divided by 7 */ -#define RCC_GCFGR2_PREDV1_DIV8 ((uint32_t)0x00000007) /*!< PREDV1 input clock divided by 8 */ -#define RCC_GCFGR2_PREDV1_DIV9 ((uint32_t)0x00000008) /*!< PREDV1 input clock divided by 9 */ -#define RCC_GCFGR2_PREDV1_DIV10 ((uint32_t)0x00000009) /*!< PREDV1 input clock divided by 10 */ -#define RCC_GCFGR2_PREDV1_DIV11 ((uint32_t)0x0000000A) /*!< PREDV1 input clock divided by 11 */ -#define RCC_GCFGR2_PREDV1_DIV12 ((uint32_t)0x0000000B) /*!< PREDV1 input clock divided by 12 */ -#define RCC_GCFGR2_PREDV1_DIV13 ((uint32_t)0x0000000C) /*!< PREDV1 input clock divided by 13 */ -#define RCC_GCFGR2_PREDV1_DIV14 ((uint32_t)0x0000000D) /*!< PREDV1 input clock divided by 14 */ -#define RCC_GCFGR2_PREDV1_DIV15 ((uint32_t)0x0000000E) /*!< PREDV1 input clock divided by 15 */ -#define RCC_GCFGR2_PREDV1_DIV16 ((uint32_t)0x0000000F) /*!< PREDV1 input clock divided by 16 */ - - -/*!< PREDIV2 configuration */ -#define RCC_GCFGR2_PREDV2 ((uint32_t)0x000000F0) /*!< PREDIV2[3:0] bits */ -#define RCC_GCFGR2_PREDV2_0 ((uint32_t)0x00000010) /*!< Bit 0 */ -#define RCC_GCFGR2_PREDV2_1 ((uint32_t)0x00000020) /*!< Bit 1 */ -#define RCC_GCFGR2_PREDV2_2 ((uint32_t)0x00000040) /*!< Bit 2 */ -#define RCC_GCFGR2_PREDV2_3 ((uint32_t)0x00000080) /*!< Bit 3 */ - -#define RCC_GCFGR2_PREDV2_DIV1 ((uint32_t)0x00000000) /*!< PREDV1 input clock not divided */ -#define RCC_GCFGR2_PREDV2_DIV2 ((uint32_t)0x00000010) /*!< PREDV1 input clock divided by 2 */ -#define RCC_GCFGR2_PREDV2_DIV3 ((uint32_t)0x00000020) /*!< PREDV1 input clock divided by 3 */ -#define RCC_GCFGR2_PREDV2_DIV4 ((uint32_t)0x00000030) /*!< PREDV1 input clock divided by 4 */ -#define RCC_GCFGR2_PREDV2_DIV5 ((uint32_t)0x00000040) /*!< PREDV1 input clock divided by 5 */ -#define RCC_GCFGR2_PREDV2_DIV6 ((uint32_t)0x00000050) /*!< PREDV1 input clock divided by 6 */ -#define RCC_GCFGR2_PREDV2_DIV7 ((uint32_t)0x00000060) /*!< PREDV1 input clock divided by 7 */ -#define RCC_GCFGR2_PREDV2_DIV8 ((uint32_t)0x00000070) /*!< PREDV1 input clock divided by 8 */ -#define RCC_GCFGR2_PREDV2_DIV9 ((uint32_t)0x00000080) /*!< PREDV1 input clock divided by 9 */ -#define RCC_GCFGR2_PREDV2_DIV10 ((uint32_t)0x00000090) /*!< PREDV1 input clock divided by 10 */ -#define RCC_GCFGR2_PREDV2_DIV11 ((uint32_t)0x000000A0) /*!< PREDV1 input clock divided by 11 */ -#define RCC_GCFGR2_PREDV2_DIV12 ((uint32_t)0x000000B0) /*!< PREDV1 input clock divided by 12 */ -#define RCC_GCFGR2_PREDV2_DIV13 ((uint32_t)0x000000C0) /*!< PREDV1 input clock divided by 13 */ -#define RCC_GCFGR2_PREDV2_DIV14 ((uint32_t)0x000000D0) /*!< PREDV1 input clock divided by 14 */ -#define RCC_GCFGR2_PREDV2_DIV15 ((uint32_t)0x000000E0) /*!< PREDV1 input clock divided by 15 */ -#define RCC_GCFGR2_PREDV2_DIV16 ((uint32_t)0x000000F0) /*!< PREDV1 input clock divided by 16 */ - -/*!< PLL2MF configuration */ -#define RCC_GCFGR2_PLL2MF ((uint32_t)0x00000F00) /*!< PLL2MF[4:0] bits (PLL2 multiplication factor) */ -#define RCC_GCFGR2_PLL2MF_0 ((uint32_t)0x00000100) /*!< Bit 0 */ -#define RCC_GCFGR2_PLL2MF_1 ((uint32_t)0x00000200) /*!< Bit 1 */ -#define RCC_GCFGR2_PLL2MF_2 ((uint32_t)0x00000400) /*!< Bit 2 */ -#define RCC_GCFGR2_PLL2MF_3 ((uint32_t)0x00000800) /*!< Bit 3 */ - -#define RCC_GCFGR2_PLL2MF8 ((uint32_t)0x00000600) /*!< PLL2 input clock*8 */ -#define RCC_GCFGR2_PLL2MF9 ((uint32_t)0x00000700) /*!< PLL2 input clock*9 */ -#define RCC_GCFGR2_PLL2MF10 ((uint32_t)0x00000800) /*!< PLL2 input clock10 */ -#define RCC_GCFGR2_PLL2MF11 ((uint32_t)0x00000900) /*!< PLL2 input clock*11 */ -#define RCC_GCFGR2_PLL2MF12 ((uint32_t)0x00000A00) /*!< PLL2 input clock*12 */ -#define RCC_GCFGR2_PLL2MF13 ((uint32_t)0x00000B00) /*!< PLL2 input clock*13 */ -#define RCC_GCFGR2_PLL2MF14 ((uint32_t)0x00000C00) /*!< PLL2 input clock*14 */ -#define RCC_GCFGR2_PLL2MF16 ((uint32_t)0x00000E00) /*!< PLL2 input clock*16 */ -#define RCC_GCFGR2_PLL2MF20 ((uint32_t)0x00000F00) /*!< PLL2 input clock*20 */ - -/*!< PLL3MF configuration */ -#define RCC_GCFGR2_PLL3MF ((uint32_t)0x0000F000) /*!< PLL3MF[4:0] bits (PLL3 multiplication factor) */ -#define RCC_GCFGR2_PLL3MF_0 ((uint32_t)0x00001000) /*!< Bit 0 */ -#define RCC_GCFGR2_PLL3MF_1 ((uint32_t)0x00002000) /*!< Bit 1 */ -#define RCC_GCFGR2_PLL3MF_2 ((uint32_t)0x00004000) /*!< Bit 2 */ -#define RCC_GCFGR2_PLL3MF_3 ((uint32_t)0x00008000) /*!< Bit 3 */ - -#define RCC_GCFGR2_PLL3MF8 ((uint32_t)0x00006000) /*!< PLL input clock*8 */ -#define RCC_GCFGR2_PLL3MF9 ((uint32_t)0x00007000) /*!< PLL input clock*9 */ -#define RCC_GCFGR2_PLL3MF10 ((uint32_t)0x00008000) /*!< PLL input clock10 */ -#define RCC_GCFGR2_PLL3MF11 ((uint32_t)0x00009000) /*!< PLL input clock*11 */ -#define RCC_GCFGR2_PLL3MF12 ((uint32_t)0x0000A000) /*!< PLL input clock*12 */ -#define RCC_GCFGR2_PLL3MF13 ((uint32_t)0x0000B000) /*!< PLL input clock*13 */ -#define RCC_GCFGR2_PLL3MF14 ((uint32_t)0x0000C000) /*!< PLL input clock*14 */ -#define RCC_GCFGR2_PLL3MF16 ((uint32_t)0x0000E000) /*!< PLL input clock*16 */ -#define RCC_GCFGR2_PLL3MF20 ((uint32_t)0x0000F000) /*!< PLL input clock*20 */ - -/*!< PREDV1SEL configuration */ -#define RCC_GCFGR2_PREDV1SEL ((uint32_t)0x00010000) /*!< PREDV1SEL bit for entry clock source */ -#define RCC_GCFGR2_PREDV1SEL_HSE ((uint32_t)0x00000000) /*!< HSE clock selected as PREDV1 entry clock source */ -#define RCC_GCFGR2_PREDV1SEL_PLL2 ((uint32_t)0x00010000) /*!< PLL2 clock selected as PREDV1 entry clock source */ - -/*!< PREDV1SEL configuration */ -#define RCC_GCFGR2_I2S2SEL ((uint32_t)0x00020000) /*!< I2S2SEL bit for entry clock source */ -#define RCC_GCFGR2_I2S2SEL_CK_SYS ((uint32_t)0x00000000) /*!< CK_SYS clock selected as I2S2 entry clock source */ -#define RCC_GCFGR2_I2S2SEL_PLL3 ((uint32_t)0x00020000) /*!< PLL3 clock selected as I2S2 entry clock source */ - - -/*!< PREDV1SEL configuration */ -#define RCC_GCFGR2_I2S3SEL ((uint32_t)0x00040000) /*!< I2S3SEL bit for entry clock source */ -#define RCC_GCFGR2_I2S3SEL_CK_SYS ((uint32_t)0x00000000) /*!< CK_SYS clock selected as I2S3 entry clock source */ -#define RCC_GCFGR2_I2S3SEL_PLL3 ((uint32_t)0x00040000) /*!< PLL3 clock selected as I2S3 entry clock source */ - -#endif/* GD32F10X_CL */ - -/******************************************************************************/ -/* */ -/* Real-Time Clock (RTC) */ -/* */ -/******************************************************************************/ - -/******************** Bits definition for RTC_TR register *******************/ - -/******************** Bits definition for RTC_CTLR1 register ****************/ -#define RTC_CTLR1_SIE ((uint8_t)0x01) /*!< RTC Second Interrupt Enable */ -#define RTC_CTLR1_AIE ((uint8_t)0x02) /*!< RTC Alarm Interrupt Enable */ -#define RTC_CTLR1_OVIE ((uint8_t)0x04) /*!< RTC OverfloW Interrupt Enable */ - -/******************** Bits definition for RTC_CTLR2 register ****************/ -#define RTC_CTLR2_SF ((uint8_t)0x01) /*!< RTC Second Flag */ -#define RTC_CTLR2_AF ((uint8_t)0x02) /*!< RTC Alarm Flag */ -#define RTC_CTLR2_OVF ((uint8_t)0x04) /*!< RTC OverfloW Flag */ -#define RTC_CTLR2_RSF ((uint8_t)0x08) /*!< RTC Registers Synchronized Flag */ -#define RTC_CTLR2_CMF ((uint8_t)0x10) /*!< RTC Configuration Mode Flag */ -#define RTC_CTLR2_LWOFF ((uint8_t)0x20) /*!< RTC Last Write Operation OFF */ - -/******************** Bits definition for RTC_PLR1 register *****************/ -#define RTC_PLR1_PLR ((uint16_t)0x000F) /*!< RTC Prescaler Value High */ - -/******************** Bits definition for RTC_PLR2 register *****************/ -#define RTC_PLR2_PLR ((uint16_t)0xFFFF) /*!< RTC Prescaler Value Low*/ - -/******************** Bits definition for RTC_PREDIV1 register **************/ -#define RTC_PREDIV1_RTC_PREDIV ((uint16_t)0x000F) /*!< RTC Divider Value High */ - -/******************** Bits definition for RTC_PREDIV2 register **************/ -#define RTC_PREDIV2_RTC_PREDIV ((uint16_t)0xFFFF) /*!< RTC Divider Value Low */ - -/******************** Bits definition for RTC_CNT1 register *****************/ -#define RTC_CNT1_RTC_CNT ((uint16_t)0xFFFF) /*!< RTC Counter Value High */ - -/******************** Bits definition for RTC_CNT2 register *****************/ -#define RTC_CNT2_RTC_CNT ((uint16_t)0xFFFF) /*!< RTC Counter Value Low */ - -/******************** Bits definition for RTC_ALRMR1 register ***************/ -#define RTC_ALRMR1_RTC_ALRMR ((uint16_t)0xFFFF) /*!< RTC Alarm Value High */ - -/******************** Bits definition for RTC_ALRMR2 register ***************/ -#define RTC_ALRMR2_RTC_ALRMR ((uint16_t)0xFFFF) /*!< RTC Alarm Value Low */ - -/******************************************************************************/ -/* */ -/* SD host Interface */ -/* */ -/******************************************************************************/ - -/****************** Bit definition for SDIO_POWER register ******************/ -#define SDIO_POWER_PWRSTATE ((uint8_t)0x03) /*!< PWRSTATE[1:0] bits (Power supply control bits) */ -#define SDIO_POWER_PWRSTATE_0 ((uint8_t)0x01) /*!< Bit 0 */ -#define SDIO_POWER_PWRSTATE_1 ((uint8_t)0x02) /*!< Bit 1 */ - -/****************** Bit definition for SDIO_CLKCTLR register *****************/ -#define SDIO_CLKCTLR_DIV ((uint16_t)0x00FF) /*!< Clock divide factor */ -#define SDIO_CLKCTLR_CKEN ((uint16_t)0x0100) /*!< Clock enable bit */ -#define SDIO_CLKCTLR_PWRSAV ((uint16_t)0x0200) /*!< Power saving configuration bit */ -#define SDIO_CLKCTLR_BYPASS ((uint16_t)0x0400) /*!< Clock divider bypass enable bit */ - -#define SDIO_CLKCTLR_BUSMODE ((uint16_t)0x1800) /*!< BUSMODE[1:0] bits (Wide bus mode enable bit) */ -#define SDIO_CLKCTLR_BUSMODE_0 ((uint16_t)0x0800) /*!< Bit 0 */ -#define SDIO_CLKCTLR_BUSMODE_1 ((uint16_t)0x1000) /*!< Bit 1 */ - -#define SDIO_CLKCTLR_CKPH ((uint16_t)0x2000) /*!< SDIO_CLK dephasing selection bit */ -#define SDIO_CLKCTLR_HWFL_EN ((uint16_t)0x4000) /*!< HW Flow Control enable */ - -/******************* Bit definition for SDIO_PARA register ******************/ -#define SDIO_PARA_CMDARG ((uint32_t)0xFFFFFFFF) /*!< Command argument */ - -/******************* Bit definition for SDIO_CMD register *******************/ -#define SDIO_CMD_CMDINDEX ((uint16_t)0x003F) /*!< Command Index */ - -#define SDIO_CMD_WAITRESP ((uint16_t)0x00C0) /*!< WAITRESP[1:0] bits (Wait for response bits) */ -#define SDIO_CMD_WAITRESP_0 ((uint16_t)0x0040) /*!< Bit 0 */ -#define SDIO_CMD_WAITRESP_1 ((uint16_t)0x0080) /*!< Bit 1 */ - -#define SDIO_CMD_WAITINT ((uint16_t)0x0100) /*!< CPSM Waits for Interrupt Request */ -#define SDIO_CMD_WAITPD ((uint16_t)0x0200) /*!< CPSM Waits for ends of data transfer (CmdPend internal signal) */ -#define SDIO_CMD_CSMEN ((uint16_t)0x0400) /*!< Command state machine (CSM) Enable bit */ -#define SDIO_CMD_SDIOSUSPEND ((uint16_t)0x0800) /*!< SD I/O suspend command */ -#define SDIO_CMD_ENCMDC ((uint16_t)0x1000) /*!< Enable CMD completion */ -#define SDIO_CMD_NIEN ((uint16_t)0x2000) /*!< Not Interrupt Enable */ -#define SDIO_CMD_ATACMD ((uint16_t)0x4000) /*!< CE-ATA command */ - -/***************** Bit definition for SDIO_RESPCMD register *****************/ -#define SDIO_RESPCMD_RESPCMD ((uint8_t)0x3F) /*!< Response command index */ - -/****************** Bit definition for SDIO_RESP1 register ******************/ -#define SDIO_RESP1_CARDSTATE1 ((uint32_t)0xFFFFFFFF) /*!< Card State */ - -/****************** Bit definition for SDIO_RESP2 register ******************/ -#define SDIO_RESP2_CARDSTATE2 ((uint32_t)0xFFFFFFFF) /*!< Card State */ - -/****************** Bit definition for SDIO_RESP3 register ******************/ -#define SDIO_RESP3_CARDSTATE3 ((uint32_t)0xFFFFFFFF) /*!< Card State */ - -/****************** Bit definition for SDIO_RESP4 register ******************/ -#define SDIO_RESP4_CARDSTATE4 ((uint32_t)0xFFFFFFFF) /*!< Card State */ - -/****************** Bit definition for SDIO_DTTR register *******************/ -#define SDIO_DTTR_DTTIME ((uint32_t)0xFFFFFFFF) /*!< Data timeout period. */ - -/****************** Bit definition for SDIO_DTLEN register ******************/ -#define SDIO_DTLEN_DTLEN ((uint32_t)0x01FFFFFF) /*!< Data length value */ - -/****************** Bit definition for SDIO_DTCTLR register *****************/ -#define SDIO_DTCTLR_DTTEN ((uint16_t)0x0001) /*!< Data transfer enabled bit */ -#define SDIO_DTCTLR_DTTDIR ((uint16_t)0x0002) /*!< Data transfer direction selection */ -#define SDIO_DTCTLR_DTTMODE ((uint16_t)0x0004) /*!< Data transfer mode selection */ -#define SDIO_DTCTLR_DMAEN ((uint16_t)0x0008) /*!< DMA enabled bit */ - -#define SDIO_DTCTLR_DTBLKSIZE ((uint16_t)0x00F0) /*!< DTBLKSIZE[3:0] bits (Data block size) */ -#define SDIO_DTCTLR_DTBLKSIZE_0 ((uint16_t)0x0010) /*!< Bit 0 */ -#define SDIO_DTCTLR_DTBLKSIZE_1 ((uint16_t)0x0020) /*!< Bit 1 */ -#define SDIO_DTCTLR_DTBLKSIZE_2 ((uint16_t)0x0040) /*!< Bit 2 */ -#define SDIO_DTCTLR_DTBLKSIZE_3 ((uint16_t)0x0080) /*!< Bit 3 */ - -#define SDIO_DTCTLR_RWSTART ((uint16_t)0x0100) /*!< Read wait start */ -#define SDIO_DTCTLR_RWSTOP ((uint16_t)0x0200) /*!< Read wait stop */ -#define SDIO_DTCTLR_RWMODE ((uint16_t)0x0400) /*!< Read wait mode */ -#define SDIO_DTCTLR_SDIOEN ((uint16_t)0x0800) /*!< SD I/O enable functions */ - -/****************** Bit definition for SDIO_DTCNT register ******************/ -#define SDIO_DTCNT_DTCNT ((uint32_t)0x01FFFFFF) /*!< Data count value */ - -/****************** Bit definition for SDIO_STR register ********************/ -#define SDIO_STR_CCRCFAIL ((uint32_t)0x00000001) /*!< Command response received (CRC check failed) */ -#define SDIO_STR_DTCRCFAIL ((uint32_t)0x00000002) /*!< Data block sent/received (CRC check failed) */ -#define SDIO_STR_CMDTMOUT ((uint32_t)0x00000004) /*!< Command response timeout */ -#define SDIO_STR_DTTMOUT ((uint32_t)0x00000008) /*!< Data timeout */ -#define SDIO_STR_TXURE ((uint32_t)0x00000010) /*!< Transmit FIFO underrun error */ -#define SDIO_STR_RXORE ((uint32_t)0x00000020) /*!< Received FIFO overrun error */ -#define SDIO_STR_CMDREND ((uint32_t)0x00000040) /*!< Command response received (CRC check passed) */ -#define SDIO_STR_CMDSENT ((uint32_t)0x00000080) /*!< Command sent (no response required) */ -#define SDIO_STR_DTEND ((uint32_t)0x00000100) /*!< Data end (data counter, SDIDCOUNT, is zero) */ -#define SDIO_STR_STBITE ((uint32_t)0x00000200) /*!< Start bit not detected on all data signals in wide bus mode */ -#define SDIO_STR_DTBLKEND ((uint32_t)0x00000400) /*!< Data block sent/received (CRC check passed) */ -#define SDIO_STR_CMDRUN ((uint32_t)0x00000800) /*!< Command transfer in progress */ -#define SDIO_STR_TXRUN ((uint32_t)0x00001000) /*!< Data transmit in progress */ -#define SDIO_STR_RXRUN ((uint32_t)0x00002000) /*!< Data receive in progress */ -#define SDIO_STR_TXFIFOHE ((uint32_t)0x00004000) /*!< Transmit FIFO Half Empty: at least 8 words can be written into the FIFO */ -#define SDIO_STR_RXFIFOHF ((uint32_t)0x00008000) /*!< Receive FIFO Half Full: there are at least 8 words in the FIFO */ -#define SDIO_STR_TXFIFOF ((uint32_t)0x00010000) /*!< Transmit FIFO full */ -#define SDIO_STR_RXFIFOF ((uint32_t)0x00020000) /*!< Receive FIFO full */ -#define SDIO_STR_TXFIFOE ((uint32_t)0x00040000) /*!< Transmit FIFO empty */ -#define SDIO_STR_RXFIFOE ((uint32_t)0x00080000) /*!< Receive FIFO empty */ -#define SDIO_STR_TXDTVAL ((uint32_t)0x00100000) /*!< Data available in transmit FIFO */ -#define SDIO_STR_RXDTVAL ((uint32_t)0x00200000) /*!< Data available in receive FIFO */ -#define SDIO_STR_SDIOINT ((uint32_t)0x00400000) /*!< SDIO interrupt received */ -#define SDIO_STR_ATAEND ((uint32_t)0x00800000) /*!< CE-ATA command completion signal received for CMD61 */ - -/******************* Bit definition for SDIO_INTCR register *****************/ -#define SDIO_INTCR_CCRCFAILC ((uint32_t)0x00000001) /*!< CCRCFAIL flag clear bit */ -#define SDIO_INTCR_DTCRCFAILC ((uint32_t)0x00000002) /*!< DTCRCFAIL flag clear bit */ -#define SDIO_INTCR_CMDTMOUTC ((uint32_t)0x00000004) /*!< CMDTMOUT flag clear bit */ -#define SDIO_INTCR_DTTMOUTC ((uint32_t)0x00000008) /*!< DTTMOUT flag clear bit */ -#define SDIO_INTCR_TXUREC ((uint32_t)0x00000010) /*!< TXURE flag clear bit */ -#define SDIO_INTCR_RXOREC ((uint32_t)0x00000020) /*!< RXORE flag clear bit */ -#define SDIO_INTCR_CMDRENDC ((uint32_t)0x00000040) /*!< CMDREND flag clear bit */ -#define SDIO_INTCR_CMDSENTC ((uint32_t)0x00000080) /*!< CMDSENT flag clear bit */ -#define SDIO_INTCR_DTENDC ((uint32_t)0x00000100) /*!< DTEND flag clear bit */ -#define SDIO_INTCR_STBITEC ((uint32_t)0x00000200) /*!< STBITE flag clear bit */ -#define SDIO_INTCR_DTBLKENDC ((uint32_t)0x00000400) /*!< DTBLKEND flag clear bit */ -#define SDIO_INTCR_SDIOINTC ((uint32_t)0x00400000) /*!< SDIOINT flag clear bit */ -#define SDIO_INTCR_ATAENDC ((uint32_t)0x00800000) /*!< ATAEND flag clear bit */ - -/****************** Bit definition for SDIO_IER register ********************/ -#define SDIO_IER_CCRCFAILIE ((uint32_t)0x00000001) /*!< Command CRC Fail Interrupt Enable */ -#define SDIO_IER_DTCRCFAILIE ((uint32_t)0x00000002) /*!< Data CRC Fail Interrupt Enable */ -#define SDIO_IER_CMDTMOUTIE ((uint32_t)0x00000004) /*!< Command TimeOut Interrupt Enable */ -#define SDIO_IER_DTTMOUTIE ((uint32_t)0x00000008) /*!< Data TimeOut Interrupt Enable */ -#define SDIO_IER_TXUREIE ((uint32_t)0x00000010) /*!< Tx FIFO UnderRun Error Interrupt Enable */ -#define SDIO_IER_RXOREIE ((uint32_t)0x00000020) /*!< Rx FIFO OverRun Error Interrupt Enable */ -#define SDIO_IER_CMDRENDIE ((uint32_t)0x00000040) /*!< Command Response Received Interrupt Enable */ -#define SDIO_IER_CMDSENTIE ((uint32_t)0x00000080) /*!< Command Sent Interrupt Enable */ -#define SDIO_IER_DTENDIE ((uint32_t)0x00000100) /*!< Data End Interrupt Enable */ -#define SDIO_IER_STBITEIE ((uint32_t)0x00000200) /*!< Start Bit Error Interrupt Enable */ -#define SDIO_IER_DTBLKENDIE ((uint32_t)0x00000400) /*!< Data Block End Interrupt Enable */ -#define SDIO_IER_CMDRUNIE ((uint32_t)0x00000800) /*!< Command Acting Interrupt Enable */ -#define SDIO_IER_TXRUNIE ((uint32_t)0x00001000) /*!< Data Transmit Acting Interrupt Enable */ -#define SDIO_IER_RXRUNIE ((uint32_t)0x00002000) /*!< Data receive acting interrupt enabled */ -#define SDIO_IER_TXFIFOHEIE ((uint32_t)0x00004000) /*!< Tx FIFO Half Empty interrupt Enable */ -#define SDIO_IER_RXFIFOHFIE ((uint32_t)0x00008000) /*!< Rx FIFO Half Full interrupt Enable */ -#define SDIO_IER_TXFIFOFIE ((uint32_t)0x00010000) /*!< Tx FIFO Full interrupt Enable */ -#define SDIO_IER_RXFIFOFIE ((uint32_t)0x00020000) /*!< Rx FIFO Full interrupt Enable */ -#define SDIO_IER_TXFIFOEIE ((uint32_t)0x00040000) /*!< Tx FIFO Empty interrupt Enable */ -#define SDIO_IER_RXFIFOEIE ((uint32_t)0x00080000) /*!< Rx FIFO Empty interrupt Enable */ -#define SDIO_IER_TXDTVALIE ((uint32_t)0x00100000) /*!< Data available in Tx FIFO interrupt Enable */ -#define SDIO_IER_RXDTVALIE ((uint32_t)0x00200000) /*!< Data available in Rx FIFO interrupt Enable */ -#define SDIO_IER_SDIOINTIE ((uint32_t)0x00400000) /*!< SDIO Mode Interrupt Received interrupt Enable */ -#define SDIO_IER_ATAENDIE ((uint32_t)0x00800000) /*!< CE-ATA command completion signal received Interrupt Enable */ - -/***************** Bit definition for SDIO_FIFOCNT register *****************/ -#define SDIO_FIFOCNT_FIFOCNT ((uint32_t)0x00FFFFFF) /*!< Remaining number of words to be written to or read from the FIFO */ - -/****************** Bit definition for SDIO_FIFO register *******************/ -#define SDIO_FIFO_FIFODT ((uint32_t)0xFFFFFFFF) /*!< Receive and transmit FIFO data */ - -/******************************************************************************/ -/* */ -/* Serial Peripheral Interface */ -/* */ -/******************************************************************************/ - -/******************* Bit definition for SPI_CTLR1 register ********************/ -#define SPI_CTLR1_SCKPH ((uint16_t)0x0001) /*!< Clock Phase */ -#define SPI_CTLR1_SCKPL ((uint16_t)0x0002) /*!< Clock Polarity */ -#define SPI_CTLR1_MSTMODE ((uint16_t)0x0004) /*!< Master Selection */ - -#define SPI_CTLR1_PSC ((uint16_t)0x0038) /*!< PSC[2:0] bits (Baud Rate Control) */ -#define SPI_CTLR1_PSC_0 ((uint16_t)0x0008) /*!< Bit 0 */ -#define SPI_CTLR1_PSC_1 ((uint16_t)0x0010) /*!< Bit 1 */ -#define SPI_CTLR1_PSC_2 ((uint16_t)0x0020) /*!< Bit 2 */ - -#define SPI_CTLR1_SPIEN ((uint16_t)0x0040) /*!< SPI Enable */ -#define SPI_CTLR1_LF ((uint16_t)0x0080) /*!< Frame Format */ -#define SPI_CTLR1_SWNSS ((uint16_t)0x0100) /*!< Internal slave select */ -#define SPI_CTLR1_SWNSSEN ((uint16_t)0x0200) /*!< Software slave management */ -#define SPI_CTLR1_RO ((uint16_t)0x0400) /*!< Receive only */ -#define SPI_CTLR1_FF16 ((uint16_t)0x0800) /*!< Data Frame Format */ -#define SPI_CTLR1_CRCNT ((uint16_t)0x1000) /*!< Transmit CRC next */ -#define SPI_CTLR1_CRCEN ((uint16_t)0x2000) /*!< Hardware CRC calculation enable */ -#define SPI_CTLR1_BDOE ((uint16_t)0x4000) /*!< Output enable in bidirectional mode */ -#define SPI_CTLR1_BDM ((uint16_t)0x8000) /*!< Bidirectional data mode enable */ - -/******************* Bit definition for SPI_CTLR2 register ********************/ -#define SPI_CTLR2_DMARE ((uint8_t)0x01) /*!< Rx Buffer DMA Enable */ -#define SPI_CTLR2_DMATE ((uint8_t)0x02) /*!< Tx Buffer DMA Enable */ -#define SPI_CTLR2_NSSDRV ((uint8_t)0x04) /*!< SS Output Enable */ -#define SPI_CTLR2_ERRIE ((uint8_t)0x20) /*!< Error Interrupt Enable */ -#define SPI_CTLR2_RBNEIE ((uint8_t)0x40) /*!< RX buffer Not Empty Interrupt Enable */ -#define SPI_CTLR2_TBEIE ((uint8_t)0x80) /*!< Tx buffer Empty Interrupt Enable */ - -/******************** Bit definition for SPI_STR register ********************/ -#define SPI_STR_RBNE ((uint8_t)0x01) /*!< Receive buffer Not Empty */ -#define SPI_STR_TBE ((uint8_t)0x02) /*!< Transmit buffer Empty */ -#define SPI_STR_I2SCH ((uint8_t)0x04) /*!< Channel side */ -#define SPI_STR_TXURE ((uint8_t)0x08) /*!< Underrun flag */ -#define SPI_STR_CRCE ((uint8_t)0x10) /*!< CRC Error flag */ -#define SPI_STR_CONFE ((uint8_t)0x20) /*!< Mode fault */ -#define SPI_STR_RXORE ((uint8_t)0x40) /*!< Overrun flag */ -#define SPI_STR_TRANS ((uint8_t)0x80) /*!< Busy flag */ - -/******************** Bit definition for SPI_DTR register ********************/ -#define SPI_DTR_DTR ((uint16_t)0xFFFF) /*!< Data Register */ - -/******************* Bit definition for SPI_CRR register ******************/ -#define SPI_CPR_CPR ((uint16_t)0xFFFF) /*!< CRC polynomial register */ - -/****************** Bit definition for SPI_RCR register ******************/ -#define SPI_RCR_RCR ((uint16_t)0xFFFF) /*!< Rx CRC Register */ - -/****************** Bit definition for SPI_TCR register ******************/ -#define SPI_TCR_TCR ((uint16_t)0xFFFF) /*!< Tx CRC Register */ - -/****************** Bit definition for SPI_I2SCTLR register *****************/ -#define SPI_I2SCTLR_CHLEN ((uint16_t)0x0001) /*!< Channel length (number of bits per audio channel) */ - -#define SPI_I2SCTLR_DTLEN ((uint16_t)0x0006) /*!< DTLEN[1:0] bits (Data length to be transferred) */ -#define SPI_I2SCTLR_DTLEN_0 ((uint16_t)0x0002) /*!< Bit 0 */ -#define SPI_I2SCTLR_DTLEN_1 ((uint16_t)0x0004) /*!< Bit 1 */ - -#define SPI_I2SCTLR_CKPL ((uint16_t)0x0008) /*!< steady state clock polarity */ - -#define SPI_I2SCTLR_I2SSTD ((uint16_t)0x0030) /*!< I2SSTD[1:0] bits (I2S standard selection) */ -#define SPI_I2SCTLR_I2SSTD_0 ((uint16_t)0x0010) /*!< Bit 0 */ -#define SPI_I2SCTLR_I2SSTD_1 ((uint16_t)0x0020) /*!< Bit 1 */ - -#define SPI_I2SCTLR_PCMSM ((uint16_t)0x0080) /*!< PCM frame synchronization */ - -#define SPI_I2SCTLR_I2SOM ((uint16_t)0x0300) /*!< I2SOM[1:0] bits (I2S configuration mode) */ -#define SPI_I2SCTLR_I2SOM_0 ((uint16_t)0x0100) /*!< Bit 0 */ -#define SPI_I2SCTLR_I2SOM_1 ((uint16_t)0x0200) /*!< Bit 1 */ - -#define SPI_I2SCTLR_I2SEN ((uint16_t)0x0400) /*!< I2S Enable */ -#define SPI_I2SCTLR_I2SSEL ((uint16_t)0x0800) /*!< I2S mode selection */ - -/****************** Bit definition for SPI_I2SCKP register *******************/ -#define SPI_I2SCKP_DIV ((uint16_t)0x00FF) /*!< I2S Linear prescaler */ -#define SPI_I2SCKP_OF ((uint16_t)0x0100) /*!< Odd factor for the prescaler */ -#define SPI_I2SCKP_MCKOE ((uint16_t)0x0200) /*!< Master Clock Output Enable */ - - - -/******************************************************************************/ -/* */ -/* Timers (TIMER) */ -/* */ -/******************************************************************************/ - -/******************* Bit definition for TIMER_CTLR1 register ********************/ -#define TIMER_CTLR1_CNTE ((uint16_t)0x0001) /*!<Counter enable */ -#define TIMER_CTLR1_UPDIS ((uint16_t)0x0002) /*!<Update disable */ -#define TIMER_CTLR1_UPS ((uint16_t)0x0004) /*!<Update request source */ -#define TIMER_CTLR1_SPM ((uint16_t)0x0008) /*!<One pulse mode */ -#define TIMER_CTLR1_DIR ((uint16_t)0x0010) /*!<Direction */ - -#define TIMER_CTLR1_CAM ((uint16_t)0x0060) /*!<CAM[1:0] bits (Center-aligned mode selection) */ -#define TIMER_CTLR1_CAM_0 ((uint16_t)0x0020) /*!<Bit 0 */ -#define TIMER_CTLR1_CAM_1 ((uint16_t)0x0040) /*!<Bit 1 */ - -#define TIMER_CTLR1_ARSE ((uint16_t)0x0080) /*!<Auto-reload preload enable */ - -#define TIMER_CTLR1_CDIV ((uint16_t)0x0300) /*!<CDIV[1:0] bits (clock division) */ -#define TIMER_CTLR1_CDIV_0 ((uint16_t)0x0100) /*!<Bit 0 */ -#define TIMER_CTLR1_CDIV_1 ((uint16_t)0x0200) /*!<Bit 1 */ - -/******************* Bit definition for TIMER_CTLR2 register ********************/ -#define TIMER_CTLR2_CCSE ((uint16_t)0x0001) /*!<Capture/Compare Preloaded Control */ -#define TIMER_CTLR2_CCUC ((uint16_t)0x0004) /*!<Capture/Compare Control Update Selection */ -#define TIMER_CTLR2_DMAS ((uint16_t)0x0008) /*!<Capture/Compare DMA Selection */ - -#define TIMER_CTLR2_MMC ((uint16_t)0x0070) /*!<MMC[2:0] bits (Master Mode Selection) */ -#define TIMER_CTLR2_MMC_0 ((uint16_t)0x0010) /*!<Bit 0 */ -#define TIMER_CTLR2_MMC_1 ((uint16_t)0x0020) /*!<Bit 1 */ -#define TIMER_CTLR2_MMC_2 ((uint16_t)0x0040) /*!<Bit 2 */ - -#define TIMER_CTLR2_TI1S ((uint16_t)0x0080) /*!<TI1 Selection */ -#define TIMER_CTLR2_ISO1 ((uint16_t)0x0100) /*!<Output Idle state 1 (OC1 output) */ -#define TIMER_CTLR2_ISO1N ((uint16_t)0x0200) /*!<Output Idle state 1 (OC1N output) */ -#define TIMER_CTLR2_ISO2 ((uint16_t)0x0400) /*!<Output Idle state 2 (OC2 output) */ -#define TIMER_CTLR2_ISO2N ((uint16_t)0x0800) /*!<Output Idle state 2 (OC2N output) */ -#define TIMER_CTLR2_ISO3 ((uint16_t)0x1000) /*!<Output Idle state 3 (OC3 output) */ -#define TIMER_CTLR2_ISO3N ((uint16_t)0x2000) /*!<Output Idle state 3 (OC3N output) */ -#define TIMER_CTLR2_ISO4 ((uint16_t)0x4000) /*!<Output Idle state 4 (OC4 output) */ - -/******************* Bit definition for TIMER_SMC register *******************/ -#define TIMER_SMC_SMC ((uint16_t)0x0007) /*!<SMC[2:0] bits (Slave mode selection) */ -#define TIMER_SMC_SMC_0 ((uint16_t)0x0001) /*!<Bit 0 */ -#define TIMER_SMC_SMC_1 ((uint16_t)0x0002) /*!<Bit 1 */ -#define TIMER_SMC_SMC_2 ((uint16_t)0x0004) /*!<Bit 2 */ - -#define TIMER_SMC_TRGS ((uint16_t)0x0070) /*!<TRGS[2:0] bits (Trigger selection) */ -#define TIMER_SMC_TRGS_0 ((uint16_t)0x0010) /*!<Bit 0 */ -#define TIMER_SMC_TRGS_1 ((uint16_t)0x0020) /*!<Bit 1 */ -#define TIMER_SMC_TRGS_2 ((uint16_t)0x0040) /*!<Bit 2 */ - -#define TIMER_SMC_MSM ((uint16_t)0x0080) /*!<Master/slave mode */ - -#define TIMER_SMC_ETFC ((uint16_t)0x0F00) /*!<ETFC[3:0] bits (External trigger filter) */ -#define TIMER_SMC_ETFC_0 ((uint16_t)0x0100) /*!<Bit 0 */ -#define TIMER_SMC_ETFC_1 ((uint16_t)0x0200) /*!<Bit 1 */ -#define TIMER_SMC_ETFC_2 ((uint16_t)0x0400) /*!<Bit 2 */ -#define TIMER_SMC_ETFC_3 ((uint16_t)0x0800) /*!<Bit 3 */ - -#define TIMER_SMC_ETPSC ((uint16_t)0x3000) /*!<ETPSC[1:0] bits (External trigger prescaler) */ -#define TIMER_SMC_ETPSC_0 ((uint16_t)0x1000) /*!<Bit 0 */ -#define TIMER_SMC_ETPSC_1 ((uint16_t)0x2000) /*!<Bit 1 */ - -#define TIMER_SMC_ECM2E ((uint16_t)0x4000) /*!<External clock enable */ -#define TIMER_SMC_ETPL ((uint16_t)0x8000) /*!<External trigger polarity */ - -/******************* Bit definition for TIMER_DIE register *******************/ -#define TIMER_DIE_UPIE ((uint16_t)0x0001) /*!<Update interrupt enable */ -#define TIMER_DIE_CH1IE ((uint16_t)0x0002) /*!<Capture/Compare 1 interrupt enable */ -#define TIMER_DIE_CH2IE ((uint16_t)0x0004) /*!<Capture/Compare 2 interrupt enable */ -#define TIMER_DIE_CH3IE ((uint16_t)0x0008) /*!<Capture/Compare 3 interrupt enable */ -#define TIMER_DIE_CH4IE ((uint16_t)0x0010) /*!<Capture/Compare 4 interrupt enable */ -#define TIMER_DIE_CCUIE ((uint16_t)0x0020) /*!<COM interrupt enable */ -#define TIMER_DIE_TRGIE ((uint16_t)0x0040) /*!<Trigger interrupt enable */ -#define TIMER_DIE_BKIE ((uint16_t)0x0080) /*!<Break interrupt enable */ -#define TIMER_DIE_UPDE ((uint16_t)0x0100) /*!<Update DMA request enable */ -#define TIMER_DIE_CH1DE ((uint16_t)0x0200) /*!<Capture/Compare 1 DMA request enable */ -#define TIMER_DIE_CH2DE ((uint16_t)0x0400) /*!<Capture/Compare 2 DMA request enable */ -#define TIMER_DIE_CH3DE ((uint16_t)0x0800) /*!<Capture/Compare 3 DMA request enable */ -#define TIMER_DIE_CH4DE ((uint16_t)0x1000) /*!<Capture/Compare 4 DMA request enable */ -#define TIMER_DIE_CCUDE ((uint16_t)0x2000) /*!<COM DMA request enable */ -#define TIMER_DIE_TRGDE ((uint16_t)0x4000) /*!<Trigger DMA request enable */ - -/******************** Bit definition for TIMER_STR register ********************/ -#define TIMER_STR_UPIF ((uint16_t)0x0001) /*!<Update interrupt Flag */ -#define TIMER_STR_CH1IF ((uint16_t)0x0002) /*!<Capture/Compare 1 interrupt Flag */ -#define TIMER_STR_CH2IF ((uint16_t)0x0004) /*!<Capture/Compare 2 interrupt Flag */ -#define TIMER_STR_CH3IF ((uint16_t)0x0008) /*!<Capture/Compare 3 interrupt Flag */ -#define TIMER_STR_CH4IF ((uint16_t)0x0010) /*!<Capture/Compare 4 interrupt Flag */ -#define TIMER_STR_CCUIF ((uint16_t)0x0020) /*!<COM interrupt Flag */ -#define TIMER_STR_TRGIF ((uint16_t)0x0040) /*!<Trigger interrupt Flag */ -#define TIMER_STR_BKIF ((uint16_t)0x0080) /*!<Break interrupt Flag */ -#define TIMER_STR_CH1OF ((uint16_t)0x0200) /*!<Capture/Compare 1 Overcapture Flag */ -#define TIMER_STR_CH2OF ((uint16_t)0x0400) /*!<Capture/Compare 2 Overcapture Flag */ -#define TIMER_STR_CH3OF ((uint16_t)0x0800) /*!<Capture/Compare 3 Overcapture Flag */ -#define TIMER_STR_CH4OF ((uint16_t)0x1000) /*!<Capture/Compare 4 Overcapture Flag */ - -/******************* Bit definition for TIMER_EVG register ********************/ -#define TIMER_EVG_UPG ((uint8_t)0x01) /*!<Update Generation */ -#define TIMER_EVG_CH1G ((uint8_t)0x02) /*!<Capture/Compare 1 Generation */ -#define TIMER_EVG_CH2G ((uint8_t)0x04) /*!<Capture/Compare 2 Generation */ -#define TIMER_EVG_CH3G ((uint8_t)0x08) /*!<Capture/Compare 3 Generation */ -#define TIMER_EVG_CH4G ((uint8_t)0x10) /*!<Capture/Compare 4 Generation */ -#define TIMER_EVG_CCUG ((uint8_t)0x20) /*!<Capture/Compare Control Update Generation */ -#define TIMER_EVG_TRGG ((uint8_t)0x40) /*!<Trigger Generation */ -#define TIMER_EVG_BKG ((uint8_t)0x80) /*!<Break Generation */ - -/****************** Bit definition for TIMER_CHCTLR1 register *******************/ -#define TIMER_CHCTLR1_CH1M ((uint16_t)0x0003) /*!<CH1M[1:0] bits (Capture/Compare 1 Selection) */ -#define TIMER_CHCTLR1_CH1M_0 ((uint16_t)0x0001) /*!<Bit 0 */ -#define TIMER_CHCTLR1_CH1M_1 ((uint16_t)0x0002) /*!<Bit 1 */ - -#define TIMER_CHCTLR1_CH1OFE ((uint16_t)0x0004) /*!<Output Compare 1 Fast enable */ -#define TIMER_CHCTLR1_CH1OSE ((uint16_t)0x0008) /*!<Output Compare 1 Preload enable */ - -#define TIMER_CHCTLR1_CH1OM ((uint16_t)0x0070) /*!<CH1OM[2:0] bits (Output Compare 1 Mode) */ -#define TIMER_CHCTLR1_CH1OM_0 ((uint16_t)0x0010) /*!<Bit 0 */ -#define TIMER_CHCTLR1_CH1OM_1 ((uint16_t)0x0020) /*!<Bit 1 */ -#define TIMER_CHCTLR1_CH1OM_2 ((uint16_t)0x0040) /*!<Bit 2 */ - -#define TIMER_CHCTLR1_CH1OCE ((uint16_t)0x0080) /*!<Output Compare 1Clear Enable */ - -#define TIMER_CHCTLR1_CH2M ((uint16_t)0x0300) /*!<CH2M[1:0] bits (Capture/Compare 2 Selection) */ -#define TIMER_CHCTLR1_CH2M_0 ((uint16_t)0x0100) /*!<Bit 0 */ -#define TIMER_CHCTLR1_CH2M_1 ((uint16_t)0x0200) /*!<Bit 1 */ - -#define TIMER_CHCTLR1_CH2OFE ((uint16_t)0x0400) /*!<Output Compare 2 Fast enable */ -#define TIMER_CHCTLR1_CH2OSE ((uint16_t)0x0800) /*!<Output Compare 2 Preload enable */ - -#define TIMER_CHCTLR1_CH2OM ((uint16_t)0x7000) /*!<CH2OM[2:0] bits (Output Compare 2 Mode) */ -#define TIMER_CHCTLR1_CH2OM_0 ((uint16_t)0x1000) /*!<Bit 0 */ -#define TIMER_CHCTLR1_CH2OM_1 ((uint16_t)0x2000) /*!<Bit 1 */ -#define TIMER_CHCTLR1_CH2OM_2 ((uint16_t)0x4000) /*!<Bit 2 */ - -#define TIMER_CHCTLR1_CH2OCE ((uint16_t)0x8000) /*!<Output Compare 2 Clear Enable */ - -/*----------------------------------------------------------------------------*/ - -#define TIMER_CHCTLR1_CH1ICP ((uint16_t)0x000C) /*!<CH1ICP[1:0] bits (Input Capture 1 Prescaler) */ -#define TIMER_CHCTLR1_CH1ICP_0 ((uint16_t)0x0004) /*!<Bit 0 */ -#define TIMER_CHCTLR1_CH1ICP_1 ((uint16_t)0x0008) /*!<Bit 1 */ - -#define TIMER_CHCTLR1_CH1ICF ((uint16_t)0x00F0) /*!<CH1ICF[3:0] bits (Input Capture 1 Filter) */ -#define TIMER_CHCTLR1_CH1ICF_0 ((uint16_t)0x0010) /*!<Bit 0 */ -#define TIMER_CHCTLR1_CH1ICF_1 ((uint16_t)0x0020) /*!<Bit 1 */ -#define TIMER_CHCTLR1_CH1ICF_2 ((uint16_t)0x0040) /*!<Bit 2 */ -#define TIMER_CHCTLR1_CH1ICF_3 ((uint16_t)0x0080) /*!<Bit 3 */ - -#define TIMER_CHCTLR1_CH2ICP ((uint16_t)0x0C00) /*!<CH2ICP[1:0] bits (Input Capture 2 Prescaler) */ -#define TIMER_CHCTLR1_CH2ICP_0 ((uint16_t)0x0400) /*!<Bit 0 */ -#define TIMER_CHCTLR1_CH2ICP_1 ((uint16_t)0x0800) /*!<Bit 1 */ - -#define TIMER_CHCTLR1_CH2ICF ((uint16_t)0xF000) /*!<CH2ICF[3:0] bits (Input Capture 2 Filter) */ -#define TIMER_CHCTLR1_CH2ICF_0 ((uint16_t)0x1000) /*!<Bit 0 */ -#define TIMER_CHCTLR1_CH2ICF_1 ((uint16_t)0x2000) /*!<Bit 1 */ -#define TIMER_CHCTLR1_CH2ICF_2 ((uint16_t)0x4000) /*!<Bit 2 */ -#define TIMER_CHCTLR1_CH2ICF_3 ((uint16_t)0x8000) /*!<Bit 3 */ - -/****************** Bit definition for TIMER_CHCTLR2 register *******************/ -#define TIMER_CHCTLR2_CH3M ((uint16_t)0x0003) /*!<CH3M[1:0] bits (Capture/Compare 3 Selection) */ -#define TIMER_CHCTLR2_CH3M_0 ((uint16_t)0x0001) /*!<Bit 0 */ -#define TIMER_CHCTLR2_CH3M_1 ((uint16_t)0x0002) /*!<Bit 1 */ - -#define TIMER_CHCTLR2_CH3OFE ((uint16_t)0x0004) /*!<Output Compare 3 Fast enable */ -#define TIMER_CHCTLR2_CH3OSE ((uint16_t)0x0008) /*!<Output Compare 3 Preload enable */ - -#define TIMER_CHCTLR2_CH3OM ((uint16_t)0x0070) /*!<CH3OM[2:0] bits (Output Compare 3 Mode) */ -#define TIMER_CHCTLR2_CH3OM_0 ((uint16_t)0x0010) /*!<Bit 0 */ -#define TIMER_CHCTLR2_CH3OM_1 ((uint16_t)0x0020) /*!<Bit 1 */ -#define TIMER_CHCTLR2_CH3OM_2 ((uint16_t)0x0040) /*!<Bit 2 */ - -#define TIMER_CHCTLR2_CH3OCE ((uint16_t)0x0080) /*!<Output Compare 3 Clear Enable */ - -#define TIMER_CHCTLR2_CH4M ((uint16_t)0x0300) /*!<CH4M[1:0] bits (Capture/Compare 4 Selection) */ -#define TIMER_CHCTLR2_CH4M_0 ((uint16_t)0x0100) /*!<Bit 0 */ -#define TIMER_CHCTLR2_CH4M_1 ((uint16_t)0x0200) /*!<Bit 1 */ - -#define TIMER_CHCTLR2_CH4OFE ((uint16_t)0x0400) /*!<Output Compare 4 Fast enable */ -#define TIMER_CHCTLR2_CH4OSE ((uint16_t)0x0800) /*!<Output Compare 4 Preload enable */ - -#define TIMER_CHCTLR2_CH4OM ((uint16_t)0x7000) /*!<CH4OM[2:0] bits (Output Compare 4 Mode) */ -#define TIMER_CHCTLR2_CH4OM_0 ((uint16_t)0x1000) /*!<Bit 0 */ -#define TIMER_CHCTLR2_CH4OM_1 ((uint16_t)0x2000) /*!<Bit 1 */ -#define TIMER_CHCTLR2_CH4OM_2 ((uint16_t)0x4000) /*!<Bit 2 */ - -#define TIMER_CHCTLR2_CH4OCE ((uint16_t)0x8000) /*!<Output Compare 4 Clear Enable */ - -/*----------------------------------------------------------------------------*/ - -#define TIMER_CHCTLR2_CH3ICP ((uint16_t)0x000C) /*!<CH3ICP[1:0] bits (Input Capture 3 Prescaler) */ -#define TIMER_CHCTLR2_CH3ICP_0 ((uint16_t)0x0004) /*!<Bit 0 */ -#define TIMER_CHCTLR2_CH3ICP_1 ((uint16_t)0x0008) /*!<Bit 1 */ - -#define TIMER_CHCTLR2_CH3ICF ((uint16_t)0x00F0) /*!<CH3ICF[3:0] bits (Input Capture 3 Filter) */ -#define TIMER_CHCTLR2_CH3ICF_0 ((uint16_t)0x0010) /*!<Bit 0 */ -#define TIMER_CHCTLR2_CH3ICF_1 ((uint16_t)0x0020) /*!<Bit 1 */ -#define TIMER_CHCTLR2_CH3ICF_2 ((uint16_t)0x0040) /*!<Bit 2 */ -#define TIMER_CHCTLR2_CH3ICF_3 ((uint16_t)0x0080) /*!<Bit 3 */ - -#define TIMER_CHCTLR2_CH4ICP ((uint16_t)0x0C00) /*!<CH4ICP[1:0] bits (Input Capture 4 Prescaler) */ -#define TIMER_CHCTLR2_CH4ICP_0 ((uint16_t)0x0400) /*!<Bit 0 */ -#define TIMER_CHCTLR2_CH4ICP_1 ((uint16_t)0x0800) /*!<Bit 1 */ - -#define TIMER_CHCTLR2_CH4ICF ((uint16_t)0xF000) /*!<CH4ICF[3:0] bits (Input Capture 4 Filter) */ -#define TIMER_CHCTLR2_CH4ICF_0 ((uint16_t)0x1000) /*!<Bit 0 */ -#define TIMER_CHCTLR2_CH4ICF_1 ((uint16_t)0x2000) /*!<Bit 1 */ -#define TIMER_CHCTLR2_CH4ICF_2 ((uint16_t)0x4000) /*!<Bit 2 */ -#define TIMER_CHCTLR2_CH4ICF_3 ((uint16_t)0x8000) /*!<Bit 3 */ - -/******************* Bit definition for TIMER_CHE register *******************/ -#define TIMER_CHE_CH1E ((uint16_t)0x0001) /*!<Capture/Compare 1 output enable */ -#define TIMER_CHE_CH1P ((uint16_t)0x0002) /*!<Capture/Compare 1 output Polarity */ -#define TIMER_CHE_CH1NE ((uint16_t)0x0004) /*!<Capture/Compare 1 Complementary output enable */ -#define TIMER_CHE_CH1NP ((uint16_t)0x0008) /*!<Capture/Compare 1 Complementary output Polarity */ -#define TIMER_CHE_CH2E ((uint16_t)0x0010) /*!<Capture/Compare 2 output enable */ -#define TIMER_CHE_CH2P ((uint16_t)0x0020) /*!<Capture/Compare 2 output Polarity */ -#define TIMER_CHE_CH2NE ((uint16_t)0x0040) /*!<Capture/Compare 2 Complementary output enable */ -#define TIMER_CHE_CH2NP ((uint16_t)0x0080) /*!<Capture/Compare 2 Complementary output Polarity */ -#define TIMER_CHE_CH3E ((uint16_t)0x0100) /*!<Capture/Compare 3 output enable */ -#define TIMER_CHE_CH3P ((uint16_t)0x0200) /*!<Capture/Compare 3 output Polarity */ -#define TIMER_CHE_CH3NE ((uint16_t)0x0400) /*!<Capture/Compare 3 Complementary output enable */ -#define TIMER_CHE_CH3NP ((uint16_t)0x0800) /*!<Capture/Compare 3 Complementary output Polarity */ -#define TIMER_CHE_CH4E ((uint16_t)0x1000) /*!<Capture/Compare 4 output enable */ -#define TIMER_CHE_CH4P ((uint16_t)0x2000) /*!<Capture/Compare 4 output Polarity */ -#define TIMER_CHE_CH4NP ((uint16_t)0x8000) /*!<Capture/Compare 4 Complementary output Polarity */ - -/******************* Bit definition for TIMER_CNT register ********************/ -#define TIMER_CNT_CNT ((uint16_t)0xFFFF) /*!<Counter Value */ - -/******************* Bit definition for TIMER_PSC register ********************/ -#define TIMER_PSC_PSC ((uint16_t)0xFFFF) /*!<Prescaler Value */ - -/******************* Bit definition for TIMER_CARL register ********************/ -#define TIMER_CARL_CARL ((uint16_t)0xFFFF) /*!<actual auto-reload Value */ - -/******************* Bit definition for TIMER_CREP register ********************/ -#define TIMER_CREP_CREP ((uint8_t)0xFF) /*!<Repetition Counter Value */ - -/******************* Bit definition for TIMER_CHCC1 register *******************/ -#define TIMER_CHCC1_CHCC1 ((uint16_t)0xFFFF) /*!<Capture/Compare 1 Value */ - -/******************* Bit definition for TIMER_CHCC2 register *******************/ -#define TIMER_CHCC2_CHCC2 ((uint16_t)0xFFFF) /*!<Capture/Compare 2 Value */ - -/******************* Bit definition for TIMER_CHCC3 register *******************/ -#define TIMER_CHCC3_CHCC3 ((uint16_t)0xFFFF) /*!<Capture/Compare 3 Value */ - -/******************* Bit definition for TIMER_CHCC4 register *******************/ -#define TIMER_CHCC4_CHCC4 ((uint16_t)0xFFFF) /*!<Capture/Compare 4 Value */ - -/******************* Bit definition for TIMER_BKDT register *******************/ -#define TIMER_BKDT_DT ((uint16_t)0x00FF) /*!<DT[0:7] bits (Dead-TIMERe Generator set-up) */ -#define TIMER_BKDT_DT_0 ((uint16_t)0x0001) /*!<Bit 0 */ -#define TIMER_BKDT_DT_1 ((uint16_t)0x0002) /*!<Bit 1 */ -#define TIMER_BKDT_DT_2 ((uint16_t)0x0004) /*!<Bit 2 */ -#define TIMER_BKDT_DT_3 ((uint16_t)0x0008) /*!<Bit 3 */ -#define TIMER_BKDT_DT_4 ((uint16_t)0x0010) /*!<Bit 4 */ -#define TIMER_BKDT_DT_5 ((uint16_t)0x0020) /*!<Bit 5 */ -#define TIMER_BKDT_DT_6 ((uint16_t)0x0040) /*!<Bit 6 */ -#define TIMER_BKDT_DT_7 ((uint16_t)0x0080) /*!<Bit 7 */ - -#define TIMER_BKDT_LK ((uint16_t)0x0300) /*!<LK[1:0] bits (Lock Configuration) */ -#define TIMER_BKDT_LK_0 ((uint16_t)0x0100) /*!<Bit 0 */ -#define TIMER_BKDT_LK_1 ((uint16_t)0x0200) /*!<Bit 1 */ - -#define TIMER_BKDT_IOS ((uint16_t)0x0400) /*!<Off-State Selection for Idle mode */ -#define TIMER_BKDT_ROS ((uint16_t)0x0800) /*!<Off-State Selection for Run mode */ -#define TIMER_BKDT_BRKE ((uint16_t)0x1000) /*!<Break enable */ -#define TIMER_BKDT_BRKP ((uint16_t)0x2000) /*!<Break Polarity */ -#define TIMER_BKDT_OAE ((uint16_t)0x4000) /*!<Automatic Output enable */ -#define TIMER_BKDT_POE ((uint16_t)0x8000) /*!<Main Output enable */ - -/******************* Bit definition for TIMER_DCTLR register ********************/ -#define TIMER_DCTLR_DBAR ((uint16_t)0x001F) /*!<DBAR[4:0] bits (DMA Base Address) */ -#define TIMER_DCTLR_DBAR_0 ((uint16_t)0x0001) /*!<Bit 0 */ -#define TIMER_DCTLR_DBAR_1 ((uint16_t)0x0002) /*!<Bit 1 */ -#define TIMER_DCTLR_DBAR_2 ((uint16_t)0x0004) /*!<Bit 2 */ -#define TIMER_DCTLR_DBAR_3 ((uint16_t)0x0008) /*!<Bit 3 */ -#define TIMER_DCTLR_DBAR_4 ((uint16_t)0x0010) /*!<Bit 4 */ - -#define TIMER_DCTLR_DBLTH ((uint16_t)0x1F00) /*!<DBLTH[4:0] bits (DMA Burst Length) */ -#define TIMER_DCTLR_DBLTH_0 ((uint16_t)0x0100) /*!<Bit 0 */ -#define TIMER_DCTLR_DBLTH_1 ((uint16_t)0x0200) /*!<Bit 1 */ -#define TIMER_DCTLR_DBLTH_2 ((uint16_t)0x0400) /*!<Bit 2 */ -#define TIMER_DCTLR_DBLTH_3 ((uint16_t)0x0800) /*!<Bit 3 */ -#define TIMER_DCTLR_DBLTH_4 ((uint16_t)0x1000) /*!<Bit 4 */ - -/******************* Bit definition for TIMER_DTRSF register *******************/ -#define TIMER_DTRSF_DTRSF ((uint16_t)0xFFFF) /*!<DMA register for burst accesses */ - -/******************************************************************************/ -/* */ -/* Universal Synchronous Asynchronous Receiver Transmitter (USART) */ -/* */ -/******************************************************************************/ - -/******************* Bit definition for USART_STR register *******************/ -#define USART_STR_PE ((uint16_t)0x0001) /*!< Parity Error */ -#define USART_STR_FE ((uint16_t)0x0002) /*!< Framing Error */ -#define USART_STR_NE ((uint16_t)0x0004) /*!< Noise Error Flag */ -#define USART_STR_ORE ((uint16_t)0x0008) /*!< OverRun Error */ -#define USART_STR_IDLEF ((uint16_t)0x0010) /*!< IDLE Line Detected Flag*/ -#define USART_STR_RBNE ((uint16_t)0x0020) /*!< Read Data Buffer Not Empty */ -#define USART_STR_TC ((uint16_t)0x0040) /*!< Transmission Complete */ -#define USART_STR_TBE ((uint16_t)0x0080) /*!< Transmit Data Buffer Empty */ -#define USART_STR_LBDF ((uint16_t)0x0100) /*!< LIN Break Detected Flag */ -#define USART_STR_CTSF ((uint16_t)0x0200) /*!< CTS Flag */ - -/******************* Bit definition for USART_DR register *******************/ -#define USART_DR_DR ((uint16_t)0x01FF) /*!< Data value */ - -/******************* Bit definition for USART_BRR register *******************/ -#define USART_BRR_BRRF ((uint16_t)0x000F) /*!< Fraction of USARTDIV */ -#define USART_BRR_BRRM ((uint16_t)0xFFF0) /*!< Mantissa of USARTDIV */ - -/******************* Bit definition for USART_CTLR1 register *******************/ -#define USART_CTLR1_SBKCMD ((uint16_t)0x0001) /*!< Send Break Command */ -#define USART_CTLR1_RWU ((uint16_t)0x0002) /*!< Receiver Wakeup */ -#define USART_CTLR1_REN ((uint16_t)0x0004) /*!< Receiver Enable */ -#define USART_CTLR1_TEN ((uint16_t)0x0008) /*!< Transmitter Enable */ -#define USART_CTLR1_IDIE ((uint16_t)0x0010) /*!< IDLE Interrupt Enable */ -#define USART_CTLR1_RBNEIE ((uint16_t)0x0020) /*!< RBNE Interrupt Enable */ -#define USART_CTLR1_TCIE ((uint16_t)0x0040) /*!< Transmission Complete Interrupt Enable */ -#define USART_CTLR1_TBEIE ((uint16_t)0x0080) /*!< TBE Interrupt Enable */ -#define USART_CTLR1_PEIE ((uint16_t)0x0100) /*!< PE Interrupt Enable */ -#define USART_CTLR1_PM ((uint16_t)0x0200) /*!< Parity Selection */ -#define USART_CTLR1_PCEN ((uint16_t)0x0400) /*!< Parity Control Enable */ -#define USART_CTLR1_WM ((uint16_t)0x0800) /*!< Wakeup method */ -#define USART_CTLR1_WL ((uint16_t)0x1000) /*!< Word Length */ -#define USART_CTLR1_UEN ((uint16_t)0x2000) /*!< USART Enable */ -#define USART_CTLR1_OVER8 ((uint16_t)0x8000) /*!< USART Oversmapling 8-bits */?????? - -/****************** Bit definition for USART_CTLR2 register *******************/ -#define USART_CTLR2_ADD ((uint16_t)0x000F) /*!< Address of the USART node */ -#define USART_CTLR2_LBDL ((uint16_t)0x0020) /*!< LIN Break Detection Length */ -#define USART_CTLR2_LBDIE ((uint16_t)0x0040) /*!< LIN Break Detection Interrupt Enable */ -#define USART_CTLR2_LBCP ((uint16_t)0x0100) /*!< Last Bit Clock pulse */ -#define USART_CTLR2_CPH ((uint16_t)0x0200) /*!< Clock Phase */ -#define USART_CTLR2_CPL ((uint16_t)0x0400) /*!< Clock Polarity */ -#define USART_CTLR2_CKEN ((uint16_t)0x0800) /*!< Clock Enable */ - -#define USART_CTLR2_STB ((uint16_t)0x3000) /*!< STOP[1:0] bits (STOP bits) */ -#define USART_CTLR2_STB_0 ((uint16_t)0x1000) /*!< Bit 0 */ -#define USART_CTLR2_STB_1 ((uint16_t)0x2000) /*!< Bit 1 */ - -#define USART_CTLR2_LMEN ((uint16_t)0x4000) /*!< LIN Mode Enable */ - -/****************** Bit definition for USART_CTLR3 register *******************/ -#define USART_CTLR3_ERIE ((uint16_t)0x0001) /*!< Error Interrupt Enable */ -#define USART_CTLR3_IREN ((uint16_t)0x0002) /*!< IrDA Mode Enable */ -#define USART_CTLR3_IRLP ((uint16_t)0x0004) /*!< IrDA Low-Power */ -#define USART_CTLR3_HDEN ((uint16_t)0x0008) /*!< Half-Duplex Enable */ -#define USART_CTLR3_NACK ((uint16_t)0x0010) /*!< Smartcard NACK Enable */ -#define USART_CTLR3_SCEN ((uint16_t)0x0020) /*!< Smartcard Mode Enable */ -#define USART_CTLR3_DENR ((uint16_t)0x0040) /*!< DMA Enable For Receiver */ -#define USART_CTLR3_DENT ((uint16_t)0x0080) /*!< DMA Enable For Transmitter */ -#define USART_CTLR3_RTSEN ((uint16_t)0x0100) /*!< RTS Enable */ -#define USART_CTLR3_CTSEN ((uint16_t)0x0200) /*!< CTS Enable */ -#define USART_CTLR3_CTSIE ((uint16_t)0x0400) /*!< CTS Interrupt Enable */ -#define USART_CTLR3_ONEBIT ((uint16_t)0x0800) /*!< One Bit method */????? - -/****************** Bit definition for USART_GTPR register ******************/ -#define USART_GTPR_PSC ((uint16_t)0x00FF) /*!< PSC[7:0] bits (Prescaler value) */ -#define USART_GTPR_PSC_0 ((uint16_t)0x0001) /*!< Bit 0 */ -#define USART_GTPR_PSC_1 ((uint16_t)0x0002) /*!< Bit 1 */ -#define USART_GTPR_PSC_2 ((uint16_t)0x0004) /*!< Bit 2 */ -#define USART_GTPR_PSC_3 ((uint16_t)0x0008) /*!< Bit 3 */ -#define USART_GTPR_PSC_4 ((uint16_t)0x0010) /*!< Bit 4 */ -#define USART_GTPR_PSC_5 ((uint16_t)0x0020) /*!< Bit 5 */ -#define USART_GTPR_PSC_6 ((uint16_t)0x0040) /*!< Bit 6 */ -#define USART_GTPR_PSC_7 ((uint16_t)0x0080) /*!< Bit 7 */ - -#define USART_GTPR_GT ((uint16_t)0xFF00) /*!< Guard time value */ - -/******************************************************************************/ -/* */ -/* Window WATCHDOG (WWDG) */ -/* */ -/******************************************************************************/ - -/******************* Bit definition for WWDG_CTLR register ********************/ -#define WWDG_CTLR_CNT ((uint8_t)0x7F) /*!< CNT[6:0] bits (7-Bit counter (MSB to LSB)) */ -#define WWDG_CTLR_CNT0 ((uint8_t)0x01) /*!< Bit 0 */ -#define WWDG_CTLR_CNT1 ((uint8_t)0x02) /*!< Bit 1 */ -#define WWDG_CTLR_CNT2 ((uint8_t)0x04) /*!< Bit 2 */ -#define WWDG_CTLR_CNT3 ((uint8_t)0x08) /*!< Bit 3 */ -#define WWDG_CTLR_CNT4 ((uint8_t)0x10) /*!< Bit 4 */ -#define WWDG_CTLR_CNT5 ((uint8_t)0x20) /*!< Bit 5 */ -#define WWDG_CTLR_CNT6 ((uint8_t)0x40) /*!< Bit 6 */ - -#define WWDG_CTLR_WDGEN ((uint8_t)0x80) /*!< Activation bit */ - -/******************* Bit definition for WWDG_CFR register *******************/ -#define WWDG_CFR_WIN ((uint16_t)0x007F) /*!< WIN[6:0] bits (7-bit window value) */ -#define WWDG_CFR_WIN0 ((uint16_t)0x0001) /*!< Bit 0 */ -#define WWDG_CFR_WIN1 ((uint16_t)0x0002) /*!< Bit 1 */ -#define WWDG_CFR_WIN2 ((uint16_t)0x0004) /*!< Bit 2 */ -#define WWDG_CFR_WIN3 ((uint16_t)0x0008) /*!< Bit 3 */ -#define WWDG_CFR_WIN4 ((uint16_t)0x0010) /*!< Bit 4 */ -#define WWDG_CFR_WIN5 ((uint16_t)0x0020) /*!< Bit 5 */ -#define WWDG_CFR_WIN6 ((uint16_t)0x0040) /*!< Bit 6 */ - -#define WWDG_CFR_PS ((uint16_t)0x0180) /*!< PS[1:0] bits (Timer Base) */ -#define WWDG_CFR_PS0 ((uint16_t)0x0080) /*!< Bit 0 */ -#define WWDG_CFR_PS1 ((uint16_t)0x0100) /*!< Bit 1 */ - -#define WWDG_CFR_EWI ((uint16_t)0x0200) /*!< Early Wakeup Interrupt */ - -/******************* Bit definition for WWDG_STR register ********************/ -#define WWDG_STR_EWIF ((uint8_t)0x01) /*!< Early Wakeup Interrupt Flag */ - -/** - * @} - */ - -/** - * @} - */ - -#ifdef USE_STDPERIPH_DRIVER -#include "gd32f10x_conf.h" -#endif - -/** @addtogroup Exported_macro - * @{ - */ - -/** - * @} - */ - -#ifdef __cplusplus -} -#endif - -#endif /* __GD32F10X_H */ - -/** - * @} - */ - -/** - * @} - */ diff --git a/bsp/gd32103c-eval/Libraries/CMSIS/GD/GD32F1xx/Include/gd32f10x_conf.h b/bsp/gd32103c-eval/Libraries/CMSIS/GD/GD32F1xx/Include/gd32f10x_conf.h deleted file mode 100644 index 5e26ebe544..0000000000 --- a/bsp/gd32103c-eval/Libraries/CMSIS/GD/GD32F1xx/Include/gd32f10x_conf.h +++ /dev/null @@ -1,39 +0,0 @@ -/** - ****************************************************************************** - * @brief Configuration file. - ****************************************************************************** - */ - -/* Define to prevent recursive inclusion -------------------------------------*/ -#ifndef __GD32F10X_CONF_H -#define __GD32F10X_CONF_H - -/* Includes ------------------------------------------------------------------*/ -/* Comment the line below to disable peripheral header file inclusion */ -#include "gd32f10x_adc.h" -#include "gd32f10x_bkp.h" -#include "gd32f10x_can.h" -#include "gd32f10x_crc.h" -#include "gd32f10x_dac.h" -#include "gd32f10x_dma.h" -#include "gd32f10x_eth.h" -#include "gd32f10x_exmc.h" -#include "gd32f10x_exti.h" -#include "gd32f10x_fmc.h" -#include "gd32f10x_gpio.h" -#include "gd32f10x_i2c.h" -#include "gd32f10x_iwdg.h" -#include "gd32f10x_mcudbg.h" -#include "gd32f10x_misc.h" -#include "gd32f10x_pwr.h" -#include "gd32f10x_rcc.h" -#include "gd32f10x_rcu.h" -#include "gd32f10x_rtc.h" -#include "gd32f10x_sdio.h" -#include "gd32f10x_spi.h" -#include "gd32f10x_timer.h" -#include "gd32f10x_usart.h" -#include "gd32f10x_wwdg.h" - -#endif /* __GD32F10X_CONF_H */ - diff --git a/bsp/gd32103c-eval/Libraries/CMSIS/GD/GD32F1xx/Include/system_gd32f10x.h b/bsp/gd32103c-eval/Libraries/CMSIS/GD/GD32F1xx/Include/system_gd32f10x.h deleted file mode 100644 index 8d23f9b7ff..0000000000 --- a/bsp/gd32103c-eval/Libraries/CMSIS/GD/GD32F1xx/Include/system_gd32f10x.h +++ /dev/null @@ -1,64 +0,0 @@ -/** - ****************************************************************************** - * @brief CMSIS Cortex-M3 Device Peripheral Access Layer System Header File. - ****************************************************************************** - */ - -/** @addtogroup CMSIS - * @{ - */ - -/** @addtogroup GD32F10x_system - * @{ - */ - -/** - * @brief Define to prevent recursive inclusion - */ -#ifndef __SYSTEM_GD32F10X_H -#define __SYSTEM_GD32F10X_H - -#ifdef __cplusplus -extern "C" { -#endif - -/** @addtogroup GD32F10x_System_Includes - * @{ - */ - -/** - * @} - */ - -/** @addtogroup GD32F10x_System_Exported_types - * @{ - */ -extern uint32_t SystemCoreClock; /*!< System Clock Frequency (Core Clock) */ - -/** - * @} - */ - -/** @addtogroup GD32F10x_System_Exported_Functions - * @{ - */ -extern void SystemInit(void); -extern void SystemCoreClockUpdate(void); -/** - * @} - */ - -#ifdef __cplusplus -} -#endif - -#endif /*__SYSTEM_GD32F10X_H */ - -/** - * @} - */ - -/** - * @} - */ - diff --git a/bsp/gd32103c-eval/Libraries/CMSIS/GD/GD32F1xx/Source/GCC/isr_tab.s b/bsp/gd32103c-eval/Libraries/CMSIS/GD/GD32F1xx/Source/GCC/isr_tab.s deleted file mode 100644 index d7d277fedf..0000000000 --- a/bsp/gd32103c-eval/Libraries/CMSIS/GD/GD32F1xx/Source/GCC/isr_tab.s +++ /dev/null @@ -1,213 +0,0 @@ -/* - * File : isr_tab.s - * This file is part of RT-Thread RTOS - * COPYRIGHT (C) 2021, RT-Thread Development Team - * - * Change Logs: - * Date Author Notes - * 2021-01-02 iysheng first implementation - */ - -.syntax unified -.cpu cortex-m3 -.fpu softvfp -.thumb - -.global g_isr_vectors - .section .isr_vector,"a",%progbits - .type g_isr_vectors, STT_OBJECT - -.weak Reset_Handler -g_isr_vectors: - .word _estack /* Top of Stack */ - .word Reset_Handler /* Reset Handler */ - .word NMI_Handler /* NMI Handler */ - .word HardFault_Handler /* Hard Fault Handler */ - .word MemManage_Handler /* MPU Fault Handler */ - .word BusFault_Handler /* Bus Fault Handler */ - .word UsageFault_Handler /* Usage Fault Handler */ - .word 0 /* Reserved */ - .word 0 /* Reserved */ - .word 0 /* Reserved */ - .word 0 /* Reserved */ - .word SVC_Handler /* SVCall Handler */ - .word DebugMon_Handler /* Debug Monitor Handler */ - .word 0 /* Reserved */ - .word PendSV_Handler /* PendSV Handler */ - .word SysTick_Handler /* SysTick Handler */ - - /* external interrupts handler */ - .word WWDGT_IRQHandler /* 16:Window Watchdog Timer */ - .word LVD_IRQHandler /* 17:LVD through EXTI Line detect */ - .word TAMPER_IRQHandler /* 18:Tamper through EXTI Line detect */ - .word RTC_IRQHandler /* 19:RTC through EXTI Line */ - .word FMC_IRQHandler /* 20:FMC */ - .word RCU_CTC_IRQHandler /* 21:RCU and CTC */ - .word EXTI0_IRQHandler /* 22:EXTI Line 0 */ - .word EXTI1_IRQHandler /* 23:EXTI Line 1 */ - .word EXTI2_IRQHandler /* 24:EXTI Line 2 */ - .word EXTI3_IRQHandler /* 25:EXTI Line 3 */ - .word EXTI4_IRQHandler /* 26:EXTI Line 4 */ - .word DMA0_Channel0_IRQHandler /* 27:DMA0 Channel0 */ - .word DMA0_Channel1_IRQHandler /* 28:DMA0 Channel1 */ - .word DMA0_Channel2_IRQHandler /* 29:DMA0 Channel2 */ - .word DMA0_Channel3_IRQHandler /* 30:DMA0 Channel3 */ - .word DMA0_Channel4_IRQHandler /* 31:DMA0 Channel4 */ - .word DMA0_Channel5_IRQHandler /* 32:DMA0 Channel5 */ - .word DMA0_Channel6_IRQHandler /* 33:DMA0 Channel6 */ - .word ADC0_1_IRQHandler /* 34:ADC0 and ADC1 */ - .word USBD_HP_CAN0_TX_IRQHandler /* 35:USBD HP and CAN0 TX */ - .word USBD_LP_CAN0_RX0_IRQHandler /* 36:USBD LP and CAN0 RX0 */ - .word CAN0_RX1_IRQHandler /* 37:CAN0 RX1 */ - .word CAN0_EWMC_IRQHandler /* 38:CAN0 EWMC */ - .word EXTI5_9_IRQHandler /* 39:EXTI5 to EXTI9 */ - .word TIMER0_BRK_IRQHandler /* 40:TIMER0 Break */ - .word TIMER0_UP_IRQHandler /* 41:TIMER0 Update */ - .word TIMER0_TRG_CMT_IRQHandler /* 42:TIMER0 Trigger and Commutation */ - .word TIMER0_Channel_IRQHandler /* 43:TIMER0 Channel Capture Compare */ - .word TIMER1_IRQHandler /* 44:TIMER1 */ - .word TIMER2_IRQHandler /* 45:TIMER2 */ - .word TIMER3_IRQHandler /* 46:TIMER3 */ - .word I2C0_EV_IRQHandler /* 47:I2C0 Event */ - .word I2C0_ER_IRQHandler /* 48:I2C0 Error */ - .word I2C1_EV_IRQHandler /* 49:I2C1 Event */ - .word I2C1_ER_IRQHandler /* 50:I2C1 Error */ - .word SPI0_IRQHandler /* 51:SPI0 */ - .word SPI1_IRQHandler /* 52:SPI1 */ - .word USART0_IRQHandler /* 53:USART0 */ - .word USART1_IRQHandler /* 54:USART1 */ - .word USART2_IRQHandler /* 55:USART2 */ - .word EXTI10_15_IRQHandler /* 56:EXTI10 to EXTI15 */ - .word RTC_Alarm_IRQHandler /* 57:RTC Alarm */ - .word USBD_WKUP_IRQHandler /* 58:USBD Wakeup */ - .word TIMER7_BRK_IRQHandler /* 59:TIMER7 Break */ - .word TIMER7_UP_IRQHandler /* 60:TIMER7 Update */ - .word TIMER7_TRG_CMT_IRQHandler /* 61:TIMER7 Trigger and Commutation */ - .word TIMER7_Channel_IRQHandler /* 62:TIMER7 Channel Capture Compare */ - .word ADC2_IRQHandler /* 63:ADC2 */ - .word EXMC_IRQHandler /* 64:EXMC */ - .word SDIO_IRQHandler /* 65:SDIO */ - .word TIMER4_IRQHandler /* 66:TIMER4 */ - .word SPI2_IRQHandler /* 67:SPI2 */ - .word UART3_IRQHandler /* 68:UART3 */ - .word UART4_IRQHandler /* 69:UART4 */ - .word TIMER5_IRQHandler /* 70:TIMER5 */ - .word TIMER6_IRQHandler /* 71:TIMER6 */ - .word DMA1_Channel0_IRQHandler /* 72:DMA1 Channel0 */ - .word DMA1_Channel1_IRQHandler /* 73:DMA1 Channel1 */ - .word DMA1_Channel2_IRQHandler /* 74:DMA1 Channel2 */ - .word DMA1_Channel3_4_IRQHandler /* 75:DMA1 Channel3 and Channel4 */ - - /* Exception Handlers */ - .weak NMI_Handler - .type NMI_Handler, STT_FUNC -NMI_Handler: - b . - - .weak MemManage_Handler - .type MemManage_Handler, STT_FUNC -MemManage_Handler: - b . - - .weak BusFault_Handler - .type BusFault_Handler, STT_FUNC -BusFault_Handler: - b . - - .weak UsageFault_Handler - .type UsageFault_Handler, STT_FUNC -UsageFault_Handler: - b . - - .weak SVC_Handler - .type SVC_Handler, STT_FUNC -SVC_Handler: - b . - - .weak DebugMon_Handler - .type DebugMon_Handler, STT_FUNC -DebugMon_Handler: - b . - - .weak PendSV_Handler - .type PendSV_Handler, STT_FUNC -PendSV_Handler: - b . - - .weak SysTick_Handler - .type SysTick_Handler, STT_FUNC -SysTick_Handler: - b . - -.global default_irq_handler - .section .text.default_irq_handler,"ax",%progbits - .type default_irq_handler, STT_FUNC -default_irq_handler: - b . - - .macro IRQ handler - .weak \handler - .set \handler, default_irq_handler - .endm - - /* IQR Handler */ - IRQ WWDGT_IRQHandler - IRQ LVD_IRQHandler - IRQ TAMPER_IRQHandler - IRQ RTC_IRQHandler - IRQ FMC_IRQHandler - IRQ RCU_CTC_IRQHandler - IRQ EXTI0_IRQHandler - IRQ EXTI1_IRQHandler - IRQ EXTI2_IRQHandler - IRQ EXTI3_IRQHandler - IRQ EXTI4_IRQHandler - IRQ DMA0_Channel0_IRQHandler - IRQ DMA0_Channel1_IRQHandler - IRQ DMA0_Channel2_IRQHandler - IRQ DMA0_Channel3_IRQHandler - IRQ DMA0_Channel4_IRQHandler - IRQ DMA0_Channel5_IRQHandler - IRQ DMA0_Channel6_IRQHandler - IRQ ADC0_1_IRQHandler - IRQ USBD_HP_CAN0_TX_IRQHandler - IRQ USBD_LP_CAN0_RX0_IRQHandler - IRQ CAN0_RX1_IRQHandler - IRQ CAN0_EWMC_IRQHandler - IRQ EXTI5_9_IRQHandler - IRQ TIMER0_BRK_IRQHandler - IRQ TIMER0_UP_IRQHandler - IRQ TIMER0_TRG_CMT_IRQHandler - IRQ TIMER0_Channel_IRQHandler - IRQ TIMER1_IRQHandler - IRQ TIMER2_IRQHandler - IRQ TIMER3_IRQHandler - IRQ I2C0_EV_IRQHandler - IRQ I2C0_ER_IRQHandler - IRQ I2C1_EV_IRQHandler - IRQ I2C1_ER_IRQHandler - IRQ SPI0_IRQHandler - IRQ SPI1_IRQHandler - IRQ USART0_IRQHandler - IRQ USART1_IRQHandler - IRQ USART2_IRQHandler - IRQ EXTI10_15_IRQHandler - IRQ RTC_Alarm_IRQHandler - IRQ USBD_WKUP_IRQHandler - IRQ TIMER7_BRK_IRQHandler - IRQ TIMER7_UP_IRQHandler - IRQ TIMER7_TRG_CMT_IRQHandler - IRQ TIMER7_Channel_IRQHandler - IRQ ADC2_IRQHandler - IRQ EXMC_IRQHandler - IRQ SDIO_IRQHandler - IRQ TIMER4_IRQHandler - IRQ SPI2_IRQHandler - IRQ UART3_IRQHandler - IRQ UART4_IRQHandler - IRQ TIMER5_IRQHandler - IRQ TIMER6_IRQHandler - IRQ DMA1_Channel0_IRQHandler - IRQ DMA1_Channel1_IRQHandler - IRQ DMA1_Channel2_IRQHandler - IRQ DMA1_Channel3_4_IRQHandler diff --git a/bsp/gd32103c-eval/Libraries/CMSIS/GD/GD32F1xx/Source/GCC/startup_gd32.s b/bsp/gd32103c-eval/Libraries/CMSIS/GD/GD32F1xx/Source/GCC/startup_gd32.s deleted file mode 100644 index 5487da4c60..0000000000 --- a/bsp/gd32103c-eval/Libraries/CMSIS/GD/GD32F1xx/Source/GCC/startup_gd32.s +++ /dev/null @@ -1,48 +0,0 @@ -/* - * File : startup_gd32f10x_hd.s - * This file is part of RT-Thread RTOS - * COPYRIGHT (C) 2006 - 2021, RT-Thread Development Team - * - * Change Logs: - * Date Author Notes - * 2021-01-02 iysheng first implementation - */ - -.syntax unified -.cpu cortex-m3 -.fpu softvfp -.thumb - -.global Reset_Handler - .section .text.Reset_Handler - .type Reset_Handler, STT_FUNC -Reset_Handler: - ldr r1, =_sidata - ldr r2, =_sdata - ldr r3, =_edata - - subs r3, r2 - ble fill_bss_start - -loop_copy_data: - subs r3, #4 - ldr r0, [r1,r3] - str r0, [r2,r3] - bgt loop_copy_data - -fill_bss_start: - ldr r1, =__bss_start - ldr r2, =__bss_end - movs r0, 0 - subs r2, r1 - ble startup_enter - -loop_fill_bss: - subs r2, #4 - str r0, [r1, r2] - bgt loop_fill_bss - -startup_enter: - bl SystemInit - bl entry - diff --git a/bsp/gd32103c-eval/Libraries/CMSIS/GD/GD32F1xx/Source/system_gd32f1xx.c b/bsp/gd32103c-eval/Libraries/CMSIS/GD/GD32F1xx/Source/system_gd32f1xx.c deleted file mode 100644 index 02a1bd93d0..0000000000 --- a/bsp/gd32103c-eval/Libraries/CMSIS/GD/GD32F1xx/Source/system_gd32f1xx.c +++ /dev/null @@ -1,1131 +0,0 @@ -/** - ****************************************************************************** - * @brief CMSIS Cortex-M3 Device Peripheral Access Layer System Source File. - ****************************************************************************** - */ - -/** @addtogroup CMSIS - * @{ - */ - -/** @addtogroup GD32f10x_system - * @{ - */ - -/** @addtogroup GD32f10x_System_Private_Includes - * @{ - */ - -#include "gd32f10x.h" - -/** - * @} - */ - -/** @addtogroup GD32f10x_System_Private_Variables - * @{ - */ - -/* Uncomment the corresponding line to configure system clock that you need */ -/* The clock is from HSE oscillator clock */ -//#define SYSCLK_FREQ_HSE HSE_VALUE -//#define SYSCLK_FREQ_24MHz 24000000 -//#define SYSCLK_FREQ_36MHz 36000000 -//#define SYSCLK_FREQ_48MHz 48000000 -//#define SYSCLK_FREQ_56MHz 56000000 -//#define SYSCLK_FREQ_72MHz 72000000 -//#define SYSCLK_FREQ_96MHz 96000000 -#define SYSCLK_FREQ_108MHz 108000000 - -/* Uncomment the corresponding line to configure system clock that you need */ -/* The clock is from HSI oscillator clock */ -//#define SYSCLK_FREQ_48MHz_HSI 48000000 -//#define SYSCLK_FREQ_72MHz_HSI 72000000 -//#define SYSCLK_FREQ_108MHz_HSI 108000000 - -/* ---------------------- RCC registers mask -------------------------------- */ - -/* RCC GCCR_HSIEN mask */ -#define SYS_GCCR_HSIEN_SET ((uint32_t)0x00000001) - -/* RCC GCFGR_Reset mask */ -#define SYS_GCFGR_RESET_CL ((uint32_t)0xE0FF0000) -#define SYS_GCFGR_RESET ((uint32_t)0xE8FF0000) - -/* RCC GCCR_HSEEN_CKMEN_PLLEN masks */ -#define SYS_GCCR_HSEEN_CKMEN_PLLEN_RESET ((uint32_t)0xFEF6FFFF) - -/* RCC GCCR_HSEBPS mask */ -#define SYS_GCCR_HSEBPS_RESET ((uint32_t)0xFFFBFFFF) - -/* RCC GCFGR_PLLSEL_PLLPREDV_PLLMF masks */ -#define SYS_GCFGR_PLLSEL_PLLPREDV_PLLMF_USBPS_RESET ((uint32_t)0xF700FFFF) -#define SYS_GCFGR_PLLSEL_PLLPREDV_PLLMF_USBPS_RESET_CL ((uint32_t)0xDF00FFFF) - -/* RCC GCCR_PLL2EN_PLL3EN masks */ -#define SYS_GCCR_PLL2EN_PLL3EN_RESET ((uint32_t)0xEBFFFFFF) - -/* RCC GCFGR2 reset */ -#define SYS_GCFGR2_RESET ((uint32_t)0x00000000) - -/* RCC GCIR_INT ans FLAG masks */ -#define SYS_GCIR_INT_FLAG_RESET ((uint32_t)0x009F0000) -#define SYS_GCIR_INT_FLAG_RESET_CL ((uint32_t)0x00FF0000) - -#define SYS_GCCR_HSEEN_HSEBPS_RESET ((uint32_t)0xFFF8FFFF) - -/* RCC GCCR_HSIADJ masks */ -#define SYS_GCCR_HSIADJ_OFFSET ((uint32_t)0x00000003) - - -#define SYS_RCC_GCFGR_PLLMF_3_0 ((uint32_t)0x003C0000) /*!< PLLMF[3:0] Bits */ - -/* RCC HSI clock divided by 2 masks */ -#define SYS_HSI_CLOCK_DIVIDED_2 ((uint32_t)0x00000001) - - - -/** - * @} - */ - - -/** @addtogroup GD32F10x_System_Private_Variables - * @{ - */ - -/******************************************************************************* -* System Clock Select -*******************************************************************************/ -#ifdef SYSCLK_FREQ_HSE - uint32_t SystemCoreClock = SYSCLK_FREQ_HSE; -#elif defined SYSCLK_FREQ_24MHz - uint32_t SystemCoreClock = SYSCLK_FREQ_24MHz; -#elif defined SYSCLK_FREQ_36MHz - uint32_t SystemCoreClock = SYSCLK_FREQ_36MHz; -#elif defined SYSCLK_FREQ_48MHz - uint32_t SystemCoreClock = SYSCLK_FREQ_48MHz; -#elif defined SYSCLK_FREQ_56MHz - uint32_t SystemCoreClock = SYSCLK_FREQ_56MHz; -#elif defined SYSCLK_FREQ_72MHz - uint32_t SystemCoreClock = SYSCLK_FREQ_72MHz; -#elif defined SYSCLK_FREQ_96MHz - uint32_t SystemCoreClock = SYSCLK_FREQ_96MHz; -#elif defined SYSCLK_FREQ_108MHz - uint32_t SystemCoreClock = SYSCLK_FREQ_108MHz; -#elif defined SYSCLK_FREQ_48MHz_HSI - uint32_t SystemCoreClock = SYSCLK_FREQ_48MHz_HSI; -#elif defined SYSCLK_FREQ_72MHz_HSI - uint32_t SystemCoreClock = SYSCLK_FREQ_72MHz_HSI; -#elif defined SYSCLK_FREQ_108MHz_HSI - uint32_t SystemCoreClock = SYSCLK_FREQ_108MHz_HSI; -#else /*!< HSI Selected as System Clock source */ - uint32_t SystemCoreClock = HSI_VALUE; /*!< System Clock Frequency (Core Clock) */ -#endif - -__I uint8_t AHBPrescTableList[16] = {0, 0, 0, 0, 0, 0, 0, 0, 1, 2, 3, 4, 6, 7, 8, 9}; - -/** - * @} - */ - -/** @addtogroup GD32f10x_System_Private_FunctionPrototypes - * @{ - */ - -static void SetSysClock(void); - -#ifdef SYSCLK_FREQ_HSE - static void SetSysClockToHSE(void); -#elif defined SYSCLK_FREQ_24MHz - static void SetSysClockTo24(void); -#elif defined SYSCLK_FREQ_36MHz - static void SetSysClockTo36(void); -#elif defined SYSCLK_FREQ_48MHz - static void SetSysClockTo48(void); -#elif defined SYSCLK_FREQ_56MHz - static void SetSysClockTo56(void); -#elif defined SYSCLK_FREQ_72MHz - static void SetSysClockTo72(void); -#elif defined SYSCLK_FREQ_96MHz - static void SetSysClockTo96(void); -#elif defined SYSCLK_FREQ_108MHz - static void SetSysClockTo108(void); -#elif defined SYSCLK_FREQ_48MHz_HSI - static void SetSysClockTo48HSI(void); -#elif defined SYSCLK_FREQ_72MHz_HSI - static void SetSysClockTo72HSI(void); -#elif defined SYSCLK_FREQ_108MHz_HSI - static void SetSysClockTo108HSI(void); -#endif - - -/** - * @} - */ - -/** @addtogroup GD32f10x_System_Private_Functions - * @{ - */ - -/** - * @brief Initialize the Embedded Flash Interface, the PLL and set the - * SystemCoreClock variable. - * @param None - * @retval None - */ - -void SystemInit(void) -{ - /* Set RCC GCCR_HSIEN mask */ - RCC->GCCR |= SYS_GCCR_HSIEN_SET; - - /* Reset SCS[1:0], AHBPS[3:0], APB1PS[2:0],APB2PS[2:0], ADCPS[2:0],CKOTUSEL[2:0] bits */ -#ifdef GD32F10X_CL - RCC->GCFGR &= SYS_GCFGR_RESET_CL; -#else - RCC->GCFGR &= SYS_GCFGR_RESET; -#endif /* GD32F10X_CL */ - - /* Reset HSEEN, CKMEN and PLLEN bits */ - RCC->GCCR &= SYS_GCCR_HSEEN_CKMEN_PLLEN_RESET; - - /* Reset HSEBPS bit */ - RCC->GCCR &= SYS_GCCR_HSEBPS_RESET; - - /* Reset PLLSEL, PLLPREDV and PLLMF[4:0] USBPS/OTGPS bits */ -#ifdef GD32F10X_CL - RCC->GCFGR &= SYS_GCFGR_PLLSEL_PLLPREDV_PLLMF_USBPS_RESET_CL; -#else - RCC->GCFGR &= SYS_GCFGR_PLLSEL_PLLPREDV_PLLMF_USBPS_RESET; -#endif /* GD32F10X_CL */ - -#ifdef GD32F10X_CL - /* Reset PLL2EN and PLL3EN bits */ - RCC->GCCR &= SYS_GCCR_PLL2EN_PLL3EN_RESET; - - /* Reset GCFGR2 register */ - RCC->GCFGR2 = SYS_GCFGR2_RESET ; - - /* Disable all interrupts and clear flag bits */ - RCC->GCIR = SYS_GCIR_INT_FLAG_RESET_CL; -#else - /* Disable all interrupts and clear flag bits */ - RCC->GCIR = SYS_GCIR_INT_FLAG_RESET; -#endif /* GD32F10X_CL */ - - /* Configure the System clock frequency, AHB, APB2 and APB1 prescalers */ - /* Configure the Flash Latency cycles and enable prefetch buffer */ - SetSysClock(); -} - -/** - * @brief Update SystemCoreClock according to RCC Register Values - * @note Update the SystemCoreClock variable values, when the core clock (HCLK) changes. - * Otherwise, any configuration based on this variable will be wrong. - * @param None - * @retval None - */ -void SystemCoreClockUpdate(void) -{ - uint32_t temp = 0, pllmf = 0, pllmf4 = 0, pllselect = 0, presc = 0; - -#ifdef GD32F10X_CL - uint32_t prediv1select = 0, prediv1factor = 0, prediv2factor = 0, pll2mf = 0; -#endif /* GD32F10X_CL */ - - /* Get CK_SYS source -------------------------------------------------------*/ - temp = RCC->GCFGR & RCC_GCFGR_SCSS; - - switch (temp) { - case 0x00: /* HSI used as CK_SYS */ - SystemCoreClock = HSI_VALUE; - break; - case 0x04: /* HSE used as CK_SYS */ - SystemCoreClock = HSE_VALUE; - break; - case 0x08: /* PLL used as CK_SYS */ -#ifdef GD32F10X_CL - /* Get PLL clock source and multiplication factor ----------------------*/ - /* Get PLLMF[3:0] */ - pllmf = RCC->GCFGR & SYS_RCC_GCFGR_PLLMF_3_0; - /* Get PLLMF[4] */ - pllmf4 = RCC->GCFGR & RCC_GCFGR_PLLMF_4; - - pllmf4 = ((pllmf4 >> 29) * 15); - - pllmf = (pllmf >> 18) + pllmf4; - if (pllmf != 0x0D) { - pllmf += 2; - } else { - /* PLL multiplication factor = PLL input clock * 6.5 */ - pllmf = 13 / 2; - } - - pllselect = RCC->GCFGR & RCC_GCFGR_PLLSEL; - if (pllselect == 0x00) { - /* HSI clock divided by 2 selected as PLL clock source */ - SystemCoreClock = (HSI_VALUE >> SYS_HSI_CLOCK_DIVIDED_2) * pllmf; - } else { - /* PREDIV1 selected as PLL clock entry */ - - /* Get PREDIV1 clock source and division factor */ - prediv1select = RCC->GCFGR2 & RCC_GCFGR2_PREDV1SEL; - prediv1factor = (RCC->GCFGR2 & RCC_GCFGR2_PREDV1) + 1; - - if (prediv1select == 0) { - /* HSE clock selected as PREDIV1 clock entry */ - SystemCoreClock = (HSE_VALUE / prediv1factor) * pllmf; - } else { - /* PLL2 clock selected as PREDIV1 clock entry */ - /* Get PREDIV2 division factor and PLL2 multiplication factor */ - prediv2factor = ((RCC->GCFGR2 & RCC_GCFGR2_PREDV2) >> 4) + 1; - pll2mf = ((RCC->GCFGR2 & RCC_GCFGR2_PLL2MF) >> 8); - if (pll2mf != 15) { - pll2mf += 2; - } else { - pll2mf += 5; - } - SystemCoreClock = (((HSE_VALUE / prediv2factor) * pll2mf) / prediv1factor) * pllmf; - } - } -#else - /* Get PLL clock source and multiplication factor ----------------------*/ - /* Get PLLMF[3:0] */ - pllmf = RCC->GCFGR & SYS_RCC_GCFGR_PLLMF_3_0; - /* Get PLLMF[4] */ - pllmf4 = RCC->GCFGR & RCC_GCFGR_PLLMF_4; - - pllmf4 = ((pllmf4 >> 27) * 15); - pllmf = (pllmf >> 18) + pllmf4 + 2; - - - pllselect = RCC->GCFGR & RCC_GCFGR_PLLSEL; - if (pllselect == 0x00) { - /* HSI clock divided by 2 selected as PLL clock source */ - SystemCoreClock = (HSI_VALUE >> SYS_HSI_CLOCK_DIVIDED_2) * pllmf; - } else { - if ((RCC->GCFGR & RCC_GCFGR_PLLPREDV) != (uint32_t)RESET) { - /* HSE clock divided by 2 */ - SystemCoreClock = (HSE_VALUE >> 1) * pllmf; - } else { - SystemCoreClock = HSE_VALUE * pllmf; - } - } -#endif - break; - default: /* HSI used as system clock */ - SystemCoreClock = HSI_VALUE; - break; - } - - /* Get AHB prescaler */ - temp = RCC->GCFGR & RCC_GCFGR_AHBPS; - temp = temp >> 4; - presc = AHBPrescTableList[temp]; - /* Get AHB clock frequency */ - SystemCoreClock = SystemCoreClock >> presc; -} - -/** - * @brief Configure the System clock frequency, AHB, APB2 and APB1 prescalers. - * @param None - * @retval None - */ - - -static void SetSysClock(void) -{ -#ifdef SYSCLK_FREQ_HSE - SetSysClockToHSE(); -#elif defined SYSCLK_FREQ_24MHz - SetSysClockTo24(); -#elif defined SYSCLK_FREQ_36MHz - SetSysClockTo36(); -#elif defined SYSCLK_FREQ_48MHz - SetSysClockTo48(); -#elif defined SYSCLK_FREQ_56MHz - SetSysClockTo56(); -#elif defined SYSCLK_FREQ_72MHz - SetSysClockTo72(); -#elif defined SYSCLK_FREQ_96MHz - SetSysClockTo96(); -#elif defined SYSCLK_FREQ_108MHz - SetSysClockTo108(); -#elif defined SYSCLK_FREQ_48MHz_HSI - SetSysClockTo48HSI(); -#elif defined SYSCLK_FREQ_72MHz_HSI - SetSysClockTo72HSI(); -#elif defined SYSCLK_FREQ_108MHz_HSI - SetSysClockTo108HSI(); -#endif - -} - -#ifdef SYSCLK_FREQ_HSE -/** - * @brief Select HSE as System clock source and configure AHB, APB2 - * and APB1 prescalers. - * @param None - * @retval None - */ -static void SetSysClockToHSE(void) -{ - __IO uint32_t StartUpCounter = 0, HSEStatus = 0; - - /* CK_SYS, AHB, APB2 and APB1 configuration ---------------------------*/ - /* Enable HSE */ - RCC->GCCR |= ((uint32_t)RCC_GCCR_HSEEN); - - /* Wait till HSE is ready and if Time out is reached exit */ - do { - HSEStatus = RCC->GCCR & RCC_GCCR_HSESTB; - StartUpCounter++; - } while ((HSEStatus == 0) && (StartUpCounter != HSE_STARTUP_TIMEOUT)); - - if ((RCC->GCCR & RCC_GCCR_HSESTB) != RESET) { - HSEStatus = (uint32_t)0x01; - } else { - HSEStatus = (uint32_t)0x00; - } - - if (HSEStatus == (uint32_t)0x01) { - /* AHB = CK_SYS not divided */ - RCC->GCFGR |= (uint32_t)RCC_GCFGR_AHBPS_DIV1; - - /* APB2 = AHB not divided */ - RCC->GCFGR |= (uint32_t)RCC_GCFGR_APB2PS_DIV1; - - /* APB1 = AHB is divided 2 */ - RCC->GCFGR |= (uint32_t)RCC_GCFGR_APB1PS_DIV2; - - /* Select HSE as system clock source */ - RCC->GCFGR &= (uint32_t)((uint32_t)~(RCC_GCFGR_SCS)); - RCC->GCFGR |= (uint32_t)RCC_GCFGR_SCS_HSE; - - /* Wait till HSE is used as system clock source */ - while ((RCC->GCFGR & (uint32_t)RCC_GCFGR_SCSS) != (uint32_t)0x04) { - } - } else { - } -} -#elif defined SYSCLK_FREQ_24MHz -/** - * @brief Set System clock frequency to 24MHz and configure AHB, APB1, and APB2 prescalers. - * @note This function should be used only after reset. - * @param None - * @retval None - */ -static void SetSysClockTo24(void) -{ - __IO uint32_t StartUpCounter = 0, HSEStatus = 0; - - /* CK_SYS, AHB, APB2 and APB1 configuration ---------------------------*/ - /* Enable HSE */ - RCC->GCCR |= ((uint32_t)RCC_GCCR_HSEEN); - - /* Wait till HSE is ready and if Time out is reached exit */ - do { - HSEStatus = RCC->GCCR & RCC_GCCR_HSESTB; - StartUpCounter++; - } while ((HSEStatus == 0) && (StartUpCounter != HSE_STARTUP_TIMEOUT)); - - if ((RCC->GCCR & RCC_GCCR_HSESTB) != RESET) { - HSEStatus = (uint32_t)0x01; - } else { - HSEStatus = (uint32_t)0x00; - } - - if (HSEStatus == (uint32_t)0x01) { - /* AHB = CK_SYS not divided */ - RCC->GCFGR |= (uint32_t)RCC_GCFGR_AHBPS_DIV1; - - /* APB2 = AHB not divided */ - RCC->GCFGR |= (uint32_t)RCC_GCFGR_APB2PS_DIV1; - - /* APB1 = AHB is divided 2 */ - RCC->GCFGR |= (uint32_t)RCC_GCFGR_APB1PS_DIV2; - -#ifdef GD32F10X_CL - /* Configure PLLs ------------------------------------------------------*/ - - /* PLL configuration: PLLCLK = PREDIV1 * 6 = 24 MHz */ - - RCC->GCFGR &= (uint32_t)~(RCC_GCFGR_PLLPREDV | RCC_GCFGR_PLLSEL | RCC_GCFGR_PLLMF); - RCC->GCFGR |= (uint32_t)(RCC_GCFGR_PLLPREDV_PREDIV1 | RCC_GCFGR_PLLSEL_PREDIV1 | RCC_GCFGR_PLLMF6); - - /* PLL2 configuration: PLL2CLK = (HSE / 5) * 8 = 40 MHz */ - /* PREDIV1 configuration: PREDIV1CLK = PLL2 / 10 = 4 MHz */ - - RCC->GCFGR2 &= (uint32_t)~(RCC_GCFGR2_PREDV2 | RCC_GCFGR2_PLL2MF | - RCC_GCFGR2_PREDV1 | RCC_GCFGR2_PREDV1SEL); - RCC->GCFGR2 |= (uint32_t)(RCC_GCFGR2_PREDV2_DIV5 | RCC_GCFGR2_PLL2MF8 | - RCC_GCFGR2_PREDV1SEL_PLL2 | RCC_GCFGR2_PREDV1_DIV10); - - /* Enable PLL2 */ - RCC->GCCR |= RCC_GCCR_PLL2EN; - /* Wait till PLL2 is ready */ - while ((RCC->GCCR & RCC_GCCR_PLL2STB) == 0) { - } -#else - /* PLL configuration: PLLCLK = (HSE /2)* 6 = 24 MHz */ - RCC->GCFGR &= (uint32_t)((uint32_t)~(RCC_GCFGR_PLLSEL | RCC_GCFGR_PLLPREDV | RCC_GCFGR_PLLMF)); - RCC->GCFGR |= (uint32_t)(RCC_GCFGR_PLLPREDV_HSE_DIV2 | RCC_GCFGR_PLLSEL_HSE | RCC_GCFGR_PLLMF6); - -#endif /* GD32F10X_CL */ - - /* Enable PLL */ - RCC->GCCR |= RCC_GCCR_PLLEN; - - /* Wait till PLL is ready */ - while ((RCC->GCCR & RCC_GCCR_PLLSTB) == 0) { - } - - /* Select PLL as system clock source */ - RCC->GCFGR &= (uint32_t)((uint32_t)~(RCC_GCFGR_SCS)); - RCC->GCFGR |= (uint32_t)RCC_GCFGR_SCS_PLL; - - /* Wait till PLL is used as system clock source */ - while ((RCC->GCFGR & (uint32_t)RCC_GCFGR_SCSS) != (uint32_t)0x08) { - } - } else { - } -} - -#elif defined SYSCLK_FREQ_36MHz -/** - * @brief Set System clock frequency to 36MHz and configure AHB, APB1, and APB2 prescalers. - * @note This function should be used only after reset. - * @param None - * @retval None - */ -static void SetSysClockTo36(void) -{ - __IO uint32_t StartUpCounter = 0, HSEStatus = 0; - - /* CK_SYS, AHB, APB2 and APB1 configuration ---------------------------*/ - /* Enable HSE */ - RCC->GCCR |= ((uint32_t)RCC_GCCR_HSEEN); - - /* Wait till HSE is ready and if Time out is reached exit */ - do { - HSEStatus = RCC->GCCR & RCC_GCCR_HSESTB; - StartUpCounter++; - } while ((HSEStatus == 0) && (StartUpCounter != HSE_STARTUP_TIMEOUT)); - - if ((RCC->GCCR & RCC_GCCR_HSESTB) != RESET) { - HSEStatus = (uint32_t)0x01; - } else { - HSEStatus = (uint32_t)0x00; - } - - if (HSEStatus == (uint32_t)0x01) { - /* AHB = CK_SYS not divided */ - RCC->GCFGR |= (uint32_t)RCC_GCFGR_AHBPS_DIV1; - - /* APB2 = AHB not divided */ - RCC->GCFGR |= (uint32_t)RCC_GCFGR_APB2PS_DIV1; - - /* APB1 = AHB is divided 2 */ - RCC->GCFGR |= (uint32_t)RCC_GCFGR_APB1PS_DIV2; - -#ifdef GD32F10X_CL - /* Configure PLLs ------------------------------------------------------*/ - /* PLL configuration: PLLCLK = PREDIV1 * 9 = 36 MHz */ - RCC->GCFGR &= (uint32_t)~(RCC_GCFGR_PLLPREDV | RCC_GCFGR_PLLSEL | RCC_GCFGR_PLLMF); - RCC->GCFGR |= (uint32_t)(RCC_GCFGR_PLLSEL_PREDIV1 | RCC_GCFGR_PLLMF9); - - /* PLL2 configuration: PLL2CLK = (HSE / 5) * 8 = 40 MHz */ - /* PREDIV1 configuration: PREDIV1CLK = PLL2 / 10 = 4 MHz */ - - RCC->GCFGR2 &= (uint32_t)~(RCC_GCFGR2_PREDV2 | RCC_GCFGR2_PLL2MF | - RCC_GCFGR2_PREDV1 | RCC_GCFGR2_PREDV1SEL); - RCC->GCFGR2 |= (uint32_t)(RCC_GCFGR2_PREDV2_DIV5 | RCC_GCFGR2_PLL2MF8 | - RCC_GCFGR2_PREDV1SEL_PLL2 | RCC_GCFGR2_PREDV1_DIV10); - - /* Enable PLL2 */ - RCC->GCCR |= RCC_GCCR_PLL2EN; - /* Wait till PLL2 is ready */ - while ((RCC->GCCR & RCC_GCCR_PLL2STB) == 0) { - } - -#else - /* PLL configuration: PLLCLK = (HSE /2)* 9 = 36 MHz */ - RCC->GCFGR &= (uint32_t)((uint32_t)~(RCC_GCFGR_PLLSEL | RCC_GCFGR_PLLPREDV | RCC_GCFGR_PLLMF)); - RCC->GCFGR |= (uint32_t)(RCC_GCFGR_PLLPREDV_HSE_DIV2 | RCC_GCFGR_PLLSEL_HSE | RCC_GCFGR_PLLMF9); - -#endif /* GD32F10X_CL */ - - /* Enable PLL */ - RCC->GCCR |= RCC_GCCR_PLLEN; - - /* Wait till PLL is ready */ - while ((RCC->GCCR & RCC_GCCR_PLLSTB) == 0) { - } - - /* Select PLL as system clock source */ - RCC->GCFGR &= (uint32_t)((uint32_t)~(RCC_GCFGR_SCS)); - RCC->GCFGR |= (uint32_t)RCC_GCFGR_SCS_PLL; - - /* Wait till PLL is used as system clock source */ - while ((RCC->GCFGR & (uint32_t)RCC_GCFGR_SCSS) != (uint32_t)0x08) { - } - } else { - } -} -#elif defined SYSCLK_FREQ_48MHz -/** - * @brief Set System clock frequency to 48MHz and configure AHB, APB1, and APB2 prescalers. - * @note This function should be used only after reset. - * @param None - * @retval None - */ -static void SetSysClockTo48(void) -{ - __IO uint32_t StartUpCounter = 0, HSEStatus = 0; - - /* CK_SYS, AHB, APB2 and APB1 configuration ---------------------------*/ - /* Enable HSE */ - RCC->GCCR |= ((uint32_t)RCC_GCCR_HSEEN); - - /* Wait till HSE is ready and if Time out is reached exit */ - do { - HSEStatus = RCC->GCCR & RCC_GCCR_HSESTB; - StartUpCounter++; - } while ((HSEStatus == 0) && (StartUpCounter != HSE_STARTUP_TIMEOUT)); - - if ((RCC->GCCR & RCC_GCCR_HSESTB) != RESET) { - HSEStatus = (uint32_t)0x01; - } else { - HSEStatus = (uint32_t)0x00; - } - - if (HSEStatus == (uint32_t)0x01) { - /* AHB = CK_SYS not divided */ - RCC->GCFGR |= (uint32_t)RCC_GCFGR_AHBPS_DIV1; - - /* APB2 = AHB not divided */ - RCC->GCFGR |= (uint32_t)RCC_GCFGR_APB2PS_DIV1; - - /* APB1 = AHB is divided 2 */ - RCC->GCFGR |= (uint32_t)RCC_GCFGR_APB1PS_DIV2; - -#ifdef GD32F10X_CL - /* Configure PLLs ------------------------------------------------------*/ - - /* PLL configuration: PLLCLK = PREDIV1 * 6 = 48 MHz */ - RCC->GCFGR &= (uint32_t)~(RCC_GCFGR_PLLPREDV | RCC_GCFGR_PLLSEL | RCC_GCFGR_PLLMF); - RCC->GCFGR |= (uint32_t)(RCC_GCFGR_PLLSEL_PREDIV1 | RCC_GCFGR_PLLMF6); - /* PLL2 configuration: PLL2CLK = (HSE / 5) * 8 = 40 MHz */ - /* PREDIV1 configuration: PREDIV1CLK = PLL2 / 5 = 8 MHz */ - - RCC->GCFGR2 &= (uint32_t)~(RCC_GCFGR2_PREDV2 | RCC_GCFGR2_PLL2MF | - RCC_GCFGR2_PREDV1 | RCC_GCFGR2_PREDV1SEL); - RCC->GCFGR2 |= (uint32_t)(RCC_GCFGR2_PREDV2_DIV5 | RCC_GCFGR2_PLL2MF8 | - RCC_GCFGR2_PREDV1SEL_PLL2 | RCC_GCFGR2_PREDV1_DIV5); - - - - /* Enable PLL2 */ - RCC->GCCR |= RCC_GCCR_PLL2EN; - /* Wait till PLL2 is ready */ - while ((RCC->GCCR & RCC_GCCR_PLL2STB) == 0) { - } - -#else - /* PLL configuration: PLLCLK = HSE * 6 = 48 MHz */ - RCC->GCFGR &= (uint32_t)((uint32_t)~(RCC_GCFGR_PLLSEL | RCC_GCFGR_PLLPREDV | RCC_GCFGR_PLLMF)); - RCC->GCFGR |= (uint32_t)(RCC_GCFGR_PLLPREDV_HSE | RCC_GCFGR_PLLSEL_HSE | RCC_GCFGR_PLLMF6); - -#endif /* GD32F10X_CL */ - - /* Enable PLL */ - RCC->GCCR |= RCC_GCCR_PLLEN; - - /* Wait till PLL is ready */ - while ((RCC->GCCR & RCC_GCCR_PLLSTB) == 0) { - } - - /* Select PLL as system clock source */ - RCC->GCFGR &= (uint32_t)((uint32_t)~(RCC_GCFGR_SCS)); - RCC->GCFGR |= (uint32_t)RCC_GCFGR_SCS_PLL; - - /* Wait till PLL is used as system clock source */ - while ((RCC->GCFGR & (uint32_t)RCC_GCFGR_SCSS) != (uint32_t)0x08) { - } - } else { - } -} - -#elif defined SYSCLK_FREQ_56MHz -/** - * @brief Set System clock frequency to 56MHz and configure AHB, APB1, and APB2 prescalers. - * @note This function should be used only after reset. - * @param None - * @retval None - */ -static void SetSysClockTo56(void) -{ - __IO uint32_t StartUpCounter = 0, HSEStatus = 0; - - /* CK_SYS, AHB, APB2 and APB1 configuration ---------------------------*/ - /* Enable HSE */ - RCC->GCCR |= ((uint32_t)RCC_GCCR_HSEEN); - - /* Wait till HSE is ready and if Time out is reached exit */ - do { - HSEStatus = RCC->GCCR & RCC_GCCR_HSESTB; - StartUpCounter++; - } while ((HSEStatus == 0) && (StartUpCounter != HSE_STARTUP_TIMEOUT)); - - if ((RCC->GCCR & RCC_GCCR_HSESTB) != RESET) { - HSEStatus = (uint32_t)0x01; - } else { - HSEStatus = (uint32_t)0x00; - } - - if (HSEStatus == (uint32_t)0x01) { - /* AHB = CK_SYS not divided */ - RCC->GCFGR |= (uint32_t)RCC_GCFGR_AHBPS_DIV1; - - /* APB2 = AHB not divided */ - RCC->GCFGR |= (uint32_t)RCC_GCFGR_APB2PS_DIV1; - - /* APB1 = AHB is divided 2 */ - RCC->GCFGR |= (uint32_t)RCC_GCFGR_APB1PS_DIV2; - -#ifdef GD32F10X_CL - /* Configure PLLs ------------------------------------------------------*/ - - /* PLL configuration: PLLCLK = PREDIV1 * 7 = 56 MHz */ - RCC->GCFGR &= (uint32_t)~(RCC_GCFGR_PLLPREDV | RCC_GCFGR_PLLSEL | RCC_GCFGR_PLLMF); - RCC->GCFGR |= (uint32_t)(RCC_GCFGR_PLLSEL_PREDIV1 | RCC_GCFGR_PLLMF7); - /* PLL2 configuration: PLL2CLK = (HSE / 5) * 8 = 40 MHz */ - /* PREDIV1 configuration: PREDIV1CLK = PLL2 / 5 = 8 MHz */ - - RCC->GCFGR2 &= (uint32_t)~(RCC_GCFGR2_PREDV2 | RCC_GCFGR2_PLL2MF | - RCC_GCFGR2_PREDV1 | RCC_GCFGR2_PREDV1SEL); - RCC->GCFGR2 |= (uint32_t)(RCC_GCFGR2_PREDV2_DIV5 | RCC_GCFGR2_PLL2MF8 | - RCC_GCFGR2_PREDV1SEL_PLL2 | RCC_GCFGR2_PREDV1_DIV5); - - /* Enable PLL2 */ - RCC->GCCR |= RCC_GCCR_PLL2EN; - /* Wait till PLL2 is ready */ - while ((RCC->GCCR & RCC_GCCR_PLL2STB) == 0) { - } - -#else - /* PLL configuration: PLLCLK = HSE * 7 = 56 MHz */ - RCC->GCFGR &= (uint32_t)((uint32_t)~(RCC_GCFGR_PLLSEL | RCC_GCFGR_PLLPREDV | RCC_GCFGR_PLLMF)); - RCC->GCFGR |= (uint32_t)(RCC_GCFGR_PLLPREDV_HSE | RCC_GCFGR_PLLSEL_HSE | RCC_GCFGR_PLLMF7); - -#endif /* GD32F10X_CL */ - - /* Enable PLL */ - RCC->GCCR |= RCC_GCCR_PLLEN; - - /* Wait till PLL is ready */ - while ((RCC->GCCR & RCC_GCCR_PLLSTB) == 0) { - } - - /* Select PLL as system clock source */ - RCC->GCFGR &= (uint32_t)((uint32_t)~(RCC_GCFGR_SCS)); - RCC->GCFGR |= (uint32_t)RCC_GCFGR_SCS_PLL; - - /* Wait till PLL is used as system clock source */ - while ((RCC->GCFGR & (uint32_t)RCC_GCFGR_SCSS) != (uint32_t)0x08) { - } - } else { - } -} - -#elif defined SYSCLK_FREQ_72MHz -/** - * @brief Set System clock frequency to 72MHz and configure AHB, APB1, and APB2 prescalers. - * @note This function should be used only after reset. - * @param None - * @retval None - */ -static void SetSysClockTo72(void) -{ - __IO uint32_t StartUpCounter = 0, HSEStatus = 0; - - /* CK_SYS, AHB, APB2 and APB1 configuration ---------------------------*/ - /* Enable HSE */ - RCC->GCCR |= ((uint32_t)RCC_GCCR_HSEEN); - - /* Wait till HSE is ready and if Time out is reached exit */ - do { - HSEStatus = RCC->GCCR & RCC_GCCR_HSESTB; - StartUpCounter++; - } while ((HSEStatus == 0) && (StartUpCounter != HSE_STARTUP_TIMEOUT)); - - if ((RCC->GCCR & RCC_GCCR_HSESTB) != RESET) { - HSEStatus = (uint32_t)0x01; - } else { - HSEStatus = (uint32_t)0x00; - } - - if (HSEStatus == (uint32_t)0x01) { - /* AHB = CK_SYS not divided */ - RCC->GCFGR |= (uint32_t)RCC_GCFGR_AHBPS_DIV1; - - /* APB2 = AHB not divided */ - RCC->GCFGR |= (uint32_t)RCC_GCFGR_APB2PS_DIV1; - - /* APB1 = AHB is divided 2 */ - RCC->GCFGR |= (uint32_t)RCC_GCFGR_APB1PS_DIV2; - -#ifdef GD32F10X_CL - /* Configure PLLs ------------------------------------------------------*/ - - /* PLL configuration: PLLCLK = PREDIV1 * 9 = 72 MHz */ - RCC->GCFGR &= (uint32_t)~(RCC_GCFGR_PLLPREDV | RCC_GCFGR_PLLSEL | RCC_GCFGR_PLLMF); - RCC->GCFGR |= (uint32_t)(RCC_GCFGR_PLLSEL_PREDIV1 | RCC_GCFGR_PLLMF9); - - /* PLL2 configuration: PLL2CLK = (HSE / 5) * 8 = 40 MHz */ - /* PREDIV1 configuration: PREDIV1CLK = PLL2 / 5 = 8 MHz */ - - RCC->GCFGR2 &= (uint32_t)~(RCC_GCFGR2_PREDV2 | RCC_GCFGR2_PLL2MF | - RCC_GCFGR2_PREDV1 | RCC_GCFGR2_PREDV1SEL); - RCC->GCFGR2 |= (uint32_t)(RCC_GCFGR2_PREDV2_DIV5 | RCC_GCFGR2_PLL2MF8 | - RCC_GCFGR2_PREDV1SEL_PLL2 | RCC_GCFGR2_PREDV1_DIV5); - - /* Enable PLL2 */ - RCC->GCCR |= RCC_GCCR_PLL2EN; - /* Wait till PLL2 is ready */ - while ((RCC->GCCR & RCC_GCCR_PLL2STB) == 0) { - } - -#else - /* PLL configuration: PLLCLK = HSE * 9 = 72 MHz */ - RCC->GCFGR &= (uint32_t)((uint32_t)~(RCC_GCFGR_PLLSEL | RCC_GCFGR_PLLPREDV | RCC_GCFGR_PLLMF)); - RCC->GCFGR |= (uint32_t)(RCC_GCFGR_PLLPREDV_HSE | RCC_GCFGR_PLLSEL_HSE | RCC_GCFGR_PLLMF9); - -#endif /* GD32F10X_CL */ - - /* Enable PLL */ - RCC->GCCR |= RCC_GCCR_PLLEN; - - /* Wait till PLL is ready */ - while ((RCC->GCCR & RCC_GCCR_PLLSTB) == 0) { - } - - /* Select PLL as system clock source */ - RCC->GCFGR &= (uint32_t)((uint32_t)~(RCC_GCFGR_SCS)); - RCC->GCFGR |= (uint32_t)RCC_GCFGR_SCS_PLL; - - /* Wait till PLL is used as system clock source */ - while ((RCC->GCFGR & (uint32_t)RCC_GCFGR_SCSS) != (uint32_t)0x08) { - } - } else { - } -} -#elif defined SYSCLK_FREQ_96MHz -/** - * @brief Set System clock frequency to 96MHz and configure AHB, APB1, and APB2 prescalers. - * @note This function should be used only after reset. - * @param None - * @retval None - */ -static void SetSysClockTo96(void) -{ - __IO uint32_t StartUpCounter = 0, HSEStatus = 0; - - /* CK_SYS, AHB, APB2 and APB1 configuration ---------------------------*/ - /* Enable HSE */ - RCC->GCCR |= ((uint32_t)RCC_GCCR_HSEEN); - - /* Wait till HSE is ready and if Time out is reached exit */ - do { - HSEStatus = RCC->GCCR & RCC_GCCR_HSESTB; - StartUpCounter++; - } while ((HSEStatus == 0) && (StartUpCounter != HSE_STARTUP_TIMEOUT)); - - if ((RCC->GCCR & RCC_GCCR_HSESTB) != RESET) { - HSEStatus = (uint32_t)0x01; - } else { - HSEStatus = (uint32_t)0x00; - } - - if (HSEStatus == (uint32_t)0x01) { - /* AHB = CK_SYS not divided */ - RCC->GCFGR |= (uint32_t)RCC_GCFGR_AHBPS_DIV1; - - /* APB2 = AHB not divided */ - RCC->GCFGR |= (uint32_t)RCC_GCFGR_APB2PS_DIV1; - - /* APB1 = AHB is divided 2 */ - RCC->GCFGR |= (uint32_t)RCC_GCFGR_APB1PS_DIV2; - -#ifdef GD32F10X_CL - /* Configure PLLs ------------------------------------------------------*/ - - /* PLL configuration: PLLCLK = PREDIV1 * 12 = 96 MHz */ - RCC->GCFGR &= (uint32_t)~(RCC_GCFGR_PLLPREDV | RCC_GCFGR_PLLSEL | RCC_GCFGR_PLLMF); - RCC->GCFGR |= (uint32_t)(RCC_GCFGR_PLLSEL_PREDIV1 | RCC_GCFGR_PLLMF12); - - /* PLL2 configuration: PLL2CLK = (HSE / 5) * 8 = 40 MHz */ - /* PREDIV1 configuration: PREDIV1CLK = PLL2 / 5 = 8 MHz */ - - RCC->GCFGR2 &= (uint32_t)~(RCC_GCFGR2_PREDV2 | RCC_GCFGR2_PLL2MF | - RCC_GCFGR2_PREDV1 | RCC_GCFGR2_PREDV1SEL); - RCC->GCFGR2 |= (uint32_t)(RCC_GCFGR2_PREDV2_DIV5 | RCC_GCFGR2_PLL2MF8 | - RCC_GCFGR2_PREDV1SEL_PLL2 | RCC_GCFGR2_PREDV1_DIV5); - - /* Enable PLL2 */ - RCC->GCCR |= RCC_GCCR_PLL2EN; - /* Wait till PLL2 is ready */ - while ((RCC->GCCR & RCC_GCCR_PLL2STB) == 0) { - } - -#else - /* PLL configuration: PLLCLK = HSE * 12 = 96 MHz */ - RCC->GCFGR &= (uint32_t)((uint32_t)~(RCC_GCFGR_PLLSEL | RCC_GCFGR_PLLPREDV | RCC_GCFGR_PLLMF)); - RCC->GCFGR |= (uint32_t)(RCC_GCFGR_PLLPREDV_HSE | RCC_GCFGR_PLLSEL_HSE | RCC_GCFGR_PLLMF12); - -#endif /* GD32F10X_CL */ - - /* Enable PLL */ - RCC->GCCR |= RCC_GCCR_PLLEN; - - /* Wait till PLL is ready */ - while ((RCC->GCCR & RCC_GCCR_PLLSTB) == 0) { - } - - /* Select PLL as system clock source */ - RCC->GCFGR &= (uint32_t)((uint32_t)~(RCC_GCFGR_SCS)); - RCC->GCFGR |= (uint32_t)RCC_GCFGR_SCS_PLL; - - /* Wait till PLL is used as system clock source */ - while ((RCC->GCFGR & (uint32_t)RCC_GCFGR_SCSS) != (uint32_t)0x08) { - } - } else { - } -} - -#elif defined SYSCLK_FREQ_108MHz -/** - * @brief Set System clock frequency to 108MHz and configure AHB, APB1, and APB2 prescalers. - * @note This function should be used only after reset. - * @param None - * @retval None - */ -static void SetSysClockTo108(void) -{ - __IO uint32_t StartUpCounter = 0, HSEStatus = 0; - - /* CK_SYS, AHB, APB2 and APB1 configuration ---------------------------*/ - /* Enable HSE */ - RCC->GCCR |= ((uint32_t)RCC_GCCR_HSEEN); - - /* Wait till HSE is ready and if Time out is reached exit */ - do { - HSEStatus = RCC->GCCR & RCC_GCCR_HSESTB; - StartUpCounter++; - } while ((HSEStatus == 0) && (StartUpCounter != HSE_STARTUP_TIMEOUT)); - - if ((RCC->GCCR & RCC_GCCR_HSESTB) != RESET) { - HSEStatus = (uint32_t)0x01; - } else { - HSEStatus = (uint32_t)0x00; - } - - if (HSEStatus == (uint32_t)0x01) { - /* AHB = CK_SYS not divided */ - RCC->GCFGR |= (uint32_t)RCC_GCFGR_AHBPS_DIV1; - /* APB2 = AHB not divided */ - RCC->GCFGR |= (uint32_t)RCC_GCFGR_APB2PS_DIV1; - /* APB1 = AHB is divided 2 */ - RCC->GCFGR |= (uint32_t)RCC_GCFGR_APB1PS_DIV2; - -#ifdef GD32F10X_CL - /* Configure PLLs ------------------------------------------------------*/ - - /* PLL configuration: PLLCLK = PREDIV1 * 9 = 108 MHz */ - RCC->GCFGR &= (uint32_t)~(RCC_GCFGR_PLLPREDV | RCC_GCFGR_PLLSEL | RCC_GCFGR_PLLMF); - RCC->GCFGR |= (uint32_t)(RCC_GCFGR_PLLPREDV_PREDIV1 | RCC_GCFGR_PLLSEL_PREDIV1 | RCC_GCFGR_PLLMF9); - - /* PLL2 configuration: PLL2CLK = (HSE / 5) * 12 = 60 MHz */ - /* PREDIV1 configuration: PREDIV1CLK = PLL2 / 5 = 12 MHz */ - - RCC->GCFGR2 &= (uint32_t)~(RCC_GCFGR2_PREDV2 | RCC_GCFGR2_PLL2MF | - RCC_GCFGR2_PREDV1 | RCC_GCFGR2_PREDV1SEL); - RCC->GCFGR2 |= (uint32_t)(RCC_GCFGR2_PREDV2_DIV5 | RCC_GCFGR2_PLL2MF12 | - RCC_GCFGR2_PREDV1SEL_PLL2 | RCC_GCFGR2_PREDV1_DIV5); - - /* Enable PLL2 */ - RCC->GCCR |= RCC_GCCR_PLL2EN; - /* Wait till PLL2 is ready */ - while ((RCC->GCCR & RCC_GCCR_PLL2STB) == 0) { - } - -#else - /* PLL configuration: PLLCLK = (HSE/2) * 27 = 108 MHz */ - RCC->GCFGR &= (uint32_t)((uint32_t)~(RCC_GCFGR_PLLSEL | RCC_GCFGR_PLLPREDV | RCC_GCFGR_PLLMF)); - RCC->GCFGR |= (uint32_t)(RCC_GCFGR_PLLPREDV_HSE_DIV2 | RCC_GCFGR_PLLSEL_HSE | RCC_GCFGR_PLLMF27); - -#endif /* GD32F10X_CL */ - - /* Enable PLL */ - RCC->GCCR |= RCC_GCCR_PLLEN; - - /* Wait till PLL is ready */ - while ((RCC->GCCR & RCC_GCCR_PLLSTB) == 0) { - } - - /* Select PLL as system clock source */ - RCC->GCFGR &= (uint32_t)((uint32_t)~(RCC_GCFGR_SCS)); - RCC->GCFGR |= (uint32_t)RCC_GCFGR_SCS_PLL; - - /* Wait till PLL is used as system clock source */ - while ((RCC->GCFGR & (uint32_t)RCC_GCFGR_SCSS) != (uint32_t)0x08) { - } - } else { - } -} -#elif defined SYSCLK_FREQ_48MHz_HSI -/** - * @brief Set System clock frequency to 48MHz and configure AHB, APB1, and APB2 prescalers. - * @note This function should be used only after reset. - * @param None - * @retval None - */ -static void SetSysClockTo48HSI(void) -{ - __IO uint32_t StartUpCounter = 0, HSEStatus = 0; - - /* CK_SYS, AHB, APB2 and APB1 configuration ---------------------------*/ - - /* AHB = CK_SYS not divided */ - RCC->GCFGR |= (uint32_t)RCC_GCFGR_AHBPS_DIV1; - - /* APB2 = AHB not divided */ - RCC->GCFGR |= (uint32_t)RCC_GCFGR_APB2PS_DIV1; - - /* APB1 = AHB is divided 2 */ - RCC->GCFGR |= (uint32_t)RCC_GCFGR_APB1PS_DIV2; - - /* Configure PLLs ------------------------------------------------------*/ - - /* PLL configuration: PLLCLK = (HSI/2) * 12 = 48 MHz */ - RCC->GCFGR &= (uint32_t)((uint32_t)~(RCC_GCFGR_PLLSEL | RCC_GCFGR_PLLMF)); - RCC->GCFGR |= (uint32_t)(RCC_GCFGR_PLLSEL_HSI_DIV2 | RCC_GCFGR_PLLMF12); - - /* Enable PLL */ - RCC->GCCR |= RCC_GCCR_PLLEN; - - /* Wait till PLL is ready */ - while ((RCC->GCCR & RCC_GCCR_PLLSTB) == 0) { - } - - /* Select PLL as system clock source */ - RCC->GCFGR &= (uint32_t)((uint32_t)~(RCC_GCFGR_SCS)); - RCC->GCFGR |= (uint32_t)RCC_GCFGR_SCS_PLL; - - /* Wait till PLL is used as system clock source */ - while ((RCC->GCFGR & (uint32_t)RCC_GCFGR_SCSS) != (uint32_t)0x08) { - } -} -#elif defined SYSCLK_FREQ_72MHz_HSI -/** - * @brief Set System clock frequency to 72MHz and configure AHB, APB1, and APB2 prescalers. - * @note This function should be used only after reset. - * @param None - * @retval None - */ -static void SetSysClockTo72HSI(void) -{ - __IO uint32_t StartUpCounter = 0, HSEStatus = 0; - - /* CK_SYS, AHB, APB2 and APB1 configuration ---------------------------*/ - - /* AHB = CK_SYS not divided */ - RCC->GCFGR |= (uint32_t)RCC_GCFGR_AHBPS_DIV1; - - /* APB2 = AHB not divided */ - RCC->GCFGR |= (uint32_t)RCC_GCFGR_APB2PS_DIV1; - - /* APB1 = AHB is divided 2 */ - RCC->GCFGR |= (uint32_t)RCC_GCFGR_APB1PS_DIV2; - - /* Configure PLLs ------------------------------------------------------*/ - - /* PLL configuration: PLLCLK = (HSI/2) * 18 = 72 MHz */ - RCC->GCFGR &= (uint32_t)((uint32_t)~(RCC_GCFGR_PLLSEL | RCC_GCFGR_PLLMF)); - RCC->GCFGR |= (uint32_t)(RCC_GCFGR_PLLSEL_HSI_DIV2 | RCC_GCFGR_PLLMF18); - - /* Enable PLL */ - RCC->GCCR |= RCC_GCCR_PLLEN; - - /* Wait till PLL is ready */ - while ((RCC->GCCR & RCC_GCCR_PLLSTB) == 0) { - } - - /* Select PLL as system clock source */ - RCC->GCFGR &= (uint32_t)((uint32_t)~(RCC_GCFGR_SCS)); - RCC->GCFGR |= (uint32_t)RCC_GCFGR_SCS_PLL; - - /* Wait till PLL is used as system clock source */ - while ((RCC->GCFGR & (uint32_t)RCC_GCFGR_SCSS) != (uint32_t)0x08) { - } -} - -#elif defined SYSCLK_FREQ_108MHz_HSI -/** - * @brief Set System clock frequency to 108MHz and configure AHB, APB1, and APB2 prescalers. - * @note This function should be used only after reset. - * @param None - * @retval None - */ -static void SetSysClockTo108HSI(void) -{ - __IO uint32_t StartUpCounter = 0, HSEStatus = 0; - - /* CK_SYS, AHB, APB2 and APB1 configuration ---------------------------*/ - - /* AHB = CK_SYS not divided */ - RCC->GCFGR |= (uint32_t)RCC_GCFGR_AHBPS_DIV1; - - /* APB2 = AHB not divided */ - RCC->GCFGR |= (uint32_t)RCC_GCFGR_APB2PS_DIV1; - - /* APB1 = AHB is divided 2 */ - RCC->GCFGR |= (uint32_t)RCC_GCFGR_APB1PS_DIV2; - - /* Configure PLLs ------------------------------------------------------*/ - - /* PLL configuration: PLLCLK = (HSI/2) * 27 = 108 MHz */ - RCC->GCFGR &= (uint32_t)((uint32_t)~(RCC_GCFGR_PLLSEL | RCC_GCFGR_PLLPREDV | RCC_GCFGR_PLLMF)); - RCC->GCFGR |= (uint32_t)(RCC_GCFGR_PLLSEL_HSI_DIV2 | RCC_GCFGR_PLLMF27); - - /* Enable PLL */ - RCC->GCCR |= RCC_GCCR_PLLEN; - - /* Wait till PLL is ready */ - while ((RCC->GCCR & RCC_GCCR_PLLSTB) == 0) { - } - - /* Select PLL as system clock source */ - RCC->GCFGR &= (uint32_t)((uint32_t)~(RCC_GCFGR_SCS)); - RCC->GCFGR |= (uint32_t)RCC_GCFGR_SCS_PLL; - - /* Wait till PLL is used as system clock source */ - while ((RCC->GCFGR & (uint32_t)RCC_GCFGR_SCSS) != (uint32_t)0x08) { - } -} -#endif - -/** - * @} - */ - -/** - * @} - */ - -/** - * @} - */ - - diff --git a/bsp/gd32103c-eval/Libraries/CMSIS/core_cm3.c b/bsp/gd32103c-eval/Libraries/CMSIS/core_cm3.c deleted file mode 100644 index f2d043b8d6..0000000000 --- a/bsp/gd32103c-eval/Libraries/CMSIS/core_cm3.c +++ /dev/null @@ -1,784 +0,0 @@ -/**************************************************************************//** - * @file core_cm3.c - * @brief CMSIS Cortex-M3 Core Peripheral Access Layer Source File - * @version V1.30 - * @date 30. October 2009 - * - * @note - * Copyright (C) 2009 ARM Limited. All rights reserved. - * - * @par - * ARM Limited (ARM) is supplying this software for use with Cortex-M - * processor based microcontrollers. This file can be freely distributed - * within development tools that are supporting such ARM based processors. - * - * @par - * THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED - * OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF - * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE. - * ARM SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR - * CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER. - * - ******************************************************************************/ - -#include <stdint.h> - -/* define compiler specific symbols */ -#if defined ( __CC_ARM ) - #define __ASM __asm /*!< asm keyword for ARM Compiler */ - #define __INLINE __inline /*!< inline keyword for ARM Compiler */ - -#elif defined ( __ICCARM__ ) - #define __ASM __asm /*!< asm keyword for IAR Compiler */ - #define __INLINE inline /*!< inline keyword for IAR Compiler. Only avaiable in High optimization mode! */ - -#elif defined ( __GNUC__ ) - #define __ASM __asm /*!< asm keyword for GNU Compiler */ - #define __INLINE inline /*!< inline keyword for GNU Compiler */ - -#elif defined ( __TASKING__ ) - #define __ASM __asm /*!< asm keyword for TASKING Compiler */ - #define __INLINE inline /*!< inline keyword for TASKING Compiler */ - -#endif - - -/* ################### Compiler specific Intrinsics ########################### */ - -#if defined ( __CC_ARM ) /*------------------RealView Compiler -----------------*/ -/* ARM armcc specific functions */ - -/** - * @brief Return the Process Stack Pointer - * - * @return ProcessStackPointer - * - * Return the actual process stack pointer - */ -__ASM uint32_t __get_PSP(void) -{ - mrs r0, psp - bx lr -} - -/** - * @brief Set the Process Stack Pointer - * - * @param topOfProcStack Process Stack Pointer - * - * Assign the value ProcessStackPointer to the MSP - * (process stack pointer) Cortex processor register - */ -__ASM void __set_PSP(uint32_t topOfProcStack) -{ - msr psp, r0 - bx lr -} - -/** - * @brief Return the Main Stack Pointer - * - * @return Main Stack Pointer - * - * Return the current value of the MSP (main stack pointer) - * Cortex processor register - */ -__ASM uint32_t __get_MSP(void) -{ - mrs r0, msp - bx lr -} - -/** - * @brief Set the Main Stack Pointer - * - * @param topOfMainStack Main Stack Pointer - * - * Assign the value mainStackPointer to the MSP - * (main stack pointer) Cortex processor register - */ -__ASM void __set_MSP(uint32_t mainStackPointer) -{ - msr msp, r0 - bx lr -} - -/** - * @brief Reverse byte order in unsigned short value - * - * @param value value to reverse - * @return reversed value - * - * Reverse byte order in unsigned short value - */ -__ASM uint32_t __REV16(uint16_t value) -{ - rev16 r0, r0 - bx lr -} - -/** - * @brief Reverse byte order in signed short value with sign extension to integer - * - * @param value value to reverse - * @return reversed value - * - * Reverse byte order in signed short value with sign extension to integer - */ -__ASM int32_t __REVSH(int16_t value) -{ - revsh r0, r0 - bx lr -} - - -#if (__ARMCC_VERSION < 400000) - -/** - * @brief Remove the exclusive lock created by ldrex - * - * Removes the exclusive lock which is created by ldrex. - */ -__ASM void __CLREX(void) -{ - clrex -} - -/** - * @brief Return the Base Priority value - * - * @return BasePriority - * - * Return the content of the base priority register - */ -__ASM uint32_t __get_BASEPRI(void) -{ - mrs r0, basepri - bx lr -} - -/** - * @brief Set the Base Priority value - * - * @param basePri BasePriority - * - * Set the base priority register - */ -__ASM void __set_BASEPRI(uint32_t basePri) -{ - msr basepri, r0 - bx lr -} - -/** - * @brief Return the Priority Mask value - * - * @return PriMask - * - * Return state of the priority mask bit from the priority mask register - */ -__ASM uint32_t __get_PRIMASK(void) -{ - mrs r0, primask - bx lr -} - -/** - * @brief Set the Priority Mask value - * - * @param priMask PriMask - * - * Set the priority mask bit in the priority mask register - */ -__ASM void __set_PRIMASK(uint32_t priMask) -{ - msr primask, r0 - bx lr -} - -/** - * @brief Return the Fault Mask value - * - * @return FaultMask - * - * Return the content of the fault mask register - */ -__ASM uint32_t __get_FAULTMASK(void) -{ - mrs r0, faultmask - bx lr -} - -/** - * @brief Set the Fault Mask value - * - * @param faultMask faultMask value - * - * Set the fault mask register - */ -__ASM void __set_FAULTMASK(uint32_t faultMask) -{ - msr faultmask, r0 - bx lr -} - -/** - * @brief Return the Control Register value - * - * @return Control value - * - * Return the content of the control register - */ -__ASM uint32_t __get_CONTROL(void) -{ - mrs r0, control - bx lr -} - -/** - * @brief Set the Control Register value - * - * @param control Control value - * - * Set the control register - */ -__ASM void __set_CONTROL(uint32_t control) -{ - msr control, r0 - bx lr -} - -#endif /* __ARMCC_VERSION */ - - - -#elif (defined (__ICCARM__)) /*------------------ ICC Compiler -------------------*/ -/* IAR iccarm specific functions */ -#pragma diag_suppress=Pe940 - -/** - * @brief Return the Process Stack Pointer - * - * @return ProcessStackPointer - * - * Return the actual process stack pointer - */ -uint32_t __get_PSP(void) -{ - __ASM("mrs r0, psp"); - __ASM("bx lr"); -} - -/** - * @brief Set the Process Stack Pointer - * - * @param topOfProcStack Process Stack Pointer - * - * Assign the value ProcessStackPointer to the MSP - * (process stack pointer) Cortex processor register - */ -void __set_PSP(uint32_t topOfProcStack) -{ - __ASM("msr psp, r0"); - __ASM("bx lr"); -} - -/** - * @brief Return the Main Stack Pointer - * - * @return Main Stack Pointer - * - * Return the current value of the MSP (main stack pointer) - * Cortex processor register - */ -uint32_t __get_MSP(void) -{ - __ASM("mrs r0, msp"); - __ASM("bx lr"); -} - -/** - * @brief Set the Main Stack Pointer - * - * @param topOfMainStack Main Stack Pointer - * - * Assign the value mainStackPointer to the MSP - * (main stack pointer) Cortex processor register - */ -void __set_MSP(uint32_t topOfMainStack) -{ - __ASM("msr msp, r0"); - __ASM("bx lr"); -} - -/** - * @brief Reverse byte order in unsigned short value - * - * @param value value to reverse - * @return reversed value - * - * Reverse byte order in unsigned short value - */ -uint32_t __REV16(uint16_t value) -{ - __ASM("rev16 r0, r0"); - __ASM("bx lr"); -} - -/** - * @brief Reverse bit order of value - * - * @param value value to reverse - * @return reversed value - * - * Reverse bit order of value - */ -uint32_t __RBIT(uint32_t value) -{ - __ASM("rbit r0, r0"); - __ASM("bx lr"); -} - -/** - * @brief LDR Exclusive (8 bit) - * - * @param *addr address pointer - * @return value of (*address) - * - * Exclusive LDR command for 8 bit values) - */ -uint8_t __LDREXB(uint8_t *addr) -{ - __ASM("ldrexb r0, [r0]"); - __ASM("bx lr"); -} - -/** - * @brief LDR Exclusive (16 bit) - * - * @param *addr address pointer - * @return value of (*address) - * - * Exclusive LDR command for 16 bit values - */ -uint16_t __LDREXH(uint16_t *addr) -{ - __ASM("ldrexh r0, [r0]"); - __ASM("bx lr"); -} - -/** - * @brief LDR Exclusive (32 bit) - * - * @param *addr address pointer - * @return value of (*address) - * - * Exclusive LDR command for 32 bit values - */ -uint32_t __LDREXW(uint32_t *addr) -{ - __ASM("ldrex r0, [r0]"); - __ASM("bx lr"); -} - -/** - * @brief STR Exclusive (8 bit) - * - * @param value value to store - * @param *addr address pointer - * @return successful / failed - * - * Exclusive STR command for 8 bit values - */ -uint32_t __STREXB(uint8_t value, uint8_t *addr) -{ - __ASM("strexb r0, r0, [r1]"); - __ASM("bx lr"); -} - -/** - * @brief STR Exclusive (16 bit) - * - * @param value value to store - * @param *addr address pointer - * @return successful / failed - * - * Exclusive STR command for 16 bit values - */ -uint32_t __STREXH(uint16_t value, uint16_t *addr) -{ - __ASM("strexh r0, r0, [r1]"); - __ASM("bx lr"); -} - -/** - * @brief STR Exclusive (32 bit) - * - * @param value value to store - * @param *addr address pointer - * @return successful / failed - * - * Exclusive STR command for 32 bit values - */ -uint32_t __STREXW(uint32_t value, uint32_t *addr) -{ - __ASM("strex r0, r0, [r1]"); - __ASM("bx lr"); -} - -#pragma diag_default=Pe940 - - -#elif (defined (__GNUC__)) /*------------------ GNU Compiler ---------------------*/ -/* GNU gcc specific functions */ - -/** - * @brief Return the Process Stack Pointer - * - * @return ProcessStackPointer - * - * Return the actual process stack pointer - */ -uint32_t __get_PSP(void) __attribute__((naked)); -uint32_t __get_PSP(void) -{ - uint32_t result = 0; - - __ASM volatile("MRS %0, psp\n\t" - "MOV r0, %0 \n\t" - "BX lr \n\t" : "=r"(result)); - return (result); -} - -/** - * @brief Set the Process Stack Pointer - * - * @param topOfProcStack Process Stack Pointer - * - * Assign the value ProcessStackPointer to the MSP - * (process stack pointer) Cortex processor register - */ -void __set_PSP(uint32_t topOfProcStack) __attribute__((naked)); -void __set_PSP(uint32_t topOfProcStack) -{ - __ASM volatile("MSR psp, %0\n\t" - "BX lr \n\t" : : "r"(topOfProcStack)); -} - -/** - * @brief Return the Main Stack Pointer - * - * @return Main Stack Pointer - * - * Return the current value of the MSP (main stack pointer) - * Cortex processor register - */ -uint32_t __get_MSP(void) __attribute__((naked)); -uint32_t __get_MSP(void) -{ - uint32_t result = 0; - - __ASM volatile("MRS %0, msp\n\t" - "MOV r0, %0 \n\t" - "BX lr \n\t" : "=r"(result)); - return (result); -} - -/** - * @brief Set the Main Stack Pointer - * - * @param topOfMainStack Main Stack Pointer - * - * Assign the value mainStackPointer to the MSP - * (main stack pointer) Cortex processor register - */ -void __set_MSP(uint32_t topOfMainStack) __attribute__((naked)); -void __set_MSP(uint32_t topOfMainStack) -{ - __ASM volatile("MSR msp, %0\n\t" - "BX lr \n\t" : : "r"(topOfMainStack)); -} - -/** - * @brief Return the Base Priority value - * - * @return BasePriority - * - * Return the content of the base priority register - */ -uint32_t __get_BASEPRI(void) -{ - uint32_t result = 0; - - __ASM volatile("MRS %0, basepri_max" : "=r"(result)); - return (result); -} - -/** - * @brief Set the Base Priority value - * - * @param basePri BasePriority - * - * Set the base priority register - */ -void __set_BASEPRI(uint32_t value) -{ - __ASM volatile("MSR basepri, %0" : : "r"(value)); -} - -/** - * @brief Return the Priority Mask value - * - * @return PriMask - * - * Return state of the priority mask bit from the priority mask register - */ -uint32_t __get_PRIMASK(void) -{ - uint32_t result = 0; - - __ASM volatile("MRS %0, primask" : "=r"(result)); - return (result); -} - -/** - * @brief Set the Priority Mask value - * - * @param priMask PriMask - * - * Set the priority mask bit in the priority mask register - */ -void __set_PRIMASK(uint32_t priMask) -{ - __ASM volatile("MSR primask, %0" : : "r"(priMask)); -} - -/** - * @brief Return the Fault Mask value - * - * @return FaultMask - * - * Return the content of the fault mask register - */ -uint32_t __get_FAULTMASK(void) -{ - uint32_t result = 0; - - __ASM volatile("MRS %0, faultmask" : "=r"(result)); - return (result); -} - -/** - * @brief Set the Fault Mask value - * - * @param faultMask faultMask value - * - * Set the fault mask register - */ -void __set_FAULTMASK(uint32_t faultMask) -{ - __ASM volatile("MSR faultmask, %0" : : "r"(faultMask)); -} - -/** - * @brief Return the Control Register value -* -* @return Control value - * - * Return the content of the control register - */ -uint32_t __get_CONTROL(void) -{ - uint32_t result = 0; - - __ASM volatile("MRS %0, control" : "=r"(result)); - return (result); -} - -/** - * @brief Set the Control Register value - * - * @param control Control value - * - * Set the control register - */ -void __set_CONTROL(uint32_t control) -{ - __ASM volatile("MSR control, %0" : : "r"(control)); -} - - -/** - * @brief Reverse byte order in integer value - * - * @param value value to reverse - * @return reversed value - * - * Reverse byte order in integer value - */ -uint32_t __REV(uint32_t value) -{ - uint32_t result = 0; - - __ASM volatile("rev %0, %1" : "=r"(result) : "r"(value)); - return (result); -} - -/** - * @brief Reverse byte order in unsigned short value - * - * @param value value to reverse - * @return reversed value - * - * Reverse byte order in unsigned short value - */ -uint32_t __REV16(uint16_t value) -{ - uint32_t result = 0; - - __ASM volatile("rev16 %0, %1" : "=r"(result) : "r"(value)); - return (result); -} - -/** - * @brief Reverse byte order in signed short value with sign extension to integer - * - * @param value value to reverse - * @return reversed value - * - * Reverse byte order in signed short value with sign extension to integer - */ -int32_t __REVSH(int16_t value) -{ - uint32_t result = 0; - - __ASM volatile("revsh %0, %1" : "=r"(result) : "r"(value)); - return (result); -} - -/** - * @brief Reverse bit order of value - * - * @param value value to reverse - * @return reversed value - * - * Reverse bit order of value - */ -uint32_t __RBIT(uint32_t value) -{ - uint32_t result = 0; - - __ASM volatile("rbit %0, %1" : "=r"(result) : "r"(value)); - return (result); -} - -/** - * @brief LDR Exclusive (8 bit) - * - * @param *addr address pointer - * @return value of (*address) - * - * Exclusive LDR command for 8 bit value - */ -uint8_t __LDREXB(uint8_t *addr) -{ - uint8_t result = 0; - - __ASM volatile("ldrexb %0, [%1]" : "=r"(result) : "r"(addr)); - return (result); -} - -/** - * @brief LDR Exclusive (16 bit) - * - * @param *addr address pointer - * @return value of (*address) - * - * Exclusive LDR command for 16 bit values - */ -uint16_t __LDREXH(uint16_t *addr) -{ - uint16_t result = 0; - - __ASM volatile("ldrexh %0, [%1]" : "=r"(result) : "r"(addr)); - return (result); -} - -/** - * @brief LDR Exclusive (32 bit) - * - * @param *addr address pointer - * @return value of (*address) - * - * Exclusive LDR command for 32 bit values - */ -uint32_t __LDREXW(uint32_t *addr) -{ - uint32_t result = 0; - - __ASM volatile("ldrex %0, [%1]" : "=r"(result) : "r"(addr)); - return (result); -} - -/** - * @brief STR Exclusive (8 bit) - * - * @param value value to store - * @param *addr address pointer - * @return successful / failed - * - * Exclusive STR command for 8 bit values - */ -uint32_t __STREXB(uint8_t value, uint8_t *addr) -{ - uint32_t result = 0; - - __ASM volatile("strexb %0, %2, [%1]" : "=r"(result) : "r"(addr), "r"(value)); - return (result); -} - -/** - * @brief STR Exclusive (16 bit) - * - * @param value value to store - * @param *addr address pointer - * @return successful / failed - * - * Exclusive STR command for 16 bit values - */ -uint32_t __STREXH(uint16_t value, uint16_t *addr) -{ - uint32_t result = 0; - - __ASM volatile("strexh %0, %2, [%1]" : "=r"(result) : "r"(addr), "r"(value)); - return (result); -} - -/** - * @brief STR Exclusive (32 bit) - * - * @param value value to store - * @param *addr address pointer - * @return successful / failed - * - * Exclusive STR command for 32 bit values - */ -uint32_t __STREXW(uint32_t value, uint32_t *addr) -{ - uint32_t result = 0; - - __ASM volatile("strex %0, %2, [%1]" : "=r"(result) : "r"(addr), "r"(value)); - return (result); -} - - -#elif (defined (__TASKING__)) /*------------------ TASKING Compiler ---------------------*/ -/* TASKING carm specific functions */ - -/* - * The CMSIS functions have been implemented as intrinsics in the compiler. - * Please use "carm -?i" to get an up to date list of all instrinsics, - * Including the CMSIS ones. - */ - -#endif diff --git a/bsp/gd32103c-eval/Libraries/CMSIS/core_cm3.h b/bsp/gd32103c-eval/Libraries/CMSIS/core_cm3.h deleted file mode 100644 index d8ec332d93..0000000000 --- a/bsp/gd32103c-eval/Libraries/CMSIS/core_cm3.h +++ /dev/null @@ -1,1614 +0,0 @@ -/**************************************************************************//** - * @file core_cm3.h - * @brief CMSIS Cortex-M3 Core Peripheral Access Layer Header File - * @version V3.20 - * @date 25. February 2013 - * - * @note - * - ******************************************************************************/ -/* Copyright (c) 2009 - 2013 ARM LIMITED - - All rights reserved. - Redistribution and use in source and binary forms, with or without - modification, are permitted provided that the following conditions are met: - - Redistributions of source code must retain the above copyright - notice, this list of conditions and the following disclaimer. - - Redistributions in binary form must reproduce the above copyright - notice, this list of conditions and the following disclaimer in the - documentation and/or other materials provided with the distribution. - - Neither the name of ARM nor the names of its contributors may be used - to endorse or promote products derived from this software without - specific prior written permission. - * - THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" - AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE - IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE - ARE DISCLAIMED. IN NO EVENT SHALL COPYRIGHT HOLDERS AND CONTRIBUTORS BE - LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR - CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF - SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS - INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN - CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) - ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE - POSSIBILITY OF SUCH DAMAGE. - ---------------------------------------------------------------------------*/ - - -#if defined ( __ICCARM__ ) - #pragma system_include /* treat file as system include file for MISRA check */ -#endif - -#ifdef __cplusplus -extern "C" { -#endif - -#ifndef __CORE_CM3_H_GENERIC -#define __CORE_CM3_H_GENERIC - -/** \page CMSIS_MISRA_Exceptions MISRA-C:2004 Compliance Exceptions - CMSIS violates the following MISRA-C:2004 rules: - - \li Required Rule 8.5, object/function definition in header file.<br> - Function definitions in header files are used to allow 'inlining'. - - \li Required Rule 18.4, declaration of union type or object of union type: '{...}'.<br> - Unions are used for effective representation of core registers. - - \li Advisory Rule 19.7, Function-like macro defined.<br> - Function-like macros are used to allow more efficient code. - */ - - -/******************************************************************************* - * CMSIS definitions - ******************************************************************************/ -/** \ingroup Cortex_M3 - @{ - */ - -/* CMSIS CM3 definitions */ -#define __CM3_CMSIS_VERSION_MAIN (0x03) /*!< [31:16] CMSIS HAL main version */ -#define __CM3_CMSIS_VERSION_SUB (0x20) /*!< [15:0] CMSIS HAL sub version */ -#define __CM3_CMSIS_VERSION ((__CM3_CMSIS_VERSION_MAIN << 16) | \ - __CM3_CMSIS_VERSION_SUB ) /*!< CMSIS HAL version number */ - -#define __CORTEX_M (0x03) /*!< Cortex-M Core */ - - -#if defined ( __CC_ARM ) -#define __ASM __asm /*!< asm keyword for ARM Compiler */ -#define __INLINE __inline /*!< inline keyword for ARM Compiler */ -#define __STATIC_INLINE static __inline - -#elif defined ( __ICCARM__ ) -#define __ASM __asm /*!< asm keyword for IAR Compiler */ -#define __INLINE inline /*!< inline keyword for IAR Compiler. Only available in High optimization mode! */ -#define __STATIC_INLINE static inline - -#elif defined ( __TMS470__ ) -#define __ASM __asm /*!< asm keyword for TI CCS Compiler */ -#define __STATIC_INLINE static inline - -#elif defined ( __GNUC__ ) -#define __ASM __asm /*!< asm keyword for GNU Compiler */ -#define __INLINE inline /*!< inline keyword for GNU Compiler */ -#define __STATIC_INLINE static inline - -#elif defined ( __TASKING__ ) -#define __ASM __asm /*!< asm keyword for TASKING Compiler */ -#define __INLINE inline /*!< inline keyword for TASKING Compiler */ -#define __STATIC_INLINE static inline - -#endif - -/** __FPU_USED indicates whether an FPU is used or not. This core does not support an FPU at all -*/ -#define __FPU_USED 0 - -#if defined ( __CC_ARM ) -#if defined __TARGET_FPU_VFP -#warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" -#endif - -#elif defined ( __ICCARM__ ) -#if defined __ARMVFP__ -#warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" -#endif - -#elif defined ( __TMS470__ ) -#if defined __TI__VFP_SUPPORT____ -#warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" -#endif - -#elif defined ( __GNUC__ ) -#if defined (__VFP_FP__) && !defined(__SOFTFP__) -#warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" -#endif - -#elif defined ( __TASKING__ ) -#if defined __FPU_VFP__ -#error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" -#endif -#endif - -#include <stdint.h> /* standard types definitions */ -#include <core_cmInstr.h> /* Core Instruction Access */ -#include <core_cmFunc.h> /* Core Function Access */ - -#endif /* __CORE_CM3_H_GENERIC */ - -#ifndef __CMSIS_GENERIC - -#ifndef __CORE_CM3_H_DEPENDANT -#define __CORE_CM3_H_DEPENDANT - -/* check device defines and use defaults */ -#if defined __CHECK_DEVICE_DEFINES -#ifndef __CM3_REV -#define __CM3_REV 0x0200 -#warning "__CM3_REV not defined in device header file; using default!" -#endif - -#ifndef __MPU_PRESENT -#define __MPU_PRESENT 0 -#warning "__MPU_PRESENT not defined in device header file; using default!" -#endif - -#ifndef __NVIC_PRIO_BITS -#define __NVIC_PRIO_BITS 4 -#warning "__NVIC_PRIO_BITS not defined in device header file; using default!" -#endif - -#ifndef __Vendor_SysTickConfig -#define __Vendor_SysTickConfig 0 -#warning "__Vendor_SysTickConfig not defined in device header file; using default!" -#endif -#endif - -/* IO definitions (access restrictions to peripheral registers) */ -/** - \defgroup CMSIS_glob_defs CMSIS Global Defines - - <strong>IO Type Qualifiers</strong> are used - \li to specify the access to peripheral variables. - \li for automatic generation of peripheral register debug information. -*/ -#ifdef __cplusplus -#define __I volatile /*!< Defines 'read only' permissions */ -#else -#define __I volatile const /*!< Defines 'read only' permissions */ -#endif -#define __O volatile /*!< Defines 'write only' permissions */ -#define __IO volatile /*!< Defines 'read / write' permissions */ - -/*@} end of group Cortex_M3 */ - - - -/******************************************************************************* - * Register Abstraction - Core Register contain: - - Core Register - - Core NVIC Register - - Core SCB Register - - Core SysTick Register - - Core Debug Register - - Core MPU Register - ******************************************************************************/ -/** \defgroup CMSIS_core_register Defines and Type Definitions - \brief Type definitions and defines for Cortex-M processor based devices. -*/ - -/** \ingroup CMSIS_core_register - \defgroup CMSIS_CORE Status and Control Registers - \brief Core Register type definitions. - @{ - */ - -/** \brief Union type to access the Application Program Status Register (APSR). - */ -typedef union { - struct { -#if (__CORTEX_M != 0x04) - uint32_t _reserved0: 27; /*!< bit: 0..26 Reserved */ -#else - uint32_t _reserved0: 16; /*!< bit: 0..15 Reserved */ - uint32_t GE: 4; /*!< bit: 16..19 Greater than or Equal flags */ - uint32_t _reserved1: 7; /*!< bit: 20..26 Reserved */ -#endif - uint32_t Q: 1; /*!< bit: 27 Saturation condition flag */ - uint32_t V: 1; /*!< bit: 28 Overflow condition code flag */ - uint32_t C: 1; /*!< bit: 29 Carry condition code flag */ - uint32_t Z: 1; /*!< bit: 30 Zero condition code flag */ - uint32_t N: 1; /*!< bit: 31 Negative condition code flag */ - } b; /*!< Structure used for bit access */ - uint32_t w; /*!< Type used for word access */ -} APSR_Type; - - -/** \brief Union type to access the Interrupt Program Status Register (IPSR). - */ -typedef union { - struct { - uint32_t ISR: 9; /*!< bit: 0.. 8 Exception number */ - uint32_t _reserved0: 23; /*!< bit: 9..31 Reserved */ - } b; /*!< Structure used for bit access */ - uint32_t w; /*!< Type used for word access */ -} IPSR_Type; - - -/** \brief Union type to access the Special-Purpose Program Status Registers (xPSR). - */ -typedef union { - struct { - uint32_t ISR: 9; /*!< bit: 0.. 8 Exception number */ -#if (__CORTEX_M != 0x04) - uint32_t _reserved0: 15; /*!< bit: 9..23 Reserved */ -#else - uint32_t _reserved0: 7; /*!< bit: 9..15 Reserved */ - uint32_t GE: 4; /*!< bit: 16..19 Greater than or Equal flags */ - uint32_t _reserved1: 4; /*!< bit: 20..23 Reserved */ -#endif - uint32_t T: 1; /*!< bit: 24 Thumb bit (read 0) */ - uint32_t IT: 2; /*!< bit: 25..26 saved IT state (read 0) */ - uint32_t Q: 1; /*!< bit: 27 Saturation condition flag */ - uint32_t V: 1; /*!< bit: 28 Overflow condition code flag */ - uint32_t C: 1; /*!< bit: 29 Carry condition code flag */ - uint32_t Z: 1; /*!< bit: 30 Zero condition code flag */ - uint32_t N: 1; /*!< bit: 31 Negative condition code flag */ - } b; /*!< Structure used for bit access */ - uint32_t w; /*!< Type used for word access */ -} xPSR_Type; - - -/** \brief Union type to access the Control Registers (CONTROL). - */ -typedef union { - struct { - uint32_t nPRIV: 1; /*!< bit: 0 Execution privilege in Thread mode */ - uint32_t SPSEL: 1; /*!< bit: 1 Stack to be used */ - uint32_t FPCA: 1; /*!< bit: 2 FP extension active flag */ - uint32_t _reserved0: 29; /*!< bit: 3..31 Reserved */ - } b; /*!< Structure used for bit access */ - uint32_t w; /*!< Type used for word access */ -} CONTROL_Type; - -/*@} end of group CMSIS_CORE */ - - -/** \ingroup CMSIS_core_register - \defgroup CMSIS_NVIC Nested Vectored Interrupt Controller (NVIC) - \brief Type definitions for the NVIC Registers - @{ - */ - -/** \brief Structure type to access the Nested Vectored Interrupt Controller (NVIC). - */ -typedef struct { - __IO uint32_t ISER[8]; /*!< Offset: 0x000 (R/W) Interrupt Set Enable Register */ - uint32_t RESERVED0[24]; - __IO uint32_t ICER[8]; /*!< Offset: 0x080 (R/W) Interrupt Clear Enable Register */ - uint32_t RSERVED1[24]; - __IO uint32_t ISPR[8]; /*!< Offset: 0x100 (R/W) Interrupt Set Pending Register */ - uint32_t RESERVED2[24]; - __IO uint32_t ICPR[8]; /*!< Offset: 0x180 (R/W) Interrupt Clear Pending Register */ - uint32_t RESERVED3[24]; - __IO uint32_t IABR[8]; /*!< Offset: 0x200 (R/W) Interrupt Active bit Register */ - uint32_t RESERVED4[56]; - __IO uint8_t IP[240]; /*!< Offset: 0x300 (R/W) Interrupt Priority Register (8Bit wide) */ - uint32_t RESERVED5[644]; - __O uint32_t STIR; /*!< Offset: 0xE00 ( /W) Software Trigger Interrupt Register */ -} NVIC_Type; - -/* Software Triggered Interrupt Register Definitions */ -#define NVIC_STIR_INTID_Pos 0 /*!< STIR: INTLINESNUM Position */ -#define NVIC_STIR_INTID_Msk (0x1FFUL << NVIC_STIR_INTID_Pos) /*!< STIR: INTLINESNUM Mask */ - -/*@} end of group CMSIS_NVIC */ - - -/** \ingroup CMSIS_core_register - \defgroup CMSIS_SCB System Control Block (SCB) - \brief Type definitions for the System Control Block Registers - @{ - */ - -/** \brief Structure type to access the System Control Block (SCB). - */ -typedef struct { - __I uint32_t CPUID; /*!< Offset: 0x000 (R/ ) CPUID Base Register */ - __IO uint32_t ICSR; /*!< Offset: 0x004 (R/W) Interrupt Control and State Register */ - __IO uint32_t VTOR; /*!< Offset: 0x008 (R/W) Vector Table Offset Register */ - __IO uint32_t AIRCR; /*!< Offset: 0x00C (R/W) Application Interrupt and Reset Control Register */ - __IO uint32_t SCR; /*!< Offset: 0x010 (R/W) System Control Register */ - __IO uint32_t CCR; /*!< Offset: 0x014 (R/W) Configuration Control Register */ - __IO uint8_t SHP[12]; /*!< Offset: 0x018 (R/W) System Handlers Priority Registers (4-7, 8-11, 12-15) */ - __IO uint32_t SHCSR; /*!< Offset: 0x024 (R/W) System Handler Control and State Register */ - __IO uint32_t CFSR; /*!< Offset: 0x028 (R/W) Configurable Fault Status Register */ - __IO uint32_t HFSR; /*!< Offset: 0x02C (R/W) HardFault Status Register */ - __IO uint32_t DFSR; /*!< Offset: 0x030 (R/W) Debug Fault Status Register */ - __IO uint32_t MMFAR; /*!< Offset: 0x034 (R/W) MemManage Fault Address Register */ - __IO uint32_t BFAR; /*!< Offset: 0x038 (R/W) BusFault Address Register */ - __IO uint32_t AFSR; /*!< Offset: 0x03C (R/W) Auxiliary Fault Status Register */ - __I uint32_t PFR[2]; /*!< Offset: 0x040 (R/ ) Processor Feature Register */ - __I uint32_t DFR; /*!< Offset: 0x048 (R/ ) Debug Feature Register */ - __I uint32_t ADR; /*!< Offset: 0x04C (R/ ) Auxiliary Feature Register */ - __I uint32_t MMFR[4]; /*!< Offset: 0x050 (R/ ) Memory Model Feature Register */ - __I uint32_t ISAR[5]; /*!< Offset: 0x060 (R/ ) Instruction Set Attributes Register */ - uint32_t RESERVED0[5]; - __IO uint32_t CPACR; /*!< Offset: 0x088 (R/W) Coprocessor Access Control Register */ -} SCB_Type; - -/* SCB CPUID Register Definitions */ -#define SCB_CPUID_IMPLEMENTER_Pos 24 /*!< SCB CPUID: IMPLEMENTER Position */ -#define SCB_CPUID_IMPLEMENTER_Msk (0xFFUL << SCB_CPUID_IMPLEMENTER_Pos) /*!< SCB CPUID: IMPLEMENTER Mask */ - -#define SCB_CPUID_VARIANT_Pos 20 /*!< SCB CPUID: VARIANT Position */ -#define SCB_CPUID_VARIANT_Msk (0xFUL << SCB_CPUID_VARIANT_Pos) /*!< SCB CPUID: VARIANT Mask */ - -#define SCB_CPUID_ARCHITECTURE_Pos 16 /*!< SCB CPUID: ARCHITECTURE Position */ -#define SCB_CPUID_ARCHITECTURE_Msk (0xFUL << SCB_CPUID_ARCHITECTURE_Pos) /*!< SCB CPUID: ARCHITECTURE Mask */ - -#define SCB_CPUID_PARTNO_Pos 4 /*!< SCB CPUID: PARTNO Position */ -#define SCB_CPUID_PARTNO_Msk (0xFFFUL << SCB_CPUID_PARTNO_Pos) /*!< SCB CPUID: PARTNO Mask */ - -#define SCB_CPUID_REVISION_Pos 0 /*!< SCB CPUID: REVISION Position */ -#define SCB_CPUID_REVISION_Msk (0xFUL << SCB_CPUID_REVISION_Pos) /*!< SCB CPUID: REVISION Mask */ - -/* SCB Interrupt Control State Register Definitions */ -#define SCB_ICSR_NMIPENDSET_Pos 31 /*!< SCB ICSR: NMIPENDSET Position */ -#define SCB_ICSR_NMIPENDSET_Msk (1UL << SCB_ICSR_NMIPENDSET_Pos) /*!< SCB ICSR: NMIPENDSET Mask */ - -#define SCB_ICSR_PENDSVSET_Pos 28 /*!< SCB ICSR: PENDSVSET Position */ -#define SCB_ICSR_PENDSVSET_Msk (1UL << SCB_ICSR_PENDSVSET_Pos) /*!< SCB ICSR: PENDSVSET Mask */ - -#define SCB_ICSR_PENDSVCLR_Pos 27 /*!< SCB ICSR: PENDSVCLR Position */ -#define SCB_ICSR_PENDSVCLR_Msk (1UL << SCB_ICSR_PENDSVCLR_Pos) /*!< SCB ICSR: PENDSVCLR Mask */ - -#define SCB_ICSR_PENDSTSET_Pos 26 /*!< SCB ICSR: PENDSTSET Position */ -#define SCB_ICSR_PENDSTSET_Msk (1UL << SCB_ICSR_PENDSTSET_Pos) /*!< SCB ICSR: PENDSTSET Mask */ - -#define SCB_ICSR_PENDSTCLR_Pos 25 /*!< SCB ICSR: PENDSTCLR Position */ -#define SCB_ICSR_PENDSTCLR_Msk (1UL << SCB_ICSR_PENDSTCLR_Pos) /*!< SCB ICSR: PENDSTCLR Mask */ - -#define SCB_ICSR_ISRPREEMPT_Pos 23 /*!< SCB ICSR: ISRPREEMPT Position */ -#define SCB_ICSR_ISRPREEMPT_Msk (1UL << SCB_ICSR_ISRPREEMPT_Pos) /*!< SCB ICSR: ISRPREEMPT Mask */ - -#define SCB_ICSR_ISRPENDING_Pos 22 /*!< SCB ICSR: ISRPENDING Position */ -#define SCB_ICSR_ISRPENDING_Msk (1UL << SCB_ICSR_ISRPENDING_Pos) /*!< SCB ICSR: ISRPENDING Mask */ - -#define SCB_ICSR_VECTPENDING_Pos 12 /*!< SCB ICSR: VECTPENDING Position */ -#define SCB_ICSR_VECTPENDING_Msk (0x1FFUL << SCB_ICSR_VECTPENDING_Pos) /*!< SCB ICSR: VECTPENDING Mask */ - -#define SCB_ICSR_RETTOBASE_Pos 11 /*!< SCB ICSR: RETTOBASE Position */ -#define SCB_ICSR_RETTOBASE_Msk (1UL << SCB_ICSR_RETTOBASE_Pos) /*!< SCB ICSR: RETTOBASE Mask */ - -#define SCB_ICSR_VECTACTIVE_Pos 0 /*!< SCB ICSR: VECTACTIVE Position */ -#define SCB_ICSR_VECTACTIVE_Msk (0x1FFUL << SCB_ICSR_VECTACTIVE_Pos) /*!< SCB ICSR: VECTACTIVE Mask */ - -/* SCB Vector Table Offset Register Definitions */ -#if (__CM3_REV < 0x0201) /* core r2p1 */ -#define SCB_VTOR_TBLBASE_Pos 29 /*!< SCB VTOR: TBLBASE Position */ -#define SCB_VTOR_TBLBASE_Msk (1UL << SCB_VTOR_TBLBASE_Pos) /*!< SCB VTOR: TBLBASE Mask */ - -#define SCB_VTOR_TBLOFF_Pos 7 /*!< SCB VTOR: TBLOFF Position */ -#define SCB_VTOR_TBLOFF_Msk (0x3FFFFFUL << SCB_VTOR_TBLOFF_Pos) /*!< SCB VTOR: TBLOFF Mask */ -#else -#define SCB_VTOR_TBLOFF_Pos 7 /*!< SCB VTOR: TBLOFF Position */ -#define SCB_VTOR_TBLOFF_Msk (0x1FFFFFFUL << SCB_VTOR_TBLOFF_Pos) /*!< SCB VTOR: TBLOFF Mask */ -#endif - -/* SCB Application Interrupt and Reset Control Register Definitions */ -#define SCB_AIRCR_VECTKEY_Pos 16 /*!< SCB AIRCR: VECTKEY Position */ -#define SCB_AIRCR_VECTKEY_Msk (0xFFFFUL << SCB_AIRCR_VECTKEY_Pos) /*!< SCB AIRCR: VECTKEY Mask */ - -#define SCB_AIRCR_VECTKEYSTAT_Pos 16 /*!< SCB AIRCR: VECTKEYSTAT Position */ -#define SCB_AIRCR_VECTKEYSTAT_Msk (0xFFFFUL << SCB_AIRCR_VECTKEYSTAT_Pos) /*!< SCB AIRCR: VECTKEYSTAT Mask */ - -#define SCB_AIRCR_ENDIANESS_Pos 15 /*!< SCB AIRCR: ENDIANESS Position */ -#define SCB_AIRCR_ENDIANESS_Msk (1UL << SCB_AIRCR_ENDIANESS_Pos) /*!< SCB AIRCR: ENDIANESS Mask */ - -#define SCB_AIRCR_PRIGROUP_Pos 8 /*!< SCB AIRCR: PRIGROUP Position */ -#define SCB_AIRCR_PRIGROUP_Msk (7UL << SCB_AIRCR_PRIGROUP_Pos) /*!< SCB AIRCR: PRIGROUP Mask */ - -#define SCB_AIRCR_SYSRESETREQ_Pos 2 /*!< SCB AIRCR: SYSRESETREQ Position */ -#define SCB_AIRCR_SYSRESETREQ_Msk (1UL << SCB_AIRCR_SYSRESETREQ_Pos) /*!< SCB AIRCR: SYSRESETREQ Mask */ - -#define SCB_AIRCR_VECTCLRACTIVE_Pos 1 /*!< SCB AIRCR: VECTCLRACTIVE Position */ -#define SCB_AIRCR_VECTCLRACTIVE_Msk (1UL << SCB_AIRCR_VECTCLRACTIVE_Pos) /*!< SCB AIRCR: VECTCLRACTIVE Mask */ - -#define SCB_AIRCR_VECTRESET_Pos 0 /*!< SCB AIRCR: VECTRESET Position */ -#define SCB_AIRCR_VECTRESET_Msk (1UL << SCB_AIRCR_VECTRESET_Pos) /*!< SCB AIRCR: VECTRESET Mask */ - -/* SCB System Control Register Definitions */ -#define SCB_SCR_SEVONPEND_Pos 4 /*!< SCB SCR: SEVONPEND Position */ -#define SCB_SCR_SEVONPEND_Msk (1UL << SCB_SCR_SEVONPEND_Pos) /*!< SCB SCR: SEVONPEND Mask */ - -#define SCB_SCR_SLEEPDEEP_Pos 2 /*!< SCB SCR: SLEEPDEEP Position */ -#define SCB_SCR_SLEEPDEEP_Msk (1UL << SCB_SCR_SLEEPDEEP_Pos) /*!< SCB SCR: SLEEPDEEP Mask */ - -#define SCB_SCR_SLEEPONEXIT_Pos 1 /*!< SCB SCR: SLEEPONEXIT Position */ -#define SCB_SCR_SLEEPONEXIT_Msk (1UL << SCB_SCR_SLEEPONEXIT_Pos) /*!< SCB SCR: SLEEPONEXIT Mask */ - -/* SCB Configuration Control Register Definitions */ -#define SCB_CCR_STKALIGN_Pos 9 /*!< SCB CCR: STKALIGN Position */ -#define SCB_CCR_STKALIGN_Msk (1UL << SCB_CCR_STKALIGN_Pos) /*!< SCB CCR: STKALIGN Mask */ - -#define SCB_CCR_BFHFNMIGN_Pos 8 /*!< SCB CCR: BFHFNMIGN Position */ -#define SCB_CCR_BFHFNMIGN_Msk (1UL << SCB_CCR_BFHFNMIGN_Pos) /*!< SCB CCR: BFHFNMIGN Mask */ - -#define SCB_CCR_DIV_0_TRP_Pos 4 /*!< SCB CCR: DIV_0_TRP Position */ -#define SCB_CCR_DIV_0_TRP_Msk (1UL << SCB_CCR_DIV_0_TRP_Pos) /*!< SCB CCR: DIV_0_TRP Mask */ - -#define SCB_CCR_UNALIGN_TRP_Pos 3 /*!< SCB CCR: UNALIGN_TRP Position */ -#define SCB_CCR_UNALIGN_TRP_Msk (1UL << SCB_CCR_UNALIGN_TRP_Pos) /*!< SCB CCR: UNALIGN_TRP Mask */ - -#define SCB_CCR_USERSETMPEND_Pos 1 /*!< SCB CCR: USERSETMPEND Position */ -#define SCB_CCR_USERSETMPEND_Msk (1UL << SCB_CCR_USERSETMPEND_Pos) /*!< SCB CCR: USERSETMPEND Mask */ - -#define SCB_CCR_NONBASETHRDENA_Pos 0 /*!< SCB CCR: NONBASETHRDENA Position */ -#define SCB_CCR_NONBASETHRDENA_Msk (1UL << SCB_CCR_NONBASETHRDENA_Pos) /*!< SCB CCR: NONBASETHRDENA Mask */ - -/* SCB System Handler Control and State Register Definitions */ -#define SCB_SHCSR_USGFAULTENA_Pos 18 /*!< SCB SHCSR: USGFAULTENA Position */ -#define SCB_SHCSR_USGFAULTENA_Msk (1UL << SCB_SHCSR_USGFAULTENA_Pos) /*!< SCB SHCSR: USGFAULTENA Mask */ - -#define SCB_SHCSR_BUSFAULTENA_Pos 17 /*!< SCB SHCSR: BUSFAULTENA Position */ -#define SCB_SHCSR_BUSFAULTENA_Msk (1UL << SCB_SHCSR_BUSFAULTENA_Pos) /*!< SCB SHCSR: BUSFAULTENA Mask */ - -#define SCB_SHCSR_MEMFAULTENA_Pos 16 /*!< SCB SHCSR: MEMFAULTENA Position */ -#define SCB_SHCSR_MEMFAULTENA_Msk (1UL << SCB_SHCSR_MEMFAULTENA_Pos) /*!< SCB SHCSR: MEMFAULTENA Mask */ - -#define SCB_SHCSR_SVCALLPENDED_Pos 15 /*!< SCB SHCSR: SVCALLPENDED Position */ -#define SCB_SHCSR_SVCALLPENDED_Msk (1UL << SCB_SHCSR_SVCALLPENDED_Pos) /*!< SCB SHCSR: SVCALLPENDED Mask */ - -#define SCB_SHCSR_BUSFAULTPENDED_Pos 14 /*!< SCB SHCSR: BUSFAULTPENDED Position */ -#define SCB_SHCSR_BUSFAULTPENDED_Msk (1UL << SCB_SHCSR_BUSFAULTPENDED_Pos) /*!< SCB SHCSR: BUSFAULTPENDED Mask */ - -#define SCB_SHCSR_MEMFAULTPENDED_Pos 13 /*!< SCB SHCSR: MEMFAULTPENDED Position */ -#define SCB_SHCSR_MEMFAULTPENDED_Msk (1UL << SCB_SHCSR_MEMFAULTPENDED_Pos) /*!< SCB SHCSR: MEMFAULTPENDED Mask */ - -#define SCB_SHCSR_USGFAULTPENDED_Pos 12 /*!< SCB SHCSR: USGFAULTPENDED Position */ -#define SCB_SHCSR_USGFAULTPENDED_Msk (1UL << SCB_SHCSR_USGFAULTPENDED_Pos) /*!< SCB SHCSR: USGFAULTPENDED Mask */ - -#define SCB_SHCSR_SYSTICKACT_Pos 11 /*!< SCB SHCSR: SYSTICKACT Position */ -#define SCB_SHCSR_SYSTICKACT_Msk (1UL << SCB_SHCSR_SYSTICKACT_Pos) /*!< SCB SHCSR: SYSTICKACT Mask */ - -#define SCB_SHCSR_PENDSVACT_Pos 10 /*!< SCB SHCSR: PENDSVACT Position */ -#define SCB_SHCSR_PENDSVACT_Msk (1UL << SCB_SHCSR_PENDSVACT_Pos) /*!< SCB SHCSR: PENDSVACT Mask */ - -#define SCB_SHCSR_MONITORACT_Pos 8 /*!< SCB SHCSR: MONITORACT Position */ -#define SCB_SHCSR_MONITORACT_Msk (1UL << SCB_SHCSR_MONITORACT_Pos) /*!< SCB SHCSR: MONITORACT Mask */ - -#define SCB_SHCSR_SVCALLACT_Pos 7 /*!< SCB SHCSR: SVCALLACT Position */ -#define SCB_SHCSR_SVCALLACT_Msk (1UL << SCB_SHCSR_SVCALLACT_Pos) /*!< SCB SHCSR: SVCALLACT Mask */ - -#define SCB_SHCSR_USGFAULTACT_Pos 3 /*!< SCB SHCSR: USGFAULTACT Position */ -#define SCB_SHCSR_USGFAULTACT_Msk (1UL << SCB_SHCSR_USGFAULTACT_Pos) /*!< SCB SHCSR: USGFAULTACT Mask */ - -#define SCB_SHCSR_BUSFAULTACT_Pos 1 /*!< SCB SHCSR: BUSFAULTACT Position */ -#define SCB_SHCSR_BUSFAULTACT_Msk (1UL << SCB_SHCSR_BUSFAULTACT_Pos) /*!< SCB SHCSR: BUSFAULTACT Mask */ - -#define SCB_SHCSR_MEMFAULTACT_Pos 0 /*!< SCB SHCSR: MEMFAULTACT Position */ -#define SCB_SHCSR_MEMFAULTACT_Msk (1UL << SCB_SHCSR_MEMFAULTACT_Pos) /*!< SCB SHCSR: MEMFAULTACT Mask */ - -/* SCB Configurable Fault Status Registers Definitions */ -#define SCB_CFSR_USGFAULTSR_Pos 16 /*!< SCB CFSR: Usage Fault Status Register Position */ -#define SCB_CFSR_USGFAULTSR_Msk (0xFFFFUL << SCB_CFSR_USGFAULTSR_Pos) /*!< SCB CFSR: Usage Fault Status Register Mask */ - -#define SCB_CFSR_BUSFAULTSR_Pos 8 /*!< SCB CFSR: Bus Fault Status Register Position */ -#define SCB_CFSR_BUSFAULTSR_Msk (0xFFUL << SCB_CFSR_BUSFAULTSR_Pos) /*!< SCB CFSR: Bus Fault Status Register Mask */ - -#define SCB_CFSR_MEMFAULTSR_Pos 0 /*!< SCB CFSR: Memory Manage Fault Status Register Position */ -#define SCB_CFSR_MEMFAULTSR_Msk (0xFFUL << SCB_CFSR_MEMFAULTSR_Pos) /*!< SCB CFSR: Memory Manage Fault Status Register Mask */ - -/* SCB Hard Fault Status Registers Definitions */ -#define SCB_HFSR_DEBUGEVT_Pos 31 /*!< SCB HFSR: DEBUGEVT Position */ -#define SCB_HFSR_DEBUGEVT_Msk (1UL << SCB_HFSR_DEBUGEVT_Pos) /*!< SCB HFSR: DEBUGEVT Mask */ - -#define SCB_HFSR_FORCED_Pos 30 /*!< SCB HFSR: FORCED Position */ -#define SCB_HFSR_FORCED_Msk (1UL << SCB_HFSR_FORCED_Pos) /*!< SCB HFSR: FORCED Mask */ - -#define SCB_HFSR_VECTTBL_Pos 1 /*!< SCB HFSR: VECTTBL Position */ -#define SCB_HFSR_VECTTBL_Msk (1UL << SCB_HFSR_VECTTBL_Pos) /*!< SCB HFSR: VECTTBL Mask */ - -/* SCB Debug Fault Status Register Definitions */ -#define SCB_DFSR_EXTERNAL_Pos 4 /*!< SCB DFSR: EXTERNAL Position */ -#define SCB_DFSR_EXTERNAL_Msk (1UL << SCB_DFSR_EXTERNAL_Pos) /*!< SCB DFSR: EXTERNAL Mask */ - -#define SCB_DFSR_VCATCH_Pos 3 /*!< SCB DFSR: VCATCH Position */ -#define SCB_DFSR_VCATCH_Msk (1UL << SCB_DFSR_VCATCH_Pos) /*!< SCB DFSR: VCATCH Mask */ - -#define SCB_DFSR_DWTTRAP_Pos 2 /*!< SCB DFSR: DWTTRAP Position */ -#define SCB_DFSR_DWTTRAP_Msk (1UL << SCB_DFSR_DWTTRAP_Pos) /*!< SCB DFSR: DWTTRAP Mask */ - -#define SCB_DFSR_BKPT_Pos 1 /*!< SCB DFSR: BKPT Position */ -#define SCB_DFSR_BKPT_Msk (1UL << SCB_DFSR_BKPT_Pos) /*!< SCB DFSR: BKPT Mask */ - -#define SCB_DFSR_HALTED_Pos 0 /*!< SCB DFSR: HALTED Position */ -#define SCB_DFSR_HALTED_Msk (1UL << SCB_DFSR_HALTED_Pos) /*!< SCB DFSR: HALTED Mask */ - -/*@} end of group CMSIS_SCB */ - - -/** \ingroup CMSIS_core_register - \defgroup CMSIS_SCnSCB System Controls not in SCB (SCnSCB) - \brief Type definitions for the System Control and ID Register not in the SCB - @{ - */ - -/** \brief Structure type to access the System Control and ID Register not in the SCB. - */ -typedef struct { - uint32_t RESERVED0[1]; - __I uint32_t ICTR; /*!< Offset: 0x004 (R/ ) Interrupt Controller Type Register */ -#if ((defined __CM3_REV) && (__CM3_REV >= 0x200)) - __IO uint32_t ACTLR; /*!< Offset: 0x008 (R/W) Auxiliary Control Register */ -#else - uint32_t RESERVED1[1]; -#endif -} SCnSCB_Type; - -/* Interrupt Controller Type Register Definitions */ -#define SCnSCB_ICTR_INTLINESNUM_Pos 0 /*!< ICTR: INTLINESNUM Position */ -#define SCnSCB_ICTR_INTLINESNUM_Msk (0xFUL << SCnSCB_ICTR_INTLINESNUM_Pos) /*!< ICTR: INTLINESNUM Mask */ - -/* Auxiliary Control Register Definitions */ - -#define SCnSCB_ACTLR_DISFOLD_Pos 2 /*!< ACTLR: DISFOLD Position */ -#define SCnSCB_ACTLR_DISFOLD_Msk (1UL << SCnSCB_ACTLR_DISFOLD_Pos) /*!< ACTLR: DISFOLD Mask */ - -#define SCnSCB_ACTLR_DISDEFWBUF_Pos 1 /*!< ACTLR: DISDEFWBUF Position */ -#define SCnSCB_ACTLR_DISDEFWBUF_Msk (1UL << SCnSCB_ACTLR_DISDEFWBUF_Pos) /*!< ACTLR: DISDEFWBUF Mask */ - -#define SCnSCB_ACTLR_DISMCYCINT_Pos 0 /*!< ACTLR: DISMCYCINT Position */ -#define SCnSCB_ACTLR_DISMCYCINT_Msk (1UL << SCnSCB_ACTLR_DISMCYCINT_Pos) /*!< ACTLR: DISMCYCINT Mask */ - -/*@} end of group CMSIS_SCnotSCB */ - - -/** \ingroup CMSIS_core_register - \defgroup CMSIS_SysTick System Tick Timer (SysTick) - \brief Type definitions for the System Timer Registers. - @{ - */ - -/** \brief Structure type to access the System Timer (SysTick). - */ -typedef struct { - __IO uint32_t CTRL; /*!< Offset: 0x000 (R/W) SysTick Control and Status Register */ - __IO uint32_t LOAD; /*!< Offset: 0x004 (R/W) SysTick Reload Value Register */ - __IO uint32_t VAL; /*!< Offset: 0x008 (R/W) SysTick Current Value Register */ - __I uint32_t CALIB; /*!< Offset: 0x00C (R/ ) SysTick Calibration Register */ -} SysTick_Type; - -/* SysTick Control / Status Register Definitions */ -#define SysTick_CTRL_COUNTFLAG_Pos 16 /*!< SysTick CTRL: COUNTFLAG Position */ -#define SysTick_CTRL_COUNTFLAG_Msk (1UL << SysTick_CTRL_COUNTFLAG_Pos) /*!< SysTick CTRL: COUNTFLAG Mask */ - -#define SysTick_CTRL_CLKSOURCE_Pos 2 /*!< SysTick CTRL: CLKSOURCE Position */ -#define SysTick_CTRL_CLKSOURCE_Msk (1UL << SysTick_CTRL_CLKSOURCE_Pos) /*!< SysTick CTRL: CLKSOURCE Mask */ - -#define SysTick_CTRL_TICKINT_Pos 1 /*!< SysTick CTRL: TICKINT Position */ -#define SysTick_CTRL_TICKINT_Msk (1UL << SysTick_CTRL_TICKINT_Pos) /*!< SysTick CTRL: TICKINT Mask */ - -#define SysTick_CTRL_ENABLE_Pos 0 /*!< SysTick CTRL: ENABLE Position */ -#define SysTick_CTRL_ENABLE_Msk (1UL << SysTick_CTRL_ENABLE_Pos) /*!< SysTick CTRL: ENABLE Mask */ - -/* SysTick Reload Register Definitions */ -#define SysTick_LOAD_RELOAD_Pos 0 /*!< SysTick LOAD: RELOAD Position */ -#define SysTick_LOAD_RELOAD_Msk (0xFFFFFFUL << SysTick_LOAD_RELOAD_Pos) /*!< SysTick LOAD: RELOAD Mask */ - -/* SysTick Current Register Definitions */ -#define SysTick_VAL_CURRENT_Pos 0 /*!< SysTick VAL: CURRENT Position */ -#define SysTick_VAL_CURRENT_Msk (0xFFFFFFUL << SysTick_VAL_CURRENT_Pos) /*!< SysTick VAL: CURRENT Mask */ - -/* SysTick Calibration Register Definitions */ -#define SysTick_CALIB_NOREF_Pos 31 /*!< SysTick CALIB: NOREF Position */ -#define SysTick_CALIB_NOREF_Msk (1UL << SysTick_CALIB_NOREF_Pos) /*!< SysTick CALIB: NOREF Mask */ - -#define SysTick_CALIB_SKEW_Pos 30 /*!< SysTick CALIB: SKEW Position */ -#define SysTick_CALIB_SKEW_Msk (1UL << SysTick_CALIB_SKEW_Pos) /*!< SysTick CALIB: SKEW Mask */ - -#define SysTick_CALIB_TENMS_Pos 0 /*!< SysTick CALIB: TENMS Position */ -#define SysTick_CALIB_TENMS_Msk (0xFFFFFFUL << SysTick_VAL_CURRENT_Pos) /*!< SysTick CALIB: TENMS Mask */ - -/*@} end of group CMSIS_SysTick */ - - -/** \ingroup CMSIS_core_register - \defgroup CMSIS_ITM Instrumentation Trace Macrocell (ITM) - \brief Type definitions for the Instrumentation Trace Macrocell (ITM) - @{ - */ - -/** \brief Structure type to access the Instrumentation Trace Macrocell Register (ITM). - */ -typedef struct { - __O union { - __O uint8_t u8; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 8-bit */ - __O uint16_t u16; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 16-bit */ - __O uint32_t u32; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 32-bit */ - } PORT [32]; /*!< Offset: 0x000 ( /W) ITM Stimulus Port Registers */ - uint32_t RESERVED0[864]; - __IO uint32_t TER; /*!< Offset: 0xE00 (R/W) ITM Trace Enable Register */ - uint32_t RESERVED1[15]; - __IO uint32_t TPR; /*!< Offset: 0xE40 (R/W) ITM Trace Privilege Register */ - uint32_t RESERVED2[15]; - __IO uint32_t TCR; /*!< Offset: 0xE80 (R/W) ITM Trace Control Register */ - uint32_t RESERVED3[29]; - __O uint32_t IWR; /*!< Offset: 0xEF8 ( /W) ITM Integration Write Register */ - __I uint32_t IRR; /*!< Offset: 0xEFC (R/ ) ITM Integration Read Register */ - __IO uint32_t IMCR; /*!< Offset: 0xF00 (R/W) ITM Integration Mode Control Register */ - uint32_t RESERVED4[43]; - __O uint32_t LAR; /*!< Offset: 0xFB0 ( /W) ITM Lock Access Register */ - __I uint32_t LSR; /*!< Offset: 0xFB4 (R/ ) ITM Lock Status Register */ - uint32_t RESERVED5[6]; - __I uint32_t PID4; /*!< Offset: 0xFD0 (R/ ) ITM Peripheral Identification Register #4 */ - __I uint32_t PID5; /*!< Offset: 0xFD4 (R/ ) ITM Peripheral Identification Register #5 */ - __I uint32_t PID6; /*!< Offset: 0xFD8 (R/ ) ITM Peripheral Identification Register #6 */ - __I uint32_t PID7; /*!< Offset: 0xFDC (R/ ) ITM Peripheral Identification Register #7 */ - __I uint32_t PID0; /*!< Offset: 0xFE0 (R/ ) ITM Peripheral Identification Register #0 */ - __I uint32_t PID1; /*!< Offset: 0xFE4 (R/ ) ITM Peripheral Identification Register #1 */ - __I uint32_t PID2; /*!< Offset: 0xFE8 (R/ ) ITM Peripheral Identification Register #2 */ - __I uint32_t PID3; /*!< Offset: 0xFEC (R/ ) ITM Peripheral Identification Register #3 */ - __I uint32_t CID0; /*!< Offset: 0xFF0 (R/ ) ITM Component Identification Register #0 */ - __I uint32_t CID1; /*!< Offset: 0xFF4 (R/ ) ITM Component Identification Register #1 */ - __I uint32_t CID2; /*!< Offset: 0xFF8 (R/ ) ITM Component Identification Register #2 */ - __I uint32_t CID3; /*!< Offset: 0xFFC (R/ ) ITM Component Identification Register #3 */ -} ITM_Type; - -/* ITM Trace Privilege Register Definitions */ -#define ITM_TPR_PRIVMASK_Pos 0 /*!< ITM TPR: PRIVMASK Position */ -#define ITM_TPR_PRIVMASK_Msk (0xFUL << ITM_TPR_PRIVMASK_Pos) /*!< ITM TPR: PRIVMASK Mask */ - -/* ITM Trace Control Register Definitions */ -#define ITM_TCR_BUSY_Pos 23 /*!< ITM TCR: BUSY Position */ -#define ITM_TCR_BUSY_Msk (1UL << ITM_TCR_BUSY_Pos) /*!< ITM TCR: BUSY Mask */ - -#define ITM_TCR_TraceBusID_Pos 16 /*!< ITM TCR: ATBID Position */ -#define ITM_TCR_TraceBusID_Msk (0x7FUL << ITM_TCR_TraceBusID_Pos) /*!< ITM TCR: ATBID Mask */ - -#define ITM_TCR_GTSFREQ_Pos 10 /*!< ITM TCR: Global timestamp frequency Position */ -#define ITM_TCR_GTSFREQ_Msk (3UL << ITM_TCR_GTSFREQ_Pos) /*!< ITM TCR: Global timestamp frequency Mask */ - -#define ITM_TCR_TSPrescale_Pos 8 /*!< ITM TCR: TSPrescale Position */ -#define ITM_TCR_TSPrescale_Msk (3UL << ITM_TCR_TSPrescale_Pos) /*!< ITM TCR: TSPrescale Mask */ - -#define ITM_TCR_SWOENA_Pos 4 /*!< ITM TCR: SWOENA Position */ -#define ITM_TCR_SWOENA_Msk (1UL << ITM_TCR_SWOENA_Pos) /*!< ITM TCR: SWOENA Mask */ - -#define ITM_TCR_DWTENA_Pos 3 /*!< ITM TCR: DWTENA Position */ -#define ITM_TCR_DWTENA_Msk (1UL << ITM_TCR_DWTENA_Pos) /*!< ITM TCR: DWTENA Mask */ - -#define ITM_TCR_SYNCENA_Pos 2 /*!< ITM TCR: SYNCENA Position */ -#define ITM_TCR_SYNCENA_Msk (1UL << ITM_TCR_SYNCENA_Pos) /*!< ITM TCR: SYNCENA Mask */ - -#define ITM_TCR_TSENA_Pos 1 /*!< ITM TCR: TSENA Position */ -#define ITM_TCR_TSENA_Msk (1UL << ITM_TCR_TSENA_Pos) /*!< ITM TCR: TSENA Mask */ - -#define ITM_TCR_ITMENA_Pos 0 /*!< ITM TCR: ITM Enable bit Position */ -#define ITM_TCR_ITMENA_Msk (1UL << ITM_TCR_ITMENA_Pos) /*!< ITM TCR: ITM Enable bit Mask */ - -/* ITM Integration Write Register Definitions */ -#define ITM_IWR_ATVALIDM_Pos 0 /*!< ITM IWR: ATVALIDM Position */ -#define ITM_IWR_ATVALIDM_Msk (1UL << ITM_IWR_ATVALIDM_Pos) /*!< ITM IWR: ATVALIDM Mask */ - -/* ITM Integration Read Register Definitions */ -#define ITM_IRR_ATREADYM_Pos 0 /*!< ITM IRR: ATREADYM Position */ -#define ITM_IRR_ATREADYM_Msk (1UL << ITM_IRR_ATREADYM_Pos) /*!< ITM IRR: ATREADYM Mask */ - -/* ITM Integration Mode Control Register Definitions */ -#define ITM_IMCR_INTEGRATION_Pos 0 /*!< ITM IMCR: INTEGRATION Position */ -#define ITM_IMCR_INTEGRATION_Msk (1UL << ITM_IMCR_INTEGRATION_Pos) /*!< ITM IMCR: INTEGRATION Mask */ - -/* ITM Lock Status Register Definitions */ -#define ITM_LSR_ByteAcc_Pos 2 /*!< ITM LSR: ByteAcc Position */ -#define ITM_LSR_ByteAcc_Msk (1UL << ITM_LSR_ByteAcc_Pos) /*!< ITM LSR: ByteAcc Mask */ - -#define ITM_LSR_Access_Pos 1 /*!< ITM LSR: Access Position */ -#define ITM_LSR_Access_Msk (1UL << ITM_LSR_Access_Pos) /*!< ITM LSR: Access Mask */ - -#define ITM_LSR_Present_Pos 0 /*!< ITM LSR: Present Position */ -#define ITM_LSR_Present_Msk (1UL << ITM_LSR_Present_Pos) /*!< ITM LSR: Present Mask */ - -/*@}*/ /* end of group CMSIS_ITM */ - - -/** \ingroup CMSIS_core_register - \defgroup CMSIS_DWT Data Watchpoint and Trace (DWT) - \brief Type definitions for the Data Watchpoint and Trace (DWT) - @{ - */ - -/** \brief Structure type to access the Data Watchpoint and Trace Register (DWT). - */ -typedef struct { - __IO uint32_t CTRL; /*!< Offset: 0x000 (R/W) Control Register */ - __IO uint32_t CYCCNT; /*!< Offset: 0x004 (R/W) Cycle Count Register */ - __IO uint32_t CPICNT; /*!< Offset: 0x008 (R/W) CPI Count Register */ - __IO uint32_t EXCCNT; /*!< Offset: 0x00C (R/W) Exception Overhead Count Register */ - __IO uint32_t SLEEPCNT; /*!< Offset: 0x010 (R/W) Sleep Count Register */ - __IO uint32_t LSUCNT; /*!< Offset: 0x014 (R/W) LSU Count Register */ - __IO uint32_t FOLDCNT; /*!< Offset: 0x018 (R/W) Folded-instruction Count Register */ - __I uint32_t PCSR; /*!< Offset: 0x01C (R/ ) Program Counter Sample Register */ - __IO uint32_t COMP0; /*!< Offset: 0x020 (R/W) Comparator Register 0 */ - __IO uint32_t MASK0; /*!< Offset: 0x024 (R/W) Mask Register 0 */ - __IO uint32_t FUNCTION0; /*!< Offset: 0x028 (R/W) Function Register 0 */ - uint32_t RESERVED0[1]; - __IO uint32_t COMP1; /*!< Offset: 0x030 (R/W) Comparator Register 1 */ - __IO uint32_t MASK1; /*!< Offset: 0x034 (R/W) Mask Register 1 */ - __IO uint32_t FUNCTION1; /*!< Offset: 0x038 (R/W) Function Register 1 */ - uint32_t RESERVED1[1]; - __IO uint32_t COMP2; /*!< Offset: 0x040 (R/W) Comparator Register 2 */ - __IO uint32_t MASK2; /*!< Offset: 0x044 (R/W) Mask Register 2 */ - __IO uint32_t FUNCTION2; /*!< Offset: 0x048 (R/W) Function Register 2 */ - uint32_t RESERVED2[1]; - __IO uint32_t COMP3; /*!< Offset: 0x050 (R/W) Comparator Register 3 */ - __IO uint32_t MASK3; /*!< Offset: 0x054 (R/W) Mask Register 3 */ - __IO uint32_t FUNCTION3; /*!< Offset: 0x058 (R/W) Function Register 3 */ -} DWT_Type; - -/* DWT Control Register Definitions */ -#define DWT_CTRL_NUMCOMP_Pos 28 /*!< DWT CTRL: NUMCOMP Position */ -#define DWT_CTRL_NUMCOMP_Msk (0xFUL << DWT_CTRL_NUMCOMP_Pos) /*!< DWT CTRL: NUMCOMP Mask */ - -#define DWT_CTRL_NOTRCPKT_Pos 27 /*!< DWT CTRL: NOTRCPKT Position */ -#define DWT_CTRL_NOTRCPKT_Msk (0x1UL << DWT_CTRL_NOTRCPKT_Pos) /*!< DWT CTRL: NOTRCPKT Mask */ - -#define DWT_CTRL_NOEXTTRIG_Pos 26 /*!< DWT CTRL: NOEXTTRIG Position */ -#define DWT_CTRL_NOEXTTRIG_Msk (0x1UL << DWT_CTRL_NOEXTTRIG_Pos) /*!< DWT CTRL: NOEXTTRIG Mask */ - -#define DWT_CTRL_NOCYCCNT_Pos 25 /*!< DWT CTRL: NOCYCCNT Position */ -#define DWT_CTRL_NOCYCCNT_Msk (0x1UL << DWT_CTRL_NOCYCCNT_Pos) /*!< DWT CTRL: NOCYCCNT Mask */ - -#define DWT_CTRL_NOPRFCNT_Pos 24 /*!< DWT CTRL: NOPRFCNT Position */ -#define DWT_CTRL_NOPRFCNT_Msk (0x1UL << DWT_CTRL_NOPRFCNT_Pos) /*!< DWT CTRL: NOPRFCNT Mask */ - -#define DWT_CTRL_CYCEVTENA_Pos 22 /*!< DWT CTRL: CYCEVTENA Position */ -#define DWT_CTRL_CYCEVTENA_Msk (0x1UL << DWT_CTRL_CYCEVTENA_Pos) /*!< DWT CTRL: CYCEVTENA Mask */ - -#define DWT_CTRL_FOLDEVTENA_Pos 21 /*!< DWT CTRL: FOLDEVTENA Position */ -#define DWT_CTRL_FOLDEVTENA_Msk (0x1UL << DWT_CTRL_FOLDEVTENA_Pos) /*!< DWT CTRL: FOLDEVTENA Mask */ - -#define DWT_CTRL_LSUEVTENA_Pos 20 /*!< DWT CTRL: LSUEVTENA Position */ -#define DWT_CTRL_LSUEVTENA_Msk (0x1UL << DWT_CTRL_LSUEVTENA_Pos) /*!< DWT CTRL: LSUEVTENA Mask */ - -#define DWT_CTRL_SLEEPEVTENA_Pos 19 /*!< DWT CTRL: SLEEPEVTENA Position */ -#define DWT_CTRL_SLEEPEVTENA_Msk (0x1UL << DWT_CTRL_SLEEPEVTENA_Pos) /*!< DWT CTRL: SLEEPEVTENA Mask */ - -#define DWT_CTRL_EXCEVTENA_Pos 18 /*!< DWT CTRL: EXCEVTENA Position */ -#define DWT_CTRL_EXCEVTENA_Msk (0x1UL << DWT_CTRL_EXCEVTENA_Pos) /*!< DWT CTRL: EXCEVTENA Mask */ - -#define DWT_CTRL_CPIEVTENA_Pos 17 /*!< DWT CTRL: CPIEVTENA Position */ -#define DWT_CTRL_CPIEVTENA_Msk (0x1UL << DWT_CTRL_CPIEVTENA_Pos) /*!< DWT CTRL: CPIEVTENA Mask */ - -#define DWT_CTRL_EXCTRCENA_Pos 16 /*!< DWT CTRL: EXCTRCENA Position */ -#define DWT_CTRL_EXCTRCENA_Msk (0x1UL << DWT_CTRL_EXCTRCENA_Pos) /*!< DWT CTRL: EXCTRCENA Mask */ - -#define DWT_CTRL_PCSAMPLENA_Pos 12 /*!< DWT CTRL: PCSAMPLENA Position */ -#define DWT_CTRL_PCSAMPLENA_Msk (0x1UL << DWT_CTRL_PCSAMPLENA_Pos) /*!< DWT CTRL: PCSAMPLENA Mask */ - -#define DWT_CTRL_SYNCTAP_Pos 10 /*!< DWT CTRL: SYNCTAP Position */ -#define DWT_CTRL_SYNCTAP_Msk (0x3UL << DWT_CTRL_SYNCTAP_Pos) /*!< DWT CTRL: SYNCTAP Mask */ - -#define DWT_CTRL_CYCTAP_Pos 9 /*!< DWT CTRL: CYCTAP Position */ -#define DWT_CTRL_CYCTAP_Msk (0x1UL << DWT_CTRL_CYCTAP_Pos) /*!< DWT CTRL: CYCTAP Mask */ - -#define DWT_CTRL_POSTINIT_Pos 5 /*!< DWT CTRL: POSTINIT Position */ -#define DWT_CTRL_POSTINIT_Msk (0xFUL << DWT_CTRL_POSTINIT_Pos) /*!< DWT CTRL: POSTINIT Mask */ - -#define DWT_CTRL_POSTPRESET_Pos 1 /*!< DWT CTRL: POSTPRESET Position */ -#define DWT_CTRL_POSTPRESET_Msk (0xFUL << DWT_CTRL_POSTPRESET_Pos) /*!< DWT CTRL: POSTPRESET Mask */ - -#define DWT_CTRL_CYCCNTENA_Pos 0 /*!< DWT CTRL: CYCCNTENA Position */ -#define DWT_CTRL_CYCCNTENA_Msk (0x1UL << DWT_CTRL_CYCCNTENA_Pos) /*!< DWT CTRL: CYCCNTENA Mask */ - -/* DWT CPI Count Register Definitions */ -#define DWT_CPICNT_CPICNT_Pos 0 /*!< DWT CPICNT: CPICNT Position */ -#define DWT_CPICNT_CPICNT_Msk (0xFFUL << DWT_CPICNT_CPICNT_Pos) /*!< DWT CPICNT: CPICNT Mask */ - -/* DWT Exception Overhead Count Register Definitions */ -#define DWT_EXCCNT_EXCCNT_Pos 0 /*!< DWT EXCCNT: EXCCNT Position */ -#define DWT_EXCCNT_EXCCNT_Msk (0xFFUL << DWT_EXCCNT_EXCCNT_Pos) /*!< DWT EXCCNT: EXCCNT Mask */ - -/* DWT Sleep Count Register Definitions */ -#define DWT_SLEEPCNT_SLEEPCNT_Pos 0 /*!< DWT SLEEPCNT: SLEEPCNT Position */ -#define DWT_SLEEPCNT_SLEEPCNT_Msk (0xFFUL << DWT_SLEEPCNT_SLEEPCNT_Pos) /*!< DWT SLEEPCNT: SLEEPCNT Mask */ - -/* DWT LSU Count Register Definitions */ -#define DWT_LSUCNT_LSUCNT_Pos 0 /*!< DWT LSUCNT: LSUCNT Position */ -#define DWT_LSUCNT_LSUCNT_Msk (0xFFUL << DWT_LSUCNT_LSUCNT_Pos) /*!< DWT LSUCNT: LSUCNT Mask */ - -/* DWT Folded-instruction Count Register Definitions */ -#define DWT_FOLDCNT_FOLDCNT_Pos 0 /*!< DWT FOLDCNT: FOLDCNT Position */ -#define DWT_FOLDCNT_FOLDCNT_Msk (0xFFUL << DWT_FOLDCNT_FOLDCNT_Pos) /*!< DWT FOLDCNT: FOLDCNT Mask */ - -/* DWT Comparator Mask Register Definitions */ -#define DWT_MASK_MASK_Pos 0 /*!< DWT MASK: MASK Position */ -#define DWT_MASK_MASK_Msk (0x1FUL << DWT_MASK_MASK_Pos) /*!< DWT MASK: MASK Mask */ - -/* DWT Comparator Function Register Definitions */ -#define DWT_FUNCTION_MATCHED_Pos 24 /*!< DWT FUNCTION: MATCHED Position */ -#define DWT_FUNCTION_MATCHED_Msk (0x1UL << DWT_FUNCTION_MATCHED_Pos) /*!< DWT FUNCTION: MATCHED Mask */ - -#define DWT_FUNCTION_DATAVADDR1_Pos 16 /*!< DWT FUNCTION: DATAVADDR1 Position */ -#define DWT_FUNCTION_DATAVADDR1_Msk (0xFUL << DWT_FUNCTION_DATAVADDR1_Pos) /*!< DWT FUNCTION: DATAVADDR1 Mask */ - -#define DWT_FUNCTION_DATAVADDR0_Pos 12 /*!< DWT FUNCTION: DATAVADDR0 Position */ -#define DWT_FUNCTION_DATAVADDR0_Msk (0xFUL << DWT_FUNCTION_DATAVADDR0_Pos) /*!< DWT FUNCTION: DATAVADDR0 Mask */ - -#define DWT_FUNCTION_DATAVSIZE_Pos 10 /*!< DWT FUNCTION: DATAVSIZE Position */ -#define DWT_FUNCTION_DATAVSIZE_Msk (0x3UL << DWT_FUNCTION_DATAVSIZE_Pos) /*!< DWT FUNCTION: DATAVSIZE Mask */ - -#define DWT_FUNCTION_LNK1ENA_Pos 9 /*!< DWT FUNCTION: LNK1ENA Position */ -#define DWT_FUNCTION_LNK1ENA_Msk (0x1UL << DWT_FUNCTION_LNK1ENA_Pos) /*!< DWT FUNCTION: LNK1ENA Mask */ - -#define DWT_FUNCTION_DATAVMATCH_Pos 8 /*!< DWT FUNCTION: DATAVMATCH Position */ -#define DWT_FUNCTION_DATAVMATCH_Msk (0x1UL << DWT_FUNCTION_DATAVMATCH_Pos) /*!< DWT FUNCTION: DATAVMATCH Mask */ - -#define DWT_FUNCTION_CYCMATCH_Pos 7 /*!< DWT FUNCTION: CYCMATCH Position */ -#define DWT_FUNCTION_CYCMATCH_Msk (0x1UL << DWT_FUNCTION_CYCMATCH_Pos) /*!< DWT FUNCTION: CYCMATCH Mask */ - -#define DWT_FUNCTION_EMITRANGE_Pos 5 /*!< DWT FUNCTION: EMITRANGE Position */ -#define DWT_FUNCTION_EMITRANGE_Msk (0x1UL << DWT_FUNCTION_EMITRANGE_Pos) /*!< DWT FUNCTION: EMITRANGE Mask */ - -#define DWT_FUNCTION_FUNCTION_Pos 0 /*!< DWT FUNCTION: FUNCTION Position */ -#define DWT_FUNCTION_FUNCTION_Msk (0xFUL << DWT_FUNCTION_FUNCTION_Pos) /*!< DWT FUNCTION: FUNCTION Mask */ - -/*@}*/ /* end of group CMSIS_DWT */ - - -/** \ingroup CMSIS_core_register - \defgroup CMSIS_TPI Trace Port Interface (TPI) - \brief Type definitions for the Trace Port Interface (TPI) - @{ - */ - -/** \brief Structure type to access the Trace Port Interface Register (TPI). - */ -typedef struct { - __IO uint32_t SSPSR; /*!< Offset: 0x000 (R/ ) Supported Parallel Port Size Register */ - __IO uint32_t CSPSR; /*!< Offset: 0x004 (R/W) Current Parallel Port Size Register */ - uint32_t RESERVED0[2]; - __IO uint32_t ACPR; /*!< Offset: 0x010 (R/W) Asynchronous Clock Prescaler Register */ - uint32_t RESERVED1[55]; - __IO uint32_t SPPR; /*!< Offset: 0x0F0 (R/W) Selected Pin Protocol Register */ - uint32_t RESERVED2[131]; - __I uint32_t FFSR; /*!< Offset: 0x300 (R/ ) Formatter and Flush Status Register */ - __IO uint32_t FFCR; /*!< Offset: 0x304 (R/W) Formatter and Flush Control Register */ - __I uint32_t FSCR; /*!< Offset: 0x308 (R/ ) Formatter Synchronization Counter Register */ - uint32_t RESERVED3[759]; - __I uint32_t TRIGGER; /*!< Offset: 0xEE8 (R/ ) TRIGGER */ - __I uint32_t FIFO0; /*!< Offset: 0xEEC (R/ ) Integration ETM Data */ - __I uint32_t ITATBCTR2; /*!< Offset: 0xEF0 (R/ ) ITATBCTR2 */ - uint32_t RESERVED4[1]; - __I uint32_t ITATBCTR0; /*!< Offset: 0xEF8 (R/ ) ITATBCTR0 */ - __I uint32_t FIFO1; /*!< Offset: 0xEFC (R/ ) Integration ITM Data */ - __IO uint32_t ITCTRL; /*!< Offset: 0xF00 (R/W) Integration Mode Control */ - uint32_t RESERVED5[39]; - __IO uint32_t CLAIMSET; /*!< Offset: 0xFA0 (R/W) Claim tag set */ - __IO uint32_t CLAIMCLR; /*!< Offset: 0xFA4 (R/W) Claim tag clear */ - uint32_t RESERVED7[8]; - __I uint32_t DEVID; /*!< Offset: 0xFC8 (R/ ) TPIU_DEVID */ - __I uint32_t DEVTYPE; /*!< Offset: 0xFCC (R/ ) TPIU_DEVTYPE */ -} TPI_Type; - -/* TPI Asynchronous Clock Prescaler Register Definitions */ -#define TPI_ACPR_PRESCALER_Pos 0 /*!< TPI ACPR: PRESCALER Position */ -#define TPI_ACPR_PRESCALER_Msk (0x1FFFUL << TPI_ACPR_PRESCALER_Pos) /*!< TPI ACPR: PRESCALER Mask */ - -/* TPI Selected Pin Protocol Register Definitions */ -#define TPI_SPPR_TXMODE_Pos 0 /*!< TPI SPPR: TXMODE Position */ -#define TPI_SPPR_TXMODE_Msk (0x3UL << TPI_SPPR_TXMODE_Pos) /*!< TPI SPPR: TXMODE Mask */ - -/* TPI Formatter and Flush Status Register Definitions */ -#define TPI_FFSR_FtNonStop_Pos 3 /*!< TPI FFSR: FtNonStop Position */ -#define TPI_FFSR_FtNonStop_Msk (0x1UL << TPI_FFSR_FtNonStop_Pos) /*!< TPI FFSR: FtNonStop Mask */ - -#define TPI_FFSR_TCPresent_Pos 2 /*!< TPI FFSR: TCPresent Position */ -#define TPI_FFSR_TCPresent_Msk (0x1UL << TPI_FFSR_TCPresent_Pos) /*!< TPI FFSR: TCPresent Mask */ - -#define TPI_FFSR_FtStopped_Pos 1 /*!< TPI FFSR: FtStopped Position */ -#define TPI_FFSR_FtStopped_Msk (0x1UL << TPI_FFSR_FtStopped_Pos) /*!< TPI FFSR: FtStopped Mask */ - -#define TPI_FFSR_FlInProg_Pos 0 /*!< TPI FFSR: FlInProg Position */ -#define TPI_FFSR_FlInProg_Msk (0x1UL << TPI_FFSR_FlInProg_Pos) /*!< TPI FFSR: FlInProg Mask */ - -/* TPI Formatter and Flush Control Register Definitions */ -#define TPI_FFCR_TrigIn_Pos 8 /*!< TPI FFCR: TrigIn Position */ -#define TPI_FFCR_TrigIn_Msk (0x1UL << TPI_FFCR_TrigIn_Pos) /*!< TPI FFCR: TrigIn Mask */ - -#define TPI_FFCR_EnFCont_Pos 1 /*!< TPI FFCR: EnFCont Position */ -#define TPI_FFCR_EnFCont_Msk (0x1UL << TPI_FFCR_EnFCont_Pos) /*!< TPI FFCR: EnFCont Mask */ - -/* TPI TRIGGER Register Definitions */ -#define TPI_TRIGGER_TRIGGER_Pos 0 /*!< TPI TRIGGER: TRIGGER Position */ -#define TPI_TRIGGER_TRIGGER_Msk (0x1UL << TPI_TRIGGER_TRIGGER_Pos) /*!< TPI TRIGGER: TRIGGER Mask */ - -/* TPI Integration ETM Data Register Definitions (FIFO0) */ -#define TPI_FIFO0_ITM_ATVALID_Pos 29 /*!< TPI FIFO0: ITM_ATVALID Position */ -#define TPI_FIFO0_ITM_ATVALID_Msk (0x3UL << TPI_FIFO0_ITM_ATVALID_Pos) /*!< TPI FIFO0: ITM_ATVALID Mask */ - -#define TPI_FIFO0_ITM_bytecount_Pos 27 /*!< TPI FIFO0: ITM_bytecount Position */ -#define TPI_FIFO0_ITM_bytecount_Msk (0x3UL << TPI_FIFO0_ITM_bytecount_Pos) /*!< TPI FIFO0: ITM_bytecount Mask */ - -#define TPI_FIFO0_ETM_ATVALID_Pos 26 /*!< TPI FIFO0: ETM_ATVALID Position */ -#define TPI_FIFO0_ETM_ATVALID_Msk (0x3UL << TPI_FIFO0_ETM_ATVALID_Pos) /*!< TPI FIFO0: ETM_ATVALID Mask */ - -#define TPI_FIFO0_ETM_bytecount_Pos 24 /*!< TPI FIFO0: ETM_bytecount Position */ -#define TPI_FIFO0_ETM_bytecount_Msk (0x3UL << TPI_FIFO0_ETM_bytecount_Pos) /*!< TPI FIFO0: ETM_bytecount Mask */ - -#define TPI_FIFO0_ETM2_Pos 16 /*!< TPI FIFO0: ETM2 Position */ -#define TPI_FIFO0_ETM2_Msk (0xFFUL << TPI_FIFO0_ETM2_Pos) /*!< TPI FIFO0: ETM2 Mask */ - -#define TPI_FIFO0_ETM1_Pos 8 /*!< TPI FIFO0: ETM1 Position */ -#define TPI_FIFO0_ETM1_Msk (0xFFUL << TPI_FIFO0_ETM1_Pos) /*!< TPI FIFO0: ETM1 Mask */ - -#define TPI_FIFO0_ETM0_Pos 0 /*!< TPI FIFO0: ETM0 Position */ -#define TPI_FIFO0_ETM0_Msk (0xFFUL << TPI_FIFO0_ETM0_Pos) /*!< TPI FIFO0: ETM0 Mask */ - -/* TPI ITATBCTR2 Register Definitions */ -#define TPI_ITATBCTR2_ATREADY_Pos 0 /*!< TPI ITATBCTR2: ATREADY Position */ -#define TPI_ITATBCTR2_ATREADY_Msk (0x1UL << TPI_ITATBCTR2_ATREADY_Pos) /*!< TPI ITATBCTR2: ATREADY Mask */ - -/* TPI Integration ITM Data Register Definitions (FIFO1) */ -#define TPI_FIFO1_ITM_ATVALID_Pos 29 /*!< TPI FIFO1: ITM_ATVALID Position */ -#define TPI_FIFO1_ITM_ATVALID_Msk (0x3UL << TPI_FIFO1_ITM_ATVALID_Pos) /*!< TPI FIFO1: ITM_ATVALID Mask */ - -#define TPI_FIFO1_ITM_bytecount_Pos 27 /*!< TPI FIFO1: ITM_bytecount Position */ -#define TPI_FIFO1_ITM_bytecount_Msk (0x3UL << TPI_FIFO1_ITM_bytecount_Pos) /*!< TPI FIFO1: ITM_bytecount Mask */ - -#define TPI_FIFO1_ETM_ATVALID_Pos 26 /*!< TPI FIFO1: ETM_ATVALID Position */ -#define TPI_FIFO1_ETM_ATVALID_Msk (0x3UL << TPI_FIFO1_ETM_ATVALID_Pos) /*!< TPI FIFO1: ETM_ATVALID Mask */ - -#define TPI_FIFO1_ETM_bytecount_Pos 24 /*!< TPI FIFO1: ETM_bytecount Position */ -#define TPI_FIFO1_ETM_bytecount_Msk (0x3UL << TPI_FIFO1_ETM_bytecount_Pos) /*!< TPI FIFO1: ETM_bytecount Mask */ - -#define TPI_FIFO1_ITM2_Pos 16 /*!< TPI FIFO1: ITM2 Position */ -#define TPI_FIFO1_ITM2_Msk (0xFFUL << TPI_FIFO1_ITM2_Pos) /*!< TPI FIFO1: ITM2 Mask */ - -#define TPI_FIFO1_ITM1_Pos 8 /*!< TPI FIFO1: ITM1 Position */ -#define TPI_FIFO1_ITM1_Msk (0xFFUL << TPI_FIFO1_ITM1_Pos) /*!< TPI FIFO1: ITM1 Mask */ - -#define TPI_FIFO1_ITM0_Pos 0 /*!< TPI FIFO1: ITM0 Position */ -#define TPI_FIFO1_ITM0_Msk (0xFFUL << TPI_FIFO1_ITM0_Pos) /*!< TPI FIFO1: ITM0 Mask */ - -/* TPI ITATBCTR0 Register Definitions */ -#define TPI_ITATBCTR0_ATREADY_Pos 0 /*!< TPI ITATBCTR0: ATREADY Position */ -#define TPI_ITATBCTR0_ATREADY_Msk (0x1UL << TPI_ITATBCTR0_ATREADY_Pos) /*!< TPI ITATBCTR0: ATREADY Mask */ - -/* TPI Integration Mode Control Register Definitions */ -#define TPI_ITCTRL_Mode_Pos 0 /*!< TPI ITCTRL: Mode Position */ -#define TPI_ITCTRL_Mode_Msk (0x1UL << TPI_ITCTRL_Mode_Pos) /*!< TPI ITCTRL: Mode Mask */ - -/* TPI DEVID Register Definitions */ -#define TPI_DEVID_NRZVALID_Pos 11 /*!< TPI DEVID: NRZVALID Position */ -#define TPI_DEVID_NRZVALID_Msk (0x1UL << TPI_DEVID_NRZVALID_Pos) /*!< TPI DEVID: NRZVALID Mask */ - -#define TPI_DEVID_MANCVALID_Pos 10 /*!< TPI DEVID: MANCVALID Position */ -#define TPI_DEVID_MANCVALID_Msk (0x1UL << TPI_DEVID_MANCVALID_Pos) /*!< TPI DEVID: MANCVALID Mask */ - -#define TPI_DEVID_PTINVALID_Pos 9 /*!< TPI DEVID: PTINVALID Position */ -#define TPI_DEVID_PTINVALID_Msk (0x1UL << TPI_DEVID_PTINVALID_Pos) /*!< TPI DEVID: PTINVALID Mask */ - -#define TPI_DEVID_MinBufSz_Pos 6 /*!< TPI DEVID: MinBufSz Position */ -#define TPI_DEVID_MinBufSz_Msk (0x7UL << TPI_DEVID_MinBufSz_Pos) /*!< TPI DEVID: MinBufSz Mask */ - -#define TPI_DEVID_AsynClkIn_Pos 5 /*!< TPI DEVID: AsynClkIn Position */ -#define TPI_DEVID_AsynClkIn_Msk (0x1UL << TPI_DEVID_AsynClkIn_Pos) /*!< TPI DEVID: AsynClkIn Mask */ - -#define TPI_DEVID_NrTraceInput_Pos 0 /*!< TPI DEVID: NrTraceInput Position */ -#define TPI_DEVID_NrTraceInput_Msk (0x1FUL << TPI_DEVID_NrTraceInput_Pos) /*!< TPI DEVID: NrTraceInput Mask */ - -/* TPI DEVTYPE Register Definitions */ -#define TPI_DEVTYPE_SubType_Pos 0 /*!< TPI DEVTYPE: SubType Position */ -#define TPI_DEVTYPE_SubType_Msk (0xFUL << TPI_DEVTYPE_SubType_Pos) /*!< TPI DEVTYPE: SubType Mask */ - -#define TPI_DEVTYPE_MajorType_Pos 4 /*!< TPI DEVTYPE: MajorType Position */ -#define TPI_DEVTYPE_MajorType_Msk (0xFUL << TPI_DEVTYPE_MajorType_Pos) /*!< TPI DEVTYPE: MajorType Mask */ - -/*@}*/ /* end of group CMSIS_TPI */ - - -#if (__MPU_PRESENT == 1) -/** \ingroup CMSIS_core_register - \defgroup CMSIS_MPU Memory Protection Unit (MPU) - \brief Type definitions for the Memory Protection Unit (MPU) - @{ - */ - -/** \brief Structure type to access the Memory Protection Unit (MPU). - */ -typedef struct { - __I uint32_t TYPE; /*!< Offset: 0x000 (R/ ) MPU Type Register */ - __IO uint32_t CTRL; /*!< Offset: 0x004 (R/W) MPU Control Register */ - __IO uint32_t RNR; /*!< Offset: 0x008 (R/W) MPU Region RNRber Register */ - __IO uint32_t RBAR; /*!< Offset: 0x00C (R/W) MPU Region Base Address Register */ - __IO uint32_t RASR; /*!< Offset: 0x010 (R/W) MPU Region Attribute and Size Register */ - __IO uint32_t RBAR_A1; /*!< Offset: 0x014 (R/W) MPU Alias 1 Region Base Address Register */ - __IO uint32_t RASR_A1; /*!< Offset: 0x018 (R/W) MPU Alias 1 Region Attribute and Size Register */ - __IO uint32_t RBAR_A2; /*!< Offset: 0x01C (R/W) MPU Alias 2 Region Base Address Register */ - __IO uint32_t RASR_A2; /*!< Offset: 0x020 (R/W) MPU Alias 2 Region Attribute and Size Register */ - __IO uint32_t RBAR_A3; /*!< Offset: 0x024 (R/W) MPU Alias 3 Region Base Address Register */ - __IO uint32_t RASR_A3; /*!< Offset: 0x028 (R/W) MPU Alias 3 Region Attribute and Size Register */ -} MPU_Type; - -/* MPU Type Register */ -#define MPU_TYPE_IREGION_Pos 16 /*!< MPU TYPE: IREGION Position */ -#define MPU_TYPE_IREGION_Msk (0xFFUL << MPU_TYPE_IREGION_Pos) /*!< MPU TYPE: IREGION Mask */ - -#define MPU_TYPE_DREGION_Pos 8 /*!< MPU TYPE: DREGION Position */ -#define MPU_TYPE_DREGION_Msk (0xFFUL << MPU_TYPE_DREGION_Pos) /*!< MPU TYPE: DREGION Mask */ - -#define MPU_TYPE_SEPARATE_Pos 0 /*!< MPU TYPE: SEPARATE Position */ -#define MPU_TYPE_SEPARATE_Msk (1UL << MPU_TYPE_SEPARATE_Pos) /*!< MPU TYPE: SEPARATE Mask */ - -/* MPU Control Register */ -#define MPU_CTRL_PRIVDEFENA_Pos 2 /*!< MPU CTRL: PRIVDEFENA Position */ -#define MPU_CTRL_PRIVDEFENA_Msk (1UL << MPU_CTRL_PRIVDEFENA_Pos) /*!< MPU CTRL: PRIVDEFENA Mask */ - -#define MPU_CTRL_HFNMIENA_Pos 1 /*!< MPU CTRL: HFNMIENA Position */ -#define MPU_CTRL_HFNMIENA_Msk (1UL << MPU_CTRL_HFNMIENA_Pos) /*!< MPU CTRL: HFNMIENA Mask */ - -#define MPU_CTRL_ENABLE_Pos 0 /*!< MPU CTRL: ENABLE Position */ -#define MPU_CTRL_ENABLE_Msk (1UL << MPU_CTRL_ENABLE_Pos) /*!< MPU CTRL: ENABLE Mask */ - -/* MPU Region Number Register */ -#define MPU_RNR_REGION_Pos 0 /*!< MPU RNR: REGION Position */ -#define MPU_RNR_REGION_Msk (0xFFUL << MPU_RNR_REGION_Pos) /*!< MPU RNR: REGION Mask */ - -/* MPU Region Base Address Register */ -#define MPU_RBAR_ADDR_Pos 5 /*!< MPU RBAR: ADDR Position */ -#define MPU_RBAR_ADDR_Msk (0x7FFFFFFUL << MPU_RBAR_ADDR_Pos) /*!< MPU RBAR: ADDR Mask */ - -#define MPU_RBAR_VALID_Pos 4 /*!< MPU RBAR: VALID Position */ -#define MPU_RBAR_VALID_Msk (1UL << MPU_RBAR_VALID_Pos) /*!< MPU RBAR: VALID Mask */ - -#define MPU_RBAR_REGION_Pos 0 /*!< MPU RBAR: REGION Position */ -#define MPU_RBAR_REGION_Msk (0xFUL << MPU_RBAR_REGION_Pos) /*!< MPU RBAR: REGION Mask */ - -/* MPU Region Attribute and Size Register */ -#define MPU_RASR_ATTRS_Pos 16 /*!< MPU RASR: MPU Region Attribute field Position */ -#define MPU_RASR_ATTRS_Msk (0xFFFFUL << MPU_RASR_ATTRS_Pos) /*!< MPU RASR: MPU Region Attribute field Mask */ - -#define MPU_RASR_XN_Pos 28 /*!< MPU RASR: ATTRS.XN Position */ -#define MPU_RASR_XN_Msk (1UL << MPU_RASR_XN_Pos) /*!< MPU RASR: ATTRS.XN Mask */ - -#define MPU_RASR_AP_Pos 24 /*!< MPU RASR: ATTRS.AP Position */ -#define MPU_RASR_AP_Msk (0x7UL << MPU_RASR_AP_Pos) /*!< MPU RASR: ATTRS.AP Mask */ - -#define MPU_RASR_TEX_Pos 19 /*!< MPU RASR: ATTRS.TEX Position */ -#define MPU_RASR_TEX_Msk (0x7UL << MPU_RASR_TEX_Pos) /*!< MPU RASR: ATTRS.TEX Mask */ - -#define MPU_RASR_S_Pos 18 /*!< MPU RASR: ATTRS.S Position */ -#define MPU_RASR_S_Msk (1UL << MPU_RASR_S_Pos) /*!< MPU RASR: ATTRS.S Mask */ - -#define MPU_RASR_C_Pos 17 /*!< MPU RASR: ATTRS.C Position */ -#define MPU_RASR_C_Msk (1UL << MPU_RASR_C_Pos) /*!< MPU RASR: ATTRS.C Mask */ - -#define MPU_RASR_B_Pos 16 /*!< MPU RASR: ATTRS.B Position */ -#define MPU_RASR_B_Msk (1UL << MPU_RASR_B_Pos) /*!< MPU RASR: ATTRS.B Mask */ - -#define MPU_RASR_SRD_Pos 8 /*!< MPU RASR: Sub-Region Disable Position */ -#define MPU_RASR_SRD_Msk (0xFFUL << MPU_RASR_SRD_Pos) /*!< MPU RASR: Sub-Region Disable Mask */ - -#define MPU_RASR_SIZE_Pos 1 /*!< MPU RASR: Region Size Field Position */ -#define MPU_RASR_SIZE_Msk (0x1FUL << MPU_RASR_SIZE_Pos) /*!< MPU RASR: Region Size Field Mask */ - -#define MPU_RASR_ENABLE_Pos 0 /*!< MPU RASR: Region enable bit Position */ -#define MPU_RASR_ENABLE_Msk (1UL << MPU_RASR_ENABLE_Pos) /*!< MPU RASR: Region enable bit Disable Mask */ - -/*@} end of group CMSIS_MPU */ -#endif - - -/** \ingroup CMSIS_core_register - \defgroup CMSIS_CoreDebug Core Debug Registers (CoreDebug) - \brief Type definitions for the Core Debug Registers - @{ - */ - -/** \brief Structure type to access the Core Debug Register (CoreDebug). - */ -typedef struct { - __IO uint32_t DHCSR; /*!< Offset: 0x000 (R/W) Debug Halting Control and Status Register */ - __O uint32_t DCRSR; /*!< Offset: 0x004 ( /W) Debug Core Register Selector Register */ - __IO uint32_t DCRDR; /*!< Offset: 0x008 (R/W) Debug Core Register Data Register */ - __IO uint32_t DEMCR; /*!< Offset: 0x00C (R/W) Debug Exception and Monitor Control Register */ -} CoreDebug_Type; - -/* Debug Halting Control and Status Register */ -#define CoreDebug_DHCSR_DBGKEY_Pos 16 /*!< CoreDebug DHCSR: DBGKEY Position */ -#define CoreDebug_DHCSR_DBGKEY_Msk (0xFFFFUL << CoreDebug_DHCSR_DBGKEY_Pos) /*!< CoreDebug DHCSR: DBGKEY Mask */ - -#define CoreDebug_DHCSR_S_RESET_ST_Pos 25 /*!< CoreDebug DHCSR: S_RESET_ST Position */ -#define CoreDebug_DHCSR_S_RESET_ST_Msk (1UL << CoreDebug_DHCSR_S_RESET_ST_Pos) /*!< CoreDebug DHCSR: S_RESET_ST Mask */ - -#define CoreDebug_DHCSR_S_RETIRE_ST_Pos 24 /*!< CoreDebug DHCSR: S_RETIRE_ST Position */ -#define CoreDebug_DHCSR_S_RETIRE_ST_Msk (1UL << CoreDebug_DHCSR_S_RETIRE_ST_Pos) /*!< CoreDebug DHCSR: S_RETIRE_ST Mask */ - -#define CoreDebug_DHCSR_S_LOCKUP_Pos 19 /*!< CoreDebug DHCSR: S_LOCKUP Position */ -#define CoreDebug_DHCSR_S_LOCKUP_Msk (1UL << CoreDebug_DHCSR_S_LOCKUP_Pos) /*!< CoreDebug DHCSR: S_LOCKUP Mask */ - -#define CoreDebug_DHCSR_S_SLEEP_Pos 18 /*!< CoreDebug DHCSR: S_SLEEP Position */ -#define CoreDebug_DHCSR_S_SLEEP_Msk (1UL << CoreDebug_DHCSR_S_SLEEP_Pos) /*!< CoreDebug DHCSR: S_SLEEP Mask */ - -#define CoreDebug_DHCSR_S_HALT_Pos 17 /*!< CoreDebug DHCSR: S_HALT Position */ -#define CoreDebug_DHCSR_S_HALT_Msk (1UL << CoreDebug_DHCSR_S_HALT_Pos) /*!< CoreDebug DHCSR: S_HALT Mask */ - -#define CoreDebug_DHCSR_S_REGRDY_Pos 16 /*!< CoreDebug DHCSR: S_REGRDY Position */ -#define CoreDebug_DHCSR_S_REGRDY_Msk (1UL << CoreDebug_DHCSR_S_REGRDY_Pos) /*!< CoreDebug DHCSR: S_REGRDY Mask */ - -#define CoreDebug_DHCSR_C_SNAPSTALL_Pos 5 /*!< CoreDebug DHCSR: C_SNAPSTALL Position */ -#define CoreDebug_DHCSR_C_SNAPSTALL_Msk (1UL << CoreDebug_DHCSR_C_SNAPSTALL_Pos) /*!< CoreDebug DHCSR: C_SNAPSTALL Mask */ - -#define CoreDebug_DHCSR_C_MASKINTS_Pos 3 /*!< CoreDebug DHCSR: C_MASKINTS Position */ -#define CoreDebug_DHCSR_C_MASKINTS_Msk (1UL << CoreDebug_DHCSR_C_MASKINTS_Pos) /*!< CoreDebug DHCSR: C_MASKINTS Mask */ - -#define CoreDebug_DHCSR_C_STEP_Pos 2 /*!< CoreDebug DHCSR: C_STEP Position */ -#define CoreDebug_DHCSR_C_STEP_Msk (1UL << CoreDebug_DHCSR_C_STEP_Pos) /*!< CoreDebug DHCSR: C_STEP Mask */ - -#define CoreDebug_DHCSR_C_HALT_Pos 1 /*!< CoreDebug DHCSR: C_HALT Position */ -#define CoreDebug_DHCSR_C_HALT_Msk (1UL << CoreDebug_DHCSR_C_HALT_Pos) /*!< CoreDebug DHCSR: C_HALT Mask */ - -#define CoreDebug_DHCSR_C_DEBUGEN_Pos 0 /*!< CoreDebug DHCSR: C_DEBUGEN Position */ -#define CoreDebug_DHCSR_C_DEBUGEN_Msk (1UL << CoreDebug_DHCSR_C_DEBUGEN_Pos) /*!< CoreDebug DHCSR: C_DEBUGEN Mask */ - -/* Debug Core Register Selector Register */ -#define CoreDebug_DCRSR_REGWnR_Pos 16 /*!< CoreDebug DCRSR: REGWnR Position */ -#define CoreDebug_DCRSR_REGWnR_Msk (1UL << CoreDebug_DCRSR_REGWnR_Pos) /*!< CoreDebug DCRSR: REGWnR Mask */ - -#define CoreDebug_DCRSR_REGSEL_Pos 0 /*!< CoreDebug DCRSR: REGSEL Position */ -#define CoreDebug_DCRSR_REGSEL_Msk (0x1FUL << CoreDebug_DCRSR_REGSEL_Pos) /*!< CoreDebug DCRSR: REGSEL Mask */ - -/* Debug Exception and Monitor Control Register */ -#define CoreDebug_DEMCR_TRCENA_Pos 24 /*!< CoreDebug DEMCR: TRCENA Position */ -#define CoreDebug_DEMCR_TRCENA_Msk (1UL << CoreDebug_DEMCR_TRCENA_Pos) /*!< CoreDebug DEMCR: TRCENA Mask */ - -#define CoreDebug_DEMCR_MON_REQ_Pos 19 /*!< CoreDebug DEMCR: MON_REQ Position */ -#define CoreDebug_DEMCR_MON_REQ_Msk (1UL << CoreDebug_DEMCR_MON_REQ_Pos) /*!< CoreDebug DEMCR: MON_REQ Mask */ - -#define CoreDebug_DEMCR_MON_STEP_Pos 18 /*!< CoreDebug DEMCR: MON_STEP Position */ -#define CoreDebug_DEMCR_MON_STEP_Msk (1UL << CoreDebug_DEMCR_MON_STEP_Pos) /*!< CoreDebug DEMCR: MON_STEP Mask */ - -#define CoreDebug_DEMCR_MON_PEND_Pos 17 /*!< CoreDebug DEMCR: MON_PEND Position */ -#define CoreDebug_DEMCR_MON_PEND_Msk (1UL << CoreDebug_DEMCR_MON_PEND_Pos) /*!< CoreDebug DEMCR: MON_PEND Mask */ - -#define CoreDebug_DEMCR_MON_EN_Pos 16 /*!< CoreDebug DEMCR: MON_EN Position */ -#define CoreDebug_DEMCR_MON_EN_Msk (1UL << CoreDebug_DEMCR_MON_EN_Pos) /*!< CoreDebug DEMCR: MON_EN Mask */ - -#define CoreDebug_DEMCR_VC_HARDERR_Pos 10 /*!< CoreDebug DEMCR: VC_HARDERR Position */ -#define CoreDebug_DEMCR_VC_HARDERR_Msk (1UL << CoreDebug_DEMCR_VC_HARDERR_Pos) /*!< CoreDebug DEMCR: VC_HARDERR Mask */ - -#define CoreDebug_DEMCR_VC_INTERR_Pos 9 /*!< CoreDebug DEMCR: VC_INTERR Position */ -#define CoreDebug_DEMCR_VC_INTERR_Msk (1UL << CoreDebug_DEMCR_VC_INTERR_Pos) /*!< CoreDebug DEMCR: VC_INTERR Mask */ - -#define CoreDebug_DEMCR_VC_BUSERR_Pos 8 /*!< CoreDebug DEMCR: VC_BUSERR Position */ -#define CoreDebug_DEMCR_VC_BUSERR_Msk (1UL << CoreDebug_DEMCR_VC_BUSERR_Pos) /*!< CoreDebug DEMCR: VC_BUSERR Mask */ - -#define CoreDebug_DEMCR_VC_STATERR_Pos 7 /*!< CoreDebug DEMCR: VC_STATERR Position */ -#define CoreDebug_DEMCR_VC_STATERR_Msk (1UL << CoreDebug_DEMCR_VC_STATERR_Pos) /*!< CoreDebug DEMCR: VC_STATERR Mask */ - -#define CoreDebug_DEMCR_VC_CHKERR_Pos 6 /*!< CoreDebug DEMCR: VC_CHKERR Position */ -#define CoreDebug_DEMCR_VC_CHKERR_Msk (1UL << CoreDebug_DEMCR_VC_CHKERR_Pos) /*!< CoreDebug DEMCR: VC_CHKERR Mask */ - -#define CoreDebug_DEMCR_VC_NOCPERR_Pos 5 /*!< CoreDebug DEMCR: VC_NOCPERR Position */ -#define CoreDebug_DEMCR_VC_NOCPERR_Msk (1UL << CoreDebug_DEMCR_VC_NOCPERR_Pos) /*!< CoreDebug DEMCR: VC_NOCPERR Mask */ - -#define CoreDebug_DEMCR_VC_MMERR_Pos 4 /*!< CoreDebug DEMCR: VC_MMERR Position */ -#define CoreDebug_DEMCR_VC_MMERR_Msk (1UL << CoreDebug_DEMCR_VC_MMERR_Pos) /*!< CoreDebug DEMCR: VC_MMERR Mask */ - -#define CoreDebug_DEMCR_VC_CORERESET_Pos 0 /*!< CoreDebug DEMCR: VC_CORERESET Position */ -#define CoreDebug_DEMCR_VC_CORERESET_Msk (1UL << CoreDebug_DEMCR_VC_CORERESET_Pos) /*!< CoreDebug DEMCR: VC_CORERESET Mask */ - -/*@} end of group CMSIS_CoreDebug */ - - -/** \ingroup CMSIS_core_register - \defgroup CMSIS_core_base Core Definitions - \brief Definitions for base addresses, unions, and structures. - @{ - */ - -/* Memory mapping of Cortex-M3 Hardware */ -#define SCS_BASE (0xE000E000UL) /*!< System Control Space Base Address */ -#define ITM_BASE (0xE0000000UL) /*!< ITM Base Address */ -#define DWT_BASE (0xE0001000UL) /*!< DWT Base Address */ -#define TPI_BASE (0xE0040000UL) /*!< TPI Base Address */ -#define CoreDebug_BASE (0xE000EDF0UL) /*!< Core Debug Base Address */ -#define SysTick_BASE (SCS_BASE + 0x0010UL) /*!< SysTick Base Address */ -#define NVIC_BASE (SCS_BASE + 0x0100UL) /*!< NVIC Base Address */ -#define SCB_BASE (SCS_BASE + 0x0D00UL) /*!< System Control Block Base Address */ - -#define SCnSCB ((SCnSCB_Type *) SCS_BASE ) /*!< System control Register not in SCB */ -#define SCB ((SCB_Type *) SCB_BASE ) /*!< SCB configuration struct */ -#define SysTick ((SysTick_Type *) SysTick_BASE ) /*!< SysTick configuration struct */ -#define NVIC ((NVIC_Type *) NVIC_BASE ) /*!< NVIC configuration struct */ -#define ITM ((ITM_Type *) ITM_BASE ) /*!< ITM configuration struct */ -#define DWT ((DWT_Type *) DWT_BASE ) /*!< DWT configuration struct */ -#define TPI ((TPI_Type *) TPI_BASE ) /*!< TPI configuration struct */ -#define CoreDebug ((CoreDebug_Type *) CoreDebug_BASE) /*!< Core Debug configuration struct */ - -#if (__MPU_PRESENT == 1) -#define MPU_BASE (SCS_BASE + 0x0D90UL) /*!< Memory Protection Unit */ -#define MPU ((MPU_Type *) MPU_BASE ) /*!< Memory Protection Unit */ -#endif - -/*@} */ - - - -/******************************************************************************* - * Hardware Abstraction Layer - Core Function Interface contains: - - Core NVIC Functions - - Core SysTick Functions - - Core Debug Functions - - Core Register Access Functions - ******************************************************************************/ -/** \defgroup CMSIS_Core_FunctionInterface Functions and Instructions Reference -*/ - - - -/* ########################## NVIC functions #################################### */ -/** \ingroup CMSIS_Core_FunctionInterface - \defgroup CMSIS_Core_NVICFunctions NVIC Functions - \brief Functions that manage interrupts and exceptions via the NVIC. - @{ - */ - -/** \brief Set Priority Grouping - - The function sets the priority grouping field using the required unlock sequence. - The parameter PriorityGroup is assigned to the field SCB->AIRCR [10:8] PRIGROUP field. - Only values from 0..7 are used. - In case of a conflict between priority grouping and available - priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set. - - \param [in] PriorityGroup Priority grouping field. - */ -__STATIC_INLINE void NVIC_SetPriorityGrouping(uint32_t PriorityGroup) -{ - uint32_t reg_value; - uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07); /* only values 0..7 are used */ - - reg_value = SCB->AIRCR; /* read old register configuration */ - reg_value &= ~(SCB_AIRCR_VECTKEY_Msk | SCB_AIRCR_PRIGROUP_Msk); /* clear bits to change */ - reg_value = (reg_value | - ((uint32_t)0x5FA << SCB_AIRCR_VECTKEY_Pos) | - (PriorityGroupTmp << 8)); /* Insert write key and priorty group */ - SCB->AIRCR = reg_value; -} - - -/** \brief Get Priority Grouping - - The function reads the priority grouping field from the NVIC Interrupt Controller. - - \return Priority grouping field (SCB->AIRCR [10:8] PRIGROUP field). - */ -__STATIC_INLINE uint32_t NVIC_GetPriorityGrouping(void) -{ - return ((SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) >> SCB_AIRCR_PRIGROUP_Pos); /* read priority grouping field */ -} - - -/** \brief Enable External Interrupt - - The function enables a device-specific interrupt in the NVIC interrupt controller. - - \param [in] IRQn External interrupt number. Value cannot be negative. - */ -__STATIC_INLINE void NVIC_EnableIRQ(IRQn_Type IRQn) -{ - NVIC->ISER[((uint32_t)(IRQn) >> 5)] = (1 << ((uint32_t)(IRQn) & 0x1F)); /* enable interrupt */ -} - - -/** \brief Disable External Interrupt - - The function disables a device-specific interrupt in the NVIC interrupt controller. - - \param [in] IRQn External interrupt number. Value cannot be negative. - */ -__STATIC_INLINE void NVIC_DisableIRQ(IRQn_Type IRQn) -{ - NVIC->ICER[((uint32_t)(IRQn) >> 5)] = (1 << ((uint32_t)(IRQn) & 0x1F)); /* disable interrupt */ -} - - -/** \brief Get Pending Interrupt - - The function reads the pending register in the NVIC and returns the pending bit - for the specified interrupt. - - \param [in] IRQn Interrupt number. - - \return 0 Interrupt status is not pending. - \return 1 Interrupt status is pending. - */ -__STATIC_INLINE uint32_t NVIC_GetPendingIRQ(IRQn_Type IRQn) -{ - return ((uint32_t)((NVIC->ISPR[(uint32_t)(IRQn) >> 5] & (1 << ((uint32_t)(IRQn) & 0x1F))) ? 1 : 0)); /* Return 1 if pending else 0 */ -} - - -/** \brief Set Pending Interrupt - - The function sets the pending bit of an external interrupt. - - \param [in] IRQn Interrupt number. Value cannot be negative. - */ -__STATIC_INLINE void NVIC_SetPendingIRQ(IRQn_Type IRQn) -{ - NVIC->ISPR[((uint32_t)(IRQn) >> 5)] = (1 << ((uint32_t)(IRQn) & 0x1F)); /* set interrupt pending */ -} - - -/** \brief Clear Pending Interrupt - - The function clears the pending bit of an external interrupt. - - \param [in] IRQn External interrupt number. Value cannot be negative. - */ -__STATIC_INLINE void NVIC_ClearPendingIRQ(IRQn_Type IRQn) -{ - NVIC->ICPR[((uint32_t)(IRQn) >> 5)] = (1 << ((uint32_t)(IRQn) & 0x1F)); /* Clear pending interrupt */ -} - - -/** \brief Get Active Interrupt - - The function reads the active register in NVIC and returns the active bit. - - \param [in] IRQn Interrupt number. - - \return 0 Interrupt status is not active. - \return 1 Interrupt status is active. - */ -__STATIC_INLINE uint32_t NVIC_GetActive(IRQn_Type IRQn) -{ - return ((uint32_t)((NVIC->IABR[(uint32_t)(IRQn) >> 5] & (1 << ((uint32_t)(IRQn) & 0x1F))) ? 1 : 0)); /* Return 1 if active else 0 */ -} - - -/** \brief Set Interrupt Priority - - The function sets the priority of an interrupt. - - \note The priority cannot be set for every core interrupt. - - \param [in] IRQn Interrupt number. - \param [in] priority Priority to set. - */ -__STATIC_INLINE void NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority) -{ - if (IRQn < 0) { - SCB->SHP[((uint32_t)(IRQn) & 0xF) - 4] = ((priority << (8 - __NVIC_PRIO_BITS)) & 0xff); - } /* set Priority for Cortex-M System Interrupts */ - else { - NVIC->IP[(uint32_t)(IRQn)] = ((priority << (8 - __NVIC_PRIO_BITS)) & 0xff); - } /* set Priority for device specific Interrupts */ -} - - -/** \brief Get Interrupt Priority - - The function reads the priority of an interrupt. The interrupt - number can be positive to specify an external (device specific) - interrupt, or negative to specify an internal (core) interrupt. - - - \param [in] IRQn Interrupt number. - \return Interrupt Priority. Value is aligned automatically to the implemented - priority bits of the microcontroller. - */ -__STATIC_INLINE uint32_t NVIC_GetPriority(IRQn_Type IRQn) -{ - - if (IRQn < 0) { - return ((uint32_t)(SCB->SHP[((uint32_t)(IRQn) & 0xF) - 4] >> (8 - __NVIC_PRIO_BITS))); - } /* get priority for Cortex-M system interrupts */ - else { - return ((uint32_t)(NVIC->IP[(uint32_t)(IRQn)] >> (8 - __NVIC_PRIO_BITS))); - } /* get priority for device specific interrupts */ -} - - -/** \brief Encode Priority - - The function encodes the priority for an interrupt with the given priority group, - preemptive priority value, and subpriority value. - In case of a conflict between priority grouping and available - priority bits (__NVIC_PRIO_BITS), the samllest possible priority group is set. - - \param [in] PriorityGroup Used priority group. - \param [in] PreemptPriority Preemptive priority value (starting from 0). - \param [in] SubPriority Subpriority value (starting from 0). - \return Encoded priority. Value can be used in the function \ref NVIC_SetPriority(). - */ -__STATIC_INLINE uint32_t NVIC_EncodePriority(uint32_t PriorityGroup, uint32_t PreemptPriority, uint32_t SubPriority) -{ - uint32_t PriorityGroupTmp = (PriorityGroup & 0x07); /* only values 0..7 are used */ - uint32_t PreemptPriorityBits; - uint32_t SubPriorityBits; - - PreemptPriorityBits = ((7 - PriorityGroupTmp) > __NVIC_PRIO_BITS) ? __NVIC_PRIO_BITS : 7 - PriorityGroupTmp; - SubPriorityBits = ((PriorityGroupTmp + __NVIC_PRIO_BITS) < 7) ? 0 : PriorityGroupTmp - 7 + __NVIC_PRIO_BITS; - - return ( - ((PreemptPriority & ((1 << (PreemptPriorityBits)) - 1)) << SubPriorityBits) | - ((SubPriority & ((1 << (SubPriorityBits)) - 1))) - ); -} - - -/** \brief Decode Priority - - The function decodes an interrupt priority value with a given priority group to - preemptive priority value and subpriority value. - In case of a conflict between priority grouping and available - priority bits (__NVIC_PRIO_BITS) the samllest possible priority group is set. - - \param [in] Priority Priority value, which can be retrieved with the function \ref NVIC_GetPriority(). - \param [in] PriorityGroup Used priority group. - \param [out] pPreemptPriority Preemptive priority value (starting from 0). - \param [out] pSubPriority Subpriority value (starting from 0). - */ -__STATIC_INLINE void NVIC_DecodePriority(uint32_t Priority, uint32_t PriorityGroup, uint32_t *pPreemptPriority, uint32_t *pSubPriority) -{ - uint32_t PriorityGroupTmp = (PriorityGroup & 0x07); /* only values 0..7 are used */ - uint32_t PreemptPriorityBits; - uint32_t SubPriorityBits; - - PreemptPriorityBits = ((7 - PriorityGroupTmp) > __NVIC_PRIO_BITS) ? __NVIC_PRIO_BITS : 7 - PriorityGroupTmp; - SubPriorityBits = ((PriorityGroupTmp + __NVIC_PRIO_BITS) < 7) ? 0 : PriorityGroupTmp - 7 + __NVIC_PRIO_BITS; - - *pPreemptPriority = (Priority >> SubPriorityBits) & ((1 << (PreemptPriorityBits)) - 1); - *pSubPriority = (Priority) & ((1 << (SubPriorityBits)) - 1); -} - - -/** \brief System Reset - - The function initiates a system reset request to reset the MCU. - */ -__STATIC_INLINE void NVIC_SystemReset(void) -{ - __DSB(); /* Ensure all outstanding memory accesses included - buffered write are completed before reset */ - SCB->AIRCR = ((0x5FA << SCB_AIRCR_VECTKEY_Pos) | - (SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) | - SCB_AIRCR_SYSRESETREQ_Msk); /* Keep priority group unchanged */ - __DSB(); /* Ensure completion of memory access */ - while (1); /* wait until reset */ -} - -/*@} end of CMSIS_Core_NVICFunctions */ - - - -/* ################################## SysTick function ############################################ */ -/** \ingroup CMSIS_Core_FunctionInterface - \defgroup CMSIS_Core_SysTickFunctions SysTick Functions - \brief Functions that configure the System. - @{ - */ - -#if (__Vendor_SysTickConfig == 0) - -/** \brief System Tick Configuration - - The function initializes the System Timer and its interrupt, and starts the System Tick Timer. - Counter is in free running mode to generate periodic interrupts. - - \param [in] ticks Number of ticks between two interrupts. - - \return 0 Function succeeded. - \return 1 Function failed. - - \note When the variable <b>__Vendor_SysTickConfig</b> is set to 1, then the - function <b>SysTick_Config</b> is not included. In this case, the file <b><i>device</i>.h</b> - must contain a vendor-specific implementation of this function. - - */ -__STATIC_INLINE uint32_t SysTick_Config(uint32_t ticks) -{ - if ((ticks - 1) > SysTick_LOAD_RELOAD_Msk) return (1); /* Reload value impossible */ - - SysTick->LOAD = ticks - 1; /* set reload register */ - NVIC_SetPriority(SysTick_IRQn, (1 << __NVIC_PRIO_BITS) - 1); /* set Priority for Systick Interrupt */ - SysTick->VAL = 0; /* Load the SysTick Counter Value */ - SysTick->CTRL = SysTick_CTRL_CLKSOURCE_Msk | - SysTick_CTRL_TICKINT_Msk | - SysTick_CTRL_ENABLE_Msk; /* Enable SysTick IRQ and SysTick Timer */ - return (0); /* Function successful */ -} - -#endif - -/*@} end of CMSIS_Core_SysTickFunctions */ - - - -/* ##################################### Debug In/Output function ########################################### */ -/** \ingroup CMSIS_Core_FunctionInterface - \defgroup CMSIS_core_DebugFunctions ITM Functions - \brief Functions that access the ITM debug interface. - @{ - */ - -extern volatile int32_t ITM_RxBuffer; /*!< External variable to receive characters. */ -#define ITM_RXBUFFER_EMPTY 0x5AA55AA5 /*!< Value identifying \ref ITM_RxBuffer is ready for next character. */ - - -/** \brief ITM Send Character - - The function transmits a character via the ITM channel 0, and - \li Just returns when no debugger is connected that has booked the output. - \li Is blocking when a debugger is connected, but the previous character sent has not been transmitted. - - \param [in] ch Character to transmit. - - \returns Character to transmit. - */ -__STATIC_INLINE uint32_t ITM_SendChar(uint32_t ch) -{ - if ((ITM->TCR & ITM_TCR_ITMENA_Msk) && /* ITM enabled */ - (ITM->TER & (1UL << 0))) { /* ITM Port #0 enabled */ - while (ITM->PORT[0].u32 == 0); - ITM->PORT[0].u8 = (uint8_t) ch; - } - return (ch); -} - - -/** \brief ITM Receive Character - - The function inputs a character via the external variable \ref ITM_RxBuffer. - - \return Received character. - \return -1 No character pending. - */ -__STATIC_INLINE int32_t ITM_ReceiveChar(void) -{ - int32_t ch = -1; /* no character available */ - - if (ITM_RxBuffer != ITM_RXBUFFER_EMPTY) { - ch = ITM_RxBuffer; - ITM_RxBuffer = ITM_RXBUFFER_EMPTY; /* ready for next character */ - } - - return (ch); -} - - -/** \brief ITM Check Character - - The function checks whether a character is pending for reading in the variable \ref ITM_RxBuffer. - - \return 0 No character available. - \return 1 Character available. - */ -__STATIC_INLINE int32_t ITM_CheckChar(void) -{ - - if (ITM_RxBuffer == ITM_RXBUFFER_EMPTY) { - return (0); /* no character available */ - } else { - return (1); /* character available */ - } -} - -/*@} end of CMSIS_core_DebugFunctions */ - -#endif /* __CORE_CM3_H_DEPENDANT */ - -#endif /* __CMSIS_GENERIC */ - -#ifdef __cplusplus -} -#endif diff --git a/bsp/gd32103c-eval/Libraries/CMSIS/core_cmFunc.h b/bsp/gd32103c-eval/Libraries/CMSIS/core_cmFunc.h deleted file mode 100644 index 4a6b5d6683..0000000000 --- a/bsp/gd32103c-eval/Libraries/CMSIS/core_cmFunc.h +++ /dev/null @@ -1,616 +0,0 @@ -/**************************************************************************//** - * @file core_cmFunc.h - * @brief CMSIS Cortex-M Core Function Access Header File - * @version V3.01 - * @date 06. March 2012 - * - * @note - * Copyright (C) 2009-2012 ARM Limited. All rights reserved. - * - * @par - * ARM Limited (ARM) is supplying this software for use with Cortex-M - * processor based microcontrollers. This file can be freely distributed - * within development tools that are supporting such ARM based processors. - * - * @par - * THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED - * OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF - * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE. - * ARM SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR - * CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER. - * - ******************************************************************************/ - -#ifndef __CORE_CMFUNC_H -#define __CORE_CMFUNC_H - - -/* ########################### Core Function Access ########################### */ -/** \ingroup CMSIS_Core_FunctionInterface - \defgroup CMSIS_Core_RegAccFunctions CMSIS Core Register Access Functions - @{ - */ - -#if defined ( __CC_ARM ) /*------------------RealView Compiler -----------------*/ -/* ARM armcc specific functions */ - -#if (__ARMCC_VERSION < 400677) - #error "Please use ARM Compiler Toolchain V4.0.677 or later!" -#endif - -/* intrinsic void __enable_irq(); */ -/* intrinsic void __disable_irq(); */ - -/** \brief Get Control Register - - This function returns the content of the Control Register. - - \return Control Register value - */ -__STATIC_INLINE uint32_t __get_CONTROL(void) -{ - register uint32_t __regControl __ASM("control"); - return (__regControl); -} - - -/** \brief Set Control Register - - This function writes the given value to the Control Register. - - \param [in] control Control Register value to set - */ -__STATIC_INLINE void __set_CONTROL(uint32_t control) -{ - register uint32_t __regControl __ASM("control"); - __regControl = control; -} - - -/** \brief Get IPSR Register - - This function returns the content of the IPSR Register. - - \return IPSR Register value - */ -__STATIC_INLINE uint32_t __get_IPSR(void) -{ - register uint32_t __regIPSR __ASM("ipsr"); - return (__regIPSR); -} - - -/** \brief Get APSR Register - - This function returns the content of the APSR Register. - - \return APSR Register value - */ -__STATIC_INLINE uint32_t __get_APSR(void) -{ - register uint32_t __regAPSR __ASM("apsr"); - return (__regAPSR); -} - - -/** \brief Get xPSR Register - - This function returns the content of the xPSR Register. - - \return xPSR Register value - */ -__STATIC_INLINE uint32_t __get_xPSR(void) -{ - register uint32_t __regXPSR __ASM("xpsr"); - return (__regXPSR); -} - - -/** \brief Get Process Stack Pointer - - This function returns the current value of the Process Stack Pointer (PSP). - - \return PSP Register value - */ -__STATIC_INLINE uint32_t __get_PSP(void) -{ - register uint32_t __regProcessStackPointer __ASM("psp"); - return (__regProcessStackPointer); -} - - -/** \brief Set Process Stack Pointer - - This function assigns the given value to the Process Stack Pointer (PSP). - - \param [in] topOfProcStack Process Stack Pointer value to set - */ -__STATIC_INLINE void __set_PSP(uint32_t topOfProcStack) -{ - register uint32_t __regProcessStackPointer __ASM("psp"); - __regProcessStackPointer = topOfProcStack; -} - - -/** \brief Get Main Stack Pointer - - This function returns the current value of the Main Stack Pointer (MSP). - - \return MSP Register value - */ -__STATIC_INLINE uint32_t __get_MSP(void) -{ - register uint32_t __regMainStackPointer __ASM("msp"); - return (__regMainStackPointer); -} - - -/** \brief Set Main Stack Pointer - - This function assigns the given value to the Main Stack Pointer (MSP). - - \param [in] topOfMainStack Main Stack Pointer value to set - */ -__STATIC_INLINE void __set_MSP(uint32_t topOfMainStack) -{ - register uint32_t __regMainStackPointer __ASM("msp"); - __regMainStackPointer = topOfMainStack; -} - - -/** \brief Get Priority Mask - - This function returns the current state of the priority mask bit from the Priority Mask Register. - - \return Priority Mask value - */ -__STATIC_INLINE uint32_t __get_PRIMASK(void) -{ - register uint32_t __regPriMask __ASM("primask"); - return (__regPriMask); -} - - -/** \brief Set Priority Mask - - This function assigns the given value to the Priority Mask Register. - - \param [in] priMask Priority Mask - */ -__STATIC_INLINE void __set_PRIMASK(uint32_t priMask) -{ - register uint32_t __regPriMask __ASM("primask"); - __regPriMask = (priMask); -} - - -#if (__CORTEX_M >= 0x03) - -/** \brief Enable FIQ - - This function enables FIQ interrupts by clearing the F-bit in the CPSR. - Can only be executed in Privileged modes. - */ -#define __enable_fault_irq __enable_fiq - - -/** \brief Disable FIQ - - This function disables FIQ interrupts by setting the F-bit in the CPSR. - Can only be executed in Privileged modes. - */ -#define __disable_fault_irq __disable_fiq - - -/** \brief Get Base Priority - - This function returns the current value of the Base Priority register. - - \return Base Priority register value - */ -__STATIC_INLINE uint32_t __get_BASEPRI(void) -{ - register uint32_t __regBasePri __ASM("basepri"); - return (__regBasePri); -} - - -/** \brief Set Base Priority - - This function assigns the given value to the Base Priority register. - - \param [in] basePri Base Priority value to set - */ -__STATIC_INLINE void __set_BASEPRI(uint32_t basePri) -{ - register uint32_t __regBasePri __ASM("basepri"); - __regBasePri = (basePri & 0xff); -} - - -/** \brief Get Fault Mask - - This function returns the current value of the Fault Mask register. - - \return Fault Mask register value - */ -__STATIC_INLINE uint32_t __get_FAULTMASK(void) -{ - register uint32_t __regFaultMask __ASM("faultmask"); - return (__regFaultMask); -} - - -/** \brief Set Fault Mask - - This function assigns the given value to the Fault Mask register. - - \param [in] faultMask Fault Mask value to set - */ -__STATIC_INLINE void __set_FAULTMASK(uint32_t faultMask) -{ - register uint32_t __regFaultMask __ASM("faultmask"); - __regFaultMask = (faultMask & (uint32_t)1); -} - -#endif /* (__CORTEX_M >= 0x03) */ - - -#if (__CORTEX_M == 0x04) - -/** \brief Get FPSCR - - This function returns the current value of the Floating Point Status/Control register. - - \return Floating Point Status/Control register value - */ -__STATIC_INLINE uint32_t __get_FPSCR(void) -{ -#if (__FPU_PRESENT == 1) && (__FPU_USED == 1) - register uint32_t __regfpscr __ASM("fpscr"); - return (__regfpscr); -#else - return (0); -#endif -} - - -/** \brief Set FPSCR - - This function assigns the given value to the Floating Point Status/Control register. - - \param [in] fpscr Floating Point Status/Control value to set - */ -__STATIC_INLINE void __set_FPSCR(uint32_t fpscr) -{ -#if (__FPU_PRESENT == 1) && (__FPU_USED == 1) - register uint32_t __regfpscr __ASM("fpscr"); - __regfpscr = (fpscr); -#endif -} - -#endif /* (__CORTEX_M == 0x04) */ - - -#elif defined ( __ICCARM__ ) /*------------------ ICC Compiler -------------------*/ -/* IAR iccarm specific functions */ - -#include <cmsis_iar.h> - - -#elif defined ( __TMS470__ ) /*---------------- TI CCS Compiler ------------------*/ -/* TI CCS specific functions */ - -#include <cmsis_ccs.h> - - -#elif defined ( __GNUC__ ) /*------------------ GNU Compiler ---------------------*/ -/* GNU gcc specific functions */ - -/** \brief Enable IRQ Interrupts - - This function enables IRQ interrupts by clearing the I-bit in the CPSR. - Can only be executed in Privileged modes. - */ -__attribute__((always_inline)) __STATIC_INLINE void __enable_irq(void) -{ - __ASM volatile("cpsie i"); -} - - -/** \brief Disable IRQ Interrupts - - This function disables IRQ interrupts by setting the I-bit in the CPSR. - Can only be executed in Privileged modes. - */ -__attribute__((always_inline)) __STATIC_INLINE void __disable_irq(void) -{ - __ASM volatile("cpsid i"); -} - - -/** \brief Get Control Register - - This function returns the content of the Control Register. - - \return Control Register value - */ -__attribute__((always_inline)) __STATIC_INLINE uint32_t __get_CONTROL(void) -{ - uint32_t result; - - __ASM volatile("MRS %0, control" : "=r"(result)); - return (result); -} - - -/** \brief Set Control Register - - This function writes the given value to the Control Register. - - \param [in] control Control Register value to set - */ -__attribute__((always_inline)) __STATIC_INLINE void __set_CONTROL(uint32_t control) -{ - __ASM volatile("MSR control, %0" : : "r"(control)); -} - - -/** \brief Get IPSR Register - - This function returns the content of the IPSR Register. - - \return IPSR Register value - */ -__attribute__((always_inline)) __STATIC_INLINE uint32_t __get_IPSR(void) -{ - uint32_t result; - - __ASM volatile("MRS %0, ipsr" : "=r"(result)); - return (result); -} - - -/** \brief Get APSR Register - - This function returns the content of the APSR Register. - - \return APSR Register value - */ -__attribute__((always_inline)) __STATIC_INLINE uint32_t __get_APSR(void) -{ - uint32_t result; - - __ASM volatile("MRS %0, apsr" : "=r"(result)); - return (result); -} - - -/** \brief Get xPSR Register - - This function returns the content of the xPSR Register. - - \return xPSR Register value - */ -__attribute__((always_inline)) __STATIC_INLINE uint32_t __get_xPSR(void) -{ - uint32_t result; - - __ASM volatile("MRS %0, xpsr" : "=r"(result)); - return (result); -} - - -/** \brief Get Process Stack Pointer - - This function returns the current value of the Process Stack Pointer (PSP). - - \return PSP Register value - */ -__attribute__((always_inline)) __STATIC_INLINE uint32_t __get_PSP(void) -{ - register uint32_t result; - - __ASM volatile("MRS %0, psp\n" : "=r"(result)); - return (result); -} - - -/** \brief Set Process Stack Pointer - - This function assigns the given value to the Process Stack Pointer (PSP). - - \param [in] topOfProcStack Process Stack Pointer value to set - */ -__attribute__((always_inline)) __STATIC_INLINE void __set_PSP(uint32_t topOfProcStack) -{ - __ASM volatile("MSR psp, %0\n" : : "r"(topOfProcStack)); -} - - -/** \brief Get Main Stack Pointer - - This function returns the current value of the Main Stack Pointer (MSP). - - \return MSP Register value - */ -__attribute__((always_inline)) __STATIC_INLINE uint32_t __get_MSP(void) -{ - register uint32_t result; - - __ASM volatile("MRS %0, msp\n" : "=r"(result)); - return (result); -} - - -/** \brief Set Main Stack Pointer - - This function assigns the given value to the Main Stack Pointer (MSP). - - \param [in] topOfMainStack Main Stack Pointer value to set - */ -__attribute__((always_inline)) __STATIC_INLINE void __set_MSP(uint32_t topOfMainStack) -{ - __ASM volatile("MSR msp, %0\n" : : "r"(topOfMainStack)); -} - - -/** \brief Get Priority Mask - - This function returns the current state of the priority mask bit from the Priority Mask Register. - - \return Priority Mask value - */ -__attribute__((always_inline)) __STATIC_INLINE uint32_t __get_PRIMASK(void) -{ - uint32_t result; - - __ASM volatile("MRS %0, primask" : "=r"(result)); - return (result); -} - - -/** \brief Set Priority Mask - - This function assigns the given value to the Priority Mask Register. - - \param [in] priMask Priority Mask - */ -__attribute__((always_inline)) __STATIC_INLINE void __set_PRIMASK(uint32_t priMask) -{ - __ASM volatile("MSR primask, %0" : : "r"(priMask)); -} - - -#if (__CORTEX_M >= 0x03) - -/** \brief Enable FIQ - - This function enables FIQ interrupts by clearing the F-bit in the CPSR. - Can only be executed in Privileged modes. - */ -__attribute__((always_inline)) __STATIC_INLINE void __enable_fault_irq(void) -{ - __ASM volatile("cpsie f"); -} - - -/** \brief Disable FIQ - - This function disables FIQ interrupts by setting the F-bit in the CPSR. - Can only be executed in Privileged modes. - */ -__attribute__((always_inline)) __STATIC_INLINE void __disable_fault_irq(void) -{ - __ASM volatile("cpsid f"); -} - - -/** \brief Get Base Priority - - This function returns the current value of the Base Priority register. - - \return Base Priority register value - */ -__attribute__((always_inline)) __STATIC_INLINE uint32_t __get_BASEPRI(void) -{ - uint32_t result; - - __ASM volatile("MRS %0, basepri_max" : "=r"(result)); - return (result); -} - - -/** \brief Set Base Priority - - This function assigns the given value to the Base Priority register. - - \param [in] basePri Base Priority value to set - */ -__attribute__((always_inline)) __STATIC_INLINE void __set_BASEPRI(uint32_t value) -{ - __ASM volatile("MSR basepri, %0" : : "r"(value)); -} - - -/** \brief Get Fault Mask - - This function returns the current value of the Fault Mask register. - - \return Fault Mask register value - */ -__attribute__((always_inline)) __STATIC_INLINE uint32_t __get_FAULTMASK(void) -{ - uint32_t result; - - __ASM volatile("MRS %0, faultmask" : "=r"(result)); - return (result); -} - - -/** \brief Set Fault Mask - - This function assigns the given value to the Fault Mask register. - - \param [in] faultMask Fault Mask value to set - */ -__attribute__((always_inline)) __STATIC_INLINE void __set_FAULTMASK(uint32_t faultMask) -{ - __ASM volatile("MSR faultmask, %0" : : "r"(faultMask)); -} - -#endif /* (__CORTEX_M >= 0x03) */ - - -#if (__CORTEX_M == 0x04) - -/** \brief Get FPSCR - - This function returns the current value of the Floating Point Status/Control register. - - \return Floating Point Status/Control register value - */ -__attribute__((always_inline)) __STATIC_INLINE uint32_t __get_FPSCR(void) -{ -#if (__FPU_PRESENT == 1) && (__FPU_USED == 1) - uint32_t result; - - __ASM volatile("VMRS %0, fpscr" : "=r"(result)); - return (result); -#else - return (0); -#endif -} - - -/** \brief Set FPSCR - - This function assigns the given value to the Floating Point Status/Control register. - - \param [in] fpscr Floating Point Status/Control value to set - */ -__attribute__((always_inline)) __STATIC_INLINE void __set_FPSCR(uint32_t fpscr) -{ -#if (__FPU_PRESENT == 1) && (__FPU_USED == 1) - __ASM volatile("VMSR fpscr, %0" : : "r"(fpscr)); -#endif -} - -#endif /* (__CORTEX_M == 0x04) */ - - -#elif defined ( __TASKING__ ) /*------------------ TASKING Compiler --------------*/ -/* TASKING carm specific functions */ - -/* - * The CMSIS functions have been implemented as intrinsics in the compiler. - * Please use "carm -?i" to get an up to date list of all instrinsics, - * Including the CMSIS ones. - */ - -#endif - -/*@} end of CMSIS_Core_RegAccFunctions */ - - -#endif /* __CORE_CMFUNC_H */ diff --git a/bsp/gd32103c-eval/Libraries/CMSIS/core_cmInstr.h b/bsp/gd32103c-eval/Libraries/CMSIS/core_cmInstr.h deleted file mode 100644 index 1c0b6f6b97..0000000000 --- a/bsp/gd32103c-eval/Libraries/CMSIS/core_cmInstr.h +++ /dev/null @@ -1,618 +0,0 @@ -/**************************************************************************//** - * @file core_cmInstr.h - * @brief CMSIS Cortex-M Core Instruction Access Header File - * @version V3.01 - * @date 06. March 2012 - * - * @note - * Copyright (C) 2009-2012 ARM Limited. All rights reserved. - * - * @par - * ARM Limited (ARM) is supplying this software for use with Cortex-M - * processor based microcontrollers. This file can be freely distributed - * within development tools that are supporting such ARM based processors. - * - * @par - * THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED - * OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF - * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE. - * ARM SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR - * CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER. - * - ******************************************************************************/ - -#ifndef __CORE_CMINSTR_H -#define __CORE_CMINSTR_H - - -/* ########################## Core Instruction Access ######################### */ -/** \defgroup CMSIS_Core_InstructionInterface CMSIS Core Instruction Interface - Access to dedicated instructions - @{ -*/ - -#if defined ( __CC_ARM ) /*------------------RealView Compiler -----------------*/ -/* ARM armcc specific functions */ - -#if (__ARMCC_VERSION < 400677) - #error "Please use ARM Compiler Toolchain V4.0.677 or later!" -#endif - - -/** \brief No Operation - - No Operation does nothing. This instruction can be used for code alignment purposes. - */ -#define __NOP __nop - - -/** \brief Wait For Interrupt - - Wait For Interrupt is a hint instruction that suspends execution - until one of a number of events occurs. - */ -#define __WFI __wfi - - -/** \brief Wait For Event - - Wait For Event is a hint instruction that permits the processor to enter - a low-power state until one of a number of events occurs. - */ -#define __WFE __wfe - - -/** \brief Send Event - - Send Event is a hint instruction. It causes an event to be signaled to the CPU. - */ -#define __SEV __sev - - -/** \brief Instruction Synchronization Barrier - - Instruction Synchronization Barrier flushes the pipeline in the processor, - so that all instructions following the ISB are fetched from cache or - memory, after the instruction has been completed. - */ -#define __ISB() __isb(0xF) - - -/** \brief Data Synchronization Barrier - - This function acts as a special kind of Data Memory Barrier. - It completes when all explicit memory accesses before this instruction complete. - */ -#define __DSB() __dsb(0xF) - - -/** \brief Data Memory Barrier - - This function ensures the apparent order of the explicit memory operations before - and after the instruction, without ensuring their completion. - */ -#define __DMB() __dmb(0xF) - - -/** \brief Reverse byte order (32 bit) - - This function reverses the byte order in integer value. - - \param [in] value Value to reverse - \return Reversed value - */ -#define __REV __rev - - -/** \brief Reverse byte order (16 bit) - - This function reverses the byte order in two unsigned short values. - - \param [in] value Value to reverse - \return Reversed value - */ -__attribute__((section(".rev16_text"))) __STATIC_INLINE __ASM uint32_t __REV16(uint32_t value) -{ - rev16 r0, r0 - bx lr -} - - -/** \brief Reverse byte order in signed short value - - This function reverses the byte order in a signed short value with sign extension to integer. - - \param [in] value Value to reverse - \return Reversed value - */ -__attribute__((section(".revsh_text"))) __STATIC_INLINE __ASM int32_t __REVSH(int32_t value) -{ - revsh r0, r0 - bx lr -} - - -/** \brief Rotate Right in unsigned value (32 bit) - - This function Rotate Right (immediate) provides the value of the contents of a register rotated by a variable number of bits. - - \param [in] value Value to rotate - \param [in] value Number of Bits to rotate - \return Rotated value - */ -#define __ROR __ror - - -#if (__CORTEX_M >= 0x03) - - /** \brief Reverse bit order of value - - This function reverses the bit order of the given value. - - \param [in] value Value to reverse - \return Reversed value - */ - #define __RBIT __rbit - - - /** \brief LDR Exclusive (8 bit) - - This function performs a exclusive LDR command for 8 bit value. - - \param [in] ptr Pointer to data - \return value of type uint8_t at (*ptr) - */ - #define __LDREXB(ptr) ((uint8_t ) __ldrex(ptr)) - - - /** \brief LDR Exclusive (16 bit) - - This function performs a exclusive LDR command for 16 bit values. - - \param [in] ptr Pointer to data - \return value of type uint16_t at (*ptr) - */ - #define __LDREXH(ptr) ((uint16_t) __ldrex(ptr)) - - - /** \brief LDR Exclusive (32 bit) - - This function performs a exclusive LDR command for 32 bit values. - - \param [in] ptr Pointer to data - \return value of type uint32_t at (*ptr) - */ - #define __LDREXW(ptr) ((uint32_t ) __ldrex(ptr)) - - - /** \brief STR Exclusive (8 bit) - - This function performs a exclusive STR command for 8 bit values. - - \param [in] value Value to store - \param [in] ptr Pointer to location - \return 0 Function succeeded - \return 1 Function failed - */ - #define __STREXB(value, ptr) __strex(value, ptr) - - - /** \brief STR Exclusive (16 bit) - - This function performs a exclusive STR command for 16 bit values. - - \param [in] value Value to store - \param [in] ptr Pointer to location - \return 0 Function succeeded - \return 1 Function failed - */ - #define __STREXH(value, ptr) __strex(value, ptr) - - - /** \brief STR Exclusive (32 bit) - - This function performs a exclusive STR command for 32 bit values. - - \param [in] value Value to store - \param [in] ptr Pointer to location - \return 0 Function succeeded - \return 1 Function failed - */ - #define __STREXW(value, ptr) __strex(value, ptr) - - - /** \brief Remove the exclusive lock - - This function removes the exclusive lock which is created by LDREX. - - */ - #define __CLREX __clrex - - - /** \brief Signed Saturate - - This function saturates a signed value. - - \param [in] value Value to be saturated - \param [in] sat Bit position to saturate to (1..32) - \return Saturated value - */ - #define __SSAT __ssat - - - /** \brief Unsigned Saturate - - This function saturates an unsigned value. - - \param [in] value Value to be saturated - \param [in] sat Bit position to saturate to (0..31) - \return Saturated value - */ - #define __USAT __usat - - - /** \brief Count leading zeros - - This function counts the number of leading zeros of a data value. - - \param [in] value Value to count the leading zeros - \return number of leading zeros in value - */ - #define __CLZ __clz - -#endif /* (__CORTEX_M >= 0x03) */ - - - -#elif defined ( __ICCARM__ ) /*------------------ ICC Compiler -------------------*/ -/* IAR iccarm specific functions */ - -#include <cmsis_iar.h> - - -#elif defined ( __TMS470__ ) /*---------------- TI CCS Compiler ------------------*/ -/* TI CCS specific functions */ - -#include <cmsis_ccs.h> - - -#elif defined ( __GNUC__ ) /*------------------ GNU Compiler ---------------------*/ -/* GNU gcc specific functions */ - -/** \brief No Operation - - No Operation does nothing. This instruction can be used for code alignment purposes. - */ -__attribute__((always_inline)) __STATIC_INLINE void __NOP(void) -{ - __ASM volatile("nop"); -} - - -/** \brief Wait For Interrupt - - Wait For Interrupt is a hint instruction that suspends execution - until one of a number of events occurs. - */ -__attribute__((always_inline)) __STATIC_INLINE void __WFI(void) -{ - __ASM volatile("wfi"); -} - - -/** \brief Wait For Event - - Wait For Event is a hint instruction that permits the processor to enter - a low-power state until one of a number of events occurs. - */ -__attribute__((always_inline)) __STATIC_INLINE void __WFE(void) -{ - __ASM volatile("wfe"); -} - - -/** \brief Send Event - - Send Event is a hint instruction. It causes an event to be signaled to the CPU. - */ -__attribute__((always_inline)) __STATIC_INLINE void __SEV(void) -{ - __ASM volatile("sev"); -} - - -/** \brief Instruction Synchronization Barrier - - Instruction Synchronization Barrier flushes the pipeline in the processor, - so that all instructions following the ISB are fetched from cache or - memory, after the instruction has been completed. - */ -__attribute__((always_inline)) __STATIC_INLINE void __ISB(void) -{ - __ASM volatile("isb"); -} - - -/** \brief Data Synchronization Barrier - - This function acts as a special kind of Data Memory Barrier. - It completes when all explicit memory accesses before this instruction complete. - */ -__attribute__((always_inline)) __STATIC_INLINE void __DSB(void) -{ - __ASM volatile("dsb"); -} - - -/** \brief Data Memory Barrier - - This function ensures the apparent order of the explicit memory operations before - and after the instruction, without ensuring their completion. - */ -__attribute__((always_inline)) __STATIC_INLINE void __DMB(void) -{ - __ASM volatile("dmb"); -} - - -/** \brief Reverse byte order (32 bit) - - This function reverses the byte order in integer value. - - \param [in] value Value to reverse - \return Reversed value - */ -__attribute__((always_inline)) __STATIC_INLINE uint32_t __REV(uint32_t value) -{ - uint32_t result; - - __ASM volatile("rev %0, %1" : "=r"(result) : "r"(value)); - return (result); -} - - -/** \brief Reverse byte order (16 bit) - - This function reverses the byte order in two unsigned short values. - - \param [in] value Value to reverse - \return Reversed value - */ -__attribute__((always_inline)) __STATIC_INLINE uint32_t __REV16(uint32_t value) -{ - uint32_t result; - - __ASM volatile("rev16 %0, %1" : "=r"(result) : "r"(value)); - return (result); -} - - -/** \brief Reverse byte order in signed short value - - This function reverses the byte order in a signed short value with sign extension to integer. - - \param [in] value Value to reverse - \return Reversed value - */ -__attribute__((always_inline)) __STATIC_INLINE int32_t __REVSH(int32_t value) -{ - uint32_t result; - - __ASM volatile("revsh %0, %1" : "=r"(result) : "r"(value)); - return (result); -} - - -/** \brief Rotate Right in unsigned value (32 bit) - - This function Rotate Right (immediate) provides the value of the contents of a register rotated by a variable number of bits. - - \param [in] value Value to rotate - \param [in] value Number of Bits to rotate - \return Rotated value - */ -__attribute__((always_inline)) __STATIC_INLINE uint32_t __ROR(uint32_t op1, uint32_t op2) -{ - - __ASM volatile("ror %0, %0, %1" : "+r"(op1) : "r"(op2)); - return (op1); -} - - -#if (__CORTEX_M >= 0x03) - -/** \brief Reverse bit order of value - - This function reverses the bit order of the given value. - - \param [in] value Value to reverse - \return Reversed value - */ -__attribute__((always_inline)) __STATIC_INLINE uint32_t __RBIT(uint32_t value) -{ - uint32_t result; - - __ASM volatile("rbit %0, %1" : "=r"(result) : "r"(value)); - return (result); -} - - -/** \brief LDR Exclusive (8 bit) - - This function performs a exclusive LDR command for 8 bit value. - - \param [in] ptr Pointer to data - \return value of type uint8_t at (*ptr) - */ -__attribute__((always_inline)) __STATIC_INLINE uint8_t __LDREXB(volatile uint8_t *addr) -{ - uint8_t result; - - __ASM volatile("ldrexb %0, [%1]" : "=r"(result) : "r"(addr)); - return (result); -} - - -/** \brief LDR Exclusive (16 bit) - - This function performs a exclusive LDR command for 16 bit values. - - \param [in] ptr Pointer to data - \return value of type uint16_t at (*ptr) - */ -__attribute__((always_inline)) __STATIC_INLINE uint16_t __LDREXH(volatile uint16_t *addr) -{ - uint16_t result; - - __ASM volatile("ldrexh %0, [%1]" : "=r"(result) : "r"(addr)); - return (result); -} - - -/** \brief LDR Exclusive (32 bit) - - This function performs a exclusive LDR command for 32 bit values. - - \param [in] ptr Pointer to data - \return value of type uint32_t at (*ptr) - */ -__attribute__((always_inline)) __STATIC_INLINE uint32_t __LDREXW(volatile uint32_t *addr) -{ - uint32_t result; - - __ASM volatile("ldrex %0, [%1]" : "=r"(result) : "r"(addr)); - return (result); -} - - -/** \brief STR Exclusive (8 bit) - - This function performs a exclusive STR command for 8 bit values. - - \param [in] value Value to store - \param [in] ptr Pointer to location - \return 0 Function succeeded - \return 1 Function failed - */ -__attribute__((always_inline)) __STATIC_INLINE uint32_t __STREXB(uint8_t value, volatile uint8_t *addr) -{ - uint32_t result; - - __ASM volatile("strexb %0, %2, [%1]" : "=&r"(result) : "r"(addr), "r"(value)); - return (result); -} - - -/** \brief STR Exclusive (16 bit) - - This function performs a exclusive STR command for 16 bit values. - - \param [in] value Value to store - \param [in] ptr Pointer to location - \return 0 Function succeeded - \return 1 Function failed - */ -__attribute__((always_inline)) __STATIC_INLINE uint32_t __STREXH(uint16_t value, volatile uint16_t *addr) -{ - uint32_t result; - - __ASM volatile("strexh %0, %2, [%1]" : "=&r"(result) : "r"(addr), "r"(value)); - return (result); -} - - -/** \brief STR Exclusive (32 bit) - - This function performs a exclusive STR command for 32 bit values. - - \param [in] value Value to store - \param [in] ptr Pointer to location - \return 0 Function succeeded - \return 1 Function failed - */ -__attribute__((always_inline)) __STATIC_INLINE uint32_t __STREXW(uint32_t value, volatile uint32_t *addr) -{ - uint32_t result; - - __ASM volatile("strex %0, %2, [%1]" : "=&r"(result) : "r"(addr), "r"(value)); - return (result); -} - - -/** \brief Remove the exclusive lock - - This function removes the exclusive lock which is created by LDREX. - - */ -__attribute__((always_inline)) __STATIC_INLINE void __CLREX(void) -{ - __ASM volatile("clrex"); -} - - -/** \brief Signed Saturate - - This function saturates a signed value. - - \param [in] value Value to be saturated - \param [in] sat Bit position to saturate to (1..32) - \return Saturated value - */ -#define __SSAT(ARG1,ARG2) \ -({ \ - uint32_t __RES, __ARG1 = (ARG1); \ - __ASM ("ssat %0, %1, %2" : "=r" (__RES) : "I" (ARG2), "r" (__ARG1) ); \ - __RES; \ - }) - - -/** \brief Unsigned Saturate - - This function saturates an unsigned value. - - \param [in] value Value to be saturated - \param [in] sat Bit position to saturate to (0..31) - \return Saturated value - */ -#define __USAT(ARG1,ARG2) \ -({ \ - uint32_t __RES, __ARG1 = (ARG1); \ - __ASM ("usat %0, %1, %2" : "=r" (__RES) : "I" (ARG2), "r" (__ARG1) ); \ - __RES; \ - }) - - -/** \brief Count leading zeros - - This function counts the number of leading zeros of a data value. - - \param [in] value Value to count the leading zeros - \return number of leading zeros in value - */ -__attribute__((always_inline)) __STATIC_INLINE uint8_t __CLZ(uint32_t value) -{ - uint8_t result; - - __ASM volatile("clz %0, %1" : "=r"(result) : "r"(value)); - return (result); -} - -#endif /* (__CORTEX_M >= 0x03) */ - - - - -#elif defined ( __TASKING__ ) /*------------------ TASKING Compiler --------------*/ -/* TASKING carm specific functions */ - -/* - * The CMSIS functions have been implemented as intrinsics in the compiler. - * Please use "carm -?i" to get an up to date list of all intrinsics, - * Including the CMSIS ones. - */ - -#endif - -/*@}*/ /* end of group CMSIS_Core_InstructionInterface */ - -#endif /* __CORE_CMINSTR_H */ diff --git a/bsp/gd32103c-eval/Libraries/GD32F1xx_standard_peripheral/Include/gd32f10x_adc.h b/bsp/gd32103c-eval/Libraries/GD32F1xx_standard_peripheral/Include/gd32f10x_adc.h deleted file mode 100644 index b51e596522..0000000000 --- a/bsp/gd32103c-eval/Libraries/GD32F1xx_standard_peripheral/Include/gd32f10x_adc.h +++ /dev/null @@ -1,278 +0,0 @@ -/** - ****************************************************************************** - * @brief ADC header file of the firmware library. - ****************************************************************************** - */ - -/* Define to prevent recursive inclusion -------------------------------------*/ -#ifndef __GD32F10X_ADC_H -#define __GD32F10X_ADC_H - -#ifdef __cplusplus -extern "C" { -#endif - -typedef enum { FALSE = 0, TRUE } BOOL; -/* Includes ------------------------------------------------------------------*/ -#include "gd32f10x.h" -/** @addtogroup GD32F10x_Firmware - * @{ - */ - -/** @addtogroup ADC - * @{ - */ - -/** @defgroup ADC_Exported_Types - * @{ - */ - -/** - * @brief ADC Init structure definition - */ - -typedef struct { - uint32_t ADC_Trig_External; /*!< AD conversion of regular channels trigger. */ - uint8_t ADC_Channel_Number; /*!< The number of converted ADC channels . - This parameter must range from 1 to 16. */ - uint32_t ADC_Data_Align; /*!< ADC data alignment,left or right. */ - - TypeState ADC_Mode_Scan; /*!< AD conversion mode,multichannels mode or Single channel mode. - This parameter can be ENABLE or DISABLE */ - uint32_t ADC_Mode; /*!< AD operation mode,independent mode or dual mode. - This parameter can be a value of @ref ADC_mode */ - TypeState ADC_Mode_Continuous; /*!< AD perform mode,continuous mode or single mode. - This parameter can be ENABLE or DISABLE. */ -} ADC_InitPara; - -/** - * @} - */ -/** @defgroup ADC_Exported_Constants - * @{ - */ - -/** @defgroup ADC_external_trigger - * @{ - */ -#define ADC_EXTERNAL_TRIGGER_MODE_T1_CC1 ((uint32_t)0x00000000) /*!< Only used in ADC1 and ADC2 */ -#define ADC_EXTERNAL_TRIGGER_MODE_T1_CC2 ((uint32_t)0x00020000) /*!< Only used in ADC1 and ADC2 */ -#define ADC_EXTERNAL_TRIGGER_MODE_T2_CC2 ((uint32_t)0x00060000) /*!< Only used in ADC1 and ADC2 */ -#define ADC_EXTERNAL_TRIGGER_MODE_T3_TRGO ((uint32_t)0x00080000) /*!< Only used in ADC1 and ADC2 */ -#define ADC_EXTERNAL_TRIGGER_MODE_T4_CC4 ((uint32_t)0x000A0000) /*!< Only used in ADC1 and ADC2 */ -#define ADC_EXTERNAL_TRIGGER_MODE_EXT_IT11_T8_TRGO ((uint32_t)0x000C0000) /*!< Only used in ADC1 and ADC2 */ -#define ADC_EXTERNAL_TRIGGER_MODE_T1_CC3 ((uint32_t)0x00040000) /*!< Used in ADC1,ADC2 and ADC3 */ -#define ADC_EXTERNAL_TRIGGER_MODE_NONE ((uint32_t)0x000E0000) /*!< Used in ADC1,ADC2 and ADC3 */ -#define ADC_EXTERNAL_TRIGGER_MODE_T3_CC1 ((uint32_t)0x00000000) /*!< Only used in ADC3 */ -#define ADC_EXTERNAL_TRIGGER_MODE_T2_CC3 ((uint32_t)0x00020000) /*!< Only used in ADC3 */ -#define ADC_EXTERNAL_TRIGGER_MODE_T8_CC1 ((uint32_t)0x00060000) /*!< Only used in ADC3 */ -#define ADC_EXTERNAL_TRIGGER_MODE_T8_TRGO ((uint32_t)0x00080000) /*!< Only used in ADC3 */ -#define ADC_EXTERNAL_TRIGGER_MODE_T5_CC1 ((uint32_t)0x000A0000) /*!< Only used in ADC3 */ -#define ADC_EXTERNAL_TRIGGER_MODE_T5_CC3 ((uint32_t)0x000C0000) /*!< Only used in ADC3 */ - -/** - * @} - */ - -/** @defgroup ADC_channels - * @{ - */ -#define ADC_CHANNEL_0 ((uint8_t)0x00) -#define ADC_CHANNEL_1 ((uint8_t)0x01) -#define ADC_CHANNEL_2 ((uint8_t)0x02) -#define ADC_CHANNEL_3 ((uint8_t)0x03) -#define ADC_CHANNEL_4 ((uint8_t)0x04) -#define ADC_CHANNEL_5 ((uint8_t)0x05) -#define ADC_CHANNEL_6 ((uint8_t)0x06) -#define ADC_CHANNEL_7 ((uint8_t)0x07) -#define ADC_CHANNEL_8 ((uint8_t)0x08) -#define ADC_CHANNEL_9 ((uint8_t)0x09) -#define ADC_CHANNEL_10 ((uint8_t)0x0A) -#define ADC_CHANNEL_11 ((uint8_t)0x0B) -#define ADC_CHANNEL_12 ((uint8_t)0x0C) -#define ADC_CHANNEL_13 ((uint8_t)0x0D) -#define ADC_CHANNEL_14 ((uint8_t)0x0E) -#define ADC_CHANNEL_15 ((uint8_t)0x0F) -#define ADC_CHANNEL_16 ((uint8_t)0x10) -#define ADC_CHANNEL_17 ((uint8_t)0x11) -#define ADC_CHANNEL_TEMPSENSOR ((uint8_t)ADC_CHANNEL_16) -#define ADC_CHANNEL_VREFINT ((uint8_t)ADC_CHANNEL_17) - -/** - * @} - */ - -/** @defgroup ADC_data_align - * @{ - */ -#define ADC_DATAALIGN_RIGHT ((uint32_t)0x00000000) -#define ADC_DATAALIGN_LEFT ((uint32_t)0x00000800) - -/** - * @} - */ - -/** @defgroup ADC_mode - * @{ - */ -#define ADC_MODE_INDEPENDENT ((uint32_t)0x00000000) -#define ADC_MODE_REGINSERTSIMULT ((uint32_t)0x00010000) -#define ADC_MODE_REGSIMULT_ALTERTRIG ((uint32_t)0x00020000) -#define ADC_MODE_INSERTSIMULT_FASTINTERL ((uint32_t)0x00030000) -#define ADC_MODE_INSERTSIMULT_SLOWINTERL ((uint32_t)0x00040000) -#define ADC_MODE_INSERTSIMULT ((uint32_t)0x00050000) -#define ADC_MODE_REGSIMULT ((uint32_t)0x00060000) -#define ADC_MODE_FASTINTERL ((uint32_t)0x00070000) -#define ADC_MODE_SLOWINTERL ((uint32_t)0x00080000) -#define ADC_MODE_ALTERTRIG ((uint32_t)0x00090000) - -/** - * @} - */ - -/** @defgroup ADC_sampling_time - * @{ - */ -#define ADC_SAMPLETIME_1POINT5 ((uint8_t)0x00) -#define ADC_SAMPLETIME_7POINT5 ((uint8_t)0x01) -#define ADC_SAMPLETIME_13POINT5 ((uint8_t)0x02) -#define ADC_SAMPLETIME_28POINT5 ((uint8_t)0x03) -#define ADC_SAMPLETIME_41POINT5 ((uint8_t)0x04) -#define ADC_SAMPLETIME_55POINT5 ((uint8_t)0x05) -#define ADC_SAMPLETIME_71POINT5 ((uint8_t)0x06) -#define ADC_SAMPLETIME_239POINT5 ((uint8_t)0x07) - -/** - * @} - */ - -/** @defgroup ADC_external_trigger_sources_for_inserted_channels_conversion - * @{ - */ -#define ADC_EXTERNAL_TRIG_INSERTCONV_T2_TRGO ((uint32_t)0x00002000) /*!< Only used in ADC1 and ADC2 */ -#define ADC_EXTERNAL_TRIG_INSERTCONV_T2_CC1 ((uint32_t)0x00003000) /*!< Only used in ADC1 and ADC2 */ -#define ADC_EXTERNAL_TRIG_INSERTCONV_T3_CC4 ((uint32_t)0x00004000) /*!< Only used in ADC1 and ADC2 */ -#define ADC_EXTERNAL_TRIG_INSERTCONV_T4_TRGO ((uint32_t)0x00005000) /*!< Only used in ADC1 and ADC2 */ -#define ADC_EXTERNAL_TRIG_INSERTCONV_EXT_IT15_T8_CC4 ((uint32_t)0x00006000) /*!< Only used in ADC1 and ADC2 */ -#define ADC_EXTERNAL_TRIG_INSERTCONV_T1_TRIG ((uint32_t)0x00000000) /*!< Used in ADC1,ADC2 and ADC3 */ -#define ADC_EXTERNAL_TRIG_INSERTCONV_T1_CC4 ((uint32_t)0x00001000) /*!< Used in ADC1,ADC2 and ADC3 */ -#define ADC_EXTERNAL_TRIG_INSERTCONV_NONE ((uint32_t)0x00007000) /*!< Used in ADC1,ADC2 and ADC3 */ -#define ADC_EXTERNAL_TRIG_INSERTCONV_T4_CC3 ((uint32_t)0x00002000) /*!< Only used in ADC3 */ -#define ADC_EXTERNAL_TRIG_INSERTCONV_T8_CC2 ((uint32_t)0x00003000) /*!< Only used in ADC3 */ -#define ADC_EXTERNAL_TRIG_INSERTCONV_T8_CC4 ((uint32_t)0x00004000) /*!< Only used in ADC3 */ -#define ADC_EXTERNAL_TRIG_INSERTCONV_T5_TRGO ((uint32_t)0x00005000) /*!< Only used in ADC3 */ -#define ADC_EXTERNAL_TRIG_INSERTCONV_T5_CC4 ((uint32_t)0x00006000) /*!< Only used in ADC3 */ - -/** - * @} - */ - -/** @defgroup ADC_inserted_channel_selection - * @{ - */ -#define ADC_INSERTEDCHANNEL_1 ((uint8_t)0x14) -#define ADC_INSERTEDCHANNEL_2 ((uint8_t)0x18) -#define ADC_INSERTEDCHANNEL_3 ((uint8_t)0x1C) -#define ADC_INSERTEDCHANNEL_4 ((uint8_t)0x20) - -/** - * @} - */ - -/** @defgroup ADC_analog_watchdog_selection - * @{ - */ -#define ADC_ANALOGWATCHDOG_SINGLEREGENABLE ((uint32_t)0x00800200) -#define ADC_ANALOGWATCHDOG_SINGLEINSERTENABLE ((uint32_t)0x00400200) -#define ADC_ANALOGWATCHDOG_SINGLEREGORINSERTENABLE ((uint32_t)0x00C00200) -#define ADC_ANALOGWATCHDOG_ALLREGENABLE ((uint32_t)0x00800000) -#define ADC_ANALOGWATCHDOG_ALLINSERTENABLE ((uint32_t)0x00400000) -#define ADC_ANALOGWATCHDOG_ALLREGALLINSERTENABLE ((uint32_t)0x00C00000) -#define ADC_ANALOGWATCHDOG_NONE ((uint32_t)0x00000000) - -/** - * @} - */ - -/** @defgroup ADC_interrupts_definition - * @{ - */ -#define ADC_INT_EOC ((uint16_t)0x0220) -#define ADC_INT_AWE ((uint16_t)0x0140) -#define ADC_INT_EOIC ((uint16_t)0x0480) - -/** - * @} - */ - -/** @defgroup ADC_flags_definition - * @{ - */ -#define ADC_FLAG_AWE ((uint8_t)0x01) -#define ADC_FLAG_EOC ((uint8_t)0x02) -#define ADC_FLAG_EOIC ((uint8_t)0x04) -#define ADC_FLAG_STIC ((uint8_t)0x08) -#define ADC_FLAG_STRC ((uint8_t)0x10) - -/** - * @} - */ - -/** - * @} - */ - - -/** @defgroup ADC_Exported_Functions - * @{ - */ -void ADC_DeInit(ADC_TypeDef *ADCx, ADC_InitPara *ADC_InitParaStruct); -void ADC_Init(ADC_TypeDef *ADCx, ADC_InitPara *ADC_InitParaStruct); -void ADC_Enable(ADC_TypeDef *ADCx, TypeState NewValue); -void ADC_DMA_Enable(ADC_TypeDef *ADCx, TypeState NewValue); -void ADC_INTConfig(ADC_TypeDef *ADCx, uint16_t ADC_INT, TypeState NewValue); -void ADC_Calibration(ADC_TypeDef *ADCx); -void ADC_SoftwareStartConv_Enable(ADC_TypeDef *ADCx, TypeState NewValue); -TypeState ADC_GetSoftwareStartConvBitState(ADC_TypeDef *ADCx); -void ADC_DiscModeChannelCount_Config(ADC_TypeDef *ADCx, uint8_t Number); -void ADC_DiscMode_Enable(ADC_TypeDef *ADCx, TypeState NewValue); -void ADC_RegularChannel_Config(ADC_TypeDef *ADCx, uint8_t ADC_Channel, uint8_t Rank, uint8_t ADC_SampleTime); -void ADC_ExternalTrigConv_Enable(ADC_TypeDef *ADCx, TypeState NewValue); -uint16_t ADC_GetConversionValue(ADC_TypeDef *ADCx); -uint32_t ADC_GetDualModeConversionValue(void); -void ADC_AutoInsertedConv_Enable(ADC_TypeDef *ADCx, TypeState NewValue); -void ADC_InsertedDiscMode_Enable(ADC_TypeDef *ADCx, TypeState NewValue); -void ADC_ExternalTrigInsertedConv_Config(ADC_TypeDef *ADCx, uint32_t ADC_ExternalTrigInsertConv); -void ADC_ExternalTrigInsertedConv_Enable(ADC_TypeDef *ADCx, TypeState NewValue); -void ADC_SoftwareStartInsertedConv_Enable(ADC_TypeDef *ADCx, TypeState NewValue); -TypeState ADC_GetSoftwareStartInsertedConvCmdBitState(ADC_TypeDef *ADCx); -void ADC_InsertedChannel_Config(ADC_TypeDef *ADCx, uint8_t ADC_Channel, uint8_t Rank, uint8_t ADC_SampleTime); -void ADC_InsertedSequencerLength_Config(ADC_TypeDef *ADCx, uint8_t Length); -void ADC_SetInsertedOffset(ADC_TypeDef *ADCx, uint8_t ADC_InsertedChannel, uint16_t Offset); -uint16_t ADC_GetInsertedConversionValue(ADC_TypeDef *ADCx, uint8_t ADC_InsertedChannel); -void ADC_AnalogWatchdog_Enable(ADC_TypeDef *ADCx, uint32_t ADC_AnalogWatchdog); -void ADC_AnalogWatchdogThresholds_Config(ADC_TypeDef *ADCx, uint16_t HighThreshold, uint16_t LowThreshold); -void ADC_AnalogWatchdogSingleChannel_Config(ADC_TypeDef *ADCx, uint8_t ADC_Channel); -void ADC_TempSensorVrefint_Enable(TypeState NewValue); -TypeState ADC_GetBitState(ADC_TypeDef *ADCx, uint8_t ADC_FLAG); -void ADC_ClearBitState(ADC_TypeDef *ADCx, uint8_t ADC_FLAG); -TypeState ADC_GetIntState(ADC_TypeDef *ADCx, uint16_t ADC_INT); -void ADC_ClearIntBitState(ADC_TypeDef *ADCx, uint16_t ADC_INT); - -/** - * @} - */ - -/** - * @} - */ - -/** - * @} - */ - -#ifdef __cplusplus -} -#endif - -#endif /*__GD32F10X_ADC_H */ diff --git a/bsp/gd32103c-eval/Libraries/GD32F1xx_standard_peripheral/Include/gd32f10x_bkp.h b/bsp/gd32103c-eval/Libraries/GD32F1xx_standard_peripheral/Include/gd32f10x_bkp.h deleted file mode 100644 index 72784b9557..0000000000 --- a/bsp/gd32103c-eval/Libraries/GD32F1xx_standard_peripheral/Include/gd32f10x_bkp.h +++ /dev/null @@ -1,139 +0,0 @@ -/** - ****************************************************************************** - * @brief BKP header file of the firmware library. - ****************************************************************************** - */ - -/* Define to prevent recursive inclusion -------------------------------------*/ -#ifndef __GD32F10X_BKP_H -#define __GD32F10X_BKP_H - -#ifdef __cplusplus -extern "C" { -#endif - - -/* Includes ------------------------------------------------------------------*/ -#include "gd32f10x.h" - -/** @addtogroup GD32F10x_Firmware - * @{ - */ - -/** @addtogroup BKP - * @{ - */ - -/** @defgroup BKP_Exported_Constants - * @{ - */ - -/** @defgroup TAMPER_pin_active_level - * @{ - */ -#define BKP_TPAL_HIGH ((uint16_t)0x0000) -#define BKP_TPAL_LOW ((uint16_t)0x0002) - -/** - * @} - */ - -/** @defgroup RTC_output_on_the_TAMPER_pin - * @{ - */ -#define BKP_RTCOUTPUT_NULL ((uint16_t)0x0000) -#define BKP_RTCOUTPUT_CLKCAL ((uint16_t)0x0080) -#define BKP_RTCOUTPUT_ALARM ((uint16_t)0x0100) -#define BKP_RTCOUTPUT_SECOND ((uint16_t)0x0300) - -/** - * @} - */ - -/** @defgroup Backup_Data_Register - * @{ - */ -#define BKP_DR1 ((uint16_t)0x0004) -#define BKP_DR2 ((uint16_t)0x0008) -#define BKP_DR3 ((uint16_t)0x000C) -#define BKP_DR4 ((uint16_t)0x0010) -#define BKP_DR5 ((uint16_t)0x0014) -#define BKP_DR6 ((uint16_t)0x0018) -#define BKP_DR7 ((uint16_t)0x001C) -#define BKP_DR8 ((uint16_t)0x0020) -#define BKP_DR9 ((uint16_t)0x0024) -#define BKP_DR10 ((uint16_t)0x0028) -#define BKP_DR11 ((uint16_t)0x0040) -#define BKP_DR12 ((uint16_t)0x0044) -#define BKP_DR13 ((uint16_t)0x0048) -#define BKP_DR14 ((uint16_t)0x004C) -#define BKP_DR15 ((uint16_t)0x0050) -#define BKP_DR16 ((uint16_t)0x0054) -#define BKP_DR17 ((uint16_t)0x0058) -#define BKP_DR18 ((uint16_t)0x005C) -#define BKP_DR19 ((uint16_t)0x0060) -#define BKP_DR20 ((uint16_t)0x0064) -#define BKP_DR21 ((uint16_t)0x0068) -#define BKP_DR22 ((uint16_t)0x006C) -#define BKP_DR23 ((uint16_t)0x0070) -#define BKP_DR24 ((uint16_t)0x0074) -#define BKP_DR25 ((uint16_t)0x0078) -#define BKP_DR26 ((uint16_t)0x007C) -#define BKP_DR27 ((uint16_t)0x0080) -#define BKP_DR28 ((uint16_t)0x0084) -#define BKP_DR29 ((uint16_t)0x0088) -#define BKP_DR30 ((uint16_t)0x008C) -#define BKP_DR31 ((uint16_t)0x0090) -#define BKP_DR32 ((uint16_t)0x0094) -#define BKP_DR33 ((uint16_t)0x0098) -#define BKP_DR34 ((uint16_t)0x009C) -#define BKP_DR35 ((uint16_t)0x00A0) -#define BKP_DR36 ((uint16_t)0x00A4) -#define BKP_DR37 ((uint16_t)0x00A8) -#define BKP_DR38 ((uint16_t)0x00AC) -#define BKP_DR39 ((uint16_t)0x00B0) -#define BKP_DR40 ((uint16_t)0x00B4) -#define BKP_DR41 ((uint16_t)0x00B8) -#define BKP_DR42 ((uint16_t)0x00BC) - -/** - * @} - */ - -/** - * @} - */ - -/** @defgroup BKP_Exported_Functions - * @{ - */ -void BKP_DeInit(void); -void BKP_WriteBackupRegister(uint16_t BKP_DR, uint16_t Data); -uint16_t BKP_ReadBackupRegister(uint16_t BKP_DR); -void BKP_RTCOutputConfig(uint16_t BKP_RTCOUTPUT); -void BKP_SetRTCCalibrationValue(uint8_t CalibrationValue); -void BKP_TamperPinConfig(uint16_t BKP_TPAL, TypeState NewValue); -void BKP_TamperINT_Enable(TypeState NewValue); -TypeState BKP_GetBitState(void); -void BKP_ClearBitState(void); -TypeState BKP_GetIntBitState(void); -void BKP_ClearIntBitState(void); - -#ifdef __cplusplus -} -#endif - -#endif /* __GD32F10X_BKP_H */ - -/** - * @} - */ - -/** - * @} - */ - -/** - * @} - */ - diff --git a/bsp/gd32103c-eval/Libraries/GD32F1xx_standard_peripheral/Include/gd32f10x_can.h b/bsp/gd32103c-eval/Libraries/GD32F1xx_standard_peripheral/Include/gd32f10x_can.h deleted file mode 100644 index a13a612566..0000000000 --- a/bsp/gd32103c-eval/Libraries/GD32F1xx_standard_peripheral/Include/gd32f10x_can.h +++ /dev/null @@ -1,512 +0,0 @@ -/** - ****************************************************************************** - * @brief CAN header file of the firmware library. - ****************************************************************************** - */ - -/* Define to prevent recursive inclusion -------------------------------------*/ -#ifndef __GD32F10X_CAN_H -#define __GD32F10X_CAN_H - -#ifdef __cplusplus -extern "C" { -#endif - -/* Includes ------------------------------------------------------------------*/ -#include "gd32f10x.h" - -/** @addtogroup GD32F10x_Firmware - * @{ - */ - -/** @addtogroup CAN - * @{ - */ - -/** @defgroup CAN_Exported_Types - * @{ - */ - -/** - * @brief CAN Initial Parameters - */ - -typedef struct { - uint16_t CAN_Prescaler; /*!< Baud rate prescaler.It can be 1 to 1024. */ - - uint8_t CAN_Mode; /*!< Set the CAN operating mode. */ - - uint8_t CAN_SJW; /*!< Set Resynchronization jump width */ - - uint8_t CAN_BS1; /*!< Set time segment 1. */ - - uint8_t CAN_BS2; /*!< Set time segment 2. */ - - TypeState CAN_TTC; /*!< Set time triggered communication mode. */ - - TypeState CAN_ABOR; /*!< Set automatic bus-off recovery. */ - - TypeState CAN_AWK; /*!< Set the automatic wake-up mode. */ - - TypeState CAN_ARD; /*!< Set the automatic retransmission mode. */ - - TypeState CAN_RFOD; /*!< Receive FIFO overwrite mode. */ - - TypeState CAN_TFO; /*!< Set the Transmit FIFO order. */ -} CAN_InitPara; - -/** - * @brief CAN filter Initial Parameters - */ - -typedef struct { - uint16_t CAN_FilterListHigh; /*!< the filter List number. - If the filter scale is 32-bit,the filter list number is MSBs. - If the filter scale is 16-bit,the filter list number is first one. - This value can take from 0x0000 to 0xFFFF */ - - uint16_t CAN_FilterListLow; /*!< the filter List number. - If the filter scale is 32-bit,the filter list number is LSBs. - If the filter scale is 16-bit,the filter list number is second one. - This value can take from 0x0000 to 0xFFFF */ - - uint16_t CAN_FilterMaskListHigh; /*!< the filter mask number or list number,according to the filter mode. - If the filter scale is 32-bit,the filter mask number or list number is MSBs. - If the filter scale is 16-bit,the filter mask number or list number is first one. - This value can take from 0x0000 to 0xFFFF */ - - uint16_t CAN_FilterMaskListLow; /*!< the filter mask number or list number,according to the filter mode. - If the filter scale is 32-bit,the filter mask number or list number is LSBs. - If the filter scale is 16-bit,the filter mask number or list number is second one. - This value can take from 0x0000 to 0xFFFF */ - - uint16_t CAN_FilterFIFOAssociation; /*!< Set the FIFO (0 or 1) which will be associated with the filter. */ - - uint8_t CAN_FilterNumber; /*!< Set the which filter to be initialized. It ranges from 0 to 13 or 0 to 27(in GD32F10X_CL). */ - - uint8_t CAN_FilterMode; /*!< Set the filter mode to be identifier mask or identifier list. */ - - uint8_t CAN_FilterScale; /*!< Set the filter scale. */ - - TypeState CAN_FilterWork; /*!< Set the filter to work or not. */ -} CAN_FilterInitPara; - -/** - * @brief CAN Tx message structure definition - */ - -typedef struct { - uint32_t StdId; /*!< Set the standard format frame identifier. - This value can take from 0 to 0x7FF. */ - - uint32_t ExtId; /*!< Set the extended format frame identifier. - This value can take from 0 to 0x1FFFFFFF. */ - - uint8_t FF; /*!< Set the format of Frame , Standard or extended Frame - for the message that will be transmitted. */ - - uint8_t FT; /*!< Set the type of frame, Data or remote - for the message that will be transmitted. */ - - uint8_t DLC; /*!< Set the length of the frame that will be transmitted. - This value can take from 0 to 8 */ - - uint8_t Data[8]; /*!< store the data that will be transmitted. - This value can take from 0 to 0xFF. */ -} CanTxMessage; - -/** - * @brief CAN Rx message structure definition - */ - -typedef struct { - uint32_t StdId; /*!< Set the standard format frame identifier. - This value can take from 0 to 0x7FF. */ - - uint32_t ExtId; /*!< Set the extended format frame identifier. - This value can take from 0 to 0x1FFFFFFF. */ - - uint8_t FF; /*!< Set the format of Frame , Standard or extended Frame - for the message that will be received. */ - - uint8_t FT; /*!< Set the type of frame, Data or remote - for the message that will be received. */ - - uint8_t DLC; /*!< Set the length of the frame that will be received. - This value can take from 0 to 8 */ - - uint8_t Data[8]; /*!< store the data that will be received. - This value can take from 0 to 0xFF. */ - - uint8_t FI; /*!< The index of the filter by which the frame is passed.. - This value can take from 0 to 0xFF */ -} CanRxMessage; - -/** - * @} - */ - -/** @defgroup CAN_Exported_Constants - * @{ - */ - -/** @defgroup CAN_sleep_constants - * @{ - */ -#define CAN_INITSTATE_FAILED ((uint8_t)0x00) /*!< CAN initialization failed */ -#define CAN_INITSTATE_SUCCESS ((uint8_t)0x01) /*!< CAN initialization OK */ - -/** - * @} - */ - -/** @defgroup CAN_Communication_Mode - * @{ - */ -#define CAN_MODE_NORMAL ((uint8_t)0x00) /*!< Normal communication mode */ -#define CAN_MODE_LOOPBACK ((uint8_t)0x01) /*!< Loopback communication mode */ -#define CAN_MODE_SILENT ((uint8_t)0x02) /*!< Silent communication mode */ -#define CAN_MODE_SILENT_LOOPBACK ((uint8_t)0x03) /*!< Loopback and silent communication mode */ - -/** - * @} - */ - - -/** - * @defgroup CAN_Working_Mode - * @{ - */ -#define CAN_WORKINGMODE_INITIAL ((uint8_t)0x00) /*!< Initial working mode */ -#define CAN_WORKINGMODE_NORMAL ((uint8_t)0x01) /*!< Normal working mode */ -#define CAN_WORKINGMODE_SLEEP ((uint8_t)0x02) /*!< Sleep working mode */ - -/** - * @} - */ - - -/** - * @defgroup CAN_Mode_State - * @{ - */ -#define CAN_MODESTATE_FAILED ((uint8_t)0x00) /*!< CAN entering the specified mode failed */ -#define CAN_MODESTATE_SUCCESS ((uint8_t)!CAN_MODESTATE_FAILED) /*!< CAN entering the specified mode Succeed */ - -/** - * @} - */ - -/** @defgroup CAN_Synchronisation_Jump_Width - * @{ - */ -#define CAN_SJW_1TQ ((uint8_t)0x00) /*!< 1 time quanta */ -#define CAN_SJW_2TQ ((uint8_t)0x01) /*!< 2 time quanta */ -#define CAN_SJW_3TQ ((uint8_t)0x02) /*!< 3 time quanta */ -#define CAN_SJW_4TQ ((uint8_t)0x03) /*!< 4 time quanta */ - -/** - * @} - */ - -/** @defgroup CAN_Time_Quanta_In_Bit_Segment_1 - * @{ - */ -#define CAN_BS1_1TQ ((uint8_t)0x00) /*!< 1 time quanta */ -#define CAN_BS1_2TQ ((uint8_t)0x01) /*!< 2 time quanta */ -#define CAN_BS1_3TQ ((uint8_t)0x02) /*!< 3 time quanta */ -#define CAN_BS1_4TQ ((uint8_t)0x03) /*!< 4 time quanta */ -#define CAN_BS1_5TQ ((uint8_t)0x04) /*!< 5 time quanta */ -#define CAN_BS1_6TQ ((uint8_t)0x05) /*!< 6 time quanta */ -#define CAN_BS1_7TQ ((uint8_t)0x06) /*!< 7 time quanta */ -#define CAN_BS1_8TQ ((uint8_t)0x07) /*!< 8 time quanta */ -#define CAN_BS1_9TQ ((uint8_t)0x08) /*!< 9 time quanta */ -#define CAN_BS1_10TQ ((uint8_t)0x09) /*!< 10 time quanta */ -#define CAN_BS1_11TQ ((uint8_t)0x0A) /*!< 11 time quanta */ -#define CAN_BS1_12TQ ((uint8_t)0x0B) /*!< 12 time quanta */ -#define CAN_BS1_13TQ ((uint8_t)0x0C) /*!< 13 time quanta */ -#define CAN_BS1_14TQ ((uint8_t)0x0D) /*!< 14 time quanta */ -#define CAN_BS1_15TQ ((uint8_t)0x0E) /*!< 15 time quanta */ -#define CAN_BS1_16TQ ((uint8_t)0x0F) /*!< 16 time quanta */ - -/** - * @} - */ - -/** @defgroup CAN_Time_Quanta_In_Bit_Segment_2 - * @{ - */ -#define CAN_BS2_1TQ ((uint8_t)0x00) /*!< 1 time quanta */ -#define CAN_BS2_2TQ ((uint8_t)0x01) /*!< 2 time quanta */ -#define CAN_BS2_3TQ ((uint8_t)0x02) /*!< 3 time quanta */ -#define CAN_BS2_4TQ ((uint8_t)0x03) /*!< 4 time quanta */ -#define CAN_BS2_5TQ ((uint8_t)0x04) /*!< 5 time quanta */ -#define CAN_BS2_6TQ ((uint8_t)0x05) /*!< 6 time quanta */ -#define CAN_BS2_7TQ ((uint8_t)0x06) /*!< 7 time quanta */ -#define CAN_BS2_8TQ ((uint8_t)0x07) /*!< 8 time quanta */ - -/** - * @} - */ - - -/** @defgroup CAN_Filter_Mode - * @{ - */ -#define CAN_FILTERMODE_MASK ((uint8_t)0x00) /*!< mask mode */ -#define CAN_FILTERMODE_LIST ((uint8_t)0x01) /*!< List mode */ - -/** - * @} - */ - -/** @defgroup CAN_Filter_Scale - * @{ - */ -#define CAN_FILTERSCALE_16BIT ((uint8_t)0x00) /*!< Two 16-bit filters */ -#define CAN_FILTERSCALE_32BIT ((uint8_t)0x01) /*!< One 32-bit filter */ - -/** - * @} - */ - -/** @defgroup CAN_Filter_FIFO - * @{ - */ -#define CAN_FILTER_FIFO0 ((uint8_t)0x00) /*!< Filter associated with FIFO0 */ -#define CAN_FILTER_FIFO1 ((uint8_t)0x01) /*!< Filter associated with FIFO1 */ - -/** - * @} - */ - -/** @defgroup CAN_Format_Frame - * @{ - */ -#define CAN_FF_STANDARD ((uint32_t)0x00000000) /*!< Standard format frame */ -#define CAN_FF_EXTENDED ((uint32_t)0x00000004) /*!< Extended format frame */ - -/** - * @} - */ - -/** @defgroup CAN_Frame_Type - * @{ - */ -#define CAN_FT_DATA ((uint32_t)0x00000000) /*!< Data frame */ -#define CAN_FT_REMOTE ((uint32_t)0x00000002) /*!< Remote frame */ - -/** - * @} - */ - -/** @defgroup CAN_Transmit_State - * @{ - */ -#define CAN_TXSTATE_FAILED ((uint8_t)0x00)/*!< CAN transmitted failure */ -#define CAN_TXSTATE_OK ((uint8_t)0x01) /*!< CAN transmitted success */ -#define CAN_TXSTATE_PENDING ((uint8_t)0x02) /*!< CAN transmitted pending */ -#define CAN_TXSTATE_NOMAILBOX ((uint8_t)0x04) /*!< No empty mailbox to be used for CAN */ - -/** - * @} - */ - -/** @defgroup CAN_Receive_FIFO_Number_Constants - * @{ - */ -#define CAN_FIFO0 ((uint8_t)0x00) /*!< Use CAN FIFO 0 to receive */ -#define CAN_FIFO1 ((uint8_t)0x01) /*!< Use CAN FIFO 1 to receive */ - -/** - * @} - */ - -/** @defgroup CAN_Sleep_Constants - * @{ - */ -#define CAN_SLEEP_FAILED ((uint8_t)0x00) /*!< CAN entered the sleep mode failed */ -#define CAN_SLEEP_OK ((uint8_t)0x01) /*!< CAN entered the sleep mode succeeded */ - -/** - * @} - */ - -/** @defgroup CAN_Wake_Wp_Constants - * @{ - */ -#define CAN_WAKEUP_FAILED ((uint8_t)0x00) /*!< CAN leaved the sleep mode failed */ -#define CAN_WAKEUP_OK ((uint8_t)0x01) /*!< CAN leaved the sleep mode succeeded */ - -/** - * @} - */ - -/** - * @defgroup CAN_Error_Type_Constants - * @{ - */ -#define CAN_ERRORTYPE_NOERR ((uint8_t)0x00) /*!< No Error */ -#define CAN_ERRORTYPE_STUFFERR ((uint8_t)0x10) /*!< Stuff Error */ -#define CAN_ERRORTYPE_FORMERR ((uint8_t)0x20) /*!< Form Error */ -#define CAN_ERRORTYPE_ACKERR ((uint8_t)0x30) /*!< Acknowledgment Error */ -#define CAN_ERRORTYPE_BITRECESSIVEERR ((uint8_t)0x40) /*!< Bit Recessive Error */ -#define CAN_ERRORTYPE_BITDOMINANTERR ((uint8_t)0x50) /*!< Bit Dominant Error */ -#define CAN_ERRORTYPE_CRCERR ((uint8_t)0x60) /*!< CRC Error */ -#define CAN_ERRORTYPE_SOFTWARESETERR ((uint8_t)0x70) /*!< Set by software */ - -/** - * @} - */ - -/** @defgroup CAN_flags - * @{ - */ -/* The flag value of 0x3XXXXXXX is used with CAN_GetBitState()and CAN_ClearBitState() functions. */ -/* The flag value of 0x1XXXXXXX is only used with CAN_GetBitState() function. */ - -/* Transmit Flags */ -#define CAN_FLAG_MTF0 ((uint32_t)0x38000001) /*!< Mailbox 0 transmit finished Flag */ -#define CAN_FLAG_MTF1 ((uint32_t)0x38000100) /*!< Mailbox 1 transmit finished Flag */ -#define CAN_FLAG_MTF2 ((uint32_t)0x38010000) /*!< Mailbox 2 transmit finished Flag */ - -/* Receive Flags */ -#define CAN_FLAG_RFL0 ((uint32_t)0x12000003) /*!< the length of the receive FIFO0 Flag */ -#define CAN_FLAG_RFF0 ((uint32_t)0x32000008) /*!< Receive FIFO 0 full Flag */ -#define CAN_FLAG_RFO0 ((uint32_t)0x32000010) /*!< Receive FIFO 0 overfull Flag */ -#define CAN_FLAG_RFL1 ((uint32_t)0x14000003) /*!< the length of the receive FIFO1 Flag */ -#define CAN_FLAG_RFF1 ((uint32_t)0x34000008) /*!< Receive FIFO 1 full Flag */ -#define CAN_FLAG_RFO1 ((uint32_t)0x34000010) /*!< Receive FIFO 1 overfull Flag */ - -/* Working Mode Flags, in CAN status register */ -#define CAN_FLAG_WU ((uint32_t)0x31000008) /*!< Wake up Flag */ -#define CAN_FLAG_SLP ((uint32_t)0x31000012) /*!< Sleep working state Flag */ - -/* Error Flags, in CAN error register */ -#define CAN_FLAG_WE ((uint32_t)0x10F00001) /*!< Warning error Flag */ -#define CAN_FLAG_PE ((uint32_t)0x10F00002) /*!< Passive error Flag */ -#define CAN_FLAG_BOE ((uint32_t)0x10F00004) /*!< Bus-off error Flag */ -#define CAN_FLAG_ET ((uint32_t)0x30F00070) /*!< Error type Flag */ - -/** - * @} - */ - - -/** @defgroup CAN_interrupts - * @{ - */ -#define CAN_INT_TME ((uint32_t)0x00000001) /*!< Transmit mailbox empty Interrupt*/ - -/* Receive Interrupts */ -#define CAN_INT_RFNE0 ((uint32_t)0x00000002) /*!< FIFO 0 not empty interrupt */ -#define CAN_INT_RFF0 ((uint32_t)0x00000004) /*!< FIFO 0 full Interrupt*/ -#define CAN_INT_RFO0 ((uint32_t)0x00000008) /*!< FIFO 0 overrun Interrupt*/ -#define CAN_INT_RFNE1 ((uint32_t)0x00000010) /*!< FIFO 1 not empty interrupt*/ -#define CAN_INT_RFF1 ((uint32_t)0x00000020) /*!< FIFO 1 full Interrupt*/ -#define CAN_INT_RFO1 ((uint32_t)0x00000040) /*!< FIFO 1 overfull Interrupt*/ - -/* Working Mode Interrupts */ -#define CAN_INT_WU ((uint32_t)0x00010000) /*!< Wake-up Interrupt*/ -#define CAN_INT_SLP ((uint32_t)0x00020000) /*!< Sleep Interrupt*/ - -/* Error Interrupts */ -#define CAN_INT_WE ((uint32_t)0x00000100) /*!< Warning error Interrupt*/ -#define CAN_INT_PE ((uint32_t)0x00000200) /*!< Passive error Interrupt*/ -#define CAN_INT_BOE ((uint32_t)0x00000400) /*!< Bus-off error Interrupt*/ -#define CAN_INT_ET ((uint32_t)0x00000800) /*!< error type Interrupt*/ -#define CAN_INT_ERR ((uint32_t)0x00008000) /*!< Error Interrupt*/ - -#define CAN_INT_MTF0 CAN_INT_TME -#define CAN_INT_MTF1 CAN_INT_TME -#define CAN_INT_MTF2 CAN_INT_TME - -/** - * @} - */ - -/** @defgroup CAN_Legacy - * @{ - */ -#define CANINITFAILED CAN_INITSTATE_FAILED -#define CANINITOK CAN_INITSTATE_SUCCESS -#define CAN_FILTERFIFO0 CAN_FILTER_FIFO0 -#define CAN_FILTERFIFO1 CAN_FILTER_FIFO1 -#define CAN_FF_STD CAN_FF_STANDARD -#define CAN_FF_EXT CAN_FF_EXTENDED -//#define CAN_FT_DATA CAN_FT_DATA -//#define CAN_FT_REMOTE CAN_FT_REMOTE -#define CANTXFAILE CAN_TXSTATE_FAILED -#define CANTXOK CAN_TXSTATE_OK -#define CANTXPENDING CAN_TXSTATE_PENDING -#define CAN_NO_MB CAN_TXSTATE_NOMAILBOX -#define CANSLEEPFAILED CAN_SLEEP_FAILED -#define CANSLEEPOK CAN_SLEEP_OK -#define CANWAKEUPFAILED CAN_WAKEUP_FAILED -#define CANWAKEUPOK CAN_WAKEUP_OK - -/** - * @} - */ - -/** - * @} - */ - - -/** @defgroup CAN_Exported_Functions - * @{ - */ -void CAN_DeInit(CAN_TypeDef *CANx); -uint8_t CAN_Init(CAN_TypeDef *CANx, CAN_InitPara *CAN_InitParaStruct); -void CAN_FilterInit(CAN_FilterInitPara *CAN_FilterInitParaStruct); -void CAN_StructInit(CAN_InitPara *CAN_InitParaStruct); -void CAN_HeaderBank(uint8_t CAN_HeaderBankNumber); -void CAN_DebugFreeze(CAN_TypeDef *CANx, TypeState NewValue); -void CAN_TimeTrigComMode_Enable(CAN_TypeDef *CANx, TypeState NewValue); - -/* Transmit functions */ -uint8_t CAN_Transmit(CAN_TypeDef *CANx, CanTxMessage *TxMessage); -uint8_t CAN_TransmitState(CAN_TypeDef *CANx, uint8_t TransmitMailbox); -void CAN_StopTransmit(CAN_TypeDef *CANx, uint8_t Mailbox); - -/* Receive functions */ -void CAN_Receive(CAN_TypeDef *CANx, uint8_t FIFONumber, CanRxMessage *RxMessage); -void CAN_FIFODequeue(CAN_TypeDef *CANx, uint8_t FIFONumber); -uint8_t CAN_MessageLength(CAN_TypeDef *CANx, uint8_t FIFONumber); - - -/* Working modes functions */ -uint8_t CAN_WorkingMode(CAN_TypeDef *CANx, uint8_t CAN_WorkingMode); -uint8_t CAN_EnterSleep(CAN_TypeDef *CANx); -uint8_t CAN_WakeUp(CAN_TypeDef *CANx); - -/* Error management functions */ -uint8_t CAN_GetErrorType(CAN_TypeDef *CANx); -uint8_t CAN_GetReceiveErrorCounter(CAN_TypeDef *CANx); -uint8_t CAN_GetTransmitErrorCounter(CAN_TypeDef *CANx); - -/* Interrupts and flags management functions */ -void CAN_INTConfig(CAN_TypeDef *CANx, uint32_t CAN_INT, TypeState NewValue); -TypeState CAN_GetBitState(CAN_TypeDef *CANx, uint32_t CAN_FLAG); -void CAN_ClearBitState(CAN_TypeDef *CANx, uint32_t CAN_FLAG); -TypeState CAN_GetIntBitState(CAN_TypeDef *CANx, uint32_t CAN_INT); -void CAN_ClearIntBitState(CAN_TypeDef *CANx, uint32_t CAN_INT); -static TypeState CheckINTState(uint32_t CAN_Reg, uint32_t Int_Bit); - -#ifdef __cplusplus -} -#endif - -#endif /* __GD32F10x_CAN_H */ -/** - * @} - */ - -/** - * @} - */ - -/** - * @} - */ diff --git a/bsp/gd32103c-eval/Libraries/GD32F1xx_standard_peripheral/Include/gd32f10x_crc.h b/bsp/gd32103c-eval/Libraries/GD32F1xx_standard_peripheral/Include/gd32f10x_crc.h deleted file mode 100644 index b4cd5d7e3b..0000000000 --- a/bsp/gd32103c-eval/Libraries/GD32F1xx_standard_peripheral/Include/gd32f10x_crc.h +++ /dev/null @@ -1,52 +0,0 @@ -/** - ****************************************************************************** - * @brief CRC header file of the firmware library. - ****************************************************************************** - */ - -/* Define to prevent recursive inclusion -------------------------------------*/ -#ifndef __GD32F10X_CRC_H -#define __GD32F10X_CRC_H - -#ifdef __cplusplus -extern "C" { -#endif - -/* Includes ------------------------------------------------------------------*/ -#include "gd32f10x.h" - -/** @addtogroup GD32F10x_Firmware - * @{ - */ - -/** @addtogroup CRC - * @{ - */ - -/** @defgroup CRC_Exported_Functions - * @{ - */ - -void CRC_ResetDTR(void); -uint32_t CRC_CalcSingleData(uint32_t CRC_data); -uint32_t CRC_CalcDataFlow(uint32_t pbuffer[], uint32_t buffer_length); -uint32_t CRC_ReadDTR(void); -void CRC_WriteFDTR(uint8_t CRC_fdtr); -uint8_t CRC_ReadFDTR(void); - -#ifdef __cplusplus -} -#endif - -#endif /*__GD32F10X_CRC_H */ -/** - * @} - */ - -/** - * @} - */ - -/** - * @} - */ diff --git a/bsp/gd32103c-eval/Libraries/GD32F1xx_standard_peripheral/Include/gd32f10x_dac.h b/bsp/gd32103c-eval/Libraries/GD32F1xx_standard_peripheral/Include/gd32f10x_dac.h deleted file mode 100644 index 95eccc7b00..0000000000 --- a/bsp/gd32103c-eval/Libraries/GD32F1xx_standard_peripheral/Include/gd32f10x_dac.h +++ /dev/null @@ -1,208 +0,0 @@ -/** - ****************************************************************************** - * @brief DAC header file of the firmware library. - ****************************************************************************** - */ - -/* Define to prevent recursive inclusion -------------------------------------*/ -#ifndef __GD32F10X_DAC_H -#define __GD32F10X_DAC_H - -#ifdef __cplusplus -extern "C" { -#endif - -/* Includes ------------------------------------------------------------------*/ -#include "gd32f10x.h" - -/** @addtogroup GD32F10x_Firmware - * @{ - */ - -/** @addtogroup DAC - * @{ - */ - -/** @defgroup DAC_Exported_Types - * @{ - */ - -/** - * @brief DAC Init structure definition - */ -typedef struct { - uint32_t DAC_Trigger; /*!< External trigger of the selected DAC channel. - This parameter can be a value of @ref DAC_Trigger */ - uint32_t DAC_WaveType; /*!< Wave type of the DAC channel, noise waves or triangle waves. - This parameter can be a value of @ref DAC_wave_type */ - uint32_t DAC_LFSRNoise_AmplitudeTriangle; /*!< The LFSR mask for noise wave generation or - the maximum amplitude triangle generation for the DAC channel. - This parameter can be a value of @ref DAC_lfsrnoise_amplitudetriangle */ - uint32_t DAC_OutputBuffer; /*!< whether the DAC channel output buffer is enabled or disabled. - This parameter can be a value of @ref DAC_OutputBuffer */ -} DAC_InitPara; - -/** - * @} - */ - -/** @defgroup DAC_Exported_Constants - * @{ - */ - -/** @defgroup DAC_Trigger - * @{ - */ -#define DAC_TRIGGER_NONE ((uint32_t)0x00000000) /*!< no trigger */ -#define DAC_TRIGGER_T2_TRIG ((uint32_t)0x00000024) /*!< TIMER2 TRIG */ -#define DAC_TRIGGER_T3_TRIG ((uint32_t)0x0000000C) /*!< TIMER3 TRIG */ -#define DAC_TRIGGER_T4_TRIG ((uint32_t)0x0000002C) /*!< TIMER4 TRIG */ -#define DAC_TRIGGER_T5_TRIG ((uint32_t)0x0000001C) /*!< TIMER5 TRIG */ -#define DAC_TRIGGER_T6_TRIG ((uint32_t)0x00000004) /*!< TIMER6 TRIG */ -#define DAC_TRIGGER_T7_TRIG ((uint32_t)0x00000014) /*!< TIMER7 TRIG */ -#define DAC_TRIGGER_T8_TRIG ((uint32_t)0x0000000C) /*!< TIMER8 TRIG */ -#define DAC_TRIGGER_T15_TRIG ((uint32_t)0x0000001C) /*!< TIMER15 TRIG */ -#define DAC_TRIGGER_EXTI_LINE9 ((uint32_t)0x00000034) /*!< EXTI Line9 event */ -#define DAC_TRIGGER_SOFTWARE ((uint32_t)0x0000003C) /*!< software trigger */ - -/** - * @} - */ - -/** @defgroup DAC_wave_type - * @{ - */ -#define DAC_WAVEGENE_NONE ((uint32_t)0x00000000) -#define DAC_WAVEGENE_NOISE ((uint32_t)0x00000040) -#define DAC_WAVEGENE_TRIANGLE ((uint32_t)0x00000080) - -/** - * @} - */ - -/** @defgroup DAC_lfsrnoise_amplitudetriangle - * @{ - */ -#define DAC_LFSR_BIT0 ((uint32_t)0x00000000) /*!< LFSR bit0 for noise wave generation */ -#define DAC_LFSR_BITS1_0 ((uint32_t)0x00000100) /*!< LFSR bit[1:0] for noise wave generation */ -#define DAC_LFSR_BITS2_0 ((uint32_t)0x00000200) /*!< LFSR bit[2:0] for noise wave generation */ -#define DAC_LFSR_BITS3_0 ((uint32_t)0x00000300) /*!< LFSR bit[3:0] for noise wave generation */ -#define DAC_LFSR_BITS4_0 ((uint32_t)0x00000400) /*!< LFSR bit[4:0] for noise wave generation */ -#define DAC_LFSR_BITS5_0 ((uint32_t)0x00000500) /*!< LFSR bit[5:0] for noise wave generation */ -#define DAC_LFSR_BITS6_0 ((uint32_t)0x00000600) /*!< LFSR bit[6:0] for noise wave generation */ -#define DAC_LFSR_BITS7_0 ((uint32_t)0x00000700) /*!< LFSR bit[7:0] for noise wave generation */ -#define DAC_LFSR_BITS8_0 ((uint32_t)0x00000800) /*!< LFSR bit[8:0] for noise wave generation */ -#define DAC_LFSR_BITS9_0 ((uint32_t)0x00000900) /*!< LFSR bit[9:0] for noise wave generation */ -#define DAC_LFSR_BITS10_0 ((uint32_t)0x00000A00) /*!< LFSR bit[10:0] for noise wave generation */ -#define DAC_LFSR_BITS11_0 ((uint32_t)0x00000B00) /*!< LFSR bit[11:0] for noise wave generation */ -#define DAC_AMPLITUDETRIANGLE_1 ((uint32_t)0x00000000) /*!< max triangle amplitude: 1 */ -#define DAC_AMPLITUDETRIANGLE_3 ((uint32_t)0x00000100) /*!< max triangle amplitude: 3 */ -#define DAC_AMPLITUDETRIANGLE_7 ((uint32_t)0x00000200) /*!< max triangle amplitude: 7 */ -#define DAC_AMPLITUDETRIANGLE_15 ((uint32_t)0x00000300) /*!< max triangle amplitude: 15 */ -#define DAC_AMPLITUDETRIANGLE_31 ((uint32_t)0x00000400) /*!< max triangle amplitude: 31 */ -#define DAC_AMPLITUDETRIANGLE_63 ((uint32_t)0x00000500) /*!< max triangle amplitude: 63 */ -#define DAC_AMPLITUDETRIANGLE_127 ((uint32_t)0x00000600) /*!< max triangle amplitude: 127 */ -#define DAC_AMPLITUDETRIANGLE_255 ((uint32_t)0x00000700) /*!< max triangle amplitude: 255 */ -#define DAC_AMPLITUDETRIANGLE_511 ((uint32_t)0x00000800) /*!< max triangle amplitude: 511 */ -#define DAC_AMPLITUDETRIANGLE_1023 ((uint32_t)0x00000900) /*!< max triangle amplitude: 1023 */ -#define DAC_AMPLITUDETRIANGLE_2047 ((uint32_t)0x00000A00) /*!< max triangle amplitude: 2047 */ -#define DAC_AMPLITUDETRIANGLE_4095 ((uint32_t)0x00000B00) /*!< max triangle amplitude: 4095 */ - -/** - * @} - */ -/** @defgroup DAC_OutputBuffer - * @{ - */ -#define DAC_OUTPUTBUFFER_ENABLE ((uint32_t)0x00000000) -#define DAC_OUTPUTBUFFER_DISABLE ((uint32_t)0x00000002) - -/** - * @} - */ - -/** @defgroup DAC_Channel_selection - * @{ - */ -#define DAC_CHANNEL_1 ((uint32_t)0x00000000) -#define DAC_CHANNEL_2 ((uint32_t)0x00000010) - -/** - * @} - */ - -/** @defgroup DAC_data_alignment - * @{ - */ -#define DAC_ALIGN_12B_R ((uint32_t)0x00000000) -#define DAC_ALIGN_12B_L ((uint32_t)0x00000004) -#define DAC_ALIGN_8B_R ((uint32_t)0x00000008) - -/** - * @} - */ - -/** @defgroup DAC_wave_generation - * @{ - */ -#define DAC_WAVE_NOISE ((uint32_t)0x00000040) -#define DAC_WAVE_TRIANGLE ((uint32_t)0x00000080) - -/** - * @} - */ - -/** @defgroup DAC_interrupts_definition - * @{ - */ -#define DAC_INT_DMAUDR ((uint32_t)0x00002000) - -/** - * @} - */ - -/** @defgroup DAC_flags_definition - * @{ - */ -#define DAC_FLAG_DMAUDR ((uint32_t)0x00002000) - -/** - * @} - */ - -/** - * @} - */ - - -/** @defgroup DAC_Exported_Functions - * @{ - */ -void DAC_DeInit(DAC_InitPara *DAC_InitParaStruct); -void DAC_Init(uint32_t DAC_Channel, DAC_InitPara *DAC_InitParaStruct); -void DAC_Enable(uint32_t DAC_Channel, TypeState NewValue); -void DAC_IntConfig(uint32_t DAC_Channel, TypeState NewValue); -void DAC_SoftwareTrigger_Enable(uint32_t DAC_Channel, TypeState NewValue); -void DAC_DualSoftwareTrigger_Enable(TypeState NewValue); -void DAC_WaveGeneration_Enable(uint32_t DAC_Channel, uint32_t DAC_Wave, TypeState NewValue); -void DAC_SetChannel1Data(uint32_t DAC_Align, uint16_t Data); -void DAC_SetChannel2Data(uint32_t DAC_Align, uint16_t Data); -void DAC_SetDualChannelData(uint32_t DAC_Align, uint16_t Data2, uint16_t Data1); -uint16_t DAC_GetDataOutputValue(uint32_t DAC_Channel); -void DAC_DMA_Enable(uint32_t DAC_Channel, TypeState NewValue); -#ifdef __cplusplus -} -#endif - -#endif /*__GD32F10X_DAC_H */ - -/** - * @} - */ - -/** - * @} - */ -/** - * @} - */ diff --git a/bsp/gd32103c-eval/Libraries/GD32F1xx_standard_peripheral/Include/gd32f10x_dma.h b/bsp/gd32103c-eval/Libraries/GD32F1xx_standard_peripheral/Include/gd32f10x_dma.h deleted file mode 100644 index 82eeba851c..0000000000 --- a/bsp/gd32103c-eval/Libraries/GD32F1xx_standard_peripheral/Include/gd32f10x_dma.h +++ /dev/null @@ -1,321 +0,0 @@ -/** - ****************************************************************************** - * @brief DMA header file of the firmware library. - ****************************************************************************** - */ - -/* Define to prevent recursive inclusion -------------------------------------*/ -#ifndef __GD32F10X_DMA_H -#define __GD32F10X_DMA_H - -#ifdef __cplusplus -extern "C" { -#endif - -/* Includes ------------------------------------------------------------------*/ -#include "gd32f10x.h" - -/** @addtogroup GD32F10x_Firmware - * @{ - */ - -/** @addtogroup DMA - * @{ - */ - -/** @defgroup DMA_Exported_Types - * @{ - */ - -/** - * @brief DMA Initial Parameters - */ - -typedef struct { - uint32_t DMA_PeripheralBaseAddr; /*!< The base address of the peripheral. */ - - uint32_t DMA_MemoryBaseAddr; /*!< The base address of the memory. */ - - uint32_t DMA_DIR; /*!< The direction of data transmission. - detailed in @ref DMA_data_transfer_direction */ - - uint32_t DMA_BufferSize; /*!< The buffer size of data transmission. */ - - uint32_t DMA_PeripheralInc; /*!< The incremented_mode of the Peripheral address register. - detailed in @ref DMA_peripheral_Address_incremented_mode */ - - uint32_t DMA_MemoryInc; /*!< The incremented_mode of the memory address register. - detailed in @ref DMA_memory_Address_incremented_mode */ - - uint32_t DMA_PeripheralDataSize; /*!< The data transmission width of Peripheral. - detailed in @ref DMA_peripheral_data_size */ - - uint32_t DMA_MemoryDataSize; /*!< The data transmission width of Memory. - detailed in @ref DMA_memory_data_size */ - - uint32_t DMA_Mode; /*!< The mode of circular transmission. - detailed in @ref DMA_circular_normal_mode */ - - uint32_t DMA_Priority; /*!< The software priority for the DMAy Channelx. - detailed in @ref DMA_priority_level */ - uint32_t DMA_MTOM; /*!< The mode of memory-to-memory transfer. - detailed in @ref DMA_memory_to_memory */ -} DMA_InitPara; - -/** - * @} - */ - -/** @defgroup DMA_Exported_Constants - * @{ - */ - -/** @defgroup DMA_data_transfer_direction - * @{ - */ - -#define DMA_DIR_PERIPHERALDST DMA_CTLR_DIR -#define DMA_DIR_PERIPHERALSRC ((uint32_t)0x00000000) -/** - * @} - */ - -/** @defgroup DMA_peripheral_Address_Increasing_mode - * @{ - */ - -#define DMA_PERIPHERALINC_ENABLE DMA_CTLR_PNAGA -#define DMA_PERIPHERALINC_DISABLE ((uint32_t)0x00000000) -/** - * @} - */ - -/** @defgroup DMA_memory_Address_Increasing_mode - * @{ - */ - -#define DMA_MEMORYINC_ENABLE DMA_CTLR_MNAGA -#define DMA_MEMORYINC_DISABLE ((uint32_t)0x00000000) -/** - * @} - */ - -/** @defgroup DMA_peripheral_data_size - * @{ - */ - -#define DMA_PERIPHERALDATASIZE_BYTE ((uint32_t)0x00000000) -#define DMA_PERIPHERALDATASIZE_HALFWORD DMA_CTLR_PSIZE_0 -#define DMA_PERIPHERALDATASIZE_WORD DMA_CTLR_PSIZE_1 -/** - * @} - */ - -/** @defgroup DMA_memory_data_size - * @{ - */ - -#define DMA_MEMORYDATASIZE_BYTE ((uint32_t)0x00000000) -#define DMA_MEMORYDATASIZE_HALFWORD DMA_CTLR_MSIZE_0 -#define DMA_MEMORYDATASIZE_WORD DMA_CTLR_MSIZE_1 -/** - * @} - */ - -/** @defgroup DMA_circular_normal_mode - * @{ - */ - -#define DMA_MODE_CIRCULAR DMA_CTLR_CIRC -#define DMA_MODE_NORMAL ((uint32_t)0x00000000) -/** - * @} - */ - -/** @defgroup DMA_priority_level - * @{ - */ - -#define DMA_PRIORITY_VERYHIGH DMA_CTLR_PRIO -#define DMA_PRIORITY_HIGH DMA_CTLR_PRIO_1 -#define DMA_PRIORITY_MEDIUM DMA_CTLR_PRIO_0 -#define DMA_PRIORITY_LOW ((uint32_t)0x00000000) -/** - * @} - */ - -/** @defgroup DMA_memory_to_memory - * @{ - */ - -#define DMA_MEMTOMEM_ENABLE DMA_CTLR_MEMTOMEM -#define DMA_MEMTOMEM_DISABLE ((uint32_t)0x00000000) -/** - * @} - */ - -/** @defgroup DMA_interrupts_definition - * @{ - */ - -#define DMA_INT_TC DMA_CTLR_TCIE -#define DMA_INT_HT DMA_CTLR_HTIE -#define DMA_INT_ERR DMA_CTLR_ERRIE - -#define DMA1_INT_GL1 DMA_IFR_GIF1 -#define DMA1_INT_TC1 DMA_IFR_TCIF1 -#define DMA1_INT_HT1 DMA_IFR_HTIF1 -#define DMA1_INT_ERR1 DMA_IFR_ERRIF1 -#define DMA1_INT_GL2 DMA_IFR_GIF2 -#define DMA1_INT_TC2 DMA_IFR_TCIF2 -#define DMA1_INT_HT2 DMA_IFR_HTIF2 -#define DMA1_INT_ERR2 DMA_IFR_ERRIF2 -#define DMA1_INT_GL3 DMA_IFR_GIF3 -#define DMA1_INT_TC3 DMA_IFR_TCIF3 -#define DMA1_INT_HT3 DMA_IFR_HTIF3 -#define DMA1_INT_ERR3 DMA_IFR_ERRIF3 -#define DMA1_INT_GL4 DMA_IFR_GIF4 -#define DMA1_INT_TC4 DMA_IFR_TCIF4 -#define DMA1_INT_HT4 DMA_IFR_HTIF4 -#define DMA1_INT_ERR4 DMA_IFR_ERRIF4 -#define DMA1_INT_GL5 DMA_IFR_GIF5 -#define DMA1_INT_TC5 DMA_IFR_TCIF5 -#define DMA1_INT_HT5 DMA_IFR_HTIF5 -#define DMA1_INT_ERR5 DMA_IFR_ERRIF5 -#define DMA1_INT_GL6 DMA_IFR_GIF6 -#define DMA1_INT_TC6 DMA_IFR_TCIF6 -#define DMA1_INT_HT6 DMA_IFR_HTIF6 -#define DMA1_INT_ERR6 DMA_IFR_ERRIF6 -#define DMA1_INT_GL7 DMA_IFR_GIF7 -#define DMA1_INT_TC7 DMA_IFR_TCIF7 -#define DMA1_INT_HT7 DMA_IFR_HTIF7 -#define DMA1_INT_ERR7 DMA_IFR_ERRIF7 - -#define DMA2_INT_GL1 ((uint32_t)0x10000001) -#define DMA2_INT_TC1 ((uint32_t)0x10000002) -#define DMA2_INT_HT1 ((uint32_t)0x10000004) -#define DMA2_INT_TE1 ((uint32_t)0x10000008) -#define DMA2_INT_GL2 ((uint32_t)0x10000010) -#define DMA2_INT_TC2 ((uint32_t)0x10000020) -#define DMA2_INT_HT2 ((uint32_t)0x10000040) -#define DMA2_INT_TE2 ((uint32_t)0x10000080) -#define DMA2_INT_GL3 ((uint32_t)0x10000100) -#define DMA2_INT_TC3 ((uint32_t)0x10000200) -#define DMA2_INT_HT3 ((uint32_t)0x10000400) -#define DMA2_INT_TE3 ((uint32_t)0x10000800) -#define DMA2_INT_GL4 ((uint32_t)0x10001000) -#define DMA2_INT_TC4 ((uint32_t)0x10002000) -#define DMA2_INT_HT4 ((uint32_t)0x10004000) -#define DMA2_INT_TE4 ((uint32_t)0x10008000) -#define DMA2_INT_GL5 ((uint32_t)0x10010000) -#define DMA2_INT_TC5 ((uint32_t)0x10020000) -#define DMA2_INT_HT5 ((uint32_t)0x10040000) -#define DMA2_INT_TE5 ((uint32_t)0x10080000) - - -/** - * @} - */ - -/** @defgroup DMA_flags_definition - * @{ - */ -#define DMA1_FLAG_GL1 DMA_IFR_GIF1 -#define DMA1_FLAG_TC1 DMA_IFR_TCIF1 -#define DMA1_FLAG_HT1 DMA_IFR_HTIF1 -#define DMA1_FLAG_ERR1 DMA_IFR_ERRIF1 -#define DMA1_FLAG_GL2 DMA_IFR_GIF2 -#define DMA1_FLAG_TC2 DMA_IFR_TCIF2 -#define DMA1_FLAG_HT2 DMA_IFR_HTIF2 -#define DMA1_FLAG_ERR2 DMA_IFR_ERRIF2 -#define DMA1_FLAG_GL3 DMA_IFR_GIF3 -#define DMA1_FLAG_TC3 DMA_IFR_TCIF3 -#define DMA1_FLAG_HT3 DMA_IFR_HTIF3 -#define DMA1_FLAG_ERR3 DMA_IFR_ERRIF3 -#define DMA1_FLAG_GL4 DMA_IFR_GIF4 -#define DMA1_FLAG_TC4 DMA_IFR_TCIF4 -#define DMA1_FLAG_HT4 DMA_IFR_HTIF4 -#define DMA1_FLAG_ERR4 DMA_IFR_ERRIF4 -#define DMA1_FLAG_GL5 DMA_IFR_GIF5 -#define DMA1_FLAG_TC5 DMA_IFR_TCIF5 -#define DMA1_FLAG_HT5 DMA_IFR_HTIF5 -#define DMA1_FLAG_ERR5 DMA_IFR_ERRIF5 -#define DMA1_FLAG_GL6 DMA_IFR_GIF6 -#define DMA1_FLAG_TC6 DMA_IFR_TCIF6 -#define DMA1_FLAG_HT6 DMA_IFR_HTIF6 -#define DMA1_FLAG_ERR6 DMA_IFR_ERRIF6 -#define DMA1_FLAG_GL7 DMA_IFR_GIF7 -#define DMA1_FLAG_TC7 DMA_IFR_TCIF7 -#define DMA1_FLAG_HT7 DMA_IFR_HTIF7 -#define DMA1_FLAG_ERR7 DMA_IFR_ERRIF7 - -#define DMA2_FLAG_GL1 ((uint32_t)0x10000001) -#define DMA2_FLAG_TC1 ((uint32_t)0x10000002) -#define DMA2_FLAG_HT1 ((uint32_t)0x10000004) -#define DMA2_FLAG_TE1 ((uint32_t)0x10000008) -#define DMA2_FLAG_GL2 ((uint32_t)0x10000010) -#define DMA2_FLAG_TC2 ((uint32_t)0x10000020) -#define DMA2_FLAG_HT2 ((uint32_t)0x10000040) -#define DMA2_FLAG_TE2 ((uint32_t)0x10000080) -#define DMA2_FLAG_GL3 ((uint32_t)0x10000100) -#define DMA2_FLAG_TC3 ((uint32_t)0x10000200) -#define DMA2_FLAG_HT3 ((uint32_t)0x10000400) -#define DMA2_FLAG_TE3 ((uint32_t)0x10000800) -#define DMA2_FLAG_GL4 ((uint32_t)0x10001000) -#define DMA2_FLAG_TC4 ((uint32_t)0x10002000) -#define DMA2_FLAG_HT4 ((uint32_t)0x10004000) -#define DMA2_FLAG_TE4 ((uint32_t)0x10008000) -#define DMA2_FLAG_GL5 ((uint32_t)0x10010000) -#define DMA2_FLAG_TC5 ((uint32_t)0x10020000) -#define DMA2_FLAG_HT5 ((uint32_t)0x10040000) -#define DMA2_FLAG_TE5 ((uint32_t)0x10080000) - -/** - * @} - */ - -/** - * @} - */ - - - -/** @defgroup DMA_Exported_Functions - * @{ - */ - -/* Function used to reset the DMA configuration */ -void DMA_DeInit(DMA_Channel_TypeDef *DMAy_Channelx); - -/* The functions of Initialization and Configuration */ -void DMA_Init(DMA_Channel_TypeDef *DMAy_Channelx, DMA_InitPara *DMA_InitParaStruct); -void DMA_ParaInit(DMA_InitPara *DMA_InitParaStruct); -void DMA_Enable(DMA_Channel_TypeDef *DMAy_Channelx, TypeState NewValue); - -/* The functions of Data Counter */ -void DMA_SetCurrDataCounter(DMA_Channel_TypeDef *DMAy_Channelx, uint16_t DataNumber); -uint16_t DMA_GetCurrDataCounter(DMA_Channel_TypeDef *DMAy_Channelx); - -/* The functions of Interrupts and flags management */ -void DMA_INTConfig(DMA_Channel_TypeDef *DMAy_Channelx, uint32_t DMA_INT, TypeState NewValue); -TypeState DMA_GetBitState(uint32_t DMA_FLAG); -void DMA_ClearBitState(uint32_t DMA_FLAG); -TypeState DMA_GetIntBitState(uint32_t DMA_INT); -void DMA_ClearIntBitState(uint32_t DMA_INT); - -#ifdef __cplusplus -} -#endif - -#endif /*__GD32F10x_DMA_H */ -/** - * @} - */ - -/** - * @} - */ - -/** - * @} - */ diff --git a/bsp/gd32103c-eval/Libraries/GD32F1xx_standard_peripheral/Include/gd32f10x_eth.h b/bsp/gd32103c-eval/Libraries/GD32F1xx_standard_peripheral/Include/gd32f10x_eth.h deleted file mode 100644 index 6500a8a9ea..0000000000 --- a/bsp/gd32103c-eval/Libraries/GD32F1xx_standard_peripheral/Include/gd32f10x_eth.h +++ /dev/null @@ -1,1407 +0,0 @@ -/** - ****************************************************************************** - * @brief ETH header file of the firmware library. - ****************************************************************************** - */ - -/* Define to prevent recursive inclusion -------------------------------------*/ -#ifndef __GD32F10X_ETH_H -#define __GD32F10X_ETH_H -#define IF_USE_EXTERNPHY_LIB 0 - -#ifdef __cplusplus -extern "C" { -#endif - -/* Includes ------------------------------------------------------------------*/ -#include "gd32f10x.h" -#if (1 == IF_USE_EXTERNPHY_LIB) -#include "phy.h" -#endif - -/** @addtogroup GD32F10x_Firmware - * @{ - */ - -/** @addtogroup ETH - * @{ - */ - -/** @defgroup ETH_Exported_Types - * @{ - */ - -/** - * @brief ETH MAC Initial Parameters - */ -typedef struct { - /** - * @brief / * MAC - */ - uint32_t ETH_MAC_AutoNegotiation; /*!< Enable or disable external PHY's AutoNegotiation function - detailed in @ref ETH_AutoNegotiation */ - - uint32_t ETH_MAC_Watchdog; /*!< Enable or disable the Watchdog timer - detailed in @ref ETH_watchdog */ - - uint32_t ETH_MAC_Jabber; /*!< Enable or disable Jabber timer - detailed in @ref ETH_Jabber */ - - uint32_t ETH_MAC_InterFrameGap; /*!< Set the gap of two frames when transmission - detailed in @ref ETH_Inter_Frame_Gap */ - - uint32_t ETH_MAC_CarrierSense; /*!< Enable or disable the Carrier Sense - detailed in @ref ETH_Carrier_Sense */ - - uint32_t ETH_MAC_Speed; /*!< Set the Ethernet speed, detailed in @ref ETH_Speed */ - - - uint32_t ETH_MAC_ReceiveOwn; /*!< Enable or disable the ReceiveOwn mode - detailed in @ref ETH_Receive_Own */ - - uint32_t ETH_MAC_LoopbackMode; /*!< Enable or disable the MAC Loopback mode - detailed in @ref ETH_Loop_Back_Mode */ - - uint32_t ETH_MAC_Mode; /*!< Set the MAC duplex mode, detailed in @ref ETH_Duplex_Mode */ - - uint32_t ETH_MAC_ChecksumOffload; /*!< Enable or disable the IPv4(TCP/UDP/ICMP headers) checksum checking when reception - detailed in @ref ETH_Checksum_Offload */ - - uint32_t ETH_MAC_RetryTransmission; /*!< Enable or disable the MAC attempt retries transmission in Half-Duplex mode when a colision occurs - detailed in @ref ETH_Retry_Transmission */ - - uint32_t ETH_MAC_AutomaticPadCRCDrop; /*!< Enable or disable the Automatic Pad/CRC Drop - detailed in @ref ETH_Automatic_Pad_CRC_Drop */ - - uint32_t ETH_MAC_BackOffLimit; /*!< Set the BackOff limit value, detailed in @ref ETH_Back_Off_Limit */ - - uint32_t ETH_MAC_DeferralCheck; /*!< Enable or disable the deferral check function only in Half-Duplex mode - detailed in @ref ETH_Deferral_Check */ - - uint32_t ETH_MAC_FilterDisable; /*!< Enable or disable the MAC filter, detailed in @ref ETH_Filter_Disable */ - - uint32_t ETH_MAC_SourceAddrFilter; /*!< Set the SA Filter mode, detailed in @ref ETH_Source_Addr_Filter */ - - uint32_t ETH_MAC_PassControlFrames; /*!< Set the mode of the control frames (including unicast and multicast PAUSE frames) - detailed in @ref ETH_Pass_Control_Frames */ - - uint32_t ETH_MAC_BroadcastFramesReception; /*!< Enable or disable the reception of Broadcast Frames - detailed in @ref ETH_Broadcast_Frames_Reception */ - - uint32_t ETH_MAC_DestinationAddrFilter; /*!< Set the DA filter mode, detailed in @ref ETH_Destination_Addr_Filter */ - - uint32_t ETH_MAC_PromiscuousMode; /*!< Enable or disable the Promiscuous Mode - detailed in @ref ETH_Promiscuous_Mode */ - - uint32_t ETH_MAC_MulticastFramesFilter; /*!< Set the Multicast Frames filter mode - detailed in @ref ETH_Multicast_Frames_Filter */ - - uint32_t ETH_MAC_UnicastFramesFilter; /*!< Set the Unicast Frames filter mode - detailed in @ref ETH_Unicast_Frames_Filter */ - - uint32_t ETH_MAC_HashListHigh; /*!< Hash list higher 32 bits */ - - uint32_t ETH_MAC_HashListLow; /*!< Hash list lower 32 bits */ - - uint32_t ETH_MAC_PauseTime; /*!< Set the Pause Time field value in the transmit control frame */ - - uint32_t ETH_MAC_ZeroQuantaPause; /*!< Enable or disable the automatic generation of Zero-Quanta Pause Control frames - detailed in @ref ETH_Zero_Quanta_Pause */ - - uint32_t ETH_MAC_PauseLowThreshold; /*!< Set the threshold of the PAUSE to be checked for - automatic retransmission of PAUSE Frame - detailed in @ref ETH_Pause_Low_Threshold */ - - uint32_t ETH_MAC_FlowControlDeactiveThreshold;/*!< Set the threshold of the deactive flow control - detailed in @ref ETH_RFD_Threshold */ - - uint32_t ETH_MAC_FlowControlActiveThreshold; /*!< Set the threshold of the active flow control - detailed in @ref ETH_RFA_Threshold */ - - uint32_t ETH_MAC_UnicastPauseFrameDetect; /*!< Enable or disable the unicast Pause frames detection - detailed in @ref ETH_Unicast_Pause_Frame_Detect */ - - uint32_t ETH_MAC_ReceiveFlowControl; /*!< Enable or disable the MAC to received Pause frame - detailed in @ref ETH_Receive_Flow_Control */ - - uint32_t ETH_MAC_TransmitFlowControl; /*!< Enable or disable the MAC to transmit Pause frames in Full-Duplex mode - or back-pressure operation in Half-Duplex mode - detailed in @ref ETH_Transmit_Flow_Control */ - - uint32_t ETH_MAC_VLANTagComparison; /*!< Set VLAN tag comparison and filtering mode - detailed in @ref ETH_VLAN_Tag_Comparison */ - - uint32_t ETH_MAC_VLANTagIdentifier; /*!< Set VLAN tag identifier for receive frames */ - - /** - * @brief / * DMA - */ - - uint32_t ETH_DMA_DropTCPIPChecksumErrorFrame; /*!< Enable or disable the TCP/IP Checksum Error Frames drop - detailed in @ref ETH_Drop_TCP_IP_Checksum_Error_Frame */ - - uint32_t ETH_DMA_ReceiveStoreForward; /*!< Set the Rx FIFO operation mode - detailed in @ref ETH_Receive_Store_Forward */ - - uint32_t ETH_DMA_FlushReceivedFrame; /*!< Enable or disable the flushing Receive FIFO - detailed in @ref ETH_Flush_Received_Frame */ - - uint32_t ETH_DMA_TransmitStoreForward; /*!< Enable or disable Tx FIFO operation mode - detailed in @ref ETH_Transmit_Store_Forward */ - - uint32_t ETH_DMA_TransmitThresholdControl; /*!< Enable or disable the Transmit Threshold Control and set the level - detailed in @ref ETH_Transmit_Threshold_Control */ - - uint32_t ETH_DMA_ForwardErrorFrames; /*!< Enable or disable receive the erroneous frames to the DMA - detailed in @ref ETH_Forward_Error_Frames */ - - uint32_t ETH_DMA_ForwardUndersizedGoodFrames; /*!< Enable or disable receive the Undersized frames with no Error - and length less than 64 bytes including pad-bytes and CRC to the DMA - detailed in @ref ETH_Forward_Undersized_Good_Frames */ - - uint32_t ETH_DMA_ReceiveThresholdControl; /*!< Enable or disable the Receive Threshold Control and set the level - detailed in @ref ETH_Receive_Threshold_Control */ - - uint32_t ETH_DMA_SecondFrameOperate; /*!< Enable or disable the Operate on second frame mode - detailed in @ref ETH_Second_Frame_Operate */ - - uint32_t ETH_DMA_AddressAligned; /*!< Enable or disable the Address Aligned - detailed in @ref ETH_Address_Aligned */ - - uint32_t ETH_DMA_FixedBurst; /*!< Enable or disable the AHB Master interface fixed burst transfers - detailed in @ref ETH_Fixed_Burst */ - - uint32_t ETH_DMA_RxDMABurstLength; /*!< Set the maximum number of beats to be transferred in one Rx DMA transaction - detailed in @ref ETH_Rx_DMA_Burst_Length */ - - uint32_t ETH_DMA_TxDMABurstLength; /*!< Set the maximum number of beats to be transferred in one Tx DMA transaction - detailed in @ref ETH_Tx_DMA_Burst_Length */ - - uint32_t ETH_DMA_DescriptorSkipLength; /*!< Set the number of word to skip between two descriptors only in Ring mode */ - - uint32_t ETH_DMA_Arbitration; /*!< Set the DMA Tx/Rx priority ratio - detailed in @ref ETH_DMA_Arbitration */ -} ETH_InitPara; - -/** - * @brief ETH DMA Desciptors structure def - */ -typedef struct { - uint32_t Status; /*!< Status */ - uint32_t ControlBufferSize; /*!< Control and Buffer1, Buffer2 lengths */ - uint32_t Buffer1Addr; /*!< Buffer1 address pointer */ - uint32_t Buffer2NextDescAddr; /*!< Buffer2 or next descriptor address pointer */ -} ETH_DMADESCTypeDef; - -/** - * @} - */ - -/** @defgroup ETH_Exported_Constants - * @{ - */ - -/** @defgroup ETH_delay_Def - * @{ - */ -/* #define USE_Delay */ - -#ifdef USE_Delay -#define _eth_delay_ Delay /*!< User can provide more timing precise _eth_delay_ function */ -#else -#define _eth_delay_ ETH_Delay /*!< Default _eth_delay_ function with less precise timing */ -#endif - -/** - * @} - */ - -/** @defgroup ETH_Buffer_Def - * @{ - */ -#define ETH_MAX_FRAME_SIZE 1520 /*!< FRAME_HEADER + FRAME_EXTRA + MAX_FRAME_PAYLOAD + FRAME_CRC */ -#define ETH_HEADER 14 /*!< 6 byte DA, 6 byte SA, 2 byte length/type */ -#define ETH_CRC 4 /*!< 4 byte CRC */ -#define ETH_EXTRA 2 /*!< Extra bytes in some cases */ -#define VLAN_TAG 4 /*!< optional 802.1q VLAN Tag */ -#define MIN_ETH_DATALENGTH 46 /*!< Minimum Eth payload byte */ -#define MAX_ETH_DATALENGTH 1500 /*!< Maximum Eth payload byte */ -#define JUMBO_FRAME_DATALENGTH 9000 /*!< Jumbo frame payload byte */ - -/** - DMA Tx Desciptor - ----------------------------------------------------------------------------------------------- - TDES0 | BUSY(31) | CTRL[30:26] | Reserved[25:24] | CTRL[23:20] | Reserved[19:17] | Status[16:0] | - ----------------------------------------------------------------------------------------------- - TDES1 | Reserved[31:29] | Buffer2 ByteCount[28:16] | Reserved[15:13] | Buffer1 ByteCount[12:0] | - ----------------------------------------------------------------------------------------------- - TDES2 | Buffer1 Address [31:0] | - ----------------------------------------------------------------------------------------------- - TDES3 | Buffer2 Address [31:0] / Next Desciptor Address [31:0] | - ----------------------------------------------------------------------------------------------- -*/ - -/** - * @brief DMA Tx descriptor TDES0 register Bit def - */ -#define ETH_DMATXDESC_BUSY ((uint32_t)0x80000000) /*!< DMA or CPU control descriptor*/ -#define ETH_DMATXDESC_INTC ((uint32_t)0x40000000) /*!< Interrupt on Completion */ -#define ETH_DMATXDESC_LSG ((uint32_t)0x20000000) /*!< contains the last segment of the frame */ -#define ETH_DMATXDESC_FSG ((uint32_t)0x10000000) /*!< contains the first segment of the frame */ -#define ETH_DMATXDESC_DCRC ((uint32_t)0x08000000) /*!< Disable CRC */ -#define ETH_DMATXDESC_DPAD ((uint32_t)0x04000000) /*!< Disable Pad */ -#define ETH_DMATXDESC_TTSEN ((uint32_t)0x02000000) /*!< Transmit Time Stamp Enable */ -#define ETH_DMATXDESC_CM ((uint32_t)0x00C00000) /*!< Checksum Mode: 4 cases */ -#define ETH_DMATXDESC_CM_DISABLE ((uint32_t)0x00000000) /*!< Checksum Insertion disabled */ -#define ETH_DMATXDESC_CM_IPV4HEADER ((uint32_t)0x00400000) /*!< Only IP header checksum calculation and insertion are enabled */ -#define ETH_DMATXDESC_CM_TCPUDPICMP_SEGMENT ((uint32_t)0x00800000) /*!< TCP/UDP/ICMP Checksum Insertion calculated but pseudo-header */ -#define ETH_DMATXDESC_CM_TCPUDPICMP_FULL ((uint32_t)0x00C00000) /*!< TCP/UDP/ICMP Checksum Insertion fully calculated */ -#define ETH_DMATXDESC_TERM ((uint32_t)0x00200000) /*!< Transmit End of Ring Mode*/ -#define ETH_DMATXDESC_TCHM ((uint32_t)0x00100000) /*!< Transmit des Chained Mode*/ -#define ETH_DMATXDESC_TTMSS ((uint32_t)0x00020000) /*!< Tx Time Stamp Status */ -#define ETH_DMATXDESC_IPHE ((uint32_t)0x00010000) /*!< IP Header Error: IP4 or IP6*/ -#define ETH_DMATXDESC_ES ((uint32_t)0x00008000) /*!< Error summary */ -#define ETH_DMATXDESC_JT ((uint32_t)0x00004000) /*!< Jabber Timeout */ -#define ETH_DMATXDESC_FRMF ((uint32_t)0x00002000) /*!< clean FIFO */ -#define ETH_DMATXDESC_IPPE ((uint32_t)0x00001000) /*!< IP Payload Error */ -#define ETH_DMATXDESC_LCA ((uint32_t)0x00000800) /*!< Loss of Carrier */ -#define ETH_DMATXDESC_NCA ((uint32_t)0x00000400) /*!< No Carrier */ -#define ETH_DMATXDESC_LCO ((uint32_t)0x00000200) /*!< Late Collision */ -#define ETH_DMATXDESC_ECO ((uint32_t)0x00000100) /*!< abort transmission due to collision */ -#define ETH_DMATXDESC_VFRM ((uint32_t)0x00000080) /*!< VLAN Frame */ -#define ETH_DMATXDESC_COCNT ((uint32_t)0x00000078) /*!< Collision Count */ -#define ETH_DMATXDESC_EXD ((uint32_t)0x00000004) /*!< Excessive Deferral */ -#define ETH_DMATXDESC_UFE ((uint32_t)0x00000002) /*!< late data arrival from the memory */ -#define ETH_DMATXDESC_DB ((uint32_t)0x00000001) /*!< Deferred Bit */ - -/** - * @brief DMA Tx descriptor TDES1 register Bit def - */ -#define ETH_DMATXDESC_TB2S ((uint32_t)0x1FFF0000) /*!< Transmit Buffer2 Size */ -#define ETH_DMATXDESC_TB1S ((uint32_t)0x00001FFF) /*!< Transmit Buffer1 Size */ - -/** - * @brief DMA Tx descriptor TDES2 register Bit def - */ -#define ETH_DMATXDESC_TB1AP ((uint32_t)0xFFFFFFFF) /*!< Buffer1 Address Pointer */ - -/** - * @brief DMA Tx descriptor TDES3 register Bit def - */ -#define ETH_DMATXDESC_TB2AP ((uint32_t)0xFFFFFFFF) /*!< Buffer2 Address Pointer */ - -/** - * @} - */ - - -/** @defgroup DMA_Rx_descriptor - * @{ - */ - -/** - DMA Rx Desciptor - -------------------------------------------------------------------------------------------------------------------- - RDES0 | BUSY(31) | Status [30:0] | - --------------------------------------------------------------------------------------------------------------------- - RDES1 | CTRL(31) | Reserved[30:29] | Buffer2 ByteCount[28:16] | CTRL[15:14] | Reserved(13) | Buffer1 ByteCount[12:0] | - --------------------------------------------------------------------------------------------------------------------- - RDES2 | Buffer1 Address [31:0] | - --------------------------------------------------------------------------------------------------------------------- - RDES3 | Buffer2 Address [31:0] / Next Desciptor Address [31:0] | - --------------------------------------------------------------------------------------------------------------------- -*/ - -/** - * @brief DMA Rx descriptor RDES0 register Bit def - */ -#define ETH_DMARXDESC_BUSY ((uint32_t)0x80000000) /*!< DMA or CPU control descriptor */ -#define ETH_DMARXDESC_DAFF ((uint32_t)0x40000000) /*!< DA filter fail */ -#define ETH_DMARXDESC_FRML ((uint32_t)0x3FFF0000) /*!< Frame length */ -#define ETH_DMARXDESC_ERRS ((uint32_t)0x00008000) /*!< Error summary */ -#define ETH_DMARXDESC_DERR ((uint32_t)0x00004000) /*!< no more descriptors for receive frame */ -#define ETH_DMARXDESC_SAFF ((uint32_t)0x00002000) /*!< SA filter fail */ -#define ETH_DMARXDESC_LERR ((uint32_t)0x00001000) /*!< Frame size not matching with length field */ -#define ETH_DMARXDESC_OERR ((uint32_t)0x00000800) /*!< FIFO Overflow Error */ -#define ETH_DMARXDESC_VTAG ((uint32_t)0x00000400) /*!< VLAN Tag: a VLAN frame tag */ -#define ETH_DMARXDESC_FDES ((uint32_t)0x00000200) /*!< First descriptor of the frame */ -#define ETH_DMARXDESC_LDES ((uint32_t)0x00000100) /*!< Last descriptor of the frame */ -#define ETH_DMARXDESC_IPHCERR ((uint32_t)0x00000080) /*!< IPC Checksum Error: Rx Ipv4 or Ipv6 header checksum error */ -#define ETH_DMARXDESC_LCO ((uint32_t)0x00000040) /*!< Late collision occurred during reception */ -#define ETH_DMARXDESC_FRMT ((uint32_t)0x00000020) /*!< Frame type */ -#define ETH_DMARXDESC_RWDT ((uint32_t)0x00000010) /*!< Receive WD Timeout */ -#define ETH_DMARXDESC_RERR ((uint32_t)0x00000008) /*!< the RX_ERR signal is asserted while RX_DV is asserted during frame reception */ -#define ETH_DMARXDESC_DBERR ((uint32_t)0x00000004) /*!< received frame has a non int multiple of bytes */ -#define ETH_DMARXDESC_CERR ((uint32_t)0x00000002) /*!< CRC error */ -#define ETH_DMARXDESC_PCERR ((uint32_t)0x00000001) /*!< Receive MAC address matched/ Receive Payload Checksum Error */ - -/** - * @brief DMA Rx descriptor RDES1 register Bit def - */ -#define ETH_DMARXDESC_DINTC ((uint32_t)0x80000000) /*!< Disable Interrupt on Completion */ -#define ETH_DMARXDESC_RB2S ((uint32_t)0x1FFF0000) /*!< Receive Buffer2 Size */ -#define ETH_DMARXDESC_RERM ((uint32_t)0x00008000) /*!< Receive End of Ring mode*/ -#define ETH_DMARXDESC_RCHM ((uint32_t)0x00004000) /*!< Receive des Chained mode */ -#define ETH_DMARXDESC_RB1S ((uint32_t)0x00001FFF) /*!< Receive Buffer1 Size */ - -/** - * @brief DMA Rx descriptor RDES2 register Bit def - */ -#define ETH_DMARXDESC_RB1AP ((uint32_t)0xFFFFFFFF) /*!< Buffer1 Address Pointer */ - -/** - * @brief DMA Rx descriptor RDES3 register Bit def - */ -#define ETH_DMARXDESC_RB2AP ((uint32_t)0xFFFFFFFF) /*!< Buffer2 Address Pointer */ - -#ifndef _PHY_H_ -#define DP83848 0 -#define LAN8700 1 -#define PHY_TYPE DP83848 - -/** - * @} - */ - -/** @defgroup PHY_Read_write_Timeouts - * @{ - */ -#define PHY_READ_TO ((uint32_t)0x0004FFFF) -#define PHY_WRITE_TO ((uint32_t)0x0004FFFF) - -/** - * @} - */ - -/** @defgroup PHY_Reset_Delay - * @{ - */ -#define PHY_RESETDELAY ((uint32_t)0x000FFFFF) - -/** - * @} - */ - -/** @defgroup PHY_Config_Delay - * @{ - */ -#define PHY_CONFIGDELAY ((uint32_t)0x00FFFFFF) - -/** - * @} - */ - -/** @defgroup PHY_Register_address - * @{ - */ -#define PHY_BCR 0 /*!< Tranceiver Basic Control Register */ -#define PHY_BSR 1 /*!< Tranceiver Basic Status Register */ - -/** - * @} - */ - -/** @defgroup PHY_basic_Control_register - * @{ - */ -#define PHY_RESET ((u16)0x8000) /*!< PHY Reset */ -#define PHY_LOOPBACK ((u16)0x4000) /*!< Enable loop-back mode */ -#define PHY_FULLDUPLEX_100M ((u16)0x2100) /*!< Configure speed to 100 Mb/s and the full-duplex mode */ -#define PHY_HALFDUPLEX_100M ((u16)0x2000) /*!< Configure speed to 100 Mb/s and the half-duplex mode */ -#define PHY_FULLDUPLEX_10M ((u16)0x0100) /*!< Configure speed to 10 Mb/s and the full-duplex mode */ -#define PHY_HALFDUPLEX_10M ((u16)0x0000) /*!< Configure speed to 10 Mb/s and the half-duplex mode */ -#define PHY_AUTONEGOTIATION ((u16)0x1000) /*!< Enable auto-negotiation function */ -#define PHY_RESTART_AUTONEGOTIATION ((u16)0x0200) /*!< Restart auto-negotiation function */ -#define PHY_POWERDOWN ((u16)0x0800) /*!< Enable the power down mode */ -#define PHY_ISOLATE ((u16)0x0400) /*!< Isolate PHY from MII */ - -/** - * @} - */ - -/** @defgroup PHY_basic_status_register - * @{ - */ -#define PHY_AUTONEGO_COMPLETE ((u16)0x0020) /*!< Auto-Negotioation process completed */ -#define PHY_LINKED_STATUS ((u16)0x0004) /*!< Valid link established */ -#define PHY_JABBER_DETECTION ((u16)0x0002) /*!< Jabber condition detected */ - -/** - * @} - */ - -/** @defgroup PHY_status_register - * @{ - */ -/* The PHY status register value change with PHY in different Manufacturer - so the user can use external PHY lib to update this value if PHY types user selected not included in firmware */ -#if(PHY_TYPE == LAN8700) -/** - * @brief For LAN8700 - */ -#define PHY_SR 31 /*!< Tranceiver Status Register */ -/* The Speed and Duplex mask values change with PHY in different Manufacturer - so the user can use external PHY lib to update this value if PHY types user selected not included in firmware */ -#define PHY_Speed_Status ((u16)0x0004) /*!< Configured information of Speed: 10Mbps */ -#define PHY_DUPLEX_STATUS ((u16)0x0010) /*!< Configured information of Duplex: Full-duplex */ - -#elif(PHY_TYPE == DP83848) -/** - * @brief For DP83848 - */ -#define PHY_SR 16 /*!< Tranceiver Status Register */ -/* The Speed and Duplex mask values change with PHY in different Manufacturer - so the user can use external PHY lib to update this value if PHY types user selected not included in firmware */ -#define PHY_SPEED_STATUS ((u16)0x0002) /*!< Configured information of Speed: 10Mbps */ -#define PHY_DUPLEX_STATUS ((u16)0x0004) /*!< Configured information of Duplex: Full-duplex */ - -#define PHY_Reset PHY_RESETDELAY -#define PHY_ResetDelay PHY_RESETDELAY -#define PHY_Speed_Status PHY_SPEED_STATUS - -#endif - -#endif - - -/** - * @} - */ - -/** @defgroup ETH_AutoNegotiation - * @{ - */ -#define ETH_AUTONEGOTIATION_ENABLE ((uint32_t)0x00000001) -#define ETH_AUTONEGOTIATION_DISABLE ((uint32_t)0x00000000) - -/** - * @} - */ - -/** @defgroup ETH_watchdog - * @{ - */ -#define ETH_WATCHDOG_ENABLE ((uint32_t)0x00000000) -#define ETH_WATCHDOG_DISABLE ((uint32_t)0x00800000) - -/** - * @} - */ - -/** @defgroup ETH_Jabber - * @{ - */ -#define ETH_JABBER_ENABLE ((uint32_t)0x00000000) -#define ETH_JABBER_DISABLE ((uint32_t)0x00400000) - -/** - * @} - */ - -/** @defgroup ETH_Inter_Frame_Gap - * @{ - */ -#define ETH_INTERFRAMEGAP_96BIT ((uint32_t)0x00000000) -#define ETH_INTERFRAMEGAP_88BIT ((uint32_t)0x00020000) -#define ETH_INTERFRAMEGAP_80BIT ((uint32_t)0x00040000) -#define ETH_INTERFRAMEGAP_72BIT ((uint32_t)0x00060000) -#define ETH_INTERFRAMEGAP_64BIT ((uint32_t)0x00080000) -#define ETH_INTERFRAMEGAP_56BIT ((uint32_t)0x000A0000) -#define ETH_INTERFRAMEGAP_48BIT ((uint32_t)0x000C0000) -#define ETH_INTERFRAMEGAP_40BIT ((uint32_t)0x000E0000) - - -/** - * @} - */ - -/** @defgroup ETH_Carrier_Sense - * @{ - */ -#define ETH_CARRIERSENSE_ENABLE ((uint32_t)0x00000000) -#define ETH_CARRIERSENSE_DISABLE ((uint32_t)0x00010000) - -/** - * @} - */ - -/** @defgroup ETH_Speed - * @{ - */ -#define ETH_SPEEDMODE_10M ((uint32_t)0x00000000) -#define ETH_SPEEDMODE_100M ((uint32_t)0x00004000) - -/** - * @} - */ - -/** @defgroup ETH_Receive_Own - * @{ - */ -#define ETH_RECEIVEOWN_ENABLE ((uint32_t)0x00000000) -#define ETH_RECEIVEOWN_DISABLE ((uint32_t)0x00002000) - - -/** - * @} - */ - -/** @defgroup ETH_Loop_Back_Mode - * @{ - */ -#define ETH_LOOPBACKMODE_ENABLE ((uint32_t)0x00001000) -#define ETH_LOOPBACKMODE_DISABLE ((uint32_t)0x00000000) - - -/** - * @} - */ - -/** @defgroup ETH_Duplex_Mode - * @{ - */ -#define ETH_MODE_FULLDUPLEX ((uint32_t)0x00000800) -#define ETH_MODE_HALFDUPLEX ((uint32_t)0x00000000) - - -/** - * @} - */ - -/** @defgroup ETH_Checksum_Offload - * @{ - */ -#define ETH_CHECKSUMOFFLOAD_ENABLE ((uint32_t)0x00000400) -#define ETH_CHECKSUMOFFLOAD_DISABLE ((uint32_t)0x00000000) - - -/** - * @} - */ - -/** @defgroup ETH_Retry_Transmission - * @{ - */ -#define ETH_RETRYTRANSMISSION_ENABLE ((uint32_t)0x00000000) -#define ETH_RETRYTRANSMISSION_DISABLE ((uint32_t)0x00000200) - - -/** - * @} - */ - -/** @defgroup ETH_Automatic_Pad_CRC_Drop - * @{ - */ -#define ETH_AUTOMATICPADCRCDROP_ENABLE ((uint32_t)0x00000080) -#define ETH_AUTOMATICPADCRCDROP_DISABLE ((uint32_t)0x00000000) - -/** - * @} - */ - -/** @defgroup ETH_Back_Off_Limit - * @{ - */ -#define ETH_BACKOFFLIMIT_10 ((uint32_t)0x00000000) -#define ETH_BACKOFFLIMIT_8 ((uint32_t)0x00000020) -#define ETH_BACKOFFLIMIT_4 ((uint32_t)0x00000040) -#define ETH_BACKOFFLIMIT_1 ((uint32_t)0x00000060) - -/** - * @} - */ - -/** @defgroup ETH_Deferral_Check - * @{ - */ -#define ETH_DEFERRALCHECK_ENABLE ((uint32_t)0x00000010) -#define ETH_DEFERRALCHECK_DISABLE ((uint32_t)0x00000000) - -/** - * @} - */ - -/** @defgroup ETH_Filter_Disable - * @{ - */ -#define ETH_FILTERDISABLE_ENABLE ((uint32_t)0x80000000) -#define ETH_FILTERDISABLE_DISABLE ((uint32_t)0x00000000) - -/** - * @} - */ - -/** @defgroup ETH_Source_Addr_Filter - * @{ - */ -#define ETH_SOURCEADDRFILTER_NORMAL_ENABLE ((uint32_t)0x00000200) -#define ETH_SOURCEADDRFILTER_INVERSE_ENABLE ((uint32_t)0x00000300) -#define ETH_SOURCEADDRFILTER_DISABLE ((uint32_t)0x00000000) - -/** - * @} - */ - -/** @defgroup ETH_Pass_Control_Frames - * @{ - */ -#define ETH_PASSCONTROLFRAMES_BLOCKALL ((uint32_t)0x00000040) -#define ETH_PASSCONTROLFRAMES_FORWARDALL ((uint32_t)0x00000080) -#define ETH_PASSCONTROLFRAMES_FORWARDPASSEDADDRFILTER ((uint32_t)0x000000C0) - -/** - * @} - */ - -/** @defgroup ETH_Broadcast_Frames_Reception - * @{ - */ -#define ETH_BROADCASTFRAMESRECEPTION_ENABLE ((uint32_t)0x00000000) -#define ETH_BROADCASTFRAMESRECEPTION_DISABLE ((uint32_t)0x00000020) - -/** - * @} - */ - -/** @defgroup ETH_Destination_Addr_Filter - * @{ - */ -#define ETH_DESTINATIONADDRFILTER_NORMAL ((uint32_t)0x00000000) -#define ETH_DESTINATIONADDRFILTER_INVERSE ((uint32_t)0x00000008) - -/** - * @} - */ - -/** @defgroup ETH_Promiscuous_Mode - * @{ - */ -#define ETH_PROMISCUOUSMODE_ENABLE ((uint32_t)0x00000001) -#define ETH_PROMISCUOUSMODE_DISABLE ((uint32_t)0x00000000) - -/** - * @} - */ - -/** @defgroup ETH_Multicast_Frames_Filter - * @{ - */ -#define ETH_MULTICASTFRAMESFILTER_PERFECTHASHTABLE ((uint32_t)0x00000404) -#define ETH_MULTICASTFRAMESFILTER_HASHTABLE ((uint32_t)0x00000004) -#define ETH_MULTICASTFRAMESFILTER_PERFECT ((uint32_t)0x00000000) -#define ETH_MULTICASTFRAMESFILTER_NONE ((uint32_t)0x00000010) - - -/** - * @} - */ - -/** @defgroup ETH_Unicast_Frames_Filter - * @{ - */ -#define ETH_UNICASTFRAMESFILTER_PERFECTHASHTABLE ((uint32_t)0x00000402) -#define ETH_UNICASTFRAMESFILTER_HASHTABLE ((uint32_t)0x00000002) -#define ETH_UNICASTFRAMESFILTER_PERFECT ((uint32_t)0x00000000) - -/** - * @} - */ - - -/** @defgroup ETH_Zero_Quanta_Pause - * @{ - */ -#define ETH_ZEROQUANTAPAUSE_ENABLE ((uint32_t)0x00000000) -#define ETH_ZEROQUANTAPAUSE_DISABLE ((uint32_t)0x00000080) -/** - * @} - */ - -/** @defgroup ETH_Pause_Low_Threshold - * @{ - */ -#define ETH_PAUSELOWTHRESHOLD_MINUS4 ((uint32_t)0x00000000) -#define ETH_PAUSELOWTHRESHOLD_MINUS28 ((uint32_t)0x00000010) -#define ETH_PAUSELOWTHRESHOLD_MINUS144 ((uint32_t)0x00000020) -#define ETH_PAUSELOWTHRESHOLD_MINUS256 ((uint32_t)0x00000030) - -/** - * @} - */ - -/** @defgroup ETH_RFD_Threshold - * @{ - */ -#define ETH_RFD_256BYTES ((uint32_t)0x00000000) -#define ETH_RFD_512BYTES ((uint32_t)0x00000010) -#define ETH_RFD_768BYTES ((uint32_t)0x00000020) -#define ETH_RFD_1024BYTES ((uint32_t)0x00000030) -#define ETH_RFD_1280BYTES ((uint32_t)0x00000040) -#define ETH_RFD_1536BYTES ((uint32_t)0x00000050) -#define ETH_RFD_1792BYTES ((uint32_t)0x00000060) - -/** - * @} - */ - -/** @defgroup ETH_RFA_Threshold - * @{ - */ -#define ETH_RFA_256BYTES ((uint32_t)0x00000000) -#define ETH_RFA_512BYTES ((uint32_t)0x00000001) -#define ETH_RFA_768BYTES ((uint32_t)0x00000002) -#define ETH_RFA_1024BYTES ((uint32_t)0x00000003) -#define ETH_RFA_1280BYTES ((uint32_t)0x00000004) -#define ETH_RFA_1536BYTES ((uint32_t)0x00000005) -#define ETH_RFA_1792BYTES ((uint32_t)0x00000006) - -/** - * @} - */ - -/** @defgroup ETH_Unicast_Pause_Frame_Detect - * @{ - */ -#define ETH_UNICASTPAUSEFRAMEDETECT_ENABLE ((uint32_t)0x00000008) -#define ETH_UNICASTPAUSEFRAMEDETECT_DISABLE ((uint32_t)0x00000000) - -/** - * @} - */ - -/** @defgroup ETH_Receive_Flow_Control - * @{ - */ -#define ETH_RECEIVEFLOWCONTROL_ENABLE ((uint32_t)0x00000004) -#define ETH_RECEIVEFLOWCONTROL_DISABLE ((uint32_t)0x00000000) - -/** - * @} - */ - -/** @defgroup ETH_Transmit_Flow_Control - * @{ - */ -#define ETH_TRANSMITFLOWCONTROL_ENABLE ((uint32_t)0x00000002) -#define ETH_TRANSMITFLOWCONTROL_DISABLE ((uint32_t)0x00000000) - -/** - * @} - */ - -/** @defgroup ETH_VLAN_Tag_Comparison - * @{ - */ -#define ETH_VLANTAGCOMPARISON_12BIT ((uint32_t)0x00010000) -#define ETH_VLANTAGCOMPARISON_16BIT ((uint32_t)0x00000000) - -/** - * @} - */ - -/** @defgroup ETH_MAC_Flags - * @{ - */ -#define ETH_MAC_FLAG_TST ((uint32_t)0x00000200) /*!< Time stamp trigger flag (on MAC) */ -#define ETH_MAC_FLAG_MSCT ((uint32_t)0x00000040) /*!< MSC transmit flag */ -#define ETH_MAC_FLAG_MSCR ((uint32_t)0x00000020) /*!< MSC receive flag */ -#define ETH_MAC_FLAG_MSC ((uint32_t)0x00000010) -#define ETH_MAC_FLAG_WUM ((uint32_t)0x00000008) -/** - * @} - */ - -/** @defgroup ETH_MAC_Interrupts - * @{ - */ -#define ETH_MAC_INT_TST ((uint32_t)0x00000200) /*!< Time stamp trigger interrupt (on MAC) */ -#define ETH_MAC_INT_MSCT ((uint32_t)0x00000040) /*!< MSC transmit interrupt */ -#define ETH_MAC_INT_MSCR ((uint32_t)0x00000020) /*!< MSC receive interrupt */ -#define ETH_MAC_INT_MSC ((uint32_t)0x00000010) -#define ETH_MAC_INT_WUM ((uint32_t)0x00000008) -/** - * @} - */ - -/** @defgroup ETH_MAC_addresses - * @{ - */ -#define ETH_MAC_ADDRESS0 ((uint32_t)0x00000000) -#define ETH_MAC_ADDRESS1 ((uint32_t)0x00000008) -#define ETH_MAC_ADDRESS2 ((uint32_t)0x00000010) -#define ETH_MAC_ADDRESS3 ((uint32_t)0x00000018) -/** - * @} - */ - -/** @defgroup ETH_MAC_addresses_filter_SA_DA_filed_of_received_frames - * @{ - */ -#define ETH_MAC_ADDRESSFILTER_SA ((uint32_t)0x00000000) -#define ETH_MAC_ADDRESSFILTER_DA ((uint32_t)0x00000008) -/** - * @} - */ - -/** @defgroup ETH_MAC_addresses_filter_Mask_bytes - * @{ - */ -#define ETH_MAC_ADDRESSMASK_BYTE6 ((uint32_t)0x20000000) /*!< Mask MAC Address high reg bits [15:8] */ -#define ETH_MAC_ADDRESSMASK_BYTE5 ((uint32_t)0x10000000) /*!< Mask MAC Address high reg bits [7:0] */ -#define ETH_MAC_ADDRESSMASK_BYTE4 ((uint32_t)0x08000000) /*!< Mask MAC Address low reg bits [31:24] */ -#define ETH_MAC_ADDRESSMASK_BYTE3 ((uint32_t)0x04000000) /*!< Mask MAC Address low reg bits [23:16] */ -#define ETH_MAC_ADDRESSMASK_BYTE2 ((uint32_t)0x02000000) /*!< Mask MAC Address low reg bits [15:8] */ -#define ETH_MAC_ADDRESSMASK_BYTE1 ((uint32_t)0x01000000) /*!< Mask MAC Address low reg bits [7:0] */ - -/** - * @} - */ - - -/** @defgroup ETH_DMA_Tx_descriptor_segment - * @{ - */ -#define ETH_DMATXDESC_LASTSEGMENT ((uint32_t)0x40000000) -#define ETH_DMATXDESC_FIRSTSEGMENT ((uint32_t)0x20000000) - -/** - * @} - */ - -/** @defgroup ETH_DMA_Tx_descriptor_Checksum_Insertion_Control - * @{ - */ -#define ETH_DMATXDESC_CHECKSUMDISABLE ((uint32_t)0x00000000) -#define ETH_DMATXDESC_CHECKSUMIPV4HEADER ((uint32_t)0x00400000) -#define ETH_DMATXDESC_CHECKSUMTCPUDPICMPSEGMENT ((uint32_t)0x00800000) -#define ETH_DMATXDESC_CHECKSUMTCPUDPICMPFULL ((uint32_t)0x00C00000) - - -/** - * @} - */ - -/** @defgroup ETH_DMA_Rx_descriptor_buffers_ - * @{ - */ -#define ETH_DMARXDESC_BUFFER1 ((uint32_t)0x00000000) -#define ETH_DMARXDESC_BUFFER2 ((uint32_t)0x00000001) - -/** - * @} - */ - -/** @defgroup ETH_Drop_TCP_IP_Checksum_Error_Frame - * @{ - */ -#define ETH_DROPTCPIPCHECKSUMERRORFRAME_ENABLE ((uint32_t)0x00000000) -#define ETH_DROPTCPIPCHECKSUMERRORFRAME_DISABLE ((uint32_t)0x04000000) -/** - * @} - */ - -/** @defgroup ETH_Receive_Store_Forward - * @{ - */ -#define ETH_RECEIVESTOREFORWARD_ENABLE ((uint32_t)0x02000000) -#define ETH_RECEIVESTOREFORWARD_DISABLE ((uint32_t)0x00000000) -/** - * @} - */ - -/** @defgroup ETH_Flush_Received_Frame - * @{ - */ -#define ETH_FLUSHRECEIVEDFRAME_ENABLE ((uint32_t)0x00000000) -#define ETH_FLUSHRECEIVEDFRAME_DISABLE ((uint32_t)0x01000000) -/** - * @} - */ - -/** @defgroup ETH_Transmit_Store_Forward - * @{ - */ -#define ETH_TRANSMITSTOREFORWARD_ENABLE ((uint32_t)0x00200000) -#define ETH_TRANSMITSTOREFORWARD_DISABLE ((uint32_t)0x00000000) -/** - * @} - */ - -/** @defgroup ETH_Transmit_Threshold_Control - * @{ - */ -#define ETH_TRANSMITTHRESHOLDCONTROL_64BYTES ((uint32_t)0x00000000) -#define ETH_TRANSMITTHRESHOLDCONTROL_128BYTES ((uint32_t)0x00004000) -#define ETH_TRANSMITTHRESHOLDCONTROL_192BYTES ((uint32_t)0x00008000) -#define ETH_TRANSMITTHRESHOLDCONTROL_256BYTES ((uint32_t)0x0000C000) -#define ETH_TRANSMITTHRESHOLDCONTROL_40BYTES ((uint32_t)0x00010000) -#define ETH_TRANSMITTHRESHOLDCONTROL_32BYTES ((uint32_t)0x00014000) -#define ETH_TRANSMITTHRESHOLDCONTROL_24BYTES ((uint32_t)0x00018000) -#define ETH_TRANSMITTHRESHOLDCONTROL_16BYTES ((uint32_t)0x0001C000) -/** - * @} - */ - -/** @defgroup ETH_Forward_Error_Frames - * @{ - */ -#define ETH_FORWARDERRORFRAMES_ENABLE ((uint32_t)0x00000080) -#define ETH_FORWARDERRORFRAMES_DISABLE ((uint32_t)0x00000000) -/** - * @} - */ - -/** @defgroup ETH_Forward_Undersized_Good_Frames - * @{ - */ -#define ETH_FORWARDUNDERSIZEDGOODFRAMES_ENABLE ((uint32_t)0x00000040) -#define ETH_FORWARDUNDERSIZEDGOODFRAMES_DISABLE ((uint32_t)0x00000000) - -/** - * @} - */ - -/** @defgroup ETH_Receive_Threshold_Control - * @{ - */ -#define ETH_RECEIVETHRESHOLDCONTROL_64BYTES ((uint32_t)0x00000000) -#define ETH_RECEIVETHRESHOLDCONTROL_32BYTES ((uint32_t)0x00000008) -#define ETH_RECEIVETHRESHOLDCONTROL_96BYTES ((uint32_t)0x00000010) -#define ETH_RECEIVETHRESHOLDCONTROL_128BYTES ((uint32_t)0x00000018) -/** - * @} - */ - -/** @defgroup ETH_Second_Frame_Operate - * @{ - */ -#define ETH_SECONDFRAMEOPERATE_ENABLE ((uint32_t)0x00000004) -#define ETH_SECONDFRAMEOPERATE_DISABLE ((uint32_t)0x00000000) - -/** - * @} - */ - -/** @defgroup ETH_Address_Aligned - * @{ - */ -#define ETH_ADDRESSALIGNED_ENABLE ((uint32_t)0x02000000) -#define ETH_ADDRESSALIGNED_DISABLE ((uint32_t)0x00000000) - -/** - * @} - */ - -/** @defgroup ETH_Fixed_Burst - * @{ - */ -#define ETH_FIXEDBURST_ENABLE ((uint32_t)0x00010000) -#define ETH_FIXEDBURST_DISABLE ((uint32_t)0x00000000) - -/** - * @} - */ - -/** @defgroup ETH_Rx_DMA_Burst_Length - * @{ - */ -#define ETH_RXDMABURSTLENGTH_1BEAT ((uint32_t)0x00020000) -#define ETH_RXDMABURSTLENGTH_2BEAT ((uint32_t)0x00040000) -#define ETH_RXDMABURSTLENGTH_4BEAT ((uint32_t)0x00080000) -#define ETH_RXDMABURSTLENGTH_8BEAT ((uint32_t)0x00100000) -#define ETH_RXDMABURSTLENGTH_16BEAT ((uint32_t)0x00200000) -#define ETH_RXDMABURSTLENGTH_32BEAT ((uint32_t)0x00400000) -#define ETH_RXDMABURSTLENGTH_4XPBL_4BEAT ((uint32_t)0x01020000) -#define ETH_RXDMABURSTLENGTH_4XPBL_8BEAT ((uint32_t)0x01040000) -#define ETH_RXDMABURSTLENGTH_4XPBL_16BEAT ((uint32_t)0x01080000) -#define ETH_RXDMABURSTLENGTH_4XPBL_32BEAT ((uint32_t)0x01100000) -#define ETH_RXDMABURSTLENGTH_4XPBL_64BEAT ((uint32_t)0x01200000) -#define ETH_RXDMABURSTLENGTH_4XPBL_128BEAT ((uint32_t)0x01400000) -/** - * @} - */ - -/** @defgroup ETH_Tx_DMA_Burst_Length - * @{ - */ -#define ETH_TXDMABURSTLENGTH_1BEAT ((uint32_t)0x00000100) -#define ETH_TXDMABURSTLENGTH_2BEAT ((uint32_t)0x00000200) -#define ETH_TXDMABURSTLENGTH_4BEAT ((uint32_t)0x00000400) -#define ETH_TXDMABURSTLENGTH_8BEAT ((uint32_t)0x00000800) -#define ETH_TXDMABURSTLENGTH_16BEAT ((uint32_t)0x00001000) -#define ETH_TXDMABURSTLENGTH_32BEAT ((uint32_t)0x00002000) -#define ETH_TXDMABURSTLENGTH_4XPBL_4BEAT ((uint32_t)0x01000100) -#define ETH_TXDMABURSTLENGTH_4XPBL_8BEAT ((uint32_t)0x01000200) -#define ETH_TXDMABURSTLENGTH_4XPBL_16BEAT ((uint32_t)0x01000400) -#define ETH_TXDMABURSTLENGTH_4XPBL_32BEAT ((uint32_t)0x01000800) -#define ETH_TXDMABURSTLENGTH_4XPBL_64BEAT ((uint32_t)0x01001000) -#define ETH_TXDMABURSTLENGTH_4XPBL_128BEAT ((uint32_t)0x01002000) - -/** - * @} - */ - -/** @defgroup ETH_DMA_Arbitration - * @{ - */ -#define ETH_DMAARBITRATION_ROUNDROBIN_RXTX_1_1 ((uint32_t)0x00000000) -#define ETH_DMAARBITRATION_ROUNDROBIN_RXTX_2_1 ((uint32_t)0x00004000) -#define ETH_DMAARBITRATION_ROUNDROBIN_RXTX_3_1 ((uint32_t)0x00008000) -#define ETH_DMAARBITRATION_ROUNDROBIN_RXTX_4_1 ((uint32_t)0x0000C000) -#define ETH_DMAARBITRATION_RXPRIORTX ((uint32_t)0x00000002) - -/** - * @} - */ - -/** @defgroup ETH_DMA_Flags - * @{ - */ -#define ETH_DMA_FLAG_TST ((uint32_t)0x20000000) /*!< Time-stamp trigger interrupt (on DMA) */ -#define ETH_DMA_FLAG_WUM ((uint32_t)0x10000000) /*!< WUM interrupt (on DMA) */ -#define ETH_DMA_FLAG_MSC ((uint32_t)0x08000000) /*!< MSC interrupt (on DMA) */ -#define ETH_DMA_FLAG_DATATRANSFERERROR ((uint32_t)0x00800000) /*!< Error bits 0-Rx DMA, 1-Tx DMA */ -#define ETH_DMA_FLAG_READWRITEERROR ((uint32_t)0x01000000) /*!< Error bits 0-write trnsf, 1-read transfr */ -#define ETH_DMA_FLAG_ACCESSERROR ((uint32_t)0x02000000) /*!< Error bits 0-data buffer, 1-desc. access */ -#define ETH_DMA_FLAG_NIS ((uint32_t)0x00010000) /*!< Normal interrupt summary flag */ -#define ETH_DMA_FLAG_AIS ((uint32_t)0x00008000) /*!< Abnormal interrupt summary flag */ -#define ETH_DMA_FLAG_ER ((uint32_t)0x00004000) /*!< Early receive flag */ -#define ETH_DMA_FLAG_FBE ((uint32_t)0x00002000) /*!< Fatal bus error flag */ -#define ETH_DMA_FLAG_ET ((uint32_t)0x00000400) /*!< Early transmit flag */ -#define ETH_DMA_FLAG_RWT ((uint32_t)0x00000200) /*!< Receive watchdog timeout flag */ -#define ETH_DMA_FLAG_RPS ((uint32_t)0x00000100) /*!< Receive process stopped flag */ -#define ETH_DMA_FLAG_RBU ((uint32_t)0x00000080) /*!< Receive buffer unavailable flag */ -#define ETH_DMA_FLAG_R ((uint32_t)0x00000040) /*!< Receive flag */ -#define ETH_DMA_FLAG_TU ((uint32_t)0x00000020) /*!< Transmit Underflow flag */ -#define ETH_DMA_FLAG_RO ((uint32_t)0x00000010) /*!< Receive Overflow flag */ -#define ETH_DMA_FLAG_TJT ((uint32_t)0x00000008) /*!< Transmit jabber timeout flag */ -#define ETH_DMA_FLAG_TBU ((uint32_t)0x00000004) /*!< Transmit buffer unavailable flag */ -#define ETH_DMA_FLAG_TPS ((uint32_t)0x00000002) /*!< Transmit process stopped flag */ -#define ETH_DMA_FLAG_T ((uint32_t)0x00000001) /*!< Transmit flag */ - -/** - * @} - */ - -/** @defgroup ETH_DMA_Interrupts - * @{ - */ -#define ETH_DMA_INT_TST ((uint32_t)0x20000000) /*!< Time-stamp trigger interrupt (on DMA) */ -#define ETH_DMA_INT_WUM ((uint32_t)0x10000000) /*!< WUM interrupt (on DMA) */ -#define ETH_DMA_INT_MSC ((uint32_t)0x08000000) /*!< MSC interrupt (on DMA) */ -#define ETH_DMA_INT_NIS ((uint32_t)0x00010000) /*!< Normal interrupt summary */ -#define ETH_DMA_INT_AIS ((uint32_t)0x00008000) /*!< Abnormal interrupt summary */ -#define ETH_DMA_INT_ER ((uint32_t)0x00004000) /*!< Early receive interrupt */ -#define ETH_DMA_INT_FBE ((uint32_t)0x00002000) /*!< Fatal bus error interrupt */ -#define ETH_DMA_INT_ET ((uint32_t)0x00000400) /*!< Early transmit interrupt */ -#define ETH_DMA_INT_RWT ((uint32_t)0x00000200) /*!< Receive watchdog timeout interrupt */ -#define ETH_DMA_INT_RPS ((uint32_t)0x00000100) /*!< Receive process stopped interrupt */ -#define ETH_DMA_INT_RBU ((uint32_t)0x00000080) /*!< Receive buffer unavailable interrupt */ -#define ETH_DMA_INT_R ((uint32_t)0x00000040) /*!< Receive interrupt */ -#define ETH_DMA_INT_TU ((uint32_t)0x00000020) /*!< Transmit Underflow interrupt */ -#define ETH_DMA_INT_RO ((uint32_t)0x00000010) /*!< Receive Overflow interrupt */ -#define ETH_DMA_INT_TJT ((uint32_t)0x00000008) /*!< Transmit jabber timeout interrupt */ -#define ETH_DMA_INT_TBU ((uint32_t)0x00000004) /*!< Transmit buffer unavailable interrupt */ -#define ETH_DMA_INT_TPS ((uint32_t)0x00000002) /*!< Transmit process stopped interrupt */ -#define ETH_DMA_INT_T ((uint32_t)0x00000001) /*!< Transmit interrupt */ - - -/** - * @} - */ - -/** @defgroup ETH_DMA_transmit_process_state_ - * @{ - */ -#define ETH_DMA_TRANSMITPROCESS_STOPPED ((uint32_t)0x00000000) -#define ETH_DMA_TRANSMITPROCESS_FETCHING ((uint32_t)0x00100000) -#define ETH_DMA_TRANSMITPROCESS_WAITING ((uint32_t)0x00200000) -#define ETH_DMA_TRANSMITPROCESS_READING ((uint32_t)0x00300000) -#define ETH_DMA_TRANSMITPROCESS_SUSPENDED ((uint32_t)0x00600000) -#define ETH_DMA_TRANSMITPROCESS_CLOSING ((uint32_t)0x00700000) - -/** - * @} - */ - - -/** @defgroup ETH_DMA_receive_process_state_ - * @{ - */ -#define ETH_DMA_RECEIVEPROCESS_STOPPED ((uint32_t)0x00000000) -#define ETH_DMA_RECEIVEPROCESS_FETCHING ((uint32_t)0x00020000) -#define ETH_DMA_RECEIVEPROCESS_WAITING ((uint32_t)0x00060000) -#define ETH_DMA_RECEIVEPROCESS_SUSPENDED ((uint32_t)0x00080000) -#define ETH_DMA_RECEIVEPROCESS_CLOSING ((uint32_t)0x000A0000) -#define ETH_DMA_RECEIVEPROCESS_QUEUING ((uint32_t)0x000E0000) - -/** - * @} - */ - -/** @defgroup ETH_DMA_overflow_ - * @{ - */ -#define ETH_DMA_OVERFLOW_RXFIFOCOUNTER ((uint32_t)0x10000000) -#define ETH_DMA_OVERFLOW_MISSEDFRAMECOUNTER ((uint32_t)0x00010000) - -/** - * @} - */ - -/** @defgroup ETH_WUM_Flags - * @{ - */ -#define ETH_WUM_FLAG_WUFFRPR ((uint32_t)0x80000000) /*!< Wake-Up Frame Filter Register Poniter Reset */ -#define ETH_WUM_FLAG_WUFR ((uint32_t)0x00000040) /*!< Wake-Up Frame Received */ -#define ETH_WUM_FLAG_MPKR ((uint32_t)0x00000020) /*!< Magic Packet Received */ - -/** - * @} - */ - -/** @defgroup ETH_MSC_Tx_Interrupts - * @{ - */ -#define ETH_MSC_INT_TGF ((uint32_t)0x00200000) /*!< When Tx good frame counter reaches half the maximum value */ -#define ETH_MSC_INT_TGFMSC ((uint32_t)0x00008000) /*!< When Tx good multi col counter reaches half the maximum value */ -#define ETH_MSC_INT_TGFSC ((uint32_t)0x00004000) /*!< When Tx good single col counter reaches half the maximum value */ - -/** - * @} - */ - -/** @defgroup ETH_MSC_Rx_Interrupts - * @{ - */ -#define ETH_MSC_INT_RGUF ((uint32_t)0x10020000) /*!< When Rx good unicast frames counter reaches half the maximum value */ -#define ETH_MSC_INT_RFAE ((uint32_t)0x10000040) /*!< When Rx alignment error counter reaches half the maximum value */ -#define ETH_MSC_INT_RFCE ((uint32_t)0x10000020) /*!< When Rx crc error counter reaches half the maximum value */ -/** - * @} - */ - -/** @defgroup ETH_MSC_Registers - * @{ - */ -#define ETH_MSC_CTLR ((uint32_t)0x00000100) -#define ETH_MSC_RISR ((uint32_t)0x00000104) -#define ETH_MSC_TISR ((uint32_t)0x00000108) -#define ETH_MSC_RIMR ((uint32_t)0x0000010C) -#define ETH_MSC_TIMR ((uint32_t)0x00000110) -#define ETH_MSC_SCCNT ((uint32_t)0x0000014C) -#define ETH_MSC_MSCCNT ((uint32_t)0x00000150) -#define ETH_MSC_TGFCNT ((uint32_t)0x00000168) -#define ETH_MSC_RFCECNT ((uint32_t)0x00000194) -#define ETH_MSC_RFAECNT ((uint32_t)0x00000198) -#define ETH_MSC_RGUFCNT ((uint32_t)0x000001C4) - - -/** - * @} - */ - -/** @defgroup ETH_PTP_time_update_mode - * @{ - */ -#define ETH_PTP_FINEMODE ((uint32_t)0x00000001) -#define ETH_PTP_COARSEMODE ((uint32_t)0x00000000) - -/** - * @} - */ - - -/** @defgroup ETH_PTP_Flags - * @{ - */ -#define ETH_PTP_FLAG_TMSARU ((uint32_t)0x00000020) /*!< Addend Register Update */ -#define ETH_PTP_FLAG_TMSITEN ((uint32_t)0x00000010) /*!< Time Stamp Interrupt Trigger Enable */ -#define ETH_PTP_FLAG_TMSSTU ((uint32_t)0x00000008) /*!< Time Stamp Update */ -#define ETH_PTP_FLAG_TMSSTI ((uint32_t)0x00000004) /*!< Time Stamp Initialize */ - -/** - * @} - */ - -/** @defgroup ETH_PTP_time_sign - * @{ - */ -#define ETH_PTP_POSITIVETIME ((uint32_t)0x00000000) -#define ETH_PTP_NEGATIVETIME ((uint32_t)0x80000000) - -/** - * @brief ETH PTP registers - */ -#define ETH_PTP_TSCTLR ((uint32_t)0x00000700) -#define ETH_PTP_SSINCR ((uint32_t)0x00000704) -#define ETH_PTP_TMSHR ((uint32_t)0x00000708) -#define ETH_PTP_TMSLR ((uint32_t)0x0000070C) -#define ETH_PTP_TMSHUR ((uint32_t)0x00000710) -#define ETH_PTP_TMSLUR ((uint32_t)0x00000714) -#define ETH_PTP_TSACNT ((uint32_t)0x00000718) -#define ETH_PTP_ETHR ((uint32_t)0x0000071C) -#define ETH_PTP_ETLR ((uint32_t)0x00000720) - -/** - * @} - */ - - -/** - * @} - */ - - -/** @defgroup ETH_Exported_Functions - * @{ - */ -void ETH_DeInit(void); -void ETH_MDIOInit(void); -uint32_t ETH_Init(ETH_InitPara *ETH_InitParaStruct, u16 PHYAddress); -void ETH_ParaInit(ETH_InitPara *ETH_InitParaStruct); -void ETH_SoftReset(void); -TypeState ETH_GetSoftResetStatus(void); -void ETH_Enable(TypeState NewValue); -uint32_t ETH_HandleTxPkt(uint8_t *pbuf, uint16_t size); -uint32_t ETH_HandleRxPkt(uint8_t *pbuf); -uint32_t ETH_GetRxPktSize(void); -void ETH_DropRxPkt(void); -/** - * @brief PHY - */ -uint16_t ETH_GetPHYRegisterValue(uint16_t PHYAddr, uint16_t PHYReg); -uint32_t ETH_SetPHYRegisterValue(uint16_t PHYAddr, uint16_t PHYReg, uint16_t PHYValue); -uint32_t ETH_PHYLoopBack_Enable(uint16_t PHYAddr, TypeState NewValue); - -/** - * @brief MAC - */ -void ETH_MACTransmission_Enable(TypeState NewValue); -void ETH_MACReception_Enable(TypeState NewValue); -TypeState ETH_GetFlowControlBusyBitState(void); -void ETH_PauseFrameInit(void) ; -void ETH_BackPressureActivation_Enable(TypeState NewValue); -TypeState ETH_GetMACBitState(uint32_t ETH_MAC_FLAG); -TypeState ETH_GetMACIntBitState(uint32_t ETH_MAC_IT); -void ETH_MACINTConfig(uint32_t ETH_MAC_IT, TypeState NewValue); -void ETH_SetMACAddress(uint32_t addr, uint8_t *buf); -void ETH_GetMACAddress(uint32_t addr, uint8_t *buf); -void ETH_MACAddressPerfectFilter_Enable(uint32_t addr, TypeState NewValue); -void ETH_MACAddressFilterConfig(uint32_t addr, uint32_t Filterfield); -void ETH_MACAddressFilterMaskBytesConfig(uint32_t addr, uint32_t addrmask); - -/** - * @brief DMA Tx/Rx descriptors - */ -void ETH_DMATxDescChainModeInit(ETH_DMADESCTypeDef *DMATxDescTab, uint8_t *pTxBuff, uint32_t TxBuffCnt); -void ETH_DMATxDescRingModeInit(ETH_DMADESCTypeDef *DMATxDescTab, uint8_t *pTxBuff1, uint8_t *pTxBuff2, uint32_t TxBuffCnt); -TypeState ETH_GetDMATxDescBitState(ETH_DMADESCTypeDef *DMATxDesc, uint32_t ETH_DMATxDescFlag); -uint32_t ETH_GetDMATxDescCollisionCount(ETH_DMADESCTypeDef *DMATxDesc); -void ETH_SetDMATxDescBusyBit(ETH_DMADESCTypeDef *DMATxDesc); -void ETH_DMATxDescTransmitINTConfig(ETH_DMADESCTypeDef *DMATxDesc, TypeState NewValue); -void ETH_SetDMATxDescFrameSegment(ETH_DMADESCTypeDef *DMATxDesc, uint32_t DMATxDesc_Segment); -void ETH_SetDMATxDescChecksumInsertion(ETH_DMADESCTypeDef *DMATxDesc, uint32_t DMATxDesc_Checksum); -void ETH_DMATxDescCRC_Enable(ETH_DMADESCTypeDef *DMATxDesc, TypeState NewValue); -void ETH_DMATxDescEndOfRing_Enable(ETH_DMADESCTypeDef *DMATxDesc, TypeState NewValue); -void ETH_DMATxDescSecondAddressChained_Enable(ETH_DMADESCTypeDef *DMATxDesc, TypeState NewValue); -void ETH_DMATxDescShortFramePadding_Enable(ETH_DMADESCTypeDef *DMATxDesc, TypeState NewValue); -void ETH_DMATxDescTimeStamp_Enable(ETH_DMADESCTypeDef *DMATxDesc, TypeState NewValue); -void ETH_SetDMATxDescBufferSize(ETH_DMADESCTypeDef *DMATxDesc, uint32_t Buffer1Size, uint32_t Buffer2Size); -void ETH_DMARxDescChainModeInit(ETH_DMADESCTypeDef *DMARxDescTab, uint8_t *pRxBuff, uint32_t RxBuffCnt); -void ETH_DMARxDescRingModeInit(ETH_DMADESCTypeDef *DMARxDescTab, uint8_t *pRxBuff1, uint8_t *pRxBuff2, uint32_t RxBuffCnt); -TypeState ETH_GetDMARxDescBitState(ETH_DMADESCTypeDef *DMARxDesc, uint32_t ETH_DMARxDescFlag); -void ETH_SetDMARxDescBusyBit(ETH_DMADESCTypeDef *DMARxDesc); -uint32_t ETH_GetDMARxDescFrameLength(ETH_DMADESCTypeDef *DMARxDesc); -void ETH_DMARxDescReceiveINTConfig(ETH_DMADESCTypeDef *DMARxDesc, TypeState NewValue); -void ETH_DMARxDescEndOfRing_Enable(ETH_DMADESCTypeDef *DMARxDesc, TypeState NewValue); -void ETH_DMARxDescSecondAddressChained_Enable(ETH_DMADESCTypeDef *DMARxDesc, TypeState NewValue); -uint32_t ETH_GetDMARxDescBufferSize(ETH_DMADESCTypeDef *DMARxDesc, uint32_t DMARxDesc_Buffer); - -/** - * @brief DMA - */ -TypeState ETH_GetDMABitState(uint32_t ETH_DMA_FLAG); -void ETH_DMAClearBitState(uint32_t ETH_DMA_FLAG); -TypeState ETH_GetDMAIntBitState(uint32_t ETH_DMA_IT); -void ETH_DMAClearIntBitState(uint32_t ETH_DMA_IT); -uint32_t ETH_GetTransmitProcessState(void); -uint32_t ETH_GetReceiveProcessState(void); -void ETH_CleanTransmitFIFO(void); -TypeState ETH_GetFlushTransmitFIFOStatus(void); -void ETH_DMATransmission_Enable(TypeState NewValue); -void ETH_DMAReception_Enable(TypeState NewValue); -void ETH_DMAINTConfig(uint32_t ETH_DMA_IT, TypeState NewValue); -TypeState ETH_GetDMAOverflowStatus(uint32_t ETH_DMA_Overflow); -uint32_t ETH_GetRxOverflowMissedFrameCounter(void); -uint32_t ETH_GetBufferUnavailableMissedFrameCounter(void); -uint32_t ETH_GetCurrentTxDescStartAddress(void); -uint32_t ETH_GetCurrentRxDescStartAddress(void); -uint32_t ETH_GetCurrentTxBufferAddress(void); -uint32_t ETH_GetCurrentRxBufferAddress(void); -void ETH_ResumeDMATransmission(void); -void ETH_ResumeDMAReception(void); - -/** - * @brief WUM - */ -void ETH_ResetWakeUpFrameFilterRegister(void); -void ETH_SetWakeUpFrameFilterRegister(uint32_t *pBuffer); -void ETH_GlobalUnicastWakeUp_Enable(TypeState NewValue); -TypeState ETH_GetWUMBitState(uint32_t ETH_WUM_FLAG); -void ETH_WakeUpFrameDetection_Enable(TypeState NewValue); -void ETH_MagicPacketDetection_Enable(TypeState NewValue); -void ETH_PowerDown_Enable(TypeState NewValue); - -/** - * @brief MSC - */ -void ETH_MSCCounterFreeze_Enable(TypeState NewValue); -void ETH_MSCResetOnRead_Enable(TypeState NewValue); -void ETH_MSCCounterRollover_Enable(TypeState NewValue); -void ETH_ResetMSCCounters(void); -void ETH_MSCINTConfig(uint32_t ETH_MSC_IT, TypeState NewValue); -TypeState ETH_GetMSCINTStatus(uint32_t ETH_MSC_IT); -uint32_t ETH_GetMSCRegister(uint32_t ETH_MSC_Register); - -/** - * @brief PTP - */ -void ETH_PTPTimeStampAddendUpdate(void); -void ETH_PTPTimeStampIntTrigger_Enable(TypeState NewValue); -void ETH_PTPTimeStampUpdate_Enable(TypeState NewValue); -void ETH_PTPTimeStampInit(void); -void ETH_PTPUpdateModeConfig(uint32_t UpdateMode); -void ETH_PTPTimeStamp_Enable(TypeState NewValue); -TypeState ETH_GetPTPBitState(uint32_t ETH_PTP_FLAG); -void ETH_SetPTPSubSecondIncrement(uint32_t SubSecond); -void ETH_SetPTPUpdateTimeValue(uint32_t Sign, uint32_t SecondValue, uint32_t SubSecondValue); -void ETH_SetPTPTimeStampAddend(uint32_t add); -void ETH_SetPTPTargetTime(uint32_t HighReg_Value, uint32_t LowReg_Value); -uint32_t ETH_GetPTPRegister(uint32_t ETH_PTPRegister); -void ETH_DMAPTPTxDescChainModeInit(ETH_DMADESCTypeDef *DMATxDescTab, ETH_DMADESCTypeDef *DMAPTPTxDescTab, - uint8_t *pTxBuff, uint32_t TxBuffCnt); -void ETH_DMAPTPRxDescChainModeInit(ETH_DMADESCTypeDef *DMARxDescTab, ETH_DMADESCTypeDef *DMAPTPRxDescTab, - uint8_t *pRxBuff, uint32_t RxBuffCnt); -uint32_t ETH_HandlePTPTxPkt(uint8_t *pbuf, uint16_t size, uint32_t *PTPTxTab); -uint32_t ETH_HandlePTPRxPkt(uint8_t *pbuf, uint32_t *PTPRxTab); - - -#ifdef __cplusplus -} -#endif - -#endif /* __GD32F10X_ETH_H */ - -/** - * @} - */ - -/** - * @} - */ - -/** - * @} - */ diff --git a/bsp/gd32103c-eval/Libraries/GD32F1xx_standard_peripheral/Include/gd32f10x_exmc.h b/bsp/gd32103c-eval/Libraries/GD32F1xx_standard_peripheral/Include/gd32f10x_exmc.h deleted file mode 100644 index 864efe9371..0000000000 --- a/bsp/gd32103c-eval/Libraries/GD32F1xx_standard_peripheral/Include/gd32f10x_exmc.h +++ /dev/null @@ -1,454 +0,0 @@ -/** - ****************************************************************************** - * @brief EXMC header file of the firmware library. - ****************************************************************************** - */ - -/* Define to prevent recursive inclusion -------------------------------------*/ -#ifndef __GD32F10X_EXMC_H -#define __GD32F10X_EXMC_H - -#ifdef __cplusplus -extern "C" { -#endif - -/* Includes ------------------------------------------------------------------*/ -#include "gd32f10x.h" - -/** @addtogroup GD32F10x_Firmware - * @{ - */ - -/** @addtogroup EXMC - * @{ - */ - -/** @defgroup EXMC_Exported_Types - * @{ - */ - -/** - * @brief Initial Timing Parameters For NOR/SRAM Banks - */ -typedef struct { - uint32_t EXMC_AsynAccessMode; /*!< The asynchronous access mode, detailed in @ref EXMC_AsynAccess_Mode*/ - uint32_t EXMC_SynDataLatency; /*!< The number of CLK cycles to configure the data latency, - which may assume a value between 0x0 and 0xF. */ - uint32_t EXMC_SynCLKDivision; /*!< The number of HCLK cycles to configure the clock divide ratio, - which can be a value between 0x0 and 0xF. */ - uint32_t EXMC_BusLatency; /*!< The number of HCLK cycles to configure the bus latency, - which can be a value between 0x0 and 0xF. */ - uint32_t EXMC_AsynDataSetupTime; /*!< The number of HCLK cycles to configure the data setup time - while in the asynchronous access mode, which can be a value - between 0x00 and 0xFF. */ - uint32_t EXMC_AsynAddressHoldTime; /*!< The number of HCLK cycles to configure the address hold time - while in the asynchronous access mode, which can be a value - between 0x0 and 0xF. */ - uint32_t EXMC_AsynAddressSetupTime; /*!< The number of HCLK cycles to configure the data setup time - while in the asynchronous access mode, which can be a value - between 0x0 and 0xF. */ -} EXMC_NORSRAMTimingInitPara; - -/** - * @brief EXMC NOR/SRAM Init structure definition - */ -typedef struct { - uint32_t EXMC_NORSRAMBank; /*!< The specified region of NORSRAM Bank1, - choose one from @ref EXMC_NORSRAMBank. */ - uint32_t EXMC_WriteMode; /*!< The write mode, details in @ref EXMC_WriteMode. */ - uint32_t EXMC_ExtendedMode; /*!< Enable or Disable the extended mode, details in - @ref EXMC_ExtendedMode. */ - uint32_t EXMC_AsynWait; /*!< Enable or disable the asynchronous wait feature,detial - in @ref EXMC_AsynWait. */ - uint32_t EXMC_NWAITSignal; /*!< Enable or Disable the NWAIT signal while in synchronous - bust mode, details in @ref EXMC_NWAITSignal. */ - uint32_t EXMC_MemoryWrite; /*!< Enable or Disable the write operation, details in - @ref EXMC_MemoryWrite. */ - uint32_t EXMC_NWAITConfig; /*!< NWAIT signal configuration, details in @ref EXMC_NWAITConfig */ - uint32_t EXMC_WrapBurstMode; /*!< Enable or Disable the wrap burst mode, details in - @ref EXMC_WrapBurstMode. */ - uint32_t EXMC_NWAITPolarity; /*!< Specifies the polarity of NWAIT signal from memory, - details in @ref EXMC_NWAITPolarity. */ - uint32_t EXMC_BurstMode; /*!< Enable or Disable the burst mode, details in - @ref EXMC_BurstMode. */ - uint32_t EXMC_DatabusWidth; /*!< Specifies the databus width of external memory, - details in @ref EXMC_DatabusWidth. */ - uint32_t EXMC_MemoryType; /*!< Specifies the type of external memory, details in - @ref EXMC_MemoryType. */ - uint32_t EXMC_AddressDataMux; /*!< Specifies whether the data bus and address bus are multiplexed - or not,details in @ref EXMC_AddressDataMux. */ - - EXMC_NORSRAMTimingInitPara *EXMC_ReadWriteTimingParaStruct; /*!< The struct EXMC_NORSRAMTimingInitPara pointer,which is - used to define the timing parameters for read and write - if the ExtendedMode is not used or define the timing - parameters for read if the ExtendedMode is used. */ - - EXMC_NORSRAMTimingInitPara *EXMC_WriteTimingParaStruct; /*!< The struct EXMC_NORSRAMTimingInitPara pointer,which is - only used to define the timing parameters for write when - the ExtendedMode is used. */ -} EXMC_NORSRAMInitPara; - -/** - * @brief Timing parameters For EXMC NAND and PCCARD Banks - */ - -typedef struct { - uint32_t EXMC_DatabusHiZTime; /*!< The number of HCLK cycles to configure the dadtabus HiZ time - for write operation, which can be a value between 0x00 and 0xFF. */ - uint32_t EXMC_HoldTime; /*!< The number of HCLK cycles to configure the address hold time - (or the data hold time for write operation),which can be a value - between 0x00 and 0xFF. */ - uint32_t EXMC_WaitTime; /*!< The number of HCLK cycles to configure the minimum wait time, - which can be a value between 0x00 and 0xFF. */ - uint32_t EXMC_SetupTime; /*!< The number of HCLK cycles to configure the address setup time , - which can be a value between 0x00 and 0xFF. */ -} EXMC_NAND_PCCARDTimingInitPara; - -/** - * @brief EXMC NAND Init structure definition - */ -typedef struct { - uint32_t EXMC_NANDBank; /*!< The specified Bank of NAND FLASH, choose one - from @ref EXMC_NANDBank. */ - uint32_t EXMC_ECCSize; /*!< The page size for the ECC calculation,details - in @ref EXMC_ECCSize. */ - uint32_t EXMC_ATRLatency; /*!< The number of HCLK cycles to configure the - latency of ALE low to RB low, which can be a - value between 0x0 and 0xF. */ - uint32_t EXMC_CTRLatency; /*!< The number of HCLK cycles to configure the - latency of CLE low to RB low, which can be a - value between 0x0 and 0xF. */ - uint32_t EXMC_ECCLogic; /*!< Enable or Disable the ECC calculation logic, - details in @ref EXMC_ECCLogic. */ - uint32_t EXMC_DatabusWidth; /*!< the NAND flash databus width, details in - @ref EXMC_DatabusWidth. */ - uint32_t EXMC_WaitFeature; /*!< Enables or Disables the Wait feature,details - in @ref EXMC_WaitFeature. */ - EXMC_NAND_PCCARDTimingInitPara *EXMC_CommonSpaceTimingParaStruct; /*!< The struct EXMC_NAND_PCCARDTimingInitPara - pointer, which is used to define the timing - parameters for NAND flash Common Space. */ - EXMC_NAND_PCCARDTimingInitPara *EXMC_AttributeSpaceTimingParaStruct; /*!< The struct EXMC_NAND_PCCARDTimingInitPara - pointer, which is used to define the timing - parameters for NAND flash Attribute Space. */ -} EXMC_NANDInitPara; - -/** - * @brief EXMC PCCARD Init structure definition - */ - -typedef struct { - uint32_t EXMC_ATRLatency; /*!< The number of HCLK cycles to configure - the latency of ALE low to RB low, which can - be a value between 0x0 and 0xF. */ - uint32_t EXMC_CTRLatency; /*!< The number of HCLK cycles to configure - the latency of CLE low to RB low, which can - be a value between 0x0 and 0xF. */ - uint32_t EXMC_WaitFeature; /*!< Enables or Disables the Wait feature,details - in @ref EXMC_WaitFeature. */ - EXMC_NAND_PCCARDTimingInitPara *EXMC_CommonSpaceTimingParaStruct; /*!< The struct EXMC_NAND_PCCARDTimingInitPara - pointer, which is used to define the timing - parameters for PC CARD Common Space. */ - EXMC_NAND_PCCARDTimingInitPara *EXMC_AttributeSpaceTimingParaStruct; /*!< The struct EXMC_NAND_PCCARDTimingInitPara - pointer, which is used to define the timing - parameters for PC CARD Attribute Space. */ - EXMC_NAND_PCCARDTimingInitPara *EXMC_IOSpaceTimingParaStruct; /*!< The struct EXMC_NAND_PCCARDTimingInitPara - pointer, which is used to define the timing - parameters for PC CARD I/O Space. */ -} EXMC_PCCARDInitPara; - -/** - * @} - */ - -/** @defgroup EXMC_Exported_Constants - * @{ - */ - -/** @defgroup EXMC_NORSRAMBank - * @{ - */ -#define EXMC_BANK1_NORSRAM1 ((uint32_t)0x00000001) -#define EXMC_BANK1_NORSRAM2 ((uint32_t)0x00000002) -#define EXMC_BANK1_NORSRAM3 ((uint32_t)0x00000003) -#define EXMC_BANK1_NORSRAM4 ((uint32_t)0x00000004) -/** - * @} - */ - -/** @defgroup EXMC_NANDBank - * @{ - */ -#define EXMC_BANK2_NAND ((uint32_t)0x00000010) -#define EXMC_BANK3_NAND ((uint32_t)0x00000100) -/** - * @} - */ - -/** @defgroup EXMC_PCCARD_Bank - * @{ - */ -#define EXMC_BANK4_PCCARD ((uint32_t)0x00001000) - -/** - * @} - */ - -/** @defgroup NORSRAM_Controller - * @{ - */ - -/** @defgroup EXMC_AddressDataMux - * @{ - */ -#define EXMC_ADDRESS_DATA_MUX_DISABLE ((uint32_t)0x00000000) -#define EXMC_ADDRESS_DATA_MUX_ENABLE ((uint32_t)0x00000002) - -/** - * @} - */ - -/** @defgroup EXMC_MemoryType - * @{ - */ -#define EXMC_MEMORY_TYPE_SRAM ((uint32_t)0x00000000) -#define EXMC_MEMORY_TYPE_PSRAM ((uint32_t)0x00000004) -#define EXMC_MEMORY_TYPE_NOR ((uint32_t)0x00000008) - -/** - * @} - */ - -/** @defgroup EXMC_DatabusWidth - * @{ - */ -#define EXMC_DATABUS_WIDTH_8B ((uint32_t)0x00000000) -#define EXMC_DATABUS_WIDTH_16B ((uint32_t)0x00000010) - -/** - * @} - */ - -/** @defgroup EXMC_NORFlash_Access - * @{ - */ -#define EXMC_NORFLASH_ACCESS_DISABLE ((uint32_t)0x00000000) -#define EXMC_NORFLASH_ACCESS_ENABLE ((uint32_t)0x00000040) - -/** - * @} - */ - -/** @defgroup EXMC_BurstMode - * @{ - */ -#define EXMC_BURST_MODE_DISABLE ((uint32_t)0x00000000) -#define EXMC_BURST_MODE_ENABLE ((uint32_t)0x00000100) - -/** - * @} - */ - -/** @defgroup EXMC_AsynWait - * @{ - */ -#define EXMC_ASYN_WAIT_DISABLE ((uint32_t)0x00000000) -#define EXMC_ASYN_WAIT_ENABLE ((uint32_t)0x00008000) - -/** - * @} - */ - -/** @defgroup EXMC_NWAITPolarity - * @{ - */ -#define EXMC_NWAIT_POLARITY_LOW ((uint32_t)0x00000000) -#define EXMC_NWAIT_POLARITY_HIGH ((uint32_t)0x00000200) - -/** - * @} - */ - -/** @defgroup EXMC_WrapBurstMode - * @{ - */ -#define EXMC_WRAP_BURST_MODE_DISABLE ((uint32_t)0x00000000) -#define EXMC_WRAP_BURST_MODE_ENABLE ((uint32_t)0x00000400) - -/** - * @} - */ - -/** @defgroup EXMC_NWAITConfig - * @{ - */ -#define EXMC_NWAIT_CONFIG_BEFORE ((uint32_t)0x00000000) -#define EXMC_NWAIT_CONFIG_DURING ((uint32_t)0x00000800) - -/** - * @} - */ - -/** @defgroup EXMC_MemoryWrite - * @{ - */ -#define EXMC_MEMORY_WRITE_DISABLE ((uint32_t)0x00000000) -#define EXMC_MEMORY_WRITE_ENABLE ((uint32_t)0x00001000) - -/** - * @} - */ - -/** @defgroup EXMC_NWAITSignal - * @{ - */ -#define EXMC_NWAIT_SIGNAL_DISABLE ((uint32_t)0x00000000) -#define EXMC_NWAIT_SIGNAL_ENABLE ((uint32_t)0x00002000) - -/** - * @} - */ - -/** @defgroup EXMC_ExtendedMode - * @{ - */ -#define EXMC_EXTENDED_MODE_DISABLE ((uint32_t)0x00000000) -#define EXMC_EXTENDED_MODE_ENABLE ((uint32_t)0x00004000) - -/** - * @} - */ - -/** @defgroup EXMC_WriteMode - * @{ - */ -#define EXMC_ASYN_WRITE ((uint32_t)0x00000000) -#define EXMC_SYN_WRITE ((uint32_t)0x00080000) - -/** - * @} - */ - -/** @defgroup EXMC_AsynAccess_Mode - * @{ - */ -#define EXMC_ACCESS_MODE_A ((uint32_t)0x00000000) -#define EXMC_ACCESS_MODE_B ((uint32_t)0x10000000) -#define EXMC_ACCESS_MODE_C ((uint32_t)0x20000000) -#define EXMC_ACCESS_MODE_D ((uint32_t)0x30000000) - -/** - * @} - */ - -/** - * @} - */ - -/** @defgroup NAND_PCCARD_Controller - * @{ - */ - -/** @defgroup EXMC_WaitFeature - * @{ - */ -#define EXMC_WAIT_FEATURE_DISABLE ((uint32_t)0x00000000) -#define EXMC_WAIT_FEATURE_ENABLE ((uint32_t)0x00000002) - -/** - * @} - */ - -/** @defgroup EXMC_ECCLogic - * @{ - */ -#define EXMC_ECC_LOGIC_DISABLE ((uint32_t)0x00000000) -#define EXMC_ECC_LOGIC_ENABLE ((uint32_t)0x00000040) - -/** - * @} - */ - -/** @defgroup EXMC_ECCSize - * @{ - */ -#define EXMC_ECC_SIZE_256BYTES ((uint32_t)0x00000000) -#define EXMC_ECC_SIZE_512BYTES ((uint32_t)0x00020000) -#define EXMC_ECC_SIZE_1024BYTES ((uint32_t)0x00040000) -#define EXMC_ECC_SIZE_2048BYTES ((uint32_t)0x00060000) -#define EXMC_ECC_SIZE_4096BYTES ((uint32_t)0x00080000) -#define EXMC_ECC_SIZE_8192BYTES ((uint32_t)0x000A0000) - -/** - * @} - */ - -/** @defgroup EXMC_Interrupt_Source - * @{ - */ -#define EXMC_INT_RISE ((uint32_t)0x00000008) -#define EXMC_INT_LEVEL ((uint32_t)0x00000010) -#define EXMC_INT_FALL ((uint32_t)0x00000020) - -/** - * @} - */ - -/** @defgroup EXMC_FLAG - * @{ - */ -#define EXMC_FLAG_RISE ((uint32_t)0x00000001) -#define EXMC_FLAG_LEVEL ((uint32_t)0x00000002) -#define EXMC_FLAG_FALL ((uint32_t)0x00000004) -#define EXMC_FLAG_FIFOE ((uint32_t)0x00000040) - -/** - * @} - */ - -/** - * @} - */ - -/** -* @} -*/ - -/** @defgroup EXMC_Exported_Functions - * @{ - */ -void EXMC_NORSRAM_DeInit(uint32_t EXMC_NORSRAMBank); -void EXMC_NAND_DeInit(uint32_t EXMC_NANDBank); -void EXMC_PCCARD_DeInit(void); -void EXMC_NORSRAM_Init(EXMC_NORSRAMInitPara *EXMC_NORSRAMInitParaStruct); -void EXMC_NAND_Init(EXMC_NANDInitPara *EXMC_NANDInitParaStruct); -void EXMC_PCCARD_Init(EXMC_PCCARDInitPara *EXMC_PCCARDInitParaStruct); -void EXMC_NORSRAMStruct_Init(EXMC_NORSRAMInitPara *EXMC_NORSRAMInitParaStruct); -void EXMC_NANDStruct_Init(EXMC_NANDInitPara *EXMC_NANDInitParaStruct); -void EXMC_PCCARDStruct_Init(EXMC_PCCARDInitPara *EXMC_PCCARDInitParaStruct); -void EXMC_NORSRAM_Enable(uint32_t EXMC_NORSRAMBank, TypeState NewValue); -void EXMC_NAND_Enable(uint32_t EXMC_NANDBank, TypeState NewValue); -void EXMC_PCCARD_Enable(TypeState NewValue); -void EXMC_NANDECC_Enable(uint32_t EXMC_NANDBank, TypeState NewValue); -uint32_t EXMC_GetECC(uint32_t EXMC_NANDBank); -void EXMC_INTConfig(uint32_t EXMC_PCNANDBank, uint32_t EXMC_INT, TypeState NewValue); -TypeState EXMC_GetBitState(uint32_t EXMC_PCNANDBank, uint32_t EXMC_FLAG); -void EXMC_ClearBitState(uint32_t EXMC_PCNANDBank, uint32_t EXMC_FLAG); -TypeState EXMC_GetIntBitState(uint32_t EXMC_PCNANDBank, uint32_t EXMC_INT); -void EXMC_ClearIntBitState(uint32_t EXMC_PCNANDBank, uint32_t EXMC_INT); - -#ifdef __cplusplus -} -#endif - -#endif /*__GD32F10x_EXMC_H */ -/** - * @} - */ - -/** - * @} - */ - -/** - * @} - */ diff --git a/bsp/gd32103c-eval/Libraries/GD32F1xx_standard_peripheral/Include/gd32f10x_exti.h b/bsp/gd32103c-eval/Libraries/GD32F1xx_standard_peripheral/Include/gd32f10x_exti.h deleted file mode 100644 index b36af10142..0000000000 --- a/bsp/gd32103c-eval/Libraries/GD32F1xx_standard_peripheral/Include/gd32f10x_exti.h +++ /dev/null @@ -1,130 +0,0 @@ -/** - ****************************************************************************** - * @brief EXTI header file of the firmware library. - ****************************************************************************** - */ - -/* Define to prevent recursive inclusion -------------------------------------*/ -#ifndef __GD32F10X_EXTI_H -#define __GD32F10X_EXTI_H - -#ifdef __cplusplus -extern "C" { -#endif - -/* Includes ------------------------------------------------------------------*/ -#include "gd32f10x.h" - -/** @addtogroup GD32F10x_Firmware - * @{ - */ - -/** @addtogroup EXTI - * @{ - */ - -/** @defgroup EXTI_Exported_Types - * @{ - */ - -/** - * @brief EXTI Mode enumeration - */ -typedef enum { - EXTI_Mode_Interrupt = 0x00, - EXTI_Mode_Event = 0x04 -} EXTI_ModePara; - -/** - * @brief EXTI Trigger enumeration - */ -typedef enum { - EXTI_Trigger_Rising = 0x08, - EXTI_Trigger_Falling = 0x0C, - EXTI_Trigger_Rising_Falling = 0x10 -} EXTI_TriggerPara; - -/** - * @brief EXTI Initial Parameters - */ -typedef struct { - uint32_t EXTI_LINE; /*!< The selection of EXTI lines. */ - EXTI_ModePara EXTI_Mode; /*!< The mode for the EXTI lines, detailed in @ref EXTIMode_Para. */ - EXTI_TriggerPara EXTI_Trigger; /*!< The trigger edge for the EXTI lines, detailed in EXTI_TriggerPara. */ - TypeState EXTI_LINEEnable; /*!< The new value of the selected EXTI lines. */ -} EXTI_InitPara; - -/** - * @} - */ - -/** @defgroup EXTI_Exported_Constants - * @{ - */ - -/** @defgroup EXTI_lines - * @{ - */ -#define EXTI_LINE0 ((uint32_t)0x00000001) /*!< External interrupt line 0 */ -#define EXTI_LINE1 ((uint32_t)0x00000002) /*!< External interrupt line 1 */ -#define EXTI_LINE2 ((uint32_t)0x00000004) /*!< External interrupt line 2 */ -#define EXTI_LINE3 ((uint32_t)0x00000008) /*!< External interrupt line 3 */ -#define EXTI_LINE4 ((uint32_t)0x00000010) /*!< External interrupt line 4 */ -#define EXTI_LINE5 ((uint32_t)0x00000020) /*!< External interrupt line 5 */ -#define EXTI_LINE6 ((uint32_t)0x00000040) /*!< External interrupt line 6 */ -#define EXTI_LINE7 ((uint32_t)0x00000080) /*!< External interrupt line 7 */ -#define EXTI_LINE8 ((uint32_t)0x00000100) /*!< External interrupt line 8 */ -#define EXTI_LINE9 ((uint32_t)0x00000200) /*!< External interrupt line 9 */ -#define EXTI_LINE10 ((uint32_t)0x00000400) /*!< External interrupt line 10 */ -#define EXTI_LINE11 ((uint32_t)0x00000800) /*!< External interrupt line 11 */ -#define EXTI_LINE12 ((uint32_t)0x00001000) /*!< External interrupt line 12 */ -#define EXTI_LINE13 ((uint32_t)0x00002000) /*!< External interrupt line 13 */ -#define EXTI_LINE14 ((uint32_t)0x00004000) /*!< External interrupt line 14 */ -#define EXTI_LINE15 ((uint32_t)0x00008000) /*!< External interrupt line 15 */ - -#define EXTI_LINE16 ((uint32_t)0x00010000) /*!< External interrupt line 16 - Connected to the LVD */ -#define EXTI_LINE17 ((uint32_t)0x00020000) /*!< External interrupt line 17 - Connected to the RTC Alarm */ -#define EXTI_LINE18 ((uint32_t)0x00040000) /*!< External interrupt line 18 - Connected to the USB Wakeup */ -#define EXTI_LINE19 ((uint32_t)0x00080000) /*!< External interrupt line 19 - Connected to the Ethernet Wakeup */ - -/** - * @} - */ - -/** - * @} - */ - -/** @defgroup EXTI_Exported_Functions - * @{ - */ -void EXTI_DeInit(EXTI_InitPara *EXTI_InitParaStruct); -void EXTI_Init(EXTI_InitPara *EXTI_InitParaStruct); -void EXTI_SWINT_Enable(uint32_t EXTI_LINE); -TypeState EXTI_GetBitState(uint32_t EXTI_LINE); -void EXTI_ClearBitState(uint32_t EXTI_LINE); -TypeState EXTI_GetIntBitState(uint32_t EXTI_LINE); -void EXTI_ClearIntBitState(uint32_t EXTI_LINE); - -#ifdef __cplusplus -} -#endif - -#endif /* __GD32F10X_EXTI_H */ - -/** - * @} - */ - -/** - * @} - */ - -/** - * @} - */ - diff --git a/bsp/gd32103c-eval/Libraries/GD32F1xx_standard_peripheral/Include/gd32f10x_fmc.h b/bsp/gd32103c-eval/Libraries/GD32F1xx_standard_peripheral/Include/gd32f10x_fmc.h deleted file mode 100644 index e57bf6b951..0000000000 --- a/bsp/gd32103c-eval/Libraries/GD32F1xx_standard_peripheral/Include/gd32f10x_fmc.h +++ /dev/null @@ -1,263 +0,0 @@ -/** - ****************************************************************************** - * @brief FMC header file of the firmware library. - ****************************************************************************** - */ - -/* Define to prevent recursive inclusion -------------------------------------*/ -#ifndef __GD32F10X_FMC_H -#define __GD32F10X_FMC_H - -#ifdef __cplusplus -extern "C" { -#endif - -/* Includes ------------------------------------------------------------------*/ -#include "gd32f10x.h" - -/** @addtogroup GD32F10x_Firmware - * @{ - */ - -/** @addtogroup FMC - * @{ - */ - -/* Exported types ------------------------------------------------------------*/ - -/** @defgroup FMC_Exported_Types - * @{ - */ - -/** - * @brief FMC State - */ -typedef enum { - FMC_READY, - FMC_BSY, - FMC_WRPERR, - FMC_PGERR, - FMC_TIMEOUT_ERR -} FMC_State; - -/** - * @} - */ - -/* Exported constants --------------------------------------------------------*/ - -/** @defgroup FMC_Exported_Constants - * @{ - */ - -/** @defgroup FMC_Interrupts - * @{ - */ - -#define FMC_INT_EOP FMC_CMR_ENDIE /*!< End of programming interrupt source */ -#define FMC_INT_ERR FMC_CMR_ERIE /*!< Error interrupt source */ -#define FMC_INT_B2_EOP ((uint32_t)0x80000400) /*!< Bank2 End of programming interrupt source */ -#define FMC_INT_B2_ERR ((uint32_t)0x80001000) /*!< Bank2 Error interrupt source */ -/** - * @} - */ - -/** @defgroup FMC_Option_Bytes_Write_Protection - * @{ - */ - - -#define WRP_SECTOR0 ((uint32_t)0x00000001) /*!< Write protection of sector 0 */ -#define WRP_SECTOR1 ((uint32_t)0x00000002) /*!< Write protection of sector 1 */ -#define WRP_SECTOR2 ((uint32_t)0x00000004) /*!< Write protection of sector 2 */ -#define WRP_SECTOR3 ((uint32_t)0x00000008) /*!< Write protection of sector 3 */ -#define WRP_SECTOR4 ((uint32_t)0x00000010) /*!< Write protection of sector 4 */ -#define WRP_SECTOR5 ((uint32_t)0x00000020) /*!< Write protection of sector 5 */ -#define WRP_SECTOR6 ((uint32_t)0x00000040) /*!< Write protection of sector 6 */ -#define WRP_SECTOR7 ((uint32_t)0x00000080) /*!< Write protection of sector 7 */ -#define WRP_SECTOR8 ((uint32_t)0x00000100) /*!< Write protection of sector 8 */ -#define WRP_SECTOR9 ((uint32_t)0x00000200) /*!< Write protection of sector 9 */ -#define WRP_SECTOR10 ((uint32_t)0x00000400) /*!< Write protection of sector 10 */ -#define WRP_SECTOR11 ((uint32_t)0x00000800) /*!< Write protection of sector 11 */ -#define WRP_SECTOR12 ((uint32_t)0x00001000) /*!< Write protection of sector 12 */ -#define WRP_SECTOR13 ((uint32_t)0x00002000) /*!< Write protection of sector 13 */ -#define WRP_SECTOR14 ((uint32_t)0x00004000) /*!< Write protection of sector 14 */ -#define WRP_SECTOR15 ((uint32_t)0x00008000) /*!< Write protection of sector 15 */ -#define WRP_SECTOR16 ((uint32_t)0x00010000) /*!< Write protection of sector 16 */ -#define WRP_SECTOR17 ((uint32_t)0x00020000) /*!< Write protection of sector 17 */ -#define WRP_SECTOR18 ((uint32_t)0x00040000) /*!< Write protection of sector 18 */ -#define WRP_SECTOR19 ((uint32_t)0x00080000) /*!< Write protection of sector 19 */ -#define WRP_SECTOR20 ((uint32_t)0x00100000) /*!< Write protection of sector 20 */ -#define WRP_SECTOR21 ((uint32_t)0x00200000) /*!< Write protection of sector 21 */ -#define WRP_SECTOR22 ((uint32_t)0x00400000) /*!< Write protection of sector 22 */ -#define WRP_SECTOR23 ((uint32_t)0x00800000) /*!< Write protection of sector 23 */ -#define WRP_SECTOR24 ((uint32_t)0x01000000) /*!< Write protection of sector 24 */ -#define WRP_SECTOR25 ((uint32_t)0x02000000) /*!< Write protection of sector 25 */ -#define WRP_SECTOR26 ((uint32_t)0x04000000) /*!< Write protection of sector 26 */ -#define WRP_SECTOR27 ((uint32_t)0x08000000) /*!< Write protection of sector 27 */ -#define WRP_SECTOR28 ((uint32_t)0x10000000) /*!< Write protection of sector 28 */ -#define WRP_SECTOR29 ((uint32_t)0x20000000) /*!< Write protection of sector 29 */ -#define WRP_SECTOR30 ((uint32_t)0x40000000) /*!< Write protection of sector 30 */ -#define WRP_SECTOR31 ((uint32_t)0x80000000) /*!< Write protection of sector 31 */ - -#define WRP_ALLSECTORS ((uint32_t)0xFFFFFFFF) /*!< Write protection of all Sectors */ - -/** - * @} - */ - -/** @defgroup FMC_Option_Bytes_Read_Protection - * @{ - */ - - -/** - * @brief FMC_Read Protection Level - */ -#define RDP_LEVEL_0 ((uint8_t)0xA5) -#define RDP_LEVEL_1 ((uint8_t)0xBB) - -/** - * @} - */ - -/** @defgroup FMC_Option_Bytes_IWatchdog - * @{ - */ -#define OB_IWDG_SW ((uint8_t)0x01) /*!< Software IWDG selected */ -#define OB_IWDG_HW ((uint8_t)0x00) /*!< Hardware IWDG selected */ - -/** - * @} - */ - -/** @defgroup FMC_Option_Bytes_nRST_DEEPSLEEP - * @{ - */ -#define OB_DEEPSLEEP_NORST ((uint8_t)0x02) /*!< No reset generated when entering in DEEPSLEEP */ -#define OB_DEEPSLEEP_RST ((uint8_t)0x00) /*!< Reset generated when entering in DEEPSLEEP */ - -/** - * @} - */ - -/** @defgroup FMC_Option_Bytes_nRST_STDBY - * @{ - */ -#define OB_STDBY_NORST ((uint8_t)0x04) /*!< No reset generated when entering in STANDBY */ -#define OB_STDBY_RST ((uint8_t)0x00) /*!< Reset generated when entering in STANDBY */ - -/** - * @} - */ - -/** @defgroup FMC_Option_Bytes_BOOT - * @{ - */ -#define OB_BOOT_B1 ((uint8_t)0x08) /*!< BOOT from Bank1 */ -#define OB_BOOT_B2 ((uint8_t)0x00) /*!< BOOT from Bank2 */ -#define OB_USER_BFB2 ((uint16_t)0x0008) /*!< Configure BOOT from Bank1 */ -/** - * @} - */ - - - -/** @defgroup FMC_Flags - * @{ - */ - -#define FMC_FLAG_BSY FMC_CSR_BUSY /*!< FMC Busy flag */ -#define FMC_FLAG_PERR FMC_CSR_PGEF /*!< FMC Programming error flag */ -#define FMC_FLAG_WERR FMC_CSR_WPEF /*!< FMC Write protected error flag */ -#define FMC_FLAG_EOP FMC_CSR_ENDF /*!< FMC End of Programming flag */ -#define FMC_FLAG_OPTERR ((uint32_t)0x00000001) /*!< FMC Option Byte error flag */ -#define FMC_FLAG_B2_BSY ((uint32_t)0x80000001) /*!< FMC Busy flag */ -#define FMC_FLAG_B2_PERR ((uint32_t)0x80000004) /*!< FMC Programming error flag */ -#define FMC_FLAG_B2_WERR ((uint32_t)0x80000010) /*!< FMC Write protected error flag */ -#define FMC_FLAG_B2_EOP ((uint32_t)0x80000020) /*!< FMC End of Programming flag */ -/** - * @} - */ - -/** @defgroup FMC_Timeout_definition - * @{ - */ -#define FMC_TIMEOUT_COUNT ((uint32_t)0x000F0000) -/** - * @} - */ -/* FMC BANK address */ -#define FMC_B1_END_ADDRESS ((uint32_t)0x807FFFF) -#define FMC_BANK1_SIZE 0x0200 -#define FMC_SIZE (*(uint16_t *)0x1ffff7e0) -/** - * @} - */ - -/** @defgroup FMC_Exported_Functions - * @{ - */ - -/** - * @brief FMC memory functions. - */ -/* FMC Main Memory Programming functions *****************************************/ -void FMC_Unlock(void); -void FMC_UnlockB1(void); -void FMC_UnlockB2(void); -void FMC_Lock(void); -void FMC_LockB1(void); -void FMC_LockB2(void); -FMC_State FMC_ErasePage(uint32_t Page_Address); -FMC_State FMC_MassErase(void); -FMC_State FMC_MassB1Erase(void); -FMC_State FMC_MassB2Erase(void); -FMC_State FMC_ProgramWord(uint32_t Address, uint32_t Data); - -/* FMC Option Bytes Programming functions *****************************************/ -void FMC_OB_Unlock(void); -void FMC_OB_Lock(void); -void FMC_OB_Reset(void); -FMC_State FMC_OB_Erase(void); -FMC_State FMC_OB_EnableWRP(uint32_t OB_WRP); -FMC_State FMC_ReadOutProtection(TypeState NewValue); -FMC_State FMC_OB_RDPConfig(uint8_t OB_RDP); -FMC_State FMC_OB_UserConfig(uint8_t OB_IWDG, uint8_t OB_DEEPSLEEP, uint8_t OB_STDBY); -FMC_State FMC_OB_BOOTConfig(uint8_t OB_BOOT); -FMC_State FMC_OB_WriteUser(uint8_t OB_USER); -FMC_State FMC_ProgramOptionByteData(uint32_t Address, uint8_t Data); -uint8_t FMC_OB_GetUser(void); -uint32_t FMC_OB_GetWRP(void); -TypeState FMC_OB_GetRDP(void); - -/* FMC Interrupts and flags management functions **********************************/ -void FMC_INTConfig(uint32_t FMC_INT, TypeState NewValue); -TypeState FMC_GetBitState(uint32_t FMC_FLAG); -void FMC_ClearBitState(uint32_t FMC_FLAG); -FMC_State FMC_GetState(void); -FMC_State FMC_GetB1State(void); -FMC_State FMC_GetB2State(void); -FMC_State FMC_WaitReady(uint32_t uCount); -FMC_State FMC_B1_WaitReady(uint32_t uCount); -FMC_State FMC_B2_WaitReady(uint32_t uCount); - - -#ifdef __cplusplus -} -#endif - -#endif /* __GD32F10X_FMC_H */ - -/** - * @} - */ - -/** - * @} - */ - -/** - * @} - */ - diff --git a/bsp/gd32103c-eval/Libraries/GD32F1xx_standard_peripheral/Include/gd32f10x_gpio.h b/bsp/gd32103c-eval/Libraries/GD32F1xx_standard_peripheral/Include/gd32f10x_gpio.h deleted file mode 100644 index d32c81a7f9..0000000000 --- a/bsp/gd32103c-eval/Libraries/GD32F1xx_standard_peripheral/Include/gd32f10x_gpio.h +++ /dev/null @@ -1,281 +0,0 @@ -/** - ****************************************************************************** - * @brief GPIO header file of the firmware library. - ****************************************************************************** - */ - -/* Define to prevent recursive inclusion -------------------------------------*/ -#ifndef __GD32F10x_GPIO_H -#define __GD32F10x_GPIO_H - -#ifdef __cplusplus -extern "C" { -#endif - -/* Includes ------------------------------------------------------------------*/ -#include "gd32f10x.h" - -/** @addtogroup GD32F10x_Firmware - * @{ - */ - -/** @addtogroup GPIO - * @{ - */ - -/** @defgroup GPIO_Exported_Types - * @{ - */ - -/** - * @brief Output_Maximum_frequency_enumeration - */ -typedef enum { - GPIO_SPEED_10MHZ = 1, - GPIO_SPEED_2MHZ, - GPIO_SPEED_50MHZ -} GPIO_SpeedPara; - -/** - * @brief GPIO_Mode_enumeration - */ -typedef enum { - GPIO_MODE_AIN = 0x0, - GPIO_MODE_IN_FLOATING = 0x04, - GPIO_MODE_IPD = 0x28, - GPIO_MODE_IPU = 0x48, - GPIO_MODE_OUT_OD = 0x14, - GPIO_MODE_OUT_PP = 0X10, - GPIO_MODE_AF_OD = 0X1C, - GPIO_MODE_AF_PP = 0X18 -} GPIO_ModePara; - -/** - * @brief GPIO Initial Parameters - */ -typedef struct { - uint16_t GPIO_Pin; /*!< The GPIO pins to be configured. choose several from @ref GPIO_pins_define */ - GPIO_SpeedPara GPIO_Speed; /*!< The speed for This parameter can be a value of @ref GPIOSpeed_TypeDef */ - GPIO_ModePara GPIO_Mode; /*!< The operating mode for the selected pins. choose one from @ref GPIO_ModePara */ -} GPIO_InitPara; - -/** - * @brief Bit_State_enumeration - */ -typedef enum { - Bit_RESET = 0, - Bit_SET -} BitState; - -/** - * @} - */ - -/** @defgroup GPIO_Exported_Constants - * @{ - */ - -/** @defgroup GPIO_pins_define - * @{ - */ -#define GPIO_PIN_0 ((uint16_t)0x0001) -#define GPIO_PIN_1 ((uint16_t)0x0002) -#define GPIO_PIN_2 ((uint16_t)0x0004) -#define GPIO_PIN_3 ((uint16_t)0x0008) -#define GPIO_PIN_4 ((uint16_t)0x0010) -#define GPIO_PIN_5 ((uint16_t)0x0020) -#define GPIO_PIN_6 ((uint16_t)0x0040) -#define GPIO_PIN_7 ((uint16_t)0x0080) -#define GPIO_PIN_8 ((uint16_t)0x0100) -#define GPIO_PIN_9 ((uint16_t)0x0200) -#define GPIO_PIN_10 ((uint16_t)0x0400) -#define GPIO_PIN_11 ((uint16_t)0x0800) -#define GPIO_PIN_12 ((uint16_t)0x1000) -#define GPIO_PIN_13 ((uint16_t)0x2000) -#define GPIO_PIN_14 ((uint16_t)0x4000) -#define GPIO_PIN_15 ((uint16_t)0x8000) -#define GPIO_PIN_ALL ((uint16_t)0xFFFF) - -/** - * @} - */ - -/** @defgroup GPIO_Remap_define - * @{ - */ -#define GPIO_REMAP_SPI1 ((uint32_t)0x00000001) -#define GPIO_REMAP_I2C1 ((uint32_t)0x00000002) -#define GPIO_REMAP_USART1 ((uint32_t)0x00000004) -#define GPIO_REMAP_USART2 ((uint32_t)0x00000008) -#define GPIO_PARTIAL_REMAP_USART3 ((uint32_t)0x00140010) -#define GPIO_FULL_REMAP_USART3 ((uint32_t)0x00140030) -#define GPIO_PARTIAL_REMAP_TIMER1 ((uint32_t)0x00160040) -#define GPIO_FULL_REMAP_TIMER1 ((uint32_t)0x001600C0) -#define GPIO_PARTIAL_REMAP1_TIMER2 ((uint32_t)0x00180100) -#define GPIO_PARTIAL_REMAP2_TIMER2 ((uint32_t)0x00180200) -#define GPIO_FULL_REMAP_TIMER2 ((uint32_t)0x00180300) -#define GPIO_PARTIAL_REMAP_TIMER3 ((uint32_t)0x001A0800) -#define GPIO_FULL_REMAP_TIMER3 ((uint32_t)0x001A0C00) -#define GPIO_REMAP_TIMER4 ((uint32_t)0x00001000) -#define GPIO_REMAP1_CAN1 ((uint32_t)0x001D4000) -#define GPIO_REMAP2_CAN1 ((uint32_t)0x001D6000) -#define GPIO_REMAP_PD01 ((uint32_t)0x00008000) -#define GPIO_REMAP_TIMER5CH4_LSI ((uint32_t)0x00200001) -#define GPIO_REMAP_ADC1_ETRGINJ ((uint32_t)0x00200002) -#define GPIO_REMAP_ADC1_ETRGREG ((uint32_t)0x00200004) -#define GPIO_REMAP_ADC2_ETRGINJ ((uint32_t)0x00200008) -#define GPIO_REMAP_ADC2_ETRGREG ((uint32_t)0x00200010) -#define GPIO_REMAP_ETH ((uint32_t)0x00200020) -#define GPIO_REMAP_CAN2 ((uint32_t)0x00200040) -#define GPIO_REMAP_SWJ_NOJTRST ((uint32_t)0x00300100) -#define GPIO_REMAP_SWJ_JTAGDISABLE ((uint32_t)0x00300200) -#define GPIO_REMAP_SWJ_DISABLE ((uint32_t)0x00300400) -#define GPIO_REMAP_SPI3 ((uint32_t)0x00201100) -#define GPIO_REMAP_TIMER2ITR1_PTP_SOF ((uint32_t)0x00202000) -#define GPIO_REMAP_PTP_PPS ((uint32_t)0x00204000) -#define GPIO_REMAP_TIMER15 ((uint32_t)0x80000001) -#define GPIO_REMAP_TIMER16 ((uint32_t)0x80000002) -#define GPIO_REMAP_TIMER17 ((uint32_t)0x80000004) -#define GPIO_REMAP_CEC ((uint32_t)0x80000008) -#define GPIO_REMAP_TIMER1_DMA ((uint32_t)0x80000010) -#define GPIO_REMAP_TIMER9 ((uint32_t)0x80000020) -#define GPIO_REMAP_TIMER10 ((uint32_t)0x80000040) -#define GPIO_REMAP_TIMER11 ((uint32_t)0x80000080) -#define GPIO_REMAP_TIMER13 ((uint32_t)0x80000100) -#define GPIO_REMAP_TIMER14 ((uint32_t)0x80000200) -#define GPIO_REMAP_EXMC_NADV ((uint32_t)0x80000400) -#define GPIO_REMAP_TIMER67_DAC_DMA ((uint32_t)0x80000800) -#define GPIO_REMAP_TIMER12 ((uint32_t)0x80001000) -#define GPIO_REMAP_MISC ((uint32_t)0x80002000) - -/** - * @} - */ - -/** @defgroup GPIO_Port_Sources - * @{ - */ -#define GPIO_PORT_SOURCE_GPIOA ((uint8_t)0x00) -#define GPIO_PORT_SOURCE_GPIOB ((uint8_t)0x01) -#define GPIO_PORT_SOURCE_GPIOC ((uint8_t)0x02) -#define GPIO_PORT_SOURCE_GPIOD ((uint8_t)0x03) -#define GPIO_PORT_SOURCE_GPIOE ((uint8_t)0x04) -#define GPIO_PORT_SOURCE_GPIOF ((uint8_t)0x05) -#define GPIO_PORT_SOURCE_GPIOG ((uint8_t)0x06) - -/** - * @} - */ - -/** @defgroup GPIO_Pin_sources - * @{ - */ -#define GPIO_PINSOURCE0 ((uint8_t)0x00) -#define GPIO_PINSOURCE1 ((uint8_t)0x01) -#define GPIO_PINSOURCE2 ((uint8_t)0x02) -#define GPIO_PINSOURCE3 ((uint8_t)0x03) -#define GPIO_PINSOURCE4 ((uint8_t)0x04) -#define GPIO_PINSOURCE5 ((uint8_t)0x05) -#define GPIO_PINSOURCE6 ((uint8_t)0x06) -#define GPIO_PINSOURCE7 ((uint8_t)0x07) -#define GPIO_PINSOURCE8 ((uint8_t)0x08) -#define GPIO_PINSOURCE9 ((uint8_t)0x09) -#define GPIO_PINSOURCE10 ((uint8_t)0x0A) -#define GPIO_PINSOURCE11 ((uint8_t)0x0B) -#define GPIO_PINSOURCE12 ((uint8_t)0x0C) -#define GPIO_PINSOURCE13 ((uint8_t)0x0D) -#define GPIO_PINSOURCE14 ((uint8_t)0x0E) -#define GPIO_PINSOURCE15 ((uint8_t)0x0F) - -/** - * @} - */ - -/** @defgroup Ethernet_Media_Interface - * @{ - */ -#define GPIO_ETH_MEDIAINTERFACE_MII ((uint32_t)0x00000000) -#define GPIO_ETH_MEDIAINTERFACE_RMII ((uint32_t)0x00800000) - -/** - * @} - */ - -/* output mode definitions */ -#define CTL_CLTR(regval) (BITS(0,1) & ((uint32_t)(regval) << 0)) -#define GPIO_MODE_INPUT CTL_CLTR(0) /*!< input mode */ -#define GPIO_MODE_OUTPUT CTL_CLTR(1) /*!< output mode */ -#define GPIO_MODE_AF CTL_CLTR(2) /*!< alternate function mode */ -#define GPIO_MODE_ANALOG CTL_CLTR(3) /*!< analog mode */ - -/** @defgroup AFIO_Event_Output - * @{ - */ -#define AFIO_ECR_EVOE_SET ((uint32_t)0x00000080) -#define AFIO_ECR_EVOE_RESET ((uint32_t)0xffffff7f) - -/* gpio alternate function */ -#define AF(regval) (BITS(0,3) & ((uint32_t)(regval) << 0)) -#define GPIO_AF_0 AF(0) /*!< alternate function selected 0 */ -#define GPIO_AF_1 AF(1) /*!< alternate function selected 1 */ -#define GPIO_AF_2 AF(2) /*!< alternate function selected 2 */ -#define GPIO_AF_3 AF(3) /*!< alternate function selected 3 */ -#define GPIO_AF_4 AF(4) /*!< alternate function selected 4 */ -#define GPIO_AF_5 AF(5) /*!< alternate function selected 5 */ -#define GPIO_AF_6 AF(6) /*!< alternate function selected 6 */ -#define GPIO_AF_7 AF(7) /*!< alternate function selected 7 */ -#define GPIO_AF_8 AF(8) /*!< alternate function selected 8 */ -#define GPIO_AF_9 AF(9) /*!< alternate function selected 9 */ -#define GPIO_AF_10 AF(10) /*!< alternate function selected 10 */ -#define GPIO_AF_11 AF(11) /*!< alternate function selected 11 */ -#define GPIO_AF_12 AF(12) /*!< alternate function selected 12 */ -#define GPIO_AF_13 AF(13) /*!< alternate function selected 13 */ -#define GPIO_AF_14 AF(14) /*!< alternate function selected 14 */ -#define GPIO_AF_15 AF(15) /*!< alternate function selected 15 */ - -/** - * @} - */ - -/** - * @} - */ - -/** @defgroup GPIO_Exported_Functions - * @{ - */ -void GPIO_DeInit(GPIO_TypeDef *GPIOx); -void GPIO_AFDeInit(void); -void GPIO_Init(GPIO_TypeDef *GPIOx, GPIO_InitPara *GPIO_InitStruct); -void GPIO_ParaInit(GPIO_InitPara *GPIO_InitStruct); -uint8_t GPIO_ReadInputBit(GPIO_TypeDef *GPIOx, uint16_t GPIO_Pin); -uint16_t GPIO_ReadInputData(GPIO_TypeDef *GPIOx); -uint8_t GPIO_ReadOutputBit(GPIO_TypeDef *GPIOx, uint16_t GPIO_Pin); -uint16_t GPIO_ReadOutputData(GPIO_TypeDef *GPIOx); -void GPIO_SetBits(GPIO_TypeDef *GPIOx, uint16_t GPIO_Pin); -void GPIO_ResetBits(GPIO_TypeDef *GPIOx, uint16_t GPIO_Pin); -void GPIO_WriteBit(GPIO_TypeDef *GPIOx, uint16_t GPIO_Pin, BitState BitVal); -void GPIO_Write(GPIO_TypeDef *GPIOx, uint16_t PortVal); -void GPIO_PinLockConfig(GPIO_TypeDef *GPIOx, uint16_t GPIO_Pin); -void GPIO_EventOutputConfig(uint8_t GPIO_PortSource, uint8_t GPIO_PinSource); -void GPIO_EventOutputEnable(TypeState NewState); -void GPIO_PinRemapConfig(uint32_t GPIO_Remap, TypeState NewState); -void GPIO_EXTILineConfig(uint8_t GPIO_PortSource, uint8_t GPIO_PinSource); -void GPIO_ETH_MediaInterfaceConfig(uint32_t GPIO_ETH_MediaInterface); - -#ifdef __cplusplus -} -#endif - -#endif /* __GD32F10X_GPIO_H */ -/** - * @} - */ - -/** - * @} - */ - -/** - * @} - */ diff --git a/bsp/gd32103c-eval/Libraries/GD32F1xx_standard_peripheral/Include/gd32f10x_i2c.h b/bsp/gd32103c-eval/Libraries/GD32F1xx_standard_peripheral/Include/gd32f10x_i2c.h deleted file mode 100644 index 8017f10a33..0000000000 --- a/bsp/gd32103c-eval/Libraries/GD32F1xx_standard_peripheral/Include/gd32f10x_i2c.h +++ /dev/null @@ -1,289 +0,0 @@ -/** - ****************************************************************************** - * @brief I2C header file of the firmware library. - ****************************************************************************** - */ - -/* Define to prevent recursive inclusion -------------------------------------*/ -#ifndef __GD32F10X_I2C_H -#define __GD32F10X_I2C_H - -#ifdef __cplusplus -extern "C" { -#endif - -/* Includes ------------------------------------------------------------------*/ -#include "gd32f10x.h" - -/** @addtogroup GD32F10x_Firmware - * @{ - */ - -/** @addtogroup I2C - * @{ - */ - -/** @defgroup I2C_Exported_Types - * @{ - */ - -/** - * @brief I2C Initial Parameters - */ -typedef struct { - uint16_t I2C_Protocol; /*!< The protocol type, detailed in @ref I2C_Protocol */ - uint16_t I2C_DutyCycle; /*!< The fast mode duty cycle, detailed in @ref I2C_Duty_Cycle */ - uint32_t I2C_BitRate; /*!< The I2C bit rate which must be lower than 400k bit/s */ - uint16_t I2C_AddressingMode; /*!< The I2C addressing mode, detailed in @ref I2C_Addressing_Mode */ - uint16_t I2C_DeviceAddress; /*!< The device address */ -} I2C_InitPara; - -/** - * @} - */ - -/** @defgroup I2C_Exported_Constants - * @{ - */ - -/** @defgroup I2C_Protocol - * @{ - */ -#define I2C_PROTOCOL_I2C ((uint16_t)0x0000) -#define I2C_PROTOCOL_SMBUSDEVICE ((uint16_t)0x0002) -#define I2C_PROTOCOL_SMBUSHOST ((uint16_t)0x000A) - -/** - * @} - */ - -/** @defgroup I2C_Duty_Cycle - * @{ - */ -#define I2C_DUTYCYCLE_16_9 ((uint16_t)0x4000) /*!< I2C fast mode Tlow/Thigh = 16/9 */ -#define I2C_DUTYCYCLE_2 ((uint16_t)0xBFFF) /*!< I2C fast mode Tlow/Thigh = 2 */ - -/** - * @} - */ - -/** @defgroup I2C_Addressing_Mode - * @{ - */ -#define I2C_ADDRESSING_MODE_7BIT ((uint16_t)0x4000) -#define I2C_ADDRESSING_MODE_10BIT ((uint16_t)0xC000) - -/** - * @} - */ - -/** @defgroup I2C_Direction - * @{ - */ -#define I2C_DIRECTION_TRANSMITTER ((uint8_t)0x00) -#define I2C_DIRECTION_RECEIVER ((uint8_t)0x01) - -/** - * @} - */ - -/** @defgroup I2C_Registers - * @{ - */ -#define I2C_REGISTER_CTLR1 ((uint8_t)0x00) -#define I2C_REGISTER_CTLR2 ((uint8_t)0x04) -#define I2C_REGISTER_AR1 ((uint8_t)0x08) -#define I2C_REGISTER_AR2 ((uint8_t)0x0C) -#define I2C_REGISTER_DTR ((uint8_t)0x10) -#define I2C_REGISTER_STR1 ((uint8_t)0x14) -#define I2C_REGISTER_STR2 ((uint8_t)0x18) -#define I2C_REGISTER_CLKR ((uint8_t)0x1C) -#define I2C_REGISTER_RTR ((uint8_t)0x20) - -/** - * @} - */ - -/** @defgroup I2C_PEC_Position - * @{ - */ -#define I2C_PECPOSITION_NEXT I2C_CTLR1_POAP -#define I2C_PECPOSITION_CURRENT ((uint16_t)~I2C_CTLR1_POAP) - -/** - * @} - */ - -/** @defgroup I2C_NACK_Position - * @{ - */ -#define I2C_NACKPOSITION_NEXT I2C_CTLR1_POAP -#define I2C_NACKPOSITION_CURRENT ((uint16_t)~I2C_CTLR1_POAP) - -/** - * @} - */ - -/** @defgroup I2C_Interrupt_Control - * @{ - */ -#define I2C_INT_EIE I2C_CTLR2_EIE -#define I2C_INT_EE I2C_CTLR2_EE -#define I2C_INT_BIE I2C_CTLR2_BIE - -/** - * @} - */ - -/** @defgroup I2C_Interrupt_Source - * @{ - */ -#define I2C_INT_SMBALTS ((uint32_t)0x01008000) -#define I2C_INT_SMBTO ((uint32_t)0x01004000) -#define I2C_INT_PECE ((uint32_t)0x01001000) -#define I2C_INT_RXORE ((uint32_t)0x01000800) -#define I2C_INT_AE ((uint32_t)0x01000400) -#define I2C_INT_LOSTARB ((uint32_t)0x01000200) -#define I2C_INT_BE ((uint32_t)0x01000100) -#define I2C_INT_TBE ((uint32_t)0x06000080) -#define I2C_INT_RBNE ((uint32_t)0x06000040) -#define I2C_INT_STPSEND ((uint32_t)0x02000010) -#define I2C_INT_ADD10SEND ((uint32_t)0x02000008) -#define I2C_INT_BTC ((uint32_t)0x02000004) -#define I2C_INT_ADDSEND ((uint32_t)0x02000002) -#define I2C_INT_SBSEND ((uint32_t)0x02000001) - -/** - * @} - */ - -/** @defgroup I2C_FLAG - * @{ - */ - -/** - * @brief STR2 register flags - */ -#define I2C_FLAG_DUMODF ((uint32_t)0x00800000) -#define I2C_FLAG_HSTSMB ((uint32_t)0x00400000) -#define I2C_FLAG_DEFSMB ((uint32_t)0x00200000) -#define I2C_FLAG_RXGC ((uint32_t)0x00100000) -#define I2C_FLAG_TRS ((uint32_t)0x00040000) -#define I2C_FLAG_I2CBSY ((uint32_t)0x00020000) -#define I2C_FLAG_MASTER ((uint32_t)0x00010000) - -/** - * @brief STR1 register flags - */ -#define I2C_FLAG_SMBALTS ((uint32_t)0x10008000) -#define I2C_FLAG_SMBTO ((uint32_t)0x10004000) -#define I2C_FLAG_PECE ((uint32_t)0x10001000) -#define I2C_FLAG_RXORE ((uint32_t)0x10000800) -#define I2C_FLAG_AE ((uint32_t)0x10000400) -#define I2C_FLAG_LOSTARB ((uint32_t)0x10000200) -#define I2C_FLAG_BE ((uint32_t)0x10000100) -#define I2C_FLAG_TBE ((uint32_t)0x10000080) -#define I2C_FLAG_RBNE ((uint32_t)0x10000040) -#define I2C_FLAG_STPSEND ((uint32_t)0x10000010) -#define I2C_FLAG_ADD10SEND ((uint32_t)0x10000008) -#define I2C_FLAG_BTC ((uint32_t)0x10000004) -#define I2C_FLAG_ADDSEND ((uint32_t)0x10000002) -#define I2C_FLAG_SBSEND ((uint32_t)0x10000001) - -/** - * @} - */ - -/** @defgroup I2C_ProgrammingMode - * @{ - */ -#define I2C_PROGRAMMINGMODE_MASTER_SBSEND ((uint32_t)0x00030001) /*!< I2CBSY, MASTER and SBSEND flag */ - -#define I2C_PROGRAMMINGMODE_MASTER_TRANSMITTER_ADDSEND ((uint32_t)0x00070002) /*!< I2CBSY, MASTER, ADDSEND and TRS flags */ -#define I2C_PROGRAMMINGMODE_MASTER_RECEIVER_ADDSEND ((uint32_t)0x00030002) /*!< I2CBSY, MASTER and ADDSEND flags */ - -#define I2C_PROGRAMMINGMODE_MASTER_ADD10SEND ((uint32_t)0x00030008) /*!< I2CBSY, MASTER and ADD10SEND flags */ - -#define I2C_PROGRAMMINGMODE_MASTER_BYTE_RECEIVED ((uint32_t)0x00030040) /*!< I2CBSY, MASTER and RBNE flags */ -#define I2C_PROGRAMMINGMODE_MASTER_BYTE_TRANSMITTING ((uint32_t)0x00070080) /*!< TRS, I2CBSY, MASTER, TBE flags */ -#define I2C_PROGRAMMINGMODE_MASTER_BYTE_TRANSMITTED ((uint32_t)0x00070084) /*!< TRS, I2CBSY, MASTER, TBE and BTC flags */ - -#define I2C_PROGRAMMINGMODE_SLAVE_RECEIVER_ADDSEND ((uint32_t)0x00020002) /*!< I2CBSY and ADDSEND flags */ -#define I2C_PROGRAMMINGMODE_SLAVE_TRANSMITTER_ADDSEND ((uint32_t)0x00060002) /*!< TRS, I2CBSY and ADDSEND flags */ - -#define I2C_PROGRAMMINGMODE_SLAVE_RECEIVER_SECONDADDRESS_SELECTED ((uint32_t)0x00820000) /*!< DUMODF and I2CBSY flags */ -#define I2C_PROGRAMMINGMODE_SLAVE_TRANSMITTER_SECONDADDRESS_SELECTED ((uint32_t)0x00860080) /*!< DUMODF, TRS, I2CBSY and TBE flags */ - -#define I2C_PROGRAMMINGMODE_SLAVE_GENERALCALLADDRESS_SELECTED ((uint32_t)0x00120000) /*!< RXGC and I2CBSY flags */ - -#define I2C_PROGRAMMINGMODE_SLAVE_BYTE_RECEIVED ((uint32_t)0x00020040) /*!< I2CBSY and RBNE flags */ -#define I2C_PROGRAMMINGMODE_SLAVE_STOP_DETECTED ((uint32_t)0x00000010) /*!< STPSEND flag */ - -#define I2C_PROGRAMMINGMODE_SLAVE_BYTE_TRANSMITTED ((uint32_t)0x00060084) /*!< TRS, I2CBSY, TBE and BTC flags */ -#define I2C_PROGRAMMINGMODE_SLAVE_BYTE_TRANSMITTING ((uint32_t)0x00060080) /*!< TRS, I2CBSY and TBE flags */ -#define I2C_PROGRAMMINGMODE_SLAVE_ACK_FAILURE ((uint32_t)0x00000400) /*!< AE flag */ - -/** - * @} - */ - -/** - * @} - */ - -/** @defgroup I2C_Exported_Functions - * @{ - */ -void I2C_DeInit(I2C_TypeDef *I2Cx); -void I2C_Init(I2C_TypeDef *I2Cx, I2C_InitPara *I2C_InitParaStruct); -void I2C_ParaInit(I2C_InitPara *I2C_InitParaStruct); -void I2C_Enable(I2C_TypeDef *I2Cx, TypeState NewValue); -void I2C_DMA_Enable(I2C_TypeDef *I2Cx, TypeState NewValue); -void I2C_DMALastTransfer_Enable(I2C_TypeDef *I2Cx, TypeState NewValue); -void I2C_StartOnBus_Enable(I2C_TypeDef *I2Cx, TypeState NewValue); -void I2C_StopOnBus_Enable(I2C_TypeDef *I2Cx, TypeState NewValue); -void I2C_Acknowledge_Enable(I2C_TypeDef *I2Cx, TypeState NewValue); -void I2C_OwnAddress2(I2C_TypeDef *I2Cx, uint8_t Address); -void I2C_DualAddress_Enable(I2C_TypeDef *I2Cx, TypeState NewValue); -void I2C_GeneralCall_Enable(I2C_TypeDef *I2Cx, TypeState NewValue); -void I2C_INTConfig(I2C_TypeDef *I2Cx, uint16_t I2C_INT, TypeState NewValue); -void I2C_SendData(I2C_TypeDef *I2Cx, uint8_t Data); -uint8_t I2C_ReceiveData(I2C_TypeDef *I2Cx); -void I2C_AddressingDevice_7bit(I2C_TypeDef *I2Cx, uint8_t Address, uint8_t I2C_Direction); -uint16_t I2C_ReadRegister(I2C_TypeDef *I2Cx, uint8_t I2C_Register); -void I2C_SoftwareReset_Enable(I2C_TypeDef *I2Cx, TypeState NewValue); -void I2C_NACKPosition_Enable(I2C_TypeDef *I2Cx, uint16_t I2C_NACKPosition); -void I2C_SMBusAlertSend_Enable(I2C_TypeDef *I2Cx, TypeState NewValue); -void I2C_PECTransmit_Enable(I2C_TypeDef *I2Cx, TypeState NewValue); -void I2C_PECPosition_Enable(I2C_TypeDef *I2Cx, uint16_t I2C_PECPosition); -void I2C_PEC_Enable(I2C_TypeDef *I2Cx, TypeState NewValue); -uint8_t I2C_GetPECValue(I2C_TypeDef *I2Cx); -void I2C_ARP_Enable(I2C_TypeDef *I2Cx, TypeState NewValue); -void I2C_StretchClock_Enable(I2C_TypeDef *I2Cx, TypeState NewValue); -void I2C_FastModeDutyCycle(I2C_TypeDef *I2Cx, uint16_t I2C_DutyCycle); - -TypeState I2C_StateDetect(I2C_TypeDef *I2Cx, uint32_t I2C_State); -uint32_t I2C_GetCurrentState(I2C_TypeDef *I2Cx); -TypeState I2C_GetBitState(I2C_TypeDef *I2Cx, uint32_t I2C_FLAG); -void I2C_ClearBitState(I2C_TypeDef *I2Cx, uint32_t I2C_FLAG); -TypeState I2C_GetIntBitState(I2C_TypeDef *I2Cx, uint32_t I2C_INT); -void I2C_ClearIntBitState(I2C_TypeDef *I2Cx, uint32_t I2C_INT); - -#ifdef __cplusplus -} -#endif - -#endif /*__GD32F10X_I2C_H */ - -/** - * @} - */ - -/** - * @} - */ - -/** - * @} - */ - diff --git a/bsp/gd32103c-eval/Libraries/GD32F1xx_standard_peripheral/Include/gd32f10x_iwdg.h b/bsp/gd32103c-eval/Libraries/GD32F1xx_standard_peripheral/Include/gd32f10x_iwdg.h deleted file mode 100644 index 6d3e319fb7..0000000000 --- a/bsp/gd32103c-eval/Libraries/GD32F1xx_standard_peripheral/Include/gd32f10x_iwdg.h +++ /dev/null @@ -1,103 +0,0 @@ -/** - ****************************************************************************** - * @brief IWDG header file of the firmware library. - ****************************************************************************** - */ - -/* Define to prevent recursive inclusion -------------------------------------*/ -#ifndef __GD32F10X_IWDG_H -#define __GD32F10X_IWDG_H - -/* Exported macro ------------------------------------------------------------*/ - -#ifdef __cplusplus -extern "C" { -#endif - -/* Includes ------------------------------------------------------------------*/ -#include "gd32f10x.h" - -/** @addtogroup GD32F10x_Firmware - * @{ - */ - -/** @defgroup IWDG - * @{ - */ - -/** @defgroup IWDG_Exported_Constants - * @{ - */ - -/** @defgroup IWDG_WriteAccess - * @{ - */ -#define IWDG_WRITEACCESS_ENABLE ((uint16_t)0x5555) -#define IWDG_WRITEACCESS_DISABLE ((uint16_t)0x0000) - -/** - * @} - */ - -/** @defgroup IWDG_prescaler - * @{ - */ -#define IWDG_PRESCALER_4 ((uint8_t)0x00) -#define IWDG_PRESCALER_8 ((uint8_t)0x01) -#define IWDG_PRESCALER_16 ((uint8_t)0x02) -#define IWDG_PRESCALER_32 ((uint8_t)0x03) -#define IWDG_PRESCALER_64 ((uint8_t)0x04) -#define IWDG_PRESCALER_128 ((uint8_t)0x05) -#define IWDG_PRESCALER_256 ((uint8_t)0x06) - -/** - * @} - */ - -/** @defgroup IWDG_Flag - * @{ - */ -#define IWDG_BIT_PUD IWDG_STR_PUD -#define IWDG_BIT_RUD IWDG_STR_RUD -#define IWDG_BIT_WUD IWDG_STR_WUD - -/** - * @} - */ - -/** - * @} - */ - -/** @defgroup IWDG_Exported_functions - * @{ - */ -/* Prescaler and Counter configuration functions ******************************/ -void IWDG_Write_Enable(uint16_t IWDG_WriteAccess); -void IWDG_SetPrescaler(uint8_t PrescalerValue); -void IWDG_SetReloadValue(uint16_t ReloadValue); -void IWDG_ReloadCounter(void); - -/* IWDG activation function ***************************************************/ -void IWDG_Enable(void); - -/* Flag management function ***************************************************/ -TypeState IWDG_GetBitState(uint16_t IWDG_FLAG); - -/** - * @} - */ - -#ifdef __cplusplus -} -#endif - -#endif /* __IWDG_GD32F10X_H */ - -/** - * @} - */ - -/** - * @} - */ diff --git a/bsp/gd32103c-eval/Libraries/GD32F1xx_standard_peripheral/Include/gd32f10x_mcudbg.h b/bsp/gd32103c-eval/Libraries/GD32F1xx_standard_peripheral/Include/gd32f10x_mcudbg.h deleted file mode 100644 index f6f1f0902f..0000000000 --- a/bsp/gd32103c-eval/Libraries/GD32F1xx_standard_peripheral/Include/gd32f10x_mcudbg.h +++ /dev/null @@ -1,90 +0,0 @@ -/** - ****************************************************************************** - * @brief MCUDBG header file of the firmware library. - ****************************************************************************** - */ - -/* Define to prevent recursive inclusion -------------------------------------*/ -#ifndef __GD32F10X_MCUDBG_H -#define __GD32F10X_MCUDBG_H - -#ifdef __cplusplus -extern "C" { -#endif - -/* Includes ------------------------------------------------------------------*/ -#include "gd32f10x.h" - -/** @addtogroup GD32F10x_Firmware - * @{ - */ - -/** @addtogroup MCUDBG - * @{ - */ - -/* Exported types ------------------------------------------------------------*/ - - - -/* Exported constants --------------------------------------------------------*/ - -/** @defgroup MCUDBG_Exported_Constants - * @{ - */ -#define MCUDBG_SLEEP_HOLD ((uint32_t)0x00000001) -#define MCUDBG_DEEPSLEEP_HOLD ((uint32_t)0x00000002) -#define MCUDBG_STDBY_HOLD ((uint32_t)0x00000004) -#define MCUDBG_IWDG_HOLD ((uint32_t)0x00000100) -#define MCUDBG_WWDG_HOLD ((uint32_t)0x00000200) -#define MCUDBG_TIMER1_HOLD ((uint32_t)0x00000400) -#define MCUDBG_TIMER2_HOLD ((uint32_t)0x00000800) -#define MCUDBG_TIMER3_HOLD ((uint32_t)0x00001000) -#define MCUDBG_TIMER4_HOLD ((uint32_t)0x00002000) -#define MCUDBG_CAN1_HOLD ((uint32_t)0x00004000) -#define MCUDBG_I2C1_HOLD ((uint32_t)0x00008000) -#define MCUDBG_I2C2_HOLD ((uint32_t)0x00010000) -#define MCUDBG_TIMER5_HOLD ((uint32_t)0x00020000) -#define MCUDBG_TIMER6_HOLD ((uint32_t)0x00040000) -#define MCUDBG_TIMER7_HOLD ((uint32_t)0x00080000) -#define MCUDBG_TIMER8_HOLD ((uint32_t)0x00100000) -#define MCUDBG_CAN2_HOLD ((uint32_t)0x00200000) -#define MCUDBG_TIMER12_HOLD ((uint32_t)0x02000000) -#define MCUDBG_TIMER13_HOLD ((uint32_t)0x04000000) -#define MCUDBG_TIMER14_HOLD ((uint32_t)0x08000000) -#define MCUDBG_TIMER9_HOLD ((uint32_t)0x10000000) -#define MCUDBG_TIMER10_HOLD ((uint32_t)0x20000000) -#define MCUDBG_TIMER11_HOLD ((uint32_t)0x40000000) - -/** - * @} - */ - -/* Exported macro ------------------------------------------------------------*/ -/* Exported functions ------------------------------------------------------- */ - -/** @defgroup MCUDBG_Exported_Functions - * @{ - */ - -uint32_t MCUDBG_GetREVID(void); -uint32_t MCUDBG_GetDEVID(void); -void MCUDBG_PeriphConfig(uint32_t MCUDBG_Periph, TypeState NewValue); - -#ifdef __cplusplus -} -#endif - -#endif /* __GD32F10X_MCUDBG_H */ -/** - * @} - */ - -/** - * @} - */ - -/** - * @} - */ - diff --git a/bsp/gd32103c-eval/Libraries/GD32F1xx_standard_peripheral/Include/gd32f10x_misc.h b/bsp/gd32103c-eval/Libraries/GD32F1xx_standard_peripheral/Include/gd32f10x_misc.h deleted file mode 100644 index 8ca8a6315f..0000000000 --- a/bsp/gd32103c-eval/Libraries/GD32F1xx_standard_peripheral/Include/gd32f10x_misc.h +++ /dev/null @@ -1,119 +0,0 @@ -/** - ****************************************************************************** - * @brief MISC header file of the firmware library. - ****************************************************************************** - */ - -/* Define to prevent recursive inclusion -------------------------------------*/ -#ifndef __GD32F10X_MISC_H -#define __GD32F10X_MISC_H - -#ifdef __cplusplus -extern "C" { -#endif - -/* Includes ------------------------------------------------------------------*/ -#include "gd32f10x.h" - -/** @addtogroup GD32F10x_Firmware - * @{ - */ - -/** @addtogroup MISC - * @{ - */ - -/** @defgroup MISC_Exported_Types - * @{ - */ - -/** - * @brief MISC Initial Parameters - */ -typedef struct { - uint8_t NVIC_IRQ; /*!< The IRQ type,detailed in @ref IRQn_Type */ - - uint8_t NVIC_IRQPreemptPriority; /*!< The pre-emption priority of NVIC_IRQ, detailed in @ref NVIC_Priority_Table */ - - uint8_t NVIC_IRQSubPriority; /*!< The SubPriority of NVIC_IRQ, detailed in @ref NVIC_Priority_Table */ - - TypeState NVIC_IRQEnable; /*!< Enable or disable the IRQ,this parameter can be ENABLE or DISABLE */ - -} NVIC_InitPara; - -/** - * @} - */ - -/** @defgroup MISC_Exported_Constants - * @{ - */ - -/** @defgroup MISC_System_Low_Power - * @{ - */ -#define NVIC_VECTTAB_RAM ((uint32_t)0x20000000) -#define NVIC_VECTTAB_FLASH ((uint32_t)0x08000000) -#define NVIC_LOWPOWER_SEVONPEND ((uint8_t)0x10) -#define NVIC_LOWPOWER_SLEEPDEEP ((uint8_t)0x04) -#define NVIC_LOWPOWER_SLEEPONEXIT ((uint8_t)0x02) - -/** - * @} - */ - -/** @defgroup MISC_Preemption_Priority_Group - * @{ - */ - -/* Preemption Priority Group -------------------------------------------------*/ -#define NVIC_PRIGROUP_0 ((uint32_t)0x700) /*!< 0 bits for pre-emption priority 4 bits for subpriority */ -#define NVIC_PRIGROUP_1 ((uint32_t)0x600) /*!< 1 bits for pre-emption priority 3 bits for subpriority */ -#define NVIC_PRIGROUP_2 ((uint32_t)0x500) /*!< 2 bits for pre-emption priority 2 bits for subpriority */ -#define NVIC_PRIGROUP_3 ((uint32_t)0x400) /*!< 3 bits for pre-emption priority 1 bits for subpriority */ -#define NVIC_PRIGROUP_4 ((uint32_t)0x300) /*!< 4 bits for pre-emption priority 0 bits for subpriority */ - -/** - * @} - */ - -/** @defgroup MISC_SysTick_clock_source - * @{ - */ -#define SYSTICK_CKSOURCE_HCLK_DIV8 ((uint32_t)0xFFFFFFFB) -#define SYSTICK_CKSOURCE_HCLK ((uint32_t)0x00000004) - -/** - * @} - */ - -/** - * @} - */ - -/** @defgroup MISC_Exported_Functions - * @{ - */ -void NVIC_Init(NVIC_InitPara *NVIC_InitStruct); -void NVIC_SystemLowPowerConfig(uint8_t LowPowerMode, TypeState NewValue); -void SysTick_CKSource_Enable(uint32_t SysTick_CKSource); -void NVIC_VectTableSet(uint32_t NVIC_VectTab, uint32_t Offset); -void NVIC_PRIGroup_Enable(uint32_t NVIC_PRIGroup); - -#ifdef __cplusplus -} -#endif - -#endif /*__GD32F10X_MISC_H */ -/** - * @} - */ - -/** - * @} - */ - -/** - * @} - */ - diff --git a/bsp/gd32103c-eval/Libraries/GD32F1xx_standard_peripheral/Include/gd32f10x_pwr.h b/bsp/gd32103c-eval/Libraries/GD32F1xx_standard_peripheral/Include/gd32f10x_pwr.h deleted file mode 100644 index 36cd112d18..0000000000 --- a/bsp/gd32103c-eval/Libraries/GD32F1xx_standard_peripheral/Include/gd32f10x_pwr.h +++ /dev/null @@ -1,131 +0,0 @@ -/** - ****************************************************************************** - * @brief PWR header file of the firmware library. - ****************************************************************************** - */ - -/* Define to prevent recursive inclusion -------------------------------------*/ -#ifndef __GD32F10X_PWR_H -#define __GD32F10X_PWR_H - -#ifdef __cplusplus -extern "C" { -#endif - -/* Includes ------------------------------------------------------------------*/ -#include "gd32f10x.h" - -/** @addtogroup GD32F10x_Firmware - * @{ - */ - -/** @addtogroup PWR - * @{ - */ - -/** @defgroup PWR_Exported_Constants - * @{ - */ - -/** @defgroup PWR_Low_Voltage_Detector_Threshold - * @{ - */ -#define PWR_LVDT_0 PWR_CTLR_LVDT_2V2 -#define PWR_LVDT_1 PWR_CTLR_LVDT_2V3 -#define PWR_LVDT_2 PWR_CTLR_LVDT_2V4 -#define PWR_LVDT_3 PWR_CTLR_LVDT_2V5 -#define PWR_LVDT_4 PWR_CTLR_LVDT_2V6 -#define PWR_LVDT_5 PWR_CTLR_LVDT_2V7 -#define PWR_LVDT_6 PWR_CTLR_LVDT_2V8 -#define PWR_LVDT_7 PWR_CTLR_LVDT_2V9 - -/** - * @} - */ - -/** @defgroup PWR_LDO_state_in_Deep-sleep_mode - * @{ - */ -#define PWR_LDO_ON ((uint32_t)0x00000000) -#define PWR_LDO_LOWPOWER PWR_CTLR_LDOLP - -/** - * @} - */ - -/** @defgroup PWR_Sleep_mode_entry - * @{ - */ -#define PWR_SLEEPENTRY_WFI ((uint8_t)0x01) -#define PWR_SLEEPENTRY_WFE ((uint8_t)0x02) - -/** - * @} - */ - -/** @defgroup PWR_Deep-sleep_mode_entry - * @{ - */ -#define PWR_DEEPSLEEPENTRY_WFI ((uint8_t)0x01) -#define PWR_DEEPSLEEPENTRY_WFE ((uint8_t)0x02) - -/** - * @} - */ - -/** @defgroup PWR_Standby_mode_entry - * @{ - */ -#define PWR_STDBYENTRY_WFI ((uint8_t)0x01) -#define PWR_STDBYENTRY_WFE ((uint8_t)0x02) - -/** - * @} - */ - -/** @defgroup PWR_Flag - * @{ - */ -#define PWR_FLAG_WKUP PWR_STR_WUF -#define PWR_FLAG_STB PWR_STR_SBF -#define PWR_FLAG_LVDF PWR_STR_LVDF - -/** - * @} - */ - -/** - * @} - */ - -/** @defgroup PWR_Exported_Functions - * @{ - */ -void PWR_DeInit(void); -void PWR_BackupAccess_Enable(TypeState NewValue); -void PWR_LVDConfig(uint32_t PWR_LVDT, TypeState NewValue); -void PWR_WKUP_Pin_Enable(TypeState NewValue); -void PWR_SLEEPMode_Entry(uint8_t PWR_SLEEPENTRY); -void PWR_DEEPSLEEPMode_Entry(uint32_t PWR_LDO, uint8_t PWR_DEEPSLEEPENTRY); -void PWR_STDBYMode_Entry(uint8_t PWR_STDBYENTRY); -TypeState PWR_GetBitState(uint32_t PWR_FLAG); -void PWR_ClearBitState(uint32_t PWR_FLAG); - -#ifdef __cplusplus -} -#endif - -#endif /* __GD32F10X_PWR_H */ - -/** - * @} - */ - -/** - * @} - */ - -/** - * @} - */ - diff --git a/bsp/gd32103c-eval/Libraries/GD32F1xx_standard_peripheral/Include/gd32f10x_rcc.h b/bsp/gd32103c-eval/Libraries/GD32F1xx_standard_peripheral/Include/gd32f10x_rcc.h deleted file mode 100644 index 9772751542..0000000000 --- a/bsp/gd32103c-eval/Libraries/GD32F1xx_standard_peripheral/Include/gd32f10x_rcc.h +++ /dev/null @@ -1,690 +0,0 @@ -/** - ****************************************************************************** - * @brief RCC header file of the firmware library. - ****************************************************************************** - */ - -/* Define to prevent recursive inclusion -------------------------------------*/ -#ifndef __GD32F10X_RCC_H -#define __GD32F10X_RCC_H - -#ifdef __cplusplus -extern "C" { -#endif - -/* Includes ------------------------------------------------------------------*/ -#include "gd32f10x.h" - -/** @addtogroup GD32F10x_Firmware - * @{ - */ - -/** @addtogroup RCC - * @{ - */ - -/** @defgroup RCC_Exported_Types - * @{ - */ - -/** - * @brief RCC Initial Parameters - */ - -typedef struct { - uint32_t CK_SYS_Frequency; /*!< The frequency of the CK_SYS. */ - uint32_t AHB_Frequency; /*!< The frequency of the AHB. */ - uint32_t APB1_Frequency; /*!< The frequency of the APB1. */ - uint32_t APB2_Frequency; /*!< The frequency of the APB2. */ - uint32_t ADCCLK_Frequency; /*!< The frequency of the ADCCLK. */ -} RCC_ClocksPara; - -/** - * @} - */ - -/** @defgroup RCC_Exported_Constants - * @{ - */ - -/** @defgroup RCC_HSE_configuration - * @{ - */ - -#define RCC_HSE_OFF ((uint32_t)0x00000000) -#define RCC_HSE_ON RCC_GCCR_HSEEN -#define RCC_HSE_BYPASS RCC_GCCR_HSEEN | RCC_GCCR_HSEBPS - -/** - * @} - */ - -/** @defgroup RCC_PLL_input_clock_source - * @{ - */ - -#define RCC_PLLSOURCE_HSI_DIV2 RCC_GCFGR_PLLSEL_HSI_DIV2 - -#ifdef GD32F10X_CL -#define RCC_PLLSOURCE_PREDIV1 RCC_GCFGR_PLLSEL_PREDIV1 - -#else -#define RCC_PLLSOURCE_HSE_DIV1 ((uint32_t)0x00010000) -#define RCC_PLLSOURCE_HSE_DIV2 ((uint32_t)0x00030000) -#endif /* GD32F10X_CL */ -/** - * @} - */ - -/** @defgroup RCC_PLL_Multiplication_factor - * @{ - */ - - -#define RCC_PLLMUL_2 RCC_GCFGR_PLLMF2 -#define RCC_PLLMUL_3 RCC_GCFGR_PLLMF3 -#define RCC_PLLMUL_4 RCC_GCFGR_PLLMF4 -#define RCC_PLLMUL_5 RCC_GCFGR_PLLMF5 -#define RCC_PLLMUL_6 RCC_GCFGR_PLLMF6 -#define RCC_PLLMUL_7 RCC_GCFGR_PLLMF7 -#define RCC_PLLMUL_8 RCC_GCFGR_PLLMF8 -#define RCC_PLLMUL_9 RCC_GCFGR_PLLMF9 -#define RCC_PLLMUL_10 RCC_GCFGR_PLLMF10 -#define RCC_PLLMUL_11 RCC_GCFGR_PLLMF11 -#define RCC_PLLMUL_12 RCC_GCFGR_PLLMF12 -#define RCC_PLLMUL_13 RCC_GCFGR_PLLMF13 -#define RCC_PLLMUL_14 RCC_GCFGR_PLLMF14 - -#define RCC_PLLMUL_16 RCC_GCFGR_PLLMF16 -#define RCC_PLLMUL_17 RCC_GCFGR_PLLMF17 -#define RCC_PLLMUL_18 RCC_GCFGR_PLLMF18 -#define RCC_PLLMUL_19 RCC_GCFGR_PLLMF19 -#define RCC_PLLMUL_20 RCC_GCFGR_PLLMF20 -#define RCC_PLLMUL_21 RCC_GCFGR_PLLMF21 -#define RCC_PLLMUL_22 RCC_GCFGR_PLLMF22 -#define RCC_PLLMUL_23 RCC_GCFGR_PLLMF23 -#define RCC_PLLMUL_24 RCC_GCFGR_PLLMF24 -#define RCC_PLLMUL_25 RCC_GCFGR_PLLMF25 -#define RCC_PLLMUL_26 RCC_GCFGR_PLLMF26 -#define RCC_PLLMUL_27 RCC_GCFGR_PLLMF27 -#define RCC_PLLMUL_28 RCC_GCFGR_PLLMF28 -#define RCC_PLLMUL_29 RCC_GCFGR_PLLMF29 -#define RCC_PLLMUL_30 RCC_GCFGR_PLLMF30 -#define RCC_PLLMUL_31 RCC_GCFGR_PLLMF31 -#define RCC_PLLMUL_32 RCC_GCFGR_PLLMF32 - -#ifdef GD32F10X_CL -#define RCC_PLLMUL_6_5 RCC_GCFGR_PLLMF6_5 -#else -#define RCC_PLLMUL_15 RCC_GCFGR_PLLMF15 - -#endif /* GD32F10X_CL */ -/** - * @} - */ - -#ifdef GD32F10X_CL -/** @defgroup RCC_PREDIV1_division_factor - * @{ - */ - -#define RCC_PREDIV1_DIV1 RCC_GCFGR2_PREDV1_DIV1 -#define RCC_PREDIV1_DIV2 RCC_GCFGR2_PREDV1_DIV2 -#define RCC_PREDIV1_DIV3 RCC_GCFGR2_PREDV1_DIV3 -#define RCC_PREDIV1_DIV4 RCC_GCFGR2_PREDV1_DIV4 -#define RCC_PREDIV1_DIV5 RCC_GCFGR2_PREDV1_DIV5 -#define RCC_PREDIV1_DIV6 RCC_GCFGR2_PREDV1_DIV6 -#define RCC_PREDIV1_DIV7 RCC_GCFGR2_PREDV1_DIV7 -#define RCC_PREDIV1_DIV8 RCC_GCFGR2_PREDV1_DIV8 -#define RCC_PREDIV1_DIV9 RCC_GCFGR2_PREDV1_DIV9 -#define RCC_PREDIV1_DIV10 RCC_GCFGR2_PREDV1_DIV10 -#define RCC_PREDIV1_DIV11 RCC_GCFGR2_PREDV1_DIV11 -#define RCC_PREDIV1_DIV12 RCC_GCFGR2_PREDV1_DIV12 -#define RCC_PREDIV1_DIV13 RCC_GCFGR2_PREDV1_DIV13 -#define RCC_PREDIV1_DIV14 RCC_GCFGR2_PREDV1_DIV14 -#define RCC_PREDIV1_DIV15 RCC_GCFGR2_PREDV1_DIV15 -#define RCC_PREDIV1_DIV16 RCC_GCFGR2_PREDV1_DIV16 - -/** - * @} - */ - - -/** @defgroup RCC_PREDIV1_clock_source - * @{ - */ - -#define RCC_PREDIV1_SOURCE_HSE RCC_GCFGR2_PREDV1SEL_HSE -#define RCC_PREDIV1_SOURCE_PLL2 RCC_GCFGR2_PREDV1SEL_PLL2 - -/** - * @} - */ - - -/** @defgroup RCC_PREDIV2_division_factor - * @{ - */ -#define RCC_PREDIV2_DIV1 RCC_GCFGR2_PREDV2_DIV1 -#define RCC_PREDIV2_DIV2 RCC_GCFGR2_PREDV2_DIV2 -#define RCC_PREDIV2_DIV3 RCC_GCFGR2_PREDV2_DIV3 -#define RCC_PREDIV2_DIV4 RCC_GCFGR2_PREDV2_DIV4 -#define RCC_PREDIV2_DIV5 RCC_GCFGR2_PREDV2_DIV5 -#define RCC_PREDIV2_DIV6 RCC_GCFGR2_PREDV2_DIV6 -#define RCC_PREDIV2_DIV7 RCC_GCFGR2_PREDV2_DIV7 -#define RCC_PREDIV2_DIV8 RCC_GCFGR2_PREDV2_DIV8 -#define RCC_PREDIV2_DIV9 RCC_GCFGR2_PREDV2_DIV9 -#define RCC_PREDIV2_DIV10 RCC_GCFGR2_PREDV2_DIV10 -#define RCC_PREDIV2_DIV11 RCC_GCFGR2_PREDV2_DIV11 -#define RCC_PREDIV2_DIV12 RCC_GCFGR2_PREDV2_DIV12 -#define RCC_PREDIV2_DIV13 RCC_GCFGR2_PREDV2_DIV13 -#define RCC_PREDIV2_DIV14 RCC_GCFGR2_PREDV2_DIV14 -#define RCC_PREDIV2_DIV15 RCC_GCFGR2_PREDV2_DIV15 -#define RCC_PREDIV2_DIV16 RCC_GCFGR2_PREDV2_DIV16 - -/** - * @} - */ - - -/** @defgroup RCC_PLL2_multiplication_factor - * @{ - */ -#define RCC_PLL2MUL_8 RCC_GCFGR2_PLL2MF8 -#define RCC_PLL2MUL_9 RCC_GCFGR2_PLL2MF9 -#define RCC_PLL2MUL_10 RCC_GCFGR2_PLL2MF10 -#define RCC_PLL2MUL_11 RCC_GCFGR2_PLL2MF11 -#define RCC_PLL2MUL_12 RCC_GCFGR2_PLL2MF12 -#define RCC_PLL2MUL_13 RCC_GCFGR2_PLL2MF13 -#define RCC_PLL2MUL_14 RCC_GCFGR2_PLL2MF14 -#define RCC_PLL2MUL_16 RCC_GCFGR2_PLL2MF16 -#define RCC_PLL2MUL_20 RCC_GCFGR2_PLL2MF20 - -/** - * @} - */ - - -/** @defgroup RCC_PLL3_multiplication_factor - * @{ - */ -#define RCC_PLL3MUL_8 RCC_GCFGR2_PLL3MF8 -#define RCC_PLL3MUL_9 RCC_GCFGR2_PLL3MF9 -#define RCC_PLL3MUL_10 RCC_GCFGR2_PLL3MF10 -#define RCC_PLL3MUL_11 RCC_GCFGR2_PLL3MF11 -#define RCC_PLL3MUL_12 RCC_GCFGR2_PLL3MF12 -#define RCC_PLL3MUL_13 RCC_GCFGR2_PLL3MF13 -#define RCC_PLL3MUL_14 RCC_GCFGR2_PLL3MF14 -#define RCC_PLL3MUL_16 RCC_GCFGR2_PLL3MF16 -#define RCC_PLL3MUL_20 RCC_GCFGR2_PLL3MF20 - -/** - * @} - */ -#endif /* GD32F10X_CL */ - - -/** @defgroup RCC_System_Clock_Source - * @{ - */ -#define RCC_SYSCLKSOURCE_HSI RCC_GCFGR_SCS_HSI -#define RCC_SYSCLKSOURCE_HSE RCC_GCFGR_SCS_HSE -#define RCC_SYSCLKSOURCE_PLLCLK RCC_GCFGR_SCS_PLL - -/** - * @} - */ - -/** @defgroup RCC_AHB_Clock_Source - * @{ - */ -#define RCC_SYSCLK_DIV1 RCC_GCFGR_AHBPS_DIV1 -#define RCC_SYSCLK_DIV2 RCC_GCFGR_AHBPS_DIV2 -#define RCC_SYSCLK_DIV4 RCC_GCFGR_AHBPS_DIV4 -#define RCC_SYSCLK_DIV8 RCC_GCFGR_AHBPS_DIV8 -#define RCC_SYSCLK_DIV16 RCC_GCFGR_AHBPS_DIV16 -#define RCC_SYSCLK_DIV64 RCC_GCFGR_AHBPS_DIV64 -#define RCC_SYSCLK_DIV128 RCC_GCFGR_AHBPS_DIV128 -#define RCC_SYSCLK_DIV256 RCC_GCFGR_AHBPS_DIV256 -#define RCC_SYSCLK_DIV512 RCC_GCFGR_AHBPS_DIV512 - -/** - * @} - */ - -/** @defgroup RCC_APB_Clock_Source - * @{ - */ -#define RCC_APB1AHB_DIV1 RCC_GCFGR_APB1PS_DIV1 -#define RCC_APB1AHB_DIV2 RCC_GCFGR_APB1PS_DIV2 -#define RCC_APB1AHB_DIV4 RCC_GCFGR_APB1PS_DIV4 -#define RCC_APB1AHB_DIV8 RCC_GCFGR_APB1PS_DIV8 -#define RCC_APB1AHB_DIV16 RCC_GCFGR_APB1PS_DIV16 - -#define RCC_APB2AHB_DIV1 RCC_GCFGR_APB2PS_DIV1 -#define RCC_APB2AHB_DIV2 RCC_GCFGR_APB2PS_DIV2 -#define RCC_APB2AHB_DIV4 RCC_GCFGR_APB2PS_DIV4 -#define RCC_APB2AHB_DIV8 RCC_GCFGR_APB2PS_DIV8 -#define RCC_APB2AHB_DIV16 RCC_GCFGR_APB2PS_DIV16 -/** - * @} - */ - -/** @defgroup RCC_ADC_clock_source - * @{ - */ -#define RCC_ADCCLK_APB2_DIV2 RCC_GCFGR_ADCPS_DIV2 -#define RCC_ADCCLK_APB2_DIV4 RCC_GCFGR_ADCPS_DIV4 -#define RCC_ADCCLK_APB2_DIV6 RCC_GCFGR_ADCPS_DIV6 -#define RCC_ADCCLK_APB2_DIV8 RCC_GCFGR_ADCPS_DIV8 -#define RCC_ADCCLK_APB2_DIV12 RCC_GCFGR_ADCPS_DIV12 -#define RCC_ADCCLK_APB2_DIV16 RCC_GCFGR_ADCPS_DIV16 - -/** - * @} - */ - -#ifdef GD32F10X_CL -/** @defgroup RCC_USB_OTG_clock_source - * @{ - */ -#define RCC_OTGCLK_PLL_DIV1 RCC_GCFGR_OTGFSPS_Div1 -#define RCC_OTGCLK_PLL_DIV1_5 RCC_GCFGR_OTGFSPS_Div1_5 -#define RCC_OTGCLK_PLL_DIV2 RCC_GCFGR_OTGFSPS_Div2 -#define RCC_OTGCLK_PLL_DIV2_5 RCC_GCFGR_OTGFSPS_Div2_5 - -/** - * @} - */ - -#else -/** @defgroup RCC_USB_clock_source - * @{ - */ -#define RCC_USBCLK_PLL_DIV1 RCC_GCFGR_USBPS_Div1 -#define RCC_USBCLK_PLL_DIV1_5 RCC_GCFGR_USBPS_Div1_5 -#define RCC_USBCLK_PLL_DIV2 RCC_GCFGR_USBPS_Div2 -#define RCC_USBCLK_PLL_DIV2_5 RCC_GCFGR_USBPS_Div2_5 - -/** - * @} - */ -#endif /* GD32F10X_CL */ - - - -/** @defgroup RCC_CK_OUT_Clock_Source - * @{ - */ -#ifdef GD32F10X_CL -#define RCC_CKOUTSRC_NOCLOCK RCC_GCFGR_CKOUTSEL_NoClock -#define RCC_CKOUTSRC_SYSCLK RCC_GCFGR_CKOUTSEL_SYSCLK -#define RCC_CKOUTSRC_HSI RCC_GCFGR_CKOUTSEL_HSI -#define RCC_CKOUTSRC_HSE RCC_GCFGR_CKOUTSEL_HSE -#define RCC_CKOUTSRC_PLLCLK_DIV2 RCC_GCFGR_CKOUTSEL_PLL_DIV2 -#define RCC_CKOUTSRC_PLL2CLK RCC_GCFGR_CKOUTSEL_PLL2 -#define RCC_CKOUTSRC_PLL3CLK RCC_GCFGR_CKOUTSEL_PLL3 -#define RCC_CKOUTSRC_PLL3CLK_DIV2 RCC_GCFGR_CKOUTSEL_PLL3_DIV2 -#define RCC_CKOUTSRC_EXT1 RCC_GCFGR_CKOUTSEL_EXT1 - -#else -#define RCC_CKOUTSRC_NOCLOCK RCC_GCFGR_CKOUTSEL_NoClock -#define RCC_CKOUTSRC_SYSCLK RCC_GCFGR_CKOUTSEL_SYSCLK -#define RCC_CKOUTSRC_HSI RCC_GCFGR_CKOUTSEL_HSI -#define RCC_CKOUTSRC_HSE RCC_GCFGR_CKOUTSEL_HSE -#define RCC_CKOUTSRC_PLLCLK_DIV2 RCC_GCFGR_CKOUTSEL_PLL_DIV2 - -#endif /* GD32F10X_CL */ - -/** - * @} - */ - -/** @defgroup RCC_Interrupt_Source - * @{ - */ -#define RCC_INT_LSISTB ((uint8_t)0x01) -#define RCC_INT_LSESTB ((uint8_t)0x02) -#define RCC_INT_HSISTB ((uint8_t)0x04) -#define RCC_INT_HSESTB ((uint8_t)0x08) -#define RCC_INT_PLLSTB ((uint8_t)0x10) -#define RCC_INT_CKM ((uint8_t)0x80) - -#ifdef GD32F10X_CL -#define RCC_INT_PLL2STB ((uint8_t)0x20) -#define RCC_INT_PLL3STB ((uint8_t)0x40) -#endif /* GD32F10X_CL */ - -/** - * @} - */ - -#ifdef GD32F10X_CL -/** @defgroup RCC_I2S2_clock_source - * @{ - */ -#define RCC_I2S2CLK_SYSCLK RCC_GCFGR2_I2S2SEL_CK_SYS -#define RCC_I2S2CLK_PLL3 RCC_GCFGR2_I2S2SEL_PLL3 - -/** - * @} - */ - -/** @defgroup RCC_I2S3_clock_source - * @{ - */ -#define RCC_I2S3CLK_SYSCLK RCC_GCFGR2_I2S3SEL_CK_SYS -#define RCC_I2S3CLK_PLL3 RCC_GCFGR2_I2S3SEL_PLL3 - -/** - * @} - */ -#endif /* GD32F10X_CL */ - - - -/** @defgroup RCC_LSE_configuration - * @{ - */ -#define RCC_LSE_OFF ((uint32_t)0x00000000) -#define RCC_LSE_EN RCC_BDCR_LSEEN -#define RCC_LSE_BYPASS ((uint32_t)(RCC_BDCR_LSEEN | RCC_BDCR_LSEBPS)) - -/** - * @} - */ - -/** @defgroup RCC_RTC_clock_source - * @{ - */ -#define RCC_RTCCLKSOURCE_LSE RCC_BDCR_RTCSEL_LSE -#define RCC_RTCCLKSOURCE_LSI RCC_BDCR_RTCSEL_LSI -#define RCC_RTCCLKSOURCE_HSE_DIV128 RCC_BDCR_RTCSEL_HSE128 - -/** - * @} - */ - -/** @defgroup RCC_AHB_peripheral - * @{ - */ -#define RCC_AHBPERIPH_DMA1 RCC_AHBCCR_DMA1EN -#define RCC_AHBPERIPH_DMA2 RCC_AHBCCR_DMA2EN -#define RCC_AHBPERIPH_SRAM RCC_AHBCCR_SRAMEN -#define RCC_AHBPERIPH_FMC RCC_AHBCCR_FMCEN -#define RCC_AHBPERIPH_CRC RCC_AHBCCR_CRCEN -#define RCC_AHBPERIPH_EXMC RCC_AHBCCR_EXMCEN - -#ifdef GD32F10X_CL -#define RCC_AHBPERIPH_OTG_FS RCC_AHBCCR_OTGFSEN -#define RCC_AHBPERIPH_ETH_MAC RCC_AHBCCR_ETHMACEN -#define RCC_AHBPERIPH_ETH_MAC_RX RCC_AHBCCR_ETHMACRXEN -#define RCC_AHBPERIPH_ETH_MAC_TX RCC_AHBCCR_ETHMACTXEN - -#else -#define RCC_AHBPERIPH_SDIO RCC_AHBCCR_SDIOEN -#endif/* GD32F10X_CL */ - -/** - * @} - */ - -/** @defgroup RCC_AHB_Peripherals_RST - * @{ - */ -#ifdef GD32F10X_CL -#define RCC_AHBPERIPH_OTGFSRST RCC_AHBRCR_OTGFSRST -#define RCC_AHBPERIPH_ETHMACRST RCC_AHBRCR_ETHMACRST - -#endif/* GD32F10X_CL */ - -/** - * @} - */ - -/** @defgroup RCC_APB2_peripheral - * @{ - */ -#define RCC_APB2PERIPH_AF RCC_APB2CCR_AFEN -#define RCC_APB2PERIPH_GPIOA RCC_APB2CCR_PAEN -#define RCC_APB2PERIPH_GPIOB RCC_APB2CCR_PBEN -#define RCC_APB2PERIPH_GPIOC RCC_APB2CCR_PCEN -#define RCC_APB2PERIPH_GPIOD RCC_APB2CCR_PDEN -#define RCC_APB2PERIPH_GPIOE RCC_APB2CCR_PEEN -#define RCC_APB2PERIPH_GPIOF RCC_APB2CCR_PFEN -#define RCC_APB2PERIPH_GPIOG RCC_APB2CCR_PGEN -#define RCC_APB2PERIPH_ADC0 RCC_APB2CCR_ADC0EN -#define RCC_APB2PERIPH_ADC1 RCC_APB2CCR_ADC1EN -#define RCC_APB2PERIPH_TIMER0 RCC_APB2CCR_TIMER0EN -#define RCC_APB2PERIPH_SPI1 RCC_APB2CCR_SPI1EN -#define RCC_APB2PERIPH_TIMER7 RCC_APB2CCR_TIMER7EN -#define RCC_APB2PERIPH_USART1 RCC_APB2CCR_USART1EN -#define RCC_APB2PERIPH_ADC2 RCC_APB2CCR_ADC2EN -#define RCC_APB2PERIPH_TIMER8 RCC_APB2CCR_TIMER8EN -#define RCC_APB2PERIPH_TIMER9 RCC_APB2CCR_TIMER9EN -#define RCC_APB2PERIPH_TIMER10 RCC_APB2CCR_TIMER10EN - -/** - * @} - */ - -/** @defgroup RCC_APB2_Peripherals_RST - * @{ - */ -#define RCC_APB2PERIPH_AFRST RCC_APB2RCR_AFRST -#define RCC_APB2PERIPH_GPIOARST RCC_APB2RCR_PARST -#define RCC_APB2PERIPH_GPIOBRST RCC_APB2RCR_PBRST -#define RCC_APB2PERIPH_GPIOCRST RCC_APB2RCR_PCRST -#define RCC_APB2PERIPH_GPIODRST RCC_APB2RCR_PDRST -#define RCC_APB2PERIPH_GPIOERST RCC_APB2RCR_PERST -#define RCC_APB2PERIPH_GPIOFRST RCC_APB2RCR_PFRST -#define RCC_APB2PERIPH_GPIOGRST RCC_APB2RCR_PGRST -#define RCC_APB2PERIPH_ADC0RST RCC_APB2RCR_ADC0RST -#define RCC_APB2PERIPH_ADC1RST RCC_APB2RCR_ADC1RST -#define RCC_APB2PERIPH_TIMER0RST RCC_APB2RCR_TIMER0RST -#define RCC_APB2PERIPH_SPI1RST RCC_APB2RCR_SPI1RST -#define RCC_APB2PERIPH_TIMER7RST RCC_APB2RCR_TIMER7RST -#define RCC_APB2PERIPH_USART0RST RCC_APB2RCR_USART0RST -#define RCC_APB2PERIPH_ADC2RST RCC_APB2RCR_ADC2RST -#define RCC_APB2PERIPH_TIMER8RST RCC_APB2RCR_TIMER8RST -#define RCC_APB2PERIPH_TIMER9RST RCC_APB2RCR_TIMER9RST -#define RCC_APB2PERIPH_TIMER10RST RCC_APB2RCR_TIMER10RST - -/** - * @} - */ - -/** @defgroup RCC_APB1_peripheral - * @{ - */ -#define RCC_APB1PERIPH_TIMER1 RCC_APB1CCR_TIMER1EN -#define RCC_APB1PERIPH_TIMER2 RCC_APB1CCR_TIMER2EN -#define RCC_APB1PERIPH_TIMER3 RCC_APB1CCR_TIMER3EN -#define RCC_APB1PERIPH_TIMER4 RCC_APB1CCR_TIMER4EN -#define RCC_APB1PERIPH_TIMER5 RCC_APB1CCR_TIMER5EN -#define RCC_APB1PERIPH_TIMER6 RCC_APB1CCR_TIMER6EN -#define RCC_APB1PERIPH_TIMER11 RCC_APB1CCR_TIMER11EN -#define RCC_APB1PERIPH_TIMER12 RCC_APB1CCR_TIMER12EN -#define RCC_APB1PERIPH_TIMER13 RCC_APB1CCR_TIMER13EN -#define RCC_APB1PERIPH_WWDG RCC_APB1CCR_WWDGEN -#define RCC_APB1PERIPH_SPI2 RCC_APB1CCR_SPI2EN -#define RCC_APB1PERIPH_SPI3 RCC_APB1CCR_SPI3EN -#define RCC_APB1PERIPH_USART2 RCC_APB1CCR_USART2EN -#define RCC_APB1PERIPH_USART3 RCC_APB1CCR_USART3EN -#define RCC_APB1PERIPH_UART4 RCC_APB1CCR_UART4EN -#define RCC_APB1PERIPH_UART5 RCC_APB1CCR_UART5EN -#define RCC_APB1PERIPH_I2C1 RCC_APB1CCR_I2C1EN -#define RCC_APB1PERIPH_I2C2 RCC_APB1CCR_I2C2EN -#define RCC_APB1PERIPH_USB RCC_APB1CCR_USBEN -#define RCC_APB1PERIPH_CAN1 RCC_APB1CCR_CAN1EN -#define RCC_APB1PERIPH_CAN2 RCC_APB1CCR_CAN2EN -#define RCC_APB1PERIPH_BKP RCC_APB1CCR_BKPEN -#define RCC_APB1PERIPH_PWR RCC_APB1CCR_PWREN -#define RCC_APB1PERIPH_DAC RCC_APB1CCR_DACEN - -/** - * @} - */ - -/** @defgroup RCC_APB1_Peripherals_RST - * @{ - */ -#define RCC_APB1PERIPH_TIMER1RST RCC_APB1RCR_TIMER1RST -#define RCC_APB1PERIPH_TIMER2RST RCC_APB1RCR_TIMER2RST -#define RCC_APB1PERIPH_TIMER3RST RCC_APB1RCR_TIMER3RST -#define RCC_APB1PERIPH_TIMER4RST RCC_APB1RCR_TIMER4RST -#define RCC_APB1PERIPH_TIMER5RST RCC_APB1RCR_TIMER5RST -#define RCC_APB1PERIPH_TIMER6RST RCC_APB1RCR_TIMER6RST -#define RCC_APB1PERIPH_TIMER11RST RCC_APB1RCR_TIMER11RST -#define RCC_APB1PERIPH_TIMER12RST RCC_APB1RCR_TIMER12RST -#define RCC_APB1PERIPH_TIMER13RST RCC_APB1RCR_TIMER13RST -#define RCC_APB1PERIPH_WWDGRST RCC_APB1RCR_WWDGRST -#define RCC_APB1PERIPH_SPI2RST RCC_APB1RCR_SPI2RST -#define RCC_APB1PERIPH_SPI3RST RCC_APB1RCR_SPI3RST -#define RCC_APB1PERIPH_USART1RST RCC_APB1RCR_USART1RST -#define RCC_APB1PERIPH_USART2RST RCC_APB1RCR_USART2RST -#define RCC_APB1PERIPH_UART3RST RCC_APB1RCR_UART3RST -#define RCC_APB1PERIPH_UART4RST RCC_APB1RCR_UART4RST -#define RCC_APB1PERIPH_I2C1RST RCC_APB1RCR_I2C1RST -#define RCC_APB1PERIPH_I2C2RST RCC_APB1RCR_I2C2RST -#define RCC_APB1PERIPH_USBRST RCC_APB1RCR_USBRST -#define RCC_APB1PERIPH_CAN1RST RCC_APB1RCR_CAN1RST -#define RCC_APB1PERIPH_CAN2RST RCC_APB1RCR_CAN2RST -#define RCC_APB1PERIPH_BKPRST RCC_APB1RCR_BKPRST -#define RCC_APB1PERIPH_PWRRST RCC_APB1RCR_PWRRST -#define RCC_APB1PERIPH_DACRST RCC_APB1RCR_DACRST - -/** - * @} - */ - -/** @defgroup RCC_Flag - * @{ - */ -/* The flag to check is in GCCR register */ -#define RCC_FLAG_HSISTB ((uint8_t)0x21) -#define RCC_FLAG_HSESTB ((uint8_t)0x31) -#define RCC_FLAG_PLLSTB ((uint8_t)0x39) - -/* The flag to check is in BDCR register */ -#define RCC_FLAG_LSESTB ((uint8_t)0x41) - -/* The flag to check is in GCSR register */ -#define RCC_FLAG_LSISTB ((uint8_t)0x61) - -#define RCC_FLAG_EPRST ((uint8_t)0x7A) -#define RCC_FLAG_POPDRST ((uint8_t)0x7B) -#define RCC_FLAG_SWRRST ((uint8_t)0x7C) -#define RCC_FLAG_IWDGRST ((uint8_t)0x7D) -#define RCC_FLAG_WWDGRST ((uint8_t)0x7E) -#define RCC_FLAG_LPRRST ((uint8_t)0x7F) - -#ifdef GD32F10X_CL -/* The flag to check is in GCCR register */ -#define RCC_FLAG_PLL2STB ((uint8_t)0x3B) -#define RCC_FLAG_PLL3STB ((uint8_t)0x3D) - -#endif/* GD32F10X_CL */ -/** - * @} - */ - -/** - * @} - */ - -/** @defgroup RCC_Exported_Functions - * @{ - */ -/* Reset the RCC clock configuration to the default reset state */ - -void RCC_DeInit(void); - -/* Internal/external clocks, PLL, CKM and CK_OUT configuration functions */ - -void RCC_HSEConfig(uint32_t RCC_HSE); -TypeState RCC_WaitForHSEStartUp(void); -void RCC_AdjustHSICalibrationValue(uint8_t HSICalibrationValue); -void RCC_HSI_Enable(TypeState NewValue); -void RCC_PLLConfig(uint32_t RCC_PLLSelect, uint32_t RCC_PLLMF); -void RCC_PLL_Enable(TypeState NewValue); -void RCC_LSEConfig(uint32_t RCC_LSE); -void RCC_LSI_Enable(TypeState NewValue); -void RCC_HSEClockMonitor_Enable(TypeState NewValue); -void RCC_CKOUTSRCConfig(uint32_t RCC_CKOUTSRC); - -#ifdef GD32F10X_CL -void RCC_PREDV1Config(uint32_t RCC_PREDV1_Source, uint32_t RCC_PREDV1_Div); -void RCC_PREDV2Config(uint32_t RCC_PREDV2_Div); -void RCC_PLL2Config(uint32_t RCC_PLL2MF); -void RCC_PLL2_Enable(TypeState NewValue); -void RCC_PLL3Config(uint32_t RCC_PLL3MF); -void RCC_PLL3_Enable(TypeState NewValue); -#endif /* GD32F10X_CL */ - -/* System, AHB, APB1 and APB2 busses clocks configuration functions */ - -void RCC_CK_SYSConfig(uint32_t RCC_SYSCLKSource); -uint8_t RCC_GetCK_SYSSource(void); -void RCC_AHBConfig(uint32_t RCC_CK_SYSDiv); -void RCC_APB1Config(uint32_t RCC_APB1); -void RCC_APB2Config(uint32_t RCC_APB2); - -#ifndef GD32F10X_CL -void RCC_USBCLKConfig(uint32_t RCC_USBCLK); -#else -void RCC_OTGFSCLKConfig(uint32_t RCC_OTGFSCLK); -#endif /* GD32F10X_CL */ - -void RCC_ADCCLKConfig(uint32_t RCC_ADCCLK); - -#ifdef GD32F10X_CL -void RCC_I2S2CLKConfig(uint32_t RCC_I2S2CLK); -void RCC_I2S3CLKConfig(uint32_t RCC_I2S3CLK); -#endif /* GD32F10X_CL */ - -void RCC_RTCCLKConfig(uint32_t RCC_RTCCLKSource); -void RCC_GetClocksFreq(RCC_ClocksPara *RCC_Clocks); - -/* Peripheral clocks configuration functions */ - -void RCC_AHBPeriphClock_Enable(uint32_t RCC_AHBPeriph, TypeState NewValue); -void RCC_APB2PeriphClock_Enable(uint32_t RCC_APB2Periph, TypeState NewValue); -void RCC_APB1PeriphClock_Enable(uint32_t RCC_APB1Periph, TypeState NewValue); -void RCC_RTCCLK_Enable(TypeState NewValue); - -#ifdef GD32F10X_CL -void RCC_AHBPeriphReset_Enable(uint32_t RCC_AHBPeriphRST, TypeState NewValue); -#endif /* GD32F10X_CL */ - -void RCC_APB2PeriphReset_Enable(uint32_t RCC_APB2PeriphRST, TypeState NewValue); -void RCC_APB1PeriphReset_Enable(uint32_t RCC_APB1PeriphRST, TypeState NewValue); -void RCC_BackupReset_Enable(TypeState NewValue); - -/* Interrupts and flags management functions */ - -void RCC_INTConfig(uint8_t RCC_INT, TypeState NewValue); -TypeState RCC_GetIntBitState(uint8_t RCC_INT); -void RCC_ClearIntBitState(uint8_t RCC_INT); -TypeState RCC_GetBitState(uint8_t RCC_FLAG); -void RCC_ClearBitState(void); - -void RCC_KERNELVOLConfig(uint32_t RCC_KERNEL_VOL); - -#ifdef __cplusplus -} -#endif - -#endif /* __GD32F10x_RCC_H */ -/** - * @} - */ - -/** - * @} - */ - -/** - * @} - */ - diff --git a/bsp/gd32103c-eval/Libraries/GD32F1xx_standard_peripheral/Include/gd32f10x_rcu.h b/bsp/gd32103c-eval/Libraries/GD32F1xx_standard_peripheral/Include/gd32f10x_rcu.h deleted file mode 100644 index d63ce98930..0000000000 --- a/bsp/gd32103c-eval/Libraries/GD32F1xx_standard_peripheral/Include/gd32f10x_rcu.h +++ /dev/null @@ -1,1019 +0,0 @@ -/*! - \file gd32f10x_rcu.h - \brief definitions for the RCU -*/ - -/* - Copyright (C) 2017 GigaDevice - - 2017-02-10, V1.0.1, firmware for GD32F30x - 2021-01-02, firmware for GD32F10x -*/ - -#ifndef GD32F10X_RCU_H -#define GD32F10X_RCU_H - -#include "gd32f10x.h" - -/* RCU definitions */ -#define RCU RCU_BASE - -/* registers definitions */ -#if (defined(GD32F10X_HD) || defined(GD32F10X_XD)) - #define RCU_CTL REG32(RCU + 0x00U) /*!< control register */ - #define RCU_CFG0 REG32(RCU + 0x04U) /*!< clock configuration register 0 */ - #define RCU_INT REG32(RCU + 0x08U) /*!< clock interrupt register */ - #define RCU_APB2RST REG32(RCU + 0x0CU) /*!< APB2 reset register */ - #define RCU_APB1RST REG32(RCU + 0x10U) /*!< APB1 reset register */ - #define RCU_AHBEN REG32(RCU + 0x14U) /*!< AHB enable register */ - #define RCU_APB2EN REG32(RCU + 0x18U) /*!< APB2 enable register */ - #define RCU_APB1EN REG32(RCU + 0x1CU) /*!< APB1 enable register */ - #define RCU_BDCTL REG32(RCU + 0x20U) /*!< backup domain control register */ - #define RCU_RSTSCK REG32(RCU + 0x24U) /*!< reset source / clock register */ - #define RCU_CFG1 REG32(RCU + 0x2CU) /*!< clock configuration register 1 */ - #define RCU_DSV REG32(RCU + 0x34U) /*!< deep-sleep mode voltage register */ - #define RCU_ADDCTL REG32(RCU + 0xC0U) /*!< Additional clock control register */ - #define RCU_ADDINT REG32(RCU + 0xCCU) /*!< Additional clock interrupt register */ - #define RCU_ADDAPB1RST REG32(RCU + 0xE0U) /*!< APB1 additional reset register */ - #define RCU_ADDAPB1EN REG32(RCU + 0xE4U) /*!< APB1 additional enable register */ -#elif defined(GD32F10X_CL) - #define RCU_CTL REG32(RCU + 0x00U) /*!< control register */ - #define RCU_CFG0 REG32(RCU + 0x04U) /*!< clock configuration register 0 */ - #define RCU_INT REG32(RCU + 0x08U) /*!< clock interrupt register */ - #define RCU_APB2RST REG32(RCU + 0x0CU) /*!< APB2 reset register */ - #define RCU_APB1RST REG32(RCU + 0x10U) /*!< APB1 reset register */ - #define RCU_AHBEN REG32(RCU + 0x14U) /*!< AHB1 enable register */ - #define RCU_APB2EN REG32(RCU + 0x18U) /*!< APB2 enable register */ - #define RCU_APB1EN REG32(RCU + 0x1CU) /*!< APB1 enable register */ - #define RCU_BDCTL REG32(RCU + 0x20U) /*!< backup domain control register */ - #define RCU_RSTSCK REG32(RCU + 0x24U) /*!< reset source / clock register */ - #define RCU_AHBRST REG32(RCU + 0x28U) /*!< AHB reset register */ - #define RCU_CFG1 REG32(RCU + 0x2CU) /*!< clock configuration register 1 */ - #define RCU_DSV REG32(RCU + 0x34U) /*!< deep-sleep mode voltage register */ - #define RCU_ADDCTL REG32(RCU + 0xC0U) /*!< Additional clock control register */ - #define RCU_ADDINT REG32(RCU + 0xCCU) /*!< Additional clock interrupt register */ - #define RCU_ADDAPB1RST REG32(RCU + 0xE0U) /*!< APB1 additional reset register */ - #define RCU_ADDAPB1EN REG32(RCU + 0xE4U) /*!< APB1 additional enable register */ -#endif /* GD32F10X_HD and GD32F10X_XD */ - -/* bits definitions */ -/* RCU_CTL */ -#if (defined(GD32F10X_HD) || defined(GD32F10X_XD)) - #define RCU_CTL_IRC8MEN BIT(0) /*!< internal high speed oscillator enable */ - #define RCU_CTL_IRC8MSTB BIT(1) /*!< IRC8M high speed internal oscillator stabilization flag */ - #define RCU_CTL_IRC8MADJ BITS(3,7) /*!< high speed internal oscillator clock trim adjust value */ - #define RCU_CTL_IRC8MCALIB BITS(8,15) /*!< high speed internal oscillator calibration value register */ - #define RCU_CTL_HXTALEN BIT(16) /*!< external high speed oscillator enable */ - #define RCU_CTL_HXTALSTB BIT(17) /*!< external crystal oscillator clock stabilization flag */ - #define RCU_CTL_HXTALBPS BIT(18) /*!< external crystal oscillator clock bypass mode enable */ - #define RCU_CTL_CKMEN BIT(19) /*!< HXTAL clock monitor enable */ - #define RCU_CTL_PLLEN BIT(24) /*!< PLL enable */ - #define RCU_CTL_PLLSTB BIT(25) /*!< PLL clock stabilization flag */ -#elif defined(GD32F10X_CL) - #define RCU_CTL_IRC8MEN BIT(0) /*!< internal high speed oscillator enable */ - #define RCU_CTL_IRC8MSTB BIT(1) /*!< IRC8M high speed internal oscillator stabilization flag */ - #define RCU_CTL_IRC8MADJ BITS(3,7) /*!< high speed internal oscillator clock trim adjust value */ - #define RCU_CTL_IRC8MCALIB BITS(8,15) /*!< high speed internal oscillator calibration value register */ - #define RCU_CTL_HXTALEN BIT(16) /*!< external high speed oscillator enable */ - #define RCU_CTL_HXTALSTB BIT(17) /*!< external crystal oscillator clock stabilization flag */ - #define RCU_CTL_HXTALBPS BIT(18) /*!< external crystal oscillator clock bypass mode enable */ - #define RCU_CTL_CKMEN BIT(19) /*!< HXTAL clock monitor enable */ - #define RCU_CTL_PLLEN BIT(24) /*!< PLL enable */ - #define RCU_CTL_PLLSTB BIT(25) /*!< PLL clock stabilization flag */ - #define RCU_CTL_PLL1EN BIT(26) /*!< PLL1 enable */ - #define RCU_CTL_PLL1STB BIT(27) /*!< PLL1 clock stabilization flag */ - #define RCU_CTL_PLL2EN BIT(28) /*!< PLL2 enable */ - #define RCU_CTL_PLL2STB BIT(29) /*!< PLL2 clock stabilization flag */ -#endif /* GD32F10X_HD and GD32F10X_XD */ - -/* RCU_CFG0 */ -#if (defined(GD32F10X_HD) || defined(GD32F10X_XD)) - #define RCU_CFG0_SCS BITS(0,1) /*!< system clock switch */ - #define RCU_CFG0_SCSS BITS(2,3) /*!< system clock switch status */ - #define RCU_CFG0_AHBPSC BITS(4,7) /*!< AHB prescaler selection */ - #define RCU_CFG0_APB1PSC BITS(8,10) /*!< APB1 prescaler selection */ - #define RCU_CFG0_APB2PSC BITS(11,13) /*!< APB2 prescaler selection */ - #define RCU_CFG0_ADCPSC BITS(14,15) /*!< ADC prescaler selection */ - #define RCU_CFG0_PLLSEL BIT(16) /*!< PLL clock source selection */ - #define RCU_CFG0_PREDV0 BIT(17) /*!< PREDV0 division factor */ - #define RCU_CFG0_PLLMF BITS(18,21) /*!< PLL clock multiplication factor */ - #define RCU_CFG0_USBDPSC BITS(22,23) /*!< USBD clock prescaler selection */ - #define RCU_CFG0_CKOUT0SEL BITS(24,26) /*!< CKOUT0 clock source selection */ - #define RCU_CFG0_PLLMF_4 BIT(27) /*!< bit 4 of PLLMF */ - #define RCU_CFG0_ADCPSC_2 BIT(28) /*!< bit 2 of ADCPSC */ - #define RCU_CFG0_PLLMF_5 BIT(30) /*!< bit 5 of PLLMF */ - #define RCU_CFG0_USBDPSC_2 BIT(31) /*!< bit 2 of USBDPSC */ -#elif defined(GD32F10X_CL) - #define RCU_CFG0_SCS BITS(0,1) /*!< system clock switch */ - #define RCU_CFG0_SCSS BITS(2,3) /*!< system clock switch status */ - #define RCU_CFG0_AHBPSC BITS(4,7) /*!< AHB prescaler selection */ - #define RCU_CFG0_APB1PSC BITS(8,10) /*!< APB1 prescaler selection */ - #define RCU_CFG0_APB2PSC BITS(11,13) /*!< APB2 prescaler selection */ - #define RCU_CFG0_ADCPSC BITS(14,15) /*!< ADC prescaler selection */ - #define RCU_CFG0_PLLSEL BIT(16) /*!< PLL clock source selection */ - #define RCU_CFG0_PREDV0_LSB BIT(17) /*!< the LSB of PREDV0 division factor */ - #define RCU_CFG0_PLLMF BITS(18,21) /*!< PLL clock multiplication factor */ - #define RCU_CFG0_USBFSPSC BITS(22,23) /*!< USBFS clock prescaler selection */ - #define RCU_CFG0_CKOUT0SEL BITS(24,27) /*!< CKOUT0 clock source selection */ - #define RCU_CFG0_ADCPSC_2 BIT(28) /*!< bit 2 of ADCPSC */ - #define RCU_CFG0_PLLMF_4 BIT(29) /*!< bit 4 of PLLMF */ - #define RCU_CFG0_PLLMF_5 BIT(30) /*!< bit 5 of PLLMF */ - #define RCU_CFG0_USBFSPSC_2 BIT(31) /*!< bit 2 of USBFSPSC */ -#endif /* GD32F10X_HD and GD32F10X_XD */ - -/* RCU_INT */ -#if (defined(GD32F10X_HD) || defined(GD32F10X_XD)) - #define RCU_INT_IRC40KSTBIF BIT(0) /*!< IRC40K stabilization interrupt flag */ - #define RCU_INT_LXTALSTBIF BIT(1) /*!< LXTAL stabilization interrupt flag */ - #define RCU_INT_IRC8MSTBIF BIT(2) /*!< IRC8M stabilization interrupt flag */ - #define RCU_INT_HXTALSTBIF BIT(3) /*!< HXTAL stabilization interrupt flag */ - #define RCU_INT_PLLSTBIF BIT(4) /*!< PLL stabilization interrupt flag */ - #define RCU_INT_CKMIF BIT(7) /*!< HXTAL clock stuck interrupt flag */ - #define RCU_INT_IRC40KSTBIE BIT(8) /*!< IRC40K stabilization interrupt enable */ - #define RCU_INT_LXTALSTBIE BIT(9) /*!< LXTAL stabilization interrupt enable */ - #define RCU_INT_IRC8MSTBIE BIT(10) /*!< IRC8M stabilization interrupt enable */ - #define RCU_INT_HXTALSTBIE BIT(11) /*!< HXTAL stabilization interrupt enable */ - #define RCU_INT_PLLSTBIE BIT(12) /*!< PLL stabilization interrupt enable */ - #define RCU_INT_IRC40KSTBIC BIT(16) /*!< IRC40K Stabilization interrupt clear */ - #define RCU_INT_LXTALSTBIC BIT(17) /*!< LXTAL Stabilization interrupt clear */ - #define RCU_INT_IRC8MSTBIC BIT(18) /*!< IRC8M Stabilization interrupt clear */ - #define RCU_INT_HXTALSTBIC BIT(19) /*!< HXTAL Stabilization interrupt clear */ - #define RCU_INT_PLLSTBIC BIT(20) /*!< PLL stabilization interrupt clear */ - #define RCU_INT_CKMIC BIT(23) /*!< HXTAL clock stuck interrupt clear */ -#elif defined(GD32F10X_CL) - #define RCU_INT_IRC40KSTBIF BIT(0) /*!< IRC40K stabilization interrupt flag */ - #define RCU_INT_LXTALSTBIF BIT(1) /*!< LXTAL stabilization interrupt flag */ - #define RCU_INT_IRC8MSTBIF BIT(2) /*!< IRC8M stabilization interrupt flag */ - #define RCU_INT_HXTALSTBIF BIT(3) /*!< HXTAL stabilization interrupt flag */ - #define RCU_INT_PLLSTBIF BIT(4) /*!< PLL stabilization interrupt flag */ - #define RCU_INT_PLL1STBIF BIT(5) /*!< PLL1 stabilization interrupt flag */ - #define RCU_INT_PLL2STBIF BIT(6) /*!< PLL2 stabilization interrupt flag */ - #define RCU_INT_CKMIF BIT(7) /*!< HXTAL clock stuck interrupt flag */ - #define RCU_INT_IRC40KSTBIE BIT(8) /*!< IRC40K stabilization interrupt enable */ - #define RCU_INT_LXTALSTBIE BIT(9) /*!< LXTAL stabilization interrupt enable */ - #define RCU_INT_IRC8MSTBIE BIT(10) /*!< IRC8M stabilization interrupt enable */ - #define RCU_INT_HXTALSTBIE BIT(11) /*!< HXTAL stabilization interrupt enable */ - #define RCU_INT_PLLSTBIE BIT(12) /*!< PLL stabilization interrupt enable */ - #define RCU_INT_PLL1STBIE BIT(13) /*!< PLL1 stabilization interrupt enable */ - #define RCU_INT_PLL2STBIE BIT(14) /*!< PLL2 stabilization interrupt enable */ - #define RCU_INT_IRC40KSTBIC BIT(16) /*!< IRC40K stabilization interrupt clear */ - #define RCU_INT_LXTALSTBIC BIT(17) /*!< LXTAL stabilization interrupt clear */ - #define RCU_INT_IRC8MSTBIC BIT(18) /*!< IRC8M stabilization interrupt clear */ - #define RCU_INT_HXTALSTBIC BIT(19) /*!< HXTAL stabilization interrupt clear */ - #define RCU_INT_PLLSTBIC BIT(20) /*!< PLL stabilization interrupt clear */ - #define RCU_INT_PLL1STBIC BIT(21) /*!< PLL1 stabilization interrupt clear */ - #define RCU_INT_PLL2STBIC BIT(22) /*!< PLL2 stabilization interrupt clear */ - #define RCU_INT_CKMIC BIT(23) /*!< HXTAL clock stuck interrupt clear */ -#endif /* GD32F10X_HD and GD32F10X_XD */ - -/* RCU_APB2RST */ -#define RCU_APB2RST_AFRST BIT(0) /*!< alternate function I/O reset */ -#define RCU_APB2RST_PARST BIT(2) /*!< GPIO port A reset */ -#define RCU_APB2RST_PBRST BIT(3) /*!< GPIO port B reset */ -#define RCU_APB2RST_PCRST BIT(4) /*!< GPIO port C reset */ -#define RCU_APB2RST_PDRST BIT(5) /*!< GPIO port D reset */ -#define RCU_APB2RST_PERST BIT(6) /*!< GPIO port E reset */ -#define RCU_APB2RST_PFRST BIT(7) /*!< GPIO port F reset */ -#define RCU_APB2RST_PGRST BIT(8) /*!< GPIO port G reset */ -#define RCU_APB2RST_ADC0RST BIT(9) /*!< ADC0 reset */ -#define RCU_APB2RST_ADC1RST BIT(10) /*!< ADC1 reset */ -#define RCU_APB2RST_TIMER0RST BIT(11) /*!< TIMER0 reset */ -#define RCU_APB2RST_SPI0RST BIT(12) /*!< SPI0 reset */ -#define RCU_APB2RST_TIMER7RST BIT(13) /*!< TIMER7 reset */ -#define RCU_APB2RST_USART0RST BIT(14) /*!< USART0 reset */ -#ifndef GD32F10X_CL - #define RCU_APB2RST_ADC2RST BIT(15) /*!< ADC2 reset */ -#endif /* GD32F10X_CL */ -#ifndef GD32F10X_HD - #define RCU_APB2RST_TIMER8RST BIT(19) /*!< TIMER8 reset */ - #define RCU_APB2RST_TIMER9RST BIT(20) /*!< TIMER9 reset */ - #define RCU_APB2RST_TIMER10RST BIT(21) /*!< TIMER10 reset */ -#endif /* GD32F10X_HD */ - -/* RCU_APB1RST */ -#define RCU_APB1RST_TIMER1RST BIT(0) /*!< TIMER1 reset */ -#define RCU_APB1RST_TIMER2RST BIT(1) /*!< TIMER2 reset */ -#define RCU_APB1RST_TIMER3RST BIT(2) /*!< TIMER3 reset */ -#define RCU_APB1RST_TIMER4RST BIT(3) /*!< TIMER4 reset */ -#define RCU_APB1RST_TIMER5RST BIT(4) /*!< TIMER5 reset */ -#define RCU_APB1RST_TIMER6RST BIT(5) /*!< TIMER6 reset */ -#ifndef GD32F10X_HD - #define RCU_APB1RST_TIMER11RST BIT(6) /*!< TIMER11 reset */ - #define RCU_APB1RST_TIMER12RST BIT(7) /*!< TIMER12 reset */ - #define RCU_APB1RST_TIMER13RST BIT(8) /*!< TIMER13 reset */ -#endif /* GD32F10X_HD */ -#define RCU_APB1RST_WWDGTRST BIT(11) /*!< WWDGT reset */ -#define RCU_APB1RST_SPI1RST BIT(14) /*!< SPI1 reset */ -#define RCU_APB1RST_SPI2RST BIT(15) /*!< SPI2 reset */ -#define RCU_APB1RST_USART1RST BIT(17) /*!< USART1 reset */ -#define RCU_APB1RST_USART2RST BIT(18) /*!< USART2 reset */ -#define RCU_APB1RST_UART3RST BIT(19) /*!< UART3 reset */ -#define RCU_APB1RST_UART4RST BIT(20) /*!< UART4 reset */ -#define RCU_APB1RST_I2C0RST BIT(21) /*!< I2C0 reset */ -#define RCU_APB1RST_I2C1RST BIT(22) /*!< I2C1 reset */ -#if (defined(GD32F10X_HD) || defined(GD32F10X_XD)) - #define RCU_APB1RST_USBDRST BIT(23) /*!< USBD reset */ -#endif /* GD32F10X_HD and GD32F10X_XD */ -#define RCU_APB1RST_CAN0RST BIT(25) /*!< CAN0 reset */ -#ifdef GD32F10X_CL - #define RCU_APB1RST_CAN1RST BIT(26) /*!< CAN1 reset */ -#endif /* GD32F10X_CL */ -#define RCU_APB1RST_BKPIRST BIT(27) /*!< backup interface reset */ -#define RCU_APB1RST_PMURST BIT(28) /*!< PMU reset */ -#define RCU_APB1RST_DACRST BIT(29) /*!< DAC reset */ - -/* RCU_AHBEN */ -#define RCU_AHBEN_DMA0EN BIT(0) /*!< DMA0 clock enable */ -#define RCU_AHBEN_DMA1EN BIT(1) /*!< DMA1 clock enable */ -#define RCU_AHBEN_SRAMSPEN BIT(2) /*!< SRAM clock enable when sleep mode */ -#define RCU_AHBEN_FMCSPEN BIT(4) /*!< FMC clock enable when sleep mode */ -#define RCU_AHBEN_CRCEN BIT(6) /*!< CRC clock enable */ -#define RCU_AHBEN_EXMCEN BIT(8) /*!< EXMC clock enable */ -#if (defined(GD32F10X_HD) || defined(GD32F10X_XD)) - #define RCU_AHBEN_SDIOEN BIT(10) /*!< SDIO clock enable */ -#elif defined(GD32F10X_CL) - #define RCU_AHBEN_USBFSEN BIT(12) /*!< USBFS clock enable */ - #define RCU_AHBEN_ENETEN BIT(14) /*!< ENET clock enable */ - #define RCU_AHBEN_ENETTXEN BIT(15) /*!< Ethernet TX clock enable */ - #define RCU_AHBEN_ENETRXEN BIT(16) /*!< Ethernet RX clock enable */ -#endif /* GD32F10X_HD and GD32F10X_XD */ - -/* RCU_APB2EN */ -#define RCU_APB2EN_AFEN BIT(0) /*!< alternate function IO clock enable */ -#define RCU_APB2EN_PAEN BIT(2) /*!< GPIO port A clock enable */ -#define RCU_APB2EN_PBEN BIT(3) /*!< GPIO port B clock enable */ -#define RCU_APB2EN_PCEN BIT(4) /*!< GPIO port C clock enable */ -#define RCU_APB2EN_PDEN BIT(5) /*!< GPIO port D clock enable */ -#define RCU_APB2EN_PEEN BIT(6) /*!< GPIO port E clock enable */ -#define RCU_APB2EN_PFEN BIT(7) /*!< GPIO port F clock enable */ -#define RCU_APB2EN_PGEN BIT(8) /*!< GPIO port G clock enable */ -#define RCU_APB2EN_ADC0EN BIT(9) /*!< ADC0 clock enable */ -#define RCU_APB2EN_ADC1EN BIT(10) /*!< ADC1 clock enable */ -#define RCU_APB2EN_TIMER0EN BIT(11) /*!< TIMER0 clock enable */ -#define RCU_APB2EN_SPI0EN BIT(12) /*!< SPI0 clock enable */ -#define RCU_APB2EN_TIMER7EN BIT(13) /*!< TIMER7 clock enable */ -#define RCU_APB2EN_USART0EN BIT(14) /*!< USART0 clock enable */ -#ifndef GD32F10X_CL - #define RCU_APB2EN_ADC2EN BIT(15) /*!< ADC2 clock enable */ -#endif /* GD32F10X_CL */ -#ifndef GD32F10X_HD - #define RCU_APB2EN_TIMER8EN BIT(19) /*!< TIMER8 clock enable */ - #define RCU_APB2EN_TIMER9EN BIT(20) /*!< TIMER9 clock enable */ - #define RCU_APB2EN_TIMER10EN BIT(21) /*!< TIMER10 clock enable */ -#endif /* GD32F10X_HD */ - -/* RCU_APB1EN */ -#define RCU_APB1EN_TIMER1EN BIT(0) /*!< TIMER1 clock enable */ -#define RCU_APB1EN_TIMER2EN BIT(1) /*!< TIMER2 clock enable */ -#define RCU_APB1EN_TIMER3EN BIT(2) /*!< TIMER3 clock enable */ -#define RCU_APB1EN_TIMER4EN BIT(3) /*!< TIMER4 clock enable */ -#define RCU_APB1EN_TIMER5EN BIT(4) /*!< TIMER5 clock enable */ -#define RCU_APB1EN_TIMER6EN BIT(5) /*!< TIMER6 clock enable */ -#ifndef GD32F10X_HD - #define RCU_APB1EN_TIMER11EN BIT(6) /*!< TIMER11 clock enable */ - #define RCU_APB1EN_TIMER12EN BIT(7) /*!< TIMER12 clock enable */ - #define RCU_APB1EN_TIMER13EN BIT(8) /*!< TIMER13 clock enable */ -#endif /* GD32F10X_HD */ -#define RCU_APB1EN_WWDGTEN BIT(11) /*!< WWDGT clock enable */ -#define RCU_APB1EN_SPI1EN BIT(14) /*!< SPI1 clock enable */ -#define RCU_APB1EN_SPI2EN BIT(15) /*!< SPI2 clock enable */ -#define RCU_APB1EN_USART1EN BIT(17) /*!< USART1 clock enable */ -#define RCU_APB1EN_USART2EN BIT(18) /*!< USART2 clock enable */ -#define RCU_APB1EN_UART3EN BIT(19) /*!< UART3 clock enable */ -#define RCU_APB1EN_UART4EN BIT(20) /*!< UART4 clock enable */ -#define RCU_APB1EN_I2C0EN BIT(21) /*!< I2C0 clock enable */ -#define RCU_APB1EN_I2C1EN BIT(22) /*!< I2C1 clock enable */ -#if (defined(GD32F10X_HD) || defined(GD32F10X_XD)) - #define RCU_APB1EN_USBDEN BIT(23) /*!< USBD clock enable */ -#endif /* GD32F10X_HD and GD32F10X_XD */ -#define RCU_APB1EN_CAN0EN BIT(25) /*!< CAN0 clock enable */ -#ifdef GD32F10X_CL - #define RCU_APB1EN_CAN1EN BIT(26) /*!< CAN1 clock enable */ -#endif /* GD32F10X_CL */ -#define RCU_APB1EN_BKPIEN BIT(27) /*!< backup interface clock enable */ -#define RCU_APB1EN_PMUEN BIT(28) /*!< PMU clock enable */ -#define RCU_APB1EN_DACEN BIT(29) /*!< DAC clock enable */ - -/* RCU_BDCTL */ -#define RCU_BDCTL_LXTALEN BIT(0) /*!< LXTAL enable */ -#define RCU_BDCTL_LXTALSTB BIT(1) /*!< low speed crystal oscillator stabilization flag */ -#define RCU_BDCTL_LXTALBPS BIT(2) /*!< LXTAL bypass mode enable */ -#define RCU_BDCTL_LXTALDRI BITS(3,4) /*!< LXTAL drive capability */ -#define RCU_BDCTL_RTCSRC BITS(8,9) /*!< RTC clock entry selection */ -#define RCU_BDCTL_RTCEN BIT(15) /*!< RTC clock enable */ -#define RCU_BDCTL_BKPRST BIT(16) /*!< backup domain reset */ - -/* RCU_RSTSCK */ -#define RCU_RSTSCK_IRC40KEN BIT(0) /*!< IRC40K enable */ -#define RCU_RSTSCK_IRC40KSTB BIT(1) /*!< IRC40K stabilization flag */ -#define RCU_RSTSCK_RSTFC BIT(24) /*!< reset flag clear */ -#define RCU_RSTSCK_EPRSTF BIT(26) /*!< external pin reset flag */ -#define RCU_RSTSCK_PORRSTF BIT(27) /*!< power reset flag */ -#define RCU_RSTSCK_SWRSTF BIT(28) /*!< software reset flag */ -#define RCU_RSTSCK_FWDGTRSTF BIT(29) /*!< free watchdog timer reset flag */ -#define RCU_RSTSCK_WWDGTRSTF BIT(30) /*!< window watchdog timer reset flag */ -#define RCU_RSTSCK_LPRSTF BIT(31) /*!< low-power reset flag */ - -#ifdef GD32F10X_CL - /* RCU_AHBRST */ - #define RCU_AHBRST_USBFSRST BIT(12) /*!< USBFS reset */ - #define RCU_AHBRST_ENETRST BIT(14) /*!< ENET reset */ -#endif /* GD32F10X_CL */ - -/* RCU_CFG1 */ -#if (defined(GD32F10X_HD) || defined(GD32F10X_XD)) - #define RCU_CFG1_ADCPSC_3 BIT(29) /*!< bit 4 of ADCPSC */ - #define RCU_CFG1_PLLPRESEL BIT(30) /*!< PLL clock source selection */ -#elif defined(GD32F10X_CL) - #define RCU_CFG1_PREDV0 BITS(0,3) /*!< PREDV0 division factor */ - #define RCU_CFG1_PREDV1 BITS(4,7) /*!< PREDV1 division factor */ - #define RCU_CFG1_PLL1MF BITS(8,11) /*!< PLL1 clock multiplication factor */ - #define RCU_CFG1_PLL2MF BITS(12,15) /*!< PLL2 clock multiplication factor */ - #define RCU_CFG1_PREDV0SEL BIT(16) /*!< PREDV0 input clock source selection */ - #define RCU_CFG1_I2S1SEL BIT(17) /*!< I2S1 clock source selection */ - #define RCU_CFG1_I2S2SEL BIT(18) /*!< I2S2 clock source selection */ - #define RCU_CFG1_ADCPSC_3 BIT(29) /*!< bit 4 of ADCPSC */ - #define RCU_CFG1_PLLPRESEL BIT(30) /*!< PLL clock source selection */ - #define RCU_CFG1_PLL2MF_4 BIT(31) /*!< bit 5 of PLL2MF */ -#endif /* GD32F10X_HD and GD32F10X_XD */ - -/* RCU_DSV */ -#define RCU_DSV_DSLPVS BITS(0,2) /*!< deep-sleep mode voltage select */ - -/* RCU_ADDCTL */ -#define RCU_ADDCTL_CK48MSEL BIT(0) /*!< 48MHz clock selection */ -#define RCU_ADDCTL_IRC48MEN BIT(16) /*!< internal 48MHz RC oscillator enable */ -#define RCU_ADDCTL_IRC48MSTB BIT(17) /*!< internal 48MHz RC oscillator clock stabilization flag */ -#define RCU_ADDCTL_IRC48MCAL BITS(24,31) /*!< internal 48MHz RC oscillator calibration value register */ - -/* RCU_ADDINT */ -#define RCU_ADDINT_IRC48MSTBIF BIT(6) /*!< IRC48M stabilization interrupt flag */ -#define RCU_ADDINT_IRC48MSTBIE BIT(14) /*!< internal 48 MHz RC oscillator stabilization interrupt enable */ -#define RCU_ADDINT_IRC48MSTBIC BIT(22) /*!< internal 48 MHz RC oscillator stabilization interrupt clear */ - -/* RCU_ADDAPB1RST */ -#define RCU_ADDAPB1RST_CTCRST BIT(27) /*!< CTC reset */ - -/* RCU_ADDAPB1EN */ -#define RCU_ADDAPB1EN_CTCEN BIT(27) /*!< CTC clock enable */ - - -/* constants definitions */ -/* define the peripheral clock enable bit position and its register index offset */ -#define RCU_REGIDX_BIT(regidx, bitpos) (((uint32_t)(regidx) << 6) | (uint32_t)(bitpos)) -#define RCU_REG_VAL(periph) (REG32(RCU + ((uint32_t)(periph) >> 6))) -#define RCU_BIT_POS(val) ((uint32_t)(val) & 0x1FU) - -/* register offset */ -/* peripherals enable */ -#define AHBEN_REG_OFFSET 0x14U /*!< AHB enable register offset */ -#define APB1EN_REG_OFFSET 0x1CU /*!< APB1 enable register offset */ -#define APB2EN_REG_OFFSET 0x18U /*!< APB2 enable register offset */ -#define ADD_APB1EN_REG_OFFSET 0xE4U /*!< APB1 additional enable register offset */ - -/* peripherals reset */ -#define AHBRST_REG_OFFSET 0x28U /*!< AHB reset register offset */ -#define APB1RST_REG_OFFSET 0x10U /*!< APB1 reset register offset */ -#define APB2RST_REG_OFFSET 0x0CU /*!< APB2 reset register offset */ -#define ADD_APB1RST_REG_OFFSET 0xE0U /*!< APB1 additional reset register offset */ -#define RSTSCK_REG_OFFSET 0x24U /*!< reset source/clock register offset */ - -/* clock control */ -#define CTL_REG_OFFSET 0x00U /*!< control register offset */ -#define BDCTL_REG_OFFSET 0x20U /*!< backup domain control register offset */ -#define ADDCTL_REG_OFFSET 0xC0U /*!< additional clock control register offset */ - -/* clock stabilization and stuck interrupt */ -#define INT_REG_OFFSET 0x08U /*!< clock interrupt register offset */ -#define ADDINT_REG_OFFSET 0xCCU /*!< additional clock interrupt register offset */ - -/* configuration register */ -#define CFG0_REG_OFFSET 0x04U /*!< clock configuration register 0 offset */ -#define CFG1_REG_OFFSET 0x2CU /*!< clock configuration register 1 offset */ - -/* peripheral clock enable */ -typedef enum { - /* AHB peripherals */ - RCU_DMA0 = RCU_REGIDX_BIT(AHBEN_REG_OFFSET, 0U), /*!< DMA0 clock */ - RCU_DMA1 = RCU_REGIDX_BIT(AHBEN_REG_OFFSET, 1U), /*!< DMA1 clock */ - RCU_CRC = RCU_REGIDX_BIT(AHBEN_REG_OFFSET, 6U), /*!< CRC clock */ - RCU_EXMC = RCU_REGIDX_BIT(AHBEN_REG_OFFSET, 8U), /*!< EXMC clock */ -#if (defined(GD32F10X_HD) || defined(GD32F10X_XD)) - RCU_SDIO = RCU_REGIDX_BIT(AHBEN_REG_OFFSET, 10U), /*!< SDIO clock */ -#elif defined(GD32F10X_CL) - RCU_USBFS = RCU_REGIDX_BIT(AHBEN_REG_OFFSET, 12U), /*!< USBFS clock */ - RCU_ENET = RCU_REGIDX_BIT(AHBEN_REG_OFFSET, 14U), /*!< ENET clock */ - RCU_ENETTX = RCU_REGIDX_BIT(AHBEN_REG_OFFSET, 15U), /*!< ENETTX clock */ - RCU_ENETRX = RCU_REGIDX_BIT(AHBEN_REG_OFFSET, 16U), /*!< ENETRX clock */ -#endif /* GD32F10X_HD and GD32F10X_XD */ - - /* APB1 peripherals */ - RCU_TIMER1 = RCU_REGIDX_BIT(APB1EN_REG_OFFSET, 0U), /*!< TIMER1 clock */ - RCU_TIMER2 = RCU_REGIDX_BIT(APB1EN_REG_OFFSET, 1U), /*!< TIMER2 clock */ - RCU_TIMER3 = RCU_REGIDX_BIT(APB1EN_REG_OFFSET, 2U), /*!< TIMER3 clock */ - RCU_TIMER4 = RCU_REGIDX_BIT(APB1EN_REG_OFFSET, 3U), /*!< TIMER4 clock */ - RCU_TIMER5 = RCU_REGIDX_BIT(APB1EN_REG_OFFSET, 4U), /*!< TIMER5 clock */ - RCU_TIMER6 = RCU_REGIDX_BIT(APB1EN_REG_OFFSET, 5U), /*!< TIMER6 clock */ -#ifndef GD32F10X_HD - RCU_TIMER11 = RCU_REGIDX_BIT(APB1EN_REG_OFFSET, 6U), /*!< TIMER11 clock */ - RCU_TIMER12 = RCU_REGIDX_BIT(APB1EN_REG_OFFSET, 7U), /*!< TIMER12 clock */ - RCU_TIMER13 = RCU_REGIDX_BIT(APB1EN_REG_OFFSET, 8U), /*!< TIMER13 clock */ -#endif /* GD32F10X_HD */ - RCU_WWDGT = RCU_REGIDX_BIT(APB1EN_REG_OFFSET, 11U), /*!< WWDGT clock */ - RCU_SPI1 = RCU_REGIDX_BIT(APB1EN_REG_OFFSET, 14U), /*!< SPI1 clock */ - RCU_SPI2 = RCU_REGIDX_BIT(APB1EN_REG_OFFSET, 15U), /*!< SPI2 clock */ - RCU_USART1 = RCU_REGIDX_BIT(APB1EN_REG_OFFSET, 17U), /*!< USART1 clock */ - RCU_USART2 = RCU_REGIDX_BIT(APB1EN_REG_OFFSET, 18U), /*!< USART2 clock */ - RCU_UART3 = RCU_REGIDX_BIT(APB1EN_REG_OFFSET, 19U), /*!< UART3 clock */ - RCU_UART4 = RCU_REGIDX_BIT(APB1EN_REG_OFFSET, 20U), /*!< UART4 clock */ - RCU_I2C0 = RCU_REGIDX_BIT(APB1EN_REG_OFFSET, 21U), /*!< I2C0 clock */ - RCU_I2C1 = RCU_REGIDX_BIT(APB1EN_REG_OFFSET, 22U), /*!< I2C1 clock */ -#if (defined(GD32F10X_HD) || defined(GD32F10X_XD)) - RCU_USBD = RCU_REGIDX_BIT(APB1EN_REG_OFFSET, 23U), /*!< USBD clock */ -#endif /* GD32F10X_HD and GD32F10X_XD */ - RCU_CAN0 = RCU_REGIDX_BIT(APB1EN_REG_OFFSET, 25U), /*!< CAN0 clock */ -#ifdef GD32F10X_CL - RCU_CAN1 = RCU_REGIDX_BIT(APB1EN_REG_OFFSET, 26U), /*!< CAN1 clock */ -#endif /* GD32F10X_CL */ - RCU_BKPI = RCU_REGIDX_BIT(APB1EN_REG_OFFSET, 27U), /*!< BKPI clock */ - RCU_PMU = RCU_REGIDX_BIT(APB1EN_REG_OFFSET, 28U), /*!< PMU clock */ - RCU_DAC = RCU_REGIDX_BIT(APB1EN_REG_OFFSET, 29U), /*!< DAC clock */ - RCU_RTC = RCU_REGIDX_BIT(BDCTL_REG_OFFSET, 15U), /*!< RTC clock */ - RCU_CTC = RCU_REGIDX_BIT(ADD_APB1EN_REG_OFFSET, 27U), /*!< CTC clock */ - - /* APB2 peripherals */ - RCU_AF = RCU_REGIDX_BIT(APB2EN_REG_OFFSET, 0U), /*!< alternate function clock */ - RCU_GPIOA = RCU_REGIDX_BIT(APB2EN_REG_OFFSET, 2U), /*!< GPIOA clock */ - RCU_GPIOB = RCU_REGIDX_BIT(APB2EN_REG_OFFSET, 3U), /*!< GPIOB clock */ - RCU_GPIOC = RCU_REGIDX_BIT(APB2EN_REG_OFFSET, 4U), /*!< GPIOC clock */ - RCU_GPIOD = RCU_REGIDX_BIT(APB2EN_REG_OFFSET, 5U), /*!< GPIOD clock */ - RCU_GPIOE = RCU_REGIDX_BIT(APB2EN_REG_OFFSET, 6U), /*!< GPIOE clock */ - RCU_GPIOF = RCU_REGIDX_BIT(APB2EN_REG_OFFSET, 7U), /*!< GPIOF clock */ - RCU_GPIOG = RCU_REGIDX_BIT(APB2EN_REG_OFFSET, 8U), /*!< GPIOG clock */ - RCU_ADC0 = RCU_REGIDX_BIT(APB2EN_REG_OFFSET, 9U), /*!< ADC0 clock */ - RCU_ADC1 = RCU_REGIDX_BIT(APB2EN_REG_OFFSET, 10U), /*!< ADC1 clock */ - RCU_TIMER0 = RCU_REGIDX_BIT(APB2EN_REG_OFFSET, 11U), /*!< TIMER0 clock */ - RCU_SPI0 = RCU_REGIDX_BIT(APB2EN_REG_OFFSET, 12U), /*!< SPI0 clock */ - RCU_TIMER7 = RCU_REGIDX_BIT(APB2EN_REG_OFFSET, 13U), /*!< TIMER7 clock */ - RCU_USART0 = RCU_REGIDX_BIT(APB2EN_REG_OFFSET, 14U), /*!< USART0 clock */ -#ifndef GD32F10X_CL - RCU_ADC2 = RCU_REGIDX_BIT(APB2EN_REG_OFFSET, 15U), /*!< ADC2 clock */ -#endif /* GD32F10X_CL */ -#ifndef GD32F10X_HD - RCU_TIMER8 = RCU_REGIDX_BIT(APB2EN_REG_OFFSET, 19U), /*!< TIMER8 clock */ - RCU_TIMER9 = RCU_REGIDX_BIT(APB2EN_REG_OFFSET, 20U), /*!< TIMER9 clock */ - RCU_TIMER10 = RCU_REGIDX_BIT(APB2EN_REG_OFFSET, 21U), /*!< TIMER10 clock */ -#endif /* GD32F10X_HD */ -} rcu_periph_enum; - -/* peripheral clock enable when sleep mode*/ -typedef enum { - /* AHB peripherals */ - RCU_SRAM_SLP = RCU_REGIDX_BIT(AHBEN_REG_OFFSET, 2U), /*!< SRAM clock */ - RCU_FMC_SLP = RCU_REGIDX_BIT(AHBEN_REG_OFFSET, 4U), /*!< FMC clock */ -} rcu_periph_sleep_enum; - -/* peripherals reset */ -typedef enum { - /* AHB peripherals */ -#ifdef GD32F10X_CL - RCU_USBFSRST = RCU_REGIDX_BIT(AHBRST_REG_OFFSET, 12U), /*!< USBFS clock reset */ - RCU_ENETRST = RCU_REGIDX_BIT(AHBRST_REG_OFFSET, 14U), /*!< ENET clock reset */ -#endif /* GD32F10X_CL */ - - /* APB1 peripherals */ - RCU_TIMER1RST = RCU_REGIDX_BIT(APB1RST_REG_OFFSET, 0U), /*!< TIMER1 clock reset */ - RCU_TIMER2RST = RCU_REGIDX_BIT(APB1RST_REG_OFFSET, 1U), /*!< TIMER2 clock reset */ - RCU_TIMER3RST = RCU_REGIDX_BIT(APB1RST_REG_OFFSET, 2U), /*!< TIMER3 clock reset */ - RCU_TIMER4RST = RCU_REGIDX_BIT(APB1RST_REG_OFFSET, 3U), /*!< TIMER4 clock reset */ - RCU_TIMER5RST = RCU_REGIDX_BIT(APB1RST_REG_OFFSET, 4U), /*!< TIMER5 clock reset */ - RCU_TIMER6RST = RCU_REGIDX_BIT(APB1RST_REG_OFFSET, 5U), /*!< TIMER6 clock reset */ -#ifndef GD32F10X_HD - RCU_TIMER11RST = RCU_REGIDX_BIT(APB1RST_REG_OFFSET, 6U), /*!< TIMER11 clock reset */ - RCU_TIMER12RST = RCU_REGIDX_BIT(APB1RST_REG_OFFSET, 7U), /*!< TIMER12 clock reset */ - RCU_TIMER13RST = RCU_REGIDX_BIT(APB1RST_REG_OFFSET, 8U), /*!< TIMER13 clock reset */ -#endif /* GD32F10X_HD */ - RCU_WWDGTRST = RCU_REGIDX_BIT(APB1RST_REG_OFFSET, 11U), /*!< WWDGT clock reset */ - RCU_SPI1RST = RCU_REGIDX_BIT(APB1RST_REG_OFFSET, 14U), /*!< SPI1 clock reset */ - RCU_SPI2RST = RCU_REGIDX_BIT(APB1RST_REG_OFFSET, 15U), /*!< SPI2 clock reset */ - RCU_USART1RST = RCU_REGIDX_BIT(APB1RST_REG_OFFSET, 17U), /*!< USART1 clock reset */ - RCU_USART2RST = RCU_REGIDX_BIT(APB1RST_REG_OFFSET, 18U), /*!< USART2 clock reset */ - RCU_UART3RST = RCU_REGIDX_BIT(APB1RST_REG_OFFSET, 19U), /*!< UART3 clock reset */ - RCU_UART4RST = RCU_REGIDX_BIT(APB1RST_REG_OFFSET, 20U), /*!< UART4 clock reset */ - RCU_I2C0RST = RCU_REGIDX_BIT(APB1RST_REG_OFFSET, 21U), /*!< I2C0 clock reset */ - RCU_I2C1RST = RCU_REGIDX_BIT(APB1RST_REG_OFFSET, 22U), /*!< I2C1 clock reset */ -#if (defined(GD32F10X_HD) || defined(GD32F10X_XD)) - RCU_USBDRST = RCU_REGIDX_BIT(APB1RST_REG_OFFSET, 23U), /*!< USBD clock reset */ -#endif /* GD32F10X_HD and GD32F10X_XD */ - RCU_CAN0RST = RCU_REGIDX_BIT(APB1RST_REG_OFFSET, 25U), /*!< CAN0 clock reset */ -#ifdef GD32F10X_CL - RCU_CAN1RST = RCU_REGIDX_BIT(APB1RST_REG_OFFSET, 26U), /*!< CAN1 clock reset */ -#endif /* GD32F10X_CL */ - RCU_BKPIRST = RCU_REGIDX_BIT(APB1RST_REG_OFFSET, 27U), /*!< BKPI clock reset */ - RCU_PMURST = RCU_REGIDX_BIT(APB1RST_REG_OFFSET, 28U), /*!< PMU clock reset */ - RCU_DACRST = RCU_REGIDX_BIT(APB1RST_REG_OFFSET, 29U), /*!< DAC clock reset */ - RCU_CTCRST = RCU_REGIDX_BIT(ADD_APB1RST_REG_OFFSET, 27U), /*!< RTC clock reset */ - - /* APB2 peripherals */ - RCU_AFRST = RCU_REGIDX_BIT(APB2RST_REG_OFFSET, 0U), /*!< alternate function clock reset */ - RCU_GPIOARST = RCU_REGIDX_BIT(APB2RST_REG_OFFSET, 2U), /*!< GPIOA clock reset */ - RCU_GPIOBRST = RCU_REGIDX_BIT(APB2RST_REG_OFFSET, 3U), /*!< GPIOB clock reset */ - RCU_GPIOCRST = RCU_REGIDX_BIT(APB2RST_REG_OFFSET, 4U), /*!< GPIOC clock reset */ - RCU_GPIODRST = RCU_REGIDX_BIT(APB2RST_REG_OFFSET, 5U), /*!< GPIOD clock reset */ - RCU_GPIOERST = RCU_REGIDX_BIT(APB2RST_REG_OFFSET, 6U), /*!< GPIOE clock reset */ - RCU_GPIOFRST = RCU_REGIDX_BIT(APB2RST_REG_OFFSET, 7U), /*!< GPIOF clock reset */ - RCU_GPIOGRST = RCU_REGIDX_BIT(APB2RST_REG_OFFSET, 8U), /*!< GPIOG clock reset */ - RCU_ADC0RST = RCU_REGIDX_BIT(APB2RST_REG_OFFSET, 9U), /*!< ADC0 clock reset */ - RCU_ADC1RST = RCU_REGIDX_BIT(APB2RST_REG_OFFSET, 10U), /*!< ADC1 clock reset */ - RCU_TIMER0RST = RCU_REGIDX_BIT(APB2RST_REG_OFFSET, 11U), /*!< TIMER0 clock reset */ - RCU_SPI0RST = RCU_REGIDX_BIT(APB2RST_REG_OFFSET, 12U), /*!< SPI0 clock reset */ - RCU_TIMER7RST = RCU_REGIDX_BIT(APB2RST_REG_OFFSET, 13U), /*!< TIMER7 clock reset */ - RCU_USART0RST = RCU_REGIDX_BIT(APB2RST_REG_OFFSET, 14U), /*!< USART0 clock reset */ -#ifndef GD32F10X_CL - RCU_ADC2RST = RCU_REGIDX_BIT(APB2RST_REG_OFFSET, 15U), /*!< ADC2 clock reset */ -#endif /* GD32F10X_CL */ -#ifndef GD32F10X_HD - RCU_TIMER8RST = RCU_REGIDX_BIT(APB2RST_REG_OFFSET, 19U), /*!< TIMER8 clock reset */ - RCU_TIMER9RST = RCU_REGIDX_BIT(APB2RST_REG_OFFSET, 20U), /*!< TIMER9 clock reset */ - RCU_TIMER10RST = RCU_REGIDX_BIT(APB2RST_REG_OFFSET, 21U), /*!< TIMER10 clock reset */ -#endif /* GD32F10X_HD */ -} rcu_periph_reset_enum; - -/* clock stabilization and peripheral reset flags */ -typedef enum { - /* clock stabilization flags */ - RCU_FLAG_IRC8MSTB = RCU_REGIDX_BIT(CTL_REG_OFFSET, 1U), /*!< IRC8M stabilization flags */ - RCU_FLAG_HXTALSTB = RCU_REGIDX_BIT(CTL_REG_OFFSET, 17U), /*!< HXTAL stabilization flags */ - RCU_FLAG_PLLSTB = RCU_REGIDX_BIT(CTL_REG_OFFSET, 25U), /*!< PLL stabilization flags */ -#ifdef GD32F10X_CL - RCU_FLAG_PLL1STB = RCU_REGIDX_BIT(CTL_REG_OFFSET, 27U), /*!< PLL1 stabilization flags */ - RCU_FLAG_PLL2STB = RCU_REGIDX_BIT(CTL_REG_OFFSET, 29U), /*!< PLL2 stabilization flags */ -#endif /* GD32F10X_CL */ - RCU_FLAG_LXTALSTB = RCU_REGIDX_BIT(BDCTL_REG_OFFSET, 1U), /*!< LXTAL stabilization flags */ - RCU_FLAG_IRC40KSTB = RCU_REGIDX_BIT(RSTSCK_REG_OFFSET, 1U), /*!< IRC40K stabilization flags */ - RCU_FLAG_IRC48MSTB = RCU_REGIDX_BIT(ADDCTL_REG_OFFSET, 17U), /*!< IRC48M stabilization flags */ - /* reset source flags */ - RCU_FLAG_EPRST = RCU_REGIDX_BIT(RSTSCK_REG_OFFSET, 26U), /*!< external PIN reset flags */ - RCU_FLAG_PORRST = RCU_REGIDX_BIT(RSTSCK_REG_OFFSET, 27U), /*!< power reset flags */ - RCU_FLAG_SWRST = RCU_REGIDX_BIT(RSTSCK_REG_OFFSET, 28U), /*!< software reset flags */ - RCU_FLAG_FWDGTRST = RCU_REGIDX_BIT(RSTSCK_REG_OFFSET, 29U), /*!< FWDGT reset flags */ - RCU_FLAG_WWDGTRST = RCU_REGIDX_BIT(RSTSCK_REG_OFFSET, 30U), /*!< WWDGT reset flags */ - RCU_FLAG_LPRST = RCU_REGIDX_BIT(RSTSCK_REG_OFFSET, 31U), /*!< low-power reset flags */ -} rcu_flag_enum; - -/* clock stabilization and ckm interrupt flags */ -typedef enum { - RCU_INT_FLAG_IRC40KSTB = RCU_REGIDX_BIT(INT_REG_OFFSET, 0U), /*!< IRC40K stabilization interrupt flag */ - RCU_INT_FLAG_LXTALSTB = RCU_REGIDX_BIT(INT_REG_OFFSET, 1U), /*!< LXTAL stabilization interrupt flag */ - RCU_INT_FLAG_IRC8MSTB = RCU_REGIDX_BIT(INT_REG_OFFSET, 2U), /*!< IRC8M stabilization interrupt flag */ - RCU_INT_FLAG_HXTALSTB = RCU_REGIDX_BIT(INT_REG_OFFSET, 3U), /*!< HXTAL stabilization interrupt flag */ - RCU_INT_FLAG_PLLSTB = RCU_REGIDX_BIT(INT_REG_OFFSET, 4U), /*!< PLL stabilization interrupt flag */ -#ifdef GD32F10X_CL - RCU_INT_FLAG_PLL1STB = RCU_REGIDX_BIT(INT_REG_OFFSET, 5U), /*!< PLL1 stabilization interrupt flag */ - RCU_INT_FLAG_PLL2STB = RCU_REGIDX_BIT(INT_REG_OFFSET, 6U), /*!< PLL2 stabilization interrupt flag */ -#endif /* GD32F10X_CL */ - RCU_INT_FLAG_CKM = RCU_REGIDX_BIT(INT_REG_OFFSET, 7U), /*!< HXTAL clock stuck interrupt flag */ - RCU_INT_FLAG_IRC48MSTB = RCU_REGIDX_BIT(ADDINT_REG_OFFSET, 6U), /*!< IRC48M stabilization interrupt flag */ -} rcu_int_flag_enum; - -/* clock stabilization and stuck interrupt flags clear */ -typedef enum { - RCU_INT_FLAG_IRC40KSTB_CLR = RCU_REGIDX_BIT(INT_REG_OFFSET, 16U), /*!< IRC40K stabilization interrupt flags clear */ - RCU_INT_FLAG_LXTALSTB_CLR = RCU_REGIDX_BIT(INT_REG_OFFSET, 17U), /*!< LXTAL stabilization interrupt flags clear */ - RCU_INT_FLAG_IRC8MSTB_CLR = RCU_REGIDX_BIT(INT_REG_OFFSET, 18U), /*!< IRC8M stabilization interrupt flags clear */ - RCU_INT_FLAG_HXTALSTB_CLR = RCU_REGIDX_BIT(INT_REG_OFFSET, 19U), /*!< HXTAL stabilization interrupt flags clear */ - RCU_INT_FLAG_PLLSTB_CLR = RCU_REGIDX_BIT(INT_REG_OFFSET, 20U), /*!< PLL stabilization interrupt flags clear */ -#ifdef GD32F10X_CL - RCU_INT_FLAG_PLL1STB_CLR = RCU_REGIDX_BIT(INT_REG_OFFSET, 21U), /*!< PLL1 stabilization interrupt flags clear */ - RCU_INT_FLAG_PLL2STB_CLR = RCU_REGIDX_BIT(INT_REG_OFFSET, 22U), /*!< PLL2 stabilization interrupt flags clear */ -#endif /* GD32F10X_CL */ - RCU_INT_FLAG_CKM_CLR = RCU_REGIDX_BIT(INT_REG_OFFSET, 23U), /*!< CKM interrupt flags clear */ - RCU_INT_FLAG_IRC48MSTB_CLR = RCU_REGIDX_BIT(ADDINT_REG_OFFSET, 22U), /*!< internal 48 MHz RC oscillator stabilization interrupt clear */ -} rcu_int_flag_clear_enum; - -/* clock stabilization interrupt enable or disable */ -typedef enum { - RCU_INT_IRC40KSTB = RCU_REGIDX_BIT(INT_REG_OFFSET, 8U), /*!< IRC40K stabilization interrupt */ - RCU_INT_LXTALSTB = RCU_REGIDX_BIT(INT_REG_OFFSET, 9U), /*!< LXTAL stabilization interrupt */ - RCU_INT_IRC8MSTB = RCU_REGIDX_BIT(INT_REG_OFFSET, 10U), /*!< IRC8M stabilization interrupt */ - RCU_INT_HXTALSTB = RCU_REGIDX_BIT(INT_REG_OFFSET, 11U), /*!< HXTAL stabilization interrupt */ - RCU_INT_PLLSTB = RCU_REGIDX_BIT(INT_REG_OFFSET, 12U), /*!< PLL stabilization interrupt */ -#ifdef GD32F10X_CL - RCU_INT_PLL1STB = RCU_REGIDX_BIT(INT_REG_OFFSET, 13U), /*!< PLL1 stabilization interrupt */ - RCU_INT_PLL2STB = RCU_REGIDX_BIT(INT_REG_OFFSET, 14U), /*!< PLL2 stabilization interrupt */ -#endif /* GD32F10X_CL */ - RCU_INT_IRC48MSTB = RCU_REGIDX_BIT(ADDINT_REG_OFFSET, 14U), /*!< internal 48 MHz RC oscillator stabilization interrupt */ -} rcu_int_enum; - -/* oscillator types */ -typedef enum { - RCU_HXTAL = RCU_REGIDX_BIT(CTL_REG_OFFSET, 16U), /*!< HXTAL */ - RCU_LXTAL = RCU_REGIDX_BIT(BDCTL_REG_OFFSET, 0U), /*!< LXTAL */ - RCU_IRC8M = RCU_REGIDX_BIT(CTL_REG_OFFSET, 0U), /*!< IRC8M */ - RCU_IRC48M = RCU_REGIDX_BIT(ADDCTL_REG_OFFSET, 16U), /*!< IRC48M */ - RCU_IRC40K = RCU_REGIDX_BIT(RSTSCK_REG_OFFSET, 0U), /*!< IRC40K */ - RCU_PLL_CK = RCU_REGIDX_BIT(CTL_REG_OFFSET, 24U), /*!< PLL */ -#ifdef GD32F10X_CL - RCU_PLL1_CK = RCU_REGIDX_BIT(CTL_REG_OFFSET, 26U), /*!< PLL1 */ - RCU_PLL2_CK = RCU_REGIDX_BIT(CTL_REG_OFFSET, 28U), /*!< PLL2 */ -#endif /* GD32F10X_CL */ -} rcu_osci_type_enum; - -/* rcu clock frequency */ -typedef enum { - CK_SYS = 0, /*!< system clock */ - CK_AHB, /*!< AHB clock */ - CK_APB1, /*!< APB1 clock */ - CK_APB2, /*!< APB2 clock */ -} rcu_clock_freq_enum; - -/* RCU_CFG0 register bit define */ -/* system clock source select */ -#define CFG0_SCS(regval) (BITS(0,1) & ((uint32_t)(regval) << 0)) -#define RCU_CKSYSSRC_IRC8M CFG0_SCS(0) /*!< system clock source select IRC8M */ -#define RCU_CKSYSSRC_HXTAL CFG0_SCS(1) /*!< system clock source select HXTAL */ -#define RCU_CKSYSSRC_PLL CFG0_SCS(2) /*!< system clock source select PLL */ - -/* system clock source select status */ -#define CFG0_SCSS(regval) (BITS(2,3) & ((uint32_t)(regval) << 2)) -#define RCU_SCSS_IRC8M CFG0_SCSS(0) /*!< system clock source select IRC8M */ -#define RCU_SCSS_HXTAL CFG0_SCSS(1) /*!< system clock source select HXTAL */ -#define RCU_SCSS_PLL CFG0_SCSS(2) /*!< system clock source select PLLP */ - -/* AHB prescaler selection */ -#define CFG0_AHBPSC(regval) (BITS(4,7) & ((uint32_t)(regval) << 4)) -#define RCU_AHB_CKSYS_DIV1 CFG0_AHBPSC(0) /*!< AHB prescaler select CK_SYS */ -#define RCU_AHB_CKSYS_DIV2 CFG0_AHBPSC(8) /*!< AHB prescaler select CK_SYS/2 */ -#define RCU_AHB_CKSYS_DIV4 CFG0_AHBPSC(9) /*!< AHB prescaler select CK_SYS/4 */ -#define RCU_AHB_CKSYS_DIV8 CFG0_AHBPSC(10) /*!< AHB prescaler select CK_SYS/8 */ -#define RCU_AHB_CKSYS_DIV16 CFG0_AHBPSC(11) /*!< AHB prescaler select CK_SYS/16 */ -#define RCU_AHB_CKSYS_DIV64 CFG0_AHBPSC(12) /*!< AHB prescaler select CK_SYS/64 */ -#define RCU_AHB_CKSYS_DIV128 CFG0_AHBPSC(13) /*!< AHB prescaler select CK_SYS/128 */ -#define RCU_AHB_CKSYS_DIV256 CFG0_AHBPSC(14) /*!< AHB prescaler select CK_SYS/256 */ -#define RCU_AHB_CKSYS_DIV512 CFG0_AHBPSC(15) /*!< AHB prescaler select CK_SYS/512 */ - -/* APB1 prescaler selection */ -#define CFG0_APB1PSC(regval) (BITS(8,10) & ((uint32_t)(regval) << 8)) -#define RCU_APB1_CKAHB_DIV1 CFG0_APB1PSC(0) /*!< APB1 prescaler select CK_AHB */ -#define RCU_APB1_CKAHB_DIV2 CFG0_APB1PSC(4) /*!< APB1 prescaler select CK_AHB/2 */ -#define RCU_APB1_CKAHB_DIV4 CFG0_APB1PSC(5) /*!< APB1 prescaler select CK_AHB/4 */ -#define RCU_APB1_CKAHB_DIV8 CFG0_APB1PSC(6) /*!< APB1 prescaler select CK_AHB/8 */ -#define RCU_APB1_CKAHB_DIV16 CFG0_APB1PSC(7) /*!< APB1 prescaler select CK_AHB/16 */ - -/* APB2 prescaler selection */ -#define CFG0_APB2PSC(regval) (BITS(11,13) & ((uint32_t)(regval) << 11)) -#define RCU_APB2_CKAHB_DIV1 CFG0_APB2PSC(0) /*!< APB2 prescaler select CK_AHB */ -#define RCU_APB2_CKAHB_DIV2 CFG0_APB2PSC(4) /*!< APB2 prescaler select CK_AHB/2 */ -#define RCU_APB2_CKAHB_DIV4 CFG0_APB2PSC(5) /*!< APB2 prescaler select CK_AHB/4 */ -#define RCU_APB2_CKAHB_DIV8 CFG0_APB2PSC(6) /*!< APB2 prescaler select CK_AHB/8 */ -#define RCU_APB2_CKAHB_DIV16 CFG0_APB2PSC(7) /*!< APB2 prescaler select CK_AHB/16 */ - -/* ADC prescaler select */ -#define RCU_CKADC_CKAPB2_DIV2 ((uint32_t)0x00000000U) /*!< ADC prescaler select CK_APB2/2 */ -#define RCU_CKADC_CKAPB2_DIV4 ((uint32_t)0x00000001U) /*!< ADC prescaler select CK_APB2/4 */ -#define RCU_CKADC_CKAPB2_DIV6 ((uint32_t)0x00000002U) /*!< ADC prescaler select CK_APB2/6 */ -#define RCU_CKADC_CKAPB2_DIV8 ((uint32_t)0x00000003U) /*!< ADC prescaler select CK_APB2/8 */ -#define RCU_CKADC_CKAPB2_DIV12 ((uint32_t)0x00000005U) /*!< ADC prescaler select CK_APB2/12 */ -#define RCU_CKADC_CKAPB2_DIV16 ((uint32_t)0x00000007U) /*!< ADC prescaler select CK_APB2/16 */ -#define RCU_CKADC_CKAHB_DIV5 ((uint32_t)0x00000008U) /*!< ADC prescaler select CK_AHB/5 */ -#define RCU_CKADC_CKAHB_DIV6 ((uint32_t)0x00000009U) /*!< ADC prescaler select CK_AHB/6 */ -#define RCU_CKADC_CKAHB_DIV10 ((uint32_t)0x0000000AU) /*!< ADC prescaler select CK_AHB/10 */ -#define RCU_CKADC_CKAHB_DIV20 ((uint32_t)0x0000000BU) /*!< ADC prescaler select CK_AHB/20 */ - -/* PLL clock source selection */ -#define RCU_PLLSRC_IRC8M_DIV2 ((uint32_t)0x00000000U) /*!< IRC8M/2 clock selected as source clock of PLL */ -#define RCU_PLLSRC_HXTAL_IRC48M RCU_CFG0_PLLSEL /*!< HXTAL or IRC48M selected as source clock of PLL */ - -/* PLL clock multiplication factor */ -#define PLLMF_4 RCU_CFG0_PLLMF_4 /* bit 4 of PLLMF */ -#define PLLMF_5 RCU_CFG0_PLLMF_5 /* bit 5 of PLLMF */ -#define PLLMF_4_5 (PLLMF_4 | PLLMF_5) /* bit 4 and 5 of PLLMF */ - -#define CFG0_PLLMF(regval) (BITS(18,21) & ((uint32_t)(regval) << 18)) -#define RCU_PLL_MUL2 CFG0_PLLMF(0) /*!< PLL source clock multiply by 2 */ -#define RCU_PLL_MUL3 CFG0_PLLMF(1) /*!< PLL source clock multiply by 3 */ -#define RCU_PLL_MUL4 CFG0_PLLMF(2) /*!< PLL source clock multiply by 4 */ -#define RCU_PLL_MUL5 CFG0_PLLMF(3) /*!< PLL source clock multiply by 5 */ -#define RCU_PLL_MUL6 CFG0_PLLMF(4) /*!< PLL source clock multiply by 6 */ -#define RCU_PLL_MUL7 CFG0_PLLMF(5) /*!< PLL source clock multiply by 7 */ -#define RCU_PLL_MUL8 CFG0_PLLMF(6) /*!< PLL source clock multiply by 8 */ -#define RCU_PLL_MUL9 CFG0_PLLMF(7) /*!< PLL source clock multiply by 9 */ -#define RCU_PLL_MUL10 CFG0_PLLMF(8) /*!< PLL source clock multiply by 10 */ -#define RCU_PLL_MUL11 CFG0_PLLMF(9) /*!< PLL source clock multiply by 11 */ -#define RCU_PLL_MUL12 CFG0_PLLMF(10) /*!< PLL source clock multiply by 12 */ -#define RCU_PLL_MUL13 CFG0_PLLMF(11) /*!< PLL source clock multiply by 13 */ -#define RCU_PLL_MUL14 CFG0_PLLMF(12) /*!< PLL source clock multiply by 14 */ -#if(defined(GD32F10X_HD) || defined(GD32F10X_XD)) - #define RCU_PLL_MUL15 CFG0_PLLMF(13) /*!< PLL source clock multiply by 15 */ -#elif defined(GD32F10X_CL) - #define RCU_PLL_MUL6_5 CFG0_PLLMF(13) /*!< PLL source clock multiply by 6.5 */ -#endif /* GD32F10X_HD and GD32F10X_XD */ -#define RCU_PLL_MUL16 CFG0_PLLMF(14) /*!< PLL source clock multiply by 16 */ -#define RCU_PLL_MUL17 (PLLMF_4 | CFG0_PLLMF(0)) /*!< PLL source clock multiply by 17 */ -#define RCU_PLL_MUL18 (PLLMF_4 | CFG0_PLLMF(1)) /*!< PLL source clock multiply by 18 */ -#define RCU_PLL_MUL19 (PLLMF_4 | CFG0_PLLMF(2)) /*!< PLL source clock multiply by 19 */ -#define RCU_PLL_MUL20 (PLLMF_4 | CFG0_PLLMF(3)) /*!< PLL source clock multiply by 20 */ -#define RCU_PLL_MUL21 (PLLMF_4 | CFG0_PLLMF(4)) /*!< PLL source clock multiply by 21 */ -#define RCU_PLL_MUL22 (PLLMF_4 | CFG0_PLLMF(5)) /*!< PLL source clock multiply by 22 */ -#define RCU_PLL_MUL23 (PLLMF_4 | CFG0_PLLMF(6)) /*!< PLL source clock multiply by 23 */ -#define RCU_PLL_MUL24 (PLLMF_4 | CFG0_PLLMF(7)) /*!< PLL source clock multiply by 24 */ -#define RCU_PLL_MUL25 (PLLMF_4 | CFG0_PLLMF(8)) /*!< PLL source clock multiply by 25 */ -#define RCU_PLL_MUL26 (PLLMF_4 | CFG0_PLLMF(9)) /*!< PLL source clock multiply by 26 */ -#define RCU_PLL_MUL27 (PLLMF_4 | CFG0_PLLMF(10)) /*!< PLL source clock multiply by 27 */ -#define RCU_PLL_MUL28 (PLLMF_4 | CFG0_PLLMF(11)) /*!< PLL source clock multiply by 28 */ -#define RCU_PLL_MUL29 (PLLMF_4 | CFG0_PLLMF(12)) /*!< PLL source clock multiply by 29 */ -#define RCU_PLL_MUL30 (PLLMF_4 | CFG0_PLLMF(13)) /*!< PLL source clock multiply by 30 */ -#define RCU_PLL_MUL31 (PLLMF_4 | CFG0_PLLMF(14)) /*!< PLL source clock multiply by 31 */ -#define RCU_PLL_MUL32 (PLLMF_4 | CFG0_PLLMF(15)) /*!< PLL source clock multiply by 32 */ -#define RCU_PLL_MUL33 (PLLMF_5 | CFG0_PLLMF(0)) /*!< PLL source clock multiply by 33 */ -#define RCU_PLL_MUL34 (PLLMF_5 | CFG0_PLLMF(1)) /*!< PLL source clock multiply by 34 */ -#define RCU_PLL_MUL35 (PLLMF_5 | CFG0_PLLMF(2)) /*!< PLL source clock multiply by 35 */ -#define RCU_PLL_MUL36 (PLLMF_5 | CFG0_PLLMF(3)) /*!< PLL source clock multiply by 36 */ -#define RCU_PLL_MUL37 (PLLMF_5 | CFG0_PLLMF(4)) /*!< PLL source clock multiply by 37 */ -#define RCU_PLL_MUL38 (PLLMF_5 | CFG0_PLLMF(5)) /*!< PLL source clock multiply by 38 */ -#define RCU_PLL_MUL39 (PLLMF_5 | CFG0_PLLMF(6)) /*!< PLL source clock multiply by 39 */ -#define RCU_PLL_MUL40 (PLLMF_5 | CFG0_PLLMF(7)) /*!< PLL source clock multiply by 40 */ -#define RCU_PLL_MUL41 (PLLMF_5 | CFG0_PLLMF(8)) /*!< PLL source clock multiply by 41 */ -#define RCU_PLL_MUL42 (PLLMF_5 | CFG0_PLLMF(9)) /*!< PLL source clock multiply by 42 */ -#define RCU_PLL_MUL43 (PLLMF_5 | CFG0_PLLMF(10)) /*!< PLL source clock multiply by 43 */ -#define RCU_PLL_MUL44 (PLLMF_5 | CFG0_PLLMF(11)) /*!< PLL source clock multiply by 44 */ -#define RCU_PLL_MUL45 (PLLMF_5 | CFG0_PLLMF(12)) /*!< PLL source clock multiply by 45 */ -#define RCU_PLL_MUL46 (PLLMF_5 | CFG0_PLLMF(13)) /*!< PLL source clock multiply by 46 */ -#define RCU_PLL_MUL47 (PLLMF_5 | CFG0_PLLMF(14)) /*!< PLL source clock multiply by 47 */ -#define RCU_PLL_MUL48 (PLLMF_5 | CFG0_PLLMF(15)) /*!< PLL source clock multiply by 48 */ -#define RCU_PLL_MUL49 (PLLMF_4_5 | CFG0_PLLMF(0)) /*!< PLL source clock multiply by 49 */ -#define RCU_PLL_MUL50 (PLLMF_4_5 | CFG0_PLLMF(1)) /*!< PLL source clock multiply by 50 */ -#define RCU_PLL_MUL51 (PLLMF_4_5 | CFG0_PLLMF(2)) /*!< PLL source clock multiply by 51 */ -#define RCU_PLL_MUL52 (PLLMF_4_5 | CFG0_PLLMF(3)) /*!< PLL source clock multiply by 52 */ -#define RCU_PLL_MUL53 (PLLMF_4_5 | CFG0_PLLMF(4)) /*!< PLL source clock multiply by 53 */ -#define RCU_PLL_MUL54 (PLLMF_4_5 | CFG0_PLLMF(5)) /*!< PLL source clock multiply by 54 */ -#define RCU_PLL_MUL55 (PLLMF_4_5 | CFG0_PLLMF(6)) /*!< PLL source clock multiply by 55 */ -#define RCU_PLL_MUL56 (PLLMF_4_5 | CFG0_PLLMF(7)) /*!< PLL source clock multiply by 56 */ -#define RCU_PLL_MUL57 (PLLMF_4_5 | CFG0_PLLMF(8)) /*!< PLL source clock multiply by 57 */ -#define RCU_PLL_MUL58 (PLLMF_4_5 | CFG0_PLLMF(9)) /*!< PLL source clock multiply by 58 */ -#define RCU_PLL_MUL59 (PLLMF_4_5 | CFG0_PLLMF(10)) /*!< PLL source clock multiply by 59 */ -#define RCU_PLL_MUL60 (PLLMF_4_5 | CFG0_PLLMF(11)) /*!< PLL source clock multiply by 60 */ -#define RCU_PLL_MUL61 (PLLMF_4_5 | CFG0_PLLMF(12)) /*!< PLL source clock multiply by 61 */ -#define RCU_PLL_MUL62 (PLLMF_4_5 | CFG0_PLLMF(13)) /*!< PLL source clock multiply by 62 */ -#define RCU_PLL_MUL63 (PLLMF_4_5 | CFG0_PLLMF(14)) /*!< PLL source clock multiply by 63 */ - -#if(defined(GD32F10X_HD) || defined(GD32F10X_XD)) - #define USBPSC_2 RCU_CFG0_USBDPSC_2 -#elif defined(GD32F10X_CL) - #define USBPSC_2 RCU_CFG0_USBFSPSC_2 -#endif /* GD32F10X_HD and GD32F10X_XD */ - -/* USBD/USBFS prescaler select */ -#define CFG0_USBPSC(regval) (BITS(22,23) & ((uint32_t)(regval) << 22)) -#define RCU_CKUSB_CKPLL_DIV1_5 CFG0_USBPSC(0) /*!< USBD/USBFS prescaler select CK_PLL/1.5 */ -#define RCU_CKUSB_CKPLL_DIV1 CFG0_USBPSC(1) /*!< USBD/USBFS prescaler select CK_PLL/1 */ -#define RCU_CKUSB_CKPLL_DIV2_5 CFG0_USBPSC(2) /*!< USBD/USBFS prescaler select CK_PLL/2.5 */ -#define RCU_CKUSB_CKPLL_DIV2 CFG0_USBPSC(3) /*!< USBD/USBFS prescaler select CK_PLL/2 */ -#define RCU_CKUSB_CKPLL_DIV3 (USBPSC_2 |CFG0_USBPSC(0)) /*!< USBD/USBFS prescaler select CK_PLL/3.5 */ -#define RCU_CKUSB_CKPLL_DIV3_5 (USBPSC_2 |CFG0_USBPSC(1)) /*!< USBD/USBFS prescaler select CK_PLL/3 */ -#define RCU_CKUSB_CKPLL_DIV4 (USBPSC_2 |CFG0_USBPSC(2)) /*!< USBD/USBFS prescaler select CK_PLL/4 */ - -/* CKOUT0 Clock source selection */ -#define CFG0_CKOUT0SEL(regval) (BITS(24,27) & ((uint32_t)(regval) << 24)) -#define RCU_CKOUT0SRC_NONE CFG0_CKOUT0SEL(0) /*!< no clock selected */ -#define RCU_CKOUT0SRC_CKSYS CFG0_CKOUT0SEL(4) /*!< system clock selected */ -#define RCU_CKOUT0SRC_IRC8M CFG0_CKOUT0SEL(5) /*!< internal 8M RC oscillator clock selected */ -#define RCU_CKOUT0SRC_HXTAL CFG0_CKOUT0SEL(6) /*!< high speed crystal oscillator clock (HXTAL) selected */ -#define RCU_CKOUT0SRC_CKPLL_DIV2 CFG0_CKOUT0SEL(7) /*!< CK_PLL/2 clock selected */ -#ifdef GD32F10X_CL - #define RCU_CKOUT0SRC_CKPLL1 CFG0_CKOUT0SEL(8) /*!< CK_PLL1 clock selected */ - #define RCU_CKOUT0SRC_CKPLL2_DIV2 CFG0_CKOUT0SEL(9) /*!< CK_PLL2/2 clock selected */ - #define RCU_CKOUT0SRC_EXT1 CFG0_CKOUT0SEL(10) /*!< EXT1 selected, to provide the external clock for ENET */ - #define RCU_CKOUT0SRC_CKPLL2 CFG0_CKOUT0SEL(11) /*!< CK_PLL2 clock selected */ -#endif /* GD32F10X_CL */ - -/* LXTAL drive capability */ -#define BDCTL_LXTALDRI(regval) (BITS(3,4) & ((uint32_t)(regval) << 3)) -#define RCU_LXTAL_LOWDRI BDCTL_LXTALDRI(0) /*!< lower driving capability */ -#define RCU_LXTAL_MED_LOWDRI BDCTL_LXTALDRI(1) /*!< medium low driving capability */ -#define RCU_LXTAL_MED_HIGHDRI BDCTL_LXTALDRI(2) /*!< medium high driving capability */ -#define RCU_LXTAL_HIGHDRI BDCTL_LXTALDRI(3) /*!< higher driving capability */ - -/* RTC clock entry selection */ -#define BDCTL_RTCSRC(regval) (BITS(8,9) & ((uint32_t)(regval) << 8)) -#define RCU_RTCSRC_NONE BDCTL_RTCSRC(0) /*!< no clock selected */ -#define RCU_RTCSRC_LXTAL BDCTL_RTCSRC(1) /*!< RTC source clock select LXTAL */ -#define RCU_RTCSRC_IRC40K BDCTL_RTCSRC(2) /*!< RTC source clock select IRC40K */ -#define RCU_RTCSRC_HXTAL_DIV_128 BDCTL_RTCSRC(3) /*!< RTC source clock select HXTAL/128 */ - -/* PREDV0 division factor */ -#define CFG1_PREDV0(regval) (BITS(0,3) & ((uint32_t)(regval) << 0)) -#define RCU_PREDV0_DIV1 CFG1_PREDV0(0) /*!< PREDV0 input source clock not divided */ -#define RCU_PREDV0_DIV2 CFG1_PREDV0(1) /*!< PREDV0 input source clock divided by 2 */ -#define RCU_PREDV0_DIV3 CFG1_PREDV0(2) /*!< PREDV0 input source clock divided by 3 */ -#define RCU_PREDV0_DIV4 CFG1_PREDV0(3) /*!< PREDV0 input source clock divided by 4 */ -#define RCU_PREDV0_DIV5 CFG1_PREDV0(4) /*!< PREDV0 input source clock divided by 5 */ -#define RCU_PREDV0_DIV6 CFG1_PREDV0(5) /*!< PREDV0 input source clock divided by 6 */ -#define RCU_PREDV0_DIV7 CFG1_PREDV0(6) /*!< PREDV0 input source clock divided by 7 */ -#define RCU_PREDV0_DIV8 CFG1_PREDV0(7) /*!< PREDV0 input source clock divided by 8 */ -#define RCU_PREDV0_DIV9 CFG1_PREDV0(8) /*!< PREDV0 input source clock divided by 9 */ -#define RCU_PREDV0_DIV10 CFG1_PREDV0(9) /*!< PREDV0 input source clock divided by 10 */ -#define RCU_PREDV0_DIV11 CFG1_PREDV0(10) /*!< PREDV0 input source clock divided by 11 */ -#define RCU_PREDV0_DIV12 CFG1_PREDV0(11) /*!< PREDV0 input source clock divided by 12 */ -#define RCU_PREDV0_DIV13 CFG1_PREDV0(12) /*!< PREDV0 input source clock divided by 13 */ -#define RCU_PREDV0_DIV14 CFG1_PREDV0(13) /*!< PREDV0 input source clock divided by 14 */ -#define RCU_PREDV0_DIV15 CFG1_PREDV0(14) /*!< PREDV0 input source clock divided by 15 */ -#define RCU_PREDV0_DIV16 CFG1_PREDV0(15) /*!< PREDV0 input source clock divided by 16 */ - -/* PREDV1 division factor */ -#define CFG1_PREDV1(regval) (BITS(4,7) & ((uint32_t)(regval) << 4)) -#define RCU_PREDV1_DIV1 CFG1_PREDV1(0) /*!< PREDV1 input source clock not divided */ -#define RCU_PREDV1_DIV2 CFG1_PREDV1(1) /*!< PREDV1 input source clock divided by 2 */ -#define RCU_PREDV1_DIV3 CFG1_PREDV1(2) /*!< PREDV1 input source clock divided by 3 */ -#define RCU_PREDV1_DIV4 CFG1_PREDV1(3) /*!< PREDV1 input source clock divided by 4 */ -#define RCU_PREDV1_DIV5 CFG1_PREDV1(4) /*!< PREDV1 input source clock divided by 5 */ -#define RCU_PREDV1_DIV6 CFG1_PREDV1(5) /*!< PREDV1 input source clock divided by 6 */ -#define RCU_PREDV1_DIV7 CFG1_PREDV1(6) /*!< PREDV1 input source clock divided by 7 */ -#define RCU_PREDV1_DIV8 CFG1_PREDV1(7) /*!< PREDV1 input source clock divided by 8 */ -#define RCU_PREDV1_DIV9 CFG1_PREDV1(8) /*!< PREDV1 input source clock divided by 9 */ -#define RCU_PREDV1_DIV10 CFG1_PREDV1(9) /*!< PREDV1 input source clock divided by 10 */ -#define RCU_PREDV1_DIV11 CFG1_PREDV1(10) /*!< PREDV1 input source clock divided by 11 */ -#define RCU_PREDV1_DIV12 CFG1_PREDV1(11) /*!< PREDV1 input source clock divided by 12 */ -#define RCU_PREDV1_DIV13 CFG1_PREDV1(12) /*!< PREDV1 input source clock divided by 13 */ -#define RCU_PREDV1_DIV14 CFG1_PREDV1(13) /*!< PREDV1 input source clock divided by 14 */ -#define RCU_PREDV1_DIV15 CFG1_PREDV1(14) /*!< PREDV1 input source clock divided by 15 */ -#define RCU_PREDV1_DIV16 CFG1_PREDV1(15) /*!< PREDV1 input source clock divided by 16 */ - -/* PLL1 clock multiplication factor */ -#define CFG1_PLL1MF(regval) (BITS(8,11) & ((uint32_t)(regval) << 8)) -#define RCU_PLL1_MUL8 CFG1_PLL1MF(6) /*!< PLL1 source clock multiply by 8 */ -#define RCU_PLL1_MUL9 CFG1_PLL1MF(7) /*!< PLL1 source clock multiply by 9 */ -#define RCU_PLL1_MUL10 CFG1_PLL1MF(8) /*!< PLL1 source clock multiply by 10 */ -#define RCU_PLL1_MUL11 CFG1_PLL1MF(9) /*!< PLL1 source clock multiply by 11 */ -#define RCU_PLL1_MUL12 CFG1_PLL1MF(10) /*!< PLL1 source clock multiply by 12 */ -#define RCU_PLL1_MUL13 CFG1_PLL1MF(11) /*!< PLL1 source clock multiply by 13 */ -#define RCU_PLL1_MUL14 CFG1_PLL1MF(12) /*!< PLL1 source clock multiply by 14 */ -#define RCU_PLL1_MUL15 CFG1_PLL1MF(13) /*!< PLL1 source clock multiply by 15 */ -#define RCU_PLL1_MUL16 CFG1_PLL1MF(14) /*!< PLL1 source clock multiply by 16 */ -#define RCU_PLL1_MUL20 CFG1_PLL1MF(15) /*!< PLL1 source clock multiply by 20 */ - -/* PLL2 clock multiplication factor */ -#define PLL2MF_4 RCU_CFG1_PLL2MF_4 /* bit 4 of PLL2MF */ - -#define CFG1_PLL2MF(regval) (BITS(12,15) & ((uint32_t)(regval) << 12)) -#define RCU_PLL2_MUL8 CFG1_PLL2MF(6) /*!< PLL2 source clock multiply by 8 */ -#define RCU_PLL2_MUL9 CFG1_PLL2MF(7) /*!< PLL2 source clock multiply by 9 */ -#define RCU_PLL2_MUL10 CFG1_PLL2MF(8) /*!< PLL2 source clock multiply by 10 */ -#define RCU_PLL2_MUL11 CFG1_PLL2MF(9) /*!< PLL2 source clock multiply by 11 */ -#define RCU_PLL2_MUL12 CFG1_PLL2MF(10) /*!< PLL2 source clock multiply by 12 */ -#define RCU_PLL2_MUL13 CFG1_PLL2MF(11) /*!< PLL2 source clock multiply by 13 */ -#define RCU_PLL2_MUL14 CFG1_PLL2MF(12) /*!< PLL2 source clock multiply by 14 */ -#define RCU_PLL2_MUL15 CFG1_PLL2MF(13) /*!< PLL2 source clock multiply by 15 */ -#define RCU_PLL2_MUL16 CFG1_PLL2MF(14) /*!< PLL2 source clock multiply by 16 */ -#define RCU_PLL2_MUL20 CFG1_PLL2MF(15) /*!< PLL2 source clock multiply by 20 */ -#define RCU_PLL2_MUL18 (PLL2MF_4 | CFG1_PLL2MF(0)) /*!< PLL2 source clock multiply by 18 */ -#define RCU_PLL2_MUL19 (PLL2MF_4 | CFG1_PLL2MF(1)) /*!< PLL2 source clock multiply by 19 */ -#define RCU_PLL2_MUL21 (PLL2MF_4 | CFG1_PLL2MF(3)) /*!< PLL2 source clock multiply by 21 */ -#define RCU_PLL2_MUL22 (PLL2MF_4 | CFG1_PLL2MF(4)) /*!< PLL2 source clock multiply by 22 */ -#define RCU_PLL2_MUL23 (PLL2MF_4 | CFG1_PLL2MF(5)) /*!< PLL2 source clock multiply by 23 */ -#define RCU_PLL2_MUL24 (PLL2MF_4 | CFG1_PLL2MF(6)) /*!< PLL2 source clock multiply by 24 */ -#define RCU_PLL2_MUL25 (PLL2MF_4 | CFG1_PLL2MF(7)) /*!< PLL2 source clock multiply by 25 */ -#define RCU_PLL2_MUL26 (PLL2MF_4 | CFG1_PLL2MF(8)) /*!< PLL2 source clock multiply by 26 */ -#define RCU_PLL2_MUL27 (PLL2MF_4 | CFG1_PLL2MF(9)) /*!< PLL2 source clock multiply by 27 */ -#define RCU_PLL2_MUL28 (PLL2MF_4 | CFG1_PLL2MF(10)) /*!< PLL2 source clock multiply by 28 */ -#define RCU_PLL2_MUL29 (PLL2MF_4 | CFG1_PLL2MF(11)) /*!< PLL2 source clock multiply by 29 */ -#define RCU_PLL2_MUL30 (PLL2MF_4 | CFG1_PLL2MF(12)) /*!< PLL2 source clock multiply by 30 */ -#define RCU_PLL2_MUL31 (PLL2MF_4 | CFG1_PLL2MF(13)) /*!< PLL2 source clock multiply by 31 */ -#define RCU_PLL2_MUL32 (PLL2MF_4 | CFG1_PLL2MF(14)) /*!< PLL2 source clock multiply by 32 */ -#define RCU_PLL2_MUL40 (PLL2MF_4 | CFG1_PLL2MF(15)) /*!< PLL2 source clock multiply by 40 */ - -#ifdef GD32F10X_CL - /* PREDV0 input clock source selection */ - #define RCU_PREDV0SRC_HXTAL_IRC48M ((uint32_t)0x00000000U) /*!< HXTAL or IRC48M selected as PREDV0 input source clock */ - #define RCU_PREDV0SRC_CKPLL1 RCU_CFG1_PREDV0SEL /*!< CK_PLL1 selected as PREDV0 input source clock */ - - /* I2S1 clock source selection */ - #define RCU_I2S1SRC_CKSYS ((uint32_t)0x00000000U) /*!< system clock selected as I2S1 source clock */ - #define RCU_I2S1SRC_CKPLL2_MUL2 RCU_CFG1_I2S1SEL /*!< (CK_PLL2 x 2) selected as I2S1 source clock */ - - /* I2S2 clock source selection */ - #define RCU_I2S2SRC_CKSYS ((uint32_t)0x00000000U) /*!< system clock selected as I2S2 source clock */ - #define RCU_I2S2SRC_CKPLL2_MUL2 RCU_CFG1_I2S2SEL /*!< (CK_PLL2 x 2) selected as I2S2 source clock */ -#endif /* GD32F10X_CL */ - -/* PLL input clock source selection */ -#define RCU_PLLPRESRC_HXTAL ((uint32_t)0x00000000U) /*!< HXTAL selected as PLL source clock */ -#define RCU_PLLPRESRC_IRC48M RCU_CFG1_PLLPRESEL /*!< CK_PLL selected as PREDV0 input source clock */ - -/* deep-sleep mode voltage */ -#define DSV_DSLPVS(regval) (BITS(0,2) & ((uint32_t)(regval) << 0)) -#define RCU_DEEPSLEEP_V_1_0 DSV_DSLPVS(0) /*!< core voltage is 1.0V in deep-sleep mode */ -#define RCU_DEEPSLEEP_V_0_9 DSV_DSLPVS(1) /*!< core voltage is 0.9V in deep-sleep mode */ -#define RCU_DEEPSLEEP_V_0_8 DSV_DSLPVS(2) /*!< core voltage is 0.8V in deep-sleep mode */ -#define RCU_DEEPSLEEP_V_0_7 DSV_DSLPVS(3) /*!< core voltage is 0.7V in deep-sleep mode */ - -/* 48MHz clock selection */ -#define RCU_CK48MSRC_CKPLL ((uint32_t)0x00000000U) /*!< use CK_PLL clock */ -#define RCU_CK48MSRC_IRC48M RCU_ADDCTL_CK48MSEL /*!< select IRC48M clock */ - -/* function declarations */ -/* deinitialize the RCU */ -void rcu_deinit(void); -/* enable the peripherals clock */ -void rcu_periph_clock_enable(rcu_periph_enum periph); -/* disable the peripherals clock */ -void rcu_periph_clock_disable(rcu_periph_enum periph); -/* enable the peripherals clock when sleep mode */ -void rcu_periph_clock_sleep_enable(rcu_periph_sleep_enum periph); -/* disable the peripherals clock when sleep mode */ -void rcu_periph_clock_sleep_disable(rcu_periph_sleep_enum periph); -/* reset the peripherals */ -void rcu_periph_reset_enable(rcu_periph_reset_enum periph_reset); -/* disable reset the peripheral */ -void rcu_periph_reset_disable(rcu_periph_reset_enum periph_reset); -/* reset the BKP domain */ -void rcu_bkp_reset_enable(void); -/* disable the BKP domain reset */ -void rcu_bkp_reset_disable(void); - -/* configure the system clock source */ -void rcu_system_clock_source_config(uint32_t ck_sys); -/* get the system clock source */ -uint32_t rcu_system_clock_source_get(void); -/* configure the AHB prescaler selection */ -void rcu_ahb_clock_config(uint32_t ck_ahb); -/* configure the APB1 prescaler selection */ -void rcu_apb1_clock_config(uint32_t ck_apb1); -/* configure the APB2 prescaler selection */ -void rcu_apb2_clock_config(uint32_t ck_apb2); -/* configure the CK_OUT0 clock source and divider */ -void rcu_ckout0_config(uint32_t ckout0_src); -/* configure the PLL clock source selection and PLL multiply factor */ -void rcu_pll_config(uint32_t pll_src, uint32_t pll_mul); -/* configure the PLL clock source preselection */ -void rcu_pllpresel_config(uint32_t pll_presel); -#if(defined(GD32F10X_HD) || defined(GD32F10X_XD)) - /* configure the PREDV0 division factor and clock source */ - void rcu_predv0_config(uint32_t predv0_div); -#elif defined(GD32F10X_CL) - /* configure the PREDV0 division factor and clock source */ - void rcu_predv0_config(uint32_t predv0_source, uint32_t predv0_div); - /* configure the PREDV1 division factor */ - void rcu_predv1_config(uint32_t predv1_div); - /* configure the PLL1 clock */ - void rcu_pll1_config(uint32_t pll_mul); - /* configure the PLL2 clock */ - void rcu_pll2_config(uint32_t pll_mul); -#endif /* GD32F10X_HD and GD32F10X_XD */ - -/* configure the ADC division factor */ -void rcu_adc_clock_config(uint32_t adc_psc); -/* configure the USBD/USBFS prescaler factor */ -void rcu_usb_clock_config(uint32_t usb_psc); -/* configure the RTC clock source selection */ -void rcu_rtc_clock_config(uint32_t rtc_clock_source); -#ifdef GD32F10X_CL - /* configure the I2S1 clock source selection */ - void rcu_i2s1_clock_config(uint32_t i2s_clock_source); - /* configure the I2S2 clock source selection */ - void rcu_i2s2_clock_config(uint32_t i2s_clock_source); -#endif /* GD32F10X_CL */ -/* configure the CK48M clock selection */ -void rcu_ck48m_clock_config(uint32_t ck48m_clock_source); - - -/* get the clock stabilization and periphral reset flags */ -FlagStatus rcu_flag_get(rcu_flag_enum flag); -/* clear the reset flag */ -void rcu_all_reset_flag_clear(void); -/* get the clock stabilization interrupt and ckm flags */ -FlagStatus rcu_interrupt_flag_get(rcu_int_flag_enum int_flag); -/* clear the interrupt flags */ -void rcu_interrupt_flag_clear(rcu_int_flag_clear_enum int_flag_clear); -/* enable the stabilization interrupt */ -void rcu_interrupt_enable(rcu_int_enum stab_int); -/* disable the stabilization interrupt */ -void rcu_interrupt_disable(rcu_int_enum stab_int); - -/* configure the LXTAL drive capability */ -void rcu_lxtal_drive_capability_config(uint32_t lxtal_dricap); -/* wait for oscillator stabilization flags is SET or oscillator startup is timeout */ -ErrStatus rcu_osci_stab_wait(rcu_osci_type_enum osci); -/* turn on the oscillator */ -void rcu_osci_on(rcu_osci_type_enum osci); -/* turn off the oscillator */ -void rcu_osci_off(rcu_osci_type_enum osci); -/* enable the oscillator bypass mode, HXTALEN or LXTALEN must be reset before it */ -void rcu_osci_bypass_mode_enable(rcu_osci_type_enum osci); -/* disable the oscillator bypass mode, HXTALEN or LXTALEN must be reset before it */ -void rcu_osci_bypass_mode_disable(rcu_osci_type_enum osci); -/* enable the HXTAL clock monitor */ -void rcu_hxtal_clock_monitor_enable(void); -/* disable the HXTAL clock monitor */ -void rcu_hxtal_clock_monitor_disable(void); - -/* set the IRC8M adjust value */ -void rcu_irc8m_adjust_value_set(uint32_t irc8m_adjval); - -/* set the deep sleep mode voltage */ -void rcu_deepsleep_voltage_set(uint32_t dsvol); - -/* get the system clock, bus and peripheral clock frequency */ -uint32_t rcu_clock_freq_get(rcu_clock_freq_enum clock); - -#endif /* GD32F10X_RCU_H */ diff --git a/bsp/gd32103c-eval/Libraries/GD32F1xx_standard_peripheral/Include/gd32f10x_rtc.h b/bsp/gd32103c-eval/Libraries/GD32F1xx_standard_peripheral/Include/gd32f10x_rtc.h deleted file mode 100644 index 65d57f06c2..0000000000 --- a/bsp/gd32103c-eval/Libraries/GD32F1xx_standard_peripheral/Include/gd32f10x_rtc.h +++ /dev/null @@ -1,92 +0,0 @@ -/** - ****************************************************************************** - * @brief RTC header file of the firmware library. - ****************************************************************************** - */ - -/* Define to prevent recursive inclusion -------------------------------------*/ -#ifndef __GD32F10X_RTC_H -#define __GD32F10X_RTC_H - -#ifdef __cplusplus -extern "C" { -#endif - -/* Includes ------------------------------------------------------------------*/ -#include "gd32f10x.h" - -/** @addtogroup GD32F10x_Firmware - * @{ - */ - -/** @addtogroup RTC - * @{ - */ - -/** @defgroup RTC_Exported_Defines - * @{ - */ - -/** @defgroup RTC_Interrupt_Def - * @{ - */ -#define RTC_INT_OVF ((uint16_t)0x0004) /*!< Overflow interrupt */ -#define RTC_INT_AF ((uint16_t)0x0002) /*!< Alarm interrupt */ -#define RTC_INT_SF ((uint16_t)0x0001) /*!< Second interrupt */ - -/** - * @} - */ - -/** @defgroup RTC_Interrupts_Flags - * @{ - */ -#define RTC_FLAG_LWOFF ((uint16_t)0x0020) /*!< Last write operation finished flag */ -#define RTC_FLAG_RSF ((uint16_t)0x0008) /*!< Registers Synchronized flag */ -#define RTC_FLAG_OVF ((uint16_t)0x0004) /*!< Overflow flag */ -#define RTC_FLAG_AF ((uint16_t)0x0002) /*!< Alarm flag */ -#define RTC_FLAG_SF ((uint16_t)0x0001) /*!< Second flag */ - -/** - * @} - */ - -/** - * @} - */ - -/** @defgroup RTC_Exported_Functions - * @{ - */ -void RTC_INT_Enable(uint16_t RTC_int, TypeState NewValue); -void RTC_EnterConfigMode(void); -void RTC_ExitConfigMode(void); -uint32_t RTC_GetCounter(void); -void RTC_SetCounter(uint32_t CounterValue); -void RTC_SetPrescaler(uint32_t PrescalerValue); -void RTC_SetAlarm(uint32_t AlarmTime); -uint32_t RTC_GetDividerValue(void); -void RTC_WaitLWOFF(void); -void RTC_WaitRSF(void); -TypeState RTC_GetBitState(uint16_t RTC_flag); -void RTC_ClearBitState(uint16_t RTC_flag); -TypeState RTC_GetIntBitState(uint16_t RTC_INT); -void RTC_ClearIntBitState(uint16_t RTC_INT); - -/** - * @} - */ - -#ifdef __cplusplus -} -#endif - -#endif /*__GD32F10X_RTC_H */ - -/** - * @} - */ - -/** - * @} - */ diff --git a/bsp/gd32103c-eval/Libraries/GD32F1xx_standard_peripheral/Include/gd32f10x_sdio.h b/bsp/gd32103c-eval/Libraries/GD32F1xx_standard_peripheral/Include/gd32f10x_sdio.h deleted file mode 100644 index 16c4d97b12..0000000000 --- a/bsp/gd32103c-eval/Libraries/GD32F1xx_standard_peripheral/Include/gd32f10x_sdio.h +++ /dev/null @@ -1,369 +0,0 @@ -/** - ****************************************************************************** - * @brief SDIO header file of the firmware library - ****************************************************************************** - */ - -/* Define to prevent recursive inclusion -------------------------------------*/ -#ifndef __GD32F10X_SDIO_H -#define __GD32F10X_SDIO_H - -#ifdef __cplusplus -extern "C" { -#endif - -/* Includes ------------------------------------------------------------------*/ -#include "gd32f10x.h" - -/** @addtogroup GD32F10x_Firmware - * @{ - */ - -/** @addtogroup SDIO - * @{ - */ - -/** @defgroup SDIO_Exported_Types - * @{ - */ - -typedef struct { - uint32_t SDIO_ClockEdge; /*!< Configure the SDIO Clock edge on which the bit capture is made. - This parameter can be a value of @ref SDIO_Clock_Edge*/ - uint32_t SDIO_ClockBypassState; /*!< Configure the SDIO Clock divider bypass mode - This parameter can be a value of @ref SDIO_Clock_Bypass_State */ - uint32_t SDIO_ClockPWRSave; /*!< Configure the SDIO Clock output powersave mode when the bus is idle. - This parameter can be a value of @ref SDIO_Clock_Power_Save */ - uint32_t SDIO_BusMode; /*!< Configure the SDIO bus mode. - This parameter can be a value of @ref SDIO_Bus_Mode */ - uint32_t SDIO_HWFlowCtrlState; /*!< Configure the SDIO hardware flow control is enabled or disabled. - This parameter can be a value of @ref SDIO_HW_Flow_Control_State */ - uint8_t SDIO_ClockDiv; /*!< Configure the clock frequency prescaler of the SDIO controller. - This parameter can be a value between 0x00 and 0xFF. */ -} SDIO_InitPara; - -typedef struct { - uint32_t SDIO_CMDParameter; /*!< Configure the SDIO command parameter which is sent to - a card as part of a command message. */ - uint32_t SDIO_CMDIndex; /*!< Configure the SDIO command index. */ - - uint32_t SDIO_ResponseType; /*!< Configure the SDIO response type. - This parameter can be a value of @ref SDIO_Response_Type */ - uint32_t SDIO_WaitINTState; /*!< Configure whether SDIO wait-for-interrupt request is enabled or disabled. - This parameter can be a value of @ref SDIO_Wait_Interrupt_State */ - uint32_t SDIO_CSMState; /*!< Configure SDIO Command state machine (CSM) is enabled or disabled. - This parameter can be a value of @ref SDIO_CSM_State */ -} SDIO_CmdInitPara; - -typedef struct { - uint32_t SDIO_DataTimeOut; /*!< Configure the data timeout period in card bus clock periods. */ - - uint32_t SDIO_DataLength; /*!< Configure the number of data bytes to be transferred. */ - - uint32_t SDIO_DataBlockSize; /*!< Configure the data block size for block transfer. - This parameter can be a value of @ref SDIO_Data_Block_Size */ - uint32_t SDIO_TransDirection; /*!< Configure the data transfer direction, read or write. - This parameter can be a value of @ref SDIO_Transfer_Direction */ - uint32_t SDIO_TransMode; /*!< Configure whether data transfer is in stream or block mode. - This parameter can be a value of @ref SDIO_Transfer_Mode */ - uint32_t SDIO_DSMState; /*!< Configure whether SDIO Data state machine (DSM) is enabled or disabled. - This parameter can be a value of @ref SDIO_DSM_State */ -} SDIO_DataInitPara; - -/** - * @} - */ - -/** @defgroup SDIO_Exported_Constants - * @{ - */ - -/** @defgroup SDIO_Clock_Edge - * @{ - */ -#define SDIO_CLOCKEDGE_RISING ((uint32_t)0x00000000) -#define SDIO_CLOCKEDGE_FALLING ((uint32_t)0x00002000) - -/** - * @} - */ - -/** @defgroup SDIO_Clock_Bypass_State - * @{ - */ -#define SDIO_CLOCKBYPASSSTATE_DISABLE ((uint32_t)0x00000000) -#define SDIO_CLOCKBYPASSSTATE_ENABLE ((uint32_t)0x00000400) - -/** - * @} - */ - -/** @defgroup SDIO_Clock_PWR_Save - * @{ - */ -#define SDIO_CLOCKPWRSAVE_DISABLE ((uint32_t)0x00000000) -#define SDIO_CLOCKPWRSAVE_ENABLE ((uint32_t)0x00000200) - -/** - * @} - */ - -/** @defgroup SDIO_Bus_Mode - * @{ - */ -#define SDIO_BUSMODE_1B ((uint32_t)0x00000000) -#define SDIO_BUSMODE_4B ((uint32_t)0x00000800) -#define SDIO_BUSMODE_8B ((uint32_t)0x00001000) - -/** - * @} - */ - -/** @defgroup SDIO_HW_Flow_Control_State - * @{ - */ - -#define SDIO_HWFLOWCTRLSTATE_DISABLE ((uint32_t)0x00000000) -#define SDIO_HWFLOWCTRLSTATE_ENABLE ((uint32_t)0x00004000) - -/** - * @} - */ - -/** @defgroup SDIO_Power_State - * @{ - */ -#define SDIO_PWRSTATE_OFF ((uint32_t)0x00000000) -#define SDIO_PWRSTATE_ON ((uint32_t)0x00000003) - -/** - * @} - */ - -/** @defgroup SDIO_Interrupt_sources - * @{ - */ -#define SDIO_INT_CCRCFAIL ((uint32_t)0x00000001) -#define SDIO_INT_DTCRCFAIL ((uint32_t)0x00000002) -#define SDIO_INT_CMDTMOUT ((uint32_t)0x00000004) -#define SDIO_INT_DTTMOUT ((uint32_t)0x00000008) -#define SDIO_INT_TXURE ((uint32_t)0x00000010) -#define SDIO_INT_RXORE ((uint32_t)0x00000020) -#define SDIO_INT_CMDREND ((uint32_t)0x00000040) -#define SDIO_INT_CMDSENT ((uint32_t)0x00000080) -#define SDIO_INT_DTEND ((uint32_t)0x00000100) -#define SDIO_INT_STBITE ((uint32_t)0x00000200) -#define SDIO_INT_DTBLKEND ((uint32_t)0x00000400) -#define SDIO_INT_CMDRUN ((uint32_t)0x00000800) -#define SDIO_INT_TXRUN ((uint32_t)0x00001000) -#define SDIO_INT_RXRUN ((uint32_t)0x00002000) -#define SDIO_INT_TXFIFOHE ((uint32_t)0x00004000) -#define SDIO_INT_RXFIFOHF ((uint32_t)0x00008000) -#define SDIO_INT_TXFIFOF ((uint32_t)0x00010000) -#define SDIO_INT_RXFIFOF ((uint32_t)0x00020000) -#define SDIO_INT_TXFIFOE ((uint32_t)0x00040000) -#define SDIO_INT_RXFIFOE ((uint32_t)0x00080000) -#define SDIO_INT_TXDTVAL ((uint32_t)0x00100000) -#define SDIO_INT_RXDTVAL ((uint32_t)0x00200000) -#define SDIO_INT_SDIOINT ((uint32_t)0x00400000) -#define SDIO_INT_ATAEND ((uint32_t)0x00800000) - -/** - * @} - */ - -/** @defgroup SDIO_Response_Type - * @{ - */ -#define SDIO_RESPONSETYPE_NO ((uint32_t)0x00000000) -#define SDIO_RESPONSETYPE_SHORT ((uint32_t)0x00000040) -#define SDIO_RESPONSETYPE_LONG ((uint32_t)0x000000C0) - -/** - * @} - */ - -/** @defgroup SDIO_Wait_Interrupt_State - * @{ - */ -#define SDIO_WAITINTSTATE_NO ((uint32_t)0x00000000) -#define SDIO_WAITINTSTATE_INT ((uint32_t)0x00000100) -#define SDIO_WAITINTSTATE_PEND ((uint32_t)0x00000200) - -/** - * @} - */ - -/** @defgroup SDIO_CSM_State - * @{ - */ -#define SDIO_CSMSTATE_DISABLE ((uint32_t)0x00000000) -#define SDIO_CSMSTATE_ENABLE ((uint32_t)0x00000400) - -/** - * @} - */ - -/** @defgroup SDIO_Response_Registers - * @{ - */ -#define SDIO_RESP1 ((uint32_t)0x00000000) -#define SDIO_RESP2 ((uint32_t)0x00000004) -#define SDIO_RESP3 ((uint32_t)0x00000008) -#define SDIO_RESP4 ((uint32_t)0x0000000C) - -/** - * @} - */ - -/** @defgroup SDIO_Data_Block_Size - * @{ - */ -#define SDIO_DATABLOCKSIZE_1B ((uint32_t)0x00000000) -#define SDIO_DATABLOCKSIZE_2B ((uint32_t)0x00000010) -#define SDIO_DATABLOCKSIZE_4B ((uint32_t)0x00000020) -#define SDIO_DATABLOCKSIZE_8B ((uint32_t)0x00000030) -#define SDIO_DATABLOCKSIZE_16B ((uint32_t)0x00000040) -#define SDIO_DATABLOCKSIZE_32B ((uint32_t)0x00000050) -#define SDIO_DATABLOCKSIZE_64B ((uint32_t)0x00000060) -#define SDIO_DATABLOCKSIZE_128B ((uint32_t)0x00000070) -#define SDIO_DATABLOCKSIZE_256B ((uint32_t)0x00000080) -#define SDIO_DATABLOCKSIZE_512B ((uint32_t)0x00000090) -#define SDIO_DATABLOCKSIZE_1024B ((uint32_t)0x000000A0) -#define SDIO_DATABLOCKSIZE_2048B ((uint32_t)0x000000B0) -#define SDIO_DATABLOCKSIZE_4096B ((uint32_t)0x000000C0) -#define SDIO_DATABLOCKSIZE_8192B ((uint32_t)0x000000D0) -#define SDIO_DATABLOCKSIZE_16384B ((uint32_t)0x000000E0) - -/** - * @} - */ - -/** @defgroup SDIO_Transfer_Direction - * @{ - */ -#define SDIO_TRANSDIRECTION_TOCARD ((uint32_t)0x00000000) -#define SDIO_TRANSDIRECTION_TOSDIO ((uint32_t)0x00000002) - -/** - * @} - */ - -/** @defgroup SDIO_Transfer_Mode - * @{ - */ -#define SDIO_TRANSMODE_BLOCK ((uint32_t)0x00000000) -#define SDIO_TRANSMODE_STREAM ((uint32_t)0x00000004) - -/** - * @} - */ - -/** @defgroup SDIO_DSM_State - * @{ - */ -#define SDIO_DSMSTATE_DISABLE ((uint32_t)0x00000000) -#define SDIO_DSMSTATE_ENABLE ((uint32_t)0x00000001) - -/** - * @} - */ - -/** @defgroup SDIO_Flag - * @{ - */ -#define SDIO_FLAG_CCRCFAIL ((uint32_t)0x00000001) -#define SDIO_FLAG_DTCRCFAIL ((uint32_t)0x00000002) -#define SDIO_FLAG_CMDTMOUT ((uint32_t)0x00000004) -#define SDIO_FLAG_DTTMOUT ((uint32_t)0x00000008) -#define SDIO_FLAG_TXURE ((uint32_t)0x00000010) -#define SDIO_FLAG_RXORE ((uint32_t)0x00000020) -#define SDIO_FLAG_CMDREND ((uint32_t)0x00000040) -#define SDIO_FLAG_CMDSENT ((uint32_t)0x00000080) -#define SDIO_FLAG_DTEND ((uint32_t)0x00000100) -#define SDIO_FLAG_STBITE ((uint32_t)0x00000200) -#define SDIO_FLAG_DTBLKEND ((uint32_t)0x00000400) -#define SDIO_FLAG_CMDRUN ((uint32_t)0x00000800) -#define SDIO_FLAG_TXRUN ((uint32_t)0x00001000) -#define SDIO_FLAG_RXRUN ((uint32_t)0x00002000) -#define SDIO_FLAG_TXFIFOHE ((uint32_t)0x00004000) -#define SDIO_FLAG_RXFIFOHF ((uint32_t)0x00008000) -#define SDIO_FLAG_TXFIFOF ((uint32_t)0x00010000) -#define SDIO_FLAG_RXFIFOF ((uint32_t)0x00020000) -#define SDIO_FLAG_TXFIFOE ((uint32_t)0x00040000) -#define SDIO_FLAG_RXFIFOE ((uint32_t)0x00080000) -#define SDIO_FLAG_TXDTVAL ((uint32_t)0x00100000) -#define SDIO_FLAG_RXDTVAL ((uint32_t)0x00200000) -#define SDIO_FLAG_SDIOINT ((uint32_t)0x00400000) -#define SDIO_FLAG_ATAEND ((uint32_t)0x00800000) - -/** - * @} - */ - -/** @defgroup SDIO_Read_Wait_Mode - * @{ - */ -#define SDIO_READWAITMODE_CLK ((uint32_t)0x00000001) -#define SDIO_READWAITMODE_DAT2 ((uint32_t)0x00000000) - -/** - * @} - */ - -/** - * @} - */ - - -/** @defgroup SDIO_Exported_Functions - * @{ - */ -void SDIO_DeInit(void); -void SDIO_Init(SDIO_InitPara *SDIO_InitParaStruct); -void SDIO_ParaInit(SDIO_InitPara *SDIO_InitParaStruct); -void SDIO_Clock_Enable(TypeState NewState); -void SDIO_SetPWRState(uint32_t SDIO_PWRState); -uint32_t SDIO_GetPWRState(void); -void SDIO_INTConfig(uint32_t SDIO_INT, TypeState NewState); -void SDIO_DMA_Enable(TypeState NewState); -void SDIO_SendCMD(SDIO_CmdInitPara *SDIO_CmdInitParaStruct); -void SDIO_CMDParaInit(SDIO_CmdInitPara *SDIO_CmdInitParaStruct); -uint8_t SDIO_GetCMDResponse(void); -uint32_t SDIO_GetResponse(uint32_t SDIO_RESP); -void SDIO_DataConfig(SDIO_DataInitPara *SDIO_DataInitParaStruct); -void SDIO_DataParaInit(SDIO_DataInitPara *SDIO_DataInitParaStruct); -uint32_t SDIO_GetDataCount(void); -uint32_t SDIO_ReadData(void); -void SDIO_WriteData(uint32_t Data); -uint32_t SDIO_GetFIFOCount(void); -void SDIO_StartSDIOReadWait(TypeState NewState); -void SDIO_StopSDIOReadWait(TypeState NewState); -void SDIO_SetSDIOReadWaitMode(uint32_t SDIO_ReadWaitMode); -void SDIO_SetSDIOOperation(TypeState NewState); -void SDIO_SendSDIOSuspend_Enable(TypeState NewState); -void SDIO_CMDCompletion_Enable(TypeState NewState); -void SDIO_CEATAInt_Enable(TypeState NewState); -void SDIO_SendCEATA_Enable(TypeState NewState); - -TypeState SDIO_GetBitState(uint32_t SDIO_FLAG); -void SDIO_ClearBitState(uint32_t SDIO_FLAG); -TypeState SDIO_GetIntBitState(uint32_t SDIO_INT); -void SDIO_ClearIntBitState(uint32_t SDIO_INT); - -#ifdef __cplusplus -} -#endif - -#endif /* __GD32F10X_SDIO_H */ -/** - * @} - */ - -/** - * @} - */ - -/** - * @} - */ diff --git a/bsp/gd32103c-eval/Libraries/GD32F1xx_standard_peripheral/Include/gd32f10x_spi.h b/bsp/gd32103c-eval/Libraries/GD32F1xx_standard_peripheral/Include/gd32f10x_spi.h deleted file mode 100644 index cf0e88e26f..0000000000 --- a/bsp/gd32103c-eval/Libraries/GD32F1xx_standard_peripheral/Include/gd32f10x_spi.h +++ /dev/null @@ -1,353 +0,0 @@ -/** - ****************************************************************************** - * @brief SPI header file of the firmware library. - ****************************************************************************** - */ - -/* Define to prevent recursive inclusion -------------------------------------*/ -#ifndef __GD32F10X_SPI_H -#define __GD32F10X_SPI_H - -#ifdef __cplusplus -extern "C" { -#endif - -/* Includes ------------------------------------------------------------------*/ -#include "gd32f10x.h" - -/** @addtogroup GD32F10x_Firmware - * @{ - */ - -/** @addtogroup SPI - * @{ - */ - -/** @defgroup SPI_Exported_Types - * @{ - */ - -/** - * @brief SPI Initial Parameters - */ -typedef struct { - uint16_t SPI_TransType; /*!< The transfer type, choose one from @ref SPI_transfer_type. */ - uint16_t SPI_Mode; /*!< The operating mode, choose one from @ref SPI_mode. */ - uint16_t SPI_FrameFormat; /*!< The SPI data frame format, choose one from @ref SPI_data_frame_format. */ - uint16_t SPI_SCKPL; /*!< The clock polarity in idel state, choose one from @ref SPI_Clock_Polarity. */ - uint16_t SPI_SCKPH; /*!< The clock phase, choose one from @ref SPI_Clock_Phase. */ - uint16_t SPI_SWNSSEN; /*!< The NSS signal management, choose one from @ref SPI_Software_NSS_management. */ - uint16_t SPI_PSC; /*!< The Baud Rate prescaler value, choose one from @ref SPI_BaudRate_Prescaler. */ - uint16_t SPI_FirstBit; /*!< The data transfers start from MSB or LSB bit, choose one from @ref SPI_MSB_LSB_transmission. */ - uint16_t SPI_CRCPOL; /*!< The polynomial used for the CRC calculation. */ -} SPI_InitPara; - -/** - * @brief I2S Initial Parameters - */ -typedef struct { - uint16_t I2S_Mode; /*!< The operating mode and transfer direction, choose one from @ref I2S_Mode. */ - uint16_t I2S_STD; /*!< The I2S standard, choose one from @ref I2S_Standard. */ - uint16_t I2S_FrameFormat; /*!< The I2S data length and channel length, choose one from @ref I2S_Data_Format. */ - uint16_t I2S_MCKOE; /*!< The I2S MCK output is enabled or disable, choose one from @ref I2S_MCLK_Output. */ - uint32_t I2S_AudioFreq; /*!< The audio sampling frequency, choose one from @ref I2S_Audio_Frequency. */ - uint16_t I2S_CKPL; /*!< The clock polarity in idel state, choose one from @ref I2S_Clock_Polarity. */ -} I2S_InitPara; - -/** - * @} - */ - -/** @defgroup SPI_Exported_Constants - * @{ - */ - -/** @defgroup SPI_transfer_type - * @{ - */ -#define SPI_TRANSTYPE_FULLDUPLEX ((uint16_t)0x0000) -#define SPI_TRANSTYPE_RXONLY SPI_CTLR1_RO -#define SPI_TRANSTYPE_BDMRX SPI_CTLR1_BDM -#define SPI_TRANSTYPE_BDMTX (SPI_CTLR1_BDM | SPI_CTLR1_BDOE) - -/** - * @} - */ - -/** @defgroup SPI_mode - * @{ - */ -#define SPI_MODE_MASTER (SPI_CTLR1_MSTMODE|SPI_CTLR1_SWNSS) -#define SPI_MODE_SLAVE ((uint16_t)0x0000) - -/** - * @} - */ - -/** @defgroup SPI_data_frame_format - * @{ - */ -#define SPI_FRAMEFORMAT_16BIT SPI_CTLR1_FF16 -#define SPI_FRAMEFORMAT_8BIT ((uint16_t)0x0000) - -/** - * @} - */ - -/** @defgroup SPI_Clock_Polarity - * @{ - */ -#define SPI_SCKPL_LOW ((uint16_t)0x0000) -#define SPI_SCKPL_HIGH SPI_CTLR1_SCKPL - -/** - * @} - */ - -/** @defgroup SPI_Clock_Phase - * @{ - */ -#define SPI_SCKPH_1EDGE ((uint16_t)0x0000) -#define SPI_SCKPH_2EDGE SPI_CTLR1_SCKPH - -/** - * @} - */ - -/** @defgroup SPI_Software_NSS_management - * @{ - */ -#define SPI_SWNSS_SOFT SPI_CTLR1_SWNSSEN -#define SPI_SWNSS_HARD ((uint16_t)0x0000) - -/** - * @} - */ - -/** @defgroup SPI_BaudRate_Prescaler - * @{ - */ -#define SPI_PSC_2 ((uint16_t)0x0000) -#define SPI_PSC_4 ((uint16_t)0x0008) -#define SPI_PSC_8 ((uint16_t)0x0010) -#define SPI_PSC_16 ((uint16_t)0x0018) -#define SPI_PSC_32 ((uint16_t)0x0020) -#define SPI_PSC_64 ((uint16_t)0x0028) -#define SPI_PSC_128 ((uint16_t)0x0030) -#define SPI_PSC_256 ((uint16_t)0x0038) - -/** - * @} - */ - -/** @defgroup SPI_MSB_LSB_transmission - * @{ - */ -#define SPI_FIRSTBIT_MSB ((uint16_t)0x0000) -#define SPI_FIRSTBIT_LSB SPI_CTLR1_LF - -/** - * @} - */ - -/** @defgroup I2S_Mode - * @{ - */ -#define I2S_MODE_SLAVETX ((uint16_t)0x0000) -#define I2S_MODE_SLAVERX ((uint16_t)0x0100) -#define I2S_MODE_MASTERTX ((uint16_t)0x0200) -#define I2S_MODE_MASTERRX ((uint16_t)0x0300) - -/** - * @} - */ - -/** @defgroup I2S_Standard - * @{ - */ -#define I2S_STD_PHILLIPS ((uint16_t)0x0000) -#define I2S_STD_MSB ((uint16_t)0x0010) -#define I2S_STD_LSB ((uint16_t)0x0020) -#define I2S_STD_PCMSHORT ((uint16_t)0x0030) -#define I2S_STD_PCMLONG ((uint16_t)0x00B0) - -/** - * @} - */ - -/** @defgroup I2S_Data_Format - * @{ - */ -#define I2S_FRAMEFORMAT_DL16b_CL16b ((uint16_t)0x0000) -#define I2S_FRAMEFORMAT_DL16b_CL32b ((uint16_t)0x0001) -#define I2S_FRAMEFORMAT_DL24b_CL32b ((uint16_t)0x0003) -#define I2S_FRAMEFORMAT_DL32b_CL32b ((uint16_t)0x0005) - -/** - * @} - */ - -/** @defgroup I2S_MCLK_Output - * @{ - */ -#define I2S_MCK_ENABLE SPI_I2SCKP_MCKOE -#define I2S_MCK_DISABLE ((uint16_t)0x0000) - -/** - * @} - */ - -/** @defgroup I2S_Audio_Frequency - * @{ - */ -#define I2S_AUDIOFREQ_DEFAULT ((uint32_t)2) -#define I2S_AUDIOFREQ_8K ((uint32_t)8000) -#define I2S_AUDIOFREQ_11K ((uint32_t)11025) -#define I2S_AUDIOFREQ_16K ((uint32_t)16000) -#define I2S_AUDIOFREQ_22K ((uint32_t)22050) -#define I2S_AUDIOFREQ_32K ((uint32_t)32000) -#define I2S_AUDIOFREQ_44K ((uint32_t)44100) -#define I2S_AUDIOFREQ_48K ((uint32_t)48000) -#define I2S_AUDIOFREQ_96K ((uint32_t)96000) -#define I2S_AUDIOFREQ_192K ((uint32_t)192000) - -/** - * @} - */ - -/** @defgroup I2S_Clock_Polarity - * @{ - */ -#define I2S_CKPL_LOW ((uint16_t)0x0000) -#define I2S_CKPL_HIGH SPI_I2SCTLR_CKPL - -/** - * @} - */ - -/** @defgroup SPI_I2S_DMA_transfer_requests - * @{ - */ -#define SPI_I2S_DMA_TX SPI_CTLR2_DMATE -#define SPI_I2S_DMA_RX SPI_CTLR2_DMARE - -/** - * @} - */ - -/** @defgroup SPI_NSS_internal_software_management - * @{ - */ -#define SPI_SWNSS_SET ((uint16_t)0x0001) -#define SPI_SWNSS_RESET ((uint16_t)0x0000) - -/** - * @} - */ - -/** @defgroup SPI_CRC_Transmit_Receive - * @{ - */ -#define SPI_CRC_TX ((uint8_t)0x00) -#define SPI_CRC_RX ((uint8_t)0x01) - -/** - * @} - */ - -/** @defgroup SPI_direction_transmit_receive - * @{ - */ -#define SPI_BDOE_RX (~SPI_CTLR1_BDOE) -#define SPI_BDOE_TX SPI_CTLR1_BDOE - -/** - * @} - */ - -/** @defgroup SPI_I2S_interrupts_definition - * @{ - */ -#define SPI_I2S_INT_TBE ((uint8_t)0x71) -#define SPI_I2S_INT_RBNE ((uint8_t)0x60) -#define SPI_I2S_INT_ERR ((uint8_t)0x50) -#define SPI_I2S_INT_OVR ((uint8_t)0x56) -#define SPI_INT_MODF ((uint8_t)0x55) -#define SPI_INT_CRCERR ((uint8_t)0x54) -#define I2S_INT_UDR ((uint8_t)0x53) - -/** - * @} - */ - -/** @defgroup SPI_I2S_flags_definition - * @{ - */ -#define SPI_FLAG_RBNE SPI_STR_RBNE -#define SPI_FLAG_TBE SPI_STR_TBE -#define SPI_FLAG_CRCERR SPI_STR_CRCE -#define SPI_FLAG_MODF SPI_STR_CONFE -#define SPI_FLAG_OVR SPI_STR_RXORE -#define SPI_FLAG_BSY SPI_STR_TRANS - -#define I2S_FLAG_RBNE SPI_STR_RBNE -#define I2S_FLAG_TBE SPI_STR_TBE -#define I2S_FLAG_CHSIDE SPI_STR_I2SCH -#define I2S_FLAG_UDR SPI_STR_TXURE -#define I2S_FLAG_OVR SPI_STR_RXORE -#define I2S_FLAG_BSY SPI_STR_TRANS - -/** - * @} - */ - -/** - * @} - */ - - -/** @defgroup SPI_Exported_Functions - * @{ - */ -void SPI_I2S_DeInit(SPI_TypeDef *SPIx); -void SPI_Init(SPI_TypeDef *SPIx, SPI_InitPara *SPI_InitParameter); -void I2S_Init(SPI_TypeDef *SPIx, I2S_InitPara *I2S_InitParameter); -void SPI_ParaInit(SPI_InitPara *SPI_InitParameter); -void I2S_ParaInit(I2S_InitPara *I2S_InitParameter); -void SPI_Enable(SPI_TypeDef *SPIx, TypeState NewValue); -void I2S_Enable(SPI_TypeDef *SPIx, TypeState NewValue); -void SPI_I2S_INTConfig(SPI_TypeDef *SPIx, uint8_t SPI_I2S_INT, TypeState NewValue); -void SPI_I2S_DMA_Enable(SPI_TypeDef *SPIx, uint16_t SPI_I2S_DMAReq, TypeState NewValue); -void SPI_I2S_SendData(SPI_TypeDef *SPIx, uint16_t Data); -uint16_t SPI_I2S_ReceiveData(SPI_TypeDef *SPIx); -void SPI_SWNSSConfig(SPI_TypeDef *SPIx, uint16_t SPI_SWNSS); -void SPI_NSSDRV(SPI_TypeDef *SPIx, TypeState NewValue); -void SPI_FrameFormatConfig(SPI_TypeDef *SPIx, uint16_t SPI_DataSize); -void SPI_SendCRCNext(SPI_TypeDef *SPIx); -void SPI_CRC_Enable(SPI_TypeDef *SPIx, TypeState NewValue); -uint16_t SPI_GetCRC(SPI_TypeDef *SPIx, uint8_t SPI_CRC); -uint16_t SPI_GetCRCPolynomial(SPI_TypeDef *SPIx); -void SPI_BDOEConfig(SPI_TypeDef *SPIx, uint16_t SPI_BDOE); -TypeState SPI_I2S_GetBitState(SPI_TypeDef *SPIx, uint16_t SPI_I2S_FLAG); -void SPI_I2S_ClearBitState(SPI_TypeDef *SPIx, uint16_t SPI_I2S_FLAG); -TypeState SPI_I2S_GetIntBitState(SPI_TypeDef *SPIx, uint8_t SPI_I2S_INT); -void SPI_I2S_ClearIntBitState(SPI_TypeDef *SPIx, uint8_t SPI_I2S_INT); - -#ifdef __cplusplus -} -#endif - -#endif /*__GD32F10X_SPI_H */ - -/** - * @} - */ - -/** - * @} - */ - -/** - * @} - */ - diff --git a/bsp/gd32103c-eval/Libraries/GD32F1xx_standard_peripheral/Include/gd32f10x_timer.h b/bsp/gd32103c-eval/Libraries/GD32F1xx_standard_peripheral/Include/gd32f10x_timer.h deleted file mode 100644 index a720a1cd3e..0000000000 --- a/bsp/gd32103c-eval/Libraries/GD32F1xx_standard_peripheral/Include/gd32f10x_timer.h +++ /dev/null @@ -1,758 +0,0 @@ -/** - ****************************************************************************** - * @brief TIMER header file of the firmware library - ****************************************************************************** - */ - -/* Define to prevent recursive inclusion -------------------------------------*/ -#ifndef __GD32F10X_TIMER_H -#define __GD32F10X_TIMER_H - -#ifdef __cplusplus -extern "C" { -#endif - -/* Includes ------------------------------------------------------------------*/ -#include "gd32f10x.h" - -/** @addtogroup GD32F10x_Firmware - * @{ - */ - -/** @addtogroup TIMER - * @{ - */ - -/** @defgroup TIMER_Exported_Types - * @{ - */ - -/** - * @brief Timer base init structure - */ -typedef struct { - uint16_t TIMER_Prescaler; /*!< Clock prescaler value . */ - uint16_t TIMER_CounterMode; /*!< Counter mode , - a value of @ref TIMER_Counter_Mode. */ - uint32_t TIMER_Period; /*!< Value to be loaded into the active CARL at the next update event. */ - uint16_t TIMER_ClockDivision; /*!< Clock division , - a value of @ref TIMER_Clock_Division_CDIV. */ - uint8_t TIMER_RepetitionCounter; /*!< Repetition counter value , only valid in TIMER1/8. */ -} TIMER_BaseInitPara; - -/** - * @brief Timer output compare init structure - */ -typedef struct { - uint16_t TIMER_OCMode; /*!< Out mode, - a value of @ref TIMER_Output_Compare_and_PWM_modes */ - - uint16_t TIMER_OutputState; /*!< Output Compare state , - a value of @ref TIMER_Output_Compare_State */ - uint16_t TIMER_OutputNState; /*!< Complementary Output Compare state , - a value of @ref TIMER_Output_Compare_N_State, - valid only for TIMER1. */ - uint32_t TIMER_Pulse; /*!< Pulse value to be loaded into the CHCCx. */ - uint16_t TIMER_OCPolarity; /*!< Output polarity , - a value of @ref TIMER_Output_Compare_Polarity */ - uint16_t TIMER_OCNPolarity; /*!< Complementary output polarity , - a value of @ref TIMER_Output_Compare_N_Polarity */ - uint16_t TIMER_OCIdleState; /*!< TIM Output Compare pin state during Idle state , - a value of @ref TIMER_Output_Compare_Idle_State, - valid only for TIMER1. */ - uint16_t TIMER_OCNIdleState; /*!< TIM Complementary Output Compare pin state during Idle state. - a value of @ref TIMER_Output_Compare_N_Idle_State , - valid only for TIMER1. */ -} TIMER_OCInitPara; - -/** - * @brief Timer input capture init structure - */ -typedef struct { - uint16_t TIMER_CH; /*!< TIMER channel , - a value of @ref TIMER_Channel */ - uint16_t TIMER_ICPolarity; /*!< Active edge of the input signal , - a value of @ref TIMER_Input_Capture_Polarity */ - uint16_t TIMER_ICSelection; /*!< Input Selection , - a value of @ref TIMER_Input_Capture_Selection */ - uint16_t TIMER_ICPrescaler; /*!< Input Capture Prescaler , - a value of @ref TIMER_Input_Capture_Prescaler */ - uint16_t TIMER_ICFilter; /*!< Input capture filter , - a number between 0x0 and 0xF */ -} TIMER_ICInitPara; - -/** - * @brief Timer break and dead-time structure , valid only for TIMER1. - */ -typedef struct { - uint16_t TIMER_ROSState; /*!< Off-State selection used in Run mode , - a value of @ref TIMER_ROS_Off_State_Selection_for_Run_mode_State */ - uint16_t TIMER_IOSState; /*!< Off-State used in Idle state , - a value of @ref TIMER_IOS_Off_State_Selection_for_Idle_mode_State */ - uint16_t TIMER_LOCKLevel; /*!< LOCK level , - a value of @ref TIMER_Lock_level */ - uint16_t TIMER_DeadTime; /*!< delay time between the switching off and on of the outputs. - a number between 0x00 and 0xFF */ - uint16_t TIMER_Break; /*!< Break input is enabled or disable, - a value of @ref TIMER_Break_Input_State */ - uint16_t TIMER_BreakPolarity; /*!< Break Input pin polarity , - a value of @ref TIMER_Break_Input_Polarity */ - uint16_t TIMER_OutAuto; /*!< Automatic Output is enabled or disable. - a value of @ref TIMER_OAE_Bit_State */ -} TIMER_BKDTInitPara; - -/** - * @} - */ - -/** @defgroup TIMER_Exported_Constants - * @{ - */ - -/** @defgroup TIMER_Output_Compare_and_PWM_modes - * @{ - */ -#define TIMER_OC_MODE_TIMING ((uint16_t)0x0000) -#define TIMER_OC_MODE_ACTIVE ((uint16_t)0x0010) -#define TIMER_OC_MODE_INACTIVE ((uint16_t)0x0020) -#define TIMER_OC_MODE_TOGGLE ((uint16_t)0x0030) -#define TIMER_OC_MODE_PWM1 ((uint16_t)0x0060) -#define TIMER_OC_MODE_PWM2 ((uint16_t)0x0070) - -/** - * @} - */ - -/** @defgroup TIMER_Single_Pulse_Mode - * @{ - */ -#define TIMER_SP_MODE_SINGLE ((uint16_t)0x0008) -#define TIMER_SP_MODE_REPETITIVE ((uint16_t)0x0000) - -/** - * @} - */ - -/** @defgroup TIMER_Channel - * @{ - */ -#define TIMER_CH_1 ((uint16_t)0x0000) -#define TIMER_CH_2 ((uint16_t)0x0004) -#define TIMER_CH_3 ((uint16_t)0x0008) -#define TIMER_CH_4 ((uint16_t)0x000C) - -/** - * @} - */ - -/** @defgroup TIMER_Clock_Division_CDIV - * @{ - */ -#define TIMER_CDIV_DIV1 ((uint16_t)0x0000) -#define TIMER_CDIV_DIV2 ((uint16_t)0x0100) -#define TIMER_CDIV_DIV4 ((uint16_t)0x0200) - -/** - * @} - */ - -/** @defgroup TIMER_Counter_Mode - * @{ - */ -#define TIMER_COUNTER_UP ((uint16_t)0x0000) -#define TIMER_COUNTER_DOWN ((uint16_t)0x0010) -#define TIMER_COUNTER_CENTER_ALIGNED1 ((uint16_t)0x0020) -#define TIMER_COUNTER_CENTER_ALIGNED2 ((uint16_t)0x0040) -#define TIMER_COUNTER_CENTER_ALIGNED3 ((uint16_t)0x0060) - -/** - * @} - */ - -/** @defgroup TIMER_Output_Compare_Polarity - * @{ - */ -#define TIMER_OC_POLARITY_HIGH ((uint16_t)0x0000) -#define TIMER_OC_POLARITY_LOW ((uint16_t)0x0002) - -/** - * @} - */ - -/** @defgroup TIMER_Output_Compare_N_Polarity - * @{ - */ -#define TIMER_OCN_POLARITY_HIGH ((uint16_t)0x0000) -#define TIMER_OCN_POLARITY_LOW ((uint16_t)0x0008) - -/** - * @} - */ - -/** @defgroup TIMER_Output_Compare_State - * @{ - */ -#define TIMER_OUTPUT_STATE_DISABLE ((uint16_t)0x0000) -#define TIMER_OUTPUT_STATE_ENABLE ((uint16_t)0x0001) - -/** - * @} - */ - -/** @defgroup TIMER_Output_Compare_N_State - * @{ - */ -#define TIMER_OUTPUTN_STATE_DISABLE ((uint16_t)0x0000) -#define TIMER_OUTPUTN_STATE_ENABLE ((uint16_t)0x0004) - -/** - * @} - */ - -/** @defgroup TIMER_Capture_Compare_State - * @{ - */ -#define TIMER_CCX_ENABLE ((uint16_t)0x0001) -#define TIMER_CCX_DISABLE ((uint16_t)0x0000) - -/** - * @} - */ - -/** @defgroup TIMER_Capture_Compare_N_State - * @{ - */ -#define TIMER_CCXN_ENABLE ((uint16_t)0x0004) -#define TIMER_CCXN_DISABLE ((uint16_t)0x0000) - -/** - * @} - */ - -/** @defgroup TIMER_Break_Input_State - * @{ - */ -#define TIMER_BREAK_ENABLE ((uint16_t)0x1000) -#define TIMER_BREAK_DISABLE ((uint16_t)0x0000) - -/** - * @} - */ - -/** @defgroup TIMER_Break_Input_Polarity - * @{ - */ -#define TIMER_BREAK_POLARITY_LOW ((uint16_t)0x0000) -#define TIMER_BREAK_POLARITY_HIGH ((uint16_t)0x2000) - -/** - * @} - */ - -/** @defgroup TIMER_OAE_Bit_State - * @{ - */ -#define TIMER_OUTAUTO_ENABLE ((uint16_t)0x4000) -#define TIMER_OUTAUTO_DISABLE ((uint16_t)0x0000) - -/** - * @} - */ - -/** @defgroup TIMER_Lock_level - * @{ - */ -#define TIMER_LOCK_LEVEL_OFF ((uint16_t)0x0000) -#define TIMER_LOCK_LEVEL_1 ((uint16_t)0x0100) -#define TIMER_LOCK_LEVEL_2 ((uint16_t)0x0200) -#define TIMER_LOCK_LEVEL_3 ((uint16_t)0x0300) - -/** - * @} - */ - -/** @defgroup TIMER_IOS_Off_State_Selection_for_Idle_mode_State - * @{ - */ -#define TIMER_IOS_STATE_ENABLE ((uint16_t)0x0400) -#define TIMER_IOS_STATE_DISABLE ((uint16_t)0x0000) - -/** - * @} - */ - -/** @defgroup TIMER_ROS_Off_State_Selection_for_Run_mode_State - * @{ - */ -#define TIMER_ROS_STATE_ENABLE ((uint16_t)0x0800) -#define TIMER_ROS_STATE_DISABLE ((uint16_t)0x0000) - -/** - * @} - */ - -/** @defgroup TIMER_Output_Compare_Idle_State - * @{ - */ -#define TIMER_OC_IDLE_STATE_SET ((uint16_t)0x0100) -#define TIMER_OC_IDLE_STATE_RESET ((uint16_t)0x0000) - -/** - * @} - */ - -/** @defgroup TIMER_Output_Compare_N_Idle_State - * @{ - */ -#define TIMER_OCN_IDLE_STATE_SET ((uint16_t)0x0200) -#define TIMER_OCN_IDLE_STATE_RESET ((uint16_t)0x0000) - -/** - * @} - */ - -/** @defgroup TIMER_Input_Capture_Polarity - * @{ - */ -#define TIMER_IC_POLARITY_RISING ((uint16_t)0x0000) -#define TIMER_IC_POLARITY_FALLING ((uint16_t)0x0002) - -/** - * @} - */ - -/** @defgroup TIMER_Input_Capture_Selection - * @{ - */ -#define TIMER_IC_SELECTION_DIRECTTI ((uint16_t)0x0001) -#define TIMER_IC_SELECTION_INDIRECTTI ((uint16_t)0x0002) -#define TIMER_IC_SELECTION_TRC ((uint16_t)0x0003) - -/** - * @} - */ - -/** @defgroup TIMER_Input_Capture_Prescaler - * @{ - */ -#define TIMER_IC_PSC_DIV1 ((uint16_t)0x0000) -#define TIMER_IC_PSC_DIV2 ((uint16_t)0x0004) -#define TIMER_IC_PSC_DIV4 ((uint16_t)0x0008) -#define TIMER_IC_PSC_DIV8 ((uint16_t)0x000C) - -/** - * @} - */ - -/** @defgroup TIMER_interrupt_sources - * @{ - */ -#define TIMER_INT_UPDATE ((uint16_t)0x0001) -#define TIMER_INT_CH1 ((uint16_t)0x0002) -#define TIMER_INT_CH2 ((uint16_t)0x0004) -#define TIMER_INT_CH3 ((uint16_t)0x0008) -#define TIMER_INT_CH4 ((uint16_t)0x0010) -#define TIMER_INT_CCUG ((uint16_t)0x0020) -#define TIMER_INT_TRIGGER ((uint16_t)0x0040) -#define TIMER_INT_BREAK ((uint16_t)0x0080) - -/** - * @} - */ - -/** @defgroup TIMER_DMA_Base_address - * @{ - */ -#define TIMER_DMA_BASE_ADDR_CTLR1 ((uint16_t)0x0000) -#define TIMER_DMA_BASE_ADDR_CTLR2 ((uint16_t)0x0001) -#define TIMER_DMA_BASE_ADDR_SMC ((uint16_t)0x0002) -#define TIMER_DMA_BASE_ADDR_DIE ((uint16_t)0x0003) -#define TIMER_DMA_BASE_ADDR_STR ((uint16_t)0x0004) -#define TIMER_DMA_BASE_ADDR_EVG ((uint16_t)0x0005) -#define TIMER_DMA_BASE_ADDR_CHCTLR1 ((uint16_t)0x0006) -#define TIMER_DMA_BASE_ADDR_CHCTLR2 ((uint16_t)0x0007) -#define TIMER_DMA_BASE_ADDR_CHE ((uint16_t)0x0008) -#define TIMER_DMA_BASE_ADDR_CNT ((uint16_t)0x0009) -#define TIMER_DMA_BASE_ADDR_PSC ((uint16_t)0x000A) -#define TIMER_DMA_BASE_ADDR_CARL ((uint16_t)0x000B) -#define TIMER_DMA_BASE_ADDR_CREP ((uint16_t)0x000C) -#define TIMER_DMA_BASE_ADDR_CHCC1 ((uint16_t)0x000D) -#define TIMER_DMA_BASE_ADDR_CHCC2 ((uint16_t)0x000E) -#define TIMER_DMA_BASE_ADDR_CHCC3 ((uint16_t)0x000F) -#define TIMER_DMA_BASE_ADDR_CHCC4 ((uint16_t)0x0010) -#define TIMER_DMA_BASE_ADDR_BKDT ((uint16_t)0x0011) -#define TIMER_DMA_BASE_ADDR_DCTLR ((uint16_t)0x0012) - -/** - * @} - */ - -/** @defgroup TIMER_DMA_Burst_Transfer_Length - * @{ - */ -#define TIMER_DMA_BURST_1TRANSFER ((uint16_t)0x0000) -#define TIMER_DMA_BURST_2TRANSFERS ((uint16_t)0x0100) -#define TIMER_DMA_BURST_3TRANSFERS ((uint16_t)0x0200) -#define TIMER_DMA_BURST_4TRANSFERS ((uint16_t)0x0300) -#define TIMER_DMA_BURST_5TRANSFERS ((uint16_t)0x0400) -#define TIMER_DMA_BURST_6TRANSFERS ((uint16_t)0x0500) -#define TIMER_DMA_BURST_7TRANSFERS ((uint16_t)0x0600) -#define TIMER_DMA_BURST_8TRANSFERS ((uint16_t)0x0700) -#define TIMER_DMA_BURST_9TRANSFERS ((uint16_t)0x0800) -#define TIMER_DMA_BURST_10TRANSFERS ((uint16_t)0x0900) -#define TIMER_DMA_BURST_11TRANSFERS ((uint16_t)0x0A00) -#define TIMER_DMA_BURST_12TRANSFERS ((uint16_t)0x0B00) -#define TIMER_DMA_BURST_13TRANSFERS ((uint16_t)0x0C00) -#define TIMER_DMA_BURST_14TRANSFERS ((uint16_t)0x0D00) -#define TIMER_DMA_BURST_15TRANSFERS ((uint16_t)0x0E00) -#define TIMER_DMA_BURST_16TRANSFERS ((uint16_t)0x0F00) -#define TIMER_DMA_BURST_17TRANSFERS ((uint16_t)0x1000) -#define TIMER_DMA_BURST_18TRANSFERS ((uint16_t)0x1100) - -/** - * @} - */ - -/** @defgroup TIMER_DMA_sources - * @{ - */ -#define TIMER_DMA_UPDATE ((uint16_t)0x0100) -#define TIMER_DMA_CH1 ((uint16_t)0x0200) -#define TIMER_DMA_CH2 ((uint16_t)0x0400) -#define TIMER_DMA_CH3 ((uint16_t)0x0800) -#define TIMER_DMA_CH4 ((uint16_t)0x1000) -#define TIMER_DMA_COM ((uint16_t)0x2000) -#define TIMER_DMA_TRIGGER ((uint16_t)0x4000) - -/** - * @} - */ - -/** @defgroup TIMER_External_Trigger_Prescaler - * @{ - */ -#define TIMER_EXT_TRI_PSC_OFF ((uint16_t)0x0000) -#define TIMER_EXT_TRI_PSC_DIV2 ((uint16_t)0x1000) -#define TIMER_EXT_TRI_PSC_DIV4 ((uint16_t)0x2000) -#define TIMER_EXT_TRI_PSC_DIV8 ((uint16_t)0x3000) - -/** - * @} - */ - -/** @defgroup TIMER_Internal_Trigger_Selection - * @{ - */ -#define TIMER_TS_ITR0 ((uint16_t)0x0000) -#define TIMER_TS_ITR1 ((uint16_t)0x0010) -#define TIMER_TS_ITR2 ((uint16_t)0x0020) -#define TIMER_TS_ITR3 ((uint16_t)0x0030) -#define TIMER_TS_TI1F_ED ((uint16_t)0x0040) -#define TIMER_TS_TI1FP1 ((uint16_t)0x0050) -#define TIMER_TS_TI2FP2 ((uint16_t)0x0060) -#define TIMER_TS_ETRF ((uint16_t)0x0070) - -/** - * @} - */ - -/** @defgroup TIMER_TIx_External_Clock_Source - * @{ - */ -#define TIMER_TIX_EXCLK1_SRC_TI1 ((uint16_t)0x0050) -#define TIMER_TIX_EXCLK1_SRC_TI2 ((uint16_t)0x0060) -#define TIMER_TIX_EXCLK1_SRC_TI1ED ((uint16_t)0x0040) - -/** - * @} - */ - -/** @defgroup TIMER_External_Trigger_Polarity - * @{ - */ -#define TIMER_EXT_TRI_POLARITY_INVERTED ((uint16_t)0x8000) -#define TIMER_EXT_TRI_POLARITY_NONINVERTED ((uint16_t)0x0000) - -/** - * @} - */ - -/** @defgroup TIMER_Prescaler_Reload_Mode - * @{ - */ -#define TIMER_PSC_RELOAD_UPDATE ((uint16_t)0x0000) -#define TIMER_PSC_RELOAD_NOW ((uint16_t)0x0001) - -/** - * @} - */ - -/** @defgroup TIMER_Forced_Output - * @{ - */ -#define TIMER_FORCED_HIGH ((uint16_t)0x0050) -#define TIMER_FORCED_LOW ((uint16_t)0x0040) - -/** - * @} - */ - -/** @defgroup TIMER_Encoder_Mode - * @{ - */ -#define TIMER_ENCODER_MODE_TI1 ((uint16_t)0x0001) -#define TIMER_ENCODER_MODE_TI2 ((uint16_t)0x0002) -#define TIMER_ENCODER_MODE_TI12 ((uint16_t)0x0003) - -/** - * @} - */ - -/** @defgroup TIMER_Event_Source - * @{ - */ -#define TIMER_EVENT_SRC_UPDATE ((uint16_t)0x0001) -#define TIMER_EVENT_SRC_CH1 ((uint16_t)0x0002) -#define TIMER_EVENT_SRC_CH2 ((uint16_t)0x0004) -#define TIMER_EVENT_SRC_CH3 ((uint16_t)0x0008) -#define TIMER_EVENT_SRC_CH4 ((uint16_t)0x0010) -#define TIMER_EVENT_SRC_COM ((uint16_t)0x0020) -#define TIMER_EVENT_SRC_TRIGGER ((uint16_t)0x0040) -#define TIMER_EVENT_SRC_BREAK ((uint16_t)0x0080) - -/** - * @} - */ - -/** @defgroup TIMER_Update_Source - * @{ - */ -#define TIMER_UPDATE_SRC_GLOBAL ((uint16_t)0x0000) -#define TIMER_UPDATE_SRC_REGULAR ((uint16_t)0x0001) - -/** - * @} - */ - -/** @defgroup TIMER_Output_Compare_Preload_State - * @{ - */ -#define TIMER_OC_PRELOAD_ENABLE ((uint16_t)0x0008) -#define TIMER_OC_PRELOAD_DISABLE ((uint16_t)0x0000) - -/** - * @} - */ - -/** @defgroup TIMER_Output_Compare_Fast_State - * @{ - */ -#define TIMER_OC_FAST_ENABLE ((uint16_t)0x0004) -#define TIMER_OC_FAST_DISABLE ((uint16_t)0x0000) - -/** - * @} - */ - -/** @defgroup TIMER_Output_Compare_Clear_State - * @{ - */ -#define TIMER_OC_CLEAR_ENABLE ((uint16_t)0x0080) -#define TIMER_OC_CLEAR_DISABLE ((uint16_t)0x0000) - -/** - * @} - */ - -/** @defgroup TIMER_Trigger_Output_Source - * @{ - */ -#define TIMER_TRI_OUT_SRC_RESET ((uint16_t)0x0000) -#define TIMER_TRI_OUT_SRC_ENABLE ((uint16_t)0x0010) -#define TIMER_TRI_OUT_SRC_UPDATE ((uint16_t)0x0020) -#define TIMER_TRI_OUT_SRC_OC1 ((uint16_t)0x0030) -#define TIMER_TRI_OUT_SRC_OC1REF ((uint16_t)0x0040) -#define TIMER_TRI_OUT_SRC_OC2REF ((uint16_t)0x0050) -#define TIMER_TRI_OUT_SRC_OC3REF ((uint16_t)0x0060) -#define TIMER_TRI_OUT_SRC_OC4REF ((uint16_t)0x0070) - -/** - * @} - */ - -/** @defgroup TIMER_Slave_Mode - * @{ - */ -#define TIMER_SLAVE_MODE_RESET ((uint16_t)0x0004) -#define TIMER_SLAVE_MODE_GATED ((uint16_t)0x0005) -#define TIMER_SLAVE_MODE_TRIGGER ((uint16_t)0x0006) -#define TIMER_SLAVE_MODE_EXTERNAL1 ((uint16_t)0x0007) - -/** - * @} - */ - -/** @defgroup TIMER_Master_Slave_Mode - * @{ - */ -#define TIMER_MASTER_SLAVE_MODE_ENABLE ((uint16_t)0x0080) -#define TIMER_MASTER_SLAVE_MODE_DISABLE ((uint16_t)0x0000) - -/** - * @} - */ - -/** @defgroup TIMER_Flags - * @{ - */ -#define TIMER_FLAG_UPDATE ((uint16_t)0x0001) -#define TIMER_FLAG_CH1 ((uint16_t)0x0002) -#define TIMER_FLAG_CH2 ((uint16_t)0x0004) -#define TIMER_FLAG_CH3 ((uint16_t)0x0008) -#define TIMER_FLAG_CH4 ((uint16_t)0x0010) -#define TIMER_FLAG_COM ((uint16_t)0x0020) -#define TIMER_FLAG_TRIGGER ((uint16_t)0x0040) -#define TIMER_FLAG_BREAK ((uint16_t)0x0080) -#define TIMER_FLAG_CH1OF ((uint16_t)0x0200) -#define TIMER_FLAG_CH2OF ((uint16_t)0x0400) -#define TIMER_FLAG_CH3OF ((uint16_t)0x0800) -#define TIMER_FLAG_CH4OF ((uint16_t)0x1000) - -/** - * @} - */ - - -/** - * @} - */ - - -/** @defgroup TIMER_Exported_Functions - * @{ - */ -/* TimeBase management ********************************************************/ -void TIMER_DeInit(TIMER_TypeDef *TIMERx); -void TIMER_BaseInit(TIMER_TypeDef *TIMERx, TIMER_BaseInitPara *TIMER_Init); -void TIMER_BaseStructInit(TIMER_BaseInitPara *TIMER_Init); -void TIMER_PrescalerConfig(TIMER_TypeDef *TIMERx, uint16_t Prescaler, uint16_t TIMER_PSCReloadMode); -void TIMER_CounterMode(TIMER_TypeDef *TIMERx, uint16_t TIMER_CounterMode); -void TIMER_SetCounter(TIMER_TypeDef *TIMERx, uint32_t Counter); -void TIMER_SetAutoreload(TIMER_TypeDef *TIMERx, uint32_t AutoReloadValue); -uint32_t TIMER_GetCounter(TIMER_TypeDef *TIMERx); -uint16_t TIMER_GetPrescaler(TIMER_TypeDef *TIMERx); -void TIMER_UpdateDisableConfig(TIMER_TypeDef *TIMERx, TypeState NewValue); -void TIMER_UpdateRequestConfig(TIMER_TypeDef *TIMERx, uint16_t TIMER_UpdateSrc); -void TIMER_CARLPreloadConfig(TIMER_TypeDef *TIMERx, TypeState NewValue); -void TIMER_SinglePulseMode(TIMER_TypeDef *TIMERx, uint16_t TIMER_SPMode); -void TIMER_SetClockDivision(TIMER_TypeDef *TIMERx, uint16_t TIMER_CDIV); -void TIMER_Enable(TIMER_TypeDef *TIMERx, TypeState NewValue); - -/* Advanced timer features*******************/ -void TIMER_BKDTConfig(TIMER_TypeDef *TIMERx, TIMER_BKDTInitPara *TIMER_BKDTInit); -void TIMER_BKDTStructInit(TIMER_BKDTInitPara *TIMER_BKDTInit); -void TIMER_CtrlPWMOutputs(TIMER_TypeDef *TIMERx, TypeState NewValue); - -/* Output Compare management **************************************************/ -void TIMER_OC1_Init(TIMER_TypeDef *TIMERx, TIMER_OCInitPara *TIMER_OCInit); -void TIMER_OC2_Init(TIMER_TypeDef *TIMERx, TIMER_OCInitPara *TIMER_OCInit); -void TIMER_OC3_Init(TIMER_TypeDef *TIMERx, TIMER_OCInitPara *TIMER_OCInit); -void TIMER_OC4_Init(TIMER_TypeDef *TIMERx, TIMER_OCInitPara *TIMER_OCInit); -void TIMER_OCStructInit(TIMER_OCInitPara *TIMER_OCInit); -void TIMER_OCxModeConfig(TIMER_TypeDef *TIMERx, uint16_t TIMER_Ch, uint16_t TIMER_OCMode); -void TIMER_Compare1Config(TIMER_TypeDef *TIMERx, uint32_t CompValue1); -void TIMER_Compare2Config(TIMER_TypeDef *TIMERx, uint32_t CompValue2); -void TIMER_Compare3Config(TIMER_TypeDef *TIMERx, uint32_t CompValue3); -void TIMER_Compare4Config(TIMER_TypeDef *TIMERx, uint32_t CompValue4); -void TIMER_Forced_OC1(TIMER_TypeDef *TIMERx, uint16_t TIMER_Forced); -void TIMER_Forced_OC2(TIMER_TypeDef *TIMERx, uint16_t TIMER_Forced); -void TIMER_Forced_OC3(TIMER_TypeDef *TIMERx, uint16_t TIMER_Forced); -void TIMER_Forced_OC4(TIMER_TypeDef *TIMERx, uint16_t TIMER_Forced); -void TIMER_CC_PreloadControl(TIMER_TypeDef *TIMERx, TypeState NewValue); -void TIMER_OC1_Preload(TIMER_TypeDef *TIMERx, uint16_t TIMER_OCPreload); -void TIMER_OC2_Preload(TIMER_TypeDef *TIMERx, uint16_t TIMER_OCPreload); -void TIMER_OC3_Preload(TIMER_TypeDef *TIMERx, uint16_t TIMER_OCPreload); -void TIMER_OC4_Preload(TIMER_TypeDef *TIMERx, uint16_t TIMER_OCPreload); -void TIMER_OC1_FastConfig(TIMER_TypeDef *TIMERx, uint16_t TIMER_OCFast); -void TIMER_OC2_FastConfig(TIMER_TypeDef *TIMERx, uint16_t TIMER_OCFast); -void TIMER_OC3_FastConfig(TIMER_TypeDef *TIMERx, uint16_t TIMER_OCFast); -void TIMER_OC4_FastConfig(TIMER_TypeDef *TIMERx, uint16_t TIMER_OCFast); -void TIMER_OC1_RefClear(TIMER_TypeDef *TIMERx, uint16_t TIMER_OCClear); -void TIMER_OC2_RefClear(TIMER_TypeDef *TIMERx, uint16_t TIMER_OCClear); -void TIMER_OC3_RefClear(TIMER_TypeDef *TIMERx, uint16_t TIMER_OCClear); -void TIMER_OC4_RefClear(TIMER_TypeDef *TIMERx, uint16_t TIMER_OCClear); -void TIMER_OC1_Polarity(TIMER_TypeDef *TIMERx, uint16_t TIMER_OCPolarity); -void TIMER_OC1N_Polarity(TIMER_TypeDef *TIMERx, uint16_t TIMER_OCNPolarity); -void TIMER_OC2_Polarity(TIMER_TypeDef *TIMERx, uint16_t TIMER_OCPolarity); -void TIMER_OC2N_Polarity(TIMER_TypeDef *TIMERx, uint16_t TIMER_OCNPolarity); -void TIMER_OC3_Polarity(TIMER_TypeDef *TIMERx, uint16_t TIMER_OCPolarity); -void TIMER_OC3N_Polarity(TIMER_TypeDef *TIMERx, uint16_t TIMER_OCNPolarity); -void TIMER_OC4_Polarity(TIMER_TypeDef *TIMERx, uint16_t TIMER_OCPolarity); -void TIMER_SelectOCRefClear(TIMER_TypeDef *TIMERx, uint16_t TIMER_OCRef_Clear); -void TIMER_CCxCmd(TIMER_TypeDef *TIMERx, uint16_t TIMER_Ch, uint16_t TIMER_CCx); -void TIMER_CCxNCmd(TIMER_TypeDef *TIMERx, uint16_t TIMER_Ch, uint16_t TIMER_CCxN); -void TIMER_SelectCOM(TIMER_TypeDef *TIMERx, TypeState NewValue); - -/* Input Capture management ***************************************************/ -void TIMER_ICInit(TIMER_TypeDef *TIMERx, TIMER_ICInitPara *TIMER_ICInit); -void TIMER_ICStructInit(TIMER_ICInitPara *TIMER_ICInit); -void TIMER_PWMCaptureConfig(TIMER_TypeDef *TIMERx, TIMER_ICInitPara *TIMER_ICInit); -uint32_t TIMER_GetCapture1(TIMER_TypeDef *TIMERx); -uint32_t TIMER_GetCapture2(TIMER_TypeDef *TIMERx); -uint32_t TIMER_GetCapture3(TIMER_TypeDef *TIMERx); -uint32_t TIMER_GetCapture4(TIMER_TypeDef *TIMERx); -void TIMER_Set_IC1_Prescaler(TIMER_TypeDef *TIMERx, uint16_t TIMER_ICPSC); -void TIMER_Set_IC2_Prescaler(TIMER_TypeDef *TIMERx, uint16_t TIMER_ICPSC); -void TIMER_Set_IC3_Prescaler(TIMER_TypeDef *TIMERx, uint16_t TIMER_ICPSC); -void TIMER_Set_IC4_Prescaler(TIMER_TypeDef *TIMERx, uint16_t TIMER_ICPSC); - -/* Interrupts, DMA and flags management ***************************************/ -void TIMER_INTConfig(TIMER_TypeDef *TIMERx, uint16_t TIMER_INT, TypeState NewValue); -void TIMER_GenerateEvent(TIMER_TypeDef *TIMERx, uint16_t TIMER_EventSrc); -TypeState TIMER_GetBitState(TIMER_TypeDef *TIMERx, uint16_t TIMER_FLAG); -void TIMER_ClearBitState(TIMER_TypeDef *TIMERx, uint16_t TIMER_FLAG); -TypeState TIMER_GetIntBitState(TIMER_TypeDef *TIMERx, uint16_t TIMER_INT); -void TIMER_ClearIntBitState(TIMER_TypeDef *TIMERx, uint16_t TIMER_INT); -void TIMER_DMAConfig(TIMER_TypeDef *TIMERx, uint16_t TIMER_DMABase, uint16_t TIMER_DMABurstLength); -void TIMER_DMACmd(TIMER_TypeDef *TIMERx, uint16_t TIMER_DMASrc, TypeState NewValue); -void TIMER_CC_DMA(TIMER_TypeDef *TIMERx, TypeState NewValue); - -/* Clocks management **********************************************************/ -void TIMER_InternalClockConfig(TIMER_TypeDef *TIMERx); -void TIMER_ITRxExtClock(TIMER_TypeDef *TIMERx, uint16_t TIMER_InputTriSrc); -void TIMER_TIxExtCLkConfig(TIMER_TypeDef *TIMERx, uint16_t TIMER_TIxExCLKSrc, - uint16_t TIMER_ICPolarity, uint16_t ICFilter); -void TIMER_ETRClockMode1Config(TIMER_TypeDef *TIMERx, uint16_t TIMER_ExTriPrescaler, uint16_t TIMER_ExTriPolarity, - uint16_t ExtTriFilter); -void TIMER_ETRClockMode2Config(TIMER_TypeDef *TIMERx, uint16_t TIMER_ExTriPrescaler, - uint16_t TIMER_ExTriPolarity, uint16_t ExtTriFilter); -/* Synchronization management *************************************************/ -void TIMER_SelectInputTrigger(TIMER_TypeDef *TIMERx, uint16_t TIMER_InputTriSrc); -void TIMER_SelectOutputTrigger(TIMER_TypeDef *TIMERx, uint16_t TIMER_TriOutSrc); -void TIMER_SelectSlaveMode(TIMER_TypeDef *TIMERx, uint16_t TIMER_SlaveMode); -void TIMER_SelectMasterSlaveMode(TIMER_TypeDef *TIMERx, uint16_t TIMER_MasterSlaveMode); -void TIMER_ETRConfig(TIMER_TypeDef *TIMERx, uint16_t TIMER_ExTriPrescaler, uint16_t TIMER_ExTriPolarity, - uint16_t ExtTriFilter); - -/* Specific interface management **********************************************/ -void TIMER_EncoderInterfaceConfig(TIMER_TypeDef *TIMERx, uint16_t TIMER_EncoderMode, - uint16_t TIMER_IC1Polarity, uint16_t TIMER_IC2Polarity); -void TIMER_SelectHallSensor(TIMER_TypeDef *TIMERx, TypeState NewValue); - -/** - * @} - */ - -#ifdef __cplusplus -} -#endif - -#endif /*__GD32F10X_TIMER_H */ - -/** - * @} - */ - -/** - * @} - */ diff --git a/bsp/gd32103c-eval/Libraries/GD32F1xx_standard_peripheral/Include/gd32f10x_usart.h b/bsp/gd32103c-eval/Libraries/GD32F1xx_standard_peripheral/Include/gd32f10x_usart.h deleted file mode 100644 index dec1f603a1..0000000000 --- a/bsp/gd32103c-eval/Libraries/GD32F1xx_standard_peripheral/Include/gd32f10x_usart.h +++ /dev/null @@ -1,297 +0,0 @@ -/** - ****************************************************************************** - * @brief USART header file of the firmware library. - ****************************************************************************** - */ - -/* Define to prevent recursive inclusion -------------------------------------*/ -#ifndef __GD32F10X_USART_H -#define __GD32F10X_USART_H - -#ifdef __cplusplus -extern "C" { -#endif - -/* Includes ------------------------------------------------------------------*/ -#include "gd32f10x.h" - -/** @addtogroup GD32F10x_Firmware - * @{ - */ - -/** @addtogroup USART - * @{ - */ - -/** @defgroup USART_Exported_Types - * @{ - */ - -/** - * @brief USART Initial Parameters - */ -typedef struct { - uint32_t USART_BRR; /*!< the USART communication baud rate configuration */ - uint16_t USART_WL; /*!< Set by USART_CTLR1_WL Word length 0: 8 Data bits, - 1: 9 Data bits */ - uint16_t USART_STBits; /*!< Stop bits configuration */ - - uint16_t USART_Parity; /*!< Set by USART_CTLR1_PCEN */ - - uint16_t USART_RxorTx; /*!< Specifies wether the Receive or Transmit mode is enabled or disabled. */ - - uint16_t USART_HardwareFlowControl; /*!< Specifies wether the hardware flow control mode is enabled - or disabled.This parameter can be a value of @ref USART_Hardware_Flow_Control */ -} USART_InitPara; - -/** - * @brief USART Clock Init Structure definition - */ - -typedef struct { - uint16_t USART_CKEN; /*!< USART clock enabled this parameter can be a value of @ref USART_CKEN */ - - uint16_t USART_CPL; /*!< Clock polarity of Steady state this parameter can be a value of @ref USART_Clock_Polarity */ - - uint16_t USART_CPH; /*!< Clock phase this parameter can be a value of @ref USART_Clock_Phase */ - - uint16_t USART_LBCP; /*!< Last bit clock pulse this parameter can be a value of @ref USART_Last_Bit */ -} USART_ClockInitPara; - -/** - * @} - */ - -/** @defgroup USART_Exported_Constants - * @{ - */ - -/** @defgroup USART_WL - * @{ - */ -#define USART_WL_8B ((uint16_t)0x0000) -#define USART_WL_9B USART_CTLR1_WL - -/** - * @} - */ - -/** @defgroup USART_STBits - * @{ - */ -#define USART_STBITS_1 ((uint16_t)0x0000) -#define USART_STBITS_0_5 ((uint16_t)0x1000) -#define USART_STBITS_2 USART_CTLR2_STB_1 -#define USART_STBITS_1_5 (USART_CTLR2_STB_0 | USART_CTLR2_STB_1) -/** - * @} - */ - -/** @defgroup USART_Parity - * @{ - */ -#define USART_PARITY_RESET ((uint16_t)0x0000) -#define USART_PARITY_SETEVEN USART_CTLR1_PCEN -#define USART_PARITY_SETODD (USART_CTLR1_PCEN | USART_CTLR1_PM) - -/** - * @} - */ - -/** @defgroup USART_RxorTx - * @{ - */ -#define USART_RXORTX_RX USART_CTLR1_REN -#define USART_RXORTX_TX USART_CTLR1_TEN - -/** - * @} - */ - -/** @defgroup USART_Hardware_Flow_Control - * @{ - */ -#define USART_HARDWAREFLOWCONTROL_NONE ((uint16_t)0x0000) -#define USART_HARDWAREFLOWCONTROL_RTS USART_CTLR3_RTSEN -#define USART_HARDWAREFLOWCONTROL_CTS USART_CTLR3_CTSEN -#define USART_HARDWAREFLOWCONTROL_RTS_CTS (USART_CTLR3_RTSEN | USART_CTLR3_CTSEN) - -/** - * @} - */ - -/** @defgroup USART_CKEN - * @{ - */ -#define USART_CKEN_RESET ((uint16_t)0x0000) -#define USART_CKEN_SET USART_CTLR2_CKEN - -/** - * @} - */ - -/** @defgroup USART_Clock_Polarity - * @{ - */ -#define USART_CPL_LOW ((uint16_t)0x0000) -#define USART_CPL_HIGH USART_CTLR2_CPL - -/** - * @} - */ - -/** @defgroup USART_Clock_Phase - * @{ - */ -#define USART_CPH_1EDGE ((uint16_t)0x0000) -#define USART_CPH_2EDGE USART_CTLR2_CPH - -/** - * @} - */ - -/** @defgroup USART_Last_Bit - * @{ - */ -#define USART_LBCP_DISABLE ((uint16_t)0x0000) -#define USART_LBCP_ENABLE USART_CTLR2_LBCP - -/** - * @} - */ - -/** @defgroup USART_DMA_Requests - * @{ - */ -#define USART_DMAREQ_TX USART_CTLR3_DENT -#define USART_DMAREQ_RX USART_CTLR3_DENR -/** - * @} - */ -/** @defgroup USART_Interrupt_definition - * @brief USART Interrupt definition - * USART_INT possible values - * @{ - */ -#define USART_INT_PE ((uint16_t)0x0028) -#define USART_INT_TBE ((uint16_t)0x0727) -#define USART_INT_TC ((uint16_t)0x0626) -#define USART_INT_RBNE ((uint16_t)0x0525) -#define USART_INT_IDLEF ((uint16_t)0x0424) -#define USART_INT_LBDF ((uint16_t)0x0846) -#define USART_INT_CTSF ((uint16_t)0x096A) -#define USART_INT_ERIE ((uint16_t)0x0060) -#define USART_INT_ORE ((uint16_t)0x0360) -#define USART_INT_NE ((uint16_t)0x0260) -#define USART_INT_FE ((uint16_t)0x0160) - -/** - * @} - */ - - - -/** @defgroup USART_MuteMode_WakeUp_methods - * @{ - */ -#define USART_WAKEUP_IDLELINE ((uint16_t)0x0000) -#define USART_WAKEUP_ADDRESSMARK USART_CTLR1_WM - -/** - * @} - */ - - -/** @defgroup USART_LIN_Break_Detection_Length - * @{ - */ -#define USART_LINBREAKDETECTLENGTH_10B ((uint16_t)0x0000) -#define USART_LINBREAKDETECTLENGTH_11B USART_CTLR2_LBDL - -/** - * @} - */ - -/** @defgroup USART_IrDA_Low_Power - * @{ - */ -#define USART_IRDAMODE_LOWPOWER USART_CTLR3_IRLP -#define USART_IRDAMODE_NORMAL ((uint16_t)0x0000) - -/** - * @} - */ - -/** @defgroup USART_Flags - * @{ - */ - -#define USART_FLAG_CTSF ((uint16_t)0x0200) -#define USART_FLAG_LBDF ((uint16_t)0x0100) -#define USART_FLAG_TBE ((uint16_t)0x0080) -#define USART_FLAG_TC ((uint16_t)0x0040) -#define USART_FLAG_RBNE ((uint16_t)0x0020) -#define USART_FLAG_IDLEF ((uint16_t)0x0010) -#define USART_FLAG_ORE ((uint16_t)0x0008) -#define USART_FLAG_NE ((uint16_t)0x0004) -#define USART_FLAG_FE ((uint16_t)0x0002) -#define USART_FLAG_PE ((uint16_t)0x0001) -/** - * @} - */ - - - -/** - * @} - */ - -/** @defgroup USART_Exported_Functions - * @{ - */ - -void USART_DeInit(USART_TypeDef *USARTx); -void USART_Init(USART_TypeDef *USARTx, USART_InitPara *USART_InitParaStruct); -void USART_ParaInit(USART_InitPara *USART_InitParaStruct); -void USART_ClockInit(USART_TypeDef *USARTx, USART_ClockInitPara *USART_ClockInitStruct); -void USART_ClockStructInit(USART_ClockInitPara *USART_ClockInitParaStruct); -void USART_Enable(USART_TypeDef *USARTx, TypeState NewValue); -void USART_HalfDuplex_Enable(USART_TypeDef *USARTx, TypeState NewValue); -void USART_SetPrescaler(USART_TypeDef *USARTx, uint8_t USART_Prescaler); -void USART_DataSend(USART_TypeDef *USARTx, uint16_t Data); -uint16_t USART_DataReceive(USART_TypeDef *USARTx); -void USART_Address(USART_TypeDef *USARTx, uint8_t USART_Address); -void USART_MuteMode_Enable(USART_TypeDef *USARTx, TypeState NewState); -void USART_MuteModeWakeUp_Set(USART_TypeDef *USARTx, uint16_t USART_WakeUp); -void USART_SetLINBDLength(USART_TypeDef *USARTx, uint16_t USART_LINBreakDetectLength); -void USART_LIN_Enable(USART_TypeDef *USARTx, TypeState NewValue); -void USART_GuardTime_Set(USART_TypeDef *USARTx, uint8_t USART_GuardTime); -void USART_SmartCard_Enable(USART_TypeDef *USARTx, TypeState NewValue); -void USART_SmartCardNACK_Enable(USART_TypeDef *USARTx, TypeState NewValue); -void USART_IrDA_Set(USART_TypeDef *USARTx, uint16_t USART_IrDAMode); -void USART_IrDA_Enable(USART_TypeDef *USARTx, TypeState NewValue); -void USART_DMA_Enable(USART_TypeDef *USARTx, uint16_t USART_DMAEnable, TypeState NewValue); -void USART_INT_Set(USART_TypeDef *USARTx, uint16_t USART_INT, TypeState NewValue); -TypeState USART_GetBitState(USART_TypeDef *USARTx, uint16_t USART_FLAG); -void USART_ClearBitState(USART_TypeDef *USARTx, uint16_t USART_FLAG); -TypeState USART_GetIntBitState(USART_TypeDef *USARTx, uint16_t USART_INT); -void USART_ClearIntBitState(USART_TypeDef *USARTx, uint16_t USART_INT); -void USART_SendBreak(USART_TypeDef *USARTx); - -#ifdef __cplusplus -} -#endif - -#endif /*__GD32F10X_USART_H */ -/** - * @} - */ - -/** - * @} - */ - -/** - * @} - */ - diff --git a/bsp/gd32103c-eval/Libraries/GD32F1xx_standard_peripheral/Include/gd32f10x_wwdg.h b/bsp/gd32103c-eval/Libraries/GD32F1xx_standard_peripheral/Include/gd32f10x_wwdg.h deleted file mode 100644 index 751defeb8e..0000000000 --- a/bsp/gd32103c-eval/Libraries/GD32F1xx_standard_peripheral/Include/gd32f10x_wwdg.h +++ /dev/null @@ -1,77 +0,0 @@ -/** - ****************************************************************************** - * @brief WWDG header file of the firmware library. - ****************************************************************************** - */ - -/* Define to prevent recursive inclusion -------------------------------------*/ -#ifndef __GD32F10X_WWDG_H -#define __GD32F10X_WWDG_H - -#ifdef __cplusplus -extern "C" { -#endif - -/* Includes ------------------------------------------------------------------*/ -#include "gd32f10x.h" - -/** @addtogroup GD32F10x_Firmware - * @{ - */ - -/** @defgroup WWDG - * @{ - */ - -/** @defgroup WWDG_Exported_Constants - * @{ - */ - -/** @defgroup WWDG_PRESCALER - * @{ - */ -#define WWDG_PRESCALER_1 ((uint32_t)0x00000000) -#define WWDG_PRESCALER_2 ((uint32_t)0x00000080) -#define WWDG_PRESCALER_4 ((uint32_t)0x00000100) -#define WWDG_PRESCALER_8 ((uint32_t)0x00000180) - -/** - * @} - */ - -/** - * @} - */ - -/* Exported functions ------------------------------------------------------- */ -/** @defgroup WWDG_Exported_Functions - * @{ - */ - -void WWDG_DeInit(void); -void WWDG_SetPrescalerValue(uint32_t PrescalerValue); -void WWDG_SetWindowValue(uint8_t WindowValue); -void WWDG_EnableInt(void); -void WWDG_SetCounterValue(uint8_t CounterValue); -void WWDG_Enable(uint8_t CounterValue); -TypeState WWDG_GetBitState(void); -void WWDG_ClearBitState(void); - -/** - * @} - */ - -#ifdef __cplusplus -} -#endif - -#endif /* __GD32F10X_WWDG_H */ - -/** - * @} - */ - -/** - * @} - */ - diff --git a/bsp/gd32103c-eval/Libraries/GD32F1xx_standard_peripheral/Source/gd32f10x_adc.c b/bsp/gd32103c-eval/Libraries/GD32F1xx_standard_peripheral/Source/gd32f10x_adc.c deleted file mode 100644 index 9d6205e1b2..0000000000 --- a/bsp/gd32103c-eval/Libraries/GD32F1xx_standard_peripheral/Source/gd32f10x_adc.c +++ /dev/null @@ -1,977 +0,0 @@ -/** - ****************************************************************************** - * @brief ADC functions of the firmware library. - ****************************************************************************** - */ - -/* Includes ------------------------------------------------------------------*/ -#include "gd32f10x_adc.h" -#include "gd32f10x_rcc.h" - -/** @addtogroup GD32F10x_Firmware - * @{ - */ - -/** @defgroup ADC - * @brief ADC driver modules - * @{ - */ - -/** @defgroup ADC_Private_Defines - * @{ - */ - -/* ADC CTLR1_DISNUM mask */ -#define CTLR1_DISNUM_RESET ((uint32_t)0xFFFF1FFF) - -/* ADC CTLR1_DISRC mask */ -#define CTLR1_DISRC_SET ((uint32_t)0x00000800) - -/* ADC CTLR1_ICA mask */ -#define CTLR1_ICA_SET ((uint32_t)0x00000400) - -/* ADC CTLR1_DISIC mask */ -#define CTLR1_DISIC_SET ((uint32_t)0x00001000) - -/* ADC CTLR1_AWCS mask */ -#define CTLR1_AWCS_RESET ((uint32_t)0xFFFFFFE0) - -/* ADC CTLR1_AWDMode mask */ -#define CTLR1_AWDMODE_RESET ((uint32_t)0xFF3FFDFF) - -/* CTLR1 register mask */ -#define CTLR1_BITS_CLEAR ((uint32_t)0xFFF0FEFF) - -/* ADC CTLR2_ADCON mask */ -#define CTLR2_ADCON_SET ((uint32_t)0x00000001) - -/* ADC CTLR2_DMA mask */ -#define CTLR2_DMA_SET ((uint32_t)0x00000100) - -/* ADC CTLR2_RSTCLB mask */ -#define CTLR2_RSTCLB_SET ((uint32_t)0x00000008) - -/* ADC CTLR2_CLB mask */ -#define CTLR2_CLB_SET ((uint32_t)0x00000004) - -/* ADC CTLR2_SWRCST mask */ -#define CTLR2_SWRCST_SET ((uint32_t)0x00400000) - -/* ADC CTLR2_ETERC mask */ -#define CTLR2_ETERC_SET ((uint32_t)0x00100000) - -/* ADC CTLR2_ETERC_SWRCST mask */ -#define CTLR2_ETERC_SWRCST_SET ((uint32_t)0x00500000) - -/* ADC CTLR2_ETSIC mask */ -#define CTLR2_ETSIC_RESET ((uint32_t)0xFFFF8FFF) - -/* ADC CTLR2_ETEIC mask */ -#define CTLR2_ETEIC_SET ((uint32_t)0x00008000) - -/* ADC CTLR2_SWICST mask */ -#define CTLR2_SWICST_SET ((uint32_t)0x00200000) - -/* ADC CTLR2_ETEIC_SWICST mask */ -#define CTLR2_ETEIC_SWICST_SET ((uint32_t)0x00208000) - -/* ADC CTLR2_TSVREN mask */ -#define CTLR2_TSVREN_SET ((uint32_t)0x00800000) - -/* CTLR2 register mask */ -#define CTLR2_BITS_CLEAR ((uint32_t)0xFFF1F7FD) - -/* ADC RSQx mask */ -#define RSQ3_RSQ_SET ((uint32_t)0x0000001F) -#define RSQ2_RSQ_SET ((uint32_t)0x0000001F) -#define RSQ1_RSQ_SET ((uint32_t)0x0000001F) - -/* RSQ1 register mask */ -#define RSQ1_BITS_CLEAR ((uint32_t)0xFF0FFFFF) - -/* ADC ISQx mask */ -#define ISQ_ISQ_SET ((uint32_t)0x0000001F) - -/* ADC IL mask */ -#define ISQ_IL_SET ((uint32_t)0x00300000) - -/* ADC SPTx mask */ -#define SPT1_SPT_SET ((uint32_t)0x00000007) -#define SPT2_SPT_SET ((uint32_t)0x00000007) - -/* ADC IDTRx registers offset */ -#define IDTR_OFFSET ((uint8_t)0x28) - -/* ADC0 RDTR register base address */ -#define RDTR_ADDRESS ((uint32_t)0x4001244C) - -/** - * @} - */ - -/** @defgroup ADC_Private_Functions - * @{ - */ - -/** - * @brief Reset the ADC interface and init the sturct ADC_InitPara. - * @param ADCx: the ADC interface where x can be 1..3. - * @param ADC_InitParaStruct : the sturct ADC_InitPara pointer. - * @retval None - */ -void ADC_DeInit(ADC_TypeDef *ADCx, ADC_InitPara *ADC_InitParaStruct) -{ - if (ADCx == ADC0) { - /* Enable ADC0 reset state */ - RCC_APB2PeriphReset_Enable(RCC_APB2PERIPH_ADC0RST, ENABLE); - /* Release ADC0 from reset state */ - RCC_APB2PeriphReset_Enable(RCC_APB2PERIPH_ADC0RST, DISABLE); - } else if (ADCx == ADC1) { - /* Enable ADC1 reset state */ - RCC_APB2PeriphReset_Enable(RCC_APB2PERIPH_ADC1RST, ENABLE); - /* Release ADC1 from reset state */ - RCC_APB2PeriphReset_Enable(RCC_APB2PERIPH_ADC1RST, DISABLE); - } - /* Initialize the ADC_Mode member,independent mode */ - ADC_InitParaStruct->ADC_Mode = ADC_MODE_INDEPENDENT; - /* Initialize the ADC_Mode_Scan member,disable scan mode */ - ADC_InitParaStruct->ADC_Mode_Scan = DISABLE; - /* Initialize the ADC_Mode_Continuous member,disable continuous mode */ - ADC_InitParaStruct->ADC_Mode_Continuous = DISABLE; - /* Initialize the ADC_Trig_External member,choose T1 CC1 as external trigger */ - ADC_InitParaStruct->ADC_Trig_External = ADC_EXTERNAL_TRIGGER_MODE_T1_CC1; - /* Initialize the ADC_Data_Align member,specifies the ADC data alignment right */ - ADC_InitParaStruct->ADC_Data_Align = ADC_DATAALIGN_RIGHT; - /* Initialize the ADC_Channel_Number member,only 1 channel */ - ADC_InitParaStruct->ADC_Channel_Number = 1; -} - -/** - * @brief Initialize the ADCx interface parameters. - * @param ADCx: the ADC interface where x can be 1..3. - * @param ADC_InitParaStruct: the sturct ADC_InitPara pointer. - * @retval None - */ -void ADC_Init(ADC_TypeDef *ADCx, ADC_InitPara *ADC_InitParaStruct) -{ - uint32_t temp1 = 0; - uint8_t temp2 = 0; - /* ADCx CTLR1 Configuration */ - /* Get the ADCx CTLR1 previous value */ - temp1 = ADCx->CTLR1; - /* Clear SM bits */ - temp1 &= CTLR1_BITS_CLEAR; - /* Configure ADCx: Dual mode and scan conversion mode */ - /* Set DUALMOD bits according to ADC_Mode value */ - /* Configure SCAN bit according to ADC_Mode_Scan value */ - temp1 |= (uint32_t)(ADC_InitParaStruct->ADC_Mode | ((uint32_t)ADC_InitParaStruct->ADC_Mode_Scan << 8)); - /* Write new value to ADCx CTLR1 */ - ADCx->CTLR1 = temp1; - - /* ADCx CTLR2 Configuration */ - /* Get the ADCx CTLR2 previous value */ - temp1 = ADCx->CTLR2; - /* Clear CTN, DAL and ETSRC bits */ - temp1 &= CTLR2_BITS_CLEAR; - /* Configure ADCx: select external trigger mode and continuous conversion mode */ - /* Configure DAL bit according to ADC_Data_Align value */ - /* Configure ETSRC bits according to ADC_Trig_External value */ - /* Configure CTN bit according to ADC_Mode_Continuous value */ - temp1 |= (uint32_t)(ADC_InitParaStruct->ADC_Data_Align | ADC_InitParaStruct->ADC_Trig_External | - ((uint32_t)ADC_InitParaStruct->ADC_Mode_Continuous << 1)); - /* Write new value to ADCx CTLR2 */ - ADCx->CTLR2 = temp1; - - /* ADCx RSQ1 Configuration */ - /* Get the ADCx RSQ1 previous value */ - temp1 = ADCx->RSQ1; - /* Clear RL bits */ - temp1 &= RSQ1_BITS_CLEAR; - /* Configure ADCx: regular channel sequence length */ - /* Configure RL bits according to ADC_Channel_Number value */ - temp2 |= (uint8_t)(ADC_InitParaStruct->ADC_Channel_Number - (uint8_t)1); - temp1 |= (uint32_t)temp2 << 20; - /* Write new value to ADCx RSQ1 */ - ADCx->RSQ1 = temp1; -} - -/** - * @brief Enable or disable the ADCx interface. - * @param ADCx: the ADC interface where x can be 1..3. - * @param NewValue: New state of the ADCx interface. - * This parameter can be: ENABLE or DISABLE. - * @retval None - */ -void ADC_Enable(ADC_TypeDef *ADCx, TypeState NewValue) -{ - if (NewValue != DISABLE) { - /* Enable the ADCx interface */ - ADCx->CTLR2 |= CTLR2_ADCON_SET; - } else { - /* Disable the ADCx interface */ - ADCx->CTLR2 &= ~CTLR2_ADCON_SET; - } -} - -/** - * @brief Enable or disable the ADCx DMA request. - * @param ADCx: the ADC interface where x can be 1..3. - * Note: ADC1 doesn't support DMA function. - * @param NewValue: New state of ADCx DMA transfer. - * This parameter can be: ENABLE or DISABLE. - * @retval None - */ -void ADC_DMA_Enable(ADC_TypeDef *ADCx, TypeState NewValue) -{ - if (NewValue != DISABLE) { - /* Enable ADCx DMA request */ - ADCx->CTLR2 |= CTLR2_DMA_SET; - } else { - /* Disable ADCx DMA request */ - ADCx->CTLR2 &= ~CTLR2_DMA_SET; - } -} - -/** - * @brief Enable or disable ADCx interrupts. - * @param ADCx: the ADC interface where x can be 1..3. - * @param ADC_INT: ADCx interrupt sources. - * This parameter can be any combination of the following values: - * @arg ADC_INT_EOC: Regular conversion over interrupt mask - * @arg ADC_INT_AWE: Analog watchdog interrupt mask - * @arg ADC_INT_EOIC: Inserted conversion over interrupt mask - * @param NewValue: ADCx interrupts state. - * This parameter can be: ENABLE or DISABLE. - * @retval None - */ -void ADC_INTConfig(ADC_TypeDef *ADCx, uint16_t ADC_INT, TypeState NewValue) -{ - uint8_t temp_it = 0; - /* ADCx INT old state */ - temp_it = (uint8_t)ADC_INT; - if (NewValue != DISABLE) { - /* Enable the ADCx interrupt */ - ADCx->CTLR1 |= temp_it; - } else { - /* Disable the ADCx interrupt */ - ADCx->CTLR1 &= (~(uint32_t)temp_it); - } -} - -/** - * @brief ADCx calibration. - * @param ADCx: the ADC interface where x can be 1..3. - * @retval None - */ -void ADC_Calibration(ADC_TypeDef *ADCx) -{ - /* Reset the selected ADCx calibration registers */ - ADCx->CTLR2 |= CTLR2_RSTCLB_SET; - /* Check the RSTCLB bit state */ - while ((ADCx->CTLR2 & CTLR2_RSTCLB_SET)); - /* Enable ADCx calibration process */ - ADCx->CTLR2 |= CTLR2_CLB_SET; - /* Check the CLB bit state */ - while ((ADCx->CTLR2 & CTLR2_CLB_SET) != (uint32_t)RESET); -} - -/** - * @brief Enable or disable ADCx software start conversion. - * @param ADCx: the ADC interface where x can be 1..3. - * @param NewValue: ADCx software start conversion state. - * This parameter can be: ENABLE or DISABLE. - * @retval None - */ -void ADC_SoftwareStartConv_Enable(ADC_TypeDef *ADCx, TypeState NewValue) -{ - if (NewValue != DISABLE) { - /* ADCx software conversion start */ - ADCx->CTLR2 |= CTLR2_ETERC_SWRCST_SET; - } else { - /* ADCx software conversion stop */ - ADCx->CTLR2 &= ~CTLR2_ETERC_SWRCST_SET; - } -} - -/** - * @brief Get the bit state of ADCx software start conversion. - * @param ADCx: the ADC interface where x can be 1..3. - * @retval ADCx software start conversion state(SET or RESET). - */ -TypeState ADC_GetSoftwareStartConvBitState(ADC_TypeDef *ADCx) -{ - /* Check the SWRCST bit state*/ - if ((ADCx->CTLR2 & CTLR2_SWRCST_SET) != (uint32_t)RESET) { - return SET; - } else { - return RESET; - } -} - -/** - * @brief Configure the ADCx channel discontinuous mode. - * @param ADCx: the ADC interface where x can be 1..3. - * @param Number: the count value of discontinuous mode regular channel. - * This number must be 1~8. - * @retval None - */ -void ADC_DiscModeChannelCount_Config(ADC_TypeDef *ADCx, uint8_t Number) -{ - uint32_t temp1 = 0; - uint32_t temp2 = 0; - /* Get the old value of CTLR1 */ - temp1 = ADCx->CTLR1; - /* Clear discontinuous mode channel count */ - temp1 &= CTLR1_DISNUM_RESET; - /* Set the discontinuous mode channel count */ - temp2 = Number - 1; - temp1 |= temp2 << 13; - /* Write new value to CTLR1 */ - ADCx->CTLR1 = temp1; -} - -/** - * @brief Enable or disable the discontinuous mode. - * @param ADCx: the ADC interface where x can be 1..3. - * @param NewValue: ADCx discontinuous mode state. - * This parameter can be: ENABLE or DISABLE. - * @retval None - */ -void ADC_DiscMode_Enable(ADC_TypeDef *ADCx, TypeState NewValue) -{ - if (NewValue != DISABLE) { - /* Enable ADCx regular discontinuous mode */ - ADCx->CTLR1 |= CTLR1_DISRC_SET; - } else { - /* Disable ADCx regular discontinuous mode */ - ADCx->CTLR1 &= ~CTLR1_DISRC_SET; - } -} - -/** - * @brief Configure array and sample time. - * @param ADCx: the ADC interface where x can be 1..3. - * @param ADC_Channel: the selected ADC channel. - * This parameter can be as follows: - * @arg ADC_CHANNEL_0: ADC Channel0 - * @arg ADC_CHANNEL_1: ADC Channel1 - * @arg ADC_CHANNEL_2: ADC Channel2 - * @arg ADC_CHANNEL_3: ADC Channel3 - * @arg ADC_CHANNEL_4: ADC Channel4 - * @arg ADC_CHANNEL_5: ADC Channel5 - * @arg ADC_CHANNEL_6: ADC Channel6 - * @arg ADC_CHANNEL_7: ADC Channel7 - * @arg ADC_CHANNEL_8: ADC Channel8 - * @arg ADC_CHANNEL_9: ADC Channel9 - * @arg ADC_CHANNEL_10: ADC Channel10 - * @arg ADC_CHANNEL_11: ADC Channel11 - * @arg ADC_CHANNEL_12: ADC Channel12 - * @arg ADC_CHANNEL_13: ADC Channel13 - * @arg ADC_CHANNEL_14: ADC Channel14 - * @arg ADC_CHANNEL_15: ADC Channel15 - * @arg ADC_CHANNEL_16: ADC Channel16 - * @arg ADC_CHANNEL_17: ADC Channel17 - * @param Array: The regular group sequencer rank. This parameter must be between 1 to 16. - * @param ADC_SampleTime: The sample time value. - * This parameter can be one of the following values: - * @arg ADC_SAMPLETIME_1POINT5: 1.5 cycles - * @arg ADC_SAMPLETIME_7POINT5: 7.5 cycles - * @arg ADC_SAMPLETIME_13POINT5: 13.5 cycles - * @arg ADC_SAMPLETIME_28POINT5: 28.5 cycles - * @arg ADC_SAMPLETIME_41POINT5: 41.5 cycles - * @arg ADC_SAMPLETIME_55POINT5: 55.5 cycles - * @arg ADC_SAMPLETIME_71POINT5: 71.5 cycles - * @arg ADC_SAMPLETIME_239POINT5: 239.5 cycles - * @retval None - */ -void ADC_RegularChannel_Config(ADC_TypeDef *ADCx, uint8_t ADC_Channel, uint8_t Array, uint8_t ADC_SampleTime) -{ - uint32_t temp1 = 0, temp2 = 0; - - /* if ADC_Channel is between 10 to 17 */ - if (ADC_Channel > ADC_CHANNEL_9) { - /* Get SPT1 value */ - temp1 = ADCx->SPT1; - /* Calculate the mask to clear */ - temp2 = SPT1_SPT_SET << (3 * (ADC_Channel - 10)); - /* Clear sample time */ - temp1 &= ~temp2; - /* Calculate the mask to set */ - temp2 = (uint32_t)ADC_SampleTime << (3 * (ADC_Channel - 10)); - /* Configure sample time */ - temp1 |= temp2; - /* Write to SPT1 */ - ADCx->SPT1 = temp1; - } else { /* ADC_Channel is between 0 to 9 */ - /* Get SPT2 value */ - temp1 = ADCx->SPT2; - /* Calculate the mask to clear */ - temp2 = SPT2_SPT_SET << (3 * ADC_Channel); - /* Clear sample time */ - temp1 &= ~temp2; - /* Calculate the mask to set */ - temp2 = (uint32_t)ADC_SampleTime << (3 * ADC_Channel); - /* Set sample time */ - temp1 |= temp2; - /* Write to SPT2 */ - ADCx->SPT2 = temp1; - } - /* For Array 1 to 6 */ - if (Array < 7) { - /* Get RSQ3 value */ - temp1 = ADCx->RSQ3; - /* Calculate the mask to clear */ - temp2 = RSQ3_RSQ_SET << (5 * (Array - 1)); - /* Clear RSQ3 bits */ - temp1 &= ~temp2; - /* Calculate the mask to set */ - temp2 = (uint32_t)ADC_Channel << (5 * (Array - 1)); - /* Configure the RSQ3 bits */ - temp1 |= temp2; - /* Write to RSQ3 */ - ADCx->RSQ3 = temp1; - } - /* For Array 7 to 12 */ - else if (Array < 13) { - /* Get RSQ2 value */ - temp1 = ADCx->RSQ2; - /* Calculate the mask to clear */ - temp2 = RSQ2_RSQ_SET << (5 * (Array - 7)); - /* Clear the old RSQ2 bits */ - temp1 &= ~temp2; - /* Calculate the mask to set */ - temp2 = (uint32_t)ADC_Channel << (5 * (Array - 7)); - /* Set the RSQ2 bits */ - temp1 |= temp2; - /* Write to RSQ2 */ - ADCx->RSQ2 = temp1; - } - /* For Array 13 to 16 */ - else { - /* Get RSQ1 value */ - temp1 = ADCx->RSQ1; - /* Calculate the mask to clear */ - temp2 = RSQ1_RSQ_SET << (5 * (Array - 13)); - /* Clear the old RSQ1 bits */ - temp1 &= ~temp2; - /* Calculate the mask to set */ - temp2 = (uint32_t)ADC_Channel << (5 * (Array - 13)); - /* Set the RSQ1 bits */ - temp1 |= temp2; - /* Write to RSQ1 */ - ADCx->RSQ1 = temp1; - } -} - -/** - * @brief Enable or disable the ADCx external conversion. - * @param ADCx: the ADC interface where x can be 1..3. - * @param NewValue: ADCx external trigger state. - * This parameter can be: ENABLE or DISABLE. - * @retval None - */ -void ADC_ExternalTrigConv_Enable(ADC_TypeDef *ADCx, TypeState NewValue) -{ - if (NewValue != DISABLE) { - /* Enable external trigger conversion */ - ADCx->CTLR2 |= CTLR2_ETERC_SET; - } else { - /* Disable external trigger conversion */ - ADCx->CTLR2 &= ~CTLR2_ETERC_SET; - } -} - -/** - * @brief Return the ADCx regular channel conversion data. - * @param ADCx: the ADC interface where x can be 1..3. - * @retval conversion data. - */ -uint16_t ADC_GetConversionValue(ADC_TypeDef *ADCx) -{ - /* Return ADCx conversion data */ - return (uint16_t) ADCx->RDTR; -} - -/** - * @brief Return the last ADC0 and ADC1 conversion result data in dual mode. - * @retval The Data conversion value. - */ -uint32_t ADC_GetDualModeConversionValue(void) -{ - /* Return conversion value */ - return (*(__IO uint32_t *) RDTR_ADDRESS); -} -/** - * @brief Enable or disable ADCx automatic inserted conversion. - * @param ADCx: the ADC interface where x can be 1..3. - * @param NewValue: ADCx auto inserted conversion state. - * This parameter can be: ENABLE or DISABLE. - * @retval None - */ -void ADC_AutoInsertedConv_Enable(ADC_TypeDef *ADCx, TypeState NewValue) -{ - if (NewValue != DISABLE) { - /* Enable ADCx automatic inserted conversion */ - ADCx->CTLR1 |= CTLR1_ICA_SET; - } else { - /* Disable ADCx automatic inserted conversion */ - ADCx->CTLR1 &= ~CTLR1_ICA_SET; - } -} - -/** - * @brief Enable or disable the discontinuous mode for ADCx inserted group channel. - * @param ADCx: the ADC interface where x can be 1..3. - * @param NewValue: ADCx discontinuous mode state. - * This parameter can be: ENABLE or DISABLE. - * @retval None - */ -void ADC_InsertedDiscMode_Enable(ADC_TypeDef *ADCx, TypeState NewValue) -{ - if (NewValue != DISABLE) { - /* Enable the inserted discontinuous mode of the selected ADC channel */ - ADCx->CTLR1 |= CTLR1_DISIC_SET; - } else { - /* Disable the inserted discontinuous mode of the selected ADC channel */ - ADCx->CTLR1 &= ~CTLR1_DISIC_SET; - } -} - -/** - * @brief Configure the ADCx inserted channels external trigger conversion. - * @param ADCx: the ADC interface where x can be 1..3. - * @param ADC_ExternalTrigInsertConv: ADC inserted conversion trigger. - * This parameter can be as follows: - * @arg ADC_EXTERNAL_TRIG_INSERTCONV_T1_TRGO: Timer1 TRIG event (used in ADC0, ADC1 and ADC2) - * @arg ADC_EXTERNAL_TRIG_INSERTCONV_T1_CC4: Timer1 capture compare4 (used in ADC0, ADC1 and ADC2) - * @arg ADC_EXTERNAL_TRIG_INSERTCONV_T2_TRGO: Timer2 TRIG event (used in ADC0 and ADC1) - * @arg ADC_EXTERNAL_TRIG_INSERTCONV_T2_CC1: Timer2 capture compare1 (used in ADC0 and ADC1) - * @arg ADC_EXTERNAL_TRIG_INSERTCONV_T3_CC4: Timer3 capture compare4 (used in ADC0 and ADC1) - * @arg ADC_EXTERNAL_TRIG_INSERTCONV_T4_TRGO: Timer4 TRIG event (used in ADC0 and ADC1) - * @arg ADC_EXTERNAL_TRIG_INSERTCONV_EXT_IT15_T8_CC4: External interrupt line 15 or Timer8 - * capture compare4 (used in ADC0 and ADC1) - * @arg ADC_EXTERNAL_TRIG_INSERTCONV_T4_CC3: Timer4 capture compare3 (used in ADC2) - * @arg ADC_EXTERNAL_TRIG_INSERTCONV_T8_CC2: Timer8 capture compare2 (used in ADC2) - * @arg ADC_EXTERNAL_TRIG_INSERTCONV_T8_CC4: Timer8 capture compare4 (used in ADC2) - * @arg ADC_EXTERNAL_TRIG_INSERTCONV_T5_TRGO: Timer5 TRIG event (used in ADC2) - * @arg ADC_EXTERNAL_TRIG_INSERTCONV_T5_CC4: Timer5 capture compare4 (used in ADC2) - * @arg ADC_EXTERNAL_TRIG_INSERTCONV_NONE: Inserted conversion started by software (used in ADC0, ADC1 and ADC2) - * @retval None - */ -void ADC_ExternalTrigInsertedConv_Config(ADC_TypeDef *ADCx, uint32_t ADC_ExternalTrigInsertConv) -{ - uint32_t temp = 0; - /* Get CRLR2 value */ - temp = ADCx->CTLR2; - /* Clear inserted external event */ - temp &= CTLR2_ETSIC_RESET; - /* Configure inserted external event */ - temp |= ADC_ExternalTrigInsertConv; - /* Write to CTLR2 */ - ADCx->CTLR2 = temp; -} - -/** - * @brief Enable or disable the ADCx inserted channels conversion through - * external trigger - * @param ADCx: the ADC interface where x can be 1..3. - * @param NewValue: ADCx external trigger start of inserted conversion state. - * This parameter can be: ENABLE or DISABLE. - * @retval None - */ -void ADC_ExternalTrigInsertedConv_Enable(ADC_TypeDef *ADCx, TypeState NewValue) -{ - if (NewValue != DISABLE) { - /* Enable external event */ - ADCx->CTLR2 |= CTLR2_ETEIC_SET; - } else { - /* Disable external event */ - ADCx->CTLR2 &= ~CTLR2_ETEIC_SET; - } -} - -/** - * @brief Enable or disable ADCx inserted channels conversion start. - * @param ADCx: the ADC interface where x can be 1..3. - * @param NewValue: ADC software start inserted conversion state. - * This parameter can be: ENABLE or DISABLE. - * @retval None - */ -void ADC_SoftwareStartInsertedConv_Enable(ADC_TypeDef *ADCx, TypeState NewValue) -{ - if (NewValue != DISABLE) { - /* Start ADCx inserted conversion */ - ADCx->CTLR2 |= CTLR2_ETEIC_SWICST_SET; - } else { - /* Stop ADCx inserted conversion */ - ADCx->CTLR2 &= ~CTLR2_ETEIC_SWICST_SET; - } -} - -/** - * @brief Get ADC Software start inserted conversion State. - * @param ADCx: the ADC interface where x can be 1..3. - * @retval ADC software start inserted conversion state(SET or RESET). - */ -TypeState ADC_GetSoftwareStartInsertedConvCmdBitState(ADC_TypeDef *ADCx) -{ - /* Check SWICST bit */ - if ((ADCx->CTLR2 & CTLR2_SWICST_SET) != (uint32_t)RESET) { - /* Set SWICST bit */ - return SET; - } else { - /* Reset SWICST bit */ - return RESET; - } -} - -/** - * @brief Configure Array and sample time for the selected ADC inserted channel. - * @param ADCx: the ADC interface where x can be 1..3. - * @param ADC_Channel: the selected ADC channel. - * This parameter can be as follows: - * @arg ADC_CHANNEL_0: ADC Channel0 - * @arg ADC_CHANNEL_1: ADC Channel1 - * @arg ADC_CHANNEL_2: ADC Channel2 - * @arg ADC_CHANNEL_3: ADC Channel3 - * @arg ADC_CHANNEL_4: ADC Channel4 - * @arg ADC_CHANNEL_5: ADC Channel5 - * @arg ADC_CHANNEL_6: ADC Channel6 - * @arg ADC_CHANNEL_7: ADC Channel7 - * @arg ADC_CHANNEL_8: ADC Channel8 - * @arg ADC_CHANNEL_9: ADC Channel9 - * @arg ADC_CHANNEL_10: ADC Channel10 - * @arg ADC_CHANNEL_11: ADC Channel11 - * @arg ADC_CHANNEL_12: ADC Channel12 - * @arg ADC_CHANNEL_13: ADC Channel13 - * @arg ADC_CHANNEL_14: ADC Channel14 - * @arg ADC_CHANNEL_15: ADC Channel15 - * @arg ADC_CHANNEL_16: ADC Channel16 - * @arg ADC_CHANNEL_17: ADC Channel17 - * @param Array: The inserted group sequencer Array. This parameter must be between 1 and 4. - * @param ADC_SampleTime: The sample time of the selected channel. - * This parameter can be as follows: - * @arg ADC_SAMPLETIME_1POINT5: 1.5 cycles - * @arg ADC_SAMPLETIME_7POINT5: 7.5 cycles - * @arg ADC_SAMPLETIME_13POINT5: 13.5 cycles - * @arg ADC_SAMPLETIME_28POINT5: 28.5 cycles - * @arg ADC_SAMPLETIME_41POINT5: 41.5 cycles - * @arg ADC_SAMPLETIME_55POINT5: 55.5 cycles - * @arg ADC_SAMPLETIME_71POINT5: 71.5 cycles - * @arg ADC_SAMPLETIME_239POINT5: 239.5 cycles - * @retval None - */ -void ADC_InsertedChannel_Config(ADC_TypeDef *ADCx, uint8_t ADC_Channel, uint8_t Array, uint8_t ADC_SampleTime) -{ - uint32_t temp1 = 0, temp2 = 0, temp3 = 0; - - /* if ADC_Channel is between 10 to 17 */ - if (ADC_Channel > ADC_CHANNEL_9) { - /* Get SPT1 value */ - temp1 = ADCx->SPT1; - /* Calculate the sample time mask */ - temp2 = SPT1_SPT_SET << (3 * (ADC_Channel - 10)); - /* Clear sample time */ - temp1 &= ~temp2; - /* Calculate the sample time mask */ - temp2 = (uint32_t)ADC_SampleTime << (3 * (ADC_Channel - 10)); - /* Set sample time */ - temp1 |= temp2; - /* Write to SPT1 */ - ADCx->SPT1 = temp1; - } else { /* ADC_Channel is between 0 to 9 */ - /* Get SPT2 value */ - temp1 = ADCx->SPT2; - /* Calculate the sample time mask */ - temp2 = SPT2_SPT_SET << (3 * ADC_Channel); - /* Clear sample time */ - temp1 &= ~temp2; - /* Calculate the sample time mask */ - temp2 = (uint32_t)ADC_SampleTime << (3 * ADC_Channel); - /* Set sample time */ - temp1 |= temp2; - /* Write to SPT2 */ - ADCx->SPT2 = temp1; - } - /* Array configuration */ - /* Get ISQ value */ - temp1 = ADCx->ISQ; - /* Get IL value: Number = IL+1 */ - temp3 = (temp1 & ISQ_IL_SET) >> 20; - /* Calculate the ISQ mask : ((Array-1)+(4-IL-1)) */ - temp2 = ISQ_ISQ_SET << (5 * (uint8_t)((Array + 3) - (temp3 + 1))); - /* Clear ISQx bits */ - temp1 &= ~temp2; - /* Calculate the ISQ mask: ((Array-1)+(4-IL-1)) */ - temp2 = (uint32_t)ADC_Channel << (5 * (uint8_t)((Array + 3) - (temp3 + 1))); - /* Set ISQx bits */ - temp1 |= temp2; - /* Write to ISQ */ - ADCx->ISQ = temp1; -} - -/** - * @brief Configure the sequencer length of inserted channels - * @param ADCx: the ADC interface where x can be 1..3. - * @param Length: The sequencer length. - * This parameter must be a number between 1 to 4. - * @retval None - */ -void ADC_InsertedSequencerLength_Config(ADC_TypeDef *ADCx, uint8_t Length) -{ - uint32_t temp1 = 0; - uint32_t temp2 = 0; - /* Get ISQ value */ - temp1 = ADCx->ISQ; - /* Clear IL bits */ - temp1 &= ~ISQ_IL_SET; - /* Set IL bits */ - temp2 = Length - 1; - temp1 |= temp2 << 20; - /* Write to ISQ */ - ADCx->ISQ = temp1; -} - -/** - * @brief Set the offset of the inserted channels conversion value. - * @param ADCx: the ADC interface where x can be 1..3. - * @param ADC_InsertedChannel: one of the four inserted channels to set its offset. - * This parameter can be one of the following values: - * @arg ADC_INSERTEDCHANNEL_1: Inserted Channel1 - * @arg ADC_INSERTEDCHANNEL_2: Inserted Channel2 - * @arg ADC_INSERTEDCHANNEL_3: Inserted Channel3 - * @arg ADC_INSERTEDCHANNEL_4: Inserted Channel4 - * @param Offset: the offset value of the selected ADC inserted channel - * This parameter must be a 12bit value. - * @retval None - */ -void ADC_SetInsertedOffset(ADC_TypeDef *ADCx, uint8_t ADC_InsertedChannel, uint16_t Offset) -{ - __IO uint32_t temp = 0; - temp = (uint32_t)ADCx; - temp += ADC_InsertedChannel; - - /* Set the offset of the selected inserted channel */ - *(__IO uint32_t *) temp = (uint32_t)Offset; -} - -/** - * @brief Get the ADC inserted channel conversion result - * @param ADCx: the ADC interface where x can be 1..3. - * @param ADC_InsertedChannel: ADC inserted channel. - * This parameter can be one of the following values: - * @arg ADC_INSERTEDCHANNEL_1: Inserted Channel1 - * @arg ADC_INSERTEDCHANNEL_2: Inserted Channel2 - * @arg ADC_INSERTEDCHANNEL_3: Inserted Channel3 - * @arg ADC_INSERTEDCHANNEL_4: Inserted Channel4 - * @retval The conversion value. - */ -uint16_t ADC_GetInsertedConversionValue(ADC_TypeDef *ADCx, uint8_t ADC_InsertedChannel) -{ - __IO uint32_t temp = 0; - temp = (uint32_t)ADCx; - temp += ADC_InsertedChannel + IDTR_OFFSET; - - /* Return the result of the selected inserted channel conversion */ - return (uint16_t)(*(__IO uint32_t *) temp); -} - -/** - * @brief Enable or disable the analog watchdog. - * @param ADCx: the ADC interface where x can be 1..3. - * @param ADC_AnalogWatchdog: the ADC analog watchdog configuration. - * This parameter can be one of the following values: - * @arg ADC_ANALOGWATCHDOG_SINGLEREGENABLE: single regular channel - * @arg ADC_ANALOGWATCHDOG_SINGLEINSERTENABLE: single inserted channel - * @arg ADC_ANALOGWATCHDOG_SINGLEREGORINSERTENABLE: single regular or inserted channel - * @arg ADC_ANALOGWATCHDOG_ALLREGENABLE: all regular channel - * @arg ADC_ANALOGWATCHDOG_ALLINSERTENABLE: all inserted channel - * @arg ADC_ANALOGWATCHDOG_ALLREGALLINSERTENABLE: all regular and inserted channels - * @arg ADC_ANALOGWATCHDOG_NONE: No channel - * @retval None - */ -void ADC_AnalogWatchdog_Enable(ADC_TypeDef *ADCx, uint32_t ADC_AnalogWatchdog) -{ - uint32_t temp = 0; - /* Get CTLR1 value */ - temp = ADCx->CTLR1; - /* Clear AWDEN, AWDENJ and AWDSGL bits */ - temp &= CTLR1_AWDMODE_RESET; - /* Set the analog watchdog mode */ - temp |= ADC_AnalogWatchdog; - /* Write to CTLR1 */ - ADCx->CTLR1 = temp; -} - -/** - * @brief Configure the high and low thresholds of the analog watchdog. - * @param ADCx: the ADC interface where x can be 1..3. - * @param HighThreshold: the ADC analog watchdog High threshold value. - * This parameter must be a 12bit value. - * @param LowThreshold: the ADC analog watchdog Low threshold value. - * This parameter must be a 12bit value. - * @retval None - */ -void ADC_AnalogWatchdogThresholds_Config(ADC_TypeDef *ADCx, uint16_t HighThreshold, - uint16_t LowThreshold) -{ - /* Set the ADCx high threshold */ - ADCx->AWHT = HighThreshold; - /* Set the ADCx low threshold */ - ADCx->AWLT = LowThreshold; -} - -/** - * @brief Configure the analog watchdog on single channel mode. - * @param ADCx: the ADC interface where x can be 1..3. - * @param ADC_Channel: ADC channel. - * This parameter can be as follows: - * @arg ADC_CHANNEL_0: ADC Channel0 - * @arg ADC_CHANNEL_1: ADC Channel1 - * @arg ADC_CHANNEL_2: ADC Channel2 - * @arg ADC_CHANNEL_3: ADC Channel3 - * @arg ADC_CHANNEL_4: ADC Channel4 - * @arg ADC_CHANNEL_5: ADC Channel5 - * @arg ADC_CHANNEL_6: ADC Channel6 - * @arg ADC_CHANNEL_7: ADC Channel7 - * @arg ADC_CHANNEL_8: ADC Channel8 - * @arg ADC_CHANNEL_9: ADC Channel9 - * @arg ADC_CHANNEL_10: ADC Channel10 - * @arg ADC_CHANNEL_11: ADC Channel11 - * @arg ADC_CHANNEL_12: ADC Channel12 - * @arg ADC_CHANNEL_13: ADC Channel13 - * @arg ADC_CHANNEL_14: ADC Channel14 - * @arg ADC_CHANNEL_15: ADC Channel15 - * @arg ADC_CHANNEL_16: ADC Channel16 - * @arg ADC_CHANNEL_17: ADC Channel17 - * @retval None - */ -void ADC_AnalogWatchdogSingleChannel_Config(ADC_TypeDef *ADCx, uint8_t ADC_Channel) -{ - uint32_t temp = 0; - /* Get CTLR1 value */ - temp = ADCx->CTLR1; - /* Clear AWCS */ - temp &= CTLR1_AWCS_RESET; - /* Set the Analog watchdog channel */ - temp |= ADC_Channel; - /* Write to CTLR1 */ - ADCx->CTLR1 = temp; -} - -/** - * @brief Enable or disable the temperature sensor and Vrefint channel. - * @param NewValue: the state of the temperature sensor. - * This parameter can be: ENABLE or DISABLE. - * @retval None - */ -void ADC_TempSensorVrefint_Enable(TypeState NewValue) -{ - if (NewValue != DISABLE) { - /* Enable the temperature sensor and Vrefint channel*/ - ADC0->CTLR2 |= CTLR2_TSVREN_SET; - } else { - /* Disable the temperature sensor and Vrefint channel*/ - ADC0->CTLR2 &= ~CTLR2_TSVREN_SET; - } -} - -/** - * @brief Check the ADC flag. - * @param ADCx: the ADC interface where x can be 1..3. - * @param ADC_FLAG: the flag to check. - * This parameter can be as follows: - * @arg ADC_FLAG_AWE: The flag of the analog watchdog - * @arg ADC_FLAG_EOC: The flag of the end of conversion - * @arg ADC_FLAG_EOIC: The flag of the end of inserted group conversion - * @arg ADC_FLAG_STIC: The flag of the start of inserted group conversion - * @arg ADC_FLAG_STRC: The flag of the start of regular group conversion - * @retval ADC_FLAG state(SET or RESET). - */ -TypeState ADC_GetBitState(ADC_TypeDef *ADCx, uint8_t ADC_FLAG) -{ - /* Check the specified ADC flag state */ - if ((ADCx->STR & ADC_FLAG) != (uint8_t)RESET) { - /* ADC_FLAG is set */ - return SET; - } else { - /* ADC_FLAG is reset */ - return RESET; - } -} - -/** - * @brief Clear the ADCx's pending flags. - * @param ADCx: the ADC interface where x can be 1..3. - * @param ADC_FLAG: the flag to clear. - * This parameter can be any combination of the following values: - * @arg ADC_FLAG_AWE: The flag of the analog watchdog - * @arg ADC_FLAG_EOC: The flag of the end of conversion - * @arg ADC_FLAG_EOIC: The flag of the end of inserted group conversion - * @arg ADC_FLAG_STIC: The flag of the start of inserted group conversion - * @arg ADC_FLAG_STRC: The flag of the start of regular group conversion - * @retval None - */ -void ADC_ClearBitState(ADC_TypeDef *ADCx, uint8_t ADC_FLAG) -{ - /* Clear the selected ADC flags */ - ADCx->STR = ~(uint32_t)ADC_FLAG; -} - -/** - * @brief Check the specified ADC interrupt. - * @param ADCx: the ADC interface where x can be 1..3. - * @param ADC_INT: ADC interrupt source. - * This parameter can be one of the following values: - * @arg ADC_INT_EOC: The interrupt mask of the end of conversion - * @arg ADC_INT_AWE: The interrupt mask of the analog watchdog - * @arg ADC_INT_EOIC: The interrupt mask of the end of inserted conversion - * @retval The new value of ADC_INT (SET or RESET). - */ -TypeState ADC_GetIntState(ADC_TypeDef *ADCx, uint16_t ADC_INT) -{ - uint32_t temp_it = 0, temp_enable = 0; - /* Get the ADC interrupt mask index */ - temp_it = ADC_INT >> 8; - /* Get the ADC_INT enable bit state */ - temp_enable = (ADCx->CTLR1 & (uint8_t)ADC_INT) ; - /* Check the state of the specified ADC interrupt */ - if (((ADCx->STR & temp_it) != (uint32_t)RESET) && temp_enable) { - /* ADC_INT is set */ - return SET; - } else { - /* ADC_INT is reset */ - return RESET; - } -} - -/** - * @brief Clear the ADCx's interrupt pending bits. - * @param ADCx: the ADC interface where x can be 1..3. - * @param ADC_INT: the ADC interrupt pending bit. - * This parameter can be any combination of the following values: - * @arg ADC_INT_EOC: The interrupt mask of the end of conversion - * @arg ADC_INT_AWE: The interrupt mask of the analog watchdog - * @arg ADC_INT_EOIC: The interrupt mask of the end of inserted conversion - * @retval None - */ -void ADC_ClearIntBitState(ADC_TypeDef *ADCx, uint16_t ADC_INT) -{ - uint8_t temp_it = 0; - /* Get the ADC interrupt mask index */ - temp_it = (uint8_t)(ADC_INT >> 8); - /* Clear ADCx interrupt pending bits */ - ADCx->STR = ~(uint32_t)temp_it; -} - -/** - * @} - */ - -/** - * @} - */ - -/** - * @} - */ diff --git a/bsp/gd32103c-eval/Libraries/GD32F1xx_standard_peripheral/Source/gd32f10x_bkp.c b/bsp/gd32103c-eval/Libraries/GD32F1xx_standard_peripheral/Source/gd32f10x_bkp.c deleted file mode 100644 index 28f219825b..0000000000 --- a/bsp/gd32103c-eval/Libraries/GD32F1xx_standard_peripheral/Source/gd32f10x_bkp.c +++ /dev/null @@ -1,250 +0,0 @@ -/** - ****************************************************************************** - * @brief BKP functions of the firmware library. - ****************************************************************************** - */ - -/* Includes ------------------------------------------------------------------*/ -#include "gd32f10x_bkp.h" -#include "gd32f10x_rcc.h" - -/** @addtogroup GD32F10x_Firmware - * @{ - */ - -/** @defgroup BKP - * @brief BKP driver modules - * @{ - */ - -/** @defgroup BKP_Private_Defines - * @{ - */ -/* RTCOUTPUT bit is masked in BKP_RCCR register */ -#define RTCOUTPUT_MASK ((uint16_t)0xFC7F) - -/** - * @} - */ - - -/** @defgroup BKP_Private_Functions - * @{ - */ - -/** - * @brief Reset the BKP peripheral registers. - * @param None - * @retval None - */ -void BKP_DeInit(void) -{ - RCC_BackupReset_Enable(ENABLE); - RCC_BackupReset_Enable(DISABLE); -} - -/** - * @brief Write user data to the BKP_DRx register. - * @param BKP_DR: the Backup Data Register. - * This parameter can be BKP_DRx where x can be (1..42) - * @param Data: data to write - * @retval None - */ -void BKP_WriteBackupRegister(uint16_t BKP_DR, uint16_t Data) -{ - __IO uint32_t temp = 0; - - temp = (uint32_t)BKP_BASE; - temp += BKP_DR; - - /* Store the write data */ - *(__IO uint16_t *) temp = Data; -} - -/** - * @brief Read data from the BKP_DRx register. - * @param BKP_DR: The Backup Data Register. - * This parameter can be BKP_DRx where x can be (1..42) - * @retval The content of the BKP_DRx register. - */ -uint16_t BKP_ReadBackupRegister(uint16_t BKP_DR) -{ - __IO uint32_t temp = 0; - - temp = (uint32_t)BKP_BASE; - temp += BKP_DR; - - /* Return the BKP_DRx register value */ - return (*(__IO uint16_t *) temp); -} - -/** - * @brief Configure the RTC output on the Tamper pin. - * @param BKP_RTCOUTPUT: the RTC output. - * This parameter can be one of the following values: - * @arg BKP_RTCOUTPUT_NULL: no RTC output on the TAMPER pin. - * @arg BKP_RTCOUTPUT_CLKCAL: output the RTC clock with frequency - * divided by 64 on the TAMPER pin. - * @arg BKP_RTCOUTPUT_ALARM: output the RTC Alarm pulse signal on - * the TAMPER pin. - * @arg BKP_RTCOUTPUT_SECOND: output the RTC Second pulse signal on - * the TAMPER pin. - * @retval None - */ -void BKP_RTCOutputConfig(uint16_t BKP_RTCOUTPUT) -{ - uint16_t temp = 0; - - temp = BKP->RCCR; - - /* Clear RCCOE, ROE and ROS bits */ - temp &= RTCOUTPUT_MASK; - - /* Set RCCOE, ROE and ROS bits according to BKP_RTCOUTPUT value */ - temp |= BKP_RTCOUTPUT; - - /* Store the new value */ - BKP->RCCR = temp; -} - -/** - * @brief Set RTC Clock Calibration value. - * @param CalibrationValue: the RTC Clock Calibration value. - * This parameter must be a number between 0 and 0x7F. - * @retval None - */ -void BKP_SetRTCCalibrationValue(uint8_t CalibrationValue) -{ - uint16_t temp = 0; - - temp = BKP->RCCR; - - /* Clear RCCV[6:0] bits */ - temp &= ~BKP_RCCR_RCCV; - - /* Set CAL[6:0] bits according to CalibrationValue */ - temp |= CalibrationValue; - - /* Store the new value */ - BKP->RCCR = temp; -} - -/** - * @brief Configure the TAMPER pin active level. - * @param BKP_TPAL: the TAMPER pin active level. - * This parameter can be one of the following values: - * @arg BKP_TPAL_HIGH: TAMPER pin active on high level - * @arg BKP_TPAL_LOW: TAMPER pin active on low level - * @param NewValue: New value of the TAMPER pin state. - * This parameter can be: ENABLE or DISABLE. - * @retval None - */ -void BKP_TamperPinConfig(uint16_t BKP_TPAL, TypeState NewValue) -{ - uint16_t temp = 0; - - temp = BKP->TPCR; - - /* Clear TPE bit */ - temp &= ~((uint16_t)BKP_TPCR_TPE); - - /* Configure TPAL bit according to BKP_TPAL value */ - temp |= BKP_TPAL; - - /* Store the new value */ - BKP->TPCR = temp; - - /* Enable the TAMPER pin */ - if (NewValue != DISABLE) { - /* The TAMPER pin is dedicated for the Backup Reset function */ - BKP->TPCR |= BKP_TPCR_TPE; - } else { - /* The TAMPER pin is free for GPIO functions */ - BKP->TPCR &= ~((uint16_t)BKP_TPCR_TPE); - } -} - -/** - * @brief Enable or disable the Tamper Interrupt. - * @param NewValue: New value of the Tamper Interrupt. - * This parameter can be: ENABLE or DISABLE. - * @retval None - */ -void BKP_TamperINT_Enable(TypeState NewValue) -{ - if (NewValue != DISABLE) { - /* Enable the tamper interrupt */ - BKP->TIER |= BKP_TIER_TIE; - } else { - /* Disable the tamper interrupt */ - BKP->TIER &= ~BKP_TIER_TIE; - } -} - -/** - * @brief Get the bit flag of Tamper Event. - * @param None - * @retval The new value of Tamper Event flag (SET or RESET). - */ -TypeState BKP_GetBitState(void) -{ - /* Check and get the Tamper Event flag */ - if ((BKP->TIER & BKP_TIER_TEF) != (uint16_t)RESET) { - /* Tamper Event occured */ - return SET; - } else { - /* No Tamper Event occured */ - return RESET; - } -} - -/** - * @brief Clear the bit flag of Tamper Event. - * @param None - * @retval None - */ -void BKP_ClearBitState(void) -{ - /* Set the TER bit to clear Tamper Event flag */ - BKP->TIER |= BKP_TIER_TER; -} - -/** - * @brief Get the interrupt bit flag of Tamper Interrupt. - * @param None - * @retval The new value of the Tamper Interrupt flag (SET or RESET). - */ -TypeState BKP_GetIntBitState(void) -{ - /* Check and get the Tamper Interrupt flag */ - if ((BKP->TIER & BKP_TIER_TIF) != (uint16_t)RESET) { - /* Tamper Interrupt occured */ - return SET; - } else { - /* No Tamper Interrupt occured */ - return RESET; - } -} - -/** - * @brief Clear the interrupt bit flag of Tamper Interrupt. - * @param None - * @retval None - */ -void BKP_ClearIntBitState(void) -{ - /* Set the TIR bit to clear Tamper Interrupt flag */ - BKP->TIER |= BKP_TIER_TIR; -} - -/** - * @} - */ - -/** - * @} - */ - -/** - * @} - */ diff --git a/bsp/gd32103c-eval/Libraries/GD32F1xx_standard_peripheral/Source/gd32f10x_can.c b/bsp/gd32103c-eval/Libraries/GD32F1xx_standard_peripheral/Source/gd32f10x_can.c deleted file mode 100644 index 604dca5caa..0000000000 --- a/bsp/gd32103c-eval/Libraries/GD32F1xx_standard_peripheral/Source/gd32f10x_can.c +++ /dev/null @@ -1,1120 +0,0 @@ -/** - ****************************************************************************** - * @brief CAN functions of the firmware library. - ****************************************************************************** - */ - -/* Includes ------------------------------------------------------------------*/ -#include "gd32f10x_can.h" -#include "gd32f10x_rcc.h" - -/** @addtogroup GD32F10x_Firmware - * @{ - */ - -/** @defgroup CAN - * @brief CAN driver modules - * @{ - */ - -/** @defgroup CAN_Private_Defines - * @{ - */ - - -/* CAN Mailbox Transmit Request */ -#define CAN_TMIR_TE ((uint32_t)0x00000001) - -/* CAN Filter Master Register bits */ -#define FMR_FINIT ((uint32_t)0x00000001) - -/* Time out for IWS bit */ -#define IWS_TIMEOUT ((uint32_t)0x0000FFFF) -/* Time out for SWS bit */ -#define SWS_TIMEOUT ((uint32_t)0x0000FFFF) - -/* CAN TMIR_StdId masks */ -#define CAN_TMIR_StdId_Mask ((uint32_t)0x000007FF) - -/* CAN TMIR_ExtId masks */ -#define CAN_TMIR_ExtId_Mask ((uint32_t)0x1FFFFFFF) - -/* CAN TMIR_ExtId masks */ -#define CAN_FLAG_Mask ((uint32_t)0x000FFFFF) - -/* Flags in TSTR register */ -#define CAN_FLAGS_TSTR ((uint32_t)0x08000000) - -/* Flags in RFR1 register */ -#define CAN_FLAGS_RFR1 ((uint32_t)0x04000000) - -/* Flags in RFR0register */ -#define CAN_FLAGS_RFR0 ((uint32_t)0x02000000) - -/* Flags in STR register */ -#define CAN_FLAGS_STR ((uint32_t)0x01000000) - -/* Flags in ER register */ -#define CAN_FLAGS_ER ((uint32_t)0x00F00000) - -/* Mailboxes definition */ -#define CAN_TXMAILBOX_0 ((uint8_t)0x00) -#define CAN_TXMAILBOX_1 ((uint8_t)0x01) -#define CAN_TXMAILBOX_2 ((uint8_t)0x02) - -/* CAN Master Control Register bit */ -#define MCR_DBF ((uint32_t)0x00010000) - - -#define CAN_MODE_MASK ((uint32_t)0x00000003) -/** - * @} - */ - - -/** @defgroup CAN_Private_Functions - * @{ - */ - -/** - * @brief Deinitialize the CAN peripheral registers. - * @param CANx: where x:[1,2] to select the CAN peripheral. - * @retval None. - */ -void CAN_DeInit(CAN_TypeDef *CANx) -{ - if (CANx == CAN1) { - /* Force CAN1 reset state */ - RCC_APB1PeriphReset_Enable(RCC_APB1PERIPH_CAN1, ENABLE); - /* Release CAN1 from reset state */ - RCC_APB1PeriphReset_Enable(RCC_APB1PERIPH_CAN1, DISABLE); - } else { - /* Force CAN2 reset state */ - RCC_APB1PeriphReset_Enable(RCC_APB1PERIPH_CAN2, ENABLE); - /* Release CAN2 from reset state */ - RCC_APB1PeriphReset_Enable(RCC_APB1PERIPH_CAN2, DISABLE); - } -} - -/** - * @brief Initialize the CAN peripheral according to the CAN_InitParaStruct. - * @param CANx:where x:[1,2] - * @param CAN_InitParaStruct: contain the configuration information for the CAN peripheral. - * @retval It will be returned the status of CAN_INITSTATE_FAILED or CAN_INITSTATE_SUCCESS. - */ -uint8_t CAN_Init(CAN_TypeDef *CANx, CAN_InitPara *CAN_InitParaStruct) -{ - uint32_t wait_ack = 0x00000000; - - /* Out of sleep mode */ - CANx->CTLR &= (~(uint32_t)CAN_CTLR_SWM); - - /* Enable initial working */ - CANx->CTLR |= CAN_CTLR_IWM ; - - /* Wait the acknowledge */ - while (((CANx->STR & CAN_STR_IWS) != CAN_STR_IWS) && (wait_ack != IWS_TIMEOUT)) { - wait_ack++; - } - - /* Check whether initial working is success */ - if ((CANx->STR & CAN_STR_IWS) != CAN_STR_IWS) { - return CAN_INITSTATE_FAILED; - } else { - /* Set the time triggered communication mode */ - if (CAN_InitParaStruct->CAN_TTC == ENABLE) { - CANx->CTLR |= CAN_CTLR_TTC; - } else { - CANx->CTLR &= ~(uint32_t)CAN_CTLR_TTC; - } - - /* Set the automatic bus-off management */ - if (CAN_InitParaStruct->CAN_ABOR == ENABLE) { - CANx->CTLR |= CAN_CTLR_ABOR; - } else { - CANx->CTLR &= ~(uint32_t)CAN_CTLR_ABOR; - } - - /* Set the automatic wake-up mode */ - if (CAN_InitParaStruct->CAN_AWK == ENABLE) { - CANx->CTLR |= CAN_CTLR_AWK; - } else { - CANx->CTLR &= ~(uint32_t)CAN_CTLR_AWK; - } - - /* Set the automatic retransmission mode */ - if (CAN_InitParaStruct->CAN_ARD == ENABLE) { - CANx->CTLR |= CAN_CTLR_ARD; - } else { - CANx->CTLR &= ~(uint32_t)CAN_CTLR_ARD; - } - - /* Set receive FIFO overwrite mode */ - if (CAN_InitParaStruct->CAN_RFOD == ENABLE) { - CANx->CTLR |= CAN_CTLR_RFOD; - } else { - CANx->CTLR &= ~(uint32_t)CAN_CTLR_RFOD; - } - - /* Set the Transmit FIFO order */ - if (CAN_InitParaStruct->CAN_TFO == ENABLE) { - CANx->CTLR |= CAN_CTLR_TFO; - } else { - CANx->CTLR &= ~(uint32_t)CAN_CTLR_TFO; - } - - /* Set the bit timing register */ - CANx->BTR = (uint32_t)((uint32_t)CAN_InitParaStruct->CAN_Mode << 30) | \ - ((uint32_t)CAN_InitParaStruct->CAN_SJW << 24) | \ - ((uint32_t)CAN_InitParaStruct->CAN_BS1 << 16) | \ - ((uint32_t)CAN_InitParaStruct->CAN_BS2 << 20) | \ - ((uint32_t)CAN_InitParaStruct->CAN_Prescaler - 1); - - /* leave initialisation */ - CANx->CTLR &= ~(uint32_t)CAN_CTLR_IWM; - - /* Wait the acknowledge */ - wait_ack = 0; - - while (((CANx->STR & CAN_STR_IWS) == CAN_STR_IWS) && (wait_ack != IWS_TIMEOUT)) { - wait_ack++; - } - - /* Check whether qiut initial working mode */ - if ((CANx->STR & CAN_STR_IWS) == CAN_STR_IWS) { - return CAN_INITSTATE_FAILED; - } else { - return CAN_INITSTATE_SUCCESS; - } - } - -} - -/** - * @brief Initialize the CAN peripheral according to the CAN_FilterInitStruct. - * @param CAN_FilterInitParaStruct:contain the information for the CAN peripheral. - * @retval None. - */ -void CAN_FilterInit(CAN_FilterInitPara *CAN_FilterInitParaStruct) -{ - uint32_t filter_number = 0; - - filter_number = ((uint32_t)1) << CAN_FilterInitParaStruct->CAN_FilterNumber; - - /* Set filter lock disable */ - CAN1->FCTLR |= CAN_FCTLR_FLD; - - /* Disable Filter */ - CAN1->FWR &= ~(uint32_t)filter_number; - - /* Filter Scale */ - if (CAN_FilterInitParaStruct->CAN_FilterScale == CAN_FILTERSCALE_16BIT) { - /* Set the filter 16-bit scale*/ - CAN1->FSR &= ~(uint32_t)filter_number; - - /* First 16-bit list and First 16-bit mask */ - /* Or First 16-bit list and Second 16-bit list */ - CAN1->FilterRegister[CAN_FilterInitParaStruct->CAN_FilterNumber].FD0R = - ((0x0000FFFF & (uint32_t)CAN_FilterInitParaStruct->CAN_FilterMaskListLow) << 16) | - (0x0000FFFF & (uint32_t)CAN_FilterInitParaStruct->CAN_FilterListLow); - - /* Second 16-bit identifier and Second 16-bit mask */ - /* Or Third 16-bit identifier and Fourth 16-bit identifier */ - CAN1->FilterRegister[CAN_FilterInitParaStruct->CAN_FilterNumber].FD1R = - ((0x0000FFFF & (uint32_t)CAN_FilterInitParaStruct->CAN_FilterMaskListHigh) << 16) | - (0x0000FFFF & (uint32_t)CAN_FilterInitParaStruct->CAN_FilterListHigh); - } - - if (CAN_FilterInitParaStruct->CAN_FilterScale == CAN_FILTERSCALE_32BIT) { - /* 32-bit scale for the filter */ - CAN1->FSR |= filter_number; - /* 32-bit identifier or First 32-bit identifier */ - CAN1->FilterRegister[CAN_FilterInitParaStruct->CAN_FilterNumber].FD0R = - ((0x0000FFFF & (uint32_t)CAN_FilterInitParaStruct->CAN_FilterListHigh) << 16) | - (0x0000FFFF & (uint32_t)CAN_FilterInitParaStruct->CAN_FilterListLow); - /* 32-bit mask or Second 32-bit identifier */ - CAN1->FilterRegister[CAN_FilterInitParaStruct->CAN_FilterNumber].FD1R = - ((0x0000FFFF & (uint32_t)CAN_FilterInitParaStruct->CAN_FilterMaskListHigh) << 16) | - (0x0000FFFF & (uint32_t)CAN_FilterInitParaStruct->CAN_FilterMaskListLow); - } - - /* Filter Mode */ - if (CAN_FilterInitParaStruct->CAN_FilterMode == CAN_FILTERMODE_MASK) { - /*Filter with Mask mode*/ - CAN1->FMR &= ~(uint32_t)filter_number; - } else { /* CAN_FilterInitStruct->CAN_FilterMode == CAN_FILTERMODE_LIST */ - /*Filter with List mode*/ - CAN1->FMR |= (uint32_t)filter_number; - } - - /* Filter associated with FIFO */ - if (CAN_FilterInitParaStruct->CAN_FilterFIFOAssociation == CAN_FILTER_FIFO0) { - /* Filter associated with FIFO 0 */ - CAN1->FAFR &= ~(uint32_t)filter_number; - } - - if (CAN_FilterInitParaStruct->CAN_FilterFIFOAssociation == CAN_FILTER_FIFO1) { - /* Filter associated with FIFO 1 */ - CAN1->FAFR |= (uint32_t)filter_number; - } - - /* Filter working */ - if (CAN_FilterInitParaStruct->CAN_FilterWork == ENABLE) { - CAN1->FWR |= filter_number; - } - - /* Exit the initialisation mode for the filter */ - CAN1->FCTLR &= ~CAN_FCTLR_FLD; -} - -/** - * @brief Configure each CAN_InitParaStruct member with default value. - * @param CAN_InitParaStruct: pointer to a CAN_InitPara structure to initialize. - * @retval None. - */ -void CAN_StructInit(CAN_InitPara *CAN_InitParaStruct) -{ - /* Set the time triggered communication mode */ - CAN_InitParaStruct->CAN_TTC = DISABLE; - - /* Set the automatic bus-off recovery */ - CAN_InitParaStruct->CAN_ABOR = DISABLE; - - /* Set the automatic wake up mode */ - CAN_InitParaStruct->CAN_AWK = DISABLE; - - /* Set the automatic retransmission disable */ - CAN_InitParaStruct->CAN_ARD = DISABLE; - - /* Set the receive FIFO overwrite mode */ - CAN_InitParaStruct->CAN_RFOD = DISABLE; - - /* Set the transmit FIFO order */ - CAN_InitParaStruct->CAN_TFO = DISABLE; - - /* Set the CAN_Mode member */ - CAN_InitParaStruct->CAN_Mode = CAN_MODE_NORMAL; - - /* Set the CAN_SJW member */ - CAN_InitParaStruct->CAN_SJW = CAN_SJW_1TQ; - - /* Set the CAN_BS1 member */ - CAN_InitParaStruct->CAN_BS1 = CAN_BS1_4TQ; - - /* Set the CAN_BS2 member */ - CAN_InitParaStruct->CAN_BS2 = CAN_BS2_3TQ; - - /* Set the CAN_Prescaler member */ - CAN_InitParaStruct->CAN_Prescaler = 1; -} - -/** - * @brief Set header bank of CAN2 filter. - * @param CAN2_HeaderBankNumber: Select header bank of CAN2 filter.It can be 1 to 27. - * @retval None. - */ -void CAN_HeaderBank(uint8_t CAN_HeaderBankNumber) -{ - /* Set filter lock disable */ - CAN1->FCTLR |= CAN_FCTLR_FLD; - - /* Select filter start number for slave CAN */ - CAN1->FCTLR &= (uint32_t)0xFFFFC0F1 ; - CAN1->FCTLR |= (uint32_t)(CAN_HeaderBankNumber) << 8; - - /* Filter out the initialization mode */ - CAN1->FCTLR |= ~CAN_FCTLR_FLD; -} - -/** - * @brief Enable or disable the Debug Freeze for CAN. - * @param CANx: where x :[1,2] for selecting the CAN peripheral. - * @param NewValue: new state of the CAN peripheral. - * This parameter can be: ENABLE or DISABLE. - * @retval None. - */ -void CAN_DebugFreeze(CAN_TypeDef *CANx, TypeState NewValue) -{ - if (NewValue != DISABLE) { - CANx->CTLR |= CAN_CTLR_DFZ; - } else { - CANx->CTLR &= ~CAN_CTLR_DFZ; - } -} - - -/** - * @brief Enable or disabe the CAN Time Triggered communication mode. - * @param CANx:where x :[1,2] for selecting the CAN peripheral. - * @param NewValue : Mode new state , This parameter can be: ENABLE or DISABLE. - * @retval None - */ -void CAN_TimeTrigComMode_Enable(CAN_TypeDef *CANx, TypeState NewValue) -{ - if (NewValue != DISABLE) { - /* Enable the TTC mode */ - CANx->CTLR |= CAN_CTLR_TTC; - - /* Set TSEbits */ - CANx->TxMailBox[0].TMPR |= ((uint32_t)CAN_TMPR0_TSE); - CANx->TxMailBox[1].TMPR |= ((uint32_t)CAN_TMPR1_TSE); - CANx->TxMailBox[2].TMPR |= ((uint32_t)CAN_TMPR2_TSE); - } else { - /* Disable the TTC mode */ - CANx->CTLR &= (uint32_t)(~(uint32_t)CAN_CTLR_TTC); - - /* Reset TSE bits */ - CANx->TxMailBox[0].TMPR &= ((uint32_t)~CAN_TMPR0_TSE); - CANx->TxMailBox[1].TMPR &= ((uint32_t)~CAN_TMPR1_TSE); - CANx->TxMailBox[2].TMPR &= ((uint32_t)~CAN_TMPR2_TSE); - } -} -/** - * @brief Initiate to transmit a message. - * @param CANx: where x:[1,2]to to select the CAN peripheral. - * @param TxMessage: contain CAN Id, CAN DLC and CAN data for the structure. - * @retval The number of the mailbox that is used for transmission - * or CAN_TxState_NoMailBox if there is no empty mailbox. - */ -uint8_t CAN_Transmit(CAN_TypeDef *CANx, CanTxMessage *TxMessage) -{ - uint8_t transmit_mailbox_number = 0; - - /* Select one empty transmit mailbox */ - if ((CANx->TSTR & CAN_TSTR_TME0) == CAN_TSTR_TME0) { - transmit_mailbox_number = 0; - } else if ((CANx->TSTR & CAN_TSTR_TME1) == CAN_TSTR_TME1) { - transmit_mailbox_number = 1; - } else if ((CANx->TSTR & CAN_TSTR_TME2) == CAN_TSTR_TME2) { - transmit_mailbox_number = 2; - } else { - transmit_mailbox_number = CAN_TXSTATE_NOMAILBOX; - } - - if (transmit_mailbox_number != CAN_TXSTATE_NOMAILBOX) { - /* Set up the Id */ - CANx->TxMailBox[transmit_mailbox_number].TMIR &= CAN_TMIR_TE; - if (TxMessage->FF == CAN_FF_STANDARD) { - CANx->TxMailBox[transmit_mailbox_number].TMIR |= ((TxMessage->StdId << 21) | \ - TxMessage->FT); - } else { - CANx->TxMailBox[transmit_mailbox_number].TMIR |= ((TxMessage->ExtId << 3) | \ - TxMessage->FF | \ - TxMessage->FT); - } - - /* Set up the DLC */ - TxMessage->DLC &= ((uint8_t)CAN_TMPR0_DLC); - CANx->TxMailBox[transmit_mailbox_number].TMPR &= ((uint32_t)~CAN_TMPR0_DLC); - CANx->TxMailBox[transmit_mailbox_number].TMPR |= TxMessage->DLC; - - /* Set up the data field */ - CANx->TxMailBox[transmit_mailbox_number].TMD0R = (((uint32_t)TxMessage->Data[3] << 24) | - ((uint32_t)TxMessage->Data[2] << 16) | - ((uint32_t)TxMessage->Data[1] << 8) | - ((uint32_t)TxMessage->Data[0])); - CANx->TxMailBox[transmit_mailbox_number].TMD1R = (((uint32_t)TxMessage->Data[7] << 24) | - ((uint32_t)TxMessage->Data[6] << 16) | - ((uint32_t)TxMessage->Data[5] << 8) | - ((uint32_t)TxMessage->Data[4])); - /* Request transmission */ - CANx->TxMailBox[transmit_mailbox_number].TMIR |= CAN_TMIR0_TE; - } - return transmit_mailbox_number; -} - -/** - * @brief Check the state of message transmission. - * @param CANx: where x:[1,2] to to select the CAN peripheral. - * @param TransmitMailbox: the number of the used transmission mailbox. - * @retval Return CAN_TXSTATE_OK or CAN_TXSTATE_FAILED. - */ -uint8_t CAN_TransmitState(CAN_TypeDef *CANx, uint8_t TransmitMailbox) -{ - uint32_t state = 0; - - switch (TransmitMailbox) { - case (CAN_TXMAILBOX_0): - state = CANx->TSTR & (CAN_TSTR_MTF0 | CAN_TSTR_MTFNE0 | CAN_TSTR_TME0); - break; - case (CAN_TXMAILBOX_1): - state = CANx->TSTR & (CAN_TSTR_MTF1 | CAN_TSTR_MTFNE1 | CAN_TSTR_TME1); - break; - case (CAN_TXMAILBOX_2): - state = CANx->TSTR & (CAN_TSTR_MTF2 | CAN_TSTR_MTFNE2 | CAN_TSTR_TME2); - break; - default: - state = CAN_TXSTATE_FAILED; - break; - } - switch (state) { - /* transmit pending */ - case (0x0): - state = CAN_TXSTATE_PENDING; - break; - /* transmit failed */ - case (CAN_TSTR_MTF0 | CAN_TSTR_TME0): - state = CAN_TXSTATE_FAILED; - break; - case (CAN_TSTR_MTF1 | CAN_TSTR_TME1): - state = CAN_TXSTATE_FAILED; - break; - case (CAN_TSTR_MTF2 | CAN_TSTR_TME2): - state = CAN_TXSTATE_FAILED; - break; - /* transmit succeeded */ - case (CAN_TSTR_MTF0 | CAN_TSTR_MTFNE0 | CAN_TSTR_TME0): - state = CAN_TXSTATE_OK; - break; - case (CAN_TSTR_MTF1 | CAN_TSTR_MTFNE1 | CAN_TSTR_TME1): - state = CAN_TXSTATE_OK; - break; - case (CAN_TSTR_MTF2 | CAN_TSTR_MTFNE2 | CAN_TSTR_TME2): - state = CAN_TXSTATE_OK; - break; - default: - state = CAN_TXSTATE_FAILED; - break; - } - return (uint8_t) state; -} - -/** - * @brief Stop a transmit mission. - * @param CANx: where x:[1,2] to to select the CAN peripheral. - * @param Mailbox: Mailbox number. - * @retval None. - */ -void CAN_StopTransmit(CAN_TypeDef *CANx, uint8_t Mailbox) -{ - /* Stop transmission */ - switch (Mailbox) { - case (CAN_TXMAILBOX_0): - CANx->TSTR |= CAN_TSTR_MST0; - break; - case (CAN_TXMAILBOX_1): - CANx->TSTR |= CAN_TSTR_MST1; - break; - case (CAN_TXMAILBOX_2): - CANx->TSTR |= CAN_TSTR_MST2; - break; - default: - break; - } -} - - -/** - * @brief Receive a message. - * @param CANx: where x:[1,2] to to select the CAN peripheral. - * @param FIFONumber: Receive FIFO number, CAN_FIFO0 or CAN_FIFO1. - * @param RxMessage: a structure receive message which contains - * CAN Id, CAN DLC, CAN datas and FI number. - * @retval None. - */ -void CAN_Receive(CAN_TypeDef *CANx, uint8_t FIFONumber, CanRxMessage *RxMessage) -{ - /* Get the frame identifier */ - RxMessage->FF = (uint8_t)0x04 & CANx->FIFOMailBox[FIFONumber].RFMIR; - if (RxMessage->FF == CAN_FF_STANDARD) { - RxMessage->StdId = CAN_TMIR_StdId_Mask & (CANx->FIFOMailBox[FIFONumber].RFMIR >> 21); - } else { - RxMessage->ExtId = CAN_TMIR_ExtId_Mask & (CANx->FIFOMailBox[FIFONumber].RFMIR >> 3); - } - - RxMessage->FT = (uint8_t)0x02 & CANx->FIFOMailBox[FIFONumber].RFMIR; - /* Get the data length code */ - RxMessage->DLC = (uint8_t)0x0F & CANx->FIFOMailBox[FIFONumber].RFMPR; - /* Get the filtering index */ - RxMessage->FI = (uint8_t)0xFF & (CANx->FIFOMailBox[FIFONumber].RFMPR >> 8); - /* Get FIFO mailbox data */ - RxMessage->Data[0] = (uint8_t)0xFF & CANx->FIFOMailBox[FIFONumber].RFMD0R; - RxMessage->Data[1] = (uint8_t)0xFF & (CANx->FIFOMailBox[FIFONumber].RFMD0R >> 8); - RxMessage->Data[2] = (uint8_t)0xFF & (CANx->FIFOMailBox[FIFONumber].RFMD0R >> 16); - RxMessage->Data[3] = (uint8_t)0xFF & (CANx->FIFOMailBox[FIFONumber].RFMD0R >> 24); - RxMessage->Data[4] = (uint8_t)0xFF & CANx->FIFOMailBox[FIFONumber].RFMD1R; - RxMessage->Data[5] = (uint8_t)0xFF & (CANx->FIFOMailBox[FIFONumber].RFMD1R >> 8); - RxMessage->Data[6] = (uint8_t)0xFF & (CANx->FIFOMailBox[FIFONumber].RFMD1R >> 16); - RxMessage->Data[7] = (uint8_t)0xFF & (CANx->FIFOMailBox[FIFONumber].RFMD1R >> 24); - /* Release the FIFO */ - if (FIFONumber == CAN_FIFO0) { - CANx->RFR0 |= CAN_RFR0_RFD0; - } - - /* FIFONumber == CAN_FIFO1 */ - else { - CANx->RFR1 |= CAN_RFR1_RFD1; - } -} - -/** - * @brief Dequeue the FIFO. - * @param CANx: where x:[1,2] to to select the CAN peripheral. - * @param FIFONumber: FIFO to dequeue, it can be CAN_FIFO0 or CAN_FIFO1. - * @retval None. - */ -void CAN_FIFODequeue(CAN_TypeDef *CANx, uint8_t FIFONumber) -{ - - if (FIFONumber == CAN_FIFO0) { - /* Release FIFO 0 */ - CANx->RFR0 |= CAN_RFR0_RFD0; - } else { /* FIFONumber == CAN_FIFO1 */ - /* Release FIFO1 */ - CANx->RFR1 |= CAN_RFR1_RFD1; - } -} - -/** - * @brief Return the length of receiving messages. - * @param CANx: where x:[1,2] to to select the CAN peripheral. - * @param FIFONumber: Receive FIFO number, CAN_FIFO0 or CAN_FIFO1. - * @retval message_length : which is the Length of pending message. - */ -uint8_t CAN_MessageLength(CAN_TypeDef *CANx, uint8_t FIFONumber) -{ - uint8_t message_length = 0; - if (FIFONumber == CAN_FIFO0) { - message_length = (uint8_t)(CANx->RFR0 & (uint32_t)0x03); - } else if (FIFONumber == CAN_FIFO1) { - message_length = (uint8_t)(CANx->RFR1 & (uint32_t)0x03); - } else { - message_length = 0; - } - return message_length; -} - - -/** - * @brief Select the CAN Working mode. - * @param CAN_WorkingMode : CAN Working Mode.It can be the following one. - * @arg CAN_WORKINGMODE_INITIAL - * @arg CAN_WORKINGMODE_NORMAL - * @arg CAN_WORKINGMODE_SLEEP - * @retval state of the requested mode which can be - * @arg CAN_MODESTATE_FAILED - * @arg CAN_MODESTATE_SUCCESS - */ -uint8_t CAN_WorkingMode(CAN_TypeDef *CANx, uint8_t CAN_WorkingMode) -{ - uint8_t state = CAN_MODESTATE_FAILED; - - /* Timeout for IWS or also for SWS bits*/ - uint32_t timeout = IWS_TIMEOUT; - - if (CAN_WorkingMode == CAN_WORKINGMODE_INITIAL) { - /* Set initialisation */ - CANx->CTLR = (uint32_t)((CANx->CTLR & (uint32_t)(~(uint32_t)CAN_CTLR_SWM)) | CAN_CTLR_IWM); - - /* Wait the acknowledge */ - while (((CANx->STR & CAN_MODE_MASK) != CAN_STR_IWS) && (timeout != 0)) { - timeout--; - } - if ((CANx->STR & CAN_MODE_MASK) != CAN_STR_IWS) { - state = CAN_MODESTATE_FAILED; - } else { - state = CAN_MODESTATE_SUCCESS; - } - } else if (CAN_WorkingMode == CAN_WORKINGMODE_NORMAL) { - /* Enter Normal mode */ - CANx->CTLR &= (uint32_t)(~(CAN_CTLR_SWM | CAN_CTLR_IWM)); - - /* Wait the acknowledge */ - while (((CANx->STR & CAN_MODE_MASK) != 0) && (timeout != 0)) { - timeout--; - } - if ((CANx->STR & CAN_MODE_MASK) != 0) { - state = CAN_MODESTATE_FAILED; - } else { - state = CAN_MODESTATE_SUCCESS; - } - } else if (CAN_WorkingMode == CAN_WORKINGMODE_SLEEP) { - /* Set Sleep mode */ - CANx->CTLR = (uint32_t)((CANx->CTLR & (uint32_t)(~(uint32_t)CAN_CTLR_IWM)) | CAN_CTLR_SWM); - - /* Wait the acknowledge */ - while (((CANx->STR & CAN_MODE_MASK) != CAN_STR_SWS) && (timeout != 0)) { - timeout--; - } - if ((CANx->STR & CAN_MODE_MASK) != CAN_STR_SWS) { - state = CAN_MODESTATE_FAILED; - } else { - state = CAN_MODESTATE_SUCCESS; - } - } else { - state = CAN_MODESTATE_FAILED; - } - - return (uint8_t) state; -} - -/** - * @brief Enter the Sleep mode. - * @param CANx: where x:[1,2] to to select the CAN peripheral. - * @retval state: CAN_SLEEP_OK or CAN_SLEEP_FAILED. - */ -uint8_t CAN_EnterSleep(CAN_TypeDef *CANx) -{ - /* Set Sleep mode */ - CANx->CTLR = (((CANx->CTLR) & (uint32_t)(~(uint32_t)CAN_CTLR_IWM)) | CAN_CTLR_SWM); - - if ((CANx->STR & (CAN_STR_SWS | CAN_STR_IWS)) == CAN_STR_SWS) { - /* Sleep mode entered success*/ - return (uint8_t)CAN_SLEEP_OK; - } else { - /* Sleep mode entered failure */ - return (uint8_t)CAN_SLEEP_FAILED; - } -} - -/** - * @brief Wake up CAN. - * @param CANx: where x:[1,2] to to select the CAN peripheral. - * @retval status: CAN_WAKEUP_OK or CAN_WAKEUP_FAILED. - */ -uint8_t CAN_WakeUp(CAN_TypeDef *CANx) -{ - uint32_t wait_sws = SWS_TIMEOUT; - - /*set wake up */ - CANx->CTLR &= ~(uint32_t)CAN_CTLR_SWM; - - /* Sleep mode state */ - while (((CANx->CTLR & CAN_CTLR_SWM) == CAN_CTLR_SWM) && (wait_sws != 0x00)) { - wait_sws--; - } - if ((CANx->CTLR & CAN_CTLR_SWM) != CAN_CTLR_SWM) { - /*Sleep mode exited */ - return (uint8_t)CAN_WAKEUP_OK; - } else { - /*Sleep mode exited failure */ - return (uint8_t)CAN_WAKEUP_FAILED; - } -} - - -/** - * @brief Return the CANx's last error type (LEC). - * @param CANx: where x:[1,2] to to select the CAN peripheral. - * @retval CAN_ErrorType: specify the Error type: - * @arg CAN_ERRORTYPE_NOERR - * @arg CAN_ERRORTYPE_STUFFERR - * @arg CAN_ERRORTYPE_FORMERR - * @arg CAN_ERRORTYPE_ACKERR - * @arg CAN_ERRORTYPE_BITRECESSIVEERR - * @arg CAN_ERRORTYPE_BITDOMINANTERR - * @arg CAN_ERRORTYPE_CRCERR - * @arg CAN_ERRORTYPE_SOFTWARESETERR - */ - -uint8_t CAN_GetErrorType(CAN_TypeDef *CANx) -{ - uint8_t error_type = 0; - - /* Get the error type*/ - error_type = (((uint8_t)CANx->ER) & (uint8_t)CAN_ER_ET); - - /* Return the error type*/ - return error_type; -} - -/** - * @brief Get the Counter of CANx Receive Error(REC). - * @note According to the error condition as defined by the CAN standard, - * the counter of CANx Receive Error is increased by 1 or by 8. - * When CAN received success everytime, the counter is decreased by 1 - * or reset to 120 if its value was over than 128. - * When the counter value is over 127, the CAN controller enters the - * error passive state. - * @param CANx: where x:[1,2] to to select the CAN peripheral. - * @retval CAN Receive Error Counter. - */ -uint8_t CAN_GetReceiveErrorCounter(CAN_TypeDef *CANx) -{ - uint8_t receive_counter = 0; - - /* Get the counter of CANx Receive Error*/ - receive_counter = (uint8_t)((CANx->ER & CAN_ER_REC) >> 24); - - /* Return the Receive Error Counter*/ - return receive_counter; -} - - -/** - * @brief Get the Counter of CANx Transmit Error (TEC). - * @param CANx: where x:[1,2] to to select the CAN peripheral. - * @retval CAN Transmit Error Counter. - */ -uint8_t CAN_GetTransmitErrorCounter(CAN_TypeDef *CANx) -{ - uint8_t transmit_counter = 0; - - /* Get the Counter of CANx Transmit Error(TEC) */ - transmit_counter = (uint8_t)((CANx->ER & CAN_ER_TEC) >> 16); - - /* Return the Transmit Error Counter*/ - return transmit_counter; -} - - -/** - * @brief Enable or disable the specified CANx interrupts. - * @param CANx: where x:[1,2] to to select the CAN peripheral. - * @param CAN_INT: specify the CAN interrupt sources to be enabled or disabled. - * This parameter can be: - * @arg CAN_INT_TME - * @arg CAN_INT_RFNE0 - * @arg CAN_INT_RFF0 - * @arg CAN_INT_RFO0 - * @arg CAN_INT_RFNE1 - * @arg CAN_INT_RFF1 - * @arg CAN_INT_RFO1 - * @arg CAN_INT_WE - * @arg CAN_INT_PE - * @arg CAN_INT_BOE - * @arg CAN_INT_ET - * @arg CAN_INT_ERR - * @arg CAN_INT_WU - * @arg CAN_INT_SLP - * @param NewValue: new state of the CAN interrupts. - * This parameter can be: ENABLE or DISABLE. - * @retval None. - */ -void CAN_INTConfig(CAN_TypeDef *CANx, uint32_t CAN_INT, TypeState NewValue) -{ - if (NewValue != DISABLE) { - /* Enable interrupt */ - CANx->IER |= CAN_INT; - } else { - /* Disable interrupt */ - CANx->IER &= ~CAN_INT; - } -} -/** - * @brief Check whether the specified CAN flag is set or not. - * @param CANx: where x:[1,2] to to select the CAN peripheral. - * @param CAN_FLAG: specify the flag to check. - * This parameter can be one of the following flags: - * @arg CAN_FLAG_WE: Warning error Flag - * @arg CAN_FLAG_PE: Passive error Flag - * @arg CAN_FLAG_BOE: Bus-off error Flag - * @arg CAN_FLAG_MTF0: Mailbox 0 transmit finished Flag - * @arg CAN_FLAG_MTF1: Mailbox 1 transmit finished Flag - * @arg CAN_FLAG_MTF2: Mailbox 2 transmit finished Flag - * @arg CAN_FLAG_RFL0: the length of the receive FIFO0 Flag - * @arg CAN_FLAG_RFF0: Receive FIFO 0 full Flag - * @arg CAN_FLAG_RFO0: Receive FIFO 0 overfull Flag - * @arg CAN_FLAG_RFL1: the length of the receive FIFO1 Flag - * @arg CAN_FLAG_RFF1: Receive FIFO 1 full Flag - * @arg CAN_FLAG_RFO1: Receive FIFO 0 overfull Flag - * @arg CAN_FLAG_WU: Wake up Flag - * @arg CAN_FLAG_SLP: Sleep working state Flag - * @arg CAN_FLAG_ET: Error type Flag - * @retval The new state of CAN_FLAG (SET or RESET). - */ -TypeState CAN_GetBitState(CAN_TypeDef *CANx, uint32_t CAN_FLAG) -{ - if ((CAN_FLAG & CAN_FLAGS_ER) != (uint32_t)RESET) { - /* Check the state of the specified CAN flag */ - if ((CANx->ER & (CAN_FLAG & CAN_FLAG_Mask)) != (uint32_t)RESET) { - /* CAN_FLAG is set */ - return SET; - } else { - /* CAN_FLAG is reset */ - return RESET; - } - } else if ((CAN_FLAG & CAN_FLAGS_STR) != (uint32_t)RESET) { - /* Check the state of the specified CAN flag */ - if ((CANx->STR & (CAN_FLAG & CAN_FLAG_Mask)) != (uint32_t)RESET) { - /* CAN_FLAG is set */ - return SET; - } else { - /* CAN_FLAG is reset */ - return RESET; - } - } else if ((CAN_FLAG & CAN_FLAGS_TSTR) != (uint32_t)RESET) { - /* Check the state of the specified CAN flag */ - if ((CANx->TSTR & (CAN_FLAG & CAN_FLAG_Mask)) != (uint32_t)RESET) { - /* CAN_FLAG is set */ - return SET; - } else { - /* CAN_FLAG is reset */ - return RESET; - } - } else if ((CAN_FLAG & CAN_FLAGS_RFR0) != (uint32_t)RESET) { - /* Check the state of the specified CAN flag */ - if ((CANx->RFR0 & (CAN_FLAG & CAN_FLAG_Mask)) != (uint32_t)RESET) { - /* CAN_FLAG is set */ - return SET; - } else { - /* CAN_FLAG is reset */ - return RESET; - } - } - /* If(CAN_FLAG & CAN_FLAGS_RFR1 != (uint32_t)RESET) */ - else { - /* Check the state of the specified CAN flag */ - if ((uint32_t)(CANx->RFR1 & (CAN_FLAG & CAN_FLAG_Mask)) != (uint32_t)RESET) { - /* CAN_FLAG is set */ - return SET; - } else { - /* CAN_FLAG is reset */ - return RESET; - } - } -} - -/** - * @brief Clear the CAN's flags. - * @param CANx: where x:[1,2] to to select the CAN peripheral. - * @param CAN_FLAG: specify the flag to clear. - * This parameter can be one of the following flags: - * @arg CAN_FLAG_MTF0: Mailbox 0 transmit finished Flag - * @arg CAN_FLAG_MTF1: Mailbox 1 transmit finished Flag - * @arg CAN_FLAG_MTF2: Mailbox 2 transmit finished Flag - * @arg CAN_FLAG_RFF0: Receive FIFO 0 full Flag - * @arg CAN_FLAG_RFO0: Receive FIFO 0 overfull Flag - * @arg CAN_FLAG_RFF1: Receive FIFO 1 full Flag - * @arg CAN_FLAG_RFO1: Receive FIFO 0 overfull Flag - * @arg CAN_FLAG_WU: Wake up Flag - * @arg CAN_FLAG_SLP: Sleep working state Flag - * @arg CAN_FLAG_ET: Error type Flag - * @retval None. - */ -void CAN_ClearBitState(CAN_TypeDef *CANx, uint32_t CAN_FLAG) -{ - uint32_t temp = 0; - - /* ER register */ - if (CAN_FLAG == CAN_FLAG_ET) { - /* Clear the selected CAN flags */ - CANx->ER = (uint32_t)RESET; - } - /* STR or TSTR or RFR0 or RFR1 */ - else { - temp = CAN_FLAG & CAN_FLAG_Mask; - - if ((CAN_FLAG & CAN_FLAGS_RFR0) != (uint32_t)RESET) { - /* Receive Flags */ - CANx->RFR0 = (uint32_t)(temp); - } else if ((CAN_FLAG & CAN_FLAGS_RFR1) != (uint32_t)RESET) { - /* Receive Flags */ - CANx->RFR1 = (uint32_t)(temp); - } else if ((CAN_FLAG & CAN_FLAGS_TSTR) != (uint32_t)RESET) { - /* Transmit Flags */ - CANx->TSTR = (uint32_t)(temp); - } - /* If((CAN_FLAG & CAN_FLAGS_STR)!=(uint32_t)RESET) */ - else { - CANx->STR = (uint32_t)(temp); - } - } -} - -/** - * @brief Check whether the specified CANx interrupt has occurred or not. - * @param CANx: where x:[1,2] to to select the CAN peripheral. - * @param CAN_INT: specify the CAN interrupt source to check. - * This parameter can be: - * @arg CAN_INT_TME - * @arg CAN_INT_RFNE0 - * @arg CAN_INT_RFF0 - * @arg CAN_INT_RFO0 - * @arg CAN_INT_RFNE1 - * @arg CAN_INT_RFF1 - * @arg CAN_INT_RFO1 - * @arg CAN_INT_WE - * @arg CAN_INT_PE - * @arg CAN_INT_BOE - * @arg CAN_INT_ET - * @arg CAN_INT_ERR - * @arg CAN_INT_WU - * @arg CAN_INT_SLP - * @retval The current state of CAN_INT (SET or RESET). - */ -TypeState CAN_GetIntBitState(CAN_TypeDef *CANx, uint32_t CAN_INT) -{ - TypeState intstate = RESET; - - /* Get the enable interrupt bit */ - if ((CANx->IER & CAN_INT) != RESET) { - switch (CAN_INT) { - case CAN_INT_TME: - /* Check CAN_TSTR_MTFx bits */ - intstate = CheckINTState(CANx->TSTR, CAN_TSTR_MTF0 | CAN_TSTR_MTF1 | CAN_TSTR_MTF2); - break; - case CAN_INT_RFNE0: - /* Check CAN_RFR0_RFL0 bit */ - intstate = CheckINTState(CANx->RFR0, CAN_RFR0_RFL0); - break; - case CAN_INT_RFF0: - /* Check CAN_RFR0_RFF0 bit */ - intstate = CheckINTState(CANx->RFR0, CAN_RFR0_RFF0); - break; - case CAN_INT_RFO0: - /* Check CAN_RFR0_RFO0 bit */ - intstate = CheckINTState(CANx->RFR0, CAN_RFR0_RFO0); - break; - case CAN_INT_RFNE1: - /* Check CAN_RFR1_RFL1 bit */ - intstate = CheckINTState(CANx->RFR1, CAN_RFR1_RFL1); - break; - case CAN_INT_RFF1: - /* Check CAN_RFR1_RFF1 bit */ - intstate = CheckINTState(CANx->RFR1, CAN_RFR1_RFF1); - break; - case CAN_INT_RFO1: - /* Check CAN_RFR1_RFO1 bit */ - intstate = CheckINTState(CANx->RFR1, CAN_RFR1_RFO1); - break; - case CAN_INT_WU: - /* Check CAN_STR_WIF bit */ - intstate = CheckINTState(CANx->STR, CAN_STR_WIF); - break; - case CAN_INT_SLP: - /* Check CAN_STR_SEIF bit */ - intstate = CheckINTState(CANx->STR, CAN_STR_SEIF); - break; - case CAN_INT_WE: - /* Check CAN_INT_WE bit */ - intstate = CheckINTState(CANx->ER, CAN_ER_WE); - break; - case CAN_INT_PE: - /* Check CAN_INT_EP bit */ - intstate = CheckINTState(CANx->ER, CAN_ER_PE); - break; - case CAN_INT_BOE: - /* Check CAN_ER_BOE bit */ - intstate = CheckINTState(CANx->ER, CAN_ER_BOE); - break; - case CAN_INT_ET: - /* Check CAN_ER_ET bit */ - intstate = CheckINTState(CANx->ER, CAN_ER_ET); - break; - case CAN_INT_ERR: - /* Check CAN_STR_EIF bit */ - intstate = CheckINTState(CANx->STR, CAN_STR_EIF); - break; - default : - /* in case of error, return RESET */ - intstate = RESET; - break; - } - } else { - /* in case the Interrupt is not enabled, return RESET */ - intstate = RESET; - } - - /* Return the CAN_INT status */ - return intstate; -} - -/** - * @brief Clear the CANx's interrupt pending bits. - * @param CANx: where x:[1,2] to to select the CAN peripheral. - * @param CAN_INT: specify the interrupt pending bit to clear. - * This parameter can be: - * @arg CAN_INT_TME - * @arg CAN_INT_RFF0 - * @arg CAN_INT_RFO0 - * @arg CAN_INT_RFF1 - * @arg CAN_INT_RFO1 - * @arg CAN_INT_WE - * @arg CAN_INT_PE - * @arg CAN_INT_BOE - * @arg CAN_INT_ET - * @arg CAN_INT_ERR - * @arg CAN_INT_WU - * @arg CAN_INT_SLP - * @retval None. - */ -void CAN_ClearIntBitState(CAN_TypeDef *CANx, uint32_t CAN_INT) -{ - switch (CAN_INT) { - case CAN_INT_TME: - /* Clear CAN_TSTR_MTFx (rc_w1)*/ - CANx->TSTR = CAN_TSTR_MTF0 | CAN_TSTR_MTF1 | CAN_TSTR_MTF2; - break; - case CAN_INT_RFF0: - /* Clear CAN_RFR0_RFF0 (rc_w1)*/ - CANx->RFR0 = CAN_RFR0_RFF0; - break; - case CAN_INT_RFO0: - /* Clear CAN_RFR0_RFO0 (rc_w1)*/ - CANx->RFR0 = CAN_RFR0_RFO0; - break; - case CAN_INT_RFF1: - /* Clear CAN_RFR1_RFF1 (rc_w1)*/ - CANx->RFR1 = CAN_RFR1_RFF1; - break; - case CAN_INT_RFO1: - /* Clear CAN_RFR1_RFO1 (rc_w1)*/ - CANx->RFR1 = CAN_RFR1_RFO1; - break; - case CAN_INT_WU: - /* Clear CAN_STR_WIF (rc_w1)*/ - CANx->STR = CAN_STR_WIF; - break; - case CAN_INT_SLP: - /* Clear CAN_STR_SEIF (rc_w1)*/ - CANx->STR = CAN_STR_SEIF; - break; - case CAN_INT_WE: - /* Clear CAN_STR_EIF (rc_w1) */ - CANx->STR = CAN_STR_EIF; - break; - case CAN_INT_PE: - /* Clear CAN_MSR_ERRI (rc_w1) */ - CANx->STR = CAN_STR_EIF; - break; - case CAN_INT_BOE: - /* Clear CAN_STR_EIF (rc_w1) */ - CANx->STR = CAN_STR_EIF; - break; - case CAN_INT_ET: - /* Clear ET bits */ - CANx->ER = RESET; - /* Clear CAN_STR_EIF (rc_w1) */ - CANx->STR = CAN_STR_EIF; - break; - case CAN_INT_ERR: - /*Clear ET bits */ - CANx->ER = RESET; - /* Clear CAN_STR_EIF (rc_w1) */ - CANx->STR = CAN_STR_EIF; - break; - default : - break; - } -} - -/** - * @brief Check whether the CAN interrupt has occurred or not. - * @param CAN_Reg: the register of CAN interrupt to check. - * @param Int_Bit: the bit of interrupt source to check. - * @retval The new state of the CAN Interrupt (SET or RESET). - */ -static TypeState CheckINTState(uint32_t CAN_Reg, uint32_t Int_Bit) -{ - if ((CAN_Reg & Int_Bit) != (uint32_t)RESET) { - /* CAN_INT is set */ - return SET; - } else { - /* CAN_IT is reset */ - return RESET; - } -} - - -/** - * @} - */ - -/** - * @} - */ - -/** - * @} - */ diff --git a/bsp/gd32103c-eval/Libraries/GD32F1xx_standard_peripheral/Source/gd32f10x_crc.c b/bsp/gd32103c-eval/Libraries/GD32F1xx_standard_peripheral/Source/gd32f10x_crc.c deleted file mode 100644 index e081db43d0..0000000000 --- a/bsp/gd32103c-eval/Libraries/GD32F1xx_standard_peripheral/Source/gd32f10x_crc.c +++ /dev/null @@ -1,101 +0,0 @@ -/** - ****************************************************************************** - * @brief CRC functions of the firmware library. - ****************************************************************************** - */ - -/* Includes ------------------------------------------------------------------*/ -#include "gd32f10x_crc.h" - -/** @addtogroup GD32F10x_Firmware - * @{ - */ - -/** @defgroup CRC - * @brief CRC driver modules - * @{ - */ - -/** @defgroup CRC_Private_Functions - * @{ - */ - -/** - * @brief Reset CRC DTR register to the value of 0xFFFFFFFF. - * @param None - * @retval None - */ -void CRC_ResetDTR(void) -{ - CRC->CTLR = CRC_CTLR_RESET; -} - -/** - * @brief Compute the 32-bit CRC value of a 32-bit data. - * @param CRC_data: data to compute its CRC value - * @retval 32-bit CRC value - */ -uint32_t CRC_CalcSingleData(uint32_t CRC_data) -{ - CRC->DTR = CRC_data; - - return (CRC->DTR); -} - -/** - * @brief Compute the 32-bit CRC value of a 32-bit data array. - * @param pbuffer[]: pointer to the data array - * @param buffer_length: length of the data array - * @retval 32-bit CRC value - */ -uint32_t CRC_CalcDataFlow(uint32_t pbuffer[], uint32_t buffer_length) -{ - uint32_t index = 0; - - for (index = 0; index < buffer_length; index++) { - CRC->DTR = pbuffer[index]; - } - return (CRC->DTR); -} - -/** - * @brief Read current CRC value. - * @param None - * @retval 32-bit CRC value - */ -uint32_t CRC_ReadDTR(void) -{ - return (CRC->DTR); -} - -/** - * @brief Write an 8-bit data in FDTR. - * @param CRC_fdtr: 8-bit data to write - * @retval None - */ -void CRC_WriteFDTR(uint8_t CRC_fdtr) -{ - CRC->FDTR = CRC_fdtr; -} - -/** - * @brief Read the 8-bit data stored in FDTR - * @param None - * @retval 8-bit data - */ -uint8_t CRC_ReadFDTR(void) -{ - return (CRC->FDTR); -} - -/** - * @} - */ - -/** - * @} - */ - -/** - * @} - */ diff --git a/bsp/gd32103c-eval/Libraries/GD32F1xx_standard_peripheral/Source/gd32f10x_dac.c b/bsp/gd32103c-eval/Libraries/GD32F1xx_standard_peripheral/Source/gd32f10x_dac.c deleted file mode 100644 index d50c031de6..0000000000 --- a/bsp/gd32103c-eval/Libraries/GD32F1xx_standard_peripheral/Source/gd32f10x_dac.c +++ /dev/null @@ -1,326 +0,0 @@ -/** - ****************************************************************************** - * @brief DAC functions of the firmware library. - ****************************************************************************** - */ - -/* Includes ------------------------------------------------------------------*/ -#include "gd32f10x_dac.h" -#include "gd32f10x_rcc.h" -/** @addtogroup GD32F10x_Firmware - * @{ - */ - -/** @defgroup DAC - * @brief DAC driver modules - * @{ - */ - -/** @defgroup DAC_Private_Defines - * @{ - */ -/* CTLR register bits mask */ -#define CTLR_BITS_CLEAR ((uint32_t)0x00000FFE) -/* DAC Dual Channels SWTRIG masks */ -#define DUAL_SWTRIG_SET ((uint32_t)0x00000003) -/* DHR registers offsets */ -#define DHR12R1_OFFSET ((uint32_t)0x00000008) -#define DHR12R2_OFFSET ((uint32_t)0x00000014) -#define DHR12RD_OFFSET ((uint32_t)0x00000020) -/* DOR register offset */ -#define DOR_OFFSET ((uint32_t)0x0000002C) - -/** - * @} - */ - -/** @defgroup DAC_Private_Functions - * @{ - */ - -/** - * @brief Deinitialize the DAC peripheral registers. - * @param DAC_InitParaStruct: DAC_InitPara structure that contains the - * configuration information for the selected DAC channel. - * @retval None - */ -void DAC_DeInit(DAC_InitPara *DAC_InitParaStruct) -{ - /* Enable DAC reset state */ - RCC_APB1PeriphReset_Enable(RCC_APB1PERIPH_DACRST, ENABLE); - /* Release DAC from reset state */ - RCC_APB1PeriphReset_Enable(RCC_APB1PERIPH_DACRST, DISABLE); - /* Initialize the DAC_Trigger */ - DAC_InitParaStruct->DAC_Trigger = DAC_TRIGGER_NONE; - /* Initialize the DAC_WaveGeneration */ - DAC_InitParaStruct->DAC_WaveType = DAC_WAVEGENE_NONE; - /* Initialize the DAC_LFSRUnmask_TriangleAmplitude */ - DAC_InitParaStruct->DAC_LFSRNoise_AmplitudeTriangle = DAC_LFSR_BIT0; - /* Initialize the DAC_OutputBuffer */ - DAC_InitParaStruct->DAC_OutputBuffer = DAC_OUTPUTBUFFER_ENABLE; -} - -/** - * @brief Initialize the DAC peripheral. - * @param DAC_Channel: the selected DAC channel. - * This parameter can be one of the following values: - * @arg DAC_Channel_1: select DAC Channel1 - * @arg DAC_Channel_2: select DAC Channel2 - * @param DAC_InitStruct: DAC_InitTypeDef structure . - * @retval None - */ -void DAC_Init(uint32_t DAC_Channel, DAC_InitPara *DAC_InitParaStruct) -{ - uint32_t temp1 = 0, temp2 = 0; - - /* DAC CTLR Configuration */ - /* Get the DAC CTLR value */ - temp1 = DAC->CTLR; - - /* Clear BOFF, TEN, TSEL, WAVE and MAMP bits */ - temp1 &= ~(CTLR_BITS_CLEAR << DAC_Channel); - - /* Configure for the DAC channel: buffer output, trigger, wave generation, - mask/amplitude for wave generation */ - /* Set TSEL and TEN bits according to DAC_Trigger */ - /* Set WAVE bits according to DAC_WaveType */ - /* Set MAMP bits according to DAC_LFSRNoise_AmplitudeTriangle */ - /* Set BOFF bit according to DAC_OutputBuffer */ - temp2 = (DAC_InitParaStruct->DAC_Trigger | DAC_InitParaStruct->DAC_OutputBuffer | - DAC_InitParaStruct->DAC_WaveType | DAC_InitParaStruct->DAC_LFSRNoise_AmplitudeTriangle); - /* Calculate CTLR register value */ - temp1 |= temp2 << DAC_Channel; - - /* Write to DAC CTLR */ - DAC->CTLR = temp1; -} - -/** - * @brief Enable or disable the DAC channel. - * @param DAC_Channel: the selected DAC channel. - * This parameter can be one of the following values: - * @arg DAC_Channel_1: select DAC Channel1. - * @arg DAC_Channel_2: select DAC Channel2. - * @param NewValue: New value of the DAC channel. - * This parameter can be: ENABLE or DISABLE. - * @retval None - */ -void DAC_Enable(uint32_t DAC_Channel, TypeState NewValue) -{ - if (NewValue != DISABLE) { - /* Enable the selected DAC channel */ - DAC->CTLR |= (DAC_CTLR_DEN1 << DAC_Channel) ; - } else { - /* Disable the selected DAC channel */ - DAC->CTLR &= ~(DAC_CTLR_DEN1 << DAC_Channel); - } -} - -/** - * @brief Enable or disable the selected DAC channel software trigger. - * @param DAC_Channel: the selected DAC channel. - * This parameter can be one of the following values: - * @arg DAC_Channel_1: select DAC Channel1 - * @arg DAC_Channel_2: select DAC Channel2 - * @param NewValue: New value of the selected DAC channel software trigger. - * This parameter can be: ENABLE or DISABLE. - * @retval None - */ -void DAC_SoftwareTrigger_Enable(uint32_t DAC_Channel, TypeState NewValue) -{ - if (NewValue != DISABLE) { - /* Enable software trigger for DAC channel1 */ - DAC->SWTR |= (uint32_t)DAC_SWTR_SWTR1 << (DAC_Channel >> 4); - } else { - /* Disable software trigger for DAC channel1 */ - DAC->SWTR &= ~((uint32_t)DAC_SWTR_SWTR1 << (DAC_Channel >> 4)); - } -} - -/** - * @brief Enable or disable simultaneously the two DAC channels software - * triggers. - * @param NewValue: new value of the DAC channels software triggers. - * This parameter can be: ENABLE or DISABLE. - * @retval None - */ -void DAC_DualSoftwareTrigger_Enable(TypeState NewValue) -{ - if (NewValue != DISABLE) { - /* Enable software trigger */ - DAC->SWTR |= DUAL_SWTRIG_SET ; - } else { - /* Disable software trigger */ - DAC->SWTR &= ~DUAL_SWTRIG_SET; - } -} - -/** - * @brief Enable or disable the selected DAC channel wave generation. - * @param DAC_Channel: the selected DAC channel. - * This parameter can be one of the following values: - * @arg DAC_Channel_1: select DAC Channel1 - * @arg DAC_Channel_2: select DAC Channel2 - * @param DAC_Wave: the wave type to enable or disable. - * This parameter can be one of the following values: - * @arg DAC_WAVE_NOISE: noise wave generation - * @arg DAC_WAVE_TRIANGLE: triangle wave generation - * @param NewValue: new value of the selected DAC channel wave generation. - * This parameter can be: ENABLE or DISABLE. - * @retval None - */ -void DAC_WaveGeneration_Enable(uint32_t DAC_Channel, uint32_t DAC_Wave, TypeState NewValue) -{ - if (NewValue != DISABLE) { - /* Enable the selected DAC channel wave generation */ - DAC->CTLR |= DAC_Wave << DAC_Channel; - } else { - /* Disable the selected DAC channel wave generation */ - DAC->CTLR &= ~(DAC_Wave << DAC_Channel); - } -} - -/** - * @brief Set the specified data holding register value for DAC channel1. - * @param DAC_Align: the data alignment for DAC channel1. - * This parameter can be one of the following values: - * @arg DAC_ALIGN_8B_R: select 8bit right data alignment - * @arg DAC_ALIGN_12B_L: select 12bit left data alignment - * @arg DAC_ALIGN_12B_R: select 12bit right data alignment - * @param Data: Data to be loaded. - * @retval None - */ -void DAC_SetChannel1Data(uint32_t DAC_Align, uint16_t Data) -{ - __IO uint32_t temp = 0; - - temp = (uint32_t)DAC_BASE; - temp += DHR12R1_OFFSET + DAC_Align; - - /* Set the DAC channel1 */ - *(__IO uint32_t *) temp = Data; -} - -/** - * @brief Set the specified data holding register value for DAC channel2. - * @param DAC_Align: the data alignment for DAC channel2. - * This parameter can be one of the following values: - * @arg DAC_ALIGN_8B_R: select 8bit right data alignment - * @arg DAC_ALIGN_12B_L: select 12bit left data alignment - * @arg DAC_ALIGN_12B_R: select 12bit right data alignment - * @param Data: Data to be loaded. - * @retval None - */ -void DAC_SetChannel2Data(uint32_t DAC_Align, uint16_t Data) -{ - __IO uint32_t temp = 0; - - temp = (uint32_t)DAC_BASE; - temp += DHR12R2_OFFSET + DAC_Align; - - /* Set the DAC channel2 */ - *(__IO uint32_t *) temp = Data; -} - -/** - * @brief Set the specified data for dual channel - * @param DAC_Align: the data alignment for dual channel DAC. - * This parameter can be one of the following values: - * @arg DAC_Align_8b_R: select 8bit right data alignment - * @arg DAC_Align_12b_L: select 12bit left data alignment - * @arg DAC_Align_12b_R: select 12bit right data alignment - * @param Data2: Data for DAC Channel2. - * @param Data1: Data for DAC Channel1. - * @retval None - */ -void DAC_SetDualChannelData(uint32_t DAC_Align, uint16_t Data2, uint16_t Data1) -{ - uint32_t data = 0, temp = 0; - - /* set dual DAC data holding register value */ - if (DAC_Align == DAC_ALIGN_8B_R) { - data = ((uint32_t)Data2 << 8) | Data1; - } else { - data = ((uint32_t)Data2 << 16) | Data1; - } - - temp = (uint32_t)DAC_BASE; - temp += DHR12RD_OFFSET + DAC_Align; - - /* Set the dual DAC selected data holding register */ - *(__IO uint32_t *)temp = data; -} - -/** - * @brief Return the last data output value. - * @param DAC_Channel: the selected DAC channel. - * This parameter can be one of the following values: - * @arg DAC_Channel_1: select DAC Channel1 - * @arg DAC_Channel_2: select DAC Channel2 - * @retval The DAC channel1 data output value. - */ -uint16_t DAC_GetDataOutputValue(uint32_t DAC_Channel) -{ - __IO uint32_t temp = 0; - - temp = (uint32_t) DAC_BASE; - temp += DOR_OFFSET + ((uint32_t)DAC_Channel >> 2); - - /* Returns the DAC channel data */ - return (uint16_t)(*(__IO uint32_t *) temp); -} - -/** - * @brief Enable or disable DMA request. - * @param DAC_Channel: the selected DAC channel. - * This parameter can be one of the following values: - * @arg DAC_Channel_1: select DAC Channel1 - * @arg DAC_Channel_2: select DAC Channel2 - * @param NewValue: New value of the selected DAC channel DMA request. - * This parameter can be: ENABLE or DISABLE. - * @retval None - */ -void DAC_DMA_Enable(uint32_t DAC_Channel, TypeState NewValue) -{ - if (NewValue != DISABLE) { - /* Enable DMA request */ - DAC->CTLR |= (DAC_CTLR_DDMAEN1 << DAC_Channel); - } else { - /* Disable DMA request */ - DAC->CTLR &= ~(DAC_CTLR_DDMAEN1 << DAC_Channel); - } -} - -/** - * @brief Enable or disable the specified DAC interrupts. - * @param DAC_Channel: the selected DAC channel. - * This parameter can be one of the following values: - * @arg DAC_Channel_1: DAC Channel1 selected - * @arg DAC_Channel_2: DAC Channel2 selected - * @param NewValue: Alternative state of the specified DAC interrupts. - * This parameter can be: ENABLE or DISABLE. - * @retval None - */ -void DAC_INTConfig(uint32_t DAC_Channel, TypeState NewValue) -{ - if (NewValue != DISABLE) { - /* Enable the DAC DMAUDR interrupts */ - DAC->CTLR |= (DAC_INT_DMAUDR << DAC_Channel); - } else { - /* Disable the DAC DMAUDR interrupts */ - DAC->CTLR &= (~(uint32_t)(DAC_INT_DMAUDR << DAC_Channel)); - } -} - -/** - * @} - */ - -/** - * @} - */ - -/** - * @} - */ - diff --git a/bsp/gd32103c-eval/Libraries/GD32F1xx_standard_peripheral/Source/gd32f10x_dma.c b/bsp/gd32103c-eval/Libraries/GD32F1xx_standard_peripheral/Source/gd32f10x_dma.c deleted file mode 100644 index a519b30b9a..0000000000 --- a/bsp/gd32103c-eval/Libraries/GD32F1xx_standard_peripheral/Source/gd32f10x_dma.c +++ /dev/null @@ -1,553 +0,0 @@ -/** - ****************************************************************************** - * @brief DMA functions of the firmware library. - ****************************************************************************** - */ - - -/* Includes ------------------------------------------------------------------*/ -#include "gd32f10x_dma.h" -#include "gd32f10x_rcc.h" - -/** @addtogroup GD32F10x_Firmware - * @{ - */ - -/** @defgroup DMA - * @brief DMA driver modules - * @{ - */ - -/** @defgroup DMA_Private_Defines - * @{ - */ - -/* DMA Reset registers mask */ -#define DMA_REGISTERS_RESET ((uint32_t)0x00000000) - -/* DMA Channel config registers Masks */ -#define CTLR_CLEAR_MASK ((uint32_t)0xFFFF800F) - -/* DMA Reset registers mask */ -#define DMA_INT_RESET ((uint32_t)0x00000000) - -/* DMA2 FLAG mask */ -#define DMA2_FLAG_Mask ((uint32_t)0x10000000) - -/* DMA1 Channelx interrupt pending bit masks */ -#define DMA1_Channel1_INT_Mask ((uint32_t)(DMA_IFR_GIF1 | DMA_IFR_TCIF1 | DMA_IFR_HTIF1 | DMA_IFR_ERRIF1)) -#define DMA1_Channel2_INT_Mask ((uint32_t)(DMA_IFR_GIF2 | DMA_IFR_TCIF2 | DMA_IFR_HTIF2 | DMA_IFR_ERRIF2)) -#define DMA1_Channel3_INT_Mask ((uint32_t)(DMA_IFR_GIF3 | DMA_IFR_TCIF3 | DMA_IFR_HTIF3 | DMA_IFR_ERRIF3)) -#define DMA1_Channel4_INT_Mask ((uint32_t)(DMA_IFR_GIF4 | DMA_IFR_TCIF4 | DMA_IFR_HTIF4 | DMA_IFR_ERRIF4)) -#define DMA1_Channel5_INT_Mask ((uint32_t)(DMA_IFR_GIF5 | DMA_IFR_TCIF5 | DMA_IFR_HTIF5 | DMA_IFR_ERRIF5)) -#define DMA1_Channel6_INT_Mask ((uint32_t)(DMA_IFR_GIF6 | DMA_IFR_TCIF6 | DMA_IFR_HTIF6 | DMA_IFR_ERRIF6)) -#define DMA1_Channel7_INT_Mask ((uint32_t)(DMA_IFR_GIF7 | DMA_IFR_TCIF7 | DMA_IFR_HTIF7 | DMA_IFR_ERRIF7)) - -/* DMA2 Channelx interrupt pending bit masks */ -#define DMA2_Channel1_INT_Mask ((uint32_t)(DMA_IFR_GIF1 | DMA_IFR_TCIF1 | DMA_IFR_HTIF1 | DMA_IFR_ERRIF1)) -#define DMA2_Channel2_INT_Mask ((uint32_t)(DMA_IFR_GIF2 | DMA_IFR_TCIF2 | DMA_IFR_HTIF2 | DMA_IFR_ERRIF2)) -#define DMA2_Channel3_INT_Mask ((uint32_t)(DMA_IFR_GIF3 | DMA_IFR_TCIF3 | DMA_IFR_HTIF3 | DMA_IFR_ERRIF3)) -#define DMA2_Channel4_INT_Mask ((uint32_t)(DMA_IFR_GIF4 | DMA_IFR_TCIF4 | DMA_IFR_HTIF4 | DMA_IFR_ERRIF4)) -#define DMA2_Channel5_INT_Mask ((uint32_t)(DMA_IFR_GIF5 | DMA_IFR_TCIF5 | DMA_IFR_HTIF5 | DMA_IFR_ERRIF5)) - -/** - * @} - */ - - -/** @defgroup DMA_Private_Functions - * @{ - */ - -/** - * @brief Deinitialize the DMAy Channelx registers - * @param DMAy_Channelx: where y:[1,2] to select the DMA , x:[1,7] for DMA1 and x:[1,5] for DMA2 to select the DMA Channel. - * @retval None - */ -void DMA_DeInit(DMA_Channel_TypeDef *DMAy_Channelx) -{ - /* Disable the selected DMAy Channelx */ - DMAy_Channelx->CTLR &= (uint16_t)(~DMA_CTLR_CHEN); - - /* Reset DMAy Channelx control register */ - DMAy_Channelx->CTLR = DMA_REGISTERS_RESET; - - /* Reset DMAy Channelx remaining bytes register */ - DMAy_Channelx->RCNT = DMA_REGISTERS_RESET; - - /* Reset DMAy Channelx peripheral address register */ - DMAy_Channelx->PBAR = DMA_REGISTERS_RESET; - - /* Reset DMAy Channelx memory address register */ - DMAy_Channelx->MBAR = DMA_REGISTERS_RESET; - - if (DMAy_Channelx == DMA1_CHANNEL1) { - /* Reset interrupt pending bits for DMA1 Channel1 */ - DMA1->ICR |= DMA1_Channel1_INT_Mask; - } else if (DMAy_Channelx == DMA1_CHANNEL2) { - /* Reset interrupt pending bits for DMA1 Channel2 */ - DMA1->ICR |= DMA1_Channel2_INT_Mask; - } else if (DMAy_Channelx == DMA1_CHANNEL3) { - /* Reset interrupt pending bits for DMA1 Channel3 */ - DMA1->ICR |= DMA1_Channel3_INT_Mask; - } else if (DMAy_Channelx == DMA1_CHANNEL4) { - /* Reset interrupt pending bits for DMA1 Channel4 */ - DMA1->ICR |= DMA1_Channel4_INT_Mask; - } else if (DMAy_Channelx == DMA1_CHANNEL5) { - /* Reset interrupt pending bits for DMA1 Channel5 */ - DMA1->ICR |= DMA1_Channel5_INT_Mask; - } else if (DMAy_Channelx == DMA1_CHANNEL6) { - /* Reset interrupt pending bits for DMA1 Channel6 */ - DMA1->ICR |= DMA1_Channel6_INT_Mask; - } else if (DMAy_Channelx == DMA1_CHANNEL7) { - /* Reset interrupt pending bits for DMA1 Channel7 */ - DMA1->ICR |= DMA1_Channel7_INT_Mask; - } else if (DMAy_Channelx == DMA2_CHANNEL1) { - /* Reset interrupt pending bits for DMA2 Channel1 */ - DMA2->ICR |= DMA2_Channel1_INT_Mask; - } else if (DMAy_Channelx == DMA2_CHANNEL2) { - /* Reset interrupt pending bits for DMA2 Channel2 */ - DMA2->ICR |= DMA2_Channel2_INT_Mask; - } else if (DMAy_Channelx == DMA2_CHANNEL3) { - /* Reset interrupt pending bits for DMA2 Channel3 */ - DMA2->ICR |= DMA2_Channel3_INT_Mask; - } else if (DMAy_Channelx == DMA2_CHANNEL4) { - /* Reset interrupt pending bits for DMA2 Channel4 */ - DMA2->ICR |= DMA2_Channel4_INT_Mask; - } else { - if (DMAy_Channelx == DMA2_CHANNEL5) { - /* Reset interrupt pending bits for DMA2 Channel5 */ - DMA2->ICR |= DMA2_Channel5_INT_Mask; - } - } -} - - -/** - * @brief Initialize the DMAy Channelx according to the DMA_InitParaStruct. - * @param DMAy_Channelx: where y:[1:2] to select the DMA , x:[1,7] for DMA1 and x:[1,5] for DMA2 to select the DMA Channel. - * @param DMA_InitParaStruct: contain the configuration information for the specified DMA Channel. - * @retval None - */ -void DMA_Init(DMA_Channel_TypeDef *DMAy_Channelx, DMA_InitPara *DMA_InitParaStruct) -{ - uint32_t temp = 0; - - /* Get the DMAy_Channelx CCR value */ - temp = DMAy_Channelx->CTLR; - - /* Clear MEMTOMEM, PRIO, MSIZE, PSIZE, MNAGA, PNAGA, CIRC and DIR bits */ - temp &= CTLR_CLEAR_MASK; - /* Configure DMAy Channelx: data transfer, data size, priority level and mode */ - /* Set MEMTOMEM, PRIO, MSIZE, PSIZE, MNAGA, PNAGA, CIRC and DIR bits according to DMA_InitParaStruct */ - temp |= DMA_InitParaStruct->DMA_DIR | DMA_InitParaStruct->DMA_Mode | - DMA_InitParaStruct->DMA_PeripheralInc | DMA_InitParaStruct->DMA_MemoryInc | - DMA_InitParaStruct->DMA_PeripheralDataSize | DMA_InitParaStruct->DMA_MemoryDataSize | - DMA_InitParaStruct->DMA_Priority | DMA_InitParaStruct->DMA_MTOM; - - /* Write to DMAy Channelx CTLR */ - DMAy_Channelx->CTLR = temp; - - /* Write to DMAy Channelx RCNT */ - DMAy_Channelx->RCNT = DMA_InitParaStruct->DMA_BufferSize; - - /* Write to DMAy Channelx PBAR */ - DMAy_Channelx->PBAR = DMA_InitParaStruct->DMA_PeripheralBaseAddr; - - /* Write to DMAy Channelx MBAR */ - DMAy_Channelx->MBAR = DMA_InitParaStruct->DMA_MemoryBaseAddr; -} - -/** - * @brief Set each DMA_InitParaStruct member to its default value. - * @param DMA_InitParaStruct: The structure pointer to DMA_InitParaStruct will be initialized. - * @retval None - */ -void DMA_ParaInit(DMA_InitPara *DMA_InitParaStruct) -{ - /* Reset DMA init structure parameters values */ - DMA_InitParaStruct->DMA_PeripheralBaseAddr = DMA_INT_RESET; - - DMA_InitParaStruct->DMA_MemoryBaseAddr = DMA_INT_RESET; - - DMA_InitParaStruct->DMA_DIR = DMA_DIR_PERIPHERALSRC; - - DMA_InitParaStruct->DMA_BufferSize = DMA_INT_RESET; - - DMA_InitParaStruct->DMA_PeripheralInc = DMA_PERIPHERALINC_DISABLE; - - DMA_InitParaStruct->DMA_MemoryInc = DMA_MEMORYINC_DISABLE; - - DMA_InitParaStruct->DMA_PeripheralDataSize = DMA_PERIPHERALDATASIZE_BYTE; - - DMA_InitParaStruct->DMA_MemoryDataSize = DMA_MEMORYDATASIZE_BYTE; - - DMA_InitParaStruct->DMA_Mode = DMA_MODE_NORMAL; - - DMA_InitParaStruct->DMA_Priority = DMA_PRIORITY_LOW; - - DMA_InitParaStruct->DMA_MTOM = DMA_MEMTOMEM_DISABLE; -} - -/** - * @brief Enable or disable the DMAy Channelx. - * @param DMAy_Channelx: where y:[1:2] to select the DMA , x:[1,7] for DMA1 and x:[1,5] for DMA2 to select the DMA Channel. - * @param NewValue: new state of the DMAy Channelx. - * This parameter can be: ENABLE or DISABLE. - * @retval None - */ -void DMA_Enable(DMA_Channel_TypeDef *DMAy_Channelx, TypeState NewValue) -{ - if (NewValue != DISABLE) { - /* Enable the DMAy Channelx */ - DMAy_Channelx->CTLR |= DMA_CTLR_CHEN; - } else { - /* Disable the DMAy Channelx */ - DMAy_Channelx->CTLR &= (uint16_t)(~DMA_CTLR_CHEN); - } -} - -/** - * @brief Enable or disable the DMAy Channelx interrupts. - * @param DMAy_Channelx: where y:[1:2] to select the DMA , x:[1,7] for DMA1 and x:[1,5] for DMA2 to select the DMA Channel. - * @param DMA_INT: specify the DMA interrupts sources to be enabled or disabled. - * This parameter can be any combination of the following values: - * @arg DMA_INT_TC: Transfer complete interrupt mask - * @arg DMA_INT_HT: Half transfer interrupt mask - * @arg DMA_INT_ERR: Transfer error interrupt mask - * @param NewValue: new state of the DMA interrupts. - * This parameter can be: ENABLE or DISABLE. - * @retval None - */ -void DMA_INTConfig(DMA_Channel_TypeDef *DMAy_Channelx, uint32_t DMA_INT, TypeState NewValue) -{ - if (NewValue != DISABLE) { - /* Enable the DMA interrupts */ - DMAy_Channelx->CTLR |= DMA_INT; - } else { - /* Disable the DMA interrupts */ - DMAy_Channelx->CTLR &= ~DMA_INT; - } -} - -/** - * @brief Set the number of the remaining counter in the current DMAy Channelx transfer. - * @param DMAy_Channelx: where y:[1:2] to select the DMA , x:[1,7] for DMA1 and x:[1,5] for DMA2 to select the DMA Channel. - * @param DataNumber: The number of the remaining counter in the current DMAy Channelx transfer. - * @retval None. - */ -void DMA_SetCurrDataCounter(DMA_Channel_TypeDef *DMAy_Channelx, uint16_t DataNumber) -{ - /* Write to DMAy Channelx RCNT */ - DMAy_Channelx->RCNT = DataNumber; -} - -/** - * @brief Return the number of remaining counter in the current DMAy Channelx transfer. - * @param DMAy_Channelx: where y:[1:2] to select the DMA , x:[1,7] for DMA1 and x:[1,5] for DMA2 to select the DMA Channel. - * @retval The number of remaining counter in the current DMAy Channelx transfer. - */ -uint16_t DMA_GetCurrDataCounter(DMA_Channel_TypeDef *DMAy_Channelx) -{ - /* Return the number of remaining counter for DMAy Channelx */ - return ((uint16_t)(DMAy_Channelx->RCNT)); -} - -/** - * @brief Check whether the DMAy Channelx flag is set or not. - * @param DMAy_FLAG: specifies the flag to check. - * This parameter can be one of the following values: - * @arg DMA1_FLAG_GL1: DMA1 Channel1 global flag. - * @arg DMA1_FLAG_TC1: DMA1 Channel1 transfer complete flag. - * @arg DMA1_FLAG_HT1: DMA1 Channel1 half transfer flag. - * @arg DMA1_FLAG_TE1: DMA1 Channel1 transfer error flag. - * @arg DMA1_FLAG_GL2: DMA1 Channel2 global flag. - * @arg DMA1_FLAG_TC2: DMA1 Channel2 transfer complete flag. - * @arg DMA1_FLAG_HT2: DMA1 Channel2 half transfer flag. - * @arg DMA1_FLAG_TE2: DMA1 Channel2 transfer error flag. - * @arg DMA1_FLAG_GL3: DMA1 Channel3 global flag. - * @arg DMA1_FLAG_TC3: DMA1 Channel3 transfer complete flag. - * @arg DMA1_FLAG_HT3: DMA1 Channel3 half transfer flag. - * @arg DMA1_FLAG_TE3: DMA1 Channel3 transfer error flag. - * @arg DMA1_FLAG_GL4: DMA1 Channel4 global flag. - * @arg DMA1_FLAG_TC4: DMA1 Channel4 transfer complete flag. - * @arg DMA1_FLAG_HT4: DMA1 Channel4 half transfer flag. - * @arg DMA1_FLAG_TE4: DMA1 Channel4 transfer error flag. - * @arg DMA1_FLAG_GL5: DMA1 Channel5 global flag. - * @arg DMA1_FLAG_TC5: DMA1 Channel5 transfer complete flag. - * @arg DMA1_FLAG_HT5: DMA1 Channel5 half transfer flag. - * @arg DMA1_FLAG_TE5: DMA1 Channel5 transfer error flag. - * @arg DMA1_FLAG_GL6: DMA1 Channel6 global flag. - * @arg DMA1_FLAG_TC6: DMA1 Channel6 transfer complete flag. - * @arg DMA1_FLAG_HT6: DMA1 Channel6 half transfer flag. - * @arg DMA1_FLAG_TE6: DMA1 Channel6 transfer error flag. - * @arg DMA1_FLAG_GL7: DMA1 Channel7 global flag. - * @arg DMA1_FLAG_TC7: DMA1 Channel7 transfer complete flag. - * @arg DMA1_FLAG_HT7: DMA1 Channel7 half transfer flag. - * @arg DMA1_FLAG_TE7: DMA1 Channel7 transfer error flag. - * @arg DMA2_FLAG_GL1: DMA2 Channel1 global flag. - * @arg DMA2_FLAG_TC1: DMA2 Channel1 transfer complete flag. - * @arg DMA2_FLAG_HT1: DMA2 Channel1 half transfer flag. - * @arg DMA2_FLAG_TE1: DMA2 Channel1 transfer error flag. - * @arg DMA2_FLAG_GL2: DMA2 Channel2 global flag. - * @arg DMA2_FLAG_TC2: DMA2 Channel2 transfer complete flag. - * @arg DMA2_FLAG_HT2: DMA2 Channel2 half transfer flag. - * @arg DMA2_FLAG_TE2: DMA2 Channel2 transfer error flag. - * @arg DMA2_FLAG_GL3: DMA2 Channel3 global flag. - * @arg DMA2_FLAG_TC3: DMA2 Channel3 transfer complete flag. - * @arg DMA2_FLAG_HT3: DMA2 Channel3 half transfer flag. - * @arg DMA2_FLAG_TE3: DMA2 Channel3 transfer error flag. - * @arg DMA2_FLAG_GL4: DMA2 Channel4 global flag. - * @arg DMA2_FLAG_TC4: DMA2 Channel4 transfer complete flag. - * @arg DMA2_FLAG_HT4: DMA2 Channel4 half transfer flag. - * @arg DMA2_FLAG_TE4: DMA2 Channel4 transfer error flag. - * @arg DMA2_FLAG_GL5: DMA2 Channel5 global flag. - * @arg DMA2_FLAG_TC5: DMA2 Channel5 transfer complete flag. - * @arg DMA2_FLAG_HT5: DMA2 Channel5 half transfer flag. - * @arg DMA2_FLAG_TE5: DMA2 Channel5 transfer error flag. - * @retval The new state of DMAy_FLAG (SET or RESET). - */ -TypeState DMA_GetBitState(uint32_t DMAy_FLAG) -{ - uint32_t temp = 0; - - /* Check the used DMAy */ - if ((DMAy_FLAG & DMA2_FLAG_Mask) != (uint32_t)RESET) { - /* Get DMA2 ISR register value */ - temp = DMA2->IFR ; - } else { - /* Get DMA1 ISR register value */ - temp = DMA1->IFR ; - } - - /* Check the status of the DMAy flag */ - if ((temp & DMAy_FLAG) != (uint32_t)RESET) { - /* DMAy_FLAG is set */ - return SET; - } else { - /* DMAy_FLAG is reset */ - return RESET; - } -} - -/** - * @brief Clear the DMAy Channelx's bit flags. - * @param DMAy_FLAG: specifies the flag to clear. - * This parameter can be any combination (for the same DMA) of the following values: - * @arg DMA1_FLAG_GL1: DMA1 Channel1 global flag. - * @arg DMA1_FLAG_TC1: DMA1 Channel1 transfer complete flag. - * @arg DMA1_FLAG_HT1: DMA1 Channel1 half transfer flag. - * @arg DMA1_FLAG_TE1: DMA1 Channel1 transfer error flag. - * @arg DMA1_FLAG_GL2: DMA1 Channel2 global flag. - * @arg DMA1_FLAG_TC2: DMA1 Channel2 transfer complete flag. - * @arg DMA1_FLAG_HT2: DMA1 Channel2 half transfer flag. - * @arg DMA1_FLAG_TE2: DMA1 Channel2 transfer error flag. - * @arg DMA1_FLAG_GL3: DMA1 Channel3 global flag. - * @arg DMA1_FLAG_TC3: DMA1 Channel3 transfer complete flag. - * @arg DMA1_FLAG_HT3: DMA1 Channel3 half transfer flag. - * @arg DMA1_FLAG_TE3: DMA1 Channel3 transfer error flag. - * @arg DMA1_FLAG_GL4: DMA1 Channel4 global flag. - * @arg DMA1_FLAG_TC4: DMA1 Channel4 transfer complete flag. - * @arg DMA1_FLAG_HT4: DMA1 Channel4 half transfer flag. - * @arg DMA1_FLAG_TE4: DMA1 Channel4 transfer error flag. - * @arg DMA1_FLAG_GL5: DMA1 Channel5 global flag. - * @arg DMA1_FLAG_TC5: DMA1 Channel5 transfer complete flag. - * @arg DMA1_FLAG_HT5: DMA1 Channel5 half transfer flag. - * @arg DMA1_FLAG_TE5: DMA1 Channel5 transfer error flag. - * @arg DMA1_FLAG_GL6: DMA1 Channel6 global flag. - * @arg DMA1_FLAG_TC6: DMA1 Channel6 transfer complete flag. - * @arg DMA1_FLAG_HT6: DMA1 Channel6 half transfer flag. - * @arg DMA1_FLAG_TE6: DMA1 Channel6 transfer error flag. - * @arg DMA1_FLAG_GL7: DMA1 Channel7 global flag. - * @arg DMA1_FLAG_TC7: DMA1 Channel7 transfer complete flag. - * @arg DMA1_FLAG_HT7: DMA1 Channel7 half transfer flag. - * @arg DMA1_FLAG_TE7: DMA1 Channel7 transfer error flag. - * @arg DMA2_FLAG_GL1: DMA2 Channel1 global flag. - * @arg DMA2_FLAG_TC1: DMA2 Channel1 transfer complete flag. - * @arg DMA2_FLAG_HT1: DMA2 Channel1 half transfer flag. - * @arg DMA2_FLAG_TE1: DMA2 Channel1 transfer error flag. - * @arg DMA2_FLAG_GL2: DMA2 Channel2 global flag. - * @arg DMA2_FLAG_TC2: DMA2 Channel2 transfer complete flag. - * @arg DMA2_FLAG_HT2: DMA2 Channel2 half transfer flag. - * @arg DMA2_FLAG_TE2: DMA2 Channel2 transfer error flag. - * @arg DMA2_FLAG_GL3: DMA2 Channel3 global flag. - * @arg DMA2_FLAG_TC3: DMA2 Channel3 transfer complete flag. - * @arg DMA2_FLAG_HT3: DMA2 Channel3 half transfer flag. - * @arg DMA2_FLAG_TE3: DMA2 Channel3 transfer error flag. - * @arg DMA2_FLAG_GL4: DMA2 Channel4 global flag. - * @arg DMA2_FLAG_TC4: DMA2 Channel4 transfer complete flag. - * @arg DMA2_FLAG_HT4: DMA2 Channel4 half transfer flag. - * @arg DMA2_FLAG_TE4: DMA2 Channel4 transfer error flag. - * @arg DMA2_FLAG_GL5: DMA2 Channel5 global flag. - * @arg DMA2_FLAG_TC5: DMA2 Channel5 transfer complete flag. - * @arg DMA2_FLAG_HT5: DMA2 Channel5 half transfer flag. - * @arg DMA2_FLAG_TE5: DMA2 Channel5 transfer error flag. - * @retval None - */ -void DMA_ClearBitState(uint32_t DMAy_FLAG) -{ - /* Check the used DMAy */ - if ((DMAy_FLAG & DMA2_FLAG_Mask) != (uint32_t)RESET) { - /* Clear the selected DMAy flags */ - DMA2->ICR = DMAy_FLAG; - } else { - /* Clear the selected DMAy flags */ - DMA1->ICR = DMAy_FLAG; - } -} - -/** - * @brief Check whether the DMAy Channelx interrupt has occurred or not. - * @param DMAy_INT: specify the DMAy interrupt source to check. - * This parameter can be one of the following values: - * @arg DMA1_INT_GL1: DMA1 Channel1 global interrupt. - * @arg DMA1_INT_TC1: DMA1 Channel1 transfer complete interrupt. - * @arg DMA1_INT_HT1: DMA1 Channel1 half transfer interrupt. - * @arg DMA1_INT_TE1: DMA1 Channel1 transfer error interrupt. - * @arg DMA1_INT_GL2: DMA1 Channel2 global interrupt. - * @arg DMA1_INT_TC2: DMA1 Channel2 transfer complete interrupt. - * @arg DMA1_INT_HT2: DMA1 Channel2 half transfer interrupt. - * @arg DMA1_INT_TE2: DMA1 Channel2 transfer error interrupt. - * @arg DMA1_INT_GL3: DMA1 Channel3 global interrupt. - * @arg DMA1_INT_TC3: DMA1 Channel3 transfer complete interrupt. - * @arg DMA1_INT_HT3: DMA1 Channel3 half transfer interrupt. - * @arg DMA1_INT_TE3: DMA1 Channel3 transfer error interrupt. - * @arg DMA1_INT_GL4: DMA1 Channel4 global interrupt. - * @arg DMA1_INT_TC4: DMA1 Channel4 transfer complete interrupt. - * @arg DMA1_INT_HT4: DMA1 Channel4 half transfer interrupt. - * @arg DMA1_INT_TE4: DMA1 Channel4 transfer error interrupt. - * @arg DMA1_INT_GL5: DMA1 Channel5 global interrupt. - * @arg DMA1_INT_TC5: DMA1 Channel5 transfer complete interrupt. - * @arg DMA1_INT_HT5: DMA1 Channel5 half transfer interrupt. - * @arg DMA1_INT_TE5: DMA1 Channel5 transfer error interrupt. - * @arg DMA1_INT_GL6: DMA1 Channel6 global interrupt. - * @arg DMA1_INT_TC6: DMA1 Channel6 transfer complete interrupt. - * @arg DMA1_INT_HT6: DMA1 Channel6 half transfer interrupt. - * @arg DMA1_INT_TE6: DMA1 Channel6 transfer error interrupt. - * @arg DMA1_INT_GL7: DMA1 Channel7 global interrupt. - * @arg DMA1_INT_TC7: DMA1 Channel7 transfer complete interrupt. - * @arg DMA1_INT_HT7: DMA1 Channel7 half transfer interrupt. - * @arg DMA1_INT_TE7: DMA1 Channel7 transfer error interrupt. - * @arg DMA2_INT_GL1: DMA2 Channel1 global interrupt. - * @arg DMA2_INT_TC1: DMA2 Channel1 transfer complete interrupt. - * @arg DMA2_INT_HT1: DMA2 Channel1 half transfer interrupt. - * @arg DMA2_INT_TE1: DMA2 Channel1 transfer error interrupt. - * @arg DMA2_INT_GL2: DMA2 Channel2 global interrupt. - * @arg DMA2_INT_TC2: DMA2 Channel2 transfer complete interrupt. - * @arg DMA2_INT_HT2: DMA2 Channel2 half transfer interrupt. - * @arg DMA2_INT_TE2: DMA2 Channel2 transfer error interrupt. - * @arg DMA2_INT_GL3: DMA2 Channel3 global interrupt. - * @arg DMA2_INT_TC3: DMA2 Channel3 transfer complete interrupt. - * @arg DMA2_INT_HT3: DMA2 Channel3 half transfer interrupt. - * @arg DMA2_INT_TE3: DMA2 Channel3 transfer error interrupt. - * @arg DMA2_INT_GL4: DMA2 Channel4 global interrupt. - * @arg DMA2_INT_TC4: DMA2 Channel4 transfer complete interrupt. - * @arg DMA2_INT_HT4: DMA2 Channel4 half transfer interrupt. - * @arg DMA2_INT_TE4: DMA2 Channel4 transfer error interrupt. - * @arg DMA2_INT_GL5: DMA2 Channel5 global interrupt. - * @arg DMA2_INT_TC5: DMA2 Channel5 transfer complete interrupt. - * @arg DMA2_INT_HT5: DMA2 Channel5 half transfer interrupt. - * @arg DMA2_INT_TE5: DMA2 Channel5 transfer error interrupt. - * @retval The new state of DMAy_IT (SET or RESET). - */ -TypeState DMA_GetIntBitState(uint32_t DMAy_INT) -{ - uint32_t temp = 0; - - /* Calculate the used DMA */ - if ((DMAy_INT & DMA2_FLAG_Mask) != (uint32_t)RESET) { - /* Get DMA2 IFR register value */ - temp = DMA2->IFR; - } else { - /* Get DMA1 IFR register value */ - temp = DMA1->IFR; - } - - /* Check the status of the DMAy interrupt */ - if ((temp & DMAy_INT) != (uint32_t)RESET) { - /* DMA_INT is set */ - return SET; - } else { - /* DMA_INT is reset */ - return RESET; - } -} - -/** - * @brief Clear the DMAy Channelx's interrupt bits. - * @param DMAy_INT: specify the DMAy interrupt pending bit to clear. - * This parameter can be any combination (for the same DMA) of the following values: - * @arg DMA1_INT_GL1: DMA1 Channel1 global interrupt. - * @arg DMA1_INT_TC1: DMA1 Channel1 transfer complete interrupt. - * @arg DMA1_INT_HT1: DMA1 Channel1 half transfer interrupt. - * @arg DMA1_INT_TE1: DMA1 Channel1 transfer error interrupt. - * @arg DMA1_INT_GL2: DMA1 Channel2 global interrupt. - * @arg DMA1_INT_TC2: DMA1 Channel2 transfer complete interrupt. - * @arg DMA1_INT_HT2: DMA1 Channel2 half transfer interrupt. - * @arg DMA1_INT_TE2: DMA1 Channel2 transfer error interrupt. - * @arg DMA1_INT_GL3: DMA1 Channel3 global interrupt. - * @arg DMA1_INT_TC3: DMA1 Channel3 transfer complete interrupt. - * @arg DMA1_INT_HT3: DMA1 Channel3 half transfer interrupt. - * @arg DMA1_INT_TE3: DMA1 Channel3 transfer error interrupt. - * @arg DMA1_INT_GL4: DMA1 Channel4 global interrupt. - * @arg DMA1_INT_TC4: DMA1 Channel4 transfer complete interrupt. - * @arg DMA1_INT_HT4: DMA1 Channel4 half transfer interrupt. - * @arg DMA1_INT_TE4: DMA1 Channel4 transfer error interrupt. - * @arg DMA1_INT_GL5: DMA1 Channel5 global interrupt. - * @arg DMA1_INT_TC5: DMA1 Channel5 transfer complete interrupt. - * @arg DMA1_INT_HT5: DMA1 Channel5 half transfer interrupt. - * @arg DMA1_INT_TE5: DMA1 Channel5 transfer error interrupt. - * @arg DMA1_INT_GL6: DMA1 Channel6 global interrupt. - * @arg DMA1_INT_TC6: DMA1 Channel6 transfer complete interrupt. - * @arg DMA1_INT_HT6: DMA1 Channel6 half transfer interrupt. - * @arg DMA1_INT_TE6: DMA1 Channel6 transfer error interrupt. - * @arg DMA1_INT_GL7: DMA1 Channel7 global interrupt. - * @arg DMA1_INT_TC7: DMA1 Channel7 transfer complete interrupt. - * @arg DMA1_INT_HT7: DMA1 Channel7 half transfer interrupt. - * @arg DMA1_INT_TE7: DMA1 Channel7 transfer error interrupt. - * @arg DMA2_INT_GL1: DMA2 Channel1 global interrupt. - * @arg DMA2_INT_TC1: DMA2 Channel1 transfer complete interrupt. - * @arg DMA2_INT_HT1: DMA2 Channel1 half transfer interrupt. - * @arg DMA2_INT_TE1: DMA2 Channel1 transfer error interrupt. - * @arg DMA2_INT_GL2: DMA2 Channel2 global interrupt. - * @arg DMA2_INT_TC2: DMA2 Channel2 transfer complete interrupt. - * @arg DMA2_INT_HT2: DMA2 Channel2 half transfer interrupt. - * @arg DMA2_INT_TE2: DMA2 Channel2 transfer error interrupt. - * @arg DMA2_INT_GL3: DMA2 Channel3 global interrupt. - * @arg DMA2_INT_TC3: DMA2 Channel3 transfer complete interrupt. - * @arg DMA2_INT_HT3: DMA2 Channel3 half transfer interrupt. - * @arg DMA2_INT_TE3: DMA2 Channel3 transfer error interrupt. - * @arg DMA2_INT_GL4: DMA2 Channel4 global interrupt. - * @arg DMA2_INT_TC4: DMA2 Channel4 transfer complete interrupt. - * @arg DMA2_INT_HT4: DMA2 Channel4 half transfer interrupt. - * @arg DMA2_INT_TE4: DMA2 Channel4 transfer error interrupt. - * @arg DMA2_INT_GL5: DMA2 Channel5 global interrupt. - * @arg DMA2_INT_TC5: DMA2 Channel5 transfer complete interrupt. - * @arg DMA2_INT_HT5: DMA2 Channel5 half transfer interrupt. - * @arg DMA2_INT_TE5: DMA2 Channel5 transfer error interrupt. - * @retval None - */ -void DMA_ClearIntBitState(uint32_t DMAy_INT) -{ - - /* Check the used DMAy */ - if ((DMAy_INT & DMA2_FLAG_Mask) != (uint32_t)RESET) { - /* Clear the DMA2 interrupt bits */ - DMA2->ICR = DMAy_INT; - } else { - /* Clear the DMA1 interrupt bits */ - DMA1->ICR = DMAy_INT; - } -} - -/** - * @} - */ - -/** - * @} - */ - -/** - * @} - */ diff --git a/bsp/gd32103c-eval/Libraries/GD32F1xx_standard_peripheral/Source/gd32f10x_eth.c b/bsp/gd32103c-eval/Libraries/GD32F1xx_standard_peripheral/Source/gd32f10x_eth.c deleted file mode 100644 index fa83328d47..0000000000 --- a/bsp/gd32103c-eval/Libraries/GD32F1xx_standard_peripheral/Source/gd32f10x_eth.c +++ /dev/null @@ -1,2587 +0,0 @@ -/** - ****************************************************************************** - * @brief ETH header file of the firmware library. - ****************************************************************************** - */ -#ifdef GD32F10X_CL -/* Includes ------------------------------------------------------------------*/ -#include "gd32f10x_eth.h" -#include "gd32f10x_rcc.h" - -/** @addtogroup GD32F10x_Firmware - * @{ - */ - -/** @defgroup ETH - * @brief ETH driver modules - * @{ - */ - -/** @defgroup ETH_Private_Defines - * @{ - */ - -/* Global transmit and receive descriptors pointers */ -ETH_DMADESCTypeDef *DMACurrentTxDesc; -ETH_DMADESCTypeDef *DMACurrentRxDesc; -ETH_DMADESCTypeDef *DMACurrentPTPTxDesc; -ETH_DMADESCTypeDef *DMACurrentPTPRxDesc; - -/* ETHERNET MAC address offsets */ -#define ETH_MAC_ADDR_HBASE (ETH_MAC_BASE + 0x40) /* ETHERNET MAC address high offset */ -#define ETH_MAC_ADDR_LBASE (ETH_MAC_BASE + 0x44) /* ETHERNET MAC address low offset */ - -/* ETHERNET MAC_PHYAR register Mask */ -#define MAC_PHYAR_CLR_MASK ((uint32_t)0xFFFFFFE3) - -/* ETHERNET MAC_PHYAR register PHY address shift */ -#define MAC_PHYAR_PHYADDRSHIFT 11 - -/* ETHERNET MAC_PHYAR register PHY register shift */ -#define MAC_PHYAR_PHYREGSHIFT 6 - -/* ETHERNET MAC_CFR register Mask */ -#define MAC_CFR_CLEAR_MASK ((uint32_t)0xFF20810F) - -/* ETHERNET MAC_FCTLR register Mask */ -#define MAC_FCTLR_CLEAR_MASK ((uint32_t)0x0000FF41) - -/* ETHERNET DMA_CTLR register Mask */ -#define DMA_CTLR_CLEAR_MASK ((uint32_t)0xF8DE3F23) - -/* ETHERNET Remote Wake-up frame register length */ -#define ETH_WAKEUP_REGISTER_LENGTH 8 - -/* ETHERNET Missed frames counter Shift */ -#define ETH_DMA_RX_OVERFLOW_MISSEDFRAMES_COUNTERSHIFT 17 - -/* ETHERNET DMA Tx descriptors Collision Count Shift */ -#define ETH_DMATXDESC_COLLISION_COUNTSHIFT 3 - -/* ETHERNET DMA Tx descriptors size */ -#define ETH_DMATXDESC_SIZE 0x10 - -/* ETHERNET DMA Rx descriptors size */ -#define ETH_DMARXDESC_SIZE 0x10 - -/* ETHERNET DMA Tx descriptors Buffer2 Size Shift */ -#define ETH_DMATXDESC_BUFFER2_SIZESHIFT 16 - -/* ETHERNET DMA Rx descriptors Frame Length Shift */ -#define ETH_DMARXDESC_FRAME_LENGTHSHIFT 16 - -/* ETHERNET DMA Rx descriptors Buffer2 Size Shift */ -#define ETH_DMARXDESC_BUFFER2_SIZESHIFT 16 - -/* ETHERNET errors */ -#define ERROR ((uint32_t)0) -#define SUCCESS ((uint32_t)1) -/** - * @} - */ - -/** @defgroup ETH_Private_FunctionPrototypes - * @{ - */ - -#ifndef USE_Delay - static void ETH_Delay(__IO uint32_t nCount); -#endif /* USE_Delay*/ - -/** - * @} - */ - -/** @defgroup ETH_Private_Functions - * @{ - */ - -/** - * @brief Reset the ETH registers. - * @param None - * @retval None - */ -void ETH_DeInit(void) -{ - RCC_AHBPeriphReset_Enable(RCC_AHBPERIPH_ETH_MAC, ENABLE); - RCC_AHBPeriphReset_Enable(RCC_AHBPERIPH_ETH_MAC, DISABLE); -} - -/** - * @brief Initialize MDIO parameters. - * @param None - * @retval None - */ -void ETH_MDIOInit(void) -{ - uint32_t temp = 0; - RCC_ClocksPara rcc_clocks; - uint32_t hclk; - - /* ETHERNET MAC_PHYAR Configuration */ - /* Get the ETH_MAC_PHYAR value */ - temp = ETH_MAC->PHYAR; - /* Clear Clock Range CLR[2:0] bits */ - temp &= MAC_PHYAR_CLR_MASK; - /* Get hclk frequency value */ - RCC_GetClocksFreq(&rcc_clocks); - hclk = rcc_clocks.AHB_Frequency; - /* Set CLR bits depending on hclk value */ - if ((hclk >= 20000000) && (hclk < 35000000)) { - /* Clock Range between 20-35 MHz */ - temp |= (uint32_t)ETH_MAC_PHYAR_CLR_DIV16; - } else if ((hclk >= 35000000) && (hclk < 60000000)) { - /* Clock Range between 35-60 MHz */ - temp |= (uint32_t)ETH_MAC_PHYAR_CLR_DIV26; - } else if ((hclk >= 60000000) && (hclk < 90000000)) { - /* Clock Range between 60-90 MHz */ - temp |= (uint32_t)ETH_MAC_PHYAR_CLR_DIV42; - } - /* ((hclk >= 90000000)&&(hclk <= 108000000)) */ - else { - /* Clock Range between 90-108 MHz */ - temp |= (uint32_t)ETH_MAC_PHYAR_CLR_DIV64; - } - /* Write to ETHERNET MAC PHYAR */ - ETH_MAC->PHYAR = (uint32_t)temp; -} - -/** - * @brief Initial the ETH parameters. - * @param ETH_InitParaStruct: The ETH_InitPara structure pointer. - * @param PHYAddress: external PHY address - * @retval The Initialize result(ERROR or SUCCESS) - */ -uint32_t ETH_Init(ETH_InitPara *ETH_InitParaStruct, uint16_t PHYAddress) -{ - uint32_t RegValue = 0, temp = 0; - __IO uint32_t i = 0; - RCC_ClocksPara rcc_clocks; - uint32_t hclk; - __IO uint32_t timeout = 0; - - /* MAC Config */ - /* ETH_MAC_PHYAR Configuration */ - /* Get the ETH_MAC_PHYAR value */ - temp = ETH_MAC->PHYAR; - /* Clear Clock Range CLR[2:0] bits */ - temp &= MAC_PHYAR_CLR_MASK; - /* Get hclk frequency value */ - RCC_GetClocksFreq(&rcc_clocks); - hclk = rcc_clocks.AHB_Frequency; - /* Set CLR bits depending on hclk value */ - if ((hclk >= 20000000) && (hclk < 35000000)) { - /* Clock Range between 20-35 MHz */ - temp |= (uint32_t)ETH_MAC_PHYAR_CLR_DIV16; - } else if ((hclk >= 35000000) && (hclk < 60000000)) { - /* Clock Range between 35-60 MHz */ - temp |= (uint32_t)ETH_MAC_PHYAR_CLR_DIV26; - } else if ((hclk >= 60000000) && (hclk < 90000000)) { - /* Clock Range between 60-90 MHz */ - temp |= (uint32_t)ETH_MAC_PHYAR_CLR_DIV42; - } - /* ((hclk >= 90000000)&&(hclk <= 108000000)) */ - else { - /* Clock Range between 90-108 MHz */ - temp |= (uint32_t)ETH_MAC_PHYAR_CLR_DIV64; - } - ETH_MAC->PHYAR = (uint32_t)temp; - /* PHY initialization and configuration */ - /* Set the PHY into reset mode */ - if (!(ETH_SetPHYRegisterValue(PHYAddress, PHY_BCR, PHY_RESET))) { - /* Return ERROR due to write timeout */ - return ERROR; - } - - /* PHY reset need some time */ - _eth_delay_(PHY_RESETDELAY); - - if (ETH_InitParaStruct->ETH_MAC_AutoNegotiation != ETH_AUTONEGOTIATION_DISABLE) { - /* Wait for PHY_LINKED_STATUS bit be set */ - do { - timeout++; - } while (!(ETH_GetPHYRegisterValue(PHYAddress, PHY_BSR) & PHY_LINKED_STATUS) && (timeout < PHY_READ_TO)); - /* Return ERROR due to timeout */ - if (timeout == PHY_READ_TO) { - return ERROR; - } - /* Reset Timeout counter */ - timeout = 0; - - /* Enable Auto-Negotiation */ - if (!(ETH_SetPHYRegisterValue(PHYAddress, PHY_BCR, PHY_AUTONEGOTIATION))) { - /* Return ERROR due to write timeout */ - return ERROR; - } - - /* Wait for the PHY_AUTONEGO_COMPLETE bit be set */ - do { - timeout++; - } while (!(ETH_GetPHYRegisterValue(PHYAddress, PHY_BSR) & PHY_AUTONEGO_COMPLETE) && (timeout < (uint32_t)PHY_READ_TO)); - /* Return ERROR due to timeout */ - if (timeout == PHY_READ_TO) { - return ERROR; - } - /* Reset Timeout counter */ - timeout = 0; - - /* Read the result of the autonegotiation */ - RegValue = ETH_GetPHYRegisterValue(PHYAddress, PHY_SR); - - /* Configure the Duplex Mode of MAC following the autonegotiation result */ - if ((RegValue & PHY_DUPLEX_STATUS) != (uint32_t)RESET) { - ETH_InitParaStruct->ETH_MAC_Mode = ETH_MODE_FULLDUPLEX; - - } else { - ETH_InitParaStruct->ETH_MAC_Mode = ETH_MODE_HALFDUPLEX; - } - /* Configure the Communication speed of MAC following the autonegotiation result */ - if (RegValue & PHY_Speed_Status) { - ETH_InitParaStruct->ETH_MAC_Speed = ETH_SPEEDMODE_10M; - } else { - ETH_InitParaStruct->ETH_MAC_Speed = ETH_SPEEDMODE_100M; - } - } else { - if (!ETH_SetPHYRegisterValue(PHYAddress, PHY_BCR, ((uint16_t)(ETH_InitParaStruct->ETH_MAC_Mode >> 3) | - (uint16_t)(ETH_InitParaStruct->ETH_MAC_Speed >> 1)))) { - /* Return ERROR due to write timeout */ - return ERROR; - } - /* PHY configuration need some time */ - _eth_delay_(PHY_CONFIGDELAY); - } - /* ETH_MAC_CFR Configuration */ - /* Get the ETH_MAC_CFR value */ - temp = ETH_MAC->CFR; - temp &= MAC_CFR_CLEAR_MASK; - /* Set the WDD bit according to ETH_MAC_Watchdog value */ - /* Set the JBD: bit according to ETH_MAC_Jabber value */ - /* Set the IG bit according to ETH_MAC_InterFrameGap value */ - /* Set the CSD bit according to ETH_MAC_CarrierSense value */ - /* Set the SPD bit according to ETH_MAC_Speed value */ - /* Set the ROD bit according to ETH_MAC_ReceiveOwn value */ - /* Set the LBM bit according to ETH_MAC_LoopbackMode value */ - /* Set the DPM bit according to ETH_MAC_Mode value */ - /* Set the IP4CO bit according to ETH_MAC_ChecksumOffload value */ - /* Set the RTD bit according to ETH_MAC_RetryTransmission value */ - /* Set the APCD bit according to ETH_MAC_AutomaticPadCRCDrop value */ - /* Set the BOL bit according to ETH_MAC_BackOffLimit value */ - /* Set the DFC bit according to ETH_MAC_DeferralCheck value */ - temp |= (uint32_t)(ETH_InitParaStruct->ETH_MAC_Watchdog | - ETH_InitParaStruct->ETH_MAC_Jabber | - ETH_InitParaStruct->ETH_MAC_InterFrameGap | - ETH_InitParaStruct->ETH_MAC_CarrierSense | - ETH_InitParaStruct->ETH_MAC_Speed | - ETH_InitParaStruct->ETH_MAC_ReceiveOwn | - ETH_InitParaStruct->ETH_MAC_LoopbackMode | - ETH_InitParaStruct->ETH_MAC_Mode | - ETH_InitParaStruct->ETH_MAC_ChecksumOffload | - ETH_InitParaStruct->ETH_MAC_RetryTransmission | - ETH_InitParaStruct->ETH_MAC_AutomaticPadCRCDrop | - ETH_InitParaStruct->ETH_MAC_BackOffLimit | - ETH_InitParaStruct->ETH_MAC_DeferralCheck); - /* Write to ETH_MAC_CFR */ - ETH_MAC->CFR = (uint32_t)temp; - - /* ETH_MAC_FRMFR Configuration */ - /* Set the FD bit according to ETH_MAC_FilterDisable value */ - /* Set the SAFLT and SAIFLT bits according to ETH_MAC_SourceAddrFilter value */ - /* Set the PCFRM bit according to ETH_MAC_PassControlFrames value */ - /* Set the DBF bit according to ETH_MAC_BroadcastFramesReception value */ - /* Set the DAIFLT bit according to ETH_MAC_DestinationAddrFilter value */ - /* Set the PM bit according to ETH_MAC_PromiscuousMode value */ - /* Set the PM, HMF and HPFLT bits according to ETH_MAC_MulticastFramesFilter value */ - /* Set the HUF and HPFLT bits according to ETH_MAC_UnicastFramesFilter value */ - /* Write to ETH_MAC_FRMFR */ - ETH_MAC->FRMFR = (uint32_t)(ETH_InitParaStruct->ETH_MAC_FilterDisable | - ETH_InitParaStruct->ETH_MAC_SourceAddrFilter | - ETH_InitParaStruct->ETH_MAC_PassControlFrames | - ETH_InitParaStruct->ETH_MAC_BroadcastFramesReception | - ETH_InitParaStruct->ETH_MAC_DestinationAddrFilter | - ETH_InitParaStruct->ETH_MAC_PromiscuousMode | - ETH_InitParaStruct->ETH_MAC_MulticastFramesFilter | - ETH_InitParaStruct->ETH_MAC_UnicastFramesFilter); - /* ETH_MAC_HLHR and MAC_HLLR Configuration */ - /* Write to ETHERNET MAC_HLHR */ - ETH_MAC->HLHR = (uint32_t)ETH_InitParaStruct->ETH_MAC_HashListHigh; - /* Write to ETHERNET MAC_HLLR */ - ETH_MAC->HLLR = (uint32_t)ETH_InitParaStruct->ETH_MAC_HashListLow; - /* ETH_MAC_FCTLR Configuration */ - /* Get the ETH_MAC_FCTLR value */ - temp = ETH_MAC->FCTLR; - temp &= MAC_FCTLR_CLEAR_MASK; - - /* Set the PTM bit according to ETH_MAC_PauseTime value */ - /* Set the ZQPD bit according to ETH_MAC_ZeroQuantaPause value */ - /* Set the PLTS bit according to ETH_MAC_PauseLowThreshold value */ - /* Set the UPFDT bit according to ETH_MAC_UnicastPauseFrameDetect value */ - /* Set the RFCEN bit according to ETH_MAC_ReceiveFlowControl value */ - /* Set the TFCEN bit according to ETH_MAC_TransmitFlowControl value */ - temp |= (uint32_t)((ETH_InitParaStruct->ETH_MAC_PauseTime << 16) | - ETH_InitParaStruct->ETH_MAC_ZeroQuantaPause | - ETH_InitParaStruct->ETH_MAC_PauseLowThreshold | - ETH_InitParaStruct->ETH_MAC_UnicastPauseFrameDetect | - ETH_InitParaStruct->ETH_MAC_ReceiveFlowControl | - ETH_InitParaStruct->ETH_MAC_TransmitFlowControl); - /* Write to ETH_MAC_FCTLR */ - ETH_MAC->FCTLR = (uint32_t)temp; - /* ETH_MAC_FCTHR Configuration */ - temp = ETH_MAC->FCTHR; - temp |= (uint32_t)(ETH_InitParaStruct->ETH_MAC_FlowControlDeactiveThreshold | - ETH_InitParaStruct->ETH_MAC_FlowControlActiveThreshold); - ETH_MAC->FCTHR = (uint32_t)temp; - /* ETH_MAC_VLTR Configuration */ - /* Set the VLTC bit according to ETH_MAC_VLANTagComparison value */ - /* Set the VLTI bit according to ETH_MAC_VLANTagIdentifier value */ - ETH_MAC->VLTR = (uint32_t)(ETH_InitParaStruct->ETH_MAC_VLANTagComparison | - ETH_InitParaStruct->ETH_MAC_VLANTagIdentifier); - - /* DMA Config */ - /* ETH_DMA_CTLR Configuration */ - /* Get the ETHERNET DMA_CTLR value */ - temp = ETH_DMA->CTLR; - temp &= DMA_CTLR_CLEAR_MASK; - - /* Set the DTCERFD bit according to ETH_DMA_DropTCPIPChecksumErrorFrame value */ - /* Set the RSFD bit according to ETH_DMA_ReceiveStoreForward value */ - /* Set the DAFRF bit according to ETH_DMA_FlushReceivedFrame value */ - /* Set the TSFD bit according to ETH_DMA_TransmitStoreForward value */ - /* Set the TTCH bit according to ETH_DMA_TransmitThresholdControl value */ - /* Set the FERF bit according to ETH_DMA_ForwardErrorFrames value */ - /* Set the FUF bit according to ETH_DMA_ForwardUndersizedGoodFrames value */ - /* Set the RTHC bit according to ETH_DMA_ReceiveThresholdControl value */ - /* Set the OSF bit according to ETH_DMA_SecondFrameOperate value */ - temp |= (uint32_t)(ETH_InitParaStruct->ETH_DMA_DropTCPIPChecksumErrorFrame | - ETH_InitParaStruct->ETH_DMA_ReceiveStoreForward | - ETH_InitParaStruct->ETH_DMA_FlushReceivedFrame | - ETH_InitParaStruct->ETH_DMA_TransmitStoreForward | - ETH_InitParaStruct->ETH_DMA_TransmitThresholdControl | - ETH_InitParaStruct->ETH_DMA_ForwardErrorFrames | - ETH_InitParaStruct->ETH_DMA_ForwardUndersizedGoodFrames | - ETH_InitParaStruct->ETH_DMA_ReceiveThresholdControl | - ETH_InitParaStruct->ETH_DMA_SecondFrameOperate); - /* Write to ETH_DMA_CTLR */ - ETH_DMA->CTLR = (uint32_t)temp; - - /* ETH_DMA_BCR Configuration */ - /* Set the AA bit according to ETH_DMA_AddressAligned value */ - /* Set the FB bit according to ETH_DMA_FixedBurst value */ - /* Set the RXDP and 4*PBL bits according to ETH_DMA_RxDMABurstLength value */ - /* Set the FPBL and 4*PBL bits according to ETH_DMA_TxDMABurstLength value */ - /* Set the DPSL bit according to ETH_DesciptorSkipLength value */ - /* Set the RTPR and DAB bits according to ETH_DMA_Arbitration value */ - ETH_DMA->BCR = (uint32_t)(ETH_InitParaStruct->ETH_DMA_AddressAligned | - ETH_InitParaStruct->ETH_DMA_FixedBurst | - ETH_InitParaStruct->ETH_DMA_RxDMABurstLength | /* If 4xPBL is selected for Tx or Rx it is applied for the other */ - ETH_InitParaStruct->ETH_DMA_TxDMABurstLength | - (ETH_InitParaStruct->ETH_DMA_DescriptorSkipLength << 2) | - ETH_InitParaStruct->ETH_DMA_Arbitration | - ETH_DMA_BCR_UIP); /* Enable use of separate PBL for Rx and Tx */ - /* Return Ethernet configuration success */ - return SUCCESS; -} - -/** - * @brief Initial the sturct ETH_InitPara. - * @param ETH_InitParaStruct: pointer to a ETH_InitPara structure. - * @retval None - */ -void ETH_ParaInit(ETH_InitPara *ETH_InitParaStruct) -{ - /* Reset ETH init structure parameters values */ - /* MAC */ - ETH_InitParaStruct->ETH_MAC_AutoNegotiation = ETH_AUTONEGOTIATION_DISABLE; - ETH_InitParaStruct->ETH_MAC_Watchdog = ETH_WATCHDOG_ENABLE; - ETH_InitParaStruct->ETH_MAC_Jabber = ETH_JABBER_ENABLE; - ETH_InitParaStruct->ETH_MAC_InterFrameGap = ETH_INTERFRAMEGAP_96BIT; - ETH_InitParaStruct->ETH_MAC_CarrierSense = ETH_CARRIERSENSE_ENABLE; - ETH_InitParaStruct->ETH_MAC_Speed = ETH_SPEEDMODE_10M; - ETH_InitParaStruct->ETH_MAC_ReceiveOwn = ETH_RECEIVEOWN_ENABLE; - ETH_InitParaStruct->ETH_MAC_LoopbackMode = ETH_LOOPBACKMODE_DISABLE; - ETH_InitParaStruct->ETH_MAC_Mode = ETH_MODE_HALFDUPLEX; - ETH_InitParaStruct->ETH_MAC_ChecksumOffload = ETH_CHECKSUMOFFLOAD_DISABLE; - ETH_InitParaStruct->ETH_MAC_RetryTransmission = ETH_RETRYTRANSMISSION_ENABLE; - ETH_InitParaStruct->ETH_MAC_AutomaticPadCRCDrop = ETH_AUTOMATICPADCRCDROP_DISABLE; - ETH_InitParaStruct->ETH_MAC_BackOffLimit = ETH_BACKOFFLIMIT_10; - ETH_InitParaStruct->ETH_MAC_DeferralCheck = ETH_DEFERRALCHECK_DISABLE; - ETH_InitParaStruct->ETH_MAC_FilterDisable = ETH_FILTERDISABLE_DISABLE; - ETH_InitParaStruct->ETH_MAC_SourceAddrFilter = ETH_SOURCEADDRFILTER_DISABLE; - ETH_InitParaStruct->ETH_MAC_PassControlFrames = ETH_PASSCONTROLFRAMES_BLOCKALL; - ETH_InitParaStruct->ETH_MAC_BroadcastFramesReception = ETH_BROADCASTFRAMESRECEPTION_DISABLE; - ETH_InitParaStruct->ETH_MAC_DestinationAddrFilter = ETH_DESTINATIONADDRFILTER_NORMAL; - ETH_InitParaStruct->ETH_MAC_PromiscuousMode = ETH_PROMISCUOUSMODE_DISABLE; - ETH_InitParaStruct->ETH_MAC_MulticastFramesFilter = ETH_MULTICASTFRAMESFILTER_PERFECT; - ETH_InitParaStruct->ETH_MAC_UnicastFramesFilter = ETH_UNICASTFRAMESFILTER_PERFECT; - ETH_InitParaStruct->ETH_MAC_HashListHigh = 0x0; - ETH_InitParaStruct->ETH_MAC_HashListLow = 0x0; - ETH_InitParaStruct->ETH_MAC_PauseTime = 0x0; - ETH_InitParaStruct->ETH_MAC_ZeroQuantaPause = ETH_ZEROQUANTAPAUSE_DISABLE; - ETH_InitParaStruct->ETH_MAC_PauseLowThreshold = ETH_PAUSELOWTHRESHOLD_MINUS4; - ETH_InitParaStruct->ETH_MAC_FlowControlDeactiveThreshold = ETH_RFD_512BYTES; - ETH_InitParaStruct->ETH_MAC_FlowControlActiveThreshold = ETH_RFA_1536BYTES; - ETH_InitParaStruct->ETH_MAC_UnicastPauseFrameDetect = ETH_UNICASTPAUSEFRAMEDETECT_DISABLE; - ETH_InitParaStruct->ETH_MAC_ReceiveFlowControl = ETH_RECEIVEFLOWCONTROL_DISABLE; - ETH_InitParaStruct->ETH_MAC_TransmitFlowControl = ETH_TRANSMITFLOWCONTROL_DISABLE; - ETH_InitParaStruct->ETH_MAC_VLANTagComparison = ETH_VLANTAGCOMPARISON_16BIT; - ETH_InitParaStruct->ETH_MAC_VLANTagIdentifier = 0x0; - /* DMA */ - ETH_InitParaStruct->ETH_DMA_DropTCPIPChecksumErrorFrame = ETH_DROPTCPIPCHECKSUMERRORFRAME_DISABLE; - ETH_InitParaStruct->ETH_DMA_ReceiveStoreForward = ETH_RECEIVESTOREFORWARD_ENABLE; - ETH_InitParaStruct->ETH_DMA_FlushReceivedFrame = ETH_FLUSHRECEIVEDFRAME_DISABLE; - ETH_InitParaStruct->ETH_DMA_TransmitStoreForward = ETH_TRANSMITSTOREFORWARD_ENABLE; - ETH_InitParaStruct->ETH_DMA_TransmitThresholdControl = ETH_TRANSMITTHRESHOLDCONTROL_64BYTES; - ETH_InitParaStruct->ETH_DMA_ForwardErrorFrames = ETH_FORWARDERRORFRAMES_DISABLE; - ETH_InitParaStruct->ETH_DMA_ForwardUndersizedGoodFrames = ETH_FORWARDUNDERSIZEDGOODFRAMES_DISABLE; - ETH_InitParaStruct->ETH_DMA_ReceiveThresholdControl = ETH_RECEIVETHRESHOLDCONTROL_64BYTES; - ETH_InitParaStruct->ETH_DMA_SecondFrameOperate = ETH_SECONDFRAMEOPERATE_DISABLE; - ETH_InitParaStruct->ETH_DMA_AddressAligned = ETH_ADDRESSALIGNED_ENABLE; - ETH_InitParaStruct->ETH_DMA_FixedBurst = ETH_FIXEDBURST_DISABLE; - ETH_InitParaStruct->ETH_DMA_RxDMABurstLength = ETH_RXDMABURSTLENGTH_1BEAT; - ETH_InitParaStruct->ETH_DMA_TxDMABurstLength = ETH_TXDMABURSTLENGTH_1BEAT; - ETH_InitParaStruct->ETH_DMA_DescriptorSkipLength = 0x0; - ETH_InitParaStruct->ETH_DMA_Arbitration = ETH_DMAARBITRATION_ROUNDROBIN_RXTX_1_1; -} - -/** - * @brief Enable or disable the ETH's receive and transmit. - * @param NewValue: ENABLE or DISABLE. - * @retval None - */ -void ETH_Enable(TypeState NewValue) -{ - /* Enable or Disable the ETH module */ - if (NewValue != DISABLE) { - /* Enable MAC transmit */ - ETH_MACTransmission_Enable(ENABLE); - /* Flush ETHERNET DMA Transmit FIFO */ - ETH_CleanTransmitFIFO(); - /* Enable MAC receive */ - ETH_MACReception_Enable(ENABLE); - - /* Enable DMA transmission */ - ETH_DMATransmission_Enable(ENABLE); - /* Enable DMA reception */ - ETH_DMAReception_Enable(ENABLE); - } else { - /* Disable MAC transmit */ - ETH_MACTransmission_Enable(DISABLE); - /* Flush ETHERNET DMA Transmit FIFO */ - ETH_CleanTransmitFIFO(); - /* Disable MAC receive */ - ETH_MACReception_Enable(DISABLE); - - /* Disable DMA transmission */ - ETH_DMATransmission_Enable(DISABLE); - /* Disable DMA reception */ - ETH_DMAReception_Enable(DISABLE); - } -} - -/** - * @brief Send data of application buffer as a transmit packet. - * @param pbuf: Pointer to the application buffer. - * @param size: the application buffer size. - * @retval The transmission result(ERROR or SUCCESS) - */ -uint32_t ETH_HandleTxPkt(uint8_t *pbuf, uint16_t size) -{ - uint32_t offset = 0; - - /* Check the busy bit of Tx descriptor status */ - if ((DMACurrentTxDesc->Status & ETH_DMATXDESC_BUSY) != (uint32_t)RESET) { - /* Return ERROR: the descriptor is busy due to own by the DMA */ - return ERROR; - } - - for (offset = 0; offset < size; offset++) { - (*(__IO uint8_t *)((DMACurrentTxDesc->Buffer1Addr) + offset)) = (*(pbuf + offset)); - } - - /* Setting the Frame Length */ - DMACurrentTxDesc->ControlBufferSize = (size & ETH_DMATXDESC_TB1S); - /* Setting the segment of frame (ETH_DMATXDESC_LSG and ETH_DMATXDESC_FSG are SET that frame is transmitted in one descriptor) */ - DMACurrentTxDesc->Status |= ETH_DMATXDESC_LSG | ETH_DMATXDESC_FSG; - /* Enable the DMA transmission */ - DMACurrentTxDesc->Status |= ETH_DMATXDESC_BUSY; - /* Check Tx Buffer unavailable flag status */ - if ((ETH_DMA->STR & ETH_DMA_STR_TBU) != (uint32_t)RESET) { - /* Clear TBU ETHERNET DMA flag */ - ETH_DMA->STR = ETH_DMA_STR_TBU; - /* Resume DMA transmission by writing to the TPER register*/ - ETH_DMA->TPER = 0; - } - - /* Update the ETHERNET DMA current Tx descriptor pointer to the next Tx decriptor in DMA Tx decriptor talbe*/ - /* Chained Mode */ - if ((DMACurrentTxDesc->Status & ETH_DMATXDESC_TCHM) != (uint32_t)RESET) { - DMACurrentTxDesc = (ETH_DMADESCTypeDef *)(DMACurrentTxDesc->Buffer2NextDescAddr); - } - /* Ring Mode */ - else { - if ((DMACurrentTxDesc->Status & ETH_DMATXDESC_TERM) != (uint32_t)RESET) { - DMACurrentTxDesc = (ETH_DMADESCTypeDef *)(ETH_DMA->TDTAR); - } else { - DMACurrentTxDesc = (ETH_DMADESCTypeDef *)((uint32_t)DMACurrentTxDesc + ETH_DMATXDESC_SIZE + ((ETH_DMA->BCR & ETH_DMA_BCR_DPSL) >> 2)); - } - } - /* Return SUCCESS */ - return SUCCESS; -} - -/** - * @brief Receive a packet data to application buffer. - * @param pbuf: Pointer on the application buffer. - * @retval The Receive size(If framelength is equal to ERROR, the receiving unsuccessful) - */ -uint32_t ETH_HandleRxPkt(uint8_t *pbuf) -{ - uint32_t offset = 0, size = 0; - - /* Check the busy bit of Rx descriptor status */ - if ((DMACurrentRxDesc->Status & ETH_DMARXDESC_BUSY) != (uint32_t)RESET) { - /* Return ERROR: the descriptor is busy due to own by the DMA */ - return ERROR; - } - - if (((DMACurrentRxDesc->Status & ETH_DMARXDESC_ERRS) == (uint32_t)RESET) && - ((DMACurrentRxDesc->Status & ETH_DMARXDESC_LDES) != (uint32_t)RESET) && - ((DMACurrentRxDesc->Status & ETH_DMARXDESC_FDES) != (uint32_t)RESET)) { - /* Get the Frame Length exclusive CRC */ - size = ((DMACurrentRxDesc->Status & ETH_DMARXDESC_FRML) >> ETH_DMARXDESC_FRAME_LENGTHSHIFT) - 4; - for (offset = 0; offset < size; offset++) { - (*(pbuf + offset)) = (*(__IO uint8_t *)((DMACurrentRxDesc->Buffer1Addr) + offset)); - } - } else { - /* Return ERROR */ - size = ERROR; - } - /* Enable reception */ - DMACurrentRxDesc->Status = ETH_DMARXDESC_BUSY; - - /* Check Rx Buffer unavailable flag status */ - if ((ETH_DMA->STR & ETH_DMA_STR_RBU) != (uint32_t)RESET) { - /* Clear RBU ETHERNET DMA flag */ - ETH_DMA->STR = ETH_DMA_STR_RBU; - /* Resume DMA reception by writing to the RPER register*/ - ETH_DMA->RPER = 0; - } - - /* Update the ETHERNET DMA current Rx descriptor pointer to the next Rx decriptor in DMA Rx decriptor talbe*/ - /* Chained Mode */ - if ((DMACurrentRxDesc->ControlBufferSize & ETH_DMARXDESC_RCHM) != (uint32_t)RESET) { - DMACurrentRxDesc = (ETH_DMADESCTypeDef *)(DMACurrentRxDesc->Buffer2NextDescAddr); - } - /* Ring Mode */ - else { - if ((DMACurrentRxDesc->ControlBufferSize & ETH_DMARXDESC_RERR) != (uint32_t)RESET) { - DMACurrentRxDesc = (ETH_DMADESCTypeDef *)(ETH_DMA->RDTAR); - } else { - DMACurrentRxDesc = (ETH_DMADESCTypeDef *)((uint32_t)DMACurrentRxDesc + ETH_DMARXDESC_SIZE + ((ETH_DMA->BCR & ETH_DMA_BCR_DPSL) >> 2)); - } - } - - /* Return Frame size or ERROR */ - return (size); -} - -/** - * @brief To obtain the received data length - * @param None - * @retval Received frame length. - */ -uint32_t ETH_GetRxPktSize(void) -{ - uint32_t size = 0; - - if ((DMACurrentRxDesc->Status & ETH_DMARXDESC_BUSY) != (uint32_t)RESET) { - return 0; - } - - if (((DMACurrentRxDesc->Status & ETH_DMARXDESC_ERRS) != (uint32_t)RESET) || - ((DMACurrentRxDesc->Status & ETH_DMARXDESC_LDES) == (uint32_t)RESET) || - ((DMACurrentRxDesc->Status & ETH_DMARXDESC_FDES) == (uint32_t)RESET)) { - ETH_DropRxPkt(); - - return 0; - } - - if (((DMACurrentRxDesc->Status & ETH_DMARXDESC_BUSY) == (uint32_t)RESET) && - ((DMACurrentRxDesc->Status & ETH_DMARXDESC_ERRS) == (uint32_t)RESET) && - ((DMACurrentRxDesc->Status & ETH_DMARXDESC_LDES) != (uint32_t)RESET) && - ((DMACurrentRxDesc->Status & ETH_DMARXDESC_FDES) != (uint32_t)RESET)) { - /* Get the size of the received data including CRC */ - size = ETH_GetDMARxDescFrameLength(DMACurrentRxDesc); - } - - /* Return Packet size */ - return size; -} - -/** - * @brief Discard a Received packet - * @param None - * @retval None - */ -void ETH_DropRxPkt(void) -{ - /* Enable reception */ - DMACurrentRxDesc->Status = ETH_DMARXDESC_BUSY; - /* Chained Mode */ - if ((DMACurrentRxDesc->ControlBufferSize & ETH_DMARXDESC_RCHM) != (uint32_t)RESET) { - DMACurrentRxDesc = (ETH_DMADESCTypeDef *)(DMACurrentRxDesc->Buffer2NextDescAddr); - } - /* Ring Mode */ - else { - if ((DMACurrentRxDesc->ControlBufferSize & ETH_DMARXDESC_RERM) != (uint32_t)RESET) { - DMACurrentRxDesc = (ETH_DMADESCTypeDef *)(ETH_DMA->RDTAR); - } else { - DMACurrentRxDesc = (ETH_DMADESCTypeDef *)((uint32_t)DMACurrentRxDesc + ETH_DMARXDESC_SIZE + ((ETH_DMA->BCR & ETH_DMA_BCR_DPSL) >> 2)); - } - } -} - -/* PHY */ -/** - * @brief Get PHY of ETHERNET parameters. - * @param PHYAddr: PHY device address, devices number max is 32. - * @param PHYReg: PHY register address, register address max is 32. - * Select one of the follwing values : - * @arg PHY_BCR: Tranceiver Basic Control Register - * @arg PHY_BSR: Tranceiver Basic Status Register - * @arg PHY_SR : Tranceiver Status Register - * @arg More PHY register could be read depending on the used PHY - * @retval value read from the selected PHY register (if timeout return ERROR) - */ -uint16_t ETH_GetPHYRegisterValue(uint16_t PHYAddr, uint16_t PHYReg) -{ - uint32_t temp = 0; - __IO uint32_t timeout = 0; - - /* Get the ETHERNET MAC_PHYAR value */ - temp = ETH_MAC->PHYAR; - temp &= ~MAC_PHYAR_CLR_MASK; - /* Configuration the PHY address register value */ - /* Set the PHY device address */ - temp |= (((uint32_t)PHYAddr << MAC_PHYAR_PHYADDRSHIFT) & ETH_MAC_PHYAR_PA); - /* Set the PHY register address */ - temp |= (((uint32_t)PHYReg << MAC_PHYAR_PHYREGSHIFT) & ETH_MAC_PHYAR_PR); - /* Set the read mode */ - temp &= ~ETH_MAC_PHYAR_PW; - /* Set the PHY Busy bit */ - temp |= ETH_MAC_PHYAR_PB; - ETH_MAC->PHYAR = temp; - /* Check the PHY Busy flag status */ - do { - timeout++; - temp = ETH_MAC->PHYAR; - } while ((temp & ETH_MAC_PHYAR_PB) && (timeout < (uint32_t)PHY_READ_TO)); - /* Return ERROR due to timeout */ - if (timeout == PHY_READ_TO) { - return (uint16_t)ERROR; - } - - /* Return PHY register selected value */ - return (uint16_t)(ETH_MAC->PHYDR); -} - -/** - * @brief Set PHY of ETHERNET parameters. - * @param PHYAddr: PHY device address, devices number max is 32. - * @param PHYReg: PHY register address, register address max is 32. - * Select one of the follwing values : - * @arg PHY_BCR : Tranceiver Control Register - * @arg More PHY register could be written depending on the used PHY - * @param PHYValue: write to register value - * @retval The Write to the selected PHY register result(ERROR or SUCCESS) - */ -uint32_t ETH_SetPHYRegisterValue(uint16_t PHYAddr, uint16_t PHYReg, uint16_t PHYValue) -{ - uint32_t temp = 0; - __IO uint32_t timeout = 0; - - /* Get the ETHERNET MAC_PHYAR value */ - temp = ETH_MAC->PHYAR; - temp &= ~MAC_PHYAR_CLR_MASK; - /* Configuration the PHY register address value */ - /* Set the PHY device address */ - temp |= (((uint32_t)PHYAddr << MAC_PHYAR_PHYADDRSHIFT) & ETH_MAC_PHYAR_PA); - /* Set the PHY register address */ - temp |= (((uint32_t)PHYReg << MAC_PHYAR_PHYREGSHIFT) & ETH_MAC_PHYAR_PR); - /* Set the write mode */ - temp |= ETH_MAC_PHYAR_PW; - /* Set the PHY Busy bit */ - temp |= ETH_MAC_PHYAR_PB; - /* Set the PHY selected register value */ - ETH_MAC->PHYDR = PHYValue; - ETH_MAC->PHYAR = temp; - /* Check the PHY Busy flag status */ - do { - timeout++; - temp = ETH_MAC->PHYAR; - } while ((temp & ETH_MAC_PHYAR_PB) && (timeout < (uint32_t)PHY_WRITE_TO)); - /* Return ERROR due to timeout */ - if (timeout == PHY_WRITE_TO) { - return ERROR; - } - - return SUCCESS; -} - -/** - * @brief Enable or disable the PHY loopBack function by write PHY register. - * @param PHYAddr: PHY device address, devices number max is 32. - * @param NewValue: new value of the PHY loopBack mode. - * This parameter can be: ENABLE or DISABLE. - * @retval The Set PHYLoopBack mode result(ERROR or SUCCESS) - */ -uint32_t ETH_PHYLoopBack_Enable(uint16_t PHYAddr, TypeState NewValue) -{ - uint16_t temp = 0; - - /* Get the PHY BCR register value */ - temp = ETH_GetPHYRegisterValue(PHYAddr, PHY_BCR); - - if (NewValue != DISABLE) { - /* Enable the PHY loopback mode */ - temp |= PHY_LOOPBACK; - } else { - /* Disable the PHY loopback mode (change to normal mode) */ - temp &= (uint16_t)(~(uint16_t)PHY_LOOPBACK); - } - /* Set the PHY BCR register with the new value */ - if (ETH_SetPHYRegisterValue(PHYAddr, PHY_BCR, temp) != (uint32_t)RESET) { - return SUCCESS; - } else { - return ERROR; - } -} - -/* MAC */ -/** - * @brief Enable or disable the MAC transmit function. - * @param NewValue: new value of the MAC transmit function. - * This parameter can be: ENABLE or DISABLE. - * @retval None - */ -void ETH_MACTransmission_Enable(TypeState NewValue) -{ - if (NewValue != DISABLE) { - /* Enable the MAC transmission */ - ETH_MAC->CFR |= ETH_MAC_CFR_TEN; - } else { - /* Disable the MAC transmission */ - ETH_MAC->CFR &= ~ETH_MAC_CFR_TEN; - } -} - -/** - * @brief Enable or disable the MAC receive function. - * @param NewValue: new value of the MAC reception. - * This parameter can be: ENABLE or DISABLE. - * @retval None - */ -void ETH_MACReception_Enable(TypeState NewValue) -{ - if (NewValue != DISABLE) { - /* Enable the MAC reception */ - ETH_MAC->CFR |= ETH_MAC_CFR_REN; - } else { - /* Disable the MAC reception */ - ETH_MAC->CFR &= ~ETH_MAC_CFR_REN; - } -} - -/** - * @brief Get the bit flag of the ETHERNET flow control busy status. - * @param None - * @retval current flow control busy bit status - */ -TypeState ETH_GetFlowControlBusyBitState(void) -{ - /* Check the flow control busy bit status */ - if ((ETH_MAC->FCTLR & ETH_MAC_FCTLR_FLCBBKPA) != (uint32_t)RESET) { - return SET; - } else { - return RESET; - } -} - -/** - * @brief Initiate a Pause Frame in Full-duplex mode only. - * @param None - * @retval None - */ -void ETH_PauseFrameInit(void) -{ - /* Initiate pause control frame in full duplex mode*/ - ETH_MAC->FCTLR |= ETH_MAC_FCTLR_FLCBBKPA; -} - -/** - * @brief Enable or disable the BackPressure requests in Half-duplex only. - * @param NewValue: new value of the BackPressure operation requests. - * This parameter can be: ENABLE or DISABLE. - * @retval None - */ -void ETH_BackPressureActivation_Enable(TypeState NewValue) -{ - if (NewValue != DISABLE) { - /* Enable the BackPressure requests */ - ETH_MAC->FCTLR |= ETH_MAC_FCTLR_FLCBBKPA; - } else { - /* Disable the BackPressure requests */ - ETH_MAC->FCTLR &= ~ETH_MAC_FCTLR_FLCBBKPA; - } -} - -/** - * @brief Get the status flag of ETH_MAC_ISR register. - * @param ETH_MAC_FLAG: the status flag of ETH_MAC_ISR register. - * Select one of the follwing values : - * @arg ETH_MAC_FLAG_TST : Time stamp trigger flag - * @arg ETH_MAC_FLAG_MSCT : MSC transmit flag - * @arg ETH_MAC_FLAG_MSCR : MSC receive flag - * @arg ETH_MAC_FLAG_MSC : MSC flag - * @arg ETH_MAC_FLAG_WUM : WUM flag - * @retval The current MAC bit selected status(SET or RESET). - */ -TypeState ETH_GetMACBitState(uint32_t ETH_MAC_FLAG) -{ - /* Check the ETH_MAC_FLAG status */ - if ((ETH_MAC->ISR & ETH_MAC_FLAG) != (uint32_t)RESET) { - return SET; - } else { - return RESET; - } -} - -/** - * @brief Get the interrupt flag of ETH_MAC_ISR register. - * @param ETH_MAC_INT: the interrupt flag of ETH_MAC_ISR register. - * Select one of the follwing values : - * @arg ETH_MAC_INT_TST : Time stamp trigger interrupt - * @arg ETH_MAC_INT_MSCT : MSC transmit interrupt - * @arg ETH_MAC_INT_MSCR : MSC receive interrupt - * @arg ETH_MAC_INT_MSC : MSC interrupt - * @arg ETH_MAC_INT_WUM : WUM interrupt - * @retval The current MAC interrupt bit selected status(SET or RESET). - */ -TypeState ETH_GetMACIntBitState(uint32_t ETH_MAC_INT) -{ - /* Check the ETH_MAC_INT status */ - if ((ETH_MAC->ISR & ETH_MAC_INT) != (uint32_t)RESET) { - return SET; - } else { - return RESET; - } -} - -/** - * @brief Enable or disable the ETH_MAC_INT control bit. - * @param ETH_MAC_INT: the interrupt bit flag. - * Select one of the follwing values : - * @arg ETH_MAC_INT_TST : Time stamp trigger interrupt - * @arg ETH_MAC_INT_WUM : WUM interrupt - * @param NewValue: new value of the ETH_MAC_INT value. - * This parameter can be: ENABLE or DISABLE. - * @retval None - */ -void ETH_MACINTConfig(uint32_t ETH_MAC_INT, TypeState NewValue) -{ - if (NewValue != DISABLE) { - /* Enable the MAC interrupt */ - ETH_MAC->IMR &= (~(uint32_t)ETH_MAC_INT); - } else { - /* Disable the MAC interrupt */ - ETH_MAC->IMR |= ETH_MAC_INT; - } -} - -/** - * @brief Set the MAC address to MAC address register selected. - * @param addr: The MAC address register to selected. - * Select one of the follwing values : - * @arg ETH_MAC_ADDRESS0 : MAC Address0 - * @arg ETH_MAC_ADDRESS1 : MAC Address1 - * @arg ETH_MAC_ADDRESS2 : MAC Address2 - * @arg ETH_MAC_ADDRESS3 : MAC Address3 - * @param buf: Pointer to application MAC address buffer(6 bytes). - * @retval None - */ -void ETH_SetMACAddress(uint32_t addr, uint8_t *buf) -{ - uint32_t temp; - - temp = ((uint32_t)buf[5] << 8) | (uint32_t)buf[4]; - /* Set the selectecd MAC address high register */ - (*(__IO uint32_t *)(ETH_MAC_ADDR_HBASE + addr)) = temp; - temp = ((uint32_t)buf[3] << 24) | ((uint32_t)buf[2] << 16) | ((uint32_t)buf[1] << 8) | buf[0]; - - /* Set the selectecd MAC address low register */ - (*(__IO uint32_t *)(ETH_MAC_ADDR_LBASE + addr)) = temp; -} - -/** - * @brief Get the MAC address from MAC address register selected. - * @param addr: The MAC addres to selected. - * Select one of the follwing values : - * @arg ETH_MAC_ADDRESS0 : MAC Address0 - * @arg ETH_MAC_ADDRESS1 : MAC Address1 - * @arg ETH_MAC_ADDRESS2 : MAC Address2 - * @arg ETH_MAC_ADDRESS3 : MAC Address3 - * @param buf: Pointer to application MAC address buffer(6 bytes). - * @retval None - */ -void ETH_GetMACAddress(uint32_t addr, uint8_t *buf) -{ - uint32_t temp; - - /* Get the selectecd MAC address high register */ - temp = (*(__IO uint32_t *)(ETH_MAC_ADDR_HBASE + addr)); - - buf[5] = ((temp >> 8) & (uint8_t)0xFF); - buf[4] = (temp & (uint8_t)0xFF); - /* Get the selectecd MAC address low register */ - temp = (*(__IO uint32_t *)(ETH_MAC_ADDR_LBASE + addr)); - buf[3] = ((temp >> 24) & (uint8_t)0xFF); - buf[2] = ((temp >> 16) & (uint8_t)0xFF); - buf[1] = ((temp >> 8) & (uint8_t)0xFF); - buf[0] = (temp & (uint8_t)0xFF); -} - -/** - * @brief Enable or disable the Address perfect filtering. - * @param addr: the MAC address register selected for prfect filtering. - * Select one of the follwing values : - * @arg ETH_MAC_ADDRESS1 : MAC Address1 - * @arg ETH_MAC_ADDRESS2 : MAC Address2 - * @arg ETH_MAC_ADDRESS3 : MAC Address3 - * @param NewValue: new value of the MAC address register selected for perfect filtering. - * This parameter can be: ENABLE or DISABLE. - * @retval None - */ -void ETH_MACAddressPerfectFilter_Enable(uint32_t addr, TypeState NewValue) -{ - if (NewValue != DISABLE) { - /* Enable the perfect filtering to the MAC address register selected */ - (*(__IO uint32_t *)(ETH_MAC_ADDR_HBASE + addr)) |= ETH_MAC_A1HR_AFE; - } else { - /* Disable the perfect filtering to the MAC address register selected */ - (*(__IO uint32_t *)(ETH_MAC_ADDR_HBASE + addr)) &= (~(uint32_t)ETH_MAC_A1HR_AFE); - } -} - -/** - * @brief Set the selected MAC address filter type mode. - * @param addr: the MAC address to be used for filtering. - * Select one of the follwing values : - * @arg ETH_MAC_ADDRESS1 : MAC Address1 - * @arg ETH_MAC_ADDRESS2 : MAC Address2 - * @arg ETH_MAC_ADDRESS3 : MAC Address3 - * @param Filterfield: the mode of receiving field for comparaison - * Select one of the follwing values : - * @arg ETH_MAC_ADDRESSFILTER_SA : Compare with the SA fields of the received frame. - * @arg ETH_MAC_ADDRESSFILTER_DA : Compare with the DA fields of the received frame. - * @retval None - */ -void ETH_MACAddressFilterConfig(uint32_t addr, uint32_t Filterfield) -{ - if (Filterfield != ETH_MAC_ADDRESSFILTER_DA) { - /* Compare with the SA fields of the received frame. */ - (*(__IO uint32_t *)(ETH_MAC_ADDR_HBASE + addr)) |= ETH_MAC_A1HR_SAF; - } else { - /* compare with the DA fields of the received frame. */ - (*(__IO uint32_t *)(ETH_MAC_ADDR_HBASE + addr)) &= (~(uint32_t)ETH_MAC_A1HR_SAF); - } -} - -/** - * @brief Set the selected MAC address filter maskbyte. - * @param addr: the MAC address to be used for filtering - * Select one of the follwing values : - * @arg ETH_MAC_ADDRESS1 : MAC Address1 - * @arg ETH_MAC_ADDRESS2 : MAC Address2 - * @arg ETH_MAC_ADDRESS3 : MAC Address3 - * @param addrmask: the address bytes be selected for address filtering comparaison - * Select one of the follwing values : - * @arg ETH_MAC_ADDRESSMASK_BYTE6 : Mask MAC Address high register bits [15:8]. - * @arg ETH_MAC_ADDRESSMASK_BYTE5 : Mask MAC Address high register bits [7:0]. - * @arg ETH_MAC_ADDRESSMASK_BYTE4 : Mask MAC Address low register bits [31:24]. - * @arg ETH_MAC_ADDRESSMASK_BYTE3 : Mask MAC Address low register bits [23:16]. - * @arg ETH_MAC_ADDRESSMASK_BYTE2 : Mask MAC Address low register bits [15:8]. - * @arg ETH_MAC_ADDRESSMASK_BYTE1 : Mask MAC Address low register bits [7:0]. - * @retval None - */ -void ETH_MACAddressFilterMaskBytesConfig(uint32_t addr, uint32_t addrmask) -{ - /* Clear the MB bit of selected MAC address */ - (*(__IO uint32_t *)(ETH_MAC_ADDR_HBASE + addr)) &= (~(uint32_t)ETH_MAC_A1HR_MB); - /* Set the mask bytes of selected Filetr */ - (*(__IO uint32_t *)(ETH_MAC_ADDR_HBASE + addr)) |= addrmask; -} - -/* DMA Tx/Rx Desciptors */ - -/** - * @brief Initialize the DMA Tx descriptors's parameters in chain mode. - * @param DMATxDescTab: Pointer to the first Tx descriptor table - * @param pTxBuff: Pointer to the first TxBuffer table - * @param TxBuffCnt: the used Tx desc num in the table - * @retval None - */ -void ETH_DMATxDescChainModeInit(ETH_DMADESCTypeDef *DMATxDescTab, uint8_t *pTxBuff, uint32_t TxBuffCnt) -{ - uint32_t num = 0; - ETH_DMADESCTypeDef *DMATxDesc; - - DMACurrentTxDesc = DMATxDescTab; - /* Configuration each DMATxDesc descriptor */ - for (num = 0; num < TxBuffCnt; num++) { - /* Get the pointer to the next descriptor of the Tx Desc table */ - DMATxDesc = DMATxDescTab + num; - /* Set TCH bit with desc status */ - DMATxDesc->Status = ETH_DMATXDESC_TCHM; - - /* Set Buffer1 address pointer to application buffer */ - DMATxDesc->Buffer1Addr = (uint32_t)(&pTxBuff[num * ETH_MAX_FRAME_SIZE]); - - if (num < (TxBuffCnt - 1)) { - /* Buffer2NextDescAddr equal to next descriptor address in the Tx Desc table */ - DMATxDesc->Buffer2NextDescAddr = (uint32_t)(DMATxDescTab + num + 1); - } else { - /* When it is the last descriptor, Buffer2NextDescAddr equal to first descriptor address in the Tx Desc table */ - DMATxDesc->Buffer2NextDescAddr = (uint32_t) DMATxDescTab; - } - } - ETH_DMA->TDTAR = (uint32_t) DMATxDescTab; -} - -/** - * @brief Initialize the DMA Tx descriptors's parameters in ring mode. - * @param DMATxDescTab: Pointer to the first Tx descriptor table - * @param pTxBuff1: Pointer to the first TxBuffer1 table - * @param pTxBuff2: Pointer to the first TxBuffer2 table - * @param TxBuffCnt: the used Tx desc num in the table - * @retval None - */ -void ETH_DMATxDescRingModeInit(ETH_DMADESCTypeDef *DMATxDescTab, uint8_t *pTxBuff1, uint8_t *pTxBuff2, uint32_t TxBuffCnt) -{ - uint32_t num = 0; - ETH_DMADESCTypeDef *DMATxDesc; - - DMACurrentTxDesc = DMATxDescTab; - /* Configuration each DMATxDesc descriptor */ - for (num = 0; num < TxBuffCnt; num++) { - /* Get the pointer to the next descriptor of the Tx Desc table */ - DMATxDesc = DMATxDescTab + num; - /* Set Buffer1 address pointer to application buffer1 */ - DMATxDesc->Buffer1Addr = (uint32_t)(&pTxBuff1[num * ETH_MAX_FRAME_SIZE]); - - /* Set Buffer2 address pointer to application buffer2 */ - DMATxDesc->Buffer2NextDescAddr = (uint32_t)(&pTxBuff2[num * ETH_MAX_FRAME_SIZE]); - - if (num == (TxBuffCnt - 1)) { - /* Set ETH_DMATXDESC_TERM bit as transmitting End */ - DMATxDesc->Status = ETH_DMATXDESC_TERM; - } - } - ETH_DMA->TDTAR = (uint32_t) DMATxDescTab; -} - -/** - * @brief Get the bit flag of ETHERNET DMA Tx Desc. - * @param DMATxDesc: pointer to a DMA Tx descriptor - * @param ETH_DMATxDescFlag: the flag of Tx descriptor status. - * Select one of the follwing values : - * @arg ETH_DMATXDESC_BUSY : BUSY bit: descriptor is owned by DMA engine - * @arg ETH_DMATXDESC_INTC : Interrupt on completetion - * @arg ETH_DMATXDESC_LSG : Last Segment - * @arg ETH_DMATXDESC_FSG : First Segment - * @arg ETH_DMATXDESC_DCRC : Disable CRC - * @arg ETH_DMATXDESC_DPAD : Disable Pad - * @arg ETH_DMATXDESC_TTSEN : Transmit Time Stamp Enable - * @arg ETH_DMATXDESC_TERM : Transmit End of Ring - * @arg ETH_DMATXDESC_TCHM : Second Address Chained - * @arg ETH_DMATXDESC_TTMSS : Tx Time Stamp Status - * @arg ETH_DMATXDESC_IPHE : IP Header Error - * @arg ETH_DMATXDESC_ES : Error summary - * @arg ETH_DMATXDESC_JT : Jabber Timeout - * @arg ETH_DMATXDESC_FRMF : Frame Flushed: DMA/MTL flushed the frame due to SW flush - * @arg ETH_DMATXDESC_IPPE : IP Payload Error - * @arg ETH_DMATXDESC_LCA : Loss of Carrier: carrier lost during tramsmission - * @arg ETH_DMATXDESC_NCA : No Carrier: no carrier signal from the tranceiver - * @arg ETH_DMATXDESC_LCO : Late Collision: transmission aborted due to collision - * @arg ETH_DMATXDESC_ECO : Excessive Collision: transmission aborted after 16 collisions - * @arg ETH_DMATXDESC_VFRM : VLAN Frame - * @arg ETH_DMATXDESC_COCNT : Collision Count - * @arg ETH_DMATXDESC_EXD : Excessive Deferral - * @arg ETH_DMATXDESC_UFE : Underflow Error: late data arrival from the memory - * @arg ETH_DMATXDESC_DB : Deferred Bit - * @retval The current ETH_DMATxDescFlag selected bit status(SET or RESET). - */ -TypeState ETH_GetDMATxDescBitState(ETH_DMADESCTypeDef *DMATxDesc, uint32_t ETH_DMATxDescFlag) -{ - if ((DMATxDesc->Status & ETH_DMATxDescFlag) != (uint32_t)RESET) { - /* ETH_DMATxDescFlag is set */ - return SET; - } else { - /* ETH_DMATxDescFlag is reset */ - return RESET; - } -} - -/** - * @brief Get the DMA Tx Desc collision count. - * @param DMATxDesc: pointer to a DMA Tx descriptor - * @retval The value of Transmit descriptor collision counter. - */ -uint32_t ETH_GetDMATxDescCollisionCount(ETH_DMADESCTypeDef *DMATxDesc) -{ - return ((DMATxDesc->Status & ETH_DMATXDESC_COCNT) >> ETH_DMATXDESC_COLLISION_COUNTSHIFT); -} - -/** - * @brief Set the DMA Tx Desc Busy bit for DMA or CPU. - * @param DMATxDesc: Pointer on a Transmit descriptor - * @retval None - */ -void ETH_SetDMATxDescBusyBit(ETH_DMADESCTypeDef *DMATxDesc) -{ - DMATxDesc->Status |= ETH_DMATXDESC_BUSY; -} - -/** - * @brief Enable or disable the ETH_DMATXDESC_INTC control bit. - * @param DMATxDesc: Pointer to a Tx descriptor - * @param NewValue: new value of the ETH_DMATXDESC_INTC control bit. - * This parameter can be: ENABLE or DISABLE. - * @retval None - */ -void ETH_DMATxDescTransmitINTConfig(ETH_DMADESCTypeDef *DMATxDesc, TypeState NewValue) -{ - if (NewValue != DISABLE) { - /* Enable the DMA Tx Desc after the frame has been transmitted Set Transmit interrupt */ - DMATxDesc->Status |= ETH_DMATXDESC_INTC; - } else { - /* Disable the DMA Tx Desc after the frame has been transmitted Set Transmit interrupt */ - DMATxDesc->Status &= (~(uint32_t)ETH_DMATXDESC_INTC); - } -} - -/** - * @brief Enable or disable the DMATxDesc_FrameSegment control bit. - * @param DMATxDesc: Pointer to a Tx descriptor - * @param DMATxDesc_Segment: the actual Tx buffer contain first or last segment. - * Select one of the follwing values : - * @arg ETH_DMATXDESC_LASTSEGMENT : current Tx desc selected contain last segment - * @arg ETH_DMATXDESC_FIRSTSEGMENT : current Tx desc selected contain first segment - * @retval None - */ -void ETH_SetDMATxDescFrameSegment(ETH_DMADESCTypeDef *DMATxDesc, uint32_t DMATxDesc_Segment) -{ - DMATxDesc->Status |= DMATxDesc_Segment; -} - -/** - * @brief Set the DMA Tx Desc Checksum Insertion mode. - * @param DMATxDesc: pointer to a DMA Tx descriptor - * @param DMATxDesc_Checksum: the type of DMA Tx descriptor checksum insertion. - * Select one of the follwing values : - * @arg ETH_DMATXDESC_CHECKSUMDISABLE : Checksum bypass - * @arg ETH_DMATXDESC_CHECKSUMIPV4HEADER : IPv4 header checksum - * @arg ETH_DMATXDESC_CHECKSUMTCPUDPICMPSEGMENT : TCP/UDP/ICMP checksum. Pseudo header checksum is assumed to be present - * @arg ETH_DMATXDESC_CHECKSUMTCPUDPICMPFULL : TCP/UDP/ICMP checksum fully in hardware including pseudo header - * @retval None - */ -void ETH_SetDMATxDescChecksumInsertion(ETH_DMADESCTypeDef *DMATxDesc, uint32_t DMATxDesc_Checksum) -{ - DMATxDesc->Status |= DMATxDesc_Checksum; -} - -/** - * @brief Enable or disable the DMA Tx descriptor CRC function. - * @param DMATxDesc: pointer to a DMA Tx descriptor - * @param NewValue: new value of the DMA Tx descriptor CRC function. - * This parameter can be: ENABLE or DISABLE. - * @retval None - */ -void ETH_DMATxDescCRC_Enable(ETH_DMADESCTypeDef *DMATxDesc, TypeState NewValue) -{ - if (NewValue != DISABLE) { - /* Enable the DMATxDesc CRC */ - DMATxDesc->Status &= (~(uint32_t)ETH_DMATXDESC_DCRC); - } else { - /* Disable the DMATxDesc CRC */ - DMATxDesc->Status |= ETH_DMATXDESC_DCRC; - } -} - -/** - * @brief Enable or disable the DMA Tx descriptor end of ring. - * @param DMATxDesc: pointer to a DMA Tx descriptor - * @param NewValue: new value of the DMA Tx descriptor end of ring. - * This parameter can be: ENABLE or DISABLE. - * @retval None - */ -void ETH_DMATxDescEndOfRing_Enable(ETH_DMADESCTypeDef *DMATxDesc, TypeState NewValue) -{ - if (NewValue != DISABLE) { - /* Enable the DMATxDesc end of ring */ - DMATxDesc->Status |= ETH_DMATXDESC_TERM; - } else { - /* Disable the DMATxDesc end of ring */ - DMATxDesc->Status &= (~(uint32_t)ETH_DMATXDESC_TERM); - } -} - -/** - * @brief Enable or disable the DMA Tx descriptor second address chained. - * @param DMATxDesc: pointer to a DMA Tx descriptor - * @param NewValue: new value of the DMA Tx descriptor second address chained. - * This parameter can be: ENABLE or DISABLE. - * @retval None - */ -void ETH_DMATxDescSecondAddressChained_Enable(ETH_DMADESCTypeDef *DMATxDesc, TypeState NewValue) -{ - if (NewValue != DISABLE) { - /* Enable the DMATxDesc second address chained */ - DMATxDesc->Status |= ETH_DMATXDESC_TCHM; - } else { - /* Disable the DMATxDesc second address chained */ - DMATxDesc->Status &= (~(uint32_t)ETH_DMATXDESC_TCHM); - } -} - -/** - * @brief Enable or disable auto padding when transmit frame shorter than 64 bytes. - * @param DMATxDesc: pointer to a DMA Tx descriptor - * @param NewValue: new value of the auto padding status. - * This parameter can be: ENABLE or DISABLE. - * @retval None - */ -void ETH_DMATxDescShortFramePadding_Enable(ETH_DMADESCTypeDef *DMATxDesc, TypeState NewValue) -{ - if (NewValue != DISABLE) { - /* Enable the DMATxDesc short frame padding */ - DMATxDesc->Status &= (~(uint32_t)ETH_DMATXDESC_DPAD); - } else { - /* Disable the DMATxDesc short frame padding */ - DMATxDesc->Status |= ETH_DMATXDESC_DPAD; - } -} - -/** - * @brief Enable or disable the DMA Tx descriptor time stamp function. - * @param DMATxDesc: pointer to a DMA Tx descriptor - * @param NewValue: new value of the DMA Tx descriptor time stamp. - * This parameter can be: ENABLE or DISABLE. - * @retval None - */ -void ETH_DMATxDescTimeStamp_Enable(ETH_DMADESCTypeDef *DMATxDesc, TypeState NewValue) -{ - if (NewValue != DISABLE) { - /* Enable the DMATxDesc time stamp */ - DMATxDesc->Status |= ETH_DMATXDESC_TTSEN; - } else { - /* Disable the DMATxDesc time stamp */ - DMATxDesc->Status &= (~(uint32_t)ETH_DMATXDESC_TTSEN); - } -} - -/** - * @brief Set the frame length by configures the DMA Tx Desc buffer1 and buffer2 sizes. - * @param DMATxDesc: Pointer to a Tx descriptor - * @param Buffer1Size: the Tx buffer1 size. - * @param Buffer2Size: the Tx buffer2 size, set to 0 indicates it is not being used. - * @retval None - */ -void ETH_SetDMATxDescBufferSize(ETH_DMADESCTypeDef *DMATxDesc, uint32_t Buffer1Size, uint32_t Buffer2Size) -{ - DMATxDesc->ControlBufferSize |= (Buffer1Size | (Buffer2Size << ETH_DMATXDESC_BUFFER2_SIZESHIFT)); -} - -/** - * @brief Initialize the DMA Rx descriptors's parameters in chain mode. - * @param DMARxDescTab: Pointer to the first Rx descriptor table - * @param pRxBuff: Pointer to the first RxBuffer table - * @param RxBuffCnt: the used Rx desc num in the table - * @retval None - */ -void ETH_DMARxDescChainModeInit(ETH_DMADESCTypeDef *DMARxDescTab, uint8_t *pRxBuff, uint32_t RxBuffCnt) -{ - uint32_t num = 0; - ETH_DMADESCTypeDef *DMARxDesc; - - DMACurrentRxDesc = DMARxDescTab; - /* Configuration each DMARxDesc descriptor */ - for (num = 0; num < RxBuffCnt; num++) { - /* Get the pointer to the next descriptor of the Rx Desc table */ - DMARxDesc = DMARxDescTab + num; - DMARxDesc->Status = ETH_DMARXDESC_BUSY; - - /* Set TCH bit and buffer1 size */ - DMARxDesc->ControlBufferSize = ETH_DMARXDESC_RCHM | (uint32_t)ETH_MAX_FRAME_SIZE; - /* Set Buffer1 address pointer to application buffer */ - DMARxDesc->Buffer1Addr = (uint32_t)(&pRxBuff[num * ETH_MAX_FRAME_SIZE]); - - if (num < (RxBuffCnt - 1)) { - /* Buffer2NextDescAddr equal to next descriptor address in the Rx Desc table */ - DMARxDesc->Buffer2NextDescAddr = (uint32_t)(DMARxDescTab + num + 1); - } else { - /* When it is the last descriptor, Buffer2NextDescAddr equal to first descriptor address in the Rx Desc table */ - DMARxDesc->Buffer2NextDescAddr = (uint32_t)(DMARxDescTab); - } - } - - ETH_DMA->RDTAR = (uint32_t) DMARxDescTab; -} - -/** - * @brief Initialize the DMA Rx descriptors's parameters in ring mode. - * @param DMARxDescTab: Pointer to the first Rx descriptor table - * @param pRxBuff1: Pointer to the first RxBuffer1 table - * @param pRxBuff2: Pointer to the first RxBuffer2 table - * @param RxBuffCnt: the used Rx descriptor num in the table - * @retval None - */ -void ETH_DMARxDescRingModeInit(ETH_DMADESCTypeDef *DMARxDescTab, uint8_t *pRxBuff1, uint8_t *pRxBuff2, uint32_t RxBuffCnt) -{ - uint32_t num = 0; - ETH_DMADESCTypeDef *DMARxDesc; - - DMACurrentRxDesc = DMARxDescTab; - /* Configuration each DMARxDesc descriptor */ - for (num = 0; num < RxBuffCnt; num++) { - /* Get the pointer to the next descriptor of the Rx Desc table */ - DMARxDesc = DMARxDescTab + num; - DMARxDesc->Status = ETH_DMARXDESC_BUSY; - DMARxDesc->ControlBufferSize = ETH_MAX_FRAME_SIZE; - /* Set Buffer1 address pointer to application buffer1 */ - DMARxDesc->Buffer1Addr = (uint32_t)(&pRxBuff1[num * ETH_MAX_FRAME_SIZE]); - - /* Set Buffer2 address pointer to application buffer2 */ - DMARxDesc->Buffer2NextDescAddr = (uint32_t)(&pRxBuff2[num * ETH_MAX_FRAME_SIZE]); - - if (num == (RxBuffCnt - 1)) { - /* Set ETH_DMARXDESC_RERR bit as Receive End */ - DMARxDesc->ControlBufferSize |= ETH_DMARXDESC_RERR; - } - } - - ETH_DMA->RDTAR = (uint32_t) DMARxDescTab; -} - -/** - * @brief Get the bit flag of ETHERNET Rx descriptor. - * @param DMARxDesc: pointer to a DMA Rx descriptor - * @param ETH_DMARxDescFlag: the flag of Rx descriptor status. - * Select one of the follwing values : - * @arg ETH_DMARXDESC_BUSY : Descriptor is owned by DMA engine - * @arg ETH_DMARXDESC_DAFF : DA Filter Fail for the rx frame - * @arg ETH_DMARXDESC_ERRS : Error summary - * @arg ETH_DMARXDESC_DERR : Desciptor error: no more descriptors for receive frame - * @arg ETH_DMARXDESC_SAFF : SA Filter Fail for the received frame - * @arg ETH_DMARXDESC_LERR : Frame size not matching with length field - * @arg ETH_DMARXDESC_OERR : Overflow Error: Frame was damaged due to buffer overflow - * @arg ETH_DMARXDESC_VTAG : VLAN Tag: received frame is a VLAN frame - * @arg ETH_DMARXDESC_FDES : First descriptor of the frame - * @arg ETH_DMARXDESC_LDES : Last descriptor of the frame - * @arg ETH_DMARXDESC_IPHCERR : IPC Checksum Error/Giant Frame: Rx Ipv4 header checksum error - * @arg ETH_DMARXDESC_LCO : Late collision occurred during reception - * @arg ETH_DMARXDESC_FRMT : Frame type - Ethernet, otherwise 802.3 - * @arg ETH_DMARXDESC_RWDT : Receive Watchdog Timeout: watchdog timer expired during reception - * @arg ETH_DMARXDESC_RERR : Receive error: error reported by MII interface - * @arg ETH_DMARXDESC_DERR : Dribble bit error: frame contains non int multiple of 8 bits - * @arg ETH_DMARXDESC_CERR : CRC error - * @arg ETH_DMARXDESC_PCERR : Rx MAC Address/Payload Checksum Error: Rx MAC address matched/ Rx Payload Checksum Error - * @retval The current ETH_DMARxDescFlag selected bit status(SET or RESET). - */ -TypeState ETH_GetDMARxDescBitState(ETH_DMADESCTypeDef *DMARxDesc, uint32_t ETH_DMARxDescFlag) -{ - if ((DMARxDesc->Status & ETH_DMARxDescFlag) != (uint32_t)RESET) { - /* ETH_DMARxDescFlag is set */ - return SET; - } else { - /* ETH_DMARxDescFlag is reset */ - return RESET; - } -} - -/** - * @brief Set the DMA Rx Desc busy bit for DMA or CPU - * @param DMARxDesc: Pointer to a Rx descriptor - * @retval None - */ -void ETH_SetDMARxDescBusyBit(ETH_DMADESCTypeDef *DMARxDesc) -{ - DMARxDesc->Status |= ETH_DMARXDESC_BUSY; -} - -/** - * @brief Get the DMA Rx Desc frame length. - * @param DMARxDesc: pointer to a DMA Rx descriptor - * @retval Received frame length of the Rx descriptor selected. - */ -uint32_t ETH_GetDMARxDescFrameLength(ETH_DMADESCTypeDef *DMARxDesc) -{ - return ((DMARxDesc->Status & ETH_DMARXDESC_FRML) >> ETH_DMARXDESC_FRAME_LENGTHSHIFT); -} - -/** - * @brief Enable or disable the DMA Rx descriptor receive interrupt. - * @param DMARxDesc: Pointer to a Rx descriptor - * @param NewValue: new value of the DMA Rx descriptor interrupt. - * This parameter can be: ENABLE or DISABLE. - * @retval None - */ -void ETH_DMARxDescReceiveINTConfig(ETH_DMADESCTypeDef *DMARxDesc, TypeState NewValue) -{ - if (NewValue != DISABLE) { - /* Enable the DMARxDesc receive interrupt */ - DMARxDesc->ControlBufferSize &= (~(uint32_t)ETH_DMARXDESC_DINTC); - } else { - /* Disable the DMARxDesc receive interrupt */ - DMARxDesc->ControlBufferSize |= ETH_DMARXDESC_DINTC; - } -} - -/** - * @brief Enable or disable the DMA Rx descriptor end of ring. - * @param DMARxDesc: pointer to a DMA Rx descriptor - * @param NewValue: new value of the DMA Rx descriptor end of ring. - * This parameter can be: ENABLE or DISABLE. - * @retval None - */ -void ETH_DMARxDescEndOfRing_Enable(ETH_DMADESCTypeDef *DMARxDesc, TypeState NewValue) -{ - if (NewValue != DISABLE) { - /* Enable the DMARxDesc end of ring */ - DMARxDesc->ControlBufferSize |= ETH_DMARXDESC_RERR; - } else { - /* Disable the DMARxDesc end of ring */ - DMARxDesc->ControlBufferSize &= (~(uint32_t)ETH_DMARXDESC_RERR); - } -} - -/** - * @brief Enable or disable the DMA Rx descriptor second address chained. - * @param DMARxDesc: pointer to a DMA Rx descriptor - * @param NewValue: new value of the DMA Rx descriptor second address chained. - * This parameter can be: ENABLE or DISABLE. - * @retval None - */ -void ETH_DMARxDescSecondAddressChained_Enable(ETH_DMADESCTypeDef *DMARxDesc, TypeState NewValue) -{ - if (NewValue != DISABLE) { - /* Enable the DMARxDesc second address chained */ - DMARxDesc->ControlBufferSize |= ETH_DMARXDESC_RCHM; - } else { - /* Disable the DMARxDesc second address chained */ - DMARxDesc->ControlBufferSize &= (~(uint32_t)ETH_DMARXDESC_RCHM); - } -} - -/** - * @brief Get the ETHERNET DMA Rx Desc buffer size. - * @param DMARxDesc: pointer to a DMA Rx descriptor - * @param DMARxDesc_BufferSelect: the DMA Rx descriptor buffer. - * Select one of the follwing values : - * @arg ETH_DMARXDESC_BUFFER1 : DMA Rx Desc Buffer1 - * @arg ETH_DMARXDESC_BUFFER2 : DMA Rx Desc Buffer2 - * @retval The Receive descriptor selected buffer size(buffer1 or buffer2). - */ -uint32_t ETH_GetDMARxDescBufferSize(ETH_DMADESCTypeDef *DMARxDesc, uint32_t DMARxDesc_BufferSelect) -{ - if (DMARxDesc_BufferSelect != ETH_DMARXDESC_BUFFER1) { - return ((DMARxDesc->ControlBufferSize & ETH_DMARXDESC_RB2S) >> ETH_DMARXDESC_BUFFER2_SIZESHIFT); - } else { - return (DMARxDesc->ControlBufferSize & ETH_DMARXDESC_RB1S); - } -} - -/* DMA */ -/** - * @brief Resets all MAC subsystem. - * @param None - * @retval None - */ -void ETH_SoftReset(void) -{ - ETH_DMA->BCR |= ETH_DMA_BCR_SWR; -} - -/** - * @brief Get the bit flag of ETHERNET software reset. - * @param None - * @retval The current DMA Bus Mode register SWR bit status(SET or RESET). - */ -TypeState ETH_GetSoftResetStatus(void) -{ - if ((ETH_DMA->BCR & ETH_DMA_BCR_SWR) != (uint32_t)RESET) { - /* The ETH_DMA_BCR_SWR bit is set */ - return SET; - } else { - /* The ETH_DMA_BCR_SWR bit is reset */ - return RESET; - } -} - -/** - * @brief Get the bit flag of specified ETHERNET DMA. - * @param ETH_DMA_FLAG: the flag of ETHERNET DMA_STR register. - * Select one of the follwing values : - * @arg ETH_DMA_FLAG_TST : Time-stamp trigger flag - * @arg ETH_DMA_FLAG_WUM : WUM flag - * @arg ETH_DMA_FLAG_MSC : MSC flag - * @arg ETH_DMA_FLAG_DATATRANSFERERROR : Error bits 0-data buffer, 1-desc. access - * @arg ETH_DMA_FLAG_READWRITEERROR : Error bits 0-write trnsf, 1-read transfr - * @arg ETH_DMA_FLAG_ACCESSERROR : Error bits 0-Rx DMA, 1-Tx DMA - * @arg ETH_DMA_FLAG_NIS : Normal interrupt summary flag - * @arg ETH_DMA_FLAG_AIS : Abnormal interrupt summary flag - * @arg ETH_DMA_FLAG_ER : Early receive flag - * @arg ETH_DMA_FLAG_FBE : Fatal bus error flag - * @arg ETH_DMA_FLAG_ET : Early transmit flag - * @arg ETH_DMA_FLAG_RWT : Receive watchdog timeout flag - * @arg ETH_DMA_FLAG_RPS : Receive process stopped flag - * @arg ETH_DMA_FLAG_RBU : Receive buffer unavailable flag - * @arg ETH_DMA_FLAG_R : Receive flag - * @arg ETH_DMA_FLAG_TU : Underflow flag - * @arg ETH_DMA_FLAG_RO : Overflow flag - * @arg ETH_DMA_FLAG_TJT : Transmit jabber timeout flag - * @arg ETH_DMA_FLAG_TBU : Transmit buffer unavailable flag - * @arg ETH_DMA_FLAG_TPS : Transmit process stopped flag - * @arg ETH_DMA_FLAG_T : Transmit flag - * @retval The current ETH_DMA_FLAG selected bit status(SET or RESET). - */ -TypeState ETH_GetDMABitState(uint32_t ETH_DMA_FLAG) -{ - if ((ETH_DMA->STR & ETH_DMA_FLAG) != (uint32_t)RESET) { - /* ETH_DMA_FLAG is set */ - return SET; - } else { - /* ETH_DMA_FLAG is reset */ - return RESET; - } -} - -/** - * @brief Clear the ETHERNET��s DMA bit flag. - * @param ETH_DMA_FLAG: the flag of ETH_DMA_STR register to clear. - * Select one of the follwing values : - * @arg ETH_DMA_FLAG_NIS : Normal interrupt summary flag - * @arg ETH_DMA_FLAG_AIS : Abnormal interrupt summary flag - * @arg ETH_DMA_FLAG_ER : Early receive flag - * @arg ETH_DMA_FLAG_FBE : Fatal bus error flag - * @arg ETH_DMA_FLAG_ETI : Early transmit flag - * @arg ETH_DMA_FLAG_RWT : Receive watchdog timeout flag - * @arg ETH_DMA_FLAG_RPS : Receive process stopped flag - * @arg ETH_DMA_FLAG_RBU : Receive buffer unavailable flag - * @arg ETH_DMA_FLAG_R : Receive flag - * @arg ETH_DMA_FLAG_TU : Transmit Underflow flag - * @arg ETH_DMA_FLAG_RO : Receive Overflow flag - * @arg ETH_DMA_FLAG_TJT : Transmit jabber timeout flag - * @arg ETH_DMA_FLAG_TBU : Transmit buffer unavailable flag - * @arg ETH_DMA_FLAG_TPS : Transmit process stopped flag - * @arg ETH_DMA_FLAG_T : Transmit flag - * @retval None - */ -void ETH_DMAClearBitState(uint32_t ETH_DMA_FLAG) -{ - ETH_DMA->STR = (uint32_t) ETH_DMA_FLAG; -} - -/** - * @brief Get the bit flag of DMA interrupt. - * @param ETH_DMA_INT: the interrupt source flag of ETHERNET DMA_STR register. - * Select one of the follwing values : - * @arg ETH_DMA_INT_TST : Time-stamp trigger interrupt - * @arg ETH_DMA_INT_WUM : WUM interrupt - * @arg ETH_DMA_INT_MSC : MSC interrupt - * @arg ETH_DMA_INT_NIS : Normal interrupt summary - * @arg ETH_DMA_INT_AIS : Abnormal interrupt summary - * @arg ETH_DMA_INT_ER : Early receive interrupt - * @arg ETH_DMA_INT_FBE : Fatal bus error interrupt - * @arg ETH_DMA_INT_ET : Early transmit interrupt - * @arg ETH_DMA_INT_RWT : Receive watchdog timeout interrupt - * @arg ETH_DMA_INT_RPS : Receive process stopped interrupt - * @arg ETH_DMA_INT_RBU : Receive buffer unavailable interrupt - * @arg ETH_DMA_INT_R : Receive interrupt - * @arg ETH_DMA_INT_TU : Underflow interrupt - * @arg ETH_DMA_INT_RO : Overflow interrupt - * @arg ETH_DMA_INT_TJT : Transmit jabber timeout interrupt - * @arg ETH_DMA_INT_TBU : Transmit buffer unavailable interrupt - * @arg ETH_DMA_INT_TPS : Transmit process stopped interrupt - * @arg ETH_DMA_INT_T : Transmit interrupt - * @retval The current ETH_DMA_INT selected bit status(SET or RESET). - */ -TypeState ETH_GetDMAIntBitState(uint32_t ETH_DMA_INT) -{ - if ((ETH_DMA->STR & ETH_DMA_INT) != (uint32_t)RESET) { - /* ETH_DMA_INT is set */ - return SET; - } else { - /* ETH_DMA_INT is reset */ - return RESET; - } -} - -/** - * @brief Clear the ETHERNET��s DMA IT bit flag. - * @param ETH_DMA_INT: the interrupt source flag of ETH_DMA_STR register to clear. - * Select one of the follwing values : - * @arg ETH_DMA_INT_NIS : Normal interrupt summary - * @arg ETH_DMA_INT_AIS : Abnormal interrupt summary - * @arg ETH_DMA_INT_ER : Early receive interrupt - * @arg ETH_DMA_INT_FBE : Fatal bus error interrupt - * @arg ETH_DMA_INT_ETI : Early transmit interrupt - * @arg ETH_DMA_INT_RWT : Receive watchdog timeout interrupt - * @arg ETH_DMA_INT_RPS : Receive process stopped interrupt - * @arg ETH_DMA_INT_RBU : Receive buffer unavailable interrupt - * @arg ETH_DMA_INT_R : Receive interrupt - * @arg ETH_DMA_INT_TU : Transmit Underflow interrupt - * @arg ETH_DMA_INT_RO : Receive Overflow interrupt - * @arg ETH_DMA_INT_TJT : Transmit jabber timeout interrupt - * @arg ETH_DMA_INT_TBU : Transmit buffer unavailable interrupt - * @arg ETH_DMA_INT_TPS : Transmit process stopped interrupt - * @arg ETH_DMA_INT_T : Transmit interrupt - * @retval None - */ -void ETH_DMAClearIntBitState(uint32_t ETH_DMA_INT) -{ - ETH_DMA->STR = (uint32_t) ETH_DMA_INT; -} - -/** - * @brief Get the DMA Transmit Process State. - * @param None - * @retval The current DMA Transmit Process State: - * Select one of the follwing values : - * - ETH_DMA_TransmitProcess_Stopped : Stopped - Reset or Stop Tx Command issued - * - ETH_DMA_TransmitProcess_Fetching : Running - fetching the Tx descriptor - * - ETH_DMA_TransmitProcess_Waiting : Running - waiting for status - * - ETH_DMA_TransmitProcess_Reading : unning - reading the data from host memory - * - ETH_DMA_TransmitProcess_Suspended : Suspended - Tx Desciptor unavailabe - * - ETH_DMA_TransmitProcess_Closing : Running - closing Rx descriptor - */ -uint32_t ETH_GetTransmitProcessState(void) -{ - return ((uint32_t)(ETH_DMA->STR & ETH_DMA_STR_TS)); -} - -/** - * @brief Get the DMA Receive Process State. - * @param None - * @retval The current DMA Receive Process State: - * Select one of the follwing values : - * - ETH_DMA_ReceiveProcess_Stopped : Stopped - Reset or Stop Rx Command issued - * - ETH_DMA_ReceiveProcess_Fetching : Running - fetching the Rx descriptor - * - ETH_DMA_ReceiveProcess_Waiting : Running - waiting for packet - * - ETH_DMA_ReceiveProcess_Suspended : Suspended - Rx Desciptor unavailable - * - ETH_DMA_ReceiveProcess_Closing : Running - closing descriptor - * - ETH_DMA_ReceiveProcess_Queuing : Running - queuing the recieve frame into host memory - */ -uint32_t ETH_GetReceiveProcessState(void) -{ - return ((uint32_t)(ETH_DMA->STR & ETH_DMA_STR_RS)); -} - -/** - * @brief Flush the ETHERNET transmit FIFO. - * @param None - * @retval None - */ -void ETH_CleanTransmitFIFO(void) -{ - /* Set the FTF bit for Flushing Transmit FIFO */ - ETH_DMA->CTLR |= ETH_DMA_CTLR_FTF; -} - -/** - * @brief Get the bit flag of ETHERNET transmit FIFO. - * @param None - * @retval The current ETHERNET flush transmit FIFO bit status(SET or RESET). - */ -TypeState ETH_GetFlushTransmitFIFOStatus(void) -{ - if ((ETH_DMA->CTLR & ETH_DMA_CTLR_FTF) != (uint32_t)RESET) { - /* Flush transmit FIFO bit is set */ - return SET; - } else { - /* Flush transmit FIFO bit is reset */ - return RESET; - } -} - -/** - * @brief Enable or disable the DMA transmission function. - * @param NewValue: new value of the DMA transmission status. - * This parameter can be: ENABLE or DISABLE. - * @retval None - */ -void ETH_DMATransmission_Enable(TypeState NewValue) -{ - if (NewValue != DISABLE) { - /* Set the STE bit for Enable the DMA transmission */ - ETH_DMA->CTLR |= ETH_DMA_CTLR_STE; - } else { - /* Reset the STE bit for Disable the DMA transmission */ - ETH_DMA->CTLR &= ~ETH_DMA_CTLR_STE; - } -} - -/** - * @brief Enable or disable the DMA reception function. - * @param NewValue: new value of the DMA reception status. - * This parameter can be: ENABLE or DISABLE. - * @retval None - */ -void ETH_DMAReception_Enable(TypeState NewValue) -{ - if (NewValue != DISABLE) { - /* Enable DMA reception */ - ETH_DMA->CTLR |= ETH_DMA_CTLR_SRE; - } else { - /* Disable DMA reception */ - ETH_DMA->CTLR &= ~ETH_DMA_CTLR_SRE; - } -} - -/** - * @brief Enable or disable the ETH_DMA_INT control bit. - * @param ETH_DMA_INT: the interrupt source flag of ETH_DMA_IER register. - * Select one of the follwing values : - * @arg ETH_DMA_INT_NIS : Normal interrupt summary - * @arg ETH_DMA_INT_AIS : Abnormal interrupt summary - * @arg ETH_DMA_INT_ER : Early receive interrupt - * @arg ETH_DMA_INT_FBE : Fatal bus error interrupt - * @arg ETH_DMA_INT_ET : Early transmit interrupt - * @arg ETH_DMA_INT_RWT : Receive watchdog timeout interrupt - * @arg ETH_DMA_INT_RPS : Receive process stopped interrupt - * @arg ETH_DMA_INT_RBU : Receive buffer unavailable interrupt - * @arg ETH_DMA_INT_R : Receive interrupt - * @arg ETH_DMA_INT_TU : Underflow interrupt - * @arg ETH_DMA_INT_RO : Overflow interrupt - * @arg ETH_DMA_INT_TJT : Transmit jabber timeout interrupt - * @arg ETH_DMA_INT_TBU : Transmit buffer unavailable interrupt - * @arg ETH_DMA_INT_TPS : Transmit process stopped interrupt - * @arg ETH_DMA_INT_T : Transmit interrupt - * @param NewValue: new value of the DMA interrupts. - * This parameter can be: ENABLE or DISABLE. - * @retval None - */ -void ETH_DMAINTConfig(uint32_t ETH_DMA_INT, TypeState NewValue) -{ - if (NewValue != DISABLE) { - /* Enable the ETH_DMA_INT control bit */ - ETH_DMA->IER |= ETH_DMA_INT; - } else { - /* Disable the ETH_DMA_INT control bit */ - ETH_DMA->IER &= (~(uint32_t)ETH_DMA_INT); - } -} - -/** - * @brief Get the bit flag of ETHERNET DMA overflow. - * @param ETH_DMA_Overflow: the DMA overflow flag of ETHERNET DMA_MFBOCNT register. - * Select one of the follwing values : - * @arg ETH_DMA_OVERFLOW_RXFIFOCOUNTER : Overflow for FIFO Overflow Counter - * @arg ETH_DMA_OVERFLOW_MISSEDFRAMECOUNTER : Overflow for Missed Frame Counter - * @retval The current ETHERNET DMA overflow Flag selected bit status(SET or RESET). - */ -TypeState ETH_GetDMAOverflowStatus(uint32_t ETH_DMA_Overflow) -{ - if ((ETH_DMA->MFBOCNT & ETH_DMA_Overflow) != (uint32_t)RESET) { - /* DMA overflow Flag is set */ - return SET; - } else { - /* DMA overflow Flag is reset */ - return RESET; - } -} - -/** - * @brief Get the DMA Rx value of overflow Missed Frame Counter. - * @param None - * @retval The ETH_DMA_MFBOCNT register MFA bit value. - */ -uint32_t ETH_GetRxOverflowMissedFrameCounter(void) -{ - return ((uint32_t)((ETH_DMA->MFBOCNT & ETH_DMA_MFBOCNT_MSFA) >> ETH_DMA_RX_OVERFLOW_MISSEDFRAMES_COUNTERSHIFT)); -} - -/** - * @brief Get the DMA value of Buffer unavailable Missed Frame Counter. - * @param None - * @retval The ETH_DMA_MFBOCNT register MFC bit value. - */ -uint32_t ETH_GetBufferUnavailableMissedFrameCounter(void) -{ - return ((uint32_t)(ETH_DMA->MFBOCNT) & ETH_DMA_MFBOCNT_MSFC); -} - -/** - * @brief Get the DMA value of the current Tx desc start address. - * @param None - * @retval The ETH_DMA_CTDAR register value. - */ -uint32_t ETH_GetCurrentTxDescStartAddress(void) -{ - return ((uint32_t)(ETH_DMA->CTDAR)); -} - -/** - * @brief Get the DMA value of the current Rx desc start address. - * @param None - * @retval The ETH_DMA_CRDAR register value. - */ -uint32_t ETH_GetCurrentRxDescStartAddress(void) -{ - return ((uint32_t)(ETH_DMA->CRDAR)); -} - -/** - * @brief Get the DMA value of the current Tx buffer address. - * @param None - * @retval The ETH_DMA_CTBAR register value. - */ -uint32_t ETH_GetCurrentTxBufferAddress(void) -{ - return ((uint32_t)(ETH_DMA->CTBAR)); -} - -/** - * @brief Get the DMA value of the current Rx buffer address. - * @param None - * @retval The ETH_DMA_CRBAR register value. - */ -uint32_t ETH_GetCurrentRxBufferAddress(void) -{ - return ((uint32_t)(ETH_DMA->CRBAR)); -} - -/** - * @brief Poll the DMA Transmission enable by writing any value to the ETH_DMA_TPER register. - * This will make the DMA to resume transmission. - * @param None - * @retval None. - */ -void ETH_ResumeDMATransmission(void) -{ - ETH_DMA->TPER = 0; -} - -/** - * @brief Poll the DMA Transmission enable by writing any value to the ETH_DMA_RPER register. - * This will make the DMA to resume reception. - * @param None - * @retval None. - */ -void ETH_ResumeDMAReception(void) -{ - ETH_DMA->RPER = 0; -} - -/* WUM */ -/** - * @brief Reset Wakeup frame filter register pointer. - * @param None - * @retval None - */ -void ETH_WakeUpFrameFilterRegisterReset(void) -{ - /* Set WUFFRPR bit for Reseting the ETH_MAC_RWFFR register pointer to 0 */ - ETH_MAC->WUMR |= ETH_MAC_WUMR_WUFFRPR; -} - -/** - * @brief Set the remote wakeup frame registers. - * @param pBuffer: Pointer to remote WakeUp Frame Filter Register buffer data (8 words). - * @retval None - */ -void ETH_SetWakeUpFrameFilterRegister(uint32_t *pBuffer) -{ - uint32_t num = 0; - - /* Configuration ETH_MAC_RWFFR register */ - for (num = 0; num < ETH_WAKEUP_REGISTER_LENGTH; num++) { - ETH_MAC->RWFFR = pBuffer[num]; - } -} - -/** - * @brief Enable or disable ETH_MAC_WUMR_GU control bit. - * @param NewValue: new value of the MAC Global Unicast Wake-Up. - * This parameter can be: ENABLE or DISABLE. - * @retval None - */ -void ETH_GlobalUnicastWakeUp_Enable(TypeState NewValue) -{ - if (NewValue != DISABLE) { - /* Enable the ETH_MAC_WUMR_GU control bit */ - ETH_MAC->WUMR |= ETH_MAC_WUMR_GU; - } else { - /* Disable the ETH_MAC_WUMR_GU control bit */ - ETH_MAC->WUMR &= ~ETH_MAC_WUMR_GU; - } -} - -/** - * @brief Get the bit flag of the WUM. - * @param ETH_WUM_FLAG: the flag of ETH_MAC_WUMR register. - * Select one of the follwing values : - * @arg ETH_WUM_FLAG_WUFFRPR : Wake-Up Frame Filter Register Poniter Reset - * @arg ETH_WUM_FLAG_WUFR : Wake-Up Frame Received - * @arg ETH_WUM_FLAG_MPKR : Magic Packet Received - * @retval The current ETHERNET WUM Flag selected bit status(SET or RESET). - */ -TypeState ETH_GetWUMBitState(uint32_t ETH_WUM_FLAG) -{ - if ((ETH_MAC->WUMR & ETH_WUM_FLAG) != (uint32_t)RESET) { - /* WUM Flag is set */ - return SET; - } else { - /* WUM Flag is reset */ - return RESET; - } -} - -/** - * @brief Enable or disable the ETH_MAC_WUMR_WFEN control bit. - * @param NewValue: new value of the ETH_MAC_WUMR_WFEN bit. - * This parameter can be: ENABLE or DISABLE. - * @retval None - */ -void ETH_WakeUpFrameDetection_Enable(TypeState NewValue) -{ - if (NewValue != DISABLE) { - /* Active the MAC Wake-Up Frame Detection */ - ETH_MAC->WUMR |= ETH_MAC_WUMR_WFEN; - } else { - /* Deactive the MAC Wake-Up Frame Detection */ - ETH_MAC->WUMR &= ~ETH_MAC_WUMR_WFEN; - } -} - -/** - * @brief Enable or disable the ETH_MAC_WUMR_MPEN control bit. - * @param NewValue: new value of the ETH_MAC_WUMR_MPEN bit. - * This parameter can be: ENABLE or DISABLE. - * @retval None - */ -void ETH_MagicPacketDetection_Enable(TypeState NewValue) -{ - if (NewValue != DISABLE) { - /* Enable the ETH_MAC_WUMR_MPEN control bit */ - ETH_MAC->WUMR |= ETH_MAC_WUMR_MPEN; - } else { - /* Disable the ETH_MAC_WUMR_MPEN control bit */ - ETH_MAC->WUMR &= ~ETH_MAC_WUMR_MPEN; - } -} - -/** - * @brief Enable or disable the ETH_MAC_WUMR_PWD control bit. - * @param NewValue: new value of the ETH_MAC_WUMR_PWD bit. - * This parameter can be: ENABLE or DISABLE. - * @retval None - */ -void ETH_PowerDown_Enable(TypeState NewValue) -{ - if (NewValue != DISABLE) { - /* Enable the ETH_MAC_WUMR_PWD control bit */ - ETH_MAC->WUMR |= ETH_MAC_WUMR_PWD; - } else { - /* Disable the ETH_MAC_WUMR_PWD control bit */ - ETH_MAC->WUMR &= ~ETH_MAC_WUMR_PWD; - } -} - -/* MSC */ -/** - * @brief Enable or disable the ETH_MSC_CTLR_MCFZ control bit. - * @param NewValue: new value of the MSC Counter Freeze. - * This parameter can be: ENABLE or DISABLE. - * @retval None - */ -void ETH_MSCCounterFreeze_Enable(TypeState NewValue) -{ - if (NewValue != DISABLE) { - /* Enable the ETH_MSC_CTLR_MCFZ control bit */ - ETH_MSC->CTLR |= ETH_MSC_CTLR_MCFZ; - } else { - /* Disable the ETH_MSC_CTLR_MCFZ control bit */ - ETH_MSC->CTLR &= ~ETH_MSC_CTLR_MCFZ; - } -} - -/** - * @brief Enable or disable the ETH_MSC_CTLR_RTOR control bit. - * @param NewValue: new value of the MSC Reset On Read. - * This parameter can be: ENABLE or DISABLE. - * @retval None - */ -void ETH_MSCResetOnRead_Enable(TypeState NewValue) -{ - if (NewValue != DISABLE) { - /* Enable the ETH_MSC_CTLR_RTOR control bit */ - ETH_MSC->CTLR |= ETH_MSC_CTLR_RTOR; - } else { - /* Disable the ETH_MSC_CTLR_RTOR control bit */ - ETH_MSC->CTLR &= ~ETH_MSC_CTLR_RTOR; - } -} - -/** - * @brief Enable or disable the ETH_MSC_CTLR_CTSR control bit. - * @param NewValue: new value of the ETH_MSC_CTLR_CTSR bit. - * This parameter can be: ENABLE or DISABLE. - * @retval None - */ -void ETH_MSCCounterRollover_Enable(TypeState NewValue) -{ - if (NewValue != DISABLE) { - /* Enable the ETH_MSC_CTLR_CTSR control bit */ - ETH_MSC->CTLR &= ~ETH_MSC_CTLR_CTSR; - } else { - /* Disable the ETH_MSC_CTLR_CTSR control bit */ - ETH_MSC->CTLR |= ETH_MSC_CTLR_CTSR; - } -} - -/** - * @brief Resets the MSC Counters. - * @param None - * @retval None - */ -void ETH_MSCCountersReset(void) -{ - ETH_MSC->CTLR |= ETH_MSC_CTLR_CTR; -} - -/** - * @brief Enable or disable the ETH_MSC_INT control bit. - * @param ETH_MSC_INT: the MSC interrupt sources flag of MSC_RIMR and MSC_TIMR. - * This parameter can be any combination of Tx interrupt or - * any combination of Rx interrupt (but not both)of the following values: - * @arg ETH_MSC_INT_TGF : When Tx good frame counter reaches half the maximum value - * @arg ETH_MSC_INT_TGFMSC: When Tx good multi col counter reaches half the maximum value - * @arg ETH_MSC_INT_TGFSC : When Tx good single col counter reaches half the maximum value - * @arg ETH_MSC_INT_RGUF : When Rx good unicast frames counter reaches half the maximum value - * @arg ETH_MSC_INT_RFAE : When Rx alignment error counter reaches half the maximum value - * @arg ETH_MSC_INT_RFCE : When Rx crc error counter reaches half the maximum value - * @param NewValue: new value of the MSC interrupt sources flag of MSC_RIMR and MSC_TIMR. - * This parameter can be: ENABLE or DISABLE. - * @retval None - */ -void ETH_MSCINTConfig(uint32_t ETH_MSC_INT, TypeState NewValue) -{ - if ((ETH_MSC_INT & (uint32_t)0x10000000) != (uint32_t)RESET) { - /* Get MSC interrupts souce bit position */ - ETH_MSC_INT &= 0xEFFFFFFF; - - /* MSC Rx interrupts souce bit selected */ - if (NewValue != DISABLE) { - /* Enable the Rx ETH_MSC_INT control bit */ - ETH_MSC->RIMR &= (~(uint32_t)ETH_MSC_INT); - } else { - /* Disable the Rx ETH_MSC_INT control bit */ - ETH_MSC->RIMR |= ETH_MSC_INT; - } - } else { - /* MSC Tx interrupts souce bit selected */ - if (NewValue != DISABLE) { - /* Enable the Tx ETH_MSC_INT control bit */ - ETH_MSC->TIMR &= (~(uint32_t)ETH_MSC_INT); - } else { - /* Disable the Tx ETH_MSC_INT control bit */ - ETH_MSC->TIMR |= ETH_MSC_INT; - } - } -} - -/** - * @brief Get the bit flag of MSC INT. - * @param ETH_MSC_INT: the MSC interrupt flag of ETH_MSC_RISR and ETH_MSC_TISR. - * Select one of the follwing values : - * @arg ETH_MSC_INT_TGF: When Tx good frame counter reaches half the maximum value - * @arg ETH_MSC_INT_TGFMSC: When Tx good multi col counter reaches half the maximum value - * @arg ETH_MSC_INT_TGFSC: When Tx good single col counter reaches half the maximum value - * @arg ETH_MSC_INT_RGUF: When Rx good unicast frames counter reaches half the maximum value - * @arg ETH_MSC_INT_RFAE : When Rx alignment error counter reaches half the maximum value - * @arg ETH_MSC_INT_RFCE : When Rx crc error counter reaches half the maximum value - * @retval The current ETHERNET MSC IT selected bit status(SET or RESET). - */ -TypeState ETH_GetMSCINTStatus(uint32_t ETH_MSC_INT) -{ - if ((ETH_MSC_INT & (uint32_t)0x10000000) != (uint32_t)RESET) { - /* Check if the MSC interrupt flag of ETH_MSC_RISR selected is enabled and occured */ - if ((((ETH_MSC->RISR & ETH_MSC_INT) != (uint32_t)RESET)) && ((ETH_MSC->RIMR & ETH_MSC_INT) != (uint32_t)RESET)) { - /* The MSC interrupt flag of ETH_MSC_RISR is set */ - return SET; - } else { - /* The MSC interrupt flag of ETH_MSC_RISR is reset */ - return RESET; - } - } else { - /* Check if the MSC interrupt flag of ETH_MSC_TISR selected is enabled and occured */ - if ((((ETH_MSC->TISR & ETH_MSC_INT) != (uint32_t)RESET)) && ((ETH_MSC->RIMR & ETH_MSC_INT) != (uint32_t)RESET)) { - /* The MSC interrupt flag of ETH_MSC_TISR is set */ - return SET; - } else { - /* The MSC interrupt flag of ETH_MSC_TISR is reset */ - return RESET; - } - } -} - -/** - * @brief Read value of the MSC module register. - * @param ETH_MSC_Register: the MSC module register selected. - * Select one of the follwing values : - * @arg ETH_MSC_CTLR : MSC CR register - * @arg ETH_MSC_RISR : MSC RIR register - * @arg ETH_MSC_TISR : MSC TIR register - * @arg ETH_MSC_RIMR : MSC RIMR register - * @arg ETH_MSC_TIMR : MSC TIMR register - * @arg ETH_MSC_SCCNT : MSC TGFSCCR register - * @arg ETH_MSC_MSCCNT : MSC TGFMSCCR register - * @arg ETH_MSC_TGFCNT : MSC TGFCR register - * @arg ETH_MSC_RFCECNT : MSC RFCECR register - * @arg ETH_MSC_RFAECNT : MSC RFAECR register - * @arg ETH_MSC_RGUFCNT : MSC RGUFCRregister - * @retval MSC module Register selected value. - */ -uint32_t ETH_GetMSCRegister(uint32_t ETH_MSC_Register) -{ - /* Return the value of MSC module Register selected */ - return (*(__IO uint32_t *)(ETH_MAC_BASE + ETH_MSC_Register)); -} - -/* PTP */ -/** - * @brief Updated the Time Stamp Addend register value to the PTP block(used only when the system time is configured - * for Fine update mode). - * @param None - * @retval None - */ -void ETH_PTPTimeStampAddendUpdate(void) -{ - ETH_PTP->TSCTLR |= ETH_PTP_TSCTLR_TMSARU; -} - -/** - * @brief Set ETH_PTP_TSCTLR_TMSITEN bit. - * @param NewValue: new value of the MAC reception. - * This parameter can be: ENABLE or DISABLE. - * @retval None - */ -void ETH_PTPTimeStampIntTrigger_Enable(TypeState NewValue) -{ - if (NewValue != DISABLE) { - /* Enable ETH_PTP_TSCTLR_TMSITEN bit */ - ETH_PTP->TSCTLR |= ETH_PTP_TSCTLR_TMSITEN; - } else { - /* Disable ETH_PTP_TSCTLR_TMSITEN bit */ - ETH_PTP->TSCTLR &= ~ETH_PTP_TSCTLR_TMSITEN; - } -} - -/** - * @brief Updated the Time Stamp Update register value to the PTP system time. - * @param NewValue: new value of the MAC reception. - * This parameter can be: ENABLE or DISABLE. - * @retval None - */ -void ETH_PTPTimeStampUpdate_Enable(TypeState NewValue) -{ - if (NewValue != DISABLE) { - /* Enable PTP time stamp update */ - ETH_PTP->TSCTLR |= ETH_PTP_TSCTLR_TMSSTU; - } else { - /* Disable PTP time stamp update */ - ETH_PTP->TSCTLR &= ~ETH_PTP_TSCTLR_TMSSTU; - } -} - -/** - * @brief Initialize the PTP Time Stamp mode - * @param None - * @retval None - */ -void ETH_PTPTimeStampInit(void) -{ - ETH_PTP->TSCTLR |= ETH_PTP_TSCTLR_TMSSTI; -} - -/** - * @brief Set the PTP Time Stamp Update mode - * @param UpdateMode: the PTP Update mode selected - * Select one of the follwing values : - * @arg ETH_PTP_FINEMODE : Fine Update method - * @arg ETH_PTP_COARSEMODE : Coarse Update method - * @retval None - */ -void ETH_PTPUpdateModeConfig(uint32_t UpdateMode) -{ - if (UpdateMode != ETH_PTP_COARSEMODE) { - /* Enable the PTP Fine Update mode */ - ETH_PTP->TSCTLR |= ETH_PTP_TSCTLR_TMSFCU; - } else { - /* Disable the PTP Coarse Update mode */ - ETH_PTP->TSCTLR &= (~(uint32_t)ETH_PTP_TSCTLR_TMSFCU); - } -} - -/** - * @brief Enable or disable ETH_PTP_TSCTLR_TMSEN control bit. - * @param NewValue: new value of the ETH_PTP_TSCTLR_TMSEN control bit - * This parameter can be: ENABLE or DISABLE. - * @retval None - */ -void ETH_PTPTimeStamp_Enable(TypeState NewValue) -{ - if (NewValue != DISABLE) { - /* Enable the ETH_PTP_TSCTLR_TMSEN control bit */ - ETH_PTP->TSCTLR |= ETH_PTP_TSCTLR_TMSEN; - } else { - /* Disable the ETH_PTP_TSCTLR_TMSEN control bit */ - ETH_PTP->TSCTLR &= (~(uint32_t)ETH_PTP_TSCTLR_TMSEN); - } -} - -/** - * @brief Get the bit flag of ETHERNET PTP. - * @param ETH_PTP_FLAG: the flag of PTP_TSCTLR register. - * Select one of the follwing values : - * @arg ETH_PTP_FLAG_TMSARU : Addend Register Update - * @arg ETH_PTP_FLAG_TMSITEN : Time Stamp Interrupt Trigger Enable - * @arg ETH_PTP_FLAG_TMSSTU : Time Stamp Update - * @arg ETH_PTP_FLAG_TMSSTI : Time Stamp Initialize - * @retval The current ETHERNET PTP Flag selected bit status(SET or RESET). - */ -TypeState ETH_GetPTPBitState(uint32_t ETH_PTP_FLAG) -{ - if ((ETH_PTP->TSCTLR & ETH_PTP_FLAG) != (uint32_t)RESET) { - /* ETH_PTP_FLAG is set */ - return SET; - } else { - /* ETH_PTP_FLAG is reset */ - return RESET; - } -} - -/** - * @brief Set Each HCLK cycle the system time Sub-Second Increased value. - * @param SubSecond: the PTP_SSINCR Register value. - * @retval None - */ -void ETH_SetPTPSubSecondIncrement(uint32_t SubSecond) -{ - ETH_PTP->SSINCR = SubSecond; -} - -/** - * @brief Set the system time update sign and values. - * @param Sign: the PTP Time update value sign(positive or negative). - * Select one of the follwing values : - * @arg ETH_PTP_POSITIVETIME : positive time value. - * @arg ETH_PTP_NEGATIVETIME : negative time value. - * @param Second: the PTP Time update value in second part. - * @param SubSecond: the PTP Time update value in sub-second part. - * This parameter is a 31 bit value, bit32 correspond to the sign. - * @retval None - */ -void ETH_SetPTPUpdateTimeValue(uint32_t Sign, uint32_t SecondValue, uint32_t SubSecondValue) -{ - /* Set the PTP Time Update High Register with second value*/ - ETH_PTP->TMSHUR = SecondValue; - - /* Set the PTP Time Update Low Register with subsecond value and sign */ - ETH_PTP->TMSLUR = Sign | SubSecondValue; -} - -/** - * @brief Set the system time Addend value(used only when the system time is configured - * for Fine update mode). - * @param add: the PTP PTP_TSACNT Register value. - * @retval None - */ -void ETH_SetPTPTimeStampAddend(uint32_t add) -{ - ETH_PTP->TSACNT = add; -} - -/** - * @brief Set the Target system Time values. - * @param HighReg_Value: the PTP Expected Time High Register value. - * @param LowReg_Value: the PTP Expected Time Low Register value. - * @retval None - */ -void ETH_SetPTPTargetTime(uint32_t HighReg_Value, uint32_t LowReg_Value) -{ - /* Set the PTP Expected Time High Register */ - ETH_PTP->ETHR = HighReg_Value; - /* Set the PTP Expected Time Low Register */ - ETH_PTP->ETLR = LowReg_Value; -} - -/** - * @brief Read the value of PTP module register . - * @param ETH_PTPRegister: the PTP module register selected. - * Select one of the follwing values : - * @arg ETH_PTP_TSCTLR : Sub-Second Increment Register - * @arg ETH_PTP_SSINCR : Sub-Second Increment Register - * @arg ETH_PTP_TMSHR : Time Stamp High Register - * @arg ETH_PTP_TMSLR : Time Stamp Low Register - * @arg ETH_PTP_TMSHUR : Time Stamp High Update Register - * @arg ETH_PTP_TMSLUR : Time Stamp Low Update Register - * @arg ETH_PTP_TSACNT : Time Stamp Addend Register - * @arg ETH_PTP_ETHR : Target Time High Register - * @arg ETH_PTP_ETLR : Target Time Low Register - * @retval ETHERNET PTP Register selected value. - */ -uint32_t ETH_GetPTPRegister(uint32_t ETH_PTPRegister) -{ - return (*(__IO uint32_t *)(ETH_MAC_BASE + ETH_PTPRegister)); -} - -/** - * @brief Initialize the DMA Tx descriptors's parameters in chain mode with PTP. - * @param DMATxDescTab: Pointer to the first Tx descriptor table - * @param DMAPTPTxDescTab: Pointer to the first PTP Tx descriptor table - * @param pTxBuff: Pointer to the first TxBuffer table - * @param TxBuffCnt: the used Tx descriptor sum in the table - * @retval None - */ -void ETH_DMAPTPTxDescChainModeInit(ETH_DMADESCTypeDef *DMATxDescTab, ETH_DMADESCTypeDef *DMAPTPTxDescTab, - uint8_t *pTxBuff, uint32_t TxBuffCnt) -{ - uint32_t num = 0; - ETH_DMADESCTypeDef *DMATxDesc; - - DMACurrentTxDesc = DMATxDescTab; - DMACurrentPTPTxDesc = DMAPTPTxDescTab; - /* Configuration each DMATxDesc descriptor */ - for (num = 0; num < TxBuffCnt; num++) { - /* Get the pointer to the next descriptor of the Tx Desc table */ - DMATxDesc = DMATxDescTab + num; - /* Set TCH bit and enable PTP with desc status */ - DMATxDesc->Status = ETH_DMATXDESC_TCHM | ETH_DMATXDESC_TTSEN; - - /* Set Buffer1 address pointer to application buffer */ - DMATxDesc->Buffer1Addr = (uint32_t)(&pTxBuff[num * ETH_MAX_FRAME_SIZE]); - - if (num < (TxBuffCnt - 1)) { - /* Buffer2NextDescAddr equal to next descriptor address in the Tx Desc table */ - DMATxDesc->Buffer2NextDescAddr = (uint32_t)(DMATxDescTab + num + 1); - } else { - /* When it is the last descriptor, Buffer2NextDescAddr equal to first descriptor address in the Tx Desc table */ - DMATxDesc->Buffer2NextDescAddr = (uint32_t) DMATxDescTab; - } - /* Set DMAPTPTxDescTab equal to DMATxDescTab */ - (&DMAPTPTxDescTab[num])->Buffer1Addr = DMATxDesc->Buffer1Addr; - (&DMAPTPTxDescTab[num])->Buffer2NextDescAddr = DMATxDesc->Buffer2NextDescAddr; - } - /* When it is the last PTPdescriptor, DMAPTPTxDesc status equal to the first descriptor address in the PTPTx Desc list address */ - (&DMAPTPTxDescTab[num - 1])->Status = (uint32_t) DMAPTPTxDescTab; - - ETH_DMA->TDTAR = (uint32_t) DMATxDescTab; -} - -/** - * @brief Initialize the DMA Rx descriptors's parameters in chain mode with PTP. - * @param DMARxDescTab: Pointer to the first Rx descriptor table - * @param DMAPTPRxDescTab: Pointer to the first PTP Rx descriptor table - * @param pRxBuff: Pointer to the first RxBuffer table - * @param RxBuffCnt: the used Rx descriptor sum in the table - * @retval None - */ -void ETH_DMAPTPRxDescChainModeInit(ETH_DMADESCTypeDef *DMARxDescTab, ETH_DMADESCTypeDef *DMAPTPRxDescTab, - uint8_t *pRxBuff, uint32_t RxBuffCnt) -{ - uint32_t num = 0; - ETH_DMADESCTypeDef *DMARxDesc; - - DMACurrentRxDesc = DMARxDescTab; - DMACurrentPTPRxDesc = DMAPTPRxDescTab; - /* Configuration each DMARxDesc descriptor */ - for (num = 0; num < RxBuffCnt; num++) { - /* Get the pointer to the next descriptor of the Rx Desc table */ - DMARxDesc = DMARxDescTab + num; - DMARxDesc->Status = ETH_DMARXDESC_BUSY; - - /* Set TCH bit and buffer1 size */ - DMARxDesc->ControlBufferSize = ETH_DMARXDESC_RCHM | (uint32_t)ETH_MAX_FRAME_SIZE; - /* Set Buffer1 address pointer to application buffer */ - DMARxDesc->Buffer1Addr = (uint32_t)(&pRxBuff[num * ETH_MAX_FRAME_SIZE]); - - if (num < (RxBuffCnt - 1)) { - /* Buffer2NextDescAddr equal to next descriptor address in the Rx Desc table */ - DMARxDesc->Buffer2NextDescAddr = (uint32_t)(DMARxDescTab + num + 1); - } else { - /* When it is the last descriptor, Buffer2NextDescAddr equal to first descriptor address in the Rx Desc table */ - DMARxDesc->Buffer2NextDescAddr = (uint32_t)(DMARxDescTab); - } - /* Set DMAPTPRxDescTab equal to DMARxDescTab */ - (&DMAPTPRxDescTab[num])->Buffer1Addr = DMARxDesc->Buffer1Addr; - (&DMAPTPRxDescTab[num])->Buffer2NextDescAddr = DMARxDesc->Buffer2NextDescAddr; - } - /* When it is the last PTPdescriptor, DMAPTPRxDesc status equal to the first descriptor address in the PTPRx Desc table address */ - (&DMAPTPRxDescTab[num - 1])->Status = (uint32_t) DMAPTPRxDescTab; - - /* Update Receive Desciptor Table Address Register */ - ETH_DMA->RDTAR = (uint32_t) DMARxDescTab; -} - -/** - * @brief Send data with Time Stamp values of application buffer as a transmit packet. - * @param pbuf: pointer to the applicationbuffer. - * @param size: the application buffer size. - * @param PTPTxTab: Pointer to the first PTP Tx table to store Time stamp values. - * @retval The transmission with PTP result(ERROR or SUCCESS) - */ -uint32_t ETH_HandlePTPTxPkt(uint8_t *pbuf, uint16_t size, uint32_t *PTPTxTab) -{ - uint32_t offset = 0, timeout = 0; - - if ((DMACurrentTxDesc->Status & ETH_DMATXDESC_BUSY) != (uint32_t)RESET) { - /* Return ERROR: the descriptor is busy due to own by the DMA */ - return ERROR; - } - for (offset = 0; offset < size; offset++) { - (*(__IO uint8_t *)((DMACurrentPTPTxDesc->Buffer1Addr) + offset)) = (*(pbuf + offset)); - } - /* Setting the Frame Length */ - DMACurrentTxDesc->ControlBufferSize = (size & (uint32_t)0x1FFF); - /* Setting the segment of frame (ETH_DMATXDESC_LSG and ETH_DMATXDESC_FSG are SET that frame is transmitted in one descriptor) */ - DMACurrentTxDesc->Status |= ETH_DMATXDESC_LSG | ETH_DMATXDESC_FSG; - /* Enable the DMA transmission */ - DMACurrentTxDesc->Status |= ETH_DMATXDESC_BUSY; - /* Check Tx Buffer unavailable flag status */ - if ((ETH_DMA->STR & ETH_DMA_STR_TBU) != (uint32_t)RESET) { - /* Clear TBU ETHERNET DMA flag */ - ETH_DMA->STR = ETH_DMA_STR_TBU; - /* Resume DMA transmission by writing to the TPER register*/ - ETH_DMA->TPER = 0; - } - /* Wait for ETH_DMATXDESC_TTMSS flag to be set unless timeout */ - do { - timeout++; - } while (!(DMACurrentTxDesc->Status & ETH_DMATXDESC_TTMSS) && (timeout < 0xFFFF)); - /* Return ERROR due to timeout */ - if (timeout == PHY_READ_TO) { - return ERROR; - } - /* Clear the DMACurrentTxDesc status register TTSS flag */ - DMACurrentTxDesc->Status &= ~ETH_DMATXDESC_TTMSS; - *PTPTxTab++ = DMACurrentTxDesc->Buffer1Addr; - *PTPTxTab = DMACurrentTxDesc->Buffer2NextDescAddr; - /* Update the ETHERNET DMA current Tx descriptor pointer to the next Tx decriptor in DMA Tx decriptor talbe*/ - /* Chained Mode */ - if ((DMACurrentTxDesc->Status & ETH_DMATXDESC_TCHM) != (uint32_t)RESET) { - DMACurrentTxDesc = (ETH_DMADESCTypeDef *)(DMACurrentPTPTxDesc->Buffer2NextDescAddr); - if (DMACurrentPTPTxDesc->Status != 0) { - DMACurrentPTPTxDesc = (ETH_DMADESCTypeDef *)(DMACurrentPTPTxDesc->Status); - } else { - DMACurrentPTPTxDesc++; - } - } - /* Ring Mode */ - else { - if ((DMACurrentTxDesc->Status & ETH_DMATXDESC_TERM) != (uint32_t)RESET) { - DMACurrentTxDesc = (ETH_DMADESCTypeDef *)(ETH_DMA->TDTAR); - DMACurrentPTPTxDesc = (ETH_DMADESCTypeDef *)(ETH_DMA->TDTAR); - } else { - DMACurrentTxDesc = (ETH_DMADESCTypeDef *)((uint32_t)DMACurrentTxDesc + ETH_DMATXDESC_SIZE + ((ETH_DMA->BCR & ETH_DMA_BCR_DPSL) >> 2)); - DMACurrentPTPTxDesc = (ETH_DMADESCTypeDef *)((uint32_t)DMACurrentPTPTxDesc + ETH_DMATXDESC_SIZE + ((ETH_DMA->BCR & ETH_DMA_BCR_DPSL) >> 2)); - } - } - return SUCCESS; -} - -/** - * @brief Receive a packet data with Time Stamp values to application buffer. - * @param pbuf: Pointer on the application buffer. - * @param PTPRxTab: Pointer to the first PTP Rx table to store Time stamp values. - * @retval The Receive frame length with PTP(If size is equal to ERROR, the receiving unsuccessful) - */ -uint32_t ETH_HandlePTPRxPkt(uint8_t *pbuf, uint32_t *PTPRxTab) -{ - uint32_t offset = 0, size = 0; - - if ((DMACurrentRxDesc->Status & ETH_DMARXDESC_BUSY) != (uint32_t)RESET) { - /* Return ERROR: the descriptor is busy due to own by the DMA */ - return ERROR; - } - if (((DMACurrentRxDesc->Status & ETH_DMARXDESC_ERRS) == (uint32_t)RESET) && - ((DMACurrentRxDesc->Status & ETH_DMARXDESC_LDES) != (uint32_t)RESET) && - ((DMACurrentRxDesc->Status & ETH_DMARXDESC_FDES) != (uint32_t)RESET)) { - /* Get the Frame Length exclusive CRC */ - size = ((DMACurrentRxDesc->Status & ETH_DMARXDESC_FRML) >> ETH_DMARXDESC_FRAME_LENGTHSHIFT) - 4; - for (offset = 0; offset < size; offset++) { - (*(pbuf + offset)) = (*(__IO uint8_t *)((DMACurrentPTPRxDesc->Buffer1Addr) + offset)); - } - } else { - /* Return ERROR */ - size = ERROR; - } - /* Check Rx Buffer unavailable flag status */ - if ((ETH_DMA->STR & ETH_DMA_STR_RBU) != (uint32_t)RESET) { - /* Clear RBU ETHERNET DMA flag */ - ETH_DMA->STR = ETH_DMA_STR_RBU; - /* Resume DMA reception by writing to the RPER register*/ - ETH_DMA->RPER = 0; - } - *PTPRxTab++ = DMACurrentRxDesc->Buffer1Addr; - *PTPRxTab = DMACurrentRxDesc->Buffer2NextDescAddr; - /* Enable reception */ - DMACurrentRxDesc->Status |= ETH_DMARXDESC_BUSY; - /* Update the ETHERNET DMA current Rx descriptor pointer to the next Rx decriptor in DMA Rx decriptor talbe*/ - /* Chained Mode */ - if ((DMACurrentRxDesc->ControlBufferSize & ETH_DMARXDESC_RCHM) != (uint32_t)RESET) { - DMACurrentRxDesc = (ETH_DMADESCTypeDef *)(DMACurrentPTPRxDesc->Buffer2NextDescAddr); - if (DMACurrentPTPRxDesc->Status != 0) { - DMACurrentPTPRxDesc = (ETH_DMADESCTypeDef *)(DMACurrentPTPRxDesc->Status); - } else { - DMACurrentPTPRxDesc++; - } - } - /* Ring Mode */ - else { - if ((DMACurrentRxDesc->ControlBufferSize & ETH_DMARXDESC_RERR) != (uint32_t)RESET) { - DMACurrentRxDesc = (ETH_DMADESCTypeDef *)(ETH_DMA->RDTAR); - } else { - DMACurrentRxDesc = (ETH_DMADESCTypeDef *)((uint32_t)DMACurrentRxDesc + ETH_DMARXDESC_SIZE + ((ETH_DMA->BCR & ETH_DMA_BCR_DPSL) >> 2)); - } - } - /* Return Frame size or ERROR */ - return (size); -} - -#ifndef USE_Delay -/** - * @brief Insert a delay time. - * @param nCount: specifies the delay time length. - * @retval None - */ -static void ETH_Delay(__IO uint32_t nCount) -{ - __IO uint32_t time = 0; - - for (time = nCount; time != 0; time--) { - } -} -#endif /* USE_Delay */ -#endif /* GD32F10X_CL */ -/** - * @} - */ - -/** - * @} - */ - -/** - * @} - */ - diff --git a/bsp/gd32103c-eval/Libraries/GD32F1xx_standard_peripheral/Source/gd32f10x_exmc.c b/bsp/gd32103c-eval/Libraries/GD32F1xx_standard_peripheral/Source/gd32f10x_exmc.c deleted file mode 100644 index b0a93ff71a..0000000000 --- a/bsp/gd32103c-eval/Libraries/GD32F1xx_standard_peripheral/Source/gd32f10x_exmc.c +++ /dev/null @@ -1,758 +0,0 @@ -/** - ****************************************************************************** - * @brief EXMC functions of the firmware library. - ****************************************************************************** - */ - -/* Includes ------------------------------------------------------------------*/ -#include "gd32f10x_exmc.h" -#include "gd32f10x_rcc.h" - -/** @addtogroup GD32F10x_Firmware - * @{ - */ - -/** @defgroup EXMC - * @brief EXMC driver modules - * @{ - */ - -/** @defgroup EXMC_Private_Defines - * @{ - */ - -/* EXMC Bank1 SCTLRx_BAKEN and SCTLRx_NORAEN Mask */ -#define SCTLR_BAKEN_SET ((uint32_t)0x00000001) -#define SCTLR_BAKEN_RESET ((uint32_t)0x000FFFFE) - -/* EXMC Bank1 SCTLRx_NOREN Mask */ -#define SCTLR_NOREN_SET ((uint32_t)0x00000040) - - -/* EXMC Bank2/3/4 CTLRx_BAKEN Mask */ -#define CTLR_BAKEN_SET ((uint32_t)0x00000004) -#define CTLR_BAKEN_RESET ((uint32_t)0x000FFFFB) - -/* EXMC Bank2/3/4 CTLRx_ECCEN Mask */ -#define CTLR_ECCEN_SET ((uint32_t)0x00000040) -#define CTLR_ECCEN_RESET ((uint32_t)0x000FFFBF) - -/* EXMC Bank2/3/4 CTLRx_MTYPE Mask */ -#define CTLR_EMTYP_NAND ((uint32_t)0x00000008) - -/* EXMC Bank1 Register Reset mask*/ -#define BANK1_SCTLR1_RESET ((uint32_t)0x000030DB) -#define BANK1_SCTLR_RESET ((uint32_t)0x000030D2) -#define BANK1_STR_RESET ((uint32_t)0x0FFFFFFF) -#define BANK1_SWTR_RESET ((uint32_t)0x0FFFFFFF) - -/* EXMC Bank2/3 Register Reset mask*/ -#define BANK2_3_CTLR_RESET ((uint32_t)0x00000018) -#define BANK2_3_SIR_RESET ((uint32_t)0x00000040) -#define BANK2_3_COMTR_RESET ((uint32_t)0xFCFCFCFC) -#define BANK2_3_ATTR_RESET ((uint32_t)0xFCFCFCFC) - -/* EXMC Bank4 Register Reset mask*/ -#define BANK4_CTLR_RESET ((uint32_t)0x00000018) -#define BANK4_SIR_RESET ((uint32_t)0x00000000) -#define BANK4_COMTR_RESET ((uint32_t)0xFCFCFCFC) -#define BANK4_ATTR_RESET ((uint32_t)0xFCFCFCFC) -#define BANK4_IOTR_RESET ((uint32_t)0xFCFCFCFC) - -/* EXMC register bit offset */ -#define STR_AHT_OFFSET ((uint32_t)0x00000004) -#define STR_DST_OFFSET ((uint32_t)0x00000008) -#define STR_BUSLAT_OFFSET ((uint32_t)0x00000010) -#define STR_CDIV_OFFSET ((uint32_t)0x00000014) -#define STR_DLAT_OFFSET ((uint32_t)0x00000018) - -#define SWTR_AHT_OFFSET ((uint32_t)0x00000004) -#define SWTR_DST_OFFSET ((uint32_t)0x00000008) -#define SWTR_CDIV_OFFSET ((uint32_t)0x00000014) -#define SWTR_DLAT_OFFSET ((uint32_t)0x00000018) - -#define CTLR_CTR_OFFSET ((uint32_t)0x00000009) -#define CTLR_ATR_OFFSET ((uint32_t)0x0000000D) - -#define COMTR_COMWT_OFFSET ((uint32_t)0x00000008) -#define COMTR_COMHT_OFFSET ((uint32_t)0x00000010) -#define COMTR_COMHIZT_OFFSET ((uint32_t)0x00000018) - -#define ATTR_ATTWT_OFFSET ((uint32_t)0x00000008) -#define ATTR_ATTHT_OFFSET ((uint32_t)0x00000010) -#define ATTR_ATTHIZT_OFFSET ((uint32_t)0x00000018) - -#define IOTR_IOTWT_OFFSET ((uint32_t)0x00000008) -#define IOTR_IOHT_OFFSET ((uint32_t)0x00000010) -#define IOTR_IOHIZT_OFFSET ((uint32_t)0x00000018) - -#define SIR_INTEN_OFFSET ((uint32_t)0x00000003) - -/** - * @} - */ - -/** @defgroup EXMC_Private_Functions - * @{ - */ - -/** - * @brief Reset the Bank1 NOR/SRAM registers. - * @param EXMC_NORSRAMBank: specifies the Region of Bank1. - * This parameter can be one of the following values: - * @arg EXMC_BANK1_NORSRAM1: the Region1 of Bank1 - * @arg EXMC_BANK1_NORSRAM2: the Region2 of Bank1 - * @arg EXMC_BANK1_NORSRAM3: the Region3 of Bank1 - * @arg EXMC_BANK1_NORSRAM4: the Region4 of Bank1 - * @retval None - */ -void EXMC_NORSRAM_DeInit(uint32_t EXMC_NORSRAMBank) -{ - switch (EXMC_NORSRAMBank) { - case EXMC_BANK1_NORSRAM1: { - /* the Region1 of Bank1 */ - EXMC_BANK1->SCTLR1 = BANK1_SCTLR1_RESET; - EXMC_BANK1->STR1 = BANK1_STR_RESET; - EXMC_BANK1_WT->SWTR1 = BANK1_SWTR_RESET; - break; - } - case EXMC_BANK1_NORSRAM2: { - /* the Region2 of Bank1 */ - EXMC_BANK1->SCTLR2 = BANK1_SCTLR_RESET; - EXMC_BANK1->STR2 = BANK1_STR_RESET; - EXMC_BANK1_WT->SWTR2 = BANK1_SWTR_RESET; - break; - } - case EXMC_BANK1_NORSRAM3: { - /* the Region3 of Bank1 */ - EXMC_BANK1->SCTLR3 = BANK1_SCTLR_RESET; - EXMC_BANK1->STR3 = BANK1_STR_RESET; - EXMC_BANK1_WT->SWTR3 = BANK1_SWTR_RESET; - break; - } - case EXMC_BANK1_NORSRAM4: { - /* the Region4 of Bank1 */ - EXMC_BANK1->SCTLR4 = BANK1_SCTLR_RESET; - EXMC_BANK1->STR4 = BANK1_STR_RESET; - EXMC_BANK1_WT->SWTR4 = BANK1_SWTR_RESET; - break; - } - default: - break; - } -} - -/** - * @brief Reset the Bank2 or Bank3 NAND registers. - * @param EXMC_NANDBank: specifies the Bank2 or Bank3 to be used. - * This parameter can be one of the following values: - * @arg EXMC_BANK2_NAND: Bank2 - * @arg EXMC_BANK3_NAND: Bank3 - * @retval None - */ -void EXMC_NAND_DeInit(uint32_t EXMC_NANDBank) -{ - if (EXMC_NANDBank == EXMC_BANK2_NAND) { - /* Reset the Bank2 NAND registers */ - EXMC_BANK2->CTLR2 = BANK2_3_CTLR_RESET; - EXMC_BANK2->SIR2 = BANK2_3_SIR_RESET; - EXMC_BANK2->COMTR2 = BANK2_3_COMTR_RESET; - EXMC_BANK2->ATTR2 = BANK2_3_ATTR_RESET; - } - /* EXMC_Bank3_NAND */ - else { - /* Reset the Bank3 NAND registers */ - EXMC_BANK3->CTLR3 = BANK2_3_CTLR_RESET; - EXMC_BANK3->SIR3 = BANK2_3_SIR_RESET; - EXMC_BANK3->COMTR3 = BANK2_3_COMTR_RESET; - EXMC_BANK3->ATTR3 = BANK2_3_ATTR_RESET; - } -} - -/** - * @brief Reset the Bank4 PCCARD registers. - * @param None - * @retval None - */ -void EXMC_PCCARD_DeInit(void) -{ - /* Reset EXMC Bank4 PCCARD registers */ - EXMC_BANK4->CTLR4 = BANK4_CTLR_RESET; - EXMC_BANK4->SIR4 = BANK4_SIR_RESET; - EXMC_BANK4->COMTR4 = BANK4_COMTR_RESET; - EXMC_BANK4->ATTR4 = BANK4_ATTR_RESET; - EXMC_BANK4->IOTR4 = BANK4_IOTR_RESET; -} - -/** - * @brief Initializes the EXMC Bank1 NOR/SRAM parameters. - * @param EXMC_NORSRAMInitParaStruct : the struct EXMC_NORSRAMInitPara pointer - * @retval None - */ -void EXMC_NORSRAM_Init(EXMC_NORSRAMInitPara *EXMC_NORSRAMInitParaStruct) -{ - uint32_t temp_SCTLR = 0x00000000, temp_STR = 0x00000000, temp_SWTR = 0x00000000; - - temp_SCTLR = (uint32_t)EXMC_NORSRAMInitParaStruct->EXMC_AddressDataMux | - EXMC_NORSRAMInitParaStruct->EXMC_MemoryType | - EXMC_NORSRAMInitParaStruct->EXMC_DatabusWidth | - EXMC_NORSRAMInitParaStruct->EXMC_BurstMode | - EXMC_NORSRAMInitParaStruct->EXMC_NWAITPolarity | - EXMC_NORSRAMInitParaStruct->EXMC_WrapBurstMode | - EXMC_NORSRAMInitParaStruct->EXMC_NWAITConfig | - EXMC_NORSRAMInitParaStruct->EXMC_MemoryWrite | - EXMC_NORSRAMInitParaStruct->EXMC_NWAITSignal | - EXMC_NORSRAMInitParaStruct->EXMC_ExtendedMode | - EXMC_NORSRAMInitParaStruct->EXMC_AsynWait | - EXMC_NORSRAMInitParaStruct->EXMC_WriteMode; - - temp_STR = (uint32_t)EXMC_NORSRAMInitParaStruct->EXMC_ReadWriteTimingParaStruct->EXMC_AsynAddressSetupTime | - (EXMC_NORSRAMInitParaStruct->EXMC_ReadWriteTimingParaStruct->EXMC_AsynAddressHoldTime << STR_AHT_OFFSET) | - (EXMC_NORSRAMInitParaStruct->EXMC_ReadWriteTimingParaStruct->EXMC_AsynDataSetupTime << STR_DST_OFFSET) | - (EXMC_NORSRAMInitParaStruct->EXMC_ReadWriteTimingParaStruct->EXMC_BusLatency << STR_BUSLAT_OFFSET) | - (EXMC_NORSRAMInitParaStruct->EXMC_ReadWriteTimingParaStruct->EXMC_SynCLKDivision << STR_CDIV_OFFSET) | - (EXMC_NORSRAMInitParaStruct->EXMC_ReadWriteTimingParaStruct->EXMC_SynDataLatency << STR_DLAT_OFFSET) | - EXMC_NORSRAMInitParaStruct->EXMC_ReadWriteTimingParaStruct->EXMC_AsynAccessMode; - - if (EXMC_NORSRAMInitParaStruct->EXMC_MemoryType == EXMC_MEMORY_TYPE_NOR) { - temp_SCTLR |= (uint32_t)SCTLR_NOREN_SET; - } - - if (EXMC_NORSRAMInitParaStruct->EXMC_ExtendedMode == EXMC_EXTENDED_MODE_ENABLE) { - temp_SWTR = (uint32_t)EXMC_NORSRAMInitParaStruct->EXMC_WriteTimingParaStruct->EXMC_AsynAddressSetupTime | - (EXMC_NORSRAMInitParaStruct->EXMC_WriteTimingParaStruct->EXMC_AsynAddressHoldTime << SWTR_AHT_OFFSET) | - (EXMC_NORSRAMInitParaStruct->EXMC_WriteTimingParaStruct->EXMC_AsynDataSetupTime << SWTR_DST_OFFSET) | - (EXMC_NORSRAMInitParaStruct->EXMC_WriteTimingParaStruct->EXMC_SynCLKDivision << SWTR_CDIV_OFFSET) | - (EXMC_NORSRAMInitParaStruct->EXMC_WriteTimingParaStruct->EXMC_SynDataLatency << SWTR_DLAT_OFFSET) | - EXMC_NORSRAMInitParaStruct->EXMC_WriteTimingParaStruct->EXMC_AsynAccessMode; - } else { - temp_SWTR = BANK1_SWTR_RESET; - } - - switch (EXMC_NORSRAMInitParaStruct->EXMC_NORSRAMBank) { - case EXMC_BANK1_NORSRAM1: { - /* Bank1 NOR/SRAM Region1 registers configuration */ - EXMC_BANK1->SCTLR1 = temp_SCTLR; - EXMC_BANK1->STR1 = temp_STR; - EXMC_BANK1_WT->SWTR1 = temp_SWTR; - break; - } - case EXMC_BANK1_NORSRAM2: { - /* Bank1 NOR/SRAM Region2 registers configuration */ - EXMC_BANK1->SCTLR2 = temp_SCTLR; - EXMC_BANK1->STR2 = temp_STR; - EXMC_BANK1_WT->SWTR2 = temp_SWTR; - break; - } - case EXMC_BANK1_NORSRAM3: { - /* Bank1 NOR/SRAM Region3 registers configuration */ - EXMC_BANK1->SCTLR3 = temp_SCTLR; - EXMC_BANK1->STR3 = temp_STR; - EXMC_BANK1_WT->SWTR3 = temp_SWTR; - break; - } - case EXMC_BANK1_NORSRAM4: { - /* Bank1 NOR/SRAM Region4 registers configuration */ - EXMC_BANK1->SCTLR4 = temp_SCTLR; - EXMC_BANK1->STR4 = temp_STR; - EXMC_BANK1_WT->SWTR4 = temp_SWTR; - break; - } - default: - break; - } -} - -/** - * @brief Initialize the EXMC Bank2 or Bank3 NAND parameters. - * @param EXMC_NANDInitParaStruct : the struct EXMC_NANDInitPara pointer - * @retval None - */ - -void EXMC_NAND_Init(EXMC_NANDInitPara *EXMC_NANDInitParaStruct) -{ - uint32_t temp_CTLR = 0x00000000, temp_COMTR = 0x00000000, temp_ATTR = 0x00000000; - - temp_CTLR = (uint32_t)EXMC_NANDInitParaStruct->EXMC_WaitFeature | - CTLR_EMTYP_NAND | - EXMC_NANDInitParaStruct->EXMC_DatabusWidth | - EXMC_NANDInitParaStruct->EXMC_ECCLogic | - EXMC_NANDInitParaStruct->EXMC_ECCSize | - (EXMC_NANDInitParaStruct->EXMC_CTRLatency << CTLR_CTR_OFFSET) | - (EXMC_NANDInitParaStruct->EXMC_ATRLatency << CTLR_ATR_OFFSET); - - temp_COMTR = (uint32_t)EXMC_NANDInitParaStruct->EXMC_CommonSpaceTimingParaStruct->EXMC_SetupTime | - (EXMC_NANDInitParaStruct->EXMC_CommonSpaceTimingParaStruct->EXMC_WaitTime << COMTR_COMWT_OFFSET) | - (EXMC_NANDInitParaStruct->EXMC_CommonSpaceTimingParaStruct->EXMC_HoldTime << COMTR_COMHT_OFFSET) | - (EXMC_NANDInitParaStruct->EXMC_CommonSpaceTimingParaStruct->EXMC_DatabusHiZTime << COMTR_COMHIZT_OFFSET); - - temp_ATTR = (uint32_t)EXMC_NANDInitParaStruct->EXMC_AttributeSpaceTimingParaStruct->EXMC_SetupTime | - (EXMC_NANDInitParaStruct->EXMC_AttributeSpaceTimingParaStruct->EXMC_WaitTime << ATTR_ATTWT_OFFSET) | - (EXMC_NANDInitParaStruct->EXMC_AttributeSpaceTimingParaStruct->EXMC_HoldTime << ATTR_ATTHT_OFFSET) | - (EXMC_NANDInitParaStruct->EXMC_AttributeSpaceTimingParaStruct->EXMC_DatabusHiZTime << ATTR_ATTHIZT_OFFSET); - - if (EXMC_NANDInitParaStruct->EXMC_NANDBank == EXMC_BANK2_NAND) { - /* Configure the EXMC_Bank2 NAND registers using the value of parameters */ - EXMC_BANK2->CTLR2 = temp_CTLR; - EXMC_BANK2->COMTR2 = temp_COMTR; - EXMC_BANK2->ATTR2 = temp_ATTR; - } else { - /* EXMC_Bank3_NAND registers configuration */ - EXMC_BANK3->CTLR3 = temp_CTLR; - EXMC_BANK3->COMTR3 = temp_COMTR; - EXMC_BANK3->ATTR3 = temp_ATTR; - } -} - -/** - * @brief Initialize the EXMC Bank4 PCCARD parameters. - * @param EXMC_PCCARDInitParaStruct : the struct EXMC_PCCARDInitPara pointer. - * @retval None - */ -void EXMC_PCCARD_Init(EXMC_PCCARDInitPara *EXMC_PCCARDInitParaStruct) -{ - /* Configure the EXMC_Bank4_PCCARD CTLR4 register using the value of parameters */ - EXMC_BANK4->CTLR4 = (uint32_t)EXMC_PCCARDInitParaStruct->EXMC_WaitFeature | - EXMC_DATABUS_WIDTH_16B | - (EXMC_PCCARDInitParaStruct->EXMC_CTRLatency << CTLR_CTR_OFFSET) | - (EXMC_PCCARDInitParaStruct->EXMC_ATRLatency << CTLR_ATR_OFFSET); - - /* Configure the EXMC_Bank4_PCCARD COMTR4 register using the value of parameters */ - EXMC_BANK4->COMTR4 = (uint32_t)EXMC_PCCARDInitParaStruct->EXMC_CommonSpaceTimingParaStruct->EXMC_SetupTime | - (EXMC_PCCARDInitParaStruct->EXMC_CommonSpaceTimingParaStruct->EXMC_WaitTime << COMTR_COMWT_OFFSET) | - (EXMC_PCCARDInitParaStruct->EXMC_CommonSpaceTimingParaStruct->EXMC_HoldTime << COMTR_COMHT_OFFSET) | - (EXMC_PCCARDInitParaStruct->EXMC_CommonSpaceTimingParaStruct->EXMC_DatabusHiZTime << COMTR_COMHIZT_OFFSET); - - /* Configure the EXMC_Bank4_PCCARD ATTR4 register using the value of parameters */ - EXMC_BANK4->ATTR4 = (uint32_t)EXMC_PCCARDInitParaStruct->EXMC_AttributeSpaceTimingParaStruct->EXMC_SetupTime | - (EXMC_PCCARDInitParaStruct->EXMC_AttributeSpaceTimingParaStruct->EXMC_WaitTime << ATTR_ATTWT_OFFSET) | - (EXMC_PCCARDInitParaStruct->EXMC_AttributeSpaceTimingParaStruct->EXMC_HoldTime << ATTR_ATTHT_OFFSET) | - (EXMC_PCCARDInitParaStruct->EXMC_AttributeSpaceTimingParaStruct->EXMC_DatabusHiZTime << ATTR_ATTHIZT_OFFSET); - - /* Configure the EXMC_Bank4_PCCARD IOTR4 register using the value of parameters */ - EXMC_BANK4->IOTR4 = (uint32_t)EXMC_PCCARDInitParaStruct->EXMC_IOSpaceTimingParaStruct->EXMC_SetupTime | - (EXMC_PCCARDInitParaStruct->EXMC_IOSpaceTimingParaStruct->EXMC_WaitTime << IOTR_IOTWT_OFFSET) | - (EXMC_PCCARDInitParaStruct->EXMC_IOSpaceTimingParaStruct->EXMC_HoldTime << IOTR_IOHT_OFFSET) | - (EXMC_PCCARDInitParaStruct->EXMC_IOSpaceTimingParaStruct->EXMC_DatabusHiZTime << IOTR_IOHIZT_OFFSET); -} - -/** - * @brief Initialize the struct EXMC_NORSRAMInitPara - * @param EXMC_NORSRAMInitParaStruct: the struct EXMC_NORSRAMInitPara pointer - * @retval None - */ -void EXMC_NORSRAMStruct_Init(EXMC_NORSRAMInitPara *EXMC_NORSRAMInitParaStruct) -{ - EXMC_NORSRAMInitParaStruct->EXMC_NORSRAMBank = EXMC_BANK1_NORSRAM1; - EXMC_NORSRAMInitParaStruct->EXMC_AddressDataMux = EXMC_ADDRESS_DATA_MUX_ENABLE; - EXMC_NORSRAMInitParaStruct->EXMC_MemoryType = EXMC_MEMORY_TYPE_SRAM; - EXMC_NORSRAMInitParaStruct->EXMC_DatabusWidth = EXMC_DATABUS_WIDTH_8B; - EXMC_NORSRAMInitParaStruct->EXMC_BurstMode = EXMC_BURST_MODE_DISABLE; - EXMC_NORSRAMInitParaStruct->EXMC_NWAITPolarity = EXMC_NWAIT_POLARITY_LOW; - EXMC_NORSRAMInitParaStruct->EXMC_WrapBurstMode = EXMC_WRAP_BURST_MODE_DISABLE; - EXMC_NORSRAMInitParaStruct->EXMC_NWAITConfig = EXMC_NWAIT_CONFIG_BEFORE; - EXMC_NORSRAMInitParaStruct->EXMC_MemoryWrite = EXMC_MEMORY_WRITE_ENABLE; - EXMC_NORSRAMInitParaStruct->EXMC_NWAITSignal = EXMC_NWAIT_SIGNAL_ENABLE; - EXMC_NORSRAMInitParaStruct->EXMC_ExtendedMode = EXMC_EXTENDED_MODE_DISABLE; - EXMC_NORSRAMInitParaStruct->EXMC_AsynWait = EXMC_ASYN_WAIT_DISABLE; - EXMC_NORSRAMInitParaStruct->EXMC_WriteMode = EXMC_ASYN_WRITE; - EXMC_NORSRAMInitParaStruct->EXMC_ReadWriteTimingParaStruct->EXMC_AsynAddressSetupTime = 0xF; - EXMC_NORSRAMInitParaStruct->EXMC_ReadWriteTimingParaStruct->EXMC_AsynAddressHoldTime = 0xF; - EXMC_NORSRAMInitParaStruct->EXMC_ReadWriteTimingParaStruct->EXMC_AsynDataSetupTime = 0xFF; - EXMC_NORSRAMInitParaStruct->EXMC_ReadWriteTimingParaStruct->EXMC_BusLatency = 0xF; - EXMC_NORSRAMInitParaStruct->EXMC_ReadWriteTimingParaStruct->EXMC_SynCLKDivision = 0xF; - EXMC_NORSRAMInitParaStruct->EXMC_ReadWriteTimingParaStruct->EXMC_SynDataLatency = 0xF; - EXMC_NORSRAMInitParaStruct->EXMC_ReadWriteTimingParaStruct->EXMC_AsynAccessMode = EXMC_ACCESS_MODE_A; - EXMC_NORSRAMInitParaStruct->EXMC_WriteTimingParaStruct->EXMC_AsynAddressSetupTime = 0xF; - EXMC_NORSRAMInitParaStruct->EXMC_WriteTimingParaStruct->EXMC_AsynAddressHoldTime = 0xF; - EXMC_NORSRAMInitParaStruct->EXMC_WriteTimingParaStruct->EXMC_AsynDataSetupTime = 0xFF; - EXMC_NORSRAMInitParaStruct->EXMC_WriteTimingParaStruct->EXMC_BusLatency = 0xF; - EXMC_NORSRAMInitParaStruct->EXMC_WriteTimingParaStruct->EXMC_SynCLKDivision = 0xF; - EXMC_NORSRAMInitParaStruct->EXMC_WriteTimingParaStruct->EXMC_SynDataLatency = 0xF; - EXMC_NORSRAMInitParaStruct->EXMC_WriteTimingParaStruct->EXMC_AsynAccessMode = EXMC_ACCESS_MODE_A; -} - -/** - * @brief Initialize the struct EXMC_NANDInitPara - * @param EXMC_NANDInitParaStruct: the struct EXMC_NANDInitPara pointer. - * @retval None - */ -void EXMC_NANDStruct_Init(EXMC_NANDInitPara *EXMC_NANDInitParaStruct) -{ - EXMC_NANDInitParaStruct->EXMC_NANDBank = EXMC_BANK2_NAND; - EXMC_NANDInitParaStruct->EXMC_WaitFeature = EXMC_WAIT_FEATURE_DISABLE; - EXMC_NANDInitParaStruct->EXMC_DatabusWidth = EXMC_DATABUS_WIDTH_8B; - EXMC_NANDInitParaStruct->EXMC_ECCLogic = EXMC_ECC_LOGIC_DISABLE; - EXMC_NANDInitParaStruct->EXMC_ECCSize = EXMC_ECC_SIZE_256BYTES; - EXMC_NANDInitParaStruct->EXMC_CTRLatency = 0x0; - EXMC_NANDInitParaStruct->EXMC_ATRLatency = 0x0; - EXMC_NANDInitParaStruct->EXMC_CommonSpaceTimingParaStruct->EXMC_SetupTime = 0xFC; - EXMC_NANDInitParaStruct->EXMC_CommonSpaceTimingParaStruct->EXMC_WaitTime = 0xFC; - EXMC_NANDInitParaStruct->EXMC_CommonSpaceTimingParaStruct->EXMC_HoldTime = 0xFC; - EXMC_NANDInitParaStruct->EXMC_CommonSpaceTimingParaStruct->EXMC_DatabusHiZTime = 0xFC; - EXMC_NANDInitParaStruct->EXMC_AttributeSpaceTimingParaStruct->EXMC_SetupTime = 0xFC; - EXMC_NANDInitParaStruct->EXMC_AttributeSpaceTimingParaStruct->EXMC_WaitTime = 0xFC; - EXMC_NANDInitParaStruct->EXMC_AttributeSpaceTimingParaStruct->EXMC_HoldTime = 0xFC; - EXMC_NANDInitParaStruct->EXMC_AttributeSpaceTimingParaStruct->EXMC_DatabusHiZTime = 0xFC; -} - -/** - * @brief Initialize the struct EXMC_PCCARDInitParaStruct - * @param EXMC_PCCARDInitPara: the struct EXMC_PCCARDInitParaStruct pointer. - * @retval None - */ -void EXMC_PCCARDStruct_Init(EXMC_PCCARDInitPara *EXMC_PCCARDInitParaStruct) -{ - EXMC_PCCARDInitParaStruct->EXMC_WaitFeature = EXMC_WAIT_FEATURE_DISABLE; - EXMC_PCCARDInitParaStruct->EXMC_CTRLatency = 0x0; - EXMC_PCCARDInitParaStruct->EXMC_ATRLatency = 0x0; - EXMC_PCCARDInitParaStruct->EXMC_CommonSpaceTimingParaStruct->EXMC_SetupTime = 0xFC; - EXMC_PCCARDInitParaStruct->EXMC_CommonSpaceTimingParaStruct->EXMC_WaitTime = 0xFC; - EXMC_PCCARDInitParaStruct->EXMC_CommonSpaceTimingParaStruct->EXMC_HoldTime = 0xFC; - EXMC_PCCARDInitParaStruct->EXMC_CommonSpaceTimingParaStruct->EXMC_DatabusHiZTime = 0xFC; - EXMC_PCCARDInitParaStruct->EXMC_AttributeSpaceTimingParaStruct->EXMC_SetupTime = 0xFC; - EXMC_PCCARDInitParaStruct->EXMC_AttributeSpaceTimingParaStruct->EXMC_WaitTime = 0xFC; - EXMC_PCCARDInitParaStruct->EXMC_AttributeSpaceTimingParaStruct->EXMC_HoldTime = 0xFC; - EXMC_PCCARDInitParaStruct->EXMC_AttributeSpaceTimingParaStruct->EXMC_DatabusHiZTime = 0xFC; - EXMC_PCCARDInitParaStruct->EXMC_IOSpaceTimingParaStruct->EXMC_SetupTime = 0xFC; - EXMC_PCCARDInitParaStruct->EXMC_IOSpaceTimingParaStruct->EXMC_WaitTime = 0xFC; - EXMC_PCCARDInitParaStruct->EXMC_IOSpaceTimingParaStruct->EXMC_HoldTime = 0xFC; - EXMC_PCCARDInitParaStruct->EXMC_IOSpaceTimingParaStruct->EXMC_DatabusHiZTime = 0xFC; -} - -/** - * @brief Enable or disable the specified Region of Bank1. - * @param EXMC_NORSRAMBank: specifies the Region of Bank1. - * This parameter can be one of the following values: - * @arg EXMC_BANK1_NORSRAM1: the Region1 of Bank1 - * @arg EXMC_BANK1_NORSRAM2: the Region2 of Bank1 - * @arg EXMC_BANK1_NORSRAM3: the Region3 of Bank1 - * @arg EXMC_BANK1_NORSRAM4: the Region4 of Bank1 - * @param NewValue: new value of the specified Region of Bank1. - * This parameter can be: ENABLE or DISABLE. - * @retval None - */ -void EXMC_NORSRAM_Enable(uint32_t EXMC_NORSRAMBank, TypeState NewValue) -{ - if (NewValue != DISABLE) { - /* Enable the selected NOR/SRAM Bank by setting the PBKEN bit in the BCRx register */ - switch (EXMC_NORSRAMBank) { - case EXMC_BANK1_NORSRAM1: - EXMC_BANK1->SCTLR1 |= SCTLR_BAKEN_SET; - break; - case EXMC_BANK1_NORSRAM2: - EXMC_BANK1->SCTLR2 |= SCTLR_BAKEN_SET; - break; - case EXMC_BANK1_NORSRAM3: - EXMC_BANK1->SCTLR3 |= SCTLR_BAKEN_SET; - break; - case EXMC_BANK1_NORSRAM4: - EXMC_BANK1->SCTLR4 |= SCTLR_BAKEN_SET; - break; - default: - break; - } - } else { - /* Disable the selected NOR/SRAM Bank by clearing the PBKEN bit in the BCRx register */ - switch (EXMC_NORSRAMBank) { - case EXMC_BANK1_NORSRAM1: - EXMC_BANK1->SCTLR1 &= SCTLR_BAKEN_RESET; - break; - case EXMC_BANK1_NORSRAM2: - EXMC_BANK1->SCTLR2 &= SCTLR_BAKEN_RESET; - break; - case EXMC_BANK1_NORSRAM3: - EXMC_BANK1->SCTLR3 &= SCTLR_BAKEN_RESET; - break; - case EXMC_BANK1_NORSRAM4: - EXMC_BANK1->SCTLR4 &= SCTLR_BAKEN_RESET; - break; - default: - break; - } - } -} - -/** - * @brief Enable or disable the specified NAND Bank2 or Bank3. - * @param EXMC_NANDBank: specifies the NAND Bank. - * This parameter can be one of the following values: - * @arg EXMC_BANK2_NAND: the NAND Bank2 - * @arg EXMC_BANK3_NAND: the NAND Bank3 - * @param NewValue: new value of the specified Bank. - * This parameter can be: ENABLE or DISABLE. - * @retval None - */ -void EXMC_NAND_Enable(uint32_t EXMC_NANDBank, TypeState NewValue) -{ - if (NewValue != DISABLE) { - /* Enable the selected NAND Bank by setting the PBKEN bit in the PCRx register */ - if (EXMC_NANDBank == EXMC_BANK2_NAND) { - EXMC_BANK2->CTLR2 |= CTLR_BAKEN_SET; - } else { - EXMC_BANK3->CTLR3 |= CTLR_BAKEN_SET; - } - } else { - /* Disable the selected NAND Bank by clearing the PBKEN bit in the PCRx register */ - if (EXMC_NANDBank == EXMC_BANK2_NAND) { - EXMC_BANK2->CTLR2 &= CTLR_BAKEN_RESET; - } else { - EXMC_BANK3->CTLR3 &= CTLR_BAKEN_RESET; - } - } -} - -/** - * @brief Enable or disable the Bank4 of PCCARD. - * @param NewValue: new value of the PCCARD Bank. - * This parameter can be: ENABLE or DISABLE. - * @retval None - */ -void EXMC_PCCARD_Enable(TypeState NewValue) -{ - if (NewValue != DISABLE) { - /* Enable the PCCARD Bank */ - EXMC_BANK4->CTLR4 |= CTLR_BAKEN_SET; - } else { - /* Disable the PCCARD Bank */ - EXMC_BANK4->CTLR4 &= CTLR_BAKEN_RESET; - } -} - -/** - * @brief Enable or disable the EXMC_CTLR1_ECCEN control bit. - * @param EXMC_NANDBank: specifies the NAND Bank. - * This parameter can be one of the following values: - * @arg EXMC_BANK2_NAND: the NAND Bank2 - * @arg EXMC_BANK3_NAND: the NAND Bank3 - * @param NewValue: new value of the EXMC Bank2 or Bank3 ECC calculation. - * This parameter can be: ENABLE or DISABLE. - * @retval None - */ -void EXMC_NANDECC_Enable(uint32_t EXMC_NANDBank, TypeState NewValue) -{ - if (NewValue != DISABLE) { - /* Enable the selected NAND Bank ECC function by setting the ECCEN bit in the PCRx register */ - if (EXMC_NANDBank == EXMC_BANK2_NAND) { - EXMC_BANK2->CTLR2 |= CTLR_ECCEN_SET; - } else { - EXMC_BANK3->CTLR3 |= CTLR_ECCEN_SET; - } - } else { - /* Disable the selected NAND Bank ECC function by clearing the ECCEN bit in the PCRx register */ - if (EXMC_NANDBank == EXMC_BANK2_NAND) { - EXMC_BANK2->CTLR2 &= CTLR_ECCEN_RESET; - } else { - EXMC_BANK3->CTLR3 &= CTLR_ECCEN_RESET; - } - } -} - -/** - * @brief Get the EXMC_ECCR value. - * @param EXMC_NANDBank: specifies the NAND Bank. - * This parameter can be one of the following values: - * @arg EXMC_BANK2_NAND: the NAND Bank2 - * @arg EXMC_BANK3_NAND: the NAND Bank3 - * @retval The Error Correction Code (ECC) value. - */ -uint32_t EXMC_GetECC(uint32_t EXMC_NANDBank) -{ - if (EXMC_NANDBank == EXMC_BANK2_NAND) { - return (EXMC_BANK2->ECCR2); - } else { - return (EXMC_BANK3->ECCR3); - } -} - -/** - * @brief Enable or disable the specified EXMC Bank2/3/4 interrupts. - * @param EXMC_PCNANDBank: specifies the NAND Bank or PCCARD Bank. - * This parameter can be one of the following values: - * @arg EXMC_BANK2_NAND: the NAND Bank2 - * @arg EXMC_BANK3_NAND: the NAND Bank3 - * @arg EXMC_BANK4_PCCARD: the PCCARD Bank4 - * @param EXMC_INT: the EXMC interrupt sources. - * This parameter can be any combination of the following values: - * @arg EXMC_INT_RISE: Rising edge detection interrupt - * @arg EXMC_INT_LEVEL: Level edge detection interrupt - * @arg EXMC_INT_FALL: Falling edge detection interrupt - * @param NewValue: new value of the specified EXMC interrupts. - * This parameter can be: ENABLE or DISABLE. - * @retval None - */ -void EXMC_INTConfig(uint32_t EXMC_PCNANDBank, uint32_t EXMC_INT, TypeState NewValue) -{ - if (NewValue != DISABLE) { - /* Enable the specified EXMC_Bank2 interrupts */ - if (EXMC_PCNANDBank == EXMC_BANK2_NAND) { - EXMC_BANK2->SIR2 |= EXMC_INT; - } - /* Enable the specified EXMC_Bank3 interrupts */ - else if (EXMC_PCNANDBank == EXMC_BANK3_NAND) { - EXMC_BANK3->SIR3 |= EXMC_INT; - } - /* Enable the specified EXMC_Bank4 interrupts */ - else { - EXMC_BANK4->SIR4 |= EXMC_INT; - } - } else { - /* Disable the specified EXMC_Bank2 interrupts */ - if (EXMC_PCNANDBank == EXMC_BANK2_NAND) { - EXMC_BANK2->SIR2 &= ~((uint32_t)EXMC_INT); - } - /* Disable the specified EXMC_Bank3 interrupts */ - else if (EXMC_PCNANDBank == EXMC_BANK3_NAND) { - EXMC_BANK3->SIR3 &= ~((uint32_t)EXMC_INT); - } - /* Disable the specified EXMC_Bank4 interrupts */ - else { - EXMC_BANK4->SIR4 &= ~((uint32_t)EXMC_INT); - } - } -} - -/** - * @brief Get the bit flag of EXMC_SIRx register. - * @param EXMC_PCNANDBank: specifies the NAND Bank or PCCARD Bank. - * This parameter can be one of the following values: - * @arg EXMC_BANK2_NAND: the NAND Bank2 - * @arg EXMC_BANK3_NAND: the NAND Bank3 - * @arg EXMC_BANK4_PCCARD: the PCCARD Bank4 - * @param EXMC_FLAG: the flag of EXMC_SIRx register. - * This parameter can be one of the following values: - * @arg EXMC_FLAG_RISE: Rising egde detection Flag - * @arg EXMC_FLAG_LEVEL: Level detection Flag - * @arg EXMC_FLAG_FALL: Falling egde detection Flag - * @arg EXMC_FLAG_FIFOE: FIFO empty Flag - * @retval The new value of EXMC_FLAG (SET or RESET). - */ -TypeState EXMC_GetBitState(uint32_t EXMC_PCNANDBank, uint32_t EXMC_FLAG) -{ - uint32_t temp_SIR = 0x00000000; - /* the NAND Bank2 */ - if (EXMC_PCNANDBank == EXMC_BANK2_NAND) { - temp_SIR = EXMC_BANK2->SIR2; - } - /* the NAND Bank3 */ - else if (EXMC_PCNANDBank == EXMC_BANK3_NAND) { - temp_SIR = EXMC_BANK3->SIR3; - } - /* the PCCARD Bank4 */ - else { - temp_SIR = EXMC_BANK4->SIR4; - } - - if ((temp_SIR & EXMC_FLAG) != (uint16_t)RESET) { - /* EXMC_FLAG is set */ - return SET; - } else { - /* EXMC_FLAG is reset */ - return RESET; - } -} - -/** - * @brief Clear the bit flag of EXMC_SIRx register. - * @param EXMC_PCNANDBank: specifies the NAND Bank or PCCARD Bank. - * This parameter can be one of the following values: - * @arg EXMC_BANK2_NAND: the NAND Bank2 - * @arg EXMC_BANK3_NAND: the NAND Bank3 - * @arg EXMC_BANK4_PCCARD: the PCCARD Bank4 - * @param EXMC_FLAG: the flag of EXMC_SIRx register. - * This parameter can be any combination of the following values: - * @arg EXMC_FLAG_RISE: Rising egde detection Flag - * @arg EXMC_FLAG_LEVEL: Level detection Flag - * @arg EXMC_FLAG_FALL: Falling egde detection Flag - * @retval None - */ -void EXMC_ClearBitState(uint32_t EXMC_PCNANDBank, uint32_t EXMC_FLAG) -{ - if (EXMC_PCNANDBank == EXMC_BANK2_NAND) { - EXMC_BANK2->SIR2 &= ~EXMC_FLAG; - } else if (EXMC_PCNANDBank == EXMC_BANK3_NAND) { - EXMC_BANK3->SIR3 &= ~EXMC_FLAG; - } - /* EXMC_Bank4_PCCARD*/ - else { - EXMC_BANK4->SIR4 &= ~EXMC_FLAG; - } -} - -/** - * @brief Get the interrupt bit flag. - * @param EXMC_PCNANDBank: specifies the NAND Bank or PCCARD Bank. - * This parameter can be one of the following values: - * @arg EXMC_BANK2_NAND: the NAND Bank2 - * @arg EXMC_BANK3_NAND: the NAND Bank3 - * @arg EXMC_BANK4_PCCARD: the PCCARD Bank4 - * @param EXMC_INT: the interrupt bit flag. - * This parameter can be one of the following values: - * @arg EXMC_INT_RISE: Rising edge detection interrupt - * @arg EXMC_INT_LEVEL: Level edge detection interrupt - * @arg EXMC_INT_FALL: Falling edge detection interrupt - * @retval The new value of EXMC_INT (SET or RESET). - */ -TypeState EXMC_GetIntBitState(uint32_t EXMC_PCNANDBank, uint32_t EXMC_INT) -{ - uint32_t temp_SIR = 0x00000000, temp_INTState = 0x00000000, temp_INTEnable = 0x00000000; - - if (EXMC_PCNANDBank == EXMC_BANK2_NAND) { - temp_SIR = EXMC_BANK2->SIR2; - } else if (EXMC_PCNANDBank == EXMC_BANK3_NAND) { - temp_SIR = EXMC_BANK3->SIR3; - } - /* EXMC_Bank4_PCCARD*/ - else { - temp_SIR = EXMC_BANK4->SIR4; - } - - temp_INTState = temp_SIR & EXMC_INT; - - temp_INTEnable = temp_SIR & (EXMC_INT >> SIR_INTEN_OFFSET); - - if ((temp_INTState != (uint32_t)RESET) && (temp_INTEnable != (uint32_t)RESET)) { - return SET; - } else { - return RESET; - } -} - -/** - * @brief Clear the interrupt bit flag. - * @param EXMC_PCNANDBank: specifies the NAND Bank or PCCARD Bank. - * This parameter can be one of the following values: - * @arg EXMC_BANK2_NAND: the NAND Bank2 - * @arg EXMC_BANK3_NAND: the NAND Bank3 - * @arg EXMC_BANK4_PCCARD: the PCCARD Bank4 - * @param EXMC_INT: the interrupt bit flag. - * This parameter can be any combination of the following values: - * @arg EXMC_FLAG_RISE: Rising edge detection interrupt - * @arg EXMC_FLAG_LEVEL: Level edge detection interrupt - * @arg EXMC_FLAG_FALL: Falling edge detection interrupt - * @retval None - */ -void EXMC_ClearIntBitState(uint32_t EXMC_PCNANDBank, uint32_t EXMC_INT) -{ - if (EXMC_PCNANDBank == EXMC_BANK2_NAND) { - EXMC_BANK2->SIR2 &= ~(EXMC_INT >> SIR_INTEN_OFFSET); - } else if (EXMC_PCNANDBank == EXMC_BANK3_NAND) { - EXMC_BANK3->SIR3 &= ~(EXMC_INT >> SIR_INTEN_OFFSET); - } - /* EXMC_Bank4_PCCARD*/ - else { - EXMC_BANK4->SIR4 &= ~(EXMC_INT >> SIR_INTEN_OFFSET); - } -} - -/** - * @} - */ - -/** - * @} - */ - -/** - * @} - */ diff --git a/bsp/gd32103c-eval/Libraries/GD32F1xx_standard_peripheral/Source/gd32f10x_exti.c b/bsp/gd32103c-eval/Libraries/GD32F1xx_standard_peripheral/Source/gd32f10x_exti.c deleted file mode 100644 index d541e371f1..0000000000 --- a/bsp/gd32103c-eval/Libraries/GD32F1xx_standard_peripheral/Source/gd32f10x_exti.c +++ /dev/null @@ -1,196 +0,0 @@ -/** - ****************************************************************************** - * @brief EXTI functions of the firmware library. - ****************************************************************************** -*/ - -/* Includes ------------------------------------------------------------------*/ -#include "gd32f10x_exti.h" - -/** @addtogroup GD32F10x_Firmware - * @{ - */ - -/** @defgroup EXTI - * @brief EXTI driver modules - * @{ - */ - -/** @defgroup EXTI_Private_Defines - * @{ - */ -/* No interrupt line is selected */ -#define EXTI_LINE_NULL ((uint32_t)0x00000000) - -/* ----------------- EXTI Reset Configuration Registers ------------------ */ -/* The reset value of EXTI_IER */ -#define EXTI_IER_RST ((uint32_t)0x00000000) - -/* The reset value of EXTI_EER */ -#define EXTI_EER_RST ((uint32_t)0x00000000) - -/* The reset value of EXTI_RTE */ -#define EXTI_RTE_RST ((uint32_t)0x00000000) - -/* The reset value of EXTI_FTE */ -#define EXTI_FTE_RST ((uint32_t)0x00000000) - -/* The reset value of EXTI_PD */ -#define EXTI_PD_RST ((uint32_t)0x000FFFFF) - -/** - * @} - */ - -/** @defgroup EXTI_Private_Functions - * @{ - */ - -/** - * @brief Reset the EXTI peripheral registers and the struct EXTI_InitPara. - * @param EXTI_InitParaStruct: the struct EXTI_InitPara pointer. - * @retval None - */ -void EXTI_DeInit(EXTI_InitPara *EXTI_InitParaStruct) -{ - /* Reset the EXTI peripheral registers */ - EXTI->IER = EXTI_IER_RST; - EXTI->EER = EXTI_EER_RST; - EXTI->RTE = EXTI_RTE_RST; - EXTI->FTE = EXTI_FTE_RST; - EXTI->PD = EXTI_PD_RST; - - /* Reset the struct EXTI_InitPara */ - EXTI_InitParaStruct->EXTI_LINE = EXTI_LINE_NULL; - EXTI_InitParaStruct->EXTI_Mode = EXTI_Mode_Interrupt; - EXTI_InitParaStruct->EXTI_Trigger = EXTI_Trigger_Falling; - EXTI_InitParaStruct->EXTI_LINEEnable = DISABLE; -} - -/** - * @brief Initialize the EXTI peripheral registers. - * @param EXTI_InitParaStruct: the struct EXTI_InitPara pointer. - * @retval None - */ -void EXTI_Init(EXTI_InitPara *EXTI_InitParaStruct) -{ - uint32_t temp = 0; - - temp = (uint32_t)EXTI_BASE; - - if (EXTI_InitParaStruct->EXTI_LINEEnable != DISABLE) { - /* Clear Interrupt and Event from EXTI Lines */ - EXTI->IER &= ~EXTI_InitParaStruct->EXTI_LINE; - EXTI->EER &= ~EXTI_InitParaStruct->EXTI_LINE; - - temp += EXTI_InitParaStruct->EXTI_Mode; - - *(__IO uint32_t *) temp |= EXTI_InitParaStruct->EXTI_LINE; - - /* Clear the Rising and Falling edge trigger enable registers */ - EXTI->RTE &= ~EXTI_InitParaStruct->EXTI_LINE; - EXTI->FTE &= ~EXTI_InitParaStruct->EXTI_LINE; - - /* Select the trigger type for the selected EXTI Lines */ - if (EXTI_InitParaStruct->EXTI_Trigger == EXTI_Trigger_Rising_Falling) { - /* Rising and Falling edge trigger are both selected */ - EXTI->RTE |= EXTI_InitParaStruct->EXTI_LINE; - EXTI->FTE |= EXTI_InitParaStruct->EXTI_LINE; - } else { - temp = (uint32_t)EXTI_BASE; - temp += EXTI_InitParaStruct->EXTI_Trigger; - - *(__IO uint32_t *) temp |= EXTI_InitParaStruct->EXTI_LINE; - } - } else { - temp += EXTI_InitParaStruct->EXTI_Mode; - - /* Disable the selected EXTI lines */ - *(__IO uint32_t *) temp &= ~EXTI_InitParaStruct->EXTI_LINE; - } -} - -/** - * @brief Activate the software interrupt or event request of the selected EXTI Lines. - * @param EXTI_LINE: the selected EXTI lines. - * This parameter can be any combination of EXTI_LINEx where x can be (0..19). - * @retval None - */ -void EXTI_SWINT_Enable(uint32_t EXTI_LINE) -{ - /* Enable the software interrupt or event request of the selected EXTI Lines */ - EXTI->SIE |= EXTI_LINE; -} - -/** - * @brief Get the bit flag of the selected EXTI lines. - * @param EXTI_LINE: the selected EXTI lines. - * This parameter can be any combination of EXTI_LINEx where x can be (0..19). - * @retval The new value of EXTI_LINE (SET or RESET). - */ -TypeState EXTI_GetBitState(uint32_t EXTI_LINE) -{ - /* Check and get the selected EXTI lines flag */ - if ((EXTI->PD & EXTI_LINE) != (uint32_t)RESET) { - /* EXTI_LINE bit is SET */ - return SET; - } else { - /* EXTI_LINE bit is RESET */ - return RESET; - } -} - -/** - * @brief Clear the bit flag of the selected EXTI lines. - * @param EXTI_LINE: the selected EXTI lines. - * This parameter can be any combination of EXTI_LINEx where x can be (0..19). - * @retval None - */ -void EXTI_ClearBitState(uint32_t EXTI_LINE) -{ - /* Clear the bit flag of the selected EXTI lines */ - EXTI->PD = EXTI_LINE; -} - -/** - * @brief Get the interrupt bit flag of the selected EXTI lines.. - * @param EXTI_LINE: the selected EXTI lines. - * This parameter can be any combination of EXTI_LINEx where x can be (0..19). - * @retval The new value of EXTI_LINE (SET or RESET). - */ -TypeState EXTI_GetIntBitState(uint32_t EXTI_LINE) -{ - /* Check and get the interrupt source is set or not */ - if (((EXTI->PD & EXTI_LINE) != (uint32_t)RESET) && ((EXTI->IER & EXTI_LINE) != (uint32_t)RESET)) { - /* The interrupt bit of EXTI_LINE is SET */ - return SET; - } else { - /* The interrupt bit of EXTI_LINE is RESET */ - return RESET; - } -} - -/** - * @brief Clear the interrupt bit flag of the selected EXTI lines. - * @param EXTI_LINE: the selected EXTI lines. - * This parameter can be any combination of EXTI_LINEx where x can be (0..19). - * @retval None - */ -void EXTI_ClearIntBitState(uint32_t EXTI_LINE) -{ - /* Clear the interrupt bit flag of the selected EXTI lines */ - EXTI->PD = EXTI_LINE; -} - -/** - * @} - */ - -/** - * @} - */ - -/** - * @} - */ - diff --git a/bsp/gd32103c-eval/Libraries/GD32F1xx_standard_peripheral/Source/gd32f10x_fmc.c b/bsp/gd32103c-eval/Libraries/GD32F1xx_standard_peripheral/Source/gd32f10x_fmc.c deleted file mode 100644 index 68d5a283a4..0000000000 --- a/bsp/gd32103c-eval/Libraries/GD32F1xx_standard_peripheral/Source/gd32f10x_fmc.c +++ /dev/null @@ -1,1166 +0,0 @@ -/** - ****************************************************************************** - * @brief FMC functions of the firmware library. - ******************************************************************************/ - -/* Includes ------------------------------------------------------------------*/ -#include "gd32f10x_fmc.h" - -/** @addtogroup GD32F10x_Firmware - * @{ - */ - -/** @defgroup FMC - * @brief FMC driver modules - * @{ - */ - -/** @defgroup FMC_Private_Functions - * @{ - */ - -/** @defgroup FMC_Group1 FMC Memory Programming functions - * @brief FMC Memory Programming functions - * -@verbatim - =============================================================================== - ##### FMC Memory Programming functions ##### - =============================================================================== - - [..] The FMC Memory Programming functions, includes the following functions: - (+) void FMC_Unlock(void); - (+) void FMC_UnlockBank1(void); - (+) void FMC_UnlockBank2(void); - (+) void FMC_Lock(void); - (+) void FMC_LockBank1(void) - (+) void FMC_LockBank2(void) - (+) FMC_State FMC_ErasePage(uint32_t Page_Address); - (+) FMC_State FMC_MassErase(void); - (+) FMC_State FMC_MassBank1Erase(void) - (+) FMC_State FMC_MassBank2Erase(void) - (+) FMC_State FMC_ProgramWord(uint32_t Address, uint32_t Data); - [..] Any operation of erase or program should follow these steps: - - (#) Call the FMC_Unlock() function to unlock the FMC operation - (#) Call erase or program data - (#) Call the FMC_Lock() to lock the FMC operation - -@endverbatim - * @{ - */ -/** - * @brief Unlock the main FMC operation. - * @param None - * @retval None - */ -void FMC_Unlock(void) -{ - if ((FMC->CMR & FMC_CMR_LK) != RESET) { - /* Write the FMC key */ - FMC->UKEYR = FMC_KEY1; - FMC->UKEYR = FMC_KEY2; - } - if (FMC_SIZE > FMC_BANK1_SIZE) { - /* Authorize the FPEC of Bank2 Access */ - if ((FMC->CMR2 & FMC_CMR_LK) != RESET) { - FMC->UKEYR2 = FMC_KEY1; - FMC->UKEYR2 = FMC_KEY2; - } - } -} - -/** - * @brief Unlocks the FMC Bank1 Program Erase Controller. - * @note This function can be used for all GD32F10x devices. - * - For GD32F10X_XD and GD32F10X_CL devices this function unlocks Bank1. - * - For all other devices it unlocks Bank1 and it is - * equivalent to FLASH_Unlock function. - * @param None - * @retval None - */ -void FMC_UnlockB1(void) -{ - /* Authorize the FPEC of Bank1 Access */ - if ((FMC->CMR & FMC_CMR_LK) != RESET) { - FMC->UKEYR = FMC_KEY1; - FMC->UKEYR = FMC_KEY2; - } -} - -/** - * @brief Unlocks the FMC Bank2 Program Erase Controller. - * @note This function can be used for GD32F10X_XD and GD32F10X_CL density devices. - * @param None - * @retval None - */ -#if defined GD32F10X_XD || defined GD32F10X_CL -void FMC_UnlockB2(void) -{ - /* Authorize the FPEC of Bank2 Access */ - if ((FMC->CMR2 & FMC_CMR_LK) != RESET) { - FMC->UKEYR2 = FMC_KEY1; - FMC->UKEYR2 = FMC_KEY2; - } -} -#endif /* GD32F10X_XD and GD32F10X_CL */ - -/** - * @brief Lock the main FMC operation. - * @param None - * @retval None - */ -void FMC_Lock(void) -{ - /* Set the LOCK bit*/ - FMC->CMR |= FMC_CMR_LK; - - if (FMC_SIZE > FMC_BANK1_SIZE) { - /* Set the Lock Bit to lock the FPEC and the CR of Bank2 */ - FMC->CMR2 |= FMC_CMR_LK; - } -} - -/** - * @brief Locks the FMC Bank1 Program Erase Controller. - * @note this function can be used for all GD32F10X devices. - * - For GD32F10X_XD and GD32F10X_CL devices this function Locks Bank1. - * - For all other devices it Locks Bank1 and it is equivalent - * to FMC_Lock function. - * @param None - * @retval None - */ -void FMC_LockB1(void) -{ - /* Set the Lock Bit to lock the FPEC and the CMR of Bank1 */ - FMC->CMR |= FMC_CMR_LK; -} - -/** - * @brief Locks the FMC Bank2 Program Erase Controller. - * @note This function can be used for GD32F10X_XD and GD32F10X_CL density devices. - * @param None - * @retval None - */ -#if defined GD32F10X_XD || defined GD32F10X_CL -void FMC_LockB2(void) -{ - /* Set the Lock Bit to lock the FPEC and the CMR of Bank2 */ - FMC->CMR2 |= FMC_CMR_LK; -} -#endif - -/** - * @brief Erase a page. - * @param Page_Address: The page address to be erased. - * @retval FMC state: FMC_READY, FMC_BSY, FMC_WRPERR, FMC_PGERR or FMC_TIMEOUT_ERR. - */ -FMC_State FMC_ErasePage(uint32_t Page_Address) -{ - if (FMC_SIZE > FMC_BANK1_SIZE) { - FMC_State temp_state = FMC_B1_WaitReady(FMC_TIMEOUT_COUNT); - if (Page_Address < FMC_B1_END_ADDRESS) { - /* Wait for last operation to be completed */ - FMC_State temp_state = FMC_B1_WaitReady(FMC_TIMEOUT_COUNT); - - if (temp_state == FMC_READY) { - FMC->CMR |= FMC_CMR_PE; - FMC->AR = Page_Address; - FMC->CMR |= FMC_CMR_START; - - /* Wait for the FMC ready */ - temp_state = FMC_B1_WaitReady(FMC_TIMEOUT_COUNT); - - /* Reset the PE bit */ - FMC->CMR &= ~FMC_CMR_PE; - } - } else { - /* Wait for last operation to be completed */ - FMC_State temp_state = FMC_B2_WaitReady(FMC_TIMEOUT_COUNT); - - if (temp_state == FMC_READY) { - FMC->CMR2 |= FMC_CMR_PE; - FMC->AR2 = Page_Address; - if (FMC->OPTR & FMC_OPTR_PLEVEL1) { - FMC->AR = Page_Address; - } - FMC->CMR2 |= FMC_CMR_START; - - /* Wait for the FMC ready */ - temp_state = FMC_B2_WaitReady(FMC_TIMEOUT_COUNT); - - /* Reset the PE bit */ - FMC->CMR2 &= ~FMC_CMR_PE; - } - } - /* Return the FMC state */ - return temp_state; - } - - else { - FMC_State temp_state = FMC_WaitReady(FMC_TIMEOUT_COUNT); - - if (temp_state == FMC_READY) { - /* Start page erase */ - FMC->CMR |= FMC_CMR_PE; - FMC->AR = Page_Address; - FMC->CMR |= FMC_CMR_START; - - /* Wait for the FMC ready */ - temp_state = FMC_WaitReady(FMC_TIMEOUT_COUNT); - - /* Reset the PE bit */ - FMC->CMR &= ~FMC_CMR_PE; - } - /* Return the FMC state */ - return temp_state; - } -} - -/** - * @brief Erase all main FMC. - * @param None - * @retval FMC state: FMC_READY, FMC_BSY, FMC_WRPERR, FMC_PGERR or FMC_TIMEOUT_ERR. - */ -FMC_State FMC_MassErase(void) -{ - if (FMC_SIZE > FMC_BANK1_SIZE) { - /* Wait for last operation to be completed */ - FMC_State temp_state = FMC_B1_WaitReady(FMC_TIMEOUT_COUNT); - if (temp_state == FMC_READY) { - /* Start chip erase */ - FMC->CMR |= FMC_CMR_ME; - FMC->CMR |= FMC_CMR_START; - - /* Wait for the FMC ready */ - temp_state = FMC_B1_WaitReady(FMC_TIMEOUT_COUNT); - - /* Reset the MER bit */ - FMC->CMR &= ~FMC_CMR_ME; - } - temp_state = FMC_B2_WaitReady(FMC_TIMEOUT_COUNT); - if (temp_state == FMC_READY) { - /* Start chip erase */ - FMC->CMR2 |= FMC_CMR_ME; - FMC->CMR2 |= FMC_CMR_START; - - /* Wait for the FMC ready */ - temp_state = FMC_B2_WaitReady(FMC_TIMEOUT_COUNT); - - /* Reset the MER bit */ - FMC->CMR2 &= ~FMC_CMR_ME; - } - /* Return the FMC state */ - return temp_state; - } else { - FMC_State temp_state = FMC_WaitReady(FMC_TIMEOUT_COUNT); - - if (temp_state == FMC_READY) { - /* Start chip erase */ - FMC->CMR |= FMC_CMR_ME; - FMC->CMR |= FMC_CMR_START; - - /* Wait for the FMC ready */ - temp_state = FMC_WaitReady(FMC_TIMEOUT_COUNT); - - /* Reset the MER bit */ - FMC->CMR &= ~FMC_CMR_ME; - } - /* Return the FMC state */ - return temp_state; - } -} - -/** - * @brief Erases all Bank1 FMC pages. - * @note This function can be used for all GD32F10x devices. - * - For GD32F10X_XD and GD32F10X_CL devices this function erases all Bank1 pages. - * - For all other devices it erases all Bank1 pages and it is equivalent - * to FLASH_EraseAllPages function. - * @param None - * @retval FLASH Status: FMC state: FMC_READY, FMC_BSY, FMC_WRPERR, FMC_PGERR or FMC_TIMEOUT_ERR. - */ -FMC_State FMC_MassB1Erase(void) -{ - FMC_State temp_state = FMC_B1_WaitReady(FMC_TIMEOUT_COUNT); - - if (temp_state == FMC_READY) { - /* Start chip erase */ - FMC->CMR |= FMC_CMR_ME; - FMC->CMR |= FMC_CMR_START; - - /* Wait for the FMC ready */ - temp_state = FMC_B1_WaitReady(FMC_TIMEOUT_COUNT); - - /* Reset the MER bit */ - FMC->CMR &= ~FMC_CMR_ME; - } - /* Return the Erase Status */ - return temp_state; -} - -/** - * @brief Erases all Bank2 FMC pages. - * @note This function can be used for GD32F10X_XD and GD32F10X_CL density devices. - * @param None - * @retval FMC Status: FMC state: FMC_READY, FMC_BSY, FMC_WRPERR, FMC_PGERR or FMC_TIMEOUT_ERR. - */ - -FMC_State FMC_MassB2Erase(void) -{ - FMC_State temp_state = FMC_B2_WaitReady(FMC_TIMEOUT_COUNT); - - if (temp_state == FMC_READY) { - /* Start chip erase */ - FMC->CMR2 |= FMC_CMR_ME; - FMC->CMR2 |= FMC_CMR_START; - - /* Wait for the FMC ready */ - temp_state = FMC_B2_WaitReady(FMC_TIMEOUT_COUNT); - - /* Reset the MER bit */ - FMC->CMR2 &= ~FMC_CMR_ME; - } - /* Return the Erase Status */ - return temp_state; -} - - -/** - * @brief Program a word at the corresponding address. - * @param Address: The address to be programmed. - * @param Data: The data to be programmed. - * @retval FMC state: FMC_READY, FMC_BSY, FMC_WRPERR, FMC_PGERR or FMC_TIMEOUT_ERR. - */ -FMC_State FMC_ProgramWord(uint32_t Address, uint32_t Data) -{ - if (FMC_SIZE > FMC_BANK1_SIZE) { - FMC_State temp_state = FMC_B1_WaitReady(FMC_TIMEOUT_COUNT); - if (Address < FMC_B1_END_ADDRESS) { - FMC_State temp_state = FMC_B1_WaitReady(FMC_TIMEOUT_COUNT); - - if (temp_state == FMC_READY) { - /* Set the PG bit to start program */ - FMC->CMR |= FMC_CMR_PG; - - *(__IO uint32_t *)Address = Data; - - /* Wait for the FMC ready */ - temp_state = FMC_WaitReady(FMC_TIMEOUT_COUNT); - - /* Reset the PG bit */ - FMC->CMR &= ~FMC_CMR_PG; - } - } else { - FMC_State temp_state = FMC_B2_WaitReady(FMC_TIMEOUT_COUNT); - - if (temp_state == FMC_READY) { - /* Set the PG bit to start program */ - FMC->CMR2 |= FMC_CMR_PG; - - *(__IO uint32_t *)Address = Data; - - /* Wait for the FMC ready */ - temp_state = FMC_B2_WaitReady(FMC_TIMEOUT_COUNT); - - /* Reset the PG bit */ - FMC->CMR2 &= ~FMC_CMR_PG; - } - } - - /* Return the FMC state */ - return temp_state; - } else { - - FMC_State temp_state = FMC_WaitReady(FMC_TIMEOUT_COUNT); - - if (temp_state == FMC_READY) { - /* Set the PG bit to start program */ - FMC->CMR |= FMC_CMR_PG; - - *(__IO uint32_t *)Address = Data; - - /* Wait for the FMC ready */ - temp_state = FMC_WaitReady(FMC_TIMEOUT_COUNT); - - /* Reset the PG bit */ - FMC->CMR &= ~FMC_CMR_PG; - } - - /* Return the FMC state */ - return temp_state; - - } - -} - -/** - * @} - */ - -/** @defgroup FMC_Group2 Option Bytes Programming functions - * @brief Option Bytes Programming functions - * -@verbatim - =============================================================================== - ##### Option Bytes Programming functions ##### - =============================================================================== - - [..] The FMC_Option Bytes Programming_functions, includes the following functions: - (+) void FMC_OB_Unlock(void); - (+) void FMC_OB_Lock(void); - (+) void FMC_OB_Reset(void); - (+) FMC_State FMC_OB_Erase(void); - (+) FMC_State FMC_OB_WRPConfig(uint32_t OB_WRP); - (+) FMC_State FMC_OB_RDPConfig(uint8_t OB_RDP); - (+) FMC_State FMC_OB_UserConfig(uint8_t OB_IWDG, uint8_t OB_DEEPSLEEP, uint8_t OB_STDBY); - (+) FMC_State FMC_OB_BOOTConfig(uint8_t OB_BOOT); - (+) FMC_State FMC_OB_WriteUser(uint8_t OB_USER); - (+) FMC_ProgramOptionByteData(uint32_t Address, uint8_t Data); - (+) uint8_t FMC_OB_GetUser(void); - (+) uint32_t FMC_OB_GetWRP(void); - (+) FlagStatus FMC_OB_GetRDP(void); - [..] Any operation of erase or program should follow these steps: - - (#) Call the FMC_OB_Unlock() function to enable the Option Bytes registers access - - (#) Call one or several functions to program the desired option bytes - (++) FMC_State FMC_OB_RDPConfig(uint8_t OB_RDP) => to set the desired read Protection Level - (++) FMC_State FMC_OB_WRPConfig(uint32_t OB_WRP, FunctionalState NewState) - => to Enable/Disable the desired sector write protection - (++) FMC_State FMC_OB_UserConfig(uint8_t OB_IWDG, uint8_t OB_DEEPSLEEP, uint8_t OB_STDBY) - => to configure the user option Bytes: IWDG, DEEPSLEEP and the Standby. - (++) FMC_State FMC_OB_BOOTConfig(uint8_t OB_BOOT1) - => to set or reset BOOT1 - (++) FMC_State FMC_OB_VDDAConfig(uint8_t OB_VDDA_ANALOG) - => to enable or disable the VDDA Analog Monitoring - (++) You can write all User Options bytes at once using a single function - by calling FMC_State FMC_OB_WriteUser(uint8_t OB_USER) - (++) FMC_ProgramOptionByteData(uint32_t Address, uint8_t Data) to program the - two half word in the option bytes - - (#) Once all needed option bytes to be programmed are correctly written, call the - FMC_OB_Launch(void) function to launch the Option Bytes programming process. - - (#) Call the FMC_OB_Lock() to disable the Option Bytes registers access (recommended - to protect the option Bytes against possible unwanted operations) - -@endverbatim - * @{ - */ - -/** - * @brief Unlock the option byte operation - * @param None - * @retval None - */ -void FMC_OB_Unlock(void) -{ - if ((FMC->CMR & FMC_CMR_OBWE) == RESET) { - /* Write the FMC key */ - FMC->OBKEYR = FMC_KEY1; - FMC->OBKEYR = FMC_KEY2; - } -} - -/** - * @brief Lock the option byte operation. - * @param None - * @retval None - */ -void FMC_OB_Lock(void) -{ - /* Reset the OBWE bit */ - FMC->CMR &= ~FMC_CMR_OBWE; -} - -/** - * @brief Generate a system reset to reload the option byte. - * @param None - * @retval None - */ -void FMC_OB_Reset(void) -{ - /* Set the OPTR bit */ - FMC->CMR |= FMC_CMR_OPTR; -} - -/** - * @brief Erase the FMC option byte. - * @param None - * @retval FMC state: FMC_READY, FMC_BSY, FMC_WRPERR, FMC_PGERR or FMC_TIMEOUT_ERR. - */ -FMC_State FMC_OB_Erase(void) -{ - uint16_t temp_rdp = RDP_LEVEL_0; - - FMC_State temp_state = FMC_WaitReady(FMC_TIMEOUT_COUNT); - - /* Check the ReadOut Protection Option Byte */ - if (FMC_OB_GetRDP() != RESET) { - temp_rdp = 0x00; - } - - if (temp_state == FMC_READY) { - /* Start erase the option byte */ - FMC->CMR |= FMC_CMR_OBER; - FMC->CMR |= FMC_CMR_START; - - /* Wait for the FMC ready */ - temp_state = FMC_WaitReady(FMC_TIMEOUT_COUNT); - - if (temp_state == FMC_READY) { - /* Reset the OPER bit */ - FMC->CMR &= ~FMC_CMR_OBER; - - /* Set the OBPG bit */ - FMC->CMR |= FMC_CMR_OBPG; - - /* Set default RDP level */ - OB->RDP = (uint16_t)temp_rdp; - - /* Wait for the FMC ready */ - temp_state = FMC_WaitReady(FMC_TIMEOUT_COUNT); - - if (temp_state != FMC_TIMEOUT_ERR) { - /* Reset the OBPG bit */ - FMC->CMR &= ~FMC_CMR_OBPG; - } - } else { - if (temp_state != FMC_TIMEOUT_ERR) { - /* Reset the OBPG bit */ - FMC->CMR &= ~FMC_CMR_OBPG; - } - } - } - /* Return the FMC state */ - return temp_state; -} - -/** - * @brief Program Write protect Byte - * @param OB_WRP: specify the address of the pages to be write protected. - * The legal parameter can be: - * @arg WRP_SECTOR0 ... WRP_SECTOR31 - * @arg WRP_ALLSECTORS - * @retval FMC state: FMC_READY, FMC_BSY, FMC_WRPERR, FMC_PGERR or FMC_TIMEOUT_ERR. - */ -FMC_State FMC_OB_EnableWRP(uint32_t OB_WRP) -{ - uint16_t temp_WRP0, temp_WRP1, temp_WRP2, temp_WRP3; - - FMC_State temp_state = FMC_WaitReady(FMC_TIMEOUT_COUNT); - - OB_WRP = (uint32_t)(~OB_WRP); - temp_WRP0 = (uint16_t)(OB_WRP & OB_WRP0_WRP0); - temp_WRP1 = (uint16_t)((OB_WRP & OB_WRP0_nWRP0) >> 8); - temp_WRP2 = (uint16_t)((OB_WRP & OB_WRP1_WRP1) >> 16); - temp_WRP3 = (uint16_t)((OB_WRP & OB_WRP1_nWRP1) >> 24); - - if (temp_state == FMC_READY) { - FMC->OBKEYR = FMC_KEY1; - FMC->OBKEYR = FMC_KEY2; - /* Set the OBPG bit*/ - FMC->CMR |= FMC_CMR_OBPG; - - if (temp_WRP0 != 0xFF) { - OB->WRP0 = temp_WRP0; - - /* Wait for the FMC ready */ - temp_state = FMC_WaitReady(FMC_TIMEOUT_COUNT); - } - if ((temp_state == FMC_READY) && (temp_WRP1 != 0xFF)) { - OB->WRP1 = temp_WRP1; - - /* Wait for the FMC ready */ - temp_state = FMC_WaitReady(FMC_TIMEOUT_COUNT); - } - if ((temp_state == FMC_READY) && (temp_WRP2 != 0xFF)) { - OB->WRP2 = temp_WRP2; - - /* Wait for the FMC ready */ - temp_state = FMC_WaitReady(FMC_TIMEOUT_COUNT); - } - if ((temp_state == FMC_READY) && (temp_WRP3 != 0xFF)) { - OB->WRP3 = temp_WRP3; - - /* Wait for the FMC ready */ - temp_state = FMC_WaitReady(FMC_TIMEOUT_COUNT); - } - if (temp_state != FMC_TIMEOUT_ERR) { - /* Reset the OBPG bit */ - FMC->CMR &= ~FMC_CMR_OBPG; - } - } - /* Return the FMC state */ - return temp_state; -} - -/** - * @brief Enable or disable the read out protection,this function erases all option bytes. - * @param NewValue: ENABLE or DISABLE. - * @retval FMC state: FMC_READY, FMC_WRPERR, FMC_PGERR or FMC_TIMEOUT_ERR. - */ -FMC_State FMC_ReadOutProtection(TypeState NewValue) -{ - FMC_State temp_state = FMC_READY; - /* Wait for the FMC ready */ - temp_state = FMC_WaitReady(FMC_TIMEOUT_COUNT); - if (temp_state == FMC_READY) { - /* Unlock option bytes */ - FMC->OBKEYR = FMC_KEY1; - FMC->OBKEYR = FMC_KEY2; - while ((FMC->CMR & FMC_CMR_OBWE) != FMC_CMR_OBWE) - {} - FMC->CMR |= FMC_CMR_OBER; - FMC->CMR |= FMC_CMR_START; - /* Wait for the FMC ready */ - temp_state = FMC_WaitReady(FMC_TIMEOUT_COUNT); - if (temp_state == FMC_READY) { - /* Disable the OBER Bit */ - FMC->CMR &= ~FMC_CMR_OBER ; - /* Enable the OBPG Bit */ - FMC->CMR |= FMC_CMR_OBPG; - if (NewValue != DISABLE) { - OB->RDP = 0x00; - } else { - OB->RDP = RDP_LEVEL_0; - } - /* Wait for the FMC ready */ - temp_state = FMC_WaitReady(FMC_TIMEOUT_COUNT); - - if (temp_state != FMC_TIMEOUT_ERR) { - /* Enable the OBPG Bit */ - FMC->CMR &= ~FMC_CMR_OBPG ; - } - } else { - if (temp_state != FMC_TIMEOUT_ERR) { - /* Disable the OBER Bit */ - FMC->CMR &= ~FMC_CMR_OBER ; - } - } - } - /* Return the FMC state */ - return temp_state; -} - -/** - * @brief Config the Read Out Protection bit. - * @param FMC_ReadProtection_Level: The Read Out Protection level. - * This parameter can be: - * @arg RDP_LEVEL_0: No protection - * @arg RDP_LEVEL_1: Read Outprotection of the memory - * @retval FMC state: FMC_READY, FMC_BSY, FMC_WRPERR, FMC_PGERR or FMC_TIMEOUT_ERR. - */ -FMC_State FMC_OB_RDPConfig(uint8_t OB_RDP) -{ - FMC_State temp_state = FMC_WaitReady(FMC_TIMEOUT_COUNT); - - if (temp_state == FMC_READY) { - FMC->CMR |= FMC_CMR_OBER; - FMC->CMR |= FMC_CMR_START; - - /* Wait for the FMC ready */ - temp_state = FMC_WaitReady(FMC_TIMEOUT_COUNT); - - if (temp_state == FMC_READY) { - /* Reset the OBER bit */ - FMC->CMR &= ~FMC_CMR_OBER; - - /* Start the Option Bytes Programming */ - FMC->CMR |= FMC_CMR_OBPG; - - OB->RDP = OB_RDP; - - /* Wait for the FMC ready */ - temp_state = FMC_WaitReady(FMC_TIMEOUT_COUNT); - - if (temp_state != FMC_TIMEOUT_ERR) { - /* Reset the OBPG bit */ - FMC->CMR &= ~FMC_CMR_OBPG; - } - } else { - if (temp_state != FMC_TIMEOUT_ERR) { - /* Reset the OBER Bit */ - FMC->CMR &= ~FMC_CMR_OBER; - } - } - } - /* Return the FMC state */ - return temp_state; -} - -/** - * @brief Program the FMC User Option Byte: IWDG_SW / RST_DEEPSLEEP / RST_STDBY. - * @param OB_IWDG: Config the WDG mode - * @arg OB_IWDG_SW: Software WDG selected - * @arg OB_IWDG_HW: Hardware WDG selected - * @param OB_DEEPSLEEP: Config Reset event when entering DEEPSLEEP mode. - * @arg OB_DEEPSLEEP_NORST: No reset generated when entering in DEEPSLEEP - * @arg OB_DEEPSLEEP_RST: Reset generated when entering in DEEPSLEEP - * @param OB_STDBY: Config Reset event when entering Standby mode. - * @arg OB_STDBY_NORST: No reset generated when entering in STANDBY - * @arg OB_STDBY_RST: Reset generated when entering in STANDBY - * @retval FMC state: FMC_READY, FMC_BSY, FMC_WRPERR, FMC_PGERR or FMC_TIMEOUT_ERR. - */ -FMC_State FMC_OB_UserConfig(uint8_t OB_IWDG, uint8_t OB_DEEPSLEEP, uint8_t OB_STDBY) -{ - FMC_State temp_state = FMC_WaitReady(FMC_TIMEOUT_COUNT); - - if (temp_state == FMC_READY) { - /* Set the OBPG bit*/ - FMC->CMR |= FMC_CMR_OBPG; - - OB->USER = (uint16_t)((uint16_t)(OB_IWDG | OB_DEEPSLEEP) | (uint16_t)(OB_STDBY | 0xF8)); - - /* Wait for the FMC ready */ - temp_state = FMC_WaitReady(FMC_TIMEOUT_COUNT); - - if (temp_state != FMC_TIMEOUT_ERR) { - /* Reset the OBPG bit */ - FMC->CMR &= ~FMC_CMR_OBPG; - } - } - /* Return the FMC state */ - return temp_state; -} - -/** - * @brief Program the BOOT option bit. - * @param OB_BOOT: The legal parameter can be one of the following value: - * @arg OB_BOOT_B1:Start up from Bank1 - * @arg OB_BOOT_B2:Start up from Bank2 - * @retval FMC state: FMC_READY, FMC_BSY, FMC_WRPERR, FMC_PGERR or FMC_TIMEOUT_ERR. - */ -FMC_State FMC_OB_BOOTConfig(uint8_t OB_BOOT) -{ - FMC_State temp_state = FMC_WaitReady(FMC_TIMEOUT_COUNT); - FMC->OBKEYR = FMC_KEY1; - FMC->OBKEYR = FMC_KEY2; - - if (temp_state == FMC_READY) { - /* Set the OBPG bit*/ - FMC->CMR |= FMC_CMR_OBPG; - - if (OB_BOOT == OB_BOOT_B1) { - OB->USER |= OB_USER_BFB2; - } else { - OB->USER &= (uint16_t)(~(uint16_t)(OB_USER_BFB2)); - } - - /* Wait for the FMC ready */ - temp_state = FMC_WaitReady(FMC_TIMEOUT_COUNT); - - if (temp_state != FMC_TIMEOUT_ERR) { - /* Reset the OBPG bit */ - FMC->CMR &= ~FMC_CMR_OBPG; - } - } - /* Return the FMC state */ - return temp_state; -} - -/** - * @brief Program the FMC User Option Byte. - * @param OB_USER: Select all user option byte - * The legal parameter is one of the following values: - * @arg OB_IWDG_SW - * @arg OB_IWDG_HW - * @arg OB_DEEPSLEEP_NORST - * @arg OB_DEEPSLEEP_RST - * @arg OB_STDBY_NORST - * @arg OB_STDBY_RST - * @arg OB_BOOT_B1 - * @arg OB_BOOT_B2 - * @retval FMC state: FMC_READY, FMC_BSY, FMC_WRPERR, FMC_PGERR or FMC_TIMEOUT_ERR. - */ -FMC_State FMC_OB_WriteUser(uint8_t OB_USER) -{ - FMC_State temp_state = FMC_WaitReady(FMC_TIMEOUT_COUNT); - - if (temp_state == FMC_READY) { - /* Set the OBPG bit */ - FMC->CMR |= FMC_CMR_OBPG; - - OB->USER = OB_USER | 0xf0; - - /* Wait for the FMC ready */ - temp_state = FMC_WaitReady(FMC_TIMEOUT_COUNT); - - if (temp_state != FMC_TIMEOUT_ERR) { - /* Reset the OBPG bit */ - FMC->CMR &= ~FMC_CMR_OBPG; - } - } - /* Return the FMC state */ - return temp_state; -} - -/** - * @brief Program Option Byte Data. - * @param Address: The Option Byte address to be programmed. - * The legal parameter can be 0x1FFFF804 or 0x1FFFF806. - * @param Data: The Byte to be programmed. - * @retval FMC state: FMC_READY, FMC_BSY, FMC_WRPERR, FMC_PGERR or FMC_TIMEOUT_ERR. - */ -FMC_State FMC_ProgramOptionByteData(uint32_t Address, uint8_t Data) -{ - FMC_State temp_state = FMC_WaitReady(FMC_TIMEOUT_COUNT); - - if (temp_state == FMC_READY) { - /* SET the OPTPG bit */ - FMC->CMR |= FMC_CMR_OBPG; - *(__IO uint16_t *)Address = Data; - - /* Wait for the FMC ready */ - temp_state = FMC_WaitReady(FMC_TIMEOUT_COUNT); - - if (temp_state != FMC_TIMEOUT_ERR) { - /* Reset the OPTPG bit */ - FMC->CMR &= ~FMC_CMR_OBPG; - } - } - /* Return the FMC state */ - return temp_state; -} - -/** - * @brief Get the FMC User Option Byte. - * @param None - * @retval The FMC User Option Byte. - */ -uint8_t FMC_OB_GetUser(void) -{ - return (uint8_t)(FMC->OPTR >> 8); -} - -/** - * @brief Get the FMC Write Protection Option Byte. - * @param None - * @retval The FMC Write Protection Option Byte - */ -uint32_t FMC_OB_GetWRP(void) -{ - return (uint32_t)(FMC->WPR); -} - -/** - * @brief Check whether the FMC Read out Protection Status is SET or RESET. - * @param None - * @retval FMC ReadOut Protection state - */ -TypeState FMC_OB_GetRDP(void) -{ - TypeState RDPState = RESET; - - if ((uint8_t)(FMC->OPTR & (FMC_OPTR_PLEVEL1)) != RESET) { - RDPState = SET; - } else { - RDPState = RESET; - } - return RDPState; -} - -/** - * @} - */ - -/** @defgroup FMC_Group3 Interrupts and flags management functions - * @brief Interrupts and flags management functions - * -@verbatim - =============================================================================== - ##### Interrupts and flags management functions ##### - =============================================================================== - -@endverbatim - * @{ - */ - -/** - * @brief Enable or disable the corresponding FMC interrupt source. - * @param FMC_INT: The FMC interrupt source to be enabled or disabled. - * This parameter can be any combination of the following values: - * @arg FMC_INT_EOP: FMC end of programming Interrupt - * @arg FMC_INT_ERR: FMC Error Interrupt - * @arg FMC_INT_B2_EOP: FMC end of programming Interrupt - * @arg FMC_INT_B2_ERR: FMC Error Interrupt - * @param NewValue: ENABLE or DISABLE. - * @retval None - */ -void FMC_INTConfig(uint32_t FMC_INT, TypeState NewValue) -{ - - if (FMC_SIZE > FMC_BANK1_SIZE) { - if ((FMC_INT & 0x80000000) != 0x0) { - if (NewValue != DISABLE) { - /* Enable the interrupt sources */ - FMC->CMR2 |= (FMC_INT & 0x7fffffff); - } else { - /* Disable the interrupt sources */ - FMC->CMR2 &= ~(uint32_t)(FMC_INT & 0x7fffffff); - } - } else { - if (NewValue != DISABLE) { - /* Enable the interrupt sources */ - FMC->CMR |= FMC_INT; - } else { - /* Disable the interrupt sources */ - FMC->CMR &= ~(uint32_t)FMC_INT; - } - } - } else { - if (NewValue != DISABLE) { - /* Enable the interrupt sources */ - FMC->CMR |= FMC_INT; - } else { - /* Disable the interrupt sources */ - FMC->CMR &= ~(uint32_t)FMC_INT; - } - } -} - -/** - * @brief Checks whether the FMC flag is SET or RESET. - * @param FMC_FLAG: the corresponding FMC flag. - * the legal parameter can be: - * @arg FMC_FLAG_BSY: FMC BUSY flag - * @arg FMC_FLAG_PERR: FMC Programming error flag flag - * @arg FMC_FLAG_WERR: FMC Write protection error flag - * @arg FMC_FLAG_EOP: FMC End of Programming flag - * @arg FMC_FLAG_OPTER: FMC option byte error flag - * @retval The state of the FMC flag. - */ -TypeState FMC_GetBitState(uint32_t FMC_FLAG) -{ - if (FMC_SIZE > FMC_BANK1_SIZE) { - /* Check the parameters */ - if (FMC_FLAG == FMC_FLAG_OPTERR) { - if ((FMC->OPTR & FMC_FLAG_OPTERR) != (uint32_t)RESET) { - return SET; - } else { - return RESET; - } - } else { - if ((FMC_FLAG & 0x80000000) != 0x0) { - if ((FMC->CSR2 & FMC_FLAG) != (uint32_t)RESET) { - return SET; - } else { - return RESET; - } - } else { - if ((FMC->CSR & FMC_FLAG) != (uint32_t)RESET) { - return SET; - } else { - return RESET; - } - } - } - } else { - if (FMC_FLAG == FMC_FLAG_OPTERR) { - if ((FMC->OPTR & FMC_FLAG_OPTERR) != (uint32_t)RESET) { - return SET; - } else { - return RESET; - } - } else { - if ((FMC->CSR & FMC_FLAG) != (uint32_t)RESET) { - return SET; - } - /* Return the state of corresponding FMC flag */ - else { - return RESET; - } - } - } -} - -/** - * @brief Clear the FMC pending flag. - * @param FMC_FLAG: clear the corresponding FMC flag. - * @arg FMC_FLAG_PERR: Programming error flag flag - * @arg FMC_FLAG_WERR: Write protection error flag - * @arg FMC_FLAG_EOP: End of Programming flag - * @retval None - */ -void FMC_ClearBitState(uint32_t FMC_FLAG) -{ - if (FMC_SIZE > FMC_BANK1_SIZE) { - if ((FMC_FLAG & 0x80000000) != 0x0) { - /* Clear the flags */ - FMC->CSR2 = FMC_FLAG; - } else { - /* Clear the flags */ - FMC->CSR = FMC_FLAG; - } - } else { - FMC->CSR = FMC_FLAG; - } -} - -/** - * @brief Return the FMC state. - * @param None - * @retval FMC state: FMC_READY, FMC_BSY, FMC_WRPERR, or FMC_PGERR - */ -FMC_State FMC_GetState(void) -{ - FMC_State temp_state = FMC_READY; - - if ((FMC->CSR & FMC_CSR_BUSY) == FMC_CSR_BUSY) { - temp_state = FMC_BSY; - } else { - if ((FMC->CSR & (uint32_t)FMC_CSR_WPEF) != (uint32_t)0x00) { - temp_state = FMC_WRPERR; - } else { - if ((FMC->CSR & (uint32_t)(FMC_CSR_PGEF)) != (uint32_t)0x00) { - temp_state = FMC_PGERR; - } else { - temp_state = FMC_READY; - } - } - } - - /* Return the FMC state */ - return temp_state; -} - -/** - * @brief Return the FMC bak1 state. - * @param None - * @retval FMC state: FMC_READY, FMC_BSY, FMC_WRPERR, or FMC_PGERR - */ -FMC_State FMC_GetB1State(void) -{ - FMC_State temp_state = FMC_READY; - - if ((FMC->CSR & FMC_CSR_BUSY) == FMC_CSR_BUSY) { - temp_state = FMC_BSY; - } else { - if ((FMC->CSR & (uint32_t)FMC_CSR_WPEF) != (uint32_t)0x00) { - temp_state = FMC_WRPERR; - } else { - if ((FMC->CSR & (uint32_t)(FMC_CSR_PGEF)) != (uint32_t)0x00) { - temp_state = FMC_PGERR; - } else { - temp_state = FMC_READY; - } - } - } - return temp_state; -} - -/** - * @brief Return the FMC bak2 state. - * @param None - * @retval FMC state: FMC_READY, FMC_BSY, FMC_WRPERR, or FMC_PGERR - */ - -FMC_State FMC_GetB2State(void) -{ - - FMC_State temp_state = FMC_READY; - - if ((FMC->CSR2 & FMC_CSR2_BUSY & 0x7fffffff) == (FMC_CSR2_BUSY & 0x7fffffff)) { - temp_state = FMC_BSY; - } else { - if ((FMC->CSR2 & FMC_CSR2_WPEF & 0x7fffffff) != (uint32_t)0x00) { - temp_state = FMC_WRPERR; - } else { - if ((FMC->CSR2 & FMC_CSR2_PGEF & 0x7fffffff) != (uint32_t)0x00) { - temp_state = FMC_PGERR; - } else { - temp_state = FMC_READY; - } - } - } - - /* Return the FMC state */ - return temp_state; -} - - -/** - * @brief Check whether FMC is ready or not. - * @param Timeout: Count of loop - * @retval FMC state: FMC_READY, FMC_BSY, FMC_WRPERR, FMC_PGERR or FMC_TIMEOUT_ERR. - */ -FMC_State FMC_WaitReady(uint32_t uCount) -{ - FMC_State temp_state = FMC_BSY; - - /* Wait for FMC ready */ - do { - /* Get FMC state */ - temp_state = FMC_GetState(); - uCount--; - } while ((temp_state == FMC_BSY) && (uCount != 0x00)); - - if (temp_state == FMC_BSY) { - temp_state = FMC_TIMEOUT_ERR; - } - /* Return the FMC state */ - return temp_state; -} - -/** - * @brief Check whether FMC Bank1 is ready or not. - * @param Timeout: Count of loop - * @retval FMC state: FMC_READY, FMC_BSY, FMC_WRPERR, FMC_PGERR or FMC_TIMEOUT_ERR. - */ -FMC_State FMC_B1_WaitReady(uint32_t uCount) -{ - FMC_State temp_state = FMC_BSY; - - /* Wait for FMC ready */ - do { - /* Get FMC state */ - temp_state = FMC_GetB1State(); - uCount--; - } while ((temp_state == FMC_BSY) && (uCount != 0x00)); - - if (temp_state == FMC_BSY) { - temp_state = FMC_TIMEOUT_ERR; - } - /* Return the FMC state */ - return temp_state; -} - -/** - * @brief Check whether FMC Bank2 is ready or not. - * @param Timeout: Count of loop - * @retval FMC state: FMC_READY, FMC_BSY, FMC_WRPERR, FMC_PGERR or FMC_TIMEOUT_ERR. - */ - -FMC_State FMC_B2_WaitReady(uint32_t uCount) -{ - FMC_State temp_state = FMC_BSY; - - /* Wait for FMC ready */ - do { - /* Get FMC state */ - temp_state = FMC_GetB2State(); - uCount--; - } while ((temp_state == (FMC_BSY && 0x7FFFFFFF)) && (uCount != 0x00)); - - if (temp_state == FMC_BSY) { - temp_state = FMC_TIMEOUT_ERR; - } - /* Return the FMC state */ - return temp_state; -} - -/** - * @} - */ - -/** - * @} - */ - -/** -* @} -*/ - -/** - * @} - */ diff --git a/bsp/gd32103c-eval/Libraries/GD32F1xx_standard_peripheral/Source/gd32f10x_gpio.c b/bsp/gd32103c-eval/Libraries/GD32F1xx_standard_peripheral/Source/gd32f10x_gpio.c deleted file mode 100644 index 99a16e4d43..0000000000 --- a/bsp/gd32103c-eval/Libraries/GD32F1xx_standard_peripheral/Source/gd32f10x_gpio.c +++ /dev/null @@ -1,511 +0,0 @@ -/** - ****************************************************************************** - * @brief GPIO functions of the firmware library. - ****************************************************************************** - */ - -/* Includes ------------------------------------------------------------------*/ -#include "gd32f10x_gpio.h" -#include "gd32f10x_rcc.h" - -/** @addtogroup GD32F10x_Firmware - * @{ - */ - -/** @defgroup GPIO - * @brief GPIO driver modules - * @{ - */ - -/** @defgroup GPIO_Private_Defines - * @{ - */ -#define ECR_PORTPINCONFIG_MASK ((uint16_t)0xFF80) -#define LSB_MASK ((uint16_t)0xFFFF) -#define DBGAFR_POSITION_MASK ((uint32_t)0x000F0000) -#define DBGAFR_SWJCFG_MASK ((uint32_t)0xF0FFFFFF) -#define DBGAFR_LOCATION_MASK ((uint32_t)0x00200000) -#define DBGAFR_NUMBITS_MASK ((uint32_t)0x00100000) -#define AFIO_PCFR1_MII_RMII ((uint32_t)0x00800000) -#define AFIO_ESSR1_BITS_FIELDS ((uint8_t)0x04) -#define AFIO_ESSR2_BITS_FIELDS ((uint8_t)0x08) -#define AFIO_ESSR3_BITS_FIELDS ((uint8_t)0x0c) -#define AFIO_ESSR_PIN_FIELDS ((uint8_t)0x04) -#define AFIO_ESSR_4BIT_FIELDS ((uint8_t)0x0f) -#define CTLR1_8BIT_FIELDS ((uint32_t)0x00ff) -#define CTLR2_8BIT_FIELDS ((uint32_t)0x00ff) -#define AFIO_PCFR2_FIELDS ((uint32_t)0x80000000) - -/** - * @} - */ - -/** @defgroup GPIO_Private_Functions - * @{ - */ - -/** - * @brief Reset the GPIOx peripheral. - * @param GPIOx: where x can be (A..G) to select the GPIO peripheral. - * @retval None - */ -void GPIO_DeInit(GPIO_TypeDef *GPIOx) -{ - if (GPIOx == GPIOA) { - /* Enable GPIOA reset state */ - RCC_APB2PeriphReset_Enable(RCC_APB2PERIPH_GPIOA, ENABLE); - /* Release GPIOA from reset state */ - RCC_APB2PeriphReset_Enable(RCC_APB2PERIPH_GPIOA, DISABLE); - } else if (GPIOx == GPIOB) { - /* Enable GPIOB reset state */ - RCC_APB2PeriphReset_Enable(RCC_APB2PERIPH_GPIOB, ENABLE); - /* Release GPIOB from reset state */ - RCC_APB2PeriphReset_Enable(RCC_APB2PERIPH_GPIOB, DISABLE); - } else if (GPIOx == GPIOC) { - /* Enable GPIOC reset state */ - RCC_APB2PeriphReset_Enable(RCC_APB2PERIPH_GPIOC, ENABLE); - /* Release GPIOC from reset state */ - RCC_APB2PeriphReset_Enable(RCC_APB2PERIPH_GPIOC, DISABLE); - } else if (GPIOx == GPIOD) { - /* Enable GPIOD reset state */ - RCC_APB2PeriphReset_Enable(RCC_APB2PERIPH_GPIOD, ENABLE); - /* Release GPIOD from reset state */ - RCC_APB2PeriphReset_Enable(RCC_APB2PERIPH_GPIOD, DISABLE); - } else if (GPIOx == GPIOE) { - /* Enable GPIOE reset state */ - RCC_APB2PeriphReset_Enable(RCC_APB2PERIPH_GPIOE, ENABLE); - /* Release GPIOE from reset state */ - RCC_APB2PeriphReset_Enable(RCC_APB2PERIPH_GPIOE, DISABLE); - } else if (GPIOx == GPIOF) { - /* Enable GPIOF reset state */ - RCC_APB2PeriphReset_Enable(RCC_APB2PERIPH_GPIOF, ENABLE); - /* Release GPIOF from reset state */ - RCC_APB2PeriphReset_Enable(RCC_APB2PERIPH_GPIOF, DISABLE); - } else if (GPIOx == GPIOG) { - /* Enable GPIOG reset state */ - RCC_APB2PeriphReset_Enable(RCC_APB2PERIPH_GPIOG, ENABLE); - /* Release GPIOG from reset state */ - RCC_APB2PeriphReset_Enable(RCC_APB2PERIPH_GPIOG, DISABLE); - } -} - -/** - * @brief Deinitialize the Alternate Functions (remap, event control - * and EXTI configuration) registers to their default reset values. - * @param None - * @retval None - */ -void GPIO_AFDeInit(void) -{ - /* Enable AFIO reset state */ - RCC_APB2PeriphReset_Enable(RCC_APB2PERIPH_AF, ENABLE); - /* Release AFIO from reset state */ - RCC_APB2PeriphReset_Enable(RCC_APB2PERIPH_AF, DISABLE); -} - -/** - * @brief Initialize the GPIOx peripheral. - * @param GPIOx: where x can be (A..G) to select the GPIO peripheral. - * @param GPIO_InitStruct: The structuer contains configuration information. - * @retval None - */ -void GPIO_Init(GPIO_TypeDef *GPIOx, GPIO_InitPara *GPIO_InitStruct) -{ - uint32_t currentmode = 0x00, currentpin = 0x00, pinpos = 0x00, pos = 0x00; - uint32_t tempreg = 0x00, pinmask = 0x00; - - /* GPIO Mode Configuration */ - currentmode = ((uint32_t)GPIO_InitStruct->GPIO_Mode) & ((uint32_t)0x0F); - if ((((uint32_t)GPIO_InitStruct->GPIO_Mode) & ((uint32_t)0x10)) != 0x00) { - /* Output mode */ - currentmode |= (uint32_t)GPIO_InitStruct->GPIO_Speed; - } - /* GPIO CTLR1 Configuration */ - /* Configure the eight low port pins */ - if (((uint32_t)GPIO_InitStruct->GPIO_Pin & CTLR1_8BIT_FIELDS) != 0x00) { - tempreg = GPIOx->CTLR1; - for (pinpos = 0x00; pinpos < 0x08; pinpos++) { - pos = ((uint32_t)0x01) << pinpos; - /* Get the port pins position */ - currentpin = (GPIO_InitStruct->GPIO_Pin) & pos; - if (currentpin == pos) { - pos = pinpos << 2; - /* Clear the corresponding low control register bits */ - pinmask = ((uint32_t)0x0F) << pos; - tempreg &= ~pinmask; - /* Write the mode configuration in the corresponding bits */ - tempreg |= (currentmode << pos); - /* Reset the corresponding ODR bit */ - if (GPIO_InitStruct->GPIO_Mode == GPIO_MODE_IPD) { - GPIOx->BCR = (((uint32_t)0x01) << pinpos); - } else { - /* Set the corresponding ODR bit */ - if (GPIO_InitStruct->GPIO_Mode == GPIO_MODE_IPU) { - GPIOx->BOR = (((uint32_t)0x01) << pinpos); - } - } - } - } - GPIOx->CTLR1 = tempreg; - } - /* GPIO CTLR2 Configuration */ - /* Configure the eight high port pins */ - if (GPIO_InitStruct->GPIO_Pin > CTLR2_8BIT_FIELDS) { - tempreg = GPIOx->CTLR2; - for (pinpos = 0x00; pinpos < 0x08; pinpos++) { - pos = (((uint32_t)0x01) << (pinpos + 0x08)); - /* Get the port pins position */ - currentpin = ((GPIO_InitStruct->GPIO_Pin) & pos); - if (currentpin == pos) { - pos = pinpos << 2; - /* Clear the corresponding high control register bits */ - pinmask = ((uint32_t)0x0F) << pos; - tempreg &= ~pinmask; - /* Write the mode configuration in the corresponding bits */ - tempreg |= (currentmode << pos); - /* Reset the corresponding DOR bit */ - if (GPIO_InitStruct->GPIO_Mode == GPIO_MODE_IPD) { - GPIOx->BCR = (((uint32_t)0x01) << (pinpos + 0x08)); - } - /* Set the corresponding DOR bit */ - if (GPIO_InitStruct->GPIO_Mode == GPIO_MODE_IPU) { - GPIOx->BOR = (((uint32_t)0x01) << (pinpos + 0x08)); - } - } - } - GPIOx->CTLR2 = tempreg; - } -} - -/** - * @brief Initial GPIO_InitParameter members. - * @param GPIO_InitParameter : pointer to a GPIO_InitPara structure. - * @retval None - */ -void GPIO_ParaInit(GPIO_InitPara *GPIO_InitStruct) -{ - /* Reset GPIO init structure parameters values */ - GPIO_InitStruct->GPIO_Pin = GPIO_PIN_ALL; - GPIO_InitStruct->GPIO_Speed = GPIO_SPEED_2MHZ; - GPIO_InitStruct->GPIO_Mode = GPIO_MODE_IN_FLOATING; -} - -/** - * @brief Read the select input port. - * @param GPIOx: Select the GPIO peripheral. - * @param GPIO_Pin: Select the port. - * @retval The input port pin value. - */ -uint8_t GPIO_ReadInputBit(GPIO_TypeDef *GPIOx, uint16_t GPIO_Pin) -{ - uint8_t bitstatus = 0x00; - - if ((GPIOx->DIR & GPIO_Pin) != (uint32_t)Bit_RESET) { - bitstatus = (uint8_t)Bit_SET; - } else { - bitstatus = (uint8_t)Bit_RESET; - } - return bitstatus; -} - -/** - * @brief Read the specified GPIO input data port. - * @param GPIOx: where x can be (A..G) to select the GPIO peripheral. - * @retval GPIO input data port value. - */ -uint16_t GPIO_ReadInputData(GPIO_TypeDef *GPIOx) -{ - return ((uint16_t)GPIOx->DIR); -} - -/** - * @brief Read the specified output data port bit. - * @param GPIOx: where x can be (A..G) to select the GPIO peripheral. - * @param GPIO_Pin: where pin can be (GPIO_PIN_0..GPIO_PIN_15) to select the GPIO peripheral. - * @retval The output port pin value. - */ -uint8_t GPIO_ReadOutputBit(GPIO_TypeDef *GPIOx, uint16_t GPIO_Pin) -{ - uint8_t bitstatus = 0x00; - - if ((GPIOx->DOR & GPIO_Pin) != (uint32_t)Bit_RESET) { - bitstatus = (uint8_t)Bit_SET; - } else { - bitstatus = (uint8_t)Bit_RESET; - } - return bitstatus; -} - -/** - * @brief Read the specified GPIO output data port. - * @param GPIOx: where x can be (A..G) to select the GPIO peripheral. - * @retval GPIO output data port value. - */ -uint16_t GPIO_ReadOutputData(GPIO_TypeDef *GPIOx) -{ - return ((uint16_t)GPIOx->DOR); -} - -/** - * @brief Set the selected data port bits. - * @param GPIOx: where x can be (A..G) to select the GPIO peripheral. - * @param GPIO_Pin: where pin can be (GPIO_PIN_0..GPIO_PIN_15) to select the GPIO peripheral. - * @retval None - */ -void GPIO_SetBits(GPIO_TypeDef *GPIOx, uint16_t GPIO_Pin) -{ - GPIOx->BOR = GPIO_Pin; -} - -/** - * @brief Clear the selected data port bits. - * @param GPIOx: where x can be (A..G) to select the GPIO peripheral. - * @param GPIO_Pin: where pin can be (GPIO_PIN_0..GPIO_PIN_15) to select the GPIO peripheral. - * @retval None - */ -void GPIO_ResetBits(GPIO_TypeDef *GPIOx, uint16_t GPIO_Pin) -{ - GPIOx->BCR = GPIO_Pin; -} - -/** - * @brief Set or clear the selected data port bit. - * @param GPIOx: where x can be (A..G) to select the GPIO peripheral. - * @param GPIO_Pin: where pin can be (GPIO_PIN_0..GPIO_PIN_15) to select the GPIO peripheral. - * @param BitVal: specifies the state of the port.Select one of the follwing values : - * @arg Bit_RESET: clear the port pin - * @arg Bit_SET: set the port pin - * @retval None - */ -void GPIO_WriteBit(GPIO_TypeDef *GPIOx, uint16_t GPIO_Pin, BitState BitVal) -{ - if (BitVal != Bit_RESET) { - GPIOx->BOR = GPIO_Pin; - } else { - GPIOx->BCR = GPIO_Pin; - } -} - -/** - * @brief Write data to the specified GPIO data port. - * @param GPIOx: where x can be (A..G) to select the GPIO peripheral. - * @param PortVal: specifies the value to be written to the port data output register. - * @retval None - */ -void GPIO_WritePort(GPIO_TypeDef *GPIOx, uint16_t PortVal) -{ - GPIOx->DOR = PortVal; -} - -/** - * @brief Lock GPIO Pins configuration. - * @param GPIOx: where x can be (A..G) to select the GPIO peripheral. - * @param GPIO_Pin: where pin can be (GPIO_PIN_0..GPIO_PIN_15) to select the GPIO peripheral. - * @retval None - */ -void GPIO_PinLockConfig(GPIO_TypeDef *GPIOx, uint16_t GPIO_Pin) -{ - uint32_t temp = 0x00010000; - - temp |= GPIO_Pin; - /* Set LCKK bit */ - GPIOx->LOCKR = temp; - /* Reset LCKK bit */ - GPIOx->LOCKR = GPIO_Pin; - /* Set LCKK bit */ - GPIOx->LOCKR = temp; - /* Read LCKK bit*/ - temp = GPIOx->LOCKR; - /* Read LCKK bit*/ - temp = GPIOx->LOCKR; -} - -/** - * @brief Select the GPIO pin used as Event output. - * @param GPIO_PortSource: This parameter can be GPIO_PORT_SOURCE_GPIOx where x can be (A..G). - * @param GPIO_PinSource: This parameter can be GPIO_PINSOURCEx where x can be (0..15). - * @retval None - */ -void GPIO_EventOutputConfig(uint8_t GPIO_PortSource, uint8_t GPIO_PinSource) -{ - uint32_t temp = 0x00; - - temp = AFIO->AFIO_EVR; - /* Clear the PORT[6:4] and PIN[3:0] bits */ - temp &= ECR_PORTPINCONFIG_MASK; - temp |= (uint32_t)GPIO_PortSource << 0x04; - temp |= GPIO_PinSource; - AFIO->AFIO_EVR = temp; -} - -/** - * @brief Enable or disable the Event Output. - * @param AFIO_Event: AFIO_Event Enable or Disable bit. - * @param NewState: new state of the Event output. - * This parameter can be: ENABLE or DISABLE. - * @retval None - */ -void GPIO_EventOutput_Enable(uint32_t AFIO_Event, TypeState NewState) -{ - /* Enable or disable the Event Output */ - if (NewState != DISABLE) { - AFIO->AFIO_EVR |= AFIO_ECR_EVOE_SET; - } else { - AFIO->AFIO_EVR &= AFIO_ECR_EVOE_RESET; - } -} - -/** - * @brief Change the mapping of the specified pin. - * @param GPIO_Remap: selects the pin to remap. - * This parameter can be one of the following values: - * @arg GPIO_REMAP_SPI1 - * @arg GPIO_REMAP_I2C1 - * @arg GPIO_REMAP_USART1 - * @arg GPIO_REMAP_USART2 - * @arg GPIO_PARTIAL_REMAP_USART3 - * @arg GPIO_FULL_REMAP_USART3 - * @arg GPIO_PARTIAL_REMAP_TIMER1 - * @arg GPIO_FULL_REMAP_TIMER1 - * @arg GPIO_PARTIAL_REMAP1_TIMER2 - * @arg GPIO_PARTIAL_REMAP2_TIMER2 - * @arg GPIO_FULL_REMAP_TIMER2 - * @arg GPIO_PARTIAL_REMAP_TIMER3 - * @arg GPIO_FULL_REMAP_TIMER3 - * @arg GPIO_REMAP_TIMER4 - * @arg GPIO_REMAP1_CAN1 - * @arg GPIO_REMAP2_CAN1 - * @arg GPIO_REMAP_PD01 - * @arg GPIO_REMAP_TIMER5CH4_LSI - * @arg GPIO_REMAP_ADC1_ETRGINJ - * @arg GPIO_REMAP_ADC1_ETRGREG - * @arg GPIO_REMAP_ADC2_ETRGINJ - * @arg GPIO_REMAP_ADC2_ETRGREG - * @arg GPIO_REMAP_ETH - * @arg GPIO_REMAP_CAN2 - * @arg GPIO_REMAP_SWJ_NOJTRST - * @arg GPIO_REMAP_SWJ_JTAGDISABLE - * @arg GPIO_REMAP_SWJ_DISABLE - * @arg GPIO_REMAP_SPI3 - * @arg GPIO_REMAP_TIMER2ITR1_PTP_SOF - * @arg GPIO_REMAP_PTP_PPS - * @arg GPIO_REMAP_TIMER15 - * @arg GPIO_REMAP_TIMER16 - * @arg GPIO_REMAP_TIMER17 - * @arg GPIO_REMAP_CEC - * @arg GPIO_REMAP_TIMER1_DMA - * @arg GPIO_REMAP_TIMER9 - * @arg GPIO_REMAP_TIMER10 - * @arg GPIO_REMAP_TIMER11 - * @arg GPIO_REMAP_TIMER13 - * @arg GPIO_REMAP_TIMER14 - * @arg GPIO_REMAP_EXMC_NADV - * @arg GPIO_REMAP_TIMER67_DAC_DMA - * @arg GPIO_REMAP_TIMER12 - * @arg GPIO_REMAP_MISC - * @param NewState: new state of the port pin remapping. - * This parameter can be: ENABLE or DISABLE. - * @retval None - */ -void GPIO_PinRemapConfig(uint32_t GPIO_Remap, TypeState NewState) -{ - uint32_t temp = 0x00, temp1 = 0x00, tempreg = 0x00, tempmask = 0x00; - - if ((GPIO_Remap & 0x80000000) == 0x80000000) { - tempreg = AFIO->AFIO_PCFR2; - } else { - tempreg = AFIO->AFIO_PCFR1; - } - - tempmask = (GPIO_Remap & DBGAFR_POSITION_MASK) >> 0x10; - temp = GPIO_Remap & LSB_MASK; - - if ((GPIO_Remap & (DBGAFR_LOCATION_MASK | DBGAFR_NUMBITS_MASK)) == (DBGAFR_LOCATION_MASK | DBGAFR_NUMBITS_MASK)) { - tempreg &= DBGAFR_SWJCFG_MASK; - AFIO->AFIO_PCFR1 &= DBGAFR_SWJCFG_MASK; - } else if ((GPIO_Remap & DBGAFR_NUMBITS_MASK) == DBGAFR_NUMBITS_MASK) { - temp1 = ((uint32_t)0x03) << tempmask; - tempreg &= ~temp1; - tempreg |= ~DBGAFR_SWJCFG_MASK; - } else { - tempreg &= ~(temp << ((GPIO_Remap >> 0x15) * 0x10)); - tempreg |= ~DBGAFR_SWJCFG_MASK; - } - if (NewState != DISABLE) { - tempreg |= (temp << ((GPIO_Remap >> 0x15) * 0x10)); - } - if ((GPIO_Remap & AFIO_PCFR2_FIELDS) == AFIO_PCFR2_FIELDS) { - AFIO->AFIO_PCFR2 = tempreg; - } else { - AFIO->AFIO_PCFR1 = tempreg; - } -} - -/** - * @brief Select the GPIO pin used as EXTI Line. - * @param GPIO_PortSource: selects the GPIO port to be used as source for EXTI lines. - * This parameter can be GPIO_PORT_SOURCE_GPIOx where x can be (A..G). - * @param GPIO_PinSource: specifies the EXTI line to be configured. - * This parameter can be GPIO_PINSOURCEx where x can be (0..15). - * @retval None - */ -void GPIO_EXTILineConfig(uint8_t GPIO_PortSource, uint8_t GPIO_PinSource) -{ - uint32_t temp = 0x00; - - temp = ((uint32_t)0x0f) << (AFIO_ESSR_PIN_FIELDS * (GPIO_PinSource & (uint8_t)0x03)); - /* Select EXTI0->EXTI3 bit */ - if (GPIO_PinSource < AFIO_ESSR1_BITS_FIELDS) { - AFIO->AFIO_ESSR1 &= ~temp; - AFIO->AFIO_ESSR1 |= (((uint32_t)GPIO_PortSource) << (AFIO_ESSR_PIN_FIELDS * (GPIO_PinSource & (uint8_t)0x03))); - } - /* Select EXTI4->EXTI7 bit */ - else if (GPIO_PinSource < AFIO_ESSR2_BITS_FIELDS) { - AFIO->AFIO_ESSR2 &= ~temp; - AFIO->AFIO_ESSR2 |= (((uint32_t)GPIO_PortSource) << (AFIO_ESSR_PIN_FIELDS * (GPIO_PinSource & (uint8_t)0x03))); - } - /* Select EXTI8->EXTI11 bit */ - else if (GPIO_PinSource < AFIO_ESSR3_BITS_FIELDS) { - AFIO->AFIO_ESSR3 &= ~temp; - AFIO->AFIO_ESSR3 |= (((uint32_t)GPIO_PortSource) << (AFIO_ESSR_PIN_FIELDS * (GPIO_PinSource & (uint8_t)0x03))); - } - /* Select EXTI12->EXTI15 bit */ - else { - AFIO->AFIO_ESSR4 &= ~temp; - AFIO->AFIO_ESSR4 |= (((uint32_t)GPIO_PortSource) << (AFIO_ESSR_PIN_FIELDS * (GPIO_PinSource & (uint8_t)0x03))); - } -} - -/** - * @brief Select the Ethernet media interface. - * @note This function applies only to GD32 Connectivity line devices. - * @param GPIO_ETH_MediaInterface: specifies the Media Interface mode. - * This parameter can be one of the following values: - * @arg GPIO_ETH_MEDIA_INTERFACE_MII: MII mode - * @arg GPIO_ETH_MEDIA_INTERFACE_RMII: RMII mode - * @retval None - */ -void GPIO_ETH_MediaInterfaceConfig(uint32_t GPIO_ETH_MediaInterface) -{ - uint32_t temp = 0; - temp = AFIO->AFIO_PCFR1; - /* Clear MII_RMII_SEL bit */ - temp &= ~((uint32_t)AFIO_PCFR1_MII_RMII); - /* Configure MII_RMII bit according to GPIO_ETH_MediaInterface value */ - temp |= GPIO_ETH_MediaInterface; - /* Store the new value */ - AFIO->AFIO_PCFR1 = temp; -} - -/** - * @} - */ - -/** - * @} - */ - -/** - * @} - */ - diff --git a/bsp/gd32103c-eval/Libraries/GD32F1xx_standard_peripheral/Source/gd32f10x_i2c.c b/bsp/gd32103c-eval/Libraries/GD32F1xx_standard_peripheral/Source/gd32f10x_i2c.c deleted file mode 100644 index efc83ed26f..0000000000 --- a/bsp/gd32103c-eval/Libraries/GD32F1xx_standard_peripheral/Source/gd32f10x_i2c.c +++ /dev/null @@ -1,899 +0,0 @@ -/** - ****************************************************************************** - * @brief I2C functions of the firmware library. - ****************************************************************************** - */ - -/* Includes ------------------------------------------------------------------*/ -#include "gd32f10x_i2c.h" -#include "gd32f10x_rcc.h" - -/** @addtogroup GD32F10x_Firmware - * @{ - */ - -/** @defgroup I2C - * @brief I2C driver modules - * @{ - */ - -/** @defgroup I2C_Private_Defines - * @{ - */ - -/* I2C CTLR1_I2CEN mask */ -#define CTLR1_I2CEN_SET I2C_CTLR1_I2CEN -#define CTLR1_I2CEN_RESET ((uint16_t)~I2C_CTLR1_I2CEN) - -/* I2C CTLR1_GENSTA mask */ -#define CTLR1_GENSTA_SET I2C_CTLR1_GENSTA -#define CTLR1_GENSTA_RESET ((uint16_t)~I2C_CTLR1_GENSTA) - -/* I2C CTLR1_GENSTP mask */ -#define CTLR1_GENSTP_SET I2C_CTLR1_GENSTP -#define CTLR1_GENSTP_RESET ((uint16_t)~I2C_CTLR1_GENSTP) - -/* I2C CTLR1_ACKEN mask */ -#define CTLR1_ACKEN_SET I2C_CTLR1_ACKEN -#define CTLR1_ACKEN_RESET ((uint16_t)~I2C_CTLR1_ACKEN) - -/* I2C CTLR1_GCEN mask */ -#define CTLR1_GCEN_SET I2C_CTLR1_GCEN -#define CTLR1_GCEN_RESET ((uint16_t)~I2C_CTLR1_GCEN) - -/* I2C CTLR1_SRESET mask */ -#define CTLR1_SRESET_SET I2C_CTLR1_SRESET -#define CTLR1_SRESET_RESET ((uint16_t)~I2C_CTLR1_SRESET) - -/* I2C CTLR1_SALT mask */ -#define CTLR1_SALT_SET I2C_CTLR1_SALT -#define CTLR1_SALT_RESET ((uint16_t)~I2C_CTLR1_SALT) - -/* I2C CTLR1_PECTRANS mask */ -#define CTLR1_PECTRANS_SET I2C_CTLR1_PECTRANS -#define CTLR1_PECTRANS_RESET ((uint16_t)~I2C_CTLR1_PECTRANS) - -/* I2C CTLR1_PECEN mask */ -#define CTLR1_PECEN_SET I2C_CTLR1_PECEN -#define CTLR1_PECEN_RESET ((uint16_t)~I2C_CTLR1_PECEN) - -/* I2C CTLR1_ARPEN mask */ -#define CTLR1_ARPEN_SET I2C_CTLR1_ARPEN -#define CTLR1_ARPEN_RESET ((uint16_t)~I2C_CTLR1_ARPEN) - -/* I2C CTLR1_DISSTRC mask */ -#define CTLR1_DISSTRC_SET I2C_CTLR1_DISSTRC -#define CTLR1_DISSTRC_RESET ((uint16_t)~I2C_CTLR1_DISSTRC) - -/* I2C registers Masks */ -#define CTLR1_CLEAR_MASK ((uint16_t)0xFBF5) - -/* I2C CTLR2_DMAON mask */ -#define CTLR2_DMAON_SET I2C_CTLR2_DMAON -#define CTLR2_DMAON_RESET ((uint16_t)~I2C_CTLR2_DMAON) - -/* I2C CTLR2_DMALST mask */ -#define CTLR2_DMALST_SET I2C_CTLR2_DMALST -#define CTLR2_DMALST_RESET ((uint16_t)~I2C_CTLR2_DMALST) - -/* I2C CTLR2_I2CCLK mask */ -#define CTLR2_I2CCLK_RESET ((uint16_t)0xFFC0) - -/* I2C I2CCLK_Freq_MAX */ -#define I2CCLK_FREQ_MAX I2C_CTLR2_I2CCLK - -/* I2C AR1_ADDRESS0 mask */ -#define AR1_ADDRESS0_SET I2C_AR1_ADDRESS0 -#define AR1_ADDRESS0_RESET ((uint16_t)~I2C_AR1_ADDRESS0) - -/* I2C AR2_DUADEN mask */ -#define AR2_DUADEN_SET ((uint16_t)0x0001) -#define AR2_DUADEN_RESET ((uint16_t)0xFFFE) - -/* I2C AR2_ADDRESS2 mask */ -#define AR2_ADDRESS2_RESET ((uint16_t)0xFF01) - -/* I2C CLKR_FAST mask */ -#define CLKR_FAST_SET ((uint16_t)0x8000) - -/* I2C CLKR_CLKC mask */ -#define CLKR_CLKC_SET ((uint16_t)0x0FFF) - -/* I2C STR_FLAG mask */ -#define STR_FLAG_MASK ((uint32_t)0x00FFFFFF) - -/* I2C Interrupt Enable mask */ -#define INTEN_MASK ((uint32_t)0x07000000) - -/** - * @} - */ - -/** @defgroup I2C_Private_Functions - * @{ - */ - -/** - * @brief Reset the I2Cx interface. - * @param I2Cx: the I2C interface where x can be 1 or 2. - * @retval None. - */ -void I2C_DeInit(I2C_TypeDef *I2Cx) -{ - if (I2Cx == I2C1) { - /* Enable I2C1 reset state */ - RCC_APB1PeriphReset_Enable(RCC_APB1PERIPH_I2C1RST, ENABLE); - /* Release I2C1 from reset state */ - RCC_APB1PeriphReset_Enable(RCC_APB1PERIPH_I2C1RST, DISABLE); - } else { - /* Enable I2C2 reset state */ - RCC_APB1PeriphReset_Enable(RCC_APB1PERIPH_I2C2RST, ENABLE); - /* Release I2C2 from reset state */ - RCC_APB1PeriphReset_Enable(RCC_APB1PERIPH_I2C2RST, DISABLE); - } -} - -/** - * @brief Initialize the I2Cx interface parameters. - * @param I2Cx: the I2C interface where x can be 1 or 2. - * @param I2C_InitParaStruct: the sturct I2C_InitPara pointer. - * @retval None. - */ -void I2C_Init(I2C_TypeDef *I2Cx, I2C_InitPara *I2C_InitParaStruct) -{ - uint16_t temp = 0, freqrange = 0; - uint16_t result = 0x04; - uint32_t pclk1 = 8000000; - RCC_ClocksPara rcc_clocks; - - /* Disable I2C */ - I2Cx->CTLR1 &= CTLR1_I2CEN_RESET; - - /* CTLR2 */ - temp = I2Cx->CTLR2; - - /* I2CCLK[5:0] */ - temp &= CTLR2_I2CCLK_RESET; - RCC_GetClocksFreq(&rcc_clocks); - pclk1 = rcc_clocks.APB1_Frequency; - freqrange = (uint16_t)(pclk1 / 1000000); - if (freqrange > I2CCLK_FREQ_MAX) { - freqrange = I2CCLK_FREQ_MAX; - } - temp |= freqrange; - I2Cx->CTLR2 = temp; - - /* RTR and CLKR */ - temp = 0; - - if (I2C_InitParaStruct->I2C_BitRate <= 100000) { - /* Standard mode */ - result = (uint16_t)(pclk1 / (I2C_InitParaStruct->I2C_BitRate << 1)); - if (result < 0x04) { - /* The CLKR.CLKC higher than 0x04 in standard mode*/ - result = 0x04; - } - temp |= result; - I2Cx->CLKR = temp; - - /* RTR */ - if (freqrange >= I2CCLK_FREQ_MAX) { - I2Cx->RTR = I2CCLK_FREQ_MAX; - } else { - I2Cx->RTR = freqrange + 1; - } - } else { - /* Fast mode */ - if (I2C_InitParaStruct->I2C_DutyCycle == I2C_DUTYCYCLE_2) { - /* I2C_DutyCycle == 2 */ - result = (uint16_t)(pclk1 / (I2C_InitParaStruct->I2C_BitRate * 3)); - } else { - /* I2C_DutyCycle == 16/9 */ - result = (uint16_t)(pclk1 / (I2C_InitParaStruct->I2C_BitRate * 25)); - result |= I2C_DUTYCYCLE_16_9; - } - - if ((result & CLKR_CLKC_SET) == 0) { - /* The CLKR.CLKC higher than 0x01 in fast mode*/ - result |= (uint16_t)0x0001; - } - temp |= (uint16_t)(result | CLKR_FAST_SET); - - /* RTR */ - I2Cx->RTR = (uint16_t)(((freqrange * (uint16_t)300) / (uint16_t)1000) + (uint16_t)1); - } - I2Cx->CLKR = temp; - - /* CTLR1 */ - I2Cx->CTLR1 |= CTLR1_I2CEN_SET; - - temp = I2Cx->CTLR1; - temp &= CTLR1_CLEAR_MASK; - temp |= (uint16_t)((uint32_t)I2C_InitParaStruct->I2C_Protocol | CTLR1_ACKEN_SET); - I2Cx->CTLR1 = temp; - - /* AR1 */ - I2Cx->AR1 = (I2C_InitParaStruct->I2C_AddressingMode | I2C_InitParaStruct->I2C_DeviceAddress); -} - -/** - * @brief Initial the sturct I2C_InitPara. - * @param I2C_InitParaStruct: the sturct I2C_InitPara pointer. - * @retval None. - */ -void I2C_ParaInit(I2C_InitPara *I2C_InitParaStruct) -{ - I2C_InitParaStruct->I2C_Protocol = I2C_PROTOCOL_I2C; - I2C_InitParaStruct->I2C_DutyCycle = I2C_DUTYCYCLE_2; - I2C_InitParaStruct->I2C_BitRate = 10000; - I2C_InitParaStruct->I2C_AddressingMode = I2C_ADDRESSING_MODE_7BIT; - I2C_InitParaStruct->I2C_DeviceAddress = 0x08; -} - -/** - * @brief Enable or disable the I2Cx interface. - * @param I2Cx: the I2C interface where x can be 1 or 2. - * @param NewValue: new value of the I2Cx interface. - * This parameter can be: ENABLE or DISABLE. - * @retval None. - */ -void I2C_Enable(I2C_TypeDef *I2Cx, TypeState NewValue) -{ - if (NewValue != DISABLE) { - /* Enable the I2Cx interface */ - I2Cx->CTLR1 |= CTLR1_I2CEN_SET; - } else { - /* Disable the I2Cx interface */ - I2Cx->CTLR1 &= CTLR1_I2CEN_RESET; - } -} - -/** - * @brief Enable or disable the I2Cx DMA requests. - * @param I2Cx: the I2C interface where x can be 1 or 2. - * @param NewValue: new value of the I2C DMA transfer. - * This parameter can be: ENABLE or DISABLE. - * @retval None. - */ -void I2C_DMA_Enable(I2C_TypeDef *I2Cx, TypeState NewValue) -{ - if (NewValue != DISABLE) { - /* Enable the I2Cx DMA requests */ - I2Cx->CTLR2 |= CTLR2_DMAON_SET; - } else { - /* Disable the I2Cx DMA requests */ - I2Cx->CTLR2 &= CTLR2_DMAON_RESET; - } -} - -/** - * @brief Enable or disable the DMA last. - * @param I2Cx: the I2C interface where x can be 1 or 2. - * @param NewValue: new value of the I2C DMA last transfer. - * This parameter can be: ENABLE or DISABLE. - * @retval None. - */ -void I2C_DMALastTransfer_Enable(I2C_TypeDef *I2Cx, TypeState NewValue) -{ - if (NewValue != DISABLE) { - /* Next DMA transfer is the last transfer */ - I2Cx->CTLR2 |= CTLR2_DMALST_SET; - } else { - /* Next DMA transfer is not the last transfer */ - I2Cx->CTLR2 &= CTLR2_DMALST_RESET; - } -} - -/** - * @brief Enable or disable I2C_CTLR1_GENSTA control bit. - * @param I2Cx: the I2C interface where x can be 1 or 2. - * @param NewValue: new value of the I2C START condition generation. - * This parameter can be: ENABLE or DISABLE. - * @retval None. - */ -void I2C_StartOnBus_Enable(I2C_TypeDef *I2Cx, TypeState NewValue) -{ - if (NewValue != DISABLE) { - /* Enable I2C_CTLR1_GENSTA control bit */ - I2Cx->CTLR1 |= CTLR1_GENSTA_SET; - } else { - /* Disable I2C_CTLR1_GENSTA control bit */ - I2Cx->CTLR1 &= CTLR1_GENSTA_RESET; - } -} - -/** - * @brief Enable or disable I2C_CTLR1_GENSTP control bit. - * @param I2Cx: the I2C interface where x can be 1 or 2. - * @param NewValue: new value of the I2C STOP condition generation. - * This parameter can be: ENABLE or DISABLE. - * @retval None. - */ -void I2C_StopOnBus_Enable(I2C_TypeDef *I2Cx, TypeState NewValue) -{ - if (NewValue != DISABLE) { - /* Enable I2C_CTLR1_GENSTP control bit */ - I2Cx->CTLR1 |= CTLR1_GENSTP_SET; - } else { - /* Disable I2C_CTLR1_GENSTP control bit */ - I2Cx->CTLR1 &= CTLR1_GENSTP_RESET; - } -} - -/** - * @brief Enable or disable the I2C_CTLR1_ACKEN control bit. - * @param I2Cx: the I2C interface where x can be 1 or 2. - * @param NewValue: new value of the I2C Acknowledgement. - * This parameter can be: ENABLE or DISABLE. - * @retval None. - */ -void I2C_Acknowledge_Enable(I2C_TypeDef *I2Cx, TypeState NewValue) -{ - if (NewValue != DISABLE) { - /* Enable I2C_CTLR1_ACKEN control bit */ - I2Cx->CTLR1 |= CTLR1_ACKEN_SET; - } else { - /* Disable I2C_CTLR1_ACKEN control bit */ - I2Cx->CTLR1 &= CTLR1_ACKEN_RESET; - } -} - -/** - * @brief Set the I2Cx own address2. - * @param I2Cx: the I2C interface where x can be 1 or 2. - * @param Address: specifies the 7bit I2C own address2. - * @retval None. - */ -void I2C_OwnAddress2(I2C_TypeDef *I2Cx, uint8_t Address) -{ - uint16_t temp = 0; - - temp = I2Cx->AR2; - temp &= AR2_ADDRESS2_RESET; - temp |= (uint16_t)((uint16_t)Address & (uint16_t)0x00FE); - /* I2C_AR2_ADDRESS2 */ - I2Cx->AR2 = temp; -} - -/** - * @brief Enable or disable the I2C_AR2_DUADEN control bit. - * @param I2Cx: the I2C interface where x can be 1 or 2. - * @param NewValue: new value of the I2C dual addressing mode. - * This parameter can be: ENABLE or DISABLE. - * @retval None. - */ -void I2C_DualAddress_Enable(I2C_TypeDef *I2Cx, TypeState NewValue) -{ - if (NewValue != DISABLE) { - /* Enable the I2C_AR2_DUADEN control bit */ - I2Cx->AR2 |= AR2_DUADEN_SET; - } else { - /* Disable the I2C_AR2_DUADEN control bit */ - I2Cx->AR2 &= AR2_DUADEN_RESET; - } -} - -/** - * @brief Enable or disable I2C_CTLR1_GCEN control bit. - * @param I2Cx: the I2C interface where x can be 1 or 2. - * @param NewValue: new value of the I2C General call. - * This parameter can be: ENABLE or DISABLE. - * @retval None. - */ -void I2C_GeneralCall_Enable(I2C_TypeDef *I2Cx, TypeState NewValue) -{ - if (NewValue != DISABLE) { - /* Enable I2C_CTLR1_GCEN control bit */ - I2Cx->CTLR1 |= CTLR1_GCEN_SET; - } else { - /* Disable I2C_CTLR1_GCEN control bit */ - I2Cx->CTLR1 &= CTLR1_GCEN_RESET; - } -} - -/** - * @brief Enable or disable the specified I2C interrupt. - * @param I2Cx: the I2C interface where x can be 1 or 2. - * @param I2C_INT: the I2C interrupt sources. - * This parameter can be any combination of the following values: - * @arg I2C_INT_EIE: Error interrupt - * @arg I2C_INT_EE: Event interrupt - * @arg I2C_INT_BIE: Buffer interrupt - * @param NewValue: new value of the specified I2C interrupts. - * This parameter can be: ENABLE or DISABLE. - * @retval None. - */ -void I2C_INTConfig(I2C_TypeDef *I2Cx, uint16_t I2C_INT, TypeState NewValue) -{ - if (NewValue != DISABLE) { - /* Enable the I2C interrupt */ - I2Cx->CTLR2 |= I2C_INT; - } else { - /* Disable the I2C interrupt */ - I2Cx->CTLR2 &= (uint16_t)~I2C_INT; - } -} - -/** - * @brief Send one byte to bus. - * @param I2Cx: the I2C interface where x can be 1 or 2. - * @param Data: Byte to be transmitted. - * @retval None. - */ -void I2C_SendData(I2C_TypeDef *I2Cx, uint8_t Data) -{ - /* Write Data to DTR */ - I2Cx->DTR = Data; -} - -/** - * @brief Receive one byte from the bus. - * @param I2Cx: the I2C interface where x can be 1 or 2. - * @retval The received data. - */ -uint8_t I2C_ReceiveData(I2C_TypeDef *I2Cx) -{ - /* Read the DTR register */ - return (uint8_t)I2Cx->DTR; -} - -/** - * @brief Addressing a device on the I2C bus. - * @param I2Cx: the I2C interface where x can be 1 or 2. - * @param Address: the slave device's address. - * @param I2C_Direction: Transmitter or a Receiver. - * This parameter can be one of the following values: - * @arg I2C_DIRECTION_TRANSMITTER: Transmitter mode - * @arg I2C_DIRECTION_RECEIVER: Receiver mode - * @retval None. - */ -void I2C_AddressingDevice_7bit(I2C_TypeDef *I2Cx, uint8_t Address, uint8_t I2C_Direction) -{ - if (I2C_Direction != I2C_DIRECTION_TRANSMITTER) { - /* Receiver mode */ - Address |= AR1_ADDRESS0_SET; - } else { - /* Transmitter mode */ - Address &= AR1_ADDRESS0_RESET; - } - I2Cx->DTR = Address; -} - -/** - * @brief Read the I2Cx register. - * @param I2Cx: the I2C interface where x can be 1 or 2. - * @param I2C_Register: the I2Cx register. - * This parameter can be one of the following values: - * @arg I2C_REGISTER_CTLR1: CTLR1 register. - * @arg I2C_REGISTER_CTLR2: CTLR2 register. - * @arg I2C_REGISTER_AR1: AR1 register. - * @arg I2C_REGISTER_AR2: AR2 register. - * @arg I2C_REGISTER_DTR: DTR register. - * @arg I2C_REGISTER_STR1: STR1 register. - * @arg I2C_REGISTER_STR2: STR2 register. - * @arg I2C_REGISTER_CLKR: CLKR register. - * @arg I2C_REGISTER_RTR: RTR register. - * @retval The value of the read register. - */ -uint16_t I2C_ReadRegister(I2C_TypeDef *I2Cx, uint8_t I2C_Register) -{ - __IO uint32_t temp = 0; - - temp = (uint32_t) I2Cx; - temp += I2C_Register; - - /* Return the selected register value */ - return (*(__IO uint16_t *) temp); -} - -/** - * @brief Enable or disable the I2C_CTLR1_SRESET control bit. - * @param I2Cx: the I2C interface where x can be 1 or 2. - * @param NewValue: new value of the I2C software reset. - * This parameter can be: ENABLE or DISABLE. - * @retval None. - */ -void I2C_SoftwareReset_Enable(I2C_TypeDef *I2Cx, TypeState NewValue) -{ - if (NewValue != DISABLE) { - /* Enable I2C_CTLR1_SRESET control bit */ - I2Cx->CTLR1 |= CTLR1_SRESET_SET; - } else { - /* Disable I2C_CTLR1_SRESET control bit */ - I2Cx->CTLR1 &= CTLR1_SRESET_RESET; - } -} - -/** - * @brief Enable or disable the I2C_CTLR1_POAP control bit. - * @param I2Cx: the I2C interface where x can be 1 or 2. - * @param I2C_NACKPosition: the position of NACK. - * This parameter can be one of the following values: - * @arg I2C_NACKPOSITION_NEXT: the next byte is the last received byte - * @arg I2C_NACKPOSITION_CURRENT: the current byte is the last received byte - * @retval None. - */ -void I2C_NACKPosition_Enable(I2C_TypeDef *I2Cx, uint16_t I2C_NACKPosition) -{ - if (I2C_NACKPosition == I2C_NACKPOSITION_NEXT) { - /* Next byte will be the last received byte */ - I2Cx->CTLR1 |= I2C_NACKPOSITION_NEXT; - } else { - /* Current byte is the last received byte */ - I2Cx->CTLR1 &= I2C_NACKPOSITION_CURRENT; - } -} - -/** - * @brief Enable or disable the I2C_CTLR1_SALT control bit. - * @param I2Cx: the I2C interface where x can be 1 or 2. - * @param NewValue: new value of the I2C software reset. - * This parameter can be: ENABLE or DISABLE. - * @retval None - */ -void I2C_SMBusAlertSend_Enable(I2C_TypeDef *I2Cx, TypeState NewValue) -{ - if (NewValue != DISABLE) { - /* Enable I2C_CTLR1_SALT control bit */ - I2Cx->CTLR1 |= CTLR1_SALT_SET; - } else { - /* Disable I2C_CTLR1_SALT control bit */ - I2Cx->CTLR1 &= CTLR1_SALT_RESET; - } -} - -/** - * @brief Enable or disable the I2C_CTLR1_PECTRANS control bit. - * @param I2Cx: the I2C interface where x can be 1 or 2. - * @param NewValue: new value of the I2C PEC transmission. - * This parameter can be: ENABLE or DISABLE. - * @retval None - */ -void I2C_PECTransmit_Enable(I2C_TypeDef *I2Cx, TypeState NewValue) -{ - if (NewValue != DISABLE) { - /* Enable I2C_CTLR1_PECTRANS control bit */ - I2Cx->CTLR1 |= CTLR1_PECTRANS_SET; - } else { - /* Disable I2C_CTLR1_PECTRANS control bit */ - I2Cx->CTLR1 &= CTLR1_PECTRANS_RESET; - } -} - -/** - * @brief Enable or disable the I2C_CTLR1_POAP control bit. - * @param I2Cx: the I2C interface where x can be 1 or 2. - * @param I2C_PECPosition: the position of PEC. - * This parameter can be one of the following values: - * @arg I2C_PECPOSITION_NEXT: the next byte is PEC - * @arg I2C_PECPOSITION_CURRENT: the current byte is PEC - * @retval None. - */ -void I2C_PECPosition_Enable(I2C_TypeDef *I2Cx, uint16_t I2C_PECPosition) -{ - if (I2C_PECPosition == I2C_PECPOSITION_NEXT) { - /* The next byte is PEC */ - I2Cx->CTLR1 |= I2C_PECPOSITION_NEXT; - } else { - /* The current byte is PEC */ - I2Cx->CTLR1 &= I2C_PECPOSITION_CURRENT; - } -} - -/** - * @brief Enable or disable the I2C_CTLR1_PECEN control bit. - * @param I2Cx: the I2C interface where x can be 1 or 2. - * @param NewValue: new value of the I2Cx PEC value calculation. - * This parameter can be: ENABLE or DISABLE. - * @retval None. - */ -void I2C_PEC_Enable(I2C_TypeDef *I2Cx, TypeState NewValue) -{ - if (NewValue != DISABLE) { - /* Enable I2C_CTLR1_PECEN control bit */ - I2Cx->CTLR1 |= CTLR1_PECEN_SET; - } else { - /* Disable I2C_CTLR1_PECEN control bit */ - I2Cx->CTLR1 &= CTLR1_PECEN_RESET; - } -} - -/** - * @brief The Packet Error Checking value. - * @param I2Cx: the I2C interface where x can be 1 or 2. - * @retval The PEC value. - */ -uint8_t I2C_GetPECValue(I2C_TypeDef *I2Cx) -{ - /* I2C_STR2_ECV */ - return ((I2Cx->STR2) >> 8); -} - -/** - * @brief Enable or disable the I2C_CTLR1_ARPEN control bit. - * @param I2Cx: the I2C interface where x can be 1 or 2. - * @param NewValue: new value of the I2Cx ARP. - * This parameter can be: ENABLE or DISABLE. - * @retval None. - */ -void I2C_ARP_Enable(I2C_TypeDef *I2Cx, TypeState NewValue) -{ - if (NewValue != DISABLE) { - /* Enable I2C_CTLR1_ARPEN control bit */ - I2Cx->CTLR1 |= CTLR1_ARPEN_SET; - } else { - /* Disable I2C_CTLR1_ARPEN control bit */ - I2Cx->CTLR1 &= CTLR1_ARPEN_RESET; - } -} - -/** - * @brief Enable or disable the I2C_CTLR1_DISSTRC control bit. - * @param I2Cx: the I2C interface where x can be 1 or 2. - * @param NewValue: new value of the I2Cx Clock stretching. - * This parameter can be: ENABLE or DISABLE. - * @retval None. - */ -void I2C_StretchClock_Enable(I2C_TypeDef *I2Cx, TypeState NewValue) -{ - if (NewValue == DISABLE) { - /* Enable I2C_CTLR1_DISSTRC control bit */ - I2Cx->CTLR1 |= CTLR1_DISSTRC_SET; - } else { - /* Enable I2C_CTLR1_DISSTRC control bit */ - I2Cx->CTLR1 &= CTLR1_DISSTRC_RESET; - } -} - -/** - * @brief Enable or disable the I2C_CLKR_DTCY control bit. - * @param I2Cx: the I2C interface where x can be 1 or 2. - * @param I2C_DutyCycle: the duty cycle in fast mode. - * This parameter can be one of the following values: - * @arg I2C_DUTYCYCLE_2: I2C fast mode Tlow/Thigh = 2 - * @arg I2C_DUTYCYCLE_16_9: I2C fast mode Tlow/Thigh = 16/9 - * @retval None. - */ -void I2C_FastModeDutyCycle(I2C_TypeDef *I2Cx, uint16_t I2C_DutyCycle) -{ - if (I2C_DutyCycle != I2C_DUTYCYCLE_16_9) { - /* DutyCycle=2:1 */ - I2Cx->CLKR &= I2C_DUTYCYCLE_2; - } else { - /* DutyCycle=16:9 */ - I2Cx->CLKR |= I2C_DUTYCYCLE_16_9; - } -} - -/** - * @brief Detect I2Cx State Machine. - * @param I2Cx: the I2C interface where x can be 1 or 2. - * @param I2C_State: I2Cx State Machine. - * This parameter can be one of the following values: - * @arg I2C_PROGRAMMINGMODE_SLAVE_TRANSMITTER_ADDSEND - * @arg I2C_PROGRAMMINGMODE_SLAVE_RECEIVER_ADDSEND - * @arg I2C_PROGRAMMINGMODE_SLAVE_TRANSMITTER_SECONDADDRESS_SELECTED - * @arg I2C_PROGRAMMINGMODE_SLAVE_RECEIVER_SECONDADDRESS_SELECTED - * @arg I2C_PROGRAMMINGMODE_SLAVE_GENERALCALLADDRESS_SELECTED - * @arg I2C_PROGRAMMINGMODE_SLAVE_BYTE_RECEIVED - * @arg (I2C_PROGRAMMINGMODE_SLAVE_BYTE_RECEIVED | I2C_FLAG_DUMODF) - * @arg (I2C_PROGRAMMINGMODE_SLAVE_BYTE_RECEIVED | I2C_FLAG_RXGC) - * @arg I2C_PROGRAMMINGMODE_SLAVE_BYTE_TRANSMITTED - * @arg (I2C_PROGRAMMINGMODE_SLAVE_BYTE_TRANSMITTED | I2C_FLAG_DUMODF) - * @arg (I2C_PROGRAMMINGMODE_SLAVE_BYTE_TRANSMITTED | I2C_FLAG_RXGC) - * @arg I2C_PROGRAMMINGMODE_SLAVE_ACK_FAILURE - * @arg I2C_PROGRAMMINGMODE_SLAVE_STOP_DETECTED - * @arg I2C_PROGRAMMINGMODE_MASTER_SBSEND - * @arg I2C_PROGRAMMINGMODE_MASTER_TRANSMITTER_ADDSEND - * @arg I2C_PROGRAMMINGMODE_MASTER_RECEIVER_ADDSEND - * @arg I2C_PROGRAMMINGMODE_MASTER_BYTE_RECEIVED - * @arg I2C_PROGRAMMINGMODE_MASTER_BYTE_TRANSMITTING - * @arg I2C_PROGRAMMINGMODE_MASTER_BYTE_TRANSMITTED - * @arg I2C_PROGRAMMINGMODE_MASTER_ADD10SEND - * @retval The detected result(SUCCESS or ERROR). - */ -TypeState I2C_StateDetect(I2C_TypeDef *I2Cx, uint32_t I2C_State) -{ - uint32_t currentstate = 0; - uint32_t flag1 = 0, flag2 = 0; - TypeState state = ERROR; - - /* Read the I2Cx status register */ - flag1 = I2Cx->STR1; - flag2 = I2Cx->STR2; - flag2 = flag2 << 16; - - /* Get the state value from I2C status register */ - currentstate = (flag1 | flag2) & STR_FLAG_MASK; - - if ((currentstate & I2C_State) == I2C_State) { - /* I2C_State is detected */ - state = SUCCESS; - } else { - /* I2C_State is not detected */ - state = ERROR; - } - return state; -} - -/** - * @brief Get the I2Cx Current State. - * @param I2Cx: the I2C interface where x can be 1 or 2. - * @retval The current state. - */ -uint32_t I2C_GetCurrentState(I2C_TypeDef *I2Cx) -{ - uint32_t currentstate = 0; - uint32_t flag1 = 0, flag2 = 0; - - /* Read the I2Cx status register */ - flag1 = I2Cx->STR1; - flag2 = I2Cx->STR2; - flag2 = flag2 << 16; - - /* Get the last event value from I2C status register */ - currentstate = (flag1 | flag2) & STR_FLAG_MASK; - - return currentstate; -} - -/** - * @brief Get the bit flag of STRx registers. - * @param I2Cx: the I2C interface where x can be 1 or 2. - * @param I2C_FLAG: the flag of STRx registers. - * This parameter can be one of the following values: - * @arg I2C_FLAG_DUMODF: Dual flag (Slave mode) - * @arg I2C_FLAG_HSTSMB: SMBus host header (Slave mode) - * @arg I2C_FLAG_DEFSMB: SMBus default header (Slave mode) - * @arg I2C_FLAG_RXGC: General call header flag (Slave mode) - * @arg I2C_FLAG_TRS: Transmitter or Receiver flag - * @arg I2C_FLAG_I2CBSY: Bus busy flag - * @arg I2C_FLAG_MASTER: Master or Slave flag - * @arg I2C_FLAG_SMBALTS: SMBus Alert flag - * @arg I2C_FLAG_SMBTO: Timeout or Tlow error flag - * @arg I2C_FLAG_PECE: PEC error in reception flag - * @arg I2C_FLAG_RXORE: Overrun or Underrun flag (Slave mode) - * @arg I2C_FLAG_AE: Acknowledge failure flag - * @arg I2C_FLAG_LOSTARB: Arbitration lost flag (Master mode) - * @arg I2C_FLAG_BE: Bus error flag - * @arg I2C_FLAG_TBE: Data register empty flag (Transmitter) - * @arg I2C_FLAG_RBNE: Data register not empty (Receiver) flag - * @arg I2C_FLAG_STPSEND: Stop detection flag (Slave mode) - * @arg I2C_FLAG_ADD10SEND: 10-bit header sent flag (Master mode) - * @arg I2C_FLAG_BTC: Byte transfer finished flag - * @arg I2C_FLAG_ADDSEND: Address sent flag (Master mode) or Address matched flag (Slave mode) - * @arg I2C_FLAG_SBSEND: Start bit flag (Master mode) - * @retval The new value of I2C_FLAG (SET or RESET). - */ -TypeState I2C_GetBitState(I2C_TypeDef *I2Cx, uint32_t I2C_FLAG) -{ - __IO uint32_t i2creg = 0, i2cxbase = 0; - - /* Get the I2Cx peripheral base address */ - i2cxbase = (uint32_t)I2Cx; - - /* Read flag register index */ - i2creg = I2C_FLAG >> 28; - - /* Get bit[23:0] of the flag */ - I2C_FLAG &= STR_FLAG_MASK; - - if (i2creg != 0) { - /* Flag in I2Cx STR1 register */ - i2cxbase += 0x14; - } else { - /* Flag in I2Cx STR2 Register */ - I2C_FLAG = (uint32_t)(I2C_FLAG >> 16); - /* Get the I2Cx STR2 register address */ - i2cxbase += 0x18; - } - - if (((*(__IO uint32_t *)i2cxbase) & I2C_FLAG) != (uint32_t)RESET) { - /* I2C_FLAG is set */ - return SET; - } else { - /* I2C_FLAG is reset */ - return RESET; - } -} - -/** - * @brief Clear the bit flag of STRx registers. - * @param I2Cx: the I2C interface where x can be 1 or 2. - * @param I2C_FLAG: the flag of STRx registers. - * This parameter can be any combination of the following values: - * @arg I2C_FLAG_SMBALTS: SMBus Alert flag - * @arg I2C_FLAG_SMBTO: Timeout or Tlow error flag - * @arg I2C_FLAG_PECE: PEC error in reception flag - * @arg I2C_FLAG_RXORE: Overrun or Underrun flag (Slave mode) - * @arg I2C_FLAG_AE: Acknowledge failure flag - * @arg I2C_FLAG_LOSTARB: Arbitration lost flag (Master mode) - * @arg I2C_FLAG_BE: Bus error flag - * @retval None. - */ -void I2C_ClearBitState(I2C_TypeDef *I2Cx, uint32_t I2C_FLAG) -{ - uint32_t flagpos = 0; - - /* Get the I2C flag position */ - flagpos = I2C_FLAG & STR_FLAG_MASK; - /* Clear the selected I2C flag */ - I2Cx->STR1 = (uint16_t)~flagpos; -} - -/** - * @brief Get the interrupt bit flag. - * @param I2Cx: the I2C interface where x can be 1 or 2. - * @param I2C_INT: the interrupt bit flag. - * This parameter can be one of the following values: - * @arg I2C_INT_SMBALTS: SMBus Alert flag - * @arg I2C_INT_SMBTO: Timeout or Tlow error flag - * @arg I2C_INT_PECE: PEC error in reception flag - * @arg I2C_INT_RXORE: Overrun or Underrun flag (Slave mode) - * @arg I2C_INT_AE: Acknowledge failure flag - * @arg I2C_INT_LOSTARB: Arbitration lost flag (Master mode) - * @arg I2C_INT_BE: Bus error flag - * @arg I2C_INT_TBE: Data register empty flag (Transmitter) - * @arg I2C_INT_RBNE: Data register not empty (Receiver) flag - * @arg I2C_INT_STPSEND: Stop detection flag (Slave mode) - * @arg I2C_INT_ADD10SEND: 10-bit header sent flag (Master mode) - * @arg I2C_INT_BTC: Byte transfer finished flag - * @arg I2C_INT_ADDSEND: Address sent flag (Master mode) or Address matched flag (Slave mode) - * @arg I2C_INT_SBSEND: Start bit flag (Master mode) - * @retval The new value of I2C_INT (SET or RESET). - */ -TypeState I2C_GetIntBitState(I2C_TypeDef *I2Cx, uint32_t I2C_INT) -{ - uint32_t enablestatus = 0; - - /* Check if the interrupt source is enabled or not */ - enablestatus = (uint32_t)(((I2C_INT & INTEN_MASK) >> 16) & (I2Cx->CTLR2)) ; - - /* Get bit[23:0] of the flag */ - I2C_INT &= STR_FLAG_MASK; - - if (((I2Cx->STR1 & I2C_INT) != (uint32_t)RESET) && enablestatus) { - /* I2C_INT is set */ - return SET; - } else { - /* I2C_INT is reset */ - return RESET; - } -} - -/** - * @brief Clear the interrupt bit flag. - * @param I2Cx: the I2C interface where x can be 1 or 2. - * @param I2C_INT: the interrupt bit flag. - * This parameter can be any combination of the following values: - * @arg I2C_INT_SMBALTS: SMBus Alert interrupt - * @arg I2C_INT_SMBTO: Timeout or Tlow error interrupt - * @arg I2C_INT_PECE: PEC error in reception interrupt - * @arg I2C_INT_RXORE: Overrun or Underrun interrupt (Slave mode) - * @arg I2C_INT_AE: Acknowledge failure interrupt - * @arg I2C_INT_LOSTARB: Arbitration lost interrupt (Master mode) - * @arg I2C_INT_BE: Bus error interrupt - * @retval None. - */ -void I2C_ClearIntBitState(I2C_TypeDef *I2Cx, uint32_t I2C_INT) -{ - uint32_t flagpos = 0; - - /* Get the I2C flag position */ - flagpos = I2C_INT & STR_FLAG_MASK; - /* Clear the selected I2C flag */ - I2Cx->STR1 = (uint16_t)~flagpos; -} - -/** - * @} - */ - -/** - * @} - */ - -/** - * @} - */ - diff --git a/bsp/gd32103c-eval/Libraries/GD32F1xx_standard_peripheral/Source/gd32f10x_iwdg.c b/bsp/gd32103c-eval/Libraries/GD32F1xx_standard_peripheral/Source/gd32f10x_iwdg.c deleted file mode 100644 index 1032f064e5..0000000000 --- a/bsp/gd32103c-eval/Libraries/GD32F1xx_standard_peripheral/Source/gd32f10x_iwdg.c +++ /dev/null @@ -1,130 +0,0 @@ -/** - ****************************************************************************** - * @brief IWDG functions of the firmware library. - ****************************************************************************** - */ - -/* Includes ------------------------------------------------------------------*/ -#include "gd32f10x_iwdg.h" - -/** @addtogroup GD32F10x_Firmware - * @{ - */ - -/** @defgroup IWDG - * @brief IWDG driver modules - * @{ - */ - -/** @defgroup IWDG_Private_Variables - * @{ - */ - -/* CTLR register bit mask */ -#define CTLR_KEY_RELOAD ((uint16_t)0xAAAA) -#define CTLR_KEY_ENABLE ((uint16_t)0xCCCC) - -/** - * @} - */ - -/** @defgroup IWDG_Private_Functions - * @{ - */ - -/** - * @brief Enable or disable the IWDG_PSR, IWDG_RLDR and IWDG_WND write protection. - * @param IWDG_WriteAccess: value to enable or disable the write access to registers. - * This parameter can be one of the following values: - * @arg IWDG_WRITEACCESS_ENABLE: Enable write access to IWDG_PSR, IWDG_RLDR and IWDG_WND registers - * @arg IWDG_WRITEACCESS_DISABLE: Disable write access to IWDG_PSR, IWDG_RLDR and IWDG_WND registers - * @retval None - */ -void IWDG_Write_Enable(uint16_t IWDG_WriteAccess) -{ - IWDG->CTLR = IWDG_WriteAccess; -} - -/** - * @brief Set IWDG prescaler value. - * @param PrescalerValue: IWDG Prescaler value. - * This parameter can be one of the following values: - * @arg IWDG_PRESCALER_4: IWDG prescaler set to 4 - * @arg IWDG_PRESCALER_8: IWDG prescaler set to 8 - * @arg IWDG_PRESCALER_16: IWDG prescaler set to 16 - * @arg IWDG_PRESCALER_32: IWDG prescaler set to 32 - * @arg IWDG_PRESCALER_64: IWDG prescaler set to 64 - * @arg IWDG_PRESCALER_128: IWDG prescaler set to 128 - * @arg IWDG_PRESCALER_256: IWDG prescaler set to 256 - * @retval None - */ -void IWDG_SetPrescaler(uint8_t PrescalerValue) -{ - IWDG->PSR = PrescalerValue; -} - -/** - * @brief Set independent watchdog counter reload value. - * @param ReloadValue: IWDG Reload value. - * This parameter must be between 0 and 0x0FFF. - * @retval None - */ -void IWDG_SetReloadValue(uint16_t ReloadValue) -{ - IWDG->RLDR = ReloadValue; -} - -/** - * @brief Reload the counter. - * @param None - * @retval None - */ -void IWDG_ReloadCounter(void) -{ - IWDG->CTLR = CTLR_KEY_RELOAD; -} - -/** - * @brief Start the independent watchdog counter. - * @param None - * @retval None - */ -void IWDG_Enable(void) -{ - IWDG->CTLR = CTLR_KEY_ENABLE; -} - -/** - * @brief Check registers' bit state. - * @param IWDG_FLAG: the flag to check. - * This parameter can be one of the following values: - * @arg IWDG_BIT_PUD: A write operation to IWDG_PSR register on going - * @arg IWDG_BIT_RUD: A write operation to IWDG_RLDR register on going - * @arg IWDG_BIT_WUD: A write operation to IWDG_WND register on going - * @retval The new state of IWDG_FLAG (SET or RESET). - */ -TypeState IWDG_GetBitState(uint16_t IWDG_FLAG) -{ - if ((IWDG->STR & IWDG_FLAG) != (uint32_t)RESET) { - return SET; - } else { - return RESET; - } -} - -/** - * @} - */ - -/** - * @} - */ - -/** - * @} - */ - -/** - * @} - */ - diff --git a/bsp/gd32103c-eval/Libraries/GD32F1xx_standard_peripheral/Source/gd32f10x_mcudbg.c b/bsp/gd32103c-eval/Libraries/GD32F1xx_standard_peripheral/Source/gd32f10x_mcudbg.c deleted file mode 100644 index 03b0618344..0000000000 --- a/bsp/gd32103c-eval/Libraries/GD32F1xx_standard_peripheral/Source/gd32f10x_mcudbg.c +++ /dev/null @@ -1,105 +0,0 @@ -/** - ****************************************************************************** - * @brief MCUDBG functions of the firmware library. - ****************************************************************************** - */ - -/* Includes ------------------------------------------------------------------*/ -#include "gd32f10x_mcudbg.h" - -/** @addtogroup GD32F10x_Firmware - * @{ - */ - -/** @defgroup MCUDBG - * @brief MCUDBG driver modules - * @{ - */ - - -/** @defgroup MCUDBG_Private_Defines - * @{ - */ - -#define IDCODE_DEVID_MASK ((uint32_t)0x00000FFF) -/** - * @} - */ - - -/** @defgroup MCUDBG_Private_Functions - * @{ - */ - -/** - * @brief Returns the device revision identifier. - * @param None - * @retval Device revision identifier - */ -uint32_t MCUDBG_GetREVID(void) -{ - return (MCUDBG->IDR >> 16); -} - -/** - * @brief Returns the device identifier. - * @param None - * @retval Device identifier - */ -uint32_t MCUDBG_GetDEVID(void) -{ - return (MCUDBG->IDR & IDCODE_DEVID_MASK); -} - -/** - * @brief Configure the specified peripheral and low power mode behavior - * when the MCU under Debug mode. - * @param MCUDBG_Periph: specifies the peripheral and low power mode. - * This parameter can be any combination of the following values: - * @arg MCUDBG_SLEEP_HOLD: Keep debugger connection during SLEEP mode - * @arg MCUDBG_DEEPSLEEP_HOLD: Keep debugger connection during DEEPSLEEP mode - * @arg MCUDBG_STDBY_HOLD: Keep debugger connection during STANDBY mode - * @arg MCUDBG_IWDG_HOLD: Debug IWDG hold when Core is halted - * @arg MCUDBG_WWDG_HOLD: Debug WWDG hold when Core is halted - * @arg MCUDBG_TIMER1_HOLD: TIMER1 counter hold when Core is halted - * @arg MCUDBG_TIMER2_HOLD: TIMER2 counter hold when Core is halted - * @arg MCUDBG_TIMER3_HOLD: TIMER3 counter hold when Core is halted - * @arg MCUDBG_TIMER4_HOLD: TIMER4 counter hold when Core is halted - * @arg MCUDBG_CAN1_HOLD: Debug CAN1 hold when Core is halted - * @arg MCUDBG_I2C1_HOLD: I2C1 SMBUS timeout mode hold when Core is halted - * @arg MCUDBG_I2C2_HOLD: I2C2 SMBUS timeout mode hold when Core is halted - * @arg MCUDBG_TIMER5_HOLD: TIMER5 counter hold when Core is halted - * @arg MCUDBG_TIMER6_HOLD: TIMER6 counter hold when Core is halted - * @arg MCUDBG_TIMER7_HOLD: TIMER7 counter hold when Core is halted - * @arg MCUDBG_TIMER8_HOLD: TIMER8 counter hold when Core is halted - * @arg MCUDBG_CAN2_HOLD: Debug CAN2 hold when Core is halted - * @arg MCUDBG_TIMER12_HOLD: TIMER12 counter hold when Core is halted - * @arg MCUDBG_TIMER13_HOLD: TIMER13 counter hold when Core is halted - * @arg MCUDBG_TIMER14_HOLD: TIMER14 counter hold when Core is halted - * @arg MCUDBG_TIMER9_HOLD: TIMER9 counter hold when Core is halted - * @arg MCUDBG_TIMER10_HOLD: TIMER10 counter hold when Core is halted - * @arg MCUDBG_TIMER11_HOLD: TIMER11 counter hold when Core is halted - * @param NewState: new state of the specified peripheral in Debug mode. - * This parameter can be: ENABLE or DISABLE. - * @retval None - */ -void MCUDBG_PeriphConfig(uint32_t MCUDBG_Periph, TypeState NewValue) -{ - if (NewValue != DISABLE) { - MCUDBG->CTLR |= MCUDBG_Periph; - } else { - MCUDBG->CTLR &= ~MCUDBG_Periph; - } -} -/** - * @} - */ - -/** - * @} - */ - -/** - * @} - */ - diff --git a/bsp/gd32103c-eval/Libraries/GD32F1xx_standard_peripheral/Source/gd32f10x_misc.c b/bsp/gd32103c-eval/Libraries/GD32F1xx_standard_peripheral/Source/gd32f10x_misc.c deleted file mode 100644 index cee195ebc5..0000000000 --- a/bsp/gd32103c-eval/Libraries/GD32F1xx_standard_peripheral/Source/gd32f10x_misc.c +++ /dev/null @@ -1,136 +0,0 @@ -/** - ****************************************************************************** - * @brief MISC functions of the firmware library. - ****************************************************************************** - */ - -/* Includes ------------------------------------------------------------------*/ -#include "gd32f10x_misc.h" - -/** @addtogroup GD32F10x_Firmware - * @{ - */ - -/** @defgroup MISC - * @brief MISC driver modules - * @{ - */ - -/** @defgroup MISC_Private_Defines - * @{ - */ -#define AIRCR_VECTKEY_MASK ((uint32_t)0x05FA0000) - -/** - * @} - */ - -/** @defgroup MISC_Private_Functions - * @{ - */ - -/** - * @brief By the PRIGROUP[10:8] bits of the AIRCR register, Setting the priority grouping: - * pre-emption priority and subpriority. - * @param NVIC_PriGroup: NVIC_PRIGROUP_0, NVIC_PRIGROUP_1,...NVIC_PRIGROUP_4. - * @retval None - */ -void NVIC_PRIGroup_Enable(uint32_t NVIC_PRIGroup) -{ - /* Set the priority grouping value */ - SCB->AIRCR = AIRCR_VECTKEY_MASK | NVIC_PRIGroup; -} - -/** - * @brief The NVIC peripheral Initialization. - * @param NVIC_InitStruct: a NVIC_InitPara structure pointer. - * @retval None - */ -void NVIC_Init(NVIC_InitPara *NVIC_InitStruct) -{ - uint32_t temppriority = 0x00, temppreempt = 0x00, tempsub = 0x00; - - if (NVIC_InitStruct->NVIC_IRQEnable != DISABLE) { - if (((SCB->AIRCR) & (uint32_t)0x700) == NVIC_PRIGROUP_0) { - temppreempt = 0; - tempsub = 0x4; - } else if (((SCB->AIRCR) & (uint32_t)0x700) == NVIC_PRIGROUP_1) { - temppreempt = 1; - tempsub = 0x3; - } else if (((SCB->AIRCR) & (uint32_t)0x700) == NVIC_PRIGROUP_2) { - temppreempt = 2; - tempsub = 0x2; - } else if (((SCB->AIRCR) & (uint32_t)0x700) == NVIC_PRIGROUP_3) { - temppreempt = 3; - tempsub = 0x1; - } else if (((SCB->AIRCR) & (uint32_t)0x700) == NVIC_PRIGROUP_4) { - temppreempt = 4; - tempsub = 0x0; - } - - temppriority = (uint32_t)NVIC_InitStruct->NVIC_IRQPreemptPriority << (0x4 - temppreempt); - temppriority |= NVIC_InitStruct->NVIC_IRQSubPriority & (0x0F >> (0x4 - tempsub)); - temppriority = temppriority << 0x04; - - NVIC->IP[NVIC_InitStruct->NVIC_IRQ] = temppriority; - - /* Enable the Selected IRQ Channels */ - NVIC->ISER[NVIC_InitStruct->NVIC_IRQ >> 0x05] = (uint32_t)0x01 << (NVIC_InitStruct->NVIC_IRQ & (uint8_t)0x1F); - } else { - /* Disable the Selected IRQ Channels */ - NVIC->ICER[NVIC_InitStruct->NVIC_IRQ >> 0x05] = (uint32_t)0x01 << (NVIC_InitStruct->NVIC_IRQ & (uint8_t)0x1F); - } -} - -/** - * @brief Specify the vector table in RAM or FLASH memory and its Offset. - * @param NVIC_VectTab: NVIC_VECTTAB_RAM,NVIC_VECTTAB_FLASH - * @param Offset: Vector Table start address. - * @retval None - */ -void NVIC_VectTableSet(uint32_t NVIC_VectTab, uint32_t Offset) -{ - SCB->VTOR = NVIC_VectTab | (Offset & (uint32_t)0x1FFFFF80); -} - -/** - * @brief Specify the state of the system to enter low power mode. - * @param LowPowerMode: NVIC_LOWPOWER_SEVONPEND,NVIC_LOWPOWER_SLEEPDEEP,NVIC_LOWPOWER_SLEEPONEXIT. - * @param NewValue: new value of Low Power state. This parameter can be: ENABLE or DISABLE. - * @retval None - */ -void NVIC_SystemLowPowerConfig(uint8_t LowPowerMode, TypeState NewValue) -{ - if (NewValue != DISABLE) { - SCB->SCR |= LowPowerMode; - } else { - SCB->SCR &= (~(uint32_t)LowPowerMode); - } -} - -/** - * @brief Specify the SysTick clock source. - * @param SysTick_CKSource: SYSTICK_CKSOURCE_HCLK_DIV8,SYSTICK_CKSOURCE_HCLK. - * @retval None - */ -void SysTick_CKSource_Enable(uint32_t SysTick_CKSource) -{ - if (SysTick_CKSource == SYSTICK_CKSOURCE_HCLK) { - SysTick->CTRL |= SYSTICK_CKSOURCE_HCLK; - } else { - SysTick->CTRL &= SYSTICK_CKSOURCE_HCLK_DIV8; - } -} - -/** - * @} - */ - -/** - * @} - */ - -/** - * @} - */ - diff --git a/bsp/gd32103c-eval/Libraries/GD32F1xx_standard_peripheral/Source/gd32f10x_pwr.c b/bsp/gd32103c-eval/Libraries/GD32F1xx_standard_peripheral/Source/gd32f10x_pwr.c deleted file mode 100644 index cd44b98dfe..0000000000 --- a/bsp/gd32103c-eval/Libraries/GD32F1xx_standard_peripheral/Source/gd32f10x_pwr.c +++ /dev/null @@ -1,333 +0,0 @@ -/** - ****************************************************************************** - * @brief PWR functions of the firmware library. - ****************************************************************************** - */ - -/* Includes ------------------------------------------------------------------*/ -#include "gd32f10x_pwr.h" -#include "gd32f10x_rcc.h" - -/** @addtogroup GD32F10x_Firmware - * @{ - */ - -/** @defgroup PWR - * @brief PWR driver modules - * @{ - */ - -/** @defgroup PWR_Private_Defines - * @{ - */ -/* Left shift SBF or WUF(PWR_STR) to SBFR or WUFR(PWR_CTLR) */ -#define BIT_SHIFT 2 - -/** - * @} - */ - -/** @defgroup PWR_Private_Functions - * @{ - */ - -/** - * @brief Reset the PWR peripheral registers. - * @param None - * @retval None - */ -void PWR_DeInit(void) -{ - RCC_APB1PeriphReset_Enable(RCC_APB1PERIPH_PWRRST, ENABLE); - RCC_APB1PeriphReset_Enable(RCC_APB1PERIPH_PWRRST, DISABLE); -} - -/** - * @brief Enable or disable write access to the registers in Backup domain. - * @note After reset, any write access to the registers in Backup domain is disabled. - * This bit has to be set to enable write access to these registers. - * @param NewValue: New value of write access state to the registers in Backup domain. - * This parameter can be: ENABLE or DISABLE. - * @retval None - */ -void PWR_BackupAccess_Enable(TypeState NewValue) -{ - if (NewValue != DISABLE) { - /* Enable the Backup Domain Access */ - PWR->CTLR |= PWR_CTLR_BKPWE; - } else { - /* Disable the Backup Domain Access */ - PWR->CTLR &= ~((uint32_t)PWR_CTLR_BKPWE); - } -} - -/** - * @brief Enable or disable the LVD(Low Voltage Detector), and configure the voltage - * threshold detected by the LVD. - * @note The LVDE bit controls whether LVD is enabled or not, while the LVDT[2:0] - * bits select the LVDT from 2.2V to 2.9V. - * @note The LVD is stopped in Standby mode. - * @param PWR_LVDT: the LVD threshold. - * This parameter can be one of the following values: - * @arg PWR_LVDT_0 - * @arg PWR_LVDT_1 - * @arg PWR_LVDT_2 - * @arg PWR_LVDT_3 - * @arg PWR_LVDT_4 - * @arg PWR_LVDT_5 - * @arg PWR_LVDT_6 - * @arg PWR_LVDT_7 - * @param NewValue: New value of the LVD state. - * This parameter can be: ENABLE or DISABLE. - * @retval None - */ -void PWR_LVDConfig(uint32_t PWR_LVDT, TypeState NewValue) -{ - uint32_t temp = 0; - - temp = PWR->CTLR; - - /* Clear LVDT[7:5] bits */ - temp &= ~((uint32_t)PWR_CTLR_LVDT); - - /* Set LVDT[7:5] bits according to PWR_LVDT value */ - temp |= PWR_LVDT; - - /* Store the new value */ - PWR->CTLR = temp; - - /* Enable or disable the LVD */ - if (NewValue != DISABLE) { - /* Enable the LVD */ - PWR->CTLR |= PWR_CTLR_LVDE; - } else { - /* Disable the LVD */ - PWR->CTLR &= ~((uint32_t)PWR_CTLR_LVDE); - } -} - -/** - * @brief Enable or disable the WakeUp Pin(PA0 pin) function. - * @note If WUPE is set before entering the power saving mode, - * a rising edge on the WKUP Pin wakes up the system from the power - * saving mode. As the WKUP pin is active high, it will setup - * an input pull down mode when this bit is high. - * @param NewValue: New value of the WKUP Pin state. - * This parameter can be: ENABLE or DISABLE. - * @retval None - */ -void PWR_WKUP_Pin_Enable(TypeState NewValue) -{ - if (NewValue != DISABLE) { - /* Enable the WKUP pin */ - PWR->STR |= PWR_STR_WUPE; - } else { - /* Disable the WKUP pin */ - PWR->STR &= ~PWR_STR_WUPE; - } -} - -/** - *@verbatim - - [..] The GD32F10x series of devices provide three types of power saving modes. - - *** Sleep mode *** - ================== - [..] The Sleep mode is based on the SLEEPING mode of the Cortex-M3. In Sleep - mode, only clock of Cortex-M3 is off. - (+) Entry: - (++) To enter the Sleep mode, it is only necessary to clear SLEEPDEEP bit - in the Cortex-M3 System Control Register, and execute a WFI or WFE - instruction. - (++) The Sleep mode is entered using the PWR_SLEEPMode_Entry() function. - (+) Wakeup: - (++) Any interrupt for WFI or Any event for WFE. - (+) Wakeup Latency: - (++) None - - *** Deep-sleep mode *** - ================= - [..] The Deep-sleep mode is based on the SLEEPDEEP mode of the Cortex-M3. In - Deep-sleep mode, all clocks in the 1.2V domain are off, and all of HSI, - HSE and PLL are disabled. The LDO can operate normally or in low - power mode depending on the LDOLP bit in the PWR_CTLR register. - (+) Entry: - (++) Before entering the Deep-sleep mode, it is necessary to set the - SLEEPDEEP bit in the Cortex-M3 System Control Register, and clear - the SDBM bit in the PWR_CTLR register. - (++) The Deep-sleep mode is entered using the PWR_DEEPSLEEPMode_Entry() - function. - (+) Wakeup: - (++) Any interrupt or event from EXTI Lines. - (+) Wakeup Latency: - (++) HSI wakeup time; LDO wakeup time if LDO is in low power mode. - - *** Standby mode *** - ==================== - [..] The Standby mode is based on the SLEEPDEEP mode of the Cortex-M3. In Standby - mode, the whole 1.2V domain is power off, the LDO is shut down, and all of - HSI, HSE and PLL are disabled. Besides, the contents of SRAM and - registers(except Backup Registers) are lost in Standby mode. - (+) Entry: - (++) Before entering the Standby mode, it is necessary to set the - SLEEPDEEP bit in the Cortex-M3 System Control Register, and set - the SDBM bit in the PWR_CTLR register, and clear WUF bit in the - PWR_STR register. . - (++) The Standby mode is entered using the PWR_STDBYMode_Entry() function. - (+) Wakeup: - (++) NRST pin, WKUP pin rising edge, RTC alarm, IWDG reset. - (+) Wakeup Latency: - (++) Power on sequence - *@endverbatim - */ -/** - * @brief Enter Sleep mode. - * @note By default, this function selects the Sleep-now entry mechanism (SLEEPONEXIT = 0). - * @param PWR_SLEEPENTRY: WFI or WFE instruction. - * This parameter can be one of the following values: - * @arg PWR_SLEEPENTRY_WFI: enter Sleep mode with WFI instruction - * @arg PWR_SLEEPENTRY_WFE: enter Sleep mode with WFE instruction - * @retval None - */ -void PWR_SLEEPMode_Entry(uint8_t PWR_SLEEPENTRY) -{ - /* Clear SLEEPDEEP bit of Cortex-M3 System Control Register */ - SCB->SCR &= ~((uint32_t)SCB_SCR_SLEEPDEEP_Msk); - - /* Select WFI or WFE to enter Sleep mode */ - if (PWR_SLEEPENTRY == PWR_SLEEPENTRY_WFI) { - __WFI(); - } else { - __WFE(); - } -} - -/** - * @brief Enter Deep-sleep mode. - * @note When exiting Deep-sleep mode, the HSI is selected as the system clock. - * @note An additional wakeup delay will be incurred if the LDO operates in - * low power mode. - * @param PWR_LDO: the LDO state in Deep-sleep mode. - * This parameter can be one of the following values: - * @arg PWR_LDO_ON: Deep-sleep mode with LDO ON - * @arg PWR_LDO_LOWPOWER: Deep-sleep mode with LDO in low power mode - * @param PWR_DEEPSLEEPENTRY: WFI or WFE instruction. - * This parameter can be one of the following values: - * @arg PWR_DEEPSLEEPENTRY_WFI: enter Deep-sleep mode with WFI instruction - * @arg PWR_DEEPSLEEPENTRY_WFE: enter Deep-sleep mode with WFE instruction - * @retval None - */ -void PWR_DEEPSLEEPMode_Entry(uint32_t PWR_LDO, uint8_t PWR_DEEPSLEEPENTRY) -{ - uint32_t temp = 0; - - /* Select the LDO state in Deep-sleep mode */ - temp = PWR->CTLR; - - /* Clear SDBM and LDOLP bits, and select Deep-sleep mode */ - temp &= ~((uint32_t)(PWR_CTLR_SDBM | PWR_CTLR_LDOLP)); - - /* Set LDOLP bit according to PWR_LDO value, and select the LDO's state */ - temp |= PWR_LDO; - - /* Store the new value */ - PWR->CTLR = temp; - - /* Set SLEEPDEEP bit of Cortex-M3 System Control Register */ - SCB->SCR |= SCB_SCR_SLEEPDEEP_Msk; - - /* Select WFI or WFE to enter Deep-sleep mode */ - if (PWR_DEEPSLEEPENTRY == PWR_DEEPSLEEPENTRY_WFI) { - __WFI(); - } else { - __SEV(); - __WFE(); - __WFE(); - } - /* Reset SLEEPDEEP bit of Cortex-M3 System Control Register */ - SCB->SCR &= ~((uint32_t)SCB_SCR_SLEEPDEEP_Msk); -} - -/** - * @brief Enter Standby mode. - * @note The Standby mode achieves the lowest power consumption, but spends - * longest time to wake up. - * @note When exiting from the Standby mode, a power-on reset occurs and the - * Cortex-M3 will execute instructions code from the 0x0000_0000 address. - * @param PWR_STDBYENTRY: WFI or WFE instruction. - * This parameter can be one of the following values: - * @arg PWR_STDBYENTRY_WFI: enter Standby mode with WFI instruction - * @arg PWR_STDBYENTRY_WFE: enter Standby mode with WFE instruction - * @retval None - */ -void PWR_STDBYMode_Entry(uint8_t PWR_STDBYENTRY) -{ - /* Set SLEEPDEEP bit of Cortex-M3 System Control Register */ - SCB->SCR |= SCB_SCR_SLEEPDEEP_Msk; - - /* Set SDBM bit, and select Standby mode */ - PWR->CTLR |= PWR_CTLR_SDBM; - - /* Reset Wakeup flag */ - PWR->CTLR |= PWR_CTLR_WUFR; - - /* Select WFI or WFE to enter Standby mode */ - if (PWR_STDBYENTRY == PWR_STDBYENTRY_WFI) { - __WFI(); - } else { - __WFE(); - } -} - -/** - * @brief Get the bit flag of some PWR_STR registers. - * @param PWR_FLAG: the flag of PWR_STR registers. - * This parameter can be one of the following values: - * @arg PWR_FLAG_WKUP: WakeUp flag. This flag indicates that a wakeup - * event was received from the WKUP pin or from the RTC alarm, - * IWDG reset or NRST pin. - * @arg PWR_FLAG_STB: StandBy flag. This flag indicates that the - * system has been in Standby mode. - * @arg PWR_FLAG_LVDF: LVD State flag. This flag is valid only if LVD - * is enabled by the PWR_LVD_Config()function. - * @retval The new value of PWR_FLAG (SET or RESET). - */ -TypeState PWR_GetBitState(uint32_t PWR_FLAG) -{ - /* Check and get the selected PWR flag */ - if ((PWR->STR & PWR_FLAG) != (uint32_t)RESET) { - /* PWR_FLAG bit is SET */ - return SET; - } else { - /* PWR_FLAG bit is RESET */ - return RESET; - } -} - -/** - * @brief Clear the bit flag of some PWR_STR registers. - * @param PWR_FLAG: the flag of PWR_STR registers. - * This parameter can be one of the following values: - * @arg PWR_FLAG_WKUP: Wake_Up flag - * @arg PWR_FLAG_STB: StandBy flag - * @retval None - */ -void PWR_ClearBitState(uint32_t PWR_FLAG) -{ - /* Clear the selected PWR flag */ - PWR->CTLR |= PWR_FLAG << BIT_SHIFT; -} - -/** - * @} - */ - -/** - * @} - */ - -/** - * @} - */ - diff --git a/bsp/gd32103c-eval/Libraries/GD32F1xx_standard_peripheral/Source/gd32f10x_rcc.c b/bsp/gd32103c-eval/Libraries/GD32F1xx_standard_peripheral/Source/gd32f10x_rcc.c deleted file mode 100644 index f14e848695..0000000000 --- a/bsp/gd32103c-eval/Libraries/GD32F1xx_standard_peripheral/Source/gd32f10x_rcc.c +++ /dev/null @@ -1,1323 +0,0 @@ -/** - ****************************************************************************** - * @brief RCC functions of the firmware library. - ****************************************************************************** - */ - -/* Includes ------------------------------------------------------------------*/ -#include "gd32f10x_rcc.h" - -/** @addtogroup GD32F10x_Firmware - * @{ - */ - -/** @defgroup RCC - * @brief RCC driver modules - * @{ - */ - -/** @defgroup RCC_Private_Defines - * @{ - */ - - -/* RCC GCCR_HSIEN mask */ -#define GCCR_HSIEN_SET ((uint32_t)0x00000001) - -/* RCC GCFGR_Reset mask */ -#define GCFGR_RESET_CL ((uint32_t)0xE0FF0000) -#define GCFGR_RESET ((uint32_t)0xE8FF0000) - -/* RCC GCCR_HSEEN_CKMEN_PLLEN masks */ -#define GCCR_HSEEN_CKMEN_PLLEN_RESET ((uint32_t)0xFEF6FFFF) - -/* RCC GCCR_HSEBPS mask */ -#define GCCR_HSEBPS_RESET ((uint32_t)0xFFFBFFFF) - -/* RCC GCFGR_PLLSEL_PLLPREDV_PLLMF masks */ -#define GCFGR_PLLSEL_PLLPREDV_PLLMF_USBPS_RESET ((uint32_t)0xF700FFFF) -#define GCFGR_PLLSEL_PLLPREDV_PLLMF_OTGFSPS_RESET_CL ((uint32_t)0xDF00FFFF) - -/* RCC GCCR_PLL2EN_PLL3EN masks */ -#define GCCR_PLL2EN_PLL3EN_RESET ((uint32_t)0xEBFFFFFF) - -/* RCC GCFGR2 reset */ -#define GCFGR2_RESET ((uint32_t)0x00000000) - -/* RCC GCIR_INT ans FLAG masks */ -#define GCIR_INT_FLAG_RESET ((uint32_t)0x009F0000) -#define GCIR_INT_FLAG_RESET_CL ((uint32_t)0x00FF0000) - -#define GCCR_HSEEN_HSEBPS_RESET ((uint32_t)0xFFFAFFFF) - -/* RCC GCCR_HSIADJ masks */ -#define GCCR_HSIADJ_OFFSET ((uint32_t)0x00000003) - - -#define RCC_GCFGR_PLLMF_3_0 ((uint32_t)0x003C0000) /*!< PLLMF[3:0] Bits */ - -/* RCC HSI clock divided by 2 masks */ -#define HSI_CLOCK_DIVIDED_2 ((uint32_t)0x00000001) - -/* RCC HSE clock divided by 2 masks */ -#define HSE_CLOCK_DIVIDED_2 ((uint32_t)0x00000001) - - -static __I uint8_t AHBPrescTable[16] = {0, 0, 0, 0, 0, 0, 0, 0, 1, 2, 3, 4, 6, 7, 8, 9}; -static __I uint8_t APBPrescTable[8] = {0, 0, 0, 0, 1, 2, 3, 4}; - - -/* GCIR register byte 1 (Bits[15:8]) base address */ -#define GCIR_BYTE1_ADDRESS ((uint32_t)0x40021009) - -/* GCIR register byte 2 (Bits[23:16]) base address */ -#define GCIR_BYTE2_ADDRESS ((uint32_t)0x4002100A) - -/* RCC Flag Mask */ -#define FLAG_MASK ((uint8_t)0x1F) - -/** - * @} - */ - -/** @defgroup RCC_Private_Functions - * @{ - */ - -/** - * @brief Reset the RCC clock configuration. - * @param None - * @retval None - */ -void RCC_DeInit(void) -{ - /* Set RCC GCCR_HSIEN mask */ - RCC->GCCR |= GCCR_HSIEN_SET; - - /* Reset SCS[1:0], AHBPS[3:0], APB1PS[2:0],APB2PS[2:0], ADCPS[2:0],CKOTUSEL[2:0] bits */ -#ifdef GD32F10X_CL - RCC->GCFGR &= GCFGR_RESET_CL; -#else - RCC->GCFGR &= GCFGR_RESET; -#endif /* GD32F10X_CL */ - - /* Reset HSEEN, CKMEN and PLLEN bits */ - RCC->GCCR &= GCCR_HSEEN_CKMEN_PLLEN_RESET; - - /* Reset HSEBPS bit */ - RCC->GCCR &= GCCR_HSEBPS_RESET; - - /* Reset PLLSEL, PLLPREDV and PLLMF[4:0] USBPS/OTGFSPS bits */ -#ifdef GD32F10X_CL - RCC->GCFGR &= GCFGR_PLLSEL_PLLPREDV_PLLMF_OTGFSPS_RESET_CL; -#else - RCC->GCFGR &= GCFGR_PLLSEL_PLLPREDV_PLLMF_USBPS_RESET; -#endif /* GD32F10X_CL */ - -#ifdef GD32F10X_CL - /* Reset PLL2EN and PLL3EN bits */ - RCC->GCCR &= GCCR_PLL2EN_PLL3EN_RESET; - - /* Reset GCFGR2 register */ - RCC->GCFGR2 = GCFGR2_RESET ; - - /* Disable all interrupts and clear flag bits */ - RCC->GCIR = GCIR_INT_FLAG_RESET_CL; -#else - /* Disable all interrupts and clear flag bits */ - RCC->GCIR = GCIR_INT_FLAG_RESET; -#endif /* GD32F10X_CL */ -} - -/** - * @brief Configure the External High Speed oscillator (HSE). - * @param RCC_HSE: specify the new state of HSE. - * This parameter can be one of the following values: - * @arg RCC_HSE_OFF: turn off the HSE - * @arg RCC_HSE_ON: turn on the HSE - * @arg RCC_HSE_BYPASS: HSE bypassed with external clock - * @retval None - */ -void RCC_HSEConfig(uint32_t RCC_HSE) -{ - /* Reset HSEEN and HSEBPS bits */ - RCC->GCCR &= GCCR_HSEEN_HSEBPS_RESET; - /* Set the new state of HSE */ - RCC->GCCR |= RCC_HSE; - -} - -/** - * @brief Wait for HSE start-up. - * @param None - * @retval The HSE start-up result(SUCCESS or ERROR) - */ -TypeState RCC_WaitForHSEStartUp(void) -{ - __IO uint32_t HSE_StartOk_Counter = 0; - TypeState HSEState = RESET; - - /* Wait until HSE is ready and if timeout to exit */ - while ((HSE_StartOk_Counter != HSE_STARTUP_TIMEOUT) && (HSEState == RESET)) { - HSEState = RCC_GetBitState(RCC_FLAG_HSESTB); - HSE_StartOk_Counter++; - } - - if (RCC_GetBitState(RCC_FLAG_HSESTB) != RESET) { - return SUCCESS; - } else { - return ERROR; - } -} - -/** - * @brief Adjust the Internal High Speed oscillator (HSI) calibration value. - * @param HSICalibrationValue: the HSI calibration value. - * This parameter must be between 0 and 0x1F. - * @retval None - */ -void RCC_AdjustHSICalibrationValue(uint8_t HSICalibrationValue) -{ - uint32_t temp_adjust = 0; - - temp_adjust = RCC->GCCR; - - /* Clear HSIADJ[4:0] bits */ - temp_adjust &= ~RCC_GCCR_HSIADJ; - - /* Set HSIADJ[4:0] bits according to HSICalibrationValue value */ - temp_adjust |= (uint32_t)HSICalibrationValue << GCCR_HSIADJ_OFFSET ; - - /* Store the calibration value */ - RCC->GCCR = temp_adjust; -} - -/** - * @brief Enable or disable the Internal High Speed oscillator (HSI). - * @param NewValue: new value of the HSI. - * This parameter can be: ENABLE or DISABLE. - * @retval None - */ -void RCC_HSI_Enable(TypeState NewValue) -{ - - if (NewValue != DISABLE) { - RCC->GCCR |= RCC_GCCR_HSIEN; - } else { - RCC->GCCR &= ~RCC_GCCR_HSIEN; - } -} - -/** - * @brief Configure the PLL clock source and multiplication factor. - * @param RCC_PLLSelect: specify the PLL clock source. - * For @b GD32_Connectivity_line_devices, this parameter can be one of the following values: - * @arg RCC_PLLSOURCE_HSI_DIV2: HSI divided by 2 selected as PLL clock source - * @arg RCC_PLLSOURCE_PREDIV1: PREDIV1 clock selected as PLL clock source - * For @b other GD32_devices, this parameter can be one of the following values: - * @arg RCC_PLLSOURCE_HSI_DIV2: HSI divided by 2 selected as PLL clock source - * @arg RCC_PLLSOURCE_HSE_DIV1: HSE selected as PLL clock source - * @arg RCC_PLLSOURCE_HSE_DIV2: HSE divided by 2 selected as PLL clock source - * @param RCC_PLLMF: specify the PLL multiplication factor. - * For @b GD32_Connectivity_line_devices, this parameter can be RCC_PLLMUL_x where x:{[2,32], 6_5} - * For @b other_GD32_devices, this parameter can be RCC_PLLMUL_x where x:[2,32] - * @retval None - */ -void RCC_PLLConfig(uint32_t RCC_PLLSelect, uint32_t RCC_PLLMF) -{ - uint32_t temp = 0; - - temp = RCC->GCFGR; - /* Clear PLLSEL [16] and PLLMF[4:0] bits */ - temp &= ~(RCC_GCFGR_PLLMF | RCC_GCFGR_PLLSEL); - /* Set the PLLSEL and PLLMF */ - temp |= RCC_PLLSelect | RCC_PLLMF; - - RCC->GCFGR = temp; -} - -/** - * @brief Enable or disable the PLL. - * @param NewValue: new value of the PLL. - * This parameter can be: ENABLE or DISABLE. - * @retval None - */ -void RCC_PLL_Enable(TypeState NewValue) -{ - if (NewValue != DISABLE) { - RCC->GCCR |= RCC_GCCR_PLLEN; - } else { - RCC->GCCR &= ~RCC_GCCR_PLLEN; - } -} - - -#ifdef GD32F10X_CL -/** - * @brief Configure the PREDV1 division factor. - * @param RCC_PREDV1_Source: specifies the PREDV1 clock source. - * This parameter can be one of the following values: - * @arg RCC_PREDIV1_SOURCE_HSE: HSE selected as PREDIV1 clock - * @arg RCC_PREDIV1_SOURCE_PLL2: PLL2 selected as PREDIV1 clock - * @param RCC_PREDV1_DIV: specify the PREDV1 division factor. - * This parameter can be RCC_PREDIV1_DIVx where x:[1,16] - * @retval None - */ -void RCC_PREDV1Config(uint32_t RCC_PREDV1_Source, uint32_t RCC_PREDV1_Div) -{ - uint32_t temp = 0; - - temp = RCC->GCFGR2; - /* Clear PREDV1[3:0] and PREDV1SEL bits */ - temp &= ~(RCC_GCFGR2_PREDV1 | RCC_GCFGR2_PREDV1SEL); - /* Set the PREDV1 division factor and PREDV1SEL */ - temp |= (RCC_PREDV1_Div | RCC_PREDV1_Source); - - RCC->GCFGR2 = temp; -} - -/** - * @brief Configure the PREDV2 division factor. - * @param RCC_PREDV2_Div: specify the PREDV2 clock division factor. - * This parameter can be RCC_PREDIV2_DIVx where x:[1,16] - * @retval None - */ -void RCC_PREDV2Config(uint32_t RCC_PREDV2_Div) -{ - uint32_t temp = 0; - - temp = RCC->GCFGR2; - /* Clear PREDV2[3:0] bits */ - temp &= ~RCC_GCFGR2_PREDV2; - /* Set the PREDV2 division factor */ - temp |= RCC_PREDV2_Div; - - RCC->GCFGR2 = temp; -} - -/** - * @brief Configure the PLL2 multiplication factor. - * @param RCC_PLL2MF: specify the PLL2 multiplication factor. - * This parameter can be RCC_PLL2MUL_x where x:{[8,14], 16, 20} - * @retval None - */ -void RCC_PLL2Config(uint32_t RCC_PLL2MF) -{ - uint32_t temp = 0; - - temp = RCC->GCFGR2; - /* Clear PLL2MF[3:0] bits */ - temp &= ~RCC_GCFGR2_PLL2MF; - /* Set the PLL2 configuration bits */ - temp |= RCC_PLL2MF; - - RCC->GCFGR2 = temp; -} - - -/** - * @brief Enable or disable the PLL2. - * @param NewValue: new value of the PLL2. - * This parameter can be: ENABLE or DISABLE. - * @retval None - */ -void RCC_PLL2_Enable(TypeState NewValue) -{ - if (NewValue != DISABLE) { - RCC->GCCR |= RCC_GCCR_PLL2EN; - } else { - RCC->GCCR &= ~RCC_GCCR_PLL2EN; - } -} - - -/** - * @brief Configure the PLL3 multiplication factor. - * @param RCC_PLL3MF: specify the PLL3 multiplication factor. - * This parameter can be RCC_PLL3MUL_x where x:{[8,14], 16, 20} - * @retval None - */ -void RCC_PLL3Config(uint32_t RCC_PLL3MF) -{ - uint32_t temp = 0; - - temp = RCC->GCFGR2; - /* Clear PLL2MF[3:0] bits */ - temp &= ~RCC_GCFGR2_PLL3MF; - /* Set the PLL3 configuration bits */ - temp |= RCC_PLL3MF; - - RCC->GCFGR2 = temp; -} - - -/** - * @brief Enable or disable the PLL3. - * @param NewValue: new value of the PLL3. - * This parameter can be: ENABLE or DISABLE. - * @retval None - */ -void RCC_PLL3_Enable(TypeState NewValue) -{ - if (NewValue != DISABLE) { - RCC->GCCR |= RCC_GCCR_PLL3EN; - } else { - RCC->GCCR &= ~RCC_GCCR_PLL3EN; - } -} -#endif /* GD32F10X_CL */ - -/** - * @brief Configure the system clock (CK_SYS) - * @param RCC_SYSCLKSource: specify the system clock source - * This parameter can be one of the following values: - * @arg RCC_SYSCLKSOURCE_HSI: selecte HSI as CK_SYS source - * @arg RCC_SYSCLKSOURCE_HSE: selecte HSE as CK_SYS source - * @arg RCC_SYSCLKSOURCE_PLLCLK: selecte PLL as CK_SYS source - * @retval None - */ -void RCC_CK_SYSConfig(uint32_t RCC_SYSCLKSource) -{ - uint32_t temp = 0; - - temp = RCC->GCFGR; - - /* Clear SCS[1:0] bits */ - temp &= ~RCC_GCFGR_SCS; - - /* Set SCS[1:0] bits according to RCC_SYSCLKSource value */ - temp |= RCC_SYSCLKSource; - - /* Store the new value */ - RCC->GCFGR = temp; -} - -/** - * @brief Get the system clock source. - * @param None - * @retval Get the system clock source. The returned value can be one - * of the following values: - * @arg 0x00: HSI used as CK_SYS source - * @arg 0x04: HSE used as CK_SYS source - * @arg 0x08: PLL used as CK_SYS source - */ -uint8_t RCC_GetCK_SYSSource(void) -{ - return ((uint8_t)(RCC->GCFGR & RCC_GCFGR_SCSS)); -} -/** - * @brief Configure the AHB clock. - * @param RCC_CK_SYSDiv: specify the AHB clock divider. This clock is derived from - * the system clock (CK_SYS). - * This parameter can be one of the following values: - * @arg RCC_SYSCLK_DIV1: AHB clock = CK_SYS - * @arg RCC_SYSCLK_DIV2: AHB clock = CK_SYS/2 - * @arg RCC_SYSCLK_DIV4: AHB clock = CK_SYS/4 - * @arg RCC_SYSCLK_DIV8: AHB clock = CK_SYS/8 - * @arg RCC_SYSCLK_DIV16: AHB clock = CK_SYS/16 - * @arg RCC_SYSCLK_DIV64: AHB clock = CK_SYS/64 - * @arg RCC_SYSCLK_DIV128: AHB clock = CK_SYS/128 - * @arg RCC_SYSCLK_DIV256: AHB clock = CK_SYS/256 - * @arg RCC_SYSCLK_DIV512: AHB clock = CK_SYS/512 - * @retval None - */ -void RCC_AHBConfig(uint32_t RCC_CK_SYSDiv) -{ - uint32_t temp = 0; - - temp = RCC->GCFGR; - - /* Clear AHBPS[3:0] bits */ - temp &= ~RCC_GCFGR_AHBPS; - - /* Set AHBPS[3:0] bits according to RCC_CK_SYSDiv value */ - temp |= RCC_CK_SYSDiv; - - /* Store the new value */ - RCC->GCFGR = temp; -} - -/** - * @brief Configure the APB1 clock. - * @param RCC_APB1: specify the APB1 clock divider. This clock is derived from - * the AHB clock. - * This parameter can be one of the following values: - * @arg RCC_APB1AHB_DIV1: APB1 clock = AHB - * @arg RCC_APB1AHB_DIV2: APB1 clock = AHB/2 - * @arg RCC_APB1AHB_DIV4: APB1 clock = AHB/4 - * @arg RCC_APB1AHB_DIV8: APB1 clock = AHB/8 - * @arg RCC_APB1AHB_DIV16: APB1 clock = AHB/16 - * @retval None - */ -void RCC_APB1Config(uint32_t RCC_APB1) -{ - uint32_t temp = 0; - - temp = RCC->GCFGR; - - /* Clear APB1PS[2:0] bits */ - temp &= ~RCC_GCFGR_APB1PS; - - /* Set APB1PS[2:0] bits according to RCC_APB1 value */ - temp |= RCC_APB1; - - /* Store the new value */ - RCC->GCFGR = temp; -} - -/** - * @brief Configure the APB2 clock. - * @param RCC_APB2: specify the APB2 clock divider. This clock is derived from - * the AHB clock. - * This parameter can be one of the following values: - * @arg RCC_APB2AHB_DIV1: APB2 clock = AHB - * @arg RCC_APB2AHB_DIV2: APB2 clock = AHB/2 - * @arg RCC_APB2AHB_DIV4: APB2 clock = AHB/4 - * @arg RCC_APB2AHB_DIV8: APB2 clock = AHB/8 - * @arg RCC_APB2AHB_DIV16: APB2 clock = AHB/16 - * @retval None - */ -void RCC_APB2Config(uint32_t RCC_APB2) -{ - uint32_t temp = 0; - - temp = RCC->GCFGR; - - /* Clear APB2PS[2:0] bits */ - temp &= ~RCC_GCFGR_APB2PS; - - /* Set APB2PS[2:0] bits according to RCC_APB2 value */ - temp |= RCC_APB2; - - /* Store the new value */ - RCC->GCFGR = temp; -} - -#ifdef GD32F10X_CL -/** - * @brief Configure the USB_OTG clock (USB_OTG CLK). - * @param RCC_OTGFSCLK: specify the USB_OTG clock source. This clock is derived - * from the PLL. - * This parameter can be one of the following values: - * @arg RCC_OTGCLK_PLL_DIV1_5: USB_OTG clock = PLL/1.5 - * @arg RCC_OTGCLK_PLL_DIV1: USB_OTG clock = PLL - * @arg RCC_OTGCLK_PLL_DIV2: USB_OTG clock = PLL/2 - * @arg RCC_OTGCLK_PLL_DIV2_5: USB-OTG clock = PLL/2.5 - * @retval None - */ -void RCC_OTGFSCLKConfig(uint32_t RCC_OTGFSCLK) -{ - - /* Clear OTGFSPS bit */ - RCC->GCFGR &= ~RCC_GCFGR_OTGFSPS; - /* Set OTGFSPS bits according to RCC_OTGFSCLK value */ - RCC->GCFGR |= RCC_OTGFSCLK; - -} - -#else -/** - * @brief Configure the USB clock (USBCLK). - * @param RCC_USBCLK: specify the USB clock source. This clock is derived - * from the PLL. - * This parameter can be one of the following values: - * @arg RCC_USBCLK_PLL_DIV1_5: USB clock = PLL/1.5 - * @arg RCC_USBCLK_PLL_DIV1: USB clock = PLL - * @arg RCC_USBCLK_PLL_DIV2: USB clock = PLL/2 - * @arg RCC_USBCLK_PLL_DIV2_5: USB clock = PLL/2.5 - * @retval None - */ -void RCC_USBCLKConfig(uint32_t RCC_USBCLK) -{ - - /* Clear USBPS bit */ - RCC->GCFGR &= ~RCC_GCFGR_USBPS; - /* Set USBPS bits according to RCC_USBCLK value */ - RCC->GCFGR |= RCC_USBCLK; - -} -#endif /* GD32F10X_CL */ - -/** - * @brief Configure the ADC clock (ADCCLK). - * @param RCC_ADCCLK: specify the ADC clock source. This clock is derived from APB2 clock. - * This parameter can be one of the following values: - * @arg RCC_ADCCLK_APB2_DIV2: ADC clock = APB2/2 - * @arg RCC_ADCCLK_APB2_DIV4: ADC clock = APB2/4 - * @arg RCC_ADCCLK_APB2_DIV6: ADC clock = APB2/6 - * @arg RCC_ADCCLK_APB2_DIV8: ADC clock = APB2/8 - * @arg RCC_ADCCLK_APB2_DIV12: ADC clock = APB2/12 - * @arg RCC_ADCCLK_APB2_DIV16: ADC clock = APB2/16 - * @retval None - */ -void RCC_ADCCLKConfig(uint32_t RCC_ADCCLK) -{ - - /* Clear ADCPS bit */ - RCC->GCFGR &= ~RCC_GCFGR_ADCPS; - /* Set ADCPS bits according to RCC_APB2 value */ - RCC->GCFGR |= RCC_ADCCLK; -} - -#ifdef GD32F10X_CL -/** - * @brief Configure the I2S2 clock source(I2S2CLK). - * @param RCC_I2S2CLK: specify the I2S2 clock source. - * This parameter can be one of the following values: - * @arg RCC_I2S2CLK_SYSCLK: system clock selected as I2S2 clock entry - * @arg RCC_I2S2CLK_PLL3: PLL3 clock selected as I2S2 clock entry - * @note If the RCC_I2S2CLK_PLL3 selected, the I2S2 clock is (PLL3 x 2). - * @retval None - */ -void RCC_I2S2CLKConfig(uint32_t RCC_I2S2CLK) -{ - /* Clear I2S2SEL bit */ - RCC->GCFGR2 &= ~RCC_GCFGR2_I2S2SEL; - /* Set I2S2CLK bits according to RCC_I2S2CLK value */ - RCC->GCFGR2 |= RCC_I2S2CLK; - -} - -/** - * @brief Configure the I2S3 clock source(I2S3CLK). - * @param RCC_I2S3CLK: specify the I2S3 clock source. - * This parameter can be one of the following values: - * @arg RCC_I2S3CLK_SYSCLK: system clock selected as I2S3 clock entry - * @arg RCC_I2S3CLK_PLL3: PLL3 clock selected as I2S3 clock entry - * @note If the RCC_I2S3CLK_PLL3 selected, the I2S3 clock is (PLL3 x 2). - * @retval None - */ -void RCC_I2S3CLKConfig(uint32_t RCC_I2S3CLK) -{ - /* Clear I2S3SEL bit */ - RCC->GCFGR2 &= ~RCC_GCFGR2_I2S3SEL; - /* Set I2S3CLK bits according to RCC_I2S3CLK value */ - RCC->GCFGR2 |= RCC_I2S3CLK; -} -#endif /* GD32F10X_CL */ - -/** - * @brief Configure the External Low Speed oscillator (LSE). - * @param RCC_LSE: specify the new state of the LSE. - * This parameter can be one of the following values: - * @arg RCC_LSE_OFF: turn off the LSE - * @arg RCC_LSE_EN: turn on the LSE - * @arg RCC_LSE_BYPASS: LSE bypassed with external clock - * @retval None - */ -void RCC_LSEConfig(uint32_t RCC_LSE) -{ - - /* Reset LSEEN and LSEBPS bits before configuring the LSE */ - RCC->BDCR &= ~(RCC_BDCR_LSEEN); - RCC->BDCR &= ~(RCC_BDCR_LSEBPS); - - /* Configure LSE */ - RCC->BDCR |= RCC_LSE; -} - - -/** - * @brief Enable or disable the Internal Low Speed oscillator (LSI). - * @param NewValue: new value of the LSI. - * This parameter can be: ENABLE or DISABLE. - * @retval None - */ -void RCC_LSI_Enable(TypeState NewValue) -{ - - if (NewValue != DISABLE) { - RCC->GCSR |= RCC_GCSR_LSIEN; - } else { - RCC->GCSR &= ~RCC_GCSR_LSIEN; - } -} - -/** - * @brief Configure the RTC clock (RTCCLK). - * @param RCC_RTCCLKSource: specify the RTC clock source. - * This parameter can be one of the following values: - * @arg RCC_RTCCLKSOURCE_LSE: selecte LSE as RTC clock - * @arg RCC_RTCCLKSOURCE_LSI: selecte LSI as RTC clock - * @arg RCC_RTCCLKSOURCE_HSE_DIV128: selecte HSE divided by 128 as RTC clock - * @note if using HSE as RTC source, the maximum clock frequency for RTC is 2 MHz. - * @retval None - */ -void RCC_RTCCLKConfig(uint32_t RCC_RTCCLKSource) -{ - /* Clear RTCSEL bit */ - RCC->BDCR &= ~RCC_BDCR_RTCSEL; - /* Select the RTC clock source */ - RCC->BDCR |= RCC_RTCCLKSource; -} - -/** - * @brief Enable or disable the RTC clock. - * @param NewValue: new state of the RTC clock. - * This parameter can be: ENABLE or DISABLE. - * @retval None - */ -void RCC_RTCCLK_Enable(TypeState NewValue) -{ - - if (NewValue != DISABLE) { - RCC->BDCR |= RCC_BDCR_RTCEN; - } else { - RCC->BDCR &= ~RCC_BDCR_RTCEN; - } -} - -/** - * @brief Get the frequencies of the CK_SYS, AHB, APB1, APB2, ADC clocks. - * @retval None - */ -void RCC_GetClocksFreq(RCC_ClocksPara *RCC_Clocks) -{ - uint32_t temp = 0, pllmf = 0, pllmf4 = 0, pllselect = 0, presc = 0; - -#ifdef GD32F10X_CL - uint32_t prediv1select = 0, prediv1factor = 0, prediv2factor = 0, pll2mf = 0; -#endif /* GD32F10X_CL */ - - - /* Get CK_SYS source */ - temp = RCC->GCFGR & RCC_GCFGR_SCSS; - - switch (temp) { - case 0x00: /* HSI used as CK_SYS */ - RCC_Clocks->CK_SYS_Frequency = HSI_VALUE; - break; - case 0x04: /* HSE used as CK_SYS */ - RCC_Clocks->CK_SYS_Frequency = HSE_VALUE; - break; - case 0x08: /* PLL used as CK_SYS */ -#ifdef GD32F10X_CL - /* Get PLL clock source and multiplication factor */ - /* Get PLLMF[3:0] */ - pllmf = RCC->GCFGR & RCC_GCFGR_PLLMF_3_0; - /* Get PLLMF[4] */ - pllmf4 = RCC->GCFGR & RCC_GCFGR_PLLMF_4; - - pllmf4 = ((pllmf4 >> 29) * 16); - - pllmf = (pllmf >> 18) + pllmf4; - if (pllmf == 0x0D) { - /* PLL multiplication factor = PLL input clock * 6.5*/ - /* Beacause of the float number 6.5, pllmf * 2 to remove the float number */ - pllmf = 13 * 2 / 2; - - } else if (pllmf >= 0x0F) { - pllmf += 1; - /* Here is consistent with the above that pllmf * 2 to remove the float number*/ - pllmf = pllmf * 2; - } else { - pllmf += 2; - /* Here is consistent with the above that pllmf * 2 to remove the float number*/ - pllmf = pllmf * 2; - } - - pllselect = RCC->GCFGR & RCC_GCFGR_PLLSEL; - if (pllselect == 0x00) { - /* HSI clock divided by 2 selected as PLL clock source */ - /* Here is consistent with the above that pllmf / 2 */ - RCC_Clocks->CK_SYS_Frequency = (HSI_VALUE >> HSI_CLOCK_DIVIDED_2) * pllmf / 2; - } else { - /* PREDIV1 selected as PLL clock entry */ - - /* Get PREDIV1 clock source and division factor */ - prediv1select = RCC->GCFGR2 & RCC_GCFGR2_PREDV1SEL; - prediv1factor = (RCC->GCFGR2 & RCC_GCFGR2_PREDV1) + 1; - - if (prediv1select == 0) { - /* HSE clock selected as PREDIV1 clock entry */ - /* Here is consistent with the above that pllmf / 2 */ - RCC_Clocks->CK_SYS_Frequency = (HSE_VALUE / prediv1factor) * pllmf / 2; - } else { - /* PLL2 clock selected as PREDIV1 clock entry */ - /* Get PREDIV2 division factor and PLL2 multiplication factor */ - prediv2factor = ((RCC->GCFGR2 & RCC_GCFGR2_PREDV2) >> 4) + 1; - pll2mf = ((RCC->GCFGR2 & RCC_GCFGR2_PLL2MF) >> 8); - if (pll2mf != 15) { - pll2mf += 2; - } else { - pll2mf += 5; - } - /* Here is consistent with the above that pllmf / 2 */ - RCC_Clocks->CK_SYS_Frequency = (((HSE_VALUE / prediv2factor) * pll2mf) / prediv1factor) * pllmf / 2; - } - } -#else - /* Get PLL clock source and multiplication factor */ - /* Get PLLMF[3:0] */ - pllmf = RCC->GCFGR & RCC_GCFGR_PLLMF_3_0; - /* Get PLLMF[4] */ - pllmf4 = RCC->GCFGR & RCC_GCFGR_PLLMF_4; - - pllmf4 = ((pllmf4 >> 27) * 16); - pllmf = (pllmf >> 18) + pllmf4; - if (pllmf >= 0x0F) - pllmf += 1; - else - pllmf += 2; - - pllselect = RCC->GCFGR & RCC_GCFGR_PLLSEL; - if (pllselect == 0x00) { - /* HSI clock divided by 2 selected as PLL clock source */ - RCC_Clocks->CK_SYS_Frequency = (HSI_VALUE >> HSI_CLOCK_DIVIDED_2) * pllmf; - } else { - if ((RCC->GCFGR & RCC_GCFGR_PLLPREDV) != (uint32_t)RESET) { - /* HSE clock divided by 2 */ - RCC_Clocks->CK_SYS_Frequency = (HSE_VALUE >> HSE_CLOCK_DIVIDED_2) * pllmf; - } else { - RCC_Clocks->CK_SYS_Frequency = HSE_VALUE * pllmf; - } - } -#endif/* GD32F10X_CL */ - break; - default: /* HSI used as system clock */ - RCC_Clocks->CK_SYS_Frequency = HSI_VALUE; - break; - } - - /* Get AHB prescaler */ - temp = RCC->GCFGR & RCC_GCFGR_AHBPS; - temp = temp >> 4; - presc = AHBPrescTable[temp]; - /* Get AHB clock frequency */ - RCC_Clocks->AHB_Frequency = RCC_Clocks->CK_SYS_Frequency >> presc; - - /* Get APB1 prescaler */ - temp = RCC->GCFGR & RCC_GCFGR_APB1PS; - temp = temp >> 8; - presc = APBPrescTable[temp]; - /* Get APB1 clock frequency */ - RCC_Clocks->APB1_Frequency = RCC_Clocks->AHB_Frequency >> presc; - - /* Get APB2 prescaler */ - temp = RCC->GCFGR & RCC_GCFGR_APB2PS; - temp = temp >> 11; - presc = APBPrescTable[temp]; - /* Get APB2 clock frequency */ - RCC_Clocks->APB2_Frequency = RCC_Clocks->AHB_Frequency >> presc; - - /* Get ADCCLK clock frequency */ - temp = ((RCC->GCFGR & RCC_GCFGR_ADCPS_2) >> 26); - temp += ((RCC->GCFGR & (RCC_GCFGR_ADCPS_0 | RCC_GCFGR_ADCPS_1)) >> 14); - switch (temp) { - case 0x00: /* ADC Clock is derived from APB2/2 */ - RCC_Clocks->ADCCLK_Frequency = (RCC_Clocks->APB2_Frequency / 2); - break; - case 0x01: /* ADC Clock is derived from APB2/4 */ - RCC_Clocks->ADCCLK_Frequency = (RCC_Clocks->APB2_Frequency / 4); - break; - case 0x02: /* ADC Clock is derived from APB2/6 */ - RCC_Clocks->ADCCLK_Frequency = (RCC_Clocks->APB2_Frequency / 6); - break; - case 0x03: /* ADC Clock is derived from APB2/8 */ - RCC_Clocks->ADCCLK_Frequency = (RCC_Clocks->APB2_Frequency / 8); - break; - case 0x04: /* ADC Clock is derived from APB2/2 */ - RCC_Clocks->ADCCLK_Frequency = (RCC_Clocks->APB2_Frequency / 2); - break; - case 0x05: /* ADC Clock is derived from APB2/12 */ - RCC_Clocks->ADCCLK_Frequency = (RCC_Clocks->APB2_Frequency / 12); - break; - case 0x06: /* ADC Clock is derived from APB2/8 */ - RCC_Clocks->ADCCLK_Frequency = (RCC_Clocks->APB2_Frequency / 8); - break; - case 0x07: /* ADC Clock is derived from APB2/16 */ - RCC_Clocks->ADCCLK_Frequency = (RCC_Clocks->APB2_Frequency / 16); - break; - default: - break; - } -} - -/** - * @brief Enable or disable the AHB peripheral clock. - * @param RCC_AHBPeriph: specify the AHB peripheral clock. - * For @b GD32_Connectivity_line_devices, - * this parameter can be any combination of the following values: - * @arg RCC_AHBPERIPH_DMA1 - * @arg RCC_AHBPERIPH_DMA2 - * @arg RCC_AHBPERIPH_SRAM - * @arg RCC_AHBPERIPH_FMC - * @arg RCC_AHBPERIPH_CRC - * @arg RCC_AHBPERIPH_EXMC - * @arg RCC_AHBPERIPH_OTG_FS - * @arg RCC_AHBPERIPH_ETH_MAC - * @arg RCC_AHBPERIPH_ETH_MAC_RX - * @arg RCC_AHBPERIPH_ETH_MAC_TX - * - * For @b other_GD32_devices, this parameter can be any combination of the - * following values: - * @arg RCC_AHBPERIPH_DMA1 - * @arg RCC_AHBPERIPH_DMA2 - * @arg RCC_AHBPERIPH_SRAM - * @arg RCC_AHBPERIPH_FMC - * @arg RCC_AHBPERIPH_CRC - * @arg RCC_AHBPERIPH_EXMC - * @arg RCC_AHBPERIPH_SDIO - * @param NewValue: new state of the peripheral clock. - * This parameter can be: ENABLE or DISABLE. - * @retval None - */ -void RCC_AHBPeriphClock_Enable(uint32_t RCC_AHBPeriph, TypeState NewValue) -{ - - if (NewValue != DISABLE) { - RCC->AHBCCR |= RCC_AHBPeriph; - } else { - RCC->AHBCCR &= ~RCC_AHBPeriph; - } -} - -/** - * @brief Enable or disable the APB2 peripheral clock. - * @param RCC_APB2Periph: specify the APB2 peripheral clock. - * This parameter can be any combination of the following values: - * @arg RCC_APB2PERIPH_AF - * @arg RCC_APB2PERIPH_GPIOA - * @arg RCC_APB2PERIPH_GPIOB - * @arg RCC_APB2PERIPH_GPIOC - * @arg RCC_APB2PERIPH_GPIOD - * @arg RCC_APB2PERIPH_GPIOE - * @arg RCC_APB2PERIPH_GPIOF - * @arg RCC_APB2PERIPH_GPIOG - * @arg RCC_APB2PERIPH_ADC1 - * @arg RCC_APB2PERIPH_ADC2 - * @arg RCC_APB2PERIPH_TIMER1 - * @arg RCC_APB2PERIPH_SPI1 - * @arg RCC_APB2PERIPH_TIMER8 - * @arg RCC_APB2PERIPH_USART1 - * @arg RCC_APB2PERIPH_ADC3 - * @arg RCC_APB2PERIPH_TIMER9 - * @arg RCC_APB2PERIPH_TIMER10 - * @arg RCC_APB2PERIPH_TIMER11 - * @param NewValue: new state of the peripheral clock. - * This parameter can be: ENABLE or DISABLE. - * @retval None - */ -void RCC_APB2PeriphClock_Enable(uint32_t RCC_APB2Periph, TypeState NewValue) -{ - if (NewValue != DISABLE) { - RCC->APB2CCR |= RCC_APB2Periph; - } else { - RCC->APB2CCR &= ~RCC_APB2Periph; - } -} - -/** - * @brief Enable or disable the APB1 peripheral clock. - * @param RCC_APB1Periph: specify the APB1 peripheral clock. - * This parameter can be any combination of the following values: - * @arg RCC_APB1PERIPH_TIMER2 - * @arg RCC_APB1PERIPH_TIMER3 - * @arg RCC_APB1PERIPH_TIMER4 - * @arg RCC_APB1PERIPH_TIMER5 - * @arg RCC_APB1PERIPH_TIMER6 - * @arg RCC_APB1PERIPH_TIMER7 - * @arg RCC_APB1PERIPH_TIMER12 - * @arg RCC_APB1PERIPH_TIMER13 - * @arg RCC_APB1PERIPH_TIMER14 - * @arg RCC_APB1PERIPH_WWDG - * @arg RCC_APB1PERIPH_SPI2 - * @arg RCC_APB1PERIPH_SPI3, - * @arg RCC_APB1PERIPH_USART2 - * @arg RCC_APB1PERIPH_USART3 - * @arg RCC_APB1PERIPH_UART4 - * @arg RCC_APB1PERIPH_UART5 - * @arg RCC_APB1PERIPH_I2C1 - * @arg RCC_APB1PERIPH_I2C2 - * @arg RCC_APB1PERIPH_USB - * @arg RCC_APB1PERIPH_CAN1 - * @arg RCC_APB1PERIPH_CAN2 - * @arg RCC_APB1PERIPH_BKP - * @arg RCC_APB1PERIPH_PWR - * @arg RCC_APB1PERIPH_DAC - * @param NewState: new state of the specified peripheral clock. - * This parameter can be: ENABLE or DISABLE. - * @retval None - */ -void RCC_APB1PeriphClock_Enable(uint32_t RCC_APB1Periph, TypeState NewValue) -{ - if (NewValue != DISABLE) { - RCC->APB1CCR |= RCC_APB1Periph; - } else { - RCC->APB1CCR &= ~RCC_APB1Periph; - } -} - -#ifdef GD32F10X_CL -/** - * @brief Force or release AHB peripheral reset. - * @param RCC_AHBPeriphRST: specify the AHB peripheral to reset. - * This parameter can be any combination of the following values: - * @arg RCC_AHBPeriph_OTGFSRST - * @arg RCC_AHBPeriph_ETHMACRST - * @param NewState: new state of the specified peripheral reset. - * This parameter can be: ENABLE or DISABLE. - * @retval None - */ -void RCC_AHBPeriphReset_Enable(uint32_t RCC_AHBPeriphRST, TypeState NewValue) -{ - if (NewValue != DISABLE) { - RCC->AHBRCR |= RCC_AHBPeriphRST; - } else { - RCC->AHBRCR &= ~RCC_AHBPeriphRST; - } -} -#endif /* GD32F10X_CL */ - -/** - * @brief Force or release APB2 peripheral reset. - * @param RCC_APB2PeriphRST: specify the APB2 peripheral to reset. - * This parameter can be any combination of the following values: - * @arg RCC_APB2PERIPH_AFRST - * @arg RCC_APB2PERIPH_GPIOARST - * @arg RCC_APB2PERIPH_GPIOBRST - * @arg RCC_APB2PERIPH_GPIOCRST - * @arg RCC_APB2PERIPH_GPIODRST - * @arg RCC_APB2PERIPH_GPIOERST - * @arg RCC_APB2PERIPH_GPIOFRST - * @arg RCC_APB2PERIPH_GPIOGRST - * @arg RCC_APB2PERIPH_ADC1RST - * @arg RCC_APB2PERIPH_ADC2RST - * @arg RCC_APB2PERIPH_TIMER1RST - * @arg RCC_APB2PERIPH_SPI1RST - * @arg RCC_APB2PERIPH_TIMER8RST - * @arg RCC_APB2PERIPH_USART1RST - * @arg RCC_APB2PERIPH_ADC3RST - * @arg RCC_APB2PERIPH_TIMER9RST - * @arg RCC_APB2PERIPH_TIMER10RST - * @arg RCC_APB2PERIPH_TIMER11RST - * @param NewValue: new state of the peripheral reset. - * This parameter can be: ENABLE or DISABLE. - * @retval None - */ -void RCC_APB2PeriphReset_Enable(uint32_t RCC_APB2PeriphRST, TypeState NewValue) -{ - - if (NewValue != DISABLE) { - RCC->APB2RCR |= RCC_APB2PeriphRST; - } else { - RCC->APB2RCR &= ~RCC_APB2PeriphRST; - } -} - - -/** - * @brief Force or release APB1 peripheral reset. - * @param RCC_APB1PeriphRST: specify the APB1 peripheral to reset. - * This parameter can be any combination of the following values: - * @arg RCC_APB1PERIPH_TIMER2RST - * @arg RCC_APB1PERIPH_TIMER3RST - * @arg RCC_APB1PERIPH_TIMER4RST - * @arg RCC_APB1PERIPH_TIMER5RST - * @arg RCC_APB1PERIPH_TIMER6RST - * @arg RCC_APB1PERIPH_TIMER7RST - * @arg RCC_APB1PERIPH_TIMER12RST - * @arg RCC_APB1PERIPH_TIMER13RST - * @arg RCC_APB1PERIPH_TIMER14RST - * @arg RCC_APB1PERIPH_WWDGRST - * @arg RCC_APB1PERIPH_SPI2RST - * @arg RCC_APB1PERIPH_SPI3RST - * @arg RCC_APB1PERIPH_USART2RST - * @arg RCC_APB1PERIPH_USART3RST - * @arg RCC_APB1PERIPH_UART4RST - * @arg RCC_APB1PERIPH_UART5RST - * @arg RCC_APB1PERIPH_I2C1RST - * @arg RCC_APB1PERIPH_I2C2RST - * @arg RCC_APB1PERIPH_USBRST - * @arg RCC_APB1PERIPH_CAN1RST - * @arg RCC_APB1PERIPH_CAN2RST - * @arg RCC_APB1PERIPH_BKPRST - * @arg RCC_APB1PERIPH_PWRRST - * @arg RCC_APB1PERIPH_DACRST - * @param NewValue: new state of the peripheral clock (ENABLE or DISABLE). - * @retval None - */ -void RCC_APB1PeriphReset_Enable(uint32_t RCC_APB1PeriphRST, TypeState NewValue) -{ - if (NewValue != DISABLE) { - RCC->APB1RCR |= RCC_APB1PeriphRST; - } else { - RCC->APB1RCR &= ~RCC_APB1PeriphRST; - } -} - -/** - * @brief Force or release the Backup domain reset. - * @param NewValue: new state of the Backup domain reset (ENABLE or DISABLE). - * @retval None - */ -void RCC_BackupReset_Enable(TypeState NewValue) -{ - - if (NewValue != DISABLE) { - RCC->BDCR |= RCC_BDCR_BKPRST; - } else { - RCC->BDCR &= ~RCC_BDCR_BKPRST; - } -} - -/** - * @brief Enable or disable the Clock Security System. - * @param NewValue: new value of the Clock Security System. - * This parameter can be: ENABLE or DISABLE. - * @retval None - */ -void RCC_HSEClockMonitor_Enable(TypeState NewValue) -{ - if (NewValue != DISABLE) { - RCC->GCCR |= RCC_GCCR_CKMEN; - } else { - RCC->GCCR &= ~RCC_GCCR_CKMEN; - } -} - -/** - * @brief Select the clock source to output on CKOUTSRC and the corresponding prescaler. - * @param RCC_CKOUTSRC: specify the clock source to output. - * For @b GD32_Connectivity_line_devices, this parameter can be one of the - * following values: - * @arg RCC_CKOUTSRC_NOCLOCK: No clock selected - * @arg RCC_CKOUTSRC_SYSCLK: System clock selected - * @arg RCC_CKOUTSRC_HSI: HSI oscillator clock selected - * @arg RCC_CKOUTSRC_HSE: HSE oscillator clock selected - * @arg RCC_CKOUTSRC_PLL2CLK: PLL2 clock selected - * @arg RCC_CKOUTSRC_PLLCLK_DIV2: PLL clock divided by 2 selected - * @arg RCC_CKOUTSRC_PLL3CLK: PLL3 clock selected - * @arg RCC_CKOUTSRC_PLL3CLK_DIV2: PLL3 clock divided by 2 selected - * @arg RCC_CKOUTSRC_EXT1: External 3-25 MHz oscillator clock selected - * For @b other_GD32_devices, this parameter can be one of the following values: - * @arg RCC_CKOUTSRC_NOCLOCK: No clock selected - * @arg RCC_CKOUTSRC_SYSCLK: System clock selected - * @arg RCC_CKOUTSRC_HSI: HSI oscillator clock selected - * @arg RCC_CKOUTSRC_HSE: HSE oscillator clock selected - * @arg RCC_CKOUTSRC_PLLCLK_DIV2: PLL clock divided by 2 selected - * @retval None - */ - -void RCC_CKOUTSRCConfig(uint32_t RCC_CKOUTSRC) -{ - uint32_t temp = 0; - - temp = RCC->GCFGR; - /* Clear CKOUTSRC[2:0] bits */ - temp &= ~(RCC_GCFGR_CKOUTSEL); - /* Set the RCC_CKOUTSRC */ - temp |= RCC_CKOUTSRC; - /* Store the new value */ - RCC->GCFGR = temp; -} - - -/** - * @brief Enable or disable RCC interrupts. - * @param RCC_INT: specify the RCC interrupt sources. - * For @b GD32_Connectivity_line_devices, this parameter can be any combination - * of the following values - * @arg RCC_INT_LSISTB: LSI ready interrupt - * @arg RCC_INT_LSESTB LSE ready interrupt - * @arg RCC_INT_HSISTB: HSI ready interrupt - * @arg RCC_INT_HSESTB: HSE ready interrupt - * @arg RCC_INT_PLLSTB: PLL ready interrupt - * @arg RCC_INT_PLL2STB: PLL2 ready interrupt - * @arg RCC_INT_PLL3STB: PLL3 ready interrupt - * - * For @b other_GD32_devices, this parameter can be any combination of the - * following values - * @arg RCC_INT_LSISTB: LSI ready interrupt - * @arg RCC_INT_LSESTB: LSE ready interrupt - * @arg RCC_INT_HSISTB: HSI ready interrupt - * @arg RCC_INT_HSESTB: HSE ready interrupt - * @arg RCC_INT_PLLSTB: PLL ready interrupt - * @param NewValue: new state of the RCC interrupts (ENABLE or DISABLE). - * @retval None - */ -void RCC_INTConfig(uint8_t RCC_INT, TypeState NewValue) -{ - if (NewValue != DISABLE) { - /* Perform Byte access to RCC_GCIR[14:8] bits to enable the selected interrupts */ - *(__IO uint8_t *) GCIR_BYTE1_ADDRESS |= RCC_INT; - } else { - /* Perform Byte access to RCC_GCIR bits to disable the selected interrupts */ - *(__IO uint8_t *) GCIR_BYTE1_ADDRESS &= (uint8_t)~RCC_INT; - } -} - - -/** - * @brief Check whether the specified RCC flag is set or not. - * @param RCC_FLAG: specify the flag to check. - * For @b GD32_Connectivity_line_devices, this parameter can be one of the - * following values: - * @arg RCC_FLAG_HSISTB: HSI clock ready - * @arg RCC_FLAG_HSESTB: HSE clock ready - * @arg RCC_FLAG_PLLSTB: PLL clock ready - * @arg RCC_FLAG_PLL2STB: PLL2 clock ready - * @arg RCC_FLAG_PLL3STB: PLL3 clock ready - * @arg RCC_FLAG_LSESTB: LSE clock ready - * @arg RCC_FLAG_LSISTB: LSI clock ready - * @arg RCC_FLAG_EPRST: Pin reset - * @arg RCC_FLAG_POPDRST: POR/PDR reset - * @arg RCC_FLAG_SWRRST: Software reset - * @arg RCC_FLAG_IWDGRST: Independent Watchdog reset - * @arg RCC_FLAG_WWDGRST: Window Watchdog reset - * @arg RCC_FLAG_LPRRST: Low Power reset - * For @b other_GD32_devices, this parameter can be one of the following values: - * @arg RCC_FLAG_HSISTB: HSI oscillator clock ready - * @arg RCC_FLAG_HSESTB: HSE oscillator clock ready - * @arg RCC_FLAG_PLLSTB: PLL clock ready - * @arg RCC_FLAG_LSESTB: LSE oscillator clock ready - * @arg RCC_FLAG_LSISTB: LSI oscillator clock ready - * @arg RCC_FLAG_EPRST: Pin reset - * @arg RCC_FLAG_POPDRST: POR/PDR reset - * @arg RCC_FLAG_SWRRST: Software reset - * @arg RCC_FLAG_IWDGRST: Independent Watchdog reset - * @arg RCC_FLAG_WWDGRST: Window Watchdog reset - * @arg RCC_FLAG_LPRRST: Low Power reset - * @retval The new state of RCC_FLAG (SET or RESET). - */ -TypeState RCC_GetBitState(uint8_t RCC_FLAG) -{ - uint32_t temp = 0; - uint32_t statusreg = 0; - - /* Get the RCC register index */ - temp = RCC_FLAG >> 5; - - /* The flag to check is in GCCR register */ - if (temp == 1) { - statusreg = RCC->GCCR; - } - - /* The flag to check is in BDCR register */ - else if (temp == 2) { - statusreg = RCC->BDCR; - } - - /* The flag to check is in GCSR register */ - else { - statusreg = RCC->GCSR; - } - - /* Get the flag position */ - temp = RCC_FLAG & FLAG_MASK; - if ((statusreg & ((uint32_t)(1 << temp))) != (uint32_t)RESET) { - return SET; - } else { - return RESET; - } - -} - -/** - * @brief Clear the RCC all reset flags. - * @param None - * @retval None - */ -void RCC_ClearBitState(void) -{ - /* Set RSTFC bit to clear all reset flags */ - RCC->GCSR |= RCC_GCSR_RSTFC; -} - - -/** - * @brief Check whether the RCC interrupt has occurred or not. - * @param RCC_INT: specify the RCC interrupt source to check. - * For @b GD32_Connectivity_line_devices, this parameter can be one of the - * following values: - * @arg RCC_INT_LSISTB: the flag of LSI ready interrupt - * @arg RCC_INT_LSESTB: the flag of LSE ready interrupt - * @arg RCC_INT_HSISTB: the flag of HSI ready interrupt - * @arg RCC_INT_HSESTB: the flag of HSE ready interrupt - * @arg RCC_INT_PLLSTB: the flag of PLL ready interrupt - * @arg RCC_INT_PLL2STB: the flag of PLL2 ready interrupt - * @arg RCC_INT_PLL3STB: the flag of PLL3 ready interrupt - * @arg RCC_INT_CKM: the flag of Clock Security System interrupt - * For @b other_GD32_devices, this parameter can be one of the following values: - * @arg RCC_INT_LSISTB: the flag of LSI ready interrupt - * @arg RCC_INT_LSESTB: the flag of LSE ready interrupt - * @arg RCC_INT_HSISTB: the flag of HSI ready interrupt - * @arg RCC_INT_HSESTB: the flag of HSE ready interrupt - * @arg RCC_INT_PLLSTB: the flag of PLL ready interrupt - * @arg RCC_INT_CKM: the flag of Clock Security System interrupt - * @retval The new state of RCC_INT (SET or RESET). - */ -TypeState RCC_GetIntBitState(uint8_t RCC_INT) -{ - /* Check the status of the RCC interrupt */ - if ((RCC->GCIR & RCC_INT) != (uint32_t)RESET) { - return SET; - } else { - return RESET; - } -} -/** - * @brief Clear the RCC interrupt bits. - * @param RCC_INT: specify the interrupt bit to clear. - * For @b GD32_Connectivity_line_devices, this parameter can be any combination - * of the following values: - * @arg RCC_INT_LSISTB: LSI ready interrupt - * @arg RCC_INT_LSESTB LSE ready interrupt - * @arg RCC_INT_HSISTB: HSI ready interrupt - * @arg RCC_INT_HSESTB: HSE ready interrupt - * @arg RCC_INT_PLLSTB: PLL ready interrupt - * @arg RCC_INT_PLL2STB: PLL2 ready interrupt - * @arg RCC_INT_PLL3STB: PLL3 ready interrupt - * @arg RCC_INT_CKM: Clock Security System interrupt - * For @b other_GD32_devices, this parameter can be any combination of the - * following values - * @arg RCC_INT_LSISTB: LSI ready interrupt - * @arg RCC_INT_LSESTB: LSE ready interrupt - * @arg RCC_INT_HSISTB: HSI ready interrupt - * @arg RCC_INT_HSESTB: HSE ready interrupt - * @arg RCC_INT_PLLSTB: PLL ready interrupt - * @arg RCC_INT_CKM: Clock Security System interrupt - * @retval None - */ - -void RCC_ClearIntBitState(uint8_t RCC_INT) -{ - - - /* Perform RCC_GCIR[23:16] bits to clear the selected interrupt bits */ - *(__IO uint8_t *) GCIR_BYTE2_ADDRESS = RCC_INT; -} - -/** - * @brief Configure the kernel voltage in Deep-sleep mode. - * @note Only unlock the power,this configuration is effective. - * @param RCC_KERNEL_VOL: specify the kernel voltage. - * This parameter can be one of the following values: - * @arg RCC_KERNEL_VOL1_2: The kernel voltage in Deep-sleep mode is 1.2V - * @arg RCC_KERNEL_VOL1_1: The kernel voltage in Deep-sleep mode is 1.1V - * @arg RCC_KERNEL_VOL1_0: The kernel voltage in Deep-sleep mode is 1.0V - * @arg RCC_KERNEL_VOL0_9: The kernel voltage in Deep-sleep mode is 0.9V - * @retval None - */ -void RCC_KERNELVOLConfig(uint32_t RCC_KERNEL_VOL) -{ - /* Clear DEEPSLEEP_VC bit */ - RCC->RCC_DEEPSLEEP_VC &= ~RCC_DEEPSLEEP_VC_CLEAR; - /* Set DEEPSLEEP_VC bits according to RCC_KERNEL_VOL value */ - RCC->RCC_DEEPSLEEP_VC |= RCC_KERNEL_VOL; -} - -/** - * @} - */ - -/** - * @} - */ - -/** - * @} - */ - - - diff --git a/bsp/gd32103c-eval/Libraries/GD32F1xx_standard_peripheral/Source/gd32f10x_rcu.c b/bsp/gd32103c-eval/Libraries/GD32F1xx_standard_peripheral/Source/gd32f10x_rcu.c deleted file mode 100644 index 1757e170ef..0000000000 --- a/bsp/gd32103c-eval/Libraries/GD32F1xx_standard_peripheral/Source/gd32f10x_rcu.c +++ /dev/null @@ -1,1277 +0,0 @@ -/*! - \file gd32f10x_rcu.c - \brief RCU driver -*/ - -/* - Copyright (C) 2017 GigaDevice - - 2017-02-10, V1.0.1, firmware for GD32F30x - 2021-01-02, firmware for GD32F10x -*/ - -#include "gd32f10x_rcu.h" - -/* define clock source */ -#define SEL_IRC8M ((uint16_t)0U) -#define SEL_HXTAL ((uint16_t)1U) -#define SEL_PLL ((uint16_t)2U) - -/* define startup timeout count */ -#define OSC_STARTUP_TIMEOUT ((uint32_t)0xFFFFFU) -#define LXTAL_STARTUP_TIMEOUT ((uint32_t)0x3FFFFFFU) - -/*! - \brief deinitialize the RCU - \param[in] none - \param[out] none - \retval none -*/ -void rcu_deinit(void) -{ - /* enable IRC8M */ - RCU_CTL |= RCU_CTL_IRC8MEN; - rcu_osci_stab_wait(RCU_IRC8M); - - /* reset CFG0 register */ -#if (defined(GD32F10X_HD) || defined(GD32F10X_XD)) - RCU_CFG0 &= ~(RCU_CFG0_SCS | RCU_CFG0_AHBPSC | RCU_CFG0_APB1PSC | RCU_CFG0_APB2PSC | - RCU_CFG0_ADCPSC | RCU_CFG0_PLLSEL | RCU_CFG0_PREDV0 | RCU_CFG0_PLLMF | - RCU_CFG0_USBDPSC | RCU_CFG0_CKOUT0SEL | RCU_CFG0_PLLMF_4 | RCU_CFG0_ADCPSC_2 | RCU_CFG0_PLLMF_5 | RCU_CFG0_USBDPSC_2); -#elif defined(GD32F10X_CL) - RCU_CFG0 &= ~(RCU_CFG0_SCS | RCU_CFG0_AHBPSC | RCU_CFG0_APB1PSC | RCU_CFG0_APB2PSC | - RCU_CFG0_ADCPSC | RCU_CFG0_PLLSEL | RCU_CFG0_PREDV0_LSB | RCU_CFG0_PLLMF | - RCU_CFG0_USBFSPSC | RCU_CFG0_CKOUT0SEL | RCU_CFG0_ADCPSC_2 | RCU_CFG0_PLLMF_4 | RCU_CFG0_PLLMF_5 | RCU_CFG0_USBFSPSC_2); -#endif /* GD32F10X_HD and GD32F10X_XD */ - /* reset CTL register */ - RCU_CTL &= ~(RCU_CTL_HXTALEN | RCU_CTL_CKMEN | RCU_CTL_PLLEN); - RCU_CTL &= ~RCU_CTL_HXTALBPS; -#ifdef GD32F10X_CL - RCU_CTL &= ~(RCU_CTL_PLL1EN | RCU_CTL_PLL2EN); -#endif /* GD32F10X_CL */ - - /* reset INT and CFG1 register */ -#if (defined(GD32F10X_HD) || defined(GD32F10X_XD)) - RCU_INT = 0x009f0000U; - RCU_CFG1 &= ~(RCU_CFG1_ADCPSC_3 | RCU_CFG1_PLLPRESEL); -#elif defined(GD32F10X_CL) - RCU_INT = 0x00ff0000U; - RCU_CFG1 &= ~(RCU_CFG1_PREDV0 | RCU_CFG1_PREDV1 | RCU_CFG1_PLL1MF | RCU_CFG1_PLL2MF | - RCU_CFG1_PREDV0SEL | RCU_CFG1_I2S1SEL | RCU_CFG1_I2S2SEL | RCU_CFG1_ADCPSC_3 | - RCU_CFG1_PLLPRESEL | RCU_CFG1_PLL2MF_4); -#endif /* GD32F10X_HD and GD32F10X_XD */ -} - -/*! - \brief enable the peripherals clock - \param[in] periph: RCU peripherals, refer to rcu_periph_enum - only one parameter can be selected which is shown as below: - \arg RCU_GPIOx (x=A,B,C,D,E,F,G): GPIO ports clock - \arg RCU_AF : alternate function clock - \arg RCU_CRC: CRC clock - \arg RCU_DMAx (x=0,1): DMA clock - \arg RCU_ENET: ENET clock(CL series available) - \arg RCU_ENETTX: ENETTX clock(CL series available) - \arg RCU_ENETRX: ENETRX clock(CL series available) - \arg RCU_USBD: USBD clock(HD,XD series available) - \arg RCU_USBFS: USBFS clock(CL series available) - \arg RCU_EXMC: EXMC clock - \arg RCU_TIMERx (x=0,1,2,3,4,5,6,7,8,9,10,11,12,13,TIMER8..13 are not available for HD series): TIMER clock - \arg RCU_WWDGT: WWDGT clock - \arg RCU_SPIx (x=0,1,2): SPI clock - \arg RCU_USARTx (x=0,1,2): USART clock - \arg RCU_UARTx (x=3,4): UART clock - \arg RCU_I2Cx (x=0,1): I2C clock - \arg RCU_CANx (x=0,1,CAN1 is only available for CL series): CAN clock - \arg RCU_PMU: PMU clock - \arg RCU_DAC: DAC clock - \arg RCU_RTC: RTC clock - \arg RCU_ADCx (x=0,1,2,ADC2 is not available for CL series): ADC clock - \arg RCU_SDIO: SDIO clock(not available for CL series) - \arg RCU_CTC: CTC clock - \arg RCU_BKPI: BKP interface clock - \param[out] none - \retval none -*/ -void rcu_periph_clock_enable(rcu_periph_enum periph) -{ - RCU_REG_VAL(periph) |= BIT(RCU_BIT_POS(periph)); -} - -/*! - \brief disable the peripherals clock - \param[in] periph: RCU peripherals, refer to rcu_periph_enum - only one parameter can be selected which is shown as below: - \arg RCU_GPIOx (x=A,B,C,D,E,F,G): GPIO ports clock - \arg RCU_AF: alternate function clock - \arg RCU_CRC: CRC clock - \arg RCU_DMAx (x=0,1): DMA clock - \arg RCU_ENET: ENET clock(CL series available) - \arg RCU_ENETTX: ENETTX clock(CL series available) - \arg RCU_ENETRX: ENETRX clock(CL series available) - \arg RCU_USBD: USBD clock(HD,XD series available) - \arg RCU_USBFS: USBFS clock(CL series available) - \arg RCU_EXMC: EXMC clock - \arg RCU_TIMERx (x=0,1,2,3,4,5,6,7,8,9,10,11,12,13,TIMER8..13 are not available for HD series): TIMER clock - \arg RCU_WWDGT: WWDGT clock - \arg RCU_SPIx (x=0,1,2): SPI clock - \arg RCU_USARTx (x=0,1,2): USART clock - \arg RCU_UARTx (x=3,4): UART clock - \arg RCU_I2Cx (x=0,1): I2C clock - \arg RCU_CANx (x=0,1,CAN1 is only available for CL series): CAN clock - \arg RCU_PMU: PMU clock - \arg RCU_DAC: DAC clock - \arg RCU_RTC: RTC clock - \arg RCU_ADCx (x=0,1,2,ADC2 is not available for CL series): ADC clock - \arg RCU_SDIO: SDIO clock(not available for CL series) - \arg RCU_CTC: CTC clock - \arg RCU_BKPI: BKP interface clock - \param[out] none - \retval none -*/ -void rcu_periph_clock_disable(rcu_periph_enum periph) -{ - RCU_REG_VAL(periph) &= ~BIT(RCU_BIT_POS(periph)); -} - -/*! - \brief enable the peripherals clock when sleep mode - \param[in] periph: RCU peripherals, refer to rcu_periph_sleep_enum - only one parameter can be selected which is shown as below: - \arg RCU_FMC_SLP: FMC clock - \arg RCU_SRAM_SLP: SRAM clock - \param[out] none - \retval none -*/ -void rcu_periph_clock_sleep_enable(rcu_periph_sleep_enum periph) -{ - RCU_REG_VAL(periph) |= BIT(RCU_BIT_POS(periph)); -} - -/*! - \brief disable the peripherals clock when sleep mode - \param[in] periph: RCU peripherals, refer to rcu_periph_sleep_enum - only one parameter can be selected which is shown as below: - \arg RCU_FMC_SLP: FMC clock - \arg RCU_SRAM_SLP: SRAM clock - \param[out] none - \retval none -*/ -void rcu_periph_clock_sleep_disable(rcu_periph_sleep_enum periph) -{ - RCU_REG_VAL(periph) &= ~BIT(RCU_BIT_POS(periph)); -} - -/*! - \brief reset the peripherals - \param[in] periph_reset: RCU peripherals reset, refer to rcu_periph_reset_enum - only one parameter can be selected which is shown as below: - \arg RCU_GPIOxRST (x=A,B,C,D,E,F,G): reset GPIO ports - \arg RCU_AFRST : reset alternate function clock - \arg RCU_ENETRST: reset ENET(CL series available) - \arg RCU_USBDRST: reset USBD(HD,XD series available) - \arg RCU_USBFSRST: reset USBFS(CL series available) - \arg RCU_TIMERxRST (x=0,1,2,3,4,5,6,7,8,9,10,11,12,13,TIMER8..13 are not available for HD series): reset TIMER - \arg RCU_WWDGTRST: reset WWDGT - \arg RCU_SPIxRST (x=0,1,2): reset SPI - \arg RCU_USARTxRST (x=0,1,2): reset USART - \arg RCU_UARTxRST (x=3,4): reset UART - \arg RCU_I2CxRST (x=0,1): reset I2C - \arg RCU_CANxRST (x=0,1,CAN1 is only available for CL series): reset CAN - \arg RCU_PMURST: reset PMU - \arg RCU_DACRST: reset DAC - \arg RCU_ADCRST (x=0,1,2,ADC2 is not available for CL series): reset ADC - \arg RCU_CTCRST: reset CTC - \arg RCU_BKPIRST: reset BKPI - \param[out] none - \retval none -*/ -void rcu_periph_reset_enable(rcu_periph_reset_enum periph_reset) -{ - RCU_REG_VAL(periph_reset) |= BIT(RCU_BIT_POS(periph_reset)); -} - -/*! - \brief disable reset the peripheral - \param[in] periph_reset: RCU peripherals reset, refer to rcu_periph_reset_enum - only one parameter can be selected which is shown as below: - \arg RCU_GPIOxRST (x=A,B,C,D,E,F,G): reset GPIO ports - \arg RCU_AFRST : reset alternate function clock - \arg RCU_ENETRST: reset ENET(CL series available) - \arg RCU_USBDRST: reset USBD(HD,XD series available) - \arg RCU_USBFSRST: reset USBFS(CL series available) - \arg RCU_TIMERxRST (x=0,1,2,3,4,5,6,7,8,9,10,11,12,13,TIMER8..13 are not available for HD series): reset TIMER - \arg RCU_WWDGTRST: reset WWDGT - \arg RCU_SPIxRST (x=0,1,2): reset SPI - \arg RCU_USARTxRST (x=0,1,2): reset USART - \arg RCU_UARTxRST (x=3,4): reset UART - \arg RCU_I2CxRST (x=0,1): reset I2C - \arg RCU_CANxRST (x=0,1,CAN1 is only available for CL series): reset CAN - \arg RCU_PMURST: reset PMU - \arg RCU_DACRST: reset DAC - \arg RCU_ADCRST (x=0,1,2,ADC2 is not available for CL series): reset ADC - \arg RCU_CTCRST: reset CTC - \arg RCU_BKPIRST: reset BKPI - \param[out] none - \retval none -*/ -void rcu_periph_reset_disable(rcu_periph_reset_enum periph_reset) -{ - RCU_REG_VAL(periph_reset) &= ~BIT(RCU_BIT_POS(periph_reset)); -} - -/*! - \brief reset the BKP domain - \param[in] none - \param[out] none - \retval none -*/ -void rcu_bkp_reset_enable(void) -{ - RCU_BDCTL |= RCU_BDCTL_BKPRST; -} - -/*! - \brief disable the BKP domain reset - \param[in] none - \param[out] none - \retval none -*/ -void rcu_bkp_reset_disable(void) -{ - RCU_BDCTL &= ~RCU_BDCTL_BKPRST; -} - -/*! - \brief configure the system clock source - \param[in] ck_sys: system clock source select - only one parameter can be selected which is shown as below: - \arg RCU_CKSYSSRC_IRC8M: select CK_IRC8M as the CK_SYS source - \arg RCU_CKSYSSRC_HXTAL: select CK_HXTAL as the CK_SYS source - \arg RCU_CKSYSSRC_PLL: select CK_PLL as the CK_SYS source - \param[out] none - \retval none -*/ -void rcu_system_clock_source_config(uint32_t ck_sys) -{ - uint32_t reg; - - reg = RCU_CFG0; - /* reset the SCS bits and set according to ck_sys */ - reg &= ~RCU_CFG0_SCS; - RCU_CFG0 = (reg | ck_sys); -} - -/*! - \brief get the system clock source - \param[in] none - \param[out] none - \retval which clock is selected as CK_SYS source - \arg RCU_SCSS_IRC8M: CK_IRC8M is selected as the CK_SYS source - \arg RCU_SCSS_HXTAL: CK_HXTAL is selected as the CK_SYS source - \arg RCU_SCSS_PLL: CK_PLL is selected as the CK_SYS source -*/ -uint32_t rcu_system_clock_source_get(void) -{ - return (RCU_CFG0 & RCU_CFG0_SCSS); -} - -/*! - \brief configure the AHB clock prescaler selection - \param[in] ck_ahb: AHB clock prescaler selection - only one parameter can be selected which is shown as below: - \arg RCU_AHB_CKSYS_DIVx, x=1, 2, 4, 8, 16, 64, 128, 256, 512 - \param[out] none - \retval none -*/ -void rcu_ahb_clock_config(uint32_t ck_ahb) -{ - uint32_t reg; - - reg = RCU_CFG0; - - /* reset the AHBPSC bits and set according to ck_ahb */ - reg &= ~RCU_CFG0_AHBPSC; - RCU_CFG0 = (reg | ck_ahb); -} - -/*! - \brief configure the APB1 clock prescaler selection - \param[in] ck_apb1: APB1 clock prescaler selection - only one parameter can be selected which is shown as below: - \arg RCU_APB1_CKAHB_DIV1: select CK_AHB as CK_APB1 - \arg RCU_APB1_CKAHB_DIV2: select CK_AHB/2 as CK_APB1 - \arg RCU_APB1_CKAHB_DIV4: select CK_AHB/4 as CK_APB1 - \arg RCU_APB1_CKAHB_DIV8: select CK_AHB/8 as CK_APB1 - \arg RCU_APB1_CKAHB_DIV16: select CK_AHB/16 as CK_APB1 - \param[out] none - \retval none -*/ -void rcu_apb1_clock_config(uint32_t ck_apb1) -{ - uint32_t reg; - - reg = RCU_CFG0; - - /* reset the APB1PSC and set according to ck_apb1 */ - reg &= ~RCU_CFG0_APB1PSC; - RCU_CFG0 = (reg | ck_apb1); -} - -/*! - \brief configure the APB2 clock prescaler selection - \param[in] ck_apb2: APB2 clock prescaler selection - only one parameter can be selected which is shown as below: - \arg RCU_APB2_CKAHB_DIV1: select CK_AHB as CK_APB2 - \arg RCU_APB2_CKAHB_DIV2: select CK_AHB/2 as CK_APB2 - \arg RCU_APB2_CKAHB_DIV4: select CK_AHB/4 as CK_APB2 - \arg RCU_APB2_CKAHB_DIV8: select CK_AHB/8 as CK_APB2 - \arg RCU_APB2_CKAHB_DIV16: select CK_AHB/16 as CK_APB2 - \param[out] none - \retval none -*/ -void rcu_apb2_clock_config(uint32_t ck_apb2) -{ - uint32_t reg; - - reg = RCU_CFG0; - - /* reset the APB2PSC and set according to ck_apb2 */ - reg &= ~RCU_CFG0_APB2PSC; - RCU_CFG0 = (reg | ck_apb2); -} - -/*! - \brief configure the CK_OUT0 clock source - \param[in] ckout0_src: CK_OUT0 clock source selection - only one parameter can be selected which is shown as below: - \arg RCU_CKOUT0SRC_NONE: no clock selected - \arg RCU_CKOUT0SRC_CKSYS: system clock selected - \arg RCU_CKOUT0SRC_IRC8M: high speed 8M internal oscillator clock selected - \arg RCU_CKOUT0SRC_HXTAL: HXTAL selected - \arg RCU_CKOUT0SRC_CKPLL_DIV2: CK_PLL/2 selected - \arg RCU_CKOUT0SRC_CKPLL1: CK_PLL1 selected - \arg RCU_CKOUT0SRC_CKPLL2_DIV2: CK_PLL2/2 selected - \arg RCU_CKOUT0SRC_EXT1: EXT1 selected - \arg RCU_CKOUT0SRC_CKPLL2: PLL selected - \param[out] none - \retval none -*/ -void rcu_ckout0_config(uint32_t ckout0_src) -{ - uint32_t reg; - - reg = RCU_CFG0; - - /* reset the CKOUT0SRC, set according to ckout0_src */ - reg &= ~RCU_CFG0_CKOUT0SEL; - RCU_CFG0 = (reg | ckout0_src); -} - -/*! - \brief configure the main PLL clock - \param[in] pll_src: PLL clock source selection - \arg RCU_PLLSRC_IRC8M_DIV2: IRC8M/2 clock selected as source clock of PLL - \arg RCU_PLLSRC_HXTAL_IRC48M: HXTAL or IRC48M selected as source clock of PLL - \param[in] pll_mul: PLL clock multiplication factor - \arg RCU_PLL_MULx (XD series x = 2..63, CL series x = 2..14, 16..63, 6.5) - \param[out] none - \retval none -*/ -void rcu_pll_config(uint32_t pll_src, uint32_t pll_mul) -{ - uint32_t reg = 0U; - - reg = RCU_CFG0; - - /* PLL clock source and multiplication factor configuration */ - reg &= ~(RCU_CFG0_PLLSEL | RCU_CFG0_PLLMF | RCU_CFG0_PLLMF_4 | RCU_CFG0_PLLMF_5); - reg |= (pll_src | pll_mul); - - RCU_CFG0 = reg; -} - -/*! - \brief configure the PLL clock source preselection - \param[in] pll_presel: PLL clock source preselection - \arg RCU_PLLPRESRC_HXTAL: HXTAL selected as PLL source clock - \arg RCU_PLLPRESRC_IRC48M: CK_PLL selected as PREDV0 input source clock - \param[out] none - \retval none -*/ -void rcu_pllpresel_config(uint32_t pll_presel) -{ - uint32_t reg = 0U; - - reg = RCU_CFG1; - - /* PLL clock source preselection */ - reg &= ~RCU_CFG1_PLLPRESEL; - reg |= pll_presel; - - RCU_CFG1 = reg; -} - -#if (defined(GD32F10X_HD) || defined(GD32F10X_XD)) -/*! - \brief configure the PREDV0 division factor - \param[in] predv0_div: PREDV0 division factor - \arg RCU_PREDV0_DIVx, x = 1,2 - \param[out] none - \retval none -*/ -void rcu_predv0_config(uint32_t predv0_div) -{ - uint32_t reg = 0U; - - reg = RCU_CFG0; - /* reset PREDV0 bit */ - reg &= ~RCU_CFG0_PREDV0; - if (RCU_PREDV0_DIV2 == predv0_div) { - /* set the PREDV0 bit */ - reg |= RCU_CFG0_PREDV0; - } - - RCU_CFG0 = reg; -} -#elif defined(GD32F10X_CL) -/*! - \brief configure the PREDV0 division factor and clock source - \param[in] predv0_source: PREDV0 input clock source selection - \arg RCU_PREDV0SRC_HXTAL_IRC48M: HXTAL or IRC48M selected as PREDV0 input source clock - \arg RCU_PREDV0SRC_CKPLL1: CK_PLL1 selected as PREDV0 input source clock - \param[in] predv0_div: PREDV0 division factor - \arg RCU_PREDV0_DIVx, x = 1..16 - \param[out] none - \retval none -*/ -void rcu_predv0_config(uint32_t predv0_source, uint32_t predv0_div) -{ - uint32_t reg = 0U; - - reg = RCU_CFG1; - /* reset PREDV0SEL and PREDV0 bits */ - reg &= ~(RCU_CFG1_PREDV0SEL | RCU_CFG1_PREDV0); - /* set the PREDV0SEL and PREDV0 division factor */ - reg |= (predv0_source | predv0_div); - - RCU_CFG1 = reg; -} - -/*! - \brief configure the PREDV1 division factor - \param[in] predv1_div: PREDV1 division factor - \arg RCU_PREDV1_DIVx, x = 1..16 - \param[out] none - \retval none -*/ -void rcu_predv1_config(uint32_t predv1_div) -{ - uint32_t reg = 0U; - - reg = RCU_CFG1; - /* reset the PREDV1 bits */ - reg &= ~RCU_CFG1_PREDV1; - /* set the PREDV1 division factor */ - reg |= predv1_div; - - RCU_CFG1 = reg; -} - -/*! - \brief configure the PLL1 clock - \param[in] pll_mul: PLL clock multiplication factor - \arg RCU_PLL1_MULx (x = 8..16, 20) - \param[out] none - \retval none -*/ -void rcu_pll1_config(uint32_t pll_mul) -{ - RCU_CFG1 &= ~RCU_CFG1_PLL1MF; - RCU_CFG1 |= pll_mul; -} - -/*! - \brief configure the PLL2 clock - \param[in] pll_mul: PLL clock multiplication factor - \arg RCU_PLL2_MULx (x = 8..16, 18..32, 40) - \param[out] none - \retval none -*/ -void rcu_pll2_config(uint32_t pll_mul) -{ - RCU_CFG1 &= ~RCU_CFG1_PLL2MF; - RCU_CFG1 |= pll_mul; -} -#endif /* GD32F10X_HD and GD32F10X_XD */ - -/*! - \brief configure the ADC prescaler factor - \param[in] adc_psc: ADC prescaler factor - \arg RCU_CKADC_CKAPB2_DIV2: ADC prescaler select CK_APB2/2 - \arg RCU_CKADC_CKAPB2_DIV4: ADC prescaler select CK_APB2/4 - \arg RCU_CKADC_CKAPB2_DIV6: ADC prescaler select CK_APB2/6 - \arg RCU_CKADC_CKAPB2_DIV8: ADC prescaler select CK_APB2/8 - \arg RCU_CKADC_CKAPB2_DIV12: ADC prescaler select CK_APB2/12 - \arg RCU_CKADC_CKAPB2_DIV16: ADC prescaler select CK_APB2/16 - \arg RCU_CKADC_CKAHB_DIV5: ADC prescaler select CK_AHB/5 - \arg RCU_CKADC_CKAHB_DIV6: ADC prescaler select CK_AHB/6 - \arg RCU_CKADC_CKAHB_DIV10: ADC prescaler select CK_AHB/10 - \arg RCU_CKADC_CKAHB_DIV20: ADC prescaler select CK_AHB/20 - \param[out] none - \retval none -*/ -void rcu_adc_clock_config(uint32_t adc_psc) -{ - uint32_t reg0, reg1; - - /* reset the ADCPSC bits */ - reg0 = RCU_CFG0; - reg0 &= ~(RCU_CFG0_ADCPSC_2 | RCU_CFG0_ADCPSC); - reg1 = RCU_CFG1; - reg1 &= ~RCU_CFG1_ADCPSC_3; - - /* set the ADC prescaler factor */ - switch (adc_psc) { - case RCU_CKADC_CKAPB2_DIV2: - case RCU_CKADC_CKAPB2_DIV4: - case RCU_CKADC_CKAPB2_DIV6: - case RCU_CKADC_CKAPB2_DIV8: - reg0 |= (adc_psc << 14); - break; - - case RCU_CKADC_CKAPB2_DIV12: - case RCU_CKADC_CKAPB2_DIV16: - adc_psc &= ~BIT(2); - reg0 |= (adc_psc << 14 | RCU_CFG0_ADCPSC_2); - break; - - case RCU_CKADC_CKAHB_DIV5: - case RCU_CKADC_CKAHB_DIV6: - case RCU_CKADC_CKAHB_DIV10: - case RCU_CKADC_CKAHB_DIV20: - adc_psc &= ~BITS(2, 3); - reg0 |= (adc_psc << 14); - reg1 |= RCU_CFG1_ADCPSC_3; - break; - - default: - break; - } - - /* set the register */ - RCU_CFG0 = reg0; - RCU_CFG1 = reg1; -} - -/*! - \brief configure the USBD/USBFS prescaler factor - \param[in] adc_div: USB prescaler factor - \arg RCU_CKUSB_CKPLL_DIV1_5: USBD/USBFS prescaler select CK_PLL/1.5 - \arg RCU_CKUSB_CKPLL_DIV1: USBD/USBFS prescaler select CK_PLL/1 - \arg RCU_CKUSB_CKPLL_DIV2_5: USBD/USBFS prescaler select CK_PLL/2.5 - \arg RCU_CKUSB_CKPLL_DIV2: USBD/USBFS prescaler select CK_PLL/2 - \arg RCU_CKUSB_CKPLL_DIV3: USBD/USBFS prescaler select CK_PLL/3 - \arg RCU_CKUSB_CKPLL_DIV3_5: USBD/USBFS prescaler select CK_PLL/3.5 - \arg RCU_CKUSB_CKPLL_DIV4: USBD/USBFS prescaler select CK_PLL/4 - \param[out] none - \retval none -*/ -void rcu_usb_clock_config(uint32_t usb_psc) -{ - uint32_t reg; - - reg = RCU_CFG0; - - /* configure the USBD/USBFS prescaler factor */ -#if (defined(GD32F10X_HD) || defined(GD32F10X_XD)) - reg &= ~RCU_CFG0_USBDPSC; -#elif defined(GD32F10X_CL) - reg &= ~RCU_CFG0_USBFSPSC; -#endif /* GD32F10X_HD and GD32F10X_XD */ - - RCU_CFG0 = (reg | usb_psc); -} - -/*! - \brief configure the RTC clock source selection - \param[in] rtc_clock_source: RTC clock source selection - only one parameter can be selected which is shown as below: - \arg RCU_RTCSRC_NONE: no clock selected - \arg RCU_RTCSRC_LXTAL: CK_LXTAL selected as RTC source clock - \arg RCU_RTCSRC_IRC40K: CK_IRC40K selected as RTC source clock - \arg RCU_RTCSRC_HXTAL_DIV_128: CK_HXTAL/128 selected as RTC source clock - \param[out] none - \retval none -*/ -void rcu_rtc_clock_config(uint32_t rtc_clock_source) -{ - uint32_t reg; - - reg = RCU_BDCTL; - /* reset the RTCSRC bits and set according to rtc_clock_source */ - reg &= ~RCU_BDCTL_RTCSRC; - RCU_BDCTL = (reg | rtc_clock_source); -} - -#ifdef GD32F10X_CL -/*! - \brief configure the I2S1 clock source selection - \param[in] i2s_clock_source: I2S1 clock source selection - only one parameter can be selected which is shown as below: - \arg RCU_I2S1SRC_CKSYS: System clock selected as I2S1 source clock - \arg RCU_I2S1SRC_CKPLL2_MUL2: CK_PLL2x2 selected as I2S1 source clock - \param[out] none - \retval none -*/ -void rcu_i2s1_clock_config(uint32_t i2s_clock_source) -{ - uint32_t reg; - - reg = RCU_CFG1; - /* reset the I2S1SEL bit and set according to i2s_clock_source */ - reg &= ~RCU_CFG1_I2S1SEL; - RCU_CFG1 = (reg | i2s_clock_source); -} - -/*! - \brief configure the I2S2 clock source selection - \param[in] i2s_clock_source: I2S2 clock source selection - only one parameter can be selected which is shown as below: - \arg RCU_I2S2SRC_CKSYS: system clock selected as I2S2 source clock - \arg RCU_I2S2SRC_CKPLL2_MUL2: CK_PLL2x2 selected as I2S2 source clock - \param[out] none - \retval none -*/ -void rcu_i2s2_clock_config(uint32_t i2s_clock_source) -{ - uint32_t reg; - - reg = RCU_CFG1; - /* reset the I2S2SEL bit and set according to i2s_clock_source */ - reg &= ~RCU_CFG1_I2S2SEL; - RCU_CFG1 = (reg | i2s_clock_source); -} -#endif /* GD32F10X_CL */ - -/*! - \brief configure the CK48M clock source selection - \param[in] ck48m_clock_source: CK48M clock source selection - only one parameter can be selected which is shown as below: - \arg RCU_CK48MSRC_CKPLL: CK_PLL selected as CK48M source clock - \arg RCU_CK48MSRC_IRC48M: CK_IRC48M selected as CK48M source clock - \param[out] none - \retval none -*/ -void rcu_ck48m_clock_config(uint32_t ck48m_clock_source) -{ - uint32_t reg; - - reg = RCU_ADDCTL; - /* reset the CK48MSEL bit and set according to ck48m_clock_source */ - reg &= ~RCU_ADDCTL_CK48MSEL; - RCU_ADDCTL = (reg | ck48m_clock_source); -} - -/*! - \brief get the clock stabilization and periphral reset flags - \param[in] flag: the clock stabilization and periphral reset flags, refer to rcu_flag_enum - only one parameter can be selected which is shown as below: - \arg RCU_FLAG_IRC8MSTB: IRC8M stabilization flag - \arg RCU_FLAG_HXTALSTB: HXTAL stabilization flag - \arg RCU_FLAG_PLLSTB: PLL stabilization flag - \arg RCU_FLAG_PLL1STB: PLL1 stabilization flag(CL series only) - \arg RCU_FLAG_PLL2STB: PLL2 stabilization flag(CL series only) - \arg RCU_FLAG_LXTALSTB: LXTAL stabilization flag - \arg RCU_FLAG_IRC40KSTB: IRC40K stabilization flag - \arg RCU_FLAG_IRC48MSTB: IRC48M stabilization flag - \arg RCU_FLAG_EPRST: external PIN reset flag - \arg RCU_FLAG_PORRST: power reset flag - \arg RCU_FLAG_SWRST: software reset flag - \arg RCU_FLAG_FWDGTRST: free watchdog timer reset flag - \arg RCU_FLAG_WWDGTRST: window watchdog timer reset flag - \arg RCU_FLAG_LPRST: low-power reset flag - \param[out] none - \retval none -*/ -FlagStatus rcu_flag_get(rcu_flag_enum flag) -{ - /* get the rcu flag */ - if (RESET != (RCU_REG_VAL(flag) & BIT(RCU_BIT_POS(flag)))) { - return SET; - } else { - return RESET; - } -} - -/*! - \brief clear all the reset flag - \param[in] none - \param[out] none - \retval none -*/ -void rcu_all_reset_flag_clear(void) -{ - RCU_RSTSCK |= RCU_RSTSCK_RSTFC; -} - -/*! - \brief get the clock stabilization interrupt and ckm flags - \param[in] int_flag: interrupt and ckm flags, refer to rcu_int_flag_enum - only one parameter can be selected which is shown as below: - \arg RCU_INT_FLAG_IRC40KSTB: IRC40K stabilization interrupt flag - \arg RCU_INT_FLAG_LXTALSTB: LXTAL stabilization interrupt flag - \arg RCU_INT_FLAG_IRC8MSTB: IRC8M stabilization interrupt flag - \arg RCU_INT_FLAG_HXTALSTB: HXTAL stabilization interrupt flag - \arg RCU_INT_FLAG_PLLSTB: PLL stabilization interrupt flag - \arg RCU_INT_FLAG_PLL1STB: PLL1 stabilization interrupt flag(CL series only) - \arg RCU_INT_FLAG_PLL2STB: PLL2 stabilization interrupt flag(CL series only) - \arg RCU_INT_FLAG_CKM: HXTAL clock stuck interrupt flag - \arg RCU_INT_FLAG_IRC48MSTB: IRC48M stabilization interrupt flag - \param[out] none - \retval FlagStatus: SET or RESET -*/ -FlagStatus rcu_interrupt_flag_get(rcu_int_flag_enum int_flag) -{ - /* get the rcu interrupt flag */ - if (RESET != (RCU_REG_VAL(int_flag) & BIT(RCU_BIT_POS(int_flag)))) { - return SET; - } else { - return RESET; - } -} - -/*! - \brief clear the interrupt flags - \param[in] int_flag_clear: clock stabilization and stuck interrupt flags clear, refer to rcu_int_flag_clear_enum - only one parameter can be selected which is shown as below: - \arg RCU_INT_FLAG_IRC40KSTB_CLR: IRC40K stabilization interrupt flag clear - \arg RCU_INT_FLAG_LXTALSTB_CLR: LXTAL stabilization interrupt flag clear - \arg RCU_INT_FLAG_IRC8MSTB_CLR: IRC8M stabilization interrupt flag clear - \arg RCU_INT_FLAG_HXTALSTB_CLR: HXTAL stabilization interrupt flag clear - \arg RCU_INT_FLAG_PLLSTB_CLR: PLL stabilization interrupt flag clear - \arg RCU_INT_FLAG_PLL1STB_CLR: PLL1 stabilization interrupt flag clear(CL series only) - \arg RCU_INT_FLAG_PLL2STB_CLR: PLL2 stabilization interrupt flag clear(CL series only) - \arg RCU_INT_FLAG_CKM_CLR: clock stuck interrupt flag clear - \arg RCU_INT_FLAG_IRC48MSTB_CLR: IRC48M stabilization interrupt flag clear - \param[out] none - \retval none -*/ -void rcu_interrupt_flag_clear(rcu_int_flag_clear_enum int_flag_clear) -{ - RCU_REG_VAL(int_flag_clear) |= BIT(RCU_BIT_POS(int_flag_clear)); -} - -/*! - \brief enable the stabilization interrupt - \param[in] stab_int: clock stabilization interrupt, refer to rcu_int_enum - Only one parameter can be selected which is shown as below: - \arg RCU_INT_IRC40KSTB: IRC40K stabilization interrupt enable - \arg RCU_INT_LXTALSTB: LXTAL stabilization interrupt enable - \arg RCU_INT_IRC8MSTB: IRC8M stabilization interrupt enable - \arg RCU_INT_HXTALSTB: HXTAL stabilization interrupt enable - \arg RCU_INT_PLLSTB: PLL stabilization interrupt enable - \arg RCU_INT_PLL1STB: PLL1 stabilization interrupt enable(CL series only) - \arg RCU_INT_PLL2STB: PLL2 stabilization interrupt enable(CL series only) - \arg RCU_INT_IRC48MSTB: IRC48M stabilization interrupt enable - \param[out] none - \retval none -*/ -void rcu_interrupt_enable(rcu_int_enum stab_int) -{ - RCU_REG_VAL(stab_int) |= BIT(RCU_BIT_POS(stab_int)); -} - -/*! - \brief disable the stabilization interrupt - \param[in] stab_int: clock stabilization interrupt, refer to rcu_int_enum - only one parameter can be selected which is shown as below: - \arg RCU_INT_IRC40KSTB: IRC40K stabilization interrupt enable - \arg RCU_INT_LXTALSTB: LXTAL stabilization interrupt enable - \arg RCU_INT_IRC8MSTB: IRC8M stabilization interrupt enable - \arg RCU_INT_HXTALSTB: HXTAL stabilization interrupt enable - \arg RCU_INT_PLLSTB: PLL stabilization interrupt enable - \arg RCU_INT_PLL1STB: PLL1 stabilization interrupt enable(CL series only) - \arg RCU_INT_PLL2STB: PLL2 stabilization interrupt enable(CL series only) - \arg RCU_INT_IRC48MSTB: IRC48M stabilization interrupt enable - \param[out] none - \retval none -*/ -void rcu_interrupt_disable(rcu_int_enum stab_int) -{ - RCU_REG_VAL(stab_int) &= ~BIT(RCU_BIT_POS(stab_int)); -} - -/*! - \brief configure the LXTAL drive capability - \param[in] lxtal_dricap: drive capability of LXTAL - only one parameter can be selected which is shown as below: - \arg RCU_LXTAL_LOWDRI: lower driving capability - \arg RCU_LXTAL_MED_LOWDRI: medium low driving capability - \arg RCU_LXTAL_MED_HIGHDRI: medium high driving capability - \arg RCU_LXTAL_HIGHDRI: higher driving capability - \param[out] none - \retval none -*/ -void rcu_lxtal_drive_capability_config(uint32_t lxtal_dricap) -{ - uint32_t reg; - - reg = RCU_BDCTL; - - /* reset the LXTALDRI bits and set according to lxtal_dricap */ - reg &= ~RCU_BDCTL_LXTALDRI; - RCU_BDCTL = (reg | lxtal_dricap); -} - -/*! - \brief wait for oscillator stabilization flags is SET or oscillator startup is timeout - \param[in] osci: oscillator types, refer to rcu_osci_type_enum - only one parameter can be selected which is shown as below: - \arg RCU_HXTAL: high speed crystal oscillator(HXTAL) - \arg RCU_LXTAL: low speed crystal oscillator(LXTAL) - \arg RCU_IRC8M: internal 8M RC oscillators(IRC8M) - \arg RCU_IRC48M: internal 48M RC oscillators(IRC48M) - \arg RCU_IRC40K: internal 40K RC oscillator(IRC40K) - \arg RCU_PLL_CK: phase locked loop(PLL) - \arg RCU_PLL1_CK: phase locked loop 1(CL series only) - \arg RCU_PLL2_CK: phase locked loop 2(CL series only) - \param[out] none - \retval ErrStatus: SUCCESS or ERROR -*/ -ErrStatus rcu_osci_stab_wait(rcu_osci_type_enum osci) -{ - uint32_t stb_cnt = 0U; - ErrStatus reval = ERROR; - FlagStatus osci_stat = RESET; - - switch (osci) { - /* wait HXTAL stable */ - case RCU_HXTAL: - while ((RESET == osci_stat) && (HXTAL_STARTUP_TIMEOUT != stb_cnt)) { - osci_stat = rcu_flag_get(RCU_FLAG_HXTALSTB); - stb_cnt++; - } - - /* check whether flag is set or not */ - if (RESET != rcu_flag_get(RCU_FLAG_HXTALSTB)) { - reval = SUCCESS; - } - break; - - /* wait LXTAL stable */ - case RCU_LXTAL: - while ((RESET == osci_stat) && (LXTAL_STARTUP_TIMEOUT != stb_cnt)) { - osci_stat = rcu_flag_get(RCU_FLAG_LXTALSTB); - stb_cnt++; - } - - /* check whether flag is set or not */ - if (RESET != rcu_flag_get(RCU_FLAG_LXTALSTB)) { - reval = SUCCESS; - } - break; - - /* wait IRC8M stable */ - case RCU_IRC8M: - while ((RESET == osci_stat) && (IRC8M_STARTUP_TIMEOUT != stb_cnt)) { - osci_stat = rcu_flag_get(RCU_FLAG_IRC8MSTB); - stb_cnt++; - } - - /* check whether flag is set or not */ - if (RESET != rcu_flag_get(RCU_FLAG_IRC8MSTB)) { - reval = SUCCESS; - } - break; - - /* wait IRC48M stable */ - case RCU_IRC48M: - while ((RESET == osci_stat) && (OSC_STARTUP_TIMEOUT != stb_cnt)) { - osci_stat = rcu_flag_get(RCU_FLAG_IRC48MSTB); - stb_cnt++; - } - - /* check whether flag is set or not */ - if (RESET != rcu_flag_get(RCU_FLAG_IRC48MSTB)) { - reval = SUCCESS; - } - break; - - /* wait IRC40K stable */ - case RCU_IRC40K: - while ((RESET == osci_stat) && (OSC_STARTUP_TIMEOUT != stb_cnt)) { - osci_stat = rcu_flag_get(RCU_FLAG_IRC40KSTB); - stb_cnt++; - } - - /* check whether flag is set or not */ - if (RESET != rcu_flag_get(RCU_FLAG_IRC40KSTB)) { - reval = SUCCESS; - } - break; - - /* wait PLL stable */ - case RCU_PLL_CK: - while ((RESET == osci_stat) && (OSC_STARTUP_TIMEOUT != stb_cnt)) { - osci_stat = rcu_flag_get(RCU_FLAG_PLLSTB); - stb_cnt++; - } - - /* check whether flag is set or not */ - if (RESET != rcu_flag_get(RCU_FLAG_PLLSTB)) { - reval = SUCCESS; - } - break; - -#ifdef GD32F10X_CL - /* wait PLL1 stable */ - case RCU_PLL1_CK: - while ((RESET == osci_stat) && (OSC_STARTUP_TIMEOUT != stb_cnt)) { - osci_stat = rcu_flag_get(RCU_FLAG_PLL1STB); - stb_cnt++; - } - - /* check whether flag is set or not */ - if (RESET != rcu_flag_get(RCU_FLAG_PLL1STB)) { - reval = SUCCESS; - } - break; - /* wait PLL2 stable */ - case RCU_PLL2_CK: - while ((RESET == osci_stat) && (OSC_STARTUP_TIMEOUT != stb_cnt)) { - osci_stat = rcu_flag_get(RCU_FLAG_PLL2STB); - stb_cnt++; - } - - /* check whether flag is set or not */ - if (RESET != rcu_flag_get(RCU_FLAG_PLL2STB)) { - reval = SUCCESS; - } - break; -#endif /* GD32F10X_CL */ - - default: - break; - } - - /* return value */ - return reval; -} - -/*! - \brief turn on the oscillator - \param[in] osci: oscillator types, refer to rcu_osci_type_enum - only one parameter can be selected which is shown as below: - \arg RCU_HXTAL: high speed crystal oscillator(HXTAL) - \arg RCU_LXTAL: low speed crystal oscillator(LXTAL) - \arg RCU_IRC8M: internal 8M RC oscillators(IRC8M) - \arg RCU_IRC48M: internal 48M RC oscillators(IRC48M) - \arg RCU_IRC40K: internal 40K RC oscillator(IRC40K) - \arg RCU_PLL_CK: phase locked loop(PLL) - \arg RCU_PLL1_CK: phase locked loop 1(CL series only) - \arg RCU_PLL2_CK: phase locked loop 2(CL series only) - \param[out] none - \retval none -*/ -void rcu_osci_on(rcu_osci_type_enum osci) -{ - RCU_REG_VAL(osci) |= BIT(RCU_BIT_POS(osci)); -} - -/*! - \brief turn off the oscillator - \param[in] osci: oscillator types, refer to rcu_osci_type_enum - only one parameter can be selected which is shown as below: - \arg RCU_HXTAL: high speed crystal oscillator(HXTAL) - \arg RCU_LXTAL: low speed crystal oscillator(LXTAL) - \arg RCU_IRC8M: internal 8M RC oscillators(IRC8M) - \arg RCU_IRC48M: internal 48M RC oscillators(IRC48M) - \arg RCU_IRC40K: internal 40K RC oscillator(IRC40K) - \arg RCU_PLL_CK: phase locked loop(PLL) - \arg RCU_PLL1_CK: phase locked loop 1(CL series only) - \arg RCU_PLL2_CK: phase locked loop 2(CL series only) - \param[out] none - \retval none -*/ -void rcu_osci_off(rcu_osci_type_enum osci) -{ - RCU_REG_VAL(osci) &= ~BIT(RCU_BIT_POS(osci)); -} - -/*! - \brief enable the oscillator bypass mode, HXTALEN or LXTALEN must be reset before it - \param[in] osci: oscillator types, refer to rcu_osci_type_enum - only one parameter can be selected which is shown as below: - \arg RCU_HXTAL: high speed crystal oscillator(HXTAL) - \arg RCU_LXTAL: low speed crystal oscillator(LXTAL) - \param[out] none - \retval none -*/ -void rcu_osci_bypass_mode_enable(rcu_osci_type_enum osci) -{ - uint32_t reg; - - switch (osci) { - /* enable HXTAL to bypass mode */ - case RCU_HXTAL: - reg = RCU_CTL; - RCU_CTL &= ~RCU_CTL_HXTALEN; - RCU_CTL = (reg | RCU_CTL_HXTALBPS); - break; - /* enable LXTAL to bypass mode */ - case RCU_LXTAL: - reg = RCU_BDCTL; - RCU_BDCTL &= ~RCU_BDCTL_LXTALEN; - RCU_BDCTL = (reg | RCU_BDCTL_LXTALBPS); - break; - case RCU_IRC8M: - case RCU_IRC48M: - case RCU_IRC40K: - case RCU_PLL_CK: -#ifdef GD32F10X_CL - case RCU_PLL1_CK: - case RCU_PLL2_CK: -#endif /* GD32F10X_CL */ - break; - default: - break; - } -} - -/*! - \brief disable the oscillator bypass mode, HXTALEN or LXTALEN must be reset before it - \param[in] osci: oscillator types, refer to rcu_osci_type_enum - only one parameter can be selected which is shown as below: - \arg RCU_HXTAL: high speed crystal oscillator(HXTAL) - \arg RCU_LXTAL: low speed crystal oscillator(LXTAL) - \param[out] none - \retval none -*/ -void rcu_osci_bypass_mode_disable(rcu_osci_type_enum osci) -{ - uint32_t reg; - - switch (osci) { - /* disable HXTAL to bypass mode */ - case RCU_HXTAL: - reg = RCU_CTL; - RCU_CTL &= ~RCU_CTL_HXTALEN; - RCU_CTL = (reg & ~RCU_CTL_HXTALBPS); - break; - /* disable LXTAL to bypass mode */ - case RCU_LXTAL: - reg = RCU_BDCTL; - RCU_BDCTL &= ~RCU_BDCTL_LXTALEN; - RCU_BDCTL = (reg & ~RCU_BDCTL_LXTALBPS); - break; - case RCU_IRC8M: - case RCU_IRC48M: - case RCU_IRC40K: - case RCU_PLL_CK: -#ifdef GD32F10X_CL - case RCU_PLL1_CK: - case RCU_PLL2_CK: -#endif /* GD32F10X_CL */ - break; - default: - break; - } -} - -/*! - \brief enable the HXTAL clock monitor - \param[in] none - \param[out] none - \retval none -*/ - -void rcu_hxtal_clock_monitor_enable(void) -{ - RCU_CTL |= RCU_CTL_CKMEN; -} - -/*! - \brief disable the HXTAL clock monitor - \param[in] none - \param[out] none - \retval none -*/ -void rcu_hxtal_clock_monitor_disable(void) -{ - RCU_CTL &= ~RCU_CTL_CKMEN; -} - -/*! - \brief set the IRC8M adjust value - \param[in] irc8m_adjval: IRC8M adjust value, must be between 0 and 0x1F - \param[out] none - \retval none -*/ -void rcu_irc8m_adjust_value_set(uint32_t irc8m_adjval) -{ - uint32_t reg; - - reg = RCU_CTL; - /* reset the IRC8MADJ bits and set according to irc8m_adjval */ - reg &= ~RCU_CTL_IRC8MADJ; - RCU_CTL = (reg | ((irc8m_adjval & 0x1FU) << 3)); -} - -/*! - \brief deep-sleep mode voltage select - \param[in] dsvol: deep sleep mode voltage - only one parameter can be selected which is shown as below: - \arg RCU_DEEPSLEEP_V_1_0: the core voltage is 1.0V - \arg RCU_DEEPSLEEP_V_0_9: the core voltage is 0.9V - \arg RCU_DEEPSLEEP_V_0_8: the core voltage is 0.8V - \arg RCU_DEEPSLEEP_V_0_7: the core voltage is 0.7V - \param[out] none - \retval none -*/ -void rcu_deepsleep_voltage_set(uint32_t dsvol) -{ - dsvol &= RCU_DSV_DSLPVS; - RCU_DSV = dsvol; -} - -/*! - \brief get the system clock, bus and peripheral clock frequency - \param[in] clock: the clock frequency which to get - only one parameter can be selected which is shown as below: - \arg CK_SYS: system clock frequency - \arg CK_AHB: AHB clock frequency - \arg CK_APB1: APB1 clock frequency - \arg CK_APB2: APB2 clock frequency - \param[out] none - \retval clock frequency of system, AHB, APB1, APB2 -*/ -uint32_t rcu_clock_freq_get(rcu_clock_freq_enum clock) -{ - uint32_t sws, ck_freq = 0U; - uint32_t cksys_freq, ahb_freq, apb1_freq, apb2_freq; - uint32_t pllsel, pllpresel, predv0sel, pllmf, ck_src, idx, clk_exp; -#ifdef GD32F10X_CL - uint32_t predv0, predv1, pll1mf; -#endif /* GD32F10X_CL */ - - /* exponent of AHB, APB1 and APB2 clock divider */ - uint8_t ahb_exp[16] = {0, 0, 0, 0, 0, 0, 0, 0, 1, 2, 3, 4, 6, 7, 8, 9}; - uint8_t apb1_exp[8] = {0, 0, 0, 0, 1, 2, 3, 4}; - uint8_t apb2_exp[8] = {0, 0, 0, 0, 1, 2, 3, 4}; - - sws = GET_BITS(RCU_CFG0, 2, 3); - switch (sws) { - /* IRC8M is selected as CK_SYS */ - case SEL_IRC8M: - cksys_freq = IRC8M_VALUE; - break; - /* HXTAL is selected as CK_SYS */ - case SEL_HXTAL: - cksys_freq = HXTAL_VALUE; - break; - /* PLL is selected as CK_SYS */ - case SEL_PLL: - /* PLL clock source selection, HXTAL, IRC48M or IRC8M/2 */ - pllsel = (RCU_CFG0 & RCU_CFG0_PLLSEL); - - if (RCU_PLLSRC_HXTAL_IRC48M == pllsel) { - /* PLL clock source is HXTAL or IRC48M */ - pllpresel = (RCU_CFG1 & RCU_CFG1_PLLPRESEL); - - if (RCU_PLLPRESRC_HXTAL == pllpresel) { - /* PLL clock source is HXTAL */ - ck_src = HXTAL_VALUE; - } else { - /* PLL clock source is IRC48 */ - ck_src = IRC48M_VALUE; - } - -#if (defined(GD32F10X_HD) || defined(GD32F10X_XD)) - predv0sel = (RCU_CFG0 & RCU_CFG0_PREDV0); - /* PREDV0 input source clock divided by 2 */ - if (RCU_CFG0_PREDV0 == predv0sel) { - ck_src = HXTAL_VALUE / 2U; - } -#elif defined(GD32F10X_CL) - predv0sel = (RCU_CFG1 & RCU_CFG1_PREDV0SEL); - /* source clock use PLL1 */ - if (RCU_PREDV0SRC_CKPLL1 == predv0sel) { - predv1 = ((RCU_CFG1 & RCU_CFG1_PREDV1) >> 4) + 1U; - pll1mf = (uint32_t)((RCU_CFG1 & RCU_CFG1_PLL1MF) >> 8) + 2U; - if (17U == pll1mf) { - pll1mf = 20U; - } - ck_src = (ck_src / predv1) * pll1mf; - } - predv0 = (RCU_CFG1 & RCU_CFG1_PREDV0) + 1U; - ck_src /= predv0; -#endif /* GD32F10X_HD and GD32F10X_XD */ - } else { - /* PLL clock source is IRC8M/2 */ - ck_src = IRC8M_VALUE / 2U; - } - - /* PLL multiplication factor */ - pllmf = GET_BITS(RCU_CFG0, 18, 21); - if ((RCU_CFG0 & RCU_CFG0_PLLMF_4)) { - pllmf |= 0x10U; - } - if ((RCU_CFG0 & RCU_CFG0_PLLMF_5)) { - pllmf |= 0x20U; - } - if (pllmf < 15U) { - pllmf += 2U; - } else if ((pllmf >= 15U) && (pllmf <= 62U)) { - pllmf += 1U; - } else { - pllmf = 63U; - } - cksys_freq = ck_src * pllmf; -#ifdef GD32F10X_CL - if (15U == pllmf) { - cksys_freq = ck_src * 6U + ck_src / 2U; - } -#endif /* GD32F10X_CL */ - - break; - /* IRC8M is selected as CK_SYS */ - default: - cksys_freq = IRC8M_VALUE; - break; - } - - /* calculate AHB clock frequency */ - idx = GET_BITS(RCU_CFG0, 4, 7); - clk_exp = ahb_exp[idx]; - ahb_freq = cksys_freq >> clk_exp; - - /* calculate APB1 clock frequency */ - idx = GET_BITS(RCU_CFG0, 8, 10); - clk_exp = apb1_exp[idx]; - apb1_freq = ahb_freq >> clk_exp; - - /* calculate APB2 clock frequency */ - idx = GET_BITS(RCU_CFG0, 11, 13); - clk_exp = apb2_exp[idx]; - apb2_freq = ahb_freq >> clk_exp; - - /* return the clocks frequency */ - switch (clock) { - case CK_SYS: - ck_freq = cksys_freq; - break; - case CK_AHB: - ck_freq = ahb_freq; - break; - case CK_APB1: - ck_freq = apb1_freq; - break; - case CK_APB2: - ck_freq = apb2_freq; - break; - default: - break; - } - return ck_freq; -} diff --git a/bsp/gd32103c-eval/Libraries/GD32F1xx_standard_peripheral/Source/gd32f10x_rtc.c b/bsp/gd32103c-eval/Libraries/GD32F1xx_standard_peripheral/Source/gd32f10x_rtc.c deleted file mode 100644 index 5080fc07f7..0000000000 --- a/bsp/gd32103c-eval/Libraries/GD32F1xx_standard_peripheral/Source/gd32f10x_rtc.c +++ /dev/null @@ -1,263 +0,0 @@ -/** - ****************************************************************************** - * @brief RTC functions of the firmware library. - ****************************************************************************** - */ - -/* Includes ------------------------------------------------------------------*/ -#include "gd32f10x_rtc.h" - -/** @addtogroup GD32F10x_Firmware - * @{ - */ - -/** @defgroup RTC - * @brief RTC driver modules - * @{ - */ - -/** @defgroup RTC_Private_Defines - * @{ - */ - -/* RTC LSB Mask */ -#define RTC_LSB_MASK ((uint32_t)0x0000FFFF) - -/* RTC Prescaler MSB Mask */ -#define PRL1_MSB_MASK ((uint32_t)0x000F0000) - -/** - * @} - */ - -/** @defgroup RTC_Private_Functions - * @{ - */ - -/** - * @brief Enable or disable the specified RTC interrupts. - * @param RTC_INT: specify the RTC interrupt sources - * This parameter can be any combination of the following value: - * @arg RTC_INT_OVI: Overflow event interrupt - * @arg RTC_INT_AI: Alarm event interrupt - * @arg RTC_INT_SI: Tamper event interrupt - * @param NewValue: RTC interrupt state to configure - * This parameter can be: ENABLE or DISABLE. - * @retval None - */ -void RTC_INT_Enable(uint16_t RTC_INT, TypeState NewValue) -{ - if (NewValue == ENABLE) { - /* Enable the interrupts in RTC_CTLR register */ - RTC->CTLR1 |= RTC_INT; - } else { - /* Disable the interrupts in RTC_CTLR register */ - RTC->CTLR1 &= ~((uint16_t)RTC_INT); - } -} - -/** - * @brief Enter the RTC configuration mode. - * @param None - * @retval None - */ -void RTC_EnterConfigMode(void) -{ - /* Enter in the Configuration Mode by set the CMF flag */ - RTC->CTLR2 |= RTC_CTLR2_CMF; -} - -/** - * @brief Exit from the RTC configuration mode. - * @param None - * @retval None - */ -void RTC_ExitConfigMode(void) -{ - /* Exit from the Configuration Mode by reset the CMF flag */ - RTC->CTLR2 &= ~((uint16_t)RTC_CTLR2_CMF); -} - -/** - * @brief Get the RTC counter value. - * @param None - * @retval The value of RTC counter. - */ -uint32_t RTC_GetCounter(void) -{ - uint16_t temp = 0; - temp = RTC->CNT2; - return (((uint32_t)RTC->CNT1 << 16) | temp) ; -} - -/** - * @brief Set the RTC counter value. - * @param CounterValue: New value of the RTC counter. - * @retval None - */ -void RTC_SetCounter(uint32_t CounterValue) -{ - RTC_EnterConfigMode(); - /* Set the RTC counter MSB word */ - RTC->CNT1 = CounterValue >> 16; - /* Set the RTC counter LSB word */ - RTC->CNT2 = (CounterValue & RTC_LSB_MASK); - RTC_ExitConfigMode(); -} - -/** - * @brief Set the RTC prescaler value. - * @param PrescalerValue: New value of the RTC prescaler. - * @retval None - */ -void RTC_SetPrescaler(uint32_t PrescalerValue) -{ - RTC_EnterConfigMode(); - /* Set the RTC prescaler MSB word */ - RTC->PLR1 = (PrescalerValue & PRL1_MSB_MASK) >> 16; - /* Set the RTC prescaler LSB word */ - RTC->PLR2 = (PrescalerValue & RTC_LSB_MASK); - RTC_ExitConfigMode(); -} - -/** - * @brief Set the RTC alarm value. - * @param AlarmValue: New value of the RTC alarm. - * @retval None - */ -void RTC_SetAlarm(uint32_t AlarmValue) -{ - RTC_EnterConfigMode(); - /* Set the alarm MSB word */ - RTC->ALRMR1 = AlarmValue >> 16; - /* Set the alarm LSB word */ - RTC->ALRMR2 = (AlarmValue & RTC_LSB_MASK); - RTC_ExitConfigMode(); -} - -/** - * @brief Get the RTC divider value. - * @param None - * @retval The value of RTC Divider. - */ -uint32_t RTC_GetDivider(void) -{ - uint32_t temp = 0x00; - temp = ((uint32_t)RTC->PREDIV1 & (uint32_t)0x000F) << 16; - temp |= RTC->PREDIV2; - return temp; -} - -/** - * @brief Wait until last write operation on RTC registers has finished. - * @note This function must be called before any write to RTC registers. - * @param None - * @retval None - */ -void RTC_WaitLWOFF(void) -{ - /* Loop until RTOFF flag is set */ - while ((RTC->CTLR2 & RTC_FLAG_LWOFF) == (uint16_t)RESET) { - } -} - -/** - * @brief Wait until the RTC registers (RTC_CNT, RTC_ALR and RTC_PRL) - * are synchronized with RTC APB clock. - * @note This function must be called before any read operation after an APB reset - * or an APB clock stop. - * @param None - * @retval None - */ -void RTC_WaitRSF(void) -{ - /* Clear RSF flag */ - RTC->CTLR2 &= ~((uint16_t)RTC_FLAG_RSF); - /* Loop until RSF flag is set */ - while ((RTC->CTLR2 & RTC_FLAG_RSF) == (uint16_t)RESET) { - } -} - -/** - * @brief Check whether the specified RTC flag is set or not. - * @param RTC_FLAG: specifie the flag to check. - * This parameter can be one the following values: - * @arg RTC_FLAG_LWOFF: RTC Operation Off flag - * @arg RTC_FLAG_RSF: Registers Synchronized flag - * @arg RTC_FLAG_OVF: Overflow flag - * @arg RTC_FLAG_AF: Alarm flag - * @arg RTC_FLAG_SF: Second flag - * @retval The new bitstate of RTC_FLAG (SET or RESET). - */ -TypeState RTC_GetBitState(uint16_t RTC_FLAG) -{ - if ((RTC->CTLR2 & RTC_FLAG) != (uint16_t)RESET) { - return SET; - } else { - return RESET; - } -} - -/** - * @brief Clear the RTC's pending flags. - * @param RTC_FLAG: specifie the flag to clear. - * This parameter can be any combination of the following values: - * @arg RTC_FLAG_RSF: Registers Synchronized flag. This flag is cleared only after - * an APB reset or an APB Clock stop. - * @arg RTC_FLAG_OVF: Overflow flag - * @arg RTC_FLAG_AF: Alarm flag - * @arg RTC_FLAG_SF: Second flag - * @retval None - */ -void RTC_ClearBitState(uint16_t RTC_flag) -{ - /* Clear the corresponding RTC flag */ - RTC->CTLR2 &= ~((uint16_t)RTC_flag); -} - -/** - * @brief Check whether the specified RTC interrupt has occurred or not. - * @param RTC_INT: specifie the RTC interrupts sources to check. - * This parameter can be one of the following values: - * @arg RTC_INT_OVI: Overflow event interrupt - * @arg RTC_INT_AI: Alarm event interrupt - * @arg RTC_INT_SI: Tamper event interrupt - * @retval The new state of the RTC_IT (SET or RESET). - */ -TypeState RTC_GetIntBitState(uint16_t RTC_INT) -{ - - if (((RTC->CTLR1 & RTC_INT) != (uint16_t)RESET) && ((RTC->CTLR2 & RTC_INT) != (uint16_t)RESET)) { - return SET; - } else { - return RESET; - } -} - -/** - * @brief Clear the RTC's interrupt bit. - * @param RTC_INT: specifie the interrupt bit to clear. - * This parameter can be any combination of the following values: - * @arg RTC_INT_OVI: Overflow event interrupt - * @arg RTC_INT_AI: Alarm event interrupt - * @arg RTC_INT_SI: Tamper event interrupt - * @retval None - */ -void RTC_ClearIntBitState(uint16_t RTC_INT) -{ - /* Clear the RTC's interrupt bitstate */ - RTC->CTLR2 &= ~((uint16_t)RTC_INT); -} - -/** - * @} - */ - -/** - * @} - */ - -/** - * @} - */ - diff --git a/bsp/gd32103c-eval/Libraries/GD32F1xx_standard_peripheral/Source/gd32f10x_sdio.c b/bsp/gd32103c-eval/Libraries/GD32F1xx_standard_peripheral/Source/gd32f10x_sdio.c deleted file mode 100644 index 110fe8f410..0000000000 --- a/bsp/gd32103c-eval/Libraries/GD32F1xx_standard_peripheral/Source/gd32f10x_sdio.c +++ /dev/null @@ -1,636 +0,0 @@ -/** - ****************************************************************************** - * @brief SDIO functions of the firmware library. - ****************************************************************************** - */ -#ifdef GD32F10X_HD -/* Includes ------------------------------------------------------------------*/ -#include "gd32f10x_sdio.h" -#include "gd32f10x_rcc.h" - -/** @addtogroup GD32F10x_Firmware - * @{ - */ - -/** @defgroup SDIO - * @brief SDIO driver modules - * @{ - */ - -/** @defgroup SDIO_Private_Defines - * @{ - */ - -/* SDIO registers bit mask */ -/* CLKCTLR register mask */ -#define CLKCTLR_CLEAR_MASK ((uint32_t)0xFFFF8100) -/* POWER_PWRSTATE mask */ -#define POWER_PWRSTATE_MASK ((uint32_t)0xFFFFFFFC) -/* DTCTLR register mask */ -#define DTCTLR_CLEAR_MASK ((uint32_t)0xFFFFFF08) -/* CMD register mask */ -#define CMD_CLEAR_MASK ((uint32_t)0xFFFFF800) - -/* SDIO RESP Registers Address */ -#define SDIO_RESP_ADDR ((uint32_t)(SDIO_BASE + 0x14)) - -/** - * @} - */ - -/** @defgroup SDIO_Private_Functions - * @{ - */ - -/** - * @brief Deinitialize the SDIO . - * @param None - * @retval None - */ -void SDIO_DeInit(void) -{ - SDIO->POWER = 0x00000000; - SDIO->CLKCTLR = 0x00000000; - SDIO->PARA = 0x00000000; - SDIO->CMD = 0x00000000; - SDIO->DTTR = 0x00000000; - SDIO->DTLEN = 0x00000000; - SDIO->DTCTLR = 0x00000000; - SDIO->ICR = 0x00C007FF; - SDIO->IER = 0x00000000; -} - -/** - * @brief Initialize the SDIO . - * @param SDIO_InitParaStruct : pointer to a SDIO_InitPara structure . - * @retval None - */ -void SDIO_Init(SDIO_InitPara *SDIO_InitParaStruct) -{ - uint32_t temp = 0; - - /* SDIO CLKCTLR Configuration */ - /* Get the SDIO CLKCTLR value */ - temp = SDIO->CLKCTLR; - - /* Clear CLKCTLR register */ - temp &= CLKCTLR_CLEAR_MASK; - - /* Configure the SDIO_ClockDiv value */ - /* Configure the SDIO_ClockPWRSave value */ - /* Configure the SDIO_ClockBypassState value */ - /* Configure the SDIO_BusMode value */ - /* Configure the SDIO_ClockEdge value */ - /* Configure the SDIO_HWFlowCtrlState value */ - temp |= (SDIO_InitParaStruct->SDIO_ClockDiv | SDIO_InitParaStruct->SDIO_ClockPWRSave | - SDIO_InitParaStruct->SDIO_ClockBypassState | SDIO_InitParaStruct->SDIO_BusMode | - SDIO_InitParaStruct->SDIO_ClockEdge | SDIO_InitParaStruct->SDIO_HWFlowCtrlState); - - /* Update the SDIO CLKCTLR */ - SDIO->CLKCTLR = temp; -} - -/** - * @brief Fill each SDIO_InitParaStruct Struct member with a default value. - * @param SDIO_InitParaStruct: pointer to an SDIO_InitPara structure. - * @retval None - */ -void SDIO_ParaInit(SDIO_InitPara *SDIO_InitParaStruct) -{ - /* Fill the default value */ - SDIO_InitParaStruct->SDIO_ClockDiv = 0x00; - SDIO_InitParaStruct->SDIO_ClockEdge = SDIO_CLOCKEDGE_RISING; - SDIO_InitParaStruct->SDIO_ClockBypassState = SDIO_CLOCKBYPASSSTATE_DISABLE; - SDIO_InitParaStruct->SDIO_ClockPWRSave = SDIO_CLOCKPWRSAVE_DISABLE; - SDIO_InitParaStruct->SDIO_BusMode = SDIO_BUSMODE_1B; - SDIO_InitParaStruct->SDIO_HWFlowCtrlState = SDIO_HWFLOWCTRLSTATE_DISABLE; -} - -/** - * @brief ENABLE or DISABLE the SDIO Clock. - * @param NewValue: ENABLE or DISABLE. - * @retval None - */ -void SDIO_Clock_Enable(TypeState NewValue) -{ - if (NewValue != DISABLE) { - SDIO->CLKCTLR |= SDIO_CLKCTLR_CKEN; - } else { - SDIO->CLKCTLR &= (uint16_t)~(SDIO_CLKCTLR_CKEN); - } -} - -/** - * @brief Configure the power state of SDIO. - * @param SDIO_PwrState: new Power state for SDIO. - * This value will be : - * @arg SDIO_PWRSTATE_ON - * @arg SDIO_PWRSTATE_OFF - * @retval None - */ -void SDIO_SetPWRState(uint32_t SDIO_PwrState) -{ - /* Update the SDIO POWER */ - SDIO->POWER |= SDIO_PwrState; -} - -/** - * @brief Get the power state of SDIO. - * @param None - * @retval Power state for SDIO. - * This value will be : - * - 0x00: Power OFF - * - 0x02: Power UP - * - 0x03: Power ON - */ -uint32_t SDIO_GetPWRState(void) -{ - return (SDIO->POWER & (~POWER_PWRSTATE_MASK)); -} - -/** - * @brief Configure interrupts enables. - * @param SDIO_INT: The interrupts sources to configure. - * This value will be : - * @arg SDIO_INT_CCRCFAIL: Command response CRC failed interrupt - * @arg SDIO_INT_DTCRCFAIL: Data CRC failed interrupt - * @arg SDIO_INT_CMDTMOUT: Command response timeout interrupt - * @arg SDIO_INT_DTTMOUT: Data timeout interrupt - * @arg SDIO_INT_TXURE: Transmit FIFO underrun error interrupt - * @arg SDIO_INT_RXORE: Received FIFO overrun error interrupt - * @arg SDIO_INT_CMDREND: Command response received (CRC check passed) interrupt - * @arg SDIO_INT_CMDSENT: Command sent (no response required) interrupt - * @arg SDIO_INT_DTEND: Data end (data counter, SDIDTCNT, is zero) interrupt - * @arg SDIO_INT_STBITE: Start bit not detected on all data signals in wide bus mode interrupt - * @arg SDIO_INT_DTBLKEND: Data block sent/received (CRC check passed) interrupt - * @arg SDIO_INT_CMDRUN: Command transfer in progress interrupt - * @arg SDIO_INT_TXRUN: Data transmit in progress interrupt - * @arg SDIO_INT_RXRUN: Data receive in progress interrupt - * @arg SDIO_INT_TXFIFOHE: Transmit FIFO Half Empty interrupt - * @arg SDIO_INT_RXFIFOHF: Receive FIFO Half Full interrupt - * @arg SDIO_INT_TXFIFOF: Transmit FIFO full interrupt - * @arg SDIO_INT_RXFIFOF: Receive FIFO full interrupt - * @arg SDIO_INT_TXFIFOE: Transmit FIFO empty interrupt - * @arg SDIO_INT_RXFIFOE: Receive FIFO empty interrupt - * @arg SDIO_INT_TXDTVAL: Data valid in transmit FIFO interrupt - * @arg SDIO_INT_RXDTVAL: Data valid in receive FIFO interrupt - * @arg SDIO_INT_SDIOINT: SD I/O interrupt received interrupt - * @arg SDIO_INT_ATAEND: CE-ATA command completion signal received for CMD61 interrupt - * @param NewValue: ENABLE or DISABLE. - * @retval None - */ -void SDIO_INTConfig(uint32_t SDIO_INT, TypeState NewValue) -{ - if (NewValue != DISABLE) { - /* Enable the interrupt */ - SDIO->IER |= SDIO_INT; - } else { - /* Disable the interrupt */ - SDIO->IER &= ~SDIO_INT; - } -} - -/** - * @brief Enable or disable the DMA request for SDIO. - * @param NewValue: ENABLE or DISABLE. - * @retval None - */ -void SDIO_DMA_Enable(TypeState NewValue) -{ - if (NewValue != DISABLE) { - /* Enable DMA request */ - SDIO->DTCTLR |= SDIO_DTCTLR_DMAEN; - } else { - /* Disenable DMA request */ - SDIO->DTCTLR &= (uint16_t)~((uint16_t)SDIO_DTCTLR_DMAEN); - } -} - -/** - * @brief Initialize the SDIO Command. - * @param SDIO_CmdInitParaStruct : pointer to a SDIO_CmdInitPara structure. - * @retval None - */ -void SDIO_SendCMD(SDIO_CmdInitPara *SDIO_CmdInitParaStruct) -{ - uint32_t temp = 0; - - /* SDIO PARA Configuration */ - /* Configure the SDIO_CMDParameter value */ - SDIO->PARA = SDIO_CmdInitParaStruct->SDIO_CMDParameter; - - /* SDIO CMD Configuration */ - /* Get the SDIO CMD value */ - temp = SDIO->CMD; - /* Clear CMD register */ - temp &= CMD_CLEAR_MASK; - /* Configure the SDIO_CMDIndex value */ - /* Configure the SDIO_ResponseType value */ - /* Configure the SDIO_WaitINTState value */ - /* Configure the SDIO_CSMState value */ - temp |= (uint32_t)SDIO_CmdInitParaStruct->SDIO_CMDIndex | SDIO_CmdInitParaStruct->SDIO_ResponseType - | SDIO_CmdInitParaStruct->SDIO_WaitINTState | SDIO_CmdInitParaStruct->SDIO_CSMState; - - /* Update the SDIO CMD */ - SDIO->CMD = temp; -} - -/** - * @brief Fill SDIO_CmdInitStruct member with a default value. - * @param SDIO_CmdInitParaStruct: pointer to an SDIO_CmdInitPara structure. - * @retval None - */ -void SDIO_CMDParaInit(SDIO_CmdInitPara *SDIO_CmdInitParaStruct) -{ - /* Fill the default value */ - SDIO_CmdInitParaStruct->SDIO_CMDParameter = 0x00; - SDIO_CmdInitParaStruct->SDIO_CMDIndex = 0x00; - SDIO_CmdInitParaStruct->SDIO_ResponseType = SDIO_RESPONSETYPE_NO ; - SDIO_CmdInitParaStruct->SDIO_WaitINTState = SDIO_WAITINTSTATE_NO; - SDIO_CmdInitParaStruct->SDIO_CSMState = SDIO_CSMSTATE_DISABLE; -} - -/** - * @brief Return last response command index. - * @param None - * @retval Return last response command index. - */ -uint8_t SDIO_GetCMDResponse(void) -{ - return (uint8_t)(SDIO->RESPCMD); -} - -/** - * @brief Return the response for the last received command. - * @param SDIO_RESP: The SDIO response registers. - * This value will be : - * @arg SDIO_RESP1: Response Register 1 - * @arg SDIO_RESP2: Response Register 2 - * @arg SDIO_RESP3: Response Register 3 - * @arg SDIO_RESP4: Response Register 4 - * @retval The Corresponding response register value. - */ -uint32_t SDIO_GetResponse(uint32_t SDIO_RESP) -{ - __IO uint32_t temp = 0; - - temp = SDIO_RESP_ADDR + SDIO_RESP; - - return (*(__IO uint32_t *) temp); -} - -/** - * @brief Initialize the SDIO SDIO_DataInitParaStruct members. - * @param SDIO_DataInitParaStruct : pointer to a SDIO_DataInitPara structure. - * @retval None - */ -void SDIO_DataConfig(SDIO_DataInitPara *SDIO_DataInitParaStruct) -{ - uint32_t temp = 0; - - /* SDIO DTTR Configuration */ - /* Set the SDIO SDIO_DataTimeOut value */ - SDIO->DTTR = SDIO_DataInitParaStruct->SDIO_DataTimeOut; - - /* SDIO DTLEN Configuration */ - /* Set the SDIO SDIO_DataLength value */ - SDIO->DTLEN = SDIO_DataInitParaStruct->SDIO_DataLength; - - /* SDIO DTCTLR Configuration */ - /* Get the SDIO DTCTLR value */ - temp = SDIO->DTCTLR; - /* Clear DTCTLR register */ - temp &= DTCTLR_CLEAR_MASK; - /* Configure the SDIO_DataBlockSize value */ - /* Configure the SDIO_TransDirection value */ - /* Configure the SDIO_TransMode value */ - /* Configure the SDIO_DSMState value */ - temp |= (uint32_t)SDIO_DataInitParaStruct->SDIO_DataBlockSize | SDIO_DataInitParaStruct->SDIO_TransDirection - | SDIO_DataInitParaStruct->SDIO_TransMode | SDIO_DataInitParaStruct->SDIO_DSMState; - - /* Update the SDIO DTCTLR */ - SDIO->DTCTLR = temp; -} - -/** - * @brief Fill each SDIO_DataInitParaStruct member with a default value. - * @param SDIO_DataInitParaStruct: pointer to an SDIO_DataInitPara structure. - * @retval None - */ -void SDIO_DataParaInit(SDIO_DataInitPara *SDIO_DataInitParaStruct) -{ - /* Fill the default value */ - SDIO_DataInitParaStruct->SDIO_DataTimeOut = 0xFFFFFFFF; - SDIO_DataInitParaStruct->SDIO_DataLength = 0x00; - SDIO_DataInitParaStruct->SDIO_DataBlockSize = SDIO_DATABLOCKSIZE_1B; - SDIO_DataInitParaStruct->SDIO_TransDirection = SDIO_TRANSDIRECTION_TOCARD; - SDIO_DataInitParaStruct->SDIO_TransMode = SDIO_TRANSMODE_BLOCK; - SDIO_DataInitParaStruct->SDIO_DSMState = SDIO_DSMSTATE_DISABLE; -} - -/** - * @brief Return the number of remaining data bytes to be transferred to card. - * @param None - * @retval Number of remaining data bytes to be transferred - */ -uint32_t SDIO_GetDataCount(void) -{ - return SDIO->DTCNT; -} - -/** - * @brief Read one word from receive FIFO. - * @param None - * @retval Data received - */ -uint32_t SDIO_ReadData(void) -{ - return SDIO->FIFO; -} - -/** - * @brief Write one word to transmit FIFO. - * @param Data: 32-bit data write to the card. - * @retval None - */ -void SDIO_WriteData(uint32_t Data) -{ - SDIO->FIFO = Data; -} - -/** - * @brief Return the number of words remaining to be written or read from FIFO. - * @param None - * @retval Remaining number of words. - */ -uint32_t SDIO_GetFIFOCount(void) -{ - return SDIO->FIFOCNT; -} - -/** - * @brief Start SD I/O Read Wait operation. - * @param NewValue: ENABLE or DISABLE. - * @retval None - */ -void SDIO_StartSDIOReadWait(TypeState NewValue) -{ - if (NewValue != DISABLE) { - /* Start Read Wait operation */ - SDIO->DTCTLR |= SDIO_DTCTLR_RWSTART; - } else { - SDIO->DTCTLR &= (uint16_t)~((uint16_t)SDIO_DTCTLR_RWSTART); - } -} - -/** - * @brief Stop the SD I/O Read Wait operation. - * @param NewValue: ENABLE or DISABLE. - * @retval None - */ -void SDIO_StopSDIOReadWait(TypeState NewValue) -{ - if (NewValue != DISABLE) { - SDIO->DTCTLR |= SDIO_DTCTLR_RWSTOP; - } else { - /* Stop Read Wait operation */ - SDIO->DTCTLR &= (uint16_t)~((uint16_t)SDIO_DTCTLR_RWSTOP); - } -} - -/** - * @brief Configure the SD I/O read wait mode. - * @param SDIO_ReadWaitMode: SD I/O Read Wait operation mode. - * This value will be : - * @arg SDIO_READWAITMODE_CLK: Read Wait operation realize by stopping SDIOCLK - * @arg SDIO_READWAITMODE_DAT2: Read Wait operation use SDIO_DAT2 - * @retval None - */ -void SDIO_SetSDIOReadWaitMode(uint32_t SDIO_ReadWaitMode) -{ - if (SDIO_ReadWaitMode == SDIO_READWAITMODE_CLK) { - /* Read Wait operation stop SDIOCLK */ - SDIO->DTCTLR |= SDIO_DTCTLR_RWMODE; - } else { - /* Read Wait operation use SDIO_DAT2 */ - SDIO->DTCTLR &= (uint16_t)~((uint16_t)SDIO_DTCTLR_RWMODE); - } -} - -/** - * @brief SD I/O Mode Operation configuration. - * @param NewValue: ENABLE or DISABLE. - * @retval None - */ -void SDIO_SetSDIOOperation(TypeState NewValue) -{ - if (NewValue != DISABLE) { - /* Enable I/O Mode Operation */ - SDIO->DTCTLR |= SDIO_DTCTLR_SDIOEN; - } else { - /* Disenable I/O Mode Operation */ - SDIO->DTCTLR &= (uint16_t)~((uint16_t)SDIO_DTCTLR_SDIOEN); - } -} - -/** - * @brief Enable or disable the SD I/O suspend operation. - * @param NewValue: ENABLE or DISABLE. - * @retval None - */ -void SDIO_SendSDIOSuspend_Enable(TypeState NewValue) -{ - if (NewValue != DISABLE) { - /* Enable suspend operation */ - SDIO->CMD |= SDIO_CMD_SDIOSUSPEND; - } else { - /* Disenable suspend operation */ - SDIO->CMD &= (uint16_t)~((uint16_t)SDIO_CMD_SDIOSUSPEND); - } -} - -/** - * @brief Enable or disable the CE-ATA command completion signal. - * @param NewValue: ENABLE or DISABLE. - * @retval None - */ -void SDIO_CMDCompletion_Enable(TypeState NewValue) -{ - if (NewValue != DISABLE) { - /* Enable CE-ATA command completion signal */ - SDIO->CMD |= SDIO_CMD_ENCMDC; - } else { - /* Disenable CE-ATA command completion signal */ - SDIO->CMD &= (uint16_t)~((uint16_t)SDIO_CMD_ENCMDC); - } -} - -/** - * @brief Enable or disable the CE-ATA interrupt. - * @param NewValue: ENABLE or DISABLE. - * @retval None - */ -void SDIO_CEATAInt_Enable(TypeState NewValue) -{ - if (NewValue != ENABLE) { - /* Enable CE-ATA interrupt */ - SDIO->CMD |= SDIO_CMD_NIEN; - } else { - /* Disenable CE-ATA interrupt */ - SDIO->CMD &= (uint16_t)~((uint16_t)SDIO_CMD_NIEN); - } -} - -/** - * @brief Send CE-ATA command (CMD61). - * @param NewValue: ENABLE or DISABLE. - * @retval None - */ -void SDIO_SendCEATA_Enable(TypeState NewValue) -{ - if (NewValue != DISABLE) { - SDIO->CMD |= SDIO_CMD_ATACMD; - } else { - SDIO->CMD &= (uint16_t)~((uint16_t)SDIO_CMD_ATACMD); - } -} - -/** - * @brief Check whether the flag is set or not. - * @param SDIO_FLAG: the flag to check. - * This value will be : - * @arg SDIO_FLAG_CCRCFAIL: Command response received (CRC failed) - * @arg SDIO_FLAG_DTCRCFAIL: Data block sent/received (CRC failed) - * @arg SDIO_FLAG_CMDTMOUT: Command response timeout - * @arg SDIO_FLAG_DTTMOUT: Data timeout - * @arg SDIO_FLAG_TXURE: Transmit FIFO underrun error - * @arg SDIO_FLAG_RXORE: Received FIFO overrun error - * @arg SDIO_FLAG_CMDREND: Command response received (CRC check passed) - * @arg SDIO_FLAG_CMDSENT: Command sent (no response required) - * @arg SDIO_FLAG_DTEND: Data end (data counter, SDIDTCNT, is zero) - * @arg SDIO_FLAG_STBITE: Start bit not detected on all data signals in wide - * bus mode. - * @arg SDIO_FLAG_DTBLKEND: Data block sent/received (CRC check passed) - * @arg SDIO_FLAG_CMDRUN: Command transfer in progress - * @arg SDIO_FLAG_TXRUN: Data transmit in progress - * @arg SDIO_FLAG_RXRUN: Data receive in progress - * @arg SDIO_FLAG_TXFIFOHE: Transmit FIFO Half Empty - * @arg SDIO_FLAG_RXFIFOHF: Receive FIFO Half Full - * @arg SDIO_FLAG_TXFIFOF: Transmit FIFO full - * @arg SDIO_FLAG_RXFIFOF: Receive FIFO full - * @arg SDIO_FLAG_TXFIFOE: Transmit FIFO empty - * @arg SDIO_FLAG_RXFIFOE: Receive FIFO empty - * @arg SDIO_FLAG_TXDTVAL: Data available in transmit FIFO - * @arg SDIO_FLAG_RXDTVAL: Data available in receive FIFO - * @arg SDIO_FLAG_SDIOINT: SD I/O interrupt received - * @arg SDIO_FLAG_ATAEND: CE-ATA command completion signal received for CMD61 - * @retval The new state of SDIO_FLAG (SET or RESET). - */ -TypeState SDIO_GetBitState(uint32_t SDIO_FLAG) -{ - if ((SDIO->STR & SDIO_FLAG) != (uint32_t)RESET) { - return SET; - } else { - return RESET; - } -} - -/** - * @brief Clear the pending flags. - * @param SDIO_FLAG: the flag to clear. - * This value will be : - * @arg SDIO_FLAG_CCRCFAIL: Command response received (CRC check failed) - * @arg SDIO_FLAG_DTCRCFAIL: Data block sent/received (CRC check failed) - * @arg SDIO_FLAG_CMDTMOUT: Command response timeout - * @arg SDIO_FLAG_DTTMOUT: Data timeout - * @arg SDIO_FLAG_TXURE: Transmit FIFO underrun error - * @arg SDIO_FLAG_RXORE: Received FIFO overrun error - * @arg SDIO_FLAG_CMDREND: Command response received (CRC check passed) - * @arg SDIO_FLAG_CMDSENT: Command sent (no response required) - * @arg SDIO_FLAG_DTEND: Data end (data counter, SDIO_DTCNT, is zero) - * @arg SDIO_FLAG_STBITE: Start bit not detected on all data signals in wide bus mode - * @arg SDIO_FLAG_DTBLKEND: Data block sent/received (CRC check passed) - * @arg SDIO_FLAG_SDIOINT: SD I/O interrupt received - * @arg SDIO_FLAG_ATAEND: CE-ATA command completion signal received for CMD61 - * @retval None - */ -void SDIO_ClearBitState(uint32_t SDIO_FLAG) -{ - SDIO->ICR = SDIO_FLAG; -} - -/** - * @brief Check whether the interrupt is pending or not. - * @param SDIO_INT: the SDIO interrupt source to check. - * This value will be : - * @arg SDIO_INT_CCRCFAIL: Command response received (CRC check failed) interrupt - * @arg SDIO_INT_DTCRCFAIL: Data block sent/received (CRC check failed) interrupt - * @arg SDIO_INT_CMDTMOUT: Command response timeout interrupt - * @arg SDIO_INT_DTTMOUT: Data timeout interrupt - * @arg SDIO_INT_TXURE: Transmit FIFO underrun error interrupt - * @arg SDIO_INT_RXORE: Received FIFO overrun error interrupt - * @arg SDIO_INT_CMDREND: Command response received (CRC check passed) interrupt - * @arg SDIO_INT_CMDSENT: Command sent (no response required) interrupt - * @arg SDIO_INT_DTEND: Data end (data counter, SDIDTCNT, is zero) interrupt - * @arg SDIO_INT_STBITE: Start bit not detected on all data signals in wide bus mode interrupt - * @arg SDIO_INT_DTBLKEND: Data block sent/received (CRC check passed) interrupt - * @arg SDIO_INT_CMDRUN: Command transfer in progress interrupt - * @arg SDIO_INT_TXRUN: Data transmit in progress interrupt - * @arg SDIO_INT_RXRUN: Data receive in progress interrupt - * @arg SDIO_INT_TXFIFOHE: Transmit FIFO Half Empty interrupt - * @arg SDIO_INT_RXFIFOHF: Receive FIFO Half Full interrupt - * @arg SDIO_INT_TXFIFOF: Transmit FIFO full interrupt - * @arg SDIO_INT_RXFIFOF: Receive FIFO full interrupt - * @arg SDIO_INT_TXFIFOE: Transmit FIFO empty interrupt - * @arg SDIO_INT_RXFIFOE: Receive FIFO empty interrupt - * @arg SDIO_INT_TXDTVAL: Data available in transmit FIFO interrupt - * @arg SDIO_INT_RXDTVAL: Data available in receive FIFO interrupt - * @arg SDIO_INT_SDIOINT: SD I/O interrupt received interrupt - * @arg SDIO_INT_ATAEND: CE-ATA command completion signal received for CMD61 interrupt - * @retval The new state of SDIO_INT (SET or RESET). - */ -TypeState SDIO_GetIntBitState(uint32_t SDIO_INT) -{ - if ((SDIO->STR & SDIO_INT) != (uint32_t)RESET) { - return SET; - } else { - return RESET; - } -} - -/** - * @brief Clear the interrupt pending bits. - * @param SDIO_INT: the interrupt pending bit to clear. - * This value will be : - * @arg SDIO_INT_CCRCFAIL: Command response received (CRC check failed) interrupt - * @arg SDIO_INT_DTCRCFAIL: Data block sent/received (CRC check failed) interrupt - * @arg SDIO_INT_CMDTMOUT: Command response timeout interrupt - * @arg SDIO_INT_DTTMOUT: Data timeout interrupt - * @arg SDIO_INT_TXURE: Transmit FIFO underrun error interrupt - * @arg SDIO_INT_RXORE: Received FIFO overrun error interrupt - * @arg SDIO_INT_CMDREND: Command response received (CRC check passed) interrupt - * @arg SDIO_INT_CMDSENT: Command sent (no response required) interrupt - * @arg SDIO_INT_DTEND: Data end (data counter, SDIDTCNT, is zero) interrupt - * @arg SDIO_INT_STBITE: Start bit not detected on all data signals in wide - * bus mode interrupt - * @arg SDIO_INT_SDIOINT: SD I/O interrupt received interrupt - * @arg SDIO_INT_ATAEND: CE-ATA command completion signal received for CMD61 - * @retval None - */ -void SDIO_ClearIntBitState(uint32_t SDIO_INT) -{ - SDIO->ICR = SDIO_INT; -} - -/** - * @} - */ - -/** - * @} - */ - -/** - * @} - */ -#endif diff --git a/bsp/gd32103c-eval/Libraries/GD32F1xx_standard_peripheral/Source/gd32f10x_spi.c b/bsp/gd32103c-eval/Libraries/GD32F1xx_standard_peripheral/Source/gd32f10x_spi.c deleted file mode 100644 index b55a6dc911..0000000000 --- a/bsp/gd32103c-eval/Libraries/GD32F1xx_standard_peripheral/Source/gd32f10x_spi.c +++ /dev/null @@ -1,554 +0,0 @@ -/** - ****************************************************************************** - * @brief SPI functions of the firmware library. - ****************************************************************************** - */ - -/* Includes ------------------------------------------------------------------*/ -#include "gd32f10x_spi.h" -#include "gd32f10x_rcc.h" - -/** @addtogroup GD32F10x_Firmware - * @{ - */ - -/** @defgroup SPI - * @brief SPI driver modules - * @{ - */ - -/** @defgroup SPI_Private_Defines - * @{ - */ - -/* SPI registers Masks */ -#define CTLR1_CLEAR_MASK ((uint16_t)0x3040) -#define I2SCTLR_CLEAR_MASK ((uint16_t)0xF040) - -/* I2S clock source selection Masks */ -#define I2S2_CLOCK_SRC ((uint32_t)(0x00020000)) -#define I2S3_CLOCK_SRC ((uint32_t)(0x00040000)) -#define I2S_MUL_MASK ((uint32_t)(0x0000F000)) -#define I2S_DIV_MASK ((uint32_t)(0x000000F0)) -/** - * @} - */ - -/** @defgroup SPI_Private_Functions - * @{ - */ - -/** - * @brief Reset the SPIx and the I2Sx peripheral. - * @param SPIx: the SPI/I2S peripheral where x can be 1..3. - * @retval None - */ -void SPI_I2S_DeInit(SPI_TypeDef *SPIx) -{ - if (SPIx == SPI1) { - /* Reset SPI1 */ - RCC_APB2PeriphReset_Enable(RCC_APB2PERIPH_SPI1RST, ENABLE); - - RCC_APB2PeriphReset_Enable(RCC_APB2PERIPH_SPI1RST, DISABLE); - } else if (SPIx == SPI2) { - /* Reset SPI2 and I2S2 peripheral */ - RCC_APB1PeriphReset_Enable(RCC_APB1PERIPH_SPI2RST, ENABLE); - RCC_APB1PeriphReset_Enable(RCC_APB1PERIPH_SPI2RST, DISABLE); - } else if (SPIx == SPI3) { - /* Reset SPI3 and I2S3 peripheral */ - RCC_APB1PeriphReset_Enable(RCC_APB1PERIPH_SPI3RST, ENABLE); - RCC_APB1PeriphReset_Enable(RCC_APB1PERIPH_SPI3RST, DISABLE); - } -} - -/** - * @brief Initialize the SPIx peripheral. - * @param SPIx: the SPI/I2S peripheral where x can be 1..3. - * @param SPI_InitParameter: The structuer contains configuration information. - * @retval None - */ -void SPI_Init(SPI_TypeDef *SPIx, SPI_InitPara *SPI_InitParameter) -{ - uint16_t temp_ctrl1 = 0; - - /* Configure SPIx CTRL1 according to the SPI_InitParameter */ - temp_ctrl1 = SPIx->CTLR1; - temp_ctrl1 &= CTLR1_CLEAR_MASK; - temp_ctrl1 |= (uint16_t)((uint32_t)SPI_InitParameter->SPI_TransType | SPI_InitParameter->SPI_Mode | - SPI_InitParameter->SPI_FrameFormat | SPI_InitParameter->SPI_SCKPL | - SPI_InitParameter->SPI_SCKPH | SPI_InitParameter->SPI_SWNSSEN | - SPI_InitParameter->SPI_PSC | SPI_InitParameter->SPI_FirstBit); - SPIx->CTLR1 = temp_ctrl1; - - /* Configure SPIx CRC Polynomial */ - SPIx->CPR = SPI_InitParameter->SPI_CRCPOL; - - /* Configure the I2SSEL bit in I2SCTLR register as SPI mode */ - SPIx->I2SCTLR &= ~SPI_I2SCTLR_I2SSEL; - -} - -/** - * @brief Initialize the I2Sx peripheral. - * @param SPIx: the SPI/I2S peripheral where x can be 2 or 3. - * @param I2S_InitParameter: The structuer contains configuration information. - * @retval None - */ -void I2S_Init(SPI_TypeDef *SPIx, I2S_InitPara *I2S_InitParameter) -{ - uint16_t temp_i2sctrl = 0, div = 2, of = 0; - uint32_t temp = 0; - RCC_ClocksPara RCC_Clocks; - uint32_t sourceclock = 0; - - /* SPIx I2SCTLR & I2SCKP Configuration */ - /* Deinit I2SCTLR I2SCKP register */ - SPIx->I2SCTLR &= I2SCTLR_CLEAR_MASK; - SPIx->I2SCKP = 0x0002; - - /* Default config of the prescaler*/ - if (I2S_InitParameter->I2S_AudioFreq == I2S_AUDIOFREQ_DEFAULT) { - of = (uint16_t)0; - div = (uint16_t)2; - } else { - /* Get the I2S clock source */ - if (((uint32_t)SPIx) == SPI2_BASE) { - temp = I2S2_CLOCK_SRC; - } else { - temp = I2S3_CLOCK_SRC; - } - - /* I2S clock source configuration depend on different device */ -#ifdef GD32F10X_CL - if ((RCC->GCFGR2 & temp) != 0) { - /* Get RCC PLL3 multiplier */ - temp = (uint32_t)((RCC->GCFGR2 & I2S_MUL_MASK) >> 12); - - if ((temp > 5) && (temp < 15)) { - /* Multiplier is between 8 and 14 (value 15 is forbidden) */ - temp += 2; - } else { - if (temp == 15) { - /* Multiplier is 20 */ - temp = 20; - } - } - /* Get the PREDV2 value */ - sourceclock = (uint32_t)(((RCC->GCFGR2 & I2S_DIV_MASK) >> 4) + 1); - - /* Calculate sourceclock based on PLL3 and PREDV2 */ - sourceclock = (uint32_t)((HSE_VALUE / sourceclock) * temp * 2); - } else { - /* Get system clock */ - RCC_GetClocksFreq(&RCC_Clocks); - sourceclock = RCC_Clocks.CK_SYS_Frequency; - } -#else - /* Get system clock */ - RCC_GetClocksFreq(&RCC_Clocks); - sourceclock = RCC_Clocks.CK_SYS_Frequency; -#endif /* GD32F10X_CL */ - - /* Calculate the prescaler depending on the MCLK output state and the data format with a flaoting point. */ - if (I2S_InitParameter->I2S_MCKOE == I2S_MCK_ENABLE) { - temp = (uint16_t)(((((sourceclock / 256) * 10) / I2S_InitParameter->I2S_AudioFreq)) + 5); - } else { - if (I2S_InitParameter->I2S_FrameFormat == I2S_FRAMEFORMAT_DL16b_CL16b) { - temp = (uint16_t)(((((sourceclock / 32) * 10) / I2S_InitParameter->I2S_AudioFreq)) + 5); - } else { - temp = (uint16_t)(((((sourceclock / 64) * 10) / I2S_InitParameter->I2S_AudioFreq)) + 5); - } - } - - /* Remove the flaoting point */ - temp = temp / 10; - of = (uint16_t)(temp & (uint16_t)0x0001); - div = (uint16_t)((temp - of) / 2); - of = (uint16_t)(of << 8); - } - - /* Inappropriate prescaler, Set the default values */ - if ((div < 1) || (div > 0xFF)) { - div = 2; - of = 0; - } - - /* Configure SPIx I2SCKP */ - SPIx->I2SCKP = (uint16_t)(div | (uint16_t)(of | (uint16_t)I2S_InitParameter->I2S_MCKOE)); - - /* Configure SPIx I2SCTLR according to the I2S_InitParameter */ - temp_i2sctrl = SPIx->I2SCTLR; - temp_i2sctrl |= (uint16_t)(SPI_I2SCTLR_I2SSEL | (uint16_t)(I2S_InitParameter->I2S_Mode | \ - (uint16_t)(I2S_InitParameter->I2S_STD | (uint16_t)(I2S_InitParameter->I2S_FrameFormat | \ - (uint16_t)I2S_InitParameter->I2S_CKPL)))); - SPIx->I2SCTLR = temp_i2sctrl; - -} - -/** - * @brief Initial SPI_InitParameter members. - * @param SPI_InitParameter : pointer to a SPI_InitPara structure. - * @retval None - */ -void SPI_ParaInit(SPI_InitPara *SPI_InitParameter) -{ - /* Reset SPI init structure parameters values */ - SPI_InitParameter->SPI_TransType = SPI_TRANSTYPE_FULLDUPLEX; - SPI_InitParameter->SPI_Mode = SPI_MODE_SLAVE; - SPI_InitParameter->SPI_FrameFormat = SPI_FRAMEFORMAT_8BIT; - SPI_InitParameter->SPI_SCKPL = SPI_SCKPL_LOW; - SPI_InitParameter->SPI_SCKPH = SPI_SCKPH_1EDGE; - SPI_InitParameter->SPI_SWNSSEN = SPI_SWNSS_HARD; - SPI_InitParameter->SPI_PSC = SPI_PSC_2; - SPI_InitParameter->SPI_FirstBit = SPI_FIRSTBIT_MSB; - SPI_InitParameter->SPI_CRCPOL = 7; -} - -/** - * @brief Initial I2S_InitParameter members. - * @param I2S_InitParameter : pointer to a I2S_InitPara structure. - * @retval None - */ -void I2S_ParaInit(I2S_InitPara *I2S_InitParameter) -{ - /* Reset I2S init structure parameters values */ - I2S_InitParameter->I2S_Mode = I2S_MODE_SLAVETX; - I2S_InitParameter->I2S_STD = I2S_STD_PHILLIPS; - I2S_InitParameter->I2S_FrameFormat = I2S_FRAMEFORMAT_DL16b_CL16b; - I2S_InitParameter->I2S_MCKOE = I2S_MCK_DISABLE; - I2S_InitParameter->I2S_AudioFreq = I2S_AUDIOFREQ_DEFAULT; - I2S_InitParameter->I2S_CKPL = I2S_CKPL_LOW; -} - -/** - * @brief Enable or disable the SPI peripheral. - * @param SPIx: the SPI/I2S peripheral where x can be 1..3. - * @param NewValue: ENABLE or DISABLE. - * @retval None - */ -void SPI_Enable(SPI_TypeDef *SPIx, TypeState NewValue) -{ - if (NewValue != DISABLE) { - SPIx->CTLR1 |= SPI_CTLR1_SPIEN; - } else { - SPIx->CTLR1 &= ~SPI_CTLR1_SPIEN; - } -} - -/** - * @brief Enable or disable the I2S peripheral. - * @param SPIx: the SPI/I2S peripheral where x can be 2 or 3. - * @param NewValue: ENABLE or DISABLE. - * @retval None - */ -void I2S_Enable(SPI_TypeDef *SPIx, TypeState NewValue) -{ - if (NewValue != DISABLE) { - SPIx->I2SCTLR |= SPI_I2SCTLR_I2SEN; - } else { - SPIx->I2SCTLR &= ~SPI_I2SCTLR_I2SEN; - } -} - -/** - * @brief Enable or disable the SPI or I2S interrupts. - * @param SPIx: the SPI/I2S peripheral where x can be 1..3. - * @param SPI_I2S_INT: specifies the SPI or I2S interrupt source. Select one of the follwing values : - * @arg SPI_I2S_INT_TBE: Tx buffer empty interrupt mask - * @arg SPI_I2S_INT_RBNE: Rx buffer not empty interrupt mask - * @arg SPI_I2S_INT_ERR: Error interrupt mask - * @param NewValue: ENABLE or DISABLE. - * @retval None - */ -void SPI_I2S_INTConfig(SPI_TypeDef *SPIx, uint8_t SPI_I2S_INT, TypeState NewValue) -{ - uint16_t intmask = 0 ; - - /* Get the interrupt enable bit in CTRL2 */ - intmask = (uint16_t)1 << (uint16_t)(SPI_I2S_INT >> 4); - - /* Enable or disable the selected interrupt */ - if (NewValue != DISABLE) { - SPIx->CTLR2 |= intmask; - } else { - SPIx->CTLR2 &= (uint16_t)~intmask; - } -} - -/** - * @brief Enable or disable the SPIx or I2Sx DMA transfer request. - * @param SPIx: the SPI/I2S peripheral where x can be 1..3. - * @param SPI_I2S_DMAReq: Select the SPI or I2S DMA transfer request. Select one of the follwing values : - * @arg SPI_I2S_DMA_TX: Tx buffer DMA transfer request - * @arg SPI_I2S_DMA_RX: Rx buffer DMA transfer request - * @param NewValue: ENABLE or DISABLE. - * @retval None - */ -void SPI_I2S_DMA_Enable(SPI_TypeDef *SPIx, uint16_t SPI_I2S_DMAReq, TypeState NewValue) -{ - if (NewValue != DISABLE) { - SPIx->CTLR2 |= SPI_I2S_DMAReq; - } else { - SPIx->CTLR2 &= (uint16_t)~SPI_I2S_DMAReq; - } -} - -/** - * @brief Send a Data by the SPIx or I2Sx peripheral. - * @param SPIx: the SPI/I2S peripheral where x can be 1..3. - * @param Data : Data to be Send. - * @retval None - */ -void SPI_I2S_SendData(SPI_TypeDef *SPIx, uint16_t Data) -{ - SPIx->DTR = Data; -} - -/** - * @brief Return the received data by the SPIx or I2Sx peripheral. - * @param SPIx: the SPI/I2S peripheral where x can be 1..3. - * @retval The value of the received data. - */ -uint16_t SPI_I2S_ReceiveData(SPI_TypeDef *SPIx) -{ - return SPIx->DTR; -} - -/** - * @brief NSS pin internal software management. - * @param SPIx: the SPI/I2S peripheral where x can be 1..3. - * @param SPI_SWNSS: specifies the SPI NSS internal state. Select one of the follwing values : - * @arg SPI_SWNSS_SET: Set NSS pin internally - * @arg SPI_SWNSS_RESET: Reset NSS pin internally - * @retval None - */ -void SPI_SWNSSConfig(SPI_TypeDef *SPIx, uint16_t SPI_SWNSS) -{ - if (SPI_SWNSS != SPI_SWNSS_RESET) { - /* Set NSS pin */ - SPIx->CTLR1 |= SPI_CTLR1_SWNSS; - } else { - /* Reset NSS pin */ - SPIx->CTLR1 &= ~SPI_CTLR1_SWNSS; - } -} - -/** - * @brief Enable or disable the NSS output. - * @param SPIx: the SPI/I2S peripheral where x can be 1..3. - * @param NewValue: ENABLE or DISABLE. - * @retval None - */ -void SPI_NSSDRV(SPI_TypeDef *SPIx, TypeState NewValue) -{ - if (NewValue != DISABLE) { - SPIx->CTLR2 |= SPI_CTLR2_NSSDRV; - } else { - SPIx->CTLR2 &= ~SPI_CTLR2_NSSDRV; - } -} - -/** - * @brief Configure the data frame format. - * @param SPIx: the SPI/I2S peripheral where x can be 1..3. - * @param SPI_FrameFormat: Select the data frame format. Select one of the follwing values : - * @arg SPI_FRAMEFORMAT_16BIT: Set data frame format to 16bit - * @arg SPI_FRAMEFORMAT_8BIT: Set data frame format to 8bit - * @retval None - */ -void SPI_FrameFormatConfig(SPI_TypeDef *SPIx, uint16_t SPI_FrameFormat) -{ - /* Clear FF16 bit */ - SPIx->CTLR1 &= (uint16_t)~SPI_FRAMEFORMAT_16BIT; - /* Set new FF16 bit value */ - SPIx->CTLR1 |= SPI_FrameFormat; -} - -/** - * @brief Send the SPIx CRC value. - * @param SPIx: the SPI/I2S peripheral where x can be 1..3. - * @retval None - */ -void SPI_SendCRCNext(SPI_TypeDef *SPIx) -{ - /* Enable the CRC transmission */ - SPIx->CTLR1 |= SPI_CTLR1_CRCNT; -} - -/** - * @brief Enable or disable the CRC calculation. - * @param SPIx: the SPI/I2S peripheral where x can be 1..3. - * @param NewValue: ENABLE or DISABLE. - * @retval None - */ -void SPI_CRC_Enable(SPI_TypeDef *SPIx, TypeState NewValue) -{ - if (NewValue != DISABLE) { - /* Enable the CRC calculation */ - SPIx->CTLR1 |= SPI_CTLR1_CRCEN; - } else { - /* Disable the CRC calculation */ - SPIx->CTLR1 &= ~SPI_CTLR1_CRCEN; - } -} - -/** - * @brief Get the transmit or the receive CRC register value. - * @param SPIx: the SPI/I2S peripheral where x can be 1..3. - * @param SPI_CRC: Select the transmit or the receive CRC register. Select one of the follwing values : - * @arg SPI_CRC_TX: Selects Tx CRC register - * @arg SPI_CRC_RX: Selects Rx CRC register - * @retval The selected CRC register value. - */ -uint16_t SPI_GetCRC(SPI_TypeDef *SPIx, uint8_t SPI_CRC) -{ - if (SPI_CRC != SPI_CRC_RX) { - /* Transmit CRC value */ - return SPIx->TCR; - } else { - /* Receive CRC value */ - return SPIx->RCR; - } -} - -/** - * @brief Get the CRC Polynomial value. - * @param SPIx: the SPI/I2S peripheral where x can be 1..3. - * @retval The CRC Polynomial value. - */ -uint16_t SPI_GetCRCPolynomial(SPI_TypeDef *SPIx) -{ - return SPIx->CPR; -} - -/** - * @brief Select the transfer direction in bidirectional mode. - * @param SPIx: the SPI/I2S peripheral where x can be 1..3. - * @param SPI_BDOE: The transfer direction in bi-directional mode. Select one of the follwing values : - * @arg SPI_BDOE_TX: Selects Tx transmission direction - * @arg SPI_BDOE_RX: Selects Rx receive direction - * @retval None - */ -void SPI_BDOEConfig(SPI_TypeDef *SPIx, uint16_t SPI_BDOE) -{ - if (SPI_BDOE == SPI_BDOE_TX) { - /* Transmit only mode*/ - SPIx->CTLR1 |= SPI_BDOE_TX; - } else { - /* Receive only mode */ - SPIx->CTLR1 &= SPI_BDOE_RX; - } -} - -/** - * @brief Check whether the flag is set or not. - * @param SPIx: the SPI/I2S peripheral where x can be 1..3. - * @param SPI_I2S_FLAG: Select the flag. Select one of the follwing values : - * @arg SPI_FLAG_TBE: Transmit buffer empty flag. - * @arg SPI_FLAG_RBNE: Receive buffer not empty flag. - * @arg SPI_FLAG_BSY: Busy flag. - * @arg SPI_FLAG_OVR: Overrun flag. - * @arg SPI_FLAG_MODF: Mode Fault flag. - * @arg SPI_FLAG_CRCERR: CRC Error flag. - * @arg I2S_FLAG_TBE: Transmit buffer empty flag. - * @arg I2S_FLAG_RBNE: Receive buffer not empty flag. - * @arg I2S_FLAG_BSY: Busy flag. - * @arg I2S_FLAG_OVR: Overrun flag. - * @arg I2S_FLAG_UDR: Underrun Error flag. - * @arg I2S_FLAG_CHSIDE: Channel Side flag. - * @retval The new state of SPI_I2S_FLAG. - */ -TypeState SPI_I2S_GetBitState(SPI_TypeDef *SPIx, uint16_t SPI_I2S_FLAG) -{ - /* Check the status of the selected flag */ - if ((SPIx->STR & SPI_I2S_FLAG) != (uint16_t)RESET) { - return SET; - } else { - return RESET; - } -} - -/** - * @brief Clear the flag, only used for clear CRCERR flag. - * @param SPIx: the SPI/I2S peripheral where x can be 1..3. - * @param SPI_I2S_FLAG: Select the flag. This parametric only can be SPI_FLAG_CRCERR. - * @note - * The other flags are cleared by software sequences: - * - OVR (OverRun error) flag is cleared by software sequence: a read - * operation to SPI_DTR register (SPI_I2S_ReceiveData()) followed by a read - * operation to SPI_STR register (SPI_I2S_GetBitState()). - * - UDR (UnderRun error) flag is cleared by a read operation to - * SPI_STR register (SPI_I2S_GetBitState()). - * - MODF (Mode Fault) flag is cleared by software sequence: a read/write - * operation to SPI_STR register (SPI_I2S_GetBitState()) followed by a - * write operation to SPI_CTLR1 register (SPI_Enable() to enable the SPI). - * @retval None - */ -void SPI_I2S_ClearBitState(SPI_TypeDef *SPIx, uint16_t SPI_I2S_FLAG) -{ - SPIx->STR = (uint16_t)~SPI_I2S_FLAG; -} - -/** - * @brief Check whether interrupt has occurred. - * @param SPIx: the SPI/I2S peripheral where x can be 1..3. - * @param SPI_I2S_INT: Select the SPI/I2S interrupt. Select one of the follwing values : - * @arg SPI_I2S_INT_TBE: Transmit buffer empty interrupt. - * @arg SPI_I2S_INT_RBNE: Receive buffer not empty interrupt. - * @arg SPI_I2S_INT_OVR: Overrun interrupt. - * @arg SPI_INT_MODF: Mode Fault interrupt. - * @arg SPI_INT_CRCERR: CRC Error interrupt. - * @arg I2S_INT_UDR: Underrun Error interrupt. - * @retval The new state of SPI_I2S_INT. - */ -TypeState SPI_I2S_GetIntBitState(SPI_TypeDef *SPIx, uint8_t SPI_I2S_INT) -{ - uint16_t intposition = 0, intmask = 0; - /* Get the interrupt pending bit and enable bit */ - intposition = 0x01 << (SPI_I2S_INT & 0x0F); - intmask = 0x01 << (SPI_I2S_INT >> 4); - - /* Check the status of the interrupt */ - if (((SPIx->STR & intposition) != (uint16_t)RESET) && (SPIx->CTLR2 & intmask)) { - return SET; - } else { - return RESET; - } -} - -/** - * @brief Clear the SPIx or I2S interrupt pending bit, only uesd for clear CRCERR interrupt. - * @param SPIx: the SPI/I2S peripheral where x can be 1..3. - * @param SPI_I2S_INT: Select the SPI or I2S interrupt. This parametric only can be SPI_INT_CRCERR. - * @note - * The other flags are cleared by software sequences: - * - OVR (OverRun error) flag is cleared by software sequence: a read - * operation to SPI_DTR register (SPI_I2S_ReceiveData()) followed by a read - * operation to SPI_STR register (SPI_I2S_GetBitState()). - * - UDR (UnderRun error) flag is cleared by a read operation to - * SPI_STR register (SPI_I2S_GetBitState()). - * - MODF (Mode Fault) flag is cleared by software sequence: a read/write - * operation to SPI_STR register (SPI_I2S_GetBitState()) followed by a - * write operation to SPI_CTLR1 register (SPI_Enable() to enable the SPI). - * @retval None - */ -void SPI_I2S_ClearIntBitState(SPI_TypeDef *SPIx, uint8_t SPI_I2S_INT) -{ - uint16_t itpos = 0; - - /* Clear the select interrupt pending bit. */ - itpos = 0x01 << (SPI_I2S_INT & 0x0F); - SPIx->STR = (uint16_t)~itpos; -} -/** - * @} - */ - -/** - * @} - */ - -/** - * @} - */ - diff --git a/bsp/gd32103c-eval/Libraries/GD32F1xx_standard_peripheral/Source/gd32f10x_timer.c b/bsp/gd32103c-eval/Libraries/GD32F1xx_standard_peripheral/Source/gd32f10x_timer.c deleted file mode 100644 index d5fd7fdf74..0000000000 --- a/bsp/gd32103c-eval/Libraries/GD32F1xx_standard_peripheral/Source/gd32f10x_timer.c +++ /dev/null @@ -1,2360 +0,0 @@ -/** - ****************************************************************************** - * @brief TIMER functions of the firmware library. - ****************************************************************************** - */ - -/* Includes ------------------------------------------------------------------*/ -#include "gd32f10x_timer.h" -#include "gd32f10x_rcc.h" - -/** @addtogroup GD32F10x_Firmware - * @{ - */ - -/** @defgroup TIMER - * @brief TIMER driver modules - * @{ - */ - -/** @defgroup TIMER_Private_Defines - * @{ - */ -/* TIMER registers bit mask */ -#define SMC_ETR_MASK ((uint16_t)0x00FF) -#define CHCTLR_OFFSET ((uint16_t)0x0018) -#define CHE_CHE_SET ((uint16_t)0x0001) -#define CHE_CHNE_SET ((uint16_t)0x0004) -/** - * @} - */ - -/* Private function prototypes */ -static void TI1_Config(TIMER_TypeDef *TIMERx, uint16_t TIMER_ICPolarity, uint16_t TIMER_ICSelection, - uint16_t TIMER_ICFilter); -static void TI2_Config(TIMER_TypeDef *TIMERx, uint16_t TIMER_ICPolarity, uint16_t TIMER_ICSelection, - uint16_t TIMER_ICFilter); -static void TI3_Config(TIMER_TypeDef *TIMERx, uint16_t TIMER_ICPolarity, uint16_t TIMER_ICSelection, - uint16_t TIMER_ICFilter); -static void TI4_Config(TIMER_TypeDef *TIMERx, uint16_t TIMER_ICPolarity, uint16_t TIMER_ICSelection, - uint16_t TIMER_ICFilter); - -/** @defgroup TIMER_Private_Functions - * @{ - */ - -/** - * @brief Deinitialize the TIMER . - * @param TIMERx: x ={ 0-13 } . - * @retval None - */ -void TIMER_DeInit(TIMER_TypeDef *TIMERx) -{ - if (TIMERx == TIMER0) { - RCC->APB2RCR |= RCC_APB2PERIPH_TIMER0RST; - RCC->APB2RCR &= ~RCC_APB2PERIPH_TIMER0; - } else if (TIMERx == TIMER1) { - RCC->APB1RCR |= RCC_APB1PERIPH_TIMER1RST; - RCC->APB1RCR &= ~RCC_APB1PERIPH_TIMER1; - } else if (TIMERx == TIMER2) { - RCC->APB1RCR |= RCC_APB1PERIPH_TIMER2RST; - RCC->APB1RCR &= ~RCC_APB1PERIPH_TIMER2; - } else if (TIMERx == TIMER3) { - RCC->APB1RCR |= RCC_APB1PERIPH_TIMER3RST; - RCC->APB1RCR &= ~RCC_APB1PERIPH_TIMER3; - } else if (TIMERx == TIMER4) { - RCC->APB1RCR |= RCC_APB1PERIPH_TIMER4RST; - RCC->APB1RCR &= ~RCC_APB1PERIPH_TIMER4; - } else if (TIMERx == TIMER5) { - RCC->APB1RCR |= RCC_APB1PERIPH_TIMER5RST; - RCC->APB1RCR &= ~RCC_APB1PERIPH_TIMER5; - } else if (TIMERx == TIMER6) { - RCC->APB1RCR |= RCC_APB1PERIPH_TIMER6RST; - RCC->APB1RCR &= ~RCC_APB1PERIPH_TIMER6; - } else if (TIMERx == TIMER7) { - RCC->APB2RCR |= RCC_APB2PERIPH_TIMER7RST; - RCC->APB2RCR &= ~RCC_APB2PERIPH_TIMER7; - } else if (TIMERx == TIMER8) { - RCC->APB2RCR |= RCC_APB2PERIPH_TIMER8RST; - RCC->APB2RCR &= ~RCC_APB2PERIPH_TIMER8; - } else if (TIMERx == TIMER9) { - RCC->APB2RCR |= RCC_APB2PERIPH_TIMER9RST; - RCC->APB2RCR &= ~RCC_APB2PERIPH_TIMER9; - } else if (TIMERx == TIMER10) { - RCC->APB2RCR |= RCC_APB2PERIPH_TIMER10RST; - RCC->APB2RCR &= ~RCC_APB2PERIPH_TIMER10; - } else if (TIMERx == TIMER11) { - RCC->APB1RCR |= RCC_APB1PERIPH_TIMER11RST; - RCC->APB1RCR &= ~RCC_APB1PERIPH_TIMER11; - } else if (TIMERx == TIMER12) { - RCC->APB1RCR |= RCC_APB1PERIPH_TIMER12RST; - RCC->APB1RCR &= ~RCC_APB1PERIPH_TIMER12; - } else if (TIMERx == TIMER13) { - RCC->APB1RCR |= RCC_APB1PERIPH_TIMER13RST; - RCC->APB1RCR &= ~RCC_APB1PERIPH_TIMER13; - } -} - -/** - * @brief Initialize the specified Timer - * @param TIMERx: x ={ 0 -13 } . - * @param TIMER_Init: pointer to a TIMER_BaseInitPara structure. - * @retval None - */ -void TIMER_BaseInit(TIMER_TypeDef *TIMERx, TIMER_BaseInitPara *TIMER_Init) -{ - uint16_t tmpctlr1 = 0; - - tmpctlr1 = TIMERx->CTLR1; - - if ((TIMERx == TIMER0) || (TIMERx == TIMER7) || (TIMERx == TIMER1) || (TIMERx == TIMER2) || - (TIMERx == TIMER3) || (TIMERx == TIMER4) || (TIMERx == TIMER8) || (TIMERx == TIMER9) - || (TIMERx == TIMER10) || (TIMERx == TIMER11) || (TIMERx == TIMER12) || (TIMERx == TIMER13)) { - /* Configure the Counter Mode */ - tmpctlr1 &= (uint16_t)(~((uint16_t)(TIMER_CTLR1_DIR | TIMER_CTLR1_CAM))); - tmpctlr1 |= (uint32_t)TIMER_Init->TIMER_CounterMode; - } - - if ((TIMERx != TIMER5) && (TIMERx != TIMER6)) { - /* Configure the clock division */ - tmpctlr1 &= (uint16_t)(~((uint16_t)TIMER_CTLR1_CDIV)); - tmpctlr1 |= (uint32_t)TIMER_Init->TIMER_ClockDivision; - } - - TIMERx->CTLR1 = tmpctlr1; - - /* Configure the Autoreload value */ - TIMERx->CARL = TIMER_Init->TIMER_Period ; - - /* Configure the Prescaler value */ - TIMERx->PSC = TIMER_Init->TIMER_Prescaler; - - if ((TIMERx == TIMER0) || - (TIMERx == TIMER7)) { - /* Configure the Repetition Counter value */ - TIMERx->CREP = TIMER_Init->TIMER_RepetitionCounter; - } - - /* Generate an update event */ - TIMERx->EVG = TIMER_PSC_RELOAD_NOW; -} - -/** - * @brief Fill each TIMER_BaseInitPara Struct member with a default value. - * @param TIMER_Init: pointer to a TIMER_BaseInitPara structure. - * @retval None - */ -void TIMER_BaseStructInit(TIMER_BaseInitPara *TIMER_Init) -{ - /* Fill the default value */ - TIMER_Init->TIMER_Period = 0xFFFFFFFF; - TIMER_Init->TIMER_Prescaler = 0x0000; - TIMER_Init->TIMER_ClockDivision = TIMER_CDIV_DIV1; - TIMER_Init->TIMER_CounterMode = TIMER_COUNTER_UP; - TIMER_Init->TIMER_RepetitionCounter = 0x0000; -} - -/** - * @brief Configure the TIMER Prescaler. - * @param TIMERx: x ={ 0-13 } - * @param Prescaler: Prescaler value - * @param TIMER_PSCReloadMode: Prescaler Reload mode - * This value will be : - * @arg TIMER_PSC_RELOAD_UPDATE : The Prescaler is loaded at the next update event. - * @arg TIMER_PSC_RELOAD_NOW : The Prescaler is loaded right now. - * @retval None - */ -void TIMER_PrescalerConfig(TIMER_TypeDef *TIMERx, uint16_t Prescaler, uint16_t TIMER_PSCReloadMode) -{ - /* Set PSC */ - TIMERx->PSC = Prescaler; - - /* Choose reload mode */ - TIMERx->EVG = TIMER_PSCReloadMode; -} - -/** - * @brief Configure the TIMER Counter Mode - * @param TIMERx: x ={ 1 , 2 , 3 , 4 , 5 , 8 , 9 , 10 , 11 , 12 , 13 , 14} . - * @param TIMER_CounterMode: the Counter Mode - * This value will be : - * @arg TIMER_COUNTER_UP : Up Counting Mode - * @arg TIMER_COUNTER_DOWN : Down Counting Mode - * @arg TIMER_COUNTER_CENTER_ALIGNED1: Center Aligned Counting Mode1 - * @arg TIMER_COUNTER_CENTER_ALIGNED2: Center Aligned Counting Mode2 - * @arg TIMER_COUNTER_CENTER_ALIGNED3: Center Aligned Counting Mode3 - * @retval None - */ -void TIMER_CounterMode(TIMER_TypeDef *TIMERx, uint16_t TIMER_CounterMode) -{ - uint16_t tmpctlr1 = 0; - - tmpctlr1 = TIMERx->CTLR1; - - /* Reset the CAM and DIR Bits */ - tmpctlr1 &= (uint16_t)(~((uint16_t)(TIMER_CTLR1_DIR | TIMER_CTLR1_CAM))); - - /* Configures the Counter Mode */ - tmpctlr1 |= TIMER_CounterMode; - - /* Update the TIMER CTLR1 */ - TIMERx->CTLR1 = tmpctlr1; -} - -/** - * @brief Configure the TIMER Counter Register value - * @param TIMERx: x ={ 0-13 } . - * @param Counter: the Counter register new value. - * @retval None - */ -void TIMER_SetCounter(TIMER_TypeDef *TIMERx, uint32_t Counter) -{ - TIMERx->CNT = Counter; -} - -/** - * @brief Configure the Autoreload value - * @param TIMERx: x ={ 0-13 } . - * @param AutoReloadValue: - * @retval None - */ -void TIMER_SetAutoreload(TIMER_TypeDef *TIMERx, uint32_t AutoReloadValue) -{ - TIMERx->CARL = AutoReloadValue; -} - -/** - * @brief Get the Counter value. - * @param TIMERx: x ={ 0-13 } . - * @retval Counter Register value. - */ -uint32_t TIMER_GetCounter(TIMER_TypeDef *TIMERx) -{ - return TIMERx->CNT; -} - -/** - * @brief Get the Prescaler value. - * @param TIMERx: x ={ 0-13 } . - * @retval Prescaler Register value - */ -uint16_t TIMER_GetPrescaler(TIMER_TypeDef *TIMERx) -{ - return TIMERx->PSC; -} - -/** - * @brief Configure the TIMERx Update event. - * @param TIMERx: x ={ 0-13 } . - * @param NewValue: new value of the TIMERx UPDIS bit - * This value will be : - * @arg ENABLE : Update Enbale - * @arg DISABLE : Update Disable - * @retval None - */ -void TIMER_UpdateDisableConfig(TIMER_TypeDef *TIMERx, TypeState NewValue) -{ - if (NewValue != DISABLE) { - TIMERx->CTLR1 |= TIMER_CTLR1_UPDIS; - } else { - TIMERx->CTLR1 &= (uint16_t)~((uint16_t)TIMER_CTLR1_UPDIS); - } -} - -/** - * @brief Configure the TIMER Update Request source. - * @param TIMERx: x ={ 0-13 } . - * @param TIMER_UpdateSrc: Configures the Update source. - * This value will be : - * @arg TIMER_UPDATE_SRC_GLOBAL : Update generate by setting of UPG bit or the counter - * overflow/underflow , or the slave mode controller trigger. - * @arg TIMER_UPDATE_SRC_REGULAR : Update generate only by counter overflow/underflow. - * @retval None - */ -void TIMER_UpdateRequestConfig(TIMER_TypeDef *TIMERx, uint16_t TIMER_UpdateSrc) -{ - if (TIMER_UpdateSrc != TIMER_UPDATE_SRC_GLOBAL) { - TIMERx->CTLR1 |= TIMER_CTLR1_UPS; - } else { - TIMERx->CTLR1 &= (uint16_t)~((uint16_t)TIMER_CTLR1_UPS); - } -} - -/** - * @brief Configure the CARL Preload function - * @param TIMERx: x ={ 0-13 } . - * @param NewValue: the state of the Preload function on CARL. - * This value will be : - * @arg ENABLE - * @arg DISABLE - * @retval None - */ -void TIMER_CARLPreloadConfig(TIMER_TypeDef *TIMERx, TypeState NewValue) -{ - if (NewValue != DISABLE) { - /* Set the CARL Preload Bit */ - TIMERx->CTLR1 |= TIMER_CTLR1_ARSE; - } else { - /* Reset the CARL Preload Bit */ - TIMERx->CTLR1 &= (uint16_t)~((uint16_t)TIMER_CTLR1_ARSE); - } -} - -/** - * @brief Select the TIMER Single Pulse Mode. - * @param TIMERx: x ={ 1 , 2 , 3 , 4 , 5 , 8 , 9 , 10 , 11 , 12 , 13 , 14} . - * @param TIMER_SPMode: specifies the SPM Mode to be used. - * This value will be : - * @arg TIMER_SP_MODE_SINGLE - * @arg TIMER_SP_MODE_REPETITIVE - * @retval None - */ -void TIMER_SinglePulseMode(TIMER_TypeDef *TIMERx, uint16_t TIMER_SPMode) -{ - /* Reset the SPM Bit */ - TIMERx->CTLR1 &= (uint16_t)~((uint16_t)TIMER_CTLR1_SPM); - - /* Set the SPM Bit */ - TIMERx->CTLR1 |= TIMER_SPMode; -} - -/** - * @brief Configure the TIMERx Clock Division value. - * @param TIMERx: x ={ 1 , 2 , 3 , 4 , 5 , 8 , 9 , 10 , 11 , 12 , 13 , 14} . - * @param TIMER_CDIV: the clock division value. - * This value will be : - * @arg TIMER_CDIV_DIV1: TDTS = Tck_tim - * @arg TIMER_CDIV_DIV2: TDTS = 2*Tck_tim - * @arg TIMER_CDIV_DIV4: TDTS = 4*Tck_tim - * @retval None - */ -void TIMER_SetClockDivision(TIMER_TypeDef *TIMERx, uint16_t TIMER_CDIV) -{ - /* Reset the CDIV value*/ - TIMERx->CTLR1 &= (uint16_t)~((uint16_t)TIMER_CTLR1_CDIV); - - /* Set the CDIV value */ - TIMERx->CTLR1 |= TIMER_CDIV; -} - -/** - * @brief ENABLE or DISABLE the TIMER. - * @param TIMERx: x ={ 0-13 } . - * @param NewValue: ENABLE or DISABLE. - * @retval None - */ -void TIMER_Enable(TIMER_TypeDef *TIMERx, TypeState NewValue) -{ - if (NewValue != DISABLE) { - /* Enable the TIMER */ - TIMERx->CTLR1 |= TIMER_CTLR1_CNTE; - } else { - /* Disable the TIMER */ - TIMERx->CTLR1 &= (uint16_t)(~((uint16_t)TIMER_CTLR1_CNTE)); - } -} - -/** - * @brief Configure the: Break feature, dead time, Lock level, ROS/IOS State and the OAE - * @param TIMERx: x ={ 1 , 8 } . - * @param TIMER_BKDTInit: pointer to a TIMER_BKDTInitPara structure that - * contains the BKDT Register configuration information for the TIMER. - * @retval None - */ -void TIMER_BKDTConfig(TIMER_TypeDef *TIMERx, TIMER_BKDTInitPara *TIMER_BKDTInit) -{ - TIMERx->BKDT = (uint32_t)TIMER_BKDTInit->TIMER_ROSState | - TIMER_BKDTInit->TIMER_IOSState | - TIMER_BKDTInit->TIMER_LOCKLevel | - TIMER_BKDTInit->TIMER_DeadTime | - TIMER_BKDTInit->TIMER_Break | - TIMER_BKDTInit->TIMER_BreakPolarity | - TIMER_BKDTInit->TIMER_OutAuto; -} - -/** - * @brief Fill TIMER_BKDTInit structure member with default value. - * @param TIMER_BKDTInit : pointer to a TIMER_BKDTInitPara structure which will be initialized. - * @retval None - */ -void TIMER_BKDTStructInit(TIMER_BKDTInitPara *TIMER_BKDTInit) -{ - TIMER_BKDTInit->TIMER_ROSState = TIMER_ROS_STATE_DISABLE; - TIMER_BKDTInit->TIMER_IOSState = TIMER_IOS_STATE_DISABLE; - TIMER_BKDTInit->TIMER_LOCKLevel = TIMER_LOCK_LEVEL_OFF; - TIMER_BKDTInit->TIMER_DeadTime = 0x00; - TIMER_BKDTInit->TIMER_Break = TIMER_BREAK_DISABLE; - TIMER_BKDTInit->TIMER_BreakPolarity = TIMER_BREAK_POLARITY_LOW; - TIMER_BKDTInit->TIMER_OutAuto = TIMER_OUTAUTO_DISABLE; -} - -/** - * @brief Enable or disable the TIMER ALL Outputs. - * @param TIMERx: x ={ 1 , 8 } . - * @param NewValue: ENABLE or DISABLE . - * @retval None - */ -void TIMER_CtrlPWMOutputs(TIMER_TypeDef *TIMERx, TypeState NewValue) -{ - if (NewValue != DISABLE) { - /* Enable the TIMER ALL Output */ - TIMERx->BKDT |= TIMER_BKDT_POE; - } else { - /* Disable the TIMER ALL Output */ - TIMERx->BKDT &= (uint16_t)(~((uint16_t)TIMER_BKDT_POE)); - } -} - -/** - * @brief Initialize the TIMERx Channel1 with TIMER_OCInitPara . - * @param TIMERx: x ={ 1 , 2 , 3 , 4 , 5 , 8 , 9 , 10 , 11 , 12 , 13 , 14} . - * @param TIMER_OCInit : pointer to a TIMER_OCInitPara structure . - * @retval None - */ -void TIMER_OC1_Init(TIMER_TypeDef *TIMERx, TIMER_OCInitPara *TIMER_OCInit) -{ - uint16_t tmpchctlrx = 0, tmpche = 0, tmpctlr2 = 0; - - /* Disable the Channel 1: Reset the CH1E Bit */ - TIMERx->CHE &= (uint16_t)(~(uint16_t)TIMER_CHE_CH1E); - - /* Get the TIMERx CHE register value */ - tmpche = TIMERx->CHE; - - /* Get the TIMERx CTLR2 register value */ - tmpctlr2 = TIMERx->CTLR2; - - /* Get the TIMERx CHCTLR1 register value */ - tmpchctlrx = TIMERx->CHCTLR1; - - /* Reset the Output Compare Mode Bits */ - tmpchctlrx &= (uint16_t)(~((uint16_t)TIMER_CHCTLR1_CH1OM)); - tmpchctlrx &= (uint16_t)(~((uint16_t)TIMER_CHCTLR1_CH1M)); - - /* Select the Output Compare Mode */ - tmpchctlrx |= TIMER_OCInit->TIMER_OCMode; - - /* Reset the Output Polarity */ - tmpche &= (uint16_t)(~((uint16_t)TIMER_CHE_CH1P)); - - /* Set the Output Compare Polarity */ - tmpche |= TIMER_OCInit->TIMER_OCPolarity; - - /* Set the Output State */ - tmpche |= TIMER_OCInit->TIMER_OutputState; - - if ((TIMERx == TIMER0) || (TIMERx == TIMER7)) { - /* Reset the Output complementary Polarity */ - tmpche &= (uint16_t)(~((uint16_t)TIMER_CHE_CH1NP)); - - /* Set the Output complementary Polarity */ - tmpche |= TIMER_OCInit->TIMER_OCNPolarity; - - /* Reset the Output complementary State */ - tmpche &= (uint16_t)(~((uint16_t)TIMER_CHE_CH1NE)); - - /* Set the Output complementary State */ - tmpche |= TIMER_OCInit->TIMER_OutputNState; - - /* Reset the Ouput Compare and Output Compare complementary IDLE State */ - tmpctlr2 &= (uint16_t)(~((uint16_t)TIMER_CTLR2_ISO1)); - tmpctlr2 &= (uint16_t)(~((uint16_t)TIMER_CTLR2_ISO1N)); - - /* Set the Output Idle state */ - tmpctlr2 |= TIMER_OCInit->TIMER_OCIdleState; - - /* Set the Output complementary Idle state */ - tmpctlr2 |= TIMER_OCInit->TIMER_OCNIdleState; - } - - /* Write to TIMERx CTLR2 */ - TIMERx->CTLR2 = tmpctlr2; - - /* Write to TIMERx CHCTLR1 */ - TIMERx->CHCTLR1 = tmpchctlrx; - - /* Set the Capture / Compare Register value */ - TIMERx->CHCC1 = TIMER_OCInit->TIMER_Pulse; - - /* Write to TIMERx CHE */ - TIMERx->CHE = tmpche; -} - -/** - * @brief Initialize the TIMERx Channel2 with TIMER_OCInitPara . - * @param TIMERx: x ={ 1 , 2 , 3 , 4 , 5 , 8 , 9 , 12 } . - * @param TIMER_OCInit : pointer to a TIMER_OCInitPara structure . - * @retval None - */ -void TIMER_OC2_Init(TIMER_TypeDef *TIMERx, TIMER_OCInitPara *TIMER_OCInit) -{ - uint16_t tmpchctlrx = 0, tmpche = 0, tmpctlr2 = 0; - - /* Disable the Channel 2: Reset the CH2E Bit */ - TIMERx->CHE &= (uint16_t)(~((uint16_t)TIMER_CHE_CH2E)); - - /* Get the TIMERx CHE register value */ - tmpche = TIMERx->CHE; - - /* Get the TIMERx CTLR2 register value */ - tmpctlr2 = TIMERx->CTLR2; - - /* Get the TIMERx CHCTLR1 register value */ - tmpchctlrx = TIMERx->CHCTLR1; - - /* Reset the Output Compare Mode Bits */ - tmpchctlrx &= (uint16_t)(~((uint16_t)TIMER_CHCTLR1_CH2OM)); - tmpchctlrx &= (uint16_t)(~((uint16_t)TIMER_CHCTLR1_CH2M)); - - /* Select the Output Compare Mode */ - tmpchctlrx |= (uint16_t)(TIMER_OCInit->TIMER_OCMode << 8); - - /* Reset the Output Polarity */ - tmpche &= (uint16_t)(~((uint16_t)TIMER_CHE_CH2P)); - - /* Set the Output Compare Polarity */ - tmpche |= (uint16_t)(TIMER_OCInit->TIMER_OCPolarity << 4); - - /* Set the Output State */ - tmpche |= (uint16_t)(TIMER_OCInit->TIMER_OutputState << 4); - - if ((TIMERx == TIMER0) || (TIMERx == TIMER7)) { - /* Reset the Output complementary Polarity */ - tmpche &= (uint16_t)(~((uint16_t)TIMER_CHE_CH2NP)); - - /* Set the Output complementary Polarity */ - tmpche |= (uint16_t)(TIMER_OCInit->TIMER_OCNPolarity << 4); - - /* Reset the Output complementary State */ - tmpche &= (uint16_t)(~((uint16_t)TIMER_CHE_CH2NE)); - - /* Set the Output complementary State */ - tmpche |= (uint16_t)(TIMER_OCInit->TIMER_OutputNState << 4); - - /* Reset the Ouput Compare and Output Compare complementary IDLE State */ - tmpctlr2 &= (uint16_t)(~((uint16_t)TIMER_CTLR2_ISO2)); - tmpctlr2 &= (uint16_t)(~((uint16_t)TIMER_CTLR2_ISO2N)); - - /* Set the Output Idle state */ - tmpctlr2 |= (uint16_t)(TIMER_OCInit->TIMER_OCIdleState << 2); - - /* Set the Output complementary Idle state */ - tmpctlr2 |= (uint16_t)(TIMER_OCInit->TIMER_OCNIdleState << 2); - } - - /* Write to TIMERx CTLR2 */ - TIMERx->CTLR2 = tmpctlr2; - - /* Write to TIMERx CHCTLR1 */ - TIMERx->CHCTLR1 = tmpchctlrx; - - /* Set the Capture / Compare Register value */ - TIMERx->CHCC2 = TIMER_OCInit->TIMER_Pulse; - - /* Write to TIMERx CHE */ - TIMERx->CHE = tmpche; -} - -/** - * @brief Initialize the TIMERx Channel3 with TIMER_OCInitPara . - * @param TIMERx: x ={ 1 , 2 , 3 , 4 , 5 , 8} . - * @param TIMER_OCInit : pointer to a TIMER_OCInitPara structure . - * @retval None - */ -void TIMER_OC3_Init(TIMER_TypeDef *TIMERx, TIMER_OCInitPara *TIMER_OCInit) -{ - uint16_t tmpchctlrx = 0, tmpche = 0, tmpctlr2 = 0; - - /* Disable the Channel 3: Reset the CH3E Bit */ - TIMERx->CHE &= (uint16_t)(~((uint16_t)TIMER_CHE_CH3E)); - - /* Get the TIMERx CHE register value */ - tmpche = TIMERx->CHE; - - /* Get the TIMERx CTLR2 register value */ - tmpctlr2 = TIMERx->CTLR2; - - /* Get the TIMERx CHCTLR2 register value */ - tmpchctlrx = TIMERx->CHCTLR2; - - /* Reset the Output Compare Mode Bits */ - tmpchctlrx &= (uint16_t)(~((uint16_t)TIMER_CHCTLR2_CH3OM)); - tmpchctlrx &= (uint16_t)(~((uint16_t)TIMER_CHCTLR2_CH3M)); - - /* Select the Output Compare Mode */ - tmpchctlrx |= TIMER_OCInit->TIMER_OCMode; - - /* Reset the Output Polarity */ - tmpche &= (uint16_t)(~((uint16_t)TIMER_CHE_CH3P)); - - /* Set the Output Compare Polarity */ - tmpche |= (uint16_t)(TIMER_OCInit->TIMER_OCPolarity << 8); - - /* Set the Output State */ - tmpche |= (uint16_t)(TIMER_OCInit->TIMER_OutputState << 8); - - if ((TIMERx == TIMER0) || (TIMERx == TIMER7)) { - /* Reset the Output complementary Polarity */ - tmpche &= (uint16_t)(~((uint16_t)TIMER_CHE_CH3NP)); - - /* Set the Output complementary Polarity */ - tmpche |= (uint16_t)(TIMER_OCInit->TIMER_OCNPolarity << 8); - - /* Reset the Output complementary State */ - tmpche &= (uint16_t)(~((uint16_t)TIMER_CHE_CH3NE)); - - /* Set the Output complementary State */ - tmpche |= (uint16_t)(TIMER_OCInit->TIMER_OutputNState << 8); - - /* Reset the Ouput Compare and Output Compare complementary IDLE State */ - tmpctlr2 &= (uint16_t)(~((uint16_t)TIMER_CTLR2_ISO3)); - tmpctlr2 &= (uint16_t)(~((uint16_t)TIMER_CTLR2_ISO3N)); - - /* Set the Output Idle state */ - tmpctlr2 |= (uint16_t)(TIMER_OCInit->TIMER_OCIdleState << 4); - - /* Set the Output complementary Idle state */ - tmpctlr2 |= (uint16_t)(TIMER_OCInit->TIMER_OCNIdleState << 4); - } - /* Write to TIMERx CTLR2 */ - TIMERx->CTLR2 = tmpctlr2; - - /* Write to TIMERx CHCTLR2 */ - TIMERx->CHCTLR2 = tmpchctlrx; - - /* Set the Capture / Compare Register value */ - TIMERx->CHCC3 = TIMER_OCInit->TIMER_Pulse; - - /* Write to TIMERx CHE */ - TIMERx->CHE = tmpche; -} - -/** - * @brief Initialize the TIMERx Channel4 with TIMER_OCInitPara . - * @param TIMERx: x ={ 1 , 2 , 3 , 4 , 5 , 8} . - * @param TIMER_OCInit : pointer to a TIMER_OCInitPara structure . - * @retval None - */ -void TIMER_OC4_Init(TIMER_TypeDef *TIMERx, TIMER_OCInitPara *TIMER_OCInit) -{ - uint16_t tmpchctlrx = 0, tmpche = 0, tmpctlr2 = 0; - - /* Disable the Channel 4: Reset the CH4E Bit */ - TIMERx->CHE &= (uint16_t)(~((uint16_t)TIMER_CHE_CH4E)); - - /* Get the TIMERx CHE register value */ - tmpche = TIMERx->CHE; - - /* Get the TIMERx CTLR2 register value */ - tmpctlr2 = TIMERx->CTLR2; - - /* Get the TIMERx CHCTLR2 register value */ - tmpchctlrx = TIMERx->CHCTLR2; - - /* Reset the Output Compare Mode Bits */ - tmpchctlrx &= (uint16_t)(~((uint16_t)TIMER_CHCTLR2_CH4OM)); - tmpchctlrx &= (uint16_t)(~((uint16_t)TIMER_CHCTLR2_CH4M)); - - /* Select the Output Compare Mode */ - tmpchctlrx |= (uint16_t)(TIMER_OCInit->TIMER_OCMode << 8); - - /* Reset the Output Polarity */ - tmpche &= (uint16_t)(~((uint16_t)TIMER_CHE_CH4P)); - - /* Set the Output Compare Polarity */ - tmpche |= (uint16_t)(TIMER_OCInit->TIMER_OCPolarity << 12); - - /* Set the Output State */ - tmpche |= (uint16_t)(TIMER_OCInit->TIMER_OutputState << 12); - - if ((TIMERx == TIMER0) || (TIMERx == TIMER7)) { - /* Reset the Ouput Compare IDLE State */ - tmpctlr2 &= (uint16_t)(~((uint16_t)TIMER_CTLR2_ISO4)); - - /* Set the Output Idle state */ - tmpctlr2 |= (uint16_t)(TIMER_OCInit->TIMER_OCIdleState << 6); - } - - /* Write to TIMERx CTLR2 */ - TIMERx->CTLR2 = tmpctlr2; - - /* Write to TIMERx CHCTLR2 */ - TIMERx->CHCTLR2 = tmpchctlrx; - - /* Set the Capture Compare Register value */ - TIMERx->CHCC4 = TIMER_OCInit->TIMER_Pulse; - - /* Write to TIMERx CHE */ - TIMERx->CHE = tmpche; -} - -/** - * @brief Fill TIMER_OCInitPara member with default value. - * @param TIMER_OCInit: pointer to a TIMER_OCInitPara structure. - * @retval None - */ -void TIMER_OCStructInit(TIMER_OCInitPara *TIMER_OCInit) -{ - TIMER_OCInit->TIMER_OCMode = TIMER_OC_MODE_TIMING; - TIMER_OCInit->TIMER_OutputState = TIMER_OUTPUT_STATE_DISABLE; - TIMER_OCInit->TIMER_OutputNState = TIMER_OUTPUTN_STATE_DISABLE; - TIMER_OCInit->TIMER_Pulse = 0x0000000; - TIMER_OCInit->TIMER_OCPolarity = TIMER_OC_POLARITY_HIGH; - TIMER_OCInit->TIMER_OCNPolarity = TIMER_OC_POLARITY_HIGH; - TIMER_OCInit->TIMER_OCIdleState = TIMER_OC_IDLE_STATE_RESET; - TIMER_OCInit->TIMER_OCNIdleState = TIMER_OCN_IDLE_STATE_RESET; -} - -/** - * @brief Configure the TIMER Output Compare Mode. - * @param TIMERx: x ={ 1 , 2 , 3 , 4 , 5 , 8 , 9 , 10 , 11 , 12 , 13 , 14} . - * @param TIMER_Ch: - * This value will be : - * @arg TIMER_CH_1 - * @arg TIMER_CH_2 - * @arg TIMER_CH_3 - * @arg TIMER_CH_4 - * @param TIMER_OCMode: the TIMER Output Compare Mode. - * This value will be : - * @arg TIMER_OC_MODE_TIMING - * @arg TIMER_OC_MODE_ACTIVE - * @arg TIMER_OC_MODE_TOGGLE - * @arg TIMER_OC_MODE_PWM1 - * @arg TIMER_OC_MODE_PWM2 - * @arg TIMER_FORCED_HIGH - * @arg TIMER_FORCED_LOW - * @retval None - */ -void TIMER_OCxModeConfig(TIMER_TypeDef *TIMERx, uint16_t TIMER_Ch, uint16_t TIMER_OCMode) -{ - uint32_t tmp = 0; - uint16_t tmp1 = 0; - - tmp = (uint32_t) TIMERx; - tmp += CHCTLR_OFFSET; - - tmp1 = CHE_CHE_SET << (uint16_t)TIMER_Ch; - - /* Disable the Channel: Reset the CHxE Bit */ - TIMERx->CHE &= (uint16_t) ~tmp1; - - if ((TIMER_Ch == TIMER_CH_1) || (TIMER_Ch == TIMER_CH_3)) { - tmp += (TIMER_Ch >> 1); - - /* Reset the CHxOM bits in the CHCTLRx register */ - *(__IO uint32_t *) tmp &= (uint32_t)~((uint32_t)TIMER_CHCTLR1_CH1OM); - - /* Configure the CHxOM bits in the CHCTLRx register */ - *(__IO uint32_t *) tmp |= TIMER_OCMode; - } else { - tmp += (uint16_t)(TIMER_Ch - (uint16_t)4) >> (uint16_t)1; - - /* Reset the CHxOM bits in the CHCTLRx register */ - *(__IO uint32_t *) tmp &= (uint32_t)~((uint32_t)TIMER_CHCTLR1_CH2OM); - - /* Configure the CHxOM bits in the CHCTLRx register */ - *(__IO uint32_t *) tmp |= (uint16_t)(TIMER_OCMode << 8); - } -} - -/** - * @brief Configure the TIMERx Capture or Compare Register value - * @param TIMERx: x ={ 1 , 2 , 3 , 4 , 5 , 8 , 9 , 10 , 11 , 12 , 13 , 14} . - * @param CompValue1: the Capture / Compare1 register new value - * @retval None - */ -void TIMER_Compare1Config(TIMER_TypeDef *TIMERx, uint32_t CompValue1) -{ - TIMERx->CHCC1 = CompValue1 ; -} - -/** - * @brief Configure the TIMERx Capture or Compare Register value - * @param TIMERx: x ={ 1 , 2 , 3 , 4 , 5 , 8 , 9 , 12 } . - * @param CompValue2: the Capture / Compare1 register new value - * @retval None - */ -void TIMER_Compare2Config(TIMER_TypeDef *TIMERx, uint32_t CompValue2) -{ - TIMERx->CHCC2 = CompValue2; -} - -/** - * @brief Configure the TIMERx Capture or Compare Register value - * @param TIMERx: x ={ 1 , 2 , 3 , 4 , 5 , 8 } . - * @param CompValue3: the Capture / Compare1 register new value - * @retval None - */ -void TIMER_Compare3Config(TIMER_TypeDef *TIMERx, uint32_t CompValue3) -{ - TIMERx->CHCC3 = CompValue3; -} - -/** - * @brief Configure the TIMERx Capture or Compare Register value - * @param TIMERx: x ={ 1 , 2 , 3 , 4 , 5 , 8 } . - * @param CompValue4: the Capture / Compare1 register new value - * @retval None - */ -void TIMER_Compare4Config(TIMER_TypeDef *TIMERx, uint32_t CompValue4) -{ - TIMERx->CHCC4 = CompValue4; -} - -/** - * @brief Force the TIMERx output level to high or low - * @param TIMERx: x ={ 1 , 2 , 3 , 4 , 5 , 8 , 9 , 10 , 11 , 12 , 13 , 14} . - * @param TIMER_Forced: forced the output level. - * This value will be : - * @arg TIMER_FORCED_HIGH: Force output high level - * @arg TIMER_FORCED_LOW : Force output low level - * @retval None - */ -void TIMER_Forced_OC1(TIMER_TypeDef *TIMERx, uint16_t TIMER_Forced) -{ - uint16_t tmpchctlr1 = 0; - - tmpchctlr1 = TIMERx->CHCTLR1; - - /* Reset the CH1OM Bits */ - tmpchctlr1 &= (uint16_t)~((uint16_t)TIMER_CHCTLR1_CH1OM); - - /* Configure The Forced output Mode */ - tmpchctlr1 |= TIMER_Forced ; - - TIMERx->CHCTLR1 = tmpchctlr1; -} - -/** - * @brief Force the TIMERx output level to high or low - * @param TIMERx: x ={ 1 , 2 , 3 , 4 , 5 , 8 , 9 , 12 } . - * @param TIMER_Forced: forced the output level. - * This value will be : - * @arg TIMER_FORCED_HIGH: Force output high level - * @arg TIMER_FORCED_LOW : Force output low level - * @retval None - */ -void TIMER_Forced_OC2(TIMER_TypeDef *TIMERx, uint16_t TIMER_Forced) -{ - uint16_t tmpchctlr1 = 0; - - tmpchctlr1 = TIMERx->CHCTLR1; - - /* Reset the CH2OM Bits */ - tmpchctlr1 &= (uint16_t)~((uint16_t)TIMER_CHCTLR1_CH2OM); - - /* Configure The Forced output Mode */ - tmpchctlr1 |= (uint16_t)(TIMER_Forced << 8); - - TIMERx->CHCTLR1 = tmpchctlr1; -} - -/** - * @brief Force the TIMERx output level to high or low - * @param TIMERx: x ={ 1 , 2 , 3 , 4 , 5 , 8 } . - * @param TIMER_Forced: forced the output level. - * This value will be : - * @arg TIMER_FORCED_HIGH: Force output high level - * @arg TIMER_FORCED_LOW : Force output low level - * @retval None - */ -void TIMER_Forced_OC3(TIMER_TypeDef *TIMERx, uint16_t TIMER_Forced) -{ - uint16_t tmpchctlr2 = 0; - - tmpchctlr2 = TIMERx->CHCTLR2; - - /* Reset the CH3OM Bits */ - tmpchctlr2 &= (uint16_t)~((uint16_t)TIMER_CHCTLR2_CH3OM); - - /* Configure The Forced output Mode */ - tmpchctlr2 |= TIMER_Forced ; - - TIMERx->CHCTLR2 = tmpchctlr2; -} - -/** - * @brief Force the TIMERx output level to high or low - * @param TIMERx: x ={ 1 , 2 , 3 , 4 , 5 , 8 } . - * @param TIMER_Forced: forced the output level. - * This value will be : - * @arg TIMER_FORCED_HIGH: Force output high level - * @arg TIMER_FORCED_LOW : Force output low level - * @retval None - */ -void TIMER_Forced_OC4(TIMER_TypeDef *TIMERx, uint16_t TIMER_Forced) -{ - uint16_t tmpchctlr2 = 0; - - tmpchctlr2 = TIMERx->CHCTLR2; - - /* Reset the CH4OM Bits */ - tmpchctlr2 &= (uint16_t)~((uint16_t)TIMER_CHCTLR2_CH4OM); - - /* Configure The Forced output Mode */ - tmpchctlr2 |= (uint16_t)(TIMER_Forced << 8); - - TIMERx->CHCTLR2 = tmpchctlr2; -} - -/** - * @brief Configure the TIMER Capture or Compare Preload Control bit - * @param TIMERx: x ={ 1 , 8 } . - * @param NewValue: ENABLE or DISABLE. - * @retval None - */ -void TIMER_CC_PreloadControl(TIMER_TypeDef *TIMERx, TypeState NewValue) -{ - if (NewValue != DISABLE) { - /* Set the CCSE Bit */ - TIMERx->CTLR2 |= TIMER_CTLR2_CCSE; - } else { - /* Reset the CCSE Bit */ - TIMERx->CTLR2 &= (uint16_t)~((uint16_t)TIMER_CTLR2_CCSE); - } -} - -/** - * @brief Configure the TIMER channel 1 Capture or Compare Preload register - * @param TIMERx: x ={ 1 , 2 , 3 , 4 , 5 , 8 , 9 , 10 , 11 , 12 , 13 , 14} . - * @param TIMER_OCPreload : state of the TIMERx Preload register - * This value will be : - * @arg TIMER_OC_PRELOAD_ENABLE - * @arg TIMER_OC_PRELOAD_DISABLE - * @retval None - */ -void TIMER_OC1_Preload(TIMER_TypeDef *TIMERx, uint16_t TIMER_OCPreload) -{ - uint16_t tmpchctlr1 = 0; - - tmpchctlr1 = TIMERx->CHCTLR1; - - /* Reset the CH1OSE Bit */ - tmpchctlr1 &= (uint16_t)~((uint16_t)TIMER_CHCTLR1_CH1OSE); - - /* Enable or Disable the Output Compare Preload */ - tmpchctlr1 |= TIMER_OCPreload; - - TIMERx->CHCTLR1 = tmpchctlr1; -} - -/** - * @brief Configure the TIMER channel 2 Capture or Compare Preload register - * @param TIMERx: x ={ 1 , 2 , 3 , 4 , 5 , 8 , 9 , 12 } . - * @param TIMER_OCPreload : state of the TIMERx Preload register - * This value will be : - * @arg TIMER_OC_PRELOAD_ENABLE - * @arg TIMER_OC_PRELOAD_DISABLE - * @retval None - */ -void TIMER_OC2_Preload(TIMER_TypeDef *TIMERx, uint16_t TIMER_OCPreload) -{ - uint16_t tmpchctlr1 = 0; - - tmpchctlr1 = TIMERx->CHCTLR1; - - /* Reset the CH2OSE Bit */ - tmpchctlr1 &= (uint16_t)~((uint16_t)TIMER_CHCTLR1_CH2OSE); - - /* Enable or Disable the Output Compare Preload */ - tmpchctlr1 |= (uint16_t)(TIMER_OCPreload << 8); - - TIMERx->CHCTLR1 = tmpchctlr1; -} - -/** - * @brief Configure the TIMER channel 3 Capture or Compare Preload register - * @param TIMERx: x ={ 1 , 2 , 3 , 4 , 5 , 8 } . - * @param TIMER_OCPreload : state of the TIMERx Preload register - * This value will be : - * @arg TIMER_OC_PRELOAD_ENABLE - * @arg TIMER_OC_PRELOAD_DISABLE - * @retval None - */ -void TIMER_OC3_Preload(TIMER_TypeDef *TIMERx, uint16_t TIMER_OCPreload) -{ - uint16_t tmpchctlr2 = 0; - - tmpchctlr2 = TIMERx->CHCTLR2; - - /* Reset the CH3OSE Bit */ - tmpchctlr2 &= (uint16_t)~((uint16_t)TIMER_CHCTLR2_CH3OSE); - - /* Enable or Disable the Output Compare Preload */ - tmpchctlr2 |= TIMER_OCPreload; - - TIMERx->CHCTLR2 = tmpchctlr2; -} - -/** - * @brief Configure the TIMER channel 4 Capture or Compare Preload register - * @param TIMERx: x ={ 1 , 2 , 3 , 4 , 5 , 8 } . - * @param TIMER_OCPreload : state of the TIMERx Preload register - * This value will be : - * @arg TIMER_OC_PRELOAD_ENABLE - * @arg TIMER_OC_PRELOAD_DISABLE - * @retval None - */ -void TIMER_OC4_Preload(TIMER_TypeDef *TIMERx, uint16_t TIMER_OCPreload) -{ - uint16_t tmpchctlr2 = 0; - - tmpchctlr2 = TIMERx->CHCTLR2; - - /* Reset the CH4OSE Bit */ - tmpchctlr2 &= (uint16_t)~((uint16_t)TIMER_CHCTLR2_CH4OSE); - - /* Enable or Disable the Output Compare Preload */ - tmpchctlr2 |= (uint16_t)(TIMER_OCPreload << 8); - - TIMERx->CHCTLR2 = tmpchctlr2; -} - -/** - * @brief Configure the TIMER channel 1 Compare output Fast mode - * @param TIMERx: x ={ 1 , 2 , 3 , 4 , 5 , 8 , 9 , 10 , 11 , 12 , 13 , 14} . - * @param TIMER_OCFast: state of the Compare Output Fast Enable Bit. - * This value will be : - * @arg TIMER_OC_FAST_ENABLE : output fast enable - * @arg TIMER_OC_FAST_DISABLE: output fast disable - * @retval None - */ -void TIMER_OC1_FastConfig(TIMER_TypeDef *TIMERx, uint16_t TIMER_OCFast) -{ - uint16_t tmpchctlr1 = 0; - - tmpchctlr1 = TIMERx->CHCTLR1; - - /* Reset the CH1OFE Bit */ - tmpchctlr1 &= (uint16_t)~((uint16_t)TIMER_CHCTLR1_CH1OFE); - - /* Enable or Disable the Output Compare Fast Bit */ - tmpchctlr1 |= TIMER_OCFast; - - TIMERx->CHCTLR1 = tmpchctlr1; -} - -/** - * @brief Configure the TIMER channel 2 Compare output Fast mode - * @param TIMERx: x ={ 1 , 2 , 3 , 4 , 5 , 8 , 9 , 12 } . - * @param TIMER_OCFast: state of the Compare Output Fast Enable Bit. - * This value will be : - * @arg TIMER_OC_FAST_ENABLE : output fast enable - * @arg TIMER_OC_FAST_DISABLE: output fast disable - * @retval None - */ -void TIMER_OC2_FastConfig(TIMER_TypeDef *TIMERx, uint16_t TIMER_OCFast) -{ - uint16_t tmpchctlr1 = 0; - - tmpchctlr1 = TIMERx->CHCTLR1; - - /* Reset the CH2OFE Bit */ - tmpchctlr1 &= (uint16_t)~((uint16_t)TIMER_CHCTLR1_CH2OFE); - - /* Enable or Disable the Output Compare Fast Bit */ - tmpchctlr1 |= (uint16_t)(TIMER_OCFast << 8); - - TIMERx->CHCTLR1 = tmpchctlr1; -} - -/** - * @brief Configure the TIMER channel 3 Compare output Fast mode - * @param TIMERx: x ={ 1 , 2 , 3 , 4 , 5 , 8 } . - * @param TIMER_OCFast: state of the Compare Output Fast Enable Bit. - * This value will be : - * @arg TIMER_OC_FAST_ENABLE : output fast enable - * @arg TIMER_OC_FAST_DISABLE: output fast disable - * @retval None - */ -void TIMER_OC3_FastConfig(TIMER_TypeDef *TIMERx, uint16_t TIMER_OCFast) -{ - uint16_t tmpchctlr2 = 0; - - tmpchctlr2 = TIMERx->CHCTLR2; - - /* Reset the CH3OFE Bit */ - tmpchctlr2 &= (uint16_t)~((uint16_t)TIMER_CHCTLR2_CH3OFE); - - /* Enable or Disable the Output Compare Fast Bit */ - tmpchctlr2 |= TIMER_OCFast; - - TIMERx->CHCTLR2 = tmpchctlr2; -} - -/** - * @brief Configure the TIMER channel 4 Compare output Fast mode - * @param TIMERx: x ={ 1 , 2 , 3 , 4 , 5 , 8 } . - * @param TIMER_OCFast: state of the Compare Output Fast Enable Bit. - * This value will be : - * @arg TIMER_OC_FAST_ENABLE : output fast enable - * @arg TIMER_OC_FAST_DISABLE: output fast disable - * @retval None - */ -void TIMER_OC4_FastConfig(TIMER_TypeDef *TIMERx, uint16_t TIMER_OCFast) -{ - uint16_t tmpchctlr2 = 0; - - tmpchctlr2 = TIMERx->CHCTLR2; - - /* Reset the CH4OFE Bit */ - tmpchctlr2 &= (uint16_t)~((uint16_t)TIMER_CHCTLR2_CH4OFE); - - /* Enable or Disable the Output Compare Fast Bit */ - tmpchctlr2 |= (uint16_t)(TIMER_OCFast << 8); - - TIMERx->CHCTLR2 = tmpchctlr2; -} - -/** - * @brief If Clear the OCREF signal on an external event - * @param TIMERx: x ={ 1 , 2 , 3 , 4 , 5 , 8 , 9 , 10 , 11 , 12 , 13 , 14} . - * @param TIMER_OCClear: new state of the Output Compare Clear Enable Bit. - * This value will be : - * @arg TIMER_OC_CLEAR_ENABLE : Output clear enable - * @arg TIMER_OC_CLEAR_DISABLE: Output clear disable - * @retval None - */ -void TIMER_OC1_RefClear(TIMER_TypeDef *TIMERx, uint16_t TIMER_OCClear) -{ - uint16_t tmpchctlr1 = 0; - - tmpchctlr1 = TIMERx->CHCTLR1; - - /* Reset the CH1OCE Bit */ - tmpchctlr1 &= (uint16_t)~((uint16_t)TIMER_CHCTLR1_CH1OCE); - - /* Enable or Disable the Output Compare Clear Bit */ - tmpchctlr1 |= TIMER_OCClear; - - TIMERx->CHCTLR1 = tmpchctlr1; -} - -/** - * @brief If Clear the OCREF signal on an external event - * @param TIMERx: x ={ 1 , 2 , 3 , 4 , 5 , 8 , 9 , 12 } . - * @param TIMER_OCClear: new state the Output Compare Clear Enable Bit. - * This value will be : - * @arg TIMER_OC_CLEAR_ENABLE : Output clear enable - * @arg TIMER_OC_CLEAR_DISABLE: Output clear disable - * @retval None - */ -void TIMER_OC2_RefClear(TIMER_TypeDef *TIMERx, uint16_t TIMER_OCClear) -{ - uint16_t tmpchctlr1 = 0; - - tmpchctlr1 = TIMERx->CHCTLR1; - - /* Reset the OC2CE Bit */ - tmpchctlr1 &= (uint16_t)~((uint16_t)TIMER_CHCTLR1_CH2OCE); - - /* Enable or Disable the Output Compare Clear Bit */ - tmpchctlr1 |= (uint16_t)(TIMER_OCClear << 8); - - TIMERx->CHCTLR1 = tmpchctlr1; -} - -/** - * @brief If Clear the OCREF signal on an external event - * @param TIMERx: x ={ 1 , 2 , 3 , 4 , 5 , 8 } . - * @param TIMER_OCClear: new state the Output Compare Clear Enable Bit. - * This value will be : - * @arg TIMER_OC_CLEAR_ENABLE : Output clear enable - * @arg TIMER_OC_CLEAR_DISABLE: Output clear disable - * @retval None - */ -void TIMER_OC3_RefClear(TIMER_TypeDef *TIMERx, uint16_t TIMER_OCClear) -{ - uint16_t tmpchctlr2 = 0; - - tmpchctlr2 = TIMERx->CHCTLR2; - - /* Reset the CH3OCE Bit */ - tmpchctlr2 &= (uint16_t)~((uint16_t)TIMER_CHCTLR2_CH3OCE); - - /* Enable or Disable the Output Compare Clear Bit */ - tmpchctlr2 |= TIMER_OCClear; - - TIMERx->CHCTLR2 = tmpchctlr2; -} - -/** - * @brief If Clear the OCREF signal on an external event - * @param TIMERx: x ={ 1 , 2 , 3 , 4 , 5 , 8 } . - * @param TIMER_OCClear: new state the Output Compare Clear Enable Bit. - * This value will be : - * @arg TIMER_OC_CLEAR_ENABLE : Output clear enable - * @arg TIMER_OC_CLEAR_DISABLE: Output clear disable - * @retval None - */ -void TIMER_OC4_RefClear(TIMER_TypeDef *TIMERx, uint16_t TIMER_OCClear) -{ - uint16_t tmpchctlr2 = 0; - - tmpchctlr2 = TIMERx->CHCTLR2; - - /* Reset the OC4CE Bit */ - tmpchctlr2 &= (uint16_t)~((uint16_t)TIMER_CHCTLR2_CH4OCE); - - /* Enable or Disable the Output Compare Clear Bit */ - tmpchctlr2 |= (uint16_t)(TIMER_OCClear << 8); - - TIMERx->CHCTLR2 = tmpchctlr2; -} - -/** - * @brief Configure the TIMERx channel 1 polarity. - * @param TIMERx: x ={ 1 , 2 , 3 , 4 , 5 , 8 , 9 , 10 , 11 , 12 , 13 , 14} . - * @param TIMER_OCPolarity : - * This value will be : - * @arg TIMER_OC_POLARITY_HIGH: active high - * @arg TIMER_OC_POLARITY_LOW : active low - * @retval None - */ -void TIMER_OC1_Polarity(TIMER_TypeDef *TIMERx, uint16_t TIMER_OCPolarity) -{ - uint16_t tmpche = 0; - - tmpche = TIMERx->CHE; - - /* Configures the CH1P Bit */ - tmpche &= (uint16_t)~((uint16_t)TIMER_CHE_CH1P); - tmpche |= TIMER_OCPolarity; - - TIMERx->CHE = tmpche; -} - -/** - * @brief Configure the TIMERx Channel 1 complementary polarity. - * @param TIMERx: x ={ 1 , 8 } . - * @param TIMER_OCNPolarity: - * This value will be : - * @arg TIMER_OCN_POLARITY_HIGH: active high - * @arg TIMER_OCN_POLARITY_LOW: active low - * @retval None - */ -void TIMER_OC1N_Polarity(TIMER_TypeDef *TIMERx, uint16_t TIMER_OCNPolarity) -{ - uint16_t tmpche = 0; - - tmpche = TIMERx->CHE; - - /* Configures the CH1NP Bit */ - tmpche &= (uint16_t)~((uint16_t)TIMER_CHE_CH1NP); - tmpche |= TIMER_OCNPolarity; - - TIMERx->CHE = tmpche; -} - -/** - * @brief Configure the TIMERx channel 2 polarity. - * @param TIMERx: x ={ 1 , 2 , 3 , 4 , 5 , 8 , 9 , 12 } . - * @param TIMER_OCPolarity : - * This value will be : - * @arg TIMER_OC_POLARITY_HIGH: active high - * @arg TIMER_OC_POLARITY_LOW : active low - * @retval None - */ -void TIMER_OC2_Polarity(TIMER_TypeDef *TIMERx, uint16_t TIMER_OCPolarity) -{ - uint16_t tmpche = 0; - - tmpche = TIMERx->CHE; - - /* Configure the CH2P Bit */ - tmpche &= (uint16_t)~((uint16_t)TIMER_CHE_CH2P); - tmpche |= (uint16_t)(TIMER_OCPolarity << 4); - - TIMERx->CHE = tmpche; -} - -/** - * @brief Configure the TIMERx Channel 2 complementary polarity. - * @param TIMERx: x ={ 1 , 8 } . - * @param TIMER_OCNPolarity: - * This value will be : - * @arg TIMER_OCN_POLARITY_HIGH: active high - * @arg TIMER_OCN_POLARITY_LOW: active low - * @retval None - */ -void TIMER_OC2N_Polarity(TIMER_TypeDef *TIMERx, uint16_t TIMER_OCNPolarity) -{ - uint16_t tmpche = 0; - - tmpche = TIMERx->CHE; - - /* Configure the CH2NP Bit */ - tmpche &= (uint16_t)~((uint16_t)TIMER_CHE_CH2NP); - tmpche |= (uint16_t)(TIMER_OCNPolarity << 4); - - TIMERx->CHE = tmpche; -} - -/** - * @brief Configure the TIMERx channel 3 polarity. - * @param TIMERx: x ={ 1 , 2 , 3 , 4 , 5 , 8 } . - * @param TIMER_OCPolarity : - * This value will be : - * @arg TIMER_OC_POLARITY_HIGH: active high - * @arg TIMER_OC_POLARITY_LOW : active low - * @retval None - */ -void TIMER_OC3_Polarity(TIMER_TypeDef *TIMERx, uint16_t TIMER_OCPolarity) -{ - uint16_t tmpche = 0; - - tmpche = TIMERx->CHE; - - /* Configure the CH3P Bit */ - tmpche &= (uint16_t)~((uint16_t)TIMER_CHE_CH3P); - tmpche |= (uint16_t)(TIMER_OCPolarity << 8); - - TIMERx->CHE = tmpche; -} - -/** - * @brief Configure the TIMERx Channel 3 complementary polarity. - * @param TIMERx: x ={ 1 , 8 } . - * @param TIMER_OCNPolarity: - * This value will be : - * @arg TIMER_OCN_POLARITY_HIGH: active high - * @arg TIMER_OCN_POLARITY_LOW : active low - * @retval None - */ -void TIMER_OC3N_Polarity(TIMER_TypeDef *TIMERx, uint16_t TIMER_OCNPolarity) -{ - uint16_t tmpche = 0; - - tmpche = TIMERx->CHE; - - /* Configure the CH3NP Bit */ - tmpche &= (uint16_t)~((uint16_t)TIMER_CHE_CH3NP); - tmpche |= (uint16_t)(TIMER_OCNPolarity << 8); - - TIMERx->CHE = tmpche; -} - -/** - * @brief Configure the TIMERx channel 4 polarity. - * @param TIMERx: x ={ 1 , 2 , 3 , 4 , 5 , 8 } . - * @param TIMER_OCPolarity : - * This value will be : - * @arg TIMER_OC_POLARITY_HIGH: active high - * @arg TIMER_OC_POLARITY_LOW : active low - * @retval None - */ -void TIMER_OC4_Polarity(TIMER_TypeDef *TIMERx, uint16_t TIMER_OCPolarity) -{ - uint16_t tmpche = 0; - - tmpche = TIMERx->CHE; - - /* Configure the CH4P Bit */ - tmpche &= (uint16_t)~((uint16_t)TIMER_CHE_CH4P); - tmpche |= (uint16_t)(TIMER_OCPolarity << 12); - - - TIMERx->CHE = tmpche; -} - -/** - * @brief Turn-on or off the Channel x Capture or Compare . - * @param TIMERx: x ={ 1 , 2 , 3 , 4 , 5 , 8 , 9 , 10 , 11 , 12 , 13 , 14} . - * @param TIMER_Ch: - * This value will be : - * @arg TIMER_CH_1: - * @arg TIMER_CH_2: - * @arg TIMER_CH_3: - * @arg TIMER_CH_4: - * @param TIMER_CCx: the TIMER Channel CCxE bit new value. - * This value will be: - * @arg TIMER_CCX_ENABLE - * @arg TIMER_CCX_DISABLE - * @retval None - */ -void TIMER_CCxCmd(TIMER_TypeDef *TIMERx, uint16_t TIMER_Ch, uint16_t TIMER_CCx) -{ - uint16_t tmp = 0; - - tmp = CHE_CHE_SET << TIMER_Ch; - - /* Reset the CCx Bit */ - TIMERx->CHE &= (uint16_t)~ tmp; - - /* Configure the CCx Bit */ - TIMERx->CHE |= (uint16_t)(TIMER_CCx << TIMER_Ch); -} - -/** - * @brief Turn-on or off the Channel x complementary Capture or Compare - * @param TIMERx: x ={ 1 , 8 } . - * @param TIMER_Ch: - * This value will be : - * @arg TIMER_CH_1: - * @arg TIMER_CH_2: - * @arg TIMER_CH_3: - * @param TIMER_CCxN: the Channel CCxN bit new value. - * This value will be: - * @arg TIMER_CCXN_ENABLE - * @arg TIMER_CCXN_DISABLE - * @retval None - */ -void TIMER_CCxNCmd(TIMER_TypeDef *TIMERx, uint16_t TIMER_Ch, uint16_t TIMER_CCxN) -{ - uint16_t tmp = 0; - - tmp = CHE_CHNE_SET << TIMER_Ch; - - /* Reset the CCxN Bit */ - TIMERx->CHE &= (uint16_t) ~tmp; - - /* Configure the CCxN Bit */ - TIMERx->CHE |= (uint16_t)(TIMER_CCxN << TIMER_Ch); -} - -/** - * @brief Select control shadow register update control. - * @param TIMERx: x ={ 1, 8 } . - * @param NewState: ENABLE or DISABLE. - * @retval None - */ -void TIMER_SelectCOM(TIMER_TypeDef *TIMERx, TypeState NewValue) -{ - - if (NewValue != DISABLE) { - /* Set the CCUC Bit */ - TIMERx->CTLR2 |= TIMER_CTLR2_CCUC; - } else { - /* Reset the CCUC Bit */ - TIMERx->CTLR2 &= (uint16_t)~((uint16_t)TIMER_CTLR2_CCUC); - } -} - -/** - * @brief Initialize the Input Capture parameters of the timer - * @param TIMERx: x ={ 1 , 2 , 3 , 4 , 5 , 8 , 9 , 10 , 11 , 12 , 13 , 14} . - * @param TIMER_ICInit: pointer to a TIMER_ICInitPara structure - * @retval None - */ -void TIMER_ICInit(TIMER_TypeDef *TIMERx, TIMER_ICInitPara *TIMER_ICInit) -{ - - if (TIMER_ICInit->TIMER_CH == TIMER_CH_1) { - TI1_Config(TIMERx, TIMER_ICInit->TIMER_ICPolarity, - TIMER_ICInit->TIMER_ICSelection, - TIMER_ICInit->TIMER_ICFilter); - - /* Set the Input Capture Prescaler value */ - TIMER_Set_IC1_Prescaler(TIMERx, TIMER_ICInit->TIMER_ICPrescaler); - } else if (TIMER_ICInit->TIMER_CH == TIMER_CH_2) { - TI2_Config(TIMERx, TIMER_ICInit->TIMER_ICPolarity, - TIMER_ICInit->TIMER_ICSelection, - TIMER_ICInit->TIMER_ICFilter); - - /* Set the Input Capture Prescaler value */ - TIMER_Set_IC2_Prescaler(TIMERx, TIMER_ICInit->TIMER_ICPrescaler); - } else if (TIMER_ICInit->TIMER_CH == TIMER_CH_3) { - TI3_Config(TIMERx, TIMER_ICInit->TIMER_ICPolarity, - TIMER_ICInit->TIMER_ICSelection, - TIMER_ICInit->TIMER_ICFilter); - - /* Set the Input Capture Prescaler value */ - TIMER_Set_IC3_Prescaler(TIMERx, TIMER_ICInit->TIMER_ICPrescaler); - } else { - TI4_Config(TIMERx, TIMER_ICInit->TIMER_ICPolarity, - TIMER_ICInit->TIMER_ICSelection, - TIMER_ICInit->TIMER_ICFilter); - - /* Set the Input Capture Prescaler value */ - TIMER_Set_IC4_Prescaler(TIMERx, TIMER_ICInit->TIMER_ICPrescaler); - } -} - -/** - * @brief Fill TIMER_ICInitPara member with default value. - * @param TIMER_ICInit : pointer to a TIMER_ICInitPara structure - * @retval None - */ -void TIMER_ICStructInit(TIMER_ICInitPara *TIMER_ICInit) -{ - TIMER_ICInit->TIMER_CH = TIMER_CH_1; - TIMER_ICInit->TIMER_ICPolarity = TIMER_IC_POLARITY_RISING; - TIMER_ICInit->TIMER_ICSelection = TIMER_IC_SELECTION_DIRECTTI; - TIMER_ICInit->TIMER_ICPrescaler = TIMER_IC_PSC_DIV1; - TIMER_ICInit->TIMER_ICFilter = 0x00; -} - -/** - * @brief Configure the TIMER PWM input Capture mode parameters - * @param TIMERx: x ={ 1 , 2 , 3 , 4 , 5 , 8 , 9 , 10 , 11 , 12 , 13 , 14} . - * @param TIMER_ICInit: pointer to a TIMER_ICInitPara structure - * @retval None - */ -void TIMER_PWMCaptureConfig(TIMER_TypeDef *TIMERx, TIMER_ICInitPara *TIMER_ICInit) -{ - uint16_t icoppositepolarity = TIMER_IC_POLARITY_RISING; - uint16_t icoppositeselection = TIMER_IC_SELECTION_DIRECTTI; - - /* Select the Opposite Input Polarity */ - if (TIMER_ICInit->TIMER_ICPolarity == TIMER_IC_POLARITY_RISING) { - icoppositepolarity = TIMER_IC_POLARITY_FALLING; - } else { - icoppositepolarity = TIMER_IC_POLARITY_RISING; - } - - /* Select the Opposite Input */ - if (TIMER_ICInit->TIMER_ICSelection == TIMER_IC_SELECTION_DIRECTTI) { - icoppositeselection = TIMER_IC_SELECTION_INDIRECTTI; - } else { - icoppositeselection = TIMER_IC_SELECTION_DIRECTTI; - } - - if (TIMER_ICInit->TIMER_CH == TIMER_CH_1) { - TI1_Config(TIMERx, TIMER_ICInit->TIMER_ICPolarity, - TIMER_ICInit->TIMER_ICSelection, - TIMER_ICInit->TIMER_ICFilter); - - TIMER_Set_IC1_Prescaler(TIMERx, TIMER_ICInit->TIMER_ICPrescaler); - - TI2_Config(TIMERx, icoppositepolarity, icoppositeselection, TIMER_ICInit->TIMER_ICFilter); - - TIMER_Set_IC2_Prescaler(TIMERx, TIMER_ICInit->TIMER_ICPrescaler); - } else { - TI2_Config(TIMERx, TIMER_ICInit->TIMER_ICPolarity, - TIMER_ICInit->TIMER_ICSelection, - TIMER_ICInit->TIMER_ICFilter); - - TIMER_Set_IC2_Prescaler(TIMERx, TIMER_ICInit->TIMER_ICPrescaler); - - TI1_Config(TIMERx, icoppositepolarity, icoppositeselection, TIMER_ICInit->TIMER_ICFilter); - - TIMER_Set_IC1_Prescaler(TIMERx, TIMER_ICInit->TIMER_ICPrescaler); - } -} - -/** - * @brief Read the TIMERx Input Capture value. - * @param TIMERx: x ={ 1 , 2 , 3 , 4 , 5 , 8 , 9 , 10 , 11 , 12 , 13 , 14} . - * @retval None - */ -uint32_t TIMER_GetCapture1(TIMER_TypeDef *TIMERx) -{ - return TIMERx->CHCC1; -} - -/** - * @brief Read the TIMERx Input Capture value. - * @param TIMERx: x ={ 1 , 2 , 3 , 4 , 5 , 8 , 9 , 12 } . - * @retval None - */ -uint32_t TIMER_GetCapture2(TIMER_TypeDef *TIMERx) -{ - return TIMERx->CHCC2; -} - -/** - * @brief Read the TIMERx Input Capture value. - * @param TIMERx: x ={ 1 , 2 , 3 , 4 , 5 , 8 } . - * @retval None - */ -uint32_t TIMER_GetCapture3(TIMER_TypeDef *TIMERx) -{ - return TIMERx->CHCC3; -} - -/** - * @brief Read the TIMERx Input Capture value. - * @param TIMERx: x ={ 1 , 2 , 3 , 4 , 5 , 8 } . - * @retval None - */ -uint32_t TIMER_GetCapture4(TIMER_TypeDef *TIMERx) -{ - return TIMERx->CHCC4; -} - -/** - * @brief Configure the TIMERx Input Capture prescaler. - * @param TIMERx: x ={ 1 , 2 , 3 , 4 , 5 , 8 , 9 , 10 , 11 , 12 , 13 , 14} . - * @param TIMER_ICPSC: the Input Capture1 prescaler value. - * This value will be : - * @arg TIMER_IC_PSC_DIV1: no prescaler - * @arg TIMER_IC_PSC_DIV2: divided by 2 - * @arg TIMER_IC_PSC_DIV4: divided by 4 - * @arg TIMER_IC_PSC_DIV8: divided by 8 - * @retval None - */ -void TIMER_Set_IC1_Prescaler(TIMER_TypeDef *TIMERx, uint16_t TIMER_ICPSC) -{ - TIMERx->CHCTLR1 &= (uint16_t)~((uint16_t)TIMER_CHCTLR1_CH1ICP); - - TIMERx->CHCTLR1 |= TIMER_ICPSC; -} - -/** - * @brief Configure the TIMERx Input Capture prescaler. - * @param TIMERx: x ={ 1 , 2 , 3 , 4 , 5 , 8 , 9 , 12 } . - * @param TIMER_ICPSC: the Input Capture1 prescaler value. - * This value will be : - * @arg TIMER_IC_PSC_DIV1: no prescaler - * @arg TIMER_IC_PSC_DIV2: divided by 2 - * @arg TIMER_IC_PSC_DIV4: divided by 4 - * @arg TIMER_IC_PSC_DIV8: divided by 8 - * @retval None - */ -void TIMER_Set_IC2_Prescaler(TIMER_TypeDef *TIMERx, uint16_t TIMER_ICPSC) -{ - TIMERx->CHCTLR1 &= (uint16_t)~((uint16_t)TIMER_CHCTLR1_CH2ICP); - - TIMERx->CHCTLR1 |= (uint16_t)(TIMER_ICPSC << 8); -} - -/** - * @brief Configure the TIMERx Input Capture prescaler. - * @param TIMERx: x ={ 1 , 2 , 3 , 4 , 5 , 8 } . - * @param TIMER_ICPSC: the Input Capture1 prescaler value. - * This value will be : - * @arg TIMER_IC_PSC_DIV1: no prescaler - * @arg TIMER_IC_PSC_DIV2: divided by 2 - * @arg TIMER_IC_PSC_DIV4: divided by 4 - * @arg TIMER_IC_PSC_DIV8: divided by 8 - * @retval None - */ -void TIMER_Set_IC3_Prescaler(TIMER_TypeDef *TIMERx, uint16_t TIMER_ICPSC) -{ - TIMERx->CHCTLR2 &= (uint16_t)~((uint16_t)TIMER_CHCTLR2_CH3ICP); - - TIMERx->CHCTLR2 |= TIMER_ICPSC; -} - -/** - * @brief Configure the TIMERx Input Capture prescaler. - * @param TIMERx: x ={ 1 , 2 , 3 , 4 , 5 , 8 } . - * @param TIMER_ICPSC: the Input Capture1 prescaler value. - * This value will be : - * @arg TIMER_IC_PSC_DIV1: no prescaler - * @arg TIMER_IC_PSC_DIV2: divided by 2 - * @arg TIMER_IC_PSC_DIV4: divided by 4 - * @arg TIMER_IC_PSC_DIV8: divided by 8 - * @retval None - */ -void TIMER_Set_IC4_Prescaler(TIMER_TypeDef *TIMERx, uint16_t TIMER_ICPSC) -{ - TIMERx->CHCTLR2 &= (uint16_t)~((uint16_t)TIMER_CHCTLR2_CH4ICP); - - TIMERx->CHCTLR2 |= (uint16_t)(TIMER_ICPSC << 8); -} - -/** - * @brief Configure interrupts Enables - * @param TIMERx: x ={ 0-13 } . - * @param TIMER_INT: the interrupts sources to Configure. - * This value will be : - * @arg TIMER_INT_UPDATE : update Interrupt - * @arg TIMER_INT_CH1 : Channel 1 Capture or Compare Interrupt - * @arg TIMER_INT_CH2 : Channel 2 Capture or Compare Interrupt - * @arg TIMER_INT_CH3 : Channel 3 Capture or Compare Interrupt - * @arg TIMER_INT_CH4 : Channel 4 Capture or Compare Interrupt - * @arg TIMER_INT_CCUG : Commutation Interrupt - * @arg TIMER_INT_TRIGGER : Trigger Interrupt - * @arg TIMER_INT_BREAK : Break Interrupt - * @param NewValue: ENABLE or DISABLE. - * @retval None - */ -void TIMER_INTConfig(TIMER_TypeDef *TIMERx, uint16_t TIMER_INT, TypeState NewValue) -{ - if (NewValue != DISABLE) { - TIMERx->DIE |= TIMER_INT; - } else { - TIMERx->DIE &= (uint16_t)~TIMER_INT; - } -} - -/** - * @brief Generate the software event - * @param TIMERx: x ={ 0-13 } . - * @param TIMER_EventSrc: - * This value will be : - * @arg TIMER_EVENT_SRC_UPDATE : update Event - * @arg TIMER_EVENT_SRC_CH1 : Channel 1 Capture or Compare Event - * @arg TIMER_EVENT_SRC_CH2 : Channel 2 Capture or Compare Event - * @arg TIMER_EVENT_SRC_CH3 : Channel 3 Capture or Compare Event - * @arg TIMER_EVENT_SRC_CH4 : Channel 4 Capture or Compare Event - * @arg TIMER_EVENT_SRC_COM : COM event - * @arg TIMER_EVENT_SRC_TRIGGER : Trigger Event - * @arg TIMER_EVENT_SRC_BREAK : Break event - * @retval None - */ -void TIMER_GenerateEvent(TIMER_TypeDef *TIMERx, uint16_t TIMER_EventSrc) -{ - TIMERx->EVG = TIMER_EventSrc; -} - -/** - * @brief Get current flag status - * @param TIMERx: x ={ 0-13 } . - * @param TIMER_FLAG: - * This value will be : - * @arg TIMER_FLAG_UPDATE : update Flag - * @arg TIMER_FLAG_CH1 : Channel 1 Capture or Compare Flag - * @arg TIMER_FLAG_CH2 : Channel 2 Capture or Compare Flag - * @arg TIMER_FLAG_CH3 : Channel 3 Capture or Compare Flag - * @arg TIMER_FLAG_CH4 : Channel 4 Capture or Compare Flag - * @arg TIMER_FLAG_COM : Commutation Flag - * @arg TIMER_FLAG_TRIGGER : Trigger Flag - * @arg TIMER_FLAG_BREAK : Break Flag - * @arg TIMER_FLAG_CH1OF : Channel 1 Capture or Compare overcapture Flag - * @arg TIMER_FLAG_CH2OF : Channel 2 Capture or Compare overcapture Flag - * @arg TIMER_FLAG_CH3OF : Channel 3 Capture or Compare overcapture Flag - * @arg TIMER_FLAG_CH4OF : Channel 4 Capture or Compare overcapture Flag - * @retval The state of TIMER_FLAG ( SET or RESET ). - */ -TypeState TIMER_GetBitState(TIMER_TypeDef *TIMERx, uint16_t TIMER_FLAG) -{ - if ((TIMERx->STR & TIMER_FLAG) != (uint16_t)RESET) { - return SET; - } else { - return RESET; - } -} - -/** - * @brief Clear the flags - * @param TIMERx: x ={ 0-13 } . - * @param TIMER_FLAG: the flag bit to clear. - * This value will be : - * @arg TIMER_FLAG_UPDATE : update Flag - * @arg TIMER_FLAG_CH1 : Channel 1 Capture or Compare Flag - * @arg TIMER_FLAG_CH2 : Channel 2 Capture or Compare Flag - * @arg TIMER_FLAG_CH3 : Channel 3 Capture or Compare Flag - * @arg TIMER_FLAG_CH4 : Channel 4 Capture or Compare Flag - * @arg TIMER_FLAG_COM : Commutation Flag - * @arg TIMER_FLAG_TRIGGER : Trigger Flag - * @arg TIMER_FLAG_BREAK : Break Flag - * @arg TIMER_FLAG_CH1OF : Channel 1 Capture or Compare overcapture Flag - * @arg TIMER_FLAG_CH2OF : Channel 2 Capture or Compare overcapture Flag - * @arg TIMER_FLAG_CH3OF : Channel 3 Capture or Compare overcapture Flag - * @arg TIMER_FLAG_CH4OF : Channel 4 Capture or Compare overcapture Flag - * @retval None - */ -void TIMER_ClearBitState(TIMER_TypeDef *TIMERx, uint16_t TIMER_FLAG) -{ - TIMERx->STR = (uint16_t)~TIMER_FLAG; -} - -/** - * @brief Get interrupt state - * @param TIMERx: x ={ 0-13 } . - * @param TIMER_INT: - * This value will be : - * @arg TIMER_INT_UPDATE: update Interrupt - * @arg TIMER_INT_CH1 : Channel 1 Capture or Compare Interrupt - * @arg TIMER_INT_CH2 : Channel 2 Capture or Compare Interrupt - * @arg TIMER_INT_CH3 : Channel 3 Capture or Compare Interrupt - * @arg TIMER_INT_CH4 : Channel 4 Capture or Compare Interrupt - * @arg TIMER_INT_CCUG : Commutation Interrupt - * @arg TIMER_INT_TRIGGER : Trigger Interrupt - * @arg TIMER_INT_BREAK : Break Interrupt - * @retval The new state of the TIMER_INT(SET or RESET). - */ -TypeState TIMER_GetIntBitState(TIMER_TypeDef *TIMERx, uint16_t TIMER_INT) -{ - uint16_t TypeState = 0x0, itenable = 0x0; - - TypeState = TIMERx->STR & TIMER_INT; - itenable = TIMERx->DIE & TIMER_INT; - - if ((TypeState != (uint16_t)RESET) && (itenable != (uint16_t)RESET)) { - return SET; - } else { - return RESET; - } -} - -/** - * @brief Clear the interrupt pending bits - * @param TIMERx: x ={ 0-13 } . - * @param TIMER_INT: - * This value will be : - * @arg TIMER_INT_UPDATE: update Interrupt - * @arg TIMER_INT_CH1 : Channel 1 Capture or Compare Interrupt - * @arg TIMER_INT_CH2 : Channel 2 Capture or Compare Interrupt - * @arg TIMER_INT_CH3 : Channel 3 Capture or Compare Interrupt - * @arg TIMER_INT_CH4 : Channel 4 Capture or Compare Interrupt - * @arg TIMER_INT_CCUG : Commutation Interrupt - * @arg TIMER_INT_TRIGGER : Trigger Interrupt - * @arg TIMER_INT_BREAK : Break Interrupt - * @retval None - */ -void TIMER_ClearIntBitState(TIMER_TypeDef *TIMERx, uint16_t TIMER_INT) -{ - TIMERx->STR = (uint16_t)~TIMER_INT; -} - -/** - * @brief Configure the DMA . - * @param TIMERx: x ={ 1 , 2 , 3 , 4 , 5 , 8 } . - * @param TIMER_DMABase: DMA Base address. - * This value will be : - * @arg TIMER_DMA_BASE_ADDR_CTLR1 - * @arg TIMER_DMA_BASE_ADDR_CTLR2 - * @arg TIMER_DMA_BASE_ADDR_SMC - * @arg TIMER_DMA_BASE_ADDR_DIE - * @arg TIMER_DMA_BASE_ADDR_STR - * @arg TIMER_DMA_BASE_ADDR_EVG - * @arg TIMER_DMA_BASE_ADDR_CHCTLR1 - * @arg TIMER_DMA_BASE_ADDR_CHCTLR2 - * @arg TIMER_DMA_BASE_ADDR_CHE - * @arg TIMER_DMA_BASE_ADDR_CNT - * @arg TIMER_DMA_BASE_ADDR_PSC - * @arg TIMER_DMA_BASE_ADDR_CARL - * @arg TIMER_DMA_BASE_ADDR_CREP - * @arg TIMER_DMA_BASE_ADDR_CHCC1 - * @arg TIMER_DMA_BASE_ADDR_CHCC2 - * @arg TIMER_DMA_BASE_ADDR_CHCC3 - * @arg TIMER_DMA_BASE_ADDR_CHCC4 - * @arg TIMER_DMA_BASE_ADDR_BKDT - * @arg TIMER_DMA_BASE_ADDR_DCTLR - * @arg TIMER_DMA_BASE_ADDR_DTRSF - * @param TIMER_DMABurstLength: DMA Burst length. - * This value will be : - * [ TIMER_DMA_BURST_1TRANSFER , TIMER_DMA_BURST_18TRANSFERS ] - * @retval None - */ -void TIMER_DMAConfig(TIMER_TypeDef *TIMERx, uint16_t TIMER_DMABase, uint16_t TIMER_DMABurstLength) -{ - TIMERx->DCTLR = TIMER_DMABase | TIMER_DMABurstLength; -} - -/** - * @brief Configure the TIMERx's DMA Requests - * @param TIMERx: x ={ 1 , 2 , 3 , 4 , 5 , 6 , 7 , 8 } . - * @param TIMER_DMASrc: the DMA Request sources. - * This value will be : - * @arg TIMER_DMA_UPDATE : update start DMA - * @arg TIMER_DMA_CH1 : Channel 1 Capture or Compare start DMA - * @arg TIMER_DMA_CH2 : Channel 2 Capture or Compare start DMA - * @arg TIMER_DMA_CH3 : Channel 3 Capture or Compare start DMA - * @arg TIMER_DMA_CH4 : Channel 4 Capture or Compare start DMA - * @arg TIMER_DMA_COM : Commutation DMA - * @arg TIMER_DMA_TRIGGER : Trigger DMA - * @param NewValue: ENABLE or DISABLE. - * @retval None - */ -void TIMER_DMACmd(TIMER_TypeDef *TIMERx, uint16_t TIMER_DMASrc, TypeState NewValue) -{ - if (NewValue != DISABLE) { - /* Enable the DMA */ - TIMERx->DIE |= TIMER_DMASrc; - } else { - /* Disable the DMA */ - TIMERx->DIE &= (uint16_t)~TIMER_DMASrc; - } -} - -/** - * @brief Select the Capture or Compare DMA source - * @param TIMERx: x ={ 1 , 2 , 3 , 4 , 5 , 8 } . - * @param NewValue: ENABLE or DISABLE - * @retval None - */ -void TIMER_CC_DMA(TIMER_TypeDef *TIMERx, TypeState NewValue) -{ - if (NewValue != DISABLE) { - TIMERx->CTLR2 |= TIMER_CTLR2_DMAS; - } else { - TIMERx->CTLR2 &= (uint16_t)~((uint16_t)TIMER_CTLR2_DMAS); - } -} - -/** - * @brief Configure the internal Clock - * @param TIMERx: x ={ 1 , 2 , 3 , 4 , 5 , 8 , 9 , 12 } - * @retval None - */ -void TIMER_InternalClockConfig(TIMER_TypeDef *TIMERx) -{ - TIMERx->SMC &= (uint16_t)(~((uint16_t)TIMER_SMC_SMC)); -} - -/** - * @brief Configure the Internal Trigger as External Input Clock - * @param TIMERx: x ={ 1 , 2 , 3 , 4 , 5 , 8 , 9 , 12 } . - * @param TIMER_InputTriSrc: - * This value will be : - * @arg TIMER_TS_ITR0 : Internal Trigger 0 - * @arg TIMER_TS_ITR1 : Internal Trigger 1 - * @arg TIMER_TS_ITR2 : Internal Trigger 2 - * @arg TIMER_TS_ITR3 : Internal Trigger 3 - * @retval None - */ -void TIMER_ITRxExtClock(TIMER_TypeDef *TIMERx, uint16_t TIMER_InputTriSrc) -{ - /* Select the Internal Trigger */ - TIMER_SelectInputTrigger(TIMERx, TIMER_InputTriSrc); - - /* Select the External clock mode1 */ - TIMERx->SMC |= TIMER_SLAVE_MODE_EXTERNAL1; -} - -/** - * @brief Configure the External Trigger as External Input Clock - * @param TIMERx: x ={ 1 , 2 , 3 , 4 , 5 , 8 , 9 , 12 } . - * @param TIMER_TIxExCLKSrc: Trigger source. - * This value will be : - * @arg TIMER_TIX_EXCLK1_SRC_TI1ED : TI1 Edge Detector - * @arg TIMER_TIX_EXCLK1_SRC_TI1 : Filtered Timer Input 1 - * @arg TIMER_TIX_EXCLK1_SRC_TI2 : Filtered Timer Input 2 - * @param TIMER_ICPolarity: - * This value will be : - * @arg TIMER_IC_POLARITY_RISING - * @arg TIMER_IC_POLARITY_FALLING - * @param ICFilter: specifies the filter value. - * This parameter must be a value between 0x0 and 0xF. - * @retval None - */ -void TIMER_TIxExtCLkConfig(TIMER_TypeDef *TIMERx, uint16_t TIMER_TIxExCLKSrc, - uint16_t TIMER_ICPolarity, uint16_t ICFilter) -{ - /* Select the Input Clock Source */ - if (TIMER_TIxExCLKSrc == TIMER_TIX_EXCLK1_SRC_TI2) { - TI2_Config(TIMERx, TIMER_ICPolarity, TIMER_IC_SELECTION_DIRECTTI, ICFilter); - } else { - TI1_Config(TIMERx, TIMER_ICPolarity, TIMER_IC_SELECTION_DIRECTTI, ICFilter); - } - - /* Select the Trigger source */ - TIMER_SelectInputTrigger(TIMERx, TIMER_TIxExCLKSrc); - - /* Enter the External clock mode1 */ - TIMERx->SMC |= TIMER_SLAVE_MODE_EXTERNAL1; -} - -/** - * @brief Configure the External clock Mode1 - * @param TIMERx: x ={ 1 , 2 , 3 , 4 , 5 , 8 } . - * @param TIMER_ExtTriPrescaler: The external Trigger Prescaler. - * This value will be : - * @arg TIMER_EXT_TRI_PSC_OFF: no divided. - * @arg TIMER_EXT_TRI_PSC_DIV2: divided by 2. - * @arg TIMER_EXT_TRI_PSC_DIV4: divided by 4. - * @arg TIMER_EXT_TRI_PSC_DIV8: divided by 8. - * @param TIMER_ExtTriPolarity: Trigger Polarity. - * This value will be : - * @arg TIMER_EXT_TRI_POLARITY_INVERTED : active low or falling edge active. - * @arg TIMER_EXT_TRI_POLARITY_NONINVERTED: active high or rising edge active. - * @param ExtTriFilter: External Trigger Filter. - * This parameter must be a value between 0x00 and 0x0F - * @retval None - */ -void TIMER_ETRClockMode1Config(TIMER_TypeDef *TIMERx, uint16_t TIMER_ExTriPrescaler, uint16_t TIMER_ExTriPolarity, - uint16_t ExtTriFilter) -{ - uint16_t tmpsmc = 0; - - /* Configure the external Trigger Clock source */ - TIMER_ETRConfig(TIMERx, TIMER_ExTriPrescaler, TIMER_ExTriPolarity, ExtTriFilter); - - /* Get the TIMERx SMC register value */ - tmpsmc = TIMERx->SMC; - - tmpsmc &= (uint16_t)(~((uint16_t)TIMER_SMC_SMC)); - - /* Select the External clock mode1 */ - tmpsmc |= TIMER_SLAVE_MODE_EXTERNAL1; - - /* Select the Trigger selection : ETRF */ - tmpsmc &= (uint16_t)(~((uint16_t)TIMER_SMC_TRGS)); - tmpsmc |= TIMER_TS_ETRF; - - TIMERx->SMC = tmpsmc; -} - -/** - * @brief Configure the External clock Mode2 - * @param TIMERx: x ={ 1 , 2 , 3 , 4 , 5 , 8 } . - * @param TIMER_ExtTriPrescaler: The external Trigger Prescaler. - * This value will be : - * @arg TIMER_EXT_TRI_PSC_OFF: no divided. - * @arg TIMER_EXT_TRI_PSC_DIV2: divided by 2. - * @arg TIMER_EXT_TRI_PSC_DIV4: divided by 4. - * @arg TIMER_EXT_TRI_PSC_DIV8: divided by 8. - * @param TIMER_ExtTriPolarity: Trigger Polarity. - * This value will be : - * @arg TIMER_EXT_TRI_POLARITY_INVERTED : active low or falling edge active. - * @arg TIMER_EXT_TRI_POLARITY_NONINVERTED: active high or rising edge active. - * @param ExtTriFilter: External Trigger Filter. - * This parameter must be a value between 0x00 and 0x0F - * @retval None - */ -void TIMER_ETRClockMode2Config(TIMER_TypeDef *TIMERx, uint16_t TIMER_ExTriPrescaler, - uint16_t TIMER_ExTriPolarity, uint16_t ExtTriFilter) -{ - /* Configure the ETR Clock source */ - TIMER_ETRConfig(TIMERx, TIMER_ExTriPrescaler, TIMER_ExTriPolarity, ExtTriFilter); - - /* Select the External clock mode2 */ - TIMERx->SMC |= TIMER_SMC_ECM2E; -} - -/** - * @brief Select the Input Trigger source - * @param TIMERx: x ={ 1 , 2 , 3 , 4 , 5 , 8 , 9 , 12 } . - * @param TIMER_InputTriSrc: The Input Trigger source. - * This value will be : - * @arg TIMER_TS_ITR0 : Internal Trigger 0 - * @arg TIMER_TS_ITR1 : Internal Trigger 1 - * @arg TIMER_TS_ITR2 : Internal Trigger 2 - * @arg TIMER_TS_ITR3 : Internal Trigger 3 - * @arg TIMER_TS_TI1F_ED : TI1 Edge Detector - * @arg TIMER_TS_TI1FP1 : Filtered Timer Input 1 - * @arg TIMER_TS_TI2FP2 : Filtered Timer Input 2 - * @arg TIMER_TS_ETRF : External Trigger input - * @retval None - */ -void TIMER_SelectInputTrigger(TIMER_TypeDef *TIMERx, uint16_t TIMER_InputTriSrc) -{ - uint16_t tmpsmc = 0; - - tmpsmc = TIMERx->SMC; - - /* Reset the TS Bits */ - tmpsmc &= (uint16_t)(~((uint16_t)TIMER_SMC_TRGS)); - - /* Set the Input Trigger source */ - tmpsmc |= TIMER_InputTriSrc ; - - TIMERx->SMC = tmpsmc; -} - -/** - * @brief Configure the TIMERx Trigger Output Mode. - * @param TIMERx: x ={ 1 , 2 , 3 , 4 , 5 , 6 , 7 , 8 ,10 , 11 , 13 , 14} . - * @param TIMER_TriOutSrc: - * This value will be : - * @arg TIMER_TRI_OUT_SRC_RESET : The UPG bit in the TIMERx_EVG register as TriO. - * @arg TIMER_TRI_OUT_SRC_ENABLE : The CEN bit in TIMERx_CTLR1 as TriO. - * @arg TIMER_TRI_OUT_SRC_UPDATE : Update event as TriO. - * @arg TIMER_TRI_OUT_SRC_OC1 : capture or compare match ( CC1IF bit set ) as TriO. - * @arg TIMER_TRI_OUT_SRC_OC1REF : OC1REF as TriO. - * @arg TIMER_TRI_OUT_SRC_OC2REF : OC2REF as TriO. - * @arg TIMER_TRI_OUT_SRC_OC3REF : OC3REF as TriO. - * @arg TIMER_TRI_OUT_SRC_OC4REF : OC4REF as TriO. - * @retval None - */ -void TIMER_SelectOutputTrigger(TIMER_TypeDef *TIMERx, uint16_t TIMER_TriOutSrc) -{ - /* Reset the MMC Bits */ - TIMERx->CTLR2 &= (uint16_t)~((uint16_t)TIMER_CTLR2_MMC); - - /* Configures the TriO source */ - TIMERx->CTLR2 |= TIMER_TriOutSrc; -} - -/** - * @brief Configure the TIMERx Slave Mode - * @param TIMERx: x ={ 1 , 2 , 3 , 4 , 5 , 8 , 9 , 12 } . - * @param TIMER_SlaveMode: - * This value will be : - * @arg TIMER_SLAVE_MODE_RESET : The trigger signal reset the timer - * @arg TIMER_SLAVE_MODE_GATED : The trigger signal enable the counter when high. - * @arg TIMER_SLAVE_MODE_TRIGGER : The trigger signal starts the counter. - * @arg TIMER_SLAVE_MODE_EXTERNAL1 : The trigger signal as a counter clock. - * @retval None - */ -void TIMER_SelectSlaveMode(TIMER_TypeDef *TIMERx, uint16_t TIMER_SlaveMode) -{ - /* Reset the SMC Bits */ - TIMERx->SMC &= (uint16_t)~((uint16_t)TIMER_SMC_SMC); - - /* Configure the Slave Mode */ - TIMERx->SMC |= TIMER_SlaveMode; -} - -/** - * @brief Configure the TIMERx Master or Slave Mode - * @param TIMERx: x ={ 1 , 2 , 3 , 4 , 5 , 8 , 10 , 11 , 13 , 14} . - * @param TIMER_MasterSlaveMode: - * This value will be : - * @arg TIMER_MASTER_SLAVE_MODE_ENABLE : synchronize master and slave by TriO - * @arg TIMER_MASTER_SLAVE_MODE_DISABLE : Don't synchronize - * @retval None - */ -void TIMER_SelectMasterSlaveMode(TIMER_TypeDef *TIMERx, uint16_t TIMER_MasterSlaveMode) -{ - /* Reset the MSM Bit */ - TIMERx->SMC &= (uint16_t)~((uint16_t)TIMER_SMC_MSM); - - /* Configure the MSM Bit */ - TIMERx->SMC |= TIMER_MasterSlaveMode; -} - -/** - * @brief Configure the External Trigger (ETR) - * @param TIMERx: x ={ 1 , 2 , 3 , 4 , 5 , 8 } . - * @param TIMER_ExTriPrescaler: external Trigger Prescaler. - * This value will be : - * @arg TIMER_EXT_TRI_PSC_OFF : no divided. - * @arg TIMER_EXT_TRI_PSC_DIV2: divided by 2. - * @arg TIMER_EXT_TRI_PSC_DIV4: divided by 4. - * @arg TIMER_EXT_TRI_PSC_DIV8: divided by 8. - * @param TIMER_ExtTriPolarity: Trigger Polarity. - * This value will be : - * @arg TIMER_EXT_TRI_POLARITY_INVERTED : active low or falling edge active. - * @arg TIMER_EXT_TRI_POLARITY_NONINVERTED: active high or rising edge active. - * @param ExtTRGFilter: The External Trigger signal Filter. - * This parameter must be a value between 0x00 and 0x0F - * @retval None - */ -void TIMER_ETRConfig(TIMER_TypeDef *TIMERx, uint16_t TIMER_ExTriPrescaler, uint16_t TIMER_ExTriPolarity, - uint16_t ExtTriFilter) -{ - uint16_t tmpsmc = 0; - - tmpsmc = TIMERx->SMC; - - /*Reset the ETR Bits */ - tmpsmc &= SMC_ETR_MASK; - - /* Configure the Prescaler, the Filter value and the Polarity */ - tmpsmc |= (uint16_t)(TIMER_ExTriPrescaler | (uint16_t)(TIMER_ExTriPolarity | (uint16_t)(ExtTriFilter << (uint16_t)8))); - - TIMERx->SMC = tmpsmc; -} - -/** - * @brief Configure the Encoder Interface. - * @param TIMERx: x ={ 1 , 8 , 9 , 12 } . - * @param TIMER_EncoderMode: - * This value will be : - * @arg TIMER_ENCODER_MODE_TI1 : Counter counts on TI1FP1 edge depending on TI2FP2 level. - * @arg TIMER_ENCODER_MODE_TI2 : Counter counts on TI2FP2 edge depending on TI1FP1 level. - * @arg TIMER_ENCODER_MODE_TI12 : Counter counts on both TI1FP1 and TI2FP2 edges depending - * on the level of the other input. - * @param TIMER_IC1Polarity: input capture 1 Polarity - * This value will be : - * @arg TIMER_IC_POLARITY_FALLING : capture Falling edge. - * @arg TIMER_IC_POLARITY_RISING : capture Rising edge. - * @param TIMER_IC2Polarity: input capture 2 Polarity - * This value will be : - * @arg TIMER_IC_POLARITY_FALLING : capture Falling edge. - * @arg TIMER_IC_POLARITY_RISING : capture Rising edge. - * @retval None - */ -void TIMER_EncoderInterfaceConfig(TIMER_TypeDef *TIMERx, uint16_t TIMER_EncoderMode, - uint16_t TIMER_IC1Polarity, uint16_t TIMER_IC2Polarity) -{ - uint16_t tmpsmc = 0; - uint16_t tmpchctlr1 = 0; - uint16_t tmpche = 0; - - tmpsmc = TIMERx->SMC; - - tmpchctlr1 = TIMERx->CHCTLR1; - - tmpche = TIMERx->CHE; - - /* select the encoder Mode */ - tmpsmc &= (uint16_t)(~((uint16_t)TIMER_SMC_SMC)); - tmpsmc |= TIMER_EncoderMode; - - tmpchctlr1 &= (uint16_t)(((uint16_t)~((uint16_t)TIMER_CHCTLR1_CH1M)) & (uint16_t)(~((uint16_t)TIMER_CHCTLR1_CH2M))); - tmpchctlr1 |= TIMER_CHCTLR1_CH1M_0 | TIMER_CHCTLR1_CH2M_0; - - /* select the TI1 and the TI2 Polarities*/ - tmpche &= (uint16_t)~((uint16_t)(TIMER_CHE_CH1P | TIMER_CHE_CH1NP)) & (uint16_t)~((uint16_t)(TIMER_CHE_CH2P | TIMER_CHE_CH2NP)); - tmpche |= (uint16_t)(TIMER_IC1Polarity | (uint16_t)(TIMER_IC2Polarity << (uint16_t)4)); - - TIMERx->SMC = tmpsmc; - - TIMERx->CHCTLR1 = tmpchctlr1; - - TIMERx->CHE = tmpche; -} - -/** - * @brief Configure the Hall sensor interface - * @param TIMERx: x ={ 1 , 8 } . - * @param NewValue: ENABLE or DISABLE. - * @retval None - */ -void TIMER_SelectHallSensor(TIMER_TypeDef *TIMERx, TypeState NewValue) -{ - if (NewValue != DISABLE) { - TIMERx->CTLR2 |= TIMER_CTLR2_TI1S; - } else { - TIMERx->CTLR2 &= (uint16_t)~((uint16_t)TIMER_CTLR2_TI1S); - } -} - -/* Private functions */ -/** - * @brief Configure the TI1 as Capture Input. - * @param TIMERx: x ={ 1 , 2 , 3 , 4 , 5 , 8 , 9 , 10 , 11 , 12 , 13 , 14} . - * @param TIMER_ICPolarity: Input Capture Polarity. - * This value will be : - * @arg TIMER_IC_POLARITY_RISING : Capture rising edge - * @arg TIMER_IC_POLARITY_FALLING : Capture falling edge - * @param TIMER_ICSelection: Input Capture source. - * This value will be : - * @arg TIMER_IC_SELECTION_DIRECTTI : connected to IC1. - * @arg TIMER_IC_SELECTION_INDIRECTTI : connected to IC2. - * @arg TIMER_IC_SELECTION_TRC : connected to TRC. - * @param TIMER_ICFilter: Input Capture Filter. - * This parameter must be a value between 0x00 and 0x0F. - * @retval None - */ -static void TI1_Config(TIMER_TypeDef *TIMERx, uint16_t TIMER_ICPolarity, uint16_t TIMER_ICSelection, - uint16_t TIMER_ICFilter) -{ - uint16_t tmpchctlr1 = 0, tmpche = 0; - - /* Disable the Channel 1 */ - TIMERx->CHE &= (uint16_t)~((uint16_t)TIMER_CHE_CH1E); - tmpchctlr1 = TIMERx->CHCTLR1; - tmpche = TIMERx->CHE; - - /* Select the Input and Configure the filter */ - tmpchctlr1 &= (uint16_t)(((uint16_t)~((uint16_t)TIMER_CHCTLR1_CH1M)) & ((uint16_t)~((uint16_t)TIMER_CHCTLR1_CH1ICF))); - tmpchctlr1 |= (uint16_t)(TIMER_ICSelection | (uint16_t)(TIMER_ICFilter << (uint16_t)4)); - - /* Configure the Polarity and channel enable Bit */ - tmpche &= (uint16_t)~((uint16_t)(TIMER_CHE_CH1P | TIMER_CHE_CH1NP)); - tmpche |= (uint16_t)(TIMER_ICPolarity | (uint16_t)TIMER_CHE_CH1E); - - TIMERx->CHCTLR1 = tmpchctlr1; - TIMERx->CHE = tmpche; -} - -/** - * @brief Configure the TI2 as Capture Input. - * @note None - * @param TIMERx: x ={ 1 , 2 , 3 , 4 , 5 , 8 , 9 , 12 } . - * @param TIMER_ICPolarity: Input Capture Polarity. - * This value will be : - * @arg TIMER_IC_POLARITY_RISING : Capture rising edge - * @arg TIMER_IC_POLARITY_FALLING : Capture falling edge - * @param TIMER_ICSelection: Input Capture source. - * This value will be : - * @arg TIMER_IC_SELECTION_DIRECTTI : connected to IC2. - * @arg TIMER_IC_SELECTION_INDIRECTTI : connected to IC1. - * @arg TIMER_IC_SELECTION_TRC : connected to TRC. - * @param TIMER_ICFilter: Input Capture Filter. - * This parameter must be a value between 0x00 and 0x0F. - * @retval None - */ -static void TI2_Config(TIMER_TypeDef *TIMERx, uint16_t TIMER_ICPolarity, uint16_t TIMER_ICSelection, - uint16_t TIMER_ICFilter) -{ - uint16_t tmpchctlr1 = 0, tmpche = 0, tmp = 0; - - /* Disable the Channel 2 */ - TIMERx->CHE &= (uint16_t)~((uint16_t)TIMER_CHE_CH2E); - tmpchctlr1 = TIMERx->CHCTLR1; - tmpche = TIMERx->CHE; - tmp = (uint16_t)(TIMER_ICPolarity << 4); - - /* Select the Input and Configure the filter */ - tmpchctlr1 &= (uint16_t)(((uint16_t)~((uint16_t)TIMER_CHCTLR1_CH2M)) & ((uint16_t)~((uint16_t)TIMER_CHCTLR1_CH2ICF))); - tmpchctlr1 |= (uint16_t)(TIMER_ICFilter << 12); - tmpchctlr1 |= (uint16_t)(TIMER_ICSelection << 8); - - /* Configure the Polarity and channel enable Bit */ - tmpche &= (uint16_t)~((uint16_t)(TIMER_CHE_CH2P | TIMER_CHE_CH2NP)); - tmpche |= (uint16_t)(tmp | (uint16_t)TIMER_CHE_CH2E); - - TIMERx->CHCTLR1 = tmpchctlr1 ; - TIMERx->CHE = tmpche; -} - -/** - * @brief Configure the TI3 as Capture Input - * @note None - * @param TIMERx: x ={ 1 , 2 , 3 , 4 , 5 , 8 } . - * @param TIMER_ICPolarity: Input Capture Polarity. - * This value will be : - * @arg TIMER_IC_POLARITY_RISING : Capture rising edge - * @arg TIMER_IC_POLARITY_FALLING : Capture falling edge - * @param TIMER_ICSelection: Input Capture source. - * This value will be : - * @arg TIMER_IC_SELECTION_DIRECTTI : connected to IC3. - * @arg TIMER_IC_SELECTION_INDIRECTTI : connected to IC4. - * @arg TIMER_IC_SELECTION_TRC : connected to TRC. - * @param TIMER_ICFilter: Input Capture Filter. - * This parameter must be a value between 0x00 and 0x0F. - * @retval None - */ -static void TI3_Config(TIMER_TypeDef *TIMERx, uint16_t TIMER_ICPolarity, uint16_t TIMER_ICSelection, - uint16_t TIMER_ICFilter) -{ - uint16_t tmpchctlr2 = 0, tmpche = 0, tmp = 0; - - /* Disable the Channel 3 */ - TIMERx->CHE &= (uint16_t)~((uint16_t)TIMER_CHE_CH3E); - tmpchctlr2 = TIMERx->CHCTLR2; - tmpche = TIMERx->CHE; - tmp = (uint16_t)(TIMER_ICPolarity << 8); - - /* Select the Input and Configure the filter */ - tmpchctlr2 &= (uint16_t)(((uint16_t)~((uint16_t)TIMER_CHCTLR2_CH3M)) & ((uint16_t)~((uint16_t)TIMER_CHCTLR2_CH3ICF))); - tmpchctlr2 |= (uint16_t)(TIMER_ICSelection | (uint16_t)(TIMER_ICFilter << (uint16_t)4)); - - /* Configure the Polarity and channel enable Bit */ - tmpche &= (uint16_t)~((uint16_t)(TIMER_CHE_CH3P | TIMER_CHE_CH3NP)); - tmpche |= (uint16_t)(tmp | (uint16_t)TIMER_CHE_CH3E); - - TIMERx->CHCTLR2 = tmpchctlr2; - TIMERx->CHE = tmpche; -} - -/** - * @brief Configure the TI4 as Capture Input - * @param TIMERx: x ={ 1 , 2 , 3 , 4 , 5 , 8 } . - * @param TIMER_ICPolarity: Input Capture Polarity. - * This value will be : - * @arg TIMER_IC_POLARITY_RISING : Capture rising edge - * @arg TIMER_IC_POLARITY_FALLING : Capture falling edge - * @param TIMER_ICSelection: Input Capture source. - * This value will be : - * @arg TIMER_IC_SELECTION_DIRECTTI : connected to IC4. - * @arg TIMER_IC_SELECTION_INDIRECTTI : connected to IC3. - * @arg TIMER_IC_SELECTION_TRC : connected to TRC. - * @param TIMER_ICFilter: Input Capture Filter. - * This parameter must be a value between 0x00 and 0x0F. - * @retval None - */ -static void TI4_Config(TIMER_TypeDef *TIMERx, uint16_t TIMER_ICPolarity, uint16_t TIMER_ICSelection, - uint16_t TIMER_ICFilter) -{ - uint16_t tmpchctlr2 = 0, tmpche = 0, tmp = 0; - - /* Disable the Channel 4 */ - TIMERx->CHE &= (uint16_t)~((uint16_t)TIMER_CHE_CH4E); - tmpchctlr2 = TIMERx->CHCTLR2; - tmpche = TIMERx->CHE; - tmp = (uint16_t)(TIMER_ICPolarity << 12); - - /* Select the Input and Configure the filter */ - tmpchctlr2 &= (uint16_t)((uint16_t)(~(uint16_t)TIMER_CHCTLR2_CH4M) & ((uint16_t)~((uint16_t)TIMER_CHCTLR2_CH4ICF))); - tmpchctlr2 |= (uint16_t)(TIMER_ICSelection << 8); - tmpchctlr2 |= (uint16_t)(TIMER_ICFilter << 12); - - /* Configure the Polarity and channel enable Bit */ - tmpche &= (uint16_t)~((uint16_t)(TIMER_CHE_CH4P | TIMER_CHE_CH4NP)); - tmpche &= (uint16_t)~((uint16_t)(TIMER_CHE_CH4P)); - tmpche |= (uint16_t)(tmp | (uint16_t)TIMER_CHE_CH4E); - - TIMERx->CHCTLR2 = tmpchctlr2; - TIMERx->CHE = tmpche; -} -/** - * @} - */ - -/** - * @} - */ - -/** - * @} - */ - diff --git a/bsp/gd32103c-eval/Libraries/GD32F1xx_standard_peripheral/Source/gd32f10x_usart.c b/bsp/gd32103c-eval/Libraries/GD32F1xx_standard_peripheral/Source/gd32f10x_usart.c deleted file mode 100644 index fa9304dd7b..0000000000 --- a/bsp/gd32103c-eval/Libraries/GD32F1xx_standard_peripheral/Source/gd32f10x_usart.c +++ /dev/null @@ -1,784 +0,0 @@ -/** - ****************************************************************************** - * @brief USART functions of the firmware library. - ****************************************************************************** - */ - -/* Includes ------------------------------------------------------------------*/ -#include "gd32f10x_usart.h" -#include "gd32f10x_rcc.h" - -/** @addtogroup GD32F10x_Firmware - * @{ - */ - -/** @defgroup USART - * @brief USART driver modules - * @{ - */ - -/** @defgroup USART_Private_Defines - * @{ - */ -/* USART Interrupts mask */ -#define INT_MASK ((uint16_t)(0x001F)) - -/* USART CTLR1 initializes bit mask */ -#define CTLR1_CLEAR_MASK ((uint16_t)(0x160C)) - -/* USART CTLR2 CLOCK initializes bit mask */ -#define CTLR2_CLOCK_CLEAR_MASK ((uint16_t)(0x0F00)) - -/* USART CTLR3 initializes bit mask */ -#define CTLR3_CLEAR_MASK ((uint16_t)(0x0300)) - -/** - * @} - */ - -/** @defgroup USART_Private_Functions - * @{ - */ - -/** - * @brief Reset the USART peripheral. - * @param USARTx: the USART peripheral. - * This parameter can be one of the following values - * @arg USART1 - * @arg USART2 - * @arg USART3 - * @arg UART4 - * @arg UART5 - * @param NewValue: new value of the USARTx peripheral. - * This parameter can be: ENABLE or DISABLE. - * @retval None - */ -void USART_DeInit(USART_TypeDef *USARTx) -{ - if (USARTx == USART0) { - RCC_APB2PeriphReset_Enable(RCC_APB2PERIPH_USART0RST, ENABLE); - RCC_APB2PeriphReset_Enable(RCC_APB2PERIPH_USART0RST, DISABLE); - } else if (USARTx == USART1) { - RCC_APB1PeriphReset_Enable(RCC_APB1PERIPH_USART1RST, ENABLE); - RCC_APB1PeriphReset_Enable(RCC_APB1PERIPH_USART1RST, DISABLE); - } else if (USARTx == USART2) { - RCC_APB1PeriphReset_Enable(RCC_APB1PERIPH_USART2RST, ENABLE); - RCC_APB1PeriphReset_Enable(RCC_APB1PERIPH_USART2RST, DISABLE); - } else if (USARTx == UART3) { - RCC_APB1PeriphReset_Enable(RCC_APB1PERIPH_UART3RST, ENABLE); - RCC_APB1PeriphReset_Enable(RCC_APB1PERIPH_UART3RST, DISABLE); - } else { - if (USARTx == UART4) { - RCC_APB1PeriphReset_Enable(RCC_APB1PERIPH_UART4RST, ENABLE); - RCC_APB1PeriphReset_Enable(RCC_APB1PERIPH_UART4RST, DISABLE); - } - } -} - -/** - * @brief Initialize the USART peripheral interface parameters. - * @param USARTx: the USART peripheral. - * This parameter can be one of the following values - * @arg USART1 - * @arg USART2 - * @arg USART3 - * @arg UART4 - * @arg UART5 - * @param USART_InitParaStruct: the struct USART_InitPara pointer. - * @retval None - */ -void USART_Init(USART_TypeDef *USARTx, USART_InitPara *USART_InitParaStruct) -{ - uint32_t divider = 0, apbclock = 0, temp = 0; - RCC_ClocksPara RCC_ClocksState; - - USARTx->CTLR1 &= ~((uint32_t)USART_CTLR1_UEN); - /* Initialize CTLR2 */ - temp = USARTx->CTLR2; - /* Reset stop bits then set it use USART_STBits */ - temp &= ~((uint32_t)USART_CTLR2_STB); - temp |= (uint32_t)USART_InitParaStruct->USART_STBits; - - USARTx->CTLR2 = temp; - - /*Initialize CTLR1*/ - temp = USARTx->CTLR1; - /* Reset WL, PCEN, PM, TEN and REN bits */ - temp &= ~((uint32_t)CTLR1_CLEAR_MASK); - - /* According to USART_WL,USART_Parity,USART_RxorTx to configure the CTLR1 */ - temp |= (uint32_t)USART_InitParaStruct->USART_WL | USART_InitParaStruct->USART_Parity | - USART_InitParaStruct->USART_RxorTx; - USARTx->CTLR1 = temp; - - /*Initialize CTLR3*/ - temp = USARTx->CTLR3; - /* Reset CTSEN and RTSEN bits */ - temp &= ~((uint32_t)CTLR3_CLEAR_MASK); - - /* According to USART_HardwareFlowControl to configure the CTLR3 */ - temp |= USART_InitParaStruct->USART_HardwareFlowControl; - USARTx->CTLR3 = temp; - - /*Initialize USART BRR*/ - RCC_GetClocksFreq(&RCC_ClocksState); - - if (USARTx == USART0) { - apbclock = RCC_ClocksState.APB2_Frequency; - } else { - apbclock = RCC_ClocksState.APB1_Frequency; - } - - /* Get integer of baud-rate divide and raction of baud-rate divider */ - divider = (uint32_t)((apbclock) / ((USART_InitParaStruct->USART_BRR))); - temp = (uint32_t)((apbclock) % ((USART_InitParaStruct->USART_BRR))); - - /* Round the divider : if fractional part i greater than 0.5 increment divider */ - if (temp >= (USART_InitParaStruct->USART_BRR) / 2) { - divider++; - } - - USARTx->BRR = (uint16_t)divider; -} - -/** - * @brief Initial the struct USART_InitPara - * @param USART_InitParaStruct: the struct USART_InitPara pointer - * @retval None - */ -void USART_ParaInit(USART_InitPara *USART_InitParaStruct) -{ - /* USART_InitStruct members default value */ - USART_InitParaStruct->USART_BRR = 9600; - USART_InitParaStruct->USART_WL = USART_WL_8B; - USART_InitParaStruct->USART_STBits = USART_STBITS_1; - USART_InitParaStruct->USART_Parity = USART_PARITY_RESET; - USART_InitParaStruct->USART_RxorTx = USART_RXORTX_RX | USART_RXORTX_TX; - USART_InitParaStruct->USART_HardwareFlowControl = USART_HARDWAREFLOWCONTROL_NONE; -} - -/** - * @brief Initialize the USARTx peripheral Clock according to the - * specified parameters in the USART_ClockInitStruct. - * @param USARTx: the USART peripheral. - * This parameter can be one of the following values - * @arg USART1 - * @arg USART2 - * @arg USART3 - * @param USART_ClockInitStruct: pointer to a USART_ClockInitTypeDef structure that contains - * the configuration information for the specified USART peripheral. - * @retval None - */ -void USART_ClockInit(USART_TypeDef *USARTx, USART_ClockInitPara *USART_ClockInitStruct) -{ - uint32_t temp = 0; - - temp = USARTx->CTLR2; - /* Clear CKEN, CPL, CPH, LBCP and SSM bits */ - temp &= ~(CTLR2_CLOCK_CLEAR_MASK); - - /* Reset hen set it usethe USART Clock, CPL, CPH, LBCP */ - temp |= (uint32_t)(USART_ClockInitStruct->USART_CKEN | USART_ClockInitStruct->USART_CPL | - USART_ClockInitStruct->USART_CPH | USART_ClockInitStruct->USART_LBCP); - /* Write to USART CTLR2 */ - USARTx->CTLR2 = (uint16_t)temp; -} - -/** - * @brief Initial the struct USART_ClockInitPara. - * @param USART_ClockInitParaStruct: the struct USART_ClockInitPara pointer - * @retval None - */ -void USART_ClockStructInit(USART_ClockInitPara *USART_ClockInitParaStruct) -{ - /*Reset USART_ClockInitStruct members default value */ - USART_ClockInitParaStruct->USART_CKEN = USART_CKEN_RESET; - USART_ClockInitParaStruct->USART_CPL = USART_CPL_LOW; - USART_ClockInitParaStruct->USART_CPH = USART_CPH_1EDGE; - USART_ClockInitParaStruct->USART_LBCP = USART_LBCP_DISABLE; -} - -/** - * @brief Enable or disable the specified USART peripheral. - * @param USARTx: the USART peripheral. - * This parameter can be one of the following values - * @arg USART1 - * @arg USART2 - * @arg USART3 - * @arg UART4 - * @arg UART5 - * @param NewValue: new value of the USARTx peripheral. - * This parameter can be: ENABLE or DISABLE. - * @retval None - */ -void USART_Enable(USART_TypeDef *USARTx, TypeState NewValue) -{ - /* Enable or disable the specified USART peripheral by setting the UEN bit in the CTLR1 register */ - if (NewValue != DISABLE) { - USARTx->CTLR1 |= USART_CTLR1_UEN; - } else { - USARTx->CTLR1 &= ~((uint16_t)USART_CTLR1_UEN); - } -} - -/** - * @brief Set the system clock prescaler. - * @param USARTx: the USART peripheral. - * This parameter can be one of the following values - * @arg USART1 - * @arg USART2 - * @arg USART3 - * @arg UART4 - * @arg UART5 - * @param USART_Prescaler: specifies the prescaler clock. - * @note This function has to be called before calling USART_Enable() function. - * @retval None - */ -void USART_SetPrescaler(USART_TypeDef *USARTx, uint8_t USART_Prescaler) -{ - /* Clear and set the USART prescaler */ - USARTx->GTPR &= ~((uint16_t)USART_GTPR_PSC); - - USARTx->GTPR |= USART_Prescaler; -} - -/** - * @brief Send data by the USART peripheral. - * @param USARTx: the USART peripheral. - * This parameter can be one of the following values - * @arg USART1 - * @arg USART2 - * @arg USART3 - * @arg UART4 - * @arg UART5 - * @param Data: the data will be sent. - * @retval None - */ -void USART_DataSend(USART_TypeDef *USARTx, uint16_t Data) -{ - USARTx->DR = (Data & (uint16_t)0x01FF); -} - -/** - * @brief Receive data by the USART peripheral. - * @param USARTx: the USART peripheral. - * This parameter can be one of the following values - * @arg USART1 - * @arg USART2 - * @arg USART3 - * @arg UART4 - * @arg UART5 - * @retval The received data. - */ -uint16_t USART_DataReceive(USART_TypeDef *USARTx) -{ - return (uint16_t)(USARTx->DR & (uint16_t)0x01FF); -} - - -/** - * @brief Set the address of the USART terminal. - * @param USARTx: the USART peripheral. - * This parameter can be one of the following values - * @arg USART1 - * @arg USART2 - * @arg USART3 - * @arg UART4 - * @arg UART5 - * @param USART_Address: Indicates the address of the USART node. - * @retval None - */ -void USART_Address(USART_TypeDef *USARTx, uint8_t USART_Address) -{ - /* Clear the USART address and Set the USART terminal*/ - USARTx->CTLR2 &= ~USART_CTLR2_ADD; - - USARTx->CTLR2 |= USART_Address; -} - -/** - * @brief Enable or disable the USART's mute mode. - * @param USARTx: the USART peripheral. - * This parameter can be one of the following values - * @arg USART1 - * @arg USART2 - * @arg USART3 - * @arg UART4 - * @arg UART5 - * @param NewValue: the USART mute mode. - * This parameter can be: ENABLE or DISABLE. - * @retval None - */ -void USART_MuteMode_Enable(USART_TypeDef *USARTx, TypeState NewValue) -{ - /* By setting the MEN bit in the CTLR1 register enable or disable the USART's mute mode*/ - if (NewValue != DISABLE) { - USARTx->CTLR1 |= USART_CTLR1_RWU; - } else { - USARTx->CTLR1 &= ~USART_CTLR1_RWU; - } -} - -/** - * @brief Set the USART WakeUp method from mute mode. - * @param USARTx: the USART peripheral. - * This parameter can be one of the following values - * @arg USART1 - * @arg USART2 - * @arg USART3 - * @arg UART4 - * @arg UART5 - * @param USART_WakeUp - * This parameter can be one of the following values - * @arg USART_WAKEUP_IDLELINE - * @arg USART_WAKEUP_ADDRESSMARK - * @retval None - */ -void USART_MuteModeWakeUp_Set(USART_TypeDef *USARTx, uint16_t USART_WakeUp) -{ - USARTx->CTLR1 &= ~((uint16_t)USART_CTLR1_WM); - USARTx->CTLR1 |= USART_WakeUp; -} - - -/** - * @brief Set the USART LIN Break detection length. - * @param USARTx: the USART peripheral. - * This parameter can be one of the following values - * @arg USART1 - * @arg USART2 - * @arg USART3 - * @arg UART4 - * @arg UART5 - * @param USART_LINBreakDetectLength - * This parameter can be one of the following values - * @arg USART_LINBREAKDETECTLENGTH_10B - * @arg USART_LINBREAKDETECTLENGTH_11B - * @retval None - */ -void USART_SetLINBDLength(USART_TypeDef *USARTx, uint16_t USART_LINBreakDetectLength) -{ - USARTx->CTLR2 &= ~((uint16_t)USART_CTLR2_LBDL); - USARTx->CTLR2 |= USART_LINBreakDetectLength; -} - -/** - * @brief Enable or disable the USART's LIN mode. - * @param USARTx: the USART peripheral. - * This parameter can be one of the following values - * @arg USART1 - * @arg USART2 - * @arg USART3 - * @arg UART4 - * @arg UART5 - * @param NewValue: the USART LIN mode value. - * This parameter can be: ENABLE or DISABLE. - * @retval None - */ -void USART_LIN_Enable(USART_TypeDef *USARTx, TypeState NewValue) -{ - /* By setting the LINEN bit in the CTLR2 register enable or disable the USART's LIN mode */ - if (NewValue != DISABLE) { - USARTx->CTLR2 |= USART_CTLR2_LMEN; - } else { - USARTx->CTLR2 &= ~((uint16_t)USART_CTLR2_LMEN); - } -} - -/** - * @brief Enable or disable the Half-duplex mode. - * @param USARTx: the USART peripheral. - * This parameter can be one of the following values - * @arg USART1 - * @arg USART2 - * @arg USART3 - * @arg UART4 - * @arg UART5 - * @param NewValue: the USART Half-duplex mode value. - * This parameter can be: ENABLE or DISABLE. - * @retval None - */ -void USART_HalfDuplex_Enable(USART_TypeDef *USARTx, TypeState NewValue) -{ - /* By setting the HDEN bit in the CTLR3 register enable or disable the Half-duplex mode */ - if (NewValue != DISABLE) { - USARTx->CTLR3 |= USART_CTLR3_HDEN; - } else { - USARTx->CTLR3 &= ~USART_CTLR3_HDEN; - } -} - -/** - * @brief Set the the USART guard time. - * @param USARTx: the USART peripheral. - * This parameter can be one of the following values - * @arg USART1 - * @arg USART2 - * @arg USART3 - * @param USART_GuardTime: the USART guard time. - * @retval None - */ -void USART_GuardTime_Set(USART_TypeDef *USARTx, uint8_t USART_GuardTime) -{ - /* Set the USART guard time */ - USARTx->GTPR &= ~((uint16_t)USART_GTPR_GT); - - USARTx->GTPR |= (uint16_t)((uint16_t)USART_GuardTime << 0x08); -} - -/** - * @brief Enable or disable the USART's Smart Card mode. - * @param USARTx: the USART peripheral. - * This parameter can be one of the following values - * @arg USART1 - * @arg USART2 - * @arg USART3 - * @param NewValue: the Smart Card mode value. - * This parameter can be: ENABLE or DISABLE. - * @retval None - */ -void USART_SmartCard_Enable(USART_TypeDef *USARTx, TypeState NewValue) -{ - /* By setting the SCEN bit in the CTLR3 register enable or disable the USART's Smart Card mode */ - if (NewValue != DISABLE) { - USARTx->CTLR3 |= USART_CTLR3_SCEN; - } else { - USARTx->CTLR3 &= ~((uint16_t)USART_CTLR3_SCEN); - } -} - -/** - * @brief Enable or disable NACK transmission. - * @param USARTx: the USART peripheral. - * This parameter can be one of the following values - * @arg USART1 - * @arg USART2 - * @arg USART3 - * @arg UART4 - * @arg UART5 - * @param NewValue: the NACK transmission state. - * This parameter can be: ENABLE or DISABLE. - * @retval None - */ -void USART_SmartCardNACK_Enable(USART_TypeDef *USARTx, TypeState NewValue) -{ - /* By setting the NACK bit in the CTLR3 register Enable or disable NACK transmission */ - if (NewValue != DISABLE) { - USARTx->CTLR3 |= USART_CTLR3_NACK; - } else { - USARTx->CTLR3 &= ~((uint32_t)USART_CTLR3_NACK); - } -} - -/** - * @brief DMA enable for transmission or reception. - * @param USARTx: the USART peripheral. - * This parameter can be one of the following values - * @arg USART1 - * @arg USART2 - * @arg USART3 - * @arg UART4 - * @arg UART5 - * @param USART_DMAEnable: the DMA request. - * This parameter can be one of the following values - * @arg USART_DMAREQ_RX - * @arg USART_DMAREQ_TX - * @param NewValue: the DMA Request sources state. - * This parameter can be: ENABLE or DISABLE. - * @retval None - */ -void USART_DMA_Enable(USART_TypeDef *USARTx, uint16_t USART_DMAEnable, TypeState NewValue) -{ - /* Enable or disable the DMA transfer for transmission or reception by setting the DENT and/or - DENR bits in the USART CTLR3 register */ - if (NewValue != DISABLE) { - USARTx->CTLR3 |= USART_DMAEnable; - } else { - USARTx->CTLR3 &= ~USART_DMAEnable; - } - -} - -/** - * @brief Set the USARTX IrDA low-power. - * @param USARTx: the USART peripheral. - * This parameter can be one of the following values - * @arg USART1 - * @arg USART2 - * @arg USART3 - * @arg UART4 - * @arg UART5 - * @param USART_IrDAMode - * This parameter can be one of the following values - * @arg USART_IRDAMODE_LOWPOWER - * @arg USART_IRDAMODE_NORMAL. - * @retval None - */ -void USART_IrDA_Set(USART_TypeDef *USARTx, uint16_t USART_IrDAMode) -{ - USARTx->CTLR3 &= ~((uint16_t)USART_CTLR3_IRLP); - USARTx->CTLR3 |= USART_IrDAMode; -} - -/** - * @brief Enable or disable the USART's IrDA interface. - * @param USARTx: the USART peripheral. - * This parameter can be one of the following values - * @arg USART1 - * @arg USART2 - * @arg USART3 - * @arg UART4 - * @arg UART5 - * @param NewValue: the IrDA mode value. - * This parameter can be: ENABLE or DISABLE. - * @retval None - */ -void USART_IrDA_Enable(USART_TypeDef *USARTx, TypeState NewValue) -{ - /* By setting the IREN bit in the CTLR3 register enable or disable the USART's IrDA interface */ - if (NewValue != DISABLE) { - USARTx->CTLR3 |= USART_CTLR3_IREN; - } else { - USARTx->CTLR3 &= ~((uint16_t)USART_CTLR3_IREN); - } -} - -/** - * @brief Detect the bit flag of STR register. - * @param USARTx: the USART peripheral. - * This parameter can be one of the following values - * @arg USART1 - * @arg USART2 - * @arg USART3 - * @arg UART4 - * @arg UART5 - * @param USART_FLAG: the flag of STR register. - * This parameter can be one of the following values: - * @arg USART_FLAG_CTSF: CTS Change flag.(not available for UART4 and UART5) - * @arg USART_FLAG_LBDF: LIN Break detection flag - * @arg USART_FLAG_TBE: Transmit data register empty flag. - * @arg USART_FLAG_TC: Transmission Complete flag. - * @arg USART_FLAG_RBNE: Receive data register not empty flag. - * @arg USART_FLAG_IDLEF:Idle Line detection flag. - * @arg USART_FLAG_ORE: OverRun Error flag. - * @arg USART_FLAG_NE: Noise Error flag. - * @arg USART_FLAG_FE: Framing Error flag. - * @arg USART_FLAG_PE: Parity Error flag. - * @retval The new state of USART_FLAG (SET or RESET). - */ -TypeState USART_GetBitState(USART_TypeDef *USARTx, uint16_t USART_FLAG) -{ - if ((USARTx->STR & USART_FLAG) != (uint16_t)RESET) { - return SET; - } else { - return RESET; - } -} - -/** - * @brief Enable or disable USART interrupt. - * @param USARTx: the USART peripheral. - * This parameter can be one of the following values - * @arg USART1 - * @arg USART2 - * @arg USART3 - * @arg UART4 - * @arg UART5 - * @param USART_INT: the USART interrupt - * This parameter can be one of the following values: - * @arg USART_INT_PE - * @arg USART_INT_TBE - * @arg USART_INT_TC - * @arg USART_INT_RBNE - * @arg USART_INT_IDLEF - * @arg USART_INT_LBDF - * @arg USART_INT_CTSF (not available for UART4 and UART5) - * @arg USART_INT_ERIE - * @param NewValue: the USART interrupt State. - * This parameter can be: ENABLE or DISABLE. - * @retval None - */ -void USART_INT_Set(USART_TypeDef *USARTx, uint16_t USART_INT, TypeState NewValue) -{ - uint32_t intpos = 0, usartreg = 0; - uint32_t usartxbase = 0; - - usartxbase = (uint32_t)USARTx; - - /* Get the USART register index and the interrupt position */ - usartreg = ((uint8_t)(USART_INT) >> 0x05); - intpos = USART_INT & INT_MASK; - - /* Get the interrupt from which register: CTLR1,CTLR2 OR CTLR3 */ - if (usartreg == 0x01) { - usartxbase += 0x0C; - } else if (usartreg == 0x02) { - usartxbase += 0x10; - } else { - usartxbase += 0x14; - } - if (NewValue != DISABLE) { - *(__IO uint32_t *)usartxbase |= (((uint32_t)0x01) << intpos); - } else { - *(__IO uint32_t *)usartxbase &= ~(((uint32_t)0x01) << intpos); - } -} - -/** - * @brief Clear the bit flag. - * @param USARTx: the USART peripheral. - * This parameter can be one of the following values - * @arg USART1 - * @arg USART2 - * @arg USART3 - * @arg UART4 - * @arg UART5 - * @param USART_FLAG: the bit flag usart . - * This parameter can be one of the following values: - * @arg USART_FLAG_CTSF: CTS Change flag.(not available for UART4 and UART5) - * @arg USART_FLAG_LBDF: LIN Break detection flag - * @arg USART_FLAG_TC: Transmission Complete flag. - * @arg USART_FLAG_RBNE: Receive data register not empty flag. - * @note - * - PE (Parity error), FE (Framing error), NE (Noise error), ORE (OverRun - * error) and IDLEF (Idle line detected) flag bits are cleared by - * software sequence: a read operation to USART_STR register - * (USART_GetBitState()) followed by a read operation to USART_DR register - * (USART_DataReceive()). - * - RBNE flag bit can be also cleared by a read to the USART_DR register - * (USART_DataReceive()). - * - TC flag bit can be also cleared by software sequence: a read - * operation to USART_STR register (USART_GetBitState()) followed by a write - * operation to USART_DR register (USART_DataSend()). - * - TBE flag bit is cleared only by a write to the USART_DR register - * (USART_DataSend()). - * @retval None - */ -void USART_ClearBitState(USART_TypeDef *USARTx, uint16_t USART_FLAG) -{ - USARTx->STR = (uint16_t)~ USART_FLAG; -} - -/** - * @brief Detect the interrupt bit flag. - * @param USARTx: the USART peripheral. - * This parameter can be one of the following values - * @arg USART1 - * @arg USART2 - * @arg USART3 - * @arg UART4 - * @arg UART5 - * @param USART_INT: the USART interrupt bit flag. - * This parameter can be one of the following values: - * @arg USART_INT_PE - * @arg USART_INT_TBE - * @arg USART_INT_TC - * @arg USART_INT_RBNE - * @arg USART_INT_IDLEF - * @arg USART_INT_LBDF - * @arg USART_INT_CTSF: CTS flag interrupt (not available for UART4 and UART5) - * @arg USART_INT_ORE - * @arg USART_INT_NE - * @arg USART_INT_FE - * @retval The new state of USART_INT (SET or RESET). - */ -TypeState USART_GetIntBitState(USART_TypeDef *USARTx, uint16_t USART_INT) -{ - uint16_t bitpos = 0, itmask = 0, usartreg = 0; - - /* Get the USART register index and the interrupt position */ - usartreg = (((uint8_t)USART_INT) >> 0x05); - - itmask = (USART_INT) & (INT_MASK); - - itmask = (uint16_t)0x01 << itmask; - - if (usartreg == 0x01) { - itmask &= USARTx->CTLR1; - } else { - if (usartreg == 0x02) { - itmask &= USARTx->CTLR2; - } else { - itmask &= USARTx->CTLR3; - } - } - - bitpos = USART_INT >> 0x08; - bitpos = (uint32_t)0x01 << bitpos; - bitpos &= USARTx->STR; - if ((itmask != (uint16_t)RESET) && (bitpos != (uint16_t)RESET)) { - return SET; - } else { - return RESET; - } -} - -/** - * @brief Clear the interrupt bit flag. - * @param USARTx: the USART peripheral. - * This parameter can be one of the following values - * @arg USART1 - * @arg USART2 - * @arg USART3 - * @arg UART4 - * @arg UART5 - * @param USART_INT: the interrupt bit flag. - * This parameter can be one of the following values: * @arg USART_INT_TC - * @arg USART_INT_LBDF - * @arg USART_INT_CTSF: CTS Flag interrupt (not available for UART4 and UART5) - * @arg USART_INT_RBNE - * @arg USART_INT_TC - * @note - * - PE (Parity error), FE (Framing error), NE (Noise error), ORE (OverRun - * error) and IDLEF (Idle line detected flag) interrupt bits are cleared by - * software sequence: a read operation to USART_STR register - * (USART_GetINTState()) followed by a read operation to USART_DR register - * (USART_DataReceive()). - * - RBNE interrupt bit can be also cleared by a read to the USART_DR register - * (USART_DataReceive()). - * - TC interrupt bit can be also cleared by software sequence: a read - * operation to USART_STR register (USART_GetINTState()) followed by a write - * operation to USART_DR register (USART_DataSend()). - * - TBE interrupt bit is cleared only by a write to the USART_DR register - * (USART_DataSend()). - * @retval None - */ -void USART_ClearIntBitState(USART_TypeDef *USARTx, uint16_t USART_INT) -{ - uint16_t bitpos = 0, itmask = 0; - - bitpos = USART_INT >> 0x08; - itmask = ((uint16_t)0x01 << (uint16_t)bitpos); - USARTx->STR = (uint16_t)~itmask; -} - -/** - * @brief Send break command. - * @param USARTx: the USART peripheral - * This parameter can be one of the following values - * @arg USART1 - * @arg USART2 - * @arg USART3 - * @arg UART4 - * @arg UART5 - * @retval None - */ -void USART_SendBreak(USART_TypeDef *USARTx) -{ - - /* Send break command */ - USARTx->CTLR1 |= USART_CTLR1_SBKCMD; -} - -/** - * @} - */ - -/** - * @} - */ - -/** - * @} - */ - diff --git a/bsp/gd32103c-eval/Libraries/GD32F1xx_standard_peripheral/Source/gd32f10x_wwdg.c b/bsp/gd32103c-eval/Libraries/GD32F1xx_standard_peripheral/Source/gd32f10x_wwdg.c deleted file mode 100644 index 504aad2868..0000000000 --- a/bsp/gd32103c-eval/Libraries/GD32F1xx_standard_peripheral/Source/gd32f10x_wwdg.c +++ /dev/null @@ -1,155 +0,0 @@ -/** - ****************************************************************************** - * @brief WWDG functions of the firmware library. - ****************************************************************************** - */ - -/* Includes ------------------------------------------------------------------*/ -#include "gd32f10x_wwdg.h" -#include "gd32f10x_rcc.h" - -/** @addtogroup GD32F10x_Firmware - * @{ - */ - -/** @defgroup WWDG - * @brief WWDG driver modules - * @{ - */ - -/** @defgroup WWDG_Private_Variables - * @{ - */ - -/* CFR register bit mask */ -#define CFR_PS_MASK ((uint32_t)0xFFFFFE7F) -#define CFR_WIN_MASK ((uint32_t)0xFFFFFF80) -#define BIT_MASK ((uint8_t)0x7F) - -/** - * @} - */ - -/** @defgroup WWDG_Private_Functions - * @{ - */ - -/** - * @brief Reset the WWDG configuration. - * @param None - * @retval None - */ -void WWDG_DeInit(void) -{ - RCC_APB1PeriphReset_Enable(RCC_APB1PERIPH_WWDG, ENABLE); - RCC_APB1PeriphReset_Enable(RCC_APB1PERIPH_WWDG, DISABLE); -} - -/** - * @brief Set WWDG prescaler value. - * @param PrescalerValue: WWDG Prescaler value. - * This parameter can be one of the following values: - * @arg WWDG_PRESCALER_1: the time base of watchdog counter = (PCLK1/4096)/1 - * @arg WWDG_PRESCALER_2: the time base of watchdog counter = (PCLK1/4096)/2 - * @arg WWDG_PRESCALER_4: the time base of watchdog counter = (PCLK1/4096)/4 - * @arg WWDG_PRESCALER_8: the time base of watchdog counter = (PCLK1/4096)/8 - * @retval None - */ -void WWDG_SetPrescalerValue(uint32_t PrescalerValue) -{ - uint32_t temp = 0; - - /* Clear PS[1:0] bits */ - temp = WWDG->CFR & CFR_PS_MASK; - - /* Set PS[1:0] bits */ - temp |= PrescalerValue; - WWDG->CFR = temp; -} - -/** - * @brief Set watchdog window value. - * @param WindowValue: the window value to be compared to the downcounter. - * @retval None - */ -void WWDG_SetWindowValue(uint8_t WindowValue) -{ - __IO uint32_t temp = 0; - - /* Clear WIN[6:0] bits */ - temp = WWDG->CFR & CFR_WIN_MASK; - - /* Set WIN[6:0] bits */ - temp |= WindowValue & (uint32_t) BIT_MASK; - WWDG->CFR = temp; -} - -/** - * @brief Enable the WWDG Early wakeup interrupt(EWI). - * @note An interrupt occurs when the counter reaches 0x40 if the bit is set. - * It's cleared by a hardware reset. A write of 0 has no effect. - * @param None - * @retval None - */ -void WWDG_EnableInt(void) -{ - WWDG->CFR |= WWDG_CFR_EWI; -} - -/** - * @brief Set the value of the watchdog counter. - * @param CounterValue: the watchdog counter value. - * @retval None - */ -void WWDG_SetCounterValue(uint8_t CounterValue) -{ - /* Write to CNT[6:0] bits */ - WWDG->CTLR = CounterValue & BIT_MASK; -} - -/** - * @brief Start the window watchdog counter. - * @param CounterValue: The value of the watchdog counter. - * @retval None - */ -void WWDG_Enable(uint8_t CounterValue) -{ - WWDG->CTLR = WWDG_CTLR_WDGEN | CounterValue; -} - -/** - * @brief Check the Early Wakeup interrupt bit state. - * @param None - * @retval The new state of the Early Wakeup interrupt (SET or RESET). - */ -TypeState WWDG_GetBitState(void) -{ - if ((WWDG->STR) != (uint32_t)RESET) { - return SET; - } else { - return RESET; - } -} - -/** - * @brief Clear Early Wakeup interrupt flag. - * @param None - * @retval None - */ -void WWDG_ClearBitState(void) -{ - WWDG->STR = (uint32_t)RESET; -} - -/** - * @} - */ - -/** - * @} - */ - -/** - * @} - */ - diff --git a/bsp/gd32103c-eval/Libraries/SConscript b/bsp/gd32103c-eval/Libraries/SConscript deleted file mode 100644 index a4967104cb..0000000000 --- a/bsp/gd32103c-eval/Libraries/SConscript +++ /dev/null @@ -1,26 +0,0 @@ -import rtconfig -from building import * - -# get current directory -cwd = GetCurrentDir() - -# The set of source files associated with this SConscript file. - -src = Glob('GD32F1xx_standard_peripheral/Source/*.c') -src += [cwd + '/CMSIS/GD/GD32F1xx/Source/system_gd32f1xx.c'] - -#add for startup script -if rtconfig.CROSS_TOOL == 'gcc': - src += [cwd + '/CMSIS/GD/GD32F1xx/Source/GCC/startup_gd32.s'] - src += [cwd + '/CMSIS/GD/GD32F1xx/Source/GCC/isr_tab.s'] - -path = [ - cwd + '/CMSIS/GD/GD32F1xx/Include', - cwd + '/CMSIS', - cwd + '/GD32F1xx_standard_peripheral/Include',] - -CPPDEFINES = ['USE_STDPERIPH_DRIVER', 'GD32F1XX'] - -group = DefineGroup('GD32_Lib', src, depend = [''], CPPPATH = path, CPPDEFINES = CPPDEFINES) - -Return('group') diff --git a/bsp/gd32103c-eval/README.md b/bsp/gd32103c-eval/README.md deleted file mode 100644 index d55bccd908..0000000000 --- a/bsp/gd32103c-eval/README.md +++ /dev/null @@ -1,74 +0,0 @@ -# GD32103C-EVAL - -## 简介 - -GD32103C-EVAL是-兆易创新推出的一款GD32F103VCT6系列的评估板，板载资源主要如下： - -| 硬件 | 描述 | -| --------- | ------------- | -| 芯片型号 | GD32F103VCT6 | -| CPU | ARM Cortex M3 | -| 主频 | 108M | -| 片内SRAM | 48K | -| 片内FLASH | 256K | -| 片外FLASH | 1Gb | - -## 编译说明 - -GD32103C-EVAL板级包支持MDK4﹑MDK5﹑IAR开发环境和GCC编译器，以下是具体版本信息： - -| IDE/编译器 | 已测试版本 | -| ---------- | ---------------------------- | -| GCC |gcc version 6.2.1 20161205 (release) | - -## 烧写及执行 - -供电方式：开发板使用 Mini USB 接口或者 DC-005 连接器提供 5V 电源。 - -下载程序：下载程序到开发板需要一套 JLink 或者使用 GD-Link 工具。 - -串口连接：使用串口线连接到COM1(UART0)，或者使用USB转TTL模块连接PA9(MCU TX)和PA10(MCU RX)。 - -### 运行结果 - -如果编译 & 烧写无误，当复位设备后，会在串口上看到RT-Thread的启动logo信息： - -```bash - \ | / -- RT - Thread Operating System - / | \ 4.0.3 build Jan 4 2021 - 2006 - 2021 Copyright by rt-thread team -msh /> -``` -## 驱动支持情况及计划 - -| 驱动 | 支持情况 | 备注 | -| --------- | -------- | :------------------------: | -| UART | 支持 | UART0~4 | -| GPIO | 支持 | GPIOA~G | -| ADC | 支持 | ADC0~1 | -| HWTIMER | 支持 | TIMER0~7 | -| RTC | 支持 | RTC | -| WDT | 支持 | Free watchdog timer | -| IIC | 未支持 | I2C0~1 | -| SPI | 未支持 | SPI0~2 | -| ETH | 未支持 | | -| LCD | 未支持 | | -| SDRAM | 未支持 | | -| SPI FLASH | 未支持 | | - -### IO在板级支持包中的映射情况 - -| IO号 | 板级包中的定义 | -| ---- | -------------- | -| PC0 | LED1 | -| PC2 | LED2 | -| PE0 | LED3 | -| PE1 | LED4 | -| PA0 | KEY1 | -| PC13 | KEY2 | -| PB14 | KEY3 | - -## 联系人信息 - -维护人：[iysheng](https://github.com/iysheng) diff --git a/bsp/gd32103c-eval/SConscript b/bsp/gd32103c-eval/SConscript deleted file mode 100644 index fe0ae941ae..0000000000 --- a/bsp/gd32103c-eval/SConscript +++ /dev/null @@ -1,14 +0,0 @@ -# for module compiling -import os -Import('RTT_ROOT') - -cwd = str(Dir('#')) -objs = [] -list = os.listdir(cwd) - -for d in list: - path = os.path.join(cwd, d) - if os.path.isfile(os.path.join(path, 'SConscript')): - objs = objs + SConscript(os.path.join(d, 'SConscript')) - -Return('objs') diff --git a/bsp/gd32103c-eval/SConstruct b/bsp/gd32103c-eval/SConstruct deleted file mode 100644 index 6b5d561848..0000000000 --- a/bsp/gd32103c-eval/SConstruct +++ /dev/null @@ -1,40 +0,0 @@ -import os -import sys -import rtconfig - -if os.getenv('RTT_ROOT'): - RTT_ROOT = os.getenv('RTT_ROOT') -else: - RTT_ROOT = os.path.normpath(os.getcwd() + '/../..') - -sys.path = sys.path + [os.path.join(RTT_ROOT, 'tools')] -try: - from building import * -except: - print('Cannot found RT-Thread root directory, please check RTT_ROOT') - print(RTT_ROOT) - exit(-1) - -TARGET = 'rtthread-gd32f4xx.' + rtconfig.TARGET_EXT - -DefaultEnvironment(tools=[]) -env = Environment(tools = ['mingw'], - AS = rtconfig.AS, ASFLAGS = rtconfig.AFLAGS, - CC = rtconfig.CC, CFLAGS = rtconfig.CFLAGS, - AR = rtconfig.AR, ARFLAGS = '-rc', - LINK = rtconfig.LINK, LINKFLAGS = rtconfig.LFLAGS) -env.PrependENVPath('PATH', rtconfig.EXEC_PATH) - -if rtconfig.PLATFORM == 'iar': - env.Replace(CCCOM = ['$CC $CFLAGS $CPPFLAGS $_CPPDEFFLAGS $_CPPINCFLAGS -o $TARGET $SOURCES']) - env.Replace(ARFLAGS = ['']) - env.Replace(LINKCOM = env["LINKCOM"] + ' --map project.map') - -Export('RTT_ROOT') -Export('rtconfig') - -# prepare building environment -objs = PrepareBuilding(env, RTT_ROOT, has_libcpu=False) - -# make a building -DoBuilding(TARGET, objs) diff --git a/bsp/gd32103c-eval/applications/SConscript b/bsp/gd32103c-eval/applications/SConscript deleted file mode 100644 index ca2395451a..0000000000 --- a/bsp/gd32103c-eval/applications/SConscript +++ /dev/null @@ -1,11 +0,0 @@ -Import('RTT_ROOT') -Import('rtconfig') -from building import * - -cwd = GetCurrentDir() -src = Glob('*.c') -CPPPATH = [cwd] - -group = DefineGroup('Applications', src, depend = [''], CPPPATH = CPPPATH) - -Return('group') diff --git a/bsp/gd32103c-eval/applications/main.c b/bsp/gd32103c-eval/applications/main.c deleted file mode 100644 index e9256f1d4d..0000000000 --- a/bsp/gd32103c-eval/applications/main.c +++ /dev/null @@ -1,33 +0,0 @@ -/* - * Copyright (c) 2006-2021, RT-Thread Development Team - * - * SPDX-License-Identifier: Apache-2.0 - * - * Change Logs: - * Date Author Notes - * 2021-01-04 iysheng first version - */ - -#include <board.h> -#include <drivers/adc.h> -#include <rtdbg.h> -#include <stdio.h> -#include <rtthread.h> -#include "board.h" - -#define LED1 GET_PIN(C, 0) - -int main(void) -{ - rt_pin_mode(LED1, PIN_MODE_OUTPUT); - - while (1) - { - rt_pin_write(LED1, PIN_HIGH); - rt_thread_mdelay(500); - rt_pin_write(LED1, PIN_LOW); - rt_thread_mdelay(500); - } - - return 0; -} diff --git a/bsp/gd32103c-eval/drivers/SConscript b/bsp/gd32103c-eval/drivers/SConscript deleted file mode 100644 index 30a1a338d0..0000000000 --- a/bsp/gd32103c-eval/drivers/SConscript +++ /dev/null @@ -1,35 +0,0 @@ -Import('RTT_ROOT') -Import('rtconfig') -from building import * - -cwd = os.path.join(str(Dir('#')), 'drivers') - -# add the general drivers. -src = Split(""" -board.c -""") - -CPPPATH = [cwd] - -# add uart drivers. -if GetDepend('RT_USING_SERIAL'): - src += ['drv_usart.c'] - -if GetDepend('RT_USING_PIN'): - src += ['drv_gpio.c'] - -if GetDepend('RT_USING_ADC'): - src += ['drv_adc.c'] - -if GetDepend('RT_USING_HWTIMER'): - src += ['drv_hwtimer.c'] - -if GetDepend('RT_USING_RTC'): - src += ['drv_rtc.c'] - -if GetDepend('RT_USING_WDT'): - src += ['drv_iwdt.c'] - -group = DefineGroup('Drivers', src, depend = [''], CPPPATH = CPPPATH) - -Return('group') diff --git a/bsp/gd32103c-eval/drivers/board.c b/bsp/gd32103c-eval/drivers/board.c deleted file mode 100644 index 0e4d1a1305..0000000000 --- a/bsp/gd32103c-eval/drivers/board.c +++ /dev/null @@ -1,74 +0,0 @@ -/* - * Copyright (c) 2006-2021, RT-Thread Development Team - * - * SPDX-License-Identifier: Apache-2.0 - * - * Change Logs: - * Date Author Notes - * 2021-01-04 iysheng first version - */ - -#include <stdint.h> -#include <rthw.h> -#include <rtthread.h> - -#include <gd32f10x.h> -#include <board.h> -#include <drv_usart.h> - -/* - * System Clock Configuration - */ -void SystemClock_Config(void) -{ - SysTick_Config(SystemCoreClock / RT_TICK_PER_SECOND); - NVIC_SetPriority(SysTick_IRQn, 0); -} - -/* - * This is the timer interrupt service routine. - */ -void SysTick_Handler(void) -{ - /* enter interrupt */ - rt_interrupt_enter(); - - rt_tick_increase(); - - /* leave interrupt */ - rt_interrupt_leave(); -} - -/** - * This function will initial GD32 board. - */ -void rt_hw_board_init() -{ - /* NVIC Configuration */ -#define NVIC_VTOR_MASK 0x3FFFFF80 -#ifdef VECT_TAB_RAM - /* Set the Vector Table base location at 0x10000000 */ - SCB->VTOR = (0x10000000 & NVIC_VTOR_MASK); -#else /* VECT_TAB_FLASH */ - /* Set the Vector Table base location at 0x08000000 */ - SCB->VTOR = (0x08000000 & NVIC_VTOR_MASK); -#endif - - SystemClock_Config(); - -#ifdef RT_USING_COMPONENTS_INIT - rt_components_board_init(); -#endif - -#if defined(RT_USING_CONSOLE) && defined(RT_USING_DEVICE) - rt_console_set_device(RT_CONSOLE_DEVICE_NAME); -#endif - -#ifdef BSP_USING_SDRAM - rt_system_heap_init((void *)EXT_SDRAM_BEGIN, (void *)EXT_SDRAM_END); -#else - rt_system_heap_init((void *)HEAP_BEGIN, (void *)HEAP_END); -#endif -} - -/*@}*/ diff --git a/bsp/gd32103c-eval/drivers/board.h b/bsp/gd32103c-eval/drivers/board.h deleted file mode 100644 index 6e48eba213..0000000000 --- a/bsp/gd32103c-eval/drivers/board.h +++ /dev/null @@ -1,26 +0,0 @@ -/* - * Copyright (c) 2006-2021, RT-Thread Development Team - * - * SPDX-License-Identifier: Apache-2.0 - * - * Change Logs: - * Date Author Notes - * 2021-01-04 iysheng first version - */ - -#ifndef __BOARD_H__ -#define __BOARD_H__ - -#include <gd32f10x.h> - -#include "drv_gpio.h" - -#define GD32_SRAM_SIZE 48 -#define GD32_SRAM_END (0x20000000 + GD32_SRAM_SIZE * 1024) - -extern int __bss_end; -#define HEAP_BEGIN (&__bss_end) - -#define HEAP_END GD32_SRAM_END - -#endif diff --git a/bsp/gd32103c-eval/drivers/drv_adc.h b/bsp/gd32103c-eval/drivers/drv_adc.h deleted file mode 100644 index 4fba7c093d..0000000000 --- a/bsp/gd32103c-eval/drivers/drv_adc.h +++ /dev/null @@ -1,23 +0,0 @@ -/* - * Copyright (c) 2006-2021, RT-Thread Development Team - * - * SPDX-License-Identifier: Apache-2.0 - * - * Change Logs: - * Date Author Notes - * 2021-01-03 iysheng first release - */ - -#ifndef __DRV_ADC_H__ -#define __DRV_ADC_H__ - -#ifdef __cplusplus -extern "C" { -#endif - -#ifdef __cplusplus -} -#endif - -#endif /* __DRV_ADC_H__ */ - diff --git a/bsp/gd32103c-eval/drivers/drv_comm.h b/bsp/gd32103c-eval/drivers/drv_comm.h deleted file mode 100644 index 5aef53cce2..0000000000 --- a/bsp/gd32103c-eval/drivers/drv_comm.h +++ /dev/null @@ -1,27 +0,0 @@ -/* - * Copyright (c) 2006-2021, RT-Thread Development Team - * - * SPDX-License-Identifier: Apache-2.0 - * - * Change Logs: - * Date Author Notes - * 2021-01-28 iysheng first version - */ - -#ifndef __DRV_COMM_H__ -#define __DRV_COMM_H__ - -#ifdef __cplusplus -extern "C" { -#endif - -#ifndef ARRAY_SIZE -#define ARRAY_SIZE(x) (sizeof(x) / sizeof(x[0])) -#endif - -#ifdef __cplusplus -} -#endif - -#endif /* __DRV_HWTIMER_H__ */ - diff --git a/bsp/gd32103c-eval/drivers/drv_gpio.c b/bsp/gd32103c-eval/drivers/drv_gpio.c deleted file mode 100644 index beee11b65d..0000000000 --- a/bsp/gd32103c-eval/drivers/drv_gpio.c +++ /dev/null @@ -1,512 +0,0 @@ -/* - * Copyright (c) 2006-2021, RT-Thread Development Team - * - * SPDX-License-Identifier: Apache-2.0 - * - * Change Logs: - * Date Author Notes - * 2020-12-27 iysheng first version - * 2021-01-01 iysheng support exti interrupt - */ - -#include <board.h> -#include "drv_gpio.h" - -#ifdef RT_USING_PIN - -#if defined(GPIOG) -#define __GD32_PORT_MAX 7u -#elif defined(GPIOF) -#define __GD32_PORT_MAX 6u -#elif defined(GPIOE) -#define __GD32_PORT_MAX 5u -#elif defined(GPIOD) -#define __GD32_PORT_MAX 4u -#elif defined(GPIOC) -#define __GD32_PORT_MAX 3u -#elif defined(GPIOB) -#define __GD32_PORT_MAX 2u -#elif defined(GPIOA) -#define __GD32_PORT_MAX 1u -#else -#define __GD32_PORT_MAX 0u -#error Unsupported GD32 GPIO peripheral. -#endif - -#define PIN_GDPORT_MAX __GD32_PORT_MAX - -static const struct pin_irq_map pin_irq_map[] = -{ -#if defined(SOC_SERIES_GD32F1) - {GPIO_PIN_0, EXTI0_IRQn}, - {GPIO_PIN_1, EXTI1_IRQn}, - {GPIO_PIN_2, EXTI2_IRQn}, - {GPIO_PIN_3, EXTI3_IRQn}, - {GPIO_PIN_4, EXTI4_IRQn}, - {GPIO_PIN_5, EXTI9_5_IRQn}, - {GPIO_PIN_6, EXTI9_5_IRQn}, - {GPIO_PIN_7, EXTI9_5_IRQn}, - {GPIO_PIN_8, EXTI9_5_IRQn}, - {GPIO_PIN_9, EXTI9_5_IRQn}, - {GPIO_PIN_10, EXTI15_10_IRQn}, - {GPIO_PIN_11, EXTI15_10_IRQn}, - {GPIO_PIN_12, EXTI15_10_IRQn}, - {GPIO_PIN_13, EXTI15_10_IRQn}, - {GPIO_PIN_14, EXTI15_10_IRQn}, - {GPIO_PIN_15, EXTI15_10_IRQn}, -#else -#error "Unsupported soc series" -#endif -}; - -static struct rt_pin_irq_hdr pin_irq_hdr_tab[] = -{ - {-1, 0, RT_NULL, RT_NULL}, - {-1, 0, RT_NULL, RT_NULL}, - {-1, 0, RT_NULL, RT_NULL}, - {-1, 0, RT_NULL, RT_NULL}, - {-1, 0, RT_NULL, RT_NULL}, - {-1, 0, RT_NULL, RT_NULL}, - {-1, 0, RT_NULL, RT_NULL}, - {-1, 0, RT_NULL, RT_NULL}, - {-1, 0, RT_NULL, RT_NULL}, - {-1, 0, RT_NULL, RT_NULL}, - {-1, 0, RT_NULL, RT_NULL}, - {-1, 0, RT_NULL, RT_NULL}, - {-1, 0, RT_NULL, RT_NULL}, - {-1, 0, RT_NULL, RT_NULL}, - {-1, 0, RT_NULL, RT_NULL}, - {-1, 0, RT_NULL, RT_NULL}, -}; -static uint32_t pin_irq_enable_mask = 0; - -#define ITEM_NUM(items) sizeof(items) / sizeof(items[0]) - -static rt_base_t gd32_pin_get(const char *name) -{ - rt_base_t pin = 0; - int hw_port_num, hw_pin_num = 0; - int i, name_len; - - name_len = rt_strlen(name); - - if ((name_len < 4) || (name_len >= 6)) - { - return -RT_EINVAL; - } - if ((name[0] != 'P') || (name[2] != '.')) - { - return -RT_EINVAL; - } - - if ((name[1] >= 'A') && (name[1] <= 'Z')) - { - hw_port_num = (int)(name[1] - 'A'); - } - else - { - return -RT_EINVAL; - } - - for (i = 3; i < name_len; i++) - { - hw_pin_num *= 10; - hw_pin_num += name[i] - '0'; - } - - pin = PIN_NUM(hw_port_num, hw_pin_num); - - return pin; -} - -static void gd32_pin_write(rt_device_t dev, rt_base_t pin, rt_base_t value) -{ - GPIO_TypeDef *gpio_port; - uint16_t gpio_pin; - - if (PIN_PORT(pin) < PIN_GDPORT_MAX) - { - gpio_port = PIN_GDPORT(pin); - gpio_pin = PIN_GDPIN(pin); - - GPIO_WriteBit(gpio_port, gpio_pin, (BitState)value); - } -} - -static int gd32_pin_read(rt_device_t dev, rt_base_t pin) -{ - GPIO_TypeDef *gpio_port; - uint16_t gpio_pin; - int value = PIN_LOW; - - if (PIN_PORT(pin) < PIN_GDPORT_MAX) - { - gpio_port = PIN_GDPORT(pin); - gpio_pin = PIN_GDPIN(pin); - value = GPIO_ReadInputBit(gpio_port, gpio_pin); - } - - return value; -} - -static void gd32_pin_mode(rt_device_t dev, rt_base_t pin, rt_base_t mode) -{ - GPIO_InitPara GPIO_InitStruct = {0}; - - if (PIN_PORT(pin) >= PIN_GDPORT_MAX) - { - return; - } - - /* Configure GPIO_InitStructure */ - GPIO_InitStruct.GPIO_Pin = PIN_GDPIN(pin); - GPIO_InitStruct.GPIO_Speed = GPIO_SPEED_2MHZ; - GPIO_InitStruct.GPIO_Mode = GPIO_MODE_IN_FLOATING; - - switch (mode) - { - case PIN_MODE_OUTPUT: - GPIO_InitStruct.GPIO_Mode = GPIO_MODE_OUT_PP; - break; - case PIN_MODE_INPUT: - GPIO_InitStruct.GPIO_Mode = GPIO_MODE_IN_FLOATING; - break; - case PIN_MODE_INPUT_PULLUP: - GPIO_InitStruct.GPIO_Mode = GPIO_MODE_IPD; - break; - case PIN_MODE_INPUT_PULLDOWN: - GPIO_InitStruct.GPIO_Mode = GPIO_MODE_IPU; - break; - case PIN_MODE_OUTPUT_OD: - GPIO_InitStruct.GPIO_Mode = GPIO_MODE_OUT_OD; - break; - default: - break; - } - - GPIO_Init(PIN_GDPORT(pin), &GPIO_InitStruct); -} - -rt_inline rt_int32_t bit2bitno(rt_uint32_t bit) -{ - int i; - for (i = 0; i < 32; i++) - { - if ((0x01 << i) == bit) - { - return i; - } - } - return -1; -} - -rt_inline const struct pin_irq_map *get_pin_irq_map(uint32_t pinbit) -{ - rt_int32_t mapindex = bit2bitno(pinbit); - if (mapindex < 0 || mapindex >= ITEM_NUM(pin_irq_map)) - { - return RT_NULL; - } - return &pin_irq_map[mapindex]; -}; - -static rt_err_t gd32_pin_attach_irq(struct rt_device *device, rt_int32_t pin, - rt_uint32_t mode, void (*hdr)(void *args), void *args) -{ - rt_base_t level; - rt_int32_t irqindex = -1; - - if (PIN_PORT(pin) >= PIN_GDPORT_MAX) - { - return -RT_ENOSYS; - } - - irqindex = bit2bitno(PIN_GDPIN(pin)); - if (irqindex < 0 || irqindex >= ITEM_NUM(pin_irq_map)) - { - return RT_ENOSYS; - } - - level = rt_hw_interrupt_disable(); - if (pin_irq_hdr_tab[irqindex].pin == pin && - pin_irq_hdr_tab[irqindex].hdr == hdr && - pin_irq_hdr_tab[irqindex].mode == mode && - pin_irq_hdr_tab[irqindex].args == args) - { - rt_hw_interrupt_enable(level); - return RT_EOK; - } - if (pin_irq_hdr_tab[irqindex].pin != -1) - { - rt_hw_interrupt_enable(level); - return RT_EBUSY; - } - pin_irq_hdr_tab[irqindex].pin = pin; - pin_irq_hdr_tab[irqindex].hdr = hdr; - pin_irq_hdr_tab[irqindex].mode = mode; - pin_irq_hdr_tab[irqindex].args = args; - rt_hw_interrupt_enable(level); - - return RT_EOK; -} - -static rt_err_t gd32_pin_dettach_irq(struct rt_device *device, rt_int32_t pin) -{ - rt_base_t level; - rt_int32_t irqindex = -1; - - if (PIN_PORT(pin) >= PIN_GDPORT_MAX) - { - return -RT_ENOSYS; - } - - irqindex = bit2bitno(PIN_GDPIN(pin)); - if (irqindex < 0 || irqindex >= ITEM_NUM(pin_irq_map)) - { - return RT_ENOSYS; - } - - level = rt_hw_interrupt_disable(); - if (pin_irq_hdr_tab[irqindex].pin == -1) - { - rt_hw_interrupt_enable(level); - return RT_EOK; - } - pin_irq_hdr_tab[irqindex].pin = -1; - pin_irq_hdr_tab[irqindex].hdr = RT_NULL; - pin_irq_hdr_tab[irqindex].mode = 0; - pin_irq_hdr_tab[irqindex].args = RT_NULL; - rt_hw_interrupt_enable(level); - - return RT_EOK; -} - -static rt_err_t gd32_pin_irq_enable(struct rt_device *device, rt_base_t pin, - rt_uint32_t enabled) -{ - const struct pin_irq_map *irqmap; - rt_base_t level; - rt_int32_t irqindex = -1; - GPIO_InitPara GPIO_InitStruct = {0}; - EXTI_InitPara EXTI_InitParaStruct = {0}; - - if (PIN_PORT(pin) >= PIN_GDPORT_MAX) - { - return -RT_ENOSYS; - } - - GPIO_InitStruct.GPIO_Pin = PIN_GDPIN(pin); - EXTI_InitParaStruct.EXTI_LINE = PIN_GDPIN(pin); - EXTI_InitParaStruct.EXTI_Mode = EXTI_Mode_Interrupt; - if (enabled == PIN_IRQ_ENABLE) - { - irqindex = bit2bitno(PIN_GDPIN(pin)); - if (irqindex < 0 || irqindex >= ITEM_NUM(pin_irq_map)) - { - return RT_ENOSYS; - } - - level = rt_hw_interrupt_disable(); - - if (pin_irq_hdr_tab[irqindex].pin == -1) - { - rt_hw_interrupt_enable(level); - return RT_ENOSYS; - } - - irqmap = &pin_irq_map[irqindex]; - - /* Configure GPIO_InitStructure */ - GPIO_InitStruct.GPIO_Speed = GPIO_SPEED_10MHZ; - GPIO_InitStruct.GPIO_Mode = GPIO_MODE_IN_FLOATING; - - EXTI_InitParaStruct.EXTI_LINEEnable = ENABLE; - GPIO_EXTILineConfig(PIN_PORT(pin), PIN_NO(pin)); - switch (pin_irq_hdr_tab[irqindex].mode) - { - case PIN_IRQ_MODE_RISING: - EXTI_InitParaStruct.EXTI_Trigger = EXTI_Trigger_Rising; - GPIO_InitStruct.GPIO_Mode = GPIO_MODE_IPD; - EXTI_Init(&EXTI_InitParaStruct); - break; - case PIN_IRQ_MODE_FALLING: - GPIO_InitStruct.GPIO_Mode = GPIO_MODE_IPU; - EXTI_InitParaStruct.EXTI_Trigger = EXTI_Trigger_Falling; - EXTI_Init(&EXTI_InitParaStruct); - break; - case PIN_IRQ_MODE_RISING_FALLING: - EXTI_InitParaStruct.EXTI_Trigger = EXTI_Trigger_Rising_Falling; - EXTI_Init(&EXTI_InitParaStruct); - break; - default: - break; - } - GPIO_Init(PIN_GDPORT(pin), &GPIO_InitStruct); - - NVIC_SetPriority(irqmap->irqno, 0); - NVIC_EnableIRQ(irqmap->irqno); - pin_irq_enable_mask |= irqmap->pinbit; - - rt_hw_interrupt_enable(level); - } - else if (enabled == PIN_IRQ_DISABLE) - { - irqmap = get_pin_irq_map(PIN_GDPIN(pin)); - if (irqmap == RT_NULL) - { - return RT_ENOSYS; - } - - level = rt_hw_interrupt_disable(); - - EXTI_InitParaStruct.EXTI_LINEEnable = DISABLE; - EXTI_Init(&EXTI_InitParaStruct); - - pin_irq_enable_mask &= ~irqmap->pinbit; - if ((irqmap->pinbit >= GPIO_PIN_5) && (irqmap->pinbit <= GPIO_PIN_9)) - { - if (!(pin_irq_enable_mask & (GPIO_PIN_5 | GPIO_PIN_6 | GPIO_PIN_7 | GPIO_PIN_8 | GPIO_PIN_9))) - { - NVIC_DisableIRQ(irqmap->irqno); - } - } - else if ((irqmap->pinbit >= GPIO_PIN_10) && (irqmap->pinbit <= GPIO_PIN_15)) - { - if (!(pin_irq_enable_mask & (GPIO_PIN_10 | GPIO_PIN_11 | GPIO_PIN_12 | GPIO_PIN_13 | GPIO_PIN_14 | GPIO_PIN_15))) - { - NVIC_DisableIRQ(irqmap->irqno); - } - } - else - { - NVIC_DisableIRQ(irqmap->irqno); - } - rt_hw_interrupt_enable(level); - } - else - { - return -RT_ENOSYS; - } - - return RT_EOK; -} -const static struct rt_pin_ops _gd32_pin_ops = -{ - gd32_pin_mode, - gd32_pin_write, - gd32_pin_read, - gd32_pin_attach_irq, - gd32_pin_dettach_irq, - gd32_pin_irq_enable, - gd32_pin_get, -}; - -rt_inline void pin_irq_hdr(int irqno) -{ - if (pin_irq_hdr_tab[irqno].hdr) - { - pin_irq_hdr_tab[irqno].hdr(pin_irq_hdr_tab[irqno].args); - } -} - -/** - * @brief This function handles EXTI interrupt request. - * @param gpio_pin: Specifies the pins connected EXTI line - * @retval none - */ -void gd32_pin_exti_irqhandler(uint16_t gpio_pin) -{ - if (SET == EXTI_GetIntBitState(gpio_pin)) - { - EXTI_ClearIntBitState(gpio_pin); - pin_irq_hdr(bit2bitno(gpio_pin)); - } -} - -void EXTI0_IRQHandler(void) -{ - rt_interrupt_enter(); - gd32_pin_exti_irqhandler(GPIO_PIN_0); - rt_interrupt_leave(); -} - -void EXTI1_IRQHandler(void) -{ - rt_interrupt_enter(); - gd32_pin_exti_irqhandler(GPIO_PIN_1); - rt_interrupt_leave(); -} - -void EXTI2_IRQHandler(void) -{ - rt_interrupt_enter(); - gd32_pin_exti_irqhandler(GPIO_PIN_2); - rt_interrupt_leave(); -} - -void EXTI3_IRQHandler(void) -{ - rt_interrupt_enter(); - gd32_pin_exti_irqhandler(GPIO_PIN_3); - rt_interrupt_leave(); -} - -void EXTI4_IRQHandler(void) -{ - rt_interrupt_enter(); - gd32_pin_exti_irqhandler(GPIO_PIN_4); - rt_interrupt_leave(); -} - -void EXTI5_9_IRQHandler(void) -{ - rt_interrupt_enter(); - gd32_pin_exti_irqhandler(GPIO_PIN_5); - gd32_pin_exti_irqhandler(GPIO_PIN_6); - gd32_pin_exti_irqhandler(GPIO_PIN_7); - gd32_pin_exti_irqhandler(GPIO_PIN_8); - gd32_pin_exti_irqhandler(GPIO_PIN_9); - rt_interrupt_leave(); -} - -void EXTI10_15_IRQHandler(void) -{ - rt_interrupt_enter(); - gd32_pin_exti_irqhandler(GPIO_PIN_10); - gd32_pin_exti_irqhandler(GPIO_PIN_11); - gd32_pin_exti_irqhandler(GPIO_PIN_12); - gd32_pin_exti_irqhandler(GPIO_PIN_13); - gd32_pin_exti_irqhandler(GPIO_PIN_14); - gd32_pin_exti_irqhandler(GPIO_PIN_15); - rt_interrupt_leave(); -} - -int rt_hw_pin_init(void) -{ -#if defined(GPIOG) - rcu_periph_clock_enable(RCU_GPIOG); -#endif -#if defined(GPIOF) - rcu_periph_clock_enable(RCU_GPIOF); -#endif -#if defined(GPIOE) - rcu_periph_clock_enable(RCU_GPIOE); -#endif -#if defined(GPIOD) - rcu_periph_clock_enable(RCU_GPIOD); -#endif -#if defined(GPIOC) - rcu_periph_clock_enable(RCU_GPIOC); -#endif -#if defined(GPIOB) - rcu_periph_clock_enable(RCU_GPIOB); -#endif -#if defined(GPIOA) - rcu_periph_clock_enable(RCU_GPIOA); -#endif - rcu_periph_clock_enable(RCU_AF); - return rt_device_pin_register("pin", &_gd32_pin_ops, RT_NULL); -} -INIT_BOARD_EXPORT(rt_hw_pin_init); -#endif /* RT_USING_PIN */ - diff --git a/bsp/gd32103c-eval/drivers/drv_gpio.h b/bsp/gd32103c-eval/drivers/drv_gpio.h deleted file mode 100644 index 34d30d63d4..0000000000 --- a/bsp/gd32103c-eval/drivers/drv_gpio.h +++ /dev/null @@ -1,45 +0,0 @@ -/* - * Copyright (c) 2006-2021, RT-Thread Development Team - * - * SPDX-License-Identifier: Apache-2.0 - * - * Change Logs: - * Date Author Notes - * 2020-12-27 iysheng first release - */ - -#ifndef __DRV_GPIO_H__ -#define __DRV_GPIO_H__ - -#include <rtthread.h> -#include <rthw.h> -#include <rtdevice.h> -#include <board.h> - -#ifdef __cplusplus -extern "C" { -#endif - -#define __GD32_PORT(port) GPIO##port##_BASE - -#define GET_PIN(PORTx,PIN) (rt_base_t)((16 * ( ((rt_base_t)__GD32_PORT(PORTx) - (rt_base_t)GPIOA_BASE)/(0x0400UL) )) + PIN) - -#define PIN_NUM(port, no) (((((port) & 0xFu) << 4) | ((no) & 0xFu))) -#define PIN_PORT(pin) ((uint8_t)(((pin) >> 4) & 0xFu)) -#define PIN_NO(pin) ((uint8_t)((pin) & 0xFu)) - -#define PIN_GDPORT(pin) ((GPIO_TypeDef *)(GPIOA_BASE + (0x400u * PIN_PORT(pin)))) -#define PIN_GDPIN(pin) ((uint16_t)(1u << PIN_NO(pin))) - -struct pin_irq_map -{ - rt_uint16_t pinbit; - IRQn_Type irqno; -}; - -#ifdef __cplusplus -} -#endif - -#endif /* __DRV_GPIO_H__ */ - diff --git a/bsp/gd32103c-eval/drivers/drv_hwtimer.h b/bsp/gd32103c-eval/drivers/drv_hwtimer.h deleted file mode 100644 index 1b1a7e7da9..0000000000 --- a/bsp/gd32103c-eval/drivers/drv_hwtimer.h +++ /dev/null @@ -1,38 +0,0 @@ -/* - * Copyright (c) 2006-2021, RT-Thread Development Team - * - * SPDX-License-Identifier: Apache-2.0 - * - * Change Logs: - * Date Author Notes - * 2021-01-15 iysheng first release - */ - -#ifndef __DRV_HWTIMER_H__ -#define __DRV_HWTIMER_H__ - -#ifdef __cplusplus -extern "C" { -#endif - -#include <drivers/hwtimer.h> - -typedef struct { - TIMER_TypeDef *reg_base; - IRQn_Type irqn; - rcu_periph_enum rcu; -} gd32_hwtimer_data; - -typedef struct { - char dev_name[RT_NAME_MAX]; - const gd32_hwtimer_data hw_data; - rt_hwtimer_t hwtimer_dev; - const struct rt_hwtimer_info hwtimer_info; -} gd32_hwtimer_device; - -#ifdef __cplusplus -} -#endif - -#endif /* __DRV_HWTIMER_H__ */ - diff --git a/bsp/gd32103c-eval/drivers/drv_usart.c b/bsp/gd32103c-eval/drivers/drv_usart.c deleted file mode 100644 index c89ce02e0c..0000000000 --- a/bsp/gd32103c-eval/drivers/drv_usart.c +++ /dev/null @@ -1,358 +0,0 @@ -/* - * Copyright (c) 2006-2021, RT-Thread Development Team - * - * SPDX-License-Identifier: Apache-2.0 - * - * Change Logs: - * Date Author Notes - * 2021-01-04 iysheng first version - */ - -#include <gd32f10x.h> -#include <drv_usart.h> -#include <board.h> - -#ifdef RT_USING_SERIAL - -#if !defined(BSP_USING_UART0) && !defined(BSP_USING_UART1) && \ - !defined(BSP_USING_UART2) && !defined(BSP_USING_UART3) && \ - !defined(BSP_USING_UART4) - #error "Please define at least one UARTx" - -#endif - -#include <rtdevice.h> - -static void uart_isr(struct rt_serial_device *serial); - -#if defined(BSP_USING_UART0) -struct rt_serial_device serial0; - -void USART0_IRQHandler(void) -{ - /* enter interrupt */ - rt_interrupt_enter(); - - uart_isr(&serial0); - - /* leave interrupt */ - rt_interrupt_leave(); -} - -#endif /* BSP_USING_UART0 */ - -#if defined(BSP_USING_UART1) -struct rt_serial_device serial1; - -void USART1_IRQHandler(void) -{ - /* enter interrupt */ - rt_interrupt_enter(); - - uart_isr(&serial1); - - /* leave interrupt */ - rt_interrupt_leave(); -} - -#endif /* BSP_USING_UART1 */ - -#if defined(BSP_USING_UART2) -struct rt_serial_device serial2; - -void USART2_IRQHandler(void) -{ - /* enter interrupt */ - rt_interrupt_enter(); - - uart_isr(&serial2); - - /* leave interrupt */ - rt_interrupt_leave(); -} - -#endif /* BSP_USING_UART2 */ - -#if defined(BSP_USING_UART3) -struct rt_serial_device serial3; - -void UART3_IRQHandler(void) -{ - /* enter interrupt */ - rt_interrupt_enter(); - - uart_isr(&serial3); - - /* leave interrupt */ - rt_interrupt_leave(); -} - -#endif /* BSP_USING_UART3 */ - -#if defined(BSP_USING_UART4) -struct rt_serial_device serial4; - -void UART4_IRQHandler(void) -{ - /* enter interrupt */ - rt_interrupt_enter(); - - uart_isr(&serial4); - - /* leave interrupt */ - rt_interrupt_leave(); -} -#endif /* BSP_USING_UART4 */ - -static const struct gd32_uart uarts[] = { -#ifdef BSP_USING_UART0 - { - USART0, /* uart peripheral index */ - USART0_IRQn, /* uart iqrn */ - RCU_USART0, RCU_GPIOA, RCU_GPIOA, /* periph clock, tx gpio clock, rt gpio clock */ - GPIOA, GPIOA, /* tx port, tx alternate, tx pin */ - GPIO_PIN_9, GPIO_PIN_10, /* rx port, rx alternate, rx pin */ - &serial0, - "uart0", - }, -#endif - -#ifdef BSP_USING_UART1 - { - USART1, /* uart peripheral index */ - USART1_IRQn, /* uart iqrn */ - RCU_USART1, RCU_GPIOA, RCU_GPIOA, /* periph clock, tx gpio clock, rt gpio clock */ - GPIOA, GPIOA, /* tx port, tx alternate, tx pin */ - GPIO_PIN_2, GPIO_PIN_3, /* rx port, rx alternate, rx pin */ - &serial1, - "uart1", - }, -#endif - -#ifdef BSP_USING_UART2 - { - USART2, /* uart peripheral index */ - USART2_IRQn, /* uart iqrn */ - RCU_USART2, RCU_GPIOB, RCU_GPIOB, /* periph clock, tx gpio clock, rt gpio clock */ - GPIOB, GPIOB, /* tx port, tx alternate, tx pin */ - GPIO_PIN_10, GPIO_PIN_11, /* rx port, rx alternate, rx pin */ - &serial2, - "uart2", - }, -#endif - -#ifdef BSP_USING_UART3 - { - UART3, /* uart peripheral index */ - UART3_IRQn, /* uart iqrn */ - RCU_UART3, RCU_GPIOC, RCU_GPIOC, /* periph clock, tx gpio clock, rt gpio clock */ - GPIOC, GPIOC, /* tx port, tx alternate, tx pin */ - GPIO_PIN_10, GPIO_PIN_11, /* rx port, rx alternate, rx pin */ - &serial3, - "uart3", - }, -#endif - -#ifdef BSP_USING_UART4 - { - UART4, /* uart peripheral index */ - UART4_IRQn, /* uart iqrn */ - RCU_UART4, RCU_GPIOC, RCU_GPIOD, /* periph clock, tx gpio clock, rt gpio clock */ - GPIOC, GPIOD, /* tx port, tx alternate, tx pin */ - GPIO_PIN_12, GPIO_PIN_2, /* rx port, rx alternate, rx pin */ - &serial4, - "uart4", - }, -#endif -}; - -/** -* @brief UART MSP Initialization -* This function configures the hardware resources used in this example: -* - Peripheral's clock enable -* - Peripheral's GPIO Configuration -* - NVIC configuration for UART interrupt request enable -* @param huart: UART handle pointer -* @retval None -*/ -void gd32_uart_gpio_init(struct gd32_uart *uart) -{ - GPIO_TypeDef *GPIOx; - GPIO_InitPara GPIO_InitStructure = {0}; - /* enable USART clock */ - rcu_periph_clock_enable(uart->tx_gpio_clk); - rcu_periph_clock_enable(uart->rx_gpio_clk); - rcu_periph_clock_enable(uart->per_clk); - - GPIOx = (GPIO_TypeDef *)uart->tx_port; - GPIO_InitStructure.GPIO_Pin = uart->tx_pin; - GPIO_InitStructure.GPIO_Mode = GPIO_MODE_AF_PP; - GPIO_InitStructure.GPIO_Speed = GPIO_SPEED_10MHZ; - GPIO_Init(GPIOx, &GPIO_InitStructure); - /* TODO 初始化 RX */ - GPIOx = (GPIO_TypeDef *)uart->rx_port; - GPIO_InitStructure.GPIO_Pin = uart->rx_pin; - GPIO_InitStructure.GPIO_Mode = GPIO_MODE_IN_FLOATING; - GPIO_InitStructure.GPIO_Speed = GPIO_SPEED_10MHZ; - GPIO_Init(GPIOx, &GPIO_InitStructure); - - NVIC_SetPriority(uart->irqn, 0); - NVIC_EnableIRQ(uart->irqn); -} - -static rt_err_t gd32_configure(struct rt_serial_device *serial, struct serial_configure *cfg) -{ - struct gd32_uart *uart; - USART_TypeDef *USARTx; - USART_InitPara USART_InitParaStruct = {0}; - - RT_ASSERT(serial != RT_NULL); - RT_ASSERT(cfg != RT_NULL); - - uart = (struct gd32_uart *)serial->parent.user_data; - gd32_uart_gpio_init(uart); - - USARTx = (USART_TypeDef *)uart->uart_periph; - USART_InitParaStruct.USART_BRR = cfg->baud_rate; - - switch (cfg->data_bits) { - case DATA_BITS_9: - USART_InitParaStruct.USART_WL = USART_WL_9B; - break; - - default: - USART_InitParaStruct.USART_WL = USART_WL_8B; - break; - } - - switch (cfg->stop_bits) { - case STOP_BITS_2: - USART_InitParaStruct.USART_STBits = USART_STBITS_2; - break; - default: - USART_InitParaStruct.USART_STBits = USART_STBITS_1; - break; - } - - switch (cfg->parity) { - case PARITY_ODD: - USART_InitParaStruct.USART_Parity = USART_PARITY_SETODD; - break; - case PARITY_EVEN: - USART_InitParaStruct.USART_Parity = USART_PARITY_SETEVEN; - break; - default: - USART_InitParaStruct.USART_Parity = USART_PARITY_RESET; - break; - } - - USART_InitParaStruct.USART_HardwareFlowControl = USART_HARDWAREFLOWCONTROL_NONE; - USART_InitParaStruct.USART_RxorTx = USART_RXORTX_RX | USART_RXORTX_TX; - USART_Init(USARTx, &USART_InitParaStruct); - USART_Enable(USARTx, ENABLE); - - return RT_EOK; -} - -static rt_err_t gd32_control(struct rt_serial_device *serial, int cmd, void *arg) -{ - struct gd32_uart *uart; - USART_TypeDef *USARTx; - - RT_ASSERT(serial != RT_NULL); - uart = (struct gd32_uart *)serial->parent.user_data; - USARTx = (USART_TypeDef *)uart->uart_periph; - - switch (cmd) { - case RT_DEVICE_CTRL_CLR_INT: - /* disable rx irq */ - NVIC_DisableIRQ(uart->irqn); - /* disable interrupt */ - USART_INT_Set(USARTx, USART_INT_RBNE, DISABLE); - break; - case RT_DEVICE_CTRL_SET_INT: - /* enable rx irq */ - NVIC_EnableIRQ(uart->irqn); - /* enable interrupt */ - USART_INT_Set(USARTx, USART_INT_RBNE, ENABLE); - break; - } - - return RT_EOK; -} - -static int gd32_putc(struct rt_serial_device *serial, char ch) -{ - struct gd32_uart *uart; - - RT_ASSERT(serial != RT_NULL); - uart = (struct gd32_uart *)serial->parent.user_data; - - - USART_DataSend((USART_TypeDef *)uart->uart_periph, ch); - while ((USART_GetBitState(uart->uart_periph, USART_FLAG_TC) == RESET)); - - return 1; -} - -static int gd32_getc(struct rt_serial_device *serial) -{ - int ch; - struct gd32_uart *uart; - - RT_ASSERT(serial != RT_NULL); - uart = (struct gd32_uart *)serial->parent.user_data; - - ch = -1; - if (USART_GetBitState(uart->uart_periph, USART_FLAG_RBNE) != RESET) - ch = USART_DataReceive(uart->uart_periph); - return ch; -} - -/** - * Uart common interrupt process. This need add to uart ISR. - * - * @param serial serial device - */ -static void uart_isr(struct rt_serial_device *serial) -{ - struct gd32_uart *uart = (struct gd32_uart *) serial->parent.user_data; - - RT_ASSERT(uart != RT_NULL); - - if ((USART_GetIntBitState((USART_TypeDef *)uart->uart_periph, USART_INT_RBNE) != RESET) && - (USART_GetBitState((USART_TypeDef *)uart->uart_periph, USART_FLAG_RBNE) != RESET)) { - rt_hw_serial_isr(serial, RT_SERIAL_EVENT_RX_IND); - /* Clear RXNE interrupt flag */ - USART_ClearBitState(uart->uart_periph, USART_FLAG_RBNE); - } -} - -static const struct rt_uart_ops gd32_uart_ops = { - gd32_configure, - gd32_control, - gd32_putc, - gd32_getc, -}; - -int gd32_hw_usart_init(void) -{ - struct serial_configure config = RT_SERIAL_CONFIG_DEFAULT; - int i; - - - for (i = 0; i < sizeof(uarts) / sizeof(uarts[0]); i++) { - uarts[i].serial->ops = &gd32_uart_ops; - uarts[i].serial->config = config; - - /* register UART device */ - rt_hw_serial_register(uarts[i].serial, - uarts[i].device_name, - RT_DEVICE_FLAG_RDWR | RT_DEVICE_FLAG_INT_RX, - (void *)&uarts[i]); - } - - return 0; -} -INIT_BOARD_EXPORT(gd32_hw_usart_init); -#endif diff --git a/bsp/gd32103c-eval/drivers/drv_usart.h b/bsp/gd32103c-eval/drivers/drv_usart.h deleted file mode 100644 index ad3455db60..0000000000 --- a/bsp/gd32103c-eval/drivers/drv_usart.h +++ /dev/null @@ -1,33 +0,0 @@ -/* - * Copyright (c) 2006-2021, RT-Thread Development Team - * - * SPDX-License-Identifier: Apache-2.0 - * - * Change Logs: - * Date Author Notes - * 2021-01-04 iysheng first version - */ - -#ifndef __USART_H__ -#define __USART_H__ - -#include <rthw.h> -#include <rtthread.h> - -/* GD32 uart driver */ -struct gd32_uart { - USART_TypeDef * uart_periph; - IRQn_Type irqn; - rcu_periph_enum per_clk; - rcu_periph_enum tx_gpio_clk; - rcu_periph_enum rx_gpio_clk; - GPIO_TypeDef * tx_port; - GPIO_TypeDef * rx_port; - uint16_t tx_pin; - uint16_t rx_pin; - - struct rt_serial_device *serial; - char *device_name; -}; - -#endif diff --git a/bsp/gd32103c-eval/gd32_rom.ld b/bsp/gd32103c-eval/gd32_rom.ld deleted file mode 100644 index 875d239e58..0000000000 --- a/bsp/gd32103c-eval/gd32_rom.ld +++ /dev/null @@ -1,146 +0,0 @@ -/* - * linker script for GD32F1xx with GNU ld - * - * Change Logs: - * Date Author Notes - * 2009-10-14 bernard.xiong first implementation - * 2021-01-02 iysheng modify to suite gd32f103c - */ - -/* Program Entry, set to mark it as "used" and avoid gc */ -MEMORY -{ - CODE (rx) : ORIGIN = 0x08000000, LENGTH = 256k /* 256KB flash */ - DATA (rw) : ORIGIN = 0x20000000, LENGTH = 48k /* 48KB sram */ -} -ENTRY(Reset_Handler) -_system_stack_size = 0x200; - -SECTIONS -{ - .text : - { - . = ALIGN(4); - _stext = .; - KEEP(*(.isr_vector)) /* Startup code */ - . = ALIGN(4); - *(.text) /* remaining code */ - *(.text.*) /* remaining code */ - *(.rodata) /* read-only data (constants) */ - *(.rodata*) - *(.glue_7) - *(.glue_7t) - *(.gnu.linkonce.t*) - - /* section information for finsh shell */ - . = ALIGN(4); - __fsymtab_start = .; - KEEP(*(FSymTab)) - __fsymtab_end = .; - . = ALIGN(4); - __vsymtab_start = .; - KEEP(*(VSymTab)) - __vsymtab_end = .; - . = ALIGN(4); - - /* section information for initial. */ - . = ALIGN(4); - __rt_init_start = .; - KEEP(*(SORT(.rti_fn*))) - __rt_init_end = .; - . = ALIGN(4); - - . = ALIGN(4); - _etext = .; - } > CODE = 0 - - /* .ARM.exidx is sorted, so has to go in its own output section. */ - __exidx_start = .; - .ARM.exidx : - { - *(.ARM.exidx* .gnu.linkonce.armexidx.*) - - /* This is used by the startup in order to initialize the .data secion */ - _sidata = .; - } > CODE - __exidx_end = .; - - /* .data section which is used for initialized data */ - - .data : AT (_sidata) - { - . = ALIGN(4); - /* This is used by the startup in order to initialize the .data secion */ - _sdata = . ; - - *(.data) - *(.data.*) - *(.gnu.linkonce.d*) - - . = ALIGN(4); - /* This is used by the startup in order to initialize the .data secion */ - _edata = . ; - } >DATA - - .stack : - { - . = . + _system_stack_size; - . = ALIGN(4); - _estack = .; - } >DATA - - __bss_start = .; - .bss : - { - . = ALIGN(4); - /* This is used by the startup in order to initialize the .bss secion */ - _sbss = .; - - *(.bss) - *(.bss.*) - *(COMMON) - - . = ALIGN(4); - /* This is used by the startup in order to initialize the .bss secion */ - _ebss = . ; - - *(.bss.init) - } > DATA - __bss_end = .; - - _end = .; - - /* Stabs debugging sections. */ - .stab 0 : { *(.stab) } - .stabstr 0 : { *(.stabstr) } - .stab.excl 0 : { *(.stab.excl) } - .stab.exclstr 0 : { *(.stab.exclstr) } - .stab.index 0 : { *(.stab.index) } - .stab.indexstr 0 : { *(.stab.indexstr) } - .comment 0 : { *(.comment) } - /* DWARF debug sections. - * Symbols in the DWARF debugging sections are relative to the beginning - * of the section so we begin them at 0. */ - /* DWARF 1 */ - .debug 0 : { *(.debug) } - .line 0 : { *(.line) } - /* GNU DWARF 1 extensions */ - .debug_srcinfo 0 : { *(.debug_srcinfo) } - .debug_sfnames 0 : { *(.debug_sfnames) } - /* DWARF 1.1 and DWARF 2 */ - .debug_aranges 0 : { *(.debug_aranges) } - .debug_pubnames 0 : { *(.debug_pubnames) } - /* DWARF 2 */ - .debug_info 0 : { *(.debug_info .gnu.linkonce.wi.*) } - .debug_abbrev 0 : { *(.debug_abbrev) } - .debug_line 0 : { *(.debug_line) } - .debug_frame 0 : { *(.debug_frame) } - .debug_str 0 : { *(.debug_str) } - .debug_loc 0 : { *(.debug_loc) } - .debug_macinfo 0 : { *(.debug_macinfo) } - /* SGI/MIPS DWARF 2 extensions */ - .debug_weaknames 0 : { *(.debug_weaknames) } - .debug_funcnames 0 : { *(.debug_funcnames) } - .debug_typenames 0 : { *(.debug_typenames) } - .debug_varnames 0 : { *(.debug_varnames) } -} diff --git a/bsp/gd32103c-eval/rtconfig.h b/bsp/gd32103c-eval/rtconfig.h deleted file mode 100644 index 8f2fc9739e..0000000000 --- a/bsp/gd32103c-eval/rtconfig.h +++ /dev/null @@ -1,208 +0,0 @@ -#ifndef RT_CONFIG_H__ -#define RT_CONFIG_H__ - -/* Automatically generated file; DO NOT EDIT. */ -/* RT-Thread Configuration */ - -/* RT-Thread Kernel */ - -#define RT_NAME_MAX 8 -#define RT_ALIGN_SIZE 4 -#define RT_THREAD_PRIORITY_32 -#define RT_THREAD_PRIORITY_MAX 32 -#define RT_TICK_PER_SECOND 100 -#define RT_USING_OVERFLOW_CHECK -#define RT_USING_HOOK -#define RT_HOOK_USING_FUNC_PTR -#define RT_USING_IDLE_HOOK -#define RT_IDLE_HOOK_LIST_SIZE 4 -#define IDLE_THREAD_STACK_SIZE 256 -#define RT_USING_TIMER_SOFT -#define RT_TIMER_THREAD_PRIO 4 -#define RT_TIMER_THREAD_STACK_SIZE 512 - -/* kservice optimization */ - -#define RT_DEBUG - -/* Inter-Thread communication */ - -#define RT_USING_SEMAPHORE -#define RT_USING_MUTEX -#define RT_USING_EVENT -#define RT_USING_MAILBOX -#define RT_USING_MESSAGEQUEUE - -/* Memory Management */ - -#define RT_USING_MEMPOOL -#define RT_USING_SMALL_MEM -#define RT_USING_SMALL_MEM_AS_HEAP -#define RT_USING_HEAP - -/* Kernel Device Object */ - -#define RT_USING_DEVICE -#define RT_USING_CONSOLE -#define RT_CONSOLEBUF_SIZE 128 -#define RT_CONSOLE_DEVICE_NAME "uart0" -#define RT_VER_NUM 0x40100 - -/* RT-Thread Components */ - -#define RT_USING_COMPONENTS_INIT -#define RT_USING_USER_MAIN -#define RT_MAIN_THREAD_STACK_SIZE 2048 -#define RT_MAIN_THREAD_PRIORITY 10 - -/* C++ features */ - - -/* Command shell */ - -#define RT_USING_FINSH -#define RT_USING_MSH -#define FINSH_USING_MSH -#define FINSH_THREAD_NAME "tshell" -#define FINSH_THREAD_PRIORITY 20 -#define FINSH_THREAD_STACK_SIZE 4096 -#define FINSH_USING_HISTORY -#define FINSH_HISTORY_LINES 5 -#define FINSH_USING_SYMTAB -#define FINSH_CMD_SIZE 80 -#define MSH_USING_BUILT_IN_COMMANDS -#define FINSH_USING_DESCRIPTION -#define FINSH_ARG_MAX 10 - -/* Device virtual file system */ - -#define RT_USING_DFS -#define DFS_USING_POSIX -#define DFS_USING_WORKDIR -#define DFS_FILESYSTEMS_MAX 2 -#define DFS_FILESYSTEM_TYPES_MAX 2 -#define DFS_FD_MAX 16 -#define RT_USING_DFS_DEVFS - -/* Device Drivers */ - -#define RT_USING_DEVICE_IPC -#define RT_USING_SERIAL -#define RT_USING_SERIAL_V1 -#define RT_SERIAL_USING_DMA -#define RT_SERIAL_RB_BUFSZ 64 -#define RT_USING_PIN - -/* Using USB */ - - -/* POSIX layer and C standard library */ - -#define RT_LIBC_DEFAULT_TIMEZONE 8 - -/* POSIX (Portable Operating System Interface) layer */ - - -/* Interprocess Communication (IPC) */ - - -/* Socket is in the 'Network' category */ - -/* Network */ - -/* Socket abstraction layer */ - - -/* Network interface device */ - - -/* light weight TCP/IP stack */ - - -/* AT commands */ - - -/* VBUS(Virtual Software BUS) */ - - -/* Utilities */ - - -/* RT-Thread Utestcases */ - - -/* RT-Thread online packages */ - -/* IoT - internet of things */ - - -/* Wi-Fi */ - -/* Marvell WiFi */ - - -/* Wiced WiFi */ - - -/* IoT Cloud */ - - -/* security packages */ - - -/* language packages */ - - -/* multimedia packages */ - -/* LVGL: powerful and easy-to-use embedded GUI library */ - - -/* u8g2: a monochrome graphic library */ - - -/* PainterEngine: A cross-platform graphics application framework written in C language */ - - -/* tools packages */ - - -/* system packages */ - -/* enhanced kernel services */ - - -/* POSIX extension functions */ - - -/* acceleration: Assembly language or algorithmic acceleration packages */ - - -/* CMSIS: ARM Cortex-M Microcontroller Software Interface Standard */ - - -/* Micrium: Micrium software products porting for RT-Thread */ - - -/* peripheral libraries and drivers */ - - -/* AI packages */ - - -/* miscellaneous packages */ - -/* samples: kernel and components samples */ - - -/* entertainment: terminal games and other interesting software packages */ - -#define SOC_SERIES_GD32F1 -#define SOC_GD32103C - -/* On-chip Peripheral Drivers */ - -#define BSP_USING_UART -#define BSP_USING_UART0 - -#endif diff --git a/bsp/gd32103c-eval/rtconfig.py b/bsp/gd32103c-eval/rtconfig.py deleted file mode 100644 index 7e8934c873..0000000000 --- a/bsp/gd32103c-eval/rtconfig.py +++ /dev/null @@ -1,126 +0,0 @@ -import os - -# toolchains options -ARCH='arm' -CPU='cortex-m3' -CROSS_TOOL='gcc' - -if os.getenv('RTT_CC'): - CROSS_TOOL = os.getenv('RTT_CC') - -# cross_tool provides the cross compiler -# EXEC_PATH is the compiler execute path, for example, CodeSourcery, Keil MDK, IAR -if CROSS_TOOL == 'gcc': - PLATFORM = 'gcc' - EXEC_PATH = r'D:/toolchain/gnu_tools_arm_embedded/5.4_2016q3/bin' -elif CROSS_TOOL == 'keil': - PLATFORM = 'armcc' - EXEC_PATH = r'C:/Keil_v5' -elif CROSS_TOOL == 'iar': - PLATFORM = 'iar' - EXEC_PATH = r'C:/Program Files (x86)/IAR Systems/Embedded Workbench 8.0' - -if os.getenv('RTT_EXEC_PATH'): - EXEC_PATH = os.getenv('RTT_EXEC_PATH') - -BUILD = 'debug' - -if PLATFORM == 'gcc': - # tool-chains - PREFIX = 'arm-none-eabi-' - CC = PREFIX + 'gcc' - AS = PREFIX + 'gcc' - AR = PREFIX + 'ar' - LINK = PREFIX + 'gcc' - TARGET_EXT = 'elf' - SIZE = PREFIX + 'size' - OBJDUMP = PREFIX + 'objdump' - OBJCPY = PREFIX + 'objcopy' - - DEVICE = ' -mcpu=cortex-m3 -mthumb -ffunction-sections -fdata-sections' - CFLAGS = DEVICE + ' -Dgcc' # -D' + PART_TYPE - AFLAGS = ' -c' + DEVICE + ' -x assembler-with-cpp -Wa,-mimplicit-it=thumb ' - LFLAGS = DEVICE + ' -Wl,--gc-sections,-Map=rtthread-gd32.map,-cref,-u,Reset_Handler -T gd32_rom.ld' - - CPATH = '' - LPATH = '' - - if BUILD == 'debug': - CFLAGS += ' -O0 -gdwarf-2 -g' - AFLAGS += ' -gdwarf-2' - else: - CFLAGS += ' -O2' - - POST_ACTION = OBJCPY + ' -O binary $TARGET rtthread.bin\n' + SIZE + ' $TARGET \n' - -elif PLATFORM == 'armcc': - # toolchains - CC = 'armcc' - AS = 'armasm' - AR = 'armar' - LINK = 'armlink' - TARGET_EXT = 'axf' - - DEVICE = ' --cpu Cortex-M4' - CFLAGS = DEVICE + ' --apcs=interwork' - AFLAGS = DEVICE - LFLAGS = DEVICE + ' --info sizes --info totals --info unused --info veneers --list rtthread-gd32.map --scatter gd32_rom.sct' - - LFLAGS += ' --keep *.o(.rti_fn.*) --keep *.o(FSymTab) --keep *.o(VSymTab)' - - EXEC_PATH += '/ARM/ARMCC/bin' - print(EXEC_PATH) - - CFLAGS += ' --c99' - - if BUILD == 'debug': - CFLAGS += ' -g -O0' - AFLAGS += ' -g' - else: - CFLAGS += ' -O2' - - POST_ACTION = 'fromelf --bin $TARGET --output rtthread.bin \nfromelf -z $TARGET' - -elif PLATFORM == 'iar': - # toolchains - CC = 'iccarm' - AS = 'iasmarm' - AR = 'iarchive' - LINK = 'ilinkarm' - TARGET_EXT = 'out' - - DEVICE = ' -D USE_STDPERIPH_DRIVER' + ' -D GD32F30X_HD' - - CFLAGS = DEVICE - CFLAGS += ' --diag_suppress Pa050' - CFLAGS += ' --no_cse' - CFLAGS += ' --no_unroll' - CFLAGS += ' --no_inline' - CFLAGS += ' --no_code_motion' - CFLAGS += ' --no_tbaa' - CFLAGS += ' --no_clustering' - CFLAGS += ' --no_scheduling' - CFLAGS += ' --debug' - CFLAGS += ' --endian=little' - CFLAGS += ' --cpu=Cortex-M4' - CFLAGS += ' -e' - CFLAGS += ' --fpu=None' - CFLAGS += ' --dlib_config "' + EXEC_PATH + '/arm/INC/c/DLib_Config_Normal.h"' - CFLAGS += ' -Ol' - CFLAGS += ' --use_c++_inline' - - AFLAGS = '' - AFLAGS += ' -s+' - AFLAGS += ' -w+' - AFLAGS += ' -r' - AFLAGS += ' --cpu Cortex-M4' - AFLAGS += ' --fpu None' - - LFLAGS = ' --config gd32_rom.icf' - LFLAGS += ' --redirect _Printf=_PrintfTiny' - LFLAGS += ' --redirect _Scanf=_ScanfSmall' - LFLAGS += ' --entry __iar_program_start' - - EXEC_PATH += '/arm/bin/' - POST_ACTION = '' - |