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diff --git a/bsp/smartfusion2/CMSIS/core_cm3.c b/bsp/smartfusion2/CMSIS/core_cm3.c new file mode 100644 index 0000000000..b8a357bf28 --- /dev/null +++ b/bsp/smartfusion2/CMSIS/core_cm3.c @@ -0,0 +1,810 @@ +/**************************************************************************//** + * @file core_cm3.c + * @brief CMSIS Cortex-M3 Core Peripheral Access Layer Source File + * @version V1.30 + * @date 30. October 2009 + * + * @note + * Copyright (C) 2009 ARM Limited. All rights reserved. + * + * @par + * ARM Limited (ARM) is supplying this software for use with Cortex-M + * processor based microcontrollers. This file can be freely distributed + * within development tools that are supporting such ARM based processors. + * + * @par + * THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED + * OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF + * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE. + * ARM SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR + * CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER. + * + ******************************************************************************/ +/******************************************************************************* + * Microsemi SoC Products Group SVN revision number for the purpose of tracking + * changes done to original file supplied by ARM: + * SVN $Revision: 6671 $ + * SVN $Date: 2014-07-04 12:15:22 +0100 (Fri, 04 Jul 2014) $ + ******************************************************************************/ + +#include <stdint.h> + +/* define compiler specific symbols */ +#if defined ( __CC_ARM ) + #define __ASM __asm /*!< asm keyword for ARM Compiler */ + #define __INLINE __inline /*!< inline keyword for ARM Compiler */ + +#elif defined ( __ICCARM__ ) + #define __ASM __asm /*!< asm keyword for IAR Compiler */ + #define __INLINE inline /*!< inline keyword for IAR Compiler. Only avaiable in High optimization mode! */ + +#elif defined ( __GNUC__ ) + #define __ASM __asm /*!< asm keyword for GNU Compiler */ + #define __INLINE inline /*!< inline keyword for GNU Compiler */ + +#elif defined ( __TASKING__ ) + #define __ASM __asm /*!< asm keyword for TASKING Compiler */ + #define __INLINE inline /*!< inline keyword for TASKING Compiler */ + +#endif + + +/* ################### Compiler specific Intrinsics ########################### */ + +#if defined ( __CC_ARM ) /*------------------RealView Compiler -----------------*/ +/* ARM armcc specific functions */ + +/** + * @brief Return the Process Stack Pointer + * + * @return ProcessStackPointer + * + * Return the actual process stack pointer + */ +__ASM uint32_t __get_PSP(void) +{ + mrs r0, psp + bx lr +} + +/** + * @brief Set the Process Stack Pointer + * + * @param topOfProcStack Process Stack Pointer + * + * Assign the value ProcessStackPointer to the MSP + * (process stack pointer) Cortex processor register + */ +__ASM void __set_PSP(uint32_t topOfProcStack) +{ + msr psp, r0 + bx lr +} + +/** + * @brief Return the Main Stack Pointer + * + * @return Main Stack Pointer + * + * Return the current value of the MSP (main stack pointer) + * Cortex processor register + */ +__ASM uint32_t __get_MSP(void) +{ + mrs r0, msp + bx lr +} + +/** + * @brief Set the Main Stack Pointer + * + * @param topOfMainStack Main Stack Pointer + * + * Assign the value mainStackPointer to the MSP + * (main stack pointer) Cortex processor register + */ +__ASM void __set_MSP(uint32_t mainStackPointer) +{ + msr msp, r0 + bx lr +} + +/** + * @brief Reverse byte order in unsigned short value + * + * @param value value to reverse + * @return reversed value + * + * Reverse byte order in unsigned short value + */ +__ASM uint32_t __REV16(uint16_t value) +{ + rev16 r0, r0 + bx lr +} + +/** + * @brief Reverse byte order in signed short value with sign extension to integer + * + * @param value value to reverse + * @return reversed value + * + * Reverse byte order in signed short value with sign extension to integer + */ +__ASM int32_t __REVSH(int16_t value) +{ + revsh r0, r0 + bx lr +} + + +#if (__ARMCC_VERSION < 400000) + +/** + * @brief Remove the exclusive lock created by ldrex + * + * Removes the exclusive lock which is created by ldrex. + */ +__ASM void __CLREX(void) +{ + clrex +} + +/** + * @brief Return the Base Priority value + * + * @return BasePriority + * + * Return the content of the base priority register + */ +__ASM uint32_t __get_BASEPRI(void) +{ + mrs r0, basepri + bx lr +} + +/** + * @brief Set the Base Priority value + * + * @param basePri BasePriority + * + * Set the base priority register + */ +__ASM void __set_BASEPRI(uint32_t basePri) +{ + msr basepri, r0 + bx lr +} + +/** + * @brief Return the Priority Mask value + * + * @return PriMask + * + * Return state of the priority mask bit from the priority mask register + */ +__ASM uint32_t __get_PRIMASK(void) +{ + mrs r0, primask + bx lr +} + +/** + * @brief Set the Priority Mask value + * + * @param priMask PriMask + * + * Set the priority mask bit in the priority mask register + */ +__ASM void __set_PRIMASK(uint32_t priMask) +{ + msr primask, r0 + bx lr +} + +/** + * @brief Return the Fault Mask value + * + * @return FaultMask + * + * Return the content of the fault mask register + */ +__ASM uint32_t __get_FAULTMASK(void) +{ + mrs r0, faultmask + bx lr +} + +/** + * @brief Set the Fault Mask value + * + * @param faultMask faultMask value + * + * Set the fault mask register + */ +__ASM void __set_FAULTMASK(uint32_t faultMask) +{ + msr faultmask, r0 + bx lr +} + +/** + * @brief Return the Control Register value + * + * @return Control value + * + * Return the content of the control register + */ +__ASM uint32_t __get_CONTROL(void) +{ + mrs r0, control + bx lr +} + +/** + * @brief Set the Control Register value + * + * @param control Control value + * + * Set the control register + */ +__ASM void __set_CONTROL(uint32_t control) +{ + msr control, r0 + bx lr +} + +#endif /* __ARMCC_VERSION */ + + + +#elif (defined (__ICCARM__)) /*------------------ ICC Compiler -------------------*/ +/* IAR iccarm specific functions */ +#pragma diag_suppress=Pe940 + +/** + * @brief Return the Process Stack Pointer + * + * @return ProcessStackPointer + * + * Return the actual process stack pointer + */ +#if (__VER__ < 6020000) +uint32_t __get_PSP(void) +{ + __ASM("mrs r0, psp"); + __ASM("bx lr"); +} +#endif + +/** + * @brief Set the Process Stack Pointer + * + * @param topOfProcStack Process Stack Pointer + * + * Assign the value ProcessStackPointer to the MSP + * (process stack pointer) Cortex processor register + */ +#if (__VER__ < 6020000) +void __set_PSP(uint32_t topOfProcStack) +{ + __ASM("msr psp, r0"); + __ASM("bx lr"); +} +#endif + +/** + * @brief Return the Main Stack Pointer + * + * @return Main Stack Pointer + * + * Return the current value of the MSP (main stack pointer) + * Cortex processor register + */ +#if (__VER__ < 6020000) +uint32_t __get_MSP(void) +{ + __ASM("mrs r0, msp"); + __ASM("bx lr"); +} +#endif + +/** + * @brief Set the Main Stack Pointer + * + * @param topOfMainStack Main Stack Pointer + * + * Assign the value mainStackPointer to the MSP + * (main stack pointer) Cortex processor register + */ +#if (__VER__ < 6020000) +void __set_MSP(uint32_t topOfMainStack) +{ + __ASM("msr msp, r0"); + __ASM("bx lr"); +} +#endif + +/** + * @brief Reverse byte order in unsigned short value + * + * @param value value to reverse + * @return reversed value + * + * Reverse byte order in unsigned short value + */ +#if (__VER__ < 6020000) +uint32_t __REV16(uint16_t value) +{ + __ASM("rev16 r0, r0"); + __ASM("bx lr"); +} +#endif + +/** + * @brief Reverse bit order of value + * + * @param value value to reverse + * @return reversed value + * + * Reverse bit order of value + */ +#if (__VER__ < 6020000) +uint32_t __RBIT(uint32_t value) +{ + __ASM("rbit r0, r0"); + __ASM("bx lr"); +} +#endif + +/** + * @brief LDR Exclusive (8 bit) + * + * @param *addr address pointer + * @return value of (*address) + * + * Exclusive LDR command for 8 bit values) + */ +#if (__VER__ < 6020000) +uint8_t __LDREXB(uint8_t *addr) +{ + __ASM("ldrexb r0, [r0]"); + __ASM("bx lr"); +} +#endif + +/** + * @brief LDR Exclusive (16 bit) + * + * @param *addr address pointer + * @return value of (*address) + * + * Exclusive LDR command for 16 bit values + */ +#if (__VER__ < 6020000) +uint16_t __LDREXH(uint16_t *addr) +{ + __ASM("ldrexh r0, [r0]"); + __ASM("bx lr"); +} +#endif + +/** + * @brief LDR Exclusive (32 bit) + * + * @param *addr address pointer + * @return value of (*address) + * + * Exclusive LDR command for 32 bit values + */ +uint32_t __LDREXW(uint32_t *addr) +{ + __ASM("ldrex r0, [r0]"); + __ASM("bx lr"); +} + +/** + * @brief STR Exclusive (8 bit) + * + * @param value value to store + * @param *addr address pointer + * @return successful / failed + * + * Exclusive STR command for 8 bit values + */ +#if (__VER__ < 6020000) +uint32_t __STREXB(uint8_t value, uint8_t *addr) +{ + __ASM("strexb r0, r0, [r1]"); + __ASM("bx lr"); +} +#endif + +/** + * @brief STR Exclusive (16 bit) + * + * @param value value to store + * @param *addr address pointer + * @return successful / failed + * + * Exclusive STR command for 16 bit values + */ +#if (__VER__ < 6020000) +uint32_t __STREXH(uint16_t value, uint16_t *addr) +{ + __ASM("strexh r0, r0, [r1]"); + __ASM("bx lr"); +} +#endif + +/** + * @brief STR Exclusive (32 bit) + * + * @param value value to store + * @param *addr address pointer + * @return successful / failed + * + * Exclusive STR command for 32 bit values + */ +uint32_t __STREXW(uint32_t value, uint32_t *addr) +{ + __ASM("strex r0, r0, [r1]"); + __ASM("bx lr"); +} + +#pragma diag_default=Pe940 + + +#elif (defined (__GNUC__)) /*------------------ GNU Compiler ---------------------*/ +/* GNU gcc specific functions */ + +/** + * @brief Return the Process Stack Pointer + * + * @return ProcessStackPointer + * + * Return the actual process stack pointer + */ +uint32_t __get_PSP(void) __attribute__( ( naked ) ); +uint32_t __get_PSP(void) +{ + uint32_t result=0; + + __ASM volatile ("MRS %0, psp\n\t" + "MOV r0, %0 \n\t" + "BX lr \n\t" : "=r" (result) ); + return(result); +} + +/** + * @brief Set the Process Stack Pointer + * + * @param topOfProcStack Process Stack Pointer + * + * Assign the value ProcessStackPointer to the MSP + * (process stack pointer) Cortex processor register + */ +void __set_PSP(uint32_t topOfProcStack) __attribute__( ( naked ) ); +void __set_PSP(uint32_t topOfProcStack) +{ + __ASM volatile ("MSR psp, %0\n\t" + "BX lr \n\t" : : "r" (topOfProcStack) ); +} + +/** + * @brief Return the Main Stack Pointer + * + * @return Main Stack Pointer + * + * Return the current value of the MSP (main stack pointer) + * Cortex processor register + */ +uint32_t __get_MSP(void) __attribute__( ( naked ) ); +uint32_t __get_MSP(void) +{ + uint32_t result=0; + + __ASM volatile ("MRS %0, msp\n\t" + "MOV r0, %0 \n\t" + "BX lr \n\t" : "=r" (result) ); + return(result); +} + +/** + * @brief Set the Main Stack Pointer + * + * @param topOfMainStack Main Stack Pointer + * + * Assign the value mainStackPointer to the MSP + * (main stack pointer) Cortex processor register + */ +void __set_MSP(uint32_t topOfMainStack) __attribute__( ( naked ) ); +void __set_MSP(uint32_t topOfMainStack) +{ + __ASM volatile ("MSR msp, %0\n\t" + "BX lr \n\t" : : "r" (topOfMainStack) ); +} + +/** + * @brief Return the Base Priority value + * + * @return BasePriority + * + * Return the content of the base priority register + */ +uint32_t __get_BASEPRI(void) +{ + uint32_t result=0; + + __ASM volatile ("MRS %0, basepri_max" : "=r" (result) ); + return(result); +} + +/** + * @brief Set the Base Priority value + * + * @param basePri BasePriority + * + * Set the base priority register + */ +void __set_BASEPRI(uint32_t value) +{ + __ASM volatile ("MSR basepri, %0" : : "r" (value) ); +} + +/** + * @brief Return the Priority Mask value + * + * @return PriMask + * + * Return state of the priority mask bit from the priority mask register + */ +uint32_t __get_PRIMASK(void) +{ + uint32_t result=0; + + __ASM volatile ("MRS %0, primask" : "=r" (result) ); + return(result); +} + +/** + * @brief Set the Priority Mask value + * + * @param priMask PriMask + * + * Set the priority mask bit in the priority mask register + */ +void __set_PRIMASK(uint32_t priMask) +{ + __ASM volatile ("MSR primask, %0" : : "r" (priMask) ); +} + +/** + * @brief Return the Fault Mask value + * + * @return FaultMask + * + * Return the content of the fault mask register + */ +uint32_t __get_FAULTMASK(void) +{ + uint32_t result=0; + + __ASM volatile ("MRS %0, faultmask" : "=r" (result) ); + return(result); +} + +/** + * @brief Set the Fault Mask value + * + * @param faultMask faultMask value + * + * Set the fault mask register + */ +void __set_FAULTMASK(uint32_t faultMask) +{ + __ASM volatile ("MSR faultmask, %0" : : "r" (faultMask) ); +} + +/** + * @brief Return the Control Register value +* +* @return Control value + * + * Return the content of the control register + */ +uint32_t __get_CONTROL(void) +{ + uint32_t result=0; + + __ASM volatile ("MRS %0, control" : "=r" (result) ); + return(result); +} + +/** + * @brief Set the Control Register value + * + * @param control Control value + * + * Set the control register + */ +void __set_CONTROL(uint32_t control) +{ + __ASM volatile ("MSR control, %0" : : "r" (control) ); +} + + +/** + * @brief Reverse byte order in integer value + * + * @param value value to reverse + * @return reversed value + * + * Reverse byte order in integer value + */ +uint32_t __REV(uint32_t value) +{ + uint32_t result=0; + + __ASM volatile ("rev %0, %1" : "=r" (result) : "r" (value) ); + return(result); +} + +/** + * @brief Reverse byte order in unsigned short value + * + * @param value value to reverse + * @return reversed value + * + * Reverse byte order in unsigned short value + */ +uint32_t __REV16(uint16_t value) +{ + uint32_t result=0; + + __ASM volatile ("rev16 %0, %1" : "=r" (result) : "r" (value) ); + return(result); +} + +/** + * @brief Reverse byte order in signed short value with sign extension to integer + * + * @param value value to reverse + * @return reversed value + * + * Reverse byte order in signed short value with sign extension to integer + */ +int32_t __REVSH(int16_t value) +{ + uint32_t result=0; + + __ASM volatile ("revsh %0, %1" : "=r" (result) : "r" (value) ); + return(result); +} + +/** + * @brief Reverse bit order of value + * + * @param value value to reverse + * @return reversed value + * + * Reverse bit order of value + */ +uint32_t __RBIT(uint32_t value) +{ + uint32_t result=0; + + __ASM volatile ("rbit %0, %1" : "=r" (result) : "r" (value) ); + return(result); +} + +/** + * @brief LDR Exclusive (8 bit) + * + * @param *addr address pointer + * @return value of (*address) + * + * Exclusive LDR command for 8 bit value + */ +uint8_t __LDREXB(uint8_t *addr) +{ + uint8_t result=0; + + __ASM volatile ("ldrexb %0, [%1]" : "=r" (result) : "r" (addr) ); + return(result); +} + +/** + * @brief LDR Exclusive (16 bit) + * + * @param *addr address pointer + * @return value of (*address) + * + * Exclusive LDR command for 16 bit values + */ +uint16_t __LDREXH(uint16_t *addr) +{ + uint16_t result=0; + + __ASM volatile ("ldrexh %0, [%1]" : "=r" (result) : "r" (addr) ); + return(result); +} + +/** + * @brief LDR Exclusive (32 bit) + * + * @param *addr address pointer + * @return value of (*address) + * + * Exclusive LDR command for 32 bit values + */ +uint32_t __LDREXW(uint32_t *addr) +{ + uint32_t result=0; + + __ASM volatile ("ldrex %0, [%1]" : "=r" (result) : "r" (addr) ); + return(result); +} + +/** + * @brief STR Exclusive (8 bit) + * + * @param value value to store + * @param *addr address pointer + * @return successful / failed + * + * Exclusive STR command for 8 bit values + */ +uint32_t __STREXB(uint8_t value, uint8_t *addr) +{ + uint32_t result=0; + + __ASM volatile ("strexb %0, %2, [%1]" : "=&r" (result) : "r" (addr), "r" (value) ); + return(result); +} + +/** + * @brief STR Exclusive (16 bit) + * + * @param value value to store + * @param *addr address pointer + * @return successful / failed + * + * Exclusive STR command for 16 bit values + */ +uint32_t __STREXH(uint16_t value, uint16_t *addr) +{ + uint32_t result=0; + + __ASM volatile ("strexh %0, %2, [%1]" : "=&r" (result) : "r" (addr), "r" (value) ); + return(result); +} + +/** + * @brief STR Exclusive (32 bit) + * + * @param value value to store + * @param *addr address pointer + * @return successful / failed + * + * Exclusive STR command for 32 bit values + */ +uint32_t __STREXW(uint32_t value, uint32_t *addr) +{ + uint32_t result=0; + + __ASM volatile ("strex %0, %2, [%1]" : "=r" (result) : "r" (addr), "r" (value) ); + return(result); +} + + +#elif (defined (__TASKING__)) /*------------------ TASKING Compiler ---------------------*/ +/* TASKING carm specific functions */ + +/* + * The CMSIS functions have been implemented as intrinsics in the compiler. + * Please use "carm -?i" to get an up to date list of all instrinsics, + * Including the CMSIS ones. + */ + +#endif diff --git a/bsp/smartfusion2/CMSIS/core_cm3.h b/bsp/smartfusion2/CMSIS/core_cm3.h new file mode 100644 index 0000000000..6c53c0f468 --- /dev/null +++ b/bsp/smartfusion2/CMSIS/core_cm3.h @@ -0,0 +1,1844 @@ +/**************************************************************************//** + * @file core_cm3.h + * @brief CMSIS Cortex-M3 Core Peripheral Access Layer Header File + * @version V1.30 + * @date 30. October 2009 + * + * @note + * Copyright (C) 2009 ARM Limited. All rights reserved. + * + * @par + * ARM Limited (ARM) is supplying this software for use with Cortex-M + * processor based microcontrollers. This file can be freely distributed + * within development tools that are supporting such ARM based processors. + * + * @par + * THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED + * OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF + * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE. + * ARM SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR + * CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER. + * + ******************************************************************************/ +/******************************************************************************* + * Microsemi SoC Products Group SVN revision number for the purpose of tracking + * changes done to original file supplied by ARM: + * SVN $Revision: 4048 $ + * SVN $Date: 2011-12-06 16:05:56 +0000 (Tue, 06 Dec 2011) $ + ******************************************************************************/ + +#ifndef __CM3_CORE_H__ +#define __CM3_CORE_H__ + +/** @addtogroup CMSIS_CM3_core_LintCinfiguration CMSIS CM3 Core Lint Configuration + * + * List of Lint messages which will be suppressed and not shown: + * - Error 10: \n + * register uint32_t __regBasePri __asm("basepri"); \n + * Error 10: Expecting ';' + * . + * - Error 530: \n + * return(__regBasePri); \n + * Warning 530: Symbol '__regBasePri' (line 264) not initialized + * . + * - Error 550: \n + * __regBasePri = (basePri & 0x1ff); \n + * Warning 550: Symbol '__regBasePri' (line 271) not accessed + * . + * - Error 754: \n + * uint32_t RESERVED0[24]; \n + * Info 754: local structure member '<some, not used in the HAL>' (line 109, file ./cm3_core.h) not referenced + * . + * - Error 750: \n + * #define __CM3_CORE_H__ \n + * Info 750: local macro '__CM3_CORE_H__' (line 43, file./cm3_core.h) not referenced + * . + * - Error 528: \n + * static __INLINE void NVIC_DisableIRQ(uint32_t IRQn) \n + * Warning 528: Symbol 'NVIC_DisableIRQ(unsigned int)' (line 419, file ./cm3_core.h) not referenced + * . + * - Error 751: \n + * } InterruptType_Type; \n + * Info 751: local typedef 'InterruptType_Type' (line 170, file ./cm3_core.h) not referenced + * . + * Note: To re-enable a Message, insert a space before 'lint' * + * + */ + +/*lint -save */ +/*lint -e10 */ +/*lint -e530 */ +/*lint -e550 */ +/*lint -e754 */ +/*lint -e750 */ +/*lint -e528 */ +/*lint -e751 */ + + +/** @addtogroup CMSIS_CM3_core_definitions CM3 Core Definitions + This file defines all structures and symbols for CMSIS core: + - CMSIS version number + - Cortex-M core registers and bitfields + - Cortex-M core peripheral base address + @{ + */ + +#ifdef __cplusplus + extern "C" { +#endif + +#define __CM3_CMSIS_VERSION_MAIN (0x01) /*!< [31:16] CMSIS HAL main version */ +#define __CM3_CMSIS_VERSION_SUB (0x30) /*!< [15:0] CMSIS HAL sub version */ +#define __CM3_CMSIS_VERSION ((__CM3_CMSIS_VERSION_MAIN << 16) | __CM3_CMSIS_VERSION_SUB) /*!< CMSIS HAL version number */ + +#define __CORTEX_M (0x03) /*!< Cortex core */ + +#include <stdint.h> /* Include standard types */ + +#if defined (__ICCARM__) + #include <intrinsics.h> /* IAR Intrinsics */ +#endif + + +#ifndef __NVIC_PRIO_BITS + #define __NVIC_PRIO_BITS 4 /*!< standard definition for NVIC Priority Bits */ +#endif + + + + +/** + * IO definitions + * + * define access restrictions to peripheral registers + */ + +#ifdef __cplusplus + #define __I volatile /*!< defines 'read only' permissions */ +#else + #define __I volatile const /*!< defines 'read only' permissions */ +#endif +#define __O volatile /*!< defines 'write only' permissions */ +#define __IO volatile /*!< defines 'read / write' permissions */ + + + +/******************************************************************************* + * Register Abstraction + ******************************************************************************/ +/** @addtogroup CMSIS_CM3_core_register CMSIS CM3 Core Register + @{ +*/ + + +/** @addtogroup CMSIS_CM3_NVIC CMSIS CM3 NVIC + memory mapped structure for Nested Vectored Interrupt Controller (NVIC) + @{ + */ +typedef struct +{ + __IO uint32_t ISER[8]; /*!< Offset: 0x000 Interrupt Set Enable Register */ + uint32_t RESERVED0[24]; + __IO uint32_t ICER[8]; /*!< Offset: 0x080 Interrupt Clear Enable Register */ + uint32_t RSERVED1[24]; + __IO uint32_t ISPR[8]; /*!< Offset: 0x100 Interrupt Set Pending Register */ + uint32_t RESERVED2[24]; + __IO uint32_t ICPR[8]; /*!< Offset: 0x180 Interrupt Clear Pending Register */ + uint32_t RESERVED3[24]; + __IO uint32_t IABR[8]; /*!< Offset: 0x200 Interrupt Active bit Register */ + uint32_t RESERVED4[56]; + __IO uint8_t IP[240]; /*!< Offset: 0x300 Interrupt Priority Register (8Bit wide) */ + uint32_t RESERVED5[644]; + __O uint32_t STIR; /*!< Offset: 0xE00 Software Trigger Interrupt Register */ +} NVIC_Type; +/*@}*/ /* end of group CMSIS_CM3_NVIC */ + + +/** @addtogroup CMSIS_CM3_SCB CMSIS CM3 SCB + memory mapped structure for System Control Block (SCB) + @{ + */ +typedef struct +{ + __I uint32_t CPUID; /*!< Offset: 0x00 CPU ID Base Register */ + __IO uint32_t ICSR; /*!< Offset: 0x04 Interrupt Control State Register */ + __IO uint32_t VTOR; /*!< Offset: 0x08 Vector Table Offset Register */ + __IO uint32_t AIRCR; /*!< Offset: 0x0C Application Interrupt / Reset Control Register */ + __IO uint32_t SCR; /*!< Offset: 0x10 System Control Register */ + __IO uint32_t CCR; /*!< Offset: 0x14 Configuration Control Register */ + __IO uint8_t SHP[12]; /*!< Offset: 0x18 System Handlers Priority Registers (4-7, 8-11, 12-15) */ + __IO uint32_t SHCSR; /*!< Offset: 0x24 System Handler Control and State Register */ + __IO uint32_t CFSR; /*!< Offset: 0x28 Configurable Fault Status Register */ + __IO uint32_t HFSR; /*!< Offset: 0x2C Hard Fault Status Register */ + __IO uint32_t DFSR; /*!< Offset: 0x30 Debug Fault Status Register */ + __IO uint32_t MMFAR; /*!< Offset: 0x34 Mem Manage Address Register */ + __IO uint32_t BFAR; /*!< Offset: 0x38 Bus Fault Address Register */ + __IO uint32_t AFSR; /*!< Offset: 0x3C Auxiliary Fault Status Register */ + __I uint32_t PFR[2]; /*!< Offset: 0x40 Processor Feature Register */ + __I uint32_t DFR; /*!< Offset: 0x48 Debug Feature Register */ + __I uint32_t ADR; /*!< Offset: 0x4C Auxiliary Feature Register */ + __I uint32_t MMFR[4]; /*!< Offset: 0x50 Memory Model Feature Register */ + __I uint32_t ISAR[5]; /*!< Offset: 0x60 ISA Feature Register */ +} SCB_Type; + +/* SCB CPUID Register Definitions */ +#define SCB_CPUID_IMPLEMENTER_Pos 24 /*!< SCB CPUID: IMPLEMENTER Position */ +#define SCB_CPUID_IMPLEMENTER_Msk (0xFFul << SCB_CPUID_IMPLEMENTER_Pos) /*!< SCB CPUID: IMPLEMENTER Mask */ + +#define SCB_CPUID_VARIANT_Pos 20 /*!< SCB CPUID: VARIANT Position */ +#define SCB_CPUID_VARIANT_Msk (0xFul << SCB_CPUID_VARIANT_Pos) /*!< SCB CPUID: VARIANT Mask */ + +#define SCB_CPUID_PARTNO_Pos 4 /*!< SCB CPUID: PARTNO Position */ +#define SCB_CPUID_PARTNO_Msk (0xFFFul << SCB_CPUID_PARTNO_Pos) /*!< SCB CPUID: PARTNO Mask */ + +#define SCB_CPUID_REVISION_Pos 0 /*!< SCB CPUID: REVISION Position */ +#define SCB_CPUID_REVISION_Msk (0xFul << SCB_CPUID_REVISION_Pos) /*!< SCB CPUID: REVISION Mask */ + +/* SCB Interrupt Control State Register Definitions */ +#define SCB_ICSR_NMIPENDSET_Pos 31 /*!< SCB ICSR: NMIPENDSET Position */ +#define SCB_ICSR_NMIPENDSET_Msk (1ul << SCB_ICSR_NMIPENDSET_Pos) /*!< SCB ICSR: NMIPENDSET Mask */ + +#define SCB_ICSR_PENDSVSET_Pos 28 /*!< SCB ICSR: PENDSVSET Position */ +#define SCB_ICSR_PENDSVSET_Msk (1ul << SCB_ICSR_PENDSVSET_Pos) /*!< SCB ICSR: PENDSVSET Mask */ + +#define SCB_ICSR_PENDSVCLR_Pos 27 /*!< SCB ICSR: PENDSVCLR Position */ +#define SCB_ICSR_PENDSVCLR_Msk (1ul << SCB_ICSR_PENDSVCLR_Pos) /*!< SCB ICSR: PENDSVCLR Mask */ + +#define SCB_ICSR_PENDSTSET_Pos 26 /*!< SCB ICSR: PENDSTSET Position */ +#define SCB_ICSR_PENDSTSET_Msk (1ul << SCB_ICSR_PENDSTSET_Pos) /*!< SCB ICSR: PENDSTSET Mask */ + +#define SCB_ICSR_PENDSTCLR_Pos 25 /*!< SCB ICSR: PENDSTCLR Position */ +#define SCB_ICSR_PENDSTCLR_Msk (1ul << SCB_ICSR_PENDSTCLR_Pos) /*!< SCB ICSR: PENDSTCLR Mask */ + +#define SCB_ICSR_ISRPREEMPT_Pos 23 /*!< SCB ICSR: ISRPREEMPT Position */ +#define SCB_ICSR_ISRPREEMPT_Msk (1ul << SCB_ICSR_ISRPREEMPT_Pos) /*!< SCB ICSR: ISRPREEMPT Mask */ + +#define SCB_ICSR_ISRPENDING_Pos 22 /*!< SCB ICSR: ISRPENDING Position */ +#define SCB_ICSR_ISRPENDING_Msk (1ul << SCB_ICSR_ISRPENDING_Pos) /*!< SCB ICSR: ISRPENDING Mask */ + +#define SCB_ICSR_VECTPENDING_Pos 12 /*!< SCB ICSR: VECTPENDING Position */ +#define SCB_ICSR_VECTPENDING_Msk (0x1FFul << SCB_ICSR_VECTPENDING_Pos) /*!< SCB ICSR: VECTPENDING Mask */ + +#define SCB_ICSR_RETTOBASE_Pos 11 /*!< SCB ICSR: RETTOBASE Position */ +#define SCB_ICSR_RETTOBASE_Msk (1ul << SCB_ICSR_RETTOBASE_Pos) /*!< SCB ICSR: RETTOBASE Mask */ + +#define SCB_ICSR_VECTACTIVE_Pos 0 /*!< SCB ICSR: VECTACTIVE Position */ +#define SCB_ICSR_VECTACTIVE_Msk (0x1FFul << SCB_ICSR_VECTACTIVE_Pos) /*!< SCB ICSR: VECTACTIVE Mask */ + +/* SCB Interrupt Control State Register Definitions */ +#define SCB_VTOR_TBLBASE_Pos 29 /*!< SCB VTOR: TBLBASE Position */ +#define SCB_VTOR_TBLBASE_Msk (0x1FFul << SCB_VTOR_TBLBASE_Pos) /*!< SCB VTOR: TBLBASE Mask */ + +#define SCB_VTOR_TBLOFF_Pos 7 /*!< SCB VTOR: TBLOFF Position */ +#define SCB_VTOR_TBLOFF_Msk (0x3FFFFFul << SCB_VTOR_TBLOFF_Pos) /*!< SCB VTOR: TBLOFF Mask */ + +/* SCB Application Interrupt and Reset Control Register Definitions */ +#define SCB_AIRCR_VECTKEY_Pos 16 /*!< SCB AIRCR: VECTKEY Position */ +#define SCB_AIRCR_VECTKEY_Msk (0xFFFFul << SCB_AIRCR_VECTKEY_Pos) /*!< SCB AIRCR: VECTKEY Mask */ + +#define SCB_AIRCR_VECTKEYSTAT_Pos 16 /*!< SCB AIRCR: VECTKEYSTAT Position */ +#define SCB_AIRCR_VECTKEYSTAT_Msk (0xFFFFul << SCB_AIRCR_VECTKEYSTAT_Pos) /*!< SCB AIRCR: VECTKEYSTAT Mask */ + +#define SCB_AIRCR_ENDIANESS_Pos 15 /*!< SCB AIRCR: ENDIANESS Position */ +#define SCB_AIRCR_ENDIANESS_Msk (1ul << SCB_AIRCR_ENDIANESS_Pos) /*!< SCB AIRCR: ENDIANESS Mask */ + +#define SCB_AIRCR_PRIGROUP_Pos 8 /*!< SCB AIRCR: PRIGROUP Position */ +#define SCB_AIRCR_PRIGROUP_Msk (7ul << SCB_AIRCR_PRIGROUP_Pos) /*!< SCB AIRCR: PRIGROUP Mask */ + +#define SCB_AIRCR_SYSRESETREQ_Pos 2 /*!< SCB AIRCR: SYSRESETREQ Position */ +#define SCB_AIRCR_SYSRESETREQ_Msk (1ul << SCB_AIRCR_SYSRESETREQ_Pos) /*!< SCB AIRCR: SYSRESETREQ Mask */ + +#define SCB_AIRCR_VECTCLRACTIVE_Pos 1 /*!< SCB AIRCR: VECTCLRACTIVE Position */ +#define SCB_AIRCR_VECTCLRACTIVE_Msk (1ul << SCB_AIRCR_VECTCLRACTIVE_Pos) /*!< SCB AIRCR: VECTCLRACTIVE Mask */ + +#define SCB_AIRCR_VECTRESET_Pos 0 /*!< SCB AIRCR: VECTRESET Position */ +#define SCB_AIRCR_VECTRESET_Msk (1ul << SCB_AIRCR_VECTRESET_Pos) /*!< SCB AIRCR: VECTRESET Mask */ + +/* SCB System Control Register Definitions */ +#define SCB_SCR_SEVONPEND_Pos 4 /*!< SCB SCR: SEVONPEND Position */ +#define SCB_SCR_SEVONPEND_Msk (1ul << SCB_SCR_SEVONPEND_Pos) /*!< SCB SCR: SEVONPEND Mask */ + +#define SCB_SCR_SLEEPDEEP_Pos 2 /*!< SCB SCR: SLEEPDEEP Position */ +#define SCB_SCR_SLEEPDEEP_Msk (1ul << SCB_SCR_SLEEPDEEP_Pos) /*!< SCB SCR: SLEEPDEEP Mask */ + +#define SCB_SCR_SLEEPONEXIT_Pos 1 /*!< SCB SCR: SLEEPONEXIT Position */ +#define SCB_SCR_SLEEPONEXIT_Msk (1ul << SCB_SCR_SLEEPONEXIT_Pos) /*!< SCB SCR: SLEEPONEXIT Mask */ + +/* SCB Configuration Control Register Definitions */ +#define SCB_CCR_STKALIGN_Pos 9 /*!< SCB CCR: STKALIGN Position */ +#define SCB_CCR_STKALIGN_Msk (1ul << SCB_CCR_STKALIGN_Pos) /*!< SCB CCR: STKALIGN Mask */ + +#define SCB_CCR_BFHFNMIGN_Pos 8 /*!< SCB CCR: BFHFNMIGN Position */ +#define SCB_CCR_BFHFNMIGN_Msk (1ul << SCB_CCR_BFHFNMIGN_Pos) /*!< SCB CCR: BFHFNMIGN Mask */ + +#define SCB_CCR_DIV_0_TRP_Pos 4 /*!< SCB CCR: DIV_0_TRP Position */ +#define SCB_CCR_DIV_0_TRP_Msk (1ul << SCB_CCR_DIV_0_TRP_Pos) /*!< SCB CCR: DIV_0_TRP Mask */ + +#define SCB_CCR_UNALIGN_TRP_Pos 3 /*!< SCB CCR: UNALIGN_TRP Position */ +#define SCB_CCR_UNALIGN_TRP_Msk (1ul << SCB_CCR_UNALIGN_TRP_Pos) /*!< SCB CCR: UNALIGN_TRP Mask */ + +#define SCB_CCR_USERSETMPEND_Pos 1 /*!< SCB CCR: USERSETMPEND Position */ +#define SCB_CCR_USERSETMPEND_Msk (1ul << SCB_CCR_USERSETMPEND_Pos) /*!< SCB CCR: USERSETMPEND Mask */ + +#define SCB_CCR_NONBASETHRDENA_Pos 0 /*!< SCB CCR: NONBASETHRDENA Position */ +#define SCB_CCR_NONBASETHRDENA_Msk (1ul << SCB_CCR_NONBASETHRDENA_Pos) /*!< SCB CCR: NONBASETHRDENA Mask */ + +/* SCB System Handler Control and State Register Definitions */ +#define SCB_SHCSR_USGFAULTENA_Pos 18 /*!< SCB SHCSR: USGFAULTENA Position */ +#define SCB_SHCSR_USGFAULTENA_Msk (1ul << SCB_SHCSR_USGFAULTENA_Pos) /*!< SCB SHCSR: USGFAULTENA Mask */ + +#define SCB_SHCSR_BUSFAULTENA_Pos 17 /*!< SCB SHCSR: BUSFAULTENA Position */ +#define SCB_SHCSR_BUSFAULTENA_Msk (1ul << SCB_SHCSR_BUSFAULTENA_Pos) /*!< SCB SHCSR: BUSFAULTENA Mask */ + +#define SCB_SHCSR_MEMFAULTENA_Pos 16 /*!< SCB SHCSR: MEMFAULTENA Position */ +#define SCB_SHCSR_MEMFAULTENA_Msk (1ul << SCB_SHCSR_MEMFAULTENA_Pos) /*!< SCB SHCSR: MEMFAULTENA Mask */ + +#define SCB_SHCSR_SVCALLPENDED_Pos 15 /*!< SCB SHCSR: SVCALLPENDED Position */ +#define SCB_SHCSR_SVCALLPENDED_Msk (1ul << SCB_SHCSR_SVCALLPENDED_Pos) /*!< SCB SHCSR: SVCALLPENDED Mask */ + +#define SCB_SHCSR_BUSFAULTPENDED_Pos 14 /*!< SCB SHCSR: BUSFAULTPENDED Position */ +#define SCB_SHCSR_BUSFAULTPENDED_Msk (1ul << SCB_SHCSR_BUSFAULTPENDED_Pos) /*!< SCB SHCSR: BUSFAULTPENDED Mask */ + +#define SCB_SHCSR_MEMFAULTPENDED_Pos 13 /*!< SCB SHCSR: MEMFAULTPENDED Position */ +#define SCB_SHCSR_MEMFAULTPENDED_Msk (1ul << SCB_SHCSR_MEMFAULTPENDED_Pos) /*!< SCB SHCSR: MEMFAULTPENDED Mask */ + +#define SCB_SHCSR_USGFAULTPENDED_Pos 12 /*!< SCB SHCSR: USGFAULTPENDED Position */ +#define SCB_SHCSR_USGFAULTPENDED_Msk (1ul << SCB_SHCSR_USGFAULTPENDED_Pos) /*!< SCB SHCSR: USGFAULTPENDED Mask */ + +#define SCB_SHCSR_SYSTICKACT_Pos 11 /*!< SCB SHCSR: SYSTICKACT Position */ +#define SCB_SHCSR_SYSTICKACT_Msk (1ul << SCB_SHCSR_SYSTICKACT_Pos) /*!< SCB SHCSR: SYSTICKACT Mask */ + +#define SCB_SHCSR_PENDSVACT_Pos 10 /*!< SCB SHCSR: PENDSVACT Position */ +#define SCB_SHCSR_PENDSVACT_Msk (1ul << SCB_SHCSR_PENDSVACT_Pos) /*!< SCB SHCSR: PENDSVACT Mask */ + +#define SCB_SHCSR_MONITORACT_Pos 8 /*!< SCB SHCSR: MONITORACT Position */ +#define SCB_SHCSR_MONITORACT_Msk (1ul << SCB_SHCSR_MONITORACT_Pos) /*!< SCB SHCSR: MONITORACT Mask */ + +#define SCB_SHCSR_SVCALLACT_Pos 7 /*!< SCB SHCSR: SVCALLACT Position */ +#define SCB_SHCSR_SVCALLACT_Msk (1ul << SCB_SHCSR_SVCALLACT_Pos) /*!< SCB SHCSR: SVCALLACT Mask */ + +#define SCB_SHCSR_USGFAULTACT_Pos 3 /*!< SCB SHCSR: USGFAULTACT Position */ +#define SCB_SHCSR_USGFAULTACT_Msk (1ul << SCB_SHCSR_USGFAULTACT_Pos) /*!< SCB SHCSR: USGFAULTACT Mask */ + +#define SCB_SHCSR_BUSFAULTACT_Pos 1 /*!< SCB SHCSR: BUSFAULTACT Position */ +#define SCB_SHCSR_BUSFAULTACT_Msk (1ul << SCB_SHCSR_BUSFAULTACT_Pos) /*!< SCB SHCSR: BUSFAULTACT Mask */ + +#define SCB_SHCSR_MEMFAULTACT_Pos 0 /*!< SCB SHCSR: MEMFAULTACT Position */ +#define SCB_SHCSR_MEMFAULTACT_Msk (1ul << SCB_SHCSR_MEMFAULTACT_Pos) /*!< SCB SHCSR: MEMFAULTACT Mask */ + +/* SCB Configurable Fault Status Registers Definitions */ +#define SCB_CFSR_USGFAULTSR_Pos 16 /*!< SCB CFSR: Usage Fault Status Register Position */ +#define SCB_CFSR_USGFAULTSR_Msk (0xFFFFul << SCB_CFSR_USGFAULTSR_Pos) /*!< SCB CFSR: Usage Fault Status Register Mask */ + +#define SCB_CFSR_BUSFAULTSR_Pos 8 /*!< SCB CFSR: Bus Fault Status Register Position */ +#define SCB_CFSR_BUSFAULTSR_Msk (0xFFul << SCB_CFSR_BUSFAULTSR_Pos) /*!< SCB CFSR: Bus Fault Status Register Mask */ + +#define SCB_CFSR_MEMFAULTSR_Pos 0 /*!< SCB CFSR: Memory Manage Fault Status Register Position */ +#define SCB_CFSR_MEMFAULTSR_Msk (0xFFul << SCB_CFSR_MEMFAULTSR_Pos) /*!< SCB CFSR: Memory Manage Fault Status Register Mask */ + +/* SCB Hard Fault Status Registers Definitions */ +#define SCB_HFSR_DEBUGEVT_Pos 31 /*!< SCB HFSR: DEBUGEVT Position */ +#define SCB_HFSR_DEBUGEVT_Msk (1ul << SCB_HFSR_DEBUGEVT_Pos) /*!< SCB HFSR: DEBUGEVT Mask */ + +#define SCB_HFSR_FORCED_Pos 30 /*!< SCB HFSR: FORCED Position */ +#define SCB_HFSR_FORCED_Msk (1ul << SCB_HFSR_FORCED_Pos) /*!< SCB HFSR: FORCED Mask */ + +#define SCB_HFSR_VECTTBL_Pos 1 /*!< SCB HFSR: VECTTBL Position */ +#define SCB_HFSR_VECTTBL_Msk (1ul << SCB_HFSR_VECTTBL_Pos) /*!< SCB HFSR: VECTTBL Mask */ + +/* SCB Debug Fault Status Register Definitions */ +#define SCB_DFSR_EXTERNAL_Pos 4 /*!< SCB DFSR: EXTERNAL Position */ +#define SCB_DFSR_EXTERNAL_Msk (1ul << SCB_DFSR_EXTERNAL_Pos) /*!< SCB DFSR: EXTERNAL Mask */ + +#define SCB_DFSR_VCATCH_Pos 3 /*!< SCB DFSR: VCATCH Position */ +#define SCB_DFSR_VCATCH_Msk (1ul << SCB_DFSR_VCATCH_Pos) /*!< SCB DFSR: VCATCH Mask */ + +#define SCB_DFSR_DWTTRAP_Pos 2 /*!< SCB DFSR: DWTTRAP Position */ +#define SCB_DFSR_DWTTRAP_Msk (1ul << SCB_DFSR_DWTTRAP_Pos) /*!< SCB DFSR: DWTTRAP Mask */ + +#define SCB_DFSR_BKPT_Pos 1 /*!< SCB DFSR: BKPT Position */ +#define SCB_DFSR_BKPT_Msk (1ul << SCB_DFSR_BKPT_Pos) /*!< SCB DFSR: BKPT Mask */ + +#define SCB_DFSR_HALTED_Pos 0 /*!< SCB DFSR: HALTED Position */ +#define SCB_DFSR_HALTED_Msk (1ul << SCB_DFSR_HALTED_Pos) /*!< SCB DFSR: HALTED Mask */ +/*@}*/ /* end of group CMSIS_CM3_SCB */ + + +/** @addtogroup CMSIS_CM3_SysTick CMSIS CM3 SysTick + memory mapped structure for SysTick + @{ + */ +typedef struct +{ + __IO uint32_t CTRL; /*!< Offset: 0x00 SysTick Control and Status Register */ + __IO uint32_t LOAD; /*!< Offset: 0x04 SysTick Reload Value Register */ + __IO uint32_t VAL; /*!< Offset: 0x08 SysTick Current Value Register */ + __I uint32_t CALIB; /*!< Offset: 0x0C SysTick Calibration Register */ +} SysTick_Type; + +/* SysTick Control / Status Register Definitions */ +#define SysTick_CTRL_COUNTFLAG_Pos 16 /*!< SysTick CTRL: COUNTFLAG Position */ +#define SysTick_CTRL_COUNTFLAG_Msk (1ul << SysTick_CTRL_COUNTFLAG_Pos) /*!< SysTick CTRL: COUNTFLAG Mask */ + +#define SysTick_CTRL_CLKSOURCE_Pos 2 /*!< SysTick CTRL: CLKSOURCE Position */ +#define SysTick_CTRL_CLKSOURCE_Msk (1ul << SysTick_CTRL_CLKSOURCE_Pos) /*!< SysTick CTRL: CLKSOURCE Mask */ + +#define SysTick_CTRL_TICKINT_Pos 1 /*!< SysTick CTRL: TICKINT Position */ +#define SysTick_CTRL_TICKINT_Msk (1ul << SysTick_CTRL_TICKINT_Pos) /*!< SysTick CTRL: TICKINT Mask */ + +#define SysTick_CTRL_ENABLE_Pos 0 /*!< SysTick CTRL: ENABLE Position */ +#define SysTick_CTRL_ENABLE_Msk (1ul << SysTick_CTRL_ENABLE_Pos) /*!< SysTick CTRL: ENABLE Mask */ + +/* SysTick Reload Register Definitions */ +#define SysTick_LOAD_RELOAD_Pos 0 /*!< SysTick LOAD: RELOAD Position */ +#define SysTick_LOAD_RELOAD_Msk (0xFFFFFFul << SysTick_LOAD_RELOAD_Pos) /*!< SysTick LOAD: RELOAD Mask */ + +/* SysTick Current Register Definitions */ +#define SysTick_VAL_CURRENT_Pos 0 /*!< SysTick VAL: CURRENT Position */ +#define SysTick_VAL_CURRENT_Msk (0xFFFFFFul << SysTick_VAL_CURRENT_Pos) /*!< SysTick VAL: CURRENT Mask */ + +/* SysTick Calibration Register Definitions */ +#define SysTick_CALIB_NOREF_Pos 31 /*!< SysTick CALIB: NOREF Position */ +#define SysTick_CALIB_NOREF_Msk (1ul << SysTick_CALIB_NOREF_Pos) /*!< SysTick CALIB: NOREF Mask */ + +#define SysTick_CALIB_SKEW_Pos 30 /*!< SysTick CALIB: SKEW Position */ +#define SysTick_CALIB_SKEW_Msk (1ul << SysTick_CALIB_SKEW_Pos) /*!< SysTick CALIB: SKEW Mask */ + +#define SysTick_CALIB_TENMS_Pos 0 /*!< SysTick CALIB: TENMS Position */ +#define SysTick_CALIB_TENMS_Msk (0xFFFFFFul << SysTick_VAL_CURRENT_Pos) /*!< SysTick CALIB: TENMS Mask */ +/*@}*/ /* end of group CMSIS_CM3_SysTick */ + + +/** @addtogroup CMSIS_CM3_ITM CMSIS CM3 ITM + memory mapped structure for Instrumentation Trace Macrocell (ITM) + @{ + */ +typedef struct +{ + __O union + { + __O uint8_t u8; /*!< Offset: ITM Stimulus Port 8-bit */ + __O uint16_t u16; /*!< Offset: ITM Stimulus Port 16-bit */ + __O uint32_t u32; /*!< Offset: ITM Stimulus Port 32-bit */ + } PORT [32]; /*!< Offset: 0x00 ITM Stimulus Port Registers */ + uint32_t RESERVED0[864]; + __IO uint32_t TER; /*!< Offset: ITM Trace Enable Register */ + uint32_t RESERVED1[15]; + __IO uint32_t TPR; /*!< Offset: ITM Trace Privilege Register */ + uint32_t RESERVED2[15]; + __IO uint32_t TCR; /*!< Offset: ITM Trace Control Register */ + uint32_t RESERVED3[29]; + __IO uint32_t IWR; /*!< Offset: ITM Integration Write Register */ + __IO uint32_t IRR; /*!< Offset: ITM Integration Read Register */ + __IO uint32_t IMCR; /*!< Offset: ITM Integration Mode Control Register */ + uint32_t RESERVED4[43]; + __IO uint32_t LAR; /*!< Offset: ITM Lock Access Register */ + __IO uint32_t LSR; /*!< Offset: ITM Lock Status Register */ + uint32_t RESERVED5[6]; + __I uint32_t PID4; /*!< Offset: ITM Peripheral Identification Register #4 */ + __I uint32_t PID5; /*!< Offset: ITM Peripheral Identification Register #5 */ + __I uint32_t PID6; /*!< Offset: ITM Peripheral Identification Register #6 */ + __I uint32_t PID7; /*!< Offset: ITM Peripheral Identification Register #7 */ + __I uint32_t PID0; /*!< Offset: ITM Peripheral Identification Register #0 */ + __I uint32_t PID1; /*!< Offset: ITM Peripheral Identification Register #1 */ + __I uint32_t PID2; /*!< Offset: ITM Peripheral Identification Register #2 */ + __I uint32_t PID3; /*!< Offset: ITM Peripheral Identification Register #3 */ + __I uint32_t CID0; /*!< Offset: ITM Component Identification Register #0 */ + __I uint32_t CID1; /*!< Offset: ITM Component Identification Register #1 */ + __I uint32_t CID2; /*!< Offset: ITM Component Identification Register #2 */ + __I uint32_t CID3; /*!< Offset: ITM Component Identification Register #3 */ +} ITM_Type; + +/* ITM Trace Privilege Register Definitions */ +#define ITM_TPR_PRIVMASK_Pos 0 /*!< ITM TPR: PRIVMASK Position */ +#define ITM_TPR_PRIVMASK_Msk (0xFul << ITM_TPR_PRIVMASK_Pos) /*!< ITM TPR: PRIVMASK Mask */ + +/* ITM Trace Control Register Definitions */ +#define ITM_TCR_BUSY_Pos 23 /*!< ITM TCR: BUSY Position */ +#define ITM_TCR_BUSY_Msk (1ul << ITM_TCR_BUSY_Pos) /*!< ITM TCR: BUSY Mask */ + +#define ITM_TCR_ATBID_Pos 16 /*!< ITM TCR: ATBID Position */ +#define ITM_TCR_ATBID_Msk (0x7Ful << ITM_TCR_ATBID_Pos) /*!< ITM TCR: ATBID Mask */ + +#define ITM_TCR_TSPrescale_Pos 8 /*!< ITM TCR: TSPrescale Position */ +#define ITM_TCR_TSPrescale_Msk (3ul << ITM_TCR_TSPrescale_Pos) /*!< ITM TCR: TSPrescale Mask */ + +#define ITM_TCR_SWOENA_Pos 4 /*!< ITM TCR: SWOENA Position */ +#define ITM_TCR_SWOENA_Msk (1ul << ITM_TCR_SWOENA_Pos) /*!< ITM TCR: SWOENA Mask */ + +#define ITM_TCR_DWTENA_Pos 3 /*!< ITM TCR: DWTENA Position */ +#define ITM_TCR_DWTENA_Msk (1ul << ITM_TCR_DWTENA_Pos) /*!< ITM TCR: DWTENA Mask */ + +#define ITM_TCR_SYNCENA_Pos 2 /*!< ITM TCR: SYNCENA Position */ +#define ITM_TCR_SYNCENA_Msk (1ul << ITM_TCR_SYNCENA_Pos) /*!< ITM TCR: SYNCENA Mask */ + +#define ITM_TCR_TSENA_Pos 1 /*!< ITM TCR: TSENA Position */ +#define ITM_TCR_TSENA_Msk (1ul << ITM_TCR_TSENA_Pos) /*!< ITM TCR: TSENA Mask */ + +#define ITM_TCR_ITMENA_Pos 0 /*!< ITM TCR: ITM Enable bit Position */ +#define ITM_TCR_ITMENA_Msk (1ul << ITM_TCR_ITMENA_Pos) /*!< ITM TCR: ITM Enable bit Mask */ + +/* ITM Integration Write Register Definitions */ +#define ITM_IWR_ATVALIDM_Pos 0 /*!< ITM IWR: ATVALIDM Position */ +#define ITM_IWR_ATVALIDM_Msk (1ul << ITM_IWR_ATVALIDM_Pos) /*!< ITM IWR: ATVALIDM Mask */ + +/* ITM Integration Read Register Definitions */ +#define ITM_IRR_ATREADYM_Pos 0 /*!< ITM IRR: ATREADYM Position */ +#define ITM_IRR_ATREADYM_Msk (1ul << ITM_IRR_ATREADYM_Pos) /*!< ITM IRR: ATREADYM Mask */ + +/* ITM Integration Mode Control Register Definitions */ +#define ITM_IMCR_INTEGRATION_Pos 0 /*!< ITM IMCR: INTEGRATION Position */ +#define ITM_IMCR_INTEGRATION_Msk (1ul << ITM_IMCR_INTEGRATION_Pos) /*!< ITM IMCR: INTEGRATION Mask */ + +/* ITM Lock Status Register Definitions */ +#define ITM_LSR_ByteAcc_Pos 2 /*!< ITM LSR: ByteAcc Position */ +#define ITM_LSR_ByteAcc_Msk (1ul << ITM_LSR_ByteAcc_Pos) /*!< ITM LSR: ByteAcc Mask */ + +#define ITM_LSR_Access_Pos 1 /*!< ITM LSR: Access Position */ +#define ITM_LSR_Access_Msk (1ul << ITM_LSR_Access_Pos) /*!< ITM LSR: Access Mask */ + +#define ITM_LSR_Present_Pos 0 /*!< ITM LSR: Present Position */ +#define ITM_LSR_Present_Msk (1ul << ITM_LSR_Present_Pos) /*!< ITM LSR: Present Mask */ +/*@}*/ /* end of group CMSIS_CM3_ITM */ + + +/** @addtogroup CMSIS_CM3_InterruptType CMSIS CM3 Interrupt Type + memory mapped structure for Interrupt Type + @{ + */ +typedef struct +{ + uint32_t RESERVED0; + __I uint32_t ICTR; /*!< Offset: 0x04 Interrupt Control Type Register */ +#if ((defined __CM3_REV) && (__CM3_REV >= 0x200)) + __IO uint32_t ACTLR; /*!< Offset: 0x08 Auxiliary Control Register */ +#else + uint32_t RESERVED1; +#endif +} InterruptType_Type; + +/* Interrupt Controller Type Register Definitions */ +#define InterruptType_ICTR_INTLINESNUM_Pos 0 /*!< InterruptType ICTR: INTLINESNUM Position */ +#define InterruptType_ICTR_INTLINESNUM_Msk (0x1Ful << InterruptType_ICTR_INTLINESNUM_Pos) /*!< InterruptType ICTR: INTLINESNUM Mask */ + +/* Auxiliary Control Register Definitions */ +#define InterruptType_ACTLR_DISFOLD_Pos 2 /*!< InterruptType ACTLR: DISFOLD Position */ +#define InterruptType_ACTLR_DISFOLD_Msk (1ul << InterruptType_ACTLR_DISFOLD_Pos) /*!< InterruptType ACTLR: DISFOLD Mask */ + +#define InterruptType_ACTLR_DISDEFWBUF_Pos 1 /*!< InterruptType ACTLR: DISDEFWBUF Position */ +#define InterruptType_ACTLR_DISDEFWBUF_Msk (1ul << InterruptType_ACTLR_DISDEFWBUF_Pos) /*!< InterruptType ACTLR: DISDEFWBUF Mask */ + +#define InterruptType_ACTLR_DISMCYCINT_Pos 0 /*!< InterruptType ACTLR: DISMCYCINT Position */ +#define InterruptType_ACTLR_DISMCYCINT_Msk (1ul << InterruptType_ACTLR_DISMCYCINT_Pos) /*!< InterruptType ACTLR: DISMCYCINT Mask */ +/*@}*/ /* end of group CMSIS_CM3_InterruptType */ + + +#if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1) +/** @addtogroup CMSIS_CM3_MPU CMSIS CM3 MPU + memory mapped structure for Memory Protection Unit (MPU) + @{ + */ +typedef struct +{ + __I uint32_t TYPE; /*!< Offset: 0x00 MPU Type Register */ + __IO uint32_t CTRL; /*!< Offset: 0x04 MPU Control Register */ + __IO uint32_t RNR; /*!< Offset: 0x08 MPU Region RNRber Register */ + __IO uint32_t RBAR; /*!< Offset: 0x0C MPU Region Base Address Register */ + __IO uint32_t RASR; /*!< Offset: 0x10 MPU Region Attribute and Size Register */ + __IO uint32_t RBAR_A1; /*!< Offset: 0x14 MPU Alias 1 Region Base Address Register */ + __IO uint32_t RASR_A1; /*!< Offset: 0x18 MPU Alias 1 Region Attribute and Size Register */ + __IO uint32_t RBAR_A2; /*!< Offset: 0x1C MPU Alias 2 Region Base Address Register */ + __IO uint32_t RASR_A2; /*!< Offset: 0x20 MPU Alias 2 Region Attribute and Size Register */ + __IO uint32_t RBAR_A3; /*!< Offset: 0x24 MPU Alias 3 Region Base Address Register */ + __IO uint32_t RASR_A3; /*!< Offset: 0x28 MPU Alias 3 Region Attribute and Size Register */ +} MPU_Type; + +/* MPU Type Register */ +#define MPU_TYPE_IREGION_Pos 16 /*!< MPU TYPE: IREGION Position */ +#define MPU_TYPE_IREGION_Msk (0xFFul << MPU_TYPE_IREGION_Pos) /*!< MPU TYPE: IREGION Mask */ + +#define MPU_TYPE_DREGION_Pos 8 /*!< MPU TYPE: DREGION Position */ +#define MPU_TYPE_DREGION_Msk (0xFFul << MPU_TYPE_DREGION_Pos) /*!< MPU TYPE: DREGION Mask */ + +#define MPU_TYPE_SEPARATE_Pos 0 /*!< MPU TYPE: SEPARATE Position */ +#define MPU_TYPE_SEPARATE_Msk (1ul << MPU_TYPE_SEPARATE_Pos) /*!< MPU TYPE: SEPARATE Mask */ + +/* MPU Control Register */ +#define MPU_CTRL_PRIVDEFENA_Pos 2 /*!< MPU CTRL: PRIVDEFENA Position */ +#define MPU_CTRL_PRIVDEFENA_Msk (1ul << MPU_CTRL_PRIVDEFENA_Pos) /*!< MPU CTRL: PRIVDEFENA Mask */ + +#define MPU_CTRL_HFNMIENA_Pos 1 /*!< MPU CTRL: HFNMIENA Position */ +#define MPU_CTRL_HFNMIENA_Msk (1ul << MPU_CTRL_HFNMIENA_Pos) /*!< MPU CTRL: HFNMIENA Mask */ + +#define MPU_CTRL_ENABLE_Pos 0 /*!< MPU CTRL: ENABLE Position */ +#define MPU_CTRL_ENABLE_Msk (1ul << MPU_CTRL_ENABLE_Pos) /*!< MPU CTRL: ENABLE Mask */ + +/* MPU Region Number Register */ +#define MPU_RNR_REGION_Pos 0 /*!< MPU RNR: REGION Position */ +#define MPU_RNR_REGION_Msk (0xFFul << MPU_RNR_REGION_Pos) /*!< MPU RNR: REGION Mask */ + +/* MPU Region Base Address Register */ +#define MPU_RBAR_ADDR_Pos 5 /*!< MPU RBAR: ADDR Position */ +#define MPU_RBAR_ADDR_Msk (0x7FFFFFFul << MPU_RBAR_ADDR_Pos) /*!< MPU RBAR: ADDR Mask */ + +#define MPU_RBAR_VALID_Pos 4 /*!< MPU RBAR: VALID Position */ +#define MPU_RBAR_VALID_Msk (1ul << MPU_RBAR_VALID_Pos) /*!< MPU RBAR: VALID Mask */ + +#define MPU_RBAR_REGION_Pos 0 /*!< MPU RBAR: REGION Position */ +#define MPU_RBAR_REGION_Msk (0xFul << MPU_RBAR_REGION_Pos) /*!< MPU RBAR: REGION Mask */ + +/* MPU Region Attribute and Size Register */ +#define MPU_RASR_XN_Pos 28 /*!< MPU RASR: XN Position */ +#define MPU_RASR_XN_Msk (1ul << MPU_RASR_XN_Pos) /*!< MPU RASR: XN Mask */ + +#define MPU_RASR_AP_Pos 24 /*!< MPU RASR: AP Position */ +#define MPU_RASR_AP_Msk (7ul << MPU_RASR_AP_Pos) /*!< MPU RASR: AP Mask */ + +#define MPU_RASR_TEX_Pos 19 /*!< MPU RASR: TEX Position */ +#define MPU_RASR_TEX_Msk (7ul << MPU_RASR_TEX_Pos) /*!< MPU RASR: TEX Mask */ + +#define MPU_RASR_S_Pos 18 /*!< MPU RASR: Shareable bit Position */ +#define MPU_RASR_S_Msk (1ul << MPU_RASR_S_Pos) /*!< MPU RASR: Shareable bit Mask */ + +#define MPU_RASR_C_Pos 17 /*!< MPU RASR: Cacheable bit Position */ +#define MPU_RASR_C_Msk (1ul << MPU_RASR_C_Pos) /*!< MPU RASR: Cacheable bit Mask */ + +#define MPU_RASR_B_Pos 16 /*!< MPU RASR: Bufferable bit Position */ +#define MPU_RASR_B_Msk (1ul << MPU_RASR_B_Pos) /*!< MPU RASR: Bufferable bit Mask */ + +#define MPU_RASR_SRD_Pos 8 /*!< MPU RASR: Sub-Region Disable Position */ +#define MPU_RASR_SRD_Msk (0xFFul << MPU_RASR_SRD_Pos) /*!< MPU RASR: Sub-Region Disable Mask */ + +#define MPU_RASR_SIZE_Pos 1 /*!< MPU RASR: Region Size Field Position */ +#define MPU_RASR_SIZE_Msk (0x1Ful << MPU_RASR_SIZE_Pos) /*!< MPU RASR: Region Size Field Mask */ + +#define MPU_RASR_ENA_Pos 0 /*!< MPU RASR: Region enable bit Position */ +#define MPU_RASR_ENA_Msk (0x1Ful << MPU_RASR_ENA_Pos) /*!< MPU RASR: Region enable bit Disable Mask */ + +/*@}*/ /* end of group CMSIS_CM3_MPU */ +#endif + + +/** @addtogroup CMSIS_CM3_CoreDebug CMSIS CM3 Core Debug + memory mapped structure for Core Debug Register + @{ + */ +typedef struct +{ + __IO uint32_t DHCSR; /*!< Offset: 0x00 Debug Halting Control and Status Register */ + __O uint32_t DCRSR; /*!< Offset: 0x04 Debug Core Register Selector Register */ + __IO uint32_t DCRDR; /*!< Offset: 0x08 Debug Core Register Data Register */ + __IO uint32_t DEMCR; /*!< Offset: 0x0C Debug Exception and Monitor Control Register */ +} CoreDebug_Type; + +/* Debug Halting Control and Status Register */ +#define CoreDebug_DHCSR_DBGKEY_Pos 16 /*!< CoreDebug DHCSR: DBGKEY Position */ +#define CoreDebug_DHCSR_DBGKEY_Msk (0xFFFFul << CoreDebug_DHCSR_DBGKEY_Pos) /*!< CoreDebug DHCSR: DBGKEY Mask */ + +#define CoreDebug_DHCSR_S_RESET_ST_Pos 25 /*!< CoreDebug DHCSR: S_RESET_ST Position */ +#define CoreDebug_DHCSR_S_RESET_ST_Msk (1ul << CoreDebug_DHCSR_S_RESET_ST_Pos) /*!< CoreDebug DHCSR: S_RESET_ST Mask */ + +#define CoreDebug_DHCSR_S_RETIRE_ST_Pos 24 /*!< CoreDebug DHCSR: S_RETIRE_ST Position */ +#define CoreDebug_DHCSR_S_RETIRE_ST_Msk (1ul << CoreDebug_DHCSR_S_RETIRE_ST_Pos) /*!< CoreDebug DHCSR: S_RETIRE_ST Mask */ + +#define CoreDebug_DHCSR_S_LOCKUP_Pos 19 /*!< CoreDebug DHCSR: S_LOCKUP Position */ +#define CoreDebug_DHCSR_S_LOCKUP_Msk (1ul << CoreDebug_DHCSR_S_LOCKUP_Pos) /*!< CoreDebug DHCSR: S_LOCKUP Mask */ + +#define CoreDebug_DHCSR_S_SLEEP_Pos 18 /*!< CoreDebug DHCSR: S_SLEEP Position */ +#define CoreDebug_DHCSR_S_SLEEP_Msk (1ul << CoreDebug_DHCSR_S_SLEEP_Pos) /*!< CoreDebug DHCSR: S_SLEEP Mask */ + +#define CoreDebug_DHCSR_S_HALT_Pos 17 /*!< CoreDebug DHCSR: S_HALT Position */ +#define CoreDebug_DHCSR_S_HALT_Msk (1ul << CoreDebug_DHCSR_S_HALT_Pos) /*!< CoreDebug DHCSR: S_HALT Mask */ + +#define CoreDebug_DHCSR_S_REGRDY_Pos 16 /*!< CoreDebug DHCSR: S_REGRDY Position */ +#define CoreDebug_DHCSR_S_REGRDY_Msk (1ul << CoreDebug_DHCSR_S_REGRDY_Pos) /*!< CoreDebug DHCSR: S_REGRDY Mask */ + +#define CoreDebug_DHCSR_C_SNAPSTALL_Pos 5 /*!< CoreDebug DHCSR: C_SNAPSTALL Position */ +#define CoreDebug_DHCSR_C_SNAPSTALL_Msk (1ul << CoreDebug_DHCSR_C_SNAPSTALL_Pos) /*!< CoreDebug DHCSR: C_SNAPSTALL Mask */ + +#define CoreDebug_DHCSR_C_MASKINTS_Pos 3 /*!< CoreDebug DHCSR: C_MASKINTS Position */ +#define CoreDebug_DHCSR_C_MASKINTS_Msk (1ul << CoreDebug_DHCSR_C_MASKINTS_Pos) /*!< CoreDebug DHCSR: C_MASKINTS Mask */ + +#define CoreDebug_DHCSR_C_STEP_Pos 2 /*!< CoreDebug DHCSR: C_STEP Position */ +#define CoreDebug_DHCSR_C_STEP_Msk (1ul << CoreDebug_DHCSR_C_STEP_Pos) /*!< CoreDebug DHCSR: C_STEP Mask */ + +#define CoreDebug_DHCSR_C_HALT_Pos 1 /*!< CoreDebug DHCSR: C_HALT Position */ +#define CoreDebug_DHCSR_C_HALT_Msk (1ul << CoreDebug_DHCSR_C_HALT_Pos) /*!< CoreDebug DHCSR: C_HALT Mask */ + +#define CoreDebug_DHCSR_C_DEBUGEN_Pos 0 /*!< CoreDebug DHCSR: C_DEBUGEN Position */ +#define CoreDebug_DHCSR_C_DEBUGEN_Msk (1ul << CoreDebug_DHCSR_C_DEBUGEN_Pos) /*!< CoreDebug DHCSR: C_DEBUGEN Mask */ + +/* Debug Core Register Selector Register */ +#define CoreDebug_DCRSR_REGWnR_Pos 16 /*!< CoreDebug DCRSR: REGWnR Position */ +#define CoreDebug_DCRSR_REGWnR_Msk (1ul << CoreDebug_DCRSR_REGWnR_Pos) /*!< CoreDebug DCRSR: REGWnR Mask */ + +#define CoreDebug_DCRSR_REGSEL_Pos 0 /*!< CoreDebug DCRSR: REGSEL Position */ +#define CoreDebug_DCRSR_REGSEL_Msk (0x1Ful << CoreDebug_DCRSR_REGSEL_Pos) /*!< CoreDebug DCRSR: REGSEL Mask */ + +/* Debug Exception and Monitor Control Register */ +#define CoreDebug_DEMCR_TRCENA_Pos 24 /*!< CoreDebug DEMCR: TRCENA Position */ +#define CoreDebug_DEMCR_TRCENA_Msk (1ul << CoreDebug_DEMCR_TRCENA_Pos) /*!< CoreDebug DEMCR: TRCENA Mask */ + +#define CoreDebug_DEMCR_MON_REQ_Pos 19 /*!< CoreDebug DEMCR: MON_REQ Position */ +#define CoreDebug_DEMCR_MON_REQ_Msk (1ul << CoreDebug_DEMCR_MON_REQ_Pos) /*!< CoreDebug DEMCR: MON_REQ Mask */ + +#define CoreDebug_DEMCR_MON_STEP_Pos 18 /*!< CoreDebug DEMCR: MON_STEP Position */ +#define CoreDebug_DEMCR_MON_STEP_Msk (1ul << CoreDebug_DEMCR_MON_STEP_Pos) /*!< CoreDebug DEMCR: MON_STEP Mask */ + +#define CoreDebug_DEMCR_MON_PEND_Pos 17 /*!< CoreDebug DEMCR: MON_PEND Position */ +#define CoreDebug_DEMCR_MON_PEND_Msk (1ul << CoreDebug_DEMCR_MON_PEND_Pos) /*!< CoreDebug DEMCR: MON_PEND Mask */ + +#define CoreDebug_DEMCR_MON_EN_Pos 16 /*!< CoreDebug DEMCR: MON_EN Position */ +#define CoreDebug_DEMCR_MON_EN_Msk (1ul << CoreDebug_DEMCR_MON_EN_Pos) /*!< CoreDebug DEMCR: MON_EN Mask */ + +#define CoreDebug_DEMCR_VC_HARDERR_Pos 10 /*!< CoreDebug DEMCR: VC_HARDERR Position */ +#define CoreDebug_DEMCR_VC_HARDERR_Msk (1ul << CoreDebug_DEMCR_VC_HARDERR_Pos) /*!< CoreDebug DEMCR: VC_HARDERR Mask */ + +#define CoreDebug_DEMCR_VC_INTERR_Pos 9 /*!< CoreDebug DEMCR: VC_INTERR Position */ +#define CoreDebug_DEMCR_VC_INTERR_Msk (1ul << CoreDebug_DEMCR_VC_INTERR_Pos) /*!< CoreDebug DEMCR: VC_INTERR Mask */ + +#define CoreDebug_DEMCR_VC_BUSERR_Pos 8 /*!< CoreDebug DEMCR: VC_BUSERR Position */ +#define CoreDebug_DEMCR_VC_BUSERR_Msk (1ul << CoreDebug_DEMCR_VC_BUSERR_Pos) /*!< CoreDebug DEMCR: VC_BUSERR Mask */ + +#define CoreDebug_DEMCR_VC_STATERR_Pos 7 /*!< CoreDebug DEMCR: VC_STATERR Position */ +#define CoreDebug_DEMCR_VC_STATERR_Msk (1ul << CoreDebug_DEMCR_VC_STATERR_Pos) /*!< CoreDebug DEMCR: VC_STATERR Mask */ + +#define CoreDebug_DEMCR_VC_CHKERR_Pos 6 /*!< CoreDebug DEMCR: VC_CHKERR Position */ +#define CoreDebug_DEMCR_VC_CHKERR_Msk (1ul << CoreDebug_DEMCR_VC_CHKERR_Pos) /*!< CoreDebug DEMCR: VC_CHKERR Mask */ + +#define CoreDebug_DEMCR_VC_NOCPERR_Pos 5 /*!< CoreDebug DEMCR: VC_NOCPERR Position */ +#define CoreDebug_DEMCR_VC_NOCPERR_Msk (1ul << CoreDebug_DEMCR_VC_NOCPERR_Pos) /*!< CoreDebug DEMCR: VC_NOCPERR Mask */ + +#define CoreDebug_DEMCR_VC_MMERR_Pos 4 /*!< CoreDebug DEMCR: VC_MMERR Position */ +#define CoreDebug_DEMCR_VC_MMERR_Msk (1ul << CoreDebug_DEMCR_VC_MMERR_Pos) /*!< CoreDebug DEMCR: VC_MMERR Mask */ + +#define CoreDebug_DEMCR_VC_CORERESET_Pos 0 /*!< CoreDebug DEMCR: VC_CORERESET Position */ +#define CoreDebug_DEMCR_VC_CORERESET_Msk (1ul << CoreDebug_DEMCR_VC_CORERESET_Pos) /*!< CoreDebug DEMCR: VC_CORERESET Mask */ +/*@}*/ /* end of group CMSIS_CM3_CoreDebug */ + + +/* Memory mapping of Cortex-M3 Hardware */ +#define SCS_BASE (0xE000E000) /*!< System Control Space Base Address */ +#define ITM_BASE (0xE0000000) /*!< ITM Base Address */ +#define CoreDebug_BASE (0xE000EDF0) /*!< Core Debug Base Address */ +#define SysTick_BASE (SCS_BASE + 0x0010) /*!< SysTick Base Address */ +#define NVIC_BASE (SCS_BASE + 0x0100) /*!< NVIC Base Address */ +#define SCB_BASE (SCS_BASE + 0x0D00) /*!< System Control Block Base Address */ + +#define InterruptType ((InterruptType_Type *) SCS_BASE) /*!< Interrupt Type Register */ +#define SCB ((SCB_Type *) SCB_BASE) /*!< SCB configuration struct */ +#define SysTick ((SysTick_Type *) SysTick_BASE) /*!< SysTick configuration struct */ +#define NVIC ((NVIC_Type *) NVIC_BASE) /*!< NVIC configuration struct */ +#define ITM ((ITM_Type *) ITM_BASE) /*!< ITM configuration struct */ +#define CoreDebug ((CoreDebug_Type *) CoreDebug_BASE) /*!< Core Debug configuration struct */ + +#if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1) + #define MPU_BASE (SCS_BASE + 0x0D90) /*!< Memory Protection Unit */ + #define MPU ((MPU_Type*) MPU_BASE) /*!< Memory Protection Unit */ +#endif + +/*@}*/ /* end of group CMSIS_CM3_core_register */ + + +/******************************************************************************* + * Hardware Abstraction Layer + ******************************************************************************/ + +#if defined ( __CC_ARM ) + #define __ASM __asm /*!< asm keyword for ARM Compiler */ + #define __INLINE __inline /*!< inline keyword for ARM Compiler */ + +#elif defined ( __ICCARM__ ) + #define __ASM __asm /*!< asm keyword for IAR Compiler */ + #define __INLINE inline /*!< inline keyword for IAR Compiler. Only avaiable in High optimization mode! */ + +#elif defined ( __GNUC__ ) + #define __ASM __asm /*!< asm keyword for GNU Compiler */ + #define __INLINE inline /*!< inline keyword for GNU Compiler */ + +#elif defined ( __TASKING__ ) + #define __ASM __asm /*!< asm keyword for TASKING Compiler */ + #define __INLINE inline /*!< inline keyword for TASKING Compiler */ + +#endif + + +/* ################### Compiler specific Intrinsics ########################### */ + +#if defined ( __CC_ARM ) /*------------------RealView Compiler -----------------*/ +/* ARM armcc specific functions */ + +#define __enable_fault_irq __enable_fiq +#define __disable_fault_irq __disable_fiq + +#define __NOP __nop +#define __WFI __wfi +#define __WFE __wfe +#define __SEV __sev +#define __ISB() __isb(0) +#define __DSB() __dsb(0) +#define __DMB() __dmb(0) +#define __REV __rev +#define __RBIT __rbit +#define __LDREXB(ptr) ((unsigned char ) __ldrex(ptr)) +#define __LDREXH(ptr) ((unsigned short) __ldrex(ptr)) +#define __LDREXW(ptr) ((unsigned int ) __ldrex(ptr)) +#define __STREXB(value, ptr) __strex(value, ptr) +#define __STREXH(value, ptr) __strex(value, ptr) +#define __STREXW(value, ptr) __strex(value, ptr) + + +/* intrinsic unsigned long long __ldrexd(volatile void *ptr) */ +/* intrinsic int __strexd(unsigned long long val, volatile void *ptr) */ +/* intrinsic void __enable_irq(); */ +/* intrinsic void __disable_irq(); */ + + +/** + * @brief Return the Process Stack Pointer + * + * @return ProcessStackPointer + * + * Return the actual process stack pointer + */ +extern uint32_t __get_PSP(void); + +/** + * @brief Set the Process Stack Pointer + * + * @param topOfProcStack Process Stack Pointer + * + * Assign the value ProcessStackPointer to the MSP + * (process stack pointer) Cortex processor register + */ +extern void __set_PSP(uint32_t topOfProcStack); + +/** + * @brief Return the Main Stack Pointer + * + * @return Main Stack Pointer + * + * Return the current value of the MSP (main stack pointer) + * Cortex processor register + */ +extern uint32_t __get_MSP(void); + +/** + * @brief Set the Main Stack Pointer + * + * @param topOfMainStack Main Stack Pointer + * + * Assign the value mainStackPointer to the MSP + * (main stack pointer) Cortex processor register + */ +extern void __set_MSP(uint32_t topOfMainStack); + +/** + * @brief Reverse byte order in unsigned short value + * + * @param value value to reverse + * @return reversed value + * + * Reverse byte order in unsigned short value + */ +extern uint32_t __REV16(uint16_t value); + +/** + * @brief Reverse byte order in signed short value with sign extension to integer + * + * @param value value to reverse + * @return reversed value + * + * Reverse byte order in signed short value with sign extension to integer + */ +extern int32_t __REVSH(int16_t value); + + +#if (__ARMCC_VERSION < 400000) + +/** + * @brief Remove the exclusive lock created by ldrex + * + * Removes the exclusive lock which is created by ldrex. + */ +extern void __CLREX(void); + +/** + * @brief Return the Base Priority value + * + * @return BasePriority + * + * Return the content of the base priority register + */ +extern uint32_t __get_BASEPRI(void); + +/** + * @brief Set the Base Priority value + * + * @param basePri BasePriority + * + * Set the base priority register + */ +extern void __set_BASEPRI(uint32_t basePri); + +/** + * @brief Return the Priority Mask value + * + * @return PriMask + * + * Return state of the priority mask bit from the priority mask register + */ +extern uint32_t __get_PRIMASK(void); + +/** + * @brief Set the Priority Mask value + * + * @param priMask PriMask + * + * Set the priority mask bit in the priority mask register + */ +extern void __set_PRIMASK(uint32_t priMask); + +/** + * @brief Return the Fault Mask value + * + * @return FaultMask + * + * Return the content of the fault mask register + */ +extern uint32_t __get_FAULTMASK(void); + +/** + * @brief Set the Fault Mask value + * + * @param faultMask faultMask value + * + * Set the fault mask register + */ +extern void __set_FAULTMASK(uint32_t faultMask); + +/** + * @brief Return the Control Register value + * + * @return Control value + * + * Return the content of the control register + */ +extern uint32_t __get_CONTROL(void); + +/** + * @brief Set the Control Register value + * + * @param control Control value + * + * Set the control register + */ +extern void __set_CONTROL(uint32_t control); + +#else /* (__ARMCC_VERSION >= 400000) */ + +/** + * @brief Remove the exclusive lock created by ldrex + * + * Removes the exclusive lock which is created by ldrex. + */ +#define __CLREX __clrex + +/** + * @brief Return the Base Priority value + * + * @return BasePriority + * + * Return the content of the base priority register + */ +static __INLINE uint32_t __get_BASEPRI(void) +{ + register uint32_t __regBasePri __ASM("basepri"); + return(__regBasePri); +} + +/** + * @brief Set the Base Priority value + * + * @param basePri BasePriority + * + * Set the base priority register + */ +static __INLINE void __set_BASEPRI(uint32_t basePri) +{ + register uint32_t __regBasePri __ASM("basepri"); + __regBasePri = (basePri & 0xff); +} + +/** + * @brief Return the Priority Mask value + * + * @return PriMask + * + * Return state of the priority mask bit from the priority mask register + */ +static __INLINE uint32_t __get_PRIMASK(void) +{ + register uint32_t __regPriMask __ASM("primask"); + return(__regPriMask); +} + +/** + * @brief Set the Priority Mask value + * + * @param priMask PriMask + * + * Set the priority mask bit in the priority mask register + */ +static __INLINE void __set_PRIMASK(uint32_t priMask) +{ + register uint32_t __regPriMask __ASM("primask"); + __regPriMask = (priMask); +} + +/** + * @brief Return the Fault Mask value + * + * @return FaultMask + * + * Return the content of the fault mask register + */ +static __INLINE uint32_t __get_FAULTMASK(void) +{ + register uint32_t __regFaultMask __ASM("faultmask"); + return(__regFaultMask); +} + +/** + * @brief Set the Fault Mask value + * + * @param faultMask faultMask value + * + * Set the fault mask register + */ +static __INLINE void __set_FAULTMASK(uint32_t faultMask) +{ + register uint32_t __regFaultMask __ASM("faultmask"); + __regFaultMask = (faultMask & 1); +} + +/** + * @brief Return the Control Register value + * + * @return Control value + * + * Return the content of the control register + */ +static __INLINE uint32_t __get_CONTROL(void) +{ + register uint32_t __regControl __ASM("control"); + return(__regControl); +} + +/** + * @brief Set the Control Register value + * + * @param control Control value + * + * Set the control register + */ +static __INLINE void __set_CONTROL(uint32_t control) +{ + register uint32_t __regControl __ASM("control"); + __regControl = control; +} + +#endif /* __ARMCC_VERSION */ + + + +#elif (defined (__ICCARM__)) /*------------------ ICC Compiler -------------------*/ +/* IAR iccarm specific functions */ + +#define __enable_irq __enable_interrupt /*!< global Interrupt enable */ +#define __disable_irq __disable_interrupt /*!< global Interrupt disable */ + +static __INLINE void __enable_fault_irq() { __ASM ("cpsie f"); } +static __INLINE void __disable_fault_irq() { __ASM ("cpsid f"); } + +#define __NOP __no_operation /*!< no operation intrinsic in IAR Compiler */ +static __INLINE void __WFI() { __ASM ("wfi"); } +static __INLINE void __WFE() { __ASM ("wfe"); } +static __INLINE void __SEV() { __ASM ("sev"); } +static __INLINE void __CLREX() { __ASM ("clrex"); } + +/* intrinsic void __ISB(void) */ +/* intrinsic void __DSB(void) */ +/* intrinsic void __DMB(void) */ +/* intrinsic void __set_PRIMASK(); */ +/* intrinsic void __get_PRIMASK(); */ +/* intrinsic void __set_FAULTMASK(); */ +/* intrinsic void __get_FAULTMASK(); */ +/* intrinsic uint32_t __REV(uint32_t value); */ +/* intrinsic uint32_t __REVSH(uint32_t value); */ +/* intrinsic unsigned long __STREX(unsigned long, unsigned long); */ +/* intrinsic unsigned long __LDREX(unsigned long *); */ + + +/** + * @brief Return the Process Stack Pointer + * + * @return ProcessStackPointer + * + * Return the actual process stack pointer + */ +#if (__VER__ < 6020000) +extern uint32_t __get_PSP(void); +#endif + +/** + * @brief Set the Process Stack Pointer + * + * @param topOfProcStack Process Stack Pointer + * + * Assign the value ProcessStackPointer to the MSP + * (process stack pointer) Cortex processor register + */ +#if (__VER__ < 6020000) +extern void __set_PSP(uint32_t topOfProcStack); +#endif + +/** + * @brief Return the Main Stack Pointer + * + * @return Main Stack Pointer + * + * Return the current value of the MSP (main stack pointer) + * Cortex processor register + */ +#if (__VER__ < 6020000) +extern uint32_t __get_MSP(void); +#endif + +/** + * @brief Set the Main Stack Pointer + * + * @param topOfMainStack Main Stack Pointer + * + * Assign the value mainStackPointer to the MSP + * (main stack pointer) Cortex processor register + */ +#if (__VER__ < 6020000) +extern void __set_MSP(uint32_t topOfMainStack); +#endif + +/** + * @brief Reverse byte order in unsigned short value + * + * @param value value to reverse + * @return reversed value + * + * Reverse byte order in unsigned short value + */ +#if (__VER__ < 6020000) +extern uint32_t __REV16(uint16_t value); +#endif + +/** + * @brief Reverse bit order of value + * + * @param value value to reverse + * @return reversed value + * + * Reverse bit order of value + */ +#if (__VER__ < 6020000) +extern uint32_t __RBIT(uint32_t value); +#endif + +/** + * @brief LDR Exclusive (8 bit) + * + * @param *addr address pointer + * @return value of (*address) + * + * Exclusive LDR command for 8 bit values) + */ +#if (__VER__ < 6020000) +extern uint8_t __LDREXB(uint8_t *addr); +#endif + +/** + * @brief LDR Exclusive (16 bit) + * + * @param *addr address pointer + * @return value of (*address) + * + * Exclusive LDR command for 16 bit values + */ +#if (__VER__ < 6020000) +extern uint16_t __LDREXH(uint16_t *addr); +#endif + +/** + * @brief LDR Exclusive (32 bit) + * + * @param *addr address pointer + * @return value of (*address) + * + * Exclusive LDR command for 32 bit values + */ +extern uint32_t __LDREXW(uint32_t *addr); + +/** + * @brief STR Exclusive (8 bit) + * + * @param value value to store + * @param *addr address pointer + * @return successful / failed + * + * Exclusive STR command for 8 bit values + */ +#if (__VER__ < 6020000) +extern uint32_t __STREXB(uint8_t value, uint8_t *addr); +#endif + +/** + * @brief STR Exclusive (16 bit) + * + * @param value value to store + * @param *addr address pointer + * @return successful / failed + * + * Exclusive STR command for 16 bit values + */ +#if (__VER__ < 6020000) +extern uint32_t __STREXH(uint16_t value, uint16_t *addr); +#endif + +/** + * @brief STR Exclusive (32 bit) + * + * @param value value to store + * @param *addr address pointer + * @return successful / failed + * + * Exclusive STR command for 32 bit values + */ +extern uint32_t __STREXW(uint32_t value, uint32_t *addr); + + + +#elif (defined (__GNUC__)) /*------------------ GNU Compiler ---------------------*/ +/* GNU gcc specific functions */ + +static __INLINE void __enable_irq(void) { __ASM volatile ("cpsie i"); } +static __INLINE void __disable_irq(void) { __ASM volatile ("cpsid i"); } + +static __INLINE void __enable_fault_irq(void) { __ASM volatile ("cpsie f"); } +static __INLINE void __disable_fault_irq(void) { __ASM volatile ("cpsid f"); } + +static __INLINE void __NOP(void) { __ASM volatile ("nop"); } +static __INLINE void __WFI(void) { __ASM volatile ("wfi"); } +static __INLINE void __WFE(void) { __ASM volatile ("wfe"); } +static __INLINE void __SEV(void) { __ASM volatile ("sev"); } +static __INLINE void __ISB(void) { __ASM volatile ("isb"); } +static __INLINE void __DSB(void) { __ASM volatile ("dsb"); } +static __INLINE void __DMB(void) { __ASM volatile ("dmb"); } +static __INLINE void __CLREX(void) { __ASM volatile ("clrex"); } + + +/** + * @brief Return the Process Stack Pointer + * + * @return ProcessStackPointer + * + * Return the actual process stack pointer + */ +extern uint32_t __get_PSP(void); + +/** + * @brief Set the Process Stack Pointer + * + * @param topOfProcStack Process Stack Pointer + * + * Assign the value ProcessStackPointer to the MSP + * (process stack pointer) Cortex processor register + */ +extern void __set_PSP(uint32_t topOfProcStack); + +/** + * @brief Return the Main Stack Pointer + * + * @return Main Stack Pointer + * + * Return the current value of the MSP (main stack pointer) + * Cortex processor register + */ +extern uint32_t __get_MSP(void); + +/** + * @brief Set the Main Stack Pointer + * + * @param topOfMainStack Main Stack Pointer + * + * Assign the value mainStackPointer to the MSP + * (main stack pointer) Cortex processor register + */ +extern void __set_MSP(uint32_t topOfMainStack); + +/** + * @brief Return the Base Priority value + * + * @return BasePriority + * + * Return the content of the base priority register + */ +extern uint32_t __get_BASEPRI(void); + +/** + * @brief Set the Base Priority value + * + * @param basePri BasePriority + * + * Set the base priority register + */ +extern void __set_BASEPRI(uint32_t basePri); + +/** + * @brief Return the Priority Mask value + * + * @return PriMask + * + * Return state of the priority mask bit from the priority mask register + */ +extern uint32_t __get_PRIMASK(void); + +/** + * @brief Set the Priority Mask value + * + * @param priMask PriMask + * + * Set the priority mask bit in the priority mask register + */ +extern void __set_PRIMASK(uint32_t priMask); + +/** + * @brief Return the Fault Mask value + * + * @return FaultMask + * + * Return the content of the fault mask register + */ +extern uint32_t __get_FAULTMASK(void); + +/** + * @brief Set the Fault Mask value + * + * @param faultMask faultMask value + * + * Set the fault mask register + */ +extern void __set_FAULTMASK(uint32_t faultMask); + +/** + * @brief Return the Control Register value +* +* @return Control value + * + * Return the content of the control register + */ +extern uint32_t __get_CONTROL(void); + +/** + * @brief Set the Control Register value + * + * @param control Control value + * + * Set the control register + */ +extern void __set_CONTROL(uint32_t control); + +/** + * @brief Reverse byte order in integer value + * + * @param value value to reverse + * @return reversed value + * + * Reverse byte order in integer value + */ +extern uint32_t __REV(uint32_t value); + +/** + * @brief Reverse byte order in unsigned short value + * + * @param value value to reverse + * @return reversed value + * + * Reverse byte order in unsigned short value + */ +extern uint32_t __REV16(uint16_t value); + +/** + * @brief Reverse byte order in signed short value with sign extension to integer + * + * @param value value to reverse + * @return reversed value + * + * Reverse byte order in signed short value with sign extension to integer + */ +extern int32_t __REVSH(int16_t value); + +/** + * @brief Reverse bit order of value + * + * @param value value to reverse + * @return reversed value + * + * Reverse bit order of value + */ +extern uint32_t __RBIT(uint32_t value); + +/** + * @brief LDR Exclusive (8 bit) + * + * @param *addr address pointer + * @return value of (*address) + * + * Exclusive LDR command for 8 bit value + */ +extern uint8_t __LDREXB(uint8_t *addr); + +/** + * @brief LDR Exclusive (16 bit) + * + * @param *addr address pointer + * @return value of (*address) + * + * Exclusive LDR command for 16 bit values + */ +extern uint16_t __LDREXH(uint16_t *addr); + +/** + * @brief LDR Exclusive (32 bit) + * + * @param *addr address pointer + * @return value of (*address) + * + * Exclusive LDR command for 32 bit values + */ +extern uint32_t __LDREXW(uint32_t *addr); + +/** + * @brief STR Exclusive (8 bit) + * + * @param value value to store + * @param *addr address pointer + * @return successful / failed + * + * Exclusive STR command for 8 bit values + */ +extern uint32_t __STREXB(uint8_t value, uint8_t *addr); + +/** + * @brief STR Exclusive (16 bit) + * + * @param value value to store + * @param *addr address pointer + * @return successful / failed + * + * Exclusive STR command for 16 bit values + */ +extern uint32_t __STREXH(uint16_t value, uint16_t *addr); + +/** + * @brief STR Exclusive (32 bit) + * + * @param value value to store + * @param *addr address pointer + * @return successful / failed + * + * Exclusive STR command for 32 bit values + */ +extern uint32_t __STREXW(uint32_t value, uint32_t *addr); + + +#elif (defined (__TASKING__)) /*------------------ TASKING Compiler ---------------------*/ +/* TASKING carm specific functions */ + +/* + * The CMSIS functions have been implemented as intrinsics in the compiler. + * Please use "carm -?i" to get an up to date list of all instrinsics, + * Including the CMSIS ones. + */ + +#endif + + +/** @addtogroup CMSIS_CM3_Core_FunctionInterface CMSIS CM3 Core Function Interface + Core Function Interface containing: + - Core NVIC Functions + - Core SysTick Functions + - Core Reset Functions +*/ +/*@{*/ + +/* ########################## NVIC functions #################################### */ + +/** + * @brief Set the Priority Grouping in NVIC Interrupt Controller + * + * @param PriorityGroup is priority grouping field + * + * Set the priority grouping field using the required unlock sequence. + * The parameter priority_grouping is assigned to the field + * SCB->AIRCR [10:8] PRIGROUP field. Only values from 0..7 are used. + * In case of a conflict between priority grouping and available + * priority bits (__NVIC_PRIO_BITS) the smallest possible priority group is set. + */ +static __INLINE void NVIC_SetPriorityGrouping(uint32_t PriorityGroup) +{ + uint32_t reg_value; + uint32_t PriorityGroupTmp = (PriorityGroup & 0x07); /* only values 0..7 are used */ + + reg_value = SCB->AIRCR; /* read old register configuration */ + reg_value &= ~(SCB_AIRCR_VECTKEY_Msk | SCB_AIRCR_PRIGROUP_Msk); /* clear bits to change */ + reg_value = (reg_value | + (0x5FA << SCB_AIRCR_VECTKEY_Pos) | + (PriorityGroupTmp << 8)); /* Insert write key and priorty group */ + SCB->AIRCR = reg_value; +} + +/** + * @brief Get the Priority Grouping from NVIC Interrupt Controller + * + * @return priority grouping field + * + * Get the priority grouping from NVIC Interrupt Controller. + * priority grouping is SCB->AIRCR [10:8] PRIGROUP field. + */ +static __INLINE uint32_t NVIC_GetPriorityGrouping(void) +{ + return ((SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) >> SCB_AIRCR_PRIGROUP_Pos); /* read priority grouping field */ +} + +/** + * @brief Enable Interrupt in NVIC Interrupt Controller + * + * @param IRQn The positive number of the external interrupt to enable + * + * Enable a device specific interupt in the NVIC interrupt controller. + * The interrupt number cannot be a negative value. + */ +static __INLINE void NVIC_EnableIRQ(IRQn_Type IRQn) +{ + NVIC->ISER[((uint32_t)(IRQn) >> 5)] = (1 << ((uint32_t)(IRQn) & 0x1F)); /* enable interrupt */ +} + +/** + * @brief Disable the interrupt line for external interrupt specified + * + * @param IRQn The positive number of the external interrupt to disable + * + * Disable a device specific interupt in the NVIC interrupt controller. + * The interrupt number cannot be a negative value. + */ +static __INLINE void NVIC_DisableIRQ(IRQn_Type IRQn) +{ + NVIC->ICER[((uint32_t)(IRQn) >> 5)] = (1 << ((uint32_t)(IRQn) & 0x1F)); /* disable interrupt */ +} + +/** + * @brief Read the interrupt pending bit for a device specific interrupt source + * + * @param IRQn The number of the device specifc interrupt + * @return 1 = interrupt pending, 0 = interrupt not pending + * + * Read the pending register in NVIC and return 1 if its status is pending, + * otherwise it returns 0 + */ +static __INLINE uint32_t NVIC_GetPendingIRQ(IRQn_Type IRQn) +{ + return((uint32_t) ((NVIC->ISPR[(uint32_t)(IRQn) >> 5] & (1 << ((uint32_t)(IRQn) & 0x1F)))?1:0)); /* Return 1 if pending else 0 */ +} + +/** + * @brief Set the pending bit for an external interrupt + * + * @param IRQn The number of the interrupt for set pending + * + * Set the pending bit for the specified interrupt. + * The interrupt number cannot be a negative value. + */ +static __INLINE void NVIC_SetPendingIRQ(IRQn_Type IRQn) +{ + NVIC->ISPR[((uint32_t)(IRQn) >> 5)] = (1 << ((uint32_t)(IRQn) & 0x1F)); /* set interrupt pending */ +} + +/** + * @brief Clear the pending bit for an external interrupt + * + * @param IRQn The number of the interrupt for clear pending + * + * Clear the pending bit for the specified interrupt. + * The interrupt number cannot be a negative value. + */ +static __INLINE void NVIC_ClearPendingIRQ(IRQn_Type IRQn) +{ + NVIC->ICPR[((uint32_t)(IRQn) >> 5)] = (1 << ((uint32_t)(IRQn) & 0x1F)); /* Clear pending interrupt */ +} + +/** + * @brief Read the active bit for an external interrupt + * + * @param IRQn The number of the interrupt for read active bit + * @return 1 = interrupt active, 0 = interrupt not active + * + * Read the active register in NVIC and returns 1 if its status is active, + * otherwise it returns 0. + */ +static __INLINE uint32_t NVIC_GetActive(IRQn_Type IRQn) +{ + return((uint32_t)((NVIC->IABR[(uint32_t)(IRQn) >> 5] & (1 << ((uint32_t)(IRQn) & 0x1F)))?1:0)); /* Return 1 if active else 0 */ +} + +/** + * @brief Set the priority for an interrupt + * + * @param IRQn The number of the interrupt for set priority + * @param priority The priority to set + * + * Set the priority for the specified interrupt. The interrupt + * number can be positive to specify an external (device specific) + * interrupt, or negative to specify an internal (core) interrupt. + * + * Note: The priority cannot be set for every core interrupt. + */ +static __INLINE void NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority) +{ + if(IRQn < 0) { + SCB->SHP[((uint32_t)(IRQn) & 0xF)-4] = ((priority << (8 - __NVIC_PRIO_BITS)) & 0xff); } /* set Priority for Cortex-M3 System Interrupts */ + else { + NVIC->IP[(uint32_t)(IRQn)] = ((priority << (8 - __NVIC_PRIO_BITS)) & 0xff); } /* set Priority for device specific Interrupts */ +} + +/** + * @brief Read the priority for an interrupt + * + * @param IRQn The number of the interrupt for get priority + * @return The priority for the interrupt + * + * Read the priority for the specified interrupt. The interrupt + * number can be positive to specify an external (device specific) + * interrupt, or negative to specify an internal (core) interrupt. + * + * The returned priority value is automatically aligned to the implemented + * priority bits of the microcontroller. + * + * Note: The priority cannot be set for every core interrupt. + */ +static __INLINE uint32_t NVIC_GetPriority(IRQn_Type IRQn) +{ + + if(IRQn < 0) { + return((uint32_t)(SCB->SHP[((uint32_t)(IRQn) & 0xF)-4] >> (8 - __NVIC_PRIO_BITS))); } /* get priority for Cortex-M3 system interrupts */ + else { + return((uint32_t)(NVIC->IP[(uint32_t)(IRQn)] >> (8 - __NVIC_PRIO_BITS))); } /* get priority for device specific interrupts */ +} + + +/** + * @brief Encode the priority for an interrupt + * + * @param PriorityGroup The used priority group + * @param PreemptPriority The preemptive priority value (starting from 0) + * @param SubPriority The sub priority value (starting from 0) + * @return The encoded priority for the interrupt + * + * Encode the priority for an interrupt with the given priority group, + * preemptive priority value and sub priority value. + * In case of a conflict between priority grouping and available + * priority bits (__NVIC_PRIO_BITS) the samllest possible priority group is set. + * + * The returned priority value can be used for NVIC_SetPriority(...) function + */ +static __INLINE uint32_t NVIC_EncodePriority (uint32_t PriorityGroup, uint32_t PreemptPriority, uint32_t SubPriority) +{ + uint32_t PriorityGroupTmp = (PriorityGroup & 0x07); /* only values 0..7 are used */ + uint32_t PreemptPriorityBits; + uint32_t SubPriorityBits; + + PreemptPriorityBits = ((7 - PriorityGroupTmp) > __NVIC_PRIO_BITS) ? __NVIC_PRIO_BITS : 7 - PriorityGroupTmp; + SubPriorityBits = ((PriorityGroupTmp + __NVIC_PRIO_BITS) < 7) ? 0 : PriorityGroupTmp - 7 + __NVIC_PRIO_BITS; + + return ( + ((PreemptPriority & ((1 << (PreemptPriorityBits)) - 1)) << SubPriorityBits) | + ((SubPriority & ((1 << (SubPriorityBits )) - 1))) + ); +} + + +/** + * @brief Decode the priority of an interrupt + * + * @param Priority The priority for the interrupt + * @param PriorityGroup The used priority group + * @param pPreemptPriority The preemptive priority value (starting from 0) + * @param pSubPriority The sub priority value (starting from 0) + * + * Decode an interrupt priority value with the given priority group to + * preemptive priority value and sub priority value. + * In case of a conflict between priority grouping and available + * priority bits (__NVIC_PRIO_BITS) the samllest possible priority group is set. + * + * The priority value can be retrieved with NVIC_GetPriority(...) function + */ +static __INLINE void NVIC_DecodePriority (uint32_t Priority, uint32_t PriorityGroup, uint32_t* pPreemptPriority, uint32_t* pSubPriority) +{ + uint32_t PriorityGroupTmp = (PriorityGroup & 0x07); /* only values 0..7 are used */ + uint32_t PreemptPriorityBits; + uint32_t SubPriorityBits; + + PreemptPriorityBits = ((7 - PriorityGroupTmp) > __NVIC_PRIO_BITS) ? __NVIC_PRIO_BITS : 7 - PriorityGroupTmp; + SubPriorityBits = ((PriorityGroupTmp + __NVIC_PRIO_BITS) < 7) ? 0 : PriorityGroupTmp - 7 + __NVIC_PRIO_BITS; + + *pPreemptPriority = (Priority >> SubPriorityBits) & ((1 << (PreemptPriorityBits)) - 1); + *pSubPriority = (Priority ) & ((1 << (SubPriorityBits )) - 1); +} + + + +/* ################################## SysTick function ############################################ */ + +#if (!defined (__Vendor_SysTickConfig)) || (__Vendor_SysTickConfig == 0) + +/** + * @brief Initialize and start the SysTick counter and its interrupt. + * + * @param ticks number of ticks between two interrupts + * @return 1 = failed, 0 = successful + * + * Initialise the system tick timer and its interrupt and start the + * system tick timer / counter in free running mode to generate + * periodical interrupts. + */ +static __INLINE uint32_t SysTick_Config(uint32_t ticks) +{ + if (ticks > SysTick_LOAD_RELOAD_Msk) return (1); /* Reload value impossible */ + + SysTick->LOAD = (ticks & SysTick_LOAD_RELOAD_Msk) - 1; /* set reload register */ + NVIC_SetPriority (SysTick_IRQn, (1<<__NVIC_PRIO_BITS) - 1); /* set Priority for Cortex-M0 System Interrupts */ + SysTick->VAL = 0; /* Load the SysTick Counter Value */ + SysTick->CTRL = SysTick_CTRL_CLKSOURCE_Msk | + SysTick_CTRL_TICKINT_Msk | + SysTick_CTRL_ENABLE_Msk; /* Enable SysTick IRQ and SysTick Timer */ + return (0); /* Function successful */ +} + +#endif + + + + +/* ################################## Reset function ############################################ */ + +/** + * @brief Initiate a system reset request. + * + * Initiate a system reset request to reset the MCU + */ +static __INLINE void NVIC_SystemReset(void) +{ + SCB->AIRCR = ((0x5FA << SCB_AIRCR_VECTKEY_Pos) | + (SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) | + SCB_AIRCR_SYSRESETREQ_Msk); /* Keep priority group unchanged */ + __DSB(); /* Ensure completion of memory access */ + while(1); /* wait until reset */ +} + +/*@}*/ /* end of group CMSIS_CM3_Core_FunctionInterface */ + + + +/* ##################################### Debug In/Output function ########################################### */ + +/** @addtogroup CMSIS_CM3_CoreDebugInterface CMSIS CM3 Core Debug Interface + Core Debug Interface containing: + - Core Debug Receive / Transmit Functions + - Core Debug Defines + - Core Debug Variables +*/ +/*@{*/ + +extern volatile int ITM_RxBuffer; /*!< variable to receive characters */ +#define ITM_RXBUFFER_EMPTY 0x5AA55AA5 /*!< value identifying ITM_RxBuffer is ready for next character */ + + +/** + * @brief Outputs a character via the ITM channel 0 + * + * @param ch character to output + * @return character to output + * + * The function outputs a character via the ITM channel 0. + * The function returns when no debugger is connected that has booked the output. + * It is blocking when a debugger is connected, but the previous character send is not transmitted. + */ +static __INLINE uint32_t ITM_SendChar (uint32_t ch) +{ + if ((CoreDebug->DEMCR & CoreDebug_DEMCR_TRCENA_Msk) && /* Trace enabled */ + (ITM->TCR & ITM_TCR_ITMENA_Msk) && /* ITM enabled */ + (ITM->TER & (1ul << 0) ) ) /* ITM Port #0 enabled */ + { + while (ITM->PORT[0].u32 == 0); + ITM->PORT[0].u8 = (uint8_t) ch; + } + return (ch); +} + + +/** + * @brief Inputs a character via variable ITM_RxBuffer + * + * @return received character, -1 = no character received + * + * The function inputs a character via variable ITM_RxBuffer. + * The function returns when no debugger is connected that has booked the output. + * It is blocking when a debugger is connected, but the previous character send is not transmitted. + */ +static __INLINE int ITM_ReceiveChar (void) { + int ch = -1; /* no character available */ + + if (ITM_RxBuffer != ITM_RXBUFFER_EMPTY) { + ch = ITM_RxBuffer; + ITM_RxBuffer = ITM_RXBUFFER_EMPTY; /* ready for next character */ + } + + return (ch); +} + + +/** + * @brief Check if a character via variable ITM_RxBuffer is available + * + * @return 1 = character available, 0 = no character available + * + * The function checks variable ITM_RxBuffer whether a character is available or not. + * The function returns '1' if a character is available and '0' if no character is available. + */ +static __INLINE int ITM_CheckChar (void) { + + if (ITM_RxBuffer == ITM_RXBUFFER_EMPTY) { + return (0); /* no character available */ + } else { + return (1); /* character available */ + } +} + +/*@}*/ /* end of group CMSIS_CM3_core_DebugInterface */ + + +#ifdef __cplusplus +} +#endif + +/*@}*/ /* end of group CMSIS_CM3_core_definitions */ + +#endif /* __CM3_CORE_H__ */ + +/*lint -restore */ diff --git a/bsp/smartfusion2/CMSIS/hw_reg_io.h b/bsp/smartfusion2/CMSIS/hw_reg_io.h new file mode 100644 index 0000000000..583099b293 --- /dev/null +++ b/bsp/smartfusion2/CMSIS/hw_reg_io.h @@ -0,0 +1,113 @@ +/******************************************************************************* + * (c) Copyright 2011-2013 Microsemi SoC Products Group. All rights reserved. + * + * SmartFusion2 Cortex Microcontroller Software Interface - Peripheral + * Access Layer. + * + * This file provides interfaces to perform register and register bit level + * read / write operations. These interfaces support bit-banding in case of + * Cortex-M3 CPU. + * + * SVN $Revision: 5263 $ + * SVN $Date: 2013-03-21 14:44:58 +0000 (Thu, 21 Mar 2013) $ + */ + +#ifndef HW_REG_IO_H_ +#define HW_REG_IO_H_ + +#include <stdint.h> /* Include standard types */ + +#if defined ( __CC_ARM ) + #define __INLINE __inline /*!< inline keyword for ARM Compiler */ + +#elif defined ( __ICCARM__ ) + #define __INLINE inline /*!< inline keyword for IAR Compiler. Only avaiable in High optimization mode! */ + +#elif defined ( __GNUC__ ) + #define __INLINE inline /*!< inline keyword for GNU Compiler */ +#endif + +/***************************************************************************************** + * Definitions for register access + */ + +#define HW_REG(addr) (*((volatile uint32_t *) (addr))) + +static __INLINE void write_reg32(volatile uint32_t * reg, uint32_t val) +{ + HW_REG(reg) = val; +} +static __INLINE void write_reg16(volatile uint16_t * reg, uint16_t val) +{ + HW_REG(reg) = val; +} +static __INLINE void write_reg8(volatile uint8_t * reg, uint8_t val) +{ + HW_REG(reg) = val; +} + +static __INLINE uint32_t read_reg32(volatile uint32_t * reg) +{ + return ( HW_REG(reg) ); +} +static __INLINE uint16_t read_reg16(volatile uint16_t * reg) +{ + return ( HW_REG(reg) ); +} +static __INLINE uint8_t read_reg8(volatile uint8_t * reg) +{ + return ( HW_REG(reg) ); +} +/***************************************************************************************** + * Definitions for register bits access using bit-band aliases for Cortex-M3 + */ +#define BITBAND(addr,bitnum) (((uint32_t)addr & 0xF0000000)+0x02000000+(((uint32_t)addr & 0xFFFFF)<<5)+(bitnum<<2)) +#define HW_REG_BIT(reg,bitnum) (*(volatile unsigned int *)((BITBAND(reg,bitnum)))) + +/***************************************************************************************** + * Functions to set a bit field in Cortex-M3 + */ +static __INLINE void set_bit_reg32(volatile uint32_t * reg, uint8_t bit) +{ + HW_REG_BIT(reg,bit) = 0x1; +} +static __INLINE void set_bit_reg16(volatile uint16_t * reg, uint8_t bit) +{ + HW_REG_BIT(reg,bit) = 0x1; +} +static __INLINE void set_bit_reg8(volatile uint8_t * reg, uint8_t bit) +{ + HW_REG_BIT(reg,bit) = 0x1; +} +/***************************************************************************************** + * Functions to clear a bit field in Cortex-M3 + */ +static __INLINE void clear_bit_reg32(volatile uint32_t * reg, uint8_t bit) +{ + HW_REG_BIT(reg,bit) = 0x0; +} +static __INLINE void clear_bit_reg16(volatile uint16_t * reg, uint8_t bit) +{ + HW_REG_BIT(reg,bit) = 0x0; +} +static __INLINE void clear_bit_reg8(volatile uint8_t * reg, uint8_t bit) +{ + HW_REG_BIT(reg,bit) = 0x0; +} +/***************************************************************************************** + * Functions to read a bit field in Cortex-M3 + */ +static __INLINE uint8_t read_bit_reg32(volatile uint32_t * reg, uint8_t bit) +{ + return (HW_REG_BIT(reg,bit)); +} +static __INLINE uint8_t read_bit_reg16(volatile uint16_t * reg, uint8_t bit) +{ + return (HW_REG_BIT(reg,bit)); +} +static __INLINE uint8_t read_bit_reg8(volatile uint8_t * reg, uint8_t bit) +{ + return (HW_REG_BIT(reg,bit)); +} + +#endif /* HW_REG_IO_H_ */ diff --git a/bsp/smartfusion2/CMSIS/m2sxxx.h b/bsp/smartfusion2/CMSIS/m2sxxx.h new file mode 100644 index 0000000000..9404959bd7 --- /dev/null +++ b/bsp/smartfusion2/CMSIS/m2sxxx.h @@ -0,0 +1,2826 @@ +/******************************************************************************* + * (c) Copyright 2010-2013 Microsemi SoC Products Group. All rights reserved. + * + * Microsemi SmartFusion2 Cortex Microcontroller Software Interface - Peripheral + * Access Layer. + * + * This file describes the interrupt assignment and peripheral registers for + * the SmartFusion2 familly of devices. + * + * SVN $Revision: 6526 $ + * SVN $Date: 2014-06-05 16:07:40 +0100 (Thu, 05 Jun 2014) $ + */ +#ifndef __SMARTFUSION2_CMSIS_PAL_H__ +#define __SMARTFUSION2_CMSIS_PAL_H__ + +#ifdef __cplusplus +extern "C" { +#endif + +/* + * ========================================================================== + * ---------- Interrupt Number Definition ----------------------------------- + * ========================================================================== + */ + +typedef enum IRQn +{ +/****** Cortex-M3 Processor Exceptions Numbers *********************************************************/ + NonMaskableInt_IRQn = -14, /*!< 2 Non Maskable Interrupt - Watchdog timeout interrupt*/ + HardFault_IRQn = -13, /*!< 2 Hard Fault Interrupt */ + MemoryManagement_IRQn = -12, /*!< 4 Cortex-M3 Memory Management Interrupt */ + BusFault_IRQn = -11, /*!< 5 Cortex-M3 Bus Fault Interrupt */ + UsageFault_IRQn = -10, /*!< 6 Cortex-M3 Usage Fault Interrupt */ + SVCall_IRQn = -5, /*!< 11 Cortex-M3 SV Call Interrupt */ + DebugMonitor_IRQn = -4, /*!< 12 Cortex-M3 Debug Monitor Interrupt */ + PendSV_IRQn = -2, /*!< 14 Cortex-M3 Pend SV Interrupt */ + SysTick_IRQn = -1, /*!< 15 Cortex-M3 System Tick Interrupt */ + +/****** SmartFusion2 specific Interrupt Numbers *********************************************************/ + WdogWakeup_IRQn = 0, /*!< WatchDog wakeup interrupt */ + RTC_Wakeup_IRQn = 1, /*!< RTC wakeup interrupt */ + SPI0_IRQn = 2, /*!< SPI0 interrupt */ + SPI1_IRQn = 3, /*!< SPI1 interrupt */ + I2C0_IRQn = 4, /*!< I2C0 interrupt */ + I2C0_SMBAlert_IRQn = 5, /*!< I2C0 SMBus Alert interrupt */ + I2C0_SMBus_IRQn = 6, /*!< I2C0 SMBus Suspend interrupt */ + I2C1_IRQn = 7, /*!< I2C1 interrupt */ + I2C1_SMBAlert_IRQn = 8, /*!< I2C1 SMBus Alert interrupt */ + I2C1_SMBus_IRQn = 9, /*!< I2C1 SMBus Suspend interrupt */ + UART0_IRQn = 10, /*!< UART0 interrupt */ + UART1_IRQn = 11, /*!< UART1 interrupt */ + EthernetMAC_IRQn = 12, /*!< Ethernet MAC interrupt */ + DMA_IRQn = 13, /*!< Peripheral DMA interrupt */ + Timer1_IRQn = 14, /*!< Timer1 interrupt */ + Timer2_IRQn = 15, /*!< Timer2 interrupt */ + CAN_IRQn = 16, /*!< CAN controller interrupt */ + ENVM0_IRQn = 17, /*!< eNVM0 operation completion interrupt */ + ENVM1_IRQn = 18, /*!< eNVM1 operation completion interrupt */ + ComBlk_IRQn = 19, /*!< COM block interrupt */ + USB_IRQn = 20, /*!< USB interrupt */ + USB_DMA_IRQn = 21, /*!< USB DMA interrupt */ + PLL_Lock_IRQn = 22, /*!< PLL lock interrupt */ + PLL_LockLost_IRQn = 23, /*!< PLL loss of lock interrupt */ + CommSwitchError_IR = 24, /*!< Communications Switch error interrupt */ + CacheError_IRQn = 25, /*!< Cache error interrupt */ + DDR_IRQn = 26, /*!< DDR controller interrupt */ + HPDMA_Complete_IRQn = 27, /*!< High speed DMA transfer complete interrupt */ + HPDMA_Error_IRQn = 28, /*!< High speed DMA transfer error interrupt */ + ECC_Error_IRQn = 29, /*!< ECC error detected */ + MDDR_IOCalib_IRQn = 30, /*!< MDDR Calibration finished interrupt */ + FAB_PLL_Lock_IRQn = 31, /*!< MSSDDR Fabric PLL lock interrupt */ + FAB_PLL_LockLost_IRQn = 32, /*!< MSSDDR Fabric PLL lock lost interrupt */ + FIC64_IRQn = 33, /*!< FIC64 interrupt */ + FabricIrq0_IRQn = 34, /*!< FPGA fabric interrupt 0 */ + FabricIrq1_IRQn = 35, /*!< FPGA fabric interrupt 1 */ + FabricIrq2_IRQn = 36, /*!< FPGA fabric interrupt 2 */ + FabricIrq3_IRQn = 37, /*!< FPGA fabric interrupt 3 */ + FabricIrq4_IRQn = 38, /*!< FPGA fabric interrupt 4 */ + FabricIrq5_IRQn = 39, /*!< FPGA fabric interrupt 5 */ + FabricIrq6_IRQn = 40, /*!< FPGA fabric interrupt 6 */ + FabricIrq7_IRQn = 41, /*!< FPGA fabric interrupt 7 */ + FabricIrq8_IRQn = 42, /*!< FPGA fabric interrupt 8 */ + FabricIrq9_IRQn = 43, /*!< FPGA fabric interrupt 9 */ + FabricIrq10_IRQn = 44, /*!< FPGA fabric interrupt 10 */ + FabricIrq11_IRQn = 45, /*!< FPGA fabric interrupt 11 */ + FabricIrq12_IRQn = 46, /*!< FPGA fabric interrupt 12 */ + FabricIrq13_IRQn = 47, /*!< FPGA fabric interrupt 13 */ + FabricIrq14_IRQn = 48, /*!< FPGA fabric interrupt 14 */ + FabricIrq15_IRQn = 49, /*!< FPGA fabric interrupt 15 */ + GPIO0_IRQn = 50, /*!< GPIO 0 interrupt */ + GPIO1_IRQn = 51, /*!< GPIO 1 interrupt */ + GPIO2_IRQn = 52, /*!< GPIO 2 interrupt */ + GPIO3_IRQn = 53, /*!< GPIO 3 interrupt */ + GPIO4_IRQn = 54, /*!< GPIO 4 interrupt */ + GPIO5_IRQn = 55, /*!< GPIO 5 interrupt */ + GPIO6_IRQn = 56, /*!< GPIO 6 interrupt */ + GPIO7_IRQn = 57, /*!< GPIO 7 interrupt */ + GPIO8_IRQn = 58, /*!< GPIO 8 interrupt */ + GPIO9_IRQn = 59, /*!< GPIO 9 interrupt */ + GPIO10_IRQn = 60, /*!< GPIO 10 interrupt */ + GPIO11_IRQn = 61, /*!< GPIO 11 interrupt */ + GPIO12_IRQn = 62, /*!< GPIO 12 interrupt */ + GPIO13_IRQn = 63, /*!< GPIO 13 interrupt */ + GPIO14_IRQn = 64, /*!< GPIO 14 interrupt */ + GPIO15_IRQn = 65, /*!< GPIO 15 interrupt */ + GPIO16_IRQn = 66, /*!< GPIO 16 interrupt */ + GPIO17_IRQn = 67, /*!< GPIO 17 interrupt */ + GPIO18_IRQn = 68, /*!< GPIO 18 interrupt */ + GPIO19_IRQn = 69, /*!< GPIO 19 interrupt */ + GPIO20_IRQn = 70, /*!< GPIO 20 interrupt */ + GPIO21_IRQn = 71, /*!< GPIO 21 interrupt */ + GPIO22_IRQn = 72, /*!< GPIO 22 interrupt */ + GPIO23_IRQn = 73, /*!< GPIO 23 interrupt */ + GPIO24_IRQn = 74, /*!< GPIO 24 interrupt */ + GPIO25_IRQn = 75, /*!< GPIO 25 interrupt */ + GPIO26_IRQn = 76, /*!< GPIO 26 interrupt */ + GPIO27_IRQn = 77, /*!< GPIO 27 interrupt */ + GPIO28_IRQn = 78, /*!< GPIO 28 interrupt */ + GPIO29_IRQn = 79, /*!< GPIO 29 interrupt */ + GPIO30_IRQn = 80, /*!< GPIO 30 interrupt */ + GPIO31_IRQn = 81 /*!< GPIO 31 interrupt */ +} IRQn_Type; + +/* + * ========================================================================== + * ----------- Processor and Core Peripheral Section ------------------------ + * ========================================================================== + */ +#define __CM3_REV 0x0201 /*!< Core revision r2p1 */ +#define __MPU_PRESENT 1 /*!< MPU present or not */ +#define __NVIC_PRIO_BITS 4 /*!< Number of Bits used for Priority Levels */ +#define __Vendor_SysTickConfig 0 /*!< Set to 1 if different SysTick Config is used */ + +#include <core_cm3.h> /* Cortex-M3 processor and core peripherals */ + +/******************************************************************************/ +/* Device Specific Peripheral registers structures */ +/******************************************************************************/ +#if defined ( __CC_ARM ) + /* Enable anonymous unions when building using Keil-MDK */ + #pragma anon_unions +#endif + +/*----------------------------------------------------------------------------*/ +/*----------------------------------- UART -----------------------------------*/ +/*----------------------------------------------------------------------------*/ +typedef struct +{ + union + { + __I uint8_t RBR; + __O uint8_t THR; + __IO uint8_t DLR; + uint32_t RESERVED0; + }; + + union + { + __IO uint8_t DMR; + __IO uint8_t IER; + uint32_t RESERVED1; + }; + + union + { + __IO uint8_t IIR; + __IO uint8_t FCR; + uint32_t RESERVED2; + }; + + __IO uint8_t LCR; + uint8_t RESERVED3[3]; + + __IO uint8_t MCR; + uint8_t RESERVED4[3]; + + __I uint8_t LSR; + uint8_t RESERVED5[3]; + + __I uint8_t MSR; + uint8_t RESERVED6[3]; + + __IO uint8_t SR; + uint8_t RESERVED7[7]; + + __IO uint8_t IEM; + uint8_t RESERVED8[3]; + + __IO uint8_t IIM; + uint8_t RESERVED9[7]; + + __IO uint8_t MM0; + uint8_t RESERVED10[3]; + + __IO uint8_t MM1; + uint8_t RESERVED11[3]; + + __IO uint8_t MM2; + uint8_t RESERVED12[3]; + + __IO uint8_t DFR; + uint8_t RESERVED13[7]; + + __IO uint8_t GFR; + uint8_t RESERVED14[3]; + + __IO uint8_t TTG; + uint8_t RESERVED15[3]; + + __IO uint8_t RTO; + uint8_t RESERVED16[3]; + + __IO uint8_t ADR; + uint8_t RESERVED17[3]; + +} UART_TypeDef; + +/*----------------------------------------------------------------------------*/ +/*----------------------------------- I2C ------------------------------------*/ +/*----------------------------------------------------------------------------*/ +typedef struct +{ + __IO uint8_t CTRL; + uint8_t RESERVED0; + uint16_t RESERVED1; + uint8_t STATUS; + uint8_t RESERVED2; + uint16_t RESERVED3; + __IO uint8_t DATA; + uint8_t RESERVED4; + uint16_t RESERVED5; + __IO uint8_t ADDR; + uint8_t RESERVED6; + uint16_t RESERVED7; + __IO uint8_t SMBUS; + uint8_t RESERVED8; + uint16_t RESERVED9; + __IO uint8_t FREQ; + uint8_t RESERVED10; + uint16_t RESERVED11; + __IO uint8_t GLITCHREG; + uint8_t RESERVED12; + uint16_t RESERVED13; + __IO uint8_t SLAVE1_ADDR; + uint8_t RESERVED14; + uint16_t RESERVED15; +} I2C_TypeDef; + +/*------------------------------------------------------------------------------ + * I2C bit band + */ +typedef struct +{ + __IO uint32_t CTRL_CR0; + __IO uint32_t CTRL_CR1; + __IO uint32_t CTRL_AA; + __IO uint32_t CTRL_SI; + __IO uint32_t CTRL_STO; + __IO uint32_t CTRL_STA; + __IO uint32_t CTRL_ENS1; + __IO uint32_t CTRL_CR2; + uint32_t RESERVED0[56]; + __IO uint32_t DATA_DIR; + uint32_t RESERVED1[31]; + __IO uint32_t ADDR_GC; +} I2C_BitBand_TypeDef; + +/*----------------------------------------------------------------------------*/ +/*----------------------------------- SPI ------------------------------------*/ +/*----------------------------------------------------------------------------*/ +typedef struct +{ + __IO uint32_t CONTROL; + __IO uint32_t TXRXDF_SIZE; + __I uint32_t STATUS; + __O uint32_t INT_CLEAR; + __I uint32_t RX_DATA; + __O uint32_t TX_DATA; + __IO uint32_t CLK_GEN; + __IO uint32_t SLAVE_SELECT; + __I uint32_t MIS; + __I uint32_t RIS; + __IO uint32_t CONTROL2; + __IO uint32_t COMMAND; + __IO uint32_t PKTSIZE; + __IO uint32_t CMDSIZE; + __IO uint32_t HWSTATUS; + __IO uint32_t STAT8; + __IO uint32_t CTRL0; + __IO uint32_t CTRL1; + __IO uint32_t CTRL2; + __IO uint32_t CTRL3; +} SPI_TypeDef; + +/*----------------------------------------------------------------------------*/ +/*----------------------------------- GPIO -----------------------------------*/ +/*----------------------------------------------------------------------------*/ +typedef struct +{ + __IO uint32_t GPIO_0_CFG; + __IO uint32_t GPIO_1_CFG; + __IO uint32_t GPIO_2_CFG; + __IO uint32_t GPIO_3_CFG; + __IO uint32_t GPIO_4_CFG; + __IO uint32_t GPIO_5_CFG; + __IO uint32_t GPIO_6_CFG; + __IO uint32_t GPIO_7_CFG; + __IO uint32_t GPIO_8_CFG; + __IO uint32_t GPIO_9_CFG; + __IO uint32_t GPIO_10_CFG; + __IO uint32_t GPIO_11_CFG; + __IO uint32_t GPIO_12_CFG; + __IO uint32_t GPIO_13_CFG; + __IO uint32_t GPIO_14_CFG; + __IO uint32_t GPIO_15_CFG; + __IO uint32_t GPIO_16_CFG; + __IO uint32_t GPIO_17_CFG; + __IO uint32_t GPIO_18_CFG; + __IO uint32_t GPIO_19_CFG; + __IO uint32_t GPIO_20_CFG; + __IO uint32_t GPIO_21_CFG; + __IO uint32_t GPIO_22_CFG; + __IO uint32_t GPIO_23_CFG; + __IO uint32_t GPIO_24_CFG; + __IO uint32_t GPIO_25_CFG; + __IO uint32_t GPIO_26_CFG; + __IO uint32_t GPIO_27_CFG; + __IO uint32_t GPIO_28_CFG; + __IO uint32_t GPIO_29_CFG; + __IO uint32_t GPIO_30_CFG; + __IO uint32_t GPIO_31_CFG; + __IO uint32_t GPIO_IRQ; + __I uint32_t GPIO_IN; + __IO uint32_t GPIO_OUT; +} GPIO_TypeDef; + +/*------------------------------------------------------------------------------ + * GPIO bit band + */ +typedef struct +{ + __IO uint32_t GPIO_0_CFG[32]; + __IO uint32_t GPIO_1_CFG[32]; + __IO uint32_t GPIO_2_CFG[32]; + __IO uint32_t GPIO_3_CFG[32]; + __IO uint32_t GPIO_4_CFG[32]; + __IO uint32_t GPIO_5_CFG[32]; + __IO uint32_t GPIO_6_CFG[32]; + __IO uint32_t GPIO_7_CFG[32]; + __IO uint32_t GPIO_8_CFG[32]; + __IO uint32_t GPIO_9_CFG[32]; + __IO uint32_t GPIO_10_CFG[32]; + __IO uint32_t GPIO_11_CFG[32]; + __IO uint32_t GPIO_12_CFG[32]; + __IO uint32_t GPIO_13_CFG[32]; + __IO uint32_t GPIO_14_CFG[32]; + __IO uint32_t GPIO_15_CFG[32]; + __IO uint32_t GPIO_16_CFG[32]; + __IO uint32_t GPIO_17_CFG[32]; + __IO uint32_t GPIO_18_CFG[32]; + __IO uint32_t GPIO_19_CFG[32]; + __IO uint32_t GPIO_20_CFG[32]; + __IO uint32_t GPIO_21_CFG[32]; + __IO uint32_t GPIO_22_CFG[32]; + __IO uint32_t GPIO_23_CFG[32]; + __IO uint32_t GPIO_24_CFG[32]; + __IO uint32_t GPIO_25_CFG[32]; + __IO uint32_t GPIO_26_CFG[32]; + __IO uint32_t GPIO_27_CFG[32]; + __IO uint32_t GPIO_28_CFG[32]; + __IO uint32_t GPIO_29_CFG[32]; + __IO uint32_t GPIO_30_CFG[32]; + __IO uint32_t GPIO_31_CFG[32]; + __IO uint32_t GPIO_IRQ[32]; + __I uint32_t GPIO_IN[32]; + __IO uint32_t GPIO_OUT[32]; +} GPIO_BitBand_TypeDef; + + +/*----------------------------------------------------------------------------*/ +/*--------------------------------- HPDMA ------------------------------------*/ +/*----------------------------------------------------------------------------*/ + +typedef struct +{ + __IO uint32_t HPDMASAR_REG ; + __IO uint32_t HPDMADAR_REG ; + __IO uint32_t HPDMACR_REG ; + __I uint32_t HPDMASR_REG ; + __I uint32_t HPDMAPTR_REG ; +}HPDMA_Descriptor_TypeDef; + +typedef struct +{ + __I uint32_t HPDMAEDR_REG ; + HPDMA_Descriptor_TypeDef Descriptor[4] ; + __O uint32_t HPDMAICR_REG ; + __I uint32_t HPDMADR_REG ; +} HPDMA_TypeDef; + +typedef struct +{ + uint32_t RESERVED0[64]; + __IO uint32_t HPDMACR_XFR_SIZE[16] ; + __IO uint32_t HPDMACR_DCP_VALID ; + __IO uint32_t HPDMACR_DCP_XFR_DIR ; + __IO uint32_t HPDMACR_DCP_CLR ; + __IO uint32_t HPDMACR_DCP_PAUSE ; + __IO uint32_t HPDMACR_XFR_CMP_INT ; + __IO uint32_t HPDMACR_XFR_ERR_INT ; + __IO uint32_t HPDMACR_NON_WORD_INT ; + uint32_t RESERVED1[9]; + + __I uint32_t HPDMASR_DCP_ACTIVE ; + __I uint32_t HPDMASR_DCP_CMPLET ; + __I uint32_t HPDMASR_DCP_SERR ; + __I uint32_t HPDMASR_DCP_DERR ; + uint32_t RESERVED2[60] ; +}HPDMA_Descriptor_BitBand_TypeDef; + +/*------------------------------------------------------------------------------ + * HPDMA bit band + */ +typedef struct +{ + __I uint32_t HPDMAEDR_DCP_EMPTY[4] ; + __I uint32_t HPDMAEDR_DCP_CMPLET[4] ; + __I uint32_t HPDMAEDR_DCP_ERR[4] ; + __I uint32_t HPDMAEDR_DCP_NON_WORD_ERR[4] ; + uint32_t RESERVED0[16] ; + + HPDMA_Descriptor_BitBand_TypeDef Descriptor[4]; + + __O uint32_t HPDMAICR_CLR_XFR_INT[4] ; + __O uint32_t HPDMAICR_NON_WORD_INT[4] ; + uint32_t RESERVED1[16] ; + + __I uint32_t HPDMADR_BFR_EMPTY ; + __I uint32_t HPDMADR_BFR_FULL ; + __I uint32_t HPDMADR_BFR_RD_PNTR[3] ; + __I uint32_t HPDMADR_BFR_WR_PNTR [3] ; + __I uint32_t HPDMADR_AHM1_CST_DBG[4] ; + __I uint32_t HPDMADR_AHM2_CST_DBG[4] ; + __I uint32_t HPDMADR_WBC_CST_DBG[3] ; + __I uint32_t HPDMADR_RBC_CST_DBG[3] ; + __I uint32_t HPDMADR_RRBN_CST_DBG[4] ; + __I uint32_t HPDMADR_DMA_CST_DBG[4] ; + + uint32_t RESERVED2[4] ; +}HPDMA_BitBand_TypeDef; + +/*----------------------------------------------------------------------------*/ +/*----------------------------------- RTC ------------------------------------*/ +/*----------------------------------------------------------------------------*/ +typedef struct +{ + __IO uint32_t CONTROL_REG ; + __IO uint32_t MODE_REG ; + __IO uint32_t PRESCALER_REG ; + __IO uint32_t ALARM_LOWER_REG ; + __IO uint32_t ALARM_UPPER_REG ; + __IO uint32_t COMPARE_LOWER_REG ; + __IO uint32_t COMPARE_UPPER_REG ; + uint32_t RESERVED0 ; + __IO uint32_t DATE_TIME_LOWER_REG ; + __IO uint32_t DATE_TIME_UPPER_REG ; + + uint32_t RESERVED1[2] ; + __IO uint32_t SECONDS_REG ; + __IO uint32_t MINUTES_REG ; + __IO uint32_t HOURS_REG ; + __IO uint32_t DAY_REG ; + __IO uint32_t MONTH_REG ; + __IO uint32_t YEAR_REG ; + __IO uint32_t WEEKDAY_REG ; + __IO uint32_t WEEK_REG ; + + __IO uint32_t SECONDS_CNT_REG ; + __IO uint32_t MINUTES_CNT_REG ; + __IO uint32_t HOURS_CNT_REG ; + __IO uint32_t DAY_CNT_REG ; + __IO uint32_t MONTH_CNT_REG ; + __IO uint32_t YEAR_CNT_REG ; + __IO uint32_t WEEKDAY_CNT_REG ; + __IO uint32_t WEEK_CNT_REG ; +} RTC_TypeDef; + +/*----------------------------------------------------------------------------*/ +/*---------------------------------- Timer -----------------------------------*/ +/*----------------------------------------------------------------------------*/ +typedef struct +{ + __I uint32_t TIM1_VAL; + __IO uint32_t TIM1_LOADVAL; + __IO uint32_t TIM1_BGLOADVAL; + __IO uint32_t TIM1_CTRL; + __IO uint32_t TIM1_RIS; + __I uint32_t TIM1_MIS; + + __I uint32_t TIM2_VAL; + __IO uint32_t TIM2_LOADVAL; + __IO uint32_t TIM2_BGLOADVAL; + __IO uint32_t TIM2_CTRL; + __IO uint32_t TIM2_RIS; + __I uint32_t TIM2_MIS; + + __I uint32_t TIM64_VAL_U; + __I uint32_t TIM64_VAL_L; + __IO uint32_t TIM64_LOADVAL_U; + __IO uint32_t TIM64_LOADVAL_L; + __IO uint32_t TIM64_BGLOADVAL_U; + __IO uint32_t TIM64_BGLOADVAL_L; + __IO uint32_t TIM64_CTRL; + __IO uint32_t TIM64_RIS; + __I uint32_t TIM64_MIS; + __IO uint32_t TIM64_MODE; +} TIMER_TypeDef; + +/*------------------------------------------------------------------------------ + * Timer bit band + */ +typedef struct +{ + __I uint32_t TIM1_VALUE_BIT[32]; + __IO uint32_t TIM1_LOADVAL[32]; + __IO uint32_t TIM1_BGLOADVAL[32]; + + __IO uint32_t TIM1ENABLE; + __IO uint32_t TIM1MODE; + __IO uint32_t TIM1INTEN; + __IO uint32_t TIM1_CTRL_RESERVED[29]; + __IO uint32_t TIM1_RIS[32]; + __I uint32_t TIM1_MIS[32]; + + __I uint32_t TIM2_VALUE[32]; + __IO uint32_t TIM2_LOADVAL[32]; + __IO uint32_t TIM2_BGLOADVAL[32]; + + __IO uint32_t TIM2ENABLE; + __IO uint32_t TIM2MODE; + __IO uint32_t TIM2INTEN; + __IO uint32_t TIM2_CTRL[29]; + __IO uint32_t TIM2_RIS[32]; + __I uint32_t TIM2_MIS[32]; + + __I uint32_t TIM64VALUEU[32]; + __I uint32_t TIM64VALUEL[32]; + __IO uint32_t TIM64LOADVALUEU[32]; + __IO uint32_t TIM64LOADVALUEL[32]; + __IO uint32_t TIM64BGLOADVALUEU[32]; + __IO uint32_t TIM64BGLOADVALUEL[32]; + __IO uint32_t TIM64ENABLE; + __IO uint32_t TIM64MODE; + __IO uint32_t TIM64INTEN; + __IO uint32_t TIM64_CTRL[29]; + __IO uint32_t TIM64_RIS[32]; + __I uint32_t TIM64_MIS[32]; + __IO uint32_t TIM64_MODE[32]; +} TIMER_BitBand_TypeDef; + +/*----------------------------------------------------------------------------*/ +/*--------------------------------- Watchdog ---------------------------------*/ +/*----------------------------------------------------------------------------*/ +typedef struct +{ + __I uint32_t WDOGVALUE; + __I uint32_t WDOGLOAD; + __I uint32_t WDOGMVRP; + __O uint32_t WDOGREFRESH; + __I uint32_t WDOGENABLE; + __IO uint32_t WDOGCONTROL; + __I uint32_t WDOGSTATUS; + __IO uint32_t WDOGRIS; + __I uint32_t WDOGMIS; +} WATCHDOG_TypeDef; + +/*----------------------------------------------------------------------------*/ +/*----------------------------- Real Time Clock ------------------------------*/ +/*----------------------------------------------------------------------------*/ + +/*----------------------------------------------------------------------------*/ +/*----------------------------- Peripherals DMA ------------------------------*/ +/*----------------------------------------------------------------------------*/ +typedef struct +{ + __IO uint32_t CRTL; + __IO uint32_t STATUS; + __IO uint32_t BUFFER_A_SRC_ADDR; + __IO uint32_t BUFFER_A_DEST_ADDR; + __IO uint32_t BUFFER_A_TRANSFER_COUNT; + __IO uint32_t BUFFER_B_SRC_ADDR; + __IO uint32_t BUFFER_B_DEST_ADDR; + __IO uint32_t BUFFER_B_TRANSFER_COUNT; +} PDMA_Channel_TypeDef; + +typedef struct +{ + __IO uint32_t RATIO_HIGH_LOW; + __IO uint32_t BUFFER_STATUS; + uint32_t RESERVED[6]; + PDMA_Channel_TypeDef CHANNEL[8]; +} PDMA_TypeDef; + +/*----------------------------------------------------------------------------*/ +/*------------------------------ Ethernet MAC --------------------------------*/ +/*----------------------------------------------------------------------------*/ +typedef struct +{ + /* + * MAC registers (MCXMAC) + */ + __IO uint32_t CFG1; + __IO uint32_t CFG2; + __IO uint32_t IFG; + __IO uint32_t HALF_DUPLEX; + __IO uint32_t MAX_FRAME_LENGTH; + uint32_t RESERVED0[2]; + __IO uint32_t TEST; + __IO uint32_t MII_CONFIG; + __IO uint32_t MII_COMMAND; + __IO uint32_t MII_ADDRESS; + __O uint32_t MII_CTRL; + __I uint32_t MII_STATUS; + __I uint32_t MII_INDICATORS; + __IO uint32_t INTERFACE_CTRL; + __I uint32_t INTERFACE_STATUS; + __IO uint32_t STATION_ADDRESS1; + __IO uint32_t STATION_ADDRESS2; + /* + * FIFO Configuration / Access registers (MCXFIF) + */ + __IO uint32_t FIFO_CFG0; + __IO uint32_t FIFO_CFG1; + __IO uint32_t FIFO_CFG2; + __IO uint32_t FIFO_CFG3; + __IO uint32_t FIFO_CFG4; + __IO uint32_t FIFO_CFG5; + __IO uint32_t FIFO_RAM_ACCESS0; + __IO uint32_t FIFO_RAM_ACCESS1; + __IO uint32_t FIFO_RAM_ACCESS2; + __I uint32_t FIFO_RAM_ACCESS3; + __IO uint32_t FIFO_RAM_ACCESS4; + __IO uint32_t FIFO_RAM_ACCESS5; + __IO uint32_t FIFO_RAM_ACCESS6; + __I uint32_t FIFO_RAM_ACCESS7; + /* + * Statistics registers (MSTAT) + */ + __IO uint32_t TR64; + __IO uint32_t TR127; + __IO uint32_t TR255; + __IO uint32_t TR511; + __IO uint32_t TR1K; + __IO uint32_t TRMAX; + __IO uint32_t TRMGV; + __IO uint32_t RBYT; + __IO uint32_t PPKT; + __IO uint32_t RFCS; + __IO uint32_t RMCA; + __IO uint32_t RBCA; + __IO uint32_t RXCF; + __IO uint32_t RXPF; + __IO uint32_t RXUO; + __IO uint32_t RALN; + __IO uint32_t RFLR; + __IO uint32_t RCDE; + __IO uint32_t RCSE; + __IO uint32_t RUND; + __IO uint32_t ROVR; + __IO uint32_t RFRG; + __IO uint32_t RJBR; + __IO uint32_t RDRP; + __IO uint32_t TBYT; + __IO uint32_t TPKT; + __IO uint32_t TMCA; + __IO uint32_t TBCA; + __IO uint32_t TXPF; + __IO uint32_t TDFR; + __IO uint32_t TEDF; + __IO uint32_t TSCL; + __IO uint32_t TMCL; + __IO uint32_t TLCL; + __IO uint32_t TXCL; + __IO uint32_t TNCL; + __IO uint32_t TPFH; + __IO uint32_t TDRP; + __IO uint32_t TJBR; + __IO uint32_t TFCS; + __IO uint32_t TXCF; + __IO uint32_t TOVR; + __IO uint32_t TUND; + __IO uint32_t TFRG; + __I uint32_t CAR1; + __I uint32_t CAR2; + __IO uint32_t CAM1; + __IO uint32_t CAM2; + uint32_t RESERVED1[16]; + /* + * DMA registers (MAHBE) + */ + __IO uint32_t DMA_TX_CTRL; + __IO uint32_t DMA_TX_DESC; + __IO uint32_t DMA_TX_STATUS; + __IO uint32_t DMA_RX_CTRL; + __IO uint32_t DMA_RX_DESC; + __IO uint32_t DMA_RX_STATUS; + __IO uint32_t DMA_IRQ_MASK; + __I uint32_t DMA_IRQ; +} MAC_TypeDef; + +/*----------------------------------------------------------------------------*/ +/*------------------------------ USB --------------------------------*/ +/*----------------------------------------------------------------------------*/ +typedef struct +{ + __IO uint16_t TX_MAX_P; + __IO uint16_t TX_CSR; + __IO uint16_t RX_MAX_P; + __IO uint16_t RX_CSR; + __IO uint16_t RX_COUNT; + __IO uint8_t TX_TYPE; + __IO uint8_t TX_INTERVAL; + __IO uint8_t RX_TYPE; + __IO uint8_t RX_INTERVAL; + __IO uint8_t RESERVED; + __IO uint8_t FIFO_SIZE; +} USB_endpoint_regs_t; + +typedef struct +{ + __IO uint8_t TX_FUNC_ADDR; + __IO uint8_t UNUSED0; + __IO uint8_t TX_HUB_ADDR; + __IO uint8_t TX_HUB_PORT; + __IO uint8_t RX_FUNC_ADDR; + __IO uint8_t UNUSED1; + __IO uint8_t RX_HUB_ADDR; + __IO uint8_t RX_HUB_PORT; +} USB_tar_t; + +typedef union +{ + struct + { + __IO uint32_t VALUE; + } WORD; + + struct + { + __IO uint8_t VALUE; + __IO uint8_t RESERVED1; + __IO uint8_t RESERVED2; + __IO uint8_t RESERVED3; + } BYTE; + + struct + { + __IO uint16_t VALUE; + __IO uint16_t RESERVED; + } HALFWORD; +} USB_fifo_t; + +typedef union +{ + struct + { + __IO uint16_t TX_MAX_P; + __IO uint16_t CSR0; + __IO uint16_t RX_MAX_P; + __IO uint16_t RX_CSR; + __IO uint16_t COUNT0; + __IO uint8_t RESERVED0; + __IO uint8_t RESERVED1; + __IO uint8_t RESERVED2; + __IO uint8_t RESERVED3; + __IO uint8_t RESERVED4; + __IO uint8_t CONFIG_DATA; + } DEVICE_EP0; + + struct + { + __IO uint16_t TX_MAX_P; + __IO uint16_t TX_CSR; + __IO uint16_t RX_MAX_P; + __IO uint16_t RX_CSR; + __IO uint16_t RX_COUNT; + __IO uint8_t RESERVED0; + __IO uint8_t RESERVED1; + __IO uint8_t RESERVED2; + __IO uint8_t RESERVED3; + __IO uint8_t RESERVED4; + __IO uint8_t FIFO_SIZE; + } DEVICE_EPN; + + struct + { + __IO uint16_t TX_MAX_P; + __IO uint16_t CSR0; + __IO uint16_t RX_MAX_P; + __IO uint16_t RX_CSR; + __IO uint16_t COUNT0; + __IO uint8_t TYPE0; + __IO uint8_t NAK_LIMIT0; + __IO uint8_t RX_TYPE; + __IO uint8_t RX_INTERVAL; + __IO uint8_t RESERVED0; + __IO uint8_t CONFIG_DATA; + } HOST_EP0; + + struct + { + __IO uint16_t TX_MAX_P; + __IO uint16_t TX_CSR; + __IO uint16_t RX_MAX_P; + __IO uint16_t RX_CSR; + __IO uint16_t RX_COUNT; + __IO uint8_t TX_TYPE; + __IO uint8_t TX_INTERVAL; + __IO uint8_t RX_TYPE; + __IO uint8_t RX_INTERVAL; + __IO uint8_t RESERVED0; + __IO uint8_t FIFO_SIZE; + } HOST_EPN; + +} USB_indexed_csr_t; + +typedef struct { + __IO uint32_t IRQ; + __IO uint32_t CNTL; + __IO uint32_t ADDR; + __IO uint32_t COUNT; +} USB_DMA_channel; + +typedef struct +{ + /* + * Common USB Registers + */ + __IO uint8_t FADDR; + __IO uint8_t POWER; + __IO uint16_t TX_IRQ; + __IO uint16_t RX_IRQ; + __IO uint16_t TX_IRQ_ENABLE; + __IO uint16_t RX_IRQ_ENABLE; + __IO uint8_t USB_IRQ; + __IO uint8_t USB_ENABLE; + __IO uint16_t FRAME; + __IO uint8_t INDEX; + __IO uint8_t TEST_MODE; + + /* + * Indexed CSR + */ + USB_indexed_csr_t INDEXED_CSR; + + /* + * Endpoint FIFOs + */ + USB_fifo_t FIFO[16]; + + /* + * OTG, dynamic FIFO and version + */ + __IO uint8_t DEV_CTRL; + __IO uint8_t MISC; + __IO uint8_t TX_FIFO_SIZE; + __IO uint8_t RX_FIFO_SIZE; + __IO uint16_t TX_FIFO_ADDR; + __IO uint16_t RX_FIFO_ADDR; + __IO uint32_t VBUS_CSR; + __IO uint16_t HW_VERSION; + __IO uint16_t RESERVED; + + /* + * ULPI and configuration registers + */ + __IO uint8_t ULPI_VBUS_CTRL; + __IO uint8_t ULPI_CARKIT_CTRL; + __IO uint8_t ULPI_IRQ_MASK; + __IO uint8_t ULPI_IRQ_SRC; + __IO uint8_t ULPI_DATA_REG; + __IO uint8_t ULPI_ADDR_REG; + __IO uint8_t ULPI_CTRL_REG; + __IO uint8_t ULPI_RAW_DATA; + __IO uint8_t EP_INFO; + __IO uint8_t RAM_INFO; + __IO uint8_t LINK_INFO; + __IO uint8_t VP_LEN; + __IO uint8_t HS_EOF1; + __IO uint8_t FS_EOF1; + __IO uint8_t LS_EOF1; + __IO uint8_t SOFT_RST; + + /* + * Target Address registers + */ + USB_tar_t TAR[16]; + + /* + * Endpoints CSR + */ + USB_endpoint_regs_t ENDPOINT[16]; + + /* + * DMA + */ + USB_DMA_channel DMA_CHANNEL[8]; + + __IO uint32_t RESERVED_EXT[32]; + __IO uint32_t RQ_PKT_CNT[16]; + __IO uint16_t RX_DPBUF_DIS; + __IO uint16_t TX_DPBUF_DIS; + __IO uint16_t C_T_UCH; + __IO uint16_t C_T_HHSRTN; + __IO uint16_t C_T_HSBT; + +} MSS_USB_TypeDef; + +/*----------------------------------------------------------------------------*/ +/*---------------------- eNVM Special Function Registers ---------------------*/ +/*----------------------------------------------------------------------------*/ +typedef struct +{ + __I uint8_t AB[128]; + __IO uint8_t WD[128]; + __I uint8_t RESERVED0[32]; + __I uint32_t STATUS; + __IO uint32_t RESERVED1; + __IO uint32_t NV_PAGE_STATUS; + __I uint32_t NV_FREQRNG; + __I uint32_t NV_DPD; + __IO uint32_t NV_CE; + uint32_t RESERVED2; + __IO uint32_t RESERVED3; + __IO uint32_t PAGE_LOCK; + __IO uint32_t DWSIZE; + __IO uint32_t CMD; + __IO uint32_t RESERVED4; + __I uint32_t RESERVED5; + __IO uint32_t INTEN; + __IO uint32_t CLRHINT; + uint32_t RESERVED6[40]; + __IO uint32_t REQ_ACCESS; +} NVM_TypeDef; + +typedef struct +{ + __I uint32_t AB[32]; + __IO uint32_t WD[32]; + __I uint32_t RESERVED0[8]; + __I uint32_t STATUS; + __IO uint32_t RESERVED1; + __IO uint32_t NV_PAGE_STATUS; + __I uint32_t NV_FREQRNG; + __I uint32_t NV_DPD; + __IO uint32_t NV_CE; + uint32_t RESERVED2; + __IO uint32_t RESERVED3; + __IO uint32_t PAGE_LOCK; + __IO uint32_t DWSIZE; + __IO uint32_t CMD; + __IO uint32_t RESERVED4; + __I uint32_t RESERVED5; + __IO uint32_t INTEN; + __IO uint32_t CLRHINT; + uint32_t RESERVED6[40]; + __IO uint32_t REQ_ACCESS; +} NVM32_TypeDef; + +/*----------------------------------------------------------------------------*/ +/*---------------------------------- COMBLK ----------------------------------*/ +/*----------------------------------------------------------------------------*/ +typedef struct +{ + __IO uint32_t CONTROL; + __IO uint32_t STATUS; + __IO uint32_t INT_ENABLE; + __IO uint32_t RESERVED; + __IO uint32_t DATA8; + __IO uint32_t DATA32; + __IO uint32_t FRAME_START8; + __IO uint32_t FRAME_START32; +} COMBLK_TypeDef; + +/*----------------------------------------------------------------------------*/ +/*--------------------- FPGA Fabric Interrupt Controller ---------------------*/ +/*----------------------------------------------------------------------------*/ +/* + * Please refer to the SmartFusion2 Interrupt Controller User's Guide for a + * description of the following registers. + * The registers defined below can be accessed using INTERRUPT_CTRL as follows: + * uint32_t reason0; + * INTERRUPT_CTRL->INTERRUPT_MODE = 0; + * reason0 = INTERRUPT_CTRL->INTERRUPT_REASON0; + */ +typedef struct +{ + __IO uint32_t INTERRUPT_ENABLE0; + __IO uint32_t INTERRUPT_ENABLE1; + __IO uint32_t INTERRUPT_REASON0; + __IO uint32_t INTERRUPT_REASON1; + __IO uint32_t INTERRUPT_MODE; +} INTERRUPT_CTRL_TypeDef; + +/* + * Please refer to the SmartFusion2 Interrupt Controller User's Guide for a + * description of the following register bits. + * The register bits defined below can be accessed using INTERRUPT_CTRL_BITBAND + * as follows: + * setting/clearing a bit: + * INTERRUPT_CTRL_BITBAND->MAC_INT_ENBL = 1; + * INTERRUPT_CTRL_BITBAND->PDMAINTERRUPT_ENBL = 0; + * reading a bit value: + * uint32_t timer1_interrupt; + * timer1_interrupt = INTERRUPT_CTRL_BITBAND->TIMER1_INTR_STATUS; + */ +typedef struct +{ + /* + * INTERRUPT_ENABLE0 register bitband definitions. + */ + __IO uint32_t SPIINT0_ENBL; + __IO uint32_t SPIINT1_ENBL; + __IO uint32_t I2C_INT0_ENBL; + __IO uint32_t I2C_INT1_ENBL; + __IO uint32_t MMUART0_INTR_ENBL; + __IO uint32_t MMUART1_INTR_ENBL; + __IO uint32_t MAC_INT_ENBL; + __IO uint32_t USB_MC_INT_ENBL; + __IO uint32_t PDMAINTERRUPT_ENBL; + __IO uint32_t HPD_XFR_CMP_INT_ENBL; + __IO uint32_t TIMER1_INTR_ENBL; + __IO uint32_t TIMER2_INTR_ENBL; + __IO uint32_t CAN_INTR_ENBL; + __IO uint32_t RTC_WAKEUP_INTR_ENBL; + __IO uint32_t WDOGWAKEUPINT_ENBL; + __IO uint32_t MSSDDR_PLL_LOCKLOST_INT_ENBL; + __IO uint32_t ENVM_INT0_ENBL; + __IO uint32_t ENVM_INT1_ENBL; + __IO uint32_t I2C_SMBALERT0_ENBL; + __IO uint32_t I2C_SMBSUS0_ENBL; + __IO uint32_t I2C_SMBALERT1_ENBL; + __IO uint32_t I2C_SMBSUS1_ENBL; + __IO uint32_t HPD_XFR_ERR_INT_ENBL; + __IO uint32_t MSSDDR_PLL_LOCK_INT_ENBL; + __IO uint32_t SW_ERRORINTERRUPT_ENBL; + __IO uint32_t DDRB_INTR_ENBL; + __IO uint32_t ECCINTR_ENBL; + __IO uint32_t CACHE_ERRINTR_ENBL; + __IO uint32_t SOFTINTERRUPT_ENBL; + __IO uint32_t COMBLK_INTR_ENBL; + __IO uint32_t USB_DMA_INT_ENBL; + __IO uint32_t RESERVED0; + + /* + * INTERRUPT_ENABLE1 register bitband definitions. + */ + __IO uint32_t RESERVED1[3]; + __IO uint32_t MDDR_IO_CALIB_INT_ENBL; + __IO uint32_t RESERVED2; + __IO uint32_t FAB_PLL_LOCK_INT_ENBL; + __IO uint32_t FAB_PLL_LOCKLOST_INT_ENBL; + __IO uint32_t FIC64_INT_ENBL; + __IO uint32_t RESERVED3[24]; + + /* + * INTERRUPT_REASON0 register bitband definitions. + */ + __IO uint32_t SPIINT0_STATUS; + __IO uint32_t SPIINT1_STATUS; + __IO uint32_t I2C_INT0_STATUS; + __IO uint32_t I2C_INT1_STATUS; + __IO uint32_t MMUART0_INTR_STATUS; + __IO uint32_t MMUART1_INTR_STATUS; + __IO uint32_t MAC_INT_STATUS; + __IO uint32_t USB_MC_INT_STATUS; + __IO uint32_t PDMAINTERRUPT_STATUS; + __IO uint32_t HPD_XFR_CMP_INT_STATUS; + __IO uint32_t TIMER1_INTR_STATUS; + __IO uint32_t TIMER2_INTR_STATUS; + __IO uint32_t CAN_INTR_STATUS; + __IO uint32_t RTC_WAKEUP_INTR_STATUS; + __IO uint32_t WDOGWAKEUPINT_STATUS; + __IO uint32_t MSSDDR_PLL_LOCKLOST_INT_STATUS; + __IO uint32_t ENVM_INT0_STATUS; + __IO uint32_t ENVM_INT1_STATUS; + __IO uint32_t I2C_SMBALERT0_STATUS; + __IO uint32_t I2C_SMBSUS0_STATUS; + __IO uint32_t I2C_SMBALERT1_STATUS; + __IO uint32_t I2C_SMBSUS1_STATUS; + __IO uint32_t HPD_XFR_ERR_INT_STATUS; + __IO uint32_t MSSDDR_PLL_LOCK_INT_STATUS; + __IO uint32_t SW_ERRORINTERRUPT_STATUS; + __IO uint32_t DDRB_INTR_STATUS; + __IO uint32_t ECCINTR_STATUS; + __IO uint32_t CACHE_ERRINTR_STATUS; + __IO uint32_t SOFTINTERRUPT_STATUS; + __IO uint32_t COMBLK_INTR_STATUS; + __IO uint32_t USB_DMA_INT_STATUS; + __IO uint32_t RESERVED4; + + /* + * INTERRUPT_REASON1 register bitband definitions. + */ + __IO uint32_t RESERVED5[3]; + __IO uint32_t MDDR_IO_CALIB_INT_STATUS; + __IO uint32_t RESERVED6; + __IO uint32_t FAB_PLL_LOCK_INT_STATUS; + __IO uint32_t FAB_PLL_LOCKLOST_INT_STATUS; + __IO uint32_t FIC64_INT_STATUS; + __IO uint32_t RESERVED7[24]; + + /* + * INTERRUPT_MODE register bitband definitions. + */ + __IO uint32_t SELECT_MODE; + __IO uint32_t RESERVED8[31]; + +} INTERRUPT_CTRL_BitBand_TypeDef; + +/*----------------------------------------------------------------------------*/ +/*------------------------ DDR Controller APB Registers ----------------------*/ +/*----------------------------------------------------------------------------*/ +typedef struct +{ + /*-------------------------------------------------------------------------- + * DDR Controller registers. + * All registers are 16-bit wide unless mentioned beside the definition. + */ + struct + { + __IO uint32_t DYN_SOFT_RESET_CR; + __IO uint32_t RESERVED0; + __IO uint32_t DYN_REFRESH_1_CR; + __IO uint32_t DYN_REFRESH_2_CR; + __IO uint32_t DYN_POWERDOWN_CR; + __IO uint32_t DYN_DEBUG_CR; + __IO uint32_t MODE_CR; + __IO uint32_t ADDR_MAP_BANK_CR; + __IO uint32_t ECC_DATA_MASK_CR; + __IO uint32_t ADDR_MAP_COL_1_CR; + __IO uint32_t ADDR_MAP_COL_2_CR; + __IO uint32_t ADDR_MAP_ROW_1_CR; + __IO uint32_t ADDR_MAP_ROW_2_CR; + __IO uint32_t INIT_1_CR; + __IO uint32_t CKE_RSTN_CYCLES_CR[2]; /* 0:27 bits are valid */ + __IO uint32_t INIT_MR_CR; + __IO uint32_t INIT_EMR_CR; + __IO uint32_t INIT_EMR2_CR; + __IO uint32_t INIT_EMR3_CR; + __IO uint32_t DRAM_BANK_TIMING_PARAM_CR; + __IO uint32_t DRAM_RD_WR_LATENCY_CR; + __IO uint32_t DRAM_RD_WR_PRE_CR; + __IO uint32_t DRAM_MR_TIMING_PARAM_CR; + __IO uint32_t DRAM_RAS_TIMING_CR; + __IO uint32_t DRAM_RD_WR_TRNARND_TIME_CR; + __IO uint32_t DRAM_T_PD_CR; + __IO uint32_t DRAM_BANK_ACT_TIMING_CR; + __IO uint32_t ODT_PARAM_1_CR; + __IO uint32_t ODT_PARAM_2_CR; + __IO uint32_t ADDR_MAP_COL_3_CR; + __IO uint32_t MODE_REG_RD_WR_CR; + __IO uint32_t MODE_REG_DATA_CR; + __IO uint32_t PWR_SAVE_1_CR; + __IO uint32_t PWR_SAVE_2_CR; + __IO uint32_t ZQ_LONG_TIME_CR; + __IO uint32_t ZQ_SHORT_TIME_CR; + __IO uint32_t ZQ_SHORT_INT_REFRESH_MARGIN_CR[2]; + __IO uint32_t PERF_PARAM_1_CR; + __IO uint32_t HPR_QUEUE_PARAM_CR[2]; + __IO uint32_t LPR_QUEUE_PARAM_CR[2]; + __IO uint32_t WR_QUEUE_PARAM_CR; + __IO uint32_t PERF_PARAM_2_CR; + __IO uint32_t PERF_PARAM_3_CR; + __IO uint32_t DFI_RDDATA_EN_CR; + __IO uint32_t DFI_MIN_CTRLUPD_TIMING_CR; + __IO uint32_t DFI_MAX_CTRLUPD_TIMING_CR; + __IO uint32_t DFI_WR_LVL_CONTROL_CR[2]; + __IO uint32_t DFI_RD_LVL_CONTROL_CR[2]; + __IO uint32_t DFI_CTRLUPD_TIME_INTERVAL_CR; + __IO uint32_t DYN_SOFT_RESET_CR2; + __IO uint32_t AXI_FABRIC_PRI_ID_CR; + __I uint32_t DDRC_SR; + __I uint32_t SINGLE_ERR_CNT_SR; + __I uint32_t DOUBLE_ERR_CNT_SR; + __I uint32_t LUE_SYNDROME_SR[5]; /* LUE : Last Uncorrected Error */ + __I uint32_t LUE_ADDRESS_SR[2]; + __I uint32_t LCE_SYNDROME_SR[5]; /* LCE : Last Corrected Error */ + __I uint32_t LCE_ADDRESS_SR[2]; + __I uint32_t LCB_NUMBER_SR; /* LCB : Last Corrected Bit */ + __I uint32_t LCB_MASK_SR[4]; + __I uint32_t ECC_INT_SR; + __O uint32_t ECC_INT_CLR_REG; + __I uint32_t ECC_OUTPUT_DATA_SR; + __IO uint32_t RESERVED1[46]; + } ddrc; + + /*-------------------------------------------------------------------------- + * DDR PHY configuration registers + */ + struct + { + __IO uint32_t DYN_BIST_TEST_CR; + __IO uint32_t DYN_BIST_TEST_ERRCLR_CR[3]; + __IO uint32_t BIST_TEST_SHIFT_PATTERN_CR[3]; + __IO uint32_t LOOPBACK_TEST_CR; + __IO uint32_t BOARD_LOOPBACK_CR; + __IO uint32_t CTRL_SLAVE_RATIO_CR; + __IO uint32_t CTRL_SLAVE_FORCE_CR; + __IO uint32_t CTRL_SLAVE_DELAY_CR; + __IO uint32_t DATA_SLICE_IN_USE_CR; + __IO uint32_t LVL_NUM_OF_DQ0_CR; + __IO uint32_t DQ_OFFSET_CR[3]; + __IO uint32_t DIS_CALIB_RST_CR; + __IO uint32_t DLL_LOCK_DIFF_CR; + __IO uint32_t FIFO_WE_IN_DELAY_CR[3]; + __IO uint32_t FIFO_WE_IN_FORCE_CR; + __IO uint32_t FIFO_WE_SLAVE_RATIO_CR[4]; + __IO uint32_t GATELVL_INIT_MODE_CR; + __IO uint32_t GATELVL_INIT_RATIO_CR[4]; + __IO uint32_t LOCAL_ODT_CR; + __IO uint32_t INVERT_CLKOUT_CR; + __IO uint32_t RD_DQS_SLAVE_DELAY_CR[3]; + __IO uint32_t RD_DQS_SLAVE_FORCE_CR; + __IO uint32_t RD_DQS_SLAVE_RATIO_CR[4]; + __IO uint32_t WR_DQS_SLAVE_DELAY_CR[3]; + __IO uint32_t WR_DQS_SLAVE_FORCE_CR; + __IO uint32_t WR_DQS_SLAVE_RATIO_CR[4]; + __IO uint32_t WR_DATA_SLAVE_DELAY_CR[3]; + __IO uint32_t WR_DATA_SLAVE_FORCE_CR; + __IO uint32_t WR_DATA_SLAVE_RATIO_CR[4]; + __IO uint32_t WRLVL_INIT_MODE_CR; + __IO uint32_t WRLVL_INIT_RATIO_CR[4]; + __IO uint32_t WR_RD_RL_CR; + __IO uint32_t RDC_FIFO_RST_ERRCNTCLR_CR; + __IO uint32_t RDC_WE_TO_RE_DELAY_CR; + __IO uint32_t USE_FIXED_RE_CR; + __IO uint32_t USE_RANK0_DELAYS_CR; + __IO uint32_t USE_LVL_TRNG_LEVEL_CR; + __IO uint32_t CONFIG_CR; + __IO uint32_t RD_WR_GATE_LVL_CR; + __IO uint32_t DYN_RESET_CR; + + /*---------------------------------------------------------------------- + * DDR PHY status registers + */ + __I uint32_t LEVELLING_FAILURE_SR; + __I uint32_t BIST_ERROR_SR[3]; + __I uint32_t WRLVL_DQS_RATIO_SR[4]; + __I uint32_t WRLVL_DQ_RATIO_SR[4]; + __I uint32_t RDLVL_DQS_RATIO_SR[4]; + __I uint32_t FIFO_SR[4]; + __I uint32_t MASTER_DLL_SR; + __I uint32_t DLL_SLAVE_VALUE_SR[2]; + __I uint32_t STATUS_OF_IN_DELAY_VAL_SR[2]; + __I uint32_t STATUS_OF_OUT_DELAY_VAL_SR[2]; + __I uint32_t DLL_LOCK_AND_SLAVE_VAL_SR; + __I uint32_t CTRL_OUTPUT_FILTER_SR; + __I uint32_t CTRL_OF_OUTPUT_DELAY_SR; + __I uint32_t RD_DQS_SLAVE_DLL_VAL_SR[3]; + __I uint32_t WR_DATA_SLAVE_DLL_VAL_SR[3]; + __I uint32_t FIFO_WE_SLAVE_DLL_VAL_SR[3]; + __I uint32_t WR_DQS_SLAVE_DLL_VAL_SR[3]; + __I uint32_t CTRL_SLAVE_DLL_VAL_SR; + __IO uint32_t RESERVED2[13]; + } phy; + + /*-------------------------------------------------------------------------- + * FIC-64 registers + * These registers are 16-bit wide and 32-bit aligned. + */ + struct + { + __IO uint32_t NB_ADDR_CR; + __IO uint32_t NBRWB_SIZE_CR; + __IO uint32_t WB_TIMEOUT_CR; + __IO uint32_t HPD_SW_RW_EN_CR; + __IO uint32_t HPD_SW_RW_INVAL_CR; + __IO uint32_t SW_WR_ERCLR_CR; + __IO uint32_t ERR_INT_ENABLE_CR; + __IO uint32_t NUM_AHB_MASTERS_CR; + __I uint32_t HPB_ERR_ADDR_SR[2]; + __I uint32_t SW_ERR_ADDR_SR[2]; + __I uint32_t HPD_SW_WRB_EMPTY_SR; + __I uint32_t SW_HPB_LOCKOUT_SR; + __I uint32_t SW_HPD_WERR_SR; + uint32_t RESERVED0; + __IO uint32_t LOCK_TIMEOUTVAL_CR[2]; + __IO uint32_t LOCK_TIMEOUT_EN_CR; + uint32_t RESERVED1[5]; + __IO uint32_t RDWR_ERR_SR; + } fic; +} DDRCore_TypeDef; + +/*----------------------------------------------------------------------------*/ +/*--------------------- MDDR APB Configuration Registers ---------------------*/ +/*----------------------------------------------------------------------------*/ +typedef struct +{ + /*-------------------------------------------------------------------------- + * MDDR core configuration registers. + * These registers are to be accessed as: + * MDDR->core.fic.<regname> = <value>; + * MDDR->core.phy.<regname> = <value>; + * MDDR->core.ddrc.<regname> = <value>; + */ + DDRCore_TypeDef core; + +} MDDR_TypeDef; + + +/*----------------------------------------------------------------------------*/ +/*--------------------- FDDR APB Configuration Registers ---------------------*/ +/*----------------------------------------------------------------------------*/ +typedef struct +{ + /*-------------------------------------------------------------------------- + * FDDR core configuration registers. These are same as corresponding + * MDDR registers. + * These registers are to be accessed as: + * FDDR->core.fic.<regname> = <value>; + * FDDR->core.phy.<regname> = <value>; + * FDDR->core.ddrc.<regname> = <value>; + */ + DDRCore_TypeDef core; + __IO uint32_t RESERVED[39]; + + /*-------------------------------------------------------------------------- + * FDDR system registers + * These registers are to be accessed as: + * FDDR->sysreg.PLL_CONFIG_LOW_2 = 0x04u; + */ + struct + { + __IO uint32_t PLL_CONFIG_LOW_1; + __IO uint32_t PLL_CONFIG_LOW_2; + __IO uint32_t PLL_CONFIG_HIGH; + __IO uint32_t FACC_CLK_EN; + __IO uint32_t FACC_MUX_CONFIG; + __IO uint32_t FACC_DIVISOR_RATIO; + __IO uint32_t PLL_DELAY_LINE_SEL; + __IO uint32_t SOFT_RESET; + __IO uint32_t IO_CALIB; + __IO uint32_t INTERRUPT_ENABLE; + __IO uint32_t AXI_AHB_MODE_SEL; + __IO uint32_t PHY_SELF_REF_EN; + __IO uint32_t FAB_PLL_CLK_SR; + __IO uint32_t FPLL_CLK_SR; + __IO uint32_t CLK_CALIB_STATUS; + __IO uint32_t INTERRUPT_SR; + __IO uint32_t CLK_CALIB_CONFIG; + __IO uint32_t IO_CALIB_SR; + __IO uint32_t FATC_RESET; + } sysreg; +} FDDR_TypeDef; + +/*----------------------------------------------------------------------------*/ +/*------------------------------ SERDES Interface ----------------------------*/ +/*----------------------------------------------------------------------------*/ + +/*------------------------------------------------------------------------------ + AXI window + */ +typedef struct +{ + __IO uint32_t base; + __IO uint32_t size; + __IO uint32_t window_lsb; + __IO uint32_t window_msb; +} axi_window_TypeDef; + +/*------------------------------------------------------------------------------ + PCI Express Bridge Core registers. + + This data structure is used to access to the registers of the PCI Express + Bridge Core. + */ +typedef struct +{ + /*======================= Information registers ======================*/ + /** + Information register: vendor_id & device_id + bits [15:0] vendor_id + bits [31:16] device_id + */ + /* 0x000 */ + __IO uint32_t VID_DEVID; + + /** + PCI Express Control & Status Register: cfg_prmscr + */ + /* 0x004 */ + __IO uint32_t CFG_PRMSCR; + + /** + Information register: class_code + */ + /* 0x008 */ + __IO uint32_t CLASS_CODE; + + __IO uint32_t RESERVED0; + + /** + Bridge Configuration Register: bar0 + */ + /* 0x010 */ + __IO uint32_t BAR0; + + /** + Bridge Configuration Register: bar1 + */ + /* 0x014 */ + __IO uint32_t BAR1; + + /** + Bridge Configuration Register: bar2 + */ + /* 0x018 */ + __IO uint32_t BAR2; + + /** + Bridge Configuration Register: bar3 + */ + /* 0x01C */ + __IO uint32_t BAR3; + + /** + Bridge Configuration Register: bar4 + */ + /* 0x020 */ + __IO uint32_t BAR4; + + /** + Bridge Configuration Register: bar5 + */ + /* 0x024 */ + __IO uint32_t BAR5; + + __IO uint32_t RESERVED1; + + /** + Information register: subsystem_id + */ + /* 0x02C */ + __IO uint32_t SUBSYSTEM_ID; + + /** + PCI Express Control & Status Register: pcie_devscr + */ + /* 0x030 */ + __IO uint32_t PCIE_DEVSCR; + + /** + PCI Express Control & Status Register: pcie_linkscr + */ + /* 0x034 */ + __IO uint32_t PCIE_LINKSCR; + + /** + Bridge Configuration Register: tc_vc_mapping + */ + /* 0x038 */ + __IO uint32_t TC_VC_MAPPING; + + /** + Information register: captured_bus_device_nb + */ + /* 0x03C */ + __IO uint32_t CAPTURED_BUS_DEVICE_NB; + + /** + Endpoint Interrupt register: msi_ctrl_status + */ + /* 0x040 */ + __IO uint32_t MSI_CTRL_STATUS; + + /** + Power Management register: ltssm + */ + /* 0x044 */ + __IO uint32_t LTSSM; + + /** + Power Management register: power_mgt_capability + */ + /* 0x048 */ + __IO uint32_t POWER_MGT_CAPABILITY; + + /** + PCI Express Control & Status Register: cfg_pmscr + */ + /* 0x04C */ + __IO uint32_t CFG_PMSCR; + + /** + Bridge Configuration Register: aer_ecrc_capability + */ + /* 0x050 */ + __IO uint32_t AER_ECRC_CAPABILITY; + + /** + Bridge Configuration Register: vc1_capability + */ + /* 0x054 */ + __IO uint32_t VC1_CAPABILITY; + + /** + Bridge Configuration Register: max_payload_size + */ + /* 0x058 */ + __IO uint32_t MAX_PAYLOAD_SIZE; + + /** + Bridge Configuration Register: clkreq + */ + /* 0x05C */ + __IO uint32_t CLKREQ; + + /** + Power Management register: aspm_l0s_capability + */ + /* 0x060 */ + __IO uint32_t ASPM_L0S_CAPABILITY; + + /** + Power Management register: aspm_l1_capability + */ + /* 0x064 */ + __IO uint32_t ASPM_L1_CAPABILITY; + + /** + Power Management register: timeout_completion + */ + /* 0x068 */ + __IO uint32_t TIMEOUT_COMPLETION; + + __IO uint32_t RESERVED2; + + /** + Power Management register: pm_data_scale + */ + /* 0x070 */ + __IO uint32_t PM_DATA_SCALE[4]; + + /** + Endpoint Interrupt register: msi + */ + /* 0x080 */ + __IO uint32_t MSI[8]; + + /** + Bridge Configuration Register: error_counter + */ + /* 0x0A0 */ + __IO uint32_t ERROR_COUNTER[4]; + + /** + Bridge Configuration Register: credit_allocation + */ + /* 0x0B0 */ + __IO uint32_t CREDIT_ALLOCATION[4]; + + /** + Address Mapping register: axi_slave_window + */ + /* 0x0C0 */ + axi_window_TypeDef AXI_SLAVE_WINDOW[4]; + + /** + Address Mapping register: axi_master_window + */ + /* 0x100 */ + axi_window_TypeDef AXI_MASTER_WINDOW[4]; + + /** + Rootport Interrupt register: imask + */ + /* 0x140 */ + __IO uint32_t IMASK; + + /** + Rootport Interrupt register: istatus + */ + /* 0x144 */ + __IO uint32_t ISTATUS; + + /** + Rootport Interrupt register: icmd + */ + /* 0x148 */ + __IO uint32_t ICMD; + + /** + Rootport Interrupt register: irstatus + */ + /* 0x14C */ + __IO uint32_t IRSTATUS; + + /** + Rootport Interrupt register: imsiaddr + */ + /* 0x150 */ + __IO uint32_t IMSIADDR; + + /** + PCI Express Control & Status Register: slotcap + */ + /* 0x154 */ + __IO uint32_t SLOTCAP; + + /** + PCI Express Control & Status Register: slotcsr + */ + /* 0x158 */ + __IO uint32_t SLOTCSR; + + /** + PCI Express Control & Status Register: rootcsr + */ + /* 0x15C */ + __IO uint32_t ROOTCSR; + + /** + Configuration Register: cfg_control + */ + /* 0x160 */ + __IO uint32_t CFG_CONTROL; + + /** + Configuration Register: cfg_write_data + */ + /* 0x164 */ + __IO uint32_t CFG_WRITE_DATA; + + /** + Configuration Register: cfg_read_data + */ + /* 0x168 */ + __IO uint32_t CFG_READ_DATA; + + /** + Information register: info + */ + /* 0x16C */ + __IO uint32_t INFO; + + /** + Input/Output Control Register: io_control + */ + /* 0x170 */ + __IO uint32_t IO_CONTROL; + + /** + Input/Output Control Register: io_addr + */ + /* 0x174 */ + __IO uint32_t IO_ADDR; + + /** + Input/Output Control Register: io_write_data + */ + /* 0x178 */ + __IO uint32_t IO_WRITE_DATA; + + /** + Input/Output Control Register: io_read_data + */ + /* 0x17C */ + __IO uint32_t IO_READ_DATA; + + /** + Configuration Register: cfg_fbe + */ + /* 0x180 */ + __IO uint32_t CFG_FBE; + + /** + Address Mapping register: prefetch_io_window + */ + /* 0x184 */ + __IO uint32_t PREFETCH_IO_WINDOW; + + __IO uint32_t RESERVED4[31]; + + /** + Bridge Configuration Register: pcie_config + */ + /* 0x204 */ + __IO uint32_t PCIE_CONFIG; + + __IO uint32_t RESERVED5[10]; + + /** + PCI Express Control & Status Register: pcie_dev2scr + */ + /* 0x230 */ + __IO uint32_t PCIE_DEV2SCR; + + /** + PCI Express Control & Status Register: pcie_link2scr + */ + /* 0x234 */ + __IO uint32_t PCIE_LINK2SCR; + + __IO uint32_t RESERVED6[10]; + + /** + Power Management register: aspm_l0s_gen2 capability + */ + /* 0x260 */ + __IO uint32_t ASPM_L0S_GEN2; + + __IO uint32_t RESERVED7[39]; + + /** + Bridge Configuration Register: k_cnt_config + */ + /* 0x300 */ + __IO uint32_t K_CNT_CONFIG[6]; + + __IO uint32_t RESERVED8[826]; + +} PCIE_TypeDef; + +/*------------------------------------------------------------------------------ + SERDESIF System Registers. + */ +typedef struct +{ + __IO uint32_t SER_PLL_CONFIG_LOW; + __IO uint32_t SER_PLL_CONFIG_HIGH; + __IO uint32_t SERDESIF_SOFT_RESET; + __IO uint32_t SER_INTERRUPT_ENABLE; + __IO uint32_t CONFIG_AXI_AHB_BRIDGE; + __IO uint32_t CONFIG_ECC_INTR_ENABLE; + __IO uint32_t CONFIG_TEST_IN; + __IO uint32_t TEST_OUT_READ_ADDR; + __IO uint32_t CONFIG_PCIE_PM; + __IO uint32_t CONFIG_PHY_MODE_0; + __IO uint32_t CONFIG_PHY_MODE_1; + __IO uint32_t CONFIG_PHY_MODE_2; + __IO uint32_t CONFIG_PCIE_0; + __IO uint32_t CONFIG_PCIE_1; + __IO uint32_t CONFIG_PCIE_2; + __IO uint32_t CONFIG_PCIE_3; + __IO uint32_t CONFIG_BAR_SIZE_0_1; + __IO uint32_t CONFIG_BAR_SIZE_2_3; + __IO uint32_t CONFIG_BAR_SIZE_3_4; + __IO uint32_t SER_CLK_STATUS; + __IO uint32_t SER_CLK_CALIB_STATUS; + __IO uint32_t TEST_OUT_READ_DATA; + __IO uint32_t SER_INTERRUPT; + __IO uint32_t SERDESIF_INTR_STATUS; + __IO uint32_t SER_CLK_CALIB_CONFIG; + __IO uint32_t REFCLK_SEL; + __IO uint32_t PCLK_SEL; + __IO uint32_t EPCS_RSTN_SEL; + __IO uint32_t CHIP_ENABLES; + __IO uint32_t SERDES_TEST_OUT; + __IO uint32_t SERDES_FATC_RESET; + __IO uint32_t RC_OSC_SPLL_REFCLK_SEL; + __IO uint32_t SPREAD_SPECTRUM_CLK; + __IO uint32_t CONF_AXI_MSTR_WNDW_0; + __IO uint32_t CONF_AXI_MSTR_WNDW_1; + __IO uint32_t CONF_AXI_MSTR_WNDW_2; + __IO uint32_t CONF_AXI_MSTR_WNDW_3; + __IO uint32_t CONF_AXI_SLV_WNDW_0; + __IO uint32_t CONF_AXI_SLV_WNDW_1; + __IO uint32_t CONF_AXI_SLV_WNDW_2; + __IO uint32_t CONF_AXI_SLV_WNDW_3; + __IO uint32_t DESKEW_CONFIG; + __IO uint32_t DEBUG_MODE_KEY; + __IO uint32_t RESERVED0; + /* + * The following registers are only available on the M2S090. + */ + __IO uint32_t IDDQ; + __IO uint32_t ADVCONFIG; + __IO uint32_t ADVSTATUS; + __IO uint32_t ECC_ERR_INJECT; + __IO uint32_t RESERVED2; + __IO uint32_t RESERVED3; + __IO uint32_t ENHANCEMENT; + __IO uint32_t RESERVED4; + __IO uint32_t RESERVED5; + __IO uint32_t RESERVED6; + __IO uint32_t RESERVED7; + __IO uint32_t RESERVED8; + __IO uint32_t RESERVED9; + __IO uint32_t RESERVED10; + __IO uint32_t RESERVED11; + __IO uint32_t RESERVED12; + __IO uint32_t RESERVED13; + __IO uint32_t RESERVED14; + __IO uint32_t RESERVED15; + __IO uint32_t RESERVED16; + __IO uint32_t RESERVED17; + __IO uint32_t RESERVED18; + __IO uint32_t RESERVED19; + __IO uint32_t RESERVED20; + __IO uint32_t CONFIG2_AXI_AHB_BRIDGE; + __IO uint32_t CONFIG2_ECC_INTR_ENABLE; + __IO uint32_t CONFIG2_TEST_IN; + __IO uint32_t TEST2_OUT_READ_ADDR; + __IO uint32_t CONFIG2_PCIE_PM; + __IO uint32_t RESERVED21; + __IO uint32_t RESERVED22; + __IO uint32_t RESERVED23; + __IO uint32_t CONFIG2_PCIE_0; + __IO uint32_t CONFIG2_PCIE_1; + __IO uint32_t CONFIG2_PCIE_2; + __IO uint32_t CONFIG2_PCIE_3; + __IO uint32_t CONFIG2_BAR_SIZE_0_1; + __IO uint32_t CONFIG2_BAR_SIZE_2_3; + __IO uint32_t CONFIG2_BAR_SIZE_3_4; + __IO uint32_t RESERVED24; + __IO uint32_t RESERVED25; + __IO uint32_t TEST2_OUT_READ_DATA; + __IO uint32_t RESERVED26; + __IO uint32_t SERDESIF2_INTR_STATUS; + __IO uint32_t RESERVED27; + __IO uint32_t RESERVED28; + __IO uint32_t RESERVED29; + __IO uint32_t RESERVED30; + __IO uint32_t RESERVED31; + __IO uint32_t RESERVED32; + __IO uint32_t RESERVED33; + __IO uint32_t RESERVED34; + __IO uint32_t RESERVED35; + __IO uint32_t CONF2_AXI_MSTR_WNDW_0; + __IO uint32_t CONF2_AXI_MSTR_WNDW_1; + __IO uint32_t CONF2_AXI_MSTR_WNDW_2; + __IO uint32_t CONF2_AXI_MSTR_WNDW_3; + __IO uint32_t CONF2_AXI_SLV_WNDW_0; + __IO uint32_t CONF2_AXI_SLV_WNDW_1; + __IO uint32_t CONF2_AXI_SLV_WNDW_2; + __IO uint32_t CONF2_AXI_SLV_WNDW_3; + __IO uint32_t RESERVED36; + __IO uint32_t RESERVED37; + __IO uint32_t RESERVED38; + __IO uint32_t RESERVED39; + __IO uint32_t ADVCONFIG2; + __IO uint32_t ADVSTATUS2; + __IO uint32_t ECC_ERR_INJECT2; +} SERDES_INTF_SYSREG_TypeDef; + +/*------------------------------------------------------------------------------ + SERDES PHY registers + */ +typedef struct +{ + /** + Control register 0 + */ + __IO uint32_t CR0; + + /** + Clock count for error counter decrement + */ + __IO uint32_t ERRCNT_DEC; + + /** + Error counter threshold - Rx idle detect max latency + */ + __IO uint32_t RXIDLE_MAX_ERRCNT_THR; + + /** + Tx Impedance ratio + */ + __IO uint32_t IMPED_RATIO; + + /** + PLL F settings and PCLK ratio + */ + __IO uint32_t PLL_F_PCLK_RATIO; + + /** + PLL M & N settings + */ + __IO uint32_t PLL_M_N; + + /** + 250ns timer base count + */ + __IO uint32_t CNT250NS_MAX; + + /** + Rx Equalization amplitude ratio + */ + __IO uint32_t RE_AMP_RATIO; + + /** + Rx Equalization Cut frequency + */ + __IO uint32_t RE_CUT_RATIO; + + /** + Tx Amplitude ratio + */ + __IO uint32_t TX_AMP_RATIO; + + /** + Tx Post-Cursor ratio + */ + __IO uint32_t TX_PST_RATIO; + + /** + Tx Pre-Cursor ratio + */ + __IO uint32_t TX_PRE_RATIO; + + /** + End of calibration counter + */ + __IO uint32_t ENDCALIB_MAX; + + /** + Calibration stability counter + */ + __IO uint32_t CALIB_STABILITY_COUNT; + + /** + Power down feature + */ + __IO uint32_t POWER_DOWN; + + /** + Rx offset counter + */ + __IO uint32_t RX_OFFSET_COUNT; + + /** + PLL F settings and PCLK ratio (in PCIe 5 Gbps speed) + */ + __IO uint32_t PLL_F_PCLK_RATIO_5GBPS; + + /** + PLL M & N sttings (in PCIe 5 Gbps spped) + */ + __IO uint32_t PLL_M_N_5GBPS; + + /** + 250ns timer base count (in PCIe 5 Gbps speed) + */ + __IO uint32_t CNT250NS_MAX_5GBPS; + + /** + reserved + */ + __IO uint32_t RESERVED; + + /** + Tx Post-Cursor ratio with TxDeemp=0, Full swing + */ + __IO uint32_t TX_PST_RATIO_DEEMP0_FULL; + + /** + Tx Pre-Cursor ratio TxDeemp=0, full swing + */ + __IO uint32_t TX_PRE_RATIO_DEEMP0_FULL; + + /** + Tx Post-Cursor ratio with TxDeemp=1, Full swing + */ + __IO uint32_t TX_PST_RATIO_DEEMP1_FULL; + + /** + Tx Pre-Cursor ratio TxDeemp=1, full swing + */ + __IO uint32_t TX_PRE_RATIO_DEEMP1_FULL; + + /** + Tx Amplitude ratio TxMargin=0, full swing + */ + __IO uint32_t TX_AMP_RATIO_MARGIN0_FULL; + + /** + Tx Amplitude ratio TxMargin=1, full swing + */ + __IO uint32_t TX_AMP_RATIO_MARGIN1_FULL; + + /** + Tx Amplitude ratio TxMargin=2, full swing + */ + __IO uint32_t TX_AMP_RATIO_MARGIN2_FULL; + + /** + Tx Amplitude ratio TxMargin=3, full swing + */ + __IO uint32_t TX_AMP_RATIO_MARGIN3_FULL; + + /** + Tx Amplitude ratio TxMargin=4, full swing + */ + __IO uint32_t TX_AMP_RATIO_MARGIN4_FULL; + + /** + Tx Amplitude ratio TxMargin=5, full swing + */ + __IO uint32_t TX_AMP_RATIO_MARGIN5_FULL; + + /** + Tx Amplitude ratio TxMargin=6, full swing + */ + __IO uint32_t TX_AMP_RATIO_MARGIN6_FULL; + + /** + Tx Amplitude ratio TxMargin=7, full swing + */ + __IO uint32_t TX_AMP_RATIO_MARGIN7_FULL; + + /** + Rx Equalization amplitude ratio TxDeemp=0 + */ + __IO uint32_t RE_AMP_RATIO_DEEMP0; + + /** + Rx Equalization Cut frequency TxDeemp=0 + */ + __IO uint32_t RE_CUT_RATIO_DEEMP0; + + /** + Rx Equalization amplitude ratio TxDeemp=1 + */ + __IO uint32_t RE_AMP_RATIO_DEEMP1; + + /** + Rx Equalization Cut frequency TxDeemp=1 + */ + __IO uint32_t RE_CUT_RATIO_DEEMP1; + + /** + Tx Post-Cursor ratio with TxDeemp=0, Half swing + */ + __IO uint32_t TX_PST_RATIO_DEEMP0_HALF; + + /** + Tx Pre-Cursor ratio TxDeemp=0, Half swing + */ + __IO uint32_t TX_PRE_RATIO_DEEMP0_HALF; + + /** + Tx Post-Cursor ratio with TxDeemp=1, Half swing + */ + __IO uint32_t TX_PST_RATIO_DEEMP1_HALF; + + /** + Tx Pre-Cursor ratio TxDeemp=1, Half swing + */ + __IO uint32_t TX_PRE_RATIO_DEEMP1_HALF; + + /** + Tx Amplitude ratio TxMargin=0, Half swing + */ + __IO uint32_t TX_AMP_RATIO_MARGIN0_HALF; + + /** + Tx Amplitude ratio TxMargin=1, Half swing + */ + __IO uint32_t TX_AMP_RATIO_MARGIN1_HALF; + + /** + Tx Amplitude ratio TxMargin=2, Half swing + */ + __IO uint32_t TX_AMP_RATIO_MARGIN2_HALF; + + /** + Tx Amplitude ratio TxMargin=3, Half swing + */ + __IO uint32_t TX_AMP_RATIO_MARGIN3_HALF; + + /** + Tx Amplitude ratio TxMargin=4, Half swing + */ + __IO uint32_t TX_AMP_RATIO_MARGIN4_HALF; + + /** + Tx Amplitude ratio TxMargin=5, Half swing + */ + __IO uint32_t TX_AMP_RATIO_MARGIN5_HALF; + + /** + Tx Amplitude ratio TxMargin=6, Half swing + */ + __IO uint32_t TX_AMP_RATIO_MARGIN6_HALF; + + /** + Tx Amplitude ratio TxMargin=7, Half swing + */ + __IO uint32_t TX_AMP_RATIO_MARGIN7_HALF; + + /** + PMA status + */ + __IO uint32_t PMA_STATUS; + + /** + Tx sweep center (RO) + */ + __IO uint32_t TX_SWEEP_CENTER; + + /** + Rx seep center (RO) + */ + __IO uint32_t RX_SWEEP_CENTER; + + /** + Rx Equalization sweep center (RO) + */ + __IO uint32_t RE_SWEEP_CENTER; + + /** + Receiver Shift Loader parameter 0 (RO) + */ + __IO uint32_t ATXDRR_7_0; + + /** + Receiver Shift Loader parameter 1 (RO) + */ + __IO uint32_t ATXDRR_14_8; + + /** + Transmitter P Shift Loader parameter0-0 + */ + __IO uint32_t ATXDRP_DYN_7_0; + + /** + Transmitter P Shift Loader parameter0-1 + */ + __IO uint32_t ATXDRP_DYN_15_8; + + /** + Transmitter P Shift Loader parameter0-2 + */ + __IO uint32_t ATXDRP_DYN_20_16; + + /** + Transmitter A Shift Loader parameter0-0 + */ + __IO uint32_t ATXDRA_DYN_7_0; + + /** + Transmitter A Shift Loader parameter0-1 + */ + __IO uint32_t ATXDRA_DYN_15_8; + + /** + Transmitter A Shift Loader parameter0-2 + */ + __IO uint32_t ATXDRA_DYN_20_16; + + /** + Transmitter T Shift Loader parameter0-0 + */ + __IO uint32_t ATXDRT_DYN_7_0; + + /** + Transmitter T Shift Loader parameter0-1 + */ + __IO uint32_t ATXDRT_DYN_15_8; + + /** + Transmitter T Shift Loader parameter0-2 + */ + __IO uint32_t ATXDRT_DYN_20_16; + + /** + Transmitter P Shift Loader parameter 1-0 (RO) + */ + __IO uint32_t ATXDRP_EI1_7_0; + + /** + Transmitter P Shift Loader parameter 1-1 (RO) + */ + __IO uint32_t ATXDRP_EI1_15_8; + + /** + Transmitter P Shift Loader parameter 1-2 (RO) + */ + __IO uint32_t ATXDRP_EI1_20_16; + + /** + Transmitter A Shift Loader parameter 1-0 (RO) + */ + __IO uint32_t ATXDRA_EI1_7_0; + + /** + Transmitter A Shift Loader parameter 1-1 (RO) + */ + __IO uint32_t ATXDRA_EI1_15_8; + + /** + Transmitter A Shift Loader parameter 1-2 (RO) + */ + __IO uint32_t ATXDRA_EI1_20_16; + + /** + Transmitter T Shift Loader parameter 1-0 (RO) + */ + __IO uint32_t ATXDRT_EI1_7_0; + + /** + Transmitter T Shift Loader parameter 1-1 (RO) + */ + __IO uint32_t ATXDRT_EI1_15_8; + + /** + Transmitter T Shift Loader parameter 1-2 (RO) + */ + __IO uint32_t ATXDRT_EI1_20_16; + + /** + Transmitter P shift Loader parameter 2-0 (RO) + */ + __IO uint32_t ATXDRP_EI2_7_0; + + /** + Transmitter P shift Loader parameter 2-1 (RO) + */ + __IO uint32_t ATXDRP_EI2_15_8; + + /** + Transmitter P shift Loader parameter 2-2 (RO) + */ + __IO uint32_t ATXDRP_EI2_20_16; + + /** + Transmitter A Shift parametr 2-0 (RO) + */ + __IO uint32_t ATXDRA_EI2_7_0; + + /** + Transmitter A Shift parametr 2-1 (RO) + */ + __IO uint32_t ATXDRA_EI2_15_8; + + /** + Transmitter A Shift parametr 2-2 (RO) + */ + __IO uint32_t ATXDRA_EI2_20_16; + + /** + Transmitter T Shift parametr 2-0 (RO) + */ + __IO uint32_t ATXDRT_EI2_7_0; + + /** + Transmitter T Shift parametr 2-1 (RO) + */ + __IO uint32_t ATXDRT_EI2_15_8; + + /** + Transmitter T Shift parametr 2-2 (RO) + */ + __IO uint32_t ATXDRT_EI2_20_16; + + /** + Override calibration register (RW) + */ + __IO uint32_t OVERRIDE_CALIB; + + /** + Force Receiver Shift Loader parameter 0 (RW) + */ + __IO uint32_t FORCE_ATXDRR_7_0; + + /** + Force Receiver Shift Loader parameter 1 (RW) + */ + __IO uint32_t FORCE_ATXDRR_15_8; + + /** + Force Receiver Shift Loader parameter 2 (RW) + */ + __IO uint32_t FORCE_ATXDRR_20_16; + + /** + Force Transmitter P Shift Loader parameter 0 (RW) + */ + __IO uint32_t FORCE_ATXDRP_7_0; + + /** + Force Transmitter P Shift Loader parameter 1 (RW) + */ + __IO uint32_t FORCE_ATXDRP_15_8; + + /** + Force Transmitter P Shift Loader parameter 2 (RW) + */ + __IO uint32_t FORCE_ATXDRP_20_16; + + /** + Force Transmitter A Shift Loader parameter 0 (RW) + */ + __IO uint32_t FORCE_ATXDRA_7_0; + + /** + Force Transmitter A Shift Loader parameter 1 (RW) + */ + __IO uint32_t FORCE_ATXDRA_15_8; + + /** + Force Transmitter A Shift Loader parameter 2 (RW) + */ + __IO uint32_t FORCE_ATXDRA_20_16; + + /** + Force Transmitter T Shift parameter 0-0 (RO) + */ + __IO uint32_t FORCE_ATXDRT_7_0; + + /** + Force Transmitter T Shift parameter 0-1 (RO) + */ + __IO uint32_t FORCE_ATXDRT_15_8; + + /** + Force Transmitter T Shift parameter 0-2 (RO) + */ + __IO uint32_t FORCE_ATXDRT_20_16; + + /** + RxD offset calibration result (RO) + */ + __IO uint32_t RXD_OFFSET_CALIB_RESULT; + + /** + RxT offset calibration result (RO) + */ + __IO uint32_t RXT_OFFSET_CALIB_RESULT; + + /** + Schmitt trigger calibration result (RO) + */ + __IO uint32_t SCHMITT_TRIG_CALIB_RESULT; + + /** + Force RxD offset calibration settings (RW) + */ + __IO uint32_t FORCE_RXD_OFFSET_CALIB; + + /** + Force RxT offset calibration settings (RW) + */ + __IO uint32_t FORCE_RXT_OFFSET_CALIB; + + /** + Force Schmitt trigger calibration settings (RW) + */ + __IO uint32_t FORCE_SCHMITT_TRIG_CALIB; + + /** + PRBS control register (RW) + */ + __IO uint32_t PRBS_CTRL; + + /** + PRBS error counter register (RO) + */ + __IO uint32_t PRBS_ERRCNT; + + /** + PHY reset override register (RW) + */ + __IO uint32_t PHY_RESET_OVERRIDE; + + /** + PHY power override register (RW) + */ + __IO uint32_t PHY_POWER_OVERRIDE; + + /** + Custom Pattern Byte 0 (RW) + */ + __IO uint32_t CUSTOM_PATTERN_7_0; + + /** + Custom Pattern Byte 1 (RW) + */ + __IO uint32_t CUSTOM_PATTERN_15_8; + + /** + Custom Pattern Byte 2 (RW) + */ + __IO uint32_t CUSTOM_PATTERN_23_16; + + /** + Custom Pattern Byte 3 (RW) + */ + __IO uint32_t CUSTOM_PATTERN_31_24; + + /** + Custom Pattern Byte 4 (RW) + */ + __IO uint32_t CUSTOM_PATTERN_39_32; + + /** + Custom Pattern Byte 5 (RW) + */ + __IO uint32_t CUSTOM_PATTERN_47_40; + + /** + Custom Pattern Byte 6 (RW) + */ + __IO uint32_t CUSTOM_PATTERN55_48; + + /** + Custom Pattern Byte 7 (RW) + */ + __IO uint32_t CUSTOM_PATTERN_63_56; + + /** + Custom Pattern Byte 8 (RW) + */ + __IO uint32_t CUSTOM_PATTERN_71_64; + + /** + Custom Pattern Byte 9 (RW) + */ + __IO uint32_t CUSTOM_PATTERN_79_72; + + /** + Custom Pattern Control (RW) + */ + __IO uint32_t CUSTOM_PATTERN_CTRL; + + /** + Custom Pattern Status register (RO) + */ + __IO uint32_t CUSTOM_PATTERN_STATUS; + + /** + PCS Loopback Control (RW) + */ + __IO uint32_t PCS_LOOPBBACK_CTRL; + + /** + Gen1 Transmit PLL Current Charge Pump (RW) + */ + __IO uint32_t GEN1_TX_PLL_CCP; + + /** + Gen1 Receive PLL Current Charge Pump (RW) + */ + __IO uint32_t GEN1_RX_PLL_CCP; + + /** + Gen2 Transmit PLL Current Charge Pump (RW) + */ + __IO uint32_t GEN2_TX_PLL_CCP; + + /** + Gen2 Receive PLL Current Charge Pump (RW) + */ + __IO uint32_t GEN2_RX_PLL_CCP; + + /** + CDR PLL manual control + */ + __IO uint32_t CDR_PLL_MANUAL_CR; + + /** + Reserved0 + */ + __IO uint32_t RESERVED0[6]; + + /** + Update settings command register + */ + __IO uint32_t UPDATE_SETTINGS; + + /** + Reserved1 + */ + __IO uint32_t RESERVED1[31]; + + /** + PRBS first error cycle counter bits [7:0] + */ + __IO uint32_t PRBS_ERR_CYC_FIRST_7_0; + + /** + PRBS first error cycle counter bits [15:8] + */ + __IO uint32_t PRBS_ERR_CYC_FIRST_15_8; + + /** + PRBS first error cycle counter bits [23:16] + */ + __IO uint32_t PRBS_ERR_CYC_FIRST_23_16; + + /** + PRBS first error cycle counter bits [31:24] + */ + __IO uint32_t PRBS_ERR_CYC_FIRST_31_24; + + /** + PRBS first error cycle counter bits [39:32] + */ + __IO uint32_t PRBS_ERR_CYC_FIRST_39_32; + + /** + PRBS first error cycle counter bits [47:40] + */ + __IO uint32_t PRBS_ERR_CYC_FIRST_47_40; + + /** + PRBS first error cycle counter bits [49:48] + */ + __IO uint32_t PRBS_ERR_CYC_FIRST_49_48; + + /** + Reserved2 + */ + __IO uint32_t RESERVED2; + + /** + PRBS last error cycle counter bits [7:0] + */ + __IO uint32_t PRBS_ERR_CYC_LAST_7_0; + + /** + PRBS last error cycle counter bits [15:8] + */ + __IO uint32_t PRBS_ERR_CYC_LAST_15_8; + + /** + PRBS last error cycle counter bits [23:16] + */ + __IO uint32_t PRBS_ERR_CYC_LAST_23_16; + + /** + PRBS last error cycle counter bits [31:24] + */ + __IO uint32_t PRBS_ERR_CYC_LAST_31_24; + + /** + PRBS last error cycle counter bits [39:32] + */ + __IO uint32_t PRBS_ERR_CYC_LAST_39_32; + + /** + PRBS last error cycle counter bits [47:40] + */ + __IO uint32_t PRBS_ERR_CYC_LAST_47_40; + + /** + PRBS last error cycle counter bits [49:48] + */ + __IO uint32_t PRBS_ERR_CYC_LAST_49_48; + + /** + Reserved3 + */ + __IO uint32_t RESERVED3[81]; + +} SERDES_TypeDef; + +/*-------------------------------------------------------------------------*//** + The serdesif_regs_t data structure provides access to the complete set of the + SERDES Interface hardware block configuration registers. These registers are + accessed through the APB interface of the SERDES Interface hardware block. + */ +typedef struct +{ + /** + PCIe core registers. + */ + PCIE_TypeDef core; + + /** + SERDES macro registers. + */ + SERDES_TypeDef lane[4]; + + /** + SERDESIF system registers. + */ + SERDES_INTF_SYSREG_TypeDef sys_regs; + +} SERDESIF_TypeDef; + + +/*----------------------------------------------------------------------------*/ +/*------------------------------ System Registers ----------------------------*/ +/*----------------------------------------------------------------------------*/ +typedef struct +{ + __IO uint32_t ESRAM_CR; /*0X0 */ + __IO uint32_t ESRAM_MAX_LAT_CR; /*0X4 */ + __IO uint32_t DDR_CR; /*0X8 */ + __IO uint32_t ENVM_CR; /*0XC */ + __IO uint32_t ENVM_REMAP_BASE_CR; /*0X10 */ + __IO uint32_t ENVM_REMAP_FAB_CR; /*0X14 */ + __IO uint32_t CC_CR; /*0X18 */ + __IO uint32_t CC_REGION_CR; /*0X1C */ + __IO uint32_t CC_LOCK_BASE_ADDR_CR; /*0X20 */ + __IO uint32_t CC_FLUSH_INDX_CR; /*0X24 */ + __IO uint32_t DDRB_BUF_TIMER_CR; /*0X28 */ + __IO uint32_t DDRB_NB_ADDR_CR; /*0X2C */ + __IO uint32_t DDRB_NB_SIZE_CR; /*0X30 */ + __IO uint32_t DDRB_CR; /*0X34 */ + __IO uint32_t EDAC_CR; /*0X38 */ + __IO uint32_t MASTER_WEIGHT0_CR; /*0X3C */ + __IO uint32_t MASTER_WEIGHT1_CR; /*0X40 */ + __IO uint32_t SOFT_IRQ_CR; /*0X44 */ + __IO uint32_t SOFT_RST_CR; /*0X48 */ + __IO uint32_t M3_CR; /*0X4C */ + __IO uint32_t FAB_IF_CR; /*0X50 */ + __IO uint32_t LOOPBACK_CR; /*0X54 */ + __IO uint32_t GPIO_SYSRESET_SEL_CR; /*0X58 */ + __IO uint32_t GPIN_SRC_SEL_CR; /*0X5C */ + __IO uint32_t MDDR_CR; /*0X60 */ + __IO uint32_t USB_IO_INPUT_SEL_CR; /*0X64 */ + __IO uint32_t PERIPH_CLK_MUX_SEL_CR; /*0X68 */ + __IO uint32_t WDOG_CR; /*0X6C */ + __IO uint32_t MDDR_IO_CALIB_CR; /*0X70 */ + __IO uint32_t SPARE_OUT_CR; /*0X74 */ + __IO uint32_t EDAC_IRQ_ENABLE_CR; /*0X78 */ + __IO uint32_t USB_CR; /*0X7C */ + __IO uint32_t ESRAM_PIPELINE_CR; /*0X80 */ + __IO uint32_t MSS_IRQ_ENABLE_CR; /*0X84 */ + __IO uint32_t RTC_WAKEUP_CR; /*0X88 */ + __IO uint32_t MAC_CR; /*0X8C */ + __IO uint32_t MSSDDR_PLL_STATUS_LOW_CR; /*0X90 */ + __IO uint32_t MSSDDR_PLL_STATUS_HIGH_CR; /*0X94 */ + __IO uint32_t MSSDDR_FACC1_CR; /*0X98 */ + __IO uint32_t MSSDDR_FACC2_CR; /*0X9C */ + __IO uint32_t PLL_LOCK_EN_CR; /*0XA0 */ + __IO uint32_t MSSDDR_CLK_CALIB_CR; /*0XA4 */ + __IO uint32_t PLL_DELAY_LINE_SEL_CR; /*0XA8 */ + __IO uint32_t MAC_STAT_CLRONRD_CR; /*0XAC */ + __IO uint32_t RESET_SOURCE_CR; /*0XB0 */ + __I uint32_t CC_DC_ERR_ADDR_SR; /*0XB4 */ + __I uint32_t CC_IC_ERR_ADDR_SR; /*0XB8 */ + __I uint32_t CC_SB_ERR_ADDR_SR; /*0XBC */ + __I uint32_t CC_DECC_ERR_ADDR_SR; /*0XC0 */ + __I uint32_t CC_IC_MISS_CNT_SR; /*0XC4 */ + __I uint32_t CC_IC_HIT_CNT_SR; /*0XC8 */ + __I uint32_t CC_DC_MISS_CNT_SR; /*0XCC */ + __I uint32_t CC_DC_HIT_CNT_SR; /*0XD0 */ + __I uint32_t CC_IC_TRANS_CNT_SR; /*0XD4 */ + __I uint32_t CC_DC_TRANS_CNT_SR; /*0XD8 */ + __I uint32_t DDRB_DS_ERR_ADR_SR; /*0XDC */ + __I uint32_t DDRB_HPD_ERR_ADR_SR; /*0XE0 */ + __I uint32_t DDRB_SW_ERR_ADR_SR; /*0XE4 */ + __I uint32_t DDRB_BUF_EMPTY_SR; /*0XE8 */ + __I uint32_t DDRB_DSBL_DN_SR; /*0XEC */ + __I uint32_t ESRAM0_EDAC_CNT; /*0XF0 */ + __I uint32_t ESRAM1_EDAC_CNT; /*0XF4 */ + __I uint32_t CC_EDAC_CNT; /*0XF8 */ + __I uint32_t MAC_EDAC_TX_CNT; /*0XFC */ + __I uint32_t MAC_EDAC_RX_CNT; /*0X100 */ + __I uint32_t USB_EDAC_CNT; /*0X104 */ + __I uint32_t CAN_EDAC_CNT; /*0X108 */ + __I uint32_t ESRAM0_EDAC_ADR; /*0X10C */ + __I uint32_t ESRAM1_EDAC_ADR; /*0X110 */ + __I uint32_t MAC_EDAC_RX_ADR; /*0X114 */ + __I uint32_t MAC_EDAC_TX_ADR; /*0X118 */ + __I uint32_t CAN_EDAC_ADR; /*0X11C */ + __I uint32_t USB_EDAC_ADR; /*0X120 */ + __I uint32_t MM0_1_2_SECURITY; /*0X124 */ + __I uint32_t MM4_5_FIC64_SECURITY; /*0X128 */ + __I uint32_t MM3_6_7_8_SECURITY; /*0X12C */ + __I uint32_t MM9_SECURITY; /*0X130 */ + __I uint32_t M3_SR; /*0X134 */ + __I uint32_t ETM_COUNT_LOW; /*0X138 */ + __I uint32_t ETM_COUNT_HIGH; /*0X13C */ + __I uint32_t DEVICE_SR; /*0X140 */ + __I uint32_t ENVM_PROTECT_USER; /*0X144 */ + __I uint32_t ENVM_STATUS; /*0X148 */ + __I uint32_t DEVICE_VERSION; /*0X14C */ + __I uint32_t MSSDDR_PLL_STATUS; /*0X150 */ + __I uint32_t USB_SR; /*0X154 */ + __I uint32_t ENVM_SR; /*0X158 */ + __I uint32_t SPARE_IN; /*0X15C */ + __I uint32_t DDRB_STATUS; /*0X160 */ + __I uint32_t MDDR_IO_CALIB_STATUS; /*0X164 */ + __I uint32_t MSSDDR_CLK_CALIB_STATUS; /*0X168 */ + __I uint32_t WDOGLOAD; /*0X16C */ + __I uint32_t WDOGMVRP; /*0X170 */ + __I uint32_t USERCONFIG0; /*0X174 */ + __I uint32_t USERCONFIG1; /*0X178 */ + __I uint32_t USERCONFIG2; /*0X17C */ + __I uint32_t USERCONFIG3; /*0X180 */ + __I uint32_t FAB_PROT_SIZE; /*0X184 */ + __I uint32_t FAB_PROT_BASE; /*0X188 */ + __I uint32_t MSS_GPIO_DEF; /*0X18C */ + __IO uint32_t EDAC_SR; /*0X190 */ + __IO uint32_t MSS_INTERNAL_SR; /*0X194 */ + __IO uint32_t MSS_EXTERNAL_SR; /*0X198 */ + __IO uint32_t WDOGTIMEOUTEVENT; /*0X19C */ + __IO uint32_t CLR_MSS_COUNTERS; /*0X1A0 */ + __IO uint32_t CLR_EDAC_COUNTERS; /*0X1A4 */ + __IO uint32_t FLUSH_CR; /*0X1A8 */ + __IO uint32_t MAC_STAT_CLR_CR; /*0X1AC */ + __IO uint32_t IOMUXCELL_CONFIG[57]; /*0X1B0 */ + __I uint32_t NVM_PROTECT_FACTORY; /*0X294 */ + __I uint32_t DEVICE_STATUS_FIXED; /*0X298 */ + __I uint32_t MBIST_ES0; /*0X29C */ + __I uint32_t MBIST_ES1; /*0X2A0 */ + __IO uint32_t MSDDR_PLL_STAUS_1; /*0X2A4 */ + __I uint32_t REDUNDANCY_ESRAM0; /*0X2A8 */ + __I uint32_t REDUNDANCY_ESRAM1; /*0X2AC */ + __I uint32_t SERDESIF; /*0X2B0 */ + +} SYSREG_TypeDef; + +#define SYSREG_ENVM0_SOFTRESET_MASK ( (uint32_t)0x01u << 0u ) +#define SYSREG_ENVM1_SOFTRESET_MASK ( (uint32_t)0x01u << 1u ) +#define SYSREG_ESRAM0_SOFTRESET_MASK ( (uint32_t)0x01u << 2u ) +#define SYSREG_ESRAM1_SOFTRESET_MASK ( (uint32_t)0x01u << 3u ) +#define SYSREG_MAC_SOFTRESET_MASK ( (uint32_t)0x01u << 4u ) +#define SYSREG_PDMA_SOFTRESET_MASK ( (uint32_t)0x01u << 5u ) +#define SYSREG_TIMER_SOFTRESET_MASK ( (uint32_t)0x01u << 6u ) +#define SYSREG_MMUART0_SOFTRESET_MASK ( (uint32_t)0x01u << 7u ) +#define SYSREG_MMUART1_SOFTRESET_MASK ( (uint32_t)0x01u << 8u ) +#define SYSREG_SPI0_SOFTRESET_MASK ( (uint32_t)0x01u << 9u ) +#define SYSREG_SPI1_SOFTRESET_MASK ( (uint32_t)0x01u << 10u ) +#define SYSREG_I2C0_SOFTRESET_MASK ( (uint32_t)0x01u << 11u ) +#define SYSREG_I2C1_SOFTRESET_MASK ( (uint32_t)0x01u << 12u ) +#define SYSREG_CAN_SOFTRESET_MASK ( (uint32_t)0x01u << 13u ) +#define SYSREG_USB_SOFTRESET_MASK ( (uint32_t)0x01u << 14u ) +#define SYSREG_COMBLK_SOFTRESET_MASK ( (uint32_t)0x01u << 15u ) +#define SYSREG_FPGA_SOFTRESET_MASK ( (uint32_t)0x01u << 16u ) +#define SYSREG_HPDMA_SOFTRESET_MASK ( (uint32_t)0x01u << 17u ) +#define SYSREG_FIC32_0_SOFTRESET_MASK ( (uint32_t)0x01u << 18u ) +#define SYSREG_FIC32_1_SOFTRESET_MASK ( (uint32_t)0x01u << 19u ) +#define SYSREG_GPIO_SOFTRESET_MASK ( (uint32_t)0x01u << 20u ) +#define SYSREG_GPIO_7_0_SOFTRESET_MASK ( (uint32_t)0x01u << 21u ) +#define SYSREG_GPIO_15_8_SOFTRESET_MASK ( (uint32_t)0x01u << 22u ) +#define SYSREG_GPIO_23_16_SOFTRESET_MASK ( (uint32_t)0x01u << 23u ) +#define SYSREG_GPIO_31_24_SOFTRESET_MASK ( (uint32_t)0x01u << 24u ) +#define SYSREG_MDDR_SOFTRESET_MASK ( (uint32_t)0x01u << 25u ) +#define SYSREG_FIC64_SOFTRESET_MASK ( (uint32_t)0x01u << 26u ) + +/*----------------------------------------------------------------------------*/ +/*-------------------------- CoreSF2Config Registers -------------------------*/ +/*----------------------------------------------------------------------------*/ +typedef struct { + __IO uint32_t CONFIG_DONE; + __I uint32_t INIT_DONE; + __IO uint32_t CLR_INIT_DONE; + __I uint32_t CONFIG_SR; + __IO uint32_t SOFT_RESET_CR; + __I uint32_t IP_VERSION_SR; +} CoreSF2Config_TypeDef; + +/******************************************************************************/ +/* Peripheral memory map */ +/******************************************************************************/ +#define UART0_BASE 0x40000000u +#define SPI0_BASE 0x40001000u +#define I2C0_BASE 0x40002000u +#define PDMA_BASE 0x40003000u +#define TIMER_BASE 0x40004000u +#define WATCHDOG_BASE 0x40005000u +#define H2F_IRQ_CTRL_BASE 0x40006000u +#define UART1_BASE 0x40010000u +#define SPI1_BASE 0x40011000u +#define I2C1_BASE 0x40012000u +#define GPIO_BASE 0x40013000u +#define HPDMA_BASE 0x40014000u +#define CAN_BASE 0x40015000u +#define COMBLK_BASE 0x40016000u +#define RTC_BASE 0x40017000u +#define DDR0_CFG_BASE 0x40020800u +#define DDR1_CFG_BASE 0x40021000u +#define CORE_SF2_CFG_BASE 0x40022000u +#define SERDES0_CFG_BASE 0x40028000u +#define SERDES1_CFG_BASE 0x4002C000u +#define SERDES2_CFG_BASE 0x40030000u +#define SERDES3_CFG_BASE 0x40034000u +#define SYSREG_BASE 0x40038000u +#define ETHERNET_BASE 0x40041000u +#define USB_BASE 0x40043000u +#define ENVM1_BASE 0x60080000u +#define ENVM2_BASE 0x600C0000u + +/******************************************************************************/ +/* bitband address calculation macro */ +/******************************************************************************/ +#define BITBAND_ADDRESS(X) ((X & 0xF0000000U) + 0x02000000U + ((X & 0xFFFFFU) << 5)) + +/******************************************************************************/ +/* Peripheral declaration */ +/******************************************************************************/ +#define UART0 ((UART_TypeDef *) UART0_BASE) +#define SPI0 ((SPI_TypeDef *) SPI0_BASE) +#define I2C0 ((I2C_TypeDef *) I2C0_BASE) +#define I2C0_BITBAND ((I2C_BitBand_TypeDef *) BITBAND_ADDRESS(I2C0_BASE)) +#define MAC ((MAC_TypeDef *) ETHERNET_BASE) +#define PDMA ((PDMA_TypeDef *) PDMA_BASE) +#define TIMER ((TIMER_TypeDef *) TIMER_BASE) +#define TIMER_BITBAND ((TIMER_BitBand_TypeDef *) BITBAND_ADDRESS(TIMER_BASE)) +#define WATCHDOG ((WATCHDOG_TypeDef *) WATCHDOG_BASE) +#define INTERRUPT_CTRL ((INTERRUPT_CTRL_TypeDef *) H2F_IRQ_CTRL_BASE) +#define INTERRUPT_CTRL_BITBAND ((INTERRUPT_CTRL_BitBand_TypeDef *) BITBAND_ADDRESS(H2F_IRQ_CTRL_BASE)) +#define UART1 ((UART_TypeDef *) UART1_BASE) +#define SPI1 ((SPI_TypeDef *) SPI1_BASE) +#define I2C1 ((I2C_TypeDef *) I2C1_BASE) +#define I2C1_BITBAND ((I2C_BitBand_TypeDef *) BITBAND_ADDRESS(I2C1_BASE)) +#define GPIO ((GPIO_TypeDef *) GPIO_BASE) +#define GPIO_BITBAND ((GPIO_BitBand_TypeDef *) BITBAND_ADDRESS(GPIO_BASE)) +#define HPDMA ((HPDMA_TypeDef *) HPDMA_BASE) +#define HPDMA_BITBAND ((HPDMA_BitBand_TypeDef *) BITBAND_ADDRESS(HPDMA_BASE)) +#define COMBLK ((COMBLK_TypeDef *) COMBLK_BASE) +#define RTC ((RTC_TypeDef *) RTC_BASE) +#define ENVM_1 ((NVM_TypeDef *) ENVM1_BASE) +#define ENVM_2 ((NVM_TypeDef *) ENVM2_BASE) +#define SYSREG ((SYSREG_TypeDef *) SYSREG_BASE) +#define MDDR ((MDDR_TypeDef *) DDR0_CFG_BASE) +#define FDDR ((FDDR_TypeDef *) DDR1_CFG_BASE) +#define USB ((MSS_USB_TypeDef *) USB_BASE) +#define SERDES0 ((SERDESIF_TypeDef *) SERDES0_CFG_BASE) +#define SERDES1 ((SERDESIF_TypeDef *) SERDES1_CFG_BASE) +#define SERDES2 ((SERDESIF_TypeDef *) SERDES2_CFG_BASE) +#define SERDES3 ((SERDESIF_TypeDef *) SERDES3_CFG_BASE) +#define CORE_SF2_CFG ((CoreSF2Config_TypeDef *) CORE_SF2_CFG_BASE) + +#ifdef __cplusplus +} +#endif + +#endif /* __SMARTFUSION2_CMSIS_PAL_H__ */ + diff --git a/bsp/smartfusion2/CMSIS/mss_assert.h b/bsp/smartfusion2/CMSIS/mss_assert.h new file mode 100644 index 0000000000..edec5c1609 --- /dev/null +++ b/bsp/smartfusion2/CMSIS/mss_assert.h @@ -0,0 +1,62 @@ +/******************************************************************************* + * (c) Copyright 2009-2013 Microsemi SoC Products Group. All rights reserved. + * + * Assertion implementation. + * + * This file provides the implementation of the ASSERT macro. This file can be + * modified to cater for project specific requirements regarding the way + * assertions are handled. + * + * SVN $Revision: 6422 $ + * SVN $Date: 2014-05-14 14:37:56 +0100 (Wed, 14 May 2014) $ + */ +#ifndef __MSS_ASSERT_H_ +#define __MSS_ASSERT_H_ + +#if defined(NDEBUG) + +#define ASSERT(CHECK) + +#else /* NDEBUG */ + +#include <assert.h> + +#if defined ( __GNUC__ ) + +/* + * SoftConsole assertion handling + */ +#define ASSERT(CHECK) \ + do { \ + if (!(CHECK)) \ + { \ + __asm volatile ("BKPT\n\t"); \ + } \ + } while (0); + +#elif defined ( __ICCARM__ ) +/* + * IAR Embedded Workbench assertion handling. + * Call C library assert function which should result in error message + * displayed in debugger. + */ +#define ASSERT(X) assert(X) + +#else +/* + * Keil assertion handling. + * Call C library assert function which should result in error message + * displayed in debugger. + */ + +#ifndef __MICROLIB + #define ASSERT(X) assert(X) +#else + #define ASSERT(X) +#endif + +#endif /* Tool Chain */ + +#endif /* NDEBUG */ + +#endif /* __MSS_ASSERT_H_ */ diff --git a/bsp/smartfusion2/CMSIS/startup_arm/low_level_init.c b/bsp/smartfusion2/CMSIS/startup_arm/low_level_init.c new file mode 100644 index 0000000000..e350509927 --- /dev/null +++ b/bsp/smartfusion2/CMSIS/startup_arm/low_level_init.c @@ -0,0 +1,44 @@ +/******************************************************************************* + * (c) Copyright 2014 Microsemi SoC Products Group. All rights reserved. + * + * Keil-MDK specific system initialization. + * + * SVN $Revision: 7375 $ + * SVN $Date: 2015-05-01 14:57:40 +0100 (Fri, 01 May 2015) $ + */ +#ifdef MSCC_NO_RELATIVE_PATHS +#include "m2sxxx.h" +#else +#include "..\m2sxxx.h" +#endif + +#define ENVM_BASE_ADDRESS 0x60000000U +#define MDDR_BASE_ADDRESS 0xA0000000U + +//extern unsigned int Image$$ER_RW$$Base; +//extern unsigned int Image$$ER_RO$$Base; + +/*============================================================================== + * The __low_level_init() function is called after SystemInit. Therefore, the + * external RAM should be configured at this stage if it is used. + */ +/* void low_level_init(void) +{ + volatile unsigned int rw_region_base; + volatile unsigned int readonly_region_base; + + rw_region_base = (unsigned int)&Image$$ER_RW$$Base; + if (rw_region_base >= MDDR_BASE_ADDRESS) + { + / -------------------------------------------------------------------------- + * Remap MDDR to address 0x00000000. + / + SYSREG->ESRAM_CR = 0u; + SYSREG->ENVM_REMAP_BASE_CR = 0u; + SYSREG->DDR_CR = 1u; + } + + readonly_region_base = (unsigned int)&Image$$ER_RO$$Base; + SCB->VTOR = readonly_region_base; +} */ + diff --git a/bsp/smartfusion2/CMSIS/startup_arm/retarget.c b/bsp/smartfusion2/CMSIS/startup_arm/retarget.c new file mode 100644 index 0000000000..229a7c0b80 --- /dev/null +++ b/bsp/smartfusion2/CMSIS/startup_arm/retarget.c @@ -0,0 +1,150 @@ +/******************************************************************************* + * (c) Copyright 2013 Microsemi SoC Products Group. All rights reserved. + * + * Redirection of the standard library I/O to one of the SmartFusion2 + * MMUART. + * + * SVN $Revision: 7375 $ + * SVN $Date: 2015-05-01 14:57:40 +0100 (Fri, 01 May 2015) $ + */ + +/*============================================================================== + * The content of this source file will only be compiled if either one of the + * following two defined symbols are defined in the project settings: + * - MICROSEMI_STDIO_THRU_MMUART0 + * - MICROSEMI_STDIO_THRU_MMUART1 + * + */ +#ifdef MICROSEMI_STDIO_THRU_MMUART0 +#ifndef MICROSEMI_STDIO_THRU_UART +#define MICROSEMI_STDIO_THRU_UART +#endif +#endif /* MICROSEMI_STDIO_THRU_MMUART0 */ + +#ifdef MICROSEMI_STDIO_THRU_MMUART1 +#ifndef MICROSEMI_STDIO_THRU_UART +#define MICROSEMI_STDIO_THRU_UART +#endif +#endif /* MICROSEMI_STDIO_THRU_MMUART1 */ + +/*============================================================================== + * Actual implementation. + */ +#ifdef MICROSEMI_STDIO_THRU_UART + +#include <stdio.h> +#include <rt_misc.h> + +#include "m2sxxx.h" +#include "mss_uart.h" +#include "core_uart_apb.h" + + +/* + * The baud rate will default to 57600 baud if no baud rate is specified though the + * MICROSEMI_STDIO_BAUD_RATE define. + */ +#ifndef MICROSEMI_STDIO_BAUD_RATE +#define MICROSEMI_STDIO_BAUD_RATE MSS_UART_115200_BAUD +#endif + +#ifdef MICROSEMI_STDIO_THRU_MMUART0 +static mss_uart_instance_t * const gp_my_uart = &g_mss_uart0; +#else +static mss_uart_instance_t * const gp_my_uart = &g_mss_uart1; +#endif + +/*============================================================================== + * Flag used to indicate if the UART driver needs to be initialized. + */ +static int g_stdio_uart_init_done = 0; + + +#define LSR_THRE_MASK 0x20u + +/* + * Disable semihosting apis + */ +#pragma import(__use_no_semihosting_swi) + +/*============================================================================== + * sendchar() + */ +int sendchar(int ch) +{ + uint32_t tx_ready; + //��һ�ε���ʱ����ʼ������ + if(!g_stdio_uart_init_done) + { + MSS_UART_init(gp_my_uart, + MICROSEMI_STDIO_BAUD_RATE, + MSS_UART_DATA_8_BITS | MSS_UART_NO_PARITY); + g_stdio_uart_init_done = 1; + } + do { + tx_ready = gp_my_uart->hw_reg->LSR & LSR_THRE_MASK; + } while(!tx_ready); + gp_my_uart->hw_reg->THR = ch; + return (ch); +} + +/*============================================================================== + * + */ +struct __FILE { int handle; /* Add whatever you need here */ }; +FILE __stdout; +FILE __stdin; + + +/*============================================================================== + * fputc() + */ +int fputc(int ch, FILE *f) +{ + return (sendchar(ch)); +} + +/*============================================================================== + * fgetc() + */ +int fgetc(FILE *f) +{ + uint8_t rx_size; + uint8_t rx_byte; + + do { + rx_size = MSS_UART_get_rx(gp_my_uart, &rx_byte, 1); + } while(0u == rx_size); + + return rx_byte; +} + +/*============================================================================== + * ferror() + */ +int ferror(FILE *f) +{ + /* Your implementation of ferror */ + return EOF; +} + +/*============================================================================== + * _ttywrch() + */ +void _ttywrch(int ch) +{ + sendchar(ch); +} + +/*============================================================================== + * _sys_exit() + */ +void _sys_exit(int return_code) +{ + for(;;) + { + ; /* endless loop */ + } +} + +#endif /* MICROSEMI_STDIO_THRU_UART */ diff --git a/bsp/smartfusion2/CMSIS/startup_arm/smartfusion2_esram_debug.sct b/bsp/smartfusion2/CMSIS/startup_arm/smartfusion2_esram_debug.sct new file mode 100644 index 0000000000..3d214ad675 --- /dev/null +++ b/bsp/smartfusion2/CMSIS/startup_arm/smartfusion2_esram_debug.sct @@ -0,0 +1,49 @@ +;*******************************************************************************
+; (c) Copyright 2015 Microsemi SoC Products Group. All rights reserved.
+; SmartFusion2 scatter file for debugging code executing in internal eSRAM.
+;
+; SVN $Revision: 7419 $
+; SVN $Date: 2015-05-15 16:50:21 +0100 (Fri, 15 May 2015) $
+;
+; * Some current (April 2015) dev kit memory map possibilities are
+; * --Type-------Device-----------address start---address end----size---Dbus--RAM IC-------SF2--Comment---------------
+; * --eNVM-------M2S010-----------0x60000000------0x6007FFFF-----256KB---------------------010------------------------
+; * --eNVM-------M2S090-----------0x60000000------0x6007FFFF-----512KB---------------------090------------------------
+; * --eSRAM------M2Sxxx-----------0x20000000------0x2000FFFF-----64KB----------------------xxx--All have same amount--
+; * --eSRAM------M2Sxxx-----------0x20000000------0x20013FFF-----80KB----------------------xxx--If ECC/SECDED not used
+; * --Fabric-----M2S010-----------0x30000000------0x6007FFFF-----400Kb---------------------010--note-K bits-----------
+; * --Fabric-----M2S090-----------0x30000000------0x6007FFFF-----2074Kb--------------------090--note-K bits-----------
+; * --LPDDR------STARTER-KIT------0xA0000000------0xA3FFFFFF-----64MB---16--MT46H32M16-----050------------------------
+; * --LPDDR------484-STARTER-KIT--0xA0000000------0xA3FFFFFF-----64MB---16--MT46H32M16-----010------------------------
+; * --LPDDR------SEC-EVAL-KIT-----0xA0000000------0xA3FFFFFF-----64MB---16--MT46H32M16LF---090--Security eval kit-----
+; * --DDR3-------ADevKit----------0xA0000000------0xBFFFFFFF-----1GB----32--MT41K256M8DA---150------------------------
+; * --Some older physical memory map possibilities are
+; * --Type-------location---------address start---address end----size---Dbus---RAM IC------SF2--Comment--------------
+; * --LPDDR------EVAL KIT---------0xA0000000------0xA3FFFFFF-----64MB-=-16--MT46H32M16LF---025--Eval Kit--------------
+; * --DDR3-------DevKit-----------0xA0000000------0xAFFFFFFF-----512MB--16--MT41K256M8DA---050------------------------
+;
+; Example linker scripts use lowest practicl values so will work accross dev kits
+; eNVM=256KB eRAM=64KB External memory = 64MB
+
+RAM_LOAD 0x20000000 0x10000
+{
+ ; First half of RAM allocated to RO Execute and data
+ ER_RO 0x20000000 0x8000
+ {
+ *.o (RESET, +First)
+ *(InRoot$$Sections)
+ .ANY (+RO)
+ }
+ ; Heap size is defined in startup_m2sxxx.s
+ ; Heap will be added after RW data in ER_RW unless explicitly
+ ; allocated a meemory region in .sct file
+ ; Stack size is defined in startup_m2sxxx.s
+ ; Stack will be added after heap in ER_RW unless explicitly
+ ; allocated a memory region in .sct file
+ ; Second half of RAM allocated to RW data, heap and stack
+ ER_RW 0x20008000 0x8000
+ {
+ .ANY (+RW +ZI)
+ }
+}
+
diff --git a/bsp/smartfusion2/CMSIS/startup_arm/smartfusion2_execute_in_place.sct b/bsp/smartfusion2/CMSIS/startup_arm/smartfusion2_execute_in_place.sct new file mode 100644 index 0000000000..e5663e79b5 --- /dev/null +++ b/bsp/smartfusion2/CMSIS/startup_arm/smartfusion2_execute_in_place.sct @@ -0,0 +1,48 @@ +;*******************************************************************************
+; (c) Copyright 2015 Microsemi SoC Products Group. All rights reserved.
+; SmartFusion2 scatter file for executing code in internal eNVM.
+;
+; SVN $Revision: 7419 $
+; SVN $Date: 2015-05-15 16:50:21 +0100 (Fri, 15 May 2015) $
+;
+; * Some current (April 2015) dev kit memory map possibilities are
+; * --Type-------Device-----------address start---address end----size---Dbus--RAM IC-------SF2--Comment---------------
+; * --eNVM-------M2S010-----------0x60000000------0x6007FFFF-----256KB---------------------010------------------------
+; * --eNVM-------M2S090-----------0x60000000------0x6007FFFF-----512KB---------------------090------------------------
+; * --eSRAM------M2Sxxx-----------0x20000000------0x2000FFFF-----64KB----------------------xxx--All have same amount--
+; * --eSRAM------M2Sxxx-----------0x20000000------0x20013FFF-----80KB----------------------xxx--If ECC/SECDED not used
+; * --Fabric-----M2S010-----------0x30000000------0x6007FFFF-----400Kb---------------------010--note-K bits-----------
+; * --Fabric-----M2S090-----------0x30000000------0x6007FFFF-----2074Kb--------------------090--note-K bits-----------
+; * --LPDDR------STARTER-KIT------0xA0000000------0xA3FFFFFF-----64MB---16--MT46H32M16-----050------------------------
+; * --LPDDR------484-STARTER-KIT--0xA0000000------0xA3FFFFFF-----64MB---16--MT46H32M16-----010------------------------
+; * --LPDDR------SEC-EVAL-KIT-----0xA0000000------0xA3FFFFFF-----64MB---16--MT46H32M16LF---090--Security eval kit-----
+; * --DDR3-------ADevKit----------0xA0000000------0xBFFFFFFF-----1GB----32--MT41K256M8DA---150------------------------
+; * --Some older physical memory map possibilities are
+; * --Type-------location---------address start---address end----size---Dbus---RAM IC------SF2--Comment--------------
+; * --LPDDR------EVAL KIT---------0xA0000000------0xA3FFFFFF-----64MB-=-16--MT46H32M16LF---025--Eval Kit--------------
+; * --DDR3-------DevKit-----------0xA0000000------0xAFFFFFFF-----512MB--16--MT41K256M8DA---050------------------------
+;
+; Example linker scripts use lowest practicl values so will work accross dev kits
+; eNVM=256KB eRAM=64KB External memory = 64MB
+
+FLASH_LOAD 0x00000000 0x40000
+{
+; All R only code/data is located in ENVM
+ ER_RO 0x00000000 0x40000
+ {
+ *.o (RESET, +First)
+ *(InRoot$$Sections)
+ .ANY (+RO)
+ }
+; Heap size is defined in startup_m2sxxx.s
+; Heap will be added after RW data in ER_RW unless explicitly
+; allocated a meemory region in .sct file
+; Stack size is defined in startup_m2sxxx.s
+; Stack will be added after heap in ER_RW unless explicitly
+; allocated a memory region in .sct file
+ ER_RW 0x20000000 0x10000
+ {
+ .ANY (+RW +ZI)
+ }
+}
+
diff --git a/bsp/smartfusion2/CMSIS/startup_arm/smartfusion2_mddr_debug.sct b/bsp/smartfusion2/CMSIS/startup_arm/smartfusion2_mddr_debug.sct new file mode 100644 index 0000000000..b2cb935927 --- /dev/null +++ b/bsp/smartfusion2/CMSIS/startup_arm/smartfusion2_mddr_debug.sct @@ -0,0 +1,54 @@ +;*******************************************************************************
+; (c) Copyright 2015 Microsemi SoC Products Group. All rights reserved.
+; SmartFusion2 scatter file for debugging code executing in external MDDR.
+;
+; SVN $Revision: 7419 $
+; SVN $Date: 2015-05-15 16:50:21 +0100 (Fri, 15 May 2015) $
+;
+; * Some current (April 2015) dev kit memory map possibilities are
+; * --Type-------Device-----------address start---address end----size---Dbus--RAM IC-------SF2--Comment---------------
+; * --eNVM-------M2S010-----------0x60000000------0x6007FFFF-----256KB---------------------010------------------------
+; * --eNVM-------M2S090-----------0x60000000------0x6007FFFF-----512KB---------------------090------------------------
+; * --eSRAM------M2Sxxx-----------0x20000000------0x2000FFFF-----64KB----------------------xxx--All have same amount--
+; * --eSRAM------M2Sxxx-----------0x20000000------0x20013FFF-----80KB----------------------xxx--If ECC/SECDED not used
+; * --Fabric-----M2S010-----------0x30000000------0x6007FFFF-----400Kb---------------------010--note-K bits-----------
+; * --Fabric-----M2S090-----------0x30000000------0x6007FFFF-----2074Kb--------------------090--note-K bits-----------
+; * --LPDDR------STARTER-KIT------0xA0000000------0xA3FFFFFF-----64MB---16--MT46H32M16-----050------------------------
+; * --LPDDR------484-STARTER-KIT--0xA0000000------0xA3FFFFFF-----64MB---16--MT46H32M16-----010------------------------
+; * --LPDDR------SEC-EVAL-KIT-----0xA0000000------0xA3FFFFFF-----64MB---16--MT46H32M16LF---090--Security eval kit-----
+; * --DDR3-------ADevKit----------0xA0000000------0xBFFFFFFF-----1GB----32--MT41K256M8DA---150------------------------
+; * --Some older physical memory map possibilities are
+; * --Type-------location---------address start---address end----size---Dbus---RAM IC------SF2--Comment--------------
+; * --LPDDR------EVAL KIT---------0xA0000000------0xA3FFFFFF-----64MB-=-16--MT46H32M16LF---025--Eval Kit--------------
+; * --DDR3-------DevKit-----------0xA0000000------0xAFFFFFFF-----512MB--16--MT41K256M8DA---050------------------------
+;
+; Example linker scripts use lowest practicl values so will work accross dev kits
+; eNVM=256KB eRAM=64KB External memory = 64MB
+
+; Extern RAM 64M in total
+; allocate 1/2 to progam, 1/2 to variable data
+RAM_LOAD 0x00000000 0x04000000
+{
+; Total = 64MB (lowest common amount accross dev kits) 32MB - First half of external memory allocated to RO Code
+ ER_RO 0x00000000 0x02000000
+ {
+ *.o (RESET, +First)
+ *(InRoot$$Sections)
+ .ANY (+RO)
+ }
+ ; Heap size is defined in startup_m2sxxx.s
+ ; Heap will be added after RW data in ER_RW unless explicitly
+ ; allocated a meemory region in .sct file
+ ; Stack size is defined in startup_m2sxxx.s
+ ; Stack will be added after heap in ER_RW unless explicitly
+ ; allocated a memory region in .sct file as is the case below
+ STACKS 0x20000000 UNINIT
+ {
+ startup_m2sxxx.o (STACK)
+ }
+; 32 MB- Second half of external memory allocated to RW data
+ ER_RW 0xA2000000 0x02000000
+ {
+ .ANY (+RW +ZI)
+ }
+}
diff --git a/bsp/smartfusion2/CMSIS/startup_arm/smartfusion2_relocate_to_external_ram.sct b/bsp/smartfusion2/CMSIS/startup_arm/smartfusion2_relocate_to_external_ram.sct new file mode 100644 index 0000000000..3769a8cda3 --- /dev/null +++ b/bsp/smartfusion2/CMSIS/startup_arm/smartfusion2_relocate_to_external_ram.sct @@ -0,0 +1,74 @@ +;*******************************************************************************
+; (c) Copyright 2015 Microsemi SoC Products Group. All rights reserved.
+; SmartFusion2 scatter file for relocating code to external RAM.
+;
+; SVN $Revision: 7419 $
+; SVN $Date: 2015-05-15 16:50:21 +0100 (Fri, 15 May 2015) $
+;
+; * Some current (April 2015) dev kit memory map possibilities are
+; * --Type-------Device-----------address start---address end----size---Dbus--RAM IC-------SF2--Comment---------------
+; * --eNVM-------M2S010-----------0x60000000------0x6007FFFF-----256KB---------------------010------------------------
+; * --eNVM-------M2S090-----------0x60000000------0x6007FFFF-----512KB---------------------090------------------------
+; * --eSRAM------M2Sxxx-----------0x20000000------0x2000FFFF-----64KB----------------------xxx--All have same amount--
+; * --eSRAM------M2Sxxx-----------0x20000000------0x20013FFF-----80KB----------------------xxx--If ECC/SECDED not used
+; * --Fabric-----M2S010-----------0x30000000------0x6007FFFF-----400Kb---------------------010--note-K bits-----------
+; * --Fabric-----M2S090-----------0x30000000------0x6007FFFF-----2074Kb--------------------090--note-K bits-----------
+; * --LPDDR------STARTER-KIT------0xA0000000------0xA3FFFFFF-----64MB---16--MT46H32M16-----050------------------------
+; * --LPDDR------484-STARTER-KIT--0xA0000000------0xA3FFFFFF-----64MB---16--MT46H32M16-----010------------------------
+; * --LPDDR------SEC-EVAL-KIT-----0xA0000000------0xA3FFFFFF-----64MB---16--MT46H32M16LF---090--Security eval kit-----
+; * --DDR3-------ADevKit----------0xA0000000------0xBFFFFFFF-----1GB----32--MT41K256M8DA---150------------------------
+; * --Some older physical memory map possibilities are
+; * --Type-------location---------address start---address end----size---Dbus---RAM IC------SF2--Comment--------------
+; * --LPDDR------EVAL KIT---------0xA0000000------0xA3FFFFFF-----64MB-=-16--MT46H32M16LF---025--Eval Kit--------------
+; * --DDR3-------DevKit-----------0xA0000000------0xAFFFFFFF-----512MB--16--MT41K256M8DA---050------------------------
+;
+; Example linker scripts use lowest practicl values so will work accross dev kits
+; eNVM=256KB eRAM=64KB External memory = 64MB
+
+FLASH_LOAD 0x60000000 0x40000
+{
+; All code required on start-up located here before relocation has occured
+ ER_RO 0x60000000 0x40000
+ {
+ *.o (RESET, +First)
+ *(InRoot$$Sections)
+ startup_m2sxxx.o
+ system_m2sxxx.o
+ sys_config.o
+ low_level_init.o
+ sys_config_SERDESIF_?.o
+ mscc_post_hw_cfg_init.o
+ ecc_error_handler.o
+ }
+ ; MDDR_RAM 0xA0000000 0x4000000
+ ; -MDDR is mapped to address space from 0 on startup
+ ; This allows the use of cache which is restriced to this area.
+ ; Code is copied to RAM_EXEC space on startup by boot code.
+ RAM_EXEC 0x00000000 0x00040000
+ {
+ .ANY (+RO)
+ }
+ ; Heap size is defined in startup_m2sxxx.s
+ ; Heap will be added after RW data in ER_RW unless explicitly
+ ; allocated a meemory region in .sct file
+ ; Stack size is defined in startup_m2sxxx.s
+ ; Stack will be added after heap in ER_RW unless explicitly
+ ; allocated a memory region in .sct file as is the case below
+ STACKS 0x20000000 UNINIT
+ {
+ startup_m2sxxx.o (STACK)
+ }
+; All internal RAM has been allocatd to the stack
+; INTERNAL_RAM 0x20008000 0x10000
+; {
+; .ANY (+RW +ZI)
+; }
+
+; MDDR_RAM 0xA0000000 0x4000000 So use top half of this for RW data
+; Bottom half has been assigned to R only code already
+ ER_RW 0xA2000000 0x2000000
+ {
+ .ANY (+RW +ZI)
+ }
+}
+
diff --git a/bsp/smartfusion2/CMSIS/startup_arm/startup_m2sxxx.s b/bsp/smartfusion2/CMSIS/startup_arm/startup_m2sxxx.s new file mode 100644 index 0000000000..5419b25cf8 --- /dev/null +++ b/bsp/smartfusion2/CMSIS/startup_arm/startup_m2sxxx.s @@ -0,0 +1,586 @@ +;******************************************************************************* +; (c) Copyright 2015 Microsemi SoC Products Group. All rights reserved. +; SmartFusion2 startup code for Keil-MDK. +; +; SmartFusion2 vector table and startup code for ARM tool chain. +; +; SVN $Revision: 7419 $ +; SVN $Date: 2015-05-15 16:50:21 +0100 (Fri, 15 May 2015) $ +; + +; *------- <<< Use Configuration Wizard in Context Menu >>> ------------------ + + +; <h> Stack Configuration +; <o> Stack Size (in Bytes) <0x0-0xFFFFFFFF:8> +; </h> + +Stack_Size EQU 0x00001000 + + AREA STACK, NOINIT, READWRITE, ALIGN=3 +stack_start +Stack_Mem SPACE Stack_Size +__initial_sp +stack_end + + +; <h> Heap Configuration +; <o> Heap Size (in Bytes) <0x0-0xFFFFFFFF:8> +; </h> + +Heap_Size EQU 0x00000200 + + AREA HEAP, NOINIT, READWRITE, ALIGN=3 +__heap_base +Heap_Mem SPACE Heap_Size +__heap_limit + + + PRESERVE8 + THUMB + + +;=============================================================================== +; Vector Table Mapped to Address 0 at Reset + AREA RESET, DATA, READONLY + EXPORT __Vectors + EXPORT __Vectors_End + EXPORT __Vectors_Size + +__Vectors DCD __initial_sp ; Top of Stack + DCD Reset_Handler ; Reset Handler + DCD NMI_Handler ; NMI Handler + DCD HardFault_Handler ; Hard Fault Handler + DCD MemManage_Handler ; MPU Fault Handler + DCD BusFault_Handler ; Bus Fault Handler + DCD UsageFault_Handler ; Usage Fault Handler + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD SVC_Handler ; SVCall Handler + DCD DebugMon_Handler ; Debug Monitor Handler + DCD 0 ; Reserved + DCD PendSV_Handler ; PendSV Handler + DCD SysTick_Handler ; SysTick Handler + + ; External Interrupts + DCD WdogWakeup_IRQHandler + DCD RTC_Wakeup_IRQHandler + DCD SPI0_IRQHandler + DCD SPI1_IRQHandler + DCD I2C0_IRQHandler + DCD I2C0_SMBAlert_IRQHandler + DCD I2C0_SMBus_IRQHandler + DCD I2C1_IRQHandler + DCD I2C1_SMBAlert_IRQHandler + DCD I2C1_SMBus_IRQHandler + DCD UART0_IRQHandler + DCD UART1_IRQHandler + DCD EthernetMAC_IRQHandler + DCD DMA_IRQHandler + DCD Timer1_IRQHandler + DCD Timer2_IRQHandler + DCD CAN_IRQHandler + DCD ENVM0_IRQHandler + DCD ENVM1_IRQHandler + DCD ComBlk_IRQHandler + DCD USB_IRQHandler + DCD USB_DMA_IRQHandler + DCD PLL_Lock_IRQHandler + DCD PLL_LockLost_IRQHandler + DCD CommSwitchError_IRQHandler + DCD CacheError_IRQHandler + DCD DDR_IRQHandler + DCD HPDMA_Complete_IRQHandler + DCD HPDMA_Error_IRQHandler + DCD ECC_Error_IRQHandler + DCD MDDR_IOCalib_IRQHandler + DCD FAB_PLL_Lock_IRQHandler + DCD FAB_PLL_LockLost_IRQHandler + DCD FIC64_IRQHandler + DCD FabricIrq0_IRQHandler + DCD FabricIrq1_IRQHandler + DCD FabricIrq2_IRQHandler + DCD FabricIrq3_IRQHandler + DCD FabricIrq4_IRQHandler + DCD FabricIrq5_IRQHandler + DCD FabricIrq6_IRQHandler + DCD FabricIrq7_IRQHandler + DCD FabricIrq8_IRQHandler + DCD FabricIrq9_IRQHandler + DCD FabricIrq10_IRQHandler + DCD FabricIrq11_IRQHandler + DCD FabricIrq12_IRQHandler + DCD FabricIrq13_IRQHandler + DCD FabricIrq14_IRQHandler + DCD FabricIrq15_IRQHandler + DCD GPIO0_IRQHandler + DCD GPIO1_IRQHandler + DCD GPIO2_IRQHandler + DCD GPIO3_IRQHandler + DCD GPIO4_IRQHandler + DCD GPIO5_IRQHandler + DCD GPIO6_IRQHandler + DCD GPIO7_IRQHandler + DCD GPIO8_IRQHandler + DCD GPIO9_IRQHandler + DCD GPIO10_IRQHandler + DCD GPIO11_IRQHandler + DCD GPIO12_IRQHandler + DCD GPIO13_IRQHandler + DCD GPIO14_IRQHandler + DCD GPIO15_IRQHandler + DCD GPIO16_IRQHandler + DCD GPIO17_IRQHandler + DCD GPIO18_IRQHandler + DCD GPIO19_IRQHandler + DCD GPIO20_IRQHandler + DCD GPIO21_IRQHandler + DCD GPIO22_IRQHandler + DCD GPIO23_IRQHandler + DCD GPIO24_IRQHandler + DCD GPIO25_IRQHandler + DCD GPIO26_IRQHandler + DCD GPIO27_IRQHandler + DCD GPIO28_IRQHandler + DCD GPIO29_IRQHandler + DCD GPIO30_IRQHandler + DCD GPIO31_IRQHandler + +__Vectors_End + +__Vectors_Size EQU __Vectors_End - __Vectors + +;=============================================================================== +; Reset Handler +; + AREA |.text|, CODE, READONLY + +Reset_Handler PROC + EXPORT Reset_Handler [WEAK] + IMPORT SystemInit + ; IMPORT low_level_init + IMPORT __main + + ;--------------------------------------------------------------- + ; Initialize stack RAM content to initialize the error detection + ; and correction (EDAC). This is done if EDAC is enabled for the + ; eSRAM blocks or the ECC/SECDED is enabled for the MDDR. + ; Register R11 is used to keep track of the RAM intialization + ; decision outcome for later use for heap RAM initialization at + ; the end of the startup code. + ; Please note that the stack has to be located in eSRAM at this + ; point and cannot be located in MDDR since MDDR is not available + ; at this point. + ; The bits of the content of register R11 have the foolwing + ; meaning: + ; reg11[0]: eSRAM EDAC enabled + ; reg11[1]: MDDR ECC/SECDED enabled + ; + MOV R11, #0 + LDR R0, SF2_MDDR_MODE_CR + LDR R0, [R0] + LDR R1, SF2_EDAC_CR + LDR R1, [R1] + AND R1, R1, #3 + AND R0, R0, #0x1C + CMP R0, #0x14 + BNE check_esram_edac + ORR R11, R11, #2 +check_esram_edac + CMP R1, #0 + BEQ check_stack_init + ORR R11, R11, #1 +check_stack_init + CMP R11, #0 + BEQ call_system_init +clear_stack + LDR R0, =stack_start + LDR R1, =stack_end + LDR R2, RAM_INIT_PATTERN + BL fill_memory ; fill_memory takes r0 - r2 as arguments uses r4, r5, r6, r7, r8, r9, and does not preserve contents */ + + ;--------------------------------------------------------------- + ; Call SystemInit() to perform Libero specified configuration. + ; +call_system_init + LDR R0, =SystemInit + BLX R0 + ; LDR R0, =low_level_init + ; BLX R0 + + ;--------------------------------------------------------------- + ; Modify MDDR configuration if ECC/SECDED is enabled for MDDR. + ; Enable write combining on MDDR bridge, disable non-bufferable + ; regions. + ; +adjust_mddr_cfg + AND R10, R11, #0x2 + CMP R10, #0 + BEQ branch_to_main + LDR R0, SF2_DDRB_NB_SIZE + LDR R1, SF2_DDRB_CR + LDR R2, [R0] + LDR R3, [R1] + push {R0, R1, R2, R3} + MOV R2, #0 + MOV R3, #0xFF + STR R2, [R0] + STR R3, [R1] + + ; -------------------------------------------------------------- + ; Initialize heap RAM content to initialize the error detection + ; and correction (EDAC). We use the decision made earlier in the + ; startup code of whether or not the stack RAM should be + ; initialized. This decision is held in register R11. A non-zero + ; value indicates that the RAM content should be initialized. + ; +clear_heap + CMP R11, #0 + BEQ branch_to_main + LDR R0, =__heap_base + LDR R1, =__heap_limit + LDR R2, HEAP_INIT_PATTERN + BL fill_memory ; fill_memory takes r0 - r2 as arguments uses r4, r5, r6, r7, r8, r9, and does not preserve contents */ + + ;--------------------------------------------------------------- + ; Branch to __main + ; +branch_to_main + LDR R0, =__main + BX R0 + ENDP + +SF2_EDAC_CR DCD 0x40038038 +SF2_DDRB_NB_SIZE DCD 0x40038030 +SF2_DDRB_CR DCD 0x40038034 +SF2_MDDR_MODE_CR DCD 0x40020818 +RAM_INIT_PATTERN DCD 0x00000000 +HEAP_INIT_PATTERN DCD 0x00000000 + +;------------------------------------------------------------------------------ +; * fill_memory. +; * @brief Fills memory with Pattern contained in r2 +; * This routine uses the stmne instruction to copy 4 words at a time which is very efficient +; * The instruction can only write to word aligned memory, hence the code at the start and end of this routine +; * to handle possible unaligned bytes at start and end. +; * +; * @param param1 r0: start address +; * @param param2 r1: end address +; * @param param3 r2: FILL PATTETN +; * +; * @note note: Most efficient if memory aligned. Linker ALIGN(4) command +; * should be used as per example linker scripts +; * Stack is not used in this routine +; * register contents r4, r5, r6, r7, r8, r9, will are used and will be returned undefined +; * @return none - Used Registers are not preserved +; */ + +fill_memory PROC + ;push {r4, r5, r6, r7, r8, r9, lr} We will not use stack as may be not available */ + cmp r0, r1 + beq fill_memory_exit ; Exit early if source and destination the same */ + ; copy non-aligned bytes at the start */ + and.w r6, r0, #3 ; see if non-alaigned bytes at the start */ + cmp r6, #0 + beq fill_memory_end_start ; no spare bytes at start, continue */ + mov r5, #4 + sub.w r4, r5, r6 ; now have number of non-aligned bytes in r4 */ + mov r7, #8 + mul r8, r7, r6 ; calculate number of shifts required to initalise pattern for non-aligned bytes */ + mov r9, r2 ; copy pattern */ + ror r9, r9, r8 ; Rotate right to keep pattern consistent */ +fill_memory_spare_bytes_start ; From above, R0 contains source address, R1 contains destination address */ + cmp r4, #0 ; no spare bytes at end- end now */ + beq fill_memory_end_start + strb r9, [r0] ; fill byte */ + ror.w r9, r9, r7 ; Rotate right by one byte for the next time, to keep pattern consistent */ + add r0, r0, #1 ; add one to address */ + subs r4, r4, #1 ; subtract one from byte count 1 */ + b fill_memory_spare_bytes_start +fill_memory_end_start + mov r6, #0 + mov r7, r1 ; save end address */ + subs r1, r1, r0 ; Calculate number of bytes to fill */ + mov r8,r1 ; Save copy of byte count */ + asrs r1,r1, #4 ; Div by 16 to get number of chunks to move */ + mov r9, r2 ; copy pattern */ + mov r4, r2 ; copy pattern */ + mov r5, r2 ; copy pattern */ + cmp r1, r6 ; compare to see if all chunks copied */ + beq fill_memory_spare_bytes_end +fill_memory_loop + it ne + stmne r0!, {r2, r4, r5, r9} ; copy pattern- note: stmne instruction must me word aligned (address in r0) */ + add.w r6, r6, #1 ; use Thumb2- make sure condition code reg. not updated */ + cmp r1, r6 ; compare to see if all chunks copied */ + bne fill_memory_loop +fill_memory_spare_bytes_end ; copy spare bytes at the end if any */ + and.w r8, r8, #15 ; get spare bytes --check can you do an ands? */ +fill_memory_spare_end_loop ; From above, R0 contains source address, R1 contains destination address */ + cmp r8, #0 ; no spare bytes at end- end now */ + beq fill_memory_exit + strb r2, [r0] + ror.w r2, r2, #8 ; Rotate right by one byte for the next time, to keep pattern consistent */ + add r0, r0, #1 ; add one to address */ + subs r8, r8, #1 ; subtract one from byte count 1 */ + b fill_memory_spare_end_loop +fill_memory_exit + bx lr ; We will not use pop as stack may be not available */ + ENDP + + + +;=============================================================================== +; Dummy Exception Handlers (infinite loops which can be modified) + +NMI_Handler PROC + EXPORT NMI_Handler [WEAK] + B . + ENDP +HardFault_Handler\ + PROC + EXPORT HardFault_Handler [WEAK] + B . + ENDP +MemManage_Handler\ + PROC + EXPORT MemManage_Handler [WEAK] + B . + ENDP +BusFault_Handler\ + PROC + EXPORT BusFault_Handler [WEAK] + B . + ENDP +UsageFault_Handler\ + PROC + EXPORT UsageFault_Handler [WEAK] + B . + ENDP +SVC_Handler PROC + EXPORT SVC_Handler [WEAK] + B . + ENDP +DebugMon_Handler\ + PROC + EXPORT DebugMon_Handler [WEAK] + B . + ENDP +PendSV_Handler PROC + EXPORT PendSV_Handler [WEAK] + B . + ENDP +SysTick_Handler PROC + EXPORT SysTick_Handler [WEAK] + B . + ENDP + +Default_Handler PROC + + EXPORT WdogWakeup_IRQHandler [WEAK] + EXPORT RTC_Wakeup_IRQHandler [WEAK] + EXPORT SPI0_IRQHandler [WEAK] + EXPORT SPI1_IRQHandler [WEAK] + EXPORT I2C0_IRQHandler [WEAK] + EXPORT I2C0_SMBAlert_IRQHandler [WEAK] + EXPORT I2C0_SMBus_IRQHandler [WEAK] + EXPORT I2C1_IRQHandler [WEAK] + EXPORT I2C1_SMBAlert_IRQHandler [WEAK] + EXPORT I2C1_SMBus_IRQHandler [WEAK] + EXPORT UART0_IRQHandler [WEAK] + EXPORT UART1_IRQHandler [WEAK] + EXPORT EthernetMAC_IRQHandler [WEAK] + EXPORT DMA_IRQHandler [WEAK] + EXPORT Timer1_IRQHandler [WEAK] + EXPORT Timer2_IRQHandler [WEAK] + EXPORT CAN_IRQHandler [WEAK] + EXPORT ENVM0_IRQHandler [WEAK] + EXPORT ENVM1_IRQHandler [WEAK] + EXPORT ComBlk_IRQHandler [WEAK] + EXPORT USB_IRQHandler [WEAK] + EXPORT USB_DMA_IRQHandler [WEAK] + EXPORT PLL_Lock_IRQHandler [WEAK] + EXPORT PLL_LockLost_IRQHandler [WEAK] + EXPORT CommSwitchError_IRQHandler [WEAK] + EXPORT CacheError_IRQHandler [WEAK] + EXPORT DDR_IRQHandler [WEAK] + EXPORT HPDMA_Complete_IRQHandler [WEAK] + EXPORT HPDMA_Error_IRQHandler [WEAK] + EXPORT ECC_Error_IRQHandler [WEAK] + EXPORT MDDR_IOCalib_IRQHandler [WEAK] + EXPORT FAB_PLL_Lock_IRQHandler [WEAK] + EXPORT FAB_PLL_LockLost_IRQHandler [WEAK] + EXPORT FIC64_IRQHandler [WEAK] + EXPORT FabricIrq0_IRQHandler [WEAK] + EXPORT FabricIrq1_IRQHandler [WEAK] + EXPORT FabricIrq2_IRQHandler [WEAK] + EXPORT FabricIrq3_IRQHandler [WEAK] + EXPORT FabricIrq4_IRQHandler [WEAK] + EXPORT FabricIrq5_IRQHandler [WEAK] + EXPORT FabricIrq6_IRQHandler [WEAK] + EXPORT FabricIrq7_IRQHandler [WEAK] + EXPORT FabricIrq8_IRQHandler [WEAK] + EXPORT FabricIrq9_IRQHandler [WEAK] + EXPORT FabricIrq10_IRQHandler [WEAK] + EXPORT FabricIrq11_IRQHandler [WEAK] + EXPORT FabricIrq12_IRQHandler [WEAK] + EXPORT FabricIrq13_IRQHandler [WEAK] + EXPORT FabricIrq14_IRQHandler [WEAK] + EXPORT FabricIrq15_IRQHandler [WEAK] + EXPORT GPIO0_IRQHandler [WEAK] + EXPORT GPIO1_IRQHandler [WEAK] + EXPORT GPIO2_IRQHandler [WEAK] + EXPORT GPIO3_IRQHandler [WEAK] + EXPORT GPIO4_IRQHandler [WEAK] + EXPORT GPIO5_IRQHandler [WEAK] + EXPORT GPIO6_IRQHandler [WEAK] + EXPORT GPIO7_IRQHandler [WEAK] + EXPORT GPIO8_IRQHandler [WEAK] + EXPORT GPIO9_IRQHandler [WEAK] + EXPORT GPIO10_IRQHandler [WEAK] + EXPORT GPIO11_IRQHandler [WEAK] + EXPORT GPIO12_IRQHandler [WEAK] + EXPORT GPIO13_IRQHandler [WEAK] + EXPORT GPIO14_IRQHandler [WEAK] + EXPORT GPIO15_IRQHandler [WEAK] + EXPORT GPIO16_IRQHandler [WEAK] + EXPORT GPIO17_IRQHandler [WEAK] + EXPORT GPIO18_IRQHandler [WEAK] + EXPORT GPIO19_IRQHandler [WEAK] + EXPORT GPIO20_IRQHandler [WEAK] + EXPORT GPIO21_IRQHandler [WEAK] + EXPORT GPIO22_IRQHandler [WEAK] + EXPORT GPIO23_IRQHandler [WEAK] + EXPORT GPIO24_IRQHandler [WEAK] + EXPORT GPIO25_IRQHandler [WEAK] + EXPORT GPIO26_IRQHandler [WEAK] + EXPORT GPIO27_IRQHandler [WEAK] + EXPORT GPIO28_IRQHandler [WEAK] + EXPORT GPIO29_IRQHandler [WEAK] + EXPORT GPIO30_IRQHandler [WEAK] + EXPORT GPIO31_IRQHandler [WEAK] + + +WdogWakeup_IRQHandler +RTC_Wakeup_IRQHandler +SPI0_IRQHandler +SPI1_IRQHandler +I2C0_IRQHandler +I2C0_SMBAlert_IRQHandler +I2C0_SMBus_IRQHandler +I2C1_IRQHandler +I2C1_SMBAlert_IRQHandler +I2C1_SMBus_IRQHandler +UART0_IRQHandler +UART1_IRQHandler +EthernetMAC_IRQHandler +DMA_IRQHandler +Timer1_IRQHandler +Timer2_IRQHandler +CAN_IRQHandler +ENVM0_IRQHandler +ENVM1_IRQHandler +ComBlk_IRQHandler +USB_IRQHandler +USB_DMA_IRQHandler +PLL_Lock_IRQHandler +PLL_LockLost_IRQHandler +CommSwitchError_IRQHandler +CacheError_IRQHandler +DDR_IRQHandler +HPDMA_Complete_IRQHandler +HPDMA_Error_IRQHandler +ECC_Error_IRQHandler +MDDR_IOCalib_IRQHandler +FAB_PLL_Lock_IRQHandler +FAB_PLL_LockLost_IRQHandler +FIC64_IRQHandler +FabricIrq0_IRQHandler +FabricIrq1_IRQHandler +FabricIrq2_IRQHandler +FabricIrq3_IRQHandler +FabricIrq4_IRQHandler +FabricIrq5_IRQHandler +FabricIrq6_IRQHandler +FabricIrq7_IRQHandler +FabricIrq8_IRQHandler +FabricIrq9_IRQHandler +FabricIrq10_IRQHandler +FabricIrq11_IRQHandler +FabricIrq12_IRQHandler +FabricIrq13_IRQHandler +FabricIrq14_IRQHandler +FabricIrq15_IRQHandler +GPIO0_IRQHandler +GPIO1_IRQHandler +GPIO2_IRQHandler +GPIO3_IRQHandler +GPIO4_IRQHandler +GPIO5_IRQHandler +GPIO6_IRQHandler +GPIO7_IRQHandler +GPIO8_IRQHandler +GPIO9_IRQHandler +GPIO10_IRQHandler +GPIO11_IRQHandler +GPIO12_IRQHandler +GPIO13_IRQHandler +GPIO14_IRQHandler +GPIO15_IRQHandler +GPIO16_IRQHandler +GPIO17_IRQHandler +GPIO18_IRQHandler +GPIO19_IRQHandler +GPIO20_IRQHandler +GPIO21_IRQHandler +GPIO22_IRQHandler +GPIO23_IRQHandler +GPIO24_IRQHandler +GPIO25_IRQHandler +GPIO26_IRQHandler +GPIO27_IRQHandler +GPIO28_IRQHandler +GPIO29_IRQHandler +GPIO30_IRQHandler +GPIO31_IRQHandler + B . + + ENDP + +mscc_post_hw_cfg_init PROC + EXPORT mscc_post_hw_cfg_init [WEAK] + BX LR + ENDP + + ALIGN + + +;=============================================================================== +; User Initial Stack & Heap + + IF :DEF:__MICROLIB + + EXPORT __initial_sp + EXPORT __heap_base + EXPORT __heap_limit + + ELSE + + IMPORT __use_two_region_memory + EXPORT __user_initial_stackheap +__user_initial_stackheap + + LDR R0, = Heap_Mem + LDR R1, =(Stack_Mem + Stack_Size) + LDR R2, = (Heap_Mem + Heap_Size) + LDR R3, = Stack_Mem + BX LR + + ALIGN + + ENDIF + + + END diff --git a/bsp/smartfusion2/CMSIS/sys_init_cfg_types.h b/bsp/smartfusion2/CMSIS/sys_init_cfg_types.h new file mode 100644 index 0000000000..38ed4ebe23 --- /dev/null +++ b/bsp/smartfusion2/CMSIS/sys_init_cfg_types.h @@ -0,0 +1,212 @@ +/******************************************************************************* + * (c) Copyright 2012 Microsemi SoC Products Group. All rights reserved. + * + * + * + * SVN $Revision: 4410 $ + * SVN $Date: 2012-07-16 14:36:17 +0100 (Mon, 16 Jul 2012) $ + */ + +#ifndef SYSTEM_INIT_CFG_TYPES_H_ +#define SYSTEM_INIT_CFG_TYPES_H_ + +#ifdef __cplusplus +extern "C" { +#endif + +/*============================================================================*/ +/* DDR Configuration */ +/*============================================================================*/ +typedef struct +{ + /*-------------------------------------------------------------------------- + * DDR Controller registers. + */ + struct + { + uint16_t DYN_SOFT_RESET_CR; + uint16_t RESERVED0; + uint16_t DYN_REFRESH_1_CR; + uint16_t DYN_REFRESH_2_CR; + uint16_t DYN_POWERDOWN_CR; + uint16_t DYN_DEBUG_CR; + uint16_t MODE_CR; + uint16_t ADDR_MAP_BANK_CR; + uint16_t ECC_DATA_MASK_CR; + uint16_t ADDR_MAP_COL_1_CR; + uint16_t ADDR_MAP_COL_2_CR; + uint16_t ADDR_MAP_ROW_1_CR; + uint16_t ADDR_MAP_ROW_2_CR; + uint16_t INIT_1_CR; + uint16_t CKE_RSTN_CYCLES_1_CR; + uint16_t CKE_RSTN_CYCLES_2_CR; + uint16_t INIT_MR_CR; + uint16_t INIT_EMR_CR; + uint16_t INIT_EMR2_CR; + uint16_t INIT_EMR3_CR; + uint16_t DRAM_BANK_TIMING_PARAM_CR; + uint16_t DRAM_RD_WR_LATENCY_CR; + uint16_t DRAM_RD_WR_PRE_CR; + uint16_t DRAM_MR_TIMING_PARAM_CR; + uint16_t DRAM_RAS_TIMING_CR; + uint16_t DRAM_RD_WR_TRNARND_TIME_CR; + uint16_t DRAM_T_PD_CR; + uint16_t DRAM_BANK_ACT_TIMING_CR; + uint16_t ODT_PARAM_1_CR; + uint16_t ODT_PARAM_2_CR; + uint16_t ADDR_MAP_COL_3_CR; + uint16_t MODE_REG_RD_WR_CR; + uint16_t MODE_REG_DATA_CR; + uint16_t PWR_SAVE_1_CR; + uint16_t PWR_SAVE_2_CR; + uint16_t ZQ_LONG_TIME_CR; + uint16_t ZQ_SHORT_TIME_CR; + uint16_t ZQ_SHORT_INT_REFRESH_MARGIN_1_CR; + uint16_t ZQ_SHORT_INT_REFRESH_MARGIN_2_CR; + uint16_t PERF_PARAM_1_CR; + uint16_t HPR_QUEUE_PARAM_1_CR; + uint16_t HPR_QUEUE_PARAM_2_CR; + uint16_t LPR_QUEUE_PARAM_1_CR; + uint16_t LPR_QUEUE_PARAM_2_CR; + uint16_t WR_QUEUE_PARAM_CR; + uint16_t PERF_PARAM_2_CR; + uint16_t PERF_PARAM_3_CR; + uint16_t DFI_RDDATA_EN_CR; + uint16_t DFI_MIN_CTRLUPD_TIMING_CR; + uint16_t DFI_MAX_CTRLUPD_TIMING_CR; + uint16_t DFI_WR_LVL_CONTROL_1_CR; + uint16_t DFI_WR_LVL_CONTROL_2_CR; + uint16_t DFI_RD_LVL_CONTROL_1_CR; + uint16_t DFI_RD_LVL_CONTROL_2_CR; + uint16_t DFI_CTRLUPD_TIME_INTERVAL_CR; + uint16_t DYN_SOFT_RESET_CR2; + uint16_t AXI_FABRIC_PRI_ID_CR; + } ddrc; + + /*-------------------------------------------------------------------------- + * DDR PHY configuration registers + */ + struct + { + uint16_t LOOPBACK_TEST_CR; + uint16_t BOARD_LOOPBACK_CR; + uint16_t CTRL_SLAVE_RATIO_CR; + uint16_t CTRL_SLAVE_FORCE_CR; + uint16_t CTRL_SLAVE_DELAY_CR; + uint16_t DATA_SLICE_IN_USE_CR; + uint16_t LVL_NUM_OF_DQ0_CR; + uint16_t DQ_OFFSET_1_CR; + uint16_t DQ_OFFSET_2_CR; + uint16_t DQ_OFFSET_3_CR; + uint16_t DIS_CALIB_RST_CR; + uint16_t DLL_LOCK_DIFF_CR; + uint16_t FIFO_WE_IN_DELAY_1_CR; + uint16_t FIFO_WE_IN_DELAY_2_CR; + uint16_t FIFO_WE_IN_DELAY_3_CR; + uint16_t FIFO_WE_IN_FORCE_CR; + uint16_t FIFO_WE_SLAVE_RATIO_1_CR; + uint16_t FIFO_WE_SLAVE_RATIO_2_CR; + uint16_t FIFO_WE_SLAVE_RATIO_3_CR; + uint16_t FIFO_WE_SLAVE_RATIO_4_CR; + uint16_t GATELVL_INIT_MODE_CR; + uint16_t GATELVL_INIT_RATIO_1_CR; + uint16_t GATELVL_INIT_RATIO_2_CR; + uint16_t GATELVL_INIT_RATIO_3_CR; + uint16_t GATELVL_INIT_RATIO_4_CR; + uint16_t LOCAL_ODT_CR; + uint16_t INVERT_CLKOUT_CR; + uint16_t RD_DQS_SLAVE_DELAY_1_CR; + uint16_t RD_DQS_SLAVE_DELAY_2_CR; + uint16_t RD_DQS_SLAVE_DELAY_3_CR; + uint16_t RD_DQS_SLAVE_FORCE_CR; + uint16_t RD_DQS_SLAVE_RATIO_1_CR; + uint16_t RD_DQS_SLAVE_RATIO_2_CR; + uint16_t RD_DQS_SLAVE_RATIO_3_CR; + uint16_t RD_DQS_SLAVE_RATIO_4_CR; + uint16_t WR_DQS_SLAVE_DELAY_1_CR; + uint16_t WR_DQS_SLAVE_DELAY_2_CR; + uint16_t WR_DQS_SLAVE_DELAY_3_CR; + uint16_t WR_DQS_SLAVE_FORCE_CR; + uint16_t WR_DQS_SLAVE_RATIO_1_CR; + uint16_t WR_DQS_SLAVE_RATIO_2_CR; + uint16_t WR_DQS_SLAVE_RATIO_3_CR; + uint16_t WR_DQS_SLAVE_RATIO_4_CR; + uint16_t WR_DATA_SLAVE_DELAY_1_CR; + uint16_t WR_DATA_SLAVE_DELAY_2_CR; + uint16_t WR_DATA_SLAVE_DELAY_3_CR; + uint16_t WR_DATA_SLAVE_FORCE_CR; + uint16_t WR_DATA_SLAVE_RATIO_1_CR; + uint16_t WR_DATA_SLAVE_RATIO_2_CR; + uint16_t WR_DATA_SLAVE_RATIO_3_CR; + uint16_t WR_DATA_SLAVE_RATIO_4_CR; + uint16_t WRLVL_INIT_MODE_CR; + uint16_t WRLVL_INIT_RATIO_1_CR; + uint16_t WRLVL_INIT_RATIO_2_CR; + uint16_t WRLVL_INIT_RATIO_3_CR; + uint16_t WRLVL_INIT_RATIO_4_CR; + uint16_t WR_RD_RL_CR; + uint16_t RDC_FIFO_RST_ERRCNTCLR_CR; + uint16_t RDC_WE_TO_RE_DELAY_CR; + uint16_t USE_FIXED_RE_CR; + uint16_t USE_RANK0_DELAYS_CR; + uint16_t USE_LVL_TRNG_LEVEL_CR; + uint16_t CONFIG_CR; + uint16_t RD_WR_GATE_LVL_CR; + uint16_t DYN_RESET_CR; + } phy; + + /*-------------------------------------------------------------------------- + * FIC-64 registers + * These registers are 16-bit wide and 32-bit aligned. + */ + struct + { + uint16_t NB_ADDR_CR; + uint16_t NBRWB_SIZE_CR; + uint16_t WB_TIMEOUT_CR; + uint16_t HPD_SW_RW_EN_CR; + uint16_t HPD_SW_RW_INVAL_CR; + uint16_t SW_WR_ERCLR_CR; + uint16_t ERR_INT_ENABLE_CR; + uint16_t NUM_AHB_MASTERS_CR; + uint16_t LOCK_TIMEOUTVAL_1_CR; + uint16_t LOCK_TIMEOUTVAL_2_CR; + uint16_t LOCK_TIMEOUT_EN_CR; + } fic; +} ddr_subsys_cfg_t; + +/*============================================================================*/ +/* FDDR Configuration */ +/*============================================================================*/ + +typedef struct +{ + uint16_t PLL_CONFIG_LOW_1; + uint16_t PLL_CONFIG_LOW_2; + uint16_t PLL_CONFIG_HIGH; + uint16_t FACC_CLK_EN; + uint16_t FACC_MUX_CONFIG; + uint16_t FACC_DIVISOR_RATIO; + uint16_t PLL_DELAY_LINE_SEL; + uint16_t SOFT_RESET; + uint16_t IO_CALIB; + uint16_t INTERRUPT_ENABLE; + uint16_t AXI_AHB_MODE_SEL; + uint16_t PHY_SELF_REF_EN; +} fddr_sysreg_t; + +/*============================================================================*/ +/* PCI Express Bridge IP Core configuration. */ +/*============================================================================*/ + +typedef struct +{ + uint32_t * p_reg; + uint32_t value; +} cfg_addr_value_pair_t; + +#ifdef __cplusplus +} +#endif + +#endif /* SYSTEM_INIT_CFG_TYPES_H_ */ diff --git a/bsp/smartfusion2/CMSIS/system_m2sxxx.c b/bsp/smartfusion2/CMSIS/system_m2sxxx.c new file mode 100644 index 0000000000..13a90af770 --- /dev/null +++ b/bsp/smartfusion2/CMSIS/system_m2sxxx.c @@ -0,0 +1,1005 @@ +/******************************************************************************* + * (c) Copyright 2012-2013 Microsemi SoC Products Group. All rights reserved. + * + * SmartFusion2 CMSIS system initialization. + * + * SVN $Revision: 7375 $ + * SVN $Date: 2015-05-01 14:57:40 +0100 (Fri, 01 May 2015) $ + */ +#include "m2sxxx.h" +#if MSCC_NO_RELATIVE_PATHS +#include "sys_config.h" +#else +#include "../drivers_config/sys_config/sys_config.h" +#endif +#include "sys_init_cfg_types.h" +/*------------------------------------------------------------------------------ + Silicon revisions. + */ +#define UNKNOWN_SILICON_REV 0 +#define M2S050_REV_A_SILICON 1 +#define M2S050_REV_B_SILICON 2 + +/*------------------------------------------------------------------------------ + * CoreConfigP IP block version. + */ +#define CORE_CONFIGP_V7_0 0x00070000u + +/*------------------------------------------------------------------------------ + * + */ +void mscc_post_hw_cfg_init(void); + +/*------------------------------------------------------------------------------ + * CoreConfigP/CoreConfigP register bits + */ +#define CONFIG_1_DONE 1u +#define CONFIG_2_DONE 2u + +#define INIT_DONE_MASK 0x00000001u +#define SDIF_RELEASED_MASK 0x00000002u + +/*------------------------------------------------------------------------------ + * System registers of interest. + */ +/* + * MSSDDR_FACC1_CR register masks: + */ +#define DDR_CLK_EN_SHIFT 8u +#define FACC_GLMUX_SEL_MASK 0x00001000u +#define CONTROLLER_PLL_INIT_MASK 0x04000000u +#define RCOSC_DIV2_MASK 0x00000004u + +/* + * MSSDDR_PLL_STATUS register masks: + */ +#define FAB_PLL_LOCK_MASK 0x00000001u +#define MPLL_LOCK_MASK 0x00000002u + +/* + * MSSDDR_PLL_STATUS_HIGH_CR register masks: + */ +#define FACC_PLL_BYPASS_MASK 0x00000001u + +/*------------------------------------------------------------------------------ + * Standard CMSIS global variables. + */ +uint32_t SystemCoreClock = MSS_SYS_M3_CLK_FREQ; /*!< System Clock Frequency (Core Clock) */ + +/*------------------------------------------------------------------------------ + * SmartFusion2 specific clocks. + */ +uint32_t g_FrequencyPCLK0 = MSS_SYS_APB_0_CLK_FREQ; /*!< Clock frequency of APB bus 0. */ +uint32_t g_FrequencyPCLK1 = MSS_SYS_APB_1_CLK_FREQ; /*!< Clock frequency of APB bus 1. */ +uint32_t g_FrequencyPCLK2 = MSS_SYS_APB_2_CLK_FREQ; /*!< Clock frequency of APB bus 2. */ +uint32_t g_FrequencyFIC0 = MSS_SYS_FIC_0_CLK_FREQ; /*!< Clock frequecny of FPGA fabric interface controller 1. */ +uint32_t g_FrequencyFIC1 = MSS_SYS_FIC_1_CLK_FREQ; /*!< Clock frequecny of FPGA fabric inteface controller 2. */ +uint32_t g_FrequencyFIC64 = MSS_SYS_FIC64_CLK_FREQ; /*!< Clock frequecny of 64-bit FPGA fabric interface controller. */ + +/*------------------------------------------------------------------------------ + * System configuration tables generated by Libero. + */ +#if MSS_SYS_MDDR_CONFIG_BY_CORTEX +extern MDDR_TypeDef * const g_m2s_mddr_addr; +extern const ddr_subsys_cfg_t g_m2s_mddr_subsys_config; +#endif + +#if MSS_SYS_FDDR_CONFIG_BY_CORTEX +extern FDDR_TypeDef * const g_m2s_fddr_addr; +extern const ddr_subsys_cfg_t g_m2s_fddr_subsys_config; +#endif + +#define MSS_SYS_SERDES_CONFIG_BY_CORTEX (MSS_SYS_SERDES_0_CONFIG_BY_CORTEX || MSS_SYS_SERDES_1_CONFIG_BY_CORTEX || MSS_SYS_SERDES_2_CONFIG_BY_CORTEX || MSS_SYS_SERDES_3_CONFIG_BY_CORTEX) + +#if MSS_SYS_SERDES_0_CONFIG_BY_CORTEX +extern const cfg_addr_value_pair_t g_m2s_serdes_0_config[SERDES_0_CFG_NB_OF_PAIRS]; +#endif + +#if MSS_SYS_SERDES_1_CONFIG_BY_CORTEX +extern const cfg_addr_value_pair_t g_m2s_serdes_1_config[SERDES_1_CFG_NB_OF_PAIRS]; +#endif + +#if MSS_SYS_SERDES_2_CONFIG_BY_CORTEX +extern const cfg_addr_value_pair_t g_m2s_serdes_2_config[SERDES_2_CFG_NB_OF_PAIRS]; +#endif + +#if MSS_SYS_SERDES_3_CONFIG_BY_CORTEX +extern const cfg_addr_value_pair_t g_m2s_serdes_3_config[SERDES_3_CFG_NB_OF_PAIRS]; +#endif + +#define MSS_SYS_CORESF2RESET_USED (MSS_SYS_MDDR_CONFIG_BY_CORTEX || MSS_SYS_FDDR_CONFIG_BY_CORTEX || MSS_SYS_SERDES_CONFIG_BY_CORTEX) + +/*============================================================================== + * List of PCIe lanes on which PMA_READY must be polled. Allows only polling PMA + * READY on the first lane of a PCIe link regardless of the number of lanes used + * or whether lane reversal is used. + */ +#if MSS_SYS_SERDES_CONFIG_BY_CORTEX + +#define CONFIG_REG_LANE_SEL_LANE_0 0x00000100U +#define CONFIG_REG_LANE_SEL_LANE_1 0x00000200U +#define CONFIG_REG_LANE_SEL_LANE_2 0x00000400U +#define CONFIG_REG_LANE_SEL_LANE_3 0x00000800U + +#define CONFIG_REG_LANE_SEL_MASK (CONFIG_REG_LANE_SEL_LANE_0 | \ + CONFIG_REG_LANE_SEL_LANE_1 | \ + CONFIG_REG_LANE_SEL_LANE_2 | \ + CONFIG_REG_LANE_SEL_LANE_3) + +#define FIRST_PCIE_CTRL 1U +#define SECOND_PCIE_CTRL 2U + +typedef struct pma_poll_info +{ + SERDESIF_TypeDef * serdes; + SERDES_TypeDef * const lane; + uint16_t config_reg_lane_sel; + uint16_t pcie_ctrl_id; /* distinguish between first and second PCIe controller on M2S090. */ +} pma_poll_info_t; + +/*------------------------------------------------------------------------------ + * SERDES0: list of PMA to poll as part of PCIe configuration. This list only + * handles the first PCIe controller of SERDES0. + */ +static const pma_poll_info_t g_serdes0_pcie_lane_cfg_lut[] = +{ + #if defined(SERDESIF_0_PCIE_LANE_PMA_STATUS_LANE_0) + { + SERDES0, /* SERDESIF_TypeDef * serdes */ + &SERDES0->lane[0], /* SERDES_TypeDef * const lane */ + CONFIG_REG_LANE_SEL_LANE_0, /* uint16_t config_reg_lane_sel */ + FIRST_PCIE_CTRL /* uint16_t pcie_ctrl_id */ + }, + #endif + + #if defined(SERDESIF_0_PCIE_LANE_PMA_STATUS_LANE_1) + { + SERDES0, /* SERDESIF_TypeDef * serdes */ + &SERDES0->lane[1], /* SERDES_TypeDef * const lane */ + CONFIG_REG_LANE_SEL_LANE_1, /* uint16_t config_reg_lane_sel */ + FIRST_PCIE_CTRL /* uint16_t pcie_ctrl_id */ + }, + #endif + + #if defined(SERDESIF_0_PCIE_LANE_PMA_STATUS_LANE_2) + { + SERDES0, /* SERDESIF_TypeDef * serdes */ + &SERDES0->lane[2], /* SERDES_TypeDef * const lane */ + CONFIG_REG_LANE_SEL_LANE_2, /* uint16_t config_reg_lane_sel */ + FIRST_PCIE_CTRL /* uint16_t pcie_ctrl_id */ + }, + #endif + + #if defined(SERDESIF_0_PCIE_LANE_PMA_STATUS_LANE_3) + { + SERDES0, /* SERDESIF_TypeDef * serdes */ + &SERDES0->lane[3], /* SERDES_TypeDef * const lane */ + CONFIG_REG_LANE_SEL_LANE_3, /* uint16_t config_reg_lane_sel */ + FIRST_PCIE_CTRL /* uint16_t pcie_ctrl_id */ + }, + #endif + + { + (SERDESIF_TypeDef *)0, /* SERDESIF_TypeDef * serdes */ + (SERDES_TypeDef *)0, /* SERDES_TypeDef * const lane */ + 0, /* uint16_t config_reg_lane_sel */ + 0 /* uint16_t pcie_ctrl_id */ + } +}; + +/*------------------------------------------------------------------------------ + * SERDES1: list of PMA to poll as part of PCIe configuration. This list handles + * both SERDES1 first PCIe controller and the M2S090 SERDES0 second PCIe + * controller. + */ +static const pma_poll_info_t g_serdes1_pcie_lane_cfg_lut[] = +{ + #if defined(SERDESIF_1_PCIE_LANE_PMA_STATUS_LANE_0) + { + SERDES1, /* SERDESIF_TypeDef * serdes */ + &SERDES1->lane[0], /* SERDES_TypeDef * const lane */ + CONFIG_REG_LANE_SEL_LANE_0, /* uint16_t config_reg_lane_sel */ + FIRST_PCIE_CTRL /* uint16_t pcie_ctrl_id */ + }, + #endif + + #if defined(SERDESIF_1_PCIE_LANE_PMA_STATUS_LANE_1) + { + SERDES1, /* SERDESIF_TypeDef * serdes */ + &SERDES1->lane[1], /* SERDES_TypeDef * const lane */ + CONFIG_REG_LANE_SEL_LANE_1, /* uint16_t config_reg_lane_sel */ + FIRST_PCIE_CTRL /* uint16_t pcie_ctrl_id */ + }, + #endif + + #if defined(SERDESIF_1_PCIE_LANE_PMA_STATUS_LANE_2) + { + SERDES1, /* SERDESIF_TypeDef * serdes */ + &SERDES1->lane[2], /* SERDES_TypeDef * const lane */ + CONFIG_REG_LANE_SEL_LANE_2, /* uint16_t config_reg_lane_sel */ + FIRST_PCIE_CTRL /* uint16_t pcie_ctrl_id */ + }, + #endif + + #if defined(SERDESIF_1_PCIE_LANE_PMA_STATUS_LANE_3) + { + SERDES1, /* SERDESIF_TypeDef * serdes */ + &SERDES1->lane[3], /* SERDES_TypeDef * const lane */ + CONFIG_REG_LANE_SEL_LANE_3, /* uint16_t config_reg_lane_sel */ + FIRST_PCIE_CTRL /* uint16_t pcie_ctrl_id */ + }, + #endif + #if defined(SERDESIF_0_PCIE_1_LANE_PMA_STATUS_LANE_0) + { + SERDES0, /* SERDESIF_TypeDef * serdes */ + &SERDES0->lane[0], /* SERDES_TypeDef * const lane */ + CONFIG_REG_LANE_SEL_LANE_0, /* uint16_t config_reg_lane_sel */ + SECOND_PCIE_CTRL /* uint16_t pcie_ctrl_id */ + }, + #endif + + #if defined(SERDESIF_0_PCIE_1_LANE_PMA_STATUS_LANE_1) + { + SERDES0, /* SERDESIF_TypeDef * serdes */ + &SERDES0->lane[1], /* SERDES_TypeDef * const lane */ + CONFIG_REG_LANE_SEL_LANE_1, /* uint16_t config_reg_lane_sel */ + SECOND_PCIE_CTRL /* uint16_t pcie_ctrl_id */ + }, + #endif + + #if defined(SERDESIF_0_PCIE_1_LANE_PMA_STATUS_LANE_2) + { + SERDES0, /* SERDESIF_TypeDef * serdes */ + &SERDES0->lane[2], /* SERDES_TypeDef * const lane */ + CONFIG_REG_LANE_SEL_LANE_2, /* uint16_t config_reg_lane_sel */ + SECOND_PCIE_CTRL /* uint16_t pcie_ctrl_id */ + }, + #endif + + #if defined(SERDESIF_0_PCIE_1_LANE_PMA_STATUS_LANE_3) + { + SERDES0, /* SERDESIF_TypeDef * serdes */ + &SERDES0->lane[3], /* SERDES_TypeDef * const lane */ + CONFIG_REG_LANE_SEL_LANE_3, /* uint16_t config_reg_lane_sel */ + SECOND_PCIE_CTRL /* uint16_t pcie_ctrl_id */ + }, + #endif + { + (SERDESIF_TypeDef *)0, /* SERDESIF_TypeDef * serdes */ + (SERDES_TypeDef *)0, /* SERDES_TypeDef * const lane */ + 0, /* uint16_t config_reg_lane_sel */ + 0 /* uint16_t pcie_ctrl_id */ + } +}; + +/*------------------------------------------------------------------------------ + * SERDES2: list of PMA to poll as part of PCIe configuration. + */ +static const pma_poll_info_t g_serdes2_pcie_lane_cfg_lut[] = +{ + #if defined(SERDESIF_2_PCIE_LANE_PMA_STATUS_LANE_0) + { + SERDES2, /* SERDESIF_TypeDef * serdes */ + &SERDES2->lane[0], /* SERDES_TypeDef * const lane */ + CONFIG_REG_LANE_SEL_LANE_0, /* uint16_t config_reg_lane_sel */ + FIRST_PCIE_CTRL /* uint16_t pcie_ctrl_id */ + }, + #endif + + #if defined(SERDESIF_2_PCIE_LANE_PMA_STATUS_LANE_1) + { + SERDES2, /* SERDESIF_TypeDef * serdes */ + &SERDES2->lane[1], /* SERDES_TypeDef * const lane */ + CONFIG_REG_LANE_SEL_LANE_1, /* uint16_t config_reg_lane_sel */ + FIRST_PCIE_CTRL /* uint16_t pcie_ctrl_id */ + }, + #endif + + #if defined(SERDESIF_2_PCIE_LANE_PMA_STATUS_LANE_2) + { + SERDES2, /* SERDESIF_TypeDef * serdes */ + &SERDES2->lane[2], /* SERDES_TypeDef * const lane */ + CONFIG_REG_LANE_SEL_LANE_2, /* uint16_t config_reg_lane_sel */ + FIRST_PCIE_CTRL /* uint16_t pcie_ctrl_id */ + }, + #endif + + #if defined(SERDESIF_2_PCIE_LANE_PMA_STATUS_LANE_3) + { + SERDES2, /* SERDESIF_TypeDef * serdes */ + &SERDES2->lane[3], /* SERDES_TypeDef * const lane */ + CONFIG_REG_LANE_SEL_LANE_3, /* uint16_t config_reg_lane_sel */ + FIRST_PCIE_CTRL /* uint16_t pcie_ctrl_id */ + }, + #endif + + { + (SERDESIF_TypeDef *)0, /* SERDESIF_TypeDef * serdes */ + (SERDES_TypeDef *)0, /* SERDES_TypeDef * const lane */ + 0, /* uint16_t config_reg_lane_sel */ + 0 /* uint16_t pcie_ctrl_id */ + } +}; + +/*------------------------------------------------------------------------------ + * SERDES3: list of PMA to poll as part of PCIe configuration. + */ +static const pma_poll_info_t g_serdes3_pcie_lane_cfg_lut[] = +{ + #if defined(SERDESIF_3_PCIE_LANE_PMA_STATUS_LANE_0) + { + SERDES3, /* SERDESIF_TypeDef * serdes */ + &SERDES3->lane[0], /* SERDES_TypeDef * const lane */ + CONFIG_REG_LANE_SEL_LANE_0, /* uint16_t config_reg_lane_sel */ + FIRST_PCIE_CTRL /* uint16_t pcie_ctrl_id */ + }, + #endif + + #if defined(SERDESIF_3_PCIE_LANE_PMA_STATUS_LANE_1) + { + SERDES3, /* SERDESIF_TypeDef * serdes */ + &SERDES3->lane[1], /* SERDES_TypeDef * const lane */ + CONFIG_REG_LANE_SEL_LANE_1, /* uint16_t config_reg_lane_sel */ + FIRST_PCIE_CTRL /* uint16_t pcie_ctrl_id */ + }, + #endif + + #if defined(SERDESIF_3_PCIE_LANE_PMA_STATUS_LANE_2) + { + SERDES3, /* SERDESIF_TypeDef * serdes */ + &SERDES3->lane[2], /* SERDES_TypeDef * const lane */ + CONFIG_REG_LANE_SEL_LANE_2, /* uint16_t config_reg_lane_sel */ + FIRST_PCIE_CTRL /* uint16_t pcie_ctrl_id */ + }, + #endif + + #if defined(SERDESIF_3_PCIE_LANE_PMA_STATUS_LANE_3) + { + SERDES3, /* SERDESIF_TypeDef * serdes */ + &SERDES3->lane[3], /* SERDES_TypeDef * const lane */ + CONFIG_REG_LANE_SEL_LANE_3, /* uint16_t config_reg_lane_sel */ + FIRST_PCIE_CTRL /* uint16_t pcie_ctrl_id */ + }, + #endif + + { + (SERDESIF_TypeDef *)0, /* SERDESIF_TypeDef * serdes */ + (SERDES_TypeDef *)0, /* SERDES_TypeDef * const lane */ + 0, /* uint16_t config_reg_lane_sel */ + 0 /* uint16_t pcie_ctrl_id */ + } +}; + +/*------------------------------------------------------------------------------ + * Master lookup table for all SERDES PCIe configuration. + */ +static const pma_poll_info_t * const g_pcie_lane_cfg_lut[] = +{ + g_serdes0_pcie_lane_cfg_lut, + g_serdes1_pcie_lane_cfg_lut, + g_serdes2_pcie_lane_cfg_lut, + g_serdes3_pcie_lane_cfg_lut +}; + +#endif + +/*------------------------------------------------------------------------------ + * Local functions: + */ +static uint32_t get_silicon_revision(void); +static void silicon_workarounds(void); +static void m2s050_rev_a_workarounds(void); + +#if (MSS_SYS_FACC_INIT_BY_CORTEX == 1) +static void complete_clock_config(void); +#endif + +#if MSS_SYS_SERDES_CONFIG_BY_CORTEX +static void configure_serdes_intf(void); +static void configure_pcie_intf(void); + +static void configure_pcie_block +( + const cfg_addr_value_pair_t * p_addr_value_pair, + uint32_t nb_of_cfg_pairs, + uint32_t serdes_id +); +#endif + +#if (MSS_SYS_MDDR_CONFIG_BY_CORTEX || MSS_SYS_FDDR_CONFIG_BY_CORTEX) +static void config_ddr_subsys +( + const ddr_subsys_cfg_t * p_ddr_subsys_cfg, + DDRCore_TypeDef * p_ddr_subsys_regs +); +#endif + +#if MSS_SYS_SERDES_CONFIG_BY_CORTEX +static void config_by_addr_value +( + const cfg_addr_value_pair_t * p_addr_value_pair, + uint32_t nb_of_cfg_pairs +); +#endif + +static uint32_t get_rcosc_25_50mhz_frequency(void); +static void set_clock_frequency_globals(uint32_t fclk); + +/***************************************************************************//** + * See system_m2sxxx.h for details. + */ +void SystemInit(void) +{ +#if MSS_SYS_SERDES_CONFIG_BY_CORTEX + uint32_t sdif_released; +#endif +#if MSS_SYS_CORESF2RESET_USED + uint32_t init_done; +#endif + +#if MSS_SYS_SERDES_CONFIG_BY_CORTEX + uint32_t core_cfg_version; + + core_cfg_version = CORE_SF2_CFG->IP_VERSION_SR; +#endif + + /* + * Do not make use of global variables or make any asumptions regarding + * memory content if modifying this function. The memory content has not been + * initialised by the time this function is called by the start-up code. + */ +#if (MSS_SYS_FACC_INIT_BY_CORTEX == 1) + complete_clock_config(); +#endif + + silicon_workarounds(); + + /*-------------------------------------------------------------------------- + * Set STKALIGN to ensure exception stacking starts on 8 bytes address + * boundary. This ensures compliance with the "Procedure Call Standards for + * the ARM Architecture" (AAPCS). + */ + SCB->CCR |= SCB_CCR_STKALIGN_Msk; + + /*-------------------------------------------------------------------------- + * MDDR configuration + */ +#if MSS_SYS_MDDR_CONFIG_BY_CORTEX + if(0u == SYSREG->DDR_CR) + { + /* + * We only configure the MDDR memory controller if MDDR is not remapped + * to address 0x00000000. If MDDR is remapped to 0x00000000 then we are + * probably executing this code from MDDR in a debugging session and + * attempting to reconfigure the MDDR memory controller will cause the + * Cortex-M3 to crash. + */ + config_ddr_subsys(&g_m2s_mddr_subsys_config, &g_m2s_mddr_addr->core); + } +#endif + + /*-------------------------------------------------------------------------- + * FDDR configuration + */ +#if MSS_SYS_FDDR_CONFIG_BY_CORTEX + config_ddr_subsys(&g_m2s_fddr_subsys_config, &g_m2s_fddr_addr->core); +#endif + + /*-------------------------------------------------------------------------- + * Call user defined configuration function. + */ + mscc_post_hw_cfg_init(); + + /*-------------------------------------------------------------------------- + * SERDES interfaces configuration. + */ +#if MSS_SYS_SERDES_CONFIG_BY_CORTEX + configure_serdes_intf(); + + if(core_cfg_version >= CORE_CONFIGP_V7_0) + { + CORE_SF2_CFG->CONFIG_DONE = CONFIG_1_DONE; + + /* Poll for SDIF_RELEASED. */ + do + { + sdif_released = CORE_SF2_CFG->INIT_DONE & SDIF_RELEASED_MASK; + } while (0u == sdif_released); + } + + configure_pcie_intf(); +#endif + + /*-------------------------------------------------------------------------- + * Synchronize with CoreSF2Reset controlling resets from the fabric. + */ +#if MSS_SYS_CORESF2RESET_USED + /* + * Negate FPGA_SOFTRESET to de-assert MSS_RESET_N_M2F in the fabric. We must + * do this here because this signal is only deasserted by the System + * Controller on a power-on reset. Other types of reset such as a watchdog + * reset would result in the FPGA fabric being held in reset and getting + * stuck waiting for the CoreSF2Config INIT_DONE to become asserted. + */ + SYSREG->SOFT_RST_CR &= ~SYSREG_FPGA_SOFTRESET_MASK; + + /* + * Signal to CoreSF2Reset that peripheral configuration registers have been + * written. + */ + CORE_SF2_CFG->CONFIG_DONE |= (CONFIG_1_DONE | CONFIG_2_DONE); + + /* Wait for INIT_DONE from CoreSF2Reset. */ + do + { + init_done = CORE_SF2_CFG->INIT_DONE & INIT_DONE_MASK; + } while (0u == init_done); +#endif +} + +/***************************************************************************//** + * SystemCoreClockUpdate() + */ +#define RCOSC_25_50MHZ_CLK_SRC 0u +#define CLK_XTAL_CLK_SRC 1u +#define RCOSC_1_MHZ_CLK_SRC 2u +#define CCC2ASCI_CLK_SRC 3u + +#define FACC_STANDBY_SHIFT 6u +#define FACC_STANDBY_SEL_MASK 0x00000007u + +#define FREQ_32KHZ 32768u +#define FREQ_1MHZ 1000000u +#define FREQ_25MHZ 25000000u +#define FREQ_50MHZ 50000000u + +void SystemCoreClockUpdate(void) +{ + uint32_t controller_pll_init; + uint32_t clk_src; + + controller_pll_init = SYSREG->MSSDDR_FACC1_CR & CONTROLLER_PLL_INIT_MASK; + + if(0u == controller_pll_init) + { + /* Normal operations. */ + uint32_t global_mux_sel; + + global_mux_sel = SYSREG->MSSDDR_FACC1_CR & FACC_GLMUX_SEL_MASK; + if(0u == global_mux_sel) + { + /* MSS clocked from MSS PLL. Use Libero flow defines. */ + SystemCoreClock = MSS_SYS_M3_CLK_FREQ; + g_FrequencyPCLK0 = MSS_SYS_APB_0_CLK_FREQ; + g_FrequencyPCLK1 = MSS_SYS_APB_1_CLK_FREQ; + g_FrequencyPCLK2 = MSS_SYS_APB_2_CLK_FREQ; + g_FrequencyFIC0 = MSS_SYS_FIC_0_CLK_FREQ; + g_FrequencyFIC1 = MSS_SYS_FIC_1_CLK_FREQ; + g_FrequencyFIC64 = MSS_SYS_FIC64_CLK_FREQ; + } + else + { + /* MSS clocked from standby clock. */ + const uint8_t standby_clock_lut[8] = { RCOSC_25_50MHZ_CLK_SRC, + CLK_XTAL_CLK_SRC, + RCOSC_25_50MHZ_CLK_SRC, + CLK_XTAL_CLK_SRC, + RCOSC_1_MHZ_CLK_SRC, + RCOSC_1_MHZ_CLK_SRC, + CCC2ASCI_CLK_SRC, + CCC2ASCI_CLK_SRC }; + + uint32_t standby_sel; + uint8_t clock_source; + + standby_sel = (SYSREG->MSSDDR_FACC2_CR >> FACC_STANDBY_SHIFT) & FACC_STANDBY_SEL_MASK; + clock_source = standby_clock_lut[standby_sel]; + switch(clock_source) + { + case RCOSC_25_50MHZ_CLK_SRC: + clk_src = get_rcosc_25_50mhz_frequency(); + set_clock_frequency_globals(clk_src); + break; + + case CLK_XTAL_CLK_SRC: + set_clock_frequency_globals(FREQ_32KHZ); + break; + + case RCOSC_1_MHZ_CLK_SRC: + set_clock_frequency_globals(FREQ_1MHZ); + break; + + case CCC2ASCI_CLK_SRC: + /* Fall through. */ + default: + set_clock_frequency_globals(FREQ_1MHZ); + break; + } + } + } + else + { + /* PLL initialization mode. Running from 25/50MHZ RC oscillator. */ + clk_src = get_rcosc_25_50mhz_frequency(); + set_clock_frequency_globals(clk_src); + } +} + +/***************************************************************************//** + * Find out frequency generated by the 25_50mhz RC osciallator. + */ +static uint32_t get_rcosc_25_50mhz_frequency(void) +{ + uint32_t rcosc_div2; + uint32_t rcosc_frequency; + + rcosc_div2 = SYSREG->MSSDDR_PLL_STATUS & RCOSC_DIV2_MASK; + if(0u == rcosc_div2) + { + /* 25_50mhz oscillator is configured for 25 MHz operations. */ + rcosc_frequency = FREQ_25MHZ; + } + else + { + /* 25_50mhz oscillator is configured for 50 MHz operations. */ + rcosc_frequency = FREQ_50MHZ; + } + + return rcosc_frequency; +} + +/***************************************************************************//** + Set the value of the clock frequency global variables based on the value of + standby_clk passed as parameter. + The following global variables are set by this function: + - SystemCoreClock + - g_FrequencyPCLK0 + - g_FrequencyPCLK1 + - g_FrequencyPCLK2 + - g_FrequencyFIC0 + - g_FrequencyFIC1 + - g_FrequencyFIC64 + */ +static void set_clock_frequency_globals(uint32_t standby_clk) +{ + SystemCoreClock = standby_clk; + g_FrequencyPCLK0 = standby_clk; + g_FrequencyPCLK1 = standby_clk; + g_FrequencyPCLK2 = MSS_SYS_APB_2_CLK_FREQ; + g_FrequencyFIC0 = standby_clk; + g_FrequencyFIC1 = standby_clk; + g_FrequencyFIC64 = standby_clk; +} + +/***************************************************************************//** + * Write 16-bit configuration values into 32-bit word aligned registers. + */ +#if (MSS_SYS_MDDR_CONFIG_BY_CORTEX || MSS_SYS_FDDR_CONFIG_BY_CORTEX) +static void copy_cfg16_to_regs +( + volatile uint32_t * p_regs, + const uint16_t * p_cfg, + uint32_t nb_16bit_words +) +{ + uint32_t inc; + + for(inc = 0u; inc < nb_16bit_words; ++inc) + { + p_regs[inc] = p_cfg[inc]; + } +} +#endif + +/***************************************************************************//** + * Configure peripheral using register address and register value pairs. + */ +#if MSS_SYS_SERDES_CONFIG_BY_CORTEX +static void config_by_addr_value +( + const cfg_addr_value_pair_t * p_addr_value_pair, + uint32_t nb_of_cfg_pairs +) +{ + uint32_t inc; + + for(inc = 0u; inc < nb_of_cfg_pairs; ++inc) + { + *p_addr_value_pair[inc].p_reg = p_addr_value_pair[inc].value; + } +} +#endif + +/***************************************************************************//** + * DDR subsystem configuration. + */ +#if (MSS_SYS_MDDR_CONFIG_BY_CORTEX || MSS_SYS_FDDR_CONFIG_BY_CORTEX) + +#define NB_OF_DDRC_REGS_TO_CONFIG 57u +#define NB_OF_DDR_PHY_REGS_TO_CONFIG 65u + +static void config_ddr_subsys +( + const ddr_subsys_cfg_t * p_ddr_subsys_cfg, + DDRCore_TypeDef * p_ddr_subsys_regs +) +{ + volatile uint32_t * p_regs; + const uint16_t * p_cfg; + + /*-------------------------------------------------------------------------- + * Configure DDR controller part of the MDDR subsystem. + */ + p_cfg = &p_ddr_subsys_cfg->ddrc.DYN_SOFT_RESET_CR; + p_regs = &p_ddr_subsys_regs->ddrc.DYN_SOFT_RESET_CR; + + copy_cfg16_to_regs(p_regs, p_cfg, NB_OF_DDRC_REGS_TO_CONFIG); + + /*-------------------------------------------------------------------------- + * Configure DDR PHY. + */ + p_cfg = &p_ddr_subsys_cfg->phy.LOOPBACK_TEST_CR; + p_regs = &p_ddr_subsys_regs->phy.LOOPBACK_TEST_CR; + + copy_cfg16_to_regs(p_regs, p_cfg, NB_OF_DDR_PHY_REGS_TO_CONFIG); + + /*-------------------------------------------------------------------------- + * Configure DDR FIC. + */ + p_ddr_subsys_regs->fic.NB_ADDR_CR = p_ddr_subsys_cfg->fic.NB_ADDR_CR; + p_ddr_subsys_regs->fic.NBRWB_SIZE_CR = p_ddr_subsys_cfg->fic.NBRWB_SIZE_CR; + p_ddr_subsys_regs->fic.WB_TIMEOUT_CR = p_ddr_subsys_cfg->fic.WB_TIMEOUT_CR; + p_ddr_subsys_regs->fic.HPD_SW_RW_EN_CR = p_ddr_subsys_cfg->fic.HPD_SW_RW_EN_CR; + p_ddr_subsys_regs->fic.HPD_SW_RW_INVAL_CR = p_ddr_subsys_cfg->fic.HPD_SW_RW_INVAL_CR; + p_ddr_subsys_regs->fic.SW_WR_ERCLR_CR = p_ddr_subsys_cfg->fic.SW_WR_ERCLR_CR; + p_ddr_subsys_regs->fic.ERR_INT_ENABLE_CR = p_ddr_subsys_cfg->fic.ERR_INT_ENABLE_CR; + p_ddr_subsys_regs->fic.NUM_AHB_MASTERS_CR = p_ddr_subsys_cfg->fic.NUM_AHB_MASTERS_CR; + p_ddr_subsys_regs->fic.LOCK_TIMEOUTVAL_CR[0] = p_ddr_subsys_cfg->fic.LOCK_TIMEOUTVAL_1_CR; + p_ddr_subsys_regs->fic.LOCK_TIMEOUTVAL_CR[1] = p_ddr_subsys_cfg->fic.LOCK_TIMEOUTVAL_2_CR; + p_ddr_subsys_regs->fic.LOCK_TIMEOUT_EN_CR = p_ddr_subsys_cfg->fic.LOCK_TIMEOUT_EN_CR; + + /*-------------------------------------------------------------------------- + * Enable DDR. + */ + p_ddr_subsys_regs->ddrc.DYN_SOFT_RESET_CR = 0x01u; + + while(0x0000u == p_ddr_subsys_regs->ddrc.DDRC_SR) + { + ; + } +} + +#endif + +/***************************************************************************//** + * Configure SERDES interfaces. + */ +#if MSS_SYS_SERDES_CONFIG_BY_CORTEX + +static void configure_serdes_intf(void) +{ + #if MSS_SYS_SERDES_0_CONFIG_BY_CORTEX + config_by_addr_value(g_m2s_serdes_0_config, SERDES_0_CFG_NB_OF_PAIRS); + #endif + + #if MSS_SYS_SERDES_1_CONFIG_BY_CORTEX + config_by_addr_value(g_m2s_serdes_1_config, SERDES_1_CFG_NB_OF_PAIRS); + #endif + + #if MSS_SYS_SERDES_2_CONFIG_BY_CORTEX + config_by_addr_value(g_m2s_serdes_2_config, SERDES_2_CFG_NB_OF_PAIRS); + #endif + + #if MSS_SYS_SERDES_3_CONFIG_BY_CORTEX + config_by_addr_value(g_m2s_serdes_3_config, SERDES_3_CFG_NB_OF_PAIRS); + #endif +} + +/***************************************************************************//** + * Configure PCIe interfaces. + */ +static void configure_pcie_intf(void) +{ + #if MSS_SYS_SERDES_0_CONFIG_BY_CORTEX + configure_pcie_block(g_m2s_serdes_0_config, SERDES_0_CFG_NB_OF_PAIRS, 0u); + #endif + + #if MSS_SYS_SERDES_1_CONFIG_BY_CORTEX + configure_pcie_block(g_m2s_serdes_1_config, SERDES_1_CFG_NB_OF_PAIRS, 1u); + #endif + + #if MSS_SYS_SERDES_2_CONFIG_BY_CORTEX + configure_pcie_block(g_m2s_serdes_2_config, SERDES_2_CFG_NB_OF_PAIRS, 2u); + #endif + + #if MSS_SYS_SERDES_3_CONFIG_BY_CORTEX + configure_pcie_block(g_m2s_serdes_3_config, SERDES_3_CFG_NB_OF_PAIRS, 3u); + #endif +} + +/*------------------------------------------------------------------------------ + Configure one individual PCIe block. + */ +static void configure_pcie_block +( + const cfg_addr_value_pair_t * p_addr_value_pair, + uint32_t nb_of_cfg_pairs, + uint32_t serdes_id +) +{ + uint32_t inc; + + const uint32_t PMA_READY_MASK = 0x00000080u; + const uint32_t PCIE_CTRL_REG_LENGTH = 0x1000u; + const uint32_t PCIE_CTLR_SOFTRESET_MASK = 0x00000001; + const uint32_t PCIE2_CTLR_SOFTRESET_MASK = 0x00000040; + + SERDESIF_TypeDef * const serdes_lut[4] = + { + SERDES0, SERDES1, SERDES2, SERDES3 + }; + + const uint32_t pcie_ctrl_top_addr_lut[4] = + { + SERDES0_CFG_BASE + PCIE_CTRL_REG_LENGTH, + SERDES1_CFG_BASE + PCIE_CTRL_REG_LENGTH, + SERDES2_CFG_BASE + PCIE_CTRL_REG_LENGTH, + SERDES3_CFG_BASE + PCIE_CTRL_REG_LENGTH + }; + + /* + * Poll for PMA_READY. + */ + inc = 0U; + while(g_pcie_lane_cfg_lut[serdes_id][inc].config_reg_lane_sel != 0) + { + uint32_t pma_ready; + uint32_t config_phy_mode_1; + + /* select lane */ + config_phy_mode_1 = g_pcie_lane_cfg_lut[serdes_id][inc].serdes->sys_regs.CONFIG_PHY_MODE_1; + config_phy_mode_1 &= ~CONFIG_REG_LANE_SEL_MASK; + config_phy_mode_1 |= (uint32_t)g_pcie_lane_cfg_lut[serdes_id][inc].config_reg_lane_sel; + g_pcie_lane_cfg_lut[serdes_id][inc].serdes->sys_regs.CONFIG_PHY_MODE_1 = config_phy_mode_1; + + /* Wait for PMA to become ready. */ + do + { + pma_ready = g_pcie_lane_cfg_lut[serdes_id][inc].lane->PMA_STATUS & PMA_READY_MASK; + } + while (0u == pma_ready); + ++inc; + } + + /* + * Configure the PCIe controller registers. + */ + for(inc = 0u; inc < nb_of_cfg_pairs; ++inc) + { + uint32_t reg_addr; + + reg_addr = (uint32_t)p_addr_value_pair[inc].p_reg; + + if(reg_addr < pcie_ctrl_top_addr_lut[serdes_id]) + { + *p_addr_value_pair[inc].p_reg = p_addr_value_pair[inc].value; + } + } + + /* + * Issue a soft-reset to the PCIe controller + */ + inc = 0U; + while(g_pcie_lane_cfg_lut[serdes_id][inc].config_reg_lane_sel != 0) + { + if(FIRST_PCIE_CTRL == g_pcie_lane_cfg_lut[serdes_id][inc].pcie_ctrl_id) + { + serdes_lut[serdes_id]->sys_regs.SERDESIF_SOFT_RESET &= ~PCIE_CTLR_SOFTRESET_MASK; + serdes_lut[serdes_id]->sys_regs.SERDESIF_SOFT_RESET |= PCIE_CTLR_SOFTRESET_MASK; + } + else + { + serdes_lut[serdes_id]->sys_regs.SERDESIF_SOFT_RESET &= ~PCIE2_CTLR_SOFTRESET_MASK; + serdes_lut[serdes_id]->sys_regs.SERDESIF_SOFT_RESET |= PCIE2_CTLR_SOFTRESET_MASK; + } + ++inc; + } +} + +#endif + +/*------------------------------------------------------------------------------ + Retrieve silicon revision from system registers. + */ +static uint32_t get_silicon_revision(void) +{ + uint32_t silicon_revision; + uint32_t device_version; + + device_version = SYSREG->DEVICE_VERSION; + switch(device_version) + { + case 0x0000F802: + silicon_revision = M2S050_REV_A_SILICON; + break; + + case 0x0001F802: + silicon_revision = M2S050_REV_B_SILICON; + break; + + default: + silicon_revision = UNKNOWN_SILICON_REV; + break; + } + + return silicon_revision; +} + +/*------------------------------------------------------------------------------ + Workarounds for various silicon versions. + */ +static void silicon_workarounds(void) +{ + uint32_t silicon_revision; + + silicon_revision = get_silicon_revision(); + + switch(silicon_revision) + { + case M2S050_REV_A_SILICON: + m2s050_rev_a_workarounds(); + break; + + case M2S050_REV_B_SILICON: + /* Fall through. */ + case UNKNOWN_SILICON_REV: + /* Fall through. */ + default: + break; + } +} + +/*------------------------------------------------------------------------------ + Silicon workarounds for M2S050 rev A. + */ +static void m2s050_rev_a_workarounds(void) +{ + /*-------------------------------------------------------------------------- + * Work around a couple of silicon issues: + */ + /* DDR_CLK_EN <- 1 */ + SYSREG->MSSDDR_FACC1_CR |= (uint32_t)1 << DDR_CLK_EN_SHIFT; + + /* CONTROLLER_PLL_INIT <- 0 */ + SYSREG->MSSDDR_FACC1_CR = SYSREG->MSSDDR_FACC1_CR & ~CONTROLLER_PLL_INIT_MASK; +} + +/*------------------------------------------------------------------------------ + Complete clock configuration if requested by Libero. + */ +#if (MSS_SYS_FACC_INIT_BY_CORTEX == 1) +static void complete_clock_config(void) +{ + uint32_t pll_locked; + + /* Wait for fabric PLL to lock. */ + do { + pll_locked = SYSREG->MSSDDR_PLL_STATUS & FAB_PLL_LOCK_MASK; + } while(!pll_locked); + + /* Negate MPLL bypass. */ + SYSREG->MSSDDR_PLL_STATUS_HIGH_CR &= ~FACC_PLL_BYPASS_MASK; + + /* Wait for MPLL to lock. */ + do { + pll_locked = SYSREG->MSSDDR_PLL_STATUS & MPLL_LOCK_MASK; + } while(!pll_locked); + + /* Switch FACC from standby to run mode. */ + SYSREG->MSSDDR_FACC1_CR &= ~FACC_GLMUX_SEL_MASK; + + /* Negate FPGA_SOFTRESET to de-assert MSS_RESET_N_M2F in the fabric */ + SYSREG->SOFT_RST_CR &= ~SYSREG_FPGA_SOFTRESET_MASK; +} +#endif + diff --git a/bsp/smartfusion2/CMSIS/system_m2sxxx.h b/bsp/smartfusion2/CMSIS/system_m2sxxx.h new file mode 100644 index 0000000000..496c601055 --- /dev/null +++ b/bsp/smartfusion2/CMSIS/system_m2sxxx.h @@ -0,0 +1,49 @@ +/******************************************************************************* + * (c) Copyright 2012-2013 Microsemi SoC Products Group. All rights reserved. + * + * SmartFusion2 CMSIS system initialization. + * + * SVN $Revision: 5280 $ + * SVN $Date: 2013-03-22 20:51:50 +0000 (Fri, 22 Mar 2013) $ + */ + +#ifndef SYSTEM_M2SXXX_H +#define SYSTEM_M2SXXX_H + +#ifdef __cplusplus +extern "C" { +#endif + +/* Standard CMSIS global variables. */ +extern uint32_t SystemCoreClock; /*!< System Clock Frequency (Core Clock) */ + +/* SmartFusion2 specific clocks. */ +extern uint32_t g_FrequencyPCLK0; /*!< Clock frequency of APB bus 0. */ +extern uint32_t g_FrequencyPCLK1; /*!< Clock frequency of APB bus 1. */ +extern uint32_t g_FrequencyPCLK2; /*!< Clock frequency of APB bus 2. */ +extern uint32_t g_FrequencyFIC0; /*!< Clock frequecny of FPGA fabric interface controller 1. */ +extern uint32_t g_FrequencyFIC1; /*!< Clock frequecny of FPGA fabric inteface controller 2. */ +extern uint32_t g_FrequencyFIC64; /*!< Clock frequecny of 64-bit FPGA fabric interface controller. */ + + +/***************************************************************************//** + * The SystemInit() is a standard CMSIS function called during system startup. + * It is meant to perform low level hardware setup such as configuring DDR and + * SERDES controllers. + */ +void SystemInit(void); + +/***************************************************************************//** + * The SystemCoreClockUpdate() is a standard CMSIS function which can be called + * by the application in order to ensure that the SystemCoreClock global + * variable contains the up to date Cortex-M3 core frequency. Calling this + * function also updates the global variables containing the frequencies of the + * APB busses connecting the peripherals. + */ +void SystemCoreClockUpdate(void); + +#ifdef __cplusplus +} +#endif + +#endif diff --git a/bsp/smartfusion2/README.md b/bsp/smartfusion2/README.md new file mode 100644 index 0000000000..23e7b3927c --- /dev/null +++ b/bsp/smartfusion2/README.md @@ -0,0 +1,92 @@ +## 移植RT-Thread到Microsemi SmartFusion2系列FPGA芯片 + +### 1. BSP简介 + +移植 RT-Thread 操作系统到 一款 **FPGA 芯片——M2S010** 上，该芯片属于 [Microsemi](https://www.microsemi.com/)（现Microchip）SmartFusion2系列，是一款**智能混合型FPGA**，片上除了 FPGA Fabric 逻辑部分，还包括一个 ARM® Cortex™-M3 内核的 MCU，主频最高 166MHz ，256KB eNVM，64KB eSRAM，集成GPIO、UART、I2C、SPI、CAN、USB等基本外设。 + +> 关于 Microsemi，第三大 FPGA 厂商，原 Actel 半导体，2010 年，Microsemi 收购 Actel，2018 年， Microchip 收购 Microsemi。 + +SmartFusion2 内部框图 + + + +### 2. 使用说明 + +#### 2.1 FPGA 工程设计 + +FPGA 部分使用 SmartDesign 图形化设计，不需要写 HDL 代码，时钟来自外部 50M 晶体输入，PLL 倍频 100M 提供给 MCU 使用，顶层配置如下图所示： + + + +MSS 部分仅使用到了GPIO 和UART0，其他外设未启用，两个 GPIO 配置成输出模式： + + + +配置完成的 FPGA 工程文件下载：[fpga_project.rar](https://wcc-blog.oss-cn-beijing.aliyuncs.com/Libero/RT-Thread/fpga_project.rar) + +#### 2.2 ARM 程序设计 + +ARM 程序使用 Keil MDK 5.26 开发，需要安装 M2S 系列芯片支持包：[Microsemi.M2Sxxx.1.0.64.pack](http://www.actel-ip.com/repositories/CMSIS-Pack/Microsemi.M2Sxxx.1.0.64.pack) + +如果官网下载失败，可以到以下地址下载：[Microsemi.M2Sxxx.1.0.64.pack](https://wcc-blog.oss-cn-beijing.aliyuncs.com/Libero/RT-Thread/Microsemi.M2Sxxx.1.0.64.pack) + +在官方生成的示例工程目录下，添加 RT-Thread 相关组件，并实现一些对接函数，最终的文件结构： + + + +### 3. 下载和运行 + +为了能使用 ARM 调试器连接到 ARM 内核，而不是 FPGA，需要把 JTAG_SEL 引脚置为低电平。使用 ARM 调试器，如 JLink，对应连接 JTAG 口的 TMS、TCK、GND 引脚，如果连接正常，可以检测到 ARM 芯片，如下图所示： + + + +配置对应的 Flash 编程算法： + + + +下载完成： + + + +如果编译 & 烧写无误，下载完成或者按下复位按键之后，会在串口上看到 RT-Thread 的启动 LOG 信息： + + +```c + \ | / +- RT - Thread Operating System + / | \ 4.0.3 build Jun 2 2020 + 2006 - 2020 Copyright by rt-thread team +msh > +``` + + + +### 4. 外设支持 + +目前仅移植了 RT-Thread 内核，支持线程调度、线程间同步和通信等，支持 Finsh 组件，PIN、Serial 等设备驱动将会在以后添加。 + +### 5. 资料下载 + +独立的工程文件下载： + +- FPGA 工程下载：[fpga_project.rar](https://wcc-blog.oss-cn-beijing.aliyuncs.com/Libero/RT-Thread/fpga_project.rar) +- ARM 工程下载：[smartfusion_rtt-master-4.0.3.rar](https://wcc-blog.oss-cn-beijing.aliyuncs.com/Libero/RT-Thread/smartfusion_rtt-master-4.0.3.rar) + +### 6. 注意事项 + +- FPGA 开发环境基于 Libero V11.8.2.4，向上兼容，不支持低版本 IDE。 +- ARM 开发环境基于 Keil MDK 5.26，如果使用SoftConsole IDE ，需要修改 `libcpu` 内的文件。 +- 调试内部 ARM 核，需要把 JTAG_SEL 拉低，否则调试器连接不上。 +- 使用 SoftConsole 开发环境可以直接使用官方的 Flash Pro 调试器进行 ARM 程序的调试。 +- 内核时钟需要和 FPGA 中 MSS 配置的对应，Libero 自动生成的时钟文件，可以直接替换`bsp\smartfusion2\libraries\sys_config`文件夹下的文件 。 + +### 7. 参考资料 + +- [学习路线 - RT-Thread 文档中心](https://www.rt-thread.org/document/site/) +- [Microsemi Libero系列中文教程](https://blog.csdn.net/whik1194/article/details/102901710) + +### 8. 联系我 + +- 邮箱：[email protected] +- 主页：www.wangchaochao.top +- 微信：wcc149 diff --git a/bsp/smartfusion2/del_obj_file.bat b/bsp/smartfusion2/del_obj_file.bat new file mode 100644 index 0000000000..e3f7398f61 --- /dev/null +++ b/bsp/smartfusion2/del_obj_file.bat @@ -0,0 +1,17 @@ +%ɾ��objĿ¼�µĶ����ļ�%
+del *.lnp /s
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+del *.htm /s
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+del *.map /s
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+del *.build_log.htm /s
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diff --git a/bsp/smartfusion2/hal/CortexM3/Keil/cpu_types.h b/bsp/smartfusion2/hal/CortexM3/Keil/cpu_types.h new file mode 100644 index 0000000000..eb81d6014f --- /dev/null +++ b/bsp/smartfusion2/hal/CortexM3/Keil/cpu_types.h @@ -0,0 +1,30 @@ +/******************************************************************************* + * (c) Copyright 2007-2013 Microsemi SoC Products Group. All rights reserved. + * + * SVN $Revision: 5258 $ + * SVN $Date: 2013-03-21 18:11:02 +0530 (Thu, 21 Mar 2013) $ + */ +#ifndef __CPU_TYPES_H +#define __CPU_TYPES_H 1 + +#include <stdint.h> + +/*------------------------------------------------------------------------------ + */ +typedef unsigned int size_t; + +/*------------------------------------------------------------------------------ + * addr_t: address type. + * Used to specify the address of peripherals present in the processor's memory + * map. + */ +typedef unsigned int addr_t; + +/*------------------------------------------------------------------------------ + * psr_t: processor state register. + * Used by HAL_disable_interrupts() and HAL_restore_interrupts() to store the + * processor's state between disabling and restoring interrupts. + */ +typedef unsigned int psr_t; + +#endif /* __CPU_TYPES_H */ diff --git a/bsp/smartfusion2/hal/CortexM3/Keil/hal.s b/bsp/smartfusion2/hal/CortexM3/Keil/hal.s new file mode 100644 index 0000000000..6f259a4312 --- /dev/null +++ b/bsp/smartfusion2/hal/CortexM3/Keil/hal.s @@ -0,0 +1,32 @@ +;------------------------------------------------------------------------------- +; (c) Copyright 2007-2013 Microsemi SoC Products Group. All rights reserved. +; +; Interrupt disabling/restoration for critical section protection. +; +; SVN $Revision: 5261 $ +; SVN $Date: 2013-03-21 19:52:41 +0530 (Thu, 21 Mar 2013) $ +; + AREA |.text|, CODE, READONLY + EXPORT HAL_disable_interrupts + EXPORT HAL_restore_interrupts + +;------------------------------------------------------------------------------- +; +; +HAL_disable_interrupts \ + PROC + mrs r0, PRIMASK + cpsid I + bx lr + ENDP + +;------------------------------------------------------------------------------- +; +; +HAL_restore_interrupts \ + PROC + msr PRIMASK, r0 + bx lr + ENDP + + END diff --git a/bsp/smartfusion2/hal/CortexM3/Keil/hw_macros.h b/bsp/smartfusion2/hal/CortexM3/Keil/hw_macros.h new file mode 100644 index 0000000000..910f10f81d --- /dev/null +++ b/bsp/smartfusion2/hal/CortexM3/Keil/hw_macros.h @@ -0,0 +1,96 @@ +/******************************************************************************* + * (c) Copyright 2007-2013 Microsemi SoC Products Group. All rights reserved. + * + * Hardware registers access macros. + * + * THE MACROS DEFINED IN THIS FILE ARE DEPRECATED. DO NOT USED FOR NEW + * DEVELOPMENT. + * + * These macros are used to access peripheral's registers. They allow access to + * 8, 16 and 32 bit wide registers. All accesses to peripheral registers should + * be done through these macros in order to ease porting accross different + * processors/bus architectures. + * + * Some of these macros also allow to access a specific register field. + * + * SVN $Revision: 5258 $ + * SVN $Date: 2013-03-21 18:11:02 +0530 (Thu, 21 Mar 2013) $ + */ +#ifndef __HW_REGISTER_MACROS_H +#define __HW_REGISTER_MACROS_H 1 + +/*------------------------------------------------------------------------------ + * 32 bits registers access: + */ +#define HW_get_uint32_reg(BASE_ADDR, REG_OFFSET) (*((uint32_t volatile *)(BASE_ADDR + REG_OFFSET##_REG_OFFSET))) + +#define HW_set_uint32_reg(BASE_ADDR, REG_OFFSET, VALUE) (*((uint32_t volatile *)(BASE_ADDR + REG_OFFSET##_REG_OFFSET)) = (VALUE)) + +#define HW_set_uint32_reg_field(BASE_ADDR, FIELD, VALUE) \ + (*((uint32_t volatile *)(BASE_ADDR + FIELD##_OFFSET)) = \ + ( \ + (uint32_t) \ + ( \ + (*((uint32_t volatile *)(BASE_ADDR + FIELD##_OFFSET))) & ~FIELD##_MASK) | \ + (uint32_t)(((VALUE) << FIELD##_SHIFT) & FIELD##_MASK) \ + ) \ + ) + +#define HW_get_uint32_reg_field( BASE_ADDR, FIELD ) \ + (( (*((uint32_t volatile *)(BASE_ADDR + FIELD##_OFFSET))) & FIELD##_MASK) >> FIELD##_SHIFT) + +/*------------------------------------------------------------------------------ + * 32 bits memory access: + */ +#define HW_get_uint32(BASE_ADDR) (*((uint32_t volatile *)(BASE_ADDR))) + +#define HW_set_uint32(BASE_ADDR, VALUE) (*((uint32_t volatile *)(BASE_ADDR)) = (VALUE)) + +/*------------------------------------------------------------------------------ + * 16 bits registers access: + */ +#define HW_get_uint16_reg(BASE_ADDR, REG_OFFSET) (*((uint16_t volatile *)(BASE_ADDR + REG_OFFSET##_REG_OFFSET))) + +#define HW_set_uint16_reg(BASE_ADDR, REG_OFFSET, VALUE) (*((uint16_t volatile *)(BASE_ADDR + REG_OFFSET##_REG_OFFSET)) = (VALUE)) + +#define HW_set_uint16_reg_field(BASE_ADDR, FIELD, VALUE) \ + (*((uint16_t volatile *)(BASE_ADDR + FIELD##_OFFSET)) = \ + ( \ + (uint16_t) \ + ( \ + (*((uint16_t volatile *)(BASE_ADDR + FIELD##_OFFSET))) & ~FIELD##_MASK) | \ + (uint16_t)(((VALUE) << FIELD##_SHIFT) & FIELD##_MASK) \ + ) \ + ) + +#define HW_get_uint16_reg_field( BASE_ADDR, FIELD ) \ + (( (*((uint16_t volatile *)(BASE_ADDR + FIELD##_OFFSET))) & FIELD##_MASK) >> FIELD##_SHIFT) + +/*------------------------------------------------------------------------------ + * 8 bits registers access: + */ +#define HW_get_uint8_reg(BASE_ADDR, REG_OFFSET) (*((uint8_t volatile *)(BASE_ADDR + REG_OFFSET##_REG_OFFSET))) + +#define HW_set_uint8_reg(BASE_ADDR, REG_OFFSET, VALUE) (*((uint8_t volatile *)(BASE_ADDR + REG_OFFSET##_REG_OFFSET)) = (VALUE)) + +#define HW_set_uint8_reg_field(BASE_ADDR, FIELD, VALUE) \ + (*((uint8_t volatile *)(BASE_ADDR + FIELD##_OFFSET)) = \ + ( \ + (uint8_t) \ + ( \ + (*((uint8_t volatile *)(BASE_ADDR + FIELD##_OFFSET))) & ~FIELD##_MASK) | \ + (uint8_t)(((VALUE) << FIELD##_SHIFT) & FIELD##_MASK) \ + ) \ + ) + +#define HW_get_uint8_reg_field( BASE_ADDR, FIELD ) \ + (( (*((uint8_t volatile *)(BASE_ADDR + FIELD##_OFFSET))) & FIELD##_MASK) >> FIELD##_SHIFT) + +/*------------------------------------------------------------------------------ + * 8 bits memory access: + */ +#define HW_get_uint8(BASE_ADDR) (*((uint8_t volatile *)(BASE_ADDR))) + +#define HW_set_uint8(BASE_ADDR, VALUE) (*((uint8_t volatile *)(BASE_ADDR)) = (VALUE)) + +#endif /* __HW_REGISTER_MACROS_H */ diff --git a/bsp/smartfusion2/hal/CortexM3/Keil/hw_reg_access.s b/bsp/smartfusion2/hal/CortexM3/Keil/hw_reg_access.s new file mode 100644 index 0000000000..b9b72167d6 --- /dev/null +++ b/bsp/smartfusion2/hal/CortexM3/Keil/hw_reg_access.s @@ -0,0 +1,175 @@ +;****************************************************************************** +; (c) Copyright 2008-2013 Microsemi SoC Products Group. All rights reserved. +; +; SVN $Revision: 5258 $ +; SVN $Date: 2013-03-21 18:11:02 +0530 (Thu, 21 Mar 2013) $ +; + + AREA |.text|, CODE, READONLY + EXPORT HW_set_32bit_reg + EXPORT HW_get_32bit_reg + EXPORT HW_set_32bit_reg_field + EXPORT HW_get_32bit_reg_field + EXPORT HW_set_16bit_reg + EXPORT HW_get_16bit_reg + EXPORT HW_set_16bit_reg_field + EXPORT HW_get_16bit_reg_field + EXPORT HW_set_8bit_reg + EXPORT HW_get_8bit_reg + EXPORT HW_set_8bit_reg_field + EXPORT HW_get_8bit_reg_field + +;------------------------------------------------------------------------------ +; R0: addr_t reg_addr +; R1: uint32_t value +; +HW_set_32bit_reg \ + PROC + STR R1, [R0] + BX LR + ENDP + +;------------------------------------------------------------------------------ +; R0: addr_t reg_addr +; +HW_get_32bit_reg \ + PROC + LDR R0, [R0] + BX LR + ENDP + +;------------------------------------------------------------------------------ +; R0: addr_t reg_addr +; R1: int_fast8_t shift +; R2: uint32_t mask +; R3: uint32_t value +; +HW_set_32bit_reg_field \ + PROC + PUSH {R1,R2,R3,LR} + LSL.W R3, R3, R1 + AND.W R3, R3, R2 + LDR R1, [R0] + MVN.W R2, R2 + AND.W R1, R1, R2 + ORR.W R1, R1, R3 + STR R1, [R0] + POP {R1,R2,R3,PC} + ENDP + +;------------------------------------------------------------------------------ +; R0: addr_t reg_addr +; R1: int_fast8_t shift +; R2: uint32_t mask +; +HW_get_32bit_reg_field \ + PROC + LDR R0, [R0] + AND.W R0, R0, R2 + LSR.W R0, R0, R1 + BX LR + ENDP + +;------------------------------------------------------------------------------ +; R0: addr_t reg_addr +; R1: uint_fast16_t value +; +HW_set_16bit_reg \ + PROC + STRH R1, [R0] + BX LR + ENDP + +;------------------------------------------------------------------------------ +; R0: addr_t reg_addr +; +HW_get_16bit_reg \ + PROC + LDRH R0, [R0] + BX LR + ENDP + +;------------------------------------------------------------------------------ +; R0: addr_t reg_addr +; R1: int_fast8_t shift +; R2: uint_fast16_t mask +; R3: uint_fast16_t value +; +HW_set_16bit_reg_field \ + PROC + PUSH {R1,R2,R3,LR} + LSL.W R3, R3, R1 + AND.W R3, R3, R2 + LDRH R1, [R0] + MVN.W R2, R2 + AND.W R1, R1, R2 + ORR.W R1, R1, R3 + STRH R1, [R0] + POP {R1,R2,R3,PC} + ENDP + +;------------------------------------------------------------------------------ +; R0: addr_t reg_addr +; R1: int_fast8_t shift +; R2: uint_fast16_t mask +; +HW_get_16bit_reg_field \ + PROC + LDRH R0, [R0] + AND.W R0, R0, R2 + LSR.W R0, R0, R1 + BX LR + ENDP + +;------------------------------------------------------------------------------ +; R0: addr_t reg_addr +; R1: uint_fast8_t value +; +HW_set_8bit_reg \ + PROC + STRB R1, [R0] + BX LR + ENDP + +;------------------------------------------------------------------------------ +; R0: addr_t reg_addr +; +HW_get_8bit_reg \ + PROC + LDRB R0, [R0] + BX LR + ENDP + +;------------------------------------------------------------------------------ +; R0: addr_t reg_addr, +; R1: int_fast8_t shift +; R2: uint_fast8_t mask +; R3: uint_fast8_t value +; +HW_set_8bit_reg_field \ + PROC + PUSH {R1,R2,R3,LR} + LSL.W R3, R3, R1 + AND.W R3, R3, R2 + LDRB R1, [R0] + MVN.W R2, R2 + AND.W R1, R1, R2 + ORR.W R1, R1, R3 + STRB R1, [R0] + POP {R1,R2,R3,PC} + ENDP + +;------------------------------------------------------------------------------ +; R0: addr_t reg_addr +; R1: int_fast8_t shift +; R2: uint_fast8_t mask +; +HW_get_8bit_reg_field \ + PROC + LDRB R0, [R0] + AND.W R0, R0, R2 + LSR.W R0, R0, R1 + BX LR + ENDP + + END diff --git a/bsp/smartfusion2/hal/CortexM3/cortex_nvic.c b/bsp/smartfusion2/hal/CortexM3/cortex_nvic.c new file mode 100644 index 0000000000..d33d7ee94b --- /dev/null +++ b/bsp/smartfusion2/hal/CortexM3/cortex_nvic.c @@ -0,0 +1,209 @@ +/******************************************************************************* + * (c) Copyright 2007-2013 Microsemi SoC Products Group. All rights reserved. + * + * Legacy Actel HAL Cortex NVIC control functions. + * The use of these functions should be replaced by calls to the equivalent + * CMSIS function in your application code. + * + * SVN $Revision: 7375 $ + * SVN $Date: 2015-05-01 19:27:40 +0530 (Fri, 01 May 2015) $ + */ +#include "cortex_nvic.h" +#ifdef MSCC_NO_RELATIVE_PATHS +#include "mss_assert.h" +#else +#include "../../CMSIS/mss_assert.h" +#endif + + +/***************************************************************************//** + * + */ +void NVIC_init( void ) +{ + /* + * Please use the NVIC control functions provided by the SmartFusion2 CMSIS + * Hardware Abstraction Layer. The use of the Actel HAL NVIC control + * functions is obsolete on SmartFusion2 devices. + * + * Simply remove the call to NVIC_init() from your application code. + */ + ASSERT(0); +} + +/***************************************************************************//** + * + */ +void NVIC_set_handler +( + uint32_t interrupt_number, + hal_nvic_irq_handler_t handler +) +{ + /* + * Please use the NVIC control functions provided by the SmartFusion2 CMSIS + * Hardware Abstraction Layer. The use of the Actel HAL NVIC control + * functions is obsolete on SmartFusion2 devices. + * + * Please remove the call to NVIC_set_handler() from your application code + * and provide a function using one of the following function prototypes to + * handle interrupts from peripherals implemeted in the SmartFusion2 FPGA + * fabric: + * - void FabricIrq0_IRQHandler(void) + * - void FabricIrq1_IRQHandler(void) + * - void FabricIrq2_IRQHandler(void) + * - void FabricIrq3_IRQHandler(void) + * - void FabricIrq4_IRQHandler(void) + * - void FabricIrq5_IRQHandler(void) + * - void FabricIrq6_IRQHandler(void) + * - void FabricIrq7_IRQHandler(void) + * - void FabricIrq8_IRQHandler(void) + * - void FabricIrq9_IRQHandler(void) + * - void FabricIrq10_IRQHandler(void) + * - void FabricIrq11_IRQHandler(void) + * - void FabricIrq12_IRQHandler(void) + * - void FabricIrq13_IRQHandler(void) + * - void FabricIrq14_IRQHandler(void) + * - void FabricIrq15_IRQHandler(void) + * The function to implement depends on which MSS_INT_F2M[n] signal is used + * in your Libero design to connect the interrupt signal of the peripheral + * generating the interrupt. + */ + ASSERT(0); +} + +/***************************************************************************//** + * + */ +void NVIC_set_priority +( + uint32_t interrupt_number, + uint8_t priority_level +) +{ + /* + * Please use the NVIC control functions provided by the SmartFusion2 CMSIS + * Hardware Abstraction Layer. The use of the Actel HAL NVIC control + * functions is obsolete on SmartFusion2 devices. + * + * Please replace calls to NVIC_set_priority() with a call to the CMSIS + * void NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority) function where + * IRQn is one of the following values: + * - FabricIrq0_IRQn + * - FabricIrq1_IRQn + * - FabricIrq2_IRQn + * - FabricIrq3_IRQn + * - FabricIrq4_IRQn + * - FabricIrq5_IRQn + * - FabricIrq6_IRQn + * - FabricIrq7_IRQn + * - FabricIrq8_IRQn + * - FabricIrq9_IRQn + * - FabricIrq10_IRQn + * - FabricIrq11_IRQn + * - FabricIrq12_IRQn + * - FabricIrq13_IRQn + * - FabricIrq14_IRQn + * - FabricIrq15_IRQn + */ + ASSERT(0); +} + +/***************************************************************************//** + * + */ +void NVIC_enable_interrupt( uint32_t interrupt_number ) +{ + /* + * Please use the NVIC control functions provided by the SmartFusion2 CMSIS + * Hardware Abstraction Layer. The use of the Actel HAL NVIC control + * functions is obsolete on SmartFusion2 devices. + * + * Please replace calls to NVIC_enable_interrupt() with a call to the CMSIS + * void NVIC_EnableIRQ(IRQn_Type IRQn) function where IRQn is one of the + * following values: + * - FabricIrq0_IRQn + * - FabricIrq1_IRQn + * - FabricIrq2_IRQn + * - FabricIrq3_IRQn + * - FabricIrq4_IRQn + * - FabricIrq5_IRQn + * - FabricIrq6_IRQn + * - FabricIrq7_IRQn + * - FabricIrq8_IRQn + * - FabricIrq9_IRQn + * - FabricIrq10_IRQn + * - FabricIrq11_IRQn + * - FabricIrq12_IRQn + * - FabricIrq13_IRQn + * - FabricIrq14_IRQn + * - FabricIrq15_IRQn + */ + ASSERT(0); +} + +/***************************************************************************//** + * + */ +void NVIC_disable_interrupt( uint32_t interrupt_number ) +{ + /* + * Please use the NVIC control functions provided by the SmartFusion2 CMSIS + * Hardware Abstraction Layer. The use of the Actel HAL NVIC control + * functions is obsolete on SmartFusion2 devices. + * + * Please replace calls to NVIC_disable_interrupt() with a call to the CMSIS + * void NVIC_DisableIRQ(IRQn_Type IRQn) function where IRQn is one of the + * following values: + * - FabricIrq0_IRQn + * - FabricIrq1_IRQn + * - FabricIrq2_IRQn + * - FabricIrq3_IRQn + * - FabricIrq4_IRQn + * - FabricIrq5_IRQn + * - FabricIrq6_IRQn + * - FabricIrq7_IRQn + * - FabricIrq8_IRQn + * - FabricIrq9_IRQn + * - FabricIrq10_IRQn + * - FabricIrq11_IRQn + * - FabricIrq12_IRQn + * - FabricIrq13_IRQn + * - FabricIrq14_IRQn + * - FabricIrq15_IRQn + */ + ASSERT(0); +} + +/***************************************************************************//** + * + */ +void NVIC_clear_interrupt( uint32_t interrupt_number ) +{ + /* + * Please use the NVIC control functions provided by the SmartFusion2 CMSIS + * Hardware Abstraction Layer. The use of the Actel HAL NVIC control + * functions is obsolete on SmartFusion2 devices. + * + * Please replace calls to NVIC_clear_interrupt() with a call to the CMSIS + * void NVIC_ClearPendingIRQ(IRQn_Type IRQn) function where IRQn is one of the + * following values: + * - FabricIrq0_IRQn + * - FabricIrq1_IRQn + * - FabricIrq2_IRQn + * - FabricIrq3_IRQn + * - FabricIrq4_IRQn + * - FabricIrq5_IRQn + * - FabricIrq6_IRQn + * - FabricIrq7_IRQn + * - FabricIrq8_IRQn + * - FabricIrq9_IRQn + * - FabricIrq10_IRQn + * - FabricIrq11_IRQn + * - FabricIrq12_IRQn + * - FabricIrq13_IRQn + * - FabricIrq14_IRQn + * - FabricIrq15_IRQn + */ + ASSERT(0); +} diff --git a/bsp/smartfusion2/hal/CortexM3/cortex_nvic.h b/bsp/smartfusion2/hal/CortexM3/cortex_nvic.h new file mode 100644 index 0000000000..0ddfe9d435 --- /dev/null +++ b/bsp/smartfusion2/hal/CortexM3/cortex_nvic.h @@ -0,0 +1,56 @@ +/******************************************************************************* + * (c) Copyright 2007-2013 Microsemi SoC Products Group. All rights reserved. + * + * Legacy Actel HAL Cortex NVIC control functions. + * The use of these functions should be replaced by calls to the equivalent + * CMSIS function in your application code. + * + * SVN $Revision: 5257 $ + * SVN $Date: 2013-03-21 17:54:10 +0530 (Thu, 21 Mar 2013) $ + */ +#ifndef CORTEX_NVIC_H_ +#define CORTEX_NVIC_H_ + +#include <stdint.h> + +typedef void (*hal_nvic_irq_handler_t)(void); + +/*------------------------------------------------------------------------------ + * + */ +void NVIC_init( void ); + +/*------------------------------------------------------------------------------ + * + */ +void NVIC_set_handler +( + uint32_t interrupt_number, + hal_nvic_irq_handler_t handler +); + +/*------------------------------------------------------------------------------ + * + */ +void NVIC_set_priority +( + uint32_t interrupt_number, + uint8_t priority_level +); + +/*------------------------------------------------------------------------------ + * + */ +void NVIC_enable_interrupt( uint32_t interrupt_number ); + +/*------------------------------------------------------------------------------ + * + */ +void NVIC_disable_interrupt( uint32_t interrupt_number ); + +/*------------------------------------------------------------------------------ + * + */ +void NVIC_clear_interrupt( uint32_t interrupt_number ); + +#endif /*CORTEX_NVIC_H_*/ diff --git a/bsp/smartfusion2/hal/hal.h b/bsp/smartfusion2/hal/hal.h new file mode 100644 index 0000000000..20f60329fb --- /dev/null +++ b/bsp/smartfusion2/hal/hal.h @@ -0,0 +1,206 @@ +/***************************************************************************//** + * (c) Copyright 2007-2013 Microsemi SoC Products Group. All rights reserved. + * + * Hardware abstraction layer functions. + * + * SVN $Revision: 5258 $ + * SVN $Date: 2013-03-21 18:11:02 +0530 (Thu, 21 Mar 2013) $ + */ +#ifndef HAL_H_ +#define HAL_H_ + +#include "cpu_types.h" +#include "hw_reg_access.h" + +/***************************************************************************//** + * Enable all interrupts at the processor level. + */ +void HAL_enable_interrupts( void ); + +/***************************************************************************//** + * Disable all interrupts at the processor core level. + * Return the interrupts enable state before disabling occured so that it can + * later be restored. + */ +psr_t HAL_disable_interrupts( void ); + +/***************************************************************************//** + * Restore the interrupts enable state at the processor core level. + * This function is normally passed the value returned from a previous call to + * HAL_disable_interrupts(). + */ +void HAL_restore_interrupts( psr_t saved_psr ); + +/***************************************************************************//** + */ +#define FIELD_OFFSET(FIELD_NAME) (FIELD_NAME##_OFFSET) +#define FIELD_SHIFT(FIELD_NAME) (FIELD_NAME##_SHIFT) +#define FIELD_MASK(FIELD_NAME) (FIELD_NAME##_MASK) + +/***************************************************************************//** + * The macro HAL_set_32bit_reg() allows writing a 32 bits wide register. + * + * BASE_ADDR: A variable of type addr_t specifying the base address of the + * peripheral containing the register. + * REG_NAME: A string identifying the register to write. These strings are + * specified in a header file associated with the peripheral. + * VALUE: A variable of type uint32_t containing the value to write. + */ +#define HAL_set_32bit_reg(BASE_ADDR, REG_NAME, VALUE) \ + (HW_set_32bit_reg( ((BASE_ADDR) + (REG_NAME##_REG_OFFSET)), (VALUE) )) + +/***************************************************************************//** + * The macro HAL_get_32bit_reg() is used to read the value of a 32 bits wide + * register. + * + * BASE_ADDR: A variable of type addr_t specifying the base address of the + * peripheral containing the register. + * REG_NAME: A string identifying the register to read. These strings are + * specified in a header file associated with the peripheral. + * RETURN: This function-like macro returns a uint32_t value. + */ +#define HAL_get_32bit_reg(BASE_ADDR, REG_NAME) \ + (HW_get_32bit_reg( ((BASE_ADDR) + (REG_NAME##_REG_OFFSET)) )) + +/***************************************************************************//** + * The macro HAL_set_32bit_reg_field() is used to write a field within a + * 32 bits wide register. The field written can be one or more bits. + * + * BASE_ADDR: A variable of type addr_t specifying the base address of the + * peripheral containing the register. + * FIELD_NAME: A string identifying the register field to write. These strings + * are specified in a header file associated with the peripheral. + * VALUE: A variable of type uint32_t containing the field value to write. + */ +#define HAL_set_32bit_reg_field(BASE_ADDR, FIELD_NAME, VALUE) \ + (HW_set_32bit_reg_field(\ + (BASE_ADDR) + FIELD_OFFSET(FIELD_NAME),\ + FIELD_SHIFT(FIELD_NAME),\ + FIELD_MASK(FIELD_NAME),\ + (VALUE))) + +/***************************************************************************//** + * The macro HAL_get_32bit_reg_field() is used to read a register field from + * within a 32 bit wide peripheral register. The field can be one or more bits. + * + * BASE_ADDR: A variable of type addr_t specifying the base address of the + * peripheral containing the register. + * FIELD_NAME: A string identifying the register field to write. These strings + * are specified in a header file associated with the peripheral. + * RETURN: This function-like macro returns a uint32_t value. + */ +#define HAL_get_32bit_reg_field(BASE_ADDR, FIELD_NAME) \ + (HW_get_32bit_reg_field(\ + (BASE_ADDR) + FIELD_OFFSET(FIELD_NAME),\ + FIELD_SHIFT(FIELD_NAME),\ + FIELD_MASK(FIELD_NAME))) + +/***************************************************************************//** + * The macro HAL_set_16bit_reg() allows writing a 16 bits wide register. + * + * BASE_ADDR: A variable of type addr_t specifying the base address of the + * peripheral containing the register. + * REG_NAME: A string identifying the register to write. These strings are + * specified in a header file associated with the peripheral. + * VALUE: A variable of type uint_fast16_t containing the value to write. + */ +#define HAL_set_16bit_reg(BASE_ADDR, REG_NAME, VALUE) \ + (HW_set_16bit_reg( ((BASE_ADDR) + (REG_NAME##_REG_OFFSET)), (VALUE) )) + +/***************************************************************************//** + * The macro HAL_get_16bit_reg() is used to read the value of a 16 bits wide + * register. + * + * BASE_ADDR: A variable of type addr_t specifying the base address of the + * peripheral containing the register. + * REG_NAME: A string identifying the register to read. These strings are + * specified in a header file associated with the peripheral. + * RETURN: This function-like macro returns a uint16_t value. + */ +#define HAL_get_16bit_reg(BASE_ADDR, REG_NAME) \ + (HW_get_16bit_reg( (BASE_ADDR) + (REG_NAME##_REG_OFFSET) )) + +/***************************************************************************//** + * The macro HAL_set_16bit_reg_field() is used to write a field within a + * 16 bits wide register. The field written can be one or more bits. + * + * BASE_ADDR: A variable of type addr_t specifying the base address of the + * peripheral containing the register. + * FIELD_NAME: A string identifying the register field to write. These strings + * are specified in a header file associated with the peripheral. + * VALUE: A variable of type uint16_t containing the field value to write. + */ +#define HAL_set_16bit_reg_field(BASE_ADDR, FIELD_NAME, VALUE) \ + (HW_set_16bit_reg_field(\ + (BASE_ADDR) + FIELD_OFFSET(FIELD_NAME),\ + FIELD_SHIFT(FIELD_NAME),\ + FIELD_MASK(FIELD_NAME),\ + (VALUE))) + +/***************************************************************************//** + * The macro HAL_get_16bit_reg_field() is used to read a register field from + * within a 8 bit wide peripheral register. The field can be one or more bits. + * + * BASE_ADDR: A variable of type addr_t specifying the base address of the + * peripheral containing the register. + * FIELD_NAME: A string identifying the register field to write. These strings + * are specified in a header file associated with the peripheral. + * RETURN: This function-like macro returns a uint16_t value. + */ +#define HAL_get_16bit_reg_field(BASE_ADDR, FIELD_NAME) \ + (HW_get_16bit_reg_field(\ + (BASE_ADDR) + FIELD_OFFSET(FIELD_NAME),\ + FIELD_SHIFT(FIELD_NAME),\ + FIELD_MASK(FIELD_NAME))) + +/***************************************************************************//** + * The macro HAL_set_8bit_reg() allows writing a 8 bits wide register. + * + * BASE_ADDR: A variable of type addr_t specifying the base address of the + * peripheral containing the register. + * REG_NAME: A string identifying the register to write. These strings are + * specified in a header file associated with the peripheral. + * VALUE: A variable of type uint_fast8_t containing the value to write. + */ +#define HAL_set_8bit_reg(BASE_ADDR, REG_NAME, VALUE) \ + (HW_set_8bit_reg( ((BASE_ADDR) + (REG_NAME##_REG_OFFSET)), (VALUE) )) + +/***************************************************************************//** + * The macro HAL_get_8bit_reg() is used to read the value of a 8 bits wide + * register. + * + * BASE_ADDR: A variable of type addr_t specifying the base address of the + * peripheral containing the register. + * REG_NAME: A string identifying the register to read. These strings are + * specified in a header file associated with the peripheral. + * RETURN: This function-like macro returns a uint8_t value. + */ +#define HAL_get_8bit_reg(BASE_ADDR, REG_NAME) \ + (HW_get_8bit_reg( (BASE_ADDR) + (REG_NAME##_REG_OFFSET) )) + +/***************************************************************************//** + */ +#define HAL_set_8bit_reg_field(BASE_ADDR, FIELD_NAME, VALUE) \ + (HW_set_8bit_reg_field(\ + (BASE_ADDR) + FIELD_OFFSET(FIELD_NAME),\ + FIELD_SHIFT(FIELD_NAME),\ + FIELD_MASK(FIELD_NAME),\ + (VALUE))) + +/***************************************************************************//** + * The macro HAL_get_8bit_reg_field() is used to read a register field from + * within a 8 bit wide peripheral register. The field can be one or more bits. + * + * BASE_ADDR: A variable of type addr_t specifying the base address of the + * peripheral containing the register. + * FIELD_NAME: A string identifying the register field to write. These strings + * are specified in a header file associated with the peripheral. + * RETURN: This function-like macro returns a uint8_t value. + */ +#define HAL_get_8bit_reg_field(BASE_ADDR, FIELD_NAME) \ + (HW_get_8bit_reg_field(\ + (BASE_ADDR) + FIELD_OFFSET(FIELD_NAME),\ + FIELD_SHIFT(FIELD_NAME),\ + FIELD_MASK(FIELD_NAME))) + +#endif /*HAL_H_*/ diff --git a/bsp/smartfusion2/hal/hal_assert.h b/bsp/smartfusion2/hal/hal_assert.h new file mode 100644 index 0000000000..f74144c39b --- /dev/null +++ b/bsp/smartfusion2/hal/hal_assert.h @@ -0,0 +1,34 @@ +/******************************************************************************* + * (c) Copyright 2008-2013 Microsemi SoC Products Group. All rights reserved. + * + * SVN $Revision: 7375 $ + * SVN $Date: 2015-05-01 19:27:40 +0530 (Fri, 01 May 2015) $ + */ +#ifndef HAL_ASSERT_HEADER +#define HAL_ASSERT_HEADER + +#ifdef MSCC_NO_RELATIVE_PATHS +#include "mss_assert.h" +#else +#include "../CMSIS/mss_assert.h" +#endif + +#if defined(NDEBUG) +/***************************************************************************//** + * HAL_ASSERT() is defined out when the NDEBUG symbol is used. + ******************************************************************************/ +#define HAL_ASSERT(CHECK) + +#else +/***************************************************************************//** + * Default behaviour for HAL_ASSERT() macro: + *------------------------------------------------------------------------------ + * Using the HAL_ASSERT() macro is the same as directly using the SmartFusion2 + * CMSIS ASSERT() macro. The behaviour is toolchain specific and project + * setting specific. + ******************************************************************************/ +#define HAL_ASSERT(CHECK) ASSERT(CHECK); + +#endif /* NDEBUG */ + +#endif /* HAL_ASSERT_HEADER */ diff --git a/bsp/smartfusion2/hal/hw_reg_access.h b/bsp/smartfusion2/hal/hw_reg_access.h new file mode 100644 index 0000000000..8ae672212e --- /dev/null +++ b/bsp/smartfusion2/hal/hw_reg_access.h @@ -0,0 +1,227 @@ +/***************************************************************************//** + * (c) Copyright 2007-2013 Microsemi SoC Products Group. All rights reserved. + * + * Hardware registers access functions. + * The implementation of these function is platform and toolchain specific. + * The functions declared here are implemented using assembler as part of the + * processor/toolchain specific HAL. + * + * SVN $Revision: 5258 $ + * SVN $Date: 2013-03-21 18:11:02 +0530 (Thu, 21 Mar 2013) $ + */ +#ifndef HW_REG_ACCESS +#define HW_REG_ACCESS + +/***************************************************************************//** + * HW_set_32bit_reg is used to write the content of a 32 bits wide peripheral + * register. + * + * @param reg_addr Address in the processor's memory map of the register to + * write. + * @param value Value to be written into the peripheral register. + */ +void +HW_set_32bit_reg +( + addr_t reg_addr, + uint32_t value +); + +/***************************************************************************//** + * HW_get_32bit_reg is used to read the content of a 32 bits wide peripheral + * register. + * + * @param reg_addr Address in the processor's memory map of the register to + * read. + * @return 32 bits value read from the peripheral register. + */ +uint32_t +HW_get_32bit_reg +( + addr_t reg_addr +); + +/***************************************************************************//** + * HW_set_32bit_reg_field is used to set the content of a field in a 32 bits + * wide peripheral register. + * + * @param reg_addr Address in the processor's memory map of the register to + * be written. + * @param shift Bit offset of the register field to be read within the + * register. + * @param mask Bit mask to be applied to the raw register value to filter + * out the other register fields values. + * @param value Value to be written in the specified field. + */ +void +HW_set_32bit_reg_field +( + addr_t reg_addr, + int_fast8_t shift, + uint32_t mask, + uint32_t value +); + +/***************************************************************************//** + * HW_get_32bit_reg_field is used to read the content of a field out of a + * 32 bits wide peripheral register. + * + * @param reg_addr Address in the processor's memory map of the register to + * read. + * @param shift Bit offset of the register field to be written within the + * register. + * @param mask Bit mask to be applied to the raw register value to filter + * out the other register fields values. + * + * @return 32 bits value containing the register field value specified + * as parameter. + */ +uint32_t +HW_get_32bit_reg_field +( + addr_t reg_addr, + int_fast8_t shift, + uint32_t mask +); + +/***************************************************************************//** + * HW_set_16bit_reg is used to write the content of a 16 bits wide peripheral + * register. + * + * @param reg_addr Address in the processor's memory map of the register to + * write. + * @param value Value to be written into the peripheral register. + */ +void +HW_set_16bit_reg +( + addr_t reg_addr, + uint_fast16_t value +); + +/***************************************************************************//** + * HW_get_16bit_reg is used to read the content of a 16 bits wide peripheral + * register. + * + * @param reg_addr Address in the processor's memory map of the register to + * read. + * @return 16 bits value read from the peripheral register. + */ +uint16_t +HW_get_16bit_reg +( + addr_t reg_addr +); + +/***************************************************************************//** + * HW_set_16bit_reg_field is used to set the content of a field in a 16 bits + * wide peripheral register. + * + * @param reg_addr Address in the processor's memory map of the register to + * be written. + * @param shift Bit offset of the register field to be read within the + * register. + * @param mask Bit mask to be applied to the raw register value to filter + * out the other register fields values. + * @param value Value to be written in the specified field. + */ +void HW_set_16bit_reg_field +( + addr_t reg_addr, + int_fast8_t shift, + uint_fast16_t mask, + uint_fast16_t value +); + +/***************************************************************************//** + * HW_get_16bit_reg_field is used to read the content of a field from a + * 16 bits wide peripheral register. + * + * @param reg_addr Address in the processor's memory map of the register to + * read. + * @param shift Bit offset of the register field to be written within the + * register. + * @param mask Bit mask to be applied to the raw register value to filter + * out the other register fields values. + * + * @return 16 bits value containing the register field value specified + * as parameter. + */ +uint16_t HW_get_16bit_reg_field +( + addr_t reg_addr, + int_fast8_t shift, + uint_fast16_t mask +); + +/***************************************************************************//** + * HW_set_8bit_reg is used to write the content of a 8 bits wide peripheral + * register. + * + * @param reg_addr Address in the processor's memory map of the register to + * write. + * @param value Value to be written into the peripheral register. + */ +void +HW_set_8bit_reg +( + addr_t reg_addr, + uint_fast8_t value +); + +/***************************************************************************//** + * HW_get_8bit_reg is used to read the content of a 8 bits wide peripheral + * register. + * + * @param reg_addr Address in the processor's memory map of the register to + * read. + * @return 8 bits value read from the peripheral register. + */ +uint8_t +HW_get_8bit_reg +( + addr_t reg_addr +); + +/***************************************************************************//** + * HW_set_8bit_reg_field is used to set the content of a field in a 8 bits + * wide peripheral register. + * + * @param reg_addr Address in the processor's memory map of the register to + * be written. + * @param shift Bit offset of the register field to be read within the + * register. + * @param mask Bit mask to be applied to the raw register value to filter + * out the other register fields values. + * @param value Value to be written in the specified field. + */ +void HW_set_8bit_reg_field +( + addr_t reg_addr, + int_fast8_t shift, + uint_fast8_t mask, + uint_fast8_t value +); + +/***************************************************************************//** + * HW_get_8bit_reg_field is used to read the content of a field from a + * 8 bits wide peripheral register. + * + * @param reg_addr Address in the processor's memory map of the register to + * read. + * @param shift Bit offset of the register field to be written within the + * register. + * @param mask Bit mask to be applied to the raw register value to filter + * out the other register fields values. + * + * @return 16 bits value containing the register field value specified + * as parameter. + */ +uint8_t HW_get_8bit_reg_field +( + addr_t reg_addr, + int_fast8_t shift, + uint_fast8_t mask +); + +#endif /* HW_REG_ACCESS */ diff --git a/bsp/smartfusion2/libraries/mss_gpio/mss_gpio.c b/bsp/smartfusion2/libraries/mss_gpio/mss_gpio.c new file mode 100644 index 0000000000..11dbc21fee --- /dev/null +++ b/bsp/smartfusion2/libraries/mss_gpio/mss_gpio.c @@ -0,0 +1,298 @@ +/******************************************************************************* + * (c) Copyright 2008-2015 Microsemi SoC Products Group. All rights reserved. + * + * SmartFusion2 microcontroller subsystem GPIO bare metal driver implementation. + * + * SVN $Revision: 7749 $ + * SVN $Date: 2015-09-04 14:32:09 +0530 (Fri, 04 Sep 2015) $ + */ +#include "mss_gpio.h" +#include "../../CMSIS/mss_assert.h" + +#ifdef __cplusplus +extern "C" { +#endif + +/*-------------------------------------------------------------------------*//** + * Defines. + */ +#define GPIO_INT_ENABLE_MASK ((uint32_t)0x00000008uL) +#define OUTPUT_BUFFER_ENABLE_MASK 0x00000004u + +#define NB_OF_GPIO ((uint32_t)32) + +/*-------------------------------------------------------------------------*//** + * Lookup table of GPIO configuration registers address indexed on GPIO ID. + */ +static uint32_t volatile * const g_config_reg_lut[NB_OF_GPIO] = +{ + &(GPIO->GPIO_0_CFG), + &(GPIO->GPIO_1_CFG), + &(GPIO->GPIO_2_CFG), + &(GPIO->GPIO_3_CFG), + &(GPIO->GPIO_4_CFG), + &(GPIO->GPIO_5_CFG), + &(GPIO->GPIO_6_CFG), + &(GPIO->GPIO_7_CFG), + &(GPIO->GPIO_8_CFG), + &(GPIO->GPIO_9_CFG), + &(GPIO->GPIO_10_CFG), + &(GPIO->GPIO_11_CFG), + &(GPIO->GPIO_12_CFG), + &(GPIO->GPIO_13_CFG), + &(GPIO->GPIO_14_CFG), + &(GPIO->GPIO_15_CFG), + &(GPIO->GPIO_16_CFG), + &(GPIO->GPIO_17_CFG), + &(GPIO->GPIO_18_CFG), + &(GPIO->GPIO_19_CFG), + &(GPIO->GPIO_20_CFG), + &(GPIO->GPIO_21_CFG), + &(GPIO->GPIO_22_CFG), + &(GPIO->GPIO_23_CFG), + &(GPIO->GPIO_24_CFG), + &(GPIO->GPIO_25_CFG), + &(GPIO->GPIO_26_CFG), + &(GPIO->GPIO_27_CFG), + &(GPIO->GPIO_28_CFG), + &(GPIO->GPIO_29_CFG), + &(GPIO->GPIO_30_CFG), + &(GPIO->GPIO_31_CFG) +}; + +/*-------------------------------------------------------------------------*//** + * Lookup table of Cortex-M3 GPIO interrupt number indexed on GPIO ID. + */ +static const IRQn_Type g_gpio_irqn_lut[NB_OF_GPIO] = +{ + GPIO0_IRQn, + GPIO1_IRQn, + GPIO2_IRQn, + GPIO3_IRQn, + GPIO4_IRQn, + GPIO5_IRQn, + GPIO6_IRQn, + GPIO7_IRQn, + GPIO8_IRQn, + GPIO9_IRQn, + GPIO10_IRQn, + GPIO11_IRQn, + GPIO12_IRQn, + GPIO13_IRQn, + GPIO14_IRQn, + GPIO15_IRQn, + GPIO16_IRQn, + GPIO17_IRQn, + GPIO18_IRQn, + GPIO19_IRQn, + GPIO20_IRQn, + GPIO21_IRQn, + GPIO22_IRQn, + GPIO23_IRQn, + GPIO24_IRQn, + GPIO25_IRQn, + GPIO26_IRQn, + GPIO27_IRQn, + GPIO28_IRQn, + GPIO29_IRQn, + GPIO30_IRQn, + GPIO31_IRQn +}; + +/*-------------------------------------------------------------------------*//** + * MSS_GPIO_init + * See "mss_gpio.h" for details of how to use this function. + */ +void MSS_GPIO_init( void ) +{ + uint32_t inc; + + /* reset MSS GPIO hardware */ + SYSREG->SOFT_RST_CR |= SYSREG_GPIO_SOFTRESET_MASK; + SYSREG->SOFT_RST_CR |= (SYSREG_GPIO_7_0_SOFTRESET_MASK | + SYSREG_GPIO_15_8_SOFTRESET_MASK | + SYSREG_GPIO_23_16_SOFTRESET_MASK | + SYSREG_GPIO_31_24_SOFTRESET_MASK); + + /* Clear any previously pended MSS GPIO interrupt */ + for(inc = 0U; inc < NB_OF_GPIO; ++inc) + { + NVIC_DisableIRQ(g_gpio_irqn_lut[inc]); + NVIC_ClearPendingIRQ(g_gpio_irqn_lut[inc]); + } + /* Take MSS GPIO hardware out of reset. */ + SYSREG->SOFT_RST_CR &= ~(SYSREG_GPIO_7_0_SOFTRESET_MASK | + SYSREG_GPIO_15_8_SOFTRESET_MASK | + SYSREG_GPIO_23_16_SOFTRESET_MASK | + SYSREG_GPIO_31_24_SOFTRESET_MASK); + SYSREG->SOFT_RST_CR &= ~SYSREG_GPIO_SOFTRESET_MASK; +} + +/*-------------------------------------------------------------------------*//** + * MSS_GPIO_config + * See "mss_gpio.h" for details of how to use this function. + */ +void MSS_GPIO_config +( + mss_gpio_id_t port_id, + uint32_t config +) +{ + uint32_t gpio_idx = (uint32_t)port_id; + + ASSERT(gpio_idx < NB_OF_GPIO); + + if(gpio_idx < NB_OF_GPIO) + { + *(g_config_reg_lut[gpio_idx]) = config; + } +} + +/*-------------------------------------------------------------------------*//** + * MSS_GPIO_set_output + * See "mss_gpio.h" for details of how to use this function. + */ +void MSS_GPIO_set_output +( + mss_gpio_id_t port_id, + uint8_t value +) +{ + uint32_t gpio_setting; + uint32_t gpio_idx = (uint32_t)port_id; + + ASSERT(gpio_idx < NB_OF_GPIO); + + if(gpio_idx < NB_OF_GPIO) + { + gpio_setting = GPIO->GPIO_OUT; + gpio_setting &= ~((uint32_t)0x01u << gpio_idx); + gpio_setting |= ((uint32_t)value & 0x01u) << gpio_idx; + GPIO->GPIO_OUT = gpio_setting; + } +} + +/*-------------------------------------------------------------------------*//** + * MSS_GPIO_drive_inout + * See "mss_gpio.h" for details of how to use this function. + */ +void MSS_GPIO_drive_inout +( + mss_gpio_id_t port_id, + mss_gpio_inout_state_t inout_state +) +{ + uint32_t outputs_state; + uint32_t config; + uint32_t gpio_idx = (uint32_t)port_id; + + ASSERT(gpio_idx < NB_OF_GPIO); + + if(gpio_idx < NB_OF_GPIO) + { + switch(inout_state) + { + case MSS_GPIO_DRIVE_HIGH: + /* Set output high */ + outputs_state = GPIO->GPIO_OUT; + outputs_state |= (uint32_t)1 << gpio_idx; + GPIO->GPIO_OUT = outputs_state; + /* Enable output buffer */ + config = *(g_config_reg_lut[gpio_idx]); + config |= OUTPUT_BUFFER_ENABLE_MASK; + *(g_config_reg_lut[gpio_idx]) = config; + break; + + case MSS_GPIO_DRIVE_LOW: + /* Set output low */ + outputs_state = GPIO->GPIO_OUT; + outputs_state &= ~((uint32_t)((uint32_t)1 << gpio_idx)); + GPIO->GPIO_OUT = outputs_state; + /* Enable output buffer */ + config = *(g_config_reg_lut[gpio_idx]); + config |= OUTPUT_BUFFER_ENABLE_MASK; + *(g_config_reg_lut[gpio_idx]) = config; + break; + + case MSS_GPIO_HIGH_Z: + /* Disable output buffer */ + config = *(g_config_reg_lut[gpio_idx]); + config &= ~OUTPUT_BUFFER_ENABLE_MASK; + *(g_config_reg_lut[gpio_idx]) = config; + break; + + default: + ASSERT(0); + break; + } + } +} + +/*-------------------------------------------------------------------------*//** + * MSS_GPIO_enable_irq + * See "mss_gpio.h" for details of how to use this function. + */ +void MSS_GPIO_enable_irq +( + mss_gpio_id_t port_id +) +{ + uint32_t cfg_value; + uint32_t gpio_idx = (uint32_t)port_id; + + ASSERT(gpio_idx < NB_OF_GPIO); + + if(gpio_idx < NB_OF_GPIO) + { + cfg_value = *(g_config_reg_lut[gpio_idx]); + *(g_config_reg_lut[gpio_idx]) = (cfg_value | GPIO_INT_ENABLE_MASK); + NVIC_EnableIRQ(g_gpio_irqn_lut[gpio_idx]); + } +} + +/*-------------------------------------------------------------------------*//** + * MSS_GPIO_disable_irq + * See "mss_gpio.h" for details of how to use this function. + */ +void MSS_GPIO_disable_irq +( + mss_gpio_id_t port_id +) +{ + uint32_t cfg_value; + uint32_t gpio_idx = (uint32_t)port_id; + + ASSERT(gpio_idx < NB_OF_GPIO); + + if(gpio_idx < NB_OF_GPIO) + { + cfg_value = *(g_config_reg_lut[gpio_idx]); + *(g_config_reg_lut[gpio_idx]) = (cfg_value & ~GPIO_INT_ENABLE_MASK); + } +} + +/*-------------------------------------------------------------------------*//** + * MSS_GPIO_clear_irq + * See "mss_gpio.h" for details of how to use this function. + */ +void MSS_GPIO_clear_irq +( + mss_gpio_id_t port_id +) +{ + uint32_t gpio_idx = (uint32_t)port_id; + + ASSERT(gpio_idx < NB_OF_GPIO); + + if(gpio_idx < NB_OF_GPIO) + { + GPIO->GPIO_IRQ = ((uint32_t)1) << gpio_idx; + } + __ASM volatile ("dsb"); + +} + +#ifdef __cplusplus +} +#endif + diff --git a/bsp/smartfusion2/libraries/mss_gpio/mss_gpio.h b/bsp/smartfusion2/libraries/mss_gpio/mss_gpio.h new file mode 100644 index 0000000000..58c98f8556 --- /dev/null +++ b/bsp/smartfusion2/libraries/mss_gpio/mss_gpio.h @@ -0,0 +1,507 @@ +/******************************************************************************* + * (c) Copyright 2008-2015 Microsemi SoC Products Group. All rights reserved. + * + * SmartFusion2 Microcontroller Subsystem GPIO bare metal software driver public + * API. + * + * SVN $Revision: 7748 $ + * SVN $Date: 2015-09-04 11:36:30 +0530 (Fri, 04 Sep 2015) $ + */ + +/*=========================================================================*//** + @mainpage SmartFusion2 MSS GPIO Bare Metal Driver. + + @section intro_sec Introduction + The SmartFusion2 Microcontroller Subsystem (MSS) includes a block of 32 general + purpose input/outputs (GPIO). + This software driver provides a set of functions for controlling the MSS GPIO + block as part of a bare metal system where no operating system is available. + This driver can be adapted for use as part of an operating system but the + implementation of the adaptation layer between this driver and the operating + system's driver model is outside the scope of this driver. + + @section hw_dependencies Hardware Flow Dependencies + The configuration of all features of the MSS GPIOs is covered by this driver + with the exception of the SmartFusion2 IOMUX configuration. SmartFusion2 + allows multiple non-concurrent uses of some external pins through IOMUX + configuration. This feature allows optimization of external pin usage by + assigning external pins for use by either the microcontroller subsystem or the + FPGA fabric. The MSS GPIOs share SmartFusion2 device external pins with the + FPGA fabric and with other MSS peripherals via an IOMUX. The MSS GPIO ports + can alternatively be routed to the FPGA fabric through an IOMUX. + The IOMUXs are configured using the SmartFusion2 MSS configurator tool. You + must ensure that the MSS GPIOs are enabled and configured in the SmartFusion2 + MSS configurator if you wish to use them. For more information on IOMUXs, + refer to the IOMUX section of the SmartFusion2 Microcontroller Subsystem (MSS) + User’s Guide. + The base address, register addresses and interrupt number assignment for the + MSS GPIO block are defined as constants in the SmartFusion2 CMSIS HAL. You + must ensure that the latest SmartFusion2 CMSIS HAL is included in the project + settings of the software tool chain used to build your project and that it is + generated into your project. + + @section theory_op Theory of Operation + The MSS GPIO driver functions are grouped into the following categories: + - Initialization + - Configuration + - Reading and setting GPIO state + - Interrupt control + + Initialization + The MSS GPIO driver is initialized through a call to the MSS_GPIO_init() + function. The MSS_GPIO_init() function must be called before any other MSS + GPIO driver functions can be called. + + Configuration + Each GPIO port is individually configured through a call to the + MSS_GPIO_config() function. Configuration includes deciding if a GPIO port + will be used as an input, an output or both. GPIO ports configured as inputs + can be further configured to generate interrupts based on the input's state. + Interrupts can be level or edge sensitive. + + Reading and Setting GPIO State + The state of the GPIO ports can be read and set using the following functions: + - MSS_GPIO_get_inputs() + - MSS_GPIO_get_outputs() + - MSS_GPIO_set_outputs() + - MSS_GPIO_set_output() + - MSS_GPIO_drive_inout() + + Interrupt Control + Interrupts generated by GPIO ports configured as inputs are controlled using + the following functions: + - MSS_GPIO_enable_irq() + - MSS_GPIO_disable_irq() + - MSS_GPIO_clear_irq() + + *//*=========================================================================*/ +#ifndef MSS_GPIO_H_ +#define MSS_GPIO_H_ + +#ifdef __cplusplus +extern "C" { +#endif + +#include "../../CMSIS/m2sxxx.h" + +/*-------------------------------------------------------------------------*//** + The mss_gpio_id_t enumeration is used to identify individual GPIO ports as an + argument to functions: + - MSS_GPIO_config() + - MSS_GPIO_set_output() and MSS_GPIO_drive_inout() + - MSS_GPIO_enable_irq(), MSS_GPIO_disable_irq() and MSS_GPIO_clear_irq() + */ +typedef enum __mss_gpio_id_t +{ + MSS_GPIO_0 = 0, + MSS_GPIO_1 = 1, + MSS_GPIO_2 = 2, + MSS_GPIO_3 = 3, + MSS_GPIO_4 = 4, + MSS_GPIO_5 = 5, + MSS_GPIO_6 = 6, + MSS_GPIO_7 = 7, + MSS_GPIO_8 = 8, + MSS_GPIO_9 = 9, + MSS_GPIO_10 = 10, + MSS_GPIO_11 = 11, + MSS_GPIO_12 = 12, + MSS_GPIO_13 = 13, + MSS_GPIO_14 = 14, + MSS_GPIO_15 = 15, + MSS_GPIO_16 = 16, + MSS_GPIO_17 = 17, + MSS_GPIO_18 = 18, + MSS_GPIO_19 = 19, + MSS_GPIO_20 = 20, + MSS_GPIO_21 = 21, + MSS_GPIO_22 = 22, + MSS_GPIO_23 = 23, + MSS_GPIO_24 = 24, + MSS_GPIO_25 = 25, + MSS_GPIO_26 = 26, + MSS_GPIO_27 = 27, + MSS_GPIO_28 = 28, + MSS_GPIO_29 = 29, + MSS_GPIO_30 = 30, + MSS_GPIO_31 = 31 +} mss_gpio_id_t; + +/*-------------------------------------------------------------------------*//** + These constant definitions are used as an argument to the + MSS_GPIO_set_outputs() function to identify GPIO ports. A logical OR of these + constants can be used to specify multiple GPIO ports. + These definitions can also be used to identify GPIO ports through logical + operations on the return value of the MSS_GPIO_get_inputs() function. + */ +#define MSS_GPIO_0_MASK 0x00000001uL +#define MSS_GPIO_1_MASK 0x00000002uL +#define MSS_GPIO_2_MASK 0x00000004uL +#define MSS_GPIO_3_MASK 0x00000008uL +#define MSS_GPIO_4_MASK 0x00000010uL +#define MSS_GPIO_5_MASK 0x00000020uL +#define MSS_GPIO_6_MASK 0x00000040uL +#define MSS_GPIO_7_MASK 0x00000080uL +#define MSS_GPIO_8_MASK 0x00000100uL +#define MSS_GPIO_9_MASK 0x00000200uL +#define MSS_GPIO_10_MASK 0x00000400uL +#define MSS_GPIO_11_MASK 0x00000800uL +#define MSS_GPIO_12_MASK 0x00001000uL +#define MSS_GPIO_13_MASK 0x00002000uL +#define MSS_GPIO_14_MASK 0x00004000uL +#define MSS_GPIO_15_MASK 0x00008000uL +#define MSS_GPIO_16_MASK 0x00010000uL +#define MSS_GPIO_17_MASK 0x00020000uL +#define MSS_GPIO_18_MASK 0x00040000uL +#define MSS_GPIO_19_MASK 0x00080000uL +#define MSS_GPIO_20_MASK 0x00100000uL +#define MSS_GPIO_21_MASK 0x00200000uL +#define MSS_GPIO_22_MASK 0x00400000uL +#define MSS_GPIO_23_MASK 0x00800000uL +#define MSS_GPIO_24_MASK 0x01000000uL +#define MSS_GPIO_25_MASK 0x02000000uL +#define MSS_GPIO_26_MASK 0x04000000uL +#define MSS_GPIO_27_MASK 0x08000000uL +#define MSS_GPIO_28_MASK 0x10000000uL +#define MSS_GPIO_29_MASK 0x20000000uL +#define MSS_GPIO_30_MASK 0x40000000uL +#define MSS_GPIO_31_MASK 0x80000000uL + +/*-------------------------------------------------------------------------*//** + These constant definitions are used as an argument to the MSS_GPIO_config() + function to specify the I/O mode of each GPIO port. + */ +#define MSS_GPIO_INPUT_MODE 0x0000000002uL +#define MSS_GPIO_OUTPUT_MODE 0x0000000005uL +#define MSS_GPIO_INOUT_MODE 0x0000000003uL + +/*-------------------------------------------------------------------------*//** + These constant definitions are used as an argument to the MSS_GPIO_config() + function to specify the interrupt mode of each GPIO port. + */ +#define MSS_GPIO_IRQ_LEVEL_HIGH 0x0000000000uL +#define MSS_GPIO_IRQ_LEVEL_LOW 0x0000000020uL +#define MSS_GPIO_IRQ_EDGE_POSITIVE 0x0000000040uL +#define MSS_GPIO_IRQ_EDGE_NEGATIVE 0x0000000060uL +#define MSS_GPIO_IRQ_EDGE_BOTH 0x0000000080uL + +/*-------------------------------------------------------------------------*//** + The mss_gpio_inout_state_t enumeration is used to specify the output state of + an INOUT GPIO port as an argument to the MSS_GPIO_drive_inout() function. + */ +typedef enum mss_gpio_inout_state +{ + MSS_GPIO_DRIVE_LOW = 0, + MSS_GPIO_DRIVE_HIGH, + MSS_GPIO_HIGH_Z +} mss_gpio_inout_state_t; + +/*-------------------------------------------------------------------------*//** + The MSS_GPIO_init() function initializes the SmartFusion2 MSS GPIO block. It + resets the MSS GPIO hardware block and it also clears any pending MSS GPIO + interrupts in the ARM Cortex-M3 interrupt controller. When the function exits, + it takes the MSS GPIO block out of reset. + + @param + This function has no parameters. + + @return + This function does not return a value. + */ +void MSS_GPIO_init( void ); + +/*-------------------------------------------------------------------------*//** + The MSS_GPIO_config() function is used to configure an individual GPIO port. + + @param port_id + The port_id parameter identifies the GPIO port to be configured. An + enumeration item of the form MSS_GPIO_n, where n is the number of the GPIO + port, is used to identify the GPIO port. For example, MSS_GPIO_0 identifies + the first GPIO port and MSS_GPIO_31 is the last one. + + @param config + The config parameter specifies the configuration to be applied to the GPIO + port identified by the port_id parameter. It is a logical OR of the required + I/O mode and the required interrupt mode. The interrupt mode is not relevant + if the GPIO is configured as an output only. + These I/O mode constants are allowed: + - MSS_GPIO_INPUT_MODE + - MSS_GPIO_OUTPUT_MODE + - MSS_GPIO_INOUT_MODE + These interrupt mode constants are allowed: + - MSS_GPIO_IRQ_LEVEL_HIGH + - MSS_GPIO_IRQ_LEVEL_LOW + - MSS_GPIO_IRQ_EDGE_POSITIVE + - MSS_GPIO_IRQ_EDGE_NEGATIVE + - MSS_GPIO_IRQ_EDGE_BOTH + + @return + none. + + Example: + The following call will configure GPIO 4 as an input generating interrupts on + a Low to High transition of the input: + @code + MSS_GPIO_config( MSS_GPIO_4, MSS_GPIO_INPUT_MODE | MSS_GPIO_IRQ_EDGE_POSITIVE ); + @endcode + */ +void MSS_GPIO_config +( + mss_gpio_id_t port_id, + uint32_t config +); + +/*-------------------------------------------------------------------------*//** + The MSS_GPIO_set_outputs() function is used to set the state of all GPIO ports + configured as outputs. + + @param value + The value parameter specifies the state of the GPIO ports configured as + outputs. It is a bit mask of the form (MSS_GPIO_n_MASK | MSS_GPIO_m_MASK) + where n and m are numbers identifying GPIOs. For example, (MSS_GPIO_0_MASK | + MSS_GPIO_1_MASK | MSS_GPIO_2_MASK ) specifies that the first, second and + third GPIO outputs must be set High and all other GPIO outputs set Low. The + driver provides 32 mask constants, MSS_GPIO_0_MASK to MSS_GPIO_31_MASK + inclusive, for this purpose. + + @return + none. + + Example 1: + Set GPIOs outputs 0 and 8 high and all other GPIO outputs low. + @code + MSS_GPIO_set_outputs( MSS_GPIO_0_MASK | MSS_GPIO_8_MASK ); + @endcode + + Example 2: + Set GPIOs outputs 2 and 4 low without affecting other GPIO outputs. + @code + uint32_t gpio_outputs; + gpio_outputs = MSS_GPIO_get_outputs(); + gpio_outputs &= ~( MSS_GPIO_2_MASK | MSS_GPIO_4_MASK ); + MSS_GPIO_set_outputs( gpio_outputs ); + @endcode + + @see MSS_GPIO_get_outputs() + */ +static __INLINE void +MSS_GPIO_set_outputs +( + uint32_t value +) +{ + GPIO->GPIO_OUT = value; +} + +/*-------------------------------------------------------------------------*//** + The MSS_GPIO_set_output() function is used to set the state of a single GPIO + port configured as an output. + Note: Using bit-band writes might be a better option than this function for + performance critical applications where the application code is not + intended to be ported to a processor other than the ARM Cortex-M3 in + SmartFusion2. The bit-band write equivalent to this function would be: + GPIO_BITBAND->GPIO_OUT[port_id] = (uint32_t)value; + + @param port_id + The port_id parameter identifies the GPIO port that is to have its output + set. An enumeration item of the form MSS_GPIO_n, where n is the number of + the GPIO port, is used to identify the GPIO port. For example, MSS_GPIO_0 + identifies the first GPIO port and MSS_GPIO_31 is the last one. + + @param value + The value parameter specifies the desired state for the GPIO output. A value + of 0 will set the output Low and a value of 1 will set the output High. + + @return + This function does not return a value. + + Example: + The following call will set GPIO output 12 High, leaving all other GPIO + outputs unaffected: + @code + _GPIO_set_output(MSS_GPIO_12, 1); + @endcode + */ +void MSS_GPIO_set_output +( + mss_gpio_id_t port_id, + uint8_t value +); + +/*-------------------------------------------------------------------------*//** + The MSS_GPIO_get_inputs() function is used to read the current state all GPIO + ports configured as inputs. + + @return + This function returns a 32-bit unsigned integer where each bit represents + the state of a GPIO input. The least significant bit represents the state of + GPIO input 0 and the most significant bit the state of GPIO input 31. + + Example: + Read and assign the current state of the GPIO outputs to a variable. + @code + uint32_t gpio_inputs; + gpio_inputs = MSS_GPIO_get_inputs(); + @endcode + */ +static __INLINE uint32_t +MSS_GPIO_get_inputs( void ) +{ + return GPIO->GPIO_IN; +} + +/*-------------------------------------------------------------------------*//** + The MSS_GPIO_get_outputs() function is used to read the current state all GPIO + ports configured as outputs. + + @return + This function returns a 32-bit unsigned integer where each bit represents + the state of a GPIO output. The least significant bit represents the state + of GPIO output 0 and the most significant bit the state of GPIO output 31. + + Example: + Read and assign the current state of the GPIO outputs to a variable. + @code + uint32_t gpio_outputs; + gpio_outputs = MSS_GPIO_get_outputs(); + @endcode + */ +static __INLINE uint32_t +MSS_GPIO_get_outputs( void ) +{ + return GPIO->GPIO_OUT; +} + +/*-------------------------------------------------------------------------*//** + The MSS_GPIO_drive_inout() function is used to set the output state of a + single GPIO port configured as an INOUT. An INOUT GPIO can be in one of three + states: + - High + - Low + - High impedance + An INOUT output would typically be used where several devices can drive the + state of a shared signal line. The High and Low states are equivalent to the + High and Low states of a GPIO configured as an output. The High impedance + state is used to prevent the GPIO from driving its output state onto the + signal line, while at the same time allowing the input state of the GPIO to + be read. + + @param port_id + The port_id parameter identifies the GPIO port for which you want to change + the output state. An enumeration item of the form MSS_GPIO_n, where n is the + number of the GPIO port, is used to identify the GPIO port. For example, + MSS_GPIO_0 identifies the first GPIO port and MSS_GPIO_31 is the last one. + + @param inout_state + The inout_state parameter specifies the state of the GPIO port identified by + the port_id parameter. Allowed values of type mss_gpio_inout_state_t are as + follows: + - MSS_GPIO_DRIVE_HIGH + - MSS_GPIO_DRIVE_LOW + - MSS_GPIO_HIGH_Z (High impedance) + + @return + This function does not return a value. + + Example: + The call to MSS_GPIO_drive_inout() below will set the GPIO 7 output to the + high impedance state. + @code + MSS_GPIO_drive_inout( MSS_GPIO_7, MSS_GPIO_HIGH_Z ); + @endcode + */ +void MSS_GPIO_drive_inout +( + mss_gpio_id_t port_id, + mss_gpio_inout_state_t inout_state +); + +/*-------------------------------------------------------------------------*//** + The MSS_GPIO_enable_irq() function is used to enable interrupt generation for + the specified GPIO input. Interrupts are generated based on the state of the + GPIO input and the interrupt mode configured for it by MSS_GPIO_config(). + + @param port_id + The port_id parameter identifies the GPIO port for which you want to enable + interrupt generation. An enumeration item of the form MSS_GPIO_n, where n is + the number of the GPIO port, is used to identify the GPIO port. For example, + MSS_GPIO_0 identifies the first GPIO port and MSS_GPIO_31 is the last one. + + @return + This function does not return a value. + + Example: + The call to MSS_GPIO_enable_irq() below will allow GPIO 8 to generate + interrupts. + @code + MSS_GPIO_enable_irq( MSS_GPIO_8 ); + @endcode + */ +void MSS_GPIO_enable_irq +( + mss_gpio_id_t port_id +); + +/*-------------------------------------------------------------------------*//** + The MSS_GPIO_disable_irq() function is used to disable interrupt generation + for the specified GPIO input. + + @param port_id + The port_id parameter identifies the GPIO port for which you want to disable + interrupt generation. An enumeration item of the form MSS_GPIO_n, where n is + the number of the GPIO port, is used to identify the GPIO port. For example, + MSS_GPIO_0 identifies the first GPIO port and MSS_GPIO_31 is the last one. + + @return + This function does not return a value. + + Example: + The call to MSS_GPIO_disable_irq() below will prevent GPIO 8 from generating + interrupts. + @code + MSS_GPIO_disable_irq( MSS_GPIO_8 ); + @endcode + */ +void MSS_GPIO_disable_irq +( + mss_gpio_id_t port_id +); + +/*-------------------------------------------------------------------------*//** + The MSS_GPIO_clear_irq() function is used to clear a pending interrupt from + the specified GPIO input. + Note: The MSS_GPIO_clear_irq() function must be called as part of any GPIO + interrupt service routine (ISR) in order to prevent the same interrupt + event retriggering a call to the GPIO ISR. + + @param port_id + The port_id parameter identifies the GPIO port for which you want to clear + the interrupt. An enumeration item of the form MSS_GPIO_n, where n is the + number of the GPIO port, is used to identify the GPIO port. For example, + MSS_GPIO_0 identifies the first GPIO port and MSS_GPIO_31 is the last one. + + @return + none. + + Example: + The example below demonstrates the use of the MSS_GPIO_clear_irq() function + as part of the GPIO 9 interrupt service routine. + @code + void GPIO9_IRQHandler( void ) + { + do_interrupt_processing(); + + MSS_GPIO_clear_irq( MSS_GPIO_9 ); + } + @endcode + */ +void MSS_GPIO_clear_irq +( + mss_gpio_id_t port_id +); + +#ifdef __cplusplus +} +#endif + +#endif /* MSS_GPIO_H_ */ diff --git a/bsp/smartfusion2/libraries/mss_sys_services/mss_comblk.c b/bsp/smartfusion2/libraries/mss_sys_services/mss_comblk.c new file mode 100644 index 0000000000..ebd9805ca2 --- /dev/null +++ b/bsp/smartfusion2/libraries/mss_sys_services/mss_comblk.c @@ -0,0 +1,752 @@ +/******************************************************************************* + * (c) Copyright 2012-2016 Microsemi SoC Products Group. All rights reserved. + * + * SmartFusion2 COMBLK access functions. + * + * SVN $Revision: 8345 $ + * SVN $Date: 2016-03-23 11:53:04 +0530 (Wed, 23 Mar 2016) $ + */ + +#include "mss_comblk.h" +#include "../../CMSIS/mss_assert.h" + +/*============================================================================== + * + */ +/*------------------------------------------------------------------------------ + * Control register bit masks. + */ +#define CR_FLUSHOUT_MASK 0x01u +#define CR_FLUSHIN_MASK 0x02u +#define CR_SIZETX_MASK 0x04u +#define CR_ENABLE_MASK 0x10u +#define CR_LOOPBACK_MASK 0x20u + +/*------------------------------------------------------------------------------ + * Status and interrupt enable registers bit masks. + */ +#define TXTOKAY_MASK 0x01u +#define RCVOKAY_MASK 0x02u +#define TXOVERFLOW_MASK 0x04u +#define RXUNDERFLOW_MASK 0x08u +/*------------------------------------------------------------------------------ + * DATA8 register bit masks. + */ +#define DATA8_COMMAND_MASK 0x8000u + +/*------------------------------------------------------------------------------ + * COMBLK driver states. + */ +#define COMBLK_IDLE 0u +#define COMBLK_TX_CMD 1u +#define COMBLK_TX_DATA 2u +#define COMBLK_WAIT_RESPONSE 3u +#define COMBLK_RX_RESPONSE 4u +#define COMBLK_TX_PAGED_DATA 5u + +#define POR_DIGEST_ERROR_OPCODE 0xF1u + +/*============================================================================== + * COMBLK interrupt service routine. + */ +void ComBlk_IRQHandler(void); + +/*============================================================================== + * Local functions. + */ +static void abort_current_cmd(void); +static void send_cmd_opcode(uint8_t opcode); +static uint32_t fill_tx_fifo(const uint8_t * p_cmd, uint32_t cmd_size); +static void handle_tx_okay_irq(void); +static void handle_rx_okay_irq(void); +static void complete_request(uint16_t response_length); +static void process_sys_ctrl_command(uint8_t cmd_opcode); + +/*============================================================================== + * Global variables: + */ +static volatile uint8_t g_comblk_cmd_opcode = 0u; +static const uint8_t * g_comblk_p_cmd = 0u; +static volatile uint16_t g_comblk_cmd_size = 0u; +static const uint8_t * g_comblk_p_data = 0u; +static volatile uint32_t g_comblk_data_size = 0u; +static uint8_t * g_comblk_p_response = 0u; +static uint16_t g_comblk_response_size = 0u; +static volatile uint16_t g_comblk_response_idx = 0u; +static comblk_completion_handler_t g_comblk_completion_handler = 0; +static uint32_t (*g_comblk_page_handler)(uint8_t const ** pp_next_page) = 0; +static volatile uint8_t g_request_in_progress = 0u; +static uint8_t g_comblk_state = COMBLK_IDLE; +static volatile comblk_async_event_handler_t g_async_event_handler = 0; + +/*============================================================================== + * + */ +void MSS_COMBLK_init +( + comblk_async_event_handler_t async_event_handler, + uint8_t* p_response +) +{ + /* + * Disable and clear previous interrupts. + */ + NVIC_DisableIRQ(ComBlk_IRQn); + COMBLK->INT_ENABLE = 0u; + NVIC_ClearPendingIRQ(ComBlk_IRQn); + + g_async_event_handler = async_event_handler; + + /* + * Initialize COMBLK driver state variables: + */ + g_request_in_progress = 0u; + g_comblk_cmd_opcode = 0u; + g_comblk_p_cmd = 0u; + g_comblk_cmd_size = 0u; + g_comblk_p_data = 0u; + g_comblk_data_size = 0u; + g_comblk_p_response = p_response; + g_comblk_response_size = 0u; + g_comblk_response_idx = 0u; + g_comblk_completion_handler = 0; + + g_comblk_state = COMBLK_IDLE; + + /* + * Disable loopback before enabling the MSS COMM_BLK to ensure that any + * codes waiting in the TX FIFO of the System Controller�s COMM_BLK are + * not lost. + */ + COMBLK->CONTROL &= ~CR_LOOPBACK_MASK; + COMBLK->CONTROL |= CR_ENABLE_MASK; + + /*-------------------------------------------------------------------------- + * Enable receive interrupt to receive asynchronous events from the system + * controller. + */ + COMBLK->INT_ENABLE &= ~TXTOKAY_MASK; + COMBLK->INT_ENABLE |= RCVOKAY_MASK; + NVIC_EnableIRQ(ComBlk_IRQn); +} + +/*============================================================================== + * + */ +void MSS_COMBLK_send_cmd_with_ptr +( + uint8_t cmd_opcode, + uint32_t cmd_params_ptr, + uint8_t * p_response, + uint16_t response_size, + comblk_completion_handler_t completion_handler +) +{ + uint32_t tx_okay; + + /*-------------------------------------------------------------------------- + * Disable and clear previous interrupts. + */ + NVIC_DisableIRQ(ComBlk_IRQn); + COMBLK->INT_ENABLE = 0u; + NVIC_ClearPendingIRQ(ComBlk_IRQn); + + /*-------------------------------------------------------------------------- + * Abort current command if any. + */ + abort_current_cmd(); + + /*-------------------------------------------------------------------------- + * Initialize COMBLK driver state variables. + */ + g_request_in_progress = 1u; + g_comblk_cmd_opcode = cmd_opcode; + g_comblk_p_cmd = 0u; + g_comblk_cmd_size = 0u; + g_comblk_p_data = 0u; + g_comblk_data_size = 0u; + g_comblk_p_response = p_response; + g_comblk_response_size = response_size; + g_comblk_response_idx = 0u; + g_comblk_page_handler = 0u; + g_comblk_completion_handler = completion_handler; + + /*-------------------------------------------------------------------------- + * Send command opcode as a single byte write to the Tx FIFO. + */ + send_cmd_opcode(g_comblk_cmd_opcode); + + /*-------------------------------------------------------------------------- + * Send the command parameters pointer to the Tx FIFO as a single 4 bytes + * write to the Tx FIFO. + */ + COMBLK->CONTROL |= CR_SIZETX_MASK; + + /* Wait for space to become available in Tx FIFO. */ + do { + tx_okay = COMBLK->STATUS & TXTOKAY_MASK; + } while(0u == tx_okay); + + /* Send command opcode. */ + COMBLK->DATA32 = cmd_params_ptr; + + COMBLK->CONTROL &= ~CR_SIZETX_MASK; + + g_comblk_state = COMBLK_WAIT_RESPONSE; + + /*-------------------------------------------------------------------------- + * Enable interrupt. + */ + COMBLK->INT_ENABLE |= RCVOKAY_MASK; + NVIC_EnableIRQ(ComBlk_IRQn); +} + +/*============================================================================== + * + */ +void MSS_COMBLK_send_cmd +( + const uint8_t * p_cmd, + uint16_t cmd_size, + const uint8_t * p_data, + uint32_t data_size, + uint8_t * p_response, + uint16_t response_size, + comblk_completion_handler_t completion_handler +) +{ + uint32_t size_sent; + + ASSERT(cmd_size > 0); + + /* + * Disable and clear previous interrupts. + */ + NVIC_DisableIRQ(ComBlk_IRQn); + COMBLK->INT_ENABLE = 0u; + NVIC_ClearPendingIRQ(ComBlk_IRQn); + + /* + * Abort current command if any. + */ + abort_current_cmd(); + + /* + * Initialize COMBLK driver state variables: + */ + g_request_in_progress = 1u; + g_comblk_cmd_opcode = p_cmd[0]; + g_comblk_p_cmd = p_cmd; + g_comblk_cmd_size = cmd_size; + g_comblk_p_data = p_data; + g_comblk_data_size = data_size; + g_comblk_p_response = p_response; + g_comblk_response_size = response_size; + g_comblk_response_idx = 0u; + g_comblk_page_handler = 0u; + g_comblk_completion_handler = completion_handler; + + COMBLK->INT_ENABLE |= RCVOKAY_MASK; + + /* + * Fill FIFO with command. + */ + send_cmd_opcode(g_comblk_cmd_opcode); + size_sent = fill_tx_fifo(&p_cmd[1], cmd_size - 1u); + ++size_sent; /* Adjust for opcode byte sent. */ + if(size_sent < cmd_size) + { + g_comblk_cmd_size = g_comblk_cmd_size - (uint16_t)size_sent; + g_comblk_p_cmd = &g_comblk_p_cmd[size_sent]; + + g_comblk_state = COMBLK_TX_CMD; + } + else + { + g_comblk_cmd_size = 0u; + if(g_comblk_data_size > 0u) + { + g_comblk_state = COMBLK_TX_DATA; + } + else + { + g_comblk_state = COMBLK_WAIT_RESPONSE; + } + } + + /* + * Enable interrupt. + */ + NVIC_EnableIRQ(ComBlk_IRQn); +} + +/*============================================================================== + * + */ +void MSS_COMBLK_send_paged_cmd +( + const uint8_t * p_cmd, + uint16_t cmd_size, + uint8_t * p_response, + uint16_t response_size, + comblk_page_handler_t page_read_handler, + comblk_completion_handler_t completion_handler +) +{ + uint32_t size_sent; + uint8_t irq_enable = 0u; + + ASSERT(cmd_size > 0u); + + /* + * Disable and clear previous interrupts. + */ + NVIC_DisableIRQ(ComBlk_IRQn); + COMBLK->INT_ENABLE = 0u; + NVIC_ClearPendingIRQ(ComBlk_IRQn); + + /* + * Abort current command if any. + */ + abort_current_cmd(); + + /* + * Initialize COMBLK driver state variables: + */ + g_request_in_progress = 1u; + g_comblk_cmd_opcode = p_cmd[0]; + g_comblk_p_cmd = p_cmd; + g_comblk_cmd_size = cmd_size; + g_comblk_p_data = 0; + g_comblk_data_size = 0u; + g_comblk_p_response = p_response; + g_comblk_response_size = response_size; + g_comblk_response_idx = 0u; + g_comblk_page_handler = page_read_handler; + g_comblk_completion_handler = completion_handler; + + /* + * Fill FIFO with command. + */ + send_cmd_opcode(g_comblk_cmd_opcode); + size_sent = fill_tx_fifo(&p_cmd[1], cmd_size - 1u); + ++size_sent; /* Adjust for opcode byte sent. */ + if(size_sent < cmd_size) + { + g_comblk_cmd_size = g_comblk_cmd_size - (uint16_t)size_sent; + g_comblk_p_cmd = &g_comblk_p_cmd[size_sent]; + + g_comblk_state = COMBLK_TX_CMD; + irq_enable = TXTOKAY_MASK | RCVOKAY_MASK; + } + else + { + g_comblk_cmd_size = 0u; + g_comblk_state = COMBLK_TX_PAGED_DATA; + irq_enable = TXTOKAY_MASK | RCVOKAY_MASK; + } + + /* + * Enable interrupt. + */ + COMBLK->INT_ENABLE |= irq_enable; + NVIC_EnableIRQ(ComBlk_IRQn); +} + +/*============================================================================== + * COMBLK interrupt handler. + */ +void ComBlk_IRQHandler(void) +{ + uint8_t status; + uint8_t tx_okay; + uint8_t rcv_okay; + + status = (uint8_t)COMBLK->STATUS; + + /* Mask off interrupt that are not enabled.*/ + status &= COMBLK->INT_ENABLE; + + rcv_okay = status & RCVOKAY_MASK; + + if(rcv_okay) + { + handle_rx_okay_irq(); + } + + tx_okay = status & TXTOKAY_MASK; + if(tx_okay) + { + handle_tx_okay_irq(); + } +} + +/*============================================================================== + * + */ +static void handle_tx_okay_irq(void) +{ + switch(g_comblk_state) + { + /*---------------------------------------------------------------------- + * The TX_OKAY interrupt should only be enabled for states COMBLK_TX_CMD + * and COMBLK_TX_DATA. + */ + case COMBLK_TX_CMD: + if(g_comblk_cmd_size > 0u) + { + uint32_t size_sent; + size_sent = fill_tx_fifo(g_comblk_p_cmd, g_comblk_cmd_size); + if(size_sent < g_comblk_cmd_size) + { + g_comblk_cmd_size = g_comblk_cmd_size - (uint16_t)size_sent; + g_comblk_p_cmd = &g_comblk_p_cmd[size_sent]; + } + else + { + g_comblk_cmd_size = 0u; + if(g_comblk_data_size > 0u) + { + g_comblk_state = COMBLK_TX_DATA; + } + else + { + g_comblk_state = COMBLK_WAIT_RESPONSE; + } + } + } + else + { + /* + * This is an invalid situation indicating a bug in the driver + * or corrupted memory. + */ + ASSERT(0); + abort_current_cmd(); + } + break; + + case COMBLK_TX_DATA: + if(g_comblk_data_size > 0u) + { + uint32_t size_sent; + size_sent = fill_tx_fifo(g_comblk_p_data, g_comblk_data_size); + if(size_sent < g_comblk_data_size) + { + g_comblk_data_size = g_comblk_data_size - size_sent; + g_comblk_p_data = &g_comblk_p_data[size_sent]; + } + else + { + COMBLK->INT_ENABLE &= ~TXTOKAY_MASK; + g_comblk_state = COMBLK_WAIT_RESPONSE; + } + } + else + { + /* + * This is an invalid situation indicating a bug in the driver + * or corrupted memory. + */ + ASSERT(0); + abort_current_cmd(); + } + break; + + case COMBLK_TX_PAGED_DATA: + /* + * Read a page of data if required. + */ + if(0u == g_comblk_data_size) + { + if(g_comblk_page_handler != 0) + { + g_comblk_data_size = g_comblk_page_handler(&g_comblk_p_data); + if(0u == g_comblk_data_size) + { + COMBLK->INT_ENABLE &= ~TXTOKAY_MASK; + g_comblk_state = COMBLK_WAIT_RESPONSE; + } + } + else + { + ASSERT(0); + abort_current_cmd(); + } + } + + /* + * Transmit the page data or move to COMBLK_WAIT_RESPONSE state if + * no further page data could be obtained by the call to the page + * handler above. + */ + if(0u == g_comblk_data_size) + { + COMBLK->INT_ENABLE &= ~TXTOKAY_MASK; + g_comblk_state = COMBLK_WAIT_RESPONSE; + } + else + { + uint32_t size_sent; + size_sent = fill_tx_fifo(g_comblk_p_data, g_comblk_data_size); + g_comblk_data_size = g_comblk_data_size - size_sent; + g_comblk_p_data = &g_comblk_p_data[size_sent]; + } + break; + + /*---------------------------------------------------------------------- + * The TX_OKAY interrupt should NOT be enabled for states COMBLK_IDLE, + * COMBLK_WAIT_RESPONSE and COMBLK_RX_RESPONSE. + */ + case COMBLK_IDLE: + /* Fall through */ + case COMBLK_WAIT_RESPONSE: + /* Fall through */ + case COMBLK_RX_RESPONSE: + /* Fall through */ + default: + COMBLK->INT_ENABLE &= ~TXTOKAY_MASK; + complete_request(0u); + g_comblk_state = COMBLK_IDLE; + break; + } +} + +/*============================================================================== + * + */ +static void handle_rx_okay_irq(void) +{ + uint16_t data16; + uint16_t is_command; + uint8_t data8; + + data16 = (uint16_t)COMBLK->DATA8; + is_command = data16 & DATA8_COMMAND_MASK; + data8 = (uint8_t)data16; + + switch(g_comblk_state) + { + /*---------------------------------------------------------------------- + * MSS_COMBLK_init() enables the RCV_OKAY interrupt for the COMBLK_IDLE + * state to receive the asynchronous power-on-reset from the system + * controller. + */ + case COMBLK_IDLE: + if(is_command) + { + if(data8 != POR_DIGEST_ERROR_OPCODE) + { + uint8_t rxed_opcode; + rxed_opcode = data8; + process_sys_ctrl_command(rxed_opcode); + } + else + { + g_comblk_response_idx = 0; + g_comblk_p_response[g_comblk_response_idx] = data8; + g_comblk_response_idx++; + g_comblk_p_response[g_comblk_response_idx] = 0x00u; + g_comblk_state = COMBLK_RX_RESPONSE; + } + } + break; + + /*---------------------------------------------------------------------- + * The RCV_OKAY interrupt should only be enabled for states + * COMBLK_WAIT_RESPONSE and COMBLK_RX_RESPONSE. + */ + case COMBLK_WAIT_RESPONSE: + if(is_command) + { + uint8_t rxed_opcode; + rxed_opcode = data8; + if(rxed_opcode == g_comblk_cmd_opcode) + { + g_comblk_response_idx = 0u; + g_comblk_p_response[g_comblk_response_idx] = rxed_opcode; + ++g_comblk_response_idx; + g_comblk_state = COMBLK_RX_RESPONSE; + } + else + { + process_sys_ctrl_command(rxed_opcode); + } + } + break; + + case COMBLK_RX_RESPONSE: + if(is_command) + { + uint8_t rxed_opcode; + rxed_opcode = data8; + process_sys_ctrl_command(rxed_opcode); + } + else + { + if( g_comblk_p_response[g_comblk_response_idx-1] == POR_DIGEST_ERROR_OPCODE) + { + g_comblk_p_response[g_comblk_response_idx] = data8; + process_sys_ctrl_command(g_comblk_p_response[g_comblk_response_idx-1]); + g_comblk_state = COMBLK_IDLE; + } + else + { + if(g_comblk_response_idx < g_comblk_response_size) + { + uint8_t rxed_data; + + rxed_data = data8; + g_comblk_p_response[g_comblk_response_idx] = rxed_data; + ++g_comblk_response_idx; + } + + if(g_comblk_response_idx == g_comblk_response_size) + { + complete_request(g_comblk_response_idx); + g_comblk_state = COMBLK_IDLE; + } + } + } + break; + + /*---------------------------------------------------------------------- + * The RCV_OKAY interrupt should NOT be enabled for states + * COMBLK_IDLE, COMBLK_TX_CMD and COMBLK_TX_DATA. + */ + case COMBLK_TX_PAGED_DATA: + /* This is needed because when there is an error, we need to terminate loading the data */ + if(!is_command) + { + g_comblk_p_response[1] = data8; + complete_request(2u); + g_comblk_state = COMBLK_IDLE; + } + else + { + uint8_t rxed_opcode; + rxed_opcode = data8; + process_sys_ctrl_command(rxed_opcode); + } + break; + + case COMBLK_TX_CMD: + /* Fall through */ + case COMBLK_TX_DATA: + /* Fall through */ + if(is_command) + { + uint8_t rxed_opcode; + rxed_opcode = data8; + process_sys_ctrl_command(rxed_opcode); + } + break; + + default: + complete_request(0u); + g_comblk_state = COMBLK_IDLE; + break; + } +} + +/*============================================================================== + * + */ +static void complete_request +( + uint16_t response_length +) +{ + if(g_comblk_completion_handler != 0) + { + g_comblk_completion_handler(g_comblk_p_response, response_length); + g_comblk_completion_handler = 0; + g_request_in_progress = 0u; + } +} + +/*============================================================================== + * + */ +static void abort_current_cmd(void) +{ + if(g_request_in_progress) + { + uint32_t flush_in_progress; + + /* + * Call completion handler just in case we are in a multi threaded system + * to avoid a task lockup. + */ + complete_request(g_comblk_response_idx); + + /* + * Flush the FIFOs + */ + COMBLK->CONTROL |= CR_FLUSHOUT_MASK; + do { + flush_in_progress = COMBLK->CONTROL & CR_FLUSHOUT_MASK; + } while(flush_in_progress); + } +} + +/*============================================================================== + * + */ +static void send_cmd_opcode +( + uint8_t opcode +) +{ + uint32_t tx_okay; + + /* Set transmit FIFO to transfer bytes. */ + COMBLK->CONTROL &= ~CR_SIZETX_MASK; + + /* Wait for space to become available in Tx FIFO. */ + do { + tx_okay = COMBLK->STATUS & TXTOKAY_MASK; + } while(0u == tx_okay); + + /* Send command opcode. */ + COMBLK->FRAME_START8 = opcode; +} + +/*============================================================================== + * + */ +static uint32_t fill_tx_fifo +( + const uint8_t * p_cmd, + uint32_t cmd_size +) +{ + volatile uint32_t tx_okay; + uint32_t size_sent; + + /* Set transmit FIFO to transfer bytes. */ + COMBLK->CONTROL &= ~CR_SIZETX_MASK; + + size_sent = 0u; + tx_okay = COMBLK->STATUS & TXTOKAY_MASK; + while((tx_okay != 0u) && (size_sent < cmd_size)) + { + COMBLK->DATA8 = p_cmd[size_sent]; + ++size_sent; + tx_okay = COMBLK->STATUS & TXTOKAY_MASK; + } + + return size_sent; +} + +/*============================================================================== + * + */ +static void process_sys_ctrl_command(uint8_t cmd_opcode) +{ + if(g_async_event_handler != 0) + { + g_async_event_handler(cmd_opcode); + } +} + diff --git a/bsp/smartfusion2/libraries/mss_sys_services/mss_comblk.h b/bsp/smartfusion2/libraries/mss_sys_services/mss_comblk.h new file mode 100644 index 0000000000..96d3af5518 --- /dev/null +++ b/bsp/smartfusion2/libraries/mss_sys_services/mss_comblk.h @@ -0,0 +1,90 @@ +/******************************************************************************* + * (c) Copyright 2012-2016 Microsemi SoC Products Group. All rights reserved. + * + * SmartFusion2 COMBLK access functions. + * + * SVN $Revision: 8345 $ + * SVN $Date: 2016-03-23 11:53:04 +0530 (Wed, 23 Mar 2016) $ + */ +#ifndef __MSS_COMBLK_H_ +#define __MSS_COMBLK_H_ 1 + +#include "../../CMSIS/m2sxxx.h" +#include "mss_comblk_page_handler.h" + +#ifdef __cplusplus +extern "C" { +#endif + +/*------------------------------------------------------------------------------ + * + */ +typedef void(*comblk_completion_handler_t)(uint8_t * p_response, uint16_t response_size); + +typedef void (*comblk_async_event_handler_t)(uint8_t event_opcode); + +/*------------------------------------------------------------------------------ + * + */ +void MSS_COMBLK_init +( + comblk_async_event_handler_t async_event_handler, + uint8_t* p_response +); + +/*------------------------------------------------------------------------------ + * + */ +void MSS_COMBLK_send_cmd_with_ptr +( + uint8_t cmd_opcode, + uint32_t cmd_params_ptr, + uint8_t * p_response, + uint16_t response_size, + comblk_completion_handler_t completion_handler +); + +/*------------------------------------------------------------------------------ + * + */ +void MSS_COMBLK_send_cmd +( + const uint8_t * p_cmd, + uint16_t cmd_size, + const uint8_t * p_data, + uint32_t data_size, + uint8_t * p_response, + uint16_t response_size, + comblk_completion_handler_t completion_handler +); + +/*------------------------------------------------------------------------------ + * + */ +void MSS_COMBLK_read +( + const uint8_t * p_data, + uint16_t cmd_size, + uint8_t * p_response, + uint16_t response_size, + comblk_completion_handler_t completion_handler +); + +/*------------------------------------------------------------------------------ + * + */ +void MSS_COMBLK_send_paged_cmd +( + const uint8_t * p_cmd, + uint16_t cmd_size, + uint8_t * p_response, + uint16_t response_size, + comblk_page_handler_t page_read_handler, + comblk_completion_handler_t completion_handler +); + +#ifdef __cplusplus +} +#endif + +#endif /* __MSS_COMBLK_H_ */ diff --git a/bsp/smartfusion2/libraries/mss_sys_services/mss_comblk_page_handler.h b/bsp/smartfusion2/libraries/mss_sys_services/mss_comblk_page_handler.h new file mode 100644 index 0000000000..1c363df54e --- /dev/null +++ b/bsp/smartfusion2/libraries/mss_sys_services/mss_comblk_page_handler.h @@ -0,0 +1,66 @@ +/******************************************************************************* + * (c) Copyright 2012-2016 Microsemi SoC Products Group. All rights reserved. + * + * SmartFusion2 MSS COM block driver, page handler callback function prototype. + * + * SVN $Revision: 8345 $ + * SVN $Date: 2016-03-23 11:53:04 +0530 (Wed, 23 Mar 2016) $ + */ + +#ifndef __MSS_COMBLK_PAGE_HANDLER_H_ +#define __MSS_COMBLK_PAGE_HANDLER_H_ 1 + +#ifdef __cplusplus +extern "C" { +#endif + +/*-------------------------------------------------------------------------*//** + The comblk_page_handler_t typedef specifies the function prototype of a COMBLK + page handler callback function. This callback is used by the system services + and COMBLK drivers as part of in-system programming (ISP) to retrieve the next + page of programming information to send to the SmartFusion2 System Controller + via the COMBLK. + The COMBLK page handler must be implemented by the application layer to return + the address of the next page of programming data to be sent to the + SmartFusion2 system controller. It must return the number of bytes contained + in the next page. Returning a value of zero indicates that all programming + data has been passed to the system services/COMBLK drivers. + + @code + #define PAGE_LENGTH 512 + + uint8_t programming_data[PROG_DATA_LENGTH]; + uint32_t prog_data_index = 0; + + uint32_t page_read_handler + ( + uint8_t const ** pp_next_page + ) + { + uint32_t returned_page_length; + uint32_t remaining_length; + + *pp_next_page = &programming_data[prog_data_index]; + remaining_length = PROG_DATA_LENGTH - prog_data_index + if(remaining_length > PAGE_LENGTH) + { + returned_page_length = PAGE_LENGTH; + } + else + { + returned_page_length = remaining_length; + prog_data_index = PROG_DATA_LENGTH; + } + + return returned_page_length; + } + + @endcode + */ +typedef uint32_t (*comblk_page_handler_t)(uint8_t const ** pp_next_page); + +#ifdef __cplusplus +} +#endif + +#endif /* __MSS_COMBLK_PAGE_HANDLER_H_ */ diff --git a/bsp/smartfusion2/libraries/mss_sys_services/mss_sys_services.c b/bsp/smartfusion2/libraries/mss_sys_services/mss_sys_services.c new file mode 100644 index 0000000000..982b9d088b --- /dev/null +++ b/bsp/smartfusion2/libraries/mss_sys_services/mss_sys_services.c @@ -0,0 +1,2452 @@ +/******************************************************************************* + * (c) Copyright 2012-2016 Microsemi SoC Products Group. All rights reserved. + * + * SmartFusion2 system services. + * + * SVN $Revision: 8688 $ + * SVN $Date: 2016-11-27 17:46:49 +0530 (Sun, 27 Nov 2016) $ + */ +#include "mss_sys_services.h" +#include "mss_comblk.h" +#include "../../CMSIS/mss_assert.h" +#include <string.h> + +/*============================================================================== + * + */ +/* + * Service request command opcodes: + */ +#define DEVICE_CERTIFICATE_REQUEST_CMD 0u +#define SERIAL_NUMBER_REQUEST_CMD 1u +#define FLASH_FREEZE_REQUEST_CMD 2u +#define AES128_REQUEST_CMD 3u +#define USERCODE_REQUEST_CMD 4u +#define DESIGNVER_REQUEST_CMD 5u +#define AES256_REQUEST_CMD 6u +#define KEYTREE_REQUEST_CMD 9u +#define SHA256_REQUEST_CMD 10u +#define HMAC_REQUEST_CMD 12u +#define PPUF_CHALLENGE_RESP_REQUEST_CMD 14u +#define POINT_MULTIPLICATION_REQUEST_CMD 16u +#define POINT_ADDITION_REQUEST_CMD 17u +#define IAP_PROGRAMMING_REQUEST_CMD 20u +#define ISP_PROGRAMMING_REQUEST_CMD 21u +#define DIGEST_CHECK_REQUEST_CMD 23u +#define PUF_ACTIVATION_CODE_REQUEST_CMD 25u +#define PUF_USER_KEY_CODE_REQUEST_CMD 26u +#define PUF_FETCH_KEY_REQUEST_CMD 27u +#define PUF_ECC_PUBLIC_KEY_REQUEST_CMD 28u +#define PUF_SEED_REQUEST_CMD 29u +#define SECONDARY_DEVICE_CERTIFICATE_REQUEST_CMD 30u +#define TAMPER_CONTROL_REQUEST_CMD 31u +#define NRBG_SELF_TEST_REQUEST_CMD 40u +#define NRBG_INSTANTIATE_REQUEST_CMD 41u +#define NRBG_GENERATE_REQUEST_CMD 42u +#define NRBG_RESEED_REQUEST_CMD 43u +#define NRBG_UNINSTANTIATE_REQUEST_CMD 44u +#define NRBG_RESET_REQUEST_CMD 45u +#define FLASHFREEZE_SHUTDOWN_CMD 224u +#define ZEROIZATION_REQUEST_CMD 240u +#define POWER_ON_RESET_DIGEST_ERROR_CMD 241u + +/* + * System Services requests length: + */ +#define FLASH_FREEZE_REQUEST_LENGTH 2u + +/* + * Service response lengths: + */ +#define STANDARD_SERV_RESP_LENGTH 6u +#define SERIAL_NUMBER_SERV_RESP_LENGTH 6u +#define USERCODE_SERV_RESP_LENGTH 6u +#define DESIGNVER_SERV_RESP_LENGTH 6u +#define DEVICE_CERT_SERV_RESP_LENGTH 6u +#define SECONDARY_DEVICE_CERT_SERV_RESP_LENGTH 6u +#define ISP_PROG_SERV_RESP_LENGTH 2u +#define IAP_PROG_SERV_RESP_LENGTH 2u +#define NRBG_RESET_SERV_RESP_LENGTH 2u +#define NRBG_SELF_TEST_SERV_RESP_LENGTH 2u +#define NRBG_UNINST_SERV_RESP_LENGTH 3u +#define DRBG_RESET_SERV_RESP_LENGTH 2u +#define DIGEST_CHECK_SERV_RESP_LENGTH 2u +#define FLASH_FREEZE_SERV_RESP_LENGTH 2u +#define PORDIGEST_CHECK_SERV_RESP_LENGTH 2u +#define TAMPER_CONTROL_SERV_RESP_LENGTH 2u +#define PUF_USER_ACTIVATION_CODE_RESP_LENGTH 2u +#define PUF_GET_NUMBER_OF_KEYS_RESP_LENGTH 6u +#define PUF_ENROLL_KEYS_RESP_LENGTH 6u +#define PUF_EXPORT_ALL_KEYCODES_RESP_LENGTH 6u +#define PUF_IMPORT_ALL_KEYCODES_RESP_LENGTH 6u +#define FACC_STANDBY_SEL 0u +#define MSS_25_50MHZ_EN 1u +#define MSS_1MHZ_EN 1u +#define FACC_STANDBY_SHIFT 6u +#define MSS_25_50MHZ_EN_SHIFT 9u +#define MSS_1MHZ_EN_SHIFT 10u +#define FACC_STANDBY_SEL_MASK 0x000001C0u +#define MSS_25_50MHZ_EN_MASK 0x00000200u +#define MSS_1MHZ_EN_MASK 0x00000400u + +/* + * Non Deterministic Random Bit Generator defines: + */ +#define INVALID_NRBG_HANDLE 0xFFu + +/* + * RTC_WAKEUP_CR system register bit masks: + */ +#define RTC_WAKEUP_G4C_EN_MASK 0x00000004u +#define RTC_WAKEUP_FAB_EN_MASK 0x00000002u + +/* + * PUF user activation code sub command + */ +#define PUF_CREATE_USER_ACTIVATION_CODE 0u +#define PUF_DELETE_USER_ACTIVATION_CODE 1u + +/* + * Sub Command for PUF service + */ +#define PUF_GET_NUMBER_OF_KC_SUBCOMMAND 0u +#define PUF_CREATE_EXT_KC_SUBCOMMAND 1u +#define PUF_CREATE_INT_KC_SUBCOMMAND 2u +#define PUF_EXPORT_ALL_KC_SUBCOMMAND 3u +#define PUF_IMPORT_ALL_KC_SUBCOMMAND 4u +#define PUF_DELETE_KC_SUBCOMMAND 5u + +/*============================================================================== + * Local functions. + */ +static void request_completion_handler(uint8_t * p_response, uint16_t response_size); +static void signal_request_start(void); +static uint16_t wait_for_request_completion(void); +static uint8_t execute_service +( + uint8_t cmd_opcode, + uint8_t * cmd_params_ptr, + uint8_t * response, + uint16_t response_length +); + +static void asynchronous_event_handler(uint8_t event_opcode); + +static void write_ptr_value_into_array +( + const uint8_t * pointer, + uint8_t target_array[], + uint32_t array_index +); + +static void write_array_into_ptr_value +( + uint8_t** pointer, + uint8_t target_array[], + uint32_t array_index +); +static void revert_clk_config(void); +static uint8_t clk_switching_fix(void); +static uint8_t* determine_seq(uint8_t val, uint8_t* len); + +/*============================================================================== + * Global variables + */ +static volatile uint8_t g_request_in_progress = 0u; +static volatile uint16_t g_last_response_length = 0u; +static sys_serv_async_event_handler_t g_event_handler = 0; +static uint8_t g_response[PORDIGEST_CHECK_SERV_RESP_LENGTH] = {0u}; +static uint32_t g_initial_mssddr_facc1_cr = 0U; + +/*============================================================================== + * See mss_sys_services.h for details. + */ +void MSS_SYS_init(sys_serv_async_event_handler_t event_handler) +{ + g_event_handler = event_handler; + g_last_response_length = 0u; + g_request_in_progress = 0u; + + /* + * Set a default good value for g_initial_mssddr_facc1_cr used to control + * the clock dividers coming in and out of Flash*Freeze. + */ + g_initial_mssddr_facc1_cr = SYSREG->MSSDDR_FACC1_CR; + + /* + * Initialize the COMBLK used to communicate with the System Controller. + */ + MSS_COMBLK_init(asynchronous_event_handler, g_response); +} + +/*============================================================================== + * See mss_sys_services.h for details. + */ +/* Tamper attempt/failure range */ +#define TAMPER_ATTEMPT_DETECT_OPCODE_RANGE_MIN 0x80u +#define TAMPER_ATTEMPT_DETECT_OPCODE_RANGE_MAX 0x8Fu +#define TAMPER_FAILURE_DETECT_OPCODE_RANGE_MIN 0x90u +#define TAMPER_FAILURE_DETECT_OPCODE_RANGE_MAX 0x9Fu +#define TAMPER_CLOCK_MONITOR_ERROR_OPCODE 0xA0u +#define TAMPER_HARDWARE_MONITOR_ERROR_OPCODE_RANGE_MIN 0xB1u +#define TAMPER_HARDWARE_MONITOR_ERROR_OPCODE_RANGE_MAX 0xB7u + +#define FACC_GLMUX_SEL_MASK 0x00001000u +#define DELAY_MORE_THAN_10US 5000U +static void asynchronous_event_handler(uint8_t event_opcode) +{ + if (event_opcode == FLASH_FREEZE_SHUTDOWN_OPCODE) + { + uint32_t running_on_standby_clock; + volatile uint32_t timeout; + + /* + * Wait for the System Controller to switch the system's clock + * from the main clock to the standby clock. This should take place + * within 10us of receiving the shut-down event. + */ + timeout = DELAY_MORE_THAN_10US; + do + { + running_on_standby_clock = SYSREG->MSSDDR_FACC1_CR & FACC_GLMUX_SEL_MASK; + --timeout; + } + while ((running_on_standby_clock == 0U) && (timeout != 0U)); + + /* Call the user's event handler. */ + if(g_event_handler != 0) + { + g_event_handler(event_opcode, g_response[1]); + } + } + else if (event_opcode == FLASH_FREEZE_EXIT_OPCODE) + { + uint32_t running_on_standby_clock; + volatile uint32_t timeout; + + /* + * Wait for the System Controller to switch the system's clock + * from the standby clock to the main clock. This should take place + * within 10us of receiving the shut-down event. + */ + timeout = DELAY_MORE_THAN_10US; + do + { + running_on_standby_clock = SYSREG->MSSDDR_FACC1_CR & FACC_GLMUX_SEL_MASK; + --timeout; + } + while ((running_on_standby_clock != 0U) && (timeout != 0U)); + + /* Restore the clock dividers values of FACC1 register. */ + revert_clk_config(); + + if(g_event_handler != 0) + { + /* Call the user's event handler. */ + g_event_handler(event_opcode, g_response[1]); + } + } + else + { + if ((event_opcode == POR_DIGEST_ERROR_OPCODE) || \ + ((event_opcode >= TAMPER_ATTEMPT_DETECT_OPCODE_RANGE_MIN) && \ + (event_opcode <= TAMPER_FAILURE_DETECT_OPCODE_RANGE_MAX)) || \ + (event_opcode == TAMPER_CLOCK_MONITOR_ERROR_OPCODE) || \ + ((event_opcode >= TAMPER_HARDWARE_MONITOR_ERROR_OPCODE_RANGE_MIN) && \ + (event_opcode <= TAMPER_HARDWARE_MONITOR_ERROR_OPCODE_RANGE_MAX))) + { + /* + * Inform to the application that new asynchronous message is received, + * only if application call-back function is registered during + * initialization. + */ + if(g_event_handler != 0) + { + /* Call the user's event handler. */ + g_event_handler(event_opcode, g_response[1]); + } + } + } +} + +/*============================================================================== + * See mss_sys_services.h for details. + */ +uint8_t MSS_SYS_get_serial_number +( + uint8_t * p_serial_number +) +{ + uint8_t response[SERIAL_NUMBER_SERV_RESP_LENGTH]; + uint8_t status; + + status = execute_service(SERIAL_NUMBER_REQUEST_CMD, + p_serial_number, + response, + SERIAL_NUMBER_SERV_RESP_LENGTH); + + return status; +} + +/*============================================================================== + * See mss_sys_services.h for details. + */ +uint8_t MSS_SYS_get_user_code +( + uint8_t * p_user_code +) +{ + uint8_t response[USERCODE_SERV_RESP_LENGTH]; + uint8_t status; + + status = execute_service(USERCODE_REQUEST_CMD, + p_user_code, + response, + USERCODE_SERV_RESP_LENGTH); + + return status; +} + +/*============================================================================== + * See mss_sys_services.h for details. + */ +uint8_t MSS_SYS_get_design_version +( + uint8_t * p_design_version +) +{ + uint8_t response[DESIGNVER_SERV_RESP_LENGTH]; + uint8_t status; + + status = execute_service(DESIGNVER_REQUEST_CMD, + p_design_version, + response, + DESIGNVER_SERV_RESP_LENGTH); + + return status; +} + +/*============================================================================== + * See mss_sys_services.h for details. + */ +uint8_t MSS_SYS_get_device_certificate +( + uint8_t * p_device_certificate +) +{ + uint8_t response[DEVICE_CERT_SERV_RESP_LENGTH]; + uint8_t status; + + status = execute_service(DEVICE_CERTIFICATE_REQUEST_CMD, + p_device_certificate, + response, + DEVICE_CERT_SERV_RESP_LENGTH); + + return status; +} + +/*============================================================================== + * See mss_sys_services.h for details. + */ +uint8_t MSS_SYS_get_secondary_device_certificate +( + uint8_t * p_secondary_device_certificate +) +{ + uint8_t response[SECONDARY_DEVICE_CERT_SERV_RESP_LENGTH]; + uint8_t status; + + /* + * The get secondary device certificate system service is not available on + * M2S050 rev A, rev B, rev C and rev D. + */ + ASSERT(0x0000F802u != SYSREG->DEVICE_VERSION); + ASSERT(0x0001F802u != SYSREG->DEVICE_VERSION); + ASSERT(0x0002F802u != SYSREG->DEVICE_VERSION); + ASSERT(0x0003F802u != SYSREG->DEVICE_VERSION); + + status = execute_service(SECONDARY_DEVICE_CERTIFICATE_REQUEST_CMD, + p_secondary_device_certificate, + response, + SECONDARY_DEVICE_CERT_SERV_RESP_LENGTH); + + return status; +} + +/*============================================================================== + * See mss_sys_services.h for details. + */ +#define CONFIG_CLOCK_DIV_MASK 0xFFC7F103u +#define CONFIG_CLOCK_DIV_32_RATIO 0x00301CD8u + +/* Sequence array for divisor */ +uint8_t div1_seq[]={ 0x00, 0x01, 0x05, 0x07}; +uint8_t div2_seq[]={ 0x01, 0x05, 0x07}; +uint8_t div4_seq[]={ 0x02, 0x03, 0x01, 0x05, 0x07}; +uint8_t div8_seq[]={ 0x04, 0x06, 0x07}; +uint8_t div16_seq[]={ 0x05, 0x07}; +uint8_t div32_seq[]={ 0x06, 0x07 }; + +/* Divisor array is used to store the values of APB0_DIVISOR, APB1_DIVISOR, + * M3_CLK_DIVISOR and FIC64_DIVISOR bit-fields before entering flash freeze. + * This value will be used to revert back the value of FACC1 register after + * exiting from Flash Freeze/IAP/Fabric digest check. + */ +uint32_t divisor[4] = {0x00}; +volatile uint8_t ind = 0; + +static uint8_t* determine_seq(uint8_t val, uint8_t* len) +{ + uint8_t*seq; + + switch(val) + { + case 0: + seq = &div1_seq[0]; + *len = 4; + break; + + case 1: + seq = &div2_seq[0]; + *len = 3; + break; + + case 2: + seq = &div4_seq[0]; + *len = 5; + break; + + case 4: + seq = &div8_seq[0]; + *len = 3; + break; + + case 5: + seq = &div16_seq[0]; + *len = 2; + break; + + case 6: + seq = &div32_seq[0]; + *len = 2; + break; + + default: + *len = 0; + seq = NULL; + break; + } + + return seq; +} + +#define CLOCK_SWITCHING_SUCCESS 0x00u +#define CLOCK_SWITCHING_ERROR 0x01u + +/* SAR 80563 - Workaround for Glitchless Clock Multiplexer Switching Issue + * If user has requested for fabric digest check/IAP/Flash Freeze service, then + * the firmware will change the clock divisor values of FACC1 register based on + * device version to avoid Glitchless Clock Multiplexer Switching Issue. + * If the device is 010/025/050/090/150 device, Cortex-M3 firmware + * dynamically divides down fclk, pclk0, pclk1 and clk_fic64 to the divided + * by 32 versions. If the device is 05 device, firmware will load the + * divisor values in sequenced from the start setting to the divide by 32 + * setting. If the device is 060 device, then firmware will compare the + * divisor values of fclk, pclk0, pclk1 and clk_fic64, and if the divisor + * values are equal to each other, then firmware will send requested command to + * system controller otherwise return CLOCK_SWITCHING_ERROR error. + */ +static uint8_t clk_switching_fix(void) +{ + uint8_t* sequence; + uint8_t len; + volatile uint32_t g_mssddr_facc1_cr = SYSREG->MSSDDR_FACC1_CR; + uint32_t var = 0; + uint32_t temp = 0; + uint32_t device_version; + uint8_t status = CLOCK_SWITCHING_SUCCESS; + + device_version = (SYSREG->DEVICE_VERSION & 0xFFFFu); + + /* For 10/25/50/90/150 devices */ + if((0xF802u == device_version) || \ + (0xF803u == device_version) || \ + (0xF804u == device_version)|| \ + (0xF807u == device_version) || \ + (0xF806u == device_version)) + { + /* Dynamically divides down fclk, pclk0, pclk1 and clk_fic64 + * to the divided by 32 versions and M3_CLK, PCLK0, PCLK1, + * CLK_FIC64 all driven from CLK_STANDBY clock. + */ + SYSREG->MSSDDR_FACC1_CR = (SYSREG->MSSDDR_FACC1_CR & CONFIG_CLOCK_DIV_MASK) | \ + CONFIG_CLOCK_DIV_32_RATIO; + status = CLOCK_SWITCHING_SUCCESS; + } + + /* For 05 devices + * When modifying clock divisor settings on M2S005, it is necessary to + * sequence them, depending on the starting configuration. + */ + else if(0xF805u == device_version) + { + /* For APB0_DIVISOR setting */ + divisor[0] = ((g_mssddr_facc1_cr >> 2) & 0x00000007); + sequence = determine_seq(divisor[0], &len); + + for(var = 1; var < len; var++) + { + temp = SYSREG->MSSDDR_FACC1_CR; + temp &= 0xFFFFFFE3u; + temp |= ((uint32_t)(sequence[var]) << 2); + SYSREG->MSSDDR_FACC1_CR = temp; + } + + /* For APB1_DIVISOR setting */ + divisor[1] = ((g_mssddr_facc1_cr >> 5) & 0x00000007); + sequence = determine_seq(divisor[1], &len); + + for(var = 1; var < len; var++) + { + temp = SYSREG->MSSDDR_FACC1_CR; + temp &= 0xFFFFFF1Fu; + temp |= ((uint32_t)(sequence[var]) << 5); + SYSREG->MSSDDR_FACC1_CR = temp; + } + + /* For M3_CLK_DIVISOR setting */ + divisor[2] = ((g_mssddr_facc1_cr >> 9) & 0x00000007); + sequence = determine_seq(divisor[2], &len); + + for(var = 1; var < len; var++) + { + temp = SYSREG->MSSDDR_FACC1_CR; + temp &= 0xFFFFF1FFu; + temp |= ((uint32_t)(sequence[var]) << 9); + SYSREG->MSSDDR_FACC1_CR = temp; + } + + /* For FIC64_DIVISOR setting */ + divisor[3] = ((g_mssddr_facc1_cr >> 19) & 0x00000007); + sequence = determine_seq(divisor[3], &len); + for(var = 1; var < len; var++) + { + temp = SYSREG->MSSDDR_FACC1_CR; + temp &= 0xFFC7FFFFu; + temp |= ((uint32_t)(sequence[var]) << 19); + SYSREG->MSSDDR_FACC1_CR = temp; + } + + /* Set the value of FACC_GLMUX_SEL bitfield of FACC1 register to 1 so + * that M3_CLK, PCLK0, PCLK1, CLK_FIC64 all driven from CLK_STANDBY + * clock. + */ + SYSREG->MSSDDR_FACC1_CR = SYSREG->MSSDDR_FACC1_CR | 0x00001000u; + + status = CLOCK_SWITCHING_SUCCESS; + } + /* For 060 devices */ + else if(0xF808u == device_version) + { + /* The divisor setting should be such that all the divisor should be + * equal to each other and set to divide by 1,2,4,8, and 16 (but not 32) + */ + divisor[0] = ((g_mssddr_facc1_cr >> 2) & 0x00000007); + divisor[1] = ((g_mssddr_facc1_cr >> 5) & 0x00000007); + divisor[2] = ((g_mssddr_facc1_cr >> 9) & 0x00000007); + divisor[3] = ((g_mssddr_facc1_cr >> 19) & 0x00000007); + + for(var = 1; var < 4; var++) + { + if((divisor[var] != divisor[0]) || \ + (divisor[0] > 5) || (divisor[var] > 5)) + { + /* If the divisor value does meet the criteria, log the clock + * switching error. + */ + status = CLOCK_SWITCHING_ERROR; + break; + } + } + } + else + { + /* Do Nothing. */ + } + + return status; +} + +/* SAR 80563 - Workaround for Glitchless Clock Multiplexer Switching Issue + * Revert back original values of various divisor in FACC1 register after + * completing the fabric digest check/IAP/Flash Freeze service. + */ +static void revert_clk_config(void) +{ + uint8_t* sequence; + uint8_t len; + uint8_t var = 0; + uint32_t temp = 0; + uint32_t device_version; + + device_version = (SYSREG->DEVICE_VERSION & 0xFFFFu); + + /* Revert back values for 10/25/50/90/150 devices */ + if((0xF802u == device_version) || (0xF803u == device_version) || \ + (0xF804u == device_version)||(0xF807u == device_version) || \ + (0xF806u == device_version)) + { + /* Restore the MSS clock dividers to their normal operations value. */ + SYSREG->MSSDDR_FACC1_CR = g_initial_mssddr_facc1_cr; + } + + /* Revert back values for 05 devices in reverse sequence. */ + else if(0xF805u == device_version) + { + sequence = determine_seq(divisor[0], &len); + for(var = len; var > 0; var--) + { + temp = SYSREG->MSSDDR_FACC1_CR; + temp &= 0xFFFFFFE3u; + temp |= ((uint32_t)(sequence[var - 1]) << 2); + SYSREG->MSSDDR_FACC1_CR = temp; + } + + /* For APB1_DIVISOR setting */ + sequence = determine_seq(divisor[1], &len); + for(var = len; var > 0; var--) + { + temp = SYSREG->MSSDDR_FACC1_CR; + temp &= 0xFFFFFF1Fu; + temp |= ((uint32_t)(sequence[var - 1]) << 5); + SYSREG->MSSDDR_FACC1_CR = temp; + } + + /* For M3_CLK_DIVISOR setting */ + sequence = determine_seq(divisor[2], &len); + for(var = len; var > 0; var--) + { + temp = SYSREG->MSSDDR_FACC1_CR; + temp &= 0xFFFFF1FFu; + temp |= ((uint32_t)(sequence[var - 1]) << 9); + SYSREG->MSSDDR_FACC1_CR = temp; + } + + /* For FIC64_DIVISOR setting */ + sequence = determine_seq(divisor[3], &len); + for(var = len; var > 0; var--) + { + temp = SYSREG->MSSDDR_FACC1_CR; + temp &= 0xFFC7FFFFu; + temp |= ((uint32_t)(sequence[var - 1]) << 19); + SYSREG->MSSDDR_FACC1_CR = temp; + } + + /* Set the value of FACC_GLMUX_SEL bitfield of FACC1 register to 0 so + * that M3_CLK, PCLK0, PCLK1, CLK_FIC64 all driven from stage 2 + * dividers (from CLK_SRC). + */ + SYSREG->MSSDDR_FACC1_CR = SYSREG->MSSDDR_FACC1_CR & 0xFFFFEFFFu; + } + else + { + /* Do Nothing. */ + } +} + +uint8_t MSS_SYS_flash_freeze(uint8_t options) +{ + uint8_t status; + uint8_t clk_switch_status = CLOCK_SWITCHING_SUCCESS; + uint16_t actual_response_length; + uint8_t flash_freeze_req[FLASH_FREEZE_REQUEST_LENGTH]; + uint8_t response[FLASH_FREEZE_SERV_RESP_LENGTH]; + + /* + * The Flash Freeze system service is not available on M2S050 rev A and rev B. + */ + ASSERT(0x0000F802u != SYSREG->DEVICE_VERSION); + ASSERT(0x0001F802u != SYSREG->DEVICE_VERSION); + + /* + * Keep track of the clocks configuration before entering Flash*Freeze so + * that it can be restored on Flash*Freeze exit. + */ + g_initial_mssddr_facc1_cr = SYSREG->MSSDDR_FACC1_CR; + + /* SAR 80563 + * Cortex-M3 firmware dynamically divides down fclk, pclk0, pclk1 and + * clk_fic64 to the divided by 32 versions based on device version. + */ + clk_switch_status = clk_switching_fix(); + + if(clk_switch_status == CLOCK_SWITCHING_SUCCESS) + { + /* + * Enable RTC wake-up interrupt to System Controller and FPGA fabric. + */ + SYSREG->RTC_WAKEUP_CR |= (RTC_WAKEUP_G4C_EN_MASK | RTC_WAKEUP_FAB_EN_MASK); + + signal_request_start(); + + flash_freeze_req[0] = FLASH_FREEZE_REQUEST_CMD; + flash_freeze_req[1] = options; + + MSS_COMBLK_send_cmd(flash_freeze_req, /* p_cmd */ + FLASH_FREEZE_REQUEST_LENGTH, /* cmd_size */ + 0, /* p_data */ + 0u, /* data_size */ + response, /* p_response */ + FLASH_FREEZE_SERV_RESP_LENGTH, /* response_size */ + request_completion_handler); /* completion_handler */ + + actual_response_length = wait_for_request_completion(); + + if((FLASH_FREEZE_SERV_RESP_LENGTH == actual_response_length) && + (FLASH_FREEZE_REQUEST_CMD == response[0])) + { + status = response[1]; + } + else + { + status = MSS_SYS_UNEXPECTED_ERROR; + } + } + else + { + /* SAR 80563 + * CLK Divisor error occurs on 060 device. The user should make sure + * that the all divisor i.e fclk, pclk0, pclk1 and clk_fic64 divisor + * must be equal to each other and set to to divide by 1,2, 4, 8, 16(but + * not 32). If the divisor value does not meet the above criteria, the + * function will not send Flash Freeze command to system controller and + * will return CLK divisor error. + */ + status = MSS_SYS_CLK_DIVISOR_ERROR; + } + + return status; +} + +/*============================================================================== + * See mss_sys_services.h for details. + */ +#define AES128_KEY_LENGTH 16u +#define IV_LENGTH 16u + +#define AES256_KEY_LENGTH 32u + +#define HMAC_KEY_LENGTH 32u + +uint8_t MSS_SYS_128bit_aes +( + const uint8_t * key, + const uint8_t * iv, + uint16_t nb_blocks, + uint8_t mode, + uint8_t * dest_addr, + const uint8_t * src_addr) +{ + uint8_t response[STANDARD_SERV_RESP_LENGTH]; + uint8_t params[44]; + uint8_t status; + + memcpy(¶ms[0], key, AES128_KEY_LENGTH); + memcpy(¶ms[16], iv, IV_LENGTH); + + params[32] = (uint8_t)nb_blocks; + params[33] = (uint8_t)(nb_blocks >> 8u); + params[34] = mode; + params[35] = 0u; + + write_ptr_value_into_array(dest_addr, params, 36u); + write_ptr_value_into_array(src_addr, params, 40u); + + status = execute_service(AES128_REQUEST_CMD, + params, + response, + STANDARD_SERV_RESP_LENGTH); + + return status; +} + +/*============================================================================== + * See mss_sys_services.h for details. + */ +uint8_t MSS_SYS_256bit_aes +( + const uint8_t * key, + const uint8_t * iv, + uint16_t nb_blocks, + uint8_t mode, + uint8_t * dest_addr, + const uint8_t * src_addr +) +{ + uint8_t response[STANDARD_SERV_RESP_LENGTH]; + uint8_t params[60]; + uint8_t status; + + memcpy(¶ms[0], key, AES256_KEY_LENGTH); + memcpy(¶ms[32], iv, IV_LENGTH); + + params[48] = (uint8_t)nb_blocks; + params[49] = (uint8_t)(nb_blocks >> 8u); + params[50] = mode; + params[51] = 0u; + + write_ptr_value_into_array(dest_addr, params, 52u); + write_ptr_value_into_array(src_addr, params, 56u); + + status = execute_service(AES256_REQUEST_CMD, + params, + response, + STANDARD_SERV_RESP_LENGTH); + + return status; +} + +/*============================================================================== + * See mss_sys_services.h for details. + */ +uint8_t MSS_SYS_sha256 +( + const uint8_t * p_data_in, + uint32_t length, + uint8_t * result +) +{ + uint8_t response[STANDARD_SERV_RESP_LENGTH]; + uint8_t params[12]; + uint8_t status; + + params[0] = (uint8_t)((uint32_t)length); + params[1] = (uint8_t)((uint32_t)length >> 8u); + params[2] = (uint8_t)((uint32_t)length >> 16u); + params[3] = (uint8_t)((uint32_t)length >> 24u); + + write_ptr_value_into_array(result, params, 4u); + write_ptr_value_into_array(p_data_in, params, 8u); + + status = execute_service(SHA256_REQUEST_CMD, + params, + response, + STANDARD_SERV_RESP_LENGTH); + + return status; +} + +/*============================================================================== + * See mss_sys_services.h for details. + */ +uint8_t MSS_SYS_hmac +( + const uint8_t * key, + const uint8_t * p_data_in, + uint32_t length, + uint8_t * p_result +) +{ + uint8_t response[STANDARD_SERV_RESP_LENGTH]; + uint8_t params[58]; + uint8_t status; + + memcpy(¶ms[0], key, HMAC_KEY_LENGTH); + + params[32] = (uint8_t)((uint32_t)length); + params[33] = (uint8_t)((uint32_t)length >> 8u); + params[34] = (uint8_t)((uint32_t)length >> 16u); + params[35] = (uint8_t)((uint32_t)length >> 24u); + + write_ptr_value_into_array(p_data_in, params, 36u); + write_ptr_value_into_array(p_result, params, 40u); + + status = execute_service(HMAC_REQUEST_CMD, + params, + response, + STANDARD_SERV_RESP_LENGTH); + + return status; +} + +/*============================================================================== + * See mss_sys_services.h for details. + */ +#define KEYTREE_KEY_LENGTH 32 +#define KEYTREE_PATH_LENGTH 16 + +uint8_t MSS_SYS_key_tree +( + uint8_t* p_key, + uint8_t op_type, + const uint8_t* path +) +{ + uint8_t response[STANDARD_SERV_RESP_LENGTH]; + uint8_t params[49]; + uint8_t status; + + memcpy(¶ms[0], p_key, KEYTREE_KEY_LENGTH); + + params[32] = op_type; + + memcpy(¶ms[33], path, KEYTREE_PATH_LENGTH); + + status = execute_service(KEYTREE_REQUEST_CMD, + params, + response, + STANDARD_SERV_RESP_LENGTH); + + if(status == MSS_SYS_SUCCESS) + { + memcpy(p_key, ¶ms[0], KEYTREE_KEY_LENGTH); + } + + return status; +} + +/*============================================================================== + * See mss_sys_services.h for details. + */ +uint8_t MSS_SYS_challenge_response +( + uint8_t* p_key, + uint8_t op_type, + const uint8_t* path +) +{ + uint8_t response[STANDARD_SERV_RESP_LENGTH]; + uint8_t params[21]; + uint8_t status; + + params[0] = (uint8_t)((uint32_t)p_key); + params[1] = (uint8_t)((uint32_t)p_key >> 8u); + params[2] = (uint8_t)((uint32_t)p_key >> 16u); + params[3] = (uint8_t)((uint32_t)p_key >> 24u); + + params[4] = op_type; + + memcpy(¶ms[5], path, KEYTREE_PATH_LENGTH); + + status = execute_service(PPUF_CHALLENGE_RESP_REQUEST_CMD, + params, + response, + STANDARD_SERV_RESP_LENGTH); + + return status; +} + +/*============================================================================== + * See mss_sys_services.h for details. + */ +uint8_t MSS_SYS_nrbg_reset(void) +{ + uint8_t status; + uint16_t actual_response_length; + uint8_t reset_cmd[4]; + uint8_t response[NRBG_RESET_SERV_RESP_LENGTH]; + + signal_request_start(); + + reset_cmd[0] = NRBG_RESET_REQUEST_CMD; + reset_cmd[1] = 0u; + reset_cmd[2] = 0u; + reset_cmd[3] = 0u; + + MSS_COMBLK_send_cmd(reset_cmd, /* p_cmd */ + sizeof(reset_cmd), /* cmd_size */ + 0, /* p_data */ + 0, /* data_size */ + response, /* p_response */ + DRBG_RESET_SERV_RESP_LENGTH, /* response_size */ + request_completion_handler); /* completion_handler */ + + actual_response_length = wait_for_request_completion(); + + if((NRBG_RESET_SERV_RESP_LENGTH == actual_response_length) && + (NRBG_RESET_REQUEST_CMD == response[0])) + { + status = response[1]; + } + else + { + status = MSS_SYS_UNEXPECTED_ERROR; + } + + return status; +} + +/*============================================================================== + * See mss_sys_services.h for details. + */ +uint8_t MSS_SYS_nrbg_self_test(void) +{ + uint8_t status; + uint16_t actual_response_length; + uint8_t self_test; + uint8_t response[NRBG_SELF_TEST_SERV_RESP_LENGTH]; + + signal_request_start(); + + self_test = NRBG_SELF_TEST_REQUEST_CMD; + + MSS_COMBLK_send_cmd(&self_test, /* p_cmd */ + sizeof(self_test), /* cmd_size */ + 0, /* p_data */ + 0, /* data_size */ + response, /* p_response */ + NRBG_SELF_TEST_SERV_RESP_LENGTH, /* response_size */ + request_completion_handler); /* completion_handler */ + + actual_response_length = wait_for_request_completion(); + + if((NRBG_SELF_TEST_SERV_RESP_LENGTH == actual_response_length) && + (NRBG_SELF_TEST_REQUEST_CMD == response[0])) + { + status = response[1]; + } + else + { + status = MSS_SYS_UNEXPECTED_ERROR; + } + + return status; +} + +/*============================================================================== + * See mss_sys_services.h for details. + */ +uint8_t MSS_SYS_nrbg_instantiate +( + const uint8_t * personalization_str, + uint16_t personalization_str_length, + uint8_t * p_nrbg_handle +) +{ + uint8_t response[STANDARD_SERV_RESP_LENGTH]; + uint8_t instantiate_params[7]; + uint8_t status; + + write_ptr_value_into_array(personalization_str, instantiate_params, 0u); + + instantiate_params[4] = (uint8_t)personalization_str_length; + instantiate_params[5] = (uint8_t)(personalization_str_length >> 8u); + instantiate_params[6] = INVALID_NRBG_HANDLE; + + status = execute_service(NRBG_INSTANTIATE_REQUEST_CMD, + instantiate_params, + response, + STANDARD_SERV_RESP_LENGTH); + + if(MSS_SYS_SUCCESS == status) + { + *p_nrbg_handle = instantiate_params[6]; + } + + return status; +} + +/*============================================================================== + * See mss_sys_services.h for details. + */ +uint8_t MSS_SYS_nrbg_generate +( + const uint8_t * p_requested_data, + const uint8_t * p_additional_input, + uint8_t requested_length, + uint8_t additional_input_length, + uint8_t pr_req, + uint8_t nrbg_handle +) +{ + uint8_t response[STANDARD_SERV_RESP_LENGTH]; + uint8_t generate_params[12]; + uint8_t status; + + write_ptr_value_into_array(p_requested_data, generate_params, 0u); + write_ptr_value_into_array(p_additional_input, generate_params, 4u); + + generate_params[8] = requested_length; + generate_params[9] = additional_input_length; + generate_params[10] = pr_req; + generate_params[11] = nrbg_handle; + + status = execute_service(NRBG_GENERATE_REQUEST_CMD, + generate_params, + response, + STANDARD_SERV_RESP_LENGTH); + + return status; +} + +/*============================================================================== + * See mss_sys_services.h for details. + */ +uint8_t MSS_SYS_nrbg_reseed +( + const uint8_t * p_additional_input, + uint8_t additional_input_length, + uint8_t nrbg_handle +) +{ + uint8_t response[STANDARD_SERV_RESP_LENGTH]; + uint8_t params[6]; + uint8_t status; + + write_ptr_value_into_array(p_additional_input, params, 0u); + + params[4] = (uint8_t)additional_input_length; + params[5] = nrbg_handle; + + status = execute_service(NRBG_RESEED_REQUEST_CMD, + params, + response, + STANDARD_SERV_RESP_LENGTH); + + return status; +} + +/*============================================================================== + * See mss_sys_services.h for details. + */ +uint8_t MSS_SYS_nrbg_uninstantiate +( + uint8_t nrbg_handle +) +{ + uint8_t status; + uint16_t actual_response_length; + uint8_t uninstantiate_req[2]; + uint8_t response[NRBG_UNINST_SERV_RESP_LENGTH]; + + signal_request_start(); + + uninstantiate_req[0] = NRBG_UNINSTANTIATE_REQUEST_CMD; + uninstantiate_req[1] = nrbg_handle; + + MSS_COMBLK_send_cmd(uninstantiate_req, /* p_cmd */ + sizeof(uninstantiate_req), /* cmd_size */ + 0, /* p_data */ + 0, /* data_size */ + response, /* p_response */ + NRBG_UNINST_SERV_RESP_LENGTH, /* response_size */ + request_completion_handler); /* completion_handler */ + + actual_response_length = wait_for_request_completion(); + + if((NRBG_UNINST_SERV_RESP_LENGTH == actual_response_length) && + (NRBG_UNINSTANTIATE_REQUEST_CMD == response[0])) + { + status = response[1]; + } + else + { + status = MSS_SYS_UNEXPECTED_ERROR; + } + + return status; +} + +/*============================================================================== + * See mss_sys_services.h for details. + */ +void MSS_SYS_zeroize_device(void) +{ + /* + * We only need to send one command byte to initiate zeroization. + * The zeroization process should result in the Cortex-M3 being reset. This + * means we should never reach the end of this function if zeroization is + * actually performed. + */ + uint8_t zeroization_req = ZEROIZATION_REQUEST_CMD; + + /* + * The Zeroization system service is not available on M2S050 rev A, rev B + * and rev C. + */ + ASSERT(0x0000F802u != SYSREG->DEVICE_VERSION); + ASSERT(0x0001F802u != SYSREG->DEVICE_VERSION); + ASSERT(0x0002F802u != SYSREG->DEVICE_VERSION); + + signal_request_start(); + + MSS_COMBLK_send_cmd(&zeroization_req, /* p_cmd */ + sizeof(zeroization_req), /* cmd_size */ + 0, /* p_data */ + 0, /* data_size */ + 0, /* p_response */ + 0, /* response_size */ + request_completion_handler); /* completion_handler */ + + /* SAR 74647 + * Zeroization is only performed if the user has instantiated the tamper + * macro (from the Libero Catalog) in the hardware design, configured the + * tamper macro to enable zeroization and set the required zeroization + * options. If program execution idles here, or in the + * wait_for_request_completion() function that follows, you should verify + * that zeroization is properly enabled in the hardware design. + */ + ASSERT(g_request_in_progress == 0u); + + /* + * Handle case where Zeroization is not enabled in the device in Release + * mode. + */ + wait_for_request_completion(); +} + +/*============================================================================== + * See mss_sys_services.h for details. + */ +#define NVM_FREQRNG_MASK 0x00001FE0U +#define NVM_FREQRNG_MAX ((uint32_t)0xFFU << 5U) + +static uint8_t g_isp_response[ISP_PROG_SERV_RESP_LENGTH]; +sys_serv_isp_complete_handler_t g_isp_completion_handler = 0; +comblk_page_handler_t g_isp_page_read_handler = 0; + +/* + * g_initial_envm_cr contains the hardware design's original eNVM configuration + * set through the ENVM_CR system register. This global variable is used to + * store the eNVM's configuration while the ISP/IAP is executing with an eNVM + * configuration ensuring successful eNVM programming on all SamrtFusion2 + * devices. It is then used to restore the eNVM's configuration once ISP/IAP has + * completed. SAR 57545. + */ +static uint32_t g_initial_envm_cr = 0x00001FF1U; +/* + * g_initial_mssddr_facc2_cr contains the hardware design's original MSS DDR + * Fabric Alignment Clock Controller (FACC) 2 configuration set through the + * MSSDDR_FACC2_CR system register. This global variable is used to + * store the FACC2's configuration while the ISP/IAP is executing on all + * SamrtFusion2 devices. It is then used to restore the Fabric alignment clock + * configuration once ISP/IAP has completed. + */ +static uint32_t g_initial_mssddr_facc2_cr = 0x00; +static uint8_t g_mode = 0; +static uint8_t wait_for_clock_switch = 1; + +static uint32_t isp_page_read_handler +( + uint8_t const ** pp_next_page +) +{ + uint32_t remaining_length = 0; + uint32_t running_on_standby_clock; + volatile uint32_t timeout; + + if((g_mode != MSS_SYS_PROG_AUTHENTICATE) & (wait_for_clock_switch == 1)) + { + timeout = DELAY_MORE_THAN_10US; + do + { + running_on_standby_clock = SYSREG->MSSDDR_FACC1_CR & FACC_GLMUX_SEL_MASK; + --timeout; + } + while ((running_on_standby_clock == 0U) && (timeout != 0U)); + wait_for_clock_switch = 0; + } + + if(g_isp_page_read_handler != 0) + { + remaining_length = g_isp_page_read_handler(pp_next_page); + } + + return remaining_length; +} + +static void isp_sys_completion_handler +( + uint8_t * p_response, + uint16_t length +) +{ + if(g_mode != MSS_SYS_PROG_AUTHENTICATE) + { + /* + * Restore the eNVM's frequency range to the values used before ISP was + * started. + */ + SYSREG->ENVM_CR = g_initial_envm_cr; + + /* + * Restore the MSS DDR FACC 2 configuration to the values used before ISP + * was started. + */ + SYSREG->MSSDDR_FACC2_CR = g_initial_mssddr_facc2_cr; + } + + if(g_isp_completion_handler != 0) + { + g_isp_completion_handler(p_response[1]); + } +} + +uint8_t MSS_SYS_start_isp +( + uint8_t mode, + comblk_page_handler_t page_read_handler, + sys_serv_isp_complete_handler_t isp_completion_handler +) +{ + uint8_t isp_prog_request[2]; + uint8_t clk_switch_status = CLOCK_SWITCHING_SUCCESS; + uint8_t status = MSS_SYS_SUCCESS; + + if(mode == MSS_SYS_PROG_VERIFY) + { + /* + * Check fabric digest before performing ISP verify + */ + MSS_SYS_check_digest(MSS_SYS_DIGEST_CHECK_FABRIC); + } + + g_mode = mode; + + if(mode != MSS_SYS_PROG_AUTHENTICATE) + { + /* + * Keep a copy of the initial eNVM configuration used before ISP was + * initiated. The eNVM configuration will be restored, as part of the ISP + * completion handler, when ISP completes. + */ + g_initial_envm_cr = SYSREG->ENVM_CR; + + /* Store the MSS DDR FACC 2 register value so that its can be restored back + * when the ISP operation is completed in asynchronous_event_handler. */ + g_initial_mssddr_facc2_cr = SYSREG->MSSDDR_FACC2_CR; + + /* + * Set the eNVM's frequency range to its maximum. This is required to ensure + * successful eNVM programming on all devices. + */ + SYSREG->ENVM_CR = (g_initial_envm_cr & ~NVM_FREQRNG_MASK) | NVM_FREQRNG_MAX; + + /* Select output of MUX 0, MUX 1 and MUX 2 during standby */ + SYSREG->MSSDDR_FACC2_CR = SYSREG->MSSDDR_FACC2_CR & ((uint32_t)(FACC_STANDBY_SEL << FACC_STANDBY_SHIFT) | ~FACC_STANDBY_SEL_MASK); + + /* Enable the signal for the 50 MHz RC oscillator */ + SYSREG->MSSDDR_FACC2_CR = SYSREG->MSSDDR_FACC2_CR | ((uint32_t)(MSS_25_50MHZ_EN << MSS_25_50MHZ_EN_SHIFT) & MSS_25_50MHZ_EN_MASK); + + /* Enable the signal for the 1 MHz RC oscillator */ + SYSREG->MSSDDR_FACC2_CR = SYSREG->MSSDDR_FACC2_CR | ((uint32_t)(MSS_1MHZ_EN << MSS_1MHZ_EN_SHIFT) & MSS_1MHZ_EN_MASK); + + /* SAR 80563 + * Cortex-M3 firmware dynamically divides down fclk, pclk0, pclk1 and + * clk_fic64 to the divided by 32 versions based on device version. + */ + clk_switch_status = clk_switching_fix(); + + wait_for_clock_switch = 1; + } + + if(clk_switch_status == CLOCK_SWITCHING_SUCCESS) + { + signal_request_start(); + + isp_prog_request[0] = ISP_PROGRAMMING_REQUEST_CMD; + isp_prog_request[1] = mode; + + g_isp_completion_handler = isp_completion_handler; + + g_isp_page_read_handler = page_read_handler; + + MSS_COMBLK_send_paged_cmd(isp_prog_request, /* p_cmd */ + sizeof(isp_prog_request), /* cmd_size */ + g_isp_response, /* p_response */ + ISP_PROG_SERV_RESP_LENGTH, /* response_size */ + isp_page_read_handler, /* page_handler */ + isp_sys_completion_handler); /* completion_handler */ + } + else + { + /* SAR 80563 + * On 060 device. The user should make sure that the all divisor i.e + * fclk, pclk0, pclk1 and clk_fic64 divisor must be equal to each other + * and set to to divide by 1,2, 4, 8, 16(but not 32). + */ + status = MSS_SYS_CLK_DIVISOR_ERROR; + } + + return status; +} + + +/*============================================================================== + * See mss_sys_services.h for details. + */ +uint8_t MSS_SYS_initiate_iap +( + uint8_t mode, + uint32_t bitstream_spi_addr +) +{ + uint8_t status = MSS_SYS_SUCCESS; + uint8_t clk_switch_status = CLOCK_SWITCHING_SUCCESS; + uint16_t actual_response_length; + uint8_t iap_prog_req[6]; + uint8_t response[IAP_PROG_SERV_RESP_LENGTH]; + + if(mode == MSS_SYS_PROG_VERIFY) + { + /* + * Check fabric digest before performing IAP verify + */ + MSS_SYS_check_digest(MSS_SYS_DIGEST_CHECK_FABRIC); + } + + if(mode != MSS_SYS_PROG_AUTHENTICATE) + { + /* + * Keep a copy of the initial eNVM configuration used before IAP was + * initiated. The eNVM configuration will be restored, as part of the IAP + * completion handler, when IAP completes. + */ + g_initial_envm_cr = SYSREG->ENVM_CR; + + /* Store the MSS DDR FACC 2 register value so that its can be restored back + * when the IAP operation is completed.asynchronous_event_handler. */ + g_initial_mssddr_facc2_cr = SYSREG->MSSDDR_FACC2_CR; + + /* + * Set the eNVM's frequency range to its maximum. This is required to ensure + * successful eNVM programming on all devices. + */ + SYSREG->ENVM_CR = (g_initial_envm_cr & ~NVM_FREQRNG_MASK) | NVM_FREQRNG_MAX; + + /* Select output of MUX 0, MUX 1 and MUX 2 during standby */ + SYSREG->MSSDDR_FACC2_CR = SYSREG->MSSDDR_FACC2_CR & ((uint32_t)(FACC_STANDBY_SEL << FACC_STANDBY_SHIFT) | ~FACC_STANDBY_SEL_MASK); + + /* Enable the signal for the 50 MHz RC oscillator */ + SYSREG->MSSDDR_FACC2_CR = SYSREG->MSSDDR_FACC2_CR | ((uint32_t)(MSS_25_50MHZ_EN << MSS_25_50MHZ_EN_SHIFT) & MSS_25_50MHZ_EN_MASK); + + /* Enable the signal for the 1 MHz RC oscillator */ + SYSREG->MSSDDR_FACC2_CR = SYSREG->MSSDDR_FACC2_CR | ((uint32_t)(MSS_1MHZ_EN << MSS_1MHZ_EN_SHIFT) & MSS_1MHZ_EN_MASK); + + /* SAR 80563 + * Cortex-M3 firmware dynamically divides down fclk, pclk0, pclk1 and + * clk_fic64 to the divided by 32 versions based on device version. + */ + clk_switch_status = clk_switching_fix(); + } + + if(clk_switch_status == CLOCK_SWITCHING_SUCCESS) + { + /* + * There is no response for Program mode because the Cortex-M3 will + * get reset on completion of the system service. + */ + iap_prog_req[0] = IAP_PROGRAMMING_REQUEST_CMD; + iap_prog_req[1] = mode; + + iap_prog_req[2] = (uint8_t)(bitstream_spi_addr); + iap_prog_req[3] = (uint8_t)(bitstream_spi_addr >> 8u); + iap_prog_req[4] = (uint8_t)(bitstream_spi_addr >> 16u); + iap_prog_req[5] = (uint8_t)(bitstream_spi_addr >> 24u); + + signal_request_start(); + + MSS_COMBLK_send_cmd(iap_prog_req, /* p_cmd */ + sizeof(iap_prog_req), /* cmd_size */ + 0, /* p_data */ + 0, /* data_size */ + response, /* p_response */ + IAP_PROG_SERV_RESP_LENGTH, /* response_size */ + request_completion_handler); /* completion_handler */ + + /* + * Handle case where service is not implemented/enabled in the device. + */ + actual_response_length = wait_for_request_completion(); + + if((IAP_PROG_SERV_RESP_LENGTH == actual_response_length) && + (IAP_PROGRAMMING_REQUEST_CMD == response[0])) + { + status = response[1]; + } + else + { + status = MSS_SYS_UNEXPECTED_ERROR; + } + + if(mode != MSS_SYS_PROG_AUTHENTICATE) + { + /* Restore back to original value. */ + SYSREG->ENVM_CR = g_initial_envm_cr; + SYSREG->MSSDDR_FACC2_CR = g_initial_mssddr_facc2_cr; + } + } + else + { + /* SAR 80563 + * On 060 device. The user should make sure that the all divisor i.e + * fclk, pclk0, pclk1 and clk_fic64 divisor must be equal to each other + * and set to to divide by 1,2, 4, 8, 16(but not 32). + */ + status = MSS_SYS_CLK_DIVISOR_ERROR; + } + + return status; +} + +/*============================================================================== + * See mss_sys_services.h for details. + */ +uint8_t MSS_SYS_check_digest +( + uint8_t options +) +{ + uint8_t status; + uint8_t clk_switch_status = CLOCK_SWITCHING_SUCCESS; + uint16_t actual_response_length; + uint8_t digest_check_req[2]; + uint8_t response[DIGEST_CHECK_SERV_RESP_LENGTH]; + + /* + * The Digest Check system service is not available on M2S050 rev A, rev B and rev C. + */ + ASSERT(0x0000F802u != SYSREG->DEVICE_VERSION); + ASSERT(0x0001F802u != SYSREG->DEVICE_VERSION); + ASSERT(0x0002F802u != SYSREG->DEVICE_VERSION); + + /* + * Private ENVM factory digest and user digest is available only on G4X + * devices + */ + if((options & 0x30u) != 0x00) + { + ASSERT(0x0002F802u != SYSREG->DEVICE_VERSION); + } + + /* SAR 80563 + * Cortex-M3 firmware dynamically divides down fclk, pclk0, pclk1 and + * clk_fic64 to the divided by 32 versions based on device version. + */ + if(MSS_SYS_DIGEST_CHECK_FABRIC == (options & 0x01u)) + { + clk_switch_status = clk_switching_fix(); + } + + if(clk_switch_status == CLOCK_SWITCHING_SUCCESS) + { + + signal_request_start(); + + digest_check_req[0] = DIGEST_CHECK_REQUEST_CMD; + digest_check_req[1] = options; + + MSS_COMBLK_send_cmd(digest_check_req, /* p_cmd */ + sizeof(digest_check_req), /* cmd_size */ + 0, /* p_data */ + 0u, /* data_size */ + response, /* p_response */ + DIGEST_CHECK_SERV_RESP_LENGTH, /* response_size */ + request_completion_handler); /* completion_handler */ + + actual_response_length = wait_for_request_completion(); + + if((DIGEST_CHECK_SERV_RESP_LENGTH == actual_response_length) && + (DIGEST_CHECK_REQUEST_CMD == response[0])) + { + status = response[1]; + } + else + { + status = MSS_SYS_UNEXPECTED_ERROR; + } + } + else + { + /* SAR 80563 + * On 060 device. The user should make sure that the all divisor i.e + * fclk, pclk0, pclk1 and clk_fic64 divisor must be equal to each other + * and set to to divide by 1,2, 4, 8, 16(but not 32). + */ + status = MSS_SYS_CLK_DIVISOR_ERROR; + } + + return status; +} + +/*============================================================================== + * See mss_sys_services.h for details. + */ +uint8_t MSS_SYS_puf_create_activation_code +( + void +) +{ + uint8_t response[PUF_USER_ACTIVATION_CODE_RESP_LENGTH]; + uint8_t status; + uint8_t params; + uint8_t key_numbers = 0u; + + /* + * The user activation code system service is not available on M2S050 rev A, + * rev B, rev C and rev D. + */ + ASSERT(0x0000F802u != SYSREG->DEVICE_VERSION); + ASSERT(0x0001F802u != SYSREG->DEVICE_VERSION); + ASSERT(0x0002F802u != SYSREG->DEVICE_VERSION); + ASSERT(0x0003F802u != SYSREG->DEVICE_VERSION); + + params = PUF_CREATE_USER_ACTIVATION_CODE; + + status = execute_service(PUF_ACTIVATION_CODE_REQUEST_CMD, + ¶ms, + response, + PUF_USER_ACTIVATION_CODE_RESP_LENGTH); + + /* + * System controller is locking eNVM-1 while executing create activation + * code service, but system controller is not releasing back after + * completing the operation. In order to unlock eNVM-1, call get number of + * key service. PUF get number of key service will release the eNVM-1 lock + * after reading the number of keys enrolled. + */ + MSS_SYS_puf_get_number_of_keys(&key_numbers); + + return status; +} + +/*============================================================================== + * See mss_sys_services.h for details. + */ +uint8_t MSS_SYS_puf_delete_activation_code +( + void +) +{ + uint8_t response[PUF_USER_ACTIVATION_CODE_RESP_LENGTH]; + uint8_t status; + uint8_t params; + uint8_t key_numbers = 0u; + + /* + * The user activation code system service is not available on M2S050 rev A, + * rev B, rev C and rev D. + */ + ASSERT(0x0000F802u != SYSREG->DEVICE_VERSION); + ASSERT(0x0001F802u != SYSREG->DEVICE_VERSION); + ASSERT(0x0002F802u != SYSREG->DEVICE_VERSION); + ASSERT(0x0003F802u != SYSREG->DEVICE_VERSION); + + params = PUF_DELETE_USER_ACTIVATION_CODE; + + status = execute_service(PUF_ACTIVATION_CODE_REQUEST_CMD, + ¶ms, + response, + PUF_USER_ACTIVATION_CODE_RESP_LENGTH); + /* + * System controller is locking eNVM-1 while executing delete activation + * code service, but system controller is not releasing back after + * completing the operation. In order to unlock eNVM-1, call get number of + * key service. PUF get number of key service will release the eNVM-1 lock + * after reading the number of keys enrolled. + */ + MSS_SYS_puf_get_number_of_keys(&key_numbers); + + return status; +} + +/*============================================================================== + * See mss_sys_services.h for details. + */ +uint8_t MSS_SYS_puf_get_number_of_keys +( + uint8_t* p_number_of_keys +) +{ + uint8_t response[6u] = { 0x00 }; + uint8_t params[11u] = { 0x00 }; + uint8_t status; + + /* + * The user key code system service is not available on M2S050 rev A, + * rev B, rev C and rev D. + */ + ASSERT(0x0000F802u != SYSREG->DEVICE_VERSION); + ASSERT(0x0001F802u != SYSREG->DEVICE_VERSION); + ASSERT(0x0002F802u != SYSREG->DEVICE_VERSION); + ASSERT(0x0003F802u != SYSREG->DEVICE_VERSION); + + params[0] = PUF_GET_NUMBER_OF_KC_SUBCOMMAND; + + status = execute_service(PUF_USER_KEY_CODE_REQUEST_CMD, + params, + response, + PUF_GET_NUMBER_OF_KEYS_RESP_LENGTH); + + *p_number_of_keys = params[9]; + + return status; +} + +/*============================================================================== + * See mss_sys_services.h for details. + */ +uint8_t MSS_SYS_puf_enroll_key +( + uint8_t key_number, + uint16_t key_size, + uint8_t* p_key_value, + uint8_t* p_key_location +) +{ + uint8_t response[6u]; + uint8_t params[11u]; + uint8_t status; + uint8_t key_numbers = 0u; + + /* + * The PUF enroll key system service is not available on M2S050 rev A, + * rev B, rev C and rev D. + */ + ASSERT(0x0000F802u != SYSREG->DEVICE_VERSION); + ASSERT(0x0001F802u != SYSREG->DEVICE_VERSION); + ASSERT(0x0002F802u != SYSREG->DEVICE_VERSION); + ASSERT(0x0003F802u != SYSREG->DEVICE_VERSION); + + if(p_key_value == 0) + { + params[0] = PUF_CREATE_INT_KC_SUBCOMMAND; + } + else + { + params[0] = PUF_CREATE_EXT_KC_SUBCOMMAND; + } + + write_ptr_value_into_array(p_key_location, params, 1u); + write_ptr_value_into_array(p_key_value, params, 5u); + + params[9] = key_number; + params[10] = key_size; + + status = execute_service(PUF_USER_KEY_CODE_REQUEST_CMD, + params, + response, + PUF_ENROLL_KEYS_RESP_LENGTH); + + /* + * System controller is locking eNVM-1 while executing create key code + * service, but system controller is not releasing back after completing the + * operation. In order to unlock eNVM-1, call get number of key service. PUF + * get number of key service will release the eNVM-1 lock after reading the + * number of keys enrolled. + */ + MSS_SYS_puf_get_number_of_keys(&key_numbers); + + return status; +} + +/*============================================================================== + * See mss_sys_services.h for details. + */ +uint8_t MSS_SYS_puf_delete_key +( + uint8_t key_number +) +{ + uint8_t response[6u]; + uint8_t params[11u]; + uint8_t status; + uint8_t key_numbers = 0u; + + /* + * The delete PUF key system service is not available on M2S050 rev A, + * rev B, rev C and rev D. + */ + ASSERT(0x0000F802u != SYSREG->DEVICE_VERSION); + ASSERT(0x0001F802u != SYSREG->DEVICE_VERSION); + ASSERT(0x0002F802u != SYSREG->DEVICE_VERSION); + ASSERT(0x0003F802u != SYSREG->DEVICE_VERSION); + + params[0] = PUF_DELETE_KC_SUBCOMMAND; + params[9] = key_number; + + status = execute_service(PUF_USER_KEY_CODE_REQUEST_CMD, + params, + response, + PUF_ENROLL_KEYS_RESP_LENGTH); + + /* + * System controller is locking eNVM-1 while executing delete key code + * service, but system controller is not releasing back after completing the + * operation. In order to unlock eNVM-1, call get number of key service. PUF + * get number of key service will release the eNVM-1 lock after reading the + * number of keys enrolled. + */ + MSS_SYS_puf_get_number_of_keys(&key_numbers); + + return status; +} + +/*============================================================================== + * See mss_sys_services.h for details. + */ +uint8_t MSS_SYS_puf_fetch_key +( + uint8_t key_number, + uint8_t ** pp_key +) +{ + uint8_t response[STANDARD_SERV_RESP_LENGTH]; + uint8_t params[5]; + uint8_t status; + + /* + * The fetch user key system service is not available on M2S050 rev A, + * rev B, rev C and rev D. + */ + ASSERT(0x0000F802u != SYSREG->DEVICE_VERSION); + ASSERT(0x0001F802u != SYSREG->DEVICE_VERSION); + ASSERT(0x0002F802u != SYSREG->DEVICE_VERSION); + ASSERT(0x0003F802u != SYSREG->DEVICE_VERSION); + + write_ptr_value_into_array(*pp_key, params, 0u); + + params[4] = key_number; + + status = execute_service(PUF_FETCH_KEY_REQUEST_CMD, + params, + response, + STANDARD_SERV_RESP_LENGTH); + if(pp_key != NULL) + { + write_array_into_ptr_value(&(*pp_key), params, 0); + } + + return status; +} + +/*============================================================================== + * See mss_sys_services.h for details. + */ +uint8_t MSS_SYS_puf_export_keycodes +( + uint8_t * p_keycodes +) +{ + uint8_t response[PUF_EXPORT_ALL_KEYCODES_RESP_LENGTH]; + uint8_t params[11u]; + uint8_t status; + + /* + * The export all user key system service is not available on M2S050 rev A, + * rev B, rev C and rev D. + */ + ASSERT(0x0000F802u != SYSREG->DEVICE_VERSION); + ASSERT(0x0001F802u != SYSREG->DEVICE_VERSION); + ASSERT(0x0002F802u != SYSREG->DEVICE_VERSION); + ASSERT(0x0003F802u != SYSREG->DEVICE_VERSION); + + params[0] = PUF_EXPORT_ALL_KC_SUBCOMMAND; + + write_ptr_value_into_array(p_keycodes, params, 1u); + + status = execute_service(PUF_USER_KEY_CODE_REQUEST_CMD, + params, + response, + PUF_EXPORT_ALL_KEYCODES_RESP_LENGTH); + + return status; +} + +/*============================================================================== + * See mss_sys_services.h for details. + */ +uint8_t MSS_SYS_puf_import_keycodes +( + uint8_t * p_keycodes +) +{ + uint8_t response[PUF_IMPORT_ALL_KEYCODES_RESP_LENGTH]; + uint8_t params[11u]; + uint8_t status; + + /* + * The import all key code system service is not available on M2S050 rev A, + * rev B, rev C and rev D. + */ + ASSERT(0x0000F802u != SYSREG->DEVICE_VERSION); + ASSERT(0x0001F802u != SYSREG->DEVICE_VERSION); + ASSERT(0x0002F802u != SYSREG->DEVICE_VERSION); + ASSERT(0x0003F802u != SYSREG->DEVICE_VERSION); + + params[0] = PUF_IMPORT_ALL_KC_SUBCOMMAND; + + write_ptr_value_into_array(p_keycodes, params, 1u); + + status = execute_service(PUF_USER_KEY_CODE_REQUEST_CMD, + params, + response, + PUF_IMPORT_ALL_KEYCODES_RESP_LENGTH); + + return status; +} + +/*============================================================================== + * See mss_sys_services.h for details. + */ +uint8_t MSS_SYS_puf_fetch_ecc_public_key +( + uint8_t* p_puf_public_key +) +{ + uint8_t response[STANDARD_SERV_RESP_LENGTH]; + uint8_t params[4]; + uint8_t status; + + /* + * The fetch puf ecc public key system service is not available on M2S050 + * rev A, rev B, rev C and rev D. + */ + ASSERT(0x0000F802u != SYSREG->DEVICE_VERSION); + ASSERT(0x0001F802u != SYSREG->DEVICE_VERSION); + ASSERT(0x0002F802u != SYSREG->DEVICE_VERSION); + ASSERT(0x0003F802u != SYSREG->DEVICE_VERSION); + + write_ptr_value_into_array(p_puf_public_key, params, 0u); + + status = execute_service(PUF_ECC_PUBLIC_KEY_REQUEST_CMD, + params, + response, + STANDARD_SERV_RESP_LENGTH); + + return status; +} + +/*============================================================================== + * See mss_sys_services.h for details. + */ +uint8_t MSS_SYS_puf_get_random_seed +( + uint8_t* p_puf_seed +) +{ + uint8_t response[STANDARD_SERV_RESP_LENGTH]; + uint8_t params[4]; + uint8_t status; + + /* + * The get puf seed system service is not available on M2S050 rev A, rev B, + * rev C and rev D. + */ + ASSERT(0x0000F802u != SYSREG->DEVICE_VERSION); + ASSERT(0x0001F802u != SYSREG->DEVICE_VERSION); + ASSERT(0x0002F802u != SYSREG->DEVICE_VERSION); + ASSERT(0x0003F802u != SYSREG->DEVICE_VERSION); + + write_ptr_value_into_array(p_puf_seed, params, 0u); + + status = execute_service(PUF_SEED_REQUEST_CMD, + params, + response, + STANDARD_SERV_RESP_LENGTH); + + return status; +} + +/*============================================================================== + * See mss_sys_services.h for details. + */ +uint8_t MSS_SYS_ecc_point_multiplication +( + uint8_t* p_scalar_d, + uint8_t* p_point_p, + uint8_t* p_point_q +) +{ + uint8_t response[STANDARD_SERV_RESP_LENGTH]; + uint8_t params[12]; + uint8_t status; + + /* + * The ECC point multiplication system service is not available on M2S050 + * rev A, rev B, rev C and rev D. + */ + ASSERT(0x0000F802u != SYSREG->DEVICE_VERSION); + ASSERT(0x0001F802u != SYSREG->DEVICE_VERSION); + ASSERT(0x0002F802u != SYSREG->DEVICE_VERSION); + ASSERT(0x0003F802u != SYSREG->DEVICE_VERSION); + + write_ptr_value_into_array(p_scalar_d, params, 0u); + write_ptr_value_into_array(p_point_p, params, 4u); + write_ptr_value_into_array(p_point_q, params, 8u); + + status = execute_service(POINT_MULTIPLICATION_REQUEST_CMD, + params, + response, + STANDARD_SERV_RESP_LENGTH); + + return status; +} + +/*============================================================================== + * See mss_sys_services.h for details. + */ +uint8_t MSS_SYS_ecc_point_addition +( + uint8_t* p_point_p, + uint8_t* p_point_q, + uint8_t* p_point_r +) +{ + uint8_t response[STANDARD_SERV_RESP_LENGTH]; + uint8_t params[12]; + uint8_t status; + + /* + * The ECC point addition system service is not available on M2S050 + * rev A, rev B, rev C and rev D. + */ + ASSERT(0x0000F802u != SYSREG->DEVICE_VERSION); + ASSERT(0x0001F802u != SYSREG->DEVICE_VERSION); + ASSERT(0x0002F802u != SYSREG->DEVICE_VERSION); + ASSERT(0x0003F802u != SYSREG->DEVICE_VERSION); + + write_ptr_value_into_array(p_point_p, params, 0u); + write_ptr_value_into_array(p_point_q, params, 4u); + write_ptr_value_into_array(p_point_r, params, 8u); + + status = execute_service(POINT_ADDITION_REQUEST_CMD, + params, + response, + STANDARD_SERV_RESP_LENGTH); + + return status; +} + +/*============================================================================== + * See mss_sys_services.h for details. + */ +void MSS_SYS_ecc_get_base_point +( + uint8_t* p_point_g +) +{ + const uint8_t base_point_g[] = + { + 0xaa, 0x87, 0xca, 0x22, 0xbe, 0x8b, 0x05, 0x37, 0x8e, 0xb1, 0xc7, 0x1e, + 0xf3, 0x20, 0xad, 0x74, 0x6e, 0x1d, 0x3b, 0x62, 0x8b, 0xa7, 0x9b, 0x98, + 0x59, 0xf7, 0x41, 0xe0, 0x82, 0x54, 0x2a, 0x38, 0x55, 0x02, 0xf2, 0x5d, + 0xbf, 0x55, 0x29, 0x6c, 0x3a, 0x54, 0x5e, 0x38, 0x72, 0x76, 0x0a, 0xB7, + 0x36, 0x17, 0xde, 0x4a, 0x96, 0x26, 0x2c, 0x6f, 0x5d, 0x9e, 0x98, 0xbf, + 0x92, 0x92, 0xdc, 0x29, 0xf8, 0xf4, 0x1d, 0xbd, 0x28, 0x9a, 0x14, 0x7c, + 0xe9, 0xda, 0x31, 0x13, 0xb5, 0xf0, 0xb8, 0xc0, 0x0a, 0x60, 0xb1, 0xce, + 0x1d, 0x7e, 0x81, 0x9d, 0x7a, 0x43, 0x1d, 0x7c, 0x90, 0xea, 0x0e, 0x5F + }; + + memcpy(p_point_g, &base_point_g[0], sizeof(base_point_g)); +} + +/*============================================================================== + * See mss_sys_services.h for details. + */ +uint8_t MSS_SYS_start_clock_monitor +( + void +) +{ + uint8_t status; + uint8_t tamper_control_req[2]; + uint8_t response[TAMPER_CONTROL_SERV_RESP_LENGTH]; + uint16_t actual_response_length; + + /* + * The Start clock monitoring tamper Control service is available only on + * G4X device. + */ + ASSERT(0x0000F802u != SYSREG->DEVICE_VERSION); + ASSERT(0x0001F802u != SYSREG->DEVICE_VERSION); + ASSERT(0x0002F802u != SYSREG->DEVICE_VERSION); + ASSERT(0x0003F802u != SYSREG->DEVICE_VERSION); + + signal_request_start(); + + tamper_control_req[0] = TAMPER_CONTROL_REQUEST_CMD; + tamper_control_req[1] = 0x01u; + + MSS_COMBLK_send_cmd(tamper_control_req, /* p_cmd */ + sizeof(tamper_control_req), /* cmd_size */ + 0, /* p_data */ + 0u, /* data_size */ + response, /* p_response */ + TAMPER_CONTROL_SERV_RESP_LENGTH, /* response_size */ + request_completion_handler); /* completion_handler */ + + actual_response_length = wait_for_request_completion(); + + if((TAMPER_CONTROL_SERV_RESP_LENGTH == actual_response_length) && + (TAMPER_CONTROL_REQUEST_CMD == response[0])) + { + status = response[1]; + } + else + { + status = MSS_SYS_UNEXPECTED_ERROR; + } + + return status; +} + +/*============================================================================== + * See mss_sys_services.h for details. + */ +uint8_t MSS_SYS_stop_clock_monitor +( + void +) +{ + uint8_t status; + uint8_t tamper_control_req[2]; + uint8_t response[TAMPER_CONTROL_SERV_RESP_LENGTH]; + uint16_t actual_response_length; + + /* + * The Stop clock monitoring tamper Control service is available only on + * G4X device. + */ + ASSERT(0x0000F802u != SYSREG->DEVICE_VERSION); + ASSERT(0x0001F802u != SYSREG->DEVICE_VERSION); + ASSERT(0x0002F802u != SYSREG->DEVICE_VERSION); + ASSERT(0x0003F802u != SYSREG->DEVICE_VERSION); + + signal_request_start(); + + tamper_control_req[0] = TAMPER_CONTROL_REQUEST_CMD; + tamper_control_req[1] = 0x02u; + + MSS_COMBLK_send_cmd(tamper_control_req, /* p_cmd */ + sizeof(tamper_control_req), /* cmd_size */ + 0, /* p_data */ + 0u, /* data_size */ + response, /* p_response */ + TAMPER_CONTROL_SERV_RESP_LENGTH, /* response_size */ + request_completion_handler); /* completion_handler */ + + actual_response_length = wait_for_request_completion(); + + if((TAMPER_CONTROL_SERV_RESP_LENGTH == actual_response_length) && + (TAMPER_CONTROL_REQUEST_CMD == response[0])) + { + status = response[1]; + } + else + { + status = MSS_SYS_UNEXPECTED_ERROR; + } + + return status; +} + +/*============================================================================== + * See mss_sys_services.h for details. + */ +uint8_t MSS_SYS_enable_puf_power_down +( + void +) +{ + uint8_t status; + uint8_t tamper_control_req[2]; + uint8_t response[TAMPER_CONTROL_SERV_RESP_LENGTH]; + uint16_t actual_response_length; + + /* + * The Enable PUF power down service is available only on G4X device. + */ + ASSERT(0x0000F802u != SYSREG->DEVICE_VERSION); + ASSERT(0x0001F802u != SYSREG->DEVICE_VERSION); + ASSERT(0x0002F802u != SYSREG->DEVICE_VERSION); + ASSERT(0x0003F802u != SYSREG->DEVICE_VERSION); + + signal_request_start(); + + tamper_control_req[0] = TAMPER_CONTROL_REQUEST_CMD; + tamper_control_req[1] = 0x04u; + + MSS_COMBLK_send_cmd(tamper_control_req, /* p_cmd */ + sizeof(tamper_control_req), /* cmd_size */ + 0, /* p_data */ + 0u, /* data_size */ + response, /* p_response */ + TAMPER_CONTROL_SERV_RESP_LENGTH, /* response_size */ + request_completion_handler); /* completion_handler */ + + actual_response_length = wait_for_request_completion(); + + if((TAMPER_CONTROL_SERV_RESP_LENGTH == actual_response_length) && + (TAMPER_CONTROL_REQUEST_CMD == response[0])) + { + status = response[1]; + } + else + { + status = MSS_SYS_UNEXPECTED_ERROR; + } + + return status; +} + +/*============================================================================== + * See mss_sys_services.h for details. + */ +uint8_t MSS_SYS_disable_puf_power_down +( + void +) +{ + uint8_t status; + uint8_t tamper_control_req[2]; + uint8_t response[TAMPER_CONTROL_SERV_RESP_LENGTH]; + uint16_t actual_response_length; + + /* + * Disable PUF power down is available only on G4X device. + */ + ASSERT(0x0000F802u != SYSREG->DEVICE_VERSION); + ASSERT(0x0001F802u != SYSREG->DEVICE_VERSION); + ASSERT(0x0002F802u != SYSREG->DEVICE_VERSION); + ASSERT(0x0003F802u != SYSREG->DEVICE_VERSION); + + signal_request_start(); + + tamper_control_req[0] = TAMPER_CONTROL_REQUEST_CMD; + tamper_control_req[1] = 0x08u; + + MSS_COMBLK_send_cmd(tamper_control_req, /* p_cmd */ + sizeof(tamper_control_req), /* cmd_size */ + 0, /* p_data */ + 0u, /* data_size */ + response, /* p_response */ + TAMPER_CONTROL_SERV_RESP_LENGTH, /* response_size */ + request_completion_handler); /* completion_handler */ + + actual_response_length = wait_for_request_completion(); + + if((TAMPER_CONTROL_SERV_RESP_LENGTH == actual_response_length) && + (TAMPER_CONTROL_REQUEST_CMD == response[0])) + { + status = response[1]; + } + else + { + status = MSS_SYS_UNEXPECTED_ERROR; + } + + return status; +} + +/*============================================================================== + * See mss_sys_services.h for details. + */ +uint8_t MSS_SYS_clear_lock_parity +( + void +) +{ + uint8_t status; + uint8_t tamper_control_req[2]; + uint8_t response[TAMPER_CONTROL_SERV_RESP_LENGTH]; + uint16_t actual_response_length; + + /* + * The Clear Lock parity is available only on G4X device. + */ + ASSERT(0x0000F802u != SYSREG->DEVICE_VERSION); + ASSERT(0x0001F802u != SYSREG->DEVICE_VERSION); + ASSERT(0x0002F802u != SYSREG->DEVICE_VERSION); + ASSERT(0x0003F802u != SYSREG->DEVICE_VERSION); + + signal_request_start(); + + tamper_control_req[0] = TAMPER_CONTROL_REQUEST_CMD; + tamper_control_req[1] = 0x10u; + + MSS_COMBLK_send_cmd(tamper_control_req, /* p_cmd */ + sizeof(tamper_control_req), /* cmd_size */ + 0, /* p_data */ + 0u, /* data_size */ + response, /* p_response */ + TAMPER_CONTROL_SERV_RESP_LENGTH, /* response_size */ + request_completion_handler); /* completion_handler */ + + actual_response_length = wait_for_request_completion(); + + if((TAMPER_CONTROL_SERV_RESP_LENGTH == actual_response_length) && + (TAMPER_CONTROL_REQUEST_CMD == response[0])) + { + status = response[1]; + } + else + { + status = MSS_SYS_UNEXPECTED_ERROR; + } + + return status; +} + +/*============================================================================== + * See mss_sys_services.h for details. + */ +uint8_t MSS_SYS_clear_mesh_short +( + void +) +{ + uint8_t status; + uint8_t tamper_control_req[2]; + uint8_t response[TAMPER_CONTROL_SERV_RESP_LENGTH]; + uint16_t actual_response_length; + + /* + * The Clear mesh short service is available only on G4X device. + */ + ASSERT(0x0000F802u != SYSREG->DEVICE_VERSION); + ASSERT(0x0001F802u != SYSREG->DEVICE_VERSION); + ASSERT(0x0002F802u != SYSREG->DEVICE_VERSION); + ASSERT(0x0003F802u != SYSREG->DEVICE_VERSION); + + signal_request_start(); + + tamper_control_req[0] = TAMPER_CONTROL_REQUEST_CMD; + tamper_control_req[1] = 0x20u; + + MSS_COMBLK_send_cmd(tamper_control_req, /* p_cmd */ + sizeof(tamper_control_req), /* cmd_size */ + 0, /* p_data */ + 0u, /* data_size */ + response, /* p_response */ + TAMPER_CONTROL_SERV_RESP_LENGTH, /* response_size */ + request_completion_handler); /* completion_handler */ + + actual_response_length = wait_for_request_completion(); + + if((TAMPER_CONTROL_SERV_RESP_LENGTH == actual_response_length) && + (TAMPER_CONTROL_REQUEST_CMD == response[0])) + { + status = response[1]; + } + else + { + status = MSS_SYS_UNEXPECTED_ERROR; + } + + return status; +} + +/*============================================================================== + * + */ +static uint8_t execute_service +( + uint8_t cmd_opcode, + uint8_t * cmd_params_ptr, + uint8_t * response, + uint16_t response_length +) +{ + uint8_t status; + uint16_t actual_response_length; + + signal_request_start(); + + MSS_COMBLK_send_cmd_with_ptr(cmd_opcode, /* cmd_opcode */ + (uint32_t)cmd_params_ptr, /* cmd_params_ptr */ + response, /* p_response */ + response_length, /* response_size */ + request_completion_handler); /* completion_handler */ + + actual_response_length = wait_for_request_completion(); + + if((response_length == actual_response_length) && (cmd_opcode == response[0])) + { + status = response[1]; + } + else + { + status = MSS_SYS_UNEXPECTED_ERROR; + } + + return status; +} + +/*============================================================================== + * + */ +static void request_completion_handler +( + uint8_t * p_response, + uint16_t response_size +) +{ + g_request_in_progress = 0u; + g_last_response_length = response_size; +} + +/*============================================================================== + * + */ +static void signal_request_start(void) +{ + /* Wait for current request to complete. */ + while(g_request_in_progress) + { + ; + } + + g_request_in_progress = 1u; + g_last_response_length = 0u; +} + +/*============================================================================== + * + */ +static uint16_t wait_for_request_completion(void) +{ + while(g_request_in_progress) + { + ; + } + + return g_last_response_length; +} + +/*============================================================================== + * + */ +static void write_ptr_value_into_array +( + const uint8_t * pointer, + uint8_t target_array[], + uint32_t array_index +) +{ + target_array[array_index] = (uint8_t)((uint32_t)pointer); + target_array[array_index + 1] = (uint8_t)((uint32_t)pointer >> 8u); + target_array[array_index + 2] = (uint8_t)((uint32_t)pointer >> 16u); + target_array[array_index + 3] = (uint8_t)((uint32_t)pointer >> 24u); +} + +/*============================================================================== + Function to write array address to pointer location. + */ +static void write_array_into_ptr_value +( + uint8_t** pointer, + uint8_t target_array[], + uint32_t array_index +) +{ + uint32_t var; + + var = (uint32_t)target_array[array_index + 3]; + var = ((var << 8u) & 0xFFFFFF00) | target_array[array_index + 2]; + var = ((var << 8u) & 0xFFFFFF00) | target_array[array_index + 1]; + var = ((var << 8u) & 0xFFFFFF00) | target_array[array_index]; + + *pointer = (uint8_t*)var; +} + diff --git a/bsp/smartfusion2/libraries/mss_sys_services/mss_sys_services.h b/bsp/smartfusion2/libraries/mss_sys_services/mss_sys_services.h new file mode 100644 index 0000000000..b2586e0e5b --- /dev/null +++ b/bsp/smartfusion2/libraries/mss_sys_services/mss_sys_services.h @@ -0,0 +1,2500 @@ +/******************************************************************************* + * (c) Copyright 2012-2016 Microsemi SoC Products Group. All rights reserved. + * + * SmartFusion2 MSS System Services bare metal software driver public API. + * + * SVN $Revision: 8680 $ + * SVN $Date: 2016-11-25 14:18:13 +0530 (Fri, 25 Nov 2016) $ + */ + +/*=========================================================================*//** + @mainpage SmartFusion2 MSS System Services Bare Metal Driver. + + @section intro_sec Introduction + The SmartFusion2 microcontroller subsystem (MSS) includes a communication + block (COMM_BLK) allowing it to communicate with the SmartFusion2 System + Controller. The SmartFusion2 System Controller performs a variety of system + wide services. This software driver provides a set of functions to access + these System Services. The driver can be adapted for use as part of an + operating system, but the implementation of the adaptation layer between the + driver and the operating system's driver model is outside the scope of the + driver. + + @section hw_dependencies Hardware Flow Dependencies + The MSS System Services driver does not require any configuration. It relies + on the SmartFusion2 communication block (MSS_COMM_BLK) to communicate with the + System Controller. The MSS_COMM_BLK is always enabled. + The base address, register addresses and interrupt number assignment for the + MSS_COMM_BLK are defined as constants in the SmartFusion2 CMSIS HAL. You must + ensure that the latest SmartFusion2 CMSIS HAL is included in the project + settings of the software tool chain used to build your project and that it is + generated into your project. + + @section theory_op Theory of Operation + The System Services driver provides access to the SmartFusion2 System + Controller services. These system services are loosely grouped into the + following features: + - Reading system information + - Cryptography + - Non-deterministic random bit generator + - Flash*Freeze + - Zeroization + - Asynchronous Messages + - Programming Services + - Digest Check Service + Note: Refer to the function descriptions for further details about the + features of each individual service. + + Reading System Information + The System Services driver can be used to read information about the + SmartFusion2 device and the design programmed into it using the following + functions: + - MSS_SYS_get_serial_number() + - MSS_SYS_get_user_code() + - MSS_SYS_get_design_version() + - MSS_SYS_get_device_certificate() + - MSS_SYS_get_secondary_device_certificate() + + Cryptography Services + The System Services driver provides cryptographic services using the following + functions: + - MSS_SYS_128bit_aes() + - MSS_SYS_256bit_aes() + - MSS_SYS_sha256() + - MSS_SYS_hmac() + - MSS_SYS_challenge_response() + - MSS_SYS_key_tree() + + Non-Deterministic Random Bit Generator + The System Services driver provides random number generation services using + the following functions: + - MSS_SYS_nrbg_instantiate() + - MSS_SYS_nrbg_self_test() + - MSS_SYS_nrbg_generate() + - MSS_SYS_nrbg_reseed() + - MSS_SYS_nrbg_uninstantiate() + - MSS_SYS_nrbg_reset() + + Flash*Freeze + The System Services driver can be used to request the system to enter + Flash*Freeze mode using the following function: + - MSS_SYS_flash_freeze() + The System Controller sends an asynchronous message to the MSS COMM_BLK when + the device is either about to enter or has exited Flash*Freeze mode. The + MSS_SYS_init() function can register a callback function with the System + Services driver to handle these asynchronous messages. + + Zeroization + The System Service driver can be used to destroy sensitive information on the + SmartFusion2 device using the following function. + - MSS_SYS_zeroize_device() + The zeroization system service erases all user configuration data, user keys, + user security settings, NVM, SRAM, FPGA flip-flops, System Controller memory, + and crypto-engine registers. The zeroization system service is enabled and + configured in the Libero hardware flow. + Note: The zeroization system service can render the SmartFusion2 device + permanently and irrevocably disabled depending on the configuration + selected in the Libero hardware flow. + + Asynchronous Messages + The System Controller sends asynchronous messages to the MSS COMM_BLK when + certain events are detected during the execution of the following system + services: + �Flash*Freeze + �Power-on-reset (POR) digest check + �Tamper detect events + The MSS_SYS_init() function can register a callback function with the System + Services driver to handle these asynchronous messages allowing the user + application code to take remedial or defensive action. If the application + code does not provide an asynchronous event handler function then the driver + simply reads and discards these asynchronous messages. + Flash*Freeze Entry and Exit + The System Controller sends a Flash*Freeze entry or exit message to the MSS + COMM_BLK when the SmartFusion2 device is either about to enter or has exited + Flash*Freeze mode. The driver passes the entry/exit message opcode as a + parameter to the event handler callback function. + Power-on Reset (POR) Digest Error + The POR digest check service is enabled in the Libero hardware flow and if + enabled is automatically performed as part of the device�s power up sequence. + The System Controller sends a POR digest check error message to the MSS + COMM_BLK when the result of the POR digest check is a mismatch between the + original stored digest and the current digest. The driver passes the command + byte and the error flags byte from the error message as parameters to the + event handler callback function. + Tamper detect events + The System Controller sends tamper message to the MSS COMM_BLK when the + tamper event is detected. This tamper message is of one byte contain only + command opcode. The driver pass the tamper message opcode as a parameter + to the event handler callback function. + + Programming Service + The In-System Programming (ISP) system service can be used for field upgrades + of the hardware design programmed in the FPGA fabric. The application program + running on the Cortex-M3 controls the ISP operations, it must retrieve the + programming file from memory or from a communication port and feed it to + the System Controller through the ISP system service. The System Controller + performs the actual programming of the FPGA (fabric and eNVM) using the + programming data it receives from the Cortex-M3 as part of the ISP system + service. + Programming files are large and cannot always be entirely retrieved by the + application before starting the ISP operation. The ISP system service is + designed to work around this issue by handling programming one page at a + time. The application initiates the ISP operation through a call to + MSS_SYS_start_isp(), passing two function pointers as parameters. These two + function pointers point to a page read handler function and an ISP completion + handler function that must be implemented as part of the application. The + system services driver will call the application�s page read handler + function every time it is ready to program the FPGA with a new page of + programming data. The page read handler function is responsible for splitting + the programming file into suitably sized pages. The page size is not fixed + and can be chosen to suit the application. The system services driver will + call the ISP completion handler function once the last page has been + programmed. + The application must keep track of the pages of programming data is has + passed to the ISP system service. It must provide the location of the next + programming page by writing the address of the page into the location + pointed to by the pp_next_page pointer passed as parameter to the page read + handler function. The page read handler must return the size of the page or + zero if the last page has already been given to the ISP system service. + + The In-Application Programming (IAP) system service provides another field + upgrade method of the hardware design programmed in FPGA fabric. Using this + method, the user application first writes the FPGA fabric design into the SPI + Flash connected to MSS SPI-0 before invoking the IAP system service. The FPGA + fabric is then programmed under control of the SmartFusion2 system controller + without intervention of the Cortex-M3 processor. The application must + configure the SPI peripheral and provide exclusive access to the IAP service + before invoking the IAP system service. + When the IAP service is invoked, the system controller will send the SPI + command 0Bh i.e. single read operation command to the SPI flash to retrieve + the FPGA fabric design. The system controller will perform one of the + following operations based on the mode selected when invoking the service: + a) Authenticate the fabric design. + b) Program the fabric design into FPGA. + c) Verify that the programming was successful. + The system controller will take 2 to 3 minutes to complete each operation. + The application must provide the starting location address of the new FPGA + fabric design present in SPI Flash when invoking the IAP service. + The system controller will return a response indicating the status of the + operation on completing the execution of the IAP service except in the case + of successful programming. The system controller will reset the device and + start execution of the new FPGA fabric design after successfully programming + the device. The system controller will not return any response information + when a successful programming operation completes. + + Digest Check Service + The System Service driver can be used to recalculate and compare digests of + selected components using the following function. + - MSS_SYS_check_digest() + Note: This function is not used for the power-on-reset (POR) digest check + service. An asynchronous event handler registered with the + MSS_SYS_init() function is used to support the POR digest check + service. + + Elliptic Curve services + The System Service driver can be used to perform elliptic curve cryptography + (ECC) mathematical operations over the field defined by the NIST P-384 + curve. point addition and point multiplication using the following functions + are provided: + - MSS_SYS_ecc_point_multiplication() + - MSS_SYS_ecc_point_addition() + - MSS_SYS_ecc_get_base_point() + One example use of these functions is the elliptic curve Diffie-Hellman + (ECDH) key establishment protocol. In this protocol, a public key is computed + by performing a point multiplication of a 384-bit private key with the base + point for the NIST P-384 curve. Both parties involved in the key + establishment compute their public keys and send them to each other. A shared + secret is established by point multiplication of each party�s private key + with the remote party�s public key. The elliptic curve mathematical + properties ensure that the private key point multiplication with the remote + party�s public key results in the same point on the curve for both parties. + The coordinates of this point on the curve is used as the shared secret for + further cryptographic operations. + Note: There is no checking done to see if the given input point or points + are valid points on the elliptic curve. Supplying illegal X-Y coordinates + for a point will result in a garbage output. However, if a valid point or + points are given, then the resulting output point is guaranteed to be valid. + + PUF Services + The SRAM-PUF system services provide a Physically Unclonable Function (PUF) + that can be used for key generation and storage as well as device + authentication. + The large SmartFusion2 devices starting from the M2S060 include an SRAM-PUF + hardware block as part of the System Controller. This hardware block makes + use of a 16Kbit SRAM block to determine an intrinsic secret unique to each + device. This intrinsic secret is in turn used to regenerate keys enrolled + with the SRAM-PUF hardware block. + The SRAM-PUF is also used in design security. Although the system services + are not used for design security, it is possible to retrieve the design + security ECC public key for device authentication purpose. + The SRAM-PUF start-up value can also be used to generate a random number + generator seed. + Note: PUF service should be executed from DDR/SRAM/eNVM-0 except for the + M2S060 device. On the M2S060 device, PUF service should be executed + from DDR/SRAM. + + Activation Code + An activation code is required by the SRAM-PUF to regenerate the intrinsic + secret from the SRAM-PUF start-up value. The start-up value of the PUF�s SRAM + block is slightly different from one power-up to the next. Some processing is + performed on the PUF�s SRAM start-up value to eliminate randomness and + retrieve the exact same intrinsic secret on each power-up cycle. This + processing is performed using the activation code, which can be thought of as + parity bits that are used to reconstruct the same PUF intrinsic secret each + time, in spite of the fact that some SRAM bits are flipped compared to the + original snapshot used when the activation code was first enrolled. + The devices are shipped with one activation code that was enrolled during + the manufacturing process. The PUF secret computed from this enrollment is + used to protect a 376-bit ECC private key that may be used for design + security purposes as described elsewhere. The user may optionally enroll a + second activation code in special �S� -suffix (i.e., security enabled) + devices. The activation code is usually generated only once, typically when + the system containing the SmartFusion2 device is being commissioned, using a + JTAG or SPI programming command. Alternatively, the activation code is + created using the following system service function: + + - MSS_SYS_puf_create_activation_code() + This might be used if the first user activation code were intentionally + deleted and a new one was desired. The activation code is stored the System + Controller�s private eNVM after being created. Its value is never exported in + clear text from the System Controller. Because of the inherent noise in each + SRAM start-up, there is a negligible probability two activation codes or the + associated PUF intrinsic secret are ever the same, even if the same device is + repeatedly re-enrolled. + The activation code can later be destroyed using the following function: + - MSS_SYS_puf_delete_activation_code() + This function would typically only be used when the system containing + SmartFusion2 is being decommissioned or repurposed. + + Enrolling Keys + The SRAM-PUF can be used to store cryptographic keys. The keys are stored in + such a way that the key�s actual value never appears in the system unless it + is retrieved by the user. A so-called "Key Code" is stored in the System + Controller�s private eNVM instead of the key�s value. The key code is + generated when a key is enrolled. The key code value is created from the + enrolled key�s value and the intrinsic secret value. The key�s value can then + later be regenerated from the key code value and intrinsic secret value upon + user request. + NOTE:Note: Key #0 and key #1 are used for design security and are not + accessible to the user. Key Code #2 may be used to store a user + data security key, but has an important optional use in JTAG- or + SPI-based key validation, as will be described below. + + The enrolled keys can be intrinsic keys or extrinsic keys. The value of an + intrinsic key is a random number generated from the SRAM-PUF start-up value. + Intrinsic keys are useful where a security protocol executing on SmartFusion2 + needs to generate a key�s value and store it for later use. For example, the + user could request a 384-bit long intrinsic key to be enrolled and use it as + private key in an elliptic curve Diffie-Hellman key exchange. + The value of an extrinsic key is specified by the user. For example, the user + could request a symmetric key obtained from a key exchange protocol to be + enrolled for later use. + The following functions are used for key enrollment: + - MSS_SYS_puf_get_number_of_keys() + - MSS_SYS_puf_enroll_key() + - MSS_SYS_puf_fetch_key() + - MSS_SYS_puf_delete_key() + + Keys are identified by a number and must be enrolled sequentially. Key codes + #0 and #1 are reserved as a 256-bit symmetric extrinsic key and a 384-bit + private (asymmetric) intrinsic key, both used for design security only, and + are enrolled by JTAG (or SPI) programming commands. These commands also + enroll the user activation code and key code #2, a 256-bit value that has a + special use in key validation, and which is enrolled at the same time as key + code #1, as will be described below. + The first step in enrolling a new key is to determine how many keys are + already enrolled. This is achieved by a call to function + MSS_SYS_puf_get_number_of_keys() which returns the number of enrolled keys. + Keys are numbered from 0 up to 57 (the maximum number of keys assuming all + user keys are less than or equal to 256 bits in length). For example, + assuming only the first three key codes mentioned above have been enrolled + using the JTAG programming commands, the value returned would be �3�. The + number of keys returned by MSS_SYS_puf_get_number_of_keys() can then be used + as the newly enrolled key identification number since key numbering is zero + based. Thus, the first data security key enrolled by the user would generate + key code #3. + + A key is enrolled through a call to function MSS_SYS_puf_enroll_key(). This + function takes the following parameters: + � The key identification number that will be used to later retrieve the + key�s value. This is the value returned by a call to + MSS_SYS_puf_get_number_of_keys(). + � The key size. + � A pointer to the buffer containing the value of the key to enroll. The + value of this pointer must be NULL if enrolling an intrinsic key where + the SRAM-PUF will generate the actual key value. + � A pointer to the buffer where the enrolled key will be regenerated when + later fetched by the user. + + The value of the enrolled keys can be regenerated through a call to function + MSS_SYS_puf_fetch_key(). The identification number of the key to fetch is + passed as parameter to this function. The requested key�s value will be + regenerated and copied to the buffer specified during key enrollment. The + key�s value is then available for use until it is no further required and + wiped, by the user�s application, from the memory buffer it was fetched into. + + Note: It is not possible to fetch a key if the key codes have been exported + and not re-imported. + + A key can be removed from the system through a call to function + MSS_SYS_puf_delete_key(). This function only requires the key identification + number to specify which key should be removed from the SRAM-PUF. + + Note: If a new key is enrolled in a key-slot where a key was previously + enrolled and deleted and which is not the highest key number enrolled, + it must be the same size as the key it replaced or an error will be + reported. + + Exporting and Importing Key Codes + The activation code and key codes used to regenerate the enrolled keys can be + exported out of the SRAM-PUF. The exported activation code and key codes are + encrypted using a one-time pad. The one-time pad is stored in the System + Controller�s private eNVM and is never exported. This means that the exported + activation and key codes can only be decrypted by the unique device that + exported them. + The activation and key code values stored in eNVM are replaced with hash + values of themselves as part of the export procedure. This means that + enrolled keys cannot be regenerated anymore after the activation and key + codes have been exported. The enrolled keys will only be regenerated + successfully if the exported activation and key codes for that unique + SmartFusion2 device are imported back. + + The activation and all the key codes are exported in one single operation + using the following function: + - MSS_SYS_puf_export_keycodes() + The MSS_SYS_puf_export_keycodes() function can only be called once since the + activation and key codes are not present anymore in the device after this + function completes. The activation and key codes must be imported back + before they can be exported again. + The activation and all the key codes are imported back in one single + operation using the following function: + - MSS_SYS_puf_import_keycodes() + It is only possible to import activation and key codes exported from the + same unique device. The imported activation and key codes are decrypted + using the one-time pad stored in eNVM used during the export procedure. + The decrypted activation and key codes are then checked again the hash + values stored in place of the activation and key codes. The activation + and key codes will only be successfully imported back if the hash values + for the imported activation and key codes match the hash values stored in + eNVM during the export procedure. Imported activation and key codes are + never again restored to non-volatile memory; rather, they are imported to + volatile scratch-pad memory, used to regenerate a key, and then deleted. + Therefore, they must be re-imported each time a key is needed. + + Retrieving the Design Security ECC Public Key + When the 384 bit user design security private ECC key is intrinsically + generated and key code #1 is stored using the JTAG or SPI programming + commands, the associated 768 bit public key is also generated and stored + in the system controller�s private eNVM. At the same time, the256 bit SHA-256 + hash of the ECC public key is enrolled to key code #2. + The 768 bit design security ECC public key can be retrieved using the following + system service function: + - MSS_SYS_puf_fetch_ecc_public_key() + Note that the public key is also exported via JTAG (or SPI) programming + commands when it is used in ECDH design security operations such as + bitstream encryption or device authentication. + + In order to mitigate man-in-the-middle attacks on the public key when it is + exported and used, it is recommended that the ECC public key is validated + using an already trusted key. This could be a user design security key, for + example. Perhaps the most convenient keys to use are one of the Microsemi + certified ECC key pairs, which are trusted because of the verifiable + Microsemi signatures on the X.509 public key certificates. This is why when + the 384 bit user ECC private key was generated and stored using key code #1, + the 256 bit hash of the associated 768 bit public key was stored using key + code #2. The JTAG (or SPI) key verification protocol has a special option + which includes the value stored in key code #2 in the computation. Thus, + besides also validating the device really �knows� the already trusted key, + with this option selected, the 256-bit value stored using key code #2 is also + validated. If this is the hash of the user ECC public key, then it is proved + that the public key is the authentic public key as stored in the device, and + not one supplied by an adversary in a man-in-the-middle attack on this key. + After the user ECC public key has been thus validated, key code #2 can be + deleted and replaced with another 256-bit value the user wishes to validate, + such as the hash of user data security key. It is recommended that key code + #2 only be used to store hashes of critical security parameters such as + secret or private keys, and not the actual secrets, themselves. + Note: The user's application need to reserve a defined block of SRAM when + using PUF system services, to prevent the compiler from using the SRAM + memory range from address 0x2000800 to 0x2000802F inclusive. This is + the default location used by the system controller to automatically + enroll KC#2, when KC#1 is enrolled. + + Random Number Generator Seed + The PUF�s SRAM start-up value randomness can be harvested to generate a + 256-bit full entropy true random seed. A random seed can be obtained using + function: + - MSS_SYS_puf_get_random_seed() + Note: Random seeds can only be generated after the SRAM-PUF has been powered + -down for 250 msec. Thus, if the PUF has been used more recently than + that, there may be a delay before the seed is generated. + + Tamper control service + The tamper control system services provide the following services: + - Enable/disable clock monitoring + - Control power to PUF + - Clear mesh short tamper + - Clear lock parity tamper + + The tamper control services are accessed using the following functions: + - MSS_SYS_start_clock_monitor() + - MSS_SYS_stop_clock_monitor() + - MSS_SYS_enable_puf_power_down() + - MSS_SYS_disable_puf_power_down() + - MSS_SYS_clear_lock_parity() + - MSS_SYS_clear_mesh_short() + + *//*=========================================================================*/ + +#ifndef __MSS_SYS_SERVICES_H_ +#define __MSS_SYS_SERVICES_H_ 1 + +#include "../../CMSIS/m2sxxx.h" +#include "mss_comblk_page_handler.h" + +#ifdef __cplusplus +extern "C" { +#endif + +/*============================================================================== + * Status codes: + */ +/*-------------------------------------------------------------------------*//** + These constants are used by multiple services to communicate the outcome of a + system services request. These status codes are used across all types of + services. + + - MSS_SYS_SUCCESS: + Indicates that the system services completed successfully. + + - MSS_SYS_UNEXPECTED_ERROR: + Indicates that the system failed in an unexpected way. + + - MSS_SYS_MEM_ACCESS_ERROR: + Indicates that the System Controller could not access the memory used to + pass parameters to the System Controller or to return a service result to + the Cortex-M3. + + - MSS_SYS_SERVICE_DISABLED_BY_FACTORY: + Indicates that the requested system service is not available on the + SmartFusion2 device. + + - MSS_SYS_SERVICE_DISABLED_BY_USER: + Indicates that the requested system service has been disabled as part of + the hardware design. + + - MSS_SYS_SERVICE_NOT_LICENSED + Indicates that the license is not available in SmartFusion2 device for + this service. + + - MSS_SYS_CLK_DIVISOR_ERROR + Indicates that on 060 device the divisor values for fclk, pclk0, pclk1, + clk_fic64 are not equal to each other or the divisor values is set to + divide by 32. + */ +#define MSS_SYS_SUCCESS 0u +#define MSS_SYS_UNEXPECTED_ERROR 200u +#define MSS_SYS_CLK_DIVISOR_ERROR 201u + +#define MSS_SYS_MEM_ACCESS_ERROR 127u +#define MSS_SYS_SERVICE_NOT_LICENSED 253u +#define MSS_SYS_SERVICE_DISABLED_BY_FACTORY 254u +#define MSS_SYS_SERVICE_DISABLED_BY_USER 255u + +/*-------------------------------------------------------------------------*//** + These constants are used by PUF services to communicate the outcome of a + system services request. These status codes are only used by PUF services. + + - MSS_SYS_ENVM_ERROR: + Indicates that a eNVM error occurred for both create and delete user + activation code sub command. + + - MSS_SYS_PUF_ERROR_WHEN_CREATING: + Indicates that PUF error occur while creating new user activation code. + + - MSS_SYS_INVALID_SUBCMD: + Indicates that the sub command is invalid. + + - MSS_SYS_INVALID_REQUEST_OR_KC: + Indicates that request or Key code is invalid, when exporting or + importing. + + - MSS_SYS_INVALID_KEYNUM_OR_ARGUMENT + Indicates that the supplied key number or argument is invalid. + + - MSS_SYS_NO_VALID_PUBLIC_KEY + Indicates that no valid public key present in eNVM. + + - MSS_SYS_INVALID_MEMORY_ADDRESS: + Indicates that memory address is invalid. + + - MSS_SYS_ENVM_PROGRAM_ERROR + Indicates that the eNVM program error occur when writing to the private eNVM + for both create and delete user activation code sub command. + + - MSS_SYS_INVALID_HASH: + Indicates that 32 byte hash is invalid. + + - MSS_SYS_INVALID_USER_AC1: + Indicates that invalid user activation code has been imported. + + - MSS_SYS_ENVM_VERIFY_ERROR: + Indicates that the eNVM verify error occur when writing to the private eNVM + for both create and delete user activation code sub command. + + - MSS_SYS_INCORRECT_KEYSIZE_FOR_RENEWING_A_KC: + Indicates that the supplied key size is incorrect while renewing the key + code. + + - MSS_SYS_PRIVATE_ENVM_USER_DIGEST_MISMATCH: + Indicates that digest mismatch occurs for private eNVM. + + - MSS_SYS_USER_KEY_CODE_INVALID_SUBCMD: + Indicate that the sub command is invalid. + + - MSS_SYS_DRBG_ERROR: + Indicates that DRBG error occurred while populating one time pad reminder + by random bits. +*/ +#define MSS_SYS_ENVM_ERROR 1u +#define MSS_SYS_PUF_ERROR_WHEN_CREATING 2u +#define MSS_SYS_INVALID_SUBCMD 3u +#define MSS_SYS_INVALID_REQUEST_OR_KC 3u +#define MSS_SYS_INVALID_KEYNUM_OR_ARGUMENT 3u +#define MSS_SYS_NO_VALID_PUBLIC_KEY 3u +#define MSS_SYS_INVALID_MEMORY_ADDRESS 4u +#define MSS_SYS_ENVM_PROGRAM_ERROR 4u +#define MSS_SYS_INVALID_HASH 5u +#define MSS_SYS_INVALID_USER_AC1 6u +#define MSS_SYS_ENVM_VERIFY_ERROR 7u +#define MSS_SYS_INCORRECT_KEYSIZE_FOR_RENEWING_A_KC 8u +#define MSS_SYS_PRIVATE_ENVM_USER_DIGEST_MISMATCH 10u +#define MSS_SYS_USER_KEY_CODE_INVALID_SUBCMD 11u +#define MSS_SYS_DRBG_ERROR 12u + +/*-------------------------------------------------------------------------*//** + * Programming services specific status codes: + */ +#define MSS_SYS_CHAINING_MISMATCH 1u +#define MSS_SYS_UNEXPECTED_DATA_RECEIVED 2u +#define MSS_SYS_INVALID_ENCRYPTION_KEY 3u +#define MSS_SYS_INVALID_COMPONENT_HEADER 4u +#define MSS_SYS_BACK_LEVEL_NOT_SATISFIED 5u +#define MSS_SYS_DSN_BINDING_MISMATCH 7u +#define MSS_SYS_ILLEGAL_COMPONENT_SEQUENCE 8u +#define MSS_SYS_INSUFFICIENT_DEV_CAPABILITIES 9u +#define MSS_SYS_INCORRECT_DEVICE_ID 10u +#define MSS_SYS_UNSUPPORTED_BITSTREAM_PROT_VER 11u +#define MSS_SYS_VERIFY_NOT_PERMITTED_ON_BITSTR 12u +#define MSS_SYS_INVALID_DEVICE_CERTIFICATE 13u +#define MSS_SYS_ABORT 127u +#define MSS_SYS_NVM_VERIFY_FAILED 129u +#define MSS_SYS_DEVICE_SECURITY_PROTECTED 130u +#define MSS_SYS_PROGRAMMING_MODE_NOT_ENABLED 131u +#define MSS_SYS_ENVM_PROGRAMMING_OPERATION_FAIL 132u +#define MSS_SYS_ENVM_VERIFY_OPERATION_FAIL 133u +#define MSS_SYS_ACCESS_ERROR 134u +#define MSS_SYS_PUF_ACCESS_ERROR 135u +#define MSS_SYS_BAD_COMPONENT 136u + +/*-------------------------------------------------------------------------*//** + These constants are used to specify the event_opcode parameter for the + event_handler() function registered with the MSS_SYS_init() function. They are + used to specify which asynchronous event is notified to the Cortex-M3 software + by the System Controller. Asynchronous events are sent by the System + Controller to the Cortex-M3 when some system events of interest occur. + + - FLASH_FREEZE_SHUTDOWN_OPCODE: + Indicates that the system is being shutdown as a result of entering the + Flash*Freeze mode. + + - FLASH_FREEZE_EXIT_OPCODE: + Indicates that the system is exiting Flash*Freeze mode. + + - POR_DIGEST_ERROR_OPCODE + Indicates that the MSS has received the POR Digest Check message. + + - TAMPER_ATTEMPT_BOUNDARY_SCAN_OPCODE + Indicates that the MSS has received the tamper boundary scan attempt + detected. + + - TAMPER_ATTEMPT_BUFFER_ACCESS_OPCODE + Indicates that the MSS has received the tamper buffer access attempt + detected. + + - TAMPER_ATTEMPT_DEBUG_OPCODE + Indicates that the MSS has received the tamper debug attempt detected. + + - TAMPER_ATTEMPT_CHECK_DIGESTS_OPCODE + Indicates that the MSS has received the tamper check digest attempt + detected. + + - TAMPER_ATTEMPT_ECC_SETUP_INSTRUCTION_OPCODE + Indicates that the MSS has received the tamper ECC setup instruction + attempt detected. + + - TAMPER_ATTEMPT_FACTORY_PRIVATE_OPCODE + Indicates that the MSS has received the tamper factory private attempt + detected. + + - TAMPER_ATTEMPT_KEY_VALIDATION_OPCODE + Indicates that the MSS has received the tamper key validation attempt + detected. + + - TAMPER_ATTEMPT_MISC_OPCODE + Indicates that the MSS has received the tamper misc attempt detected. + + - TAMPER_ATTEMPT_PASSCODE_MATCH_OPCODE + Indicates that the MSS has received the tamper passcode match attempt + detected. + + - TAMPER_ATTEMPT_PASSCODE_SETUP_INSTRUCTION_OPCODE + Indicates that the MSS has received the tamper passcode setup instruction + attempt detected. + + - TAMPER_ATTEMPT_PROGRAMMING_OPCODE + Indicates that the MSS has received the tamper programming attempt detected. + + - TAMPER_ATTEMPT_PUBLIC_INFORMATION_OPCODE + Indicates that the MSS has received the tamper public information attempt + detected. + + - TAMPER_ATTEMPT_PUF_KEY_MANAGEMENT_OPCODE + Indicates that the MSS has received the tamper PUF key management attempt + detected. + + - TAMPER_ATTEMPT_UNUSED_OPCODE + Indicates that the MSS has received the tamper unused attempt detected. + + - TAMPER_ATTEMPT_USER_JTAG_OPCODE + Indicates that the MSS has received the tamper user JTAG attempt detected. + + - TAMPER_ATTEMPT_ZEROIZATION_RECOVERY_OPCODE + Indicates that the MSS has received the tamper zeroization recovery + attempt detected. + + - TAMPER_FAILURE_BOUNDARY_SCAN_OPCODE + Indicates that the MSS has received the tamper boundary scan failure + detected. + + - TAMPER_FAILURE_BUFFER_ACCESS_OPCODE + Indicates that the MSS has received the tamper buffer access + failure detected. + + - TAMPER_FAILURE_DEBUG_OPCODE + Indicates that the MSS has received the tamper debug failure detected. + + - TAMPER_FAILURE_CHECK_DIGESTS_OPCODE + Indicates that the MSS has received the tamper check digest failure + detected. + + - TAMPER_FAILURE_ECC_SETUP_INSTRUCTION_OPCODE + Indicates that the MSS has received the tamper ECC setup instruction + failure detected. + + - TAMPER_FAILURE_FACTORY_PRIVATE_OPCODE + Indicates that the MSS has received the tamper factory private failure + detected. + + - TAMPER_FAILURE_KEY_VALIDATION_OPCODE + Indicates that the MSS has received the tamper key validation failure + detected. + + - TAMPER_FAILURE_MISC_OPCODE + Indicates that the MSS has received the tamper misc failure detected. + + - TAMPER_FAILURE_PASSCODE_MATCH_OPCODE + Indicates that the MSS has received the tamper passcode match failure + detected. + + - TAMPER_FAILURE_PASSCODE_SETUP_INSTRUCTION_OPCODE + Indicates that the MSS has received the tamper passcode setup instruction + failure detected. + + - TAMPER_FAILURE_PROGRAMMING_OPCODE + Indicates that the MSS has received the tamper programming failure detected. + + - TAMPER_FAILURE_PUBLIC_INFORMATION_OPCODE + Indicates that the MSS has received the tamper public information failure + detected. + + - TAMPER_FAILURE_PUF_KEY_MANAGEMENT_OPCODE + Indicates that the MSS has received the tamper PUF key management failure + detected. + + - TAMPER_FAILURE_UNUSED_OPCODE + Indicates that the MSS has received the tamper unused failure detected. + + - TAMPER_FAILURE_USER_JTAG_OPCODE + Indicates that the MSS has received the tamper user jtag failure detected. + + - TAMPER_FAILURE_ZEROIZATION_RECOVERY_OPCODE + Indicates that the MSS has received the tamper zeroization recovery + failure detected. + + - TAMPER_CLOCK_ERROR_DETECT_OPCODE0 + Indicates that the MSS has received the tamper clock monitor error detected. + + - TAMPER_HARDWARE_MONITOR_JTAGACTIVE_ERROR_OPCODE + Indicates that the MSS has received the tamper jtag active hardware + monitor error detected. + + - TAMPER_HARDWARE_MONITOR_LOCKPARITY_ERROR_OPCODE + Indicates that the MSS has received the tamper lock parity hardware + monitor error detected. + + - TAMPER_HARDWARE_MONITOR_MESHSHORT_ERROR_OPCODE + Indicates that the MSS has received the tamper mesh short hardware monitor + error detected. +*/ +#define FLASH_FREEZE_SHUTDOWN_OPCODE 0xE0u +#define FLASH_FREEZE_EXIT_OPCODE 0xE1u +#define POR_DIGEST_ERROR_OPCODE 0xF1u +#define TAMPER_ATTEMPT_BOUNDARY_SCAN_OPCODE 0x80u +#define TAMPER_ATTEMPT_BUFFER_ACCESS_OPCODE 0x81u +#define TAMPER_ATTEMPT_DEBUG_OPCODE 0x82u +#define TAMPER_ATTEMPT_CHECK_DIGESTS_OPCODE 0x83u +#define TAMPER_ATTEMPT_ECC_SETUP_INSTRUCTION_OPCODE 0x84u +#define TAMPER_ATTEMPT_FACTORY_PRIVATE_OPCODE 0x85u +#define TAMPER_ATTEMPT_KEY_VALIDATION_OPCODE 0x86u +#define TAMPER_ATTEMPT_MISC_OPCODE 0x87u +#define TAMPER_ATTEMPT_PASSCODE_MATCH_OPCODE 0x88u +#define TAMPER_ATTEMPT_PASSCODE_SETUP_INSTRUCTION_OPCODE 0x89u +#define TAMPER_ATTEMPT_PROGRAMMING_OPCODE 0x8Au +#define TAMPER_ATTEMPT_PUBLIC_INFORMATION_OPCODE 0x8Bu +#define TAMPER_ATTEMPT_PUF_KEY_MANAGEMENT_OPCODE 0x8Cu +#define TAMPER_ATTEMPT_UNUSED_OPCODE 0x8Du +#define TAMPER_ATTEMPT_USER_JTAG_OPCODE 0x8Eu +#define TAMPER_ATTEMPT_ZEROIZATION_RECOVERY_OPCODE 0x8Fu +#define TAMPER_FAILURE_BOUNDARY_SCAN_OPCODE 0x90u +#define TAMPER_FAILURE_BUFFER_ACCESS_OPCODE 0x91u +#define TAMPER_FAILURE_DEBUG_OPCODE 0x92u +#define TAMPER_FAILURE_CHECK_DIGESTS_OPCODE 0x93u +#define TAMPER_FAILURE_ECC_SETUP_INSTRUCTION_OPCODE 0x94u +#define TAMPER_FAILURE_FACTORY_PRIVATE_OPCODE 0x95u +#define TAMPER_FAILURE_KEY_VALIDATION_OPCODE 0x96u +#define TAMPER_FAILURE_MISC_OPCODE 0x97u +#define TAMPER_FAILURE_PASSCODE_MATCH_OPCODE 0x98u +#define TAMPER_FAILURE_PASSCODE_SETUP_INSTRUCTION_OPCODE 0x99u +#define TAMPER_FAILURE_PROGRAMMING_OPCODE 0x9Au +#define TAMPER_FAILURE_PUBLIC_INFORMATION_OPCODE 0x9Bu +#define TAMPER_FAILURE_PUF_KEY_MANAGEMENT_OPCODE 0x9Cu +#define TAMPER_FAILURE_UNUSED_OPCODE 0x9Du +#define TAMPER_FAILURE_USER_JTAG_OPCODE 0x9Eu +#define TAMPER_FAILURE_ZEROIZATION_RECOVERY_OPCODE 0x9Fu +#define TAMPER_CLOCK_ERROR_DETECT_OPCODE 0xA0u +#define TAMPER_HARDWARE_MONITOR_JTAGACTIVE_ERROR_OPCODE 0xB1u +#define TAMPER_HARDWARE_MONITOR_LOCKPARITY_ERROR_OPCODE 0xB2u +#define TAMPER_HARDWARE_MONITOR_MESHSHORT_ERROR_OPCODE 0xB4u + +/*-------------------------------------------------------------------------*//** + These constants are used to specify the options parameter for the + MSS_SYS_flash_freeze() function. + + - MSS_SYS_FPGA_POWER_DOWN: + Indicates that the MSS_SYS_flash_freeze() function should request the FPGA + fabric to enter Flash*Freeze mode. + + - MSS_SYS_MPLL_POWER_DOWN: + Indicates that the MSS_SYS_flash_freeze() function should request the MSS + PLL to enter Flash*Freeze mode. + */ +#define MSS_SYS_FPGA_POWER_DOWN 0x00u +#define MSS_SYS_MPLL_POWER_DOWN 0x04u + +/*-------------------------------------------------------------------------*//** + These constants are used to specify the mode parameter for the + MSS_SYS_128aes() and MSS_SYS_256bit_aes() functions. + + - MSS_SYS_ECB_ENCRYPT: + Indicates that the cryptography function should perform encryption using + the Electronic Codebook (ECB) mode. + + - MSS_SYS_ECB_DECRYPT: + Indicates that the cryptography function should perform decryption using + the Electronic Codebook (ECB) mode. + + - MSS_SYS_CBC_ENCRYPT: + Indicates that the cryptography function should perform encryption using + the Cipher-Block Chaining (CBC) mode. + + - MSS_SYS_CBC_DECRYPT: + Indicates that the cryptography function should perform decryption using + the Cipher-Block Chaining (CBC) mode. + + - MSS_SYS_OFB_ENCRYPT: + Indicates that the cryptography function should perform encryption using + the Output Feedback (OFB) mode. + + - MSS_SYS_OFB_DECRYPT: + Indicates that the cryptography function should perform decryption using + the Output Feedback (OFB) mode. + + - MSS_SYS_CTR_ENCRYPT: + Indicates that the cryptography function should perform encryption using + the Counter (CTR) mode. + + - MSS_SYS_CTR_DECRYPT: + Indicates that the cryptography function should perform decryption using + the Counter (CTR) mode. + */ +#define MSS_SYS_ECB_ENCRYPT 0x00u +#define MSS_SYS_ECB_DECRYPT 0x80u +#define MSS_SYS_CBC_ENCRYPT 0x01u +#define MSS_SYS_CBC_DECRYPT 0x81u +#define MSS_SYS_OFB_ENCRYPT 0x02u +#define MSS_SYS_OFB_DECRYPT 0x82u +#define MSS_SYS_CTR_ENCRYPT 0x03u +#define MSS_SYS_CTR_DECRYPT 0x83u + +/*------------------------------------------------------------------------------ + These constants are used by non deterministic random bit generator (NDRBG) + services to communicate the outcome of a system services request. These status + codes are only used by NDRBG services. + + - MSS_SYS_NRBG_CATASTROPHIC_ERROR: + Indicates that a catastrophic error occurred. + + - MSS_SYS_NRBG_MAX_INST_EXCEEDED: + Indicates that the maximum number of NDRBG instances has been exceeded. + You need to release already instantiated NDRBG instances using the + MSS_SYS_ndrbg_uninstantiate() function. + + - MSS_SYS_NRBG_INVALID_HANDLE: + Indicates that the handle parameter has an invalid value. + + - MSS_SYS_NRBG_GEN_REQ_TOO_BIG: + Indicates that the requested random number is too long. The requested + length is larger than the maximum number of digits that can be generated. + + - MSS_SYS_NRBG_MAX_LENGTH_EXCEEDED: + Indicates that the supplied additional data length is exceeded. + */ +#define MSS_SYS_NRBG_CATASTROPHIC_ERROR 1u +#define MSS_SYS_NRBG_MAX_INST_EXCEEDED 2u +#define MSS_SYS_NRBG_INVALID_HANDLE 3u +#define MSS_SYS_NRBG_GEN_REQ_TOO_BIG 4u +#define MSS_SYS_NRBG_MAX_LENGTH_EXCEEDED 5u + +/*-------------------------------------------------------------------------*//** + The sys_serv_isp_complete_handler_t typedef specifies the function prototype + of the in-system programming (ISP) completion handler that is passed as a + parameter to the MSS_SYS_start_isp() function. The ISP completion handler + function must be implemented by the application program and it is called by + the System Services driver when an ISP operation initiated by a call to + MSS_SYS_start_isp() completes. The ISP completion handler function receives + a status parameter indicating the outcome of the ISP operation. Refer to the + description of the MSS_SYS_start_isp() function for more details. + */ +typedef void (*sys_serv_isp_complete_handler_t)(uint32_t status); + +/*-------------------------------------------------------------------------*//** + The sys_serv_async_event_handler_t type specifies the function prototype of + an asynchronous event handler that can be implemented by the application to + handle asynchronous messages from the System Controller. The System + Controller sends asynchronous messages to the MSS COMM_BLK when certain + events such as Flash*Freeze shutdown, Flash*Freeze exit and power-on-reset + (POR) digest check errors are detected during the execution of the following + system services: + - Flash*Freeze + - Power-on-reset (POR) digest check + The asynchronous event handler function is registered with the System + Services driver through the MSS_SYS_init() function. The driver calls the + asynchronous event handler when the MSS COMM_BLK receives an asynchronous message. + */ +typedef void (*sys_serv_async_event_handler_t)(uint8_t event_opcode, uint8_t response); + +/*-------------------------------------------------------------------------*//** + This constant is used as parameter to the MSS_SYS_init() function to indicate + that the application code does not supply an asynchronous event handler + function. + */ +#define MSS_SYS_NO_EVENT_HANDLER ((sys_serv_async_event_handler_t)0) + +/*-------------------------------------------------------------------------*//** + The MSS_SYS_init function initializes the system services communication with + the System Controller. + + @param + The event_handler parameter specifies an optional asynchronous event + handler function. This event handler function is provided by the + application. It will be called by the System Services driver whenever an + asynchronous event is received from the SmartFusion2 System controller. + This event handler is typically used to handle entry and exit of + Flash*Freeze mode. + + @return + This function does not return a value. + */ +void MSS_SYS_init +( + sys_serv_async_event_handler_t event_handler +); + +/*============================================================================== + * Device and Design Information Services. + */ + +/*-------------------------------------------------------------------------*//** + The MSS_SYS_get_serial_number function fetches the 128-bit Device Serial + Number (DSN). + + @param p_serial_number + The p_serial_number parameter is a pointer to the 16-bytes buffer where the + serial number will be written by this system service. + + @return + The MSS_SYS_get_serial_number function returns one of following status codes: + - MSS_SYS_SUCCESS + - MSS_SYS_MEM_ACCESS_ERROR + - MSS_SYS_UNEXPECTED_ERROR + */ +uint8_t MSS_SYS_get_serial_number +( + uint8_t * p_serial_number +); + +/*-------------------------------------------------------------------------*//** + The MSS_SYS_get_user_code functions fetches the 32-bit USERCODE. + + @param p_user_code + The p_user_code parameter is a pointer to the 4-bytes buffer where the + USERCODE will be written by this system service. + + @return + The MSS_SYS_get_user_code function returns one of following status codes: + - MSS_SYS_SUCCESS + - MSS_SYS_MEM_ACCESS_ERROR + - MSS_SYS_UNEXPECTED_ERROR + */ +uint8_t MSS_SYS_get_user_code +( + uint8_t * p_user_code +); + +/*-------------------------------------------------------------------------*//** + The MSS_SYS_get_design_version function fetches the design version. + + @param p_design_version + The p_design_version parameter is a pointer to the 2-bytes buffer where the + design version will be written by this system service. + + @return + The MSS_SYS_get_design_version function returns one of following status codes: + - MSS_SYS_SUCCESS + - MSS_SYS_MEM_ACCESS_ERROR + - MSS_SYS_UNEXPECTED_ERROR + */ +uint8_t MSS_SYS_get_design_version +( + uint8_t * p_design_version +); + +/*-------------------------------------------------------------------------*//** + The MSS_SYS_get_device_certificate function fetches the device certificate. + + @param p_device_certificate + The p_device_certificate parameter is a pointer to the 512-bytes buffer + where the device certificate will be written by this system service. + + @return + The MSS_SYS_get_device_certificate function returns one of following status + codes: + - MSS_SYS_SUCCESS + - MSS_SYS_MEM_ACCESS_ERROR + - MSS_SYS_UNEXPECTED_ERROR + */ +uint8_t MSS_SYS_get_device_certificate +( + uint8_t * p_device_certificate +); + +/*-------------------------------------------------------------------------*//** + The MSS_SYS_get_secondary_device_certificate function fetches the secondary + device certificate. The secondary device certificate is second ECC Key + Certificate which is a 640-byte digitally-signed X-509 certificate programmed + during manufacturing. This certificate only contains the public key for the + ECC key and is otherwise unused by the device. + + @param p_secondary_device_certificate + The p_secondary_device_certificate parameter is a pointer to the 640-bytes + buffer where the secondary device certificate will be written by this system + service. + + @return + The MSS_SYS_get_secondary_device_certificate function returns one of + following status codes: + - MSS_SYS_SUCCESS + - MSS_SYS_MEM_ACCESS_ERROR + - MSS_SYS_UNEXPECTED_ERROR + */ +uint8_t MSS_SYS_get_secondary_device_certificate +( + uint8_t * p_secondary_device_certificate +); + +/*-------------------------------------------------------------------------*//** + The MSS_SYS_flash_freeze function requests the FPGA to enter the Flash*Freeze + mode. + + @param options + The options parameter can be used to power down additional parts of + SmartFusion2 when the FPGA fabric enters Flash*Freeze mode. This parameter + is a bit mask of the following options: + - MSS_SYS_FPGA_POWER_DOWN + - MSS_SYS_MPLL_POWER_DOWN + MSS_SYS_FPGA_POWER_DOWN on its own will only power down the FPGA fabric. + MSS_SYS_MPLL_POWER_DOWN specifies that the MSS PLL is powered down during + the Flash*Freeze period. + + @return + The MSS_SYS_flash_freeze function returns one of following status codes: + - MSS_SYS_SUCCESS + - MSS_SYS_SERVICE_DISABLED_BY_FACTORY + - MSS_SYS_SERVICE_DISABLED_BY_USER + - MSS_SYS_UNEXPECTED_ERROR + - MSS_SYS_CLK_DIVISOR_ERROR + + The following example demonstrates how to request the FPGA fabric to enter + the Flash*Freeze mode: + @code + MSS_SYS_flash_freeze(MSS_SYS_FPGA_POWER_DOWN | MSS_SYS_MPLL_POWER_DOWN); + @endcode + */ +uint8_t MSS_SYS_flash_freeze(uint8_t options); + +/*============================================================================== + * Cryptographic Services. + */ + +/*-------------------------------------------------------------------------*//** + The MSS_SYS_128bit_aes function provides access to the SmartFusion2 AES-128 + cryptography service. + + @param key + The key parameter is a pointer to a 16-bytes array containing the key to use + for the requested encryption/decryption operation. + + @param iv + The iv parameter is a pointer to a 16-bytes array containing the + initialization vector that will be used as part of the requested + encryption/decryption operation. Its use is different depending on the mode. + ----------------------------------------- + | Mode | Usage | + ----------------------------------------- + | ECB | Ignored. | + ----------------------------------------- + | CBC | Randomization. | + ----------------------------------------- + | OFB | Randomization. | + ----------------------------------------- + | CTR | Used as initial counter value. | + ----------------------------------------- + + @param nb_blocks + The nb_blocks parameter specifies the number of 128-bit blocks of + plaintext/ciphertext to be processed by the AES-128 system service. + + @param mode + The mode parameter specifies the cipher mode of operation and whether the + source text must be encrypted or decrypted. The modes of operation are: + - Electronic Codebook (ECB) + - Cipher-Block Chaining (CBC) + - Output Feedback (OFB) + - Counter (CTR) + The CTR mode uses the content of the initialization vector as its initial + counter value. The counter increment is 2^64. + Allowed values for the mode parameter are: + - MSS_SYS_ECB_ENCRYPT + - MSS_SYS_ECB_DECRYPT + - MSS_SYS_CBC_ENCRYPT + - MSS_SYS_CBC_DECRYPT + - MSS_SYS_OFB_ENCRYPT + - MSS_SYS_OFB_DECRYPT + - MSS_SYS_CTR_ENCRYPT + - MSS_SYS_CTR_DECRYPT + + @param dest_addr + The dest_addr parameter is a pointer to the memory buffer where the result + of the encryption/decryption operation will be stored. + + @param src_addr + The src_addr parameter is a pointer to the memory buffer containing the source + plaintext/ciphertext to be encrypted/decrypted. + + @return + The MSS_SYS_128bit_aes function returns one of following status codes: + - MSS_SYS_SUCCESS + - MSS_SYS_MEM_ACCESS_ERROR + - MSS_SYS_SERVICE_NOT_LICENSED + - MSS_SYS_SERVICE_DISABLED_BY_FACTORY + - MSS_SYS_SERVICE_DISABLED_BY_USER + */ +uint8_t MSS_SYS_128bit_aes +( + const uint8_t * key, + const uint8_t * iv, + uint16_t nb_blocks, + uint8_t mode, + uint8_t * dest_addr, + const uint8_t * src_addr +); + +/*-------------------------------------------------------------------------*//** + The MSS_SYS_256bit_aes function provides access to the SmartFusion2 AES-256 + cryptography service. + + @param key + The key parameter is a pointer to a 32-bytes array containing the key to use + for the requested encryption/decryption operation. + + @param iv + The iv parameter is a pointer to a 16-bytes array containing the + initialization vector that will be used as part of the requested + encryption/decryption operation. Its use is different depending on the mode. + ----------------------------------------- + | Mode | Usage | + ----------------------------------------- + | ECB | Ignored. | + ----------------------------------------- + | CBC | Randomization. | + ----------------------------------------- + | OFB | Randomization. | + ----------------------------------------- + | CTR | Used as initial counter value. | + ----------------------------------------- + + @param nb_blocks + The nb_blocks parameter specifies the number of 128-bit blocks of + plaintext/ciphertext requested to be processed by the AES-128 system service. + + @param mode + The mode parameter specifies the cipher mode of operation and whether the + source text must be encrypted or decrypted. The modes of operation are: + - Electronic Codebook (ECB) + - Cypher-Block Chaining (CBC) + - Output Feedback (OFB) + - Counter (CTR) + The CTR mode uses the content of the initialization vector as its initial + counter value. The counter increment is 2^64. + Allowed values for the mode parameter are: + - MSS_SYS_ECB_ENCRYPT + - MSS_SYS_ECB_DECRYPT + - MSS_SYS_CBC_ENCRYPT + - MSS_SYS_CBC_DECRYPT + - MSS_SYS_OFB_ENCRYPT + - MSS_SYS_OFB_DECRYPT + - MSS_SYS_CTR_ENCRYPT + - MSS_SYS_CTR_DECRYPT + + @param dest_addr + The dest_addr parameter is a pointer to the memory buffer where the result + of the encryption/decryption operation will be stored. + + @param src_addr + The src_addr parameter is a pointer to the memory buffer containing the source + plaintext/ciphertext to be encrypted/decrypted. + + @return + The MSS_SYS_256bit_aes function returns one of following status codes: + - MSS_SYS_SUCCESS + - MSS_SYS_MEM_ACCESS_ERROR + - MSS_SYS_SERVICE_NOT_LICENSED + - MSS_SYS_SERVICE_DISABLED_BY_FACTORY + - MSS_SYS_SERVICE_DISABLED_BY_USER + */ +uint8_t MSS_SYS_256bit_aes +( + const uint8_t * key, + const uint8_t * iv, + uint16_t nb_blocks, + uint8_t mode, + uint8_t * dest_addr, + const uint8_t * src_addr +); + +/*-------------------------------------------------------------------------*//** + The MSS_SYS_sha256 function provides access to the SmartFusion2 SHA-256 + cryptography service. + + @param p_data_in + The p_data_in parameter is a pointer to the memory location containing the + data that will be hashed using the SHA-256 system service. + + @param length + The length parameter specifies the length in bits of the data to hash. + + @param result + The result parameter is a pointer to a 32 bytes buffer where the hash result + will be stored. + + @return + The MSS_SYS_sha256 function returns one of following status codes: + - MSS_SYS_SUCCESS + - MSS_SYS_MEM_ACCESS_ERROR + - MSS_SYS_SERVICE_NOT_LICENSED + - MSS_SYS_SERVICE_DISABLED_BY_FACTORY + - MSS_SYS_SERVICE_DISABLED_BY_USER + */ +uint8_t MSS_SYS_sha256 +( + const uint8_t * p_data_in, + uint32_t length, + uint8_t * result +); + +/*-------------------------------------------------------------------------*//** + The MSS_SYS_hmac function provides access to the SmartFusion2 HMAC + cryptography service. The HMAC system service generates message authentication + codes using the SHA-256 hash function. + + @param key + The key parameter is a pointer to a 32 bytes array containing the key used + to generate the message authentication code. + + @param p_data_in + The p_data_in parameter is a pointer to the data to be authenticated. + + @param length + The length parameter specifies the number of data bytes for which to generate + the authentication code. It is the size of the data pointed to by the + p_data_in parameter. + + @param p_result + The p_result parameter is a pointer to a 32 bytes buffer where the + authentication code generated by the HMAC system service will be stored. + + @return + The MSS_SYS_hmac function returns one of following status codes: + - MSS_SYS_SUCCESS + - MSS_SYS_MEM_ACCESS_ERROR + - MSS_SYS_SERVICE_NOT_LICENSED + - MSS_SYS_SERVICE_DISABLED_BY_FACTORY + - MSS_SYS_SERVICE_DISABLED_BY_USER + */ +uint8_t MSS_SYS_hmac +( + const uint8_t * key, + const uint8_t * p_data_in, + uint32_t length, + uint8_t * p_result +); + +/*-------------------------------------------------------------------------*//** + The MSS_SYS_key_tree() function provides access to a SHA-256 based key-tree + cryptography algorithm. The key-tree service begins with a user-supplied root + key and derives an output key based on a 7-bit parameter which can be used to + create uniqueness for different applications using the same root key, and a + 128-bit path variable. Both the 7-bit input parameter and the 128-bit path + variable are assumed to be publicly known. One common use for the output key + is as a keyed validator, similar to a message authentication code tag. + + @param p_key + The p_key parameter is a pointer to a 32 bytes array containing root key + used to generate derived key by Key Tree service and also used to store the + derived key. + + @param op_type + The op_type parameter specifies the operational parameter to be used to + generate the output key. + + @param path + The path parameter specifies the 128-bit path to be used to generate the + output key. + + @return + The MSS_SYS_key_tree function returns one of following status codes: + - MSS_SYS_SUCCESS + - MSS_SYS_MEM_ACCESS_ERROR + - MSS_SYS_SERVICE_NOT_LICENSED + - MSS_SYS_MEM_ACCESS_ERROR + - MSS_SYS_SERVICE_DISABLED_BY_USER + */ +uint8_t MSS_SYS_key_tree +( + uint8_t* p_key, + uint8_t op_type, + const uint8_t* path +); + +/*-------------------------------------------------------------------------*//** + The MSS_SYS_challenge_response function... + + The MSS_SYS_challenge_response() function accept a challenge comprising a + 7-bit optype and 128-bit path and return a 256-bit response unique to the + given challenge and the device. + + @param p_key + The key parameter is a pointer to a 32 bytes array containing 256 bit + unique response to the given challenge. + + @param op_type + The op_type parameter specifies the operational parameter to be used to + generate the unique 256-bits unique response. + + @param path + The path parameter specifies the 128-bit path to be used to generate the + unique 256-bits unique response. + + @return + The MSS_SYS_challenge_response function returns one of following status + codes: + - MSS_SYS_SUCCESS + - MSS_SYS_MEM_ACCESS_ERROR + - MSS_SYS_SERVICE_NOT_LICENSED + - MSS_SYS_SERVICE_DISABLED_BY_FACTORY + - MSS_SYS_SERVICE_DISABLED_BY_USER + */ +uint8_t MSS_SYS_challenge_response +( + uint8_t* p_key, + uint8_t op_type, + const uint8_t* path +); + +/*============================================================================== + * Non Deterministic Random Bit Generator Services. + */ + /*-------------------------------------------------------------------------*//** + The MSS_SYS_nrbg_reset() function is used to reset the + non-deterministic random bit generator (NRBG). + + @return + The MSS_SYS_nrbg_self_test function returns one of following status codes: + - MSS_SYS_SUCCESS + - MSS_SYS_NRBG_CATASTROPHIC_ERROR + - MSS_SYS_NRBG_MAX_INST_EXCEEDED + - MSS_SYS_NRBG_INVALID_HANDLE + - MSS_SYS_NRBG_GEN_REQ_TOO_BIG + - MSS_SYS_NRBG_MAX_LENGTH_EXCEEDED + - MSS_SYS_MEM_ACCESS_ERROR + - MSS_SYS_SERVICE_NOT_LICENSED + - MSS_SYS_SERVICE_DISABLED_BY_FACTORY + - MSS_SYS_SERVICE_DISABLED_BY_USER + - MSS_SYS_UNEXPECTED_ERROR +*/ +uint8_t MSS_SYS_nrbg_reset(void); + +/*-------------------------------------------------------------------------*//** + The MSS_SYS_nrbg_self_test() function performs a self test of the + non-deterministic random bit generator (NRBG). + + @return + The MSS_SYS_nrbg_self_test function returns one of following status codes: + - MSS_SYS_SUCCESS + - MSS_SYS_NRBG_CATASTROPHIC_ERROR + - MSS_SYS_NRBG_MAX_INST_EXCEEDED + - MSS_SYS_NRBG_INVALID_HANDLE + - MSS_SYS_NRBG_GEN_REQ_TOO_BIG + - MSS_SYS_NRBG_MAX_LENGTH_EXCEEDED + - MSS_SYS_MEM_ACCESS_ERROR + - MSS_SYS_SERVICE_NOT_LICENSED + - MSS_SYS_SERVICE_DISABLED_BY_FACTORY + - MSS_SYS_SERVICE_DISABLED_BY_USER + - MSS_SYS_UNEXPECTED_ERROR + */ +uint8_t MSS_SYS_nrbg_self_test(void); + +/*-------------------------------------------------------------------------*//** + The MSS_SYS_nrbg_instantiate() function instantiates a non-deterministic + random bit generator (NRBG) instance. A maximum of two concurrent instances + are available. + + @param personalization_str + The personalization_str parameter is a pointer to a buffer containing a + random bit generator personalization string. The personalization string + can be up to 128 bytes long. + + @param personalization_str_length + The personalization_str_length parameter specifies the byte length of the + personalization string pointed to by personalization_str. + + @param p_nrbg_handle + The p_nrbg_handle parameter is a pointer to a byte that will contain the + handle of the instantiated NRBG if this function call succeeds. + + @return + The MSS_SYS_nrbg_instantiate function returns one of following status codes: + - MSS_SYS_SUCCESS + - MSS_SYS_NRBG_CATASTROPHIC_ERROR + - MSS_SYS_NRBG_MAX_INST_EXCEEDED + - MSS_SYS_NRBG_INVALID_HANDLE + - MSS_SYS_NRBG_GEN_REQ_TOO_BIG + - MSS_SYS_NRBG_MAX_LENGTH_EXCEEDED + - MSS_SYS_MEM_ACCESS_ERROR + - MSS_SYS_SERVICE_NOT_LICENSED + - MSS_SYS_SERVICE_DISABLED_BY_FACTORY + - MSS_SYS_SERVICE_DISABLED_BY_USER + */ +uint8_t MSS_SYS_nrbg_instantiate +( + const uint8_t * personalization_str, + uint16_t personalization_str_length, + uint8_t * p_nrbg_handle +); + +/*-------------------------------------------------------------------------*//** + The MSS_SYS_nrbg_generate function generates a random bit sequence up to + 128 bytes long. + + @param p_requested_data + The p_requested_data parameter is a pointer to the buffer where the requested + random data will be stored on completion of this system service. + + @param p_additional_input + The p_additional_input parameter is a pointer to the buffer containing + additional input data for the random bit generation. + + @param requested_length + The requested_length parameter specifies the number of random data bytes + requested to be generated. The maximum generated data length is 128 bytes. + + @param additional_input_length + The additional_input_length parameter specifies the number of additional + input bytes to use in the random data generation. + + @param pr_req + The pr_req parameter specifies if prediction resistance is requested. + + @param nrbg_handle + The nrbg_handle parameter specifies which non-deterministic random bit + generator (NRBG) instance will be used to generate the random data. The + value of nrbg_handle is obtained as a result of a previous call to the + MSS_SYS_nrbg_instantiate() function. + + @return + The MSS_SYS_nrbg_generate function returns one of following status codes: + - MSS_SYS_SUCCESS + - MSS_SYS_NRBG_CATASTROPHIC_ERROR + - MSS_SYS_NRBG_MAX_INST_EXCEEDED + - MSS_SYS_NRBG_INVALID_HANDLE + - MSS_SYS_NRBG_GEN_REQ_TOO_BIG + - MSS_SYS_NRBG_MAX_LENGTH_EXCEEDED + - MSS_SYS_MEM_ACCESS_ERROR + - MSS_SYS_SERVICE_NOT_LICENSED + - MSS_SYS_SERVICE_DISABLED_BY_FACTORY + - MSS_SYS_SERVICE_DISABLED_BY_USER + */ +uint8_t MSS_SYS_nrbg_generate +( + const uint8_t * p_requested_data, + const uint8_t * p_additional_input, + uint8_t requested_length, + uint8_t additional_input_length, + uint8_t pr_req, + uint8_t nrbg_handle +); + +/*-------------------------------------------------------------------------*//** + The MSS_SYS_nrbg_reseed() function is used to reseed the non-deterministic + random bit generator (NRBG) identified by the nrbg_handle parameter. + + @param p_additional_input + The additional_input_length parameter specifies the number of additional + input bytes used to reseed the NRBG identified by the nrbg_handle parameter. + + @param additional_input_length + The additional_input_length parameter specifies the number of additional + input bytes used to reseed the NRBG. + + @param nrbg_handle + The nrbg_handle parameter specifies which NRBG instance to reseed. The value + of nrbg_handle is obtained as a result of a previous call to the + MSS_SYS_nrbg_instantiate() function. + + @return + The MSS_SYS_nrbg_reseed function returns one of following status codes: + - MSS_SYS_SUCCESS + - MSS_SYS_NRBG_CATASTROPHIC_ERROR + - MSS_SYS_NRBG_MAX_INST_EXCEEDED + - MSS_SYS_NRBG_INVALID_HANDLE + - MSS_SYS_NRBG_GEN_REQ_TOO_BIG + - MSS_SYS_NRBG_MAX_LENGTH_EXCEEDED + - MSS_SYS_MEM_ACCESS_ERROR + - MSS_SYS_SERVICE_NOT_LICENSED + - MSS_SYS_SERVICE_DISABLED_BY_FACTORY + - MSS_SYS_SERVICE_DISABLED_BY_USER + + */ +uint8_t MSS_SYS_nrbg_reseed +( + const uint8_t * p_additional_input, + uint8_t additional_input_length, + uint8_t nrbg_handle +); + +/*-------------------------------------------------------------------------*//** + The MSS_SYS_nrbg_uninstantiate() function releases the non-deterministic + random bit generator (NRBG) identified by the nrbg_handle parameter. + + @param nrbg_handle + The nrbg_handle parameter specifies which NRBG instance will be released. + The value of nrbg_handle is obtained as a result of a previous call to the + MSS_SYS_nrbg_instantiate() function. + + @return + The MSS_SYS_nrbg_uninstantiate function returns one of following status codes: + - MSS_SYS_SUCCESS + - MSS_SYS_NRBG_CATASTROPHIC_ERROR + - MSS_SYS_NRBG_MAX_INST_EXCEEDED + - MSS_SYS_NRBG_INVALID_HANDLE + - MSS_SYS_NRBG_GEN_REQ_TOO_BIG + - MSS_SYS_NRBG_MAX_LENGTH_EXCEEDED + - MSS_SYS_MEM_ACCESS_ERROR + - MSS_SYS_SERVICE_NOT_LICENSED + - MSS_SYS_SERVICE_DISABLED_BY_FACTORY + - MSS_SYS_SERVICE_DISABLED_BY_USER + - MSS_SYS_UNEXPECTED_ERROR + */ +uint8_t MSS_SYS_nrbg_uninstantiate +( + uint8_t nrbg_handle +); + +/*============================================================================== + * Zeroization Services. + */ +/*-------------------------------------------------------------------------*//** + The MSS_SYS_zeroize_device() function destroys sensitive information stored on + the device. Zeroization system services driver will destroy all user configuration + data, user keys, user security settings, NVM, SRAM, FPGA fabric, system + controller memory, and crypto-engine registers are erased. The level of + information destroyed by this function is configured as part of the hardware + flow of the design programmed into the device. + + @param + This function does not take any parameters + + @return + This function does not return any value. +*/ +void MSS_SYS_zeroize_device +( + void +); + +/*============================================================================== + * Programming Services. + */ + +#define MSS_SYS_PROG_AUTHENTICATE 0u +#define MSS_SYS_PROG_PROGRAM 1u +#define MSS_SYS_PROG_VERIFY 2u + +/*-------------------------------------------------------------------------*//** + The MSS_SYS_start_isp() function starts the In-System Programming (ISP) + system service which allows the Cortex-M3 processor to directly provide a + bitstream for programming the SmartFusion2 device. + The ISP system service can perform these services: + � Authenticate a programming bitstream + � Program the device with a programming bitstream + � Verify that a programming bitstream has been correctly programmed + The mode parameter specifies the ISP system service to perform. The + application must also provide two functions as parameters to the + MSS_SYS_start_isp() function. The first function is used by the ISP system + service to read the programming bitstream. The second function is used by + the ISP system service to notify the application that the ISP system service + has completed. + + @param mode + The mode parameter specifies ISP service to perform. It can be one of: + - MSS_SYS_PROG_AUTHENTICATE + - MSS_SYS_PROG_PROGRAM + - MSS_SYS_PROG_VERIFY + + @param page_read_handler + The page_read_handler parameter is a pointer to a function with the + following prototype: + uint32_t page_read_handler(uint8 const ** pp_next_page); + The page_read_handler function must be implemented by the application + program to provide the System Services driver with the address of the + next page of programming data to be sent to the System Controller and + the number of bytes contained in the next page. Refer to the description + of the comblk_page_handler_t type for details of the page_read_handler + function�s parameters and return values. + + @param isp_completion_handler + The isp_completion_handler parameter is a pointer to a function with the + following prototype. + void (*sys_serv_isp_complete_handler_t)(uint32_t status); + The isp_completion_handler function must be implemented by the application + program and it is called by the System Services driver when an ISP + operation initiated by a call to MSS_SYS_start_isp() completes. + + The isp_completion_handler function receives one of the following status + codes through its status parameter indicating the outcome of the ISP + operation: + - MSS_SYS_SUCCESS + - MSS_SYS_CHAINING_MISMATCH + - MSS_SYS_UNEXPECTED_DATA_RECEIVED + - MSS_SYS_INVALID_ENCRYPTION_KEY + - MSS_SYS_INVALID_COMPONENT_HEADER + - MSS_SYS_BACK_LEVEL_NOT_SATISFIED + - MSS_SYS_DSN_BINDING_MISMATCH + - MSS_SYS_ILLEGAL_COMPONENT_SEQUENCE + - MSS_SYS_INSUFFICIENT_DEV_CAPABILITIES + - MSS_SYS_INCORRECT_DEVICE_ID + - MSS_SYS_UNSUPPORTED_BITSTREAM_PROT_VER + - MSS_SYS_VERIFY_NOT_PERMITTED_ON_BITSTR + - MSS_SYS_ABORT + - MSS_SYS_NVM_VERIFY_FAILED + - MSS_SYS_DEVICE_SECURITY_PROTECTED + - MSS_SYS_PROGRAMMING_MODE_NOT_ENABLED + - MSS_SYS_SERVICE_DISABLED_BY_USER + + @return + This function return status as MSS_SYS_CLK_DIVISOR_ERROR, if fclk, pclk0, + pclk1 and clk_fic64 divisor are not equal to each other or set to divide by + 32 on 060 device. + */ +uint8_t MSS_SYS_start_isp +( + uint8_t mode, + comblk_page_handler_t page_read_handler, + sys_serv_isp_complete_handler_t isp_completion_handler +); + + +/*-------------------------------------------------------------------------*//** + The MSS_SYS_initiate_iap() function invokes the In application programming + system service by sending the request to System Controller to reprogram the + device using a bitstream present in SPI FLASH connected to MSS SPI-0. The + IAP Service is initiated by a call to MSS_SYS_initiate_iap(). The IAP + Service can perform these services: + - authenticate a programming bitstream + - program a bitstream + - verify that a programming bitstream has been correctly programmed + + @param mode + The mode parameter specifies IAP service to perform. It can be one of: + - MSS_SYS_PROG_AUTHENTICATE + - MSS_SYS_PROG_PROGRAM + - MSS_SYS_PROG_VERIFY + + @param bitstream_spi_addr + The bitstream_spi_addr parameter specifies the starting location address of + the programmed bitstream present in SPI flash connected to MSS SPI 0. + User should copy the programming bitstream into SPI Flash before calling + IAP system service. + + @return + The MSS_SYS_initiate_iap function will receive one of the following status + codes: + - MSS_SYS_SUCCESS + - MSS_SYS_CHAINING_MISMATCH + - MSS_SYS_UNEXPECTED_DATA_RECEIVED + - MSS_SYS_INVALID_ENCRYPTION_KEY + - MSS_SYS_INVALID_COMPONENT_HEADER + - MSS_SYS_BACK_LEVEL_NOT_SATISFIED + - MSS_SYS_DSN_BINDING_MISMATCH + - MSS_SYS_ILLEGAL_COMPONENT_SEQUENCE + - MSS_SYS_INSUFFICIENT_DEV_CAPABILITIES + - MSS_SYS_INCORRECT_DEVICE_ID + - MSS_SYS_UNSUPPORTED_BITSTREAM_PROT_VER + - MSS_SYS_VERIFY_NOT_PERMITTED_ON_BITSTR + - MSS_SYS_INVALID_DEVICE_CERTIFICATE + - MSS_SYS_ABORT + - MSS_SYS_NVM_VERIFY_FAILED + - MSS_SYS_DEVICE_SECURITY_PROTECTED + - MSS_SYS_PROGRAMMING_MODE_NOT_ENABLED + - MSS_SYS_ENVM_PROGRAMMING_OPERATION_FAIL + - MSS_SYS_ENVM_VERIFY_OPERATION_FAIL + - MSS_SYS_ACCESS_ERROR + - MSS_SYS_PUF_ACCESS_ERROR + - MSS_SYS_BAD_COMPONENT + - MSS_SYS_SERVICE_DISABLED_BY_USER + - MSS_SYS_CLK_DIVISOR_ERROR +*/ +uint8_t MSS_SYS_initiate_iap +( + uint8_t mode, + uint32_t bitstream_spi_addr +); + +/*-------------------------------------------------------------------------*//** + The MSS_SYS_check_digest() function is used to recalculate and compare + cryptographic digests of selected NVM component(s) � FPGA fabric, eNVM0, and + eNVM1 � to those previously computed and saved in NVM. + Note: The FPGA fabric will enter the Flash*Freeze state if it is powered up + when its digest is checked. + + @param options + The options parameter specifies which components' digest will be recalculated + and checked. The allowed values for the options parameter are any one of the + following bitmask constants or a bitwise OR of more than one: + � MSS_SYS_DIGEST_CHECK_FABRIC (bit mask = 0x01) + � MSS_SYS_DIGEST_CHECK_ENVM0 (bit mask = 0x02) + � MSS_SYS_DIGEST_CHECK_ENVM1 (bit mask = 0x04) + � MSS_SYS_DIGEST_CHECK_SYS (bit mask = 0x08) + � MSS_SYS_DIGEST_CHECK_ENVMFP (bit mask = 0x10) + � MSS_SYS_DIGEST_CHECK_ENVMUP (bit mask = 0x20) + NOTE: Private factory eNVM and private user eNVM digest checks are only + available on the M2S060 and larger devices. + @return + The MSS_SYS_check_digest function returns the result of the digest check as + an 8-bit unsigned integer. The meaning of the digest check return value is + as follows: + bit 0: Fabric digest error + bit 1: ENVM0 digest error + bit 2: ENVM1 digest error + bit 3: System Controller ROM digest error + bit 4: Private eNVM factory digest error + bit 5: Private eNVM user digest error + bit 7: Service Disable by user lock. + A '1' in one of the above bits indicates a digest mismatch. The return + value can be compared to the bitmask constants specified as allowed values + for the options parameter to discover which of the NVM components produced + a digest check error. + On 060 device, the MSS_SYS_check_digest function returns + MSS_SYS_CLK_DIVISOR_ERROR, if the the divisor values of fclk, pclk0, pclk1 + and clk_fic64 divisor are not equal to each other or set to divide by 32. + */ +#define MSS_SYS_DIGEST_CHECK_FABRIC 0x01u +#define MSS_SYS_DIGEST_CHECK_ENVM0 0x02u +#define MSS_SYS_DIGEST_CHECK_ENVM1 0x04u +#define MSS_SYS_DIGEST_CHECK_SYS 0x08u +#define MSS_SYS_DIGEST_CHECK_ENVMFP 0x10u +#define MSS_SYS_DIGEST_CHECK_ENVMUP 0x20u + +#define MSS_SYS_DIGEST_CHECK_SVCDISABLED 0x80u + +uint8_t MSS_SYS_check_digest +( + uint8_t options +); + +/*-------------------------------------------------------------------------*//** + The MSS_SYS_puf_create_activation_code() function is used to create the + SRAM-PUF user activation code. This function is typically only used once when + enrolling the device into the overall system it operates in. It creates an + activation code which will be used to regenerate the SRAM-PUF secret key after + each power-up of the SRAM-PUF. The activation code is used to eliminate the + randomness of the SRAM-PUF power-up content in order to retrieve the device�s + unique PUF secret key. + Note: This system service is only available on large SmartFusion2 devices + starting with the M2S060. + + @param + This function does not take any parameters. + + @return + The MSS_SYS_puf_create_activation_code() function returns one of the + following status codes: + - MSS_SYS_SUCCESS + - MSS_SYS_ENVM_ERROR + - MSS_SYS_PUF_ERROR_WHEN_CREATING + - MSS_SYS_INVALID_SUBCMD + - MSS_SYS_ENVM_PROGRAM_ERROR + - MSS_SYS_ENVM_VERIFY_ERROR + - MSS_SYS_MEM_ACCESS_ERROR + - MSS_SYS_SERVICE_NOT_LICENSED + - MSS_SYS_SERVICE_DISABLED_BY_FACTORY + - MSS_SYS_SERVICE_DISABLED_BY_USER + - MSS_SYS_UNEXPECTED_ERROR +*/ +uint8_t MSS_SYS_puf_create_activation_code +( + void +); + +/*-------------------------------------------------------------------------*//** + The MSS_SYS_puf_delete_activation_code() function is used to delete the user + activation code. This function would typically be used only once when + decommissioning the device. + Note: This system services is only available on large SmartFusion2 devices + starting with the M2S060. + + @param + This function does not take any parameters. + + @return + The MSS_SYS_puf_delete_activation_code() function returns one of the + following status codes: + - MSS_SYS_SUCCESS + - MSS_SYS_ENVM_ERROR + - MSS_SYS_PUF_ERROR_WHEN_CREATING + - MSS_SYS_INVALID_SUBCMD + - MSS_SYS_ENVM_PROGRAM_ERROR + - MSS_SYS_ENVM_VERIFY_ERROR + - MSS_SYS_MEM_ACCESS_ERROR + - MSS_SYS_SERVICE_NOT_LICENSED + - MSS_SYS_SERVICE_DISABLED_BY_FACTORY + - MSS_SYS_SERVICE_DISABLED_BY_USER + - MSS_SYS_UNEXPECTED_ERROR +*/ +uint8_t MSS_SYS_puf_delete_activation_code +( + void +); + +/*-------------------------------------------------------------------------*//** + The MSS_SYS_puf_get_number_of_keys() function is used to retrieve the number + of user keys enrolled with the SRAM-PUF service. The number of enrolled keys + is also the key identification number to use for the next key to enroll since + keys must be enrolled sequentially and the key numbering starts at zero. Up + to 58 keys can be enrolled. Keys number 0 and 1 are used for design security + and are not available to the user. + Note: This system service is only available on large SmartFusion2 devices + starting with the M2S060. + + @param p_number_of_user_keys + The p_user_key parameter is a pointer to the byte in which the number of + keys will be written on successful completion of the system service. + + @return + The MSS_SYS_puf_get_number_of_user_keys() function returns one of the + following status codes: + - MSS_SYS_SUCCESS + - MSS_SYS_ENVM_ERROR + - MSS_SYS_PUF_ERROR_WHEN_CREATING + - MSS_SYS_ENVM_PROGRAM_ERROR + - MSS_SYS_INVALID_HASH + - MSS_SYS_INVALID_USER_AC1 + - MSS_SYS_ENVM_VERIFY_ERROR + - MSS_SYS_PRIVATE_ENVM_USER_DIGEST_MISMATCH + - MSS_SYS_DRBG_ERROR + - MSS_SYS_MEM_ACCESS_ERROR + - MSS_SYS_SERVICE_NOT_LICENSED + - MSS_SYS_SERVICE_DISABLED_BY_FACTORY + - MSS_SYS_SERVICE_DISABLED_BY_USER + - MSS_SYS_UNEXPECTED_ERROR +*/ +uint8_t MSS_SYS_puf_get_number_of_keys +( + uint8_t* p_number_of_keys +); + +/*-------------------------------------------------------------------------*//** + The MSS_SYS_puf_enroll_key() function is used to enroll keys into the + SRAM-PUF hardware block. Keys can be either intrinsic keys or extrinsic keys. + An intrinsic key�s value is randomly generated by the SRAM-PUF hardware block + during key enrollment. An extrinsic key�s value is supplied by the user. A key + code is created and stored in the System Controller�s private eNVM during key + enrollment. The key code along with the activation code created as part of the + call to MSS_SYS_puf_create_activation_code() and the SRAM-PUF start-up value + can then be used later to regenerate the enrolled key�s value. Enrolled keys + can be later reconstructed and retrieved using the MSS_SYS_puf_fetch_key() + function. The value of the key is protected until it is fetched since its + actual value is not stored anywhere in the system. + Note: This system service is only available on large SmartFusion2 devices + starting with the M2S060. + + @param key_number + The key_number parameter specifies the key number that will be used to + identify the key in later use after enrollment. The key number will be used + to identify which key to retrieve in subsequent calls to function + MSS_SYS_puf_fetch_key(). + Keys must be enrolled sequentially. Therefore, an arbitrary value cannot be + used for key_number when enrolling a new key. The value for key_number must + be derived from a call to MSS_SYS_puf_get_number_of_keys() to find the + number of keys currently enrolled and derive the next key number in the + sequence. + Note: Valid values for key identification numbers are 2 to 57. Keys number + 0 and 1 are used for design security and not available to the user. + + @param key_size + The key_size parameter specifies the size of the key to enroll. The key size + is a multiple of 64-bit up to 4096-bit. + + @param p_key_value + The p_key_value parameter is a pointer to the buffer containing the value of + the key to enroll. The buffer pointed to by p_key_value contains the value + of the extrinsic key specified by the user. + Setting this pointer�s value to zero specifies that an intrinsic key is to + be enrolled. In this case, a random value is generated using the SRAM-PUF as + the key value. + + @param p_key_location + The p_key_location parameter is a pointer to the buffer where the key will + be copied when it is fetched through a call to MSS_SYS_puf_fetch_key(). + + @return + The MSS_SYS_puf_enroll_key() function returns one of the following status + codes: + - MSS_SYS_SUCCESS + - MSS_SYS_ENVM_ERROR + - MSS_SYS_PUF_ERROR_WHEN_CREATING + - MSS_SYS_INVALID_REQUEST_OR_KC + - MSS_SYS_ENVM_PROGRAM_ERROR + - MSS_SYS_INVALID_HASH + - MSS_SYS_INVALID_USER_AC1 + - MSS_SYS_ENVM_VERIFY_ERROR + - MSS_SYS_INCORRECT_KEYSIZE_FOR_RENEWING_A_KC + - MSS_SYS_PRIVATE_ENVM_USER_DIGEST_MISMATCH + - MSS_SYS_USER_KEY_CODE_INVALID_SUBCMD + - MSS_SYS_DRBG_ERROR + - MSS_SYS_MEM_ACCESS_ERROR + - MSS_SYS_SERVICE_NOT_LICENSED + - MSS_SYS_SERVICE_DISABLED_BY_FACTORY + - MSS_SYS_SERVICE_DISABLED_BY_USER + - MSS_SYS_UNEXPECTED_ERROR +*/ +uint8_t MSS_SYS_puf_enroll_key +( + uint8_t key_number, + uint16_t key_size, + uint8_t* p_key_value, + uint8_t* p_key_location +); + +/*-------------------------------------------------------------------------*//** + The MSS_SYS_puf_delete_key() function is used to delete a previously enrolled + key from the SRAM-PUF. + Note: This system service is only available on large SmartFusion2 devices + starting with the M2S060. + + @param key_number + The key_number parameter specifies the key number of the key to delete. + + @return + The MSS_SYS_puf_delete_key() function returns one of the following status + codes: + - MSS_SYS_SUCCESS + - MSS_SYS_ENVM_ERROR + - MSS_SYS_PUF_ERROR_WHEN_CREATING + - MSS_SYS_INVALID_REQUEST_OR_KC + - MSS_SYS_ENVM_PROGRAM_ERROR + - MSS_SYS_INVALID_HASH + - MSS_SYS_INVALID_USER_AC1 + - MSS_SYS_ENVM_VERIFY_ERROR + - MSS_SYS_INCORRECT_KEYSIZE_FOR_RENEWING_A_KC + - MSS_SYS_PRIVATE_ENVM_USER_DIGEST_MISMATCH + - MSS_SYS_USER_KEY_CODE_INVALID_SUBCMD + - MSS_SYS_DRBG_ERROR + - MSS_SYS_MEM_ACCESS_ERROR + - MSS_SYS_SERVICE_NOT_LICENSED + - MSS_SYS_SERVICE_DISABLED_BY_FACTORY + - MSS_SYS_SERVICE_DISABLED_BY_USER + - MSS_SYS_UNEXPECTED_ERROR +*/ +uint8_t MSS_SYS_puf_delete_key +( + uint8_t key_number +); + +/*-------------------------------------------------------------------------*//** + The MSS_SYS_puf_fetch_key() function is used to retrieve a user PUF key from + the SRAM-PUF hardware block. The key must have been previously enrolled using + the MSS_SYS_puf_enroll_key() function. The key to retrieve is identified + through the key number used at key enrollment time. The key value is copied + into the buffer location specified at key enrollment time. The location of + this buffer is returned through function argument pp_key. + The key value is reconstructed based on the SRAM-PUF power-on value, the + activation code created when the device was commissioned using the + MSS_SYS_puf_create_activation_code() function and the key code stored in the + SRAM-PUF hardware block�s private eNVM at key enrollment time. The key value + does not exist anywhere in the system until it is retrieved by a call to + MSS_SYS_puf_fetch_key(). Care must be taken to destroy the key value returned + by MSS_SYS_puf_fetch_key() once it is not required anymore. + Note: This system service is only available on large SmartFusion2 devices + starting with the M2S060. + + @param key_number + The key_number parameter specifies the key number identifying the user key + to fetch. The valid range of key numbers is from 2 to 57. + + @param pp_key + The pp_key parameter is a pointer to a pointer to the buffer that will + contain the user key value on successful completion of the system service. + The pp_key parameter can be set to zero if your application keeps track of + the location of the key specified though the call to function + MSS_SYS_puf_enroll_key() at key enrollment time. + + @return + The MSS_SYS_puf_fetch_key() function returns one of the following status + codes: + - MSS_SYS_SUCCESS + - MSS_SYS_PUF_ERROR_WHEN_CREATING + - MSS_SYS_INVALID_KEYNUM_OR_ARGUMENT + - MSS_SYS_INVALID_HASH + - MSS_SYS_PRIVATE_ENVM_USER_DIGEST_MISMATCH + - MSS_SYS_MEM_ACCESS_ERROR + - MSS_SYS_SERVICE_NOT_LICENSED + - MSS_SYS_SERVICE_DISABLED_BY_FACTORY + - MSS_SYS_SERVICE_DISABLED_BY_USER + - MSS_SYS_UNEXPECTED_ERROR +*/ +uint8_t MSS_SYS_puf_fetch_key +( + uint8_t key_number, + uint8_t ** pp_key +); + +/*-------------------------------------------------------------------------*//** + The MSS_SYS_puf_export_keycodes() function is used to export an encrypted + copy of all the key codes used internally by the SRAM-PUF hardware block to + reconstruct the enrolled keys. Up to 3894 bytes of data can be exported + depending on the number and size of keys enrolled. + Keys cannot be fetched any more after calling MSS_SYS_puf_export_keycodes() + until a subsequent call to function MSS_SYS_puf_import_keycodes() is made + with the exported encrypted key codes. + Calling MSS_SYS_puf_export_keycodes() and moving the exported data off chip + is similar to removing the enrolled keys from the device. The enrolled keys + will only be available again if the exported key codes are imported back into + the device. + A SmartFusion2 device will only accept imported key codes generated from the + last set of enrolled keys on that specific device. This makes the exported + key codes data specific to one unique SmartFuson2 device. Key codes cannot + be exported from one SmartFusion2 device and imported into another + SmartFusion2 device. The exported key codes data is specific to the unique + SmartFusion2 device it was exported from. + Keys cannot be reconstructed from the exported key codes data since the + intrinsic secret of the SRAM-PUF is required to reconstruct the keys from + the key codes. Furthermore, the key codes data is also encrypted using a + random key generated from the SRAM-PUF thus preventing an attacker from + deriving useful information from the exported key codes data. + Note: This system service is only available on large SmartFusion2 devices + starting with the M2S060. + + @param p_keycodes + The p_keycodes parameter is a pointer to the buffer where the PUF key codes + will be exported. + + @return + The MSS_SYS_puf_export_keycodes() function returns one of the following + status codes: + - MSS_SYS_SUCCESS + - MSS_SYS_ENVM_ERROR + - MSS_SYS_PUF_ERROR_WHEN_CREATING + - MSS_SYS_INVALID_REQUEST_OR_KC + - MSS_SYS_ENVM_PROGRAM_ERROR + - MSS_SYS_INVALID_HASH + - MSS_SYS_INVALID_USER_AC1 + - MSS_SYS_ENVM_VERIFY_ERROR + - MSS_SYS_INCORRECT_KEYSIZE_FOR_RENEWING_A_KC + - MSS_SYS_PRIVATE_ENVM_USER_DIGEST_MISMATCH + - MSS_SYS_USER_KEY_CODE_INVALID_SUBCMD + - MSS_SYS_DRBG_ERROR + - MSS_SYS_MEM_ACCESS_ERROR + - MSS_SYS_SERVICE_NOT_LICENSED + - MSS_SYS_SERVICE_DISABLED_BY_FACTORY + - MSS_SYS_SERVICE_DISABLED_BY_USER + - MSS_SYS_UNEXPECTED_ERROR + */ +uint8_t MSS_SYS_puf_export_keycodes +( + uint8_t * p_keycodes +); + +/*-------------------------------------------------------------------------*//** + The MSS_SYS_puf_import_keycodes() function is used to import a set of PUF + key codes that was previously exported using the MSS_SYS_puf_export_keycodes() + function. Importing the exported key codes allows the enrolled keys to be + regenerated. Enrolled keys cannot be regenerated while the key codes have + been exported and not imported back. + Importing back the key codes results in all keys being regenerated and copied + to the memory locations specified during key enrollment. The content of the + buffer holding the imported key codes is modified by function + MSS_SYS_puf_import_keycodes() to contain the list of pointers to the + locations where the keys have been regenerated. This list starts with the + address where key number 2 has been regenerated. The location for keys 0 and + 1 are not contained in that list because these keys are used for design + security and are not accessible to the user. + Note: This system service is only available on large SmartFusion2 devices + starting with the M2S060. + + @param p_keycodes + The p_keycodes parameter is a pointer to the buffer containing the PUF key + codes to import. + + @return + The MSS_SYS_puf_import_keycodes() function returns one of the following status codes: + - MSS_SYS_SUCCESS + - MSS_SYS_ENVM_ERROR + - MSS_SYS_PUF_ERROR_WHEN_CREATING + - MSS_SYS_INVALID_REQUEST_OR_KC + - MSS_SYS_ENVM_PROGRAM_ERROR + - MSS_SYS_INVALID_HASH + - MSS_SYS_INVALID_USER_AC1 + - MSS_SYS_ENVM_VERIFY_ERROR + - MSS_SYS_INCORRECT_KEYSIZE_FOR_RENEWING_A_KC + - MSS_SYS_PRIVATE_ENVM_USER_DIGEST_MISMATCH + - MSS_SYS_USER_KEY_CODE_INVALID_SUBCMD + - MSS_SYS_DRBG_ERROR + - MSS_SYS_MEM_ACCESS_ERROR + - MSS_SYS_SERVICE_NOT_LICENSED + - MSS_SYS_SERVICE_DISABLED_BY_FACTORY + - MSS_SYS_SERVICE_DISABLED_BY_USER + - MSS_SYS_UNEXPECTED_ERROR + */ +uint8_t MSS_SYS_puf_import_keycodes +( + uint8_t * p_keycodes +); + +/*-------------------------------------------------------------------------*//** + The MSS_SYS_puf_fetch_ecc_public_key() function is used to fetch PUF ECC + public key from eNVM. + + @param p_puf_public_key + The p_puf_public_key parameter is a pointer to buffer where the PUF ECC + public key will be stored on successful completion of system service. + Note: This system service is only available on large SmartFusion2 devices + starting with the M2S060. + + @return + The MSS_SYS_puf_fetch_ecc_public_key() function returns one of the following + status codes: + - MSS_SYS_SUCCESS + - MSS_SYS_NO_VALID_PUBLIC_KEY + - MSS_SYS_PRIVATE_ENVM_USER_DIGEST_MISMATCH + - MSS_SYS_MEM_ACCESS_ERROR + - MSS_SYS_SERVICE_NOT_LICENSED + - MSS_SYS_SERVICE_DISABLED_BY_FACTORY + - MSS_SYS_SERVICE_DISABLED_BY_USER + - MSS_SYS_UNEXPECTED_ERROR +*/ +uint8_t MSS_SYS_puf_fetch_ecc_public_key +( + uint8_t* p_puf_public_key +); + +/*-------------------------------------------------------------------------*//** + The MSS_SYS_puf_get_random_seed() function is used to generate a 256-bit true + random number seed using the SmartFusion2 SRAM-PUF. + + @param p_puf_seed + The p_puf_seed parameter is a pointer to the buffer where the PUF seed will + be stored on successful completion of the system service. + Note: This system service is only available on large SmartFusion2 devices + starting with the M2S060. + + @return + The MSS_SYS_puf_get_random_seed() function returns one of the following + status codes: + - MSS_SYS_SUCCESS + - MSS_SYS_PUF_ERROR_WHEN_CREATING + - MSS_SYS_MEM_ACCESS_ERROR + - MSS_SYS_SERVICE_NOT_LICENSED + - MSS_SYS_SERVICE_DISABLED_BY_FACTORY + - MSS_SYS_SERVICE_DISABLED_BY_USER + - MSS_SYS_UNEXPECTED_ERROR +*/ +uint8_t MSS_SYS_puf_get_random_seed +( + uint8_t* p_puf_seed +); + +/*-------------------------------------------------------------------------*//** + The MSS_SYS_ecc_point_multiplication() function provides access to the + SmartFusion2 System Controller�s Elliptic Curve Cryptography (ECC) point + multiplication system service. The MSS_SYS_ecc_point_multiplication() function + computes the point multiplication of a point P on the NIST-384 curve by a + scalar value d. The point multiplication results in point Q as follows: + d * P = Q + The points are defined by their x and y coordinates as follows: + P = (x1, y1) + Q = (x2, y2) + Each x and y coordinate and the scalar d are 384-bit long big-endian numbers. + Note: The point at infinity is specified using point x =0, y = 0. + Note: This system service is only available on large SmartFusion2 devices + starting with the M2S060. + + @param p_scalar_d + The p_scalar_d parameter is a pointer to a buffer containing the 384-bit + scalar d. The scalar d is 384-bit long meaning that p_scalar_d should point + to a 96 bytes buffer. + + @param p_point_p + The p_point_p parameter is a pointer to a buffer containing the (x1, y1) + coordinates of input point P. Each x and y coordinate is 384-bit long + meaning that p_point_p should point to a 96 bytes buffer. + + @param p_point_q + The p_point_q parameter is a pointer to a buffer where the (x2, y2) + coordinates of result Q will be stored. Each x and y coordinate is 384-bit + long meaning that p_point_q should point to a 96 bytes buffer. + + @return + The MSS_SYS_ecc_point_multiplication function returns one of the following + status codes: + - MSS_SYS_SUCCESS + - MSS_SYS_MEM_ACCESS_ERROR + - MSS_SYS_SERVICE_NOT_LICENSED + - MSS_SYS_SERVICE_DISABLED_BY_FACTORY + - MSS_SYS_SERVICE_DISABLED_BY_USER + - MSS_SYS_UNEXPECTED_ERROR +*/ +uint8_t MSS_SYS_ecc_point_multiplication +( + uint8_t* p_scalar_d, + uint8_t* p_point_p, + uint8_t* p_point_q +); + +/*-------------------------------------------------------------------------*//** + The MSS_SYS_ecc_point_addition() function provides access to the SmartFusion2 + System Controller�s Elliptic Curve Cryptography (ECC) point addition system + service. The MSS_SYS_ecc_point_addition() function computes the addition of + two points, P and Q, on the NIST P-384 curve. The point addition results in + point R as follows: + P + Q = R + The points are defined by their x and y coordinates as follows: + P = (x1, y1) + Q = (x2, y2) + R = (x3, y3) + Each x and y coordinate are 384-bit long big-endian numbers. + Note: The point at infinity is specified using point x =0, y = 0. + Note: This system service is only available on large SmartFusion2 devices + starting with the M2S060. + + @param p_point_p + The p_point_p parameter is a pointer to a buffer containing the (x1, y1) + coordinates of input point P. Each x and y coordinate is 384-bit long + meaning that p_point_p should point to a 96 bytes buffer. + + @param p_point_q + The p_point_q parameter is a pointer to a buffer containing the (x2, y2) + coordinates of input point Q. Each x and y coordinate is 384-bit long + meaning that p_point_q should point to a 96 bytes buffer. + + @param p_point_r + The p_point_r parameter is a pointer to a buffer where the (x3, y3) + coordinates of result R will be stored. Each x and y coordinate is 384-bit + long meaning that p_point_r should point to a 96 bytes buffer. + + @return + The MSS_SYS_ecc_point_addition() function returns one of the following + status codes: + - MSS_SYS_SUCCESS + - MSS_SYS_MEM_ACCESS_ERROR + - MSS_SYS_SERVICE_NOT_LICENSED + - MSS_SYS_SERVICE_DISABLED_BY_FACTORY + - MSS_SYS_SERVICE_DISABLED_BY_USER + - MSS_SYS_UNEXPECTED_ERROR +*/ +uint8_t MSS_SYS_ecc_point_addition +( + uint8_t* p_point_p, + uint8_t* p_point_q, + uint8_t* p_point_r +); + +/*-------------------------------------------------------------------------*//** + The MSS_SYS_ecc_get_base_point() function provides the value of the base + point G for NIST elliptic curve P-384. The value of the base point can then + be used to generate a public key by multiplying the base point G with a + private key using function MSS_SYS_ecc_point_multiplication(). + Note: This system service is only available on large SmartFusion2 devices + starting with the M2S060. + + @param p_point_p + The p_point_g parameter is a pointer to a buffer where the coordinate of + base point G (xG, yG) for curve P-384 will be stored. Each x and y + coordinate is 384-bit long meaning that p_point_g should point to a 96 + bytes buffer. + + @return + This function does not return a value. +*/ +void MSS_SYS_ecc_get_base_point +( + uint8_t* p_point_g +); + +/*-------------------------------------------------------------------------*//** + The MSS_SYS_start_clock_monitor() function enables clock monitoring based on + user configuration. The system controller will start monitoring the 50MHz + clock timing reference for four 1MHz clock cycle. The expected count is 200 + +/- tolerance. If the clock fall outside the tolerance limits, interrupt will + be generated and system controller will send clock monitor tamper detect + event through COMBLK. MSS should inform to the application about clock + monitoring tamper detect event though call back function. + NOTE: Do not enable both start clock monitoring and stop clock monitoring at + the same time. + Note: This system service is only available on large SmartFusion2 devices + starting with the M2S060. + + @param + This function does not take any parameters + + @return + The MSS_SYS_start_clock_monitor() function returns one of the following + status codes: + � MSS_SYS_SUCCESS + � MSS_SYS_UNEXPECTED_ERROR +*/ +uint8_t MSS_SYS_start_clock_monitor +( + void +); + +/*-------------------------------------------------------------------------*//** + The MSS_SYS_stop_clock_monitor() function is used to stop the clock monitoring. + System controller will disable 50 MHZ timing clock monitoring and clock + monitor tamper detect interrupt. + NOTE: Do not enable both start clock monitoring and stop clock monitoring at + the same time. + NOTE: This system service is only available on large SmartFusion2 devices + starting with the M2S060. + + @param + This function does not take any parameters + + @return + The MSS_SYS_stop_clock_monitor() function returns one of the following + status codes: + � MSS_SYS_SUCCESS + � MSS_SYS_UNEXPECTED_ERROR +*/ +uint8_t MSS_SYS_stop_clock_monitor +( + void +); + +/*-------------------------------------------------------------------------*//** + The MSS_SYS_enable_puf_power_down() function is used to instruct the system + controller to power down the PUF after each of the following operations: + � key fetch + � key creation + � key import + � random seed generation + Powering down the PUF after these operations is the default PUF behaviour. + Note: This system service is only available on large SmartFusion2 devices + starting with the M2S060. + + @param + This function does not take any parameters. + + @return + The MSS_SYS_enable_puf_power_down() function returns one of the following + status codes: + � MSS_SYS_SUCCESS + � MSS_SYS_UNEXPECTED_ERROR +*/ +uint8_t MSS_SYS_enable_puf_power_down +( + void +); + +/*-------------------------------------------------------------------------*//** + The MSS_SYS_disable_puf_power_down() function is used to retain PUF power + after the following operations: + � key fetch + � key creation + � key import + � random seed generation + Note: This system service is only available on large SmartFusion2 devices + starting with the M2S060. + + @param + This function does not take any parameters + + @return + The MSS_SYS_disable_puf_power_down() function returns one of the following + status codes: + � MSS_SYS_SUCCESS + � MSS_SYS_UNEXPECTED_ERROR +*/ +uint8_t MSS_SYS_disable_puf_power_down +( + void +); + +/*-------------------------------------------------------------------------*//** + The MSS_SYS_clear_lock_parity() function is used to clear the previously set + Lock Parity tamper flag. System controller will set this flag on detection of + parity error on internal lock data. To clear lock parity flag, use tamper + control service with bit 4 of Option set to 1, then the LOCKPARITY tamper flag + is cleared provided the hardware conditions are no longer present to raise + this flag. + Note: This system service is only available on large SmartFusion2 devices + starting with the M2S060. + + @param + This function does not take any parameters + + @return + The MSS_SYS_clear_lock_parity() function returns one of the following + status codes: + � MSS_SYS_SUCCESS + � MSS_SYS_UNEXPECTED_ERROR +*/ +uint8_t MSS_SYS_clear_lock_parity +( + void +); + +/*-------------------------------------------------------------------------*//** + The MSS_SYS_clear_mesh_short() function is used to clear the previously mesh + short tamper flag. System Controller monitors the security flash array for + invasive tampering using an active mesh. This mesh is driven by LFSR and the + return value is monitored for discrepancies against the expected value generated + by the LFSR. When a tamper event is detected the MESHSHORT tamper flag is set, + generating a tamper interrupt. To clear mesh short tamper flag, use tamper + control service with bit 5 of Options set to 1. The MESHSHORT tamper flag is + cleared provided the hardware conditions are no longer present to raise this + flag. + Note: This system service is only available on large SmartFusion2 devices + starting with the M2S060. + + @param + This function does not take any parameters + + @return + The MSS_SYS_clear_mesh_short() function returns one of the following + status codes: + � MSS_SYS_SUCCESS + � MSS_SYS_UNEXPECTED_ERROR +*/ +uint8_t MSS_SYS_clear_mesh_short +( + void +); + +/*-------------------------------------------------------------------------*//** + The IAP Service requests the System Controller to reprogram the device using + a bitstream already programmed into MSS SPI 0. The IAP Service is initiated by + a call to MSS_SYS_initiate_IAP(). The IAP Service can: + - authenticate a programming bitstream + - program a bitstream + - verify that a programming bitstream has been correctly programmed + + @param mode + The mode parameter specifies IAP service to perform. It can be one of: + - MSS_SYS_PROG_AUTHENTICATE + - MSS_SYS_PROG_PROGRAM + - MSS_SYS_PROG_VERIFY + + @param bitstream_spi_addr + The bitstream_spi_addr parameter specifies the address of the programming + bitstream within the SPI flash connected to MSS SPI 0. + + @return + The MSS_SYS_initiate_IAP function will receive one of the following status + codes: + - MSS_SYS_SUCCESS + - MSS_SYS_CHAINING_MISMATCH + - MSS_SYS_UNEXPECTED_DATA_RECEIVED + - MSS_SYS_INVALID_ENCRYPTION_KEY + - MSS_SYS_INVALID_COMPONENT_HEADER + - MSS_SYS_BACK_LEVEL_NOT_SATISFIED + - MSS_SYS_DSN_BINDING_MISMATCH + - MSS_SYS_ILLEGAL_COMPONENT_SEQUENCE + - MSS_SYS_INSUFFICIENT_DEV_CAPABILITIES + - MSS_SYS_INCORRECT_DEVICE_ID + - MSS_SYS_UNSUPPORTED_BITSTREAM_PROT_VER + - MSS_SYS_VERIFY_NOT_PERMITTED_ON_BITSTR + - MSS_SYS_INVALID_DEVICE_CERTIFICATE + - MSS_SYS_ABORT + - MSS_SYS_NVM_VERIFY_FAILED + - MSS_SYS_DEVICE_SECURITY_PROTECTED + - MSS_SYS_PROGRAMMING_MODE_NOT_ENABLED + - MSS_SYS_ENVM_PROGRAMMING_OPERATION_FAIL + - MSS_SYS_ENVM_VERIFY_OPERATION_FAIL + - MSS_SYS_ACCESS_ERROR + - MSS_SYS_PUF_ACCESS_ERROR + - MSS_SYS_BAD_COMPONENT + - MSS_SYS_SERVICE_DISABLED_BY_USER +*/ +uint8_t MSS_SYS_initiate_IAP +( + uint8_t mode, + uint32_t bitstream_spi_addr +); + +#ifdef __cplusplus +} +#endif + +#endif /* __MSS_SYS_SERVICES_H_ */ diff --git a/bsp/smartfusion2/libraries/mss_uart/mss_uart.c b/bsp/smartfusion2/libraries/mss_uart/mss_uart.c new file mode 100644 index 0000000000..2d04985fbc --- /dev/null +++ b/bsp/smartfusion2/libraries/mss_uart/mss_uart.c @@ -0,0 +1,1762 @@ +/******************************************************************************* + * (c) Copyright 2011-2013 Microsemi SoC Products Group. All rights reserved. + * + * SmartFusion2 Microcontroller Subsystem MMUART bare metal software driver + * implementation. + * + * SVN $Revision: 5610 $ + * SVN $Date: 2013-04-05 18:49:30 +0530 (Fri, 05 Apr 2013) $ + */ +#include "mss_uart.h" +#include "mss_uart_regs.h" +#include "../../CMSIS/mss_assert.h" +#include "../../CMSIS/hw_reg_io.h" +#include "../../CMSIS/system_m2sxxx.h" + +#ifdef __cplusplus +extern "C" { +#endif + +/******************************************************************************* + * Defines + */ +#define TX_COMPLETE 0u +#define TX_FIFO_SIZE 16u + +#define FCR_TRIG_LEVEL_MASK 0xC0u + +#define IIRF_MASK 0x0Fu + +#define INVALID_INTERRUPT 0u +#define INVALID_IRQ_HANDLER ((mss_uart_irq_handler_t) 0) +#define NULL_HANDLER ((mss_uart_irq_handler_t) 0) + +#define MSS_UART_DATA_READY ((uint8_t) 0x01) + +#define SYNC_ASYNC_MODE_MASK (0x7u) + +/******************************************************************************* + * Possible values for Interrupt Identification Register Field. + */ +#define IIRF_MODEM_STATUS 0x00u +#define IIRF_THRE 0x02u +#define IIRF_MMI 0x03u +#define IIRF_RX_DATA 0x04u +#define IIRF_RX_LINE_STATUS 0x06u +#define IIRF_DATA_TIMEOUT 0x0Cu + +/******************************************************************************* + * Receiver error status mask. + */ +#define STATUS_ERROR_MASK ( MSS_UART_OVERUN_ERROR | MSS_UART_PARITY_ERROR | \ + MSS_UART_FRAMING_ERROR | MSS_UART_BREAK_ERROR | \ + MSS_UART_FIFO_ERROR) + +/******************************************************************************* + * Cortex-M3 interrupt handler functions implemented as part of the MSS UART + * driver. + */ +#if defined(__GNUC__) +__attribute__((__interrupt__)) void UART0_IRQHandler(void); +#else +void UART0_IRQHandler(void); +#endif + +#if defined(__GNUC__) +__attribute__((__interrupt__)) void UART1_IRQHandler(void); +#else +void UART1_IRQHandler(void); +#endif + +/******************************************************************************* + * Local functions. + */ +static void global_init(mss_uart_instance_t * this_uart, uint32_t baud_rate, + uint8_t line_config); +static void MSS_UART_isr(mss_uart_instance_t * this_uart); +static void default_tx_handler(mss_uart_instance_t * this_uart); + +static void config_baud_divisors +( + mss_uart_instance_t * this_uart, + uint32_t baudrate +); + +/******************************************************************************* + * Instance definitions + */ +mss_uart_instance_t g_mss_uart0; +mss_uart_instance_t g_mss_uart1; + + +/******************************************************************************* + * Public Functions + *******************************************************************************/ +/***************************************************************************//** + * See mss_uart.h for details of how to use this function. + */ +void +MSS_UART_init +( + mss_uart_instance_t* this_uart, + uint32_t baud_rate, + uint8_t line_config +) +{ + /* The driver expects g_mss_uart0 and g_mss_uart1 to be the only + * mss_uart_instance_t instances used to identify UART0 and UART1. */ + ASSERT((this_uart == &g_mss_uart0) || (this_uart == &g_mss_uart1)); + + /* Perform generic initialization */ + global_init(this_uart, baud_rate, line_config); + + /* Disable LIN mode */ + clear_bit_reg8(&this_uart->hw_reg->MM0, ELIN); + + /* Disable IrDA mode */ + clear_bit_reg8(&this_uart->hw_reg->MM1, EIRD); + + /* Disable SmartCard Mode */ + clear_bit_reg8(&this_uart->hw_reg->MM2, EERR); + + /* set default tx handler for automated TX using interrupt in USART mode */ + this_uart->tx_handler = default_tx_handler; +} + +/***************************************************************************//** + * See mss_uart.h for details of how to use this function. + */ +void MSS_UART_lin_init +( + mss_uart_instance_t* this_uart, + uint32_t baud_rate, + uint8_t line_config +) +{ + /* The driver expects g_mss_uart0 and g_mss_uart1 to be the only + * mss_uart_instance_t instances used to identify UART0 and UART1. */ + ASSERT((this_uart == &g_mss_uart0) || (this_uart == &g_mss_uart1)); + + /* Perform generic initialization */ + global_init(this_uart, baud_rate, line_config); + + /* Enable LIN mode */ + set_bit_reg8(&this_uart->hw_reg->MM0, ELIN); + + /* Disable IrDA mode */ + clear_bit_reg8(&this_uart->hw_reg->MM1, EIRD); + + /* Disable SmartCard Mode */ + clear_bit_reg8(&this_uart->hw_reg->MM2, EERR); +} + +/***************************************************************************//** + * See mss_uart.h for details of how to use this function. + */ +void +MSS_UART_irda_init +( + mss_uart_instance_t* this_uart, + uint32_t baud_rate, + uint8_t line_config, + mss_uart_rzi_polarity_t rxpol, + mss_uart_rzi_polarity_t txpol, + mss_uart_rzi_pulsewidth_t pw +) +{ + /* The driver expects g_mss_uart0 and g_mss_uart1 to be the only + * mss_uart_instance_t instances used to identify UART0 and UART1. */ + ASSERT((this_uart == &g_mss_uart0) || (this_uart == &g_mss_uart1)); + + /* Perform generic initialization */ + global_init(this_uart, baud_rate, line_config); + + /* Enable LIN mode */ + clear_bit_reg8(&this_uart->hw_reg->MM0, ELIN); + + /* Disable IrDA mode */ + set_bit_reg8(&this_uart->hw_reg->MM1, EIRD); + ((rxpol == MSS_UART_ACTIVE_LOW) ? clear_bit_reg8(&this_uart->hw_reg->MM1,EIRX) : + set_bit_reg8(&this_uart->hw_reg->MM1,EIRX)); + + ((txpol == MSS_UART_ACTIVE_LOW) ? clear_bit_reg8(&this_uart->hw_reg->MM1,EITX) : + set_bit_reg8(&this_uart->hw_reg->MM1,EITX)); + + ((pw == MSS_UART_3_BY_16) ? clear_bit_reg8(&this_uart->hw_reg->MM1,EITP) : + set_bit_reg8(&this_uart->hw_reg->MM1,EITP)); + /* Disable SmartCard Mode */ + clear_bit_reg8(&this_uart->hw_reg->MM2, EERR); +} + +/***************************************************************************//** + * See mss_uart.h for details of how to use this function. + */ +void +MSS_UART_smartcard_init +( + mss_uart_instance_t* this_uart, + uint32_t baud_rate, + uint8_t line_config +) +{ + /* The driver expects g_mss_uart0 and g_mss_uart1 to be the only + * mss_uart_instance_t instances used to identify UART0 and UART1. */ + ASSERT((this_uart == &g_mss_uart0) || (this_uart == &g_mss_uart1)); + + /* Perform generic initialization */ + global_init(this_uart, baud_rate, line_config); + + /* Disable LIN mode */ + clear_bit_reg8(&this_uart->hw_reg->MM0, ELIN); + + /* Disable IrDA mode */ + clear_bit_reg8(&this_uart->hw_reg->MM1, EIRD); + + /* Enable SmartCard Mode : Only when data is 8-bit and 2 stop bits*/ + if( ( MSS_UART_DATA_8_BITS | MSS_UART_TWO_STOP_BITS) == + (line_config & (MSS_UART_DATA_8_BITS | MSS_UART_TWO_STOP_BITS))) + { + set_bit_reg8(&this_uart->hw_reg->MM2, EERR); + /* Enable single wire half-duplex mode */ + set_bit_reg8(&this_uart->hw_reg->MM2,ESWM); + } +} + +/***************************************************************************//** + * See mss_uart.h for details of how to use this function. + */ +void +MSS_UART_polled_tx +( + mss_uart_instance_t * this_uart, + const uint8_t * pbuff, + uint32_t tx_size +) +{ + uint32_t char_idx = 0u; + uint32_t size_sent; + uint8_t status; + + ASSERT((this_uart == &g_mss_uart0) || (this_uart == &g_mss_uart1)); + ASSERT(pbuff != ( (uint8_t *)0)); + ASSERT(tx_size > 0u); + + if(((this_uart == &g_mss_uart0) || (this_uart == &g_mss_uart1)) && + (pbuff != ((uint8_t *)0)) && (tx_size > 0u)) + { + /* Remain in this loop until the entire input buffer + * has been transferred to the UART. + */ + do { + /* Read the Line Status Register and update the sticky record */ + status = this_uart->hw_reg->LSR; + this_uart->status |= status; + + /* Check if TX FIFO is empty. */ + if(status & MSS_UART_THRE) + { + uint32_t fill_size = TX_FIFO_SIZE; + + /* Calculate the number of bytes to transmit. */ + if(tx_size < TX_FIFO_SIZE) + { + fill_size = tx_size; + } + + /* Fill the TX FIFO with the calculated the number of bytes. */ + for(size_sent = 0u; size_sent < fill_size; ++size_sent) + { + /* Send next character in the buffer. */ + this_uart->hw_reg->THR = pbuff[char_idx]; + char_idx++; + } + + /* Calculate the number of untransmitted bytes remaining. */ + tx_size -= size_sent; + } + } while(tx_size); + } +} + +/***************************************************************************//** + * See mss_uart.h for details of how to use this function. + */ +void +MSS_UART_polled_tx_string +( + mss_uart_instance_t * this_uart, + const uint8_t * p_sz_string +) +{ + uint32_t char_idx = 0u; + uint32_t fill_size; + uint8_t data_byte; + uint8_t status; + + ASSERT((this_uart == &g_mss_uart0) || (this_uart == &g_mss_uart1)); + ASSERT(p_sz_string != ((uint8_t *)0)); + + if(((this_uart == &g_mss_uart0) || (this_uart == &g_mss_uart1)) && + (p_sz_string != ((uint8_t *)0))) + { + /* Get the first data byte from the input buffer */ + data_byte = p_sz_string[char_idx]; + + /* First check for the NULL terminator byte. + * Then remain in this loop until the entire string in the input buffer + * has been transferred to the UART. + */ + while(0u != data_byte) + { + /* Wait until TX FIFO is empty. */ + do { + status = this_uart->hw_reg->LSR; + this_uart->status |= status; + } while (0u == (status & MSS_UART_THRE)); + + /* Send bytes from the input buffer until the TX FIFO is full + * or we reach the NULL terminator byte. + */ + fill_size = 0u; + while((0u != data_byte) && (fill_size < TX_FIFO_SIZE)) + { + /* Send the data byte */ + this_uart->hw_reg->THR = data_byte; + ++fill_size; + char_idx++; + /* Get the next data byte from the input buffer */ + data_byte = p_sz_string[char_idx]; + } + } + } +} + +/***************************************************************************//** + * See mss_uart.h for details of how to use this function. + */ +void +MSS_UART_irq_tx +( + mss_uart_instance_t * this_uart, + const uint8_t * pbuff, + uint32_t tx_size +) +{ + ASSERT((this_uart == &g_mss_uart0) || (this_uart == &g_mss_uart1)); + ASSERT(pbuff != ((uint8_t *)0)); + ASSERT(tx_size > 0u); + + if((tx_size > 0u) && ( pbuff != ((uint8_t *)0)) && + ((this_uart == &g_mss_uart0) || (this_uart == &g_mss_uart1))) + { + /*Initialise the transmit info for the UART instance with the arguments.*/ + this_uart->tx_buffer = pbuff; + this_uart->tx_buff_size = tx_size; + this_uart->tx_idx = (uint16_t)0; + + /* Clear any previously pended interrupts */ + NVIC_ClearPendingIRQ(this_uart->irqn); + + /* assign default handler for data transfer */ + this_uart->tx_handler = default_tx_handler; + + /* enables TX interrupt */ + set_bit_reg8(&this_uart->hw_reg->IER,ETBEI); + + /* Enable UART instance interrupt in Cortex-M3 NVIC. */ + NVIC_EnableIRQ(this_uart->irqn); + } +} + +/***************************************************************************//** + * See mss_uart.h for details of how to use this function. + */ +int8_t +MSS_UART_tx_complete +( + mss_uart_instance_t * this_uart +) +{ + int8_t ret_value = 0; + uint8_t status = 0u; + + ASSERT((this_uart == &g_mss_uart0) || (this_uart == &g_mss_uart1)); + + if((this_uart == &g_mss_uart0) || (this_uart == &g_mss_uart1)) + { + /* Read the Line Status Register and update the sticky record. */ + status = this_uart->hw_reg->LSR; + this_uart->status |= status; + + if((TX_COMPLETE == this_uart->tx_buff_size) && + ((status & MSS_UART_TEMT) != 0u)) + { + ret_value = (int8_t)1; + } + } + return ret_value; +} + + +/***************************************************************************//** + * See mss_uart.h for details of how to use this function. + */ +size_t +MSS_UART_get_rx +( + mss_uart_instance_t * this_uart, + uint8_t * rx_buff, + size_t buff_size +) +{ + size_t rx_size = 0u; + uint8_t status = 0u; + + ASSERT((this_uart == &g_mss_uart0) || (this_uart == &g_mss_uart1)); + ASSERT(rx_buff != ((uint8_t *)0)); + ASSERT(buff_size > 0u); + + if(((this_uart == &g_mss_uart0) || (this_uart == &g_mss_uart1)) && + (rx_buff != ((uint8_t *)0)) && (buff_size > 0u)) + { + status = this_uart->hw_reg->LSR; + this_uart->status |= status; + + while(((status & MSS_UART_DATA_READY) != 0u) && + (rx_size < buff_size)) + { + rx_buff[rx_size] = this_uart->hw_reg->RBR; + ++rx_size; + status = this_uart->hw_reg->LSR; + this_uart->status |= status; + } + } + return rx_size; +} +/***************************************************************************//** + * See mss_uart.h for details of how to use this function. + */ +void +MSS_UART_enable_irq +( + mss_uart_instance_t * this_uart, + mss_uart_irq_t irq_mask +) +{ + ASSERT((this_uart == &g_mss_uart0) || (this_uart == &g_mss_uart1)); + ASSERT(MSS_UART_INVALID_IRQ > irq_mask); + + if(((this_uart == &g_mss_uart0) || (this_uart == &g_mss_uart1)) && + (MSS_UART_INVALID_IRQ > irq_mask)) + { + /* Clear any previously pended interrupts */ + NVIC_ClearPendingIRQ(this_uart->irqn); + + /* irq_mask encoding: 1- enable + * bit 0 - Receive Data Available Interrupt + * bit 1 - Transmitter Holding Register Empty Interrupt + * bit 2 - Receiver Line Status Interrupt + * bit 3 - Modem Status Interrupt + */ + this_uart->hw_reg->IER |= (uint8_t)irq_mask & IIRF_MASK; + + /* + * bit 4 - Receiver time-out interrupt + * bit 5 - NACK / ERR signal interrupt + * bit 6 - PID parity error interrupt + * bit 7 - LIN break detection interrupt + * bit 8 - LIN Sync detection interrupt + */ + this_uart->hw_reg->IEM |= (uint8_t)(((uint32_t)irq_mask & ~((uint32_t)IIRF_MASK)) >> 4u); + + /* Enable UART instance interrupt in Cortex-M3 NVIC. */ + NVIC_EnableIRQ(this_uart->irqn); + } +} + +/***************************************************************************//** + * See mss_uart.h for details of how to use this function. + */ +void +MSS_UART_disable_irq +( + mss_uart_instance_t * this_uart, + mss_uart_irq_t irq_mask +) +{ + ASSERT((this_uart == &g_mss_uart0) || (this_uart == &g_mss_uart1)); + + if((this_uart == &g_mss_uart0) || (this_uart == &g_mss_uart1)) + { + /* irq_mask encoding: 1 - disable + * bit 0 - Receive Data Available Interrupt + * bit 1 - Transmitter Holding Register Empty Interrupt + * bit 2 - Receiver Line Status Interrupt + * bit 3 - Modem Status Interrupt + */ + this_uart->hw_reg->IER &= ((uint8_t)(~((uint32_t)irq_mask & (uint32_t)IIRF_MASK))); + + /* + * bit 4 - Receiver time-out interrupt + * bit 5 - NACK / ERR signal interrupt + * bit 6 - PID parity error interrupt + * bit 7 - LIN break detection interrupt + * bit 8 - LIN Sync detection interrupt + */ + this_uart->hw_reg->IEM |= (uint8_t)(~(((uint32_t)irq_mask & ~((uint32_t)IIRF_MASK)) >> 8u)); + + /* Clear any previously pended interrupts */ + NVIC_ClearPendingIRQ(this_uart->irqn); + + if(irq_mask == IIRF_MASK) + { + /* Disable UART instance interrupt in Cortex-M3 NVIC. */ + NVIC_DisableIRQ(this_uart->irqn); + + } + } +} + +/***************************************************************************//** + * See mss_uart.h for details of how to use this function. + */ +void +MSS_UART_set_rx_handler +( + mss_uart_instance_t * this_uart, + mss_uart_irq_handler_t handler, + mss_uart_rx_trig_level_t trigger_level +) +{ + ASSERT((this_uart == &g_mss_uart0) || (this_uart == &g_mss_uart1)); + ASSERT(handler != INVALID_IRQ_HANDLER ); + ASSERT(trigger_level < MSS_UART_FIFO_INVALID_TRIG_LEVEL); + + if(((this_uart == &g_mss_uart0) || (this_uart == &g_mss_uart1)) && + (handler != INVALID_IRQ_HANDLER) && + (trigger_level < MSS_UART_FIFO_INVALID_TRIG_LEVEL)) + { + this_uart->rx_handler = handler; + + /* Set the receive interrupt trigger level. */ + this_uart->hw_reg->FCR = (this_uart->hw_reg->FCR & + (uint8_t)(~((uint8_t)FCR_TRIG_LEVEL_MASK))) | + (uint8_t)trigger_level; + /* Clear any previously pended interrupts */ + NVIC_ClearPendingIRQ(this_uart->irqn); + + /* Enable receive interrupt. */ + set_bit_reg8(&this_uart->hw_reg->IER,ERBFI); + + /* Enable UART instance interrupt in Cortex-M3 NVIC. */ + NVIC_EnableIRQ(this_uart->irqn); + } +} + +/***************************************************************************//** + * See mss_uart.h for details of how to use this function. + */ +void +MSS_UART_set_loopback +( + mss_uart_instance_t * this_uart, + mss_uart_loopback_t loopback +) +{ + ASSERT((this_uart == &g_mss_uart0) || (this_uart == &g_mss_uart1)); + ASSERT(MSS_UART_INVALID_LOOPBACK > loopback); + + if(((this_uart == &g_mss_uart0) || (this_uart == &g_mss_uart1)) || + (MSS_UART_INVALID_LOOPBACK > loopback)) + { + switch(loopback) + { + case MSS_UART_LOCAL_LOOPBACK_OFF: + /* Disable local loopback */ + clear_bit_reg8(&this_uart->hw_reg->MCR,LOOP); + break; + + case MSS_UART_LOCAL_LOOPBACK_ON: + /* Enable local loopback */ + set_bit_reg8(&this_uart->hw_reg->MCR,LOOP); + break; + + case MSS_UART_REMOTE_LOOPBACK_OFF: + case MSS_UART_AUTO_ECHO_OFF: + /* Disable remote loopback & automatic echo*/ + this_uart->hw_reg->MCR &= ~RLOOP_MASK; + break; + + case MSS_UART_REMOTE_LOOPBACK_ON: + /* Enable remote loopback */ + this_uart->hw_reg->MCR |= (1u << RLOOP); + break; + + case MSS_UART_AUTO_ECHO_ON: + /* Enable automatic echo */ + this_uart->hw_reg->MCR |= (1u << ECHO); + break; + + case MSS_UART_INVALID_LOOPBACK: + /* Fall through to default. */ + default: + ASSERT(0); + break; + } + } +} + +/***************************************************************************//** + * UART0 interrupt service routine. + * UART0_IRQHandler is included within the Cortex-M3 vector table as part of the + * Fusion 2 CMSIS. + */ +#if defined(__GNUC__) +__attribute__((__interrupt__)) void UART0_IRQHandler(void) +#else +void UART0_IRQHandler(void) +#endif +{ + MSS_UART_isr(&g_mss_uart0); +} + +/***************************************************************************//** + * UART1 interrupt service routine. + * UART2_IRQHandler is included within the Cortex-M3 vector table as part of the + * Fusion 2 CMSIS. + */ +#if defined(__GNUC__) +__attribute__((__interrupt__)) void UART1_IRQHandler(void) +#else +void UART1_IRQHandler(void) +#endif +{ + MSS_UART_isr(&g_mss_uart1); +} + +/***************************************************************************//** + * See mss_uart.h for details of how to use this function. + */ +void +MSS_UART_set_rxstatus_handler +( + mss_uart_instance_t * this_uart, + mss_uart_irq_handler_t handler +) +{ + ASSERT((this_uart == &g_mss_uart0) || (this_uart == &g_mss_uart1)); + ASSERT(handler != INVALID_IRQ_HANDLER); + + if(((this_uart == &g_mss_uart0) || (this_uart == &g_mss_uart1)) && + (handler != INVALID_IRQ_HANDLER)) + { + this_uart->linests_handler = handler; + + /* Clear any previously pended interrupts */ + NVIC_ClearPendingIRQ(this_uart->irqn); + + /* Enable receiver line status interrupt. */ + set_bit_reg8(&this_uart->hw_reg->IER,ELSI); + + /* Enable UART instance interrupt in Cortex-M3 NVIC. */ + NVIC_EnableIRQ(this_uart->irqn); + } +} + +/***************************************************************************//** + * See mss_uart.h for details of how to use this function. + */ +void +MSS_UART_set_tx_handler +( + mss_uart_instance_t * this_uart, + mss_uart_irq_handler_t handler +) +{ + ASSERT((this_uart == &g_mss_uart0) || (this_uart == &g_mss_uart1)); + ASSERT(handler != INVALID_IRQ_HANDLER); + + if(((this_uart == &g_mss_uart0) || (this_uart == &g_mss_uart1)) && + (handler != INVALID_IRQ_HANDLER)) + { + this_uart->tx_handler = handler; + + /* Make TX buffer info invalid */ + this_uart->tx_buffer = (const uint8_t *)0; + this_uart->tx_buff_size = 0u; + + /* Clear any previously pended interrupts */ + NVIC_ClearPendingIRQ(this_uart->irqn); + + /* Enable transmitter holding register Empty interrupt. */ + set_bit_reg8(&this_uart->hw_reg->IER,ETBEI); + + /* Enable UART instance interrupt in Cortex-M3 NVIC. */ + NVIC_EnableIRQ(this_uart->irqn); + } +} + +/***************************************************************************//** + * See mss_uart.h for details of how to use this function. + */ +void +MSS_UART_set_modemstatus_handler +( + mss_uart_instance_t * this_uart, + mss_uart_irq_handler_t handler +) +{ + ASSERT((this_uart == &g_mss_uart0) || (this_uart == &g_mss_uart1)); + ASSERT(handler != INVALID_IRQ_HANDLER); + + if(((this_uart == &g_mss_uart0) || (this_uart == &g_mss_uart1)) && + (handler != INVALID_IRQ_HANDLER)) + { + this_uart->modemsts_handler = handler; + + /* Clear any previously pended interrupts */ + NVIC_ClearPendingIRQ(this_uart->irqn); + + /* Enable modem status interrupt. */ + set_bit_reg8(&this_uart->hw_reg->IER,EDSSI); + + /* Enable UART instance interrupt in Cortex-M3 NVIC. */ + NVIC_EnableIRQ(this_uart->irqn); + } +} + +/***************************************************************************//** + * See mss_uart.h for details of how to use this function. + */ +size_t +MSS_UART_fill_tx_fifo +( + mss_uart_instance_t * this_uart, + const uint8_t * tx_buffer, + size_t tx_size +) +{ + uint8_t status = 0u; + size_t size_sent = 0u; + + ASSERT((this_uart == &g_mss_uart0) || (this_uart == &g_mss_uart1)); + ASSERT(tx_buffer != ( (uint8_t *)0)); + ASSERT(tx_size > 0); + + /* Fill the UART's Tx FIFO until the FIFO is full or the complete input + * buffer has been written. */ + if(((this_uart == &g_mss_uart0) || (this_uart == &g_mss_uart1)) && + (tx_buffer != ((uint8_t *)0)) && + (tx_size > 0u)) + { + status = this_uart->hw_reg->LSR; + this_uart->status |= status; + + if(status & MSS_UART_THRE) + { + uint32_t fill_size = TX_FIFO_SIZE; + + if(tx_size < TX_FIFO_SIZE) + { + fill_size = tx_size; + } + /* Fill up FIFO */ + for(size_sent = 0u; size_sent < fill_size; ++size_sent) + { + + /* Send next character in the buffer. */ + this_uart->hw_reg->THR = tx_buffer[size_sent]; + } + } + } + return size_sent; +} + +/***************************************************************************//** + * See mss_uart.h for details of how to use this function. + */ +uint8_t +MSS_UART_get_rx_status +( + mss_uart_instance_t * this_uart +) +{ + uint8_t status = MSS_UART_INVALID_PARAM; + + ASSERT((this_uart == &g_mss_uart0) || (this_uart == &g_mss_uart1)); + + if((this_uart == &g_mss_uart0) || (this_uart == &g_mss_uart1)) + { + /* + * Extract UART receive error status. + * Bit 1 - Overflow error status + * Bit 2 - Parity error status + * Bit 3 - Frame error status + * Bit 4 - Break interrupt indicator + * Bit 7 - FIFO data error status + */ + this_uart->status |= (this_uart->hw_reg->LSR); + status = (this_uart->status & STATUS_ERROR_MASK); + /* Clear the sticky status after reading */ + this_uart->status = 0u; + } + return status; +} + +/***************************************************************************//** + * See mss_uart.h for details of how to use this function. + */ +uint8_t +MSS_UART_get_modem_status +( + mss_uart_instance_t * this_uart +) +{ + uint8_t status = MSS_UART_INVALID_PARAM; + + ASSERT((this_uart == &g_mss_uart0) || (this_uart == &g_mss_uart1)); + + if((this_uart == &g_mss_uart0) || (this_uart == &g_mss_uart1)) + { + /* + * Extract UART modem status and place in lower bits of "status". + * Bit 0 - Delta Clear to Send Indicator + * Bit 1 - Delta Clear to Receive Indicator + * Bit 2 - Trailing edge of Ring Indicator detector + * Bit 3 - Delta Data Carrier Detect indicator + * Bit 4 - Clear To Send + * Bit 5 - Data Set Ready + * Bit 6 - Ring Indicator + * Bit 7 - Data Carrier Detect + */ + status = this_uart->hw_reg->MSR; + } + return status; +} + +/***************************************************************************//** + * MSS_UART_get_tx_status. + * See mss_uart.h for details of how to use this function. + */ +uint8_t +MSS_UART_get_tx_status +( + mss_uart_instance_t * this_uart +) +{ + uint8_t status = MSS_UART_TX_BUSY; + + ASSERT((this_uart == &g_mss_uart0) || (this_uart == &g_mss_uart1)); + + if((this_uart == &g_mss_uart0) || (this_uart == &g_mss_uart1)) + { + /* Read the Line Status Register and update the sticky record. */ + status = this_uart->hw_reg->LSR; + this_uart->status |= status; + /* + * Extract the transmit status bits from the UART's Line Status Register. + * Bit 5 - Transmitter Holding Register/FIFO Empty (THRE) status. (If = 1, TX FIFO is empty) + * Bit 6 - Transmitter Empty (TEMT) status. (If = 1, both TX FIFO and shift register are empty) + */ + status &= (MSS_UART_THRE | MSS_UART_TEMT); + } + return status; +} + +/***************************************************************************//** + * See mss_uart.h for details of how to use this function. + */ +void +MSS_UART_set_break +( + mss_uart_instance_t * this_uart +) +{ + ASSERT((this_uart == &g_mss_uart0) || (this_uart == &g_mss_uart1)); + if((this_uart == &g_mss_uart0) || (this_uart == &g_mss_uart1)) + { + /* set break charecter on Tx line */ + set_bit_reg8(&this_uart->hw_reg->LCR,SB); + } +} + +/***************************************************************************//** + * See mss_uart.h for details of how to use this function. + */ +void +MSS_UART_clear_break +( + mss_uart_instance_t * this_uart +) +{ + ASSERT((this_uart == &g_mss_uart0) || (this_uart == &g_mss_uart1)); + if((this_uart == &g_mss_uart0) || (this_uart == &g_mss_uart1)) + { + /* remove break charecter from Tx line */ + clear_bit_reg8(&this_uart->hw_reg->LCR,SB); + } +} + +/***************************************************************************//** + * See mss_uart.h for details of how to use this function. + */ +void +MSS_UART_set_pidpei_handler +( + mss_uart_instance_t * this_uart, + mss_uart_irq_handler_t handler +) +{ + ASSERT((this_uart == &g_mss_uart0) || (this_uart == &g_mss_uart1)); + ASSERT(handler != INVALID_IRQ_HANDLER); + + if(((this_uart == &g_mss_uart0) || (this_uart == &g_mss_uart1)) && + (handler != INVALID_IRQ_HANDLER)) + { + this_uart->pid_pei_handler = handler; + + /* Clear any previously pended interrupts */ + NVIC_ClearPendingIRQ( this_uart->irqn ); + + /* Enable PID parity error interrupt. */ + set_bit_reg8(&this_uart->hw_reg->IEM,EPID_PEI); + + /* Enable UART instance interrupt in Cortex-M3 NVIC. */ + NVIC_EnableIRQ(this_uart->irqn); + } +} + +/***************************************************************************//** + * See mss_uart.h for details of how to use this function. + */ +void +MSS_UART_set_linbreak_handler +( + mss_uart_instance_t * this_uart, + mss_uart_irq_handler_t handler +) +{ + ASSERT((this_uart == &g_mss_uart0) || (this_uart == &g_mss_uart1)); + ASSERT(handler != INVALID_IRQ_HANDLER); + + if(((this_uart == &g_mss_uart0) || (this_uart == &g_mss_uart1)) && + (handler != INVALID_IRQ_HANDLER)) + { + this_uart->break_handler = handler; + + /* Clear any previously pended interrupts */ + NVIC_ClearPendingIRQ( this_uart->irqn ); + + /* Enable LIN break detection interrupt. */ + set_bit_reg8(&this_uart->hw_reg->IEM,ELINBI); + + /* Enable UART instance interrupt in Cortex-M3 NVIC. */ + NVIC_EnableIRQ(this_uart->irqn); + } +} + +/***************************************************************************//** + * See mss_uart.h for details of how to use this function. + */ +void +MSS_UART_set_linsync_handler +( + mss_uart_instance_t * this_uart, + mss_uart_irq_handler_t handler +) +{ + ASSERT((this_uart == &g_mss_uart0) || (this_uart == &g_mss_uart1)); + ASSERT(handler != INVALID_IRQ_HANDLER); + + if(((this_uart == &g_mss_uart0) || (this_uart == &g_mss_uart1)) && + (handler != INVALID_IRQ_HANDLER)) + { + this_uart->sync_handler = handler; + + /* Clear any previously pended interrupts */ + NVIC_ClearPendingIRQ( this_uart->irqn ); + + /* Enable LIN sync detection interrupt. */ + set_bit_reg8(&this_uart->hw_reg->IEM,ELINSI); + + /* Enable UART instance interrupt in Cortex-M3 NVIC. */ + NVIC_EnableIRQ(this_uart->irqn); + } +} + +/***************************************************************************//** + * See mss_uart.h for details of how to use this function. + */ +void +MSS_UART_set_nack_handler +( + mss_uart_instance_t * this_uart, + mss_uart_irq_handler_t handler +) +{ + ASSERT((this_uart == &g_mss_uart0) || (this_uart == &g_mss_uart1)); + ASSERT(handler != INVALID_IRQ_HANDLER); + + if(((this_uart == &g_mss_uart0) || (this_uart == &g_mss_uart1)) && + (handler != INVALID_IRQ_HANDLER)) + { + this_uart->nack_handler = handler; + + /* Clear any previously pended interrupts */ + NVIC_ClearPendingIRQ( this_uart->irqn ); + + /* Enable LIN sync detection interrupt. */ + set_bit_reg8(&this_uart->hw_reg->IEM,ENACKI); + + /* Enable UART instance interrupt in Cortex-M3 NVIC. */ + NVIC_EnableIRQ(this_uart->irqn); + } +} + +/***************************************************************************//** + * See mss_uart.h for details of how to use this function. + */ +void +MSS_UART_set_rx_timeout_handler +( + mss_uart_instance_t * this_uart, + mss_uart_irq_handler_t handler +) +{ + ASSERT((this_uart == &g_mss_uart0) || (this_uart == &g_mss_uart1)); + ASSERT(handler != INVALID_IRQ_HANDLER); + + if(((this_uart == &g_mss_uart0) || (this_uart == &g_mss_uart1)) && + (handler != INVALID_IRQ_HANDLER)) + { + this_uart->rto_handler = handler; + + /* Clear any previously pended interrupts */ + NVIC_ClearPendingIRQ( this_uart->irqn ); + + /* Enable receiver timeout interrupt. */ + set_bit_reg8(&this_uart->hw_reg->IEM,ERTOI); + + /* Enable UART instance interrupt in Cortex-M3 NVIC. */ + NVIC_EnableIRQ(this_uart->irqn); + } +} + +/***************************************************************************//** + * See mss_uart.h for details of how to use this function. + */ +void +MSS_UART_enable_half_duplex +( + mss_uart_instance_t * this_uart +) +{ + ASSERT((this_uart == &g_mss_uart0) || (this_uart == &g_mss_uart1)); + if((this_uart == &g_mss_uart0) || (this_uart == &g_mss_uart1)) + { + /* enable single wire half-duplex mode */ + set_bit_reg8(&this_uart->hw_reg->MM2,ESWM); + } +} + +/***************************************************************************//** + * See mss_uart.h for details of how to use this function. + */ +void +MSS_UART_disable_half_duplex +( + mss_uart_instance_t * this_uart +) +{ + ASSERT((this_uart == &g_mss_uart0) || (this_uart == &g_mss_uart1)); + if((this_uart == &g_mss_uart0) || (this_uart == &g_mss_uart1)) + { + /* enable single wire half-duplex mode */ + clear_bit_reg8(&this_uart->hw_reg->MM2,ESWM); + } +} + +/***************************************************************************//** + * See mss_uart.h for details of how to use this function. + */ +void +MSS_UART_set_rx_endian +( + mss_uart_instance_t * this_uart, + mss_uart_endian_t endian +) +{ + ASSERT((this_uart == &g_mss_uart0) || (this_uart == &g_mss_uart1)); + ASSERT(MSS_UART_INVALID_ENDIAN > endian); + + if(((this_uart == &g_mss_uart0) || (this_uart == &g_mss_uart1)) && + (MSS_UART_INVALID_ENDIAN > endian)) + { + /* Configure MSB first / LSB first for receiver */ + ((MSS_UART_LITTLEEND == endian) ? (clear_bit_reg8(&this_uart->hw_reg->MM1,E_MSB_RX)) : + (set_bit_reg8(&this_uart->hw_reg->MM1,E_MSB_RX))); + } +} + +/***************************************************************************//** + * See mss_uart.h for details of how to use this function. + */ +void +MSS_UART_set_tx_endian +( + mss_uart_instance_t * this_uart, + mss_uart_endian_t endian +) +{ + ASSERT((this_uart == &g_mss_uart0) || (this_uart == &g_mss_uart1)); + ASSERT(MSS_UART_INVALID_ENDIAN > endian); + + if(((this_uart == &g_mss_uart0) || (this_uart == &g_mss_uart1)) && + (MSS_UART_INVALID_ENDIAN > endian)) + { + /* Configure MSB first / LSB first for transmitter */ + ((MSS_UART_LITTLEEND == endian) ? (clear_bit_reg8(&this_uart->hw_reg->MM1,E_MSB_TX)) : + (set_bit_reg8(&this_uart->hw_reg->MM1,E_MSB_TX)) ) ; + } +} + +/***************************************************************************//** + * See mss_uart.h for details of how to use this function. + */ +void +MSS_UART_set_filter_length +( + mss_uart_instance_t * this_uart, + mss_uart_filter_length_t length +) +{ + ASSERT((this_uart == &g_mss_uart0) || (this_uart == &g_mss_uart1)); + ASSERT(MSS_UART_INVALID_FILTER_LENGTH > length); + + if(((this_uart == &g_mss_uart0) || (this_uart == &g_mss_uart1)) && + (MSS_UART_INVALID_FILTER_LENGTH > length)) + { + /* Configure glitch filter length */ + this_uart->hw_reg->GFR = (uint8_t)length; + } +} + +/***************************************************************************//** + * See mss_uart.h for details of how to use this function. + */ +void +MSS_UART_enable_afm +( + mss_uart_instance_t * this_uart +) +{ + ASSERT((this_uart == &g_mss_uart0) || (this_uart == &g_mss_uart1)); + + if((this_uart == &g_mss_uart0) || (this_uart == &g_mss_uart1)) + { + /* Disable RX FIFO till address flag with correct address is received */ + set_bit_reg8(&this_uart->hw_reg->MM2,EAFM); + } +} + +/***************************************************************************//** + * See mss_uart.h for details of how to use this function. + */ +void +MSS_UART_disable_afm +( + mss_uart_instance_t * this_uart +) +{ + ASSERT((this_uart == &g_mss_uart0) || (this_uart == &g_mss_uart1)); + + if((this_uart == &g_mss_uart0) || (this_uart == &g_mss_uart1)) + { + /* Enable RX FIFO irrespective of address flag and + correct address is received */ + clear_bit_reg8(&this_uart->hw_reg->MM2,EAFM); + } +} + +/***************************************************************************//** + * See mss_uart.h for details of how to use this function. + */ +void +MSS_UART_enable_afclear +( + mss_uart_instance_t * this_uart +) +{ + ASSERT((this_uart == &g_mss_uart0) || (this_uart == &g_mss_uart1)); + + if((this_uart == &g_mss_uart0) || (this_uart == &g_mss_uart1)) + { + /* Enable address flag clearing */ + /* Disable RX FIFO till another address flag with + correct address is received */ + set_bit_reg8(&this_uart->hw_reg->MM2,EAFC); + } +} + +/***************************************************************************//** + * See mss_uart.h for details of how to use this function. + */ +void +MSS_UART_disable_afclear +( + mss_uart_instance_t * this_uart +) +{ + ASSERT((this_uart == &g_mss_uart0) || (this_uart == &g_mss_uart1)); + + if((this_uart == &g_mss_uart0) || (this_uart == &g_mss_uart1)) + { + /* Disable address flag clearing */ + clear_bit_reg8(&this_uart->hw_reg->MM2,EAFC); + } +} + +/***************************************************************************//** + * See mss_uart.h for details of how to use this function. + */ +void +MSS_UART_enable_rx_timeout +( + mss_uart_instance_t * this_uart, + uint8_t timeout +) +{ + ASSERT((this_uart == &g_mss_uart0) || (this_uart == &g_mss_uart1)); + + if((this_uart == &g_mss_uart0) || (this_uart == &g_mss_uart1)) + { + /* Load the receive timeout value */ + this_uart->hw_reg->RTO = timeout; + /*Enable receiver time-out */ + set_bit_reg8(&this_uart->hw_reg->MM0,ERTO); + } +} + +/***************************************************************************//** + * See mss_uart.h for details of how to use this function. + */ +void +MSS_UART_disable_rx_timeout +( + mss_uart_instance_t * this_uart +) +{ + ASSERT((this_uart == &g_mss_uart0) || (this_uart == &g_mss_uart1)); + + if((this_uart == &g_mss_uart0) || (this_uart == &g_mss_uart1)) + { + /*Disable receiver time-out */ + clear_bit_reg8(&this_uart->hw_reg->MM0,ERTO); + } +} + +/***************************************************************************//** + * See mss_uart.h for details of how to use this function. + */ +void +MSS_UART_enable_tx_time_guard +( + mss_uart_instance_t * this_uart, + uint8_t timeguard +) +{ + ASSERT((this_uart == &g_mss_uart0) || (this_uart == &g_mss_uart1)); + + if((this_uart == &g_mss_uart0) || (this_uart == &g_mss_uart1)) + { + /* Load the transmitter time guard value */ + this_uart->hw_reg->TTG = timeguard; + /*Enable transmitter time guard */ + set_bit_reg8(&this_uart->hw_reg->MM0,ETTG); + } +} + +/***************************************************************************//** + * See mss_uart.h for details of how to use this function. + */ +void +MSS_UART_disable_tx_time_guard +( + mss_uart_instance_t * this_uart +) +{ + ASSERT((this_uart == &g_mss_uart0) || (this_uart == &g_mss_uart1)); + + if((this_uart == &g_mss_uart0) || (this_uart == &g_mss_uart1)) + { + /*Disable transmitter time guard */ + clear_bit_reg8(&this_uart->hw_reg->MM0,ETTG); + } +} + +/***************************************************************************//** + * See mss_uart.h for details of how to use this function. + */ +void +MSS_UART_set_address +( + mss_uart_instance_t * this_uart, + uint8_t address +) +{ + ASSERT((this_uart == &g_mss_uart0) || (this_uart == &g_mss_uart1)); + + if((this_uart == &g_mss_uart0) || (this_uart == &g_mss_uart1)) + { + this_uart->hw_reg->ADR = address; + } +} + +/***************************************************************************//** + * See mss_uart.h for details of how to use this function. + */ +void +MSS_UART_set_ready_mode +( + mss_uart_instance_t * this_uart, + mss_uart_ready_mode_t mode +) +{ + ASSERT((this_uart == &g_mss_uart0) || (this_uart == &g_mss_uart1)); + ASSERT(MSS_UART_INVALID_READY_MODE > mode); + + if(((this_uart == &g_mss_uart0) || (this_uart == &g_mss_uart1)) && + (MSS_UART_INVALID_READY_MODE > mode ) ) + { + /* Configure mode 0 or mode 1 for TXRDY and RXRDY */ + ((MSS_UART_READY_MODE0 == mode) ? clear_bit_reg8(&this_uart->hw_reg->FCR,RDYMODE) : + set_bit_reg8(&this_uart->hw_reg->FCR,RDYMODE) ); + } +} + +/***************************************************************************//** + * Configure baud divisors using fractional baud rate if possible. + */ +static void +config_baud_divisors +( + mss_uart_instance_t * this_uart, + uint32_t baudrate +) +{ + ASSERT((this_uart == &g_mss_uart0) || (this_uart == &g_mss_uart1)); + + if((this_uart == &g_mss_uart0) || (this_uart == &g_mss_uart1)) + { + uint32_t baud_value; + uint32_t baud_value_by_64; + uint32_t baud_value_by_128; + uint32_t fractional_baud_value; + uint32_t pclk_freq; + + this_uart->baudrate = baudrate; + + /* Force the value of the CMSIS global variables holding the various system + * clock frequencies to be updated. */ + SystemCoreClockUpdate(); + if(this_uart == &g_mss_uart0) + { + pclk_freq = g_FrequencyPCLK0; + } + else + { + pclk_freq = g_FrequencyPCLK1; + } + + /* + * Compute baud value based on requested baud rate and PCLK frequency. + * The baud value is computed using the following equation: + * baud_value = PCLK_Frequency / (baud_rate * 16) + */ + baud_value_by_128 = (8u * pclk_freq) / baudrate; + baud_value_by_64 = baud_value_by_128 / 2u; + baud_value = baud_value_by_64 / 64u; + fractional_baud_value = baud_value_by_64 - (baud_value * 64u); + fractional_baud_value += (baud_value_by_128 - (baud_value * 128u)) - (fractional_baud_value * 2u); + + /* Assert if integer baud value fits in 16-bit. */ + ASSERT(baud_value <= UINT16_MAX); + + if(baud_value <= (uint32_t)UINT16_MAX) + { + if(baud_value > 1u) + { + /* + * Use Frational baud rate divisors + */ + /* set divisor latch */ + set_bit_reg8(&this_uart->hw_reg->LCR,DLAB); + + /* msb of baud value */ + this_uart->hw_reg->DMR = (uint8_t)(baud_value >> 8); + /* lsb of baud value */ + this_uart->hw_reg->DLR = (uint8_t)baud_value; + + /* reset divisor latch */ + clear_bit_reg8(&this_uart->hw_reg->LCR,DLAB); + + /* Enable Fractional baud rate */ + set_bit_reg8(&this_uart->hw_reg->MM0,EFBR); + + /* Load the fractional baud rate register */ + ASSERT(fractional_baud_value <= (uint32_t)UINT8_MAX); + this_uart->hw_reg->DFR = (uint8_t)fractional_baud_value; + } + else + { + /* + * Do NOT use Frational baud rate divisors. + */ + /* set divisor latch */ + set_bit_reg8(&this_uart->hw_reg->LCR,DLAB); + + /* msb of baud value */ + this_uart->hw_reg->DMR = (uint8_t)(baud_value >> 8u); + /* lsb of baud value */ + this_uart->hw_reg->DLR = (uint8_t)baud_value; + + /* reset divisor latch */ + clear_bit_reg8(&this_uart->hw_reg->LCR,DLAB); + + /* Disable Fractional baud rate */ + clear_bit_reg8(&this_uart->hw_reg->MM0,EFBR); + } + } + } +} + +/***************************************************************************//** + * See mss_uart.h for details of how to use this function. + */ +void +MSS_UART_set_usart_mode +( + mss_uart_instance_t * this_uart, + mss_uart_usart_mode_t mode +) +{ + ASSERT((this_uart == &g_mss_uart0) || (this_uart == &g_mss_uart1)); + ASSERT(MSS_UART_INVALID_SYNC_MODE > mode); + + if(((this_uart == &g_mss_uart0) || (this_uart == &g_mss_uart1)) && + (MSS_UART_INVALID_SYNC_MODE > mode)) + { + /* Nothing to do for the baudrate: operates at PCLK / 2 + glitch filter length */ + /* Clear the ESYN bits 2:0 */ + this_uart->hw_reg->MM0 &= ~SYNC_ASYNC_MODE_MASK; + this_uart->hw_reg->MM0 |= (uint8_t)mode; + } +} + +/******************************************************************************* + * Local Functions + *******************************************************************************/ +/******************************************************************************* + * Global initialization for all modes + */ +static void global_init +( + mss_uart_instance_t * this_uart, + uint32_t baud_rate, + uint8_t line_config +) +{ + /* The driver expects g_mss_uart0 and g_mss_uart1 to be the only + * mss_uart_instance_t instances used to identify UART0 and UART1. */ + ASSERT((this_uart == &g_mss_uart0) || (this_uart == &g_mss_uart1)); + + if(this_uart == &g_mss_uart0) + { + this_uart->hw_reg = UART0; + this_uart->irqn = UART0_IRQn; + /* reset UART0 */ + SYSREG->SOFT_RST_CR |= SYSREG_MMUART0_SOFTRESET_MASK; + /* Clear any previously pended UART0 interrupt */ + NVIC_ClearPendingIRQ(UART0_IRQn); + /* Take UART0 out of reset. */ + SYSREG->SOFT_RST_CR &= ~SYSREG_MMUART0_SOFTRESET_MASK; + } + else + { + this_uart->hw_reg = UART1; + this_uart->irqn = UART1_IRQn; + /* Reset UART1 */ + SYSREG->SOFT_RST_CR |= SYSREG_MMUART1_SOFTRESET_MASK; + /* Clear any previously pended UART1 interrupt */ + NVIC_ClearPendingIRQ(UART1_IRQn); + /* Take UART1 out of reset. */ + SYSREG->SOFT_RST_CR &= ~SYSREG_MMUART1_SOFTRESET_MASK; + } + + /* disable interrupts */ + this_uart->hw_reg->IER = 0u; + + /* FIFO configuration */ + this_uart->hw_reg->FCR = (uint8_t)MSS_UART_FIFO_SINGLE_BYTE; + /* clear receiver FIFO */ + set_bit_reg8(&this_uart->hw_reg->FCR,CLEAR_RX_FIFO); + /* clear transmitter FIFO */ + set_bit_reg8(&this_uart->hw_reg->FCR,CLEAR_TX_FIFO); + + /* set default READY mode : Mode 0*/ + /* enable RXRDYN and TXRDYN pins. The earlier FCR write to set the TX FIFO + * trigger level inadvertently disabled the FCR_RXRDY_TXRDYN_EN bit. */ + set_bit_reg8(&this_uart->hw_reg->FCR,RXRDY_TXRDYN_EN); + + /* disable loopback : local * remote */ + clear_bit_reg8(&this_uart->hw_reg->MCR,LOOP); + clear_bit_reg8(&this_uart->hw_reg->MCR,RLOOP); + + /* set default TX endian */ + clear_bit_reg8(&this_uart->hw_reg->MM1,E_MSB_TX); + /* set default RX endian */ + clear_bit_reg8(&this_uart->hw_reg->MM1,E_MSB_RX); + + /* default AFM : disabled */ + clear_bit_reg8(&this_uart->hw_reg->MM2,EAFM); + + /* disable TX time gaurd */ + clear_bit_reg8(&this_uart->hw_reg->MM0,ETTG); + + /* set default RX timeout */ + clear_bit_reg8(&this_uart->hw_reg->MM0,ERTO); + + /* disable fractional baud-rate */ + clear_bit_reg8(&this_uart->hw_reg->MM0,EFBR); + + /* disable single wire mode */ + clear_bit_reg8(&this_uart->hw_reg->MM2,ESWM); + + /* set filter to minimum value */ + this_uart->hw_reg->GFR = 0u; + /* set default TX time gaurd */ + this_uart->hw_reg->TTG = 0u; + /* set default RX timeout */ + this_uart->hw_reg->RTO = 0u; + + /* + * Configure baud rate divisors. This uses the frational baud rate divisor + * where possible to provide the most accurate baud rat possible. + */ + config_baud_divisors(this_uart, baud_rate); + + /* set the line control register (bit length, stop bits, parity) */ + this_uart->hw_reg->LCR = line_config; + + /* Instance setup */ + this_uart->baudrate = baud_rate; + this_uart->lineconfig = line_config; + this_uart->tx_buff_size = TX_COMPLETE; + this_uart->tx_buffer = (const uint8_t *)0; + this_uart->tx_idx = 0u; + + /* Default handlers for MSS UART interrupts */ + this_uart->rx_handler = NULL_HANDLER; + this_uart->tx_handler = NULL_HANDLER; + this_uart->linests_handler = NULL_HANDLER; + this_uart->modemsts_handler = NULL_HANDLER; + this_uart->rto_handler = NULL_HANDLER; + this_uart->nack_handler = NULL_HANDLER; + this_uart->pid_pei_handler = NULL_HANDLER; + this_uart->break_handler = NULL_HANDLER; + this_uart->sync_handler = NULL_HANDLER; + + /* Initialize the sticky status */ + this_uart->status = 0u; +} + +/***************************************************************************//** + * Interrupt service routine triggered by any MSS UART interrupt. This routine + * will call the handler function appropriate to the interrupt from the + * handlers previously registered with the driver through calls to the + * MSS_UART_set_*_handler() functions, or it will call the default_tx_handler() + * function in response to transmit interrupts if MSS_UART_irq_tx() is used to + * transmit data. + */ +static void +MSS_UART_isr +( + mss_uart_instance_t * this_uart +) +{ + uint8_t iirf; + + ASSERT((this_uart == &g_mss_uart0) || (this_uart == &g_mss_uart1)); + + if((this_uart == &g_mss_uart0) || (this_uart == &g_mss_uart1)) + { + iirf = this_uart->hw_reg->IIR & IIRF_MASK; + + switch (iirf) + { + case IIRF_MODEM_STATUS: /* Modem status interrupt */ + { + ASSERT(NULL_HANDLER != this_uart->modemsts_handler); + if(NULL_HANDLER != this_uart->modemsts_handler) + { + (*(this_uart->modemsts_handler))(this_uart); + } + } + break; + + case IIRF_THRE: /* Transmitter Holding Register Empty */ + { + ASSERT(NULL_HANDLER != this_uart->tx_handler); + if(NULL_HANDLER != this_uart->tx_handler) + { + (*(this_uart->tx_handler))(this_uart); + } + } + break; + + case IIRF_RX_DATA: /* Received Data Available */ + case IIRF_DATA_TIMEOUT: /* Received Data Timed-out */ + { + ASSERT(NULL_HANDLER != this_uart->rx_handler); + if(NULL_HANDLER != this_uart->rx_handler) + { + (*(this_uart->rx_handler))(this_uart); + } + } + break; + + case IIRF_RX_LINE_STATUS: /* Line Status Interrupt */ + { + ASSERT(NULL_HANDLER != this_uart->linests_handler); + if(NULL_HANDLER != this_uart->linests_handler) + { + (*(this_uart->linests_handler))(this_uart); + } + } + break; + + case IIRF_MMI: + { + /* Identify multimode interrupts and handle */ + + /* Receiver time-out interrupt */ + if(read_bit_reg8(&this_uart->hw_reg->IIM,ERTOI)) + { + ASSERT(NULL_HANDLER != this_uart->rto_handler); + if(NULL_HANDLER != this_uart->rto_handler) + { + (*(this_uart->rto_handler))(this_uart); + } + } + /* NACK interrupt */ + if(read_bit_reg8(&this_uart->hw_reg->IIM,ENACKI)) + { + ASSERT(NULL_HANDLER != this_uart->nack_handler); + if(NULL_HANDLER != this_uart->nack_handler) + { + (*(this_uart->nack_handler))(this_uart); + } + } + + /* PID parity error interrupt */ + if(read_bit_reg8(&this_uart->hw_reg->IIM,EPID_PEI)) + { + ASSERT(NULL_HANDLER != this_uart->pid_pei_handler); + if(NULL_HANDLER != this_uart->pid_pei_handler) + { + (*(this_uart->pid_pei_handler))(this_uart); + } + } + + /* LIN break detection interrupt */ + if(read_bit_reg8(&this_uart->hw_reg->IIM,ELINBI)) + { + ASSERT(NULL_HANDLER != this_uart->break_handler); + if(NULL_HANDLER != this_uart->break_handler) + { + (*(this_uart->break_handler))(this_uart); + } + } + + /* LIN Sync detection interrupt */ + if(read_bit_reg8(&this_uart->hw_reg->IIM,ELINSI)) + { + ASSERT(NULL_HANDLER != this_uart->sync_handler); + if(NULL_HANDLER != this_uart->sync_handler) + { + (*(this_uart->sync_handler))(this_uart); + } + } + break; + } + + default: + { + ASSERT(INVALID_INTERRUPT); + } + break; + } + } +} + +/***************************************************************************//** + * See mss_uart.h for details of how to use this function. + */ +static void +default_tx_handler +( + mss_uart_instance_t * this_uart +) +{ + uint8_t status; + + ASSERT((this_uart == &g_mss_uart0) || (this_uart == &g_mss_uart1)); + ASSERT(( (uint8_t *)0 ) != this_uart->tx_buffer); + ASSERT(0u < this_uart->tx_buff_size); + + if(((this_uart == &g_mss_uart0) || (this_uart == &g_mss_uart1)) && + (((uint8_t *)0 ) != this_uart->tx_buffer) && + (0u < this_uart->tx_buff_size)) + { + /* Read the Line Status Register and update the sticky record. */ + status = this_uart->hw_reg->LSR; + this_uart->status |= status; + + /* + * This function should only be called as a result of a THRE interrupt. + * Verify that this is true before proceeding to transmit data. + */ + if(status & MSS_UART_THRE) + { + uint32_t i; + uint32_t fill_size = TX_FIFO_SIZE; + uint32_t tx_remain = this_uart->tx_buff_size - this_uart->tx_idx; + + /* Calculate the number of bytes to transmit. */ + if(tx_remain < TX_FIFO_SIZE) + { + fill_size = tx_remain; + } + + /* Fill the TX FIFO with the calculated the number of bytes. */ + for(i = 0u; i < fill_size; ++i) + { + /* Send next character in the buffer. */ + this_uart->hw_reg->THR = this_uart->tx_buffer[this_uart->tx_idx]; + ++this_uart->tx_idx; + } + } + + /* Flag Tx as complete if all data has been pushed into the Tx FIFO. */ + if(this_uart->tx_idx == this_uart->tx_buff_size) + { + this_uart->tx_buff_size = TX_COMPLETE; + /* disables TX interrupt */ + clear_bit_reg8(&this_uart->hw_reg->IER,ETBEI); + } + } +} + +#ifdef __cplusplus +} +#endif diff --git a/bsp/smartfusion2/libraries/mss_uart/mss_uart.h b/bsp/smartfusion2/libraries/mss_uart/mss_uart.h new file mode 100644 index 0000000000..9efa7ed234 --- /dev/null +++ b/bsp/smartfusion2/libraries/mss_uart/mss_uart.h @@ -0,0 +1,2639 @@ +/******************************************************************************* + * (c) Copyright 2011-2013 Microsemi SoC Products Group. All rights reserved. + * + * SmartFusion2 Microcontroller Subsystem MMUART bare metal software driver + * public API. + * + * SVN $Revision: 5610 $ + * SVN $Date: 2013-04-05 18:49:30 +0530 (Fri, 05 Apr 2013) $ + */ +/*=========================================================================*//** + @mainpage SmartFusion2 MSS UART Bare Metal Driver. + ============================================================================== + @section intro_sec Introduction + ============================================================================== + The SmartFusion2 microcontroller subsystem (MSS) includes two multi-mode UART + (MMUART) peripherals for serial communication. This driver provides a set of + functions for controlling the MSS MMUARTs as part of a bare metal system + where no operating system is available. These drivers can be adapted for use + as part of an operating system, but the implementation of the adaptation layer + between this driver and the operating system's driver model is outside the + scope of this driver. + Note: MSS UART is synonymous with MSS MMUART in this document. + + ============================================================================== + @section hw_dependencies Hardware Flow Dependencies + ============================================================================== + The configuration of all features of the MSS MMUART peripherals is covered by + this driver with the exception of the SmartFusion2 IOMUX configuration. + SmartFusion2 allows multiple non-concurrent uses of some external pins through + IOMUX configuration. This feature allows optimization of external pin usage by + assigning external pins for use by either the microcontroller subsystem or the + FPGA fabric. The MSS MMUART serial signals are routed through IOMUXs to the + SmartFusion2 device external pins. The MSS MMUART serial signals may also be + routed through IOMUXs to the SmartFusion2 FPGA fabric. For more information on + IOMUX, refer to the IOMUX section of the SmartFusion2 Microcontroller + Subsystem (MSS) User�s Guide. + The IOMUXs are configured using the SmartFusion2 MSS configurator tool. You + must ensure that the MSS MMUART peripherals are enabled and configured in the + SmartFusion2 MSS configurator if you wish to use them. For more information on + IOMUXs, refer to the IOMUX section of the SmartFusion2 Microcontroller + Subsystem (MSS) User�s Guide. + The base address, register addresses and interrupt number assignment for the + MSS MMUART peripherals are defined as constants in the SmartFusion2 CMSIS HAL. + You must ensure that the latest SmartFusion2 CMSIS HAL is included in the + project settings of the software tool chain used to build your project and + that it is generated into your project. + + ============================================================================== + @section theory_op Theory of Operation + ============================================================================== + The MSS MMUART driver functions are grouped into the following categories: + - Initialization and configuration functions + - Polled transmit and receive functions + - Interrupt driven transmit and receive functions + + -------------------------------- + Initialization and Configuration + -------------------------------- + The MSS MMUART supports the following four broad modes of operation: + - UART or USART mode + - LIN mode + - IrDA mode + - Smartcard or ISO 7816 mode + The MSS MMUART driver provides the MSS_UART_init(), MSS_UART_lin_init(), + MSS_UART_irda_init() and MSS_UART_smartcard_init() functions to initialize the + MSS MMUARTs for operation in one of these modes. One of these initialization + functions must be called before any other MSS MMUART driver functions can be + called. The MSS MMUART operating modes are mutually exclusive; therefore only + one of the initialization functions must be called. The first parameter of the + initialization functions is a pointer to one of two global data structures + used to store state information for each MSS MMUART. A pointer to these data + structures is also used as the first parameter to many of the driver functions + to identify which MSS MMUART will be used by the called function. The names of + these two data structures are g_mss_uart0 and g_mss_uart1. Therefore, any call + to an MSS MMUART function should be of the form + MSS_UART_function_name( &g_mss_uart0, ... ) or + MSS_UART_function_name( &g_mss_uart1, ... ). + + UART or USART Mode + For the UART or USART modes of operation, the MSS MMUART driver is initialized + through a call to the MSS_UART_init() function. This function takes the UART�s + configuration as its parameters. The MSS_UART_init() function must be called + before any other MSS MMUART driver functions can be called. + The MSS_UART_init() function configures the baud rate based on the input baud + rate parameter and if possible uses a fractional baud rate for greater + precision. This function disables the LIN, IrDA and SmartCard modes. + + LIN mode + For the LIN mode of operation, the MSS MMUART driver is initialized through a + call to the MSS_UART_lin_init() function. This function takes the LIN node�s + configuration as its parameters. The MSS_UART_lin_init() function must be + called before any other MSS MMUART driver functions can be called. The + MSS_UART_lin_init() function configures the baud rate based on the input baud + rate parameter and if possible uses a fractional baud rate for greater + precision. This function disables the IrDA and SmartCard modes. + The driver also provides the following LIN mode configuration functions: + - MSS_UART_set_break() + - MSS_UART_clear_break() + - MSS_UART_set_pidpei_handler() + - MSS_UART_set_linbreak_handler() + - MSS_UART_set_linsync_handler() + Note: These LIN mode configuration functions can only be called after the + MSS_UART_lin_init() function is called. + + IrDA mode + For the IrDA mode of operation, the driver is initialized through a call to + the MSS_UART_irda_init() function. This function takes the IrDA node�s + configuration as its parameters. The MSS_UART_irda_init() function must be + called before any other MSS MMUART driver functions can be called. The + MSS_UART_irda_init() function configures the baud rate based on the input baud + rate parameter and if possible uses a fractional baud rate for greater + precision. This function disables the LIN and SmartCard modes. + + Smartcard or ISO 7816 mode + For the Smartcard or ISO 7816 mode of operation, the driver is initialized + through a call to the MSS_UART_smartcard_init() function. This function takes + the smartcard configuration as its parameters. The MSS_UART_smartcard_init() + function must be called before any other MSS MMUART driver functions can be + called. The MSS_UART_smartcard_init() function configures the baud rate based + on the input baud rate parameter and if possible uses a fractional baud rate + for greater precision. This function disables the LIN and IrDA modes. + The driver also provides the following Smartcard mode configuration functions: + - MSS_UART_enable_halfduplex() + - MSS_UART_disable_halfduplex() + - MSS_UART_set_nack_handler() + Note: These Smartcard mode configuration functions can only be called after + the MSS_UART_smartcard_init() function is called. + + Common Configuration Functions + The driver also provides the configuration functions that can be used with all + MSS MMUART operating modes. These common configuration functions are as + follows: + - MSS_UART_set_rx_endian() + - MSS_UART_set_tx_endian() + - MSS_UART_enable_afclear() + - MSS_UART_disable_afclear() + - MSS_UART_enable_rx_timeout() + - MSS_UART_disable_rx_timeout() + - MSS_UART_enable_tx_time_guard() + - MSS_UART_disable_tx_time_guard() + - MSS_UART_set_address() + - MSS_UART_set_ready_mode() + - MSS_UART_set_usart_mode() + - MSS_UART_set_filter_length() + - MSS_UART_enable_afm() + - MSS_UART_disable_afm() + Note: These configuration functions can only be called after one of the + MSS_UART_init(), MSS_UART_lin_init(), MSS_UART_irda_init() or + MSS_UART_smartcard_init() functions is called. + + -------------------------------------- + Polled Transmit and Receive Operations + -------------------------------------- + The driver can be used to transmit and receive data once initialized. + Data is transmitted using the MSS_UART_polled_tx() function. This function is + blocking, meaning that it will only return once the data passed to the + function has been sent to the MSS MMUART hardware transmitter. Data received + by the MSS MMUART hardware receiver can be read by the MSS_UART_get_rx() + function. + The MSS_UART_polled_tx_string() function is provided to transmit a NULL (�\0�) + terminated string in polled mode. This function is blocking, meaning that it + will only return once the data passed to the function has been sent to the MSS + MMUART hardware transmitter. + The MSS_UART_fill_tx_fifo() function fills the MSS MMUART hardware transmit + FIFO with data from a buffer passed as a parameter and returns the number of + bytes transferred to the FIFO. If the transmit FIFO is not empty when the + MSS_UART_fill_tx_fifo() function is called it returns immediately without + transferring any data to the FIFO. + + --------------------------- + Interrupt Driven Operations + --------------------------- + The driver can also transmit or receive data under interrupt control, freeing + your application to perform other tasks until an interrupt occurs indicating + that the driver�s attention is required. + + Interrupt Handlers + The MSS MMUART driver supports all types of interrupt triggered by the MSS + MMUART. The driver�s internal top level interrupt handler identifies the + source of the MSS MMUART interrupt and calls the corresponding lower level + handler function that you previously registered with the driver through calls + to the MSS_UART_set_rx_handler(), MSS_UART_set_tx_handler(), + MSS_UART_set_rxstatus_handler(), and MSS_UART_set_modemstatus_handler() + functions. You are responsible for creating these lower level interrupt + handlers as part of your application program and registering them with the + driver. + Note: The SmartFusion2 CMSIS-PAL defines the UART0_IRQHandler() and + UART1_IRQHandler() functions (with weak linkage) and assigns them as the + interrupt service routines (ISR) for the MSS MMUART interrupt inputs to + the Cortex-M3 NVIC. The MSS MMUART driver provides the implementation + functions for both of these ISRs from which it calls its own internal + top level, interrupt handler function. + The MSS_UART_enable_irq() and MSS_UART_disable_irq() functions are used to + enable or disable the received line status, received data available/character + timeout, transmit holding register empty and modem status interrupts at the + MSS MMUART level. The MSS_UART_enable_irq() function also enables the MSS + MMUART instance interrupt at the Cortex-M3 level. + + Transmitting Data + Interrupt-driven transmit is initiated by a call to MSS_UART_irq_tx(), + specifying the block of data to transmit. Your application is then free to + perform other tasks and inquire later whether transmit has completed by + calling the MSS_UART_tx_complete() function. The MSS_UART_irq_tx() function + enables the UART�s transmit holding register empty (THRE) interrupt and then, + when the interrupt goes active, the driver�s default THRE interrupt handler + transfers the data block to the UART until the entire block is transmitted. + Note: You can use the MSS_UART_set_tx_handler() function to assign an + alternative handler to the THRE interrupt. In this case, you must not + use the MSS_UART_irq_tx() function to initiate the transmit, as this + will re-assign the driver�s default THRE interrupt handler to the THRE + interrupt. Instead, your alternative THRE interrupt handler must include + a call to the MSS_UART_fill_tx_fifo() function to transfer the data to + the UART. + + Receiving Data + Interrupt-driven receive is performed by first calling + MSS_UART_set_rx_handler() to register a receive handler function that will be + called by the driver whenever receive data is available. You must provide this + receive handler function which must include a call to the MSS_UART_get_rx() + function to actually read the received data. + + ----------- + UART Status + ----------- + The function MSS_UART_get_rx_status() is used to read the receiver error + status. This function returns the overrun, parity, framing, break, and FIFO + error status of the receiver. + The function MSS_UART_get_tx_status() is used to read the transmitter status. + This function returns the transmit empty (TEMT) and transmit holding register + empty (THRE) status of the transmitter. + The function MSS_UART_get_modem_status() is used to read the modem status + flags. This function returns the current value of the modem status register. + + -------- + Loopback + -------- + The MSS_UART_set_loopback() function can be used to locally loopback the Tx + and Rx lines of a UART. This is not to be confused with the loopback of UART0 + to UART1, which can be achieved through the microcontroller subsystem�s system + registers. + + *//*=========================================================================*/ +#ifndef __MSS_UART_H_ +#define __MSS_UART_H_ 1 + +#include "../../CMSIS/m2sxxx.h" +#include <stddef.h> + +#ifdef __cplusplus +extern "C" { +#endif + +/***************************************************************************//** + Baud rates + The following definitions are used to specify standard baud rates as a + parameter to the MSS_UART_init() function. + */ +#define MSS_UART_110_BAUD 110 +#define MSS_UART_300_BAUD 300 +#define MSS_UART_1200_BAUD 1200 +#define MSS_UART_2400_BAUD 2400 +#define MSS_UART_4800_BAUD 4800 +#define MSS_UART_9600_BAUD 9600 +#define MSS_UART_19200_BAUD 19200 +#define MSS_UART_38400_BAUD 38400 +#define MSS_UART_57600_BAUD 57600 +#define MSS_UART_115200_BAUD 115200 +#define MSS_UART_230400_BAUD 230400 +#define MSS_UART_460800_BAUD 460800 +#define MSS_UART_921600_BAUD 921600 + +/***************************************************************************//** + Data Bits Length + The following defines are used to build the value of the MSS_UART_init() + function line_config parameter. + */ +#define MSS_UART_DATA_5_BITS ( (uint8_t) 0x00 ) +#define MSS_UART_DATA_6_BITS ( (uint8_t) 0x01 ) +#define MSS_UART_DATA_7_BITS ( (uint8_t) 0x02 ) +#define MSS_UART_DATA_8_BITS ( (uint8_t) 0x03 ) + +/***************************************************************************//** + Parity + The following defines are used to build the value of the MSS_UART_init() + function line_config parameter. + */ +#define MSS_UART_NO_PARITY ( (uint8_t) 0x00 ) +#define MSS_UART_ODD_PARITY ( (uint8_t) 0x08 ) +#define MSS_UART_EVEN_PARITY ( (uint8_t) 0x18 ) +#define MSS_UART_STICK_PARITY_0 ( (uint8_t) 0x38 ) +#define MSS_UART_STICK_PARITY_1 ( (uint8_t) 0x28 ) + +/***************************************************************************//** + Number of Stop Bits + The following defines are used to build the value of the MSS_UART_init() + function line_config parameter. + */ +#define MSS_UART_ONE_STOP_BIT ( (uint8_t) 0x00 ) +#define MSS_UART_ONEHALF_STOP_BIT ( (uint8_t) 0x04 ) +#define MSS_UART_TWO_STOP_BITS ( (uint8_t) 0x04 ) + +/***************************************************************************//** + Receiver Error Status + The following defines are used to determine the UART receiver error type. + These bit mask constants are used with the return value of the + MSS_UART_get_rx_status() function to find out if any errors occurred while + receiving data. + */ +#define MSS_UART_INVALID_PARAM ( (uint8_t)0xFF ) +#define MSS_UART_NO_ERROR ( (uint8_t)0x00 ) +#define MSS_UART_OVERUN_ERROR ( (uint8_t)0x02 ) +#define MSS_UART_PARITY_ERROR ( (uint8_t)0x04 ) +#define MSS_UART_FRAMING_ERROR ( (uint8_t)0x08 ) +#define MSS_UART_BREAK_ERROR ( (uint8_t)0x10 ) +#define MSS_UART_FIFO_ERROR ( (uint8_t)0x80 ) + +/***************************************************************************//** + Transmitter Status + The following definitions are used to determine the UART transmitter status. + These bit mask constants are used with the return value of the + MSS_UART_get_tx_status() function to find out the status of the transmitter. + */ +#define MSS_UART_TX_BUSY ( (uint8_t) 0x00 ) +#define MSS_UART_THRE ( (uint8_t) 0x20 ) +#define MSS_UART_TEMT ( (uint8_t) 0x40 ) + +/***************************************************************************//** + Modem Status + The following defines are used to determine the modem status. These bit + mask constants are used with the return value of the + MSS_UART_get_modem_status() function to find out the modem status of + the UART. + */ +#define MSS_UART_DCTS ( (uint8_t) 0x01 ) +#define MSS_UART_DDSR ( (uint8_t) 0x02 ) +#define MSS_UART_TERI ( (uint8_t) 0x04 ) +#define MSS_UART_DDCD ( (uint8_t) 0x08 ) +#define MSS_UART_CTS ( (uint8_t) 0x10 ) +#define MSS_UART_DSR ( (uint8_t) 0x20 ) +#define MSS_UART_RI ( (uint8_t) 0x40 ) +#define MSS_UART_DCD ( (uint8_t) 0x80 ) + +/***************************************************************************//** + This typedef specifies the irq_mask parameter for the MSS_UART_enable_irq() + and MSS_UART_disable_irq() functions. The driver defines a set of bit masks + that are used to build the value of the irq_mask parameter. A bitwise OR of + these bit masks is used to enable or disable multiple MSS MMUART interrupts. + */ +typedef uint16_t mss_uart_irq_t; + +/***************************************************************************//** + The following defines specify the interrupt masks to enable and disable MSS + MMUART interrupts. They are used to build the value of the irq_mask parameter + for the MSS_UART_enable_irq() and MSS_UART_disable_irq() functions. A bitwise + OR of these constants is used to enable or disable multiple interrupts. + */ +#define MSS_UART_RBF_IRQ 0x001 +#define MSS_UART_TBE_IRQ 0x002 +#define MSS_UART_LS_IRQ 0x004 +#define MSS_UART_MS_IRQ 0x008 +#define MSS_UART_RTO_IRQ 0x010 +#define MSS_UART_NACK_IRQ 0x020 +#define MSS_UART_PIDPE_IRQ 0x040 +#define MSS_UART_LINB_IRQ 0x080 +#define MSS_UART_LINS_IRQ 0x100 +#define MSS_UART_INVALID_IRQ UINT16_MAX + +/***************************************************************************//** + This enumeration specifies the receiver FIFO trigger level. This is the number + of bytes that must be received before the UART generates a receive data + available interrupt. It provides the allowed values for the + MSS_UART_set_rx_handler() function trigger_level parameter. + */ +typedef enum { + MSS_UART_FIFO_SINGLE_BYTE = 0x00, + MSS_UART_FIFO_FOUR_BYTES = 0x40, + MSS_UART_FIFO_EIGHT_BYTES = 0x80, + MSS_UART_FIFO_FOURTEEN_BYTES = 0xC0, + MSS_UART_FIFO_INVALID_TRIG_LEVEL +} mss_uart_rx_trig_level_t; + +/***************************************************************************//** + This enumeration specifies the loopback configuration of the UART. It provides + the allowed values for the MSS_UART_set_loopback() function�s loopback + parameter. Use MSS_UART_LOCAL_LOOPBACK_ON to set up the UART to locally + loopback its Tx and Rx lines. Use MSS_UART_REMOTE_LOOPBACK_ON to set up the + UART in remote loopback mode. + */ +typedef enum { + MSS_UART_LOCAL_LOOPBACK_OFF, + MSS_UART_LOCAL_LOOPBACK_ON, + MSS_UART_REMOTE_LOOPBACK_OFF, + MSS_UART_REMOTE_LOOPBACK_ON, + MSS_UART_AUTO_ECHO_OFF, + MSS_UART_AUTO_ECHO_ON, + MSS_UART_INVALID_LOOPBACK +} mss_uart_loopback_t; + +/***************************************************************************//** + IrDA input / output polarity. + This enumeration specifies the RZI modem polarity for input and output signals. + This is passed as parameters in MSS_UART_irda_init() function. + */ +typedef enum { + MSS_UART_ACTIVE_LOW = 0u, + MSS_UART_ACTIVE_HIGH = 1u, + MSS_UART_INVALID_POLARITY +} mss_uart_rzi_polarity_t; + +/***************************************************************************//** + IrDA input / output pulse width. + This enumeration specifies the RZI modem pulse width for input and output signals. + This is passed as parameters in MSS_UART_irda_init() function. + */ +typedef enum { + MSS_UART_3_BY_16 = 0u, + MSS_UART_1_BY_4 = 1u, + MSS_UART_INVALID_PW +} mss_uart_rzi_pulsewidth_t; + +/***************************************************************************//** + Tx / Rx endianess. + This enumeration specifies the MSB first or LSB first for MSS UART transmitter + and receiver. The parameter of this type shall be passed in + MSS_UART_set_rx_endian()and MSS_UART_set_tx_endian() functions. + */ +typedef enum { + MSS_UART_LITTLEEND, + MSS_UART_BIGEND, + MSS_UART_INVALID_ENDIAN +} mss_uart_endian_t; + +/***************************************************************************//** + Glitch filter length. + This enumeration specifies the glitch filter length. The function + MSS_UART_set_filter_length() accepts the parameter of this type. + */ +typedef enum { + MSS_UART_LEN0 = 0, + MSS_UART_LEN1 = 1, + MSS_UART_LEN2 = 2, + MSS_UART_LEN3 = 3, + MSS_UART_LEN4 = 4, + MSS_UART_LEN5 = 5, + MSS_UART_LEN6 = 6, + MSS_UART_LEN7 = 7, + MSS_UART_INVALID_FILTER_LENGTH = 8 +} mss_uart_filter_length_t; + +/***************************************************************************//** + TXRDY and RXRDY mode. + This enumeration specifies the TXRDY and RXRDY signal modes. The function + MSS_UART_set_ready_mode() accepts the parameter of this type. + */ +typedef enum { + MSS_UART_READY_MODE0, + MSS_UART_READY_MODE1, + MSS_UART_INVALID_READY_MODE +} mss_uart_ready_mode_t; + +/***************************************************************************//** + USART mode of operation. + This enumeration specifies the mode of operation of MSS UART when operating + as USART. The function MSS_UART_set_usart_mode() accepts the parameter of this type. + */ +typedef enum { + MSS_UART_ASYNC_MODE = 0, + MSS_UART_SYNC_SLAVE_POS_EDGE_CLK = 1, + MSS_UART_SYNC_SLAVE_NEG_EDGE_CLK = 2, + MSS_UART_SYNC_MASTER_POS_EDGE_CLK = 3, + MSS_UART_SYNC_MASTER_NEG_EDGE_CLK = 4, + MSS_UART_INVALID_SYNC_MODE = 5 +} mss_uart_usart_mode_t; + + +/***************************************************************************//** + MSS UART instance type. + This is type definition for MSS UART instance. You need to create and + maintain a record of this type. This holds all data regarding the MSS UART + instance + */ +typedef struct mss_uart_instance mss_uart_instance_t; + +/***************************************************************************//** + Interrupt handler prototype. + This typedef specifies the function prototype for MSS UART interrupt handlers. + All interrupt handlers registered with the MSS UART driver must be of this type. + The interrupt handlers are registered with the driver through the + MSS_UART_set_rx_handler(), MSS_UART_set_tx_handler(), + MSS_UART_set_rxstatus_handler(), and MSS_UART_set_modemstatus_handler() + functions. + The this_uart parameter is a pointer to either g_mss_uart0 or g_mss_uart1 to + identify the MSS UART to associate with the handler function. + */ +typedef void (*mss_uart_irq_handler_t)( mss_uart_instance_t * this_uart ); + +/***************************************************************************//** + mss_uart_instance. + There is one instance of this structure for each instance of the + microcontroller subsystem�s UARTs. Instances of this structure are used to + identify a specific UART. A pointer to an initialized instance of the + mss_uart_instance_t structure is passed as the first parameter to + MSS UART driver functions to identify which UART should perform the + requested operation. + */ +struct mss_uart_instance{ + /* CMSIS related defines identifying the UART hardware. */ + UART_TypeDef * hw_reg; /*!< Pointer to UART registers. */ + IRQn_Type irqn; /*!< UART's Cortex-M3 NVIC interrupt number. */ + uint32_t baudrate; /*!< Operating baud rate. */ + uint8_t lineconfig; /*!< Line configuration parameters. */ + uint8_t status; /*!< Sticky line status. */ + + /* transmit related info (used with interrupt driven transmit): */ + const uint8_t * tx_buffer; /*!< Pointer to transmit buffer. */ + uint32_t tx_buff_size; /*!< Transmit buffer size. */ + uint32_t tx_idx; /*!< Index within transmit buffer of next byte to transmit.*/ + + /* line status interrupt handler:*/ + mss_uart_irq_handler_t linests_handler; /*!< Pointer to user registered line status handler. */ + /* receive interrupt handler:*/ + mss_uart_irq_handler_t rx_handler; /*!< Pointer to user registered receiver handler. */ + /* transmit interrupt handler:*/ + mss_uart_irq_handler_t tx_handler; /*!< Pointer to user registered transmit handler. */ + /* modem status interrupt handler:*/ + mss_uart_irq_handler_t modemsts_handler; /*!< Pointer to user registered modem status handler. */ + /* receiver timeout interrupt handler */ + mss_uart_irq_handler_t rto_handler; /*!< Pointer to user registered receiver timeout handler. */ + /* NACK interrupt handler */ + mss_uart_irq_handler_t nack_handler; /*!< Pointer to user registered NACK handler. */ + /* PID parity prror interrup handler */ + mss_uart_irq_handler_t pid_pei_handler; /*!< Pointer to user registered PID parity error handler. */ + /* LIN break interrupt handler */ + mss_uart_irq_handler_t break_handler; /*!< Pointer to user registered LIN break handler. */ + /* LIN sync detection interrupt handler */ + mss_uart_irq_handler_t sync_handler; /*!< Pointer to user registered LIN sync dectection handler. */ +}; + +/***************************************************************************//** + This instance of mss_uart_instance_t holds all data related to the operations + performed by UART0. The function MSS_UART_init() initializes this structure. + A pointer to g_mss_uart0 is passed as the first parameter to MSS UART driver + functions to indicate that UART0 should perform the requested operation. + */ +extern mss_uart_instance_t g_mss_uart0; + +/***************************************************************************//** + This instance of mss_uart_instance_t holds all data related to the operations + performed by UART1. The function MSS_UART_init() initializes this structure. + A pointer to g_mss_uart1 is passed as the first parameter to MSS UART driver + functions to indicate that UART1 should perform the requested operation. + */ +extern mss_uart_instance_t g_mss_uart1; + +/***************************************************************************//** + The MSS_UART_init() function initializes and configures one of the SmartFusion2 + MSS UARTs with the configuration passed as a parameter. The configuration + parameters are the baud_rate which is used to generate the baud value and the + line_config which is used to specify the line configuration (bit length, + stop bits and parity). + + @param this_uart + The this_uart parameter is a pointer to an mss_uart_instance_t structure + identifying the MSS UART hardware block to be initialized. There are two + such data structures, g_mss_uart0 and g_mss_uart1, associated with MSS + UART0 and MSS UART1 respectively. This parameter must point to either + the g_mss_uart0 or g_mss_uart1 global data structure defined within + the UART driver.. + + @param baud_rate + The baud_rate parameter specifies the baud rate. It can be specified for + common baud rates� using the following defines: + � MSS_UART_110_BAUD + � MSS_UART_300_BAUD + � MSS_UART_1200_BAUD + � MSS_UART_2400_BAUD + � MSS_UART_4800_BAUD + � MSS_UART_9600_BAUD + � MSS_UART_19200_BAUD + � MSS_UART_38400_BAUD + � MSS_UART_57600_BAUD + � MSS_UART_115200_BAUD + � MSS_UART_230400_BAUD + � MSS_UART_460800_BAUD + � MSS_UART_921600_BAUD + Alternatively, any nonstandard baud rate can be specified by simply passing + the actual required baud rate as the value for this parameter. + + @param line_config + The line_config parameter is the line configuration specifying the bit length, + number of stop bits and parity settings. This is a bitwise OR of one value + from each of the following groups of allowed values: + � One of the following to specify the transmit/receive data bit length: + MSS_UART_DATA_5_BITS + MSS_UART_DATA_6_BITS, + MSS_UART_DATA_7_BITS + MSS_UART_DATA_8_BITS + � One of the following to specify the parity setting: + MSS_UART_NO_PARITY + MSS_UART_EVEN_PARITY + MSS_UART_ODD_PARITY + MSS_UART_STICK_PARITY_0 + MSS_UART_STICK_PARITY_1 + � One of the following to specify the number of stop bits: + MSS_UART_ONE_STOP_BIT + MSS_UART_ONEHALF_STOP_BIT + MSS_UART_TWO_STOP_BITS + + @return + This function does not return a value. + + Example: + @code + #include "mss_uart.h" + + int main(void) + { + MSS_UART_init(&g_mss_uart0, + MSS_UART_57600_BAUD, + MSS_UART_DATA_8_BITS | MSS_UART_NO_PARITY | MSS_UART_ONE_STOP_BIT); + + return(0); + } + @endcode + */ +void +MSS_UART_init +( + mss_uart_instance_t* this_uart, + uint32_t baud_rate, + uint8_t line_config +); + +/***************************************************************************//** + The MSS_UART_lin_init() function is used to initialize the MSS UART for + LIN mode of operation. The configuration parameters are the baud_rate which is + used to generate the baud value and the line_config which is used to specify + the line configuration (bit length, stop bits and parity). + + @param this_uart + The this_uart parameter is a pointer to an mss_uart_instance_t + structure identifying the MSS UART hardware block that will perform + the requested function. There are two such data structures, + g_mss_uart0 and g_mss_uart1, associated with MSS UART0 and MSS UART1. + This parameter must point to either the g_mss_uart0 or g_mss_uart1 + global data structure defined within the UART driver. + + @param baud_rate + The baud_rate parameter specifies the baud rate. It can be specified for + common baud rates� using the following defines: + � MSS_UART_110_BAUD + � MSS_UART_300_BAUD + � MSS_UART_1200_BAUD + � MSS_UART_2400_BAUD + � MSS_UART_4800_BAUD + � MSS_UART_9600_BAUD + � MSS_UART_19200_BAUD + � MSS_UART_38400_BAUD + � MSS_UART_57600_BAUD + � MSS_UART_115200_BAUD + � MSS_UART_230400_BAUD + � MSS_UART_460800_BAUD + � MSS_UART_921600_BAUD + Alternatively, any nonstandard baud rate can be specified by simply passing + the actual required baud rate as the value for this parameter. + + @param line_config + The line_config parameter is the line configuration specifying the bit length, + number of stop bits and parity settings. This is a bitwise OR of one value + from each of the following groups of allowed values: + � One of the following to specify the transmit/receive data bit length: + MSS_UART_DATA_5_BITS + MSS_UART_DATA_6_BITS, + MSS_UART_DATA_7_BITS + MSS_UART_DATA_8_BITS + � One of the following to specify the parity setting: + MSS_UART_NO_PARITY + MSS_UART_EVEN_PARITY + MSS_UART_ODD_PARITY + MSS_UART_STICK_PARITY_0 + MSS_UART_STICK_PARITY_1 + � One of the following to specify the number of stop bits: + MSS_UART_ONE_STOP_BIT + MSS_UART_ONEHALF_STOP_BIT + MSS_UART_TWO_STOP_BITS + + @return + This function does not return a value. + + Example: + @code + #include "mss_uart.h" + + int main(void) + { + MSS_UART_lin_init(&g_mss_uart0, + MSS_UART_57600_BAUD, + MSS_UART_DATA_8_BITS | MSS_UART_NO_PARITY | MSS_UART_ONE_STOP_BIT); + + return(0); + } + @endcode + */ +void +MSS_UART_lin_init +( + mss_uart_instance_t* this_uart, + uint32_t baud_rate, + uint8_t line_config +); + +/***************************************************************************//** + The MSS_UART_irda_init() function is used to initialize the MSS UART instance + referenced by the parameter this_uart for IrDA mode of operation. This + function must be called before calling any other IrDA functionality specific + functions. + + @param this_uart + The this_uart parameter is a pointer to an mss_uart_instance_t + structure identifying the MSS UART hardware block that will perform + the requested function. There are two such data structures, + g_mss_uart0 and g_mss_uart1, associated with MSS UART0 and MSS UART1. + This parameter must point to either the g_mss_uart0 or g_mss_uart1 + global data structure defined within the UART driver. + + @param baud_rate + The baud_rate parameter specifies the baud rate. It can be specified for + common baud rates� using the following defines: + � MSS_UART_110_BAUD + � MSS_UART_300_BAUD + � MSS_UART_1200_BAUD + � MSS_UART_2400_BAUD + � MSS_UART_4800_BAUD + � MSS_UART_9600_BAUD + � MSS_UART_19200_BAUD + � MSS_UART_38400_BAUD + � MSS_UART_57600_BAUD + � MSS_UART_115200_BAUD + � MSS_UART_230400_BAUD + � MSS_UART_460800_BAUD + � MSS_UART_921600_BAUD + Alternatively, any nonstandard baud rate can be specified by simply passing + the actual required baud rate as the value for this parameter. + + @param line_config + The line_config parameter is the line configuration specifying the bit length, + number of stop bits and parity settings. This is a bitwise OR of one value + from each of the following groups of allowed values: + � One of the following to specify the transmit/receive data bit length: + MSS_UART_DATA_5_BITS + MSS_UART_DATA_6_BITS, + MSS_UART_DATA_7_BITS + MSS_UART_DATA_8_BITS + � One of the following to specify the parity setting: + MSS_UART_NO_PARITY + MSS_UART_EVEN_PARITY + MSS_UART_ODD_PARITY + MSS_UART_STICK_PARITY_0 + MSS_UART_STICK_PARITY_1 + � One of the following to specify the number of stop bits: + MSS_UART_ONE_STOP_BIT + MSS_UART_ONEHALF_STOP_BIT + MSS_UART_TWO_STOP_BITS + + @return + This function does not return a value. + + Example: + @code + MSS_UART_irda_init(&g_mss_uart0, + MSS_UART_57600_BAUD, + MSS_UART_DATA_8_BITS | MSS_UART_NO_PARITY | MSS_UART_ONE_STOP_BIT, + MSS_UART_ACTIVE_LOW, + MSS_UART_ACTIVE_LOW, + MSS_UART_3_BY_16); + @endcode + */ +void +MSS_UART_irda_init +( + mss_uart_instance_t* this_uart, + uint32_t baud_rate, + uint8_t line_config, + mss_uart_rzi_polarity_t rxpol, + mss_uart_rzi_polarity_t txpol, + mss_uart_rzi_pulsewidth_t pw +); + +/***************************************************************************//** + The MSS_UART_smartcard_init() function is used to initialize the MSS UART + for ISO 7816 (smartcard) mode of operation. The configuration parameters are + the baud_rate which is used to generate the baud value and the line_config + which is used to specify the line configuration (bit length, stop bits and parity). + This function disables all other modes of the MSS UART instance pointed by + the parameter this_uart. + + @param this_uart + The this_uart parameter is a pointer to an mss_uart_instance_t + structure identifying the MSS UART hardware block that will perform + the requested function. There are two such data structures, + g_mss_uart0 and g_mss_uart1, associated with MSS UART0 and MSS UART1. + This parameter must point to either the g_mss_uart0 or g_mss_uart1 + global data structure defined within the UART driver. + + @param baud_rate + The baud_rate parameter specifies the baud rate. It can be specified for + common baud rates� using the following defines: + � MSS_UART_110_BAUD + � MSS_UART_300_BAUD + � MSS_UART_1200_BAUD + � MSS_UART_2400_BAUD + � MSS_UART_4800_BAUD + � MSS_UART_9600_BAUD + � MSS_UART_19200_BAUD + � MSS_UART_38400_BAUD + � MSS_UART_57600_BAUD + � MSS_UART_115200_BAUD + � MSS_UART_230400_BAUD + � MSS_UART_460800_BAUD + � MSS_UART_921600_BAUD + Alternatively, any nonstandard baud rate can be specified by simply passing + the actual required baud rate as the value for this parameter. + + @param line_config + The line_config parameter is the line configuration specifying the bit length, + number of stop bits and parity settings. This is a bitwise OR of one value + from each of the following groups of allowed values: + � One of the following to specify the transmit/receive data bit length: + MSS_UART_DATA_5_BITS + MSS_UART_DATA_6_BITS, + MSS_UART_DATA_7_BITS + MSS_UART_DATA_8_BITS + � One of the following to specify the parity setting: + MSS_UART_NO_PARITY + MSS_UART_EVEN_PARITY + MSS_UART_ODD_PARITY + MSS_UART_STICK_PARITY_0 + MSS_UART_STICK_PARITY_1 + � One of the following to specify the number of stop bits: + MSS_UART_ONE_STOP_BIT + MSS_UART_ONEHALF_STOP_BIT + MSS_UART_TWO_STOP_BITS + + @return + This function does not return a value. + + Example: + @code + #include "mss_uart.h" + + int main(void) + { + MSS_UART_smartcard_init(&g_mss_uart0, + MSS_UART_57600_BAUD, + MSS_UART_DATA_8_BITS | MSS_UART_NO_PARITY | MSS_UART_ONE_STOP_BIT); + + return(0); + } + @endcode + */ +void +MSS_UART_smartcard_init +( + mss_uart_instance_t* this_uart, + uint32_t baud_rate, + uint8_t line_config +); + +/***************************************************************************//** + The function MSS_UART_polled_tx() is used to transmit data. It transfers the + contents of the transmitter data buffer, passed as a function parameter, into + the UART�s hardware transmitter FIFO. It returns when the full content of the + transmit data buffer has been transferred to the UART�s transmit FIFO. It is + safe to release or reuse the memory used as the transmitter data buffer once + this function returns. + + Note: This function reads the UART�s line status register (LSR) to poll + for the active state of the transmitter holding register empty (THRE) bit + before transferring data from the data buffer to the transmitter FIFO. It + transfers data to the transmitter FIFO in blocks of 16 bytes or less and + allows the FIFO to empty before transferring the next block of data. + + Note: The actual transmission over the serial connection will still be + in progress when this function returns. Use the MSS_UART_get_tx_status() + function if you need to know when the transmitter is empty. + + @param this_uart + The this_uart parameter is a pointer to an mss_uart_instance_t + structure identifying the MSS UART hardware block that will perform + the requested function. There are two such data structures, + g_mss_uart0 and g_mss_uart1, associated with MSS UART0 and MSS UART1. + This parameter must point to either the g_mss_uart0 or g_mss_uart1 + global data structure defined within the UART driver. + + @param pbuff + The pbuff parameter is a pointer to a buffer containing the data to + be transmitted. + + @param tx_size + The tx_size parameter specifies the size, in bytes, of the data to + be transmitted. + + @return + This function does not return a value. + + Example: + @code + #include "mss_uart.h" + + int main(void) + { + uint8_t message[12] = "Hello World"; + + MSS_UART_init(&g_mss_uart0, + MSS_UART_57600_BAUD, + MSS_UART_DATA_8_BITS | MSS_UART_NO_PARITY | MSS_UART_ONE_STOP_BIT); + + MSS_UART_polled_tx(&g_mss_uart0, message, sizeof(message)); + + return(0); + } + @endcode + */ +void +MSS_UART_polled_tx +( + mss_uart_instance_t * this_uart, + const uint8_t * pbuff, + uint32_t tx_size +); + +/***************************************************************************//** + The function MSS_UART_polled_tx_string() is used to transmit a NULL ('\0') + terminated string. It transfers the text string, from the buffer starting at + the address pointed to by p_sz_string into the UART�s hardware transmitter + FIFO. It returns when the complete string has been transferred to the UART's + transmit FIFO. It is safe to release or reuse the memory used as the string + buffer once this function returns. + + Note: This function reads the UART�s line status register (LSR) to poll + for the active state of the transmitter holding register empty (THRE) bit + before transferring data from the data buffer to the transmitter FIFO. It + transfers data to the transmitter FIFO in blocks of 16 bytes or less and + allows the FIFO to empty before transferring the next block of data. + + Note: The actual transmission over the serial connection will still be + in progress when this function returns. Use the MSS_UART_get_tx_status() + function if you need to know when the transmitter is empty. + + @param this_uart + The this_uart parameter is a pointer to an mss_uart_instance_t + structure identifying the MSS UART hardware block that will perform + the requested function. There are two such data structures, + g_mss_uart0 and g_mss_uart1, associated with MSS UART0 and MSS UART1. + This parameter must point to either the g_mss_uart0 or g_mss_uart1 + global data structure defined within the UART driver. + + @param p_sz_string + The p_sz_string parameter is a pointer to a buffer containing the NULL + ('\0') terminated string to be transmitted. + + @return + This function does not return a value. + + Example: + @code + #include "mss_uart.h" + + int main(void) + { + uint8_t message[12] = "Hello World"; + + MSS_UART_init(&g_mss_uart0, + MSS_UART_57600_BAUD, + MSS_UART_DATA_8_BITS | MSS_UART_NO_PARITY | MSS_UART_ONE_STOP_BIT); + + MSS_UART_polled_tx_string(&g_mss_uart0, message); + + return(0); + } + @endcode + + */ +void +MSS_UART_polled_tx_string +( + mss_uart_instance_t * this_uart, + const uint8_t * p_sz_string +); + + +/***************************************************************************//** + The function MSS_UART_irq_tx() is used to initiate an interrupt-driven + transmit. It returns immediately after making a note of the transmit buffer + location and enabling transmit interrupts both at the UART and Cortex-M3 NVIC + level. This function takes a pointer via the pbuff parameter to a memory + buffer containing the data to transmit. The memory buffer specified through + this pointer must remain allocated and contain the data to transmit until + the transmit completion has been detected through calls to function + MSS_UART_tx_complete(). The actual transmission over the serial connection + is still in progress until calls to the MSS_UART_tx_complete() function + indicate transmit completion. + + Note: The MSS_UART_irq_tx() function enables both the transmit holding + register empty (THRE) interrupt in the UART and the MSS UART instance + interrupt in the Cortex-M3 NVIC as part of its implementation. + + Note: The MSS_UART_irq_tx() function assigns an internal default transmit + interrupt handler function to the UART�s THRE interrupt. This interrupt + handler overrides any custom interrupt handler that you may have previously + registered using the MSS_UART_set_tx_handler() function. + + Note: The MSS_UART_irq_tx() function�s default transmit interrupt + handler disables the UART�s THRE interrupt when all of the data has + been transferred to the UART's transmit FIFO. + + + @param this_uart + The this_uart parameter is a pointer to an mss_uart_instance_t + structure identifying the MSS UART hardware block that will perform + the requested function. There are two such data structures, + g_mss_uart0 and g_mss_uart1, associated with MSS UART0 and MSS UART1. + This parameter must point to either the g_mss_uart0 or g_mss_uart1 + global data structure defined within the UART driver. + + @param pbuff + The pbuff parameter is a pointer to a buffer containing the data + to be transmitted. + + @param tx_size + The tx_size parameter specifies the size, in bytes, of the data + to be transmitted. + + @return + This function does not return a value. + + Example: + @code + #include "mss_uart.h" + + int main(void) + { + uint8_t tx_buff[10] = "abcdefghi"; + + MSS_UART_init(&g_mss_uart0, + MSS_UART_57600_BAUD, + MSS_UART_DATA_8_BITS | MSS_UART_NO_PARITY | MSS_UART_ONE_STOP_BIT); + + MSS_UART_irq_tx(&g_mss_uart0, tx_buff, sizeof(tx_buff)); + + while(0 == MSS_UART_tx_complete(&g_mss_uart0)) + { + ; + } + return(0); + } + @endcode + */ +void +MSS_UART_irq_tx +( + mss_uart_instance_t * this_uart, + const uint8_t * pbuff, + uint32_t tx_size +); + +/***************************************************************************//** + The MSS_UART_tx_complete() function is used to find out if the interrupt-driven + transmit previously initiated through a call to MSS_UART_irq_tx() is complete. + This is typically used to find out when it is safe to reuse or release the + memory buffer holding transmit data. + + Note: The transfer of all of the data from the memory buffer to the UART�s + transmit FIFO and the actual transmission over the serial connection are both + complete when a call to the MSS_UART_tx_complete() function indicates transmit + completion. + + @param this_uart + The this_uart parameter is a pointer to an mss_uart_instance_t + structure identifying the MSS UART hardware block that will perform + the requested function. There are two such data structures, + g_mss_uart0 and g_mss_uart1, associated with MSS UART0 and MSS UART1. + This parameter must point to either the g_mss_uart0 or g_mss_uart1 + global data structure defined within the UART driver. + + @return + This function return a non-zero value if transmit has completed, otherwise + it returns zero. + + Example: + See the MSS_UART_irq_tx() function for an example that uses the + MSS_UART_tx_complete() function. + */ +int8_t +MSS_UART_tx_complete +( + mss_uart_instance_t * this_uart +); + +/***************************************************************************//** + The MSS_UART_get_rx() function reads the content of the UART receiver�s FIFO + and stores it in the receive buffer that is passed via the rx_buff function + parameter. It copies either the full contents of the FIFO into the receive + buffer, or just enough data from the FIFO to fill the receive buffer, + dependent upon the size of the receive buffer passed by the buff_size + parameter. The MSS_UART_get_rx() function returns the number of bytes copied + into the receive buffer .This function is non-blocking and will return 0 + immediately if no data has been received. + + Note: The MSS_UART_get_rx() function reads and accumulates the receiver + status of the MSS UART instance before reading each byte from the receiver's + data register/FIFO. This allows the driver to maintain a sticky record of any + receiver errors that occur as the UART receives each data byte; receiver + errors would otherwise be lost after each read from the receiver's data register. + A call to the MSS_UART_get_rx_status() function returns any receiver errors + accumulated during the execution of the MSS_UART_get_rx() function. + + Note: If you need to read the error status for each byte received, set + the buff_size to 1 and read the receive line error status for each byte + using the MSS_UART_get_rx_status() function. + The MSS_UART_get_rx() function can be used in polled mode, where it is called + at regular intervals to find out if any data has been received, or in interrupt + driven-mode, where it is called as part of a receive handler that is called + by the driver as a result of data being received. + + Note: In interrupt driven mode you should call the MSS_UART_get_rx() + function as part of the receive handler function that you register with + the MSS UART driver through a call to MSS_UART_set_rx_handler(). + + @param this_uart + The this_uart parameter is a pointer to an mss_uart_instance_t + structure identifying the MSS UART hardware block that will perform + the requested function. There are two such data structures, + g_mss_uart0 and g_mss_uart1, associated with MSS UART0 and MSS UART1. + This parameter must point to either the g_mss_uart0 or g_mss_uart1 + global data structure defined within the UART driver. + + @param rx_buff + The rx_buff parameter is a pointer to a buffer where the received + data is copied. + + @param buff_size + The buff_size parameter specifies the size of the receive buffer in bytes. + + @return + This function returns the number of bytes that were copied into the + rx_buff buffer. It returns 0 if no data has been received. + + Polled mode example: + @code + int main( void ) + { + uint8_t rx_buff[RX_BUFF_SIZE]; + uint32_t rx_idx = 0; + + MSS_UART_init(&g_mss_uart0, + MSS_UART_57600_BAUD, + MSS_UART_DATA_8_BITS | MSS_UART_NO_PARITY | MSS_UART_ONE_STOP_BIT); + + while(1) + { + rx_size = MSS_UART_get_rx(&g_mss_uart0, rx_buff, sizeof(rx_buff)); + if(rx_size > 0) + { + process_rx_data(rx_buff, rx_size); + } + task_a(); + task_b(); + } + return 0; + } + @endcode + + Interrupt driven example: + @code + int main( void ) + { + MSS_UART_init(&g_mss_uart1, + MSS_UART_57600_BAUD, + MSS_UART_DATA_8_BITS | MSS_UART_NO_PARITY | MSS_UART_ONE_STOP_BIT); + + MSS_UART_set_rx_handler(&g_mss_uart1, + uart1_rx_handler, + MSS_UART_FIFO_SINGLE_BYTE); + + while(1) + { + task_a(); + task_b(); + } + return 0; + } + + void uart1_rx_handler(mss_uart_instance_t * this_uart) + { + uint8_t rx_buff[RX_BUFF_SIZE]; + uint32_t rx_idx = 0; + rx_size = MSS_UART_get_rx(this_uart, rx_buff, sizeof(rx_buff)); + process_rx_data(rx_buff, rx_size); + } + @endcode + */ +size_t +MSS_UART_get_rx +( + mss_uart_instance_t * this_uart, + uint8_t * rx_buff, + size_t buff_size +); + +/***************************************************************************//** + The MSS_UART_set_rx_handler() function is used to register a receive handler + function that is called by the driver when a UART receive data available (RDA) + interrupt occurs. You must create and register the receive handler function + to suit your application and it must include a call to the MSS_UART_get_rx() + function to actually read the received data. + + Note: The MSS_UART_set_rx_handler() function enables both the RDA + interrupt in the UART and the MSS UART instance interrupt in the Cortex-M3 + NVIC as part + of its implementation. + + Note: You can disable the RDA interrupt once the data is received by + calling the MSS_UART_disable_irq() function. This is your choice and is + dependent upon your application. + + + @param this_uart + The this_uart parameter is a pointer to an mss_uart_instance_t + structure identifying the MSS UART hardware block that will perform + the requested function. There are two such data structures, + g_mss_uart0 and g_mss_uart1, associated with MSS UART0 and MSS UART1. + This parameter must point to either the g_mss_uart0 or g_mss_uart1 + global data structure defined within the UART driver. + + @param handler + The handler parameter is a pointer to a receive interrupt handler function + provided by your application that will be called as a result of a UART RDA + interrupt. This handler function must be of type mss_uart_irq_handler_t. + + @param trigger_level + The trigger_level parameter is the receive FIFO trigger level. This + specifies the number of bytes that must be received before the UART + triggers an RDA interrupt. + + @return + This function does not return a value. + + Example: + @code + #include "mss_uart.h" + + #define RX_BUFF_SIZE 64 + + uint8_t g_rx_buff[RX_BUFF_SIZE]; + + void uart0_rx_handler(mss_uart_instance_t * this_uart) + { + MSS_UART_get_rx(this_uart, &g_rx_buff[g_rx_idx], sizeof(g_rx_buff)); + } + + int main(void) + { + MSS_UART_init(&g_mss_uart0, + MSS_UART_57600_BAUD, + MSS_UART_DATA_8_BITS | MSS_UART_NO_PARITY | MSS_UART_ONE_STOP_BIT); + + MSS_UART_set_rx_handler(&g_mss_uart0, + uart0_rx_handler, + MSS_UART_FIFO_SINGLE_BYTE); + + while(1) + { + ; + } + return(0); + } + @endcode + */ +void +MSS_UART_set_rx_handler +( + mss_uart_instance_t * this_uart, + mss_uart_irq_handler_t handler, + mss_uart_rx_trig_level_t trigger_level +); + +/***************************************************************************//** + The MSS_UART_set_loopback() function is used to locally loopback the Tx and + Rx lines of a UART. This is not to be confused with the loopback of UART0 + to UART1, which can be achieved through the microcontroller subsystem�s + system registers. + + @param this_uart + The this_uart parameter is a pointer to an mss_uart_instance_t + structure identifying the MSS UART hardware block that will perform + the requested function. There are two such data structures, + g_mss_uart0 and g_mss_uart1, associated with MSS UART0 and MSS UART1. + This parameter must point to either the g_mss_uart0 or g_mss_uart1 + global data structure defined within the UART driver. + + @param loopback + The loopback parameter indicates whether or not the UART�s transmit + and receive lines should be looped back. Allowed values are as follows: + - MSS_UART_LOCAL_LOOPBACK_ON + - MSS_UART_LOCAL_LOOPBACK_OFF + - MSS_UART_REMOTE_LOOPBACK_ON + - MSS_UART_REMOTE_LOOPBACK_OFF + - MSS_UART_AUTO_ECHO_ON + - MSS_UART_AUTO_ECHO_OFF + + @return + This function does not return a value. + + Example: + @code + MSS_UART_init(&g_mss_uart0, + MSS_UART_57600_BAUD, + MSS_UART_DATA_8_BITS | MSS_UART_NO_PARITY | MSS_UART_ONE_STOP_BIT); + + MSS_UART_set_loopback(&g_mss_uart0, MSS_UART_LOCAL_LOOPBACK_OFF); + @endcode + */ +void +MSS_UART_set_loopback +( + mss_uart_instance_t * this_uart, + mss_uart_loopback_t loopback +); + +/***************************************************************************//** + The MSS_UART_enable_irq() function enables the MSS UART interrupts specified + by the irq_mask parameter. The irq_mask parameter identifies the MSS UART + interrupts by bit position, as defined in the interrupt enable register (IER) + of MSS UART. The MSS UART interrupts and their identifying irq_mask bit + positions are as follows: + When an irq_mask bit position is set to 1, this function enables the + corresponding MSS UART interrupt in the IER register. When an irq_mask bit + position is set to 0, the corresponding interrupt�s state remains unchanged in + the IER register. + Note: The MSS_UART_enable_irq() function also enables the MSS UART instance + interrupt in the Cortex-M3 NVIC. + + @param this_uart + The this_uart parameter is a pointer to an mss_uart_instance_t structure + identifying the MSS UART hardware block that will perform the requested + function. There are two such data structures, g_mss_uart0 and g_mss_uart1, + associated with MSS UART0 and MSS UART1. This parameter must point to either + the g_mss_uart0 or g_mss_uart1 global data structure defined within the UART + driver. + + @param irq_mask + The irq_mask parameter is used to select which of the MSS UART�s interrupts + you want to enable. The allowed value for the irq_mask parameter is one of + the following constants or a bitwise OR of more than one: + - MSS_UART_RBF_IRQ (bit mask = 0x001) + - MSS_UART_TBE_IRQ (bit mask = 0x002) + - MSS_UART_LS_IRQ (bit mask = 0x004) + - MSS_UART_MS_IRQ (bit mask = 0x008) + - MSS_UART_RTO_IRQ (bit mask = 0x010) + - MSS_UART_NACK_IRQ (bit mask = 0x020) + - MSS_UART_PIDPE_IRQ (bit mask = 0x040) + - MSS_UART_LINB_IRQ (bit mask = 0x080) + - MSS_UART_LINS_IRQ (bit mask = 0x100) + + @return + This function does not return a value. + + Example: + @code + MSS_UART_enable_irq(&g_mss_uart0,(MSS_UART_RBF_IRQ | MSS_UART_TBE_IRQ)); + @endcode + */ +void +MSS_UART_enable_irq +( + mss_uart_instance_t * this_uart, + mss_uart_irq_t irq_mask +); + +/***************************************************************************//** + The MSS_UART_disable_irq() function disables the MSS UART interrupts specified + by the irq_mask parameter. The irq_mask parameter identifies the MSS UART + interrupts by bit position, as defined in the interrupt enable register (IER) + of MSS UART. The MSS UART interrupts and their identifying bit positions are + as follows: + When an irq_mask bit position is set to 1, this function disables the + corresponding MSS UART interrupt in the IER register. When an irq_mask bit + position is set to 0, the corresponding interrupt�s state remains unchanged in + the IER register. + Note: If you disable all four of the UART�s interrupts, the + MSS_UART_disable_irq() function also disables the MSS UART instance + interrupt in the Cortex-M3 NVIC. + + @param this_uart + The this_uart parameter is a pointer to an mss_uart_instance_t + structure identifying the MSS UART hardware block that will perform + the requested function. There are two such data structures, + g_mss_uart0 and g_mss_uart1, associated with MSS UART0 and MSS UART1. + This parameter must point to either the g_mss_uart0 or g_mss_uart1 + global data structure defined within the UART driver. + + @param irq_mask + The irq_mask parameter is used to select which of the MSS UART�s interrupts + you want to disable. The allowed value for the irq_mask parameter is one of + the following constants or a bitwise OR of more than one: + - MSS_UART_RBF_IRQ (bit mask = 0x001) + - MSS_UART_TBE_IRQ (bit mask = 0x002) + - MSS_UART_LS_IRQ (bit mask = 0x004) + - MSS_UART_MS_IRQ (bit mask = 0x008) + - MSS_UART_RTO_IRQ (bit mask = 0x010) + - MSS_UART_NACK_IRQ (bit mask = 0x020) + - MSS_UART_PIDPE_IRQ (bit mask = 0x040) + - MSS_UART_LINB_IRQ (bit mask = 0x080) + - MSS_UART_LINS_IRQ (bit mask = 0x100) + + @return + This function does not return a value. + + Example: + @code + MSS_UART_disable_irq(&g_mss_uart0, (MSS_UART_RBF_IRQ | MSS_UART_TBE_IRQ)); + @endcode + */ +void +MSS_UART_disable_irq +( + mss_uart_instance_t * this_uart, + mss_uart_irq_t irq_mask +); + +/***************************************************************************//** + The MSS_UART_set_pidpei_handler() function is used assign a custom interrupt + handler for the PIDPEI (PID parity error interrupt) when the MSS UART is + operating in LIN mode. + + @param this_uart + The this_uart parameter is a pointer to an mss_uart_instance_t + structure identifying the MSS UART hardware block that will perform + the requested function. There are two such data structures, + g_mss_uart0 and g_mss_uart1, associated with MSS UART0 and MSS UART1. + This parameter must point to either the g_mss_uart0 or g_mss_uart1 + global data structure defined within the UART driver. + + @param handler + The handler parameter is the pointer to the custom handler function. + This parameter is of type mss_uart_irq_handler_t. + + @return + This function does not return a value. + + Example: + @code + MSS_UART_ set_pidpei_handler(&g_mss_uart0, my_pidpei_handler); + @endcode + */ +void +MSS_UART_set_pidpei_handler +( + mss_uart_instance_t * this_uart, + mss_uart_irq_handler_t handler +); + +/***************************************************************************//** + The MSS_UART_set_linbreak_handler () function is used assign a custom + interrupt handler for the LIN Break detection interrupt when the MSS UART + is operating in LIN mode. + + @param this_uart + The this_uart parameter is a pointer to an mss_uart_instance_t + structure identifying the MSS UART hardware block that will perform + the requested function. There are two such data structures, + g_mss_uart0 and g_mss_uart1, associated with MSS UART0 and MSS UART1. + This parameter must point to either the g_mss_uart0 or g_mss_uart1 + global data structure defined within the UART driver. + + @param handler + The handler parameter is the pointer to the custom handler function. + This parameter is of type mss_uart_irq_handler_t. + + @return + This function does not return a value. + Example: + @code + MSS_UART_set_linbreak_handler(&g_mss_uart0, my_break_handler); + @endcode + */ +void +MSS_UART_set_linbreak_handler +( + mss_uart_instance_t * this_uart, + mss_uart_irq_handler_t handler +); + +/***************************************************************************//** + The MSS_UART_set_linsync_handler() function is used assign a custom interrupt + handler for the LIN Sync character detection interrupt when the MSS UART + is operating in LIN mode. + + @param this_uart + The this_uart parameter is a pointer to an mss_uart_instance_t + structure identifying the MSS UART hardware block that will perform + the requested function. There are two such data structures, + g_mss_uart0 and g_mss_uart1, associated with MSS UART0 and MSS UART1. + This parameter must point to either the g_mss_uart0 or g_mss_uart1 + global data structure defined within the UART driver. + + @param handler + The handler parameter is the pointer to the custom handler function. + This parameter is of type mss_uart_irq_handler_t. + + @return + This function does not return a value. + Example: + @code + MSS_UART_set_linsync_handler(&g_mss_uart0, my_linsync_handler); + @endcode + */ +void +MSS_UART_set_linsync_handler +( + mss_uart_instance_t * this_uart, + mss_uart_irq_handler_t handler +); + +/***************************************************************************//** + The MSS_UART_set_nack_handler() function is used assign a custom interrupt + handler for the NACK character detection interrupt when the MSS UART + is operating in Smartcard mode. + + @param this_uart + The this_uart parameter is a pointer to an mss_uart_instance_t + structure identifying the MSS UART hardware block that will perform + the requested function. There are two such data structures, + g_mss_uart0 and g_mss_uart1, associated with MSS UART0 and MSS UART1. + This parameter must point to either the g_mss_uart0 or g_mss_uart1 + global data structure defined within the UART driver. + + @param handler + The handler parameter is the pointer to the custom handler function. + This parameter is of type mss_uart_irq_handler_t. + + @return + This function does not return a value. + Example: + @code + MSS_UART_set_nack_handler(&g_mss_uart0, my_nack_handler); + @endcode + */ +void +MSS_UART_set_nack_handler +( + mss_uart_instance_t * this_uart, + mss_uart_irq_handler_t handler +); + +/***************************************************************************//** + The MSS_UART_set_rx_timeout_handler() function is used assign a custom + interrupt handler for the receiver timeout interrupt when the MSS UART is + operating in mode. It finds application in IrDA mode of operation. + + @param this_uart + The this_uart parameter is a pointer to an mss_uart_instance_t + structure identifying the MSS UART hardware block that will perform + the requested function. There are two such data structures, + g_mss_uart0 and g_mss_uart1, associated with MSS UART0 and MSS UART1. + This parameter must point to either the g_mss_uart0 or g_mss_uart1 + global data structure defined within the UART driver. + + @param handler + The handler parameter is the pointer to the custom handler function. + This parameter is of type mss_uart_irq_handler_t. + + @return + This function does not return a value. + Example: + @code + MSS_UART_set_rx_timeout_handler(&g_mss_uart0, my_rxtimeout_handler); + @endcode + */ +void +MSS_UART_set_rx_timeout_handler +( + mss_uart_instance_t * this_uart, + mss_uart_irq_handler_t handler +); + +/***************************************************************************//** + The MSS_UART_set_rxstatus_handler() function is used to register a receiver + status handler function that is called by the driver when a UART receiver + line status (RLS) interrupt occurs. You must create and register the handler + function to suit your application. + + Note: The MSS_UART_set_rxstatus_handler() function enables both the RLS + interrupt in the UART and the MSS UART instance interrupt in the Cortex-M3 + NVIC as part of its implementation. + + Note: You can disable the RLS interrupt when required by calling the + MSS_UART_disable_irq() function. This is your choice and is dependent upon + your application. + + @param this_uart + The this_uart parameter is a pointer to an mss_uart_instance_t + structure identifying the MSS UART hardware block that will perform + the requested function. There are two such data structures, + g_mss_uart0 and g_mss_uart1, associated with MSS UART0 and MSS UART1. + This parameter must point to either the g_mss_uart0 or g_mss_uart1 + global data structure defined within the UART driver. + + @param handler + The handler parameter is a pointer to a receiver line status interrupt + handler function provided by your application that will be called as a + result of a UART RLS interrupt. This handler function must be of type + mss_uart_irq_handler_t. + + @return + This function does not return a value. + + Example: + @code + #include "mss_uart.h" + + void uart_rxsts_handler(mss_uart_instance_t * this_uart) + { + uint8_t status; + status = MSS_UART_get_rx_status(this_uart); + if(status & MSS_UART_OVERUN_ERROR) + { + discard_rx_data(); + } + } + + int main(void) + { + MSS_UART_init( &g_mss_uart0, + MSS_UART_57600_BAUD, + MSS_UART_DATA_8_BITS | MSS_UART_NO_PARITY | + MSS_UART_ONE_STOP_BIT ); + + MSS_UART_set_rxstatus_handler(&g_mss_uart0, uart_rxsts_handler); + + while(1) + { + ; + } + return(0); + } + @endcode + */ +void +MSS_UART_set_rxstatus_handler +( + mss_uart_instance_t * this_uart, + mss_uart_irq_handler_t handler +); + +/***************************************************************************//** + The MSS_UART_set_tx_handler() function is used to register a transmit handler + function that is called by the driver when a UART transmit holding register + empty (THRE) interrupt occurs. You must create and register the transmit + handler function to suit your application. You can use the + MSS_UART_fill_tx_fifo() function in your transmit handler function to + write data to the transmitter. + + Note: The MSS_UART_set_tx_handler() function enables both the THRE + interrupt in the UART and the MSS UART instance interrupt in the Cortex-M3 + NVIC as part of its implementation. + + Note: You can disable the THRE interrupt when required by calling the + MSS_UART_disable_irq() function. This is your choice and is dependent upon + your application. + + Note: The MSS_UART_irq_tx() function does not use the transmit handler + function that you register with the MSS_UART_set_tx_handler() function. + It uses its own internal THRE interrupt handler function that overrides + any custom interrupt handler that you register using the + MSS_UART_set_tx_handler() function. + + @param this_uart + The this_uart parameter is a pointer to an mss_uart_instance_t + structure identifying the MSS UART hardware block that will perform + the requested function. There are two such data structures, + g_mss_uart0 and g_mss_uart1, associated with MSS UART0 and MSS UART1. + This parameter must point to either the g_mss_uart0 or g_mss_uart1 + global data structure defined within the UART driver. + + @param handler + The handler parameter is a pointer to a transmit interrupt handler + function provided by your application that will be called as a result + of a UART THRE interrupt. This handler function must be of type + mss_uart_irq_handler_t. + + @return + This function does not return a value. + + Example: + @code + #include "mss_uart.h" + + uint8_t * g_tx_buffer; + size_t g_tx_size = 0; + + void uart_tx_handler(mss_uart_instance_t * this_uart) + { + size_t size_in_fifo; + size_in_fifo = MSS_UART_fill_tx_fifo(this_uart, + (const uint8_t *)g_tx_buffer, + g_tx_size); + + if(size_in_fifo == g_tx_size) + { + g_tx_size = 0; + MSS_UART_disable_irq(this_uart, MSS_UART_TBE_IRQ); + } + else + { + g_tx_buffer = &g_tx_buffer[size_in_fifo]; + g_tx_size = g_tx_size - size_in_fifo; + } + } + + int main(void) + { + uint8_t message[12] = "Hello world"; + + MSS_UART_init(&g_mss_uart0, + MSS_UART_57600_BAUD, + MSS_UART_DATA_8_BITS | MSS_UART_NO_PARITY | + MSS_UART_ONE_STOP_BIT); + + g_tx_buffer = message; + g_tx_size = sizeof(message); + + MSS_UART_set_tx_handler(&g_mss_uart0, uart_tx_handler); + + while(1) + { + ; + } + return(0); + } + @endcode + */ +void +MSS_UART_set_tx_handler +( + mss_uart_instance_t * this_uart, + mss_uart_irq_handler_t handler +); + +/***************************************************************************//** + The MSS_UART_set_modemstatus_handler() function is used to register a modem + status handler function that is called by the driver when a UART modem status + (MS) interrupt occurs. You must create and register the handler function to + suit your application. + + Note: The MSS_UART_set_modemstatus_handler() function enables both the MS + interrupt in the UART and the MSS UART instance interrupt in the Cortex-M3 NVIC + as part of its implementation. + + Note: You can disable the MS interrupt when required by calling the + MSS_UART_disable_irq() function. This is your choice and is dependent + upon your application. + + @param this_uart + The this_uart parameter is a pointer to an mss_uart_instance_t + structure identifying the MSS UART hardware block that will perform + the requested function. There are two such data structures, + g_mss_uart0 and g_mss_uart1, associated with MSS UART0 and MSS UART1. + This parameter must point to either the g_mss_uart0 or g_mss_uart1 + global data structure defined within the UART driver. + + @param handler + The handler parameter is a pointer to a modem status interrupt handler + function provided by your application that will be called as a result + of a UART MS interrupt. This handler function must be of type + mss_uart_irq_handler_t. + + @return + This function does not return a value. + + Example: + @code + #include "mss_uart.h" + + void uart_modem_handler(mss_uart_instance_t * this_uart) + { + uint8_t status; + status = MSS_UART_get_modem_status(this_uart); + if(status & MSS_UART_CTS) + { + uart_cts_handler(); + } + } + + int main(void) + { + MSS_UART_init(&g_mss_uart0, + MSS_UART_57600_BAUD, + MSS_UART_DATA_8_BITS | MSS_UART_NO_PARITY | + MSS_UART_ONE_STOP_BIT); + MSS_UART_set_modemstatus_handler(&g_mss_uart0, uart_modem_handler); + + while(1) + { + ; + } + return(0); + } + @endcode + */ + +void +MSS_UART_set_modemstatus_handler +( + mss_uart_instance_t * this_uart, + mss_uart_irq_handler_t handler +); + +/***************************************************************************//** + The MSS_UART_fill_tx_fifo() function fills the UART's hardware transmitter + FIFO with the data found in the transmitter buffer that is passed via the + tx_buffer function parameter. If the transmitter FIFO is not empty when + the function is called, the function returns immediately without transferring + any data to the FIFO; otherwise, the function transfers data from the + transmitter buffer to the FIFO until it is full or until the complete + contents of the transmitter buffer have been copied into the FIFO. The + function returns the number of bytes copied into the UART's transmitter FIFO. + + Note: This function reads the UART�s line status register (LSR) to check + for the active state of the transmitter holding register empty (THRE) bit + before transferring data from the data buffer to the transmitter FIFO. If + THRE is 0, the function returns immediately, without transferring any data + to the FIFO. If THRE is 1, the function transfers up to 16 bytes of data + to the FIFO and then returns. + + Note: The actual transmission over the serial connection will still be + in progress when this function returns. Use the MSS_UART_get_tx_status() + function if you need to know when the transmitter is empty. + + @param this_uart + The this_uart parameter is a pointer to an mss_uart_instance_t + structure identifying the MSS UART hardware block that will perform + the requested function. There are two such data structures, + g_mss_uart0 and g_mss_uart1, associated with MSS UART0 and MSS UART1. + This parameter must point to either the g_mss_uart0 or g_mss_uart1 + global data structure defined within the UART driver. + + @param tx_buffer + The tx_buffer parameter is a pointer to a buffer containing the data + to be transmitted. + + @param tx_size + The tx_size parameter is the size in bytes, of the data to be transmitted. + + @return + This function returns the number of bytes copied into the UART's + transmitter FIFO. + + Example: + @code + void send_using_interrupt(uint8_t * pbuff, size_t tx_size) + { + size_t size_in_fifo; + size_in_fifo = MSS_UART_fill_tx_fifo(&g_mss_uart0, pbuff, tx_size); + } + @endcode + */ +size_t +MSS_UART_fill_tx_fifo +( + mss_uart_instance_t * this_uart, + const uint8_t * tx_buffer, + size_t tx_size +); + +/***************************************************************************//** + The MSS_UART_get_rx_status() function returns the receiver error status of the + MSS UART instance. It reads both the current error status of the receiver from + the UART�s line status register (LSR) and the accumulated error status from + preceding calls to the MSS_UART_get_rx() function, and it combines them using + a bitwise OR. It returns the cumulative overrun, parity, framing, break and + FIFO error status of the receiver, since the previous call to + MSS_UART_get_rx_status(), as an 8-bit encoded value. + + Note: The MSS_UART_get_rx() function reads and accumulates the receiver + status of the MSS UART instance before reading each byte from the receiver�s + data register/FIFO. The driver maintains a sticky record of the cumulative + receiver error status, which persists after the MSS_UART_get_rx() function + returns. The MSS_UART_get_rx_status() function clears the driver�s sticky + receiver error record before returning. + + Note: The driver�s transmit functions also read the line status + register (LSR) as part of their implementation. When the driver reads the + LSR, the UART clears any active receiver error bits in the LSR. This could + result in the driver losing receiver errors. To avoid any loss of receiver + errors, the transmit functions also update the driver�s sticky record of the + cumulative receiver error status whenever they read the LSR. + + @param this_uart + The this_uart parameter is a pointer to an mss_uart_instance_t + structure identifying the MSS UART hardware block that will perform + the requested function. There are two such data structures, + g_mss_uart0 and g_mss_uart1, associated with MSS UART0 and MSS UART1. + This parameter must point to either the g_mss_uart0 or g_mss_uart1 + global data structure defined within the UART driver. + + @return + This function returns the UART�s receiver error status as an 8-bit unsigned + integer. The returned value is 0 if no receiver errors occurred. The driver + provides a set of bit mask constants that should be compared with and/or + used to mask the returned value to determine the receiver error status. + When the return value is compared to the following bit masks, a non-zero + result indicates that the corresponding error occurred: + � MSS_UART_OVERRUN_ERROR (bit mask = 0x02) + � MSS_UART_PARITY_ERROR (bit mask = 0x04) + � MSS_UART_FRAMING_ERROR (bit mask = 0x08) + � MSS_UART_BREAK_ERROR (bit mask = 0x10) + � MSS_UART_FIFO_ERROR (bit mask = 0x80) + When the return value is compared to the following bit mask, a non-zero + result indicates that no error occurred: + � MSS_UART_NO_ERROR (bit mask = 0x00) + Upon unsuccessful execution, this function returns: + � MSS_UART_INVALID_PARAM (bit mask = 0xFF) + + Example: + @code + uint8_t rx_data[MAX_RX_DATA_SIZE]; + uint8_t err_status; + err_status = MSS_UART_get_rx_status(&g_mss_uart0); + + if(MSS_UART_NO_ERROR == err_status) + { + rx_size = MSS_UART_get_rx(&g_mss_uart0, rx_data, MAX_RX_DATA_SIZE); + } + @endcode + */ +uint8_t +MSS_UART_get_rx_status +( + mss_uart_instance_t * this_uart +); + +/***************************************************************************//** + The MSS_UART_get_modem_status() function returns the modem status of the + MSS UART instance. It reads the modem status register (MSR) and returns + the 8 bit value. The bit encoding of the returned value is exactly the + same as the definition of the bits in the MSR. + + @param this_uart + The this_uart parameter is a pointer to an mss_uart_instance_t + structure identifying the MSS UART hardware block that will perform + the requested function. There are two such data structures, + g_mss_uart0 and g_mss_uart1, associated with MSS UART0 and MSS UART1. + This parameter must point to either the g_mss_uart0 or g_mss_uart1 + global data structure defined within the UART driver. + + @return + This function returns current state of the UART's MSR as an 8 bit + unsigned integer. The driver provides the following set of bit mask + constants that should be compared with and/or used to mask the + returned value to determine the modem status: + � MSS_UART_DCTS (bit mask = 0x01) + � MSS_UART_DDSR (bit mask = 0x02) + � MSS_UART_TERI (bit mask = 0x04) + � MSS_UART_DDCD (bit mask = 0x08) + � MSS_UART_CTS (bit mask = 0x10) + � MSS_UART_DSR (bit mask = 0x20) + � MSS_UART_RI (bit mask = 0x40) + � MSS_UART_DCD (bit mask = 0x80) + + Example: + @code + void uart_modem_status_isr(mss_uart_instance_t * this_uart) + { + uint8_t status; + status = MSS_UART_get_modem_status(this_uart); + if( status & MSS_UART_DCTS ) + { + uart_dcts_handler(); + } + if( status & MSS_UART_CTS ) + { + uart_cts_handler(); + } + } + @endcode + */ +uint8_t +MSS_UART_get_modem_status +( + mss_uart_instance_t * this_uart +); + +/***************************************************************************//** + The MSS_UART_get_tx_status() function returns the transmitter status of the + MSS UART instance. It reads both the UART�s line status register (LSR) and + returns the status of the transmit holding register empty (THRE) and + transmitter empty (TEMT) bits.* + + @param this_uart + The this_uart parameter is a pointer to an mss_uart_instance_t + structure identifying the MSS UART hardware block that will perform + the requested function. There are two such data structures, + g_mss_uart0 and g_mss_uart1, associated with MSS UART0 and MSS UART1. + This parameter must point to either the g_mss_uart0 or g_mss_uart1 + global data structure defined within the UART driver. + + @return + This function returns the UART�s transmitter status as an 8-bit unsigned + integer. The returned value is 0 if the transmitter status bits are not + set or the function execution failed. The driver provides a set of bit + mask constants that should be compared with and/or used to mask the + returned value to determine the transmitter status. + When the return value is compared to the following bit mask, a non-zero + result indicates that the corresponding transmitter status bit is set: + � MSS_UART_THRE (bit mask = 0x20) + � MSS_UART_TEMT (bit mask = 0x40) + When the return value is compared to the following bit mask, a non-zero + result indicates that the transmitter is busy or the function execution + failed. + � MSS_UART_TX_BUSY (bit mask = 0x00) + + Example: + @code + uint8_t tx_buff[10] = "abcdefghi"; + MSS_UART_init(&g_mss_uart0, + MSS_UART_57600_BAUD, + MSS_UART_DATA_8_BITS | MSS_UART_NO_PARITY | MSS_UART_ONE_STOP_BIT); + + MSS_UART_polled_tx(&g_mss_uart0, tx_buff, sizeof(tx_buff)); + + while(!(MSS_UART_TEMT & MSS_UART_get_tx_status(&g_mss_uart0))) + { + ; + } + @endcode + */ +uint8_t +MSS_UART_get_tx_status +( + mss_uart_instance_t * this_uart +); + +/***************************************************************************//** + The MSS_UART_set_break() function is used to send the break + (9 zeros after stop bit) signal on the TX line. This function can be used + only when the MSS UART is initialized in LIN mode by using MSS_UART_lin_init(). + + @param this_uart + The this_uart parameter is a pointer to an mss_uart_instance_t + structure identifying the MSS UART hardware block that will perform + the requested function. There are two such data structures, + g_mss_uart0 and g_mss_uart1, associated with MSS UART0 and MSS UART1. + This parameter must point to either the g_mss_uart0 or g_mss_uart1 + global data structure defined within the UART driver. + + @return + This function does not return a value. + + Example: + @code + MSS_UART_init(&g_mss_uart0, + MSS_UART_57600_BAUD, + MSS_UART_DATA_8_BITS | MSS_UART_NO_PARITY | MSS_UART_ONE_STOP_BIT); + + MSS_UART_set_break(&g_mss_uart0); + @endcode + */ +void +MSS_UART_set_break +( + mss_uart_instance_t * this_uart +); + +/***************************************************************************//** + The MSS_UART_clear_break() function is used to remove the break signal on the + TX line. This function can be used only when the MSS UART is initialized in + LIN mode by using MSS_UART_lin_init(). + + @param this_uart + The this_uart parameter is a pointer to an mss_uart_instance_t + structure identifying the MSS UART hardware block that will perform + the requested function. There are two such data structures, + g_mss_uart0 and g_mss_uart1, associated with MSS UART0 and MSS UART1. + This parameter must point to either the g_mss_uart0 or g_mss_uart1 + global data structure defined within the UART driver. + + @return + This function does not return a value. + + Example: + @code + MSS_UART_init(&g_mss_uart0, + MSS_UART_57600_BAUD, + MSS_UART_DATA_8_BITS | MSS_UART_NO_PARITY | MSS_UART_ONE_STOP_BIT); + + MSS_UART_clear_break(&g_mss_uart0); + @endcode + */ +void +MSS_UART_clear_break +( + mss_uart_instance_t * this_uart +); + +/***************************************************************************//** + The MSS_UART_enable_half_duplex() function is used to enable the half-duplex + (single wire) mode for the MSS UART. Though it finds application in Smartcard + mode, half-duplex mode can be used in other modes as well. + + @param this_uart + The this_uart parameter is a pointer to an mss_uart_instance_t + structure identifying the MSS UART hardware block that will perform + the requested function. There are two such data structures, + g_mss_uart0 and g_mss_uart1, associated with MSS UART0 and MSS UART1. + This parameter must point to either the g_mss_uart0 or g_mss_uart1 + global data structure defined within the UART driver. + + @return + This function does not return a value. + + Example: + @code + MSS_UART_init(&g_mss_uart0, + MSS_UART_57600_BAUD, + MSS_UART_DATA_8_BITS | MSS_UART_NO_PARITY | MSS_UART_ONE_STOP_BIT); + + MSS_UART_enable_half_duplex(&g_mss_uart0); + @endcode + */ +void +MSS_UART_enable_half_duplex +( + mss_uart_instance_t * this_uart +); + +/***************************************************************************//** + The MSS_UART_disable_half_duplex() function is used to disable the half-duplex + (single wire) mode for the MSS UART. Though it finds application in Smartcard + mode, half-duplex mode can be used in other modes as well. + + @param this_uart + The this_uart parameter is a pointer to an mss_uart_instance_t + structure identifying the MSS UART hardware block that will perform + the requested function. There are two such data structures, + g_mss_uart0 and g_mss_uart1, associated with MSS UART0 and MSS UART1. + This parameter must point to either the g_mss_uart0 or g_mss_uart1 + global data structure defined within the UART driver. + + @return + This function does not return a value. + + Example: + @code + MSS_UART_init(&g_mss_uart0, + MSS_UART_57600_BAUD, + MSS_UART_DATA_8_BITS | MSS_UART_NO_PARITY | MSS_UART_ONE_STOP_BIT); + + MSS_UART_disable_half_duplex(&g_mss_uart0); + @endcode + */ +void +MSS_UART_disable_half_duplex +( + mss_uart_instance_t * this_uart +); + +/***************************************************************************//** + The MSS_UART_set_rx_endian() function is used to configure the LSB first or + MSB first setting for MSS UART receiver + + @param this_uart + The this_uart parameter is a pointer to an mss_uart_instance_t + structure identifying the MSS UART hardware block that will perform + the requested function. There are two such data structures, + g_mss_uart0 and g_mss_uart1, associated with MSS UART0 and MSS UART1. + This parameter must point to either the g_mss_uart0 or g_mss_uart1 + global data structure defined within the UART driver. + + @param endian + The endian parameter tells the LSB first or MSB first configuration. + This parameter is of type mss_uart_endian_t. + + @return + This function does not return a value. + + Example: + @code + MSS_UART_init(&g_mss_uart0, + MSS_UART_57600_BAUD, + MSS_UART_DATA_8_BITS | MSS_UART_NO_PARITY | MSS_UART_ONE_STOP_BIT); + + MSS_UART_set_rx_endian(&g_mss_uart0, MSS_UART_LITTLEEND); + @endcode + */ +void +MSS_UART_set_rx_endian +( + mss_uart_instance_t * this_uart, + mss_uart_endian_t endian +); + +/***************************************************************************//** + The MSS_UART_set_tx_endian() function is used to configure the LSB first or + MSB first setting for MSS UART transmitter. + + @param this_uart + The this_uart parameter is a pointer to an mss_uart_instance_t + structure identifying the MSS UART hardware block that will perform + the requested function. There are two such data structures, + g_mss_uart0 and g_mss_uart1, associated with MSS UART0 and MSS UART1. + This parameter must point to either the g_mss_uart0 or g_mss_uart1 + global data structure defined within the UART driver. + + @param endian + The endian parameter tells the LSB first or MSB first configuration. + This parameter is of type mss_uart_endian_t. + + @return + This function does not return a value. + + Example: + @code + MSS_UART_init(&g_mss_uart0, + MSS_UART_57600_BAUD, + MSS_UART_DATA_8_BITS | MSS_UART_NO_PARITY | MSS_UART_ONE_STOP_BIT); + + MSS_UART_set_tx_endian(&g_mss_uart0, MSS_UART_LITTLEEND); + @endcode + */ +void +MSS_UART_set_tx_endian +( + mss_uart_instance_t * this_uart, + mss_uart_endian_t endian +); + +/***************************************************************************//** + The MSS_UART_set_filter_length () function is used to configure the glitch + filter length of the MSS UART. This should be configured in accordance with + the chosen baud rate. + + @param this_uart + The this_uart parameter is a pointer to an mss_uart_instance_t + structure identifying the MSS UART hardware block that will perform + the requested function. There are two such data structures, + g_mss_uart0 and g_mss_uart1, associated with MSS UART0 and MSS UART1. + This parameter must point to either the g_mss_uart0 or g_mss_uart1 + global data structure defined within the UART driver. + + @param length + The length parameter is of mss_uart_filter_length_t type that determines + the length of the glitch filter. + + @return + This function does not return a value. + + Example: + @code + MSS_UART_init(&g_mss_uart0, + MSS_UART_57600_BAUD, + MSS_UART_DATA_8_BITS | MSS_UART_NO_PARITY | MSS_UART_ONE_STOP_BIT); + + MSS_UART_set_filter_length(&g_mss_uart0, MSS_UART_LEN2); + @endcode + */ +void +MSS_UART_set_filter_length +( + mss_uart_instance_t * this_uart, + mss_uart_filter_length_t length +); + +/***************************************************************************//** + The MSS_UART_enable_afm() function is used to enable address flag detection + mode of the MSS UART + + @param this_uart + The this_uart parameter is a pointer to an mss_uart_instance_t + structure identifying the MSS UART hardware block that will perform + the requested function. There are two such data structures, + g_mss_uart0 and g_mss_uart1, associated with MSS UART0 and MSS UART1. + This parameter must point to either the g_mss_uart0 or g_mss_uart1 + global data structure defined within the UART driver. + + @return + This function does not return a value. + + Example: + @code + MSS_UART_init(&g_mss_uart0, + MSS_UART_57600_BAUD, + MSS_UART_DATA_8_BITS | MSS_UART_NO_PARITY | MSS_UART_ONE_STOP_BIT); + + MSS_UART_enable_afm(&g_mss_uart0); + @endcode + */ +void +MSS_UART_enable_afm +( + mss_uart_instance_t * this_uart +); + +/***************************************************************************//** + The MSS_UART_disable_afm() function is used to disable address flag detection + mode of the MSS UART. + + @param this_uart + The this_uart parameter is a pointer to an mss_uart_instance_t + structure identifying the MSS UART hardware block that will perform + the requested function. There are two such data structures, + g_mss_uart0 and g_mss_uart1, associated with MSS UART0 and MSS UART1. + This parameter must point to either the g_mss_uart0 or g_mss_uart1 + global data structure defined within the UART driver. + + @return + This function does not return a value. + + Example: + @code + MSS_UART_init(&g_mss_uart0, + MSS_UART_57600_BAUD, + MSS_UART_DATA_8_BITS | MSS_UART_NO_PARITY | MSS_UART_ONE_STOP_BIT); + + MSS_UART_disable_afm(&g_mss_uart0); + @endcode + */ +void +MSS_UART_disable_afm +( + mss_uart_instance_t * this_uart +); + +/***************************************************************************//** + The MSS_UART_enable_afclear () function is used to enable address flag clear + of the MSS UART. This should be used in conjunction with address flag + detection mode (AFM). + + @param this_uart + The this_uart parameter is a pointer to an mss_uart_instance_t + structure identifying the MSS UART hardware block that will perform + the requested function. There are two such data structures, + g_mss_uart0 and g_mss_uart1, associated with MSS UART0 and MSS UART1. + This parameter must point to either the g_mss_uart0 or g_mss_uart1 + global data structure defined within the UART driver. + + @return + This function does not return a value. + + Example: + @code + MSS_UART_init(&g_mss_uart0, + MSS_UART_57600_BAUD, + MSS_UART_DATA_8_BITS | MSS_UART_NO_PARITY | MSS_UART_ONE_STOP_BIT); + + MSS_UART_enable_afclear(&g_mss_uart0); + @endcode + */ +void +MSS_UART_enable_afclear +( + mss_uart_instance_t * this_uart +); + +/***************************************************************************//** + The MSS_UART_disable_afclear () function is used to disable address flag + clear of the MSS UART. This should be used in conjunction with address flag + detection mode (AFM). + + @param this_uart + The this_uart parameter is a pointer to an mss_uart_instance_t + structure identifying the MSS UART hardware block that will perform + the requested function. There are two such data structures, + g_mss_uart0 and g_mss_uart1, associated with MSS UART0 and MSS UART1. + This parameter must point to either the g_mss_uart0 or g_mss_uart1 + global data structure defined within the UART driver. + + @return + This function does not return a value. + + Example: + @code + MSS_UART_init(&g_mss_uart0, + MSS_UART_57600_BAUD, + MSS_UART_DATA_8_BITS | MSS_UART_NO_PARITY | MSS_UART_ONE_STOP_BIT); + + MSS_UART_disable_afclear(&g_mss_uart0); + @endcode + */ +void +MSS_UART_disable_afclear +( + mss_uart_instance_t * this_uart +); + +/***************************************************************************//** + The MSS_UART_enable_rx_timeout() function is used to enable and configure + the receiver timeout functionality of MSS UART. This function accepts the + timeout parameter and applies the timeout based up on the baud rate as per + the formula 4 x timeout x bit time. + + @param this_uart + The this_uart parameter is a pointer to an mss_uart_instance_t + structure identifying the MSS UART hardware block that will perform + the requested function. There are two such data structures, + g_mss_uart0 and g_mss_uart1, associated with MSS UART0 and MSS UART1. + This parameter must point to either the g_mss_uart0 or g_mss_uart1 + global data structure defined within the UART driver. + + @param timeout + The timeout parameter specifies the receiver timeout multiple. + It should be configured according to the baud rate in use. + + @return + This function does not return a value. + + Example: + @code + MSS_UART_init(&g_mss_uart0, + MSS_UART_57600_BAUD, + MSS_UART_DATA_8_BITS | MSS_UART_NO_PARITY | MSS_UART_ONE_STOP_BIT); + + MSS_UART_enable_rx_timeout(&g_mss_uart0 , 24); + @endcode + */ +void +MSS_UART_enable_rx_timeout +( + mss_uart_instance_t * this_uart, + uint8_t timeout +); + +/***************************************************************************//** + The MSS_UART_disable_rx_timeout() function is used to disable the receiver + timeout functionality of MSS UART. + + @param this_uart + The this_uart parameter is a pointer to an mss_uart_instance_t + structure identifying the MSS UART hardware block that will perform + the requested function. There are two such data structures, + g_mss_uart0 and g_mss_uart1, associated with MSS UART0 and MSS UART1. + This parameter must point to either the g_mss_uart0 or g_mss_uart1 + global data structure defined within the UART driver. + + @return + This function does not return a value. + + Example: + @code + MSS_UART_init(&g_mss_uart0, + MSS_UART_57600_BAUD, + MSS_UART_DATA_8_BITS | MSS_UART_NO_PARITY | MSS_UART_ONE_STOP_BIT); + + MSS_UART_disable_rx_timeout(&g_mss_uart0); + @endcode + */ +void +MSS_UART_disable_rx_timeout +( + mss_uart_instance_t * this_uart +); + +/***************************************************************************//** + The MSS_UART_enable_tx_time_guard() function is used to enable and configure + the transmitter time guard functionality of MSS UART. This function accepts + the timeguard parameter and applies the timeguard based up on the baud rate + as per the formula timeguard x bit time. + + @param this_uart + The this_uart parameter is a pointer to an mss_uart_instance_t + structure identifying the MSS UART hardware block that will perform + the requested function. There are two such data structures, + g_mss_uart0 and g_mss_uart1, associated with MSS UART0 and MSS UART1. + This parameter must point to either the g_mss_uart0 or g_mss_uart1 + global data structure defined within the UART driver. + + @return + This function does not return a value. + + Example: + @code + MSS_UART_init(&g_mss_uart0, + MSS_UART_57600_BAUD, + MSS_UART_DATA_8_BITS | MSS_UART_NO_PARITY | MSS_UART_ONE_STOP_BIT); + + MSS_UART_enable_tx_time_guard(&g_mss_uart0 , 24); + @endcode + */ +void +MSS_UART_enable_tx_time_guard +( + mss_uart_instance_t * this_uart, + uint8_t timeguard +); + +/***************************************************************************//** + The MSS_UART_disable_tx_time_guard() function is used to disable the + transmitter time guard functionality of MSS UART. + + @param this_uart + The this_uart parameter is a pointer to an mss_uart_instance_t + structure identifying the MSS UART hardware block that will perform + the requested function. There are two such data structures, + g_mss_uart0 and g_mss_uart1, associated with MSS UART0 and MSS UART1. + This parameter must point to either the g_mss_uart0 or g_mss_uart1 + global data structure defined within the UART driver. + + @return + This function does not return a value. + + Example: + @code + MSS_UART_init(&g_mss_uart0, + MSS_UART_57600_BAUD, + MSS_UART_DATA_8_BITS | MSS_UART_NO_PARITY | MSS_UART_ONE_STOP_BIT); + + MSS_UART_disable_tx_time_guard(&g_mss_uart0); + @endcode + */ +void +MSS_UART_disable_tx_time_guard +( + mss_uart_instance_t * this_uart +); + +/***************************************************************************//** + The MSS_UART_set_address() function is used to set the 8-bit address for + the MSS UART referenced by this_uart parameter. + + @param this_uart + The this_uart parameter is a pointer to an mss_uart_instance_t + structure identifying the MSS UART hardware block that will perform + the requested function. There are two such data structures, + g_mss_uart0 and g_mss_uart1, associated with MSS UART0 and MSS UART1. + This parameter must point to either the g_mss_uart0 or g_mss_uart1 + global data structure defined within the UART driver. + + @param address + The address parameter is the 8-bit address which is to be configured + to the MSS UART referenced by this_uart parameter. + + @return + This function does not return a value. + + Example: + @code + MSS_UART_init(&g_mss_uart0, + MSS_UART_57600_BAUD, + MSS_UART_DATA_8_BITS | MSS_UART_NO_PARITY | MSS_UART_ONE_STOP_BIT); + + MSS_UART_set_address(&g_mss_uart0, 0xAA); + @endcode + */ +void +MSS_UART_set_address +( + mss_uart_instance_t * this_uart, + uint8_t address +); + +/***************************************************************************//** + The MSS_UART_set_ready_mode() function is used to configure the MODE0 or MODE1 + to the TXRDY and RXRDY signals of the MSS UART referenced by this_uart + parameter. The mode parameter is used to provide the mode to be configured. + + @param this_uart + The this_uart parameter is a pointer to an mss_uart_instance_t + structure identifying the MSS UART hardware block that will perform + the requested function. There are two such data structures, + g_mss_uart0 and g_mss_uart1, associated with MSS UART0 and MSS UART1. + This parameter must point to either the g_mss_uart0 or g_mss_uart1 + global data structure defined within the UART driver. + + @param mode + The mode parameter is the mss_uart_ready_mode_t type which is used to + configure the TXRDY and RXRDY signal modes. + + @return + This function does not return a value. + + Example: + @code + MSS_UART_init(&g_mss_uart0, + MSS_UART_57600_BAUD, + MSS_UART_DATA_8_BITS | MSS_UART_NO_PARITY | MSS_UART_ONE_STOP_BIT); + + MSS_UART_set_ready_mode(&g_mss_uart0, MSS_UART_READY_MODE0); + @endcode + */ +void +MSS_UART_set_ready_mode +( + mss_uart_instance_t * this_uart, + mss_uart_ready_mode_t mode +); + +/***************************************************************************//** + The MSS_UART_set_usart_mode() function is used to configure the MSS UART + referenced by the parameter this_uart in USART mode. Various USART modes + are supported which can be configured by the parameter mode of type + mss_uart_usart_mode_t. + + @param this_uart + The this_uart parameter is a pointer to an mss_uart_instance_t + structure identifying the MSS UART hardware block that will perform + the requested function. There are two such data structures, + g_mss_uart0 and g_mss_uart1, associated with MSS UART0 and MSS UART1. + This parameter must point to either the g_mss_uart0 or g_mss_uart1 + global data structure defined within the UART driver. + + @param mode + The mode parameter is the USART mode to be configured. + This parameter is of type mss_uart_usart_mode_t. + + @return + This function does not return a value. + + Example: + @code + MSS_UART_init(&g_mss_uart0, + MSS_UART_57600_BAUD, + MSS_UART_DATA_8_BITS | MSS_UART_NO_PARITY | MSS_UART_ONE_STOP_BIT); + + MSS_UART_set_usart_mode(&g_mss_uart0, MSS_UART_SYNC_MASTER_POS_EDGE_CLK); + @endcode + */ +void +MSS_UART_set_usart_mode +( + mss_uart_instance_t * this_uart, + mss_uart_usart_mode_t mode +); + +#ifdef __cplusplus +} +#endif + +#endif /* __MSS_UART_H_ */ diff --git a/bsp/smartfusion2/libraries/mss_uart/mss_uart_regs.h b/bsp/smartfusion2/libraries/mss_uart/mss_uart_regs.h new file mode 100644 index 0000000000..3079ad4ba3 --- /dev/null +++ b/bsp/smartfusion2/libraries/mss_uart/mss_uart_regs.h @@ -0,0 +1,83 @@ +/******************************************************************************* + * (c) Copyright 2011-2013 Microsemi SoC Products Group. All rights reserved. + * + * Register bit offsets and masks defintions for SmartFusion2 MSS MMUART. + * + * SVN $Revision: 5610 $ + * SVN $Date: 2013-04-05 18:49:30 +0530 (Fri, 05 Apr 2013) $ + */ +#ifndef MSS_UART_REGS_H_ +#define MSS_UART_REGS_H_ + +#ifdef __cplusplus +extern "C" { +#endif + +/******************************************************************************* + Register Bit definitions + */ + +/* Line Control register bit definitions */ +#define SB 6u /* Set break */ +#define DLAB 7u /* Divisor latch access bit */ + +/* FIFO Control register bit definitions */ +#define RXRDY_TXRDYN_EN 0u /* Enable TXRDY and RXRDY signals */ +#define CLEAR_RX_FIFO 1u /* Clear receiver FIFO */ +#define CLEAR_TX_FIFO 2u /* Clear transimtter FIFO */ +#define RDYMODE 3u /* Mode 0 or Mode 1 for TXRDY and RXRDY */ + +/* Modem Control register bit definitions */ +#define LOOP 4u /* Local loopback */ +#define RLOOP 5u /* Remote loopback */ +#define ECHO 6u /* Automatic echo */ +#define RLOOP_MASK 0x6u /* Remote loopback & Automatic echo*/ + +/* Line Status register bit definitions */ +#define DR 0u /* Data ready */ +#define THRE 5u /* Transmitter holding register empty */ +#define TEMT 6u /* Transitter empty */ + +/* Interrupt Enable register bit definitions */ +#define ERBFI 0u /* Enable receiver buffer full interrupt */ +#define ETBEI 1u /* Enable transmitter buffer empty interrupt */ +#define ELSI 2u /* Enable line status interrupt */ +#define EDSSI 3u /* Enable modem status interrupt */ + +/* Multimode register 0 bit definitions */ +#define ELIN 3u /* Enable LIN header detection */ +#define ETTG 5u /* Enable transmitter time guard */ +#define ERTO 6u /* Enable receiver time-out */ +#define EFBR 7u /* Enable fractional baud rate mode */ + +/* Multimode register 1 bit definitions */ +#define E_MSB_RX 0u /* MSB / LSB first for receiver */ +#define E_MSB_TX 1u /* MSB / LSB first for transmitter */ +#define EIRD 2u /* Enable IrDA modem */ +#define EIRX 3u /* Input polarity for IrDA modem */ +#define EITX 4u /* Output polarity for IrDA modem */ +#define EITP 5u /* Output pulse width for IrDA modem */ + +/* Multimode register 2 bit definitions */ +#define EERR 0u /* Enable ERR / NACK during stop time */ +#define EAFM 1u /* Enable 9-bit address flag mode */ +#define EAFC 2u /* Enable address flag clear */ +#define ESWM 3u /* Enable single wire half-duplex mode */ + +/* Multimode Interrupt Enable register and + Multimode Interrupt Identification register definitions */ +#define ERTOI 0u /* Enable receiver timeout interrupt */ +#define ENACKI 1u /* Enable NACK / ERR interrupt */ +#define EPID_PEI 2u /* Enable PID parity error interrupt */ +#define ELINBI 3u /* Enable LIN break interrupt */ +#define ELINSI 4u /* Enable LIN sync detection interrupt */ + + +#ifdef __cplusplus +} +#endif + +#endif /* MSS_UART_REGS_H_ */ + + + diff --git a/bsp/smartfusion2/libraries/sys_config/sys_config.c b/bsp/smartfusion2/libraries/sys_config/sys_config.c new file mode 100644 index 0000000000..b7d72fe08f --- /dev/null +++ b/bsp/smartfusion2/libraries/sys_config/sys_config.c @@ -0,0 +1,385 @@ +/******************************************************************************* + * (c) Copyright 2012 Microsemi SoC Products Group. All rights reserved. + * + * Smartfusion2 system configuration. This file is automatically generated + * by the Libero tools. It contains the Smartfusion2 system configuration that + * was selected during the hardware configuration flow. + * + */ + +#include "../../CMSIS/m2sxxx.h" +#include "../../CMSIS/sys_init_cfg_types.h" +#include "sys_config.h" + +/*============================================================================== + * !!! WARNING !!! + *============================================================================== + * The project including this file must be linked so that the content of this + * file is located in internal eNVM at run time. The content of this file is + * used to configure the system prior to RAM content initialization. This means + * that the content of the data structures below will be used before the copy + * from LMA to VMA takes place. The LMA and VMA locations of the content of this + * file must be identical for the system to be seamlessly configured as part of + * the CMSIS boot process. + */ + +/*============================================================================== + * Clock configuration + */ +/* No configuration data structure required. */ + +/*============================================================================== + * Memory remapping configuration + */ +/* TBD. */ + +/*============================================================================== + * MDDR configuration + */ +#if MSS_SYS_MDDR_CONFIG_BY_CORTEX + +#include "sys_config_mddr_define.h" + +MDDR_TypeDef * const g_m2s_mddr_addr = (MDDR_TypeDef *)0x40020800; + +const ddr_subsys_cfg_t g_m2s_mddr_subsys_config = +{ + /*--------------------------------------------------------------------- + * DDR Controller registers. + * All registers are 16-bit wide unless mentioned beside the definition. + */ + { + MDDR_DDRC_DYN_SOFT_RESET_CR, + MDDR_DDRC_RESERVED0, + MDDR_DDRC_DYN_REFRESH_1_CR, + MDDR_DDRC_DYN_REFRESH_2_CR, + MDDR_DDRC_DYN_POWERDOWN_CR, + MDDR_DDRC_DYN_DEBUG_CR, + MDDR_DDRC_MODE_CR, + MDDR_DDRC_ADDR_MAP_BANK_CR, + MDDR_DDRC_ECC_DATA_MASK_CR, + MDDR_DDRC_ADDR_MAP_COL_1_CR, + MDDR_DDRC_ADDR_MAP_COL_2_CR, + MDDR_DDRC_ADDR_MAP_ROW_1_CR, + MDDR_DDRC_ADDR_MAP_ROW_2_CR, + MDDR_DDRC_INIT_1_CR, + MDDR_DDRC_CKE_RSTN_CYCLES_1_CR, + MDDR_DDRC_CKE_RSTN_CYCLES_2_CR, + MDDR_DDRC_INIT_MR_CR, + MDDR_DDRC_INIT_EMR_CR, + MDDR_DDRC_INIT_EMR2_CR, + MDDR_DDRC_INIT_EMR3_CR, + MDDR_DDRC_DRAM_BANK_TIMING_PARAM_CR, + MDDR_DDRC_DRAM_RD_WR_LATENCY_CR, + MDDR_DDRC_DRAM_RD_WR_PRE_CR, + MDDR_DDRC_DRAM_MR_TIMING_PARAM_CR, + MDDR_DDRC_DRAM_RAS_TIMING_CR, + MDDR_DDRC_DRAM_RD_WR_TRNARND_TIME_CR, + MDDR_DDRC_DRAM_T_PD_CR, + MDDR_DDRC_DRAM_BANK_ACT_TIMING_CR, + MDDR_DDRC_ODT_PARAM_1_CR, + MDDR_DDRC_ODT_PARAM_2_CR, + MDDR_DDRC_ADDR_MAP_COL_3_CR, + MDDR_DDRC_MODE_REG_RD_WR_CR, + MDDR_DDRC_MODE_REG_DATA_CR, + MDDR_DDRC_PWR_SAVE_1_CR, + MDDR_DDRC_PWR_SAVE_2_CR, + MDDR_DDRC_ZQ_LONG_TIME_CR, + MDDR_DDRC_ZQ_SHORT_TIME_CR, + MDDR_DDRC_ZQ_SHORT_INT_REFRESH_MARGIN_1_CR, + MDDR_DDRC_ZQ_SHORT_INT_REFRESH_MARGIN_2_CR, + MDDR_DDRC_PERF_PARAM_1_CR, + MDDR_DDRC_HPR_QUEUE_PARAM_1_CR, + MDDR_DDRC_HPR_QUEUE_PARAM_2_CR, + MDDR_DDRC_LPR_QUEUE_PARAM_1_CR, + MDDR_DDRC_LPR_QUEUE_PARAM_2_CR, + MDDR_DDRC_WR_QUEUE_PARAM_CR, + MDDR_DDRC_PERF_PARAM_2_CR, + MDDR_DDRC_PERF_PARAM_3_CR, + MDDR_DDRC_DFI_RDDATA_EN_CR, + MDDR_DDRC_DFI_MIN_CTRLUPD_TIMING_CR, + MDDR_DDRC_DFI_MAX_CTRLUPD_TIMING_CR, + MDDR_DDRC_DFI_WR_LVL_CONTROL_1_CR, + MDDR_DDRC_DFI_WR_LVL_CONTROL_2_CR, + MDDR_DDRC_DFI_RD_LVL_CONTROL_1_CR, + MDDR_DDRC_DFI_RD_LVL_CONTROL_2_CR, + MDDR_DDRC_DFI_CTRLUPD_TIME_INTERVAL_CR, + MDDR_DDRC_DYN_SOFT_RESET_ALIAS_CR, + MDDR_DDRC_AXI_FABRIC_PRI_ID_CR, + }, + + /*--------------------------------------------------------------------- + * DDR PHY configuration registers + */ + { + MDDR_PHY_LOOPBACK_TEST_CR, + MDDR_PHY_BOARD_LOOPBACK_CR, + MDDR_PHY_CTRL_SLAVE_RATIO_CR, + MDDR_PHY_CTRL_SLAVE_FORCE_CR, + MDDR_PHY_CTRL_SLAVE_DELAY_CR, + MDDR_PHY_DATA_SLICE_IN_USE_CR, + MDDR_PHY_LVL_NUM_OF_DQ0_CR, + MDDR_PHY_DQ_OFFSET_1_CR, + MDDR_PHY_DQ_OFFSET_2_CR, + MDDR_PHY_DQ_OFFSET_3_CR, + MDDR_PHY_DIS_CALIB_RST_CR, + MDDR_PHY_DLL_LOCK_DIFF_CR, + MDDR_PHY_FIFO_WE_IN_DELAY_1_CR, + MDDR_PHY_FIFO_WE_IN_DELAY_2_CR, + MDDR_PHY_FIFO_WE_IN_DELAY_3_CR, + MDDR_PHY_FIFO_WE_IN_FORCE_CR, + MDDR_PHY_FIFO_WE_SLAVE_RATIO_1_CR, + MDDR_PHY_FIFO_WE_SLAVE_RATIO_2_CR, + MDDR_PHY_FIFO_WE_SLAVE_RATIO_3_CR, + MDDR_PHY_FIFO_WE_SLAVE_RATIO_4_CR, + MDDR_PHY_GATELVL_INIT_MODE_CR, + MDDR_PHY_GATELVL_INIT_RATIO_1_CR, + MDDR_PHY_GATELVL_INIT_RATIO_2_CR, + MDDR_PHY_GATELVL_INIT_RATIO_3_CR, + MDDR_PHY_GATELVL_INIT_RATIO_4_CR, + MDDR_PHY_LOCAL_ODT_CR, + MDDR_PHY_INVERT_CLKOUT_CR, + MDDR_PHY_RD_DQS_SLAVE_DELAY_1_CR, + MDDR_PHY_RD_DQS_SLAVE_DELAY_2_CR, + MDDR_PHY_RD_DQS_SLAVE_DELAY_3_CR, + MDDR_PHY_RD_DQS_SLAVE_FORCE_CR, + MDDR_PHY_RD_DQS_SLAVE_RATIO_1_CR, + MDDR_PHY_RD_DQS_SLAVE_RATIO_2_CR, + MDDR_PHY_RD_DQS_SLAVE_RATIO_3_CR, + MDDR_PHY_RD_DQS_SLAVE_RATIO_4_CR, + MDDR_PHY_WR_DQS_SLAVE_DELAY_1_CR, + MDDR_PHY_WR_DQS_SLAVE_DELAY_2_CR, + MDDR_PHY_WR_DQS_SLAVE_DELAY_3_CR, + MDDR_PHY_WR_DQS_SLAVE_FORCE_CR, + MDDR_PHY_WR_DQS_SLAVE_RATIO_1_CR, + MDDR_PHY_WR_DQS_SLAVE_RATIO_2_CR, + MDDR_PHY_WR_DQS_SLAVE_RATIO_3_CR, + MDDR_PHY_WR_DQS_SLAVE_RATIO_4_CR, + MDDR_PHY_WR_DATA_SLAVE_DELAY_1_CR, + MDDR_PHY_WR_DATA_SLAVE_DELAY_2_CR, + MDDR_PHY_WR_DATA_SLAVE_DELAY_3_CR, + MDDR_PHY_WR_DATA_SLAVE_FORCE_CR, + MDDR_PHY_WR_DATA_SLAVE_RATIO_1_CR, + MDDR_PHY_WR_DATA_SLAVE_RATIO_2_CR, + MDDR_PHY_WR_DATA_SLAVE_RATIO_3_CR, + MDDR_PHY_WR_DATA_SLAVE_RATIO_4_CR, + MDDR_PHY_WRLVL_INIT_MODE_CR, + MDDR_PHY_WRLVL_INIT_RATIO_1_CR, + MDDR_PHY_WRLVL_INIT_RATIO_2_CR, + MDDR_PHY_WRLVL_INIT_RATIO_3_CR, + MDDR_PHY_WRLVL_INIT_RATIO_4_CR, + MDDR_PHY_WR_RD_RL_CR, + MDDR_PHY_RDC_FIFO_RST_ERR_CNT_CLR_CR, + MDDR_PHY_RDC_WE_TO_RE_DELAY_CR, + MDDR_PHY_USE_FIXED_RE_CR, + MDDR_PHY_USE_RANK0_DELAYS_CR, + MDDR_PHY_USE_LVL_TRNG_LEVEL_CR, + MDDR_PHY_DYN_CONFIG_CR, + MDDR_PHY_RD_WR_GATE_LVL_CR, + MDDR_PHY_DYN_RESET_CR + }, + + /*--------------------------------------------------------------------- + * FIC-64 registers + * These registers are 16-bit wide and 32-bit aligned. + */ + { + MDDR_DDR_FIC_NB_ADDR_CR, + MDDR_DDR_FIC_NBRWB_SIZE_CR, + MDDR_DDR_FIC_WB_TIMEOUT_CR, + MDDR_DDR_FIC_HPD_SW_RW_EN_CR, + MDDR_DDR_FIC_HPD_SW_RW_INVAL_CR, + MDDR_DDR_FIC_SW_WR_ERCLR_CR, + MDDR_DDR_FIC_ERR_INT_ENABLE_CR, + MDDR_DDR_FIC_NUM_AHB_MASTERS_CR, + MDDR_DDR_FIC_LOCK_TIMEOUTVAL_1_CR, + MDDR_DDR_FIC_LOCK_TIMEOUTVAL_2_CR, + MDDR_DDR_FIC_LOCK_TIMEOUT_EN_CR + } +}; + +#endif + +/*============================================================================== + * FDDR configuration + */ +#if MSS_SYS_FDDR_CONFIG_BY_CORTEX + +#include "sys_config_fddr_define.h" + +FDDR_TypeDef * const g_m2s_fddr_addr = (FDDR_TypeDef *)0x40021000; + +const fddr_sysreg_t g_m2s_fddr_sysreg_subsys_config = +{ + 0x0001u, /* PLL_CONFIG_LOW_1 */ + 0x0002u, /* PLL_CONFIG_LOW_2 */ + 0x0003u, /* PLL_CONFIG_HIGH */ + 0x0004u, /* FACC_CLK_EN */ + 0x0005u, /* FACC_MUX_CONFIG */ + 0x0006u, /* FACC_DIVISOR_RATIO */ + 0x0007u, /* PLL_DELAY_LINE_SEL */ + 0x0008u, /* SOFT_RESET */ + 0x0009u, /* IO_CALIB */ + 0x000Au, /* INTERRUPT_ENABLE */ + 0x000Bu, /* AXI_AHB_MODE_SEL */ + 0x000Cu /* PHY_SELF_REF_EN */ +}; + +const ddr_subsys_cfg_t g_m2s_fddr_subsys_config = +{ + /*--------------------------------------------------------------------- + * DDR Controller registers. + * All registers are 16-bit wide unless mentioned beside the definition. + */ + { + FDDR_DDRC_DYN_SOFT_RESET_CR, + FDDR_DDRC_RESERVED0, + FDDR_DDRC_DYN_REFRESH_1_CR, + FDDR_DDRC_DYN_REFRESH_2_CR, + FDDR_DDRC_DYN_POWERDOWN_CR, + FDDR_DDRC_DYN_DEBUG_CR, + FDDR_DDRC_MODE_CR, + FDDR_DDRC_ADDR_MAP_BANK_CR, + FDDR_DDRC_ECC_DATA_MASK_CR, + FDDR_DDRC_ADDR_MAP_COL_1_CR, + FDDR_DDRC_ADDR_MAP_COL_2_CR, + FDDR_DDRC_ADDR_MAP_ROW_1_CR, + FDDR_DDRC_ADDR_MAP_ROW_2_CR, + FDDR_DDRC_INIT_1_CR, + FDDR_DDRC_CKE_RSTN_CYCLES_1_CR, + FDDR_DDRC_CKE_RSTN_CYCLES_2_CR, + FDDR_DDRC_INIT_MR_CR, + FDDR_DDRC_INIT_EMR_CR, + FDDR_DDRC_INIT_EMR2_CR, + FDDR_DDRC_INIT_EMR3_CR, + FDDR_DDRC_DRAM_BANK_TIMING_PARAM_CR, + FDDR_DDRC_DRAM_RD_WR_LATENCY_CR, + FDDR_DDRC_DRAM_RD_WR_PRE_CR, + FDDR_DDRC_DRAM_MR_TIMING_PARAM_CR, + FDDR_DDRC_DRAM_RAS_TIMING_CR, + FDDR_DDRC_DRAM_RD_WR_TRNARND_TIME_CR, + FDDR_DDRC_DRAM_T_PD_CR, + FDDR_DDRC_DRAM_BANK_ACT_TIMING_CR, + FDDR_DDRC_ODT_PARAM_1_CR, + FDDR_DDRC_ODT_PARAM_2_CR, + FDDR_DDRC_ADDR_MAP_COL_3_CR, + FDDR_DDRC_MODE_REG_RD_WR_CR, + FDDR_DDRC_MODE_REG_DATA_CR, + FDDR_DDRC_PWR_SAVE_1_CR, + FDDR_DDRC_PWR_SAVE_2_CR, + FDDR_DDRC_ZQ_LONG_TIME_CR, + FDDR_DDRC_ZQ_SHORT_TIME_CR, + FDDR_DDRC_ZQ_SHORT_INT_REFRESH_MARGIN_1_CR, + FDDR_DDRC_ZQ_SHORT_INT_REFRESH_MARGIN_2_CR, + FDDR_DDRC_PERF_PARAM_1_CR, + FDDR_DDRC_HPR_QUEUE_PARAM_1_CR, + FDDR_DDRC_HPR_QUEUE_PARAM_2_CR, + FDDR_DDRC_LPR_QUEUE_PARAM_1_CR, + FDDR_DDRC_LPR_QUEUE_PARAM_2_CR, + FDDR_DDRC_WR_QUEUE_PARAM_CR, + FDDR_DDRC_PERF_PARAM_2_CR, + FDDR_DDRC_PERF_PARAM_3_CR, + FDDR_DDRC_DFI_RDDATA_EN_CR, + FDDR_DDRC_DFI_MIN_CTRLUPD_TIMING_CR, + FDDR_DDRC_DFI_MAX_CTRLUPD_TIMING_CR, + FDDR_DDRC_DFI_WR_LVL_CONTROL_1_CR, + FDDR_DDRC_DFI_WR_LVL_CONTROL_2_CR, + FDDR_DDRC_DFI_RD_LVL_CONTROL_1_CR, + FDDR_DDRC_DFI_RD_LVL_CONTROL_2_CR, + FDDR_DDRC_DFI_CTRLUPD_TIME_INTERVAL_CR, + FDDR_DDRC_DYN_SOFT_RESET_ALIAS_CR, + FDDR_DDRC_AXI_FABRIC_PRI_ID_CR + }, + + /*--------------------------------------------------------------------- + * DDR PHY configuration registers + */ + { + FDDR_PHY_LOOPBACK_TEST_CR, + FDDR_PHY_BOARD_LOOPBACK_CR, + FDDR_PHY_CTRL_SLAVE_RATIO_CR, + FDDR_PHY_CTRL_SLAVE_FORCE_CR, + FDDR_PHY_CTRL_SLAVE_DELAY_CR, + FDDR_PHY_DATA_SLICE_IN_USE_CR, + FDDR_PHY_LVL_NUM_OF_DQ0_CR, + FDDR_PHY_DQ_OFFSET_1_CR, + FDDR_PHY_DQ_OFFSET_2_CR, + FDDR_PHY_DQ_OFFSET_3_CR, + FDDR_PHY_DIS_CALIB_RST_CR, + FDDR_PHY_DLL_LOCK_DIFF_CR, + FDDR_PHY_FIFO_WE_IN_DELAY_1_CR, + FDDR_PHY_FIFO_WE_IN_DELAY_2_CR, + FDDR_PHY_FIFO_WE_IN_DELAY_3_CR, + FDDR_PHY_FIFO_WE_IN_FORCE_CR, + FDDR_PHY_FIFO_WE_SLAVE_RATIO_1_CR, + FDDR_PHY_FIFO_WE_SLAVE_RATIO_2_CR, + FDDR_PHY_FIFO_WE_SLAVE_RATIO_3_CR, + FDDR_PHY_FIFO_WE_SLAVE_RATIO_4_CR, + FDDR_PHY_GATELVL_INIT_MODE_CR, + FDDR_PHY_GATELVL_INIT_RATIO_1_CR, + FDDR_PHY_GATELVL_INIT_RATIO_2_CR, + FDDR_PHY_GATELVL_INIT_RATIO_3_CR, + FDDR_PHY_GATELVL_INIT_RATIO_4_CR, + FDDR_PHY_LOCAL_ODT_CR, + FDDR_PHY_INVERT_CLKOUT_CR, + FDDR_PHY_RD_DQS_SLAVE_DELAY_1_CR, + FDDR_PHY_RD_DQS_SLAVE_DELAY_2_CR, + FDDR_PHY_RD_DQS_SLAVE_DELAY_3_CR, + FDDR_PHY_RD_DQS_SLAVE_FORCE_CR, + FDDR_PHY_RD_DQS_SLAVE_RATIO_1_CR, + FDDR_PHY_RD_DQS_SLAVE_RATIO_2_CR, + FDDR_PHY_RD_DQS_SLAVE_RATIO_3_CR, + FDDR_PHY_RD_DQS_SLAVE_RATIO_4_CR, + FDDR_PHY_WR_DQS_SLAVE_DELAY_1_CR, + FDDR_PHY_WR_DQS_SLAVE_DELAY_2_CR, + FDDR_PHY_WR_DQS_SLAVE_DELAY_3_CR, + FDDR_PHY_WR_DQS_SLAVE_FORCE_CR, + FDDR_PHY_WR_DQS_SLAVE_RATIO_1_CR, + FDDR_PHY_WR_DQS_SLAVE_RATIO_2_CR, + FDDR_PHY_WR_DQS_SLAVE_RATIO_3_CR, + FDDR_PHY_WR_DQS_SLAVE_RATIO_4_CR, + FDDR_PHY_WR_DATA_SLAVE_DELAY_1_CR, + FDDR_PHY_WR_DATA_SLAVE_DELAY_2_CR, + FDDR_PHY_WR_DATA_SLAVE_DELAY_3_CR, + FDDR_PHY_WR_DATA_SLAVE_FORCE_CR, + FDDR_PHY_WR_DATA_SLAVE_RATIO_1_CR, + FDDR_PHY_WR_DATA_SLAVE_RATIO_2_CR, + FDDR_PHY_WR_DATA_SLAVE_RATIO_3_CR, + FDDR_PHY_WR_DATA_SLAVE_RATIO_4_CR, + FDDR_PHY_WRLVL_INIT_MODE_CR, + FDDR_PHY_WRLVL_INIT_RATIO_1_CR, + FDDR_PHY_WRLVL_INIT_RATIO_2_CR, + FDDR_PHY_WRLVL_INIT_RATIO_3_CR, + FDDR_PHY_WRLVL_INIT_RATIO_4_CR, + FDDR_PHY_WR_RD_RL_CR, + FDDR_PHY_RDC_FIFO_RST_ERR_CNT_CLR_CR, + FDDR_PHY_RDC_WE_TO_RE_DELAY_CR, + FDDR_PHY_USE_FIXED_RE_CR, + FDDR_PHY_USE_RANK0_DELAYS_CR, + FDDR_PHY_USE_LVL_TRNG_LEVEL_CR, + FDDR_PHY_DYN_CONFIG_CR, + FDDR_PHY_RD_WR_GATE_LVL_CR, + FDDR_PHY_DYN_RESET_CR, + }, + + /*--------------------------------------------------------------------- + * FIC-64 registers + * These registers are 16-bit wide and 32-bit aligned. + */ + { + FDDR_DDR_FIC_NB_ADDR_CR, + FDDR_DDR_FIC_NBRWB_SIZE_CR, + FDDR_DDR_FIC_WB_TIMEOUT_CR, + FDDR_DDR_FIC_HPD_SW_RW_EN_CR, + FDDR_DDR_FIC_HPD_SW_RW_INVAL_CR, + FDDR_DDR_FIC_SW_WR_ERCLR_CR, + FDDR_DDR_FIC_ERR_INT_ENABLE_CR, + FDDR_DDR_FIC_NUM_AHB_MASTERS_CR, + FDDR_DDR_FIC_LOCK_TIMEOUTVAL_1_CR, + FDDR_DDR_FIC_LOCK_TIMEOUTVAL_2_CR, + FDDR_DDR_FIC_LOCK_TIMEOUT_EN_CR + } +}; + +#endif + diff --git a/bsp/smartfusion2/libraries/sys_config/sys_config.h b/bsp/smartfusion2/libraries/sys_config/sys_config.h new file mode 100644 index 0000000000..65c49b1d7d --- /dev/null +++ b/bsp/smartfusion2/libraries/sys_config/sys_config.h @@ -0,0 +1,66 @@ +/******************************************************************************* + * (c) Copyright 2012 Microsemi SoC Products Group. All rights reserved. + * + * Smartfusion2 system configuration. This file is automatically generated + * by the Libero tools. + * + */ +#ifndef MSS_SYSTEM_CONFIGURATION +#define MSS_SYSTEM_CONFIGURATION + +/*============================================================================== + * Clock configuration + */ +#include "sys_config_mss_clocks.h" + +/*============================================================================== + * Memory remapping configuration + */ +/* TBD */ + +/*============================================================================== + * FACC_INIT (Cortex-M3 runs the FACC INIT procedure) + * Only set to 1 for design targeting the M2S050T_ES device + */ +#define MSS_SYS_FACC_INIT_BY_CORTEX 0 + +/*============================================================================== + * MDDR configuration + */ +#define MSS_SYS_MDDR_CONFIG_BY_CORTEX 0 + +/*============================================================================== + * FDDR configuration + */ +#define MSS_SYS_FDDR_CONFIG_BY_CORTEX 0 + +/*============================================================================== + * SERDES Interface configuration + */ +#define MSS_SYS_SERDES_0_CONFIG_BY_CORTEX 0 +#if MSS_SYS_SERDES_0_CONFIG_BY_CORTEX +#include "sys_config_SERDESIF_0.h" +#endif + +#define MSS_SYS_SERDES_1_CONFIG_BY_CORTEX 0 +#if MSS_SYS_SERDES_1_CONFIG_BY_CORTEX +#include "sys_config_SERDESIF_1.h" +#endif + +#define MSS_SYS_SERDES_2_CONFIG_BY_CORTEX 0 +#if MSS_SYS_SERDES_2_CONFIG_BY_CORTEX +#include "sys_config_SERDESIF_2.h" +#endif + +#define MSS_SYS_SERDES_3_CONFIG_BY_CORTEX 0 +#if MSS_SYS_SERDES_3_CONFIG_BY_CORTEX +#include "sys_config_SERDESIF_3.h" +#endif + +/*============================================================================== + * Cache configuration + */ +#define MSS_SYS_CACHE_CONFIG_BY_CORTEX 0 + +#endif /* MSS_SYSTEM_CONFIGURATION */ + diff --git a/bsp/smartfusion2/libraries/sys_config/sys_config_mss_clocks.h b/bsp/smartfusion2/libraries/sys_config/sys_config_mss_clocks.h new file mode 100644 index 0000000000..1110c97169 --- /dev/null +++ b/bsp/smartfusion2/libraries/sys_config/sys_config_mss_clocks.h @@ -0,0 +1,21 @@ +/*=============================================================*/ +/* Created by Microsemi SmartDesign Fri May 22 15:04:18 2020 */ +/* */ +/* Warning: Do not modify this file, it may lead to unexpected */ +/* functional failures in your design. */ +/* */ +/*=============================================================*/ + +#ifndef SYS_CONFIG_MSS_CLOCKS +#define SYS_CONFIG_MSS_CLOCKS + +#define MSS_SYS_M3_CLK_FREQ 100000000u +#define MSS_SYS_MDDR_CLK_FREQ 100000000u +#define MSS_SYS_APB_0_CLK_FREQ 100000000u +#define MSS_SYS_APB_1_CLK_FREQ 100000000u +#define MSS_SYS_APB_2_CLK_FREQ 25000000u +#define MSS_SYS_FIC_0_CLK_FREQ 100000000u +#define MSS_SYS_FIC_1_CLK_FREQ 100000000u +#define MSS_SYS_FIC64_CLK_FREQ 100000000u + +#endif /* SYS_CONFIG_MSS_CLOCKS */ diff --git a/bsp/smartfusion2/obj/project.sct b/bsp/smartfusion2/obj/project.sct new file mode 100644 index 0000000000..12075206ce --- /dev/null +++ b/bsp/smartfusion2/obj/project.sct @@ -0,0 +1,16 @@ +; *************************************************************
+; *** Scatter-Loading Description File generated by uVision ***
+; *************************************************************
+
+LR_IROM1 0x00000000 0x00040000 { ; load region size_region
+ ER_IROM1 0x00000000 0x00040000 { ; load address = execution address
+ *.o (RESET, +First)
+ *(InRoot$$Sections)
+ .ANY (+RO)
+ .ANY (+XO)
+ }
+ RW_IRAM1 0x20000000 0x00010000 { ; RW data
+ .ANY (+RW +ZI)
+ }
+}
+
diff --git a/bsp/smartfusion2/user/EventRecorderStub.scvd b/bsp/smartfusion2/user/EventRecorderStub.scvd new file mode 100644 index 0000000000..2956b29683 --- /dev/null +++ b/bsp/smartfusion2/user/EventRecorderStub.scvd @@ -0,0 +1,9 @@ +<?xml version="1.0" encoding="utf-8"?> + +<component_viewer schemaVersion="0.1" xmlns:xs="http://www.w3.org/2001/XMLSchema-instance" xs:noNamespaceSchemaLocation="Component_Viewer.xsd"> + +<component name="EventRecorderStub" version="1.0.0"/> <!--name and version of the component--> + <events> + </events> + +</component_viewer> diff --git a/bsp/smartfusion2/user/JLinkLog.txt b/bsp/smartfusion2/user/JLinkLog.txt new file mode 100644 index 0000000000..e13365065e --- /dev/null +++ b/bsp/smartfusion2/user/JLinkLog.txt @@ -0,0 +1,7286 @@ +T3170 081:402 SEGGER J-Link V6.32i Log File (0000ms, 21800ms total) +T3170 081:402 DLL Compiled: Jul 24 2018 15:19:55 (0000ms, 21800ms total) +T3170 081:402 Logging started @ 2020-06-05 19:40 (0000ms, 21800ms total) +T3170 081:402 JLINK_SetWarnOutHandler(...) (0000ms, 21800ms total) +T3170 081:402 JLINK_OpenEx(...) +Firmware: J-Link ARM-OB STM32 compiled Aug 22 2012 19:52:04 +Hardware: V7.00 +S/N: 20090928 +Feature(s): RDI,FlashDL,FlashBP,JFlash,GDBFull +TELNET listener socket opened on port 19021WEBSRV +Starting webserver (0111ms, 21911ms total) +T3170 081:402 WEBSRV Webserver running on local port 19080 (0111ms, 21911ms total) +T3170 081:402 returns O.K. (0111ms, 21911ms total) +T3170 081:513 JLINK_GetEmuCaps() returns 0x88EA5833 (0000ms, 21911ms total) +T3170 081:513 JLINK_TIF_GetAvailable(...) (0008ms, 21919ms total) +T3170 081:599 JLINK_SetErrorOutHandler(...) (0000ms, 21919ms total) +T3170 081:599 JLINK_ExecCommand("ProjectFile = "D:\workspace\fpga\rt-thread\bsp\smartfusion2\user\JLinkSettings.ini"", ...). returns 0x00 (0001ms, 21920ms total) +T3170 081:602 JLINK_ExecCommand("Device = M2S010", ...). Device "M2S010" selected. returns 0x00 (0002ms, 21922ms total) +T3170 081:604 JLINK_ExecCommand("DisableConnectionTimeout", ...). returns 0x01 (0000ms, 21922ms total) +T3170 081:604 JLINK_GetHardwareVersion() returns 0x11170 (0000ms, 21922ms total) +T3170 081:604 JLINK_GetDLLVersion() returns 63209 (0000ms, 21922ms total) +T3170 081:604 JLINK_GetFirmwareString(...) (0000ms, 21922ms total) +T3170 081:608 JLINK_GetDLLVersion() returns 63209 (0000ms, 21922ms total) +T3170 081:608 JLINK_GetCompileDateTime() (0000ms, 21922ms total) +T3170 081:609 JLINK_GetFirmwareString(...) (0001ms, 21923ms total) +T3170 081:611 JLINK_GetHardwareVersion() returns 0x11170 (0000ms, 21923ms total) +T3170 081:616 JLINK_TIF_Select(JLINKARM_TIF_SWD) returns 0x00 (0085ms, 22008ms total) +T3170 081:702 JLINK_SetSpeed(10000) (0001ms, 22009ms total) +T3170 081:703 JLINK_GetId() >0x10B TIF>Found SW-DP with ID 0x2BA01477 >0x0D TIF> >0x28 TIF> >0x0D TIF> >0x28 TIF> >0x0D TIF> >0x28 TIF> >0x0D TIF> >0x28 TIF> >0x0D TIF> >0x21 TIF> >0x0D TIF> >0x28 TIF>Scanning AP map to find all available APs >0x0D TIF> >0x28 TIF> >0x0D TIF> >0x21 TIF> >0x0D TIF> >0x21 TIF> >0x0D TIF> >0x28 TIF> >0x0D TIF> >0x21 TIF> >0x0D TIF> >0x21 TIF>AP[1]: Stopped AP scan as end of AP map has been reachedAP[0]: AHB-AP (IDR: 0x24770011)Iterating through AP map to find AHB-AP to use + >0x42 TIF> >0x28 TIF> >0x0D TIF> >0x28 TIF> >0x0D TIF> >0x21 TIF> >0x0D TIF> >0x21 TIF> >0x42 TIF> >0x28 TIF> >0x0D TIF> >0x28 TIF> >0x0D TIF> >0x28 TIF> >0x0D TIF> >0x21 TIF> >0x0D TIF> >0x21 TIF>AP[0]: Core foundAP[0]: AHB-AP ROM base: 0xE00FF000 >0x0D TIF> >0x28 TIF> >0x0D TIF> >0x28 TIF> >0x0D TIF> >0x28 TIF> >0x0D TIF> >0x21 TIF> >0x0D TIF> >0x21 TIF>CPUID register: 0x412FC231. Implementer code: 0x41 (ARM)Found Cortex-M3 r2p1, Little endian. -- Max. mem block: 0x00002C18 + -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_WriteMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE0002000)FPUnit: 6 code (BP) slots and 2 literal slots -- CPU_ReadMem(4 bytes @ 0xE000EDFC) -- CPU_WriteMem(4 bytes @ 0xE000EDFC) -- CPU_ReadMem(4 bytes @ 0xE0001000) -- CPU_WriteMem(4 bytes @ 0xE0001000) -- CPU_ReadMem(4 bytes @ 0xE000ED88) -- CPU_WriteMem(4 bytes @ 0xE000ED88) -- CPU_ReadMem(4 bytes @ 0xE000ED88) -- CPU_WriteMem(4 bytes @ 0xE000ED88)CoreSight components:ROMTbl[0] @ E00FF000 + -- CPU_ReadMem(16 bytes @ 0xE00FF000) -- CPU_ReadMem(16 bytes @ 0xE000EFF0) -- CPU_ReadMem(16 bytes @ 0xE000EFE0)ROMTbl[0][0]: E000E000, CID: B105E00D, PID: 000BB000 SCS -- CPU_ReadMem(16 bytes @ 0xE0001FF0) -- CPU_ReadMem(16 bytes @ 0xE0001FE0)ROMTbl[0][1]: E0001000, CID: B105E00D, PID: 003BB002 DWT -- CPU_ReadMem(16 bytes @ 0xE0002FF0) -- CPU_ReadMem(16 bytes @ 0xE0002FE0)ROMTbl[0][2]: E0002000, CID: B105E00D, PID: 002BB003 FPB -- CPU_ReadMem(16 bytes @ 0xE0000FF0) + -- CPU_ReadMem(16 bytes @ 0xE0000FE0)ROMTbl[0][3]: E0000000, CID: B105E00D, PID: 003BB001 ITM -- CPU_ReadMem(16 bytes @ 0xE00FF010) -- CPU_ReadMem(16 bytes @ 0xE0040FF0) -- CPU_ReadMem(16 bytes @ 0xE0040FE0)ROMTbl[0][4]: E0040000, CID: B105900D, PID: 003BB923 TPIU-Lite -- CPU_ReadMem(16 bytes @ 0xE0041FF0) -- CPU_ReadMem(16 bytes @ 0xE0041FE0)ROMTbl[0][5]: E0041000, CID: B105900D, PID: 003BB924 ETM-M3 >0x0D TIF> >0x21 TIF> returns 0x2BA01477 (1396ms, 23405ms total) +T3170 083:099 JLINK_GetDLLVersion() returns 63209 (0001ms, 23406ms total) +T3170 083:103 JLINK_CORE_GetFound() returns 0x30000FF (0000ms, 23406ms total) +T3170 083:103 JLINK_GetDebugInfo(0x100 = JLINKARM_ROM_TABLE_ADDR_INDEX) -- Value=0xE00FF000 returns 0x00 (0000ms, 23406ms total) +T3170 083:110 JLINK_GetDebugInfo(0x100 = JLINKARM_ROM_TABLE_ADDR_INDEX) -- Value=0xE00FF000 returns 0x00 (0000ms, 23406ms total) +T3170 083:110 JLINK_GetDebugInfo(0x101 = JLINKARM_DEBUG_INFO_ETM_ADDR_INDEX) -- Value=0xE0041000 returns 0x00 (0000ms, 23406ms total) +T3170 083:110 JLINK_ReadMemEx(0xE0041FD0, 0x0020 Bytes, ..., Flags = 0x02000004) -- CPU_ReadMem(32 bytes @ 0xE0041FD0) - Data: 04 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 ... returns 0x20 (0004ms, 23410ms total) +T3170 083:114 JLINK_GetDebugInfo(0x102 = JLINKARM_DEBUG_INFO_MTB_ADDR_INDEX) -- Value=0x00000000 returns 0x00 (0000ms, 23410ms total) +T3170 083:114 JLINK_GetDebugInfo(0x103 = JLINKARM_DEBUG_INFO_TPIU_ADDR_INDEX) -- Value=0xE0040000 returns 0x00 (0000ms, 23410ms total) +T3170 083:114 JLINK_GetDebugInfo(0x104 = JLINKARM_DEBUG_INFO_ITM_ADDR_INDEX) -- Value=0xE0000000 returns 0x00 (0000ms, 23410ms total) +T3170 083:114 JLINK_GetDebugInfo(0x105 = JLINKARM_DEBUG_INFO_DWT_ADDR_INDEX) -- Value=0xE0001000 returns 0x00 (0000ms, 23410ms total) +T3170 083:114 JLINK_GetDebugInfo(0x106 = JLINKARM_DEBUG_INFO_FPB_ADDR_INDEX) -- Value=0xE0002000 returns 0x00 (0000ms, 23410ms total) +T3170 083:114 JLINK_GetDebugInfo(0x107 = JLINKARM_DEBUG_INFO_NVIC_ADDR_INDEX) -- Value=0xE000E000 returns 0x00 (0000ms, 23410ms total) +T3170 083:114 JLINK_GetDebugInfo(0x10C = JLINKARM_DEBUG_INFO_DBG_ADDR_INDEX) -- Value=0xE000EDF0 returns 0x00 (0000ms, 23410ms total) +T3170 083:114 JLINK_GetDebugInfo(0x01 = Unknown) -- Value=0x00000000 returns 0x00 (0000ms, 23410ms total) +T3170 083:114 JLINK_ReadMemU32(0xE000ED00, 0x0001 Items, ...) -- CPU_ReadMem(4 bytes @ 0xE000ED00) - Data: 31 C2 2F 41 returns 0x01 (0034ms, 23444ms total) +T3170 083:148 JLINK_GetDebugInfo(0x10F = JLINKARM_DEBUG_INFO_HAS_CORTEX_M_SECURITY_EXT_INDEX) -- Value=0x00000000 returns 0x00 (0000ms, 23444ms total) +T3170 083:148 JLINK_SetResetType(JLINKARM_CM3_RESET_TYPE_NORMAL) returns JLINKARM_CM3_RESET_TYPE_NORMAL (0000ms, 23444ms total) +T3170 083:148 JLINK_Reset() -- CPU is running -- CPU_WriteMem(4 bytes @ 0xE000EDF0) -- CPU is running -- CPU_WriteMem(4 bytes @ 0xE000EDFC)Reset: Halt core after reset via DEMCR.VC_CORERESET. >0x35 TIF>Reset: Reset device via AIRCR.SYSRESETREQ. -- CPU is running -- CPU_WriteMem(4 bytes @ 0xE000ED0C) >0x0D TIF> >0x28 TIF> -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU is running -- CPU_WriteMem(4 bytes @ 0xE000EDF0) -- CPU is running -- CPU_WriteMem(4 bytes @ 0xE000EDFC) + -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_WriteMem(4 bytes @ 0xE0002000) -- CPU_ReadMem(4 bytes @ 0xE000EDFC) -- CPU_ReadMem(4 bytes @ 0xE0001000) (0262ms, 23706ms total) +T3170 083:410 JLINK_Halt() returns 0x00 (0000ms, 23706ms total) +T3170 083:410 JLINK_ReadMemU32(0xE000EDF0, 0x0001 Items, ...) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) - Data: 03 00 03 00 returns 0x01 (0002ms, 23708ms total) +T3170 083:412 JLINK_WriteU32(0xE000EDF0, 0xA05F0003) -- CPU_WriteMem(4 bytes @ 0xE000EDF0) returns 0x00 (0003ms, 23711ms total) +T3170 083:415 JLINK_WriteU32(0xE000EDFC, 0x01000000) -- CPU_WriteMem(4 bytes @ 0xE000EDFC) returns 0x00 (0084ms, 23795ms total) +T3170 083:513 JLINK_GetHWStatus(...) returns 0x00 (0002ms, 23797ms total) +T3170 083:524 JLINK_GetNumBPUnits(Type = 0xFFFFFF00) returns 0x06 (0000ms, 23797ms total) +T3170 083:524 JLINK_GetNumBPUnits(Type = 0xF0) returns 0x2000 (0000ms, 23797ms total) +T3170 083:524 JLINK_GetNumWPUnits() returns 0x04 (0000ms, 23797ms total) +T3170 083:535 JLINK_GetSpeed() returns 0xFA0 (0000ms, 23797ms total) +T3170 083:544 JLINK_ReadMemU32(0xE000E004, 0x0001 Items, ...) -- CPU_ReadMem(4 bytes @ 0xE000E004) - Data: 02 00 00 00 returns 0x01 (0055ms, 23852ms total) +T3170 083:599 JLINK_ReadMemU32(0xE000E004, 0x0001 Items, ...) -- CPU_ReadMem(4 bytes @ 0xE000E004) - Data: 02 00 00 00 returns 0x01 (0003ms, 23855ms total) +T3170 083:602 JLINK_WriteMemEx(0xE0001000, 0x001C Bytes, ..., Flags = 0x02000004) - Data: 01 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 ... -- CPU_WriteMem(28 bytes @ 0xE0001000) returns 0x1C (0003ms, 23858ms total) +T3170 083:605 JLINK_Halt() returns 0x00 (0000ms, 23858ms total) +T3170 083:605 JLINK_IsHalted() returns TRUE (0000ms, 23858ms total) +T3170 083:607 JLINK_WriteMem(0x20000000, 0x0144 Bytes, ...) - Data: 00 BE 0A E0 0D 78 2D 06 68 40 08 24 40 00 00 D3 ... -- CPU_WriteMem(324 bytes @ 0x20000000) returns 0x144 (0005ms, 23863ms total) +T3170 083:612 JLINK_WriteReg(R0, 0x00000000) returns 0x00 (0001ms, 23864ms total) +T3170 083:613 JLINK_WriteReg(R1, 0x05F5E100) returns 0x00 (0000ms, 23864ms total) +T3170 083:613 JLINK_WriteReg(R2, 0x00000001) returns 0x00 (0000ms, 23864ms total) +T3170 083:613 JLINK_WriteReg(R3, 0x00000000) returns 0x00 (0000ms, 23864ms total) +T3170 083:613 JLINK_WriteReg(R4, 0x00000000) returns 0x00 (0000ms, 23864ms total) +T3170 083:613 JLINK_WriteReg(R5, 0x00000000) returns 0x00 (0000ms, 23864ms total) +T3170 083:613 JLINK_WriteReg(R6, 0x00000000) returns 0x00 (0000ms, 23864ms total) +T3170 083:613 JLINK_WriteReg(R7, 0x00000000) returns 0x00 (0000ms, 23864ms total) +T3170 083:613 JLINK_WriteReg(R8, 0x00000000) returns 0x00 (0000ms, 23864ms total) +T3170 083:613 JLINK_WriteReg(R9, 0x2000013C) returns 0x00 (0000ms, 23864ms total) +T3170 083:613 JLINK_WriteReg(R10, 0x00000000) returns 0x00 (0000ms, 23864ms total) +T3170 083:613 JLINK_WriteReg(R11, 0x00000000) returns 0x00 (0000ms, 23864ms total) +T3170 083:613 JLINK_WriteReg(R12, 0x00000000) returns 0x00 (0000ms, 23864ms total) +T3170 083:613 JLINK_WriteReg(R13 (SP), 0x20001000) returns 0x00 (0000ms, 23864ms total) +T3170 083:613 JLINK_WriteReg(R14, 0x20000001) returns 0x00 (0000ms, 23864ms total) +T3170 083:613 JLINK_WriteReg(R15 (PC), 0x20000040) returns 0x00 (0000ms, 23864ms total) +T3170 083:613 JLINK_WriteReg(XPSR, 0x01000000) returns 0x00 (0000ms, 23864ms total) +T3170 083:613 JLINK_WriteReg(MSP, 0x20001000) returns 0x00 (0000ms, 23864ms total) +T3170 083:613 JLINK_WriteReg(PSP, 0x20001000) returns 0x00 (0000ms, 23864ms total) +T3170 083:613 JLINK_WriteReg(CFBP, 0x00000000) returns 0x00 (0000ms, 23864ms total) +T3170 083:613 JLINK_SetBPEx(Addr = 0x20000000, Type = 0xFFFFFFF2) -- CPU_ReadMem(2 bytes @ 0x20000000) returns 0x00000001 (0002ms, 23866ms total) +T3170 083:615 JLINK_Go() -- CPU_WriteMem(2 bytes @ 0x20000000) -- CPU_ReadMem(4 bytes @ 0xE0001000) -- CPU_WriteMem(4 bytes @ 0xE0002008) -- CPU_WriteMem(4 bytes @ 0xE000200C) -- CPU_WriteMem(4 bytes @ 0xE0002010) -- CPU_WriteMem(4 bytes @ 0xE0002014) -- CPU_WriteMem(4 bytes @ 0xE0002018) -- CPU_WriteMem(4 bytes @ 0xE000201C) -- CPU_WriteMem(4 bytes @ 0xE0001004) (0099ms, 23965ms total) +T3170 083:715 JLINK_IsHalted() -- CPU_ReadMem(2 bytes @ 0x20000000) returns TRUE (0091ms, 24056ms total) +T3170 083:806 JLINK_ReadReg(R15 (PC)) returns 0x20000000 (0000ms, 23965ms total) +T3170 083:806 JLINK_ClrBPEx(BPHandle = 0x00000001) returns 0x00 (0000ms, 23965ms total) +T3170 083:806 JLINK_ReadReg(R0) returns 0x00000000 (0000ms, 23965ms total) +T3170 083:807 JLINK_WriteReg(R0, 0x00000000) returns 0x00 (0000ms, 23965ms total) +T3170 083:807 JLINK_WriteReg(R1, 0x00001000) returns 0x00 (0000ms, 23965ms total) +T3170 083:807 JLINK_WriteReg(R2, 0x000000FF) returns 0x00 (0000ms, 23965ms total) +T3170 083:807 JLINK_WriteReg(R3, 0x00000000) returns 0x00 (0000ms, 23965ms total) +T3170 083:807 JLINK_WriteReg(R4, 0x00000000) returns 0x00 (0000ms, 23965ms total) +T3170 083:807 JLINK_WriteReg(R5, 0x00000000) returns 0x00 (0000ms, 23965ms total) +T3170 083:807 JLINK_WriteReg(R6, 0x00000000) returns 0x00 (0000ms, 23965ms total) +T3170 083:807 JLINK_WriteReg(R7, 0x00000000) returns 0x00 (0000ms, 23965ms total) +T3170 083:807 JLINK_WriteReg(R8, 0x00000000) returns 0x00 (0000ms, 23965ms total) +T3170 083:807 JLINK_WriteReg(R9, 0x2000013C) returns 0x00 (0000ms, 23965ms total) +T3170 083:807 JLINK_WriteReg(R10, 0x00000000) returns 0x00 (0000ms, 23965ms total) +T3170 083:807 JLINK_WriteReg(R11, 0x00000000) returns 0x00 (0000ms, 23965ms total) +T3170 083:807 JLINK_WriteReg(R12, 0x00000000) returns 0x00 (0000ms, 23965ms total) +T3170 083:807 JLINK_WriteReg(R13 (SP), 0x20001000) returns 0x00 (0000ms, 23965ms total) +T3170 083:807 JLINK_WriteReg(R14, 0x20000001) returns 0x00 (0000ms, 23965ms total) +T3170 083:807 JLINK_WriteReg(R15 (PC), 0x20000020) returns 0x00 (0000ms, 23965ms total) +T3170 083:807 JLINK_WriteReg(XPSR, 0x01000000) returns 0x00 (0000ms, 23965ms total) +T3170 083:807 JLINK_WriteReg(MSP, 0x20001000) returns 0x00 (0000ms, 23965ms total) +T3170 083:807 JLINK_WriteReg(PSP, 0x20001000) returns 0x00 (0000ms, 23965ms total) +T3170 083:807 JLINK_WriteReg(CFBP, 0x00000000) returns 0x00 (0000ms, 23965ms total) +T3170 083:807 JLINK_SetBPEx(Addr = 0x20000000, Type = 0xFFFFFFF2) returns 0x00000002 (0000ms, 23965ms total) +T3170 083:807 JLINK_Go() -- CPU_ReadMem(4 bytes @ 0xE0001000) (0008ms, 23973ms total) +T3170 083:815 JLINK_IsHalted() -- CPU_ReadMem(2 bytes @ 0x20000000) returns TRUE (0090ms, 24063ms total) +T3170 083:906 JLINK_ReadReg(R15 (PC)) returns 0x20000000 (0000ms, 23973ms total) +T3170 083:906 JLINK_ClrBPEx(BPHandle = 0x00000002) returns 0x00 (0000ms, 23973ms total) +T3170 083:906 JLINK_ReadReg(R0) returns 0x00000001 (0000ms, 23973ms total) +T3170 083:906 JLINK_WriteReg(R0, 0x00000000) returns 0x00 (0000ms, 23973ms total) +T3170 083:906 JLINK_WriteReg(R1, 0x00001000) returns 0x00 (0000ms, 23973ms total) +T3170 083:906 JLINK_WriteReg(R2, 0x000000FF) returns 0x00 (0000ms, 23973ms total) +T3170 083:906 JLINK_WriteReg(R3, 0x00000000) returns 0x00 (0000ms, 23973ms total) +T3170 083:906 JLINK_WriteReg(R4, 0x00000000) returns 0x00 (0000ms, 23973ms total) +T3170 083:906 JLINK_WriteReg(R5, 0x00000000) returns 0x00 (0000ms, 23973ms total) +T3170 083:906 JLINK_WriteReg(R6, 0x00000000) returns 0x00 (0000ms, 23973ms total) +T3170 083:906 JLINK_WriteReg(R7, 0x00000000) returns 0x00 (0000ms, 23973ms total) +T3170 083:906 JLINK_WriteReg(R8, 0x00000000) returns 0x00 (0000ms, 23973ms total) +T3170 083:906 JLINK_WriteReg(R9, 0x2000013C) returns 0x00 (0000ms, 23973ms total) +T3170 083:906 JLINK_WriteReg(R10, 0x00000000) returns 0x00 (0000ms, 23973ms total) +T3170 083:906 JLINK_WriteReg(R11, 0x00000000) returns 0x00 (0000ms, 23973ms total) +T3170 083:906 JLINK_WriteReg(R12, 0x00000000) returns 0x00 (0000ms, 23973ms total) +T3170 083:906 JLINK_WriteReg(R13 (SP), 0x20001000) returns 0x00 (0000ms, 23973ms total) +T3170 083:906 JLINK_WriteReg(R14, 0x20000001) returns 0x00 (0000ms, 23973ms total) +T3170 083:906 JLINK_WriteReg(R15 (PC), 0x20000058) returns 0x00 (0000ms, 23973ms total) +T3170 083:906 JLINK_WriteReg(XPSR, 0x01000000) returns 0x00 (0000ms, 23973ms total) +T3170 083:906 JLINK_WriteReg(MSP, 0x20001000) returns 0x00 (0000ms, 23973ms total) +T3170 083:906 JLINK_WriteReg(PSP, 0x20001000) returns 0x00 (0000ms, 23973ms total) +T3170 083:906 JLINK_WriteReg(CFBP, 0x00000000) returns 0x00 (0000ms, 23973ms total) +T3170 083:906 JLINK_SetBPEx(Addr = 0x20000000, Type = 0xFFFFFFF2) returns 0x00000003 (0000ms, 23973ms total) +T3170 083:906 JLINK_Go() -- CPU_ReadMem(4 bytes @ 0xE0001000) (0007ms, 23980ms total) +T3170 083:913 JLINK_IsHalted() -- CPU_ReadMem(2 bytes @ 0x20000000) returns TRUE (0093ms, 24073ms total) +T3170 084:006 JLINK_ReadReg(R15 (PC)) returns 0x20000000 (0000ms, 23980ms total) +T3170 084:006 JLINK_ClrBPEx(BPHandle = 0x00000003) returns 0x00 (0000ms, 23980ms total) +T3170 084:006 JLINK_ReadReg(R0) returns 0x00000000 (0000ms, 23980ms total) +T3170 084:007 JLINK_WriteReg(R0, 0x00001000) returns 0x00 (0000ms, 23980ms total) +T3170 084:007 JLINK_WriteReg(R1, 0x00001000) returns 0x00 (0000ms, 23980ms total) +T3170 084:007 JLINK_WriteReg(R2, 0x000000FF) returns 0x00 (0000ms, 23980ms total) +T3170 084:007 JLINK_WriteReg(R3, 0x00000000) returns 0x00 (0000ms, 23980ms total) +T3170 084:007 JLINK_WriteReg(R4, 0x00000000) returns 0x00 (0000ms, 23980ms total) +T3170 084:007 JLINK_WriteReg(R5, 0x00000000) returns 0x00 (0000ms, 23980ms total) +T3170 084:007 JLINK_WriteReg(R6, 0x00000000) returns 0x00 (0000ms, 23980ms total) +T3170 084:007 JLINK_WriteReg(R7, 0x00000000) returns 0x00 (0000ms, 23980ms total) +T3170 084:007 JLINK_WriteReg(R8, 0x00000000) returns 0x00 (0000ms, 23980ms total) +T3170 084:007 JLINK_WriteReg(R9, 0x2000013C) returns 0x00 (0000ms, 23980ms total) +T3170 084:007 JLINK_WriteReg(R10, 0x00000000) returns 0x00 (0000ms, 23980ms total) +T3170 084:007 JLINK_WriteReg(R11, 0x00000000) returns 0x00 (0000ms, 23980ms total) +T3170 084:007 JLINK_WriteReg(R12, 0x00000000) returns 0x00 (0000ms, 23980ms total) +T3170 084:007 JLINK_WriteReg(R13 (SP), 0x20001000) returns 0x00 (0000ms, 23980ms total) +T3170 084:007 JLINK_WriteReg(R14, 0x20000001) returns 0x00 (0000ms, 23980ms total) +T3170 084:007 JLINK_WriteReg(R15 (PC), 0x20000020) returns 0x00 (0000ms, 23980ms total) +T3170 084:007 JLINK_WriteReg(XPSR, 0x01000000) returns 0x00 (0000ms, 23980ms total) +T3170 084:007 JLINK_WriteReg(MSP, 0x20001000) returns 0x00 (0000ms, 23980ms total) +T3170 084:007 JLINK_WriteReg(PSP, 0x20001000) returns 0x00 (0000ms, 23980ms total) +T3170 084:007 JLINK_WriteReg(CFBP, 0x00000000) returns 0x00 (0000ms, 23980ms total) +T3170 084:007 JLINK_SetBPEx(Addr = 0x20000000, Type = 0xFFFFFFF2) returns 0x00000004 (0000ms, 23980ms total) +T3170 084:007 JLINK_Go() -- CPU_ReadMem(4 bytes @ 0xE0001000) (0007ms, 23987ms total) +T3170 084:014 JLINK_IsHalted() -- CPU_ReadMem(2 bytes @ 0x20000000) returns TRUE (0090ms, 24077ms total) +T3170 084:104 JLINK_ReadReg(R15 (PC)) returns 0x20000000 (0000ms, 23987ms total) +T3170 084:104 JLINK_ClrBPEx(BPHandle = 0x00000004) returns 0x00 (0000ms, 23987ms total) +T3170 084:104 JLINK_ReadReg(R0) returns 0x00000001 (0000ms, 23987ms total) +T3170 084:104 JLINK_WriteReg(R0, 0x00001000) returns 0x00 (0000ms, 23987ms total) +T3170 084:104 JLINK_WriteReg(R1, 0x00001000) returns 0x00 (0000ms, 23987ms total) +T3170 084:104 JLINK_WriteReg(R2, 0x000000FF) returns 0x00 (0000ms, 23987ms total) +T3170 084:104 JLINK_WriteReg(R3, 0x00000000) returns 0x00 (0000ms, 23987ms total) +T3170 084:104 JLINK_WriteReg(R4, 0x00000000) returns 0x00 (0000ms, 23987ms total) +T3170 084:104 JLINK_WriteReg(R5, 0x00000000) returns 0x00 (0000ms, 23987ms total) +T3170 084:104 JLINK_WriteReg(R6, 0x00000000) returns 0x00 (0000ms, 23987ms total) +T3170 084:104 JLINK_WriteReg(R7, 0x00000000) returns 0x00 (0000ms, 23987ms total) +T3170 084:104 JLINK_WriteReg(R8, 0x00000000) returns 0x00 (0000ms, 23987ms total) +T3170 084:104 JLINK_WriteReg(R9, 0x2000013C) returns 0x00 (0000ms, 23987ms total) +T3170 084:104 JLINK_WriteReg(R10, 0x00000000) returns 0x00 (0000ms, 23987ms total) +T3170 084:104 JLINK_WriteReg(R11, 0x00000000) returns 0x00 (0000ms, 23987ms total) +T3170 084:104 JLINK_WriteReg(R12, 0x00000000) returns 0x00 (0000ms, 23987ms total) +T3170 084:104 JLINK_WriteReg(R13 (SP), 0x20001000) returns 0x00 (0000ms, 23987ms total) +T3170 084:104 JLINK_WriteReg(R14, 0x20000001) returns 0x00 (0000ms, 23987ms total) +T3170 084:104 JLINK_WriteReg(R15 (PC), 0x20000058) returns 0x00 (0000ms, 23987ms total) +T3170 084:104 JLINK_WriteReg(XPSR, 0x01000000) returns 0x00 (0000ms, 23987ms total) +T3170 084:104 JLINK_WriteReg(MSP, 0x20001000) returns 0x00 (0000ms, 23987ms total) +T3170 084:104 JLINK_WriteReg(PSP, 0x20001000) returns 0x00 (0001ms, 23988ms total) +T3170 084:105 JLINK_WriteReg(CFBP, 0x00000000) returns 0x00 (0000ms, 23988ms total) +T3170 084:105 JLINK_SetBPEx(Addr = 0x20000000, Type = 0xFFFFFFF2) returns 0x00000005 (0000ms, 23988ms total) +T3170 084:105 JLINK_Go() -- CPU_ReadMem(4 bytes @ 0xE0001000) (0007ms, 23995ms total) +T3170 084:112 JLINK_IsHalted() -- CPU_ReadMem(2 bytes @ 0x20000000) returns TRUE (0087ms, 24082ms total) +T3170 084:199 JLINK_ReadReg(R15 (PC)) returns 0x20000000 (0000ms, 23995ms total) +T3170 084:203 JLINK_ClrBPEx(BPHandle = 0x00000005) returns 0x00 (0000ms, 23995ms total) +T3170 084:203 JLINK_ReadReg(R0) returns 0x00000000 (0000ms, 23995ms total) +T3170 084:203 JLINK_WriteReg(R0, 0x00002000) returns 0x00 (0000ms, 23995ms total) +T3170 084:203 JLINK_WriteReg(R1, 0x00001000) returns 0x00 (0000ms, 23995ms total) +T3170 084:203 JLINK_WriteReg(R2, 0x000000FF) returns 0x00 (0000ms, 23995ms total) +T3170 084:203 JLINK_WriteReg(R3, 0x00000000) returns 0x00 (0000ms, 23995ms total) +T3170 084:203 JLINK_WriteReg(R4, 0x00000000) returns 0x00 (0000ms, 23995ms total) +T3170 084:203 JLINK_WriteReg(R5, 0x00000000) returns 0x00 (0000ms, 23995ms total) +T3170 084:203 JLINK_WriteReg(R6, 0x00000000) returns 0x00 (0000ms, 23995ms total) +T3170 084:203 JLINK_WriteReg(R7, 0x00000000) returns 0x00 (0000ms, 23995ms total) +T3170 084:203 JLINK_WriteReg(R8, 0x00000000) returns 0x00 (0000ms, 23995ms total) +T3170 084:203 JLINK_WriteReg(R9, 0x2000013C) returns 0x00 (0000ms, 23995ms total) +T3170 084:203 JLINK_WriteReg(R10, 0x00000000) returns 0x00 (0000ms, 23995ms total) +T3170 084:203 JLINK_WriteReg(R11, 0x00000000) returns 0x00 (0000ms, 23995ms total) +T3170 084:203 JLINK_WriteReg(R12, 0x00000000) returns 0x00 (0000ms, 23995ms total) +T3170 084:203 JLINK_WriteReg(R13 (SP), 0x20001000) returns 0x00 (0000ms, 23995ms total) +T3170 084:203 JLINK_WriteReg(R14, 0x20000001) returns 0x00 (0000ms, 23995ms total) +T3170 084:203 JLINK_WriteReg(R15 (PC), 0x20000020) returns 0x00 (0000ms, 23995ms total) +T3170 084:203 JLINK_WriteReg(XPSR, 0x01000000) returns 0x00 (0000ms, 23995ms total) +T3170 084:203 JLINK_WriteReg(MSP, 0x20001000) returns 0x00 (0000ms, 23995ms total) +T3170 084:203 JLINK_WriteReg(PSP, 0x20001000) returns 0x00 (0000ms, 23995ms total) +T3170 084:203 JLINK_WriteReg(CFBP, 0x00000000) returns 0x00 (0000ms, 23995ms total) +T3170 084:203 JLINK_SetBPEx(Addr = 0x20000000, Type = 0xFFFFFFF2) returns 0x00000006 (0000ms, 23995ms total) +T3170 084:203 JLINK_Go() -- CPU_ReadMem(4 bytes @ 0xE0001000) (0008ms, 24003ms total) +T3170 084:211 JLINK_IsHalted() -- CPU_ReadMem(2 bytes @ 0x20000000) returns TRUE (0062ms, 24065ms total) +T3170 084:273 JLINK_ReadReg(R15 (PC)) returns 0x20000000 (0000ms, 24003ms total) +T3170 084:273 JLINK_ClrBPEx(BPHandle = 0x00000006) returns 0x00 (0000ms, 24003ms total) +T3170 084:273 JLINK_ReadReg(R0) returns 0x00000001 (0000ms, 24003ms total) +T3170 084:273 JLINK_WriteReg(R0, 0x00002000) returns 0x00 (0000ms, 24003ms total) +T3170 084:273 JLINK_WriteReg(R1, 0x00001000) returns 0x00 (0000ms, 24003ms total) +T3170 084:273 JLINK_WriteReg(R2, 0x000000FF) returns 0x00 (0000ms, 24003ms total) +T3170 084:273 JLINK_WriteReg(R3, 0x00000000) returns 0x00 (0000ms, 24003ms total) +T3170 084:273 JLINK_WriteReg(R4, 0x00000000) returns 0x00 (0000ms, 24003ms total) +T3170 084:273 JLINK_WriteReg(R5, 0x00000000) returns 0x00 (0000ms, 24003ms total) +T3170 084:273 JLINK_WriteReg(R6, 0x00000000) returns 0x00 (0000ms, 24003ms total) +T3170 084:273 JLINK_WriteReg(R7, 0x00000000) returns 0x00 (0001ms, 24004ms total) +T3170 084:274 JLINK_WriteReg(R8, 0x00000000) returns 0x00 (0000ms, 24004ms total) +T3170 084:274 JLINK_WriteReg(R9, 0x2000013C) returns 0x00 (0000ms, 24004ms total) +T3170 084:274 JLINK_WriteReg(R10, 0x00000000) returns 0x00 (0000ms, 24004ms total) +T3170 084:274 JLINK_WriteReg(R11, 0x00000000) returns 0x00 (0000ms, 24004ms total) +T3170 084:274 JLINK_WriteReg(R12, 0x00000000) returns 0x00 (0000ms, 24004ms total) +T3170 084:274 JLINK_WriteReg(R13 (SP), 0x20001000) returns 0x00 (0000ms, 24004ms total) +T3170 084:274 JLINK_WriteReg(R14, 0x20000001) returns 0x00 (0000ms, 24004ms total) +T3170 084:274 JLINK_WriteReg(R15 (PC), 0x20000058) returns 0x00 (0000ms, 24004ms total) +T3170 084:274 JLINK_WriteReg(XPSR, 0x01000000) returns 0x00 (0000ms, 24004ms total) +T3170 084:274 JLINK_WriteReg(MSP, 0x20001000) returns 0x00 (0000ms, 24004ms total) +T3170 084:274 JLINK_WriteReg(PSP, 0x20001000) returns 0x00 (0000ms, 24004ms total) +T3170 084:274 JLINK_WriteReg(CFBP, 0x00000000) returns 0x00 (0000ms, 24004ms total) +T3170 084:274 JLINK_SetBPEx(Addr = 0x20000000, Type = 0xFFFFFFF2) returns 0x00000007 (0000ms, 24004ms total) +T3170 084:274 JLINK_Go() -- CPU_ReadMem(4 bytes @ 0xE0001000) (0030ms, 24034ms total) +T3170 084:305 JLINK_IsHalted() -- CPU_ReadMem(2 bytes @ 0x20000000) returns TRUE (0009ms, 24043ms total) +T3170 084:314 JLINK_ReadReg(R15 (PC)) returns 0x20000000 (0000ms, 24034ms total) +T3170 084:314 JLINK_ClrBPEx(BPHandle = 0x00000007) returns 0x00 (0000ms, 24034ms total) +T3170 084:314 JLINK_ReadReg(R0) returns 0x00000000 (0000ms, 24034ms total) +T3170 084:314 JLINK_WriteReg(R0, 0x00003000) returns 0x00 (0000ms, 24034ms total) +T3170 084:314 JLINK_WriteReg(R1, 0x00001000) returns 0x00 (0000ms, 24034ms total) +T3170 084:314 JLINK_WriteReg(R2, 0x000000FF) returns 0x00 (0000ms, 24034ms total) +T3170 084:314 JLINK_WriteReg(R3, 0x00000000) returns 0x00 (0000ms, 24034ms total) +T3170 084:314 JLINK_WriteReg(R4, 0x00000000) returns 0x00 (0000ms, 24034ms total) +T3170 084:314 JLINK_WriteReg(R5, 0x00000000) returns 0x00 (0000ms, 24034ms total) +T3170 084:314 JLINK_WriteReg(R6, 0x00000000) returns 0x00 (0000ms, 24034ms total) +T3170 084:314 JLINK_WriteReg(R7, 0x00000000) returns 0x00 (0000ms, 24034ms total) +T3170 084:314 JLINK_WriteReg(R8, 0x00000000) returns 0x00 (0000ms, 24034ms total) +T3170 084:314 JLINK_WriteReg(R9, 0x2000013C) returns 0x00 (0000ms, 24034ms total) +T3170 084:314 JLINK_WriteReg(R10, 0x00000000) returns 0x00 (0000ms, 24034ms total) +T3170 084:314 JLINK_WriteReg(R11, 0x00000000) returns 0x00 (0000ms, 24034ms total) +T3170 084:314 JLINK_WriteReg(R12, 0x00000000) returns 0x00 (0000ms, 24034ms total) +T3170 084:314 JLINK_WriteReg(R13 (SP), 0x20001000) returns 0x00 (0000ms, 24034ms total) +T3170 084:314 JLINK_WriteReg(R14, 0x20000001) returns 0x00 (0000ms, 24034ms total) +T3170 084:314 JLINK_WriteReg(R15 (PC), 0x20000020) returns 0x00 (0000ms, 24034ms total) +T3170 084:314 JLINK_WriteReg(XPSR, 0x01000000) returns 0x00 (0000ms, 24034ms total) +T3170 084:314 JLINK_WriteReg(MSP, 0x20001000) returns 0x00 (0000ms, 24034ms total) +T3170 084:314 JLINK_WriteReg(PSP, 0x20001000) returns 0x00 (0000ms, 24034ms total) +T3170 084:314 JLINK_WriteReg(CFBP, 0x00000000) returns 0x00 (0000ms, 24034ms total) +T3170 084:315 JLINK_SetBPEx(Addr = 0x20000000, Type = 0xFFFFFFF2) returns 0x00000008 (0000ms, 24035ms total) +T3170 084:315 JLINK_Go() -- CPU_ReadMem(4 bytes @ 0xE0001000) (0089ms, 24124ms total) +T3170 084:404 JLINK_IsHalted() -- CPU_ReadMem(2 bytes @ 0x20000000) returns TRUE (0007ms, 24131ms total) +T3170 084:411 JLINK_ReadReg(R15 (PC)) returns 0x20000000 (0000ms, 24124ms total) +T3170 084:411 JLINK_ClrBPEx(BPHandle = 0x00000008) returns 0x00 (0000ms, 24124ms total) +T3170 084:411 JLINK_ReadReg(R0) returns 0x00000001 (0000ms, 24124ms total) +T3170 084:411 JLINK_WriteReg(R0, 0x00003000) returns 0x00 (0000ms, 24124ms total) +T3170 084:411 JLINK_WriteReg(R1, 0x00001000) returns 0x00 (0000ms, 24124ms total) +T3170 084:411 JLINK_WriteReg(R2, 0x000000FF) returns 0x00 (0000ms, 24124ms total) +T3170 084:411 JLINK_WriteReg(R3, 0x00000000) returns 0x00 (0000ms, 24124ms total) +T3170 084:411 JLINK_WriteReg(R4, 0x00000000) returns 0x00 (0000ms, 24124ms total) +T3170 084:411 JLINK_WriteReg(R5, 0x00000000) returns 0x00 (0000ms, 24124ms total) +T3170 084:411 JLINK_WriteReg(R6, 0x00000000) returns 0x00 (0000ms, 24124ms total) +T3170 084:411 JLINK_WriteReg(R7, 0x00000000) returns 0x00 (0000ms, 24124ms total) +T3170 084:411 JLINK_WriteReg(R8, 0x00000000) returns 0x00 (0000ms, 24124ms total) +T3170 084:411 JLINK_WriteReg(R9, 0x2000013C) returns 0x00 (0000ms, 24124ms total) +T3170 084:411 JLINK_WriteReg(R10, 0x00000000) returns 0x00 (0000ms, 24124ms total) +T3170 084:411 JLINK_WriteReg(R11, 0x00000000) returns 0x00 (0000ms, 24124ms total) +T3170 084:411 JLINK_WriteReg(R12, 0x00000000) returns 0x00 (0000ms, 24124ms total) +T3170 084:411 JLINK_WriteReg(R13 (SP), 0x20001000) returns 0x00 (0000ms, 24124ms total) +T3170 084:411 JLINK_WriteReg(R14, 0x20000001) returns 0x00 (0000ms, 24124ms total) +T3170 084:411 JLINK_WriteReg(R15 (PC), 0x20000058) returns 0x00 (0001ms, 24125ms total) +T3170 084:412 JLINK_WriteReg(XPSR, 0x01000000) returns 0x00 (0000ms, 24125ms total) +T3170 084:412 JLINK_WriteReg(MSP, 0x20001000) returns 0x00 (0000ms, 24125ms total) +T3170 084:412 JLINK_WriteReg(PSP, 0x20001000) returns 0x00 (0000ms, 24125ms total) +T3170 084:412 JLINK_WriteReg(CFBP, 0x00000000) returns 0x00 (0000ms, 24125ms total) +T3170 084:412 JLINK_SetBPEx(Addr = 0x20000000, Type = 0xFFFFFFF2) returns 0x00000009 (0000ms, 24125ms total) +T3170 084:412 JLINK_Go() -- CPU_ReadMem(4 bytes @ 0xE0001000) (0087ms, 24212ms total) +T3170 084:499 JLINK_IsHalted() -- CPU_ReadMem(2 bytes @ 0x20000000) returns TRUE (0007ms, 24219ms total) +T3170 084:506 JLINK_ReadReg(R15 (PC)) returns 0x20000000 (0000ms, 24212ms total) +T3170 084:506 JLINK_ClrBPEx(BPHandle = 0x00000009) returns 0x00 (0000ms, 24212ms total) +T3170 084:506 JLINK_ReadReg(R0) returns 0x00000000 (0000ms, 24212ms total) +T3170 084:506 JLINK_WriteReg(R0, 0x00004000) returns 0x00 (0000ms, 24212ms total) +T3170 084:506 JLINK_WriteReg(R1, 0x00001000) returns 0x00 (0000ms, 24212ms total) +T3170 084:506 JLINK_WriteReg(R2, 0x000000FF) returns 0x00 (0000ms, 24212ms total) +T3170 084:506 JLINK_WriteReg(R3, 0x00000000) returns 0x00 (0000ms, 24212ms total) +T3170 084:506 JLINK_WriteReg(R4, 0x00000000) returns 0x00 (0000ms, 24212ms total) +T3170 084:506 JLINK_WriteReg(R5, 0x00000000) returns 0x00 (0000ms, 24212ms total) +T3170 084:506 JLINK_WriteReg(R6, 0x00000000) returns 0x00 (0000ms, 24212ms total) +T3170 084:506 JLINK_WriteReg(R7, 0x00000000) returns 0x00 (0000ms, 24212ms total) +T3170 084:506 JLINK_WriteReg(R8, 0x00000000) returns 0x00 (0000ms, 24212ms total) +T3170 084:506 JLINK_WriteReg(R9, 0x2000013C) returns 0x00 (0000ms, 24212ms total) +T3170 084:506 JLINK_WriteReg(R10, 0x00000000) returns 0x00 (0001ms, 24213ms total) +T3170 084:507 JLINK_WriteReg(R11, 0x00000000) returns 0x00 (0000ms, 24213ms total) +T3170 084:507 JLINK_WriteReg(R12, 0x00000000) returns 0x00 (0000ms, 24213ms total) +T3170 084:507 JLINK_WriteReg(R13 (SP), 0x20001000) returns 0x00 (0000ms, 24213ms total) +T3170 084:507 JLINK_WriteReg(R14, 0x20000001) returns 0x00 (0000ms, 24213ms total) +T3170 084:507 JLINK_WriteReg(R15 (PC), 0x20000020) returns 0x00 (0000ms, 24213ms total) +T3170 084:507 JLINK_WriteReg(XPSR, 0x01000000) returns 0x00 (0000ms, 24213ms total) +T3170 084:507 JLINK_WriteReg(MSP, 0x20001000) returns 0x00 (0000ms, 24213ms total) +T3170 084:507 JLINK_WriteReg(PSP, 0x20001000) returns 0x00 (0000ms, 24213ms total) +T3170 084:507 JLINK_WriteReg(CFBP, 0x00000000) returns 0x00 (0000ms, 24213ms total) +T3170 084:507 JLINK_SetBPEx(Addr = 0x20000000, Type = 0xFFFFFFF2) returns 0x0000000A (0000ms, 24213ms total) +T3170 084:507 JLINK_Go() -- CPU_ReadMem(4 bytes @ 0xE0001000) (0007ms, 24220ms total) +T3170 084:514 JLINK_IsHalted() -- CPU_ReadMem(2 bytes @ 0x20000000) returns TRUE (0090ms, 24310ms total) +T3170 084:604 JLINK_ReadReg(R15 (PC)) returns 0x20000000 (0000ms, 24220ms total) +T3170 084:607 JLINK_ClrBPEx(BPHandle = 0x0000000A) returns 0x00 (0000ms, 24220ms total) +T3170 084:607 JLINK_ReadReg(R0) returns 0x00000001 (0000ms, 24220ms total) +T3170 084:607 JLINK_WriteReg(R0, 0x00004000) returns 0x00 (0000ms, 24220ms total) +T3170 084:607 JLINK_WriteReg(R1, 0x00001000) returns 0x00 (0000ms, 24220ms total) +T3170 084:607 JLINK_WriteReg(R2, 0x000000FF) returns 0x00 (0000ms, 24220ms total) +T3170 084:607 JLINK_WriteReg(R3, 0x00000000) returns 0x00 (0000ms, 24220ms total) +T3170 084:607 JLINK_WriteReg(R4, 0x00000000) returns 0x00 (0000ms, 24220ms total) +T3170 084:607 JLINK_WriteReg(R5, 0x00000000) returns 0x00 (0000ms, 24220ms total) +T3170 084:607 JLINK_WriteReg(R6, 0x00000000) returns 0x00 (0001ms, 24221ms total) +T3170 084:608 JLINK_WriteReg(R7, 0x00000000) returns 0x00 (0000ms, 24221ms total) +T3170 084:608 JLINK_WriteReg(R8, 0x00000000) returns 0x00 (0000ms, 24221ms total) +T3170 084:608 JLINK_WriteReg(R9, 0x2000013C) returns 0x00 (0000ms, 24221ms total) +T3170 084:608 JLINK_WriteReg(R10, 0x00000000) returns 0x00 (0000ms, 24221ms total) +T3170 084:608 JLINK_WriteReg(R11, 0x00000000) returns 0x00 (0000ms, 24221ms total) +T3170 084:608 JLINK_WriteReg(R12, 0x00000000) returns 0x00 (0000ms, 24221ms total) +T3170 084:608 JLINK_WriteReg(R13 (SP), 0x20001000) returns 0x00 (0000ms, 24221ms total) +T3170 084:608 JLINK_WriteReg(R14, 0x20000001) returns 0x00 (0000ms, 24221ms total) +T3170 084:608 JLINK_WriteReg(R15 (PC), 0x20000058) returns 0x00 (0000ms, 24221ms total) +T3170 084:608 JLINK_WriteReg(XPSR, 0x01000000) returns 0x00 (0000ms, 24221ms total) +T3170 084:608 JLINK_WriteReg(MSP, 0x20001000) returns 0x00 (0000ms, 24221ms total) +T3170 084:608 JLINK_WriteReg(PSP, 0x20001000) returns 0x00 (0000ms, 24221ms total) +T3170 084:608 JLINK_WriteReg(CFBP, 0x00000000) returns 0x00 (0000ms, 24221ms total) +T3170 084:608 JLINK_SetBPEx(Addr = 0x20000000, Type = 0xFFFFFFF2) returns 0x0000000B (0000ms, 24221ms total) +T3170 084:608 JLINK_Go() -- CPU_ReadMem(4 bytes @ 0xE0001000) (0006ms, 24227ms total) +T3170 084:615 JLINK_IsHalted() -- CPU_ReadMem(2 bytes @ 0x20000000) returns TRUE (0090ms, 24318ms total) +T3170 084:705 JLINK_ReadReg(R15 (PC)) returns 0x20000000 (0000ms, 24228ms total) +T3170 084:705 JLINK_ClrBPEx(BPHandle = 0x0000000B) returns 0x00 (0000ms, 24228ms total) +T3170 084:705 JLINK_ReadReg(R0) returns 0x00000000 (0000ms, 24228ms total) +T3170 084:705 JLINK_WriteReg(R0, 0x00005000) returns 0x00 (0000ms, 24228ms total) +T3170 084:705 JLINK_WriteReg(R1, 0x00001000) returns 0x00 (0000ms, 24228ms total) +T3170 084:705 JLINK_WriteReg(R2, 0x000000FF) returns 0x00 (0000ms, 24228ms total) +T3170 084:705 JLINK_WriteReg(R3, 0x00000000) returns 0x00 (0000ms, 24228ms total) +T3170 084:705 JLINK_WriteReg(R4, 0x00000000) returns 0x00 (0000ms, 24228ms total) +T3170 084:705 JLINK_WriteReg(R5, 0x00000000) returns 0x00 (0000ms, 24228ms total) +T3170 084:705 JLINK_WriteReg(R6, 0x00000000) returns 0x00 (0000ms, 24228ms total) +T3170 084:705 JLINK_WriteReg(R7, 0x00000000) returns 0x00 (0000ms, 24228ms total) +T3170 084:705 JLINK_WriteReg(R8, 0x00000000) returns 0x00 (0000ms, 24228ms total) +T3170 084:705 JLINK_WriteReg(R9, 0x2000013C) returns 0x00 (0000ms, 24228ms total) +T3170 084:705 JLINK_WriteReg(R10, 0x00000000) returns 0x00 (0000ms, 24228ms total) +T3170 084:705 JLINK_WriteReg(R11, 0x00000000) returns 0x00 (0000ms, 24228ms total) +T3170 084:705 JLINK_WriteReg(R12, 0x00000000) returns 0x00 (0000ms, 24228ms total) +T3170 084:705 JLINK_WriteReg(R13 (SP), 0x20001000) returns 0x00 (0000ms, 24228ms total) +T3170 084:705 JLINK_WriteReg(R14, 0x20000001) returns 0x00 (0000ms, 24228ms total) +T3170 084:705 JLINK_WriteReg(R15 (PC), 0x20000020) returns 0x00 (0000ms, 24228ms total) +T3170 084:705 JLINK_WriteReg(XPSR, 0x01000000) returns 0x00 (0000ms, 24228ms total) +T3170 084:705 JLINK_WriteReg(MSP, 0x20001000) returns 0x00 (0000ms, 24228ms total) +T3170 084:705 JLINK_WriteReg(PSP, 0x20001000) returns 0x00 (0000ms, 24228ms total) +T3170 084:705 JLINK_WriteReg(CFBP, 0x00000000) returns 0x00 (0000ms, 24228ms total) +T3170 084:705 JLINK_SetBPEx(Addr = 0x20000000, Type = 0xFFFFFFF2) returns 0x0000000C (0000ms, 24228ms total) +T3170 084:705 JLINK_Go() -- CPU_ReadMem(4 bytes @ 0xE0001000) (0009ms, 24237ms total) +T3170 084:714 JLINK_IsHalted() -- CPU_ReadMem(2 bytes @ 0x20000000) returns TRUE (0090ms, 24327ms total) +T3170 084:804 JLINK_ReadReg(R15 (PC)) returns 0x20000000 (0000ms, 24237ms total) +T3170 084:804 JLINK_ClrBPEx(BPHandle = 0x0000000C) returns 0x00 (0000ms, 24237ms total) +T3170 084:804 JLINK_ReadReg(R0) returns 0x00000001 (0000ms, 24237ms total) +T3170 084:804 JLINK_WriteReg(R0, 0x00005000) returns 0x00 (0000ms, 24237ms total) +T3170 084:804 JLINK_WriteReg(R1, 0x00001000) returns 0x00 (0000ms, 24237ms total) +T3170 084:804 JLINK_WriteReg(R2, 0x000000FF) returns 0x00 (0000ms, 24237ms total) +T3170 084:804 JLINK_WriteReg(R3, 0x00000000) returns 0x00 (0000ms, 24237ms total) +T3170 084:804 JLINK_WriteReg(R4, 0x00000000) returns 0x00 (0000ms, 24237ms total) +T3170 084:804 JLINK_WriteReg(R5, 0x00000000) returns 0x00 (0000ms, 24237ms total) +T3170 084:804 JLINK_WriteReg(R6, 0x00000000) returns 0x00 (0000ms, 24237ms total) +T3170 084:804 JLINK_WriteReg(R7, 0x00000000) returns 0x00 (0000ms, 24237ms total) +T3170 084:804 JLINK_WriteReg(R8, 0x00000000) returns 0x00 (0000ms, 24237ms total) +T3170 084:804 JLINK_WriteReg(R9, 0x2000013C) returns 0x00 (0001ms, 24238ms total) +T3170 084:805 JLINK_WriteReg(R10, 0x00000000) returns 0x00 (0000ms, 24238ms total) +T3170 084:805 JLINK_WriteReg(R11, 0x00000000) returns 0x00 (0000ms, 24238ms total) +T3170 084:805 JLINK_WriteReg(R12, 0x00000000) returns 0x00 (0000ms, 24238ms total) +T3170 084:805 JLINK_WriteReg(R13 (SP), 0x20001000) returns 0x00 (0000ms, 24238ms total) +T3170 084:805 JLINK_WriteReg(R14, 0x20000001) returns 0x00 (0000ms, 24238ms total) +T3170 084:805 JLINK_WriteReg(R15 (PC), 0x20000058) returns 0x00 (0000ms, 24238ms total) +T3170 084:805 JLINK_WriteReg(XPSR, 0x01000000) returns 0x00 (0000ms, 24238ms total) +T3170 084:805 JLINK_WriteReg(MSP, 0x20001000) returns 0x00 (0000ms, 24238ms total) +T3170 084:805 JLINK_WriteReg(PSP, 0x20001000) returns 0x00 (0000ms, 24238ms total) +T3170 084:805 JLINK_WriteReg(CFBP, 0x00000000) returns 0x00 (0000ms, 24238ms total) +T3170 084:805 JLINK_SetBPEx(Addr = 0x20000000, Type = 0xFFFFFFF2) returns 0x0000000D (0000ms, 24238ms total) +T3170 084:805 JLINK_Go() -- CPU_ReadMem(4 bytes @ 0xE0001000) (0008ms, 24246ms total) +T3170 084:814 JLINK_IsHalted() -- CPU_ReadMem(2 bytes @ 0x20000000) returns TRUE (0092ms, 24339ms total) +T3170 084:907 JLINK_ReadReg(R15 (PC)) returns 0x20000000 (0000ms, 24247ms total) +T3170 084:907 JLINK_ClrBPEx(BPHandle = 0x0000000D) returns 0x00 (0000ms, 24247ms total) +T3170 084:907 JLINK_ReadReg(R0) returns 0x00000000 (0000ms, 24247ms total) +T3170 084:907 JLINK_WriteReg(R0, 0x00000001) returns 0x00 (0000ms, 24247ms total) +T3170 084:907 JLINK_WriteReg(R1, 0x00001000) returns 0x00 (0000ms, 24247ms total) +T3170 084:907 JLINK_WriteReg(R2, 0x000000FF) returns 0x00 (0000ms, 24247ms total) +T3170 084:907 JLINK_WriteReg(R3, 0x00000000) returns 0x00 (0000ms, 24247ms total) +T3170 084:907 JLINK_WriteReg(R4, 0x00000000) returns 0x00 (0000ms, 24247ms total) +T3170 084:907 JLINK_WriteReg(R5, 0x00000000) returns 0x00 (0000ms, 24247ms total) +T3170 084:907 JLINK_WriteReg(R6, 0x00000000) returns 0x00 (0000ms, 24247ms total) +T3170 084:907 JLINK_WriteReg(R7, 0x00000000) returns 0x00 (0000ms, 24247ms total) +T3170 084:907 JLINK_WriteReg(R8, 0x00000000) returns 0x00 (0000ms, 24247ms total) +T3170 084:907 JLINK_WriteReg(R9, 0x2000013C) returns 0x00 (0000ms, 24247ms total) +T3170 084:907 JLINK_WriteReg(R10, 0x00000000) returns 0x00 (0000ms, 24247ms total) +T3170 084:907 JLINK_WriteReg(R11, 0x00000000) returns 0x00 (0000ms, 24247ms total) +T3170 084:907 JLINK_WriteReg(R12, 0x00000000) returns 0x00 (0000ms, 24247ms total) +T3170 084:907 JLINK_WriteReg(R13 (SP), 0x20001000) returns 0x00 (0000ms, 24247ms total) +T3170 084:907 JLINK_WriteReg(R14, 0x20000001) returns 0x00 (0000ms, 24247ms total) +T3170 084:907 JLINK_WriteReg(R15 (PC), 0x20000054) returns 0x00 (0000ms, 24247ms total) +T3170 084:907 JLINK_WriteReg(XPSR, 0x01000000) returns 0x00 (0000ms, 24247ms total) +T3170 084:907 JLINK_WriteReg(MSP, 0x20001000) returns 0x00 (0000ms, 24247ms total) +T3170 084:907 JLINK_WriteReg(PSP, 0x20001000) returns 0x00 (0000ms, 24247ms total) +T3170 084:907 JLINK_WriteReg(CFBP, 0x00000000) returns 0x00 (0000ms, 24247ms total) +T3170 084:907 JLINK_SetBPEx(Addr = 0x20000000, Type = 0xFFFFFFF2) returns 0x0000000E (0000ms, 24247ms total) +T3170 084:907 JLINK_Go() -- CPU_ReadMem(4 bytes @ 0xE0001000) (0007ms, 24254ms total) +T3170 084:914 JLINK_IsHalted() -- CPU_ReadMem(2 bytes @ 0x20000000) returns TRUE (0090ms, 24344ms total) +T3170 085:004 JLINK_ReadReg(R15 (PC)) returns 0x20000000 (0000ms, 24254ms total) +T3170 085:004 JLINK_ClrBPEx(BPHandle = 0x0000000E) returns 0x00 (0000ms, 24254ms total) +T3170 085:004 JLINK_ReadReg(R0) returns 0x00000000 (0000ms, 24254ms total) +T3170 085:061 JLINK_WriteMem(0x20000000, 0x0144 Bytes, ...) - Data: 00 BE 0A E0 0D 78 2D 06 68 40 08 24 40 00 00 D3 ... -- CPU_WriteMem(324 bytes @ 0x20000000) returns 0x144 (0042ms, 24296ms total) +T3170 085:103 JLINK_WriteReg(R0, 0x00000000) returns 0x00 (0000ms, 24296ms total) +T3170 085:103 JLINK_WriteReg(R1, 0x05F5E100) returns 0x00 (0000ms, 24296ms total) +T3170 085:103 JLINK_WriteReg(R2, 0x00000002) returns 0x00 (0000ms, 24296ms total) +T3170 085:103 JLINK_WriteReg(R3, 0x00000000) returns 0x00 (0000ms, 24296ms total) +T3170 085:103 JLINK_WriteReg(R4, 0x00000000) returns 0x00 (0000ms, 24296ms total) +T3170 085:103 JLINK_WriteReg(R5, 0x00000000) returns 0x00 (0000ms, 24296ms total) +T3170 085:103 JLINK_WriteReg(R6, 0x00000000) returns 0x00 (0000ms, 24296ms total) +T3170 085:103 JLINK_WriteReg(R7, 0x00000000) returns 0x00 (0000ms, 24296ms total) +T3170 085:103 JLINK_WriteReg(R8, 0x00000000) returns 0x00 (0000ms, 24296ms total) +T3170 085:103 JLINK_WriteReg(R9, 0x2000013C) returns 0x00 (0000ms, 24296ms total) +T3170 085:103 JLINK_WriteReg(R10, 0x00000000) returns 0x00 (0000ms, 24296ms total) +T3170 085:103 JLINK_WriteReg(R11, 0x00000000) returns 0x00 (0000ms, 24296ms total) +T3170 085:103 JLINK_WriteReg(R12, 0x00000000) returns 0x00 (0000ms, 24296ms total) +T3170 085:103 JLINK_WriteReg(R13 (SP), 0x20001000) returns 0x00 (0000ms, 24296ms total) +T3170 085:103 JLINK_WriteReg(R14, 0x20000001) returns 0x00 (0000ms, 24296ms total) +T3170 085:103 JLINK_WriteReg(R15 (PC), 0x20000040) returns 0x00 (0000ms, 24296ms total) +T3170 085:103 JLINK_WriteReg(XPSR, 0x01000000) returns 0x00 (0000ms, 24296ms total) +T3170 085:103 JLINK_WriteReg(MSP, 0x20001000) returns 0x00 (0000ms, 24296ms total) +T3170 085:103 JLINK_WriteReg(PSP, 0x20001000) returns 0x00 (0000ms, 24296ms total) +T3170 085:103 JLINK_WriteReg(CFBP, 0x00000000) returns 0x00 (0000ms, 24296ms total) +T3170 085:103 JLINK_SetBPEx(Addr = 0x20000000, Type = 0xFFFFFFF2) -- CPU_ReadMem(2 bytes @ 0x20000000) returns 0x0000000F (0002ms, 24298ms total) +T3170 085:105 JLINK_Go() -- CPU_WriteMem(2 bytes @ 0x20000000) -- CPU_ReadMem(4 bytes @ 0xE0001000) (0008ms, 24306ms total) +T3170 085:113 JLINK_IsHalted() -- CPU_ReadMem(2 bytes @ 0x20000000) returns TRUE (0090ms, 24396ms total) +T3170 085:204 JLINK_ReadReg(R15 (PC)) returns 0x20000000 (0000ms, 24306ms total) +T3170 085:204 JLINK_ClrBPEx(BPHandle = 0x0000000F) returns 0x00 (0000ms, 24306ms total) +T3170 085:204 JLINK_ReadReg(R0) returns 0x00000000 (0000ms, 24306ms total) +T3170 085:204 JLINK_WriteMem(0x20000144, 0x0080 Bytes, ...) - Data: C0 26 00 20 25 02 00 00 1F 03 00 00 0D 04 00 00 ... -- CPU_WriteMem(128 bytes @ 0x20000144) returns 0x80 (0004ms, 24310ms total) +T3170 085:208 JLINK_WriteReg(R0, 0x00000000) returns 0x00 (0000ms, 24310ms total) +T3170 085:208 JLINK_WriteReg(R1, 0x00000080) returns 0x00 (0000ms, 24310ms total) +T3170 085:208 JLINK_WriteReg(R2, 0x20000144) returns 0x00 (0000ms, 24310ms total) +T3170 085:208 JLINK_WriteReg(R3, 0x00000000) returns 0x00 (0000ms, 24310ms total) +T3170 085:208 JLINK_WriteReg(R4, 0x00000000) returns 0x00 (0000ms, 24310ms total) +T3170 085:208 JLINK_WriteReg(R5, 0x00000000) returns 0x00 (0000ms, 24310ms total) +T3170 085:208 JLINK_WriteReg(R6, 0x00000000) returns 0x00 (0000ms, 24310ms total) +T3170 085:208 JLINK_WriteReg(R7, 0x00000000) returns 0x00 (0000ms, 24310ms total) +T3170 085:208 JLINK_WriteReg(R8, 0x00000000) returns 0x00 (0000ms, 24310ms total) +T3170 085:208 JLINK_WriteReg(R9, 0x2000013C) returns 0x00 (0000ms, 24310ms total) +T3170 085:208 JLINK_WriteReg(R10, 0x00000000) returns 0x00 (0000ms, 24310ms total) +T3170 085:208 JLINK_WriteReg(R11, 0x00000000) returns 0x00 (0000ms, 24310ms total) +T3170 085:208 JLINK_WriteReg(R12, 0x00000000) returns 0x00 (0000ms, 24310ms total) +T3170 085:208 JLINK_WriteReg(R13 (SP), 0x20001000) returns 0x00 (0000ms, 24310ms total) +T3170 085:208 JLINK_WriteReg(R14, 0x20000001) returns 0x00 (0000ms, 24310ms total) +T3170 085:208 JLINK_WriteReg(R15 (PC), 0x2000005C) returns 0x00 (0000ms, 24310ms total) +T3170 085:208 JLINK_WriteReg(XPSR, 0x01000000) returns 0x00 (0000ms, 24310ms total) +T3170 085:208 JLINK_WriteReg(MSP, 0x20001000) returns 0x00 (0000ms, 24310ms total) +T3170 085:208 JLINK_WriteReg(PSP, 0x20001000) returns 0x00 (0000ms, 24310ms total) +T3170 085:208 JLINK_WriteReg(CFBP, 0x00000000) returns 0x00 (0000ms, 24310ms total) +T3170 085:208 JLINK_SetBPEx(Addr = 0x20000000, Type = 0xFFFFFFF2) returns 0x00000010 (0000ms, 24310ms total) +T3170 085:208 JLINK_Go() -- CPU_ReadMem(4 bytes @ 0xE0001000) (0018ms, 24328ms total) +T3170 085:226 JLINK_IsHalted() -- CPU_ReadMem(2 bytes @ 0x20000000) returns TRUE (0079ms, 24407ms total) +T3170 085:305 JLINK_ReadReg(R15 (PC)) returns 0x20000000 (0000ms, 24328ms total) +T3170 085:307 JLINK_ClrBPEx(BPHandle = 0x00000010) returns 0x00 (0000ms, 24328ms total) +T3170 085:307 JLINK_ReadReg(R0) returns 0x00000000 (0000ms, 24328ms total) +T3170 085:311 JLINK_WriteMem(0x20000144, 0x0080 Bytes, ...) - Data: 31 03 00 00 31 03 00 00 31 03 00 00 31 03 00 00 ... -- CPU_WriteMem(128 bytes @ 0x20000144) returns 0x80 (0003ms, 24331ms total) +T3170 085:314 JLINK_WriteReg(R0, 0x00000080) returns 0x00 (0000ms, 24331ms total) +T3170 085:314 JLINK_WriteReg(R1, 0x00000080) returns 0x00 (0000ms, 24331ms total) +T3170 085:314 JLINK_WriteReg(R2, 0x20000144) returns 0x00 (0000ms, 24331ms total) +T3170 085:314 JLINK_WriteReg(R3, 0x00000000) returns 0x00 (0000ms, 24331ms total) +T3170 085:314 JLINK_WriteReg(R4, 0x00000000) returns 0x00 (0000ms, 24331ms total) +T3170 085:314 JLINK_WriteReg(R5, 0x00000000) returns 0x00 (0000ms, 24331ms total) +T3170 085:314 JLINK_WriteReg(R6, 0x00000000) returns 0x00 (0000ms, 24331ms total) +T3170 085:314 JLINK_WriteReg(R7, 0x00000000) returns 0x00 (0000ms, 24331ms total) +T3170 085:314 JLINK_WriteReg(R8, 0x00000000) returns 0x00 (0000ms, 24331ms total) +T3170 085:314 JLINK_WriteReg(R9, 0x2000013C) returns 0x00 (0000ms, 24331ms total) +T3170 085:314 JLINK_WriteReg(R10, 0x00000000) returns 0x00 (0000ms, 24331ms total) +T3170 085:314 JLINK_WriteReg(R11, 0x00000000) returns 0x00 (0000ms, 24331ms total) +T3170 085:314 JLINK_WriteReg(R12, 0x00000000) returns 0x00 (0000ms, 24331ms total) +T3170 085:314 JLINK_WriteReg(R13 (SP), 0x20001000) returns 0x00 (0000ms, 24331ms total) +T3170 085:314 JLINK_WriteReg(R14, 0x20000001) returns 0x00 (0000ms, 24331ms total) +T3170 085:314 JLINK_WriteReg(R15 (PC), 0x2000005C) returns 0x00 (0000ms, 24331ms total) +T3170 085:315 JLINK_WriteReg(XPSR, 0x01000000) returns 0x00 (0000ms, 24332ms total) +T3170 085:315 JLINK_WriteReg(MSP, 0x20001000) returns 0x00 (0000ms, 24332ms total) +T3170 085:315 JLINK_WriteReg(PSP, 0x20001000) returns 0x00 (0000ms, 24332ms total) +T3170 085:315 JLINK_WriteReg(CFBP, 0x00000000) returns 0x00 (0000ms, 24332ms total) +T3170 085:315 JLINK_SetBPEx(Addr = 0x20000000, Type = 0xFFFFFFF2) returns 0x00000011 (0000ms, 24332ms total) +T3170 085:315 JLINK_Go() -- CPU_ReadMem(4 bytes @ 0xE0001000) (0089ms, 24421ms total) +T3170 085:404 JLINK_IsHalted() -- CPU_ReadMem(2 bytes @ 0x20000000) returns TRUE (0010ms, 24431ms total) +T3170 085:414 JLINK_ReadReg(R15 (PC)) returns 0x20000000 (0000ms, 24421ms total) +T3170 085:414 JLINK_ClrBPEx(BPHandle = 0x00000011) returns 0x00 (0000ms, 24421ms total) +T3170 085:414 JLINK_ReadReg(R0) returns 0x00000000 (0000ms, 24421ms total) +T3170 085:414 JLINK_WriteMem(0x20000144, 0x0080 Bytes, ...) - Data: 31 03 00 00 31 03 00 00 31 03 00 00 31 03 00 00 ... -- CPU_WriteMem(128 bytes @ 0x20000144) returns 0x80 (0086ms, 24507ms total) +T3170 085:500 JLINK_WriteReg(R0, 0x00000100) returns 0x00 (0000ms, 24507ms total) +T3170 085:500 JLINK_WriteReg(R1, 0x00000080) returns 0x00 (0000ms, 24507ms total) +T3170 085:500 JLINK_WriteReg(R2, 0x20000144) returns 0x00 (0000ms, 24507ms total) +T3170 085:500 JLINK_WriteReg(R3, 0x00000000) returns 0x00 (0000ms, 24507ms total) +T3170 085:500 JLINK_WriteReg(R4, 0x00000000) returns 0x00 (0001ms, 24508ms total) +T3170 085:501 JLINK_WriteReg(R5, 0x00000000) returns 0x00 (0000ms, 24508ms total) +T3170 085:501 JLINK_WriteReg(R6, 0x00000000) returns 0x00 (0000ms, 24508ms total) +T3170 085:501 JLINK_WriteReg(R7, 0x00000000) returns 0x00 (0000ms, 24508ms total) +T3170 085:501 JLINK_WriteReg(R8, 0x00000000) returns 0x00 (0000ms, 24508ms total) +T3170 085:501 JLINK_WriteReg(R9, 0x2000013C) returns 0x00 (0000ms, 24508ms total) +T3170 085:501 JLINK_WriteReg(R10, 0x00000000) returns 0x00 (0000ms, 24508ms total) +T3170 085:501 JLINK_WriteReg(R11, 0x00000000) returns 0x00 (0000ms, 24508ms total) +T3170 085:501 JLINK_WriteReg(R12, 0x00000000) returns 0x00 (0000ms, 24508ms total) +T3170 085:501 JLINK_WriteReg(R13 (SP), 0x20001000) returns 0x00 (0000ms, 24508ms total) +T3170 085:501 JLINK_WriteReg(R14, 0x20000001) returns 0x00 (0000ms, 24508ms total) +T3170 085:501 JLINK_WriteReg(R15 (PC), 0x2000005C) returns 0x00 (0000ms, 24508ms total) +T3170 085:501 JLINK_WriteReg(XPSR, 0x01000000) returns 0x00 (0000ms, 24508ms total) +T3170 085:501 JLINK_WriteReg(MSP, 0x20001000) returns 0x00 (0000ms, 24508ms total) +T3170 085:501 JLINK_WriteReg(PSP, 0x20001000) returns 0x00 (0000ms, 24508ms total) +T3170 085:501 JLINK_WriteReg(CFBP, 0x00000000) returns 0x00 (0000ms, 24508ms total) +T3170 085:501 JLINK_SetBPEx(Addr = 0x20000000, Type = 0xFFFFFFF2) returns 0x00000012 (0000ms, 24508ms total) +T3170 085:501 JLINK_Go() -- CPU_ReadMem(4 bytes @ 0xE0001000) (0008ms, 24516ms total) +T3170 085:509 JLINK_IsHalted() -- CPU_ReadMem(2 bytes @ 0x20000000) returns TRUE (0090ms, 24606ms total) +T3170 085:599 JLINK_ReadReg(R15 (PC)) returns 0x20000000 (0000ms, 24516ms total) +T3170 085:599 JLINK_ClrBPEx(BPHandle = 0x00000012) returns 0x00 (0000ms, 24516ms total) +T3170 085:599 JLINK_ReadReg(R0) returns 0x00000000 (0000ms, 24516ms total) +T3170 085:600 JLINK_WriteMem(0x20000144, 0x0080 Bytes, ...) - Data: 31 03 00 00 31 03 00 00 00 F0 02 F8 00 F0 3A F8 ... -- CPU_WriteMem(128 bytes @ 0x20000144) returns 0x80 (0003ms, 24519ms total) +T3170 085:603 JLINK_WriteReg(R0, 0x00000180) returns 0x00 (0000ms, 24519ms total) +T3170 085:603 JLINK_WriteReg(R1, 0x00000080) returns 0x00 (0000ms, 24519ms total) +T3170 085:603 JLINK_WriteReg(R2, 0x20000144) returns 0x00 (0000ms, 24519ms total) +T3170 085:603 JLINK_WriteReg(R3, 0x00000000) returns 0x00 (0000ms, 24519ms total) +T3170 085:603 JLINK_WriteReg(R4, 0x00000000) returns 0x00 (0000ms, 24519ms total) +T3170 085:603 JLINK_WriteReg(R5, 0x00000000) returns 0x00 (0000ms, 24519ms total) +T3170 085:603 JLINK_WriteReg(R6, 0x00000000) returns 0x00 (0000ms, 24519ms total) +T3170 085:603 JLINK_WriteReg(R7, 0x00000000) returns 0x00 (0000ms, 24519ms total) +T3170 085:603 JLINK_WriteReg(R8, 0x00000000) returns 0x00 (0000ms, 24519ms total) +T3170 085:603 JLINK_WriteReg(R9, 0x2000013C) returns 0x00 (0000ms, 24519ms total) +T3170 085:603 JLINK_WriteReg(R10, 0x00000000) returns 0x00 (0000ms, 24519ms total) +T3170 085:603 JLINK_WriteReg(R11, 0x00000000) returns 0x00 (0000ms, 24519ms total) +T3170 085:603 JLINK_WriteReg(R12, 0x00000000) returns 0x00 (0000ms, 24519ms total) +T3170 085:603 JLINK_WriteReg(R13 (SP), 0x20001000) returns 0x00 (0000ms, 24519ms total) +T3170 085:603 JLINK_WriteReg(R14, 0x20000001) returns 0x00 (0000ms, 24519ms total) +T3170 085:603 JLINK_WriteReg(R15 (PC), 0x2000005C) returns 0x00 (0000ms, 24519ms total) +T3170 085:603 JLINK_WriteReg(XPSR, 0x01000000) returns 0x00 (0000ms, 24519ms total) +T3170 085:603 JLINK_WriteReg(MSP, 0x20001000) returns 0x00 (0000ms, 24519ms total) +T3170 085:603 JLINK_WriteReg(PSP, 0x20001000) returns 0x00 (0000ms, 24519ms total) +T3170 085:603 JLINK_WriteReg(CFBP, 0x00000000) returns 0x00 (0000ms, 24519ms total) +T3170 085:603 JLINK_SetBPEx(Addr = 0x20000000, Type = 0xFFFFFFF2) returns 0x00000013 (0000ms, 24519ms total) +T3170 085:603 JLINK_Go() -- CPU_ReadMem(4 bytes @ 0xE0001000) (0006ms, 24525ms total) +T3170 085:610 JLINK_IsHalted() -- CPU_ReadMem(2 bytes @ 0x20000000) returns TRUE (0023ms, 24549ms total) +T3170 085:633 JLINK_ReadReg(R15 (PC)) returns 0x20000000 (0000ms, 24526ms total) +T3170 085:633 JLINK_ClrBPEx(BPHandle = 0x00000013) returns 0x00 (0000ms, 24526ms total) +T3170 085:633 JLINK_ReadReg(R0) returns 0x00000000 (0000ms, 24526ms total) +T3170 085:634 JLINK_WriteMem(0x20000144, 0x0080 Bytes, ...) - Data: 10 B5 10 BD 00 F0 DC FA 11 46 FF F7 F7 FF 00 F0 ... -- CPU_WriteMem(128 bytes @ 0x20000144) returns 0x80 (0066ms, 24592ms total) +T3170 085:701 JLINK_WriteReg(R0, 0x00000200) returns 0x00 (0000ms, 24592ms total) +T3170 085:701 JLINK_WriteReg(R1, 0x00000080) returns 0x00 (0000ms, 24592ms total) +T3170 085:701 JLINK_WriteReg(R2, 0x20000144) returns 0x00 (0000ms, 24592ms total) +T3170 085:701 JLINK_WriteReg(R3, 0x00000000) returns 0x00 (0000ms, 24592ms total) +T3170 085:701 JLINK_WriteReg(R4, 0x00000000) returns 0x00 (0000ms, 24592ms total) +T3170 085:701 JLINK_WriteReg(R5, 0x00000000) returns 0x00 (0000ms, 24592ms total) +T3170 085:701 JLINK_WriteReg(R6, 0x00000000) returns 0x00 (0000ms, 24592ms total) +T3170 085:701 JLINK_WriteReg(R7, 0x00000000) returns 0x00 (0000ms, 24592ms total) +T3170 085:701 JLINK_WriteReg(R8, 0x00000000) returns 0x00 (0000ms, 24592ms total) +T3170 085:701 JLINK_WriteReg(R9, 0x2000013C) returns 0x00 (0000ms, 24592ms total) +T3170 085:701 JLINK_WriteReg(R10, 0x00000000) returns 0x00 (0000ms, 24592ms total) +T3170 085:701 JLINK_WriteReg(R11, 0x00000000) returns 0x00 (0000ms, 24592ms total) +T3170 085:701 JLINK_WriteReg(R12, 0x00000000) returns 0x00 (0000ms, 24592ms total) +T3170 085:701 JLINK_WriteReg(R13 (SP), 0x20001000) returns 0x00 (0000ms, 24592ms total) +T3170 085:701 JLINK_WriteReg(R14, 0x20000001) returns 0x00 (0000ms, 24592ms total) +T3170 085:701 JLINK_WriteReg(R15 (PC), 0x2000005C) returns 0x00 (0000ms, 24592ms total) +T3170 085:701 JLINK_WriteReg(XPSR, 0x01000000) returns 0x00 (0000ms, 24592ms total) +T3170 085:701 JLINK_WriteReg(MSP, 0x20001000) returns 0x00 (0000ms, 24592ms total) +T3170 085:701 JLINK_WriteReg(PSP, 0x20001000) returns 0x00 (0000ms, 24592ms total) +T3170 085:701 JLINK_WriteReg(CFBP, 0x00000000) returns 0x00 (0000ms, 24592ms total) +T3170 085:701 JLINK_SetBPEx(Addr = 0x20000000, Type = 0xFFFFFFF2) returns 0x00000014 (0000ms, 24592ms total) +T3170 085:701 JLINK_Go() -- CPU_ReadMem(4 bytes @ 0xE0001000) (0008ms, 24600ms total) +T3170 085:709 JLINK_IsHalted() -- CPU_ReadMem(2 bytes @ 0x20000000) returns TRUE (0090ms, 24690ms total) +T3170 085:799 JLINK_ReadReg(R15 (PC)) returns 0x20000000 (0000ms, 24600ms total) +T3170 085:799 JLINK_ClrBPEx(BPHandle = 0x00000014) returns 0x00 (0000ms, 24600ms total) +T3170 085:799 JLINK_ReadReg(R0) returns 0x00000000 (0000ms, 24600ms total) +T3170 085:800 JLINK_WriteMem(0x20000144, 0x0080 Bytes, ...) - Data: 04 D0 32 48 32 49 07 4A 00 F0 0E F8 31 48 00 47 ... -- CPU_WriteMem(128 bytes @ 0x20000144) returns 0x80 (0003ms, 24603ms total) +T3170 085:803 JLINK_WriteReg(R0, 0x00000280) returns 0x00 (0000ms, 24603ms total) +T3170 085:803 JLINK_WriteReg(R1, 0x00000080) returns 0x00 (0000ms, 24603ms total) +T3170 085:803 JLINK_WriteReg(R2, 0x20000144) returns 0x00 (0000ms, 24603ms total) +T3170 085:803 JLINK_WriteReg(R3, 0x00000000) returns 0x00 (0000ms, 24603ms total) +T3170 085:803 JLINK_WriteReg(R4, 0x00000000) returns 0x00 (0000ms, 24603ms total) +T3170 085:803 JLINK_WriteReg(R5, 0x00000000) returns 0x00 (0000ms, 24603ms total) +T3170 085:803 JLINK_WriteReg(R6, 0x00000000) returns 0x00 (0000ms, 24603ms total) +T3170 085:803 JLINK_WriteReg(R7, 0x00000000) returns 0x00 (0000ms, 24603ms total) +T3170 085:803 JLINK_WriteReg(R8, 0x00000000) returns 0x00 (0000ms, 24603ms total) +T3170 085:803 JLINK_WriteReg(R9, 0x2000013C) returns 0x00 (0000ms, 24603ms total) +T3170 085:803 JLINK_WriteReg(R10, 0x00000000) returns 0x00 (0000ms, 24603ms total) +T3170 085:803 JLINK_WriteReg(R11, 0x00000000) returns 0x00 (0000ms, 24603ms total) +T3170 085:803 JLINK_WriteReg(R12, 0x00000000) returns 0x00 (0000ms, 24603ms total) +T3170 085:803 JLINK_WriteReg(R13 (SP), 0x20001000) returns 0x00 (0000ms, 24603ms total) +T3170 085:803 JLINK_WriteReg(R14, 0x20000001) returns 0x00 (0000ms, 24603ms total) +T3170 085:803 JLINK_WriteReg(R15 (PC), 0x2000005C) returns 0x00 (0000ms, 24603ms total) +T3170 085:803 JLINK_WriteReg(XPSR, 0x01000000) returns 0x00 (0000ms, 24603ms total) +T3170 085:803 JLINK_WriteReg(MSP, 0x20001000) returns 0x00 (0000ms, 24603ms total) +T3170 085:803 JLINK_WriteReg(PSP, 0x20001000) returns 0x00 (0000ms, 24603ms total) +T3170 085:803 JLINK_WriteReg(CFBP, 0x00000000) returns 0x00 (0000ms, 24603ms total) +T3170 085:803 JLINK_SetBPEx(Addr = 0x20000000, Type = 0xFFFFFFF2) returns 0x00000015 (0000ms, 24603ms total) +T3170 085:803 JLINK_Go() -- CPU_ReadMem(4 bytes @ 0xE0001000) (0007ms, 24610ms total) +T3170 085:810 JLINK_IsHalted() -- CPU_ReadMem(2 bytes @ 0x20000000) returns TRUE (0055ms, 24665ms total) +T3170 085:865 JLINK_ReadReg(R15 (PC)) returns 0x20000000 (0000ms, 24610ms total) +T3170 085:865 JLINK_ClrBPEx(BPHandle = 0x00000015) returns 0x00 (0000ms, 24610ms total) +T3170 085:865 JLINK_ReadReg(R0) returns 0x00000000 (0000ms, 24610ms total) +T3170 085:866 JLINK_WriteMem(0x20000144, 0x0080 Bytes, ...) - Data: F8 D1 08 F0 0F 08 B8 F1 00 0F 07 D0 02 70 4F EA ... -- CPU_WriteMem(128 bytes @ 0x20000144) returns 0x80 (0035ms, 24645ms total) +T3170 085:901 JLINK_WriteReg(R0, 0x00000300) returns 0x00 (0000ms, 24645ms total) +T3170 085:901 JLINK_WriteReg(R1, 0x00000080) returns 0x00 (0000ms, 24645ms total) +T3170 085:901 JLINK_WriteReg(R2, 0x20000144) returns 0x00 (0000ms, 24645ms total) +T3170 085:901 JLINK_WriteReg(R3, 0x00000000) returns 0x00 (0000ms, 24645ms total) +T3170 085:901 JLINK_WriteReg(R4, 0x00000000) returns 0x00 (0000ms, 24645ms total) +T3170 085:901 JLINK_WriteReg(R5, 0x00000000) returns 0x00 (0000ms, 24645ms total) +T3170 085:901 JLINK_WriteReg(R6, 0x00000000) returns 0x00 (0000ms, 24645ms total) +T3170 085:901 JLINK_WriteReg(R7, 0x00000000) returns 0x00 (0000ms, 24645ms total) +T3170 085:901 JLINK_WriteReg(R8, 0x00000000) returns 0x00 (0000ms, 24645ms total) +T3170 085:901 JLINK_WriteReg(R9, 0x2000013C) returns 0x00 (0000ms, 24645ms total) +T3170 085:901 JLINK_WriteReg(R10, 0x00000000) returns 0x00 (0000ms, 24645ms total) +T3170 085:901 JLINK_WriteReg(R11, 0x00000000) returns 0x00 (0000ms, 24645ms total) +T3170 085:901 JLINK_WriteReg(R12, 0x00000000) returns 0x00 (0000ms, 24645ms total) +T3170 085:901 JLINK_WriteReg(R13 (SP), 0x20001000) returns 0x00 (0000ms, 24645ms total) +T3170 085:901 JLINK_WriteReg(R14, 0x20000001) returns 0x00 (0000ms, 24645ms total) +T3170 085:901 JLINK_WriteReg(R15 (PC), 0x2000005C) returns 0x00 (0000ms, 24645ms total) +T3170 085:901 JLINK_WriteReg(XPSR, 0x01000000) returns 0x00 (0000ms, 24645ms total) +T3170 085:901 JLINK_WriteReg(MSP, 0x20001000) returns 0x00 (0000ms, 24645ms total) +T3170 085:901 JLINK_WriteReg(PSP, 0x20001000) returns 0x00 (0000ms, 24645ms total) +T3170 085:901 JLINK_WriteReg(CFBP, 0x00000000) returns 0x00 (0000ms, 24645ms total) +T3170 085:901 JLINK_SetBPEx(Addr = 0x20000000, Type = 0xFFFFFFF2) returns 0x00000016 (0000ms, 24645ms total) +T3170 085:901 JLINK_Go() -- CPU_ReadMem(4 bytes @ 0xE0001000) (0007ms, 24652ms total) +T3170 085:908 JLINK_IsHalted() -- CPU_ReadMem(2 bytes @ 0x20000000) returns TRUE (0005ms, 24657ms total) +T3170 085:913 JLINK_ReadReg(R15 (PC)) returns 0x20000000 (0000ms, 24652ms total) +T3170 085:913 JLINK_ClrBPEx(BPHandle = 0x00000016) returns 0x00 (0000ms, 24652ms total) +T3170 085:913 JLINK_ReadReg(R0) returns 0x00000000 (0000ms, 24652ms total) +T3170 085:914 JLINK_WriteMem(0x20000144, 0x0080 Bytes, ...) - Data: 01 03 13 60 2F 4A 10 60 2F 4A 11 60 2F 48 4F F0 ... -- CPU_WriteMem(128 bytes @ 0x20000144) returns 0x80 (0003ms, 24655ms total) +T3170 085:917 JLINK_WriteReg(R0, 0x00000380) returns 0x00 (0000ms, 24655ms total) +T3170 085:917 JLINK_WriteReg(R1, 0x00000080) returns 0x00 (0000ms, 24655ms total) +T3170 085:917 JLINK_WriteReg(R2, 0x20000144) returns 0x00 (0000ms, 24655ms total) +T3170 085:917 JLINK_WriteReg(R3, 0x00000000) returns 0x00 (0000ms, 24655ms total) +T3170 085:917 JLINK_WriteReg(R4, 0x00000000) returns 0x00 (0000ms, 24655ms total) +T3170 085:917 JLINK_WriteReg(R5, 0x00000000) returns 0x00 (0000ms, 24655ms total) +T3170 085:917 JLINK_WriteReg(R6, 0x00000000) returns 0x00 (0000ms, 24655ms total) +T3170 085:917 JLINK_WriteReg(R7, 0x00000000) returns 0x00 (0000ms, 24655ms total) +T3170 085:917 JLINK_WriteReg(R8, 0x00000000) returns 0x00 (0000ms, 24655ms total) +T3170 085:917 JLINK_WriteReg(R9, 0x2000013C) returns 0x00 (0000ms, 24655ms total) +T3170 085:917 JLINK_WriteReg(R10, 0x00000000) returns 0x00 (0000ms, 24655ms total) +T3170 085:917 JLINK_WriteReg(R11, 0x00000000) returns 0x00 (0000ms, 24655ms total) +T3170 085:917 JLINK_WriteReg(R12, 0x00000000) returns 0x00 (0000ms, 24655ms total) +T3170 085:917 JLINK_WriteReg(R13 (SP), 0x20001000) returns 0x00 (0000ms, 24655ms total) +T3170 085:917 JLINK_WriteReg(R14, 0x20000001) returns 0x00 (0000ms, 24655ms total) +T3170 085:917 JLINK_WriteReg(R15 (PC), 0x2000005C) returns 0x00 (0000ms, 24655ms total) +T3170 085:917 JLINK_WriteReg(XPSR, 0x01000000) returns 0x00 (0000ms, 24655ms total) +T3170 085:917 JLINK_WriteReg(MSP, 0x20001000) returns 0x00 (0000ms, 24655ms total) +T3170 085:917 JLINK_WriteReg(PSP, 0x20001000) returns 0x00 (0000ms, 24655ms total) +T3170 085:917 JLINK_WriteReg(CFBP, 0x00000000) returns 0x00 (0000ms, 24655ms total) +T3170 085:917 JLINK_SetBPEx(Addr = 0x20000000, Type = 0xFFFFFFF2) returns 0x00000017 (0000ms, 24655ms total) +T3170 085:917 JLINK_Go() -- CPU_ReadMem(4 bytes @ 0xE0001000) (0086ms, 24741ms total) +T3170 086:003 JLINK_IsHalted() -- CPU_ReadMem(2 bytes @ 0x20000000) returns TRUE (0010ms, 24751ms total) +T3170 086:013 JLINK_ReadReg(R15 (PC)) returns 0x20000000 (0000ms, 24741ms total) +T3170 086:013 JLINK_ClrBPEx(BPHandle = 0x00000017) returns 0x00 (0000ms, 24741ms total) +T3170 086:013 JLINK_ReadReg(R0) returns 0x00000000 (0000ms, 24741ms total) +T3170 086:014 JLINK_WriteMem(0x20000144, 0x0080 Bytes, ...) - Data: 00 68 80 F3 08 88 61 B6 62 B6 70 47 1E F0 04 0F ... -- CPU_WriteMem(128 bytes @ 0x20000144) returns 0x80 (0086ms, 24827ms total) +T3170 086:100 JLINK_WriteReg(R0, 0x00000400) returns 0x00 (0000ms, 24827ms total) +T3170 086:100 JLINK_WriteReg(R1, 0x00000080) returns 0x00 (0000ms, 24827ms total) +T3170 086:100 JLINK_WriteReg(R2, 0x20000144) returns 0x00 (0000ms, 24827ms total) +T3170 086:100 JLINK_WriteReg(R3, 0x00000000) returns 0x00 (0000ms, 24827ms total) +T3170 086:100 JLINK_WriteReg(R4, 0x00000000) returns 0x00 (0000ms, 24827ms total) +T3170 086:100 JLINK_WriteReg(R5, 0x00000000) returns 0x00 (0000ms, 24827ms total) +T3170 086:100 JLINK_WriteReg(R6, 0x00000000) returns 0x00 (0000ms, 24827ms total) +T3170 086:100 JLINK_WriteReg(R7, 0x00000000) returns 0x00 (0000ms, 24827ms total) +T3170 086:100 JLINK_WriteReg(R8, 0x00000000) returns 0x00 (0000ms, 24827ms total) +T3170 086:100 JLINK_WriteReg(R9, 0x2000013C) returns 0x00 (0000ms, 24827ms total) +T3170 086:100 JLINK_WriteReg(R10, 0x00000000) returns 0x00 (0000ms, 24827ms total) +T3170 086:100 JLINK_WriteReg(R11, 0x00000000) returns 0x00 (0000ms, 24827ms total) +T3170 086:100 JLINK_WriteReg(R12, 0x00000000) returns 0x00 (0001ms, 24828ms total) +T3170 086:101 JLINK_WriteReg(R13 (SP), 0x20001000) returns 0x00 (0000ms, 24828ms total) +T3170 086:101 JLINK_WriteReg(R14, 0x20000001) returns 0x00 (0000ms, 24828ms total) +T3170 086:101 JLINK_WriteReg(R15 (PC), 0x2000005C) returns 0x00 (0000ms, 24828ms total) +T3170 086:101 JLINK_WriteReg(XPSR, 0x01000000) returns 0x00 (0000ms, 24828ms total) +T3170 086:101 JLINK_WriteReg(MSP, 0x20001000) returns 0x00 (0000ms, 24828ms total) +T3170 086:101 JLINK_WriteReg(PSP, 0x20001000) returns 0x00 (0000ms, 24828ms total) +T3170 086:101 JLINK_WriteReg(CFBP, 0x00000000) returns 0x00 (0000ms, 24828ms total) +T3170 086:101 JLINK_SetBPEx(Addr = 0x20000000, Type = 0xFFFFFFF2) returns 0x00000018 (0000ms, 24828ms total) +T3170 086:101 JLINK_Go() -- CPU_ReadMem(4 bytes @ 0xE0001000) (0007ms, 24835ms total) +T3170 086:108 JLINK_IsHalted() -- CPU_ReadMem(2 bytes @ 0x20000000) returns TRUE (0009ms, 24844ms total) +T3170 086:117 JLINK_ReadReg(R15 (PC)) returns 0x20000000 (0000ms, 24835ms total) +T3170 086:117 JLINK_ClrBPEx(BPHandle = 0x00000018) returns 0x00 (0000ms, 24835ms total) +T3170 086:117 JLINK_ReadReg(R0) returns 0x00000000 (0000ms, 24835ms total) +T3170 086:117 JLINK_WriteMem(0x20000144, 0x0080 Bytes, ...) - Data: 7B F9 00 21 8D F8 0B 10 0A 21 0D F1 0A 00 8D F8 ... -- CPU_WriteMem(128 bytes @ 0x20000144) returns 0x80 (0083ms, 24918ms total) +T3170 086:201 JLINK_WriteReg(R0, 0x00000480) returns 0x00 (0000ms, 24918ms total) +T3170 086:201 JLINK_WriteReg(R1, 0x00000080) returns 0x00 (0000ms, 24918ms total) +T3170 086:201 JLINK_WriteReg(R2, 0x20000144) returns 0x00 (0000ms, 24918ms total) +T3170 086:201 JLINK_WriteReg(R3, 0x00000000) returns 0x00 (0000ms, 24918ms total) +T3170 086:201 JLINK_WriteReg(R4, 0x00000000) returns 0x00 (0000ms, 24918ms total) +T3170 086:201 JLINK_WriteReg(R5, 0x00000000) returns 0x00 (0000ms, 24918ms total) +T3170 086:201 JLINK_WriteReg(R6, 0x00000000) returns 0x00 (0000ms, 24918ms total) +T3170 086:201 JLINK_WriteReg(R7, 0x00000000) returns 0x00 (0000ms, 24918ms total) +T3170 086:201 JLINK_WriteReg(R8, 0x00000000) returns 0x00 (0000ms, 24918ms total) +T3170 086:201 JLINK_WriteReg(R9, 0x2000013C) returns 0x00 (0000ms, 24918ms total) +T3170 086:201 JLINK_WriteReg(R10, 0x00000000) returns 0x00 (0000ms, 24918ms total) +T3170 086:201 JLINK_WriteReg(R11, 0x00000000) returns 0x00 (0000ms, 24918ms total) +T3170 086:201 JLINK_WriteReg(R12, 0x00000000) returns 0x00 (0000ms, 24918ms total) +T3170 086:201 JLINK_WriteReg(R13 (SP), 0x20001000) returns 0x00 (0000ms, 24918ms total) +T3170 086:201 JLINK_WriteReg(R14, 0x20000001) returns 0x00 (0000ms, 24918ms total) +T3170 086:201 JLINK_WriteReg(R15 (PC), 0x2000005C) returns 0x00 (0000ms, 24918ms total) +T3170 086:201 JLINK_WriteReg(XPSR, 0x01000000) returns 0x00 (0000ms, 24918ms total) +T3170 086:201 JLINK_WriteReg(MSP, 0x20001000) returns 0x00 (0000ms, 24918ms total) +T3170 086:201 JLINK_WriteReg(PSP, 0x20001000) returns 0x00 (0000ms, 24918ms total) +T3170 086:201 JLINK_WriteReg(CFBP, 0x00000000) returns 0x00 (0000ms, 24918ms total) +T3170 086:201 JLINK_SetBPEx(Addr = 0x20000000, Type = 0xFFFFFFF2) returns 0x00000019 (0000ms, 24918ms total) +T3170 086:201 JLINK_Go() -- CPU_ReadMem(4 bytes @ 0xE0001000) (0008ms, 24926ms total) +T3170 086:209 JLINK_IsHalted() -- CPU_ReadMem(2 bytes @ 0x20000000) returns TRUE (0090ms, 25016ms total) +T3170 086:299 JLINK_ReadReg(R15 (PC)) returns 0x20000000 (0001ms, 24927ms total) +T3170 086:300 JLINK_ClrBPEx(BPHandle = 0x00000019) returns 0x00 (0000ms, 24927ms total) +T3170 086:300 JLINK_ReadReg(R0) returns 0x00000000 (0000ms, 24927ms total) +T3170 086:300 JLINK_WriteMem(0x20000144, 0x0080 Bytes, ...) - Data: 02 F8 01 1B 0D D0 1B 0A F8 E7 11 F8 01 3B 00 2B ... -- CPU_WriteMem(128 bytes @ 0x20000144) returns 0x80 (0003ms, 24930ms total) +T3170 086:303 JLINK_WriteReg(R0, 0x00000500) returns 0x00 (0000ms, 24930ms total) +T3170 086:303 JLINK_WriteReg(R1, 0x00000080) returns 0x00 (0000ms, 24930ms total) +T3170 086:303 JLINK_WriteReg(R2, 0x20000144) returns 0x00 (0000ms, 24930ms total) +T3170 086:303 JLINK_WriteReg(R3, 0x00000000) returns 0x00 (0000ms, 24930ms total) +T3170 086:303 JLINK_WriteReg(R4, 0x00000000) returns 0x00 (0000ms, 24930ms total) +T3170 086:303 JLINK_WriteReg(R5, 0x00000000) returns 0x00 (0000ms, 24930ms total) +T3170 086:303 JLINK_WriteReg(R6, 0x00000000) returns 0x00 (0000ms, 24930ms total) +T3170 086:303 JLINK_WriteReg(R7, 0x00000000) returns 0x00 (0000ms, 24930ms total) +T3170 086:303 JLINK_WriteReg(R8, 0x00000000) returns 0x00 (0000ms, 24930ms total) +T3170 086:303 JLINK_WriteReg(R9, 0x2000013C) returns 0x00 (0000ms, 24930ms total) +T3170 086:303 JLINK_WriteReg(R10, 0x00000000) returns 0x00 (0000ms, 24930ms total) +T3170 086:303 JLINK_WriteReg(R11, 0x00000000) returns 0x00 (0000ms, 24930ms total) +T3170 086:303 JLINK_WriteReg(R12, 0x00000000) returns 0x00 (0000ms, 24930ms total) +T3170 086:303 JLINK_WriteReg(R13 (SP), 0x20001000) returns 0x00 (0000ms, 24930ms total) +T3170 086:303 JLINK_WriteReg(R14, 0x20000001) returns 0x00 (0000ms, 24930ms total) +T3170 086:303 JLINK_WriteReg(R15 (PC), 0x2000005C) returns 0x00 (0000ms, 24930ms total) +T3170 086:303 JLINK_WriteReg(XPSR, 0x01000000) returns 0x00 (0000ms, 24930ms total) +T3170 086:303 JLINK_WriteReg(MSP, 0x20001000) returns 0x00 (0000ms, 24930ms total) +T3170 086:303 JLINK_WriteReg(PSP, 0x20001000) returns 0x00 (0000ms, 24930ms total) +T3170 086:303 JLINK_WriteReg(CFBP, 0x00000000) returns 0x00 (0000ms, 24930ms total) +T3170 086:303 JLINK_SetBPEx(Addr = 0x20000000, Type = 0xFFFFFFF2) returns 0x0000001A (0000ms, 24930ms total) +T3170 086:303 JLINK_Go() -- CPU_ReadMem(4 bytes @ 0xE0001000) (0006ms, 24936ms total) +T3170 086:309 JLINK_IsHalted() -- CPU_ReadMem(2 bytes @ 0x20000000) returns TRUE (0036ms, 24972ms total) +T3170 086:346 JLINK_ReadReg(R15 (PC)) returns 0x20000000 (0000ms, 24936ms total) +T3170 086:346 JLINK_ClrBPEx(BPHandle = 0x0000001A) returns 0x00 (0000ms, 24936ms total) +T3170 086:346 JLINK_ReadReg(R0) returns 0x00000000 (0000ms, 24936ms total) +T3170 086:346 JLINK_WriteMem(0x20000144, 0x0080 Bytes, ...) - Data: C6 15 17 D0 D8 B2 E1 B2 40 1A 50 EA 05 61 10 D1 ... -- CPU_WriteMem(128 bytes @ 0x20000144) returns 0x80 (0055ms, 24991ms total) +T3170 086:401 JLINK_WriteReg(R0, 0x00000580) returns 0x00 (0000ms, 24991ms total) +T3170 086:401 JLINK_WriteReg(R1, 0x00000080) returns 0x00 (0000ms, 24991ms total) +T3170 086:401 JLINK_WriteReg(R2, 0x20000144) returns 0x00 (0000ms, 24991ms total) +T3170 086:401 JLINK_WriteReg(R3, 0x00000000) returns 0x00 (0000ms, 24991ms total) +T3170 086:401 JLINK_WriteReg(R4, 0x00000000) returns 0x00 (0000ms, 24991ms total) +T3170 086:401 JLINK_WriteReg(R5, 0x00000000) returns 0x00 (0000ms, 24991ms total) +T3170 086:401 JLINK_WriteReg(R6, 0x00000000) returns 0x00 (0000ms, 24991ms total) +T3170 086:401 JLINK_WriteReg(R7, 0x00000000) returns 0x00 (0000ms, 24991ms total) +T3170 086:401 JLINK_WriteReg(R8, 0x00000000) returns 0x00 (0000ms, 24991ms total) +T3170 086:401 JLINK_WriteReg(R9, 0x2000013C) returns 0x00 (0000ms, 24991ms total) +T3170 086:401 JLINK_WriteReg(R10, 0x00000000) returns 0x00 (0000ms, 24991ms total) +T3170 086:401 JLINK_WriteReg(R11, 0x00000000) returns 0x00 (0000ms, 24991ms total) +T3170 086:401 JLINK_WriteReg(R12, 0x00000000) returns 0x00 (0000ms, 24991ms total) +T3170 086:401 JLINK_WriteReg(R13 (SP), 0x20001000) returns 0x00 (0000ms, 24991ms total) +T3170 086:401 JLINK_WriteReg(R14, 0x20000001) returns 0x00 (0000ms, 24991ms total) +T3170 086:401 JLINK_WriteReg(R15 (PC), 0x2000005C) returns 0x00 (0000ms, 24991ms total) +T3170 086:401 JLINK_WriteReg(XPSR, 0x01000000) returns 0x00 (0000ms, 24991ms total) +T3170 086:401 JLINK_WriteReg(MSP, 0x20001000) returns 0x00 (0000ms, 24991ms total) +T3170 086:401 JLINK_WriteReg(PSP, 0x20001000) returns 0x00 (0000ms, 24991ms total) +T3170 086:401 JLINK_WriteReg(CFBP, 0x00000000) returns 0x00 (0000ms, 24991ms total) +T3170 086:401 JLINK_SetBPEx(Addr = 0x20000000, Type = 0xFFFFFFF2) returns 0x0000001B (0000ms, 24991ms total) +T3170 086:401 JLINK_Go() -- CPU_ReadMem(4 bytes @ 0xE0001000) (0009ms, 25000ms total) +T3170 086:410 JLINK_IsHalted() -- CPU_ReadMem(2 bytes @ 0x20000000) returns TRUE (0093ms, 25093ms total) +T3170 086:503 JLINK_ReadReg(R15 (PC)) returns 0x20000000 (0000ms, 25000ms total) +T3170 086:506 JLINK_ClrBPEx(BPHandle = 0x0000001B) returns 0x00 (0000ms, 25000ms total) +T3170 086:506 JLINK_ReadReg(R0) returns 0x00000000 (0000ms, 25000ms total) +T3170 086:507 JLINK_WriteMem(0x20000144, 0x0080 Bytes, ...) - Data: FB D1 11 F8 01 3B 00 2B 02 F8 01 3B F9 D1 70 47 ... -- CPU_WriteMem(128 bytes @ 0x20000144) returns 0x80 (0003ms, 25003ms total) +T3170 086:510 JLINK_WriteReg(R0, 0x00000600) returns 0x00 (0000ms, 25003ms total) +T3170 086:510 JLINK_WriteReg(R1, 0x00000080) returns 0x00 (0000ms, 25003ms total) +T3170 086:510 JLINK_WriteReg(R2, 0x20000144) returns 0x00 (0000ms, 25003ms total) +T3170 086:510 JLINK_WriteReg(R3, 0x00000000) returns 0x00 (0000ms, 25003ms total) +T3170 086:510 JLINK_WriteReg(R4, 0x00000000) returns 0x00 (0000ms, 25003ms total) +T3170 086:510 JLINK_WriteReg(R5, 0x00000000) returns 0x00 (0000ms, 25003ms total) +T3170 086:511 JLINK_WriteReg(R6, 0x00000000) returns 0x00 (0000ms, 25004ms total) +T3170 086:511 JLINK_WriteReg(R7, 0x00000000) returns 0x00 (0000ms, 25004ms total) +T3170 086:511 JLINK_WriteReg(R8, 0x00000000) returns 0x00 (0000ms, 25004ms total) +T3170 086:511 JLINK_WriteReg(R9, 0x2000013C) returns 0x00 (0000ms, 25004ms total) +T3170 086:511 JLINK_WriteReg(R10, 0x00000000) returns 0x00 (0000ms, 25004ms total) +T3170 086:511 JLINK_WriteReg(R11, 0x00000000) returns 0x00 (0000ms, 25004ms total) +T3170 086:511 JLINK_WriteReg(R12, 0x00000000) returns 0x00 (0000ms, 25004ms total) +T3170 086:511 JLINK_WriteReg(R13 (SP), 0x20001000) returns 0x00 (0000ms, 25004ms total) +T3170 086:511 JLINK_WriteReg(R14, 0x20000001) returns 0x00 (0000ms, 25004ms total) +T3170 086:511 JLINK_WriteReg(R15 (PC), 0x2000005C) returns 0x00 (0000ms, 25004ms total) +T3170 086:511 JLINK_WriteReg(XPSR, 0x01000000) returns 0x00 (0000ms, 25004ms total) +T3170 086:511 JLINK_WriteReg(MSP, 0x20001000) returns 0x00 (0000ms, 25004ms total) +T3170 086:511 JLINK_WriteReg(PSP, 0x20001000) returns 0x00 (0000ms, 25004ms total) +T3170 086:511 JLINK_WriteReg(CFBP, 0x00000000) returns 0x00 (0000ms, 25004ms total) +T3170 086:511 JLINK_SetBPEx(Addr = 0x20000000, Type = 0xFFFFFFF2) returns 0x0000001C (0000ms, 25004ms total) +T3170 086:511 JLINK_Go() -- CPU_ReadMem(4 bytes @ 0xE0001000) (0015ms, 25019ms total) +T3170 086:526 JLINK_IsHalted() -- CPU_ReadMem(2 bytes @ 0x20000000) returns TRUE (0077ms, 25096ms total) +T3170 086:604 JLINK_ReadReg(R15 (PC)) returns 0x20000000 (0000ms, 25019ms total) +T3170 086:604 JLINK_ClrBPEx(BPHandle = 0x0000001C) returns 0x00 (0000ms, 25019ms total) +T3170 086:604 JLINK_ReadReg(R0) returns 0x00000000 (0000ms, 25019ms total) +T3170 086:604 JLINK_WriteMem(0x20000144, 0x0080 Bytes, ...) - Data: 03 0C 00 F0 1B 80 CC F1 04 0C BC F1 02 0F 18 BF ... -- CPU_WriteMem(128 bytes @ 0x20000144) returns 0x80 (0003ms, 25022ms total) +T3170 086:607 JLINK_WriteReg(R0, 0x00000680) returns 0x00 (0000ms, 25022ms total) +T3170 086:607 JLINK_WriteReg(R1, 0x00000080) returns 0x00 (0000ms, 25022ms total) +T3170 086:607 JLINK_WriteReg(R2, 0x20000144) returns 0x00 (0000ms, 25022ms total) +T3170 086:607 JLINK_WriteReg(R3, 0x00000000) returns 0x00 (0000ms, 25022ms total) +T3170 086:607 JLINK_WriteReg(R4, 0x00000000) returns 0x00 (0000ms, 25022ms total) +T3170 086:607 JLINK_WriteReg(R5, 0x00000000) returns 0x00 (0000ms, 25022ms total) +T3170 086:607 JLINK_WriteReg(R6, 0x00000000) returns 0x00 (0000ms, 25022ms total) +T3170 086:607 JLINK_WriteReg(R7, 0x00000000) returns 0x00 (0000ms, 25022ms total) +T3170 086:607 JLINK_WriteReg(R8, 0x00000000) returns 0x00 (0000ms, 25022ms total) +T3170 086:607 JLINK_WriteReg(R9, 0x2000013C) returns 0x00 (0000ms, 25022ms total) +T3170 086:607 JLINK_WriteReg(R10, 0x00000000) returns 0x00 (0000ms, 25022ms total) +T3170 086:607 JLINK_WriteReg(R11, 0x00000000) returns 0x00 (0000ms, 25022ms total) +T3170 086:607 JLINK_WriteReg(R12, 0x00000000) returns 0x00 (0000ms, 25022ms total) +T3170 086:607 JLINK_WriteReg(R13 (SP), 0x20001000) returns 0x00 (0000ms, 25022ms total) +T3170 086:607 JLINK_WriteReg(R14, 0x20000001) returns 0x00 (0000ms, 25022ms total) +T3170 086:607 JLINK_WriteReg(R15 (PC), 0x2000005C) returns 0x00 (0000ms, 25022ms total) +T3170 086:607 JLINK_WriteReg(XPSR, 0x01000000) returns 0x00 (0000ms, 25022ms total) +T3170 086:607 JLINK_WriteReg(MSP, 0x20001000) returns 0x00 (0000ms, 25022ms total) +T3170 086:607 JLINK_WriteReg(PSP, 0x20001000) returns 0x00 (0000ms, 25022ms total) +T3170 086:607 JLINK_WriteReg(CFBP, 0x00000000) returns 0x00 (0000ms, 25022ms total) +T3170 086:607 JLINK_SetBPEx(Addr = 0x20000000, Type = 0xFFFFFFF2) returns 0x0000001D (0000ms, 25022ms total) +T3170 086:607 JLINK_Go() -- CPU_ReadMem(4 bytes @ 0xE0001000) (0006ms, 25028ms total) +T3170 086:613 JLINK_IsHalted() -- CPU_ReadMem(2 bytes @ 0x20000000) returns TRUE (0091ms, 25119ms total) +T3170 086:704 JLINK_ReadReg(R15 (PC)) returns 0x20000000 (0000ms, 25028ms total) +T3170 086:704 JLINK_ClrBPEx(BPHandle = 0x0000001D) returns 0x00 (0000ms, 25028ms total) +T3170 086:704 JLINK_ReadReg(R0) returns 0x00000000 (0000ms, 25028ms total) +T3170 086:704 JLINK_WriteMem(0x20000144, 0x0080 Bytes, ...) - Data: 00 F8 01 2B 70 47 10 B5 04 46 10 F0 03 0F 08 BF ... -- CPU_WriteMem(128 bytes @ 0x20000144) returns 0x80 (0004ms, 25032ms total) +T3170 086:708 JLINK_WriteReg(R0, 0x00000700) returns 0x00 (0000ms, 25032ms total) +T3170 086:708 JLINK_WriteReg(R1, 0x00000080) returns 0x00 (0000ms, 25032ms total) +T3170 086:708 JLINK_WriteReg(R2, 0x20000144) returns 0x00 (0000ms, 25032ms total) +T3170 086:708 JLINK_WriteReg(R3, 0x00000000) returns 0x00 (0000ms, 25032ms total) +T3170 086:708 JLINK_WriteReg(R4, 0x00000000) returns 0x00 (0000ms, 25032ms total) +T3170 086:708 JLINK_WriteReg(R5, 0x00000000) returns 0x00 (0000ms, 25032ms total) +T3170 086:708 JLINK_WriteReg(R6, 0x00000000) returns 0x00 (0000ms, 25032ms total) +T3170 086:708 JLINK_WriteReg(R7, 0x00000000) returns 0x00 (0000ms, 25032ms total) +T3170 086:708 JLINK_WriteReg(R8, 0x00000000) returns 0x00 (0000ms, 25032ms total) +T3170 086:708 JLINK_WriteReg(R9, 0x2000013C) returns 0x00 (0000ms, 25032ms total) +T3170 086:708 JLINK_WriteReg(R10, 0x00000000) returns 0x00 (0000ms, 25032ms total) +T3170 086:708 JLINK_WriteReg(R11, 0x00000000) returns 0x00 (0000ms, 25032ms total) +T3170 086:708 JLINK_WriteReg(R12, 0x00000000) returns 0x00 (0000ms, 25032ms total) +T3170 086:708 JLINK_WriteReg(R13 (SP), 0x20001000) returns 0x00 (0000ms, 25032ms total) +T3170 086:708 JLINK_WriteReg(R14, 0x20000001) returns 0x00 (0000ms, 25032ms total) +T3170 086:708 JLINK_WriteReg(R15 (PC), 0x2000005C) returns 0x00 (0000ms, 25032ms total) +T3170 086:708 JLINK_WriteReg(XPSR, 0x01000000) returns 0x00 (0000ms, 25032ms total) +T3170 086:708 JLINK_WriteReg(MSP, 0x20001000) returns 0x00 (0000ms, 25032ms total) +T3170 086:708 JLINK_WriteReg(PSP, 0x20001000) returns 0x00 (0000ms, 25032ms total) +T3170 086:708 JLINK_WriteReg(CFBP, 0x00000000) returns 0x00 (0000ms, 25032ms total) +T3170 086:708 JLINK_SetBPEx(Addr = 0x20000000, Type = 0xFFFFFFF2) returns 0x0000001E (0000ms, 25032ms total) +T3170 086:708 JLINK_Go() -- CPU_ReadMem(4 bytes @ 0xE0001000) (0044ms, 25076ms total) +T3170 086:753 JLINK_IsHalted() -- CPU_ReadMem(2 bytes @ 0x20000000) returns TRUE (0056ms, 25132ms total) +T3170 086:809 JLINK_ReadReg(R15 (PC)) returns 0x20000000 (0000ms, 25076ms total) +T3170 086:809 JLINK_ClrBPEx(BPHandle = 0x0000001E) returns 0x00 (0000ms, 25076ms total) +T3170 086:809 JLINK_ReadReg(R0) returns 0x00000000 (0000ms, 25076ms total) +T3170 086:809 JLINK_WriteMem(0x20000144, 0x0080 Bytes, ...) - Data: 00 F0 04 F8 20 78 00 28 F9 D1 10 BD 08 B5 69 46 ... -- CPU_WriteMem(128 bytes @ 0x20000144) returns 0x80 (0004ms, 25080ms total) +T3170 086:813 JLINK_WriteReg(R0, 0x00000780) returns 0x00 (0000ms, 25080ms total) +T3170 086:813 JLINK_WriteReg(R1, 0x00000080) returns 0x00 (0000ms, 25080ms total) +T3170 086:813 JLINK_WriteReg(R2, 0x20000144) returns 0x00 (0000ms, 25080ms total) +T3170 086:813 JLINK_WriteReg(R3, 0x00000000) returns 0x00 (0000ms, 25080ms total) +T3170 086:813 JLINK_WriteReg(R4, 0x00000000) returns 0x00 (0000ms, 25080ms total) +T3170 086:813 JLINK_WriteReg(R5, 0x00000000) returns 0x00 (0000ms, 25080ms total) +T3170 086:813 JLINK_WriteReg(R6, 0x00000000) returns 0x00 (0000ms, 25080ms total) +T3170 086:813 JLINK_WriteReg(R7, 0x00000000) returns 0x00 (0000ms, 25080ms total) +T3170 086:813 JLINK_WriteReg(R8, 0x00000000) returns 0x00 (0000ms, 25080ms total) +T3170 086:813 JLINK_WriteReg(R9, 0x2000013C) returns 0x00 (0000ms, 25080ms total) +T3170 086:813 JLINK_WriteReg(R10, 0x00000000) returns 0x00 (0000ms, 25080ms total) +T3170 086:813 JLINK_WriteReg(R11, 0x00000000) returns 0x00 (0000ms, 25080ms total) +T3170 086:813 JLINK_WriteReg(R12, 0x00000000) returns 0x00 (0000ms, 25080ms total) +T3170 086:813 JLINK_WriteReg(R13 (SP), 0x20001000) returns 0x00 (0000ms, 25080ms total) +T3170 086:813 JLINK_WriteReg(R14, 0x20000001) returns 0x00 (0000ms, 25080ms total) +T3170 086:813 JLINK_WriteReg(R15 (PC), 0x2000005C) returns 0x00 (0000ms, 25080ms total) +T3170 086:813 JLINK_WriteReg(XPSR, 0x01000000) returns 0x00 (0000ms, 25080ms total) +T3170 086:813 JLINK_WriteReg(MSP, 0x20001000) returns 0x00 (0000ms, 25080ms total) +T3170 086:813 JLINK_WriteReg(PSP, 0x20001000) returns 0x00 (0000ms, 25080ms total) +T3170 086:813 JLINK_WriteReg(CFBP, 0x00000000) returns 0x00 (0001ms, 25081ms total) +T3170 086:814 JLINK_SetBPEx(Addr = 0x20000000, Type = 0xFFFFFFF2) returns 0x0000001F (0000ms, 25081ms total) +T3170 086:814 JLINK_Go() -- CPU_ReadMem(4 bytes @ 0xE0001000) (0089ms, 25170ms total) +T3170 086:903 JLINK_IsHalted() -- CPU_ReadMem(2 bytes @ 0x20000000) returns TRUE (0008ms, 25178ms total) +T3170 086:911 JLINK_ReadReg(R15 (PC)) returns 0x20000000 (0000ms, 25170ms total) +T3170 086:911 JLINK_ClrBPEx(BPHandle = 0x0000001F) returns 0x00 (0000ms, 25170ms total) +T3170 086:911 JLINK_ReadReg(R0) returns 0x00000000 (0000ms, 25170ms total) +T3170 086:911 JLINK_WriteMem(0x20000144, 0x0080 Bytes, ...) - Data: C0 09 AC E8 C0 09 8D 46 70 47 10 B5 04 46 AF F3 ... -- CPU_WriteMem(128 bytes @ 0x20000144) returns 0x80 (0002ms, 25172ms total) +T3170 086:913 JLINK_WriteReg(R0, 0x00000800) returns 0x00 (0000ms, 25172ms total) +T3170 086:913 JLINK_WriteReg(R1, 0x00000080) returns 0x00 (0000ms, 25172ms total) +T3170 086:913 JLINK_WriteReg(R2, 0x20000144) returns 0x00 (0001ms, 25173ms total) +T3170 086:914 JLINK_WriteReg(R3, 0x00000000) returns 0x00 (0000ms, 25173ms total) +T3170 086:914 JLINK_WriteReg(R4, 0x00000000) returns 0x00 (0000ms, 25173ms total) +T3170 086:914 JLINK_WriteReg(R5, 0x00000000) returns 0x00 (0000ms, 25173ms total) +T3170 086:914 JLINK_WriteReg(R6, 0x00000000) returns 0x00 (0000ms, 25173ms total) +T3170 086:914 JLINK_WriteReg(R7, 0x00000000) returns 0x00 (0000ms, 25173ms total) +T3170 086:914 JLINK_WriteReg(R8, 0x00000000) returns 0x00 (0000ms, 25173ms total) +T3170 086:914 JLINK_WriteReg(R9, 0x2000013C) returns 0x00 (0000ms, 25173ms total) +T3170 086:914 JLINK_WriteReg(R10, 0x00000000) returns 0x00 (0000ms, 25173ms total) +T3170 086:914 JLINK_WriteReg(R11, 0x00000000) returns 0x00 (0000ms, 25173ms total) +T3170 086:914 JLINK_WriteReg(R12, 0x00000000) returns 0x00 (0000ms, 25173ms total) +T3170 086:914 JLINK_WriteReg(R13 (SP), 0x20001000) returns 0x00 (0000ms, 25173ms total) +T3170 086:914 JLINK_WriteReg(R14, 0x20000001) returns 0x00 (0000ms, 25173ms total) +T3170 086:914 JLINK_WriteReg(R15 (PC), 0x2000005C) returns 0x00 (0000ms, 25173ms total) +T3170 086:914 JLINK_WriteReg(XPSR, 0x01000000) returns 0x00 (0000ms, 25173ms total) +T3170 086:914 JLINK_WriteReg(MSP, 0x20001000) returns 0x00 (0000ms, 25173ms total) +T3170 086:914 JLINK_WriteReg(PSP, 0x20001000) returns 0x00 (0000ms, 25173ms total) +T3170 086:914 JLINK_WriteReg(CFBP, 0x00000000) returns 0x00 (0000ms, 25173ms total) +T3170 086:914 JLINK_SetBPEx(Addr = 0x20000000, Type = 0xFFFFFFF2) returns 0x00000020 (0000ms, 25173ms total) +T3170 086:914 JLINK_Go() -- CPU_ReadMem(4 bytes @ 0xE0001000) (0088ms, 25261ms total) +T3170 087:002 JLINK_IsHalted() -- CPU_ReadMem(2 bytes @ 0x20000000) returns TRUE (0006ms, 25267ms total) +T3170 087:008 JLINK_ReadReg(R15 (PC)) returns 0x20000000 (0000ms, 25261ms total) +T3170 087:008 JLINK_ClrBPEx(BPHandle = 0x00000020) returns 0x00 (0000ms, 25261ms total) +T3170 087:008 JLINK_ReadReg(R0) returns 0x00000000 (0000ms, 25261ms total) +T3170 087:008 JLINK_WriteMem(0x20000144, 0x0080 Bytes, ...) - Data: BD E8 70 40 0A 20 FF F7 81 BF 10 B5 04 F0 99 F8 ... -- CPU_WriteMem(128 bytes @ 0x20000144) returns 0x80 (0003ms, 25264ms total) +T3170 087:011 JLINK_WriteReg(R0, 0x00000880) returns 0x00 (0000ms, 25264ms total) +T3170 087:011 JLINK_WriteReg(R1, 0x00000080) returns 0x00 (0000ms, 25264ms total) +T3170 087:011 JLINK_WriteReg(R2, 0x20000144) returns 0x00 (0000ms, 25264ms total) +T3170 087:011 JLINK_WriteReg(R3, 0x00000000) returns 0x00 (0000ms, 25264ms total) +T3170 087:011 JLINK_WriteReg(R4, 0x00000000) returns 0x00 (0000ms, 25264ms total) +T3170 087:011 JLINK_WriteReg(R5, 0x00000000) returns 0x00 (0000ms, 25264ms total) +T3170 087:011 JLINK_WriteReg(R6, 0x00000000) returns 0x00 (0000ms, 25264ms total) +T3170 087:011 JLINK_WriteReg(R7, 0x00000000) returns 0x00 (0000ms, 25264ms total) +T3170 087:011 JLINK_WriteReg(R8, 0x00000000) returns 0x00 (0000ms, 25264ms total) +T3170 087:011 JLINK_WriteReg(R9, 0x2000013C) returns 0x00 (0001ms, 25265ms total) +T3170 087:012 JLINK_WriteReg(R10, 0x00000000) returns 0x00 (0000ms, 25265ms total) +T3170 087:012 JLINK_WriteReg(R11, 0x00000000) returns 0x00 (0000ms, 25265ms total) +T3170 087:012 JLINK_WriteReg(R12, 0x00000000) returns 0x00 (0000ms, 25265ms total) +T3170 087:012 JLINK_WriteReg(R13 (SP), 0x20001000) returns 0x00 (0000ms, 25265ms total) +T3170 087:012 JLINK_WriteReg(R14, 0x20000001) returns 0x00 (0000ms, 25265ms total) +T3170 087:012 JLINK_WriteReg(R15 (PC), 0x2000005C) returns 0x00 (0000ms, 25265ms total) +T3170 087:012 JLINK_WriteReg(XPSR, 0x01000000) returns 0x00 (0000ms, 25265ms total) +T3170 087:012 JLINK_WriteReg(MSP, 0x20001000) returns 0x00 (0000ms, 25265ms total) +T3170 087:012 JLINK_WriteReg(PSP, 0x20001000) returns 0x00 (0000ms, 25265ms total) +T3170 087:012 JLINK_WriteReg(CFBP, 0x00000000) returns 0x00 (0000ms, 25265ms total) +T3170 087:012 JLINK_SetBPEx(Addr = 0x20000000, Type = 0xFFFFFFF2) returns 0x00000021 (0000ms, 25265ms total) +T3170 087:012 JLINK_Go() -- CPU_ReadMem(4 bytes @ 0xE0001000) (0087ms, 25352ms total) +T3170 087:099 JLINK_IsHalted() -- CPU_ReadMem(2 bytes @ 0x20000000) returns TRUE (0009ms, 25361ms total) +T3170 087:108 JLINK_ReadReg(R15 (PC)) returns 0x20000000 (0000ms, 25352ms total) +T3170 087:108 JLINK_ClrBPEx(BPHandle = 0x00000021) returns 0x00 (0000ms, 25352ms total) +T3170 087:108 JLINK_ReadReg(R0) returns 0x00000000 (0000ms, 25352ms total) +T3170 087:108 JLINK_WriteMem(0x20000144, 0x0080 Bytes, ...) - Data: 10 B5 1A 49 89 6C 41 F4 80 11 18 4A 91 64 11 46 ... -- CPU_WriteMem(128 bytes @ 0x20000144) returns 0x80 (0004ms, 25356ms total) +T3170 087:112 JLINK_WriteReg(R0, 0x00000900) returns 0x00 (0001ms, 25357ms total) +T3170 087:113 JLINK_WriteReg(R1, 0x00000080) returns 0x00 (0000ms, 25357ms total) +T3170 087:113 JLINK_WriteReg(R2, 0x20000144) returns 0x00 (0000ms, 25357ms total) +T3170 087:113 JLINK_WriteReg(R3, 0x00000000) returns 0x00 (0000ms, 25357ms total) +T3170 087:113 JLINK_WriteReg(R4, 0x00000000) returns 0x00 (0000ms, 25357ms total) +T3170 087:113 JLINK_WriteReg(R5, 0x00000000) returns 0x00 (0000ms, 25357ms total) +T3170 087:113 JLINK_WriteReg(R6, 0x00000000) returns 0x00 (0000ms, 25357ms total) +T3170 087:113 JLINK_WriteReg(R7, 0x00000000) returns 0x00 (0000ms, 25357ms total) +T3170 087:113 JLINK_WriteReg(R8, 0x00000000) returns 0x00 (0000ms, 25357ms total) +T3170 087:113 JLINK_WriteReg(R9, 0x2000013C) returns 0x00 (0000ms, 25357ms total) +T3170 087:113 JLINK_WriteReg(R10, 0x00000000) returns 0x00 (0000ms, 25357ms total) +T3170 087:113 JLINK_WriteReg(R11, 0x00000000) returns 0x00 (0000ms, 25357ms total) +T3170 087:113 JLINK_WriteReg(R12, 0x00000000) returns 0x00 (0000ms, 25357ms total) +T3170 087:113 JLINK_WriteReg(R13 (SP), 0x20001000) returns 0x00 (0000ms, 25357ms total) +T3170 087:113 JLINK_WriteReg(R14, 0x20000001) returns 0x00 (0000ms, 25357ms total) +T3170 087:113 JLINK_WriteReg(R15 (PC), 0x2000005C) returns 0x00 (0000ms, 25357ms total) +T3170 087:113 JLINK_WriteReg(XPSR, 0x01000000) returns 0x00 (0000ms, 25357ms total) +T3170 087:113 JLINK_WriteReg(MSP, 0x20001000) returns 0x00 (0000ms, 25357ms total) +T3170 087:113 JLINK_WriteReg(PSP, 0x20001000) returns 0x00 (0000ms, 25357ms total) +T3170 087:113 JLINK_WriteReg(CFBP, 0x00000000) returns 0x00 (0000ms, 25357ms total) +T3170 087:113 JLINK_SetBPEx(Addr = 0x20000000, Type = 0xFFFFFFF2) returns 0x00000022 (0000ms, 25357ms total) +T3170 087:113 JLINK_Go() -- CPU_ReadMem(4 bytes @ 0xE0001000) (0088ms, 25445ms total) +T3170 087:201 JLINK_IsHalted() -- CPU_ReadMem(2 bytes @ 0x20000000) returns TRUE (0008ms, 25453ms total) +T3170 087:209 JLINK_ReadReg(R15 (PC)) returns 0x20000000 (0000ms, 25445ms total) +T3170 087:209 JLINK_ClrBPEx(BPHandle = 0x00000022) returns 0x00 (0000ms, 25445ms total) +T3170 087:209 JLINK_ReadReg(R0) returns 0x00000000 (0000ms, 25445ms total) +T3170 087:209 JLINK_WriteMem(0x20000144, 0x0080 Bytes, ...) - Data: 05 46 0F 46 2C 46 20 2C 00 D2 04 E0 A4 22 0A A1 ... -- CPU_WriteMem(128 bytes @ 0x20000144) returns 0x80 (0003ms, 25448ms total) +T3170 087:212 JLINK_WriteReg(R0, 0x00000980) returns 0x00 (0000ms, 25448ms total) +T3170 087:212 JLINK_WriteReg(R1, 0x00000080) returns 0x00 (0000ms, 25448ms total) +T3170 087:212 JLINK_WriteReg(R2, 0x20000144) returns 0x00 (0000ms, 25448ms total) +T3170 087:212 JLINK_WriteReg(R3, 0x00000000) returns 0x00 (0000ms, 25448ms total) +T3170 087:212 JLINK_WriteReg(R4, 0x00000000) returns 0x00 (0000ms, 25448ms total) +T3170 087:212 JLINK_WriteReg(R5, 0x00000000) returns 0x00 (0001ms, 25449ms total) +T3170 087:213 JLINK_WriteReg(R6, 0x00000000) returns 0x00 (0000ms, 25449ms total) +T3170 087:213 JLINK_WriteReg(R7, 0x00000000) returns 0x00 (0000ms, 25449ms total) +T3170 087:213 JLINK_WriteReg(R8, 0x00000000) returns 0x00 (0000ms, 25449ms total) +T3170 087:213 JLINK_WriteReg(R9, 0x2000013C) returns 0x00 (0000ms, 25449ms total) +T3170 087:213 JLINK_WriteReg(R10, 0x00000000) returns 0x00 (0000ms, 25449ms total) +T3170 087:213 JLINK_WriteReg(R11, 0x00000000) returns 0x00 (0000ms, 25449ms total) +T3170 087:213 JLINK_WriteReg(R12, 0x00000000) returns 0x00 (0000ms, 25449ms total) +T3170 087:213 JLINK_WriteReg(R13 (SP), 0x20001000) returns 0x00 (0000ms, 25449ms total) +T3170 087:213 JLINK_WriteReg(R14, 0x20000001) returns 0x00 (0000ms, 25449ms total) +T3170 087:213 JLINK_WriteReg(R15 (PC), 0x2000005C) returns 0x00 (0000ms, 25449ms total) +T3170 087:213 JLINK_WriteReg(XPSR, 0x01000000) returns 0x00 (0000ms, 25449ms total) +T3170 087:213 JLINK_WriteReg(MSP, 0x20001000) returns 0x00 (0000ms, 25449ms total) +T3170 087:213 JLINK_WriteReg(PSP, 0x20001000) returns 0x00 (0000ms, 25449ms total) +T3170 087:213 JLINK_WriteReg(CFBP, 0x00000000) returns 0x00 (0000ms, 25449ms total) +T3170 087:213 JLINK_SetBPEx(Addr = 0x20000000, Type = 0xFFFFFFF2) returns 0x00000023 (0000ms, 25449ms total) +T3170 087:213 JLINK_Go() -- CPU_ReadMem(4 bytes @ 0xE0001000) (0089ms, 25538ms total) +T3170 087:302 JLINK_IsHalted() -- CPU_ReadMem(2 bytes @ 0x20000000) returns TRUE (0009ms, 25547ms total) +T3170 087:311 JLINK_ReadReg(R15 (PC)) returns 0x20000000 (0000ms, 25538ms total) +T3170 087:311 JLINK_ClrBPEx(BPHandle = 0x00000023) returns 0x00 (0000ms, 25538ms total) +T3170 087:311 JLINK_ReadReg(R0) returns 0x00000000 (0000ms, 25538ms total) +T3170 087:311 JLINK_WriteMem(0x20000144, 0x0080 Bytes, ...) - Data: 04 46 0D 46 16 46 00 27 B8 46 20 48 84 42 02 D0 ... -- CPU_WriteMem(128 bytes @ 0x20000144) returns 0x80 (0003ms, 25541ms total) +T3170 087:314 JLINK_WriteReg(R0, 0x00000A00) returns 0x00 (0000ms, 25541ms total) +T3170 087:314 JLINK_WriteReg(R1, 0x00000080) returns 0x00 (0000ms, 25541ms total) +T3170 087:314 JLINK_WriteReg(R2, 0x20000144) returns 0x00 (0000ms, 25541ms total) +T3170 087:314 JLINK_WriteReg(R3, 0x00000000) returns 0x00 (0000ms, 25541ms total) +T3170 087:314 JLINK_WriteReg(R4, 0x00000000) returns 0x00 (0000ms, 25541ms total) +T3170 087:314 JLINK_WriteReg(R5, 0x00000000) returns 0x00 (0000ms, 25541ms total) +T3170 087:314 JLINK_WriteReg(R6, 0x00000000) returns 0x00 (0000ms, 25541ms total) +T3170 087:314 JLINK_WriteReg(R7, 0x00000000) returns 0x00 (0000ms, 25541ms total) +T3170 087:314 JLINK_WriteReg(R8, 0x00000000) returns 0x00 (0000ms, 25541ms total) +T3170 087:314 JLINK_WriteReg(R9, 0x2000013C) returns 0x00 (0000ms, 25541ms total) +T3170 087:314 JLINK_WriteReg(R10, 0x00000000) returns 0x00 (0000ms, 25541ms total) +T3170 087:314 JLINK_WriteReg(R11, 0x00000000) returns 0x00 (0000ms, 25541ms total) +T3170 087:314 JLINK_WriteReg(R12, 0x00000000) returns 0x00 (0000ms, 25541ms total) +T3170 087:314 JLINK_WriteReg(R13 (SP), 0x20001000) returns 0x00 (0000ms, 25541ms total) +T3170 087:314 JLINK_WriteReg(R14, 0x20000001) returns 0x00 (0000ms, 25541ms total) +T3170 087:314 JLINK_WriteReg(R15 (PC), 0x2000005C) returns 0x00 (0000ms, 25541ms total) +T3170 087:314 JLINK_WriteReg(XPSR, 0x01000000) returns 0x00 (0000ms, 25541ms total) +T3170 087:314 JLINK_WriteReg(MSP, 0x20001000) returns 0x00 (0000ms, 25541ms total) +T3170 087:314 JLINK_WriteReg(PSP, 0x20001000) returns 0x00 (0000ms, 25541ms total) +T3170 087:314 JLINK_WriteReg(CFBP, 0x00000000) returns 0x00 (0000ms, 25541ms total) +T3170 087:314 JLINK_SetBPEx(Addr = 0x20000000, Type = 0xFFFFFFF2) returns 0x00000024 (0000ms, 25541ms total) +T3170 087:314 JLINK_Go() -- CPU_ReadMem(4 bytes @ 0xE0001000) (0088ms, 25629ms total) +T3170 087:402 JLINK_IsHalted() -- CPU_ReadMem(2 bytes @ 0x20000000) returns TRUE (0009ms, 25638ms total) +T3170 087:411 JLINK_ReadReg(R15 (PC)) returns 0x20000000 (0000ms, 25629ms total) +T3170 087:411 JLINK_ClrBPEx(BPHandle = 0x00000024) returns 0x00 (0000ms, 25629ms total) +T3170 087:411 JLINK_ReadReg(R0) returns 0x00000000 (0000ms, 25629ms total) +T3170 087:411 JLINK_WriteMem(0x20000144, 0x0080 Bytes, ...) - Data: B7 42 EF D3 38 46 BD E8 F0 81 00 00 F8 10 00 20 ... -- CPU_WriteMem(128 bytes @ 0x20000144) returns 0x80 (0004ms, 25633ms total) +T3170 087:415 JLINK_WriteReg(R0, 0x00000A80) returns 0x00 (0000ms, 25633ms total) +T3170 087:415 JLINK_WriteReg(R1, 0x00000080) returns 0x00 (0000ms, 25633ms total) +T3170 087:415 JLINK_WriteReg(R2, 0x20000144) returns 0x00 (0000ms, 25633ms total) +T3170 087:415 JLINK_WriteReg(R3, 0x00000000) returns 0x00 (0000ms, 25633ms total) +T3170 087:415 JLINK_WriteReg(R4, 0x00000000) returns 0x00 (0000ms, 25633ms total) +T3170 087:415 JLINK_WriteReg(R5, 0x00000000) returns 0x00 (0000ms, 25633ms total) +T3170 087:415 JLINK_WriteReg(R6, 0x00000000) returns 0x00 (0000ms, 25633ms total) +T3170 087:415 JLINK_WriteReg(R7, 0x00000000) returns 0x00 (0000ms, 25633ms total) +T3170 087:415 JLINK_WriteReg(R8, 0x00000000) returns 0x00 (0000ms, 25633ms total) +T3170 087:415 JLINK_WriteReg(R9, 0x2000013C) returns 0x00 (0000ms, 25633ms total) +T3170 087:415 JLINK_WriteReg(R10, 0x00000000) returns 0x00 (0000ms, 25633ms total) +T3170 087:415 JLINK_WriteReg(R11, 0x00000000) returns 0x00 (0000ms, 25633ms total) +T3170 087:415 JLINK_WriteReg(R12, 0x00000000) returns 0x00 (0000ms, 25633ms total) +T3170 087:415 JLINK_WriteReg(R13 (SP), 0x20001000) returns 0x00 (0000ms, 25633ms total) +T3170 087:415 JLINK_WriteReg(R14, 0x20000001) returns 0x00 (0000ms, 25633ms total) +T3170 087:415 JLINK_WriteReg(R15 (PC), 0x2000005C) returns 0x00 (0000ms, 25633ms total) +T3170 087:415 JLINK_WriteReg(XPSR, 0x01000000) returns 0x00 (0000ms, 25633ms total) +T3170 087:415 JLINK_WriteReg(MSP, 0x20001000) returns 0x00 (0000ms, 25633ms total) +T3170 087:415 JLINK_WriteReg(PSP, 0x20001000) returns 0x00 (0000ms, 25633ms total) +T3170 087:415 JLINK_WriteReg(CFBP, 0x00000000) returns 0x00 (0000ms, 25633ms total) +T3170 087:415 JLINK_SetBPEx(Addr = 0x20000000, Type = 0xFFFFFFF2) returns 0x00000025 (0000ms, 25633ms total) +T3170 087:415 JLINK_Go() -- CPU_ReadMem(4 bytes @ 0xE0001000) (0090ms, 25723ms total) +T3170 087:505 JLINK_IsHalted() -- CPU_ReadMem(2 bytes @ 0x20000000) returns TRUE (0008ms, 25731ms total) +T3170 087:513 JLINK_ReadReg(R15 (PC)) returns 0x20000000 (0000ms, 25723ms total) +T3170 087:513 JLINK_ClrBPEx(BPHandle = 0x00000025) returns 0x00 (0000ms, 25723ms total) +T3170 087:513 JLINK_ReadReg(R0) returns 0x00000000 (0000ms, 25723ms total) +T3170 087:513 JLINK_WriteMem(0x20000144, 0x0080 Bytes, ...) - Data: 28 75 69 6E 74 38 5F 74 20 2A 29 30 29 00 00 00 ... -- CPU_WriteMem(128 bytes @ 0x20000144) returns 0x80 (0070ms, 25793ms total) +T3170 087:584 JLINK_WriteReg(R0, 0x00000B00) returns 0x00 (0000ms, 25794ms total) +T3170 087:584 JLINK_WriteReg(R1, 0x00000080) returns 0x00 (0000ms, 25794ms total) +T3170 087:584 JLINK_WriteReg(R2, 0x20000144) returns 0x00 (0000ms, 25794ms total) +T3170 087:584 JLINK_WriteReg(R3, 0x00000000) returns 0x00 (0000ms, 25794ms total) +T3170 087:584 JLINK_WriteReg(R4, 0x00000000) returns 0x00 (0000ms, 25794ms total) +T3170 087:584 JLINK_WriteReg(R5, 0x00000000) returns 0x00 (0000ms, 25794ms total) +T3170 087:584 JLINK_WriteReg(R6, 0x00000000) returns 0x00 (0000ms, 25794ms total) +T3170 087:584 JLINK_WriteReg(R7, 0x00000000) returns 0x00 (0000ms, 25794ms total) +T3170 087:584 JLINK_WriteReg(R8, 0x00000000) returns 0x00 (0000ms, 25794ms total) +T3170 087:584 JLINK_WriteReg(R9, 0x2000013C) returns 0x00 (0000ms, 25794ms total) +T3170 087:584 JLINK_WriteReg(R10, 0x00000000) returns 0x00 (0000ms, 25794ms total) +T3170 087:584 JLINK_WriteReg(R11, 0x00000000) returns 0x00 (0000ms, 25794ms total) +T3170 087:584 JLINK_WriteReg(R12, 0x00000000) returns 0x00 (0000ms, 25794ms total) +T3170 087:584 JLINK_WriteReg(R13 (SP), 0x20001000) returns 0x00 (0000ms, 25794ms total) +T3170 087:584 JLINK_WriteReg(R14, 0x20000001) returns 0x00 (0000ms, 25794ms total) +T3170 087:584 JLINK_WriteReg(R15 (PC), 0x2000005C) returns 0x00 (0000ms, 25794ms total) +T3170 087:584 JLINK_WriteReg(XPSR, 0x01000000) returns 0x00 (0000ms, 25794ms total) +T3170 087:584 JLINK_WriteReg(MSP, 0x20001000) returns 0x00 (0000ms, 25794ms total) +T3170 087:584 JLINK_WriteReg(PSP, 0x20001000) returns 0x00 (0000ms, 25794ms total) +T3170 087:584 JLINK_WriteReg(CFBP, 0x00000000) returns 0x00 (0000ms, 25794ms total) +T3170 087:584 JLINK_SetBPEx(Addr = 0x20000000, Type = 0xFFFFFFF2) returns 0x00000026 (0000ms, 25794ms total) +T3170 087:584 JLINK_Go() -- CPU_ReadMem(4 bytes @ 0xE0001000) (0020ms, 25814ms total) +T3170 087:605 JLINK_IsHalted() -- CPU_ReadMem(2 bytes @ 0x20000000) returns TRUE (0007ms, 25822ms total) +T3170 087:612 JLINK_ReadReg(R15 (PC)) returns 0x20000000 (0001ms, 25816ms total) +T3170 087:615 JLINK_ClrBPEx(BPHandle = 0x00000026) returns 0x00 (0000ms, 25816ms total) +T3170 087:699 JLINK_ReadReg(R0) returns 0x00000000 (0000ms, 25816ms total) +T3170 087:699 JLINK_WriteMem(0x20000144, 0x0080 Bytes, ...) - Data: 69 62 72 61 72 69 65 73 5C 6D 73 73 5F 75 61 72 ... -- CPU_WriteMem(128 bytes @ 0x20000144) returns 0x80 (0005ms, 25821ms total) +T3170 087:704 JLINK_WriteReg(R0, 0x00000B80) returns 0x00 (0000ms, 25821ms total) +T3170 087:704 JLINK_WriteReg(R1, 0x00000080) returns 0x00 (0000ms, 25821ms total) +T3170 087:704 JLINK_WriteReg(R2, 0x20000144) returns 0x00 (0000ms, 25821ms total) +T3170 087:704 JLINK_WriteReg(R3, 0x00000000) returns 0x00 (0000ms, 25821ms total) +T3170 087:704 JLINK_WriteReg(R4, 0x00000000) returns 0x00 (0000ms, 25821ms total) +T3170 087:704 JLINK_WriteReg(R5, 0x00000000) returns 0x00 (0000ms, 25821ms total) +T3170 087:704 JLINK_WriteReg(R6, 0x00000000) returns 0x00 (0000ms, 25821ms total) +T3170 087:704 JLINK_WriteReg(R7, 0x00000000) returns 0x00 (0000ms, 25821ms total) +T3170 087:704 JLINK_WriteReg(R8, 0x00000000) returns 0x00 (0000ms, 25821ms total) +T3170 087:704 JLINK_WriteReg(R9, 0x2000013C) returns 0x00 (0000ms, 25821ms total) +T3170 087:704 JLINK_WriteReg(R10, 0x00000000) returns 0x00 (0000ms, 25821ms total) +T3170 087:704 JLINK_WriteReg(R11, 0x00000000) returns 0x00 (0000ms, 25821ms total) +T3170 087:704 JLINK_WriteReg(R12, 0x00000000) returns 0x00 (0000ms, 25821ms total) +T3170 087:704 JLINK_WriteReg(R13 (SP), 0x20001000) returns 0x00 (0000ms, 25821ms total) +T3170 087:704 JLINK_WriteReg(R14, 0x20000001) returns 0x00 (0000ms, 25821ms total) +T3170 087:704 JLINK_WriteReg(R15 (PC), 0x2000005C) returns 0x00 (0000ms, 25821ms total) +T3170 087:704 JLINK_WriteReg(XPSR, 0x01000000) returns 0x00 (0000ms, 25821ms total) +T3170 087:705 JLINK_WriteReg(MSP, 0x20001000) returns 0x00 (0000ms, 25822ms total) +T3170 087:705 JLINK_WriteReg(PSP, 0x20001000) returns 0x00 (0000ms, 25822ms total) +T3170 087:705 JLINK_WriteReg(CFBP, 0x00000000) returns 0x00 (0000ms, 25822ms total) +T3170 087:705 JLINK_SetBPEx(Addr = 0x20000000, Type = 0xFFFFFFF2) returns 0x00000027 (0000ms, 25822ms total) +T3170 087:705 JLINK_Go() -- CPU_ReadMem(4 bytes @ 0xE0001000) (0005ms, 25827ms total) +T3170 087:710 JLINK_IsHalted() -- CPU_ReadMem(2 bytes @ 0x20000000) returns TRUE (0089ms, 25916ms total) +T3170 087:799 JLINK_ReadReg(R15 (PC)) returns 0x20000000 (0000ms, 25827ms total) +T3170 087:799 JLINK_ClrBPEx(BPHandle = 0x00000027) returns 0x00 (0000ms, 25827ms total) +T3170 087:799 JLINK_ReadReg(R0) returns 0x00000000 (0000ms, 25827ms total) +T3170 087:799 JLINK_WriteMem(0x20000144, 0x0080 Bytes, ...) - Data: 84 42 02 D0 64 48 84 42 71 D1 20 68 00 7A 00 F0 ... -- CPU_WriteMem(128 bytes @ 0x20000144) returns 0x80 (0004ms, 25831ms total) +T3170 087:803 JLINK_WriteReg(R0, 0x00000C00) returns 0x00 (0000ms, 25831ms total) +T3170 087:803 JLINK_WriteReg(R1, 0x00000080) returns 0x00 (0000ms, 25831ms total) +T3170 087:803 JLINK_WriteReg(R2, 0x20000144) returns 0x00 (0000ms, 25831ms total) +T3170 087:803 JLINK_WriteReg(R3, 0x00000000) returns 0x00 (0000ms, 25831ms total) +T3170 087:803 JLINK_WriteReg(R4, 0x00000000) returns 0x00 (0000ms, 25831ms total) +T3170 087:803 JLINK_WriteReg(R5, 0x00000000) returns 0x00 (0000ms, 25831ms total) +T3170 087:803 JLINK_WriteReg(R6, 0x00000000) returns 0x00 (0000ms, 25831ms total) +T3170 087:803 JLINK_WriteReg(R7, 0x00000000) returns 0x00 (0000ms, 25831ms total) +T3170 087:803 JLINK_WriteReg(R8, 0x00000000) returns 0x00 (0000ms, 25831ms total) +T3170 087:803 JLINK_WriteReg(R9, 0x2000013C) returns 0x00 (0000ms, 25831ms total) +T3170 087:803 JLINK_WriteReg(R10, 0x00000000) returns 0x00 (0000ms, 25831ms total) +T3170 087:803 JLINK_WriteReg(R11, 0x00000000) returns 0x00 (0000ms, 25831ms total) +T3170 087:803 JLINK_WriteReg(R12, 0x00000000) returns 0x00 (0000ms, 25831ms total) +T3170 087:803 JLINK_WriteReg(R13 (SP), 0x20001000) returns 0x00 (0000ms, 25831ms total) +T3170 087:803 JLINK_WriteReg(R14, 0x20000001) returns 0x00 (0000ms, 25831ms total) +T3170 087:803 JLINK_WriteReg(R15 (PC), 0x2000005C) returns 0x00 (0000ms, 25831ms total) +T3170 087:803 JLINK_WriteReg(XPSR, 0x01000000) returns 0x00 (0000ms, 25831ms total) +T3170 087:803 JLINK_WriteReg(MSP, 0x20001000) returns 0x00 (0000ms, 25831ms total) +T3170 087:803 JLINK_WriteReg(PSP, 0x20001000) returns 0x00 (0000ms, 25831ms total) +T3170 087:803 JLINK_WriteReg(CFBP, 0x00000000) returns 0x00 (0000ms, 25831ms total) +T3170 087:803 JLINK_SetBPEx(Addr = 0x20000000, Type = 0xFFFFFFF2) returns 0x00000028 (0000ms, 25831ms total) +T3170 087:803 JLINK_Go() -- CPU_ReadMem(4 bytes @ 0xE0001000) (0007ms, 25838ms total) +T3170 087:810 JLINK_IsHalted() -- CPU_ReadMem(2 bytes @ 0x20000000) returns TRUE (0053ms, 25891ms total) +T3170 087:863 JLINK_ReadReg(R15 (PC)) returns 0x20000000 (0000ms, 25838ms total) +T3170 087:863 JLINK_ClrBPEx(BPHandle = 0x00000028) returns 0x00 (0000ms, 25838ms total) +T3170 087:863 JLINK_ReadReg(R0) returns 0x00000000 (0000ms, 25838ms total) +T3170 087:863 JLINK_WriteMem(0x20000144, 0x0080 Bytes, ...) - Data: 10 B1 20 46 21 6A 88 47 81 E0 E0 69 00 B1 05 E0 ... -- CPU_WriteMem(128 bytes @ 0x20000144) returns 0x80 (0038ms, 25876ms total) +T3170 087:901 JLINK_WriteReg(R0, 0x00000C80) returns 0x00 (0000ms, 25876ms total) +T3170 087:901 JLINK_WriteReg(R1, 0x00000080) returns 0x00 (0000ms, 25876ms total) +T3170 087:901 JLINK_WriteReg(R2, 0x20000144) returns 0x00 (0000ms, 25876ms total) +T3170 087:901 JLINK_WriteReg(R3, 0x00000000) returns 0x00 (0000ms, 25876ms total) +T3170 087:901 JLINK_WriteReg(R4, 0x00000000) returns 0x00 (0000ms, 25876ms total) +T3170 087:901 JLINK_WriteReg(R5, 0x00000000) returns 0x00 (0000ms, 25876ms total) +T3170 087:901 JLINK_WriteReg(R6, 0x00000000) returns 0x00 (0000ms, 25876ms total) +T3170 087:901 JLINK_WriteReg(R7, 0x00000000) returns 0x00 (0000ms, 25876ms total) +T3170 087:901 JLINK_WriteReg(R8, 0x00000000) returns 0x00 (0000ms, 25876ms total) +T3170 087:901 JLINK_WriteReg(R9, 0x2000013C) returns 0x00 (0000ms, 25876ms total) +T3170 087:901 JLINK_WriteReg(R10, 0x00000000) returns 0x00 (0000ms, 25876ms total) +T3170 087:901 JLINK_WriteReg(R11, 0x00000000) returns 0x00 (0000ms, 25876ms total) +T3170 087:901 JLINK_WriteReg(R12, 0x00000000) returns 0x00 (0000ms, 25876ms total) +T3170 087:901 JLINK_WriteReg(R13 (SP), 0x20001000) returns 0x00 (0000ms, 25876ms total) +T3170 087:901 JLINK_WriteReg(R14, 0x20000001) returns 0x00 (0000ms, 25876ms total) +T3170 087:901 JLINK_WriteReg(R15 (PC), 0x2000005C) returns 0x00 (0000ms, 25876ms total) +T3170 087:901 JLINK_WriteReg(XPSR, 0x01000000) returns 0x00 (0000ms, 25876ms total) +T3170 087:901 JLINK_WriteReg(MSP, 0x20001000) returns 0x00 (0000ms, 25876ms total) +T3170 087:901 JLINK_WriteReg(PSP, 0x20001000) returns 0x00 (0000ms, 25876ms total) +T3170 087:901 JLINK_WriteReg(CFBP, 0x00000000) returns 0x00 (0000ms, 25876ms total) +T3170 087:901 JLINK_SetBPEx(Addr = 0x20000000, Type = 0xFFFFFFF2) returns 0x00000029 (0000ms, 25876ms total) +T3170 087:901 JLINK_Go() -- CPU_ReadMem(4 bytes @ 0xE0001000) (0006ms, 25882ms total) +T3170 087:907 JLINK_IsHalted() -- CPU_ReadMem(2 bytes @ 0x20000000) returns TRUE (0094ms, 25976ms total) +T3170 088:001 JLINK_ReadReg(R15 (PC)) returns 0x20000000 (0000ms, 25882ms total) +T3170 088:001 JLINK_ClrBPEx(BPHandle = 0x00000029) returns 0x00 (0000ms, 25882ms total) +T3170 088:001 JLINK_ReadReg(R0) returns 0x00000000 (0000ms, 25882ms total) +T3170 088:002 JLINK_WriteMem(0x20000144, 0x0080 Bytes, ...) - Data: 88 47 21 68 01 F1 28 00 02 21 02 F0 51 FA 68 B1 ... -- CPU_WriteMem(128 bytes @ 0x20000144) returns 0x80 (0004ms, 25886ms total) +T3170 088:006 JLINK_WriteReg(R0, 0x00000D00) returns 0x00 (0000ms, 25886ms total) +T3170 088:006 JLINK_WriteReg(R1, 0x00000080) returns 0x00 (0000ms, 25886ms total) +T3170 088:006 JLINK_WriteReg(R2, 0x20000144) returns 0x00 (0000ms, 25886ms total) +T3170 088:006 JLINK_WriteReg(R3, 0x00000000) returns 0x00 (0000ms, 25886ms total) +T3170 088:006 JLINK_WriteReg(R4, 0x00000000) returns 0x00 (0000ms, 25886ms total) +T3170 088:006 JLINK_WriteReg(R5, 0x00000000) returns 0x00 (0000ms, 25886ms total) +T3170 088:006 JLINK_WriteReg(R6, 0x00000000) returns 0x00 (0000ms, 25886ms total) +T3170 088:006 JLINK_WriteReg(R7, 0x00000000) returns 0x00 (0000ms, 25886ms total) +T3170 088:006 JLINK_WriteReg(R8, 0x00000000) returns 0x00 (0000ms, 25886ms total) +T3170 088:006 JLINK_WriteReg(R9, 0x2000013C) returns 0x00 (0000ms, 25886ms total) +T3170 088:006 JLINK_WriteReg(R10, 0x00000000) returns 0x00 (0000ms, 25886ms total) +T3170 088:006 JLINK_WriteReg(R11, 0x00000000) returns 0x00 (0000ms, 25886ms total) +T3170 088:006 JLINK_WriteReg(R12, 0x00000000) returns 0x00 (0000ms, 25886ms total) +T3170 088:006 JLINK_WriteReg(R13 (SP), 0x20001000) returns 0x00 (0000ms, 25886ms total) +T3170 088:006 JLINK_WriteReg(R14, 0x20000001) returns 0x00 (0000ms, 25886ms total) +T3170 088:006 JLINK_WriteReg(R15 (PC), 0x2000005C) returns 0x00 (0000ms, 25886ms total) +T3170 088:006 JLINK_WriteReg(XPSR, 0x01000000) returns 0x00 (0000ms, 25886ms total) +T3170 088:006 JLINK_WriteReg(MSP, 0x20001000) returns 0x00 (0000ms, 25886ms total) +T3170 088:006 JLINK_WriteReg(PSP, 0x20001000) returns 0x00 (0000ms, 25886ms total) +T3170 088:006 JLINK_WriteReg(CFBP, 0x00000000) returns 0x00 (0000ms, 25886ms total) +T3170 088:006 JLINK_SetBPEx(Addr = 0x20000000, Type = 0xFFFFFFF2) returns 0x0000002A (0000ms, 25886ms total) +T3170 088:006 JLINK_Go() -- CPU_ReadMem(4 bytes @ 0xE0001000) (0007ms, 25893ms total) +T3170 088:013 JLINK_IsHalted() -- CPU_ReadMem(2 bytes @ 0x20000000) returns TRUE (0089ms, 25982ms total) +T3170 088:102 JLINK_ReadReg(R15 (PC)) returns 0x20000000 (0000ms, 25893ms total) +T3170 088:102 JLINK_ClrBPEx(BPHandle = 0x0000002A) returns 0x00 (0000ms, 25893ms total) +T3170 088:102 JLINK_ReadReg(R0) returns 0x00000000 (0000ms, 25893ms total) +T3170 088:102 JLINK_WriteMem(0x20000144, 0x0080 Bytes, ...) - Data: 05 E0 40 F2 9F 62 05 A1 9E A0 FF F7 67 FB 00 BF ... -- CPU_WriteMem(128 bytes @ 0x20000144) returns 0x80 (0003ms, 25896ms total) +T3170 088:105 JLINK_WriteReg(R0, 0x00000D80) returns 0x00 (0000ms, 25896ms total) +T3170 088:105 JLINK_WriteReg(R1, 0x00000080) returns 0x00 (0000ms, 25896ms total) +T3170 088:105 JLINK_WriteReg(R2, 0x20000144) returns 0x00 (0000ms, 25896ms total) +T3170 088:105 JLINK_WriteReg(R3, 0x00000000) returns 0x00 (0000ms, 25896ms total) +T3170 088:105 JLINK_WriteReg(R4, 0x00000000) returns 0x00 (0000ms, 25896ms total) +T3170 088:105 JLINK_WriteReg(R5, 0x00000000) returns 0x00 (0000ms, 25896ms total) +T3170 088:105 JLINK_WriteReg(R6, 0x00000000) returns 0x00 (0000ms, 25896ms total) +T3170 088:105 JLINK_WriteReg(R7, 0x00000000) returns 0x00 (0000ms, 25896ms total) +T3170 088:105 JLINK_WriteReg(R8, 0x00000000) returns 0x00 (0000ms, 25896ms total) +T3170 088:105 JLINK_WriteReg(R9, 0x2000013C) returns 0x00 (0000ms, 25896ms total) +T3170 088:105 JLINK_WriteReg(R10, 0x00000000) returns 0x00 (0000ms, 25896ms total) +T3170 088:105 JLINK_WriteReg(R11, 0x00000000) returns 0x00 (0000ms, 25896ms total) +T3170 088:105 JLINK_WriteReg(R12, 0x00000000) returns 0x00 (0000ms, 25896ms total) +T3170 088:105 JLINK_WriteReg(R13 (SP), 0x20001000) returns 0x00 (0000ms, 25896ms total) +T3170 088:105 JLINK_WriteReg(R14, 0x20000001) returns 0x00 (0000ms, 25896ms total) +T3170 088:105 JLINK_WriteReg(R15 (PC), 0x2000005C) returns 0x00 (0000ms, 25896ms total) +T3170 088:105 JLINK_WriteReg(XPSR, 0x01000000) returns 0x00 (0000ms, 25896ms total) +T3170 088:105 JLINK_WriteReg(MSP, 0x20001000) returns 0x00 (0000ms, 25896ms total) +T3170 088:105 JLINK_WriteReg(PSP, 0x20001000) returns 0x00 (0000ms, 25896ms total) +T3170 088:105 JLINK_WriteReg(CFBP, 0x00000000) returns 0x00 (0000ms, 25896ms total) +T3170 088:105 JLINK_SetBPEx(Addr = 0x20000000, Type = 0xFFFFFFF2) returns 0x0000002B (0000ms, 25896ms total) +T3170 088:105 JLINK_Go() -- CPU_ReadMem(4 bytes @ 0xE0001000) (0010ms, 25906ms total) +T3170 088:115 JLINK_IsHalted() -- CPU_ReadMem(2 bytes @ 0x20000000) returns TRUE (0091ms, 25997ms total) +T3170 088:207 JLINK_ReadReg(R15 (PC)) returns 0x20000000 (0000ms, 25906ms total) +T3170 088:207 JLINK_ClrBPEx(BPHandle = 0x0000002B) returns 0x00 (0000ms, 25906ms total) +T3170 088:207 JLINK_ReadReg(R0) returns 0x00000000 (0000ms, 25906ms total) +T3170 088:207 JLINK_WriteMem(0x20000144, 0x0080 Bytes, ...) - Data: 73 5F 75 61 72 74 5F 69 72 71 5F 68 61 6E 64 6C ... -- CPU_WriteMem(128 bytes @ 0x20000144) returns 0x80 (0003ms, 25909ms total) +T3170 088:210 JLINK_WriteReg(R0, 0x00000E00) returns 0x00 (0000ms, 25909ms total) +T3170 088:210 JLINK_WriteReg(R1, 0x00000080) returns 0x00 (0000ms, 25909ms total) +T3170 088:210 JLINK_WriteReg(R2, 0x20000144) returns 0x00 (0000ms, 25909ms total) +T3170 088:210 JLINK_WriteReg(R3, 0x00000000) returns 0x00 (0000ms, 25909ms total) +T3170 088:211 JLINK_WriteReg(R4, 0x00000000) returns 0x00 (0000ms, 25909ms total) +T3170 088:211 JLINK_WriteReg(R5, 0x00000000) returns 0x00 (0000ms, 25909ms total) +T3170 088:211 JLINK_WriteReg(R6, 0x00000000) returns 0x00 (0000ms, 25909ms total) +T3170 088:211 JLINK_WriteReg(R7, 0x00000000) returns 0x00 (0000ms, 25909ms total) +T3170 088:211 JLINK_WriteReg(R8, 0x00000000) returns 0x00 (0000ms, 25909ms total) +T3170 088:211 JLINK_WriteReg(R9, 0x2000013C) returns 0x00 (0000ms, 25909ms total) +T3170 088:211 JLINK_WriteReg(R10, 0x00000000) returns 0x00 (0000ms, 25909ms total) +T3170 088:211 JLINK_WriteReg(R11, 0x00000000) returns 0x00 (0000ms, 25909ms total) +T3170 088:211 JLINK_WriteReg(R12, 0x00000000) returns 0x00 (0000ms, 25909ms total) +T3170 088:211 JLINK_WriteReg(R13 (SP), 0x20001000) returns 0x00 (0000ms, 25909ms total) +T3170 088:211 JLINK_WriteReg(R14, 0x20000001) returns 0x00 (0000ms, 25909ms total) +T3170 088:211 JLINK_WriteReg(R15 (PC), 0x2000005C) returns 0x00 (0000ms, 25909ms total) +T3170 088:211 JLINK_WriteReg(XPSR, 0x01000000) returns 0x00 (0000ms, 25909ms total) +T3170 088:211 JLINK_WriteReg(MSP, 0x20001000) returns 0x00 (0000ms, 25909ms total) +T3170 088:211 JLINK_WriteReg(PSP, 0x20001000) returns 0x00 (0000ms, 25909ms total) +T3170 088:211 JLINK_WriteReg(CFBP, 0x00000000) returns 0x00 (0000ms, 25909ms total) +T3170 088:211 JLINK_SetBPEx(Addr = 0x20000000, Type = 0xFFFFFFF2) returns 0x0000002C (0000ms, 25909ms total) +T3170 088:211 JLINK_Go() -- CPU_ReadMem(4 bytes @ 0xE0001000) (0022ms, 25931ms total) +T3170 088:234 JLINK_IsHalted() -- CPU_ReadMem(2 bytes @ 0x20000000) returns TRUE (0070ms, 26001ms total) +T3170 088:304 JLINK_ReadReg(R15 (PC)) returns 0x20000000 (0000ms, 25931ms total) +T3170 088:304 JLINK_ClrBPEx(BPHandle = 0x0000002C) returns 0x00 (0000ms, 25931ms total) +T3170 088:304 JLINK_ReadReg(R0) returns 0x00000000 (0000ms, 25931ms total) +T3170 088:304 JLINK_WriteMem(0x20000144, 0x0080 Bytes, ...) - Data: 61 6E 64 6C 65 72 5F 74 29 20 30 29 20 21 3D 20 ... -- CPU_WriteMem(128 bytes @ 0x20000144) returns 0x80 (0003ms, 25934ms total) +T3170 088:307 JLINK_WriteReg(R0, 0x00000E80) returns 0x00 (0000ms, 25934ms total) +T3170 088:307 JLINK_WriteReg(R1, 0x00000080) returns 0x00 (0000ms, 25934ms total) +T3170 088:307 JLINK_WriteReg(R2, 0x20000144) returns 0x00 (0000ms, 25934ms total) +T3170 088:307 JLINK_WriteReg(R3, 0x00000000) returns 0x00 (0000ms, 25934ms total) +T3170 088:307 JLINK_WriteReg(R4, 0x00000000) returns 0x00 (0000ms, 25934ms total) +T3170 088:307 JLINK_WriteReg(R5, 0x00000000) returns 0x00 (0000ms, 25934ms total) +T3170 088:307 JLINK_WriteReg(R6, 0x00000000) returns 0x00 (0000ms, 25934ms total) +T3170 088:307 JLINK_WriteReg(R7, 0x00000000) returns 0x00 (0000ms, 25934ms total) +T3170 088:307 JLINK_WriteReg(R8, 0x00000000) returns 0x00 (0000ms, 25934ms total) +T3170 088:307 JLINK_WriteReg(R9, 0x2000013C) returns 0x00 (0000ms, 25934ms total) +T3170 088:307 JLINK_WriteReg(R10, 0x00000000) returns 0x00 (0000ms, 25934ms total) +T3170 088:307 JLINK_WriteReg(R11, 0x00000000) returns 0x00 (0000ms, 25934ms total) +T3170 088:307 JLINK_WriteReg(R12, 0x00000000) returns 0x00 (0000ms, 25934ms total) +T3170 088:307 JLINK_WriteReg(R13 (SP), 0x20001000) returns 0x00 (0000ms, 25934ms total) +T3170 088:307 JLINK_WriteReg(R14, 0x20000001) returns 0x00 (0000ms, 25934ms total) +T3170 088:307 JLINK_WriteReg(R15 (PC), 0x2000005C) returns 0x00 (0000ms, 25934ms total) +T3170 088:307 JLINK_WriteReg(XPSR, 0x01000000) returns 0x00 (0000ms, 25934ms total) +T3170 088:307 JLINK_WriteReg(MSP, 0x20001000) returns 0x00 (0000ms, 25934ms total) +T3170 088:307 JLINK_WriteReg(PSP, 0x20001000) returns 0x00 (0000ms, 25934ms total) +T3170 088:307 JLINK_WriteReg(CFBP, 0x00000000) returns 0x00 (0000ms, 25934ms total) +T3170 088:307 JLINK_SetBPEx(Addr = 0x20000000, Type = 0xFFFFFFF2) returns 0x0000002D (0000ms, 25934ms total) +T3170 088:307 JLINK_Go() -- CPU_ReadMem(4 bytes @ 0xE0001000) (0007ms, 25941ms total) +T3170 088:314 JLINK_IsHalted() -- CPU_ReadMem(2 bytes @ 0x20000000) returns TRUE (0090ms, 26031ms total) +T3170 088:404 JLINK_ReadReg(R15 (PC)) returns 0x20000000 (0000ms, 25941ms total) +T3170 088:404 JLINK_ClrBPEx(BPHandle = 0x0000002D) returns 0x00 (0000ms, 25941ms total) +T3170 088:404 JLINK_ReadReg(R0) returns 0x00000000 (0000ms, 25941ms total) +T3170 088:404 JLINK_WriteMem(0x20000144, 0x0080 Bytes, ...) - Data: 20 21 3D 20 74 68 69 73 5F 75 61 72 74 2D 3E 72 ... -- CPU_WriteMem(128 bytes @ 0x20000144) returns 0x80 (0005ms, 25946ms total) +T3170 088:409 JLINK_WriteReg(R0, 0x00000F00) returns 0x00 (0000ms, 25946ms total) +T3170 088:409 JLINK_WriteReg(R1, 0x00000080) returns 0x00 (0000ms, 25946ms total) +T3170 088:409 JLINK_WriteReg(R2, 0x20000144) returns 0x00 (0000ms, 25946ms total) +T3170 088:409 JLINK_WriteReg(R3, 0x00000000) returns 0x00 (0000ms, 25946ms total) +T3170 088:409 JLINK_WriteReg(R4, 0x00000000) returns 0x00 (0000ms, 25946ms total) +T3170 088:409 JLINK_WriteReg(R5, 0x00000000) returns 0x00 (0000ms, 25946ms total) +T3170 088:409 JLINK_WriteReg(R6, 0x00000000) returns 0x00 (0000ms, 25946ms total) +T3170 088:409 JLINK_WriteReg(R7, 0x00000000) returns 0x00 (0000ms, 25946ms total) +T3170 088:409 JLINK_WriteReg(R8, 0x00000000) returns 0x00 (0000ms, 25946ms total) +T3170 088:409 JLINK_WriteReg(R9, 0x2000013C) returns 0x00 (0000ms, 25946ms total) +T3170 088:409 JLINK_WriteReg(R10, 0x00000000) returns 0x00 (0000ms, 25946ms total) +T3170 088:409 JLINK_WriteReg(R11, 0x00000000) returns 0x00 (0000ms, 25946ms total) +T3170 088:409 JLINK_WriteReg(R12, 0x00000000) returns 0x00 (0000ms, 25946ms total) +T3170 088:409 JLINK_WriteReg(R13 (SP), 0x20001000) returns 0x00 (0000ms, 25946ms total) +T3170 088:409 JLINK_WriteReg(R14, 0x20000001) returns 0x00 (0000ms, 25946ms total) +T3170 088:409 JLINK_WriteReg(R15 (PC), 0x2000005C) returns 0x00 (0000ms, 25946ms total) +T3170 088:409 JLINK_WriteReg(XPSR, 0x01000000) returns 0x00 (0000ms, 25946ms total) +T3170 088:409 JLINK_WriteReg(MSP, 0x20001000) returns 0x00 (0000ms, 25946ms total) +T3170 088:409 JLINK_WriteReg(PSP, 0x20001000) returns 0x00 (0000ms, 25946ms total) +T3170 088:409 JLINK_WriteReg(CFBP, 0x00000000) returns 0x00 (0000ms, 25946ms total) +T3170 088:409 JLINK_SetBPEx(Addr = 0x20000000, Type = 0xFFFFFFF2) returns 0x0000002E (0000ms, 25946ms total) +T3170 088:409 JLINK_Go() -- CPU_ReadMem(4 bytes @ 0xE0001000) (0056ms, 26002ms total) +T3170 088:465 JLINK_IsHalted() -- CPU_ReadMem(2 bytes @ 0x20000000) returns TRUE (0041ms, 26043ms total) +T3170 088:506 JLINK_ReadReg(R15 (PC)) returns 0x20000000 (0000ms, 26002ms total) +T3170 088:506 JLINK_ClrBPEx(BPHandle = 0x0000002E) returns 0x00 (0000ms, 26002ms total) +T3170 088:506 JLINK_ReadReg(R0) returns 0x00000000 (0000ms, 26002ms total) +T3170 088:506 JLINK_WriteMem(0x20000144, 0x0080 Bytes, ...) - Data: 69 64 5F 70 65 69 5F 68 61 6E 64 6C 65 72 00 00 ... -- CPU_WriteMem(128 bytes @ 0x20000144) returns 0x80 (0004ms, 26006ms total) +T3170 088:510 JLINK_WriteReg(R0, 0x00000F80) returns 0x00 (0000ms, 26006ms total) +T3170 088:510 JLINK_WriteReg(R1, 0x00000080) returns 0x00 (0000ms, 26006ms total) +T3170 088:510 JLINK_WriteReg(R2, 0x20000144) returns 0x00 (0000ms, 26006ms total) +T3170 088:510 JLINK_WriteReg(R3, 0x00000000) returns 0x00 (0000ms, 26006ms total) +T3170 088:510 JLINK_WriteReg(R4, 0x00000000) returns 0x00 (0000ms, 26006ms total) +T3170 088:510 JLINK_WriteReg(R5, 0x00000000) returns 0x00 (0000ms, 26006ms total) +T3170 088:510 JLINK_WriteReg(R6, 0x00000000) returns 0x00 (0000ms, 26006ms total) +T3170 088:510 JLINK_WriteReg(R7, 0x00000000) returns 0x00 (0000ms, 26006ms total) +T3170 088:510 JLINK_WriteReg(R8, 0x00000000) returns 0x00 (0000ms, 26006ms total) +T3170 088:510 JLINK_WriteReg(R9, 0x2000013C) returns 0x00 (0000ms, 26006ms total) +T3170 088:510 JLINK_WriteReg(R10, 0x00000000) returns 0x00 (0000ms, 26006ms total) +T3170 088:510 JLINK_WriteReg(R11, 0x00000000) returns 0x00 (0000ms, 26006ms total) +T3170 088:510 JLINK_WriteReg(R12, 0x00000000) returns 0x00 (0000ms, 26006ms total) +T3170 088:510 JLINK_WriteReg(R13 (SP), 0x20001000) returns 0x00 (0000ms, 26006ms total) +T3170 088:510 JLINK_WriteReg(R14, 0x20000001) returns 0x00 (0000ms, 26006ms total) +T3170 088:510 JLINK_WriteReg(R15 (PC), 0x2000005C) returns 0x00 (0000ms, 26006ms total) +T3170 088:510 JLINK_WriteReg(XPSR, 0x01000000) returns 0x00 (0000ms, 26006ms total) +T3170 088:510 JLINK_WriteReg(MSP, 0x20001000) returns 0x00 (0000ms, 26006ms total) +T3170 088:510 JLINK_WriteReg(PSP, 0x20001000) returns 0x00 (0000ms, 26006ms total) +T3170 088:510 JLINK_WriteReg(CFBP, 0x00000000) returns 0x00 (0000ms, 26006ms total) +T3170 088:510 JLINK_SetBPEx(Addr = 0x20000000, Type = 0xFFFFFFF2) returns 0x0000002F (0000ms, 26006ms total) +T3170 088:510 JLINK_Go() -- CPU_ReadMem(4 bytes @ 0xE0001000) (0089ms, 26095ms total) +T3170 088:599 JLINK_IsHalted() -- CPU_ReadMem(2 bytes @ 0x20000000) returns TRUE (0007ms, 26102ms total) +T3170 088:606 JLINK_ReadReg(R15 (PC)) returns 0x20000000 (0000ms, 26095ms total) +T3170 088:606 JLINK_ClrBPEx(BPHandle = 0x0000002F) returns 0x00 (0000ms, 26095ms total) +T3170 088:606 JLINK_ReadReg(R0) returns 0x00000000 (0000ms, 26095ms total) +T3170 088:606 JLINK_WriteMem(0x20000144, 0x0080 Bytes, ...) - Data: 6C 65 72 00 30 75 00 00 02 46 00 BF 06 4B 1B 68 ... -- CPU_WriteMem(128 bytes @ 0x20000144) returns 0x80 (0003ms, 26098ms total) +T3170 088:609 JLINK_WriteReg(R0, 0x00001000) returns 0x00 (0000ms, 26098ms total) +T3170 088:609 JLINK_WriteReg(R1, 0x00000080) returns 0x00 (0000ms, 26098ms total) +T3170 088:609 JLINK_WriteReg(R2, 0x20000144) returns 0x00 (0000ms, 26098ms total) +T3170 088:609 JLINK_WriteReg(R3, 0x00000000) returns 0x00 (0000ms, 26098ms total) +T3170 088:609 JLINK_WriteReg(R4, 0x00000000) returns 0x00 (0000ms, 26098ms total) +T3170 088:609 JLINK_WriteReg(R5, 0x00000000) returns 0x00 (0000ms, 26098ms total) +T3170 088:609 JLINK_WriteReg(R6, 0x00000000) returns 0x00 (0000ms, 26098ms total) +T3170 088:609 JLINK_WriteReg(R7, 0x00000000) returns 0x00 (0000ms, 26098ms total) +T3170 088:609 JLINK_WriteReg(R8, 0x00000000) returns 0x00 (0000ms, 26098ms total) +T3170 088:609 JLINK_WriteReg(R9, 0x2000013C) returns 0x00 (0000ms, 26098ms total) +T3170 088:609 JLINK_WriteReg(R10, 0x00000000) returns 0x00 (0000ms, 26098ms total) +T3170 088:609 JLINK_WriteReg(R11, 0x00000000) returns 0x00 (0000ms, 26098ms total) +T3170 088:609 JLINK_WriteReg(R12, 0x00000000) returns 0x00 (0000ms, 26098ms total) +T3170 088:609 JLINK_WriteReg(R13 (SP), 0x20001000) returns 0x00 (0000ms, 26098ms total) +T3170 088:609 JLINK_WriteReg(R14, 0x20000001) returns 0x00 (0000ms, 26098ms total) +T3170 088:609 JLINK_WriteReg(R15 (PC), 0x2000005C) returns 0x00 (0000ms, 26098ms total) +T3170 088:609 JLINK_WriteReg(XPSR, 0x01000000) returns 0x00 (0000ms, 26098ms total) +T3170 088:610 JLINK_WriteReg(MSP, 0x20001000) returns 0x00 (0000ms, 26099ms total) +T3170 088:610 JLINK_WriteReg(PSP, 0x20001000) returns 0x00 (0000ms, 26099ms total) +T3170 088:610 JLINK_WriteReg(CFBP, 0x00000000) returns 0x00 (0000ms, 26099ms total) +T3170 088:610 JLINK_SetBPEx(Addr = 0x20000000, Type = 0xFFFFFFF2) returns 0x00000030 (0000ms, 26099ms total) +T3170 088:610 JLINK_Go() -- CPU_ReadMem(4 bytes @ 0xE0001000) (0082ms, 26181ms total) +T3170 088:692 JLINK_IsHalted() -- CPU_ReadMem(2 bytes @ 0x20000000) returns TRUE (0012ms, 26193ms total) +T3170 088:704 JLINK_ReadReg(R15 (PC)) returns 0x20000000 (0000ms, 26181ms total) +T3170 088:704 JLINK_ClrBPEx(BPHandle = 0x00000030) returns 0x00 (0000ms, 26181ms total) +T3170 088:704 JLINK_ReadReg(R0) returns 0x00000000 (0000ms, 26181ms total) +T3170 088:704 JLINK_WriteMem(0x20000144, 0x0080 Bytes, ...) - Data: 69 62 72 61 72 69 65 73 5C 6D 73 73 5F 75 61 72 ... -- CPU_WriteMem(128 bytes @ 0x20000144) returns 0x80 (0003ms, 26184ms total) +T3170 088:707 JLINK_WriteReg(R0, 0x00001080) returns 0x00 (0000ms, 26184ms total) +T3170 088:707 JLINK_WriteReg(R1, 0x00000080) returns 0x00 (0000ms, 26184ms total) +T3170 088:707 JLINK_WriteReg(R2, 0x20000144) returns 0x00 (0000ms, 26184ms total) +T3170 088:707 JLINK_WriteReg(R3, 0x00000000) returns 0x00 (0000ms, 26184ms total) +T3170 088:707 JLINK_WriteReg(R4, 0x00000000) returns 0x00 (0000ms, 26184ms total) +T3170 088:707 JLINK_WriteReg(R5, 0x00000000) returns 0x00 (0000ms, 26184ms total) +T3170 088:707 JLINK_WriteReg(R6, 0x00000000) returns 0x00 (0000ms, 26184ms total) +T3170 088:707 JLINK_WriteReg(R7, 0x00000000) returns 0x00 (0000ms, 26184ms total) +T3170 088:707 JLINK_WriteReg(R8, 0x00000000) returns 0x00 (0000ms, 26184ms total) +T3170 088:707 JLINK_WriteReg(R9, 0x2000013C) returns 0x00 (0000ms, 26184ms total) +T3170 088:707 JLINK_WriteReg(R10, 0x00000000) returns 0x00 (0000ms, 26184ms total) +T3170 088:707 JLINK_WriteReg(R11, 0x00000000) returns 0x00 (0000ms, 26184ms total) +T3170 088:707 JLINK_WriteReg(R12, 0x00000000) returns 0x00 (0000ms, 26184ms total) +T3170 088:707 JLINK_WriteReg(R13 (SP), 0x20001000) returns 0x00 (0000ms, 26184ms total) +T3170 088:707 JLINK_WriteReg(R14, 0x20000001) returns 0x00 (0000ms, 26184ms total) +T3170 088:707 JLINK_WriteReg(R15 (PC), 0x2000005C) returns 0x00 (0000ms, 26184ms total) +T3170 088:707 JLINK_WriteReg(XPSR, 0x01000000) returns 0x00 (0000ms, 26184ms total) +T3170 088:708 JLINK_WriteReg(MSP, 0x20001000) returns 0x00 (0000ms, 26184ms total) +T3170 088:708 JLINK_WriteReg(PSP, 0x20001000) returns 0x00 (0000ms, 26184ms total) +T3170 088:708 JLINK_WriteReg(CFBP, 0x00000000) returns 0x00 (0000ms, 26184ms total) +T3170 088:708 JLINK_SetBPEx(Addr = 0x20000000, Type = 0xFFFFFFF2) returns 0x00000031 (0000ms, 26184ms total) +T3170 088:708 JLINK_Go() -- CPU_ReadMem(4 bytes @ 0xE0001000) (0006ms, 26190ms total) +T3170 088:714 JLINK_IsHalted() -- CPU_ReadMem(2 bytes @ 0x20000000) returns TRUE (0088ms, 26278ms total) +T3170 088:802 JLINK_ReadReg(R15 (PC)) returns 0x20000000 (0000ms, 26190ms total) +T3170 088:804 JLINK_ClrBPEx(BPHandle = 0x00000031) returns 0x00 (0000ms, 26190ms total) +T3170 088:804 JLINK_ReadReg(R0) returns 0x00000000 (0000ms, 26190ms total) +T3170 088:804 JLINK_WriteMem(0x20000144, 0x0080 Bytes, ...) - Data: D7 FA 10 BD 2D E9 FC 41 27 48 00 68 00 F0 80 64 ... -- CPU_WriteMem(128 bytes @ 0x20000144) returns 0x80 (0004ms, 26194ms total) +T3170 088:808 JLINK_WriteReg(R0, 0x00001100) returns 0x00 (0000ms, 26194ms total) +T3170 088:808 JLINK_WriteReg(R1, 0x00000080) returns 0x00 (0000ms, 26194ms total) +T3170 088:808 JLINK_WriteReg(R2, 0x20000144) returns 0x00 (0000ms, 26194ms total) +T3170 088:808 JLINK_WriteReg(R3, 0x00000000) returns 0x00 (0000ms, 26194ms total) +T3170 088:808 JLINK_WriteReg(R4, 0x00000000) returns 0x00 (0000ms, 26194ms total) +T3170 088:808 JLINK_WriteReg(R5, 0x00000000) returns 0x00 (0000ms, 26194ms total) +T3170 088:808 JLINK_WriteReg(R6, 0x00000000) returns 0x00 (0000ms, 26194ms total) +T3170 088:808 JLINK_WriteReg(R7, 0x00000000) returns 0x00 (0000ms, 26194ms total) +T3170 088:808 JLINK_WriteReg(R8, 0x00000000) returns 0x00 (0000ms, 26194ms total) +T3170 088:808 JLINK_WriteReg(R9, 0x2000013C) returns 0x00 (0000ms, 26194ms total) +T3170 088:808 JLINK_WriteReg(R10, 0x00000000) returns 0x00 (0000ms, 26194ms total) +T3170 088:808 JLINK_WriteReg(R11, 0x00000000) returns 0x00 (0000ms, 26194ms total) +T3170 088:808 JLINK_WriteReg(R12, 0x00000000) returns 0x00 (0000ms, 26194ms total) +T3170 088:808 JLINK_WriteReg(R13 (SP), 0x20001000) returns 0x00 (0000ms, 26194ms total) +T3170 088:808 JLINK_WriteReg(R14, 0x20000001) returns 0x00 (0000ms, 26194ms total) +T3170 088:808 JLINK_WriteReg(R15 (PC), 0x2000005C) returns 0x00 (0000ms, 26194ms total) +T3170 088:808 JLINK_WriteReg(XPSR, 0x01000000) returns 0x00 (0000ms, 26194ms total) +T3170 088:808 JLINK_WriteReg(MSP, 0x20001000) returns 0x00 (0000ms, 26194ms total) +T3170 088:808 JLINK_WriteReg(PSP, 0x20001000) returns 0x00 (0000ms, 26194ms total) +T3170 088:808 JLINK_WriteReg(CFBP, 0x00000000) returns 0x00 (0000ms, 26194ms total) +T3170 088:808 JLINK_SetBPEx(Addr = 0x20000000, Type = 0xFFFFFFF2) returns 0x00000032 (0000ms, 26194ms total) +T3170 088:808 JLINK_Go() -- CPU_ReadMem(4 bytes @ 0xE0001000) (0007ms, 26201ms total) +T3170 088:815 JLINK_IsHalted() -- CPU_ReadMem(2 bytes @ 0x20000000) returns TRUE (0092ms, 26293ms total) +T3170 088:907 JLINK_ReadReg(R15 (PC)) returns 0x20000000 (0000ms, 26201ms total) +T3170 088:907 JLINK_ClrBPEx(BPHandle = 0x00000032) returns 0x00 (0000ms, 26201ms total) +T3170 088:907 JLINK_ReadReg(R0) returns 0x00000000 (0000ms, 26201ms total) +T3170 088:907 JLINK_WriteMem(0x20000144, 0x0080 Bytes, ...) - Data: 14 48 03 F0 71 FC 04 E0 00 BF 12 48 03 F0 6C FC ... -- CPU_WriteMem(128 bytes @ 0x20000144) returns 0x80 (0004ms, 26205ms total) +T3170 088:911 JLINK_WriteReg(R0, 0x00001180) returns 0x00 (0000ms, 26205ms total) +T3170 088:911 JLINK_WriteReg(R1, 0x00000080) returns 0x00 (0000ms, 26205ms total) +T3170 088:911 JLINK_WriteReg(R2, 0x20000144) returns 0x00 (0000ms, 26205ms total) +T3170 088:911 JLINK_WriteReg(R3, 0x00000000) returns 0x00 (0000ms, 26205ms total) +T3170 088:911 JLINK_WriteReg(R4, 0x00000000) returns 0x00 (0000ms, 26205ms total) +T3170 088:911 JLINK_WriteReg(R5, 0x00000000) returns 0x00 (0000ms, 26205ms total) +T3170 088:911 JLINK_WriteReg(R6, 0x00000000) returns 0x00 (0000ms, 26205ms total) +T3170 088:911 JLINK_WriteReg(R7, 0x00000000) returns 0x00 (0000ms, 26205ms total) +T3170 088:911 JLINK_WriteReg(R8, 0x00000000) returns 0x00 (0000ms, 26205ms total) +T3170 088:911 JLINK_WriteReg(R9, 0x2000013C) returns 0x00 (0000ms, 26205ms total) +T3170 088:911 JLINK_WriteReg(R10, 0x00000000) returns 0x00 (0000ms, 26205ms total) +T3170 088:911 JLINK_WriteReg(R11, 0x00000000) returns 0x00 (0000ms, 26205ms total) +T3170 088:911 JLINK_WriteReg(R12, 0x00000000) returns 0x00 (0000ms, 26205ms total) +T3170 088:911 JLINK_WriteReg(R13 (SP), 0x20001000) returns 0x00 (0000ms, 26205ms total) +T3170 088:911 JLINK_WriteReg(R14, 0x20000001) returns 0x00 (0000ms, 26205ms total) +T3170 088:911 JLINK_WriteReg(R15 (PC), 0x2000005C) returns 0x00 (0000ms, 26205ms total) +T3170 088:911 JLINK_WriteReg(XPSR, 0x01000000) returns 0x00 (0000ms, 26205ms total) +T3170 088:911 JLINK_WriteReg(MSP, 0x20001000) returns 0x00 (0000ms, 26205ms total) +T3170 088:911 JLINK_WriteReg(PSP, 0x20001000) returns 0x00 (0000ms, 26205ms total) +T3170 088:911 JLINK_WriteReg(CFBP, 0x00000000) returns 0x00 (0000ms, 26205ms total) +T3170 088:911 JLINK_SetBPEx(Addr = 0x20000000, Type = 0xFFFFFFF2) returns 0x00000033 (0000ms, 26205ms total) +T3170 088:911 JLINK_Go() -- CPU_ReadMem(4 bytes @ 0xE0001000) (0045ms, 26250ms total) +T3170 088:956 JLINK_IsHalted() -- CPU_ReadMem(2 bytes @ 0x20000000) returns TRUE (0048ms, 26298ms total) +T3170 089:004 JLINK_ReadReg(R15 (PC)) returns 0x20000000 (0000ms, 26250ms total) +T3170 089:004 JLINK_ClrBPEx(BPHandle = 0x00000033) returns 0x00 (0000ms, 26250ms total) +T3170 089:004 JLINK_ReadReg(R0) returns 0x00000000 (0000ms, 26250ms total) +T3170 089:004 JLINK_WriteMem(0x20000144, 0x0080 Bytes, ...) - Data: F8 10 00 20 10 B5 02 48 FF F7 EA FC 10 BD 00 00 ... -- CPU_WriteMem(128 bytes @ 0x20000144) returns 0x80 (0003ms, 26253ms total) +T3170 089:007 JLINK_WriteReg(R0, 0x00001200) returns 0x00 (0000ms, 26253ms total) +T3170 089:007 JLINK_WriteReg(R1, 0x00000080) returns 0x00 (0000ms, 26253ms total) +T3170 089:007 JLINK_WriteReg(R2, 0x20000144) returns 0x00 (0000ms, 26253ms total) +T3170 089:007 JLINK_WriteReg(R3, 0x00000000) returns 0x00 (0000ms, 26253ms total) +T3170 089:007 JLINK_WriteReg(R4, 0x00000000) returns 0x00 (0000ms, 26253ms total) +T3170 089:007 JLINK_WriteReg(R5, 0x00000000) returns 0x00 (0000ms, 26253ms total) +T3170 089:007 JLINK_WriteReg(R6, 0x00000000) returns 0x00 (0000ms, 26253ms total) +T3170 089:007 JLINK_WriteReg(R7, 0x00000000) returns 0x00 (0000ms, 26253ms total) +T3170 089:007 JLINK_WriteReg(R8, 0x00000000) returns 0x00 (0000ms, 26253ms total) +T3170 089:007 JLINK_WriteReg(R9, 0x2000013C) returns 0x00 (0000ms, 26253ms total) +T3170 089:007 JLINK_WriteReg(R10, 0x00000000) returns 0x00 (0000ms, 26253ms total) +T3170 089:007 JLINK_WriteReg(R11, 0x00000000) returns 0x00 (0000ms, 26253ms total) +T3170 089:007 JLINK_WriteReg(R12, 0x00000000) returns 0x00 (0000ms, 26253ms total) +T3170 089:007 JLINK_WriteReg(R13 (SP), 0x20001000) returns 0x00 (0000ms, 26253ms total) +T3170 089:007 JLINK_WriteReg(R14, 0x20000001) returns 0x00 (0000ms, 26253ms total) +T3170 089:007 JLINK_WriteReg(R15 (PC), 0x2000005C) returns 0x00 (0000ms, 26253ms total) +T3170 089:007 JLINK_WriteReg(XPSR, 0x01000000) returns 0x00 (0000ms, 26253ms total) +T3170 089:007 JLINK_WriteReg(MSP, 0x20001000) returns 0x00 (0000ms, 26253ms total) +T3170 089:007 JLINK_WriteReg(PSP, 0x20001000) returns 0x00 (0000ms, 26253ms total) +T3170 089:007 JLINK_WriteReg(CFBP, 0x00000000) returns 0x00 (0000ms, 26253ms total) +T3170 089:007 JLINK_SetBPEx(Addr = 0x20000000, Type = 0xFFFFFFF2) returns 0x00000034 (0000ms, 26253ms total) +T3170 089:007 JLINK_Go() -- CPU_ReadMem(4 bytes @ 0xE0001000) (0007ms, 26260ms total) +T3170 089:014 JLINK_IsHalted() -- CPU_ReadMem(2 bytes @ 0x20000000) returns TRUE (0090ms, 26350ms total) +T3170 089:104 JLINK_ReadReg(R15 (PC)) returns 0x20000000 (0000ms, 26260ms total) +T3170 089:104 JLINK_ClrBPEx(BPHandle = 0x00000034) returns 0x00 (0000ms, 26260ms total) +T3170 089:104 JLINK_ReadReg(R0) returns 0x00000000 (0000ms, 26260ms total) +T3170 089:104 JLINK_WriteMem(0x20000144, 0x0080 Bytes, ...) - Data: 00 EB 11 60 00 78 19 30 DF E7 00 00 24 4D 00 00 ... -- CPU_WriteMem(128 bytes @ 0x20000144) returns 0x80 (0004ms, 26264ms total) +T3170 089:108 JLINK_WriteReg(R0, 0x00001280) returns 0x00 (0000ms, 26264ms total) +T3170 089:108 JLINK_WriteReg(R1, 0x00000080) returns 0x00 (0000ms, 26264ms total) +T3170 089:108 JLINK_WriteReg(R2, 0x20000144) returns 0x00 (0000ms, 26264ms total) +T3170 089:108 JLINK_WriteReg(R3, 0x00000000) returns 0x00 (0000ms, 26264ms total) +T3170 089:108 JLINK_WriteReg(R4, 0x00000000) returns 0x00 (0000ms, 26264ms total) +T3170 089:108 JLINK_WriteReg(R5, 0x00000000) returns 0x00 (0000ms, 26264ms total) +T3170 089:108 JLINK_WriteReg(R6, 0x00000000) returns 0x00 (0000ms, 26264ms total) +T3170 089:108 JLINK_WriteReg(R7, 0x00000000) returns 0x00 (0000ms, 26264ms total) +T3170 089:108 JLINK_WriteReg(R8, 0x00000000) returns 0x00 (0000ms, 26264ms total) +T3170 089:108 JLINK_WriteReg(R9, 0x2000013C) returns 0x00 (0000ms, 26264ms total) +T3170 089:108 JLINK_WriteReg(R10, 0x00000000) returns 0x00 (0000ms, 26264ms total) +T3170 089:108 JLINK_WriteReg(R11, 0x00000000) returns 0x00 (0000ms, 26264ms total) +T3170 089:108 JLINK_WriteReg(R12, 0x00000000) returns 0x00 (0000ms, 26264ms total) +T3170 089:108 JLINK_WriteReg(R13 (SP), 0x20001000) returns 0x00 (0000ms, 26264ms total) +T3170 089:108 JLINK_WriteReg(R14, 0x20000001) returns 0x00 (0000ms, 26264ms total) +T3170 089:108 JLINK_WriteReg(R15 (PC), 0x2000005C) returns 0x00 (0000ms, 26264ms total) +T3170 089:108 JLINK_WriteReg(XPSR, 0x01000000) returns 0x00 (0000ms, 26264ms total) +T3170 089:108 JLINK_WriteReg(MSP, 0x20001000) returns 0x00 (0000ms, 26264ms total) +T3170 089:108 JLINK_WriteReg(PSP, 0x20001000) returns 0x00 (0000ms, 26264ms total) +T3170 089:108 JLINK_WriteReg(CFBP, 0x00000000) returns 0x00 (0000ms, 26264ms total) +T3170 089:108 JLINK_SetBPEx(Addr = 0x20000000, Type = 0xFFFFFFF2) returns 0x00000035 (0000ms, 26264ms total) +T3170 089:108 JLINK_Go() -- CPU_ReadMem(4 bytes @ 0xE0001000) (0007ms, 26271ms total) +T3170 089:115 JLINK_IsHalted() -- CPU_ReadMem(2 bytes @ 0x20000000) returns TRUE (0091ms, 26362ms total) +T3170 089:206 JLINK_ReadReg(R15 (PC)) returns 0x20000000 (0000ms, 26271ms total) +T3170 089:206 JLINK_ClrBPEx(BPHandle = 0x00000035) returns 0x00 (0000ms, 26271ms total) +T3170 089:206 JLINK_ReadReg(R0) returns 0x00000000 (0000ms, 26271ms total) +T3170 089:206 JLINK_WriteMem(0x20000144, 0x0080 Bytes, ...) - Data: 5F FD 05 46 15 B9 4F F0 FF 30 F3 E7 20 21 01 A8 ... -- CPU_WriteMem(128 bytes @ 0x20000144) returns 0x80 (0003ms, 26274ms total) +T3170 089:209 JLINK_WriteReg(R0, 0x00001300) returns 0x00 (0000ms, 26274ms total) +T3170 089:209 JLINK_WriteReg(R1, 0x00000080) returns 0x00 (0000ms, 26274ms total) +T3170 089:209 JLINK_WriteReg(R2, 0x20000144) returns 0x00 (0000ms, 26274ms total) +T3170 089:209 JLINK_WriteReg(R3, 0x00000000) returns 0x00 (0000ms, 26274ms total) +T3170 089:209 JLINK_WriteReg(R4, 0x00000000) returns 0x00 (0000ms, 26274ms total) +T3170 089:209 JLINK_WriteReg(R5, 0x00000000) returns 0x00 (0000ms, 26274ms total) +T3170 089:209 JLINK_WriteReg(R6, 0x00000000) returns 0x00 (0000ms, 26274ms total) +T3170 089:209 JLINK_WriteReg(R7, 0x00000000) returns 0x00 (0000ms, 26274ms total) +T3170 089:209 JLINK_WriteReg(R8, 0x00000000) returns 0x00 (0000ms, 26274ms total) +T3170 089:209 JLINK_WriteReg(R9, 0x2000013C) returns 0x00 (0000ms, 26274ms total) +T3170 089:209 JLINK_WriteReg(R10, 0x00000000) returns 0x00 (0000ms, 26274ms total) +T3170 089:209 JLINK_WriteReg(R11, 0x00000000) returns 0x00 (0000ms, 26274ms total) +T3170 089:209 JLINK_WriteReg(R12, 0x00000000) returns 0x00 (0000ms, 26274ms total) +T3170 089:209 JLINK_WriteReg(R13 (SP), 0x20001000) returns 0x00 (0000ms, 26274ms total) +T3170 089:209 JLINK_WriteReg(R14, 0x20000001) returns 0x00 (0000ms, 26274ms total) +T3170 089:209 JLINK_WriteReg(R15 (PC), 0x2000005C) returns 0x00 (0000ms, 26274ms total) +T3170 089:209 JLINK_WriteReg(XPSR, 0x01000000) returns 0x00 (0000ms, 26274ms total) +T3170 089:209 JLINK_WriteReg(MSP, 0x20001000) returns 0x00 (0000ms, 26274ms total) +T3170 089:209 JLINK_WriteReg(PSP, 0x20001000) returns 0x00 (0000ms, 26274ms total) +T3170 089:209 JLINK_WriteReg(CFBP, 0x00000000) returns 0x00 (0000ms, 26274ms total) +T3170 089:209 JLINK_SetBPEx(Addr = 0x20000000, Type = 0xFFFFFFF2) returns 0x00000036 (0000ms, 26274ms total) +T3170 089:209 JLINK_Go() -- CPU_ReadMem(4 bytes @ 0xE0001000) (0008ms, 26282ms total) +T3170 089:217 JLINK_IsHalted() -- CPU_ReadMem(2 bytes @ 0x20000000) returns TRUE (0086ms, 26368ms total) +T3170 089:303 JLINK_ReadReg(R15 (PC)) returns 0x20000000 (0000ms, 26282ms total) +T3170 089:303 JLINK_ClrBPEx(BPHandle = 0x00000036) returns 0x00 (0000ms, 26282ms total) +T3170 089:303 JLINK_ReadReg(R0) returns 0x00000000 (0000ms, 26282ms total) +T3170 089:303 JLINK_WriteMem(0x20000144, 0x0080 Bytes, ...) - Data: 20 60 A7 76 67 76 00 20 E0 61 C4 F8 28 80 C4 F8 ... -- CPU_WriteMem(128 bytes @ 0x20000144) returns 0x80 (0003ms, 26285ms total) +T3170 089:307 JLINK_WriteReg(R0, 0x00001380) returns 0x00 (0000ms, 26286ms total) +T3170 089:307 JLINK_WriteReg(R1, 0x00000080) returns 0x00 (0000ms, 26286ms total) +T3170 089:307 JLINK_WriteReg(R2, 0x20000144) returns 0x00 (0000ms, 26286ms total) +T3170 089:307 JLINK_WriteReg(R3, 0x00000000) returns 0x00 (0000ms, 26286ms total) +T3170 089:307 JLINK_WriteReg(R4, 0x00000000) returns 0x00 (0000ms, 26286ms total) +T3170 089:307 JLINK_WriteReg(R5, 0x00000000) returns 0x00 (0000ms, 26286ms total) +T3170 089:307 JLINK_WriteReg(R6, 0x00000000) returns 0x00 (0000ms, 26286ms total) +T3170 089:307 JLINK_WriteReg(R7, 0x00000000) returns 0x00 (0000ms, 26286ms total) +T3170 089:307 JLINK_WriteReg(R8, 0x00000000) returns 0x00 (0000ms, 26286ms total) +T3170 089:307 JLINK_WriteReg(R9, 0x2000013C) returns 0x00 (0000ms, 26286ms total) +T3170 089:307 JLINK_WriteReg(R10, 0x00000000) returns 0x00 (0000ms, 26286ms total) +T3170 089:307 JLINK_WriteReg(R11, 0x00000000) returns 0x00 (0000ms, 26286ms total) +T3170 089:307 JLINK_WriteReg(R12, 0x00000000) returns 0x00 (0000ms, 26286ms total) +T3170 089:307 JLINK_WriteReg(R13 (SP), 0x20001000) returns 0x00 (0000ms, 26286ms total) +T3170 089:307 JLINK_WriteReg(R14, 0x20000001) returns 0x00 (0000ms, 26286ms total) +T3170 089:307 JLINK_WriteReg(R15 (PC), 0x2000005C) returns 0x00 (0000ms, 26286ms total) +T3170 089:307 JLINK_WriteReg(XPSR, 0x01000000) returns 0x00 (0000ms, 26286ms total) +T3170 089:307 JLINK_WriteReg(MSP, 0x20001000) returns 0x00 (0000ms, 26286ms total) +T3170 089:307 JLINK_WriteReg(PSP, 0x20001000) returns 0x00 (0000ms, 26286ms total) +T3170 089:307 JLINK_WriteReg(CFBP, 0x00000000) returns 0x00 (0000ms, 26286ms total) +T3170 089:307 JLINK_SetBPEx(Addr = 0x20000000, Type = 0xFFFFFFF2) returns 0x00000037 (0000ms, 26286ms total) +T3170 089:307 JLINK_Go() -- CPU_ReadMem(4 bytes @ 0xE0001000) (0006ms, 26292ms total) +T3170 089:313 JLINK_IsHalted() -- CPU_ReadMem(2 bytes @ 0x20000000) returns TRUE (0091ms, 26383ms total) +T3170 089:404 JLINK_ReadReg(R15 (PC)) returns 0x20000000 (0000ms, 26292ms total) +T3170 089:404 JLINK_ClrBPEx(BPHandle = 0x00000037) returns 0x00 (0000ms, 26292ms total) +T3170 089:404 JLINK_ReadReg(R0) returns 0x00000000 (0000ms, 26292ms total) +T3170 089:404 JLINK_WriteMem(0x20000144, 0x0080 Bytes, ...) - Data: 02 46 00 20 01 46 0E E0 02 F1 14 03 03 EB C1 00 ... -- CPU_WriteMem(128 bytes @ 0x20000144) returns 0x80 (0004ms, 26296ms total) +T3170 089:408 JLINK_WriteReg(R0, 0x00001400) returns 0x00 (0000ms, 26296ms total) +T3170 089:408 JLINK_WriteReg(R1, 0x00000080) returns 0x00 (0000ms, 26296ms total) +T3170 089:408 JLINK_WriteReg(R2, 0x20000144) returns 0x00 (0000ms, 26296ms total) +T3170 089:408 JLINK_WriteReg(R3, 0x00000000) returns 0x00 (0000ms, 26296ms total) +T3170 089:408 JLINK_WriteReg(R4, 0x00000000) returns 0x00 (0000ms, 26296ms total) +T3170 089:408 JLINK_WriteReg(R5, 0x00000000) returns 0x00 (0000ms, 26296ms total) +T3170 089:408 JLINK_WriteReg(R6, 0x00000000) returns 0x00 (0000ms, 26296ms total) +T3170 089:408 JLINK_WriteReg(R7, 0x00000000) returns 0x00 (0000ms, 26296ms total) +T3170 089:408 JLINK_WriteReg(R8, 0x00000000) returns 0x00 (0000ms, 26296ms total) +T3170 089:408 JLINK_WriteReg(R9, 0x2000013C) returns 0x00 (0000ms, 26296ms total) +T3170 089:408 JLINK_WriteReg(R10, 0x00000000) returns 0x00 (0000ms, 26296ms total) +T3170 089:408 JLINK_WriteReg(R11, 0x00000000) returns 0x00 (0000ms, 26296ms total) +T3170 089:408 JLINK_WriteReg(R12, 0x00000000) returns 0x00 (0000ms, 26296ms total) +T3170 089:408 JLINK_WriteReg(R13 (SP), 0x20001000) returns 0x00 (0000ms, 26296ms total) +T3170 089:408 JLINK_WriteReg(R14, 0x20000001) returns 0x00 (0000ms, 26296ms total) +T3170 089:408 JLINK_WriteReg(R15 (PC), 0x2000005C) returns 0x00 (0000ms, 26296ms total) +T3170 089:408 JLINK_WriteReg(XPSR, 0x01000000) returns 0x00 (0000ms, 26296ms total) +T3170 089:408 JLINK_WriteReg(MSP, 0x20001000) returns 0x00 (0000ms, 26296ms total) +T3170 089:408 JLINK_WriteReg(PSP, 0x20001000) returns 0x00 (0000ms, 26296ms total) +T3170 089:408 JLINK_WriteReg(CFBP, 0x00000000) returns 0x00 (0000ms, 26296ms total) +T3170 089:408 JLINK_SetBPEx(Addr = 0x20000000, Type = 0xFFFFFFF2) returns 0x00000038 (0000ms, 26296ms total) +T3170 089:408 JLINK_Go() -- CPU_ReadMem(4 bytes @ 0xE0001000) (0041ms, 26337ms total) +T3170 089:449 JLINK_IsHalted() -- CPU_ReadMem(2 bytes @ 0x20000000) returns TRUE (0057ms, 26394ms total) +T3170 089:506 JLINK_ReadReg(R15 (PC)) returns 0x20000000 (0000ms, 26337ms total) +T3170 089:506 JLINK_ClrBPEx(BPHandle = 0x00000038) returns 0x00 (0000ms, 26337ms total) +T3170 089:506 JLINK_ReadReg(R0) returns 0x00000000 (0000ms, 26337ms total) +T3170 089:506 JLINK_WriteMem(0x20000144, 0x0080 Bytes, ...) - Data: 02 00 10 B1 22 A0 02 F0 6B F9 17 48 00 78 00 F0 ... -- CPU_WriteMem(128 bytes @ 0x20000144) returns 0x80 (0004ms, 26341ms total) +T3170 089:510 JLINK_WriteReg(R0, 0x00001480) returns 0x00 (0000ms, 26341ms total) +T3170 089:510 JLINK_WriteReg(R1, 0x00000080) returns 0x00 (0000ms, 26341ms total) +T3170 089:510 JLINK_WriteReg(R2, 0x20000144) returns 0x00 (0000ms, 26341ms total) +T3170 089:510 JLINK_WriteReg(R3, 0x00000000) returns 0x00 (0000ms, 26341ms total) +T3170 089:510 JLINK_WriteReg(R4, 0x00000000) returns 0x00 (0000ms, 26341ms total) +T3170 089:510 JLINK_WriteReg(R5, 0x00000000) returns 0x00 (0000ms, 26341ms total) +T3170 089:510 JLINK_WriteReg(R6, 0x00000000) returns 0x00 (0000ms, 26341ms total) +T3170 089:510 JLINK_WriteReg(R7, 0x00000000) returns 0x00 (0000ms, 26341ms total) +T3170 089:510 JLINK_WriteReg(R8, 0x00000000) returns 0x00 (0000ms, 26341ms total) +T3170 089:510 JLINK_WriteReg(R9, 0x2000013C) returns 0x00 (0000ms, 26341ms total) +T3170 089:510 JLINK_WriteReg(R10, 0x00000000) returns 0x00 (0000ms, 26341ms total) +T3170 089:510 JLINK_WriteReg(R11, 0x00000000) returns 0x00 (0000ms, 26341ms total) +T3170 089:510 JLINK_WriteReg(R12, 0x00000000) returns 0x00 (0000ms, 26341ms total) +T3170 089:510 JLINK_WriteReg(R13 (SP), 0x20001000) returns 0x00 (0000ms, 26341ms total) +T3170 089:510 JLINK_WriteReg(R14, 0x20000001) returns 0x00 (0000ms, 26341ms total) +T3170 089:510 JLINK_WriteReg(R15 (PC), 0x2000005C) returns 0x00 (0000ms, 26341ms total) +T3170 089:510 JLINK_WriteReg(XPSR, 0x01000000) returns 0x00 (0000ms, 26341ms total) +T3170 089:510 JLINK_WriteReg(MSP, 0x20001000) returns 0x00 (0000ms, 26341ms total) +T3170 089:510 JLINK_WriteReg(PSP, 0x20001000) returns 0x00 (0000ms, 26341ms total) +T3170 089:510 JLINK_WriteReg(CFBP, 0x00000000) returns 0x00 (0000ms, 26341ms total) +T3170 089:510 JLINK_SetBPEx(Addr = 0x20000000, Type = 0xFFFFFFF2) returns 0x00000039 (0000ms, 26341ms total) +T3170 089:510 JLINK_Go() -- CPU_ReadMem(4 bytes @ 0xE0001000) (0089ms, 26430ms total) +T3170 089:599 JLINK_IsHalted() -- CPU_ReadMem(2 bytes @ 0x20000000) returns TRUE (0009ms, 26439ms total) +T3170 089:608 JLINK_ReadReg(R15 (PC)) returns 0x20000000 (0000ms, 26430ms total) +T3170 089:608 JLINK_ClrBPEx(BPHandle = 0x00000039) returns 0x00 (0000ms, 26430ms total) +T3170 089:608 JLINK_ReadReg(R0) returns 0x00000000 (0000ms, 26430ms total) +T3170 089:608 JLINK_WriteMem(0x20000144, 0x0080 Bytes, ...) - Data: 20 00 00 00 49 42 55 53 45 52 52 20 00 00 00 00 ... -- CPU_WriteMem(128 bytes @ 0x20000144) returns 0x80 (0004ms, 26434ms total) +T3170 089:612 JLINK_WriteReg(R0, 0x00001500) returns 0x00 (0000ms, 26434ms total) +T3170 089:612 JLINK_WriteReg(R1, 0x00000080) returns 0x00 (0000ms, 26434ms total) +T3170 089:612 JLINK_WriteReg(R2, 0x20000144) returns 0x00 (0000ms, 26434ms total) +T3170 089:612 JLINK_WriteReg(R3, 0x00000000) returns 0x00 (0000ms, 26434ms total) +T3170 089:612 JLINK_WriteReg(R4, 0x00000000) returns 0x00 (0000ms, 26434ms total) +T3170 089:612 JLINK_WriteReg(R5, 0x00000000) returns 0x00 (0000ms, 26434ms total) +T3170 089:612 JLINK_WriteReg(R6, 0x00000000) returns 0x00 (0000ms, 26434ms total) +T3170 089:612 JLINK_WriteReg(R7, 0x00000000) returns 0x00 (0000ms, 26434ms total) +T3170 089:612 JLINK_WriteReg(R8, 0x00000000) returns 0x00 (0000ms, 26434ms total) +T3170 089:612 JLINK_WriteReg(R9, 0x2000013C) returns 0x00 (0000ms, 26434ms total) +T3170 089:612 JLINK_WriteReg(R10, 0x00000000) returns 0x00 (0000ms, 26434ms total) +T3170 089:612 JLINK_WriteReg(R11, 0x00000000) returns 0x00 (0000ms, 26434ms total) +T3170 089:612 JLINK_WriteReg(R12, 0x00000000) returns 0x00 (0000ms, 26434ms total) +T3170 089:612 JLINK_WriteReg(R13 (SP), 0x20001000) returns 0x00 (0000ms, 26434ms total) +T3170 089:612 JLINK_WriteReg(R14, 0x20000001) returns 0x00 (0000ms, 26434ms total) +T3170 089:612 JLINK_WriteReg(R15 (PC), 0x2000005C) returns 0x00 (0000ms, 26434ms total) +T3170 089:612 JLINK_WriteReg(XPSR, 0x01000000) returns 0x00 (0000ms, 26434ms total) +T3170 089:612 JLINK_WriteReg(MSP, 0x20001000) returns 0x00 (0000ms, 26434ms total) +T3170 089:612 JLINK_WriteReg(PSP, 0x20001000) returns 0x00 (0000ms, 26434ms total) +T3170 089:612 JLINK_WriteReg(CFBP, 0x00000000) returns 0x00 (0000ms, 26434ms total) +T3170 089:612 JLINK_SetBPEx(Addr = 0x20000000, Type = 0xFFFFFFF2) returns 0x0000003A (0000ms, 26434ms total) +T3170 089:612 JLINK_Go() -- CPU_ReadMem(4 bytes @ 0xE0001000) (0087ms, 26521ms total) +T3170 089:700 JLINK_IsHalted() -- CPU_ReadMem(2 bytes @ 0x20000000) returns TRUE (0007ms, 26528ms total) +T3170 089:707 JLINK_ReadReg(R15 (PC)) returns 0x20000000 (0000ms, 26521ms total) +T3170 089:707 JLINK_ClrBPEx(BPHandle = 0x0000003A) returns 0x00 (0000ms, 26521ms total) +T3170 089:707 JLINK_ReadReg(R0) returns 0x00000000 (0001ms, 26522ms total) +T3170 089:708 JLINK_WriteMem(0x20000144, 0x0080 Bytes, ...) - Data: 10 BD 70 B5 04 46 0D 46 00 F0 44 FF 00 20 70 BD ... -- CPU_WriteMem(128 bytes @ 0x20000144) returns 0x80 (0003ms, 26525ms total) +T3170 089:711 JLINK_WriteReg(R0, 0x00001580) returns 0x00 (0001ms, 26526ms total) +T3170 089:712 JLINK_WriteReg(R1, 0x00000080) returns 0x00 (0000ms, 26526ms total) +T3170 089:712 JLINK_WriteReg(R2, 0x20000144) returns 0x00 (0000ms, 26526ms total) +T3170 089:712 JLINK_WriteReg(R3, 0x00000000) returns 0x00 (0000ms, 26526ms total) +T3170 089:712 JLINK_WriteReg(R4, 0x00000000) returns 0x00 (0000ms, 26526ms total) +T3170 089:712 JLINK_WriteReg(R5, 0x00000000) returns 0x00 (0000ms, 26526ms total) +T3170 089:712 JLINK_WriteReg(R6, 0x00000000) returns 0x00 (0000ms, 26526ms total) +T3170 089:712 JLINK_WriteReg(R7, 0x00000000) returns 0x00 (0000ms, 26526ms total) +T3170 089:712 JLINK_WriteReg(R8, 0x00000000) returns 0x00 (0000ms, 26526ms total) +T3170 089:712 JLINK_WriteReg(R9, 0x2000013C) returns 0x00 (0000ms, 26526ms total) +T3170 089:712 JLINK_WriteReg(R10, 0x00000000) returns 0x00 (0000ms, 26526ms total) +T3170 089:712 JLINK_WriteReg(R11, 0x00000000) returns 0x00 (0000ms, 26526ms total) +T3170 089:712 JLINK_WriteReg(R12, 0x00000000) returns 0x00 (0000ms, 26526ms total) +T3170 089:712 JLINK_WriteReg(R13 (SP), 0x20001000) returns 0x00 (0000ms, 26526ms total) +T3170 089:712 JLINK_WriteReg(R14, 0x20000001) returns 0x00 (0000ms, 26526ms total) +T3170 089:712 JLINK_WriteReg(R15 (PC), 0x2000005C) returns 0x00 (0000ms, 26526ms total) +T3170 089:712 JLINK_WriteReg(XPSR, 0x01000000) returns 0x00 (0000ms, 26526ms total) +T3170 089:712 JLINK_WriteReg(MSP, 0x20001000) returns 0x00 (0000ms, 26526ms total) +T3170 089:712 JLINK_WriteReg(PSP, 0x20001000) returns 0x00 (0000ms, 26526ms total) +T3170 089:712 JLINK_WriteReg(CFBP, 0x00000000) returns 0x00 (0000ms, 26526ms total) +T3170 089:712 JLINK_SetBPEx(Addr = 0x20000000, Type = 0xFFFFFFF2) returns 0x0000003B (0000ms, 26526ms total) +T3170 089:712 JLINK_Go() -- CPU_ReadMem(4 bytes @ 0xE0001000) (0087ms, 26613ms total) +T3170 089:799 JLINK_IsHalted() -- CPU_ReadMem(2 bytes @ 0x20000000) returns TRUE (0006ms, 26619ms total) +T3170 089:805 JLINK_ReadReg(R15 (PC)) returns 0x20000000 (0000ms, 26613ms total) +T3170 089:805 JLINK_ClrBPEx(BPHandle = 0x0000003B) returns 0x00 (0000ms, 26613ms total) +T3170 089:805 JLINK_ReadReg(R0) returns 0x00000000 (0000ms, 26613ms total) +T3170 089:805 JLINK_WriteMem(0x20000144, 0x0080 Bytes, ...) - Data: A0 EB 46 00 06 44 B5 F5 80 3F 00 D2 05 E0 40 F2 ... -- CPU_WriteMem(128 bytes @ 0x20000144) returns 0x80 (0003ms, 26616ms total) +T3170 089:808 JLINK_WriteReg(R0, 0x00001600) returns 0x00 (0000ms, 26616ms total) +T3170 089:808 JLINK_WriteReg(R1, 0x00000080) returns 0x00 (0000ms, 26616ms total) +T3170 089:808 JLINK_WriteReg(R2, 0x20000144) returns 0x00 (0000ms, 26616ms total) +T3170 089:808 JLINK_WriteReg(R3, 0x00000000) returns 0x00 (0000ms, 26616ms total) +T3170 089:808 JLINK_WriteReg(R4, 0x00000000) returns 0x00 (0000ms, 26616ms total) +T3170 089:808 JLINK_WriteReg(R5, 0x00000000) returns 0x00 (0000ms, 26616ms total) +T3170 089:808 JLINK_WriteReg(R6, 0x00000000) returns 0x00 (0000ms, 26616ms total) +T3170 089:808 JLINK_WriteReg(R7, 0x00000000) returns 0x00 (0000ms, 26616ms total) +T3170 089:808 JLINK_WriteReg(R8, 0x00000000) returns 0x00 (0000ms, 26616ms total) +T3170 089:808 JLINK_WriteReg(R9, 0x2000013C) returns 0x00 (0000ms, 26616ms total) +T3170 089:808 JLINK_WriteReg(R10, 0x00000000) returns 0x00 (0000ms, 26616ms total) +T3170 089:808 JLINK_WriteReg(R11, 0x00000000) returns 0x00 (0000ms, 26616ms total) +T3170 089:808 JLINK_WriteReg(R12, 0x00000000) returns 0x00 (0000ms, 26616ms total) +T3170 089:808 JLINK_WriteReg(R13 (SP), 0x20001000) returns 0x00 (0000ms, 26616ms total) +T3170 089:808 JLINK_WriteReg(R14, 0x20000001) returns 0x00 (0000ms, 26616ms total) +T3170 089:808 JLINK_WriteReg(R15 (PC), 0x2000005C) returns 0x00 (0000ms, 26616ms total) +T3170 089:808 JLINK_WriteReg(XPSR, 0x01000000) returns 0x00 (0000ms, 26616ms total) +T3170 089:808 JLINK_WriteReg(MSP, 0x20001000) returns 0x00 (0000ms, 26616ms total) +T3170 089:808 JLINK_WriteReg(PSP, 0x20001000) returns 0x00 (0000ms, 26616ms total) +T3170 089:808 JLINK_WriteReg(CFBP, 0x00000000) returns 0x00 (0000ms, 26616ms total) +T3170 089:808 JLINK_SetBPEx(Addr = 0x20000000, Type = 0xFFFFFFF2) returns 0x0000003C (0000ms, 26616ms total) +T3170 089:808 JLINK_Go() -- CPU_ReadMem(4 bytes @ 0xE0001000) (0007ms, 26623ms total) +T3170 089:815 JLINK_IsHalted() -- CPU_ReadMem(2 bytes @ 0x20000000) returns TRUE (0091ms, 26714ms total) +T3170 089:906 JLINK_ReadReg(R15 (PC)) returns 0x20000000 (0000ms, 26623ms total) +T3170 089:906 JLINK_ClrBPEx(BPHandle = 0x0000003C) returns 0x00 (0000ms, 26623ms total) +T3170 089:906 JLINK_ReadReg(R0) returns 0x00000000 (0000ms, 26623ms total) +T3170 089:907 JLINK_WriteMem(0x20000144, 0x0080 Bytes, ...) - Data: 0D 70 21 68 01 F1 0C 00 07 21 FF F7 6D FF 21 68 ... -- CPU_WriteMem(128 bytes @ 0x20000144) returns 0x80 (0003ms, 26627ms total) +T3170 089:910 JLINK_WriteReg(R0, 0x00001680) returns 0x00 (0000ms, 26627ms total) +T3170 089:910 JLINK_WriteReg(R1, 0x00000080) returns 0x00 (0000ms, 26627ms total) +T3170 089:910 JLINK_WriteReg(R2, 0x20000144) returns 0x00 (0000ms, 26627ms total) +T3170 089:910 JLINK_WriteReg(R3, 0x00000000) returns 0x00 (0000ms, 26627ms total) +T3170 089:910 JLINK_WriteReg(R4, 0x00000000) returns 0x00 (0000ms, 26627ms total) +T3170 089:910 JLINK_WriteReg(R5, 0x00000000) returns 0x00 (0000ms, 26627ms total) +T3170 089:910 JLINK_WriteReg(R6, 0x00000000) returns 0x00 (0000ms, 26627ms total) +T3170 089:910 JLINK_WriteReg(R7, 0x00000000) returns 0x00 (0000ms, 26627ms total) +T3170 089:910 JLINK_WriteReg(R8, 0x00000000) returns 0x00 (0000ms, 26627ms total) +T3170 089:910 JLINK_WriteReg(R9, 0x2000013C) returns 0x00 (0000ms, 26627ms total) +T3170 089:910 JLINK_WriteReg(R10, 0x00000000) returns 0x00 (0001ms, 26628ms total) +T3170 089:911 JLINK_WriteReg(R11, 0x00000000) returns 0x00 (0000ms, 26628ms total) +T3170 089:911 JLINK_WriteReg(R12, 0x00000000) returns 0x00 (0000ms, 26628ms total) +T3170 089:911 JLINK_WriteReg(R13 (SP), 0x20001000) returns 0x00 (0000ms, 26628ms total) +T3170 089:911 JLINK_WriteReg(R14, 0x20000001) returns 0x00 (0000ms, 26628ms total) +T3170 089:911 JLINK_WriteReg(R15 (PC), 0x2000005C) returns 0x00 (0000ms, 26628ms total) +T3170 089:911 JLINK_WriteReg(XPSR, 0x01000000) returns 0x00 (0000ms, 26628ms total) +T3170 089:911 JLINK_WriteReg(MSP, 0x20001000) returns 0x00 (0000ms, 26628ms total) +T3170 089:911 JLINK_WriteReg(PSP, 0x20001000) returns 0x00 (0000ms, 26628ms total) +T3170 089:911 JLINK_WriteReg(CFBP, 0x00000000) returns 0x00 (0000ms, 26628ms total) +T3170 089:911 JLINK_SetBPEx(Addr = 0x20000000, Type = 0xFFFFFFF2) returns 0x0000003D (0000ms, 26628ms total) +T3170 089:911 JLINK_Go() -- CPU_ReadMem(4 bytes @ 0xE0001000) (0018ms, 26646ms total) +T3170 089:929 JLINK_IsHalted() -- CPU_ReadMem(2 bytes @ 0x20000000) returns TRUE (0077ms, 26723ms total) +T3170 090:006 JLINK_ReadReg(R15 (PC)) returns 0x20000000 (0000ms, 26646ms total) +T3170 090:009 JLINK_ClrBPEx(BPHandle = 0x0000003D) returns 0x00 (0000ms, 26646ms total) +T3170 090:009 JLINK_ReadReg(R0) returns 0x00000000 (0000ms, 26646ms total) +T3170 090:009 JLINK_WriteMem(0x20000144, 0x0080 Bytes, ...) - Data: 75 61 72 74 31 29 00 00 04 00 00 20 08 00 00 20 ... -- CPU_WriteMem(128 bytes @ 0x20000144) returns 0x80 (0004ms, 26650ms total) +T3170 090:013 JLINK_WriteReg(R0, 0x00001700) returns 0x00 (0000ms, 26650ms total) +T3170 090:013 JLINK_WriteReg(R1, 0x00000080) returns 0x00 (0000ms, 26650ms total) +T3170 090:013 JLINK_WriteReg(R2, 0x20000144) returns 0x00 (0000ms, 26650ms total) +T3170 090:013 JLINK_WriteReg(R3, 0x00000000) returns 0x00 (0000ms, 26650ms total) +T3170 090:013 JLINK_WriteReg(R4, 0x00000000) returns 0x00 (0000ms, 26650ms total) +T3170 090:013 JLINK_WriteReg(R5, 0x00000000) returns 0x00 (0000ms, 26650ms total) +T3170 090:013 JLINK_WriteReg(R6, 0x00000000) returns 0x00 (0000ms, 26650ms total) +T3170 090:013 JLINK_WriteReg(R7, 0x00000000) returns 0x00 (0000ms, 26650ms total) +T3170 090:013 JLINK_WriteReg(R8, 0x00000000) returns 0x00 (0000ms, 26650ms total) +T3170 090:013 JLINK_WriteReg(R9, 0x2000013C) returns 0x00 (0000ms, 26650ms total) +T3170 090:013 JLINK_WriteReg(R10, 0x00000000) returns 0x00 (0000ms, 26650ms total) +T3170 090:013 JLINK_WriteReg(R11, 0x00000000) returns 0x00 (0000ms, 26650ms total) +T3170 090:013 JLINK_WriteReg(R12, 0x00000000) returns 0x00 (0000ms, 26650ms total) +T3170 090:013 JLINK_WriteReg(R13 (SP), 0x20001000) returns 0x00 (0000ms, 26650ms total) +T3170 090:013 JLINK_WriteReg(R14, 0x20000001) returns 0x00 (0000ms, 26650ms total) +T3170 090:013 JLINK_WriteReg(R15 (PC), 0x2000005C) returns 0x00 (0000ms, 26650ms total) +T3170 090:013 JLINK_WriteReg(XPSR, 0x01000000) returns 0x00 (0000ms, 26650ms total) +T3170 090:013 JLINK_WriteReg(MSP, 0x20001000) returns 0x00 (0000ms, 26650ms total) +T3170 090:013 JLINK_WriteReg(PSP, 0x20001000) returns 0x00 (0000ms, 26650ms total) +T3170 090:013 JLINK_WriteReg(CFBP, 0x00000000) returns 0x00 (0000ms, 26650ms total) +T3170 090:013 JLINK_SetBPEx(Addr = 0x20000000, Type = 0xFFFFFFF2) returns 0x0000003E (0000ms, 26650ms total) +T3170 090:013 JLINK_Go() -- CPU_ReadMem(4 bytes @ 0xE0001000) (0090ms, 26740ms total) +T3170 090:103 JLINK_IsHalted() -- CPU_ReadMem(2 bytes @ 0x20000000) returns TRUE (0007ms, 26747ms total) +T3170 090:110 JLINK_ReadReg(R15 (PC)) returns 0x20000000 (0000ms, 26740ms total) +T3170 090:110 JLINK_ClrBPEx(BPHandle = 0x0000003E) returns 0x00 (0000ms, 26740ms total) +T3170 090:110 JLINK_ReadReg(R0) returns 0x00000000 (0000ms, 26740ms total) +T3170 090:110 JLINK_WriteMem(0x20000144, 0x0080 Bytes, ...) - Data: 00 D9 05 E0 40 F2 B3 62 1D A1 40 A0 FE F7 66 FE ... -- CPU_WriteMem(128 bytes @ 0x20000144) returns 0x80 (0003ms, 26743ms total) +T3170 090:114 JLINK_WriteReg(R0, 0x00001780) returns 0x00 (0000ms, 26743ms total) +T3170 090:114 JLINK_WriteReg(R1, 0x00000080) returns 0x00 (0000ms, 26743ms total) +T3170 090:114 JLINK_WriteReg(R2, 0x20000144) returns 0x00 (0000ms, 26743ms total) +T3170 090:114 JLINK_WriteReg(R3, 0x00000000) returns 0x00 (0000ms, 26743ms total) +T3170 090:114 JLINK_WriteReg(R4, 0x00000000) returns 0x00 (0000ms, 26743ms total) +T3170 090:114 JLINK_WriteReg(R5, 0x00000000) returns 0x00 (0000ms, 26743ms total) +T3170 090:114 JLINK_WriteReg(R6, 0x00000000) returns 0x00 (0000ms, 26743ms total) +T3170 090:114 JLINK_WriteReg(R7, 0x00000000) returns 0x00 (0000ms, 26743ms total) +T3170 090:114 JLINK_WriteReg(R8, 0x00000000) returns 0x00 (0000ms, 26743ms total) +T3170 090:114 JLINK_WriteReg(R9, 0x2000013C) returns 0x00 (0000ms, 26743ms total) +T3170 090:114 JLINK_WriteReg(R10, 0x00000000) returns 0x00 (0000ms, 26743ms total) +T3170 090:114 JLINK_WriteReg(R11, 0x00000000) returns 0x00 (0000ms, 26743ms total) +T3170 090:114 JLINK_WriteReg(R12, 0x00000000) returns 0x00 (0000ms, 26743ms total) +T3170 090:114 JLINK_WriteReg(R13 (SP), 0x20001000) returns 0x00 (0000ms, 26743ms total) +T3170 090:114 JLINK_WriteReg(R14, 0x20000001) returns 0x00 (0000ms, 26743ms total) +T3170 090:114 JLINK_WriteReg(R15 (PC), 0x2000005C) returns 0x00 (0000ms, 26743ms total) +T3170 090:114 JLINK_WriteReg(XPSR, 0x01000000) returns 0x00 (0000ms, 26743ms total) +T3170 090:114 JLINK_WriteReg(MSP, 0x20001000) returns 0x00 (0000ms, 26743ms total) +T3170 090:114 JLINK_WriteReg(PSP, 0x20001000) returns 0x00 (0000ms, 26743ms total) +T3170 090:114 JLINK_WriteReg(CFBP, 0x00000000) returns 0x00 (0000ms, 26743ms total) +T3170 090:114 JLINK_SetBPEx(Addr = 0x20000000, Type = 0xFFFFFFF2) returns 0x0000003F (0000ms, 26743ms total) +T3170 090:114 JLINK_Go() -- CPU_ReadMem(4 bytes @ 0xE0001000) (0088ms, 26831ms total) +T3170 090:202 JLINK_IsHalted() -- CPU_ReadMem(2 bytes @ 0x20000000) returns TRUE (0008ms, 26839ms total) +T3170 090:210 JLINK_ReadReg(R15 (PC)) returns 0x20000000 (0000ms, 26831ms total) +T3170 090:210 JLINK_ClrBPEx(BPHandle = 0x0000003F) returns 0x00 (0000ms, 26831ms total) +T3170 090:210 JLINK_ReadReg(R0) returns 0x00000000 (0000ms, 26831ms total) +T3170 090:210 JLINK_WriteMem(0x20000144, 0x0080 Bytes, ...) - Data: 2E 2E 5C 6C 69 62 72 61 72 69 65 73 5C 6D 73 73 ... -- CPU_WriteMem(128 bytes @ 0x20000144) returns 0x80 (0004ms, 26835ms total) +T3170 090:214 JLINK_WriteReg(R0, 0x00001800) returns 0x00 (0000ms, 26835ms total) +T3170 090:214 JLINK_WriteReg(R1, 0x00000080) returns 0x00 (0000ms, 26835ms total) +T3170 090:214 JLINK_WriteReg(R2, 0x20000144) returns 0x00 (0000ms, 26835ms total) +T3170 090:214 JLINK_WriteReg(R3, 0x00000000) returns 0x00 (0000ms, 26835ms total) +T3170 090:214 JLINK_WriteReg(R4, 0x00000000) returns 0x00 (0000ms, 26835ms total) +T3170 090:214 JLINK_WriteReg(R5, 0x00000000) returns 0x00 (0000ms, 26835ms total) +T3170 090:214 JLINK_WriteReg(R6, 0x00000000) returns 0x00 (0000ms, 26835ms total) +T3170 090:214 JLINK_WriteReg(R7, 0x00000000) returns 0x00 (0000ms, 26835ms total) +T3170 090:214 JLINK_WriteReg(R8, 0x00000000) returns 0x00 (0000ms, 26835ms total) +T3170 090:214 JLINK_WriteReg(R9, 0x2000013C) returns 0x00 (0000ms, 26835ms total) +T3170 090:214 JLINK_WriteReg(R10, 0x00000000) returns 0x00 (0000ms, 26835ms total) +T3170 090:214 JLINK_WriteReg(R11, 0x00000000) returns 0x00 (0000ms, 26835ms total) +T3170 090:214 JLINK_WriteReg(R12, 0x00000000) returns 0x00 (0000ms, 26835ms total) +T3170 090:215 JLINK_WriteReg(R13 (SP), 0x20001000) returns 0x00 (0000ms, 26836ms total) +T3170 090:215 JLINK_WriteReg(R14, 0x20000001) returns 0x00 (0000ms, 26836ms total) +T3170 090:215 JLINK_WriteReg(R15 (PC), 0x2000005C) returns 0x00 (0000ms, 26836ms total) +T3170 090:215 JLINK_WriteReg(XPSR, 0x01000000) returns 0x00 (0000ms, 26836ms total) +T3170 090:215 JLINK_WriteReg(MSP, 0x20001000) returns 0x00 (0000ms, 26836ms total) +T3170 090:215 JLINK_WriteReg(PSP, 0x20001000) returns 0x00 (0000ms, 26836ms total) +T3170 090:215 JLINK_WriteReg(CFBP, 0x00000000) returns 0x00 (0000ms, 26836ms total) +T3170 090:215 JLINK_SetBPEx(Addr = 0x20000000, Type = 0xFFFFFFF2) returns 0x00000040 (0000ms, 26836ms total) +T3170 090:215 JLINK_Go() -- CPU_ReadMem(4 bytes @ 0xE0001000) (0088ms, 26924ms total) +T3170 090:303 JLINK_IsHalted() -- CPU_ReadMem(2 bytes @ 0x20000000) returns TRUE (0008ms, 26932ms total) +T3170 090:311 JLINK_ReadReg(R15 (PC)) returns 0x20000000 (0000ms, 26924ms total) +T3170 090:311 JLINK_ClrBPEx(BPHandle = 0x00000040) returns 0x00 (0000ms, 26924ms total) +T3170 090:311 JLINK_ReadReg(R0) returns 0x00000000 (0000ms, 26924ms total) +T3170 090:311 JLINK_WriteMem(0x20000144, 0x0080 Bytes, ...) - Data: 78 5F 62 75 66 66 65 72 00 00 00 00 30 75 20 3C ... -- CPU_WriteMem(128 bytes @ 0x20000144) returns 0x80 (0003ms, 26927ms total) +T3170 090:314 JLINK_WriteReg(R0, 0x00001880) returns 0x00 (0000ms, 26927ms total) +T3170 090:314 JLINK_WriteReg(R1, 0x00000080) returns 0x00 (0000ms, 26927ms total) +T3170 090:314 JLINK_WriteReg(R2, 0x20000144) returns 0x00 (0000ms, 26927ms total) +T3170 090:314 JLINK_WriteReg(R3, 0x00000000) returns 0x00 (0000ms, 26927ms total) +T3170 090:314 JLINK_WriteReg(R4, 0x00000000) returns 0x00 (0000ms, 26927ms total) +T3170 090:314 JLINK_WriteReg(R5, 0x00000000) returns 0x00 (0000ms, 26927ms total) +T3170 090:314 JLINK_WriteReg(R6, 0x00000000) returns 0x00 (0000ms, 26927ms total) +T3170 090:314 JLINK_WriteReg(R7, 0x00000000) returns 0x00 (0000ms, 26927ms total) +T3170 090:314 JLINK_WriteReg(R8, 0x00000000) returns 0x00 (0000ms, 26927ms total) +T3170 090:314 JLINK_WriteReg(R9, 0x2000013C) returns 0x00 (0000ms, 26927ms total) +T3170 090:314 JLINK_WriteReg(R10, 0x00000000) returns 0x00 (0000ms, 26927ms total) +T3170 090:314 JLINK_WriteReg(R11, 0x00000000) returns 0x00 (0000ms, 26927ms total) +T3170 090:314 JLINK_WriteReg(R12, 0x00000000) returns 0x00 (0000ms, 26927ms total) +T3170 090:314 JLINK_WriteReg(R13 (SP), 0x20001000) returns 0x00 (0000ms, 26927ms total) +T3170 090:314 JLINK_WriteReg(R14, 0x20000001) returns 0x00 (0000ms, 26927ms total) +T3170 090:314 JLINK_WriteReg(R15 (PC), 0x2000005C) returns 0x00 (0000ms, 26927ms total) +T3170 090:314 JLINK_WriteReg(XPSR, 0x01000000) returns 0x00 (0000ms, 26927ms total) +T3170 090:314 JLINK_WriteReg(MSP, 0x20001000) returns 0x00 (0000ms, 26927ms total) +T3170 090:314 JLINK_WriteReg(PSP, 0x20001000) returns 0x00 (0000ms, 26927ms total) +T3170 090:314 JLINK_WriteReg(CFBP, 0x00000000) returns 0x00 (0000ms, 26927ms total) +T3170 090:314 JLINK_SetBPEx(Addr = 0x20000000, Type = 0xFFFFFFF2) returns 0x00000041 (0000ms, 26927ms total) +T3170 090:314 JLINK_Go() -- CPU_ReadMem(4 bytes @ 0xE0001000) (0087ms, 27014ms total) +T3170 090:402 JLINK_IsHalted() -- CPU_ReadMem(2 bytes @ 0x20000000) returns TRUE (0010ms, 27025ms total) +T3170 090:412 JLINK_ReadReg(R15 (PC)) returns 0x20000000 (0000ms, 27015ms total) +T3170 090:412 JLINK_ClrBPEx(BPHandle = 0x00000041) returns 0x00 (0000ms, 27015ms total) +T3170 090:412 JLINK_ReadReg(R0) returns 0x00000000 (0000ms, 27015ms total) +T3170 090:412 JLINK_WriteMem(0x20000144, 0x0080 Bytes, ...) - Data: F0 00 00 20 D8 13 00 20 F4 00 00 20 6D 73 68 20 ... -- CPU_WriteMem(128 bytes @ 0x20000144) returns 0x80 (0004ms, 27019ms total) +T3170 090:416 JLINK_WriteReg(R0, 0x00001900) returns 0x00 (0000ms, 27019ms total) +T3170 090:416 JLINK_WriteReg(R1, 0x00000080) returns 0x00 (0000ms, 27019ms total) +T3170 090:416 JLINK_WriteReg(R2, 0x20000144) returns 0x00 (0000ms, 27019ms total) +T3170 090:416 JLINK_WriteReg(R3, 0x00000000) returns 0x00 (0000ms, 27019ms total) +T3170 090:416 JLINK_WriteReg(R4, 0x00000000) returns 0x00 (0000ms, 27019ms total) +T3170 090:416 JLINK_WriteReg(R5, 0x00000000) returns 0x00 (0000ms, 27019ms total) +T3170 090:416 JLINK_WriteReg(R6, 0x00000000) returns 0x00 (0000ms, 27019ms total) +T3170 090:416 JLINK_WriteReg(R7, 0x00000000) returns 0x00 (0000ms, 27019ms total) +T3170 090:416 JLINK_WriteReg(R8, 0x00000000) returns 0x00 (0000ms, 27019ms total) +T3170 090:416 JLINK_WriteReg(R9, 0x2000013C) returns 0x00 (0000ms, 27019ms total) +T3170 090:416 JLINK_WriteReg(R10, 0x00000000) returns 0x00 (0000ms, 27019ms total) +T3170 090:416 JLINK_WriteReg(R11, 0x00000000) returns 0x00 (0000ms, 27019ms total) +T3170 090:416 JLINK_WriteReg(R12, 0x00000000) returns 0x00 (0000ms, 27019ms total) +T3170 090:416 JLINK_WriteReg(R13 (SP), 0x20001000) returns 0x00 (0000ms, 27019ms total) +T3170 090:416 JLINK_WriteReg(R14, 0x20000001) returns 0x00 (0000ms, 27019ms total) +T3170 090:416 JLINK_WriteReg(R15 (PC), 0x2000005C) returns 0x00 (0000ms, 27019ms total) +T3170 090:416 JLINK_WriteReg(XPSR, 0x01000000) returns 0x00 (0000ms, 27019ms total) +T3170 090:416 JLINK_WriteReg(MSP, 0x20001000) returns 0x00 (0000ms, 27019ms total) +T3170 090:416 JLINK_WriteReg(PSP, 0x20001000) returns 0x00 (0000ms, 27019ms total) +T3170 090:416 JLINK_WriteReg(CFBP, 0x00000000) returns 0x00 (0000ms, 27019ms total) +T3170 090:416 JLINK_SetBPEx(Addr = 0x20000000, Type = 0xFFFFFFF2) returns 0x00000042 (0000ms, 27019ms total) +T3170 090:416 JLINK_Go() -- CPU_ReadMem(4 bytes @ 0xE0001000) (0088ms, 27107ms total) +T3170 090:504 JLINK_IsHalted() -- CPU_ReadMem(2 bytes @ 0x20000000) returns TRUE (0010ms, 27117ms total) +T3170 090:514 JLINK_ReadReg(R15 (PC)) returns 0x20000000 (0000ms, 27107ms total) +T3170 090:514 JLINK_ClrBPEx(BPHandle = 0x00000042) returns 0x00 (0000ms, 27107ms total) +T3170 090:514 JLINK_ReadReg(R0) returns 0x00000000 (0000ms, 27107ms total) +T3170 090:515 JLINK_WriteMem(0x20000144, 0x0080 Bytes, ...) - Data: 0A 20 06 21 4F F4 80 63 00 22 CD E9 00 10 14 49 ... -- CPU_WriteMem(128 bytes @ 0x20000144) returns 0x80 (0051ms, 27158ms total) +T3170 090:566 JLINK_WriteReg(R0, 0x00001980) returns 0x00 (0000ms, 27158ms total) +T3170 090:566 JLINK_WriteReg(R1, 0x00000080) returns 0x00 (0000ms, 27158ms total) +T3170 090:566 JLINK_WriteReg(R2, 0x20000144) returns 0x00 (0000ms, 27158ms total) +T3170 090:566 JLINK_WriteReg(R3, 0x00000000) returns 0x00 (0000ms, 27158ms total) +T3170 090:566 JLINK_WriteReg(R4, 0x00000000) returns 0x00 (0000ms, 27158ms total) +T3170 090:566 JLINK_WriteReg(R5, 0x00000000) returns 0x00 (0000ms, 27158ms total) +T3170 090:566 JLINK_WriteReg(R6, 0x00000000) returns 0x00 (0000ms, 27158ms total) +T3170 090:566 JLINK_WriteReg(R7, 0x00000000) returns 0x00 (0000ms, 27158ms total) +T3170 090:566 JLINK_WriteReg(R8, 0x00000000) returns 0x00 (0000ms, 27158ms total) +T3170 090:566 JLINK_WriteReg(R9, 0x2000013C) returns 0x00 (0000ms, 27158ms total) +T3170 090:566 JLINK_WriteReg(R10, 0x00000000) returns 0x00 (0000ms, 27158ms total) +T3170 090:566 JLINK_WriteReg(R11, 0x00000000) returns 0x00 (0000ms, 27158ms total) +T3170 090:566 JLINK_WriteReg(R12, 0x00000000) returns 0x00 (0000ms, 27158ms total) +T3170 090:566 JLINK_WriteReg(R13 (SP), 0x20001000) returns 0x00 (0000ms, 27158ms total) +T3170 090:566 JLINK_WriteReg(R14, 0x20000001) returns 0x00 (0001ms, 27159ms total) +T3170 090:567 JLINK_WriteReg(R15 (PC), 0x2000005C) returns 0x00 (0000ms, 27159ms total) +T3170 090:567 JLINK_WriteReg(XPSR, 0x01000000) returns 0x00 (0000ms, 27159ms total) +T3170 090:567 JLINK_WriteReg(MSP, 0x20001000) returns 0x00 (0000ms, 27159ms total) +T3170 090:567 JLINK_WriteReg(PSP, 0x20001000) returns 0x00 (0000ms, 27159ms total) +T3170 090:567 JLINK_WriteReg(CFBP, 0x00000000) returns 0x00 (0000ms, 27159ms total) +T3170 090:567 JLINK_SetBPEx(Addr = 0x20000000, Type = 0xFFFFFFF2) returns 0x00000043 (0000ms, 27159ms total) +T3170 090:567 JLINK_Go() -- CPU_ReadMem(4 bytes @ 0xE0001000) (0037ms, 27196ms total) +T3170 090:604 JLINK_IsHalted() -- CPU_ReadMem(2 bytes @ 0x20000000) returns TRUE (0011ms, 27207ms total) +T3170 090:615 JLINK_ReadReg(R15 (PC)) returns 0x20000000 (0000ms, 27196ms total) +T3170 090:615 JLINK_ClrBPEx(BPHandle = 0x00000043) returns 0x00 (0000ms, 27196ms total) +T3170 090:615 JLINK_ReadReg(R0) returns 0x00000000 (0000ms, 27196ms total) +T3170 090:615 JLINK_WriteMem(0x20000144, 0x0080 Bytes, ...) - Data: 40 1C E6 49 09 68 81 F8 21 00 FF F7 4F FF 05 46 ... -- CPU_WriteMem(128 bytes @ 0x20000144) returns 0x80 (0085ms, 27281ms total) +T3170 090:701 JLINK_WriteReg(R0, 0x00001A00) returns 0x00 (0000ms, 27281ms total) +T3170 090:701 JLINK_WriteReg(R1, 0x00000080) returns 0x00 (0000ms, 27281ms total) +T3170 090:701 JLINK_WriteReg(R2, 0x20000144) returns 0x00 (0000ms, 27281ms total) +T3170 090:701 JLINK_WriteReg(R3, 0x00000000) returns 0x00 (0000ms, 27281ms total) +T3170 090:701 JLINK_WriteReg(R4, 0x00000000) returns 0x00 (0000ms, 27281ms total) +T3170 090:701 JLINK_WriteReg(R5, 0x00000000) returns 0x00 (0000ms, 27281ms total) +T3170 090:701 JLINK_WriteReg(R6, 0x00000000) returns 0x00 (0000ms, 27281ms total) +T3170 090:701 JLINK_WriteReg(R7, 0x00000000) returns 0x00 (0000ms, 27281ms total) +T3170 090:701 JLINK_WriteReg(R8, 0x00000000) returns 0x00 (0000ms, 27281ms total) +T3170 090:701 JLINK_WriteReg(R9, 0x2000013C) returns 0x00 (0000ms, 27281ms total) +T3170 090:701 JLINK_WriteReg(R10, 0x00000000) returns 0x00 (0000ms, 27281ms total) +T3170 090:701 JLINK_WriteReg(R11, 0x00000000) returns 0x00 (0000ms, 27281ms total) +T3170 090:701 JLINK_WriteReg(R12, 0x00000000) returns 0x00 (0000ms, 27281ms total) +T3170 090:701 JLINK_WriteReg(R13 (SP), 0x20001000) returns 0x00 (0000ms, 27281ms total) +T3170 090:701 JLINK_WriteReg(R14, 0x20000001) returns 0x00 (0000ms, 27281ms total) +T3170 090:701 JLINK_WriteReg(R15 (PC), 0x2000005C) returns 0x00 (0000ms, 27281ms total) +T3170 090:701 JLINK_WriteReg(XPSR, 0x01000000) returns 0x00 (0000ms, 27281ms total) +T3170 090:701 JLINK_WriteReg(MSP, 0x20001000) returns 0x00 (0000ms, 27281ms total) +T3170 090:701 JLINK_WriteReg(PSP, 0x20001000) returns 0x00 (0000ms, 27281ms total) +T3170 090:701 JLINK_WriteReg(CFBP, 0x00000000) returns 0x00 (0000ms, 27281ms total) +T3170 090:701 JLINK_SetBPEx(Addr = 0x20000000, Type = 0xFFFFFFF2) returns 0x00000044 (0000ms, 27281ms total) +T3170 090:701 JLINK_Go() -- CPU_ReadMem(4 bytes @ 0xE0001000) (0008ms, 27289ms total) +T3170 090:709 JLINK_IsHalted() -- CPU_ReadMem(2 bytes @ 0x20000000) returns TRUE (0087ms, 27376ms total) +T3170 090:796 JLINK_ReadReg(R15 (PC)) returns 0x20000000 (0000ms, 27289ms total) +T3170 090:796 JLINK_ClrBPEx(BPHandle = 0x00000044) returns 0x00 (0000ms, 27289ms total) +T3170 090:796 JLINK_ReadReg(R0) returns 0x00000000 (0000ms, 27289ms total) +T3170 090:796 JLINK_WriteMem(0x20000144, 0x0080 Bytes, ...) - Data: C6 48 00 68 B0 F8 74 00 58 B1 C5 A0 01 F0 68 FE ... -- CPU_WriteMem(128 bytes @ 0x20000144) returns 0x80 (0005ms, 27294ms total) +T3170 090:801 JLINK_WriteReg(R0, 0x00001A80) returns 0x00 (0000ms, 27294ms total) +T3170 090:801 JLINK_WriteReg(R1, 0x00000080) returns 0x00 (0000ms, 27294ms total) +T3170 090:801 JLINK_WriteReg(R2, 0x20000144) returns 0x00 (0000ms, 27294ms total) +T3170 090:801 JLINK_WriteReg(R3, 0x00000000) returns 0x00 (0000ms, 27294ms total) +T3170 090:801 JLINK_WriteReg(R4, 0x00000000) returns 0x00 (0000ms, 27294ms total) +T3170 090:801 JLINK_WriteReg(R5, 0x00000000) returns 0x00 (0000ms, 27294ms total) +T3170 090:801 JLINK_WriteReg(R6, 0x00000000) returns 0x00 (0000ms, 27294ms total) +T3170 090:801 JLINK_WriteReg(R7, 0x00000000) returns 0x00 (0000ms, 27294ms total) +T3170 090:801 JLINK_WriteReg(R8, 0x00000000) returns 0x00 (0000ms, 27294ms total) +T3170 090:801 JLINK_WriteReg(R9, 0x2000013C) returns 0x00 (0000ms, 27294ms total) +T3170 090:801 JLINK_WriteReg(R10, 0x00000000) returns 0x00 (0000ms, 27294ms total) +T3170 090:801 JLINK_WriteReg(R11, 0x00000000) returns 0x00 (0000ms, 27294ms total) +T3170 090:801 JLINK_WriteReg(R12, 0x00000000) returns 0x00 (0000ms, 27294ms total) +T3170 090:801 JLINK_WriteReg(R13 (SP), 0x20001000) returns 0x00 (0000ms, 27294ms total) +T3170 090:801 JLINK_WriteReg(R14, 0x20000001) returns 0x00 (0000ms, 27294ms total) +T3170 090:801 JLINK_WriteReg(R15 (PC), 0x2000005C) returns 0x00 (0000ms, 27294ms total) +T3170 090:801 JLINK_WriteReg(XPSR, 0x01000000) returns 0x00 (0000ms, 27294ms total) +T3170 090:801 JLINK_WriteReg(MSP, 0x20001000) returns 0x00 (0000ms, 27294ms total) +T3170 090:801 JLINK_WriteReg(PSP, 0x20001000) returns 0x00 (0000ms, 27294ms total) +T3170 090:801 JLINK_WriteReg(CFBP, 0x00000000) returns 0x00 (0000ms, 27294ms total) +T3170 090:801 JLINK_SetBPEx(Addr = 0x20000000, Type = 0xFFFFFFF2) returns 0x00000045 (0000ms, 27294ms total) +T3170 090:801 JLINK_Go() -- CPU_ReadMem(4 bytes @ 0xE0001000) (0007ms, 27301ms total) +T3170 090:808 JLINK_IsHalted() -- CPU_ReadMem(2 bytes @ 0x20000000) returns TRUE (0005ms, 27306ms total) +T3170 090:813 JLINK_ReadReg(R15 (PC)) returns 0x20000000 (0000ms, 27301ms total) +T3170 090:813 JLINK_ClrBPEx(BPHandle = 0x00000045) returns 0x00 (0000ms, 27301ms total) +T3170 090:813 JLINK_ReadReg(R0) returns 0x00000000 (0000ms, 27301ms total) +T3170 090:814 JLINK_WriteMem(0x20000144, 0x0080 Bytes, ...) - Data: 00 68 B0 F8 74 00 A8 42 F5 DC A4 48 00 68 22 30 ... -- CPU_WriteMem(128 bytes @ 0x20000144) returns 0x80 (0013ms, 27314ms total) +T3170 090:827 JLINK_WriteReg(R0, 0x00001B00) returns 0x00 (0000ms, 27314ms total) +T3170 090:827 JLINK_WriteReg(R1, 0x00000080) returns 0x00 (0000ms, 27314ms total) +T3170 090:827 JLINK_WriteReg(R2, 0x20000144) returns 0x00 (0000ms, 27314ms total) +T3170 090:827 JLINK_WriteReg(R3, 0x00000000) returns 0x00 (0000ms, 27314ms total) +T3170 090:827 JLINK_WriteReg(R4, 0x00000000) returns 0x00 (0000ms, 27314ms total) +T3170 090:827 JLINK_WriteReg(R5, 0x00000000) returns 0x00 (0000ms, 27314ms total) +T3170 090:827 JLINK_WriteReg(R6, 0x00000000) returns 0x00 (0000ms, 27314ms total) +T3170 090:827 JLINK_WriteReg(R7, 0x00000000) returns 0x00 (0000ms, 27314ms total) +T3170 090:827 JLINK_WriteReg(R8, 0x00000000) returns 0x00 (0000ms, 27314ms total) +T3170 090:827 JLINK_WriteReg(R9, 0x2000013C) returns 0x00 (0000ms, 27314ms total) +T3170 090:827 JLINK_WriteReg(R10, 0x00000000) returns 0x00 (0001ms, 27315ms total) +T3170 090:828 JLINK_WriteReg(R11, 0x00000000) returns 0x00 (0000ms, 27315ms total) +T3170 090:828 JLINK_WriteReg(R12, 0x00000000) returns 0x00 (0000ms, 27315ms total) +T3170 090:828 JLINK_WriteReg(R13 (SP), 0x20001000) returns 0x00 (0000ms, 27315ms total) +T3170 090:828 JLINK_WriteReg(R14, 0x20000001) returns 0x00 (0000ms, 27315ms total) +T3170 090:828 JLINK_WriteReg(R15 (PC), 0x2000005C) returns 0x00 (0000ms, 27315ms total) +T3170 090:828 JLINK_WriteReg(XPSR, 0x01000000) returns 0x00 (0000ms, 27315ms total) +T3170 090:828 JLINK_WriteReg(MSP, 0x20001000) returns 0x00 (0000ms, 27315ms total) +T3170 090:828 JLINK_WriteReg(PSP, 0x20001000) returns 0x00 (0000ms, 27315ms total) +T3170 090:828 JLINK_WriteReg(CFBP, 0x00000000) returns 0x00 (0000ms, 27315ms total) +T3170 090:828 JLINK_SetBPEx(Addr = 0x20000000, Type = 0xFFFFFFF2) returns 0x00000046 (0000ms, 27315ms total) +T3170 090:828 JLINK_Go() -- CPU_ReadMem(4 bytes @ 0xE0001000) (0076ms, 27391ms total) +T3170 090:904 JLINK_IsHalted() -- CPU_ReadMem(2 bytes @ 0x20000000) returns TRUE (0009ms, 27400ms total) +T3170 090:913 JLINK_ReadReg(R15 (PC)) returns 0x20000000 (0000ms, 27391ms total) +T3170 090:913 JLINK_ClrBPEx(BPHandle = 0x00000046) returns 0x00 (0000ms, 27391ms total) +T3170 090:913 JLINK_ReadReg(R0) returns 0x00000000 (0000ms, 27391ms total) +T3170 090:913 JLINK_WriteMem(0x20000144, 0x0080 Bytes, ...) - Data: 1B 68 B3 F8 72 30 85 4E 36 68 B6 F8 74 60 9A 1B ... -- CPU_WriteMem(128 bytes @ 0x20000144) returns 0x80 (0003ms, 27394ms total) +T3170 090:916 JLINK_WriteReg(R0, 0x00001B80) returns 0x00 (0000ms, 27394ms total) +T3170 090:916 JLINK_WriteReg(R1, 0x00000080) returns 0x00 (0000ms, 27394ms total) +T3170 090:916 JLINK_WriteReg(R2, 0x20000144) returns 0x00 (0000ms, 27394ms total) +T3170 090:916 JLINK_WriteReg(R3, 0x00000000) returns 0x00 (0000ms, 27394ms total) +T3170 090:916 JLINK_WriteReg(R4, 0x00000000) returns 0x00 (0000ms, 27394ms total) +T3170 090:916 JLINK_WriteReg(R5, 0x00000000) returns 0x00 (0000ms, 27394ms total) +T3170 090:916 JLINK_WriteReg(R6, 0x00000000) returns 0x00 (0000ms, 27394ms total) +T3170 090:917 JLINK_WriteReg(R7, 0x00000000) returns 0x00 (0000ms, 27395ms total) +T3170 090:917 JLINK_WriteReg(R8, 0x00000000) returns 0x00 (0000ms, 27395ms total) +T3170 090:917 JLINK_WriteReg(R9, 0x2000013C) returns 0x00 (0000ms, 27395ms total) +T3170 090:917 JLINK_WriteReg(R10, 0x00000000) returns 0x00 (0000ms, 27395ms total) +T3170 090:917 JLINK_WriteReg(R11, 0x00000000) returns 0x00 (0000ms, 27395ms total) +T3170 090:917 JLINK_WriteReg(R12, 0x00000000) returns 0x00 (0000ms, 27395ms total) +T3170 090:917 JLINK_WriteReg(R13 (SP), 0x20001000) returns 0x00 (0000ms, 27395ms total) +T3170 090:917 JLINK_WriteReg(R14, 0x20000001) returns 0x00 (0000ms, 27395ms total) +T3170 090:917 JLINK_WriteReg(R15 (PC), 0x2000005C) returns 0x00 (0000ms, 27395ms total) +T3170 090:917 JLINK_WriteReg(XPSR, 0x01000000) returns 0x00 (0000ms, 27395ms total) +T3170 090:917 JLINK_WriteReg(MSP, 0x20001000) returns 0x00 (0000ms, 27395ms total) +T3170 090:917 JLINK_WriteReg(PSP, 0x20001000) returns 0x00 (0000ms, 27395ms total) +T3170 090:917 JLINK_WriteReg(CFBP, 0x00000000) returns 0x00 (0000ms, 27395ms total) +T3170 090:917 JLINK_SetBPEx(Addr = 0x20000000, Type = 0xFFFFFFF2) returns 0x00000047 (0000ms, 27395ms total) +T3170 090:917 JLINK_Go() -- CPU_ReadMem(4 bytes @ 0xE0001000) (0087ms, 27482ms total) +T3170 091:004 JLINK_IsHalted() -- CPU_ReadMem(2 bytes @ 0x20000000) returns TRUE (0007ms, 27489ms total) +T3170 091:011 JLINK_ReadReg(R15 (PC)) returns 0x20000000 (0000ms, 27482ms total) +T3170 091:011 JLINK_ClrBPEx(BPHandle = 0x00000047) returns 0x00 (0000ms, 27482ms total) +T3170 091:011 JLINK_ReadReg(R0) returns 0x00000000 (0000ms, 27482ms total) +T3170 091:011 JLINK_WriteMem(0x20000144, 0x0080 Bytes, ...) - Data: 01 F0 AE FD 00 21 65 48 00 68 B0 F8 72 20 63 48 ... -- CPU_WriteMem(128 bytes @ 0x20000144) returns 0x80 (0003ms, 27485ms total) +T3170 091:014 JLINK_WriteReg(R0, 0x00001C00) returns 0x00 (0000ms, 27485ms total) +T3170 091:014 JLINK_WriteReg(R1, 0x00000080) returns 0x00 (0000ms, 27485ms total) +T3170 091:014 JLINK_WriteReg(R2, 0x20000144) returns 0x00 (0000ms, 27485ms total) +T3170 091:014 JLINK_WriteReg(R3, 0x00000000) returns 0x00 (0000ms, 27485ms total) +T3170 091:014 JLINK_WriteReg(R4, 0x00000000) returns 0x00 (0000ms, 27485ms total) +T3170 091:014 JLINK_WriteReg(R5, 0x00000000) returns 0x00 (0000ms, 27485ms total) +T3170 091:014 JLINK_WriteReg(R6, 0x00000000) returns 0x00 (0000ms, 27485ms total) +T3170 091:014 JLINK_WriteReg(R7, 0x00000000) returns 0x00 (0000ms, 27485ms total) +T3170 091:014 JLINK_WriteReg(R8, 0x00000000) returns 0x00 (0000ms, 27485ms total) +T3170 091:014 JLINK_WriteReg(R9, 0x2000013C) returns 0x00 (0000ms, 27485ms total) +T3170 091:014 JLINK_WriteReg(R10, 0x00000000) returns 0x00 (0000ms, 27485ms total) +T3170 091:014 JLINK_WriteReg(R11, 0x00000000) returns 0x00 (0000ms, 27485ms total) +T3170 091:014 JLINK_WriteReg(R12, 0x00000000) returns 0x00 (0000ms, 27485ms total) +T3170 091:014 JLINK_WriteReg(R13 (SP), 0x20001000) returns 0x00 (0000ms, 27485ms total) +T3170 091:014 JLINK_WriteReg(R14, 0x20000001) returns 0x00 (0000ms, 27485ms total) +T3170 091:014 JLINK_WriteReg(R15 (PC), 0x2000005C) returns 0x00 (0000ms, 27485ms total) +T3170 091:014 JLINK_WriteReg(XPSR, 0x01000000) returns 0x00 (0000ms, 27485ms total) +T3170 091:014 JLINK_WriteReg(MSP, 0x20001000) returns 0x00 (0000ms, 27485ms total) +T3170 091:014 JLINK_WriteReg(PSP, 0x20001000) returns 0x00 (0000ms, 27485ms total) +T3170 091:014 JLINK_WriteReg(CFBP, 0x00000000) returns 0x00 (0000ms, 27485ms total) +T3170 091:014 JLINK_SetBPEx(Addr = 0x20000000, Type = 0xFFFFFFF2) returns 0x00000048 (0000ms, 27485ms total) +T3170 091:014 JLINK_Go() -- CPU_ReadMem(4 bytes @ 0xE0001000) (0087ms, 27572ms total) +T3170 091:101 JLINK_IsHalted() -- CPU_ReadMem(2 bytes @ 0x20000000) returns TRUE (0008ms, 27580ms total) +T3170 091:109 JLINK_ReadReg(R15 (PC)) returns 0x20000000 (0000ms, 27572ms total) +T3170 091:109 JLINK_ClrBPEx(BPHandle = 0x00000048) returns 0x00 (0000ms, 27572ms total) +T3170 091:109 JLINK_ReadReg(R0) returns 0x00000000 (0000ms, 27572ms total) +T3170 091:109 JLINK_WriteMem(0x20000144, 0x0080 Bytes, ...) - Data: 50 28 04 DB 00 20 45 49 09 68 A1 F8 72 00 43 48 ... -- CPU_WriteMem(128 bytes @ 0x20000144) returns 0x80 (0004ms, 27576ms total) +T3170 091:113 JLINK_WriteReg(R0, 0x00001C80) returns 0x00 (0000ms, 27576ms total) +T3170 091:113 JLINK_WriteReg(R1, 0x00000080) returns 0x00 (0000ms, 27576ms total) +T3170 091:113 JLINK_WriteReg(R2, 0x20000144) returns 0x00 (0000ms, 27576ms total) +T3170 091:113 JLINK_WriteReg(R3, 0x00000000) returns 0x00 (0000ms, 27576ms total) +T3170 091:113 JLINK_WriteReg(R4, 0x00000000) returns 0x00 (0000ms, 27576ms total) +T3170 091:113 JLINK_WriteReg(R5, 0x00000000) returns 0x00 (0000ms, 27576ms total) +T3170 091:113 JLINK_WriteReg(R6, 0x00000000) returns 0x00 (0000ms, 27576ms total) +T3170 091:113 JLINK_WriteReg(R7, 0x00000000) returns 0x00 (0000ms, 27576ms total) +T3170 091:113 JLINK_WriteReg(R8, 0x00000000) returns 0x00 (0000ms, 27576ms total) +T3170 091:113 JLINK_WriteReg(R9, 0x2000013C) returns 0x00 (0000ms, 27576ms total) +T3170 091:113 JLINK_WriteReg(R10, 0x00000000) returns 0x00 (0000ms, 27576ms total) +T3170 091:113 JLINK_WriteReg(R11, 0x00000000) returns 0x00 (0001ms, 27577ms total) +T3170 091:114 JLINK_WriteReg(R12, 0x00000000) returns 0x00 (0000ms, 27577ms total) +T3170 091:114 JLINK_WriteReg(R13 (SP), 0x20001000) returns 0x00 (0000ms, 27577ms total) +T3170 091:114 JLINK_WriteReg(R14, 0x20000001) returns 0x00 (0000ms, 27577ms total) +T3170 091:114 JLINK_WriteReg(R15 (PC), 0x2000005C) returns 0x00 (0000ms, 27577ms total) +T3170 091:114 JLINK_WriteReg(XPSR, 0x01000000) returns 0x00 (0000ms, 27577ms total) +T3170 091:114 JLINK_WriteReg(MSP, 0x20001000) returns 0x00 (0000ms, 27577ms total) +T3170 091:114 JLINK_WriteReg(PSP, 0x20001000) returns 0x00 (0000ms, 27577ms total) +T3170 091:114 JLINK_WriteReg(CFBP, 0x00000000) returns 0x00 (0000ms, 27577ms total) +T3170 091:114 JLINK_SetBPEx(Addr = 0x20000000, Type = 0xFFFFFFF2) returns 0x00000049 (0000ms, 27577ms total) +T3170 091:114 JLINK_Go() -- CPU_ReadMem(4 bytes @ 0xE0001000) (0090ms, 27667ms total) +T3170 091:204 JLINK_IsHalted() -- CPU_ReadMem(2 bytes @ 0x20000000) returns TRUE (0005ms, 27672ms total) +T3170 091:212 JLINK_ReadReg(R15 (PC)) returns 0x20000000 (0000ms, 27667ms total) +T3170 091:212 JLINK_ClrBPEx(BPHandle = 0x00000049) returns 0x00 (0000ms, 27667ms total) +T3170 091:212 JLINK_ReadReg(R0) returns 0x00000000 (0000ms, 27667ms total) +T3170 091:212 JLINK_WriteMem(0x20000144, 0x0080 Bytes, ...) - Data: 26 48 00 68 22 30 11 18 2B A0 01 F0 29 FD 23 48 ... -- CPU_WriteMem(128 bytes @ 0x20000144) returns 0x80 (0002ms, 27669ms total) +T3170 091:214 JLINK_WriteReg(R0, 0x00001D00) returns 0x00 (0000ms, 27669ms total) +T3170 091:214 JLINK_WriteReg(R1, 0x00000080) returns 0x00 (0000ms, 27669ms total) +T3170 091:214 JLINK_WriteReg(R2, 0x20000144) returns 0x00 (0000ms, 27669ms total) +T3170 091:214 JLINK_WriteReg(R3, 0x00000000) returns 0x00 (0000ms, 27669ms total) +T3170 091:214 JLINK_WriteReg(R4, 0x00000000) returns 0x00 (0000ms, 27669ms total) +T3170 091:214 JLINK_WriteReg(R5, 0x00000000) returns 0x00 (0000ms, 27669ms total) +T3170 091:214 JLINK_WriteReg(R6, 0x00000000) returns 0x00 (0000ms, 27669ms total) +T3170 091:214 JLINK_WriteReg(R7, 0x00000000) returns 0x00 (0000ms, 27669ms total) +T3170 091:214 JLINK_WriteReg(R8, 0x00000000) returns 0x00 (0000ms, 27669ms total) +T3170 091:214 JLINK_WriteReg(R9, 0x2000013C) returns 0x00 (0000ms, 27669ms total) +T3170 091:214 JLINK_WriteReg(R10, 0x00000000) returns 0x00 (0000ms, 27669ms total) +T3170 091:214 JLINK_WriteReg(R11, 0x00000000) returns 0x00 (0000ms, 27669ms total) +T3170 091:214 JLINK_WriteReg(R12, 0x00000000) returns 0x00 (0000ms, 27669ms total) +T3170 091:215 JLINK_WriteReg(R13 (SP), 0x20001000) returns 0x00 (0000ms, 27670ms total) +T3170 091:215 JLINK_WriteReg(R14, 0x20000001) returns 0x00 (0000ms, 27670ms total) +T3170 091:215 JLINK_WriteReg(R15 (PC), 0x2000005C) returns 0x00 (0000ms, 27670ms total) +T3170 091:215 JLINK_WriteReg(XPSR, 0x01000000) returns 0x00 (0000ms, 27670ms total) +T3170 091:215 JLINK_WriteReg(MSP, 0x20001000) returns 0x00 (0000ms, 27670ms total) +T3170 091:215 JLINK_WriteReg(PSP, 0x20001000) returns 0x00 (0000ms, 27670ms total) +T3170 091:215 JLINK_WriteReg(CFBP, 0x00000000) returns 0x00 (0000ms, 27670ms total) +T3170 091:215 JLINK_SetBPEx(Addr = 0x20000000, Type = 0xFFFFFFF2) returns 0x0000004A (0000ms, 27670ms total) +T3170 091:215 JLINK_Go() -- CPU_ReadMem(4 bytes @ 0xE0001000) (0089ms, 27759ms total) +T3170 091:304 JLINK_IsHalted() -- CPU_ReadMem(2 bytes @ 0x20000000) returns TRUE (0007ms, 27766ms total) +T3170 091:311 JLINK_ReadReg(R15 (PC)) returns 0x20000000 (0000ms, 27759ms total) +T3170 091:311 JLINK_ClrBPEx(BPHandle = 0x0000004A) returns 0x00 (0000ms, 27759ms total) +T3170 091:311 JLINK_ReadReg(R0) returns 0x00000000 (0000ms, 27759ms total) +T3170 091:311 JLINK_WriteMem(0x20000144, 0x0080 Bytes, ...) - Data: 72 00 50 28 08 DB 00 20 04 49 09 68 A1 F8 72 00 ... -- CPU_WriteMem(128 bytes @ 0x20000144) returns 0x80 (0003ms, 27762ms total) +T3170 091:314 JLINK_WriteReg(R0, 0x00001D80) returns 0x00 (0000ms, 27762ms total) +T3170 091:314 JLINK_WriteReg(R1, 0x00000080) returns 0x00 (0000ms, 27762ms total) +T3170 091:314 JLINK_WriteReg(R2, 0x20000144) returns 0x00 (0000ms, 27762ms total) +T3170 091:314 JLINK_WriteReg(R3, 0x00000000) returns 0x00 (0000ms, 27762ms total) +T3170 091:314 JLINK_WriteReg(R4, 0x00000000) returns 0x00 (0000ms, 27762ms total) +T3170 091:314 JLINK_WriteReg(R5, 0x00000000) returns 0x00 (0000ms, 27762ms total) +T3170 091:314 JLINK_WriteReg(R6, 0x00000000) returns 0x00 (0000ms, 27762ms total) +T3170 091:314 JLINK_WriteReg(R7, 0x00000000) returns 0x00 (0000ms, 27762ms total) +T3170 091:314 JLINK_WriteReg(R8, 0x00000000) returns 0x00 (0000ms, 27762ms total) +T3170 091:314 JLINK_WriteReg(R9, 0x2000013C) returns 0x00 (0000ms, 27762ms total) +T3170 091:314 JLINK_WriteReg(R10, 0x00000000) returns 0x00 (0000ms, 27762ms total) +T3170 091:314 JLINK_WriteReg(R11, 0x00000000) returns 0x00 (0000ms, 27762ms total) +T3170 091:314 JLINK_WriteReg(R12, 0x00000000) returns 0x00 (0000ms, 27762ms total) +T3170 091:314 JLINK_WriteReg(R13 (SP), 0x20001000) returns 0x00 (0000ms, 27762ms total) +T3170 091:314 JLINK_WriteReg(R14, 0x20000001) returns 0x00 (0000ms, 27762ms total) +T3170 091:314 JLINK_WriteReg(R15 (PC), 0x2000005C) returns 0x00 (0000ms, 27762ms total) +T3170 091:314 JLINK_WriteReg(XPSR, 0x01000000) returns 0x00 (0000ms, 27762ms total) +T3170 091:314 JLINK_WriteReg(MSP, 0x20001000) returns 0x00 (0000ms, 27762ms total) +T3170 091:314 JLINK_WriteReg(PSP, 0x20001000) returns 0x00 (0000ms, 27762ms total) +T3170 091:314 JLINK_WriteReg(CFBP, 0x00000000) returns 0x00 (0000ms, 27762ms total) +T3170 091:314 JLINK_SetBPEx(Addr = 0x20000000, Type = 0xFFFFFFF2) returns 0x0000004B (0000ms, 27762ms total) +T3170 091:314 JLINK_Go() -- CPU_ReadMem(4 bytes @ 0xE0001000) (0088ms, 27850ms total) +T3170 091:402 JLINK_IsHalted() -- CPU_ReadMem(2 bytes @ 0x20000000) returns TRUE (0007ms, 27857ms total) +T3170 091:409 JLINK_ReadReg(R15 (PC)) returns 0x20000000 (0000ms, 27850ms total) +T3170 091:409 JLINK_ClrBPEx(BPHandle = 0x0000004B) returns 0x00 (0000ms, 27850ms total) +T3170 091:409 JLINK_ReadReg(R0) returns 0x00000000 (0000ms, 27850ms total) +T3170 091:409 JLINK_WriteMem(0x20000144, 0x0080 Bytes, ...) - Data: 4C 81 03 40 70 B5 04 46 0E 46 15 46 52 48 84 42 ... -- CPU_WriteMem(128 bytes @ 0x20000144) returns 0x80 (0003ms, 27853ms total) +T3170 091:412 JLINK_WriteReg(R0, 0x00001E00) returns 0x00 (0000ms, 27853ms total) +T3170 091:412 JLINK_WriteReg(R1, 0x00000080) returns 0x00 (0000ms, 27853ms total) +T3170 091:412 JLINK_WriteReg(R2, 0x20000144) returns 0x00 (0000ms, 27853ms total) +T3170 091:412 JLINK_WriteReg(R3, 0x00000000) returns 0x00 (0000ms, 27853ms total) +T3170 091:412 JLINK_WriteReg(R4, 0x00000000) returns 0x00 (0000ms, 27853ms total) +T3170 091:412 JLINK_WriteReg(R5, 0x00000000) returns 0x00 (0000ms, 27853ms total) +T3170 091:412 JLINK_WriteReg(R6, 0x00000000) returns 0x00 (0000ms, 27853ms total) +T3170 091:412 JLINK_WriteReg(R7, 0x00000000) returns 0x00 (0000ms, 27853ms total) +T3170 091:412 JLINK_WriteReg(R8, 0x00000000) returns 0x00 (0000ms, 27853ms total) +T3170 091:412 JLINK_WriteReg(R9, 0x2000013C) returns 0x00 (0000ms, 27853ms total) +T3170 091:412 JLINK_WriteReg(R10, 0x00000000) returns 0x00 (0000ms, 27853ms total) +T3170 091:412 JLINK_WriteReg(R11, 0x00000000) returns 0x00 (0000ms, 27853ms total) +T3170 091:412 JLINK_WriteReg(R12, 0x00000000) returns 0x00 (0000ms, 27853ms total) +T3170 091:412 JLINK_WriteReg(R13 (SP), 0x20001000) returns 0x00 (0000ms, 27853ms total) +T3170 091:412 JLINK_WriteReg(R14, 0x20000001) returns 0x00 (0000ms, 27853ms total) +T3170 091:412 JLINK_WriteReg(R15 (PC), 0x2000005C) returns 0x00 (0000ms, 27853ms total) +T3170 091:412 JLINK_WriteReg(XPSR, 0x01000000) returns 0x00 (0000ms, 27853ms total) +T3170 091:412 JLINK_WriteReg(MSP, 0x20001000) returns 0x00 (0000ms, 27853ms total) +T3170 091:412 JLINK_WriteReg(PSP, 0x20001000) returns 0x00 (0000ms, 27853ms total) +T3170 091:412 JLINK_WriteReg(CFBP, 0x00000000) returns 0x00 (0000ms, 27853ms total) +T3170 091:412 JLINK_SetBPEx(Addr = 0x20000000, Type = 0xFFFFFFF2) returns 0x0000004C (0000ms, 27853ms total) +T3170 091:412 JLINK_Go() -- CPU_ReadMem(4 bytes @ 0xE0001000) (0087ms, 27940ms total) +T3170 091:499 JLINK_IsHalted() -- CPU_ReadMem(2 bytes @ 0x20000000) returns TRUE (0006ms, 27946ms total) +T3170 091:505 JLINK_ReadReg(R15 (PC)) returns 0x20000000 (0000ms, 27940ms total) +T3170 091:505 JLINK_ClrBPEx(BPHandle = 0x0000004C) returns 0x00 (0000ms, 27940ms total) +T3170 091:505 JLINK_ReadReg(R0) returns 0x00000000 (0000ms, 27940ms total) +T3170 091:505 JLINK_WriteMem(0x20000144, 0x0080 Bytes, ...) - Data: 08 71 21 68 08 72 21 68 01 F1 08 00 01 21 02 F0 ... -- CPU_WriteMem(128 bytes @ 0x20000144) returns 0x80 (0003ms, 27943ms total) +T3170 091:508 JLINK_WriteReg(R0, 0x00001E80) returns 0x00 (0000ms, 27943ms total) +T3170 091:508 JLINK_WriteReg(R1, 0x00000080) returns 0x00 (0000ms, 27943ms total) +T3170 091:508 JLINK_WriteReg(R2, 0x20000144) returns 0x00 (0000ms, 27943ms total) +T3170 091:508 JLINK_WriteReg(R3, 0x00000000) returns 0x00 (0000ms, 27943ms total) +T3170 091:508 JLINK_WriteReg(R4, 0x00000000) returns 0x00 (0000ms, 27943ms total) +T3170 091:508 JLINK_WriteReg(R5, 0x00000000) returns 0x00 (0000ms, 27943ms total) +T3170 091:508 JLINK_WriteReg(R6, 0x00000000) returns 0x00 (0000ms, 27943ms total) +T3170 091:508 JLINK_WriteReg(R7, 0x00000000) returns 0x00 (0000ms, 27943ms total) +T3170 091:508 JLINK_WriteReg(R8, 0x00000000) returns 0x00 (0000ms, 27943ms total) +T3170 091:508 JLINK_WriteReg(R9, 0x2000013C) returns 0x00 (0000ms, 27943ms total) +T3170 091:508 JLINK_WriteReg(R10, 0x00000000) returns 0x00 (0000ms, 27943ms total) +T3170 091:508 JLINK_WriteReg(R11, 0x00000000) returns 0x00 (0000ms, 27943ms total) +T3170 091:508 JLINK_WriteReg(R12, 0x00000000) returns 0x00 (0000ms, 27943ms total) +T3170 091:508 JLINK_WriteReg(R13 (SP), 0x20001000) returns 0x00 (0000ms, 27943ms total) +T3170 091:508 JLINK_WriteReg(R14, 0x20000001) returns 0x00 (0000ms, 27943ms total) +T3170 091:508 JLINK_WriteReg(R15 (PC), 0x2000005C) returns 0x00 (0000ms, 27943ms total) +T3170 091:508 JLINK_WriteReg(XPSR, 0x01000000) returns 0x00 (0000ms, 27943ms total) +T3170 091:508 JLINK_WriteReg(MSP, 0x20001000) returns 0x00 (0000ms, 27943ms total) +T3170 091:508 JLINK_WriteReg(PSP, 0x20001000) returns 0x00 (0001ms, 27944ms total) +T3170 091:509 JLINK_WriteReg(CFBP, 0x00000000) returns 0x00 (0000ms, 27944ms total) +T3170 091:509 JLINK_SetBPEx(Addr = 0x20000000, Type = 0xFFFFFFF2) returns 0x0000004D (0000ms, 27944ms total) +T3170 091:509 JLINK_Go() -- CPU_ReadMem(4 bytes @ 0xE0001000) (0006ms, 27950ms total) +T3170 091:515 JLINK_IsHalted() -- CPU_ReadMem(2 bytes @ 0x20000000) returns TRUE (0092ms, 28042ms total) +T3170 091:607 JLINK_ReadReg(R15 (PC)) returns 0x20000000 (0000ms, 27950ms total) +T3170 091:607 JLINK_ClrBPEx(BPHandle = 0x0000004D) returns 0x00 (0000ms, 27950ms total) +T3170 091:607 JLINK_ReadReg(R0) returns 0x00000000 (0000ms, 27950ms total) +T3170 091:607 JLINK_WriteMem(0x20000144, 0x0080 Bytes, ...) - Data: 01 F1 30 00 07 21 FF F7 2F FB 21 68 01 F1 38 00 ... -- CPU_WriteMem(128 bytes @ 0x20000144) returns 0x80 (0004ms, 27954ms total) +T3170 091:611 JLINK_WriteReg(R0, 0x00001F00) returns 0x00 (0000ms, 27954ms total) +T3170 091:611 JLINK_WriteReg(R1, 0x00000080) returns 0x00 (0000ms, 27954ms total) +T3170 091:611 JLINK_WriteReg(R2, 0x20000144) returns 0x00 (0000ms, 27954ms total) +T3170 091:611 JLINK_WriteReg(R3, 0x00000000) returns 0x00 (0000ms, 27954ms total) +T3170 091:611 JLINK_WriteReg(R4, 0x00000000) returns 0x00 (0000ms, 27954ms total) +T3170 091:611 JLINK_WriteReg(R5, 0x00000000) returns 0x00 (0000ms, 27954ms total) +T3170 091:611 JLINK_WriteReg(R6, 0x00000000) returns 0x00 (0000ms, 27954ms total) +T3170 091:611 JLINK_WriteReg(R7, 0x00000000) returns 0x00 (0000ms, 27954ms total) +T3170 091:611 JLINK_WriteReg(R8, 0x00000000) returns 0x00 (0000ms, 27954ms total) +T3170 091:611 JLINK_WriteReg(R9, 0x2000013C) returns 0x00 (0000ms, 27954ms total) +T3170 091:611 JLINK_WriteReg(R10, 0x00000000) returns 0x00 (0000ms, 27954ms total) +T3170 091:611 JLINK_WriteReg(R11, 0x00000000) returns 0x00 (0000ms, 27954ms total) +T3170 091:611 JLINK_WriteReg(R12, 0x00000000) returns 0x00 (0000ms, 27954ms total) +T3170 091:611 JLINK_WriteReg(R13 (SP), 0x20001000) returns 0x00 (0000ms, 27954ms total) +T3170 091:611 JLINK_WriteReg(R14, 0x20000001) returns 0x00 (0000ms, 27954ms total) +T3170 091:611 JLINK_WriteReg(R15 (PC), 0x2000005C) returns 0x00 (0000ms, 27954ms total) +T3170 091:611 JLINK_WriteReg(XPSR, 0x01000000) returns 0x00 (0000ms, 27954ms total) +T3170 091:611 JLINK_WriteReg(MSP, 0x20001000) returns 0x00 (0000ms, 27954ms total) +T3170 091:611 JLINK_WriteReg(PSP, 0x20001000) returns 0x00 (0000ms, 27954ms total) +T3170 091:611 JLINK_WriteReg(CFBP, 0x00000000) returns 0x00 (0000ms, 27954ms total) +T3170 091:611 JLINK_SetBPEx(Addr = 0x20000000, Type = 0xFFFFFFF2) returns 0x0000004E (0000ms, 27954ms total) +T3170 091:611 JLINK_Go() -- CPU_ReadMem(4 bytes @ 0xE0001000) (0063ms, 28017ms total) +T3170 091:674 JLINK_IsHalted() -- CPU_ReadMem(2 bytes @ 0x20000000) returns TRUE (0032ms, 28049ms total) +T3170 091:706 JLINK_ReadReg(R15 (PC)) returns 0x20000000 (0000ms, 28017ms total) +T3170 091:706 JLINK_ClrBPEx(BPHandle = 0x0000004E) returns 0x00 (0000ms, 28017ms total) +T3170 091:706 JLINK_ReadReg(R0) returns 0x00000000 (0000ms, 28017ms total) +T3170 091:706 JLINK_WriteMem(0x20000144, 0x0080 Bytes, ...) - Data: 00 00 00 00 28 74 68 69 73 5F 75 61 72 74 20 3D ... -- CPU_WriteMem(128 bytes @ 0x20000144) returns 0x80 (0004ms, 28021ms total) +T3170 091:710 JLINK_WriteReg(R0, 0x00001F80) returns 0x00 (0000ms, 28021ms total) +T3170 091:710 JLINK_WriteReg(R1, 0x00000080) returns 0x00 (0000ms, 28021ms total) +T3170 091:710 JLINK_WriteReg(R2, 0x20000144) returns 0x00 (0000ms, 28021ms total) +T3170 091:710 JLINK_WriteReg(R3, 0x00000000) returns 0x00 (0000ms, 28021ms total) +T3170 091:710 JLINK_WriteReg(R4, 0x00000000) returns 0x00 (0000ms, 28021ms total) +T3170 091:710 JLINK_WriteReg(R5, 0x00000000) returns 0x00 (0000ms, 28021ms total) +T3170 091:710 JLINK_WriteReg(R6, 0x00000000) returns 0x00 (0000ms, 28021ms total) +T3170 091:710 JLINK_WriteReg(R7, 0x00000000) returns 0x00 (0000ms, 28021ms total) +T3170 091:710 JLINK_WriteReg(R8, 0x00000000) returns 0x00 (0000ms, 28021ms total) +T3170 091:710 JLINK_WriteReg(R9, 0x2000013C) returns 0x00 (0000ms, 28021ms total) +T3170 091:710 JLINK_WriteReg(R10, 0x00000000) returns 0x00 (0000ms, 28021ms total) +T3170 091:710 JLINK_WriteReg(R11, 0x00000000) returns 0x00 (0000ms, 28021ms total) +T3170 091:710 JLINK_WriteReg(R12, 0x00000000) returns 0x00 (0000ms, 28021ms total) +T3170 091:710 JLINK_WriteReg(R13 (SP), 0x20001000) returns 0x00 (0000ms, 28021ms total) +T3170 091:710 JLINK_WriteReg(R14, 0x20000001) returns 0x00 (0000ms, 28021ms total) +T3170 091:710 JLINK_WriteReg(R15 (PC), 0x2000005C) returns 0x00 (0000ms, 28021ms total) +T3170 091:710 JLINK_WriteReg(XPSR, 0x01000000) returns 0x00 (0000ms, 28021ms total) +T3170 091:710 JLINK_WriteReg(MSP, 0x20001000) returns 0x00 (0000ms, 28021ms total) +T3170 091:710 JLINK_WriteReg(PSP, 0x20001000) returns 0x00 (0000ms, 28021ms total) +T3170 091:710 JLINK_WriteReg(CFBP, 0x00000000) returns 0x00 (0000ms, 28021ms total) +T3170 091:710 JLINK_SetBPEx(Addr = 0x20000000, Type = 0xFFFFFFF2) returns 0x0000004F (0000ms, 28021ms total) +T3170 091:710 JLINK_Go() -- CPU_ReadMem(4 bytes @ 0xE0001000) (0089ms, 28110ms total) +T3170 091:799 JLINK_IsHalted() -- CPU_ReadMem(2 bytes @ 0x20000000) returns TRUE (0009ms, 28119ms total) +T3170 091:808 JLINK_ReadReg(R15 (PC)) returns 0x20000000 (0000ms, 28110ms total) +T3170 091:808 JLINK_ClrBPEx(BPHandle = 0x0000004F) returns 0x00 (0000ms, 28110ms total) +T3170 091:808 JLINK_ReadReg(R0) returns 0x00000000 (0000ms, 28110ms total) +T3170 091:808 JLINK_WriteMem(0x20000144, 0x0080 Bytes, ...) - Data: 00 88 08 B1 02 F0 BA FD 04 48 00 68 00 F0 00 40 ... -- CPU_WriteMem(128 bytes @ 0x20000144) returns 0x80 (0003ms, 28113ms total) +T3170 091:811 JLINK_WriteReg(R0, 0x00002000) returns 0x00 (0000ms, 28113ms total) +T3170 091:811 JLINK_WriteReg(R1, 0x00000080) returns 0x00 (0000ms, 28113ms total) +T3170 091:811 JLINK_WriteReg(R2, 0x20000144) returns 0x00 (0000ms, 28113ms total) +T3170 091:811 JLINK_WriteReg(R3, 0x00000000) returns 0x00 (0000ms, 28113ms total) +T3170 091:811 JLINK_WriteReg(R4, 0x00000000) returns 0x00 (0000ms, 28113ms total) +T3170 091:811 JLINK_WriteReg(R5, 0x00000000) returns 0x00 (0000ms, 28113ms total) +T3170 091:811 JLINK_WriteReg(R6, 0x00000000) returns 0x00 (0000ms, 28113ms total) +T3170 091:811 JLINK_WriteReg(R7, 0x00000000) returns 0x00 (0000ms, 28113ms total) +T3170 091:811 JLINK_WriteReg(R8, 0x00000000) returns 0x00 (0000ms, 28113ms total) +T3170 091:811 JLINK_WriteReg(R9, 0x2000013C) returns 0x00 (0000ms, 28113ms total) +T3170 091:811 JLINK_WriteReg(R10, 0x00000000) returns 0x00 (0000ms, 28113ms total) +T3170 091:811 JLINK_WriteReg(R11, 0x00000000) returns 0x00 (0000ms, 28113ms total) +T3170 091:811 JLINK_WriteReg(R12, 0x00000000) returns 0x00 (0000ms, 28113ms total) +T3170 091:811 JLINK_WriteReg(R13 (SP), 0x20001000) returns 0x00 (0000ms, 28113ms total) +T3170 091:811 JLINK_WriteReg(R14, 0x20000001) returns 0x00 (0000ms, 28113ms total) +T3170 091:811 JLINK_WriteReg(R15 (PC), 0x2000005C) returns 0x00 (0000ms, 28113ms total) +T3170 091:811 JLINK_WriteReg(XPSR, 0x01000000) returns 0x00 (0000ms, 28113ms total) +T3170 091:811 JLINK_WriteReg(MSP, 0x20001000) returns 0x00 (0000ms, 28113ms total) +T3170 091:811 JLINK_WriteReg(PSP, 0x20001000) returns 0x00 (0000ms, 28113ms total) +T3170 091:811 JLINK_WriteReg(CFBP, 0x00000000) returns 0x00 (0000ms, 28113ms total) +T3170 091:811 JLINK_SetBPEx(Addr = 0x20000000, Type = 0xFFFFFFF2) returns 0x00000050 (0000ms, 28113ms total) +T3170 091:811 JLINK_Go() -- CPU_ReadMem(4 bytes @ 0xE0001000) (0088ms, 28201ms total) +T3170 091:899 JLINK_IsHalted() -- CPU_ReadMem(2 bytes @ 0x20000000) returns TRUE (0009ms, 28210ms total) +T3170 091:908 JLINK_ReadReg(R15 (PC)) returns 0x20000000 (0000ms, 28201ms total) +T3170 091:908 JLINK_ClrBPEx(BPHandle = 0x00000050) returns 0x00 (0000ms, 28201ms total) +T3170 091:908 JLINK_ReadReg(R0) returns 0x00000000 (0000ms, 28201ms total) +T3170 091:908 JLINK_WriteMem(0x20000144, 0x0080 Bytes, ...) - Data: 00 B9 04 E0 0C A0 21 68 01 F0 6A FB 00 BF 08 34 ... -- CPU_WriteMem(128 bytes @ 0x20000144) returns 0x80 (0004ms, 28205ms total) +T3170 091:912 JLINK_WriteReg(R0, 0x00002080) returns 0x00 (0000ms, 28205ms total) +T3170 091:912 JLINK_WriteReg(R1, 0x00000080) returns 0x00 (0000ms, 28205ms total) +T3170 091:912 JLINK_WriteReg(R2, 0x20000144) returns 0x00 (0000ms, 28205ms total) +T3170 091:912 JLINK_WriteReg(R3, 0x00000000) returns 0x00 (0000ms, 28205ms total) +T3170 091:912 JLINK_WriteReg(R4, 0x00000000) returns 0x00 (0000ms, 28205ms total) +T3170 091:912 JLINK_WriteReg(R5, 0x00000000) returns 0x00 (0000ms, 28205ms total) +T3170 091:912 JLINK_WriteReg(R6, 0x00000000) returns 0x00 (0000ms, 28205ms total) +T3170 091:912 JLINK_WriteReg(R7, 0x00000000) returns 0x00 (0000ms, 28205ms total) +T3170 091:912 JLINK_WriteReg(R8, 0x00000000) returns 0x00 (0000ms, 28205ms total) +T3170 091:912 JLINK_WriteReg(R9, 0x2000013C) returns 0x00 (0000ms, 28205ms total) +T3170 091:912 JLINK_WriteReg(R10, 0x00000000) returns 0x00 (0000ms, 28205ms total) +T3170 091:912 JLINK_WriteReg(R11, 0x00000000) returns 0x00 (0000ms, 28205ms total) +T3170 091:912 JLINK_WriteReg(R12, 0x00000000) returns 0x00 (0000ms, 28205ms total) +T3170 091:912 JLINK_WriteReg(R13 (SP), 0x20001000) returns 0x00 (0000ms, 28205ms total) +T3170 091:912 JLINK_WriteReg(R14, 0x20000001) returns 0x00 (0000ms, 28205ms total) +T3170 091:912 JLINK_WriteReg(R15 (PC), 0x2000005C) returns 0x00 (0000ms, 28205ms total) +T3170 091:912 JLINK_WriteReg(XPSR, 0x01000000) returns 0x00 (0000ms, 28205ms total) +T3170 091:912 JLINK_WriteReg(MSP, 0x20001000) returns 0x00 (0000ms, 28205ms total) +T3170 091:912 JLINK_WriteReg(PSP, 0x20001000) returns 0x00 (0000ms, 28205ms total) +T3170 091:912 JLINK_WriteReg(CFBP, 0x00000000) returns 0x00 (0000ms, 28205ms total) +T3170 091:912 JLINK_SetBPEx(Addr = 0x20000000, Type = 0xFFFFFFF2) returns 0x00000051 (0000ms, 28205ms total) +T3170 091:912 JLINK_Go() -- CPU_ReadMem(4 bytes @ 0xE0001000) (0087ms, 28292ms total) +T3170 091:999 JLINK_IsHalted() -- CPU_ReadMem(2 bytes @ 0x20000000) returns TRUE (0008ms, 28300ms total) +T3170 092:007 JLINK_ReadReg(R15 (PC)) returns 0x20000000 (0000ms, 28292ms total) +T3170 092:007 JLINK_ClrBPEx(BPHandle = 0x00000051) returns 0x00 (0000ms, 28292ms total) +T3170 092:007 JLINK_ReadReg(R0) returns 0x00000000 (0000ms, 28292ms total) +T3170 092:007 JLINK_WriteMem(0x20000144, 0x0080 Bytes, ...) - Data: 3B E0 02 A8 50 F8 25 00 A0 F1 0C 06 FE F7 2C F9 ... -- CPU_WriteMem(128 bytes @ 0x20000144) returns 0x80 (0003ms, 28295ms total) +T3170 092:010 JLINK_WriteReg(R0, 0x00002100) returns 0x00 (0000ms, 28295ms total) +T3170 092:010 JLINK_WriteReg(R1, 0x00000080) returns 0x00 (0000ms, 28295ms total) +T3170 092:010 JLINK_WriteReg(R2, 0x20000144) returns 0x00 (0000ms, 28295ms total) +T3170 092:010 JLINK_WriteReg(R3, 0x00000000) returns 0x00 (0000ms, 28295ms total) +T3170 092:010 JLINK_WriteReg(R4, 0x00000000) returns 0x00 (0000ms, 28295ms total) +T3170 092:010 JLINK_WriteReg(R5, 0x00000000) returns 0x00 (0000ms, 28295ms total) +T3170 092:010 JLINK_WriteReg(R6, 0x00000000) returns 0x00 (0000ms, 28295ms total) +T3170 092:010 JLINK_WriteReg(R7, 0x00000000) returns 0x00 (0000ms, 28295ms total) +T3170 092:010 JLINK_WriteReg(R8, 0x00000000) returns 0x00 (0000ms, 28295ms total) +T3170 092:010 JLINK_WriteReg(R9, 0x2000013C) returns 0x00 (0000ms, 28295ms total) +T3170 092:010 JLINK_WriteReg(R10, 0x00000000) returns 0x00 (0000ms, 28295ms total) +T3170 092:010 JLINK_WriteReg(R11, 0x00000000) returns 0x00 (0000ms, 28295ms total) +T3170 092:010 JLINK_WriteReg(R12, 0x00000000) returns 0x00 (0000ms, 28295ms total) +T3170 092:010 JLINK_WriteReg(R13 (SP), 0x20001000) returns 0x00 (0000ms, 28295ms total) +T3170 092:010 JLINK_WriteReg(R14, 0x20000001) returns 0x00 (0000ms, 28295ms total) +T3170 092:010 JLINK_WriteReg(R15 (PC), 0x2000005C) returns 0x00 (0000ms, 28295ms total) +T3170 092:010 JLINK_WriteReg(XPSR, 0x01000000) returns 0x00 (0000ms, 28295ms total) +T3170 092:010 JLINK_WriteReg(MSP, 0x20001000) returns 0x00 (0000ms, 28295ms total) +T3170 092:010 JLINK_WriteReg(PSP, 0x20001000) returns 0x00 (0000ms, 28295ms total) +T3170 092:010 JLINK_WriteReg(CFBP, 0x00000000) returns 0x00 (0000ms, 28295ms total) +T3170 092:010 JLINK_SetBPEx(Addr = 0x20000000, Type = 0xFFFFFFF2) returns 0x00000052 (0000ms, 28295ms total) +T3170 092:010 JLINK_Go() -- CPU_ReadMem(4 bytes @ 0xE0001000) (0089ms, 28384ms total) +T3170 092:099 JLINK_IsHalted() -- CPU_ReadMem(2 bytes @ 0x20000000) returns TRUE (0009ms, 28393ms total) +T3170 092:108 JLINK_ReadReg(R15 (PC)) returns 0x20000000 (0000ms, 28384ms total) +T3170 092:108 JLINK_ClrBPEx(BPHandle = 0x00000052) returns 0x00 (0000ms, 28384ms total) +T3170 092:108 JLINK_ReadReg(R0) returns 0x00000000 (0000ms, 28384ms total) +T3170 092:109 JLINK_WriteMem(0x20000144, 0x0080 Bytes, ...) - Data: 00 2F B7 D1 00 20 0F B0 BD E8 F0 8F 65 76 65 6E ... -- CPU_WriteMem(128 bytes @ 0x20000144) returns 0x80 (0003ms, 28387ms total) +T3170 092:112 JLINK_WriteReg(R0, 0x00002180) returns 0x00 (0000ms, 28387ms total) +T3170 092:112 JLINK_WriteReg(R1, 0x00000080) returns 0x00 (0000ms, 28387ms total) +T3170 092:112 JLINK_WriteReg(R2, 0x20000144) returns 0x00 (0000ms, 28387ms total) +T3170 092:112 JLINK_WriteReg(R3, 0x00000000) returns 0x00 (0000ms, 28387ms total) +T3170 092:112 JLINK_WriteReg(R4, 0x00000000) returns 0x00 (0000ms, 28387ms total) +T3170 092:112 JLINK_WriteReg(R5, 0x00000000) returns 0x00 (0000ms, 28387ms total) +T3170 092:112 JLINK_WriteReg(R6, 0x00000000) returns 0x00 (0000ms, 28387ms total) +T3170 092:112 JLINK_WriteReg(R7, 0x00000000) returns 0x00 (0000ms, 28387ms total) +T3170 092:112 JLINK_WriteReg(R8, 0x00000000) returns 0x00 (0000ms, 28387ms total) +T3170 092:112 JLINK_WriteReg(R9, 0x2000013C) returns 0x00 (0000ms, 28387ms total) +T3170 092:112 JLINK_WriteReg(R10, 0x00000000) returns 0x00 (0000ms, 28387ms total) +T3170 092:112 JLINK_WriteReg(R11, 0x00000000) returns 0x00 (0000ms, 28387ms total) +T3170 092:112 JLINK_WriteReg(R12, 0x00000000) returns 0x00 (0000ms, 28387ms total) +T3170 092:112 JLINK_WriteReg(R13 (SP), 0x20001000) returns 0x00 (0000ms, 28387ms total) +T3170 092:112 JLINK_WriteReg(R14, 0x20000001) returns 0x00 (0000ms, 28387ms total) +T3170 092:112 JLINK_WriteReg(R15 (PC), 0x2000005C) returns 0x00 (0000ms, 28387ms total) +T3170 092:112 JLINK_WriteReg(XPSR, 0x01000000) returns 0x00 (0000ms, 28387ms total) +T3170 092:112 JLINK_WriteReg(MSP, 0x20001000) returns 0x00 (0000ms, 28387ms total) +T3170 092:112 JLINK_WriteReg(PSP, 0x20001000) returns 0x00 (0000ms, 28387ms total) +T3170 092:112 JLINK_WriteReg(CFBP, 0x00000000) returns 0x00 (0000ms, 28387ms total) +T3170 092:112 JLINK_SetBPEx(Addr = 0x20000000, Type = 0xFFFFFFF2) returns 0x00000053 (0000ms, 28387ms total) +T3170 092:113 JLINK_Go() -- CPU_ReadMem(4 bytes @ 0xE0001000) (0086ms, 28473ms total) +T3170 092:199 JLINK_IsHalted() -- CPU_ReadMem(2 bytes @ 0x20000000) returns TRUE (0006ms, 28479ms total) +T3170 092:205 JLINK_ReadReg(R15 (PC)) returns 0x20000000 (0001ms, 28474ms total) +T3170 092:206 JLINK_ClrBPEx(BPHandle = 0x00000053) returns 0x00 (0000ms, 28474ms total) +T3170 092:206 JLINK_ReadReg(R0) returns 0x00000000 (0000ms, 28474ms total) +T3170 092:206 JLINK_WriteMem(0x20000144, 0x0080 Bytes, ...) - Data: 0A 00 00 00 2D E9 F0 47 04 46 0D 46 16 46 1F 46 ... -- CPU_WriteMem(128 bytes @ 0x20000144) returns 0x80 (0003ms, 28477ms total) +T3170 092:209 JLINK_WriteReg(R0, 0x00002200) returns 0x00 (0000ms, 28477ms total) +T3170 092:209 JLINK_WriteReg(R1, 0x00000080) returns 0x00 (0000ms, 28477ms total) +T3170 092:209 JLINK_WriteReg(R2, 0x20000144) returns 0x00 (0000ms, 28477ms total) +T3170 092:209 JLINK_WriteReg(R3, 0x00000000) returns 0x00 (0000ms, 28477ms total) +T3170 092:209 JLINK_WriteReg(R4, 0x00000000) returns 0x00 (0000ms, 28477ms total) +T3170 092:209 JLINK_WriteReg(R5, 0x00000000) returns 0x00 (0000ms, 28477ms total) +T3170 092:209 JLINK_WriteReg(R6, 0x00000000) returns 0x00 (0000ms, 28477ms total) +T3170 092:209 JLINK_WriteReg(R7, 0x00000000) returns 0x00 (0000ms, 28477ms total) +T3170 092:209 JLINK_WriteReg(R8, 0x00000000) returns 0x00 (0000ms, 28477ms total) +T3170 092:209 JLINK_WriteReg(R9, 0x2000013C) returns 0x00 (0000ms, 28477ms total) +T3170 092:209 JLINK_WriteReg(R10, 0x00000000) returns 0x00 (0000ms, 28477ms total) +T3170 092:209 JLINK_WriteReg(R11, 0x00000000) returns 0x00 (0000ms, 28477ms total) +T3170 092:209 JLINK_WriteReg(R12, 0x00000000) returns 0x00 (0000ms, 28477ms total) +T3170 092:209 JLINK_WriteReg(R13 (SP), 0x20001000) returns 0x00 (0000ms, 28477ms total) +T3170 092:209 JLINK_WriteReg(R14, 0x20000001) returns 0x00 (0000ms, 28477ms total) +T3170 092:209 JLINK_WriteReg(R15 (PC), 0x2000005C) returns 0x00 (0000ms, 28477ms total) +T3170 092:209 JLINK_WriteReg(XPSR, 0x01000000) returns 0x00 (0000ms, 28477ms total) +T3170 092:209 JLINK_WriteReg(MSP, 0x20001000) returns 0x00 (0000ms, 28477ms total) +T3170 092:209 JLINK_WriteReg(PSP, 0x20001000) returns 0x00 (0000ms, 28477ms total) +T3170 092:209 JLINK_WriteReg(CFBP, 0x00000000) returns 0x00 (0000ms, 28477ms total) +T3170 092:209 JLINK_SetBPEx(Addr = 0x20000000, Type = 0xFFFFFFF2) returns 0x00000054 (0000ms, 28477ms total) +T3170 092:209 JLINK_Go() -- CPU_ReadMem(4 bytes @ 0xE0001000) (0090ms, 28567ms total) +T3170 092:299 JLINK_IsHalted() -- CPU_ReadMem(2 bytes @ 0x20000000) returns TRUE (0010ms, 28577ms total) +T3170 092:309 JLINK_ReadReg(R15 (PC)) returns 0x20000000 (0000ms, 28567ms total) +T3170 092:309 JLINK_ClrBPEx(BPHandle = 0x00000054) returns 0x00 (0000ms, 28567ms total) +T3170 092:309 JLINK_ReadReg(R0) returns 0x00000000 (0000ms, 28567ms total) +T3170 092:309 JLINK_WriteMem(0x20000144, 0x0080 Bytes, ...) - Data: 00 20 E1 E7 00 BF 00 26 D4 F8 04 90 0B E0 2D 68 ... -- CPU_WriteMem(128 bytes @ 0x20000144) returns 0x80 (0003ms, 28570ms total) +T3170 092:312 JLINK_WriteReg(R0, 0x00002280) returns 0x00 (0001ms, 28571ms total) +T3170 092:313 JLINK_WriteReg(R1, 0x00000080) returns 0x00 (0000ms, 28571ms total) +T3170 092:313 JLINK_WriteReg(R2, 0x20000144) returns 0x00 (0000ms, 28571ms total) +T3170 092:313 JLINK_WriteReg(R3, 0x00000000) returns 0x00 (0000ms, 28571ms total) +T3170 092:313 JLINK_WriteReg(R4, 0x00000000) returns 0x00 (0000ms, 28571ms total) +T3170 092:313 JLINK_WriteReg(R5, 0x00000000) returns 0x00 (0000ms, 28571ms total) +T3170 092:313 JLINK_WriteReg(R6, 0x00000000) returns 0x00 (0000ms, 28571ms total) +T3170 092:313 JLINK_WriteReg(R7, 0x00000000) returns 0x00 (0000ms, 28571ms total) +T3170 092:313 JLINK_WriteReg(R8, 0x00000000) returns 0x00 (0000ms, 28571ms total) +T3170 092:313 JLINK_WriteReg(R9, 0x2000013C) returns 0x00 (0000ms, 28571ms total) +T3170 092:313 JLINK_WriteReg(R10, 0x00000000) returns 0x00 (0000ms, 28571ms total) +T3170 092:313 JLINK_WriteReg(R11, 0x00000000) returns 0x00 (0000ms, 28571ms total) +T3170 092:313 JLINK_WriteReg(R12, 0x00000000) returns 0x00 (0000ms, 28571ms total) +T3170 092:313 JLINK_WriteReg(R13 (SP), 0x20001000) returns 0x00 (0000ms, 28571ms total) +T3170 092:313 JLINK_WriteReg(R14, 0x20000001) returns 0x00 (0000ms, 28571ms total) +T3170 092:313 JLINK_WriteReg(R15 (PC), 0x2000005C) returns 0x00 (0000ms, 28571ms total) +T3170 092:313 JLINK_WriteReg(XPSR, 0x01000000) returns 0x00 (0000ms, 28571ms total) +T3170 092:313 JLINK_WriteReg(MSP, 0x20001000) returns 0x00 (0000ms, 28571ms total) +T3170 092:313 JLINK_WriteReg(PSP, 0x20001000) returns 0x00 (0000ms, 28571ms total) +T3170 092:313 JLINK_WriteReg(CFBP, 0x00000000) returns 0x00 (0000ms, 28571ms total) +T3170 092:313 JLINK_SetBPEx(Addr = 0x20000000, Type = 0xFFFFFFF2) returns 0x00000055 (0000ms, 28571ms total) +T3170 092:313 JLINK_Go() -- CPU_ReadMem(4 bytes @ 0xE0001000) (0090ms, 28661ms total) +T3170 092:403 JLINK_IsHalted() -- CPU_ReadMem(2 bytes @ 0x20000000) returns TRUE (0009ms, 28670ms total) +T3170 092:413 JLINK_ReadReg(R15 (PC)) returns 0x20000000 (0000ms, 28670ms total) +T3170 092:413 JLINK_ClrBPEx(BPHandle = 0x00000055) returns 0x00 (0000ms, 28670ms total) +T3170 092:413 JLINK_ReadReg(R0) returns 0x00000000 (0000ms, 28670ms total) +T3170 092:413 JLINK_WriteMem(0x20000144, 0x0080 Bytes, ...) - Data: A0 F1 0C 06 FE F7 30 F8 83 46 30 7A 20 F0 80 00 ... -- CPU_WriteMem(128 bytes @ 0x20000144) returns 0x80 (0003ms, 28673ms total) +T3170 092:416 JLINK_WriteReg(R0, 0x00002300) returns 0x00 (0000ms, 28673ms total) +T3170 092:416 JLINK_WriteReg(R1, 0x00000080) returns 0x00 (0000ms, 28673ms total) +T3170 092:416 JLINK_WriteReg(R2, 0x20000144) returns 0x00 (0000ms, 28673ms total) +T3170 092:416 JLINK_WriteReg(R3, 0x00000000) returns 0x00 (0000ms, 28673ms total) +T3170 092:416 JLINK_WriteReg(R4, 0x00000000) returns 0x00 (0000ms, 28673ms total) +T3170 092:416 JLINK_WriteReg(R5, 0x00000000) returns 0x00 (0000ms, 28673ms total) +T3170 092:416 JLINK_WriteReg(R6, 0x00000000) returns 0x00 (0000ms, 28673ms total) +T3170 092:416 JLINK_WriteReg(R7, 0x00000000) returns 0x00 (0000ms, 28673ms total) +T3170 092:416 JLINK_WriteReg(R8, 0x00000000) returns 0x00 (0000ms, 28673ms total) +T3170 092:416 JLINK_WriteReg(R9, 0x2000013C) returns 0x00 (0000ms, 28673ms total) +T3170 092:416 JLINK_WriteReg(R10, 0x00000000) returns 0x00 (0000ms, 28673ms total) +T3170 092:416 JLINK_WriteReg(R11, 0x00000000) returns 0x00 (0000ms, 28673ms total) +T3170 092:416 JLINK_WriteReg(R12, 0x00000000) returns 0x00 (0000ms, 28673ms total) +T3170 092:416 JLINK_WriteReg(R13 (SP), 0x20001000) returns 0x00 (0000ms, 28673ms total) +T3170 092:416 JLINK_WriteReg(R14, 0x20000001) returns 0x00 (0000ms, 28673ms total) +T3170 092:416 JLINK_WriteReg(R15 (PC), 0x2000005C) returns 0x00 (0000ms, 28673ms total) +T3170 092:416 JLINK_WriteReg(XPSR, 0x01000000) returns 0x00 (0000ms, 28673ms total) +T3170 092:417 JLINK_WriteReg(MSP, 0x20001000) returns 0x00 (0000ms, 28673ms total) +T3170 092:417 JLINK_WriteReg(PSP, 0x20001000) returns 0x00 (0000ms, 28673ms total) +T3170 092:417 JLINK_WriteReg(CFBP, 0x00000000) returns 0x00 (0000ms, 28673ms total) +T3170 092:417 JLINK_SetBPEx(Addr = 0x20000000, Type = 0xFFFFFFF2) returns 0x00000056 (0000ms, 28673ms total) +T3170 092:417 JLINK_Go() -- CPU_ReadMem(4 bytes @ 0xE0001000) (0087ms, 28760ms total) +T3170 092:504 JLINK_IsHalted() -- CPU_ReadMem(2 bytes @ 0x20000000) returns TRUE (0010ms, 28770ms total) +T3170 092:514 JLINK_ReadReg(R15 (PC)) returns 0x20000000 (0000ms, 28760ms total) +T3170 092:514 JLINK_ClrBPEx(BPHandle = 0x00000056) returns 0x00 (0000ms, 28760ms total) +T3170 092:514 JLINK_ReadReg(R0) returns 0x00000000 (0001ms, 28761ms total) +T3170 092:515 JLINK_WriteMem(0x20000144, 0x0080 Bytes, ...) - Data: EF F9 00 BF 6D 1C 10 98 A8 42 B6 DC 00 2F AD D1 ... -- CPU_WriteMem(128 bytes @ 0x20000144) returns 0x80 (0061ms, 28822ms total) +T3170 092:576 JLINK_WriteReg(R0, 0x00002380) returns 0x00 (0000ms, 28822ms total) +T3170 092:576 JLINK_WriteReg(R1, 0x00000080) returns 0x00 (0000ms, 28822ms total) +T3170 092:576 JLINK_WriteReg(R2, 0x20000144) returns 0x00 (0000ms, 28822ms total) +T3170 092:576 JLINK_WriteReg(R3, 0x00000000) returns 0x00 (0000ms, 28822ms total) +T3170 092:576 JLINK_WriteReg(R4, 0x00000000) returns 0x00 (0000ms, 28822ms total) +T3170 092:576 JLINK_WriteReg(R5, 0x00000000) returns 0x00 (0000ms, 28822ms total) +T3170 092:576 JLINK_WriteReg(R6, 0x00000000) returns 0x00 (0000ms, 28822ms total) +T3170 092:576 JLINK_WriteReg(R7, 0x00000000) returns 0x00 (0000ms, 28822ms total) +T3170 092:576 JLINK_WriteReg(R8, 0x00000000) returns 0x00 (0000ms, 28822ms total) +T3170 092:576 JLINK_WriteReg(R9, 0x2000013C) returns 0x00 (0000ms, 28822ms total) +T3170 092:576 JLINK_WriteReg(R10, 0x00000000) returns 0x00 (0000ms, 28822ms total) +T3170 092:576 JLINK_WriteReg(R11, 0x00000000) returns 0x00 (0000ms, 28822ms total) +T3170 092:576 JLINK_WriteReg(R12, 0x00000000) returns 0x00 (0000ms, 28822ms total) +T3170 092:576 JLINK_WriteReg(R13 (SP), 0x20001000) returns 0x00 (0000ms, 28822ms total) +T3170 092:576 JLINK_WriteReg(R14, 0x20000001) returns 0x00 (0000ms, 28822ms total) +T3170 092:576 JLINK_WriteReg(R15 (PC), 0x2000005C) returns 0x00 (0000ms, 28822ms total) +T3170 092:576 JLINK_WriteReg(XPSR, 0x01000000) returns 0x00 (0000ms, 28822ms total) +T3170 092:576 JLINK_WriteReg(MSP, 0x20001000) returns 0x00 (0000ms, 28822ms total) +T3170 092:576 JLINK_WriteReg(PSP, 0x20001000) returns 0x00 (0000ms, 28822ms total) +T3170 092:576 JLINK_WriteReg(CFBP, 0x00000000) returns 0x00 (0000ms, 28822ms total) +T3170 092:576 JLINK_SetBPEx(Addr = 0x20000000, Type = 0xFFFFFFF2) returns 0x00000057 (0000ms, 28822ms total) +T3170 092:576 JLINK_Go() -- CPU_ReadMem(4 bytes @ 0xE0001000) (0028ms, 28850ms total) +T3170 092:604 JLINK_IsHalted() -- CPU_ReadMem(2 bytes @ 0x20000000) returns TRUE (0008ms, 28858ms total) +T3170 092:612 JLINK_ReadReg(R15 (PC)) returns 0x20000000 (0000ms, 28850ms total) +T3170 092:612 JLINK_ClrBPEx(BPHandle = 0x00000057) returns 0x00 (0000ms, 28850ms total) +T3170 092:612 JLINK_ReadReg(R0) returns 0x00000000 (0000ms, 28850ms total) +T3170 092:612 JLINK_WriteMem(0x20000144, 0x0080 Bytes, ...) - Data: 2A 73 20 25 30 34 64 20 20 25 30 34 64 20 25 64 ... -- CPU_WriteMem(128 bytes @ 0x20000144) returns 0x80 (0003ms, 28853ms total) +T3170 092:615 JLINK_WriteReg(R0, 0x00002400) returns 0x00 (0000ms, 28853ms total) +T3170 092:615 JLINK_WriteReg(R1, 0x00000080) returns 0x00 (0000ms, 28853ms total) +T3170 092:615 JLINK_WriteReg(R2, 0x20000144) returns 0x00 (0000ms, 28853ms total) +T3170 092:615 JLINK_WriteReg(R3, 0x00000000) returns 0x00 (0000ms, 28853ms total) +T3170 092:615 JLINK_WriteReg(R4, 0x00000000) returns 0x00 (0000ms, 28853ms total) +T3170 092:615 JLINK_WriteReg(R5, 0x00000000) returns 0x00 (0000ms, 28853ms total) +T3170 092:615 JLINK_WriteReg(R6, 0x00000000) returns 0x00 (0000ms, 28853ms total) +T3170 092:615 JLINK_WriteReg(R7, 0x00000000) returns 0x00 (0000ms, 28853ms total) +T3170 092:615 JLINK_WriteReg(R8, 0x00000000) returns 0x00 (0000ms, 28853ms total) +T3170 092:615 JLINK_WriteReg(R9, 0x2000013C) returns 0x00 (0000ms, 28853ms total) +T3170 092:615 JLINK_WriteReg(R10, 0x00000000) returns 0x00 (0000ms, 28853ms total) +T3170 092:615 JLINK_WriteReg(R11, 0x00000000) returns 0x00 (0000ms, 28853ms total) +T3170 092:615 JLINK_WriteReg(R12, 0x00000000) returns 0x00 (0000ms, 28853ms total) +T3170 092:615 JLINK_WriteReg(R13 (SP), 0x20001000) returns 0x00 (0000ms, 28853ms total) +T3170 092:615 JLINK_WriteReg(R14, 0x20000001) returns 0x00 (0000ms, 28853ms total) +T3170 092:615 JLINK_WriteReg(R15 (PC), 0x2000005C) returns 0x00 (0000ms, 28853ms total) +T3170 092:615 JLINK_WriteReg(XPSR, 0x01000000) returns 0x00 (0000ms, 28853ms total) +T3170 092:615 JLINK_WriteReg(MSP, 0x20001000) returns 0x00 (0000ms, 28853ms total) +T3170 092:615 JLINK_WriteReg(PSP, 0x20001000) returns 0x00 (0000ms, 28853ms total) +T3170 092:615 JLINK_WriteReg(CFBP, 0x00000000) returns 0x00 (0000ms, 28853ms total) +T3170 092:615 JLINK_SetBPEx(Addr = 0x20000000, Type = 0xFFFFFFF2) returns 0x00000058 (0000ms, 28853ms total) +T3170 092:615 JLINK_Go() -- CPU_ReadMem(4 bytes @ 0xE0001000) (0090ms, 28943ms total) +T3170 092:705 JLINK_IsHalted() -- CPU_ReadMem(2 bytes @ 0x20000000) returns TRUE (0011ms, 28954ms total) +T3170 092:716 JLINK_ReadReg(R15 (PC)) returns 0x20000000 (0000ms, 28943ms total) +T3170 092:716 JLINK_ClrBPEx(BPHandle = 0x00000058) returns 0x00 (0000ms, 28943ms total) +T3170 092:716 JLINK_ReadReg(R0) returns 0x00000000 (0000ms, 28943ms total) +T3170 092:716 JLINK_WriteMem(0x20000144, 0x0080 Bytes, ...) - Data: 6D 6F 72 79 3A 20 25 64 0A 00 00 00 2D E9 F0 4F ... -- CPU_WriteMem(128 bytes @ 0x20000144) returns 0x80 (0084ms, 29027ms total) +T3170 092:800 JLINK_WriteReg(R0, 0x00002480) returns 0x00 (0000ms, 29027ms total) +T3170 092:800 JLINK_WriteReg(R1, 0x00000080) returns 0x00 (0000ms, 29027ms total) +T3170 092:800 JLINK_WriteReg(R2, 0x20000144) returns 0x00 (0000ms, 29027ms total) +T3170 092:800 JLINK_WriteReg(R3, 0x00000000) returns 0x00 (0000ms, 29027ms total) +T3170 092:800 JLINK_WriteReg(R4, 0x00000000) returns 0x00 (0000ms, 29027ms total) +T3170 092:800 JLINK_WriteReg(R5, 0x00000000) returns 0x00 (0000ms, 29027ms total) +T3170 092:800 JLINK_WriteReg(R6, 0x00000000) returns 0x00 (0000ms, 29027ms total) +T3170 092:800 JLINK_WriteReg(R7, 0x00000000) returns 0x00 (0000ms, 29027ms total) +T3170 092:800 JLINK_WriteReg(R8, 0x00000000) returns 0x00 (0000ms, 29027ms total) +T3170 092:800 JLINK_WriteReg(R9, 0x2000013C) returns 0x00 (0000ms, 29027ms total) +T3170 092:801 JLINK_WriteReg(R10, 0x00000000) returns 0x00 (0000ms, 29027ms total) +T3170 092:801 JLINK_WriteReg(R11, 0x00000000) returns 0x00 (0000ms, 29027ms total) +T3170 092:801 JLINK_WriteReg(R12, 0x00000000) returns 0x00 (0000ms, 29027ms total) +T3170 092:801 JLINK_WriteReg(R13 (SP), 0x20001000) returns 0x00 (0000ms, 29027ms total) +T3170 092:801 JLINK_WriteReg(R14, 0x20000001) returns 0x00 (0000ms, 29027ms total) +T3170 092:801 JLINK_WriteReg(R15 (PC), 0x2000005C) returns 0x00 (0000ms, 29027ms total) +T3170 092:801 JLINK_WriteReg(XPSR, 0x01000000) returns 0x00 (0000ms, 29027ms total) +T3170 092:801 JLINK_WriteReg(MSP, 0x20001000) returns 0x00 (0000ms, 29027ms total) +T3170 092:801 JLINK_WriteReg(PSP, 0x20001000) returns 0x00 (0000ms, 29027ms total) +T3170 092:801 JLINK_WriteReg(CFBP, 0x00000000) returns 0x00 (0000ms, 29027ms total) +T3170 092:801 JLINK_SetBPEx(Addr = 0x20000000, Type = 0xFFFFFFF2) returns 0x00000059 (0000ms, 29027ms total) +T3170 092:801 JLINK_Go() -- CPU_ReadMem(4 bytes @ 0xE0001000) (0007ms, 29034ms total) +T3170 092:808 JLINK_IsHalted() -- CPU_ReadMem(2 bytes @ 0x20000000) returns TRUE (0091ms, 29125ms total) +T3170 092:899 JLINK_ReadReg(R15 (PC)) returns 0x20000000 (0000ms, 29034ms total) +T3170 092:899 JLINK_ClrBPEx(BPHandle = 0x00000059) returns 0x00 (0000ms, 29034ms total) +T3170 092:899 JLINK_ReadReg(R0) returns 0x00000000 (0000ms, 29034ms total) +T3170 092:899 JLINK_WriteMem(0x20000144, 0x0080 Bytes, ...) - Data: 01 F0 7B F9 A8 B9 04 F1 14 00 01 F0 7E F9 82 46 ... -- CPU_WriteMem(128 bytes @ 0x20000144) returns 0x80 (0004ms, 29038ms total) +T3170 092:903 JLINK_WriteReg(R0, 0x00002500) returns 0x00 (0000ms, 29038ms total) +T3170 092:903 JLINK_WriteReg(R1, 0x00000080) returns 0x00 (0000ms, 29038ms total) +T3170 092:903 JLINK_WriteReg(R2, 0x20000144) returns 0x00 (0000ms, 29038ms total) +T3170 092:903 JLINK_WriteReg(R3, 0x00000000) returns 0x00 (0000ms, 29038ms total) +T3170 092:903 JLINK_WriteReg(R4, 0x00000000) returns 0x00 (0000ms, 29038ms total) +T3170 092:903 JLINK_WriteReg(R5, 0x00000000) returns 0x00 (0000ms, 29038ms total) +T3170 092:903 JLINK_WriteReg(R6, 0x00000000) returns 0x00 (0000ms, 29038ms total) +T3170 092:903 JLINK_WriteReg(R7, 0x00000000) returns 0x00 (0000ms, 29038ms total) +T3170 092:903 JLINK_WriteReg(R8, 0x00000000) returns 0x00 (0000ms, 29038ms total) +T3170 092:903 JLINK_WriteReg(R9, 0x2000013C) returns 0x00 (0000ms, 29038ms total) +T3170 092:903 JLINK_WriteReg(R10, 0x00000000) returns 0x00 (0000ms, 29038ms total) +T3170 092:904 JLINK_WriteReg(R11, 0x00000000) returns 0x00 (0000ms, 29039ms total) +T3170 092:904 JLINK_WriteReg(R12, 0x00000000) returns 0x00 (0000ms, 29039ms total) +T3170 092:904 JLINK_WriteReg(R13 (SP), 0x20001000) returns 0x00 (0000ms, 29039ms total) +T3170 092:904 JLINK_WriteReg(R14, 0x20000001) returns 0x00 (0000ms, 29039ms total) +T3170 092:904 JLINK_WriteReg(R15 (PC), 0x2000005C) returns 0x00 (0000ms, 29039ms total) +T3170 092:904 JLINK_WriteReg(XPSR, 0x01000000) returns 0x00 (0000ms, 29039ms total) +T3170 092:904 JLINK_WriteReg(MSP, 0x20001000) returns 0x00 (0000ms, 29039ms total) +T3170 092:904 JLINK_WriteReg(PSP, 0x20001000) returns 0x00 (0000ms, 29039ms total) +T3170 092:904 JLINK_WriteReg(CFBP, 0x00000000) returns 0x00 (0000ms, 29039ms total) +T3170 092:904 JLINK_SetBPEx(Addr = 0x20000000, Type = 0xFFFFFFF2) returns 0x0000005A (0000ms, 29039ms total) +T3170 092:904 JLINK_Go() -- CPU_ReadMem(4 bytes @ 0xE0001000) (0006ms, 29045ms total) +T3170 092:910 JLINK_IsHalted() -- CPU_ReadMem(2 bytes @ 0x20000000) returns TRUE (0093ms, 29138ms total) +T3170 093:003 JLINK_ReadReg(R15 (PC)) returns 0x20000000 (0000ms, 29045ms total) +T3170 093:003 JLINK_ClrBPEx(BPHandle = 0x0000005A) returns 0x00 (0000ms, 29045ms total) +T3170 093:003 JLINK_ReadReg(R0) returns 0x00000000 (0000ms, 29045ms total) +T3170 093:003 JLINK_WriteMem(0x20000144, 0x0080 Bytes, ...) - Data: 65 6E 64 20 74 68 72 65 61 64 0A 00 20 2D 2D 2D ... -- CPU_WriteMem(128 bytes @ 0x20000144) returns 0x80 (0004ms, 29049ms total) +T3170 093:007 JLINK_WriteReg(R0, 0x00002580) returns 0x00 (0000ms, 29049ms total) +T3170 093:007 JLINK_WriteReg(R1, 0x00000080) returns 0x00 (0000ms, 29049ms total) +T3170 093:007 JLINK_WriteReg(R2, 0x20000144) returns 0x00 (0000ms, 29049ms total) +T3170 093:007 JLINK_WriteReg(R3, 0x00000000) returns 0x00 (0000ms, 29049ms total) +T3170 093:007 JLINK_WriteReg(R4, 0x00000000) returns 0x00 (0000ms, 29049ms total) +T3170 093:007 JLINK_WriteReg(R5, 0x00000000) returns 0x00 (0000ms, 29049ms total) +T3170 093:007 JLINK_WriteReg(R6, 0x00000000) returns 0x00 (0000ms, 29049ms total) +T3170 093:007 JLINK_WriteReg(R7, 0x00000000) returns 0x00 (0000ms, 29049ms total) +T3170 093:007 JLINK_WriteReg(R8, 0x00000000) returns 0x00 (0000ms, 29049ms total) +T3170 093:007 JLINK_WriteReg(R9, 0x2000013C) returns 0x00 (0000ms, 29049ms total) +T3170 093:007 JLINK_WriteReg(R10, 0x00000000) returns 0x00 (0000ms, 29049ms total) +T3170 093:007 JLINK_WriteReg(R11, 0x00000000) returns 0x00 (0000ms, 29049ms total) +T3170 093:007 JLINK_WriteReg(R12, 0x00000000) returns 0x00 (0000ms, 29049ms total) +T3170 093:007 JLINK_WriteReg(R13 (SP), 0x20001000) returns 0x00 (0000ms, 29049ms total) +T3170 093:007 JLINK_WriteReg(R14, 0x20000001) returns 0x00 (0000ms, 29049ms total) +T3170 093:007 JLINK_WriteReg(R15 (PC), 0x2000005C) returns 0x00 (0000ms, 29049ms total) +T3170 093:007 JLINK_WriteReg(XPSR, 0x01000000) returns 0x00 (0000ms, 29049ms total) +T3170 093:007 JLINK_WriteReg(MSP, 0x20001000) returns 0x00 (0000ms, 29049ms total) +T3170 093:007 JLINK_WriteReg(PSP, 0x20001000) returns 0x00 (0000ms, 29049ms total) +T3170 093:007 JLINK_WriteReg(CFBP, 0x00000000) returns 0x00 (0001ms, 29050ms total) +T3170 093:008 JLINK_SetBPEx(Addr = 0x20000000, Type = 0xFFFFFFF2) returns 0x0000005B (0000ms, 29050ms total) +T3170 093:008 JLINK_Go() -- CPU_ReadMem(4 bytes @ 0xE0001000) (0007ms, 29057ms total) +T3170 093:016 JLINK_IsHalted() -- CPU_ReadMem(2 bytes @ 0x20000000) returns TRUE (0087ms, 29145ms total) +T3170 093:103 JLINK_ReadReg(R15 (PC)) returns 0x20000000 (0000ms, 29058ms total) +T3170 093:103 JLINK_ClrBPEx(BPHandle = 0x0000005B) returns 0x00 (0000ms, 29058ms total) +T3170 093:103 JLINK_ReadReg(R0) returns 0x00000000 (0000ms, 29058ms total) +T3170 093:104 JLINK_WriteMem(0x20000144, 0x0080 Bytes, ...) - Data: AF F8 00 BF 0C A9 38 46 FF F7 11 FE 07 46 00 26 ... -- CPU_WriteMem(128 bytes @ 0x20000144) returns 0x80 (0006ms, 29064ms total) +T3170 093:110 JLINK_WriteReg(R0, 0x00002600) returns 0x00 (0000ms, 29064ms total) +T3170 093:110 JLINK_WriteReg(R1, 0x00000080) returns 0x00 (0000ms, 29064ms total) +T3170 093:110 JLINK_WriteReg(R2, 0x20000144) returns 0x00 (0000ms, 29064ms total) +T3170 093:110 JLINK_WriteReg(R3, 0x00000000) returns 0x00 (0000ms, 29064ms total) +T3170 093:110 JLINK_WriteReg(R4, 0x00000000) returns 0x00 (0000ms, 29064ms total) +T3170 093:110 JLINK_WriteReg(R5, 0x00000000) returns 0x00 (0000ms, 29064ms total) +T3170 093:110 JLINK_WriteReg(R6, 0x00000000) returns 0x00 (0000ms, 29064ms total) +T3170 093:110 JLINK_WriteReg(R7, 0x00000000) returns 0x00 (0000ms, 29064ms total) +T3170 093:110 JLINK_WriteReg(R8, 0x00000000) returns 0x00 (0000ms, 29064ms total) +T3170 093:110 JLINK_WriteReg(R9, 0x2000013C) returns 0x00 (0000ms, 29064ms total) +T3170 093:110 JLINK_WriteReg(R10, 0x00000000) returns 0x00 (0000ms, 29064ms total) +T3170 093:110 JLINK_WriteReg(R11, 0x00000000) returns 0x00 (0000ms, 29064ms total) +T3170 093:110 JLINK_WriteReg(R12, 0x00000000) returns 0x00 (0000ms, 29064ms total) +T3170 093:110 JLINK_WriteReg(R13 (SP), 0x20001000) returns 0x00 (0000ms, 29064ms total) +T3170 093:110 JLINK_WriteReg(R14, 0x20000001) returns 0x00 (0000ms, 29064ms total) +T3170 093:110 JLINK_WriteReg(R15 (PC), 0x2000005C) returns 0x00 (0000ms, 29064ms total) +T3170 093:110 JLINK_WriteReg(XPSR, 0x01000000) returns 0x00 (0000ms, 29064ms total) +T3170 093:110 JLINK_WriteReg(MSP, 0x20001000) returns 0x00 (0000ms, 29064ms total) +T3170 093:110 JLINK_WriteReg(PSP, 0x20001000) returns 0x00 (0000ms, 29064ms total) +T3170 093:110 JLINK_WriteReg(CFBP, 0x00000000) returns 0x00 (0000ms, 29064ms total) +T3170 093:110 JLINK_SetBPEx(Addr = 0x20000000, Type = 0xFFFFFFF2) returns 0x0000005C (0000ms, 29064ms total) +T3170 093:110 JLINK_Go() -- CPU_ReadMem(4 bytes @ 0xE0001000) (0089ms, 29153ms total) +T3170 093:199 JLINK_IsHalted() -- CPU_ReadMem(2 bytes @ 0x20000000) returns TRUE (0007ms, 29160ms total) +T3170 093:206 JLINK_ReadReg(R15 (PC)) returns 0x20000000 (0000ms, 29153ms total) +T3170 093:206 JLINK_ClrBPEx(BPHandle = 0x0000005C) returns 0x00 (0000ms, 29153ms total) +T3170 093:206 JLINK_ReadReg(R0) returns 0x00000000 (0000ms, 29153ms total) +T3170 093:206 JLINK_WriteMem(0x20000144, 0x0080 Bytes, ...) - Data: 25 2D 2A 2E 73 20 20 20 6F 77 6E 65 72 20 20 68 ... -- CPU_WriteMem(128 bytes @ 0x20000144) returns 0x80 (0003ms, 29156ms total) +T3170 093:209 JLINK_WriteReg(R0, 0x00002680) returns 0x00 (0000ms, 29156ms total) +T3170 093:209 JLINK_WriteReg(R1, 0x00000080) returns 0x00 (0000ms, 29156ms total) +T3170 093:209 JLINK_WriteReg(R2, 0x20000144) returns 0x00 (0000ms, 29156ms total) +T3170 093:209 JLINK_WriteReg(R3, 0x00000000) returns 0x00 (0000ms, 29156ms total) +T3170 093:209 JLINK_WriteReg(R4, 0x00000000) returns 0x00 (0000ms, 29156ms total) +T3170 093:209 JLINK_WriteReg(R5, 0x00000000) returns 0x00 (0000ms, 29156ms total) +T3170 093:209 JLINK_WriteReg(R6, 0x00000000) returns 0x00 (0000ms, 29156ms total) +T3170 093:209 JLINK_WriteReg(R7, 0x00000000) returns 0x00 (0000ms, 29156ms total) +T3170 093:209 JLINK_WriteReg(R8, 0x00000000) returns 0x00 (0000ms, 29156ms total) +T3170 093:209 JLINK_WriteReg(R9, 0x2000013C) returns 0x00 (0000ms, 29156ms total) +T3170 093:209 JLINK_WriteReg(R10, 0x00000000) returns 0x00 (0000ms, 29156ms total) +T3170 093:209 JLINK_WriteReg(R11, 0x00000000) returns 0x00 (0000ms, 29156ms total) +T3170 093:209 JLINK_WriteReg(R12, 0x00000000) returns 0x00 (0000ms, 29156ms total) +T3170 093:209 JLINK_WriteReg(R13 (SP), 0x20001000) returns 0x00 (0000ms, 29156ms total) +T3170 093:209 JLINK_WriteReg(R14, 0x20000001) returns 0x00 (0000ms, 29156ms total) +T3170 093:209 JLINK_WriteReg(R15 (PC), 0x2000005C) returns 0x00 (0000ms, 29156ms total) +T3170 093:209 JLINK_WriteReg(XPSR, 0x01000000) returns 0x00 (0000ms, 29156ms total) +T3170 093:209 JLINK_WriteReg(MSP, 0x20001000) returns 0x00 (0000ms, 29156ms total) +T3170 093:209 JLINK_WriteReg(PSP, 0x20001000) returns 0x00 (0000ms, 29156ms total) +T3170 093:209 JLINK_WriteReg(CFBP, 0x00000000) returns 0x00 (0000ms, 29156ms total) +T3170 093:209 JLINK_SetBPEx(Addr = 0x20000000, Type = 0xFFFFFFF2) returns 0x0000005D (0000ms, 29156ms total) +T3170 093:209 JLINK_Go() -- CPU_ReadMem(4 bytes @ 0xE0001000) (0021ms, 29177ms total) +T3170 093:230 JLINK_IsHalted() -- CPU_ReadMem(2 bytes @ 0x20000000) returns TRUE (0076ms, 29253ms total) +T3170 093:306 JLINK_ReadReg(R15 (PC)) returns 0x20000000 (0000ms, 29177ms total) +T3170 093:306 JLINK_ClrBPEx(BPHandle = 0x0000005D) returns 0x00 (0000ms, 29177ms total) +T3170 093:306 JLINK_ReadReg(R0) returns 0x00000000 (0000ms, 29177ms total) +T3170 093:306 JLINK_WriteMem(0x20000144, 0x0080 Bytes, ...) - Data: 2F F8 40 46 00 F0 3E FC 34 A0 01 F0 29 F8 00 BF ... -- CPU_WriteMem(128 bytes @ 0x20000144) returns 0x80 (0004ms, 29181ms total) +T3170 093:310 JLINK_WriteReg(R0, 0x00002700) returns 0x00 (0000ms, 29181ms total) +T3170 093:310 JLINK_WriteReg(R1, 0x00000080) returns 0x00 (0000ms, 29181ms total) +T3170 093:310 JLINK_WriteReg(R2, 0x20000144) returns 0x00 (0000ms, 29181ms total) +T3170 093:310 JLINK_WriteReg(R3, 0x00000000) returns 0x00 (0000ms, 29181ms total) +T3170 093:310 JLINK_WriteReg(R4, 0x00000000) returns 0x00 (0000ms, 29181ms total) +T3170 093:310 JLINK_WriteReg(R5, 0x00000000) returns 0x00 (0000ms, 29181ms total) +T3170 093:310 JLINK_WriteReg(R6, 0x00000000) returns 0x00 (0000ms, 29181ms total) +T3170 093:310 JLINK_WriteReg(R7, 0x00000000) returns 0x00 (0000ms, 29181ms total) +T3170 093:310 JLINK_WriteReg(R8, 0x00000000) returns 0x00 (0000ms, 29181ms total) +T3170 093:310 JLINK_WriteReg(R9, 0x2000013C) returns 0x00 (0000ms, 29181ms total) +T3170 093:310 JLINK_WriteReg(R10, 0x00000000) returns 0x00 (0000ms, 29181ms total) +T3170 093:310 JLINK_WriteReg(R11, 0x00000000) returns 0x00 (0000ms, 29181ms total) +T3170 093:310 JLINK_WriteReg(R12, 0x00000000) returns 0x00 (0000ms, 29181ms total) +T3170 093:310 JLINK_WriteReg(R13 (SP), 0x20001000) returns 0x00 (0000ms, 29181ms total) +T3170 093:310 JLINK_WriteReg(R14, 0x20000001) returns 0x00 (0000ms, 29181ms total) +T3170 093:310 JLINK_WriteReg(R15 (PC), 0x2000005C) returns 0x00 (0000ms, 29181ms total) +T3170 093:310 JLINK_WriteReg(XPSR, 0x01000000) returns 0x00 (0000ms, 29181ms total) +T3170 093:310 JLINK_WriteReg(MSP, 0x20001000) returns 0x00 (0000ms, 29181ms total) +T3170 093:310 JLINK_WriteReg(PSP, 0x20001000) returns 0x00 (0000ms, 29181ms total) +T3170 093:310 JLINK_WriteReg(CFBP, 0x00000000) returns 0x00 (0000ms, 29181ms total) +T3170 093:310 JLINK_SetBPEx(Addr = 0x20000000, Type = 0xFFFFFFF2) returns 0x0000005E (0000ms, 29181ms total) +T3170 093:310 JLINK_Go() -- CPU_ReadMem(4 bytes @ 0xE0001000) (0090ms, 29271ms total) +T3170 093:400 JLINK_IsHalted() -- CPU_ReadMem(2 bytes @ 0x20000000) returns TRUE (0010ms, 29281ms total) +T3170 093:410 JLINK_ReadReg(R15 (PC)) returns 0x20000000 (0000ms, 29271ms total) +T3170 093:410 JLINK_ClrBPEx(BPHandle = 0x0000005E) returns 0x00 (0000ms, 29271ms total) +T3170 093:410 JLINK_ReadReg(R0) returns 0x00000000 (0000ms, 29271ms total) +T3170 093:410 JLINK_WriteMem(0x20000144, 0x0080 Bytes, ...) - Data: 0D E0 04 F1 14 00 01 F0 40 F8 82 46 A0 8B 23 46 ... -- CPU_WriteMem(128 bytes @ 0x20000144) returns 0x80 (0004ms, 29275ms total) +T3170 093:414 JLINK_WriteReg(R0, 0x00002780) returns 0x00 (0000ms, 29275ms total) +T3170 093:414 JLINK_WriteReg(R1, 0x00000080) returns 0x00 (0000ms, 29275ms total) +T3170 093:414 JLINK_WriteReg(R2, 0x20000144) returns 0x00 (0000ms, 29275ms total) +T3170 093:414 JLINK_WriteReg(R3, 0x00000000) returns 0x00 (0000ms, 29275ms total) +T3170 093:414 JLINK_WriteReg(R4, 0x00000000) returns 0x00 (0000ms, 29275ms total) +T3170 093:414 JLINK_WriteReg(R5, 0x00000000) returns 0x00 (0000ms, 29275ms total) +T3170 093:414 JLINK_WriteReg(R6, 0x00000000) returns 0x00 (0000ms, 29275ms total) +T3170 093:414 JLINK_WriteReg(R7, 0x00000000) returns 0x00 (0000ms, 29275ms total) +T3170 093:414 JLINK_WriteReg(R8, 0x00000000) returns 0x00 (0000ms, 29275ms total) +T3170 093:414 JLINK_WriteReg(R9, 0x2000013C) returns 0x00 (0000ms, 29275ms total) +T3170 093:414 JLINK_WriteReg(R10, 0x00000000) returns 0x00 (0000ms, 29275ms total) +T3170 093:414 JLINK_WriteReg(R11, 0x00000000) returns 0x00 (0000ms, 29275ms total) +T3170 093:414 JLINK_WriteReg(R12, 0x00000000) returns 0x00 (0000ms, 29275ms total) +T3170 093:414 JLINK_WriteReg(R13 (SP), 0x20001000) returns 0x00 (0000ms, 29275ms total) +T3170 093:414 JLINK_WriteReg(R14, 0x20000001) returns 0x00 (0000ms, 29275ms total) +T3170 093:414 JLINK_WriteReg(R15 (PC), 0x2000005C) returns 0x00 (0000ms, 29275ms total) +T3170 093:414 JLINK_WriteReg(XPSR, 0x01000000) returns 0x00 (0000ms, 29275ms total) +T3170 093:414 JLINK_WriteReg(MSP, 0x20001000) returns 0x00 (0000ms, 29275ms total) +T3170 093:414 JLINK_WriteReg(PSP, 0x20001000) returns 0x00 (0000ms, 29275ms total) +T3170 093:414 JLINK_WriteReg(CFBP, 0x00000000) returns 0x00 (0000ms, 29275ms total) +T3170 093:414 JLINK_SetBPEx(Addr = 0x20000000, Type = 0xFFFFFFF2) returns 0x0000005F (0000ms, 29275ms total) +T3170 093:414 JLINK_Go() -- CPU_ReadMem(4 bytes @ 0xE0001000) (0089ms, 29364ms total) +T3170 093:504 JLINK_IsHalted() -- CPU_ReadMem(2 bytes @ 0x20000000) returns TRUE (0008ms, 29372ms total) +T3170 093:512 JLINK_ReadReg(R15 (PC)) returns 0x20000000 (0000ms, 29372ms total) +T3170 093:512 JLINK_ClrBPEx(BPHandle = 0x0000005F) returns 0x00 (0000ms, 29372ms total) +T3170 093:512 JLINK_ReadReg(R0) returns 0x00000000 (0000ms, 29372ms total) +T3170 093:512 JLINK_WriteMem(0x20000144, 0x0080 Bytes, ...) - Data: 25 64 3A 00 25 2D 2A 2E 2A 73 20 25 30 33 64 20 ... -- CPU_WriteMem(128 bytes @ 0x20000144) returns 0x80 (0004ms, 29376ms total) +T3170 093:516 JLINK_WriteReg(R0, 0x00002800) returns 0x00 (0000ms, 29376ms total) +T3170 093:516 JLINK_WriteReg(R1, 0x00000080) returns 0x00 (0000ms, 29376ms total) +T3170 093:516 JLINK_WriteReg(R2, 0x20000144) returns 0x00 (0000ms, 29376ms total) +T3170 093:516 JLINK_WriteReg(R3, 0x00000000) returns 0x00 (0000ms, 29376ms total) +T3170 093:516 JLINK_WriteReg(R4, 0x00000000) returns 0x00 (0000ms, 29376ms total) +T3170 093:516 JLINK_WriteReg(R5, 0x00000000) returns 0x00 (0000ms, 29376ms total) +T3170 093:516 JLINK_WriteReg(R6, 0x00000000) returns 0x00 (0000ms, 29376ms total) +T3170 093:516 JLINK_WriteReg(R7, 0x00000000) returns 0x00 (0000ms, 29376ms total) +T3170 093:516 JLINK_WriteReg(R8, 0x00000000) returns 0x00 (0000ms, 29376ms total) +T3170 093:516 JLINK_WriteReg(R9, 0x2000013C) returns 0x00 (0000ms, 29376ms total) +T3170 093:516 JLINK_WriteReg(R10, 0x00000000) returns 0x00 (0000ms, 29376ms total) +T3170 093:516 JLINK_WriteReg(R11, 0x00000000) returns 0x00 (0000ms, 29376ms total) +T3170 093:516 JLINK_WriteReg(R12, 0x00000000) returns 0x00 (0000ms, 29376ms total) +T3170 093:516 JLINK_WriteReg(R13 (SP), 0x20001000) returns 0x00 (0000ms, 29376ms total) +T3170 093:516 JLINK_WriteReg(R14, 0x20000001) returns 0x00 (0000ms, 29376ms total) +T3170 093:516 JLINK_WriteReg(R15 (PC), 0x2000005C) returns 0x00 (0000ms, 29376ms total) +T3170 093:516 JLINK_WriteReg(XPSR, 0x01000000) returns 0x00 (0000ms, 29376ms total) +T3170 093:516 JLINK_WriteReg(MSP, 0x20001000) returns 0x00 (0000ms, 29376ms total) +T3170 093:516 JLINK_WriteReg(PSP, 0x20001000) returns 0x00 (0000ms, 29376ms total) +T3170 093:516 JLINK_WriteReg(CFBP, 0x00000000) returns 0x00 (0000ms, 29376ms total) +T3170 093:516 JLINK_SetBPEx(Addr = 0x20000000, Type = 0xFFFFFFF2) returns 0x00000060 (0000ms, 29376ms total) +T3170 093:516 JLINK_Go() -- CPU_ReadMem(4 bytes @ 0xE0001000) (0087ms, 29463ms total) +T3170 093:603 JLINK_IsHalted() -- CPU_ReadMem(2 bytes @ 0x20000000) returns TRUE (0010ms, 29473ms total) +T3170 093:614 JLINK_ReadReg(R15 (PC)) returns 0x20000000 (0000ms, 29463ms total) +T3170 093:614 JLINK_ClrBPEx(BPHandle = 0x00000060) returns 0x00 (0000ms, 29463ms total) +T3170 093:614 JLINK_ReadReg(R0) returns 0x00000000 (0000ms, 29463ms total) +T3170 093:614 JLINK_WriteMem(0x20000144, 0x0080 Bytes, ...) - Data: 80 22 29 46 03 A8 FD F7 C3 FE 30 98 FD F7 70 FD ... -- CPU_WriteMem(128 bytes @ 0x20000144) returns 0x80 (0049ms, 29512ms total) +T3170 093:663 JLINK_WriteReg(R0, 0x00002880) returns 0x00 (0000ms, 29512ms total) +T3170 093:663 JLINK_WriteReg(R1, 0x00000080) returns 0x00 (0000ms, 29512ms total) +T3170 093:663 JLINK_WriteReg(R2, 0x20000144) returns 0x00 (0000ms, 29512ms total) +T3170 093:663 JLINK_WriteReg(R3, 0x00000000) returns 0x00 (0000ms, 29512ms total) +T3170 093:663 JLINK_WriteReg(R4, 0x00000000) returns 0x00 (0000ms, 29512ms total) +T3170 093:663 JLINK_WriteReg(R5, 0x00000000) returns 0x00 (0000ms, 29512ms total) +T3170 093:663 JLINK_WriteReg(R6, 0x00000000) returns 0x00 (0000ms, 29512ms total) +T3170 093:663 JLINK_WriteReg(R7, 0x00000000) returns 0x00 (0000ms, 29512ms total) +T3170 093:663 JLINK_WriteReg(R8, 0x00000000) returns 0x00 (0000ms, 29512ms total) +T3170 093:663 JLINK_WriteReg(R9, 0x2000013C) returns 0x00 (0000ms, 29512ms total) +T3170 093:663 JLINK_WriteReg(R10, 0x00000000) returns 0x00 (0000ms, 29512ms total) +T3170 093:663 JLINK_WriteReg(R11, 0x00000000) returns 0x00 (0000ms, 29512ms total) +T3170 093:663 JLINK_WriteReg(R12, 0x00000000) returns 0x00 (0000ms, 29512ms total) +T3170 093:663 JLINK_WriteReg(R13 (SP), 0x20001000) returns 0x00 (0000ms, 29512ms total) +T3170 093:663 JLINK_WriteReg(R14, 0x20000001) returns 0x00 (0000ms, 29512ms total) +T3170 093:663 JLINK_WriteReg(R15 (PC), 0x2000005C) returns 0x00 (0000ms, 29512ms total) +T3170 093:663 JLINK_WriteReg(XPSR, 0x01000000) returns 0x00 (0000ms, 29512ms total) +T3170 093:663 JLINK_WriteReg(MSP, 0x20001000) returns 0x00 (0000ms, 29512ms total) +T3170 093:663 JLINK_WriteReg(PSP, 0x20001000) returns 0x00 (0000ms, 29512ms total) +T3170 093:663 JLINK_WriteReg(CFBP, 0x00000000) returns 0x00 (0000ms, 29512ms total) +T3170 093:663 JLINK_SetBPEx(Addr = 0x20000000, Type = 0xFFFFFFF2) returns 0x00000061 (0000ms, 29512ms total) +T3170 093:663 JLINK_Go() -- CPU_ReadMem(4 bytes @ 0xE0001000) (0044ms, 29556ms total) +T3170 093:707 JLINK_IsHalted() -- CPU_ReadMem(2 bytes @ 0x20000000) returns TRUE (0006ms, 29562ms total) +T3170 093:715 JLINK_ReadReg(R15 (PC)) returns 0x20000000 (0000ms, 29556ms total) +T3170 093:715 JLINK_ClrBPEx(BPHandle = 0x00000061) returns 0x00 (0000ms, 29556ms total) +T3170 093:715 JLINK_ReadReg(R0) returns 0x00000000 (0000ms, 29556ms total) +T3170 093:715 JLINK_WriteMem(0x20000144, 0x0080 Bytes, ...) - Data: F1 F0 02 90 21 6B A0 6C CD E9 00 01 E3 69 A0 6A ... -- CPU_WriteMem(128 bytes @ 0x20000144) returns 0x80 (0085ms, 29641ms total) +T3170 093:800 JLINK_WriteReg(R0, 0x00002900) returns 0x00 (0000ms, 29641ms total) +T3170 093:800 JLINK_WriteReg(R1, 0x00000080) returns 0x00 (0000ms, 29641ms total) +T3170 093:800 JLINK_WriteReg(R2, 0x20000144) returns 0x00 (0000ms, 29641ms total) +T3170 093:800 JLINK_WriteReg(R3, 0x00000000) returns 0x00 (0000ms, 29641ms total) +T3170 093:800 JLINK_WriteReg(R4, 0x00000000) returns 0x00 (0000ms, 29641ms total) +T3170 093:800 JLINK_WriteReg(R5, 0x00000000) returns 0x00 (0000ms, 29641ms total) +T3170 093:800 JLINK_WriteReg(R6, 0x00000000) returns 0x00 (0000ms, 29641ms total) +T3170 093:800 JLINK_WriteReg(R7, 0x00000000) returns 0x00 (0000ms, 29641ms total) +T3170 093:800 JLINK_WriteReg(R8, 0x00000000) returns 0x00 (0000ms, 29641ms total) +T3170 093:800 JLINK_WriteReg(R9, 0x2000013C) returns 0x00 (0000ms, 29641ms total) +T3170 093:800 JLINK_WriteReg(R10, 0x00000000) returns 0x00 (0001ms, 29642ms total) +T3170 093:801 JLINK_WriteReg(R11, 0x00000000) returns 0x00 (0000ms, 29642ms total) +T3170 093:801 JLINK_WriteReg(R12, 0x00000000) returns 0x00 (0000ms, 29642ms total) +T3170 093:801 JLINK_WriteReg(R13 (SP), 0x20001000) returns 0x00 (0000ms, 29642ms total) +T3170 093:801 JLINK_WriteReg(R14, 0x20000001) returns 0x00 (0000ms, 29642ms total) +T3170 093:801 JLINK_WriteReg(R15 (PC), 0x2000005C) returns 0x00 (0000ms, 29642ms total) +T3170 093:801 JLINK_WriteReg(XPSR, 0x01000000) returns 0x00 (0000ms, 29642ms total) +T3170 093:801 JLINK_WriteReg(MSP, 0x20001000) returns 0x00 (0000ms, 29642ms total) +T3170 093:801 JLINK_WriteReg(PSP, 0x20001000) returns 0x00 (0000ms, 29642ms total) +T3170 093:801 JLINK_WriteReg(CFBP, 0x00000000) returns 0x00 (0000ms, 29642ms total) +T3170 093:801 JLINK_SetBPEx(Addr = 0x20000000, Type = 0xFFFFFFF2) returns 0x00000062 (0000ms, 29642ms total) +T3170 093:801 JLINK_Go() -- CPU_ReadMem(4 bytes @ 0xE0001000) (0007ms, 29649ms total) +T3170 093:808 JLINK_IsHalted() -- CPU_ReadMem(2 bytes @ 0x20000000) returns TRUE (0006ms, 29655ms total) +T3170 093:814 JLINK_ReadReg(R15 (PC)) returns 0x20000000 (0000ms, 29649ms total) +T3170 093:814 JLINK_ClrBPEx(BPHandle = 0x00000062) returns 0x00 (0000ms, 29649ms total) +T3170 093:814 JLINK_ReadReg(R0) returns 0x00000000 (0000ms, 29649ms total) +T3170 093:814 JLINK_WriteMem(0x20000144, 0x0080 Bytes, ...) - Data: 2D 2D 2D 0A 00 00 00 00 25 2D 2A 2E 2A 73 20 25 ... -- CPU_WriteMem(128 bytes @ 0x20000144) returns 0x80 (0086ms, 29735ms total) +T3170 093:901 JLINK_WriteReg(R0, 0x00002980) returns 0x00 (0000ms, 29735ms total) +T3170 093:901 JLINK_WriteReg(R1, 0x00000080) returns 0x00 (0000ms, 29735ms total) +T3170 093:901 JLINK_WriteReg(R2, 0x20000144) returns 0x00 (0000ms, 29735ms total) +T3170 093:901 JLINK_WriteReg(R3, 0x00000000) returns 0x00 (0000ms, 29735ms total) +T3170 093:901 JLINK_WriteReg(R4, 0x00000000) returns 0x00 (0000ms, 29735ms total) +T3170 093:901 JLINK_WriteReg(R5, 0x00000000) returns 0x00 (0000ms, 29735ms total) +T3170 093:901 JLINK_WriteReg(R6, 0x00000000) returns 0x00 (0000ms, 29735ms total) +T3170 093:901 JLINK_WriteReg(R7, 0x00000000) returns 0x00 (0000ms, 29735ms total) +T3170 093:901 JLINK_WriteReg(R8, 0x00000000) returns 0x00 (0000ms, 29735ms total) +T3170 093:901 JLINK_WriteReg(R9, 0x2000013C) returns 0x00 (0000ms, 29735ms total) +T3170 093:901 JLINK_WriteReg(R10, 0x00000000) returns 0x00 (0000ms, 29735ms total) +T3170 093:901 JLINK_WriteReg(R11, 0x00000000) returns 0x00 (0000ms, 29735ms total) +T3170 093:901 JLINK_WriteReg(R12, 0x00000000) returns 0x00 (0000ms, 29735ms total) +T3170 093:901 JLINK_WriteReg(R13 (SP), 0x20001000) returns 0x00 (0000ms, 29735ms total) +T3170 093:901 JLINK_WriteReg(R14, 0x20000001) returns 0x00 (0000ms, 29735ms total) +T3170 093:901 JLINK_WriteReg(R15 (PC), 0x2000005C) returns 0x00 (0000ms, 29735ms total) +T3170 093:901 JLINK_WriteReg(XPSR, 0x01000000) returns 0x00 (0000ms, 29735ms total) +T3170 093:901 JLINK_WriteReg(MSP, 0x20001000) returns 0x00 (0000ms, 29735ms total) +T3170 093:901 JLINK_WriteReg(PSP, 0x20001000) returns 0x00 (0000ms, 29735ms total) +T3170 093:901 JLINK_WriteReg(CFBP, 0x00000000) returns 0x00 (0000ms, 29735ms total) +T3170 093:901 JLINK_SetBPEx(Addr = 0x20000000, Type = 0xFFFFFFF2) returns 0x00000063 (0000ms, 29735ms total) +T3170 093:901 JLINK_Go() -- CPU_ReadMem(4 bytes @ 0xE0001000) (0007ms, 29742ms total) +T3170 093:908 JLINK_IsHalted() -- CPU_ReadMem(2 bytes @ 0x20000000) returns TRUE (0018ms, 29760ms total) +T3170 093:926 JLINK_ReadReg(R15 (PC)) returns 0x20000000 (0000ms, 29742ms total) +T3170 093:926 JLINK_ClrBPEx(BPHandle = 0x00000063) returns 0x00 (0000ms, 29742ms total) +T3170 093:926 JLINK_ReadReg(R0) returns 0x00000000 (0000ms, 29742ms total) +T3170 093:926 JLINK_WriteMem(0x20000144, 0x0080 Bytes, ...) - Data: 0F F2 B4 09 08 23 03 AA 0A 21 0B A8 FF F7 FA FB ... -- CPU_WriteMem(128 bytes @ 0x20000144) returns 0x80 (0074ms, 29816ms total) +T3170 094:000 JLINK_WriteReg(R0, 0x00002A00) returns 0x00 (0000ms, 29816ms total) +T3170 094:000 JLINK_WriteReg(R1, 0x00000080) returns 0x00 (0000ms, 29816ms total) +T3170 094:000 JLINK_WriteReg(R2, 0x20000144) returns 0x00 (0000ms, 29816ms total) +T3170 094:000 JLINK_WriteReg(R3, 0x00000000) returns 0x00 (0000ms, 29816ms total) +T3170 094:000 JLINK_WriteReg(R4, 0x00000000) returns 0x00 (0000ms, 29816ms total) +T3170 094:000 JLINK_WriteReg(R5, 0x00000000) returns 0x00 (0000ms, 29816ms total) +T3170 094:000 JLINK_WriteReg(R6, 0x00000000) returns 0x00 (0000ms, 29816ms total) +T3170 094:000 JLINK_WriteReg(R7, 0x00000000) returns 0x00 (0000ms, 29816ms total) +T3170 094:000 JLINK_WriteReg(R8, 0x00000000) returns 0x00 (0000ms, 29816ms total) +T3170 094:000 JLINK_WriteReg(R9, 0x2000013C) returns 0x00 (0000ms, 29816ms total) +T3170 094:000 JLINK_WriteReg(R10, 0x00000000) returns 0x00 (0000ms, 29816ms total) +T3170 094:000 JLINK_WriteReg(R11, 0x00000000) returns 0x00 (0000ms, 29816ms total) +T3170 094:000 JLINK_WriteReg(R12, 0x00000000) returns 0x00 (0000ms, 29816ms total) +T3170 094:000 JLINK_WriteReg(R13 (SP), 0x20001000) returns 0x00 (0000ms, 29816ms total) +T3170 094:000 JLINK_WriteReg(R14, 0x20000001) returns 0x00 (0000ms, 29816ms total) +T3170 094:000 JLINK_WriteReg(R15 (PC), 0x2000005C) returns 0x00 (0000ms, 29816ms total) +T3170 094:000 JLINK_WriteReg(XPSR, 0x01000000) returns 0x00 (0000ms, 29816ms total) +T3170 094:000 JLINK_WriteReg(MSP, 0x20001000) returns 0x00 (0000ms, 29816ms total) +T3170 094:000 JLINK_WriteReg(PSP, 0x20001000) returns 0x00 (0000ms, 29816ms total) +T3170 094:000 JLINK_WriteReg(CFBP, 0x00000000) returns 0x00 (0000ms, 29816ms total) +T3170 094:000 JLINK_SetBPEx(Addr = 0x20000000, Type = 0xFFFFFFF2) returns 0x00000064 (0000ms, 29816ms total) +T3170 094:000 JLINK_Go() -- CPU_ReadMem(4 bytes @ 0xE0001000) (0007ms, 29823ms total) +T3170 094:007 JLINK_IsHalted() -- CPU_ReadMem(2 bytes @ 0x20000000) returns TRUE (0092ms, 29915ms total) +T3170 094:099 JLINK_ReadReg(R15 (PC)) returns 0x20000000 (0000ms, 29823ms total) +T3170 094:099 JLINK_ClrBPEx(BPHandle = 0x00000064) returns 0x00 (0000ms, 29823ms total) +T3170 094:099 JLINK_ReadReg(R0) returns 0x00000000 (0000ms, 29823ms total) +T3170 094:099 JLINK_WriteMem(0x20000144, 0x0080 Bytes, ...) - Data: 01 00 18 B1 27 A0 00 F0 6B FE 02 E0 28 A0 00 F0 ... -- CPU_WriteMem(128 bytes @ 0x20000144) returns 0x80 (0004ms, 29827ms total) +T3170 094:103 JLINK_WriteReg(R0, 0x00002A80) returns 0x00 (0000ms, 29827ms total) +T3170 094:103 JLINK_WriteReg(R1, 0x00000080) returns 0x00 (0000ms, 29827ms total) +T3170 094:103 JLINK_WriteReg(R2, 0x20000144) returns 0x00 (0000ms, 29827ms total) +T3170 094:103 JLINK_WriteReg(R3, 0x00000000) returns 0x00 (0000ms, 29827ms total) +T3170 094:103 JLINK_WriteReg(R4, 0x00000000) returns 0x00 (0000ms, 29827ms total) +T3170 094:103 JLINK_WriteReg(R5, 0x00000000) returns 0x00 (0000ms, 29827ms total) +T3170 094:103 JLINK_WriteReg(R6, 0x00000000) returns 0x00 (0000ms, 29827ms total) +T3170 094:103 JLINK_WriteReg(R7, 0x00000000) returns 0x00 (0000ms, 29827ms total) +T3170 094:103 JLINK_WriteReg(R8, 0x00000000) returns 0x00 (0000ms, 29827ms total) +T3170 094:103 JLINK_WriteReg(R9, 0x2000013C) returns 0x00 (0000ms, 29827ms total) +T3170 094:103 JLINK_WriteReg(R10, 0x00000000) returns 0x00 (0000ms, 29827ms total) +T3170 094:103 JLINK_WriteReg(R11, 0x00000000) returns 0x00 (0000ms, 29827ms total) +T3170 094:103 JLINK_WriteReg(R12, 0x00000000) returns 0x00 (0000ms, 29827ms total) +T3170 094:103 JLINK_WriteReg(R13 (SP), 0x20001000) returns 0x00 (0000ms, 29827ms total) +T3170 094:103 JLINK_WriteReg(R14, 0x20000001) returns 0x00 (0000ms, 29827ms total) +T3170 094:103 JLINK_WriteReg(R15 (PC), 0x2000005C) returns 0x00 (0000ms, 29827ms total) +T3170 094:103 JLINK_WriteReg(XPSR, 0x01000000) returns 0x00 (0000ms, 29827ms total) +T3170 094:103 JLINK_WriteReg(MSP, 0x20001000) returns 0x00 (0000ms, 29827ms total) +T3170 094:103 JLINK_WriteReg(PSP, 0x20001000) returns 0x00 (0000ms, 29827ms total) +T3170 094:103 JLINK_WriteReg(CFBP, 0x00000000) returns 0x00 (0000ms, 29827ms total) +T3170 094:103 JLINK_SetBPEx(Addr = 0x20000000, Type = 0xFFFFFFF2) returns 0x00000065 (0000ms, 29827ms total) +T3170 094:103 JLINK_Go() -- CPU_ReadMem(4 bytes @ 0xE0001000) (0007ms, 29834ms total) +T3170 094:110 JLINK_IsHalted() -- CPU_ReadMem(2 bytes @ 0x20000000) returns TRUE (0049ms, 29883ms total) +T3170 094:159 JLINK_ReadReg(R15 (PC)) returns 0x20000000 (0000ms, 29834ms total) +T3170 094:159 JLINK_ClrBPEx(BPHandle = 0x00000065) returns 0x00 (0000ms, 29834ms total) +T3170 094:159 JLINK_ReadReg(R0) returns 0x00000000 (0000ms, 29834ms total) +T3170 094:159 JLINK_WriteMem(0x20000144, 0x0080 Bytes, ...) - Data: 2D 2D 2D 2D 2D 2D 2D 2D 2D 2D 0A 00 25 2D 2A 2E ... -- CPU_WriteMem(128 bytes @ 0x20000144) returns 0x80 (0042ms, 29876ms total) +T3170 094:201 JLINK_WriteReg(R0, 0x00002B00) returns 0x00 (0000ms, 29876ms total) +T3170 094:201 JLINK_WriteReg(R1, 0x00000080) returns 0x00 (0000ms, 29876ms total) +T3170 094:201 JLINK_WriteReg(R2, 0x20000144) returns 0x00 (0000ms, 29876ms total) +T3170 094:201 JLINK_WriteReg(R3, 0x00000000) returns 0x00 (0000ms, 29876ms total) +T3170 094:201 JLINK_WriteReg(R4, 0x00000000) returns 0x00 (0000ms, 29876ms total) +T3170 094:201 JLINK_WriteReg(R5, 0x00000000) returns 0x00 (0000ms, 29876ms total) +T3170 094:201 JLINK_WriteReg(R6, 0x00000000) returns 0x00 (0000ms, 29876ms total) +T3170 094:201 JLINK_WriteReg(R7, 0x00000000) returns 0x00 (0000ms, 29876ms total) +T3170 094:201 JLINK_WriteReg(R8, 0x00000000) returns 0x00 (0000ms, 29876ms total) +T3170 094:201 JLINK_WriteReg(R9, 0x2000013C) returns 0x00 (0000ms, 29876ms total) +T3170 094:201 JLINK_WriteReg(R10, 0x00000000) returns 0x00 (0000ms, 29876ms total) +T3170 094:201 JLINK_WriteReg(R11, 0x00000000) returns 0x00 (0000ms, 29876ms total) +T3170 094:201 JLINK_WriteReg(R12, 0x00000000) returns 0x00 (0000ms, 29876ms total) +T3170 094:201 JLINK_WriteReg(R13 (SP), 0x20001000) returns 0x00 (0000ms, 29876ms total) +T3170 094:201 JLINK_WriteReg(R14, 0x20000001) returns 0x00 (0000ms, 29876ms total) +T3170 094:201 JLINK_WriteReg(R15 (PC), 0x2000005C) returns 0x00 (0000ms, 29876ms total) +T3170 094:201 JLINK_WriteReg(XPSR, 0x01000000) returns 0x00 (0000ms, 29876ms total) +T3170 094:201 JLINK_WriteReg(MSP, 0x20001000) returns 0x00 (0000ms, 29876ms total) +T3170 094:201 JLINK_WriteReg(PSP, 0x20001000) returns 0x00 (0000ms, 29876ms total) +T3170 094:201 JLINK_WriteReg(CFBP, 0x00000000) returns 0x00 (0000ms, 29876ms total) +T3170 094:201 JLINK_SetBPEx(Addr = 0x20000000, Type = 0xFFFFFFF2) returns 0x00000066 (0000ms, 29876ms total) +T3170 094:201 JLINK_Go() -- CPU_ReadMem(4 bytes @ 0xE0001000) (0008ms, 29884ms total) +T3170 094:209 JLINK_IsHalted() -- CPU_ReadMem(2 bytes @ 0x20000000) returns TRUE (0090ms, 29974ms total) +T3170 094:299 JLINK_ReadReg(R15 (PC)) returns 0x20000000 (0000ms, 29884ms total) +T3170 094:299 JLINK_ClrBPEx(BPHandle = 0x00000066) returns 0x00 (0000ms, 29884ms total) +T3170 094:299 JLINK_ReadReg(R0) returns 0x00000000 (0000ms, 29884ms total) +T3170 094:299 JLINK_WriteMem(0x20000144, 0x0080 Bytes, ...) - Data: 17 E0 01 21 00 20 FD F7 F9 FE 01 21 08 46 FD F7 ... -- CPU_WriteMem(128 bytes @ 0x20000144) returns 0x80 (0004ms, 29888ms total) +T3170 094:303 JLINK_WriteReg(R0, 0x00002B80) returns 0x00 (0000ms, 29888ms total) +T3170 094:303 JLINK_WriteReg(R1, 0x00000080) returns 0x00 (0000ms, 29888ms total) +T3170 094:303 JLINK_WriteReg(R2, 0x20000144) returns 0x00 (0000ms, 29888ms total) +T3170 094:303 JLINK_WriteReg(R3, 0x00000000) returns 0x00 (0000ms, 29888ms total) +T3170 094:303 JLINK_WriteReg(R4, 0x00000000) returns 0x00 (0000ms, 29888ms total) +T3170 094:303 JLINK_WriteReg(R5, 0x00000000) returns 0x00 (0000ms, 29888ms total) +T3170 094:303 JLINK_WriteReg(R6, 0x00000000) returns 0x00 (0000ms, 29888ms total) +T3170 094:303 JLINK_WriteReg(R7, 0x00000000) returns 0x00 (0000ms, 29888ms total) +T3170 094:303 JLINK_WriteReg(R8, 0x00000000) returns 0x00 (0000ms, 29888ms total) +T3170 094:303 JLINK_WriteReg(R9, 0x2000013C) returns 0x00 (0000ms, 29888ms total) +T3170 094:303 JLINK_WriteReg(R10, 0x00000000) returns 0x00 (0000ms, 29888ms total) +T3170 094:303 JLINK_WriteReg(R11, 0x00000000) returns 0x00 (0000ms, 29888ms total) +T3170 094:303 JLINK_WriteReg(R12, 0x00000000) returns 0x00 (0000ms, 29888ms total) +T3170 094:303 JLINK_WriteReg(R13 (SP), 0x20001000) returns 0x00 (0000ms, 29888ms total) +T3170 094:303 JLINK_WriteReg(R14, 0x20000001) returns 0x00 (0000ms, 29888ms total) +T3170 094:303 JLINK_WriteReg(R15 (PC), 0x2000005C) returns 0x00 (0000ms, 29888ms total) +T3170 094:303 JLINK_WriteReg(XPSR, 0x01000000) returns 0x00 (0000ms, 29888ms total) +T3170 094:303 JLINK_WriteReg(MSP, 0x20001000) returns 0x00 (0000ms, 29888ms total) +T3170 094:303 JLINK_WriteReg(PSP, 0x20001000) returns 0x00 (0000ms, 29888ms total) +T3170 094:303 JLINK_WriteReg(CFBP, 0x00000000) returns 0x00 (0000ms, 29888ms total) +T3170 094:303 JLINK_SetBPEx(Addr = 0x20000000, Type = 0xFFFFFFF2) returns 0x00000067 (0000ms, 29888ms total) +T3170 094:303 JLINK_Go() -- CPU_ReadMem(4 bytes @ 0xE0001000) (0007ms, 29895ms total) +T3170 094:310 JLINK_IsHalted() -- CPU_ReadMem(2 bytes @ 0x20000000) returns TRUE (0077ms, 29972ms total) +T3170 094:387 JLINK_ReadReg(R15 (PC)) returns 0x20000000 (0000ms, 29895ms total) +T3170 094:387 JLINK_ClrBPEx(BPHandle = 0x00000067) returns 0x00 (0000ms, 29895ms total) +T3170 094:387 JLINK_ReadReg(R0) returns 0x00000000 (0000ms, 29895ms total) +T3170 094:388 JLINK_WriteMem(0x20000144, 0x0080 Bytes, ...) - Data: 00 78 00 F0 08 00 10 B1 1F A0 00 F0 A9 FD 11 48 ... -- CPU_WriteMem(128 bytes @ 0x20000144) returns 0x80 (0013ms, 29908ms total) +T3170 094:401 JLINK_WriteReg(R0, 0x00002C00) returns 0x00 (0000ms, 29908ms total) +T3170 094:401 JLINK_WriteReg(R1, 0x00000080) returns 0x00 (0000ms, 29908ms total) +T3170 094:401 JLINK_WriteReg(R2, 0x20000144) returns 0x00 (0000ms, 29908ms total) +T3170 094:401 JLINK_WriteReg(R3, 0x00000000) returns 0x00 (0000ms, 29908ms total) +T3170 094:401 JLINK_WriteReg(R4, 0x00000000) returns 0x00 (0000ms, 29908ms total) +T3170 094:401 JLINK_WriteReg(R5, 0x00000000) returns 0x00 (0000ms, 29908ms total) +T3170 094:401 JLINK_WriteReg(R6, 0x00000000) returns 0x00 (0000ms, 29908ms total) +T3170 094:401 JLINK_WriteReg(R7, 0x00000000) returns 0x00 (0000ms, 29908ms total) +T3170 094:401 JLINK_WriteReg(R8, 0x00000000) returns 0x00 (0000ms, 29908ms total) +T3170 094:401 JLINK_WriteReg(R9, 0x2000013C) returns 0x00 (0000ms, 29908ms total) +T3170 094:401 JLINK_WriteReg(R10, 0x00000000) returns 0x00 (0000ms, 29908ms total) +T3170 094:401 JLINK_WriteReg(R11, 0x00000000) returns 0x00 (0000ms, 29908ms total) +T3170 094:401 JLINK_WriteReg(R12, 0x00000000) returns 0x00 (0000ms, 29908ms total) +T3170 094:401 JLINK_WriteReg(R13 (SP), 0x20001000) returns 0x00 (0000ms, 29908ms total) +T3170 094:401 JLINK_WriteReg(R14, 0x20000001) returns 0x00 (0000ms, 29908ms total) +T3170 094:401 JLINK_WriteReg(R15 (PC), 0x2000005C) returns 0x00 (0000ms, 29908ms total) +T3170 094:401 JLINK_WriteReg(XPSR, 0x01000000) returns 0x00 (0000ms, 29908ms total) +T3170 094:401 JLINK_WriteReg(MSP, 0x20001000) returns 0x00 (0000ms, 29908ms total) +T3170 094:401 JLINK_WriteReg(PSP, 0x20001000) returns 0x00 (0000ms, 29908ms total) +T3170 094:401 JLINK_WriteReg(CFBP, 0x00000000) returns 0x00 (0000ms, 29908ms total) +T3170 094:401 JLINK_SetBPEx(Addr = 0x20000000, Type = 0xFFFFFFF2) returns 0x00000068 (0000ms, 29908ms total) +T3170 094:401 JLINK_Go() -- CPU_ReadMem(4 bytes @ 0xE0001000) (0007ms, 29915ms total) +T3170 094:408 JLINK_IsHalted() -- CPU_ReadMem(2 bytes @ 0x20000000) returns TRUE (0008ms, 29923ms total) +T3170 094:416 JLINK_ReadReg(R15 (PC)) returns 0x20000000 (0000ms, 29915ms total) +T3170 094:416 JLINK_ClrBPEx(BPHandle = 0x00000068) returns 0x00 (0000ms, 29915ms total) +T3170 094:416 JLINK_ReadReg(R0) returns 0x00000000 (0000ms, 29915ms total) +T3170 094:416 JLINK_WriteMem(0x20000144, 0x0080 Bytes, ...) - Data: 56 49 4F 4C 20 00 00 00 4D 55 4E 53 54 4B 45 52 ... -- CPU_WriteMem(128 bytes @ 0x20000144) returns 0x80 (0084ms, 29999ms total) +T3170 094:500 JLINK_WriteReg(R0, 0x00002C80) returns 0x00 (0000ms, 29999ms total) +T3170 094:500 JLINK_WriteReg(R1, 0x00000080) returns 0x00 (0000ms, 29999ms total) +T3170 094:501 JLINK_WriteReg(R2, 0x20000144) returns 0x00 (0000ms, 29999ms total) +T3170 094:501 JLINK_WriteReg(R3, 0x00000000) returns 0x00 (0000ms, 29999ms total) +T3170 094:501 JLINK_WriteReg(R4, 0x00000000) returns 0x00 (0000ms, 29999ms total) +T3170 094:501 JLINK_WriteReg(R5, 0x00000000) returns 0x00 (0000ms, 29999ms total) +T3170 094:501 JLINK_WriteReg(R6, 0x00000000) returns 0x00 (0000ms, 29999ms total) +T3170 094:501 JLINK_WriteReg(R7, 0x00000000) returns 0x00 (0000ms, 29999ms total) +T3170 094:501 JLINK_WriteReg(R8, 0x00000000) returns 0x00 (0000ms, 29999ms total) +T3170 094:501 JLINK_WriteReg(R9, 0x2000013C) returns 0x00 (0000ms, 29999ms total) +T3170 094:501 JLINK_WriteReg(R10, 0x00000000) returns 0x00 (0000ms, 29999ms total) +T3170 094:501 JLINK_WriteReg(R11, 0x00000000) returns 0x00 (0000ms, 29999ms total) +T3170 094:501 JLINK_WriteReg(R12, 0x00000000) returns 0x00 (0000ms, 29999ms total) +T3170 094:501 JLINK_WriteReg(R13 (SP), 0x20001000) returns 0x00 (0000ms, 29999ms total) +T3170 094:501 JLINK_WriteReg(R14, 0x20000001) returns 0x00 (0000ms, 29999ms total) +T3170 094:501 JLINK_WriteReg(R15 (PC), 0x2000005C) returns 0x00 (0000ms, 29999ms total) +T3170 094:501 JLINK_WriteReg(XPSR, 0x01000000) returns 0x00 (0000ms, 29999ms total) +T3170 094:501 JLINK_WriteReg(MSP, 0x20001000) returns 0x00 (0000ms, 29999ms total) +T3170 094:501 JLINK_WriteReg(PSP, 0x20001000) returns 0x00 (0000ms, 29999ms total) +T3170 094:501 JLINK_WriteReg(CFBP, 0x00000000) returns 0x00 (0000ms, 29999ms total) +T3170 094:501 JLINK_SetBPEx(Addr = 0x20000000, Type = 0xFFFFFFF2) returns 0x00000069 (0000ms, 29999ms total) +T3170 094:501 JLINK_Go() -- CPU_ReadMem(4 bytes @ 0xE0001000) (0008ms, 30007ms total) +T3170 094:509 JLINK_IsHalted() -- CPU_ReadMem(2 bytes @ 0x20000000) returns TRUE (0090ms, 30097ms total) +T3170 094:599 JLINK_ReadReg(R15 (PC)) returns 0x20000000 (0000ms, 30007ms total) +T3170 094:599 JLINK_ClrBPEx(BPHandle = 0x00000069) returns 0x00 (0000ms, 30007ms total) +T3170 094:599 JLINK_ReadReg(R0) returns 0x00000000 (0000ms, 30007ms total) +T3170 094:599 JLINK_WriteMem(0x20000144, 0x0080 Bytes, ...) - Data: 47 46 38 46 FD F7 0E FC 06 46 41 46 38 46 01 F0 ... -- CPU_WriteMem(128 bytes @ 0x20000144) returns 0x80 (0004ms, 30011ms total) +T3170 094:603 JLINK_WriteReg(R0, 0x00002D00) returns 0x00 (0000ms, 30011ms total) +T3170 094:603 JLINK_WriteReg(R1, 0x00000080) returns 0x00 (0000ms, 30011ms total) +T3170 094:603 JLINK_WriteReg(R2, 0x20000144) returns 0x00 (0000ms, 30011ms total) +T3170 094:603 JLINK_WriteReg(R3, 0x00000000) returns 0x00 (0000ms, 30011ms total) +T3170 094:603 JLINK_WriteReg(R4, 0x00000000) returns 0x00 (0000ms, 30011ms total) +T3170 094:603 JLINK_WriteReg(R5, 0x00000000) returns 0x00 (0000ms, 30011ms total) +T3170 094:603 JLINK_WriteReg(R6, 0x00000000) returns 0x00 (0000ms, 30011ms total) +T3170 094:603 JLINK_WriteReg(R7, 0x00000000) returns 0x00 (0000ms, 30011ms total) +T3170 094:603 JLINK_WriteReg(R8, 0x00000000) returns 0x00 (0000ms, 30011ms total) +T3170 094:603 JLINK_WriteReg(R9, 0x2000013C) returns 0x00 (0000ms, 30011ms total) +T3170 094:603 JLINK_WriteReg(R10, 0x00000000) returns 0x00 (0000ms, 30011ms total) +T3170 094:603 JLINK_WriteReg(R11, 0x00000000) returns 0x00 (0000ms, 30011ms total) +T3170 094:603 JLINK_WriteReg(R12, 0x00000000) returns 0x00 (0000ms, 30011ms total) +T3170 094:603 JLINK_WriteReg(R13 (SP), 0x20001000) returns 0x00 (0000ms, 30011ms total) +T3170 094:603 JLINK_WriteReg(R14, 0x20000001) returns 0x00 (0000ms, 30011ms total) +T3170 094:603 JLINK_WriteReg(R15 (PC), 0x2000005C) returns 0x00 (0000ms, 30011ms total) +T3170 094:603 JLINK_WriteReg(XPSR, 0x01000000) returns 0x00 (0000ms, 30011ms total) +T3170 094:603 JLINK_WriteReg(MSP, 0x20001000) returns 0x00 (0000ms, 30011ms total) +T3170 094:603 JLINK_WriteReg(PSP, 0x20001000) returns 0x00 (0000ms, 30011ms total) +T3170 094:603 JLINK_WriteReg(CFBP, 0x00000000) returns 0x00 (0000ms, 30011ms total) +T3170 094:603 JLINK_SetBPEx(Addr = 0x20000000, Type = 0xFFFFFFF2) returns 0x0000006A (0000ms, 30011ms total) +T3170 094:603 JLINK_Go() -- CPU_ReadMem(4 bytes @ 0xE0001000) (0009ms, 30020ms total) +T3170 094:613 JLINK_IsHalted() -- CPU_ReadMem(2 bytes @ 0x20000000) returns TRUE (0091ms, 30112ms total) +T3170 094:704 JLINK_ReadReg(R15 (PC)) returns 0x20000000 (0000ms, 30021ms total) +T3170 094:707 JLINK_ClrBPEx(BPHandle = 0x0000006A) returns 0x00 (0000ms, 30021ms total) +T3170 094:707 JLINK_ReadReg(R0) returns 0x00000000 (0000ms, 30021ms total) +T3170 094:707 JLINK_WriteMem(0x20000144, 0x0080 Bytes, ...) - Data: F6 E7 20 46 00 E0 40 1C 01 78 20 29 02 D0 01 78 ... -- CPU_WriteMem(128 bytes @ 0x20000144) returns 0x80 (0003ms, 30024ms total) +T3170 094:710 JLINK_WriteReg(R0, 0x00002D80) returns 0x00 (0000ms, 30024ms total) +T3170 094:710 JLINK_WriteReg(R1, 0x00000080) returns 0x00 (0000ms, 30024ms total) +T3170 094:710 JLINK_WriteReg(R2, 0x20000144) returns 0x00 (0000ms, 30024ms total) +T3170 094:710 JLINK_WriteReg(R3, 0x00000000) returns 0x00 (0000ms, 30024ms total) +T3170 094:710 JLINK_WriteReg(R4, 0x00000000) returns 0x00 (0000ms, 30024ms total) +T3170 094:710 JLINK_WriteReg(R5, 0x00000000) returns 0x00 (0000ms, 30024ms total) +T3170 094:710 JLINK_WriteReg(R6, 0x00000000) returns 0x00 (0000ms, 30024ms total) +T3170 094:710 JLINK_WriteReg(R7, 0x00000000) returns 0x00 (0000ms, 30024ms total) +T3170 094:710 JLINK_WriteReg(R8, 0x00000000) returns 0x00 (0000ms, 30024ms total) +T3170 094:710 JLINK_WriteReg(R9, 0x2000013C) returns 0x00 (0000ms, 30024ms total) +T3170 094:710 JLINK_WriteReg(R10, 0x00000000) returns 0x00 (0000ms, 30024ms total) +T3170 094:710 JLINK_WriteReg(R11, 0x00000000) returns 0x00 (0000ms, 30024ms total) +T3170 094:710 JLINK_WriteReg(R12, 0x00000000) returns 0x00 (0000ms, 30024ms total) +T3170 094:710 JLINK_WriteReg(R13 (SP), 0x20001000) returns 0x00 (0000ms, 30024ms total) +T3170 094:710 JLINK_WriteReg(R14, 0x20000001) returns 0x00 (0000ms, 30024ms total) +T3170 094:710 JLINK_WriteReg(R15 (PC), 0x2000005C) returns 0x00 (0000ms, 30024ms total) +T3170 094:710 JLINK_WriteReg(XPSR, 0x01000000) returns 0x00 (0000ms, 30024ms total) +T3170 094:710 JLINK_WriteReg(MSP, 0x20001000) returns 0x00 (0000ms, 30024ms total) +T3170 094:710 JLINK_WriteReg(PSP, 0x20001000) returns 0x00 (0000ms, 30024ms total) +T3170 094:710 JLINK_WriteReg(CFBP, 0x00000000) returns 0x00 (0000ms, 30024ms total) +T3170 094:710 JLINK_SetBPEx(Addr = 0x20000000, Type = 0xFFFFFFF2) returns 0x0000006B (0000ms, 30024ms total) +T3170 094:710 JLINK_Go() -- CPU_ReadMem(4 bytes @ 0xE0001000) (0089ms, 30113ms total) +T3170 094:799 JLINK_IsHalted() -- CPU_ReadMem(2 bytes @ 0x20000000) returns TRUE (0010ms, 30123ms total) +T3170 094:810 JLINK_ReadReg(R15 (PC)) returns 0x20000000 (0000ms, 30113ms total) +T3170 094:810 JLINK_ClrBPEx(BPHandle = 0x0000006B) returns 0x00 (0000ms, 30113ms total) +T3170 094:810 JLINK_ReadReg(R0) returns 0x00000000 (0000ms, 30113ms total) +T3170 094:810 JLINK_WriteMem(0x20000144, 0x0080 Bytes, ...) - Data: 84 42 E5 D3 00 BF 38 46 BD E8 F0 81 E0 00 00 20 ... -- CPU_WriteMem(128 bytes @ 0x20000144) returns 0x80 (0003ms, 30116ms total) +T3170 094:813 JLINK_WriteReg(R0, 0x00002E00) returns 0x00 (0000ms, 30116ms total) +T3170 094:813 JLINK_WriteReg(R1, 0x00000080) returns 0x00 (0000ms, 30116ms total) +T3170 094:813 JLINK_WriteReg(R2, 0x20000144) returns 0x00 (0000ms, 30116ms total) +T3170 094:813 JLINK_WriteReg(R3, 0x00000000) returns 0x00 (0000ms, 30116ms total) +T3170 094:813 JLINK_WriteReg(R4, 0x00000000) returns 0x00 (0000ms, 30116ms total) +T3170 094:813 JLINK_WriteReg(R5, 0x00000000) returns 0x00 (0000ms, 30116ms total) +T3170 094:813 JLINK_WriteReg(R6, 0x00000000) returns 0x00 (0000ms, 30116ms total) +T3170 094:813 JLINK_WriteReg(R7, 0x00000000) returns 0x00 (0000ms, 30116ms total) +T3170 094:813 JLINK_WriteReg(R8, 0x00000000) returns 0x00 (0001ms, 30117ms total) +T3170 094:814 JLINK_WriteReg(R9, 0x2000013C) returns 0x00 (0000ms, 30117ms total) +T3170 094:814 JLINK_WriteReg(R10, 0x00000000) returns 0x00 (0000ms, 30117ms total) +T3170 094:814 JLINK_WriteReg(R11, 0x00000000) returns 0x00 (0000ms, 30117ms total) +T3170 094:814 JLINK_WriteReg(R12, 0x00000000) returns 0x00 (0000ms, 30117ms total) +T3170 094:814 JLINK_WriteReg(R13 (SP), 0x20001000) returns 0x00 (0000ms, 30117ms total) +T3170 094:814 JLINK_WriteReg(R14, 0x20000001) returns 0x00 (0000ms, 30117ms total) +T3170 094:814 JLINK_WriteReg(R15 (PC), 0x2000005C) returns 0x00 (0000ms, 30117ms total) +T3170 094:814 JLINK_WriteReg(XPSR, 0x01000000) returns 0x00 (0000ms, 30117ms total) +T3170 094:814 JLINK_WriteReg(MSP, 0x20001000) returns 0x00 (0000ms, 30117ms total) +T3170 094:814 JLINK_WriteReg(PSP, 0x20001000) returns 0x00 (0000ms, 30117ms total) +T3170 094:814 JLINK_WriteReg(CFBP, 0x00000000) returns 0x00 (0000ms, 30117ms total) +T3170 094:814 JLINK_SetBPEx(Addr = 0x20000000, Type = 0xFFFFFFF2) returns 0x0000006C (0000ms, 30117ms total) +T3170 094:814 JLINK_Go() -- CPU_ReadMem(4 bytes @ 0xE0001000) (0092ms, 30209ms total) +T3170 094:906 JLINK_IsHalted() -- CPU_ReadMem(2 bytes @ 0x20000000) returns TRUE (0006ms, 30215ms total) +T3170 094:912 JLINK_ReadReg(R15 (PC)) returns 0x20000000 (0000ms, 30209ms total) +T3170 094:913 JLINK_ClrBPEx(BPHandle = 0x0000006C) returns 0x00 (0000ms, 30209ms total) +T3170 094:913 JLINK_ReadReg(R0) returns 0x00000000 (0000ms, 30209ms total) +T3170 094:913 JLINK_WriteMem(0x20000144, 0x0080 Bytes, ...) - Data: 64 5F 00 00 25 73 20 00 E4 00 00 20 0A 00 00 00 ... -- CPU_WriteMem(128 bytes @ 0x20000144) returns 0x80 (0003ms, 30212ms total) +T3170 094:916 JLINK_WriteReg(R0, 0x00002E80) returns 0x00 (0000ms, 30212ms total) +T3170 094:916 JLINK_WriteReg(R1, 0x00000080) returns 0x00 (0000ms, 30212ms total) +T3170 094:916 JLINK_WriteReg(R2, 0x20000144) returns 0x00 (0000ms, 30212ms total) +T3170 094:916 JLINK_WriteReg(R3, 0x00000000) returns 0x00 (0000ms, 30212ms total) +T3170 094:916 JLINK_WriteReg(R4, 0x00000000) returns 0x00 (0000ms, 30212ms total) +T3170 094:916 JLINK_WriteReg(R5, 0x00000000) returns 0x00 (0000ms, 30212ms total) +T3170 094:916 JLINK_WriteReg(R6, 0x00000000) returns 0x00 (0000ms, 30212ms total) +T3170 094:916 JLINK_WriteReg(R7, 0x00000000) returns 0x00 (0000ms, 30212ms total) +T3170 094:916 JLINK_WriteReg(R8, 0x00000000) returns 0x00 (0000ms, 30212ms total) +T3170 094:916 JLINK_WriteReg(R9, 0x2000013C) returns 0x00 (0000ms, 30212ms total) +T3170 094:916 JLINK_WriteReg(R10, 0x00000000) returns 0x00 (0000ms, 30212ms total) +T3170 094:916 JLINK_WriteReg(R11, 0x00000000) returns 0x00 (0000ms, 30212ms total) +T3170 094:916 JLINK_WriteReg(R12, 0x00000000) returns 0x00 (0000ms, 30212ms total) +T3170 094:916 JLINK_WriteReg(R13 (SP), 0x20001000) returns 0x00 (0000ms, 30212ms total) +T3170 094:916 JLINK_WriteReg(R14, 0x20000001) returns 0x00 (0000ms, 30212ms total) +T3170 094:916 JLINK_WriteReg(R15 (PC), 0x2000005C) returns 0x00 (0000ms, 30212ms total) +T3170 094:916 JLINK_WriteReg(XPSR, 0x01000000) returns 0x00 (0000ms, 30212ms total) +T3170 094:916 JLINK_WriteReg(MSP, 0x20001000) returns 0x00 (0000ms, 30212ms total) +T3170 094:916 JLINK_WriteReg(PSP, 0x20001000) returns 0x00 (0000ms, 30212ms total) +T3170 094:916 JLINK_WriteReg(CFBP, 0x00000000) returns 0x00 (0001ms, 30213ms total) +T3170 094:917 JLINK_SetBPEx(Addr = 0x20000000, Type = 0xFFFFFFF2) returns 0x0000006D (0000ms, 30213ms total) +T3170 094:917 JLINK_Go() -- CPU_ReadMem(4 bytes @ 0xE0001000) (0087ms, 30300ms total) +T3170 095:004 JLINK_IsHalted() -- CPU_ReadMem(2 bytes @ 0x20000000) returns TRUE (0008ms, 30308ms total) +T3170 095:012 JLINK_ReadReg(R15 (PC)) returns 0x20000000 (0000ms, 30300ms total) +T3170 095:012 JLINK_ClrBPEx(BPHandle = 0x0000006D) returns 0x00 (0000ms, 30300ms total) +T3170 095:012 JLINK_ReadReg(R0) returns 0x00000000 (0000ms, 30300ms total) +T3170 095:012 JLINK_WriteMem(0x20000144, 0x0080 Bytes, ...) - Data: 09 E0 20 78 5C 28 04 D1 60 78 22 28 01 D1 64 1C ... -- CPU_WriteMem(128 bytes @ 0x20000144) returns 0x80 (0003ms, 30303ms total) +T3170 095:015 JLINK_WriteReg(R0, 0x00002F00) returns 0x00 (0000ms, 30303ms total) +T3170 095:015 JLINK_WriteReg(R1, 0x00000080) returns 0x00 (0000ms, 30303ms total) +T3170 095:015 JLINK_WriteReg(R2, 0x20000144) returns 0x00 (0000ms, 30303ms total) +T3170 095:015 JLINK_WriteReg(R3, 0x00000000) returns 0x00 (0000ms, 30303ms total) +T3170 095:015 JLINK_WriteReg(R4, 0x00000000) returns 0x00 (0000ms, 30303ms total) +T3170 095:015 JLINK_WriteReg(R5, 0x00000000) returns 0x00 (0000ms, 30303ms total) +T3170 095:015 JLINK_WriteReg(R6, 0x00000000) returns 0x00 (0000ms, 30303ms total) +T3170 095:015 JLINK_WriteReg(R7, 0x00000000) returns 0x00 (0000ms, 30303ms total) +T3170 095:015 JLINK_WriteReg(R8, 0x00000000) returns 0x00 (0000ms, 30303ms total) +T3170 095:015 JLINK_WriteReg(R9, 0x2000013C) returns 0x00 (0000ms, 30303ms total) +T3170 095:015 JLINK_WriteReg(R10, 0x00000000) returns 0x00 (0000ms, 30303ms total) +T3170 095:015 JLINK_WriteReg(R11, 0x00000000) returns 0x00 (0000ms, 30303ms total) +T3170 095:015 JLINK_WriteReg(R12, 0x00000000) returns 0x00 (0000ms, 30303ms total) +T3170 095:015 JLINK_WriteReg(R13 (SP), 0x20001000) returns 0x00 (0000ms, 30303ms total) +T3170 095:015 JLINK_WriteReg(R14, 0x20000001) returns 0x00 (0000ms, 30303ms total) +T3170 095:015 JLINK_WriteReg(R15 (PC), 0x2000005C) returns 0x00 (0000ms, 30303ms total) +T3170 095:015 JLINK_WriteReg(XPSR, 0x01000000) returns 0x00 (0000ms, 30303ms total) +T3170 095:015 JLINK_WriteReg(MSP, 0x20001000) returns 0x00 (0000ms, 30303ms total) +T3170 095:015 JLINK_WriteReg(PSP, 0x20001000) returns 0x00 (0000ms, 30303ms total) +T3170 095:015 JLINK_WriteReg(CFBP, 0x00000000) returns 0x00 (0000ms, 30303ms total) +T3170 095:015 JLINK_SetBPEx(Addr = 0x20000000, Type = 0xFFFFFFF2) returns 0x0000006E (0000ms, 30303ms total) +T3170 095:015 JLINK_Go() -- CPU_ReadMem(4 bytes @ 0xE0001000) (0085ms, 30388ms total) +T3170 095:101 JLINK_IsHalted() -- CPU_ReadMem(2 bytes @ 0x20000000) returns TRUE (0008ms, 30396ms total) +T3170 095:109 JLINK_ReadReg(R15 (PC)) returns 0x20000000 (0000ms, 30388ms total) +T3170 095:109 JLINK_ClrBPEx(BPHandle = 0x0000006E) returns 0x00 (0000ms, 30388ms total) +T3170 095:109 JLINK_ReadReg(R0) returns 0x00000000 (0000ms, 30388ms total) +T3170 095:109 JLINK_WriteMem(0x20000144, 0x0080 Bytes, ...) - Data: 25 73 20 00 10 B5 04 46 02 E0 04 A0 00 F0 E8 FB ... -- CPU_WriteMem(128 bytes @ 0x20000144) returns 0x80 (0004ms, 30392ms total) +T3170 095:113 JLINK_WriteReg(R0, 0x00002F80) returns 0x00 (0000ms, 30392ms total) +T3170 095:113 JLINK_WriteReg(R1, 0x00000080) returns 0x00 (0000ms, 30392ms total) +T3170 095:113 JLINK_WriteReg(R2, 0x20000144) returns 0x00 (0000ms, 30392ms total) +T3170 095:113 JLINK_WriteReg(R3, 0x00000000) returns 0x00 (0000ms, 30392ms total) +T3170 095:113 JLINK_WriteReg(R4, 0x00000000) returns 0x00 (0000ms, 30392ms total) +T3170 095:113 JLINK_WriteReg(R5, 0x00000000) returns 0x00 (0000ms, 30392ms total) +T3170 095:113 JLINK_WriteReg(R6, 0x00000000) returns 0x00 (0000ms, 30392ms total) +T3170 095:113 JLINK_WriteReg(R7, 0x00000000) returns 0x00 (0000ms, 30392ms total) +T3170 095:113 JLINK_WriteReg(R8, 0x00000000) returns 0x00 (0000ms, 30392ms total) +T3170 095:113 JLINK_WriteReg(R9, 0x2000013C) returns 0x00 (0000ms, 30392ms total) +T3170 095:113 JLINK_WriteReg(R10, 0x00000000) returns 0x00 (0000ms, 30392ms total) +T3170 095:113 JLINK_WriteReg(R11, 0x00000000) returns 0x00 (0000ms, 30392ms total) +T3170 095:113 JLINK_WriteReg(R12, 0x00000000) returns 0x00 (0000ms, 30392ms total) +T3170 095:113 JLINK_WriteReg(R13 (SP), 0x20001000) returns 0x00 (0000ms, 30392ms total) +T3170 095:113 JLINK_WriteReg(R14, 0x20000001) returns 0x00 (0000ms, 30392ms total) +T3170 095:113 JLINK_WriteReg(R15 (PC), 0x2000005C) returns 0x00 (0000ms, 30392ms total) +T3170 095:113 JLINK_WriteReg(XPSR, 0x01000000) returns 0x00 (0000ms, 30392ms total) +T3170 095:113 JLINK_WriteReg(MSP, 0x20001000) returns 0x00 (0000ms, 30392ms total) +T3170 095:113 JLINK_WriteReg(PSP, 0x20001000) returns 0x00 (0000ms, 30392ms total) +T3170 095:113 JLINK_WriteReg(CFBP, 0x00000000) returns 0x00 (0000ms, 30392ms total) +T3170 095:113 JLINK_SetBPEx(Addr = 0x20000000, Type = 0xFFFFFFF2) returns 0x0000006F (0000ms, 30392ms total) +T3170 095:113 JLINK_Go() -- CPU_ReadMem(4 bytes @ 0xE0001000) (0089ms, 30481ms total) +T3170 095:202 JLINK_IsHalted() -- CPU_ReadMem(2 bytes @ 0x20000000) returns TRUE (0008ms, 30489ms total) +T3170 095:210 JLINK_ReadReg(R15 (PC)) returns 0x20000000 (0000ms, 30481ms total) +T3170 095:210 JLINK_ClrBPEx(BPHandle = 0x0000006F) returns 0x00 (0000ms, 30481ms total) +T3170 095:210 JLINK_ReadReg(R0) returns 0x00000000 (0000ms, 30481ms total) +T3170 095:210 JLINK_WriteMem(0x20000144, 0x0080 Bytes, ...) - Data: 02 4D 44 68 2D 68 2C 44 A3 60 30 BD 24 00 00 20 ... -- CPU_WriteMem(128 bytes @ 0x20000144) returns 0x80 (0003ms, 30484ms total) +T3170 095:213 JLINK_WriteReg(R0, 0x00003000) returns 0x00 (0000ms, 30484ms total) +T3170 095:213 JLINK_WriteReg(R1, 0x00000080) returns 0x00 (0000ms, 30484ms total) +T3170 095:213 JLINK_WriteReg(R2, 0x20000144) returns 0x00 (0000ms, 30484ms total) +T3170 095:213 JLINK_WriteReg(R3, 0x00000000) returns 0x00 (0000ms, 30484ms total) +T3170 095:213 JLINK_WriteReg(R4, 0x00000000) returns 0x00 (0000ms, 30484ms total) +T3170 095:213 JLINK_WriteReg(R5, 0x00000000) returns 0x00 (0000ms, 30484ms total) +T3170 095:213 JLINK_WriteReg(R6, 0x00000000) returns 0x00 (0000ms, 30484ms total) +T3170 095:213 JLINK_WriteReg(R7, 0x00000000) returns 0x00 (0000ms, 30484ms total) +T3170 095:213 JLINK_WriteReg(R8, 0x00000000) returns 0x00 (0000ms, 30484ms total) +T3170 095:213 JLINK_WriteReg(R9, 0x2000013C) returns 0x00 (0000ms, 30484ms total) +T3170 095:213 JLINK_WriteReg(R10, 0x00000000) returns 0x00 (0000ms, 30484ms total) +T3170 095:213 JLINK_WriteReg(R11, 0x00000000) returns 0x00 (0000ms, 30484ms total) +T3170 095:213 JLINK_WriteReg(R12, 0x00000000) returns 0x00 (0000ms, 30484ms total) +T3170 095:213 JLINK_WriteReg(R13 (SP), 0x20001000) returns 0x00 (0000ms, 30484ms total) +T3170 095:213 JLINK_WriteReg(R14, 0x20000001) returns 0x00 (0000ms, 30484ms total) +T3170 095:213 JLINK_WriteReg(R15 (PC), 0x2000005C) returns 0x00 (0000ms, 30484ms total) +T3170 095:213 JLINK_WriteReg(XPSR, 0x01000000) returns 0x00 (0000ms, 30484ms total) +T3170 095:213 JLINK_WriteReg(MSP, 0x20001000) returns 0x00 (0000ms, 30484ms total) +T3170 095:213 JLINK_WriteReg(PSP, 0x20001000) returns 0x00 (0000ms, 30484ms total) +T3170 095:213 JLINK_WriteReg(CFBP, 0x00000000) returns 0x00 (0000ms, 30484ms total) +T3170 095:213 JLINK_SetBPEx(Addr = 0x20000000, Type = 0xFFFFFFF2) returns 0x00000070 (0000ms, 30484ms total) +T3170 095:213 JLINK_Go() -- CPU_ReadMem(4 bytes @ 0xE0001000) (0090ms, 30574ms total) +T3170 095:303 JLINK_IsHalted() -- CPU_ReadMem(2 bytes @ 0x20000000) returns TRUE (0009ms, 30583ms total) +T3170 095:312 JLINK_ReadReg(R15 (PC)) returns 0x20000000 (0000ms, 30574ms total) +T3170 095:312 JLINK_ClrBPEx(BPHandle = 0x00000070) returns 0x00 (0000ms, 30574ms total) +T3170 095:312 JLINK_ReadReg(R0) returns 0x00000000 (0000ms, 30574ms total) +T3170 095:312 JLINK_WriteMem(0x20000144, 0x0080 Bytes, ...) - Data: B8 F1 00 0F 01 D0 2B 27 05 E0 04 F0 08 08 B8 F1 ... -- CPU_WriteMem(128 bytes @ 0x20000144) returns 0x80 (0004ms, 30578ms total) +T3170 095:316 JLINK_WriteReg(R0, 0x00003080) returns 0x00 (0000ms, 30578ms total) +T3170 095:316 JLINK_WriteReg(R1, 0x00000080) returns 0x00 (0000ms, 30578ms total) +T3170 095:316 JLINK_WriteReg(R2, 0x20000144) returns 0x00 (0000ms, 30578ms total) +T3170 095:316 JLINK_WriteReg(R3, 0x00000000) returns 0x00 (0000ms, 30578ms total) +T3170 095:316 JLINK_WriteReg(R4, 0x00000000) returns 0x00 (0000ms, 30578ms total) +T3170 095:316 JLINK_WriteReg(R5, 0x00000000) returns 0x00 (0000ms, 30578ms total) +T3170 095:317 JLINK_WriteReg(R6, 0x00000000) returns 0x00 (0000ms, 30578ms total) +T3170 095:317 JLINK_WriteReg(R7, 0x00000000) returns 0x00 (0000ms, 30578ms total) +T3170 095:317 JLINK_WriteReg(R8, 0x00000000) returns 0x00 (0000ms, 30578ms total) +T3170 095:317 JLINK_WriteReg(R9, 0x2000013C) returns 0x00 (0000ms, 30578ms total) +T3170 095:317 JLINK_WriteReg(R10, 0x00000000) returns 0x00 (0000ms, 30578ms total) +T3170 095:317 JLINK_WriteReg(R11, 0x00000000) returns 0x00 (0000ms, 30578ms total) +T3170 095:317 JLINK_WriteReg(R12, 0x00000000) returns 0x00 (0000ms, 30578ms total) +T3170 095:317 JLINK_WriteReg(R13 (SP), 0x20001000) returns 0x00 (0000ms, 30578ms total) +T3170 095:317 JLINK_WriteReg(R14, 0x20000001) returns 0x00 (0000ms, 30578ms total) +T3170 095:317 JLINK_WriteReg(R15 (PC), 0x2000005C) returns 0x00 (0000ms, 30578ms total) +T3170 095:317 JLINK_WriteReg(XPSR, 0x01000000) returns 0x00 (0000ms, 30578ms total) +T3170 095:317 JLINK_WriteReg(MSP, 0x20001000) returns 0x00 (0000ms, 30578ms total) +T3170 095:317 JLINK_WriteReg(PSP, 0x20001000) returns 0x00 (0000ms, 30578ms total) +T3170 095:317 JLINK_WriteReg(CFBP, 0x00000000) returns 0x00 (0000ms, 30578ms total) +T3170 095:317 JLINK_SetBPEx(Addr = 0x20000000, Type = 0xFFFFFFF2) returns 0x00000071 (0000ms, 30578ms total) +T3170 095:317 JLINK_Go() -- CPU_ReadMem(4 bytes @ 0xE0001000) (0087ms, 30665ms total) +T3170 095:404 JLINK_IsHalted() -- CPU_ReadMem(2 bytes @ 0x20000000) returns TRUE (0009ms, 30674ms total) +T3170 095:413 JLINK_ReadReg(R15 (PC)) returns 0x20000000 (0000ms, 30665ms total) +T3170 095:413 JLINK_ClrBPEx(BPHandle = 0x00000071) returns 0x00 (0000ms, 30665ms total) +T3170 095:413 JLINK_ReadReg(R0) returns 0x00000000 (0000ms, 30665ms total) +T3170 095:413 JLINK_WriteMem(0x20000144, 0x0080 Bytes, ...) - Data: 5B 1E 06 E0 A8 42 03 D2 4F F0 20 08 80 F8 00 80 ... -- CPU_WriteMem(128 bytes @ 0x20000144) returns 0x80 (0054ms, 30719ms total) +T3170 095:467 JLINK_WriteReg(R0, 0x00003100) returns 0x00 (0000ms, 30719ms total) +T3170 095:467 JLINK_WriteReg(R1, 0x00000080) returns 0x00 (0000ms, 30719ms total) +T3170 095:467 JLINK_WriteReg(R2, 0x20000144) returns 0x00 (0000ms, 30719ms total) +T3170 095:468 JLINK_WriteReg(R3, 0x00000000) returns 0x00 (0000ms, 30720ms total) +T3170 095:468 JLINK_WriteReg(R4, 0x00000000) returns 0x00 (0000ms, 30720ms total) +T3170 095:468 JLINK_WriteReg(R5, 0x00000000) returns 0x00 (0000ms, 30720ms total) +T3170 095:468 JLINK_WriteReg(R6, 0x00000000) returns 0x00 (0000ms, 30720ms total) +T3170 095:468 JLINK_WriteReg(R7, 0x00000000) returns 0x00 (0000ms, 30720ms total) +T3170 095:468 JLINK_WriteReg(R8, 0x00000000) returns 0x00 (0000ms, 30720ms total) +T3170 095:468 JLINK_WriteReg(R9, 0x2000013C) returns 0x00 (0000ms, 30720ms total) +T3170 095:468 JLINK_WriteReg(R10, 0x00000000) returns 0x00 (0000ms, 30720ms total) +T3170 095:468 JLINK_WriteReg(R11, 0x00000000) returns 0x00 (0000ms, 30720ms total) +T3170 095:468 JLINK_WriteReg(R12, 0x00000000) returns 0x00 (0000ms, 30720ms total) +T3170 095:468 JLINK_WriteReg(R13 (SP), 0x20001000) returns 0x00 (0000ms, 30720ms total) +T3170 095:468 JLINK_WriteReg(R14, 0x20000001) returns 0x00 (0000ms, 30720ms total) +T3170 095:468 JLINK_WriteReg(R15 (PC), 0x2000005C) returns 0x00 (0000ms, 30720ms total) +T3170 095:468 JLINK_WriteReg(XPSR, 0x01000000) returns 0x00 (0000ms, 30720ms total) +T3170 095:468 JLINK_WriteReg(MSP, 0x20001000) returns 0x00 (0000ms, 30720ms total) +T3170 095:468 JLINK_WriteReg(PSP, 0x20001000) returns 0x00 (0000ms, 30720ms total) +T3170 095:468 JLINK_WriteReg(CFBP, 0x00000000) returns 0x00 (0000ms, 30720ms total) +T3170 095:468 JLINK_SetBPEx(Addr = 0x20000000, Type = 0xFFFFFFF2) returns 0x00000072 (0000ms, 30720ms total) +T3170 095:468 JLINK_Go() -- CPU_ReadMem(4 bytes @ 0xE0001000) (0038ms, 30758ms total) +T3170 095:506 JLINK_IsHalted() -- CPU_ReadMem(2 bytes @ 0x20000000) returns TRUE (0009ms, 30767ms total) +T3170 095:515 JLINK_ReadReg(R15 (PC)) returns 0x20000000 (0000ms, 30758ms total) +T3170 095:515 JLINK_ClrBPEx(BPHandle = 0x00000072) returns 0x00 (0000ms, 30758ms total) +T3170 095:515 JLINK_ReadReg(R0) returns 0x00000000 (0000ms, 30758ms total) +T3170 095:515 JLINK_WriteMem(0x20000144, 0x0080 Bytes, ...) - Data: 04 80 B8 F1 00 0F EC D1 06 E0 A8 42 03 D2 4F F0 ... -- CPU_WriteMem(128 bytes @ 0x20000144) returns 0x80 (0085ms, 30843ms total) +T3170 095:600 JLINK_WriteReg(R0, 0x00003180) returns 0x00 (0000ms, 30843ms total) +T3170 095:600 JLINK_WriteReg(R1, 0x00000080) returns 0x00 (0000ms, 30843ms total) +T3170 095:600 JLINK_WriteReg(R2, 0x20000144) returns 0x00 (0000ms, 30843ms total) +T3170 095:600 JLINK_WriteReg(R3, 0x00000000) returns 0x00 (0000ms, 30843ms total) +T3170 095:600 JLINK_WriteReg(R4, 0x00000000) returns 0x00 (0000ms, 30843ms total) +T3170 095:600 JLINK_WriteReg(R5, 0x00000000) returns 0x00 (0000ms, 30843ms total) +T3170 095:600 JLINK_WriteReg(R6, 0x00000000) returns 0x00 (0000ms, 30843ms total) +T3170 095:600 JLINK_WriteReg(R7, 0x00000000) returns 0x00 (0000ms, 30843ms total) +T3170 095:600 JLINK_WriteReg(R8, 0x00000000) returns 0x00 (0000ms, 30843ms total) +T3170 095:600 JLINK_WriteReg(R9, 0x2000013C) returns 0x00 (0000ms, 30843ms total) +T3170 095:600 JLINK_WriteReg(R10, 0x00000000) returns 0x00 (0000ms, 30843ms total) +T3170 095:600 JLINK_WriteReg(R11, 0x00000000) returns 0x00 (0000ms, 30843ms total) +T3170 095:600 JLINK_WriteReg(R12, 0x00000000) returns 0x00 (0001ms, 30844ms total) +T3170 095:601 JLINK_WriteReg(R13 (SP), 0x20001000) returns 0x00 (0000ms, 30844ms total) +T3170 095:601 JLINK_WriteReg(R14, 0x20000001) returns 0x00 (0000ms, 30844ms total) +T3170 095:601 JLINK_WriteReg(R15 (PC), 0x2000005C) returns 0x00 (0000ms, 30844ms total) +T3170 095:601 JLINK_WriteReg(XPSR, 0x01000000) returns 0x00 (0000ms, 30844ms total) +T3170 095:601 JLINK_WriteReg(MSP, 0x20001000) returns 0x00 (0000ms, 30844ms total) +T3170 095:601 JLINK_WriteReg(PSP, 0x20001000) returns 0x00 (0000ms, 30844ms total) +T3170 095:601 JLINK_WriteReg(CFBP, 0x00000000) returns 0x00 (0000ms, 30844ms total) +T3170 095:601 JLINK_SetBPEx(Addr = 0x20000000, Type = 0xFFFFFFF2) returns 0x00000073 (0000ms, 30844ms total) +T3170 095:601 JLINK_Go() -- CPU_ReadMem(4 bytes @ 0xE0001000) (0007ms, 30851ms total) +T3170 095:608 JLINK_IsHalted() -- CPU_ReadMem(2 bytes @ 0x20000000) returns TRUE (0057ms, 30908ms total) +T3170 095:666 JLINK_ReadReg(R15 (PC)) returns 0x20000000 (0000ms, 30851ms total) +T3170 095:666 JLINK_ClrBPEx(BPHandle = 0x00000073) returns 0x00 (0000ms, 30851ms total) +T3170 095:666 JLINK_ReadReg(R0) returns 0x00000000 (0000ms, 30851ms total) +T3170 095:666 JLINK_WriteMem(0x20000144, 0x0080 Bytes, ...) - Data: 05 F0 00 F0 1F FB 06 46 2E B1 04 FB 05 F2 00 21 ... -- CPU_WriteMem(128 bytes @ 0x20000144) returns 0x80 (0035ms, 30886ms total) +T3170 095:701 JLINK_WriteReg(R0, 0x00003200) returns 0x00 (0000ms, 30886ms total) +T3170 095:701 JLINK_WriteReg(R1, 0x00000080) returns 0x00 (0000ms, 30886ms total) +T3170 095:701 JLINK_WriteReg(R2, 0x20000144) returns 0x00 (0000ms, 30886ms total) +T3170 095:701 JLINK_WriteReg(R3, 0x00000000) returns 0x00 (0000ms, 30886ms total) +T3170 095:701 JLINK_WriteReg(R4, 0x00000000) returns 0x00 (0000ms, 30886ms total) +T3170 095:701 JLINK_WriteReg(R5, 0x00000000) returns 0x00 (0000ms, 30886ms total) +T3170 095:701 JLINK_WriteReg(R6, 0x00000000) returns 0x00 (0000ms, 30886ms total) +T3170 095:701 JLINK_WriteReg(R7, 0x00000000) returns 0x00 (0000ms, 30886ms total) +T3170 095:701 JLINK_WriteReg(R8, 0x00000000) returns 0x00 (0000ms, 30886ms total) +T3170 095:701 JLINK_WriteReg(R9, 0x2000013C) returns 0x00 (0000ms, 30886ms total) +T3170 095:701 JLINK_WriteReg(R10, 0x00000000) returns 0x00 (0000ms, 30886ms total) +T3170 095:701 JLINK_WriteReg(R11, 0x00000000) returns 0x00 (0000ms, 30886ms total) +T3170 095:701 JLINK_WriteReg(R12, 0x00000000) returns 0x00 (0000ms, 30886ms total) +T3170 095:701 JLINK_WriteReg(R13 (SP), 0x20001000) returns 0x00 (0000ms, 30886ms total) +T3170 095:701 JLINK_WriteReg(R14, 0x20000001) returns 0x00 (0000ms, 30886ms total) +T3170 095:701 JLINK_WriteReg(R15 (PC), 0x2000005C) returns 0x00 (0000ms, 30886ms total) +T3170 095:701 JLINK_WriteReg(XPSR, 0x01000000) returns 0x00 (0000ms, 30886ms total) +T3170 095:701 JLINK_WriteReg(MSP, 0x20001000) returns 0x00 (0000ms, 30886ms total) +T3170 095:701 JLINK_WriteReg(PSP, 0x20001000) returns 0x00 (0000ms, 30886ms total) +T3170 095:701 JLINK_WriteReg(CFBP, 0x00000000) returns 0x00 (0000ms, 30886ms total) +T3170 095:701 JLINK_SetBPEx(Addr = 0x20000000, Type = 0xFFFFFFF2) returns 0x00000074 (0000ms, 30886ms total) +T3170 095:701 JLINK_Go() -- CPU_ReadMem(4 bytes @ 0xE0001000) (0009ms, 30895ms total) +T3170 095:710 JLINK_IsHalted() -- CPU_ReadMem(2 bytes @ 0x20000000) returns TRUE (0089ms, 30984ms total) +T3170 095:799 JLINK_ReadReg(R15 (PC)) returns 0x20000000 (0000ms, 30895ms total) +T3170 095:802 JLINK_ClrBPEx(BPHandle = 0x00000074) returns 0x00 (0000ms, 30895ms total) +T3170 095:802 JLINK_ReadReg(R0) returns 0x00000000 (0000ms, 30895ms total) +T3170 095:805 JLINK_WriteMem(0x20000144, 0x0080 Bytes, ...) - Data: 40 1E 00 B2 0A 49 08 80 08 46 B0 F9 00 00 00 28 ... -- CPU_WriteMem(128 bytes @ 0x20000144) returns 0x80 (0008ms, 30903ms total) +T3170 095:813 JLINK_WriteReg(R0, 0x00003280) returns 0x00 (0000ms, 30903ms total) +T3170 095:813 JLINK_WriteReg(R1, 0x00000080) returns 0x00 (0000ms, 30903ms total) +T3170 095:813 JLINK_WriteReg(R2, 0x20000144) returns 0x00 (0000ms, 30903ms total) +T3170 095:813 JLINK_WriteReg(R3, 0x00000000) returns 0x00 (0000ms, 30903ms total) +T3170 095:813 JLINK_WriteReg(R4, 0x00000000) returns 0x00 (0000ms, 30903ms total) +T3170 095:813 JLINK_WriteReg(R5, 0x00000000) returns 0x00 (0000ms, 30903ms total) +T3170 095:813 JLINK_WriteReg(R6, 0x00000000) returns 0x00 (0000ms, 30903ms total) +T3170 095:813 JLINK_WriteReg(R7, 0x00000000) returns 0x00 (0000ms, 30903ms total) +T3170 095:813 JLINK_WriteReg(R8, 0x00000000) returns 0x00 (0000ms, 30903ms total) +T3170 095:813 JLINK_WriteReg(R9, 0x2000013C) returns 0x00 (0000ms, 30903ms total) +T3170 095:813 JLINK_WriteReg(R10, 0x00000000) returns 0x00 (0000ms, 30903ms total) +T3170 095:813 JLINK_WriteReg(R11, 0x00000000) returns 0x00 (0001ms, 30904ms total) +T3170 095:814 JLINK_WriteReg(R12, 0x00000000) returns 0x00 (0000ms, 30904ms total) +T3170 095:814 JLINK_WriteReg(R13 (SP), 0x20001000) returns 0x00 (0000ms, 30904ms total) +T3170 095:814 JLINK_WriteReg(R14, 0x20000001) returns 0x00 (0000ms, 30904ms total) +T3170 095:814 JLINK_WriteReg(R15 (PC), 0x2000005C) returns 0x00 (0000ms, 30904ms total) +T3170 095:814 JLINK_WriteReg(XPSR, 0x01000000) returns 0x00 (0000ms, 30904ms total) +T3170 095:814 JLINK_WriteReg(MSP, 0x20001000) returns 0x00 (0000ms, 30904ms total) +T3170 095:814 JLINK_WriteReg(PSP, 0x20001000) returns 0x00 (0000ms, 30904ms total) +T3170 095:814 JLINK_WriteReg(CFBP, 0x00000000) returns 0x00 (0000ms, 30904ms total) +T3170 095:814 JLINK_SetBPEx(Addr = 0x20000000, Type = 0xFFFFFFF2) returns 0x00000075 (0000ms, 30904ms total) +T3170 095:814 JLINK_Go() -- CPU_ReadMem(4 bytes @ 0xE0001000) (0087ms, 30991ms total) +T3170 095:901 JLINK_IsHalted() -- CPU_ReadMem(2 bytes @ 0x20000000) returns TRUE (0009ms, 31000ms total) +T3170 095:910 JLINK_ReadReg(R15 (PC)) returns 0x20000000 (0000ms, 30991ms total) +T3170 095:910 JLINK_ClrBPEx(BPHandle = 0x00000075) returns 0x00 (0000ms, 30991ms total) +T3170 095:910 JLINK_ReadReg(R0) returns 0x00000000 (0000ms, 30991ms total) +T3170 095:910 JLINK_WriteMem(0x20000144, 0x0080 Bytes, ...) - Data: 60 80 4F F4 F5 50 20 80 21 48 00 68 84 42 01 D2 ... -- CPU_WriteMem(128 bytes @ 0x20000144) returns 0x80 (0003ms, 30994ms total) +T3170 095:913 JLINK_WriteReg(R0, 0x00003300) returns 0x00 (0000ms, 30994ms total) +T3170 095:913 JLINK_WriteReg(R1, 0x00000080) returns 0x00 (0000ms, 30994ms total) +T3170 095:913 JLINK_WriteReg(R2, 0x20000144) returns 0x00 (0000ms, 30994ms total) +T3170 095:913 JLINK_WriteReg(R3, 0x00000000) returns 0x00 (0000ms, 30994ms total) +T3170 095:913 JLINK_WriteReg(R4, 0x00000000) returns 0x00 (0000ms, 30994ms total) +T3170 095:913 JLINK_WriteReg(R5, 0x00000000) returns 0x00 (0000ms, 30994ms total) +T3170 095:913 JLINK_WriteReg(R6, 0x00000000) returns 0x00 (0000ms, 30994ms total) +T3170 095:913 JLINK_WriteReg(R7, 0x00000000) returns 0x00 (0000ms, 30994ms total) +T3170 095:913 JLINK_WriteReg(R8, 0x00000000) returns 0x00 (0000ms, 30994ms total) +T3170 095:913 JLINK_WriteReg(R9, 0x2000013C) returns 0x00 (0000ms, 30994ms total) +T3170 095:913 JLINK_WriteReg(R10, 0x00000000) returns 0x00 (0000ms, 30994ms total) +T3170 095:913 JLINK_WriteReg(R11, 0x00000000) returns 0x00 (0000ms, 30994ms total) +T3170 095:913 JLINK_WriteReg(R12, 0x00000000) returns 0x00 (0000ms, 30994ms total) +T3170 095:913 JLINK_WriteReg(R13 (SP), 0x20001000) returns 0x00 (0000ms, 30994ms total) +T3170 095:913 JLINK_WriteReg(R14, 0x20000001) returns 0x00 (0000ms, 30994ms total) +T3170 095:913 JLINK_WriteReg(R15 (PC), 0x2000005C) returns 0x00 (0000ms, 30994ms total) +T3170 095:913 JLINK_WriteReg(XPSR, 0x01000000) returns 0x00 (0000ms, 30994ms total) +T3170 095:913 JLINK_WriteReg(MSP, 0x20001000) returns 0x00 (0000ms, 30994ms total) +T3170 095:913 JLINK_WriteReg(PSP, 0x20001000) returns 0x00 (0000ms, 30994ms total) +T3170 095:913 JLINK_WriteReg(CFBP, 0x00000000) returns 0x00 (0000ms, 30994ms total) +T3170 095:913 JLINK_SetBPEx(Addr = 0x20000000, Type = 0xFFFFFFF2) returns 0x00000076 (0000ms, 30994ms total) +T3170 095:913 JLINK_Go() -- CPU_ReadMem(4 bytes @ 0xE0001000) (0089ms, 31083ms total) +T3170 096:002 JLINK_IsHalted() -- CPU_ReadMem(2 bytes @ 0x20000000) returns TRUE (0006ms, 31089ms total) +T3170 096:008 JLINK_ReadReg(R15 (PC)) returns 0x20000000 (0000ms, 31083ms total) +T3170 096:008 JLINK_ClrBPEx(BPHandle = 0x00000076) returns 0x00 (0000ms, 31083ms total) +T3170 096:008 JLINK_ReadReg(R0) returns 0x00000000 (0000ms, 31083ms total) +T3170 096:008 JLINK_WriteMem(0x20000144, 0x0080 Bytes, ...) - Data: 63 20 63 6F 64 65 3A 20 30 78 25 30 34 78 0A 00 ... -- CPU_WriteMem(128 bytes @ 0x20000144) returns 0x80 (0003ms, 31086ms total) +T3170 096:011 JLINK_WriteReg(R0, 0x00003380) returns 0x00 (0000ms, 31086ms total) +T3170 096:011 JLINK_WriteReg(R1, 0x00000080) returns 0x00 (0000ms, 31086ms total) +T3170 096:011 JLINK_WriteReg(R2, 0x20000144) returns 0x00 (0000ms, 31086ms total) +T3170 096:011 JLINK_WriteReg(R3, 0x00000000) returns 0x00 (0000ms, 31086ms total) +T3170 096:011 JLINK_WriteReg(R4, 0x00000000) returns 0x00 (0000ms, 31086ms total) +T3170 096:011 JLINK_WriteReg(R5, 0x00000000) returns 0x00 (0000ms, 31086ms total) +T3170 096:011 JLINK_WriteReg(R6, 0x00000000) returns 0x00 (0000ms, 31086ms total) +T3170 096:011 JLINK_WriteReg(R7, 0x00000000) returns 0x00 (0000ms, 31086ms total) +T3170 096:011 JLINK_WriteReg(R8, 0x00000000) returns 0x00 (0000ms, 31086ms total) +T3170 096:011 JLINK_WriteReg(R9, 0x2000013C) returns 0x00 (0000ms, 31086ms total) +T3170 096:011 JLINK_WriteReg(R10, 0x00000000) returns 0x00 (0000ms, 31086ms total) +T3170 096:011 JLINK_WriteReg(R11, 0x00000000) returns 0x00 (0000ms, 31086ms total) +T3170 096:011 JLINK_WriteReg(R12, 0x00000000) returns 0x00 (0000ms, 31086ms total) +T3170 096:011 JLINK_WriteReg(R13 (SP), 0x20001000) returns 0x00 (0000ms, 31086ms total) +T3170 096:011 JLINK_WriteReg(R14, 0x20000001) returns 0x00 (0000ms, 31086ms total) +T3170 096:011 JLINK_WriteReg(R15 (PC), 0x2000005C) returns 0x00 (0000ms, 31086ms total) +T3170 096:011 JLINK_WriteReg(XPSR, 0x01000000) returns 0x00 (0000ms, 31086ms total) +T3170 096:011 JLINK_WriteReg(MSP, 0x20001000) returns 0x00 (0000ms, 31086ms total) +T3170 096:011 JLINK_WriteReg(PSP, 0x20001000) returns 0x00 (0000ms, 31086ms total) +T3170 096:011 JLINK_WriteReg(CFBP, 0x00000000) returns 0x00 (0000ms, 31086ms total) +T3170 096:011 JLINK_SetBPEx(Addr = 0x20000000, Type = 0xFFFFFFF2) returns 0x00000077 (0000ms, 31086ms total) +T3170 096:011 JLINK_Go() -- CPU_ReadMem(4 bytes @ 0xE0001000) (0086ms, 31172ms total) +T3170 096:097 JLINK_IsHalted() -- CPU_ReadMem(2 bytes @ 0x20000000) returns TRUE (0007ms, 31179ms total) +T3170 096:104 JLINK_ReadReg(R15 (PC)) returns 0x20000000 (0000ms, 31172ms total) +T3170 096:104 JLINK_ClrBPEx(BPHandle = 0x00000077) returns 0x00 (0000ms, 31172ms total) +T3170 096:104 JLINK_ReadReg(R0) returns 0x00000000 (0000ms, 31172ms total) +T3170 096:104 JLINK_WriteMem(0x20000144, 0x0080 Bytes, ...) - Data: 13 E0 20 78 0A 28 04 D1 0D 21 0A 48 00 68 FD F7 ... -- CPU_WriteMem(128 bytes @ 0x20000144) returns 0x80 (0003ms, 31175ms total) +T3170 096:107 JLINK_WriteReg(R0, 0x00003400) returns 0x00 (0000ms, 31175ms total) +T3170 096:107 JLINK_WriteReg(R1, 0x00000080) returns 0x00 (0000ms, 31175ms total) +T3170 096:107 JLINK_WriteReg(R2, 0x20000144) returns 0x00 (0000ms, 31175ms total) +T3170 096:107 JLINK_WriteReg(R3, 0x00000000) returns 0x00 (0000ms, 31175ms total) +T3170 096:107 JLINK_WriteReg(R4, 0x00000000) returns 0x00 (0000ms, 31175ms total) +T3170 096:107 JLINK_WriteReg(R5, 0x00000000) returns 0x00 (0000ms, 31175ms total) +T3170 096:107 JLINK_WriteReg(R6, 0x00000000) returns 0x00 (0000ms, 31175ms total) +T3170 096:107 JLINK_WriteReg(R7, 0x00000000) returns 0x00 (0000ms, 31175ms total) +T3170 096:107 JLINK_WriteReg(R8, 0x00000000) returns 0x00 (0000ms, 31175ms total) +T3170 096:107 JLINK_WriteReg(R9, 0x2000013C) returns 0x00 (0000ms, 31175ms total) +T3170 096:107 JLINK_WriteReg(R10, 0x00000000) returns 0x00 (0000ms, 31175ms total) +T3170 096:107 JLINK_WriteReg(R11, 0x00000000) returns 0x00 (0000ms, 31175ms total) +T3170 096:107 JLINK_WriteReg(R12, 0x00000000) returns 0x00 (0000ms, 31175ms total) +T3170 096:107 JLINK_WriteReg(R13 (SP), 0x20001000) returns 0x00 (0000ms, 31175ms total) +T3170 096:107 JLINK_WriteReg(R14, 0x20000001) returns 0x00 (0000ms, 31175ms total) +T3170 096:107 JLINK_WriteReg(R15 (PC), 0x2000005C) returns 0x00 (0001ms, 31176ms total) +T3170 096:108 JLINK_WriteReg(XPSR, 0x01000000) returns 0x00 (0000ms, 31176ms total) +T3170 096:108 JLINK_WriteReg(MSP, 0x20001000) returns 0x00 (0000ms, 31176ms total) +T3170 096:108 JLINK_WriteReg(PSP, 0x20001000) returns 0x00 (0000ms, 31176ms total) +T3170 096:108 JLINK_WriteReg(CFBP, 0x00000000) returns 0x00 (0000ms, 31176ms total) +T3170 096:108 JLINK_SetBPEx(Addr = 0x20000000, Type = 0xFFFFFFF2) returns 0x00000078 (0000ms, 31176ms total) +T3170 096:108 JLINK_Go() -- CPU_ReadMem(4 bytes @ 0xE0001000) (0007ms, 31183ms total) +T3170 096:115 JLINK_IsHalted() -- CPU_ReadMem(2 bytes @ 0x20000000) returns TRUE (0092ms, 31275ms total) +T3170 096:207 JLINK_ReadReg(R15 (PC)) returns 0x20000000 (0000ms, 31183ms total) +T3170 096:207 JLINK_ClrBPEx(BPHandle = 0x00000078) returns 0x00 (0000ms, 31183ms total) +T3170 096:207 JLINK_ReadReg(R0) returns 0x00000000 (0000ms, 31183ms total) +T3170 096:208 JLINK_WriteMem(0x20000144, 0x0080 Bytes, ...) - Data: 35 A0 21 68 00 F0 6C F9 37 A0 61 68 00 F0 68 F9 ... -- CPU_WriteMem(128 bytes @ 0x20000144) returns 0x80 (0004ms, 31187ms total) +T3170 096:213 JLINK_WriteReg(R0, 0x00003480) returns 0x00 (0000ms, 31187ms total) +T3170 096:213 JLINK_WriteReg(R1, 0x00000080) returns 0x00 (0000ms, 31187ms total) +T3170 096:213 JLINK_WriteReg(R2, 0x20000144) returns 0x00 (0000ms, 31187ms total) +T3170 096:213 JLINK_WriteReg(R3, 0x00000000) returns 0x00 (0000ms, 31187ms total) +T3170 096:213 JLINK_WriteReg(R4, 0x00000000) returns 0x00 (0000ms, 31187ms total) +T3170 096:213 JLINK_WriteReg(R5, 0x00000000) returns 0x00 (0000ms, 31187ms total) +T3170 096:213 JLINK_WriteReg(R6, 0x00000000) returns 0x00 (0000ms, 31187ms total) +T3170 096:213 JLINK_WriteReg(R7, 0x00000000) returns 0x00 (0000ms, 31187ms total) +T3170 096:213 JLINK_WriteReg(R8, 0x00000000) returns 0x00 (0000ms, 31187ms total) +T3170 096:213 JLINK_WriteReg(R9, 0x2000013C) returns 0x00 (0000ms, 31187ms total) +T3170 096:213 JLINK_WriteReg(R10, 0x00000000) returns 0x00 (0000ms, 31187ms total) +T3170 096:213 JLINK_WriteReg(R11, 0x00000000) returns 0x00 (0000ms, 31187ms total) +T3170 096:213 JLINK_WriteReg(R12, 0x00000000) returns 0x00 (0000ms, 31187ms total) +T3170 096:213 JLINK_WriteReg(R13 (SP), 0x20001000) returns 0x00 (0000ms, 31187ms total) +T3170 096:213 JLINK_WriteReg(R14, 0x20000001) returns 0x00 (0000ms, 31187ms total) +T3170 096:213 JLINK_WriteReg(R15 (PC), 0x2000005C) returns 0x00 (0000ms, 31187ms total) +T3170 096:213 JLINK_WriteReg(XPSR, 0x01000000) returns 0x00 (0000ms, 31187ms total) +T3170 096:213 JLINK_WriteReg(MSP, 0x20001000) returns 0x00 (0000ms, 31187ms total) +T3170 096:213 JLINK_WriteReg(PSP, 0x20001000) returns 0x00 (0000ms, 31187ms total) +T3170 096:213 JLINK_WriteReg(CFBP, 0x00000000) returns 0x00 (0000ms, 31187ms total) +T3170 096:213 JLINK_SetBPEx(Addr = 0x20000000, Type = 0xFFFFFFF2) returns 0x00000079 (0000ms, 31187ms total) +T3170 096:213 JLINK_Go() -- CPU_ReadMem(4 bytes @ 0xE0001000) (0089ms, 31276ms total) +T3170 096:302 JLINK_IsHalted() -- CPU_ReadMem(2 bytes @ 0x20000000) returns TRUE (0007ms, 31283ms total) +T3170 096:309 JLINK_ReadReg(R15 (PC)) returns 0x20000000 (0000ms, 31276ms total) +T3170 096:309 JLINK_ClrBPEx(BPHandle = 0x00000079) returns 0x00 (0000ms, 31276ms total) +T3170 096:309 JLINK_ReadReg(R0) returns 0x00000000 (0000ms, 31276ms total) +T3170 096:309 JLINK_WriteMem(0x20000144, 0x0080 Bytes, ...) - Data: FE E7 00 00 DC 00 00 20 70 73 72 3A 20 30 78 25 ... -- CPU_WriteMem(128 bytes @ 0x20000144) returns 0x80 (0003ms, 31279ms total) +T3170 096:312 JLINK_WriteReg(R0, 0x00003500) returns 0x00 (0000ms, 31279ms total) +T3170 096:312 JLINK_WriteReg(R1, 0x00000080) returns 0x00 (0000ms, 31279ms total) +T3170 096:312 JLINK_WriteReg(R2, 0x20000144) returns 0x00 (0000ms, 31279ms total) +T3170 096:312 JLINK_WriteReg(R3, 0x00000000) returns 0x00 (0000ms, 31279ms total) +T3170 096:312 JLINK_WriteReg(R4, 0x00000000) returns 0x00 (0000ms, 31279ms total) +T3170 096:312 JLINK_WriteReg(R5, 0x00000000) returns 0x00 (0000ms, 31279ms total) +T3170 096:312 JLINK_WriteReg(R6, 0x00000000) returns 0x00 (0000ms, 31279ms total) +T3170 096:312 JLINK_WriteReg(R7, 0x00000000) returns 0x00 (0000ms, 31279ms total) +T3170 096:312 JLINK_WriteReg(R8, 0x00000000) returns 0x00 (0000ms, 31279ms total) +T3170 096:312 JLINK_WriteReg(R9, 0x2000013C) returns 0x00 (0000ms, 31279ms total) +T3170 096:312 JLINK_WriteReg(R10, 0x00000000) returns 0x00 (0000ms, 31279ms total) +T3170 096:312 JLINK_WriteReg(R11, 0x00000000) returns 0x00 (0000ms, 31279ms total) +T3170 096:312 JLINK_WriteReg(R12, 0x00000000) returns 0x00 (0000ms, 31279ms total) +T3170 096:312 JLINK_WriteReg(R13 (SP), 0x20001000) returns 0x00 (0000ms, 31279ms total) +T3170 096:312 JLINK_WriteReg(R14, 0x20000001) returns 0x00 (0000ms, 31279ms total) +T3170 096:312 JLINK_WriteReg(R15 (PC), 0x2000005C) returns 0x00 (0000ms, 31279ms total) +T3170 096:312 JLINK_WriteReg(XPSR, 0x01000000) returns 0x00 (0000ms, 31279ms total) +T3170 096:312 JLINK_WriteReg(MSP, 0x20001000) returns 0x00 (0000ms, 31279ms total) +T3170 096:312 JLINK_WriteReg(PSP, 0x20001000) returns 0x00 (0000ms, 31279ms total) +T3170 096:312 JLINK_WriteReg(CFBP, 0x00000000) returns 0x00 (0000ms, 31279ms total) +T3170 096:312 JLINK_SetBPEx(Addr = 0x20000000, Type = 0xFFFFFFF2) returns 0x0000007A (0000ms, 31279ms total) +T3170 096:312 JLINK_Go() -- CPU_ReadMem(4 bytes @ 0xE0001000) (0089ms, 31368ms total) +T3170 096:401 JLINK_IsHalted() -- CPU_ReadMem(2 bytes @ 0x20000000) returns TRUE (0008ms, 31376ms total) +T3170 096:409 JLINK_ReadReg(R15 (PC)) returns 0x20000000 (0000ms, 31368ms total) +T3170 096:409 JLINK_ClrBPEx(BPHandle = 0x0000007A) returns 0x00 (0000ms, 31368ms total) +T3170 096:409 JLINK_ReadReg(R0) returns 0x00000000 (0000ms, 31368ms total) +T3170 096:409 JLINK_WriteMem(0x20000144, 0x0080 Bytes, ...) - Data: 30 38 78 0A 00 00 00 00 72 30 37 3A 20 30 78 25 ... -- CPU_WriteMem(128 bytes @ 0x20000144) returns 0x80 (0004ms, 31372ms total) +T3170 096:413 JLINK_WriteReg(R0, 0x00003580) returns 0x00 (0000ms, 31372ms total) +T3170 096:413 JLINK_WriteReg(R1, 0x00000080) returns 0x00 (0000ms, 31372ms total) +T3170 096:413 JLINK_WriteReg(R2, 0x20000144) returns 0x00 (0000ms, 31372ms total) +T3170 096:413 JLINK_WriteReg(R3, 0x00000000) returns 0x00 (0000ms, 31372ms total) +T3170 096:413 JLINK_WriteReg(R4, 0x00000000) returns 0x00 (0000ms, 31372ms total) +T3170 096:413 JLINK_WriteReg(R5, 0x00000000) returns 0x00 (0000ms, 31372ms total) +T3170 096:413 JLINK_WriteReg(R6, 0x00000000) returns 0x00 (0000ms, 31372ms total) +T3170 096:413 JLINK_WriteReg(R7, 0x00000000) returns 0x00 (0000ms, 31372ms total) +T3170 096:413 JLINK_WriteReg(R8, 0x00000000) returns 0x00 (0000ms, 31372ms total) +T3170 096:413 JLINK_WriteReg(R9, 0x2000013C) returns 0x00 (0000ms, 31372ms total) +T3170 096:413 JLINK_WriteReg(R10, 0x00000000) returns 0x00 (0000ms, 31372ms total) +T3170 096:413 JLINK_WriteReg(R11, 0x00000000) returns 0x00 (0000ms, 31372ms total) +T3170 096:413 JLINK_WriteReg(R12, 0x00000000) returns 0x00 (0000ms, 31372ms total) +T3170 096:413 JLINK_WriteReg(R13 (SP), 0x20001000) returns 0x00 (0000ms, 31372ms total) +T3170 096:413 JLINK_WriteReg(R14, 0x20000001) returns 0x00 (0000ms, 31372ms total) +T3170 096:413 JLINK_WriteReg(R15 (PC), 0x2000005C) returns 0x00 (0000ms, 31372ms total) +T3170 096:413 JLINK_WriteReg(XPSR, 0x01000000) returns 0x00 (0000ms, 31372ms total) +T3170 096:413 JLINK_WriteReg(MSP, 0x20001000) returns 0x00 (0000ms, 31372ms total) +T3170 096:413 JLINK_WriteReg(PSP, 0x20001000) returns 0x00 (0000ms, 31372ms total) +T3170 096:413 JLINK_WriteReg(CFBP, 0x00000000) returns 0x00 (0000ms, 31372ms total) +T3170 096:413 JLINK_SetBPEx(Addr = 0x20000000, Type = 0xFFFFFFF2) returns 0x0000007B (0000ms, 31372ms total) +T3170 096:413 JLINK_Go() -- CPU_ReadMem(4 bytes @ 0xE0001000) (0090ms, 31462ms total) +T3170 096:504 JLINK_IsHalted() -- CPU_ReadMem(2 bytes @ 0x20000000) returns TRUE (0009ms, 31471ms total) +T3170 096:513 JLINK_ReadReg(R15 (PC)) returns 0x20000000 (0000ms, 31471ms total) +T3170 096:513 JLINK_ClrBPEx(BPHandle = 0x0000007B) returns 0x00 (0000ms, 31471ms total) +T3170 096:513 JLINK_ReadReg(R0) returns 0x00000000 (0000ms, 31471ms total) +T3170 096:513 JLINK_WriteMem(0x20000144, 0x0080 Bytes, ...) - Data: 30 38 78 0A 00 00 00 00 68 61 72 64 20 66 61 75 ... -- CPU_WriteMem(128 bytes @ 0x20000144) returns 0x80 (0003ms, 31474ms total) +T3170 096:517 JLINK_WriteReg(R0, 0x00003600) returns 0x00 (0000ms, 31475ms total) +T3170 096:517 JLINK_WriteReg(R1, 0x00000080) returns 0x00 (0000ms, 31475ms total) +T3170 096:517 JLINK_WriteReg(R2, 0x20000144) returns 0x00 (0000ms, 31475ms total) +T3170 096:517 JLINK_WriteReg(R3, 0x00000000) returns 0x00 (0000ms, 31475ms total) +T3170 096:517 JLINK_WriteReg(R4, 0x00000000) returns 0x00 (0000ms, 31475ms total) +T3170 096:517 JLINK_WriteReg(R5, 0x00000000) returns 0x00 (0000ms, 31475ms total) +T3170 096:517 JLINK_WriteReg(R6, 0x00000000) returns 0x00 (0000ms, 31475ms total) +T3170 096:517 JLINK_WriteReg(R7, 0x00000000) returns 0x00 (0000ms, 31475ms total) +T3170 096:517 JLINK_WriteReg(R8, 0x00000000) returns 0x00 (0000ms, 31475ms total) +T3170 096:517 JLINK_WriteReg(R9, 0x2000013C) returns 0x00 (0000ms, 31475ms total) +T3170 096:517 JLINK_WriteReg(R10, 0x00000000) returns 0x00 (0000ms, 31475ms total) +T3170 096:517 JLINK_WriteReg(R11, 0x00000000) returns 0x00 (0000ms, 31475ms total) +T3170 096:517 JLINK_WriteReg(R12, 0x00000000) returns 0x00 (0000ms, 31475ms total) +T3170 096:517 JLINK_WriteReg(R13 (SP), 0x20001000) returns 0x00 (0000ms, 31475ms total) +T3170 096:517 JLINK_WriteReg(R14, 0x20000001) returns 0x00 (0000ms, 31475ms total) +T3170 096:517 JLINK_WriteReg(R15 (PC), 0x2000005C) returns 0x00 (0000ms, 31475ms total) +T3170 096:517 JLINK_WriteReg(XPSR, 0x01000000) returns 0x00 (0000ms, 31475ms total) +T3170 096:517 JLINK_WriteReg(MSP, 0x20001000) returns 0x00 (0000ms, 31475ms total) +T3170 096:517 JLINK_WriteReg(PSP, 0x20001000) returns 0x00 (0000ms, 31475ms total) +T3170 096:517 JLINK_WriteReg(CFBP, 0x00000000) returns 0x00 (0000ms, 31475ms total) +T3170 096:517 JLINK_SetBPEx(Addr = 0x20000000, Type = 0xFFFFFFF2) returns 0x0000007C (0000ms, 31475ms total) +T3170 096:517 JLINK_Go() -- CPU_ReadMem(4 bytes @ 0xE0001000) (0087ms, 31562ms total) +T3170 096:604 JLINK_IsHalted() -- CPU_ReadMem(2 bytes @ 0x20000000) returns TRUE (0011ms, 31573ms total) +T3170 096:615 JLINK_ReadReg(R15 (PC)) returns 0x20000000 (0000ms, 31562ms total) +T3170 096:615 JLINK_ClrBPEx(BPHandle = 0x0000007C) returns 0x00 (0000ms, 31562ms total) +T3170 096:615 JLINK_ReadReg(R0) returns 0x00000000 (0000ms, 31562ms total) +T3170 096:615 JLINK_WriteMem(0x20000144, 0x0080 Bytes, ...) - Data: 4F F0 80 7C C1 F8 3C C0 F0 BD 00 00 EF BE AD DE ... -- CPU_WriteMem(128 bytes @ 0x20000144) returns 0x80 (0085ms, 31647ms total) +T3170 096:700 JLINK_WriteReg(R0, 0x00003680) returns 0x00 (0000ms, 31647ms total) +T3170 096:700 JLINK_WriteReg(R1, 0x00000080) returns 0x00 (0000ms, 31647ms total) +T3170 096:700 JLINK_WriteReg(R2, 0x20000144) returns 0x00 (0000ms, 31647ms total) +T3170 096:700 JLINK_WriteReg(R3, 0x00000000) returns 0x00 (0000ms, 31647ms total) +T3170 096:700 JLINK_WriteReg(R4, 0x00000000) returns 0x00 (0000ms, 31647ms total) +T3170 096:700 JLINK_WriteReg(R5, 0x00000000) returns 0x00 (0000ms, 31647ms total) +T3170 096:700 JLINK_WriteReg(R6, 0x00000000) returns 0x00 (0000ms, 31647ms total) +T3170 096:700 JLINK_WriteReg(R7, 0x00000000) returns 0x00 (0001ms, 31648ms total) +T3170 096:701 JLINK_WriteReg(R8, 0x00000000) returns 0x00 (0000ms, 31648ms total) +T3170 096:701 JLINK_WriteReg(R9, 0x2000013C) returns 0x00 (0000ms, 31648ms total) +T3170 096:701 JLINK_WriteReg(R10, 0x00000000) returns 0x00 (0000ms, 31648ms total) +T3170 096:701 JLINK_WriteReg(R11, 0x00000000) returns 0x00 (0000ms, 31648ms total) +T3170 096:701 JLINK_WriteReg(R12, 0x00000000) returns 0x00 (0000ms, 31648ms total) +T3170 096:701 JLINK_WriteReg(R13 (SP), 0x20001000) returns 0x00 (0000ms, 31648ms total) +T3170 096:701 JLINK_WriteReg(R14, 0x20000001) returns 0x00 (0000ms, 31648ms total) +T3170 096:701 JLINK_WriteReg(R15 (PC), 0x2000005C) returns 0x00 (0000ms, 31648ms total) +T3170 096:701 JLINK_WriteReg(XPSR, 0x01000000) returns 0x00 (0000ms, 31648ms total) +T3170 096:701 JLINK_WriteReg(MSP, 0x20001000) returns 0x00 (0000ms, 31648ms total) +T3170 096:701 JLINK_WriteReg(PSP, 0x20001000) returns 0x00 (0000ms, 31648ms total) +T3170 096:701 JLINK_WriteReg(CFBP, 0x00000000) returns 0x00 (0000ms, 31648ms total) +T3170 096:701 JLINK_SetBPEx(Addr = 0x20000000, Type = 0xFFFFFFF2) returns 0x0000007D (0000ms, 31648ms total) +T3170 096:701 JLINK_Go() -- CPU_ReadMem(4 bytes @ 0xE0001000) (0007ms, 31655ms total) +T3170 096:708 JLINK_IsHalted() -- CPU_ReadMem(2 bytes @ 0x20000000) returns TRUE (0005ms, 31660ms total) +T3170 096:713 JLINK_ReadReg(R15 (PC)) returns 0x20000000 (0000ms, 31655ms total) +T3170 096:713 JLINK_ClrBPEx(BPHandle = 0x0000007D) returns 0x00 (0001ms, 31656ms total) +T3170 096:714 JLINK_ReadReg(R0) returns 0x00000000 (0000ms, 31656ms total) +T3170 096:714 JLINK_WriteMem(0x20000144, 0x0080 Bytes, ...) - Data: 05 E0 04 F1 14 01 28 46 00 F0 60 F8 1C E0 2E 68 ... -- CPU_WriteMem(128 bytes @ 0x20000144) returns 0x80 (0013ms, 31669ms total) +T3170 096:799 JLINK_WriteReg(R0, 0x00003700) returns 0x00 (0000ms, 31669ms total) +T3170 096:799 JLINK_WriteReg(R1, 0x00000080) returns 0x00 (0000ms, 31669ms total) +T3170 096:799 JLINK_WriteReg(R2, 0x20000144) returns 0x00 (0000ms, 31669ms total) +T3170 096:799 JLINK_WriteReg(R3, 0x00000000) returns 0x00 (0000ms, 31669ms total) +T3170 096:799 JLINK_WriteReg(R4, 0x00000000) returns 0x00 (0000ms, 31669ms total) +T3170 096:799 JLINK_WriteReg(R5, 0x00000000) returns 0x00 (0000ms, 31669ms total) +T3170 096:799 JLINK_WriteReg(R6, 0x00000000) returns 0x00 (0000ms, 31669ms total) +T3170 096:799 JLINK_WriteReg(R7, 0x00000000) returns 0x00 (0000ms, 31669ms total) +T3170 096:799 JLINK_WriteReg(R8, 0x00000000) returns 0x00 (0000ms, 31669ms total) +T3170 096:799 JLINK_WriteReg(R9, 0x2000013C) returns 0x00 (0000ms, 31669ms total) +T3170 096:799 JLINK_WriteReg(R10, 0x00000000) returns 0x00 (0000ms, 31669ms total) +T3170 096:799 JLINK_WriteReg(R11, 0x00000000) returns 0x00 (0000ms, 31669ms total) +T3170 096:799 JLINK_WriteReg(R12, 0x00000000) returns 0x00 (0000ms, 31669ms total) +T3170 096:799 JLINK_WriteReg(R13 (SP), 0x20001000) returns 0x00 (0000ms, 31669ms total) +T3170 096:799 JLINK_WriteReg(R14, 0x20000001) returns 0x00 (0000ms, 31669ms total) +T3170 096:799 JLINK_WriteReg(R15 (PC), 0x2000005C) returns 0x00 (0000ms, 31669ms total) +T3170 096:799 JLINK_WriteReg(XPSR, 0x01000000) returns 0x00 (0000ms, 31669ms total) +T3170 096:799 JLINK_WriteReg(MSP, 0x20001000) returns 0x00 (0000ms, 31669ms total) +T3170 096:799 JLINK_WriteReg(PSP, 0x20001000) returns 0x00 (0000ms, 31669ms total) +T3170 096:799 JLINK_WriteReg(CFBP, 0x00000000) returns 0x00 (0000ms, 31669ms total) +T3170 096:799 JLINK_SetBPEx(Addr = 0x20000000, Type = 0xFFFFFFF2) returns 0x0000007E (0000ms, 31669ms total) +T3170 096:799 JLINK_Go() -- CPU_ReadMem(4 bytes @ 0xE0001000) (0008ms, 31677ms total) +T3170 096:807 JLINK_IsHalted() -- CPU_ReadMem(2 bytes @ 0x20000000) returns TRUE (0006ms, 31683ms total) +T3170 096:813 JLINK_ReadReg(R15 (PC)) returns 0x20000000 (0000ms, 31677ms total) +T3170 096:813 JLINK_ClrBPEx(BPHandle = 0x0000007E) returns 0x00 (0000ms, 31677ms total) +T3170 096:813 JLINK_ReadReg(R0) returns 0x00000000 (0000ms, 31677ms total) +T3170 096:813 JLINK_WriteMem(0x20000144, 0x0080 Bytes, ...) - Data: 3D FE 00 20 00 90 38 BC 5D F8 14 FB F8 12 00 20 ... -- CPU_WriteMem(128 bytes @ 0x20000144) returns 0x80 (0003ms, 31680ms total) +T3170 096:816 JLINK_WriteReg(R0, 0x00003780) returns 0x00 (0000ms, 31680ms total) +T3170 096:816 JLINK_WriteReg(R1, 0x00000080) returns 0x00 (0000ms, 31680ms total) +T3170 096:816 JLINK_WriteReg(R2, 0x20000144) returns 0x00 (0000ms, 31680ms total) +T3170 096:816 JLINK_WriteReg(R3, 0x00000000) returns 0x00 (0000ms, 31680ms total) +T3170 096:816 JLINK_WriteReg(R4, 0x00000000) returns 0x00 (0000ms, 31680ms total) +T3170 096:816 JLINK_WriteReg(R5, 0x00000000) returns 0x00 (0000ms, 31680ms total) +T3170 096:816 JLINK_WriteReg(R6, 0x00000000) returns 0x00 (0000ms, 31680ms total) +T3170 096:816 JLINK_WriteReg(R7, 0x00000000) returns 0x00 (0000ms, 31680ms total) +T3170 096:816 JLINK_WriteReg(R8, 0x00000000) returns 0x00 (0000ms, 31680ms total) +T3170 096:816 JLINK_WriteReg(R9, 0x2000013C) returns 0x00 (0000ms, 31680ms total) +T3170 096:816 JLINK_WriteReg(R10, 0x00000000) returns 0x00 (0000ms, 31680ms total) +T3170 096:816 JLINK_WriteReg(R11, 0x00000000) returns 0x00 (0000ms, 31680ms total) +T3170 096:816 JLINK_WriteReg(R12, 0x00000000) returns 0x00 (0000ms, 31680ms total) +T3170 096:816 JLINK_WriteReg(R13 (SP), 0x20001000) returns 0x00 (0000ms, 31680ms total) +T3170 096:816 JLINK_WriteReg(R14, 0x20000001) returns 0x00 (0000ms, 31680ms total) +T3170 096:816 JLINK_WriteReg(R15 (PC), 0x2000005C) returns 0x00 (0000ms, 31680ms total) +T3170 096:816 JLINK_WriteReg(XPSR, 0x01000000) returns 0x00 (0000ms, 31680ms total) +T3170 096:816 JLINK_WriteReg(MSP, 0x20001000) returns 0x00 (0000ms, 31680ms total) +T3170 096:816 JLINK_WriteReg(PSP, 0x20001000) returns 0x00 (0000ms, 31680ms total) +T3170 096:816 JLINK_WriteReg(CFBP, 0x00000000) returns 0x00 (0000ms, 31680ms total) +T3170 096:816 JLINK_SetBPEx(Addr = 0x20000000, Type = 0xFFFFFFF2) returns 0x0000007F (0000ms, 31680ms total) +T3170 096:816 JLINK_Go() -- CPU_ReadMem(4 bytes @ 0xE0001000) (0088ms, 31768ms total) +T3170 096:904 JLINK_IsHalted() -- CPU_ReadMem(2 bytes @ 0x20000000) returns TRUE (0005ms, 31773ms total) +T3170 096:912 JLINK_ReadReg(R15 (PC)) returns 0x20000000 (0000ms, 31773ms total) +T3170 096:912 JLINK_ClrBPEx(BPHandle = 0x0000007F) returns 0x00 (0000ms, 31773ms total) +T3170 096:912 JLINK_ReadReg(R0) returns 0x00000000 (0000ms, 31773ms total) +T3170 096:912 JLINK_WriteMem(0x20000144, 0x0080 Bytes, ...) - Data: 01 D1 01 20 70 47 00 20 FC E7 01 46 00 20 0A 46 ... -- CPU_WriteMem(128 bytes @ 0x20000144) returns 0x80 (0002ms, 31775ms total) +T3170 096:914 JLINK_WriteReg(R0, 0x00003800) returns 0x00 (0000ms, 31775ms total) +T3170 096:914 JLINK_WriteReg(R1, 0x00000080) returns 0x00 (0000ms, 31775ms total) +T3170 096:914 JLINK_WriteReg(R2, 0x20000144) returns 0x00 (0000ms, 31775ms total) +T3170 096:914 JLINK_WriteReg(R3, 0x00000000) returns 0x00 (0000ms, 31775ms total) +T3170 096:914 JLINK_WriteReg(R4, 0x00000000) returns 0x00 (0000ms, 31775ms total) +T3170 096:914 JLINK_WriteReg(R5, 0x00000000) returns 0x00 (0000ms, 31775ms total) +T3170 096:914 JLINK_WriteReg(R6, 0x00000000) returns 0x00 (0000ms, 31775ms total) +T3170 096:914 JLINK_WriteReg(R7, 0x00000000) returns 0x00 (0000ms, 31775ms total) +T3170 096:914 JLINK_WriteReg(R8, 0x00000000) returns 0x00 (0000ms, 31775ms total) +T3170 096:914 JLINK_WriteReg(R9, 0x2000013C) returns 0x00 (0000ms, 31775ms total) +T3170 096:914 JLINK_WriteReg(R10, 0x00000000) returns 0x00 (0000ms, 31775ms total) +T3170 096:914 JLINK_WriteReg(R11, 0x00000000) returns 0x00 (0000ms, 31775ms total) +T3170 096:914 JLINK_WriteReg(R12, 0x00000000) returns 0x00 (0000ms, 31775ms total) +T3170 096:914 JLINK_WriteReg(R13 (SP), 0x20001000) returns 0x00 (0000ms, 31775ms total) +T3170 096:914 JLINK_WriteReg(R14, 0x20000001) returns 0x00 (0000ms, 31775ms total) +T3170 096:914 JLINK_WriteReg(R15 (PC), 0x2000005C) returns 0x00 (0001ms, 31776ms total) +T3170 096:915 JLINK_WriteReg(XPSR, 0x01000000) returns 0x00 (0000ms, 31776ms total) +T3170 096:915 JLINK_WriteReg(MSP, 0x20001000) returns 0x00 (0000ms, 31776ms total) +T3170 096:915 JLINK_WriteReg(PSP, 0x20001000) returns 0x00 (0000ms, 31776ms total) +T3170 096:915 JLINK_WriteReg(CFBP, 0x00000000) returns 0x00 (0000ms, 31776ms total) +T3170 096:915 JLINK_SetBPEx(Addr = 0x20000000, Type = 0xFFFFFFF2) returns 0x00000080 (0000ms, 31776ms total) +T3170 096:915 JLINK_Go() -- CPU_ReadMem(4 bytes @ 0xE0001000) (0088ms, 31864ms total) +T3170 097:003 JLINK_IsHalted() -- CPU_ReadMem(2 bytes @ 0x20000000) returns TRUE (0006ms, 31870ms total) +T3170 097:009 JLINK_ReadReg(R15 (PC)) returns 0x20000000 (0000ms, 31864ms total) +T3170 097:009 JLINK_ClrBPEx(BPHandle = 0x00000080) returns 0x00 (0000ms, 31864ms total) +T3170 097:009 JLINK_ReadReg(R0) returns 0x00000000 (0000ms, 31864ms total) +T3170 097:009 JLINK_WriteMem(0x20000144, 0x0080 Bytes, ...) - Data: 47 48 00 68 84 19 60 88 00 28 74 D1 06 F1 0C 00 ... -- CPU_WriteMem(128 bytes @ 0x20000144) returns 0x80 (0003ms, 31867ms total) +T3170 097:012 JLINK_WriteReg(R0, 0x00003880) returns 0x00 (0000ms, 31867ms total) +T3170 097:012 JLINK_WriteReg(R1, 0x00000080) returns 0x00 (0000ms, 31867ms total) +T3170 097:012 JLINK_WriteReg(R2, 0x20000144) returns 0x00 (0000ms, 31867ms total) +T3170 097:012 JLINK_WriteReg(R3, 0x00000000) returns 0x00 (0000ms, 31867ms total) +T3170 097:012 JLINK_WriteReg(R4, 0x00000000) returns 0x00 (0000ms, 31867ms total) +T3170 097:012 JLINK_WriteReg(R5, 0x00000000) returns 0x00 (0000ms, 31867ms total) +T3170 097:012 JLINK_WriteReg(R6, 0x00000000) returns 0x00 (0000ms, 31867ms total) +T3170 097:012 JLINK_WriteReg(R7, 0x00000000) returns 0x00 (0000ms, 31867ms total) +T3170 097:012 JLINK_WriteReg(R8, 0x00000000) returns 0x00 (0000ms, 31867ms total) +T3170 097:012 JLINK_WriteReg(R9, 0x2000013C) returns 0x00 (0000ms, 31867ms total) +T3170 097:013 JLINK_WriteReg(R10, 0x00000000) returns 0x00 (0000ms, 31868ms total) +T3170 097:013 JLINK_WriteReg(R11, 0x00000000) returns 0x00 (0000ms, 31868ms total) +T3170 097:013 JLINK_WriteReg(R12, 0x00000000) returns 0x00 (0000ms, 31868ms total) +T3170 097:013 JLINK_WriteReg(R13 (SP), 0x20001000) returns 0x00 (0000ms, 31868ms total) +T3170 097:013 JLINK_WriteReg(R14, 0x20000001) returns 0x00 (0000ms, 31868ms total) +T3170 097:013 JLINK_WriteReg(R15 (PC), 0x2000005C) returns 0x00 (0000ms, 31868ms total) +T3170 097:013 JLINK_WriteReg(XPSR, 0x01000000) returns 0x00 (0000ms, 31868ms total) +T3170 097:013 JLINK_WriteReg(MSP, 0x20001000) returns 0x00 (0000ms, 31868ms total) +T3170 097:013 JLINK_WriteReg(PSP, 0x20001000) returns 0x00 (0000ms, 31868ms total) +T3170 097:013 JLINK_WriteReg(CFBP, 0x00000000) returns 0x00 (0000ms, 31868ms total) +T3170 097:013 JLINK_SetBPEx(Addr = 0x20000000, Type = 0xFFFFFFF2) returns 0x00000081 (0000ms, 31868ms total) +T3170 097:013 JLINK_Go() -- CPU_ReadMem(4 bytes @ 0xE0001000) (0087ms, 31955ms total) +T3170 097:100 JLINK_IsHalted() -- CPU_ReadMem(2 bytes @ 0x20000000) returns TRUE (0009ms, 31964ms total) +T3170 097:109 JLINK_ReadReg(R15 (PC)) returns 0x20000000 (0000ms, 31955ms total) +T3170 097:109 JLINK_ClrBPEx(BPHandle = 0x00000081) returns 0x00 (0000ms, 31955ms total) +T3170 097:109 JLINK_ReadReg(R0) returns 0x00000000 (0000ms, 31955ms total) +T3170 097:109 JLINK_WriteMem(0x20000144, 0x0080 Bytes, ...) - Data: 28 48 00 68 28 49 08 60 14 E0 01 20 60 80 24 49 ... -- CPU_WriteMem(128 bytes @ 0x20000144) returns 0x80 (0004ms, 31959ms total) +T3170 097:113 JLINK_WriteReg(R0, 0x00003900) returns 0x00 (0000ms, 31959ms total) +T3170 097:113 JLINK_WriteReg(R1, 0x00000080) returns 0x00 (0000ms, 31959ms total) +T3170 097:113 JLINK_WriteReg(R2, 0x20000144) returns 0x00 (0000ms, 31959ms total) +T3170 097:113 JLINK_WriteReg(R3, 0x00000000) returns 0x00 (0000ms, 31959ms total) +T3170 097:113 JLINK_WriteReg(R4, 0x00000000) returns 0x00 (0000ms, 31959ms total) +T3170 097:113 JLINK_WriteReg(R5, 0x00000000) returns 0x00 (0000ms, 31959ms total) +T3170 097:113 JLINK_WriteReg(R6, 0x00000000) returns 0x00 (0000ms, 31959ms total) +T3170 097:113 JLINK_WriteReg(R7, 0x00000000) returns 0x00 (0000ms, 31959ms total) +T3170 097:113 JLINK_WriteReg(R8, 0x00000000) returns 0x00 (0000ms, 31959ms total) +T3170 097:113 JLINK_WriteReg(R9, 0x2000013C) returns 0x00 (0000ms, 31959ms total) +T3170 097:113 JLINK_WriteReg(R10, 0x00000000) returns 0x00 (0000ms, 31959ms total) +T3170 097:113 JLINK_WriteReg(R11, 0x00000000) returns 0x00 (0000ms, 31959ms total) +T3170 097:113 JLINK_WriteReg(R12, 0x00000000) returns 0x00 (0000ms, 31959ms total) +T3170 097:113 JLINK_WriteReg(R13 (SP), 0x20001000) returns 0x00 (0000ms, 31959ms total) +T3170 097:113 JLINK_WriteReg(R14, 0x20000001) returns 0x00 (0000ms, 31959ms total) +T3170 097:113 JLINK_WriteReg(R15 (PC), 0x2000005C) returns 0x00 (0000ms, 31959ms total) +T3170 097:113 JLINK_WriteReg(XPSR, 0x01000000) returns 0x00 (0000ms, 31959ms total) +T3170 097:113 JLINK_WriteReg(MSP, 0x20001000) returns 0x00 (0000ms, 31959ms total) +T3170 097:113 JLINK_WriteReg(PSP, 0x20001000) returns 0x00 (0000ms, 31959ms total) +T3170 097:113 JLINK_WriteReg(CFBP, 0x00000000) returns 0x00 (0000ms, 31959ms total) +T3170 097:113 JLINK_SetBPEx(Addr = 0x20000000, Type = 0xFFFFFFF2) returns 0x00000082 (0000ms, 31959ms total) +T3170 097:113 JLINK_Go() -- CPU_ReadMem(4 bytes @ 0xE0001000) (0089ms, 32048ms total) +T3170 097:202 JLINK_IsHalted() -- CPU_ReadMem(2 bytes @ 0x20000000) returns TRUE (0010ms, 32058ms total) +T3170 097:212 JLINK_ReadReg(R15 (PC)) returns 0x20000000 (0000ms, 32048ms total) +T3170 097:212 JLINK_ClrBPEx(BPHandle = 0x00000082) returns 0x00 (0000ms, 32048ms total) +T3170 097:212 JLINK_ReadReg(R0) returns 0x00000000 (0000ms, 32048ms total) +T3170 097:212 JLINK_WriteMem(0x20000144, 0x0080 Bytes, ...) - Data: 00 68 40 1B B0 42 3F F6 7B AF 03 48 00 F0 EB F9 ... -- CPU_WriteMem(128 bytes @ 0x20000144) returns 0x80 (0004ms, 32052ms total) +T3170 097:216 JLINK_WriteReg(R0, 0x00003980) returns 0x00 (0000ms, 32052ms total) +T3170 097:216 JLINK_WriteReg(R1, 0x00000080) returns 0x00 (0000ms, 32052ms total) +T3170 097:216 JLINK_WriteReg(R2, 0x20000144) returns 0x00 (0000ms, 32052ms total) +T3170 097:216 JLINK_WriteReg(R3, 0x00000000) returns 0x00 (0000ms, 32052ms total) +T3170 097:216 JLINK_WriteReg(R4, 0x00000000) returns 0x00 (0000ms, 32052ms total) +T3170 097:216 JLINK_WriteReg(R5, 0x00000000) returns 0x00 (0000ms, 32052ms total) +T3170 097:216 JLINK_WriteReg(R6, 0x00000000) returns 0x00 (0000ms, 32052ms total) +T3170 097:216 JLINK_WriteReg(R7, 0x00000000) returns 0x00 (0000ms, 32052ms total) +T3170 097:216 JLINK_WriteReg(R8, 0x00000000) returns 0x00 (0000ms, 32052ms total) +T3170 097:216 JLINK_WriteReg(R9, 0x2000013C) returns 0x00 (0000ms, 32052ms total) +T3170 097:216 JLINK_WriteReg(R10, 0x00000000) returns 0x00 (0000ms, 32052ms total) +T3170 097:216 JLINK_WriteReg(R11, 0x00000000) returns 0x00 (0000ms, 32052ms total) +T3170 097:216 JLINK_WriteReg(R12, 0x00000000) returns 0x00 (0000ms, 32052ms total) +T3170 097:216 JLINK_WriteReg(R13 (SP), 0x20001000) returns 0x00 (0000ms, 32052ms total) +T3170 097:216 JLINK_WriteReg(R14, 0x20000001) returns 0x00 (0000ms, 32052ms total) +T3170 097:216 JLINK_WriteReg(R15 (PC), 0x2000005C) returns 0x00 (0000ms, 32052ms total) +T3170 097:216 JLINK_WriteReg(XPSR, 0x01000000) returns 0x00 (0000ms, 32052ms total) +T3170 097:216 JLINK_WriteReg(MSP, 0x20001000) returns 0x00 (0000ms, 32052ms total) +T3170 097:216 JLINK_WriteReg(PSP, 0x20001000) returns 0x00 (0000ms, 32052ms total) +T3170 097:216 JLINK_WriteReg(CFBP, 0x00000000) returns 0x00 (0000ms, 32052ms total) +T3170 097:216 JLINK_SetBPEx(Addr = 0x20000000, Type = 0xFFFFFFF2) returns 0x00000083 (0000ms, 32052ms total) +T3170 097:216 JLINK_Go() -- CPU_ReadMem(4 bytes @ 0xE0001000) (0087ms, 32139ms total) +T3170 097:303 JLINK_IsHalted() -- CPU_ReadMem(2 bytes @ 0x20000000) returns TRUE (0007ms, 32146ms total) +T3170 097:310 JLINK_ReadReg(R15 (PC)) returns 0x20000000 (0000ms, 32139ms total) +T3170 097:310 JLINK_ClrBPEx(BPHandle = 0x00000083) returns 0x00 (0000ms, 32139ms total) +T3170 097:310 JLINK_ReadReg(R0) returns 0x00000000 (0000ms, 32139ms total) +T3170 097:310 JLINK_WriteMem(0x20000144, 0x0080 Bytes, ...) - Data: 03 07 97 B9 01 46 46 EA 06 23 43 EA 03 43 04 E0 ... -- CPU_WriteMem(128 bytes @ 0x20000144) returns 0x80 (0003ms, 32142ms total) +T3170 097:313 JLINK_WriteReg(R0, 0x00003A00) returns 0x00 (0000ms, 32142ms total) +T3170 097:313 JLINK_WriteReg(R1, 0x00000080) returns 0x00 (0000ms, 32142ms total) +T3170 097:313 JLINK_WriteReg(R2, 0x20000144) returns 0x00 (0000ms, 32142ms total) +T3170 097:313 JLINK_WriteReg(R3, 0x00000000) returns 0x00 (0000ms, 32142ms total) +T3170 097:313 JLINK_WriteReg(R4, 0x00000000) returns 0x00 (0000ms, 32142ms total) +T3170 097:313 JLINK_WriteReg(R5, 0x00000000) returns 0x00 (0000ms, 32142ms total) +T3170 097:313 JLINK_WriteReg(R6, 0x00000000) returns 0x00 (0000ms, 32142ms total) +T3170 097:313 JLINK_WriteReg(R7, 0x00000000) returns 0x00 (0000ms, 32142ms total) +T3170 097:313 JLINK_WriteReg(R8, 0x00000000) returns 0x00 (0000ms, 32142ms total) +T3170 097:313 JLINK_WriteReg(R9, 0x2000013C) returns 0x00 (0001ms, 32143ms total) +T3170 097:314 JLINK_WriteReg(R10, 0x00000000) returns 0x00 (0000ms, 32143ms total) +T3170 097:314 JLINK_WriteReg(R11, 0x00000000) returns 0x00 (0000ms, 32143ms total) +T3170 097:314 JLINK_WriteReg(R12, 0x00000000) returns 0x00 (0000ms, 32143ms total) +T3170 097:314 JLINK_WriteReg(R13 (SP), 0x20001000) returns 0x00 (0000ms, 32143ms total) +T3170 097:314 JLINK_WriteReg(R14, 0x20000001) returns 0x00 (0000ms, 32143ms total) +T3170 097:314 JLINK_WriteReg(R15 (PC), 0x2000005C) returns 0x00 (0000ms, 32143ms total) +T3170 097:314 JLINK_WriteReg(XPSR, 0x01000000) returns 0x00 (0000ms, 32143ms total) +T3170 097:314 JLINK_WriteReg(MSP, 0x20001000) returns 0x00 (0000ms, 32143ms total) +T3170 097:314 JLINK_WriteReg(PSP, 0x20001000) returns 0x00 (0000ms, 32143ms total) +T3170 097:314 JLINK_WriteReg(CFBP, 0x00000000) returns 0x00 (0000ms, 32143ms total) +T3170 097:314 JLINK_SetBPEx(Addr = 0x20000000, Type = 0xFFFFFFF2) returns 0x00000084 (0000ms, 32143ms total) +T3170 097:314 JLINK_Go() -- CPU_ReadMem(4 bytes @ 0xE0001000) (0088ms, 32231ms total) +T3170 097:402 JLINK_IsHalted() -- CPU_ReadMem(2 bytes @ 0x20000000) returns TRUE (0009ms, 32240ms total) +T3170 097:411 JLINK_ReadReg(R15 (PC)) returns 0x20000000 (0000ms, 32231ms total) +T3170 097:411 JLINK_ClrBPEx(BPHandle = 0x00000084) returns 0x00 (0000ms, 32231ms total) +T3170 097:411 JLINK_ReadReg(R0) returns 0x00000000 (0000ms, 32231ms total) +T3170 097:411 JLINK_WriteMem(0x20000144, 0x0080 Bytes, ...) - Data: FF F7 8F FE 40 46 FC F7 73 FC 20 46 E3 E7 70 B5 ... -- CPU_WriteMem(128 bytes @ 0x20000144) returns 0x80 (0003ms, 32234ms total) +T3170 097:414 JLINK_WriteReg(R0, 0x00003A80) returns 0x00 (0000ms, 32234ms total) +T3170 097:414 JLINK_WriteReg(R1, 0x00000080) returns 0x00 (0000ms, 32234ms total) +T3170 097:414 JLINK_WriteReg(R2, 0x20000144) returns 0x00 (0000ms, 32234ms total) +T3170 097:414 JLINK_WriteReg(R3, 0x00000000) returns 0x00 (0000ms, 32234ms total) +T3170 097:414 JLINK_WriteReg(R4, 0x00000000) returns 0x00 (0000ms, 32234ms total) +T3170 097:414 JLINK_WriteReg(R5, 0x00000000) returns 0x00 (0000ms, 32234ms total) +T3170 097:414 JLINK_WriteReg(R6, 0x00000000) returns 0x00 (0000ms, 32234ms total) +T3170 097:414 JLINK_WriteReg(R7, 0x00000000) returns 0x00 (0000ms, 32234ms total) +T3170 097:414 JLINK_WriteReg(R8, 0x00000000) returns 0x00 (0000ms, 32234ms total) +T3170 097:414 JLINK_WriteReg(R9, 0x2000013C) returns 0x00 (0000ms, 32234ms total) +T3170 097:414 JLINK_WriteReg(R10, 0x00000000) returns 0x00 (0000ms, 32234ms total) +T3170 097:414 JLINK_WriteReg(R11, 0x00000000) returns 0x00 (0000ms, 32234ms total) +T3170 097:414 JLINK_WriteReg(R12, 0x00000000) returns 0x00 (0000ms, 32234ms total) +T3170 097:414 JLINK_WriteReg(R13 (SP), 0x20001000) returns 0x00 (0000ms, 32234ms total) +T3170 097:415 JLINK_WriteReg(R14, 0x20000001) returns 0x00 (0000ms, 32234ms total) +T3170 097:415 JLINK_WriteReg(R15 (PC), 0x2000005C) returns 0x00 (0000ms, 32234ms total) +T3170 097:415 JLINK_WriteReg(XPSR, 0x01000000) returns 0x00 (0000ms, 32234ms total) +T3170 097:415 JLINK_WriteReg(MSP, 0x20001000) returns 0x00 (0000ms, 32234ms total) +T3170 097:415 JLINK_WriteReg(PSP, 0x20001000) returns 0x00 (0000ms, 32234ms total) +T3170 097:415 JLINK_WriteReg(CFBP, 0x00000000) returns 0x00 (0000ms, 32234ms total) +T3170 097:415 JLINK_SetBPEx(Addr = 0x20000000, Type = 0xFFFFFFF2) returns 0x00000085 (0000ms, 32234ms total) +T3170 097:415 JLINK_Go() -- CPU_ReadMem(4 bytes @ 0xE0001000) (0090ms, 32324ms total) +T3170 097:505 JLINK_IsHalted() -- CPU_ReadMem(2 bytes @ 0x20000000) returns TRUE (0009ms, 32333ms total) +T3170 097:514 JLINK_ReadReg(R15 (PC)) returns 0x20000000 (0000ms, 32324ms total) +T3170 097:514 JLINK_ClrBPEx(BPHandle = 0x00000085) returns 0x00 (0000ms, 32324ms total) +T3170 097:514 JLINK_ReadReg(R0) returns 0x00000000 (0000ms, 32324ms total) +T3170 097:514 JLINK_WriteMem(0x20000144, 0x0080 Bytes, ...) - Data: 90 46 00 26 28 46 FF F7 E3 FF 07 46 FF F7 A2 FB ... -- CPU_WriteMem(128 bytes @ 0x20000144) returns 0x80 (0013ms, 32337ms total) +T3170 097:527 JLINK_WriteReg(R0, 0x00003B00) returns 0x00 (0000ms, 32337ms total) +T3170 097:527 JLINK_WriteReg(R1, 0x00000080) returns 0x00 (0000ms, 32337ms total) +T3170 097:527 JLINK_WriteReg(R2, 0x20000144) returns 0x00 (0000ms, 32337ms total) +T3170 097:527 JLINK_WriteReg(R3, 0x00000000) returns 0x00 (0000ms, 32337ms total) +T3170 097:527 JLINK_WriteReg(R4, 0x00000000) returns 0x00 (0000ms, 32337ms total) +T3170 097:527 JLINK_WriteReg(R5, 0x00000000) returns 0x00 (0000ms, 32337ms total) +T3170 097:527 JLINK_WriteReg(R6, 0x00000000) returns 0x00 (0000ms, 32337ms total) +T3170 097:527 JLINK_WriteReg(R7, 0x00000000) returns 0x00 (0000ms, 32337ms total) +T3170 097:527 JLINK_WriteReg(R8, 0x00000000) returns 0x00 (0000ms, 32337ms total) +T3170 097:527 JLINK_WriteReg(R9, 0x2000013C) returns 0x00 (0000ms, 32337ms total) +T3170 097:527 JLINK_WriteReg(R10, 0x00000000) returns 0x00 (0000ms, 32337ms total) +T3170 097:527 JLINK_WriteReg(R11, 0x00000000) returns 0x00 (0000ms, 32337ms total) +T3170 097:527 JLINK_WriteReg(R12, 0x00000000) returns 0x00 (0000ms, 32337ms total) +T3170 097:527 JLINK_WriteReg(R13 (SP), 0x20001000) returns 0x00 (0000ms, 32337ms total) +T3170 097:527 JLINK_WriteReg(R14, 0x20000001) returns 0x00 (0000ms, 32337ms total) +T3170 097:527 JLINK_WriteReg(R15 (PC), 0x2000005C) returns 0x00 (0000ms, 32337ms total) +T3170 097:527 JLINK_WriteReg(XPSR, 0x01000000) returns 0x00 (0000ms, 32337ms total) +T3170 097:527 JLINK_WriteReg(MSP, 0x20001000) returns 0x00 (0000ms, 32337ms total) +T3170 097:527 JLINK_WriteReg(PSP, 0x20001000) returns 0x00 (0000ms, 32337ms total) +T3170 097:527 JLINK_WriteReg(CFBP, 0x00000000) returns 0x00 (0000ms, 32337ms total) +T3170 097:527 JLINK_SetBPEx(Addr = 0x20000000, Type = 0xFFFFFFF2) returns 0x00000086 (0000ms, 32337ms total) +T3170 097:527 JLINK_Go() -- CPU_ReadMem(4 bytes @ 0xE0001000) (0077ms, 32414ms total) +T3170 097:604 JLINK_IsHalted() -- CPU_ReadMem(2 bytes @ 0x20000000) returns TRUE (0006ms, 32420ms total) +T3170 097:610 JLINK_ReadReg(R15 (PC)) returns 0x20000000 (0000ms, 32414ms total) +T3170 097:610 JLINK_ClrBPEx(BPHandle = 0x00000086) returns 0x00 (0000ms, 32414ms total) +T3170 097:610 JLINK_ReadReg(R0) returns 0x00000000 (0000ms, 32414ms total) +T3170 097:610 JLINK_WriteMem(0x20000144, 0x0080 Bytes, ...) - Data: 04 46 3B 48 00 68 90 F8 34 00 00 F0 07 00 03 28 ... -- CPU_WriteMem(128 bytes @ 0x20000144) returns 0x80 (0003ms, 32417ms total) +T3170 097:613 JLINK_WriteReg(R0, 0x00003B80) returns 0x00 (0000ms, 32417ms total) +T3170 097:613 JLINK_WriteReg(R1, 0x00000080) returns 0x00 (0000ms, 32417ms total) +T3170 097:613 JLINK_WriteReg(R2, 0x20000144) returns 0x00 (0000ms, 32417ms total) +T3170 097:613 JLINK_WriteReg(R3, 0x00000000) returns 0x00 (0000ms, 32417ms total) +T3170 097:613 JLINK_WriteReg(R4, 0x00000000) returns 0x00 (0000ms, 32417ms total) +T3170 097:613 JLINK_WriteReg(R5, 0x00000000) returns 0x00 (0000ms, 32417ms total) +T3170 097:613 JLINK_WriteReg(R6, 0x00000000) returns 0x00 (0000ms, 32417ms total) +T3170 097:613 JLINK_WriteReg(R7, 0x00000000) returns 0x00 (0000ms, 32417ms total) +T3170 097:613 JLINK_WriteReg(R8, 0x00000000) returns 0x00 (0000ms, 32417ms total) +T3170 097:613 JLINK_WriteReg(R9, 0x2000013C) returns 0x00 (0000ms, 32417ms total) +T3170 097:613 JLINK_WriteReg(R10, 0x00000000) returns 0x00 (0000ms, 32417ms total) +T3170 097:613 JLINK_WriteReg(R11, 0x00000000) returns 0x00 (0000ms, 32417ms total) +T3170 097:613 JLINK_WriteReg(R12, 0x00000000) returns 0x00 (0000ms, 32417ms total) +T3170 097:613 JLINK_WriteReg(R13 (SP), 0x20001000) returns 0x00 (0000ms, 32417ms total) +T3170 097:613 JLINK_WriteReg(R14, 0x20000001) returns 0x00 (0000ms, 32417ms total) +T3170 097:613 JLINK_WriteReg(R15 (PC), 0x2000005C) returns 0x00 (0000ms, 32417ms total) +T3170 097:613 JLINK_WriteReg(XPSR, 0x01000000) returns 0x00 (0000ms, 32417ms total) +T3170 097:613 JLINK_WriteReg(MSP, 0x20001000) returns 0x00 (0000ms, 32417ms total) +T3170 097:613 JLINK_WriteReg(PSP, 0x20001000) returns 0x00 (0000ms, 32417ms total) +T3170 097:613 JLINK_WriteReg(CFBP, 0x00000000) returns 0x00 (0001ms, 32418ms total) +T3170 097:614 JLINK_SetBPEx(Addr = 0x20000000, Type = 0xFFFFFFF2) returns 0x00000087 (0000ms, 32418ms total) +T3170 097:614 JLINK_Go() -- CPU_ReadMem(4 bytes @ 0xE0001000) (0088ms, 32506ms total) +T3170 097:703 JLINK_IsHalted() -- CPU_ReadMem(2 bytes @ 0x20000000) returns TRUE (0010ms, 32517ms total) +T3170 097:713 JLINK_ReadReg(R15 (PC)) returns 0x20000000 (0000ms, 32507ms total) +T3170 097:713 JLINK_ClrBPEx(BPHandle = 0x00000087) returns 0x00 (0000ms, 32507ms total) +T3170 097:713 JLINK_ReadReg(R0) returns 0x00000000 (0000ms, 32507ms total) +T3170 097:713 JLINK_WriteMem(0x20000144, 0x0080 Bytes, ...) - Data: 94 F8 34 00 20 F0 07 00 40 F0 03 00 84 F8 34 00 ... -- CPU_WriteMem(128 bytes @ 0x20000144) returns 0x80 (0047ms, 32554ms total) +T3170 097:760 JLINK_WriteReg(R0, 0x00003C00) returns 0x00 (0000ms, 32554ms total) +T3170 097:760 JLINK_WriteReg(R1, 0x00000080) returns 0x00 (0000ms, 32554ms total) +T3170 097:760 JLINK_WriteReg(R2, 0x20000144) returns 0x00 (0000ms, 32554ms total) +T3170 097:760 JLINK_WriteReg(R3, 0x00000000) returns 0x00 (0000ms, 32554ms total) +T3170 097:761 JLINK_WriteReg(R4, 0x00000000) returns 0x00 (0000ms, 32555ms total) +T3170 097:761 JLINK_WriteReg(R5, 0x00000000) returns 0x00 (0000ms, 32555ms total) +T3170 097:761 JLINK_WriteReg(R6, 0x00000000) returns 0x00 (0000ms, 32555ms total) +T3170 097:761 JLINK_WriteReg(R7, 0x00000000) returns 0x00 (0000ms, 32555ms total) +T3170 097:761 JLINK_WriteReg(R8, 0x00000000) returns 0x00 (0000ms, 32555ms total) +T3170 097:761 JLINK_WriteReg(R9, 0x2000013C) returns 0x00 (0000ms, 32555ms total) +T3170 097:761 JLINK_WriteReg(R10, 0x00000000) returns 0x00 (0000ms, 32555ms total) +T3170 097:761 JLINK_WriteReg(R11, 0x00000000) returns 0x00 (0000ms, 32555ms total) +T3170 097:761 JLINK_WriteReg(R12, 0x00000000) returns 0x00 (0000ms, 32555ms total) +T3170 097:761 JLINK_WriteReg(R13 (SP), 0x20001000) returns 0x00 (0000ms, 32555ms total) +T3170 097:761 JLINK_WriteReg(R14, 0x20000001) returns 0x00 (0000ms, 32555ms total) +T3170 097:761 JLINK_WriteReg(R15 (PC), 0x2000005C) returns 0x00 (0000ms, 32555ms total) +T3170 097:761 JLINK_WriteReg(XPSR, 0x01000000) returns 0x00 (0000ms, 32555ms total) +T3170 097:761 JLINK_WriteReg(MSP, 0x20001000) returns 0x00 (0000ms, 32555ms total) +T3170 097:761 JLINK_WriteReg(PSP, 0x20001000) returns 0x00 (0000ms, 32555ms total) +T3170 097:761 JLINK_WriteReg(CFBP, 0x00000000) returns 0x00 (0000ms, 32555ms total) +T3170 097:761 JLINK_SetBPEx(Addr = 0x20000000, Type = 0xFFFFFFF2) returns 0x00000088 (0000ms, 32555ms total) +T3170 097:761 JLINK_Go() -- CPU_ReadMem(4 bytes @ 0xE0001000) (0044ms, 32599ms total) +T3170 097:805 JLINK_IsHalted() -- CPU_ReadMem(2 bytes @ 0x20000000) returns TRUE (0009ms, 32608ms total) +T3170 097:814 JLINK_ReadReg(R15 (PC)) returns 0x20000000 (0000ms, 32599ms total) +T3170 097:814 JLINK_ClrBPEx(BPHandle = 0x00000088) returns 0x00 (0000ms, 32599ms total) +T3170 097:814 JLINK_ReadReg(R0) returns 0x00000000 (0000ms, 32599ms total) +T3170 097:814 JLINK_WriteMem(0x20000144, 0x0080 Bytes, ...) - Data: FC F7 72 FB 05 46 16 48 00 68 84 42 08 D1 94 F8 ... -- CPU_WriteMem(128 bytes @ 0x20000144) returns 0x80 (0086ms, 32685ms total) +T3170 097:900 JLINK_WriteReg(R0, 0x00003C80) returns 0x00 (0000ms, 32685ms total) +T3170 097:900 JLINK_WriteReg(R1, 0x00000080) returns 0x00 (0000ms, 32685ms total) +T3170 097:900 JLINK_WriteReg(R2, 0x20000144) returns 0x00 (0000ms, 32685ms total) +T3170 097:900 JLINK_WriteReg(R3, 0x00000000) returns 0x00 (0000ms, 32685ms total) +T3170 097:900 JLINK_WriteReg(R4, 0x00000000) returns 0x00 (0000ms, 32685ms total) +T3170 097:900 JLINK_WriteReg(R5, 0x00000000) returns 0x00 (0000ms, 32685ms total) +T3170 097:900 JLINK_WriteReg(R6, 0x00000000) returns 0x00 (0000ms, 32685ms total) +T3170 097:900 JLINK_WriteReg(R7, 0x00000000) returns 0x00 (0001ms, 32686ms total) +T3170 097:901 JLINK_WriteReg(R8, 0x00000000) returns 0x00 (0000ms, 32686ms total) +T3170 097:901 JLINK_WriteReg(R9, 0x2000013C) returns 0x00 (0000ms, 32686ms total) +T3170 097:901 JLINK_WriteReg(R10, 0x00000000) returns 0x00 (0000ms, 32686ms total) +T3170 097:901 JLINK_WriteReg(R11, 0x00000000) returns 0x00 (0000ms, 32686ms total) +T3170 097:901 JLINK_WriteReg(R12, 0x00000000) returns 0x00 (0000ms, 32686ms total) +T3170 097:901 JLINK_WriteReg(R13 (SP), 0x20001000) returns 0x00 (0000ms, 32686ms total) +T3170 097:901 JLINK_WriteReg(R14, 0x20000001) returns 0x00 (0000ms, 32686ms total) +T3170 097:901 JLINK_WriteReg(R15 (PC), 0x2000005C) returns 0x00 (0000ms, 32686ms total) +T3170 097:901 JLINK_WriteReg(XPSR, 0x01000000) returns 0x00 (0000ms, 32686ms total) +T3170 097:901 JLINK_WriteReg(MSP, 0x20001000) returns 0x00 (0000ms, 32686ms total) +T3170 097:901 JLINK_WriteReg(PSP, 0x20001000) returns 0x00 (0000ms, 32686ms total) +T3170 097:901 JLINK_WriteReg(CFBP, 0x00000000) returns 0x00 (0000ms, 32686ms total) +T3170 097:901 JLINK_SetBPEx(Addr = 0x20000000, Type = 0xFFFFFFF2) returns 0x00000089 (0000ms, 32686ms total) +T3170 097:901 JLINK_Go() -- CPU_ReadMem(4 bytes @ 0xE0001000) (0008ms, 32694ms total) +T3170 097:909 JLINK_IsHalted() -- CPU_ReadMem(2 bytes @ 0x20000000) returns TRUE (0051ms, 32745ms total) +T3170 097:960 JLINK_ReadReg(R15 (PC)) returns 0x20000000 (0000ms, 32694ms total) +T3170 097:960 JLINK_ClrBPEx(BPHandle = 0x00000089) returns 0x00 (0000ms, 32694ms total) +T3170 097:960 JLINK_ReadReg(R0) returns 0x00000000 (0000ms, 32694ms total) +T3170 097:961 JLINK_WriteMem(0x20000144, 0x0080 Bytes, ...) - Data: D0 E9 00 12 11 60 40 60 00 60 00 BF 94 F8 35 10 ... -- CPU_WriteMem(128 bytes @ 0x20000144) returns 0x80 (0040ms, 32734ms total) +T3170 098:001 JLINK_WriteReg(R0, 0x00003D00) returns 0x00 (0000ms, 32734ms total) +T3170 098:001 JLINK_WriteReg(R1, 0x00000080) returns 0x00 (0000ms, 32734ms total) +T3170 098:001 JLINK_WriteReg(R2, 0x20000144) returns 0x00 (0000ms, 32734ms total) +T3170 098:001 JLINK_WriteReg(R3, 0x00000000) returns 0x00 (0000ms, 32734ms total) +T3170 098:001 JLINK_WriteReg(R4, 0x00000000) returns 0x00 (0000ms, 32734ms total) +T3170 098:001 JLINK_WriteReg(R5, 0x00000000) returns 0x00 (0000ms, 32734ms total) +T3170 098:001 JLINK_WriteReg(R6, 0x00000000) returns 0x00 (0000ms, 32734ms total) +T3170 098:001 JLINK_WriteReg(R7, 0x00000000) returns 0x00 (0000ms, 32734ms total) +T3170 098:001 JLINK_WriteReg(R8, 0x00000000) returns 0x00 (0000ms, 32734ms total) +T3170 098:001 JLINK_WriteReg(R9, 0x2000013C) returns 0x00 (0000ms, 32734ms total) +T3170 098:001 JLINK_WriteReg(R10, 0x00000000) returns 0x00 (0000ms, 32734ms total) +T3170 098:001 JLINK_WriteReg(R11, 0x00000000) returns 0x00 (0000ms, 32734ms total) +T3170 098:001 JLINK_WriteReg(R12, 0x00000000) returns 0x00 (0000ms, 32734ms total) +T3170 098:001 JLINK_WriteReg(R13 (SP), 0x20001000) returns 0x00 (0000ms, 32734ms total) +T3170 098:001 JLINK_WriteReg(R14, 0x20000001) returns 0x00 (0000ms, 32734ms total) +T3170 098:001 JLINK_WriteReg(R15 (PC), 0x2000005C) returns 0x00 (0000ms, 32734ms total) +T3170 098:001 JLINK_WriteReg(XPSR, 0x01000000) returns 0x00 (0000ms, 32734ms total) +T3170 098:001 JLINK_WriteReg(MSP, 0x20001000) returns 0x00 (0000ms, 32734ms total) +T3170 098:001 JLINK_WriteReg(PSP, 0x20001000) returns 0x00 (0000ms, 32734ms total) +T3170 098:001 JLINK_WriteReg(CFBP, 0x00000000) returns 0x00 (0000ms, 32734ms total) +T3170 098:001 JLINK_SetBPEx(Addr = 0x20000000, Type = 0xFFFFFFF2) returns 0x0000008A (0000ms, 32734ms total) +T3170 098:001 JLINK_Go() -- CPU_ReadMem(4 bytes @ 0xE0001000) (0009ms, 32743ms total) +T3170 098:010 JLINK_IsHalted() -- CPU_ReadMem(2 bytes @ 0x20000000) returns TRUE (0090ms, 32833ms total) +T3170 098:100 JLINK_ReadReg(R15 (PC)) returns 0x20000000 (0000ms, 32743ms total) +T3170 098:104 JLINK_ClrBPEx(BPHandle = 0x0000008A) returns 0x00 (0000ms, 32743ms total) +T3170 098:104 JLINK_ReadReg(R0) returns 0x00000000 (0000ms, 32743ms total) +T3170 098:104 JLINK_WriteMem(0x20000144, 0x0080 Bytes, ...) - Data: FF F7 A6 FC 01 25 02 E0 A0 8B 40 1C A0 83 30 46 ... -- CPU_WriteMem(128 bytes @ 0x20000144) returns 0x80 (0003ms, 32746ms total) +T3170 098:107 JLINK_WriteReg(R0, 0x00003D80) returns 0x00 (0000ms, 32746ms total) +T3170 098:107 JLINK_WriteReg(R1, 0x00000080) returns 0x00 (0000ms, 32746ms total) +T3170 098:107 JLINK_WriteReg(R2, 0x20000144) returns 0x00 (0000ms, 32746ms total) +T3170 098:107 JLINK_WriteReg(R3, 0x00000000) returns 0x00 (0000ms, 32746ms total) +T3170 098:107 JLINK_WriteReg(R4, 0x00000000) returns 0x00 (0000ms, 32746ms total) +T3170 098:107 JLINK_WriteReg(R5, 0x00000000) returns 0x00 (0000ms, 32746ms total) +T3170 098:107 JLINK_WriteReg(R6, 0x00000000) returns 0x00 (0000ms, 32746ms total) +T3170 098:107 JLINK_WriteReg(R7, 0x00000000) returns 0x00 (0000ms, 32746ms total) +T3170 098:107 JLINK_WriteReg(R8, 0x00000000) returns 0x00 (0000ms, 32746ms total) +T3170 098:107 JLINK_WriteReg(R9, 0x2000013C) returns 0x00 (0000ms, 32746ms total) +T3170 098:107 JLINK_WriteReg(R10, 0x00000000) returns 0x00 (0000ms, 32746ms total) +T3170 098:107 JLINK_WriteReg(R11, 0x00000000) returns 0x00 (0000ms, 32746ms total) +T3170 098:107 JLINK_WriteReg(R12, 0x00000000) returns 0x00 (0000ms, 32746ms total) +T3170 098:107 JLINK_WriteReg(R13 (SP), 0x20001000) returns 0x00 (0000ms, 32746ms total) +T3170 098:107 JLINK_WriteReg(R14, 0x20000001) returns 0x00 (0000ms, 32746ms total) +T3170 098:107 JLINK_WriteReg(R15 (PC), 0x2000005C) returns 0x00 (0000ms, 32746ms total) +T3170 098:107 JLINK_WriteReg(XPSR, 0x01000000) returns 0x00 (0000ms, 32746ms total) +T3170 098:107 JLINK_WriteReg(MSP, 0x20001000) returns 0x00 (0000ms, 32746ms total) +T3170 098:107 JLINK_WriteReg(PSP, 0x20001000) returns 0x00 (0000ms, 32746ms total) +T3170 098:107 JLINK_WriteReg(CFBP, 0x00000000) returns 0x00 (0000ms, 32746ms total) +T3170 098:107 JLINK_SetBPEx(Addr = 0x20000000, Type = 0xFFFFFFF2) returns 0x0000008B (0000ms, 32746ms total) +T3170 098:107 JLINK_Go() -- CPU_ReadMem(4 bytes @ 0xE0001000) (0008ms, 32754ms total) +T3170 098:115 JLINK_IsHalted() -- CPU_ReadMem(2 bytes @ 0x20000000) returns TRUE (0090ms, 32844ms total) +T3170 098:205 JLINK_ReadReg(R15 (PC)) returns 0x20000000 (0000ms, 32754ms total) +T3170 098:205 JLINK_ClrBPEx(BPHandle = 0x0000008B) returns 0x00 (0000ms, 32754ms total) +T3170 098:205 JLINK_ReadReg(R0) returns 0x00000000 (0000ms, 32754ms total) +T3170 098:205 JLINK_WriteMem(0x20000144, 0x0080 Bytes, ...) - Data: FC F7 B6 FA FF F7 AC FE 20 6B 08 B1 20 6B DD E7 ... -- CPU_WriteMem(128 bytes @ 0x20000144) returns 0x80 (0004ms, 32758ms total) +T3170 098:209 JLINK_WriteReg(R0, 0x00003E00) returns 0x00 (0000ms, 32758ms total) +T3170 098:209 JLINK_WriteReg(R1, 0x00000080) returns 0x00 (0000ms, 32758ms total) +T3170 098:209 JLINK_WriteReg(R2, 0x20000144) returns 0x00 (0000ms, 32758ms total) +T3170 098:209 JLINK_WriteReg(R3, 0x00000000) returns 0x00 (0000ms, 32758ms total) +T3170 098:209 JLINK_WriteReg(R4, 0x00000000) returns 0x00 (0000ms, 32758ms total) +T3170 098:209 JLINK_WriteReg(R5, 0x00000000) returns 0x00 (0000ms, 32758ms total) +T3170 098:209 JLINK_WriteReg(R6, 0x00000000) returns 0x00 (0000ms, 32758ms total) +T3170 098:210 JLINK_WriteReg(R7, 0x00000000) returns 0x00 (0000ms, 32759ms total) +T3170 098:210 JLINK_WriteReg(R8, 0x00000000) returns 0x00 (0000ms, 32759ms total) +T3170 098:210 JLINK_WriteReg(R9, 0x2000013C) returns 0x00 (0000ms, 32759ms total) +T3170 098:210 JLINK_WriteReg(R10, 0x00000000) returns 0x00 (0000ms, 32759ms total) +T3170 098:210 JLINK_WriteReg(R11, 0x00000000) returns 0x00 (0000ms, 32759ms total) +T3170 098:210 JLINK_WriteReg(R12, 0x00000000) returns 0x00 (0000ms, 32759ms total) +T3170 098:210 JLINK_WriteReg(R13 (SP), 0x20001000) returns 0x00 (0000ms, 32759ms total) +T3170 098:210 JLINK_WriteReg(R14, 0x20000001) returns 0x00 (0000ms, 32759ms total) +T3170 098:210 JLINK_WriteReg(R15 (PC), 0x2000005C) returns 0x00 (0000ms, 32759ms total) +T3170 098:210 JLINK_WriteReg(XPSR, 0x01000000) returns 0x00 (0000ms, 32759ms total) +T3170 098:210 JLINK_WriteReg(MSP, 0x20001000) returns 0x00 (0000ms, 32759ms total) +T3170 098:210 JLINK_WriteReg(PSP, 0x20001000) returns 0x00 (0000ms, 32759ms total) +T3170 098:210 JLINK_WriteReg(CFBP, 0x00000000) returns 0x00 (0000ms, 32759ms total) +T3170 098:210 JLINK_SetBPEx(Addr = 0x20000000, Type = 0xFFFFFFF2) returns 0x0000008C (0000ms, 32759ms total) +T3170 098:210 JLINK_Go() -- CPU_ReadMem(4 bytes @ 0xE0001000) (0006ms, 32765ms total) +T3170 098:216 JLINK_IsHalted() -- CPU_ReadMem(2 bytes @ 0x20000000) returns TRUE (0090ms, 32855ms total) +T3170 098:306 JLINK_ReadReg(R15 (PC)) returns 0x20000000 (0000ms, 32765ms total) +T3170 098:306 JLINK_ClrBPEx(BPHandle = 0x0000008C) returns 0x00 (0000ms, 32765ms total) +T3170 098:306 JLINK_ReadReg(R0) returns 0x00000000 (0000ms, 32765ms total) +T3170 098:306 JLINK_WriteMem(0x20000144, 0x0080 Bytes, ...) - Data: 20 20 20 25 64 2E 25 64 2E 25 64 20 62 75 69 6C ... -- CPU_WriteMem(128 bytes @ 0x20000144) returns 0x80 (0003ms, 32768ms total) +T3170 098:309 JLINK_WriteReg(R0, 0x00003E80) returns 0x00 (0000ms, 32768ms total) +T3170 098:309 JLINK_WriteReg(R1, 0x00000080) returns 0x00 (0000ms, 32768ms total) +T3170 098:309 JLINK_WriteReg(R2, 0x20000144) returns 0x00 (0000ms, 32768ms total) +T3170 098:309 JLINK_WriteReg(R3, 0x00000000) returns 0x00 (0000ms, 32768ms total) +T3170 098:309 JLINK_WriteReg(R4, 0x00000000) returns 0x00 (0000ms, 32768ms total) +T3170 098:309 JLINK_WriteReg(R5, 0x00000000) returns 0x00 (0000ms, 32768ms total) +T3170 098:309 JLINK_WriteReg(R6, 0x00000000) returns 0x00 (0000ms, 32768ms total) +T3170 098:309 JLINK_WriteReg(R7, 0x00000000) returns 0x00 (0000ms, 32768ms total) +T3170 098:309 JLINK_WriteReg(R8, 0x00000000) returns 0x00 (0000ms, 32768ms total) +T3170 098:309 JLINK_WriteReg(R9, 0x2000013C) returns 0x00 (0000ms, 32768ms total) +T3170 098:309 JLINK_WriteReg(R10, 0x00000000) returns 0x00 (0000ms, 32768ms total) +T3170 098:309 JLINK_WriteReg(R11, 0x00000000) returns 0x00 (0000ms, 32768ms total) +T3170 098:309 JLINK_WriteReg(R12, 0x00000000) returns 0x00 (0000ms, 32768ms total) +T3170 098:309 JLINK_WriteReg(R13 (SP), 0x20001000) returns 0x00 (0000ms, 32768ms total) +T3170 098:309 JLINK_WriteReg(R14, 0x20000001) returns 0x00 (0000ms, 32768ms total) +T3170 098:309 JLINK_WriteReg(R15 (PC), 0x2000005C) returns 0x00 (0000ms, 32768ms total) +T3170 098:309 JLINK_WriteReg(XPSR, 0x01000000) returns 0x00 (0000ms, 32768ms total) +T3170 098:309 JLINK_WriteReg(MSP, 0x20001000) returns 0x00 (0000ms, 32768ms total) +T3170 098:309 JLINK_WriteReg(PSP, 0x20001000) returns 0x00 (0000ms, 32768ms total) +T3170 098:309 JLINK_WriteReg(CFBP, 0x00000000) returns 0x00 (0000ms, 32768ms total) +T3170 098:309 JLINK_SetBPEx(Addr = 0x20000000, Type = 0xFFFFFFF2) returns 0x0000008D (0000ms, 32768ms total) +T3170 098:309 JLINK_Go() -- CPU_ReadMem(4 bytes @ 0xE0001000) (0007ms, 32775ms total) +T3170 098:316 JLINK_IsHalted() -- CPU_ReadMem(2 bytes @ 0x20000000) returns TRUE (0090ms, 32865ms total) +T3170 098:406 JLINK_ReadReg(R15 (PC)) returns 0x20000000 (0000ms, 32775ms total) +T3170 098:406 JLINK_ClrBPEx(BPHandle = 0x0000008D) returns 0x00 (0000ms, 32775ms total) +T3170 098:406 JLINK_ReadReg(R0) returns 0x00000000 (0000ms, 32775ms total) +T3170 098:406 JLINK_WriteMem(0x20000144, 0x0080 Bytes, ...) - Data: 0C 46 00 BF 14 F8 01 6B 00 F8 01 6B 3E B9 02 E0 ... -- CPU_WriteMem(128 bytes @ 0x20000144) returns 0x80 (0004ms, 32779ms total) +T3170 098:410 JLINK_WriteReg(R0, 0x00003F00) returns 0x00 (0000ms, 32779ms total) +T3170 098:410 JLINK_WriteReg(R1, 0x00000080) returns 0x00 (0000ms, 32779ms total) +T3170 098:410 JLINK_WriteReg(R2, 0x20000144) returns 0x00 (0000ms, 32779ms total) +T3170 098:410 JLINK_WriteReg(R3, 0x00000000) returns 0x00 (0000ms, 32779ms total) +T3170 098:410 JLINK_WriteReg(R4, 0x00000000) returns 0x00 (0000ms, 32779ms total) +T3170 098:410 JLINK_WriteReg(R5, 0x00000000) returns 0x00 (0000ms, 32779ms total) +T3170 098:410 JLINK_WriteReg(R6, 0x00000000) returns 0x00 (0000ms, 32779ms total) +T3170 098:410 JLINK_WriteReg(R7, 0x00000000) returns 0x00 (0000ms, 32779ms total) +T3170 098:410 JLINK_WriteReg(R8, 0x00000000) returns 0x00 (0000ms, 32779ms total) +T3170 098:410 JLINK_WriteReg(R9, 0x2000013C) returns 0x00 (0000ms, 32779ms total) +T3170 098:410 JLINK_WriteReg(R10, 0x00000000) returns 0x00 (0000ms, 32779ms total) +T3170 098:410 JLINK_WriteReg(R11, 0x00000000) returns 0x00 (0000ms, 32779ms total) +T3170 098:410 JLINK_WriteReg(R12, 0x00000000) returns 0x00 (0000ms, 32779ms total) +T3170 098:410 JLINK_WriteReg(R13 (SP), 0x20001000) returns 0x00 (0000ms, 32779ms total) +T3170 098:410 JLINK_WriteReg(R14, 0x20000001) returns 0x00 (0000ms, 32779ms total) +T3170 098:410 JLINK_WriteReg(R15 (PC), 0x2000005C) returns 0x00 (0000ms, 32779ms total) +T3170 098:410 JLINK_WriteReg(XPSR, 0x01000000) returns 0x00 (0000ms, 32779ms total) +T3170 098:410 JLINK_WriteReg(MSP, 0x20001000) returns 0x00 (0000ms, 32779ms total) +T3170 098:410 JLINK_WriteReg(PSP, 0x20001000) returns 0x00 (0000ms, 32779ms total) +T3170 098:410 JLINK_WriteReg(CFBP, 0x00000000) returns 0x00 (0000ms, 32779ms total) +T3170 098:410 JLINK_SetBPEx(Addr = 0x20000000, Type = 0xFFFFFFF2) returns 0x0000008E (0000ms, 32779ms total) +T3170 098:410 JLINK_Go() -- CPU_ReadMem(4 bytes @ 0xE0001000) (0006ms, 32785ms total) +T3170 098:416 JLINK_IsHalted() -- CPU_ReadMem(2 bytes @ 0x20000000) returns TRUE (0090ms, 32875ms total) +T3170 098:506 JLINK_ReadReg(R15 (PC)) returns 0x20000000 (0000ms, 32785ms total) +T3170 098:506 JLINK_ClrBPEx(BPHandle = 0x0000008E) returns 0x00 (0000ms, 32785ms total) +T3170 098:506 JLINK_ReadReg(R0) returns 0x00000000 (0000ms, 32785ms total) +T3170 098:506 JLINK_WriteMem(0x20000144, 0x0080 Bytes, ...) - Data: 22 49 60 68 09 68 08 44 21 49 08 60 4F F4 F5 50 ... -- CPU_WriteMem(128 bytes @ 0x20000144) returns 0x80 (0003ms, 32788ms total) +T3170 098:509 JLINK_WriteReg(R0, 0x00003F80) returns 0x00 (0000ms, 32788ms total) +T3170 098:509 JLINK_WriteReg(R1, 0x00000080) returns 0x00 (0000ms, 32788ms total) +T3170 098:509 JLINK_WriteReg(R2, 0x20000144) returns 0x00 (0000ms, 32788ms total) +T3170 098:509 JLINK_WriteReg(R3, 0x00000000) returns 0x00 (0000ms, 32788ms total) +T3170 098:509 JLINK_WriteReg(R4, 0x00000000) returns 0x00 (0000ms, 32788ms total) +T3170 098:509 JLINK_WriteReg(R5, 0x00000000) returns 0x00 (0000ms, 32788ms total) +T3170 098:509 JLINK_WriteReg(R6, 0x00000000) returns 0x00 (0000ms, 32788ms total) +T3170 098:509 JLINK_WriteReg(R7, 0x00000000) returns 0x00 (0000ms, 32788ms total) +T3170 098:509 JLINK_WriteReg(R8, 0x00000000) returns 0x00 (0000ms, 32788ms total) +T3170 098:509 JLINK_WriteReg(R9, 0x2000013C) returns 0x00 (0000ms, 32788ms total) +T3170 098:509 JLINK_WriteReg(R10, 0x00000000) returns 0x00 (0000ms, 32788ms total) +T3170 098:509 JLINK_WriteReg(R11, 0x00000000) returns 0x00 (0000ms, 32788ms total) +T3170 098:509 JLINK_WriteReg(R12, 0x00000000) returns 0x00 (0000ms, 32788ms total) +T3170 098:509 JLINK_WriteReg(R13 (SP), 0x20001000) returns 0x00 (0000ms, 32788ms total) +T3170 098:509 JLINK_WriteReg(R14, 0x20000001) returns 0x00 (0000ms, 32788ms total) +T3170 098:509 JLINK_WriteReg(R15 (PC), 0x2000005C) returns 0x00 (0000ms, 32788ms total) +T3170 098:509 JLINK_WriteReg(XPSR, 0x01000000) returns 0x00 (0000ms, 32788ms total) +T3170 098:509 JLINK_WriteReg(MSP, 0x20001000) returns 0x00 (0000ms, 32788ms total) +T3170 098:509 JLINK_WriteReg(PSP, 0x20001000) returns 0x00 (0000ms, 32788ms total) +T3170 098:509 JLINK_WriteReg(CFBP, 0x00000000) returns 0x00 (0000ms, 32788ms total) +T3170 098:509 JLINK_SetBPEx(Addr = 0x20000000, Type = 0xFFFFFFF2) returns 0x0000008F (0000ms, 32788ms total) +T3170 098:509 JLINK_Go() -- CPU_ReadMem(4 bytes @ 0xE0001000) (0007ms, 32795ms total) +T3170 098:516 JLINK_IsHalted() -- CPU_ReadMem(2 bytes @ 0x20000000) returns TRUE (0091ms, 32886ms total) +T3170 098:608 JLINK_ReadReg(R15 (PC)) returns 0x20000000 (0000ms, 32795ms total) +T3170 098:608 JLINK_ClrBPEx(BPHandle = 0x0000008F) returns 0x00 (0000ms, 32795ms total) +T3170 098:608 JLINK_ReadReg(R0) returns 0x00000000 (0000ms, 32795ms total) +T3170 098:608 JLINK_WriteMem(0x20000144, 0x0080 Bytes, ...) - Data: 65 73 73 20 30 78 25 78 0A 00 00 00 24 00 00 20 ... -- CPU_WriteMem(128 bytes @ 0x20000144) returns 0x80 (0003ms, 32798ms total) +T3170 098:612 JLINK_WriteReg(R0, 0x00004000) returns 0x00 (0000ms, 32799ms total) +T3170 098:612 JLINK_WriteReg(R1, 0x00000080) returns 0x00 (0000ms, 32799ms total) +T3170 098:612 JLINK_WriteReg(R2, 0x20000144) returns 0x00 (0000ms, 32799ms total) +T3170 098:612 JLINK_WriteReg(R3, 0x00000000) returns 0x00 (0000ms, 32799ms total) +T3170 098:612 JLINK_WriteReg(R4, 0x00000000) returns 0x00 (0000ms, 32799ms total) +T3170 098:612 JLINK_WriteReg(R5, 0x00000000) returns 0x00 (0000ms, 32799ms total) +T3170 098:612 JLINK_WriteReg(R6, 0x00000000) returns 0x00 (0000ms, 32799ms total) +T3170 098:612 JLINK_WriteReg(R7, 0x00000000) returns 0x00 (0000ms, 32799ms total) +T3170 098:612 JLINK_WriteReg(R8, 0x00000000) returns 0x00 (0000ms, 32799ms total) +T3170 098:612 JLINK_WriteReg(R9, 0x2000013C) returns 0x00 (0000ms, 32799ms total) +T3170 098:612 JLINK_WriteReg(R10, 0x00000000) returns 0x00 (0000ms, 32799ms total) +T3170 098:612 JLINK_WriteReg(R11, 0x00000000) returns 0x00 (0000ms, 32799ms total) +T3170 098:612 JLINK_WriteReg(R12, 0x00000000) returns 0x00 (0000ms, 32799ms total) +T3170 098:612 JLINK_WriteReg(R13 (SP), 0x20001000) returns 0x00 (0000ms, 32799ms total) +T3170 098:612 JLINK_WriteReg(R14, 0x20000001) returns 0x00 (0000ms, 32799ms total) +T3170 098:612 JLINK_WriteReg(R15 (PC), 0x2000005C) returns 0x00 (0000ms, 32799ms total) +T3170 098:612 JLINK_WriteReg(XPSR, 0x01000000) returns 0x00 (0000ms, 32799ms total) +T3170 098:612 JLINK_WriteReg(MSP, 0x20001000) returns 0x00 (0000ms, 32799ms total) +T3170 098:612 JLINK_WriteReg(PSP, 0x20001000) returns 0x00 (0000ms, 32799ms total) +T3170 098:612 JLINK_WriteReg(CFBP, 0x00000000) returns 0x00 (0000ms, 32799ms total) +T3170 098:612 JLINK_SetBPEx(Addr = 0x20000000, Type = 0xFFFFFFF2) returns 0x00000090 (0000ms, 32799ms total) +T3170 098:612 JLINK_Go() -- CPU_ReadMem(4 bytes @ 0xE0001000) (0020ms, 32819ms total) +T3170 098:632 JLINK_IsHalted() -- CPU_ReadMem(2 bytes @ 0x20000000) returns TRUE (0074ms, 32893ms total) +T3170 098:706 JLINK_ReadReg(R15 (PC)) returns 0x20000000 (0001ms, 32820ms total) +T3170 098:707 JLINK_ClrBPEx(BPHandle = 0x00000090) returns 0x00 (0000ms, 32820ms total) +T3170 098:707 JLINK_ReadReg(R0) returns 0x00000000 (0000ms, 32820ms total) +T3170 098:707 JLINK_WriteMem(0x20000144, 0x0080 Bytes, ...) - Data: A8 F9 38 BD B4 00 00 20 10 B5 00 24 05 E0 04 49 ... -- CPU_WriteMem(128 bytes @ 0x20000144) returns 0x80 (0002ms, 32822ms total) +T3170 098:709 JLINK_WriteReg(R0, 0x00004080) returns 0x00 (0000ms, 32822ms total) +T3170 098:709 JLINK_WriteReg(R1, 0x00000080) returns 0x00 (0000ms, 32822ms total) +T3170 098:709 JLINK_WriteReg(R2, 0x20000144) returns 0x00 (0000ms, 32822ms total) +T3170 098:709 JLINK_WriteReg(R3, 0x00000000) returns 0x00 (0000ms, 32822ms total) +T3170 098:709 JLINK_WriteReg(R4, 0x00000000) returns 0x00 (0000ms, 32822ms total) +T3170 098:709 JLINK_WriteReg(R5, 0x00000000) returns 0x00 (0000ms, 32822ms total) +T3170 098:709 JLINK_WriteReg(R6, 0x00000000) returns 0x00 (0000ms, 32822ms total) +T3170 098:709 JLINK_WriteReg(R7, 0x00000000) returns 0x00 (0000ms, 32822ms total) +T3170 098:709 JLINK_WriteReg(R8, 0x00000000) returns 0x00 (0000ms, 32822ms total) +T3170 098:709 JLINK_WriteReg(R9, 0x2000013C) returns 0x00 (0000ms, 32822ms total) +T3170 098:709 JLINK_WriteReg(R10, 0x00000000) returns 0x00 (0000ms, 32822ms total) +T3170 098:709 JLINK_WriteReg(R11, 0x00000000) returns 0x00 (0000ms, 32822ms total) +T3170 098:709 JLINK_WriteReg(R12, 0x00000000) returns 0x00 (0000ms, 32822ms total) +T3170 098:709 JLINK_WriteReg(R13 (SP), 0x20001000) returns 0x00 (0000ms, 32822ms total) +T3170 098:709 JLINK_WriteReg(R14, 0x20000001) returns 0x00 (0000ms, 32822ms total) +T3170 098:709 JLINK_WriteReg(R15 (PC), 0x2000005C) returns 0x00 (0000ms, 32822ms total) +T3170 098:709 JLINK_WriteReg(XPSR, 0x01000000) returns 0x00 (0000ms, 32822ms total) +T3170 098:709 JLINK_WriteReg(MSP, 0x20001000) returns 0x00 (0000ms, 32822ms total) +T3170 098:709 JLINK_WriteReg(PSP, 0x20001000) returns 0x00 (0000ms, 32822ms total) +T3170 098:709 JLINK_WriteReg(CFBP, 0x00000000) returns 0x00 (0000ms, 32822ms total) +T3170 098:709 JLINK_SetBPEx(Addr = 0x20000000, Type = 0xFFFFFFF2) returns 0x00000091 (0000ms, 32822ms total) +T3170 098:709 JLINK_Go() -- CPU_ReadMem(4 bytes @ 0xE0001000) (0007ms, 32829ms total) +T3170 098:716 JLINK_IsHalted() -- CPU_ReadMem(2 bytes @ 0x20000000) returns TRUE (0090ms, 32919ms total) +T3170 098:806 JLINK_ReadReg(R15 (PC)) returns 0x20000000 (0000ms, 32829ms total) +T3170 098:806 JLINK_ClrBPEx(BPHandle = 0x00000091) returns 0x00 (0000ms, 32829ms total) +T3170 098:806 JLINK_ReadReg(R0) returns 0x00000000 (0000ms, 32829ms total) +T3170 098:806 JLINK_WriteMem(0x20000144, 0x0080 Bytes, ...) - Data: FC F7 32 F9 05 46 20 46 FF F7 F0 FD 04 20 84 F8 ... -- CPU_WriteMem(128 bytes @ 0x20000144) returns 0x80 (0003ms, 32832ms total) +T3170 098:809 JLINK_WriteReg(R0, 0x00004100) returns 0x00 (0000ms, 32832ms total) +T3170 098:809 JLINK_WriteReg(R1, 0x00000080) returns 0x00 (0000ms, 32832ms total) +T3170 098:809 JLINK_WriteReg(R2, 0x20000144) returns 0x00 (0000ms, 32832ms total) +T3170 098:809 JLINK_WriteReg(R3, 0x00000000) returns 0x00 (0000ms, 32832ms total) +T3170 098:809 JLINK_WriteReg(R4, 0x00000000) returns 0x00 (0000ms, 32832ms total) +T3170 098:809 JLINK_WriteReg(R5, 0x00000000) returns 0x00 (0000ms, 32832ms total) +T3170 098:809 JLINK_WriteReg(R6, 0x00000000) returns 0x00 (0000ms, 32832ms total) +T3170 098:809 JLINK_WriteReg(R7, 0x00000000) returns 0x00 (0000ms, 32832ms total) +T3170 098:809 JLINK_WriteReg(R8, 0x00000000) returns 0x00 (0000ms, 32832ms total) +T3170 098:809 JLINK_WriteReg(R9, 0x2000013C) returns 0x00 (0000ms, 32832ms total) +T3170 098:809 JLINK_WriteReg(R10, 0x00000000) returns 0x00 (0000ms, 32832ms total) +T3170 098:809 JLINK_WriteReg(R11, 0x00000000) returns 0x00 (0000ms, 32832ms total) +T3170 098:809 JLINK_WriteReg(R12, 0x00000000) returns 0x00 (0000ms, 32832ms total) +T3170 098:809 JLINK_WriteReg(R13 (SP), 0x20001000) returns 0x00 (0000ms, 32832ms total) +T3170 098:809 JLINK_WriteReg(R14, 0x20000001) returns 0x00 (0000ms, 32832ms total) +T3170 098:809 JLINK_WriteReg(R15 (PC), 0x2000005C) returns 0x00 (0000ms, 32832ms total) +T3170 098:809 JLINK_WriteReg(XPSR, 0x01000000) returns 0x00 (0000ms, 32832ms total) +T3170 098:809 JLINK_WriteReg(MSP, 0x20001000) returns 0x00 (0000ms, 32832ms total) +T3170 098:809 JLINK_WriteReg(PSP, 0x20001000) returns 0x00 (0000ms, 32832ms total) +T3170 098:809 JLINK_WriteReg(CFBP, 0x00000000) returns 0x00 (0000ms, 32832ms total) +T3170 098:809 JLINK_SetBPEx(Addr = 0x20000000, Type = 0xFFFFFFF2) returns 0x00000092 (0000ms, 32832ms total) +T3170 098:809 JLINK_Go() -- CPU_ReadMem(4 bytes @ 0xE0001000) (0006ms, 32838ms total) +T3170 098:816 JLINK_IsHalted() -- CPU_ReadMem(2 bytes @ 0x20000000) returns TRUE (0089ms, 32928ms total) +T3170 098:906 JLINK_ReadReg(R15 (PC)) returns 0x20000000 (0000ms, 32839ms total) +T3170 098:906 JLINK_ClrBPEx(BPHandle = 0x00000092) returns 0x00 (0000ms, 32839ms total) +T3170 098:906 JLINK_ReadReg(R0) returns 0x00000000 (0000ms, 32839ms total) +T3170 098:906 JLINK_WriteMem(0x20000144, 0x0080 Bytes, ...) - Data: 00 BF FF F7 67 F8 A0 6F 10 B1 20 46 A1 6F 88 47 ... -- CPU_WriteMem(128 bytes @ 0x20000144) returns 0x80 (0003ms, 32842ms total) +T3170 098:909 JLINK_WriteReg(R0, 0x00004180) returns 0x00 (0001ms, 32843ms total) +T3170 098:910 JLINK_WriteReg(R1, 0x00000080) returns 0x00 (0000ms, 32843ms total) +T3170 098:910 JLINK_WriteReg(R2, 0x20000144) returns 0x00 (0000ms, 32843ms total) +T3170 098:910 JLINK_WriteReg(R3, 0x00000000) returns 0x00 (0000ms, 32843ms total) +T3170 098:910 JLINK_WriteReg(R4, 0x00000000) returns 0x00 (0000ms, 32843ms total) +T3170 098:910 JLINK_WriteReg(R5, 0x00000000) returns 0x00 (0000ms, 32843ms total) +T3170 098:910 JLINK_WriteReg(R6, 0x00000000) returns 0x00 (0000ms, 32843ms total) +T3170 098:910 JLINK_WriteReg(R7, 0x00000000) returns 0x00 (0000ms, 32843ms total) +T3170 098:910 JLINK_WriteReg(R8, 0x00000000) returns 0x00 (0000ms, 32843ms total) +T3170 098:910 JLINK_WriteReg(R9, 0x2000013C) returns 0x00 (0000ms, 32843ms total) +T3170 098:910 JLINK_WriteReg(R10, 0x00000000) returns 0x00 (0000ms, 32843ms total) +T3170 098:910 JLINK_WriteReg(R11, 0x00000000) returns 0x00 (0000ms, 32843ms total) +T3170 098:910 JLINK_WriteReg(R12, 0x00000000) returns 0x00 (0000ms, 32843ms total) +T3170 098:910 JLINK_WriteReg(R13 (SP), 0x20001000) returns 0x00 (0000ms, 32843ms total) +T3170 098:910 JLINK_WriteReg(R14, 0x20000001) returns 0x00 (0000ms, 32843ms total) +T3170 098:910 JLINK_WriteReg(R15 (PC), 0x2000005C) returns 0x00 (0000ms, 32843ms total) +T3170 098:910 JLINK_WriteReg(XPSR, 0x01000000) returns 0x00 (0000ms, 32843ms total) +T3170 098:910 JLINK_WriteReg(MSP, 0x20001000) returns 0x00 (0000ms, 32843ms total) +T3170 098:910 JLINK_WriteReg(PSP, 0x20001000) returns 0x00 (0000ms, 32843ms total) +T3170 098:910 JLINK_WriteReg(CFBP, 0x00000000) returns 0x00 (0000ms, 32843ms total) +T3170 098:910 JLINK_SetBPEx(Addr = 0x20000000, Type = 0xFFFFFFF2) returns 0x00000093 (0000ms, 32843ms total) +T3170 098:910 JLINK_Go() -- CPU_ReadMem(4 bytes @ 0xE0001000) (0006ms, 32849ms total) +T3170 098:916 JLINK_IsHalted() -- CPU_ReadMem(2 bytes @ 0x20000000) returns TRUE (0090ms, 32939ms total) +T3170 099:007 JLINK_ReadReg(R15 (PC)) returns 0x20000000 (0000ms, 32849ms total) +T3170 099:007 JLINK_ClrBPEx(BPHandle = 0x00000093) returns 0x00 (0000ms, 32849ms total) +T3170 099:007 JLINK_ReadReg(R0) returns 0x00000000 (0000ms, 32849ms total) +T3170 099:007 JLINK_WriteMem(0x20000144, 0x0080 Bytes, ...) - Data: 01 32 03 91 00 90 0C 49 01 EB C4 10 00 23 0B 4A ... -- CPU_WriteMem(128 bytes @ 0x20000144) returns 0x80 (0004ms, 32853ms total) +T3170 099:011 JLINK_WriteReg(R0, 0x00004200) returns 0x00 (0000ms, 32853ms total) +T3170 099:011 JLINK_WriteReg(R1, 0x00000080) returns 0x00 (0000ms, 32853ms total) +T3170 099:011 JLINK_WriteReg(R2, 0x20000144) returns 0x00 (0000ms, 32853ms total) +T3170 099:011 JLINK_WriteReg(R3, 0x00000000) returns 0x00 (0000ms, 32853ms total) +T3170 099:011 JLINK_WriteReg(R4, 0x00000000) returns 0x00 (0000ms, 32853ms total) +T3170 099:011 JLINK_WriteReg(R5, 0x00000000) returns 0x00 (0000ms, 32853ms total) +T3170 099:011 JLINK_WriteReg(R6, 0x00000000) returns 0x00 (0000ms, 32853ms total) +T3170 099:011 JLINK_WriteReg(R7, 0x00000000) returns 0x00 (0000ms, 32853ms total) +T3170 099:011 JLINK_WriteReg(R8, 0x00000000) returns 0x00 (0000ms, 32853ms total) +T3170 099:011 JLINK_WriteReg(R9, 0x2000013C) returns 0x00 (0000ms, 32853ms total) +T3170 099:011 JLINK_WriteReg(R10, 0x00000000) returns 0x00 (0000ms, 32853ms total) +T3170 099:011 JLINK_WriteReg(R11, 0x00000000) returns 0x00 (0000ms, 32853ms total) +T3170 099:011 JLINK_WriteReg(R12, 0x00000000) returns 0x00 (0000ms, 32853ms total) +T3170 099:011 JLINK_WriteReg(R13 (SP), 0x20001000) returns 0x00 (0000ms, 32853ms total) +T3170 099:011 JLINK_WriteReg(R14, 0x20000001) returns 0x00 (0000ms, 32853ms total) +T3170 099:011 JLINK_WriteReg(R15 (PC), 0x2000005C) returns 0x00 (0000ms, 32853ms total) +T3170 099:011 JLINK_WriteReg(XPSR, 0x01000000) returns 0x00 (0000ms, 32853ms total) +T3170 099:011 JLINK_WriteReg(MSP, 0x20001000) returns 0x00 (0000ms, 32853ms total) +T3170 099:011 JLINK_WriteReg(PSP, 0x20001000) returns 0x00 (0000ms, 32853ms total) +T3170 099:011 JLINK_WriteReg(CFBP, 0x00000000) returns 0x00 (0000ms, 32853ms total) +T3170 099:011 JLINK_SetBPEx(Addr = 0x20000000, Type = 0xFFFFFFF2) returns 0x00000094 (0000ms, 32853ms total) +T3170 099:011 JLINK_Go() -- CPU_ReadMem(4 bytes @ 0xE0001000) (0089ms, 32942ms total) +T3170 099:100 JLINK_IsHalted() -- CPU_ReadMem(2 bytes @ 0x20000000) returns TRUE (0007ms, 32949ms total) +T3170 099:107 JLINK_ReadReg(R15 (PC)) returns 0x20000000 (0000ms, 32942ms total) +T3170 099:107 JLINK_ClrBPEx(BPHandle = 0x00000094) returns 0x00 (0000ms, 32942ms total) +T3170 099:107 JLINK_ReadReg(R0) returns 0x00000000 (0000ms, 32942ms total) +T3170 099:107 JLINK_WriteMem(0x20000144, 0x0080 Bytes, ...) - Data: 28 46 00 F0 25 F8 70 BD 70 B5 04 46 94 F8 34 00 ... -- CPU_WriteMem(128 bytes @ 0x20000144) returns 0x80 (0003ms, 32945ms total) +T3170 099:110 JLINK_WriteReg(R0, 0x00004280) returns 0x00 (0000ms, 32945ms total) +T3170 099:110 JLINK_WriteReg(R1, 0x00000080) returns 0x00 (0000ms, 32945ms total) +T3170 099:110 JLINK_WriteReg(R2, 0x20000144) returns 0x00 (0000ms, 32945ms total) +T3170 099:110 JLINK_WriteReg(R3, 0x00000000) returns 0x00 (0000ms, 32945ms total) +T3170 099:110 JLINK_WriteReg(R4, 0x00000000) returns 0x00 (0000ms, 32945ms total) +T3170 099:110 JLINK_WriteReg(R5, 0x00000000) returns 0x00 (0000ms, 32945ms total) +T3170 099:110 JLINK_WriteReg(R6, 0x00000000) returns 0x00 (0000ms, 32945ms total) +T3170 099:110 JLINK_WriteReg(R7, 0x00000000) returns 0x00 (0000ms, 32945ms total) +T3170 099:110 JLINK_WriteReg(R8, 0x00000000) returns 0x00 (0000ms, 32945ms total) +T3170 099:110 JLINK_WriteReg(R9, 0x2000013C) returns 0x00 (0000ms, 32945ms total) +T3170 099:110 JLINK_WriteReg(R10, 0x00000000) returns 0x00 (0000ms, 32945ms total) +T3170 099:110 JLINK_WriteReg(R11, 0x00000000) returns 0x00 (0000ms, 32945ms total) +T3170 099:110 JLINK_WriteReg(R12, 0x00000000) returns 0x00 (0000ms, 32945ms total) +T3170 099:110 JLINK_WriteReg(R13 (SP), 0x20001000) returns 0x00 (0000ms, 32945ms total) +T3170 099:110 JLINK_WriteReg(R14, 0x20000001) returns 0x00 (0000ms, 32945ms total) +T3170 099:110 JLINK_WriteReg(R15 (PC), 0x2000005C) returns 0x00 (0000ms, 32945ms total) +T3170 099:110 JLINK_WriteReg(XPSR, 0x01000000) returns 0x00 (0000ms, 32945ms total) +T3170 099:110 JLINK_WriteReg(MSP, 0x20001000) returns 0x00 (0000ms, 32945ms total) +T3170 099:110 JLINK_WriteReg(PSP, 0x20001000) returns 0x00 (0000ms, 32945ms total) +T3170 099:110 JLINK_WriteReg(CFBP, 0x00000000) returns 0x00 (0000ms, 32945ms total) +T3170 099:110 JLINK_SetBPEx(Addr = 0x20000000, Type = 0xFFFFFFF2) returns 0x00000095 (0000ms, 32945ms total) +T3170 099:110 JLINK_Go() -- CPU_ReadMem(4 bytes @ 0xE0001000) (0015ms, 32960ms total) +T3170 099:125 JLINK_IsHalted() -- CPU_ReadMem(2 bytes @ 0x20000000) returns TRUE (0080ms, 33040ms total) +T3170 099:205 JLINK_ReadReg(R15 (PC)) returns 0x20000000 (0000ms, 32960ms total) +T3170 099:207 JLINK_ClrBPEx(BPHandle = 0x00000095) returns 0x00 (0000ms, 32960ms total) +T3170 099:207 JLINK_ReadReg(R0) returns 0x00000000 (0000ms, 32960ms total) +T3170 099:207 JLINK_WriteMem(0x20000144, 0x0080 Bytes, ...) - Data: 2F FC 20 6B 80 1C 08 B9 00 20 20 63 00 20 38 BD ... -- CPU_WriteMem(128 bytes @ 0x20000144) returns 0x80 (0004ms, 32964ms total) +T3170 099:211 JLINK_WriteReg(R0, 0x00004300) returns 0x00 (0000ms, 32964ms total) +T3170 099:211 JLINK_WriteReg(R1, 0x00000080) returns 0x00 (0000ms, 32964ms total) +T3170 099:211 JLINK_WriteReg(R2, 0x20000144) returns 0x00 (0000ms, 32964ms total) +T3170 099:211 JLINK_WriteReg(R3, 0x00000000) returns 0x00 (0000ms, 32964ms total) +T3170 099:211 JLINK_WriteReg(R4, 0x00000000) returns 0x00 (0000ms, 32964ms total) +T3170 099:211 JLINK_WriteReg(R5, 0x00000000) returns 0x00 (0000ms, 32964ms total) +T3170 099:211 JLINK_WriteReg(R6, 0x00000000) returns 0x00 (0000ms, 32964ms total) +T3170 099:211 JLINK_WriteReg(R7, 0x00000000) returns 0x00 (0000ms, 32964ms total) +T3170 099:211 JLINK_WriteReg(R8, 0x00000000) returns 0x00 (0000ms, 32964ms total) +T3170 099:211 JLINK_WriteReg(R9, 0x2000013C) returns 0x00 (0000ms, 32964ms total) +T3170 099:211 JLINK_WriteReg(R10, 0x00000000) returns 0x00 (0000ms, 32964ms total) +T3170 099:211 JLINK_WriteReg(R11, 0x00000000) returns 0x00 (0000ms, 32964ms total) +T3170 099:211 JLINK_WriteReg(R12, 0x00000000) returns 0x00 (0000ms, 32964ms total) +T3170 099:211 JLINK_WriteReg(R13 (SP), 0x20001000) returns 0x00 (0000ms, 32964ms total) +T3170 099:211 JLINK_WriteReg(R14, 0x20000001) returns 0x00 (0000ms, 32964ms total) +T3170 099:211 JLINK_WriteReg(R15 (PC), 0x2000005C) returns 0x00 (0000ms, 32964ms total) +T3170 099:211 JLINK_WriteReg(XPSR, 0x01000000) returns 0x00 (0000ms, 32964ms total) +T3170 099:211 JLINK_WriteReg(MSP, 0x20001000) returns 0x00 (0000ms, 32964ms total) +T3170 099:211 JLINK_WriteReg(PSP, 0x20001000) returns 0x00 (0000ms, 32964ms total) +T3170 099:211 JLINK_WriteReg(CFBP, 0x00000000) returns 0x00 (0000ms, 32964ms total) +T3170 099:211 JLINK_SetBPEx(Addr = 0x20000000, Type = 0xFFFFFFF2) returns 0x00000096 (0000ms, 32964ms total) +T3170 099:211 JLINK_Go() -- CPU_ReadMem(4 bytes @ 0xE0001000) (0089ms, 33053ms total) +T3170 099:300 JLINK_IsHalted() -- CPU_ReadMem(2 bytes @ 0x20000000) returns TRUE (0007ms, 33060ms total) +T3170 099:307 JLINK_ReadReg(R15 (PC)) returns 0x20000000 (0000ms, 33053ms total) +T3170 099:307 JLINK_ClrBPEx(BPHandle = 0x00000096) returns 0x00 (0000ms, 33053ms total) +T3170 099:307 JLINK_ReadReg(R0) returns 0x00000000 (0000ms, 33053ms total) +T3170 099:307 JLINK_WriteMem(0x20000144, 0x0080 Bytes, ...) - Data: 00 20 E7 E7 70 B5 04 46 25 46 6F F0 01 00 28 63 ... -- CPU_WriteMem(128 bytes @ 0x20000144) returns 0x80 (0003ms, 33056ms total) +T3170 099:310 JLINK_WriteReg(R0, 0x00004380) returns 0x00 (0000ms, 33056ms total) +T3170 099:310 JLINK_WriteReg(R1, 0x00000080) returns 0x00 (0000ms, 33056ms total) +T3170 099:310 JLINK_WriteReg(R2, 0x20000144) returns 0x00 (0000ms, 33056ms total) +T3170 099:310 JLINK_WriteReg(R3, 0x00000000) returns 0x00 (0000ms, 33056ms total) +T3170 099:310 JLINK_WriteReg(R4, 0x00000000) returns 0x00 (0000ms, 33056ms total) +T3170 099:310 JLINK_WriteReg(R5, 0x00000000) returns 0x00 (0000ms, 33056ms total) +T3170 099:310 JLINK_WriteReg(R6, 0x00000000) returns 0x00 (0000ms, 33056ms total) +T3170 099:310 JLINK_WriteReg(R7, 0x00000000) returns 0x00 (0000ms, 33056ms total) +T3170 099:310 JLINK_WriteReg(R8, 0x00000000) returns 0x00 (0000ms, 33056ms total) +T3170 099:310 JLINK_WriteReg(R9, 0x2000013C) returns 0x00 (0000ms, 33056ms total) +T3170 099:310 JLINK_WriteReg(R10, 0x00000000) returns 0x00 (0000ms, 33056ms total) +T3170 099:310 JLINK_WriteReg(R11, 0x00000000) returns 0x00 (0000ms, 33056ms total) +T3170 099:310 JLINK_WriteReg(R12, 0x00000000) returns 0x00 (0000ms, 33056ms total) +T3170 099:310 JLINK_WriteReg(R13 (SP), 0x20001000) returns 0x00 (0000ms, 33056ms total) +T3170 099:310 JLINK_WriteReg(R14, 0x20000001) returns 0x00 (0000ms, 33056ms total) +T3170 099:310 JLINK_WriteReg(R15 (PC), 0x2000005C) returns 0x00 (0000ms, 33056ms total) +T3170 099:310 JLINK_WriteReg(XPSR, 0x01000000) returns 0x00 (0000ms, 33056ms total) +T3170 099:310 JLINK_WriteReg(MSP, 0x20001000) returns 0x00 (0000ms, 33056ms total) +T3170 099:310 JLINK_WriteReg(PSP, 0x20001000) returns 0x00 (0000ms, 33056ms total) +T3170 099:310 JLINK_WriteReg(CFBP, 0x00000000) returns 0x00 (0000ms, 33056ms total) +T3170 099:310 JLINK_SetBPEx(Addr = 0x20000000, Type = 0xFFFFFFF2) returns 0x00000097 (0000ms, 33056ms total) +T3170 099:310 JLINK_Go() -- CPU_ReadMem(4 bytes @ 0xE0001000) (0071ms, 33127ms total) +T3170 099:381 JLINK_IsHalted() -- CPU_ReadMem(2 bytes @ 0x20000000) returns TRUE (0026ms, 33153ms total) +T3170 099:407 JLINK_ReadReg(R15 (PC)) returns 0x20000000 (0000ms, 33127ms total) +T3170 099:407 JLINK_ClrBPEx(BPHandle = 0x00000097) returns 0x00 (0000ms, 33127ms total) +T3170 099:407 JLINK_ReadReg(R0) returns 0x00000000 (0000ms, 33127ms total) +T3170 099:407 JLINK_WriteMem(0x20000144, 0x0080 Bytes, ...) - Data: FF F7 60 FF 04 46 A0 6C 40 1E A0 64 A0 6C 48 B9 ... -- CPU_WriteMem(128 bytes @ 0x20000144) returns 0x80 (0004ms, 33131ms total) +T3170 099:411 JLINK_WriteReg(R0, 0x00004400) returns 0x00 (0000ms, 33131ms total) +T3170 099:411 JLINK_WriteReg(R1, 0x00000080) returns 0x00 (0000ms, 33131ms total) +T3170 099:411 JLINK_WriteReg(R2, 0x20000144) returns 0x00 (0000ms, 33131ms total) +T3170 099:411 JLINK_WriteReg(R3, 0x00000000) returns 0x00 (0000ms, 33131ms total) +T3170 099:411 JLINK_WriteReg(R4, 0x00000000) returns 0x00 (0000ms, 33131ms total) +T3170 099:411 JLINK_WriteReg(R5, 0x00000000) returns 0x00 (0000ms, 33131ms total) +T3170 099:411 JLINK_WriteReg(R6, 0x00000000) returns 0x00 (0000ms, 33131ms total) +T3170 099:411 JLINK_WriteReg(R7, 0x00000000) returns 0x00 (0000ms, 33131ms total) +T3170 099:411 JLINK_WriteReg(R8, 0x00000000) returns 0x00 (0000ms, 33131ms total) +T3170 099:411 JLINK_WriteReg(R9, 0x2000013C) returns 0x00 (0000ms, 33131ms total) +T3170 099:411 JLINK_WriteReg(R10, 0x00000000) returns 0x00 (0000ms, 33131ms total) +T3170 099:411 JLINK_WriteReg(R11, 0x00000000) returns 0x00 (0000ms, 33131ms total) +T3170 099:411 JLINK_WriteReg(R12, 0x00000000) returns 0x00 (0000ms, 33131ms total) +T3170 099:411 JLINK_WriteReg(R13 (SP), 0x20001000) returns 0x00 (0000ms, 33131ms total) +T3170 099:411 JLINK_WriteReg(R14, 0x20000001) returns 0x00 (0000ms, 33131ms total) +T3170 099:411 JLINK_WriteReg(R15 (PC), 0x2000005C) returns 0x00 (0000ms, 33131ms total) +T3170 099:411 JLINK_WriteReg(XPSR, 0x01000000) returns 0x00 (0000ms, 33131ms total) +T3170 099:411 JLINK_WriteReg(MSP, 0x20001000) returns 0x00 (0000ms, 33131ms total) +T3170 099:411 JLINK_WriteReg(PSP, 0x20001000) returns 0x00 (0000ms, 33131ms total) +T3170 099:411 JLINK_WriteReg(CFBP, 0x00000000) returns 0x00 (0000ms, 33131ms total) +T3170 099:411 JLINK_SetBPEx(Addr = 0x20000000, Type = 0xFFFFFFF2) returns 0x00000098 (0000ms, 33131ms total) +T3170 099:411 JLINK_Go() -- CPU_ReadMem(4 bytes @ 0xE0001000) (0089ms, 33220ms total) +T3170 099:500 JLINK_IsHalted() -- CPU_ReadMem(2 bytes @ 0x20000000) returns TRUE (0006ms, 33226ms total) +T3170 099:506 JLINK_ReadReg(R15 (PC)) returns 0x20000000 (0000ms, 33220ms total) +T3170 099:506 JLINK_ClrBPEx(BPHandle = 0x00000098) returns 0x00 (0000ms, 33220ms total) +T3170 099:506 JLINK_ReadReg(R0) returns 0x00000000 (0000ms, 33220ms total) +T3170 099:506 JLINK_WriteMem(0x20000144, 0x0080 Bytes, ...) - Data: 00 F0 60 F8 05 E0 60 7A 20 F0 01 00 60 72 00 E0 ... -- CPU_WriteMem(128 bytes @ 0x20000144) returns 0x80 (0003ms, 33223ms total) +T3170 099:509 JLINK_WriteReg(R0, 0x00004480) returns 0x00 (0000ms, 33223ms total) +T3170 099:509 JLINK_WriteReg(R1, 0x00000080) returns 0x00 (0000ms, 33223ms total) +T3170 099:509 JLINK_WriteReg(R2, 0x20000144) returns 0x00 (0000ms, 33223ms total) +T3170 099:509 JLINK_WriteReg(R3, 0x00000000) returns 0x00 (0000ms, 33223ms total) +T3170 099:509 JLINK_WriteReg(R4, 0x00000000) returns 0x00 (0000ms, 33223ms total) +T3170 099:509 JLINK_WriteReg(R5, 0x00000000) returns 0x00 (0000ms, 33223ms total) +T3170 099:509 JLINK_WriteReg(R6, 0x00000000) returns 0x00 (0000ms, 33223ms total) +T3170 099:509 JLINK_WriteReg(R7, 0x00000000) returns 0x00 (0000ms, 33223ms total) +T3170 099:509 JLINK_WriteReg(R8, 0x00000000) returns 0x00 (0000ms, 33223ms total) +T3170 099:509 JLINK_WriteReg(R9, 0x2000013C) returns 0x00 (0000ms, 33223ms total) +T3170 099:509 JLINK_WriteReg(R10, 0x00000000) returns 0x00 (0000ms, 33223ms total) +T3170 099:509 JLINK_WriteReg(R11, 0x00000000) returns 0x00 (0000ms, 33223ms total) +T3170 099:509 JLINK_WriteReg(R12, 0x00000000) returns 0x00 (0000ms, 33223ms total) +T3170 099:509 JLINK_WriteReg(R13 (SP), 0x20001000) returns 0x00 (0000ms, 33223ms total) +T3170 099:509 JLINK_WriteReg(R14, 0x20000001) returns 0x00 (0000ms, 33223ms total) +T3170 099:509 JLINK_WriteReg(R15 (PC), 0x2000005C) returns 0x00 (0000ms, 33223ms total) +T3170 099:509 JLINK_WriteReg(XPSR, 0x01000000) returns 0x00 (0000ms, 33223ms total) +T3170 099:509 JLINK_WriteReg(MSP, 0x20001000) returns 0x00 (0000ms, 33223ms total) +T3170 099:509 JLINK_WriteReg(PSP, 0x20001000) returns 0x00 (0000ms, 33223ms total) +T3170 099:509 JLINK_WriteReg(CFBP, 0x00000000) returns 0x00 (0000ms, 33223ms total) +T3170 099:509 JLINK_SetBPEx(Addr = 0x20000000, Type = 0xFFFFFFF2) returns 0x00000099 (0000ms, 33223ms total) +T3170 099:509 JLINK_Go() -- CPU_ReadMem(4 bytes @ 0xE0001000) (0006ms, 33229ms total) +T3170 099:515 JLINK_IsHalted() -- CPU_ReadMem(2 bytes @ 0x20000000) returns TRUE (0093ms, 33322ms total) +T3170 099:608 JLINK_ReadReg(R15 (PC)) returns 0x20000000 (0000ms, 33229ms total) +T3170 099:608 JLINK_ClrBPEx(BPHandle = 0x00000099) returns 0x00 (0000ms, 33229ms total) +T3170 099:608 JLINK_ReadReg(R0) returns 0x00000000 (0000ms, 33229ms total) +T3170 099:608 JLINK_WriteMem(0x20000144, 0x0080 Bytes, ...) - Data: 20 46 FC F7 7C FF 28 46 FB F7 32 FF 20 46 FF F7 ... -- CPU_WriteMem(128 bytes @ 0x20000144) returns 0x80 (0004ms, 33233ms total) +T3170 099:612 JLINK_WriteReg(R0, 0x00004500) returns 0x00 (0000ms, 33233ms total) +T3170 099:612 JLINK_WriteReg(R1, 0x00000080) returns 0x00 (0000ms, 33233ms total) +T3170 099:612 JLINK_WriteReg(R2, 0x20000144) returns 0x00 (0000ms, 33233ms total) +T3170 099:612 JLINK_WriteReg(R3, 0x00000000) returns 0x00 (0000ms, 33233ms total) +T3170 099:612 JLINK_WriteReg(R4, 0x00000000) returns 0x00 (0000ms, 33233ms total) +T3170 099:612 JLINK_WriteReg(R5, 0x00000000) returns 0x00 (0000ms, 33233ms total) +T3170 099:612 JLINK_WriteReg(R6, 0x00000000) returns 0x00 (0000ms, 33233ms total) +T3170 099:612 JLINK_WriteReg(R7, 0x00000000) returns 0x00 (0000ms, 33233ms total) +T3170 099:612 JLINK_WriteReg(R8, 0x00000000) returns 0x00 (0000ms, 33233ms total) +T3170 099:612 JLINK_WriteReg(R9, 0x2000013C) returns 0x00 (0000ms, 33233ms total) +T3170 099:612 JLINK_WriteReg(R10, 0x00000000) returns 0x00 (0000ms, 33233ms total) +T3170 099:612 JLINK_WriteReg(R11, 0x00000000) returns 0x00 (0000ms, 33233ms total) +T3170 099:612 JLINK_WriteReg(R12, 0x00000000) returns 0x00 (0000ms, 33233ms total) +T3170 099:612 JLINK_WriteReg(R13 (SP), 0x20001000) returns 0x00 (0000ms, 33233ms total) +T3170 099:612 JLINK_WriteReg(R14, 0x20000001) returns 0x00 (0000ms, 33233ms total) +T3170 099:612 JLINK_WriteReg(R15 (PC), 0x2000005C) returns 0x00 (0000ms, 33233ms total) +T3170 099:612 JLINK_WriteReg(XPSR, 0x01000000) returns 0x00 (0000ms, 33233ms total) +T3170 099:612 JLINK_WriteReg(MSP, 0x20001000) returns 0x00 (0000ms, 33233ms total) +T3170 099:612 JLINK_WriteReg(PSP, 0x20001000) returns 0x00 (0000ms, 33233ms total) +T3170 099:612 JLINK_WriteReg(CFBP, 0x00000000) returns 0x00 (0000ms, 33233ms total) +T3170 099:612 JLINK_SetBPEx(Addr = 0x20000000, Type = 0xFFFFFFF2) returns 0x0000009A (0000ms, 33233ms total) +T3170 099:612 JLINK_Go() -- CPU_ReadMem(4 bytes @ 0xE0001000) (0088ms, 33321ms total) +T3170 099:700 JLINK_IsHalted() -- CPU_ReadMem(2 bytes @ 0x20000000) returns TRUE (0008ms, 33329ms total) +T3170 099:708 JLINK_ReadReg(R15 (PC)) returns 0x20000000 (0000ms, 33321ms total) +T3170 099:708 JLINK_ClrBPEx(BPHandle = 0x0000009A) returns 0x00 (0000ms, 33321ms total) +T3170 099:708 JLINK_ReadReg(R0) returns 0x00000000 (0000ms, 33321ms total) +T3170 099:708 JLINK_WriteMem(0x20000144, 0x0080 Bytes, ...) - Data: 24 20 11 68 14 22 02 EB C4 02 88 1A 82 6A AB 6A ... -- CPU_WriteMem(128 bytes @ 0x20000144) returns 0x80 (0003ms, 33324ms total) +T3170 099:711 JLINK_WriteReg(R0, 0x00004580) returns 0x00 (0000ms, 33324ms total) +T3170 099:711 JLINK_WriteReg(R1, 0x00000080) returns 0x00 (0000ms, 33324ms total) +T3170 099:711 JLINK_WriteReg(R2, 0x20000144) returns 0x00 (0000ms, 33324ms total) +T3170 099:711 JLINK_WriteReg(R3, 0x00000000) returns 0x00 (0000ms, 33324ms total) +T3170 099:711 JLINK_WriteReg(R4, 0x00000000) returns 0x00 (0000ms, 33324ms total) +T3170 099:711 JLINK_WriteReg(R5, 0x00000000) returns 0x00 (0000ms, 33324ms total) +T3170 099:711 JLINK_WriteReg(R6, 0x00000000) returns 0x00 (0000ms, 33324ms total) +T3170 099:711 JLINK_WriteReg(R7, 0x00000000) returns 0x00 (0000ms, 33324ms total) +T3170 099:711 JLINK_WriteReg(R8, 0x00000000) returns 0x00 (0000ms, 33324ms total) +T3170 099:711 JLINK_WriteReg(R9, 0x2000013C) returns 0x00 (0000ms, 33324ms total) +T3170 099:711 JLINK_WriteReg(R10, 0x00000000) returns 0x00 (0000ms, 33324ms total) +T3170 099:711 JLINK_WriteReg(R11, 0x00000000) returns 0x00 (0000ms, 33324ms total) +T3170 099:711 JLINK_WriteReg(R12, 0x00000000) returns 0x00 (0000ms, 33324ms total) +T3170 099:711 JLINK_WriteReg(R13 (SP), 0x20001000) returns 0x00 (0000ms, 33324ms total) +T3170 099:711 JLINK_WriteReg(R14, 0x20000001) returns 0x00 (0000ms, 33324ms total) +T3170 099:711 JLINK_WriteReg(R15 (PC), 0x2000005C) returns 0x00 (0000ms, 33324ms total) +T3170 099:711 JLINK_WriteReg(XPSR, 0x01000000) returns 0x00 (0000ms, 33324ms total) +T3170 099:711 JLINK_WriteReg(MSP, 0x20001000) returns 0x00 (0000ms, 33324ms total) +T3170 099:711 JLINK_WriteReg(PSP, 0x20001000) returns 0x00 (0000ms, 33324ms total) +T3170 099:711 JLINK_WriteReg(CFBP, 0x00000000) returns 0x00 (0000ms, 33324ms total) +T3170 099:711 JLINK_SetBPEx(Addr = 0x20000000, Type = 0xFFFFFFF2) returns 0x0000009B (0000ms, 33324ms total) +T3170 099:711 JLINK_Go() -- CPU_ReadMem(4 bytes @ 0xE0001000) (0089ms, 33413ms total) +T3170 099:800 JLINK_IsHalted() -- CPU_ReadMem(2 bytes @ 0x20000000) returns TRUE (0009ms, 33422ms total) +T3170 099:812 JLINK_ReadReg(R15 (PC)) returns 0x20000000 (0000ms, 33413ms total) +T3170 099:812 JLINK_ClrBPEx(BPHandle = 0x0000009B) returns 0x00 (0000ms, 33413ms total) +T3170 099:812 JLINK_ReadReg(R0) returns 0x00000000 (0000ms, 33413ms total) +T3170 099:812 JLINK_WriteMem(0x20000144, 0x0080 Bytes, ...) - Data: 02 EB C3 01 C4 F1 01 02 5D F8 22 00 FF F7 D7 F8 ... -- CPU_WriteMem(128 bytes @ 0x20000144) returns 0x80 (0004ms, 33417ms total) +T3170 099:816 JLINK_WriteReg(R0, 0x00004600) returns 0x00 (0000ms, 33417ms total) +T3170 099:816 JLINK_WriteReg(R1, 0x00000080) returns 0x00 (0000ms, 33417ms total) +T3170 099:816 JLINK_WriteReg(R2, 0x20000144) returns 0x00 (0000ms, 33417ms total) +T3170 099:816 JLINK_WriteReg(R3, 0x00000000) returns 0x00 (0000ms, 33417ms total) +T3170 099:816 JLINK_WriteReg(R4, 0x00000000) returns 0x00 (0000ms, 33417ms total) +T3170 099:816 JLINK_WriteReg(R5, 0x00000000) returns 0x00 (0000ms, 33417ms total) +T3170 099:816 JLINK_WriteReg(R6, 0x00000000) returns 0x00 (0000ms, 33417ms total) +T3170 099:816 JLINK_WriteReg(R7, 0x00000000) returns 0x00 (0000ms, 33417ms total) +T3170 099:816 JLINK_WriteReg(R8, 0x00000000) returns 0x00 (0000ms, 33417ms total) +T3170 099:816 JLINK_WriteReg(R9, 0x2000013C) returns 0x00 (0000ms, 33417ms total) +T3170 099:816 JLINK_WriteReg(R10, 0x00000000) returns 0x00 (0000ms, 33417ms total) +T3170 099:816 JLINK_WriteReg(R11, 0x00000000) returns 0x00 (0000ms, 33417ms total) +T3170 099:816 JLINK_WriteReg(R12, 0x00000000) returns 0x00 (0000ms, 33417ms total) +T3170 099:816 JLINK_WriteReg(R13 (SP), 0x20001000) returns 0x00 (0000ms, 33417ms total) +T3170 099:816 JLINK_WriteReg(R14, 0x20000001) returns 0x00 (0000ms, 33417ms total) +T3170 099:817 JLINK_WriteReg(R15 (PC), 0x2000005C) returns 0x00 (0000ms, 33418ms total) +T3170 099:817 JLINK_WriteReg(XPSR, 0x01000000) returns 0x00 (0000ms, 33418ms total) +T3170 099:817 JLINK_WriteReg(MSP, 0x20001000) returns 0x00 (0000ms, 33418ms total) +T3170 099:817 JLINK_WriteReg(PSP, 0x20001000) returns 0x00 (0000ms, 33418ms total) +T3170 099:817 JLINK_WriteReg(CFBP, 0x00000000) returns 0x00 (0000ms, 33418ms total) +T3170 099:817 JLINK_SetBPEx(Addr = 0x20000000, Type = 0xFFFFFFF2) returns 0x0000009C (0000ms, 33418ms total) +T3170 099:817 JLINK_Go() -- CPU_ReadMem(4 bytes @ 0xE0001000) (0085ms, 33503ms total) +T3170 099:903 JLINK_IsHalted() -- CPU_ReadMem(2 bytes @ 0x20000000) returns TRUE (0006ms, 33509ms total) +T3170 099:909 JLINK_ReadReg(R15 (PC)) returns 0x20000000 (0000ms, 33503ms total) +T3170 099:909 JLINK_ClrBPEx(BPHandle = 0x0000009C) returns 0x00 (0000ms, 33503ms total) +T3170 099:909 JLINK_ReadReg(R0) returns 0x00000000 (0000ms, 33503ms total) +T3170 099:909 JLINK_WriteMem(0x20000144, 0x0080 Bytes, ...) - Data: 4F F0 FF 36 A6 EB 08 00 0A 90 6F E1 0B 98 00 78 ... -- CPU_WriteMem(128 bytes @ 0x20000144) returns 0x80 (0004ms, 33507ms total) +T3170 099:913 JLINK_WriteReg(R0, 0x00004680) returns 0x00 (0000ms, 33507ms total) +T3170 099:913 JLINK_WriteReg(R1, 0x00000080) returns 0x00 (0000ms, 33507ms total) +T3170 099:913 JLINK_WriteReg(R2, 0x20000144) returns 0x00 (0000ms, 33507ms total) +T3170 099:913 JLINK_WriteReg(R3, 0x00000000) returns 0x00 (0000ms, 33507ms total) +T3170 099:913 JLINK_WriteReg(R4, 0x00000000) returns 0x00 (0000ms, 33507ms total) +T3170 099:913 JLINK_WriteReg(R5, 0x00000000) returns 0x00 (0000ms, 33507ms total) +T3170 099:913 JLINK_WriteReg(R6, 0x00000000) returns 0x00 (0000ms, 33507ms total) +T3170 099:913 JLINK_WriteReg(R7, 0x00000000) returns 0x00 (0000ms, 33507ms total) +T3170 099:913 JLINK_WriteReg(R8, 0x00000000) returns 0x00 (0000ms, 33507ms total) +T3170 099:913 JLINK_WriteReg(R9, 0x2000013C) returns 0x00 (0000ms, 33507ms total) +T3170 099:913 JLINK_WriteReg(R10, 0x00000000) returns 0x00 (0000ms, 33507ms total) +T3170 099:913 JLINK_WriteReg(R11, 0x00000000) returns 0x00 (0000ms, 33507ms total) +T3170 099:913 JLINK_WriteReg(R12, 0x00000000) returns 0x00 (0000ms, 33507ms total) +T3170 099:913 JLINK_WriteReg(R13 (SP), 0x20001000) returns 0x00 (0000ms, 33507ms total) +T3170 099:913 JLINK_WriteReg(R14, 0x20000001) returns 0x00 (0000ms, 33507ms total) +T3170 099:913 JLINK_WriteReg(R15 (PC), 0x2000005C) returns 0x00 (0000ms, 33507ms total) +T3170 099:913 JLINK_WriteReg(XPSR, 0x01000000) returns 0x00 (0000ms, 33507ms total) +T3170 099:913 JLINK_WriteReg(MSP, 0x20001000) returns 0x00 (0000ms, 33507ms total) +T3170 099:913 JLINK_WriteReg(PSP, 0x20001000) returns 0x00 (0000ms, 33507ms total) +T3170 099:913 JLINK_WriteReg(CFBP, 0x00000000) returns 0x00 (0000ms, 33507ms total) +T3170 099:913 JLINK_SetBPEx(Addr = 0x20000000, Type = 0xFFFFFFF2) returns 0x0000009D (0000ms, 33507ms total) +T3170 099:913 JLINK_Go() -- CPU_ReadMem(4 bytes @ 0xE0001000) (0090ms, 33597ms total) +T3170 100:003 JLINK_IsHalted() -- CPU_ReadMem(2 bytes @ 0x20000000) returns TRUE (0011ms, 33608ms total) +T3170 100:014 JLINK_ReadReg(R15 (PC)) returns 0x20000000 (0000ms, 33597ms total) +T3170 100:014 JLINK_ClrBPEx(BPHandle = 0x0000009D) returns 0x00 (0000ms, 33597ms total) +T3170 100:014 JLINK_ReadReg(R0) returns 0x00000000 (0000ms, 33597ms total) +T3170 100:014 JLINK_WriteMem(0x20000144, 0x0080 Bytes, ...) - Data: 30 38 0A 28 04 D2 0B A8 00 F0 14 FA 07 46 0E E0 ... -- CPU_WriteMem(128 bytes @ 0x20000144) returns 0x80 (0002ms, 33599ms total) +T3170 100:016 JLINK_WriteReg(R0, 0x00004700) returns 0x00 (0000ms, 33599ms total) +T3170 100:016 JLINK_WriteReg(R1, 0x00000080) returns 0x00 (0001ms, 33600ms total) +T3170 100:017 JLINK_WriteReg(R2, 0x20000144) returns 0x00 (0000ms, 33600ms total) +T3170 100:017 JLINK_WriteReg(R3, 0x00000000) returns 0x00 (0000ms, 33600ms total) +T3170 100:017 JLINK_WriteReg(R4, 0x00000000) returns 0x00 (0000ms, 33600ms total) +T3170 100:017 JLINK_WriteReg(R5, 0x00000000) returns 0x00 (0000ms, 33600ms total) +T3170 100:017 JLINK_WriteReg(R6, 0x00000000) returns 0x00 (0000ms, 33600ms total) +T3170 100:017 JLINK_WriteReg(R7, 0x00000000) returns 0x00 (0000ms, 33600ms total) +T3170 100:017 JLINK_WriteReg(R8, 0x00000000) returns 0x00 (0000ms, 33600ms total) +T3170 100:017 JLINK_WriteReg(R9, 0x2000013C) returns 0x00 (0000ms, 33600ms total) +T3170 100:017 JLINK_WriteReg(R10, 0x00000000) returns 0x00 (0000ms, 33600ms total) +T3170 100:017 JLINK_WriteReg(R11, 0x00000000) returns 0x00 (0000ms, 33600ms total) +T3170 100:017 JLINK_WriteReg(R12, 0x00000000) returns 0x00 (0000ms, 33600ms total) +T3170 100:017 JLINK_WriteReg(R13 (SP), 0x20001000) returns 0x00 (0000ms, 33600ms total) +T3170 100:017 JLINK_WriteReg(R14, 0x20000001) returns 0x00 (0000ms, 33600ms total) +T3170 100:017 JLINK_WriteReg(R15 (PC), 0x2000005C) returns 0x00 (0000ms, 33600ms total) +T3170 100:017 JLINK_WriteReg(XPSR, 0x01000000) returns 0x00 (0000ms, 33600ms total) +T3170 100:017 JLINK_WriteReg(MSP, 0x20001000) returns 0x00 (0000ms, 33600ms total) +T3170 100:017 JLINK_WriteReg(PSP, 0x20001000) returns 0x00 (0000ms, 33600ms total) +T3170 100:017 JLINK_WriteReg(CFBP, 0x00000000) returns 0x00 (0000ms, 33600ms total) +T3170 100:017 JLINK_SetBPEx(Addr = 0x20000000, Type = 0xFFFFFFF2) returns 0x0000009E (0000ms, 33600ms total) +T3170 100:017 JLINK_Go() -- CPU_ReadMem(4 bytes @ 0xE0001000) (0086ms, 33686ms total) +T3170 100:103 JLINK_IsHalted() -- CPU_ReadMem(2 bytes @ 0x20000000) returns TRUE (0007ms, 33693ms total) +T3170 100:110 JLINK_ReadReg(R15 (PC)) returns 0x20000000 (0000ms, 33686ms total) +T3170 100:110 JLINK_ClrBPEx(BPHandle = 0x0000009E) returns 0x00 (0000ms, 33686ms total) +T3170 100:110 JLINK_ReadReg(R0) returns 0x00000000 (0000ms, 33686ms total) +T3170 100:110 JLINK_WriteMem(0x20000144, 0x0080 Bytes, ...) - Data: 0B 98 00 78 6C 28 05 D1 0B 98 00 78 04 90 0B 98 ... -- CPU_WriteMem(128 bytes @ 0x20000144) returns 0x80 (0003ms, 33689ms total) +T3170 100:113 JLINK_WriteReg(R0, 0x00004780) returns 0x00 (0000ms, 33689ms total) +T3170 100:113 JLINK_WriteReg(R1, 0x00000080) returns 0x00 (0000ms, 33689ms total) +T3170 100:113 JLINK_WriteReg(R2, 0x20000144) returns 0x00 (0000ms, 33689ms total) +T3170 100:113 JLINK_WriteReg(R3, 0x00000000) returns 0x00 (0000ms, 33689ms total) +T3170 100:113 JLINK_WriteReg(R4, 0x00000000) returns 0x00 (0000ms, 33689ms total) +T3170 100:113 JLINK_WriteReg(R5, 0x00000000) returns 0x00 (0000ms, 33689ms total) +T3170 100:113 JLINK_WriteReg(R6, 0x00000000) returns 0x00 (0000ms, 33689ms total) +T3170 100:113 JLINK_WriteReg(R7, 0x00000000) returns 0x00 (0000ms, 33689ms total) +T3170 100:113 JLINK_WriteReg(R8, 0x00000000) returns 0x00 (0000ms, 33689ms total) +T3170 100:113 JLINK_WriteReg(R9, 0x2000013C) returns 0x00 (0000ms, 33689ms total) +T3170 100:113 JLINK_WriteReg(R10, 0x00000000) returns 0x00 (0000ms, 33689ms total) +T3170 100:113 JLINK_WriteReg(R11, 0x00000000) returns 0x00 (0000ms, 33689ms total) +T3170 100:113 JLINK_WriteReg(R12, 0x00000000) returns 0x00 (0000ms, 33689ms total) +T3170 100:113 JLINK_WriteReg(R13 (SP), 0x20001000) returns 0x00 (0000ms, 33689ms total) +T3170 100:113 JLINK_WriteReg(R14, 0x20000001) returns 0x00 (0000ms, 33689ms total) +T3170 100:113 JLINK_WriteReg(R15 (PC), 0x2000005C) returns 0x00 (0000ms, 33689ms total) +T3170 100:113 JLINK_WriteReg(XPSR, 0x01000000) returns 0x00 (0000ms, 33689ms total) +T3170 100:113 JLINK_WriteReg(MSP, 0x20001000) returns 0x00 (0000ms, 33689ms total) +T3170 100:113 JLINK_WriteReg(PSP, 0x20001000) returns 0x00 (0000ms, 33689ms total) +T3170 100:113 JLINK_WriteReg(CFBP, 0x00000000) returns 0x00 (0000ms, 33689ms total) +T3170 100:113 JLINK_SetBPEx(Addr = 0x20000000, Type = 0xFFFFFFF2) returns 0x0000009F (0000ms, 33689ms total) +T3170 100:113 JLINK_Go() -- CPU_ReadMem(4 bytes @ 0xE0001000) (0090ms, 33779ms total) +T3170 100:203 JLINK_IsHalted() -- CPU_ReadMem(2 bytes @ 0x20000000) returns TRUE (0010ms, 33789ms total) +T3170 100:213 JLINK_ReadReg(R15 (PC)) returns 0x20000000 (0000ms, 33779ms total) +T3170 100:213 JLINK_ClrBPEx(BPHandle = 0x0000009F) returns 0x00 (0000ms, 33779ms total) +T3170 100:213 JLINK_ReadReg(R0) returns 0x00000000 (0000ms, 33779ms total) +T3170 100:213 JLINK_WriteMem(0x20000144, 0x0080 Bytes, ...) - Data: 01 D2 20 20 20 70 64 1C 78 1E 07 1E F7 DC AA E0 ... -- CPU_WriteMem(128 bytes @ 0x20000144) returns 0x80 (0004ms, 33783ms total) +T3170 100:217 JLINK_WriteReg(R0, 0x00004800) returns 0x00 (0000ms, 33783ms total) +T3170 100:217 JLINK_WriteReg(R1, 0x00000080) returns 0x00 (0000ms, 33783ms total) +T3170 100:217 JLINK_WriteReg(R2, 0x20000144) returns 0x00 (0000ms, 33783ms total) +T3170 100:217 JLINK_WriteReg(R3, 0x00000000) returns 0x00 (0000ms, 33783ms total) +T3170 100:217 JLINK_WriteReg(R4, 0x00000000) returns 0x00 (0000ms, 33783ms total) +T3170 100:217 JLINK_WriteReg(R5, 0x00000000) returns 0x00 (0000ms, 33783ms total) +T3170 100:217 JLINK_WriteReg(R6, 0x00000000) returns 0x00 (0000ms, 33783ms total) +T3170 100:217 JLINK_WriteReg(R7, 0x00000000) returns 0x00 (0000ms, 33783ms total) +T3170 100:217 JLINK_WriteReg(R8, 0x00000000) returns 0x00 (0000ms, 33783ms total) +T3170 100:217 JLINK_WriteReg(R9, 0x2000013C) returns 0x00 (0000ms, 33783ms total) +T3170 100:217 JLINK_WriteReg(R10, 0x00000000) returns 0x00 (0000ms, 33783ms total) +T3170 100:217 JLINK_WriteReg(R11, 0x00000000) returns 0x00 (0000ms, 33783ms total) +T3170 100:217 JLINK_WriteReg(R12, 0x00000000) returns 0x00 (0000ms, 33783ms total) +T3170 100:217 JLINK_WriteReg(R13 (SP), 0x20001000) returns 0x00 (0000ms, 33783ms total) +T3170 100:217 JLINK_WriteReg(R14, 0x20000001) returns 0x00 (0000ms, 33783ms total) +T3170 100:217 JLINK_WriteReg(R15 (PC), 0x2000005C) returns 0x00 (0000ms, 33783ms total) +T3170 100:217 JLINK_WriteReg(XPSR, 0x01000000) returns 0x00 (0000ms, 33783ms total) +T3170 100:217 JLINK_WriteReg(MSP, 0x20001000) returns 0x00 (0000ms, 33783ms total) +T3170 100:217 JLINK_WriteReg(PSP, 0x20001000) returns 0x00 (0000ms, 33783ms total) +T3170 100:217 JLINK_WriteReg(CFBP, 0x00000000) returns 0x00 (0000ms, 33783ms total) +T3170 100:217 JLINK_SetBPEx(Addr = 0x20000000, Type = 0xFFFFFFF2) returns 0x000000A0 (0000ms, 33783ms total) +T3170 100:217 JLINK_Go() -- CPU_ReadMem(4 bytes @ 0xE0001000) (0089ms, 33872ms total) +T3170 100:306 JLINK_IsHalted() -- CPU_ReadMem(2 bytes @ 0x20000000) returns TRUE (0009ms, 33881ms total) +T3170 100:400 JLINK_ReadReg(R15 (PC)) returns 0x20000000 (0000ms, 33881ms total) +T3170 100:400 JLINK_ClrBPEx(BPHandle = 0x000000A0) returns 0x00 (0000ms, 33881ms total) +T3170 100:400 JLINK_ReadReg(R0) returns 0x00000000 (0000ms, 33881ms total) +T3170 100:400 JLINK_WriteMem(0x20000144, 0x0080 Bytes, ...) - Data: 64 1C 38 46 7F 1E 58 45 F6 DC 6C E0 1C E0 15 E0 ... -- CPU_WriteMem(128 bytes @ 0x20000144) returns 0x80 (0004ms, 33885ms total) +T3170 100:404 JLINK_WriteReg(R0, 0x00004880) returns 0x00 (0000ms, 33885ms total) +T3170 100:404 JLINK_WriteReg(R1, 0x00000080) returns 0x00 (0000ms, 33885ms total) +T3170 100:404 JLINK_WriteReg(R2, 0x20000144) returns 0x00 (0000ms, 33885ms total) +T3170 100:404 JLINK_WriteReg(R3, 0x00000000) returns 0x00 (0000ms, 33885ms total) +T3170 100:404 JLINK_WriteReg(R4, 0x00000000) returns 0x00 (0000ms, 33885ms total) +T3170 100:404 JLINK_WriteReg(R5, 0x00000000) returns 0x00 (0000ms, 33885ms total) +T3170 100:404 JLINK_WriteReg(R6, 0x00000000) returns 0x00 (0000ms, 33885ms total) +T3170 100:404 JLINK_WriteReg(R7, 0x00000000) returns 0x00 (0000ms, 33885ms total) +T3170 100:404 JLINK_WriteReg(R8, 0x00000000) returns 0x00 (0000ms, 33885ms total) +T3170 100:404 JLINK_WriteReg(R9, 0x2000013C) returns 0x00 (0000ms, 33885ms total) +T3170 100:404 JLINK_WriteReg(R10, 0x00000000) returns 0x00 (0000ms, 33885ms total) +T3170 100:404 JLINK_WriteReg(R11, 0x00000000) returns 0x00 (0000ms, 33885ms total) +T3170 100:404 JLINK_WriteReg(R12, 0x00000000) returns 0x00 (0000ms, 33885ms total) +T3170 100:404 JLINK_WriteReg(R13 (SP), 0x20001000) returns 0x00 (0000ms, 33885ms total) +T3170 100:405 JLINK_WriteReg(R14, 0x20000001) returns 0x00 (0000ms, 33886ms total) +T3170 100:405 JLINK_WriteReg(R15 (PC), 0x2000005C) returns 0x00 (0000ms, 33886ms total) +T3170 100:405 JLINK_WriteReg(XPSR, 0x01000000) returns 0x00 (0000ms, 33886ms total) +T3170 100:405 JLINK_WriteReg(MSP, 0x20001000) returns 0x00 (0000ms, 33886ms total) +T3170 100:405 JLINK_WriteReg(PSP, 0x20001000) returns 0x00 (0000ms, 33886ms total) +T3170 100:405 JLINK_WriteReg(CFBP, 0x00000000) returns 0x00 (0000ms, 33886ms total) +T3170 100:405 JLINK_SetBPEx(Addr = 0x20000000, Type = 0xFFFFFFF2) returns 0x000000A1 (0000ms, 33886ms total) +T3170 100:405 JLINK_Go() -- CPU_ReadMem(4 bytes @ 0xE0001000) (0006ms, 33892ms total) +T3170 100:411 JLINK_IsHalted() -- CPU_ReadMem(2 bytes @ 0x20000000) returns TRUE (0089ms, 33981ms total) +T3170 100:500 JLINK_ReadReg(R15 (PC)) returns 0x20000000 (0000ms, 33892ms total) +T3170 100:500 JLINK_ClrBPEx(BPHandle = 0x000000A1) returns 0x00 (0000ms, 33892ms total) +T3170 100:500 JLINK_ReadReg(R0) returns 0x00000000 (0000ms, 33892ms total) +T3170 100:500 JLINK_WriteMem(0x20000144, 0x0080 Bytes, ...) - Data: 02 E0 0B 98 40 1E 0B 90 2D E0 00 BF 04 98 6C 28 ... -- CPU_WriteMem(128 bytes @ 0x20000144) returns 0x80 (0004ms, 33896ms total) +T3170 100:504 JLINK_WriteReg(R0, 0x00004900) returns 0x00 (0000ms, 33896ms total) +T3170 100:504 JLINK_WriteReg(R1, 0x00000080) returns 0x00 (0000ms, 33896ms total) +T3170 100:504 JLINK_WriteReg(R2, 0x20000144) returns 0x00 (0000ms, 33896ms total) +T3170 100:504 JLINK_WriteReg(R3, 0x00000000) returns 0x00 (0000ms, 33896ms total) +T3170 100:504 JLINK_WriteReg(R4, 0x00000000) returns 0x00 (0000ms, 33896ms total) +T3170 100:504 JLINK_WriteReg(R5, 0x00000000) returns 0x00 (0000ms, 33896ms total) +T3170 100:504 JLINK_WriteReg(R6, 0x00000000) returns 0x00 (0000ms, 33896ms total) +T3170 100:504 JLINK_WriteReg(R7, 0x00000000) returns 0x00 (0000ms, 33896ms total) +T3170 100:504 JLINK_WriteReg(R8, 0x00000000) returns 0x00 (0000ms, 33896ms total) +T3170 100:504 JLINK_WriteReg(R9, 0x2000013C) returns 0x00 (0000ms, 33896ms total) +T3170 100:504 JLINK_WriteReg(R10, 0x00000000) returns 0x00 (0000ms, 33896ms total) +T3170 100:504 JLINK_WriteReg(R11, 0x00000000) returns 0x00 (0000ms, 33896ms total) +T3170 100:504 JLINK_WriteReg(R12, 0x00000000) returns 0x00 (0000ms, 33896ms total) +T3170 100:504 JLINK_WriteReg(R13 (SP), 0x20001000) returns 0x00 (0000ms, 33896ms total) +T3170 100:504 JLINK_WriteReg(R14, 0x20000001) returns 0x00 (0000ms, 33896ms total) +T3170 100:504 JLINK_WriteReg(R15 (PC), 0x2000005C) returns 0x00 (0000ms, 33896ms total) +T3170 100:504 JLINK_WriteReg(XPSR, 0x01000000) returns 0x00 (0000ms, 33896ms total) +T3170 100:504 JLINK_WriteReg(MSP, 0x20001000) returns 0x00 (0000ms, 33896ms total) +T3170 100:504 JLINK_WriteReg(PSP, 0x20001000) returns 0x00 (0000ms, 33896ms total) +T3170 100:504 JLINK_WriteReg(CFBP, 0x00000000) returns 0x00 (0000ms, 33896ms total) +T3170 100:504 JLINK_SetBPEx(Addr = 0x20000000, Type = 0xFFFFFFF2) returns 0x000000A2 (0000ms, 33896ms total) +T3170 100:504 JLINK_Go() -- CPU_ReadMem(4 bytes @ 0xE0001000) (0007ms, 33903ms total) +T3170 100:511 JLINK_IsHalted() -- CPU_ReadMem(2 bytes @ 0x20000000) returns TRUE (0048ms, 33951ms total) +T3170 100:559 JLINK_ReadReg(R15 (PC)) returns 0x20000000 (0000ms, 33903ms total) +T3170 100:559 JLINK_ClrBPEx(BPHandle = 0x000000A2) returns 0x00 (0000ms, 33903ms total) +T3170 100:559 JLINK_ReadReg(R0) returns 0x00000000 (0000ms, 33903ms total) +T3170 100:559 JLINK_WriteMem(0x20000144, 0x0080 Bytes, ...) - Data: 20 70 02 E0 00 20 06 F8 01 0C A4 EB 08 00 0D B0 ... -- CPU_WriteMem(128 bytes @ 0x20000144) returns 0x80 (0042ms, 33945ms total) +T3170 100:602 JLINK_WriteReg(R0, 0x00004980) returns 0x00 (0000ms, 33945ms total) +T3170 100:602 JLINK_WriteReg(R1, 0x00000080) returns 0x00 (0000ms, 33945ms total) +T3170 100:602 JLINK_WriteReg(R2, 0x20000144) returns 0x00 (0000ms, 33945ms total) +T3170 100:602 JLINK_WriteReg(R3, 0x00000000) returns 0x00 (0000ms, 33945ms total) +T3170 100:602 JLINK_WriteReg(R4, 0x00000000) returns 0x00 (0000ms, 33945ms total) +T3170 100:602 JLINK_WriteReg(R5, 0x00000000) returns 0x00 (0000ms, 33945ms total) +T3170 100:602 JLINK_WriteReg(R6, 0x00000000) returns 0x00 (0000ms, 33945ms total) +T3170 100:602 JLINK_WriteReg(R7, 0x00000000) returns 0x00 (0000ms, 33945ms total) +T3170 100:602 JLINK_WriteReg(R8, 0x00000000) returns 0x00 (0000ms, 33945ms total) +T3170 100:602 JLINK_WriteReg(R9, 0x2000013C) returns 0x00 (0000ms, 33945ms total) +T3170 100:602 JLINK_WriteReg(R10, 0x00000000) returns 0x00 (0000ms, 33945ms total) +T3170 100:602 JLINK_WriteReg(R11, 0x00000000) returns 0x00 (0000ms, 33945ms total) +T3170 100:602 JLINK_WriteReg(R12, 0x00000000) returns 0x00 (0000ms, 33945ms total) +T3170 100:602 JLINK_WriteReg(R13 (SP), 0x20001000) returns 0x00 (0000ms, 33945ms total) +T3170 100:602 JLINK_WriteReg(R14, 0x20000001) returns 0x00 (0000ms, 33945ms total) +T3170 100:602 JLINK_WriteReg(R15 (PC), 0x2000005C) returns 0x00 (0000ms, 33945ms total) +T3170 100:602 JLINK_WriteReg(XPSR, 0x01000000) returns 0x00 (0000ms, 33945ms total) +T3170 100:602 JLINK_WriteReg(MSP, 0x20001000) returns 0x00 (0000ms, 33945ms total) +T3170 100:602 JLINK_WriteReg(PSP, 0x20001000) returns 0x00 (0000ms, 33945ms total) +T3170 100:602 JLINK_WriteReg(CFBP, 0x00000000) returns 0x00 (0000ms, 33945ms total) +T3170 100:602 JLINK_SetBPEx(Addr = 0x20000000, Type = 0xFFFFFFF2) returns 0x000000A3 (0000ms, 33945ms total) +T3170 100:602 JLINK_Go() -- CPU_ReadMem(4 bytes @ 0xE0001000) (0006ms, 33951ms total) +T3170 100:608 JLINK_IsHalted() -- CPU_ReadMem(2 bytes @ 0x20000000) returns TRUE (0092ms, 34043ms total) +T3170 100:700 JLINK_ReadReg(R15 (PC)) returns 0x20000000 (0000ms, 33951ms total) +T3170 100:700 JLINK_ClrBPEx(BPHandle = 0x000000A3) returns 0x00 (0000ms, 33951ms total) +T3170 100:700 JLINK_ReadReg(R0) returns 0x00000000 (0000ms, 33951ms total) +T3170 100:700 JLINK_WriteMem(0x20000144, 0x0080 Bytes, ...) - Data: 48 65 6C 6C 6F 20 52 54 2D 54 68 72 65 61 64 21 ... -- CPU_WriteMem(128 bytes @ 0x20000144) returns 0x80 (0004ms, 33955ms total) +T3170 100:704 JLINK_WriteReg(R0, 0x00004A00) returns 0x00 (0000ms, 33955ms total) +T3170 100:704 JLINK_WriteReg(R1, 0x00000080) returns 0x00 (0000ms, 33955ms total) +T3170 100:704 JLINK_WriteReg(R2, 0x20000144) returns 0x00 (0000ms, 33955ms total) +T3170 100:704 JLINK_WriteReg(R3, 0x00000000) returns 0x00 (0000ms, 33955ms total) +T3170 100:704 JLINK_WriteReg(R4, 0x00000000) returns 0x00 (0000ms, 33955ms total) +T3170 100:704 JLINK_WriteReg(R5, 0x00000000) returns 0x00 (0000ms, 33955ms total) +T3170 100:704 JLINK_WriteReg(R6, 0x00000000) returns 0x00 (0000ms, 33955ms total) +T3170 100:704 JLINK_WriteReg(R7, 0x00000000) returns 0x00 (0000ms, 33955ms total) +T3170 100:704 JLINK_WriteReg(R8, 0x00000000) returns 0x00 (0000ms, 33955ms total) +T3170 100:704 JLINK_WriteReg(R9, 0x2000013C) returns 0x00 (0000ms, 33955ms total) +T3170 100:704 JLINK_WriteReg(R10, 0x00000000) returns 0x00 (0000ms, 33955ms total) +T3170 100:704 JLINK_WriteReg(R11, 0x00000000) returns 0x00 (0000ms, 33955ms total) +T3170 100:704 JLINK_WriteReg(R12, 0x00000000) returns 0x00 (0000ms, 33955ms total) +T3170 100:704 JLINK_WriteReg(R13 (SP), 0x20001000) returns 0x00 (0000ms, 33955ms total) +T3170 100:704 JLINK_WriteReg(R14, 0x20000001) returns 0x00 (0000ms, 33955ms total) +T3170 100:704 JLINK_WriteReg(R15 (PC), 0x2000005C) returns 0x00 (0000ms, 33955ms total) +T3170 100:704 JLINK_WriteReg(XPSR, 0x01000000) returns 0x00 (0000ms, 33955ms total) +T3170 100:704 JLINK_WriteReg(MSP, 0x20001000) returns 0x00 (0000ms, 33955ms total) +T3170 100:704 JLINK_WriteReg(PSP, 0x20001000) returns 0x00 (0000ms, 33955ms total) +T3170 100:704 JLINK_WriteReg(CFBP, 0x00000000) returns 0x00 (0000ms, 33955ms total) +T3170 100:704 JLINK_SetBPEx(Addr = 0x20000000, Type = 0xFFFFFFF2) returns 0x000000A4 (0000ms, 33955ms total) +T3170 100:704 JLINK_Go() -- CPU_ReadMem(4 bytes @ 0xE0001000) (0007ms, 33962ms total) +T3170 100:711 JLINK_IsHalted() -- CPU_ReadMem(2 bytes @ 0x20000000) returns TRUE (0078ms, 34040ms total) +T3170 100:789 JLINK_ReadReg(R15 (PC)) returns 0x20000000 (0000ms, 33962ms total) +T3170 100:789 JLINK_ClrBPEx(BPHandle = 0x000000A4) returns 0x00 (0000ms, 33962ms total) +T3170 100:789 JLINK_ReadReg(R0) returns 0x00000000 (0000ms, 33962ms total) +T3170 100:789 JLINK_WriteMem(0x20000144, 0x0080 Bytes, ...) - Data: 08 60 08 49 08 60 70 47 00 00 00 20 04 00 00 20 ... -- CPU_WriteMem(128 bytes @ 0x20000144) returns 0x80 (0013ms, 33975ms total) +T3170 100:802 JLINK_WriteReg(R0, 0x00004A80) returns 0x00 (0000ms, 33975ms total) +T3170 100:802 JLINK_WriteReg(R1, 0x00000080) returns 0x00 (0000ms, 33975ms total) +T3170 100:802 JLINK_WriteReg(R2, 0x20000144) returns 0x00 (0000ms, 33975ms total) +T3170 100:802 JLINK_WriteReg(R3, 0x00000000) returns 0x00 (0000ms, 33975ms total) +T3170 100:802 JLINK_WriteReg(R4, 0x00000000) returns 0x00 (0000ms, 33975ms total) +T3170 100:802 JLINK_WriteReg(R5, 0x00000000) returns 0x00 (0000ms, 33975ms total) +T3170 100:802 JLINK_WriteReg(R6, 0x00000000) returns 0x00 (0000ms, 33975ms total) +T3170 100:802 JLINK_WriteReg(R7, 0x00000000) returns 0x00 (0000ms, 33975ms total) +T3170 100:802 JLINK_WriteReg(R8, 0x00000000) returns 0x00 (0000ms, 33975ms total) +T3170 100:802 JLINK_WriteReg(R9, 0x2000013C) returns 0x00 (0000ms, 33975ms total) +T3170 100:802 JLINK_WriteReg(R10, 0x00000000) returns 0x00 (0000ms, 33975ms total) +T3170 100:802 JLINK_WriteReg(R11, 0x00000000) returns 0x00 (0000ms, 33975ms total) +T3170 100:802 JLINK_WriteReg(R12, 0x00000000) returns 0x00 (0000ms, 33975ms total) +T3170 100:802 JLINK_WriteReg(R13 (SP), 0x20001000) returns 0x00 (0000ms, 33975ms total) +T3170 100:802 JLINK_WriteReg(R14, 0x20000001) returns 0x00 (0000ms, 33975ms total) +T3170 100:802 JLINK_WriteReg(R15 (PC), 0x2000005C) returns 0x00 (0000ms, 33975ms total) +T3170 100:802 JLINK_WriteReg(XPSR, 0x01000000) returns 0x00 (0000ms, 33975ms total) +T3170 100:802 JLINK_WriteReg(MSP, 0x20001000) returns 0x00 (0000ms, 33975ms total) +T3170 100:802 JLINK_WriteReg(PSP, 0x20001000) returns 0x00 (0000ms, 33975ms total) +T3170 100:802 JLINK_WriteReg(CFBP, 0x00000000) returns 0x00 (0000ms, 33975ms total) +T3170 100:802 JLINK_SetBPEx(Addr = 0x20000000, Type = 0xFFFFFFF2) returns 0x000000A5 (0000ms, 33975ms total) +T3170 100:802 JLINK_Go() -- CPU_ReadMem(4 bytes @ 0xE0001000) (0007ms, 33982ms total) +T3170 100:809 JLINK_IsHalted() -- CPU_ReadMem(2 bytes @ 0x20000000) returns TRUE (0091ms, 34073ms total) +T3170 100:900 JLINK_ReadReg(R15 (PC)) returns 0x20000000 (0000ms, 33982ms total) +T3170 100:900 JLINK_ClrBPEx(BPHandle = 0x000000A5) returns 0x00 (0000ms, 33982ms total) +T3170 100:900 JLINK_ReadReg(R0) returns 0x00000000 (0000ms, 33982ms total) +T3170 100:901 JLINK_WriteMem(0x20000144, 0x0080 Bytes, ...) - Data: 2D 68 A5 42 F0 D1 70 BD 25 73 00 00 2F 00 00 00 ... -- CPU_WriteMem(128 bytes @ 0x20000144) returns 0x80 (0003ms, 33985ms total) +T3170 100:904 JLINK_WriteReg(R0, 0x00004B00) returns 0x00 (0000ms, 33985ms total) +T3170 100:904 JLINK_WriteReg(R1, 0x00000080) returns 0x00 (0000ms, 33985ms total) +T3170 100:904 JLINK_WriteReg(R2, 0x20000144) returns 0x00 (0000ms, 33985ms total) +T3170 100:904 JLINK_WriteReg(R3, 0x00000000) returns 0x00 (0000ms, 33985ms total) +T3170 100:904 JLINK_WriteReg(R4, 0x00000000) returns 0x00 (0000ms, 33985ms total) +T3170 100:904 JLINK_WriteReg(R5, 0x00000000) returns 0x00 (0000ms, 33985ms total) +T3170 100:904 JLINK_WriteReg(R6, 0x00000000) returns 0x00 (0000ms, 33985ms total) +T3170 100:904 JLINK_WriteReg(R7, 0x00000000) returns 0x00 (0000ms, 33985ms total) +T3170 100:904 JLINK_WriteReg(R8, 0x00000000) returns 0x00 (0000ms, 33985ms total) +T3170 100:904 JLINK_WriteReg(R9, 0x2000013C) returns 0x00 (0000ms, 33985ms total) +T3170 100:904 JLINK_WriteReg(R10, 0x00000000) returns 0x00 (0000ms, 33985ms total) +T3170 100:904 JLINK_WriteReg(R11, 0x00000000) returns 0x00 (0000ms, 33985ms total) +T3170 100:904 JLINK_WriteReg(R12, 0x00000000) returns 0x00 (0000ms, 33985ms total) +T3170 100:905 JLINK_WriteReg(R13 (SP), 0x20001000) returns 0x00 (0000ms, 33985ms total) +T3170 100:905 JLINK_WriteReg(R14, 0x20000001) returns 0x00 (0000ms, 33985ms total) +T3170 100:905 JLINK_WriteReg(R15 (PC), 0x2000005C) returns 0x00 (0000ms, 33985ms total) +T3170 100:905 JLINK_WriteReg(XPSR, 0x01000000) returns 0x00 (0000ms, 33985ms total) +T3170 100:905 JLINK_WriteReg(MSP, 0x20001000) returns 0x00 (0000ms, 33985ms total) +T3170 100:905 JLINK_WriteReg(PSP, 0x20001000) returns 0x00 (0000ms, 33985ms total) +T3170 100:905 JLINK_WriteReg(CFBP, 0x00000000) returns 0x00 (0000ms, 33985ms total) +T3170 100:905 JLINK_SetBPEx(Addr = 0x20000000, Type = 0xFFFFFFF2) returns 0x000000A6 (0000ms, 33985ms total) +T3170 100:905 JLINK_Go() -- CPU_ReadMem(4 bytes @ 0xE0001000) (0006ms, 33991ms total) +T3170 100:911 JLINK_IsHalted() -- CPU_ReadMem(2 bytes @ 0x20000000) returns TRUE (0089ms, 34080ms total) +T3170 101:000 JLINK_ReadReg(R15 (PC)) returns 0x20000000 (0000ms, 33991ms total) +T3170 101:000 JLINK_ClrBPEx(BPHandle = 0x000000A6) returns 0x00 (0000ms, 33991ms total) +T3170 101:000 JLINK_ReadReg(R0) returns 0x00000000 (0000ms, 33991ms total) +T3170 101:000 JLINK_WriteMem(0x20000144, 0x0080 Bytes, ...) - Data: FE F7 EE FD 20 48 01 88 20 A0 FE F7 E9 FD 1E 48 ... -- CPU_WriteMem(128 bytes @ 0x20000144) returns 0x80 (0004ms, 33995ms total) +T3170 101:004 JLINK_WriteReg(R0, 0x00004B80) returns 0x00 (0000ms, 33995ms total) +T3170 101:004 JLINK_WriteReg(R1, 0x00000080) returns 0x00 (0000ms, 33995ms total) +T3170 101:004 JLINK_WriteReg(R2, 0x20000144) returns 0x00 (0000ms, 33995ms total) +T3170 101:004 JLINK_WriteReg(R3, 0x00000000) returns 0x00 (0000ms, 33995ms total) +T3170 101:004 JLINK_WriteReg(R4, 0x00000000) returns 0x00 (0000ms, 33995ms total) +T3170 101:004 JLINK_WriteReg(R5, 0x00000000) returns 0x00 (0000ms, 33995ms total) +T3170 101:004 JLINK_WriteReg(R6, 0x00000000) returns 0x00 (0000ms, 33995ms total) +T3170 101:004 JLINK_WriteReg(R7, 0x00000000) returns 0x00 (0000ms, 33995ms total) +T3170 101:004 JLINK_WriteReg(R8, 0x00000000) returns 0x00 (0000ms, 33995ms total) +T3170 101:004 JLINK_WriteReg(R9, 0x2000013C) returns 0x00 (0000ms, 33995ms total) +T3170 101:004 JLINK_WriteReg(R10, 0x00000000) returns 0x00 (0000ms, 33995ms total) +T3170 101:004 JLINK_WriteReg(R11, 0x00000000) returns 0x00 (0000ms, 33995ms total) +T3170 101:004 JLINK_WriteReg(R12, 0x00000000) returns 0x00 (0000ms, 33995ms total) +T3170 101:004 JLINK_WriteReg(R13 (SP), 0x20001000) returns 0x00 (0000ms, 33995ms total) +T3170 101:004 JLINK_WriteReg(R14, 0x20000001) returns 0x00 (0000ms, 33995ms total) +T3170 101:004 JLINK_WriteReg(R15 (PC), 0x2000005C) returns 0x00 (0000ms, 33995ms total) +T3170 101:004 JLINK_WriteReg(XPSR, 0x01000000) returns 0x00 (0000ms, 33995ms total) +T3170 101:004 JLINK_WriteReg(MSP, 0x20001000) returns 0x00 (0000ms, 33995ms total) +T3170 101:004 JLINK_WriteReg(PSP, 0x20001000) returns 0x00 (0000ms, 33995ms total) +T3170 101:004 JLINK_WriteReg(CFBP, 0x00000000) returns 0x00 (0000ms, 33995ms total) +T3170 101:004 JLINK_SetBPEx(Addr = 0x20000000, Type = 0xFFFFFFF2) returns 0x000000A7 (0000ms, 33995ms total) +T3170 101:004 JLINK_Go() -- CPU_ReadMem(4 bytes @ 0xE0001000) (0007ms, 34002ms total) +T3170 101:011 JLINK_IsHalted() -- CPU_ReadMem(2 bytes @ 0x20000000) returns TRUE (0089ms, 34091ms total) +T3170 101:100 JLINK_ReadReg(R15 (PC)) returns 0x20000000 (0001ms, 34003ms total) +T3170 101:101 JLINK_ClrBPEx(BPHandle = 0x000000A7) returns 0x00 (0000ms, 34003ms total) +T3170 101:101 JLINK_ReadReg(R0) returns 0x00000000 (0000ms, 34003ms total) +T3170 101:101 JLINK_WriteMem(0x20000144, 0x0080 Bytes, ...) - Data: 75 6C 74 3A 0A 00 00 00 2A ED 00 E0 53 43 42 5F ... -- CPU_WriteMem(128 bytes @ 0x20000144) returns 0x80 (0004ms, 34007ms total) +T3170 101:105 JLINK_WriteReg(R0, 0x00004C00) returns 0x00 (0000ms, 34007ms total) +T3170 101:105 JLINK_WriteReg(R1, 0x00000080) returns 0x00 (0000ms, 34007ms total) +T3170 101:105 JLINK_WriteReg(R2, 0x20000144) returns 0x00 (0000ms, 34007ms total) +T3170 101:105 JLINK_WriteReg(R3, 0x00000000) returns 0x00 (0000ms, 34007ms total) +T3170 101:105 JLINK_WriteReg(R4, 0x00000000) returns 0x00 (0000ms, 34007ms total) +T3170 101:105 JLINK_WriteReg(R5, 0x00000000) returns 0x00 (0000ms, 34007ms total) +T3170 101:105 JLINK_WriteReg(R6, 0x00000000) returns 0x00 (0000ms, 34007ms total) +T3170 101:105 JLINK_WriteReg(R7, 0x00000000) returns 0x00 (0000ms, 34007ms total) +T3170 101:105 JLINK_WriteReg(R8, 0x00000000) returns 0x00 (0000ms, 34007ms total) +T3170 101:105 JLINK_WriteReg(R9, 0x2000013C) returns 0x00 (0000ms, 34007ms total) +T3170 101:105 JLINK_WriteReg(R10, 0x00000000) returns 0x00 (0000ms, 34007ms total) +T3170 101:105 JLINK_WriteReg(R11, 0x00000000) returns 0x00 (0000ms, 34007ms total) +T3170 101:105 JLINK_WriteReg(R12, 0x00000000) returns 0x00 (0000ms, 34007ms total) +T3170 101:105 JLINK_WriteReg(R13 (SP), 0x20001000) returns 0x00 (0000ms, 34007ms total) +T3170 101:105 JLINK_WriteReg(R14, 0x20000001) returns 0x00 (0000ms, 34007ms total) +T3170 101:105 JLINK_WriteReg(R15 (PC), 0x2000005C) returns 0x00 (0000ms, 34007ms total) +T3170 101:105 JLINK_WriteReg(XPSR, 0x01000000) returns 0x00 (0000ms, 34007ms total) +T3170 101:105 JLINK_WriteReg(MSP, 0x20001000) returns 0x00 (0000ms, 34007ms total) +T3170 101:105 JLINK_WriteReg(PSP, 0x20001000) returns 0x00 (0000ms, 34007ms total) +T3170 101:105 JLINK_WriteReg(CFBP, 0x00000000) returns 0x00 (0000ms, 34007ms total) +T3170 101:105 JLINK_SetBPEx(Addr = 0x20000000, Type = 0xFFFFFFF2) returns 0x000000A8 (0000ms, 34007ms total) +T3170 101:105 JLINK_Go() -- CPU_ReadMem(4 bytes @ 0xE0001000) (0006ms, 34013ms total) +T3170 101:111 JLINK_IsHalted() -- CPU_ReadMem(2 bytes @ 0x20000000) returns TRUE (0090ms, 34103ms total) +T3170 101:201 JLINK_ReadReg(R15 (PC)) returns 0x20000000 (0000ms, 34013ms total) +T3170 101:201 JLINK_ClrBPEx(BPHandle = 0x000000A8) returns 0x00 (0000ms, 34013ms total) +T3170 101:201 JLINK_ReadReg(R0) returns 0x00000000 (0000ms, 34013ms total) +T3170 101:201 JLINK_WriteMem(0x20000144, 0x0080 Bytes, ...) - Data: 6C 6F 00 00 00 30 01 40 04 30 01 40 08 30 01 40 ... -- CPU_WriteMem(128 bytes @ 0x20000144) returns 0x80 (0003ms, 34016ms total) +T3170 101:204 JLINK_WriteReg(R0, 0x00004C80) returns 0x00 (0000ms, 34016ms total) +T3170 101:204 JLINK_WriteReg(R1, 0x00000080) returns 0x00 (0000ms, 34016ms total) +T3170 101:204 JLINK_WriteReg(R2, 0x20000144) returns 0x00 (0000ms, 34016ms total) +T3170 101:204 JLINK_WriteReg(R3, 0x00000000) returns 0x00 (0000ms, 34016ms total) +T3170 101:204 JLINK_WriteReg(R4, 0x00000000) returns 0x00 (0000ms, 34016ms total) +T3170 101:204 JLINK_WriteReg(R5, 0x00000000) returns 0x00 (0000ms, 34016ms total) +T3170 101:204 JLINK_WriteReg(R6, 0x00000000) returns 0x00 (0000ms, 34016ms total) +T3170 101:204 JLINK_WriteReg(R7, 0x00000000) returns 0x00 (0000ms, 34016ms total) +T3170 101:204 JLINK_WriteReg(R8, 0x00000000) returns 0x00 (0000ms, 34016ms total) +T3170 101:204 JLINK_WriteReg(R9, 0x2000013C) returns 0x00 (0000ms, 34016ms total) +T3170 101:204 JLINK_WriteReg(R10, 0x00000000) returns 0x00 (0000ms, 34016ms total) +T3170 101:204 JLINK_WriteReg(R11, 0x00000000) returns 0x00 (0000ms, 34016ms total) +T3170 101:204 JLINK_WriteReg(R12, 0x00000000) returns 0x00 (0000ms, 34016ms total) +T3170 101:204 JLINK_WriteReg(R13 (SP), 0x20001000) returns 0x00 (0000ms, 34016ms total) +T3170 101:204 JLINK_WriteReg(R14, 0x20000001) returns 0x00 (0000ms, 34016ms total) +T3170 101:204 JLINK_WriteReg(R15 (PC), 0x2000005C) returns 0x00 (0000ms, 34016ms total) +T3170 101:204 JLINK_WriteReg(XPSR, 0x01000000) returns 0x00 (0000ms, 34016ms total) +T3170 101:204 JLINK_WriteReg(MSP, 0x20001000) returns 0x00 (0000ms, 34016ms total) +T3170 101:204 JLINK_WriteReg(PSP, 0x20001000) returns 0x00 (0000ms, 34016ms total) +T3170 101:204 JLINK_WriteReg(CFBP, 0x00000000) returns 0x00 (0000ms, 34016ms total) +T3170 101:204 JLINK_SetBPEx(Addr = 0x20000000, Type = 0xFFFFFFF2) returns 0x000000A9 (0000ms, 34016ms total) +T3170 101:204 JLINK_Go() -- CPU_ReadMem(4 bytes @ 0xE0001000) (0008ms, 34024ms total) +T3170 101:212 JLINK_IsHalted() -- CPU_ReadMem(2 bytes @ 0x20000000) returns TRUE (0089ms, 34113ms total) +T3170 101:301 JLINK_ReadReg(R15 (PC)) returns 0x20000000 (0000ms, 34024ms total) +T3170 101:301 JLINK_ClrBPEx(BPHandle = 0x000000A9) returns 0x00 (0000ms, 34024ms total) +T3170 101:301 JLINK_ReadReg(R0) returns 0x00000000 (0000ms, 34024ms total) +T3170 101:301 JLINK_WriteMem(0x20000144, 0x0080 Bytes, ...) - Data: 7C 30 01 40 32 33 34 35 36 37 38 39 3A 3B 3C 3D ... -- CPU_WriteMem(128 bytes @ 0x20000144) returns 0x80 (0004ms, 34028ms total) +T3170 101:305 JLINK_WriteReg(R0, 0x00004D00) returns 0x00 (0000ms, 34028ms total) +T3170 101:305 JLINK_WriteReg(R1, 0x00000080) returns 0x00 (0000ms, 34028ms total) +T3170 101:305 JLINK_WriteReg(R2, 0x20000144) returns 0x00 (0000ms, 34028ms total) +T3170 101:305 JLINK_WriteReg(R3, 0x00000000) returns 0x00 (0000ms, 34028ms total) +T3170 101:305 JLINK_WriteReg(R4, 0x00000000) returns 0x00 (0000ms, 34028ms total) +T3170 101:305 JLINK_WriteReg(R5, 0x00000000) returns 0x00 (0000ms, 34028ms total) +T3170 101:305 JLINK_WriteReg(R6, 0x00000000) returns 0x00 (0000ms, 34028ms total) +T3170 101:305 JLINK_WriteReg(R7, 0x00000000) returns 0x00 (0000ms, 34028ms total) +T3170 101:305 JLINK_WriteReg(R8, 0x00000000) returns 0x00 (0000ms, 34028ms total) +T3170 101:305 JLINK_WriteReg(R9, 0x2000013C) returns 0x00 (0000ms, 34028ms total) +T3170 101:305 JLINK_WriteReg(R10, 0x00000000) returns 0x00 (0000ms, 34028ms total) +T3170 101:305 JLINK_WriteReg(R11, 0x00000000) returns 0x00 (0000ms, 34028ms total) +T3170 101:305 JLINK_WriteReg(R12, 0x00000000) returns 0x00 (0000ms, 34028ms total) +T3170 101:305 JLINK_WriteReg(R13 (SP), 0x20001000) returns 0x00 (0000ms, 34028ms total) +T3170 101:305 JLINK_WriteReg(R14, 0x20000001) returns 0x00 (0000ms, 34028ms total) +T3170 101:305 JLINK_WriteReg(R15 (PC), 0x2000005C) returns 0x00 (0000ms, 34028ms total) +T3170 101:305 JLINK_WriteReg(XPSR, 0x01000000) returns 0x00 (0000ms, 34028ms total) +T3170 101:305 JLINK_WriteReg(MSP, 0x20001000) returns 0x00 (0000ms, 34028ms total) +T3170 101:305 JLINK_WriteReg(PSP, 0x20001000) returns 0x00 (0000ms, 34028ms total) +T3170 101:305 JLINK_WriteReg(CFBP, 0x00000000) returns 0x00 (0000ms, 34028ms total) +T3170 101:305 JLINK_SetBPEx(Addr = 0x20000000, Type = 0xFFFFFFF2) returns 0x000000AA (0000ms, 34028ms total) +T3170 101:305 JLINK_Go() -- CPU_ReadMem(4 bytes @ 0xE0001000) (0007ms, 34035ms total) +T3170 101:312 JLINK_IsHalted() -- CPU_ReadMem(2 bytes @ 0x20000000) returns TRUE (0092ms, 34127ms total) +T3170 101:405 JLINK_ReadReg(R15 (PC)) returns 0x20000000 (0000ms, 34035ms total) +T3170 101:405 JLINK_ClrBPEx(BPHandle = 0x000000AA) returns 0x00 (0000ms, 34035ms total) +T3170 101:405 JLINK_ReadReg(R0) returns 0x00000000 (0000ms, 34035ms total) +T3170 101:405 JLINK_WriteMem(0x20000144, 0x0080 Bytes, ...) - Data: 02 00 01 00 05 00 01 00 02 00 01 00 03 00 01 00 ... -- CPU_WriteMem(128 bytes @ 0x20000144) returns 0x80 (0004ms, 34039ms total) +T3170 101:409 JLINK_WriteReg(R0, 0x00004D80) returns 0x00 (0000ms, 34039ms total) +T3170 101:409 JLINK_WriteReg(R1, 0x00000080) returns 0x00 (0000ms, 34039ms total) +T3170 101:409 JLINK_WriteReg(R2, 0x20000144) returns 0x00 (0000ms, 34039ms total) +T3170 101:409 JLINK_WriteReg(R3, 0x00000000) returns 0x00 (0000ms, 34039ms total) +T3170 101:409 JLINK_WriteReg(R4, 0x00000000) returns 0x00 (0000ms, 34039ms total) +T3170 101:409 JLINK_WriteReg(R5, 0x00000000) returns 0x00 (0000ms, 34039ms total) +T3170 101:409 JLINK_WriteReg(R6, 0x00000000) returns 0x00 (0000ms, 34039ms total) +T3170 101:409 JLINK_WriteReg(R7, 0x00000000) returns 0x00 (0000ms, 34039ms total) +T3170 101:409 JLINK_WriteReg(R8, 0x00000000) returns 0x00 (0000ms, 34039ms total) +T3170 101:409 JLINK_WriteReg(R9, 0x2000013C) returns 0x00 (0000ms, 34039ms total) +T3170 101:409 JLINK_WriteReg(R10, 0x00000000) returns 0x00 (0000ms, 34039ms total) +T3170 101:409 JLINK_WriteReg(R11, 0x00000000) returns 0x00 (0000ms, 34039ms total) +T3170 101:409 JLINK_WriteReg(R12, 0x00000000) returns 0x00 (0000ms, 34039ms total) +T3170 101:409 JLINK_WriteReg(R13 (SP), 0x20001000) returns 0x00 (0000ms, 34039ms total) +T3170 101:409 JLINK_WriteReg(R14, 0x20000001) returns 0x00 (0000ms, 34039ms total) +T3170 101:409 JLINK_WriteReg(R15 (PC), 0x2000005C) returns 0x00 (0000ms, 34039ms total) +T3170 101:409 JLINK_WriteReg(XPSR, 0x01000000) returns 0x00 (0000ms, 34039ms total) +T3170 101:409 JLINK_WriteReg(MSP, 0x20001000) returns 0x00 (0000ms, 34039ms total) +T3170 101:409 JLINK_WriteReg(PSP, 0x20001000) returns 0x00 (0000ms, 34039ms total) +T3170 101:409 JLINK_WriteReg(CFBP, 0x00000000) returns 0x00 (0000ms, 34039ms total) +T3170 101:409 JLINK_SetBPEx(Addr = 0x20000000, Type = 0xFFFFFFF2) returns 0x000000AB (0000ms, 34039ms total) +T3170 101:409 JLINK_Go() -- CPU_ReadMem(4 bytes @ 0xE0001000) (0006ms, 34045ms total) +T3170 101:415 JLINK_IsHalted() -- CPU_ReadMem(2 bytes @ 0x20000000) returns TRUE (0090ms, 34135ms total) +T3170 101:505 JLINK_ReadReg(R15 (PC)) returns 0x20000000 (0000ms, 34045ms total) +T3170 101:508 JLINK_ClrBPEx(BPHandle = 0x000000AB) returns 0x00 (0000ms, 34045ms total) +T3170 101:508 JLINK_ReadReg(R0) returns 0x00000000 (0000ms, 34045ms total) +T3170 101:509 JLINK_WriteMem(0x20000144, 0x0080 Bytes, ...) - Data: 02 00 01 00 05 00 01 00 02 00 01 00 03 00 01 00 ... -- CPU_WriteMem(128 bytes @ 0x20000144) returns 0x80 (0003ms, 34048ms total) +T3170 101:513 JLINK_WriteReg(R0, 0x00004E00) returns 0x00 (0000ms, 34048ms total) +T3170 101:513 JLINK_WriteReg(R1, 0x00000080) returns 0x00 (0000ms, 34048ms total) +T3170 101:513 JLINK_WriteReg(R2, 0x20000144) returns 0x00 (0000ms, 34048ms total) +T3170 101:513 JLINK_WriteReg(R3, 0x00000000) returns 0x00 (0000ms, 34048ms total) +T3170 101:513 JLINK_WriteReg(R4, 0x00000000) returns 0x00 (0000ms, 34048ms total) +T3170 101:513 JLINK_WriteReg(R5, 0x00000000) returns 0x00 (0000ms, 34048ms total) +T3170 101:513 JLINK_WriteReg(R6, 0x00000000) returns 0x00 (0000ms, 34048ms total) +T3170 101:513 JLINK_WriteReg(R7, 0x00000000) returns 0x00 (0000ms, 34048ms total) +T3170 101:513 JLINK_WriteReg(R8, 0x00000000) returns 0x00 (0000ms, 34048ms total) +T3170 101:513 JLINK_WriteReg(R9, 0x2000013C) returns 0x00 (0000ms, 34048ms total) +T3170 101:513 JLINK_WriteReg(R10, 0x00000000) returns 0x00 (0000ms, 34048ms total) +T3170 101:513 JLINK_WriteReg(R11, 0x00000000) returns 0x00 (0000ms, 34048ms total) +T3170 101:513 JLINK_WriteReg(R12, 0x00000000) returns 0x00 (0000ms, 34048ms total) +T3170 101:513 JLINK_WriteReg(R13 (SP), 0x20001000) returns 0x00 (0000ms, 34048ms total) +T3170 101:513 JLINK_WriteReg(R14, 0x20000001) returns 0x00 (0000ms, 34048ms total) +T3170 101:513 JLINK_WriteReg(R15 (PC), 0x2000005C) returns 0x00 (0000ms, 34048ms total) +T3170 101:513 JLINK_WriteReg(XPSR, 0x01000000) returns 0x00 (0000ms, 34048ms total) +T3170 101:513 JLINK_WriteReg(MSP, 0x20001000) returns 0x00 (0000ms, 34048ms total) +T3170 101:513 JLINK_WriteReg(PSP, 0x20001000) returns 0x00 (0000ms, 34048ms total) +T3170 101:513 JLINK_WriteReg(CFBP, 0x00000000) returns 0x00 (0000ms, 34048ms total) +T3170 101:513 JLINK_SetBPEx(Addr = 0x20000000, Type = 0xFFFFFFF2) returns 0x000000AC (0000ms, 34048ms total) +T3170 101:513 JLINK_Go() -- CPU_ReadMem(4 bytes @ 0xE0001000) (0090ms, 34138ms total) +T3170 101:603 JLINK_IsHalted() -- CPU_ReadMem(2 bytes @ 0x20000000) returns TRUE (0009ms, 34147ms total) +T3170 101:612 JLINK_ReadReg(R15 (PC)) returns 0x20000000 (0000ms, 34138ms total) +T3170 101:612 JLINK_ClrBPEx(BPHandle = 0x000000AC) returns 0x00 (0000ms, 34138ms total) +T3170 101:612 JLINK_ReadReg(R0) returns 0x00000000 (0000ms, 34138ms total) +T3170 101:612 JLINK_WriteMem(0x20000144, 0x0080 Bytes, ...) - Data: 74 5F 74 68 72 65 61 64 00 5F 5F 63 6D 64 5F 6C ... -- CPU_WriteMem(128 bytes @ 0x20000144) returns 0x80 (0004ms, 34142ms total) +T3170 101:616 JLINK_WriteReg(R0, 0x00004E80) returns 0x00 (0000ms, 34142ms total) +T3170 101:616 JLINK_WriteReg(R1, 0x00000080) returns 0x00 (0000ms, 34142ms total) +T3170 101:616 JLINK_WriteReg(R2, 0x20000144) returns 0x00 (0000ms, 34142ms total) +T3170 101:616 JLINK_WriteReg(R3, 0x00000000) returns 0x00 (0000ms, 34142ms total) +T3170 101:616 JLINK_WriteReg(R4, 0x00000000) returns 0x00 (0000ms, 34142ms total) +T3170 101:616 JLINK_WriteReg(R5, 0x00000000) returns 0x00 (0000ms, 34142ms total) +T3170 101:616 JLINK_WriteReg(R6, 0x00000000) returns 0x00 (0000ms, 34142ms total) +T3170 101:616 JLINK_WriteReg(R7, 0x00000000) returns 0x00 (0000ms, 34142ms total) +T3170 101:616 JLINK_WriteReg(R8, 0x00000000) returns 0x00 (0000ms, 34142ms total) +T3170 101:616 JLINK_WriteReg(R9, 0x2000013C) returns 0x00 (0000ms, 34142ms total) +T3170 101:616 JLINK_WriteReg(R10, 0x00000000) returns 0x00 (0000ms, 34142ms total) +T3170 101:616 JLINK_WriteReg(R11, 0x00000000) returns 0x00 (0000ms, 34142ms total) +T3170 101:616 JLINK_WriteReg(R12, 0x00000000) returns 0x00 (0000ms, 34142ms total) +T3170 101:616 JLINK_WriteReg(R13 (SP), 0x20001000) returns 0x00 (0000ms, 34142ms total) +T3170 101:616 JLINK_WriteReg(R14, 0x20000001) returns 0x00 (0000ms, 34142ms total) +T3170 101:616 JLINK_WriteReg(R15 (PC), 0x2000005C) returns 0x00 (0000ms, 34142ms total) +T3170 101:616 JLINK_WriteReg(XPSR, 0x01000000) returns 0x00 (0000ms, 34142ms total) +T3170 101:617 JLINK_WriteReg(MSP, 0x20001000) returns 0x00 (0000ms, 34142ms total) +T3170 101:617 JLINK_WriteReg(PSP, 0x20001000) returns 0x00 (0000ms, 34142ms total) +T3170 101:617 JLINK_WriteReg(CFBP, 0x00000000) returns 0x00 (0000ms, 34142ms total) +T3170 101:617 JLINK_SetBPEx(Addr = 0x20000000, Type = 0xFFFFFFF2) returns 0x000000AD (0000ms, 34142ms total) +T3170 101:617 JLINK_Go() -- CPU_ReadMem(4 bytes @ 0xE0001000) (0085ms, 34227ms total) +T3170 101:702 JLINK_IsHalted() -- CPU_ReadMem(2 bytes @ 0x20000000) returns TRUE (0009ms, 34236ms total) +T3170 101:711 JLINK_ReadReg(R15 (PC)) returns 0x20000000 (0000ms, 34227ms total) +T3170 101:711 JLINK_ClrBPEx(BPHandle = 0x000000AD) returns 0x00 (0000ms, 34227ms total) +T3170 101:712 JLINK_ReadReg(R0) returns 0x00000000 (0000ms, 34228ms total) +T3170 101:712 JLINK_WriteMem(0x20000144, 0x0080 Bytes, ...) - Data: 73 74 5F 6D 61 69 6C 62 6F 78 00 6C 69 73 74 5F ... -- CPU_WriteMem(128 bytes @ 0x20000144) returns 0x80 (0004ms, 34232ms total) +T3170 101:716 JLINK_WriteReg(R0, 0x00004F00) returns 0x00 (0000ms, 34232ms total) +T3170 101:716 JLINK_WriteReg(R1, 0x00000080) returns 0x00 (0000ms, 34232ms total) +T3170 101:716 JLINK_WriteReg(R2, 0x20000144) returns 0x00 (0000ms, 34232ms total) +T3170 101:716 JLINK_WriteReg(R3, 0x00000000) returns 0x00 (0000ms, 34232ms total) +T3170 101:716 JLINK_WriteReg(R4, 0x00000000) returns 0x00 (0000ms, 34232ms total) +T3170 101:716 JLINK_WriteReg(R5, 0x00000000) returns 0x00 (0000ms, 34232ms total) +T3170 101:716 JLINK_WriteReg(R6, 0x00000000) returns 0x00 (0000ms, 34232ms total) +T3170 101:716 JLINK_WriteReg(R7, 0x00000000) returns 0x00 (0000ms, 34232ms total) +T3170 101:716 JLINK_WriteReg(R8, 0x00000000) returns 0x00 (0000ms, 34232ms total) +T3170 101:716 JLINK_WriteReg(R9, 0x2000013C) returns 0x00 (0000ms, 34232ms total) +T3170 101:716 JLINK_WriteReg(R10, 0x00000000) returns 0x00 (0000ms, 34232ms total) +T3170 101:716 JLINK_WriteReg(R11, 0x00000000) returns 0x00 (0000ms, 34232ms total) +T3170 101:716 JLINK_WriteReg(R12, 0x00000000) returns 0x00 (0000ms, 34232ms total) +T3170 101:716 JLINK_WriteReg(R13 (SP), 0x20001000) returns 0x00 (0000ms, 34232ms total) +T3170 101:716 JLINK_WriteReg(R14, 0x20000001) returns 0x00 (0000ms, 34232ms total) +T3170 101:716 JLINK_WriteReg(R15 (PC), 0x2000005C) returns 0x00 (0000ms, 34232ms total) +T3170 101:716 JLINK_WriteReg(XPSR, 0x01000000) returns 0x00 (0000ms, 34232ms total) +T3170 101:716 JLINK_WriteReg(MSP, 0x20001000) returns 0x00 (0000ms, 34232ms total) +T3170 101:716 JLINK_WriteReg(PSP, 0x20001000) returns 0x00 (0000ms, 34232ms total) +T3170 101:716 JLINK_WriteReg(CFBP, 0x00000000) returns 0x00 (0000ms, 34232ms total) +T3170 101:716 JLINK_SetBPEx(Addr = 0x20000000, Type = 0xFFFFFFF2) returns 0x000000AE (0000ms, 34232ms total) +T3170 101:716 JLINK_Go() -- CPU_ReadMem(4 bytes @ 0xE0001000) (0090ms, 34322ms total) +T3170 101:806 JLINK_IsHalted() -- CPU_ReadMem(2 bytes @ 0x20000000) returns TRUE (0009ms, 34331ms total) +T3170 101:815 JLINK_ReadReg(R15 (PC)) returns 0x20000000 (0000ms, 34322ms total) +T3170 101:815 JLINK_ClrBPEx(BPHandle = 0x000000AE) returns 0x00 (0000ms, 34322ms total) +T3170 101:815 JLINK_ReadReg(R0) returns 0x00000000 (0000ms, 34322ms total) +T3170 101:815 JLINK_WriteMem(0x20000144, 0x0080 Bytes, ...) - Data: 73 20 20 20 20 20 20 73 70 20 20 20 20 20 73 74 ... -- CPU_WriteMem(128 bytes @ 0x20000144) returns 0x80 (0028ms, 34350ms total) +T3170 101:843 JLINK_WriteReg(R0, 0x00004F80) returns 0x00 (0000ms, 34350ms total) +T3170 101:843 JLINK_WriteReg(R1, 0x00000080) returns 0x00 (0000ms, 34350ms total) +T3170 101:843 JLINK_WriteReg(R2, 0x20000144) returns 0x00 (0000ms, 34350ms total) +T3170 101:843 JLINK_WriteReg(R3, 0x00000000) returns 0x00 (0000ms, 34350ms total) +T3170 101:843 JLINK_WriteReg(R4, 0x00000000) returns 0x00 (0000ms, 34350ms total) +T3170 101:843 JLINK_WriteReg(R5, 0x00000000) returns 0x00 (0000ms, 34350ms total) +T3170 101:843 JLINK_WriteReg(R6, 0x00000000) returns 0x00 (0000ms, 34350ms total) +T3170 101:843 JLINK_WriteReg(R7, 0x00000000) returns 0x00 (0000ms, 34350ms total) +T3170 101:843 JLINK_WriteReg(R8, 0x00000000) returns 0x00 (0000ms, 34350ms total) +T3170 101:843 JLINK_WriteReg(R9, 0x2000013C) returns 0x00 (0001ms, 34351ms total) +T3170 101:844 JLINK_WriteReg(R10, 0x00000000) returns 0x00 (0000ms, 34351ms total) +T3170 101:844 JLINK_WriteReg(R11, 0x00000000) returns 0x00 (0000ms, 34351ms total) +T3170 101:844 JLINK_WriteReg(R12, 0x00000000) returns 0x00 (0000ms, 34351ms total) +T3170 101:844 JLINK_WriteReg(R13 (SP), 0x20001000) returns 0x00 (0000ms, 34351ms total) +T3170 101:844 JLINK_WriteReg(R14, 0x20000001) returns 0x00 (0000ms, 34351ms total) +T3170 101:844 JLINK_WriteReg(R15 (PC), 0x2000005C) returns 0x00 (0000ms, 34351ms total) +T3170 101:844 JLINK_WriteReg(XPSR, 0x01000000) returns 0x00 (0000ms, 34351ms total) +T3170 101:844 JLINK_WriteReg(MSP, 0x20001000) returns 0x00 (0000ms, 34351ms total) +T3170 101:844 JLINK_WriteReg(PSP, 0x20001000) returns 0x00 (0000ms, 34351ms total) +T3170 101:844 JLINK_WriteReg(CFBP, 0x00000000) returns 0x00 (0000ms, 34351ms total) +T3170 101:844 JLINK_SetBPEx(Addr = 0x20000000, Type = 0xFFFFFFF2) returns 0x000000AF (0000ms, 34351ms total) +T3170 101:844 JLINK_Go() -- CPU_ReadMem(4 bytes @ 0xE0001000) (0061ms, 34412ms total) +T3170 101:905 JLINK_IsHalted() -- CPU_ReadMem(2 bytes @ 0x20000000) returns TRUE (0008ms, 34420ms total) +T3170 101:913 JLINK_ReadReg(R15 (PC)) returns 0x20000000 (0000ms, 34412ms total) +T3170 101:913 JLINK_ClrBPEx(BPHandle = 0x000000AF) returns 0x00 (0000ms, 34412ms total) +T3170 101:913 JLINK_ReadReg(R0) returns 0x00000000 (0000ms, 34412ms total) +T3170 101:913 JLINK_WriteMem(0x20000144, 0x0080 Bytes, ...) - Data: 65 4C 00 00 7D 4E 00 00 15 28 00 00 89 4E 00 00 ... -- CPU_WriteMem(128 bytes @ 0x20000144) returns 0x80 (0004ms, 34416ms total) +T3170 101:917 JLINK_WriteReg(R0, 0x00005000) returns 0x00 (0000ms, 34416ms total) +T3170 101:917 JLINK_WriteReg(R1, 0x00000080) returns 0x00 (0000ms, 34416ms total) +T3170 101:917 JLINK_WriteReg(R2, 0x20000144) returns 0x00 (0000ms, 34416ms total) +T3170 101:917 JLINK_WriteReg(R3, 0x00000000) returns 0x00 (0000ms, 34416ms total) +T3170 101:917 JLINK_WriteReg(R4, 0x00000000) returns 0x00 (0000ms, 34416ms total) +T3170 101:917 JLINK_WriteReg(R5, 0x00000000) returns 0x00 (0000ms, 34416ms total) +T3170 101:917 JLINK_WriteReg(R6, 0x00000000) returns 0x00 (0000ms, 34416ms total) +T3170 101:917 JLINK_WriteReg(R7, 0x00000000) returns 0x00 (0000ms, 34416ms total) +T3170 101:917 JLINK_WriteReg(R8, 0x00000000) returns 0x00 (0000ms, 34416ms total) +T3170 101:917 JLINK_WriteReg(R9, 0x2000013C) returns 0x00 (0000ms, 34416ms total) +T3170 101:917 JLINK_WriteReg(R10, 0x00000000) returns 0x00 (0000ms, 34416ms total) +T3170 101:917 JLINK_WriteReg(R11, 0x00000000) returns 0x00 (0001ms, 34417ms total) +T3170 101:918 JLINK_WriteReg(R12, 0x00000000) returns 0x00 (0000ms, 34417ms total) +T3170 101:918 JLINK_WriteReg(R13 (SP), 0x20001000) returns 0x00 (0000ms, 34417ms total) +T3170 101:918 JLINK_WriteReg(R14, 0x20000001) returns 0x00 (0000ms, 34417ms total) +T3170 101:918 JLINK_WriteReg(R15 (PC), 0x2000005C) returns 0x00 (0000ms, 34417ms total) +T3170 101:918 JLINK_WriteReg(XPSR, 0x01000000) returns 0x00 (0000ms, 34417ms total) +T3170 101:918 JLINK_WriteReg(MSP, 0x20001000) returns 0x00 (0000ms, 34417ms total) +T3170 101:918 JLINK_WriteReg(PSP, 0x20001000) returns 0x00 (0000ms, 34417ms total) +T3170 101:918 JLINK_WriteReg(CFBP, 0x00000000) returns 0x00 (0000ms, 34417ms total) +T3170 101:918 JLINK_SetBPEx(Addr = 0x20000000, Type = 0xFFFFFFF2) returns 0x000000B0 (0000ms, 34417ms total) +T3170 101:918 JLINK_Go() -- CPU_ReadMem(4 bytes @ 0xE0001000) (0087ms, 34504ms total) +T3170 102:005 JLINK_IsHalted() -- CPU_ReadMem(2 bytes @ 0x20000000) returns TRUE (0009ms, 34513ms total) +T3170 102:014 JLINK_ReadReg(R15 (PC)) returns 0x20000000 (0000ms, 34504ms total) +T3170 102:014 JLINK_ClrBPEx(BPHandle = 0x000000B0) returns 0x00 (0000ms, 34504ms total) +T3170 102:014 JLINK_ReadReg(R0) returns 0x00000000 (0000ms, 34504ms total) +T3170 102:014 JLINK_WriteMem(0x20000144, 0x0080 Bytes, ...) - Data: 1D 2E 00 00 59 4F 00 00 91 15 00 00 62 4F 00 00 ... -- CPU_WriteMem(128 bytes @ 0x20000144) returns 0x80 (0002ms, 34506ms total) +T3170 102:017 JLINK_WriteReg(R0, 0x00005080) returns 0x00 (0000ms, 34506ms total) +T3170 102:017 JLINK_WriteReg(R1, 0x00000080) returns 0x00 (0000ms, 34506ms total) +T3170 102:017 JLINK_WriteReg(R2, 0x20000144) returns 0x00 (0000ms, 34506ms total) +T3170 102:017 JLINK_WriteReg(R3, 0x00000000) returns 0x00 (0000ms, 34506ms total) +T3170 102:017 JLINK_WriteReg(R4, 0x00000000) returns 0x00 (0000ms, 34506ms total) +T3170 102:017 JLINK_WriteReg(R5, 0x00000000) returns 0x00 (0000ms, 34506ms total) +T3170 102:017 JLINK_WriteReg(R6, 0x00000000) returns 0x00 (0000ms, 34506ms total) +T3170 102:017 JLINK_WriteReg(R7, 0x00000000) returns 0x00 (0000ms, 34506ms total) +T3170 102:017 JLINK_WriteReg(R8, 0x00000000) returns 0x00 (0000ms, 34506ms total) +T3170 102:017 JLINK_WriteReg(R9, 0x2000013C) returns 0x00 (0000ms, 34506ms total) +T3170 102:017 JLINK_WriteReg(R10, 0x00000000) returns 0x00 (0000ms, 34506ms total) +T3170 102:017 JLINK_WriteReg(R11, 0x00000000) returns 0x00 (0000ms, 34506ms total) +T3170 102:017 JLINK_WriteReg(R12, 0x00000000) returns 0x00 (0000ms, 34506ms total) +T3170 102:017 JLINK_WriteReg(R13 (SP), 0x20001000) returns 0x00 (0000ms, 34506ms total) +T3170 102:017 JLINK_WriteReg(R14, 0x20000001) returns 0x00 (0000ms, 34506ms total) +T3170 102:017 JLINK_WriteReg(R15 (PC), 0x2000005C) returns 0x00 (0000ms, 34506ms total) +T3170 102:017 JLINK_WriteReg(XPSR, 0x01000000) returns 0x00 (0000ms, 34506ms total) +T3170 102:017 JLINK_WriteReg(MSP, 0x20001000) returns 0x00 (0000ms, 34506ms total) +T3170 102:017 JLINK_WriteReg(PSP, 0x20001000) returns 0x00 (0000ms, 34506ms total) +T3170 102:017 JLINK_WriteReg(CFBP, 0x00000000) returns 0x00 (0000ms, 34506ms total) +T3170 102:017 JLINK_SetBPEx(Addr = 0x20000000, Type = 0xFFFFFFF2) returns 0x000000B1 (0000ms, 34506ms total) +T3170 102:017 JLINK_Go() -- CPU_ReadMem(4 bytes @ 0xE0001000) (0088ms, 34594ms total) +T3170 102:105 JLINK_IsHalted() -- CPU_ReadMem(2 bytes @ 0x20000000) returns TRUE (0008ms, 34602ms total) +T3170 102:113 JLINK_ReadReg(R15 (PC)) returns 0x20000000 (0000ms, 34594ms total) +T3170 102:113 JLINK_ClrBPEx(BPHandle = 0x000000B1) returns 0x00 (0000ms, 34594ms total) +T3170 102:113 JLINK_ReadReg(R0) returns 0x00000000 (0001ms, 34595ms total) +T3170 102:114 JLINK_WriteMem(0x20000144, 0x0080 Bytes, ...) - Data: 02 00 00 00 50 00 00 20 50 00 00 20 20 00 00 00 ... -- CPU_WriteMem(128 bytes @ 0x20000144) returns 0x80 (0004ms, 34599ms total) +T3170 102:118 JLINK_WriteReg(R0, 0x00005100) returns 0x00 (0000ms, 34599ms total) +T3170 102:118 JLINK_WriteReg(R1, 0x00000080) returns 0x00 (0000ms, 34599ms total) +T3170 102:118 JLINK_WriteReg(R2, 0x20000144) returns 0x00 (0000ms, 34599ms total) +T3170 102:118 JLINK_WriteReg(R3, 0x00000000) returns 0x00 (0000ms, 34599ms total) +T3170 102:118 JLINK_WriteReg(R4, 0x00000000) returns 0x00 (0000ms, 34599ms total) +T3170 102:118 JLINK_WriteReg(R5, 0x00000000) returns 0x00 (0000ms, 34599ms total) +T3170 102:118 JLINK_WriteReg(R6, 0x00000000) returns 0x00 (0000ms, 34599ms total) +T3170 102:118 JLINK_WriteReg(R7, 0x00000000) returns 0x00 (0000ms, 34599ms total) +T3170 102:118 JLINK_WriteReg(R8, 0x00000000) returns 0x00 (0000ms, 34599ms total) +T3170 102:118 JLINK_WriteReg(R9, 0x2000013C) returns 0x00 (0000ms, 34599ms total) +T3170 102:118 JLINK_WriteReg(R10, 0x00000000) returns 0x00 (0000ms, 34599ms total) +T3170 102:118 JLINK_WriteReg(R11, 0x00000000) returns 0x00 (0000ms, 34599ms total) +T3170 102:118 JLINK_WriteReg(R12, 0x00000000) returns 0x00 (0000ms, 34599ms total) +T3170 102:118 JLINK_WriteReg(R13 (SP), 0x20001000) returns 0x00 (0000ms, 34599ms total) +T3170 102:118 JLINK_WriteReg(R14, 0x20000001) returns 0x00 (0000ms, 34599ms total) +T3170 102:118 JLINK_WriteReg(R15 (PC), 0x2000005C) returns 0x00 (0000ms, 34599ms total) +T3170 102:118 JLINK_WriteReg(XPSR, 0x01000000) returns 0x00 (0000ms, 34599ms total) +T3170 102:118 JLINK_WriteReg(MSP, 0x20001000) returns 0x00 (0000ms, 34599ms total) +T3170 102:118 JLINK_WriteReg(PSP, 0x20001000) returns 0x00 (0000ms, 34599ms total) +T3170 102:118 JLINK_WriteReg(CFBP, 0x00000000) returns 0x00 (0000ms, 34599ms total) +T3170 102:118 JLINK_SetBPEx(Addr = 0x20000000, Type = 0xFFFFFFF2) returns 0x000000B2 (0000ms, 34599ms total) +T3170 102:118 JLINK_Go() -- CPU_ReadMem(4 bytes @ 0xE0001000) (0087ms, 34686ms total) +T3170 102:205 JLINK_IsHalted() -- CPU_ReadMem(2 bytes @ 0x20000000) returns TRUE (0006ms, 34692ms total) +T3170 102:211 JLINK_ReadReg(R15 (PC)) returns 0x20000000 (0000ms, 34686ms total) +T3170 102:211 JLINK_ClrBPEx(BPHandle = 0x000000B2) returns 0x00 (0000ms, 34686ms total) +T3170 102:211 JLINK_ReadReg(R0) returns 0x00000000 (0000ms, 34686ms total) +T3170 102:211 JLINK_WriteMem(0x20000144, 0x0080 Bytes, ...) - Data: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 ... -- CPU_WriteMem(128 bytes @ 0x20000144) returns 0x80 (0003ms, 34689ms total) +T3170 102:214 JLINK_WriteReg(R0, 0x00005180) returns 0x00 (0000ms, 34689ms total) +T3170 102:214 JLINK_WriteReg(R1, 0x0000002C) returns 0x00 (0000ms, 34689ms total) +T3170 102:214 JLINK_WriteReg(R2, 0x20000144) returns 0x00 (0000ms, 34689ms total) +T3170 102:214 JLINK_WriteReg(R3, 0x00000000) returns 0x00 (0000ms, 34689ms total) +T3170 102:214 JLINK_WriteReg(R4, 0x00000000) returns 0x00 (0000ms, 34689ms total) +T3170 102:214 JLINK_WriteReg(R5, 0x00000000) returns 0x00 (0000ms, 34689ms total) +T3170 102:214 JLINK_WriteReg(R6, 0x00000000) returns 0x00 (0000ms, 34689ms total) +T3170 102:214 JLINK_WriteReg(R7, 0x00000000) returns 0x00 (0000ms, 34689ms total) +T3170 102:214 JLINK_WriteReg(R8, 0x00000000) returns 0x00 (0000ms, 34689ms total) +T3170 102:214 JLINK_WriteReg(R9, 0x2000013C) returns 0x00 (0000ms, 34689ms total) +T3170 102:214 JLINK_WriteReg(R10, 0x00000000) returns 0x00 (0000ms, 34689ms total) +T3170 102:214 JLINK_WriteReg(R11, 0x00000000) returns 0x00 (0000ms, 34689ms total) +T3170 102:214 JLINK_WriteReg(R12, 0x00000000) returns 0x00 (0000ms, 34689ms total) +T3170 102:214 JLINK_WriteReg(R13 (SP), 0x20001000) returns 0x00 (0000ms, 34689ms total) +T3170 102:214 JLINK_WriteReg(R14, 0x20000001) returns 0x00 (0000ms, 34689ms total) +T3170 102:214 JLINK_WriteReg(R15 (PC), 0x2000005C) returns 0x00 (0000ms, 34689ms total) +T3170 102:214 JLINK_WriteReg(XPSR, 0x01000000) returns 0x00 (0000ms, 34689ms total) +T3170 102:214 JLINK_WriteReg(MSP, 0x20001000) returns 0x00 (0000ms, 34689ms total) +T3170 102:214 JLINK_WriteReg(PSP, 0x20001000) returns 0x00 (0000ms, 34689ms total) +T3170 102:214 JLINK_WriteReg(CFBP, 0x00000000) returns 0x00 (0000ms, 34689ms total) +T3170 102:214 JLINK_SetBPEx(Addr = 0x20000000, Type = 0xFFFFFFF2) returns 0x000000B3 (0000ms, 34689ms total) +T3170 102:214 JLINK_Go() -- CPU_ReadMem(4 bytes @ 0xE0001000) (0089ms, 34778ms total) +T3170 102:303 JLINK_IsHalted() -- CPU_ReadMem(2 bytes @ 0x20000000) returns TRUE (0011ms, 34789ms total) +T3170 102:314 JLINK_ReadReg(R15 (PC)) returns 0x20000000 (0000ms, 34778ms total) +T3170 102:314 JLINK_ClrBPEx(BPHandle = 0x000000B3) returns 0x00 (0000ms, 34778ms total) +T3170 102:314 JLINK_ReadReg(R0) returns 0x00000000 (0000ms, 34778ms total) +T3170 102:314 JLINK_WriteReg(R0, 0x00000002) returns 0x00 (0000ms, 34778ms total) +T3170 102:314 JLINK_WriteReg(R1, 0x0000002C) returns 0x00 (0000ms, 34778ms total) +T3170 102:314 JLINK_WriteReg(R2, 0x20000144) returns 0x00 (0000ms, 34778ms total) +T3170 102:314 JLINK_WriteReg(R3, 0x00000000) returns 0x00 (0000ms, 34778ms total) +T3170 102:314 JLINK_WriteReg(R4, 0x00000000) returns 0x00 (0000ms, 34778ms total) +T3170 102:314 JLINK_WriteReg(R5, 0x00000000) returns 0x00 (0000ms, 34778ms total) +T3170 102:314 JLINK_WriteReg(R6, 0x00000000) returns 0x00 (0000ms, 34778ms total) +T3170 102:314 JLINK_WriteReg(R7, 0x00000000) returns 0x00 (0000ms, 34778ms total) +T3170 102:314 JLINK_WriteReg(R8, 0x00000000) returns 0x00 (0000ms, 34778ms total) +T3170 102:314 JLINK_WriteReg(R9, 0x2000013C) returns 0x00 (0000ms, 34778ms total) +T3170 102:314 JLINK_WriteReg(R10, 0x00000000) returns 0x00 (0000ms, 34778ms total) +T3170 102:314 JLINK_WriteReg(R11, 0x00000000) returns 0x00 (0000ms, 34778ms total) +T3170 102:314 JLINK_WriteReg(R12, 0x00000000) returns 0x00 (0000ms, 34778ms total) +T3170 102:314 JLINK_WriteReg(R13 (SP), 0x20001000) returns 0x00 (0000ms, 34778ms total) +T3170 102:314 JLINK_WriteReg(R14, 0x20000001) returns 0x00 (0000ms, 34778ms total) +T3170 102:314 JLINK_WriteReg(R15 (PC), 0x20000054) returns 0x00 (0000ms, 34778ms total) +T3170 102:314 JLINK_WriteReg(XPSR, 0x01000000) returns 0x00 (0000ms, 34778ms total) +T3170 102:314 JLINK_WriteReg(MSP, 0x20001000) returns 0x00 (0000ms, 34778ms total) +T3170 102:314 JLINK_WriteReg(PSP, 0x20001000) returns 0x00 (0000ms, 34778ms total) +T3170 102:314 JLINK_WriteReg(CFBP, 0x00000000) returns 0x00 (0000ms, 34778ms total) +T3170 102:314 JLINK_SetBPEx(Addr = 0x20000000, Type = 0xFFFFFFF2) returns 0x000000B4 (0000ms, 34778ms total) +T3170 102:314 JLINK_Go() -- CPU_ReadMem(4 bytes @ 0xE0001000) (0089ms, 34867ms total) +T3170 102:404 JLINK_IsHalted() -- CPU_ReadMem(2 bytes @ 0x20000000) returns TRUE (0009ms, 34877ms total) +T3170 102:413 JLINK_ReadReg(R15 (PC)) returns 0x20000000 (0000ms, 34868ms total) +T3170 102:413 JLINK_ClrBPEx(BPHandle = 0x000000B4) returns 0x00 (0000ms, 34868ms total) +T3170 102:413 JLINK_ReadReg(R0) returns 0x00000000 (0000ms, 34868ms total) +T3170 102:467 JLINK_WriteMem(0x20000000, 0x0144 Bytes, ...) - Data: 00 BE 0A E0 0D 78 2D 06 68 40 08 24 40 00 00 D3 ... -- CPU_WriteMem(324 bytes @ 0x20000000) returns 0x144 (0036ms, 34904ms total) +T3170 102:504 JLINK_WriteReg(R0, 0x00000000) returns 0x00 (0000ms, 34905ms total) +T3170 102:504 JLINK_WriteReg(R1, 0x05F5E100) returns 0x00 (0000ms, 34905ms total) +T3170 102:504 JLINK_WriteReg(R2, 0x00000003) returns 0x00 (0000ms, 34905ms total) +T3170 102:504 JLINK_WriteReg(R3, 0x00000000) returns 0x00 (0000ms, 34905ms total) +T3170 102:504 JLINK_WriteReg(R4, 0x00000000) returns 0x00 (0000ms, 34905ms total) +T3170 102:504 JLINK_WriteReg(R5, 0x00000000) returns 0x00 (0000ms, 34905ms total) +T3170 102:504 JLINK_WriteReg(R6, 0x00000000) returns 0x00 (0000ms, 34905ms total) +T3170 102:504 JLINK_WriteReg(R7, 0x00000000) returns 0x00 (0000ms, 34905ms total) +T3170 102:504 JLINK_WriteReg(R8, 0x00000000) returns 0x00 (0000ms, 34905ms total) +T3170 102:504 JLINK_WriteReg(R9, 0x2000013C) returns 0x00 (0000ms, 34905ms total) +T3170 102:504 JLINK_WriteReg(R10, 0x00000000) returns 0x00 (0000ms, 34905ms total) +T3170 102:504 JLINK_WriteReg(R11, 0x00000000) returns 0x00 (0000ms, 34905ms total) +T3170 102:504 JLINK_WriteReg(R12, 0x00000000) returns 0x00 (0000ms, 34905ms total) +T3170 102:504 JLINK_WriteReg(R13 (SP), 0x20001000) returns 0x00 (0000ms, 34905ms total) +T3170 102:504 JLINK_WriteReg(R14, 0x20000001) returns 0x00 (0000ms, 34905ms total) +T3170 102:504 JLINK_WriteReg(R15 (PC), 0x20000040) returns 0x00 (0000ms, 34905ms total) +T3170 102:504 JLINK_WriteReg(XPSR, 0x01000000) returns 0x00 (0000ms, 34905ms total) +T3170 102:504 JLINK_WriteReg(MSP, 0x20001000) returns 0x00 (0000ms, 34905ms total) +T3170 102:504 JLINK_WriteReg(PSP, 0x20001000) returns 0x00 (0000ms, 34905ms total) +T3170 102:504 JLINK_WriteReg(CFBP, 0x00000000) returns 0x00 (0000ms, 34905ms total) +T3170 102:504 JLINK_SetBPEx(Addr = 0x20000000, Type = 0xFFFFFFF2) -- CPU_ReadMem(2 bytes @ 0x20000000) returns 0x000000B5 (0002ms, 34907ms total) +T3170 102:506 JLINK_Go() -- CPU_WriteMem(2 bytes @ 0x20000000) -- CPU_ReadMem(4 bytes @ 0xE0001000) (0008ms, 34915ms total) +T3170 102:514 JLINK_IsHalted() -- CPU_ReadMem(2 bytes @ 0x20000000) returns TRUE (0086ms, 35001ms total) +T3170 102:600 JLINK_ReadReg(R15 (PC)) returns 0x20000000 (0000ms, 34915ms total) +T3170 102:600 JLINK_ClrBPEx(BPHandle = 0x000000B5) returns 0x00 (0000ms, 34915ms total) +T3170 102:600 JLINK_ReadReg(R0) returns 0x00000000 (0000ms, 34915ms total) +T3170 102:600 JLINK_WriteMem(0x20000144, 0x0080 Bytes, ...) - Data: C0 26 00 20 25 02 00 00 1F 03 00 00 0D 04 00 00 ... -- CPU_WriteMem(128 bytes @ 0x20000144) returns 0x80 (0005ms, 34920ms total) +T3170 102:605 JLINK_WriteReg(R0, 0x00000000) returns 0x00 (0000ms, 34920ms total) +T3170 102:605 JLINK_WriteReg(R1, 0x00000080) returns 0x00 (0000ms, 34920ms total) +T3170 102:605 JLINK_WriteReg(R2, 0x20000144) returns 0x00 (0000ms, 34920ms total) +T3170 102:605 JLINK_WriteReg(R3, 0x00000000) returns 0x00 (0000ms, 34920ms total) +T3170 102:605 JLINK_WriteReg(R4, 0x00000000) returns 0x00 (0000ms, 34920ms total) +T3170 102:605 JLINK_WriteReg(R5, 0x00000000) returns 0x00 (0000ms, 34920ms total) +T3170 102:605 JLINK_WriteReg(R6, 0x00000000) returns 0x00 (0000ms, 34920ms total) +T3170 102:605 JLINK_WriteReg(R7, 0x00000000) returns 0x00 (0000ms, 34920ms total) +T3170 102:605 JLINK_WriteReg(R8, 0x00000000) returns 0x00 (0000ms, 34920ms total) +T3170 102:605 JLINK_WriteReg(R9, 0x2000013C) returns 0x00 (0000ms, 34920ms total) +T3170 102:605 JLINK_WriteReg(R10, 0x00000000) returns 0x00 (0000ms, 34920ms total) +T3170 102:605 JLINK_WriteReg(R11, 0x00000000) returns 0x00 (0000ms, 34920ms total) +T3170 102:605 JLINK_WriteReg(R12, 0x00000000) returns 0x00 (0000ms, 34920ms total) +T3170 102:605 JLINK_WriteReg(R13 (SP), 0x20001000) returns 0x00 (0000ms, 34920ms total) +T3170 102:605 JLINK_WriteReg(R14, 0x20000001) returns 0x00 (0000ms, 34920ms total) +T3170 102:605 JLINK_WriteReg(R15 (PC), 0x20000104) returns 0x00 (0000ms, 34920ms total) +T3170 102:605 JLINK_WriteReg(XPSR, 0x01000000) returns 0x00 (0000ms, 34920ms total) +T3170 102:605 JLINK_WriteReg(MSP, 0x20001000) returns 0x00 (0000ms, 34920ms total) +T3170 102:605 JLINK_WriteReg(PSP, 0x20001000) returns 0x00 (0000ms, 34920ms total) +T3170 102:605 JLINK_WriteReg(CFBP, 0x00000000) returns 0x00 (0000ms, 34920ms total) +T3170 102:605 JLINK_SetBPEx(Addr = 0x20000000, Type = 0xFFFFFFF2) returns 0x000000B6 (0000ms, 34920ms total) +T3170 102:605 JLINK_Go() -- CPU_ReadMem(4 bytes @ 0xE0001000) (0006ms, 34926ms total) +T3170 102:611 JLINK_IsHalted() -- CPU_ReadMem(2 bytes @ 0x20000000) returns TRUE (0089ms, 35015ms total) +T3170 102:700 JLINK_ReadReg(R15 (PC)) returns 0x20000000 (0000ms, 34926ms total) +T3170 102:703 JLINK_ClrBPEx(BPHandle = 0x000000B6) returns 0x00 (0000ms, 34926ms total) +T3170 102:703 JLINK_ReadReg(R0) returns 0x00000080 (0000ms, 34926ms total) +T3170 102:703 JLINK_WriteMem(0x20000144, 0x0080 Bytes, ...) - Data: 31 03 00 00 31 03 00 00 31 03 00 00 31 03 00 00 ... -- CPU_WriteMem(128 bytes @ 0x20000144) returns 0x80 (0004ms, 34930ms total) +T3170 102:707 JLINK_WriteReg(R0, 0x00000080) returns 0x00 (0000ms, 34930ms total) +T3170 102:707 JLINK_WriteReg(R1, 0x00000080) returns 0x00 (0000ms, 34930ms total) +T3170 102:707 JLINK_WriteReg(R2, 0x20000144) returns 0x00 (0000ms, 34930ms total) +T3170 102:707 JLINK_WriteReg(R3, 0x00000000) returns 0x00 (0000ms, 34930ms total) +T3170 102:707 JLINK_WriteReg(R4, 0x00000000) returns 0x00 (0000ms, 34930ms total) +T3170 102:707 JLINK_WriteReg(R5, 0x00000000) returns 0x00 (0000ms, 34930ms total) +T3170 102:707 JLINK_WriteReg(R6, 0x00000000) returns 0x00 (0000ms, 34930ms total) +T3170 102:707 JLINK_WriteReg(R7, 0x00000000) returns 0x00 (0000ms, 34930ms total) +T3170 102:707 JLINK_WriteReg(R8, 0x00000000) returns 0x00 (0000ms, 34930ms total) +T3170 102:707 JLINK_WriteReg(R9, 0x2000013C) returns 0x00 (0000ms, 34930ms total) +T3170 102:707 JLINK_WriteReg(R10, 0x00000000) returns 0x00 (0000ms, 34930ms total) +T3170 102:707 JLINK_WriteReg(R11, 0x00000000) returns 0x00 (0000ms, 34930ms total) +T3170 102:707 JLINK_WriteReg(R12, 0x00000000) returns 0x00 (0000ms, 34930ms total) +T3170 102:708 JLINK_WriteReg(R13 (SP), 0x20001000) returns 0x00 (0000ms, 34930ms total) +T3170 102:708 JLINK_WriteReg(R14, 0x20000001) returns 0x00 (0000ms, 34930ms total) +T3170 102:708 JLINK_WriteReg(R15 (PC), 0x20000104) returns 0x00 (0000ms, 34930ms total) +T3170 102:708 JLINK_WriteReg(XPSR, 0x01000000) returns 0x00 (0000ms, 34930ms total) +T3170 102:708 JLINK_WriteReg(MSP, 0x20001000) returns 0x00 (0000ms, 34930ms total) +T3170 102:708 JLINK_WriteReg(PSP, 0x20001000) returns 0x00 (0000ms, 34930ms total) +T3170 102:708 JLINK_WriteReg(CFBP, 0x00000000) returns 0x00 (0000ms, 34930ms total) +T3170 102:708 JLINK_SetBPEx(Addr = 0x20000000, Type = 0xFFFFFFF2) returns 0x000000B7 (0000ms, 34930ms total) +T3170 102:708 JLINK_Go() -- CPU_ReadMem(4 bytes @ 0xE0001000) (0008ms, 34938ms total) +T3170 102:716 JLINK_IsHalted() -- CPU_ReadMem(2 bytes @ 0x20000000) returns TRUE (0089ms, 35027ms total) +T3170 102:806 JLINK_ReadReg(R15 (PC)) returns 0x20000000 (0000ms, 34938ms total) +T3170 102:809 JLINK_ClrBPEx(BPHandle = 0x000000B7) returns 0x00 (0000ms, 34938ms total) +T3170 102:809 JLINK_ReadReg(R0) returns 0x00000100 (0000ms, 34938ms total) +T3170 102:809 JLINK_WriteMem(0x20000144, 0x0080 Bytes, ...) - Data: 31 03 00 00 31 03 00 00 31 03 00 00 31 03 00 00 ... -- CPU_WriteMem(128 bytes @ 0x20000144) returns 0x80 (0004ms, 34942ms total) +T3170 102:813 JLINK_WriteReg(R0, 0x00000100) returns 0x00 (0000ms, 34942ms total) +T3170 102:813 JLINK_WriteReg(R1, 0x00000080) returns 0x00 (0000ms, 34942ms total) +T3170 102:813 JLINK_WriteReg(R2, 0x20000144) returns 0x00 (0000ms, 34942ms total) +T3170 102:813 JLINK_WriteReg(R3, 0x00000000) returns 0x00 (0000ms, 34942ms total) +T3170 102:813 JLINK_WriteReg(R4, 0x00000000) returns 0x00 (0000ms, 34942ms total) +T3170 102:813 JLINK_WriteReg(R5, 0x00000000) returns 0x00 (0000ms, 34942ms total) +T3170 102:813 JLINK_WriteReg(R6, 0x00000000) returns 0x00 (0000ms, 34942ms total) +T3170 102:813 JLINK_WriteReg(R7, 0x00000000) returns 0x00 (0000ms, 34942ms total) +T3170 102:813 JLINK_WriteReg(R8, 0x00000000) returns 0x00 (0000ms, 34942ms total) +T3170 102:813 JLINK_WriteReg(R9, 0x2000013C) returns 0x00 (0000ms, 34942ms total) +T3170 102:813 JLINK_WriteReg(R10, 0x00000000) returns 0x00 (0000ms, 34942ms total) +T3170 102:813 JLINK_WriteReg(R11, 0x00000000) returns 0x00 (0000ms, 34942ms total) +T3170 102:813 JLINK_WriteReg(R12, 0x00000000) returns 0x00 (0000ms, 34942ms total) +T3170 102:813 JLINK_WriteReg(R13 (SP), 0x20001000) returns 0x00 (0000ms, 34942ms total) +T3170 102:813 JLINK_WriteReg(R14, 0x20000001) returns 0x00 (0000ms, 34942ms total) +T3170 102:813 JLINK_WriteReg(R15 (PC), 0x20000104) returns 0x00 (0000ms, 34942ms total) +T3170 102:813 JLINK_WriteReg(XPSR, 0x01000000) returns 0x00 (0000ms, 34942ms total) +T3170 102:813 JLINK_WriteReg(MSP, 0x20001000) returns 0x00 (0000ms, 34942ms total) +T3170 102:813 JLINK_WriteReg(PSP, 0x20001000) returns 0x00 (0000ms, 34942ms total) +T3170 102:813 JLINK_WriteReg(CFBP, 0x00000000) returns 0x00 (0000ms, 34942ms total) +T3170 102:813 JLINK_SetBPEx(Addr = 0x20000000, Type = 0xFFFFFFF2) returns 0x000000B8 (0000ms, 34942ms total) +T3170 102:813 JLINK_Go() -- CPU_ReadMem(4 bytes @ 0xE0001000) (0090ms, 35032ms total) +T3170 102:903 JLINK_IsHalted() -- CPU_ReadMem(2 bytes @ 0x20000000) returns TRUE (0008ms, 35040ms total) +T3170 102:911 JLINK_ReadReg(R15 (PC)) returns 0x20000000 (0000ms, 35032ms total) +T3170 102:911 JLINK_ClrBPEx(BPHandle = 0x000000B8) returns 0x00 (0000ms, 35032ms total) +T3170 102:911 JLINK_ReadReg(R0) returns 0x00000180 (0000ms, 35032ms total) +T3170 102:911 JLINK_WriteMem(0x20000144, 0x0080 Bytes, ...) - Data: 31 03 00 00 31 03 00 00 00 F0 02 F8 00 F0 3A F8 ... -- CPU_WriteMem(128 bytes @ 0x20000144) returns 0x80 (0004ms, 35036ms total) +T3170 102:915 JLINK_WriteReg(R0, 0x00000180) returns 0x00 (0000ms, 35036ms total) +T3170 102:915 JLINK_WriteReg(R1, 0x00000080) returns 0x00 (0000ms, 35036ms total) +T3170 102:915 JLINK_WriteReg(R2, 0x20000144) returns 0x00 (0000ms, 35036ms total) +T3170 102:915 JLINK_WriteReg(R3, 0x00000000) returns 0x00 (0000ms, 35036ms total) +T3170 102:915 JLINK_WriteReg(R4, 0x00000000) returns 0x00 (0000ms, 35036ms total) +T3170 102:915 JLINK_WriteReg(R5, 0x00000000) returns 0x00 (0000ms, 35036ms total) +T3170 102:915 JLINK_WriteReg(R6, 0x00000000) returns 0x00 (0000ms, 35036ms total) +T3170 102:915 JLINK_WriteReg(R7, 0x00000000) returns 0x00 (0000ms, 35036ms total) +T3170 102:915 JLINK_WriteReg(R8, 0x00000000) returns 0x00 (0000ms, 35036ms total) +T3170 102:915 JLINK_WriteReg(R9, 0x2000013C) returns 0x00 (0000ms, 35036ms total) +T3170 102:915 JLINK_WriteReg(R10, 0x00000000) returns 0x00 (0000ms, 35036ms total) +T3170 102:915 JLINK_WriteReg(R11, 0x00000000) returns 0x00 (0000ms, 35036ms total) +T3170 102:915 JLINK_WriteReg(R12, 0x00000000) returns 0x00 (0000ms, 35036ms total) +T3170 102:915 JLINK_WriteReg(R13 (SP), 0x20001000) returns 0x00 (0000ms, 35036ms total) +T3170 102:915 JLINK_WriteReg(R14, 0x20000001) returns 0x00 (0000ms, 35036ms total) +T3170 102:915 JLINK_WriteReg(R15 (PC), 0x20000104) returns 0x00 (0000ms, 35036ms total) +T3170 102:915 JLINK_WriteReg(XPSR, 0x01000000) returns 0x00 (0000ms, 35036ms total) +T3170 102:915 JLINK_WriteReg(MSP, 0x20001000) returns 0x00 (0000ms, 35036ms total) +T3170 102:915 JLINK_WriteReg(PSP, 0x20001000) returns 0x00 (0000ms, 35036ms total) +T3170 102:915 JLINK_WriteReg(CFBP, 0x00000000) returns 0x00 (0000ms, 35036ms total) +T3170 102:915 JLINK_SetBPEx(Addr = 0x20000000, Type = 0xFFFFFFF2) returns 0x000000B9 (0000ms, 35036ms total) +T3170 102:915 JLINK_Go() -- CPU_ReadMem(4 bytes @ 0xE0001000) (0089ms, 35125ms total) +T3170 103:004 JLINK_IsHalted() -- CPU_ReadMem(2 bytes @ 0x20000000) returns TRUE (0007ms, 35132ms total) +T3170 103:011 JLINK_ReadReg(R15 (PC)) returns 0x20000000 (0000ms, 35125ms total) +T3170 103:011 JLINK_ClrBPEx(BPHandle = 0x000000B9) returns 0x00 (0000ms, 35125ms total) +T3170 103:011 JLINK_ReadReg(R0) returns 0x00000200 (0000ms, 35125ms total) +T3170 103:011 JLINK_WriteMem(0x20000144, 0x0080 Bytes, ...) - Data: 10 B5 10 BD 00 F0 DC FA 11 46 FF F7 F7 FF 00 F0 ... -- CPU_WriteMem(128 bytes @ 0x20000144) returns 0x80 (0003ms, 35128ms total) +T3170 103:014 JLINK_WriteReg(R0, 0x00000200) returns 0x00 (0000ms, 35128ms total) +T3170 103:014 JLINK_WriteReg(R1, 0x00000080) returns 0x00 (0000ms, 35128ms total) +T3170 103:014 JLINK_WriteReg(R2, 0x20000144) returns 0x00 (0000ms, 35128ms total) +T3170 103:014 JLINK_WriteReg(R3, 0x00000000) returns 0x00 (0000ms, 35128ms total) +T3170 103:014 JLINK_WriteReg(R4, 0x00000000) returns 0x00 (0000ms, 35128ms total) +T3170 103:014 JLINK_WriteReg(R5, 0x00000000) returns 0x00 (0000ms, 35128ms total) +T3170 103:014 JLINK_WriteReg(R6, 0x00000000) returns 0x00 (0000ms, 35128ms total) +T3170 103:014 JLINK_WriteReg(R7, 0x00000000) returns 0x00 (0000ms, 35128ms total) +T3170 103:014 JLINK_WriteReg(R8, 0x00000000) returns 0x00 (0000ms, 35128ms total) +T3170 103:014 JLINK_WriteReg(R9, 0x2000013C) returns 0x00 (0000ms, 35128ms total) +T3170 103:014 JLINK_WriteReg(R10, 0x00000000) returns 0x00 (0000ms, 35128ms total) +T3170 103:014 JLINK_WriteReg(R11, 0x00000000) returns 0x00 (0000ms, 35128ms total) +T3170 103:014 JLINK_WriteReg(R12, 0x00000000) returns 0x00 (0000ms, 35128ms total) +T3170 103:014 JLINK_WriteReg(R13 (SP), 0x20001000) returns 0x00 (0000ms, 35128ms total) +T3170 103:014 JLINK_WriteReg(R14, 0x20000001) returns 0x00 (0000ms, 35128ms total) +T3170 103:014 JLINK_WriteReg(R15 (PC), 0x20000104) returns 0x00 (0000ms, 35128ms total) +T3170 103:014 JLINK_WriteReg(XPSR, 0x01000000) returns 0x00 (0000ms, 35128ms total) +T3170 103:014 JLINK_WriteReg(MSP, 0x20001000) returns 0x00 (0000ms, 35128ms total) +T3170 103:014 JLINK_WriteReg(PSP, 0x20001000) returns 0x00 (0000ms, 35128ms total) +T3170 103:014 JLINK_WriteReg(CFBP, 0x00000000) returns 0x00 (0000ms, 35128ms total) +T3170 103:014 JLINK_SetBPEx(Addr = 0x20000000, Type = 0xFFFFFFF2) returns 0x000000BA (0001ms, 35129ms total) +T3170 103:015 JLINK_Go() -- CPU_ReadMem(4 bytes @ 0xE0001000) (0090ms, 35219ms total) +T3170 103:105 JLINK_IsHalted() -- CPU_ReadMem(2 bytes @ 0x20000000) returns TRUE (0010ms, 35229ms total) +T3170 103:115 JLINK_ReadReg(R15 (PC)) returns 0x20000000 (0000ms, 35219ms total) +T3170 103:115 JLINK_ClrBPEx(BPHandle = 0x000000BA) returns 0x00 (0000ms, 35219ms total) +T3170 103:115 JLINK_ReadReg(R0) returns 0x00000280 (0000ms, 35219ms total) +T3170 103:115 JLINK_WriteMem(0x20000144, 0x0080 Bytes, ...) - Data: 04 D0 32 48 32 49 07 4A 00 F0 0E F8 31 48 00 47 ... -- CPU_WriteMem(128 bytes @ 0x20000144) returns 0x80 (0035ms, 35254ms total) +T3170 103:150 JLINK_WriteReg(R0, 0x00000280) returns 0x00 (0000ms, 35254ms total) +T3170 103:150 JLINK_WriteReg(R1, 0x00000080) returns 0x00 (0000ms, 35254ms total) +T3170 103:150 JLINK_WriteReg(R2, 0x20000144) returns 0x00 (0000ms, 35254ms total) +T3170 103:150 JLINK_WriteReg(R3, 0x00000000) returns 0x00 (0000ms, 35254ms total) +T3170 103:150 JLINK_WriteReg(R4, 0x00000000) returns 0x00 (0000ms, 35254ms total) +T3170 103:150 JLINK_WriteReg(R5, 0x00000000) returns 0x00 (0000ms, 35254ms total) +T3170 103:150 JLINK_WriteReg(R6, 0x00000000) returns 0x00 (0000ms, 35254ms total) +T3170 103:150 JLINK_WriteReg(R7, 0x00000000) returns 0x00 (0000ms, 35254ms total) +T3170 103:150 JLINK_WriteReg(R8, 0x00000000) returns 0x00 (0000ms, 35254ms total) +T3170 103:150 JLINK_WriteReg(R9, 0x2000013C) returns 0x00 (0000ms, 35254ms total) +T3170 103:150 JLINK_WriteReg(R10, 0x00000000) returns 0x00 (0000ms, 35254ms total) +T3170 103:150 JLINK_WriteReg(R11, 0x00000000) returns 0x00 (0000ms, 35254ms total) +T3170 103:150 JLINK_WriteReg(R12, 0x00000000) returns 0x00 (0000ms, 35254ms total) +T3170 103:150 JLINK_WriteReg(R13 (SP), 0x20001000) returns 0x00 (0000ms, 35254ms total) +T3170 103:150 JLINK_WriteReg(R14, 0x20000001) returns 0x00 (0000ms, 35254ms total) +T3170 103:150 JLINK_WriteReg(R15 (PC), 0x20000104) returns 0x00 (0000ms, 35254ms total) +T3170 103:150 JLINK_WriteReg(XPSR, 0x01000000) returns 0x00 (0000ms, 35254ms total) +T3170 103:150 JLINK_WriteReg(MSP, 0x20001000) returns 0x00 (0000ms, 35254ms total) +T3170 103:150 JLINK_WriteReg(PSP, 0x20001000) returns 0x00 (0000ms, 35254ms total) +T3170 103:150 JLINK_WriteReg(CFBP, 0x00000000) returns 0x00 (0000ms, 35254ms total) +T3170 103:150 JLINK_SetBPEx(Addr = 0x20000000, Type = 0xFFFFFFF2) returns 0x000000BB (0000ms, 35254ms total) +T3170 103:150 JLINK_Go() -- CPU_ReadMem(4 bytes @ 0xE0001000) (0055ms, 35309ms total) +T3170 103:205 JLINK_IsHalted() -- CPU_ReadMem(2 bytes @ 0x20000000) returns TRUE (0011ms, 35320ms total) +T3170 103:216 JLINK_ReadReg(R15 (PC)) returns 0x20000000 (0000ms, 35309ms total) +T3170 103:216 JLINK_ClrBPEx(BPHandle = 0x000000BB) returns 0x00 (0000ms, 35309ms total) +T3170 103:216 JLINK_ReadReg(R0) returns 0x00000300 (0000ms, 35309ms total) +T3170 103:216 JLINK_WriteMem(0x20000144, 0x0080 Bytes, ...) - Data: F8 D1 08 F0 0F 08 B8 F1 00 0F 07 D0 02 70 4F EA ... -- CPU_WriteMem(128 bytes @ 0x20000144) returns 0x80 (0085ms, 35394ms total) +T3170 103:301 JLINK_WriteReg(R0, 0x00000300) returns 0x00 (0000ms, 35394ms total) +T3170 103:301 JLINK_WriteReg(R1, 0x00000080) returns 0x00 (0000ms, 35394ms total) +T3170 103:301 JLINK_WriteReg(R2, 0x20000144) returns 0x00 (0000ms, 35394ms total) +T3170 103:301 JLINK_WriteReg(R3, 0x00000000) returns 0x00 (0001ms, 35395ms total) +T3170 103:302 JLINK_WriteReg(R4, 0x00000000) returns 0x00 (0000ms, 35395ms total) +T3170 103:302 JLINK_WriteReg(R5, 0x00000000) returns 0x00 (0000ms, 35395ms total) +T3170 103:302 JLINK_WriteReg(R6, 0x00000000) returns 0x00 (0000ms, 35395ms total) +T3170 103:302 JLINK_WriteReg(R7, 0x00000000) returns 0x00 (0000ms, 35395ms total) +T3170 103:302 JLINK_WriteReg(R8, 0x00000000) returns 0x00 (0000ms, 35395ms total) +T3170 103:302 JLINK_WriteReg(R9, 0x2000013C) returns 0x00 (0000ms, 35395ms total) +T3170 103:302 JLINK_WriteReg(R10, 0x00000000) returns 0x00 (0000ms, 35395ms total) +T3170 103:302 JLINK_WriteReg(R11, 0x00000000) returns 0x00 (0000ms, 35395ms total) +T3170 103:302 JLINK_WriteReg(R12, 0x00000000) returns 0x00 (0000ms, 35395ms total) +T3170 103:302 JLINK_WriteReg(R13 (SP), 0x20001000) returns 0x00 (0000ms, 35395ms total) +T3170 103:302 JLINK_WriteReg(R14, 0x20000001) returns 0x00 (0000ms, 35395ms total) +T3170 103:302 JLINK_WriteReg(R15 (PC), 0x20000104) returns 0x00 (0000ms, 35395ms total) +T3170 103:302 JLINK_WriteReg(XPSR, 0x01000000) returns 0x00 (0000ms, 35395ms total) +T3170 103:302 JLINK_WriteReg(MSP, 0x20001000) returns 0x00 (0000ms, 35395ms total) +T3170 103:302 JLINK_WriteReg(PSP, 0x20001000) returns 0x00 (0000ms, 35395ms total) +T3170 103:302 JLINK_WriteReg(CFBP, 0x00000000) returns 0x00 (0000ms, 35395ms total) +T3170 103:302 JLINK_SetBPEx(Addr = 0x20000000, Type = 0xFFFFFFF2) returns 0x000000BC (0000ms, 35395ms total) +T3170 103:302 JLINK_Go() -- CPU_ReadMem(4 bytes @ 0xE0001000) (0008ms, 35403ms total) +T3170 103:311 JLINK_IsHalted() -- CPU_ReadMem(2 bytes @ 0x20000000) returns TRUE (0038ms, 35442ms total) +T3170 103:349 JLINK_ReadReg(R15 (PC)) returns 0x20000000 (0001ms, 35405ms total) +T3170 103:350 JLINK_ClrBPEx(BPHandle = 0x000000BC) returns 0x00 (0000ms, 35405ms total) +T3170 103:350 JLINK_ReadReg(R0) returns 0x00000380 (0000ms, 35405ms total) +T3170 103:350 JLINK_WriteMem(0x20000144, 0x0080 Bytes, ...) - Data: 01 03 13 60 2F 4A 10 60 2F 4A 11 60 2F 48 4F F0 ... -- CPU_WriteMem(128 bytes @ 0x20000144) returns 0x80 (0051ms, 35456ms total) +T3170 103:402 JLINK_WriteReg(R0, 0x00000380) returns 0x00 (0000ms, 35456ms total) +T3170 103:402 JLINK_WriteReg(R1, 0x00000080) returns 0x00 (0000ms, 35456ms total) +T3170 103:402 JLINK_WriteReg(R2, 0x20000144) returns 0x00 (0000ms, 35456ms total) +T3170 103:402 JLINK_WriteReg(R3, 0x00000000) returns 0x00 (0000ms, 35456ms total) +T3170 103:402 JLINK_WriteReg(R4, 0x00000000) returns 0x00 (0000ms, 35456ms total) +T3170 103:402 JLINK_WriteReg(R5, 0x00000000) returns 0x00 (0000ms, 35456ms total) +T3170 103:402 JLINK_WriteReg(R6, 0x00000000) returns 0x00 (0000ms, 35456ms total) +T3170 103:402 JLINK_WriteReg(R7, 0x00000000) returns 0x00 (0000ms, 35456ms total) +T3170 103:402 JLINK_WriteReg(R8, 0x00000000) returns 0x00 (0000ms, 35456ms total) +T3170 103:402 JLINK_WriteReg(R9, 0x2000013C) returns 0x00 (0000ms, 35456ms total) +T3170 103:402 JLINK_WriteReg(R10, 0x00000000) returns 0x00 (0000ms, 35456ms total) +T3170 103:402 JLINK_WriteReg(R11, 0x00000000) returns 0x00 (0000ms, 35456ms total) +T3170 103:402 JLINK_WriteReg(R12, 0x00000000) returns 0x00 (0000ms, 35456ms total) +T3170 103:402 JLINK_WriteReg(R13 (SP), 0x20001000) returns 0x00 (0000ms, 35456ms total) +T3170 103:402 JLINK_WriteReg(R14, 0x20000001) returns 0x00 (0000ms, 35456ms total) +T3170 103:402 JLINK_WriteReg(R15 (PC), 0x20000104) returns 0x00 (0000ms, 35456ms total) +T3170 103:402 JLINK_WriteReg(XPSR, 0x01000000) returns 0x00 (0000ms, 35456ms total) +T3170 103:402 JLINK_WriteReg(MSP, 0x20001000) returns 0x00 (0000ms, 35456ms total) +T3170 103:402 JLINK_WriteReg(PSP, 0x20001000) returns 0x00 (0000ms, 35456ms total) +T3170 103:402 JLINK_WriteReg(CFBP, 0x00000000) returns 0x00 (0000ms, 35456ms total) +T3170 103:402 JLINK_SetBPEx(Addr = 0x20000000, Type = 0xFFFFFFF2) returns 0x000000BD (0000ms, 35456ms total) +T3170 103:402 JLINK_Go() -- CPU_ReadMem(4 bytes @ 0xE0001000) (0008ms, 35464ms total) +T3170 103:410 JLINK_IsHalted() -- CPU_ReadMem(2 bytes @ 0x20000000) returns TRUE (0090ms, 35554ms total) +T3170 103:500 JLINK_ReadReg(R15 (PC)) returns 0x20000000 (0000ms, 35464ms total) +T3170 103:500 JLINK_ClrBPEx(BPHandle = 0x000000BD) returns 0x00 (0000ms, 35464ms total) +T3170 103:500 JLINK_ReadReg(R0) returns 0x00000400 (0000ms, 35464ms total) +T3170 103:500 JLINK_WriteMem(0x20000144, 0x0080 Bytes, ...) - Data: 00 68 80 F3 08 88 61 B6 62 B6 70 47 1E F0 04 0F ... -- CPU_WriteMem(128 bytes @ 0x20000144) returns 0x80 (0004ms, 35468ms total) +T3170 103:504 JLINK_WriteReg(R0, 0x00000400) returns 0x00 (0000ms, 35468ms total) +T3170 103:504 JLINK_WriteReg(R1, 0x00000080) returns 0x00 (0000ms, 35468ms total) +T3170 103:504 JLINK_WriteReg(R2, 0x20000144) returns 0x00 (0000ms, 35468ms total) +T3170 103:504 JLINK_WriteReg(R3, 0x00000000) returns 0x00 (0000ms, 35468ms total) +T3170 103:504 JLINK_WriteReg(R4, 0x00000000) returns 0x00 (0000ms, 35468ms total) +T3170 103:504 JLINK_WriteReg(R5, 0x00000000) returns 0x00 (0000ms, 35468ms total) +T3170 103:504 JLINK_WriteReg(R6, 0x00000000) returns 0x00 (0000ms, 35468ms total) +T3170 103:504 JLINK_WriteReg(R7, 0x00000000) returns 0x00 (0000ms, 35468ms total) +T3170 103:504 JLINK_WriteReg(R8, 0x00000000) returns 0x00 (0000ms, 35468ms total) +T3170 103:504 JLINK_WriteReg(R9, 0x2000013C) returns 0x00 (0000ms, 35468ms total) +T3170 103:504 JLINK_WriteReg(R10, 0x00000000) returns 0x00 (0000ms, 35468ms total) +T3170 103:504 JLINK_WriteReg(R11, 0x00000000) returns 0x00 (0000ms, 35468ms total) +T3170 103:504 JLINK_WriteReg(R12, 0x00000000) returns 0x00 (0000ms, 35468ms total) +T3170 103:504 JLINK_WriteReg(R13 (SP), 0x20001000) returns 0x00 (0000ms, 35468ms total) +T3170 103:504 JLINK_WriteReg(R14, 0x20000001) returns 0x00 (0000ms, 35468ms total) +T3170 103:504 JLINK_WriteReg(R15 (PC), 0x20000104) returns 0x00 (0000ms, 35468ms total) +T3170 103:504 JLINK_WriteReg(XPSR, 0x01000000) returns 0x00 (0000ms, 35468ms total) +T3170 103:504 JLINK_WriteReg(MSP, 0x20001000) returns 0x00 (0000ms, 35468ms total) +T3170 103:504 JLINK_WriteReg(PSP, 0x20001000) returns 0x00 (0000ms, 35468ms total) +T3170 103:504 JLINK_WriteReg(CFBP, 0x00000000) returns 0x00 (0000ms, 35468ms total) +T3170 103:504 JLINK_SetBPEx(Addr = 0x20000000, Type = 0xFFFFFFF2) returns 0x000000BE (0000ms, 35468ms total) +T3170 103:504 JLINK_Go() -- CPU_ReadMem(4 bytes @ 0xE0001000) (0007ms, 35475ms total) +T3170 103:511 JLINK_IsHalted() -- CPU_ReadMem(2 bytes @ 0x20000000) returns TRUE (0067ms, 35542ms total) +T3170 103:578 JLINK_ReadReg(R15 (PC)) returns 0x20000000 (0000ms, 35475ms total) +T3170 103:578 JLINK_ClrBPEx(BPHandle = 0x000000BE) returns 0x00 (0000ms, 35475ms total) +T3170 103:578 JLINK_ReadReg(R0) returns 0x00000480 (0000ms, 35475ms total) +T3170 103:578 JLINK_WriteMem(0x20000144, 0x0080 Bytes, ...) - Data: 7B F9 00 21 8D F8 0B 10 0A 21 0D F1 0A 00 8D F8 ... -- CPU_WriteMem(128 bytes @ 0x20000144) returns 0x80 (0024ms, 35499ms total) +T3170 103:602 JLINK_WriteReg(R0, 0x00000480) returns 0x00 (0000ms, 35499ms total) +T3170 103:602 JLINK_WriteReg(R1, 0x00000080) returns 0x00 (0000ms, 35499ms total) +T3170 103:602 JLINK_WriteReg(R2, 0x20000144) returns 0x00 (0000ms, 35499ms total) +T3170 103:602 JLINK_WriteReg(R3, 0x00000000) returns 0x00 (0000ms, 35499ms total) +T3170 103:602 JLINK_WriteReg(R4, 0x00000000) returns 0x00 (0000ms, 35499ms total) +T3170 103:602 JLINK_WriteReg(R5, 0x00000000) returns 0x00 (0000ms, 35499ms total) +T3170 103:602 JLINK_WriteReg(R6, 0x00000000) returns 0x00 (0000ms, 35499ms total) +T3170 103:602 JLINK_WriteReg(R7, 0x00000000) returns 0x00 (0000ms, 35499ms total) +T3170 103:602 JLINK_WriteReg(R8, 0x00000000) returns 0x00 (0000ms, 35499ms total) +T3170 103:602 JLINK_WriteReg(R9, 0x2000013C) returns 0x00 (0000ms, 35499ms total) +T3170 103:602 JLINK_WriteReg(R10, 0x00000000) returns 0x00 (0000ms, 35499ms total) +T3170 103:602 JLINK_WriteReg(R11, 0x00000000) returns 0x00 (0000ms, 35499ms total) +T3170 103:602 JLINK_WriteReg(R12, 0x00000000) returns 0x00 (0000ms, 35499ms total) +T3170 103:602 JLINK_WriteReg(R13 (SP), 0x20001000) returns 0x00 (0000ms, 35499ms total) +T3170 103:602 JLINK_WriteReg(R14, 0x20000001) returns 0x00 (0000ms, 35499ms total) +T3170 103:602 JLINK_WriteReg(R15 (PC), 0x20000104) returns 0x00 (0000ms, 35499ms total) +T3170 103:602 JLINK_WriteReg(XPSR, 0x01000000) returns 0x00 (0000ms, 35499ms total) +T3170 103:602 JLINK_WriteReg(MSP, 0x20001000) returns 0x00 (0000ms, 35499ms total) +T3170 103:602 JLINK_WriteReg(PSP, 0x20001000) returns 0x00 (0000ms, 35499ms total) +T3170 103:602 JLINK_WriteReg(CFBP, 0x00000000) returns 0x00 (0000ms, 35499ms total) +T3170 103:602 JLINK_SetBPEx(Addr = 0x20000000, Type = 0xFFFFFFF2) returns 0x000000BF (0000ms, 35499ms total) +T3170 103:602 JLINK_Go() -- CPU_ReadMem(4 bytes @ 0xE0001000) (0007ms, 35506ms total) +T3170 103:609 JLINK_IsHalted() -- CPU_ReadMem(2 bytes @ 0x20000000) returns TRUE (0091ms, 35597ms total) +T3170 103:700 JLINK_ReadReg(R15 (PC)) returns 0x20000000 (0000ms, 35597ms total) +T3170 103:700 JLINK_ClrBPEx(BPHandle = 0x000000BF) returns 0x00 (0000ms, 35597ms total) +T3170 103:700 JLINK_ReadReg(R0) returns 0x00000500 (0000ms, 35597ms total) +T3170 103:700 JLINK_WriteMem(0x20000144, 0x0080 Bytes, ...) - Data: 02 F8 01 1B 0D D0 1B 0A F8 E7 11 F8 01 3B 00 2B ... -- CPU_WriteMem(128 bytes @ 0x20000144) returns 0x80 (0004ms, 35601ms total) +T3170 103:704 JLINK_WriteReg(R0, 0x00000500) returns 0x00 (0000ms, 35601ms total) +T3170 103:704 JLINK_WriteReg(R1, 0x00000080) returns 0x00 (0000ms, 35601ms total) +T3170 103:704 JLINK_WriteReg(R2, 0x20000144) returns 0x00 (0000ms, 35601ms total) +T3170 103:704 JLINK_WriteReg(R3, 0x00000000) returns 0x00 (0000ms, 35601ms total) +T3170 103:704 JLINK_WriteReg(R4, 0x00000000) returns 0x00 (0000ms, 35601ms total) +T3170 103:704 JLINK_WriteReg(R5, 0x00000000) returns 0x00 (0000ms, 35601ms total) +T3170 103:704 JLINK_WriteReg(R6, 0x00000000) returns 0x00 (0000ms, 35601ms total) +T3170 103:704 JLINK_WriteReg(R7, 0x00000000) returns 0x00 (0000ms, 35601ms total) +T3170 103:704 JLINK_WriteReg(R8, 0x00000000) returns 0x00 (0000ms, 35601ms total) +T3170 103:704 JLINK_WriteReg(R9, 0x2000013C) returns 0x00 (0000ms, 35601ms total) +T3170 103:704 JLINK_WriteReg(R10, 0x00000000) returns 0x00 (0000ms, 35601ms total) +T3170 103:704 JLINK_WriteReg(R11, 0x00000000) returns 0x00 (0000ms, 35601ms total) +T3170 103:704 JLINK_WriteReg(R12, 0x00000000) returns 0x00 (0000ms, 35601ms total) +T3170 103:704 JLINK_WriteReg(R13 (SP), 0x20001000) returns 0x00 (0000ms, 35601ms total) +T3170 103:704 JLINK_WriteReg(R14, 0x20000001) returns 0x00 (0000ms, 35601ms total) +T3170 103:704 JLINK_WriteReg(R15 (PC), 0x20000104) returns 0x00 (0000ms, 35601ms total) +T3170 103:704 JLINK_WriteReg(XPSR, 0x01000000) returns 0x00 (0000ms, 35601ms total) +T3170 103:704 JLINK_WriteReg(MSP, 0x20001000) returns 0x00 (0000ms, 35601ms total) +T3170 103:704 JLINK_WriteReg(PSP, 0x20001000) returns 0x00 (0000ms, 35601ms total) +T3170 103:704 JLINK_WriteReg(CFBP, 0x00000000) returns 0x00 (0000ms, 35601ms total) +T3170 103:704 JLINK_SetBPEx(Addr = 0x20000000, Type = 0xFFFFFFF2) returns 0x000000C0 (0000ms, 35601ms total) +T3170 103:704 JLINK_Go() -- CPU_ReadMem(4 bytes @ 0xE0001000) (0007ms, 35608ms total) +T3170 103:711 JLINK_IsHalted() -- CPU_ReadMem(2 bytes @ 0x20000000) returns TRUE (0089ms, 35697ms total) +T3170 103:800 JLINK_ReadReg(R15 (PC)) returns 0x20000000 (0000ms, 35608ms total) +T3170 103:800 JLINK_ClrBPEx(BPHandle = 0x000000C0) returns 0x00 (0000ms, 35608ms total) +T3170 103:800 JLINK_ReadReg(R0) returns 0x00000580 (0000ms, 35608ms total) +T3170 103:800 JLINK_WriteMem(0x20000144, 0x0080 Bytes, ...) - Data: C6 15 17 D0 D8 B2 E1 B2 40 1A 50 EA 05 61 10 D1 ... -- CPU_WriteMem(128 bytes @ 0x20000144) returns 0x80 (0004ms, 35612ms total) +T3170 103:804 JLINK_WriteReg(R0, 0x00000580) returns 0x00 (0000ms, 35612ms total) +T3170 103:804 JLINK_WriteReg(R1, 0x00000080) returns 0x00 (0000ms, 35612ms total) +T3170 103:804 JLINK_WriteReg(R2, 0x20000144) returns 0x00 (0000ms, 35612ms total) +T3170 103:804 JLINK_WriteReg(R3, 0x00000000) returns 0x00 (0000ms, 35612ms total) +T3170 103:804 JLINK_WriteReg(R4, 0x00000000) returns 0x00 (0000ms, 35612ms total) +T3170 103:804 JLINK_WriteReg(R5, 0x00000000) returns 0x00 (0000ms, 35612ms total) +T3170 103:804 JLINK_WriteReg(R6, 0x00000000) returns 0x00 (0000ms, 35612ms total) +T3170 103:804 JLINK_WriteReg(R7, 0x00000000) returns 0x00 (0000ms, 35612ms total) +T3170 103:804 JLINK_WriteReg(R8, 0x00000000) returns 0x00 (0000ms, 35612ms total) +T3170 103:804 JLINK_WriteReg(R9, 0x2000013C) returns 0x00 (0000ms, 35612ms total) +T3170 103:804 JLINK_WriteReg(R10, 0x00000000) returns 0x00 (0000ms, 35612ms total) +T3170 103:804 JLINK_WriteReg(R11, 0x00000000) returns 0x00 (0000ms, 35612ms total) +T3170 103:804 JLINK_WriteReg(R12, 0x00000000) returns 0x00 (0000ms, 35612ms total) +T3170 103:804 JLINK_WriteReg(R13 (SP), 0x20001000) returns 0x00 (0000ms, 35612ms total) +T3170 103:804 JLINK_WriteReg(R14, 0x20000001) returns 0x00 (0000ms, 35612ms total) +T3170 103:804 JLINK_WriteReg(R15 (PC), 0x20000104) returns 0x00 (0000ms, 35612ms total) +T3170 103:804 JLINK_WriteReg(XPSR, 0x01000000) returns 0x00 (0000ms, 35612ms total) +T3170 103:804 JLINK_WriteReg(MSP, 0x20001000) returns 0x00 (0000ms, 35612ms total) +T3170 103:804 JLINK_WriteReg(PSP, 0x20001000) returns 0x00 (0000ms, 35612ms total) +T3170 103:804 JLINK_WriteReg(CFBP, 0x00000000) returns 0x00 (0000ms, 35612ms total) +T3170 103:804 JLINK_SetBPEx(Addr = 0x20000000, Type = 0xFFFFFFF2) returns 0x000000C1 (0000ms, 35612ms total) +T3170 103:804 JLINK_Go() -- CPU_ReadMem(4 bytes @ 0xE0001000) (0006ms, 35618ms total) +T3170 103:810 JLINK_IsHalted() -- CPU_ReadMem(2 bytes @ 0x20000000) returns TRUE (0022ms, 35640ms total) +T3170 103:833 JLINK_ReadReg(R15 (PC)) returns 0x20000000 (0000ms, 35618ms total) +T3170 103:900 JLINK_ClrBPEx(BPHandle = 0x000000C1) returns 0x00 (0000ms, 35618ms total) +T3170 103:901 JLINK_ReadReg(R0) returns 0x00000600 (0000ms, 35619ms total) +T3170 103:901 JLINK_WriteMem(0x20000144, 0x0080 Bytes, ...) - Data: FB D1 11 F8 01 3B 00 2B 02 F8 01 3B F9 D1 70 47 ... -- CPU_WriteMem(128 bytes @ 0x20000144) returns 0x80 (0004ms, 35623ms total) +T3170 103:905 JLINK_WriteReg(R0, 0x00000600) returns 0x00 (0000ms, 35623ms total) +T3170 103:905 JLINK_WriteReg(R1, 0x00000080) returns 0x00 (0000ms, 35623ms total) +T3170 103:905 JLINK_WriteReg(R2, 0x20000144) returns 0x00 (0000ms, 35623ms total) +T3170 103:905 JLINK_WriteReg(R3, 0x00000000) returns 0x00 (0000ms, 35623ms total) +T3170 103:905 JLINK_WriteReg(R4, 0x00000000) returns 0x00 (0000ms, 35623ms total) +T3170 103:905 JLINK_WriteReg(R5, 0x00000000) returns 0x00 (0000ms, 35623ms total) +T3170 103:905 JLINK_WriteReg(R6, 0x00000000) returns 0x00 (0000ms, 35623ms total) +T3170 103:905 JLINK_WriteReg(R7, 0x00000000) returns 0x00 (0000ms, 35623ms total) +T3170 103:905 JLINK_WriteReg(R8, 0x00000000) returns 0x00 (0000ms, 35623ms total) +T3170 103:905 JLINK_WriteReg(R9, 0x2000013C) returns 0x00 (0000ms, 35623ms total) +T3170 103:905 JLINK_WriteReg(R10, 0x00000000) returns 0x00 (0000ms, 35623ms total) +T3170 103:905 JLINK_WriteReg(R11, 0x00000000) returns 0x00 (0000ms, 35623ms total) +T3170 103:905 JLINK_WriteReg(R12, 0x00000000) returns 0x00 (0000ms, 35623ms total) +T3170 103:905 JLINK_WriteReg(R13 (SP), 0x20001000) returns 0x00 (0000ms, 35623ms total) +T3170 103:905 JLINK_WriteReg(R14, 0x20000001) returns 0x00 (0000ms, 35623ms total) +T3170 103:905 JLINK_WriteReg(R15 (PC), 0x20000104) returns 0x00 (0000ms, 35623ms total) +T3170 103:905 JLINK_WriteReg(XPSR, 0x01000000) returns 0x00 (0000ms, 35623ms total) +T3170 103:905 JLINK_WriteReg(MSP, 0x20001000) returns 0x00 (0000ms, 35623ms total) +T3170 103:905 JLINK_WriteReg(PSP, 0x20001000) returns 0x00 (0000ms, 35623ms total) +T3170 103:905 JLINK_WriteReg(CFBP, 0x00000000) returns 0x00 (0000ms, 35623ms total) +T3170 103:905 JLINK_SetBPEx(Addr = 0x20000000, Type = 0xFFFFFFF2) returns 0x000000C2 (0000ms, 35623ms total) +T3170 103:905 JLINK_Go() -- CPU_ReadMem(4 bytes @ 0xE0001000) (0009ms, 35632ms total) +T3170 103:914 JLINK_IsHalted() -- CPU_ReadMem(2 bytes @ 0x20000000) returns TRUE (0090ms, 35722ms total) +T3170 104:004 JLINK_ReadReg(R15 (PC)) returns 0x20000000 (0000ms, 35632ms total) +T3170 104:004 JLINK_ClrBPEx(BPHandle = 0x000000C2) returns 0x00 (0000ms, 35632ms total) +T3170 104:005 JLINK_ReadReg(R0) returns 0x00000680 (0000ms, 35633ms total) +T3170 104:005 JLINK_WriteMem(0x20000144, 0x0080 Bytes, ...) - Data: 03 0C 00 F0 1B 80 CC F1 04 0C BC F1 02 0F 18 BF ... -- CPU_WriteMem(128 bytes @ 0x20000144) returns 0x80 (0003ms, 35636ms total) +T3170 104:008 JLINK_WriteReg(R0, 0x00000680) returns 0x00 (0000ms, 35636ms total) +T3170 104:008 JLINK_WriteReg(R1, 0x00000080) returns 0x00 (0000ms, 35636ms total) +T3170 104:008 JLINK_WriteReg(R2, 0x20000144) returns 0x00 (0000ms, 35636ms total) +T3170 104:008 JLINK_WriteReg(R3, 0x00000000) returns 0x00 (0000ms, 35636ms total) +T3170 104:008 JLINK_WriteReg(R4, 0x00000000) returns 0x00 (0000ms, 35636ms total) +T3170 104:008 JLINK_WriteReg(R5, 0x00000000) returns 0x00 (0000ms, 35636ms total) +T3170 104:008 JLINK_WriteReg(R6, 0x00000000) returns 0x00 (0001ms, 35637ms total) +T3170 104:009 JLINK_WriteReg(R7, 0x00000000) returns 0x00 (0000ms, 35637ms total) +T3170 104:009 JLINK_WriteReg(R8, 0x00000000) returns 0x00 (0000ms, 35637ms total) +T3170 104:009 JLINK_WriteReg(R9, 0x2000013C) returns 0x00 (0000ms, 35637ms total) +T3170 104:009 JLINK_WriteReg(R10, 0x00000000) returns 0x00 (0000ms, 35637ms total) +T3170 104:009 JLINK_WriteReg(R11, 0x00000000) returns 0x00 (0000ms, 35637ms total) +T3170 104:009 JLINK_WriteReg(R12, 0x00000000) returns 0x00 (0000ms, 35637ms total) +T3170 104:009 JLINK_WriteReg(R13 (SP), 0x20001000) returns 0x00 (0000ms, 35637ms total) +T3170 104:009 JLINK_WriteReg(R14, 0x20000001) returns 0x00 (0000ms, 35637ms total) +T3170 104:009 JLINK_WriteReg(R15 (PC), 0x20000104) returns 0x00 (0000ms, 35637ms total) +T3170 104:009 JLINK_WriteReg(XPSR, 0x01000000) returns 0x00 (0000ms, 35637ms total) +T3170 104:009 JLINK_WriteReg(MSP, 0x20001000) returns 0x00 (0000ms, 35637ms total) +T3170 104:009 JLINK_WriteReg(PSP, 0x20001000) returns 0x00 (0000ms, 35637ms total) +T3170 104:009 JLINK_WriteReg(CFBP, 0x00000000) returns 0x00 (0000ms, 35637ms total) +T3170 104:009 JLINK_SetBPEx(Addr = 0x20000000, Type = 0xFFFFFFF2) returns 0x000000C3 (0000ms, 35637ms total) +T3170 104:009 JLINK_Go() -- CPU_ReadMem(4 bytes @ 0xE0001000) (0006ms, 35643ms total) +T3170 104:015 JLINK_IsHalted() -- CPU_ReadMem(2 bytes @ 0x20000000) returns TRUE (0090ms, 35733ms total) +T3170 104:105 JLINK_ReadReg(R15 (PC)) returns 0x20000000 (0000ms, 35643ms total) +T3170 104:105 JLINK_ClrBPEx(BPHandle = 0x000000C3) returns 0x00 (0000ms, 35643ms total) +T3170 104:105 JLINK_ReadReg(R0) returns 0x00000700 (0000ms, 35643ms total) +T3170 104:105 JLINK_WriteMem(0x20000144, 0x0080 Bytes, ...) - Data: 00 F8 01 2B 70 47 10 B5 04 46 10 F0 03 0F 08 BF ... -- CPU_WriteMem(128 bytes @ 0x20000144) returns 0x80 (0004ms, 35647ms total) +T3170 104:109 JLINK_WriteReg(R0, 0x00000700) returns 0x00 (0000ms, 35647ms total) +T3170 104:109 JLINK_WriteReg(R1, 0x00000080) returns 0x00 (0000ms, 35647ms total) +T3170 104:109 JLINK_WriteReg(R2, 0x20000144) returns 0x00 (0000ms, 35647ms total) +T3170 104:109 JLINK_WriteReg(R3, 0x00000000) returns 0x00 (0000ms, 35647ms total) +T3170 104:109 JLINK_WriteReg(R4, 0x00000000) returns 0x00 (0000ms, 35647ms total) +T3170 104:109 JLINK_WriteReg(R5, 0x00000000) returns 0x00 (0000ms, 35647ms total) +T3170 104:109 JLINK_WriteReg(R6, 0x00000000) returns 0x00 (0000ms, 35647ms total) +T3170 104:109 JLINK_WriteReg(R7, 0x00000000) returns 0x00 (0000ms, 35647ms total) +T3170 104:109 JLINK_WriteReg(R8, 0x00000000) returns 0x00 (0000ms, 35647ms total) +T3170 104:109 JLINK_WriteReg(R9, 0x2000013C) returns 0x00 (0000ms, 35647ms total) +T3170 104:109 JLINK_WriteReg(R10, 0x00000000) returns 0x00 (0000ms, 35647ms total) +T3170 104:109 JLINK_WriteReg(R11, 0x00000000) returns 0x00 (0000ms, 35647ms total) +T3170 104:109 JLINK_WriteReg(R12, 0x00000000) returns 0x00 (0000ms, 35647ms total) +T3170 104:109 JLINK_WriteReg(R13 (SP), 0x20001000) returns 0x00 (0000ms, 35647ms total) +T3170 104:109 JLINK_WriteReg(R14, 0x20000001) returns 0x00 (0000ms, 35647ms total) +T3170 104:109 JLINK_WriteReg(R15 (PC), 0x20000104) returns 0x00 (0000ms, 35647ms total) +T3170 104:109 JLINK_WriteReg(XPSR, 0x01000000) returns 0x00 (0000ms, 35647ms total) +T3170 104:109 JLINK_WriteReg(MSP, 0x20001000) returns 0x00 (0000ms, 35647ms total) +T3170 104:109 JLINK_WriteReg(PSP, 0x20001000) returns 0x00 (0000ms, 35647ms total) +T3170 104:109 JLINK_WriteReg(CFBP, 0x00000000) returns 0x00 (0000ms, 35647ms total) +T3170 104:109 JLINK_SetBPEx(Addr = 0x20000000, Type = 0xFFFFFFF2) returns 0x000000C4 (0000ms, 35647ms total) +T3170 104:109 JLINK_Go() -- CPU_ReadMem(4 bytes @ 0xE0001000) (0091ms, 35738ms total) +T3170 104:200 JLINK_IsHalted() -- CPU_ReadMem(2 bytes @ 0x20000000) returns TRUE (0009ms, 35747ms total) +T3170 104:209 JLINK_ReadReg(R15 (PC)) returns 0x20000000 (0000ms, 35738ms total) +T3170 104:209 JLINK_ClrBPEx(BPHandle = 0x000000C4) returns 0x00 (0000ms, 35738ms total) +T3170 104:209 JLINK_ReadReg(R0) returns 0x00000780 (0000ms, 35738ms total) +T3170 104:209 JLINK_WriteMem(0x20000144, 0x0080 Bytes, ...) - Data: 00 F0 04 F8 20 78 00 28 F9 D1 10 BD 08 B5 69 46 ... -- CPU_WriteMem(128 bytes @ 0x20000144) returns 0x80 (0004ms, 35742ms total) +T3170 104:213 JLINK_WriteReg(R0, 0x00000780) returns 0x00 (0000ms, 35742ms total) +T3170 104:213 JLINK_WriteReg(R1, 0x00000080) returns 0x00 (0000ms, 35742ms total) +T3170 104:213 JLINK_WriteReg(R2, 0x20000144) returns 0x00 (0000ms, 35742ms total) +T3170 104:213 JLINK_WriteReg(R3, 0x00000000) returns 0x00 (0000ms, 35742ms total) +T3170 104:213 JLINK_WriteReg(R4, 0x00000000) returns 0x00 (0000ms, 35742ms total) +T3170 104:213 JLINK_WriteReg(R5, 0x00000000) returns 0x00 (0000ms, 35742ms total) +T3170 104:213 JLINK_WriteReg(R6, 0x00000000) returns 0x00 (0000ms, 35742ms total) +T3170 104:213 JLINK_WriteReg(R7, 0x00000000) returns 0x00 (0000ms, 35742ms total) +T3170 104:213 JLINK_WriteReg(R8, 0x00000000) returns 0x00 (0000ms, 35742ms total) +T3170 104:213 JLINK_WriteReg(R9, 0x2000013C) returns 0x00 (0000ms, 35742ms total) +T3170 104:213 JLINK_WriteReg(R10, 0x00000000) returns 0x00 (0000ms, 35742ms total) +T3170 104:213 JLINK_WriteReg(R11, 0x00000000) returns 0x00 (0000ms, 35742ms total) +T3170 104:213 JLINK_WriteReg(R12, 0x00000000) returns 0x00 (0000ms, 35742ms total) +T3170 104:213 JLINK_WriteReg(R13 (SP), 0x20001000) returns 0x00 (0000ms, 35742ms total) +T3170 104:213 JLINK_WriteReg(R14, 0x20000001) returns 0x00 (0000ms, 35742ms total) +T3170 104:213 JLINK_WriteReg(R15 (PC), 0x20000104) returns 0x00 (0000ms, 35742ms total) +T3170 104:213 JLINK_WriteReg(XPSR, 0x01000000) returns 0x00 (0000ms, 35742ms total) +T3170 104:213 JLINK_WriteReg(MSP, 0x20001000) returns 0x00 (0000ms, 35742ms total) +T3170 104:213 JLINK_WriteReg(PSP, 0x20001000) returns 0x00 (0000ms, 35742ms total) +T3170 104:213 JLINK_WriteReg(CFBP, 0x00000000) returns 0x00 (0000ms, 35742ms total) +T3170 104:213 JLINK_SetBPEx(Addr = 0x20000000, Type = 0xFFFFFFF2) returns 0x000000C5 (0000ms, 35742ms total) +T3170 104:213 JLINK_Go() -- CPU_ReadMem(4 bytes @ 0xE0001000) (0087ms, 35829ms total) +T3170 104:300 JLINK_IsHalted() -- CPU_ReadMem(2 bytes @ 0x20000000) returns TRUE (0011ms, 35840ms total) +T3170 104:311 JLINK_ReadReg(R15 (PC)) returns 0x20000000 (0000ms, 35829ms total) +T3170 104:311 JLINK_ClrBPEx(BPHandle = 0x000000C5) returns 0x00 (0000ms, 35829ms total) +T3170 104:311 JLINK_ReadReg(R0) returns 0x00000800 (0000ms, 35829ms total) +T3170 104:311 JLINK_WriteMem(0x20000144, 0x0080 Bytes, ...) - Data: C0 09 AC E8 C0 09 8D 46 70 47 10 B5 04 46 AF F3 ... -- CPU_WriteMem(128 bytes @ 0x20000144) returns 0x80 (0003ms, 35832ms total) +T3170 104:314 JLINK_WriteReg(R0, 0x00000800) returns 0x00 (0000ms, 35832ms total) +T3170 104:314 JLINK_WriteReg(R1, 0x00000080) returns 0x00 (0000ms, 35832ms total) +T3170 104:314 JLINK_WriteReg(R2, 0x20000144) returns 0x00 (0000ms, 35832ms total) +T3170 104:314 JLINK_WriteReg(R3, 0x00000000) returns 0x00 (0000ms, 35832ms total) +T3170 104:314 JLINK_WriteReg(R4, 0x00000000) returns 0x00 (0000ms, 35832ms total) +T3170 104:314 JLINK_WriteReg(R5, 0x00000000) returns 0x00 (0000ms, 35832ms total) +T3170 104:314 JLINK_WriteReg(R6, 0x00000000) returns 0x00 (0000ms, 35832ms total) +T3170 104:314 JLINK_WriteReg(R7, 0x00000000) returns 0x00 (0000ms, 35832ms total) +T3170 104:314 JLINK_WriteReg(R8, 0x00000000) returns 0x00 (0000ms, 35832ms total) +T3170 104:314 JLINK_WriteReg(R9, 0x2000013C) returns 0x00 (0000ms, 35832ms total) +T3170 104:314 JLINK_WriteReg(R10, 0x00000000) returns 0x00 (0000ms, 35832ms total) +T3170 104:314 JLINK_WriteReg(R11, 0x00000000) returns 0x00 (0000ms, 35832ms total) +T3170 104:314 JLINK_WriteReg(R12, 0x00000000) returns 0x00 (0000ms, 35832ms total) +T3170 104:314 JLINK_WriteReg(R13 (SP), 0x20001000) returns 0x00 (0000ms, 35832ms total) +T3170 104:314 JLINK_WriteReg(R14, 0x20000001) returns 0x00 (0000ms, 35832ms total) +T3170 104:314 JLINK_WriteReg(R15 (PC), 0x20000104) returns 0x00 (0000ms, 35832ms total) +T3170 104:314 JLINK_WriteReg(XPSR, 0x01000000) returns 0x00 (0000ms, 35832ms total) +T3170 104:314 JLINK_WriteReg(MSP, 0x20001000) returns 0x00 (0000ms, 35832ms total) +T3170 104:314 JLINK_WriteReg(PSP, 0x20001000) returns 0x00 (0000ms, 35832ms total) +T3170 104:314 JLINK_WriteReg(CFBP, 0x00000000) returns 0x00 (0000ms, 35832ms total) +T3170 104:314 JLINK_SetBPEx(Addr = 0x20000000, Type = 0xFFFFFFF2) returns 0x000000C6 (0000ms, 35832ms total) +T3170 104:314 JLINK_Go() -- CPU_ReadMem(4 bytes @ 0xE0001000) (0091ms, 35923ms total) +T3170 104:405 JLINK_IsHalted() -- CPU_ReadMem(2 bytes @ 0x20000000) returns TRUE (0006ms, 35929ms total) +T3170 104:411 JLINK_ReadReg(R15 (PC)) returns 0x20000000 (0000ms, 35923ms total) +T3170 104:411 JLINK_ClrBPEx(BPHandle = 0x000000C6) returns 0x00 (0000ms, 35923ms total) +T3170 104:411 JLINK_ReadReg(R0) returns 0x00000880 (0000ms, 35923ms total) +T3170 104:411 JLINK_WriteMem(0x20000144, 0x0080 Bytes, ...) - Data: BD E8 70 40 0A 20 FF F7 81 BF 10 B5 04 F0 99 F8 ... -- CPU_WriteMem(128 bytes @ 0x20000144) returns 0x80 (0004ms, 35927ms total) +T3170 104:415 JLINK_WriteReg(R0, 0x00000880) returns 0x00 (0000ms, 35927ms total) +T3170 104:415 JLINK_WriteReg(R1, 0x00000080) returns 0x00 (0000ms, 35927ms total) +T3170 104:415 JLINK_WriteReg(R2, 0x20000144) returns 0x00 (0000ms, 35927ms total) +T3170 104:415 JLINK_WriteReg(R3, 0x00000000) returns 0x00 (0000ms, 35927ms total) +T3170 104:415 JLINK_WriteReg(R4, 0x00000000) returns 0x00 (0000ms, 35927ms total) +T3170 104:415 JLINK_WriteReg(R5, 0x00000000) returns 0x00 (0000ms, 35927ms total) +T3170 104:415 JLINK_WriteReg(R6, 0x00000000) returns 0x00 (0000ms, 35927ms total) +T3170 104:415 JLINK_WriteReg(R7, 0x00000000) returns 0x00 (0000ms, 35927ms total) +T3170 104:415 JLINK_WriteReg(R8, 0x00000000) returns 0x00 (0000ms, 35927ms total) +T3170 104:415 JLINK_WriteReg(R9, 0x2000013C) returns 0x00 (0000ms, 35927ms total) +T3170 104:415 JLINK_WriteReg(R10, 0x00000000) returns 0x00 (0000ms, 35927ms total) +T3170 104:415 JLINK_WriteReg(R11, 0x00000000) returns 0x00 (0000ms, 35927ms total) +T3170 104:415 JLINK_WriteReg(R12, 0x00000000) returns 0x00 (0000ms, 35927ms total) +T3170 104:415 JLINK_WriteReg(R13 (SP), 0x20001000) returns 0x00 (0000ms, 35927ms total) +T3170 104:415 JLINK_WriteReg(R14, 0x20000001) returns 0x00 (0000ms, 35927ms total) +T3170 104:415 JLINK_WriteReg(R15 (PC), 0x20000104) returns 0x00 (0000ms, 35927ms total) +T3170 104:415 JLINK_WriteReg(XPSR, 0x01000000) returns 0x00 (0000ms, 35927ms total) +T3170 104:415 JLINK_WriteReg(MSP, 0x20001000) returns 0x00 (0000ms, 35927ms total) +T3170 104:415 JLINK_WriteReg(PSP, 0x20001000) returns 0x00 (0000ms, 35927ms total) +T3170 104:415 JLINK_WriteReg(CFBP, 0x00000000) returns 0x00 (0000ms, 35927ms total) +T3170 104:415 JLINK_SetBPEx(Addr = 0x20000000, Type = 0xFFFFFFF2) returns 0x000000C7 (0000ms, 35927ms total) +T3170 104:415 JLINK_Go() -- CPU_ReadMem(4 bytes @ 0xE0001000) (0087ms, 36014ms total) +T3170 104:502 JLINK_IsHalted() -- CPU_ReadMem(2 bytes @ 0x20000000) returns TRUE (0009ms, 36023ms total) +T3170 104:511 JLINK_ReadReg(R15 (PC)) returns 0x20000000 (0000ms, 36014ms total) +T3170 104:511 JLINK_ClrBPEx(BPHandle = 0x000000C7) returns 0x00 (0000ms, 36014ms total) +T3170 104:511 JLINK_ReadReg(R0) returns 0x00000900 (0000ms, 36014ms total) +T3170 104:511 JLINK_WriteMem(0x20000144, 0x0080 Bytes, ...) - Data: 10 B5 1A 49 89 6C 41 F4 80 11 18 4A 91 64 11 46 ... -- CPU_WriteMem(128 bytes @ 0x20000144) returns 0x80 (0003ms, 36017ms total) +T3170 104:514 JLINK_WriteReg(R0, 0x00000900) returns 0x00 (0000ms, 36017ms total) +T3170 104:514 JLINK_WriteReg(R1, 0x00000080) returns 0x00 (0000ms, 36017ms total) +T3170 104:514 JLINK_WriteReg(R2, 0x20000144) returns 0x00 (0000ms, 36017ms total) +T3170 104:514 JLINK_WriteReg(R3, 0x00000000) returns 0x00 (0000ms, 36017ms total) +T3170 104:514 JLINK_WriteReg(R4, 0x00000000) returns 0x00 (0000ms, 36017ms total) +T3170 104:514 JLINK_WriteReg(R5, 0x00000000) returns 0x00 (0000ms, 36017ms total) +T3170 104:514 JLINK_WriteReg(R6, 0x00000000) returns 0x00 (0000ms, 36017ms total) +T3170 104:514 JLINK_WriteReg(R7, 0x00000000) returns 0x00 (0000ms, 36017ms total) +T3170 104:514 JLINK_WriteReg(R8, 0x00000000) returns 0x00 (0000ms, 36017ms total) +T3170 104:514 JLINK_WriteReg(R9, 0x2000013C) returns 0x00 (0000ms, 36017ms total) +T3170 104:514 JLINK_WriteReg(R10, 0x00000000) returns 0x00 (0000ms, 36017ms total) +T3170 104:514 JLINK_WriteReg(R11, 0x00000000) returns 0x00 (0000ms, 36017ms total) +T3170 104:514 JLINK_WriteReg(R12, 0x00000000) returns 0x00 (0000ms, 36017ms total) +T3170 104:514 JLINK_WriteReg(R13 (SP), 0x20001000) returns 0x00 (0000ms, 36017ms total) +T3170 104:514 JLINK_WriteReg(R14, 0x20000001) returns 0x00 (0000ms, 36017ms total) +T3170 104:514 JLINK_WriteReg(R15 (PC), 0x20000104) returns 0x00 (0000ms, 36017ms total) +T3170 104:514 JLINK_WriteReg(XPSR, 0x01000000) returns 0x00 (0000ms, 36017ms total) +T3170 104:514 JLINK_WriteReg(MSP, 0x20001000) returns 0x00 (0000ms, 36017ms total) +T3170 104:514 JLINK_WriteReg(PSP, 0x20001000) returns 0x00 (0000ms, 36017ms total) +T3170 104:514 JLINK_WriteReg(CFBP, 0x00000000) returns 0x00 (0000ms, 36017ms total) +T3170 104:514 JLINK_SetBPEx(Addr = 0x20000000, Type = 0xFFFFFFF2) returns 0x000000C8 (0000ms, 36017ms total) +T3170 104:514 JLINK_Go() -- CPU_ReadMem(4 bytes @ 0xE0001000) (0089ms, 36106ms total) +T3170 104:603 JLINK_IsHalted() -- CPU_ReadMem(2 bytes @ 0x20000000) returns TRUE (0011ms, 36117ms total) +T3170 104:614 JLINK_ReadReg(R15 (PC)) returns 0x20000000 (0000ms, 36106ms total) +T3170 104:614 JLINK_ClrBPEx(BPHandle = 0x000000C8) returns 0x00 (0000ms, 36106ms total) +T3170 104:614 JLINK_ReadReg(R0) returns 0x00000980 (0000ms, 36106ms total) +T3170 104:614 JLINK_WriteMem(0x20000144, 0x0080 Bytes, ...) - Data: 05 46 0F 46 2C 46 20 2C 00 D2 04 E0 A4 22 0A A1 ... -- CPU_WriteMem(128 bytes @ 0x20000144) returns 0x80 (0015ms, 36121ms total) +T3170 104:629 JLINK_WriteReg(R0, 0x00000980) returns 0x00 (0000ms, 36121ms total) +T3170 104:629 JLINK_WriteReg(R1, 0x00000080) returns 0x00 (0000ms, 36121ms total) +T3170 104:629 JLINK_WriteReg(R2, 0x20000144) returns 0x00 (0000ms, 36121ms total) +T3170 104:629 JLINK_WriteReg(R3, 0x00000000) returns 0x00 (0000ms, 36121ms total) +T3170 104:629 JLINK_WriteReg(R4, 0x00000000) returns 0x00 (0000ms, 36121ms total) +T3170 104:629 JLINK_WriteReg(R5, 0x00000000) returns 0x00 (0000ms, 36121ms total) +T3170 104:629 JLINK_WriteReg(R6, 0x00000000) returns 0x00 (0000ms, 36121ms total) +T3170 104:629 JLINK_WriteReg(R7, 0x00000000) returns 0x00 (0000ms, 36121ms total) +T3170 104:629 JLINK_WriteReg(R8, 0x00000000) returns 0x00 (0000ms, 36121ms total) +T3170 104:629 JLINK_WriteReg(R9, 0x2000013C) returns 0x00 (0000ms, 36121ms total) +T3170 104:629 JLINK_WriteReg(R10, 0x00000000) returns 0x00 (0000ms, 36121ms total) +T3170 104:629 JLINK_WriteReg(R11, 0x00000000) returns 0x00 (0000ms, 36121ms total) +T3170 104:629 JLINK_WriteReg(R12, 0x00000000) returns 0x00 (0000ms, 36121ms total) +T3170 104:629 JLINK_WriteReg(R13 (SP), 0x20001000) returns 0x00 (0000ms, 36121ms total) +T3170 104:629 JLINK_WriteReg(R14, 0x20000001) returns 0x00 (0000ms, 36121ms total) +T3170 104:629 JLINK_WriteReg(R15 (PC), 0x20000104) returns 0x00 (0000ms, 36121ms total) +T3170 104:629 JLINK_WriteReg(XPSR, 0x01000000) returns 0x00 (0000ms, 36121ms total) +T3170 104:629 JLINK_WriteReg(MSP, 0x20001000) returns 0x00 (0000ms, 36121ms total) +T3170 104:629 JLINK_WriteReg(PSP, 0x20001000) returns 0x00 (0000ms, 36121ms total) +T3170 104:629 JLINK_WriteReg(CFBP, 0x00000000) returns 0x00 (0000ms, 36121ms total) +T3170 104:629 JLINK_SetBPEx(Addr = 0x20000000, Type = 0xFFFFFFF2) returns 0x000000C9 (0000ms, 36121ms total) +T3170 104:629 JLINK_Go() -- CPU_ReadMem(4 bytes @ 0xE0001000) (0076ms, 36197ms total) +T3170 104:705 JLINK_IsHalted() -- CPU_ReadMem(2 bytes @ 0x20000000) returns TRUE (0011ms, 36208ms total) +T3170 104:716 JLINK_ReadReg(R15 (PC)) returns 0x20000000 (0000ms, 36197ms total) +T3170 104:716 JLINK_ClrBPEx(BPHandle = 0x000000C9) returns 0x00 (0000ms, 36197ms total) +T3170 104:716 JLINK_ReadReg(R0) returns 0x00000A00 (0000ms, 36197ms total) +T3170 104:716 JLINK_WriteMem(0x20000144, 0x0080 Bytes, ...) - Data: 04 46 0D 46 16 46 00 27 B8 46 20 48 84 42 02 D0 ... -- CPU_WriteMem(128 bytes @ 0x20000144) returns 0x80 (0085ms, 36282ms total) +T3170 104:801 JLINK_WriteReg(R0, 0x00000A00) returns 0x00 (0000ms, 36282ms total) +T3170 104:801 JLINK_WriteReg(R1, 0x00000080) returns 0x00 (0000ms, 36282ms total) +T3170 104:801 JLINK_WriteReg(R2, 0x20000144) returns 0x00 (0000ms, 36282ms total) +T3170 104:801 JLINK_WriteReg(R3, 0x00000000) returns 0x00 (0000ms, 36282ms total) +T3170 104:801 JLINK_WriteReg(R4, 0x00000000) returns 0x00 (0000ms, 36282ms total) +T3170 104:801 JLINK_WriteReg(R5, 0x00000000) returns 0x00 (0001ms, 36283ms total) +T3170 104:802 JLINK_WriteReg(R6, 0x00000000) returns 0x00 (0000ms, 36283ms total) +T3170 104:802 JLINK_WriteReg(R7, 0x00000000) returns 0x00 (0000ms, 36283ms total) +T3170 104:802 JLINK_WriteReg(R8, 0x00000000) returns 0x00 (0000ms, 36283ms total) +T3170 104:802 JLINK_WriteReg(R9, 0x2000013C) returns 0x00 (0000ms, 36283ms total) +T3170 104:802 JLINK_WriteReg(R10, 0x00000000) returns 0x00 (0000ms, 36283ms total) +T3170 104:802 JLINK_WriteReg(R11, 0x00000000) returns 0x00 (0000ms, 36283ms total) +T3170 104:802 JLINK_WriteReg(R12, 0x00000000) returns 0x00 (0000ms, 36283ms total) +T3170 104:802 JLINK_WriteReg(R13 (SP), 0x20001000) returns 0x00 (0000ms, 36283ms total) +T3170 104:802 JLINK_WriteReg(R14, 0x20000001) returns 0x00 (0000ms, 36283ms total) +T3170 104:802 JLINK_WriteReg(R15 (PC), 0x20000104) returns 0x00 (0000ms, 36283ms total) +T3170 104:802 JLINK_WriteReg(XPSR, 0x01000000) returns 0x00 (0000ms, 36283ms total) +T3170 104:802 JLINK_WriteReg(MSP, 0x20001000) returns 0x00 (0000ms, 36283ms total) +T3170 104:802 JLINK_WriteReg(PSP, 0x20001000) returns 0x00 (0000ms, 36283ms total) +T3170 104:802 JLINK_WriteReg(CFBP, 0x00000000) returns 0x00 (0000ms, 36283ms total) +T3170 104:802 JLINK_SetBPEx(Addr = 0x20000000, Type = 0xFFFFFFF2) returns 0x000000CA (0000ms, 36283ms total) +T3170 104:802 JLINK_Go() -- CPU_ReadMem(4 bytes @ 0xE0001000) (0007ms, 36290ms total) +T3170 104:809 JLINK_IsHalted() -- CPU_ReadMem(2 bytes @ 0x20000000) returns TRUE (0021ms, 36311ms total) +T3170 104:830 JLINK_ReadReg(R15 (PC)) returns 0x20000000 (0000ms, 36290ms total) +T3170 104:830 JLINK_ClrBPEx(BPHandle = 0x000000CA) returns 0x00 (0000ms, 36290ms total) +T3170 104:830 JLINK_ReadReg(R0) returns 0x00000A80 (0000ms, 36290ms total) +T3170 104:830 JLINK_WriteMem(0x20000144, 0x0080 Bytes, ...) - Data: B7 42 EF D3 38 46 BD E8 F0 81 00 00 F8 10 00 20 ... -- CPU_WriteMem(128 bytes @ 0x20000144) returns 0x80 (0071ms, 36361ms total) +T3170 104:901 JLINK_WriteReg(R0, 0x00000A80) returns 0x00 (0000ms, 36361ms total) +T3170 104:901 JLINK_WriteReg(R1, 0x00000080) returns 0x00 (0000ms, 36361ms total) +T3170 104:902 JLINK_WriteReg(R2, 0x20000144) returns 0x00 (0000ms, 36362ms total) +T3170 104:902 JLINK_WriteReg(R3, 0x00000000) returns 0x00 (0000ms, 36362ms total) +T3170 104:902 JLINK_WriteReg(R4, 0x00000000) returns 0x00 (0000ms, 36362ms total) +T3170 104:902 JLINK_WriteReg(R5, 0x00000000) returns 0x00 (0000ms, 36362ms total) +T3170 104:902 JLINK_WriteReg(R6, 0x00000000) returns 0x00 (0000ms, 36362ms total) +T3170 104:902 JLINK_WriteReg(R7, 0x00000000) returns 0x00 (0000ms, 36362ms total) +T3170 104:902 JLINK_WriteReg(R8, 0x00000000) returns 0x00 (0000ms, 36362ms total) +T3170 104:902 JLINK_WriteReg(R9, 0x2000013C) returns 0x00 (0000ms, 36362ms total) +T3170 104:902 JLINK_WriteReg(R10, 0x00000000) returns 0x00 (0000ms, 36362ms total) +T3170 104:902 JLINK_WriteReg(R11, 0x00000000) returns 0x00 (0000ms, 36362ms total) +T3170 104:902 JLINK_WriteReg(R12, 0x00000000) returns 0x00 (0000ms, 36362ms total) +T3170 104:902 JLINK_WriteReg(R13 (SP), 0x20001000) returns 0x00 (0000ms, 36362ms total) +T3170 104:902 JLINK_WriteReg(R14, 0x20000001) returns 0x00 (0000ms, 36362ms total) +T3170 104:902 JLINK_WriteReg(R15 (PC), 0x20000104) returns 0x00 (0000ms, 36362ms total) +T3170 104:902 JLINK_WriteReg(XPSR, 0x01000000) returns 0x00 (0000ms, 36362ms total) +T3170 104:902 JLINK_WriteReg(MSP, 0x20001000) returns 0x00 (0000ms, 36362ms total) +T3170 104:902 JLINK_WriteReg(PSP, 0x20001000) returns 0x00 (0000ms, 36362ms total) +T3170 104:902 JLINK_WriteReg(CFBP, 0x00000000) returns 0x00 (0000ms, 36362ms total) +T3170 104:902 JLINK_SetBPEx(Addr = 0x20000000, Type = 0xFFFFFFF2) returns 0x000000CB (0000ms, 36362ms total) +T3170 104:902 JLINK_Go() -- CPU_ReadMem(4 bytes @ 0xE0001000) (0008ms, 36370ms total) +T3170 104:910 JLINK_IsHalted() -- CPU_ReadMem(2 bytes @ 0x20000000) returns TRUE (0090ms, 36460ms total) +T3170 105:000 JLINK_ReadReg(R15 (PC)) returns 0x20000000 (0000ms, 36370ms total) +T3170 105:000 JLINK_ClrBPEx(BPHandle = 0x000000CB) returns 0x00 (0000ms, 36370ms total) +T3170 105:000 JLINK_ReadReg(R0) returns 0x00000B00 (0000ms, 36370ms total) +T3170 105:000 JLINK_WriteMem(0x20000144, 0x0080 Bytes, ...) - Data: 28 75 69 6E 74 38 5F 74 20 2A 29 30 29 00 00 00 ... -- CPU_WriteMem(128 bytes @ 0x20000144) returns 0x80 (0004ms, 36374ms total) +T3170 105:004 JLINK_WriteReg(R0, 0x00000B00) returns 0x00 (0000ms, 36374ms total) +T3170 105:004 JLINK_WriteReg(R1, 0x00000080) returns 0x00 (0000ms, 36374ms total) +T3170 105:004 JLINK_WriteReg(R2, 0x20000144) returns 0x00 (0000ms, 36374ms total) +T3170 105:004 JLINK_WriteReg(R3, 0x00000000) returns 0x00 (0000ms, 36374ms total) +T3170 105:004 JLINK_WriteReg(R4, 0x00000000) returns 0x00 (0000ms, 36374ms total) +T3170 105:004 JLINK_WriteReg(R5, 0x00000000) returns 0x00 (0000ms, 36374ms total) +T3170 105:004 JLINK_WriteReg(R6, 0x00000000) returns 0x00 (0000ms, 36374ms total) +T3170 105:004 JLINK_WriteReg(R7, 0x00000000) returns 0x00 (0000ms, 36374ms total) +T3170 105:004 JLINK_WriteReg(R8, 0x00000000) returns 0x00 (0000ms, 36374ms total) +T3170 105:004 JLINK_WriteReg(R9, 0x2000013C) returns 0x00 (0000ms, 36374ms total) +T3170 105:004 JLINK_WriteReg(R10, 0x00000000) returns 0x00 (0000ms, 36374ms total) +T3170 105:004 JLINK_WriteReg(R11, 0x00000000) returns 0x00 (0000ms, 36374ms total) +T3170 105:004 JLINK_WriteReg(R12, 0x00000000) returns 0x00 (0000ms, 36374ms total) +T3170 105:004 JLINK_WriteReg(R13 (SP), 0x20001000) returns 0x00 (0000ms, 36374ms total) +T3170 105:004 JLINK_WriteReg(R14, 0x20000001) returns 0x00 (0000ms, 36374ms total) +T3170 105:004 JLINK_WriteReg(R15 (PC), 0x20000104) returns 0x00 (0000ms, 36374ms total) +T3170 105:004 JLINK_WriteReg(XPSR, 0x01000000) returns 0x00 (0000ms, 36374ms total) +T3170 105:004 JLINK_WriteReg(MSP, 0x20001000) returns 0x00 (0000ms, 36374ms total) +T3170 105:004 JLINK_WriteReg(PSP, 0x20001000) returns 0x00 (0000ms, 36374ms total) +T3170 105:004 JLINK_WriteReg(CFBP, 0x00000000) returns 0x00 (0000ms, 36374ms total) +T3170 105:004 JLINK_SetBPEx(Addr = 0x20000000, Type = 0xFFFFFFF2) returns 0x000000CC (0000ms, 36374ms total) +T3170 105:004 JLINK_Go() -- CPU_ReadMem(4 bytes @ 0xE0001000) (0007ms, 36381ms total) +T3170 105:011 JLINK_IsHalted() -- CPU_ReadMem(2 bytes @ 0x20000000) returns TRUE (0089ms, 36470ms total) +T3170 105:100 JLINK_ReadReg(R15 (PC)) returns 0x20000000 (0000ms, 36381ms total) +T3170 105:104 JLINK_ClrBPEx(BPHandle = 0x000000CC) returns 0x00 (0000ms, 36381ms total) +T3170 105:104 JLINK_ReadReg(R0) returns 0x00000B80 (0000ms, 36381ms total) +T3170 105:104 JLINK_WriteMem(0x20000144, 0x0080 Bytes, ...) - Data: 69 62 72 61 72 69 65 73 5C 6D 73 73 5F 75 61 72 ... -- CPU_WriteMem(128 bytes @ 0x20000144) returns 0x80 (0004ms, 36385ms total) +T3170 105:108 JLINK_WriteReg(R0, 0x00000B80) returns 0x00 (0000ms, 36385ms total) +T3170 105:108 JLINK_WriteReg(R1, 0x00000080) returns 0x00 (0000ms, 36385ms total) +T3170 105:108 JLINK_WriteReg(R2, 0x20000144) returns 0x00 (0000ms, 36385ms total) +T3170 105:108 JLINK_WriteReg(R3, 0x00000000) returns 0x00 (0000ms, 36385ms total) +T3170 105:108 JLINK_WriteReg(R4, 0x00000000) returns 0x00 (0000ms, 36385ms total) +T3170 105:108 JLINK_WriteReg(R5, 0x00000000) returns 0x00 (0000ms, 36385ms total) +T3170 105:108 JLINK_WriteReg(R6, 0x00000000) returns 0x00 (0000ms, 36385ms total) +T3170 105:108 JLINK_WriteReg(R7, 0x00000000) returns 0x00 (0000ms, 36385ms total) +T3170 105:108 JLINK_WriteReg(R8, 0x00000000) returns 0x00 (0000ms, 36385ms total) +T3170 105:108 JLINK_WriteReg(R9, 0x2000013C) returns 0x00 (0000ms, 36385ms total) +T3170 105:108 JLINK_WriteReg(R10, 0x00000000) returns 0x00 (0000ms, 36385ms total) +T3170 105:108 JLINK_WriteReg(R11, 0x00000000) returns 0x00 (0000ms, 36385ms total) +T3170 105:108 JLINK_WriteReg(R12, 0x00000000) returns 0x00 (0000ms, 36385ms total) +T3170 105:108 JLINK_WriteReg(R13 (SP), 0x20001000) returns 0x00 (0000ms, 36385ms total) +T3170 105:108 JLINK_WriteReg(R14, 0x20000001) returns 0x00 (0000ms, 36385ms total) +T3170 105:108 JLINK_WriteReg(R15 (PC), 0x20000104) returns 0x00 (0000ms, 36385ms total) +T3170 105:108 JLINK_WriteReg(XPSR, 0x01000000) returns 0x00 (0000ms, 36385ms total) +T3170 105:108 JLINK_WriteReg(MSP, 0x20001000) returns 0x00 (0000ms, 36385ms total) +T3170 105:108 JLINK_WriteReg(PSP, 0x20001000) returns 0x00 (0000ms, 36385ms total) +T3170 105:108 JLINK_WriteReg(CFBP, 0x00000000) returns 0x00 (0000ms, 36385ms total) +T3170 105:108 JLINK_SetBPEx(Addr = 0x20000000, Type = 0xFFFFFFF2) returns 0x000000CD (0000ms, 36385ms total) +T3170 105:108 JLINK_Go() -- CPU_ReadMem(4 bytes @ 0xE0001000) (0006ms, 36391ms total) +T3170 105:115 JLINK_IsHalted() -- CPU_ReadMem(2 bytes @ 0x20000000) returns TRUE (0092ms, 36484ms total) +T3170 105:208 JLINK_ReadReg(R15 (PC)) returns 0x20000000 (0000ms, 36392ms total) +T3170 105:208 JLINK_ClrBPEx(BPHandle = 0x000000CD) returns 0x00 (0000ms, 36392ms total) +T3170 105:208 JLINK_ReadReg(R0) returns 0x00000C00 (0000ms, 36392ms total) +T3170 105:208 JLINK_WriteMem(0x20000144, 0x0080 Bytes, ...) - Data: 84 42 02 D0 64 48 84 42 71 D1 20 68 00 7A 00 F0 ... -- CPU_WriteMem(128 bytes @ 0x20000144) returns 0x80 (0004ms, 36396ms total) +T3170 105:212 JLINK_WriteReg(R0, 0x00000C00) returns 0x00 (0000ms, 36396ms total) +T3170 105:212 JLINK_WriteReg(R1, 0x00000080) returns 0x00 (0000ms, 36396ms total) +T3170 105:212 JLINK_WriteReg(R2, 0x20000144) returns 0x00 (0000ms, 36396ms total) +T3170 105:212 JLINK_WriteReg(R3, 0x00000000) returns 0x00 (0000ms, 36396ms total) +T3170 105:212 JLINK_WriteReg(R4, 0x00000000) returns 0x00 (0000ms, 36396ms total) +T3170 105:212 JLINK_WriteReg(R5, 0x00000000) returns 0x00 (0000ms, 36396ms total) +T3170 105:212 JLINK_WriteReg(R6, 0x00000000) returns 0x00 (0000ms, 36396ms total) +T3170 105:212 JLINK_WriteReg(R7, 0x00000000) returns 0x00 (0000ms, 36396ms total) +T3170 105:212 JLINK_WriteReg(R8, 0x00000000) returns 0x00 (0000ms, 36396ms total) +T3170 105:212 JLINK_WriteReg(R9, 0x2000013C) returns 0x00 (0000ms, 36396ms total) +T3170 105:212 JLINK_WriteReg(R10, 0x00000000) returns 0x00 (0000ms, 36396ms total) +T3170 105:212 JLINK_WriteReg(R11, 0x00000000) returns 0x00 (0000ms, 36396ms total) +T3170 105:212 JLINK_WriteReg(R12, 0x00000000) returns 0x00 (0000ms, 36396ms total) +T3170 105:212 JLINK_WriteReg(R13 (SP), 0x20001000) returns 0x00 (0000ms, 36396ms total) +T3170 105:212 JLINK_WriteReg(R14, 0x20000001) returns 0x00 (0000ms, 36396ms total) +T3170 105:212 JLINK_WriteReg(R15 (PC), 0x20000104) returns 0x00 (0000ms, 36396ms total) +T3170 105:212 JLINK_WriteReg(XPSR, 0x01000000) returns 0x00 (0000ms, 36396ms total) +T3170 105:212 JLINK_WriteReg(MSP, 0x20001000) returns 0x00 (0000ms, 36396ms total) +T3170 105:212 JLINK_WriteReg(PSP, 0x20001000) returns 0x00 (0000ms, 36396ms total) +T3170 105:212 JLINK_WriteReg(CFBP, 0x00000000) returns 0x00 (0000ms, 36396ms total) +T3170 105:212 JLINK_SetBPEx(Addr = 0x20000000, Type = 0xFFFFFFF2) returns 0x000000CE (0000ms, 36396ms total) +T3170 105:212 JLINK_Go() -- CPU_ReadMem(4 bytes @ 0xE0001000) (0090ms, 36486ms total) +T3170 105:303 JLINK_IsHalted() -- CPU_ReadMem(2 bytes @ 0x20000000) returns TRUE (0006ms, 36492ms total) +T3170 105:309 JLINK_ReadReg(R15 (PC)) returns 0x20000000 (0000ms, 36486ms total) +T3170 105:309 JLINK_ClrBPEx(BPHandle = 0x000000CE) returns 0x00 (0000ms, 36486ms total) +T3170 105:309 JLINK_ReadReg(R0) returns 0x00000C80 (0000ms, 36486ms total) +T3170 105:309 JLINK_WriteMem(0x20000144, 0x0080 Bytes, ...) - Data: 10 B1 20 46 21 6A 88 47 81 E0 E0 69 00 B1 05 E0 ... -- CPU_WriteMem(128 bytes @ 0x20000144) returns 0x80 (0003ms, 36489ms total) +T3170 105:312 JLINK_WriteReg(R0, 0x00000C80) returns 0x00 (0000ms, 36489ms total) +T3170 105:312 JLINK_WriteReg(R1, 0x00000080) returns 0x00 (0000ms, 36489ms total) +T3170 105:312 JLINK_WriteReg(R2, 0x20000144) returns 0x00 (0000ms, 36489ms total) +T3170 105:312 JLINK_WriteReg(R3, 0x00000000) returns 0x00 (0000ms, 36489ms total) +T3170 105:312 JLINK_WriteReg(R4, 0x00000000) returns 0x00 (0000ms, 36489ms total) +T3170 105:312 JLINK_WriteReg(R5, 0x00000000) returns 0x00 (0000ms, 36489ms total) +T3170 105:312 JLINK_WriteReg(R6, 0x00000000) returns 0x00 (0000ms, 36489ms total) +T3170 105:312 JLINK_WriteReg(R7, 0x00000000) returns 0x00 (0000ms, 36489ms total) +T3170 105:312 JLINK_WriteReg(R8, 0x00000000) returns 0x00 (0000ms, 36489ms total) +T3170 105:312 JLINK_WriteReg(R9, 0x2000013C) returns 0x00 (0000ms, 36489ms total) +T3170 105:312 JLINK_WriteReg(R10, 0x00000000) returns 0x00 (0000ms, 36489ms total) +T3170 105:312 JLINK_WriteReg(R11, 0x00000000) returns 0x00 (0000ms, 36489ms total) +T3170 105:312 JLINK_WriteReg(R12, 0x00000000) returns 0x00 (0000ms, 36489ms total) +T3170 105:312 JLINK_WriteReg(R13 (SP), 0x20001000) returns 0x00 (0000ms, 36489ms total) +T3170 105:312 JLINK_WriteReg(R14, 0x20000001) returns 0x00 (0000ms, 36489ms total) +T3170 105:312 JLINK_WriteReg(R15 (PC), 0x20000104) returns 0x00 (0000ms, 36489ms total) +T3170 105:312 JLINK_WriteReg(XPSR, 0x01000000) returns 0x00 (0000ms, 36489ms total) +T3170 105:312 JLINK_WriteReg(MSP, 0x20001000) returns 0x00 (0000ms, 36489ms total) +T3170 105:312 JLINK_WriteReg(PSP, 0x20001000) returns 0x00 (0000ms, 36489ms total) +T3170 105:313 JLINK_WriteReg(CFBP, 0x00000000) returns 0x00 (0000ms, 36490ms total) +T3170 105:313 JLINK_SetBPEx(Addr = 0x20000000, Type = 0xFFFFFFF2) returns 0x000000CF (0000ms, 36490ms total) +T3170 105:313 JLINK_Go() -- CPU_ReadMem(4 bytes @ 0xE0001000) (0087ms, 36577ms total) +T3170 105:400 JLINK_IsHalted() -- CPU_ReadMem(2 bytes @ 0x20000000) returns TRUE (0009ms, 36586ms total) +T3170 105:409 JLINK_ReadReg(R15 (PC)) returns 0x20000000 (0000ms, 36577ms total) +T3170 105:409 JLINK_ClrBPEx(BPHandle = 0x000000CF) returns 0x00 (0000ms, 36577ms total) +T3170 105:409 JLINK_ReadReg(R0) returns 0x00000D00 (0000ms, 36577ms total) +T3170 105:409 JLINK_WriteMem(0x20000144, 0x0080 Bytes, ...) - Data: 88 47 21 68 01 F1 28 00 02 21 02 F0 51 FA 68 B1 ... -- CPU_WriteMem(128 bytes @ 0x20000144) returns 0x80 (0004ms, 36581ms total) +T3170 105:413 JLINK_WriteReg(R0, 0x00000D00) returns 0x00 (0000ms, 36581ms total) +T3170 105:413 JLINK_WriteReg(R1, 0x00000080) returns 0x00 (0000ms, 36581ms total) +T3170 105:413 JLINK_WriteReg(R2, 0x20000144) returns 0x00 (0000ms, 36581ms total) +T3170 105:413 JLINK_WriteReg(R3, 0x00000000) returns 0x00 (0000ms, 36581ms total) +T3170 105:413 JLINK_WriteReg(R4, 0x00000000) returns 0x00 (0000ms, 36581ms total) +T3170 105:413 JLINK_WriteReg(R5, 0x00000000) returns 0x00 (0000ms, 36581ms total) +T3170 105:413 JLINK_WriteReg(R6, 0x00000000) returns 0x00 (0001ms, 36582ms total) +T3170 105:414 JLINK_WriteReg(R7, 0x00000000) returns 0x00 (0000ms, 36582ms total) +T3170 105:414 JLINK_WriteReg(R8, 0x00000000) returns 0x00 (0000ms, 36582ms total) +T3170 105:414 JLINK_WriteReg(R9, 0x2000013C) returns 0x00 (0000ms, 36582ms total) +T3170 105:414 JLINK_WriteReg(R10, 0x00000000) returns 0x00 (0000ms, 36582ms total) +T3170 105:414 JLINK_WriteReg(R11, 0x00000000) returns 0x00 (0000ms, 36582ms total) +T3170 105:414 JLINK_WriteReg(R12, 0x00000000) returns 0x00 (0000ms, 36582ms total) +T3170 105:414 JLINK_WriteReg(R13 (SP), 0x20001000) returns 0x00 (0000ms, 36582ms total) +T3170 105:414 JLINK_WriteReg(R14, 0x20000001) returns 0x00 (0000ms, 36582ms total) +T3170 105:414 JLINK_WriteReg(R15 (PC), 0x20000104) returns 0x00 (0000ms, 36582ms total) +T3170 105:414 JLINK_WriteReg(XPSR, 0x01000000) returns 0x00 (0000ms, 36582ms total) +T3170 105:414 JLINK_WriteReg(MSP, 0x20001000) returns 0x00 (0000ms, 36582ms total) +T3170 105:414 JLINK_WriteReg(PSP, 0x20001000) returns 0x00 (0000ms, 36582ms total) +T3170 105:414 JLINK_WriteReg(CFBP, 0x00000000) returns 0x00 (0000ms, 36582ms total) +T3170 105:414 JLINK_SetBPEx(Addr = 0x20000000, Type = 0xFFFFFFF2) returns 0x000000D0 (0000ms, 36582ms total) +T3170 105:414 JLINK_Go() -- CPU_ReadMem(4 bytes @ 0xE0001000) (0088ms, 36670ms total) +T3170 105:502 JLINK_IsHalted() -- CPU_ReadMem(2 bytes @ 0x20000000) returns TRUE (0009ms, 36679ms total) +T3170 105:511 JLINK_ReadReg(R15 (PC)) returns 0x20000000 (0000ms, 36670ms total) +T3170 105:511 JLINK_ClrBPEx(BPHandle = 0x000000D0) returns 0x00 (0000ms, 36670ms total) +T3170 105:511 JLINK_ReadReg(R0) returns 0x00000D80 (0000ms, 36670ms total) +T3170 105:511 JLINK_WriteMem(0x20000144, 0x0080 Bytes, ...) - Data: 05 E0 40 F2 9F 62 05 A1 9E A0 FF F7 67 FB 00 BF ... -- CPU_WriteMem(128 bytes @ 0x20000144) returns 0x80 (0004ms, 36674ms total) +T3170 105:515 JLINK_WriteReg(R0, 0x00000D80) returns 0x00 (0000ms, 36674ms total) +T3170 105:515 JLINK_WriteReg(R1, 0x00000080) returns 0x00 (0000ms, 36674ms total) +T3170 105:515 JLINK_WriteReg(R2, 0x20000144) returns 0x00 (0000ms, 36674ms total) +T3170 105:515 JLINK_WriteReg(R3, 0x00000000) returns 0x00 (0000ms, 36674ms total) +T3170 105:515 JLINK_WriteReg(R4, 0x00000000) returns 0x00 (0000ms, 36674ms total) +T3170 105:515 JLINK_WriteReg(R5, 0x00000000) returns 0x00 (0000ms, 36674ms total) +T3170 105:515 JLINK_WriteReg(R6, 0x00000000) returns 0x00 (0001ms, 36675ms total) +T3170 105:516 JLINK_WriteReg(R7, 0x00000000) returns 0x00 (0000ms, 36675ms total) +T3170 105:516 JLINK_WriteReg(R8, 0x00000000) returns 0x00 (0000ms, 36675ms total) +T3170 105:516 JLINK_WriteReg(R9, 0x2000013C) returns 0x00 (0000ms, 36675ms total) +T3170 105:516 JLINK_WriteReg(R10, 0x00000000) returns 0x00 (0000ms, 36675ms total) +T3170 105:516 JLINK_WriteReg(R11, 0x00000000) returns 0x00 (0000ms, 36675ms total) +T3170 105:516 JLINK_WriteReg(R12, 0x00000000) returns 0x00 (0000ms, 36675ms total) +T3170 105:516 JLINK_WriteReg(R13 (SP), 0x20001000) returns 0x00 (0000ms, 36675ms total) +T3170 105:516 JLINK_WriteReg(R14, 0x20000001) returns 0x00 (0000ms, 36675ms total) +T3170 105:516 JLINK_WriteReg(R15 (PC), 0x20000104) returns 0x00 (0000ms, 36675ms total) +T3170 105:516 JLINK_WriteReg(XPSR, 0x01000000) returns 0x00 (0000ms, 36675ms total) +T3170 105:516 JLINK_WriteReg(MSP, 0x20001000) returns 0x00 (0000ms, 36675ms total) +T3170 105:516 JLINK_WriteReg(PSP, 0x20001000) returns 0x00 (0000ms, 36675ms total) +T3170 105:516 JLINK_WriteReg(CFBP, 0x00000000) returns 0x00 (0000ms, 36675ms total) +T3170 105:516 JLINK_SetBPEx(Addr = 0x20000000, Type = 0xFFFFFFF2) returns 0x000000D1 (0000ms, 36675ms total) +T3170 105:516 JLINK_Go() -- CPU_ReadMem(4 bytes @ 0xE0001000) (0089ms, 36764ms total) +T3170 105:605 JLINK_IsHalted() -- CPU_ReadMem(2 bytes @ 0x20000000) returns TRUE (0009ms, 36773ms total) +T3170 105:614 JLINK_ReadReg(R15 (PC)) returns 0x20000000 (0001ms, 36765ms total) +T3170 105:615 JLINK_ClrBPEx(BPHandle = 0x000000D1) returns 0x00 (0000ms, 36765ms total) +T3170 105:615 JLINK_ReadReg(R0) returns 0x00000E00 (0000ms, 36765ms total) +T3170 105:615 JLINK_WriteMem(0x20000144, 0x0080 Bytes, ...) - Data: 73 5F 75 61 72 74 5F 69 72 71 5F 68 61 6E 64 6C ... -- CPU_WriteMem(128 bytes @ 0x20000144) returns 0x80 (0019ms, 36784ms total) +T3170 105:634 JLINK_WriteReg(R0, 0x00000E00) returns 0x00 (0000ms, 36784ms total) +T3170 105:634 JLINK_WriteReg(R1, 0x00000080) returns 0x00 (0000ms, 36784ms total) +T3170 105:634 JLINK_WriteReg(R2, 0x20000144) returns 0x00 (0000ms, 36784ms total) +T3170 105:634 JLINK_WriteReg(R3, 0x00000000) returns 0x00 (0000ms, 36784ms total) +T3170 105:634 JLINK_WriteReg(R4, 0x00000000) returns 0x00 (0000ms, 36784ms total) +T3170 105:634 JLINK_WriteReg(R5, 0x00000000) returns 0x00 (0000ms, 36784ms total) +T3170 105:634 JLINK_WriteReg(R6, 0x00000000) returns 0x00 (0000ms, 36784ms total) +T3170 105:634 JLINK_WriteReg(R7, 0x00000000) returns 0x00 (0000ms, 36784ms total) +T3170 105:634 JLINK_WriteReg(R8, 0x00000000) returns 0x00 (0000ms, 36784ms total) +T3170 105:634 JLINK_WriteReg(R9, 0x2000013C) returns 0x00 (0000ms, 36784ms total) +T3170 105:634 JLINK_WriteReg(R10, 0x00000000) returns 0x00 (0000ms, 36784ms total) +T3170 105:634 JLINK_WriteReg(R11, 0x00000000) returns 0x00 (0000ms, 36784ms total) +T3170 105:634 JLINK_WriteReg(R12, 0x00000000) returns 0x00 (0000ms, 36784ms total) +T3170 105:634 JLINK_WriteReg(R13 (SP), 0x20001000) returns 0x00 (0000ms, 36784ms total) +T3170 105:634 JLINK_WriteReg(R14, 0x20000001) returns 0x00 (0000ms, 36784ms total) +T3170 105:634 JLINK_WriteReg(R15 (PC), 0x20000104) returns 0x00 (0000ms, 36784ms total) +T3170 105:634 JLINK_WriteReg(XPSR, 0x01000000) returns 0x00 (0000ms, 36784ms total) +T3170 105:634 JLINK_WriteReg(MSP, 0x20001000) returns 0x00 (0000ms, 36784ms total) +T3170 105:634 JLINK_WriteReg(PSP, 0x20001000) returns 0x00 (0000ms, 36784ms total) +T3170 105:634 JLINK_WriteReg(CFBP, 0x00000000) returns 0x00 (0000ms, 36784ms total) +T3170 105:634 JLINK_SetBPEx(Addr = 0x20000000, Type = 0xFFFFFFF2) returns 0x000000D2 (0000ms, 36784ms total) +T3170 105:634 JLINK_Go() -- CPU_ReadMem(4 bytes @ 0xE0001000) (0071ms, 36855ms total) +T3170 105:705 JLINK_IsHalted() -- CPU_ReadMem(2 bytes @ 0x20000000) returns TRUE (0008ms, 36863ms total) +T3170 105:713 JLINK_ReadReg(R15 (PC)) returns 0x20000000 (0000ms, 36855ms total) +T3170 105:713 JLINK_ClrBPEx(BPHandle = 0x000000D2) returns 0x00 (0000ms, 36855ms total) +T3170 105:713 JLINK_ReadReg(R0) returns 0x00000E80 (0000ms, 36855ms total) +T3170 105:713 JLINK_WriteMem(0x20000144, 0x0080 Bytes, ...) - Data: 61 6E 64 6C 65 72 5F 74 29 20 30 29 20 21 3D 20 ... -- CPU_WriteMem(128 bytes @ 0x20000144) returns 0x80 (0002ms, 36857ms total) +T3170 105:715 JLINK_WriteReg(R0, 0x00000E80) returns 0x00 (0000ms, 36857ms total) +T3170 105:715 JLINK_WriteReg(R1, 0x00000080) returns 0x00 (0000ms, 36857ms total) +T3170 105:715 JLINK_WriteReg(R2, 0x20000144) returns 0x00 (0000ms, 36857ms total) +T3170 105:715 JLINK_WriteReg(R3, 0x00000000) returns 0x00 (0000ms, 36857ms total) +T3170 105:715 JLINK_WriteReg(R4, 0x00000000) returns 0x00 (0001ms, 36858ms total) +T3170 105:716 JLINK_WriteReg(R5, 0x00000000) returns 0x00 (0000ms, 36858ms total) +T3170 105:716 JLINK_WriteReg(R6, 0x00000000) returns 0x00 (0000ms, 36858ms total) +T3170 105:716 JLINK_WriteReg(R7, 0x00000000) returns 0x00 (0000ms, 36858ms total) +T3170 105:716 JLINK_WriteReg(R8, 0x00000000) returns 0x00 (0000ms, 36858ms total) +T3170 105:716 JLINK_WriteReg(R9, 0x2000013C) returns 0x00 (0000ms, 36858ms total) +T3170 105:716 JLINK_WriteReg(R10, 0x00000000) returns 0x00 (0000ms, 36858ms total) +T3170 105:716 JLINK_WriteReg(R11, 0x00000000) returns 0x00 (0000ms, 36858ms total) +T3170 105:716 JLINK_WriteReg(R12, 0x00000000) returns 0x00 (0000ms, 36858ms total) +T3170 105:716 JLINK_WriteReg(R13 (SP), 0x20001000) returns 0x00 (0000ms, 36858ms total) +T3170 105:716 JLINK_WriteReg(R14, 0x20000001) returns 0x00 (0000ms, 36858ms total) +T3170 105:716 JLINK_WriteReg(R15 (PC), 0x20000104) returns 0x00 (0000ms, 36858ms total) +T3170 105:716 JLINK_WriteReg(XPSR, 0x01000000) returns 0x00 (0000ms, 36858ms total) +T3170 105:716 JLINK_WriteReg(MSP, 0x20001000) returns 0x00 (0000ms, 36858ms total) +T3170 105:716 JLINK_WriteReg(PSP, 0x20001000) returns 0x00 (0000ms, 36858ms total) +T3170 105:716 JLINK_WriteReg(CFBP, 0x00000000) returns 0x00 (0000ms, 36858ms total) +T3170 105:716 JLINK_SetBPEx(Addr = 0x20000000, Type = 0xFFFFFFF2) returns 0x000000D3 (0000ms, 36858ms total) +T3170 105:716 JLINK_Go() -- CPU_ReadMem(4 bytes @ 0xE0001000) (0090ms, 36948ms total) +T3170 105:806 JLINK_IsHalted() -- CPU_ReadMem(2 bytes @ 0x20000000) returns TRUE (0028ms, 36976ms total) +T3170 105:900 JLINK_ReadReg(R15 (PC)) returns 0x20000000 (0001ms, 36949ms total) +T3170 105:901 JLINK_ClrBPEx(BPHandle = 0x000000D3) returns 0x00 (0000ms, 36949ms total) +T3170 105:901 JLINK_ReadReg(R0) returns 0x00000F00 (0000ms, 36949ms total) +T3170 105:901 JLINK_WriteMem(0x20000144, 0x0080 Bytes, ...) - Data: 20 21 3D 20 74 68 69 73 5F 75 61 72 74 2D 3E 72 ... -- CPU_WriteMem(128 bytes @ 0x20000144) returns 0x80 (0004ms, 36953ms total) +T3170 105:905 JLINK_WriteReg(R0, 0x00000F00) returns 0x00 (0000ms, 36953ms total) +T3170 105:905 JLINK_WriteReg(R1, 0x00000080) returns 0x00 (0000ms, 36953ms total) +T3170 105:905 JLINK_WriteReg(R2, 0x20000144) returns 0x00 (0000ms, 36953ms total) +T3170 105:905 JLINK_WriteReg(R3, 0x00000000) returns 0x00 (0000ms, 36953ms total) +T3170 105:905 JLINK_WriteReg(R4, 0x00000000) returns 0x00 (0000ms, 36953ms total) +T3170 105:905 JLINK_WriteReg(R5, 0x00000000) returns 0x00 (0000ms, 36953ms total) +T3170 105:905 JLINK_WriteReg(R6, 0x00000000) returns 0x00 (0000ms, 36953ms total) +T3170 105:905 JLINK_WriteReg(R7, 0x00000000) returns 0x00 (0000ms, 36953ms total) +T3170 105:905 JLINK_WriteReg(R8, 0x00000000) returns 0x00 (0000ms, 36953ms total) +T3170 105:905 JLINK_WriteReg(R9, 0x2000013C) returns 0x00 (0000ms, 36953ms total) +T3170 105:905 JLINK_WriteReg(R10, 0x00000000) returns 0x00 (0000ms, 36953ms total) +T3170 105:905 JLINK_WriteReg(R11, 0x00000000) returns 0x00 (0000ms, 36953ms total) +T3170 105:905 JLINK_WriteReg(R12, 0x00000000) returns 0x00 (0000ms, 36953ms total) +T3170 105:905 JLINK_WriteReg(R13 (SP), 0x20001000) returns 0x00 (0000ms, 36953ms total) +T3170 105:905 JLINK_WriteReg(R14, 0x20000001) returns 0x00 (0000ms, 36953ms total) +T3170 105:905 JLINK_WriteReg(R15 (PC), 0x20000104) returns 0x00 (0000ms, 36953ms total) +T3170 105:905 JLINK_WriteReg(XPSR, 0x01000000) returns 0x00 (0000ms, 36953ms total) +T3170 105:905 JLINK_WriteReg(MSP, 0x20001000) returns 0x00 (0000ms, 36953ms total) +T3170 105:905 JLINK_WriteReg(PSP, 0x20001000) returns 0x00 (0000ms, 36953ms total) +T3170 105:905 JLINK_WriteReg(CFBP, 0x00000000) returns 0x00 (0000ms, 36953ms total) +T3170 105:905 JLINK_SetBPEx(Addr = 0x20000000, Type = 0xFFFFFFF2) returns 0x000000D4 (0000ms, 36953ms total) +T3170 105:905 JLINK_Go() -- CPU_ReadMem(4 bytes @ 0xE0001000) (0006ms, 36959ms total) +T3170 105:911 JLINK_IsHalted() -- CPU_ReadMem(2 bytes @ 0x20000000) returns TRUE (0089ms, 37048ms total) +T3170 106:000 JLINK_ReadReg(R15 (PC)) returns 0x20000000 (0000ms, 36959ms total) +T3170 106:000 JLINK_ClrBPEx(BPHandle = 0x000000D4) returns 0x00 (0000ms, 36959ms total) +T3170 106:000 JLINK_ReadReg(R0) returns 0x00000F80 (0000ms, 36959ms total) +T3170 106:000 JLINK_WriteMem(0x20000144, 0x0080 Bytes, ...) - Data: 69 64 5F 70 65 69 5F 68 61 6E 64 6C 65 72 00 00 ... -- CPU_WriteMem(128 bytes @ 0x20000144) returns 0x80 (0004ms, 36963ms total) +T3170 106:004 JLINK_WriteReg(R0, 0x00000F80) returns 0x00 (0000ms, 36963ms total) +T3170 106:004 JLINK_WriteReg(R1, 0x00000080) returns 0x00 (0000ms, 36963ms total) +T3170 106:004 JLINK_WriteReg(R2, 0x20000144) returns 0x00 (0000ms, 36963ms total) +T3170 106:004 JLINK_WriteReg(R3, 0x00000000) returns 0x00 (0000ms, 36963ms total) +T3170 106:004 JLINK_WriteReg(R4, 0x00000000) returns 0x00 (0000ms, 36963ms total) +T3170 106:004 JLINK_WriteReg(R5, 0x00000000) returns 0x00 (0000ms, 36963ms total) +T3170 106:004 JLINK_WriteReg(R6, 0x00000000) returns 0x00 (0000ms, 36963ms total) +T3170 106:004 JLINK_WriteReg(R7, 0x00000000) returns 0x00 (0000ms, 36963ms total) +T3170 106:004 JLINK_WriteReg(R8, 0x00000000) returns 0x00 (0000ms, 36963ms total) +T3170 106:004 JLINK_WriteReg(R9, 0x2000013C) returns 0x00 (0000ms, 36963ms total) +T3170 106:004 JLINK_WriteReg(R10, 0x00000000) returns 0x00 (0000ms, 36963ms total) +T3170 106:004 JLINK_WriteReg(R11, 0x00000000) returns 0x00 (0000ms, 36963ms total) +T3170 106:004 JLINK_WriteReg(R12, 0x00000000) returns 0x00 (0000ms, 36963ms total) +T3170 106:004 JLINK_WriteReg(R13 (SP), 0x20001000) returns 0x00 (0000ms, 36963ms total) +T3170 106:004 JLINK_WriteReg(R14, 0x20000001) returns 0x00 (0000ms, 36963ms total) +T3170 106:004 JLINK_WriteReg(R15 (PC), 0x20000104) returns 0x00 (0000ms, 36963ms total) +T3170 106:004 JLINK_WriteReg(XPSR, 0x01000000) returns 0x00 (0000ms, 36963ms total) +T3170 106:004 JLINK_WriteReg(MSP, 0x20001000) returns 0x00 (0000ms, 36963ms total) +T3170 106:004 JLINK_WriteReg(PSP, 0x20001000) returns 0x00 (0000ms, 36963ms total) +T3170 106:004 JLINK_WriteReg(CFBP, 0x00000000) returns 0x00 (0000ms, 36963ms total) +T3170 106:004 JLINK_SetBPEx(Addr = 0x20000000, Type = 0xFFFFFFF2) returns 0x000000D5 (0000ms, 36963ms total) +T3170 106:004 JLINK_Go() -- CPU_ReadMem(4 bytes @ 0xE0001000) (0007ms, 36970ms total) +T3170 106:011 JLINK_IsHalted() -- CPU_ReadMem(2 bytes @ 0x20000000) returns TRUE (0085ms, 37055ms total) +T3170 106:096 JLINK_ReadReg(R15 (PC)) returns 0x20000000 (0000ms, 36970ms total) +T3170 106:096 JLINK_ClrBPEx(BPHandle = 0x000000D5) returns 0x00 (0000ms, 36970ms total) +T3170 106:096 JLINK_ReadReg(R0) returns 0x00001000 (0000ms, 36970ms total) +T3170 106:096 JLINK_WriteMem(0x20000144, 0x0080 Bytes, ...) - Data: 6C 65 72 00 30 75 00 00 02 46 00 BF 06 4B 1B 68 ... -- CPU_WriteMem(128 bytes @ 0x20000144) returns 0x80 (0006ms, 36976ms total) +T3170 106:102 JLINK_WriteReg(R0, 0x00001000) returns 0x00 (0000ms, 36976ms total) +T3170 106:102 JLINK_WriteReg(R1, 0x00000080) returns 0x00 (0000ms, 36976ms total) +T3170 106:102 JLINK_WriteReg(R2, 0x20000144) returns 0x00 (0000ms, 36976ms total) +T3170 106:102 JLINK_WriteReg(R3, 0x00000000) returns 0x00 (0000ms, 36976ms total) +T3170 106:102 JLINK_WriteReg(R4, 0x00000000) returns 0x00 (0000ms, 36976ms total) +T3170 106:102 JLINK_WriteReg(R5, 0x00000000) returns 0x00 (0000ms, 36976ms total) +T3170 106:102 JLINK_WriteReg(R6, 0x00000000) returns 0x00 (0000ms, 36976ms total) +T3170 106:102 JLINK_WriteReg(R7, 0x00000000) returns 0x00 (0000ms, 36976ms total) +T3170 106:102 JLINK_WriteReg(R8, 0x00000000) returns 0x00 (0000ms, 36976ms total) +T3170 106:102 JLINK_WriteReg(R9, 0x2000013C) returns 0x00 (0000ms, 36976ms total) +T3170 106:102 JLINK_WriteReg(R10, 0x00000000) returns 0x00 (0000ms, 36976ms total) +T3170 106:102 JLINK_WriteReg(R11, 0x00000000) returns 0x00 (0000ms, 36976ms total) +T3170 106:102 JLINK_WriteReg(R12, 0x00000000) returns 0x00 (0000ms, 36976ms total) +T3170 106:102 JLINK_WriteReg(R13 (SP), 0x20001000) returns 0x00 (0000ms, 36976ms total) +T3170 106:102 JLINK_WriteReg(R14, 0x20000001) returns 0x00 (0000ms, 36976ms total) +T3170 106:102 JLINK_WriteReg(R15 (PC), 0x20000104) returns 0x00 (0000ms, 36976ms total) +T3170 106:102 JLINK_WriteReg(XPSR, 0x01000000) returns 0x00 (0000ms, 36976ms total) +T3170 106:102 JLINK_WriteReg(MSP, 0x20001000) returns 0x00 (0000ms, 36976ms total) +T3170 106:102 JLINK_WriteReg(PSP, 0x20001000) returns 0x00 (0000ms, 36976ms total) +T3170 106:102 JLINK_WriteReg(CFBP, 0x00000000) returns 0x00 (0000ms, 36976ms total) +T3170 106:102 JLINK_SetBPEx(Addr = 0x20000000, Type = 0xFFFFFFF2) returns 0x000000D6 (0000ms, 36976ms total) +T3170 106:102 JLINK_Go() -- CPU_ReadMem(4 bytes @ 0xE0001000) (0007ms, 36983ms total) +T3170 106:109 JLINK_IsHalted() -- CPU_ReadMem(2 bytes @ 0x20000000) returns TRUE (0091ms, 37074ms total) +T3170 106:200 JLINK_ReadReg(R15 (PC)) returns 0x20000000 (0000ms, 36983ms total) +T3170 106:200 JLINK_ClrBPEx(BPHandle = 0x000000D6) returns 0x00 (0000ms, 36983ms total) +T3170 106:200 JLINK_ReadReg(R0) returns 0x00001080 (0001ms, 36984ms total) +T3170 106:201 JLINK_WriteMem(0x20000144, 0x0080 Bytes, ...) - Data: 69 62 72 61 72 69 65 73 5C 6D 73 73 5F 75 61 72 ... -- CPU_WriteMem(128 bytes @ 0x20000144) returns 0x80 (0003ms, 36987ms total) +T3170 106:204 JLINK_WriteReg(R0, 0x00001080) returns 0x00 (0000ms, 36987ms total) +T3170 106:204 JLINK_WriteReg(R1, 0x00000080) returns 0x00 (0000ms, 36987ms total) +T3170 106:204 JLINK_WriteReg(R2, 0x20000144) returns 0x00 (0001ms, 36988ms total) +T3170 106:205 JLINK_WriteReg(R3, 0x00000000) returns 0x00 (0000ms, 36988ms total) +T3170 106:205 JLINK_WriteReg(R4, 0x00000000) returns 0x00 (0000ms, 36988ms total) +T3170 106:205 JLINK_WriteReg(R5, 0x00000000) returns 0x00 (0000ms, 36988ms total) +T3170 106:205 JLINK_WriteReg(R6, 0x00000000) returns 0x00 (0000ms, 36988ms total) +T3170 106:205 JLINK_WriteReg(R7, 0x00000000) returns 0x00 (0000ms, 36988ms total) +T3170 106:205 JLINK_WriteReg(R8, 0x00000000) returns 0x00 (0000ms, 36988ms total) +T3170 106:205 JLINK_WriteReg(R9, 0x2000013C) returns 0x00 (0000ms, 36988ms total) +T3170 106:205 JLINK_WriteReg(R10, 0x00000000) returns 0x00 (0000ms, 36988ms total) +T3170 106:205 JLINK_WriteReg(R11, 0x00000000) returns 0x00 (0000ms, 36988ms total) +T3170 106:205 JLINK_WriteReg(R12, 0x00000000) returns 0x00 (0000ms, 36988ms total) +T3170 106:205 JLINK_WriteReg(R13 (SP), 0x20001000) returns 0x00 (0000ms, 36988ms total) +T3170 106:205 JLINK_WriteReg(R14, 0x20000001) returns 0x00 (0000ms, 36988ms total) +T3170 106:205 JLINK_WriteReg(R15 (PC), 0x20000104) returns 0x00 (0000ms, 36988ms total) +T3170 106:205 JLINK_WriteReg(XPSR, 0x01000000) returns 0x00 (0000ms, 36988ms total) +T3170 106:205 JLINK_WriteReg(MSP, 0x20001000) returns 0x00 (0000ms, 36988ms total) +T3170 106:205 JLINK_WriteReg(PSP, 0x20001000) returns 0x00 (0000ms, 36988ms total) +T3170 106:205 JLINK_WriteReg(CFBP, 0x00000000) returns 0x00 (0000ms, 36988ms total) +T3170 106:205 JLINK_SetBPEx(Addr = 0x20000000, Type = 0xFFFFFFF2) returns 0x000000D7 (0000ms, 36988ms total) +T3170 106:205 JLINK_Go() -- CPU_ReadMem(4 bytes @ 0xE0001000) (0008ms, 36996ms total) +T3170 106:213 JLINK_IsHalted() -- CPU_ReadMem(2 bytes @ 0x20000000) returns TRUE (0091ms, 37087ms total) +T3170 106:304 JLINK_ReadReg(R15 (PC)) returns 0x20000000 (0000ms, 36996ms total) +T3170 106:307 JLINK_ClrBPEx(BPHandle = 0x000000D7) returns 0x00 (0000ms, 36996ms total) +T3170 106:307 JLINK_ReadReg(R0) returns 0x00001100 (0000ms, 36996ms total) +T3170 106:307 JLINK_WriteMem(0x20000144, 0x0080 Bytes, ...) - Data: D7 FA 10 BD 2D E9 FC 41 27 48 00 68 00 F0 80 64 ... -- CPU_WriteMem(128 bytes @ 0x20000144) returns 0x80 (0004ms, 37000ms total) +T3170 106:311 JLINK_WriteReg(R0, 0x00001100) returns 0x00 (0000ms, 37000ms total) +T3170 106:311 JLINK_WriteReg(R1, 0x00000080) returns 0x00 (0000ms, 37000ms total) +T3170 106:311 JLINK_WriteReg(R2, 0x20000144) returns 0x00 (0000ms, 37000ms total) +T3170 106:311 JLINK_WriteReg(R3, 0x00000000) returns 0x00 (0000ms, 37000ms total) +T3170 106:311 JLINK_WriteReg(R4, 0x00000000) returns 0x00 (0000ms, 37000ms total) +T3170 106:311 JLINK_WriteReg(R5, 0x00000000) returns 0x00 (0000ms, 37000ms total) +T3170 106:311 JLINK_WriteReg(R6, 0x00000000) returns 0x00 (0000ms, 37000ms total) +T3170 106:311 JLINK_WriteReg(R7, 0x00000000) returns 0x00 (0000ms, 37000ms total) +T3170 106:311 JLINK_WriteReg(R8, 0x00000000) returns 0x00 (0000ms, 37000ms total) +T3170 106:311 JLINK_WriteReg(R9, 0x2000013C) returns 0x00 (0000ms, 37000ms total) +T3170 106:311 JLINK_WriteReg(R10, 0x00000000) returns 0x00 (0000ms, 37000ms total) +T3170 106:311 JLINK_WriteReg(R11, 0x00000000) returns 0x00 (0000ms, 37000ms total) +T3170 106:311 JLINK_WriteReg(R12, 0x00000000) returns 0x00 (0000ms, 37000ms total) +T3170 106:311 JLINK_WriteReg(R13 (SP), 0x20001000) returns 0x00 (0000ms, 37000ms total) +T3170 106:311 JLINK_WriteReg(R14, 0x20000001) returns 0x00 (0000ms, 37000ms total) +T3170 106:311 JLINK_WriteReg(R15 (PC), 0x20000104) returns 0x00 (0000ms, 37000ms total) +T3170 106:311 JLINK_WriteReg(XPSR, 0x01000000) returns 0x00 (0001ms, 37001ms total) +T3170 106:312 JLINK_WriteReg(MSP, 0x20001000) returns 0x00 (0000ms, 37001ms total) +T3170 106:312 JLINK_WriteReg(PSP, 0x20001000) returns 0x00 (0000ms, 37001ms total) +T3170 106:312 JLINK_WriteReg(CFBP, 0x00000000) returns 0x00 (0000ms, 37001ms total) +T3170 106:312 JLINK_SetBPEx(Addr = 0x20000000, Type = 0xFFFFFFF2) returns 0x000000D8 (0000ms, 37001ms total) +T3170 106:312 JLINK_Go() -- CPU_ReadMem(4 bytes @ 0xE0001000) (0088ms, 37089ms total) +T3170 106:400 JLINK_IsHalted() -- CPU_ReadMem(2 bytes @ 0x20000000) returns TRUE (0007ms, 37096ms total) +T3170 106:407 JLINK_ReadReg(R15 (PC)) returns 0x20000000 (0001ms, 37090ms total) +T3170 106:408 JLINK_ClrBPEx(BPHandle = 0x000000D8) returns 0x00 (0000ms, 37090ms total) +T3170 106:408 JLINK_ReadReg(R0) returns 0x00001180 (0000ms, 37090ms total) +T3170 106:408 JLINK_WriteMem(0x20000144, 0x0080 Bytes, ...) - Data: 14 48 03 F0 71 FC 04 E0 00 BF 12 48 03 F0 6C FC ... -- CPU_WriteMem(128 bytes @ 0x20000144) returns 0x80 (0003ms, 37093ms total) +T3170 106:411 JLINK_WriteReg(R0, 0x00001180) returns 0x00 (0000ms, 37093ms total) +T3170 106:411 JLINK_WriteReg(R1, 0x00000080) returns 0x00 (0000ms, 37093ms total) +T3170 106:411 JLINK_WriteReg(R2, 0x20000144) returns 0x00 (0000ms, 37093ms total) +T3170 106:411 JLINK_WriteReg(R3, 0x00000000) returns 0x00 (0000ms, 37093ms total) +T3170 106:411 JLINK_WriteReg(R4, 0x00000000) returns 0x00 (0000ms, 37093ms total) +T3170 106:411 JLINK_WriteReg(R5, 0x00000000) returns 0x00 (0000ms, 37093ms total) +T3170 106:411 JLINK_WriteReg(R6, 0x00000000) returns 0x00 (0000ms, 37093ms total) +T3170 106:411 JLINK_WriteReg(R7, 0x00000000) returns 0x00 (0000ms, 37093ms total) +T3170 106:411 JLINK_WriteReg(R8, 0x00000000) returns 0x00 (0000ms, 37093ms total) +T3170 106:411 JLINK_WriteReg(R9, 0x2000013C) returns 0x00 (0000ms, 37093ms total) +T3170 106:411 JLINK_WriteReg(R10, 0x00000000) returns 0x00 (0000ms, 37093ms total) +T3170 106:411 JLINK_WriteReg(R11, 0x00000000) returns 0x00 (0000ms, 37093ms total) +T3170 106:411 JLINK_WriteReg(R12, 0x00000000) returns 0x00 (0000ms, 37093ms total) +T3170 106:411 JLINK_WriteReg(R13 (SP), 0x20001000) returns 0x00 (0000ms, 37093ms total) +T3170 106:411 JLINK_WriteReg(R14, 0x20000001) returns 0x00 (0000ms, 37093ms total) +T3170 106:411 JLINK_WriteReg(R15 (PC), 0x20000104) returns 0x00 (0000ms, 37093ms total) +T3170 106:411 JLINK_WriteReg(XPSR, 0x01000000) returns 0x00 (0000ms, 37093ms total) +T3170 106:411 JLINK_WriteReg(MSP, 0x20001000) returns 0x00 (0000ms, 37093ms total) +T3170 106:411 JLINK_WriteReg(PSP, 0x20001000) returns 0x00 (0000ms, 37093ms total) +T3170 106:411 JLINK_WriteReg(CFBP, 0x00000000) returns 0x00 (0000ms, 37093ms total) +T3170 106:411 JLINK_SetBPEx(Addr = 0x20000000, Type = 0xFFFFFFF2) returns 0x000000D9 (0000ms, 37093ms total) +T3170 106:411 JLINK_Go() -- CPU_ReadMem(4 bytes @ 0xE0001000) (0089ms, 37182ms total) +T3170 106:500 JLINK_IsHalted() -- CPU_ReadMem(2 bytes @ 0x20000000) returns TRUE (0010ms, 37192ms total) +T3170 106:511 JLINK_ReadReg(R15 (PC)) returns 0x20000000 (0000ms, 37182ms total) +T3170 106:511 JLINK_ClrBPEx(BPHandle = 0x000000D9) returns 0x00 (0000ms, 37182ms total) +T3170 106:511 JLINK_ReadReg(R0) returns 0x00001200 (0000ms, 37182ms total) +T3170 106:511 JLINK_WriteMem(0x20000144, 0x0080 Bytes, ...) - Data: F8 10 00 20 10 B5 02 48 FF F7 EA FC 10 BD 00 00 ... -- CPU_WriteMem(128 bytes @ 0x20000144) returns 0x80 (0004ms, 37186ms total) +T3170 106:515 JLINK_WriteReg(R0, 0x00001200) returns 0x00 (0000ms, 37186ms total) +T3170 106:515 JLINK_WriteReg(R1, 0x00000080) returns 0x00 (0000ms, 37186ms total) +T3170 106:515 JLINK_WriteReg(R2, 0x20000144) returns 0x00 (0000ms, 37186ms total) +T3170 106:515 JLINK_WriteReg(R3, 0x00000000) returns 0x00 (0000ms, 37186ms total) +T3170 106:515 JLINK_WriteReg(R4, 0x00000000) returns 0x00 (0000ms, 37186ms total) +T3170 106:515 JLINK_WriteReg(R5, 0x00000000) returns 0x00 (0000ms, 37186ms total) +T3170 106:515 JLINK_WriteReg(R6, 0x00000000) returns 0x00 (0000ms, 37186ms total) +T3170 106:515 JLINK_WriteReg(R7, 0x00000000) returns 0x00 (0000ms, 37186ms total) +T3170 106:515 JLINK_WriteReg(R8, 0x00000000) returns 0x00 (0000ms, 37186ms total) +T3170 106:515 JLINK_WriteReg(R9, 0x2000013C) returns 0x00 (0000ms, 37186ms total) +T3170 106:515 JLINK_WriteReg(R10, 0x00000000) returns 0x00 (0000ms, 37186ms total) +T3170 106:515 JLINK_WriteReg(R11, 0x00000000) returns 0x00 (0000ms, 37186ms total) +T3170 106:515 JLINK_WriteReg(R12, 0x00000000) returns 0x00 (0000ms, 37186ms total) +T3170 106:515 JLINK_WriteReg(R13 (SP), 0x20001000) returns 0x00 (0000ms, 37186ms total) +T3170 106:515 JLINK_WriteReg(R14, 0x20000001) returns 0x00 (0000ms, 37186ms total) +T3170 106:515 JLINK_WriteReg(R15 (PC), 0x20000104) returns 0x00 (0000ms, 37186ms total) +T3170 106:515 JLINK_WriteReg(XPSR, 0x01000000) returns 0x00 (0000ms, 37186ms total) +T3170 106:515 JLINK_WriteReg(MSP, 0x20001000) returns 0x00 (0000ms, 37186ms total) +T3170 106:515 JLINK_WriteReg(PSP, 0x20001000) returns 0x00 (0000ms, 37186ms total) +T3170 106:515 JLINK_WriteReg(CFBP, 0x00000000) returns 0x00 (0000ms, 37186ms total) +T3170 106:515 JLINK_SetBPEx(Addr = 0x20000000, Type = 0xFFFFFFF2) returns 0x000000DA (0000ms, 37186ms total) +T3170 106:515 JLINK_Go() -- CPU_ReadMem(4 bytes @ 0xE0001000) (0090ms, 37276ms total) +T3170 106:605 JLINK_IsHalted() -- CPU_ReadMem(2 bytes @ 0x20000000) returns TRUE (0009ms, 37285ms total) +T3170 106:614 JLINK_ReadReg(R15 (PC)) returns 0x20000000 (0000ms, 37276ms total) +T3170 106:614 JLINK_ClrBPEx(BPHandle = 0x000000DA) returns 0x00 (0000ms, 37276ms total) +T3170 106:614 JLINK_ReadReg(R0) returns 0x00001280 (0000ms, 37276ms total) +T3170 106:614 JLINK_WriteMem(0x20000144, 0x0080 Bytes, ...) - Data: 00 EB 11 60 00 78 19 30 DF E7 00 00 24 4D 00 00 ... -- CPU_WriteMem(128 bytes @ 0x20000144) returns 0x80 (0087ms, 37363ms total) +T3170 106:701 JLINK_WriteReg(R0, 0x00001280) returns 0x00 (0000ms, 37363ms total) +T3170 106:701 JLINK_WriteReg(R1, 0x00000080) returns 0x00 (0000ms, 37363ms total) +T3170 106:701 JLINK_WriteReg(R2, 0x20000144) returns 0x00 (0000ms, 37363ms total) +T3170 106:701 JLINK_WriteReg(R3, 0x00000000) returns 0x00 (0001ms, 37364ms total) +T3170 106:702 JLINK_WriteReg(R4, 0x00000000) returns 0x00 (0000ms, 37364ms total) +T3170 106:702 JLINK_WriteReg(R5, 0x00000000) returns 0x00 (0000ms, 37364ms total) +T3170 106:702 JLINK_WriteReg(R6, 0x00000000) returns 0x00 (0000ms, 37364ms total) +T3170 106:702 JLINK_WriteReg(R7, 0x00000000) returns 0x00 (0000ms, 37364ms total) +T3170 106:702 JLINK_WriteReg(R8, 0x00000000) returns 0x00 (0000ms, 37364ms total) +T3170 106:702 JLINK_WriteReg(R9, 0x2000013C) returns 0x00 (0000ms, 37364ms total) +T3170 106:702 JLINK_WriteReg(R10, 0x00000000) returns 0x00 (0000ms, 37364ms total) +T3170 106:702 JLINK_WriteReg(R11, 0x00000000) returns 0x00 (0000ms, 37364ms total) +T3170 106:702 JLINK_WriteReg(R12, 0x00000000) returns 0x00 (0000ms, 37364ms total) +T3170 106:702 JLINK_WriteReg(R13 (SP), 0x20001000) returns 0x00 (0000ms, 37364ms total) +T3170 106:702 JLINK_WriteReg(R14, 0x20000001) returns 0x00 (0000ms, 37364ms total) +T3170 106:702 JLINK_WriteReg(R15 (PC), 0x20000104) returns 0x00 (0000ms, 37364ms total) +T3170 106:702 JLINK_WriteReg(XPSR, 0x01000000) returns 0x00 (0000ms, 37364ms total) +T3170 106:702 JLINK_WriteReg(MSP, 0x20001000) returns 0x00 (0000ms, 37364ms total) +T3170 106:702 JLINK_WriteReg(PSP, 0x20001000) returns 0x00 (0000ms, 37364ms total) +T3170 106:702 JLINK_WriteReg(CFBP, 0x00000000) returns 0x00 (0000ms, 37364ms total) +T3170 106:702 JLINK_SetBPEx(Addr = 0x20000000, Type = 0xFFFFFFF2) returns 0x000000DB (0000ms, 37364ms total) +T3170 106:702 JLINK_Go() -- CPU_ReadMem(4 bytes @ 0xE0001000) (0007ms, 37371ms total) +T3170 106:709 JLINK_IsHalted() -- CPU_ReadMem(2 bytes @ 0x20000000) returns TRUE (0008ms, 37379ms total) +T3170 106:717 JLINK_ReadReg(R15 (PC)) returns 0x20000000 (0000ms, 37371ms total) +T3170 106:717 JLINK_ClrBPEx(BPHandle = 0x000000DB) returns 0x00 (0000ms, 37371ms total) +T3170 106:717 JLINK_ReadReg(R0) returns 0x00001300 (0000ms, 37371ms total) +T3170 106:717 JLINK_WriteMem(0x20000144, 0x0080 Bytes, ...) - Data: 5F FD 05 46 15 B9 4F F0 FF 30 F3 E7 20 21 01 A8 ... -- CPU_WriteMem(128 bytes @ 0x20000144) returns 0x80 (0085ms, 37456ms total) +T3170 106:802 JLINK_WriteReg(R0, 0x00001300) returns 0x00 (0000ms, 37456ms total) +T3170 106:802 JLINK_WriteReg(R1, 0x00000080) returns 0x00 (0000ms, 37456ms total) +T3170 106:802 JLINK_WriteReg(R2, 0x20000144) returns 0x00 (0000ms, 37456ms total) +T3170 106:802 JLINK_WriteReg(R3, 0x00000000) returns 0x00 (0000ms, 37456ms total) +T3170 106:802 JLINK_WriteReg(R4, 0x00000000) returns 0x00 (0000ms, 37456ms total) +T3170 106:803 JLINK_WriteReg(R5, 0x00000000) returns 0x00 (0000ms, 37456ms total) +T3170 106:803 JLINK_WriteReg(R6, 0x00000000) returns 0x00 (0000ms, 37456ms total) +T3170 106:803 JLINK_WriteReg(R7, 0x00000000) returns 0x00 (0000ms, 37456ms total) +T3170 106:803 JLINK_WriteReg(R8, 0x00000000) returns 0x00 (0000ms, 37456ms total) +T3170 106:803 JLINK_WriteReg(R9, 0x2000013C) returns 0x00 (0000ms, 37456ms total) +T3170 106:803 JLINK_WriteReg(R10, 0x00000000) returns 0x00 (0000ms, 37456ms total) +T3170 106:803 JLINK_WriteReg(R11, 0x00000000) returns 0x00 (0000ms, 37456ms total) +T3170 106:803 JLINK_WriteReg(R12, 0x00000000) returns 0x00 (0000ms, 37456ms total) +T3170 106:803 JLINK_WriteReg(R13 (SP), 0x20001000) returns 0x00 (0000ms, 37456ms total) +T3170 106:803 JLINK_WriteReg(R14, 0x20000001) returns 0x00 (0000ms, 37456ms total) +T3170 106:803 JLINK_WriteReg(R15 (PC), 0x20000104) returns 0x00 (0000ms, 37456ms total) +T3170 106:803 JLINK_WriteReg(XPSR, 0x01000000) returns 0x00 (0000ms, 37456ms total) +T3170 106:803 JLINK_WriteReg(MSP, 0x20001000) returns 0x00 (0000ms, 37456ms total) +T3170 106:803 JLINK_WriteReg(PSP, 0x20001000) returns 0x00 (0000ms, 37456ms total) +T3170 106:803 JLINK_WriteReg(CFBP, 0x00000000) returns 0x00 (0000ms, 37456ms total) +T3170 106:803 JLINK_SetBPEx(Addr = 0x20000000, Type = 0xFFFFFFF2) returns 0x000000DC (0000ms, 37456ms total) +T3170 106:803 JLINK_Go() -- CPU_ReadMem(4 bytes @ 0xE0001000) (0008ms, 37464ms total) +T3170 106:811 JLINK_IsHalted() -- CPU_ReadMem(2 bytes @ 0x20000000) returns TRUE (0090ms, 37554ms total) +T3170 106:901 JLINK_ReadReg(R15 (PC)) returns 0x20000000 (0000ms, 37464ms total) +T3170 106:901 JLINK_ClrBPEx(BPHandle = 0x000000DC) returns 0x00 (0000ms, 37464ms total) +T3170 106:901 JLINK_ReadReg(R0) returns 0x00001380 (0000ms, 37464ms total) +T3170 106:901 JLINK_WriteMem(0x20000144, 0x0080 Bytes, ...) - Data: 20 60 A7 76 67 76 00 20 E0 61 C4 F8 28 80 C4 F8 ... -- CPU_WriteMem(128 bytes @ 0x20000144) returns 0x80 (0004ms, 37468ms total) +T3170 106:905 JLINK_WriteReg(R0, 0x00001380) returns 0x00 (0000ms, 37468ms total) +T3170 106:905 JLINK_WriteReg(R1, 0x00000080) returns 0x00 (0000ms, 37468ms total) +T3170 106:905 JLINK_WriteReg(R2, 0x20000144) returns 0x00 (0000ms, 37468ms total) +T3170 106:905 JLINK_WriteReg(R3, 0x00000000) returns 0x00 (0000ms, 37468ms total) +T3170 106:905 JLINK_WriteReg(R4, 0x00000000) returns 0x00 (0000ms, 37468ms total) +T3170 106:905 JLINK_WriteReg(R5, 0x00000000) returns 0x00 (0000ms, 37468ms total) +T3170 106:905 JLINK_WriteReg(R6, 0x00000000) returns 0x00 (0000ms, 37468ms total) +T3170 106:905 JLINK_WriteReg(R7, 0x00000000) returns 0x00 (0000ms, 37468ms total) +T3170 106:905 JLINK_WriteReg(R8, 0x00000000) returns 0x00 (0000ms, 37468ms total) +T3170 106:905 JLINK_WriteReg(R9, 0x2000013C) returns 0x00 (0000ms, 37468ms total) +T3170 106:905 JLINK_WriteReg(R10, 0x00000000) returns 0x00 (0000ms, 37468ms total) +T3170 106:905 JLINK_WriteReg(R11, 0x00000000) returns 0x00 (0000ms, 37468ms total) +T3170 106:905 JLINK_WriteReg(R12, 0x00000000) returns 0x00 (0000ms, 37468ms total) +T3170 106:905 JLINK_WriteReg(R13 (SP), 0x20001000) returns 0x00 (0000ms, 37468ms total) +T3170 106:905 JLINK_WriteReg(R14, 0x20000001) returns 0x00 (0000ms, 37468ms total) +T3170 106:905 JLINK_WriteReg(R15 (PC), 0x20000104) returns 0x00 (0000ms, 37468ms total) +T3170 106:905 JLINK_WriteReg(XPSR, 0x01000000) returns 0x00 (0000ms, 37468ms total) +T3170 106:905 JLINK_WriteReg(MSP, 0x20001000) returns 0x00 (0000ms, 37468ms total) +T3170 106:905 JLINK_WriteReg(PSP, 0x20001000) returns 0x00 (0000ms, 37468ms total) +T3170 106:905 JLINK_WriteReg(CFBP, 0x00000000) returns 0x00 (0000ms, 37468ms total) +T3170 106:905 JLINK_SetBPEx(Addr = 0x20000000, Type = 0xFFFFFFF2) returns 0x000000DD (0000ms, 37468ms total) +T3170 106:905 JLINK_Go() -- CPU_ReadMem(4 bytes @ 0xE0001000) (0007ms, 37475ms total) +T3170 106:912 JLINK_IsHalted() -- CPU_ReadMem(2 bytes @ 0x20000000) returns TRUE (0015ms, 37490ms total) +T3170 106:927 JLINK_ReadReg(R15 (PC)) returns 0x20000000 (0000ms, 37475ms total) +T3170 106:927 JLINK_ClrBPEx(BPHandle = 0x000000DD) returns 0x00 (0000ms, 37475ms total) +T3170 106:927 JLINK_ReadReg(R0) returns 0x00001400 (0000ms, 37475ms total) +T3170 106:927 JLINK_WriteMem(0x20000144, 0x0080 Bytes, ...) - Data: 02 46 00 20 01 46 0E E0 02 F1 14 03 03 EB C1 00 ... -- CPU_WriteMem(128 bytes @ 0x20000144) returns 0x80 (0074ms, 37549ms total) +T3170 107:002 JLINK_WriteReg(R0, 0x00001400) returns 0x00 (0000ms, 37549ms total) +T3170 107:002 JLINK_WriteReg(R1, 0x00000080) returns 0x00 (0000ms, 37549ms total) +T3170 107:002 JLINK_WriteReg(R2, 0x20000144) returns 0x00 (0000ms, 37549ms total) +T3170 107:002 JLINK_WriteReg(R3, 0x00000000) returns 0x00 (0000ms, 37549ms total) +T3170 107:002 JLINK_WriteReg(R4, 0x00000000) returns 0x00 (0000ms, 37549ms total) +T3170 107:002 JLINK_WriteReg(R5, 0x00000000) returns 0x00 (0000ms, 37549ms total) +T3170 107:002 JLINK_WriteReg(R6, 0x00000000) returns 0x00 (0000ms, 37549ms total) +T3170 107:002 JLINK_WriteReg(R7, 0x00000000) returns 0x00 (0000ms, 37549ms total) +T3170 107:002 JLINK_WriteReg(R8, 0x00000000) returns 0x00 (0000ms, 37549ms total) +T3170 107:002 JLINK_WriteReg(R9, 0x2000013C) returns 0x00 (0000ms, 37549ms total) +T3170 107:002 JLINK_WriteReg(R10, 0x00000000) returns 0x00 (0000ms, 37549ms total) +T3170 107:002 JLINK_WriteReg(R11, 0x00000000) returns 0x00 (0000ms, 37549ms total) +T3170 107:002 JLINK_WriteReg(R12, 0x00000000) returns 0x00 (0000ms, 37549ms total) +T3170 107:002 JLINK_WriteReg(R13 (SP), 0x20001000) returns 0x00 (0000ms, 37549ms total) +T3170 107:002 JLINK_WriteReg(R14, 0x20000001) returns 0x00 (0000ms, 37549ms total) +T3170 107:002 JLINK_WriteReg(R15 (PC), 0x20000104) returns 0x00 (0000ms, 37549ms total) +T3170 107:002 JLINK_WriteReg(XPSR, 0x01000000) returns 0x00 (0000ms, 37549ms total) +T3170 107:002 JLINK_WriteReg(MSP, 0x20001000) returns 0x00 (0000ms, 37549ms total) +T3170 107:002 JLINK_WriteReg(PSP, 0x20001000) returns 0x00 (0000ms, 37549ms total) +T3170 107:002 JLINK_WriteReg(CFBP, 0x00000000) returns 0x00 (0000ms, 37549ms total) +T3170 107:002 JLINK_SetBPEx(Addr = 0x20000000, Type = 0xFFFFFFF2) returns 0x000000DE (0000ms, 37549ms total) +T3170 107:002 JLINK_Go() -- CPU_ReadMem(4 bytes @ 0xE0001000) (0008ms, 37557ms total) +T3170 107:010 JLINK_IsHalted() -- CPU_ReadMem(2 bytes @ 0x20000000) returns TRUE (0090ms, 37647ms total) +T3170 107:100 JLINK_ReadReg(R15 (PC)) returns 0x20000000 (0000ms, 37557ms total) +T3170 107:100 JLINK_ClrBPEx(BPHandle = 0x000000DE) returns 0x00 (0000ms, 37557ms total) +T3170 107:100 JLINK_ReadReg(R0) returns 0x00001480 (0000ms, 37557ms total) +T3170 107:100 JLINK_WriteMem(0x20000144, 0x0080 Bytes, ...) - Data: 02 00 10 B1 22 A0 02 F0 6B F9 17 48 00 78 00 F0 ... -- CPU_WriteMem(128 bytes @ 0x20000144) returns 0x80 (0004ms, 37561ms total) +T3170 107:104 JLINK_WriteReg(R0, 0x00001480) returns 0x00 (0000ms, 37561ms total) +T3170 107:104 JLINK_WriteReg(R1, 0x00000080) returns 0x00 (0000ms, 37561ms total) +T3170 107:104 JLINK_WriteReg(R2, 0x20000144) returns 0x00 (0000ms, 37561ms total) +T3170 107:104 JLINK_WriteReg(R3, 0x00000000) returns 0x00 (0000ms, 37561ms total) +T3170 107:104 JLINK_WriteReg(R4, 0x00000000) returns 0x00 (0000ms, 37561ms total) +T3170 107:104 JLINK_WriteReg(R5, 0x00000000) returns 0x00 (0000ms, 37561ms total) +T3170 107:104 JLINK_WriteReg(R6, 0x00000000) returns 0x00 (0000ms, 37561ms total) +T3170 107:104 JLINK_WriteReg(R7, 0x00000000) returns 0x00 (0000ms, 37561ms total) +T3170 107:104 JLINK_WriteReg(R8, 0x00000000) returns 0x00 (0000ms, 37561ms total) +T3170 107:104 JLINK_WriteReg(R9, 0x2000013C) returns 0x00 (0000ms, 37561ms total) +T3170 107:104 JLINK_WriteReg(R10, 0x00000000) returns 0x00 (0000ms, 37561ms total) +T3170 107:104 JLINK_WriteReg(R11, 0x00000000) returns 0x00 (0000ms, 37561ms total) +T3170 107:104 JLINK_WriteReg(R12, 0x00000000) returns 0x00 (0000ms, 37561ms total) +T3170 107:104 JLINK_WriteReg(R13 (SP), 0x20001000) returns 0x00 (0000ms, 37561ms total) +T3170 107:104 JLINK_WriteReg(R14, 0x20000001) returns 0x00 (0000ms, 37561ms total) +T3170 107:104 JLINK_WriteReg(R15 (PC), 0x20000104) returns 0x00 (0000ms, 37561ms total) +T3170 107:104 JLINK_WriteReg(XPSR, 0x01000000) returns 0x00 (0000ms, 37561ms total) +T3170 107:104 JLINK_WriteReg(MSP, 0x20001000) returns 0x00 (0000ms, 37561ms total) +T3170 107:104 JLINK_WriteReg(PSP, 0x20001000) returns 0x00 (0000ms, 37561ms total) +T3170 107:104 JLINK_WriteReg(CFBP, 0x00000000) returns 0x00 (0000ms, 37561ms total) +T3170 107:104 JLINK_SetBPEx(Addr = 0x20000000, Type = 0xFFFFFFF2) returns 0x000000DF (0000ms, 37561ms total) +T3170 107:104 JLINK_Go() -- CPU_ReadMem(4 bytes @ 0xE0001000) (0007ms, 37568ms total) +T3170 107:111 JLINK_IsHalted() -- CPU_ReadMem(2 bytes @ 0x20000000) returns TRUE (0051ms, 37619ms total) +T3170 107:162 JLINK_ReadReg(R15 (PC)) returns 0x20000000 (0000ms, 37568ms total) +T3170 107:162 JLINK_ClrBPEx(BPHandle = 0x000000DF) returns 0x00 (0000ms, 37568ms total) +T3170 107:162 JLINK_ReadReg(R0) returns 0x00001500 (0000ms, 37568ms total) +T3170 107:162 JLINK_WriteMem(0x20000144, 0x0080 Bytes, ...) - Data: 20 00 00 00 49 42 55 53 45 52 52 20 00 00 00 00 ... -- CPU_WriteMem(128 bytes @ 0x20000144) returns 0x80 (0040ms, 37608ms total) +T3170 107:202 JLINK_WriteReg(R0, 0x00001500) returns 0x00 (0000ms, 37608ms total) +T3170 107:202 JLINK_WriteReg(R1, 0x00000080) returns 0x00 (0000ms, 37608ms total) +T3170 107:202 JLINK_WriteReg(R2, 0x20000144) returns 0x00 (0000ms, 37608ms total) +T3170 107:202 JLINK_WriteReg(R3, 0x00000000) returns 0x00 (0001ms, 37609ms total) +T3170 107:203 JLINK_WriteReg(R4, 0x00000000) returns 0x00 (0000ms, 37609ms total) +T3170 107:203 JLINK_WriteReg(R5, 0x00000000) returns 0x00 (0000ms, 37609ms total) +T3170 107:203 JLINK_WriteReg(R6, 0x00000000) returns 0x00 (0000ms, 37609ms total) +T3170 107:203 JLINK_WriteReg(R7, 0x00000000) returns 0x00 (0000ms, 37609ms total) +T3170 107:203 JLINK_WriteReg(R8, 0x00000000) returns 0x00 (0000ms, 37609ms total) +T3170 107:203 JLINK_WriteReg(R9, 0x2000013C) returns 0x00 (0000ms, 37609ms total) +T3170 107:203 JLINK_WriteReg(R10, 0x00000000) returns 0x00 (0000ms, 37609ms total) +T3170 107:203 JLINK_WriteReg(R11, 0x00000000) returns 0x00 (0000ms, 37609ms total) +T3170 107:203 JLINK_WriteReg(R12, 0x00000000) returns 0x00 (0000ms, 37609ms total) +T3170 107:203 JLINK_WriteReg(R13 (SP), 0x20001000) returns 0x00 (0000ms, 37609ms total) +T3170 107:203 JLINK_WriteReg(R14, 0x20000001) returns 0x00 (0000ms, 37609ms total) +T3170 107:203 JLINK_WriteReg(R15 (PC), 0x20000104) returns 0x00 (0000ms, 37609ms total) +T3170 107:203 JLINK_WriteReg(XPSR, 0x01000000) returns 0x00 (0000ms, 37609ms total) +T3170 107:203 JLINK_WriteReg(MSP, 0x20001000) returns 0x00 (0000ms, 37609ms total) +T3170 107:203 JLINK_WriteReg(PSP, 0x20001000) returns 0x00 (0000ms, 37609ms total) +T3170 107:203 JLINK_WriteReg(CFBP, 0x00000000) returns 0x00 (0000ms, 37609ms total) +T3170 107:203 JLINK_SetBPEx(Addr = 0x20000000, Type = 0xFFFFFFF2) returns 0x000000E0 (0000ms, 37609ms total) +T3170 107:203 JLINK_Go() -- CPU_ReadMem(4 bytes @ 0xE0001000) (0007ms, 37616ms total) +T3170 107:210 JLINK_IsHalted() -- CPU_ReadMem(2 bytes @ 0x20000000) returns TRUE (0006ms, 37622ms total) +T3170 107:216 JLINK_ReadReg(R15 (PC)) returns 0x20000000 (0000ms, 37616ms total) +T3170 107:216 JLINK_ClrBPEx(BPHandle = 0x000000E0) returns 0x00 (0000ms, 37616ms total) +T3170 107:216 JLINK_ReadReg(R0) returns 0x00001580 (0000ms, 37616ms total) +T3170 107:216 JLINK_WriteMem(0x20000144, 0x0080 Bytes, ...) - Data: 10 BD 70 B5 04 46 0D 46 00 F0 44 FF 00 20 70 BD ... -- CPU_WriteMem(128 bytes @ 0x20000144) returns 0x80 (0085ms, 37701ms total) +T3170 107:301 JLINK_WriteReg(R0, 0x00001580) returns 0x00 (0000ms, 37701ms total) +T3170 107:301 JLINK_WriteReg(R1, 0x00000080) returns 0x00 (0000ms, 37701ms total) +T3170 107:301 JLINK_WriteReg(R2, 0x20000144) returns 0x00 (0000ms, 37701ms total) +T3170 107:301 JLINK_WriteReg(R3, 0x00000000) returns 0x00 (0000ms, 37701ms total) +T3170 107:301 JLINK_WriteReg(R4, 0x00000000) returns 0x00 (0000ms, 37701ms total) +T3170 107:301 JLINK_WriteReg(R5, 0x00000000) returns 0x00 (0000ms, 37701ms total) +T3170 107:301 JLINK_WriteReg(R6, 0x00000000) returns 0x00 (0000ms, 37701ms total) +T3170 107:301 JLINK_WriteReg(R7, 0x00000000) returns 0x00 (0000ms, 37701ms total) +T3170 107:301 JLINK_WriteReg(R8, 0x00000000) returns 0x00 (0000ms, 37701ms total) +T3170 107:301 JLINK_WriteReg(R9, 0x2000013C) returns 0x00 (0000ms, 37701ms total) +T3170 107:301 JLINK_WriteReg(R10, 0x00000000) returns 0x00 (0000ms, 37701ms total) +T3170 107:301 JLINK_WriteReg(R11, 0x00000000) returns 0x00 (0000ms, 37701ms total) +T3170 107:302 JLINK_WriteReg(R12, 0x00000000) returns 0x00 (0000ms, 37702ms total) +T3170 107:302 JLINK_WriteReg(R13 (SP), 0x20001000) returns 0x00 (0000ms, 37702ms total) +T3170 107:302 JLINK_WriteReg(R14, 0x20000001) returns 0x00 (0000ms, 37702ms total) +T3170 107:302 JLINK_WriteReg(R15 (PC), 0x20000104) returns 0x00 (0000ms, 37702ms total) +T3170 107:302 JLINK_WriteReg(XPSR, 0x01000000) returns 0x00 (0000ms, 37702ms total) +T3170 107:302 JLINK_WriteReg(MSP, 0x20001000) returns 0x00 (0000ms, 37702ms total) +T3170 107:302 JLINK_WriteReg(PSP, 0x20001000) returns 0x00 (0000ms, 37702ms total) +T3170 107:302 JLINK_WriteReg(CFBP, 0x00000000) returns 0x00 (0000ms, 37702ms total) +T3170 107:302 JLINK_SetBPEx(Addr = 0x20000000, Type = 0xFFFFFFF2) returns 0x000000E1 (0000ms, 37702ms total) +T3170 107:302 JLINK_Go() -- CPU_ReadMem(4 bytes @ 0xE0001000) (0007ms, 37709ms total) +T3170 107:309 JLINK_IsHalted() -- CPU_ReadMem(2 bytes @ 0x20000000) returns TRUE (0088ms, 37797ms total) +T3170 107:397 JLINK_ReadReg(R15 (PC)) returns 0x20000000 (0000ms, 37709ms total) +T3170 107:397 JLINK_ClrBPEx(BPHandle = 0x000000E1) returns 0x00 (0000ms, 37709ms total) +T3170 107:397 JLINK_ReadReg(R0) returns 0x00001600 (0000ms, 37709ms total) +T3170 107:397 JLINK_WriteMem(0x20000144, 0x0080 Bytes, ...) - Data: A0 EB 46 00 06 44 B5 F5 80 3F 00 D2 05 E0 40 F2 ... -- CPU_WriteMem(128 bytes @ 0x20000144) returns 0x80 (0005ms, 37714ms total) +T3170 107:402 JLINK_WriteReg(R0, 0x00001600) returns 0x00 (0000ms, 37714ms total) +T3170 107:402 JLINK_WriteReg(R1, 0x00000080) returns 0x00 (0000ms, 37714ms total) +T3170 107:402 JLINK_WriteReg(R2, 0x20000144) returns 0x00 (0000ms, 37714ms total) +T3170 107:402 JLINK_WriteReg(R3, 0x00000000) returns 0x00 (0000ms, 37714ms total) +T3170 107:402 JLINK_WriteReg(R4, 0x00000000) returns 0x00 (0000ms, 37714ms total) +T3170 107:402 JLINK_WriteReg(R5, 0x00000000) returns 0x00 (0000ms, 37714ms total) +T3170 107:402 JLINK_WriteReg(R6, 0x00000000) returns 0x00 (0000ms, 37714ms total) +T3170 107:402 JLINK_WriteReg(R7, 0x00000000) returns 0x00 (0000ms, 37714ms total) +T3170 107:402 JLINK_WriteReg(R8, 0x00000000) returns 0x00 (0000ms, 37714ms total) +T3170 107:402 JLINK_WriteReg(R9, 0x2000013C) returns 0x00 (0000ms, 37714ms total) +T3170 107:402 JLINK_WriteReg(R10, 0x00000000) returns 0x00 (0000ms, 37714ms total) +T3170 107:402 JLINK_WriteReg(R11, 0x00000000) returns 0x00 (0000ms, 37714ms total) +T3170 107:402 JLINK_WriteReg(R12, 0x00000000) returns 0x00 (0000ms, 37714ms total) +T3170 107:402 JLINK_WriteReg(R13 (SP), 0x20001000) returns 0x00 (0000ms, 37714ms total) +T3170 107:402 JLINK_WriteReg(R14, 0x20000001) returns 0x00 (0000ms, 37714ms total) +T3170 107:402 JLINK_WriteReg(R15 (PC), 0x20000104) returns 0x00 (0000ms, 37714ms total) +T3170 107:402 JLINK_WriteReg(XPSR, 0x01000000) returns 0x00 (0000ms, 37714ms total) +T3170 107:402 JLINK_WriteReg(MSP, 0x20001000) returns 0x00 (0000ms, 37714ms total) +T3170 107:402 JLINK_WriteReg(PSP, 0x20001000) returns 0x00 (0000ms, 37714ms total) +T3170 107:402 JLINK_WriteReg(CFBP, 0x00000000) returns 0x00 (0000ms, 37714ms total) +T3170 107:402 JLINK_SetBPEx(Addr = 0x20000000, Type = 0xFFFFFFF2) returns 0x000000E2 (0000ms, 37714ms total) +T3170 107:402 JLINK_Go() -- CPU_ReadMem(4 bytes @ 0xE0001000) (0007ms, 37721ms total) +T3170 107:409 JLINK_IsHalted() -- CPU_ReadMem(2 bytes @ 0x20000000) returns TRUE (0091ms, 37812ms total) +T3170 107:500 JLINK_ReadReg(R15 (PC)) returns 0x20000000 (0000ms, 37721ms total) +T3170 107:503 JLINK_ClrBPEx(BPHandle = 0x000000E2) returns 0x00 (0000ms, 37721ms total) +T3170 107:503 JLINK_ReadReg(R0) returns 0x00001680 (0000ms, 37721ms total) +T3170 107:503 JLINK_WriteMem(0x20000144, 0x0080 Bytes, ...) - Data: 0D 70 21 68 01 F1 0C 00 07 21 FF F7 6D FF 21 68 ... -- CPU_WriteMem(128 bytes @ 0x20000144) returns 0x80 (0004ms, 37725ms total) +T3170 107:507 JLINK_WriteReg(R0, 0x00001680) returns 0x00 (0000ms, 37725ms total) +T3170 107:507 JLINK_WriteReg(R1, 0x00000080) returns 0x00 (0000ms, 37725ms total) +T3170 107:507 JLINK_WriteReg(R2, 0x20000144) returns 0x00 (0001ms, 37726ms total) +T3170 107:508 JLINK_WriteReg(R3, 0x00000000) returns 0x00 (0000ms, 37726ms total) +T3170 107:508 JLINK_WriteReg(R4, 0x00000000) returns 0x00 (0000ms, 37726ms total) +T3170 107:508 JLINK_WriteReg(R5, 0x00000000) returns 0x00 (0000ms, 37726ms total) +T3170 107:508 JLINK_WriteReg(R6, 0x00000000) returns 0x00 (0000ms, 37726ms total) +T3170 107:508 JLINK_WriteReg(R7, 0x00000000) returns 0x00 (0000ms, 37726ms total) +T3170 107:508 JLINK_WriteReg(R8, 0x00000000) returns 0x00 (0000ms, 37726ms total) +T3170 107:508 JLINK_WriteReg(R9, 0x2000013C) returns 0x00 (0000ms, 37726ms total) +T3170 107:508 JLINK_WriteReg(R10, 0x00000000) returns 0x00 (0000ms, 37726ms total) +T3170 107:508 JLINK_WriteReg(R11, 0x00000000) returns 0x00 (0000ms, 37726ms total) +T3170 107:508 JLINK_WriteReg(R12, 0x00000000) returns 0x00 (0000ms, 37726ms total) +T3170 107:508 JLINK_WriteReg(R13 (SP), 0x20001000) returns 0x00 (0000ms, 37726ms total) +T3170 107:508 JLINK_WriteReg(R14, 0x20000001) returns 0x00 (0000ms, 37726ms total) +T3170 107:508 JLINK_WriteReg(R15 (PC), 0x20000104) returns 0x00 (0000ms, 37726ms total) +T3170 107:508 JLINK_WriteReg(XPSR, 0x01000000) returns 0x00 (0000ms, 37726ms total) +T3170 107:508 JLINK_WriteReg(MSP, 0x20001000) returns 0x00 (0000ms, 37726ms total) +T3170 107:508 JLINK_WriteReg(PSP, 0x20001000) returns 0x00 (0000ms, 37726ms total) +T3170 107:508 JLINK_WriteReg(CFBP, 0x00000000) returns 0x00 (0000ms, 37726ms total) +T3170 107:508 JLINK_SetBPEx(Addr = 0x20000000, Type = 0xFFFFFFF2) returns 0x000000E3 (0000ms, 37726ms total) +T3170 107:508 JLINK_Go() -- CPU_ReadMem(4 bytes @ 0xE0001000) (0008ms, 37734ms total) +T3170 107:516 JLINK_IsHalted() -- CPU_ReadMem(2 bytes @ 0x20000000) returns TRUE (0091ms, 37825ms total) +T3170 107:607 JLINK_ReadReg(R15 (PC)) returns 0x20000000 (0000ms, 37734ms total) +T3170 107:607 JLINK_ClrBPEx(BPHandle = 0x000000E3) returns 0x00 (0000ms, 37734ms total) +T3170 107:607 JLINK_ReadReg(R0) returns 0x00001700 (0000ms, 37734ms total) +T3170 107:607 JLINK_WriteMem(0x20000144, 0x0080 Bytes, ...) - Data: 75 61 72 74 31 29 00 00 04 00 00 20 08 00 00 20 ... -- CPU_WriteMem(128 bytes @ 0x20000144) returns 0x80 (0004ms, 37738ms total) +T3170 107:611 JLINK_WriteReg(R0, 0x00001700) returns 0x00 (0000ms, 37738ms total) +T3170 107:611 JLINK_WriteReg(R1, 0x00000080) returns 0x00 (0000ms, 37738ms total) +T3170 107:611 JLINK_WriteReg(R2, 0x20000144) returns 0x00 (0000ms, 37738ms total) +T3170 107:611 JLINK_WriteReg(R3, 0x00000000) returns 0x00 (0000ms, 37738ms total) +T3170 107:611 JLINK_WriteReg(R4, 0x00000000) returns 0x00 (0000ms, 37738ms total) +T3170 107:611 JLINK_WriteReg(R5, 0x00000000) returns 0x00 (0000ms, 37738ms total) +T3170 107:611 JLINK_WriteReg(R6, 0x00000000) returns 0x00 (0000ms, 37738ms total) +T3170 107:611 JLINK_WriteReg(R7, 0x00000000) returns 0x00 (0000ms, 37738ms total) +T3170 107:611 JLINK_WriteReg(R8, 0x00000000) returns 0x00 (0000ms, 37738ms total) +T3170 107:611 JLINK_WriteReg(R9, 0x2000013C) returns 0x00 (0000ms, 37738ms total) +T3170 107:611 JLINK_WriteReg(R10, 0x00000000) returns 0x00 (0000ms, 37738ms total) +T3170 107:611 JLINK_WriteReg(R11, 0x00000000) returns 0x00 (0000ms, 37738ms total) +T3170 107:611 JLINK_WriteReg(R12, 0x00000000) returns 0x00 (0000ms, 37738ms total) +T3170 107:611 JLINK_WriteReg(R13 (SP), 0x20001000) returns 0x00 (0000ms, 37738ms total) +T3170 107:611 JLINK_WriteReg(R14, 0x20000001) returns 0x00 (0000ms, 37738ms total) +T3170 107:611 JLINK_WriteReg(R15 (PC), 0x20000104) returns 0x00 (0000ms, 37738ms total) +T3170 107:611 JLINK_WriteReg(XPSR, 0x01000000) returns 0x00 (0001ms, 37739ms total) +T3170 107:612 JLINK_WriteReg(MSP, 0x20001000) returns 0x00 (0000ms, 37739ms total) +T3170 107:612 JLINK_WriteReg(PSP, 0x20001000) returns 0x00 (0000ms, 37739ms total) +T3170 107:612 JLINK_WriteReg(CFBP, 0x00000000) returns 0x00 (0000ms, 37739ms total) +T3170 107:612 JLINK_SetBPEx(Addr = 0x20000000, Type = 0xFFFFFFF2) returns 0x000000E4 (0000ms, 37739ms total) +T3170 107:612 JLINK_Go() -- CPU_ReadMem(4 bytes @ 0xE0001000) (0088ms, 37827ms total) +T3170 107:700 JLINK_IsHalted() -- CPU_ReadMem(2 bytes @ 0x20000000) returns TRUE (0011ms, 37838ms total) +T3170 107:711 JLINK_ReadReg(R15 (PC)) returns 0x20000000 (0000ms, 37827ms total) +T3170 107:711 JLINK_ClrBPEx(BPHandle = 0x000000E4) returns 0x00 (0000ms, 37827ms total) +T3170 107:711 JLINK_ReadReg(R0) returns 0x00001780 (0000ms, 37827ms total) +T3170 107:711 JLINK_WriteMem(0x20000144, 0x0080 Bytes, ...) - Data: 00 D9 05 E0 40 F2 B3 62 1D A1 40 A0 FE F7 66 FE ... -- CPU_WriteMem(128 bytes @ 0x20000144) returns 0x80 (0004ms, 37831ms total) +T3170 107:715 JLINK_WriteReg(R0, 0x00001780) returns 0x00 (0000ms, 37831ms total) +T3170 107:715 JLINK_WriteReg(R1, 0x00000080) returns 0x00 (0000ms, 37831ms total) +T3170 107:715 JLINK_WriteReg(R2, 0x20000144) returns 0x00 (0000ms, 37831ms total) +T3170 107:715 JLINK_WriteReg(R3, 0x00000000) returns 0x00 (0000ms, 37831ms total) +T3170 107:715 JLINK_WriteReg(R4, 0x00000000) returns 0x00 (0000ms, 37831ms total) +T3170 107:715 JLINK_WriteReg(R5, 0x00000000) returns 0x00 (0000ms, 37831ms total) +T3170 107:715 JLINK_WriteReg(R6, 0x00000000) returns 0x00 (0000ms, 37831ms total) +T3170 107:715 JLINK_WriteReg(R7, 0x00000000) returns 0x00 (0000ms, 37831ms total) +T3170 107:715 JLINK_WriteReg(R8, 0x00000000) returns 0x00 (0000ms, 37831ms total) +T3170 107:715 JLINK_WriteReg(R9, 0x2000013C) returns 0x00 (0000ms, 37831ms total) +T3170 107:715 JLINK_WriteReg(R10, 0x00000000) returns 0x00 (0000ms, 37831ms total) +T3170 107:715 JLINK_WriteReg(R11, 0x00000000) returns 0x00 (0000ms, 37831ms total) +T3170 107:715 JLINK_WriteReg(R12, 0x00000000) returns 0x00 (0000ms, 37831ms total) +T3170 107:715 JLINK_WriteReg(R13 (SP), 0x20001000) returns 0x00 (0000ms, 37831ms total) +T3170 107:715 JLINK_WriteReg(R14, 0x20000001) returns 0x00 (0000ms, 37831ms total) +T3170 107:715 JLINK_WriteReg(R15 (PC), 0x20000104) returns 0x00 (0000ms, 37831ms total) +T3170 107:715 JLINK_WriteReg(XPSR, 0x01000000) returns 0x00 (0000ms, 37831ms total) +T3170 107:715 JLINK_WriteReg(MSP, 0x20001000) returns 0x00 (0000ms, 37831ms total) +T3170 107:715 JLINK_WriteReg(PSP, 0x20001000) returns 0x00 (0000ms, 37831ms total) +T3170 107:715 JLINK_WriteReg(CFBP, 0x00000000) returns 0x00 (0000ms, 37831ms total) +T3170 107:715 JLINK_SetBPEx(Addr = 0x20000000, Type = 0xFFFFFFF2) returns 0x000000E5 (0000ms, 37831ms total) +T3170 107:715 JLINK_Go() -- CPU_ReadMem(4 bytes @ 0xE0001000) (0089ms, 37920ms total) +T3170 107:804 JLINK_IsHalted() -- CPU_ReadMem(2 bytes @ 0x20000000) returns TRUE (0011ms, 37931ms total) +T3170 107:815 JLINK_ReadReg(R15 (PC)) returns 0x20000000 (0000ms, 37920ms total) +T3170 107:815 JLINK_ClrBPEx(BPHandle = 0x000000E5) returns 0x00 (0000ms, 37920ms total) +T3170 107:815 JLINK_ReadReg(R0) returns 0x00001800 (0000ms, 37920ms total) +T3170 107:815 JLINK_WriteMem(0x20000144, 0x0080 Bytes, ...) - Data: 2E 2E 5C 6C 69 62 72 61 72 69 65 73 5C 6D 73 73 ... -- CPU_WriteMem(128 bytes @ 0x20000144) returns 0x80 (0086ms, 38006ms total) +T3170 107:901 JLINK_WriteReg(R0, 0x00001800) returns 0x00 (0000ms, 38006ms total) +T3170 107:901 JLINK_WriteReg(R1, 0x00000080) returns 0x00 (0000ms, 38006ms total) +T3170 107:901 JLINK_WriteReg(R2, 0x20000144) returns 0x00 (0000ms, 38006ms total) +T3170 107:901 JLINK_WriteReg(R3, 0x00000000) returns 0x00 (0000ms, 38006ms total) +T3170 107:901 JLINK_WriteReg(R4, 0x00000000) returns 0x00 (0000ms, 38006ms total) +T3170 107:901 JLINK_WriteReg(R5, 0x00000000) returns 0x00 (0000ms, 38006ms total) +T3170 107:901 JLINK_WriteReg(R6, 0x00000000) returns 0x00 (0000ms, 38006ms total) +T3170 107:901 JLINK_WriteReg(R7, 0x00000000) returns 0x00 (0000ms, 38006ms total) +T3170 107:901 JLINK_WriteReg(R8, 0x00000000) returns 0x00 (0000ms, 38006ms total) +T3170 107:901 JLINK_WriteReg(R9, 0x2000013C) returns 0x00 (0000ms, 38006ms total) +T3170 107:901 JLINK_WriteReg(R10, 0x00000000) returns 0x00 (0000ms, 38006ms total) +T3170 107:901 JLINK_WriteReg(R11, 0x00000000) returns 0x00 (0000ms, 38006ms total) +T3170 107:901 JLINK_WriteReg(R12, 0x00000000) returns 0x00 (0000ms, 38006ms total) +T3170 107:901 JLINK_WriteReg(R13 (SP), 0x20001000) returns 0x00 (0000ms, 38006ms total) +T3170 107:901 JLINK_WriteReg(R14, 0x20000001) returns 0x00 (0000ms, 38006ms total) +T3170 107:901 JLINK_WriteReg(R15 (PC), 0x20000104) returns 0x00 (0000ms, 38006ms total) +T3170 107:901 JLINK_WriteReg(XPSR, 0x01000000) returns 0x00 (0001ms, 38007ms total) +T3170 107:902 JLINK_WriteReg(MSP, 0x20001000) returns 0x00 (0000ms, 38007ms total) +T3170 107:902 JLINK_WriteReg(PSP, 0x20001000) returns 0x00 (0000ms, 38007ms total) +T3170 107:902 JLINK_WriteReg(CFBP, 0x00000000) returns 0x00 (0000ms, 38007ms total) +T3170 107:902 JLINK_SetBPEx(Addr = 0x20000000, Type = 0xFFFFFFF2) returns 0x000000E6 (0000ms, 38007ms total) +T3170 107:902 JLINK_Go() -- CPU_ReadMem(4 bytes @ 0xE0001000) (0007ms, 38014ms total) +T3170 107:909 JLINK_IsHalted() -- CPU_ReadMem(2 bytes @ 0x20000000) returns TRUE (0045ms, 38059ms total) +T3170 107:954 JLINK_ReadReg(R15 (PC)) returns 0x20000000 (0000ms, 38014ms total) +T3170 107:954 JLINK_ClrBPEx(BPHandle = 0x000000E6) returns 0x00 (0000ms, 38014ms total) +T3170 107:954 JLINK_ReadReg(R0) returns 0x00001880 (0000ms, 38014ms total) +T3170 107:954 JLINK_WriteMem(0x20000144, 0x0080 Bytes, ...) - Data: 78 5F 62 75 66 66 65 72 00 00 00 00 30 75 20 3C ... -- CPU_WriteMem(128 bytes @ 0x20000144) returns 0x80 (0048ms, 38062ms total) +T3170 108:002 JLINK_WriteReg(R0, 0x00001880) returns 0x00 (0000ms, 38062ms total) +T3170 108:002 JLINK_WriteReg(R1, 0x00000080) returns 0x00 (0000ms, 38062ms total) +T3170 108:002 JLINK_WriteReg(R2, 0x20000144) returns 0x00 (0000ms, 38062ms total) +T3170 108:002 JLINK_WriteReg(R3, 0x00000000) returns 0x00 (0000ms, 38062ms total) +T3170 108:002 JLINK_WriteReg(R4, 0x00000000) returns 0x00 (0000ms, 38062ms total) +T3170 108:002 JLINK_WriteReg(R5, 0x00000000) returns 0x00 (0000ms, 38062ms total) +T3170 108:002 JLINK_WriteReg(R6, 0x00000000) returns 0x00 (0000ms, 38062ms total) +T3170 108:002 JLINK_WriteReg(R7, 0x00000000) returns 0x00 (0000ms, 38062ms total) +T3170 108:002 JLINK_WriteReg(R8, 0x00000000) returns 0x00 (0000ms, 38062ms total) +T3170 108:002 JLINK_WriteReg(R9, 0x2000013C) returns 0x00 (0000ms, 38062ms total) +T3170 108:002 JLINK_WriteReg(R10, 0x00000000) returns 0x00 (0000ms, 38062ms total) +T3170 108:002 JLINK_WriteReg(R11, 0x00000000) returns 0x00 (0000ms, 38062ms total) +T3170 108:002 JLINK_WriteReg(R12, 0x00000000) returns 0x00 (0000ms, 38062ms total) +T3170 108:002 JLINK_WriteReg(R13 (SP), 0x20001000) returns 0x00 (0000ms, 38062ms total) +T3170 108:002 JLINK_WriteReg(R14, 0x20000001) returns 0x00 (0000ms, 38062ms total) +T3170 108:002 JLINK_WriteReg(R15 (PC), 0x20000104) returns 0x00 (0000ms, 38062ms total) +T3170 108:002 JLINK_WriteReg(XPSR, 0x01000000) returns 0x00 (0000ms, 38062ms total) +T3170 108:002 JLINK_WriteReg(MSP, 0x20001000) returns 0x00 (0000ms, 38062ms total) +T3170 108:002 JLINK_WriteReg(PSP, 0x20001000) returns 0x00 (0000ms, 38062ms total) +T3170 108:002 JLINK_WriteReg(CFBP, 0x00000000) returns 0x00 (0000ms, 38062ms total) +T3170 108:002 JLINK_SetBPEx(Addr = 0x20000000, Type = 0xFFFFFFF2) returns 0x000000E7 (0000ms, 38062ms total) +T3170 108:002 JLINK_Go() -- CPU_ReadMem(4 bytes @ 0xE0001000) (0009ms, 38071ms total) +T3170 108:011 JLINK_IsHalted() -- CPU_ReadMem(2 bytes @ 0x20000000) returns TRUE (0089ms, 38160ms total) +T3170 108:100 JLINK_ReadReg(R15 (PC)) returns 0x20000000 (0000ms, 38071ms total) +T3170 108:100 JLINK_ClrBPEx(BPHandle = 0x000000E7) returns 0x00 (0000ms, 38071ms total) +T3170 108:100 JLINK_ReadReg(R0) returns 0x00001900 (0000ms, 38071ms total) +T3170 108:100 JLINK_WriteMem(0x20000144, 0x0080 Bytes, ...) - Data: F0 00 00 20 D8 13 00 20 F4 00 00 20 6D 73 68 20 ... -- CPU_WriteMem(128 bytes @ 0x20000144) returns 0x80 (0004ms, 38075ms total) +T3170 108:104 JLINK_WriteReg(R0, 0x00001900) returns 0x00 (0000ms, 38075ms total) +T3170 108:104 JLINK_WriteReg(R1, 0x00000080) returns 0x00 (0000ms, 38075ms total) +T3170 108:104 JLINK_WriteReg(R2, 0x20000144) returns 0x00 (0000ms, 38075ms total) +T3170 108:104 JLINK_WriteReg(R3, 0x00000000) returns 0x00 (0000ms, 38075ms total) +T3170 108:104 JLINK_WriteReg(R4, 0x00000000) returns 0x00 (0000ms, 38075ms total) +T3170 108:104 JLINK_WriteReg(R5, 0x00000000) returns 0x00 (0000ms, 38075ms total) +T3170 108:104 JLINK_WriteReg(R6, 0x00000000) returns 0x00 (0000ms, 38075ms total) +T3170 108:104 JLINK_WriteReg(R7, 0x00000000) returns 0x00 (0000ms, 38075ms total) +T3170 108:104 JLINK_WriteReg(R8, 0x00000000) returns 0x00 (0000ms, 38075ms total) +T3170 108:104 JLINK_WriteReg(R9, 0x2000013C) returns 0x00 (0000ms, 38075ms total) +T3170 108:104 JLINK_WriteReg(R10, 0x00000000) returns 0x00 (0000ms, 38075ms total) +T3170 108:104 JLINK_WriteReg(R11, 0x00000000) returns 0x00 (0000ms, 38075ms total) +T3170 108:104 JLINK_WriteReg(R12, 0x00000000) returns 0x00 (0000ms, 38075ms total) +T3170 108:104 JLINK_WriteReg(R13 (SP), 0x20001000) returns 0x00 (0000ms, 38075ms total) +T3170 108:104 JLINK_WriteReg(R14, 0x20000001) returns 0x00 (0000ms, 38075ms total) +T3170 108:104 JLINK_WriteReg(R15 (PC), 0x20000104) returns 0x00 (0000ms, 38075ms total) +T3170 108:104 JLINK_WriteReg(XPSR, 0x01000000) returns 0x00 (0000ms, 38075ms total) +T3170 108:104 JLINK_WriteReg(MSP, 0x20001000) returns 0x00 (0000ms, 38075ms total) +T3170 108:104 JLINK_WriteReg(PSP, 0x20001000) returns 0x00 (0000ms, 38075ms total) +T3170 108:104 JLINK_WriteReg(CFBP, 0x00000000) returns 0x00 (0000ms, 38075ms total) +T3170 108:104 JLINK_SetBPEx(Addr = 0x20000000, Type = 0xFFFFFFF2) returns 0x000000E8 (0000ms, 38075ms total) +T3170 108:104 JLINK_Go() -- CPU_ReadMem(4 bytes @ 0xE0001000) (0007ms, 38082ms total) +T3170 108:111 JLINK_IsHalted() -- CPU_ReadMem(2 bytes @ 0x20000000) returns TRUE (0074ms, 38156ms total) +T3170 108:185 JLINK_ReadReg(R15 (PC)) returns 0x20000000 (0000ms, 38082ms total) +T3170 108:185 JLINK_ClrBPEx(BPHandle = 0x000000E8) returns 0x00 (0000ms, 38082ms total) +T3170 108:185 JLINK_ReadReg(R0) returns 0x00001980 (0000ms, 38082ms total) +T3170 108:185 JLINK_WriteMem(0x20000144, 0x0080 Bytes, ...) - Data: 0A 20 06 21 4F F4 80 63 00 22 CD E9 00 10 14 49 ... -- CPU_WriteMem(128 bytes @ 0x20000144) returns 0x80 (0017ms, 38099ms total) +T3170 108:202 JLINK_WriteReg(R0, 0x00001980) returns 0x00 (0000ms, 38099ms total) +T3170 108:202 JLINK_WriteReg(R1, 0x00000080) returns 0x00 (0000ms, 38099ms total) +T3170 108:202 JLINK_WriteReg(R2, 0x20000144) returns 0x00 (0000ms, 38099ms total) +T3170 108:202 JLINK_WriteReg(R3, 0x00000000) returns 0x00 (0000ms, 38099ms total) +T3170 108:202 JLINK_WriteReg(R4, 0x00000000) returns 0x00 (0000ms, 38099ms total) +T3170 108:202 JLINK_WriteReg(R5, 0x00000000) returns 0x00 (0000ms, 38099ms total) +T3170 108:202 JLINK_WriteReg(R6, 0x00000000) returns 0x00 (0000ms, 38099ms total) +T3170 108:202 JLINK_WriteReg(R7, 0x00000000) returns 0x00 (0000ms, 38099ms total) +T3170 108:202 JLINK_WriteReg(R8, 0x00000000) returns 0x00 (0000ms, 38099ms total) +T3170 108:202 JLINK_WriteReg(R9, 0x2000013C) returns 0x00 (0000ms, 38099ms total) +T3170 108:202 JLINK_WriteReg(R10, 0x00000000) returns 0x00 (0000ms, 38099ms total) +T3170 108:202 JLINK_WriteReg(R11, 0x00000000) returns 0x00 (0000ms, 38099ms total) +T3170 108:202 JLINK_WriteReg(R12, 0x00000000) returns 0x00 (0000ms, 38099ms total) +T3170 108:202 JLINK_WriteReg(R13 (SP), 0x20001000) returns 0x00 (0000ms, 38099ms total) +T3170 108:202 JLINK_WriteReg(R14, 0x20000001) returns 0x00 (0000ms, 38099ms total) +T3170 108:202 JLINK_WriteReg(R15 (PC), 0x20000104) returns 0x00 (0000ms, 38099ms total) +T3170 108:202 JLINK_WriteReg(XPSR, 0x01000000) returns 0x00 (0000ms, 38099ms total) +T3170 108:202 JLINK_WriteReg(MSP, 0x20001000) returns 0x00 (0000ms, 38099ms total) +T3170 108:202 JLINK_WriteReg(PSP, 0x20001000) returns 0x00 (0000ms, 38099ms total) +T3170 108:202 JLINK_WriteReg(CFBP, 0x00000000) returns 0x00 (0000ms, 38099ms total) +T3170 108:202 JLINK_SetBPEx(Addr = 0x20000000, Type = 0xFFFFFFF2) returns 0x000000E9 (0000ms, 38099ms total) +T3170 108:202 JLINK_Go() -- CPU_ReadMem(4 bytes @ 0xE0001000) (0007ms, 38106ms total) +T3170 108:209 JLINK_IsHalted() -- CPU_ReadMem(2 bytes @ 0x20000000) returns TRUE (0005ms, 38111ms total) +T3170 108:215 JLINK_ReadReg(R15 (PC)) returns 0x20000000 (0000ms, 38106ms total) +T3170 108:215 JLINK_ClrBPEx(BPHandle = 0x000000E9) returns 0x00 (0000ms, 38106ms total) +T3170 108:215 JLINK_ReadReg(R0) returns 0x00001A00 (0000ms, 38106ms total) +T3170 108:215 JLINK_WriteMem(0x20000144, 0x0080 Bytes, ...) - Data: 40 1C E6 49 09 68 81 F8 21 00 FF F7 4F FF 05 46 ... -- CPU_WriteMem(128 bytes @ 0x20000144) returns 0x80 (0003ms, 38109ms total) +T3170 108:218 JLINK_WriteReg(R0, 0x00001A00) returns 0x00 (0000ms, 38109ms total) +T3170 108:218 JLINK_WriteReg(R1, 0x00000080) returns 0x00 (0000ms, 38109ms total) +T3170 108:218 JLINK_WriteReg(R2, 0x20000144) returns 0x00 (0000ms, 38109ms total) +T3170 108:218 JLINK_WriteReg(R3, 0x00000000) returns 0x00 (0000ms, 38109ms total) +T3170 108:218 JLINK_WriteReg(R4, 0x00000000) returns 0x00 (0000ms, 38109ms total) +T3170 108:218 JLINK_WriteReg(R5, 0x00000000) returns 0x00 (0000ms, 38109ms total) +T3170 108:218 JLINK_WriteReg(R6, 0x00000000) returns 0x00 (0000ms, 38109ms total) +T3170 108:218 JLINK_WriteReg(R7, 0x00000000) returns 0x00 (0000ms, 38109ms total) +T3170 108:218 JLINK_WriteReg(R8, 0x00000000) returns 0x00 (0000ms, 38109ms total) +T3170 108:218 JLINK_WriteReg(R9, 0x2000013C) returns 0x00 (0000ms, 38109ms total) +T3170 108:218 JLINK_WriteReg(R10, 0x00000000) returns 0x00 (0000ms, 38109ms total) +T3170 108:218 JLINK_WriteReg(R11, 0x00000000) returns 0x00 (0000ms, 38109ms total) +T3170 108:218 JLINK_WriteReg(R12, 0x00000000) returns 0x00 (0000ms, 38109ms total) +T3170 108:218 JLINK_WriteReg(R13 (SP), 0x20001000) returns 0x00 (0000ms, 38109ms total) +T3170 108:218 JLINK_WriteReg(R14, 0x20000001) returns 0x00 (0000ms, 38109ms total) +T3170 108:218 JLINK_WriteReg(R15 (PC), 0x20000104) returns 0x00 (0000ms, 38109ms total) +T3170 108:218 JLINK_WriteReg(XPSR, 0x01000000) returns 0x00 (0000ms, 38109ms total) +T3170 108:218 JLINK_WriteReg(MSP, 0x20001000) returns 0x00 (0000ms, 38109ms total) +T3170 108:218 JLINK_WriteReg(PSP, 0x20001000) returns 0x00 (0000ms, 38109ms total) +T3170 108:218 JLINK_WriteReg(CFBP, 0x00000000) returns 0x00 (0000ms, 38109ms total) +T3170 108:218 JLINK_SetBPEx(Addr = 0x20000000, Type = 0xFFFFFFF2) returns 0x000000EA (0000ms, 38109ms total) +T3170 108:218 JLINK_Go() -- CPU_ReadMem(4 bytes @ 0xE0001000) (0086ms, 38195ms total) +T3170 108:304 JLINK_IsHalted() -- CPU_ReadMem(2 bytes @ 0x20000000) returns TRUE (0011ms, 38206ms total) +T3170 108:315 JLINK_ReadReg(R15 (PC)) returns 0x20000000 (0000ms, 38195ms total) +T3170 108:315 JLINK_ClrBPEx(BPHandle = 0x000000EA) returns 0x00 (0000ms, 38195ms total) +T3170 108:315 JLINK_ReadReg(R0) returns 0x00001A80 (0000ms, 38195ms total) +T3170 108:315 JLINK_WriteMem(0x20000144, 0x0080 Bytes, ...) - Data: C6 48 00 68 B0 F8 74 00 58 B1 C5 A0 01 F0 68 FE ... -- CPU_WriteMem(128 bytes @ 0x20000144) returns 0x80 (0086ms, 38281ms total) +T3170 108:401 JLINK_WriteReg(R0, 0x00001A80) returns 0x00 (0000ms, 38281ms total) +T3170 108:401 JLINK_WriteReg(R1, 0x00000080) returns 0x00 (0000ms, 38281ms total) +T3170 108:401 JLINK_WriteReg(R2, 0x20000144) returns 0x00 (0000ms, 38281ms total) +T3170 108:401 JLINK_WriteReg(R3, 0x00000000) returns 0x00 (0000ms, 38281ms total) +T3170 108:401 JLINK_WriteReg(R4, 0x00000000) returns 0x00 (0000ms, 38281ms total) +T3170 108:401 JLINK_WriteReg(R5, 0x00000000) returns 0x00 (0000ms, 38281ms total) +T3170 108:401 JLINK_WriteReg(R6, 0x00000000) returns 0x00 (0000ms, 38281ms total) +T3170 108:401 JLINK_WriteReg(R7, 0x00000000) returns 0x00 (0000ms, 38281ms total) +T3170 108:401 JLINK_WriteReg(R8, 0x00000000) returns 0x00 (0000ms, 38281ms total) +T3170 108:401 JLINK_WriteReg(R9, 0x2000013C) returns 0x00 (0000ms, 38281ms total) +T3170 108:401 JLINK_WriteReg(R10, 0x00000000) returns 0x00 (0000ms, 38281ms total) +T3170 108:401 JLINK_WriteReg(R11, 0x00000000) returns 0x00 (0000ms, 38281ms total) +T3170 108:402 JLINK_WriteReg(R12, 0x00000000) returns 0x00 (0000ms, 38281ms total) +T3170 108:402 JLINK_WriteReg(R13 (SP), 0x20001000) returns 0x00 (0000ms, 38281ms total) +T3170 108:402 JLINK_WriteReg(R14, 0x20000001) returns 0x00 (0000ms, 38281ms total) +T3170 108:402 JLINK_WriteReg(R15 (PC), 0x20000104) returns 0x00 (0000ms, 38281ms total) +T3170 108:402 JLINK_WriteReg(XPSR, 0x01000000) returns 0x00 (0000ms, 38281ms total) +T3170 108:402 JLINK_WriteReg(MSP, 0x20001000) returns 0x00 (0000ms, 38281ms total) +T3170 108:402 JLINK_WriteReg(PSP, 0x20001000) returns 0x00 (0000ms, 38281ms total) +T3170 108:402 JLINK_WriteReg(CFBP, 0x00000000) returns 0x00 (0000ms, 38281ms total) +T3170 108:402 JLINK_SetBPEx(Addr = 0x20000000, Type = 0xFFFFFFF2) returns 0x000000EB (0000ms, 38281ms total) +T3170 108:402 JLINK_Go() -- CPU_ReadMem(4 bytes @ 0xE0001000) (0008ms, 38289ms total) +T3170 108:410 JLINK_IsHalted() -- CPU_ReadMem(2 bytes @ 0x20000000) returns TRUE (0017ms, 38306ms total) +T3170 108:427 JLINK_ReadReg(R15 (PC)) returns 0x20000000 (0000ms, 38289ms total) +T3170 108:427 JLINK_ClrBPEx(BPHandle = 0x000000EB) returns 0x00 (0000ms, 38289ms total) +T3170 108:427 JLINK_ReadReg(R0) returns 0x00001B00 (0000ms, 38289ms total) +T3170 108:427 JLINK_WriteMem(0x20000144, 0x0080 Bytes, ...) - Data: 00 68 B0 F8 74 00 A8 42 F5 DC A4 48 00 68 22 30 ... -- CPU_WriteMem(128 bytes @ 0x20000144) returns 0x80 (0074ms, 38363ms total) +T3170 108:501 JLINK_WriteReg(R0, 0x00001B00) returns 0x00 (0000ms, 38363ms total) +T3170 108:501 JLINK_WriteReg(R1, 0x00000080) returns 0x00 (0000ms, 38363ms total) +T3170 108:501 JLINK_WriteReg(R2, 0x20000144) returns 0x00 (0000ms, 38363ms total) +T3170 108:501 JLINK_WriteReg(R3, 0x00000000) returns 0x00 (0000ms, 38363ms total) +T3170 108:501 JLINK_WriteReg(R4, 0x00000000) returns 0x00 (0000ms, 38363ms total) +T3170 108:501 JLINK_WriteReg(R5, 0x00000000) returns 0x00 (0000ms, 38363ms total) +T3170 108:501 JLINK_WriteReg(R6, 0x00000000) returns 0x00 (0000ms, 38363ms total) +T3170 108:501 JLINK_WriteReg(R7, 0x00000000) returns 0x00 (0000ms, 38363ms total) +T3170 108:501 JLINK_WriteReg(R8, 0x00000000) returns 0x00 (0001ms, 38364ms total) +T3170 108:502 JLINK_WriteReg(R9, 0x2000013C) returns 0x00 (0000ms, 38364ms total) +T3170 108:502 JLINK_WriteReg(R10, 0x00000000) returns 0x00 (0000ms, 38364ms total) +T3170 108:502 JLINK_WriteReg(R11, 0x00000000) returns 0x00 (0000ms, 38364ms total) +T3170 108:502 JLINK_WriteReg(R12, 0x00000000) returns 0x00 (0000ms, 38364ms total) +T3170 108:502 JLINK_WriteReg(R13 (SP), 0x20001000) returns 0x00 (0000ms, 38364ms total) +T3170 108:502 JLINK_WriteReg(R14, 0x20000001) returns 0x00 (0000ms, 38364ms total) +T3170 108:502 JLINK_WriteReg(R15 (PC), 0x20000104) returns 0x00 (0000ms, 38364ms total) +T3170 108:502 JLINK_WriteReg(XPSR, 0x01000000) returns 0x00 (0000ms, 38364ms total) +T3170 108:502 JLINK_WriteReg(MSP, 0x20001000) returns 0x00 (0000ms, 38364ms total) +T3170 108:502 JLINK_WriteReg(PSP, 0x20001000) returns 0x00 (0000ms, 38364ms total) +T3170 108:502 JLINK_WriteReg(CFBP, 0x00000000) returns 0x00 (0000ms, 38364ms total) +T3170 108:502 JLINK_SetBPEx(Addr = 0x20000000, Type = 0xFFFFFFF2) returns 0x000000EC (0000ms, 38364ms total) +T3170 108:502 JLINK_Go() -- CPU_ReadMem(4 bytes @ 0xE0001000) (0006ms, 38370ms total) +T3170 108:508 JLINK_IsHalted() -- CPU_ReadMem(2 bytes @ 0x20000000) returns TRUE (0008ms, 38378ms total) +T3170 108:516 JLINK_ReadReg(R15 (PC)) returns 0x20000000 (0000ms, 38370ms total) +T3170 108:516 JLINK_ClrBPEx(BPHandle = 0x000000EC) returns 0x00 (0000ms, 38370ms total) +T3170 108:516 JLINK_ReadReg(R0) returns 0x00001B80 (0000ms, 38370ms total) +T3170 108:516 JLINK_WriteMem(0x20000144, 0x0080 Bytes, ...) - Data: 1B 68 B3 F8 72 30 85 4E 36 68 B6 F8 74 60 9A 1B ... -- CPU_WriteMem(128 bytes @ 0x20000144) returns 0x80 (0085ms, 38455ms total) +T3170 108:601 JLINK_WriteReg(R0, 0x00001B80) returns 0x00 (0000ms, 38455ms total) +T3170 108:601 JLINK_WriteReg(R1, 0x00000080) returns 0x00 (0000ms, 38455ms total) +T3170 108:601 JLINK_WriteReg(R2, 0x20000144) returns 0x00 (0000ms, 38455ms total) +T3170 108:601 JLINK_WriteReg(R3, 0x00000000) returns 0x00 (0001ms, 38456ms total) +T3170 108:602 JLINK_WriteReg(R4, 0x00000000) returns 0x00 (0000ms, 38456ms total) +T3170 108:602 JLINK_WriteReg(R5, 0x00000000) returns 0x00 (0000ms, 38456ms total) +T3170 108:602 JLINK_WriteReg(R6, 0x00000000) returns 0x00 (0000ms, 38456ms total) +T3170 108:602 JLINK_WriteReg(R7, 0x00000000) returns 0x00 (0000ms, 38456ms total) +T3170 108:602 JLINK_WriteReg(R8, 0x00000000) returns 0x00 (0000ms, 38456ms total) +T3170 108:602 JLINK_WriteReg(R9, 0x2000013C) returns 0x00 (0000ms, 38456ms total) +T3170 108:602 JLINK_WriteReg(R10, 0x00000000) returns 0x00 (0000ms, 38456ms total) +T3170 108:602 JLINK_WriteReg(R11, 0x00000000) returns 0x00 (0000ms, 38456ms total) +T3170 108:602 JLINK_WriteReg(R12, 0x00000000) returns 0x00 (0000ms, 38456ms total) +T3170 108:602 JLINK_WriteReg(R13 (SP), 0x20001000) returns 0x00 (0000ms, 38456ms total) +T3170 108:602 JLINK_WriteReg(R14, 0x20000001) returns 0x00 (0000ms, 38456ms total) +T3170 108:602 JLINK_WriteReg(R15 (PC), 0x20000104) returns 0x00 (0000ms, 38456ms total) +T3170 108:602 JLINK_WriteReg(XPSR, 0x01000000) returns 0x00 (0000ms, 38456ms total) +T3170 108:602 JLINK_WriteReg(MSP, 0x20001000) returns 0x00 (0000ms, 38456ms total) +T3170 108:602 JLINK_WriteReg(PSP, 0x20001000) returns 0x00 (0000ms, 38456ms total) +T3170 108:602 JLINK_WriteReg(CFBP, 0x00000000) returns 0x00 (0000ms, 38456ms total) +T3170 108:602 JLINK_SetBPEx(Addr = 0x20000000, Type = 0xFFFFFFF2) returns 0x000000ED (0000ms, 38456ms total) +T3170 108:602 JLINK_Go() -- CPU_ReadMem(4 bytes @ 0xE0001000) (0007ms, 38463ms total) +T3170 108:609 JLINK_IsHalted() -- CPU_ReadMem(2 bytes @ 0x20000000) returns TRUE (0051ms, 38514ms total) +T3170 108:660 JLINK_ReadReg(R15 (PC)) returns 0x20000000 (0000ms, 38463ms total) +T3170 108:700 JLINK_ClrBPEx(BPHandle = 0x000000ED) returns 0x00 (0000ms, 38463ms total) +T3170 108:700 JLINK_ReadReg(R0) returns 0x00001C00 (0000ms, 38463ms total) +T3170 108:700 JLINK_WriteMem(0x20000144, 0x0080 Bytes, ...) - Data: 01 F0 AE FD 00 21 65 48 00 68 B0 F8 72 20 63 48 ... -- CPU_WriteMem(128 bytes @ 0x20000144) returns 0x80 (0004ms, 38467ms total) +T3170 108:704 JLINK_WriteReg(R0, 0x00001C00) returns 0x00 (0000ms, 38467ms total) +T3170 108:704 JLINK_WriteReg(R1, 0x00000080) returns 0x00 (0000ms, 38467ms total) +T3170 108:704 JLINK_WriteReg(R2, 0x20000144) returns 0x00 (0000ms, 38467ms total) +T3170 108:704 JLINK_WriteReg(R3, 0x00000000) returns 0x00 (0000ms, 38467ms total) +T3170 108:704 JLINK_WriteReg(R4, 0x00000000) returns 0x00 (0000ms, 38467ms total) +T3170 108:704 JLINK_WriteReg(R5, 0x00000000) returns 0x00 (0000ms, 38467ms total) +T3170 108:704 JLINK_WriteReg(R6, 0x00000000) returns 0x00 (0000ms, 38467ms total) +T3170 108:704 JLINK_WriteReg(R7, 0x00000000) returns 0x00 (0000ms, 38467ms total) +T3170 108:704 JLINK_WriteReg(R8, 0x00000000) returns 0x00 (0000ms, 38467ms total) +T3170 108:704 JLINK_WriteReg(R9, 0x2000013C) returns 0x00 (0000ms, 38467ms total) +T3170 108:705 JLINK_WriteReg(R10, 0x00000000) returns 0x00 (0000ms, 38467ms total) +T3170 108:705 JLINK_WriteReg(R11, 0x00000000) returns 0x00 (0000ms, 38467ms total) +T3170 108:705 JLINK_WriteReg(R12, 0x00000000) returns 0x00 (0000ms, 38467ms total) +T3170 108:705 JLINK_WriteReg(R13 (SP), 0x20001000) returns 0x00 (0000ms, 38467ms total) +T3170 108:705 JLINK_WriteReg(R14, 0x20000001) returns 0x00 (0000ms, 38467ms total) +T3170 108:705 JLINK_WriteReg(R15 (PC), 0x20000104) returns 0x00 (0000ms, 38467ms total) +T3170 108:705 JLINK_WriteReg(XPSR, 0x01000000) returns 0x00 (0000ms, 38467ms total) +T3170 108:705 JLINK_WriteReg(MSP, 0x20001000) returns 0x00 (0000ms, 38467ms total) +T3170 108:705 JLINK_WriteReg(PSP, 0x20001000) returns 0x00 (0000ms, 38467ms total) +T3170 108:705 JLINK_WriteReg(CFBP, 0x00000000) returns 0x00 (0000ms, 38467ms total) +T3170 108:705 JLINK_SetBPEx(Addr = 0x20000000, Type = 0xFFFFFFF2) returns 0x000000EE (0000ms, 38467ms total) +T3170 108:705 JLINK_Go() -- CPU_ReadMem(4 bytes @ 0xE0001000) (0006ms, 38473ms total) +T3170 108:711 JLINK_IsHalted() -- CPU_ReadMem(2 bytes @ 0x20000000) returns TRUE (0089ms, 38562ms total) +T3170 108:800 JLINK_ReadReg(R15 (PC)) returns 0x20000000 (0000ms, 38473ms total) +T3170 108:800 JLINK_ClrBPEx(BPHandle = 0x000000EE) returns 0x00 (0000ms, 38473ms total) +T3170 108:800 JLINK_ReadReg(R0) returns 0x00001C80 (0000ms, 38473ms total) +T3170 108:800 JLINK_WriteMem(0x20000144, 0x0080 Bytes, ...) - Data: 50 28 04 DB 00 20 45 49 09 68 A1 F8 72 00 43 48 ... -- CPU_WriteMem(128 bytes @ 0x20000144) returns 0x80 (0004ms, 38477ms total) +T3170 108:804 JLINK_WriteReg(R0, 0x00001C80) returns 0x00 (0000ms, 38477ms total) +T3170 108:804 JLINK_WriteReg(R1, 0x00000080) returns 0x00 (0000ms, 38477ms total) +T3170 108:804 JLINK_WriteReg(R2, 0x20000144) returns 0x00 (0000ms, 38477ms total) +T3170 108:804 JLINK_WriteReg(R3, 0x00000000) returns 0x00 (0000ms, 38477ms total) +T3170 108:804 JLINK_WriteReg(R4, 0x00000000) returns 0x00 (0000ms, 38477ms total) +T3170 108:804 JLINK_WriteReg(R5, 0x00000000) returns 0x00 (0000ms, 38477ms total) +T3170 108:804 JLINK_WriteReg(R6, 0x00000000) returns 0x00 (0000ms, 38477ms total) +T3170 108:804 JLINK_WriteReg(R7, 0x00000000) returns 0x00 (0000ms, 38477ms total) +T3170 108:804 JLINK_WriteReg(R8, 0x00000000) returns 0x00 (0000ms, 38477ms total) +T3170 108:804 JLINK_WriteReg(R9, 0x2000013C) returns 0x00 (0000ms, 38477ms total) +T3170 108:804 JLINK_WriteReg(R10, 0x00000000) returns 0x00 (0000ms, 38477ms total) +T3170 108:804 JLINK_WriteReg(R11, 0x00000000) returns 0x00 (0000ms, 38477ms total) +T3170 108:804 JLINK_WriteReg(R12, 0x00000000) returns 0x00 (0000ms, 38477ms total) +T3170 108:804 JLINK_WriteReg(R13 (SP), 0x20001000) returns 0x00 (0000ms, 38477ms total) +T3170 108:804 JLINK_WriteReg(R14, 0x20000001) returns 0x00 (0000ms, 38477ms total) +T3170 108:804 JLINK_WriteReg(R15 (PC), 0x20000104) returns 0x00 (0000ms, 38477ms total) +T3170 108:804 JLINK_WriteReg(XPSR, 0x01000000) returns 0x00 (0000ms, 38477ms total) +T3170 108:804 JLINK_WriteReg(MSP, 0x20001000) returns 0x00 (0000ms, 38477ms total) +T3170 108:804 JLINK_WriteReg(PSP, 0x20001000) returns 0x00 (0000ms, 38477ms total) +T3170 108:804 JLINK_WriteReg(CFBP, 0x00000000) returns 0x00 (0000ms, 38477ms total) +T3170 108:804 JLINK_SetBPEx(Addr = 0x20000000, Type = 0xFFFFFFF2) returns 0x000000EF (0000ms, 38477ms total) +T3170 108:804 JLINK_Go() -- CPU_ReadMem(4 bytes @ 0xE0001000) (0007ms, 38484ms total) +T3170 108:811 JLINK_IsHalted() -- CPU_ReadMem(2 bytes @ 0x20000000) returns TRUE (0089ms, 38573ms total) +T3170 108:900 JLINK_ReadReg(R15 (PC)) returns 0x20000000 (0000ms, 38484ms total) +T3170 108:903 JLINK_ClrBPEx(BPHandle = 0x000000EF) returns 0x00 (0000ms, 38484ms total) +T3170 108:903 JLINK_ReadReg(R0) returns 0x00001D00 (0000ms, 38484ms total) +T3170 108:903 JLINK_WriteMem(0x20000144, 0x0080 Bytes, ...) - Data: 26 48 00 68 22 30 11 18 2B A0 01 F0 29 FD 23 48 ... -- CPU_WriteMem(128 bytes @ 0x20000144) returns 0x80 (0003ms, 38487ms total) +T3170 108:906 JLINK_WriteReg(R0, 0x00001D00) returns 0x00 (0000ms, 38487ms total) +T3170 108:906 JLINK_WriteReg(R1, 0x00000080) returns 0x00 (0000ms, 38487ms total) +T3170 108:906 JLINK_WriteReg(R2, 0x20000144) returns 0x00 (0000ms, 38487ms total) +T3170 108:906 JLINK_WriteReg(R3, 0x00000000) returns 0x00 (0000ms, 38487ms total) +T3170 108:906 JLINK_WriteReg(R4, 0x00000000) returns 0x00 (0000ms, 38487ms total) +T3170 108:906 JLINK_WriteReg(R5, 0x00000000) returns 0x00 (0000ms, 38487ms total) +T3170 108:906 JLINK_WriteReg(R6, 0x00000000) returns 0x00 (0000ms, 38487ms total) +T3170 108:906 JLINK_WriteReg(R7, 0x00000000) returns 0x00 (0000ms, 38487ms total) +T3170 108:906 JLINK_WriteReg(R8, 0x00000000) returns 0x00 (0000ms, 38487ms total) +T3170 108:906 JLINK_WriteReg(R9, 0x2000013C) returns 0x00 (0000ms, 38487ms total) +T3170 108:906 JLINK_WriteReg(R10, 0x00000000) returns 0x00 (0000ms, 38487ms total) +T3170 108:906 JLINK_WriteReg(R11, 0x00000000) returns 0x00 (0000ms, 38487ms total) +T3170 108:906 JLINK_WriteReg(R12, 0x00000000) returns 0x00 (0000ms, 38487ms total) +T3170 108:906 JLINK_WriteReg(R13 (SP), 0x20001000) returns 0x00 (0000ms, 38487ms total) +T3170 108:906 JLINK_WriteReg(R14, 0x20000001) returns 0x00 (0000ms, 38487ms total) +T3170 108:906 JLINK_WriteReg(R15 (PC), 0x20000104) returns 0x00 (0000ms, 38487ms total) +T3170 108:906 JLINK_WriteReg(XPSR, 0x01000000) returns 0x00 (0000ms, 38487ms total) +T3170 108:906 JLINK_WriteReg(MSP, 0x20001000) returns 0x00 (0000ms, 38487ms total) +T3170 108:906 JLINK_WriteReg(PSP, 0x20001000) returns 0x00 (0000ms, 38487ms total) +T3170 108:907 JLINK_WriteReg(CFBP, 0x00000000) returns 0x00 (0000ms, 38488ms total) +T3170 108:907 JLINK_SetBPEx(Addr = 0x20000000, Type = 0xFFFFFFF2) returns 0x000000F0 (0000ms, 38488ms total) +T3170 108:907 JLINK_Go() -- CPU_ReadMem(4 bytes @ 0xE0001000) (0006ms, 38494ms total) +T3170 108:913 JLINK_IsHalted() -- CPU_ReadMem(2 bytes @ 0x20000000) returns TRUE (0088ms, 38582ms total) +T3170 109:001 JLINK_ReadReg(R15 (PC)) returns 0x20000000 (0000ms, 38494ms total) +T3170 109:001 JLINK_ClrBPEx(BPHandle = 0x000000F0) returns 0x00 (0000ms, 38494ms total) +T3170 109:001 JLINK_ReadReg(R0) returns 0x00001D80 (0000ms, 38494ms total) +T3170 109:001 JLINK_WriteMem(0x20000144, 0x0080 Bytes, ...) - Data: 72 00 50 28 08 DB 00 20 04 49 09 68 A1 F8 72 00 ... -- CPU_WriteMem(128 bytes @ 0x20000144) returns 0x80 (0004ms, 38498ms total) +T3170 109:005 JLINK_WriteReg(R0, 0x00001D80) returns 0x00 (0000ms, 38498ms total) +T3170 109:005 JLINK_WriteReg(R1, 0x00000080) returns 0x00 (0000ms, 38498ms total) +T3170 109:005 JLINK_WriteReg(R2, 0x20000144) returns 0x00 (0000ms, 38498ms total) +T3170 109:005 JLINK_WriteReg(R3, 0x00000000) returns 0x00 (0000ms, 38498ms total) +T3170 109:005 JLINK_WriteReg(R4, 0x00000000) returns 0x00 (0000ms, 38498ms total) +T3170 109:005 JLINK_WriteReg(R5, 0x00000000) returns 0x00 (0000ms, 38498ms total) +T3170 109:005 JLINK_WriteReg(R6, 0x00000000) returns 0x00 (0000ms, 38498ms total) +T3170 109:005 JLINK_WriteReg(R7, 0x00000000) returns 0x00 (0000ms, 38498ms total) +T3170 109:005 JLINK_WriteReg(R8, 0x00000000) returns 0x00 (0000ms, 38498ms total) +T3170 109:005 JLINK_WriteReg(R9, 0x2000013C) returns 0x00 (0000ms, 38498ms total) +T3170 109:005 JLINK_WriteReg(R10, 0x00000000) returns 0x00 (0000ms, 38498ms total) +T3170 109:005 JLINK_WriteReg(R11, 0x00000000) returns 0x00 (0000ms, 38498ms total) +T3170 109:005 JLINK_WriteReg(R12, 0x00000000) returns 0x00 (0000ms, 38498ms total) +T3170 109:005 JLINK_WriteReg(R13 (SP), 0x20001000) returns 0x00 (0000ms, 38498ms total) +T3170 109:005 JLINK_WriteReg(R14, 0x20000001) returns 0x00 (0000ms, 38498ms total) +T3170 109:005 JLINK_WriteReg(R15 (PC), 0x20000104) returns 0x00 (0000ms, 38498ms total) +T3170 109:005 JLINK_WriteReg(XPSR, 0x01000000) returns 0x00 (0000ms, 38498ms total) +T3170 109:005 JLINK_WriteReg(MSP, 0x20001000) returns 0x00 (0000ms, 38498ms total) +T3170 109:005 JLINK_WriteReg(PSP, 0x20001000) returns 0x00 (0000ms, 38498ms total) +T3170 109:005 JLINK_WriteReg(CFBP, 0x00000000) returns 0x00 (0000ms, 38498ms total) +T3170 109:005 JLINK_SetBPEx(Addr = 0x20000000, Type = 0xFFFFFFF2) returns 0x000000F1 (0000ms, 38498ms total) +T3170 109:005 JLINK_Go() -- CPU_ReadMem(4 bytes @ 0xE0001000) (0007ms, 38505ms total) +T3170 109:012 JLINK_IsHalted() -- CPU_ReadMem(2 bytes @ 0x20000000) returns TRUE (0088ms, 38593ms total) +T3170 109:100 JLINK_ReadReg(R15 (PC)) returns 0x20000000 (0000ms, 38505ms total) +T3170 109:100 JLINK_ClrBPEx(BPHandle = 0x000000F1) returns 0x00 (0000ms, 38505ms total) +T3170 109:100 JLINK_ReadReg(R0) returns 0x00001E00 (0000ms, 38505ms total) +T3170 109:100 JLINK_WriteMem(0x20000144, 0x0080 Bytes, ...) - Data: 4C 81 03 40 70 B5 04 46 0E 46 15 46 52 48 84 42 ... -- CPU_WriteMem(128 bytes @ 0x20000144) returns 0x80 (0004ms, 38509ms total) +T3170 109:104 JLINK_WriteReg(R0, 0x00001E00) returns 0x00 (0000ms, 38509ms total) +T3170 109:104 JLINK_WriteReg(R1, 0x00000080) returns 0x00 (0000ms, 38509ms total) +T3170 109:104 JLINK_WriteReg(R2, 0x20000144) returns 0x00 (0000ms, 38509ms total) +T3170 109:104 JLINK_WriteReg(R3, 0x00000000) returns 0x00 (0000ms, 38509ms total) +T3170 109:104 JLINK_WriteReg(R4, 0x00000000) returns 0x00 (0000ms, 38509ms total) +T3170 109:104 JLINK_WriteReg(R5, 0x00000000) returns 0x00 (0000ms, 38509ms total) +T3170 109:104 JLINK_WriteReg(R6, 0x00000000) returns 0x00 (0000ms, 38509ms total) +T3170 109:104 JLINK_WriteReg(R7, 0x00000000) returns 0x00 (0000ms, 38509ms total) +T3170 109:104 JLINK_WriteReg(R8, 0x00000000) returns 0x00 (0000ms, 38509ms total) +T3170 109:104 JLINK_WriteReg(R9, 0x2000013C) returns 0x00 (0000ms, 38509ms total) +T3170 109:104 JLINK_WriteReg(R10, 0x00000000) returns 0x00 (0000ms, 38509ms total) +T3170 109:104 JLINK_WriteReg(R11, 0x00000000) returns 0x00 (0000ms, 38509ms total) +T3170 109:104 JLINK_WriteReg(R12, 0x00000000) returns 0x00 (0000ms, 38509ms total) +T3170 109:104 JLINK_WriteReg(R13 (SP), 0x20001000) returns 0x00 (0000ms, 38509ms total) +T3170 109:104 JLINK_WriteReg(R14, 0x20000001) returns 0x00 (0000ms, 38509ms total) +T3170 109:104 JLINK_WriteReg(R15 (PC), 0x20000104) returns 0x00 (0000ms, 38509ms total) +T3170 109:104 JLINK_WriteReg(XPSR, 0x01000000) returns 0x00 (0000ms, 38509ms total) +T3170 109:104 JLINK_WriteReg(MSP, 0x20001000) returns 0x00 (0000ms, 38509ms total) +T3170 109:104 JLINK_WriteReg(PSP, 0x20001000) returns 0x00 (0000ms, 38509ms total) +T3170 109:104 JLINK_WriteReg(CFBP, 0x00000000) returns 0x00 (0000ms, 38509ms total) +T3170 109:104 JLINK_SetBPEx(Addr = 0x20000000, Type = 0xFFFFFFF2) returns 0x000000F2 (0000ms, 38509ms total) +T3170 109:104 JLINK_Go() -- CPU_ReadMem(4 bytes @ 0xE0001000) (0007ms, 38516ms total) +T3170 109:111 JLINK_IsHalted() -- CPU_ReadMem(2 bytes @ 0x20000000) returns TRUE (0089ms, 38605ms total) +T3170 109:200 JLINK_ReadReg(R15 (PC)) returns 0x20000000 (0000ms, 38516ms total) +T3170 109:200 JLINK_ClrBPEx(BPHandle = 0x000000F2) returns 0x00 (0000ms, 38516ms total) +T3170 109:200 JLINK_ReadReg(R0) returns 0x00001E80 (0000ms, 38516ms total) +T3170 109:201 JLINK_WriteMem(0x20000144, 0x0080 Bytes, ...) - Data: 08 71 21 68 08 72 21 68 01 F1 08 00 01 21 02 F0 ... -- CPU_WriteMem(128 bytes @ 0x20000144) returns 0x80 (0003ms, 38519ms total) +T3170 109:204 JLINK_WriteReg(R0, 0x00001E80) returns 0x00 (0000ms, 38519ms total) +T3170 109:204 JLINK_WriteReg(R1, 0x00000080) returns 0x00 (0000ms, 38519ms total) +T3170 109:204 JLINK_WriteReg(R2, 0x20000144) returns 0x00 (0000ms, 38519ms total) +T3170 109:204 JLINK_WriteReg(R3, 0x00000000) returns 0x00 (0000ms, 38519ms total) +T3170 109:204 JLINK_WriteReg(R4, 0x00000000) returns 0x00 (0000ms, 38519ms total) +T3170 109:204 JLINK_WriteReg(R5, 0x00000000) returns 0x00 (0000ms, 38519ms total) +T3170 109:204 JLINK_WriteReg(R6, 0x00000000) returns 0x00 (0000ms, 38519ms total) +T3170 109:204 JLINK_WriteReg(R7, 0x00000000) returns 0x00 (0000ms, 38519ms total) +T3170 109:204 JLINK_WriteReg(R8, 0x00000000) returns 0x00 (0000ms, 38519ms total) +T3170 109:204 JLINK_WriteReg(R9, 0x2000013C) returns 0x00 (0000ms, 38519ms total) +T3170 109:204 JLINK_WriteReg(R10, 0x00000000) returns 0x00 (0000ms, 38519ms total) +T3170 109:204 JLINK_WriteReg(R11, 0x00000000) returns 0x00 (0000ms, 38519ms total) +T3170 109:204 JLINK_WriteReg(R12, 0x00000000) returns 0x00 (0000ms, 38519ms total) +T3170 109:204 JLINK_WriteReg(R13 (SP), 0x20001000) returns 0x00 (0000ms, 38519ms total) +T3170 109:204 JLINK_WriteReg(R14, 0x20000001) returns 0x00 (0000ms, 38519ms total) +T3170 109:204 JLINK_WriteReg(R15 (PC), 0x20000104) returns 0x00 (0000ms, 38519ms total) +T3170 109:204 JLINK_WriteReg(XPSR, 0x01000000) returns 0x00 (0000ms, 38519ms total) +T3170 109:204 JLINK_WriteReg(MSP, 0x20001000) returns 0x00 (0000ms, 38519ms total) +T3170 109:204 JLINK_WriteReg(PSP, 0x20001000) returns 0x00 (0000ms, 38519ms total) +T3170 109:204 JLINK_WriteReg(CFBP, 0x00000000) returns 0x00 (0000ms, 38519ms total) +T3170 109:204 JLINK_SetBPEx(Addr = 0x20000000, Type = 0xFFFFFFF2) returns 0x000000F3 (0000ms, 38519ms total) +T3170 109:204 JLINK_Go() -- CPU_ReadMem(4 bytes @ 0xE0001000) (0006ms, 38525ms total) +T3170 109:210 JLINK_IsHalted() -- CPU_ReadMem(2 bytes @ 0x20000000) returns TRUE (0015ms, 38540ms total) +T3170 109:225 JLINK_ReadReg(R15 (PC)) returns 0x20000000 (0000ms, 38525ms total) +T3170 109:225 JLINK_ClrBPEx(BPHandle = 0x000000F3) returns 0x00 (0000ms, 38525ms total) +T3170 109:225 JLINK_ReadReg(R0) returns 0x00001F00 (0000ms, 38525ms total) +T3170 109:225 JLINK_WriteMem(0x20000144, 0x0080 Bytes, ...) - Data: 01 F1 30 00 07 21 FF F7 2F FB 21 68 01 F1 38 00 ... -- CPU_WriteMem(128 bytes @ 0x20000144) returns 0x80 (0076ms, 38601ms total) +T3170 109:301 JLINK_WriteReg(R0, 0x00001F00) returns 0x00 (0000ms, 38601ms total) +T3170 109:301 JLINK_WriteReg(R1, 0x00000080) returns 0x00 (0000ms, 38601ms total) +T3170 109:301 JLINK_WriteReg(R2, 0x20000144) returns 0x00 (0000ms, 38601ms total) +T3170 109:301 JLINK_WriteReg(R3, 0x00000000) returns 0x00 (0000ms, 38601ms total) +T3170 109:301 JLINK_WriteReg(R4, 0x00000000) returns 0x00 (0000ms, 38601ms total) +T3170 109:301 JLINK_WriteReg(R5, 0x00000000) returns 0x00 (0000ms, 38601ms total) +T3170 109:301 JLINK_WriteReg(R6, 0x00000000) returns 0x00 (0001ms, 38602ms total) +T3170 109:302 JLINK_WriteReg(R7, 0x00000000) returns 0x00 (0000ms, 38602ms total) +T3170 109:302 JLINK_WriteReg(R8, 0x00000000) returns 0x00 (0000ms, 38602ms total) +T3170 109:302 JLINK_WriteReg(R9, 0x2000013C) returns 0x00 (0000ms, 38602ms total) +T3170 109:302 JLINK_WriteReg(R10, 0x00000000) returns 0x00 (0000ms, 38602ms total) +T3170 109:302 JLINK_WriteReg(R11, 0x00000000) returns 0x00 (0000ms, 38602ms total) +T3170 109:302 JLINK_WriteReg(R12, 0x00000000) returns 0x00 (0000ms, 38602ms total) +T3170 109:302 JLINK_WriteReg(R13 (SP), 0x20001000) returns 0x00 (0000ms, 38602ms total) +T3170 109:302 JLINK_WriteReg(R14, 0x20000001) returns 0x00 (0000ms, 38602ms total) +T3170 109:302 JLINK_WriteReg(R15 (PC), 0x20000104) returns 0x00 (0000ms, 38602ms total) +T3170 109:302 JLINK_WriteReg(XPSR, 0x01000000) returns 0x00 (0000ms, 38602ms total) +T3170 109:302 JLINK_WriteReg(MSP, 0x20001000) returns 0x00 (0000ms, 38602ms total) +T3170 109:302 JLINK_WriteReg(PSP, 0x20001000) returns 0x00 (0000ms, 38602ms total) +T3170 109:302 JLINK_WriteReg(CFBP, 0x00000000) returns 0x00 (0000ms, 38602ms total) +T3170 109:302 JLINK_SetBPEx(Addr = 0x20000000, Type = 0xFFFFFFF2) returns 0x000000F4 (0000ms, 38602ms total) +T3170 109:302 JLINK_Go() -- CPU_ReadMem(4 bytes @ 0xE0001000) (0006ms, 38608ms total) +T3170 109:308 JLINK_IsHalted() -- CPU_ReadMem(2 bytes @ 0x20000000) returns TRUE (0006ms, 38614ms total) +T3170 109:314 JLINK_ReadReg(R15 (PC)) returns 0x20000000 (0000ms, 38608ms total) +T3170 109:314 JLINK_ClrBPEx(BPHandle = 0x000000F4) returns 0x00 (0000ms, 38608ms total) +T3170 109:314 JLINK_ReadReg(R0) returns 0x00001F80 (0000ms, 38608ms total) +T3170 109:314 JLINK_WriteMem(0x20000144, 0x0080 Bytes, ...) - Data: 00 00 00 00 28 74 68 69 73 5F 75 61 72 74 20 3D ... -- CPU_WriteMem(128 bytes @ 0x20000144) returns 0x80 (0003ms, 38611ms total) +T3170 109:317 JLINK_WriteReg(R0, 0x00001F80) returns 0x00 (0000ms, 38611ms total) +T3170 109:317 JLINK_WriteReg(R1, 0x00000080) returns 0x00 (0000ms, 38611ms total) +T3170 109:317 JLINK_WriteReg(R2, 0x20000144) returns 0x00 (0000ms, 38611ms total) +T3170 109:317 JLINK_WriteReg(R3, 0x00000000) returns 0x00 (0000ms, 38611ms total) +T3170 109:317 JLINK_WriteReg(R4, 0x00000000) returns 0x00 (0000ms, 38611ms total) +T3170 109:317 JLINK_WriteReg(R5, 0x00000000) returns 0x00 (0000ms, 38611ms total) +T3170 109:317 JLINK_WriteReg(R6, 0x00000000) returns 0x00 (0000ms, 38611ms total) +T3170 109:317 JLINK_WriteReg(R7, 0x00000000) returns 0x00 (0000ms, 38611ms total) +T3170 109:317 JLINK_WriteReg(R8, 0x00000000) returns 0x00 (0000ms, 38611ms total) +T3170 109:317 JLINK_WriteReg(R9, 0x2000013C) returns 0x00 (0000ms, 38611ms total) +T3170 109:317 JLINK_WriteReg(R10, 0x00000000) returns 0x00 (0000ms, 38611ms total) +T3170 109:317 JLINK_WriteReg(R11, 0x00000000) returns 0x00 (0000ms, 38611ms total) +T3170 109:317 JLINK_WriteReg(R12, 0x00000000) returns 0x00 (0000ms, 38611ms total) +T3170 109:317 JLINK_WriteReg(R13 (SP), 0x20001000) returns 0x00 (0000ms, 38611ms total) +T3170 109:317 JLINK_WriteReg(R14, 0x20000001) returns 0x00 (0000ms, 38611ms total) +T3170 109:317 JLINK_WriteReg(R15 (PC), 0x20000104) returns 0x00 (0000ms, 38611ms total) +T3170 109:317 JLINK_WriteReg(XPSR, 0x01000000) returns 0x00 (0000ms, 38611ms total) +T3170 109:317 JLINK_WriteReg(MSP, 0x20001000) returns 0x00 (0000ms, 38611ms total) +T3170 109:317 JLINK_WriteReg(PSP, 0x20001000) returns 0x00 (0000ms, 38611ms total) +T3170 109:317 JLINK_WriteReg(CFBP, 0x00000000) returns 0x00 (0001ms, 38612ms total) +T3170 109:318 JLINK_SetBPEx(Addr = 0x20000000, Type = 0xFFFFFFF2) returns 0x000000F5 (0000ms, 38612ms total) +T3170 109:318 JLINK_Go() -- CPU_ReadMem(4 bytes @ 0xE0001000) (0087ms, 38699ms total) +T3170 109:405 JLINK_IsHalted() -- CPU_ReadMem(2 bytes @ 0x20000000) returns TRUE (0005ms, 38704ms total) +T3170 109:410 JLINK_ReadReg(R15 (PC)) returns 0x20000000 (0000ms, 38699ms total) +T3170 109:410 JLINK_ClrBPEx(BPHandle = 0x000000F5) returns 0x00 (0000ms, 38699ms total) +T3170 109:410 JLINK_ReadReg(R0) returns 0x00002000 (0000ms, 38699ms total) +T3170 109:411 JLINK_WriteMem(0x20000144, 0x0080 Bytes, ...) - Data: 00 88 08 B1 02 F0 BA FD 04 48 00 68 00 F0 00 40 ... -- CPU_WriteMem(128 bytes @ 0x20000144) returns 0x80 (0003ms, 38702ms total) +T3170 109:414 JLINK_WriteReg(R0, 0x00002000) returns 0x00 (0000ms, 38702ms total) +T3170 109:414 JLINK_WriteReg(R1, 0x00000080) returns 0x00 (0000ms, 38702ms total) +T3170 109:414 JLINK_WriteReg(R2, 0x20000144) returns 0x00 (0000ms, 38702ms total) +T3170 109:414 JLINK_WriteReg(R3, 0x00000000) returns 0x00 (0000ms, 38702ms total) +T3170 109:414 JLINK_WriteReg(R4, 0x00000000) returns 0x00 (0000ms, 38702ms total) +T3170 109:414 JLINK_WriteReg(R5, 0x00000000) returns 0x00 (0000ms, 38702ms total) +T3170 109:414 JLINK_WriteReg(R6, 0x00000000) returns 0x00 (0000ms, 38702ms total) +T3170 109:414 JLINK_WriteReg(R7, 0x00000000) returns 0x00 (0000ms, 38702ms total) +T3170 109:414 JLINK_WriteReg(R8, 0x00000000) returns 0x00 (0000ms, 38702ms total) +T3170 109:414 JLINK_WriteReg(R9, 0x2000013C) returns 0x00 (0000ms, 38702ms total) +T3170 109:414 JLINK_WriteReg(R10, 0x00000000) returns 0x00 (0000ms, 38702ms total) +T3170 109:414 JLINK_WriteReg(R11, 0x00000000) returns 0x00 (0000ms, 38702ms total) +T3170 109:414 JLINK_WriteReg(R12, 0x00000000) returns 0x00 (0000ms, 38702ms total) +T3170 109:414 JLINK_WriteReg(R13 (SP), 0x20001000) returns 0x00 (0000ms, 38702ms total) +T3170 109:414 JLINK_WriteReg(R14, 0x20000001) returns 0x00 (0000ms, 38702ms total) +T3170 109:414 JLINK_WriteReg(R15 (PC), 0x20000104) returns 0x00 (0000ms, 38702ms total) +T3170 109:414 JLINK_WriteReg(XPSR, 0x01000000) returns 0x00 (0000ms, 38702ms total) +T3170 109:414 JLINK_WriteReg(MSP, 0x20001000) returns 0x00 (0000ms, 38702ms total) +T3170 109:414 JLINK_WriteReg(PSP, 0x20001000) returns 0x00 (0000ms, 38702ms total) +T3170 109:414 JLINK_WriteReg(CFBP, 0x00000000) returns 0x00 (0000ms, 38702ms total) +T3170 109:414 JLINK_SetBPEx(Addr = 0x20000000, Type = 0xFFFFFFF2) returns 0x000000F6 (0000ms, 38702ms total) +T3170 109:414 JLINK_Go() -- CPU_ReadMem(4 bytes @ 0xE0001000) (0089ms, 38791ms total) +T3170 109:503 JLINK_IsHalted() -- CPU_ReadMem(2 bytes @ 0x20000000) returns TRUE (0009ms, 38800ms total) +T3170 109:512 JLINK_ReadReg(R15 (PC)) returns 0x20000000 (0000ms, 38791ms total) +T3170 109:512 JLINK_ClrBPEx(BPHandle = 0x000000F6) returns 0x00 (0000ms, 38791ms total) +T3170 109:512 JLINK_ReadReg(R0) returns 0x00002080 (0000ms, 38791ms total) +T3170 109:512 JLINK_WriteMem(0x20000144, 0x0080 Bytes, ...) - Data: 00 B9 04 E0 0C A0 21 68 01 F0 6A FB 00 BF 08 34 ... -- CPU_WriteMem(128 bytes @ 0x20000144) returns 0x80 (0004ms, 38795ms total) +T3170 109:516 JLINK_WriteReg(R0, 0x00002080) returns 0x00 (0000ms, 38795ms total) +T3170 109:516 JLINK_WriteReg(R1, 0x00000080) returns 0x00 (0000ms, 38795ms total) +T3170 109:516 JLINK_WriteReg(R2, 0x20000144) returns 0x00 (0000ms, 38795ms total) +T3170 109:516 JLINK_WriteReg(R3, 0x00000000) returns 0x00 (0000ms, 38795ms total) +T3170 109:516 JLINK_WriteReg(R4, 0x00000000) returns 0x00 (0000ms, 38795ms total) +T3170 109:516 JLINK_WriteReg(R5, 0x00000000) returns 0x00 (0000ms, 38795ms total) +T3170 109:516 JLINK_WriteReg(R6, 0x00000000) returns 0x00 (0000ms, 38795ms total) +T3170 109:516 JLINK_WriteReg(R7, 0x00000000) returns 0x00 (0000ms, 38795ms total) +T3170 109:516 JLINK_WriteReg(R8, 0x00000000) returns 0x00 (0000ms, 38795ms total) +T3170 109:516 JLINK_WriteReg(R9, 0x2000013C) returns 0x00 (0000ms, 38795ms total) +T3170 109:516 JLINK_WriteReg(R10, 0x00000000) returns 0x00 (0000ms, 38795ms total) +T3170 109:516 JLINK_WriteReg(R11, 0x00000000) returns 0x00 (0000ms, 38795ms total) +T3170 109:516 JLINK_WriteReg(R12, 0x00000000) returns 0x00 (0000ms, 38795ms total) +T3170 109:516 JLINK_WriteReg(R13 (SP), 0x20001000) returns 0x00 (0000ms, 38795ms total) +T3170 109:516 JLINK_WriteReg(R14, 0x20000001) returns 0x00 (0000ms, 38795ms total) +T3170 109:516 JLINK_WriteReg(R15 (PC), 0x20000104) returns 0x00 (0000ms, 38795ms total) +T3170 109:517 JLINK_WriteReg(XPSR, 0x01000000) returns 0x00 (0000ms, 38795ms total) +T3170 109:517 JLINK_WriteReg(MSP, 0x20001000) returns 0x00 (0000ms, 38795ms total) +T3170 109:517 JLINK_WriteReg(PSP, 0x20001000) returns 0x00 (0000ms, 38795ms total) +T3170 109:517 JLINK_WriteReg(CFBP, 0x00000000) returns 0x00 (0000ms, 38795ms total) +T3170 109:517 JLINK_SetBPEx(Addr = 0x20000000, Type = 0xFFFFFFF2) returns 0x000000F7 (0000ms, 38795ms total) +T3170 109:517 JLINK_Go() -- CPU_ReadMem(4 bytes @ 0xE0001000) (0084ms, 38879ms total) +T3170 109:602 JLINK_IsHalted() -- CPU_ReadMem(2 bytes @ 0x20000000) returns TRUE (0008ms, 38887ms total) +T3170 109:610 JLINK_ReadReg(R15 (PC)) returns 0x20000000 (0000ms, 38879ms total) +T3170 109:610 JLINK_ClrBPEx(BPHandle = 0x000000F7) returns 0x00 (0000ms, 38879ms total) +T3170 109:610 JLINK_ReadReg(R0) returns 0x00002100 (0000ms, 38879ms total) +T3170 109:610 JLINK_WriteMem(0x20000144, 0x0080 Bytes, ...) - Data: 3B E0 02 A8 50 F8 25 00 A0 F1 0C 06 FE F7 2C F9 ... -- CPU_WriteMem(128 bytes @ 0x20000144) returns 0x80 (0004ms, 38883ms total) +T3170 109:614 JLINK_WriteReg(R0, 0x00002100) returns 0x00 (0000ms, 38883ms total) +T3170 109:614 JLINK_WriteReg(R1, 0x00000080) returns 0x00 (0000ms, 38883ms total) +T3170 109:614 JLINK_WriteReg(R2, 0x20000144) returns 0x00 (0000ms, 38883ms total) +T3170 109:614 JLINK_WriteReg(R3, 0x00000000) returns 0x00 (0000ms, 38883ms total) +T3170 109:614 JLINK_WriteReg(R4, 0x00000000) returns 0x00 (0000ms, 38883ms total) +T3170 109:614 JLINK_WriteReg(R5, 0x00000000) returns 0x00 (0000ms, 38883ms total) +T3170 109:614 JLINK_WriteReg(R6, 0x00000000) returns 0x00 (0000ms, 38883ms total) +T3170 109:614 JLINK_WriteReg(R7, 0x00000000) returns 0x00 (0000ms, 38883ms total) +T3170 109:614 JLINK_WriteReg(R8, 0x00000000) returns 0x00 (0000ms, 38883ms total) +T3170 109:614 JLINK_WriteReg(R9, 0x2000013C) returns 0x00 (0000ms, 38883ms total) +T3170 109:614 JLINK_WriteReg(R10, 0x00000000) returns 0x00 (0000ms, 38883ms total) +T3170 109:614 JLINK_WriteReg(R11, 0x00000000) returns 0x00 (0000ms, 38883ms total) +T3170 109:614 JLINK_WriteReg(R12, 0x00000000) returns 0x00 (0000ms, 38883ms total) +T3170 109:614 JLINK_WriteReg(R13 (SP), 0x20001000) returns 0x00 (0000ms, 38883ms total) +T3170 109:614 JLINK_WriteReg(R14, 0x20000001) returns 0x00 (0000ms, 38883ms total) +T3170 109:614 JLINK_WriteReg(R15 (PC), 0x20000104) returns 0x00 (0000ms, 38883ms total) +T3170 109:614 JLINK_WriteReg(XPSR, 0x01000000) returns 0x00 (0000ms, 38883ms total) +T3170 109:614 JLINK_WriteReg(MSP, 0x20001000) returns 0x00 (0000ms, 38883ms total) +T3170 109:614 JLINK_WriteReg(PSP, 0x20001000) returns 0x00 (0000ms, 38883ms total) +T3170 109:614 JLINK_WriteReg(CFBP, 0x00000000) returns 0x00 (0000ms, 38883ms total) +T3170 109:614 JLINK_SetBPEx(Addr = 0x20000000, Type = 0xFFFFFFF2) returns 0x000000F8 (0000ms, 38883ms total) +T3170 109:614 JLINK_Go() -- CPU_ReadMem(4 bytes @ 0xE0001000) (0087ms, 38970ms total) +T3170 109:701 JLINK_IsHalted() -- CPU_ReadMem(2 bytes @ 0x20000000) returns TRUE (0009ms, 38979ms total) +T3170 109:710 JLINK_ReadReg(R15 (PC)) returns 0x20000000 (0000ms, 38970ms total) +T3170 109:710 JLINK_ClrBPEx(BPHandle = 0x000000F8) returns 0x00 (0000ms, 38970ms total) +T3170 109:710 JLINK_ReadReg(R0) returns 0x00002180 (0000ms, 38970ms total) +T3170 109:710 JLINK_WriteMem(0x20000144, 0x0080 Bytes, ...) - Data: 00 2F B7 D1 00 20 0F B0 BD E8 F0 8F 65 76 65 6E ... -- CPU_WriteMem(128 bytes @ 0x20000144) returns 0x80 (0004ms, 38974ms total) +T3170 109:714 JLINK_WriteReg(R0, 0x00002180) returns 0x00 (0000ms, 38974ms total) +T3170 109:714 JLINK_WriteReg(R1, 0x00000080) returns 0x00 (0000ms, 38974ms total) +T3170 109:714 JLINK_WriteReg(R2, 0x20000144) returns 0x00 (0000ms, 38974ms total) +T3170 109:714 JLINK_WriteReg(R3, 0x00000000) returns 0x00 (0000ms, 38974ms total) +T3170 109:714 JLINK_WriteReg(R4, 0x00000000) returns 0x00 (0000ms, 38974ms total) +T3170 109:714 JLINK_WriteReg(R5, 0x00000000) returns 0x00 (0000ms, 38974ms total) +T3170 109:714 JLINK_WriteReg(R6, 0x00000000) returns 0x00 (0000ms, 38974ms total) +T3170 109:714 JLINK_WriteReg(R7, 0x00000000) returns 0x00 (0000ms, 38974ms total) +T3170 109:714 JLINK_WriteReg(R8, 0x00000000) returns 0x00 (0000ms, 38974ms total) +T3170 109:714 JLINK_WriteReg(R9, 0x2000013C) returns 0x00 (0000ms, 38974ms total) +T3170 109:714 JLINK_WriteReg(R10, 0x00000000) returns 0x00 (0000ms, 38974ms total) +T3170 109:714 JLINK_WriteReg(R11, 0x00000000) returns 0x00 (0000ms, 38974ms total) +T3170 109:714 JLINK_WriteReg(R12, 0x00000000) returns 0x00 (0000ms, 38974ms total) +T3170 109:714 JLINK_WriteReg(R13 (SP), 0x20001000) returns 0x00 (0000ms, 38974ms total) +T3170 109:714 JLINK_WriteReg(R14, 0x20000001) returns 0x00 (0000ms, 38974ms total) +T3170 109:714 JLINK_WriteReg(R15 (PC), 0x20000104) returns 0x00 (0000ms, 38974ms total) +T3170 109:714 JLINK_WriteReg(XPSR, 0x01000000) returns 0x00 (0000ms, 38974ms total) +T3170 109:714 JLINK_WriteReg(MSP, 0x20001000) returns 0x00 (0000ms, 38974ms total) +T3170 109:714 JLINK_WriteReg(PSP, 0x20001000) returns 0x00 (0000ms, 38974ms total) +T3170 109:714 JLINK_WriteReg(CFBP, 0x00000000) returns 0x00 (0000ms, 38974ms total) +T3170 109:714 JLINK_SetBPEx(Addr = 0x20000000, Type = 0xFFFFFFF2) returns 0x000000F9 (0000ms, 38974ms total) +T3170 109:714 JLINK_Go() -- CPU_ReadMem(4 bytes @ 0xE0001000) (0087ms, 39061ms total) +T3170 109:801 JLINK_IsHalted() -- CPU_ReadMem(2 bytes @ 0x20000000) returns TRUE (0009ms, 39070ms total) +T3170 109:811 JLINK_ReadReg(R15 (PC)) returns 0x20000000 (0000ms, 39061ms total) +T3170 109:811 JLINK_ClrBPEx(BPHandle = 0x000000F9) returns 0x00 (0000ms, 39061ms total) +T3170 109:811 JLINK_ReadReg(R0) returns 0x00002200 (0000ms, 39061ms total) +T3170 109:811 JLINK_WriteMem(0x20000144, 0x0080 Bytes, ...) - Data: 0A 00 00 00 2D E9 F0 47 04 46 0D 46 16 46 1F 46 ... -- CPU_WriteMem(128 bytes @ 0x20000144) returns 0x80 (0003ms, 39064ms total) +T3170 109:814 JLINK_WriteReg(R0, 0x00002200) returns 0x00 (0000ms, 39064ms total) +T3170 109:814 JLINK_WriteReg(R1, 0x00000080) returns 0x00 (0000ms, 39064ms total) +T3170 109:814 JLINK_WriteReg(R2, 0x20000144) returns 0x00 (0000ms, 39064ms total) +T3170 109:814 JLINK_WriteReg(R3, 0x00000000) returns 0x00 (0000ms, 39064ms total) +T3170 109:814 JLINK_WriteReg(R4, 0x00000000) returns 0x00 (0000ms, 39064ms total) +T3170 109:814 JLINK_WriteReg(R5, 0x00000000) returns 0x00 (0000ms, 39064ms total) +T3170 109:814 JLINK_WriteReg(R6, 0x00000000) returns 0x00 (0001ms, 39065ms total) +T3170 109:815 JLINK_WriteReg(R7, 0x00000000) returns 0x00 (0000ms, 39065ms total) +T3170 109:815 JLINK_WriteReg(R8, 0x00000000) returns 0x00 (0000ms, 39065ms total) +T3170 109:815 JLINK_WriteReg(R9, 0x2000013C) returns 0x00 (0000ms, 39065ms total) +T3170 109:815 JLINK_WriteReg(R10, 0x00000000) returns 0x00 (0000ms, 39065ms total) +T3170 109:815 JLINK_WriteReg(R11, 0x00000000) returns 0x00 (0000ms, 39065ms total) +T3170 109:815 JLINK_WriteReg(R12, 0x00000000) returns 0x00 (0000ms, 39065ms total) +T3170 109:815 JLINK_WriteReg(R13 (SP), 0x20001000) returns 0x00 (0000ms, 39065ms total) +T3170 109:815 JLINK_WriteReg(R14, 0x20000001) returns 0x00 (0000ms, 39065ms total) +T3170 109:815 JLINK_WriteReg(R15 (PC), 0x20000104) returns 0x00 (0000ms, 39065ms total) +T3170 109:815 JLINK_WriteReg(XPSR, 0x01000000) returns 0x00 (0000ms, 39065ms total) +T3170 109:815 JLINK_WriteReg(MSP, 0x20001000) returns 0x00 (0000ms, 39065ms total) +T3170 109:815 JLINK_WriteReg(PSP, 0x20001000) returns 0x00 (0000ms, 39065ms total) +T3170 109:815 JLINK_WriteReg(CFBP, 0x00000000) returns 0x00 (0000ms, 39065ms total) +T3170 109:815 JLINK_SetBPEx(Addr = 0x20000000, Type = 0xFFFFFFF2) returns 0x000000FA (0000ms, 39065ms total) +T3170 109:815 JLINK_Go() -- CPU_ReadMem(4 bytes @ 0xE0001000) (0088ms, 39153ms total) +T3170 109:904 JLINK_IsHalted() -- CPU_ReadMem(2 bytes @ 0x20000000) returns TRUE (0007ms, 39160ms total) +T3170 109:911 JLINK_ReadReg(R15 (PC)) returns 0x20000000 (0000ms, 39153ms total) +T3170 109:911 JLINK_ClrBPEx(BPHandle = 0x000000FA) returns 0x00 (0000ms, 39153ms total) +T3170 109:911 JLINK_ReadReg(R0) returns 0x00002280 (0000ms, 39153ms total) +T3170 109:911 JLINK_WriteMem(0x20000144, 0x0080 Bytes, ...) - Data: 00 20 E1 E7 00 BF 00 26 D4 F8 04 90 0B E0 2D 68 ... -- CPU_WriteMem(128 bytes @ 0x20000144) returns 0x80 (0003ms, 39156ms total) +T3170 109:914 JLINK_WriteReg(R0, 0x00002280) returns 0x00 (0000ms, 39156ms total) +T3170 109:914 JLINK_WriteReg(R1, 0x00000080) returns 0x00 (0000ms, 39156ms total) +T3170 109:914 JLINK_WriteReg(R2, 0x20000144) returns 0x00 (0000ms, 39156ms total) +T3170 109:914 JLINK_WriteReg(R3, 0x00000000) returns 0x00 (0000ms, 39156ms total) +T3170 109:914 JLINK_WriteReg(R4, 0x00000000) returns 0x00 (0000ms, 39156ms total) +T3170 109:914 JLINK_WriteReg(R5, 0x00000000) returns 0x00 (0000ms, 39156ms total) +T3170 109:914 JLINK_WriteReg(R6, 0x00000000) returns 0x00 (0000ms, 39156ms total) +T3170 109:914 JLINK_WriteReg(R7, 0x00000000) returns 0x00 (0000ms, 39156ms total) +T3170 109:914 JLINK_WriteReg(R8, 0x00000000) returns 0x00 (0000ms, 39156ms total) +T3170 109:914 JLINK_WriteReg(R9, 0x2000013C) returns 0x00 (0000ms, 39156ms total) +T3170 109:914 JLINK_WriteReg(R10, 0x00000000) returns 0x00 (0000ms, 39156ms total) +T3170 109:914 JLINK_WriteReg(R11, 0x00000000) returns 0x00 (0000ms, 39156ms total) +T3170 109:914 JLINK_WriteReg(R12, 0x00000000) returns 0x00 (0000ms, 39156ms total) +T3170 109:914 JLINK_WriteReg(R13 (SP), 0x20001000) returns 0x00 (0000ms, 39156ms total) +T3170 109:914 JLINK_WriteReg(R14, 0x20000001) returns 0x00 (0000ms, 39156ms total) +T3170 109:914 JLINK_WriteReg(R15 (PC), 0x20000104) returns 0x00 (0000ms, 39156ms total) +T3170 109:914 JLINK_WriteReg(XPSR, 0x01000000) returns 0x00 (0000ms, 39156ms total) +T3170 109:914 JLINK_WriteReg(MSP, 0x20001000) returns 0x00 (0000ms, 39156ms total) +T3170 109:914 JLINK_WriteReg(PSP, 0x20001000) returns 0x00 (0000ms, 39156ms total) +T3170 109:914 JLINK_WriteReg(CFBP, 0x00000000) returns 0x00 (0000ms, 39156ms total) +T3170 109:914 JLINK_SetBPEx(Addr = 0x20000000, Type = 0xFFFFFFF2) returns 0x000000FB (0000ms, 39156ms total) +T3170 109:914 JLINK_Go() -- CPU_ReadMem(4 bytes @ 0xE0001000) (0089ms, 39245ms total) +T3170 110:003 JLINK_IsHalted() -- CPU_ReadMem(2 bytes @ 0x20000000) returns TRUE (0009ms, 39254ms total) +T3170 110:012 JLINK_ReadReg(R15 (PC)) returns 0x20000000 (0000ms, 39245ms total) +T3170 110:012 JLINK_ClrBPEx(BPHandle = 0x000000FB) returns 0x00 (0000ms, 39245ms total) +T3170 110:012 JLINK_ReadReg(R0) returns 0x00002300 (0000ms, 39245ms total) +T3170 110:012 JLINK_WriteMem(0x20000144, 0x0080 Bytes, ...) - Data: A0 F1 0C 06 FE F7 30 F8 83 46 30 7A 20 F0 80 00 ... -- CPU_WriteMem(128 bytes @ 0x20000144) returns 0x80 (0004ms, 39249ms total) +T3170 110:016 JLINK_WriteReg(R0, 0x00002300) returns 0x00 (0000ms, 39249ms total) +T3170 110:016 JLINK_WriteReg(R1, 0x00000080) returns 0x00 (0000ms, 39249ms total) +T3170 110:016 JLINK_WriteReg(R2, 0x20000144) returns 0x00 (0000ms, 39249ms total) +T3170 110:016 JLINK_WriteReg(R3, 0x00000000) returns 0x00 (0000ms, 39249ms total) +T3170 110:016 JLINK_WriteReg(R4, 0x00000000) returns 0x00 (0000ms, 39249ms total) +T3170 110:016 JLINK_WriteReg(R5, 0x00000000) returns 0x00 (0000ms, 39249ms total) +T3170 110:016 JLINK_WriteReg(R6, 0x00000000) returns 0x00 (0000ms, 39249ms total) +T3170 110:016 JLINK_WriteReg(R7, 0x00000000) returns 0x00 (0000ms, 39249ms total) +T3170 110:016 JLINK_WriteReg(R8, 0x00000000) returns 0x00 (0000ms, 39249ms total) +T3170 110:016 JLINK_WriteReg(R9, 0x2000013C) returns 0x00 (0001ms, 39250ms total) +T3170 110:017 JLINK_WriteReg(R10, 0x00000000) returns 0x00 (0000ms, 39250ms total) +T3170 110:017 JLINK_WriteReg(R11, 0x00000000) returns 0x00 (0000ms, 39250ms total) +T3170 110:017 JLINK_WriteReg(R12, 0x00000000) returns 0x00 (0000ms, 39250ms total) +T3170 110:017 JLINK_WriteReg(R13 (SP), 0x20001000) returns 0x00 (0000ms, 39250ms total) +T3170 110:017 JLINK_WriteReg(R14, 0x20000001) returns 0x00 (0000ms, 39250ms total) +T3170 110:017 JLINK_WriteReg(R15 (PC), 0x20000104) returns 0x00 (0000ms, 39250ms total) +T3170 110:017 JLINK_WriteReg(XPSR, 0x01000000) returns 0x00 (0000ms, 39250ms total) +T3170 110:017 JLINK_WriteReg(MSP, 0x20001000) returns 0x00 (0000ms, 39250ms total) +T3170 110:017 JLINK_WriteReg(PSP, 0x20001000) returns 0x00 (0000ms, 39250ms total) +T3170 110:017 JLINK_WriteReg(CFBP, 0x00000000) returns 0x00 (0000ms, 39250ms total) +T3170 110:017 JLINK_SetBPEx(Addr = 0x20000000, Type = 0xFFFFFFF2) returns 0x000000FC (0000ms, 39250ms total) +T3170 110:017 JLINK_Go() -- CPU_ReadMem(4 bytes @ 0xE0001000) (0084ms, 39334ms total) +T3170 110:102 JLINK_IsHalted() -- CPU_ReadMem(2 bytes @ 0x20000000) returns TRUE (0006ms, 39340ms total) +T3170 110:108 JLINK_ReadReg(R15 (PC)) returns 0x20000000 (0000ms, 39334ms total) +T3170 110:108 JLINK_ClrBPEx(BPHandle = 0x000000FC) returns 0x00 (0000ms, 39334ms total) +T3170 110:108 JLINK_ReadReg(R0) returns 0x00002380 (0000ms, 39334ms total) +T3170 110:108 JLINK_WriteMem(0x20000144, 0x0080 Bytes, ...) - Data: EF F9 00 BF 6D 1C 10 98 A8 42 B6 DC 00 2F AD D1 ... -- CPU_WriteMem(128 bytes @ 0x20000144) returns 0x80 (0003ms, 39337ms total) +T3170 110:111 JLINK_WriteReg(R0, 0x00002380) returns 0x00 (0000ms, 39337ms total) +T3170 110:111 JLINK_WriteReg(R1, 0x00000080) returns 0x00 (0000ms, 39337ms total) +T3170 110:111 JLINK_WriteReg(R2, 0x20000144) returns 0x00 (0000ms, 39337ms total) +T3170 110:111 JLINK_WriteReg(R3, 0x00000000) returns 0x00 (0000ms, 39337ms total) +T3170 110:111 JLINK_WriteReg(R4, 0x00000000) returns 0x00 (0000ms, 39337ms total) +T3170 110:111 JLINK_WriteReg(R5, 0x00000000) returns 0x00 (0000ms, 39337ms total) +T3170 110:111 JLINK_WriteReg(R6, 0x00000000) returns 0x00 (0000ms, 39337ms total) +T3170 110:111 JLINK_WriteReg(R7, 0x00000000) returns 0x00 (0000ms, 39337ms total) +T3170 110:111 JLINK_WriteReg(R8, 0x00000000) returns 0x00 (0000ms, 39337ms total) +T3170 110:111 JLINK_WriteReg(R9, 0x2000013C) returns 0x00 (0000ms, 39337ms total) +T3170 110:111 JLINK_WriteReg(R10, 0x00000000) returns 0x00 (0000ms, 39337ms total) +T3170 110:111 JLINK_WriteReg(R11, 0x00000000) returns 0x00 (0000ms, 39337ms total) +T3170 110:111 JLINK_WriteReg(R12, 0x00000000) returns 0x00 (0000ms, 39337ms total) +T3170 110:111 JLINK_WriteReg(R13 (SP), 0x20001000) returns 0x00 (0000ms, 39337ms total) +T3170 110:111 JLINK_WriteReg(R14, 0x20000001) returns 0x00 (0000ms, 39337ms total) +T3170 110:111 JLINK_WriteReg(R15 (PC), 0x20000104) returns 0x00 (0000ms, 39337ms total) +T3170 110:111 JLINK_WriteReg(XPSR, 0x01000000) returns 0x00 (0000ms, 39337ms total) +T3170 110:111 JLINK_WriteReg(MSP, 0x20001000) returns 0x00 (0000ms, 39337ms total) +T3170 110:111 JLINK_WriteReg(PSP, 0x20001000) returns 0x00 (0000ms, 39337ms total) +T3170 110:111 JLINK_WriteReg(CFBP, 0x00000000) returns 0x00 (0000ms, 39337ms total) +T3170 110:111 JLINK_SetBPEx(Addr = 0x20000000, Type = 0xFFFFFFF2) returns 0x000000FD (0000ms, 39337ms total) +T3170 110:111 JLINK_Go() -- CPU_ReadMem(4 bytes @ 0xE0001000) (0089ms, 39426ms total) +T3170 110:200 JLINK_IsHalted() -- CPU_ReadMem(2 bytes @ 0x20000000) returns TRUE (0008ms, 39434ms total) +T3170 110:208 JLINK_ReadReg(R15 (PC)) returns 0x20000000 (0000ms, 39426ms total) +T3170 110:208 JLINK_ClrBPEx(BPHandle = 0x000000FD) returns 0x00 (0000ms, 39426ms total) +T3170 110:208 JLINK_ReadReg(R0) returns 0x00002400 (0000ms, 39426ms total) +T3170 110:208 JLINK_WriteMem(0x20000144, 0x0080 Bytes, ...) - Data: 2A 73 20 25 30 34 64 20 20 25 30 34 64 20 25 64 ... -- CPU_WriteMem(128 bytes @ 0x20000144) returns 0x80 (0004ms, 39430ms total) +T3170 110:212 JLINK_WriteReg(R0, 0x00002400) returns 0x00 (0000ms, 39430ms total) +T3170 110:212 JLINK_WriteReg(R1, 0x00000080) returns 0x00 (0000ms, 39430ms total) +T3170 110:212 JLINK_WriteReg(R2, 0x20000144) returns 0x00 (0000ms, 39430ms total) +T3170 110:212 JLINK_WriteReg(R3, 0x00000000) returns 0x00 (0000ms, 39430ms total) +T3170 110:212 JLINK_WriteReg(R4, 0x00000000) returns 0x00 (0000ms, 39430ms total) +T3170 110:212 JLINK_WriteReg(R5, 0x00000000) returns 0x00 (0000ms, 39430ms total) +T3170 110:212 JLINK_WriteReg(R6, 0x00000000) returns 0x00 (0000ms, 39430ms total) +T3170 110:212 JLINK_WriteReg(R7, 0x00000000) returns 0x00 (0000ms, 39430ms total) +T3170 110:212 JLINK_WriteReg(R8, 0x00000000) returns 0x00 (0000ms, 39430ms total) +T3170 110:212 JLINK_WriteReg(R9, 0x2000013C) returns 0x00 (0000ms, 39430ms total) +T3170 110:212 JLINK_WriteReg(R10, 0x00000000) returns 0x00 (0000ms, 39430ms total) +T3170 110:212 JLINK_WriteReg(R11, 0x00000000) returns 0x00 (0000ms, 39430ms total) +T3170 110:212 JLINK_WriteReg(R12, 0x00000000) returns 0x00 (0000ms, 39430ms total) +T3170 110:212 JLINK_WriteReg(R13 (SP), 0x20001000) returns 0x00 (0000ms, 39430ms total) +T3170 110:212 JLINK_WriteReg(R14, 0x20000001) returns 0x00 (0000ms, 39430ms total) +T3170 110:213 JLINK_WriteReg(R15 (PC), 0x20000104) returns 0x00 (0000ms, 39430ms total) +T3170 110:213 JLINK_WriteReg(XPSR, 0x01000000) returns 0x00 (0000ms, 39430ms total) +T3170 110:213 JLINK_WriteReg(MSP, 0x20001000) returns 0x00 (0000ms, 39430ms total) +T3170 110:213 JLINK_WriteReg(PSP, 0x20001000) returns 0x00 (0000ms, 39430ms total) +T3170 110:213 JLINK_WriteReg(CFBP, 0x00000000) returns 0x00 (0000ms, 39430ms total) +T3170 110:213 JLINK_SetBPEx(Addr = 0x20000000, Type = 0xFFFFFFF2) returns 0x000000FE (0000ms, 39430ms total) +T3170 110:213 JLINK_Go() -- CPU_ReadMem(4 bytes @ 0xE0001000) (0090ms, 39520ms total) +T3170 110:303 JLINK_IsHalted() -- CPU_ReadMem(2 bytes @ 0x20000000) returns TRUE (0009ms, 39529ms total) +T3170 110:312 JLINK_ReadReg(R15 (PC)) returns 0x20000000 (0000ms, 39520ms total) +T3170 110:312 JLINK_ClrBPEx(BPHandle = 0x000000FE) returns 0x00 (0000ms, 39520ms total) +T3170 110:312 JLINK_ReadReg(R0) returns 0x00002480 (0000ms, 39520ms total) +T3170 110:312 JLINK_WriteMem(0x20000144, 0x0080 Bytes, ...) - Data: 6D 6F 72 79 3A 20 25 64 0A 00 00 00 2D E9 F0 4F ... -- CPU_WriteMem(128 bytes @ 0x20000144) returns 0x80 (0004ms, 39524ms total) +T3170 110:316 JLINK_WriteReg(R0, 0x00002480) returns 0x00 (0000ms, 39524ms total) +T3170 110:316 JLINK_WriteReg(R1, 0x00000080) returns 0x00 (0000ms, 39524ms total) +T3170 110:316 JLINK_WriteReg(R2, 0x20000144) returns 0x00 (0000ms, 39524ms total) +T3170 110:316 JLINK_WriteReg(R3, 0x00000000) returns 0x00 (0000ms, 39524ms total) +T3170 110:316 JLINK_WriteReg(R4, 0x00000000) returns 0x00 (0000ms, 39524ms total) +T3170 110:316 JLINK_WriteReg(R5, 0x00000000) returns 0x00 (0000ms, 39524ms total) +T3170 110:316 JLINK_WriteReg(R6, 0x00000000) returns 0x00 (0000ms, 39524ms total) +T3170 110:316 JLINK_WriteReg(R7, 0x00000000) returns 0x00 (0000ms, 39524ms total) +T3170 110:316 JLINK_WriteReg(R8, 0x00000000) returns 0x00 (0000ms, 39524ms total) +T3170 110:316 JLINK_WriteReg(R9, 0x2000013C) returns 0x00 (0000ms, 39524ms total) +T3170 110:316 JLINK_WriteReg(R10, 0x00000000) returns 0x00 (0000ms, 39524ms total) +T3170 110:316 JLINK_WriteReg(R11, 0x00000000) returns 0x00 (0000ms, 39524ms total) +T3170 110:316 JLINK_WriteReg(R12, 0x00000000) returns 0x00 (0000ms, 39524ms total) +T3170 110:316 JLINK_WriteReg(R13 (SP), 0x20001000) returns 0x00 (0000ms, 39524ms total) +T3170 110:316 JLINK_WriteReg(R14, 0x20000001) returns 0x00 (0000ms, 39524ms total) +T3170 110:316 JLINK_WriteReg(R15 (PC), 0x20000104) returns 0x00 (0000ms, 39524ms total) +T3170 110:316 JLINK_WriteReg(XPSR, 0x01000000) returns 0x00 (0000ms, 39524ms total) +T3170 110:316 JLINK_WriteReg(MSP, 0x20001000) returns 0x00 (0000ms, 39524ms total) +T3170 110:316 JLINK_WriteReg(PSP, 0x20001000) returns 0x00 (0000ms, 39524ms total) +T3170 110:316 JLINK_WriteReg(CFBP, 0x00000000) returns 0x00 (0000ms, 39524ms total) +T3170 110:316 JLINK_SetBPEx(Addr = 0x20000000, Type = 0xFFFFFFF2) returns 0x000000FF (0000ms, 39524ms total) +T3170 110:316 JLINK_Go() -- CPU_ReadMem(4 bytes @ 0xE0001000) (0090ms, 39614ms total) +T3170 110:406 JLINK_IsHalted() -- CPU_ReadMem(2 bytes @ 0x20000000) returns TRUE (0008ms, 39622ms total) +T3170 110:414 JLINK_ReadReg(R15 (PC)) returns 0x20000000 (0000ms, 39614ms total) +T3170 110:414 JLINK_ClrBPEx(BPHandle = 0x000000FF) returns 0x00 (0000ms, 39614ms total) +T3170 110:414 JLINK_ReadReg(R0) returns 0x00002500 (0000ms, 39614ms total) +T3170 110:414 JLINK_WriteMem(0x20000144, 0x0080 Bytes, ...) - Data: 01 F0 7B F9 A8 B9 04 F1 14 00 01 F0 7E F9 82 46 ... -- CPU_WriteMem(128 bytes @ 0x20000144) returns 0x80 (0003ms, 39617ms total) +T3170 110:417 JLINK_WriteReg(R0, 0x00002500) returns 0x00 (0000ms, 39617ms total) +T3170 110:417 JLINK_WriteReg(R1, 0x00000080) returns 0x00 (0000ms, 39617ms total) +T3170 110:417 JLINK_WriteReg(R2, 0x20000144) returns 0x00 (0000ms, 39617ms total) +T3170 110:417 JLINK_WriteReg(R3, 0x00000000) returns 0x00 (0000ms, 39617ms total) +T3170 110:417 JLINK_WriteReg(R4, 0x00000000) returns 0x00 (0000ms, 39617ms total) +T3170 110:417 JLINK_WriteReg(R5, 0x00000000) returns 0x00 (0000ms, 39617ms total) +T3170 110:417 JLINK_WriteReg(R6, 0x00000000) returns 0x00 (0000ms, 39617ms total) +T3170 110:417 JLINK_WriteReg(R7, 0x00000000) returns 0x00 (0000ms, 39617ms total) +T3170 110:417 JLINK_WriteReg(R8, 0x00000000) returns 0x00 (0000ms, 39617ms total) +T3170 110:417 JLINK_WriteReg(R9, 0x2000013C) returns 0x00 (0000ms, 39617ms total) +T3170 110:417 JLINK_WriteReg(R10, 0x00000000) returns 0x00 (0000ms, 39617ms total) +T3170 110:417 JLINK_WriteReg(R11, 0x00000000) returns 0x00 (0000ms, 39617ms total) +T3170 110:417 JLINK_WriteReg(R12, 0x00000000) returns 0x00 (0000ms, 39617ms total) +T3170 110:417 JLINK_WriteReg(R13 (SP), 0x20001000) returns 0x00 (0000ms, 39617ms total) +T3170 110:417 JLINK_WriteReg(R14, 0x20000001) returns 0x00 (0000ms, 39617ms total) +T3170 110:417 JLINK_WriteReg(R15 (PC), 0x20000104) returns 0x00 (0000ms, 39617ms total) +T3170 110:417 JLINK_WriteReg(XPSR, 0x01000000) returns 0x00 (0000ms, 39617ms total) +T3170 110:417 JLINK_WriteReg(MSP, 0x20001000) returns 0x00 (0000ms, 39617ms total) +T3170 110:417 JLINK_WriteReg(PSP, 0x20001000) returns 0x00 (0000ms, 39617ms total) +T3170 110:417 JLINK_WriteReg(CFBP, 0x00000000) returns 0x00 (0000ms, 39617ms total) +T3170 110:417 JLINK_SetBPEx(Addr = 0x20000000, Type = 0xFFFFFFF2) returns 0x00000100 (0000ms, 39617ms total) +T3170 110:417 JLINK_Go() -- CPU_ReadMem(4 bytes @ 0xE0001000) (0088ms, 39705ms total) +T3170 110:505 JLINK_IsHalted() -- CPU_ReadMem(2 bytes @ 0x20000000) returns TRUE (0007ms, 39712ms total) +T3170 110:512 JLINK_ReadReg(R15 (PC)) returns 0x20000000 (0000ms, 39705ms total) +T3170 110:512 JLINK_ClrBPEx(BPHandle = 0x00000100) returns 0x00 (0000ms, 39705ms total) +T3170 110:512 JLINK_ReadReg(R0) returns 0x00002580 (0000ms, 39705ms total) +T3170 110:513 JLINK_WriteMem(0x20000144, 0x0080 Bytes, ...) - Data: 65 6E 64 20 74 68 72 65 61 64 0A 00 20 2D 2D 2D ... -- CPU_WriteMem(128 bytes @ 0x20000144) returns 0x80 (0003ms, 39708ms total) +T3170 110:516 JLINK_WriteReg(R0, 0x00002580) returns 0x00 (0000ms, 39708ms total) +T3170 110:516 JLINK_WriteReg(R1, 0x00000080) returns 0x00 (0000ms, 39708ms total) +T3170 110:516 JLINK_WriteReg(R2, 0x20000144) returns 0x00 (0000ms, 39708ms total) +T3170 110:516 JLINK_WriteReg(R3, 0x00000000) returns 0x00 (0000ms, 39708ms total) +T3170 110:516 JLINK_WriteReg(R4, 0x00000000) returns 0x00 (0001ms, 39709ms total) +T3170 110:517 JLINK_WriteReg(R5, 0x00000000) returns 0x00 (0000ms, 39709ms total) +T3170 110:517 JLINK_WriteReg(R6, 0x00000000) returns 0x00 (0000ms, 39709ms total) +T3170 110:517 JLINK_WriteReg(R7, 0x00000000) returns 0x00 (0000ms, 39709ms total) +T3170 110:517 JLINK_WriteReg(R8, 0x00000000) returns 0x00 (0000ms, 39709ms total) +T3170 110:517 JLINK_WriteReg(R9, 0x2000013C) returns 0x00 (0000ms, 39709ms total) +T3170 110:517 JLINK_WriteReg(R10, 0x00000000) returns 0x00 (0000ms, 39709ms total) +T3170 110:517 JLINK_WriteReg(R11, 0x00000000) returns 0x00 (0000ms, 39709ms total) +T3170 110:517 JLINK_WriteReg(R12, 0x00000000) returns 0x00 (0000ms, 39709ms total) +T3170 110:517 JLINK_WriteReg(R13 (SP), 0x20001000) returns 0x00 (0000ms, 39709ms total) +T3170 110:517 JLINK_WriteReg(R14, 0x20000001) returns 0x00 (0000ms, 39709ms total) +T3170 110:517 JLINK_WriteReg(R15 (PC), 0x20000104) returns 0x00 (0000ms, 39709ms total) +T3170 110:517 JLINK_WriteReg(XPSR, 0x01000000) returns 0x00 (0000ms, 39709ms total) +T3170 110:517 JLINK_WriteReg(MSP, 0x20001000) returns 0x00 (0000ms, 39709ms total) +T3170 110:517 JLINK_WriteReg(PSP, 0x20001000) returns 0x00 (0000ms, 39709ms total) +T3170 110:517 JLINK_WriteReg(CFBP, 0x00000000) returns 0x00 (0000ms, 39709ms total) +T3170 110:517 JLINK_SetBPEx(Addr = 0x20000000, Type = 0xFFFFFFF2) returns 0x00000101 (0000ms, 39709ms total) +T3170 110:517 JLINK_Go() -- CPU_ReadMem(4 bytes @ 0xE0001000) (0085ms, 39794ms total) +T3170 110:602 JLINK_IsHalted() -- CPU_ReadMem(2 bytes @ 0x20000000) returns TRUE (0010ms, 39804ms total) +T3170 110:612 JLINK_ReadReg(R15 (PC)) returns 0x20000000 (0000ms, 39794ms total) +T3170 110:612 JLINK_ClrBPEx(BPHandle = 0x00000101) returns 0x00 (0000ms, 39794ms total) +T3170 110:612 JLINK_ReadReg(R0) returns 0x00002600 (0000ms, 39794ms total) +T3170 110:612 JLINK_WriteMem(0x20000144, 0x0080 Bytes, ...) - Data: AF F8 00 BF 0C A9 38 46 FF F7 11 FE 07 46 00 26 ... -- CPU_WriteMem(128 bytes @ 0x20000144) returns 0x80 (0004ms, 39798ms total) +T3170 110:616 JLINK_WriteReg(R0, 0x00002600) returns 0x00 (0000ms, 39798ms total) +T3170 110:616 JLINK_WriteReg(R1, 0x00000080) returns 0x00 (0000ms, 39798ms total) +T3170 110:616 JLINK_WriteReg(R2, 0x20000144) returns 0x00 (0000ms, 39798ms total) +T3170 110:616 JLINK_WriteReg(R3, 0x00000000) returns 0x00 (0000ms, 39798ms total) +T3170 110:616 JLINK_WriteReg(R4, 0x00000000) returns 0x00 (0000ms, 39798ms total) +T3170 110:616 JLINK_WriteReg(R5, 0x00000000) returns 0x00 (0000ms, 39798ms total) +T3170 110:616 JLINK_WriteReg(R6, 0x00000000) returns 0x00 (0000ms, 39798ms total) +T3170 110:616 JLINK_WriteReg(R7, 0x00000000) returns 0x00 (0000ms, 39798ms total) +T3170 110:616 JLINK_WriteReg(R8, 0x00000000) returns 0x00 (0000ms, 39798ms total) +T3170 110:616 JLINK_WriteReg(R9, 0x2000013C) returns 0x00 (0000ms, 39798ms total) +T3170 110:616 JLINK_WriteReg(R10, 0x00000000) returns 0x00 (0000ms, 39798ms total) +T3170 110:616 JLINK_WriteReg(R11, 0x00000000) returns 0x00 (0000ms, 39798ms total) +T3170 110:616 JLINK_WriteReg(R12, 0x00000000) returns 0x00 (0000ms, 39798ms total) +T3170 110:616 JLINK_WriteReg(R13 (SP), 0x20001000) returns 0x00 (0000ms, 39798ms total) +T3170 110:616 JLINK_WriteReg(R14, 0x20000001) returns 0x00 (0000ms, 39798ms total) +T3170 110:616 JLINK_WriteReg(R15 (PC), 0x20000104) returns 0x00 (0000ms, 39798ms total) +T3170 110:616 JLINK_WriteReg(XPSR, 0x01000000) returns 0x00 (0000ms, 39798ms total) +T3170 110:616 JLINK_WriteReg(MSP, 0x20001000) returns 0x00 (0000ms, 39798ms total) +T3170 110:616 JLINK_WriteReg(PSP, 0x20001000) returns 0x00 (0000ms, 39798ms total) +T3170 110:616 JLINK_WriteReg(CFBP, 0x00000000) returns 0x00 (0000ms, 39798ms total) +T3170 110:616 JLINK_SetBPEx(Addr = 0x20000000, Type = 0xFFFFFFF2) returns 0x00000102 (0000ms, 39798ms total) +T3170 110:616 JLINK_Go() -- CPU_ReadMem(4 bytes @ 0xE0001000) (0089ms, 39887ms total) +T3170 110:705 JLINK_IsHalted() -- CPU_ReadMem(2 bytes @ 0x20000000) returns TRUE (0010ms, 39897ms total) +T3170 110:715 JLINK_ReadReg(R15 (PC)) returns 0x20000000 (0000ms, 39887ms total) +T3170 110:715 JLINK_ClrBPEx(BPHandle = 0x00000102) returns 0x00 (0000ms, 39887ms total) +T3170 110:715 JLINK_ReadReg(R0) returns 0x00002680 (0000ms, 39887ms total) +T3170 110:716 JLINK_WriteMem(0x20000144, 0x0080 Bytes, ...) - Data: 25 2D 2A 2E 73 20 20 20 6F 77 6E 65 72 20 20 68 ... -- CPU_WriteMem(128 bytes @ 0x20000144) returns 0x80 (0046ms, 39933ms total) +T3170 110:762 JLINK_WriteReg(R0, 0x00002680) returns 0x00 (0000ms, 39933ms total) +T3170 110:762 JLINK_WriteReg(R1, 0x00000080) returns 0x00 (0000ms, 39933ms total) +T3170 110:762 JLINK_WriteReg(R2, 0x20000144) returns 0x00 (0000ms, 39933ms total) +T3170 110:762 JLINK_WriteReg(R3, 0x00000000) returns 0x00 (0000ms, 39933ms total) +T3170 110:762 JLINK_WriteReg(R4, 0x00000000) returns 0x00 (0000ms, 39933ms total) +T3170 110:762 JLINK_WriteReg(R5, 0x00000000) returns 0x00 (0000ms, 39933ms total) +T3170 110:762 JLINK_WriteReg(R6, 0x00000000) returns 0x00 (0000ms, 39933ms total) +T3170 110:762 JLINK_WriteReg(R7, 0x00000000) returns 0x00 (0000ms, 39933ms total) +T3170 110:762 JLINK_WriteReg(R8, 0x00000000) returns 0x00 (0000ms, 39933ms total) +T3170 110:762 JLINK_WriteReg(R9, 0x2000013C) returns 0x00 (0000ms, 39933ms total) +T3170 110:762 JLINK_WriteReg(R10, 0x00000000) returns 0x00 (0000ms, 39933ms total) +T3170 110:762 JLINK_WriteReg(R11, 0x00000000) returns 0x00 (0000ms, 39933ms total) +T3170 110:762 JLINK_WriteReg(R12, 0x00000000) returns 0x00 (0000ms, 39933ms total) +T3170 110:762 JLINK_WriteReg(R13 (SP), 0x20001000) returns 0x00 (0000ms, 39933ms total) +T3170 110:762 JLINK_WriteReg(R14, 0x20000001) returns 0x00 (0000ms, 39933ms total) +T3170 110:762 JLINK_WriteReg(R15 (PC), 0x20000104) returns 0x00 (0000ms, 39933ms total) +T3170 110:762 JLINK_WriteReg(XPSR, 0x01000000) returns 0x00 (0001ms, 39934ms total) +T3170 110:763 JLINK_WriteReg(MSP, 0x20001000) returns 0x00 (0000ms, 39934ms total) +T3170 110:763 JLINK_WriteReg(PSP, 0x20001000) returns 0x00 (0000ms, 39934ms total) +T3170 110:763 JLINK_WriteReg(CFBP, 0x00000000) returns 0x00 (0000ms, 39934ms total) +T3170 110:763 JLINK_SetBPEx(Addr = 0x20000000, Type = 0xFFFFFFF2) returns 0x00000103 (0000ms, 39934ms total) +T3170 110:763 JLINK_Go() -- CPU_ReadMem(4 bytes @ 0xE0001000) (0042ms, 39976ms total) +T3170 110:805 JLINK_IsHalted() -- CPU_ReadMem(2 bytes @ 0x20000000) returns TRUE (0008ms, 39984ms total) +T3170 110:813 JLINK_ReadReg(R15 (PC)) returns 0x20000000 (0000ms, 39976ms total) +T3170 110:813 JLINK_ClrBPEx(BPHandle = 0x00000103) returns 0x00 (0000ms, 39976ms total) +T3170 110:813 JLINK_ReadReg(R0) returns 0x00002700 (0000ms, 39976ms total) +T3170 110:813 JLINK_WriteMem(0x20000144, 0x0080 Bytes, ...) - Data: 2F F8 40 46 00 F0 3E FC 34 A0 01 F0 29 F8 00 BF ... -- CPU_WriteMem(128 bytes @ 0x20000144) returns 0x80 (0004ms, 39980ms total) +T3170 110:817 JLINK_WriteReg(R0, 0x00002700) returns 0x00 (0000ms, 39980ms total) +T3170 110:817 JLINK_WriteReg(R1, 0x00000080) returns 0x00 (0000ms, 39980ms total) +T3170 110:817 JLINK_WriteReg(R2, 0x20000144) returns 0x00 (0000ms, 39980ms total) +T3170 110:817 JLINK_WriteReg(R3, 0x00000000) returns 0x00 (0000ms, 39980ms total) +T3170 110:817 JLINK_WriteReg(R4, 0x00000000) returns 0x00 (0000ms, 39980ms total) +T3170 110:817 JLINK_WriteReg(R5, 0x00000000) returns 0x00 (0000ms, 39980ms total) +T3170 110:817 JLINK_WriteReg(R6, 0x00000000) returns 0x00 (0000ms, 39980ms total) +T3170 110:817 JLINK_WriteReg(R7, 0x00000000) returns 0x00 (0000ms, 39980ms total) +T3170 110:817 JLINK_WriteReg(R8, 0x00000000) returns 0x00 (0000ms, 39980ms total) +T3170 110:817 JLINK_WriteReg(R9, 0x2000013C) returns 0x00 (0000ms, 39980ms total) +T3170 110:817 JLINK_WriteReg(R10, 0x00000000) returns 0x00 (0000ms, 39980ms total) +T3170 110:817 JLINK_WriteReg(R11, 0x00000000) returns 0x00 (0000ms, 39980ms total) +T3170 110:818 JLINK_WriteReg(R12, 0x00000000) returns 0x00 (0000ms, 39981ms total) +T3170 110:818 JLINK_WriteReg(R13 (SP), 0x20001000) returns 0x00 (0000ms, 39981ms total) +T3170 110:818 JLINK_WriteReg(R14, 0x20000001) returns 0x00 (0000ms, 39981ms total) +T3170 110:818 JLINK_WriteReg(R15 (PC), 0x20000104) returns 0x00 (0000ms, 39981ms total) +T3170 110:818 JLINK_WriteReg(XPSR, 0x01000000) returns 0x00 (0000ms, 39981ms total) +T3170 110:818 JLINK_WriteReg(MSP, 0x20001000) returns 0x00 (0000ms, 39981ms total) +T3170 110:818 JLINK_WriteReg(PSP, 0x20001000) returns 0x00 (0000ms, 39981ms total) +T3170 110:818 JLINK_WriteReg(CFBP, 0x00000000) returns 0x00 (0000ms, 39981ms total) +T3170 110:818 JLINK_SetBPEx(Addr = 0x20000000, Type = 0xFFFFFFF2) returns 0x00000104 (0000ms, 39981ms total) +T3170 110:818 JLINK_Go() -- CPU_ReadMem(4 bytes @ 0xE0001000) (0088ms, 40069ms total) +T3170 110:906 JLINK_IsHalted() -- CPU_ReadMem(2 bytes @ 0x20000000) returns TRUE (0054ms, 40123ms total) +T3170 111:001 JLINK_ReadReg(R15 (PC)) returns 0x20000000 (0000ms, 40069ms total) +T3170 111:001 JLINK_ClrBPEx(BPHandle = 0x00000104) returns 0x00 (0000ms, 40069ms total) +T3170 111:001 JLINK_ReadReg(R0) returns 0x00002780 (0000ms, 40069ms total) +T3170 111:001 JLINK_WriteMem(0x20000144, 0x0080 Bytes, ...) - Data: 0D E0 04 F1 14 00 01 F0 40 F8 82 46 A0 8B 23 46 ... -- CPU_WriteMem(128 bytes @ 0x20000144) returns 0x80 (0004ms, 40073ms total) +T3170 111:005 JLINK_WriteReg(R0, 0x00002780) returns 0x00 (0000ms, 40073ms total) +T3170 111:005 JLINK_WriteReg(R1, 0x00000080) returns 0x00 (0000ms, 40073ms total) +T3170 111:005 JLINK_WriteReg(R2, 0x20000144) returns 0x00 (0000ms, 40073ms total) +T3170 111:005 JLINK_WriteReg(R3, 0x00000000) returns 0x00 (0000ms, 40073ms total) +T3170 111:005 JLINK_WriteReg(R4, 0x00000000) returns 0x00 (0000ms, 40073ms total) +T3170 111:005 JLINK_WriteReg(R5, 0x00000000) returns 0x00 (0000ms, 40073ms total) +T3170 111:005 JLINK_WriteReg(R6, 0x00000000) returns 0x00 (0000ms, 40073ms total) +T3170 111:005 JLINK_WriteReg(R7, 0x00000000) returns 0x00 (0000ms, 40073ms total) +T3170 111:005 JLINK_WriteReg(R8, 0x00000000) returns 0x00 (0000ms, 40073ms total) +T3170 111:005 JLINK_WriteReg(R9, 0x2000013C) returns 0x00 (0000ms, 40073ms total) +T3170 111:005 JLINK_WriteReg(R10, 0x00000000) returns 0x00 (0000ms, 40073ms total) +T3170 111:005 JLINK_WriteReg(R11, 0x00000000) returns 0x00 (0000ms, 40073ms total) +T3170 111:005 JLINK_WriteReg(R12, 0x00000000) returns 0x00 (0000ms, 40073ms total) +T3170 111:005 JLINK_WriteReg(R13 (SP), 0x20001000) returns 0x00 (0000ms, 40073ms total) +T3170 111:005 JLINK_WriteReg(R14, 0x20000001) returns 0x00 (0000ms, 40073ms total) +T3170 111:005 JLINK_WriteReg(R15 (PC), 0x20000104) returns 0x00 (0000ms, 40073ms total) +T3170 111:005 JLINK_WriteReg(XPSR, 0x01000000) returns 0x00 (0000ms, 40073ms total) +T3170 111:005 JLINK_WriteReg(MSP, 0x20001000) returns 0x00 (0000ms, 40073ms total) +T3170 111:005 JLINK_WriteReg(PSP, 0x20001000) returns 0x00 (0000ms, 40073ms total) +T3170 111:005 JLINK_WriteReg(CFBP, 0x00000000) returns 0x00 (0000ms, 40073ms total) +T3170 111:005 JLINK_SetBPEx(Addr = 0x20000000, Type = 0xFFFFFFF2) returns 0x00000105 (0000ms, 40073ms total) +T3170 111:005 JLINK_Go() -- CPU_ReadMem(4 bytes @ 0xE0001000) (0007ms, 40080ms total) +T3170 111:012 JLINK_IsHalted() -- CPU_ReadMem(2 bytes @ 0x20000000) returns TRUE (0088ms, 40168ms total) +T3170 111:100 JLINK_ReadReg(R15 (PC)) returns 0x20000000 (0000ms, 40080ms total) +T3170 111:100 JLINK_ClrBPEx(BPHandle = 0x00000105) returns 0x00 (0000ms, 40080ms total) +T3170 111:100 JLINK_ReadReg(R0) returns 0x00002800 (0000ms, 40080ms total) +T3170 111:100 JLINK_WriteMem(0x20000144, 0x0080 Bytes, ...) - Data: 25 64 3A 00 25 2D 2A 2E 2A 73 20 25 30 33 64 20 ... -- CPU_WriteMem(128 bytes @ 0x20000144) returns 0x80 (0004ms, 40084ms total) +T3170 111:104 JLINK_WriteReg(R0, 0x00002800) returns 0x00 (0000ms, 40084ms total) +T3170 111:104 JLINK_WriteReg(R1, 0x00000080) returns 0x00 (0000ms, 40084ms total) +T3170 111:104 JLINK_WriteReg(R2, 0x20000144) returns 0x00 (0000ms, 40084ms total) +T3170 111:104 JLINK_WriteReg(R3, 0x00000000) returns 0x00 (0000ms, 40084ms total) +T3170 111:104 JLINK_WriteReg(R4, 0x00000000) returns 0x00 (0000ms, 40084ms total) +T3170 111:104 JLINK_WriteReg(R5, 0x00000000) returns 0x00 (0000ms, 40084ms total) +T3170 111:104 JLINK_WriteReg(R6, 0x00000000) returns 0x00 (0000ms, 40084ms total) +T3170 111:104 JLINK_WriteReg(R7, 0x00000000) returns 0x00 (0000ms, 40084ms total) +T3170 111:104 JLINK_WriteReg(R8, 0x00000000) returns 0x00 (0000ms, 40084ms total) +T3170 111:104 JLINK_WriteReg(R9, 0x2000013C) returns 0x00 (0000ms, 40084ms total) +T3170 111:104 JLINK_WriteReg(R10, 0x00000000) returns 0x00 (0000ms, 40084ms total) +T3170 111:104 JLINK_WriteReg(R11, 0x00000000) returns 0x00 (0000ms, 40084ms total) +T3170 111:104 JLINK_WriteReg(R12, 0x00000000) returns 0x00 (0000ms, 40084ms total) +T3170 111:104 JLINK_WriteReg(R13 (SP), 0x20001000) returns 0x00 (0000ms, 40084ms total) +T3170 111:104 JLINK_WriteReg(R14, 0x20000001) returns 0x00 (0000ms, 40084ms total) +T3170 111:104 JLINK_WriteReg(R15 (PC), 0x20000104) returns 0x00 (0000ms, 40084ms total) +T3170 111:104 JLINK_WriteReg(XPSR, 0x01000000) returns 0x00 (0000ms, 40084ms total) +T3170 111:104 JLINK_WriteReg(MSP, 0x20001000) returns 0x00 (0000ms, 40084ms total) +T3170 111:104 JLINK_WriteReg(PSP, 0x20001000) returns 0x00 (0000ms, 40084ms total) +T3170 111:104 JLINK_WriteReg(CFBP, 0x00000000) returns 0x00 (0000ms, 40084ms total) +T3170 111:104 JLINK_SetBPEx(Addr = 0x20000000, Type = 0xFFFFFFF2) returns 0x00000106 (0000ms, 40084ms total) +T3170 111:104 JLINK_Go() -- CPU_ReadMem(4 bytes @ 0xE0001000) (0008ms, 40092ms total) +T3170 111:112 JLINK_IsHalted() -- CPU_ReadMem(2 bytes @ 0x20000000) returns TRUE (0088ms, 40180ms total) +T3170 111:200 JLINK_ReadReg(R15 (PC)) returns 0x20000000 (0000ms, 40092ms total) +T3170 111:200 JLINK_ClrBPEx(BPHandle = 0x00000106) returns 0x00 (0000ms, 40092ms total) +T3170 111:200 JLINK_ReadReg(R0) returns 0x00002880 (0000ms, 40092ms total) +T3170 111:200 JLINK_WriteMem(0x20000144, 0x0080 Bytes, ...) - Data: 80 22 29 46 03 A8 FD F7 C3 FE 30 98 FD F7 70 FD ... -- CPU_WriteMem(128 bytes @ 0x20000144) returns 0x80 (0004ms, 40096ms total) +T3170 111:204 JLINK_WriteReg(R0, 0x00002880) returns 0x00 (0000ms, 40096ms total) +T3170 111:204 JLINK_WriteReg(R1, 0x00000080) returns 0x00 (0000ms, 40096ms total) +T3170 111:204 JLINK_WriteReg(R2, 0x20000144) returns 0x00 (0000ms, 40096ms total) +T3170 111:204 JLINK_WriteReg(R3, 0x00000000) returns 0x00 (0000ms, 40096ms total) +T3170 111:204 JLINK_WriteReg(R4, 0x00000000) returns 0x00 (0000ms, 40096ms total) +T3170 111:204 JLINK_WriteReg(R5, 0x00000000) returns 0x00 (0000ms, 40096ms total) +T3170 111:204 JLINK_WriteReg(R6, 0x00000000) returns 0x00 (0000ms, 40096ms total) +T3170 111:204 JLINK_WriteReg(R7, 0x00000000) returns 0x00 (0000ms, 40096ms total) +T3170 111:204 JLINK_WriteReg(R8, 0x00000000) returns 0x00 (0000ms, 40096ms total) +T3170 111:204 JLINK_WriteReg(R9, 0x2000013C) returns 0x00 (0000ms, 40096ms total) +T3170 111:204 JLINK_WriteReg(R10, 0x00000000) returns 0x00 (0000ms, 40096ms total) +T3170 111:204 JLINK_WriteReg(R11, 0x00000000) returns 0x00 (0000ms, 40096ms total) +T3170 111:204 JLINK_WriteReg(R12, 0x00000000) returns 0x00 (0000ms, 40096ms total) +T3170 111:204 JLINK_WriteReg(R13 (SP), 0x20001000) returns 0x00 (0000ms, 40096ms total) +T3170 111:204 JLINK_WriteReg(R14, 0x20000001) returns 0x00 (0000ms, 40096ms total) +T3170 111:204 JLINK_WriteReg(R15 (PC), 0x20000104) returns 0x00 (0000ms, 40096ms total) +T3170 111:204 JLINK_WriteReg(XPSR, 0x01000000) returns 0x00 (0000ms, 40096ms total) +T3170 111:204 JLINK_WriteReg(MSP, 0x20001000) returns 0x00 (0000ms, 40096ms total) +T3170 111:204 JLINK_WriteReg(PSP, 0x20001000) returns 0x00 (0000ms, 40096ms total) +T3170 111:204 JLINK_WriteReg(CFBP, 0x00000000) returns 0x00 (0000ms, 40096ms total) +T3170 111:204 JLINK_SetBPEx(Addr = 0x20000000, Type = 0xFFFFFFF2) returns 0x00000107 (0000ms, 40096ms total) +T3170 111:204 JLINK_Go() -- CPU_ReadMem(4 bytes @ 0xE0001000) (0006ms, 40102ms total) +T3170 111:210 JLINK_IsHalted() -- CPU_ReadMem(2 bytes @ 0x20000000) returns TRUE (0032ms, 40134ms total) +T3170 111:242 JLINK_ReadReg(R15 (PC)) returns 0x20000000 (0000ms, 40102ms total) +T3170 111:242 JLINK_ClrBPEx(BPHandle = 0x00000107) returns 0x00 (0000ms, 40102ms total) +T3170 111:242 JLINK_ReadReg(R0) returns 0x00002900 (0000ms, 40102ms total) +T3170 111:242 JLINK_WriteMem(0x20000144, 0x0080 Bytes, ...) - Data: F1 F0 02 90 21 6B A0 6C CD E9 00 01 E3 69 A0 6A ... -- CPU_WriteMem(128 bytes @ 0x20000144) returns 0x80 (0059ms, 40161ms total) +T3170 111:302 JLINK_WriteReg(R0, 0x00002900) returns 0x00 (0000ms, 40161ms total) +T3170 111:302 JLINK_WriteReg(R1, 0x00000080) returns 0x00 (0000ms, 40161ms total) +T3170 111:302 JLINK_WriteReg(R2, 0x20000144) returns 0x00 (0000ms, 40161ms total) +T3170 111:302 JLINK_WriteReg(R3, 0x00000000) returns 0x00 (0000ms, 40161ms total) +T3170 111:302 JLINK_WriteReg(R4, 0x00000000) returns 0x00 (0000ms, 40161ms total) +T3170 111:302 JLINK_WriteReg(R5, 0x00000000) returns 0x00 (0000ms, 40161ms total) +T3170 111:302 JLINK_WriteReg(R6, 0x00000000) returns 0x00 (0000ms, 40161ms total) +T3170 111:302 JLINK_WriteReg(R7, 0x00000000) returns 0x00 (0000ms, 40161ms total) +T3170 111:302 JLINK_WriteReg(R8, 0x00000000) returns 0x00 (0000ms, 40161ms total) +T3170 111:302 JLINK_WriteReg(R9, 0x2000013C) returns 0x00 (0000ms, 40161ms total) +T3170 111:302 JLINK_WriteReg(R10, 0x00000000) returns 0x00 (0000ms, 40161ms total) +T3170 111:302 JLINK_WriteReg(R11, 0x00000000) returns 0x00 (0000ms, 40161ms total) +T3170 111:302 JLINK_WriteReg(R12, 0x00000000) returns 0x00 (0000ms, 40161ms total) +T3170 111:302 JLINK_WriteReg(R13 (SP), 0x20001000) returns 0x00 (0000ms, 40161ms total) +T3170 111:302 JLINK_WriteReg(R14, 0x20000001) returns 0x00 (0000ms, 40161ms total) +T3170 111:302 JLINK_WriteReg(R15 (PC), 0x20000104) returns 0x00 (0000ms, 40161ms total) +T3170 111:302 JLINK_WriteReg(XPSR, 0x01000000) returns 0x00 (0000ms, 40161ms total) +T3170 111:302 JLINK_WriteReg(MSP, 0x20001000) returns 0x00 (0000ms, 40161ms total) +T3170 111:302 JLINK_WriteReg(PSP, 0x20001000) returns 0x00 (0000ms, 40161ms total) +T3170 111:302 JLINK_WriteReg(CFBP, 0x00000000) returns 0x00 (0000ms, 40161ms total) +T3170 111:302 JLINK_SetBPEx(Addr = 0x20000000, Type = 0xFFFFFFF2) returns 0x00000108 (0000ms, 40161ms total) +T3170 111:302 JLINK_Go() -- CPU_ReadMem(4 bytes @ 0xE0001000) (0008ms, 40169ms total) +T3170 111:310 JLINK_IsHalted() -- CPU_ReadMem(2 bytes @ 0x20000000) returns TRUE (0090ms, 40259ms total) +T3170 111:400 JLINK_ReadReg(R15 (PC)) returns 0x20000000 (0000ms, 40169ms total) +T3170 111:400 JLINK_ClrBPEx(BPHandle = 0x00000108) returns 0x00 (0000ms, 40169ms total) +T3170 111:400 JLINK_ReadReg(R0) returns 0x00002980 (0000ms, 40169ms total) +T3170 111:400 JLINK_WriteMem(0x20000144, 0x0080 Bytes, ...) - Data: 2D 2D 2D 0A 00 00 00 00 25 2D 2A 2E 2A 73 20 25 ... -- CPU_WriteMem(128 bytes @ 0x20000144) returns 0x80 (0004ms, 40173ms total) +T3170 111:404 JLINK_WriteReg(R0, 0x00002980) returns 0x00 (0000ms, 40173ms total) +T3170 111:404 JLINK_WriteReg(R1, 0x00000080) returns 0x00 (0000ms, 40173ms total) +T3170 111:404 JLINK_WriteReg(R2, 0x20000144) returns 0x00 (0000ms, 40173ms total) +T3170 111:404 JLINK_WriteReg(R3, 0x00000000) returns 0x00 (0000ms, 40173ms total) +T3170 111:404 JLINK_WriteReg(R4, 0x00000000) returns 0x00 (0000ms, 40173ms total) +T3170 111:404 JLINK_WriteReg(R5, 0x00000000) returns 0x00 (0000ms, 40173ms total) +T3170 111:404 JLINK_WriteReg(R6, 0x00000000) returns 0x00 (0000ms, 40173ms total) +T3170 111:404 JLINK_WriteReg(R7, 0x00000000) returns 0x00 (0000ms, 40173ms total) +T3170 111:404 JLINK_WriteReg(R8, 0x00000000) returns 0x00 (0000ms, 40173ms total) +T3170 111:404 JLINK_WriteReg(R9, 0x2000013C) returns 0x00 (0000ms, 40173ms total) +T3170 111:404 JLINK_WriteReg(R10, 0x00000000) returns 0x00 (0000ms, 40173ms total) +T3170 111:404 JLINK_WriteReg(R11, 0x00000000) returns 0x00 (0000ms, 40173ms total) +T3170 111:404 JLINK_WriteReg(R12, 0x00000000) returns 0x00 (0000ms, 40173ms total) +T3170 111:404 JLINK_WriteReg(R13 (SP), 0x20001000) returns 0x00 (0000ms, 40173ms total) +T3170 111:404 JLINK_WriteReg(R14, 0x20000001) returns 0x00 (0000ms, 40173ms total) +T3170 111:404 JLINK_WriteReg(R15 (PC), 0x20000104) returns 0x00 (0000ms, 40173ms total) +T3170 111:404 JLINK_WriteReg(XPSR, 0x01000000) returns 0x00 (0000ms, 40173ms total) +T3170 111:404 JLINK_WriteReg(MSP, 0x20001000) returns 0x00 (0000ms, 40173ms total) +T3170 111:404 JLINK_WriteReg(PSP, 0x20001000) returns 0x00 (0000ms, 40173ms total) +T3170 111:404 JLINK_WriteReg(CFBP, 0x00000000) returns 0x00 (0000ms, 40173ms total) +T3170 111:404 JLINK_SetBPEx(Addr = 0x20000000, Type = 0xFFFFFFF2) returns 0x00000109 (0000ms, 40173ms total) +T3170 111:404 JLINK_Go() -- CPU_ReadMem(4 bytes @ 0xE0001000) (0006ms, 40179ms total) +T3170 111:410 JLINK_IsHalted() -- CPU_ReadMem(2 bytes @ 0x20000000) returns TRUE (0064ms, 40243ms total) +T3170 111:474 JLINK_ReadReg(R15 (PC)) returns 0x20000000 (0000ms, 40179ms total) +T3170 111:474 JLINK_ClrBPEx(BPHandle = 0x00000109) returns 0x00 (0000ms, 40179ms total) +T3170 111:474 JLINK_ReadReg(R0) returns 0x00002A00 (0000ms, 40179ms total) +T3170 111:474 JLINK_WriteMem(0x20000144, 0x0080 Bytes, ...) - Data: 0F F2 B4 09 08 23 03 AA 0A 21 0B A8 FF F7 FA FB ... -- CPU_WriteMem(128 bytes @ 0x20000144) returns 0x80 (0028ms, 40207ms total) +T3170 111:502 JLINK_WriteReg(R0, 0x00002A00) returns 0x00 (0000ms, 40207ms total) +T3170 111:502 JLINK_WriteReg(R1, 0x00000080) returns 0x00 (0000ms, 40207ms total) +T3170 111:502 JLINK_WriteReg(R2, 0x20000144) returns 0x00 (0000ms, 40207ms total) +T3170 111:502 JLINK_WriteReg(R3, 0x00000000) returns 0x00 (0000ms, 40207ms total) +T3170 111:502 JLINK_WriteReg(R4, 0x00000000) returns 0x00 (0000ms, 40207ms total) +T3170 111:502 JLINK_WriteReg(R5, 0x00000000) returns 0x00 (0000ms, 40207ms total) +T3170 111:502 JLINK_WriteReg(R6, 0x00000000) returns 0x00 (0000ms, 40207ms total) +T3170 111:502 JLINK_WriteReg(R7, 0x00000000) returns 0x00 (0000ms, 40207ms total) +T3170 111:502 JLINK_WriteReg(R8, 0x00000000) returns 0x00 (0000ms, 40207ms total) +T3170 111:502 JLINK_WriteReg(R9, 0x2000013C) returns 0x00 (0000ms, 40207ms total) +T3170 111:502 JLINK_WriteReg(R10, 0x00000000) returns 0x00 (0000ms, 40207ms total) +T3170 111:502 JLINK_WriteReg(R11, 0x00000000) returns 0x00 (0000ms, 40207ms total) +T3170 111:502 JLINK_WriteReg(R12, 0x00000000) returns 0x00 (0000ms, 40207ms total) +T3170 111:502 JLINK_WriteReg(R13 (SP), 0x20001000) returns 0x00 (0000ms, 40207ms total) +T3170 111:502 JLINK_WriteReg(R14, 0x20000001) returns 0x00 (0000ms, 40207ms total) +T3170 111:502 JLINK_WriteReg(R15 (PC), 0x20000104) returns 0x00 (0000ms, 40207ms total) +T3170 111:502 JLINK_WriteReg(XPSR, 0x01000000) returns 0x00 (0000ms, 40207ms total) +T3170 111:502 JLINK_WriteReg(MSP, 0x20001000) returns 0x00 (0000ms, 40207ms total) +T3170 111:502 JLINK_WriteReg(PSP, 0x20001000) returns 0x00 (0000ms, 40207ms total) +T3170 111:502 JLINK_WriteReg(CFBP, 0x00000000) returns 0x00 (0000ms, 40207ms total) +T3170 111:502 JLINK_SetBPEx(Addr = 0x20000000, Type = 0xFFFFFFF2) returns 0x0000010A (0000ms, 40207ms total) +T3170 111:502 JLINK_Go() -- CPU_ReadMem(4 bytes @ 0xE0001000) (0006ms, 40213ms total) +T3170 111:508 JLINK_IsHalted() -- CPU_ReadMem(2 bytes @ 0x20000000) returns TRUE (0008ms, 40221ms total) +T3170 111:516 JLINK_ReadReg(R15 (PC)) returns 0x20000000 (0000ms, 40213ms total) +T3170 111:516 JLINK_ClrBPEx(BPHandle = 0x0000010A) returns 0x00 (0000ms, 40213ms total) +T3170 111:516 JLINK_ReadReg(R0) returns 0x00002A80 (0000ms, 40213ms total) +T3170 111:517 JLINK_WriteMem(0x20000144, 0x0080 Bytes, ...) - Data: 01 00 18 B1 27 A0 00 F0 6B FE 02 E0 28 A0 00 F0 ... -- CPU_WriteMem(128 bytes @ 0x20000144) returns 0x80 (0084ms, 40297ms total) +T3170 111:601 JLINK_WriteReg(R0, 0x00002A80) returns 0x00 (0000ms, 40297ms total) +T3170 111:601 JLINK_WriteReg(R1, 0x00000080) returns 0x00 (0000ms, 40297ms total) +T3170 111:601 JLINK_WriteReg(R2, 0x20000144) returns 0x00 (0000ms, 40297ms total) +T3170 111:601 JLINK_WriteReg(R3, 0x00000000) returns 0x00 (0000ms, 40297ms total) +T3170 111:601 JLINK_WriteReg(R4, 0x00000000) returns 0x00 (0000ms, 40297ms total) +T3170 111:601 JLINK_WriteReg(R5, 0x00000000) returns 0x00 (0000ms, 40297ms total) +T3170 111:601 JLINK_WriteReg(R6, 0x00000000) returns 0x00 (0000ms, 40297ms total) +T3170 111:601 JLINK_WriteReg(R7, 0x00000000) returns 0x00 (0000ms, 40297ms total) +T3170 111:602 JLINK_WriteReg(R8, 0x00000000) returns 0x00 (0000ms, 40298ms total) +T3170 111:602 JLINK_WriteReg(R9, 0x2000013C) returns 0x00 (0000ms, 40298ms total) +T3170 111:602 JLINK_WriteReg(R10, 0x00000000) returns 0x00 (0000ms, 40298ms total) +T3170 111:602 JLINK_WriteReg(R11, 0x00000000) returns 0x00 (0000ms, 40298ms total) +T3170 111:602 JLINK_WriteReg(R12, 0x00000000) returns 0x00 (0000ms, 40298ms total) +T3170 111:602 JLINK_WriteReg(R13 (SP), 0x20001000) returns 0x00 (0000ms, 40298ms total) +T3170 111:602 JLINK_WriteReg(R14, 0x20000001) returns 0x00 (0000ms, 40298ms total) +T3170 111:602 JLINK_WriteReg(R15 (PC), 0x20000104) returns 0x00 (0000ms, 40298ms total) +T3170 111:602 JLINK_WriteReg(XPSR, 0x01000000) returns 0x00 (0000ms, 40298ms total) +T3170 111:602 JLINK_WriteReg(MSP, 0x20001000) returns 0x00 (0000ms, 40298ms total) +T3170 111:602 JLINK_WriteReg(PSP, 0x20001000) returns 0x00 (0000ms, 40298ms total) +T3170 111:602 JLINK_WriteReg(CFBP, 0x00000000) returns 0x00 (0000ms, 40298ms total) +T3170 111:602 JLINK_SetBPEx(Addr = 0x20000000, Type = 0xFFFFFFF2) returns 0x0000010B (0000ms, 40298ms total) +T3170 111:602 JLINK_Go() -- CPU_ReadMem(4 bytes @ 0xE0001000) (0008ms, 40306ms total) +T3170 111:610 JLINK_IsHalted() -- CPU_ReadMem(2 bytes @ 0x20000000) returns TRUE (0090ms, 40396ms total) +T3170 111:700 JLINK_ReadReg(R15 (PC)) returns 0x00000000 (0000ms, 40306ms total) +T3170 111:700 JLINK_ClrBPEx(BPHandle = 0x0000010B) returns 0x01 (0000ms, 40306ms total) +T3170 111:700 JLINK_WriteReg(R0, 0x00000003) returns 0x01 (0000ms, 40306ms total) +T3170 111:700 JLINK_WriteReg(R1, 0x00000080) returns 0x01 (0000ms, 40306ms total) +T3170 111:700 JLINK_WriteReg(R2, 0x20000144) returns 0x01 (0000ms, 40306ms total) +T3170 111:700 JLINK_WriteReg(R3, 0x00000000) returns 0x01 (0000ms, 40306ms total) +T3170 111:700 JLINK_WriteReg(R4, 0x00000000) returns 0x01 (0000ms, 40306ms total) +T3170 111:700 JLINK_WriteReg(R5, 0x00000000) returns 0x01 (0000ms, 40306ms total) +T3170 111:700 JLINK_WriteReg(R6, 0x00000000) returns 0x01 (0000ms, 40306ms total) +T3170 111:700 JLINK_WriteReg(R7, 0x00000000) returns 0x01 (0000ms, 40306ms total) +T3170 111:700 JLINK_WriteReg(R8, 0x00000000) returns 0x01 (0000ms, 40306ms total) +T3170 111:700 JLINK_WriteReg(R9, 0x2000013C) returns 0x01 (0000ms, 40306ms total) +T3170 111:700 JLINK_WriteReg(R10, 0x00000000) returns 0x01 (0000ms, 40306ms total) +T3170 111:700 JLINK_WriteReg(R11, 0x00000000) returns 0x01 (0000ms, 40306ms total) +T3170 111:700 JLINK_WriteReg(R12, 0x00000000) returns 0x01 (0000ms, 40306ms total) +T3170 111:700 JLINK_WriteReg(R13 (SP), 0x20001000) returns 0x01 (0000ms, 40306ms total) +T3170 111:700 JLINK_WriteReg(R14, 0x20000001) returns 0x01 (0000ms, 40306ms total) +T3170 111:700 JLINK_WriteReg(R15 (PC), 0x20000054) returns 0x01 (0000ms, 40306ms total) +T3170 111:700 JLINK_WriteReg(XPSR, 0x01000000) returns 0x01 (0000ms, 40306ms total) +T3170 111:700 JLINK_WriteReg(MSP, 0x20001000) returns 0x01 (0000ms, 40306ms total) +T3170 111:700 JLINK_WriteReg(PSP, 0x20001000) returns 0x01 (0000ms, 40306ms total) +T3170 111:700 JLINK_WriteReg(CFBP, 0x00000000) returns 0x01 (0000ms, 40306ms total) +T3170 111:700 JLINK_SetBPEx(Addr = 0x20000000, Type = 0xFFFFFFF2) returns 0x00000000 (0000ms, 40306ms total) +T33EC 111:700 + ***** Error: Connection to emulator lost! (340071ms, 380377ms total) +T3170 924:303 JLINK_Close() (0004ms, 40310ms total) +T3170 924:303 (0004ms, 40310ms total) +T3170 924:303 Closed (0004ms, 40310ms total) diff --git a/bsp/smartfusion2/user/JLinkSettings.ini b/bsp/smartfusion2/user/JLinkSettings.ini new file mode 100644 index 0000000000..292d9a0285 --- /dev/null +++ b/bsp/smartfusion2/user/JLinkSettings.ini @@ -0,0 +1,39 @@ +[BREAKPOINTS]
+ForceImpTypeAny = 0
+ShowInfoWin = 1
+EnableFlashBP = 2
+BPDuringExecution = 0
+[CFI]
+CFISize = 0x00
+CFIAddr = 0x00
+[CPU]
+MonModeVTableAddr = 0xFFFFFFFF
+MonModeDebug = 0
+MaxNumAPs = 0
+LowPowerHandlingMode = 0
+OverrideMemMap = 0
+AllowSimulation = 1
+ScriptFile=""
+[FLASH]
+CacheExcludeSize = 0x00
+CacheExcludeAddr = 0x00
+MinNumBytesFlashDL = 0
+SkipProgOnCRCMatch = 1
+VerifyDownload = 1
+AllowCaching = 1
+EnableFlashDL = 2
+Override = 0
+Device="ARM7"
+[GENERAL]
+WorkRAMSize = 0x00
+WorkRAMAddr = 0x00
+RAMUsageLimit = 0x00
+[SWO]
+SWOLogFile=""
+[MEM]
+RdOverrideOrMask = 0x00
+RdOverrideAndMask = 0xFFFFFFFF
+RdOverrideAddr = 0xFFFFFFFF
+WrOverrideOrMask = 0x00
+WrOverrideAndMask = 0xFFFFFFFF
+WrOverrideAddr = 0xFFFFFFFF
diff --git a/bsp/smartfusion2/user/README.txt b/bsp/smartfusion2/user/README.txt new file mode 100644 index 0000000000..8b13789179 --- /dev/null +++ b/bsp/smartfusion2/user/README.txt @@ -0,0 +1 @@ + diff --git a/bsp/smartfusion2/user/board.c b/bsp/smartfusion2/user/board.c new file mode 100644 index 0000000000..b5c1f32653 --- /dev/null +++ b/bsp/smartfusion2/user/board.c @@ -0,0 +1,91 @@ +/* + * Copyright (c) 2006-2019, RT-Thread Development Team + * + * SPDX-License-Identifier: Apache-2.0 + * + * Change Logs: + * Date Author Notes + * 2017-07-24 Tanek the first version + * 2018-11-12 Ernest Chen modify copyright + */ + +#include <stdint.h> +#include <rthw.h> +#include <rtthread.h> + +#define _SCB_BASE (0xE000E010UL) +#define _SYSTICK_CTRL (*(rt_uint32_t *)(_SCB_BASE + 0x0)) +#define _SYSTICK_LOAD (*(rt_uint32_t *)(_SCB_BASE + 0x4)) +#define _SYSTICK_VAL (*(rt_uint32_t *)(_SCB_BASE + 0x8)) +#define _SYSTICK_CALIB (*(rt_uint32_t *)(_SCB_BASE + 0xC)) +#define _SYSTICK_PRI (*(rt_uint8_t *)(0xE000ED23UL)) + +// Updates the variable SystemCoreClock and must be called +// whenever the core clock is changed during program execution. +extern void SystemCoreClockUpdate(void); + +// Holds the system core clock, which is the system clock +// frequency supplied to the SysTick timer and the processor +// core clock. +extern uint32_t SystemCoreClock; + +static uint32_t _SysTick_Config(rt_uint32_t ticks) +{ + if ((ticks - 1) > 0xFFFFFF) + { + return 1; + } + + _SYSTICK_LOAD = ticks - 1; + _SYSTICK_PRI = 0xFF; + _SYSTICK_VAL = 0; + _SYSTICK_CTRL = 0x07; + + return 0; +} + +#if defined(RT_USING_USER_MAIN) && defined(RT_USING_HEAP) +#define RT_HEAP_SIZE 1024 +static uint32_t rt_heap[RT_HEAP_SIZE]; // heap default size: 4K(1024 * 4) +RT_WEAK void *rt_heap_begin_get(void) +{ + return rt_heap; +} + +RT_WEAK void *rt_heap_end_get(void) +{ + return rt_heap + RT_HEAP_SIZE; +} +#endif + +/* This function will initial your board. */ +void rt_hw_board_init() +{ + /* System Clock Update */ + SystemCoreClockUpdate(); + + /* System Tick Configuration */ + _SysTick_Config(SystemCoreClock / RT_TICK_PER_SECOND); + + /* Call components board initial (use INIT_BOARD_EXPORT()) */ +#ifdef RT_USING_COMPONENTS_INIT + rt_components_board_init(); +#endif +//#ifdef RT_USING_CONSOLE +// rt_console_set_device(RT_CONSOLE_DEVICE_NAME); +//#endif +#if defined(RT_USING_USER_MAIN) && defined(RT_USING_HEAP) + rt_system_heap_init(rt_heap_begin_get(), rt_heap_end_get()); +#endif +} + +void SysTick_Handler(void) +{ + /* enter interrupt */ + rt_interrupt_enter(); + + rt_tick_increase(); + + /* leave interrupt */ + rt_interrupt_leave(); +} diff --git a/bsp/smartfusion2/user/config.c b/bsp/smartfusion2/user/config.c new file mode 100644 index 0000000000..118a460725 --- /dev/null +++ b/bsp/smartfusion2/user/config.c @@ -0,0 +1,59 @@ +#include "config.h" + +mss_uart_instance_t * const gp_my_uart0 = &g_mss_uart0; + +/* gpio and uart0 initialization */ +void boardInit(void) +{ + /* mss gpio init */ + MSS_GPIO_init(); + MSS_GPIO_config(MSS_GPIO_0, MSS_GPIO_OUTPUT_MODE); + MSS_GPIO_config(MSS_GPIO_1, MSS_GPIO_OUTPUT_MODE); + + /* mss uart0 init: 115200, 8, no, 1 */ + MSS_UART_init(gp_my_uart0, MSS_UART_115200_BAUD, + MSS_UART_DATA_8_BITS | MSS_UART_NO_PARITY | MSS_UART_ONE_STOP_BIT); +} +INIT_BOARD_EXPORT(boardInit); + +/* mss uart0 transmit one byte data */ +void MSS_UART_polled_tx_byte(mss_uart_instance_t *this_uart, const uint8_t byte) +{ + uint32_t tx_ready; + do { + tx_ready = gp_my_uart0->hw_reg->LSR & 0x20u; + } while(!tx_ready); + gp_my_uart0->hw_reg->THR = byte; +} + +/* docking finish component */ +void rt_hw_console_output(const char *str) +{ + while(*str != '\0') + { + if(*str == '\n') + MSS_UART_polled_tx_byte(gp_my_uart0, '\r'); + MSS_UART_polled_tx_byte(gp_my_uart0, *str++); + while(!MSS_UART_tx_complete(&g_mss_uart0)); + } +} + +/* docking finish component */ +char rt_hw_console_getchar(void) +{ + char dat; + uint8_t rx_size; + do { + rx_size = MSS_UART_get_rx(gp_my_uart0, (uint8_t *)&dat, 1); + } while(0u == rx_size); + return dat; +} + +/* custom finish command */ +extern uint32_t SystemCoreClock; +void sayHello(void) +{ + rt_kprintf("Hello RT-Thread! By SmartFusion2 M2S010\r\n"); + rt_kprintf("MSS System Core Clock: %d\r\n", SystemCoreClock); +} +MSH_CMD_EXPORT(sayHello, "say hello to console"); diff --git a/bsp/smartfusion2/user/config.h b/bsp/smartfusion2/user/config.h new file mode 100644 index 0000000000..f0f0ab1b26 --- /dev/null +++ b/bsp/smartfusion2/user/config.h @@ -0,0 +1,16 @@ +#ifndef __INIT_H__ +#define __INIT_H__ + +#include "mss_gpio.h" +#include "mss_uart.h" + +#include <rthw.h> +#include <rtthread.h> + +void boardInit(void); +void MSS_UART_polled_tx_byte(mss_uart_instance_t *this_uart, const uint8_t byte); +void rt_hw_console_output(const char *str); +char rt_hw_console_getchar(void); +void sayHello(void); + +#endif diff --git a/bsp/smartfusion2/user/main.c b/bsp/smartfusion2/user/main.c new file mode 100644 index 0000000000..d71ce7f934 --- /dev/null +++ b/bsp/smartfusion2/user/main.c @@ -0,0 +1,25 @@ +#include "config.h" +#include <rthw.h> +#include <rtthread.h> + +#define LED0_PIN MSS_GPIO_0 +#define LED1_PIN MSS_GPIO_1 + +int main(void) +{ + int count = 0; + + while(count++) + { + MSS_GPIO_set_output(LED0_PIN, 1); + MSS_GPIO_set_output(LED1_PIN, 1); + rt_thread_mdelay(500); + + MSS_GPIO_set_output(LED0_PIN, 0); + MSS_GPIO_set_output(LED1_PIN, 0); + rt_thread_mdelay(500); + } + + return RT_EOK; +} + diff --git a/bsp/smartfusion2/user/project.uvguix.whik b/bsp/smartfusion2/user/project.uvguix.whik new file mode 100644 index 0000000000..ea9ddd614e --- /dev/null +++ b/bsp/smartfusion2/user/project.uvguix.whik @@ -0,0 +1,1874 @@ +<?xml version="1.0" encoding="UTF-8" standalone="no" ?> +<ProjectGui xmlns:xsi="http://www.w3.org/2001/XMLSchema-instance" xsi:noNamespaceSchemaLocation="project_guix.xsd"> + + <SchemaVersion>-6.1</SchemaVersion> + + <Header>### uVision Project, (C) Keil Software</Header> + + <ViewPool/> + + <SECTreeCtrl> + <View> + <WinId>38003</WinId> + <ViewName>Registers</ViewName> + <TableColWidths>163 163</TableColWidths> + </View> + <View> + <WinId>346</WinId> + <ViewName>Code Coverage</ViewName> + <TableColWidths>720 160</TableColWidths> + </View> + <View> + <WinId>204</WinId> + <ViewName>Performance Analyzer</ViewName> + <TableColWidths>880</TableColWidths> + </View> + </SECTreeCtrl> + + <TreeListPane> + <View> + <WinId>35141</WinId> + <ViewName>Event Statistics</ViewName> + <UserString></UserString> + <TableColWidths>200 50 700</TableColWidths> + </View> + <View> + <WinId>1506</WinId> + <ViewName>Symbols</ViewName> + <UserString></UserString> + <TableColWidths>80 80 80</TableColWidths> + </View> + <View> + <WinId>1936</WinId> + <ViewName>Watch 1</ViewName> + <UserString></UserString> + <TableColWidths>200 133 133</TableColWidths> + </View> + <View> + <WinId>1937</WinId> + <ViewName>Watch 2</ViewName> + <UserString></UserString> + <TableColWidths>200 133 133</TableColWidths> + </View> + <View> + <WinId>1935</WinId> + <ViewName>Call Stack + Locals</ViewName> + <UserString></UserString> + <TableColWidths>200 133 133</TableColWidths> + </View> + <View> + <WinId>2506</WinId> + <ViewName>Trace Data</ViewName> + <UserString></UserString> + <TableColWidths>75 135 130 95 70 230 200 150</TableColWidths> + </View> + <View> + <WinId>466</WinId> + <ViewName>Source Browser</ViewName> + <UserString>500</UserString> + <TableColWidths>300</TableColWidths> + </View> + </TreeListPane> + + <CompViewPool/> + + <WindowSettings> + <LogicAnalizer> + <ShowLACursor>1</ShowLACursor> + <ShowSignalInfo>1</ShowSignalInfo> + <ShowCycles>0</ShowCycles> + <LeftSideBarSize>0</LeftSideBarSize> + <TimeBaseIndex>-1</TimeBaseIndex> + </LogicAnalizer> + </WindowSettings> + + <WinLayoutEx> + <sActiveDebugView></sActiveDebugView> + <WindowPosition> + <length>44</length> + <flags>2</flags> + <showCmd>3</showCmd> + <MinPosition> + <xPos>-1</xPos> + <yPos>-1</yPos> + </MinPosition> + <MaxPosition> + <xPos>-1</xPos> + <yPos>-1</yPos> + </MaxPosition> + <NormalPosition> + <Top>180</Top> + <Left>180</Left> + <Right>1332</Right> + <Bottom>776</Bottom> + </NormalPosition> + </WindowPosition> + <MDIClientArea> + <RegID>0</RegID> + <MDITabState> + <Len>244</Len> + <Data>01000000040000000100000001000000010000000100000000000000020000000000000001000000010000000000000028000000280000000100000001000000000000000100000030443A5C4D7946696C655C72742D7468726561645C6273705C736D617274667573696F6E325C757365725C6D61696E2E6300000000066D61696E2E6300000000C5D4F200FFFFFFFF0100000010000000C5D4F200FFDC7800BECEA100F0A0A100BCA8E1009CC1B600F7B88600D9ADC200A5C2D700B3A6BE00EAD6A300F6FA7D00B5E99D005FC3CF00C1838300CACAD500010000000000000002000000540100006E000000800700008E020000</Data> + </MDITabState> + </MDIClientArea> + <ViewEx> + <ViewType>0</ViewType> + <ViewName>Build</ViewName> + <Window> + <RegID>-1</RegID> + <PaneID>-1</PaneID> + <IsVisible>0</IsVisible> + <IsFloating>0</IsFloating> + <IsTabbed>0</IsTabbed> + <IsActivated>0</IsActivated> + <MRUWidth>32767</MRUWidth> + <PinState>0</PinState> + <RecentFrameAlignment>4096</RecentFrameAlignment> + <RecentRowIndex>0</RecentRowIndex> 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<RecentFrameAlignment>4096</RecentFrameAlignment> + <RecentRowIndex>0</RecentRowIndex> + <RectRecentDocked> + <Len>16</Len> + <Data>03000000730000004D01000054020000</Data> + </RectRecentDocked> + <RectRecentFloat> + <Len>16</Len> + <Data>630000007E0000004501000037020000</Data> + </RectRecentFloat> + </Window> + <Window> + <RegID>1465</RegID> + <PaneID>1465</PaneID> + <IsVisible>0</IsVisible> + <IsFloating>0</IsFloating> + <IsTabbed>0</IsTabbed> + <IsActivated>0</IsActivated> + <MRUWidth>32767</MRUWidth> + <PinState>0</PinState> + <RecentFrameAlignment>4096</RecentFrameAlignment> + <RecentRowIndex>0</RecentRowIndex> + <RectRecentDocked> + <Len>16</Len> + <Data>03000000A30100006B040000EF010000</Data> + </RectRecentDocked> + <RectRecentFloat> + <Len>16</Len> + <Data>630000007E0000009A020000EC000000</Data> + </RectRecentFloat> + </Window> + <Window> + <RegID>1466</RegID> + <PaneID>1466</PaneID> + <IsVisible>0</IsVisible> + <IsFloating>0</IsFloating> + <IsTabbed>0</IsTabbed> + <IsActivated>0</IsActivated> + <MRUWidth>32767</MRUWidth> + <PinState>0</PinState> + <RecentFrameAlignment>4096</RecentFrameAlignment> + <RecentRowIndex>0</RecentRowIndex> + <RectRecentDocked> + <Len>16</Len> + <Data>03000000A30100006B040000EF010000</Data> + </RectRecentDocked> + <RectRecentFloat> + <Len>16</Len> + <Data>630000007E0000009A020000EC000000</Data> + </RectRecentFloat> + </Window> + <Window> + <RegID>1467</RegID> + <PaneID>1467</PaneID> + <IsVisible>0</IsVisible> + <IsFloating>0</IsFloating> + <IsTabbed>0</IsTabbed> + <IsActivated>0</IsActivated> + <MRUWidth>32767</MRUWidth> + <PinState>0</PinState> + <RecentFrameAlignment>4096</RecentFrameAlignment> + <RecentRowIndex>0</RecentRowIndex> + <RectRecentDocked> + <Len>16</Len> + <Data>03000000A30100006B040000EF010000</Data> + </RectRecentDocked> + <RectRecentFloat> + <Len>16</Len> + <Data>630000007E0000009A020000EC000000</Data> + </RectRecentFloat> + </Window> + <Window> + <RegID>1468</RegID> + <PaneID>1468</PaneID> + <IsVisible>0</IsVisible> + <IsFloating>0</IsFloating> + <IsTabbed>0</IsTabbed> + <IsActivated>0</IsActivated> + <MRUWidth>32767</MRUWidth> + <PinState>0</PinState> + <RecentFrameAlignment>4096</RecentFrameAlignment> + <RecentRowIndex>0</RecentRowIndex> + <RectRecentDocked> + <Len>16</Len> + <Data>03000000A30100006B040000EF010000</Data> + </RectRecentDocked> + <RectRecentFloat> + <Len>16</Len> + <Data>630000007E0000009A020000EC000000</Data> + </RectRecentFloat> + </Window> + <Window> + <RegID>1506</RegID> + <PaneID>1506</PaneID> + <IsVisible>0</IsVisible> + <IsFloating>0</IsFloating> + <IsTabbed>0</IsTabbed> + <IsActivated>0</IsActivated> + <MRUWidth>32767</MRUWidth> + <PinState>0</PinState> + <RecentFrameAlignment>16384</RecentFrameAlignment> + <RecentRowIndex>0</RecentRowIndex> + <RectRecentDocked> + <Len>16</Len> + <Data>81030000730000006B0400007D010000</Data> + </RectRecentDocked> + <RectRecentFloat> + <Len>16</Len> + <Data>630000007E0000005301000047010000</Data> + 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<RectRecentFloat> + <Len>16</Len> + <Data>630000007E0000005301000047010000</Data> + </RectRecentFloat> + </Window> + <Window> + <RegID>1936</RegID> + <PaneID>1936</PaneID> + <IsVisible>0</IsVisible> + <IsFloating>0</IsFloating> + <IsTabbed>0</IsTabbed> + <IsActivated>0</IsActivated> + <MRUWidth>32767</MRUWidth> + <PinState>0</PinState> + <RecentFrameAlignment>4096</RecentFrameAlignment> + <RecentRowIndex>0</RecentRowIndex> + <RectRecentDocked> + <Len>16</Len> + <Data>03000000A30100006B040000EF010000</Data> + </RectRecentDocked> + <RectRecentFloat> + <Len>16</Len> + <Data>630000007E0000005301000047010000</Data> + </RectRecentFloat> + </Window> + <Window> + <RegID>1937</RegID> + <PaneID>1937</PaneID> + <IsVisible>0</IsVisible> + <IsFloating>0</IsFloating> + <IsTabbed>0</IsTabbed> + <IsActivated>0</IsActivated> + <MRUWidth>32767</MRUWidth> + <PinState>0</PinState> + <RecentFrameAlignment>4096</RecentFrameAlignment> + <RecentRowIndex>0</RecentRowIndex> + <RectRecentDocked> + <Len>16</Len> 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<FilePath>..\HAL\CortexM3\Keil\hal.s</FilePath> + </File> + </Files> + </Group> + <Group> + <GroupName>CMSIS</GroupName> + <Files> + <File> + <FileName>system_m2sxxx.c</FileName> + <FileType>1</FileType> + <FilePath>..\CMSIS\system_m2sxxx.c</FilePath> + </File> + <File> + <FileName>startup_m2sxxx.s</FileName> + <FileType>2</FileType> + <FilePath>..\CMSIS\startup_arm\startup_m2sxxx.s</FilePath> + </File> + <File> + <FileName>core_cm3.c</FileName> + <FileType>1</FileType> + <FilePath>..\CMSIS\core_cm3.c</FilePath> + </File> + </Files> + </Group> + <Group> + <GroupName>RT-Thread/Kernel</GroupName> + <Files> + <File> + <FileName>clock.c</FileName> + <FileType>1</FileType> + <FilePath>..\..\..\src\clock.c</FilePath> + </File> + <File> + <FileName>components.c</FileName> + <FileType>1</FileType> + <FilePath>..\..\..\src\components.c</FilePath> + </File> + <File> + <FileName>cpu.c</FileName> + <FileType>1</FileType> + <FilePath>..\..\..\src\cpu.c</FilePath> + </File> + <File> + <FileName>device.c</FileName> + <FileType>1</FileType> + <FilePath>..\..\..\src\device.c</FilePath> + </File> + <File> + <FileName>idle.c</FileName> + <FileType>1</FileType> + <FilePath>..\..\..\src\idle.c</FilePath> + </File> + <File> + <FileName>ipc.c</FileName> + <FileType>1</FileType> + <FilePath>..\..\..\src\ipc.c</FilePath> + </File> + <File> + <FileName>irq.c</FileName> + <FileType>1</FileType> + <FilePath>..\..\..\src\irq.c</FilePath> + </File> + <File> + <FileName>kservice.c</FileName> + <FileType>1</FileType> + <FilePath>..\..\..\src\kservice.c</FilePath> + </File> + <File> + <FileName>mem.c</FileName> + <FileType>1</FileType> + <FilePath>..\..\..\src\mem.c</FilePath> + </File> + <File> + <FileName>memheap.c</FileName> + <FileType>1</FileType> + <FilePath>..\..\..\src\memheap.c</FilePath> + </File> + <File> + <FileName>mempool.c</FileName> + <FileType>1</FileType> + <FilePath>..\..\..\src\mempool.c</FilePath> + </File> + <File> + <FileName>object.c</FileName> + <FileType>1</FileType> + <FilePath>..\..\..\src\object.c</FilePath> + </File> + <File> + <FileName>scheduler.c</FileName> + <FileType>1</FileType> + <FilePath>..\..\..\src\scheduler.c</FilePath> + </File> + <File> + <FileName>signal.c</FileName> + <FileType>1</FileType> + <FilePath>..\..\..\src\signal.c</FilePath> + </File> + <File> + <FileName>slab.c</FileName> + <FileType>1</FileType> + <FilePath>..\..\..\src\slab.c</FilePath> + </File> + <File> + <FileName>thread.c</FileName> + <FileType>1</FileType> + <FilePath>..\..\..\src\thread.c</FilePath> + </File> + <File> + <FileName>timer.c</FileName> + <FileType>1</FileType> + <FilePath>..\..\..\src\timer.c</FilePath> + </File> + </Files> + </Group> + <Group> + <GroupName>RT-Thread/Libcpu</GroupName> + <Files> + <File> + <FileName>cpuport.c</FileName> + <FileType>1</FileType> + <FilePath>..\..\..\libcpu\arm\cortex-m3\cpuport.c</FilePath> + </File> + <File> + <FileName>context_rvds.S</FileName> + <FileType>2</FileType> + <FilePath>..\..\..\libcpu\arm\cortex-m3\context_rvds.S</FilePath> + </File> + </Files> + </Group> + <Group> + <GroupName>RT-Thread/Finsh</GroupName> + <Files> + <File> + <FileName>cmd.c</FileName> + <FileType>1</FileType> + <FilePath>..\..\..\components\finsh\cmd.c</FilePath> + </File> + <File> + <FileName>finsh_compiler.c</FileName> + <FileType>1</FileType> + <FilePath>..\..\..\components\finsh\finsh_compiler.c</FilePath> + </File> + <File> + <FileName>finsh_error.c</FileName> + <FileType>1</FileType> + <FilePath>..\..\..\components\finsh\finsh_error.c</FilePath> + </File> + <File> + <FileName>finsh_heap.c</FileName> + <FileType>1</FileType> + <FilePath>..\..\..\components\finsh\finsh_heap.c</FilePath> + </File> + <File> + <FileName>finsh_init.c</FileName> + <FileType>1</FileType> + <FilePath>..\..\..\components\finsh\finsh_init.c</FilePath> + </File> + <File> + <FileName>finsh_node.c</FileName> + <FileType>1</FileType> + <FilePath>..\..\..\components\finsh\finsh_node.c</FilePath> + </File> + <File> + <FileName>finsh_ops.c</FileName> + <FileType>1</FileType> + <FilePath>..\..\..\components\finsh\finsh_ops.c</FilePath> + </File> + <File> + <FileName>finsh_parser.c</FileName> + <FileType>1</FileType> + <FilePath>..\..\..\components\finsh\finsh_parser.c</FilePath> + </File> + <File> + <FileName>finsh_token.c</FileName> + <FileType>1</FileType> + <FilePath>..\..\..\components\finsh\finsh_token.c</FilePath> + </File> + <File> + <FileName>finsh_var.c</FileName> + <FileType>1</FileType> + <FilePath>..\..\..\components\finsh\finsh_var.c</FilePath> + </File> + <File> + <FileName>finsh_vm.c</FileName> + <FileType>1</FileType> + <FilePath>..\..\..\components\finsh\finsh_vm.c</FilePath> + </File> + <File> + <FileName>msh.c</FileName> + <FileType>1</FileType> + <FilePath>..\..\..\components\finsh\msh.c</FilePath> + </File> + <File> + <FileName>msh_file.c</FileName> + <FileType>1</FileType> + <FilePath>..\..\..\components\finsh\msh_file.c</FilePath> + </File> + <File> + <FileName>shell.c</FileName> + <FileType>1</FileType> + <FilePath>..\..\..\components\finsh\shell.c</FilePath> + </File> + <File> + <FileName>symbol.c</FileName> + <FileType>1</FileType> + <FilePath>..\..\..\components\finsh\symbol.c</FilePath> + </File> + </Files> + </Group> + </Groups> + </Target> + </Targets> + + <RTE> + <apis/> + <components/> + <files> + <file attr="config" category="source" name="bsp\board.c" version="3.1.3"> + <instance index="0" removed="1">RTE\RTOS\board.c</instance> + <component Cbundle="RT-Thread" Cclass="RTOS" Cgroup="kernel" Cvendor="RealThread" Cversion="3.1.3" condition="CMSIS Core with RTOS"/> + <package license="License.txt" name="RT-Thread" schemaVersion="1.4" supportContact="https://www.rt-thread.org" url="https://www.rt-thread.org/download/mdk/" vendor="RealThread" version="3.1.3"/> + <targetInfos/> + </file> + <file attr="config" category="header" name="bsp\rtconfig.h" version="3.1.3"> + <instance index="0" removed="1">RTE\RTOS\rtconfig.h</instance> + <component Cbundle="RT-Thread" Cclass="RTOS" Cgroup="kernel" Cvendor="RealThread" Cversion="3.1.3" condition="CMSIS Core with RTOS"/> + <package license="License.txt" name="RT-Thread" schemaVersion="1.4" supportContact="https://www.rt-thread.org" url="https://www.rt-thread.org/download/mdk/" vendor="RealThread" version="3.1.3"/> + <targetInfos/> + </file> + </files> + </RTE> + +</Project> diff --git a/bsp/smartfusion2/user/rtconfig.h b/bsp/smartfusion2/user/rtconfig.h new file mode 100644 index 0000000000..c985b8583c --- /dev/null +++ b/bsp/smartfusion2/user/rtconfig.h @@ -0,0 +1,160 @@ +/* RT-Thread config file */ + +#ifndef __RTTHREAD_CFG_H__ +#define __RTTHREAD_CFG_H__ + +#if defined(__CC_ARM) || defined(__CLANG_ARM) +//#include "RTE_Components.h" + +#define RT_USING_FINSH +#if defined(RTE_USING_FINSH) +#define RT_USING_FINSH +#endif //RTE_USING_FINSH + +#endif //(__CC_ARM) || (__CLANG_ARM) + +// <<< Use Configuration Wizard in Context Menu >>> +// <h>Basic Configuration +// <o>Maximal level of thread priority <8-256> +// <i>Default: 32 +#define RT_THREAD_PRIORITY_MAX 8 +// <o>OS tick per second +// <i>Default: 1000 (1ms) +#define RT_TICK_PER_SECOND 1000 +// <o>Alignment size for CPU architecture data access +// <i>Default: 4 +#define RT_ALIGN_SIZE 4 +// <o>the max length of object name<2-16> +// <i>Default: 8 +#define RT_NAME_MAX 8 +// <c1>Using RT-Thread components initialization +// <i>Using RT-Thread components initialization +#define RT_USING_COMPONENTS_INIT +// </c> + +#define RT_USING_USER_MAIN +//#define RT_USING_DEVICE +//#define RT_USING_PIN +//#define RT_USING_SERIAL +//#define RT_CONSOLE_DEVICE_NAME "uart0" +//#define RT_CONSOLEBUF_SIZE 128 + +// <o>the stack size of main thread<1-4086> +// <i>Default: 512 +#define RT_MAIN_THREAD_STACK_SIZE 512 + +// </h> + +// <h>Debug Configuration +// <c1>enable kernel debug configuration +// <i>Default: enable kernel debug configuration +//#define RT_DEBUG +// </c> +// <o>enable components initialization debug configuration<0-1> +// <i>Default: 0 +#define RT_DEBUG_INIT 0 +// <c1>thread stack over flow detect +// <i> Diable Thread stack over flow detect +//#define RT_USING_OVERFLOW_CHECK +// </c> +// </h> + +// <h>Hook Configuration +// <c1>using hook +// <i>using hook +//#define RT_USING_HOOK +// </c> +// <c1>using idle hook +// <i>using idle hook +//#define RT_USING_IDLE_HOOK +// </c> +// </h> + +// <e>Software timers Configuration +// <i> Enables user timers +#define RT_USING_TIMER_SOFT 0 +#if RT_USING_TIMER_SOFT == 0 + #undef RT_USING_TIMER_SOFT +#endif +// <o>The priority level of timer thread <0-31> +// <i>Default: 4 +#define RT_TIMER_THREAD_PRIO 4 +// <o>The stack size of timer thread <0-8192> +// <i>Default: 512 +#define RT_TIMER_THREAD_STACK_SIZE 512 +// </e> + +// <h>IPC(Inter-process communication) Configuration +// <c1>Using Semaphore +// <i>Using Semaphore +#define RT_USING_SEMAPHORE +// </c> +// <c1>Using Mutex +// <i>Using Mutex +#define RT_USING_MUTEX +// </c> +// <c1>Using Event +// <i>Using Event +#define RT_USING_EVENT +// </c> +// <c1>Using MailBox +// <i>Using MailBox +#define RT_USING_MAILBOX +// </c> +// <c1>Using Message Queue +// <i>Using Message Queue +#define RT_USING_MESSAGEQUEUE +// </c> +// </h> + +// <h>Memory Management Configuration +// <c1>Dynamic Heap Management +// <i>Dynamic Heap Management +#define RT_USING_HEAP +// </c> +// <c1>using small memory +// <i>using small memory +#define RT_USING_SMALL_MEM +// </c> +// <c1>using tiny size of memory +// <i>using tiny size of memory +//#define RT_USING_TINY_SIZE +// </c> +// </h> + +// <h>Console Configuration +// <c1>Using console +// <i>Using console +#define RT_USING_CONSOLE +// </c> +// <o>the buffer size of console <1-1024> +// <i>the buffer size of console +// <i>Default: 128 (128Byte) +#define RT_CONSOLEBUF_SIZE 128 +// </h> + +#if defined(RT_USING_FINSH) + #define FINSH_USING_MSH + #define FINSH_USING_MSH_ONLY + // <h>Finsh Configuration + // <o>the priority of finsh thread <1-7> + // <i>the priority of finsh thread + // <i>Default: 6 + #define __FINSH_THREAD_PRIORITY 5 + #define FINSH_THREAD_PRIORITY (RT_THREAD_PRIORITY_MAX / 8 * __FINSH_THREAD_PRIORITY + 1) + // <o>the stack of finsh thread <1-4096> + // <i>the stack of finsh thread + // <i>Default: 4096 (4096Byte) + #define FINSH_THREAD_STACK_SIZE 1024 + // <o>the history lines of finsh thread <1-32> + // <i>the history lines of finsh thread + // <i>Default: 5 + #define FINSH_HISTORY_LINES 5 + + #define FINSH_USING_SYMTAB + // </h> +#endif + +// <<< end of configuration section >>> + +#endif |