diff options
| -rw-r--r-- | bsp/rm48x50/HALCoGen/source/dabort.asm | 98 | ||||
| -rw-r--r-- | bsp/rm48x50/HALCoGen/source/esm.c | 713 | ||||
| -rw-r--r-- | bsp/rm48x50/HALCoGen/source/notification.c | 125 | ||||
| -rw-r--r-- | bsp/rm48x50/HALCoGen/source/pinmux.c | 121 | ||||
| -rw-r--r-- | bsp/rm48x50/HALCoGen/source/rti.c | 28 | ||||
| -rw-r--r-- | bsp/rm48x50/HALCoGen/source/sci.c | 549 | ||||
| -rw-r--r-- | bsp/rm48x50/HALCoGen/source/sys_core.asm | 291 | ||||
| -rw-r--r-- | bsp/rm48x50/HALCoGen/source/sys_dma.c | 322 | ||||
| -rw-r--r-- | bsp/rm48x50/HALCoGen/source/sys_intvecs.asm | 16 | ||||
| -rw-r--r-- | bsp/rm48x50/HALCoGen/source/sys_main.c | 82 | ||||
| -rw-r--r-- | bsp/rm48x50/HALCoGen/source/sys_mpu.asm | 403 | ||||
| -rw-r--r-- | bsp/rm48x50/HALCoGen/source/sys_pcr.c | 602 | ||||
| -rw-r--r-- | bsp/rm48x50/HALCoGen/source/sys_phantom.c | 32 | ||||
| -rw-r--r-- | bsp/rm48x50/HALCoGen/source/sys_pmm.c | 348 | ||||
| -rw-r--r-- | bsp/rm48x50/HALCoGen/source/sys_pmu.asm | 223 | ||||
| -rw-r--r-- | bsp/rm48x50/HALCoGen/source/sys_selftest.c | 2178 | ||||
| -rw-r--r-- | bsp/rm48x50/HALCoGen/source/sys_startup.c | 367 | ||||
| -rw-r--r-- | bsp/rm48x50/HALCoGen/source/sys_vim.c | 148 | ||||
| -rw-r--r-- | bsp/rm48x50/HALCoGen/source/system.c | 7 |
19 files changed, 142 insertions, 6511 deletions
diff --git a/bsp/rm48x50/HALCoGen/source/dabort.asm b/bsp/rm48x50/HALCoGen/source/dabort.asm deleted file mode 100644 index dcc88229e4..0000000000 --- a/bsp/rm48x50/HALCoGen/source/dabort.asm +++ /dev/null @@ -1,98 +0,0 @@ -;------------------------------------------------------------------------------- -; dabort.asm -; -; (c) Texas Instruments 2009-2013, All rights reserved. -; - - .text - .arm - - -;------------------------------------------------------------------------------- -; Run Memory Test - - .ref custom_dabort - .def _dabort - .asmfunc - -_dabort - stmfd r13!, {r0 - r12, lr}; push registers and link register on to stack - - ldr r12, esmsr3 ; ESM Group3 status register - ldr r0, [r12] - tst r0, #0x8 ; check if bit 3 is set, this indicates uncorrectable ECC error on B0TCM - bne ramErrorFound - tst r0, #0x20 ; check if bit 5 is set, this indicates uncorrectable ECC error on B1TCM - bne ramErrorFound - -noRAMerror - tst r0, #0x80 ; check if bit 7 is set, this indicates uncorrectable ECC error on ATCM - bne flashErrorFound - - bl custom_dabort ; custom data abort handler required - ; If this custom handler is written in assembly, all registers used in the routine - ; and the link register must be saved on to the stack upon entry, and restored before - ; return from the routine. - - ldmfd r13!, {r0 - r12, lr}; pop registers and link register from stack - subs pc, lr, #8 ; restore state of CPU when abort occurred, and branch back to instruction that was aborted - -ramErrorFound - ldr r1, ramctrl ; RAM control register for B0TCM TCRAMW - ldr r2, [r1] - tst r2, #0x100 ; check if bit 8 is set in RAMCTRL, this indicates ECC memory write is enabled - beq ramErrorReal - mov r2, #0x20 - str r2, [r1, #0x10] ; clear RAM error status register - ldr r1, ram2ctrl - str r2, [r1, #0x10] ; clear RAM error status register - - mov r2, #0x28 - str r2, [r12] ; clear ESM group3 flags for uncorrectable RAM ECC errors - mov r2, #5 - str r2, [r12, #0x18] ; The nERROR pin will become inactive once the LTC counter expires - - ldmfd r13!, {r0 - r12, lr} - subs pc, lr, #4 ; branch to instruction after the one that caused the abort - ; this is the case because the data abort was caused intentionally - ; and we do not want to cause the same data abort again. - -ramErrorReal - b ramErrorReal ; branch here forever as continuing operation is not recommended - -flashErrorFound - ldr r1, flashbase - ldr r2, [r1, #0x6C] ; read FDIAGCTRL register - - mov r2, r2, lsr #16 - tst r2, #5 ; check if bits 19:16 are 5, this indicates diagnostic mode is enabled - beq flashErrorReal - mov r2, #1 - mov r2, r2, lsl #8 - - str r2, [r1, #0x1C] ; clear FEDACSTATUS error flag - - mov r2, #0x80 - str r2, [r12] ; clear ESM group3 flag for uncorrectable flash ECC error - mov r2, #5 - str r2, [r12, #0x18] ; The nERROR pin will become inactive once the LTC counter expires - - ldmfd r13!, {r0 - r12, lr} - subs pc, lr, #4 ; branch to instruction after the one that caused the abort - ; this is the case because the data abort was caused intentionally - ; and we do not want to cause the same data abort again. - - -flashErrorReal - b flashErrorReal ; branch here forever as continuing operation is not recommended - -esmsr3 .word 0xFFFFF520 -ramctrl .word 0xFFFFF800 -ram2ctrl .word 0xFFFFF900 -ram1errstat .word 0xFFFFF810 -ram2errstat .word 0xFFFFF910 -flashbase .word 0xFFF87000 - - .endasmfunc - - diff --git a/bsp/rm48x50/HALCoGen/source/esm.c b/bsp/rm48x50/HALCoGen/source/esm.c deleted file mode 100644 index a56e32950d..0000000000 --- a/bsp/rm48x50/HALCoGen/source/esm.c +++ /dev/null @@ -1,713 +0,0 @@ -/** @file esm.c -* @brief Esm Driver Source File -* @date 29.May.2013 -* @version 03.05.02 -* -* This file contains: -* - API Functions -* . -* which are relevant for the Esm driver. -*/ - -/* (c) Texas Instruments 2009-2013, All rights reserved. */ - -/* USER CODE BEGIN (0) */ -/* USER CODE END */ - -/* Include Files */ - -#include "esm.h" - -/* USER CODE BEGIN (1) */ -/* USER CODE END */ - - -/** @fn void esmInit(void) -* @brief Initializes Esm Driver -* -* This function initializes the Esm driver. -* -*/ - -/* USER CODE BEGIN (2) */ -/* USER CODE END */ - -void esmInit(void) -{ -/* USER CODE BEGIN (3) */ -/* USER CODE END */ - - /** - Disable error pin channels */ - esmREG->EPENACLR1 = 0xFFFFFFFFU; - esmREG->EPENACLR4 = 0xFFFFFFFFU; - - /** - Disable interrupts */ - esmREG->INTENACLR1 = 0xFFFFFFFFU; - esmREG->INTENACLR4 = 0xFFFFFFFFU; - - /** - Clear error status flags */ - esmREG->ESTATUS1[0U] = 0xFFFFFFFFU; - esmREG->ESTATUS1[1U] = 0xFFFFFFFFU; - esmREG->ESTATUS2EMU = 0xFFFFFFFFU; - esmREG->ESTATUS1[2U] = 0xFFFFFFFFU; - esmREG->ESTATUS4[0U] = 0xFFFFFFFFU; - esmREG->ESTATUS4[1U] = 0xFFFFFFFFU; - esmREG->ESTATUS5EMU = 0xFFFFFFFFU; - esmREG->ESTATUS4[2U] = 0xFFFFFFFFU; - - /** - Setup LPC preload */ - esmREG->LTCPRELOAD = 16384U - 1U; - - /** - Reset error pin */ - if (esmREG->EPSTATUS == 0U) - { - esmREG->KEY = 0x00000005U; - } - else - { - esmREG->KEY = 0x00000000U; - } - - /** - Clear interrupt level */ - esmREG->INTLVLCLR1 = 0xFFFFFFFFU; - esmREG->INTLVLCLR4 = 0xFFFFFFFFU; - - /** - Set interrupt level */ - esmREG->INTLVLSET1 = (0U << 31U) - | (0U << 30U) - | (0U << 29U) - | (0U << 28U) - | (0U << 27U) - | (0U << 26U) - | (0U << 25U) - | (0U << 24U) - | (0U << 23U) - | (0U << 22U) - | (0U << 21U) - | (0U << 20U) - | (0U << 19U) - | (0U << 18U) - | (0U << 17U) - | (0U << 16U) - | (0U << 15U) - | (0U << 14U) - | (0U << 13U) - | (0U << 12U) - | (0U << 11U) - | (0U << 10U) - | (0U << 9U) - | (0U << 8U) - | (0U << 7U) - | (0U << 6U) - | (0U << 5U) - | (0U << 4U) - | (0U << 3U) - | (0U << 2U) - | (0U << 1U) - | (0U); - - esmREG->INTLVLSET4 = (0U << 31U) - | (0U << 30U) - | (0U << 29U) - | (0U << 28U) - | (0U << 27U) - | (0U << 26U) - | (0U << 25U) - | (0U << 24U) - | (0U << 23U) - | (0U << 22U) - | (0U << 21U) - | (0U << 20U) - | (0U << 19U) - | (0U << 18U) - | (0U << 17U) - | (0U << 16U) - | (0U << 15U) - | (0U << 14U) - | (0U << 13U) - | (0U << 12U) - | (0U << 11U) - | (0U << 10U) - | (0U << 9U) - | (0U << 8U) - | (0U << 7U) - | (0U << 6U) - | (0U << 5U) - | (0U << 4U) - | (0U << 3U) - | (0U << 2U) - | (0U << 1U) - | (0U); - - /** - Enable error pin channels */ - esmREG->EPENASET1 = (0U << 31U) - | (0U << 30U) - | (0U << 29U) - | (0U << 28U) - | (0U << 27U) - | (0U << 26U) - | (0U << 25U) - | (0U << 24U) - | (0U << 23U) - | (0U << 22U) - | (0U << 21U) - | (0U << 20U) - | (0U << 19U) - | (0U << 18U) - | (0U << 17U) - | (0U << 16U) - | (0U << 15U) - | (0U << 14U) - | (0U << 13U) - | (0U << 12U) - | (0U << 11U) - | (0U << 10U) - | (0U << 9U) - | (0U << 8U) - | (0U << 7U) - | (0U << 6U) - | (0U << 5U) - | (0U << 4U) - | (0U << 3U) - | (0U << 2U) - | (0U << 1U) - | (0U); - - esmREG->EPENASET4 = (0U << 31U) - | (0U << 30U) - | (0U << 29U) - | (0U << 28U) - | (0U << 27U) - | (0U << 26U) - | (0U << 25U) - | (0U << 24U) - | (0U << 23U) - | (0U << 22U) - | (0U << 21U) - | (0U << 20U) - | (0U << 19U) - | (0U << 18U) - | (0U << 17U) - | (0U << 16U) - | (0U << 15U) - | (0U << 14U) - | (0U << 13U) - | (0U << 12U) - | (0U << 11U) - | (0U << 10U) - | (0U << 9U) - | (0U << 8U) - | (0U << 7U) - | (0U << 6U) - | (0U << 5U) - | (0U << 4U) - | (0U << 3U) - | (0U << 2U) - | (0U << 1U) - | (0U); - - /** - Enable interrupts */ - esmREG->INTENASET1 = (0U << 31U) - | (0U << 30U) - | (0U << 29U) - | (0U << 28U) - | (0U << 27U) - | (0U << 26U) - | (0U << 25U) - | (0U << 24U) - | (0U << 23U) - | (0U << 22U) - | (0U << 21U) - | (0U << 20U) - | (0U << 19U) - | (0U << 18U) - | (0U << 17U) - | (0U << 16U) - | (0U << 15U) - | (0U << 14U) - | (0U << 13U) - | (0U << 12U) - | (0U << 11U) - | (0U << 10U) - | (0U << 9U) - | (0U << 8U) - | (0U << 7U) - | (0U << 6U) - | (0U << 5U) - | (0U << 4U) - | (0U << 3U) - | (0U << 2U) - | (0U << 1U) - | (0U); - - esmREG->INTENASET4 = (0U << 31U) - | (0U << 30U) - | (0U << 29U) - | (0U << 28U) - | (0U << 27U) - | (0U << 26U) - | (0U << 25U) - | (0U << 24U) - | (0U << 23U) - | (0U << 22U) - | (0U << 21U) - | (0U << 20U) - | (0U << 19U) - | (0U << 18U) - | (0U << 17U) - | (0U << 16U) - | (0U << 15U) - | (0U << 14U) - | (0U << 13U) - | (0U << 12U) - | (0U << 11U) - | (0U << 10U) - | (0U << 9U) - | (0U << 8U) - | (0U << 7U) - | (0U << 6U) - | (0U << 5U) - | (0U << 4U) - | (0U << 3U) - | (0U << 2U) - | (0U << 1U) - | (0U); - -/* USER CODE BEGIN (4) */ -/* USER CODE END */ -} - - -/** @fn uint32 esmError(void) -* @brief Return Error status -* -* @return The error status -* -* Returns the error status. -*/ -uint32 esmError(void) -{ - uint32 status; - -/* USER CODE BEGIN (5) */ -/* USER CODE END */ - - status = esmREG->EPSTATUS; - -/* USER CODE BEGIN (6) */ -/* USER CODE END */ - - return status; -} - - -/** @fn void esmEnableError(uint64 channels) -* @brief Enable Group 1 Channels Error Signals propagation -* -* @param[in] channels - Channel mask -* -* Enable Group 1 Channels Error Signals propagation to the error pin. -*/ -void esmEnableError(uint64 channels) -{ -/* USER CODE BEGIN (7) */ -/* USER CODE END */ - - esmREG->EPENASET4 = (uint32)((channels >> 32U) & 0xFFFFFFFFU); - esmREG->EPENASET1 = (uint32)(channels & 0xFFFFFFFFU); - -/* USER CODE BEGIN (8) */ -/* USER CODE END */ -} - - -/** @fn void esmDisableError(uint64 channels) -* @brief Disable Group 1 Channels Error Signals propagation -* -* @param[in] channels - Channel mask -* -* Disable Group 1 Channels Error Signals propagation to the error pin. -*/ -void esmDisableError(uint64 channels) -{ -/* USER CODE BEGIN (9) */ -/* USER CODE END */ - - esmREG->EPENACLR4 = (uint32)((channels >> 32U) & 0xFFFFFFFFU); - esmREG->EPENACLR1 = (uint32)(channels & 0xFFFFFFFFU); - -/* USER CODE BEGIN (10) */ -/* USER CODE END */ -} - - -/** @fn void esmTriggerErrorPinReset(void) -* @brief Trigger error pin reset and switch back to normal operation -* -* Trigger error pin reset and switch back to normal operation. -*/ -void esmTriggerErrorPinReset(void) -{ -/* USER CODE BEGIN (11) */ -/* USER CODE END */ - - esmREG->KEY = 5U; - -/* USER CODE BEGIN (12) */ -/* USER CODE END */ -} - - -/** @fn void esmActivateNormalOperation(void) -* @brief Activate normal operation -* -* Activates normal operation mode. -*/ -void esmActivateNormalOperation(void) -{ -/* USER CODE BEGIN (13) */ -/* USER CODE END */ - - esmREG->KEY = 0U; - -/* USER CODE BEGIN (14) */ -/* USER CODE END */ -} - - -/** @fn void esmEnableInterrupt(uint64 channels) -* @brief Enable Group 1 Channels Interrupts -* -* @param[in] channels - Channel mask -* -* Enable Group 1 Channels Interrupts. -*/ -void esmEnableInterrupt(uint64 channels) -{ -/* USER CODE BEGIN (15) */ -/* USER CODE END */ - - esmREG->INTENASET4 = (uint32)((channels >> 32U) & 0xFFFFFFFFU); - esmREG->INTENASET1 = (uint32)(channels & 0xFFFFFFFFU); - -/* USER CODE BEGIN (16) */ -/* USER CODE END */ -} - - -/** @fn void esmDisableInterrupt(uint64 channels) -* @brief Disable Group 1 Channels Interrupts -* -* @param[in] channels - Channel mask -* -* Disable Group 1 Channels Interrupts. -*/ -void esmDisableInterrupt(uint64 channels) -{ -/* USER CODE BEGIN (17) */ -/* USER CODE END */ - - esmREG->INTENACLR4 = (uint32)((channels >> 32U) & 0xFFFFFFFFU); - esmREG->INTENACLR1 = (uint32)(channels & 0xFFFFFFFFU); - -/* USER CODE BEGIN (18) */ -/* USER CODE END */ -} - - -/** @fn void esmSetInterruptLevel(uint64 channels, uint64 flags) -* @brief Set Group 1 Channels Interrupt Levels -* -* @param[in] channels - Channel mask -* @param[in] flags - Level mask: - 0: Low priority interrupt -* - 1: High priority interrupt -* -* Set Group 1 Channels Interrupts levels. -*/ -void esmSetInterruptLevel(uint64 channels, uint64 flags) -{ -/* USER CODE BEGIN (19) */ -/* USER CODE END */ - - esmREG->INTLVLCLR4 = (uint32)(((channels & (~flags)) >> 32U) & 0xFFFFFFFU); - esmREG->INTLVLSET4 = (uint32)(((channels & flags) >> 32U) & 0xFFFFFFFFU); - esmREG->INTLVLCLR1 = (uint32)((channels & (~flags)) & 0xFFFFFFFU); - esmREG->INTLVLSET1 = (uint32)((channels & flags) & 0xFFFFFFFFU); - -/* USER CODE BEGIN (20) */ -/* USER CODE END */ -} - - -/** @fn void esmClearStatus(uint32 group, uint64 channels) -* @brief Clear Group error status -* -* @param[in] group - Error group -* @param[in] channels - Channel mask -* -* Clear Group error status. -*/ -void esmClearStatus(uint32 group, uint64 channels) -{ -/* USER CODE BEGIN (21) */ -/* USER CODE END */ - - esmREG->ESTATUS4[group] = (uint32)((channels >> 32U) & 0xFFFFFFFFU); - esmREG->ESTATUS1[group] = (uint32)(channels & 0xFFFFFFFFU); - -/* USER CODE BEGIN (22) */ -/* USER CODE END */ -} - - -/** @fn void esmClearStatusBuffer(uint64 channels) -* @brief Clear Group 2 error status buffer -* -* @param[in] channels - Channel mask -* -* Clear Group 2 error status buffer. -*/ -void esmClearStatusBuffer(uint64 channels) -{ -/* USER CODE BEGIN (23) */ -/* USER CODE END */ - - esmREG->ESTATUS5EMU = (uint32)((channels >> 32U) & 0xFFFFFFFFU); - esmREG->ESTATUS2EMU = (uint32)(channels & 0xFFFFFFFFU); - -/* USER CODE BEGIN (24) */ -/* USER CODE END */ -} - - -/** @fn void esmSetCounterPreloadValue(uint32 value) -* @brief Set counter preload value -* -* @param[in] value - Counter preload value -* -* Set counter preload value. -*/ -void esmSetCounterPreloadValue(uint32 value) -{ -/* USER CODE BEGIN (25) */ -/* USER CODE END */ - - esmREG->LTCPRELOAD = value & 0xC000U; - -/* USER CODE BEGIN (26) */ -/* USER CODE END */ -} - - -/** @fn uint64 esmGetStatus(uint32 group, uint64 channels) -* @brief Return Error status -* -* @param[in] group - Error group -* @param[in] channels - Error Channels -* -* @return The channels status of selected group -* -* Returns the channels status of selected group. -*/ -uint64 esmGetStatus(uint32 group, uint64 channels) -{ - uint64 status; - -/* USER CODE BEGIN (27) */ -/* USER CODE END */ - /*SAFETYMCUSW 51 S MR:12.3 <REVIEWED> "Needs shifting for 64-bit value" */ - status = (((uint64)esmREG->ESTATUS4[group] << 32U) | (uint64)esmREG->ESTATUS1[group]) & channels; - -/* USER CODE BEGIN (28) */ -/* USER CODE END */ - - return status; -} - - -/** @fn uint64 esmGetStatusBuffer(uint64 channels) -* @brief Return Group 2 channel x Error status buffer -* -* @param[in] channels - Error Channels -* -* @return The channels status -* -* Returns the group 2 buffered status of selected channels. -*/ -uint64 esmGetStatusBuffer(uint64 channels) -{ - uint64 status; - -/* USER CODE BEGIN (29) */ -/* USER CODE END */ - /*SAFETYMCUSW 51 S MR:12.3 <REVIEWED> "Needs shifting for 64-bit value" */ - status = (((uint64)esmREG->ESTATUS5EMU << 32U) | (uint64)esmREG->ESTATUS2EMU) & channels; - -/* USER CODE BEGIN (30) */ -/* USER CODE END */ - - return status; -} - -/** @fn esmSelfTestFlag_t esmEnterSelfTest(void) -* @brief Return ESM Self test status -* -* @return ESM Self test status -* -* Returns the ESM Self test status. -*/ -esmSelfTestFlag_t esmEnterSelfTest(void) -{ - esmSelfTestFlag_t status; - -/* USER CODE BEGIN (31) */ -/* USER CODE END */ - - if(((esmREG->EPSTATUS & 0x1U) == 0x0U) && (esmREG->KEY == 0x0U)) - { - status = esmSelfTest_NotStarted; - } - else - { - esmREG->KEY = 0xAU; - status = esmSelfTest_Active; - if((esmREG->EPSTATUS & 0x1U) != 0x0U) - { - status = esmSelfTest_Failed; - } - esmREG->KEY = 0x5U; - } - -/* USER CODE BEGIN (32) */ -/* USER CODE END */ - - return status; -} - -/** @fn esmSelfTestFlag_t esmSelfTestStatus(void) -* @brief Return ESM Self test status -* -* Returns the ESM Self test status. -*/ -esmSelfTestFlag_t esmSelfTestStatus(void) -{ - esmSelfTestFlag_t status; - -/* USER CODE BEGIN (33) */ -/* USER CODE END */ - - if((esmREG->EPSTATUS & 0x1U) == 0x0U) - { - if(esmREG->KEY == 0x5U) - { - status = esmSelfTest_Active; - } - else - { - status = esmSelfTest_Failed; - } - } - else - { - status = esmSelfTest_Passed; - } - -/* USER CODE BEGIN (34) */ -/* USER CODE END */ - - return status; -} - -/** @fn void esmGetConfigValue(esm_config_reg_t *config_reg, config_value_type_t type) -* @brief Get the initial or current values of the configuration registers -* -* @param[in] *config_reg: pointer to the struct to which the initial or current -* value of the configuration registers need to be stored -* @param[in] type: whether initial or current value of the configuration registers need to be stored -* - InitialValue: initial value of the configuration registers will be stored -* in the struct pointed by config_reg -* - CurrentValue: initial value of the configuration registers will be stored -* in the struct pointed by config_reg -* -* This function will copy the initial or current value (depending on the parameter 'type') -* of the configuration registers to the struct pointed by config_reg -* -*/ - -void esmGetConfigValue(esm_config_reg_t *config_reg, config_value_type_t type) -{ - if (type == InitialValue) - { - config_reg->CONFIG_EPENASET1 = ESM_EPENASET1_CONFIGVALUE; - config_reg->CONFIG_INTENASET1 = ESM_INTENASET1_CONFIGVALUE; - config_reg->CONFIG_INTLVLSET1 = ESM_INTLVLSET1_CONFIGVALUE; - config_reg->CONFIG_LTCPRELOAD = ESM_LTCPRELOAD_CONFIGVALUE; - config_reg->CONFIG_KEY = ESM_KEY_CONFIGVALUE; - config_reg->CONFIG_EPENASET4 = ESM_EPENASET4_CONFIGVALUE; - config_reg->CONFIG_INTENASET4 = ESM_INTENASET4_CONFIGVALUE; - config_reg->CONFIG_INTLVLSET4 = ESM_INTLVLSET4_CONFIGVALUE; - } - else - { - config_reg->CONFIG_EPENASET1 = esmREG->EPENASET1; - config_reg->CONFIG_INTENASET1 = esmREG->INTENASET1; - config_reg->CONFIG_INTLVLSET1 = esmREG->INTLVLSET1; - config_reg->CONFIG_LTCPRELOAD = esmREG->LTCPRELOAD; - config_reg->CONFIG_KEY = esmREG->KEY; - config_reg->CONFIG_EPENASET4 = esmREG->EPENASET4; - config_reg->CONFIG_INTENASET4 = esmREG->INTENASET4; - config_reg->CONFIG_INTLVLSET4 = esmREG->INTLVLSET4; - } -} - -/* USER CODE BEGIN (35) */ -/* USER CODE END */ - -/** @fn void esmHighInterrupt(void) -* @brief High Level Interrupt for ESM -*/ -#pragma CODE_STATE(esmHighInterrupt, 32) -#pragma INTERRUPT(esmHighInterrupt, FIQ) - -void esmHighInterrupt(void) -{ - sint32 vec = esmREG->INTOFFH - 1U; - -/* USER CODE BEGIN (36) */ -/* USER CODE END */ - - if (vec >= 96U) - { - esmREG->ESTATUS4[1U] = 1U << (vec-96U); - esmGroup2Notification(vec-64U); - } - else if (vec >= 64U) - { - esmREG->ESTATUS4[0U] = 1U << (vec-64U); - esmGroup1Notification(vec-32U); - } - else if (vec >= 32U) - { - esmREG->ESTATUS1[1U] = 1U << (vec-32U); - esmGroup2Notification(vec-32U); - } - else if (vec >= 0U) - { - esmREG->ESTATUS1[0U] = 1U << vec; - esmGroup1Notification(vec); - } - else - { - esmREG->ESTATUS4[1U] = 0xFFFFFFFFU; - esmREG->ESTATUS4[0U] = 0xFFFFFFFFU; - esmREG->ESTATUS1[1U] = 0xFFFFFFFFU; - esmREG->ESTATUS1[0U] = 0xFFFFFFFFU; - } - -/* USER CODE BEGIN (37) */ -/* USER CODE END */ -} - - -/* USER CODE BEGIN (41) */ -/* USER CODE END */ diff --git a/bsp/rm48x50/HALCoGen/source/notification.c b/bsp/rm48x50/HALCoGen/source/notification.c deleted file mode 100644 index 4d1e06c89c..0000000000 --- a/bsp/rm48x50/HALCoGen/source/notification.c +++ /dev/null @@ -1,125 +0,0 @@ -/** @file notification.c -* @brief User Notification Definition File -* @date 29.May.2013 -* @version 03.05.02 -* -* This file defines empty notification routines to avoid -* linker errors, Driver expects user to define the notification. -* The user needs to either remove this file and use their custom -* notification function or place their code sequence in this file -* between the provided USER CODE BEGIN and USER CODE END. -* -*/ - -/* Include Files */ - -#include "esm.h" -#include "sys_selftest.h" -#include "gio.h" -#include "sci.h" -#include "rti.h" -#include "sys_dma.h" -/* USER CODE BEGIN (0) */ -#include <stdint.h> -/* USER CODE END */ - -void esmGroup1Notification(uint32 channel) -{ -/* enter user code between the USER CODE BEGIN and USER CODE END. */ -/* USER CODE BEGIN (1) */ -/* USER CODE END */ -} - -/* USER CODE BEGIN (2) */ -/* USER CODE END */ - -void esmGroup2Notification(uint32 channel) -{ -/* enter user code between the USER CODE BEGIN and USER CODE END. */ -/* USER CODE BEGIN (3) */ -/* USER CODE END */ -} - -/* USER CODE BEGIN (4) */ -/* USER CODE END */ - -void memoryPort0TestFailNotification(uint32 groupSelect, uint32 dataSelect, uint32 address, uint32 data) -{ -/* enter user code between the USER CODE BEGIN and USER CODE END. */ -/* USER CODE BEGIN (5) */ -/* USER CODE END */ -} - -/* USER CODE BEGIN (6) */ -/* USER CODE END */ - -void memoryPort1TestFailNotification(uint32 groupSelect, uint32 dataSelect, uint32 address, uint32 data) -{ -/* enter user code between the USER CODE BEGIN and USER CODE END. */ -/* USER CODE BEGIN (7) */ -/* USER CODE END */ -} - -/* USER CODE BEGIN (8) */ -/* USER CODE END */ -void rtiNotification(uint32 notification) -{ -/* enter user code between the USER CODE BEGIN and USER CODE END. */ -/* USER CODE BEGIN (9) */ -sciSendByte(scilinREG, 'I'); -/* USER CODE END */ -} - -/* USER CODE BEGIN (10) */ -/* USER CODE END */ -void gioNotification(gioPORT_t *port, sint32 bit) -{ -/* enter user code between the USER CODE BEGIN and USER CODE END. */ -/* USER CODE BEGIN (19) */ -/* USER CODE END */ -} - -/* USER CODE BEGIN (20) */ -/* USER CODE END */ - -void sciNotification(sciBASE_t *sci, uint32 flags) -{ -/* enter user code between the USER CODE BEGIN and USER CODE END. */ -/* USER CODE BEGIN (29) */ - if (sci == scilinREG && flags == SCI_RX_INT) - { - } -/* USER CODE END */ -} - -/* USER CODE BEGIN (30) */ -/* USER CODE END */ - - - -/* USER CODE BEGIN (43) */ -/* USER CODE END */ - - -/* USER CODE BEGIN (47) */ -/* USER CODE END */ - - -/* USER CODE BEGIN (50) */ -/* USER CODE END */ - - -/* USER CODE BEGIN (53) */ -/* USER CODE END */ - -void dmaGroupANotification(dmaInterrupt_t inttype, sint32 channel) -{ -/* enter user code between the USER CODE BEGIN and USER CODE END. */ -/* USER CODE BEGIN (54) */ -/* USER CODE END */ -} -/* USER CODE BEGIN (55) */ -/* USER CODE END */ - -/* USER CODE BEGIN (56) */ -/* USER CODE END */ diff --git a/bsp/rm48x50/HALCoGen/source/pinmux.c b/bsp/rm48x50/HALCoGen/source/pinmux.c deleted file mode 100644 index d6aa3d8769..0000000000 --- a/bsp/rm48x50/HALCoGen/source/pinmux.c +++ /dev/null @@ -1,121 +0,0 @@ -/** @file pinmux.c -* @brief PINMUX Driver Inmplmentation File -* @date 29.May.2013 -* @version 03.05.02 -* -*/ - -/* (c) Texas Instruments 2009-2013, All rights reserved. */ - -/* Include Files */ - -#include "pinmux.h" - -#define PINMUX_SET(REG, BALLID, MUX) \ - pinMuxReg->PINMMR##REG## = (pinMuxReg->PINMMR##REG## & PINMUX_BALL_##BALLID##_MASK) | (PINMUX_BALL_##BALLID##_##MUX) - -#define PINMUX_GATE_EMIF_CLK_ENABLE(state) \ - pinMuxReg->PINMMR29 = (pinMuxReg->PINMMR29 & PINMUX_GATE_EMIF_CLK_MASK) | (PINMUX_GATE_EMIF_CLK_##state) - -#define PINMUX_GIOB_DISABLE_HET2_ENABLE(state) \ - pinMuxReg->PINMMR29 = (pinMuxReg->PINMMR29 & PINMUX_GIOB_DISABLE_HET2_MASK) | (PINMUX_GIOB_DISABLE_HET2_##state) - -#define PINMUX_ALT_ADC_TRIGGER_SELECT(num) \ - pinMuxReg->PINMMR30 = (pinMuxReg->PINMMR30 & PINMUX_ALT_ADC_TRIGGER_MASK) | (PINMUX_ALT_ADC_TRIGGER_##num) - -#define PINMUX_ETHERNET_SELECT(interface) \ - pinMuxReg->PINMMR29 = (pinMuxReg->PINMMR29 & PINMUX_ETHERNET_MASK) | (PINMUX_ETHERNET_##interface) - -/* USER CODE BEGIN (0) */ -/* USER CODE END */ - -void muxInit(void){ - -/* USER CODE BEGIN (1) */ -/* USER CODE END */ - - /* Enable Pin Muxing */ - kickerReg->KICKER0 = 0x83E70B13U; - kickerReg->KICKER1 = 0x95A4F1E0U; - -/* USER CODE BEGIN (2) */ -/* USER CODE END */ - - pinMuxReg->PINMMR0 = PINMUX_BALL_W10_GIOB_3 | PINMUX_BALL_A5_GIOA_0 | PINMUX_BALL_C3_MIBSPI3NCS_3 | PINMUX_BALL_B2_MIBSPI3NCS_2; - - pinMuxReg->PINMMR1 = PINMUX_BALL_C2_GIOA_1 | PINMUX_BALL_E3_HET1_11 | PINMUX_BALL_E5_ETMDATA_20 | PINMUX_BALL_F5_ETMDATA_21; - - pinMuxReg->PINMMR2 = PINMUX_BALL_C1_GIOA_2 | PINMUX_BALL_G5_ETMDATA_22 | PINMUX_BALL_E1_GIOA_3 | PINMUX_BALL_B5_GIOA_5; - - pinMuxReg->PINMMR3 = PINMUX_BALL_K5_ETMDATA_23 | PINMUX_BALL_B3_HET1_22 | PINMUX_BALL_H3_GIOA_6 | PINMUX_BALL_L5_ETMDATA_24; - - pinMuxReg->PINMMR4 = PINMUX_BALL_M1_GIOA_7 | PINMUX_BALL_M5_ETMDATA_25 | PINMUX_BALL_V2_HET1_01 | PINMUX_BALL_U1_HET1_03; - - pinMuxReg->PINMMR5 = PINMUX_BALL_K18_HET1_0 | PINMUX_BALL_W5_HET1_02 | PINMUX_BALL_V6_HET1_05 | PINMUX_BALL_N5_ETMDATA_26; - - pinMuxReg->PINMMR6 = PINMUX_BALL_T1_HET1_07 | PINMUX_BALL_P5_ETMDATA_27 | PINMUX_BALL_V7_HET1_09 | PINMUX_BALL_R5_ETMDATA_28; - - pinMuxReg->PINMMR7 = PINMUX_BALL_R6_ETMDATA_29 | PINMUX_BALL_V5_MIBSPI3NCS_1 | PINMUX_BALL_W3_HET1_06 | PINMUX_BALL_R7_ETMDATA_30; - - pinMuxReg->PINMMR8 = PINMUX_BALL_N2_HET1_13 | PINMUX_BALL_G3_MIBSPI1NCS_2 | PINMUX_BALL_N1_HET1_15 | PINMUX_BALL_R8_ETMDATA_31; - - pinMuxReg->PINMMR9 = (~(pinMuxReg->PINMMR9 >> 18U) & 0x00000001U ) << 18U| PINMUX_BALL_R9_ETMTRACECLKIN | PINMUX_BALL_W9_MIBSPI3NENA | PINMUX_BALL_V10_MIBSPI3NCS_0 | PINMUX_BALL_J3_MIBSPI1NCS_3; - - pinMuxReg->PINMMR10 = PINMUX_BALL_N19_AD1EVT | PINMUX_BALL_N15_ETMDATA_19 | PINMUX_BALL_N17_EMIF_nCS_0 | PINMUX_BALL_M15_ETMDATA_18; - - pinMuxReg->PINMMR11 = PINMUX_BALL_K17_EMIF_nCS_3 | PINMUX_BALL_M17_EMIF_nCS_4 | PINMUX_BALL_L15_ETMDATA_17 | PINMUX_BALL_P1_HET1_24; - - pinMuxReg->PINMMR12 = PINMUX_BALL_A14_HET1_26 | PINMUX_BALL_K15_ETMDATA_16 | PINMUX_BALL_G19_MIBSPI1NENA | PINMUX_BALL_H18_MIBSPI5NENA; - - pinMuxReg->PINMMR13 = PINMUX_BALL_J18_MIBSPI5SOMI_0 | PINMUX_BALL_J19_MIBSPI5SIMO_0 | PINMUX_BALL_H19_MIBSPI5CLK | PINMUX_BALL_R2_MIBSPI1NCS_0; - - pinMuxReg->PINMMR14 = PINMUX_BALL_E18_HET1_08 | PINMUX_BALL_K19_HET1_28 | PINMUX_BALL_D17_EMIF_nWE | PINMUX_BALL_D16_EMIF_BA_1; - - pinMuxReg->PINMMR15 = PINMUX_BALL_C17_EMIF_ADDR_21 | PINMUX_BALL_C16_EMIF_ADDR_20 | PINMUX_BALL_C15_EMIF_ADDR_19 | PINMUX_BALL_D15_EMIF_ADDR_18; - - pinMuxReg->PINMMR16 = PINMUX_BALL_E13_ETMDATA_12 | PINMUX_BALL_C14_EMIF_ADDR_17 | PINMUX_BALL_D14_EMIF_ADDR_16 | PINMUX_BALL_E12_ETMDATA_13; - - pinMuxReg->PINMMR17 = PINMUX_BALL_D19_HET1_10 | PINMUX_BALL_E11_ETMDATA_14 | PINMUX_BALL_B4_HET1_12 | PINMUX_BALL_E9_ETMDATA_08; - - pinMuxReg->PINMMR18 = PINMUX_BALL_C13_EMIF_ADDR_15 | PINMUX_BALL_A11_HET1_14 | PINMUX_BALL_C12_EMIF_ADDR_14 | PINMUX_BALL_M2_GIOB_0; - - pinMuxReg->PINMMR19 = PINMUX_BALL_E8_ETMDATA_09 | PINMUX_BALL_B11_HET1_30 | PINMUX_BALL_E10_ETMDATA_15 | PINMUX_BALL_E7_ETMDATA_10; - - pinMuxReg->PINMMR20 = PINMUX_BALL_C11_EMIF_ADDR_13 | PINMUX_BALL_C10_EMIF_ADDR_12 | PINMUX_BALL_F3_MIBSPI1NCS_1 | PINMUX_BALL_C9_EMIF_ADDR_11; - - pinMuxReg->PINMMR21 = PINMUX_BALL_D5_EMIF_ADDR_1 | PINMUX_BALL_K2_GIOB_1 | PINMUX_BALL_C8_EMIF_ADDR_10 | PINMUX_BALL_C7_EMIF_ADDR_9; - - pinMuxReg->PINMMR22 = PINMUX_BALL_D4_EMIF_ADDR_0 | PINMUX_BALL_C5_EMIF_ADDR_7 | PINMUX_BALL_C4_EMIF_ADDR_6 | PINMUX_BALL_E6_ETMDATA_11; - - pinMuxReg->PINMMR23 = (~(pinMuxReg->PINMMR5 >> 1U) & 0x00000001U ) << 8U |(~(pinMuxReg->PINMMR5 >> 9U) & 0x00000001U ) << 16U|(~(pinMuxReg->PINMMR5 >> 17U) & 0x00000001U ) << 24U| PINMUX_BALL_C6_EMIF_ADDR_8; - - pinMuxReg->PINMMR24 = (~(pinMuxReg->PINMMR4 >> 17U) & 0x00000001U ) << 0U|(~(pinMuxReg->PINMMR4 >> 25U) & 0x00000001U ) << 8U|(~(pinMuxReg->PINMMR20 >> 17U) & 0x00000001U ) << 16U | (~(pinMuxReg->PINMMR8 >> 9U) & 0x00000001U ) << 24U; - - pinMuxReg->PINMMR25 = (~(pinMuxReg->PINMMR12 >> 17U) & 0x00000001U ) << 8U|(~(pinMuxReg->PINMMR7 >> 9U) & 0x00000001U ) << 16U|(~(pinMuxReg->PINMMR0 >> 26U) & 0x00000001U ) << 24U; - - pinMuxReg->PINMMR26 = (~(pinMuxReg->PINMMR0 >> 18U) & 0x00000001U ) << 0U|(~(pinMuxReg->PINMMR9 >> 10U) & 0x00000001U ) << 8U|PINMUX_BALL_W6_MIBSPI5NCS_2 | PINMUX_BALL_T12_MIBSPI5NCS_3; - - pinMuxReg->PINMMR27 = PINMUX_BALL_E19_MIBSPI5NCS_0 | PINMUX_BALL_B6_MIBSPI5NCS_1 | PINMUX_BALL_E16_MIBSPI5SIMO_1 | PINMUX_BALL_H17_MIBSPI5SIMO_2; - - pinMuxReg->PINMMR28 = PINMUX_BALL_G17_MIBSPI5SIMO_3 | PINMUX_BALL_E17_MIBSPI5SOMI_1 | PINMUX_BALL_H16_MIBSPI5SOMI_2 | PINMUX_BALL_G16_MIBSPI5SOMI_3; - - pinMuxReg->PINMMR29 = PINMUX_BALL_D3_SPI2NENA; - - PINMUX_GATE_EMIF_CLK_ENABLE(OFF); - PINMUX_GIOB_DISABLE_HET2_ENABLE(OFF); - PINMUX_ALT_ADC_TRIGGER_SELECT(1); - PINMUX_ETHERNET_SELECT(RMII); - -/* USER CODE BEGIN (3) */ -/* USER CODE END */ - - /* Disable Pin Muxing */ - kickerReg->KICKER0 = 0x00000000U; - kickerReg->KICKER1 = 0x00000000U; - -/* USER CODE BEGIN (4) */ -/* USER CODE END */ -} - -/* USER CODE BEGIN (5) */ -/* USER CODE END */ diff --git a/bsp/rm48x50/HALCoGen/source/rti.c b/bsp/rm48x50/HALCoGen/source/rti.c index 254a55499c..fdb0acb478 100644 --- a/bsp/rm48x50/HALCoGen/source/rti.c +++ b/bsp/rm48x50/HALCoGen/source/rti.c @@ -764,31 +764,3 @@ void rtiGetConfigValue(rti_config_reg_t *config_reg, config_value_type_t type) } } - - - -/* USER CODE BEGIN (82) */ -/* USER CODE END */ - -/** @fn void rtiCompare3Interrupt(void) -* @brief RTI1 Compare 3 Interrupt Handler -* -* RTI1 Compare 3 interrupt handler -* -*/ - -void rtiCompare3Interrupt(void) -{ -/* USER CODE BEGIN (83) */ -/* USER CODE END */ - - rtiREG1->INTFLAG = 8U; - rtiNotification(rtiNOTIFICATION_COMPARE3); - -/* USER CODE BEGIN (84) */ -/* USER CODE END */ -} - - - - diff --git a/bsp/rm48x50/HALCoGen/source/sci.c b/bsp/rm48x50/HALCoGen/source/sci.c deleted file mode 100644 index 67a1bbc1d7..0000000000 --- a/bsp/rm48x50/HALCoGen/source/sci.c +++ /dev/null @@ -1,549 +0,0 @@ -/** @file sci.c -* @brief SCI Driver Implementation File -* @date 29.May.2013 -* @version 03.05.02 -* -*/ - -/* (c) Texas Instruments 2009-2013, All rights reserved. */ - -/* USER CODE BEGIN (0) */ -/* USER CODE END */ - -#include "sci.h" - -/* USER CODE BEGIN (1) */ -/* USER CODE END */ -/** @struct g_sciTransfer -* @brief Interrupt mode globals -* -*/ -static struct g_sciTransfer -{ - uint32 mode; - uint32 length; - uint8 * data; -} g_sciTransfer_t[2U]; - - -/** @fn void sciInit(void) -* @brief Initializes the SCI Driver -* -* This function initializes the SCI module. -*/ -void sciInit(void) -{ -/* USER CODE BEGIN (2) */ -/* USER CODE END */ - - - /** @b initialize @b SCILIN */ - - /** - bring SCI out of reset */ - scilinREG->GCR0 = 1U; - - /** - Disable all interrupts */ - scilinREG->CLRINT = 0xFFFFFFFFU; - scilinREG->CLRINTLVL = 0xFFFFFFFFU; - - /** - global control 1 */ - scilinREG->GCR1 = (1U << 25U) /* enable transmit */ - | (1U << 24U) /* enable receive */ - | (1U << 5U) /* internal clock (device has no clock pin) */ - | ((1U-1U) << 4U) /* number of stop bits */ - | (0U << 3U) /* even parity, otherwise odd */ - | (0U << 2U) /* enable parity */ - | (1U << 1U); /* asynchronous timing mode */ - - /** - set baudrate */ - scilinREG->BRS = 53U; /* baudrate */ - - /** - transmission length */ - scilinREG->FORMAT = 8U - 1U; /* length */ - - /** - set SCI pins functional mode */ - scilinREG->FUN = (1U << 2U) /* tx pin */ - | (1U << 1U) /* rx pin */ - | (0U); /* clk pin */ - - /** - set SCI pins default output value */ - scilinREG->DOUT = (0U << 2U) /* tx pin */ - | (0U << 1U) /* rx pin */ - | (0U); /* clk pin */ - - /** - set SCI pins output direction */ - scilinREG->DIR = (0U << 2U) /* tx pin */ - | (0U << 1U) /* rx pin */ - | (0U); /* clk pin */ - - /** - set SCI pins open drain enable */ - scilinREG->ODR = (0U << 2U) /* tx pin */ - | (0U << 1U) /* rx pin */ - | (0U); /* clk pin */ - - /** - set SCI pins pullup/pulldown enable */ - scilinREG->PD = (0U << 2U) /* tx pin */ - | (0U << 1U) /* rx pin */ - | (0U); /* clk pin */ - - /** - set SCI pins pullup/pulldown select */ - scilinREG->PSL = (1U << 2U) /* tx pin */ - | (1U << 1U) /* rx pin */ - | (1U); /* clk pin */ - - /** - set interrupt level */ - scilinREG->SETINTLVL = (0U << 26U) /* Framing error */ - | (0U << 25U) /* Overrun error */ - | (0U << 24U) /* Parity error */ - | (0U << 9U) /* Receive */ - | (0U << 8U) /* Transmit */ - | (0U << 1U) /* Wakeup */ - | (0U); /* Break detect */ - - /** - set interrupt enable */ - scilinREG->SETINT = (0U << 26U) /* Framing error */ - | (0U << 25U) /* Overrun error */ - | (0U << 24U) /* Parity error */ - | (1U << 9U) /* Receive */ - | (0U << 1U) /* Wakeup */ - | (0U); /* Break detect */ - - /** - initialize global transfer variables */ - g_sciTransfer_t[1U].mode = 0U << 8U; - g_sciTransfer_t[1U].length = 0U; - - /** - Finaly start SCILIN */ - scilinREG->GCR1 |= (1U << 7U); - -/* USER CODE BEGIN (3) */ -/* USER CODE END */ -} - - -/** @fn void sciSetFunctional(sciBASE_t *sci, uint32 port) -* @brief Change functional behavior of pins at runtime. -* @param[in] sci - sci module base address -* @param[in] port - Value to write to FUN register -* -* Change the value of the PCFUN register at runtime, this allows to -* dynamically change the functionality of the SCI pins between functional -* and GIO mode. -*/ -void sciSetFunctional(sciBASE_t *sci, uint32 port) -{ -/* USER CODE BEGIN (4) */ -/* USER CODE END */ - - sci->FUN = port; - -/* USER CODE BEGIN (5) */ -/* USER CODE END */ -} - - -/** @fn void sciSetBaudrate(sciBASE_t *sci, uint32 baud) -* @brief Change baudrate at runtime. -* @param[in] sci - sci module base address -* @param[in] baud - baudrate in Hz -* -* Change the SCI baudrate at runtime. -*/ -void sciSetBaudrate(sciBASE_t *sci, uint32 baud) -{ - float64 vclk = 100.000 * 1000000.0; - uint32 f = ((sci->GCR1 & 2U) == 2U) ? 16U : 1U; - -/* USER CODE BEGIN (6) */ -/* USER CODE END */ - - /*SAFETYMCUSW 96 S MR:6.1 <REVIEWED> "Calculations including int and float cannot be avoided" */ - sci->BRS = ((uint32)((vclk /(f*baud) + 0.5)) - 1U) & 0x00FFFFFFU; - -/* USER CODE BEGIN (7) */ -/* USER CODE END */ -} - - -/** @fn uint32 sciIsTxReady(sciBASE_t *sci) -* @brief Check if Tx buffer empty -* @param[in] sci - sci module base address -* -* @return The TX ready flag -* -* Checks to see if the Tx buffer ready flag is set, returns -* 0 is flags not set otherwise will return the Tx flag itself. -*/ -uint32 sciIsTxReady(sciBASE_t *sci) -{ -/* USER CODE BEGIN (8) */ -/* USER CODE END */ - - return sci->FLR & SCI_TX_INT; -} - - -/** @fn void sciSendByte(sciBASE_t *sci, uint8 byte) -* @brief Send Byte -* @param[in] sci - sci module base address -* @param[in] byte - byte to transfer -* -* Sends a single byte in polling mode, will wait in the -* routine until the transmit buffer is empty before sending -* the byte. Use sciIsTxReady to check for Tx buffer empty -* before calling sciSendByte to avoid waiting. -*/ -void sciSendByte(sciBASE_t *sci, uint8 byte) -{ -/* USER CODE BEGIN (9) */ -/* USER CODE END */ - - while ((sci->FLR & SCI_TX_INT) == 0U) - { - } /* Wait */ - sci->TD = byte; - -/* USER CODE BEGIN (10) */ -/* USER CODE END */ -} - - -/** @fn void sciSend(sciBASE_t *sci, uint32 length, uint8 * data) -* @brief Send Data -* @param[in] sci - sci module base address -* @param[in] length - number of data words to transfer -* @param[in] data - pointer to data to send -* -* Send a block of data pointed to by 'data' and 'length' bytes -* long. If interrupts have been enabled the data is sent using -* interrupt mode, otherwise polling mode is used. In interrupt -* mode transmission of the first byte is started and the routine -* returns immediately, sciSend must not be called again until the -* transfer is complete, when the sciNotification callback will -* be called. In polling mode, sciSend will not return until -* the transfer is complete. -* -* @note if data word is less than 8 bits, then the data must be left -* aligned in the data byte. -*/ -void sciSend(sciBASE_t *sci, uint32 length, uint8 * data) -{ - uint32 index = sci == sciREG ? 0U : 1U; - -/* USER CODE BEGIN (11) */ -/* USER CODE END */ - - if ((g_sciTransfer_t[index].mode & SCI_TX_INT) != 0U) - { - /* we are in interrupt mode */ - - g_sciTransfer_t[index].length = length; - g_sciTransfer_t[index].data = data; - - /* start transmit by sending first byte */ - sci->TD = *g_sciTransfer_t[index].data++ ; - sci->SETINT = SCI_TX_INT; - } - else - { - /* send the data */ - while (length-- > 0U) - { - while ((sci->FLR & SCI_TX_INT) == 0U) - { - } /* Wait */ - sci->TD = *data++; - } - } - -/* USER CODE BEGIN (12) */ -/* USER CODE END */ -} - - -/** @fn uint32 sciIsRxReady(sciBASE_t *sci) -* @brief Check if Rx buffer full -* @param[in] sci - sci module base address -* -* @return The Rx ready flag -* -* Checks to see if the Rx buffer full flag is set, returns -* 0 is flags not set otherwise will return the Rx flag itself. -*/ -uint32 sciIsRxReady(sciBASE_t *sci) -{ -/* USER CODE BEGIN (13) */ -/* USER CODE END */ - - return sci->FLR & SCI_RX_INT; -} - -/** @fn uint32 sciIsIdleDetected(sciBASE_t *sci) -* @brief Check if Idle Period is Detected -* @param[in] sci - sci module base address -* -* @return The Idle flag -* -* Checks to see if the SCI Idle flag is set, returns 0 is flags -* not set otherwise will return the Ilde flag itself. -*/ -uint32 sciIsIdleDetected(sciBASE_t *sci) -{ -/* USER CODE BEGIN (14) */ -/* USER CODE END */ - - return sci->FLR & SCI_IDLE; -} - - -/** @fn uint32 sciRxError(sciBASE_t *sci) -* @brief Return Rx Error flags -* @param[in] sci - sci module base address -* -* @return The Rx error flags -* -* Returns the Rx framing, overrun and parity errors flags, -* also clears the error flags before returning. -*/ -uint32 sciRxError(sciBASE_t *sci) -{ - uint32 status = sci->FLR & (SCI_FE_INT | SCI_OE_INT |SCI_PE_INT); - -/* USER CODE BEGIN (15) */ -/* USER CODE END */ - - sci->FLR = SCI_FE_INT | SCI_OE_INT | SCI_PE_INT; - return status; -} - - -/** @fn uint32 sciReceiveByte(sciBASE_t *sci) -* @brief Receive Byte -* @param[in] sci - sci module base address -* -* @return Received byte -* -* Receives a single byte in polling mode. If there is -* not a byte in the receive buffer the routine will wait -* until one is received. Use sciIsRxReady to check to -* see if the buffer is full to avoid waiting. -*/ -uint32 sciReceiveByte(sciBASE_t *sci) -{ -/* USER CODE BEGIN (16) */ -/* USER CODE END */ - - while ((sci->FLR & SCI_RX_INT) == 0U) - { - } /* Wait */ - - return (sci->RD & 0x000000FFU); -} - - -/** @fn void sciReceive(sciBASE_t *sci, uint32 length, uint8 * data) -* @brief Receive Data -* @param[in] sci - sci module base address -* @param[in] length - number of data words to transfer -* @param[in] data - pointer to data buffer -* -* Receive a block of 'length' bytes long and place it into the -* data buffer pointed to by 'data'. If interrupts have been -* enabled the data is received using interrupt mode, otherwise -* polling mode is used. In interrupt mode receive is setup and -* the routine returns immediately, sciReceive must not be called -* again until the transfer is complete, when the sciNotification -* callback will be called. In polling mode, sciReceive will not -* return until the transfer is complete. -*/ -void sciReceive(sciBASE_t *sci, uint32 length, uint8 * data) -{ -/* USER CODE BEGIN (17) */ -/* USER CODE END */ - - if ((sci->SETINT & SCI_RX_INT) == SCI_RX_INT) - { - /* we are in interrupt mode */ - uint32 index = sci == sciREG ? 0U : 1U; - - /* clear error flags */ - sci->FLR = SCI_FE_INT | SCI_OE_INT | SCI_PE_INT; - - g_sciTransfer_t[index].length = length; - g_sciTransfer_t[index].data = data; - } - else - { - while (length-- > 0U) - { - while ((sci->FLR & SCI_RX_INT) == 0U) - { - } /* Wait */ - *data++ = (uint8)(sci->RD & 0x000000FFU); - } - } -/* USER CODE BEGIN (18) */ -/* USER CODE END */ -} - -/** @fn void sciEnableLoopback(sciBASE_t *sci, loopBackType_t Loopbacktype) -* @brief Enable Loopback mode for self test -* @param[in] sci - sci module base address -* @param[in] Loopbacktype - Digital or Analog -* -* This function enables the Loopback mode for self test. -*/ -void sciEnableLoopback(sciBASE_t *sci, loopBackType_t Loopbacktype) -{ -/* USER CODE BEGIN (19) */ -/* USER CODE END */ - - /* Clear Loopback incase enabled already */ - sci->IODFTCTRL = 0U; - - /* Enable Loopback either in Analog or Digital Mode */ - sci->IODFTCTRL = 0x00000A00U - | (Loopbacktype << 1U); - -/* USER CODE BEGIN (20) */ -/* USER CODE END */ -} - -/** @fn void sciDisableLoopback(sciBASE_t *sci) -* @brief Enable Loopback mode for self test -* @param[in] sci - sci module base address -* -* This function disable the Loopback mode. -*/ -void sciDisableLoopback(sciBASE_t *sci) -{ -/* USER CODE BEGIN (21) */ -/* USER CODE END */ - - /* Disable Loopback Mode */ - sci->IODFTCTRL = 0x00000500U; - -/* USER CODE BEGIN (22) */ -/* USER CODE END */ -} - -/** @fn sciEnableNotification(sciBASE_t *sci, uint32 flags) -* @brief Enable interrupts -* @param[in] sci - sci module base address -* @param[in] flags - Interrupts to be enabled, can be ored value of: -* SCI_FE_INT - framing error, -* SCI_OE_INT - overrun error, -* SCI_PE_INT - parity error, -* SCI_RX_INT - receive buffer ready, -* SCI_TX_INT - transmit buffer ready, -* SCI_WAKE_INT - wakeup, -* SCI_BREAK_INT - break detect -*/ -void sciEnableNotification(sciBASE_t *sci, uint32 flags) -{ - uint32 index = sci == sciREG ? 0U : 1U; - -/* USER CODE BEGIN (23) */ -/* USER CODE END */ - - g_sciTransfer_t[index].mode |= (flags & SCI_TX_INT); - sci->SETINT = (flags & (~(SCI_TX_INT))); - -/* USER CODE BEGIN (24) */ -/* USER CODE END */ -} - - -/** @fn sciDisableNotification(sciBASE_t *sci, uint32 flags) -* @brief Disable interrupts -* @param[in] sci - sci module base address -* @param[in] flags - Interrupts to be disabled, can be ored value of: -* SCI_FE_INT - framing error, -* SCI_OE_INT - overrun error, -* SCI_PE_INT - parity error, -* SCI_RX_INT - receive buffer ready, -* SCI_TX_INT - transmit buffer ready, -* SCI_WAKE_INT - wakeup, -* SCI_BREAK_INT - break detect -*/ -void sciDisableNotification(sciBASE_t *sci, uint32 flags) -{ - uint32 index = sci == sciREG ? 0U : 1U; - -/* USER CODE BEGIN (25) */ -/* USER CODE END */ - - g_sciTransfer_t[index].mode &= ~(flags & SCI_TX_INT); - sci->CLRINT = (flags & (~SCI_TX_INT)); - -/* USER CODE BEGIN (26) */ -/* USER CODE END */ -} - -/** @fn void linHighLevelInterrupt(void) -* @brief Level 0 Interrupt for SCILIN -*/ -void linHighLevelInterrupt(void) -{ - uint32 vec = scilinREG->INTVECT0; - -/* USER CODE BEGIN (35) */ -/* USER CODE END */ - - switch (vec) - { - case 1U: - sciNotification(scilinREG, SCI_WAKE_INT); - break; - case 3U: - sciNotification(scilinREG, SCI_PE_INT); - break; - case 6U: - sciNotification(scilinREG, SCI_FE_INT); - break; - case 7U: - sciNotification(scilinREG, SCI_BREAK_INT); - break; - case 9U: - sciNotification(scilinREG, SCI_OE_INT); - break; - - case 11U: - /* receive */ - { uint32 byte = (scilinREG->RD & 0x000000FFU); - - if (g_sciTransfer_t[1U].length > 0U) - { - *g_sciTransfer_t[1U].data++ = byte; - g_sciTransfer_t[1U].length--; - if (g_sciTransfer_t[1U].length == 0U) - { - sciNotification(scilinREG, SCI_RX_INT); - } - } - } - break; - - case 12U: - /* transmit */ - if (--g_sciTransfer_t[1U].length > 0U) - { - scilinREG->TD = *g_sciTransfer_t[1U].data++; - } - else - { - scilinREG->CLRINT = SCI_TX_INT; - sciNotification(scilinREG, SCI_TX_INT); - } - break; - - default: - /* phantom interrupt, clear flags and return */ - scilinREG->FLR = ~scilinREG->SETINTLVL & 0x07000303U; - break; - } -/* USER CODE BEGIN (36) */ -/* USER CODE END */ -} -/* USER CODE BEGIN (37) */ -/* USER CODE END */ - diff --git a/bsp/rm48x50/HALCoGen/source/sys_core.asm b/bsp/rm48x50/HALCoGen/source/sys_core.asm index ae2a9ebd93..186d4f28ab 100644 --- a/bsp/rm48x50/HALCoGen/source/sys_core.asm +++ b/bsp/rm48x50/HALCoGen/source/sys_core.asm @@ -7,17 +7,14 @@ .text .arm -;------------------------------------------------------------------------------- -; Initialize CPU Registers + .ref _c_int00 - .def _coreInitRegisters_ + .def _reset .asmfunc - - -_coreInitRegisters_ - - - ; After reset, the CPU is in the Supervisor mode (M = 10011) +_reset +;------------------------------------------------------------------------------- +; Initialize CPU Registers +; After reset, the CPU is in the Supervisor mode (M = 10011) mov r0, lr mov r1, #0x0000 mov r2, #0x0000 @@ -33,7 +30,7 @@ _coreInitRegisters_ mov r12, #0x0000 mov r13, #0x0000 mrs r1, cpsr - msr spsr_cxsf, r1 + msr spsr_cxsf, r1 ; Switch to FIQ mode (M = 10001) cps #17 mov lr, r0 @@ -43,27 +40,27 @@ _coreInitRegisters_ mov r11, #0x0000 mov r12, #0x0000 mrs r1, cpsr - msr spsr_cxsf, r1 + msr spsr_cxsf, r1 ; Switch to IRQ mode (M = 10010) cps #18 mov lr, r0 mrs r1,cpsr - msr spsr_cxsf, r1 + msr spsr_cxsf, r1 ; Switch to Abort mode (M = 10111) cps #23 mov lr, r0 mrs r1,cpsr - msr spsr_cxsf, r1 + msr spsr_cxsf, r1 ; Switch to Undefined Instruction Mode (M = 11011) cps #27 mov lr, r0 mrs r1,cpsr - msr spsr_cxsf, r1 + msr spsr_cxsf, r1 ; Switch to System Mode ( Shares User Mode registers ) (M = 11111) cps #31 mov lr, r0 mrs r1,cpsr - msr spsr_cxsf, r1 + msr spsr_cxsf, r1 ; Switch back to Supervisor Mode (M = 10011) cps #19 @@ -94,27 +91,9 @@ _coreInitRegisters_ fmdrr d14, r1, r1 fmdrr d15, r1, r1 .endif - bl next1 -next1 - bl next2 -next2 - bl next3 -next3 - bl next4 -next4 - bx r0 - - .endasmfunc - ;------------------------------------------------------------------------------- ; Initialize Stack Pointers - - .def _coreInitStackPointer_ - .asmfunc - -_coreInitStackPointer_ - cps #17 ldr sp, fiqSp cps #18 @@ -127,8 +106,19 @@ _coreInitStackPointer_ ldr sp, userSp cps #19 ldr sp, svcSp - bx lr + bl next1 +next1 + bl next2 +next2 + bl next3 +next3 + bl next4 +next4 + ldr lr, int00ad + bx lr + +int00ad .word _c_int00 userSp .word 0x08000000+0x00001000 svcSp .word 0x08000000+0x00001000+0x00000100 fiqSp .word 0x08000000+0x00001000+0x00000100+0x00000100 @@ -139,90 +129,6 @@ undefSp .word 0x08000000+0x00001000+0x00000100+0x00000100+0x00000100+0x00000100+ .endasmfunc ;------------------------------------------------------------------------------- -; Get CPSR Value - - .def _getCPSRValue_ - .asmfunc - -_getCPSRValue_ - - mrs r0, CPSR - bx lr - - .endasmfunc - -;------------------------------------------------------------------------------- -; Take CPU to IDLE state - - .def _gotoCPUIdle_ - .asmfunc - -_gotoCPUIdle_ - - WFI - nop - nop - nop - nop - bx lr - - .endasmfunc - - -;------------------------------------------------------------------------------- -; Enable VFP Unit - - .def _coreEnableVfp_ - .asmfunc - -_coreEnableVfp_ - - mrc p15, #0x00, r0, c1, c0, #0x02 - orr r0, r0, #0xF00000 - mcr p15, #0x00, r0, c1, c0, #0x02 - mov r0, #0x40000000 - fmxr fpexc, r0 - bx lr - - .endasmfunc - -;------------------------------------------------------------------------------- -; Enable Event Bus Export - - .def _coreEnableEventBusExport_ - .asmfunc - -_coreEnableEventBusExport_ - - stmfd sp!, {r0} - mrc p15, #0x00, r0, c9, c12, #0x00 - orr r0, r0, #0x10 - mcr p15, #0x00, r0, c9, c12, #0x00 - ldmfd sp!, {r0} - bx lr - - .endasmfunc - - -;------------------------------------------------------------------------------- -; Disable Event Bus Export - - .def _coreDisableEventBusExport_ - .asmfunc - -_coreDisableEventBusExport_ - - stmfd sp!, {r0} - mrc p15, #0x00, r0, c9, c12, #0x00 - bic r0, r0, #0x10 - mcr p15, #0x00, r0, c9, c12, #0x00 - ldmfd sp!, {r0} - bx lr - - .endasmfunc - - -;------------------------------------------------------------------------------- ; Enable RAM ECC Support .def _coreEnableRamEcc_ @@ -234,7 +140,7 @@ _coreEnableRamEcc_ mrc p15, #0x00, r0, c1, c0, #0x01 orr r0, r0, #0x0C000000 mcr p15, #0x00, r0, c1, c0, #0x01 - ldmfd sp!, {r0} + ldmfd sp!, {r0} bx lr .endasmfunc @@ -252,7 +158,7 @@ _coreDisableRamEcc_ mrc p15, #0x00, r0, c1, c0, #0x01 bic r0, r0, #0x0C000000 mcr p15, #0x00, r0, c1, c0, #0x01 - ldmfd sp!, {r0} + ldmfd sp!, {r0} bx lr .endasmfunc @@ -271,7 +177,7 @@ _coreEnableFlashEcc_ orr r0, r0, #0x02000000 dmb mcr p15, #0x00, r0, c1, c0, #0x01 - ldmfd sp!, {r0} + ldmfd sp!, {r0} bx lr .endasmfunc @@ -289,30 +195,11 @@ _coreDisableFlashEcc_ mrc p15, #0x00, r0, c1, c0, #0x01 bic r0, r0, #0x02000000 mcr p15, #0x00, r0, c1, c0, #0x01 - ldmfd sp!, {r0} - bx lr - - .endasmfunc - - -;------------------------------------------------------------------------------- -; Enable Offset via Vic controller - - .def _coreEnableIrqVicOffset_ - .asmfunc - -_coreEnableIrqVicOffset_ - - stmfd sp!, {r0} - mrc p15, #0, r0, c1, c0, #0 - orr r0, r0, #0x01000000 - mcr p15, #0, r0, c1, c0, #0 - ldmfd sp!, {r0} + ldmfd sp!, {r0} bx lr .endasmfunc - ;------------------------------------------------------------------------------- ; Get data fault status register @@ -338,7 +225,7 @@ _coreClearDataFault_ stmfd sp!, {r0} mov r0, #0 mcr p15, #0, r0, c5, c0, #0 - ldmfd sp!, {r0} + ldmfd sp!, {r0} bx lr .endasmfunc @@ -369,7 +256,7 @@ _coreClearInstructionFault_ stmfd sp!, {r0} mov r0, #0 mcr p15, #0, r0, c5, c0, #1 - ldmfd sp!, {r0} + ldmfd sp!, {r0} bx lr .endasmfunc @@ -400,7 +287,7 @@ _coreClearDataFaultAddress_ stmfd sp!, {r0} mov r0, #0 mcr p15, #0, r0, c6, c0, #0 - ldmfd sp!, {r0} + ldmfd sp!, {r0} bx lr .endasmfunc @@ -431,7 +318,7 @@ _coreClearInstructionFaultAddress_ stmfd sp!, {r0} mov r0, #0 mcr p15, #0, r0, c6, c0, #2 - ldmfd sp!, {r0} + ldmfd sp!, {r0} bx lr .endasmfunc @@ -462,7 +349,7 @@ _coreClearAuxiliaryDataFault_ stmfd sp!, {r0} mov r0, #0 mcr p15, #0, r0, c5, c1, #0 - ldmfd sp!, {r0} + ldmfd sp!, {r0} bx lr .endasmfunc @@ -492,65 +379,12 @@ _coreClearAuxiliaryInstructionFault_ stmfd sp!, {r0} mov r0, #0 mrc p15, #0, r0, c5, c1, #1 - ldmfd sp!, {r0} + ldmfd sp!, {r0} bx lr .endasmfunc ;------------------------------------------------------------------------------- -; Disable interrupts - R4 IRQ & FIQ - - .def _disable_interrupt_ - .asmfunc - -_disable_interrupt_ - - cpsid if - bx lr - - .endasmfunc - -;------------------------------------------------------------------------------- -; Disable FIQ interrupt - - .def _disable_FIQ_interrupt_ - .asmfunc - -_disable_FIQ_interrupt_ - - cpsid f - bx lr - - .endasmfunc - -;------------------------------------------------------------------------------- -; Disable FIQ interrupt - - .def _disable_IRQ_interrupt_ - .asmfunc - -_disable_IRQ_interrupt_ - - cpsid i - bx lr - - .endasmfunc - -;------------------------------------------------------------------------------- -; Enable interrupts - R4 IRQ & FIQ - - .def _enable_interrupt_ - .asmfunc - -_enable_interrupt_ - - cpsie if - bx lr - - .endasmfunc - - -;------------------------------------------------------------------------------- ; Clear ESM CCM errorss .def _esmCcmErrorsClear_ @@ -558,7 +392,7 @@ _enable_interrupt_ _esmCcmErrorsClear_ - stmfd sp!, {r0-r2} + stmfd sp!, {r0-r2} ldr r0, ESMSR1_REG ; load the ESMSR1 status register address ldr r2, ESMSR1_ERR_CLR str r2, [r0] ; clear the ESMSR1 register @@ -581,7 +415,7 @@ _esmCcmErrorsClear_ ldr r0, CCMR4_STAT_REG ; load the CCMR4 status register address ldr r2, CCMR4_ERR_CLR str r2, [r0] ; clear the CCMR4 status register - ldmfd sp!, {r0-r2} + ldmfd sp!, {r0-r2} bx lr ESMSR1_REG .word 0xFFFFF518 @@ -598,16 +432,16 @@ ESMSSR2_ERR_CLR .word 0x00000004 VIM_INT_CLR .word 0x00000001 VIM_INTREQ .word 0xFFFFFE20 - .endasmfunc + .endasmfunc ;------------------------------------------------------------------------------- ; Work Around for Errata CORTEX-R4#57: -; -; Errata Description: +; +; Errata Description: ; Conditional VMRS APSR_Nzcv, FPSCR May Evaluate With Incorrect Flags ; Workaround: -; Disable out-of-order single-precision floating point -; multiply-accumulate instruction completion +; Disable out-of-order single-precision floating point +; multiply-accumulate instruction completion .def _errata_CORTEXR4_57_ .asmfunc @@ -615,22 +449,22 @@ VIM_INTREQ .word 0xFFFFFE20 _errata_CORTEXR4_57_ push {r0} - mrc p15, #0, r0, c15, c0, #0 ; Read Secondary Auxiliary Control Register - orr r0, r0, #0x10000 ; Set BIT 16 (Set DOOFMACS) - mcr p15, #0, r0, c15, c0, #0 ; Write Secondary Auxiliary Control Register + mrc p15, #0, r0, c15, c0, #0 ; Read Secondary Auxiliary Control Register + orr r0, r0, #0x10000 ; Set BIT 16 (Set DOOFMACS) + mcr p15, #0, r0, c15, c0, #0 ; Write Secondary Auxiliary Control Register pop {r0} bx lr .endasmfunc ;------------------------------------------------------------------------------- ; Work Around for Errata CORTEX-R4#66: -; -; Errata Description: -; Register Corruption During A Load-Multiple Instruction At +; +; Errata Description: +; Register Corruption During A Load-Multiple Instruction At ; an Exception Vector ; Workaround: -; Disable out-of-order completion for divide instructions in -; Auxiliary Control register +; Disable out-of-order completion for divide instructions in +; Auxiliary Control register .def _errata_CORTEXR4_66_ .asmfunc @@ -639,12 +473,33 @@ _errata_CORTEXR4_66_ push {r0} mrc p15, #0, r0, c1, c0, #1 ; Read Auxiliary Control register - orr r0, r0, #0x80 ; Set BIT 7 (Disable out-of-order completion + orr r0, r0, #0x80 ; Set BIT 7 (Disable out-of-order completion ; for divide instructions.) mcr p15, #0, r0, c1, c0, #1 ; Write Auxiliary Control register - pop {r0} + pop {r0} bx lr .endasmfunc + + .def turnon_VFP + .asmfunc +turnon_VFP + ; Enable FPV + STMDB sp!, {r0} + fmrx r0, fpexc + orr r0, r0, #0x40000000 + fmxr fpexc, r0 + LDMIA sp!, {r0} + subs pc, lr, #4 + .endasmfunc + + .def _dabort + .asmfunc + +_dabort + stmfd r13!, {r0 - r12, lr} + ldmfd r13!, {r0 - r12, lr} + subs pc, lr, #8 + .endasmfunc ;------------------------------------------------------------------------------- ; C++ construct table pointers @@ -655,6 +510,6 @@ __TI_PINIT_Base .long SHT$$INIT_ARRAY$$Base __TI_PINIT_Limit .long SHT$$INIT_ARRAY$$Limit - + ;------------------------------------------------------------------------------- diff --git a/bsp/rm48x50/HALCoGen/source/sys_dma.c b/bsp/rm48x50/HALCoGen/source/sys_dma.c deleted file mode 100644 index 0756d25050..0000000000 --- a/bsp/rm48x50/HALCoGen/source/sys_dma.c +++ /dev/null @@ -1,322 +0,0 @@ -/** @file dma.c -* @brief DMA Driver Inmplmentation File -* @date 29.May.2013 -* @version 03.05.02 -* -*/ - -/* (c) Texas Instruments 2009-2013, All rights reserved. */ - - -#include "sys_dma.h" - - -/** @fn void dmaEnable(void) -* @brief enables DMA module -* -* This function brings DMA out of reset -*/ -void dmaEnable(void) -{ - dmaREG->GCTRL = 0x00000001U; /* reset dma */ - dmaREG->GCTRL |= 0x00010000U; /* enable dma */ - dmaREG->GCTRL |= 0x00000300U; /* stop at suspend */ -} - -/** @fn void dmaDisable(void) -* @brief disables DMA module -* -* This function disables DMA module -*/ -void dmaDisable(void) -{ - /* Wait until DMA's external bus has completed data transfer */ - while((dmaREG->GCTRL & DMA_GCTRL_BUSBUSY) != 0U) - { - } /* Wait */ - /* Disable DMA module */ - dmaREG->GCTRL = 0U; -} - - -/** @fn void dmaReqAssign(uint32 channel,uint32 reqline) -* @brief Initializes the DMA Driver -* @param[in] channel DMA channel -* @param[in] reqline DMA request line -* -* This function assigns dma request lines to channels -*/ -void dmaReqAssign(uint32 channel,uint32 reqline) -{ - register uint32 i=0U,j=0U; - - i = channel >> 2U; /* Find the register to configure */ - j = channel -(i<<2U); /* Find the offset of the type */ - j = 3U-j; /* reverse the byte order */ - j = j<<3U; /* find the bit location */ - - /* mapping channel 'i' to request line 'j' */ - dmaREG->DREQASI[i] &= ~(0xffU<<j); - dmaREG->DREQASI[i] |= (reqline<<j); -} - - -/** @fn uint32 dmaGetReq(uint32 channel) -* @brief Gets the request line number mapped to the selected channel -* @param[in] channel DMA channel -* -* This function returns the request line number mapped to the selected channel -*/ -uint32 dmaGetReq(uint32 channel) -{ - register uint32 i=0U,j=0U; - - i = channel >> 2U; /* Find the register to configure */ - j = channel -(i<<2U); /* Find the offset of the type */ - j = 3U-j; /* reverse the byte order */ - j = j<<3U; /* find the bit location */ - return ((dmaREG->DREQASI[i] >> j) &0xffU); -} - - -/** @fn void dmaSetCtrlPacket(uint32 channel) -* @brief Initializes the DMA Driver -* -* This function sets control packet -*/ -void dmaSetCtrlPacket(uint32 channel, g_dmaCTRL g_dmaCTRLPKT) -{ - register uint32 i=0U,j=0U; - - dmaRAMREG->PCP[channel].ISADDR = g_dmaCTRLPKT.SADD; - - dmaRAMREG->PCP[channel].IDADDR = g_dmaCTRLPKT.DADD; - - dmaRAMREG->PCP[channel].ITCOUNT = (g_dmaCTRLPKT.FRCNT << 16U) | g_dmaCTRLPKT.ELCNT; - - dmaRAMREG->PCP[channel].CHCTRL = (g_dmaCTRLPKT.RDSIZE << 14U) | (g_dmaCTRLPKT.WRSIZE << 12U) | (g_dmaCTRLPKT.TTYPE << 8U)| \ - (g_dmaCTRLPKT.ADDMODERD << 3U ) | (g_dmaCTRLPKT.ADDMODEWR << 1U ) | (g_dmaCTRLPKT.AUTOINIT); - - dmaRAMREG->PCP[channel].CHCTRL |= (g_dmaCTRLPKT.CHCTRL << 16U); - - dmaRAMREG->PCP[channel].EIOFF = (g_dmaCTRLPKT.ELDOFFSET << 16U) | (g_dmaCTRLPKT.ELSOFFSET); - - dmaRAMREG->PCP[channel].FIOFF = (g_dmaCTRLPKT.FRDOFFSET << 16U) | (g_dmaCTRLPKT.FRSOFFSET); - - i = channel >> 3U; /* Find the register to write */ - j = channel -(i << 3U); /* Find the offset of the 4th bit */ - j = 7U -j; /* Reverse the order of the 4th bit offset */ - j = j<<2U; /* Find the bit location of the 4th bit to write */ - - dmaREG->PAR[i] &= ~(0xfU<<j); - dmaREG->PAR[i] |= (g_dmaCTRLPKT.PORTASGN<<j); -} - - - -/** @fn void dmaSetChEnable(uint32 channel,uint32 type) -* @brief Enable channel -* @param[in] channel DMA channel -* @param[in] type Type of triggering -* - DMA_HW: Enables the selected DMA channel for hardware triggering -* - DMA_SW: Enables the selected DMA channel for software triggering -* -* This function enables the DMA channel for hardware or software triggering -*/ -void dmaSetChEnable(uint32 channel,uint32 type) -{ - if(type == DMA_HW) - { - dmaREG->HWCHENAS = (1U << channel); - } - else if(type == DMA_SW) - { - dmaREG->SWCHENAS = (1U << channel); - } - else - { - /** Empty */ - } -} - - - -/** @fn void dmaSetPriority(uint32 channel, dmaPRIORITY_t priority) -* @brief Assign Priority to the channel -* @param[in] channel DMA channel -* @param[in] priority Priority queue to which channel needs to be assigned -* - LOWPRIORITY : The selected channel will be assigned to low priority queue -* - HIGHPRIORITY: The selected channel will be assigned to high priority queue -* -* This function assigns the selected priority to the selected channel -*/ -void dmaSetPriority(uint32 channel, dmaPRIORITY_t priority) -{ - if (priority == LOWPRIORITY) - { - dmaREG->CHPRIOR |= 1U << channel; - } - else - { - dmaREG->CHPRIOS |= 1U << channel; - } -} - - -/** @fn void dmaEnableInterrupt(uint32 channel, dmaInterrupt_t inttype) -* @brief Enable selected interrupt -* @param[in] channel DMA channel -* @param[in] inttype Interrupt to be enabled -* - FTC: Frame Transfer Complete Interrupt will be disabled for the selected channel -* - LFS: Last Frame Transfer Started Interrupt will be disabled for the selected channel -* - HBC: First Half Of Block Complete Interrupt will be disabled for the selected channel -* - BTC: Block transfer complete Interrupt will be disabled for the selected channel -* - BER: Bus Error Interrupt will be disabled for the selected channel -* -* This function enables the selected interrupt for the selected channel -*/ -void dmaEnableInterrupt(uint32 channel, dmaInterrupt_t inttype) -{ - dmaREG->GCHIENAS = 1 << channel; - - switch (inttype) - { - case FTC: dmaREG->FTCINTENAS |= 1U << channel; - break; - case LFS: dmaREG->LFSINTENAS |= 1U << channel; - break; - case HBC: dmaREG->HBCINTENAS |= 1U << channel; - break; - case BTC: dmaREG->BTCINTENAS |= 1U << channel; - break; - default : - break; - } -} - - - -/** @fn void dmaDisableInterrupt(uint32 channel, dmaInterrupt_t inttype) -* @brief Disable selected interrupt -* @param[in] channel DMA channel -* @param[in] inttype Interrupt to be disabled -* - FTC: Frame Transfer Complete Interrupt will be disabled for the selected channel -* - LFS: Last Frame Transfer Started Interrupt will be disabled for the selected channel -* - HBC: First Half Of Block Complete Interrupt will be disabled for the selected channel -* - BTC: Block transfer complete Interrupt will be disabled for the selected channel -* - BER: Bus Error Interrupt will be disabled for the selected channel -* -* This function disables the selected interrupt for the selected channel -*/ -void dmaDisableInterrupt(uint32 channel, dmaInterrupt_t inttype) -{ - switch (inttype) - { - case FTC: dmaREG->FTCINTENAR |= 1U << channel; - break; - case LFS: dmaREG->LFSINTENAR |= 1U << channel; - break; - case HBC: dmaREG->HBCINTENAR |= 1U << channel; - break; - case BTC: dmaREG->BTCINTENAR |= 1U << channel; - break; - default : - break; - } -} - - - -/** @fn void dmaDefineRegion(dmaREGION_t region, uint32 start_add, uint32 end_add) -* @brief Configure start and end address of the region -* @param[in] region Memory Region -* - DMA_REGION0 -* - DMA_REGION1 -* - DMA_REGION2 -* - DMA_REGION3 -* @param[in] start_add Start address of the the region -* @param[in] end_add End address of the region -* -* This function configure start and end address of the selected region -*/ -void dmaDefineRegion(dmaREGION_t region, uint32 start_add, uint32 end_add) -{ - dmaREG->DMAMPR[region].STARTADD = start_add; - dmaREG->DMAMPR[region].ENDADD = end_add; -} - - - -/** @fn void dmaEnableRegion(dmaREGION_t region, dmaRegionAccess_t access, boolean intenable) -* @brief Enable the selected region -* @param[in] region Memory Region -* - DMA_REGION0 -* - DMA_REGION1 -* - DMA_REGION2 -* - DMA_REGION3 -* @param[in] access Access permission of the selected region -* - FULLACCESS -* - READONLY -* - WRITEONLY -* - NOACCESS -* @param[in] intenable Interrupt to be enabled or not -* - INTERRUPT_ENABLE : Enable interrupt for the selected region -* - INTERRUPT_DISABLE: Disable interrupt for the selected region -* -* This function enables the selected region with selected access permission with or without interrupt enable -*/ -void dmaEnableRegion(dmaREGION_t region, dmaRegionAccess_t access, boolean intenable) -{ - /* Enable the region */ - dmaREG->DMAMPCTRL |= 1U << (region*8U); - /* Set access permission for the region */ - dmaREG->DMAMPCTRL |= access << ((region*8U) + 1U); - /* Enable or Disable interrupt */ - dmaREG->DMAMPCTRL |= intenable << ((region*8U) + 3U); -} - - - -/** @fn void dmaDisableRegion(dmaREGION_t region) -* @brief Disable the selected region -* @param[in] region Memory Region -* - DMA_REGION0 -* - DMA_REGION1 -* - DMA_REGION2 -* - DMA_REGION3 -* -* This function disables the selected region(no address checking done). -*/ -void dmaDisableRegion(dmaREGION_t region) -{ - dmaREG->DMAMPCTRL &= ~(1U << (region*8U)); -} - - - -/** @fn void dmaEnableParityCheck(void) -* @brief Enable Parity Check -* -* This function enables parit check -*/ -void dmaEnableParityCheck(void) -{ - dmaREG->DMAPCR = 0x5U; -} - - - -/** @fn void dmaDisableParityCheck(void) -* @brief Disable Parity Check -* -* This function disables parity check -*/ -void dmaDisableParityCheck(void) -{ - dmaREG->DMAPCR = 0xAU; -} - - - - - diff --git a/bsp/rm48x50/HALCoGen/source/sys_intvecs.asm b/bsp/rm48x50/HALCoGen/source/sys_intvecs.asm index e97ba448ac..0ac6647266 100644 --- a/bsp/rm48x50/HALCoGen/source/sys_intvecs.asm +++ b/bsp/rm48x50/HALCoGen/source/sys_intvecs.asm @@ -10,17 +10,18 @@ ;------------------------------------------------------------------------------- ; import reference for interrupt routines - .ref _c_int00 + .ref _reset .ref _dabort + .ref turnon_VFP .ref IRQ_Handler - + .def resetEntry ;------------------------------------------------------------------------------- ; interrupt vectors resetEntry - b _c_int00 + b _reset b turnon_VFP svcEntry b svcEntry @@ -32,13 +33,4 @@ reservedEntry b IRQ_Handler ldr pc,[pc,#-0x1b0] - .sect ".text" -turnon_VFP - ; Enable FPV - STMDB sp!, {r0} - fmrx r0, fpexc - orr r0, r0, #0x40000000 - fmxr fpexc, r0 - LDMIA sp!, {r0} - subs pc, lr, #4 ;------------------------------------------------------------------------------- diff --git a/bsp/rm48x50/HALCoGen/source/sys_main.c b/bsp/rm48x50/HALCoGen/source/sys_main.c deleted file mode 100644 index b59cfe37f4..0000000000 --- a/bsp/rm48x50/HALCoGen/source/sys_main.c +++ /dev/null @@ -1,82 +0,0 @@ -/** @file sys_main.c -* @brief Application main file -* @date 29.May.2013 -* @version 03.05.02 -* -* This file contains an empty main function, -* which can be used for the application. -*/ - -/* (c) Texas Instruments 2009-2013, All rights reserved. */ - -/* USER CODE BEGIN (0) */ -/* we will use our own main and get rid off everything from HALCoGen here */ -#if 0 -#include <stdint.h> -/* USER CODE END */ - -/* Include Files */ - -#include "sys_common.h" -#include "system.h" - -/* USER CODE BEGIN (1) */ - -/* Include HET header file - types, definitions and function declarations for system driver */ -#include "het.h" -#include "esm.h" -#include "sci.h" -#include "rti.h" - -/* Task1 */ -void vTaskDelay(int t) -{ - for (; t; t--) - { - int i; - for(i = 100000;i ; i--) - { - } - } -} -/* USER CODE END */ - -/** @fn void main(void) -* @brief Application main function -* @note This function is empty by default. -* -* This function is called after startup. -* The user can use this function to implement the application. -*/ - -/* USER CODE BEGIN (2) */ -uint8_t sci_buf; -/* USER CODE END */ - -void main(void) -{ -/* USER CODE BEGIN (3) */ - - /* Set high end timer GIO port hetPort pin direction to all output */ - gioSetDirection(hetPORT1, 0xFFFFFFFF); - sciInit(); - rtiInit(); - rtiStartCounter(rtiCOUNTER_BLOCK1); - rtiEnableNotification(rtiNOTIFICATION_COMPARE3); - _enable_IRQ(); - sciReceive(scilinREG, 1, &sci_buf); - - for(;;) - { - gioSetBit(hetPORT1, 17, gioGetBit(hetPORT1, 17) ^ 1); - /* Taggle HET[1] with timer tick */ - /*sciSendByte(scilinREG, 'b');*/ - vTaskDelay(100); - /*sciSendByte(scilinREG, 'a');*/ - } -/* USER CODE END */ -} - -/* USER CODE BEGIN (4) */ -#endif -/* USER CODE END */ diff --git a/bsp/rm48x50/HALCoGen/source/sys_mpu.asm b/bsp/rm48x50/HALCoGen/source/sys_mpu.asm deleted file mode 100644 index 9d5ca152dd..0000000000 --- a/bsp/rm48x50/HALCoGen/source/sys_mpu.asm +++ /dev/null @@ -1,403 +0,0 @@ -;------------------------------------------------------------------------------- -; sys_mpu.asm -; -; (c) Texas Instruments 2009-2013, All rights reserved. -; - - .text - .arm - - -;------------------------------------------------------------------------------- -; Initalize Mpu - - .def _mpuInit_ - .asmfunc - -_mpuInit_ - stmfd sp!, {r0} - ; Disable mpu - mrc p15, #0, r0, c1, c0, #0 - bic r0, r0, #1 - dsb - mcr p15, #0, r0, c1, c0, #0 - isb - ; Disable background region - mrc p15, #0, r0, c1, c0, #0 - bic r0, r0, #0x20000 - mcr p15, #0, r0, c1, c0, #0 - ; Setup region 1 - mov r0, #0 - mcr p15, #0, r0, c6, c2, #0 - ldr r0, r1Base - mcr p15, #0, r0, c6, c1, #0 - mov r0, #0x0008 - orr r0, r0, #0x1000 - mcr p15, #0, r0, c6, c1, #4 - movw r0, #((1 << 15) + (1 << 14) + (1 << 13) + (1 << 12) + (1 << 11) + (1 << 10) + (1 << 9) + (1 << 8) + (0x1F << 1) + (1)) - mcr p15, #0, r0, c6, c1, #2 - ; Setup region 2 - mov r0, #1 - mcr p15, #0, r0, c6, c2, #0 - ldr r0, r2Base - mcr p15, #0, r0, c6, c1, #0 - mov r0, #0x0008 - orr r0, r0, #0x0600 - mcr p15, #0, r0, c6, c1, #4 - movw r0, #((0 << 15) + (0 << 14) + (0 << 13) + (0 << 12) + (0 << 11) + (0 << 10) + (0 << 9) + (0 << 8) + (0x15 << 1) + (1)) - mcr p15, #0, r0, c6, c1, #2 - ; Setup region - mov r0, #2 - mcr p15, #0, r0, c6, c2, #0 - ldr r0, r3Base - mcr p15, #0, r0, c6, c1, #0 - mov r0, #0x0008 - orr r0, r0, #0x0300 - mcr p15, #0, r0, c6, c1, #4 - movw r0, #((0 << 15) + (0 << 14) + (0 << 13) + (0 << 12) + (0 << 11) + (0 << 10) + (0 << 9) + (0 << 8) + (0x11 << 1) + (1)) - mcr p15, #0, r0, c6, c1, #2 - ; Setup region 4 - mov r0, #3 - mcr p15, #0, r0, c6, c2, #0 - ldr r0, r4Base - mcr p15, #0, r0, c6, c1, #0 - mov r0, #0x0008 - orr r0, r0, #0x0300 - mcr p15, #0, r0, c6, c1, #4 - movw r0, #((0 << 15) + (0 << 14) + (0 << 13) + (0 << 12) + (0 << 11) + (0 << 10) + (0 << 9) + (0 << 8) + (0x11 << 1) + (1)) - mcr p15, #0, r0, c6, c1, #2 - ; Setup region 5 - mov r0, #4 - mcr p15, #0, r0, c6, c2, #0 - ldr r0, r5Base - mcr p15, #0, r0, c6, c1, #0 - mov r0, #0x0000 - orr r0, r0, #0x0300 - mcr p15, #0, r0, c6, c1, #4 - movw r0, #((1 << 15) + (1 << 14) + (0 << 13) + (0 << 12) + (0 << 11) + (0 << 10) + (0 << 9) + (0 << 8) + (0x19 << 1) + (1)) - mcr p15, #0, r0, c6, c1, #2 - ; Setup region 6 - mov r0, #5 - mcr p15, #0, r0, c6, c2, #0 - ldr r0, r6Base - mcr p15, #0, r0, c6, c1, #0 - mov r0, #0x0000 - orr r0, r0, #0x0300 - mcr p15, #0, r0, c6, c1, #4 - movw r0, #((0 << 15) + (0 << 14) + (0 << 13) + (0 << 12) + (0 << 11) + (0 << 10) + (0 << 9) + (0 << 8) + (0x1A << 1) + (1)) - mcr p15, #0, r0, c6, c1, #2 - ; Setup region 7 - mov r0, #6 - mcr p15, #0, r0, c6, c2, #0 - ldr r0, r7Base - mcr p15, #0, r0, c6, c1, #0 - mov r0, #0x0008 - orr r0, r0, #0x1200 - mcr p15, #0, r0, c6, c1, #4 - movw r0, #((0 << 15) + (0 << 14) + (0 << 13) + (0 << 12) + (0 << 11) + (0 << 10) + (0 << 9) + (0 << 8) + (0x16 << 1) + (1)) - mcr p15, #0, r0, c6, c1, #2 - ; Setup region 8 - mov r0, #7 - mcr p15, #0, r0, c6, c2, #0 - ldr r0, r8Base - mcr p15, #0, r0, c6, c1, #0 - mov r0, #0x0010 - orr r0, r0, #0x1300 - mcr p15, #0, r0, c6, c1, #4 - movw r0, #((0 << 15) + (0 << 14) + (0 << 13) + (0 << 12) + (0 << 11) + (0 << 10) + (0 << 9) + (0 << 8) + (0x17 << 1) + (1)) - mcr p15, #0, r0, c6, c1, #2 - ; Setup region 9 - mov r0, #8 - mcr p15, #0, r0, c6, c2, #0 - ldr r0, r9Base - mcr p15, #0, r0, c6, c1, #0 - mov r0, #0x0010 - orr r0, r0, #0x1300 - mcr p15, #0, r0, c6, c1, #4 - movw r0, #((0 << 15) + (0 << 14) + (0 << 13) + (0 << 12) + (0 << 11) + (0 << 10) + (0 << 9) + (0 << 8) + (0x08 << 1) + (1)) - mcr p15, #0, r0, c6, c1, #2 - ; Setup region 10 - mov r0, #9 - mcr p15, #0, r0, c6, c2, #0 - ldr r0, r10Base - mcr p15, #0, r0, c6, c1, #0 - mov r0, #0x0010 - orr r0, r0, #0x1300 - mcr p15, #0, r0, c6, c1, #4 - movw r0, #((0 << 15) + (0 << 14) + (0 << 13) + (0 << 12) + (0 << 11) + (0 << 10) + (0 << 9) + (0 << 8) + (0x17 << 1) + (1)) - mcr p15, #0, r0, c6, c1, #2 - ; Setup region 11 - mov r0, #10 - mcr p15, #0, r0, c6, c2, #0 - ldr r0, r11Base - mcr p15, #0, r0, c6, c1, #0 - mov r0, #0x0008 - orr r0, r0, #0x1100 - mcr p15, #0, r0, c6, c1, #4 - movw r0, #((1 << 15) + (1 << 14) + (1 << 13) + (0 << 12) + (0 << 11) + (0 << 10) + (0 << 9) + (0 << 8) + (0x0A << 1) + (0)) - mcr p15, #0, r0, c6, c1, #2 - ; Setup region 12 - mov r0, #11 - mcr p15, #0, r0, c6, c2, #0 - ldr r0, r12Base - mcr p15, #0, r0, c6, c1, #0 - mov r0, #0x0008 - orr r0, r0, #0x1300 - mcr p15, #0, r0, c6, c1, #4 - movw r0, #((1 << 15) + (1 << 14) + (0 << 13) + (0 << 12) + (0 << 11) + (0 << 10) + (0 << 9) + (0 << 8) + (0x15 << 1) + (0)) - mcr p15, #0, r0, c6, c1, #2 - - - ; Enable mpu background region - mrc p15, #0, r0, c1, c0, #0 - orr r0, r0, #0x20000 - mcr p15, #0, r0, c1, c0, #0 - ; Enable mpu - mrc p15, #0, r0, c1, c0, #0 - orr r0, r0, #1 - dsb - mcr p15, #0, r0, c1, c0, #0 - isb - ldmfd sp!, {r0} - bx lr - -r1Base .word 0x00000000 -r2Base .word 0x00000000 -r3Base .word 0x08000000 -r4Base .word 0x08400000 -r5Base .word 0x60000000 -r6Base .word 0x80000000 -r7Base .word 0xF0000000 -r8Base .word 0xFC000000 -r9Base .word 0xFE000000 -r10Base .word 0xFF000000 -r11Base .word 0x08001000 -r12Base .word 0x20000000 - - .endasmfunc - - -;------------------------------------------------------------------------------- -; Enable Mpu - - .def _mpuEnable_ - .asmfunc - -_mpuEnable_ - - stmfd sp!, {r0} - mrc p15, #0, r0, c1, c0, #0 - orr r0, r0, #1 - dsb - mcr p15, #0, r0, c1, c0, #0 - isb - ldmfd sp!, {r0} - bx lr - - .endasmfunc - - -;------------------------------------------------------------------------------- -; Disable Mpu - - .def _mpuDisable_ - .asmfunc - -_mpuDisable_ - - stmfd sp!, {r0} - mrc p15, #0, r0, c1, c0, #0 - bic r0, r0, #1 - dsb - mcr p15, #0, r0, c1, c0, #0 - isb - ldmfd sp!, {r0} - bx lr - - .endasmfunc - - -;------------------------------------------------------------------------------- -; Enable Mpu background region - - .def _mpuEnableBackgroundRegion_ - .asmfunc - -_mpuEnableBackgroundRegion_ - - stmfd sp!, {r0} - mrc p15, #0, r0, c1, c0, #0 - orr r0, r0, #0x20000 - mcr p15, #0, r0, c1, c0, #0 - ldmfd sp!, {r0} - bx lr - - .endasmfunc - - -;------------------------------------------------------------------------------- -; Disable Mpu background region - - .def _mpuDisableBackgroundRegion_ - .asmfunc - -_mpuDisableBackgroundRegion_ - - stmfd sp!, {r0} - mrc p15, #0, r0, c1, c0, #0 - bic r0, r0, #0x20000 - mcr p15, #0, r0, c1, c0, #0 - ldmfd sp!, {r0} - bx lr - - .endasmfunc - - -;------------------------------------------------------------------------------- -; Returns number of implemented Mpu regions - - .def _mpuGetNumberOfRegions_ - .asmfunc - -_mpuGetNumberOfRegions_ - - mrc p15, #0, r0, c0, c0, #4 - uxtb r0, r0, ROR #8 - bx lr - - .endasmfunc - - -;------------------------------------------------------------------------------- -; Returns the type of the implemented mpu regions - - .def _mpuAreRegionsSeparate_ - .asmfunc - -_mpuAreRegionsSeparate_ - - mrc p15, #0, r0, c0, c0, #4 - uxtb r0, r0 - bx lr - - .endasmfunc - - -;------------------------------------------------------------------------------- -; Set mpu region number - - .def _mpuSetRegion_ - .asmfunc - -_mpuSetRegion_ - - mcr p15, #0, r0, c6, c2, #0 - bx lr - - .endasmfunc - - -;------------------------------------------------------------------------------- -; Get mpu region number - - .def _mpuGetRegion_ - .asmfunc - -_mpuGetRegion_ - - mrc p15, #0, r0, c6, c2, #0 - bx lr - - .endasmfunc - - -;------------------------------------------------------------------------------- -; Set base address - - .def _mpuSetRegionBaseAddress_ - .asmfunc - -_mpuSetRegionBaseAddress_ - - mcr p15, #0, r0, c6, c1, #0 - bx lr - - .endasmfunc - - -;------------------------------------------------------------------------------- -; Get base address - - .def _mpuGetRegionBaseAddress_ - .asmfunc - -_mpuGetRegionBaseAddress_ - - mrc p15, #0, r0, c6, c1, #0 - bx lr - - .endasmfunc - - -;------------------------------------------------------------------------------- -; Set type and permission - - .def _mpuSetRegionTypeAndPermission_ - .asmfunc - -_mpuSetRegionTypeAndPermission_ - - orr r0, r0, r1 - mcr p15, #0, r0, c6, c1, #4 - bx lr - - .endasmfunc - - -;------------------------------------------------------------------------------- -; Get type - - .def _mpuGetRegionType_ - .asmfunc - -_mpuGetRegionType_ - - mrc p15, #0, r0, c6, c1, #4 - bic r0, r0, #0xFF00 - bx lr - - .endasmfunc - - -;------------------------------------------------------------------------------- -; Get permission - - .def _mpuGetRegionPermission_ - .asmfunc - -_mpuGetRegionPermission_ - - mrc p15, #0, r0, c6, c1, #4 - bic r0, r0, #0xFF - bx lr - - .endasmfunc - - -;------------------------------------------------------------------------------- -; Set region size register value - - .def _mpuSetRegionSizeRegister_ - .asmfunc - -_mpuSetRegionSizeRegister_ - - mcr p15, #0, r0, c6, c1, #2 - bx lr - - .endasmfunc - - - -;------------------------------------------------------------------------------- - diff --git a/bsp/rm48x50/HALCoGen/source/sys_pcr.c b/bsp/rm48x50/HALCoGen/source/sys_pcr.c deleted file mode 100644 index 870fc6e3b3..0000000000 --- a/bsp/rm48x50/HALCoGen/source/sys_pcr.c +++ /dev/null @@ -1,602 +0,0 @@ -/** @file sys_pcr.c -* @brief PCR Driver Implementation File -* @date 29.May.2013 -* @version 03.05.02 -* -*/ -/* (c) Texas Instruments 2009-2013, All rights reserved. */ - -#include "sys_pcr.h" - -/* USER CODE BEGIN (0) */ -/* USER CODE END */ - -/* USER CODE BEGIN (1) */ -/* USER CODE END */ - -/** @fn void peripheral_Frame_Protection_Set(peripheral_Frame_Select_t peripheral_Frame) -* @brief Set the peripheral protection of the selected frame -* @param[in] peripheral_Frame - Peripheral frame to be protected -* -* This function sets the protection for the selected frame. -*/ -void peripheral_Frame_Protection_Set(peripheral_Frame_Select_t peripheral_Frame) -{ - -/* USER CODE BEGIN (2) */ -/* USER CODE END */ - - uint32 chip_select_grp; - uint32 Quarant_selct; - - chip_select_grp = (peripheral_Frame.Peripheral_CS >> 3U); - Quarant_selct = (uint32)(peripheral_Frame.Peripheral_Quadrant << ((peripheral_Frame.Peripheral_CS & 7U) << 2U)); - - if (chip_select_grp >= 3U) - { - pcrREG->PPROTSET3 = Quarant_selct; - } - else if (chip_select_grp >= 2U) - { - pcrREG->PPROTSET2 = Quarant_selct; - } - else if (chip_select_grp >= 1U) - { - pcrREG->PPROTSET1 = Quarant_selct; - } - else - { - pcrREG->PPROTSET0 = Quarant_selct; - } - -/* USER CODE BEGIN (3) */ -/* USER CODE END */ -} - -/* USER CODE BEGIN (4) */ -/* USER CODE END */ - -/** @fn void peripheral_Frame_Protection_Clr(peripheral_Frame_Select_t peripheral_Frame) -* @brief Clear the peripheral protection of the selected frame -* @param[in] peripheral_Frame - Peripheral frame to be out of protection -* -* This function clears the protection set for the selected frame. -*/ -void peripheral_Frame_Protection_Clr(peripheral_Frame_Select_t peripheral_Frame) -{ - -/* USER CODE BEGIN (5) */ -/* USER CODE END */ - - uint32 chip_select_grp; - uint32 Quarant_selct; - - chip_select_grp = (peripheral_Frame.Peripheral_CS >> 3U); - Quarant_selct = (uint32)(peripheral_Frame.Peripheral_Quadrant << ((peripheral_Frame.Peripheral_CS & 7U) << 2U)); - - if (chip_select_grp >= 3U) - { - pcrREG->PPROTCLR3 = Quarant_selct; - } - else if (chip_select_grp >= 2U) - { - pcrREG->PPROTCLR2 = Quarant_selct; - } - else if (chip_select_grp >= 1U) - { - pcrREG->PPROTCLR1 = Quarant_selct; - } - else - { - pcrREG->PPROTCLR0 = Quarant_selct; - } - -/* USER CODE BEGIN (6) */ -/* USER CODE END */ -} - -/* USER CODE BEGIN (7) */ -/* USER CODE END */ - -/** @fn void peripheral_Frame_Powerdown_Set(peripheral_Frame_Select_t peripheral_Frame) -* @brief Take the selected peripheral to powerdown -* @param[in] peripheral_Frame - Peripheral frame to be taken to powerdown -* -* This function will set the selected peripheral frame to powerdown. -*/ -void peripheral_Frame_Powerdown_Set(peripheral_Frame_Select_t peripheral_Frame) -{ - -/* USER CODE BEGIN (8) */ -/* USER CODE END */ - - uint32 chip_select_grp; - uint32 Quarant_selct; - - chip_select_grp = (peripheral_Frame.Peripheral_CS >> 3U); - Quarant_selct = (uint32)(peripheral_Frame.Peripheral_Quadrant << ((peripheral_Frame.Peripheral_CS & 7U) << 2U)); - - if (chip_select_grp >= 3U) - { - pcrREG->PSPWRDWNSET3 = Quarant_selct; - } - else if (chip_select_grp >= 2U) - { - pcrREG->PSPWRDWNSET2 = Quarant_selct; - } - else if (chip_select_grp >= 1U) - { - pcrREG->PSPWRDWNSET1 = Quarant_selct; - } - else - { - pcrREG->PSPWRDWNSET0 = Quarant_selct; - } - -/* USER CODE BEGIN (9) */ -/* USER CODE END */ -} - -/* USER CODE BEGIN (10) */ -/* USER CODE END */ - -/** @fn void peripheral_Frame_Powerdown_Clr(peripheral_Frame_Select_t peripheral_Frame) -* @brief Bring the selected peripheral frame out of powerdown -* @param[in] peripheral_Frame - Peripheral frame to be taken out of powerdown -* -* This function will bring the selected peripheral frame out of powerdown. -*/ -void peripheral_Frame_Powerdown_Clr(peripheral_Frame_Select_t peripheral_Frame) -{ - -/* USER CODE BEGIN (11) */ -/* USER CODE END */ - - uint32 chip_select_grp; - uint32 Quarant_selct; - - chip_select_grp = (peripheral_Frame.Peripheral_CS >> 3U); - Quarant_selct = (uint32)(peripheral_Frame.Peripheral_Quadrant << ((peripheral_Frame.Peripheral_CS & 7U) << 2U)); - - if (chip_select_grp >= 3U) - { - pcrREG->PSPWRDWNCLR3 = Quarant_selct; - } - else if (chip_select_grp >= 2U) - { - pcrREG->PSPWRDWNCLR2 = Quarant_selct; - } - else if (chip_select_grp >= 1U) - { - pcrREG->PSPWRDWNCLR1 = Quarant_selct; - } - else - { - pcrREG->PSPWRDWNCLR0 = Quarant_selct; - } -/* USER CODE BEGIN (12) */ -/* USER CODE END */ -} - -/* USER CODE BEGIN (13) */ -/* USER CODE END */ - -/** @fn void peripheral_Mem_Frame_Prot_Set(peripheral_MemoryFrame_CS_t peripheral_Memory_Frame_CS) -* @brief Set the peripheral memory protection of the selected frame -* @param[in] peripheral_Memory_Frame_CS - Peripheral memory frame to be protected -* -* This function sets the protection for the selected peripheral memory frame. -*/ -void peripheral_Mem_Frame_Prot_Set(peripheral_MemoryFrame_CS_t peripheral_Memory_Frame_CS) -{ - -/* USER CODE BEGIN (14) */ -/* USER CODE END */ - - uint32 chip_select_grp; - - chip_select_grp = (peripheral_Memory_Frame_CS >> 5U); - - if (chip_select_grp >= 1U) - { - pcrREG->PMPROTSET1 = (1U << (peripheral_Memory_Frame_CS & 0xFU)); - } - else - { - pcrREG->PMPROTSET0 = (1U << peripheral_Memory_Frame_CS); - } - -/* USER CODE BEGIN (15) */ -/* USER CODE END */ -} - -/* USER CODE BEGIN (16) */ -/* USER CODE END */ - -/** @fn void peripheral_Mem_Frame_Prot_Clr(peripheral_MemoryFrame_CS_t peripheral_Memory_Frame_CS) -* @brief Clear the peripheral memory protection of the selected frame -* @param[in] peripheral_Memory_Frame_CS - Peripheral memory frame to be cleared from protection -* -* This function clears the protection set for the selected peripheral memory frame. -*/ -void peripheral_Mem_Frame_Prot_Clr(peripheral_MemoryFrame_CS_t peripheral_Memory_Frame_CS) -{ - -/* USER CODE BEGIN (17) */ -/* USER CODE END */ - - uint32 chip_select_grp; - - chip_select_grp = (peripheral_Memory_Frame_CS >> 5U); - - if (chip_select_grp >= 1U) - { - pcrREG->PMPROTCLR1 = (1U << (peripheral_Memory_Frame_CS & 0xFU)); - } - else - { - pcrREG->PMPROTCLR0 = (1U << peripheral_Memory_Frame_CS); - } - -/* USER CODE BEGIN (18) */ -/* USER CODE END */ -} - -/* USER CODE BEGIN (19) */ -/* USER CODE END */ - -/** @fn void peripheral_Mem_Frame_Pwrdwn_Set(peripheral_MemoryFrame_CS_t peripheral_Memory_Frame_CS) -* @brief Take the selected peripheral memory frame to powerdown -* @param[in] peripheral_Memory_Frame_CS - Peripheral memory frame to be taken to powerdown -* -* This function will set the selected peripheral memory frame to powerdown. -*/ -void peripheral_Mem_Frame_Pwrdwn_Set(peripheral_MemoryFrame_CS_t peripheral_Memory_Frame_CS) -{ - -/* USER CODE BEGIN (20) */ -/* USER CODE END */ - - uint32 chip_select_grp; - - chip_select_grp = (peripheral_Memory_Frame_CS >> 5U); - - if (chip_select_grp >= 1U) - { - pcrREG->PSPWRDWNSET1 = (1U << (peripheral_Memory_Frame_CS & 0xFU)); - } - else - { - pcrREG->PSPWRDWNSET0 = (1U << peripheral_Memory_Frame_CS); - } - -/* USER CODE BEGIN (21) */ -/* USER CODE END */ -} - -/* USER CODE BEGIN (22) */ -/* USER CODE END */ - -/** @fn void peripheral_Mem_Frame_Pwrdwn_Clr (peripheral_MemoryFrame_CS_t peripheral_Memory_Frame_CS) -* @brief Bring the selected peripheral Memory frame out of powerdown -* @param[in] peripheral_Memory_Frame_CS - Peripheral memory frame to be taken out of powerdown -* -* This function will bring the selected peripheral memory frame out of powerdown. -*/ -void peripheral_Mem_Frame_Pwrdwn_Clr (peripheral_MemoryFrame_CS_t peripheral_Memory_Frame_CS) -{ - -/* USER CODE BEGIN (23) */ -/* USER CODE END */ - - uint32 chip_select_grp; - - chip_select_grp = (peripheral_Memory_Frame_CS >> 5U); - - if (chip_select_grp >= 1U) - { - pcrREG->PSPWRDWNCLR1 = (1U << (peripheral_Memory_Frame_CS & 0xFU)); - } - else - { - pcrREG->PSPWRDWNCLR0 = (1U << peripheral_Memory_Frame_CS); - } - -/* USER CODE BEGIN (24) */ -/* USER CODE END */ -} - -/* USER CODE BEGIN (25) */ -/* USER CODE END */ - -/** @fn void peripheral_Protection_Set(peripheral_Quad_ChipSelect_t peripheral_Quad_CS) -* @brief Set the peripheral protection of all the selected frames -* @param[in] peripheral_Quad_CS - All Peripheral frames to be protected -* -* This function sets the protection for all the selected frames. -*/ -void peripheral_Protection_Set(peripheral_Quad_ChipSelect_t peripheral_Quad_CS) -{ - -/* USER CODE BEGIN (26) */ -/* USER CODE END */ - - pcrREG->PPROTSET0 = peripheral_Quad_CS.Peripheral_Quad0_3_CS0_7; - pcrREG->PPROTSET1 = peripheral_Quad_CS.Peripheral_Quad4_7_CS8_15; - pcrREG->PPROTSET2 = peripheral_Quad_CS.Peripheral_Quad8_11_CS16_23; - pcrREG->PPROTSET3 = peripheral_Quad_CS.Peripheral_Quad12_15_CS24_31; - -/* USER CODE BEGIN (27) */ -/* USER CODE END */ -} - -/* USER CODE BEGIN (28) */ -/* USER CODE END */ - -/** @fn void peripheral_Protection_Clr(peripheral_Quad_ChipSelect_t peripheral_Quad_CS) -* @brief Clear the peripheral protection of all the selected frames -* @param[in] peripheral_Quad_CS - All Peripheral frames to be out of protection. -* -* This function clears the protection set for all the selected frame. -*/ -void peripheral_Protection_Clr(peripheral_Quad_ChipSelect_t peripheral_Quad_CS) -{ - -/* USER CODE BEGIN (29) */ -/* USER CODE END */ - - pcrREG->PPROTCLR0 = peripheral_Quad_CS.Peripheral_Quad0_3_CS0_7; - pcrREG->PPROTCLR1 = peripheral_Quad_CS.Peripheral_Quad4_7_CS8_15; - pcrREG->PPROTCLR2 = peripheral_Quad_CS.Peripheral_Quad8_11_CS16_23; - pcrREG->PPROTCLR3 = peripheral_Quad_CS.Peripheral_Quad12_15_CS24_31; - -/* USER CODE BEGIN (30) */ -/* USER CODE END */ -} - -/* USER CODE BEGIN (31) */ -/* USER CODE END */ - -/** @fn void peripheral_Powerdown_Set(peripheral_Quad_ChipSelect_t peripheral_Quad_CS) -* @brief Take all the selected peripheral frame to powerdown -* @param[in] peripheral_Quad_CS - Peripheral frames to be taken to powerdown -* -* This function will set all the selected peripheral frame to powerdown. -*/ -void peripheral_Powerdown_Set(peripheral_Quad_ChipSelect_t peripheral_Quad_CS) -{ - -/* USER CODE BEGIN (32) */ -/* USER CODE END */ - - pcrREG->PSPWRDWNSET0 = peripheral_Quad_CS.Peripheral_Quad0_3_CS0_7; - pcrREG->PSPWRDWNSET1 = peripheral_Quad_CS.Peripheral_Quad4_7_CS8_15; - pcrREG->PSPWRDWNSET2 = peripheral_Quad_CS.Peripheral_Quad8_11_CS16_23; - pcrREG->PSPWRDWNSET3 = peripheral_Quad_CS.Peripheral_Quad12_15_CS24_31; - -/* USER CODE BEGIN (33) */ -/* USER CODE END */ -} - -/* USER CODE BEGIN (34) */ -/* USER CODE END */ - -/** @fn void peripheral_Powerdown_Clr(peripheral_Quad_ChipSelect_t peripheral_Quad_CS) -* @brief Bring all the selected peripheral frame out of powerdown -* @param[in] peripheral_Quad_CS - Peripheral frames to be taken out of powerdown -* -* This function will bring all the selected peripheral frame out of powerdown. -*/ -void peripheral_Powerdown_Clr(peripheral_Quad_ChipSelect_t peripheral_Quad_CS) -{ - -/* USER CODE BEGIN (35) */ -/* USER CODE END */ - - pcrREG->PSPWRDWNCLR0 = peripheral_Quad_CS.Peripheral_Quad0_3_CS0_7; - pcrREG->PSPWRDWNCLR1 = peripheral_Quad_CS.Peripheral_Quad4_7_CS8_15; - pcrREG->PSPWRDWNCLR2 = peripheral_Quad_CS.Peripheral_Quad8_11_CS16_23; - pcrREG->PSPWRDWNCLR3 = peripheral_Quad_CS.Peripheral_Quad12_15_CS24_31; - -/* USER CODE BEGIN (36) */ -/* USER CODE END */ -} - -/* USER CODE BEGIN (37) */ -/* USER CODE END */ - -/** @fn void peripheral_Memory_Protection_Set(peripheral_Memory_ChipSelect_t peripheral_Memory_CS) -* @brief Set the peripheral memory protection of all the selected frame -* @param[in] peripheral_Memory_CS - Peripheral memory frames to be protected -* -* This function sets the protection for all the selected peripheral memory frame. -*/ -void peripheral_Memory_Protection_Set(peripheral_Memory_ChipSelect_t peripheral_Memory_CS) -{ - -/* USER CODE BEGIN (38) */ -/* USER CODE END */ - - pcrREG->PMPROTSET0 = peripheral_Memory_CS.Peripheral_Mem_CS0_31; - pcrREG->PMPROTSET1 = peripheral_Memory_CS.Peripheral_Mem_CS32_63; - -/* USER CODE BEGIN (39) */ -/* USER CODE END */ -} - -/* USER CODE BEGIN (40) */ -/* USER CODE END */ - -/** @fn void peripheral_Memory_Protection_Clr(peripheral_Memory_ChipSelect_t peripheral_Memory_CS) -* @brief Clear the peripheral memory protection of all the selected frame -* @param[in] peripheral_Memory_CS - Peripheral memory frames to be cleared from protection -* -* This function clears the protection set for all the selected peripheral memory frame. -*/ -void peripheral_Memory_Protection_Clr(peripheral_Memory_ChipSelect_t peripheral_Memory_CS) -{ - -/* USER CODE BEGIN (41) */ -/* USER CODE END */ - - pcrREG->PMPROTCLR0 = peripheral_Memory_CS.Peripheral_Mem_CS0_31; - pcrREG->PMPROTCLR1 = peripheral_Memory_CS.Peripheral_Mem_CS32_63; - -/* USER CODE BEGIN (42) */ -/* USER CODE END */ -} - -/* USER CODE BEGIN (43) */ -/* USER CODE END */ - -/** @fn void peripheral_Memory_Powerdown_Set(peripheral_Memory_ChipSelect_t peripheral_Memory_CS) -* @brief Take all the selected peripheral memory frame to powerdown -* @param[in] peripheral_Memory_CS - Peripheral memory frames to be taken to powerdown -* -* This function will set all the selected peripheral memory frame to powerdown. -*/ -void peripheral_Memory_Powerdown_Set(peripheral_Memory_ChipSelect_t peripheral_Memory_CS) -{ - -/* USER CODE BEGIN (44) */ -/* USER CODE END */ - - pcrREG->PSPWRDWNSET0 = peripheral_Memory_CS.Peripheral_Mem_CS0_31; - pcrREG->PSPWRDWNSET1 = peripheral_Memory_CS.Peripheral_Mem_CS32_63; - -/* USER CODE BEGIN (45) */ -/* USER CODE END */ -} - -/* USER CODE BEGIN (46) */ -/* USER CODE END */ - -/** @fn void peripheral_Memory_Powerdown_Clr(peripheral_Memory_ChipSelect_t peripheral_Memory_CS) -* @brief Bring all the selected peripheral Memory frame out of powerdown -* @param[in] peripheral_Memory_CS - Peripheral memory frames to be taken out of powerdown -* -* This function will bring all the selected peripheral memory frame out of powerdown. -*/ -void peripheral_Memory_Powerdown_Clr(peripheral_Memory_ChipSelect_t peripheral_Memory_CS) -{ - -/* USER CODE BEGIN (47) */ -/* USER CODE END */ - - pcrREG->PSPWRDWNCLR0 = peripheral_Memory_CS.Peripheral_Mem_CS0_31; - pcrREG->PSPWRDWNCLR1 = peripheral_Memory_CS.Peripheral_Mem_CS32_63; - -/* USER CODE BEGIN (48) */ -/* USER CODE END */ -} - -/* USER CODE BEGIN (49) */ -/* USER CODE END */ - -/** @fn peripheral_Quad_ChipSelect_t peripheral_Powerdown_Status(void) -* @brief Get the powerdown status of the peripheral frames. -* @return Peripheral frames power down status -* -* This function gets the powerdown status of the peripheral frames. -*/ -peripheral_Quad_ChipSelect_t peripheral_Powerdown_Status(void) -{ - -/* USER CODE BEGIN (50) */ -/* USER CODE END */ - - peripheral_Quad_ChipSelect_t peripheral_Quad_CS; - - peripheral_Quad_CS.Peripheral_Quad0_3_CS0_7 = pcrREG->PSPWRDWNSET0; - peripheral_Quad_CS.Peripheral_Quad4_7_CS8_15 = pcrREG->PSPWRDWNSET1; - peripheral_Quad_CS.Peripheral_Quad8_11_CS16_23 = pcrREG->PSPWRDWNSET2; - peripheral_Quad_CS.Peripheral_Quad12_15_CS24_31 = pcrREG->PSPWRDWNSET3; - -/* USER CODE BEGIN (51) */ -/* USER CODE END */ - - return peripheral_Quad_CS; -} - -/* USER CODE BEGIN (52) */ -/* USER CODE END */ - -/** @fn peripheral_Quad_ChipSelect_t peripheral_Protection_Status(void) -* @brief Get the protection status of the peripheral frames -* @return Peripheral frames protection status -* -* This function gets the protection status of the peripheral frames. -*/ -peripheral_Quad_ChipSelect_t peripheral_Protection_Status(void) -{ - -/* USER CODE BEGIN (53) */ -/* USER CODE END */ - - peripheral_Quad_ChipSelect_t peripheral_Quad_CS; - - peripheral_Quad_CS.Peripheral_Quad0_3_CS0_7 = pcrREG->PPROTSET0; - peripheral_Quad_CS.Peripheral_Quad4_7_CS8_15 = pcrREG->PPROTSET1; - peripheral_Quad_CS.Peripheral_Quad8_11_CS16_23 = pcrREG->PPROTSET2; - peripheral_Quad_CS.Peripheral_Quad12_15_CS24_31 = pcrREG->PPROTSET3; - -/* USER CODE BEGIN (54) */ -/* USER CODE END */ - - return peripheral_Quad_CS; -} - -/* USER CODE BEGIN (55) */ -/* USER CODE END */ - -/** @fn peripheral_Memory_ChipSelect_t peripheral_Memory_Protection_Status(void) -* @brief Get the protection set of all the peripheral Memory frame -* @return Peripheral memory frames protection status -* -* This function gets the protection status of all the peripheral Memory frame. -*/ -peripheral_Memory_ChipSelect_t peripheral_Memory_Protection_Status(void) -{ - -/* USER CODE BEGIN (56) */ -/* USER CODE END */ - - peripheral_Memory_ChipSelect_t peripheral_Memory_CS; - - peripheral_Memory_CS.Peripheral_Mem_CS0_31 = pcrREG->PMPROTSET0; - peripheral_Memory_CS.Peripheral_Mem_CS32_63 = pcrREG->PMPROTSET1; - -/* USER CODE BEGIN (57) */ -/* USER CODE END */ - - return peripheral_Memory_CS; -} - -/* USER CODE BEGIN (58) */ -/* USER CODE END */ - -/** @fn peripheral_Memory_ChipSelect_t Periipheral_Memory_Powerdown_Status(void) -* @brief Get the powerdown status of all the peripheral Memory frame -* @return Peripheral memory frames powerdown status -* -* This function gets the powerdown status of all the peripheral Memory frame. -*/ -peripheral_Memory_ChipSelect_t Periipheral_Memory_Powerdown_Status(void) -{ - -/* USER CODE BEGIN (59) */ -/* USER CODE END */ - - peripheral_Memory_ChipSelect_t peripheral_Memory_CS; - - peripheral_Memory_CS.Peripheral_Mem_CS0_31 = pcrREG->PSPWRDWNSET0; - peripheral_Memory_CS.Peripheral_Mem_CS32_63 = pcrREG->PSPWRDWNSET1; - -/* USER CODE BEGIN (60) */ -/* USER CODE END */ - - return peripheral_Memory_CS; -} - -/* USER CODE BEGIN (61) */ -/* USER CODE END */ diff --git a/bsp/rm48x50/HALCoGen/source/sys_phantom.c b/bsp/rm48x50/HALCoGen/source/sys_phantom.c deleted file mode 100644 index 3e84d2c237..0000000000 --- a/bsp/rm48x50/HALCoGen/source/sys_phantom.c +++ /dev/null @@ -1,32 +0,0 @@ -/** @file sys_phantom.c -* @brief Phantom Interrupt Source File -* @date 29.May.2013 -* @version 03.05.02 -* -* This file contains: -* - Phantom Interrupt Handler -*/ - -/* (c) Texas Instruments 2009-2013, All rights reserved. */ - -#include "sys_common.h" - -/* USER CODE BEGIN (0) */ -/* USER CODE END */ - -/* Phantom Interrupt Handler */ - -/* USER CODE BEGIN (1) */ -/* USER CODE END */ - -#pragma CODE_STATE(phantomInterrupt, 32) -#pragma INTERRUPT(phantomInterrupt, IRQ) - -void phantomInterrupt(void) -{ -/* USER CODE BEGIN (2) */ -/* USER CODE END */ -} - -/* USER CODE BEGIN (3) */ -/* USER CODE END */ diff --git a/bsp/rm48x50/HALCoGen/source/sys_pmm.c b/bsp/rm48x50/HALCoGen/source/sys_pmm.c deleted file mode 100644 index 8dc5615d47..0000000000 --- a/bsp/rm48x50/HALCoGen/source/sys_pmm.c +++ /dev/null @@ -1,348 +0,0 @@ -/** @file sys_pmm.c -* @brief PCR Driver Implementation File -* @date 29.May.2013 -* @version 03.05.02 -* -*/ -/* (c) Texas Instruments 2009-2013, All rights reserved. */ - -#include "sys_pmm.h" - -/** @fn void pmmInit(void) -* @brief Initializes the PMM Driver -* -* This function initializes the PMM module. -*/ -void pmmInit(void) -{ - /*Disable clocks to all logic domains*/ - pmmREG->PDCLKDISREG = 0xFU; - /*Enable or disable clock to pmctrl_wakeup block and automatic clock wake up*/ - pmmREG->GLOBALCTRL1 = (0U << 8U) | (0U << 0U); /*from GUI*/ - /*Power on the logic power domains*/ - pmmREG->LOGICPDPWRCTRL0 = PMM_LOGICPDPWRCTRL0_CONFIGVALUE; - /*Power on the memory-only power domains*/ - pmmREG->MEMPDPWRCTRL0 = PMM_MEMPDPWRCTRL0_CONFIGVALUE; - - /*wait till Logic Power Domain PD2 turns ON*/ - while((pmmREG->LOGICPDPWRSTAT[PMM_LOGICPD2] & PMM_LOGICPDPWRSTAT_DOMAINON) == 0U) - { - }/* Wait */ - /*wait till Logic Power Domain PD3 turns ON*/ - while((pmmREG->LOGICPDPWRSTAT[PMM_LOGICPD3] & PMM_LOGICPDPWRSTAT_DOMAINON) == 0U) - { - }/* Wait */ - /*wait till Logic Power Domain PD4 turns OFF*/ - while((pmmREG->LOGICPDPWRSTAT[PMM_LOGICPD4] & PMM_LOGICPDPWRSTAT_LOGICPDPWRSTAT) != 0U) - { - }/* Wait */ - /*wait till Logic Power Domain PD5 turns ON*/ - while((pmmREG->LOGICPDPWRSTAT[PMM_LOGICPD5] & PMM_LOGICPDPWRSTAT_DOMAINON) == 0U) - { - }/* Wait */ - - /*wait till Memory Only Power Domain RAM_PD1 turns ON*/ - while((pmmREG->MEMPDPWRSTAT[PMM_MEMPD1] & PMM_MEMPDPWRSTAT_DOMAINON) == 0U) - { - }/* Wait */ - /*wait till Memory Only Power Domain RAM_PD2 turns ON*/ - while((pmmREG->MEMPDPWRSTAT[PMM_MEMPD2] & PMM_MEMPDPWRSTAT_DOMAINON) == 0U) - { - }/* Wait */ - /*wait till Memory Only Power Domain RAM_PD3 turns ON*/ - while((pmmREG->MEMPDPWRSTAT[PMM_MEMPD3] & PMM_MEMPDPWRSTAT_DOMAINON) == 0U) - { - }/* Wait */ - if ((pmmREG->GLOBALCTRL1 & PMM_GLOBALCTRL1_AUTOCLKWAKEENA) == 0U) - { - /* Enable clocks for the selected logic domain */ - pmmREG->PDCLKDISREG = PMM_PDCLKDISREG_CONFIGVALUE; - } - -} - - -/** @fn void pmmTurnONLogicPowerDomain(pmm_LogicPD_t logicPD) -* @brief Turns on Logic Power Domain -* @param[in] logicPD - Power Domain to be turned on -* - PMM_LOGICPD2: Power domain PD2 will be turned on -* - PMM_LOGICPD3: Power domain PD3 will be turned on -* - PMM_LOGICPD4: Power domain PD4 will be turned on -* - PMM_LOGICPD5: Power domain PD5 will be turned on -* -* This function turns on the selected Logic Power Domain -* -*/ -void pmmTurnONLogicPowerDomain(pmm_LogicPD_t logicPD) -{ - if (logicPD != PMM_LOGICPD1) - { - /* Power on the domain */ - if (logicPD == PMM_LOGICPD2) - { - pmmREG->LOGICPDPWRCTRL0 = (pmmREG->LOGICPDPWRCTRL0 & 0xF0FFFFFFU) | (0x5U << 24U); - } - else if (logicPD == PMM_LOGICPD3) - { - pmmREG->LOGICPDPWRCTRL0 = (pmmREG->LOGICPDPWRCTRL0 & 0xFFF0FFFFU) | (0x5U << 16U); - } - else if (logicPD == PMM_LOGICPD4) - { - pmmREG->LOGICPDPWRCTRL0 = (pmmREG->LOGICPDPWRCTRL0 & 0xFFFFF0FFU) | (0x5U << 8U); - } - else - { - pmmREG->LOGICPDPWRCTRL0 = (pmmREG->LOGICPDPWRCTRL0 & 0xFFFFFFF0U) | (0x5U << 0U); - } - /* Wait until the power domain turns on */ - while((pmmREG->LOGICPDPWRSTAT[logicPD] & PMM_LOGICPDPWRSTAT_DOMAINON) == 0U) - { - }/* Wait */ - if ((pmmREG->GLOBALCTRL1 & PMM_GLOBALCTRL1_AUTOCLKWAKEENA) == 0U) - { - /* Enable clocks to the power domain */ - pmmREG->PDCLKDISCLRREG = 1U << (uint32)logicPD; - } - } -} - -/** @fn void pmmTurnONMemPowerDomain(pmm_MemPD_t memPD) -* @brief Turns on Memory Power Domain -* @param[in] memPD - Power Domain to be tured on -* - PMM_MEMPD1: Power domain RAM_PD1 will be turned on -* - PMM_MEMPD2: Power domain RAM_PD2 will be turned on -* - PMM_MEMPD3: Power domain RAM_PD3 will be turned on -* -* This function turns on the selected Memory Power Domain -* -*/ -void pmmTurnONMemPowerDomain(pmm_MemPD_t memPD) -{ - /* Power on the domain */ - if (memPD == PMM_MEMPD1) - { - pmmREG->MEMPDPWRCTRL0 = (pmmREG->MEMPDPWRCTRL0 & 0xF0FFFFFFU) | (0x5U << 24U); - } - else if (memPD == PMM_MEMPD2) - { - pmmREG->MEMPDPWRCTRL0 = (pmmREG->MEMPDPWRCTRL0 & 0xFFF0FFFFU) | (0x5U << 16U); - } - else - { - pmmREG->MEMPDPWRCTRL0 = (pmmREG->MEMPDPWRCTRL0 & 0xFFFFF0FFU) | (0x5U << 8U); - } - /*Wait until the power domain turns on*/ - while((pmmREG->MEMPDPWRSTAT[memPD] & PMM_MEMPDPWRSTAT_DOMAINON) == 0U) - { - }/* Wait */ -} - -/** @fn void pmmTurnOFFLogicPowerDomain(pmm_LogicPD_t logicPD) -* @brief Turns off Logic Power Domain -* @param[in] logicPD - Power Domain to be tured off -* - PMM_LOGICPD2: Power domain PD2 will be turned off -* - PMM_LOGICPD3: Power domain PD3 will be turned off -* - PMM_LOGICPD4: Power domain PD4 will be turned off -* - PMM_LOGICPD5: Power doamin PD5 will be turned off -* -* This function turns off the selected Logic Power Domain -* -*/ -void pmmTurnOFFLogicPowerDomain(pmm_LogicPD_t logicPD) -{ - if (logicPD != PMM_LOGICPD1) - { - /* Disable all clocks to the power domain */ - pmmREG->PDCLKDISSETREG = 1U << (uint32)logicPD; - - /* Power down the domain */ - if (logicPD == PMM_LOGICPD2) - { - pmmREG->LOGICPDPWRCTRL0 = (pmmREG->LOGICPDPWRCTRL0 & 0xF0FFFFFFU) | (0xAU << 24U); - } - else if (logicPD == PMM_LOGICPD3) - { - pmmREG->LOGICPDPWRCTRL0 = (pmmREG->LOGICPDPWRCTRL0 & 0xFFF0FFFFU) | (0xAU << 16U); - } - else if (logicPD == PMM_LOGICPD4) - { - pmmREG->LOGICPDPWRCTRL0 = (pmmREG->LOGICPDPWRCTRL0 & 0xFFFFF0FFU) | (0xAU << 8U); - } - else - { - pmmREG->LOGICPDPWRCTRL0 = (pmmREG->LOGICPDPWRCTRL0 & 0xFFFFFFF0U) | (0xAU << 0U); - } - /* Wait until the power domain turns off */ - while((pmmREG->LOGICPDPWRSTAT[logicPD] & PMM_LOGICPDPWRSTAT_LOGICPDPWRSTAT) != 0U) - { - }/* Wait */ - } -} - -/** @fn void pmmTurnOFFMemPowerDomain(pmm_MemPD_t memPD) -* @brief Turns off Memory Power Domain -* @param[in] memPD - Power Domain to be tured off -* - PMM_MEMPD1: Power domain RAM_PD1 will be turned off -* - PMM_MEMPD2: Power domain RAM_PD2 will be turned off -* - PMM_MEMPD3: Power domain RAM_PD3 will be turned off -* -* This function turns off the selected Memory Power Domain -* -*/ -void pmmTurnOFFMemPowerDomain(pmm_MemPD_t memPD) -{ - /* Power down the domain */ - if (memPD == PMM_MEMPD1) - { - pmmREG->MEMPDPWRCTRL0 = (pmmREG->MEMPDPWRCTRL0 & 0xF0FFFFFFU) | (0xAU << 24U); - } - else if (memPD == PMM_MEMPD2) - { - pmmREG->MEMPDPWRCTRL0 = (pmmREG->MEMPDPWRCTRL0 & 0xFFF0FFFFU) | (0xAU << 16U); - } - else - { - pmmREG->MEMPDPWRCTRL0 = (pmmREG->MEMPDPWRCTRL0 & 0xFFFFF0FFU) | (0xAU << 8U); - } - /*Wait until the power domain turns off*/ - while((pmmREG->MEMPDPWRSTAT[memPD] & PMM_MEMPDPWRSTAT_MEMPDPWRSTAT) != 0U) - { - }/* Wait */ -} - -/** @fn boolean pmmIsLogicPowerDomainActive(pmm_LogicPD_t logicPD) -* @brief Check if the power domain is active or not -* @param[in] logicPD - Power Domain to be be checked -* - PMM_LOGICPD2: Checks whether Power domain PD2 is active or not -* - PMM_LOGICPD3: Checks whether Power domain PD3 is active or not -* - PMM_LOGICPD4: Checks whether Power domain PD4 is active or not -* - PMM_LOGICPD5: Checks whether Power domain PD5 is active or not -* @return The function will return: -* - TRUE : When the selected power domain is in Active state. -* - FALSE: When the selected power domain is in OFF state. -* -* This function checks whether the selected power domain is active or not. -* -*/ -boolean pmmIsLogicPowerDomainActive(pmm_LogicPD_t logicPD) -{ - boolean status; - if ((pmmREG->LOGICPDPWRSTAT[logicPD] & PMM_LOGICPDPWRSTAT_DOMAINON) == 0U) - { - status = FALSE; - } - else - { - status = TRUE; - } - return status; -} - -/** @fn boolean pmmIsMemPowerDomainActive(pmm_MemPD_t memPD) -* @brief Check if the power domain is active or not -* @param[in] memPD - Power Domain to be tured off -* - PMM_MEMPD1: Checks whether Power domain RAM_PD1 is active or not -* - PMM_MEMPD2: Checks whether Power domain RAM_PD2 is active or not -* - PMM_MEMPD3: Checks whether Power domain RAM_PD3 is active or not -* @return The function will return: -* - TRUE : When the selected power domain is in Active state. -* - FALSE: When the selected power domain is in OFF state. -* -* This function checks whether the selected power domain is active or not. -* -*/ -boolean pmmIsMemPowerDomainActive(pmm_MemPD_t memPD) -{ - boolean status; - if ((pmmREG->MEMPDPWRSTAT[memPD] & PMM_MEMPDPWRSTAT_DOMAINON) == 0U) - { - status = FALSE; - } - else - { - status = TRUE; - } - return status; -} - -/** @fn void pmmGetConfigValue(pmm_config_reg_t *config_reg, config_value_type_t type) -* @brief Get the initial or current values of the configuration register -* @param[in] *config_reg - pointer to the struct to which the initial or current value of the configuration registers need to be stored -* @param[in] type - whether initial or current value of the configuration registers need to be stored -* - InitialValue: initial value of the configuration registers will be stored in the struct pointed by config_reg -* - CurrentValue: initial value of the configuration registers will be stored in the struct pointed by config_reg -* This function will copy the initial or current value (depending on the parameter 'type') of the configuration registers to the struct pointed by config_reg -*/ -void pmmGetConfigValue(pmm_config_reg_t *config_reg, config_value_type_t type) -{ - if (type == InitialValue) - { - config_reg->CONFIG_LOGICPDPWRCTRL0 = PMM_LOGICPDPWRCTRL0_CONFIGVALUE; - config_reg->CONFIG_MEMPDPWRCTRL0 = PMM_MEMPDPWRCTRL0_CONFIGVALUE; - config_reg->CONFIG_PDCLKDISREG = PMM_PDCLKDISREG_CONFIGVALUE; - config_reg->CONFIG_GLOBALCTRL1 = PMM_GLOBALCTRL1_CONFIGVALUE; - } - else - { - config_reg->CONFIG_LOGICPDPWRCTRL0 = pmmREG->LOGICPDPWRCTRL0; - config_reg->CONFIG_MEMPDPWRCTRL0 = pmmREG->MEMPDPWRCTRL0; - config_reg->CONFIG_PDCLKDISREG = pmmREG->PDCLKDISREG; - config_reg->CONFIG_GLOBALCTRL1 = pmmREG->GLOBALCTRL1; - } -} - -/** @fn void pmmSetMode(pmm_Mode_t mode) -* @brief Set PSCON Compare Block Mode -* @param[in] mode - PSCON Compare Block mode -* - LockStep : PSCON compare block is set to Lock-Step mode -* - SelfTest : PSCON compare block is set to Self-Test mode -* - ErrorForcing : PSCON compare block is set to Error-Forcing mode -* - SelfTestErrorForcing : PSCON compare block is set to Self-Test-Error-Forcing mode -* -* This function sets the PSCON Compare block to the selected mode -* -*/ -void pmmSetMode(pmm_Mode_t mode) -{ - /* Set PSCON Compare Block Mode */ - pmmREG->PRCKEYREG = mode; -} - -/** @fn boolean pmmPerformSelfTest(void) -* @brief Perform self test and return the result -* -* @return The function will return -* - TRUE if PSCON compare block passed self-test -* - FALSE if PSCON compare block failed in self-test -* -* This function checks whether PSCON compare block passed the self-test or not. -* -*/ -boolean pmmPerformSelfTest(void) -{ - boolean status = TRUE; - /*Enter self-test mode*/ - pmmREG->PRCKEYREG = SelfTest; - /*Wait till self test is completed*/ - while ((pmmREG->LPDDCSTAT1 & 0xFU) != 0xFU) - { - }/* Wait */ - - while ((pmmREG->MPDDCSTAT1 & 0x7U) != 0x7U) - { - }/* Wait */ - - /*Check whether self-test passed or not*/ - if ((pmmREG->LPDDCSTAT2 & 0xFU) != 0U) - { - status = FALSE; - } - if ((pmmREG->MPDDCSTAT2 & 0x7U) != 0U) - { - status = FALSE; - } - /*Enter lock-step mode*/ - pmmREG->PRCKEYREG = LockStep; - - return status; -} diff --git a/bsp/rm48x50/HALCoGen/source/sys_pmu.asm b/bsp/rm48x50/HALCoGen/source/sys_pmu.asm deleted file mode 100644 index c60bb91bf7..0000000000 --- a/bsp/rm48x50/HALCoGen/source/sys_pmu.asm +++ /dev/null @@ -1,223 +0,0 @@ -;------------------------------------------------------------------------------- -; sys_pmu.asm -; -; (c) Texas Instruments 2009-2013, All rights reserved. -; - - .text - .arm - - -;------------------------------------------------------------------------------- -; Initialize Pmu -; Note: It will reset all counters - - .def _pmuInit_ - .asmfunc - -_pmuInit_ - - stmfd sp!, {r0} - ; set control register - mrc p15, #0, r0, c9, c12, #0 - orr r0, r0, #(1 << 4) + 6 + 1 - mcr p15, #0, r0, c9, c12, #0 - ; clear flags - mov r0, #0 - sub r1, r1, #1 - mcr p15, #0, r0, c9, c12, #3 - ; select counter 0 event - mcr p15, #0, r0, c9, c12, #5 ; select counter - mov r0, #0x11 - mcr p15, #0, r0, c9, c13, #1 ; select event - ; select counter 1 event - mov r0, #1 - mcr p15, #0, r0, c9, c12, #5 ; select counter - mov r0, #0x11 - mcr p15, #0, r0, c9, c13, #1 ; select event - ; select counter 2 event - mov r0, #2 - mcr p15, #0, r0, c9, c12, #5 ; select counter - mov r0, #0x11 - mcr p15, #0, r0, c9, c13, #1 ; select event - ldmfd sp!, {r0} - bx lr - - .endasmfunc - - -;------------------------------------------------------------------------------- -; Enable Counters Global [Cycle, Event [0..2]] -; Note: It will reset all counters - - .def _pmuEnableCountersGlobal_ - .asmfunc - -_pmuEnableCountersGlobal_ - - stmfd sp!, {r0} - mrc p15, #0, r0, c9, c12, #0 - orr r0, r0, #7 - mcr p15, #0, r0, c9, c12, #0 - ldmfd sp!, {r0} - bx lr - - .endasmfunc - -;------------------------------------------------------------------------------- -; Disable Counters Global [Cycle, Event [0..2]] - - .def _pmuDisableCountersGlobal_ - .asmfunc - -_pmuDisableCountersGlobal_ - - stmfd sp!, {r0} - mrc p15, #0, r0, c9, c12, #0 - bic r0, r0, #1 - mcr p15, #0, r0, c9, c12, #0 - ldmfd sp!, {r0} - bx lr - - .endasmfunc - -;------------------------------------------------------------------------------- -; Reset Cycle Counter - - .def _pmuResetCycleCounter_ - .asmfunc - -_pmuResetCycleCounter_ - - stmfd sp!, {r0} - mrc p15, #0, r0, c9, c12, #0 - orr r0, r0, #4 - mcr p15, #0, r0, c9, c12, #0 - ldmfd sp!, {r0} - bx lr - - .endasmfunc - -;------------------------------------------------------------------------------- -; Reset Event Counters [0..2] - - .def _pmuResetEventCounters_ - .asmfunc - -_pmuResetEventCounters_ - - stmfd sp!, {r0} - mrc p15, #0, r0, c9, c12, #0 - orr r0, r0, #2 - mcr p15, #0, r0, c9, c12, #0 - ldmfd sp!, {r0} - bx lr - - .endasmfunc - -;------------------------------------------------------------------------------- -; Reset Cycle Counter abd Event Counters [0..2] - - .def _pmuResetCounters_ - .asmfunc - -_pmuResetCounters_ - - stmfd sp!, {r0} - mrc p15, #0, r0, c9, c12, #0 - orr r0, r0, #6 - mcr p15, #0, r0, c9, c12, #0 - ldmfd sp!, {r0} - bx lr - - .endasmfunc - -;------------------------------------------------------------------------------- -; Start Counters [Cycle, 0..2] - - .def _pmuStartCounters_ - .asmfunc - -_pmuStartCounters_ - - mcr p15, #0, r0, c9, c12, #1 - bx lr - - .endasmfunc - -;------------------------------------------------------------------------------- -; Stop Counters [Cycle, 0..2] - - .def _pmuStopCounters_ - .asmfunc - -_pmuStopCounters_ - - mcr p15, #0, r0, c9, c12, #2 - bx lr - - .endasmfunc - -;------------------------------------------------------------------------------- -; Set Count event - - .def _pmuSetCountEvent_ - .asmfunc - -_pmuSetCountEvent_ - - lsr r0, r0, #1 - mcr p15, #0, r0, c9, c12, #5 ; select counter - mcr p15, #0, r1, c9, c13, #1 ; select event - bx lr - - .endasmfunc - -;------------------------------------------------------------------------------- -; Get Cycle Count - - .def _pmuGetCycleCount_ - .asmfunc - -_pmuGetCycleCount_ - - mrc p15, #0, r0, c9, c13, #0 - bx lr - - .endasmfunc - -;------------------------------------------------------------------------------- -; Get Event Counter Count Value - - .def _pmuGetEventCount_ - .asmfunc - -_pmuGetEventCount_ - - lsr r0, r0, #1 - mcr p15, #0, r0, c9, c12, #5 ; select counter - mrc p15, #0, r0, c9, c13, #2 ; read event counter - bx lr - - .endasmfunc - -;------------------------------------------------------------------------------- -; Get Overflow Flags - - .def _pmuGetOverflow_ - .asmfunc - -_pmuGetOverflow_ - - mrc p15, #0, r0, c9, c12, #3 ; read overflow - mov r1, #0 - sub r1, r1, #1 - mcr p15, #0, r1, c9, c12, #3 ; clear flags - bx lr - - .endasmfunc - - - -;------------------------------------------------------------------------------- - diff --git a/bsp/rm48x50/HALCoGen/source/sys_selftest.c b/bsp/rm48x50/HALCoGen/source/sys_selftest.c deleted file mode 100644 index ffc698c470..0000000000 --- a/bsp/rm48x50/HALCoGen/source/sys_selftest.c +++ /dev/null @@ -1,2178 +0,0 @@ -/** @file sys_selftest.c -* @brief Selftest Source File -* @date 29.May.2013 -* @version 03.05.02 -* -* This file contains: -* - Selftest API's -*/ - -/* (c) Texas Instruments 2009-2013, All rights reserved. */ - -/* USER CODE BEGIN (0) */ -/* USER CODE END */ - -#include "sys_selftest.h" - -/* USER CODE BEGIN (1) */ -/* USER CODE END */ - -/** @fn void ccmSelfCheck(void) -* @brief CCM module self check Driver -* -* This function self checks the CCM module. -*/ -void ccmSelfCheck(void) -{ -/* USER CODE BEGIN (2) */ -/* USER CODE END */ - - /* Run a diagnostic check on the CCM-R4F module */ - /* This step ensures that the CCM-R4F can actually indicate an error */ - - /* Configure CCM in self-test mode */ - CCMKEYR = 0x6U; - /* Wait for CCM self-test to complete */ - while ((CCMSR & 0x100U) != 0x100U) - { - }/* Wait */ - -/* USER CODE BEGIN (3) */ -/* USER CODE END */ - - /* Check if there was an error during the self-test */ - if ((CCMSR & 0x1U) == 0x1U) - { - /* STE is set */ - ccmFail(0U); - } - else - { - /* Check CCM-R4 self-test error flag by itself (without compare error) */ - if ((esmREG->ESTATUS1[0U] & 0x80000000U) != 0x80000000U) - { - /* ESM flag is not set */ - ccmFail(1U); - } - else - { - /* clear ESM group1 channel 31 flag */ - esmREG->ESTATUS1[0U] = 0x80000000U; - - /* Configure CCM in error-forcing mode */ - CCMKEYR = 0x9U; - - /* check if compare error flag is set */ - if ((esmREG->ESTATUS1[1U] & 0x4U) != 0x4U) - { - /* ESM flag is not set */ - ccmFail(2U); - } - else - { - /* Check FIQIVEC to ESM High Interrupt flag is set */ - if((vimREG->FIQINDEX & 0x000000FFU) != 1U) - { - /* ESM High Interrupt flag is not set in VIM*/ - ccmFail(3U); - } - /* clear ESM group2 channel 2 flag */ - esmREG->ESTATUS1[1U] = 0x4U; - - /* clear ESM group2 shadow status flag */ - esmREG->ESTATUS5EMU = 0x4U; - - /* ESM self-test error needs to also be cleared */ - esmREG->ESTATUS1[0U] = 0x80000000U; - - /* Clear CCM-R4 CMPE flag */ - CCMSR = 0x00010000U; - - /* Return CCM-R4 to lock-step mode */ - CCMKEYR = 0x0U; - - /* The nERROR pin will become inactive once the LTC counter expires */ - esmREG->KEY = 0x5U; - } - } - } -} - -/* USER CODE BEGIN (4) */ -/* USER CODE END */ - -/** @fn void ccmFail(uint32 x) -* @brief CCM module fail service routine -* -* This function is called if CCM module selftest fail. -*/ -void ccmFail(uint32 x) -{ -/* USER CODE BEGIN (5) */ -/* USER CODE END */ - if (x == 0U) - { - /* CCM-R4 is not able to flag a compare error in self-test mode. - * Lock-step operation cannot be verified. - */ -/* USER CODE BEGIN (6) */ -/* USER CODE END */ - } - else if (x == 1U) - { - /* CCM-R4 self-test error flag is not set in ESM register. - * Could be due to a connection issue inside the part. - */ -/* USER CODE BEGIN (7) */ -/* USER CODE END */ - } - else if (x == 2U) - { - /* CCM-R4 compare error flag is not set in ESM. - * Lock-step operation cannot be verified. - */ -/* USER CODE BEGIN (8) */ -/* USER CODE END */ - } - else if (x == 3U) - { - /* ESM High Interrupt Flag is not set in VIM. - */ -/* USER CODE BEGIN (9) */ -/* USER CODE END */ - } - else - { - /* */ -/* USER CODE BEGIN (10) */ -/* USER CODE END */ - } -} - -/** @fn void memoryInit(uint32 ram) -* @brief Memory Initialization Driver -* -* This function is called to perform Memory initialization of selected RAM's. -*/ -void memoryInit(uint32 ram) -{ -/* USER CODE BEGIN (11) */ -/* USER CODE END */ - - /* Enable Memory Hardware Initialization */ - systemREG1->MINITGCR = 0xAU; - - /* Enable Memory Hardware Initialization for selected RAM's */ - systemREG1->MSINENA = ram; - - /* Wait until Memory Hardware Initialization complete */ - while((systemREG1->MSTCGSTAT & 0x00000100U) != 0x00000100U) - { - }/* Wait */ - - /* Disable Memory Hardware Initialization */ - systemREG1->MINITGCR = 0x5U; - -/* USER CODE BEGIN (12) */ -/* USER CODE END */ -} - -/** @fn void stcSelfCheck(void) -* @brief STC module self check Driver -* -* This function is called to perform STC module self check. -*/ -void stcSelfCheck(void) -{ -/* USER CODE BEGIN (13) */ -/* USER CODE END */ - volatile uint32 i = 0U; - - /* Run a diagnostic check on the CPU self-test controller */ - /* First set up the STC clock divider as STC is only supported up to 90MHz */ - - /* STC clock is now normal mode CPU clock frequency/2 = 180MHz/2 */ - systemREG2->STCCLKDIV = 0x01000000U; - - /* Select one test interval, restart self-test next time, 0x00010001 */ - stcREG->STCGCR0 = 0x00010001U; - - /* Enable comparator self-check and stuck-at-0 fault insertion in CPU, 0x1A */ - stcREG->STCSCSCR = 0x1AU; - - /* Maximum time-out period */ - stcREG->STCTPR = 0xFFFFFFFFU; - - /* wait for 16 VBUS clock cycles at least, based on HCLK to VCLK ratio */ - for (i=0U; i<(16U + (16U * 1U)); i++){ /* Wait */ } - - /* Enable self-test */ - stcREG->STCGCR1 = 0xAU; - - /* wait for 16 VBUS clock cycles at least, based on HCLK to VCLK ratio */ - for (i=0U; i<(16U + (16U * 1U)); i++){ /* Wait */ } - -/* USER CODE BEGIN (14) */ -/* USER CODE END */ - - /* Idle the CPU so that the self-test can start */ - _gotoCPUIdle_(); - -/* USER CODE BEGIN (15) */ -/* USER CODE END */ -} - -/** @fn void cpuSelfTest(uint32 no_of_intervals, uint32 max_timeout, boolean restart_test) -* @brief CPU self test Driver -* @param[in] no_of_intervals - Number of Test Intervals to be -* @param[in] max_timeout - Maximum Timeout to complete selected test Intervals -* @param[in] restart_test - Restart the test from Interval 0 or Continue from where it stopped. -* -* This function is called to perform CPU self test using STC module. -*/ -void cpuSelfTest(uint32 no_of_intervals, uint32 max_timeout, boolean restart_test) -{ - volatile uint32 i = 0U; - -/* USER CODE BEGIN (16) */ -/* USER CODE END */ - - /* Run specified no of test intervals starting from interval 0 */ - /* Start test from interval 0 or continue the test. */ - stcREG->STCGCR0 = (no_of_intervals << 16U) - | (uint32) restart_test; - - /* Configure Maximum time-out period */ - stcREG->STCTPR = max_timeout; - - /* wait for 16 VBUS clock cycles at least, based on HCLK to VCLK ratio */ - for (i=0U; i<(16U + (16U * 1U)); i++){ /* Wait */ } - - /* Enable self-test */ - stcREG->STCGCR1 = 0xAU; - -/* USER CODE BEGIN (17) */ -/* USER CODE END */ - /* Idle the CPU so that the self-test can start */ - - _gotoCPUIdle_(); - -} - -/** @fn void pbistSelfCheck(void) -* @brief PBIST self test Driver -* -* This function is called to perform PBIST self test. -*/ -void pbistSelfCheck(void) -{ - volatile uint32 i = 0U; -/* USER CODE BEGIN (18) */ -/* USER CODE END */ - /* Run a diagnostic check on the memory self-test controller */ - /* First set up the PBIST ROM clock as this clock frequency is limited to 90MHz */ - - /* PBIST ROM clock frequency = HCLK frequency /2 */ - systemREG1->MSTGCR |= 0x00000100U; - - /* Enable PBIST controller */ - systemREG1->MSINENA = 0x1U; - - /* clear MSTGENA field */ - systemREG1->MSTGCR &= ~(0xFU); - - /* Enable PBIST self-test */ - systemREG1->MSTGCR |= 0xAU; - - /* wait for 32 VBUS clock cycles at least, based on HCLK to VCLK ratio */ - for (i=0U; i<(32U + (32U * 1U)); i++){ /* Wait */ } - -/* USER CODE BEGIN (19) */ -/* USER CODE END */ - - /* Enable PBIST clocks and ROM clock */ - pbistREG->PACT = 0x3U; - - /* Select algo#3, march13n to be run */ - pbistREG->ALGO = 0x00000004U; - - /* Select RAM Group 1, which is actually the PBIST ROM */ - pbistREG->RINFOL = 0x1U; - - /* ROM contents will not override ALGO and RINFOx settings */ - pbistREG->OVER = 0x0U; - - /* Algorithm code is loaded from ROM */ - pbistREG->ROM = 0x3U; - - /* Start PBIST */ - pbistREG->DLR = 0x14U; - - /* wait until memory self-test done is indicated */ - while ((systemREG1->MSTCGSTAT & 0x1U) != 0x1U) - { - }/* Wait */ - - /* Check for the failure */ - if (((pbistREG->FSRF0 & 0x1U) != 0x1U) & ((pbistREG->FSRF1 & 0x1U) != 0x1U)) - { - /* no failure was indicated even if the march13n algorithm was run on a ROM */ - pbistSelfCheckFail(); -/* USER CODE BEGIN (20) */ -/* USER CODE END */ - } - else - { - /* PBIST self-check has passed */ - - /* Disable PBIST clocks and ROM clock */ - pbistREG->PACT = 0x0U; - - /* Disable PBIST */ - systemREG1->MSTGCR &= ~(0xFU); - systemREG1->MSTGCR |= 0x5U; - -/* USER CODE BEGIN (21) */ -/* USER CODE END */ - } -} - -/** @fn void pbistSelfCheckFail(void) -* @brief PBIST self test Driver failure service routine -* -* This function is called on PBIST self test failure. -*/ -void pbistSelfCheckFail(void) -{ - /* The PBIST controller is not capable of reporting a failure. - * PBIST cannot be used to verify memory integrity. - * Need custom handler here. - */ -/* USER CODE BEGIN (22) */ -/* USER CODE END */ -} - -/** @fn void pbistRun(uint32 raminfoL, uint32 algomask) -* @brief CPU self test Driver -* @param[in] raminfoL - Select the list of RAM to be tested. -* @param[in] algomask - Select the list of Algorithm to be run. -* -* This function performs Memory Built-in Self test using PBIST module. -*/ -void pbistRun(uint32 raminfoL, uint32 algomask) -{ - volatile uint32 i = 0U; - -/* USER CODE BEGIN (23) */ -/* USER CODE END */ - - /* PBIST ROM clock frequency = HCLK frequency /2 */ - systemREG1->MSTGCR |= 0x00000100U; - - /* Enable PBIST controller */ - systemREG1->MSINENA = 0x1U; - - /* clear MSTGENA field */ - systemREG1->MSTGCR &= ~(0xFU); - - /* Enable PBIST self-test */ - systemREG1->MSTGCR |= 0xAU; - - /* wait for 32 VBUS clock cycles at least, based on HCLK to VCLK ratio */ - for (i=0U; i<(32U + (32U * 1U)); i++){ /* Wait */ } - -/* USER CODE BEGIN (24) */ -/* USER CODE END */ - - /* Enable PBIST clocks and ROM clock */ - pbistREG->PACT = 0x3U; - - /* Select all algorithms to be tested */ - pbistREG->ALGO = algomask; - - /* Select RAM groups */ - pbistREG->RINFOL = raminfoL; - - /* Select all RAM groups */ - pbistREG->RINFOU = 0x00000000U; - - /* ROM contents will not override RINFOx settings */ - pbistREG->OVER = 0x0U; - - /* Algorithm code is loaded from ROM */ - pbistREG->ROM = 0x3U; - - /* Start PBIST */ - pbistREG->DLR = 0x14U; - -/* USER CODE BEGIN (25) */ -/* USER CODE END */ -} - -/** @fn void pbistStop(void) -* @brief Routine to stop PBIST test enabled. -* -* This function is called to stop PBIST after test is performed. -*/ -void pbistStop(void) -{ -/* USER CODE BEGIN (26) */ -/* USER CODE END */ - /* disable pbist clocks and ROM clock */ - pbistREG->PACT = 0x0U; - systemREG1->MSTGCR &= ~(0xFU); - systemREG1->MSTGCR |= 0x5U; -/* USER CODE BEGIN (27) */ -/* USER CODE END */ -} - -/** @fn boolean pbistIsTestCompleted(void) -* @brief Checks to see if the PBIST test is completed. -* @return 1 if PBIST test completed, otherwise 0. -* -* Checks to see if the PBIST test is completed. -*/ -boolean pbistIsTestCompleted(void) -{ -/* USER CODE BEGIN (28) */ -/* USER CODE END */ - - return ((systemREG1->MSTCGSTAT & 0x1U) != 0U); -/* USER CODE BEGIN (29) */ -/* USER CODE END */ -} - -/** @fn boolean pbistIsTestPassed(void) -* @brief Checks to see if the PBIST test is completed successfully. -* @return 1 if PBIST test passed, otherwise 0. -* -* Checks to see if the PBIST test is completed successfully. -*/ -boolean pbistIsTestPassed(void) -{ -/* USER CODE BEGIN (30) */ -/* USER CODE END */ - - return (((pbistREG->FSRF0 ==0U) && (pbistREG->FSRF1 ==0U)) == TRUE); -/* USER CODE BEGIN (31) */ -/* USER CODE END */ -} - -/** @fn boolean pbistPortTestStatus(uint32 port) -* @brief Checks to see if the PBIST Port test is completed successfully. -* @param[in] port - Select the port to get the status. -* @return 1 if PBIST Port test completed successfully, otherwise 0. -* -* Checks to see if the selected PBIST Port test is completed successfully. -*/ -boolean pbistPortTestStatus(uint32 port) -{ - boolean status; -/* USER CODE BEGIN (32) */ -/* USER CODE END */ - - if(port == PBIST_PORT0) - { - status = ((boolean)pbistREG->FSRF0 == 0U); - } - else - { - status = ((boolean)pbistREG->FSRF1 == 0U); - } - - return status; -} - -/** @fn void efcCheck(void) -* @brief EFUSE module self check Driver -* -* This function self checks the EFSUE module. -*/ -void efcCheck(void) -{ - uint32 efcStatus = 0U; - -/* USER CODE BEGIN (33) */ -/* USER CODE END */ - - /* read the EFC Error Status Register */ - efcStatus = efcREG->ERROR; - -/* USER CODE BEGIN (34) */ -/* USER CODE END */ - - if (efcStatus == 0x0U) - { - /* run stuck-at-zero test and check if it passed */ - if (efcStuckZeroTest()== TRUE) - { - /* start EFC ECC logic self-test */ - efcSelfTest(); - } - else - { - /* EFC output is stuck-at-zero, device operation unreliable */ - efcClass2Error(); - } - } - /* EFC Error Register is not zero */ - else - { - /* one-bit error detected during autoload */ - if (efcStatus == 0x15U) - { - /* start EFC ECC logic self-test */ - efcSelfTest(); - } - else - { - /* Some other EFC error was detected */ - efcClass2Error(); - } - } -} - -/** @fn boolean efcStuckZeroTest(void) -* @brief Checks to see if the EFUSE Stuck at zero test is completed successfully. -* @return 1 if EFUSE Stuck at zero test completed, otherwise 0. -* -* Checks to see if the EFUSE Stuck at zero test is completed successfully. -*/ -boolean efcStuckZeroTest(void) -{ -/* USER CODE BEGIN (35) */ -/* USER CODE END */ - - boolean result = FALSE; - uint32 error_checks = EFC_INSTRUCTION_INFO_EN | - EFC_INSTRUCTION_ERROR_EN | - EFC_AUTOLOAD_ERROR_EN | - EFC_SELF_TEST_ERROR_EN ; - - /* configure the output enable for auto load error , instruction info, - instruction error, and self test error using boundary register - and drive values one across all the errors */ - efcREG->BOUNDARY = (OUTPUT_ENABLE | error_checks); - - /* Read from the pin register. This register holds the current values - of above errors. This value should be 0x5c00.If not at least one of - the above errors is stuck at 0. */ - if ((efcREG->PINS & 0x5C00U) == 0x5C00U) - { - /* check if the ESM group1 channels 40 is set and group3 channel 2 is set */ - if (((esmREG->ESTATUS4[0U] & 0x200U) == 0x200U) & ((esmREG->ESTATUS1[2U] & 0x2U) == 0x2U)) - { - /* stuck-at-zero test passed */ - result = TRUE; - } - } - - /* put the pins back low */ - efcREG->BOUNDARY = OUTPUT_ENABLE; - - /* clear group1 flags */ - esmREG->ESTATUS4[0U] = 0x300U; - - /* clear group3 flag */ - esmREG->ESTATUS1[2U] = 0x2U; - - /* The nERROR pin will become inactive once the LTC counter expires */ - esmREG->KEY = 0x5U; - - return result; -} - -/** @fn void efcSelfTest(void) -* @brief EFUSE module self check Driver -* -* This function self checks the EFSUE module. -*/ -void efcSelfTest(void) -{ -/* USER CODE BEGIN (36) */ -/* USER CODE END */ - /* configure self-test cycles */ - efcREG->SELF_TEST_CYCLES = 0x258U; - - /* configure self-test signature */ - efcREG->SELF_TEST_SIGN = 0x5362F97FU; - - /* configure boundary register to start ECC self-test */ - efcREG->BOUNDARY = 0x0000200FU; -} - -/** @fn boolean checkefcSelfTest(void) -* @brief EFUSE module self check Driver -* -* This function self checks the EFSUE module. -*/ -boolean checkefcSelfTest(void) -{ -/* USER CODE BEGIN (37) */ -/* USER CODE END */ - boolean result = FALSE; - - /* wait until EFC self-test is done */ - while((!(efcREG->PINS & EFC_SELF_TEST_DONE)) != 0U) - { - }/* Wait */ - - /* check if EFC self-test error occurred */ - if (((!(efcREG->PINS & EFC_SELF_TEST_ERROR)) & (!(efcREG->ERROR & SELF_TEST_ERROR))) !=0U) - { - /* check if EFC self-test error is set */ - if ((esmREG->ESTATUS4[0U] & 0x100U) != 0x100U) - { - result = TRUE; - } - } - return result; -} - -/** @fn void efcClass1Error(void) -* @brief EFUSE Class1 Error service routine -* -* This function is called if EFC ECC logic self-test. -*/ -void efcClass1Error(void) -{ -/* USER CODE BEGIN (38) */ -/* USER CODE END */ - /* Autoload error was detected during device power-up, and device operation is not reliable. */ - /* for(;;) can be removed by adding "# if 0" and "# endif" in the user codes above and below */ -/* USER CODE BEGIN (39) */ -/* USER CODE END */ - for(;;) - { - }/* Wait */ -/* USER CODE BEGIN (40) */ -/* USER CODE END */ -} - -/** @fn void efcClass2Error(void) -* @brief EFUSE Class2 Error service routine -* -* This function is called if EFC output is stuck-at-zero. -*/ -void efcClass2Error(void) -{ -/* USER CODE BEGIN (41) */ -/* USER CODE END */ - /* The ECC logic inside the eFuse controller is not operational. Device operation is not reliable. */ - /* for(;;) can be removed by adding "# if 0" and "# endif" in the user codes above and below */ -/* USER CODE BEGIN (42) */ -/* USER CODE END */ - for(;;) - { - }/* Wait */ -/* USER CODE BEGIN (43) */ -/* USER CODE END */ -} - -/** @fn void fmcBus2Check(void) -* @brief Self Check Flash Bus2 Interface -* -* This function self checks Flash Bus2 Interface -*/ -void fmcBus2Check(void) -{ -/* USER CODE BEGIN (44) */ -/* USER CODE END */ - /* enable ECC logic inside FMC */ - flashWREG->FEDACCTRL1 = 0x000A060AU; - - if ((esmREG->ESTATUS1[0U] & 0x40U) == 0x40U) - { - /* a 1-bit error was detected during flash OTP read by flash module - run a self-check on ECC logic inside FMC */ - - /* clear ESM group1 channel 6 flag */ - esmREG->ESTATUS1[0U] = 0x40U; - - fmcECCcheck(); - } - - /* no 2-bit or 1-bit error detected during power-up */ - else - { - fmcECCcheck(); - } -/* USER CODE BEGIN (45) */ -/* USER CODE END */ -} - -/** @fn void fmcECCcheck(void) -* @brief Check Flash ECC Single Bit and multi Bit errors detection logic. -* -* This function Checks Flash ECC Single Bit and multi Bit errors detection logic. -*/ -void fmcECCcheck(void) -{ - volatile uint32 otpread; - volatile uint32 temp; - -/* USER CODE BEGIN (46) */ -/* USER CODE END */ - - /* read location with deliberate 1-bit error */ - otpread = flash1bitError; - if ((esmREG->ESTATUS1[0U] & 0x40U) == 0x40U) - { - /* 1-bit failure was indicated and corrected */ - flashWREG->FEDACSTATUS = 0x00010006U; - - /* clear ESM group1 channel 6 flag */ - esmREG->ESTATUS1[0U] = 0x40U; - - /* read location with deliberate 2-bit error */ - otpread = flash2bitError; - if ((esmREG->ESTATUS1[2U] & 0x80U) == 0x80U) - { - /* 2-bit failure was detected correctly */ - temp = flashWREG->FUNCERRADD; - flashWREG->FEDACSTATUS = 0x00020100U; - - /* clear ESM group3 channel 7 */ - esmREG->ESTATUS1[2U] = 0x80U; - - /* The nERROR pin will become inactive once the LTC counter expires */ - esmREG->KEY = 0x5U; - - } - else - { - /* ECC logic inside FMC cannot detect 2-bit error */ - fmcClass2Error(); - } - } - else - { - /* ECC logic inside FMC cannot detect 1-bit error */ - fmcClass2Error(); - } -/* USER CODE BEGIN (47) */ -/* USER CODE END */ -} - -/** @fn void fmcClass1Error(void) -* @brief Flash Multi bit ECC error service routine detected during reset configuration. -* -* This function is called if Flash Multi bit ECC error detected during reset configuration. -*/ -void fmcClass1Error(void) -{ -/* USER CODE BEGIN (48) */ -/* USER CODE END */ - /* there was a multi-bit error detected during the reset configuration word read from the OTP */ - /* This affects the device power domains, endianness, and exception handling ISA */ - /* Device operation is not reliable. */ - /* for(;;) can be removed by adding "# if 0" and "# endif" in the user codes above and below */ -/* USER CODE BEGIN (49) */ -/* USER CODE END */ - for(;;) - { - }/* Wait */ -/* USER CODE BEGIN (50) */ -/* USER CODE END */ -} - -/** @fn void fmcClass2Error(void) -* @brief Flash OTP or EEPROM read Multi bit ECC error service routine -* -* This function is called if Flash OTP or EEPROM read Multi bit ECC error detected. -*/ -void fmcClass2Error(void) -{ -/* USER CODE BEGIN (51) */ -/* USER CODE END */ - /* The ECC logic inside FMC used to protect against 1-bit and 2-bit errors in OTP and EEPROM banks */ - /* is not operational. Device operation is not reliable. */ - /* for(;;) can be removed by adding "# if 0" and "# endif" in the user codes above and below */ -/* USER CODE BEGIN (52) */ -/* USER CODE END */ - for(;;) - { - }/* Wait */ -/* USER CODE BEGIN (53) */ -/* USER CODE END */ -} - -/** @fn void checkB0RAMECC(void) -* @brief Check TCRAM1 ECC error detection logic. -* -* This function checks TCRAM1 ECC error detection logic. -*/ -void checkB0RAMECC(void) -{ - volatile uint32 ramread = 0U; - volatile uint32 i; -/* USER CODE BEGIN (54) */ -/* USER CODE END */ - - /* enable writes to ECC RAM, enable ECC error response */ - tcram1REG->RAMCTRL = 0x0005010AU; - tcram2REG->RAMCTRL = 0x0005010AU; - - /* the first 1-bit error will cause an error response */ - tcram1REG->RAMTHRESHOLD = 0x1U; - tcram2REG->RAMTHRESHOLD = 0x1U; - - /* allow SERR to be reported to ESM */ - tcram1REG->RAMINTCTRL = 0x1U; - tcram2REG->RAMINTCTRL = 0x1U; - - /* cause a 1-bit ECC error */ - tcramA1bitError ^= 0x1U; - - /* disable writes to ECC RAM */ - tcram1REG->RAMCTRL = 0x0005000AU; - tcram2REG->RAMCTRL = 0x0005000AU; - - /* read from location with 1-bit ECC error */ - ramread = tcramA1bit; - - /* SERR not set in TCRAM1 or TCRAM2 modules */ - if ((!(((tcram1REG->RAMERRSTATUS & 1U) == 1U) || ((tcram2REG->RAMERRSTATUS & 1U) == 1U))) !=0U) - { - /* TCRAM module does not reflect 1-bit error reported by CPU */ - tcramClass2Error(); - } - else - { - /* clear SERR flag */ - tcram1REG->RAMERRSTATUS = 0x1U; - tcram2REG->RAMERRSTATUS = 0x1U; - - /* clear status flags for ESM group1 channels 26 and 28 */ - esmREG->ESTATUS1[0U] = 0x14000000U; - } - - /* enable writes to ECC RAM, enable ECC error response */ - tcram1REG->RAMCTRL = 0x0005010AU; - tcram2REG->RAMCTRL = 0x0005010AU; - - /* cause a 2-bit ECC error */ - tcramA2bitError ^= 0x3U; - ramread = tcram1REG->RAMCTRL; - ramread = tcram2REG->RAMCTRL; - - /* read from location with 2-bit ECC error this will cause a data abort to be generated */ - ramread = tcramA2bit; - - /* delay before restoring the ram value */ - for(i=0U;i<10U;i++) - { - }/* Wait */ - - /* disable RAM ECC Support */ - _coreDisableRamEcc_(); - - /* enable writes to ECC RAM, enable ECC error response */ - tcram1REG->RAMCTRL = 0x0005010AU; - tcram2REG->RAMCTRL = 0x0005010AU; - - /* revert back the flipped bits */ - tcramA1bitError ^= 0x1U; - tcramA2bitError ^= 0x3U; - - /* disable writes to ECC RAM */ - tcram1REG->RAMCTRL = 0x0005000AU; - tcram2REG->RAMCTRL = 0x0005000AU; - - /* enable RAM ECC Support */ - _coreEnableRamEcc_(); - -/* USER CODE BEGIN (55) */ -/* USER CODE END */ -} - -/** @fn void checkB1RAMECC(void) -* @brief Check TCRAM2 ECC error detection logic. -* -* This function checks TCRAM2 ECC error detection logic. -*/ -void checkB1RAMECC(void) -{ - volatile uint32 ramread = 0U; - volatile uint32 i; -/* USER CODE BEGIN (56) */ -/* USER CODE END */ - - /* enable writes to ECC RAM, enable ECC error response */ - tcram1REG->RAMCTRL = 0x0005010AU; - tcram2REG->RAMCTRL = 0x0005010AU; - - /* the first 1-bit error will cause an error response */ - tcram1REG->RAMTHRESHOLD = 0x1U; - tcram2REG->RAMTHRESHOLD = 0x1U; - - /* allow SERR to be reported to ESM */ - tcram1REG->RAMINTCTRL = 0x1U; - tcram2REG->RAMINTCTRL = 0x1U; - - /* cause a 1-bit ECC error */ - tcramB1bitError ^= 0x1U; - - /* disable writes to ECC RAM */ - tcram1REG->RAMCTRL = 0x0005000AU; - tcram2REG->RAMCTRL = 0x0005000AU; - - /* read from location with 1-bit ECC error */ - ramread = tcramB1bit; - - /* SERR not set in TCRAM1 or TCRAM2 modules */ - if ((!(((tcram1REG->RAMERRSTATUS & 1U) == 1U) || ((tcram2REG->RAMERRSTATUS & 1U) == 1U))) !=0U) - { - /* TCRAM module does not reflect 1-bit error reported by CPU */ - tcramClass2Error(); - } - else - { - /* clear SERR flag */ - tcram1REG->RAMERRSTATUS = 0x1U; - tcram2REG->RAMERRSTATUS = 0x1U; - - /* clear status flags for ESM group1 channels 26 and 28 */ - esmREG->ESTATUS1[0U] = 0x14000000U; - } - - /* enable writes to ECC RAM, enable ECC error response */ - tcram1REG->RAMCTRL = 0x0005010AU; - tcram2REG->RAMCTRL = 0x0005010AU; - - /* cause a 2-bit ECC error */ - tcramB2bitError ^= 0x3U; - - /* disable writes to ECC RAM */ - tcram1REG->RAMCTRL = 0x0005000AU; - tcram2REG->RAMCTRL = 0x0005000AU; - - /* delay before restoring the ram value */ - for(i=0U;i<10U;i++) - { - }/* Wait */ - - /* disable RAM ECC Support */ - _coreDisableRamEcc_(); - - /* enable writes to ECC RAM, enable ECC error response */ - tcram1REG->RAMCTRL = 0x0005010AU; - tcram2REG->RAMCTRL = 0x0005010AU; - - /* revert back the flipped bits */ - tcramB1bitError ^= 0x1U; - tcramB2bitError ^= 0x3U; - - /* disable writes to ECC RAM */ - tcram1REG->RAMCTRL = 0x0005000AU; - tcram2REG->RAMCTRL = 0x0005000AU; - - /* enable RAM ECC Support */ - _coreEnableRamEcc_(); - -/* USER CODE BEGIN (57) */ -/* USER CODE END */ -} - -/** @fn void tcramClass1Error(void) -* @brief Error service routine called if TCRAM module cannot capture 2-bit error. -* -* Error service routine called if TCRAM module cannot respond to 2-bit error. -*/ -void tcramClass1Error(void) -{ -/* USER CODE BEGIN (58) */ -/* USER CODE END */ - /* TCRAM module is not capable of responding to 2-bit error indicated by CPU. - * Device operation is not reliable and not recommended. - */ - /* for(;;) can be removed by adding "# if 0" and "# endif" in the user codes above and below */ -/* USER CODE BEGIN (59) */ -/* USER CODE END */ - for(;;) - { - }/* Wait */ -/* USER CODE BEGIN (60) */ -/* USER CODE END */ -} - -/** @fn void tcramClass2Error(void) -* @brief Error service routine called if TCRAM module cannot capture 1-bit error. -* -* Error service routine called if TCRAM module cannot respond to 1-bit error. -*/ -void tcramClass2Error(void) -{ -/* USER CODE BEGIN (61) */ -/* USER CODE END */ - /* TCRAM module is not capable of responding to 1-bit error indicated by CPU. - * Device operation is possible, but is prone to future multi-bit errors not being detected. - * Need custom handler here instead of the infinite loop. - */ - /* for(;;) can be removed by adding "# if 0" and "# endif" in the user codes above and below */ - -/* USER CODE BEGIN (62) */ -/* USER CODE END */ - for(;;) - { - }/* Wait */ -/* USER CODE BEGIN (63) */ -/* USER CODE END */ -} - -/** @fn void checkFlashECC(void) -* @brief Check Flash ECC error detection logic. -* -* This function checks Flash ECC error detection logic. -*/ -void checkFlashECC(void) -{ - /* Routine to check operation of ECC logic inside CPU for accesses to program flash */ - volatile uint32 flashread = 0U; - -/* USER CODE BEGIN (64) */ -/* USER CODE END */ - - /* Flash Module ECC Response enabled */ - flashWREG->FEDACCTRL1 = 0x000A060AU; - - /* Enable diagnostic mode and select diag mode 7 */ - flashWREG->FDIAGCTRL = 0x00050007U; - - /* Select ECC diagnostic mode, single-bit to be corrupted */ - flashWREG->FPAROVR = 0x00005A01U; - - /* Set the trigger for the diagnostic mode */ - flashWREG->FDIAGCTRL |= 0x01000000U; - - /* read a flash location from the mirrored memory map */ - flashread = flashBadECC; - - /* disable diagnostic mode */ - flashWREG->FDIAGCTRL = 0x000A0007U; - - /* this will have caused a single-bit error to be generated and corrected by CPU */ - /* single-bit error not captured in flash module */ - if ((!(flashWREG->FEDACSTATUS & 0x2U)) !=0U) - { - flashClass2Error(); - } - else - { - /* clear single-bit error flag */ - flashWREG->FEDACSTATUS = 0x2U; - - /* clear ESM flag */ - esmREG->ESTATUS1[0U] = 0x40U; - - /* Enable diagnostic mode and select diag mode 7 */ - flashWREG->FDIAGCTRL = 0x00050007U; - - /* Select ECC diagnostic mode, two bits of ECC to be corrupted */ - flashWREG->FPAROVR = 0x00005A03U; - - /* Set the trigger for the diagnostic mode */ - flashWREG->FDIAGCTRL |= 0x01000000U; - - /* read from flash location from mirrored memory map this will cause a data abort */ - flashread = flashBadECC; - - /* disable diagnostic mode */ - flashWREG->FDIAGCTRL = 0x000A0007U; - } - -/* USER CODE BEGIN (65) */ -/* USER CODE END */ -} - -/** @fn void flashClass1Error(void) -* @brief Error service routine called if Flash module cannot capture 2-bit error. -* -* Error service routine called if Flash module cannot capture 2-bit error. -*/ -void flashClass1Error(void) -{ -/* USER CODE BEGIN (66) */ -/* USER CODE END */ - /* Flash module not able to capture 2-bit error from CPU. - * Device operation not reliable. - */ - /* for(;;) can be removed by adding "# if 0" and "# endif" in the user codes above and below */ -/* USER CODE BEGIN (67) */ -/* USER CODE END */ - for(;;) - { - }/* Wait */ -/* USER CODE BEGIN (68) */ -/* USER CODE END */ - -} - -/** @fn void flashClass2Error(void) -* @brief Error service routine called if Flash module cannot capture 1-bit error. -* -* Error service routine called if Flash module cannot capture 1-bit error. -*/ -void flashClass2Error(void) -{ - /* Flash module not able to capture 1-bit error from CPU. - * Device operation possible if this weakness in diagnostic is okay. - */ -/* USER CODE BEGIN (69) */ -/* USER CODE END */ -} - -/** @fn void custom_dabort(void) -* @brief Custom Data abort routine for the application. -* -* Custom Data abort routine for the application. -*/ -void custom_dabort(void) -{ - /* Need custom data abort handler here. - * This data abort is not caused due to diagnostic checks of flash and TCRAM ECC logic. - */ -/* USER CODE BEGIN (70) */ -/* USER CODE END */ -} - -/** @fn void stcSelfCheckFail(void) -* @brief STC Self test check fail service routine -* -* This function is called if STC Self test check fail. -*/ -void stcSelfCheckFail(void) -{ -/* USER CODE BEGIN (71) */ -/* USER CODE END */ - /* CPU self-test controller's own self-test failed. - * It is not possible to verify that STC is capable of indicating a CPU self-test error. - * It is not recommended to continue operation. - */ - - /* User can add small piece of code to take system to Safe state using user code section. - * Note: Just removing the for(;;) will take the system to unknown state under ST failure, - * since it is not handled by HALCogen driver */ -/* USER CODE BEGIN (72) */ -/* USER CODE END */ - for(;;) - { - }/* Wait */ -/* USER CODE BEGIN (73) */ -/* USER CODE END */ -} - -/** @fn void cpuSelfTestFail(void) -* @brief CPU Self test check fail service routine -* -* This function is called if CPU Self test check fail. -*/ -void cpuSelfTestFail(void) -{ -/* USER CODE BEGIN (74) */ -/* USER CODE END */ - /* CPU self-test has failed. - * CPU operation is not reliable. - */ - /* for(;;) can be removed by adding "# if 0" and "# endif" in the user codes above and below */ -/* USER CODE BEGIN (75) */ -/* USER CODE END */ - for(;;) - { - }/* Wait */ -/* USER CODE BEGIN (76) */ -/* USER CODE END */ -} - - -/** @fn void vimParityCheck(void) -* @brief Routine to check VIM RAM parity error detection and signaling mechanism -* -* Routine to check VIM RAM parity error detection and signaling mechanism -*/ -void vimParityCheck(void) -{ - volatile uint32 vimramread = 0U; - -/* USER CODE BEGIN (77) */ -/* USER CODE END */ - - /* Enable parity checking and parity test mode */ - VIM_PARCTL = 0x0000010AU; - - /* flip a bit in the VIM RAM parity location */ - VIMRAMPARLOC ^= 0x1U; - - /* disable parity test mode */ - VIM_PARCTL = 0x0000000AU; - - /* cause parity error */ - vimramread = VIMRAMLOC; - - /* check if ESM group1 channel 15 is flagged */ - if ((!(esmREG->ESTATUS1[0U] & 0x8000U)) !=0U) - { - /* VIM RAM parity error was not flagged to ESM. */ - /* Need custom routine to handle this failure instead of the infinite loop. */ - /* for(;;) can be removed by adding "# if 0" and "# endif" in the user codes above and below */ -/* USER CODE BEGIN (78) */ -/* USER CODE END */ - for(;;) - { - }/* Wait */ -/* USER CODE BEGIN (79) */ -/* USER CODE END */ - - } - else - { - /* clear VIM RAM parity error flag in VIM */ - VIM_PARFLG = 0x1U; - - /* clear ESM group1 channel 15 flag */ - esmREG->ESTATUS1[0U] = 0x8000U; - - /* Enable parity checking and parity test mode */ - VIM_PARCTL = 0x0000010AU; - - /* Revert back to correct data, flip bit 0 of the parity location */ - VIMRAMPARLOC ^= 0x1U; - - /* disable parity test mode */ - VIM_PARCTL = 0x0000000AU; - } -/* USER CODE BEGIN (80) */ -/* USER CODE END */ -} - -/** @fn void dmaParityCheck(void) -* @brief Routine to check DMA control packet RAM parity error detection and signaling mechanism -* -* Routine to check DMA control packet RAM parity error detection and signaling mechanism -*/ -void dmaParityCheck(void) -{ - volatile uint32 dmaread = 0U; - -/* USER CODE BEGIN (81) */ -/* USER CODE END */ - - /* Enable parity checking and parity test mode */ - DMA_PARCR = 0x0000010AU; - - /* Flip a bit in DMA RAM parity location */ - DMARAMPARLOC ^= 0x1U; - - /* Disable parity test mode */ - DMA_PARCR = 0x0000000AU; - - /* Cause parity error */ - dmaread = DMARAMLOC; - - /* Check if ESM group1 channel 3 is flagged */ - if ((!(esmREG->ESTATUS1[0U] & 0x8U)) != 0U) - { - /* DMA RAM parity error was not flagged to ESM. */ - /* Need custom routine to handle this failure instead of the infinite loop. */ - /* for(;;) can be removed by adding "# if 0" and "# endif" in the user codes above and below */ -/* USER CODE BEGIN (82) */ -/* USER CODE END */ - for(;;) - { - }/* Wait */ -/* USER CODE BEGIN (83) */ -/* USER CODE END */ - } - else - { - /* clear DMA parity error flag in DMA */ - DMA_PARADDR = 0x01000000U; - - /* clear ESM group1 channel 3 flag */ - esmREG->ESTATUS1[0U] = 0x8U; - - /* Enable parity checking and parity test mode */ - DMA_PARCR = 0x0000010AU; - - /* Revert back to correct data, flip bit 0 of the parity location */ - DMARAMPARLOC ^= 0x1U; - - /* Disable parity test mode */ - DMA_PARCR = 0x0000000AU; - } -/* USER CODE BEGIN (84) */ -/* USER CODE END */ -} - -/** @fn void het1ParityCheck(void) -* @brief Routine to check HET1 RAM parity error detection and signaling mechanism -* -* Routine to check HET1 RAM parity error detection and signaling mechanism -*/ -void het1ParityCheck(void) -{ - volatile uint32 nhetread = 0U; - -/* USER CODE BEGIN (85) */ -/* USER CODE END */ - - /* Set TEST mode and enable parity checking */ - hetREG1->PCR = 0x0000010AU; - - /* flip parity bit */ - NHET1RAMPARLOC ^= 0x1U; - - /* Disable TEST mode */ - hetREG1->PCR = 0x0000000AU; - - /* read to cause parity error */ - nhetread = NHET1RAMLOC; - - /* check if ESM group1 channel 7 is flagged */ - if ((!(esmREG->ESTATUS1[0U] & 0x80U)) !=0U) - { - /* NHET1 RAM parity error was not flagged to ESM. */ - /* Need custom routine to handle this failure instead of the infinite loop. */ - /* for(;;) can be removed by adding "# if 0" and "# endif" in the user codes above and below */ -/* USER CODE BEGIN (86) */ -/* USER CODE END */ - for(;;) - { - }/* Wait */ -/* USER CODE BEGIN (87) */ -/* USER CODE END */ - } - else - { - /* clear ESM group1 channel 7 flag */ - esmREG->ESTATUS1[0U] = 0x80U; - - /* Set TEST mode and enable parity checking */ - hetREG1->PCR = 0x0000010AU; - - /* Revert back to correct data, flip bit 0 of the parity location */ - NHET1RAMPARLOC ^= 0x1U; - - /* Disable TEST mode */ - hetREG1->PCR = 0x0000000AU; - } -/* USER CODE BEGIN (88) */ -/* USER CODE END */ -} - -/** @fn void htu1ParityCheck(void) -* @brief Routine to check HTU1 RAM parity error detection and signaling mechanism -* -* Routine to check HTU1 RAM parity error detection and signaling mechanism -*/ -void htu1ParityCheck(void) -{ - volatile uint32 hturead = 0U; - -/* USER CODE BEGIN (89) */ -/* USER CODE END */ - - /* Enable parity and TEST mode */ - htuREG1->PCR = 0x0000010AU; - - /* flip parity bit */ - HTU1PARLOC ^= 0x1U; - - /* Disable parity RAM test mode */ - htuREG1->PCR = 0x0000000AU; - - /* read to cause parity error */ - hturead = HTU1RAMLOC; - - /* check if ESM group1 channel 8 is flagged */ - if ((!(esmREG->ESTATUS1[0U] & 0x100U)) != 0U) - { - /* HTU1 RAM parity error was not flagged to ESM. */ - /* Need custom routine to handle this failure instead of the infinite loop. */ - /* for(;;) can be removed by adding "# if 0" and "# endif" in the user codes above and below */ -/* USER CODE BEGIN (90) */ -/* USER CODE END */ - for(;;) - { - }/* Wait */ -/* USER CODE BEGIN (91) */ -/* USER CODE END */ - } - else - { - /* Clear HTU parity error flag */ - htuREG1->PAR = 0x00010000U; - esmREG->ESTATUS1[0U] = 0x100U; - - /* Enable parity and TEST mode */ - htuREG1->PCR = 0x0000010AU; - - /* Revert back to correct data, flip bit 0 of the parity location */ - HTU1PARLOC ^= 0x1U; - - /* Disable parity RAM test mode */ - htuREG1->PCR = 0x0000000AU; - - } - -/* USER CODE BEGIN (92) */ -/* USER CODE END */ - -} - -/** @fn void het2ParityCheck(void) -* @brief Routine to check HET2 RAM parity error detection and signaling mechanism -* -* Routine to check HET2 RAM parity error detection and signaling mechanism -*/ -void het2ParityCheck(void) -{ - volatile uint32 nhetread = 0U; - -/* USER CODE BEGIN (93) */ -/* USER CODE END */ - - /* Set TEST mode and enable parity checking */ - hetREG2->PCR = 0x0000010AU; - - /* flip parity bit */ - NHET2RAMPARLOC ^= 0x1U; - - /* Disable TEST mode */ - hetREG2->PCR = 0x0000000AU; - - /* read to cause parity error */ - nhetread = NHET2RAMLOC; - - /* check if ESM group1 channel 7 or 34 is flagged */ - if ((!(esmREG->ESTATUS1[0U] & 0x80U) != 0U) && (!(esmREG->ESTATUS4[0U] & 0x4U) !=0U)) - { - /* NHET2 RAM parity error was not flagged to ESM. */ - /* Need custom routine to handle this failure instead of the infinite loop. */ - /* for(;;) can be removed by adding "# if 0" and "# endif" in the user codes above and below */ -/* USER CODE BEGIN (94) */ -/* USER CODE END */ - for(;;) - { - }/* Wait */ -/* USER CODE BEGIN (95) */ -/* USER CODE END */ - } - else - { - /* clear ESM group1 channel 7 flag */ - esmREG->ESTATUS1[0U] = 0x80U; - - /* clear ESM group1 channel 34 flag */ - esmREG->ESTATUS4[0U] = 0x4U; - - /* Set TEST mode and enable parity checking */ - hetREG2->PCR = 0x0000010AU; - - /* Revert back to correct data, flip bit 0 of the parity location */ - NHET2RAMPARLOC ^= 0x1U; - - /* Disable TEST mode */ - hetREG2->PCR = 0x0000000AU; - } - -/* USER CODE BEGIN (96) */ -/* USER CODE END */ -} - -/** @fn void htu2ParityCheck(void) -* @brief Routine to check HTU2 RAM parity error detection and signaling mechanism -* -* Routine to check HTU2 RAM parity error detection and signaling mechanism -*/ -void htu2ParityCheck(void) -{ - volatile uint32 hturead = 0U; - -/* USER CODE BEGIN (97) */ -/* USER CODE END */ - - /* Enable parity and TEST mode */ - htuREG2->PCR = 0x0000010AU; - - /* flip parity bit */ - HTU2PARLOC ^= 0x1U; - - /* Disable parity RAM test mode */ - htuREG2->PCR = 0x0000000AU; - - /* read to cause parity error */ - hturead = HTU2RAMLOC; - - /* check if ESM group1 channel 8 is flagged */ - if ((!(esmREG->ESTATUS1[0U] & 0x100U)) != 0U) - { - /* HTU2 RAM parity error was not flagged to ESM. */ - /* Need custom routine to handle this failure instead of the infinite loop. */ - /* for(;;) can be removed by adding "# if 0" and "# endif" in the user codes above and below */ -/* USER CODE BEGIN (98) */ -/* USER CODE END */ - for(;;) - { - }/* Wait */ -/* USER CODE BEGIN (99) */ -/* USER CODE END */ - } - else - { - /* Clear HTU parity error flag */ - htuREG2->PAR = 0x00010000U; - esmREG->ESTATUS1[0U] = 0x100U; - - /* Enable parity and TEST mode */ - htuREG2->PCR = 0x0000010AU; - - /* Revert back to correct data, flip bit 0 of the parity location */ - HTU2PARLOC ^= 0x1U; - - /* Disable parity RAM test mode */ - htuREG2->PCR = 0x0000000AU; - } - -/* USER CODE BEGIN (100) */ -/* USER CODE END */ -} - -/** @fn void adc1ParityCheck(void) -* @brief Routine to check ADC1 RAM parity error detection and signaling mechanism -* -* Routine to check ADC1 RAM parity error detection and signaling mechanism -*/ -void adc1ParityCheck(void) -{ - volatile uint32 adcramread = 0U; - -/* USER CODE BEGIN (101) */ -/* USER CODE END */ - - /* Set the TEST bit in the PARCR and enable parity checking */ - adcREG1->PARCR = 0x10AU; - - /* Invert the parity bits inside the ADC1 RAM's first location */ - adcPARRAM1 = ~(adcPARRAM1); - - /* clear the TEST bit */ - adcREG1->PARCR = 0x00AU; - - /* This read is expected to trigger a parity error */ - adcramread = adcRAM1; - - /* Check for ESM group1 channel 19 to be flagged */ - if ((!(esmREG->ESTATUS1[0U] & 0x80000U)) !=0U) - { - /* no ADC1 RAM parity error was flagged to ESM */ - /* Need custom routine to handle this failure instead of the infinite loop */ - /* for(;;) can be removed by adding "# if 0" and "# endif" in the user codes above and below */ -/* USER CODE BEGIN (102) */ -/* USER CODE END */ - for(;;) - { - }/* Wait */ -/* USER CODE BEGIN (103) */ -/* USER CODE END */ - } - else - { - /* clear ADC1 RAM parity error flag */ - esmREG->ESTATUS1[0U] = 0x80000U; - - /* Set the TEST bit in the PARCR and enable parity checking */ - adcREG1->PARCR = 0x10AU; - - /* Revert back the parity bits to correct data */ - adcPARRAM1 = ~(adcPARRAM1); - - /* clear the TEST bit */ - adcREG1->PARCR = 0x00AU; - } - -/* USER CODE BEGIN (104) */ -/* USER CODE END */ -} - -/** @fn void adc2ParityCheck(void) -* @brief Routine to check ADC2 RAM parity error detection and signaling mechanism -* -* Routine to check ADC2 RAM parity error detection and signaling mechanism -*/ -void adc2ParityCheck(void) -{ - volatile uint32 adcramread = 0U; - -/* USER CODE BEGIN (105) */ -/* USER CODE END */ - - /* Set the TEST bit in the PARCR and enable parity checking */ - adcREG2->PARCR = 0x10AU; - - /* Invert the parity bits inside the ADC2 RAM's first location */ - adcPARRAM2 = ~(adcPARRAM2); - - /* clear the TEST bit */ - adcREG2->PARCR = 0x00AU; - - /* This read is expected to trigger a parity error */ - adcramread = adcRAM2; - - /* Check for ESM group1 channel 1 to be flagged */ - if ((!(esmREG->ESTATUS1[0U] & 0x2U)) != 0U) - { - /* no ADC2 RAM parity error was flagged to ESM */ - /* Need custom routine to handle this failure instead of the infinite loop */ - /* for(;;) can be removed by adding "# if 0" and "# endif" in the user codes above and below */ -/* USER CODE BEGIN (106) */ -/* USER CODE END */ - for(;;) - { - }/* Wait */ -/* USER CODE BEGIN (107) */ -/* USER CODE END */ - } - else - { - /* clear ADC2 RAM parity error flag */ - esmREG->ESTATUS1[0U] = 0x2U; - - /* Set the TEST bit in the PARCR and enable parity checking */ - adcREG2->PARCR = 0x10AU; - - /* Revert back the parity bits to correct data */ - adcPARRAM2 = ~(adcPARRAM2); - - /* clear the TEST bit */ - adcREG2->PARCR = 0x00AU; - } - -/* USER CODE BEGIN (108) */ -/* USER CODE END */ -} - -/** @fn void can1ParityCheck(void) -* @brief Routine to check CAN1 RAM parity error detection and signaling mechanism -* -* Routine to check CAN1 RAM parity error detection and signaling mechanism -*/ -void can1ParityCheck(void) -{ - volatile uint32 canread = 0U; - -/* USER CODE BEGIN (109) */ -/* USER CODE END */ - - /* Disable parity, init mode, TEST mode */ - canREG1->CTL = 0x00001481U; - - /* Enable RAM Direct Access mode */ - canREG1->TEST = 0x00000200U; - - /* flip the parity bit */ - canPARRAM1 ^= 0x00001000U; - - /* Enable parity, disable init, still TEST mode */ - canREG1->CTL = 0x00002880U; - - /* Read location with parity error */ - canread = canRAM1; - - /* check if ESM group1 channel 21 is flagged */ - if ((!(esmREG->ESTATUS1[0U] & 0x00200000U)) != 0U) - { - /* No DCAN1 RAM parity error was flagged to ESM */ - /* Need custom routine to handle this failure instead of the infinite loop */ - /* for(;;) can be removed by adding "# if 0" and "# endif" in the user codes above and below */ -/* USER CODE BEGIN (110) */ -/* USER CODE END */ - for(;;) - { - }/* Wait */ -/* USER CODE BEGIN (111) */ -/* USER CODE END */ - } - else - { - /* clear ESM group1 channel 21 flag */ - esmREG->ESTATUS1[0U] = 0x00200000U; - - /* Disable parity, init mode, TEST mode */ - canREG1->CTL = 0x00001481U; - - /* Enable RAM Direct Access mode */ - canREG1->TEST = 0x00000200U; - - /* Revert back to correct data, flip bit 0 of the parity location */ - canPARRAM1 ^= 0x00001000U; - - /* disable TEST mode */ - canREG1->CTL = 0x00002800U; - } - -/* USER CODE BEGIN (112) */ -/* USER CODE END */ -} - -/** @fn void can2ParityCheck(void) -* @brief Routine to check CAN2 RAM parity error detection and signaling mechanism -* -* Routine to check CAN2 RAM parity error detection and signaling mechanism -*/ -void can2ParityCheck(void) -{ - volatile uint32 canread = 0U; - -/* USER CODE BEGIN (113) */ -/* USER CODE END */ - - /* Disable parity, init mode, TEST mode */ - canREG2->CTL = 0x00001481U; - - /* Enable RAM Direct Access mode */ - canREG2->TEST = 0x00000200U; - - /* flip the parity bit */ - canPARRAM2 ^= 0x00001000U; - - /* Enable parity, disable init, still TEST mode */ - canREG2->CTL = 0x00002880U; - - /* Read location with parity error */ - canread = canRAM2; - - /* check if ESM group1 channel 23 is flagged */ - if ((!(esmREG->ESTATUS1[0U] & 0x00800000U)) != 0U) - { - /* No DCAN2 RAM parity error was flagged to ESM */ - /* Need custom routine to handle this failure instead of the infinite loop */ - /* for(;;) can be removed by adding "# if 0" and "# endif" in the user codes above and below */ -/* USER CODE BEGIN (114) */ -/* USER CODE END */ - for(;;) - { - }/* Wait */ -/* USER CODE BEGIN (115) */ -/* USER CODE END */ - } - else - { - /* clear ESM group1 channel 23 flag */ - esmREG->ESTATUS1[0U] = 0x00800000U; - - /* Disable parity, init mode, TEST mode */ - canREG2->CTL = 0x00001481U; - - /* Enable RAM Direct Access mode */ - canREG2->TEST = 0x00000200U; - - /* Revert back to correct data, flip bit 0 of the parity location */ - canPARRAM2 ^= 0x00001000U; - - /* disable TEST mode */ - canREG2->CTL = 0x00002800U; - } - -/* USER CODE BEGIN (116) */ -/* USER CODE END */ -} - -/** @fn void can3ParityCheck(void) -* @brief Routine to check CAN3 RAM parity error detection and signaling mechanism -* -* Routine to check CAN3 RAM parity error detection and signaling mechanism -*/ -void can3ParityCheck(void) -{ - volatile uint32 canread = 0U; - -/* USER CODE BEGIN (117) */ -/* USER CODE END */ - - /* Disable parity, init mode, TEST mode */ - canREG3->CTL = 0x00001481U; - - /* Enable RAM Direct Access mode */ - canREG3->TEST = 0x00000200U; - - /* flip the parity bit */ - canPARRAM3 ^= 0x00001000U; - - /* Enable parity, disable init, still TEST mode */ - canREG3->CTL = 0x00002880U; - - /* Read location with parity error */ - canread = canRAM3; - - /* check if ESM group1 channel 22 is flagged */ - if ((!(esmREG->ESTATUS1[0U] & 0x00400000U)) != 0U) - { - /* No DCAN3 RAM parity error was flagged to ESM */ - /* Need custom routine to handle this failure instead of the infinite loop */ - /* for(;;) can be removed by adding "# if 0" and "# endif" in the user codes above and below */ -/* USER CODE BEGIN (118) */ -/* USER CODE END */ - for(;;) - { - }/* Wait */ -/* USER CODE BEGIN (119) */ -/* USER CODE END */ - } - else - { - /* clear ESM group1 channel 22 flag */ - esmREG->ESTATUS1[0U] = 0x00400000U; - - /* Disable parity, init mode, TEST mode */ - canREG3->CTL = 0x00001481U; - - /* Enable RAM Direct Access mode */ - canREG3->TEST = 0x00000200U; - - /* Revert back to correct data, flip bit 0 of the parity location */ - canPARRAM3 ^= 0x00001000U; - - /* disable TEST mode */ - canREG3->CTL = 0x00002800U; - } - -/* USER CODE BEGIN (120) */ -/* USER CODE END */ -} - -/** @fn void mibspi1ParityCheck(void) -* @brief Routine to check MIBSPI1 RAM parity error detection and signaling mechanism -* -* Routine to check MIBSPI1 RAM parity error detection and signaling mechanism -*/ -void mibspi1ParityCheck(void) -{ - volatile uint32 spiread = 0U; - -/* USER CODE BEGIN (121) */ -/* USER CODE END */ - - /* enable multi-buffered mode */ - mibspiREG1->MIBSPIE = 0x1U; - - /* enable parity error detection */ - mibspiREG1->UERRCTRL = (mibspiREG1->UERRCTRL & 0xFFFFFFF0U) | (0xAU); - - /* enable parity test mode */ - mibspiREG1->UERRCTRL |= 1U << 8U; - - /* flip bit 0 of the parity location */ - mibspiPARRAM1 ^= 0x1U; - - /* disable parity test mode */ - mibspiREG1->UERRCTRL &= ~(1U << 8U); - - /* read from MibSPI1 RAM to cause parity error */ - spiread = *(uint32 *) mibspiRAM1; - - /* check if ESM group1 channel 17 is flagged */ - if ((!(esmREG->ESTATUS1[0U] & 0x20000U)) != 0U) - { - /* No MibSPI1 RAM parity error was flagged to ESM. */ - /* Need custom routine to handle this failure instead of the infinite loop */ - /* for(;;) can be removed by adding "# if 0" and "# endif" in the user codes above and below */ -/* USER CODE BEGIN (122) */ -/* USER CODE END */ - for(;;) - { - }/* Wait */ -/* USER CODE BEGIN (123) */ -/* USER CODE END */ - } - else - { - /* clear parity error flags */ - mibspiREG1->UERRSTAT = 0x3U; - - /* clear ESM group1 channel 17 flag */ - esmREG->ESTATUS1[0U] = 0x20000U; - - /* enable parity test mode */ - mibspiREG1->UERRCTRL |= 1U << 8U; - - /* Revert back to correct data, flip bit 0 of the parity location */ - mibspiPARRAM1 ^= 0x1U; - - /* disable parity test mode */ - mibspiREG1->UERRCTRL &= ~(1U << 8U); - - /* revert multi-buffered mode */ - mibspiREG1->MIBSPIE = 0x0U; - } - -/* USER CODE BEGIN (124) */ -/* USER CODE END */ -} - -/** @fn void mibspi3ParityCheck(void) -* @brief Routine to check MIBSPI3 RAM parity error detection and signaling mechanism -* -* Routine to check MIBSPI3 RAM parity error detection and signaling mechanism -*/ -void mibspi3ParityCheck(void) -{ - volatile uint32 spiread = 0U; - -/* USER CODE BEGIN (125) */ -/* USER CODE END */ - - /* enable multi-buffered mode */ - mibspiREG3->MIBSPIE = 0x1U; - - /* enable parity test mode */ - mibspiREG3->UERRCTRL |= 1U << 8U; - - /* flip bit 0 of the parity location */ - mibspiPARRAM3 ^= 0x1U; - - /* enable parity error detection */ - mibspiREG3->UERRCTRL = (mibspiREG3->UERRCTRL & 0xFFFFFFF0U) | (0xAU); - - /* disable parity test mode */ - mibspiREG3->UERRCTRL &= ~(1U << 8U); - - /* read from MibSPI3 RAM to cause parity error */ - spiread = *(uint32 *) mibspiRAM3; - - /* check if ESM group1 channel 18 is flagged */ - if ((!(esmREG->ESTATUS1[0U] & 0x40000U)) != 0U) - { - /* No MibSPI3 RAM parity error was flagged to ESM. */ - /* Need custom routine to handle this failure instead of the infinite loop */ - /* for(;;) can be removed by adding "# if 0" and "# endif" in the user codes above and below */ -/* USER CODE BEGIN (126) */ -/* USER CODE END */ - for(;;) - { - }/* Wait */ -/* USER CODE BEGIN (127) */ -/* USER CODE END */ - } - else - { - /* clear parity error flags */ - mibspiREG3->UERRSTAT = 0x3U; - - /* clear ESM group1 channel 18 flag */ - esmREG->ESTATUS1[0U] = 0x40000U; - - /* enable parity test mode */ - mibspiREG3->UERRCTRL |= 1U << 8U; - - /* Revert back to correct data, flip bit 0 of the parity location */ - mibspiPARRAM3 ^= 0x1U; - - /* disable parity test mode */ - mibspiREG3->UERRCTRL &= ~(1U << 8U); - - /* revert multi-buffered mode */ - mibspiREG3->MIBSPIE = 0x0U; - } - -/* USER CODE BEGIN (128) */ -/* USER CODE END */ -} - -/** @fn void mibspi5ParityCheck(void) -* @brief Routine to check MIBSPI5 RAM parity error detection and signaling mechanism -* -* Routine to check MIBSPI5 RAM parity error detection and signaling mechanism -*/ -void mibspi5ParityCheck(void) -{ - volatile uint32 spiread = 0U; - -/* USER CODE BEGIN (129) */ -/* USER CODE END */ - - /* enable multi-buffered mode */ - mibspiREG5->MIBSPIE = 0x1U; - - /* enable parity test mode */ - mibspiREG5->UERRCTRL |= 1U << 8U; - - /* flip bit 0 of the parity location */ - mibspiPARRAM5 ^= 0x1U; - - /* enable parity error detection */ - mibspiREG5->UERRCTRL = (mibspiREG5->UERRCTRL & 0xFFFFFFF0U) | (0xAU); - - /* disable parity test mode */ - mibspiREG5->UERRCTRL &= ~(1U << 8U); - - /* read from MibSPI5 RAM to cause parity error */ - spiread = *(uint32 *) mibspiRAM5; - - /* check if ESM group1 channel 24 is flagged */ - if ((!(esmREG->ESTATUS1[0U] & 0x01000000U)) != 0U) - { - /* No MibSPI5 RAM parity error was flagged to ESM. */ - /* Need custom routine to handle this failure instead of the infinite loop */ - /* for(;;) can be removed by adding "# if 0" and "# endif" in the user codes above and below */ -/* USER CODE BEGIN (130) */ -/* USER CODE END */ - for(;;) - { - }/* Wait */ -/* USER CODE BEGIN (131) */ -/* USER CODE END */ - } - else - { - /* clear parity error flags */ - mibspiREG5->UERRSTAT = 0x3U; - - /* clear ESM group1 channel 24 flag */ - esmREG->ESTATUS1[0U] = 0x01000000U; - - /* enable parity test mode */ - mibspiREG5->UERRCTRL |= 1U << 8U; - - /* Revert back to correct data, flip bit 0 of the parity location */ - mibspiPARRAM5 ^= 0x1U; - - /* disable parity test mode */ - mibspiREG5->UERRCTRL &= ~(1U << 8U); - - /* revert multi-buffered mode */ - mibspiREG5->MIBSPIE = 0x0U; - } - -/* USER CODE BEGIN (132) */ -/* USER CODE END */ -} - - -/** @fn void pbistGetConfigValue(pbist_config_reg_t *config_reg, config_value_type_t type) -* @brief Get the initial or current values of the configuration registers -* -* @param[in] *config_reg: pointer to the struct to which the initial or current value of the configuration registers need to be stored -* @param[in] type: whether initial or current value of the configuration registers need to be stored -* - InitialValue: initial value of the configuration registers will be stored in the struct pointed by config_reg -* - CurrentValue: initial value of the configuration registers will be stored in the struct pointed by config_reg -* -* This function will copy the initial or current value (depending on the parameter 'type') of the configuration registers to the struct pointed by config_reg -* -*/ - -void pbistGetConfigValue(pbist_config_reg_t *config_reg, config_value_type_t type) -{ - if (type == InitialValue) - { - config_reg->CONFIG_RAMT = PBIST_RAMT_CONFIGVALUE; - config_reg->CONFIG_DLR = PBIST_DLR_CONFIGVALUE; - config_reg->CONFIG_PACT = PBIST_PACT_CONFIGVALUE; - config_reg->CONFIG_PBISTID = PBIST_PBISTID_CONFIGVALUE; - config_reg->CONFIG_OVER = PBIST_OVER_CONFIGVALUE; - config_reg->CONFIG_FSRDL1 = PBIST_FSRDL1_CONFIGVALUE; - config_reg->CONFIG_ROM = PBIST_ROM_CONFIGVALUE; - config_reg->CONFIG_ALGO = PBIST_ALGO_CONFIGVALUE; - config_reg->CONFIG_RINFOL = PBIST_RINFOL_CONFIGVALUE; - config_reg->CONFIG_RINFOU = PBIST_RINFOU_CONFIGVALUE; - } - else - { - config_reg->CONFIG_RAMT = pbistREG->RAMT; - config_reg->CONFIG_DLR = pbistREG->DLR; - config_reg->CONFIG_PACT = pbistREG->PACT; - config_reg->CONFIG_PBISTID = pbistREG->PBISTID; - config_reg->CONFIG_OVER = pbistREG->OVER; - config_reg->CONFIG_FSRDL1 = pbistREG->FSRDL1; - config_reg->CONFIG_ROM = pbistREG->ROM; - config_reg->CONFIG_ALGO = pbistREG->ALGO; - config_reg->CONFIG_RINFOL = pbistREG->RINFOL; - config_reg->CONFIG_RINFOU = pbistREG->RINFOU; - } -} - -/** @fn void stcGetConfigValue(stc_config_reg_t *config_reg, config_value_type_t type) -* @brief Get the initial or current values of the configuration registers -* -* @param[in] *config_reg: pointer to the struct to which the initial or current value of the configuration registers need to be stored -* @param[in] type: whether initial or current value of the configuration registers need to be stored -* - InitialValue: initial value of the configuration registers will be stored in the struct pointed by config_reg -* - CurrentValue: initial value of the configuration registers will be stored in the struct pointed by config_reg -* -* This function will copy the initial or current value (depending on the parameter 'type') of the configuration registers to the struct pointed by config_reg -* -*/ - -void stcGetConfigValue(stc_config_reg_t *config_reg, config_value_type_t type) -{ - if (type == InitialValue) - { - config_reg->CONFIG_STCGCR0 = STC_STCGCR0_CONFIGVALUE; - config_reg->CONFIG_STCGCR1 = STC_STCGCR1_CONFIGVALUE; - config_reg->CONFIG_STCTPR = STC_STCTPR_CONFIGVALUE; - config_reg->CONFIG_STCSCSCR = STC_STCSCSCR_CONFIGVALUE; - } - else - { - config_reg->CONFIG_STCGCR0 = stcREG->STCGCR0; - config_reg->CONFIG_STCGCR1 = stcREG->STCGCR1; - config_reg->CONFIG_STCTPR = stcREG->STCTPR; - config_reg->CONFIG_STCSCSCR = stcREG->STCSCSCR; - } -} - - -/** @fn void efcGetConfigValue(efc_config_reg_t *config_reg, config_value_type_t type) -* @brief Get the initial or current values of the configuration registers -* -* @param[in] *config_reg: pointer to the struct to which the initial or current value of the configuration registers need to be stored -* @param[in] type: whether initial or current value of the configuration registers need to be stored -* - InitialValue: initial value of the configuration registers will be stored in the struct pointed by config_reg -* - CurrentValue: initial value of the configuration registers will be stored in the struct pointed by config_reg -* -* This function will copy the initial or current value (depending on the parameter 'type') of the configuration registers to the struct pointed by config_reg -* -*/ - -void efcGetConfigValue(efc_config_reg_t *config_reg, config_value_type_t type) -{ - if (type == InitialValue) - { - config_reg->CONFIG_BOUNDARY = EFC_BOUNDARY_CONFIGVALUE; - config_reg->CONFIG_PINS = EFC_PINS_CONFIGVALUE; - config_reg->CONFIG_SELFTESTCYCLES = EFC_SELFTESTCYCLES_CONFIGVALUE; - config_reg->CONFIG_SELFTESTSIGN = EFC_SELFTESTSIGN_CONFIGVALUE; - } - else - { - config_reg->CONFIG_BOUNDARY = efcREG->BOUNDARY; - config_reg->CONFIG_PINS = efcREG->PINS; - config_reg->CONFIG_SELFTESTCYCLES = efcREG->SELF_TEST_CYCLES; - config_reg->CONFIG_SELFTESTSIGN = efcREG->SELF_TEST_SIGN; - } -} - - -/** @fn void ccmr4GetConfigValue(ccmr4_config_reg_t *config_reg, config_value_type_t type) -* @brief Get the initial or current values of the configuration registers -* -* @param[in] *config_reg: pointer to the struct to which the initial or current value of the configuration registers need to be stored -* @param[in] type: whether initial or current value of the configuration registers need to be stored -* - InitialValue: initial value of the configuration registers will be stored in the struct pointed by config_reg -* - CurrentValue: initial value of the configuration registers will be stored in the struct pointed by config_reg -* -* This function will copy the initial or current value (depending on the parameter 'type') of the configuration registers to the struct pointed by config_reg -* -*/ - -void ccmr4GetConfigValue(ccmr4_config_reg_t *config_reg, config_value_type_t type) -{ - if (type == InitialValue) - { - config_reg->CONFIG_CCMKEYR = CCMR4_CCMKEYR_CONFIGVALUE; - } - else - { - config_reg->CONFIG_CCMKEYR = CCMKEYR; - } -} diff --git a/bsp/rm48x50/HALCoGen/source/sys_startup.c b/bsp/rm48x50/HALCoGen/source/sys_startup.c index 88af206463..0350e21e2b 100644 --- a/bsp/rm48x50/HALCoGen/source/sys_startup.c +++ b/bsp/rm48x50/HALCoGen/source/sys_startup.c @@ -1,4 +1,4 @@ -/** @file sys_startup.c +/** @file sys_startup.c * @brief Startup Source File * @date 29.May.2013 * @version 03.05.02 @@ -15,10 +15,6 @@ /* (c) Texas Instruments 2009-2013, All rights reserved. */ -/* USER CODE BEGIN (0) */ -/* USER CODE END */ - - /* Include Files */ #include "sys_common.h" @@ -29,22 +25,13 @@ #include "esm.h" #include "mibspi.h" -/* USER CODE BEGIN (1) */ -/* USER CODE END */ - - /* Type Definitions */ typedef void (*handler_fptr)(const uint8 * in, uint8 * out); -/* USER CODE BEGIN (2) */ -/* USER CODE END */ - - /* External Functions */ /*SAFETYMCUSW 94 S MR:11.1 <REVIEWED> "Startup code(handler pointers)" */ -/*SAFETYMCUSW 122 S MR:20.11 <REVIEWED> "Startup code(exit and abort need to be present)" */ /*SAFETYMCUSW 296 S MR:8.6 <REVIEWED> "Startup code(library functions at block scope)" */ /*SAFETYMCUSW 298 S MR: <REVIEWED> "Startup code(handler pointers)" */ /*SAFETYMCUSW 299 S MR: <REVIEWED> "Startup code(typedef for handler pointers in library )" */ @@ -69,40 +56,46 @@ extern uint32 __TI_PINIT_Limit; extern uint32 * __binit__; extern void main(void); -extern void exit(void); - -extern void muxInit(void); /* USER CODE BEGIN (3) */ /* USER CODE END */ /* Startup Routine */ -/* USER CODE BEGIN (4) */ +/** @fn void memoryInit(uint32 ram) +* @brief Memory Initialization Driver +* +* This function is called to perform Memory initialization of selected RAM's. +*/ +void memoryInit(uint32 ram) +{ +/* USER CODE BEGIN (11) */ /* USER CODE END */ -#pragma CODE_STATE(_c_int00, 32) -#pragma INTERRUPT(_c_int00, RESET) + /* Enable Memory Hardware Initialization */ + systemREG1->MINITGCR = 0xAU; -void _c_int00(void) -{ - -/* USER CODE BEGIN (5) */ -/* USER CODE END */ + /* Enable Memory Hardware Initialization for selected RAM's */ + systemREG1->MSINENA = ram; - /* Initialize Core Registers to avoid CCM Error */ - _coreInitRegisters_(); + /* Wait until Memory Hardware Initialization complete */ + while((systemREG1->MSTCGSTAT & 0x00000100U) != 0x00000100U) + { + }/* Wait */ -/* USER CODE BEGIN (6) */ -/* USER CODE END */ + /* Disable Memory Hardware Initialization */ + systemREG1->MINITGCR = 0x5U; - /* Initialize Stack Pointers */ - _coreInitStackPointer_(); +/* USER CODE BEGIN (12) */ +/* USER CODE END */ +} -/* USER CODE BEGIN (7) */ +/* USER CODE BEGIN (4) */ /* USER CODE END */ - /* Work Around for Errata DEVICE#140: ( Only on Rev A silicon) +void _c_int00(void) +{ + /* Work Around for Errata DEVICE#140: ( Only on Rev A silicon) * * Errata Description: * The Core Compare Module(CCM-R4) may cause nERROR to be asserted after a cold power-on @@ -112,29 +105,20 @@ void _c_int00(void) { _esmCcmErrorsClear_(); } - + /* USER CODE BEGIN (8) */ /* USER CODE END */ - - /* Enable CPU Event Export */ - /* This allows the CPU to signal any single-bit or double-bit errors detected - * by its ECC logic for accesses to program flash or data RAM. - */ - _coreEnableEventBusExport_(); - /* USER CODE BEGIN (11) */ /* USER CODE END */ /* Reset handler: the following instructions read from the system exception status register - * to identify the cause of the CPU reset. - */ - + * to identify the cause of the CPU reset. */ /* check for power-on reset condition */ if ((SYS_EXCEPTION & POWERON_RESET) != 0U) { /* USER CODE BEGIN (12) */ /* USER CODE END */ - + /* clear all reset status flags */ SYS_EXCEPTION = 0xFFFFU; @@ -142,12 +126,12 @@ void _c_int00(void) /* USER CODE END */ _errata_CORTEXR4_66_(); - + /* USER CODE BEGIN (14) */ /* USER CODE END */ _errata_CORTEXR4_57_(); - + /* USER CODE BEGIN (15) */ /* USER CODE END */ @@ -163,26 +147,26 @@ void _c_int00(void) } else if ((SYS_EXCEPTION & WATCHDOG_RESET) !=0U) { - /* Reset caused due + /* Reset caused due * 1) windowed watchdog violation - Add user code here to handle watchdog violation. * 2) ICEPICK Reset - After loading code via CCS / System Reset through CCS */ /* Check the WatchDog Status register */ if(WATCHDOG_STATUS != 0U) { - /* Add user code here to handle watchdog violation. */ + /* Add user code here to handle watchdog violation. */ /* USER CODE BEGIN (17) */ /* USER CODE END */ - /* Clear the Watchdog reset flag in Exception Status register */ + /* Clear the Watchdog reset flag in Exception Status register */ SYS_EXCEPTION = WATCHDOG_RESET; - + /* USER CODE BEGIN (18) */ /* USER CODE END */ } else { - /* Clear the ICEPICK reset flag in Exception Status register */ + /* Clear the ICEPICK reset flag in Exception Status register */ SYS_EXCEPTION = ICEPICK_RESET; /* USER CODE BEGIN (19) */ /* USER CODE END */ @@ -221,108 +205,21 @@ void _c_int00(void) /* USER CODE END */ } - /* Check if there were ESM group3 errors during power-up. - * These could occur during eFuse auto-load or during reads from flash OTP - * during power-up. Device operation is not reliable and not recommended - * in this case. - * An ESM group3 error only drives the nERROR pin low. An external circuit - * that monitors the nERROR pin must take the appropriate action to ensure that - * the system is placed in a safe state, as determined by the application. - */ - if ((esmREG->ESTATUS1[2]) != 0U) - { - /* for(;;) can be removed by adding "# if 0" and "# endif" in the user codes above and below */ -/* USER CODE BEGIN (24) */ -/* USER CODE END */ - for(;;) - { - }/* Wait */ -/* USER CODE BEGIN (25) */ -/* USER CODE END */ - } - /* USER CODE BEGIN (26) */ /* USER CODE END */ - /* Initialize System - Clock, Flash settings with Efuse self check */ systemInit(); - - /* USER CODE BEGIN (29) */ /* USER CODE END */ - - - /* Run a diagnostic check on the memory self-test controller. - * This function chooses a RAM test algorithm and runs it on an on-chip ROM. - * The memory self-test is expected to fail. The function ensures that the PBIST controller - * is capable of detecting and indicating a memory self-test failure. - */ - pbistSelfCheck(); - /* USER CODE BEGIN (31) */ /* USER CODE END */ - - - /* Run PBIST on CPU RAM. - * The PBIST controller needs to be configured separately for single-port and dual-port SRAMs. - * The CPU RAM is a single-port memory. The actual "RAM Group" for all on-chip SRAMs is defined in the - * device datasheet. - */ - pbistRun(0x08300020U, /* ESRAM Single Port PBIST */ - (uint32)PBIST_March13N_SP); - -/* USER CODE BEGIN (32) */ -/* USER CODE END */ - - /* Wait for PBIST for CPU RAM to be completed */ - while((!pbistIsTestCompleted()) == TRUE) - { - }/* Wait */ - - /* USER CODE BEGIN (33) */ /* USER CODE END */ - /* Check if CPU RAM passed the self-test */ - if( pbistIsTestPassed() != TRUE) - { - /* CPU RAM failed the self-test. - * Need custom handler to check the memory failure - * and to take the appropriate next step. - */ - if(pbistPortTestStatus((uint32)PBIST_PORT0) != TRUE) - { - memoryPort0TestFailNotification((uint32)((pbistREG->RAMT & 0xFF000000U) >> 24U), (uint32)((pbistREG->RAMT & 0x00FF0000U) >> 16U), (uint32)pbistREG->FSRA0, (uint32)pbistREG->FSRDL0); - } - else if(pbistPortTestStatus((uint32)PBIST_PORT1) != TRUE) - { - memoryPort1TestFailNotification((uint32)((pbistREG->RAMT & 0xFF000000U) >> 24U), (uint32)((pbistREG->RAMT & 0x00FF0000U) >> 16U),(uint32)pbistREG->FSRA1, (uint32)pbistREG->FSRDL1); - } - else - { - /* for(;;) can be removed by adding "# if 0" and "# endif" in the user codes above and below */ -/* USER CODE BEGIN (34) */ -/* USER CODE END */ - for(;;) - { - }/* Wait */ - -/* USER CODE BEGIN (35) */ -/* USER CODE END */ - } - } - /* USER CODE BEGIN (36) */ /* USER CODE END */ - - /* Disable PBIST clocks and disable memory self-test mode */ - pbistStop(); - - /* USER CODE BEGIN (37) */ /* USER CODE END */ - - /* Initialize CPU RAM. * This function uses the system module's hardware for auto-initialization of memories and their * associated protection schemes. The CPU RAM is initialized by setting bit 0 of the MSIENA register. @@ -333,58 +230,13 @@ void _c_int00(void) /* USER CODE BEGIN (38) */ /* USER CODE END */ - - /* Enable ECC checking for TCRAM accesses. - * This function enables the CPU's ECC logic for accesses to B0TCM and B1TCM. - */ _coreEnableRamEcc_(); - /* USER CODE BEGIN (39) */ /* USER CODE END */ - - - /* Start PBIST on all dual-port memories */ - /* NOTE : Please Refer DEVICE DATASHEET for the list of Supported Dual port Memories. - PBIST test perfomed only on the user selected memories in HALCoGen's GUI SAFETY INIT tab. - */ - - pbistRun( 0x00000000U - | 0x00000000U - | 0x00000800U - | 0x00000200U - | 0x00000040U - | 0x00000080U - | 0x00000100U - | 0x00000004U - | 0x00000008U - | 0x00000010U - | 0x00000400U - | 0x00020000U - | 0x00001000U - | 0x00040000U - | 0x00002000U - | 0x00080000U - | 0x00004000U - | 0x00000000U - | 0x00000000U - ,(uint32) PBIST_March13N_DP); - /* USER CODE BEGIN (40) */ /* USER CODE END */ - - - /* Test the CPU ECC mechanism for RAM accesses. - * The checkBxRAMECC functions cause deliberate single-bit and double-bit errors in TCRAM accesses - * by corrupting 1 or 2 bits in the ECC. Reading from the TCRAM location with a 2-bit error - * in the ECC causes a data abort exception. The data abort handler is written to look for - * deliberately caused exception and to return the code execution to the instruction - * following the one that caused the abort. - */ - checkB0RAMECC(); tcram1REG->RAMCTRL &= ~(0x00000100U); /* disable writes to ECC RAM */ tcram2REG->RAMCTRL &= ~(0x00000100U); - - checkB1RAMECC(); tcram1REG->RAMCTRL &= ~(0x00000100U); /* disable writes to ECC RAM */ tcram2REG->RAMCTRL &= ~(0x00000100U); @@ -395,74 +247,28 @@ void _c_int00(void) /* USER CODE BEGIN (43) */ /* USER CODE END */ - /* Wait for PBIST for CPU RAM to be completed */ - while((!pbistIsTestCompleted()) == TRUE) - { - }/* Wait */ - - /* USER CODE BEGIN (44) */ /* USER CODE END */ - /* Check if CPU RAM passed the self-test */ - if( pbistIsTestPassed() != TRUE) - { - -/* USER CODE BEGIN (45) */ -/* USER CODE END */ - - /* CPU RAM failed the self-test. - * Need custom handler to check the memory failure - * and to take the appropriate next step. - */ - if(pbistPortTestStatus((uint32)PBIST_PORT0) != TRUE) - { - memoryPort0TestFailNotification((uint32)((pbistREG->RAMT & 0xFF000000U) >> 24U), (uint32)((pbistREG->RAMT & 0x00FF0000U) >> 16U),(uint32)pbistREG->FSRA0, (uint32)pbistREG->FSRDL0); - } - else if(pbistPortTestStatus((uint32)PBIST_PORT1) != TRUE) - { - memoryPort1TestFailNotification((uint32)((pbistREG->RAMT & 0xFF000000U) >> 24U), (uint32)((pbistREG->RAMT & 0x00FF0000U) >> 16U), (uint32)pbistREG->FSRA1, (uint32)pbistREG->FSRDL1); - } - else - { - /* for(;;) can be removed by adding "# if 0" and "# endif" in the user codes above and below */ -/* USER CODE BEGIN (46) */ -/* USER CODE END */ - for(;;) - { - }/* Wait */ - -/* USER CODE BEGIN (47) */ -/* USER CODE END */ - } - } - /* USER CODE BEGIN (48) */ /* USER CODE END */ - - /* Disable PBIST clocks and disable memory self-test mode */ - pbistStop(); - - - /* USER CODE BEGIN (56) */ /* USER CODE END */ - /* Release the MibSPI1 modules from local reset. * This will cause the MibSPI1 RAMs to get initialized along with the parity memory. */ mibspiREG1->GCR0 = 0x1U; - + /* Release the MibSPI3 modules from local reset. * This will cause the MibSPI3 RAMs to get initialized along with the parity memory. */ mibspiREG3->GCR0 = 0x1U; - + /* Release the MibSPI5 modules from local reset. * This will cause the MibSPI5 RAMs to get initialized along with the parity memory. */ mibspiREG5->GCR0 = 0x1U; - + /* USER CODE BEGIN (57) */ /* USER CODE END */ @@ -475,129 +281,74 @@ void _c_int00(void) /* NOTE : Please Refer DEVICE DATASHEET for the list of Supported Memories and their channel numbers. Memory Initialization is perfomed only on the user selected memories in HALCoGen's GUI SAFETY INIT tab. */ - memoryInit( (1U << 1U) - | (1U << 2U) - | (1U << 5U) - | (1U << 6U) - | (1U << 10U) - | (1U << 8U) - | (1U << 14U) - | (1U << 3U) - | (1U << 4U) - | (1U << 15U) - | (1U << 16U) + memoryInit( (1U << 1U) + | (1U << 2U) + | (1U << 5U) + | (1U << 6U) + | (1U << 10U) + | (1U << 8U) + | (1U << 14U) + | (1U << 3U) + | (1U << 4U) + | (1U << 15U) + | (1U << 16U) | (0U << 13U) ); - - /* Test the parity protection mechanism for peripheral RAMs - NOTE : Please Refer DEVICE DATASHEET for the list of Supported Memories with parity. - Parity Self check is perfomed only on the user selected memories in HALCoGen's GUI SAFETY INIT tab. - */ - /* USER CODE BEGIN (58) */ /* USER CODE END */ - - het1ParityCheck(); - /* USER CODE BEGIN (59) */ /* USER CODE END */ - - htu1ParityCheck(); - /* USER CODE BEGIN (60) */ /* USER CODE END */ - - het2ParityCheck(); - /* USER CODE BEGIN (61) */ /* USER CODE END */ - - htu2ParityCheck(); - /* USER CODE BEGIN (62) */ /* USER CODE END */ - - adc1ParityCheck(); - /* USER CODE BEGIN (63) */ /* USER CODE END */ - - adc2ParityCheck(); - /* USER CODE BEGIN (64) */ /* USER CODE END */ - - can1ParityCheck(); - /* USER CODE BEGIN (65) */ /* USER CODE END */ - - can2ParityCheck(); - /* USER CODE BEGIN (66) */ /* USER CODE END */ - - can3ParityCheck(); - /* USER CODE BEGIN (67) */ /* USER CODE END */ - - vimParityCheck(); - /* USER CODE BEGIN (68) */ /* USER CODE END */ - - dmaParityCheck(); - - /* USER CODE BEGIN (69) */ /* USER CODE END */ while ((mibspiREG1->FLG & 0x01000000U) == 0x01000000U) - { - }/* Wait */ + { + }/* Wait */ /* wait for MibSPI1 RAM to complete initialization */ while ((mibspiREG3->FLG & 0x01000000U) == 0x01000000U) - { - }/* Wait */ - /* wait for MibSPI3 RAM to complete initialization */ + { + }/* Wait */ + /* wait for MibSPI3 RAM to complete initialization */ while ((mibspiREG5->FLG & 0x01000000U) == 0x01000000U) - { - }/* Wait */ + { + }/* Wait */ /* wait for MibSPI5 RAM to complete initialization */ /* USER CODE BEGIN (70) */ /* USER CODE END */ - - mibspi1ParityCheck(); - /* USER CODE BEGIN (71) */ /* USER CODE END */ - - mibspi3ParityCheck(); - /* USER CODE BEGIN (72) */ /* USER CODE END */ - - mibspi5ParityCheck(); - /* USER CODE BEGIN (73) */ /* USER CODE END */ - - /* USER CODE BEGIN (74) */ /* USER CODE END */ /* Initialize VIM table */ - vimInit(); + vimInit(); /* USER CODE BEGIN (75) */ /* USER CODE END */ - /* Configure system response to error conditions signaled to the ESM group1 */ - /* This function can be configured from the ESM tab of HALCoGen */ - esmInit(); - /* initialize copy table */ if ((uint32 *)&__binit__ != (uint32 *)0xFFFFFFFFU) { @@ -636,14 +387,12 @@ void _c_int00(void) /* USER CODE BEGIN (76) */ /* USER CODE END */ - /* call the application */ main(); /* USER CODE BEGIN (77) */ /* USER CODE END */ - exit(); /* USER CODE BEGIN (78) */ /* USER CODE END */ } diff --git a/bsp/rm48x50/HALCoGen/source/sys_vim.c b/bsp/rm48x50/HALCoGen/source/sys_vim.c index e48b9f1e81..97b91501be 100644 --- a/bsp/rm48x50/HALCoGen/source/sys_vim.c +++ b/bsp/rm48x50/HALCoGen/source/sys_vim.c @@ -30,140 +30,6 @@ typedef volatile struct vimRam #define vimRAM ((vimRAM_t *)0xFFF82000U) -static const t_isrFuncPTR s_vim_init[129] = -{ - &phantomInterrupt, - &esmHighInterrupt, - &phantomInterrupt, - &phantomInterrupt, - &phantomInterrupt, - &phantomInterrupt, - &rtiCompare3Interrupt, - &phantomInterrupt, - &phantomInterrupt, - &phantomInterrupt, - &phantomInterrupt, - &phantomInterrupt, - &phantomInterrupt, - &phantomInterrupt, - &linHighLevelInterrupt, - &phantomInterrupt, - &phantomInterrupt, - &phantomInterrupt, - &phantomInterrupt, - &phantomInterrupt, - &phantomInterrupt, - &phantomInterrupt, - &phantomInterrupt, - &phantomInterrupt, - &phantomInterrupt, - &phantomInterrupt, - &phantomInterrupt, - &phantomInterrupt, - &phantomInterrupt, - &phantomInterrupt, - &phantomInterrupt, - &phantomInterrupt, - &phantomInterrupt, - &phantomInterrupt, - &phantomInterrupt, - &phantomInterrupt, - &phantomInterrupt, - &phantomInterrupt, - &phantomInterrupt, - &phantomInterrupt, - &phantomInterrupt, - &phantomInterrupt, - &phantomInterrupt, - &phantomInterrupt, - &phantomInterrupt, - &phantomInterrupt, - &phantomInterrupt, - &phantomInterrupt, - &phantomInterrupt, - &phantomInterrupt, - &phantomInterrupt, - &phantomInterrupt, - &phantomInterrupt, - &phantomInterrupt, - &phantomInterrupt, - &phantomInterrupt, - &phantomInterrupt, - &phantomInterrupt, - &phantomInterrupt, - &phantomInterrupt, - &phantomInterrupt, - &phantomInterrupt, - &phantomInterrupt, - &phantomInterrupt, - &phantomInterrupt, - &phantomInterrupt, - &phantomInterrupt, - &phantomInterrupt, - &phantomInterrupt, - &phantomInterrupt, - &phantomInterrupt, - &phantomInterrupt, - &phantomInterrupt, - &phantomInterrupt, - &phantomInterrupt, - &phantomInterrupt, - &phantomInterrupt, - &phantomInterrupt, - &phantomInterrupt, - &phantomInterrupt, - &phantomInterrupt, - &phantomInterrupt, - &phantomInterrupt, - &phantomInterrupt, - &phantomInterrupt, - &phantomInterrupt, - &phantomInterrupt, - &phantomInterrupt, - &phantomInterrupt, - &phantomInterrupt, - &phantomInterrupt, - &phantomInterrupt, - &phantomInterrupt, - &phantomInterrupt, - &phantomInterrupt, - &phantomInterrupt, - &phantomInterrupt, - &phantomInterrupt, - &phantomInterrupt, - &phantomInterrupt, - &phantomInterrupt, - &phantomInterrupt, - &phantomInterrupt, - &phantomInterrupt, - &phantomInterrupt, - &phantomInterrupt, - &phantomInterrupt, - &phantomInterrupt, - &phantomInterrupt, - &phantomInterrupt, - &phantomInterrupt, - &phantomInterrupt, - &phantomInterrupt, - &phantomInterrupt, - &phantomInterrupt, - &phantomInterrupt, - &phantomInterrupt, - &phantomInterrupt, - &phantomInterrupt, - &phantomInterrupt, - &phantomInterrupt, - &phantomInterrupt, - &phantomInterrupt, - &phantomInterrupt, - &phantomInterrupt, - &phantomInterrupt, - &phantomInterrupt, - &phantomInterrupt, - &phantomInterrupt, -}; -void vimParityErrorHandler(void); - /** @fn void vimInit(void) * @brief Initializes VIM module * @@ -172,18 +38,8 @@ void vimParityErrorHandler(void); void vimInit(void) { -/* Initialize VIM table */ - { - uint32 i; - - for (i = 0U; i < (VIM_CHANNELS + 1U); i++) - { - vimRAM->ISR[i] = s_vim_init[i]; - } - } - /* Set Fall-Back Address Parity Error Register */ - VIM_FBPARERR = (uint32)&vimParityErrorHandler; + /*VIM_FBPARERR = (uint32)&vimParityErrorHandler;*/ /* set IRQ/FIQ priorities */ vimREG->FIRQPR0 = SYS_FIQ @@ -627,6 +483,7 @@ void vimGetConfigValue(vim_config_reg_t *config_reg, config_value_type_t type) } +#if 0 #pragma CODE_STATE(vimParityErrorHandler, 32) #pragma INTERRUPT(vimParityErrorHandler, IRQ) @@ -674,3 +531,4 @@ void vimParityErrorHandler(void) } } } +#endif diff --git a/bsp/rm48x50/HALCoGen/source/system.c b/bsp/rm48x50/HALCoGen/source/system.c index 49ddb1d786..58c1ec8635 100644 --- a/bsp/rm48x50/HALCoGen/source/system.c +++ b/bsp/rm48x50/HALCoGen/source/system.c @@ -282,7 +282,7 @@ void systemInit(void) /* Run eFuse controller start-up checks and start eFuse controller ECC self-test. * This includes a check for the eFuse controller error outputs to be stuck-at-zero. */ - efcCheck(); + //efcCheck(); /* USER CODE BEGIN (17) */ /* USER CODE END */ @@ -294,17 +294,18 @@ void systemInit(void) /* USER CODE END */ /* Configure device-level multiplexing and I/O multiplexing */ - muxInit(); + //muxInit(); /* USER CODE BEGIN (19) */ /* USER CODE END */ +#if 0 /* Wait for eFuse controller self-test to complete and check results */ if ((!checkefcSelfTest()) !=0U) /* eFuse controller ECC logic self-test failed */ { efcClass2Error(); /* device operation is not reliable */ } - +#endif /* USER CODE BEGIN (20) */ /* USER CODE END */ |