diff options
13 files changed, 2451 insertions, 115 deletions
diff --git a/bsp/stm32/stm32f429-atk-apollo/board/CubeMX_Config/.mxproject b/bsp/stm32/stm32f429-atk-apollo/board/CubeMX_Config/.mxproject index a670902ac2..ce6cbcb32b 100644 --- a/bsp/stm32/stm32f429-atk-apollo/board/CubeMX_Config/.mxproject +++ b/bsp/stm32/stm32f429-atk-apollo/board/CubeMX_Config/.mxproject @@ -1,17 +1,17 @@ [PreviousGenFiles] -HeaderPath=D:/rt-thread/bsp/stm32/stm32f429-atk-apollo/board/CubeMX_Config/Inc +HeaderPath=E:/work_relative/RT_THREAD/rt-thread/bsp/stm32/stm32f429-atk-apollo/board/CubeMX_Config/Inc HeaderFiles=stm32f4xx_it.h;stm32f4xx_hal_conf.h;main.h; -SourcePath=D:/rt-thread/bsp/stm32/stm32f429-atk-apollo/board/CubeMX_Config/Src +SourcePath=E:/work_relative/RT_THREAD/rt-thread/bsp/stm32/stm32f429-atk-apollo/board/CubeMX_Config/Src SourceFiles=stm32f4xx_it.c;stm32f4xx_hal_msp.c;main.c; [PreviousLibFiles] -LibFiles=Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_adc.h;Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_adc_ex.h;Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_can.h;Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_eth.h;Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_ll_fmc.h;Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_sdram.h;Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_iwdg.h;Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_rtc.h;Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_rtc_ex.h;Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_ll_sdmmc.h;Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_sd.h;Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_spi.h;Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_tim.h;Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_tim_ex.h;Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_uart.h;Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_rcc.h;Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_rcc_ex.h;Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_flash.h;Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_flash_ex.h;Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_flash_ramfunc.h;Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_gpio.h;Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_gpio_ex.h;Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_dma_ex.h;Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_dma.h;Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_pwr.h;Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_pwr_ex.h;Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_cortex.h;Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal.h;Drivers/STM32F4xx_HAL_Driver/Inc/Legacy/stm32_hal_legacy.h;Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_def.h;Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_exti.h;Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_adc.c;Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_adc_ex.c;Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_can.c;Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_eth.c;Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_ll_fmc.c;Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_sdram.c;Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_iwdg.c;Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_rtc.c;Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_rtc_ex.c;Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_ll_sdmmc.c;Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_sd.c;Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_spi.c;Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_tim.c;Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_tim_ex.c;Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_uart.c;Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_rcc.c;Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_rcc_ex.c;Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_flash.c;Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_flash_ex.c;Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_flash_ramfunc.c;Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_gpio.c;Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_dma_ex.c;Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_dma.c;Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pwr.c;Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pwr_ex.c;Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_cortex.c;Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal.c;Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_exti.c;Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_adc.h;Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_adc_ex.h;Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_can.h;Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_eth.h;Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_ll_fmc.h;Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_sdram.h;Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_iwdg.h;Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_rtc.h;Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_rtc_ex.h;Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_ll_sdmmc.h;Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_sd.h;Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_spi.h;Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_tim.h;Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_tim_ex.h;Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_uart.h;Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_rcc.h;Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_rcc_ex.h;Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_flash.h;Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_flash_ex.h;Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_flash_ramfunc.h;Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_gpio.h;Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_gpio_ex.h;Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_dma_ex.h;Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_dma.h;Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_pwr.h;Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_pwr_ex.h;Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_cortex.h;Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal.h;Drivers/STM32F4xx_HAL_Driver/Inc/Legacy/stm32_hal_legacy.h;Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_def.h;Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_exti.h;Drivers/CMSIS/Device/ST/STM32F4xx/Include/stm32f429xx.h;Drivers/CMSIS/Device/ST/STM32F4xx/Include/stm32f4xx.h;Drivers/CMSIS/Device/ST/STM32F4xx/Include/system_stm32f4xx.h;Drivers/CMSIS/Device/ST/STM32F4xx/Source/Templates/system_stm32f4xx.c;Drivers/CMSIS/Include/cmsis_armcc.h;Drivers/CMSIS/Include/cmsis_armclang.h;Drivers/CMSIS/Include/cmsis_compiler.h;Drivers/CMSIS/Include/cmsis_gcc.h;Drivers/CMSIS/Include/cmsis_iccarm.h;Drivers/CMSIS/Include/cmsis_version.h;Drivers/CMSIS/Include/core_armv8mbl.h;Drivers/CMSIS/Include/core_armv8mml.h;Drivers/CMSIS/Include/core_cm0.h;Drivers/CMSIS/Include/core_cm0plus.h;Drivers/CMSIS/Include/core_cm1.h;Drivers/CMSIS/Include/core_cm23.h;Drivers/CMSIS/Include/core_cm3.h;Drivers/CMSIS/Include/core_cm33.h;Drivers/CMSIS/Include/core_cm4.h;Drivers/CMSIS/Include/core_cm7.h;Drivers/CMSIS/Include/core_sc000.h;Drivers/CMSIS/Include/core_sc300.h;Drivers/CMSIS/Include/mpu_armv7.h;Drivers/CMSIS/Include/mpu_armv8.h;Drivers/CMSIS/Include/tz_context.h; +LibFiles=Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_adc.h;Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_adc_ex.h;Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_can.h;Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_eth.h;Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_ll_fmc.h;Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_sdram.h;Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_iwdg.h;Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_rtc.h;Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_rtc_ex.h;Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_sai.h;Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_sai_ex.h;Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_ll_sdmmc.h;Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_sd.h;Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_spi.h;Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_tim.h;Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_tim_ex.h;Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_uart.h;Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_rcc.h;Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_rcc_ex.h;Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_flash.h;Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_flash_ex.h;Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_flash_ramfunc.h;Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_gpio.h;Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_gpio_ex.h;Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_dma_ex.h;Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_dma.h;Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_pwr.h;Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_pwr_ex.h;Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_cortex.h;Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal.h;Drivers/STM32F4xx_HAL_Driver/Inc/Legacy/stm32_hal_legacy.h;Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_def.h;Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_exti.h;Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_adc.c;Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_adc_ex.c;Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_can.c;Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_eth.c;Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_ll_fmc.c;Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_sdram.c;Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_iwdg.c;Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_rtc.c;Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_rtc_ex.c;Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_sai.c;Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_sai_ex.c;Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_ll_sdmmc.c;Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_sd.c;Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_spi.c;Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_tim.c;Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_tim_ex.c;Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_uart.c;Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_rcc.c;Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_rcc_ex.c;Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_flash.c;Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_flash_ex.c;Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_flash_ramfunc.c;Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_gpio.c;Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_dma_ex.c;Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_dma.c;Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pwr.c;Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pwr_ex.c;Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_cortex.c;Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal.c;Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_exti.c;Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_adc.h;Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_adc_ex.h;Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_can.h;Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_eth.h;Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_ll_fmc.h;Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_sdram.h;Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_iwdg.h;Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_rtc.h;Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_rtc_ex.h;Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_sai.h;Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_sai_ex.h;Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_ll_sdmmc.h;Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_sd.h;Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_spi.h;Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_tim.h;Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_tim_ex.h;Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_uart.h;Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_rcc.h;Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_rcc_ex.h;Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_flash.h;Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_flash_ex.h;Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_flash_ramfunc.h;Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_gpio.h;Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_gpio_ex.h;Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_dma_ex.h;Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_dma.h;Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_pwr.h;Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_pwr_ex.h;Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_cortex.h;Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal.h;Drivers/STM32F4xx_HAL_Driver/Inc/Legacy/stm32_hal_legacy.h;Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_def.h;Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_exti.h;Drivers/CMSIS/Device/ST/STM32F4xx/Include/stm32f429xx.h;Drivers/CMSIS/Device/ST/STM32F4xx/Include/stm32f4xx.h;Drivers/CMSIS/Device/ST/STM32F4xx/Include/system_stm32f4xx.h;Drivers/CMSIS/Device/ST/STM32F4xx/Source/Templates/system_stm32f4xx.c;Drivers/CMSIS/Include/cmsis_armcc.h;Drivers/CMSIS/Include/cmsis_armclang.h;Drivers/CMSIS/Include/cmsis_compiler.h;Drivers/CMSIS/Include/cmsis_gcc.h;Drivers/CMSIS/Include/cmsis_iccarm.h;Drivers/CMSIS/Include/cmsis_version.h;Drivers/CMSIS/Include/core_armv8mbl.h;Drivers/CMSIS/Include/core_armv8mml.h;Drivers/CMSIS/Include/core_cm0.h;Drivers/CMSIS/Include/core_cm0plus.h;Drivers/CMSIS/Include/core_cm1.h;Drivers/CMSIS/Include/core_cm23.h;Drivers/CMSIS/Include/core_cm3.h;Drivers/CMSIS/Include/core_cm33.h;Drivers/CMSIS/Include/core_cm4.h;Drivers/CMSIS/Include/core_cm7.h;Drivers/CMSIS/Include/core_sc000.h;Drivers/CMSIS/Include/core_sc300.h;Drivers/CMSIS/Include/mpu_armv7.h;Drivers/CMSIS/Include/mpu_armv8.h;Drivers/CMSIS/Include/tz_context.h; [] SourceFiles=;; [PreviousUsedKeilFiles] -SourceFiles=..\Src\main.c;..\Src\stm32f4xx_it.c;..\Src\stm32f4xx_hal_msp.c;../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_adc.c;../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_adc_ex.c;../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_can.c;../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_eth.c;../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_ll_fmc.c;../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_sdram.c;../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_iwdg.c;../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_rtc.c;../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_rtc_ex.c;../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_ll_sdmmc.c;../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_sd.c;../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_spi.c;../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_tim.c;../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_tim_ex.c;../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_uart.c;../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_rcc.c;../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_rcc_ex.c;../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_flash.c;../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_flash_ex.c;../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_flash_ramfunc.c;../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_gpio.c;../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_dma_ex.c;../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_dma.c;../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pwr.c;../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pwr_ex.c;../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_cortex.c;../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal.c;../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_exti.c;../\Src/system_stm32f4xx.c;../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_adc.c;../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_adc_ex.c;../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_can.c;../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_eth.c;../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_ll_fmc.c;../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_sdram.c;../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_iwdg.c;../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_rtc.c;../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_rtc_ex.c;../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_ll_sdmmc.c;../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_sd.c;../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_spi.c;../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_tim.c;../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_tim_ex.c;../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_uart.c;../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_rcc.c;../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_rcc_ex.c;../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_flash.c;../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_flash_ex.c;../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_flash_ramfunc.c;../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_gpio.c;../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_dma_ex.c;../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_dma.c;../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pwr.c;../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pwr_ex.c;../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_cortex.c;../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal.c;../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_exti.c;../\Src/system_stm32f4xx.c;../Drivers/CMSIS/Device/ST/STM32F4xx/Source/Templates/system_stm32f4xx.c;null; +SourceFiles=..\Src\main.c;..\Src\stm32f4xx_it.c;..\Src\stm32f4xx_hal_msp.c;../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_adc.c;../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_adc_ex.c;../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_can.c;../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_eth.c;../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_ll_fmc.c;../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_sdram.c;../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_iwdg.c;../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_rtc.c;../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_rtc_ex.c;../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_sai.c;../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_sai_ex.c;../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_ll_sdmmc.c;../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_sd.c;../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_spi.c;../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_tim.c;../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_tim_ex.c;../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_uart.c;../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_rcc.c;../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_rcc_ex.c;../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_flash.c;../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_flash_ex.c;../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_flash_ramfunc.c;../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_gpio.c;../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_dma_ex.c;../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_dma.c;../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pwr.c;../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pwr_ex.c;../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_cortex.c;../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal.c;../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_exti.c;../\Src/system_stm32f4xx.c;../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_adc.c;../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_adc_ex.c;../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_can.c;../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_eth.c;../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_ll_fmc.c;../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_sdram.c;../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_iwdg.c;../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_rtc.c;../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_rtc_ex.c;../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_sai.c;../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_sai_ex.c;../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_ll_sdmmc.c;../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_sd.c;../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_spi.c;../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_tim.c;../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_tim_ex.c;../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_uart.c;../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_rcc.c;../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_rcc_ex.c;../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_flash.c;../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_flash_ex.c;../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_flash_ramfunc.c;../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_gpio.c;../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_dma_ex.c;../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_dma.c;../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pwr.c;../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pwr_ex.c;../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_cortex.c;../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal.c;../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_exti.c;../\Src/system_stm32f4xx.c;../Drivers/CMSIS/Device/ST/STM32F4xx/Source/Templates/system_stm32f4xx.c;null; HeaderPath=..\Drivers\STM32F4xx_HAL_Driver\Inc;..\Drivers\STM32F4xx_HAL_Driver\Inc\Legacy;..\Drivers\CMSIS\Device\ST\STM32F4xx\Include;..\Drivers\CMSIS\Include;..\Inc; CDefines=USE_HAL_DRIVER;STM32F429xx;USE_HAL_DRIVER;STM32F429xx; diff --git a/bsp/stm32/stm32f429-atk-apollo/board/CubeMX_Config/Inc/stm32f4xx_hal_conf.h b/bsp/stm32/stm32f429-atk-apollo/board/CubeMX_Config/Inc/stm32f4xx_hal_conf.h index 3cc23478e5..65a892fc3d 100644 --- a/bsp/stm32/stm32f429-atk-apollo/board/CubeMX_Config/Inc/stm32f4xx_hal_conf.h +++ b/bsp/stm32/stm32f429-atk-apollo/board/CubeMX_Config/Inc/stm32f4xx_hal_conf.h @@ -57,7 +57,7 @@ /* #define HAL_LTDC_MODULE_ENABLED */ /* #define HAL_RNG_MODULE_ENABLED */ #define HAL_RTC_MODULE_ENABLED -/* #define HAL_SAI_MODULE_ENABLED */ +#define HAL_SAI_MODULE_ENABLED #define HAL_SD_MODULE_ENABLED /* #define HAL_MMC_MODULE_ENABLED */ #define HAL_SPI_MODULE_ENABLED diff --git a/bsp/stm32/stm32f429-atk-apollo/board/CubeMX_Config/STM32F429IG.ioc b/bsp/stm32/stm32f429-atk-apollo/board/CubeMX_Config/STM32F429IG.ioc index 59ac576086..fad96a6839 100644 --- a/bsp/stm32/stm32f429-atk-apollo/board/CubeMX_Config/STM32F429IG.ioc +++ b/bsp/stm32/stm32f429-atk-apollo/board/CubeMX_Config/STM32F429IG.ioc @@ -14,114 +14,120 @@ KeepUserPlacement=false Mcu.Family=STM32F4 Mcu.IP0=ADC1 Mcu.IP1=CAN1 -Mcu.IP10=SPI2 -Mcu.IP11=SPI5 -Mcu.IP12=SYS -Mcu.IP13=TIM2 -Mcu.IP14=TIM11 -Mcu.IP15=TIM13 -Mcu.IP16=TIM14 -Mcu.IP17=USART1 -Mcu.IP18=USART2 -Mcu.IP19=USART3 +Mcu.IP10=SPI1 +Mcu.IP11=SPI2 +Mcu.IP12=SPI5 +Mcu.IP13=SYS +Mcu.IP14=TIM2 +Mcu.IP15=TIM11 +Mcu.IP16=TIM13 +Mcu.IP17=TIM14 +Mcu.IP18=USART1 +Mcu.IP19=USART2 Mcu.IP2=ETH +Mcu.IP20=USART3 Mcu.IP3=FMC Mcu.IP4=IWDG Mcu.IP5=NVIC Mcu.IP6=RCC Mcu.IP7=RTC -Mcu.IP8=SDIO -Mcu.IP9=SPI1 -Mcu.IPNb=20 +Mcu.IP8=SAI1 +Mcu.IP9=SDIO +Mcu.IPNb=21 Mcu.Name=STM32F429I(E-G)Tx Mcu.Package=LQFP176 -Mcu.Pin0=PC14/OSC32_IN -Mcu.Pin1=PC15/OSC32_OUT -Mcu.Pin10=PF9 -Mcu.Pin11=PH0/OSC_IN -Mcu.Pin12=PH1/OSC_OUT -Mcu.Pin13=PC0 -Mcu.Pin14=PC1 -Mcu.Pin15=PC2 -Mcu.Pin16=PC3 -Mcu.Pin17=PA1 -Mcu.Pin18=PA2 -Mcu.Pin19=PA3 -Mcu.Pin2=PF0 -Mcu.Pin20=PA5 -Mcu.Pin21=PA6 -Mcu.Pin22=PA7 -Mcu.Pin23=PC4 -Mcu.Pin24=PC5 -Mcu.Pin25=PF11 -Mcu.Pin26=PF12 -Mcu.Pin27=PF13 -Mcu.Pin28=PF14 -Mcu.Pin29=PF15 -Mcu.Pin3=PF1 -Mcu.Pin30=PG0 -Mcu.Pin31=PG1 -Mcu.Pin32=PE7 -Mcu.Pin33=PE8 -Mcu.Pin34=PE9 -Mcu.Pin35=PE10 -Mcu.Pin36=PE11 -Mcu.Pin37=PE12 -Mcu.Pin38=PE13 -Mcu.Pin39=PE14 -Mcu.Pin4=PF2 -Mcu.Pin40=PE15 -Mcu.Pin41=PB10 -Mcu.Pin42=PB11 -Mcu.Pin43=PB13 -Mcu.Pin44=PB14 -Mcu.Pin45=PB15 -Mcu.Pin46=PD8 -Mcu.Pin47=PD9 -Mcu.Pin48=PD10 -Mcu.Pin49=PD14 -Mcu.Pin5=PF3 -Mcu.Pin50=PD15 -Mcu.Pin51=PG2 -Mcu.Pin52=PG4 -Mcu.Pin53=PG5 -Mcu.Pin54=PG8 -Mcu.Pin55=PC8 -Mcu.Pin56=PC9 -Mcu.Pin57=PA9 -Mcu.Pin58=PA10 -Mcu.Pin59=PA11 -Mcu.Pin6=PF4 -Mcu.Pin60=PA12 -Mcu.Pin61=PA13 -Mcu.Pin62=PA14 -Mcu.Pin63=PC10 -Mcu.Pin64=PC11 -Mcu.Pin65=PC12 -Mcu.Pin66=PD0 -Mcu.Pin67=PD1 -Mcu.Pin68=PD2 -Mcu.Pin69=PD5 -Mcu.Pin7=PF5 -Mcu.Pin70=PD6 -Mcu.Pin71=PG11 -Mcu.Pin72=PG13 -Mcu.Pin73=PG14 -Mcu.Pin74=PG15 -Mcu.Pin75=PB3 -Mcu.Pin76=PB5 -Mcu.Pin77=PE0 -Mcu.Pin78=PE1 -Mcu.Pin79=VP_IWDG_VS_IWDG -Mcu.Pin8=PF7 -Mcu.Pin80=VP_RTC_VS_RTC_Activate -Mcu.Pin81=VP_SYS_VS_Systick -Mcu.Pin82=VP_TIM2_VS_ClockSourceINT -Mcu.Pin83=VP_TIM11_VS_ClockSourceINT -Mcu.Pin84=VP_TIM13_VS_ClockSourceINT -Mcu.Pin85=VP_TIM14_VS_ClockSourceINT -Mcu.Pin9=PF8 -Mcu.PinsNb=86 +Mcu.Pin0=PE2 +Mcu.Pin1=PE3 +Mcu.Pin10=PF3 +Mcu.Pin11=PF4 +Mcu.Pin12=PF5 +Mcu.Pin13=PF7 +Mcu.Pin14=PF8 +Mcu.Pin15=PF9 +Mcu.Pin16=PH0/OSC_IN +Mcu.Pin17=PH1/OSC_OUT +Mcu.Pin18=PC0 +Mcu.Pin19=PC1 +Mcu.Pin2=PE4 +Mcu.Pin20=PC2 +Mcu.Pin21=PC3 +Mcu.Pin22=PA1 +Mcu.Pin23=PA2 +Mcu.Pin24=PA3 +Mcu.Pin25=PA5 +Mcu.Pin26=PA6 +Mcu.Pin27=PA7 +Mcu.Pin28=PC4 +Mcu.Pin29=PC5 +Mcu.Pin3=PE5 +Mcu.Pin30=PF11 +Mcu.Pin31=PF12 +Mcu.Pin32=PF13 +Mcu.Pin33=PF14 +Mcu.Pin34=PF15 +Mcu.Pin35=PG0 +Mcu.Pin36=PG1 +Mcu.Pin37=PE7 +Mcu.Pin38=PE8 +Mcu.Pin39=PE9 +Mcu.Pin4=PE6 +Mcu.Pin40=PE10 +Mcu.Pin41=PE11 +Mcu.Pin42=PE12 +Mcu.Pin43=PE13 +Mcu.Pin44=PE14 +Mcu.Pin45=PE15 +Mcu.Pin46=PB10 +Mcu.Pin47=PB11 +Mcu.Pin48=PB13 +Mcu.Pin49=PB14 +Mcu.Pin5=PC14/OSC32_IN +Mcu.Pin50=PB15 +Mcu.Pin51=PD8 +Mcu.Pin52=PD9 +Mcu.Pin53=PD10 +Mcu.Pin54=PD14 +Mcu.Pin55=PD15 +Mcu.Pin56=PG2 +Mcu.Pin57=PG4 +Mcu.Pin58=PG5 +Mcu.Pin59=PG8 +Mcu.Pin6=PC15/OSC32_OUT +Mcu.Pin60=PC8 +Mcu.Pin61=PC9 +Mcu.Pin62=PA9 +Mcu.Pin63=PA10 +Mcu.Pin64=PA11 +Mcu.Pin65=PA12 +Mcu.Pin66=PA13 +Mcu.Pin67=PA14 +Mcu.Pin68=PC10 +Mcu.Pin69=PC11 +Mcu.Pin7=PF0 +Mcu.Pin70=PC12 +Mcu.Pin71=PD0 +Mcu.Pin72=PD1 +Mcu.Pin73=PD2 +Mcu.Pin74=PD5 +Mcu.Pin75=PD6 +Mcu.Pin76=PG11 +Mcu.Pin77=PG13 +Mcu.Pin78=PG14 +Mcu.Pin79=PG15 +Mcu.Pin8=PF1 +Mcu.Pin80=PB3 +Mcu.Pin81=PB5 +Mcu.Pin82=PE0 +Mcu.Pin83=PE1 +Mcu.Pin84=VP_IWDG_VS_IWDG +Mcu.Pin85=VP_RTC_VS_RTC_Activate +Mcu.Pin86=VP_SYS_VS_Systick +Mcu.Pin87=VP_TIM2_VS_ClockSourceINT +Mcu.Pin88=VP_TIM11_VS_ClockSourceINT +Mcu.Pin89=VP_TIM13_VS_ClockSourceINT +Mcu.Pin9=PF2 +Mcu.Pin90=VP_TIM14_VS_ClockSourceINT +Mcu.PinsNb=91 Mcu.ThirdPartyNb=0 Mcu.UserConstants= Mcu.UserName=STM32F429IGTx @@ -230,6 +236,16 @@ PE12.Signal=FMC_D9_DA9 PE13.Signal=FMC_D10_DA10 PE14.Signal=FMC_D11_DA11 PE15.Signal=FMC_D12_DA12 +PE2.Mode=SAI_A_MasterWithClock +PE2.Signal=SAI1_MCLK_A +PE3.Mode=SAI_B_SyncSlave +PE3.Signal=SAI1_SD_B +PE4.Mode=SAI_A_MasterWithClock +PE4.Signal=SAI1_FS_A +PE5.Mode=SAI_A_MasterWithClock +PE5.Signal=SAI1_SCK_A +PE6.Mode=SAI_A_MasterWithClock +PE6.Signal=SAI1_SD_A PE7.Signal=FMC_D4_DA4 PE8.Signal=FMC_D5_DA5 PE9.Signal=FMC_D6_DA6 @@ -313,8 +329,8 @@ RCC.HCLKFreq_Value=180000000 RCC.HSE_VALUE=25000000 RCC.HSI_VALUE=16000000 RCC.I2SClocksFreq_Value=160000000 -RCC.IPParameters=48MHZClocksFreq_Value,AHBFreq_Value,APB1CLKDivider,APB1Freq_Value,APB1TimFreq_Value,APB2CLKDivider,APB2Freq_Value,APB2TimFreq_Value,CortexFreq_Value,EthernetFreq_Value,FCLKCortexFreq_Value,FamilyName,HCLKFreq_Value,HSE_VALUE,HSI_VALUE,I2SClocksFreq_Value,LCDTFTFreq_Value,LSI_VALUE,MCO2PinFreq_Value,PLLCLKFreq_Value,PLLM,PLLN,PLLQ,PLLQCLKFreq_Value,PLLSourceVirtual,RCC_RTC_Clock_Source,RCC_RTC_Clock_SourceVirtual,RTCFreq_Value,RTCHSEDivFreq_Value,SAI_AClocksFreq_Value,SAI_BClocksFreq_Value,SYSCLKFreq_VALUE,SYSCLKSource,VCOI2SOutputFreq_Value,VCOInputFreq_Value,VCOOutputFreq_Value,VCOSAIOutputFreq_Value,VCOSAIOutputFreq_ValueQ,VCOSAIOutputFreq_ValueR,VcooutputI2S,VcooutputI2SQ -RCC.LCDTFTFreq_Value=20416666.666666668 +RCC.IPParameters=48MHZClocksFreq_Value,AHBFreq_Value,APB1CLKDivider,APB1Freq_Value,APB1TimFreq_Value,APB2CLKDivider,APB2Freq_Value,APB2TimFreq_Value,CortexFreq_Value,EthernetFreq_Value,FCLKCortexFreq_Value,FamilyName,HCLKFreq_Value,HSE_VALUE,HSI_VALUE,I2SClocksFreq_Value,LCDTFTFreq_Value,LSI_VALUE,MCO2PinFreq_Value,PLLCLKFreq_Value,PLLM,PLLN,PLLQ,PLLQCLKFreq_Value,PLLSAIN,PLLSourceVirtual,RCC_RTC_Clock_Source,RCC_RTC_Clock_SourceVirtual,RTCFreq_Value,RTCHSEDivFreq_Value,SAI_AClocksFreq_Value,SAI_BClocksFreq_Value,SYSCLKFreq_VALUE,SYSCLKSource,VCOI2SOutputFreq_Value,VCOInputFreq_Value,VCOOutputFreq_Value,VCOSAIOutputFreq_Value,VCOSAIOutputFreq_ValueQ,VCOSAIOutputFreq_ValueR,VcooutputI2S,VcooutputI2SQ +RCC.LCDTFTFreq_Value=25000000 RCC.LSI_VALUE=32000 RCC.MCO2PinFreq_Value=180000000 RCC.PLLCLKFreq_Value=180000000 @@ -322,23 +338,35 @@ RCC.PLLM=15 RCC.PLLN=216 RCC.PLLQ=8 RCC.PLLQCLKFreq_Value=45000000 +RCC.PLLSAIN=60 RCC.PLLSourceVirtual=RCC_PLLSOURCE_HSE RCC.RCC_RTC_Clock_Source=RCC_RTCCLKSOURCE_LSE RCC.RCC_RTC_Clock_SourceVirtual=RCC_RTCCLKSOURCE_LSE RCC.RTCFreq_Value=32768 RCC.RTCHSEDivFreq_Value=12500000 -RCC.SAI_AClocksFreq_Value=20416666.666666668 -RCC.SAI_BClocksFreq_Value=20416666.666666668 +RCC.SAI_AClocksFreq_Value=25000000 +RCC.SAI_BClocksFreq_Value=25000000 RCC.SYSCLKFreq_VALUE=180000000 RCC.SYSCLKSource=RCC_SYSCLKSOURCE_PLLCLK RCC.VCOI2SOutputFreq_Value=320000000 RCC.VCOInputFreq_Value=1666666.6666666667 RCC.VCOOutputFreq_Value=360000000 -RCC.VCOSAIOutputFreq_Value=81666666.66666667 -RCC.VCOSAIOutputFreq_ValueQ=20416666.666666668 -RCC.VCOSAIOutputFreq_ValueR=40833333.333333336 +RCC.VCOSAIOutputFreq_Value=100000000 +RCC.VCOSAIOutputFreq_ValueQ=25000000 +RCC.VCOSAIOutputFreq_ValueR=50000000 RCC.VcooutputI2S=160000000 RCC.VcooutputI2SQ=160000000 +SAI1.ErrorAudioFreq-SAI_A_MasterWithClock=-49.13 % +SAI1.FrameLength-SAI_B_SyncSlave=8 +SAI1.IPParameters=Instance-SAI_B_SyncSlave,VirtualMode-SAI_B_SyncSlave,Synchro-SAI_B_SyncSlave,FrameLength-SAI_B_SyncSlave,Instance-SAI_A_MasterWithClock,VirtualMode-SAI_A_MasterWithClock,Synchro-SAI_A_MasterWithClock,MClockEnable-SAI_A_MasterWithClock,RealAudioFreq-SAI_A_MasterWithClock,ErrorAudioFreq-SAI_A_MasterWithClock +SAI1.Instance-SAI_A_MasterWithClock=SAI$Index_Block_A +SAI1.Instance-SAI_B_SyncSlave=SAI$Index_Block_B +SAI1.MClockEnable-SAI_A_MasterWithClock=SAI_MASTERCLOCK_ENABLE +SAI1.RealAudioFreq-SAI_A_MasterWithClock=97.656 KHz +SAI1.Synchro-SAI_A_MasterWithClock=SAI_ASYNCHRONOUS +SAI1.Synchro-SAI_B_SyncSlave=SAI_SYNCHRONOUS +SAI1.VirtualMode-SAI_A_MasterWithClock=VM_MASTER +SAI1.VirtualMode-SAI_B_SyncSlave=VM_SLAVE SH.ADCx_IN5.0=ADC1_IN5,IN5 SH.ADCx_IN5.ConfNb=1 SH.FMC_A0.0=FMC_A0,13b-sda1 diff --git a/bsp/stm32/stm32f429-atk-apollo/board/CubeMX_Config/Src/main.c b/bsp/stm32/stm32f429-atk-apollo/board/CubeMX_Config/Src/main.c index 77c653fbd9..342aa48b67 100644 --- a/bsp/stm32/stm32f429-atk-apollo/board/CubeMX_Config/Src/main.c +++ b/bsp/stm32/stm32f429-atk-apollo/board/CubeMX_Config/Src/main.c @@ -72,6 +72,9 @@ IWDG_HandleTypeDef hiwdg; RTC_HandleTypeDef hrtc; +SAI_HandleTypeDef hsai_BlockA1; +SAI_HandleTypeDef hsai_BlockB1; + SD_HandleTypeDef hsd; SPI_HandleTypeDef hspi1; @@ -112,6 +115,7 @@ static void MX_SPI1_Init(void); static void MX_SPI2_Init(void); static void MX_SPI5_Init(void); static void MX_CAN1_Init(void); +static void MX_SAI1_Init(void); static void MX_USART2_UART_Init(void); static void MX_USART3_UART_Init(void); /* USER CODE BEGIN PFP */ @@ -168,6 +172,7 @@ int main(void) MX_SPI2_Init(); MX_SPI5_Init(); MX_CAN1_Init(); + MX_SAI1_Init(); MX_USART2_UART_Init(); MX_USART3_UART_Init(); /* USER CODE BEGIN 2 */ @@ -197,6 +202,12 @@ void SystemClock_Config(void) RCC_ClkInitTypeDef RCC_ClkInitStruct = {0}; RCC_PeriphCLKInitTypeDef PeriphClkInitStruct = {0}; + /** Macro to configure SAI1BlockB clock source selection + */ + __HAL_RCC_SAI_BLOCKBCLKSOURCE_CONFIG(SAI_CLKSOURCE_PLLSAI); + /** Macro to configure SAI1BlockA clock source selection + */ + __HAL_RCC_SAI_BLOCKACLKSOURCE_CONFIG(SAI_CLKSOURCE_PLLSAI); /** Configure the main internal regulator output voltage */ __HAL_RCC_PWR_CLK_ENABLE(); @@ -237,7 +248,10 @@ void SystemClock_Config(void) { Error_Handler(); } - PeriphClkInitStruct.PeriphClockSelection = RCC_PERIPHCLK_RTC; + PeriphClkInitStruct.PeriphClockSelection = RCC_PERIPHCLK_SAI_PLLSAI|RCC_PERIPHCLK_RTC; + PeriphClkInitStruct.PLLSAI.PLLSAIN = 60; + PeriphClkInitStruct.PLLSAI.PLLSAIQ = 4; + PeriphClkInitStruct.PLLSAIDivQ = 1; PeriphClkInitStruct.RTCClockSelection = RCC_RTCCLKSOURCE_LSE; if (HAL_RCCEx_PeriphCLKConfig(&PeriphClkInitStruct) != HAL_OK) { @@ -440,6 +454,72 @@ static void MX_RTC_Init(void) } /** + * @brief SAI1 Initialization Function + * @param None + * @retval None + */ +static void MX_SAI1_Init(void) +{ + + /* USER CODE BEGIN SAI1_Init 0 */ + + /* USER CODE END SAI1_Init 0 */ + + /* USER CODE BEGIN SAI1_Init 1 */ + + /* USER CODE END SAI1_Init 1 */ + hsai_BlockA1.Instance = SAI1_Block_A; + hsai_BlockA1.Init.Protocol = SAI_FREE_PROTOCOL; + hsai_BlockA1.Init.AudioMode = SAI_MODEMASTER_TX; + hsai_BlockA1.Init.DataSize = SAI_DATASIZE_24; + hsai_BlockA1.Init.FirstBit = SAI_FIRSTBIT_MSB; + hsai_BlockA1.Init.ClockStrobing = SAI_CLOCKSTROBING_FALLINGEDGE; + hsai_BlockA1.Init.OutputDrive = SAI_OUTPUTDRIVE_DISABLE; + hsai_BlockA1.Init.NoDivider = SAI_MASTERDIVIDER_ENABLE; + hsai_BlockA1.Init.FIFOThreshold = SAI_FIFOTHRESHOLD_EMPTY; + hsai_BlockA1.Init.ClockSource = SAI_CLKSOURCE_PLLSAI; + hsai_BlockA1.Init.AudioFrequency = SAI_AUDIO_FREQUENCY_192K; + hsai_BlockA1.FrameInit.FrameLength = 8; + hsai_BlockA1.FrameInit.ActiveFrameLength = 1; + hsai_BlockA1.FrameInit.FSDefinition = SAI_FS_STARTFRAME; + hsai_BlockA1.FrameInit.FSPolarity = SAI_FS_ACTIVE_LOW; + hsai_BlockA1.FrameInit.FSOffset = SAI_FS_FIRSTBIT; + hsai_BlockA1.SlotInit.FirstBitOffset = 0; + hsai_BlockA1.SlotInit.SlotSize = SAI_SLOTSIZE_DATASIZE; + hsai_BlockA1.SlotInit.SlotNumber = 1; + hsai_BlockA1.SlotInit.SlotActive = 0x00000000; + if (HAL_SAI_Init(&hsai_BlockA1) != HAL_OK) + { + Error_Handler(); + } + hsai_BlockB1.Instance = SAI1_Block_B; + hsai_BlockB1.Init.Protocol = SAI_FREE_PROTOCOL; + hsai_BlockB1.Init.AudioMode = SAI_MODESLAVE_RX; + hsai_BlockB1.Init.DataSize = SAI_DATASIZE_24; + hsai_BlockB1.Init.FirstBit = SAI_FIRSTBIT_MSB; + hsai_BlockB1.Init.ClockStrobing = SAI_CLOCKSTROBING_FALLINGEDGE; + hsai_BlockB1.Init.OutputDrive = SAI_OUTPUTDRIVE_DISABLE; + hsai_BlockB1.Init.FIFOThreshold = SAI_FIFOTHRESHOLD_EMPTY; + hsai_BlockB1.FrameInit.FrameLength = 8; + hsai_BlockB1.FrameInit.ActiveFrameLength = 1; + hsai_BlockB1.FrameInit.FSDefinition = SAI_FS_STARTFRAME; + hsai_BlockB1.FrameInit.FSPolarity = SAI_FS_ACTIVE_LOW; + hsai_BlockB1.FrameInit.FSOffset = SAI_FS_FIRSTBIT; + hsai_BlockB1.SlotInit.FirstBitOffset = 0; + hsai_BlockB1.SlotInit.SlotSize = SAI_SLOTSIZE_DATASIZE; + hsai_BlockB1.SlotInit.SlotNumber = 1; + hsai_BlockB1.SlotInit.SlotActive = 0x00000000; + if (HAL_SAI_Init(&hsai_BlockB1) != HAL_OK) + { + Error_Handler(); + } + /* USER CODE BEGIN SAI1_Init 2 */ + + /* USER CODE END SAI1_Init 2 */ + +} + +/** * @brief SDIO Initialization Function * @param None * @retval None @@ -896,12 +976,12 @@ static void MX_GPIO_Init(void) { /* GPIO Ports Clock Enable */ + __HAL_RCC_GPIOE_CLK_ENABLE(); __HAL_RCC_GPIOC_CLK_ENABLE(); __HAL_RCC_GPIOF_CLK_ENABLE(); __HAL_RCC_GPIOH_CLK_ENABLE(); __HAL_RCC_GPIOA_CLK_ENABLE(); __HAL_RCC_GPIOG_CLK_ENABLE(); - __HAL_RCC_GPIOE_CLK_ENABLE(); __HAL_RCC_GPIOB_CLK_ENABLE(); __HAL_RCC_GPIOD_CLK_ENABLE(); diff --git a/bsp/stm32/stm32f429-atk-apollo/board/CubeMX_Config/Src/stm32f4xx_hal_msp.c b/bsp/stm32/stm32f429-atk-apollo/board/CubeMX_Config/Src/stm32f4xx_hal_msp.c index e50a6d733b..20fa0028c0 100644 --- a/bsp/stm32/stm32f429-atk-apollo/board/CubeMX_Config/Src/stm32f4xx_hal_msp.c +++ b/bsp/stm32/stm32f429-atk-apollo/board/CubeMX_Config/Src/stm32f4xx_hal_msp.c @@ -1105,6 +1105,97 @@ void HAL_SDRAM_MspDeInit(SDRAM_HandleTypeDef* hsdram){ /* USER CODE END SDRAM_MspDeInit 1 */ } +static uint32_t SAI1_client =0; + +void HAL_SAI_MspInit(SAI_HandleTypeDef* hsai) +{ + + GPIO_InitTypeDef GPIO_InitStruct; +/* SAI1 */ + if(hsai->Instance==SAI1_Block_A) + { + /* Peripheral clock enable */ + if (SAI1_client == 0) + { + __HAL_RCC_SAI1_CLK_ENABLE(); + } + SAI1_client ++; + + /**SAI1_A_Block_A GPIO Configuration + PE2 ------> SAI1_MCLK_A + PE4 ------> SAI1_FS_A + PE5 ------> SAI1_SCK_A + PE6 ------> SAI1_SD_A + */ + GPIO_InitStruct.Pin = GPIO_PIN_2|GPIO_PIN_4|GPIO_PIN_5|GPIO_PIN_6; + GPIO_InitStruct.Mode = GPIO_MODE_AF_PP; + GPIO_InitStruct.Pull = GPIO_NOPULL; + GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_LOW; + GPIO_InitStruct.Alternate = GPIO_AF6_SAI1; + HAL_GPIO_Init(GPIOE, &GPIO_InitStruct); + + } + if(hsai->Instance==SAI1_Block_B) + { + /* Peripheral clock enable */ + if (SAI1_client == 0) + { + __HAL_RCC_SAI1_CLK_ENABLE(); + } + SAI1_client ++; + + /**SAI1_B_Block_B GPIO Configuration + PE3 ------> SAI1_SD_B + */ + GPIO_InitStruct.Pin = GPIO_PIN_3; + GPIO_InitStruct.Mode = GPIO_MODE_AF_PP; + GPIO_InitStruct.Pull = GPIO_NOPULL; + GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_LOW; + GPIO_InitStruct.Alternate = GPIO_AF6_SAI1; + HAL_GPIO_Init(GPIOE, &GPIO_InitStruct); + + } +} + +void HAL_SAI_MspDeInit(SAI_HandleTypeDef* hsai) +{ + +/* SAI1 */ + if(hsai->Instance==SAI1_Block_A) + { + SAI1_client --; + if (SAI1_client == 0) + { + /* Peripheral clock disable */ + __HAL_RCC_SAI1_CLK_DISABLE(); + } + + /**SAI1_A_Block_A GPIO Configuration + PE2 ------> SAI1_MCLK_A + PE4 ------> SAI1_FS_A + PE5 ------> SAI1_SCK_A + PE6 ------> SAI1_SD_A + */ + HAL_GPIO_DeInit(GPIOE, GPIO_PIN_2|GPIO_PIN_4|GPIO_PIN_5|GPIO_PIN_6); + + } + if(hsai->Instance==SAI1_Block_B) + { + SAI1_client --; + if (SAI1_client == 0) + { + /* Peripheral clock disable */ + __HAL_RCC_SAI1_CLK_DISABLE(); + } + + /**SAI1_B_Block_B GPIO Configuration + PE3 ------> SAI1_SD_B + */ + HAL_GPIO_DeInit(GPIOE, GPIO_PIN_3); + + } +} + /* USER CODE BEGIN 1 */ /* USER CODE END 1 */ diff --git a/bsp/stm32/stm32f429-atk-apollo/board/Kconfig b/bsp/stm32/stm32f429-atk-apollo/board/Kconfig index f8bbfea973..e7bdc34715 100644 --- a/bsp/stm32/stm32f429-atk-apollo/board/Kconfig +++ b/bsp/stm32/stm32f429-atk-apollo/board/Kconfig @@ -60,7 +60,24 @@ menu "Onboard Peripheral Drivers" select RT_USING_DFS select RT_USING_DFS_ELMFAT default n + + config BSP_USING_AUDIO + bool "Enable AUDIO (WM8978)" + select BSP_USING_I2C1 + select RT_USING_AUDIO + default n + + if BSP_USING_AUDIO + config BSP_USING_AUDIO_PLAY + bool "Enable Audio Play" + default y + config BSP_USING_AUDIO_RECORD + bool "Enable Audio Record" + select BSP_USING_AUDIO_PLAY + default n + endif + endmenu menu "On-chip Peripheral Drivers" diff --git a/bsp/stm32/stm32f429-atk-apollo/board/SConscript b/bsp/stm32/stm32f429-atk-apollo/board/SConscript index bfe1107e3f..de3c4b99ab 100644 --- a/bsp/stm32/stm32f429-atk-apollo/board/SConscript +++ b/bsp/stm32/stm32f429-atk-apollo/board/SConscript @@ -20,11 +20,21 @@ if GetDepend(['BSP_USING_SPI_FLASH']): if GetDepend(['BSP_USING_SDCARD']): src += Glob('ports/sdcard_port.c') - + +if GetDepend(['BSP_USING_AUDIO']): + src += Glob('ports/audio/drv_wm8978.c') + src += Glob('ports/audio/drv_sound.c') + +if GetDepend(['BSP_USING_AUDIO_RECORD']): + src += Glob('ports/audio/drv_mic.c') + path = [cwd] path += [cwd + '/CubeMX_Config/Inc'] path += [cwd + '/ports'] +if GetDepend(['BSP_USING_AUDIO']): + path += [cwd + '/ports/audio'] + startup_path_prefix = SDK_LIB if rtconfig.CROSS_TOOL == 'gcc': diff --git a/bsp/stm32/stm32f429-atk-apollo/board/ports/audio/drv_mic.c b/bsp/stm32/stm32f429-atk-apollo/board/ports/audio/drv_mic.c new file mode 100644 index 0000000000..ce1021fb60 --- /dev/null +++ b/bsp/stm32/stm32f429-atk-apollo/board/ports/audio/drv_mic.c @@ -0,0 +1,385 @@ +/* + * Copyright (c) 2006-2018, RT-Thread Development Team + * + * SPDX-License-Identifier: Apache-2.0 + * + * Change Logs: + * Date Author Notes + * 2019-07-28 Ernest the first version + */ + +#include "board.h" +#include "drv_mic.h" +#include "drv_wm8978.h" +#include "drv_sound.h" + +#define DBG_TAG "drv.mic" +#define DBG_LVL DBG_INFO +#include <rtdbg.h> + +#define CODEC_I2C_NAME ("i2c1") +#define RX_DMA_FIFO_SIZE (2048) + +extern struct drv_sai _sai_a; +static struct drv_sai _sai_b = {0}; + +struct stm32_mic +{ + struct rt_i2c_bus_device *i2c_bus; + struct rt_audio_device audio; + struct rt_audio_configure config; + rt_uint8_t *rx_fifo; + rt_bool_t startup; +}; +static struct stm32_mic _stm32_audio_record = {0}; + +static rt_err_t SAIB_samplerate_set(rt_uint32_t freq) +{ + __HAL_SAI_DISABLE(&_sai_b.hsai); + _sai_b.hsai.Init.AudioFrequency = freq; + HAL_SAI_Init(&_sai_b.hsai); + __HAL_SAI_ENABLE(&_sai_b.hsai); + + return RT_EOK; +} + +void SAIB_channels_set(rt_uint16_t channels) +{ + if (channels == 2) + { + _sai_b.hsai.Init.MonoStereoMode = SAI_STEREOMODE; + } + else + { + _sai_b.hsai.Init.MonoStereoMode = SAI_MONOMODE; + } + __HAL_SAI_DISABLE(&_sai_b.hsai); + HAL_SAI_Init(&_sai_b.hsai); + __HAL_SAI_ENABLE(&_sai_b.hsai); +} + +void SAIB_samplebits_set(rt_uint16_t samplebits) +{ + switch (samplebits) + { + case 16: + _sai_b.hsai.Init.DataSize = SAI_DATASIZE_16; + break; + case 24: + _sai_b.hsai.Init.DataSize = SAI_DATASIZE_24; + break; + case 32: + _sai_b.hsai.Init.DataSize = SAI_DATASIZE_32; + break; + default: + _sai_b.hsai.Init.DataSize = SAI_DATASIZE_16; + break; + } + __HAL_SAI_DISABLE(&_sai_b.hsai); + HAL_SAI_Init(&_sai_b.hsai); + __HAL_SAI_ENABLE(&_sai_b.hsai); +} + +void SAIB_config_set(struct rt_audio_configure config) +{ + SAIB_channels_set(config.channels); + SAIB_samplerate_set(config.samplerate); + SAIB_samplebits_set(config.samplebits); +} + +static void SAIB_config_init() +{ + _sai_b.hsai.Instance = SAI1_Block_B; + _sai_b.hsai.Init.AudioMode = SAI_MODESLAVE_RX; + _sai_b.hsai.Init.Synchro = SAI_SYNCHRONOUS; + _sai_b.hsai.Init.OutputDrive = SAI_OUTPUTDRIVE_ENABLE; + _sai_b.hsai.Init.NoDivider = SAI_MASTERDIVIDER_ENABLE; + _sai_b.hsai.Init.FIFOThreshold = SAI_FIFOTHRESHOLD_1QF; + _sai_b.hsai.Init.ClockSource = SAI_CLKSOURCE_PLLI2S; + _sai_b.hsai.Init.MonoStereoMode = SAI_STEREOMODE; + _sai_b.hsai.Init.Protocol = SAI_FREE_PROTOCOL; + _sai_b.hsai.Init.DataSize = SAI_DATASIZE_16; + _sai_b.hsai.Init.FirstBit = SAI_FIRSTBIT_MSB; + _sai_b.hsai.Init.ClockStrobing = SAI_CLOCKSTROBING_RISINGEDGE; + + /* frame */ + _sai_b.hsai.FrameInit.FrameLength = 64; + _sai_b.hsai.FrameInit.ActiveFrameLength = 32; + _sai_b.hsai.FrameInit.FSDefinition = SAI_FS_CHANNEL_IDENTIFICATION; + _sai_b.hsai.FrameInit.FSPolarity = SAI_FS_ACTIVE_LOW; + _sai_b.hsai.FrameInit.FSOffset = SAI_FS_BEFOREFIRSTBIT; + + /* slot */ + _sai_b.hsai.SlotInit.FirstBitOffset = 0; + _sai_b.hsai.SlotInit.SlotSize = SAI_SLOTSIZE_32B; + _sai_b.hsai.SlotInit.SlotNumber = 2; + _sai_b.hsai.SlotInit.SlotActive = SAI_SLOTACTIVE_0 | SAI_SLOTACTIVE_1; + + HAL_SAI_Init(&_sai_b.hsai); + __HAL_SAI_ENABLE(&_sai_b.hsai); +} + +static void SAIB_tx_dma(void) +{ + __HAL_RCC_DMA2_CLK_ENABLE(); + __HAL_LINKDMA(&_sai_b.hsai, hdmarx, _sai_b.hdma); + _sai_b.hdma.Instance = DMA2_Stream5; + _sai_b.hdma.Init.Channel = DMA_CHANNEL_0; + _sai_b.hdma.Init.Direction = DMA_PERIPH_TO_MEMORY; + _sai_b.hdma.Init.PeriphInc = DMA_PINC_DISABLE; + _sai_b.hdma.Init.MemInc = DMA_MINC_ENABLE; + _sai_b.hdma.Init.PeriphDataAlignment = DMA_PDATAALIGN_HALFWORD; + _sai_b.hdma.Init.MemDataAlignment = DMA_MDATAALIGN_HALFWORD; + _sai_b.hdma.Init.Mode = DMA_CIRCULAR; + _sai_b.hdma.Init.Priority = DMA_PRIORITY_MEDIUM; + _sai_b.hdma.Init.FIFOMode = DMA_FIFOMODE_DISABLE; + _sai_b.hdma.Init.MemBurst = DMA_MBURST_SINGLE; + _sai_b.hdma.Init.PeriphBurst = DMA_PBURST_SINGLE; + HAL_DMA_DeInit(&_sai_b.hdma); + HAL_DMA_Init(&_sai_b.hdma); + + __HAL_DMA_DISABLE(&_sai_b.hdma); + + __HAL_DMA_CLEAR_FLAG(&_sai_b.hdma, DMA_FLAG_TCIF1_5); + __HAL_DMA_ENABLE_IT(&_sai_b.hdma, DMA_IT_TC); + + HAL_NVIC_SetPriority(DMA2_Stream5_IRQn, 5, 1); + HAL_NVIC_EnableIRQ(DMA2_Stream5_IRQn); +} + +static rt_err_t sai_record_init() +{ + SAIA_config_init(); + SAIB_config_init(); + + /* set record samplerate */ + SAIA_config_set(_stm32_audio_record.config); + SAIB_config_set(_stm32_audio_record.config); + SAIA_tx_dma(); + SAIB_tx_dma(); + + return RT_EOK; +} + +void DMA2_Stream5_IRQHandler(void) +{ + rt_interrupt_enter(); + HAL_DMA_IRQHandler(_sai_b.hsai.hdmarx); + rt_interrupt_leave(); +} + +void HAL_SAI_RxCpltCallback(SAI_HandleTypeDef *hsai) +{ + rt_audio_rx_done(&(_stm32_audio_record.audio), &_stm32_audio_record.rx_fifo[0], RX_DMA_FIFO_SIZE / 2); +} + +void HAL_SAI_RxHalfCpltCallback(SAI_HandleTypeDef *hsai) +{ + + rt_audio_rx_done(&(_stm32_audio_record.audio), &_stm32_audio_record.rx_fifo[RX_DMA_FIFO_SIZE / 2], RX_DMA_FIFO_SIZE / 2); +} + +static rt_err_t stm32_mic_getcaps(struct rt_audio_device *audio, struct rt_audio_caps *caps) +{ + rt_err_t result = RT_EOK; + + LOG_D("%s:main_type: %d, sub_type: %d", __FUNCTION__, caps->main_type, caps->sub_type); + + switch (caps->main_type) + { + /* Provide capabilities of INTPUT unit */ + case AUDIO_TYPE_INPUT: + { + switch (caps->sub_type) + { + case AUDIO_DSP_PARAM: + caps->udata.config.channels = _stm32_audio_record.config.channels; + caps->udata.config.samplebits = _stm32_audio_record.config.samplebits; + caps->udata.config.samplerate = _stm32_audio_record.config.samplerate; + break; + + case AUDIO_DSP_SAMPLERATE: + caps->udata.config.samplerate = _stm32_audio_record.config.samplerate; + break; + + case AUDIO_DSP_CHANNELS: + caps->udata.config.channels = _stm32_audio_record.config.channels; + break; + + case AUDIO_DSP_SAMPLEBITS: + caps->udata.config.samplebits = _stm32_audio_record.config.samplebits; + break; + default: + result = -RT_ERROR; + break; + } + break; + } + + default: + result = -RT_ERROR; + break; + } + + return result; +} + +static void start_record_mode(void) +{ + rt_uint8_t temp[4] = {0}; + + HAL_SAI_DMAStop(&_sai_b.hsai); + HAL_SAI_Transmit(&_sai_a.hsai, temp, 4, 0); + HAL_SAI_Receive_DMA(&_sai_b.hsai, _stm32_audio_record.rx_fifo, RX_DMA_FIFO_SIZE / 2); +} + +static rt_err_t stm32_mic_configure(struct rt_audio_device *audio, struct rt_audio_caps *caps) +{ + rt_err_t result = RT_EOK; + + LOG_D("%s:main_type: %d, sub_type: %d", __FUNCTION__, caps->main_type, caps->sub_type); + + switch (caps->main_type) + { + case AUDIO_TYPE_INPUT: + { + switch (caps->sub_type) + { + + case AUDIO_DSP_PARAM: + { + _stm32_audio_record.config.samplerate = caps->udata.config.samplerate; + _stm32_audio_record.config.channels = caps->udata.config.channels; + _stm32_audio_record.config.samplebits = caps->udata.config.samplebits; + + HAL_SAI_DMAStop(&_sai_b.hsai); + SAIA_config_set(caps->udata.config); + SAIB_config_set(caps->udata.config); + break; + } + + case AUDIO_DSP_SAMPLERATE: + { + _stm32_audio_record.config.samplerate = caps->udata.config.samplerate; + SAIA_samplerate_set(caps->udata.config.samplerate); + break; + } + case AUDIO_DSP_CHANNELS: + { + _stm32_audio_record.config.channels = caps->udata.config.channels; + SAIA_channels_set(caps->udata.config.channels); + SAIB_channels_set(caps->udata.config.channels); + break; + } + + case AUDIO_DSP_SAMPLEBITS: + { + _stm32_audio_record.config.samplebits = caps->udata.config.samplebits; + SAIA_samplebits_set(caps->udata.config.samplebits); + break; + } + + default: + result = -RT_ERROR; + break; + } + /* After set config, MCLK will stop */ + start_record_mode(); + break; + } + + default: + break; + } + + return result; +} + +static rt_err_t stm32_mic_init(struct rt_audio_device *audio) +{ + rt_err_t result = RT_EOK; + + /* initialize wm8978 */ + _stm32_audio_record.i2c_bus = (struct rt_i2c_bus_device *)rt_device_find(CODEC_I2C_NAME); + if (_stm32_audio_record.i2c_bus != RT_NULL) + { + LOG_D("Find device i2c1 success"); + } + else + { + LOG_E("Find device i2c1 error"); + return -RT_ERROR; + } + + result = wm8978_init(_stm32_audio_record.i2c_bus); + if (result != RT_EOK) + { + LOG_E("initialize wm8978 failed"); + return result; + } + + sai_record_init(); + + return RT_EOK; +} + +static rt_err_t stm32_mic_start(struct rt_audio_device *audio, int stream) +{ + rt_err_t result = RT_EOK; + + if (stream == AUDIO_STREAM_RECORD) + { + /* set mic start */ + wm8978_record_start(_stm32_audio_record.i2c_bus); + /* start transfer data */ + start_record_mode(); + } + + return result; +} + +static rt_err_t stm32_mic_stop(struct rt_audio_device *audio, int stream) +{ + if (stream == AUDIO_STREAM_RECORD) + { + HAL_SAI_DMAStop(&_sai_b.hsai); + HAL_SAI_DMAStop(&_sai_a.hsai); + wm8978_mic_enabled(_stm32_audio_record.i2c_bus, 0); + } + + return RT_EOK; +} + +static struct rt_audio_ops _mic_audio_ops = +{ + .getcaps = stm32_mic_getcaps, + .configure = stm32_mic_configure, + .init = stm32_mic_init, + .start = stm32_mic_start, + .stop = stm32_mic_stop, + .transmit = RT_NULL, + .buffer_info = RT_NULL, +}; + +int rt_hw_mic_init(void) +{ + struct rt_audio_device *audio = &_stm32_audio_record.audio; + /* mic default */ + _stm32_audio_record.rx_fifo = rt_calloc(1, RX_DMA_FIFO_SIZE); + if (_stm32_audio_record.rx_fifo == RT_NULL) + { + return -RT_ENOMEM; + } + + _stm32_audio_record.config.channels = 1; + _stm32_audio_record.config.samplerate = 16000; + _stm32_audio_record.config.samplebits = 16; + + /* register mic device */ + audio->ops = &_mic_audio_ops; + rt_audio_register(audio, "mic0", RT_DEVICE_FLAG_RDONLY, &_stm32_audio_record); + + return RT_EOK; +} + +INIT_DEVICE_EXPORT(rt_hw_mic_init); diff --git a/bsp/stm32/stm32f429-atk-apollo/board/ports/audio/drv_mic.h b/bsp/stm32/stm32f429-atk-apollo/board/ports/audio/drv_mic.h new file mode 100644 index 0000000000..8aeede498c --- /dev/null +++ b/bsp/stm32/stm32f429-atk-apollo/board/ports/audio/drv_mic.h @@ -0,0 +1,17 @@ +/* + * Copyright (c) 2006-2018, RT-Thread Development Team + * + * SPDX-License-Identifier: Apache-2.0 + * + * Change Logs: + * Date Author Notes + * 2019-07-28 Ernest the first version + */ + +#ifndef __DRV_MIC_H_ +#define __DRV_MIC_H_ + +#include <rtthread.h> +#include <rtdevice.h> + +#endif diff --git a/bsp/stm32/stm32f429-atk-apollo/board/ports/audio/drv_sound.c b/bsp/stm32/stm32f429-atk-apollo/board/ports/audio/drv_sound.c new file mode 100644 index 0000000000..4a51ef6347 --- /dev/null +++ b/bsp/stm32/stm32f429-atk-apollo/board/ports/audio/drv_sound.c @@ -0,0 +1,470 @@ +/* + * Copyright (c) 2006-2018, RT-Thread Development Team + * + * SPDX-License-Identifier: Apache-2.0 + * + * Change Logs: + * Date Author Notes + * 2019-07-28 Ernest the first version + */ + +#include "board.h" +#include "drv_wm8978.h" +#include "drv_sound.h" + +#define DBG_TAG "drv.sound" +#define DBG_LVL DBG_INFO +#include <rtdbg.h> + +#define CODEC_I2C_NAME ("i2c1") + +#define TX_DMA_FIFO_SIZE (2048) + +struct drv_sai _sai_a = {0}; + +struct stm32_audio +{ + struct rt_i2c_bus_device *i2c_bus; + struct rt_audio_device audio; + struct rt_audio_configure replay_config; + int replay_volume; + rt_uint8_t *tx_fifo; + rt_bool_t startup; +}; +struct stm32_audio _stm32_audio_play = {0}; + +/* sample_rate, PLLI2SN(50.7), PLLI2SQ, PLLI2SDivQ, MCKDIV */ +const rt_uint32_t SAI_PSC_TBL[][5] = +{ + {AUDIO_FREQUENCY_048K, 206, 7, 0, 12}, + {AUDIO_FREQUENCY_044K, 257, 2, 18, 2}, + {AUDIO_FREQUENCY_032K, 206, 7, 0, 6}, + {AUDIO_FREQUENCY_022K, 257, 2, 18, 1}, + {AUDIO_FREQUENCY_016K, 206, 7, 0, 3}, + {AUDIO_FREQUENCY_011K, 257, 2, 18, 0}, + {AUDIO_FREQUENCY_008K, 206, 7, 0, 2}, +}; + +void SAIA_samplerate_set(rt_uint32_t freq) +{ + RCC_PeriphCLKInitTypeDef PeriphClkInitStruct; + int i; + + /* check frequence */ + for (i = 0; i < (sizeof(SAI_PSC_TBL) / sizeof(SAI_PSC_TBL[0])); i++) + { + if ((freq) == SAI_PSC_TBL[i][0])break; + } + if (i == (sizeof(SAI_PSC_TBL) / sizeof(SAI_PSC_TBL[0]))) + { + LOG_E("Can not support this frequence: %d.", freq); + return; + } + + PeriphClkInitStruct.PeriphClockSelection = RCC_PERIPHCLK_SAI_PLLI2S; + PeriphClkInitStruct.PLLI2S.PLLI2SN = SAI_PSC_TBL[i][1]; + PeriphClkInitStruct.PLLI2S.PLLI2SQ = SAI_PSC_TBL[i][2]; + PeriphClkInitStruct.PLLI2SDivQ = SAI_PSC_TBL[i][3] + 1; + + HAL_RCCEx_PeriphCLKConfig(&PeriphClkInitStruct); + + __HAL_RCC_SAI_BLOCKACLKSOURCE_CONFIG(RCC_SAIACLKSOURCE_PLLI2S); + + __HAL_SAI_DISABLE(&_sai_a.hsai); + _sai_a.hsai.Init.AudioFrequency = freq; + HAL_SAI_Init(&_sai_a.hsai); + __HAL_SAI_ENABLE(&_sai_a.hsai); +} + +void SAIA_channels_set(rt_uint16_t channels) +{ + if (channels == 2) + { + _sai_a.hsai.Init.MonoStereoMode = SAI_STEREOMODE; + } + else + { + _sai_a.hsai.Init.MonoStereoMode = SAI_MONOMODE; + } + __HAL_SAI_DISABLE(&_sai_a.hsai); + HAL_SAI_Init(&_sai_a.hsai); + __HAL_SAI_ENABLE(&_sai_a.hsai); +} + +void SAIA_samplebits_set(rt_uint16_t samplebits) +{ + switch (samplebits) + { + case 16: + _sai_a.hsai.Init.DataSize = SAI_DATASIZE_16; + break; + case 24: + _sai_a.hsai.Init.DataSize = SAI_DATASIZE_24; + break; + case 32: + _sai_a.hsai.Init.DataSize = SAI_DATASIZE_32; + break; + default: + _sai_a.hsai.Init.DataSize = SAI_DATASIZE_16; + break; + } + __HAL_SAI_DISABLE(&_sai_a.hsai); + HAL_SAI_Init(&_sai_a.hsai); + __HAL_SAI_ENABLE(&_sai_a.hsai); +} + +void SAIA_config_set(struct rt_audio_configure config) +{ + SAIA_channels_set(config.channels); + SAIA_samplerate_set(config.samplerate); + SAIA_samplebits_set(config.samplebits); +} + +/* initial sai A */ +rt_err_t SAIA_config_init(void) +{ + _sai_a.hsai.Instance = SAI1_Block_A; + _sai_a.hsai.Init.AudioMode = SAI_MODEMASTER_TX; + _sai_a.hsai.Init.Synchro = SAI_ASYNCHRONOUS; + _sai_a.hsai.Init.OutputDrive = SAI_OUTPUTDRIVE_ENABLE; + _sai_a.hsai.Init.NoDivider = SAI_MASTERDIVIDER_ENABLE; + _sai_a.hsai.Init.FIFOThreshold = SAI_FIFOTHRESHOLD_1QF; + _sai_a.hsai.Init.ClockSource = SAI_CLKSOURCE_PLLI2S; + + _sai_a.hsai.Init.Protocol = SAI_FREE_PROTOCOL; + _sai_a.hsai.Init.DataSize = SAI_DATASIZE_16; + _sai_a.hsai.Init.FirstBit = SAI_FIRSTBIT_MSB; + _sai_a.hsai.Init.ClockStrobing = SAI_CLOCKSTROBING_RISINGEDGE; + + //frame + _sai_a.hsai.FrameInit.FrameLength = 64; + _sai_a.hsai.FrameInit.ActiveFrameLength = 32; + _sai_a.hsai.FrameInit.FSDefinition = SAI_FS_CHANNEL_IDENTIFICATION; + _sai_a.hsai.FrameInit.FSPolarity = SAI_FS_ACTIVE_LOW; + _sai_a.hsai.FrameInit.FSOffset = SAI_FS_BEFOREFIRSTBIT; + + //slot + _sai_a.hsai.SlotInit.FirstBitOffset = 0; + _sai_a.hsai.SlotInit.SlotSize = SAI_SLOTSIZE_32B; + _sai_a.hsai.SlotInit.SlotNumber = 2; + _sai_a.hsai.SlotInit.SlotActive = SAI_SLOTACTIVE_0 | SAI_SLOTACTIVE_1; + + HAL_SAI_Init(&_sai_a.hsai); + __HAL_SAI_ENABLE(&_sai_a.hsai); + + return RT_EOK; +} + +rt_err_t SAIA_tx_dma(void) +{ + __HAL_RCC_DMA2_CLK_ENABLE(); + __HAL_LINKDMA(&_sai_a.hsai, hdmatx, _sai_a.hdma); + + _sai_a.hdma.Instance = DMA2_Stream3; + _sai_a.hdma.Init.Channel = DMA_CHANNEL_0; + _sai_a.hdma.Init.Direction = DMA_MEMORY_TO_PERIPH; + _sai_a.hdma.Init.PeriphInc = DMA_PINC_DISABLE; + _sai_a.hdma.Init.MemInc = DMA_MINC_ENABLE; + + _sai_a.hdma.Init.PeriphDataAlignment = DMA_PDATAALIGN_HALFWORD; + _sai_a.hdma.Init.MemDataAlignment = DMA_MDATAALIGN_HALFWORD; + + _sai_a.hdma.Init.Mode = DMA_CIRCULAR; + _sai_a.hdma.Init.Priority = DMA_PRIORITY_HIGH; + _sai_a.hdma.Init.FIFOMode = DMA_FIFOMODE_DISABLE; + _sai_a.hdma.Init.FIFOThreshold = DMA_FIFO_THRESHOLD_FULL; + _sai_a.hdma.Init.MemBurst = DMA_MBURST_SINGLE; + _sai_a.hdma.Init.PeriphBurst = DMA_PBURST_SINGLE; + + HAL_DMA_DeInit(&_sai_a.hdma); + HAL_DMA_Init(&_sai_a.hdma); + + __HAL_DMA_DISABLE(&_sai_a.hdma); + + __HAL_DMA_ENABLE_IT(&_sai_a.hdma, DMA_IT_TC); + __HAL_DMA_CLEAR_FLAG(&_sai_a.hdma, DMA_FLAG_TCIF3_7); + /* set nvic */ + HAL_NVIC_SetPriority(DMA2_Stream3_IRQn, 5, 0); + HAL_NVIC_EnableIRQ(DMA2_Stream3_IRQn); + return RT_EOK; +} + +void DMA2_Stream3_IRQHandler(void) +{ + rt_interrupt_enter(); + HAL_DMA_IRQHandler(_sai_a.hsai.hdmatx); + rt_interrupt_leave(); +} + +void HAL_SAI_TxHalfCpltCallback(SAI_HandleTypeDef *hsai) +{ + rt_audio_tx_complete(&_stm32_audio_play.audio); +} + +void HAL_SAI_TxCpltCallback(SAI_HandleTypeDef *hsai) +{ + rt_audio_tx_complete(&_stm32_audio_play.audio); +} + +rt_err_t sai_a_init() +{ + /* set sai_a DMA */ + SAIA_tx_dma(); + SAIA_config_init(); + + return RT_EOK; +} + +static rt_err_t stm32_player_getcaps(struct rt_audio_device *audio, struct rt_audio_caps *caps) +{ + rt_err_t result = RT_EOK; + struct stm32_audio *st_audio = (struct stm32_audio *)audio->parent.user_data; + + LOG_D("%s:main_type: %d, sub_type: %d", __FUNCTION__, caps->main_type, caps->sub_type); + + switch (caps->main_type) + { + case AUDIO_TYPE_QUERY: /* query the types of hw_codec device */ + { + switch (caps->sub_type) + { + case AUDIO_TYPE_QUERY: + caps->udata.mask = AUDIO_TYPE_OUTPUT | AUDIO_TYPE_MIXER; + break; + + default: + result = -RT_ERROR; + break; + } + + break; + } + + case AUDIO_TYPE_OUTPUT: /* Provide capabilities of OUTPUT unit */ + { + switch (caps->sub_type) + { + case AUDIO_DSP_PARAM: + caps->udata.config.channels = st_audio->replay_config.channels; + caps->udata.config.samplebits = st_audio->replay_config.samplebits; + caps->udata.config.samplerate = st_audio->replay_config.samplerate; + break; + + case AUDIO_DSP_SAMPLERATE: + caps->udata.config.samplerate = st_audio->replay_config.samplerate; + break; + + case AUDIO_DSP_CHANNELS: + caps->udata.config.channels = st_audio->replay_config.channels; + break; + + case AUDIO_DSP_SAMPLEBITS: + caps->udata.config.samplebits = st_audio->replay_config.samplebits; + break; + + default: + result = -RT_ERROR; + break; + } + + break; + } + + case AUDIO_TYPE_MIXER: /* report the Mixer Units */ + { + switch (caps->sub_type) + { + case AUDIO_MIXER_QUERY: + caps->udata.mask = AUDIO_MIXER_VOLUME | AUDIO_MIXER_LINE; + break; + + case AUDIO_MIXER_VOLUME: + caps->udata.value = st_audio->replay_volume; + break; + + case AUDIO_MIXER_LINE: + break; + + default: + result = -RT_ERROR; + break; + } + + break; + } + + default: + result = -RT_ERROR; + break; + } + + return result; +} + +static rt_err_t stm32_player_configure(struct rt_audio_device *audio, struct rt_audio_caps *caps) +{ + rt_err_t result = RT_EOK; + struct stm32_audio *st_audio = (struct stm32_audio *)audio->parent.user_data; + + LOG_D("%s:main_type: %d, sub_type: %d", __FUNCTION__, caps->main_type, caps->sub_type); + + switch (caps->main_type) + { + case AUDIO_TYPE_MIXER: + { + switch (caps->sub_type) + { + case AUDIO_MIXER_MUTE: + { + /* set mute mode */ + wm8978_mute_enabled(_stm32_audio_play.i2c_bus, RT_FALSE); + break; + } + + case AUDIO_MIXER_VOLUME: + { + int volume = caps->udata.value; + + st_audio->replay_volume = volume; + /* set mixer volume */ + wm8978_set_volume(_stm32_audio_play.i2c_bus, volume); + + break; + } + + default: + result = -RT_ERROR; + break; + } + + break; + } + + case AUDIO_TYPE_OUTPUT: + { + switch (caps->sub_type) + { + case AUDIO_DSP_PARAM: + { + struct rt_audio_configure config = caps->udata.config; + + st_audio->replay_config.samplerate = config.samplerate; + st_audio->replay_config.samplebits = config.samplebits; + st_audio->replay_config.channels = config.channels; + + SAIA_config_set(config); + break; + } + + case AUDIO_DSP_SAMPLERATE: + { + st_audio->replay_config.samplerate = caps->udata.config.samplerate; + SAIA_samplerate_set(caps->udata.config.samplerate); + break; + } + + case AUDIO_DSP_CHANNELS: + { + st_audio->replay_config.channels = caps->udata.config.channels; + SAIA_channels_set(caps->udata.config.channels); + break; + } + + case AUDIO_DSP_SAMPLEBITS: + { + st_audio->replay_config.samplebits = caps->udata.config.samplebits; + SAIA_samplebits_set(caps->udata.config.samplebits); + break; + } + + default: + result = -RT_ERROR; + break; + } + break; + } + + default: + break; + } + + return result; +} + +static rt_err_t stm32_player_init(struct rt_audio_device *audio) +{ + /* initialize wm8978 */ + _stm32_audio_play.i2c_bus = (struct rt_i2c_bus_device *)rt_device_find(CODEC_I2C_NAME); + + sai_a_init(); + wm8978_init(_stm32_audio_play.i2c_bus); + return RT_EOK; +} + +static rt_err_t stm32_player_start(struct rt_audio_device *audio, int stream) +{ + if (stream == AUDIO_STREAM_REPLAY) + { + HAL_SAI_Transmit_DMA(&_sai_a.hsai, _stm32_audio_play.tx_fifo, TX_DMA_FIFO_SIZE / 2); + wm8978_player_start(_stm32_audio_play.i2c_bus); + } + + return RT_EOK; +} + +static rt_err_t stm32_player_stop(struct rt_audio_device *audio, int stream) +{ + if (stream == AUDIO_STREAM_REPLAY) + { + HAL_SAI_DMAStop(&_sai_a.hsai); + } + + return RT_EOK; +} + +static void stm32_player_buffer_info(struct rt_audio_device *audio, struct rt_audio_buf_info *info) +{ + /** + * TX_FIFO + * +----------------+----------------+ + * | block1 | block2 | + * +----------------+----------------+ + * \ block_size / + */ + info->buffer = _stm32_audio_play.tx_fifo; + info->total_size = TX_DMA_FIFO_SIZE; + info->block_size = TX_DMA_FIFO_SIZE / 2; + info->block_count = 2; +} +static struct rt_audio_ops _p_audio_ops = +{ + .getcaps = stm32_player_getcaps, + .configure = stm32_player_configure, + .init = stm32_player_init, + .start = stm32_player_start, + .stop = stm32_player_stop, + .transmit = RT_NULL, + .buffer_info = stm32_player_buffer_info, +}; + +int rt_hw_sound_init(void) +{ + rt_uint8_t *tx_fifo; + + /* player */ + tx_fifo = rt_malloc(TX_DMA_FIFO_SIZE); + if (tx_fifo == RT_NULL) + { + return -RT_ENOMEM; + } + rt_memset(tx_fifo, 0, TX_DMA_FIFO_SIZE); + _stm32_audio_play.tx_fifo = tx_fifo; + + /* register sound device */ + _stm32_audio_play.audio.ops = &_p_audio_ops; + rt_audio_register(&_stm32_audio_play.audio, "sound0", RT_DEVICE_FLAG_WRONLY, &_stm32_audio_play); + + return RT_EOK; +} + +INIT_DEVICE_EXPORT(rt_hw_sound_init); diff --git a/bsp/stm32/stm32f429-atk-apollo/board/ports/audio/drv_sound.h b/bsp/stm32/stm32f429-atk-apollo/board/ports/audio/drv_sound.h new file mode 100644 index 0000000000..216481444f --- /dev/null +++ b/bsp/stm32/stm32f429-atk-apollo/board/ports/audio/drv_sound.h @@ -0,0 +1,40 @@ +/* + * Copyright (c) 2006-2018, RT-Thread Development Team + * + * SPDX-License-Identifier: Apache-2.0 + * + * Change Logs: + * Date Author Notes + * 2019-07-28 Ernest the first version + */ + +#ifndef __DRV_SOUND_H_ +#define __DRV_SOUND_H_ + +#include <rtthread.h> +#include <rtdevice.h> +#include <board.h> + +#define AUDIO_FREQUENCY_048K ((rt_uint32_t) 48000) +#define AUDIO_FREQUENCY_044K ((rt_uint32_t) 44100) +#define AUDIO_FREQUENCY_032K ((rt_uint32_t) 32000) +#define AUDIO_FREQUENCY_022K ((rt_uint32_t) 22050) +#define AUDIO_FREQUENCY_016K ((rt_uint32_t) 16000) +#define AUDIO_FREQUENCY_011K ((rt_uint32_t) 11025) +#define AUDIO_FREQUENCY_008K ((rt_uint32_t) 8000) + +struct drv_sai +{ + SAI_HandleTypeDef hsai; + DMA_HandleTypeDef hdma; +}; + +void SAIA_samplerate_set(rt_uint32_t samplerate); +void SAIA_channels_set(rt_uint16_t channels); +void SAIA_samplebits_set(rt_uint16_t samplebits); +void SAIA_config_set(struct rt_audio_configure config); + +rt_err_t SAIA_tx_dma(void); +rt_err_t SAIA_config_init(void); + +#endif diff --git a/bsp/stm32/stm32f429-atk-apollo/board/ports/audio/drv_wm8978.c b/bsp/stm32/stm32f429-atk-apollo/board/ports/audio/drv_wm8978.c new file mode 100644 index 0000000000..5c7b8084c4 --- /dev/null +++ b/bsp/stm32/stm32f429-atk-apollo/board/ports/audio/drv_wm8978.c @@ -0,0 +1,1140 @@ +/* + * Copyright (c) 2006-2018, RT-Thread Development Team + * + * SPDX-License-Identifier: Apache-2.0 + * + * Change Logs: + * Date Author Notes + * 2018-11-14 ZeroFree first implementation + * 2019-07-28 Ernest perfect player, add record funciton and other APIs + */ + +#include <rtthread.h> +#include <rtdevice.h> + +#include "drv_wm8978.h" +#include <stdlib.h> + +/* Register Definitions */ +#define REG_SOFTWARE_RESET ((uint16_t)0) +#define REG_POWER_MANAGEMENT1 ((uint16_t)(1 << 9)) +#define REG_POWER_MANAGEMENT2 ((uint16_t)(2 << 9)) +#define REG_POWER_MANAGEMENT3 ((uint16_t)(3 << 9)) +#define REG_AUDIO_INTERFACE ((uint16_t)(4 << 9)) +#define REG_COMPANDING ((uint16_t)(5 << 9)) +#define REG_CLOCK_GEN ((uint16_t)(6 << 9)) +#define REG_ADDITIONAL ((uint16_t)(7 << 9)) +#define REG_GPIO ((uint16_t)(8 << 9)) +#define REG_JACK_DETECT1 ((uint16_t)(9 << 9)) +#define REG_DAC ((uint16_t)(10 << 9)) +#define REG_LEFT_DAC_VOL ((uint16_t)(11 << 9)) +#define REG_RIGHT_DAC_VOL ((uint16_t)(12 << 9)) +#define REG_JACK_DETECT2 ((uint16_t)(13 << 9)) +#define REG_ADC ((uint16_t)(14 << 9)) +#define REG_LEFT_ADC_VOL ((uint16_t)(15 << 9)) +#define REG_RIGHT_ADC_VOL ((uint16_t)(16 << 9)) +#define REG_EQ1 ((uint16_t)(18 << 9)) +#define REG_EQ2 ((uint16_t)(19 << 9)) +#define REG_EQ3 ((uint16_t)(20 << 9)) +#define REG_EQ4 ((uint16_t)(21 << 9)) +#define REG_EQ5 ((uint16_t)(22 << 9)) +#define REG_DAC_LIMITER1 ((uint16_t)(24 << 9)) +#define REG_DAC_LIMITER2 ((uint16_t)(25 << 9)) +#define REG_NOTCH_FILTER1 ((uint16_t)(27 << 9)) +#define REG_NOTCH_FILTER2 ((uint16_t)(28 << 9)) +#define REG_NOTCH_FILTER3 ((uint16_t)(29 << 9)) +#define REG_NOTCH_FILTER4 ((uint16_t)(30 << 9)) +#define REG_ALC1 ((uint16_t)(32 << 9)) +#define REG_ALC2 ((uint16_t)(33 << 9)) +#define REG_ALC3 ((uint16_t)(34 << 9)) +#define REG_NOISE_GATE ((uint16_t)(35 << 9)) +#define REG_PLL_N ((uint16_t)(36 << 9)) +#define REG_PLL_K1 ((uint16_t)(37 << 9)) +#define REG_PLL_K2 ((uint16_t)(38 << 9)) +#define REG_PLL_K3 ((uint16_t)(39 << 9)) +#define REG_3D ((uint16_t)(41 << 9)) +#define REG_BEEP ((uint16_t)(43 << 9)) +#define REG_INPUT ((uint16_t)(44 << 9)) +#define REG_LEFT_PGA_GAIN ((uint16_t)(45 << 9)) +#define REG_RIGHT_PGA_GAIN ((uint16_t)(46 << 9)) +#define REG_LEFT_ADC_BOOST ((uint16_t)(47 << 9)) +#define REG_RIGHT_ADC_BOOST ((uint16_t)(48 << 9)) +#define REG_OUTPUT ((uint16_t)(49 << 9)) +#define REG_LEFT_MIXER ((uint16_t)(50 << 9)) +#define REG_RIGHT_MIXER ((uint16_t)(51 << 9)) +#define REG_LOUT1_VOL ((uint16_t)(52 << 9)) +#define REG_ROUT1_VOL ((uint16_t)(53 << 9)) +#define REG_LOUT2_VOL ((uint16_t)(54 << 9)) +#define REG_ROUT2_VOL ((uint16_t)(55 << 9)) +#define REG_OUT3_MIXER ((uint16_t)(56 << 9)) +#define REG_OUT4_MIXER ((uint16_t)(57 << 9)) + +// R01 REG_POWER_MANAGEMENT1 +#define BUFDCOPEN (1 << 8) +#define OUT4MIXEN (1 << 7) +#define OUT3MIXEN (1 << 6) +#define PLLEN (1 << 5) +#define MICBEN (1 << 4) +#define BIASEN (1 << 3) +#define BUFIOEN (1 << 2) +#define VMIDSEL_OFF (0) +#define VMIDSEL_75K (1) +#define VMIDSEL_300K (2) +#define VMIDSEL_5K (3) + +// R02 REG_POWER_MANAGEMENT2 +#define ROUT1EN (1 << 8) +#define LOUT1EN (1 << 7) +#define SLEEP (1 << 6) +#define BOOSTENR (1 << 5) +#define BOOSTENL (1 << 4) +#define INPPGAENR (1 << 3) +#define INPPGAENL (1 << 2) +#define ADCENR (1 << 1) +#define ADCENL (1) + +// R03 REG_POWER_MANAGEMENT3 +#define OUT4EN (1 << 8) +#define OUT3EN (1 << 7) +#define LOUT2EN (1 << 6) +#define ROUT2EN (1 << 5) +#define RMIXEN (1 << 3) +#define LMIXEN (1 << 2) +#define DACENR (1 << 1) +#define DACENL (1) + +// R04 REG_AUDIO_INTERFACE +#define BCP_NORMAL (0) +#define BCP_INVERTED (1 << 8) +#define LRP_NORMAL (0) +#define LRP_INVERTED (1 << 7) +#define WL_16BITS (0) +#define WL_20BITS (1 << 5) +#define WL_24BITS (2 << 5) // Default value +#define WL_32BITS (3 << 5) +#define FMT_RIGHT_JUSTIFIED (0) +#define FMT_LEFT_JUSTIFIED (1 << 3) +#define FMT_I2S (2 << 3) // Default value +#define FMT_PCM (3 << 3) +#define DACLRSWAP (1 << 2) +#define ADCLRSWAP (1 << 1) +#define MONO (1) + +// R05 REG_COMPANDING +#define WL8 (1 << 5) +#define DAC_COMP_OFF (0) // Default value +#define DAC_COMP_ULAW (2 << 3) +#define DAC_COMP_ALAW (3 << 3) +#define ADC_COMP_OFF (0) // Default value +#define ADC_COMP_ULAW (2 << 1) +#define ADC_COMP_ALAW (3 << 1) +#define LOOPBACK (1) + +// R06 REG_CLOCK_GEN +#define CLKSEL_MCLK (0) +#define CLKSEL_PLL (1 << 8) // Default value +#define MCLK_DIV1 (0) +#define MCLK_DIV1_5 (1 << 5) +#define MCLK_DIV2 (2 << 5) // Default value +#define MCLK_DIV3 (3 << 5) +#define MCLK_DIV4 (4 << 5) +#define MCLK_DIV6 (5 << 5) +#define MCLK_DIV8 (6 << 5) +#define MCLK_DIV12 (7 << 5) +#define BCLK_DIV1 (0) // Default value +#define BCLK_DIV2 (1 << 2) +#define BCLK_DIV4 (2 << 2) +#define BCLK_DIV8 (3 << 2) +#define BCLK_DIV16 (4 << 2) +#define BCLK_DIV32 (5 << 2) +#define MS (1) + +// R07 REG_ADDITIONAL +#define WM_SR_48KHZ (0) // Default value +#define WM_SR_32KHZ (1 << 1) +#define WM_SR_24KHZ (2 << 1) +#define WM_SR_16KHZ (3 << 1) +#define WM_SR_12KHZ (4 << 1) +#define WM_SR_8KHZ (5 << 1) +#define SLOWCLKEN (1) + +// R08 REG_GPIO +#define OPCLK_DIV1 (0) // Default value +#define OPCLK_DIV2 (1 << 4) +#define OPCLK_DIV3 (2 << 4) +#define OPCLK_DIV4 (3 << 4) +#define GPIO1POL_NONINVERTED (0) // Default value +#define GPIO1POL_INVERTED (1 << 3) +#define GPIO1SEL_INPUT (0) // Default value +#define GPIO1SEL_TEMP_OK (2) +#define GPIO1SEL_AMUTE_ACTIVE (3) +#define GPIO1SEL_PLL_CLK_OP (4) +#define GPIO1SEL_PLL_LOCK (5) +#define GPIO1SEL_LOGIC1 (6) +#define GPIO1SEL_LOGIC0 (7) + +// R09 REG_JACK_DETECT1 +#define JD_VMID_EN1 (1 << 8) +#define JD_VMID_EN0 (1 << 7) +#define JD_EN (1 << 6) +#define JD_SEL_GPIO1 (0 << 4) // Default value +#define JD_SEL_GPIO2 (1 << 4) +#define JD_SEL_GPIO3 (2 << 4) + +// R10 REG_DAC +#define SOFTMUTE (1 << 6) +#define DACOSR128 (1 << 3) +#define AMUTE (1 << 2) +#define DACPOLR (1 << 1) +#define DACPOLL (1) + +// R11 & R12 REG_LEFT_DAC_VOL & REG_RIGHT_DAC_VOL +#define DACVU (1 << 8) +#define DACVOL_POS (0) +#define DACVOL_MASK (0xFF) + +// R13 REG_JACK_DETECT2 +#define JD_OUT4_EN1 (1 << 7) +#define JD_OUT3_EN1 (1 << 6) +#define JD_OUT2_EN1 (1 << 5) +#define JD_OUT1_EN1 (1 << 4) +#define JD_OUT4_EN0 (1 << 3) +#define JD_OUT3_EN0 (1 << 2) +#define JD_OUT2_EN0 (1 << 1) +#define JD_OUT1_EN0 (1) + +// R14 REG_ADC +#define HPFEN (1 << 8) +#define HPFAPP (1 << 7) +#define HPFCUT_POS (4) +#define HPFCUT_MASK (7) +#define HPFCUT_0 (0) +#define HPFCUT_1 (1 << 4) +#define HPFCUT_2 (2 << 4) +#define HPFCUT_3 (3 << 4) +#define HPFCUT_4 (4 << 4) +#define HPFCUT_5 (5 << 4) +#define HPFCUT_6 (6 << 4) +#define HPFCUT_7 (7 << 4) +#define ADCOSR128 (1 << 3) +#define ADCRPOL (1 << 1) +#define ADCLPOL (1) + +// R15 & R16 REG_LEFT_ADC_VOL & REG_RIGHT_ADC_VOL +#define ADCVU (1 << 8) +#define ADCVOL_POS (0) +#define ADCVOL_MASK (0xFF) + +// R18 REG_EQ1 +#define EQ3DMODE_ADC (0) +#define EQ3DMODE_DAC (1 << 8) // Default value +#define EQ1C_80HZ (0) +#define EQ1C_105HZ (1 << 5) // Default value +#define EQ1C_135HZ (2 << 5) +#define EQ1C_175HZ (3 << 5) + +// R19 REG_EQ2 +#define EQ2BW_NARROW (0) // Default value +#define EQ2BW_WIDE (1 << 8) +#define EQ2C_230HZ (0) +#define EQ2C_300HZ (1 << 5) // Default value +#define EQ2C_385HZ (2 << 5) +#define EQ2C_500HZ (3 << 5) + +// R20 REG_EQ3 +#define EQ3BW_NARROW (0) // Default value +#define EQ3BW_WIDE (1 << 8) +#define EQ3C_650HZ (0) +#define EQ3C_850HZ (1 << 5) // Default value +#define EQ3C_1_1KHZ (2 << 5) +#define EQ3C_1_4KHZ (3 << 5) + +// R21 REG_EQ4 +#define EQ4BW_NARROW (0) // Default value +#define EQ4BW_WIDE (1 << 8) +#define EQ4C_1_8KHZ (0) +#define EQ4C_2_4KHZ (1 << 5) // Default value +#define EQ4C_3_2KHZ (2 << 5) +#define EQ4C_4_1KHZ (3 << 5) + +// R22 REG_EQ5 +#define EQ5C_5_3KHZ (0) +#define EQ5C_6_9KHZ (1 << 5) // Default value +#define EQ5C_9KHZ (2 << 5) +#define EQ5C_11_7KHZ (3 << 5) + +// R18 - R22 +#define EQC_POS (5) +#define EQC_MASK (3) +#define EQG_POS (0) +#define EQG_MASK (31) + +// R24 REG_DAC_LIMITER1 +#define LIMEN (1 << 8) +#define LIMDCY_POS (4) +#define LIMDCY_MASK (15) +#define LIMDCY_750US (0) +#define LIMDCY_1_5MS (1 << 4) +#define LIMDCY_3MS (2 << 4) +#define LIMDCY_6MS (3 << 4) // Default value +#define LIMDCY_12MS (4 << 4) +#define LIMDCY_24MS (5 << 4) +#define LIMDCY_48MS (6 << 4) +#define LIMDCY_96MS (7 << 4) +#define LIMDCY_192MS (8 << 4) +#define LIMDCY_384MS (9 << 4) +#define LIMDCY_768MS (10 << 4) +#define LIMATK_POS (0) +#define LIMATK_MASK (15) +#define LIMATK_94US (0) +#define LIMATK_188US (1) +#define LIMATK_375US (2) // Default value +#define LIMATK_750US (3) +#define LIMATK_1_5MS (4) +#define LIMATK_3MS (5) +#define LIMATK_6MS (6) +#define LIMATK_12MS (7) +#define LIMATK_24MS (8) +#define LIMATK_48MS (9) +#define LIMATK_96MS (10) +#define LIMATK_192MS (11) + +// R25 REG_DAC_LIMITER2 +#define LIMLVL_POS (4) +#define LIMLVL_MASK (7) +#define LIMLVL_N1DB (0) // Default value +#define LIMLVL_N2DB (1 << 4) +#define LIMLVL_N3DB (2 << 4) +#define LIMLVL_N4DB (3 << 4) +#define LIMLVL_N5DB (4 << 4) +#define LIMLVL_N6DB (5 << 4) +#define LIMBOOST_POS (0) +#define LIMBOOST_MASK (15) +#define LIMBOOST_0DB (0) +#define LIMBOOST_1DB (1) +#define LIMBOOST_2DB (2) +#define LIMBOOST_3DB (3) +#define LIMBOOST_4DB (4) +#define LIMBOOST_5DB (5) +#define LIMBOOST_6DB (6) +#define LIMBOOST_7DB (7) +#define LIMBOOST_8DB (8) +#define LIMBOOST_9DB (9) +#define LIMBOOST_10DB (10) +#define LIMBOOST_11DB (11) +#define LIMBOOST_12DB (12) + +// R27 - R30 REG_NOTCH_FILTER1 - REG_NOTCH_FILTER4 +#define NFU (1 << 8) +#define NFEN (1 << 7) +#define NFA_POS (0) +#define NFA_MASK (127) + +// R32 REG_ALC1 +#define ALCSEL_OFF (0) // Default value +#define ALCSEL_RIGHT_ONLY (1 << 7) +#define ALCSEL_LEFT_ONLY (2 << 7) +#define ALCSEL_BOTH_ON (3 << 7) +#define ALCMAXGAIN_POS (3) +#define ALCMAXGAIN_MASK (7) +#define ALCMAXGAIN_N6_75DB (0) +#define ALCMAXGAIN_N0_75DB (1 << 3) +#define ALCMAXGAIN_5_25DB (2 << 3) +#define ALCMAXGAIN_11_25DB (3 << 3) +#define ALCMAXGAIN_17_25DB (4 << 3) +#define ALCMAXGAIN_23_25DB (5 << 3) +#define ALCMAXGAIN_29_25DB (6 << 3) +#define ALCMAXGAIN_35_25DB (7 << 3) // Default value +#define ALCMINGAIN_POS (0) +#define ALCMINGAIN_MASK (7) +#define ALCMINGAIN_N12DB (0) // Default value +#define ALCMINGAIN_N6DB (1) +#define ALCMINGAIN_0DB (2) +#define ALCMINGAIN_6DB (3) +#define ALCMINGAIN_12DB (4) +#define ALCMINGAIN_18DB (5) +#define ALCMINGAIN_24DB (6) +#define ALCMINGAIN_30DB (7) + +// R33 REG_ALC2 +#define ALCHLD_POS (4) +#define ALCHLD_MASK (15) +#define ALCHLD_0MS (0) // Default value +#define ALCHLD_2_67MS (1 << 4) +#define ALCHLD_5_33MS (2 << 4) +#define ALCHLD_10_67MS (3 << 4) +#define ALCHLD_21_33MS (4 << 4) +#define ALCHLD_42_67MS (5 << 4) +#define ALCHLD_85_33MS (6 << 4) +#define ALCHLD_170_67MS (7 << 4) +#define ALCHLD_341_33MS (8 << 4) +#define ALCHLD_682_67MS (9 << 4) +#define ALCHLD_1_36S (10 << 4) +#define ALCLVL_POS (0) +#define ALCLVL_MASK (15) +#define ALCLVL_N22_5DBFS (0) +#define ALCLVL_N21DBFS (1) +#define ALCLVL_N19_5DBFS (2) +#define ALCLVL_N18DBFS (3) +#define ALCLVL_N16_5DBFS (4) +#define ALCLVL_N15DBFS (5) +#define ALCLVL_N13_5DBFS (6) +#define ALCLVL_N12DBFS (7) +#define ALCLVL_N10_5DBFS (8) +#define ALCLVL_N9DBFS (9) +#define ALCLVL_N7_5DBFS (10) +#define ALCLVL_N6DBFS (11) // Default value +#define ALCLVL_N4_5DBFS (12) +#define ALCLVL_N3DBFS (13) +#define ALCLVL_N1_5DBFS (14) + +// R34 REG_ALC3 +#define ALCMODE_ALC (0) // Default value +#define ALCMODE_LIMITER (1 << 8) +#define ALCDCY_POS (4) +#define ALCDCY_MASK (15) +#define ALCDCY_0 (0) +#define ALCDCY_1 (1 << 4) +#define ALCDCY_2 (2 << 4) +#define ALCDCY_3 (3 << 4) // Default value +#define ALCDCY_4 (4 << 4) +#define ALCDCY_5 (5 << 4) +#define ALCDCY_6 (6 << 4) +#define ALCDCY_7 (7 << 4) +#define ALCDCY_8 (8 << 4) +#define ALCDCY_9 (9 << 4) +#define ALCDCY_10 (10 << 4) +#define ALCATK_POS (0) +#define ALCATK_MASK (15) +#define ALCATK_0 (0) +#define ALCATK_1 (1) +#define ALCATK_2 (2) // Default value +#define ALCATK_3 (3) +#define ALCATK_4 (4) +#define ALCATK_5 (5) +#define ALCATK_6 (6) +#define ALCATK_7 (7) +#define ALCATK_8 (8) +#define ALCATK_9 (9) +#define ALCATK_10 (10) + +// R35 REG_NOISE_GATE +#define NGEN (1 << 3) +#define NGTH_POS (0) +#define NGTH_MASK (7) +#define NGTH_N39DB (0) // Default value +#define NGTH_N45DB (1) +#define NGTH_N51DB (2) +#define NGTH_N57DB (3) +#define NGTH_N63DB (4) +#define NGTH_N69DB (5) +#define NGTH_N75DB (6) +#define NGTH_N81DB (7) + +// R36 REG_PLL_N +#define PLLPRESCALE (1 << 4) +#define PLLN_POS (0) +#define PLLN_MASK (15) + +// R37 - R39 REG_PLL_K1 - REG_PLL_K3 +#define PLLK1_POS (0) +#define PLLK1_MASK (63) +#define PLLK2_POS (0) +#define PLLK2_MASK (511) +#define PLLK3_POS (0) +#define PLLK3_MASK (511) + +// R41 REG_3D +#define DEPTH3D_POS (0) +#define DEPTH3D_MASK (15) +#define DEPTH3D_0 (0) // Default value +#define DEPTH3D_6_67 (1) +#define DEPTH3D_13_33 (2) +#define DEPTH3D_20 (3) +#define DEPTH3D_26_67 (4) +#define DEPTH3D_33_33 (5) +#define DEPTH3D_40 (6) +#define DEPTH3D_46_67 (7) +#define DEPTH3D_53_33 (8) +#define DEPTH3D_60 (9) +#define DEPTH3D_66_67 (10) +#define DEPTH3D_73_33 (11) +#define DEPTH3D_80 (12) +#define DEPTH3D_86_67 (13) +#define DEPTH3D_93_33 (14) +#define DEPTH3D_100 (15) + +// R43 REG_BEEP +#define MUTERPGA2INV (1 << 5) +#define INVROUT2 (1 << 4) +#define BEEPVOL_POS (1) +#define BEEPVOL_MASK (7) +#define BEEPVOL_N15DB (0) +#define BEEPVOL_N12DB (1 << 1) +#define BEEPVOL_N9DB (2 << 1) +#define BEEPVOL_N6DB (3 << 1) +#define BEEPVOL_N3DB (4 << 1) +#define BEEPVOL_0DB (5 << 1) +#define BEEPVOL_3DB (6 << 1) +#define BEEPVOL_6DB (7 << 1) +#define BEEPEN (1) + +// R44 REG_INPUT +#define MBVSEL_0_9AVDD (0) // Default value +#define MBVSEL_0_65AVDD (1 << 8) +#define R2_2INPVGA (1 << 6) +#define RIN2INPVGA (1 << 5) // Default value +#define RIP2INPVGA (1 << 4) // Default value +#define L2_2INPVGA (1 << 2) +#define LIN2INPVGA (1 << 1) // Default value +#define LIP2INPVGA (1) // Default value + +// R45 REG_LEFT_PGA_GAIN +#define INPPGAUPDATE (1 << 8) +#define INPPGAZCL (1 << 7) +#define INPPGAMUTEL (1 << 6) + +// R46 REG_RIGHT_PGA_GAIN +#define INPPGAZCR (1 << 7) +#define INPPGAMUTER (1 << 6) + +// R45 - R46 +#define INPPGAVOL_POS (0) +#define INPPGAVOL_MASK (63) + +// R47 REG_LEFT_ADC_BOOST +#define PGABOOSTL (1 << 8) // Default value +#define L2_2BOOSTVOL_POS (4) +#define L2_2BOOSTVOL_MASK (7) +#define L2_2BOOSTVOL_DISABLED (0) // Default value +#define L2_2BOOSTVOL_N12DB (1 << 4) +#define L2_2BOOSTVOL_N9DB (2 << 4) +#define L2_2BOOSTVOL_N6DB (3 << 4) +#define L2_2BOOSTVOL_N3DB (4 << 4) +#define L2_2BOOSTVOL_0DB (5 << 4) +#define L2_2BOOSTVOL_3DB (6 << 4) +#define L2_2BOOSTVOL_6DB (7 << 4) +#define AUXL2BOOSTVOL_POS (0) +#define AUXL2BOOSTVOL_MASK (7) +#define AUXL2BOOSTVOL_DISABLED (0) // Default value +#define AUXL2BOOSTVOL_N12DB (1) +#define AUXL2BOOSTVOL_N9DB (2) +#define AUXL2BOOSTVOL_N6DB (3) +#define AUXL2BOOSTVOL_N3DB (4) +#define AUXL2BOOSTVOL_0DB (5) +#define AUXL2BOOSTVOL_3DB (6) +#define AUXL2BOOSTVOL_6DB (7) + +// R48 REG_RIGHT_ADC_BOOST +#define PGABOOSTR (1 << 8) // Default value +#define R2_2BOOSTVOL_POS (4) +#define R2_2BOOSTVOL_MASK (7) +#define R2_2BOOSTVOL_DISABLED (0) // Default value +#define R2_2BOOSTVOL_N12DB (1 << 4) +#define R2_2BOOSTVOL_N9DB (2 << 4) +#define R2_2BOOSTVOL_N6DB (3 << 4) +#define R2_2BOOSTVOL_N3DB (4 << 4) +#define R2_2BOOSTVOL_0DB (5 << 4) +#define R2_2BOOSTVOL_3DB (6 << 4) +#define R2_2BOOSTVOL_6DB (7 << 4) +#define AUXR2BOOSTVOL_POS (0) +#define AUXR2BOOSTVOL_MASK (7) +#define AUXR2BOOSTVOL_DISABLED (0) // Default value +#define AUXR2BOOSTVOL_N12DB (1) +#define AUXR2BOOSTVOL_N9DB (2) +#define AUXR2BOOSTVOL_N6DB (3) +#define AUXR2BOOSTVOL_N3DB (4) +#define AUXR2BOOSTVOL_0DB (5) +#define AUXR2BOOSTVOL_3DB (6) +#define AUXR2BOOSTVOL_6DB (7) + +// R49 REG_OUTPUT +#define DACL2RMIX (1 << 6) +#define DACR2LMIX (1 << 5) +#define OUT4BOOST (1 << 4) +#define OUT3BOOST (1 << 3) +#define SPKBOOST (1 << 2) +#define TSDEN (1 << 1) +#define VROI (1) + +// R50 REG_LEFT_MIXER +#define AUXLMIXVOL_POS (6) +#define AUXLMIXVOL_MASK (7) +#define AUXLMIXVOL_N15DB (0) // Default value +#define AUXLMIXVOL_N12DB (1 << 6) +#define AUXLMIXVOL_N9DB (2 << 6) +#define AUXLMIXVOL_N6DB (3 << 6) +#define AUXLMIXVOL_N3DB (4 << 6) +#define AUXLMIXVOL_0DB (5 << 6) +#define AUXLMIXVOL_3DB (6 << 6) +#define AUXLMIXVOL_6DB (7 << 6) +#define AUXL2LMIX (1 << 5) +#define BYPLMIXVOL_POS (2) +#define BYPLMIXVOL_MASK (7) +#define BYPLMIXVOL_N15DB (0) // Default value +#define BYPLMIXVOL_N12DB (1 << 2) +#define BYPLMIXVOL_N9DB (2 << 2) +#define BYPLMIXVOL_N6DB (3 << 2) +#define BYPLMIXVOL_N3DB (4 << 2) +#define BYPLMIXVOL_0DB (5 << 2) +#define BYPLMIXVOL_3DB (6 << 2) +#define BYPLMIXVOL_6DB (7 << 2) +#define BYPL2LMIX (1 << 1) +#define DACL2LMIX (1) + +// R51 REG_RIGHT_MIXER +#define AUXRMIXVOL_POS (6) +#define AUXRMIXVOL_MASK (7) +#define AUXRMIXVOL_N15DB (0) // Default value +#define AUXRMIXVOL_N12DB (1 << 6) +#define AUXRMIXVOL_N9DB (2 << 6) +#define AUXRMIXVOL_N6DB (3 << 6) +#define AUXRMIXVOL_N3DB (4 << 6) +#define AUXRMIXVOL_0DB (5 << 6) +#define AUXRMIXVOL_3DB (6 << 6) +#define AUXRMIXVOL_6DB (7 << 6) +#define AUXR2RMIX (1 << 5) +#define BYPRMIXVOL_POS (2) +#define BYPRMIXVOL_MASK (7) +#define BYPRMIXVOL_N15DB (0) // Default value +#define BYPRMIXVOL_N12DB (1 << 2) +#define BYPRMIXVOL_N9DB (2 << 2) +#define BYPRMIXVOL_N6DB (3 << 2) +#define BYPRMIXVOL_N3DB (4 << 2) +#define BYPRMIXVOL_0DB (5 << 2) +#define BYPRMIXVOL_3DB (6 << 2) +#define BYPRMIXVOL_6DB (7 << 2) +#define BYPR2RMIX (1 << 1) +#define DACR2RMIX (1) + +// R52 - R55 REG_LOUT1_VOL - REG_ROUT2_VOL +#define HPVU (1 << 8) +#define SPKVU (1 << 8) +#define LOUT1ZC (1 << 7) +#define LOUT1MUTE (1 << 6) +#define ROUT1ZC (1 << 7) +#define ROUT1MUTE (1 << 6) +#define LOUT2ZC (1 << 7) +#define LOUT2MUTE (1 << 6) +#define ROUT2ZC (1 << 7) +#define ROUT2MUTE (1 << 6) +#define VOL_POS (0) +#define VOL_MASK (63) + +// R56 REG_OUT3_MIXER +#define OUT3MUTE (1 << 6) +#define OUT4_2OUT3 (1 << 3) +#define BYPL2OUT3 (1 << 2) +#define LMIX2OUT3 (1 << 1) +#define LDAC2OUT3 (1) + +// R57 REG_OUT4_MIXER +#define OUT4MUTE (1 << 6) +#define HALFSIG (1 << 5) +#define LMIX2OUT4 (1 << 4) +#define LDAC2OUT4 (1 << 3) +#define BYPR2OUT4 (1 << 2) +#define RMIX2OUT4 (1 << 1) +#define RDAC2OUT4 (1) + +static rt_uint16_t wm8978_regval_tbl[58] = +{ + 0X0000, 0X0000, 0X0000, 0X0000, 0X0050, 0X0000, 0X0140, 0X0000, + 0X0000, 0X0000, 0X0000, 0X00FF, 0X00FF, 0X0000, 0X0100, 0X00FF, + 0X00FF, 0X0000, 0X012C, 0X002C, 0X002C, 0X002C, 0X002C, 0X0000, + 0X0032, 0X0000, 0X0000, 0X0000, 0X0000, 0X0000, 0X0000, 0X0000, + 0X0038, 0X000B, 0X0032, 0X0000, 0X0008, 0X000C, 0X0093, 0X00E9, + 0X0000, 0X0000, 0X0000, 0X0000, 0X0003, 0X0010, 0X0010, 0X0100, + 0X0100, 0X0002, 0X0001, 0X0001, 0X0039, 0X0039, 0X0039, 0X0039, + 0X0001, 0X0001 +}; + +static void wm8978_write_reg(struct rt_i2c_bus_device *dev, rt_uint16_t s_data) +{ + struct rt_i2c_msg msg; + rt_uint8_t send_buffer[2]; + RT_ASSERT(dev != RT_NULL); + /* store temp */ + wm8978_regval_tbl[s_data >> 9] = s_data & 0x1FF; + send_buffer[0] = (rt_uint8_t)(s_data >> 8); + send_buffer[1] = (rt_uint8_t)(s_data); + msg.addr = 0x1A; + msg.flags = RT_I2C_WR; + msg.len = 2; + msg.buf = send_buffer; + rt_i2c_transfer(dev, &msg, 1); +} + +static rt_uint16_t wm8978_read_reg(struct rt_i2c_bus_device *dev, rt_uint16_t reg) +{ + return wm8978_regval_tbl[reg >> 9]; +} + +/** + * @brief Init WM8978 Codec device. + * @param dev: I2C device handle + * @retval RT_EOK if correct communication, else wrong communication + */ +void wm8978_player_start(struct rt_i2c_bus_device *dev) +{ + wm8978_reset(dev); + + /* 1.5x boost power up sequence,Mute all outputs. */ + wm8978_write_reg(dev, REG_LOUT1_VOL | LOUT1MUTE); + wm8978_write_reg(dev, REG_ROUT1_VOL | ROUT1MUTE); + wm8978_write_reg(dev, REG_LOUT2_VOL | LOUT2MUTE); + wm8978_write_reg(dev, REG_ROUT2_VOL | ROUT2MUTE); + + /* Enable unused output chosen from L/ROUT2, OUT3 or OUT4. */ + wm8978_write_reg(dev, REG_POWER_MANAGEMENT3 | OUT4EN); + /* Set BUFDCOPEN=1, BIASEN=1 and BUFIOEN=1 in register R1 */ + wm8978_write_reg(dev, REG_POWER_MANAGEMENT1 | BUFDCOPEN | BUFIOEN | BIASEN); + /* Set SPKBOOST=1 in register R49. */ + wm8978_write_reg(dev, REG_OUTPUT | SPKBOOST); + /* Set VMIDSEL[1:0] to required value in register R1. */ + wm8978_write_reg(dev, REG_POWER_MANAGEMENT1 | BUFDCOPEN | BUFIOEN | VMIDSEL_75K); + /* Set L/RMIXEN=1 and DACENL/R=1 in register R3.*/ + wm8978_write_reg(dev, REG_POWER_MANAGEMENT3 | LMIXEN | RMIXEN | DACENL | DACENR); + /* Set BIASEN=1 in register R1. */ + wm8978_write_reg(dev, REG_POWER_MANAGEMENT1 | BUFDCOPEN | BUFIOEN | VMIDSEL_75K); + /* Set L/ROUT2EN=1 in register R3. */ + wm8978_write_reg(dev, REG_POWER_MANAGEMENT3 | LMIXEN | RMIXEN | DACENL | DACENR | LOUT2EN | ROUT2EN); + /* Enable other outputs as required. */ + wm8978_write_reg(dev, REG_POWER_MANAGEMENT2 | LOUT1EN | ROUT1EN | BOOSTENL | BOOSTENR | INPPGAENL | INPPGAENR); + wm8978_write_reg(dev, REG_POWER_MANAGEMENT2 | LOUT1EN | ROUT1EN | BOOSTENL | BOOSTENR | INPPGAENL | INPPGAENR | ADCENL | ADCENR); + + /* Digital inferface setup. */ + wm8978_write_reg(dev, REG_AUDIO_INTERFACE | BCP_NORMAL | LRP_NORMAL | WL_16BITS | FMT_I2S); + + wm8978_write_reg(dev, REG_ADDITIONAL | WM_SR_8KHZ); + + wm8978_write_reg(dev, REG_POWER_MANAGEMENT1 | BUFDCOPEN | BUFIOEN | VMIDSEL_75K | MICBEN | BIASEN); + wm8978_write_reg(dev, REG_CLOCK_GEN | CLKSEL_MCLK | MCLK_DIV1); + + /* Enable DAC 128x oversampling. */ + wm8978_write_reg(dev, REG_DAC | DACOSR128); + /* Set LOUT2/ROUT2 in BTL operation. */ + wm8978_write_reg(dev, REG_BEEP | INVROUT2); + wm8978_DAC_enabled(dev, 1); + + /* Set output volume. */ + wm8978_set_volume(dev, 50); +} + +void wm8978_record_start(struct rt_i2c_bus_device *dev) +{ + wm8978_write_reg(dev, REG_POWER_MANAGEMENT1 | MICBEN | BIASEN | VMIDSEL_5K); + wm8978_write_reg(dev, REG_POWER_MANAGEMENT2 | ROUT1EN | LOUT1EN | BOOSTENR | BOOSTENL); + wm8978_write_reg(dev, REG_POWER_MANAGEMENT3 | LOUT2EN | ROUT2EN | RMIXEN | LMIXEN); + /* mclk be supplied by outside */ + wm8978_write_reg(dev, REG_CLOCK_GEN); + + wm8978_write_reg(dev, (REG_BEEP | BEEPVOL_N3DB)); + wm8978_write_reg(dev, (REG_LEFT_ADC_BOOST | PGABOOSTL)); + wm8978_write_reg(dev, (REG_RIGHT_ADC_BOOST | PGABOOSTR)); + wm8978_write_reg(dev, (REG_OUTPUT | TSDEN | SPKBOOST)); + wm8978_write_reg(dev, (REG_DAC | RMIXEN)); + wm8978_write_reg(dev, (REG_ADC | ADCOSR128)); + wm8978_ADC_enabled(dev, 1); + wm8978_DAC_enabled(dev, 0); + wm8978_mic_enabled(dev, 1); + wm8978_linein_enabled(dev, 1); + wm8978_aux_enabled(dev, 0); + wm8978_output_set(dev, 0, 0); + wm8978_aux_gain(dev, 5); + wm8978_mic_gain(dev, 50); +} + +rt_err_t wm8978_init(struct rt_i2c_bus_device *dev) +{ + wm8978_reset(dev); + wm8978_write_reg(dev, REG_POWER_MANAGEMENT1 | MICBEN | BIASEN | VMIDSEL_5K); + wm8978_write_reg(dev, REG_POWER_MANAGEMENT2 | ROUT1EN | LOUT1EN | BOOSTENR | BOOSTENL); + wm8978_write_reg(dev, REG_POWER_MANAGEMENT3 | LOUT2EN | ROUT2EN | RMIXEN | LMIXEN); + /* mclk be supplied by outside */ + wm8978_write_reg(dev, REG_CLOCK_GEN); + + wm8978_write_reg(dev, (REG_BEEP | BEEPVOL_N3DB)); + wm8978_write_reg(dev, (REG_LEFT_ADC_BOOST | PGABOOSTL)); + wm8978_write_reg(dev, (REG_RIGHT_ADC_BOOST | PGABOOSTR)); + wm8978_write_reg(dev, (REG_OUTPUT | TSDEN | SPKBOOST)); + wm8978_write_reg(dev, (REG_DAC | RMIXEN)); + wm8978_write_reg(dev, (REG_ADC | ADCOSR128)); + + wm8978_interface_cfg(dev, I2S_FOMAT_SELECT, 16); + wm8978_mic_enabled(dev, 0); + + return RT_EOK; +} + +void wm8978_DAC_enabled(struct rt_i2c_bus_device *dev, rt_bool_t bool) +{ + rt_uint16_t value; + + value = wm8978_read_reg(dev, REG_POWER_MANAGEMENT3); + bool ? (value |= 3) : (value &= ~3); + wm8978_write_reg(dev, REG_POWER_MANAGEMENT3 | value); +} + +void wm8978_ADC_enabled(struct rt_i2c_bus_device *dev, rt_bool_t bool) +{ + rt_uint16_t value; + + value = wm8978_read_reg(dev, REG_POWER_MANAGEMENT2); + bool ? (value |= 3) : (value &= ~3); + wm8978_write_reg(dev, REG_POWER_MANAGEMENT2 | value); +} + +void wm8978_mic_enabled(struct rt_i2c_bus_device *dev, rt_bool_t bool) +{ + rt_uint16_t value; + + value = wm8978_read_reg(dev, REG_POWER_MANAGEMENT2); + bool ? (value |= 3 << 2) : (value &= ~(3 << 2)); + wm8978_write_reg(dev, REG_POWER_MANAGEMENT2 | value); + + value = wm8978_read_reg(dev, REG_INPUT); + bool ? (value |= 3 << 4 | 3) : (value &= ~(3 << 4 | 3)); + wm8978_write_reg(dev, REG_INPUT | value); +} + +void wm8978_linein_gain(struct rt_i2c_bus_device *dev, rt_uint8_t value) +{ + rt_uint16_t regval; + + value &= 0x7; + /* set left boost */ + regval = wm8978_read_reg(dev, REG_LEFT_ADC_BOOST); + regval &= ~(7 << 4); + wm8978_write_reg(dev, REG_LEFT_ADC_BOOST | regval | value << 4); + + /* set right boost */ + regval = wm8978_read_reg(dev, REG_RIGHT_ADC_BOOST); + regval &= ~(7 << 4); + wm8978_write_reg(dev, REG_RIGHT_ADC_BOOST | regval | value << 4); + +} + +void wm8978_aux_gain(struct rt_i2c_bus_device *dev, rt_uint8_t value) +{ + rt_uint16_t regval; + + value &= 0x7; + /* set left boost */ + regval = wm8978_read_reg(dev, REG_LEFT_ADC_BOOST); + regval &= ~(7 << 0); + wm8978_write_reg(dev, REG_LEFT_ADC_BOOST | regval | value << 0); + + /* set right boost */ + regval = wm8978_read_reg(dev, REG_RIGHT_ADC_BOOST); + regval &= ~(7 << 0); + wm8978_write_reg(dev, REG_RIGHT_ADC_BOOST | regval | value << 0); + +} + +void wm8978_mic_gain(struct rt_i2c_bus_device *dev, rt_uint8_t gain) +{ + gain &= 0X3F; + wm8978_write_reg(dev, REG_LEFT_PGA_GAIN | gain); + wm8978_write_reg(dev, REG_RIGHT_PGA_GAIN | gain | 1 << 8); + +} +void wm8978_linein_enabled(struct rt_i2c_bus_device *dev, rt_bool_t bool) +{ + wm8978_linein_gain(dev, (bool ? L2_2BOOSTVOL_0DB : 0)); +} + +void wm8978_aux_enabled(struct rt_i2c_bus_device *dev, rt_bool_t bool) +{ + wm8978_linein_gain(dev, (bool ? AUXL2BOOSTVOL_6DB : 0)); +} + +void wm8978_output_set(struct rt_i2c_bus_device *dev, rt_bool_t dacen, rt_bool_t bypass) +{ + rt_uint16_t regval = 0; + if (dacen) + { + regval |= 1 << 0; + } + if (bypass) + { + regval |= 1 << 1; + regval |= 5 << 2; + } + wm8978_write_reg(dev, REG_LEFT_MIXER | regval); + wm8978_write_reg(dev, REG_RIGHT_MIXER | regval); +} + +void wm8978_hpvol_set(struct rt_i2c_bus_device *dev, rt_uint8_t volume) +{ + volume &= 0X3F; + if (volume == 0) + { + volume |= 1 << 6;//mute mode + } + wm8978_write_reg(dev, REG_LOUT1_VOL | volume); + wm8978_write_reg(dev, REG_ROUT1_VOL | volume | (1 << 8)); +} + +void wm8978_spkvol_set(struct rt_i2c_bus_device *dev, rt_uint8_t volume) +{ + volume &= 0X3F; + if (volume == 0) + { + volume |= 1 << 6;//mute mode + } + wm8978_write_reg(dev, REG_LOUT2_VOL | volume); + wm8978_write_reg(dev, REG_ROUT2_VOL | volume | (1 << 8)); +} + +/** + * @brief Set WM8978 DAC volume level. + * @param dev: I2C device handle + * @param vol: volume level(0 ~ 99) + * @retval RT_EOK if correct communication, else wrong communication + */ +int wm8978_set_volume(struct rt_i2c_bus_device *dev, int vol) +{ + vol = 63 * vol / 100; + vol = (vol & VOL_MASK) << VOL_POS; + wm8978_write_reg(dev, REG_LOUT1_VOL | vol); + wm8978_write_reg(dev, REG_ROUT1_VOL | HPVU | vol); + wm8978_write_reg(dev, REG_LOUT2_VOL | vol); + wm8978_write_reg(dev, REG_ROUT2_VOL | SPKVU | vol); + + return RT_EOK; +} + +void wm8978_interface_cfg(struct rt_i2c_bus_device *dev, enum data_fomat_select fmt, rt_uint32_t bitBand) +{ + rt_uint16_t temp = 0; + + switch (fmt) + { + case RIGHT_FOMAT_SELECT: + temp = FMT_RIGHT_JUSTIFIED; + break; + case LEFT_FOMAT_SELECT: + temp = FMT_LEFT_JUSTIFIED; + break; + case I2S_FOMAT_SELECT: + temp = FMT_I2S; + break; + case PCM_FOMAT_SELECT: + temp = FMT_PCM; + break; + default: + break; + } + + switch (bitBand) + { + case 16: + temp |= WL_16BITS; + break; + case 20: + temp |= WL_20BITS; + break; + case 24: + temp |= WL_24BITS; + break; + case 32: + temp |= WL_32BITS; + break; + default: + break; + } + + wm8978_write_reg(dev, REG_AUDIO_INTERFACE | temp); +} + +void wm8978_reset(struct rt_i2c_bus_device *dev) +{ + wm8978_write_reg(dev, REG_SOFTWARE_RESET); +} + +void wm8978_mute_enabled(struct rt_i2c_bus_device *dev, rt_bool_t enable) +{ + wm8978_write_reg(dev, REG_POWER_MANAGEMENT1 | (enable ? BIASEN : 0)); +} + +rt_err_t wm8978_set_EQ1(struct rt_i2c_bus_device *dev, rt_uint8_t freq, rt_uint8_t gain) +{ + rt_uint16_t temp = 0; + + if (freq > 3 || gain > 24) + { + return -RT_ERROR; + } + switch (freq) + { + case 0: + temp = EQ1C_80HZ; + break; + case 1: + temp = EQ1C_105HZ; + break; + case 2: + temp = EQ1C_135HZ; + break; + case 3: + temp = EQ1C_175HZ; + break; + default: + break; + } + + /* 0 - 24 as -12~+12dB */ + gain = 24 - gain; + temp |= gain; + + wm8978_write_reg(dev, REG_EQ1 | temp); + + return RT_EOK; +} + +rt_err_t wm8978_set_EQ2(struct rt_i2c_bus_device *dev, rt_uint8_t freq, rt_uint8_t gain) +{ + rt_uint16_t temp = 0; + + if (freq > 3 || gain > 24) + { + return -RT_ERROR; + } + switch (freq) + { + case 0: + temp = EQ2C_230HZ; + break; + case 1: + temp = EQ2C_300HZ; + break; + case 2: + temp = EQ2C_385HZ; + break; + case 3: + temp = EQ2C_500HZ; + break; + default: + break; + } + + /* 0 - 24 as -12~+12dB */ + gain = 24 - gain; + temp |= gain; + + wm8978_write_reg(dev, REG_EQ2 | temp); + + return RT_EOK; +} + +rt_err_t wm8978_set_EQ3(struct rt_i2c_bus_device *dev, rt_uint8_t freq, rt_uint8_t gain) +{ + rt_uint16_t temp = 0; + + if (freq > 3 || gain > 24) + { + return -RT_ERROR; + } + switch (freq) + { + case 0: + temp = EQ3C_650HZ; + break; + case 1: + temp = EQ3C_850HZ; + break; + case 2: + temp = EQ3C_1_1KHZ; + break; + case 3: + temp = EQ3C_1_4KHZ; + break; + default: + break; + } + + /* 0 - 24 as -12~+12dB */ + gain = 24 - gain; + temp |= gain; + + wm8978_write_reg(dev, REG_EQ3 | temp); + + return RT_EOK; +} + +rt_err_t wm8978_set_EQ4(struct rt_i2c_bus_device *dev, rt_uint8_t freq, rt_uint8_t gain) +{ + rt_uint16_t temp = 0; + + if (freq > 3 || gain > 24) + { + return -RT_ERROR; + } + switch (freq) + { + case 0: + temp = EQ4C_1_8KHZ; + break; + case 1: + temp = EQ4C_2_4KHZ; + break; + case 2: + temp = EQ4C_3_2KHZ; + break; + case 3: + temp = EQ4C_4_1KHZ; + break; + default: + break; + } + + /* 0 - 24 as -12~+12dB */ + gain = 24 - gain; + temp |= gain; + + wm8978_write_reg(dev, REG_EQ4 | temp); + + return RT_EOK; +} + +rt_err_t wm8978_set_EQ5(struct rt_i2c_bus_device *dev, rt_uint8_t freq, rt_uint8_t gain) +{ + rt_uint16_t temp = 0; + + if (freq > 3 || gain > 24) + { + return -RT_ERROR; + } + switch (freq) + { + case 0: + temp = EQ5C_5_3KHZ; + break; + case 1: + temp = EQ5C_6_9KHZ; + break; + case 2: + temp = EQ5C_9KHZ; + break; + case 3: + temp = EQ5C_11_7KHZ; + break; + default: + break; + } + + /* 0 - 24 as -12~+12dB */ + gain = 24 - gain; + temp |= gain; + + wm8978_write_reg(dev, REG_EQ5 | temp); + + return RT_EOK; +} + +void wm8978_3D_Set(struct rt_i2c_bus_device *dev, rt_uint8_t depth) +{ + wm8978_write_reg(dev, REG_3D | (depth & 0xf)); +} + diff --git a/bsp/stm32/stm32f429-atk-apollo/board/ports/audio/drv_wm8978.h b/bsp/stm32/stm32f429-atk-apollo/board/ports/audio/drv_wm8978.h new file mode 100644 index 0000000000..d385255f9c --- /dev/null +++ b/bsp/stm32/stm32f429-atk-apollo/board/ports/audio/drv_wm8978.h @@ -0,0 +1,58 @@ +/* + * Copyright (c) 2006-2018, RT-Thread Development Team + * + * SPDX-License-Identifier: Apache-2.0 + * + * Change Logs: + * Date Author Notes + * 2018-11-14 ZeroFree first implementation + * 2019-07-28 Ernest perfect player, add record and other APIs + */ + +#ifndef __DRV_WM8978_H__ +#define __DRV_WM8978_H__ + +#include <rtthread.h> +#include <rtdevice.h> + +enum data_fomat_select +{ + RIGHT_FOMAT_SELECT, + LEFT_FOMAT_SELECT, + I2S_FOMAT_SELECT, + PCM_FOMAT_SELECT, +}; + +rt_err_t wm8978_init(struct rt_i2c_bus_device *dev); +void wm8978_player_start(struct rt_i2c_bus_device *dev); +void wm8978_record_start(struct rt_i2c_bus_device *dev); + +int wm8978_set_volume(struct rt_i2c_bus_device *dev, int vol); + +void wm8978_reset(struct rt_i2c_bus_device *dev); +/* enable ADC/DAC */ +void wm8978_ADC_enabled(struct rt_i2c_bus_device *dev, rt_bool_t bool); +void wm8978_DAC_enabled(struct rt_i2c_bus_device *dev, rt_bool_t bool); + +void wm8978_mic_enabled(struct rt_i2c_bus_device *dev, rt_bool_t bool); +void wm8978_linein_enabled(struct rt_i2c_bus_device *dev, rt_bool_t bool); +void wm8978_aux_enabled(struct rt_i2c_bus_device *dev, rt_bool_t bool); +void wm8978_linein_gain(struct rt_i2c_bus_device *dev, rt_uint8_t value); +void wm8978_aux_gain(struct rt_i2c_bus_device *dev, rt_uint8_t value); +void wm8978_mic_gain(struct rt_i2c_bus_device *dev, rt_uint8_t gain); +void wm8978_output_set(struct rt_i2c_bus_device *dev, rt_bool_t dac, rt_bool_t bypass); +void wm8978_hpvol_set(struct rt_i2c_bus_device *dev, rt_uint8_t volume); +void wm8978_spkvol_set(struct rt_i2c_bus_device *dev, rt_uint8_t volume); + +/* set interface mode */ +void wm8978_interface_cfg(struct rt_i2c_bus_device *dev, enum data_fomat_select fmt, rt_uint32_t bitBand); + +void wm8978_mute_enabled(struct rt_i2c_bus_device *dev, rt_bool_t enable); +rt_err_t wm8978_set_EQ1(struct rt_i2c_bus_device *dev, rt_uint8_t freq, rt_uint8_t gain); +rt_err_t wm8978_set_EQ2(struct rt_i2c_bus_device *dev, rt_uint8_t freq, rt_uint8_t gain); +rt_err_t wm8978_set_EQ3(struct rt_i2c_bus_device *dev, rt_uint8_t freq, rt_uint8_t gain); +rt_err_t wm8978_set_EQ4(struct rt_i2c_bus_device *dev, rt_uint8_t freq, rt_uint8_t gain); +rt_err_t wm8978_set_EQ5(struct rt_i2c_bus_device *dev, rt_uint8_t freq, rt_uint8_t gain); +void wm8978_3D_Set(struct rt_i2c_bus_device *dev, rt_uint8_t depth); + +#endif |