diff options
| -rw-r--r-- | bsp/sep4020/Ext_SDRAM.ini | 40 | ||||
| -rw-r--r-- | bsp/sep4020/Memory.ini | 14 | ||||
| -rw-r--r-- | bsp/sep4020/application.c | 86 | ||||
| -rw-r--r-- | bsp/sep4020/board.c | 140 | ||||
| -rw-r--r-- | bsp/sep4020/board.h | 26 | ||||
| -rw-r--r-- | bsp/sep4020/project.uvopt | 2957 | ||||
| -rw-r--r-- | bsp/sep4020/project.uvproj | 1007 | ||||
| -rw-r--r-- | bsp/sep4020/rtconfig.h | 150 | ||||
| -rw-r--r-- | bsp/sep4020/rtthread-sep4020-rom.sct | 15 | ||||
| -rw-r--r-- | bsp/sep4020/rtthread-sep4020-sdram.sct | 15 | ||||
| -rw-r--r-- | bsp/sep4020/sep4020.h | 637 | ||||
| -rw-r--r-- | bsp/sep4020/startup.c | 132 | ||||
| -rw-r--r-- | libcpu/arm/sep4020/clk.c | 112 | ||||
| -rw-r--r-- | libcpu/arm/sep4020/context_rvds.S | 107 | ||||
| -rw-r--r-- | libcpu/arm/sep4020/cpu.c | 42 | ||||
| -rw-r--r-- | libcpu/arm/sep4020/interrupt.c | 107 | ||||
| -rw-r--r-- | libcpu/arm/sep4020/serial.c | 281 | ||||
| -rw-r--r-- | libcpu/arm/sep4020/serial.h | 56 | ||||
| -rw-r--r-- | libcpu/arm/sep4020/stack.c | 61 | ||||
| -rw-r--r-- | libcpu/arm/sep4020/start_rvds.S | 374 | ||||
| -rw-r--r-- | libcpu/arm/sep4020/trap.c | 66 |
21 files changed, 6425 insertions, 0 deletions
diff --git a/bsp/sep4020/Ext_SDRAM.ini b/bsp/sep4020/Ext_SDRAM.ini new file mode 100644 index 0000000000..19cb88911b --- /dev/null +++ b/bsp/sep4020/Ext_SDRAM.ini @@ -0,0 +1,40 @@ +/******************************************************************************/
+/* Ext_RAM.INI: External RAM (SDRAM) Initialization File */
+/******************************************************************************/
+// <<< Use Configuration Wizard in Context Menu >>> //
+/******************************************************************************/
+/* This file is part of the uVision/ARM development tools. */
+/* Copyright (c) 2005-2008 Keil Software. All rights reserved. */
+/* This software may only be used under the terms of a valid, current, */
+/* end user licence from KEIL for a compatible version of KEIL software */
+/* development tools. Nothing else gives you the right to use this software. */
+/******************************************************************************/
+
+
+FUNC void SetupForStart (void) {
+
+// <o> Program Entry Point
+ PC = 0x30000000;
+}
+
+
+FUNC void Init (void) {
+
+ _WDWORD(0x1000200C, 0x00000000); // Disable Watchdog
+
+ // Clock Setup
+
+ _WDWORD(0x10001000, 0x00fa00fa); //
+ _WDWORD(0x10001014, 0x00000001); //
+ _WDWORD(0x10001004, 0x00004009); //
+ _WDWORD(0x10001004, 0x0000C009); //
+ _WDWORD(0x11000018, 0x1E104177); //
+ _WDWORD(0x1100001c, 0x80001860); //
+
+
+}
+
+Init(); // Initialize memory
+LOAD build\rtthread-sep4020.axf INCREMENTAL // Download program
+SetupForStart(); // Setup for Running
+g, main // Goto Main
diff --git a/bsp/sep4020/Memory.ini b/bsp/sep4020/Memory.ini new file mode 100644 index 0000000000..205cc469ec --- /dev/null +++ b/bsp/sep4020/Memory.ini @@ -0,0 +1,14 @@ +/******************************************************************************/
+/* MEMORY.INI: Memory Debug Initialization File */
+/******************************************************************************/
+/* This file is part of the uVision/ARM development tools. */
+/* Copyright (c) 2005-2006 Keil Software. All rights reserved. */
+/* This software may only be used under the terms of a valid, current, */
+/* end user licence from KEIL for a compatible version of KEIL software */
+/* development tools. Nothing else gives you the right to use this software. */
+/******************************************************************************/
+
+MAP 0x00000000,0x0000FFFF READ EXEC // External ROM
+MAP 0x30000000,0x31FFFFFF READ WRITE // External RAM
+MAP 0x10000000,0x11000000 READ WRITE
+MAP 0x11000000,0x12000000 READ WRITE
diff --git a/bsp/sep4020/application.c b/bsp/sep4020/application.c new file mode 100644 index 0000000000..5245e52346 --- /dev/null +++ b/bsp/sep4020/application.c @@ -0,0 +1,86 @@ +/*
+ * File : application.c
+ * This file is part of RT-Thread RTOS
+ * COPYRIGHT (C) 2006, RT-Thread Development Team
+ *
+ * The license and distribution terms for this file may be
+ * found in the file LICENSE in this distribution or at
+ * http://www.rt-thread.org/license/LICENSE
+ *
+ * Change Logs:
+ * Date Author Notes
+ * 2009-01-05 Bernard the first version
+ */
+
+/**
+ * @addtogroup SEP4020
+ */
+/*@{*/
+
+#include <rtthread.h>
+#include "board.h"
+
+static void rt_thread_entry_led1(void* parameter)
+{
+ /* init led configuration */
+ /* rt_hw_led_init(); */
+
+ while (1)
+ {
+ /* led on */
+ //rt_kprintf("led1 on\r\n");
+ GPIO_PORTE_DATA |= 0x1<<3;
+ rt_thread_delay(50); /* sleep 0.5 second and switch to other thread */
+
+ /* led off */
+ //rt_kprintf("led1 off\r\n");
+ GPIO_PORTE_DATA &= ~(0x1<<3);
+ rt_thread_delay(50);
+ }
+}
+
+char thread_led2_stack[1024];
+struct rt_thread thread_led2;
+void rt_thread_entry_led2(void* parameter)
+{
+ unsigned int count=0;
+ while (1)
+ {
+ /* led on */
+ //rt_kprintf("led2 on,count : %d\r\n",count);
+ count++;
+ GPIO_PORTE_DATA |= 0x1<<4;
+ rt_thread_delay(RT_TICK_PER_SECOND);
+
+ /* led off */
+ //rt_kprintf("led2 off\r\n");
+ GPIO_PORTE_DATA &= ~(0x1<<4);
+ rt_thread_delay(RT_TICK_PER_SECOND);
+ }
+}
+
+int rt_application_init()
+{
+ rt_thread_t thread;
+
+ /* create led1 thread */
+ thread = rt_thread_create("led1",
+ rt_thread_entry_led1, RT_NULL,
+ 512,
+ 20, 5);
+ if (thread != RT_NULL)
+ rt_thread_startup(thread);
+
+ //------- init led2 thread
+ rt_thread_init(&thread_led2,
+ "led2",
+ rt_thread_entry_led2,
+ RT_NULL,
+ &thread_led2_stack[0],
+ sizeof(thread_led2_stack),10,10);
+ rt_thread_startup(&thread_led2);
+
+ return 0;
+}
+
+/*@}*/
diff --git a/bsp/sep4020/board.c b/bsp/sep4020/board.c new file mode 100644 index 0000000000..162b491f25 --- /dev/null +++ b/bsp/sep4020/board.c @@ -0,0 +1,140 @@ +/* + * File : board.c + * This file is part of RT-Thread RTOS + * COPYRIGHT (C) 2006, RT-Thread Develop Team + * + * The license and distribution terms for this file may be + * found in the file LICENSE in this distribution or at + * http://openlab.rt-thread.com/license/LICENSE + * + * Change Logs: + * Date Author Notes + * 2006-08-23 Bernard first implementation + */ + +#include <rtthread.h> +#include <rthw.h> + +#include <sep4020.h> +#include "board.h"
+#include "serial.h" + +/** + * @addtogroup sep4020 + */ +/*@{*/
+ +extern rt_uint32_t rt_hw_get_clock(void);
+ +/* uart0 */
+#define UART0 ((struct uartport *)UART0BASE)
+struct serial_int_rx uart0_int_rx;
+struct serial_device uart0 =
+{
+ UART0,
+ &uart0_int_rx,
+ RT_NULL
+};
+struct rt_device uart0_device; +/** + * This is the timer interrupt service routine. + * @param vector the irq number for timer + */ +void rt_hw_timer_handler(int vector) +{
+ /* clear interrupt */
+ TIMER_T1ISCR; + /* increase a tick */ + rt_tick_increase(); +}
+ +/** + * This is the uart0 interrupt service routine. + * @param vector the irq number for uart0 + */
+void rt_serial_handler(int vector)
+{
+ rt_hw_serial_isr(&uart0_device);
+}
+
+/**
+ * This function will handle init uart.
+ */
+void rt_hw_uart_init(void)
+{
+ rt_uint32_t baud;
+ rt_uint32_t sysclock;
+
+ sysclock = rt_hw_get_clock();
+ /* caculate baud rate register */
+ baud = sysclock/16/BR;
+
+ /* LCR */
+ uart0.uart_device->lcr = 0x83;
+ /* DLBH, IER */
+ uart0.uart_device->dlbh_ier = (baud>>8)&0xff;;
+ /* DLBL */
+ uart0.uart_device->dlbl_rxfifo_txfifo = baud&0xff;
+ /* LCR */
+ uart0.uart_device->lcr = 0x03;
+ /* IER */
+ uart0.uart_device->dlbh_ier = 0x01;
+ /* FCR */
+ uart0.uart_device->iir_fcr = 0x00;
+
+ rt_hw_serial_register(&uart0_device, "uart0",
+ RT_DEVICE_FLAG_RDWR | RT_DEVICE_FLAG_INT_RX | RT_DEVICE_FLAG_STREAM,
+ &uart0);
+ /* install uart isr */
+ INTC_IER |= (1<<INT_UART0);
+
+ rt_hw_interrupt_install(INT_UART0, rt_serial_handler, RT_NULL);
+ rt_hw_interrupt_umask(INT_UART0);
+} +/** + * This function will init led on the board + */ +static void rt_hw_board_led_init(void) +{ + /* PE3 PE4 PE5 for led */
+ GPIO_PORTE_SEL |=0x38; /* GPIO */
+
+ GPIO_PORTE_DIR &= ~0x38; /* output*/
+
+ GPIO_PORTE_DATA &= ~0x38; /* low */ +}
+
+/**
+ * This function will init timer1 for system ticks
+ */
+ static void rt_hw_timer_init(void)
+ {
+ TIMER_T1CR = 0x06; /* reload mode and interrupt enable */
+ TIMER_T1LCR = 0xAFC80; /* 10ms under 72MHz 0xAFC80=720000 */
+
+ INTC_IER |= (1<<INT_TIMER1); /* interrupt enable */
+
+ rt_hw_interrupt_install(INT_TIMER1, rt_hw_timer_handler, RT_NULL);
+ rt_hw_interrupt_umask(INT_TIMER1);
+
+ TIMER_T1CR |= 0x01; /* enable the timer 1 */
+ } + +/** + * This function will initial sam7x board. + */ +void rt_hw_board_init() +{ + + /* init hardware uart */
+ rt_hw_uart_init();
+ rt_console_set_device("uart0"); + + /* init led */ + rt_hw_board_led_init(); + + /* init timer for tick */
+ rt_hw_timer_init(); + +} +/*@}*/ diff --git a/bsp/sep4020/board.h b/bsp/sep4020/board.h new file mode 100644 index 0000000000..1edc635bdc --- /dev/null +++ b/bsp/sep4020/board.h @@ -0,0 +1,26 @@ +/* + * File : board.h + * This file is part of RT-Thread RTOS + * COPYRIGHT (C) 2006, RT-Thread Develop Team + * + * The license and distribution terms for this file may be + * found in the file LICENSE in this distribution or at + * http://openlab.rt-thread.com/license/LICENSE + * + * Change Logs: + * Date Author Notes + * 2006-10-08 Bernard add board.h to this bsp + */ + +#ifndef __BOARD_H__ +#define __BOARD_H__ + +#include <rthw.h> +#include <rtthread.h>
+#include <sep4020.h> + +#define BR 115200 /* Baud Rate */ + +void rt_hw_board_init(void); + +#endif diff --git a/bsp/sep4020/project.uvopt b/bsp/sep4020/project.uvopt new file mode 100644 index 0000000000..b93f867bef --- /dev/null +++ b/bsp/sep4020/project.uvopt @@ -0,0 +1,2957 @@ +<?xml version="1.0" encoding="UTF-8" standalone="no" ?> +<ProjectOpt xmlns:xsi="http://www.w3.org/2001/XMLSchema-instance" xsi:noNamespaceSchemaLocation="project_opt.xsd"> + + <SchemaVersion>1.0</SchemaVersion> + + <Header>### uVision Project, (C) Keil Software</Header> + + <Extensions> + <cExt>*.c</cExt> + <aExt>*.s*; *.src; *.a*</aExt> + <oExt>*.obj</oExt> + <lExt>*.lib</lExt> + <tExt>*.txt; *.h; *.inc</tExt> + <pExt>*.plm</pExt> + <CppX>*.cpp</CppX> + </Extensions> + + <DaveTm> + <dwLowDateTime>0</dwLowDateTime> + <dwHighDateTime>0</dwHighDateTime> + </DaveTm> + + <Target> + <TargetName>RT-Thread/SEP4020</TargetName> + <ToolsetNumber>0x4</ToolsetNumber> + <ToolsetName>ARM-ADS</ToolsetName> + <TargetOption> + <CLKADS>14745600</CLKADS> + <OPTTT> + <gFlags>1</gFlags> + <BeepAtEnd>1</BeepAtEnd> + <RunSim>1</RunSim> + <RunTarget>0</RunTarget> + </OPTTT> + <OPTHX> + <HexSelection>1</HexSelection> + <FlashByte>65535</FlashByte> + <HexRangeLowAddress>0</HexRangeLowAddress> + <HexRangeHighAddress>0</HexRangeHighAddress> + <HexOffset>0</HexOffset> + </OPTHX> + <OPTLEX> + <PageWidth>79</PageWidth> + <PageLength>66</PageLength> + <TabStop>8</TabStop> + <ListingPath>.\build\</ListingPath> + </OPTLEX> + <ListingPage> + <CreateCListing>1</CreateCListing> + <CreateAListing>1</CreateAListing> + <CreateLListing>1</CreateLListing> + <CreateIListing>0</CreateIListing> + <AsmCond>1</AsmCond> + <AsmSymb>1</AsmSymb> + <AsmXref>0</AsmXref> + <CCond>1</CCond> + <CCode>0</CCode> + <CListInc>0</CListInc> + <CSymb>0</CSymb> + <LinkerCodeListing>0</LinkerCodeListing> + </ListingPage> + <OPTXL> + <LMap>1</LMap> + <LComments>1</LComments> + <LGenerateSymbols>1</LGenerateSymbols> + <LLibSym>1</LLibSym> + <LLines>1</LLines> + <LLocSym>1</LLocSym> + <LPubSym>1</LPubSym> + <LXref>0</LXref> + <LExpSel>0</LExpSel> + </OPTXL> + <OPTFL> + <tvExp>1</tvExp> + <tvExpOptDlg>0</tvExpOptDlg> + <IsCurrentTarget>1</IsCurrentTarget> + </OPTFL> + <CpuCode>0</CpuCode> + <DllOpt> + <SimDllName>SARM.DLL</SimDllName> + <SimDllArguments></SimDllArguments> + <SimDlgDllName>DARMSH.DLL</SimDlgDllName> + <SimDlgDllArguments></SimDlgDllArguments> + <TargetDllName>SARM.DLL</TargetDllName> + <TargetDllArguments></TargetDllArguments> + <TargetDlgDllName>TARMSH.DLL</TargetDlgDllName> + <TargetDlgDllArguments></TargetDlgDllArguments> + </DllOpt> + <DebugOpt> + <uSim>0</uSim> + <uTrg>1</uTrg> + <sLdApp>1</sLdApp> + <sGomain>0</sGomain> + <sRbreak>1</sRbreak> + <sRwatch>1</sRwatch> + <sRmem>1</sRmem> + <sRfunc>1</sRfunc> + <sRbox>1</sRbox> + <tLdApp>0</tLdApp> + <tGomain>0</tGomain> + <tRbreak>0</tRbreak> + <tRwatch>1</tRwatch> + <tRmem>1</tRmem> + <tRfunc>0</tRfunc> + <tRbox>1</tRbox> + <sRunDeb>0</sRunDeb> + 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<OtherWinName></OtherWinName> + <WinType>1</WinType> + <DockType>2</DockType> + <DockLocation>2</DockLocation> + <Pinned>0</Pinned> + <DockedRect_top>76</DockedRect_top> + <DockedRect_left>1070</DockedRect_left> + <DockedRect_bottom>511</DockedRect_bottom> + <DockedRect_right>1280</DockedRect_right> + <FloatingRect_top>0</FloatingRect_top> + <FloatingRect_left>0</FloatingRect_left> + <FloatingRect_bottom>600</FloatingRect_bottom> + <FloatingRect_right>250</FloatingRect_right> + <ContainerPercent>100</ContainerPercent> + <ActiveTab>0</ActiveTab> + <Visible>0</Visible> + <Dynamic>0</Dynamic> + </Window> + <Window> + <WinId>35886</WinId> + <ItemNo>29</ItemNo> + <Name>not set</Name> + <AnchorWinID>35885</AnchorWinID> + <AnchorWinName>???</AnchorWinName> + <OtherWinID>0</OtherWinID> + <OtherWinName></OtherWinName> + <WinType>1</WinType> + <DockType>4</DockType> + <DockLocation>2</DockLocation> + <Pinned>0</Pinned> + <DockedRect_top>76</DockedRect_top> + <DockedRect_left>1070</DockedRect_left> + <DockedRect_bottom>511</DockedRect_bottom> + <DockedRect_right>1280</DockedRect_right> + <FloatingRect_top>0</FloatingRect_top> + <FloatingRect_left>0</FloatingRect_left> + <FloatingRect_bottom>600</FloatingRect_bottom> + <FloatingRect_right>250</FloatingRect_right> + <ContainerPercent>100</ContainerPercent> + <ActiveTab>0</ActiveTab> + <Visible>0</Visible> + <Dynamic>0</Dynamic> + </Window> + <Window> + <WinId>35887</WinId> + <ItemNo>30</ItemNo> + <Name>not set</Name> + <AnchorWinID>35886</AnchorWinID> + <AnchorWinName>???</AnchorWinName> + <OtherWinID>0</OtherWinID> + <OtherWinName></OtherWinName> + <WinType>1</WinType> + <DockType>4</DockType> + <DockLocation>2</DockLocation> + <Pinned>0</Pinned> + <DockedRect_top>76</DockedRect_top> + <DockedRect_left>1070</DockedRect_left> + <DockedRect_bottom>511</DockedRect_bottom> + <DockedRect_right>1280</DockedRect_right> + <FloatingRect_top>0</FloatingRect_top> + <FloatingRect_left>0</FloatingRect_left> + <FloatingRect_bottom>600</FloatingRect_bottom> + <FloatingRect_right>250</FloatingRect_right> + <ContainerPercent>100</ContainerPercent> + <ActiveTab>0</ActiveTab> + <Visible>0</Visible> + <Dynamic>0</Dynamic> + </Window> + <Window> + <WinId>35888</WinId> + <ItemNo>31</ItemNo> + <Name>not set</Name> + <AnchorWinID>35887</AnchorWinID> + <AnchorWinName>???</AnchorWinName> + <OtherWinID>0</OtherWinID> + <OtherWinName></OtherWinName> + <WinType>1</WinType> + <DockType>4</DockType> + <DockLocation>2</DockLocation> + <Pinned>0</Pinned> + <DockedRect_top>76</DockedRect_top> + <DockedRect_left>1070</DockedRect_left> + <DockedRect_bottom>511</DockedRect_bottom> + <DockedRect_right>1280</DockedRect_right> + <FloatingRect_top>0</FloatingRect_top> + <FloatingRect_left>0</FloatingRect_left> + <FloatingRect_bottom>600</FloatingRect_bottom> + <FloatingRect_right>250</FloatingRect_right> + <ContainerPercent>100</ContainerPercent> + <ActiveTab>0</ActiveTab> + <Visible>0</Visible> + <Dynamic>0</Dynamic> + </Window> + <Window> + <WinId>35889</WinId> + <ItemNo>32</ItemNo> + <Name>not set</Name> + <AnchorWinID>35888</AnchorWinID> + <AnchorWinName>???</AnchorWinName> + <OtherWinID>0</OtherWinID> + <OtherWinName></OtherWinName> + <WinType>1</WinType> + <DockType>4</DockType> + <DockLocation>2</DockLocation> + <Pinned>0</Pinned> + <DockedRect_top>76</DockedRect_top> + <DockedRect_left>1070</DockedRect_left> + <DockedRect_bottom>511</DockedRect_bottom> + <DockedRect_right>1280</DockedRect_right> + <FloatingRect_top>0</FloatingRect_top> + <FloatingRect_left>0</FloatingRect_left> + <FloatingRect_bottom>600</FloatingRect_bottom> + <FloatingRect_right>250</FloatingRect_right> + <ContainerPercent>100</ContainerPercent> + <ActiveTab>0</ActiveTab> + <Visible>0</Visible> + <Dynamic>0</Dynamic> + </Window> + <Window> + <WinId>35890</WinId> + <ItemNo>33</ItemNo> + <Name>not set</Name> + <AnchorWinID>35889</AnchorWinID> + <AnchorWinName>???</AnchorWinName> + <OtherWinID>0</OtherWinID> + <OtherWinName></OtherWinName> + <WinType>1</WinType> + <DockType>4</DockType> + <DockLocation>2</DockLocation> + <Pinned>0</Pinned> + <DockedRect_top>76</DockedRect_top> + <DockedRect_left>1070</DockedRect_left> + <DockedRect_bottom>511</DockedRect_bottom> + <DockedRect_right>1280</DockedRect_right> + <FloatingRect_top>0</FloatingRect_top> + <FloatingRect_left>0</FloatingRect_left> + <FloatingRect_bottom>600</FloatingRect_bottom> + <FloatingRect_right>250</FloatingRect_right> + <ContainerPercent>100</ContainerPercent> + <ActiveTab>0</ActiveTab> + <Visible>0</Visible> + <Dynamic>0</Dynamic> + </Window> + <Window> + <WinId>35891</WinId> + <ItemNo>34</ItemNo> + <Name>not set</Name> + <AnchorWinID>35890</AnchorWinID> + <AnchorWinName>???</AnchorWinName> + <OtherWinID>0</OtherWinID> + <OtherWinName></OtherWinName> + <WinType>1</WinType> + <DockType>4</DockType> + <DockLocation>2</DockLocation> + <Pinned>0</Pinned> + <DockedRect_top>76</DockedRect_top> + <DockedRect_left>1070</DockedRect_left> + <DockedRect_bottom>511</DockedRect_bottom> + <DockedRect_right>1280</DockedRect_right> + <FloatingRect_top>0</FloatingRect_top> + <FloatingRect_left>0</FloatingRect_left> + <FloatingRect_bottom>600</FloatingRect_bottom> + <FloatingRect_right>250</FloatingRect_right> + <ContainerPercent>100</ContainerPercent> + <ActiveTab>0</ActiveTab> + <Visible>0</Visible> + <Dynamic>0</Dynamic> + </Window> + <Window> + <WinId>35892</WinId> + <ItemNo>35</ItemNo> + <Name>not set</Name> + <AnchorWinID>35891</AnchorWinID> + <AnchorWinName>???</AnchorWinName> + <OtherWinID>0</OtherWinID> + <OtherWinName></OtherWinName> + <WinType>1</WinType> + <DockType>4</DockType> + <DockLocation>2</DockLocation> + <Pinned>0</Pinned> + <DockedRect_top>76</DockedRect_top> + <DockedRect_left>1070</DockedRect_left> + <DockedRect_bottom>511</DockedRect_bottom> + <DockedRect_right>1280</DockedRect_right> + <FloatingRect_top>0</FloatingRect_top> + <FloatingRect_left>0</FloatingRect_left> + <FloatingRect_bottom>600</FloatingRect_bottom> + <FloatingRect_right>250</FloatingRect_right> + <ContainerPercent>100</ContainerPercent> + <ActiveTab>0</ActiveTab> + <Visible>0</Visible> + <Dynamic>0</Dynamic> + </Window> + <Window> + <WinId>35893</WinId> + <ItemNo>36</ItemNo> + <Name>not set</Name> + <AnchorWinID>35892</AnchorWinID> + <AnchorWinName>???</AnchorWinName> + <OtherWinID>0</OtherWinID> + <OtherWinName></OtherWinName> + <WinType>1</WinType> + <DockType>4</DockType> + <DockLocation>2</DockLocation> + <Pinned>0</Pinned> + <DockedRect_top>76</DockedRect_top> + <DockedRect_left>1070</DockedRect_left> + <DockedRect_bottom>511</DockedRect_bottom> + <DockedRect_right>1280</DockedRect_right> + <FloatingRect_top>0</FloatingRect_top> + <FloatingRect_left>0</FloatingRect_left> + <FloatingRect_bottom>600</FloatingRect_bottom> + <FloatingRect_right>250</FloatingRect_right> + <ContainerPercent>100</ContainerPercent> + <ActiveTab>0</ActiveTab> + <Visible>0</Visible> + <Dynamic>0</Dynamic> + </Window> + <Window> + <WinId>35894</WinId> + <ItemNo>37</ItemNo> + <Name>not set</Name> + <AnchorWinID>35893</AnchorWinID> + <AnchorWinName>???</AnchorWinName> + <OtherWinID>0</OtherWinID> + <OtherWinName></OtherWinName> + <WinType>1</WinType> + <DockType>4</DockType> + <DockLocation>2</DockLocation> + <Pinned>0</Pinned> + <DockedRect_top>76</DockedRect_top> + <DockedRect_left>1070</DockedRect_left> + <DockedRect_bottom>511</DockedRect_bottom> + <DockedRect_right>1280</DockedRect_right> + <FloatingRect_top>0</FloatingRect_top> + <FloatingRect_left>0</FloatingRect_left> + <FloatingRect_bottom>600</FloatingRect_bottom> + <FloatingRect_right>250</FloatingRect_right> + <ContainerPercent>100</ContainerPercent> + <ActiveTab>0</ActiveTab> + <Visible>0</Visible> + <Dynamic>0</Dynamic> + </Window> + <Window> + <WinId>35895</WinId> + <ItemNo>38</ItemNo> + <Name>not set</Name> + <AnchorWinID>35894</AnchorWinID> + <AnchorWinName>???</AnchorWinName> + <OtherWinID>0</OtherWinID> + <OtherWinName></OtherWinName> + <WinType>1</WinType> + <DockType>4</DockType> + <DockLocation>2</DockLocation> + <Pinned>0</Pinned> + <DockedRect_top>76</DockedRect_top> + <DockedRect_left>1070</DockedRect_left> + <DockedRect_bottom>511</DockedRect_bottom> + <DockedRect_right>1280</DockedRect_right> + <FloatingRect_top>0</FloatingRect_top> + <FloatingRect_left>0</FloatingRect_left> + <FloatingRect_bottom>600</FloatingRect_bottom> + <FloatingRect_right>250</FloatingRect_right> + <ContainerPercent>100</ContainerPercent> + <ActiveTab>0</ActiveTab> + <Visible>0</Visible> + <Dynamic>0</Dynamic> + </Window> + <Window> + <WinId>35896</WinId> + <ItemNo>39</ItemNo> + <Name>not set</Name> + <AnchorWinID>35895</AnchorWinID> + <AnchorWinName>???</AnchorWinName> + <OtherWinID>0</OtherWinID> + <OtherWinName></OtherWinName> + <WinType>1</WinType> + <DockType>4</DockType> + <DockLocation>2</DockLocation> + <Pinned>0</Pinned> + <DockedRect_top>76</DockedRect_top> + <DockedRect_left>1070</DockedRect_left> + <DockedRect_bottom>511</DockedRect_bottom> + <DockedRect_right>1280</DockedRect_right> + <FloatingRect_top>0</FloatingRect_top> + <FloatingRect_left>0</FloatingRect_left> + <FloatingRect_bottom>600</FloatingRect_bottom> + <FloatingRect_right>250</FloatingRect_right> + <ContainerPercent>100</ContainerPercent> + <ActiveTab>0</ActiveTab> + <Visible>0</Visible> + <Dynamic>0</Dynamic> + </Window> + <Window> + <WinId>35897</WinId> + <ItemNo>40</ItemNo> + <Name>not set</Name> + <AnchorWinID>35896</AnchorWinID> + <AnchorWinName>???</AnchorWinName> + <OtherWinID>0</OtherWinID> + <OtherWinName></OtherWinName> + <WinType>1</WinType> + <DockType>4</DockType> + <DockLocation>2</DockLocation> + <Pinned>0</Pinned> + <DockedRect_top>76</DockedRect_top> + <DockedRect_left>1070</DockedRect_left> + <DockedRect_bottom>511</DockedRect_bottom> + <DockedRect_right>1280</DockedRect_right> + <FloatingRect_top>0</FloatingRect_top> + <FloatingRect_left>0</FloatingRect_left> + <FloatingRect_bottom>600</FloatingRect_bottom> + <FloatingRect_right>250</FloatingRect_right> + <ContainerPercent>100</ContainerPercent> + <ActiveTab>0</ActiveTab> + <Visible>0</Visible> + <Dynamic>0</Dynamic> + </Window> + <Window> + <WinId>35898</WinId> + <ItemNo>41</ItemNo> + <Name>not set</Name> + <AnchorWinID>35897</AnchorWinID> + <AnchorWinName>???</AnchorWinName> + <OtherWinID>0</OtherWinID> + <OtherWinName></OtherWinName> + <WinType>1</WinType> + <DockType>4</DockType> + <DockLocation>2</DockLocation> + <Pinned>0</Pinned> + <DockedRect_top>76</DockedRect_top> + <DockedRect_left>1070</DockedRect_left> + <DockedRect_bottom>511</DockedRect_bottom> + <DockedRect_right>1280</DockedRect_right> + <FloatingRect_top>0</FloatingRect_top> + <FloatingRect_left>0</FloatingRect_left> + <FloatingRect_bottom>600</FloatingRect_bottom> + <FloatingRect_right>250</FloatingRect_right> + <ContainerPercent>100</ContainerPercent> + <ActiveTab>0</ActiveTab> + <Visible>0</Visible> + <Dynamic>0</Dynamic> + </Window> + <Window> + <WinId>35899</WinId> + <ItemNo>42</ItemNo> + <Name>not set</Name> + <AnchorWinID>35898</AnchorWinID> + <AnchorWinName>???</AnchorWinName> + <OtherWinID>0</OtherWinID> + <OtherWinName></OtherWinName> + <WinType>1</WinType> + <DockType>4</DockType> + <DockLocation>2</DockLocation> + <Pinned>0</Pinned> + <DockedRect_top>76</DockedRect_top> + <DockedRect_left>1070</DockedRect_left> + <DockedRect_bottom>511</DockedRect_bottom> + <DockedRect_right>1280</DockedRect_right> + <FloatingRect_top>0</FloatingRect_top> + <FloatingRect_left>0</FloatingRect_left> + <FloatingRect_bottom>600</FloatingRect_bottom> + <FloatingRect_right>250</FloatingRect_right> + <ContainerPercent>100</ContainerPercent> + <ActiveTab>0</ActiveTab> + <Visible>0</Visible> + <Dynamic>0</Dynamic> + </Window> + <Window> + <WinId>35900</WinId> + <ItemNo>43</ItemNo> + <Name>not set</Name> + <AnchorWinID>35899</AnchorWinID> + <AnchorWinName>???</AnchorWinName> + <OtherWinID>0</OtherWinID> + <OtherWinName></OtherWinName> + <WinType>1</WinType> + <DockType>4</DockType> + <DockLocation>2</DockLocation> + <Pinned>0</Pinned> + <DockedRect_top>76</DockedRect_top> + <DockedRect_left>1070</DockedRect_left> + <DockedRect_bottom>511</DockedRect_bottom> + <DockedRect_right>1280</DockedRect_right> + <FloatingRect_top>0</FloatingRect_top> + <FloatingRect_left>0</FloatingRect_left> + <FloatingRect_bottom>600</FloatingRect_bottom> + <FloatingRect_right>250</FloatingRect_right> + <ContainerPercent>100</ContainerPercent> + <ActiveTab>0</ActiveTab> + <Visible>0</Visible> + <Dynamic>0</Dynamic> + </Window> + <Window> + <WinId>35901</WinId> + <ItemNo>44</ItemNo> + <Name>not set</Name> + <AnchorWinID>35900</AnchorWinID> + <AnchorWinName>???</AnchorWinName> + <OtherWinID>0</OtherWinID> + <OtherWinName></OtherWinName> + <WinType>1</WinType> + <DockType>4</DockType> + <DockLocation>2</DockLocation> + <Pinned>0</Pinned> + <DockedRect_top>76</DockedRect_top> + <DockedRect_left>1070</DockedRect_left> + <DockedRect_bottom>511</DockedRect_bottom> + <DockedRect_right>1280</DockedRect_right> + <FloatingRect_top>0</FloatingRect_top> + <FloatingRect_left>0</FloatingRect_left> + <FloatingRect_bottom>600</FloatingRect_bottom> + <FloatingRect_right>250</FloatingRect_right> + <ContainerPercent>100</ContainerPercent> + <ActiveTab>0</ActiveTab> + <Visible>0</Visible> + <Dynamic>0</Dynamic> + </Window> + <Window> + <WinId>35902</WinId> + <ItemNo>45</ItemNo> + <Name>not set</Name> + <AnchorWinID>35901</AnchorWinID> + <AnchorWinName>???</AnchorWinName> + <OtherWinID>0</OtherWinID> + <OtherWinName></OtherWinName> + <WinType>1</WinType> + <DockType>4</DockType> + <DockLocation>2</DockLocation> + <Pinned>0</Pinned> + <DockedRect_top>76</DockedRect_top> + <DockedRect_left>1070</DockedRect_left> + <DockedRect_bottom>511</DockedRect_bottom> + <DockedRect_right>1280</DockedRect_right> + <FloatingRect_top>0</FloatingRect_top> + <FloatingRect_left>0</FloatingRect_left> + <FloatingRect_bottom>600</FloatingRect_bottom> + <FloatingRect_right>250</FloatingRect_right> + <ContainerPercent>100</ContainerPercent> + <ActiveTab>0</ActiveTab> + <Visible>0</Visible> + <Dynamic>0</Dynamic> + </Window> + <Window> + <WinId>35903</WinId> + <ItemNo>46</ItemNo> + <Name>not set</Name> + <AnchorWinID>35902</AnchorWinID> + <AnchorWinName>???</AnchorWinName> + <OtherWinID>0</OtherWinID> + <OtherWinName></OtherWinName> + <WinType>1</WinType> + <DockType>4</DockType> + <DockLocation>2</DockLocation> + <Pinned>0</Pinned> + <DockedRect_top>76</DockedRect_top> + <DockedRect_left>1070</DockedRect_left> + <DockedRect_bottom>511</DockedRect_bottom> + <DockedRect_right>1280</DockedRect_right> + <FloatingRect_top>0</FloatingRect_top> + <FloatingRect_left>0</FloatingRect_left> + <FloatingRect_bottom>600</FloatingRect_bottom> + <FloatingRect_right>250</FloatingRect_right> + <ContainerPercent>100</ContainerPercent> + <ActiveTab>0</ActiveTab> + <Visible>0</Visible> + <Dynamic>0</Dynamic> + </Window> + <Window> + <WinId>35904</WinId> + <ItemNo>47</ItemNo> + <Name>not set</Name> + <AnchorWinID>35903</AnchorWinID> + <AnchorWinName>???</AnchorWinName> + <OtherWinID>0</OtherWinID> + <OtherWinName></OtherWinName> + <WinType>1</WinType> + <DockType>4</DockType> + <DockLocation>2</DockLocation> + <Pinned>0</Pinned> + <DockedRect_top>76</DockedRect_top> + <DockedRect_left>1070</DockedRect_left> + <DockedRect_bottom>511</DockedRect_bottom> + <DockedRect_right>1280</DockedRect_right> + <FloatingRect_top>0</FloatingRect_top> + <FloatingRect_left>0</FloatingRect_left> + <FloatingRect_bottom>600</FloatingRect_bottom> + <FloatingRect_right>250</FloatingRect_right> + <ContainerPercent>100</ContainerPercent> + <ActiveTab>0</ActiveTab> + <Visible>0</Visible> + <Dynamic>0</Dynamic> + </Window> + <Window> + <WinId>35905</WinId> + <ItemNo>48</ItemNo> + <Name>not set</Name> + <AnchorWinID>35904</AnchorWinID> + <AnchorWinName>???</AnchorWinName> + <OtherWinID>0</OtherWinID> + <OtherWinName></OtherWinName> + <WinType>1</WinType> + <DockType>4</DockType> + <DockLocation>2</DockLocation> + <Pinned>0</Pinned> + <DockedRect_top>76</DockedRect_top> + <DockedRect_left>1070</DockedRect_left> + <DockedRect_bottom>511</DockedRect_bottom> + <DockedRect_right>1280</DockedRect_right> + <FloatingRect_top>0</FloatingRect_top> + <FloatingRect_left>0</FloatingRect_left> + <FloatingRect_bottom>600</FloatingRect_bottom> + <FloatingRect_right>250</FloatingRect_right> + <ContainerPercent>100</ContainerPercent> + <ActiveTab>0</ActiveTab> + <Visible>0</Visible> + <Dynamic>0</Dynamic> + </Window> + <Window> + <WinId>203</WinId> + <ItemNo>49</ItemNo> + <Name>Disassembly</Name> + <AnchorWinID>0</AnchorWinID> + <AnchorWinName></AnchorWinName> + <OtherWinID>0</OtherWinID> + <OtherWinName></OtherWinName> + <WinType>1</WinType> + <DockType>2</DockType> + <DockLocation>3</DockLocation> + <Pinned>0</Pinned> + <DockedRect_top>76</DockedRect_top> + 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<ActiveTab>0</ActiveTab> + <Visible>0</Visible> + <Dynamic>0</Dynamic> + </Window> + <Window> + <WinId>204</WinId> + <ItemNo>52</ItemNo> + <Name>Performance Analyzer</Name> + <AnchorWinID>343</AnchorWinID> + <AnchorWinName>Performance Analyzer</AnchorWinName> + <OtherWinID>0</OtherWinID> + <OtherWinName></OtherWinName> + <WinType>1</WinType> + <DockType>4</DockType> + <DockLocation>2</DockLocation> + <Pinned>0</Pinned> + <DockedRect_top>76</DockedRect_top> + <DockedRect_left>214</DockedRect_left> + <DockedRect_bottom>286</DockedRect_bottom> + <DockedRect_right>1280</DockedRect_right> + <FloatingRect_top>0</FloatingRect_top> + <FloatingRect_left>0</FloatingRect_left> + <FloatingRect_bottom>250</FloatingRect_bottom> + <FloatingRect_right>600</FloatingRect_right> + <ContainerPercent>100</ContainerPercent> + <ActiveTab>0</ActiveTab> + <Visible>0</Visible> + <Dynamic>0</Dynamic> + </Window> + <Window> + <WinId>346</WinId> + <ItemNo>53</ItemNo> + <Name>Code Coverage</Name> + <AnchorWinID>204</AnchorWinID> + <AnchorWinName>Performance Analyzer</AnchorWinName> + <OtherWinID>0</OtherWinID> + <OtherWinName></OtherWinName> + <WinType>1</WinType> + <DockType>4</DockType> + <DockLocation>2</DockLocation> + <Pinned>0</Pinned> + <DockedRect_top>76</DockedRect_top> + <DockedRect_left>214</DockedRect_left> + <DockedRect_bottom>286</DockedRect_bottom> + <DockedRect_right>1280</DockedRect_right> + <FloatingRect_top>0</FloatingRect_top> + <FloatingRect_left>0</FloatingRect_left> + <FloatingRect_bottom>250</FloatingRect_bottom> + <FloatingRect_right>600</FloatingRect_right> + <ContainerPercent>100</ContainerPercent> + <ActiveTab>0</ActiveTab> + <Visible>0</Visible> + <Dynamic>0</Dynamic> + </Window> + </View> + </WinLayout> + + <MDIGroups> + <Orientation>1</Orientation> + <ActiveMDIGroup>0</ActiveMDIGroup> + <MDIGroup> + <Size>100</Size> + <ActiveTab>2</ActiveTab> + <Documents> + <Doc> + <Name>E:\temp\rt-thread-sep4020\libcpu\arm\sep4020\start_rvds.S</Name> + <ColumnNumber>0</ColumnNumber> + <TopLine>87</TopLine> + <CurrentLine>94</CurrentLine> + </Doc> + <Doc> + <Name>.\startup.c</Name> + <ColumnNumber>0</ColumnNumber> + <TopLine>113</TopLine> + <CurrentLine>120</CurrentLine> + </Doc> + <Doc> + <Name>..\..\src\idle.c</Name> + <ColumnNumber>0</ColumnNumber> + <TopLine>57</TopLine> + <CurrentLine>65</CurrentLine> + </Doc> + <Doc> + <Name>..\..\src\kservice.h</Name> + <ColumnNumber>0</ColumnNumber> + <TopLine>1</TopLine> + <CurrentLine>1</CurrentLine> + </Doc> + </Documents> + </MDIGroup> + </MDIGroups> + +</ProjectOpt> diff --git a/bsp/sep4020/project.uvproj b/bsp/sep4020/project.uvproj new file mode 100644 index 0000000000..07e5664179 --- /dev/null +++ b/bsp/sep4020/project.uvproj @@ -0,0 +1,1007 @@ +<?xml version="1.0" encoding="UTF-8" standalone="no" ?> +<Project xmlns:xsi="http://www.w3.org/2001/XMLSchema-instance" xsi:noNamespaceSchemaLocation="project_proj.xsd"> + + <SchemaVersion>1.0</SchemaVersion> + + <Header>### uVision Project, (C) Keil Software</Header> + + <Targets> + <Target> + <TargetName>RT-Thread/SEP4020</TargetName> + <ToolsetNumber>0x4</ToolsetNumber> + <ToolsetName>ARM-ADS</ToolsetName> + <TargetOption> + <TargetCommonOption> + <Device>SEP4020</Device> + <Vendor>SeuIC</Vendor> + <Cpu>IRAM(0x60000000-0x60007FFF) CLOCK(14745600) CPUTYPE(ARM7TDMI)</Cpu> + <FlashUtilSpec></FlashUtilSpec> + <StartupFile></StartupFile> + <FlashDriverDll></FlashDriverDll> + <DeviceId>0</DeviceId> + <RegisterFile></RegisterFile> + <MemoryEnv></MemoryEnv> + <Cmp></Cmp> + <Asm></Asm> + <Linker></Linker> + <OHString></OHString> + <InfinionOptionDll></InfinionOptionDll> + <SLE66CMisc></SLE66CMisc> + <SLE66AMisc></SLE66AMisc> + <SLE66LinkerMisc></SLE66LinkerMisc> + <UseEnv>0</UseEnv> + <BinPath></BinPath> + <IncludePath></IncludePath> + <LibPath></LibPath> + <RegisterFilePath>Atmel\SAM7X\</RegisterFilePath> + <DBRegisterFilePath>Atmel\SAM7X\</DBRegisterFilePath> + <TargetStatus> + <Error>0</Error> + <ExitCodeStop>0</ExitCodeStop> + <ButtonStop>0</ButtonStop> + <NotGenerated>0</NotGenerated> + <InvalidFlash>1</InvalidFlash> + </TargetStatus> + <OutputDirectory>.\build\</OutputDirectory> + <OutputName>rtthread-sep4020</OutputName> + <CreateExecutable>1</CreateExecutable> + <CreateLib>0</CreateLib> + <CreateHexFile>0</CreateHexFile> + <DebugInformation>1</DebugInformation> + <BrowseInformation>1</BrowseInformation> + <ListingPath>.\build\</ListingPath> + <HexFormatSelection>1</HexFormatSelection> + <Merge32K>0</Merge32K> + <CreateBatchFile>0</CreateBatchFile> + <BeforeCompile> + <RunUserProg1>0</RunUserProg1> + <RunUserProg2>0</RunUserProg2> + <UserProg1Name></UserProg1Name> + <UserProg2Name></UserProg2Name> + <UserProg1Dos16Mode>0</UserProg1Dos16Mode> + <UserProg2Dos16Mode>0</UserProg2Dos16Mode> + </BeforeCompile> + <BeforeMake> + <RunUserProg1>0</RunUserProg1> + <RunUserProg2>0</RunUserProg2> + <UserProg1Name></UserProg1Name> + <UserProg2Name></UserProg2Name> + <UserProg1Dos16Mode>0</UserProg1Dos16Mode> + <UserProg2Dos16Mode>0</UserProg2Dos16Mode> + </BeforeMake> + <AfterMake> + <RunUserProg1>1</RunUserProg1> + <RunUserProg2>0</RunUserProg2> + <UserProg1Name>fromelf.exe --bin -o ./build/SEP4020.bin ./build/*.axf</UserProg1Name> + <UserProg2Name></UserProg2Name> + <UserProg1Dos16Mode>0</UserProg1Dos16Mode> + <UserProg2Dos16Mode>0</UserProg2Dos16Mode> + </AfterMake> + <SelectedForBatchBuild>0</SelectedForBatchBuild> + <SVCSIdString></SVCSIdString> + </TargetCommonOption> + <CommonProperty> + <UseCPPCompiler>0</UseCPPCompiler> + <RVCTCodeConst>0</RVCTCodeConst> + <RVCTZI>0</RVCTZI> + <RVCTOtherData>0</RVCTOtherData> + <ModuleSelection>0</ModuleSelection> + <IncludeInBuild>1</IncludeInBuild> + <AlwaysBuild>0</AlwaysBuild> + <GenerateAssemblyFile>0</GenerateAssemblyFile> + <AssembleAssemblyFile>0</AssembleAssemblyFile> + <PublicsOnly>0</PublicsOnly> + <StopOnExitCode>3</StopOnExitCode> + <CustomArgument></CustomArgument> + <IncludeLibraryModules></IncludeLibraryModules> + </CommonProperty> + <DllOption> + <SimDllName>SARM.DLL</SimDllName> + <SimDllArguments></SimDllArguments> + <SimDlgDll>DARMSH.DLL</SimDlgDll> + <SimDlgDllArguments></SimDlgDllArguments> + <TargetDllName>SARM.DLL</TargetDllName> + <TargetDllArguments></TargetDllArguments> + <TargetDlgDll>TARMSH.DLL</TargetDlgDll> + <TargetDlgDllArguments></TargetDlgDllArguments> + </DllOption> + <DebugOption> + <OPTHX> + <HexSelection>1</HexSelection> + <HexRangeLowAddress>0</HexRangeLowAddress> + <HexRangeHighAddress>0</HexRangeHighAddress> + <HexOffset>0</HexOffset> + <Oh166RecLen>16</Oh166RecLen> + </OPTHX> + <Simulator> + <UseSimulator>0</UseSimulator> + <LoadApplicationAtStartup>1</LoadApplicationAtStartup> + <RunToMain>0</RunToMain> + <RestoreBreakpoints>1</RestoreBreakpoints> + <RestoreWatchpoints>1</RestoreWatchpoints> + <RestoreMemoryDisplay>1</RestoreMemoryDisplay> + <RestoreFunctions>1</RestoreFunctions> + <RestoreToolbox>1</RestoreToolbox> + <LimitSpeedToRealTime>0</LimitSpeedToRealTime> + </Simulator> + <Target> + <UseTarget>1</UseTarget> + <LoadApplicationAtStartup>0</LoadApplicationAtStartup> + <RunToMain>0</RunToMain> + <RestoreBreakpoints>0</RestoreBreakpoints> + <RestoreWatchpoints>1</RestoreWatchpoints> + <RestoreMemoryDisplay>1</RestoreMemoryDisplay> + <RestoreFunctions>0</RestoreFunctions> + <RestoreToolbox>1</RestoreToolbox> + </Target> + <RunDebugAfterBuild>0</RunDebugAfterBuild> + <TargetSelection>6</TargetSelection> + <SimDlls> + <CpuDll></CpuDll> + <CpuDllArguments></CpuDllArguments> + <PeripheralDll></PeripheralDll> + <PeripheralDllArguments></PeripheralDllArguments> + <InitializationFile>.\Memory.ini</InitializationFile> + </SimDlls> + <TargetDlls> + <CpuDll></CpuDll> + <CpuDllArguments></CpuDllArguments> + <PeripheralDll></PeripheralDll> + <PeripheralDllArguments></PeripheralDllArguments> + <InitializationFile>.\Ext_SDRAM.ini</InitializationFile> + <Driver>Segger\JLTAgdi.dll</Driver> + </TargetDlls> + </DebugOption> + <Utilities> + <Flash1> + <UseTargetDll>1</UseTargetDll> + <UseExternalTool>0</UseExternalTool> + <RunIndependent>0</RunIndependent> + <UpdateFlashBeforeDebugging>0</UpdateFlashBeforeDebugging> + <Capability>1</Capability> + <DriverSelection>4100</DriverSelection> + </Flash1> + <Flash2>Segger\JLTAgdi.dll</Flash2> + <Flash3></Flash3> + <Flash4></Flash4> + </Utilities> + <TargetArmAds> + <ArmAdsMisc> + <GenerateListings>0</GenerateListings> + <asHll>1</asHll> + <asAsm>1</asAsm> + <asMacX>1</asMacX> + <asSyms>1</asSyms> + <asFals>1</asFals> + <asDbgD>1</asDbgD> + <asForm>1</asForm> + <ldLst>0</ldLst> + <ldmm>1</ldmm> + <ldXref>1</ldXref> + <BigEnd>0</BigEnd> + <AdsALst>0</AdsALst> + <AdsACrf>1</AdsACrf> + <AdsANop>0</AdsANop> + <AdsANot>0</AdsANot> + <AdsLLst>1</AdsLLst> + <AdsLmap>1</AdsLmap> + <AdsLcgr>1</AdsLcgr> + <AdsLsym>1</AdsLsym> + <AdsLszi>1</AdsLszi> + <AdsLtoi>1</AdsLtoi> + <AdsLsun>1</AdsLsun> + <AdsLven>1</AdsLven> + <AdsLsxf>1</AdsLsxf> + <RvctClst>0</RvctClst> + <GenPPlst>0</GenPPlst> + <AdsCpuType>ARM7TDMI</AdsCpuType> + <RvctDeviceName></RvctDeviceName> + <mOS>0</mOS> + <uocRom>0</uocRom> + <uocRam>0</uocRam> + <hadIROM>0</hadIROM> + <hadIRAM>1</hadIRAM> + <hadXRAM>0</hadXRAM> + <uocXRam>0</uocXRam> + <RvdsVP>0</RvdsVP> + <hadIRAM2>0</hadIRAM2> + <hadIROM2>0</hadIROM2> + <StupSel>0</StupSel> + <useUlib>0</useUlib> + <EndSel>0</EndSel> + <uLtcg>0</uLtcg> + <RoSelD>3</RoSelD> + <RwSelD>3</RwSelD> + <CodeSel>0</CodeSel> + <OptFeed>1</OptFeed> + <NoZi1>0</NoZi1> + <NoZi2>0</NoZi2> + <NoZi3>0</NoZi3> + <NoZi4>0</NoZi4> + <NoZi5>0</NoZi5> + <Ro1Chk>1</Ro1Chk> + <Ro2Chk>0</Ro2Chk> + <Ro3Chk>0</Ro3Chk> + <Ir1Chk>0</Ir1Chk> + <Ir2Chk>0</Ir2Chk> + <Ra1Chk>1</Ra1Chk> + <Ra2Chk>0</Ra2Chk> + <Ra3Chk>0</Ra3Chk> + <Im1Chk>0</Im1Chk> + <Im2Chk>0</Im2Chk> + <OnChipMemories> + <Ocm1> + <Type>0</Type> + <StartAddress>0x0</StartAddress> + <Size>0x0</Size> + </Ocm1> + <Ocm2> + <Type>0</Type> + <StartAddress>0x0</StartAddress> + <Size>0x0</Size> + </Ocm2> + <Ocm3> + <Type>0</Type> + <StartAddress>0x0</StartAddress> + <Size>0x0</Size> + </Ocm3> + <Ocm4> + <Type>0</Type> + <StartAddress>0x0</StartAddress> + <Size>0x0</Size> + </Ocm4> + <Ocm5> + <Type>0</Type> + <StartAddress>0x0</StartAddress> + <Size>0x0</Size> + </Ocm5> + <Ocm6> + <Type>0</Type> + <StartAddress>0x0</StartAddress> + <Size>0x0</Size> + </Ocm6> + <IRAM> + <Type>0</Type> + <StartAddress>0x60000000</StartAddress> + <Size>0x8000</Size> + </IRAM> + <IROM> + <Type>1</Type> + <StartAddress>0x100000</StartAddress> + <Size>0x40000</Size> + </IROM> + <XRAM> + <Type>0</Type> + <StartAddress>0x0</StartAddress> + <Size>0x0</Size> + </XRAM> + <OCR_RVCT1> + <Type>1</Type> + <StartAddress>0x0</StartAddress> + <Size>0x200000</Size> + </OCR_RVCT1> + <OCR_RVCT2> + <Type>1</Type> + <StartAddress>0x0</StartAddress> + <Size>0x0</Size> + </OCR_RVCT2> + <OCR_RVCT3> + <Type>1</Type> + <StartAddress>0x0</StartAddress> + <Size>0x0</Size> + </OCR_RVCT3> + <OCR_RVCT4> + <Type>1</Type> + <StartAddress>0x0</StartAddress> + <Size>0x0</Size> + </OCR_RVCT4> + <OCR_RVCT5> + <Type>1</Type> + <StartAddress>0x0</StartAddress> + <Size>0x0</Size> + </OCR_RVCT5> + <OCR_RVCT6> + <Type>0</Type> + <StartAddress>0x30000000</StartAddress> + <Size>0x2000000</Size> + </OCR_RVCT6> + <OCR_RVCT7> + <Type>0</Type> + <StartAddress>0x0</StartAddress> + <Size>0x0</Size> + </OCR_RVCT7> + <OCR_RVCT8> + <Type>0</Type> + <StartAddress>0x0</StartAddress> + <Size>0x0</Size> + </OCR_RVCT8> + <OCR_RVCT9> + <Type>0</Type> + <StartAddress>0x60000000</StartAddress> + <Size>0x8000</Size> + </OCR_RVCT9> + <OCR_RVCT10> + <Type>0</Type> + <StartAddress>0x0</StartAddress> + <Size>0x0</Size> + </OCR_RVCT10> + </OnChipMemories> + <RvctStartVector></RvctStartVector> + </ArmAdsMisc> + <Cads> + <interw>1</interw> + <Optim>1</Optim> + <oTime>0</oTime> + <SplitLS>0</SplitLS> + <OneElfS>0</OneElfS> + <Strict>0</Strict> + <EnumInt>0</EnumInt> + <PlainCh>0</PlainCh> + <Ropi>0</Ropi> + <Rwpi>0</Rwpi> + <wLevel>2</wLevel> + <uThumb>0</uThumb> + <VariousControls> + <MiscControls></MiscControls> + <Define></Define> + <Undefine></Undefine> + <IncludePath>.;..\..\include;..\..\finsh;..\..\net\lwip\src\include;..\..\net\lwip\src;..\..\net\lwip\src\arch\include;..\..\net\lwip\src\include\ipv4;;..\..\filesystem\dfs;..\..\filesystem\dfs\include;..\..\filesystem\dfs\filesystems\efsl\src\include;..\..\filesystem\dfs\filesystems\efsl\src\base\include;..\..\filesystem\dfs\filesystems\efsl\src\fs\vfat\include;..\..\libcpu\arm\sep4020;..\..\libcpu\arm\sep4020;..\..\components\finsh</IncludePath> + </VariousControls> + </Cads> + <Aads> + <interw>1</interw> + <Ropi>0</Ropi> + <Rwpi>0</Rwpi> + <thumb>0</thumb> + <SplitLS>0</SplitLS> + <SwStkChk>0</SwStkChk> + <NoWarn>0</NoWarn> + <VariousControls> + <MiscControls></MiscControls> + <Define>RAM_INTVEC REMAP</Define> + <Undefine></Undefine> + <IncludePath></IncludePath> + </VariousControls> + </Aads> + <LDads> + <umfTarg>0</umfTarg> + <Ropi>0</Ropi> + <Rwpi>0</Rwpi> + <noStLib>0</noStLib> + <RepFail>1</RepFail> + <useFile>0</useFile> + <TextAddressRange>0x0</TextAddressRange> + <DataAddressRange></DataAddressRange> + <ScatterFile>.\rtthread-sep4020-sdram.sct</ScatterFile> + <IncludeLibs></IncludeLibs> + <IncludeLibsPath></IncludeLibsPath> + <Misc>--keep __fsym_* --keep __vsym_*</Misc> + <LinkerInputFile></LinkerInputFile> + <DisabledWarnings></DisabledWarnings> + </LDads> + </TargetArmAds> + </TargetOption> + <Groups> + <Group> + <GroupName>bsp</GroupName> + <Files> + <File> + <FileName>rtconfig.h</FileName> + <FileType>5</FileType> + <FilePath>.\rtconfig.h</FilePath> + </File> + <File> + <FileName>application.c</FileName> + <FileType>1</FileType> + <FilePath>.\application.c</FilePath> + </File> + <File> + <FileName>board.c</FileName> + <FileType>1</FileType> + <FilePath>.\board.c</FilePath> + </File> + <File> + <FileName>startup.c</FileName> + <FileType>1</FileType> + <FilePath>.\startup.c</FilePath> + </File> + </Files> + </Group> + <Group> + <GroupName>kernel</GroupName> + <Files> + <File> + <FileName>clock.c</FileName> + <FileType>1</FileType> + <FilePath>..\..\src\clock.c</FilePath> + </File> + <File> + <FileName>idle.c</FileName> + <FileType>1</FileType> + <FilePath>..\..\src\idle.c</FilePath> + </File> + <File> + <FileName>ipc.c</FileName> + <FileType>1</FileType> + <FilePath>..\..\src\ipc.c</FilePath> + </File> + <File> + <FileName>irq.c</FileName> + <FileType>1</FileType> + <FilePath>..\..\src\irq.c</FilePath> + </File> + <File> + <FileName>kservice.c</FileName> + <FileType>1</FileType> + <FilePath>..\..\src\kservice.c</FilePath> + </File> + <File> + <FileName>mem.c</FileName> + <FileType>1</FileType> + <FilePath>..\..\src\mem.c</FilePath> + </File> + <File> + <FileName>mempool.c</FileName> + <FileType>1</FileType> + <FilePath>..\..\src\mempool.c</FilePath> + </File> + <File> + <FileName>object.c</FileName> + <FileType>1</FileType> + <FilePath>..\..\src\object.c</FilePath> + </File> + <File> + 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<FileName>trap.c</FileName> + <FileType>1</FileType> + <FilePath>E:\temp\rt-thread-sep4020\libcpu\arm\sep4020\trap.c</FilePath> + </File> + <File> + <FileName>cpu.c</FileName> + <FileType>1</FileType> + <FilePath>E:\temp\rt-thread-sep4020\libcpu\arm\sep4020\cpu.c</FilePath> + </File> + <File> + <FileName>start_rvds.S</FileName> + <FileType>2</FileType> + <FilePath>E:\temp\rt-thread-sep4020\libcpu\arm\sep4020\start_rvds.S</FilePath> + </File> + <File> + <FileName>context_rvds.S</FileName> + <FileType>2</FileType> + <FilePath>E:\temp\rt-thread-sep4020\libcpu\arm\sep4020\context_rvds.S</FilePath> + </File> + <File> + <FileName>clk.c</FileName> + <FileType>1</FileType> + <FilePath>..\..\libcpu\arm\sep4020\clk.c</FilePath> + </File> + <File> + <FileName>serial.c</FileName> + <FileType>1</FileType> + <FilePath>..\..\libcpu\arm\sep4020\serial.c</FilePath> + </File> + <File> + <FileName>serial.h</FileName> + <FileType>5</FileType> + <FilePath>..\..\libcpu\arm\sep4020\serial.h</FilePath> + </File> + </Files> + </Group> + <Group> + <GroupName>finsh</GroupName> + <Files> + <File> + <FileName>cmd.c</FileName> + <FileType>1</FileType> + <FilePath>..\..\components\finsh\cmd.c</FilePath> + </File> + <File> + <FileName>finsh_compiler.c</FileName> + <FileType>1</FileType> + <FilePath>..\..\components\finsh\finsh_compiler.c</FilePath> + </File> + <File> + <FileName>finsh_error.c</FileName> + <FileType>1</FileType> + <FilePath>..\..\components\finsh\finsh_error.c</FilePath> + </File> + <File> + <FileName>finsh_heap.c</FileName> + <FileType>1</FileType> + <FilePath>..\..\components\finsh\finsh_heap.c</FilePath> + </File> + <File> + <FileName>finsh_init.c</FileName> + <FileType>1</FileType> + <FilePath>..\..\components\finsh\finsh_init.c</FilePath> + </File> + <File> + <FileName>finsh_node.c</FileName> + <FileType>1</FileType> + <FilePath>..\..\components\finsh\finsh_node.c</FilePath> + </File> + <File> + <FileName>finsh_ops.c</FileName> + <FileType>1</FileType> + <FilePath>..\..\components\finsh\finsh_ops.c</FilePath> + </File> + <File> + <FileName>finsh_parser.c</FileName> + <FileType>1</FileType> + <FilePath>..\..\components\finsh\finsh_parser.c</FilePath> + </File> + <File> + <FileName>finsh_token.c</FileName> + <FileType>1</FileType> + <FilePath>..\..\components\finsh\finsh_token.c</FilePath> + </File> + <File> + <FileName>finsh_var.c</FileName> + <FileType>1</FileType> + <FilePath>..\..\components\finsh\finsh_var.c</FilePath> + </File> + <File> + <FileName>finsh_vm.c</FileName> + <FileType>1</FileType> + <FilePath>..\..\components\finsh\finsh_vm.c</FilePath> + </File> + <File> + <FileName>shell.c</FileName> + <FileType>1</FileType> + <FilePath>..\..\components\finsh\shell.c</FilePath> + </File> + <File> + <FileName>symbol.c</FileName> + <FileType>1</FileType> + <FilePath>..\..\components\finsh\symbol.c</FilePath> + </File> + </Files> + </Group> + <Group> + <GroupName>lwip</GroupName> + <GroupOption> + <CommonProperty> + <UseCPPCompiler>0</UseCPPCompiler> + <RVCTCodeConst>0</RVCTCodeConst> + <RVCTZI>0</RVCTZI> + <RVCTOtherData>0</RVCTOtherData> + <ModuleSelection>0</ModuleSelection> + <IncludeInBuild>0</IncludeInBuild> + <AlwaysBuild>0</AlwaysBuild> + <GenerateAssemblyFile>2</GenerateAssemblyFile> + <AssembleAssemblyFile>2</AssembleAssemblyFile> + <PublicsOnly>2</PublicsOnly> + <StopOnExitCode>11</StopOnExitCode> + <CustomArgument></CustomArgument> + <IncludeLibraryModules></IncludeLibraryModules> + </CommonProperty> + <GroupArmAds> + <Cads> + <interw>2</interw> + <Optim>0</Optim> + <oTime>2</oTime> + <SplitLS>2</SplitLS> + <OneElfS>2</OneElfS> + <Strict>2</Strict> + <EnumInt>2</EnumInt> + <PlainCh>2</PlainCh> + <Ropi>2</Ropi> + <Rwpi>2</Rwpi> + <wLevel>0</wLevel> + <uThumb>2</uThumb> + <VariousControls> + <MiscControls></MiscControls> + <Define></Define> + <Undefine></Undefine> + <IncludePath></IncludePath> + </VariousControls> + </Cads> + <Aads> + <interw>2</interw> + <Ropi>2</Ropi> + <Rwpi>2</Rwpi> + <thumb>2</thumb> + <SplitLS>2</SplitLS> + <SwStkChk>2</SwStkChk> + <NoWarn>2</NoWarn> + <VariousControls> + <MiscControls></MiscControls> + <Define></Define> + <Undefine></Undefine> + <IncludePath></IncludePath> + </VariousControls> + </Aads> + </GroupArmAds> + </GroupOption> + <Files> + <File> + <FileName>dhcp.c</FileName> + <FileType>1</FileType> + <FilePath>..\..\net\lwip\src\core\dhcp.c</FilePath> + </File> + <File> + <FileName>dns.c</FileName> + <FileType>1</FileType> + <FilePath>..\..\net\lwip\src\core\dns.c</FilePath> + </File> + <File> + <FileName>init.c</FileName> + <FileType>1</FileType> + <FilePath>..\..\net\lwip\src\core\init.c</FilePath> + </File> + <File> + <FileName>netif.c</FileName> + <FileType>1</FileType> + <FilePath>..\..\net\lwip\src\core\netif.c</FilePath> + </File> + <File> + <FileName>pbuf.c</FileName> + <FileType>1</FileType> + <FilePath>..\..\net\lwip\src\core\pbuf.c</FilePath> + </File> + <File> + <FileName>raw.c</FileName> + <FileType>1</FileType> + <FilePath>..\..\net\lwip\src\core\raw.c</FilePath> + </File> + <File> + <FileName>stats.c</FileName> + <FileType>1</FileType> + <FilePath>..\..\net\lwip\src\core\stats.c</FilePath> + </File> + <File> + <FileName>sys.c</FileName> + <FileType>1</FileType> + <FilePath>..\..\net\lwip\src\core\sys.c</FilePath> + </File> + <File> + <FileName>tcp.c</FileName> + <FileType>1</FileType> + <FilePath>..\..\net\lwip\src\core\tcp.c</FilePath> + </File> + <File> + <FileName>tcp_in.c</FileName> + <FileType>1</FileType> + <FilePath>..\..\net\lwip\src\core\tcp_in.c</FilePath> + </File> + <File> + <FileName>tcp_out.c</FileName> + <FileType>1</FileType> + <FilePath>..\..\net\lwip\src\core\tcp_out.c</FilePath> + </File> + <File> + <FileName>udp.c</FileName> + <FileType>1</FileType> + <FilePath>..\..\net\lwip\src\core\udp.c</FilePath> + </File> + <File> + <FileName>autoip.c</FileName> + <FileType>1</FileType> + <FilePath>..\..\net\lwip\src\core\ipv4\autoip.c</FilePath> + </File> + <File> + <FileName>icmp.c</FileName> + <FileType>1</FileType> + <FilePath>..\..\net\lwip\src\core\ipv4\icmp.c</FilePath> + </File> + <File> + <FileName>igmp.c</FileName> + <FileType>1</FileType> + <FilePath>..\..\net\lwip\src\core\ipv4\igmp.c</FilePath> + </File> + <File> + <FileName>inet.c</FileName> + <FileType>1</FileType> + <FilePath>..\..\net\lwip\src\core\ipv4\inet.c</FilePath> + </File> + <File> + <FileName>inet_chksum.c</FileName> + <FileType>1</FileType> + <FilePath>..\..\net\lwip\src\core\ipv4\inet_chksum.c</FilePath> + </File> + <File> + <FileName>ip.c</FileName> + <FileType>1</FileType> + <FilePath>..\..\net\lwip\src\core\ipv4\ip.c</FilePath> + </File> + <File> + <FileName>ip_addr.c</FileName> + <FileType>1</FileType> + <FilePath>..\..\net\lwip\src\core\ipv4\ip_addr.c</FilePath> + </File> + <File> + <FileName>ip_frag.c</FileName> + <FileType>1</FileType> + <FilePath>..\..\net\lwip\src\core\ipv4\ip_frag.c</FilePath> + </File> + <File> + <FileName>asn1_dec.c</FileName> + <FileType>1</FileType> + <FilePath>..\..\net\lwip\src\core\snmp\asn1_dec.c</FilePath> + </File> + <File> + <FileName>asn1_enc.c</FileName> + <FileType>1</FileType> + <FilePath>..\..\net\lwip\src\core\snmp\asn1_enc.c</FilePath> + </File> + <File> + <FileName>mib2.c</FileName> + <FileType>1</FileType> + <FilePath>..\..\net\lwip\src\core\snmp\mib2.c</FilePath> + </File> + <File> + <FileName>mib_structs.c</FileName> + <FileType>1</FileType> + <FilePath>..\..\net\lwip\src\core\snmp\mib_structs.c</FilePath> + </File> + <File> + <FileName>msg_in.c</FileName> + <FileType>1</FileType> + <FilePath>..\..\net\lwip\src\core\snmp\msg_in.c</FilePath> + </File> + <File> + <FileName>msg_out.c</FileName> + <FileType>1</FileType> + <FilePath>..\..\net\lwip\src\core\snmp\msg_out.c</FilePath> + </File> + <File> + <FileName>api_lib.c</FileName> + <FileType>1</FileType> + <FilePath>..\..\net\lwip\src\api\api_lib.c</FilePath> + </File> + <File> + <FileName>api_msg.c</FileName> + <FileType>1</FileType> + <FilePath>..\..\net\lwip\src\api\api_msg.c</FilePath> + </File> + <File> + <FileName>err.c</FileName> + <FileType>1</FileType> + <FilePath>..\..\net\lwip\src\api\err.c</FilePath> + </File> + <File> + <FileName>netbuf.c</FileName> + <FileType>1</FileType> + <FilePath>..\..\net\lwip\src\api\netbuf.c</FilePath> + </File> + <File> + <FileName>netdb.c</FileName> + <FileType>1</FileType> + <FilePath>..\..\net\lwip\src\api\netdb.c</FilePath> + </File> + <File> + <FileName>netifapi.c</FileName> + <FileType>1</FileType> + <FilePath>..\..\net\lwip\src\api\netifapi.c</FilePath> + </File> + <File> + <FileName>tcpip.c</FileName> + <FileType>1</FileType> + <FilePath>..\..\net\lwip\src\api\tcpip.c</FilePath> + </File> + <File> + <FileName>etharp.c</FileName> + <FileType>1</FileType> + <FilePath>..\..\net\lwip\src\netif\etharp.c</FilePath> + </File> + <File> + <FileName>ethernetif.c</FileName> + <FileType>1</FileType> + <FilePath>..\..\net\lwip\src\netif\ethernetif.c</FilePath> + </File> + <File> + <FileName>loopif.c</FileName> + <FileType>1</FileType> + <FilePath>..\..\net\lwip\src\netif\loopif.c</FilePath> + </File> + <File> + <FileName>sys_arch_init.c</FileName> + <FileType>1</FileType> + <FilePath>..\..\net\lwip\src\arch\sys_arch_init.c</FilePath> + </File> + <File> + <FileName>sys_arch.c</FileName> + <FileType>1</FileType> + <FilePath>..\..\net\lwip\src\arch\sys_arch.c</FilePath> + </File> + <File> + <FileName>sockets.c</FileName> + <FileType>1</FileType> + <FilePath>..\..\net\lwip\src\api\sockets.c</FilePath> + </File> + <File> + <FileName>memp.c</FileName> + <FileType>1</FileType> + <FilePath>..\..\net\lwip\src\core\memp.c</FilePath> + </File> + </Files> + </Group> + <Group> + <GroupName>filesystem</GroupName> + <GroupOption> + <CommonProperty> + <UseCPPCompiler>0</UseCPPCompiler> + <RVCTCodeConst>0</RVCTCodeConst> + <RVCTZI>0</RVCTZI> + <RVCTOtherData>0</RVCTOtherData> + <ModuleSelection>0</ModuleSelection> + <IncludeInBuild>0</IncludeInBuild> + <AlwaysBuild>0</AlwaysBuild> + <GenerateAssemblyFile>2</GenerateAssemblyFile> + <AssembleAssemblyFile>2</AssembleAssemblyFile> + <PublicsOnly>2</PublicsOnly> + <StopOnExitCode>11</StopOnExitCode> + <CustomArgument></CustomArgument> + <IncludeLibraryModules></IncludeLibraryModules> + </CommonProperty> + <GroupArmAds> + <Cads> + <interw>2</interw> + <Optim>0</Optim> + <oTime>2</oTime> + <SplitLS>2</SplitLS> + <OneElfS>2</OneElfS> + <Strict>2</Strict> + <EnumInt>2</EnumInt> + <PlainCh>2</PlainCh> + <Ropi>2</Ropi> + <Rwpi>2</Rwpi> + <wLevel>0</wLevel> + <uThumb>2</uThumb> + <VariousControls> + <MiscControls></MiscControls> + <Define></Define> + <Undefine></Undefine> + <IncludePath></IncludePath> + </VariousControls> + </Cads> + <Aads> + <interw>2</interw> + <Ropi>2</Ropi> + <Rwpi>2</Rwpi> + <thumb>2</thumb> + <SplitLS>2</SplitLS> + <SwStkChk>2</SwStkChk> + <NoWarn>2</NoWarn> + <VariousControls> + <MiscControls></MiscControls> + <Define></Define> + <Undefine></Undefine> + <IncludePath></IncludePath> + </VariousControls> + </Aads> + </GroupArmAds> + </GroupOption> + <Files> + <File> + <FileName>dfs_util.c</FileName> + <FileType>1</FileType> + <FilePath>..\..\filesystem\dfs\src\dfs_util.c</FilePath> + </File> + <File> + <FileName>dfs_cache.c</FileName> + <FileType>1</FileType> + <FilePath>..\..\filesystem\dfs\src\dfs_cache.c</FilePath> + </File> + <File> + <FileName>dfs_fs.c</FileName> + <FileType>1</FileType> + <FilePath>..\..\filesystem\dfs\src\dfs_fs.c</FilePath> + </File> + <File> + <FileName>dfs_init.c</FileName> + <FileType>1</FileType> + <FilePath>..\..\filesystem\dfs\src\dfs_init.c</FilePath> + </File> + <File> + <FileName>dfs_raw.c</FileName> + <FileType>1</FileType> + <FilePath>..\..\filesystem\dfs\src\dfs_raw.c</FilePath> + </File> + <File> + <FileName>dfs_posix.c</FileName> + <FileType>1</FileType> + <FilePath>..\..\filesystem\dfs\src\dfs_posix.c</FilePath> + </File> + <File> + <FileName>plibc.c</FileName> + <FileType>1</FileType> + <FilePath>..\..\filesystem\dfs\filesystems\efsl\src\base\plibc.c</FilePath> + </File> + <File> + <FileName>efs.c</FileName> + <FileType>1</FileType> + <FilePath>..\..\filesystem\dfs\filesystems\efsl\src\base\efs.c</FilePath> + </File> + <File> + <FileName>extract.c</FileName> + <FileType>1</FileType> + <FilePath>..\..\filesystem\dfs\filesystems\efsl\src\base\extract.c</FilePath> + </File> + <File> + <FileName>partition.c</FileName> + <FileType>1</FileType> + <FilePath>..\..\filesystem\dfs\filesystems\efsl\src\base\partition.c</FilePath> + </File> + <File> + <FileName>ui.c</FileName> + <FileType>1</FileType> + <FilePath>..\..\filesystem\dfs\filesystems\efsl\src\fs\vfat\ui.c</FilePath> + </File> + <File> + <FileName>dir.c</FileName> + <FileType>1</FileType> + <FilePath>..\..\filesystem\dfs\filesystems\efsl\src\fs\vfat\dir.c</FilePath> + </File> + <File> + <FileName>fat.c</FileName> + <FileType>1</FileType> + <FilePath>..\..\filesystem\dfs\filesystems\efsl\src\fs\vfat\fat.c</FilePath> + </File> + <File> + <FileName>file.c</FileName> + <FileType>1</FileType> + <FilePath>..\..\filesystem\dfs\filesystems\efsl\src\fs\vfat\file.c</FilePath> + </File> + <File> + <FileName>fs.c</FileName> + <FileType>1</FileType> + <FilePath>..\..\filesystem\dfs\filesystems\efsl\src\fs\vfat\fs.c</FilePath> + </File> + <File> + <FileName>ls.c</FileName> + <FileType>1</FileType> + <FilePath>..\..\filesystem\dfs\filesystems\efsl\src\fs\vfat\ls.c</FilePath> + </File> + <File> + <FileName>time.c</FileName> + <FileType>1</FileType> + <FilePath>..\..\filesystem\dfs\filesystems\efsl\src\fs\vfat\time.c</FilePath> + </File> + </Files> + </Group> + </Groups> + </Target> + </Targets> + +</Project> diff --git a/bsp/sep4020/rtconfig.h b/bsp/sep4020/rtconfig.h new file mode 100644 index 0000000000..6a47581def --- /dev/null +++ b/bsp/sep4020/rtconfig.h @@ -0,0 +1,150 @@ +/* RT-Thread config file */
+#ifndef __RTTHREAD_CFG_H__
+#define __RTTHREAD_CFG_H__
+
+/* RT_NAME_MAX*/
+#define RT_NAME_MAX 8
+
+/* RT_ALIGN_SIZE*/
+#define RT_ALIGN_SIZE 4
+
+/* PRIORITY_MAX*/
+#define RT_THREAD_PRIORITY_MAX 32
+
+/* Tick per Second*/
+#define RT_TICK_PER_SECOND 100
+
+/* SECTION: RT_DEBUG */
+/* Thread Debug*/
+/* #define RT_THREAD_DEBUG */
+
+/* Using Hook*/
+#define RT_USING_HOOK
+
+/* SECTION: IPC */
+/* Using Semaphore*/
+#define RT_USING_SEMAPHORE
+
+/* Using Mutex*/
+#define RT_USING_MUTEX
+
+/* Using Event*/
+#define RT_USING_EVENT
+
+/* Using Faset Event*/
+/* #define RT_USING_FASTEVENT */
+
+/* Using MailBox*/
+#define RT_USING_MAILBOX
+
+/* Using Message Queue*/
+#define RT_USING_MESSAGEQUEUE
+
+/* SECTION: Memory Management */
+/* Using Memory Pool Management*/
+#define RT_USING_MEMPOOL
+
+/* Using Dynamic Heap Management*/
+#define RT_USING_HEAP
+
+/* Using Small MM*/
+#define RT_USING_SMALL_MEM
+#define RT_MEM_STATS
+
+/* Using SLAB Allocator*/
+/* #define RT_USING_SLAB */
+
+/* SECTION: Device System */
+/* Using Device System*/
+#define RT_USING_DEVICE
+#define RT_USING_UART1
+#define RT_UART_RX_BUFFER_SIZE 128
+
+/* SECTION: Console options */
+/* the buffer size of console*/
+#define RT_CONSOLEBUF_SIZE 128
+
+/* SECTION: FinSH shell options */
+/* Using FinSH as Shell*/
+#define RT_USING_FINSH
+/* use symbol table */
+#define FINSH_USING_SYMTAB
+#define FINSH_USING_DESCRIPTION
+
+/* SECTION: a mini libc */
+/* Using mini libc library*/
+/* #define RT_USING_MINILIBC */
+
+/* SECTION: C++ support */
+/* Using C++ support*/
+/* #define RT_USING_CPLUSPLUS */
+
+/* SECTION: lwip, a lighwight TCP/IP protocol stack */
+/* Using lighweight TCP/IP protocol stack*/
+//#define RT_USING_LWIP
+
+/* Trace LwIP protocol*/
+/* #define RT_LWIP_DEBUG */
+
+/* LwIP tcp thread option */
+#define RT_LWIP_TCPTHREAD_PRIORITY 8
+#define RT_LWIP_TCPTHREAD_STACKSIZE 4096
+#define RT_LWIP_TCPTHREAD_MBOX_SIZE 32
+
+/* LwIP eth thread option */
+#define RT_LWIP_ETHTHREAD_PRIORITY 15
+#define RT_LWIP_ETHTHREAD_STACKSIZE 1024
+#define RT_LWIP_ETHTHREAD_MBOX_SIZE 8
+
+/* Enable ICMP protocol*/
+#define RT_LWIP_ICMP
+
+/* Enable IGMP protocol*/
+#define RT_LWIP_IGMP
+
+/* Enable UDP protocol*/
+#define RT_LWIP_UDP
+
+/* Enable TCP protocol*/
+#define RT_LWIP_TCP
+
+/* the number of simulatenously active TCP connections*/
+#define RT_LWIP_TCP_PCB_NUM 5
+
+/* TCP sender buffer space*/
+#define RT_LWIP_TCP_SND_BUF 1500
+
+/* Enable SNMP protocol*/
+/* #define RT_LWIP_SNMP */
+
+/* Using DHCP*/
+/* #define RT_LWIP_DHCP */
+
+/* ip address of target*/
+#define RT_LWIP_IPADDR0 192
+#define RT_LWIP_IPADDR1 168
+#define RT_LWIP_IPADDR2 1
+#define RT_LWIP_IPADDR3 30
+
+/* gateway address of target*/
+#define RT_LWIP_GWADDR0 192
+#define RT_LWIP_GWADDR1 168
+#define RT_LWIP_GWADDR2 1
+#define RT_LWIP_GWADDR3 1
+
+/* mask address of target*/
+#define RT_LWIP_MSKADDR0 255
+#define RT_LWIP_MSKADDR1 255
+#define RT_LWIP_MSKADDR2 255
+#define RT_LWIP_MSKADDR3 0
+
+/* SECTION: DFS options */
+//#define RT_USING_DFS +/* the max number of mounted filesystem */ +#define DFS_FILESYSTEMS_MAX 1 +/* the max number of opened files */ +#define DFS_FD_MAX 2 +/* the max number of cached sector */ +#define DFS_CACHE_MAX_NUM 4
+ +#endif
diff --git a/bsp/sep4020/rtthread-sep4020-rom.sct b/bsp/sep4020/rtthread-sep4020-rom.sct new file mode 100644 index 0000000000..c28581f0d1 --- /dev/null +++ b/bsp/sep4020/rtthread-sep4020-rom.sct @@ -0,0 +1,15 @@ +; *************************************************************
+; *** Scatter-Loading Description File generated by uVision ***
+; *************************************************************
+
+LR_ROM1 0x00000000 0x00200000 { ; load region size_region
+ ER_ROM1 0x00000000 0x00200000 { ; load address = execution address
+ *.o (RESET, +First)
+ *(InRoot$$Sections)
+ .ANY (+RO)
+ }
+ RW_RAM1 0x30000000 0x32000000 { ; RW data
+ .ANY (+RW +ZI)
+ }
+}
+
diff --git a/bsp/sep4020/rtthread-sep4020-sdram.sct b/bsp/sep4020/rtthread-sep4020-sdram.sct new file mode 100644 index 0000000000..bac01fca63 --- /dev/null +++ b/bsp/sep4020/rtthread-sep4020-sdram.sct @@ -0,0 +1,15 @@ +; *************************************************************
+; *** Scatter-Loading Description File generated by uVision ***
+; *************************************************************
+
+LR_ROM1 0x30000000 0x02000000 { ; load region size_region
+ ER_ROM1 0x30000000 0x02000000 { ; load address = execution address
+ *.o (RESET, +First)
+ *(InRoot$$Sections)
+ .ANY (+RO)
+ }
+ RW_RAM1 0x31000000{
+ .ANY (+RW +ZI)
+ }
+}
+
diff --git a/bsp/sep4020/sep4020.h b/bsp/sep4020/sep4020.h new file mode 100644 index 0000000000..06a50f8efa --- /dev/null +++ b/bsp/sep4020/sep4020.h @@ -0,0 +1,637 @@ +/*************************************************************************************
+ *
+ * File name: sep4020.h
+ *
+ * Change Logs: + * Date Author Notes
+ * 2010-03-17 zchong first version
+ **************************************************************************************/
+
+#ifndef __SEP4020_H__
+#define __SEP4020_H__
+
+/*************************************
+ macros for INTC
+*************************************/
+
+/*interrupt resources */
+
+#define INTGLOBAL 32
+
+#define INT_RTC 31
+#define INT_DMAC 30
+#define INT_EMI 29
+#define INT_MAC 28
+#define INT_TIMER1 27
+#define INT_TIMER2 26
+#define INT_TIMER3 25
+#define INT_UART0 24
+#define INT_UART1 23
+#define INT_UART2 22
+#define INT_UART3 21
+#define INT_PWM 20
+#define INT_LCDC 19
+#define INT_I2S 18
+#define INT_SSI 17
+#define INT_NOTUSED16 16
+#define INT_USB 15
+#define INT_SMC0 14
+#define INT_SMC1 13
+#define INT_SDIO 12
+#define INT_EXINT10 11
+#define INT_EXINT9 10
+#define INT_EXINT8 9
+#define INT_EXINT7 8
+#define INT_EXINT6 7
+#define INT_EXINT5 6
+#define INT_EXINT4 5
+#define INT_EXINT3 4
+#define INT_EXINT2 3
+#define INT_EXINT1 2
+#define INT_EXINT0 1
+#define INT_NOTUSED0 0
+
+/******************************************************************************************
+ * INTCģ��
+ * ��ַ: 0x10000000
+ ******************************************************************************************/
+
+#define INTC_IER (*(volatile unsigned *)0x10000000) /* IRQ interrupt enable register */
+#define INTC_IMR (*(volatile unsigned *)0x10000008) /* IRQ interrupt mask register */
+#define INTC_IFR (*(volatile unsigned *)0x10000010) /* IRQ����ǿ���жϼĴ��� */
+#define INTC_IRSR (*(volatile unsigned *)0x10000018) /* IRQδ�����ж�״̬�Ĵ��� */
+#define INTC_ISR (*(volatile unsigned *)0x10000020) /* IRQ�ж�״̬�Ĵ��� */
+#define INTC_IMSR (*(volatile unsigned *)0x10000028) /* IRQ�����ж�״̬�Ĵ��� */
+#define INTC_IFSR (*(volatile unsigned *)0x10000030) /* IRQ�ж�����״̬�Ĵ��� */
+#define INTC_FIER (*(volatile unsigned *)0x100000C0) /* FIQ�ж������Ĵ��� */
+#define INTC_FIMR (*(volatile unsigned *)0x100000C4) /* FIQ�ж����μĴ��� */
+#define INTC_FIFR (*(volatile unsigned *)0x100000C8) /* FIQ����ǿ���жϼĴ��� */
+#define INTC_FIRSR (*(volatile unsigned *)0x100000CC) /* FIQδ�����ж�״̬�Ĵ��� */
+#define INTC_FISR (*(volatile unsigned *)0x100000D0) /* FIQ�ж�״̬�Ĵ��� */
+#define INTC_FIFSR (*(volatile unsigned *)0x100000D4) /* FIQ�ж�����״̬�Ĵ��� */
+#define INTC_IPLR (*(volatile unsigned *)0x100000D8) /* IRQ�ж����ȼ��Ĵ��� */
+#define INTC_ICR1 (*(volatile unsigned *)0x100000DC) /* IRQ�ڲ��ж����ȼ����ƼĴ���1 */
+#define INTC_ICR2 (*(volatile unsigned *)0x100000E0) /* IRQ�ڲ��ж����ȼ����ƼĴ���2 */
+#define INTC_EXICR1 (*(volatile unsigned *)0x100000E4) /* IRQ�ⲿ�ж����ȼ����ƼĴ���1 */
+#define INTC_EXICR2 (*(volatile unsigned *)0x100000E8) /* IRQ�ⲿ�ж����ȼ����ƼĴ���2 */
+
+
+/******************************************************************************************
+ * PMCģ��
+ * ��ַ: 0x10001000
+ ******************************************************************************************/
+
+#define PMC_PLTR (*(volatile unsigned *)0x10001000) /* PLL���ȶ�����ʱ�� */
+#define PMC_PMCR (*(volatile unsigned *)0x10001004) /* ϵͳ��ʱ��PLL�Ŀ��ƼĴ��� */
+#define PMC_PUCR (*(volatile unsigned *)0x10001008) /* USBʱ��PLL�Ŀ��ƼĴ��� */
+#define PMC_PCSR (*(volatile unsigned *)0x1000100C) /* �ڲ�ģ��ʱ��Դ�����Ŀ��ƼĴ��� */
+#define PMC_PDSLOW (*(volatile unsigned *)0x10001010) /* SLOW״̬��ʱ�ӵķ�Ƶ���� */
+#define PMC_PMDR (*(volatile unsigned *)0x10001014) /* оƬ����ģʽ�Ĵ��� */
+#define PMC_RCTR (*(volatile unsigned *)0x10001018) /* Reset���ƼĴ��� */
+#define PMC_CLRWAKUP (*(volatile unsigned *)0x1000101C) /* WakeUp����Ĵ��� */
+
+
+/******************************************************************************************
+ * RTCģ��
+ * ��ַ: 0x10002000
+ ******************************************************************************************/
+
+#define RTC_STA_YMD (*(volatile unsigned *)0x10002000) /* ��, ��, �ռ����Ĵ��� */
+#define RTC_STA_HMS (*(volatile unsigned *)0x10002004) /* Сʱ, ����, ��Ĵ��� */
+#define RTC_ALARM_ALL (*(volatile unsigned *)0x10002008) /* ��ʱ��, ��, ʱ, �ּĴ��� */
+#define RTC_CTR (*(volatile unsigned *)0x1000200C) /* ���ƼĴ��� */
+#define RTC_INT_EN (*(volatile unsigned *)0x10002010) /* �ж�ʹ�ܼĴ��� */
+#define RTC_INT_STS (*(volatile unsigned *)0x10002014) /* �ж�״̬�Ĵ��� */
+#define RTC_SAMP (*(volatile unsigned *)0x10002018) /* �������ڼĴ��� */
+#define RTC_WD_CNT (*(volatile unsigned *)0x1000201C) /* Watch-Dog����ֵ�Ĵ��� */
+#define RTC_WD_SEV (*(volatile unsigned *)0x10002020) /* Watch-Dog����Ĵ��� */
+#define RTC_CONFIG_CHECK (*(volatile unsigned *)0x10002024) /* ����ʱ��ȷ�ϼĴ��� (������ʱ��֮ǰ��д0xaaaaaaaa) */
+#define RTC_SOFTRESET (*(volatile unsigned *)0x10002028) /* ������λ���ƼĴ���, 4020�б�ȥ���� */
+#define RTC_KEY0 (*(volatile unsigned *)0x1000202C) /* ��Կ�Ĵ���0, 4020��ֻ����һ���Ĵ��� */
+#define RTC_KEY1 (*(volatile unsigned *)0x10002030) /* ��Կ�Ĵ���1 */
+#define RTC_KEY2 (*(volatile unsigned *)0x10002034) /* ��Կ�Ĵ���2 */
+#define RTC_KEY3 (*(volatile unsigned *)0x10002038) /* ��Կ�Ĵ���3 */
+#define RTC_KEY4 (*(volatile unsigned *)0x1000203C) /* ��Կ�Ĵ���4 */
+#define RTC_KEY5 (*(volatile unsigned *)0x10002040) /* ��Կ�Ĵ���5 */
+
+
+/******************************************************************************************
+ * TIMERģ��
+ * ��ַ: 0x10003000
+ ******************************************************************************************/
+
+#define TIMER_T1LCR (*(volatile unsigned *)0x10003000) /* ͨ��1���ؼ����Ĵ��� */
+#define TIMER_T1CCR (*(volatile unsigned *)0x10003004) /* ͨ��1��ǰ����ֵ�Ĵ��� */
+#define TIMER_T1CR (*(volatile unsigned *)0x10003008) /* ͨ��1���ƼĴ��� */
+#define TIMER_T1ISCR (*(volatile unsigned *)0x1000300C) /* ͨ��1�ж�״̬����Ĵ��� */
+#define TIMER_T1IMSR (*(volatile unsigned *)0x10003010) /* ͨ��1�ж�����״̬�Ĵ��� */
+#define TIMER_T2LCR (*(volatile unsigned *)0x10003020) /* ͨ��2���ؼ����Ĵ��� */
+#define TIMER_T2CCR (*(volatile unsigned *)0x10003024) /* ͨ��2��ǰ����ֵ�Ĵ��� */
+#define TIMER_T2CR (*(volatile unsigned *)0x10003028) /* ͨ��2���ƼĴ��� */
+#define TIMER_T2ISCR (*(volatile unsigned *)0x1000302C) /* ͨ��2�ж�״̬����Ĵ��� */
+#define TIMER_T2IMSR (*(volatile unsigned *)0x10003030) /* ͨ��2�ж�����״̬�Ĵ��� */
+#define TIMER_T3LCR (*(volatile unsigned *)0x10003040) /* ͨ��3���ؼ����Ĵ��� */
+#define TIMER_T3CCR (*(volatile unsigned *)0x10003044) /* ͨ��3��ǰ����ֵ�Ĵ��� */
+#define TIMER_T3CR (*(volatile unsigned *)0x10003048) /* ͨ��3���ƼĴ��� */
+#define TIMER_T3ISCR (*(volatile unsigned *)0x1000304C) /* ͨ��3�ж�״̬����Ĵ��� */
+#define TIMER_T3IMSR (*(volatile unsigned *)0x10003050) /* ͨ��3�ж�����״̬�Ĵ��� */
+#define TIMER_T3CAPR (*(volatile unsigned *)0x10003054) /* ͨ��3����Ĵ��� */
+#define TIMER_T4LCR (*(volatile unsigned *)0x10003060) /* ͨ��4���ؼ����Ĵ��� */
+#define TIMER_T4CCR (*(volatile unsigned *)0x10003064) /* ͨ��4��ǰ����ֵ�Ĵ��� */
+#define TIMER_T4CR (*(volatile unsigned *)0x10003068) /* ͨ��4���ƼĴ��� */
+#define TIMER_T4ISCR (*(volatile unsigned *)0x1000306C) /* ͨ��4�ж�״̬����Ĵ��� */
+#define TIMER_T4IMSR (*(volatile unsigned *)0x10003070) /* ͨ��4�ж�����״̬�Ĵ��� */
+#define TIMER_T4CAPR (*(volatile unsigned *)0x10003074) /* ͨ��4����Ĵ��� */
+#define TIMER_T5LCR (*(volatile unsigned *)0x10003080) /* ͨ��5���ؼ����Ĵ��� */
+#define TIMER_T5CCR (*(volatile unsigned *)0x10003084) /* ͨ��5��ǰ����ֵ�Ĵ��� */
+#define TIMER_T5CR (*(volatile unsigned *)0x10003088) /* ͨ��5���ƼĴ��� */
+#define TIMER_T5ISCR (*(volatile unsigned *)0x1000308C) /* ͨ��5�ж�״̬����Ĵ��� */
+#define TIMER_T5IMSR (*(volatile unsigned *)0x10003090) /* ͨ��5�ж�����״̬�Ĵ��� */
+#define TIMER_T5CAPR (*(volatile unsigned *)0x10003094) /* ͨ��5����Ĵ��� */
+#define TIMER_T6LCR (*(volatile unsigned *)0x100030A0) /* ͨ��6���ؼ����Ĵ��� */
+#define TIMER_T6CCR (*(volatile unsigned *)0x100030A4) /* ͨ��6��ǰ����ֵ�Ĵ��� */
+#define TIMER_T6CR (*(volatile unsigned *)0x100030A8) /* ͨ��6���ƼĴ��� */
+#define TIMER_T6ISCR (*(volatile unsigned *)0x100030AC) /* ͨ��6�ж�״̬����Ĵ��� */
+#define TIMER_T6IMSR (*(volatile unsigned *)0x100030B0) /* ͨ��6�ж�����״̬�Ĵ��� */
+#define TIMER_T6CAPR (*(volatile unsigned *)0x100030B4) /* ͨ��6����Ĵ��� */
+#define TIMER_T7LCR (*(volatile unsigned *)0x100030C0) /* ͨ��7���ؼ����Ĵ��� */
+#define TIMER_T7CCR (*(volatile unsigned *)0x100030C4) /* ͨ��7��ǰ����ֵ�Ĵ��� */
+#define TIMER_T7CR (*(volatile unsigned *)0x100030C8) /* ͨ��7���ƼĴ��� */
+#define TIMER_T7ISCR (*(volatile unsigned *)0x100030CC) /* ͨ��7�ж�״̬����Ĵ��� */
+#define TIMER_T7IMSR (*(volatile unsigned *)0x100030D0) /* ͨ��7�ж�����״̬�Ĵ��� */
+#define TIMER_T8LCR (*(volatile unsigned *)0x100030E0) /* ͨ��8���ؼ����Ĵ��� */
+#define TIMER_T8CCR (*(volatile unsigned *)0x100030E4) /* ͨ��8��ǰ����ֵ�Ĵ��� */
+#define TIMER_T8CR (*(volatile unsigned *)0x100030E8) /* ͨ��8���ƼĴ��� */
+#define TIMER_T8ISCR (*(volatile unsigned *)0x100030EC) /* ͨ��8�ж�״̬����Ĵ��� */
+#define TIMER_T8IMSR (*(volatile unsigned *)0x100030F0) /* ͨ��8�ж�����״̬�Ĵ��� */
+#define TIMER_T9LCR (*(volatile unsigned *)0x10003100) /* ͨ��9���ؼ����Ĵ��� */
+#define TIMER_T9CCR (*(volatile unsigned *)0x10003104) /* ͨ��9��ǰ����ֵ�Ĵ��� */
+#define TIMER_T9CR (*(volatile unsigned *)0x10003108) /* ͨ��9���ƼĴ��� */
+#define TIMER_T9ISCR (*(volatile unsigned *)0x1000310C) /* ͨ��9�ж�״̬����Ĵ��� */
+#define TIMER_T9IMSR (*(volatile unsigned *)0x10003110) /* ͨ��9�ж�����״̬�Ĵ��� */
+#define TIMER_T10LCR (*(volatile unsigned *)0x10003120) /* ͨ��10���ؼ����Ĵ��� */
+#define TIMER_T10CCR (*(volatile unsigned *)0x10003124) /* ͨ��10��ǰ����ֵ�Ĵ��� */
+#define TIMER_T10CR (*(volatile unsigned *)0x10003128) /* ͨ��10���ƼĴ��� */
+#define TIMER_T10ISCR (*(volatile unsigned *)0x1000312C) /* ͨ��10�ж�״̬����Ĵ��� */
+#define TIMER_T10IMSR (*(volatile unsigned *)0x10003130) /* ͨ��10�ж�����״̬�Ĵ��� */
+#define TIMER_TIMSR (*(volatile unsigned *)0x10003140) /* TIMER�ж�����״̬�Ĵ��� */
+#define TIMER_TISCR (*(volatile unsigned *)0x10003144) /* TIMER�ж�״̬����Ĵ��� */
+#define TIMER_TISR (*(volatile unsigned *)0x10003148) /* TIMER�ж�״̬�Ĵ��� */
+
+
+/******************************************************************************************
+ * PWMģ��
+ * ��ַ: 0x10004000
+ ******************************************************************************************/
+
+#define PWM1_CTRL (*(volatile unsigned *)0x10004000) /* PWM1���ƼĴ��� */
+#define PWM1_DIV (*(volatile unsigned *)0x10004004) /* PWM1��Ƶ�Ĵ��� */
+#define PWM1_PERIOD (*(volatile unsigned *)0x10004008) /* PWM1���ڼĴ��� */
+#define PWM1_DATA (*(volatile unsigned *)0x1000400C) /* PWM1���ݼĴ��� */
+#define PWM1_CNT (*(volatile unsigned *)0x10004010) /* PWM1�����Ĵ��� */
+#define PWM1_STATUS (*(volatile unsigned *)0x10004014) /* PWM1״̬�Ĵ��� */
+#define PWM2_CTRL (*(volatile unsigned *)0x10004020) /* PWM2���ƼĴ��� */
+#define PWM2_DIV (*(volatile unsigned *)0x10004024) /* PWM2��Ƶ�Ĵ��� */
+#define PWM2_PERIOD (*(volatile unsigned *)0x10004028) /* PWM2���ڼĴ��� */
+#define PWM2_DATA (*(volatile unsigned *)0x1000402C) /* PWM2���ݼĴ��� */
+#define PWM2_CNT (*(volatile unsigned *)0x10004030) /* PWM2�����Ĵ��� */
+#define PWM2_STATUS (*(volatile unsigned *)0x10004034) /* PWM2״̬�Ĵ��� */
+#define PWM3_CTRL (*(volatile unsigned *)0x10004040) /* PWM3���ƼĴ��� */
+#define PWM3_DIV (*(volatile unsigned *)0x10004044) /* PWM3��Ƶ�Ĵ��� */
+#define PWM3_PERIOD (*(volatile unsigned *)0x10004048) /* PWM3���ڼĴ��� */
+#define PWM3_DATA (*(volatile unsigned *)0x1000404C) /* PWM3���ݼĴ��� */
+#define PWM3_CNT (*(volatile unsigned *)0x10004050) /* PWM3�����Ĵ��� */
+#define PWM3_STATUS (*(volatile unsigned *)0x10004054) /* PWM3״̬�Ĵ��� */
+#define PWM4_CTRL (*(volatile unsigned *)0x10004060) /* PWM4���ƼĴ��� */
+#define PWM4_DIV (*(volatile unsigned *)0x10004064) /* PWM4��Ƶ�Ĵ��� */
+#define PWM4_PERIOD (*(volatile unsigned *)0x10004068) /* PWM4���ڼĴ��� */
+#define PWM4_DATA (*(volatile unsigned *)0x1000406C) /* PWM4���ݼĴ��� */
+#define PWM4_CNT (*(volatile unsigned *)0x10004070) /* PWM4�����Ĵ��� */
+#define PWM4_STATUS (*(volatile unsigned *)0x10004074) /* PWM4״̬�Ĵ��� */
+#define PWM_INTMASK (*(volatile unsigned *)0x10004080) /* PWM�ж����μĴ��� */
+#define PWM_INT (*(volatile unsigned *)0x10004084) /* PWM�жϼĴ��� */
+#define PWM_ENABLE (*(volatile unsigned *)0x10004088) /* PWMʹ�ܼĴ��� */
+
+
+/******************************************************************************************
+ * UART0ģ��
+ * ��ַ: 0x10005000
+ ******************************************************************************************/
+#define UART0BASE ((volatile unsigned *)0x10005000)
+#define UART0_DLBL (*(volatile unsigned char*)0x10005000) /* ���������õͰ�λ�Ĵ��� */
+#define UART0_RXFIFO (*(volatile unsigned char*)0x10005000) /* ����FIFO */
+#define UART0_TXFIFO (*(volatile unsigned char*)0x10005000) /* ����FIFO */
+#define UART0_DLBH (*(volatile unsigned char*)0x10005004) /* ���������ø߰�λ�Ĵ��� */
+#define UART0_IER (*(volatile unsigned char*)0x10005004) /* �ж�ʹ�ܼĴ��� */
+#define UART0_IIR (*(volatile unsigned *)0x10005008) /* �ж�ʶ��Ĵ��� */
+#define UART0_FCR (*(volatile unsigned *)0x10005008) /* FIFO���ƼĴ��� */
+#define UART0_LCR (*(volatile unsigned *)0x1000500C) /* �п��ƼĴ��� */
+#define UART0_MCR (*(volatile unsigned *)0x10005010) /* Modem���ƼĴ��� */
+#define UART0_LSR (*(volatile unsigned *)0x10005014) /* ��״̬�Ĵ��� */
+#define UART0_MSR (*(volatile unsigned *)0x10005018) /* Modem״̬�Ĵ��� */
+
+
+/******************************************************************************************
+ * UART1ģ��
+ * ��ַ: 0x10006000
+ ******************************************************************************************/
+ #define UART1BASE ((volatile unsigned *)0x10006000)
+#define UART1_DLBL (*(volatile unsigned *)0x10006000) /* ���������õͰ�λ�Ĵ��� */
+#define UART1_RXFIFO (*(volatile unsigned *)0x10006000) /* ����FIFO */
+#define UART1_TXFIFO (*(volatile unsigned *)0x10006000) /* ����FIFO */
+#define UART1_DLBH (*(volatile unsigned *)0x10006004) /* ���������ø߰�λ�Ĵ��� */
+#define UART1_IER (*(volatile unsigned *)0x10006004) /* �ж�ʹ�ܼĴ��� */
+#define UART1_IIR (*(volatile unsigned *)0x10006008) /* �ж�ʶ��Ĵ��� */
+#define UART1_FCR (*(volatile unsigned *)0x10006008) /* FIFO���ƼĴ��� */
+#define UART1_LCR (*(volatile unsigned *)0x1000600C) /* �п��ƼĴ��� */
+#define UART1_MCR (*(volatile unsigned *)0x10006010) /* Modem���ƼĴ��� */
+#define UART1_LSR (*(volatile unsigned *)0x10006014) /* ��״̬�Ĵ��� */
+#define UART1_MSR (*(volatile unsigned *)0x10006018) /* Modem״̬�Ĵ��� */
+
+
+/******************************************************************************************
+ * UART2ģ��
+ * ��ַ: 0x10007000
+ ******************************************************************************************/
+#define UART2BASE ((volatile unsigned *)0x10007000)
+#define UART2_DLBL (*(volatile unsigned *)0x10007000) /* ���������õͰ�λ�Ĵ��� */
+#define UART2_RXFIFO (*(volatile unsigned *)0x10007000) /* ����FIFO */
+#define UART2_TXFIFO (*(volatile unsigned *)0x10007000) /* ����FIFO */
+#define UART2_DLBH (*(volatile unsigned *)0x10007004) /* ���������ø߰�λ�Ĵ��� */
+#define UART2_IER (*(volatile unsigned *)0x10007004) /* �ж�ʹ�ܼĴ��� */
+#define UART2_IIR (*(volatile unsigned *)0x10007008) /* �ж�ʶ��Ĵ��� */
+#define UART2_FCR (*(volatile unsigned *)0x10007008) /* FIFO���ƼĴ��� */
+#define UART2_LCR (*(volatile unsigned *)0x1000700C) /* �п��ƼĴ��� */
+#define UART2_MCR (*(volatile unsigned *)0x10007010) /* Modem���ƼĴ��� */
+#define UART2_LSR (*(volatile unsigned *)0x10007014) /* ��״̬�Ĵ��� */
+#define UART2_MSR (*(volatile unsigned *)0x10007018) /* Modem״̬�Ĵ��� */
+
+
+/******************************************************************************************
+ * UART3ģ��
+ * ��ַ: 0x10008000
+ ******************************************************************************************/
+#define UART3BASE ((volatile unsigned *)0x10008000)
+#define UART3_DLBL (*(volatile unsigned *)0x10008000) /* ���������õͰ�λ�Ĵ��� */
+#define UART3_RXFIFO (*(volatile unsigned *)0x10008000) /* ����FIFO */
+#define UART3_TXFIFO (*(volatile unsigned *)0x10008000) /* ����FIFO */
+#define UART3_DLBH (*(volatile unsigned *)0x10008004) /* ���������ø߰�λ�Ĵ��� */
+#define UART3_IER (*(volatile unsigned *)0x10008004) /* �ж�ʹ�ܼĴ��� */
+#define UART3_IIR (*(volatile unsigned *)0x10008008) /* �ж�ʶ��Ĵ��� */
+#define UART3_FCR (*(volatile unsigned *)0x10008008) /* FIFO���ƼĴ��� */
+#define UART3_LCR (*(volatile unsigned *)0x1000800C) /* �п��ƼĴ��� */
+#define UART3_MCR (*(volatile unsigned *)0x10008010) /* Modem���ƼĴ��� */
+#define UART3_LSR (*(volatile unsigned *)0x10008014) /* ��״̬�Ĵ��� */
+#define UART3_MSR (*(volatile unsigned *)0x10008018) /* Modem״̬�Ĵ��� */
+
+
+/******************************************************************************************
+ * SSIģ��
+ * ��ַ: 0x10009000
+ ******************************************************************************************/
+
+#define SSI_CONTROL0 (*(volatile unsigned *)0x10009000) /* ���ƼĴ���0 */
+#define SSI_CONTROL1 (*(volatile unsigned *)0x10009004) /* ���ƼĴ���1 */
+#define SSI_SSIENR (*(volatile unsigned *)0x10009008) /* SSIʹ�ܼĴ��� */
+#define SSI_MWCR (*(volatile unsigned *)0x1000900C) /* Microwire���ƼĴ��� */
+#define SSI_SER (*(volatile unsigned *)0x10009010) /* ���豸ʹ�ܼĴ��� */
+#define SSI_BAUDR (*(volatile unsigned *)0x10009014) /* ���������üĴ��� */
+#define SSI_TXFTLR (*(volatile unsigned *)0x10009018) /* ����FIFO��ֵ�Ĵ��� */
+#define SSI_RXFTLR (*(volatile unsigned *)0x1000901C) /* ����FIFO��ֵ�Ĵ��� */
+#define SSI_TXFLR (*(volatile unsigned *)0x10009020) /* ����FIFO״̬�Ĵ��� */
+#define SSI_RXFLR (*(volatile unsigned *)0x10009024) /* ����FIFO״̬�Ĵ��� */
+#define SSI_SR (*(volatile unsigned *)0x10009028) /* ״̬�Ĵ��� */
+#define SSI_IMR (*(volatile unsigned *)0x1000902C) /* �ж����μĴ��� */
+#define SSI_ISR (*(volatile unsigned *)0x10009030) /* �ж�����״̬�Ĵ��� */
+#define SSI_RISR (*(volatile unsigned *)0x10009034) /* �ж�ԭʼ״̬�Ĵ��� */
+#define SSI_TXOICR (*(volatile unsigned *)0x10009038) /* ����FIFO�����ж�����Ĵ��� */
+#define SSI_RXOICR (*(volatile unsigned *)0x1000903C) /* ����FIFO�����ж�����Ĵ��� */
+#define SSI_RXUICR (*(volatile unsigned *)0x10009040) /* ����FIFO�����ж�����Ĵ��� */
+#define SSI_ICR (*(volatile unsigned *)0x1000902C) /* �ж�����Ĵ��� */
+#define SSI_DMACR (*(volatile unsigned *)0x1000904C) /* DMA���ƼĴ��� */
+#define SSI_DMATDLR (*(volatile unsigned *)0x10009050) /* DMA����״̬�Ĵ��� */
+#define SSI_DMARDLR (*(volatile unsigned *)0x10009054) /* DMA����״̬�Ĵ��� */
+#define SSI_DR (*(volatile unsigned *)0x10009060) /* ���ݼĴ��� */
+
+
+/******************************************************************************************
+ * I2Sģ��
+ * ��ַ: 0x1000A000
+ ******************************************************************************************/
+
+#define I2S_CTRL (*(volatile unsigned *)0x1000A000) /* I2S���ƼĴ��� */
+#define I2S_DATA (*(volatile unsigned *)0x1000A004) /* I2S���ݼĴ��� */
+#define I2S_INT (*(volatile unsigned *)0x1000A008) /* I2S�жϼĴ��� */
+#define I2S_STATUS (*(volatile unsigned *)0x1000A00C) /* I2S״̬�Ĵ��� */
+
+
+/******************************************************************************************
+ * GPIOģ��
+ * ��ַ: 0x1000F000
+ ******************************************************************************************/
+
+#define GPIO_DBCLK_DIV (*(volatile unsigned *)0x1000F000) /* ȥë�̲���ʱ�ӷ�Ƶ�����üĴ��� */
+#define GPIO_PORTA_DIR (*(volatile unsigned *)0x1000F004) /* A��˿���������������üĴ��� */
+#define GPIO_PORTA_SEL (*(volatile unsigned *)0x1000F008) /* A��˿�ͨ����;ѡ�����üĴ��� */
+#define GPIO_PORTA_INCTL (*(volatile unsigned *)0x1000F00C) /* A��˿�ͨ����;����ʱ�������üĴ��� */
+#define GPIO_PORTA_INTRCTL (*(volatile unsigned *)0x1000F010) /* A��˿��жϴ����������üĴ��� */
+#define GPIO_PORTA_INTRCLR (*(volatile unsigned *)0x1000F014) /* A��˿�ͨ����;�ж�������üĴ��� */
+#define GPIO_PORTA_DATA (*(volatile unsigned *)0x1000F018) /* A��˿�ͨ����;�������üĴ��� */
+#define GPIO_PORTB_DIR (*(volatile unsigned *)0x1000F01C) /* B��˿���������������üĴ��� */
+#define GPIO_PORTB_SEL (*(volatile unsigned *)0x1000F020) /* B��˿�ͨ����;ѡ�����üĴ��� */
+#define GPIO_PORTB_DATA (*(volatile unsigned *)0x1000F024) /* B��˿�ͨ����;�������üĴ��� */
+#define GPIO_PORTC_DIR (*(volatile unsigned *)0x1000F028) /* C��˿���������������üĴ��� */
+#define GPIO_PORTC_SEL (*(volatile unsigned *)0x1000F02C) /* C��˿�ͨ����;ѡ�����üĴ��� */
+#define GPIO_PORTC_DATA (*(volatile unsigned *)0x1000F030) /* C��˿�ͨ����;�������üĴ��� */
+#define GPIO_PORTD_DIR (*(volatile unsigned *)0x1000F034) /* D��˿���������������üĴ��� */
+#define GPIO_PORTD_SEL (*(volatile unsigned *)0x1000F038) /* D��˿�ͨ����;ѡ�����üĴ��� */
+#define GPIO_PORTD_SPECII (*(volatile unsigned *)0x1000F03C) /* D��˿�ר����;2ѡ�����üĴ��� */
+#define GPIO_PORTD_DATA (*(volatile unsigned *)0x1000F040) /* D��˿�ͨ����;�������üĴ��� */
+#define GPIO_PORTE_DIR (*(volatile unsigned *)0x1000F044) /* E��˿���������������üĴ��� */
+#define GPIO_PORTE_SEL (*(volatile unsigned *)0x1000F048) /* E��˿�ͨ����;ѡ�����üĴ��� */
+#define GPIO_PORTE_DATA (*(volatile unsigned *)0x1000F04C) /* E��˿�ͨ����;�������üĴ��� */
+#define GPIO_PORTF_DIR (*(volatile unsigned *)0x1000F050) /* F��˿���������������üĴ��� */
+#define GPIO_PORTF_SEL (*(volatile unsigned *)0x1000F054) /* F��˿�ͨ����;ѡ�����üĴ��� */
+#define GPIO_PORTF_INCTL (*(volatile unsigned *)0x1000F058) /* F��˿�ͨ����;����ʱ�������üĴ��� */
+#define GPIO_PORTF_INTRCTL (*(volatile unsigned *)0x1000F05C) /* F��˿��жϴ����������üĴ��� */
+#define GPIO_PORTF_INTRCLR (*(volatile unsigned *)0x1000F060) /* F��˿�ͨ����;�ж�������üĴ��� */
+#define GPIO_PORTF_DATA (*(volatile unsigned *)0x1000F064) /* F��˿�ͨ����;�������üĴ��� */
+#define GPIO_PORTG_DIR (*(volatile unsigned *)0x1000F068) /* G��˿���������������üĴ��� */
+#define GPIO_PORTG_SEL (*(volatile unsigned *)0x1000F06C) /* G��˿�ͨ����;ѡ�����üĴ��� */
+#define GPIO_PORTG_DATA (*(volatile unsigned *)0x1000F070) /* G��˿�ͨ����;�������üĴ��� */
+#define GPIO_PORTH_DIR (*(volatile unsigned *)0x1000F074) /* H��˿���������������üĴ��� */
+#define GPIO_PORTH_SEL (*(volatile unsigned *)0x1000F078) /* H��˿�ͨ����;ѡ�����üĴ��� */
+#define GPIO_PORTH_DATA (*(volatile unsigned *)0x1000F07c) /* H��˿�ͨ����;�������üĴ��� */
+#define GPIO_PORTI_DIR (*(volatile unsigned *)0x1000F080) /* I��˿���������������üĴ��� */
+#define GPIO_PORTI_SEL (*(volatile unsigned *)0x1000F084) /* I��˿�ͨ����;ѡ�����üĴ��� */
+#define GPIO_PORTI_DATA (*(volatile unsigned *)0x1000F088) /* I��˿�ͨ����;�������üĴ��� */
+
+
+/******************************************************************************************
+ * SMC0ģ��
+ * ��ַ: 0x1000C000
+ ******************************************************************************************/
+
+#define SMC0_CTRL (*(volatile unsigned *)0x1000C000) /* SMC0���ƼĴ��� */
+#define SMC0_INT (*(volatile unsigned *)0x1000C004) /* SMC0�жϼĴ��� */
+#define SMC0_FD (*(volatile unsigned *)0x1000C008) /* SMC0������Ԫʱ��Ĵ��� */
+#define SMC0_CT (*(volatile unsigned *)0x1000C00C) /* SMC0�ַ�����ʱ��Ĵ��� */
+#define SMC0_BT (*(volatile unsigned *)0x1000C010) /* SMC0�鴫��ʱ��Ĵ��� */
+
+
+/******************************************************************************************
+ * SMC1ģ��
+ * ��ַ: 0x1000D000
+ ******************************************************************************************/
+
+#define SMC1_CTRL (*(volatile unsigned *)0x1000D000) /* SMC1���ƼĴ��� */
+#define SMC1_INT (*(volatile unsigned *)0x1000D004) /* SMC1�жϼĴ��� */
+#define SMC1_FD (*(volatile unsigned *)0x1000D008) /* SMC1������Ԫʱ��Ĵ��� */
+#define SMC1_CT (*(volatile unsigned *)0x1000D00C) /* SMC1�ַ�����ʱ��Ĵ��� */
+#define SMC1_BT (*(volatile unsigned *)0x1000D010) /* SMC1�鴫��ʱ��Ĵ��� */
+
+
+/******************************************************************************************
+ * USBDģ��
+ * ��ַ: 0x1000E000
+ ******************************************************************************************/
+
+#define USBD_PROTOCOLINTR (*(volatile unsigned *)0x1000E000) /* USBЭ���жϼĴ��� */
+#define USBD_INTRMASK (*(volatile unsigned *)0x1000E004) /* USB�ж����μĴ��� */
+#define USBD_INTRCTRL (*(volatile unsigned *)0x1000E008) /* USB�ж����Ϳ��ƼĴ��� */
+#define USBD_EPINFO (*(volatile unsigned *)0x1000E00C) /* USB��˵�״̬�Ĵ��� */
+#define USBD_BCONFIGURATIONVALUE (*(volatile unsigned *)0x1000E010) /* SET_CCONFIGURATION��¼ */
+#define USBD_BMATTRIBUTES (*(volatile unsigned *)0x1000E014) /* ��ǰ�������ԼĴ��� */
+#define USBD_DEVSPEED (*(volatile unsigned *)0x1000E018) /* ��ǰ�豸�����ٶȼĴ��� */
+#define USBD_FRAMENUMBER (*(volatile unsigned *)0x1000E01C) /* ��¼��ǰSOF���ڵ�֡�� */
+#define USBD_EPTRANSACTIONS0 (*(volatile unsigned *)0x1000E020) /* ��¼�´�Ҫ��Ĵ������ */
+#define USBD_EPTRANSACTIONS1 (*(volatile unsigned *)0x1000E024) /* ��¼�´�Ҫ��Ĵ������ */
+#define USBD_APPIFUPDATE (*(volatile unsigned *)0x1000E028) /* �ӿںſ��ٸ��¼Ĵ��� */
+#define USBD_CFGINTERFACE0 (*(volatile unsigned *)0x1000E02c) /* ��¼�ӿڵ�ֵ */
+#define USBD_CFGINTERFACE1 (*(volatile unsigned *)0x1000E030) /* ��¼�ӿڵ�ֵ */
+#define USBD_CFGINTERFACE2 (*(volatile unsigned *)0x1000E034) /* ��¼�ӿڵ�ֵ */
+#define USBD_CFGINTERFACE3 (*(volatile unsigned *)0x1000E038) /* ��¼�ӿڵ�ֵ */
+#define USBD_CFGINTERFACE4 (*(volatile unsigned *)0x1000E03c) /* ��¼�ӿڵ�ֵ */
+#define USBD_CFGINTERFACE5 (*(volatile unsigned *)0x1000E040) /* ��¼�ӿڵ�ֵ */
+#define USBD_CFGINTERFACE6 (*(volatile unsigned *)0x1000E044) /* ��¼�ӿڵ�ֵ */
+#define USBD_CFGINTERFACE7 (*(volatile unsigned *)0x1000E048) /* ��¼�ӿڵ�ֵ */
+#define USBD_CFGINTERFACE8 (*(volatile unsigned *)0x1000E04c) /* ��¼�ӿڵ�ֵ */
+#define USBD_CFGINTERFACE9 (*(volatile unsigned *)0x1000E050) /* ��¼�ӿڵ�ֵ */
+#define USBD_CFGINTERFACE10 (*(volatile unsigned *)0x1000E054) /* ��¼�ӿڵ�ֵ */
+#define USBD_CFGINTERFACE11 (*(volatile unsigned *)0x1000E058) /* ��¼�ӿڵ�ֵ */
+#define USBD_CFGINTERFACE12 (*(volatile unsigned *)0x1000E05c) /* ��¼�ӿڵ�ֵ */
+#define USBD_CFGINTERFACE13 (*(volatile unsigned *)0x1000E060) /* ��¼�ӿڵ�ֵ */
+#define USBD_CFGINTERFACE14 (*(volatile unsigned *)0x1000E064) /* ��¼�ӿڵ�ֵ */
+#define USBD_CFGINTERFACE15 (*(volatile unsigned *)0x1000E068) /* ��¼�ӿڵ�ֵ */
+#define USBD_CFGINTERFACE16 (*(volatile unsigned *)0x1000E06c) /* ��¼�ӿڵ�ֵ */
+#define USBD_CFGINTERFACE17 (*(volatile unsigned *)0x1000E070) /* ��¼�ӿڵ�ֵ */
+#define USBD_CFGINTERFACE18 (*(volatile unsigned *)0x1000E074) /* ��¼�ӿڵ�ֵ */
+#define USBD_CFGINTERFACE19 (*(volatile unsigned *)0x1000E078) /* ��¼�ӿڵ�ֵ */
+#define USBD_CFGINTERFACE20 (*(volatile unsigned *)0x1000E07c) /* ��¼�ӿڵ�ֵ */
+#define USBD_CFGINTERFACE21 (*(volatile unsigned *)0x1000E080) /* ��¼�ӿڵ�ֵ */
+#define USBD_CFGINTERFACE22 (*(volatile unsigned *)0x1000E084) /* ��¼�ӿڵ�ֵ */
+#define USBD_CFGINTERFACE23 (*(volatile unsigned *)0x1000E088) /* ��¼�ӿڵ�ֵ */
+#define USBD_CFGINTERFACE24 (*(volatile unsigned *)0x1000E08c) /* ��¼�ӿڵ�ֵ */
+#define USBD_CFGINTERFACE25 (*(volatile unsigned *)0x1000E090) /* ��¼�ӿڵ�ֵ */
+#define USBD_CFGINTERFACE26 (*(volatile unsigned *)0x1000E094) /* ��¼�ӿڵ�ֵ */
+#define USBD_CFGINTERFACE27 (*(volatile unsigned *)0x1000E098) /* ��¼�ӿڵ�ֵ */
+#define USBD_CFGINTERFACE28 (*(volatile unsigned *)0x1000E09c) /* ��¼�ӿڵ�ֵ */
+#define USBD_CFGINTERFACE29 (*(volatile unsigned *)0x1000E0a0) /* ��¼�ӿڵ�ֵ */
+#define USBD_CFGINTERFACE30 (*(volatile unsigned *)0x1000E0a4) /* ��¼�ӿڵ�ֵ */
+#define USBD_CFGINTERFACE31 (*(volatile unsigned *)0x1000E0a8) /* ��¼�ӿڵ�ֵ */
+#define USBD_PKTPASSEDCTRL (*(volatile unsigned *)0x1000E0ac) /* ��¼�ɹ����յİ��� */
+#define USBD_PKTDROPPEDCTRL (*(volatile unsigned *)0x1000E0b0) /* ��¼��ʧ�İ��� */
+#define USBD_CRCERRCTRL (*(volatile unsigned *)0x1000E0b4) /* ��¼CRC����İ��� */
+#define USBD_BITSTUFFERRCTRL (*(volatile unsigned *)0x1000E0b8) /* ��¼λ������İ��� */
+#define USBD_PIDERRCTRL (*(volatile unsigned *)0x1000E0bc) /* ��¼PID����İ��� */
+#define USBD_FRAMINGERRCTL (*(volatile unsigned *)0x1000E0c0) /* ��¼��SYNC��EOP�İ��� */
+#define USBD_TXPKTCTRL (*(volatile unsigned *)0x1000E0c4) /* ��¼���Ͱ������� */
+#define USBD_STATCTRLOV (*(volatile unsigned *)0x1000E0c8) /* ��¼ͳ�ƼĴ��������� */
+#define USBD_TXLENGTH (*(volatile unsigned *)0x1000E0cc) /* ��¼ÿ��IN������������� */
+#define USBD_RXLENGTH (*(volatile unsigned *)0x1000E0d0) /* ��¼OUT������������� */
+#define USBD_RESUME (*(volatile unsigned *)0x1000E0d4) /* USB���ѼĴ��� */
+#define USBD_READFLAG (*(volatile unsigned *)0x1000E0d8) /* ���첽״̬�Ĵ�����־ */
+#define USBD_RECEIVETYPE (*(volatile unsigned *)0x1000E0dc) /* ����״̬�Ĵ��� */
+#define USBD_APPLOCK (*(volatile unsigned *)0x1000E0e0) /* ���źżĴ��� */
+#define USBD_EP0OUTADDR (*(volatile unsigned *)0x1000E100) /* �˵�0�˵�źͷ��� */
+#define USBD_EP0OUTBMATTR (*(volatile unsigned *)0x1000E104) /* �˵�0���ͼĴ��� */
+#define USBD_EP0OUTMAXPKTSIZE (*(volatile unsigned *)0x1000E108) /* �˵�0�����ߴ�Ĵ��� */
+#define USBD_EP0OUTIFNUM (*(volatile unsigned *)0x1000E10c) /* �˵�0�ӿںżĴ��� */
+#define USBD_EP0OUTSTAT (*(volatile unsigned *)0x1000E110) /* �˵�0״̬�Ĵ��� */
+#define USBD_EP0OUTBMREQTYPE (*(volatile unsigned *)0x1000E114) /* �˵�0 SETUP���������� */
+#define USBD_EP0OUTBREQUEST (*(volatile unsigned *)0x1000E118) /* �˵�0 SETUP������������ */
+#define USBD_EP0OUTWVALUE (*(volatile unsigned *)0x1000E11c) /* �˵�0 SETUP��������ֵ */
+#define USBD_EP0OUTWINDEX (*(volatile unsigned *)0x1000E120) /* �˵�0 SETUP������������ */
+#define USBD_EP0OUTWLENGTH (*(volatile unsigned *)0x1000E120) /* �˵�0 SETUP�������� */
+#define USBD_EP0OUTSYNCHFRAME (*(volatile unsigned *)0x1000E128) /* �˵�0ͬ����֡�� */
+#define USBD_EP1OUTADDR (*(volatile unsigned *)0x1000E12c) /* �˵�1����˵�źͷ��� */
+#define USBD_EP1OUTBMATTR (*(volatile unsigned *)0x1000E130) /* �˵�1������ͼĴ��� */
+#define USBD_EP1OUTMAXPKTSIZE (*(volatile unsigned *)0x1000E134) /* �˵�1��������ߴ�Ĵ��� */
+#define USBD_EP1OUTIFNUM (*(volatile unsigned *)0x1000E138) /* �˵�1����ӿںżĴ��� */
+#define USBD_EP1OUTSTAT (*(volatile unsigned *)0x1000E13c) /* �˵�1���״̬�Ĵ��� */
+#define USBD_EP1OUTBMREQTYPE (*(volatile unsigned *)0x1000E140) /* �˵�1���SETUP������������ */
+#define USBD_EP1OUTBREQUEST (*(volatile unsigned *)0x1000E144) /* �˵�1���SETUP������������ */
+#define USBD_EP1OUTWVALUE (*(volatile unsigned *)0x1000E148) /* �˵�1���SETUP��������ֵ */
+#define USBD_EP1OUTWINDX (*(volatile unsigned *)0x1000E14c) /* �˵�1���SETUP������������ */
+#define USBD_EP1OUTWLENGH (*(volatile unsigned *)0x1000E150) /* �˵�1���SETUP���������� */
+#define USBD_EP1OUTSYNCHFRAME (*(volatile unsigned *)0x1000E154) /* �˵�1���ͬ����֡�� */
+#define USBD_EP1INADDR (*(volatile unsigned *)0x1000E158) /* �˵�1����˵�źͷ��� */
+#define USBD_EP1INBMATTR (*(volatile unsigned *)0x1000E15c) /* �˵�1�������ͼĴ��� */
+#define USBD_EP1INMAXPKTSIZE (*(volatile unsigned *)0x1000E160) /* �˵�1���������ߴ�Ĵ��� */
+#define USBD_EP1INIFNUM (*(volatile unsigned *)0x1000E164) /* �˵�1����ӿںżĴ��� */
+#define USBD_EP1INSTAT (*(volatile unsigned *)0x1000E168) /* �˵�1����״̬�Ĵ��� */
+#define USBD_EP1INBMREQTYPE (*(volatile unsigned *)0x1000E16c) /* �˵�1����SETUP������������ */
+#define USBD_EP1INBREQUEST (*(volatile unsigned *)0x1000E170) /* �˵�1����SETUP������������ */
+#define USBD_EP1INWVALUE (*(volatile unsigned *)0x1000E174) /* �˵�1����SETUP��������ֵ */
+#define USBD_EP1INWINDEX (*(volatile unsigned *)0x1000E178) /* �˵�1����SETUP������������ */
+#define USBD_EP1INWLENGTH (*(volatile unsigned *)0x1000E17c) /* �˵�1����SETUP���������� */
+#define USBD_EP1INSYNCHFRAME (*(volatile unsigned *)0x1000E180) /* �˵�1����ͬ����֡�� */
+#define USBD_EP2OUTADDR (*(volatile unsigned *)0x1000E184) /* �˵�2����˵�źͷ��� */
+#define USBD_EP2OUTBMATTR (*(volatile unsigned *)0x1000E188) /* �˵�2������ͼĴ��� */
+#define USBD_EP2OUTMAXPKTSIZE (*(volatile unsigned *)0x1000E18c) /* �˵�2��������ߴ�Ĵ��� */
+#define USBD_EP2OUTIFNUM (*(volatile unsigned *)0x1000E190) /* �˵�2����ӿںżĴ��� */
+#define USBD_EP2OUTSTAT (*(volatile unsigned *)0x1000E194) /* �˵�2���״̬�Ĵ��� */
+#define USBD_EP2OUTBMREQTYPE (*(volatile unsigned *)0x1000E198) /* �˵�2���SETUP������������ */
+#define USBD_EP2OUTBREQUEST (*(volatile unsigned *)0x1000E19c) /* �˵�2���SETUP������������ */
+#define USBD_EP2OUTWVALUE (*(volatile unsigned *)0x1000E1a0) /* �˵�2���SETUP��������ֵ */
+#define USBD_EP2OUTWINDEX (*(volatile unsigned *)0x1000E1a4) /* �˵�2���SETUP������������ */
+#define USBD_EP2OUTWLENGTH (*(volatile unsigned *)0x1000E1a8) /* �˵�2���SETUP���������� */
+#define USBD_EP2OUTSYNCHFRAME (*(volatile unsigned *)0x1000E1ac) /* �˵�2���ͬ����֡�� */
+#define USBD_EP2INADDR (*(volatile unsigned *)0x1000E1b0) /* �˵�2����˵�źͷ��� */
+#define USBD_EP2INBMATTR (*(volatile unsigned *)0x1000E1b4) /* �˵�2�������ͼĴ��� */
+#define USBD_EP2INMAXPKTSIZE (*(volatile unsigned *)0x1000E1b8) /* �˵�2���������ߴ�Ĵ��� */
+#define USBD_EP2INIFNUM (*(volatile unsigned *)0x1000E1bc) /* �˵�2����ӿںżĴ��� */
+#define USBD_EP2INSTAT (*(volatile unsigned *)0x1000E1c0) /* �˵�2����״̬�Ĵ��� */
+#define USBD_EP2INBMREQTYPE (*(volatile unsigned *)0x1000E1c4) /* �˵�2����SETUP������������ */
+#define USBD_EP2INBREQUEST (*(volatile unsigned *)0x1000E1c8) /* �˵�2����SETUP������������ */
+#define USBD_EP2INWVALUE (*(volatile unsigned *)0x1000E1cc) /* �˵�2����SETUP��������ֵ */
+#define USBD_EP2INWINDEX (*(volatile unsigned *)0x1000E1d0) /* �˵�2����SETUP������������ */
+#define USBD_EP2INWLENGTH (*(volatile unsigned *)0x1000E1d4) /* �˵�2����SETUP���������� */
+#define USBD_EP2INSYNCHFRAME (*(volatile unsigned *)0x1000E1d8) /* �˵�2����ͬ����֡�� */
+#define USBD_RXFIFO (*(volatile unsigned *)0x1000E200) /* ����FIFO */
+#define USBD_TXFIFO (*(volatile unsigned *)0x1000E300) /* ����FIFO */
+
+
+/******************************************************************************************
+ * EMIģ��
+ * ��ַ: 0x11000000
+ ******************************************************************************************/
+
+#define EMI_CSACONF (*(volatile unsigned *)0x11000000) /* CSA�������üĴ��� */
+#define EMI_CSBCONF (*(volatile unsigned *)0x11000004) /* CSB�������üĴ��� */
+#define EMI_CSCCONF (*(volatile unsigned *)0x11000008) /* CSC�������üĴ��� */
+#define EMI_CSDCONF (*(volatile unsigned *)0x1100000c) /* CSD�������üĴ��� */
+#define EMI_CSECONF (*(volatile unsigned *)0x11000010) /* CSE�������üĴ��� */
+#define EMI_CSFCONF (*(volatile unsigned *)0x11000014) /* CSF�������üĴ��� */
+#define EMI_SDCONF1 (*(volatile unsigned *)0x11000018) /* SDRAMʱ�����üĴ���1 */
+#define EMI_SDCONF2 (*(volatile unsigned *)0x1100001c) /* SDRAMʱ�����üĴ���2, SDRAM��ʼ���õ���������Ϣ */
+#define EMI_REMAPCONF (*(volatile unsigned *)0x11000020) /* Ƭѡ�ռ估��ַӳ��REMAP���üĴ��� */
+#define EMI_NAND_ADDR1 (*(volatile unsigned *)0x11000100) /* NAND FLASH�ĵ�ַ�Ĵ���1 */
+#define EMI_NAND_COM (*(volatile unsigned *)0x11000104) /* NAND FLASH�Ŀ����ּĴ��� */
+#define EMI_NAND_STA (*(volatile unsigned *)0x1100010c) /* NAND FLASH��״̬�Ĵ��� */
+#define EMI_ERR_ADDR1 (*(volatile unsigned *)0x11000110) /* �����������ĵ�ַ�Ĵ���1 */
+#define EMI_ERR_ADDR2 (*(volatile unsigned *)0x11000114) /* �����������ĵ�ַ�Ĵ���2 */
+#define EMI_NAND_CONF1 (*(volatile unsigned *)0x11000118) /* NAND FLASH������������1 */
+#define EMI_NAND_INTR (*(volatile unsigned *)0x1100011c) /* NAND FLASH�жϼĴ��� */
+#define EMI_NAND_ECC (*(volatile unsigned *)0x11000120) /* ECCУ����ɼĴ��� */
+#define EMI_NAND_IDLE (*(volatile unsigned *)0x11000124) /* NAND FLASH���мĴ��� */
+#define EMI_NAND_CONF2 (*(volatile unsigned *)0x11000128) /* NAND FLASH������������2 */
+#define EMI_NAND_ADDR2 (*(volatile unsigned *)0x1100012c) /* NAND FLASH�ĵ�ַ�Ĵ���2 */
+#define EMI_NAND_ID (*(volatile unsigned *)0x11000130) /* NAND FLASH��ID�Ĵ���*/
+#define EMI_NAND_DATA (*(volatile unsigned *)0x11000200) /* NAND FLASH�����ݼĴ��� */
+
+
+/******************************************************************************************
+ * DMACģ��
+ * ��ַ: 0x11001000
+ ******************************************************************************************/
+
+#define DMAC_INTSTATUS (*(volatile unsigned *)0x11001020) /* DAMC�ж�״̬�Ĵ����� */
+#define DMAC_INTTCSTATUS (*(volatile unsigned *)0x11001050) /* DMAC��������ж�״̬�Ĵ��� */
+#define DMAC_INTTCCLEAR (*(volatile unsigned *)0x11001060) /* DMAC��������ж�״̬����Ĵ��� */
+#define DMAC_INTERRORSTATUS (*(volatile unsigned *)0x11001080) /* DMAC��������ж�״̬�Ĵ��� */
+#define DMAC_INTERRCLR (*(volatile unsigned *)0x11001090) /* DMAC��������ж�״̬����Ĵ��� */
+#define DMAC_ENBLDCHNS (*(volatile unsigned *)0x110010b0) /* DMACͨ��ʹ��״̬�Ĵ��� */
+#define DMAC_C0SRCADDR (*(volatile unsigned *)0x11001000) /* DMAC��0Դ��ַ�Ĵ��� */
+#define DMAC_C0DESTADD (*(volatile unsigned *)0x11001004) /* DMAC��0Ŀ�ĵ�ַ�Ĵ��� */
+#define DMAC_C0CONTROL (*(volatile unsigned *)0x1100100c) /* DMAC��0���ƼĴ��� */
+#define DMAC_C0CONFIGURATION (*(volatile unsigned *)0x11001010) /* DMAC��0���üĴ��� */
+#define DMAC_C0DESCRIPTOR (*(volatile unsigned *)0x11001014) /* DMAC��0������ַ�Ĵ��� */
+#define DMAC_C1SRCADDR (*(volatile unsigned *)0x11001100) /* DMAC��1Դ��ַ�Ĵ��� */
+#define DMAC_C1DESTADDR (*(volatile unsigned *)0x11001104) /* DMAC��1Ŀ�ĵ�ַ�Ĵ��� */
+#define DMAC_C1CONTROL (*(volatile unsigned *)0x1100110c) /* DMAC��1���ƼĴ��� */
+#define DMAC_C1CONFIGURATION (*(volatile unsigned *)0x11001110) /* DMAC��1���üĴ��� */
+#define DMAC_C1DESCRIPTOR (*(volatile unsigned *)0x11001114) /* DMAC��1������ַ�Ĵ��� */
+#define DMAC_C2SRCADDR (*(volatile unsigned *)0x11001200) /* DMAC��2Դ��ַ�Ĵ��� */
+#define DMAC_C2DESTADDR (*(volatile unsigned *)0x11001204) /* DMAC��2Ŀ�ĵ�ַ�Ĵ��� */
+#define DMAC_C2CONTROL (*(volatile unsigned *)0x1100120c) /* DMAC��2���ƼĴ��� */
+#define DMAC_C2CONFIGURATION (*(volatile unsigned *)0x11001210) /* DMAC��2���üĴ��� */
+#define DMAC_C2DESCRIPTOR (*(volatile unsigned *)0x11001214) /* DMAC��2������ַ�Ĵ��� */
+#define DMAC_C3SRCADDR (*(volatile unsigned *)0x11001300) /* DMAC��3Դ��ַ�Ĵ��� */
+#define DMAC_C3DESTADDR (*(volatile unsigned *)0x11001304) /* DMAC��3Ŀ�ĵ�ַ�Ĵ��� */
+#define DMAC_C3CONTROL (*(volatile unsigned *)0x1100130c) /* DMAC��3���ƼĴ��� */
+#define DMAC_C3CONFIGURATION (*(volatile unsigned *)0x11001310) /* DMAC��3���üĴ��� */
+#define DMAC_C3DESCRIPTOR (*(volatile unsigned *)0x11001314) /* DMAC��3������ַ�Ĵ��� */
+#define DMAC_C4SRCADDR (*(volatile unsigned *)0x11001400) /* DMAC��4Դ��ַ�Ĵ��� */
+#define DMAC_C4DESTADDR (*(volatile unsigned *)0x11001404) /* DMAC��4Ŀ�ĵ�ַ�Ĵ��� */
+#define DMAC_C4CONTROL (*(volatile unsigned *)0x1100140c) /* DMAC��4���ƼĴ��� */
+#define DMAC_C4CONFIGURATION (*(volatile unsigned *)0x11001410) /* DMAC��4���üĴ��� */
+#define DMAC_C4DESCRIPTOR (*(volatile unsigned *)0x11001414) /* DMAC��4������ַ�Ĵ��� */
+#define DMAC_C5SRCADDR (*(volatile unsigned *)0x11001500) /* DMAC��5Դ��ַ�Ĵ��� */
+#define DMAC_C5DESTADDR (*(volatile unsigned *)0x11001504) /* DMAC��5Ŀ�ĵ�ַ�Ĵ��� */
+#define DMAC_C5CONTROL (*(volatile unsigned *)0x1100150c) /* DMAC��5���ƼĴ��� */
+#define DMAC_C5CONFIGURATION (*(volatile unsigned *)0x11001510) /* DMAC��5���üĴ��� */
+#define DMAC_C5DESCRIPTOR (*(volatile unsigned *)0x11001514) /* DMAC��5������ַ�Ĵ��� */
+
+
+/******************************************************************************************
+ * LCDCģ��
+ * ��ַ: 0x11002000
+ ******************************************************************************************/
+
+#define LCDC_SSA (*(volatile unsigned *)0x11002000) /* ��Ļ��ʼ��ַ�Ĵ��� */
+#define LCDC_SIZE (*(volatile unsigned *)0x11002004) /* ��Ļ�ߴ�Ĵ��� */
+#define LCDC_PCR (*(volatile unsigned *)0x11002008) /* ������üĴ��� */
+#define LCDC_HCR (*(volatile unsigned *)0x1100200c) /* ˮƽ���üĴ��� */
+#define LCDC_VCR (*(volatile unsigned *)0x11002010) /* ��ֱ���üĴ��� */
+#define LCDC_PWMR (*(volatile unsigned *)0x11002014) /* PWM�Աȶȿ��ƼĴ��� */
+#define LCDC_LECR (*(volatile unsigned *)0x11002018) /* ʹ�ܿ��ƼĴ��� */
+#define LCDC_DMACR (*(volatile unsigned *)0x1100201c) /* DMA���ƼĴ��� */
+#define LCDC_LCDISREN (*(volatile unsigned *)0x11002020) /* �ж�ʹ�ܼĴ��� */
+#define LCDC_LCDISR (*(volatile unsigned *)0x11002024) /* �ж�״̬�Ĵ��� */
+#define LCDC_LGPMR (*(volatile unsigned *)0x11002040) /* �Ҷȵ�ɫӳ��Ĵ����� */
+ /*(0x40-0x7c 16��32bit�Ĵ���) */
+
+
+/******************************************************************************************
+ * MACģ��
+ * ��ַ: 0x11003000
+ ******************************************************************************************/
+
+#define MAC_CTRL (*(volatile unsigned *)0x11003000) /* MAC���ƼĴ��� */
+#define MAC_INTSRC (*(volatile unsigned *)0x11003004) /* MAC�ж�Դ�Ĵ��� */
+#define MAC_INTMASK (*(volatile unsigned *)0x11003008) /* MAC�ж����μĴ��� */
+#define MAC_IPGT (*(volatile unsigned *)0x1100300c) /* ����֡����Ĵ��� */
+#define MAC_IPGR1 (*(volatile unsigned *)0x11003010) /* �ȴ����ڼĴ��� */
+#define MAC_IPGR2 (*(volatile unsigned *)0x11003014) /* �ȴ����ڼĴ��� */
+#define MAC_PACKETLEN (*(volatile unsigned *)0x11003018) /* ֡���ȼĴ��� */
+#define MAC_COLLCONF (*(volatile unsigned *)0x1100301c) /* ��ײ�ط��Ĵ��� */
+#define MAC_TXBD_NUM (*(volatile unsigned *)0x11003020) /* �����������Ĵ��� */
+#define MAC_FLOWCTRL (*(volatile unsigned *)0x11003024) /* ���ؼĴ��� */
+#define MAC_MII_CTRL (*(volatile unsigned *)0x11003028) /* PHY���ƼĴ��� */
+#define MAC_MII_CMD (*(volatile unsigned *)0x1100302c) /* PHY����Ĵ��� */
+#define MAC_MII_ADDRESS (*(volatile unsigned *)0x11003030) /* PHY��ַ�Ĵ��� */
+#define MAC_MII_TXDATA (*(volatile unsigned *)0x11003034) /* PHYд���ݼĴ��� */
+#define MAC_MII_RXDATA (*(volatile unsigned *)0x11003038) /* PHY�����ݼĴ��� */
+#define MAC_MII_STATUS (*(volatile unsigned *)0x1100303c) /* PHY״̬�Ĵ��� */
+#define MAC_ADDR0 (*(volatile unsigned *)0x11003040) /* MAC��ַ�Ĵ��� */
+#define MAC_ADDR1 (*(volatile unsigned *)0x11003044) /* MAC��ַ�Ĵ��� */
+#define MAC_HASH0 (*(volatile unsigned *)0x11003048) /* MAC HASH�Ĵ��� */
+#define MAC_HASH1 (*(volatile unsigned *)0x1100304c) /* MAC HASH�Ĵ��� */
+#define MAC_TXPAUSE (*(volatile unsigned *)0x11003050) /* MAC����֡�Ĵ��� */
+#define MAC_BD /* 0x4*/
+
+
+#endif
+
+/*******************END OF FILE*************************/
diff --git a/bsp/sep4020/startup.c b/bsp/sep4020/startup.c new file mode 100644 index 0000000000..e642fcdaf7 --- /dev/null +++ b/bsp/sep4020/startup.c @@ -0,0 +1,132 @@ +/* + * File : startup.c + * This file is part of RT-Thread RTOS + * COPYRIGHT (C) 2006, RT-Thread Develop Team + * + * The license and distribution terms for this file may be + * found in the file LICENSE in this distribution or at + * http://openlab.rt-thread.com/license/LICENSE + * + * Change Logs: + * Date Author Notes + * 2006-08-31 Bernard first implementation + */ + +#include <rthw.h> +#include <rtthread.h> + +#include "board.h" + +/** + * @addtogroup STM32 + */ + +/*@{*/ + +extern int rt_application_init(void);
+
+#ifdef RT_USING_FINSH
+extern void finsh_system_init(void);
+extern void finsh_set_device(const char* device);
+#endif + +#ifdef __CC_ARM +extern int Image$$RW_RAM1$$ZI$$Limit; +#elif __ICCARM__ +#pragma section="HEAP" +#else +extern int __bss_end; +#endif + +#ifdef DEBUG +/******************************************************************************* +* Function Name : assert_failed +* Description : Reports the name of the source file and the source line number +* where the assert error has occurred. +* Input : - file: pointer to the source file name +* - line: assert error line source number +* Output : None +* Return : None +*******************************************************************************/ +void assert_failed(u8* file, u32 line) +{ + rt_kprintf("\n\r Wrong parameter value detected on\r\n"); + rt_kprintf(" file %s\r\n", file); + rt_kprintf(" line %d\r\n", line); + + while (1) ; +} +#endif + +/** + * This function will startup RT-Thread RTOS. + */ +void rtthread_startup(void) +{
+ /* init hardware interrupt */ + rt_hw_interrupt_init(); + /* init board */ + rt_hw_board_init(); + + /* show version */ + rt_show_version(); + + /* init tick */ + rt_system_tick_init(); + + /* init kernel object */ + rt_system_object_init(); + + /* init timer system */ + rt_system_timer_init(); + +#ifdef RT_USING_HEAP + #ifdef __CC_ARM + rt_system_heap_init((void*)&Image$$RW_RAM1$$ZI$$Limit, (void*)0x32000000); + #elif __ICCARM__ + rt_system_heap_init(__segment_end("HEAP"), (void*)STM32_SRAM_END); + #else + /* init memory system */ + rt_system_heap_init((void*)&__bss_end, (void*)STM32_SRAM_END); + #endif +#endif + + /* init scheduler system */ + rt_system_scheduler_init(); + + /* init all device */ + rt_device_init_all(); + + /* init application */ + rt_application_init();
+
+#ifdef RT_USING_FINSH
+ /* init finsh */
+ finsh_system_init();
+ finsh_set_device("uart0");
+#endif + + /* init idle thread */ + rt_thread_idle_init(); + + /* start scheduler */ + rt_system_scheduler_start(); + + /* never reach here */ + return ; +} + +int main(void) +{ + rt_uint32_t UNUSED level; + + /* disable interrupt first */ + level = rt_hw_interrupt_disable(); + + /* startup RT-Thread RTOS */ + rtthread_startup(); + + return 0; +} + +/*@}*/ diff --git a/libcpu/arm/sep4020/clk.c b/libcpu/arm/sep4020/clk.c new file mode 100644 index 0000000000..7b298ea825 --- /dev/null +++ b/libcpu/arm/sep4020/clk.c @@ -0,0 +1,112 @@ +/*
+ * File : clock.c
+ * This file is part of RT-Thread RTOS
+ * COPYRIGHT (C) 2006, RT-Thread Development Team
+ *
+ * The license and distribution terms for this file may be
+ * found in the file LICENSE in this distribution or at
+ * http://openlab.rt-thread.com/license/LICENSE
+ *
+ * Change Logs:
+ * Date Author Notes
+ * 2010-03-20 zchong first version
+ */
+
+#include <rtthread.h>
+#include "sep4020.h"
+
+#define CLK_IN 4000000 /* Fin = 4.00MHz */
+#define SYSCLK 72000000 /* system clock we want */
+
+#define CLK_ESRAM 0
+#define CLK_LCDC 1
+#define CLK_PWM 2
+#define CLK_DMAC 3
+#define CLK_EMI 4
+#define CLK_MMCSD 5
+#define CLK_SSI 7
+#define CLK_UART0 8
+#define CLK_UART1 9
+#define CLK_UART2 10
+#define CLK_UART3 11
+#define CLK_USB 12
+#define CLK_MAC 13
+#define CLK_SMC 14
+#define CLK_I2C 15
+#define CLK_GPT 16
+
+static void rt_hw_set_system_clock(void)
+{
+ rt_uint8_t pv;
+
+ /* pv value*/
+ pv = SYSCLK/2/CLK_IN;
+ /* go to normal mode*/
+ PMC_PMDR = 0x01;
+ /* set the clock */
+ PMC_PMCR = 0x4000 | pv;
+ /* trige configurate*/
+ PMC_PMCR = 0xc000 | pv;
+}
+
+static void rt_hw_set_usb_clock(void)
+{
+ /* set the clock */
+ PMC_PUCR = 0x000c;
+ /* trige configurate*/
+ PMC_PMCR = 0x800c;
+
+}
+
+/**
+ * @brief System Clock Configuration
+ */
+void rt_hw_clock_init(void)
+{
+ /* set system clock */
+ rt_hw_set_system_clock();
+ /* set usb clock */
+ rt_hw_set_usb_clock();
+}
+
+/**
+ * @brief Get system clock
+ */
+rt_uint32_t rt_hw_get_clock(void)
+{
+ rt_uint32_t val;
+ rt_uint8_t pv, pd, npd;
+
+ /* get PMCR value */
+ val = PMC_PMCR;
+ /* get NPD */
+ npd = (val >> 14) & 0x01;
+ /* get PD */
+ pd = (val >> 10) & 0x0f;
+ /* get PV */
+ pv = val & 0x7f;
+ /* caculate the system clock */
+ if(npd)
+ val = 2 * CLK_IN * pv;
+ else
+ val = CLK_IN * pv / (pd + 1);
+
+ return(val);
+}
+
+/**
+ * @brief Enable module clock
+ */
+ void rt_hw_enable_module_clock(rt_uint8_t module)
+ {
+
+ }
+
+/**
+ * @brief Disable module clock
+ */
+ void rt_hw_disable_module_clock(rt_uint8_t module)
+ {
+
+ }
+
diff --git a/libcpu/arm/sep4020/context_rvds.S b/libcpu/arm/sep4020/context_rvds.S new file mode 100644 index 0000000000..82c5adc574 --- /dev/null +++ b/libcpu/arm/sep4020/context_rvds.S @@ -0,0 +1,107 @@ +;/* +; * File : context_rvds.S +; * This file is part of RT-Thread RTOS +; * COPYRIGHT (C) 2006, RT-Thread Development Team +; * +; * The license and distribution terms for this file may be +; * found in the file LICENSE in this distribution or at +; * http://www.rt-thread.org/license/LICENSE +; * +; * Change Logs: +; * Date Author Notes +; * 2009-01-20 Bernard first version +; */ + +NOINT EQU 0xc0 ; disable interrupt in psr
+ + AREA |.text|, CODE, READONLY, ALIGN=2
+ ARM
+ REQUIRE8
+ PRESERVE8
+ +;/* +; * rt_base_t rt_hw_interrupt_disable(); +; */ +rt_hw_interrupt_disable PROC + EXPORT rt_hw_interrupt_disable + MRS r0, cpsr + ORR r1, r0, #NOINT + MSR cpsr_c, r1
+ BX lr + ENDP
+ +;/* +; * void rt_hw_interrupt_enable(rt_base_t level); +; */ +rt_hw_interrupt_enable PROC + EXPORT rt_hw_interrupt_enable + MSR cpsr_c, r0
+ BX lr + ENDP + +;/* +; * void rt_hw_context_switch(rt_uint32 from, rt_uint32 to); +; * r0 --> from +; * r1 --> to +; */ +rt_hw_context_switch PROC + EXPORT rt_hw_context_switch + STMFD sp!, {lr} ; push pc (lr should be pushed in place of PC) + STMFD sp!, {r0-r12, lr} ; push lr & register file + + MRS r4, cpsr + STMFD sp!, {r4} ; push cpsr + MRS r4, spsr + STMFD sp!, {r4} ; push spsr + + STR sp, [r0] ; store sp in preempted tasks TCB + LDR sp, [r1] ; get new task stack pointer + + LDMFD sp!, {r4} ; pop new task spsr + MSR spsr_cxsf, r4 + LDMFD sp!, {r4} ; pop new task cpsr + MSR cpsr_cxsf, r4 + + LDMFD sp!, {r0-r12, lr, pc} ; pop new task r0-r12, lr & pc + ENDP
+ +;/* +; * void rt_hw_context_switch_to(rt_uint32 to); +; * r0 --> to +; */ +rt_hw_context_switch_to PROC + EXPORT rt_hw_context_switch_to + LDR sp, [r0] ; get new task stack pointer + + LDMFD sp!, {r4} ; pop new task spsr + MSR spsr_cxsf, r4 + LDMFD sp!, {r4} ; pop new task cpsr + MSR cpsr_cxsf, r4 + + LDMFD sp!, {r0-r12, lr, pc} ; pop new task r0-r12, lr & pc + ENDP
+ +;/* +; * void rt_hw_context_switch_interrupt(rt_uint32 from, rt_uint32 to); +; */ + IMPORT rt_thread_switch_interrput_flag + IMPORT rt_interrupt_from_thread + IMPORT rt_interrupt_to_thread
+ +rt_hw_context_switch_interrupt PROC + EXPORT rt_hw_context_switch_interrupt + LDR r2, =rt_thread_switch_interrput_flag + LDR r3, [r2] + CMP r3, #1 + BEQ _reswitch + MOV r3, #1 ; set rt_thread_switch_interrput_flag to 1 + STR r3, [r2] + LDR r2, =rt_interrupt_from_thread ; set rt_interrupt_from_thread + STR r0, [r2] +_reswitch + LDR r2, =rt_interrupt_to_thread ; set rt_interrupt_to_thread + STR r1, [r2]
+ BX lr + ENDP
+
+ END
\ No newline at end of file diff --git a/libcpu/arm/sep4020/cpu.c b/libcpu/arm/sep4020/cpu.c new file mode 100644 index 0000000000..1905da812e --- /dev/null +++ b/libcpu/arm/sep4020/cpu.c @@ -0,0 +1,42 @@ +/* + * File : cpu.c + * This file is part of RT-Thread RTOS + * COPYRIGHT (C) 2006, RT-Thread Develop Team + * + * The license and distribution terms for this file may be + * found in the file LICENSE in this distribution or at + * http://www.rt-thread.org/license/LICENSE + * + * Change Logs: + * Date Author Notes + * 2006-08-23 Bernard first version + */ + +#include <rtthread.h> + + +/** + * @addtogroup AT91SAM7X + */ +/*@{*/ + +/** + * this function will reset CPU + * + */ +void rt_hw_cpu_reset() +{ +} + +/** + * this function will shutdown CPU + * + */ +void rt_hw_cpu_shutdown() +{ + rt_kprintf("shutdown...\n"); + + while (1); +} + +/*@}*/ diff --git a/libcpu/arm/sep4020/interrupt.c b/libcpu/arm/sep4020/interrupt.c new file mode 100644 index 0000000000..810e0185b7 --- /dev/null +++ b/libcpu/arm/sep4020/interrupt.c @@ -0,0 +1,107 @@ +/* + * File : trap.c + * This file is part of RT-Thread RTOS + * COPYRIGHT (C) 2006, RT-Thread Development Team + * + * The license and distribution terms for this file may be + * found in the file LICENSE in this distribution or at + * http://openlab.rt-thread.com/license/LICENSE + * + * Change Logs: + * Date Author Notes + * 2006-08-23 Bernard first version
+ * 2010-03-17 zchong SEP4020 + */ + +#include <rtthread.h> +#include "sep4020.h" + +#define MAX_HANDLERS 32 + +extern rt_uint32_t rt_interrupt_nest;
+ +/* exception and interrupt handler table */
+rt_isr_handler_t isr_table[MAX_HANDLERS]; +rt_uint32_t rt_interrupt_from_thread, rt_interrupt_to_thread; +rt_uint32_t rt_thread_switch_interrput_flag; + +/** + * @addtogroup SEP4020 + */ +/*@{*/ + +void rt_hw_interrupt_handler(int vector) +{ + rt_kprintf("Unhandled interrupt %d occured!!!\n", vector); +} + +/** + * This function will initialize hardware interrupt + */ +void rt_hw_interrupt_init() +{ + register rt_uint32_t idx;
+
+ /* disable all interrupts */
+ INTC_IER = 0x0;
+
+ /* mask all interrupts */
+ INTC_IMR = 0xFFFFFFFF; + + /* init exceptions table */
+ for(idx=0; idx < MAX_HANDLERS; idx++)
+ {
+ isr_table[idx] = (rt_isr_handler_t)rt_hw_interrupt_handler;
+ } + + /* init interrupt nest, and context in thread sp */ + rt_interrupt_nest = 0; + rt_interrupt_from_thread = 0; + rt_interrupt_to_thread = 0; + rt_thread_switch_interrput_flag = 0; +} + +/** + * This function will mask a interrupt. + * @param vector the interrupt number + */ +void rt_hw_interrupt_mask(int vector) +{
+ INTC_IMR |= 1 << vector; +} + +/** + * This function will un-mask a interrupt. + * @param vector the interrupt number + */ +void rt_hw_interrupt_umask(int vector) +{
+ /* un-mask interrupt */ + if ((vector == INT_NOTUSED0) || (vector == INT_NOTUSED16))
+ {
+ rt_kprintf("Interrupt vec %d is not used!\n", vector);
+ // while(1);
+ }
+ else if (vector == INTGLOBAL)
+ INTC_IMR = 0x0;
+ else
+ INTC_IMR &= ~(1 << vector);
+ +} + +/** + * This function will install a interrupt service routine to a interrupt. + * @param vector the interrupt number + * @param new_handler the interrupt service routine to be installed + * @param old_handler the old interrupt service routine + */ +void rt_hw_interrupt_install(int vector, rt_isr_handler_t new_handler, rt_isr_handler_t *old_handler) +{ + if(vector >= 0 && vector < MAX_HANDLERS) + { + if (*old_handler != RT_NULL) *old_handler = isr_table[vector];
+ if (new_handler != RT_NULL) isr_table[vector] = new_handler; + } +} + +/*@}*/ diff --git a/libcpu/arm/sep4020/serial.c b/libcpu/arm/sep4020/serial.c new file mode 100644 index 0000000000..7f50348335 --- /dev/null +++ b/libcpu/arm/sep4020/serial.c @@ -0,0 +1,281 @@ +/*
+ * File : serial.c
+ * This file is part of RT-Thread RTOS
+ * COPYRIGHT (C) 2009, RT-Thread Development Team
+ *
+ * The license and distribution terms for this file may be
+ * found in the file LICENSE in this distribution or at
+ * http://www.rt-thread.org/license/LICENSE
+ *
+ * Change Logs:
+ * Date Author Notes
+ * 2009-02-05 Bernard first version
+ * 2009-10-25 Bernard fix rt_serial_read bug when there is no data
+ * in the buffer.
+ * 2010-03-29 Bernard cleanup code.
+ * 2010-06-14 zchong for sep4020
+ */
+
+#include "serial.h"
+
+/**
+ * @addtogroup SEP4020
+ */
+/*@{*/
+
+/* RT-Thread Device Interface */
+static rt_err_t rt_serial_init (rt_device_t dev)
+{
+ struct serial_device* uart = (struct serial_device*) dev->private;
+
+ if (!(dev->flag & RT_DEVICE_FLAG_ACTIVATED))
+ {
+
+ if (dev->flag & RT_DEVICE_FLAG_INT_RX)
+ {
+ rt_memset(uart->int_rx->rx_buffer, 0,
+ sizeof(uart->int_rx->rx_buffer));
+ uart->int_rx->read_index = uart->int_rx->save_index = 0;
+ }
+
+ if (dev->flag & RT_DEVICE_FLAG_INT_TX)
+ {
+ rt_memset(uart->int_tx->tx_buffer, 0,
+ sizeof(uart->int_tx->tx_buffer));
+ uart->int_tx->write_index = uart->int_tx->save_index = 0;
+ }
+
+ dev->flag |= RT_DEVICE_FLAG_ACTIVATED;
+ }
+
+ return RT_EOK;
+}
+
+static rt_err_t rt_serial_open(rt_device_t dev, rt_uint16_t oflag)
+{
+ return RT_EOK;
+}
+
+static rt_err_t rt_serial_close(rt_device_t dev)
+{
+ return RT_EOK;
+}
+
+static rt_size_t rt_serial_read (rt_device_t dev, rt_off_t pos, void* buffer, rt_size_t size)
+{
+ rt_uint8_t* ptr;
+ rt_err_t err_code;
+ struct serial_device* uart;
+
+ ptr = buffer;
+ err_code = RT_EOK;
+ uart = (struct serial_device*)dev->private;
+
+ if (dev->flag & RT_DEVICE_FLAG_INT_RX)
+ {
+ /* interrupt mode Rx */
+ while (size)
+ {
+ rt_base_t level;
+
+ /* disable interrupt */
+ level = rt_hw_interrupt_disable();
+
+ if (uart->int_rx->read_index != uart->int_rx->save_index)
+ {
+ /* read a character */
+ *ptr++ = uart->int_rx->rx_buffer[uart->int_rx->read_index];
+ size--;
+
+ /* move to next position */
+ uart->int_rx->read_index ++;
+ if (uart->int_rx->read_index >= UART_RX_BUFFER_SIZE)
+ uart->int_rx->read_index = 0;
+ }
+ else
+ {
+ /* set error code */
+ err_code = -RT_EEMPTY;
+
+ /* enable interrupt */
+ rt_hw_interrupt_enable(level);
+ break;
+ }
+
+ /* enable interrupt */
+ rt_hw_interrupt_enable(level);
+ }
+ }
+ else
+ {
+ /* polling mode */
+ while ((rt_uint32_t)ptr - (rt_uint32_t)buffer < size)
+ {
+ while (uart->uart_device->lsr & USTAT_RCV_READY)
+ {
+ *ptr = uart->uart_device->dlbl_rxfifo_txfifo & 0xff;
+ ptr ++;
+ }
+ }
+ }
+
+ /* set error code */
+ rt_set_errno(err_code);
+ return (rt_uint32_t)ptr - (rt_uint32_t)buffer;
+}
+
+
+static rt_size_t rt_serial_write (rt_device_t dev, rt_off_t pos, const void* buffer, rt_size_t size)
+{
+ rt_uint8_t* ptr;
+ rt_err_t err_code;
+ struct serial_device* uart;
+
+ err_code = RT_EOK;
+ ptr = (rt_uint8_t*)buffer;
+ uart = (struct serial_device*)dev->private;
+
+ if (dev->flag & RT_DEVICE_FLAG_INT_TX)
+ {
+ /* interrupt mode Tx */
+ while (uart->int_tx->save_index != uart->int_tx->write_index)
+ {
+ /* save on tx buffer */
+ uart->int_tx->tx_buffer[uart->int_tx->save_index] = *ptr++;
+
+ -- size;
+
+ /* move to next position */
+ uart->int_tx->save_index ++;
+
+ /* wrap save index */
+ if (uart->int_tx->save_index >= UART_TX_BUFFER_SIZE)
+ uart->int_tx->save_index = 0;
+ }
+
+ /* set error code */
+ if (size > 0)
+ err_code = -RT_EFULL;
+ }
+ else
+ {
+ /* polling mode */
+ while (size)
+ {
+ /*
+ * to be polite with serial console add a line feed
+ * to the carriage return character
+ */
+ if (*ptr == '\n' && (dev->flag & RT_DEVICE_FLAG_STREAM))
+ {
+ while (!(uart->uart_device->lsr & USTAT_TXB_EMPTY));
+ uart->uart_device->dlbl_rxfifo_txfifo = '\r';
+ }
+
+ while (!(uart->uart_device->lsr & USTAT_TXB_EMPTY));
+ uart->uart_device->dlbl_rxfifo_txfifo = (*ptr & 0x1FF);
+
+ ++ptr; --size;
+ }
+ }
+
+ /* set error code */
+ rt_set_errno(err_code);
+
+ return (rt_uint32_t)ptr - (rt_uint32_t)buffer;
+}
+
+static rt_err_t rt_serial_control (rt_device_t dev, rt_uint8_t cmd, void *args)
+{
+// struct serial_device* uart;
+
+ RT_ASSERT(dev != RT_NULL);
+
+// uart = (struct serial_device*)dev->private;
+ switch (cmd)
+ {
+ case RT_DEVICE_CTRL_SUSPEND:
+ /* suspend device */
+ dev->flag |= RT_DEVICE_FLAG_SUSPENDED;
+ break;
+
+ case RT_DEVICE_CTRL_RESUME:
+ /* resume device */
+ dev->flag &= ~RT_DEVICE_FLAG_SUSPENDED;
+ break;
+ }
+
+ return RT_EOK;
+}
+
+/*
+ * serial register for SEP4020
+ */
+rt_err_t rt_hw_serial_register(rt_device_t device, const char* name, rt_uint32_t flag, struct serial_device *serial)
+{
+ RT_ASSERT(device != RT_NULL);
+
+
+ device->type = RT_Device_Class_Char;
+ device->rx_indicate = RT_NULL;
+ device->tx_complete = RT_NULL;
+ device->init = rt_serial_init;
+ device->open = rt_serial_open;
+ device->close = rt_serial_close;
+ device->read = rt_serial_read;
+ device->write = rt_serial_write;
+ device->control = rt_serial_control;
+ device->private = serial;
+
+ /* register a character device */
+ return rt_device_register(device, name, RT_DEVICE_FLAG_RDWR | flag);
+}
+
+/* ISR for serial interrupt */
+void rt_hw_serial_isr(rt_device_t device)
+{
+ rt_base_t level;
+ struct serial_device* uart = (struct serial_device*) device->private;
+
+ /* interrupt mode receive */
+ RT_ASSERT(device->flag & RT_DEVICE_FLAG_INT_RX);
+
+ /* save on rx buffer */
+ while (uart->uart_device->lsr & USTAT_RCV_READY)
+ {
+ /* disable interrupt */
+ level = rt_hw_interrupt_disable();
+
+ uart->int_rx->rx_buffer[uart->int_rx->save_index] = uart->uart_device->dlbl_rxfifo_txfifo & 0xff;
+ uart->int_rx->save_index ++;
+ if (uart->int_rx->save_index >= UART_RX_BUFFER_SIZE)
+ uart->int_rx->save_index = 0;
+
+ /* if the next position is read index, discard this 'read char' */
+ if (uart->int_rx->save_index == uart->int_rx->read_index)
+ {
+ uart->int_rx->read_index ++;
+ if (uart->int_rx->read_index >= UART_RX_BUFFER_SIZE)
+ uart->int_rx->read_index = 0;
+ }
+
+ /* enable interrupt */
+ rt_hw_interrupt_enable(level);
+ }
+
+ /* invoke callback */
+ if (device->rx_indicate != RT_NULL)
+ {
+ rt_size_t rx_length;
+
+ /* get rx length */
+ rx_length = uart->int_rx->read_index > uart->int_rx->save_index ?
+ UART_RX_BUFFER_SIZE - uart->int_rx->read_index + uart->int_rx->save_index :
+ uart->int_rx->save_index - uart->int_rx->read_index;
+
+ device->rx_indicate(device, rx_length);
+ }
+}
+
+
+/*@}*/
diff --git a/libcpu/arm/sep4020/serial.h b/libcpu/arm/sep4020/serial.h new file mode 100644 index 0000000000..391cbe16e9 --- /dev/null +++ b/libcpu/arm/sep4020/serial.h @@ -0,0 +1,56 @@ +#ifndef __RT_SERIAL_H__
+#define __RT_SERIAL_H__
+
+#include <rthw.h>
+#include <rtthread.h>
+
+
+#define USTAT_RCV_READY 0x01 /* receive data ready */
+#define USTAT_TXB_EMPTY 0x20 /* tx buffer empty */
+#define BPS 115200 /* serial baudrate */
+
+#define UART_RX_BUFFER_SIZE 64
+#define UART_TX_BUFFER_SIZE 64
+
+struct serial_int_rx
+{
+ rt_uint8_t rx_buffer[UART_RX_BUFFER_SIZE];
+ rt_uint32_t read_index, save_index;
+};
+
+struct serial_int_tx
+{
+ rt_uint8_t tx_buffer[UART_TX_BUFFER_SIZE];
+ rt_uint32_t write_index, save_index;
+};
+
+/* serial port registers */
+typedef struct uartport
+{
+ rt_uint32_t dlbl_rxfifo_txfifo;
+ rt_uint32_t dlbh_ier;
+ rt_uint32_t iir_fcr;
+ rt_uint32_t lcr;
+ rt_uint32_t mcr;
+ rt_uint32_t lsr;
+ rt_uint32_t msr;
+}uartport;
+
+struct serial_device
+{
+ /* uart hardware registers */
+ uartport* uart_device;
+
+ /* rx structure */
+ struct serial_int_rx* int_rx;
+
+ /* tx structure */
+ struct serial_int_tx* int_tx;
+};
+
+rt_err_t rt_hw_serial_register(rt_device_t device, const char* name, rt_uint32_t flag, struct serial_device *serial);
+
+void rt_hw_serial_isr(rt_device_t device);
+
+#endif
+
diff --git a/libcpu/arm/sep4020/stack.c b/libcpu/arm/sep4020/stack.c new file mode 100644 index 0000000000..6060b63722 --- /dev/null +++ b/libcpu/arm/sep4020/stack.c @@ -0,0 +1,61 @@ +/* + * File : stack.c + * This file is part of RT-Thread RTOS + * COPYRIGHT (C) 2006, RT-Thread Development Team + * + * The license and distribution terms for this file may be + * found in the file LICENSE in this distribution or at + * http://openlab.rt-thread.com/license/LICENSE + * + * Change Logs: + * Date Author Notes + * 2006-08-23 Bernard the first version + */ +#include <rtthread.h> + +#define SVCMODE 0x13 + +/** + * @addtogroup AT91SAM7 + */ +/*@{*/ + +/** + * This function will initialize thread stack + * + * @param tentry the entry of thread + * @param parameter the parameter of entry + * @param stack_addr the beginning stack address + * @param texit the function will be called when thread exit + * + * @return stack address + */ +rt_uint8_t *rt_hw_stack_init(void *tentry, void *parameter, + rt_uint8_t *stack_addr, void *texit) +{ + unsigned long *stk; + + stk = (unsigned long *)stack_addr; + *(stk) = (unsigned long)tentry; /* entry point */ + *(--stk) = (unsigned long)texit; /* lr */ + *(--stk) = 0; /* r12 */ + *(--stk) = 0; /* r11 */ + *(--stk) = 0; /* r10 */ + *(--stk) = 0; /* r9 */ + *(--stk) = 0; /* r8 */ + *(--stk) = 0; /* r7 */ + *(--stk) = 0; /* r6 */ + *(--stk) = 0; /* r5 */ + *(--stk) = 0; /* r4 */ + *(--stk) = 0; /* r3 */ + *(--stk) = 0; /* r2 */ + *(--stk) = 0; /* r1 */ + *(--stk) = (unsigned long)parameter; /* r0 : argument */ + *(--stk) = SVCMODE; /* cpsr */ + *(--stk) = SVCMODE; /* spsr */ + + /* return task's current stack address */ + return (rt_uint8_t *)stk; +} + +/*@}*/ diff --git a/libcpu/arm/sep4020/start_rvds.S b/libcpu/arm/sep4020/start_rvds.S new file mode 100644 index 0000000000..6de4ee54a8 --- /dev/null +++ b/libcpu/arm/sep4020/start_rvds.S @@ -0,0 +1,374 @@ +;==============================================================================================
+; star_rvds.s for Keil MDK 4.10
+;
+; SEP4020 start up code
+;
+; Change Logs: +; Date Author Notes
+; 2010-03-17 zchong
+;=============================================================================================
+
+;
+
+PMU_PLTR EQU 0x10001000 ; PLL���ȶ�����ʱ��
+PMU_PMCR EQU 0x10001004 ; ϵͳ��ʱ��PLL�Ŀ��ƼĴ���
+PMU_PUCR EQU 0x10001008 ; USBʱ��PLL�Ŀ��ƼĴ���
+PMU_PCSR EQU 0x1000100C ; �ڲ�ģ��ʱ��Դ�����Ŀ��ƼĴ���
+PMU_PDSLOW EQU 0x10001010 ; SLOW״̬��ʱ�ӵķ�Ƶ����
+PMU_PMDR EQU 0x10001014 ; оƬ����ģʽ�Ĵ���
+PMU_RCTR EQU 0x10001018 ; Reset���ƼĴ���
+PMU_CLRWAKUP EQU 0x1000101C ; WakeUp����Ĵ���
+
+RTC_CTR EQU 0x1000200C ; RTC���ƼĴ���
+
+INTC_IER EQU 0x10000000 ; IRQ�ж������Ĵ���
+INTC_IMR EQU 0x10000008 ; IRQ�ж����μĴ���
+INTC_IFSR EQU 0x10000030 ; IRQ�ж�����״̬�Ĵ���
+INTC_FIER EQU 0x100000C0 ; FIQ�ж������Ĵ���
+INTC_FIMR EQU 0x100000C4 ; FIQ�ж����μĴ���
+
+EMI_CSACONF EQU 0x11000000 ; CSA�������üĴ���
+EMI_CSECONF EQU 0x11000010 ; CSE�������üĴ���
+EMI_CSFCONF EQU 0x11000014 ; CSF�������üĴ���
+EMI_SDCONF1 EQU 0x11000018 ; SDRAMʱ�����üĴ���1
+EMI_SDCONF2 EQU 0x1100001C ; SDRAMʱ�����üĴ���2, SDRAM��ʼ���õ���������Ϣ
+EMI_REMAPCONF EQU 0x11000020 ; Ƭѡ�ռ估��ַӳ��REMAP���üĴ���
+
+Mode_USR EQU 0x10
+Mode_FIQ EQU 0x11
+Mode_IRQ EQU 0x12
+Mode_SVC EQU 0x13
+Mode_ABT EQU 0x17
+Mode_UND EQU 0x1B
+Mode_SYS EQU 0x1F
+
+I_Bit EQU 0x80 ; when I bit is set, IRQ is disabled
+F_Bit EQU 0x40 ; when F bit is set, FIQ is disabled
+NOINT EQU 0xc0
+MASK_MODE EQU 0x0000003F
+MODE_SVC32 EQU 0x00000013
+
+; Internal Memory Base Addresses
+FLASH_BASE EQU 0x20000000
+RAM_BASE EQU 0x04000000
+
+; Stack
+UND_Stack_Size EQU 0x00000000
+SVC_Stack_Size EQU 0x00000400
+ABT_Stack_Size EQU 0x00000000
+FIQ_Stack_Size EQU 0x00000000
+IRQ_Stack_Size EQU 0x00000100
+USR_Stack_Size EQU 0x00000000
+
+ISR_Stack_Size EQU (UND_Stack_Size + SVC_Stack_Size + ABT_Stack_Size + \
+ FIQ_Stack_Size + IRQ_Stack_Size)
+
+ AREA STACK, NOINIT, READWRITE, ALIGN=3
+
+Stack_Mem SPACE USR_Stack_Size
+__initial_sp SPACE ISR_Stack_Size
+Stack_Top
+
+; Heap
+Heap_Size EQU 0x00000000
+
+ AREA HEAP, NOINIT, READWRITE, ALIGN=3
+__heap_base
+Heap_Mem SPACE Heap_Size
+__heap_limit
+
+
+ PRESERVE8
+
+; Area Definition and Entry Point
+; Startup Code must be linked first at Address at which it expects to run.
+
+ AREA RESET, CODE, READONLY
+ ARM
+
+; Exception Vectors
+; Mapped to Address 0.
+; Absolute addressing mode must be used.
+; Dummy Handlers are implemented as infinite loops which can be modified.
+
+Vectors LDR PC,Reset_Addr
+ LDR PC,Undef_Addr
+ LDR PC,SWI_Addr
+ LDR PC,PAbt_Addr
+ LDR PC,DAbt_Addr
+ NOP ; Reserved Vector
+ LDR PC,IRQ_Addr
+ LDR PC,FIQ_Addr
+
+Reset_Addr DCD Reset_Handler
+Undef_Addr DCD Undef_Handler
+SWI_Addr DCD SWI_Handler
+PAbt_Addr DCD PAbt_Handler
+DAbt_Addr DCD DAbt_Handler
+ DCD 0 ; Reserved Address
+IRQ_Addr DCD IRQ_Handler
+FIQ_Addr DCD FIQ_Handler
+
+Undef_Handler B Undef_Handler
+SWI_Handler B SWI_Handler
+PAbt_Handler B PAbt_Handler
+DAbt_Handler B DAbt_Handler
+FIQ_Handler B FIQ_Handler
+
+
+; Reset Handler
+
+ EXPORT Reset_Handler
+Reset_Handler
+
+;****************************************************************
+;* �رտ��Ź�
+;****************************************************************
+ LDR R0,=RTC_CTR
+ LDR R1,=0x0
+ STR R1,[R0]
+
+;****************************************************************
+;* ���ж�
+;****************************************************************
+ MRS R0, CPSR
+ BIC R0, R0, #MASK_MODE
+ ORR R0, R0, #MODE_SVC32
+ ORR R0, R0, #I_Bit
+ ORR R0, R0, #F_Bit
+ MSR CPSR_c, r0
+
+ LDR R0,=INTC_IER
+ LDR R1,=0x0
+ STR R1,[R0]
+ LDR R0,=INTC_IMR
+ LDR R1,=0xFFFFFFFF
+ STR R1,[R0]
+
+ LDR R0,=INTC_FIER
+ LDR R1,=0x0
+ STR R1,[R0]
+ LDR R0,=INTC_FIMR
+ LDR R1,=0x0F
+ STR R1,[R0]
+
+;****************************************************************
+;* ��ʼ��PMUģ��, ����ϵͳʱ��
+;****************************************************************
+ LDR R4, =PMU_PCSR ; ������ģ��ʱ��
+ LDR R5, =0x0001ffff
+ STR R5, [ R4 ]
+
+ LDR R4, =PMU_PLTR ; ����PLL�ȶ�����ʱ��Ϊ����ֵ50us*100M.
+ LDR R5, =0x00fa00fa
+ STR R5, [ R4 ]
+
+ LDR R4, =PMU_PMDR ; ��SLOWģʽ����NORMALģʽ
+ LDR R5, =0x00000001
+ STR R5, [ R4 ]
+
+ LDR R4, =PMU_PMCR ; ����ϵͳʱ��Ϊ72MHz 2*Fin*9=2*4*9=72MHz
+ LDR R5, =0x00004009 ; MFCN 0->1 trigger PLL to reconfigure event when mode isn''t SLOW
+ STR R5, [ R4 ]
+ LDR R4, =PMU_PMCR ;
+ LDR R5, =0x0000c009
+ STR R5, [ R4 ]
+
+;****************************************************************
+;* ��ʼ��EMI
+;****************************************************************
+; LDR R4, =EMI_CSACONF ; CSAƬѡʱ���������
+; LDR R5, =0x08a6a6a1
+; STR R5, [ R4 ]
+
+; LDR R4, =EMI_CSECONF ; CSEƬѡʱ���������,�������
+; LDR R5, =0x8cfffff1
+; STR R5, [ R4 ]
+
+; LDR R4, =EMI_SDCONF1 ; SDRAM��������1
+; LDR R5, =0x1E104177
+; STR R5, [ R4 ]
+
+; LDR R4, =EMI_SDCONF2 ; SDRAM��������2
+; LDR R5, =0x80001860
+; STR R5, [ R4 ]
+
+
+; Copy Exception Vectors to Internal RAM
+
+ IF :DEF:RAM_INTVEC
+ ADR R8, Vectors ; Source
+ LDR R9, =RAM_BASE ; Destination
+ LDMIA R8!, {R0-R7} ; Load Vectors
+ STMIA R9!, {R0-R7} ; Store Vectors
+ LDMIA R8!, {R0-R7} ; Load Handler Addresses
+ STMIA R9!, {R0-R7} ; Store Handler Addresses
+ ENDIF
+
+
+; Remap on-chip RAM to address 0
+
+ IF :DEF:REMAP
+ LDR R0, =EMI_REMAPCONF
+ MOV R1, #0x80000000
+ STR R1, [R0, #0] ; Remap
+ ENDIF
+
+
+; Setup Stack for each mode
+
+ LDR R0, =Stack_Top
+
+; Enter Undefined Instruction Mode and set its Stack Pointer
+ MSR CPSR_c, #Mode_UND:OR:I_Bit:OR:F_Bit
+ MOV SP, R0
+ SUB R0, R0, #UND_Stack_Size
+
+; Enter Abort Mode and set its Stack Pointer
+ MSR CPSR_c, #Mode_ABT:OR:I_Bit:OR:F_Bit
+ MOV SP, R0
+ SUB R0, R0, #ABT_Stack_Size
+
+; Enter FIQ Mode and set its Stack Pointer
+ MSR CPSR_c, #Mode_FIQ:OR:I_Bit:OR:F_Bit
+ MOV SP, R0
+ SUB R0, R0, #FIQ_Stack_Size
+
+; Enter IRQ Mode and set its Stack Pointer
+ MSR CPSR_c, #Mode_IRQ:OR:I_Bit:OR:F_Bit
+ MOV SP, R0
+ SUB R0, R0, #IRQ_Stack_Size
+
+; Enter Supervisor Mode and set its Stack Pointer
+ MSR CPSR_c, #Mode_SVC:OR:I_Bit:OR:F_Bit
+ MOV SP, R0
+ SUB R0, R0, #SVC_Stack_Size
+
+; Enter User Mode and set its Stack Pointer
+ ; MSR CPSR_c, #Mode_USR
+ IF :DEF:__MICROLIB
+
+ EXPORT __initial_sp
+
+ ELSE
+
+ ; No usr mode stack here.
+ ;MOV SP, R0
+ ;SUB SL, SP, #USR_Stack_Size
+
+ ENDIF
+
+
+; Enter the C code
+
+ IMPORT __main
+ LDR R0, =__main
+ BX R0
+
+ IMPORT rt_interrupt_enter
+ IMPORT rt_interrupt_leave
+ IMPORT rt_thread_switch_interrput_flag
+ IMPORT rt_interrupt_from_thread
+ IMPORT rt_interrupt_to_thread
+ IMPORT rt_hw_trap_irq
+ IMPORT rt_hw_trap_abort
+ IMPORT rt_interrupt_nest
+
+Abort_Handler PROC
+ EXPORT Abort_Handler
+ STMFD SP!, {R0-R12,LR}
+ LDR R0, =rt_interrupt_nest
+ LDR R1, [R0]
+ CMP R1, #0
+DeadLoop BHI DeadLoop ; Abort happened in irq mode, halt system.
+ BL rt_interrupt_enter
+ BL rt_hw_trap_abort
+ BL rt_interrupt_leave
+ B SWITCH
+ ENDP
+
+IRQ_Handler PROC
+ EXPORT IRQ_Handler
+ STMFD SP!, {R0-R12,LR}
+ BL rt_interrupt_enter
+ BL rt_hw_trap_irq
+ BL rt_interrupt_leave
+
+ ; if rt_thread_switch_interrput_flag set, jump to
+ ; rt_hw_context_switch_interrupt_do and don't return
+SWITCH
+ LDR R0, =rt_thread_switch_interrput_flag
+ LDR R1, [R0]
+ CMP R1, #1
+ BEQ rt_hw_context_switch_interrupt_do
+
+ LDMFD SP!, {R0-R12,LR}
+ SUBS PC, LR, #4
+ ENDP
+
+; /*
+; * void rt_hw_context_switch_interrupt_do(rt_base_t flag)
+; */
+rt_hw_context_switch_interrupt_do PROC
+ EXPORT rt_hw_context_switch_interrupt_do
+ MOV r1, #0 ; clear flag
+ STR r1, [r0]
+
+ LDMFD sp!, {r0-r12,lr}; reload saved registers
+ STMFD sp!, {r0-r3} ; save r0-r3
+ MOV r1, sp
+ ADD sp, sp, #16 ; restore sp
+ SUB r2, lr, #4 ; save old task's pc to r2
+
+ MRS r3, spsr ; get cpsr of interrupt thread
+
+ ; switch to SVC mode and no interrupt
+ MSR cpsr_c, #I_Bit:OR:F_Bit:OR:Mode_SVC
+
+ STMFD sp!, {r2} ; push old task's pc
+ STMFD sp!, {r4-r12,lr}; push old task's lr,r12-r4
+ MOV r4, r1 ; Special optimised code below
+ MOV r5, r3
+ LDMFD r4!, {r0-r3}
+ STMFD sp!, {r0-r3} ; push old task's r3-r0
+ STMFD sp!, {r5} ; push old task's cpsr
+ MRS r4, spsr
+ STMFD sp!, {r4} ; push old task's spsr
+
+ LDR r4, =rt_interrupt_from_thread
+ LDR r5, [r4]
+ STR sp, [r5] ; store sp in preempted tasks's TCB
+
+ LDR r6, =rt_interrupt_to_thread
+ LDR r6, [r6]
+ LDR sp, [r6] ; get new task's stack pointer
+
+ LDMFD sp!, {r4} ; pop new task's spsr
+ MSR spsr_cxsf, r4
+ LDMFD sp!, {r4} ; pop new task's psr
+ MSR cpsr_cxsf, r4
+
+ LDMFD sp!, {r0-r12,lr,pc} ; pop new task's r0-r12,lr & pc
+ ENDP
+
+ IF :DEF:__MICROLIB
+
+ EXPORT __heap_base
+ EXPORT __heap_limit
+
+ ELSE
+; User Initial Stack & Heap
+ AREA |.text|, CODE, READONLY
+
+ IMPORT __use_two_region_memory
+ EXPORT __user_initial_stackheap
+__user_initial_stackheap
+
+ LDR R0, = Heap_Mem
+ LDR R1, = (Stack_Mem + IRQ_Stack_Size)
+ LDR R2, = (Heap_Mem + Heap_Size)
+ LDR R3, = Stack_Mem
+ BX LR
+ ENDIF
+
+ END
diff --git a/libcpu/arm/sep4020/trap.c b/libcpu/arm/sep4020/trap.c new file mode 100644 index 0000000000..cad14e88fc --- /dev/null +++ b/libcpu/arm/sep4020/trap.c @@ -0,0 +1,66 @@ +/* + * File : trap.c + * This file is part of RT-Thread RTOS + * COPYRIGHT (C) 2006, RT-Thread Development Team + * + * The license and distribution terms for this file may be + * found in the file LICENSE in this distribution or at + * http://openlab.rt-thread.com/license/LICENSE + * + * Change Logs: + * Date Author Notes + * 2006-08-25 Bernard first version
+ * 2010-03-18 zchong for sep4020 + */ + +#include <rtthread.h> +#include <rthw.h> + +#include "sep4020.h" + +/** + * @addtogroup SEP4020 + */ +/*@{*/ + +extern rt_isr_handler_t isr_table[];
+
+void rt_hw_trap_irq()
+{
+ rt_uint32_t intstat,intnum;
+ rt_uint8_t i = 0;
+ rt_isr_handler_t isr_func;
+
+ /* get interrupt source */
+ intstat = INTC_IFSR;
+
+ intnum = intstat;
+ if (intstat == INTGLOBAL) return;
+
+ while(intnum != 0x00000001)
+ {
+ intnum = intnum>>1;
+ i++;
+ }
+ /* get interrupt service routine */
+ isr_func = isr_table[i];
+
+ /* turn to interrupt service routine */
+ isr_func(intstat);
+
+} + +void rt_hw_trap_fiq() +{ + rt_kprintf("fast interrupt request\n"); +}
+ +extern struct rt_thread* rt_current_thread; +void rt_hw_trap_abort() +{
+ rt_kprintf("Abort occured!!! Thread [%s] suspended.\n",rt_current_thread->name);
+ rt_thread_suspend(rt_current_thread);
+ rt_schedule(); + +} +/*@}*/ |