diff options
112 files changed, 24057 insertions, 18283 deletions
diff --git a/bsp/swm320-lq100/.config b/bsp/swm320-lq100/.config index 12a39ca43b..f5b76827e9 100644 --- a/bsp/swm320-lq100/.config +++ b/bsp/swm320-lq100/.config @@ -7,19 +7,27 @@ # RT-Thread Kernel # CONFIG_RT_NAME_MAX=8 +# CONFIG_RT_USING_ARCH_DATA_TYPE is not set # CONFIG_RT_USING_SMP is not set CONFIG_RT_ALIGN_SIZE=4 # CONFIG_RT_THREAD_PRIORITY_8 is not set CONFIG_RT_THREAD_PRIORITY_32=y # CONFIG_RT_THREAD_PRIORITY_256 is not set CONFIG_RT_THREAD_PRIORITY_MAX=32 -CONFIG_RT_TICK_PER_SECOND=100 +CONFIG_RT_TICK_PER_SECOND=1000 CONFIG_RT_USING_OVERFLOW_CHECK=y CONFIG_RT_USING_HOOK=y CONFIG_RT_USING_IDLE_HOOK=y CONFIG_RT_IDLE_HOOK_LIST_SIZE=4 CONFIG_IDLE_THREAD_STACK_SIZE=256 # CONFIG_RT_USING_TIMER_SOFT is not set + +# +# kservice optimization +# +# CONFIG_RT_KSERVICE_USING_STDLIB is not set +# CONFIG_RT_KSERVICE_USING_TINY_SIZE is not set +# CONFIG_RT_USING_ASM_MEMCPY is not set CONFIG_RT_DEBUG=y CONFIG_RT_DEBUG_COLOR=y # CONFIG_RT_DEBUG_INIT_CONFIG is not set @@ -48,10 +56,12 @@ CONFIG_RT_USING_MESSAGEQUEUE=y # CONFIG_RT_USING_MEMPOOL=y CONFIG_RT_USING_MEMHEAP=y +CONFIG_RT_USING_MEMHEAP_AUTO_BINDING=y # CONFIG_RT_USING_NOHEAP is not set -CONFIG_RT_USING_SMALL_MEM=y +# CONFIG_RT_USING_SMALL_MEM is not set # CONFIG_RT_USING_SLAB is not set -# CONFIG_RT_USING_MEMHEAP_AS_HEAP is not set +CONFIG_RT_USING_MEMHEAP_AS_HEAP=y +# CONFIG_RT_USING_USERHEAP is not set # CONFIG_RT_USING_MEMTRACE is not set CONFIG_RT_USING_HEAP=y @@ -64,7 +74,12 @@ CONFIG_RT_USING_DEVICE=y CONFIG_RT_USING_CONSOLE=y CONFIG_RT_CONSOLEBUF_SIZE=128 CONFIG_RT_CONSOLE_DEVICE_NAME="uart0" -CONFIG_RT_VER_NUM=0x40000 +# CONFIG_RT_PRINTF_LONGLONG is not set +CONFIG_RT_VER_NUM=0x40004 +CONFIG_ARCH_ARM=y +CONFIG_RT_USING_CPU_FFS=y +CONFIG_ARCH_ARM_CORTEX_M=y +CONFIG_ARCH_ARM_CORTEX_M4=y # CONFIG_ARCH_CPU_STACK_GROWS_UPWARD is not set # @@ -84,53 +99,67 @@ CONFIG_RT_MAIN_THREAD_PRIORITY=10 # Command shell # CONFIG_RT_USING_FINSH=y +CONFIG_RT_USING_MSH=y +CONFIG_FINSH_USING_MSH=y CONFIG_FINSH_THREAD_NAME="tshell" +CONFIG_FINSH_THREAD_PRIORITY=20 +CONFIG_FINSH_THREAD_STACK_SIZE=4096 CONFIG_FINSH_USING_HISTORY=y CONFIG_FINSH_HISTORY_LINES=5 CONFIG_FINSH_USING_SYMTAB=y +CONFIG_FINSH_CMD_SIZE=80 +CONFIG_MSH_USING_BUILT_IN_COMMANDS=y CONFIG_FINSH_USING_DESCRIPTION=y # CONFIG_FINSH_ECHO_DISABLE_DEFAULT is not set -CONFIG_FINSH_THREAD_PRIORITY=20 -CONFIG_FINSH_THREAD_STACK_SIZE=4096 -CONFIG_FINSH_CMD_SIZE=80 # CONFIG_FINSH_USING_AUTH is not set -CONFIG_FINSH_USING_MSH=y -CONFIG_FINSH_USING_MSH_DEFAULT=y -# CONFIG_FINSH_USING_MSH_ONLY is not set CONFIG_FINSH_ARG_MAX=10 # # Device virtual file system # # CONFIG_RT_USING_DFS is not set +# CONFIG_RT_DFS_ELM_USE_LFN_0 is not set +# CONFIG_RT_DFS_ELM_USE_LFN_1 is not set +# CONFIG_RT_DFS_ELM_USE_LFN_2 is not set +# CONFIG_RT_DFS_ELM_USE_LFN_3 is not set +# CONFIG_RT_DFS_ELM_LFN_UNICODE_0 is not set +# CONFIG_RT_DFS_ELM_LFN_UNICODE_1 is not set +# CONFIG_RT_DFS_ELM_LFN_UNICODE_2 is not set +# CONFIG_RT_DFS_ELM_LFN_UNICODE_3 is not set # # Device Drivers # CONFIG_RT_USING_DEVICE_IPC=y CONFIG_RT_PIPE_BUFSZ=512 +# CONFIG_RT_USING_SYSTEM_WORKQUEUE is not set CONFIG_RT_USING_SERIAL=y +CONFIG_RT_USING_SERIAL_V1=y +# CONFIG_RT_USING_SERIAL_V2 is not set # CONFIG_RT_SERIAL_USING_DMA is not set +CONFIG_RT_SERIAL_RB_BUFSZ=64 # CONFIG_RT_USING_CAN is not set -CONFIG_RT_USING_HWTIMER=y +# CONFIG_RT_USING_HWTIMER is not set # CONFIG_RT_USING_CPUTIME is not set # CONFIG_RT_USING_I2C is not set +# CONFIG_RT_USING_PHY is not set CONFIG_RT_USING_PIN=y # CONFIG_RT_USING_ADC is not set -CONFIG_RT_USING_PWM=y +# CONFIG_RT_USING_DAC is not set +# CONFIG_RT_USING_PWM is not set # CONFIG_RT_USING_MTD_NOR is not set # CONFIG_RT_USING_MTD_NAND is not set -# CONFIG_RT_USING_MTD is not set # CONFIG_RT_USING_PM is not set # CONFIG_RT_USING_RTC is not set # CONFIG_RT_USING_SDIO is not set # CONFIG_RT_USING_SPI is not set # CONFIG_RT_USING_WDT is not set # CONFIG_RT_USING_AUDIO is not set - -# -# Using WiFi -# +# CONFIG_RT_USING_SENSOR is not set +# CONFIG_RT_USING_TOUCH is not set +# CONFIG_RT_USING_HWCRYPTO is not set +# CONFIG_RT_USING_PULSE_ENCODER is not set +# CONFIG_RT_USING_INPUT_CAPTURE is not set # CONFIG_RT_USING_WIFI is not set # @@ -142,8 +171,11 @@ CONFIG_RT_USING_PWM=y # # POSIX layer and C standard library # -# CONFIG_RT_USING_LIBC is not set +CONFIG_RT_USING_LIBC=y # CONFIG_RT_USING_PTHREADS is not set +CONFIG_RT_LIBC_USING_TIME=y +# CONFIG_RT_USING_MODULE is not set +CONFIG_RT_LIBC_DEFAULT_TIMEZONE=8 # # Network @@ -155,14 +187,14 @@ CONFIG_RT_USING_PWM=y # CONFIG_RT_USING_SAL is not set # -# light weight TCP/IP stack +# Network interface device # -# CONFIG_RT_USING_LWIP is not set +# CONFIG_RT_USING_NETDEV is not set # -# Modbus master and slave stack +# light weight TCP/IP stack # -# CONFIG_RT_USING_MODBUS is not set +# CONFIG_RT_USING_LWIP is not set # # AT commands @@ -177,10 +209,16 @@ CONFIG_RT_USING_PWM=y # # Utilities # -# CONFIG_RT_USING_LOGTRACE is not set # CONFIG_RT_USING_RYM is not set # CONFIG_RT_USING_ULOG is not set # CONFIG_RT_USING_UTEST is not set +# CONFIG_RT_USING_RT_LINK is not set +# CONFIG_RT_USING_LWP is not set + +# +# RT-Thread Utestcases +# +# CONFIG_RT_USING_UTESTCASES is not set # # RT-Thread online packages @@ -189,13 +227,20 @@ CONFIG_RT_USING_PWM=y # # IoT - internet of things # +# CONFIG_PKG_USING_LORAWAN_DRIVER is not set # CONFIG_PKG_USING_PAHOMQTT is not set +# CONFIG_PKG_USING_UMQTT is not set # CONFIG_PKG_USING_WEBCLIENT is not set # CONFIG_PKG_USING_WEBNET is not set # CONFIG_PKG_USING_MONGOOSE is not set +# CONFIG_PKG_USING_MYMQTT is not set +# CONFIG_PKG_USING_KAWAII_MQTT is not set +# CONFIG_PKG_USING_BC28_MQTT is not set # CONFIG_PKG_USING_WEBTERMINAL is not set # CONFIG_PKG_USING_CJSON is not set # CONFIG_PKG_USING_JSMN is not set +# CONFIG_PKG_USING_LIBMODBUS is not set +# CONFIG_PKG_USING_FREEMODBUS is not set # CONFIG_PKG_USING_LJSON is not set # CONFIG_PKG_USING_EZXML is not set # CONFIG_PKG_USING_NANOPB is not set @@ -213,11 +258,16 @@ CONFIG_RT_USING_PWM=y # Wiced WiFi # # CONFIG_PKG_USING_WLAN_WICED is not set +# CONFIG_PKG_USING_RW007 is not set # CONFIG_PKG_USING_COAP is not set # CONFIG_PKG_USING_NOPOLL is not set # CONFIG_PKG_USING_NETUTILS is not set +# CONFIG_PKG_USING_CMUX is not set +# CONFIG_PKG_USING_PPP_DEVICE is not set # CONFIG_PKG_USING_AT_DEVICE is not set +# CONFIG_PKG_USING_ATSRV_SOCKET is not set # CONFIG_PKG_USING_WIZNET is not set +# CONFIG_PKG_USING_ZB_COORDINATOR is not set # # IoT Cloud @@ -226,7 +276,39 @@ CONFIG_RT_USING_PWM=y # CONFIG_PKG_USING_GAGENT_CLOUD is not set # CONFIG_PKG_USING_ALI_IOTKIT is not set # CONFIG_PKG_USING_AZURE is not set -# CONFIG_PKG_USING_TENCENT_IOTKIT is not set +# CONFIG_PKG_USING_TENCENT_IOT_EXPLORER is not set +# CONFIG_PKG_USING_JIOT-C-SDK is not set +# CONFIG_PKG_USING_UCLOUD_IOT_SDK is not set +# CONFIG_PKG_USING_JOYLINK is not set +# CONFIG_PKG_USING_NIMBLE is not set +# CONFIG_PKG_USING_OTA_DOWNLOADER is not set +# CONFIG_PKG_USING_IPMSG is not set +# CONFIG_PKG_USING_LSSDP is not set +# CONFIG_PKG_USING_AIRKISS_OPEN is not set +# CONFIG_PKG_USING_LIBRWS is not set +# CONFIG_PKG_USING_TCPSERVER is not set +# CONFIG_PKG_USING_PROTOBUF_C is not set +# CONFIG_PKG_USING_DLT645 is not set +# CONFIG_PKG_USING_QXWZ is not set +# CONFIG_PKG_USING_SMTP_CLIENT is not set +# CONFIG_PKG_USING_ABUP_FOTA is not set +# CONFIG_PKG_USING_LIBCURL2RTT is not set +# CONFIG_PKG_USING_CAPNP is not set +# CONFIG_PKG_USING_RT_CJSON_TOOLS is not set +# CONFIG_PKG_USING_AGILE_TELNET is not set +# CONFIG_PKG_USING_NMEALIB is not set +# CONFIG_PKG_USING_AGILE_JSMN is not set +# CONFIG_PKG_USING_PDULIB is not set +# CONFIG_PKG_USING_BTSTACK is not set +# CONFIG_PKG_USING_LORAWAN_ED_STACK is not set +# CONFIG_PKG_USING_WAYZ_IOTKIT is not set +# CONFIG_PKG_USING_MAVLINK is not set +# CONFIG_PKG_USING_RAPIDJSON is not set +# CONFIG_PKG_USING_BSAL is not set +# CONFIG_PKG_USING_AGILE_MODBUS is not set +# CONFIG_PKG_USING_AGILE_FTP is not set +# CONFIG_PKG_USING_EMBEDDEDPROTO is not set +# CONFIG_PKG_USING_RT_LINK_HW is not set # # security packages @@ -234,6 +316,8 @@ CONFIG_RT_USING_PWM=y # CONFIG_PKG_USING_MBEDTLS is not set # CONFIG_PKG_USING_libsodium is not set # CONFIG_PKG_USING_TINYCRYPT is not set +# CONFIG_PKG_USING_TFM is not set +# CONFIG_PKG_USING_YD_CRYPTO is not set # # language packages @@ -241,12 +325,23 @@ CONFIG_RT_USING_PWM=y # CONFIG_PKG_USING_LUA is not set # CONFIG_PKG_USING_JERRYSCRIPT is not set # CONFIG_PKG_USING_MICROPYTHON is not set +# CONFIG_PKG_USING_PIKASCRIPT is not set # # multimedia packages # # CONFIG_PKG_USING_OPENMV is not set # CONFIG_PKG_USING_MUPDF is not set +# CONFIG_PKG_USING_STEMWIN is not set +# CONFIG_PKG_USING_WAVPLAYER is not set +# CONFIG_PKG_USING_TJPGD is not set +# CONFIG_PKG_USING_PDFGEN is not set +# CONFIG_PKG_USING_HELIX is not set +# CONFIG_PKG_USING_AZUREGUIX is not set +# CONFIG_PKG_USING_TOUCHGFX2RTT is not set +# CONFIG_PKG_USING_NUEMWIN is not set +# CONFIG_PKG_USING_MP3PLAYER is not set +# CONFIG_PKG_USING_TINYJPEG is not set # # tools packages @@ -255,120 +350,262 @@ CONFIG_RT_USING_PWM=y # CONFIG_PKG_USING_EASYFLASH is not set # CONFIG_PKG_USING_EASYLOGGER is not set # CONFIG_PKG_USING_SYSTEMVIEW is not set +# CONFIG_PKG_USING_SEGGER_RTT is not set # CONFIG_PKG_USING_RDB is not set # CONFIG_PKG_USING_QRCODE is not set # CONFIG_PKG_USING_ULOG_EASYFLASH is not set +# CONFIG_PKG_USING_ULOG_FILE is not set +# CONFIG_PKG_USING_LOGMGR is not set +# CONFIG_PKG_USING_ADBD is not set +# CONFIG_PKG_USING_COREMARK is not set +# CONFIG_PKG_USING_DHRYSTONE is not set +# CONFIG_PKG_USING_MEMORYPERF is not set +# CONFIG_PKG_USING_NR_MICRO_SHELL is not set +# CONFIG_PKG_USING_CHINESE_FONT_LIBRARY is not set +# CONFIG_PKG_USING_LUNAR_CALENDAR is not set +# CONFIG_PKG_USING_BS8116A is not set +# CONFIG_PKG_USING_GPS_RMC is not set +# CONFIG_PKG_USING_URLENCODE is not set +# CONFIG_PKG_USING_UMCN is not set +# CONFIG_PKG_USING_LWRB2RTT is not set +# CONFIG_PKG_USING_CPU_USAGE is not set +# CONFIG_PKG_USING_GBK2UTF8 is not set +# CONFIG_PKG_USING_VCONSOLE is not set +# CONFIG_PKG_USING_KDB is not set +# CONFIG_PKG_USING_WAMR is not set +# CONFIG_PKG_USING_MICRO_XRCE_DDS_CLIENT is not set +# CONFIG_PKG_USING_LWLOG is not set +# CONFIG_PKG_USING_ANV_TRACE is not set +# CONFIG_PKG_USING_ANV_MEMLEAK is not set +# CONFIG_PKG_USING_ANV_TESTSUIT is not set +# CONFIG_PKG_USING_ANV_BENCH is not set +# CONFIG_PKG_USING_DEVMEM is not set +# CONFIG_PKG_USING_REGEX is not set +# CONFIG_PKG_USING_MEM_SANDBOX is not set +# CONFIG_PKG_USING_SOLAR_TERMS is not set +# CONFIG_PKG_USING_GAN_ZHI is not set # # system packages # + +# +# acceleration: Assembly language or algorithmic acceleration packages +# +# CONFIG_PKG_USING_RT_MEMCPY_CM is not set +# CONFIG_PKG_USING_QFPLIB_M0_FULL is not set +# CONFIG_PKG_USING_QFPLIB_M0_TINY is not set +# CONFIG_PKG_USING_QFPLIB_M3 is not set + +# +# Micrium: Micrium software products porting for RT-Thread +# +# CONFIG_PKG_USING_UCOSIII_WRAPPER is not set +# CONFIG_PKG_USING_UCOSII_WRAPPER is not set +# CONFIG_PKG_USING_UC_CRC is not set +# CONFIG_PKG_USING_UC_CLK is not set +# CONFIG_PKG_USING_UC_COMMON is not set +# CONFIG_PKG_USING_UC_MODBUS is not set # CONFIG_PKG_USING_GUIENGINE is not set +# CONFIG_PKG_USING_PERSIMMON is not set # CONFIG_PKG_USING_CAIRO is not set # CONFIG_PKG_USING_PIXMAN is not set -# CONFIG_PKG_USING_LWEXT4 is not set # CONFIG_PKG_USING_PARTITION is not set # CONFIG_PKG_USING_FAL is not set +# CONFIG_PKG_USING_FLASHDB is not set # CONFIG_PKG_USING_SQLITE is not set # CONFIG_PKG_USING_RTI is not set # CONFIG_PKG_USING_LITTLEVGL2RTT is not set # CONFIG_PKG_USING_CMSIS is not set # CONFIG_PKG_USING_DFS_YAFFS is not set # CONFIG_PKG_USING_LITTLEFS is not set +# CONFIG_PKG_USING_DFS_JFFS2 is not set +# CONFIG_PKG_USING_DFS_UFFS is not set +# CONFIG_PKG_USING_LWEXT4 is not set +# CONFIG_PKG_USING_THREAD_POOL is not set +# CONFIG_PKG_USING_ROBOTS is not set +# CONFIG_PKG_USING_EV is not set +# CONFIG_PKG_USING_SYSWATCH is not set +# CONFIG_PKG_USING_SYS_LOAD_MONITOR is not set +# CONFIG_PKG_USING_PLCCORE is not set +# CONFIG_PKG_USING_RAMDISK is not set +# CONFIG_PKG_USING_MININI is not set +# CONFIG_PKG_USING_QBOOT is not set +# CONFIG_PKG_USING_PPOOL is not set +# CONFIG_PKG_USING_OPENAMP is not set +# CONFIG_PKG_USING_RT_KPRINTF_THREADSAFE is not set +# CONFIG_PKG_USING_LPM is not set +# CONFIG_PKG_USING_TLSF is not set +# CONFIG_PKG_USING_EVENT_RECORDER is not set +# CONFIG_PKG_USING_ARM_2D is not set +# CONFIG_PKG_USING_WCWIDTH is not set # # peripheral libraries and drivers # +# CONFIG_PKG_USING_SENSORS_DRIVERS is not set # CONFIG_PKG_USING_REALTEK_AMEBA is not set # CONFIG_PKG_USING_SHT2X is not set -# CONFIG_PKG_USING_AHT10 is not set -# CONFIG_PKG_USING_AP3216C is not set +# CONFIG_PKG_USING_SHT3X is not set +# CONFIG_PKG_USING_AS7341 is not set # CONFIG_PKG_USING_STM32_SDIO is not set # CONFIG_PKG_USING_ICM20608 is not set # CONFIG_PKG_USING_U8G2 is not set # CONFIG_PKG_USING_BUTTON is not set -# CONFIG_PKG_USING_MPU6XXX is not set # CONFIG_PKG_USING_PCF8574 is not set +# CONFIG_PKG_USING_SX12XX is not set +# CONFIG_PKG_USING_SIGNAL_LED is not set +# CONFIG_PKG_USING_LEDBLINK is not set +# CONFIG_PKG_USING_LITTLED is not set +# CONFIG_PKG_USING_LKDGUI is not set +# CONFIG_PKG_USING_NRF5X_SDK is not set +# CONFIG_PKG_USING_NRFX is not set +# CONFIG_PKG_USING_WM_LIBRARIES is not set # CONFIG_PKG_USING_KENDRYTE_SDK is not set +# CONFIG_PKG_USING_INFRARED is not set +# CONFIG_PKG_USING_AGILE_BUTTON is not set +# CONFIG_PKG_USING_AGILE_LED is not set +# CONFIG_PKG_USING_AT24CXX is not set +# CONFIG_PKG_USING_MOTIONDRIVER2RTT is not set +# CONFIG_PKG_USING_AD7746 is not set +# CONFIG_PKG_USING_PCA9685 is not set +# CONFIG_PKG_USING_I2C_TOOLS is not set +# CONFIG_PKG_USING_NRF24L01 is not set +# CONFIG_PKG_USING_TOUCH_DRIVERS is not set +# CONFIG_PKG_USING_MAX17048 is not set +# CONFIG_PKG_USING_RPLIDAR is not set +# CONFIG_PKG_USING_AS608 is not set +# CONFIG_PKG_USING_RC522 is not set +# CONFIG_PKG_USING_WS2812B is not set +# CONFIG_PKG_USING_EMBARC_BSP is not set +# CONFIG_PKG_USING_EXTERN_RTC_DRIVERS is not set +# CONFIG_PKG_USING_MULTI_RTIMER is not set +# CONFIG_PKG_USING_MAX7219 is not set +# CONFIG_PKG_USING_BEEP is not set +# CONFIG_PKG_USING_EASYBLINK is not set +# CONFIG_PKG_USING_PMS_SERIES is not set +# CONFIG_PKG_USING_CAN_YMODEM is not set +# CONFIG_PKG_USING_LORA_RADIO_DRIVER is not set +# CONFIG_PKG_USING_QLED is not set +# CONFIG_PKG_USING_PAJ7620 is not set +# CONFIG_PKG_USING_AGILE_CONSOLE is not set +# CONFIG_PKG_USING_LD3320 is not set +# CONFIG_PKG_USING_WK2124 is not set +# CONFIG_PKG_USING_LY68L6400 is not set +# CONFIG_PKG_USING_DM9051 is not set +# CONFIG_PKG_USING_SSD1306 is not set +# CONFIG_PKG_USING_QKEY is not set +# CONFIG_PKG_USING_RS485 is not set +# CONFIG_PKG_USING_NES is not set +# CONFIG_PKG_USING_VIRTUAL_SENSOR is not set +# CONFIG_PKG_USING_VDEVICE is not set +# CONFIG_PKG_USING_SGM706 is not set +# CONFIG_PKG_USING_STM32WB55_SDK is not set +# CONFIG_PKG_USING_RDA58XX is not set +# CONFIG_PKG_USING_LIBNFC is not set +# CONFIG_PKG_USING_MFOC is not set +# CONFIG_PKG_USING_TMC51XX is not set +# CONFIG_PKG_USING_TCA9534 is not set +# CONFIG_PKG_USING_KOBUKI is not set +# CONFIG_PKG_USING_ROSSERIAL is not set +# CONFIG_PKG_USING_MICRO_ROS is not set +# CONFIG_PKG_USING_MCP23008 is not set +# CONFIG_PKG_USING_BLUETRUM_SDK is not set + +# +# AI packages +# +# CONFIG_PKG_USING_LIBANN is not set +# CONFIG_PKG_USING_NNOM is not set +# CONFIG_PKG_USING_ONNX_BACKEND is not set +# CONFIG_PKG_USING_ONNX_PARSER is not set +# CONFIG_PKG_USING_TENSORFLOWLITEMICRO is not set +# CONFIG_PKG_USING_ELAPACK is not set +# CONFIG_PKG_USING_ULAPACK is not set +# CONFIG_PKG_USING_QUEST is not set +# CONFIG_PKG_USING_NAXOS is not set # # miscellaneous packages # + +# +# samples: kernel and components samples +# +# CONFIG_PKG_USING_KERNEL_SAMPLES is not set +# CONFIG_PKG_USING_FILESYSTEM_SAMPLES is not set +# CONFIG_PKG_USING_NETWORK_SAMPLES is not set +# CONFIG_PKG_USING_PERIPHERAL_SAMPLES is not set + +# +# entertainment: terminal games and other interesting software packages +# +# CONFIG_PKG_USING_CMATRIX is not set +# CONFIG_PKG_USING_SL is not set +# CONFIG_PKG_USING_CAL is not set +# CONFIG_PKG_USING_ACLOCK is not set +# CONFIG_PKG_USING_THREES is not set +# CONFIG_PKG_USING_2048 is not set +# CONFIG_PKG_USING_SNAKE is not set +# CONFIG_PKG_USING_TETRIS is not set +# CONFIG_PKG_USING_DONUT is not set # CONFIG_PKG_USING_LIBCSV is not set # CONFIG_PKG_USING_OPTPARSE is not set # CONFIG_PKG_USING_FASTLZ is not set # CONFIG_PKG_USING_MINILZO is not set # CONFIG_PKG_USING_QUICKLZ is not set +# CONFIG_PKG_USING_LZMA is not set # CONFIG_PKG_USING_MULTIBUTTON is not set +# CONFIG_PKG_USING_FLEXIBLE_BUTTON is not set # CONFIG_PKG_USING_CANFESTIVAL is not set # CONFIG_PKG_USING_ZLIB is not set +# CONFIG_PKG_USING_MINIZIP is not set # CONFIG_PKG_USING_DSTR is not set # CONFIG_PKG_USING_TINYFRAME is not set - -# -# samples: kernel and components samples -# -# CONFIG_PKG_USING_KERNEL_SAMPLES is not set -# CONFIG_PKG_USING_FILESYSTEM_SAMPLES is not set -# CONFIG_PKG_USING_NETWORK_SAMPLES is not set -# CONFIG_PKG_USING_PERIPHERAL_SAMPLES is not set +# CONFIG_PKG_USING_KENDRYTE_DEMO is not set +# CONFIG_PKG_USING_DIGITALCTRL is not set +# CONFIG_PKG_USING_UPACKER is not set +# CONFIG_PKG_USING_UPARAM is not set # CONFIG_PKG_USING_HELLO is not set -CONFIG_SOC_SWM320VET7=y +# CONFIG_PKG_USING_VI is not set +# CONFIG_PKG_USING_KI is not set +# CONFIG_PKG_USING_ARMv7M_DWT is not set +# CONFIG_PKG_USING_VT100 is not set +# CONFIG_PKG_USING_UKAL is not set +# CONFIG_PKG_USING_CRCLIB is not set +# CONFIG_PKG_USING_LWGPS is not set +# CONFIG_PKG_USING_STATE_MACHINE is not set +# CONFIG_PKG_USING_MCURSES is not set +# CONFIG_PKG_USING_COWSAY is not set +# CONFIG_PKG_USING_TERMBOX is not set # # Hardware Drivers Config # +CONFIG_SOC_SWM320=y # # On-chip Peripheral Drivers # -CONFIG_BSP_USING_GPIO=y -# CONFIG_BSP_USING_WDT is not set - -# -# UART Drivers -# +CONFIG_BSP_USING_UART=y CONFIG_BSP_USING_UART0=y # CONFIG_BSP_USING_UART1 is not set # CONFIG_BSP_USING_UART2 is not set # CONFIG_BSP_USING_UART3 is not set - -# -# SPI Drivers -# -# CONFIG_BSP_USING_SPI0 is not set -# CONFIG_BSP_USING_SPI1 is not set - -# -# I2C Drivers -# +CONFIG_BSP_USING_GPIO=y +# CONFIG_BSP_USING_ADC is not set +# CONFIG_BSP_USING_TIM is not set # CONFIG_BSP_USING_I2C is not set - -# -# PWM Drivers -# -# CONFIG_BSP_USING_PWM0 is not set -# CONFIG_BSP_USING_PWM1 is not set -# CONFIG_BSP_USING_PWM2 is not set -# CONFIG_BSP_USING_PWM3 is not set - -# -# RTC Drivers -# +# CONFIG_BSP_USING_PWM is not set # CONFIG_BSP_USING_RTC is not set - -# -# HWtimer Drivers -# -# CONFIG_BSP_USING_HWTIMER0 is not set -# CONFIG_BSP_USING_HWTIMER1 is not set -# CONFIG_BSP_USING_HWTIMER2 is not set -# CONFIG_BSP_USING_HWTIMER3 is not set -# CONFIG_BSP_USING_HWTIMER4 is not set -# CONFIG_BSP_USING_HWTIMER5 is not set +# CONFIG_BSP_USING_SPI is not set +# CONFIG_BSP_USING_WDT is not set +# CONFIG_BSP_USING_CRC is not set # # Onboard Peripheral Drivers # +# CONFIG_BSP_USING_SDIO is not set # CONFIG_BSP_USING_EXT_SRAM is not set # CONFIG_BSP_USING_NOR_FLASH is not set diff --git a/bsp/swm320-lq100/Kconfig b/bsp/swm320-lq100/Kconfig index 59dcef1b29..126a6a1f5c 100644 --- a/bsp/swm320-lq100/Kconfig +++ b/bsp/swm320-lq100/Kconfig @@ -17,11 +17,9 @@ config PKGS_DIR source "$RTT_DIR/Kconfig" source "$PKGS_DIR/Kconfig" +source "drivers/Kconfig" -config SOC_SWM320VET7 +config SOC_SWM320 bool - select RT_USING_COMPONENTS_INIT - select RT_USING_USER_MAIN + select ARCH_ARM_CORTEX_M4 default y - -source "drivers/Kconfig" diff --git a/bsp/swm320-lq100/Libraries/CMSIS/CoreSupport/arm_common_tables.h b/bsp/swm320-lq100/Libraries/CMSIS/CoreSupport/arm_common_tables.h index 76aadca490..368705e1c2 100644 --- a/bsp/swm320-lq100/Libraries/CMSIS/CoreSupport/arm_common_tables.h +++ b/bsp/swm320-lq100/Libraries/CMSIS/CoreSupport/arm_common_tables.h @@ -2,12 +2,12 @@ * Copyright (C) 2010-2014 ARM Limited. All rights reserved. * * $Date: 31. July 2014 -* $Revision: V1.4.4 +* $Revision: V1.4.4 * -* Project: CMSIS DSP Library -* Title: arm_common_tables.h +* Project: CMSIS DSP Library +* Title: arm_common_tables.h * -* Description: This file has extern declaration for common tables like Bitreverse, reciprocal etc which are used across different functions +* Description: This file has extern declaration for common tables like Bitreverse, reciprocal etc which are used across different functions * * Target Processor: Cortex-M4/Cortex-M3 * @@ -85,14 +85,13 @@ extern const float32_t twiddleCoef_rfft_1024[1024]; extern const float32_t twiddleCoef_rfft_2048[2048]; extern const float32_t twiddleCoef_rfft_4096[4096]; - /* floating-point bit reversal tables */ -#define ARMBITREVINDEXTABLE__16_TABLE_LENGTH ((uint16_t)20 ) -#define ARMBITREVINDEXTABLE__32_TABLE_LENGTH ((uint16_t)48 ) -#define ARMBITREVINDEXTABLE__64_TABLE_LENGTH ((uint16_t)56 ) -#define ARMBITREVINDEXTABLE_128_TABLE_LENGTH ((uint16_t)208 ) -#define ARMBITREVINDEXTABLE_256_TABLE_LENGTH ((uint16_t)440 ) -#define ARMBITREVINDEXTABLE_512_TABLE_LENGTH ((uint16_t)448 ) +#define ARMBITREVINDEXTABLE__16_TABLE_LENGTH ((uint16_t)20) +#define ARMBITREVINDEXTABLE__32_TABLE_LENGTH ((uint16_t)48) +#define ARMBITREVINDEXTABLE__64_TABLE_LENGTH ((uint16_t)56) +#define ARMBITREVINDEXTABLE_128_TABLE_LENGTH ((uint16_t)208) +#define ARMBITREVINDEXTABLE_256_TABLE_LENGTH ((uint16_t)440) +#define ARMBITREVINDEXTABLE_512_TABLE_LENGTH ((uint16_t)448) #define ARMBITREVINDEXTABLE1024_TABLE_LENGTH ((uint16_t)1800) #define ARMBITREVINDEXTABLE2048_TABLE_LENGTH ((uint16_t)3808) #define ARMBITREVINDEXTABLE4096_TABLE_LENGTH ((uint16_t)4032) @@ -108,13 +107,13 @@ extern const uint16_t armBitRevIndexTable2048[ARMBITREVINDEXTABLE2048_TABLE_LENG extern const uint16_t armBitRevIndexTable4096[ARMBITREVINDEXTABLE4096_TABLE_LENGTH]; /* fixed-point bit reversal tables */ -#define ARMBITREVINDEXTABLE_FIXED___16_TABLE_LENGTH ((uint16_t)12 ) -#define ARMBITREVINDEXTABLE_FIXED___32_TABLE_LENGTH ((uint16_t)24 ) -#define ARMBITREVINDEXTABLE_FIXED___64_TABLE_LENGTH ((uint16_t)56 ) -#define ARMBITREVINDEXTABLE_FIXED__128_TABLE_LENGTH ((uint16_t)112 ) -#define ARMBITREVINDEXTABLE_FIXED__256_TABLE_LENGTH ((uint16_t)240 ) -#define ARMBITREVINDEXTABLE_FIXED__512_TABLE_LENGTH ((uint16_t)480 ) -#define ARMBITREVINDEXTABLE_FIXED_1024_TABLE_LENGTH ((uint16_t)992 ) +#define ARMBITREVINDEXTABLE_FIXED___16_TABLE_LENGTH ((uint16_t)12) +#define ARMBITREVINDEXTABLE_FIXED___32_TABLE_LENGTH ((uint16_t)24) +#define ARMBITREVINDEXTABLE_FIXED___64_TABLE_LENGTH ((uint16_t)56) +#define ARMBITREVINDEXTABLE_FIXED__128_TABLE_LENGTH ((uint16_t)112) +#define ARMBITREVINDEXTABLE_FIXED__256_TABLE_LENGTH ((uint16_t)240) +#define ARMBITREVINDEXTABLE_FIXED__512_TABLE_LENGTH ((uint16_t)480) +#define ARMBITREVINDEXTABLE_FIXED_1024_TABLE_LENGTH ((uint16_t)992) #define ARMBITREVINDEXTABLE_FIXED_2048_TABLE_LENGTH ((uint16_t)1984) #define ARMBITREVINDEXTABLE_FIXED_4096_TABLE_LENGTH ((uint16_t)4032) diff --git a/bsp/swm320-lq100/Libraries/CMSIS/CoreSupport/arm_const_structs.h b/bsp/swm320-lq100/Libraries/CMSIS/CoreSupport/arm_const_structs.h index 217f1d50e2..2033c5e375 100644 --- a/bsp/swm320-lq100/Libraries/CMSIS/CoreSupport/arm_const_structs.h +++ b/bsp/swm320-lq100/Libraries/CMSIS/CoreSupport/arm_const_structs.h @@ -2,12 +2,12 @@ * Copyright (C) 2010-2014 ARM Limited. All rights reserved. * * $Date: 31. July 2014 -* $Revision: V1.4.4 +* $Revision: V1.4.4 * -* Project: CMSIS DSP Library -* Title: arm_const_structs.h +* Project: CMSIS DSP Library +* Title: arm_const_structs.h * -* Description: This file has constant structs that are initialized for +* Description: This file has constant structs that are initialized for * user convenience. For example, some can be given as * arguments to the arm_cfft_f32() function. * @@ -46,34 +46,34 @@ #include "arm_math.h" #include "arm_common_tables.h" - extern const arm_cfft_instance_f32 arm_cfft_sR_f32_len16; - extern const arm_cfft_instance_f32 arm_cfft_sR_f32_len32; - extern const arm_cfft_instance_f32 arm_cfft_sR_f32_len64; - extern const arm_cfft_instance_f32 arm_cfft_sR_f32_len128; - extern const arm_cfft_instance_f32 arm_cfft_sR_f32_len256; - extern const arm_cfft_instance_f32 arm_cfft_sR_f32_len512; - extern const arm_cfft_instance_f32 arm_cfft_sR_f32_len1024; - extern const arm_cfft_instance_f32 arm_cfft_sR_f32_len2048; - extern const arm_cfft_instance_f32 arm_cfft_sR_f32_len4096; +extern const arm_cfft_instance_f32 arm_cfft_sR_f32_len16; +extern const arm_cfft_instance_f32 arm_cfft_sR_f32_len32; +extern const arm_cfft_instance_f32 arm_cfft_sR_f32_len64; +extern const arm_cfft_instance_f32 arm_cfft_sR_f32_len128; +extern const arm_cfft_instance_f32 arm_cfft_sR_f32_len256; +extern const arm_cfft_instance_f32 arm_cfft_sR_f32_len512; +extern const arm_cfft_instance_f32 arm_cfft_sR_f32_len1024; +extern const arm_cfft_instance_f32 arm_cfft_sR_f32_len2048; +extern const arm_cfft_instance_f32 arm_cfft_sR_f32_len4096; - extern const arm_cfft_instance_q31 arm_cfft_sR_q31_len16; - extern const arm_cfft_instance_q31 arm_cfft_sR_q31_len32; - extern const arm_cfft_instance_q31 arm_cfft_sR_q31_len64; - extern const arm_cfft_instance_q31 arm_cfft_sR_q31_len128; - extern const arm_cfft_instance_q31 arm_cfft_sR_q31_len256; - extern const arm_cfft_instance_q31 arm_cfft_sR_q31_len512; - extern const arm_cfft_instance_q31 arm_cfft_sR_q31_len1024; - extern const arm_cfft_instance_q31 arm_cfft_sR_q31_len2048; - extern const arm_cfft_instance_q31 arm_cfft_sR_q31_len4096; +extern const arm_cfft_instance_q31 arm_cfft_sR_q31_len16; +extern const arm_cfft_instance_q31 arm_cfft_sR_q31_len32; +extern const arm_cfft_instance_q31 arm_cfft_sR_q31_len64; +extern const arm_cfft_instance_q31 arm_cfft_sR_q31_len128; +extern const arm_cfft_instance_q31 arm_cfft_sR_q31_len256; +extern const arm_cfft_instance_q31 arm_cfft_sR_q31_len512; +extern const arm_cfft_instance_q31 arm_cfft_sR_q31_len1024; +extern const arm_cfft_instance_q31 arm_cfft_sR_q31_len2048; +extern const arm_cfft_instance_q31 arm_cfft_sR_q31_len4096; - extern const arm_cfft_instance_q15 arm_cfft_sR_q15_len16; - extern const arm_cfft_instance_q15 arm_cfft_sR_q15_len32; - extern const arm_cfft_instance_q15 arm_cfft_sR_q15_len64; - extern const arm_cfft_instance_q15 arm_cfft_sR_q15_len128; - extern const arm_cfft_instance_q15 arm_cfft_sR_q15_len256; - extern const arm_cfft_instance_q15 arm_cfft_sR_q15_len512; - extern const arm_cfft_instance_q15 arm_cfft_sR_q15_len1024; - extern const arm_cfft_instance_q15 arm_cfft_sR_q15_len2048; - extern const arm_cfft_instance_q15 arm_cfft_sR_q15_len4096; +extern const arm_cfft_instance_q15 arm_cfft_sR_q15_len16; +extern const arm_cfft_instance_q15 arm_cfft_sR_q15_len32; +extern const arm_cfft_instance_q15 arm_cfft_sR_q15_len64; +extern const arm_cfft_instance_q15 arm_cfft_sR_q15_len128; +extern const arm_cfft_instance_q15 arm_cfft_sR_q15_len256; +extern const arm_cfft_instance_q15 arm_cfft_sR_q15_len512; +extern const arm_cfft_instance_q15 arm_cfft_sR_q15_len1024; +extern const arm_cfft_instance_q15 arm_cfft_sR_q15_len2048; +extern const arm_cfft_instance_q15 arm_cfft_sR_q15_len4096; #endif diff --git a/bsp/swm320-lq100/Libraries/CMSIS/CoreSupport/arm_math.h b/bsp/swm320-lq100/Libraries/CMSIS/CoreSupport/arm_math.h index f06a0713eb..5698fe08ab 100644 --- a/bsp/swm320-lq100/Libraries/CMSIS/CoreSupport/arm_math.h +++ b/bsp/swm320-lq100/Libraries/CMSIS/CoreSupport/arm_math.h @@ -2,12 +2,12 @@ * Copyright (C) 2010-2014 ARM Limited. All rights reserved. * * $Date: 12. March 2014 -* $Revision: V1.4.4 +* $Revision: V1.4.4 * -* Project: CMSIS DSP Library -* Title: arm_math.h +* Project: CMSIS DSP Library +* Title: arm_math.h * -* Description: Public header file for CMSIS DSP Library +* Description: Public header file for CMSIS DSP Library * * Target Processor: Cortex-M7/Cortex-M4/Cortex-M3/Cortex-M0 * @@ -134,7 +134,7 @@ * <hr> * CMSIS-DSP in ARM::CMSIS Pack * ----------------------------- - * + * * The following files relevant to CMSIS-DSP are present in the <b>ARM::CMSIS</b> Pack directories: * |File/Folder |Content | * |------------------------------|------------------------------------------------------------------------| @@ -142,7 +142,7 @@ * |\b CMSIS\\DSP_Lib | Software license agreement (license.txt) | * |\b CMSIS\\DSP_Lib\\Examples | Example projects demonstrating the usage of the library functions | * |\b CMSIS\\DSP_Lib\\Source | Source files for rebuilding the library | - * + * * <hr> * Revision History of CMSIS-DSP * ------------ @@ -154,7 +154,6 @@ * Copyright (C) 2010-2014 ARM Limited. All rights reserved. */ - /** * @defgroup groupMath Basic Math Functions */ @@ -281,122 +280,121 @@ #ifndef _ARM_MATH_H #define _ARM_MATH_H -#define __CMSIS_GENERIC /* disable NVIC and Systick functions */ +#define __CMSIS_GENERIC /* disable NVIC and Systick functions */ #if defined(ARM_MATH_CM7) - #include "core_cm7.h" -#elif defined (ARM_MATH_CM4) - #include "core_cm4.h" -#elif defined (ARM_MATH_CM3) - #include "core_cm3.h" -#elif defined (ARM_MATH_CM0) - #include "core_cm0.h" +#include "core_cm7.h" +#elif defined(ARM_MATH_CM4) +#include "core_cm4.h" +#elif defined(ARM_MATH_CM3) +#include "core_cm3.h" +#elif defined(ARM_MATH_CM0) +#include "core_cm0.h" #define ARM_MATH_CM0_FAMILY - #elif defined (ARM_MATH_CM0PLUS) +#elif defined(ARM_MATH_CM0PLUS) #include "core_cm0plus.h" - #define ARM_MATH_CM0_FAMILY +#define ARM_MATH_CM0_FAMILY #else - #error "Define according the used Cortex core ARM_MATH_CM7, ARM_MATH_CM4, ARM_MATH_CM3, ARM_MATH_CM0PLUS or ARM_MATH_CM0" +#error "Define according the used Cortex core ARM_MATH_CM7, ARM_MATH_CM4, ARM_MATH_CM3, ARM_MATH_CM0PLUS or ARM_MATH_CM0" #endif -#undef __CMSIS_GENERIC /* enable NVIC and Systick functions */ +#undef __CMSIS_GENERIC /* enable NVIC and Systick functions */ #include "string.h" #include "math.h" -#ifdef __cplusplus +#ifdef __cplusplus extern "C" { #endif - - /** + /** * @brief Macros required for reciprocal calculation in Normalized LMS */ -#define DELTA_Q31 (0x100) -#define DELTA_Q15 0x5 -#define INDEX_MASK 0x0000003F +#define DELTA_Q31 (0x100) +#define DELTA_Q15 0x5 +#define INDEX_MASK 0x0000003F #ifndef PI -#define PI 3.14159265358979f +#define PI 3.14159265358979f #endif - /** + /** * @brief Macros required for SINE and COSINE Fast math approximations */ -#define FAST_MATH_TABLE_SIZE 512 -#define FAST_MATH_Q31_SHIFT (32 - 10) -#define FAST_MATH_Q15_SHIFT (16 - 10) -#define CONTROLLER_Q31_SHIFT (32 - 9) -#define TABLE_SIZE 256 -#define TABLE_SPACING_Q31 0x400000 -#define TABLE_SPACING_Q15 0x80 +#define FAST_MATH_TABLE_SIZE 512 +#define FAST_MATH_Q31_SHIFT (32 - 10) +#define FAST_MATH_Q15_SHIFT (16 - 10) +#define CONTROLLER_Q31_SHIFT (32 - 9) +#define TABLE_SIZE 256 +#define TABLE_SPACING_Q31 0x400000 +#define TABLE_SPACING_Q15 0x80 - /** + /** * @brief Macros required for SINE and COSINE Controller functions */ - /* 1.31(q31) Fixed value of 2/360 */ - /* -1 to +1 is divided into 360 values so total spacing is (2/360) */ -#define INPUT_SPACING 0xB60B61 + /* 1.31(q31) Fixed value of 2/360 */ + /* -1 to +1 is divided into 360 values so total spacing is (2/360) */ +#define INPUT_SPACING 0xB60B61 - /** + /** * @brief Macro for Unaligned Support */ #ifndef UNALIGNED_SUPPORT_DISABLE - #define ALIGN4 +#define ALIGN4 #else - #if defined (__GNUC__) - #define ALIGN4 __attribute__((aligned(4))) - #else - #define ALIGN4 __align(4) - #endif -#endif /* #ifndef UNALIGNED_SUPPORT_DISABLE */ +#if defined(__GNUC__) +#define ALIGN4 __attribute__((aligned(4))) +#else +#define ALIGN4 __align(4) +#endif +#endif /* #ifndef UNALIGNED_SUPPORT_DISABLE */ - /** + /** * @brief Error status returned by some functions in the library. */ - typedef enum - { - ARM_MATH_SUCCESS = 0, /**< No error */ - ARM_MATH_ARGUMENT_ERROR = -1, /**< One or more arguments are incorrect */ - ARM_MATH_LENGTH_ERROR = -2, /**< Length of data buffer is incorrect */ - ARM_MATH_SIZE_MISMATCH = -3, /**< Size of matrices is not compatible with the operation. */ - ARM_MATH_NANINF = -4, /**< Not-a-number (NaN) or infinity is generated */ - ARM_MATH_SINGULAR = -5, /**< Generated by matrix inversion if the input matrix is singular and cannot be inverted. */ - ARM_MATH_TEST_FAILURE = -6 /**< Test Failed */ - } arm_status; + typedef enum + { + ARM_MATH_SUCCESS = 0, /**< No error */ + ARM_MATH_ARGUMENT_ERROR = -1, /**< One or more arguments are incorrect */ + ARM_MATH_LENGTH_ERROR = -2, /**< Length of data buffer is incorrect */ + ARM_MATH_SIZE_MISMATCH = -3, /**< Size of matrices is not compatible with the operation. */ + ARM_MATH_NANINF = -4, /**< Not-a-number (NaN) or infinity is generated */ + ARM_MATH_SINGULAR = -5, /**< Generated by matrix inversion if the input matrix is singular and cannot be inverted. */ + ARM_MATH_TEST_FAILURE = -6 /**< Test Failed */ + } arm_status; - /** + /** * @brief 8-bit fractional data type in 1.7 format. */ - typedef int8_t q7_t; + typedef int8_t q7_t; - /** + /** * @brief 16-bit fractional data type in 1.15 format. */ - typedef int16_t q15_t; + typedef int16_t q15_t; - /** + /** * @brief 32-bit fractional data type in 1.31 format. */ - typedef int32_t q31_t; + typedef int32_t q31_t; - /** + /** * @brief 64-bit fractional data type in 1.63 format. */ - typedef int64_t q63_t; + typedef int64_t q63_t; - /** + /** * @brief 32-bit floating-point type definition. */ - typedef float float32_t; + typedef float float32_t; - /** + /** * @brief 64-bit floating-point type definition. */ - typedef double float64_t; + typedef double float64_t; - /** + /** * @brief definition to read/write two 16 bit values. */ #if defined __CC_ARM @@ -408,704 +406,681 @@ extern "C" #elif defined __GNUC__ #define __SIMD32_TYPE int32_t #define CMSIS_UNUSED __attribute__((unused)) -#elif defined __CSMC__ /* Cosmic */ +#elif defined __CSMC__ /* Cosmic */ #define CMSIS_UNUSED #define __SIMD32_TYPE int32_t #else #error Unknown compiler #endif -#define __SIMD32(addr) (*(__SIMD32_TYPE **) & (addr)) -#define __SIMD32_CONST(addr) ((__SIMD32_TYPE *)(addr)) +#define __SIMD32(addr) (*(__SIMD32_TYPE **)&(addr)) +#define __SIMD32_CONST(addr) ((__SIMD32_TYPE *)(addr)) -#define _SIMD32_OFFSET(addr) (*(__SIMD32_TYPE *) (addr)) +#define _SIMD32_OFFSET(addr) (*(__SIMD32_TYPE *)(addr)) -#define __SIMD64(addr) (*(int64_t **) & (addr)) +#define __SIMD64(addr) (*(int64_t **)&(addr)) -#if defined (ARM_MATH_CM3) || defined (ARM_MATH_CM0_FAMILY) - /** +#if defined(ARM_MATH_CM3) || defined(ARM_MATH_CM0_FAMILY) + /** * @brief definition to pack two 16 bit values. */ -#define __PKHBT(ARG1, ARG2, ARG3) ( (((int32_t)(ARG1) << 0) & (int32_t)0x0000FFFF) | \ - (((int32_t)(ARG2) << ARG3) & (int32_t)0xFFFF0000) ) -#define __PKHTB(ARG1, ARG2, ARG3) ( (((int32_t)(ARG1) << 0) & (int32_t)0xFFFF0000) | \ - (((int32_t)(ARG2) >> ARG3) & (int32_t)0x0000FFFF) ) +#define __PKHBT(ARG1, ARG2, ARG3) ((((int32_t)(ARG1) << 0) & (int32_t)0x0000FFFF) | \ + (((int32_t)(ARG2) << ARG3) & (int32_t)0xFFFF0000)) +#define __PKHTB(ARG1, ARG2, ARG3) ((((int32_t)(ARG1) << 0) & (int32_t)0xFFFF0000) | \ + (((int32_t)(ARG2) >> ARG3) & (int32_t)0x0000FFFF)) #endif - - /** + /** * @brief definition to pack four 8 bit values. */ #ifndef ARM_MATH_BIG_ENDIAN -#define __PACKq7(v0,v1,v2,v3) ( (((int32_t)(v0) << 0) & (int32_t)0x000000FF) | \ - (((int32_t)(v1) << 8) & (int32_t)0x0000FF00) | \ - (((int32_t)(v2) << 16) & (int32_t)0x00FF0000) | \ - (((int32_t)(v3) << 24) & (int32_t)0xFF000000) ) +#define __PACKq7(v0, v1, v2, v3) ((((int32_t)(v0) << 0) & (int32_t)0x000000FF) | \ + (((int32_t)(v1) << 8) & (int32_t)0x0000FF00) | \ + (((int32_t)(v2) << 16) & (int32_t)0x00FF0000) | \ + (((int32_t)(v3) << 24) & (int32_t)0xFF000000)) #else -#define __PACKq7(v0,v1,v2,v3) ( (((int32_t)(v3) << 0) & (int32_t)0x000000FF) | \ - (((int32_t)(v2) << 8) & (int32_t)0x0000FF00) | \ - (((int32_t)(v1) << 16) & (int32_t)0x00FF0000) | \ - (((int32_t)(v0) << 24) & (int32_t)0xFF000000) ) +#define __PACKq7(v0, v1, v2, v3) ((((int32_t)(v3) << 0) & (int32_t)0x000000FF) | \ + (((int32_t)(v2) << 8) & (int32_t)0x0000FF00) | \ + (((int32_t)(v1) << 16) & (int32_t)0x00FF0000) | \ + (((int32_t)(v0) << 24) & (int32_t)0xFF000000)) #endif - - /** + /** * @brief Clips Q63 to Q31 values. */ - static __INLINE q31_t clip_q63_to_q31( - q63_t x) - { - return ((q31_t) (x >> 32) != ((q31_t) x >> 31)) ? - ((0x7FFFFFFF ^ ((q31_t) (x >> 63)))) : (q31_t) x; - } + static __INLINE q31_t clip_q63_to_q31( + q63_t x) + { + return ((q31_t)(x >> 32) != ((q31_t)x >> 31)) ? ((0x7FFFFFFF ^ ((q31_t)(x >> 63)))) : (q31_t)x; + } - /** + /** * @brief Clips Q63 to Q15 values. */ - static __INLINE q15_t clip_q63_to_q15( - q63_t x) - { - return ((q31_t) (x >> 32) != ((q31_t) x >> 31)) ? - ((0x7FFF ^ ((q15_t) (x >> 63)))) : (q15_t) (x >> 15); - } + static __INLINE q15_t clip_q63_to_q15( + q63_t x) + { + return ((q31_t)(x >> 32) != ((q31_t)x >> 31)) ? ((0x7FFF ^ ((q15_t)(x >> 63)))) : (q15_t)(x >> 15); + } - /** + /** * @brief Clips Q31 to Q7 values. */ - static __INLINE q7_t clip_q31_to_q7( - q31_t x) - { - return ((q31_t) (x >> 24) != ((q31_t) x >> 23)) ? - ((0x7F ^ ((q7_t) (x >> 31)))) : (q7_t) x; - } + static __INLINE q7_t clip_q31_to_q7( + q31_t x) + { + return ((q31_t)(x >> 24) != ((q31_t)x >> 23)) ? ((0x7F ^ ((q7_t)(x >> 31)))) : (q7_t)x; + } - /** + /** * @brief Clips Q31 to Q15 values. */ - static __INLINE q15_t clip_q31_to_q15( - q31_t x) - { - return ((q31_t) (x >> 16) != ((q31_t) x >> 15)) ? - ((0x7FFF ^ ((q15_t) (x >> 31)))) : (q15_t) x; - } + static __INLINE q15_t clip_q31_to_q15( + q31_t x) + { + return ((q31_t)(x >> 16) != ((q31_t)x >> 15)) ? ((0x7FFF ^ ((q15_t)(x >> 31)))) : (q15_t)x; + } - /** + /** * @brief Multiplies 32 X 64 and returns 32 bit result in 2.30 format. */ - static __INLINE q63_t mult32x64( - q63_t x, - q31_t y) - { - return ((((q63_t) (x & 0x00000000FFFFFFFF) * y) >> 32) + - (((q63_t) (x >> 32) * y))); - } - + static __INLINE q63_t mult32x64( + q63_t x, + q31_t y) + { + return ((((q63_t)(x & 0x00000000FFFFFFFF) * y) >> 32) + + (((q63_t)(x >> 32) * y))); + } -#if defined (ARM_MATH_CM0_FAMILY) && defined ( __CC_ARM ) +#if defined(ARM_MATH_CM0_FAMILY) && defined(__CC_ARM) #define __CLZ __clz #endif -#if defined (ARM_MATH_CM0_FAMILY) && ((defined (__ICCARM__)) ||(defined (__GNUC__)) || defined (__TASKING__) ) +#if defined(ARM_MATH_CM0_FAMILY) && ((defined(__ICCARM__)) || (defined(__GNUC__)) || defined(__TASKING__)) - static __INLINE uint32_t __CLZ( - q31_t data); + static __INLINE uint32_t __CLZ( + q31_t data); - - static __INLINE uint32_t __CLZ( - q31_t data) - { - uint32_t count = 0; - uint32_t mask = 0x80000000; - - while((data & mask) == 0) + static __INLINE uint32_t __CLZ( + q31_t data) { - count += 1u; - mask = mask >> 1u; - } + uint32_t count = 0; + uint32_t mask = 0x80000000; - return (count); + while ((data & mask) == 0) + { + count += 1u; + mask = mask >> 1u; + } - } + return (count); + } #endif - /** + /** * @brief Function to Calculates 1/in (reciprocal) value of Q31 Data type. */ - static __INLINE uint32_t arm_recip_q31( - q31_t in, - q31_t * dst, - q31_t * pRecipTable) - { - - uint32_t out, tempVal; - uint32_t index, i; - uint32_t signBits; - - if(in > 0) + static __INLINE uint32_t arm_recip_q31( + q31_t in, + q31_t *dst, + q31_t *pRecipTable) { - signBits = __CLZ(in) - 1; - } - else - { - signBits = __CLZ(-in) - 1; - } - /* Convert input sample to 1.31 format */ - in = in << signBits; + uint32_t out, tempVal; + uint32_t index, i; + uint32_t signBits; - /* calculation of index for initial approximated Val */ - index = (uint32_t) (in >> 24u); - index = (index & INDEX_MASK); + if (in > 0) + { + signBits = __CLZ(in) - 1; + } + else + { + signBits = __CLZ(-in) - 1; + } - /* 1.31 with exp 1 */ - out = pRecipTable[index]; + /* Convert input sample to 1.31 format */ + in = in << signBits; - /* calculation of reciprocal value */ - /* running approximation for two iterations */ - for (i = 0u; i < 2u; i++) - { - tempVal = (q31_t) (((q63_t) in * out) >> 31u); - tempVal = 0x7FFFFFFF - tempVal; - /* 1.31 with exp 1 */ - //out = (q31_t) (((q63_t) out * tempVal) >> 30u); - out = (q31_t) clip_q63_to_q31(((q63_t) out * tempVal) >> 30u); - } + /* calculation of index for initial approximated Val */ + index = (uint32_t)(in >> 24u); + index = (index & INDEX_MASK); - /* write output */ - *dst = out; + /* 1.31 with exp 1 */ + out = pRecipTable[index]; - /* return num of signbits of out = 1/in value */ - return (signBits + 1u); + /* calculation of reciprocal value */ + /* running approximation for two iterations */ + for (i = 0u; i < 2u; i++) + { + tempVal = (q31_t)(((q63_t)in * out) >> 31u); + tempVal = 0x7FFFFFFF - tempVal; + /* 1.31 with exp 1 */ + //out = (q31_t) (((q63_t) out * tempVal) >> 30u); + out = (q31_t)clip_q63_to_q31(((q63_t)out * tempVal) >> 30u); + } - } + /* write output */ + *dst = out; - /** + /* return num of signbits of out = 1/in value */ + return (signBits + 1u); + } + + /** * @brief Function to Calculates 1/in (reciprocal) value of Q15 Data type. */ - static __INLINE uint32_t arm_recip_q15( - q15_t in, - q15_t * dst, - q15_t * pRecipTable) - { - - uint32_t out = 0, tempVal = 0; - uint32_t index = 0, i = 0; - uint32_t signBits = 0; - - if(in > 0) + static __INLINE uint32_t arm_recip_q15( + q15_t in, + q15_t *dst, + q15_t *pRecipTable) { - signBits = __CLZ(in) - 17; - } - else - { - signBits = __CLZ(-in) - 17; - } - /* Convert input sample to 1.15 format */ - in = in << signBits; + uint32_t out = 0, tempVal = 0; + uint32_t index = 0, i = 0; + uint32_t signBits = 0; - /* calculation of index for initial approximated Val */ - index = in >> 8; - index = (index & INDEX_MASK); + if (in > 0) + { + signBits = __CLZ(in) - 17; + } + else + { + signBits = __CLZ(-in) - 17; + } - /* 1.15 with exp 1 */ - out = pRecipTable[index]; + /* Convert input sample to 1.15 format */ + in = in << signBits; - /* calculation of reciprocal value */ - /* running approximation for two iterations */ - for (i = 0; i < 2; i++) - { - tempVal = (q15_t) (((q31_t) in * out) >> 15); - tempVal = 0x7FFF - tempVal; - /* 1.15 with exp 1 */ - out = (q15_t) (((q31_t) out * tempVal) >> 14); - } + /* calculation of index for initial approximated Val */ + index = in >> 8; + index = (index & INDEX_MASK); - /* write output */ - *dst = out; + /* 1.15 with exp 1 */ + out = pRecipTable[index]; - /* return num of signbits of out = 1/in value */ - return (signBits + 1); + /* calculation of reciprocal value */ + /* running approximation for two iterations */ + for (i = 0; i < 2; i++) + { + tempVal = (q15_t)(((q31_t)in * out) >> 15); + tempVal = 0x7FFF - tempVal; + /* 1.15 with exp 1 */ + out = (q15_t)(((q31_t)out * tempVal) >> 14); + } - } + /* write output */ + *dst = out; + /* return num of signbits of out = 1/in value */ + return (signBits + 1); + } - /* + /* * @brief C custom defined intrinisic function for only M0 processors */ #if defined(ARM_MATH_CM0_FAMILY) - static __INLINE q31_t __SSAT( - q31_t x, - uint32_t y) - { - int32_t posMax, negMin; - uint32_t i; - - posMax = 1; - for (i = 0; i < (y - 1); i++) - { - posMax = posMax * 2; - } - - if(x > 0) + static __INLINE q31_t __SSAT( + q31_t x, + uint32_t y) { - posMax = (posMax - 1); + int32_t posMax, negMin; + uint32_t i; - if(x > posMax) - { - x = posMax; - } - } - else - { - negMin = -posMax; + posMax = 1; + for (i = 0; i < (y - 1); i++) + { + posMax = posMax * 2; + } - if(x < negMin) - { - x = negMin; - } - } - return (x); + if (x > 0) + { + posMax = (posMax - 1); + if (x > posMax) + { + x = posMax; + } + } + else + { + negMin = -posMax; - } + if (x < negMin) + { + x = negMin; + } + } + return (x); + } #endif /* end of ARM_MATH_CM0_FAMILY */ - - - /* + /* * @brief C custom defined intrinsic function for M3 and M0 processors */ -#if defined (ARM_MATH_CM3) || defined (ARM_MATH_CM0_FAMILY) +#if defined(ARM_MATH_CM3) || defined(ARM_MATH_CM0_FAMILY) - /* + /* * @brief C custom defined QADD8 for M3 and M0 processors */ - static __INLINE q31_t __QADD8( - q31_t x, - q31_t y) - { - - q31_t sum; - q7_t r, s, t, u; + static __INLINE q31_t __QADD8( + q31_t x, + q31_t y) + { - r = (q7_t) x; - s = (q7_t) y; + q31_t sum; + q7_t r, s, t, u; - r = __SSAT((q31_t) (r + s), 8); - s = __SSAT(((q31_t) (((x << 16) >> 24) + ((y << 16) >> 24))), 8); - t = __SSAT(((q31_t) (((x << 8) >> 24) + ((y << 8) >> 24))), 8); - u = __SSAT(((q31_t) ((x >> 24) + (y >> 24))), 8); + r = (q7_t)x; + s = (q7_t)y; - sum = - (((q31_t) u << 24) & 0xFF000000) | (((q31_t) t << 16) & 0x00FF0000) | - (((q31_t) s << 8) & 0x0000FF00) | (r & 0x000000FF); + r = __SSAT((q31_t)(r + s), 8); + s = __SSAT(((q31_t)(((x << 16) >> 24) + ((y << 16) >> 24))), 8); + t = __SSAT(((q31_t)(((x << 8) >> 24) + ((y << 8) >> 24))), 8); + u = __SSAT(((q31_t)((x >> 24) + (y >> 24))), 8); - return sum; + sum = + (((q31_t)u << 24) & 0xFF000000) | (((q31_t)t << 16) & 0x00FF0000) | + (((q31_t)s << 8) & 0x0000FF00) | (r & 0x000000FF); - } + return sum; + } - /* + /* * @brief C custom defined QSUB8 for M3 and M0 processors */ - static __INLINE q31_t __QSUB8( - q31_t x, - q31_t y) - { + static __INLINE q31_t __QSUB8( + q31_t x, + q31_t y) + { - q31_t sum; - q31_t r, s, t, u; + q31_t sum; + q31_t r, s, t, u; - r = (q7_t) x; - s = (q7_t) y; + r = (q7_t)x; + s = (q7_t)y; - r = __SSAT((r - s), 8); - s = __SSAT(((q31_t) (((x << 16) >> 24) - ((y << 16) >> 24))), 8) << 8; - t = __SSAT(((q31_t) (((x << 8) >> 24) - ((y << 8) >> 24))), 8) << 16; - u = __SSAT(((q31_t) ((x >> 24) - (y >> 24))), 8) << 24; + r = __SSAT((r - s), 8); + s = __SSAT(((q31_t)(((x << 16) >> 24) - ((y << 16) >> 24))), 8) << 8; + t = __SSAT(((q31_t)(((x << 8) >> 24) - ((y << 8) >> 24))), 8) << 16; + u = __SSAT(((q31_t)((x >> 24) - (y >> 24))), 8) << 24; - sum = - (u & 0xFF000000) | (t & 0x00FF0000) | (s & 0x0000FF00) | (r & - 0x000000FF); + sum = + (u & 0xFF000000) | (t & 0x00FF0000) | (s & 0x0000FF00) | (r & 0x000000FF); - return sum; - } + return sum; + } - /* + /* * @brief C custom defined QADD16 for M3 and M0 processors */ - /* + /* * @brief C custom defined QADD16 for M3 and M0 processors */ - static __INLINE q31_t __QADD16( - q31_t x, - q31_t y) - { - - q31_t sum; - q31_t r, s; + static __INLINE q31_t __QADD16( + q31_t x, + q31_t y) + { - r = (q15_t) x; - s = (q15_t) y; + q31_t sum; + q31_t r, s; - r = __SSAT(r + s, 16); - s = __SSAT(((q31_t) ((x >> 16) + (y >> 16))), 16) << 16; + r = (q15_t)x; + s = (q15_t)y; - sum = (s & 0xFFFF0000) | (r & 0x0000FFFF); + r = __SSAT(r + s, 16); + s = __SSAT(((q31_t)((x >> 16) + (y >> 16))), 16) << 16; - return sum; + sum = (s & 0xFFFF0000) | (r & 0x0000FFFF); - } + return sum; + } - /* + /* * @brief C custom defined SHADD16 for M3 and M0 processors */ - static __INLINE q31_t __SHADD16( - q31_t x, - q31_t y) - { - - q31_t sum; - q31_t r, s; + static __INLINE q31_t __SHADD16( + q31_t x, + q31_t y) + { - r = (q15_t) x; - s = (q15_t) y; + q31_t sum; + q31_t r, s; - r = ((r >> 1) + (s >> 1)); - s = ((q31_t) ((x >> 17) + (y >> 17))) << 16; + r = (q15_t)x; + s = (q15_t)y; - sum = (s & 0xFFFF0000) | (r & 0x0000FFFF); + r = ((r >> 1) + (s >> 1)); + s = ((q31_t)((x >> 17) + (y >> 17))) << 16; - return sum; + sum = (s & 0xFFFF0000) | (r & 0x0000FFFF); - } + return sum; + } - /* + /* * @brief C custom defined QSUB16 for M3 and M0 processors */ - static __INLINE q31_t __QSUB16( - q31_t x, - q31_t y) - { + static __INLINE q31_t __QSUB16( + q31_t x, + q31_t y) + { - q31_t sum; - q31_t r, s; + q31_t sum; + q31_t r, s; - r = (q15_t) x; - s = (q15_t) y; + r = (q15_t)x; + s = (q15_t)y; - r = __SSAT(r - s, 16); - s = __SSAT(((q31_t) ((x >> 16) - (y >> 16))), 16) << 16; + r = __SSAT(r - s, 16); + s = __SSAT(((q31_t)((x >> 16) - (y >> 16))), 16) << 16; - sum = (s & 0xFFFF0000) | (r & 0x0000FFFF); + sum = (s & 0xFFFF0000) | (r & 0x0000FFFF); - return sum; - } + return sum; + } - /* + /* * @brief C custom defined SHSUB16 for M3 and M0 processors */ - static __INLINE q31_t __SHSUB16( - q31_t x, - q31_t y) - { + static __INLINE q31_t __SHSUB16( + q31_t x, + q31_t y) + { - q31_t diff; - q31_t r, s; + q31_t diff; + q31_t r, s; - r = (q15_t) x; - s = (q15_t) y; + r = (q15_t)x; + s = (q15_t)y; - r = ((r >> 1) - (s >> 1)); - s = (((x >> 17) - (y >> 17)) << 16); + r = ((r >> 1) - (s >> 1)); + s = (((x >> 17) - (y >> 17)) << 16); - diff = (s & 0xFFFF0000) | (r & 0x0000FFFF); + diff = (s & 0xFFFF0000) | (r & 0x0000FFFF); - return diff; - } + return diff; + } - /* + /* * @brief C custom defined QASX for M3 and M0 processors */ - static __INLINE q31_t __QASX( - q31_t x, - q31_t y) - { + static __INLINE q31_t __QASX( + q31_t x, + q31_t y) + { - q31_t sum = 0; + q31_t sum = 0; - sum = - ((sum + - clip_q31_to_q15((q31_t) ((q15_t) (x >> 16) + (q15_t) y))) << 16) + - clip_q31_to_q15((q31_t) ((q15_t) x - (q15_t) (y >> 16))); + sum = + ((sum + + clip_q31_to_q15((q31_t)((q15_t)(x >> 16) + (q15_t)y))) + << 16) + + clip_q31_to_q15((q31_t)((q15_t)x - (q15_t)(y >> 16))); - return sum; - } + return sum; + } - /* + /* * @brief C custom defined SHASX for M3 and M0 processors */ - static __INLINE q31_t __SHASX( - q31_t x, - q31_t y) - { - - q31_t sum; - q31_t r, s; + static __INLINE q31_t __SHASX( + q31_t x, + q31_t y) + { - r = (q15_t) x; - s = (q15_t) y; + q31_t sum; + q31_t r, s; - r = ((r >> 1) - (y >> 17)); - s = (((x >> 17) + (s >> 1)) << 16); + r = (q15_t)x; + s = (q15_t)y; - sum = (s & 0xFFFF0000) | (r & 0x0000FFFF); + r = ((r >> 1) - (y >> 17)); + s = (((x >> 17) + (s >> 1)) << 16); - return sum; - } + sum = (s & 0xFFFF0000) | (r & 0x0000FFFF); + return sum; + } - /* + /* * @brief C custom defined QSAX for M3 and M0 processors */ - static __INLINE q31_t __QSAX( - q31_t x, - q31_t y) - { + static __INLINE q31_t __QSAX( + q31_t x, + q31_t y) + { - q31_t sum = 0; + q31_t sum = 0; - sum = - ((sum + - clip_q31_to_q15((q31_t) ((q15_t) (x >> 16) - (q15_t) y))) << 16) + - clip_q31_to_q15((q31_t) ((q15_t) x + (q15_t) (y >> 16))); + sum = + ((sum + + clip_q31_to_q15((q31_t)((q15_t)(x >> 16) - (q15_t)y))) + << 16) + + clip_q31_to_q15((q31_t)((q15_t)x + (q15_t)(y >> 16))); - return sum; - } + return sum; + } - /* + /* * @brief C custom defined SHSAX for M3 and M0 processors */ - static __INLINE q31_t __SHSAX( - q31_t x, - q31_t y) - { + static __INLINE q31_t __SHSAX( + q31_t x, + q31_t y) + { - q31_t sum; - q31_t r, s; + q31_t sum; + q31_t r, s; - r = (q15_t) x; - s = (q15_t) y; + r = (q15_t)x; + s = (q15_t)y; - r = ((r >> 1) + (y >> 17)); - s = (((x >> 17) - (s >> 1)) << 16); + r = ((r >> 1) + (y >> 17)); + s = (((x >> 17) - (s >> 1)) << 16); - sum = (s & 0xFFFF0000) | (r & 0x0000FFFF); + sum = (s & 0xFFFF0000) | (r & 0x0000FFFF); - return sum; - } + return sum; + } - /* + /* * @brief C custom defined SMUSDX for M3 and M0 processors */ - static __INLINE q31_t __SMUSDX( - q31_t x, - q31_t y) - { + static __INLINE q31_t __SMUSDX( + q31_t x, + q31_t y) + { - return ((q31_t) (((q15_t) x * (q15_t) (y >> 16)) - - ((q15_t) (x >> 16) * (q15_t) y))); - } + return ((q31_t)(((q15_t)x * (q15_t)(y >> 16)) - + ((q15_t)(x >> 16) * (q15_t)y))); + } - /* + /* * @brief C custom defined SMUADX for M3 and M0 processors */ - static __INLINE q31_t __SMUADX( - q31_t x, - q31_t y) - { + static __INLINE q31_t __SMUADX( + q31_t x, + q31_t y) + { - return ((q31_t) (((q15_t) x * (q15_t) (y >> 16)) + - ((q15_t) (x >> 16) * (q15_t) y))); - } + return ((q31_t)(((q15_t)x * (q15_t)(y >> 16)) + + ((q15_t)(x >> 16) * (q15_t)y))); + } - /* + /* * @brief C custom defined QADD for M3 and M0 processors */ - static __INLINE q31_t __QADD( - q31_t x, - q31_t y) - { - return clip_q63_to_q31((q63_t) x + y); - } + static __INLINE q31_t __QADD( + q31_t x, + q31_t y) + { + return clip_q63_to_q31((q63_t)x + y); + } - /* + /* * @brief C custom defined QSUB for M3 and M0 processors */ - static __INLINE q31_t __QSUB( - q31_t x, - q31_t y) - { - return clip_q63_to_q31((q63_t) x - y); - } + static __INLINE q31_t __QSUB( + q31_t x, + q31_t y) + { + return clip_q63_to_q31((q63_t)x - y); + } - /* + /* * @brief C custom defined SMLAD for M3 and M0 processors */ - static __INLINE q31_t __SMLAD( - q31_t x, - q31_t y, - q31_t sum) - { + static __INLINE q31_t __SMLAD( + q31_t x, + q31_t y, + q31_t sum) + { - return (sum + ((q15_t) (x >> 16) * (q15_t) (y >> 16)) + - ((q15_t) x * (q15_t) y)); - } + return (sum + ((q15_t)(x >> 16) * (q15_t)(y >> 16)) + + ((q15_t)x * (q15_t)y)); + } - /* + /* * @brief C custom defined SMLADX for M3 and M0 processors */ - static __INLINE q31_t __SMLADX( - q31_t x, - q31_t y, - q31_t sum) - { + static __INLINE q31_t __SMLADX( + q31_t x, + q31_t y, + q31_t sum) + { - return (sum + ((q15_t) (x >> 16) * (q15_t) (y)) + - ((q15_t) x * (q15_t) (y >> 16))); - } + return (sum + ((q15_t)(x >> 16) * (q15_t)(y)) + + ((q15_t)x * (q15_t)(y >> 16))); + } - /* + /* * @brief C custom defined SMLSDX for M3 and M0 processors */ - static __INLINE q31_t __SMLSDX( - q31_t x, - q31_t y, - q31_t sum) - { + static __INLINE q31_t __SMLSDX( + q31_t x, + q31_t y, + q31_t sum) + { - return (sum - ((q15_t) (x >> 16) * (q15_t) (y)) + - ((q15_t) x * (q15_t) (y >> 16))); - } + return (sum - ((q15_t)(x >> 16) * (q15_t)(y)) + + ((q15_t)x * (q15_t)(y >> 16))); + } - /* + /* * @brief C custom defined SMLALD for M3 and M0 processors */ - static __INLINE q63_t __SMLALD( - q31_t x, - q31_t y, - q63_t sum) - { + static __INLINE q63_t __SMLALD( + q31_t x, + q31_t y, + q63_t sum) + { - return (sum + ((q15_t) (x >> 16) * (q15_t) (y >> 16)) + - ((q15_t) x * (q15_t) y)); - } + return (sum + ((q15_t)(x >> 16) * (q15_t)(y >> 16)) + + ((q15_t)x * (q15_t)y)); + } - /* + /* * @brief C custom defined SMLALDX for M3 and M0 processors */ - static __INLINE q63_t __SMLALDX( - q31_t x, - q31_t y, - q63_t sum) - { + static __INLINE q63_t __SMLALDX( + q31_t x, + q31_t y, + q63_t sum) + { - return (sum + ((q15_t) (x >> 16) * (q15_t) y)) + - ((q15_t) x * (q15_t) (y >> 16)); - } + return (sum + ((q15_t)(x >> 16) * (q15_t)y)) + + ((q15_t)x * (q15_t)(y >> 16)); + } - /* + /* * @brief C custom defined SMUAD for M3 and M0 processors */ - static __INLINE q31_t __SMUAD( - q31_t x, - q31_t y) - { + static __INLINE q31_t __SMUAD( + q31_t x, + q31_t y) + { - return (((x >> 16) * (y >> 16)) + - (((x << 16) >> 16) * ((y << 16) >> 16))); - } + return (((x >> 16) * (y >> 16)) + + (((x << 16) >> 16) * ((y << 16) >> 16))); + } - /* + /* * @brief C custom defined SMUSD for M3 and M0 processors */ - static __INLINE q31_t __SMUSD( - q31_t x, - q31_t y) - { - - return (-((x >> 16) * (y >> 16)) + - (((x << 16) >> 16) * ((y << 16) >> 16))); - } + static __INLINE q31_t __SMUSD( + q31_t x, + q31_t y) + { + return (-((x >> 16) * (y >> 16)) + + (((x << 16) >> 16) * ((y << 16) >> 16))); + } - /* + /* * @brief C custom defined SXTB16 for M3 and M0 processors */ - static __INLINE q31_t __SXTB16( - q31_t x) - { - - return ((((x << 24) >> 24) & 0x0000FFFF) | - (((x << 8) >> 8) & 0xFFFF0000)); - } + static __INLINE q31_t __SXTB16( + q31_t x) + { + return ((((x << 24) >> 24) & 0x0000FFFF) | + (((x << 8) >> 8) & 0xFFFF0000)); + } #endif /* defined (ARM_MATH_CM3) || defined (ARM_MATH_CM0_FAMILY) */ - - /** + /** * @brief Instance structure for the Q7 FIR filter. */ - typedef struct - { - uint16_t numTaps; /**< number of filter coefficients in the filter. */ - q7_t *pState; /**< points to the state variable array. The array is of length numTaps+blockSize-1. */ - q7_t *pCoeffs; /**< points to the coefficient array. The array is of length numTaps.*/ - } arm_fir_instance_q7; + typedef struct + { + uint16_t numTaps; /**< number of filter coefficients in the filter. */ + q7_t *pState; /**< points to the state variable array. The array is of length numTaps+blockSize-1. */ + q7_t *pCoeffs; /**< points to the coefficient array. The array is of length numTaps.*/ + } arm_fir_instance_q7; - /** + /** * @brief Instance structure for the Q15 FIR filter. */ - typedef struct - { - uint16_t numTaps; /**< number of filter coefficients in the filter. */ - q15_t *pState; /**< points to the state variable array. The array is of length numTaps+blockSize-1. */ - q15_t *pCoeffs; /**< points to the coefficient array. The array is of length numTaps.*/ - } arm_fir_instance_q15; + typedef struct + { + uint16_t numTaps; /**< number of filter coefficients in the filter. */ + q15_t *pState; /**< points to the state variable array. The array is of length numTaps+blockSize-1. */ + q15_t *pCoeffs; /**< points to the coefficient array. The array is of length numTaps.*/ + } arm_fir_instance_q15; - /** + /** * @brief Instance structure for the Q31 FIR filter. */ - typedef struct - { - uint16_t numTaps; /**< number of filter coefficients in the filter. */ - q31_t *pState; /**< points to the state variable array. The array is of length numTaps+blockSize-1. */ - q31_t *pCoeffs; /**< points to the coefficient array. The array is of length numTaps. */ - } arm_fir_instance_q31; + typedef struct + { + uint16_t numTaps; /**< number of filter coefficients in the filter. */ + q31_t *pState; /**< points to the state variable array. The array is of length numTaps+blockSize-1. */ + q31_t *pCoeffs; /**< points to the coefficient array. The array is of length numTaps. */ + } arm_fir_instance_q31; - /** + /** * @brief Instance structure for the floating-point FIR filter. */ - typedef struct - { - uint16_t numTaps; /**< number of filter coefficients in the filter. */ - float32_t *pState; /**< points to the state variable array. The array is of length numTaps+blockSize-1. */ - float32_t *pCoeffs; /**< points to the coefficient array. The array is of length numTaps. */ - } arm_fir_instance_f32; - + typedef struct + { + uint16_t numTaps; /**< number of filter coefficients in the filter. */ + float32_t *pState; /**< points to the state variable array. The array is of length numTaps+blockSize-1. */ + float32_t *pCoeffs; /**< points to the coefficient array. The array is of length numTaps. */ + } arm_fir_instance_f32; - /** + /** * @brief Processing function for the Q7 FIR filter. * @param[in] *S points to an instance of the Q7 FIR filter structure. * @param[in] *pSrc points to the block of input data. @@ -1113,14 +1088,13 @@ extern "C" * @param[in] blockSize number of samples to process. * @return none. */ - void arm_fir_q7( - const arm_fir_instance_q7 * S, - q7_t * pSrc, - q7_t * pDst, - uint32_t blockSize); + void arm_fir_q7( + const arm_fir_instance_q7 *S, + q7_t *pSrc, + q7_t *pDst, + uint32_t blockSize); - - /** + /** * @brief Initialization function for the Q7 FIR filter. * @param[in,out] *S points to an instance of the Q7 FIR structure. * @param[in] numTaps Number of filter coefficients in the filter. @@ -1129,15 +1103,14 @@ extern "C" * @param[in] blockSize number of samples that are processed. * @return none */ - void arm_fir_init_q7( - arm_fir_instance_q7 * S, - uint16_t numTaps, - q7_t * pCoeffs, - q7_t * pState, - uint32_t blockSize); + void arm_fir_init_q7( + arm_fir_instance_q7 *S, + uint16_t numTaps, + q7_t *pCoeffs, + q7_t *pState, + uint32_t blockSize); - - /** + /** * @brief Processing function for the Q15 FIR filter. * @param[in] *S points to an instance of the Q15 FIR structure. * @param[in] *pSrc points to the block of input data. @@ -1145,13 +1118,13 @@ extern "C" * @param[in] blockSize number of samples to process. * @return none. */ - void arm_fir_q15( - const arm_fir_instance_q15 * S, - q15_t * pSrc, - q15_t * pDst, - uint32_t blockSize); + void arm_fir_q15( + const arm_fir_instance_q15 *S, + q15_t *pSrc, + q15_t *pDst, + uint32_t blockSize); - /** + /** * @brief Processing function for the fast Q15 FIR filter for Cortex-M3 and Cortex-M4. * @param[in] *S points to an instance of the Q15 FIR filter structure. * @param[in] *pSrc points to the block of input data. @@ -1159,13 +1132,13 @@ extern "C" * @param[in] blockSize number of samples to process. * @return none. */ - void arm_fir_fast_q15( - const arm_fir_instance_q15 * S, - q15_t * pSrc, - q15_t * pDst, - uint32_t blockSize); + void arm_fir_fast_q15( + const arm_fir_instance_q15 *S, + q15_t *pSrc, + q15_t *pDst, + uint32_t blockSize); - /** + /** * @brief Initialization function for the Q15 FIR filter. * @param[in,out] *S points to an instance of the Q15 FIR filter structure. * @param[in] numTaps Number of filter coefficients in the filter. Must be even and greater than or equal to 4. @@ -1176,14 +1149,14 @@ extern "C" * <code>numTaps</code> is not a supported value. */ - arm_status arm_fir_init_q15( - arm_fir_instance_q15 * S, - uint16_t numTaps, - q15_t * pCoeffs, - q15_t * pState, - uint32_t blockSize); + arm_status arm_fir_init_q15( + arm_fir_instance_q15 *S, + uint16_t numTaps, + q15_t *pCoeffs, + q15_t *pState, + uint32_t blockSize); - /** + /** * @brief Processing function for the Q31 FIR filter. * @param[in] *S points to an instance of the Q31 FIR filter structure. * @param[in] *pSrc points to the block of input data. @@ -1191,13 +1164,13 @@ extern "C" * @param[in] blockSize number of samples to process. * @return none. */ - void arm_fir_q31( - const arm_fir_instance_q31 * S, - q31_t * pSrc, - q31_t * pDst, - uint32_t blockSize); + void arm_fir_q31( + const arm_fir_instance_q31 *S, + q31_t *pSrc, + q31_t *pDst, + uint32_t blockSize); - /** + /** * @brief Processing function for the fast Q31 FIR filter for Cortex-M3 and Cortex-M4. * @param[in] *S points to an instance of the Q31 FIR structure. * @param[in] *pSrc points to the block of input data. @@ -1205,29 +1178,29 @@ extern "C" * @param[in] blockSize number of samples to process. * @return none. */ - void arm_fir_fast_q31( - const arm_fir_instance_q31 * S, - q31_t * pSrc, - q31_t * pDst, - uint32_t blockSize); + void arm_fir_fast_q31( + const arm_fir_instance_q31 *S, + q31_t *pSrc, + q31_t *pDst, + uint32_t blockSize); - /** + /** * @brief Initialization function for the Q31 FIR filter. * @param[in,out] *S points to an instance of the Q31 FIR structure. - * @param[in] numTaps Number of filter coefficients in the filter. - * @param[in] *pCoeffs points to the filter coefficients. - * @param[in] *pState points to the state buffer. - * @param[in] blockSize number of samples that are processed at a time. - * @return none. + * @param[in] numTaps Number of filter coefficients in the filter. + * @param[in] *pCoeffs points to the filter coefficients. + * @param[in] *pState points to the state buffer. + * @param[in] blockSize number of samples that are processed at a time. + * @return none. */ - void arm_fir_init_q31( - arm_fir_instance_q31 * S, - uint16_t numTaps, - q31_t * pCoeffs, - q31_t * pState, - uint32_t blockSize); + void arm_fir_init_q31( + arm_fir_instance_q31 *S, + uint16_t numTaps, + q31_t *pCoeffs, + q31_t *pState, + uint32_t blockSize); - /** + /** * @brief Processing function for the floating-point FIR filter. * @param[in] *S points to an instance of the floating-point FIR structure. * @param[in] *pSrc points to the block of input data. @@ -1235,69 +1208,64 @@ extern "C" * @param[in] blockSize number of samples to process. * @return none. */ - void arm_fir_f32( - const arm_fir_instance_f32 * S, - float32_t * pSrc, - float32_t * pDst, - uint32_t blockSize); + void arm_fir_f32( + const arm_fir_instance_f32 *S, + float32_t *pSrc, + float32_t *pDst, + uint32_t blockSize); - /** + /** * @brief Initialization function for the floating-point FIR filter. * @param[in,out] *S points to an instance of the floating-point FIR filter structure. - * @param[in] numTaps Number of filter coefficients in the filter. - * @param[in] *pCoeffs points to the filter coefficients. - * @param[in] *pState points to the state buffer. - * @param[in] blockSize number of samples that are processed at a time. - * @return none. + * @param[in] numTaps Number of filter coefficients in the filter. + * @param[in] *pCoeffs points to the filter coefficients. + * @param[in] *pState points to the state buffer. + * @param[in] blockSize number of samples that are processed at a time. + * @return none. */ - void arm_fir_init_f32( - arm_fir_instance_f32 * S, - uint16_t numTaps, - float32_t * pCoeffs, - float32_t * pState, - uint32_t blockSize); + void arm_fir_init_f32( + arm_fir_instance_f32 *S, + uint16_t numTaps, + float32_t *pCoeffs, + float32_t *pState, + uint32_t blockSize); - - /** + /** * @brief Instance structure for the Q15 Biquad cascade filter. */ - typedef struct - { - int8_t numStages; /**< number of 2nd order stages in the filter. Overall order is 2*numStages. */ - q15_t *pState; /**< Points to the array of state coefficients. The array is of length 4*numStages. */ - q15_t *pCoeffs; /**< Points to the array of coefficients. The array is of length 5*numStages. */ - int8_t postShift; /**< Additional shift, in bits, applied to each output sample. */ - - } arm_biquad_casd_df1_inst_q15; + typedef struct + { + int8_t numStages; /**< number of 2nd order stages in the filter. Overall order is 2*numStages. */ + q15_t *pState; /**< Points to the array of state coefficients. The array is of length 4*numStages. */ + q15_t *pCoeffs; /**< Points to the array of coefficients. The array is of length 5*numStages. */ + int8_t postShift; /**< Additional shift, in bits, applied to each output sample. */ + } arm_biquad_casd_df1_inst_q15; - /** + /** * @brief Instance structure for the Q31 Biquad cascade filter. */ - typedef struct - { - uint32_t numStages; /**< number of 2nd order stages in the filter. Overall order is 2*numStages. */ - q31_t *pState; /**< Points to the array of state coefficients. The array is of length 4*numStages. */ - q31_t *pCoeffs; /**< Points to the array of coefficients. The array is of length 5*numStages. */ - uint8_t postShift; /**< Additional shift, in bits, applied to each output sample. */ + typedef struct + { + uint32_t numStages; /**< number of 2nd order stages in the filter. Overall order is 2*numStages. */ + q31_t *pState; /**< Points to the array of state coefficients. The array is of length 4*numStages. */ + q31_t *pCoeffs; /**< Points to the array of coefficients. The array is of length 5*numStages. */ + uint8_t postShift; /**< Additional shift, in bits, applied to each output sample. */ - } arm_biquad_casd_df1_inst_q31; + } arm_biquad_casd_df1_inst_q31; - /** + /** * @brief Instance structure for the floating-point Biquad cascade filter. */ - typedef struct - { - uint32_t numStages; /**< number of 2nd order stages in the filter. Overall order is 2*numStages. */ - float32_t *pState; /**< Points to the array of state coefficients. The array is of length 4*numStages. */ - float32_t *pCoeffs; /**< Points to the array of coefficients. The array is of length 5*numStages. */ - - - } arm_biquad_casd_df1_inst_f32; - + typedef struct + { + uint32_t numStages; /**< number of 2nd order stages in the filter. Overall order is 2*numStages. */ + float32_t *pState; /**< Points to the array of state coefficients. The array is of length 4*numStages. */ + float32_t *pCoeffs; /**< Points to the array of coefficients. The array is of length 5*numStages. */ + } arm_biquad_casd_df1_inst_f32; - /** + /** * @brief Processing function for the Q15 Biquad cascade filter. * @param[in] *S points to an instance of the Q15 Biquad cascade structure. * @param[in] *pSrc points to the block of input data. @@ -1306,13 +1274,13 @@ extern "C" * @return none. */ - void arm_biquad_cascade_df1_q15( - const arm_biquad_casd_df1_inst_q15 * S, - q15_t * pSrc, - q15_t * pDst, - uint32_t blockSize); + void arm_biquad_cascade_df1_q15( + const arm_biquad_casd_df1_inst_q15 *S, + q15_t *pSrc, + q15_t *pDst, + uint32_t blockSize); - /** + /** * @brief Initialization function for the Q15 Biquad cascade filter. * @param[in,out] *S points to an instance of the Q15 Biquad cascade structure. * @param[in] numStages number of 2nd order stages in the filter. @@ -1322,15 +1290,14 @@ extern "C" * @return none */ - void arm_biquad_cascade_df1_init_q15( - arm_biquad_casd_df1_inst_q15 * S, - uint8_t numStages, - q15_t * pCoeffs, - q15_t * pState, - int8_t postShift); + void arm_biquad_cascade_df1_init_q15( + arm_biquad_casd_df1_inst_q15 *S, + uint8_t numStages, + q15_t *pCoeffs, + q15_t *pState, + int8_t postShift); - - /** + /** * @brief Fast but less precise processing function for the Q15 Biquad cascade filter for Cortex-M3 and Cortex-M4. * @param[in] *S points to an instance of the Q15 Biquad cascade structure. * @param[in] *pSrc points to the block of input data. @@ -1339,14 +1306,13 @@ extern "C" * @return none. */ - void arm_biquad_cascade_df1_fast_q15( - const arm_biquad_casd_df1_inst_q15 * S, - q15_t * pSrc, - q15_t * pDst, - uint32_t blockSize); + void arm_biquad_cascade_df1_fast_q15( + const arm_biquad_casd_df1_inst_q15 *S, + q15_t *pSrc, + q15_t *pDst, + uint32_t blockSize); - - /** + /** * @brief Processing function for the Q31 Biquad cascade filter * @param[in] *S points to an instance of the Q31 Biquad cascade structure. * @param[in] *pSrc points to the block of input data. @@ -1355,13 +1321,13 @@ extern "C" * @return none. */ - void arm_biquad_cascade_df1_q31( - const arm_biquad_casd_df1_inst_q31 * S, - q31_t * pSrc, - q31_t * pDst, - uint32_t blockSize); + void arm_biquad_cascade_df1_q31( + const arm_biquad_casd_df1_inst_q31 *S, + q31_t *pSrc, + q31_t *pDst, + uint32_t blockSize); - /** + /** * @brief Fast but less precise processing function for the Q31 Biquad cascade filter for Cortex-M3 and Cortex-M4. * @param[in] *S points to an instance of the Q31 Biquad cascade structure. * @param[in] *pSrc points to the block of input data. @@ -1370,13 +1336,13 @@ extern "C" * @return none. */ - void arm_biquad_cascade_df1_fast_q31( - const arm_biquad_casd_df1_inst_q31 * S, - q31_t * pSrc, - q31_t * pDst, - uint32_t blockSize); + void arm_biquad_cascade_df1_fast_q31( + const arm_biquad_casd_df1_inst_q31 *S, + q31_t *pSrc, + q31_t *pDst, + uint32_t blockSize); - /** + /** * @brief Initialization function for the Q31 Biquad cascade filter. * @param[in,out] *S points to an instance of the Q31 Biquad cascade structure. * @param[in] numStages number of 2nd order stages in the filter. @@ -1386,14 +1352,14 @@ extern "C" * @return none */ - void arm_biquad_cascade_df1_init_q31( - arm_biquad_casd_df1_inst_q31 * S, - uint8_t numStages, - q31_t * pCoeffs, - q31_t * pState, - int8_t postShift); + void arm_biquad_cascade_df1_init_q31( + arm_biquad_casd_df1_inst_q31 *S, + uint8_t numStages, + q31_t *pCoeffs, + q31_t *pState, + int8_t postShift); - /** + /** * @brief Processing function for the floating-point Biquad cascade filter. * @param[in] *S points to an instance of the floating-point Biquad cascade structure. * @param[in] *pSrc points to the block of input data. @@ -1402,13 +1368,13 @@ extern "C" * @return none. */ - void arm_biquad_cascade_df1_f32( - const arm_biquad_casd_df1_inst_f32 * S, - float32_t * pSrc, - float32_t * pDst, - uint32_t blockSize); + void arm_biquad_cascade_df1_f32( + const arm_biquad_casd_df1_inst_f32 *S, + float32_t *pSrc, + float32_t *pDst, + uint32_t blockSize); - /** + /** * @brief Initialization function for the floating-point Biquad cascade filter. * @param[in,out] *S points to an instance of the floating-point Biquad cascade structure. * @param[in] numStages number of 2nd order stages in the filter. @@ -1417,63 +1383,59 @@ extern "C" * @return none */ - void arm_biquad_cascade_df1_init_f32( - arm_biquad_casd_df1_inst_f32 * S, - uint8_t numStages, - float32_t * pCoeffs, - float32_t * pState); - + void arm_biquad_cascade_df1_init_f32( + arm_biquad_casd_df1_inst_f32 *S, + uint8_t numStages, + float32_t *pCoeffs, + float32_t *pState); - /** + /** * @brief Instance structure for the floating-point matrix structure. */ - typedef struct - { - uint16_t numRows; /**< number of rows of the matrix. */ - uint16_t numCols; /**< number of columns of the matrix. */ - float32_t *pData; /**< points to the data of the matrix. */ - } arm_matrix_instance_f32; - + typedef struct + { + uint16_t numRows; /**< number of rows of the matrix. */ + uint16_t numCols; /**< number of columns of the matrix. */ + float32_t *pData; /**< points to the data of the matrix. */ + } arm_matrix_instance_f32; - /** + /** * @brief Instance structure for the floating-point matrix structure. */ - typedef struct - { - uint16_t numRows; /**< number of rows of the matrix. */ - uint16_t numCols; /**< number of columns of the matrix. */ - float64_t *pData; /**< points to the data of the matrix. */ - } arm_matrix_instance_f64; + typedef struct + { + uint16_t numRows; /**< number of rows of the matrix. */ + uint16_t numCols; /**< number of columns of the matrix. */ + float64_t *pData; /**< points to the data of the matrix. */ + } arm_matrix_instance_f64; - /** + /** * @brief Instance structure for the Q15 matrix structure. */ - typedef struct - { - uint16_t numRows; /**< number of rows of the matrix. */ - uint16_t numCols; /**< number of columns of the matrix. */ - q15_t *pData; /**< points to the data of the matrix. */ + typedef struct + { + uint16_t numRows; /**< number of rows of the matrix. */ + uint16_t numCols; /**< number of columns of the matrix. */ + q15_t *pData; /**< points to the data of the matrix. */ - } arm_matrix_instance_q15; + } arm_matrix_instance_q15; - /** + /** * @brief Instance structure for the Q31 matrix structure. */ - typedef struct - { - uint16_t numRows; /**< number of rows of the matrix. */ - uint16_t numCols; /**< number of columns of the matrix. */ - q31_t *pData; /**< points to the data of the matrix. */ - - } arm_matrix_instance_q31; - + typedef struct + { + uint16_t numRows; /**< number of rows of the matrix. */ + uint16_t numCols; /**< number of columns of the matrix. */ + q31_t *pData; /**< points to the data of the matrix. */ + } arm_matrix_instance_q31; - /** + /** * @brief Floating-point matrix addition. * @param[in] *pSrcA points to the first input matrix structure * @param[in] *pSrcB points to the second input matrix structure @@ -1482,12 +1444,12 @@ extern "C" * <code>ARM_MATH_SIZE_MISMATCH</code> or <code>ARM_MATH_SUCCESS</code> based on the outcome of size checking. */ - arm_status arm_mat_add_f32( - const arm_matrix_instance_f32 * pSrcA, - const arm_matrix_instance_f32 * pSrcB, - arm_matrix_instance_f32 * pDst); + arm_status arm_mat_add_f32( + const arm_matrix_instance_f32 *pSrcA, + const arm_matrix_instance_f32 *pSrcB, + arm_matrix_instance_f32 *pDst); - /** + /** * @brief Q15 matrix addition. * @param[in] *pSrcA points to the first input matrix structure * @param[in] *pSrcB points to the second input matrix structure @@ -1496,12 +1458,12 @@ extern "C" * <code>ARM_MATH_SIZE_MISMATCH</code> or <code>ARM_MATH_SUCCESS</code> based on the outcome of size checking. */ - arm_status arm_mat_add_q15( - const arm_matrix_instance_q15 * pSrcA, - const arm_matrix_instance_q15 * pSrcB, - arm_matrix_instance_q15 * pDst); + arm_status arm_mat_add_q15( + const arm_matrix_instance_q15 *pSrcA, + const arm_matrix_instance_q15 *pSrcB, + arm_matrix_instance_q15 *pDst); - /** + /** * @brief Q31 matrix addition. * @param[in] *pSrcA points to the first input matrix structure * @param[in] *pSrcB points to the second input matrix structure @@ -1510,12 +1472,12 @@ extern "C" * <code>ARM_MATH_SIZE_MISMATCH</code> or <code>ARM_MATH_SUCCESS</code> based on the outcome of size checking. */ - arm_status arm_mat_add_q31( - const arm_matrix_instance_q31 * pSrcA, - const arm_matrix_instance_q31 * pSrcB, - arm_matrix_instance_q31 * pDst); + arm_status arm_mat_add_q31( + const arm_matrix_instance_q31 *pSrcA, + const arm_matrix_instance_q31 *pSrcB, + arm_matrix_instance_q31 *pDst); - /** + /** * @brief Floating-point, complex, matrix multiplication. * @param[in] *pSrcA points to the first input matrix structure * @param[in] *pSrcB points to the second input matrix structure @@ -1524,12 +1486,12 @@ extern "C" * <code>ARM_MATH_SIZE_MISMATCH</code> or <code>ARM_MATH_SUCCESS</code> based on the outcome of size checking. */ - arm_status arm_mat_cmplx_mult_f32( - const arm_matrix_instance_f32 * pSrcA, - const arm_matrix_instance_f32 * pSrcB, - arm_matrix_instance_f32 * pDst); + arm_status arm_mat_cmplx_mult_f32( + const arm_matrix_instance_f32 *pSrcA, + const arm_matrix_instance_f32 *pSrcB, + arm_matrix_instance_f32 *pDst); - /** + /** * @brief Q15, complex, matrix multiplication. * @param[in] *pSrcA points to the first input matrix structure * @param[in] *pSrcB points to the second input matrix structure @@ -1538,13 +1500,13 @@ extern "C" * <code>ARM_MATH_SIZE_MISMATCH</code> or <code>ARM_MATH_SUCCESS</code> based on the outcome of size checking. */ - arm_status arm_mat_cmplx_mult_q15( - const arm_matrix_instance_q15 * pSrcA, - const arm_matrix_instance_q15 * pSrcB, - arm_matrix_instance_q15 * pDst, - q15_t * pScratch); + arm_status arm_mat_cmplx_mult_q15( + const arm_matrix_instance_q15 *pSrcA, + const arm_matrix_instance_q15 *pSrcB, + arm_matrix_instance_q15 *pDst, + q15_t *pScratch); - /** + /** * @brief Q31, complex, matrix multiplication. * @param[in] *pSrcA points to the first input matrix structure * @param[in] *pSrcB points to the second input matrix structure @@ -1553,51 +1515,48 @@ extern "C" * <code>ARM_MATH_SIZE_MISMATCH</code> or <code>ARM_MATH_SUCCESS</code> based on the outcome of size checking. */ - arm_status arm_mat_cmplx_mult_q31( - const arm_matrix_instance_q31 * pSrcA, - const arm_matrix_instance_q31 * pSrcB, - arm_matrix_instance_q31 * pDst); + arm_status arm_mat_cmplx_mult_q31( + const arm_matrix_instance_q31 *pSrcA, + const arm_matrix_instance_q31 *pSrcB, + arm_matrix_instance_q31 *pDst); - - /** + /** * @brief Floating-point matrix transpose. * @param[in] *pSrc points to the input matrix * @param[out] *pDst points to the output matrix - * @return The function returns either <code>ARM_MATH_SIZE_MISMATCH</code> + * @return The function returns either <code>ARM_MATH_SIZE_MISMATCH</code> * or <code>ARM_MATH_SUCCESS</code> based on the outcome of size checking. */ - arm_status arm_mat_trans_f32( - const arm_matrix_instance_f32 * pSrc, - arm_matrix_instance_f32 * pDst); + arm_status arm_mat_trans_f32( + const arm_matrix_instance_f32 *pSrc, + arm_matrix_instance_f32 *pDst); - - /** + /** * @brief Q15 matrix transpose. * @param[in] *pSrc points to the input matrix * @param[out] *pDst points to the output matrix - * @return The function returns either <code>ARM_MATH_SIZE_MISMATCH</code> + * @return The function returns either <code>ARM_MATH_SIZE_MISMATCH</code> * or <code>ARM_MATH_SUCCESS</code> based on the outcome of size checking. */ - arm_status arm_mat_trans_q15( - const arm_matrix_instance_q15 * pSrc, - arm_matrix_instance_q15 * pDst); + arm_status arm_mat_trans_q15( + const arm_matrix_instance_q15 *pSrc, + arm_matrix_instance_q15 *pDst); - /** + /** * @brief Q31 matrix transpose. * @param[in] *pSrc points to the input matrix * @param[out] *pDst points to the output matrix - * @return The function returns either <code>ARM_MATH_SIZE_MISMATCH</code> + * @return The function returns either <code>ARM_MATH_SIZE_MISMATCH</code> * or <code>ARM_MATH_SUCCESS</code> based on the outcome of size checking. */ - arm_status arm_mat_trans_q31( - const arm_matrix_instance_q31 * pSrc, - arm_matrix_instance_q31 * pDst); - + arm_status arm_mat_trans_q31( + const arm_matrix_instance_q31 *pSrc, + arm_matrix_instance_q31 *pDst); - /** + /** * @brief Floating-point matrix multiplication * @param[in] *pSrcA points to the first input matrix structure * @param[in] *pSrcB points to the second input matrix structure @@ -1606,44 +1565,44 @@ extern "C" * <code>ARM_MATH_SIZE_MISMATCH</code> or <code>ARM_MATH_SUCCESS</code> based on the outcome of size checking. */ - arm_status arm_mat_mult_f32( - const arm_matrix_instance_f32 * pSrcA, - const arm_matrix_instance_f32 * pSrcB, - arm_matrix_instance_f32 * pDst); + arm_status arm_mat_mult_f32( + const arm_matrix_instance_f32 *pSrcA, + const arm_matrix_instance_f32 *pSrcB, + arm_matrix_instance_f32 *pDst); - /** + /** * @brief Q15 matrix multiplication * @param[in] *pSrcA points to the first input matrix structure * @param[in] *pSrcB points to the second input matrix structure * @param[out] *pDst points to output matrix structure - * @param[in] *pState points to the array for storing intermediate results + * @param[in] *pState points to the array for storing intermediate results * @return The function returns either * <code>ARM_MATH_SIZE_MISMATCH</code> or <code>ARM_MATH_SUCCESS</code> based on the outcome of size checking. */ - arm_status arm_mat_mult_q15( - const arm_matrix_instance_q15 * pSrcA, - const arm_matrix_instance_q15 * pSrcB, - arm_matrix_instance_q15 * pDst, - q15_t * pState); + arm_status arm_mat_mult_q15( + const arm_matrix_instance_q15 *pSrcA, + const arm_matrix_instance_q15 *pSrcB, + arm_matrix_instance_q15 *pDst, + q15_t *pState); - /** + /** * @brief Q15 matrix multiplication (fast variant) for Cortex-M3 and Cortex-M4 * @param[in] *pSrcA points to the first input matrix structure * @param[in] *pSrcB points to the second input matrix structure * @param[out] *pDst points to output matrix structure - * @param[in] *pState points to the array for storing intermediate results + * @param[in] *pState points to the array for storing intermediate results * @return The function returns either * <code>ARM_MATH_SIZE_MISMATCH</code> or <code>ARM_MATH_SUCCESS</code> based on the outcome of size checking. */ - arm_status arm_mat_mult_fast_q15( - const arm_matrix_instance_q15 * pSrcA, - const arm_matrix_instance_q15 * pSrcB, - arm_matrix_instance_q15 * pDst, - q15_t * pState); + arm_status arm_mat_mult_fast_q15( + const arm_matrix_instance_q15 *pSrcA, + const arm_matrix_instance_q15 *pSrcB, + arm_matrix_instance_q15 *pDst, + q15_t *pState); - /** + /** * @brief Q31 matrix multiplication * @param[in] *pSrcA points to the first input matrix structure * @param[in] *pSrcB points to the second input matrix structure @@ -1652,12 +1611,12 @@ extern "C" * <code>ARM_MATH_SIZE_MISMATCH</code> or <code>ARM_MATH_SUCCESS</code> based on the outcome of size checking. */ - arm_status arm_mat_mult_q31( - const arm_matrix_instance_q31 * pSrcA, - const arm_matrix_instance_q31 * pSrcB, - arm_matrix_instance_q31 * pDst); + arm_status arm_mat_mult_q31( + const arm_matrix_instance_q31 *pSrcA, + const arm_matrix_instance_q31 *pSrcB, + arm_matrix_instance_q31 *pDst); - /** + /** * @brief Q31 matrix multiplication (fast variant) for Cortex-M3 and Cortex-M4 * @param[in] *pSrcA points to the first input matrix structure * @param[in] *pSrcB points to the second input matrix structure @@ -1666,13 +1625,12 @@ extern "C" * <code>ARM_MATH_SIZE_MISMATCH</code> or <code>ARM_MATH_SUCCESS</code> based on the outcome of size checking. */ - arm_status arm_mat_mult_fast_q31( - const arm_matrix_instance_q31 * pSrcA, - const arm_matrix_instance_q31 * pSrcB, - arm_matrix_instance_q31 * pDst); - + arm_status arm_mat_mult_fast_q31( + const arm_matrix_instance_q31 *pSrcA, + const arm_matrix_instance_q31 *pSrcB, + arm_matrix_instance_q31 *pDst); - /** + /** * @brief Floating-point matrix subtraction * @param[in] *pSrcA points to the first input matrix structure * @param[in] *pSrcB points to the second input matrix structure @@ -1681,12 +1639,12 @@ extern "C" * <code>ARM_MATH_SIZE_MISMATCH</code> or <code>ARM_MATH_SUCCESS</code> based on the outcome of size checking. */ - arm_status arm_mat_sub_f32( - const arm_matrix_instance_f32 * pSrcA, - const arm_matrix_instance_f32 * pSrcB, - arm_matrix_instance_f32 * pDst); + arm_status arm_mat_sub_f32( + const arm_matrix_instance_f32 *pSrcA, + const arm_matrix_instance_f32 *pSrcB, + arm_matrix_instance_f32 *pDst); - /** + /** * @brief Q15 matrix subtraction * @param[in] *pSrcA points to the first input matrix structure * @param[in] *pSrcB points to the second input matrix structure @@ -1695,12 +1653,12 @@ extern "C" * <code>ARM_MATH_SIZE_MISMATCH</code> or <code>ARM_MATH_SUCCESS</code> based on the outcome of size checking. */ - arm_status arm_mat_sub_q15( - const arm_matrix_instance_q15 * pSrcA, - const arm_matrix_instance_q15 * pSrcB, - arm_matrix_instance_q15 * pDst); + arm_status arm_mat_sub_q15( + const arm_matrix_instance_q15 *pSrcA, + const arm_matrix_instance_q15 *pSrcB, + arm_matrix_instance_q15 *pDst); - /** + /** * @brief Q31 matrix subtraction * @param[in] *pSrcA points to the first input matrix structure * @param[in] *pSrcB points to the second input matrix structure @@ -1709,12 +1667,12 @@ extern "C" * <code>ARM_MATH_SIZE_MISMATCH</code> or <code>ARM_MATH_SUCCESS</code> based on the outcome of size checking. */ - arm_status arm_mat_sub_q31( - const arm_matrix_instance_q31 * pSrcA, - const arm_matrix_instance_q31 * pSrcB, - arm_matrix_instance_q31 * pDst); + arm_status arm_mat_sub_q31( + const arm_matrix_instance_q31 *pSrcA, + const arm_matrix_instance_q31 *pSrcB, + arm_matrix_instance_q31 *pDst); - /** + /** * @brief Floating-point matrix scaling. * @param[in] *pSrc points to the input matrix * @param[in] scale scale factor @@ -1723,12 +1681,12 @@ extern "C" * <code>ARM_MATH_SIZE_MISMATCH</code> or <code>ARM_MATH_SUCCESS</code> based on the outcome of size checking. */ - arm_status arm_mat_scale_f32( - const arm_matrix_instance_f32 * pSrc, - float32_t scale, - arm_matrix_instance_f32 * pDst); + arm_status arm_mat_scale_f32( + const arm_matrix_instance_f32 *pSrc, + float32_t scale, + arm_matrix_instance_f32 *pDst); - /** + /** * @brief Q15 matrix scaling. * @param[in] *pSrc points to input matrix * @param[in] scaleFract fractional portion of the scale factor @@ -1738,13 +1696,13 @@ extern "C" * <code>ARM_MATH_SIZE_MISMATCH</code> or <code>ARM_MATH_SUCCESS</code> based on the outcome of size checking. */ - arm_status arm_mat_scale_q15( - const arm_matrix_instance_q15 * pSrc, - q15_t scaleFract, - int32_t shift, - arm_matrix_instance_q15 * pDst); + arm_status arm_mat_scale_q15( + const arm_matrix_instance_q15 *pSrc, + q15_t scaleFract, + int32_t shift, + arm_matrix_instance_q15 *pDst); - /** + /** * @brief Q31 matrix scaling. * @param[in] *pSrc points to input matrix * @param[in] scaleFract fractional portion of the scale factor @@ -1754,224 +1712,215 @@ extern "C" * <code>ARM_MATH_SIZE_MISMATCH</code> or <code>ARM_MATH_SUCCESS</code> based on the outcome of size checking. */ - arm_status arm_mat_scale_q31( - const arm_matrix_instance_q31 * pSrc, - q31_t scaleFract, - int32_t shift, - arm_matrix_instance_q31 * pDst); - + arm_status arm_mat_scale_q31( + const arm_matrix_instance_q31 *pSrc, + q31_t scaleFract, + int32_t shift, + arm_matrix_instance_q31 *pDst); - /** + /** * @brief Q31 matrix initialization. * @param[in,out] *S points to an instance of the floating-point matrix structure. * @param[in] nRows number of rows in the matrix. * @param[in] nColumns number of columns in the matrix. - * @param[in] *pData points to the matrix data array. + * @param[in] *pData points to the matrix data array. * @return none */ - void arm_mat_init_q31( - arm_matrix_instance_q31 * S, - uint16_t nRows, - uint16_t nColumns, - q31_t * pData); + void arm_mat_init_q31( + arm_matrix_instance_q31 *S, + uint16_t nRows, + uint16_t nColumns, + q31_t *pData); - /** + /** * @brief Q15 matrix initialization. * @param[in,out] *S points to an instance of the floating-point matrix structure. * @param[in] nRows number of rows in the matrix. * @param[in] nColumns number of columns in the matrix. - * @param[in] *pData points to the matrix data array. + * @param[in] *pData points to the matrix data array. * @return none */ - void arm_mat_init_q15( - arm_matrix_instance_q15 * S, - uint16_t nRows, - uint16_t nColumns, - q15_t * pData); + void arm_mat_init_q15( + arm_matrix_instance_q15 *S, + uint16_t nRows, + uint16_t nColumns, + q15_t *pData); - /** + /** * @brief Floating-point matrix initialization. * @param[in,out] *S points to an instance of the floating-point matrix structure. * @param[in] nRows number of rows in the matrix. * @param[in] nColumns number of columns in the matrix. - * @param[in] *pData points to the matrix data array. + * @param[in] *pData points to the matrix data array. * @return none */ - void arm_mat_init_f32( - arm_matrix_instance_f32 * S, - uint16_t nRows, - uint16_t nColumns, - float32_t * pData); - + void arm_mat_init_f32( + arm_matrix_instance_f32 *S, + uint16_t nRows, + uint16_t nColumns, + float32_t *pData); - - /** + /** * @brief Instance structure for the Q15 PID Control. */ - typedef struct - { - q15_t A0; /**< The derived gain, A0 = Kp + Ki + Kd . */ + typedef struct + { + q15_t A0; /**< The derived gain, A0 = Kp + Ki + Kd . */ #ifdef ARM_MATH_CM0_FAMILY - q15_t A1; - q15_t A2; + q15_t A1; + q15_t A2; #else - q31_t A1; /**< The derived gain A1 = -Kp - 2Kd | Kd.*/ + q31_t A1; /**< The derived gain A1 = -Kp - 2Kd | Kd.*/ #endif - q15_t state[3]; /**< The state array of length 3. */ - q15_t Kp; /**< The proportional gain. */ - q15_t Ki; /**< The integral gain. */ - q15_t Kd; /**< The derivative gain. */ - } arm_pid_instance_q15; + q15_t state[3]; /**< The state array of length 3. */ + q15_t Kp; /**< The proportional gain. */ + q15_t Ki; /**< The integral gain. */ + q15_t Kd; /**< The derivative gain. */ + } arm_pid_instance_q15; - /** + /** * @brief Instance structure for the Q31 PID Control. */ - typedef struct - { - q31_t A0; /**< The derived gain, A0 = Kp + Ki + Kd . */ - q31_t A1; /**< The derived gain, A1 = -Kp - 2Kd. */ - q31_t A2; /**< The derived gain, A2 = Kd . */ - q31_t state[3]; /**< The state array of length 3. */ - q31_t Kp; /**< The proportional gain. */ - q31_t Ki; /**< The integral gain. */ - q31_t Kd; /**< The derivative gain. */ + typedef struct + { + q31_t A0; /**< The derived gain, A0 = Kp + Ki + Kd . */ + q31_t A1; /**< The derived gain, A1 = -Kp - 2Kd. */ + q31_t A2; /**< The derived gain, A2 = Kd . */ + q31_t state[3]; /**< The state array of length 3. */ + q31_t Kp; /**< The proportional gain. */ + q31_t Ki; /**< The integral gain. */ + q31_t Kd; /**< The derivative gain. */ - } arm_pid_instance_q31; + } arm_pid_instance_q31; - /** + /** * @brief Instance structure for the floating-point PID Control. */ - typedef struct - { - float32_t A0; /**< The derived gain, A0 = Kp + Ki + Kd . */ - float32_t A1; /**< The derived gain, A1 = -Kp - 2Kd. */ - float32_t A2; /**< The derived gain, A2 = Kd . */ - float32_t state[3]; /**< The state array of length 3. */ - float32_t Kp; /**< The proportional gain. */ - float32_t Ki; /**< The integral gain. */ - float32_t Kd; /**< The derivative gain. */ - } arm_pid_instance_f32; - - + typedef struct + { + float32_t A0; /**< The derived gain, A0 = Kp + Ki + Kd . */ + float32_t A1; /**< The derived gain, A1 = -Kp - 2Kd. */ + float32_t A2; /**< The derived gain, A2 = Kd . */ + float32_t state[3]; /**< The state array of length 3. */ + float32_t Kp; /**< The proportional gain. */ + float32_t Ki; /**< The integral gain. */ + float32_t Kd; /**< The derivative gain. */ + } arm_pid_instance_f32; - /** + /** * @brief Initialization function for the floating-point PID Control. * @param[in,out] *S points to an instance of the PID structure. * @param[in] resetStateFlag flag to reset the state. 0 = no change in state 1 = reset the state. * @return none. */ - void arm_pid_init_f32( - arm_pid_instance_f32 * S, - int32_t resetStateFlag); + void arm_pid_init_f32( + arm_pid_instance_f32 *S, + int32_t resetStateFlag); - /** + /** * @brief Reset function for the floating-point PID Control. * @param[in,out] *S is an instance of the floating-point PID Control structure * @return none */ - void arm_pid_reset_f32( - arm_pid_instance_f32 * S); - + void arm_pid_reset_f32( + arm_pid_instance_f32 *S); - /** + /** * @brief Initialization function for the Q31 PID Control. * @param[in,out] *S points to an instance of the Q15 PID structure. * @param[in] resetStateFlag flag to reset the state. 0 = no change in state 1 = reset the state. * @return none. */ - void arm_pid_init_q31( - arm_pid_instance_q31 * S, - int32_t resetStateFlag); - + void arm_pid_init_q31( + arm_pid_instance_q31 *S, + int32_t resetStateFlag); - /** + /** * @brief Reset function for the Q31 PID Control. * @param[in,out] *S points to an instance of the Q31 PID Control structure * @return none */ - void arm_pid_reset_q31( - arm_pid_instance_q31 * S); + void arm_pid_reset_q31( + arm_pid_instance_q31 *S); - /** + /** * @brief Initialization function for the Q15 PID Control. * @param[in,out] *S points to an instance of the Q15 PID structure. * @param[in] resetStateFlag flag to reset the state. 0 = no change in state 1 = reset the state. * @return none. */ - void arm_pid_init_q15( - arm_pid_instance_q15 * S, - int32_t resetStateFlag); + void arm_pid_init_q15( + arm_pid_instance_q15 *S, + int32_t resetStateFlag); - /** + /** * @brief Reset function for the Q15 PID Control. * @param[in,out] *S points to an instance of the q15 PID Control structure * @return none */ - void arm_pid_reset_q15( - arm_pid_instance_q15 * S); + void arm_pid_reset_q15( + arm_pid_instance_q15 *S); - - /** + /** * @brief Instance structure for the floating-point Linear Interpolate function. */ - typedef struct - { - uint32_t nValues; /**< nValues */ - float32_t x1; /**< x1 */ - float32_t xSpacing; /**< xSpacing */ - float32_t *pYData; /**< pointer to the table of Y values */ - } arm_linear_interp_instance_f32; + typedef struct + { + uint32_t nValues; /**< nValues */ + float32_t x1; /**< x1 */ + float32_t xSpacing; /**< xSpacing */ + float32_t *pYData; /**< pointer to the table of Y values */ + } arm_linear_interp_instance_f32; - /** + /** * @brief Instance structure for the floating-point bilinear interpolation function. */ - typedef struct - { - uint16_t numRows; /**< number of rows in the data table. */ - uint16_t numCols; /**< number of columns in the data table. */ - float32_t *pData; /**< points to the data table. */ - } arm_bilinear_interp_instance_f32; + typedef struct + { + uint16_t numRows; /**< number of rows in the data table. */ + uint16_t numCols; /**< number of columns in the data table. */ + float32_t *pData; /**< points to the data table. */ + } arm_bilinear_interp_instance_f32; - /** + /** * @brief Instance structure for the Q31 bilinear interpolation function. */ - typedef struct - { - uint16_t numRows; /**< number of rows in the data table. */ - uint16_t numCols; /**< number of columns in the data table. */ - q31_t *pData; /**< points to the data table. */ - } arm_bilinear_interp_instance_q31; + typedef struct + { + uint16_t numRows; /**< number of rows in the data table. */ + uint16_t numCols; /**< number of columns in the data table. */ + q31_t *pData; /**< points to the data table. */ + } arm_bilinear_interp_instance_q31; - /** + /** * @brief Instance structure for the Q15 bilinear interpolation function. */ - typedef struct - { - uint16_t numRows; /**< number of rows in the data table. */ - uint16_t numCols; /**< number of columns in the data table. */ - q15_t *pData; /**< points to the data table. */ - } arm_bilinear_interp_instance_q15; + typedef struct + { + uint16_t numRows; /**< number of rows in the data table. */ + uint16_t numCols; /**< number of columns in the data table. */ + q15_t *pData; /**< points to the data table. */ + } arm_bilinear_interp_instance_q15; - /** + /** * @brief Instance structure for the Q15 bilinear interpolation function. */ - typedef struct - { - uint16_t numRows; /**< number of rows in the data table. */ - uint16_t numCols; /**< number of columns in the data table. */ - q7_t *pData; /**< points to the data table. */ - } arm_bilinear_interp_instance_q7; - + typedef struct + { + uint16_t numRows; /**< number of rows in the data table. */ + uint16_t numCols; /**< number of columns in the data table. */ + q7_t *pData; /**< points to the data table. */ + } arm_bilinear_interp_instance_q7; - /** + /** * @brief Q7 vector multiplication. * @param[in] *pSrcA points to the first input vector * @param[in] *pSrcB points to the second input vector @@ -1980,13 +1929,13 @@ extern "C" * @return none. */ - void arm_mult_q7( - q7_t * pSrcA, - q7_t * pSrcB, - q7_t * pDst, - uint32_t blockSize); + void arm_mult_q7( + q7_t *pSrcA, + q7_t *pSrcB, + q7_t *pDst, + uint32_t blockSize); - /** + /** * @brief Q15 vector multiplication. * @param[in] *pSrcA points to the first input vector * @param[in] *pSrcB points to the second input vector @@ -1995,13 +1944,13 @@ extern "C" * @return none. */ - void arm_mult_q15( - q15_t * pSrcA, - q15_t * pSrcB, - q15_t * pDst, - uint32_t blockSize); + void arm_mult_q15( + q15_t *pSrcA, + q15_t *pSrcB, + q15_t *pDst, + uint32_t blockSize); - /** + /** * @brief Q31 vector multiplication. * @param[in] *pSrcA points to the first input vector * @param[in] *pSrcB points to the second input vector @@ -2010,13 +1959,13 @@ extern "C" * @return none. */ - void arm_mult_q31( - q31_t * pSrcA, - q31_t * pSrcB, - q31_t * pDst, - uint32_t blockSize); + void arm_mult_q31( + q31_t *pSrcA, + q31_t *pSrcB, + q31_t *pDst, + uint32_t blockSize); - /** + /** * @brief Floating-point vector multiplication. * @param[in] *pSrcA points to the first input vector * @param[in] *pSrcB points to the second input vector @@ -2025,353 +1974,346 @@ extern "C" * @return none. */ - void arm_mult_f32( - float32_t * pSrcA, - float32_t * pSrcB, - float32_t * pDst, - uint32_t blockSize); - - - - + void arm_mult_f32( + float32_t *pSrcA, + float32_t *pSrcB, + float32_t *pDst, + uint32_t blockSize); - - /** + /** * @brief Instance structure for the Q15 CFFT/CIFFT function. */ - typedef struct - { - uint16_t fftLen; /**< length of the FFT. */ - uint8_t ifftFlag; /**< flag that selects forward (ifftFlag=0) or inverse (ifftFlag=1) transform. */ - uint8_t bitReverseFlag; /**< flag that enables (bitReverseFlag=1) or disables (bitReverseFlag=0) bit reversal of output. */ - q15_t *pTwiddle; /**< points to the Sin twiddle factor table. */ - uint16_t *pBitRevTable; /**< points to the bit reversal table. */ - uint16_t twidCoefModifier; /**< twiddle coefficient modifier that supports different size FFTs with the same twiddle factor table. */ - uint16_t bitRevFactor; /**< bit reversal modifier that supports different size FFTs with the same bit reversal table. */ - } arm_cfft_radix2_instance_q15; - -/* Deprecated */ - arm_status arm_cfft_radix2_init_q15( - arm_cfft_radix2_instance_q15 * S, - uint16_t fftLen, - uint8_t ifftFlag, - uint8_t bitReverseFlag); - -/* Deprecated */ - void arm_cfft_radix2_q15( - const arm_cfft_radix2_instance_q15 * S, - q15_t * pSrc); + typedef struct + { + uint16_t fftLen; /**< length of the FFT. */ + uint8_t ifftFlag; /**< flag that selects forward (ifftFlag=0) or inverse (ifftFlag=1) transform. */ + uint8_t bitReverseFlag; /**< flag that enables (bitReverseFlag=1) or disables (bitReverseFlag=0) bit reversal of output. */ + q15_t *pTwiddle; /**< points to the Sin twiddle factor table. */ + uint16_t *pBitRevTable; /**< points to the bit reversal table. */ + uint16_t twidCoefModifier; /**< twiddle coefficient modifier that supports different size FFTs with the same twiddle factor table. */ + uint16_t bitRevFactor; /**< bit reversal modifier that supports different size FFTs with the same bit reversal table. */ + } arm_cfft_radix2_instance_q15; + /* Deprecated */ + arm_status arm_cfft_radix2_init_q15( + arm_cfft_radix2_instance_q15 *S, + uint16_t fftLen, + uint8_t ifftFlag, + uint8_t bitReverseFlag); + /* Deprecated */ + void arm_cfft_radix2_q15( + const arm_cfft_radix2_instance_q15 *S, + q15_t *pSrc); - /** + /** * @brief Instance structure for the Q15 CFFT/CIFFT function. */ - typedef struct - { - uint16_t fftLen; /**< length of the FFT. */ - uint8_t ifftFlag; /**< flag that selects forward (ifftFlag=0) or inverse (ifftFlag=1) transform. */ - uint8_t bitReverseFlag; /**< flag that enables (bitReverseFlag=1) or disables (bitReverseFlag=0) bit reversal of output. */ - q15_t *pTwiddle; /**< points to the twiddle factor table. */ - uint16_t *pBitRevTable; /**< points to the bit reversal table. */ - uint16_t twidCoefModifier; /**< twiddle coefficient modifier that supports different size FFTs with the same twiddle factor table. */ - uint16_t bitRevFactor; /**< bit reversal modifier that supports different size FFTs with the same bit reversal table. */ - } arm_cfft_radix4_instance_q15; + typedef struct + { + uint16_t fftLen; /**< length of the FFT. */ + uint8_t ifftFlag; /**< flag that selects forward (ifftFlag=0) or inverse (ifftFlag=1) transform. */ + uint8_t bitReverseFlag; /**< flag that enables (bitReverseFlag=1) or disables (bitReverseFlag=0) bit reversal of output. */ + q15_t *pTwiddle; /**< points to the twiddle factor table. */ + uint16_t *pBitRevTable; /**< points to the bit reversal table. */ + uint16_t twidCoefModifier; /**< twiddle coefficient modifier that supports different size FFTs with the same twiddle factor table. */ + uint16_t bitRevFactor; /**< bit reversal modifier that supports different size FFTs with the same bit reversal table. */ + } arm_cfft_radix4_instance_q15; -/* Deprecated */ - arm_status arm_cfft_radix4_init_q15( - arm_cfft_radix4_instance_q15 * S, - uint16_t fftLen, - uint8_t ifftFlag, - uint8_t bitReverseFlag); + /* Deprecated */ + arm_status arm_cfft_radix4_init_q15( + arm_cfft_radix4_instance_q15 *S, + uint16_t fftLen, + uint8_t ifftFlag, + uint8_t bitReverseFlag); -/* Deprecated */ - void arm_cfft_radix4_q15( - const arm_cfft_radix4_instance_q15 * S, - q15_t * pSrc); + /* Deprecated */ + void arm_cfft_radix4_q15( + const arm_cfft_radix4_instance_q15 *S, + q15_t *pSrc); - /** + /** * @brief Instance structure for the Radix-2 Q31 CFFT/CIFFT function. */ - typedef struct - { - uint16_t fftLen; /**< length of the FFT. */ - uint8_t ifftFlag; /**< flag that selects forward (ifftFlag=0) or inverse (ifftFlag=1) transform. */ - uint8_t bitReverseFlag; /**< flag that enables (bitReverseFlag=1) or disables (bitReverseFlag=0) bit reversal of output. */ - q31_t *pTwiddle; /**< points to the Twiddle factor table. */ - uint16_t *pBitRevTable; /**< points to the bit reversal table. */ - uint16_t twidCoefModifier; /**< twiddle coefficient modifier that supports different size FFTs with the same twiddle factor table. */ - uint16_t bitRevFactor; /**< bit reversal modifier that supports different size FFTs with the same bit reversal table. */ - } arm_cfft_radix2_instance_q31; + typedef struct + { + uint16_t fftLen; /**< length of the FFT. */ + uint8_t ifftFlag; /**< flag that selects forward (ifftFlag=0) or inverse (ifftFlag=1) transform. */ + uint8_t bitReverseFlag; /**< flag that enables (bitReverseFlag=1) or disables (bitReverseFlag=0) bit reversal of output. */ + q31_t *pTwiddle; /**< points to the Twiddle factor table. */ + uint16_t *pBitRevTable; /**< points to the bit reversal table. */ + uint16_t twidCoefModifier; /**< twiddle coefficient modifier that supports different size FFTs with the same twiddle factor table. */ + uint16_t bitRevFactor; /**< bit reversal modifier that supports different size FFTs with the same bit reversal table. */ + } arm_cfft_radix2_instance_q31; -/* Deprecated */ - arm_status arm_cfft_radix2_init_q31( - arm_cfft_radix2_instance_q31 * S, - uint16_t fftLen, - uint8_t ifftFlag, - uint8_t bitReverseFlag); + /* Deprecated */ + arm_status arm_cfft_radix2_init_q31( + arm_cfft_radix2_instance_q31 *S, + uint16_t fftLen, + uint8_t ifftFlag, + uint8_t bitReverseFlag); -/* Deprecated */ - void arm_cfft_radix2_q31( - const arm_cfft_radix2_instance_q31 * S, - q31_t * pSrc); + /* Deprecated */ + void arm_cfft_radix2_q31( + const arm_cfft_radix2_instance_q31 *S, + q31_t *pSrc); - /** + /** * @brief Instance structure for the Q31 CFFT/CIFFT function. */ - typedef struct - { - uint16_t fftLen; /**< length of the FFT. */ - uint8_t ifftFlag; /**< flag that selects forward (ifftFlag=0) or inverse (ifftFlag=1) transform. */ - uint8_t bitReverseFlag; /**< flag that enables (bitReverseFlag=1) or disables (bitReverseFlag=0) bit reversal of output. */ - q31_t *pTwiddle; /**< points to the twiddle factor table. */ - uint16_t *pBitRevTable; /**< points to the bit reversal table. */ - uint16_t twidCoefModifier; /**< twiddle coefficient modifier that supports different size FFTs with the same twiddle factor table. */ - uint16_t bitRevFactor; /**< bit reversal modifier that supports different size FFTs with the same bit reversal table. */ - } arm_cfft_radix4_instance_q31; + typedef struct + { + uint16_t fftLen; /**< length of the FFT. */ + uint8_t ifftFlag; /**< flag that selects forward (ifftFlag=0) or inverse (ifftFlag=1) transform. */ + uint8_t bitReverseFlag; /**< flag that enables (bitReverseFlag=1) or disables (bitReverseFlag=0) bit reversal of output. */ + q31_t *pTwiddle; /**< points to the twiddle factor table. */ + uint16_t *pBitRevTable; /**< points to the bit reversal table. */ + uint16_t twidCoefModifier; /**< twiddle coefficient modifier that supports different size FFTs with the same twiddle factor table. */ + uint16_t bitRevFactor; /**< bit reversal modifier that supports different size FFTs with the same bit reversal table. */ + } arm_cfft_radix4_instance_q31; -/* Deprecated */ - void arm_cfft_radix4_q31( - const arm_cfft_radix4_instance_q31 * S, - q31_t * pSrc); + /* Deprecated */ + void arm_cfft_radix4_q31( + const arm_cfft_radix4_instance_q31 *S, + q31_t *pSrc); -/* Deprecated */ - arm_status arm_cfft_radix4_init_q31( - arm_cfft_radix4_instance_q31 * S, - uint16_t fftLen, - uint8_t ifftFlag, - uint8_t bitReverseFlag); + /* Deprecated */ + arm_status arm_cfft_radix4_init_q31( + arm_cfft_radix4_instance_q31 *S, + uint16_t fftLen, + uint8_t ifftFlag, + uint8_t bitReverseFlag); - /** + /** * @brief Instance structure for the floating-point CFFT/CIFFT function. */ - typedef struct - { - uint16_t fftLen; /**< length of the FFT. */ - uint8_t ifftFlag; /**< flag that selects forward (ifftFlag=0) or inverse (ifftFlag=1) transform. */ - uint8_t bitReverseFlag; /**< flag that enables (bitReverseFlag=1) or disables (bitReverseFlag=0) bit reversal of output. */ - float32_t *pTwiddle; /**< points to the Twiddle factor table. */ - uint16_t *pBitRevTable; /**< points to the bit reversal table. */ - uint16_t twidCoefModifier; /**< twiddle coefficient modifier that supports different size FFTs with the same twiddle factor table. */ - uint16_t bitRevFactor; /**< bit reversal modifier that supports different size FFTs with the same bit reversal table. */ - float32_t onebyfftLen; /**< value of 1/fftLen. */ - } arm_cfft_radix2_instance_f32; + typedef struct + { + uint16_t fftLen; /**< length of the FFT. */ + uint8_t ifftFlag; /**< flag that selects forward (ifftFlag=0) or inverse (ifftFlag=1) transform. */ + uint8_t bitReverseFlag; /**< flag that enables (bitReverseFlag=1) or disables (bitReverseFlag=0) bit reversal of output. */ + float32_t *pTwiddle; /**< points to the Twiddle factor table. */ + uint16_t *pBitRevTable; /**< points to the bit reversal table. */ + uint16_t twidCoefModifier; /**< twiddle coefficient modifier that supports different size FFTs with the same twiddle factor table. */ + uint16_t bitRevFactor; /**< bit reversal modifier that supports different size FFTs with the same bit reversal table. */ + float32_t onebyfftLen; /**< value of 1/fftLen. */ + } arm_cfft_radix2_instance_f32; -/* Deprecated */ - arm_status arm_cfft_radix2_init_f32( - arm_cfft_radix2_instance_f32 * S, - uint16_t fftLen, - uint8_t ifftFlag, - uint8_t bitReverseFlag); + /* Deprecated */ + arm_status arm_cfft_radix2_init_f32( + arm_cfft_radix2_instance_f32 *S, + uint16_t fftLen, + uint8_t ifftFlag, + uint8_t bitReverseFlag); -/* Deprecated */ - void arm_cfft_radix2_f32( - const arm_cfft_radix2_instance_f32 * S, - float32_t * pSrc); + /* Deprecated */ + void arm_cfft_radix2_f32( + const arm_cfft_radix2_instance_f32 *S, + float32_t *pSrc); - /** + /** * @brief Instance structure for the floating-point CFFT/CIFFT function. */ - typedef struct - { - uint16_t fftLen; /**< length of the FFT. */ - uint8_t ifftFlag; /**< flag that selects forward (ifftFlag=0) or inverse (ifftFlag=1) transform. */ - uint8_t bitReverseFlag; /**< flag that enables (bitReverseFlag=1) or disables (bitReverseFlag=0) bit reversal of output. */ - float32_t *pTwiddle; /**< points to the Twiddle factor table. */ - uint16_t *pBitRevTable; /**< points to the bit reversal table. */ - uint16_t twidCoefModifier; /**< twiddle coefficient modifier that supports different size FFTs with the same twiddle factor table. */ - uint16_t bitRevFactor; /**< bit reversal modifier that supports different size FFTs with the same bit reversal table. */ - float32_t onebyfftLen; /**< value of 1/fftLen. */ - } arm_cfft_radix4_instance_f32; + typedef struct + { + uint16_t fftLen; /**< length of the FFT. */ + uint8_t ifftFlag; /**< flag that selects forward (ifftFlag=0) or inverse (ifftFlag=1) transform. */ + uint8_t bitReverseFlag; /**< flag that enables (bitReverseFlag=1) or disables (bitReverseFlag=0) bit reversal of output. */ + float32_t *pTwiddle; /**< points to the Twiddle factor table. */ + uint16_t *pBitRevTable; /**< points to the bit reversal table. */ + uint16_t twidCoefModifier; /**< twiddle coefficient modifier that supports different size FFTs with the same twiddle factor table. */ + uint16_t bitRevFactor; /**< bit reversal modifier that supports different size FFTs with the same bit reversal table. */ + float32_t onebyfftLen; /**< value of 1/fftLen. */ + } arm_cfft_radix4_instance_f32; -/* Deprecated */ - arm_status arm_cfft_radix4_init_f32( - arm_cfft_radix4_instance_f32 * S, - uint16_t fftLen, - uint8_t ifftFlag, - uint8_t bitReverseFlag); + /* Deprecated */ + arm_status arm_cfft_radix4_init_f32( + arm_cfft_radix4_instance_f32 *S, + uint16_t fftLen, + uint8_t ifftFlag, + uint8_t bitReverseFlag); -/* Deprecated */ - void arm_cfft_radix4_f32( - const arm_cfft_radix4_instance_f32 * S, - float32_t * pSrc); + /* Deprecated */ + void arm_cfft_radix4_f32( + const arm_cfft_radix4_instance_f32 *S, + float32_t *pSrc); - /** + /** * @brief Instance structure for the fixed-point CFFT/CIFFT function. */ - typedef struct - { - uint16_t fftLen; /**< length of the FFT. */ - const q15_t *pTwiddle; /**< points to the Twiddle factor table. */ - const uint16_t *pBitRevTable; /**< points to the bit reversal table. */ - uint16_t bitRevLength; /**< bit reversal table length. */ - } arm_cfft_instance_q15; + typedef struct + { + uint16_t fftLen; /**< length of the FFT. */ + const q15_t *pTwiddle; /**< points to the Twiddle factor table. */ + const uint16_t *pBitRevTable; /**< points to the bit reversal table. */ + uint16_t bitRevLength; /**< bit reversal table length. */ + } arm_cfft_instance_q15; -void arm_cfft_q15( - const arm_cfft_instance_q15 * S, - q15_t * p1, - uint8_t ifftFlag, - uint8_t bitReverseFlag); + void arm_cfft_q15( + const arm_cfft_instance_q15 *S, + q15_t *p1, + uint8_t ifftFlag, + uint8_t bitReverseFlag); - /** + /** * @brief Instance structure for the fixed-point CFFT/CIFFT function. */ - typedef struct - { - uint16_t fftLen; /**< length of the FFT. */ - const q31_t *pTwiddle; /**< points to the Twiddle factor table. */ - const uint16_t *pBitRevTable; /**< points to the bit reversal table. */ - uint16_t bitRevLength; /**< bit reversal table length. */ - } arm_cfft_instance_q31; + typedef struct + { + uint16_t fftLen; /**< length of the FFT. */ + const q31_t *pTwiddle; /**< points to the Twiddle factor table. */ + const uint16_t *pBitRevTable; /**< points to the bit reversal table. */ + uint16_t bitRevLength; /**< bit reversal table length. */ + } arm_cfft_instance_q31; -void arm_cfft_q31( - const arm_cfft_instance_q31 * S, - q31_t * p1, - uint8_t ifftFlag, - uint8_t bitReverseFlag); - - /** + void arm_cfft_q31( + const arm_cfft_instance_q31 *S, + q31_t *p1, + uint8_t ifftFlag, + uint8_t bitReverseFlag); + + /** * @brief Instance structure for the floating-point CFFT/CIFFT function. */ - typedef struct - { - uint16_t fftLen; /**< length of the FFT. */ - const float32_t *pTwiddle; /**< points to the Twiddle factor table. */ - const uint16_t *pBitRevTable; /**< points to the bit reversal table. */ - uint16_t bitRevLength; /**< bit reversal table length. */ - } arm_cfft_instance_f32; + typedef struct + { + uint16_t fftLen; /**< length of the FFT. */ + const float32_t *pTwiddle; /**< points to the Twiddle factor table. */ + const uint16_t *pBitRevTable; /**< points to the bit reversal table. */ + uint16_t bitRevLength; /**< bit reversal table length. */ + } arm_cfft_instance_f32; - void arm_cfft_f32( - const arm_cfft_instance_f32 * S, - float32_t * p1, - uint8_t ifftFlag, - uint8_t bitReverseFlag); + void arm_cfft_f32( + const arm_cfft_instance_f32 *S, + float32_t *p1, + uint8_t ifftFlag, + uint8_t bitReverseFlag); - /** + /** * @brief Instance structure for the Q15 RFFT/RIFFT function. */ - typedef struct - { - uint32_t fftLenReal; /**< length of the real FFT. */ - uint8_t ifftFlagR; /**< flag that selects forward (ifftFlagR=0) or inverse (ifftFlagR=1) transform. */ - uint8_t bitReverseFlagR; /**< flag that enables (bitReverseFlagR=1) or disables (bitReverseFlagR=0) bit reversal of output. */ - uint32_t twidCoefRModifier; /**< twiddle coefficient modifier that supports different size FFTs with the same twiddle factor table. */ - q15_t *pTwiddleAReal; /**< points to the real twiddle factor table. */ - q15_t *pTwiddleBReal; /**< points to the imag twiddle factor table. */ - const arm_cfft_instance_q15 *pCfft; /**< points to the complex FFT instance. */ - } arm_rfft_instance_q15; + typedef struct + { + uint32_t fftLenReal; /**< length of the real FFT. */ + uint8_t ifftFlagR; /**< flag that selects forward (ifftFlagR=0) or inverse (ifftFlagR=1) transform. */ + uint8_t bitReverseFlagR; /**< flag that enables (bitReverseFlagR=1) or disables (bitReverseFlagR=0) bit reversal of output. */ + uint32_t twidCoefRModifier; /**< twiddle coefficient modifier that supports different size FFTs with the same twiddle factor table. */ + q15_t *pTwiddleAReal; /**< points to the real twiddle factor table. */ + q15_t *pTwiddleBReal; /**< points to the imag twiddle factor table. */ + const arm_cfft_instance_q15 *pCfft; /**< points to the complex FFT instance. */ + } arm_rfft_instance_q15; - arm_status arm_rfft_init_q15( - arm_rfft_instance_q15 * S, - uint32_t fftLenReal, - uint32_t ifftFlagR, - uint32_t bitReverseFlag); + arm_status arm_rfft_init_q15( + arm_rfft_instance_q15 *S, + uint32_t fftLenReal, + uint32_t ifftFlagR, + uint32_t bitReverseFlag); - void arm_rfft_q15( - const arm_rfft_instance_q15 * S, - q15_t * pSrc, - q15_t * pDst); + void arm_rfft_q15( + const arm_rfft_instance_q15 *S, + q15_t *pSrc, + q15_t *pDst); - /** + /** * @brief Instance structure for the Q31 RFFT/RIFFT function. */ - typedef struct - { - uint32_t fftLenReal; /**< length of the real FFT. */ - uint8_t ifftFlagR; /**< flag that selects forward (ifftFlagR=0) or inverse (ifftFlagR=1) transform. */ - uint8_t bitReverseFlagR; /**< flag that enables (bitReverseFlagR=1) or disables (bitReverseFlagR=0) bit reversal of output. */ - uint32_t twidCoefRModifier; /**< twiddle coefficient modifier that supports different size FFTs with the same twiddle factor table. */ - q31_t *pTwiddleAReal; /**< points to the real twiddle factor table. */ - q31_t *pTwiddleBReal; /**< points to the imag twiddle factor table. */ - const arm_cfft_instance_q31 *pCfft; /**< points to the complex FFT instance. */ - } arm_rfft_instance_q31; + typedef struct + { + uint32_t fftLenReal; /**< length of the real FFT. */ + uint8_t ifftFlagR; /**< flag that selects forward (ifftFlagR=0) or inverse (ifftFlagR=1) transform. */ + uint8_t bitReverseFlagR; /**< flag that enables (bitReverseFlagR=1) or disables (bitReverseFlagR=0) bit reversal of output. */ + uint32_t twidCoefRModifier; /**< twiddle coefficient modifier that supports different size FFTs with the same twiddle factor table. */ + q31_t *pTwiddleAReal; /**< points to the real twiddle factor table. */ + q31_t *pTwiddleBReal; /**< points to the imag twiddle factor table. */ + const arm_cfft_instance_q31 *pCfft; /**< points to the complex FFT instance. */ + } arm_rfft_instance_q31; - arm_status arm_rfft_init_q31( - arm_rfft_instance_q31 * S, - uint32_t fftLenReal, - uint32_t ifftFlagR, - uint32_t bitReverseFlag); + arm_status arm_rfft_init_q31( + arm_rfft_instance_q31 *S, + uint32_t fftLenReal, + uint32_t ifftFlagR, + uint32_t bitReverseFlag); - void arm_rfft_q31( - const arm_rfft_instance_q31 * S, - q31_t * pSrc, - q31_t * pDst); + void arm_rfft_q31( + const arm_rfft_instance_q31 *S, + q31_t *pSrc, + q31_t *pDst); - /** + /** * @brief Instance structure for the floating-point RFFT/RIFFT function. */ - typedef struct - { - uint32_t fftLenReal; /**< length of the real FFT. */ - uint16_t fftLenBy2; /**< length of the complex FFT. */ - uint8_t ifftFlagR; /**< flag that selects forward (ifftFlagR=0) or inverse (ifftFlagR=1) transform. */ - uint8_t bitReverseFlagR; /**< flag that enables (bitReverseFlagR=1) or disables (bitReverseFlagR=0) bit reversal of output. */ - uint32_t twidCoefRModifier; /**< twiddle coefficient modifier that supports different size FFTs with the same twiddle factor table. */ - float32_t *pTwiddleAReal; /**< points to the real twiddle factor table. */ - float32_t *pTwiddleBReal; /**< points to the imag twiddle factor table. */ - arm_cfft_radix4_instance_f32 *pCfft; /**< points to the complex FFT instance. */ - } arm_rfft_instance_f32; + typedef struct + { + uint32_t fftLenReal; /**< length of the real FFT. */ + uint16_t fftLenBy2; /**< length of the complex FFT. */ + uint8_t ifftFlagR; /**< flag that selects forward (ifftFlagR=0) or inverse (ifftFlagR=1) transform. */ + uint8_t bitReverseFlagR; /**< flag that enables (bitReverseFlagR=1) or disables (bitReverseFlagR=0) bit reversal of output. */ + uint32_t twidCoefRModifier; /**< twiddle coefficient modifier that supports different size FFTs with the same twiddle factor table. */ + float32_t *pTwiddleAReal; /**< points to the real twiddle factor table. */ + float32_t *pTwiddleBReal; /**< points to the imag twiddle factor table. */ + arm_cfft_radix4_instance_f32 *pCfft; /**< points to the complex FFT instance. */ + } arm_rfft_instance_f32; - arm_status arm_rfft_init_f32( - arm_rfft_instance_f32 * S, - arm_cfft_radix4_instance_f32 * S_CFFT, - uint32_t fftLenReal, - uint32_t ifftFlagR, - uint32_t bitReverseFlag); + arm_status arm_rfft_init_f32( + arm_rfft_instance_f32 *S, + arm_cfft_radix4_instance_f32 *S_CFFT, + uint32_t fftLenReal, + uint32_t ifftFlagR, + uint32_t bitReverseFlag); - void arm_rfft_f32( - const arm_rfft_instance_f32 * S, - float32_t * pSrc, - float32_t * pDst); + void arm_rfft_f32( + const arm_rfft_instance_f32 *S, + float32_t *pSrc, + float32_t *pDst); - /** + /** * @brief Instance structure for the floating-point RFFT/RIFFT function. */ -typedef struct - { - arm_cfft_instance_f32 Sint; /**< Internal CFFT structure. */ - uint16_t fftLenRFFT; /**< length of the real sequence */ - float32_t * pTwiddleRFFT; /**< Twiddle factors real stage */ - } arm_rfft_fast_instance_f32 ; + typedef struct + { + arm_cfft_instance_f32 Sint; /**< Internal CFFT structure. */ + uint16_t fftLenRFFT; /**< length of the real sequence */ + float32_t *pTwiddleRFFT; /**< Twiddle factors real stage */ + } arm_rfft_fast_instance_f32; -arm_status arm_rfft_fast_init_f32 ( - arm_rfft_fast_instance_f32 * S, - uint16_t fftLen); + arm_status arm_rfft_fast_init_f32( + arm_rfft_fast_instance_f32 *S, + uint16_t fftLen); -void arm_rfft_fast_f32( - arm_rfft_fast_instance_f32 * S, - float32_t * p, float32_t * pOut, - uint8_t ifftFlag); + void arm_rfft_fast_f32( + arm_rfft_fast_instance_f32 *S, + float32_t *p, float32_t *pOut, + uint8_t ifftFlag); - /** + /** * @brief Instance structure for the floating-point DCT4/IDCT4 function. */ - typedef struct - { - uint16_t N; /**< length of the DCT4. */ - uint16_t Nby2; /**< half of the length of the DCT4. */ - float32_t normalize; /**< normalizing factor. */ - float32_t *pTwiddle; /**< points to the twiddle factor table. */ - float32_t *pCosFactor; /**< points to the cosFactor table. */ - arm_rfft_instance_f32 *pRfft; /**< points to the real FFT instance. */ - arm_cfft_radix4_instance_f32 *pCfft; /**< points to the complex FFT instance. */ - } arm_dct4_instance_f32; + typedef struct + { + uint16_t N; /**< length of the DCT4. */ + uint16_t Nby2; /**< half of the length of the DCT4. */ + float32_t normalize; /**< normalizing factor. */ + float32_t *pTwiddle; /**< points to the twiddle factor table. */ + float32_t *pCosFactor; /**< points to the cosFactor table. */ + arm_rfft_instance_f32 *pRfft; /**< points to the real FFT instance. */ + arm_cfft_radix4_instance_f32 *pCfft; /**< points to the complex FFT instance. */ + } arm_dct4_instance_f32; - /** + /** * @brief Initialization function for the floating-point DCT4/IDCT4. * @param[in,out] *S points to an instance of floating-point DCT4/IDCT4 structure. * @param[in] *S_RFFT points to an instance of floating-point RFFT/RIFFT structure. @@ -2379,18 +2321,18 @@ void arm_rfft_fast_f32( * @param[in] N length of the DCT4. * @param[in] Nby2 half of the length of the DCT4. * @param[in] normalize normalizing factor. - * @return arm_status function returns ARM_MATH_SUCCESS if initialization is successful or ARM_MATH_ARGUMENT_ERROR if <code>fftLenReal</code> is not a supported transform length. + * @return arm_status function returns ARM_MATH_SUCCESS if initialization is successful or ARM_MATH_ARGUMENT_ERROR if <code>fftLenReal</code> is not a supported transform length. */ - arm_status arm_dct4_init_f32( - arm_dct4_instance_f32 * S, - arm_rfft_instance_f32 * S_RFFT, - arm_cfft_radix4_instance_f32 * S_CFFT, - uint16_t N, - uint16_t Nby2, - float32_t normalize); + arm_status arm_dct4_init_f32( + arm_dct4_instance_f32 *S, + arm_rfft_instance_f32 *S_RFFT, + arm_cfft_radix4_instance_f32 *S_CFFT, + uint16_t N, + uint16_t Nby2, + float32_t normalize); - /** + /** * @brief Processing function for the floating-point DCT4/IDCT4. * @param[in] *S points to an instance of the floating-point DCT4/IDCT4 structure. * @param[in] *pState points to state buffer. @@ -2398,27 +2340,27 @@ void arm_rfft_fast_f32( * @return none. */ - void arm_dct4_f32( - const arm_dct4_instance_f32 * S, - float32_t * pState, - float32_t * pInlineBuffer); + void arm_dct4_f32( + const arm_dct4_instance_f32 *S, + float32_t *pState, + float32_t *pInlineBuffer); - /** + /** * @brief Instance structure for the Q31 DCT4/IDCT4 function. */ - typedef struct - { - uint16_t N; /**< length of the DCT4. */ - uint16_t Nby2; /**< half of the length of the DCT4. */ - q31_t normalize; /**< normalizing factor. */ - q31_t *pTwiddle; /**< points to the twiddle factor table. */ - q31_t *pCosFactor; /**< points to the cosFactor table. */ - arm_rfft_instance_q31 *pRfft; /**< points to the real FFT instance. */ - arm_cfft_radix4_instance_q31 *pCfft; /**< points to the complex FFT instance. */ - } arm_dct4_instance_q31; + typedef struct + { + uint16_t N; /**< length of the DCT4. */ + uint16_t Nby2; /**< half of the length of the DCT4. */ + q31_t normalize; /**< normalizing factor. */ + q31_t *pTwiddle; /**< points to the twiddle factor table. */ + q31_t *pCosFactor; /**< points to the cosFactor table. */ + arm_rfft_instance_q31 *pRfft; /**< points to the real FFT instance. */ + arm_cfft_radix4_instance_q31 *pCfft; /**< points to the complex FFT instance. */ + } arm_dct4_instance_q31; - /** + /** * @brief Initialization function for the Q31 DCT4/IDCT4. * @param[in,out] *S points to an instance of Q31 DCT4/IDCT4 structure. * @param[in] *S_RFFT points to an instance of Q31 RFFT/RIFFT structure @@ -2426,18 +2368,18 @@ void arm_rfft_fast_f32( * @param[in] N length of the DCT4. * @param[in] Nby2 half of the length of the DCT4. * @param[in] normalize normalizing factor. - * @return arm_status function returns ARM_MATH_SUCCESS if initialization is successful or ARM_MATH_ARGUMENT_ERROR if <code>N</code> is not a supported transform length. + * @return arm_status function returns ARM_MATH_SUCCESS if initialization is successful or ARM_MATH_ARGUMENT_ERROR if <code>N</code> is not a supported transform length. */ - arm_status arm_dct4_init_q31( - arm_dct4_instance_q31 * S, - arm_rfft_instance_q31 * S_RFFT, - arm_cfft_radix4_instance_q31 * S_CFFT, - uint16_t N, - uint16_t Nby2, - q31_t normalize); + arm_status arm_dct4_init_q31( + arm_dct4_instance_q31 *S, + arm_rfft_instance_q31 *S_RFFT, + arm_cfft_radix4_instance_q31 *S_CFFT, + uint16_t N, + uint16_t Nby2, + q31_t normalize); - /** + /** * @brief Processing function for the Q31 DCT4/IDCT4. * @param[in] *S points to an instance of the Q31 DCT4 structure. * @param[in] *pState points to state buffer. @@ -2445,27 +2387,27 @@ void arm_rfft_fast_f32( * @return none. */ - void arm_dct4_q31( - const arm_dct4_instance_q31 * S, - q31_t * pState, - q31_t * pInlineBuffer); + void arm_dct4_q31( + const arm_dct4_instance_q31 *S, + q31_t *pState, + q31_t *pInlineBuffer); - /** + /** * @brief Instance structure for the Q15 DCT4/IDCT4 function. */ - typedef struct - { - uint16_t N; /**< length of the DCT4. */ - uint16_t Nby2; /**< half of the length of the DCT4. */ - q15_t normalize; /**< normalizing factor. */ - q15_t *pTwiddle; /**< points to the twiddle factor table. */ - q15_t *pCosFactor; /**< points to the cosFactor table. */ - arm_rfft_instance_q15 *pRfft; /**< points to the real FFT instance. */ - arm_cfft_radix4_instance_q15 *pCfft; /**< points to the complex FFT instance. */ - } arm_dct4_instance_q15; + typedef struct + { + uint16_t N; /**< length of the DCT4. */ + uint16_t Nby2; /**< half of the length of the DCT4. */ + q15_t normalize; /**< normalizing factor. */ + q15_t *pTwiddle; /**< points to the twiddle factor table. */ + q15_t *pCosFactor; /**< points to the cosFactor table. */ + arm_rfft_instance_q15 *pRfft; /**< points to the real FFT instance. */ + arm_cfft_radix4_instance_q15 *pCfft; /**< points to the complex FFT instance. */ + } arm_dct4_instance_q15; - /** + /** * @brief Initialization function for the Q15 DCT4/IDCT4. * @param[in,out] *S points to an instance of Q15 DCT4/IDCT4 structure. * @param[in] *S_RFFT points to an instance of Q15 RFFT/RIFFT structure. @@ -2473,18 +2415,18 @@ void arm_rfft_fast_f32( * @param[in] N length of the DCT4. * @param[in] Nby2 half of the length of the DCT4. * @param[in] normalize normalizing factor. - * @return arm_status function returns ARM_MATH_SUCCESS if initialization is successful or ARM_MATH_ARGUMENT_ERROR if <code>N</code> is not a supported transform length. + * @return arm_status function returns ARM_MATH_SUCCESS if initialization is successful or ARM_MATH_ARGUMENT_ERROR if <code>N</code> is not a supported transform length. */ - arm_status arm_dct4_init_q15( - arm_dct4_instance_q15 * S, - arm_rfft_instance_q15 * S_RFFT, - arm_cfft_radix4_instance_q15 * S_CFFT, - uint16_t N, - uint16_t Nby2, - q15_t normalize); + arm_status arm_dct4_init_q15( + arm_dct4_instance_q15 *S, + arm_rfft_instance_q15 *S_RFFT, + arm_cfft_radix4_instance_q15 *S_CFFT, + uint16_t N, + uint16_t Nby2, + q15_t normalize); - /** + /** * @brief Processing function for the Q15 DCT4/IDCT4. * @param[in] *S points to an instance of the Q15 DCT4 structure. * @param[in] *pState points to state buffer. @@ -2492,12 +2434,12 @@ void arm_rfft_fast_f32( * @return none. */ - void arm_dct4_q15( - const arm_dct4_instance_q15 * S, - q15_t * pState, - q15_t * pInlineBuffer); + void arm_dct4_q15( + const arm_dct4_instance_q15 *S, + q15_t *pState, + q15_t *pInlineBuffer); - /** + /** * @brief Floating-point vector addition. * @param[in] *pSrcA points to the first input vector * @param[in] *pSrcB points to the second input vector @@ -2506,13 +2448,13 @@ void arm_rfft_fast_f32( * @return none. */ - void arm_add_f32( - float32_t * pSrcA, - float32_t * pSrcB, - float32_t * pDst, - uint32_t blockSize); + void arm_add_f32( + float32_t *pSrcA, + float32_t *pSrcB, + float32_t *pDst, + uint32_t blockSize); - /** + /** * @brief Q7 vector addition. * @param[in] *pSrcA points to the first input vector * @param[in] *pSrcB points to the second input vector @@ -2521,13 +2463,13 @@ void arm_rfft_fast_f32( * @return none. */ - void arm_add_q7( - q7_t * pSrcA, - q7_t * pSrcB, - q7_t * pDst, - uint32_t blockSize); + void arm_add_q7( + q7_t *pSrcA, + q7_t *pSrcB, + q7_t *pDst, + uint32_t blockSize); - /** + /** * @brief Q15 vector addition. * @param[in] *pSrcA points to the first input vector * @param[in] *pSrcB points to the second input vector @@ -2536,13 +2478,13 @@ void arm_rfft_fast_f32( * @return none. */ - void arm_add_q15( - q15_t * pSrcA, - q15_t * pSrcB, - q15_t * pDst, - uint32_t blockSize); + void arm_add_q15( + q15_t *pSrcA, + q15_t *pSrcB, + q15_t *pDst, + uint32_t blockSize); - /** + /** * @brief Q31 vector addition. * @param[in] *pSrcA points to the first input vector * @param[in] *pSrcB points to the second input vector @@ -2551,13 +2493,13 @@ void arm_rfft_fast_f32( * @return none. */ - void arm_add_q31( - q31_t * pSrcA, - q31_t * pSrcB, - q31_t * pDst, - uint32_t blockSize); + void arm_add_q31( + q31_t *pSrcA, + q31_t *pSrcB, + q31_t *pDst, + uint32_t blockSize); - /** + /** * @brief Floating-point vector subtraction. * @param[in] *pSrcA points to the first input vector * @param[in] *pSrcB points to the second input vector @@ -2566,13 +2508,13 @@ void arm_rfft_fast_f32( * @return none. */ - void arm_sub_f32( - float32_t * pSrcA, - float32_t * pSrcB, - float32_t * pDst, - uint32_t blockSize); + void arm_sub_f32( + float32_t *pSrcA, + float32_t *pSrcB, + float32_t *pDst, + uint32_t blockSize); - /** + /** * @brief Q7 vector subtraction. * @param[in] *pSrcA points to the first input vector * @param[in] *pSrcB points to the second input vector @@ -2581,13 +2523,13 @@ void arm_rfft_fast_f32( * @return none. */ - void arm_sub_q7( - q7_t * pSrcA, - q7_t * pSrcB, - q7_t * pDst, - uint32_t blockSize); + void arm_sub_q7( + q7_t *pSrcA, + q7_t *pSrcB, + q7_t *pDst, + uint32_t blockSize); - /** + /** * @brief Q15 vector subtraction. * @param[in] *pSrcA points to the first input vector * @param[in] *pSrcB points to the second input vector @@ -2596,13 +2538,13 @@ void arm_rfft_fast_f32( * @return none. */ - void arm_sub_q15( - q15_t * pSrcA, - q15_t * pSrcB, - q15_t * pDst, - uint32_t blockSize); + void arm_sub_q15( + q15_t *pSrcA, + q15_t *pSrcB, + q15_t *pDst, + uint32_t blockSize); - /** + /** * @brief Q31 vector subtraction. * @param[in] *pSrcA points to the first input vector * @param[in] *pSrcB points to the second input vector @@ -2611,13 +2553,13 @@ void arm_rfft_fast_f32( * @return none. */ - void arm_sub_q31( - q31_t * pSrcA, - q31_t * pSrcB, - q31_t * pDst, - uint32_t blockSize); + void arm_sub_q31( + q31_t *pSrcA, + q31_t *pSrcB, + q31_t *pDst, + uint32_t blockSize); - /** + /** * @brief Multiplies a floating-point vector by a scalar. * @param[in] *pSrc points to the input vector * @param[in] scale scale factor to be applied @@ -2626,13 +2568,13 @@ void arm_rfft_fast_f32( * @return none. */ - void arm_scale_f32( - float32_t * pSrc, - float32_t scale, - float32_t * pDst, - uint32_t blockSize); + void arm_scale_f32( + float32_t *pSrc, + float32_t scale, + float32_t *pDst, + uint32_t blockSize); - /** + /** * @brief Multiplies a Q7 vector by a scalar. * @param[in] *pSrc points to the input vector * @param[in] scaleFract fractional portion of the scale value @@ -2642,14 +2584,14 @@ void arm_rfft_fast_f32( * @return none. */ - void arm_scale_q7( - q7_t * pSrc, - q7_t scaleFract, - int8_t shift, - q7_t * pDst, - uint32_t blockSize); + void arm_scale_q7( + q7_t *pSrc, + q7_t scaleFract, + int8_t shift, + q7_t *pDst, + uint32_t blockSize); - /** + /** * @brief Multiplies a Q15 vector by a scalar. * @param[in] *pSrc points to the input vector * @param[in] scaleFract fractional portion of the scale value @@ -2659,14 +2601,14 @@ void arm_rfft_fast_f32( * @return none. */ - void arm_scale_q15( - q15_t * pSrc, - q15_t scaleFract, - int8_t shift, - q15_t * pDst, - uint32_t blockSize); + void arm_scale_q15( + q15_t *pSrc, + q15_t scaleFract, + int8_t shift, + q15_t *pDst, + uint32_t blockSize); - /** + /** * @brief Multiplies a Q31 vector by a scalar. * @param[in] *pSrc points to the input vector * @param[in] scaleFract fractional portion of the scale value @@ -2676,14 +2618,14 @@ void arm_rfft_fast_f32( * @return none. */ - void arm_scale_q31( - q31_t * pSrc, - q31_t scaleFract, - int8_t shift, - q31_t * pDst, - uint32_t blockSize); + void arm_scale_q31( + q31_t *pSrc, + q31_t scaleFract, + int8_t shift, + q31_t *pDst, + uint32_t blockSize); - /** + /** * @brief Q7 vector absolute value. * @param[in] *pSrc points to the input buffer * @param[out] *pDst points to the output buffer @@ -2691,12 +2633,12 @@ void arm_rfft_fast_f32( * @return none. */ - void arm_abs_q7( - q7_t * pSrc, - q7_t * pDst, - uint32_t blockSize); + void arm_abs_q7( + q7_t *pSrc, + q7_t *pDst, + uint32_t blockSize); - /** + /** * @brief Floating-point vector absolute value. * @param[in] *pSrc points to the input buffer * @param[out] *pDst points to the output buffer @@ -2704,12 +2646,12 @@ void arm_rfft_fast_f32( * @return none. */ - void arm_abs_f32( - float32_t * pSrc, - float32_t * pDst, - uint32_t blockSize); + void arm_abs_f32( + float32_t *pSrc, + float32_t *pDst, + uint32_t blockSize); - /** + /** * @brief Q15 vector absolute value. * @param[in] *pSrc points to the input buffer * @param[out] *pDst points to the output buffer @@ -2717,12 +2659,12 @@ void arm_rfft_fast_f32( * @return none. */ - void arm_abs_q15( - q15_t * pSrc, - q15_t * pDst, - uint32_t blockSize); + void arm_abs_q15( + q15_t *pSrc, + q15_t *pDst, + uint32_t blockSize); - /** + /** * @brief Q31 vector absolute value. * @param[in] *pSrc points to the input buffer * @param[out] *pDst points to the output buffer @@ -2730,12 +2672,12 @@ void arm_rfft_fast_f32( * @return none. */ - void arm_abs_q31( - q31_t * pSrc, - q31_t * pDst, - uint32_t blockSize); + void arm_abs_q31( + q31_t *pSrc, + q31_t *pDst, + uint32_t blockSize); - /** + /** * @brief Dot product of floating-point vectors. * @param[in] *pSrcA points to the first input vector * @param[in] *pSrcB points to the second input vector @@ -2744,13 +2686,13 @@ void arm_rfft_fast_f32( * @return none. */ - void arm_dot_prod_f32( - float32_t * pSrcA, - float32_t * pSrcB, - uint32_t blockSize, - float32_t * result); + void arm_dot_prod_f32( + float32_t *pSrcA, + float32_t *pSrcB, + uint32_t blockSize, + float32_t *result); - /** + /** * @brief Dot product of Q7 vectors. * @param[in] *pSrcA points to the first input vector * @param[in] *pSrcB points to the second input vector @@ -2759,13 +2701,13 @@ void arm_rfft_fast_f32( * @return none. */ - void arm_dot_prod_q7( - q7_t * pSrcA, - q7_t * pSrcB, - uint32_t blockSize, - q31_t * result); + void arm_dot_prod_q7( + q7_t *pSrcA, + q7_t *pSrcB, + uint32_t blockSize, + q31_t *result); - /** + /** * @brief Dot product of Q15 vectors. * @param[in] *pSrcA points to the first input vector * @param[in] *pSrcB points to the second input vector @@ -2774,13 +2716,13 @@ void arm_rfft_fast_f32( * @return none. */ - void arm_dot_prod_q15( - q15_t * pSrcA, - q15_t * pSrcB, - uint32_t blockSize, - q63_t * result); + void arm_dot_prod_q15( + q15_t *pSrcA, + q15_t *pSrcB, + uint32_t blockSize, + q63_t *result); - /** + /** * @brief Dot product of Q31 vectors. * @param[in] *pSrcA points to the first input vector * @param[in] *pSrcB points to the second input vector @@ -2789,13 +2731,13 @@ void arm_rfft_fast_f32( * @return none. */ - void arm_dot_prod_q31( - q31_t * pSrcA, - q31_t * pSrcB, - uint32_t blockSize, - q63_t * result); + void arm_dot_prod_q31( + q31_t *pSrcA, + q31_t *pSrcB, + uint32_t blockSize, + q63_t *result); - /** + /** * @brief Shifts the elements of a Q7 vector a specified number of bits. * @param[in] *pSrc points to the input vector * @param[in] shiftBits number of bits to shift. A positive value shifts left; a negative value shifts right. @@ -2804,13 +2746,13 @@ void arm_rfft_fast_f32( * @return none. */ - void arm_shift_q7( - q7_t * pSrc, - int8_t shiftBits, - q7_t * pDst, - uint32_t blockSize); + void arm_shift_q7( + q7_t *pSrc, + int8_t shiftBits, + q7_t *pDst, + uint32_t blockSize); - /** + /** * @brief Shifts the elements of a Q15 vector a specified number of bits. * @param[in] *pSrc points to the input vector * @param[in] shiftBits number of bits to shift. A positive value shifts left; a negative value shifts right. @@ -2819,13 +2761,13 @@ void arm_rfft_fast_f32( * @return none. */ - void arm_shift_q15( - q15_t * pSrc, - int8_t shiftBits, - q15_t * pDst, - uint32_t blockSize); + void arm_shift_q15( + q15_t *pSrc, + int8_t shiftBits, + q15_t *pDst, + uint32_t blockSize); - /** + /** * @brief Shifts the elements of a Q31 vector a specified number of bits. * @param[in] *pSrc points to the input vector * @param[in] shiftBits number of bits to shift. A positive value shifts left; a negative value shifts right. @@ -2834,13 +2776,13 @@ void arm_rfft_fast_f32( * @return none. */ - void arm_shift_q31( - q31_t * pSrc, - int8_t shiftBits, - q31_t * pDst, - uint32_t blockSize); + void arm_shift_q31( + q31_t *pSrc, + int8_t shiftBits, + q31_t *pDst, + uint32_t blockSize); - /** + /** * @brief Adds a constant offset to a floating-point vector. * @param[in] *pSrc points to the input vector * @param[in] offset is the offset to be added @@ -2849,13 +2791,13 @@ void arm_rfft_fast_f32( * @return none. */ - void arm_offset_f32( - float32_t * pSrc, - float32_t offset, - float32_t * pDst, - uint32_t blockSize); + void arm_offset_f32( + float32_t *pSrc, + float32_t offset, + float32_t *pDst, + uint32_t blockSize); - /** + /** * @brief Adds a constant offset to a Q7 vector. * @param[in] *pSrc points to the input vector * @param[in] offset is the offset to be added @@ -2864,13 +2806,13 @@ void arm_rfft_fast_f32( * @return none. */ - void arm_offset_q7( - q7_t * pSrc, - q7_t offset, - q7_t * pDst, - uint32_t blockSize); + void arm_offset_q7( + q7_t *pSrc, + q7_t offset, + q7_t *pDst, + uint32_t blockSize); - /** + /** * @brief Adds a constant offset to a Q15 vector. * @param[in] *pSrc points to the input vector * @param[in] offset is the offset to be added @@ -2879,13 +2821,13 @@ void arm_rfft_fast_f32( * @return none. */ - void arm_offset_q15( - q15_t * pSrc, - q15_t offset, - q15_t * pDst, - uint32_t blockSize); + void arm_offset_q15( + q15_t *pSrc, + q15_t offset, + q15_t *pDst, + uint32_t blockSize); - /** + /** * @brief Adds a constant offset to a Q31 vector. * @param[in] *pSrc points to the input vector * @param[in] offset is the offset to be added @@ -2894,13 +2836,13 @@ void arm_rfft_fast_f32( * @return none. */ - void arm_offset_q31( - q31_t * pSrc, - q31_t offset, - q31_t * pDst, - uint32_t blockSize); + void arm_offset_q31( + q31_t *pSrc, + q31_t offset, + q31_t *pDst, + uint32_t blockSize); - /** + /** * @brief Negates the elements of a floating-point vector. * @param[in] *pSrc points to the input vector * @param[out] *pDst points to the output vector @@ -2908,12 +2850,12 @@ void arm_rfft_fast_f32( * @return none. */ - void arm_negate_f32( - float32_t * pSrc, - float32_t * pDst, - uint32_t blockSize); + void arm_negate_f32( + float32_t *pSrc, + float32_t *pDst, + uint32_t blockSize); - /** + /** * @brief Negates the elements of a Q7 vector. * @param[in] *pSrc points to the input vector * @param[out] *pDst points to the output vector @@ -2921,12 +2863,12 @@ void arm_rfft_fast_f32( * @return none. */ - void arm_negate_q7( - q7_t * pSrc, - q7_t * pDst, - uint32_t blockSize); + void arm_negate_q7( + q7_t *pSrc, + q7_t *pDst, + uint32_t blockSize); - /** + /** * @brief Negates the elements of a Q15 vector. * @param[in] *pSrc points to the input vector * @param[out] *pDst points to the output vector @@ -2934,12 +2876,12 @@ void arm_rfft_fast_f32( * @return none. */ - void arm_negate_q15( - q15_t * pSrc, - q15_t * pDst, - uint32_t blockSize); + void arm_negate_q15( + q15_t *pSrc, + q15_t *pDst, + uint32_t blockSize); - /** + /** * @brief Negates the elements of a Q31 vector. * @param[in] *pSrc points to the input vector * @param[out] *pDst points to the output vector @@ -2947,106 +2889,106 @@ void arm_rfft_fast_f32( * @return none. */ - void arm_negate_q31( - q31_t * pSrc, - q31_t * pDst, - uint32_t blockSize); - /** + void arm_negate_q31( + q31_t *pSrc, + q31_t *pDst, + uint32_t blockSize); + /** * @brief Copies the elements of a floating-point vector. * @param[in] *pSrc input pointer * @param[out] *pDst output pointer * @param[in] blockSize number of samples to process * @return none. */ - void arm_copy_f32( - float32_t * pSrc, - float32_t * pDst, - uint32_t blockSize); + void arm_copy_f32( + float32_t *pSrc, + float32_t *pDst, + uint32_t blockSize); - /** + /** * @brief Copies the elements of a Q7 vector. * @param[in] *pSrc input pointer * @param[out] *pDst output pointer * @param[in] blockSize number of samples to process * @return none. */ - void arm_copy_q7( - q7_t * pSrc, - q7_t * pDst, - uint32_t blockSize); + void arm_copy_q7( + q7_t *pSrc, + q7_t *pDst, + uint32_t blockSize); - /** + /** * @brief Copies the elements of a Q15 vector. * @param[in] *pSrc input pointer * @param[out] *pDst output pointer * @param[in] blockSize number of samples to process * @return none. */ - void arm_copy_q15( - q15_t * pSrc, - q15_t * pDst, - uint32_t blockSize); + void arm_copy_q15( + q15_t *pSrc, + q15_t *pDst, + uint32_t blockSize); - /** + /** * @brief Copies the elements of a Q31 vector. * @param[in] *pSrc input pointer * @param[out] *pDst output pointer * @param[in] blockSize number of samples to process * @return none. */ - void arm_copy_q31( - q31_t * pSrc, - q31_t * pDst, - uint32_t blockSize); - /** + void arm_copy_q31( + q31_t *pSrc, + q31_t *pDst, + uint32_t blockSize); + /** * @brief Fills a constant value into a floating-point vector. * @param[in] value input value to be filled * @param[out] *pDst output pointer * @param[in] blockSize number of samples to process * @return none. */ - void arm_fill_f32( - float32_t value, - float32_t * pDst, - uint32_t blockSize); + void arm_fill_f32( + float32_t value, + float32_t *pDst, + uint32_t blockSize); - /** + /** * @brief Fills a constant value into a Q7 vector. * @param[in] value input value to be filled * @param[out] *pDst output pointer * @param[in] blockSize number of samples to process * @return none. */ - void arm_fill_q7( - q7_t value, - q7_t * pDst, - uint32_t blockSize); + void arm_fill_q7( + q7_t value, + q7_t *pDst, + uint32_t blockSize); - /** + /** * @brief Fills a constant value into a Q15 vector. * @param[in] value input value to be filled * @param[out] *pDst output pointer * @param[in] blockSize number of samples to process * @return none. */ - void arm_fill_q15( - q15_t value, - q15_t * pDst, - uint32_t blockSize); + void arm_fill_q15( + q15_t value, + q15_t *pDst, + uint32_t blockSize); - /** + /** * @brief Fills a constant value into a Q31 vector. * @param[in] value input value to be filled * @param[out] *pDst output pointer * @param[in] blockSize number of samples to process * @return none. */ - void arm_fill_q31( - q31_t value, - q31_t * pDst, - uint32_t blockSize); + void arm_fill_q31( + q31_t value, + q31_t *pDst, + uint32_t blockSize); -/** + /** * @brief Convolution of floating-point sequences. * @param[in] *pSrcA points to the first input sequence. * @param[in] srcALen length of the first input sequence. @@ -3056,15 +2998,14 @@ void arm_rfft_fast_f32( * @return none. */ - void arm_conv_f32( - float32_t * pSrcA, - uint32_t srcALen, - float32_t * pSrcB, - uint32_t srcBLen, - float32_t * pDst); - + void arm_conv_f32( + float32_t *pSrcA, + uint32_t srcALen, + float32_t *pSrcB, + uint32_t srcBLen, + float32_t *pDst); - /** + /** * @brief Convolution of Q15 sequences. * @param[in] *pSrcA points to the first input sequence. * @param[in] srcALen length of the first input sequence. @@ -3076,18 +3017,16 @@ void arm_rfft_fast_f32( * @return none. */ + void arm_conv_opt_q15( + q15_t *pSrcA, + uint32_t srcALen, + q15_t *pSrcB, + uint32_t srcBLen, + q15_t *pDst, + q15_t *pScratch1, + q15_t *pScratch2); - void arm_conv_opt_q15( - q15_t * pSrcA, - uint32_t srcALen, - q15_t * pSrcB, - uint32_t srcBLen, - q15_t * pDst, - q15_t * pScratch1, - q15_t * pScratch2); - - -/** + /** * @brief Convolution of Q15 sequences. * @param[in] *pSrcA points to the first input sequence. * @param[in] srcALen length of the first input sequence. @@ -3097,14 +3036,14 @@ void arm_rfft_fast_f32( * @return none. */ - void arm_conv_q15( - q15_t * pSrcA, - uint32_t srcALen, - q15_t * pSrcB, - uint32_t srcBLen, - q15_t * pDst); + void arm_conv_q15( + q15_t *pSrcA, + uint32_t srcALen, + q15_t *pSrcB, + uint32_t srcBLen, + q15_t *pDst); - /** + /** * @brief Convolution of Q15 sequences (fast version) for Cortex-M3 and Cortex-M4 * @param[in] *pSrcA points to the first input sequence. * @param[in] srcALen length of the first input sequence. @@ -3114,14 +3053,14 @@ void arm_rfft_fast_f32( * @return none. */ - void arm_conv_fast_q15( - q15_t * pSrcA, - uint32_t srcALen, - q15_t * pSrcB, - uint32_t srcBLen, - q15_t * pDst); + void arm_conv_fast_q15( + q15_t *pSrcA, + uint32_t srcALen, + q15_t *pSrcB, + uint32_t srcBLen, + q15_t *pDst); - /** + /** * @brief Convolution of Q15 sequences (fast version) for Cortex-M3 and Cortex-M4 * @param[in] *pSrcA points to the first input sequence. * @param[in] srcALen length of the first input sequence. @@ -3133,18 +3072,16 @@ void arm_rfft_fast_f32( * @return none. */ - void arm_conv_fast_opt_q15( - q15_t * pSrcA, - uint32_t srcALen, - q15_t * pSrcB, - uint32_t srcBLen, - q15_t * pDst, - q15_t * pScratch1, - q15_t * pScratch2); - + void arm_conv_fast_opt_q15( + q15_t *pSrcA, + uint32_t srcALen, + q15_t *pSrcB, + uint32_t srcBLen, + q15_t *pDst, + q15_t *pScratch1, + q15_t *pScratch2); - - /** + /** * @brief Convolution of Q31 sequences. * @param[in] *pSrcA points to the first input sequence. * @param[in] srcALen length of the first input sequence. @@ -3154,14 +3091,14 @@ void arm_rfft_fast_f32( * @return none. */ - void arm_conv_q31( - q31_t * pSrcA, - uint32_t srcALen, - q31_t * pSrcB, - uint32_t srcBLen, - q31_t * pDst); + void arm_conv_q31( + q31_t *pSrcA, + uint32_t srcALen, + q31_t *pSrcB, + uint32_t srcBLen, + q31_t *pDst); - /** + /** * @brief Convolution of Q31 sequences (fast version) for Cortex-M3 and Cortex-M4 * @param[in] *pSrcA points to the first input sequence. * @param[in] srcALen length of the first input sequence. @@ -3171,13 +3108,12 @@ void arm_rfft_fast_f32( * @return none. */ - void arm_conv_fast_q31( - q31_t * pSrcA, - uint32_t srcALen, - q31_t * pSrcB, - uint32_t srcBLen, - q31_t * pDst); - + void arm_conv_fast_q31( + q31_t *pSrcA, + uint32_t srcALen, + q31_t *pSrcB, + uint32_t srcBLen, + q31_t *pDst); /** * @brief Convolution of Q7 sequences. @@ -3191,18 +3127,16 @@ void arm_rfft_fast_f32( * @return none. */ - void arm_conv_opt_q7( - q7_t * pSrcA, - uint32_t srcALen, - q7_t * pSrcB, - uint32_t srcBLen, - q7_t * pDst, - q15_t * pScratch1, - q15_t * pScratch2); - - + void arm_conv_opt_q7( + q7_t *pSrcA, + uint32_t srcALen, + q7_t *pSrcB, + uint32_t srcBLen, + q7_t *pDst, + q15_t *pScratch1, + q15_t *pScratch2); - /** + /** * @brief Convolution of Q7 sequences. * @param[in] *pSrcA points to the first input sequence. * @param[in] srcALen length of the first input sequence. @@ -3212,15 +3146,14 @@ void arm_rfft_fast_f32( * @return none. */ - void arm_conv_q7( - q7_t * pSrcA, - uint32_t srcALen, - q7_t * pSrcB, - uint32_t srcBLen, - q7_t * pDst); - + void arm_conv_q7( + q7_t *pSrcA, + uint32_t srcALen, + q7_t *pSrcB, + uint32_t srcBLen, + q7_t *pDst); - /** + /** * @brief Partial convolution of floating-point sequences. * @param[in] *pSrcA points to the first input sequence. * @param[in] srcALen length of the first input sequence. @@ -3232,14 +3165,14 @@ void arm_rfft_fast_f32( * @return Returns either ARM_MATH_SUCCESS if the function completed correctly or ARM_MATH_ARGUMENT_ERROR if the requested subset is not in the range [0 srcALen+srcBLen-2]. */ - arm_status arm_conv_partial_f32( - float32_t * pSrcA, - uint32_t srcALen, - float32_t * pSrcB, - uint32_t srcBLen, - float32_t * pDst, - uint32_t firstIndex, - uint32_t numPoints); + arm_status arm_conv_partial_f32( + float32_t *pSrcA, + uint32_t srcALen, + float32_t *pSrcB, + uint32_t srcBLen, + float32_t *pDst, + uint32_t firstIndex, + uint32_t numPoints); /** * @brief Partial convolution of Q15 sequences. @@ -3255,19 +3188,18 @@ void arm_rfft_fast_f32( * @return Returns either ARM_MATH_SUCCESS if the function completed correctly or ARM_MATH_ARGUMENT_ERROR if the requested subset is not in the range [0 srcALen+srcBLen-2]. */ - arm_status arm_conv_partial_opt_q15( - q15_t * pSrcA, - uint32_t srcALen, - q15_t * pSrcB, - uint32_t srcBLen, - q15_t * pDst, - uint32_t firstIndex, - uint32_t numPoints, - q15_t * pScratch1, - q15_t * pScratch2); - + arm_status arm_conv_partial_opt_q15( + q15_t *pSrcA, + uint32_t srcALen, + q15_t *pSrcB, + uint32_t srcBLen, + q15_t *pDst, + uint32_t firstIndex, + uint32_t numPoints, + q15_t *pScratch1, + q15_t *pScratch2); -/** + /** * @brief Partial convolution of Q15 sequences. * @param[in] *pSrcA points to the first input sequence. * @param[in] srcALen length of the first input sequence. @@ -3279,16 +3211,16 @@ void arm_rfft_fast_f32( * @return Returns either ARM_MATH_SUCCESS if the function completed correctly or ARM_MATH_ARGUMENT_ERROR if the requested subset is not in the range [0 srcALen+srcBLen-2]. */ - arm_status arm_conv_partial_q15( - q15_t * pSrcA, - uint32_t srcALen, - q15_t * pSrcB, - uint32_t srcBLen, - q15_t * pDst, - uint32_t firstIndex, - uint32_t numPoints); + arm_status arm_conv_partial_q15( + q15_t *pSrcA, + uint32_t srcALen, + q15_t *pSrcB, + uint32_t srcBLen, + q15_t *pDst, + uint32_t firstIndex, + uint32_t numPoints); - /** + /** * @brief Partial convolution of Q15 sequences (fast version) for Cortex-M3 and Cortex-M4 * @param[in] *pSrcA points to the first input sequence. * @param[in] srcALen length of the first input sequence. @@ -3300,17 +3232,16 @@ void arm_rfft_fast_f32( * @return Returns either ARM_MATH_SUCCESS if the function completed correctly or ARM_MATH_ARGUMENT_ERROR if the requested subset is not in the range [0 srcALen+srcBLen-2]. */ - arm_status arm_conv_partial_fast_q15( - q15_t * pSrcA, - uint32_t srcALen, - q15_t * pSrcB, - uint32_t srcBLen, - q15_t * pDst, - uint32_t firstIndex, - uint32_t numPoints); + arm_status arm_conv_partial_fast_q15( + q15_t *pSrcA, + uint32_t srcALen, + q15_t *pSrcB, + uint32_t srcBLen, + q15_t *pDst, + uint32_t firstIndex, + uint32_t numPoints); - - /** + /** * @brief Partial convolution of Q15 sequences (fast version) for Cortex-M3 and Cortex-M4 * @param[in] *pSrcA points to the first input sequence. * @param[in] srcALen length of the first input sequence. @@ -3324,19 +3255,18 @@ void arm_rfft_fast_f32( * @return Returns either ARM_MATH_SUCCESS if the function completed correctly or ARM_MATH_ARGUMENT_ERROR if the requested subset is not in the range [0 srcALen+srcBLen-2]. */ - arm_status arm_conv_partial_fast_opt_q15( - q15_t * pSrcA, - uint32_t srcALen, - q15_t * pSrcB, - uint32_t srcBLen, - q15_t * pDst, - uint32_t firstIndex, - uint32_t numPoints, - q15_t * pScratch1, - q15_t * pScratch2); - + arm_status arm_conv_partial_fast_opt_q15( + q15_t *pSrcA, + uint32_t srcALen, + q15_t *pSrcB, + uint32_t srcBLen, + q15_t *pDst, + uint32_t firstIndex, + uint32_t numPoints, + q15_t *pScratch1, + q15_t *pScratch2); - /** + /** * @brief Partial convolution of Q31 sequences. * @param[in] *pSrcA points to the first input sequence. * @param[in] srcALen length of the first input sequence. @@ -3348,17 +3278,16 @@ void arm_rfft_fast_f32( * @return Returns either ARM_MATH_SUCCESS if the function completed correctly or ARM_MATH_ARGUMENT_ERROR if the requested subset is not in the range [0 srcALen+srcBLen-2]. */ - arm_status arm_conv_partial_q31( - q31_t * pSrcA, - uint32_t srcALen, - q31_t * pSrcB, - uint32_t srcBLen, - q31_t * pDst, - uint32_t firstIndex, - uint32_t numPoints); - + arm_status arm_conv_partial_q31( + q31_t *pSrcA, + uint32_t srcALen, + q31_t *pSrcB, + uint32_t srcBLen, + q31_t *pDst, + uint32_t firstIndex, + uint32_t numPoints); - /** + /** * @brief Partial convolution of Q31 sequences (fast version) for Cortex-M3 and Cortex-M4 * @param[in] *pSrcA points to the first input sequence. * @param[in] srcALen length of the first input sequence. @@ -3370,17 +3299,16 @@ void arm_rfft_fast_f32( * @return Returns either ARM_MATH_SUCCESS if the function completed correctly or ARM_MATH_ARGUMENT_ERROR if the requested subset is not in the range [0 srcALen+srcBLen-2]. */ - arm_status arm_conv_partial_fast_q31( - q31_t * pSrcA, - uint32_t srcALen, - q31_t * pSrcB, - uint32_t srcBLen, - q31_t * pDst, - uint32_t firstIndex, - uint32_t numPoints); + arm_status arm_conv_partial_fast_q31( + q31_t *pSrcA, + uint32_t srcALen, + q31_t *pSrcB, + uint32_t srcBLen, + q31_t *pDst, + uint32_t firstIndex, + uint32_t numPoints); - - /** + /** * @brief Partial convolution of Q7 sequences * @param[in] *pSrcA points to the first input sequence. * @param[in] srcALen length of the first input sequence. @@ -3394,19 +3322,18 @@ void arm_rfft_fast_f32( * @return Returns either ARM_MATH_SUCCESS if the function completed correctly or ARM_MATH_ARGUMENT_ERROR if the requested subset is not in the range [0 srcALen+srcBLen-2]. */ - arm_status arm_conv_partial_opt_q7( - q7_t * pSrcA, - uint32_t srcALen, - q7_t * pSrcB, - uint32_t srcBLen, - q7_t * pDst, - uint32_t firstIndex, - uint32_t numPoints, - q15_t * pScratch1, - q15_t * pScratch2); + arm_status arm_conv_partial_opt_q7( + q7_t *pSrcA, + uint32_t srcALen, + q7_t *pSrcB, + uint32_t srcBLen, + q7_t *pDst, + uint32_t firstIndex, + uint32_t numPoints, + q15_t *pScratch1, + q15_t *pScratch2); - -/** + /** * @brief Partial convolution of Q7 sequences. * @param[in] *pSrcA points to the first input sequence. * @param[in] srcALen length of the first input sequence. @@ -3418,58 +3345,54 @@ void arm_rfft_fast_f32( * @return Returns either ARM_MATH_SUCCESS if the function completed correctly or ARM_MATH_ARGUMENT_ERROR if the requested subset is not in the range [0 srcALen+srcBLen-2]. */ - arm_status arm_conv_partial_q7( - q7_t * pSrcA, - uint32_t srcALen, - q7_t * pSrcB, - uint32_t srcBLen, - q7_t * pDst, - uint32_t firstIndex, - uint32_t numPoints); - - + arm_status arm_conv_partial_q7( + q7_t *pSrcA, + uint32_t srcALen, + q7_t *pSrcB, + uint32_t srcBLen, + q7_t *pDst, + uint32_t firstIndex, + uint32_t numPoints); - /** + /** * @brief Instance structure for the Q15 FIR decimator. */ - typedef struct - { - uint8_t M; /**< decimation factor. */ - uint16_t numTaps; /**< number of coefficients in the filter. */ - q15_t *pCoeffs; /**< points to the coefficient array. The array is of length numTaps.*/ - q15_t *pState; /**< points to the state variable array. The array is of length numTaps+blockSize-1. */ - } arm_fir_decimate_instance_q15; + typedef struct + { + uint8_t M; /**< decimation factor. */ + uint16_t numTaps; /**< number of coefficients in the filter. */ + q15_t *pCoeffs; /**< points to the coefficient array. The array is of length numTaps.*/ + q15_t *pState; /**< points to the state variable array. The array is of length numTaps+blockSize-1. */ + } arm_fir_decimate_instance_q15; - /** + /** * @brief Instance structure for the Q31 FIR decimator. */ - typedef struct - { - uint8_t M; /**< decimation factor. */ - uint16_t numTaps; /**< number of coefficients in the filter. */ - q31_t *pCoeffs; /**< points to the coefficient array. The array is of length numTaps.*/ - q31_t *pState; /**< points to the state variable array. The array is of length numTaps+blockSize-1. */ + typedef struct + { + uint8_t M; /**< decimation factor. */ + uint16_t numTaps; /**< number of coefficients in the filter. */ + q31_t *pCoeffs; /**< points to the coefficient array. The array is of length numTaps.*/ + q31_t *pState; /**< points to the state variable array. The array is of length numTaps+blockSize-1. */ - } arm_fir_decimate_instance_q31; + } arm_fir_decimate_instance_q31; - /** + /** * @brief Instance structure for the floating-point FIR decimator. */ - typedef struct - { - uint8_t M; /**< decimation factor. */ - uint16_t numTaps; /**< number of coefficients in the filter. */ - float32_t *pCoeffs; /**< points to the coefficient array. The array is of length numTaps.*/ - float32_t *pState; /**< points to the state variable array. The array is of length numTaps+blockSize-1. */ - - } arm_fir_decimate_instance_f32; - + typedef struct + { + uint8_t M; /**< decimation factor. */ + uint16_t numTaps; /**< number of coefficients in the filter. */ + float32_t *pCoeffs; /**< points to the coefficient array. The array is of length numTaps.*/ + float32_t *pState; /**< points to the state variable array. The array is of length numTaps+blockSize-1. */ + } arm_fir_decimate_instance_f32; - /** + /** * @brief Processing function for the floating-point FIR decimator. * @param[in] *S points to an instance of the floating-point FIR decimator structure. * @param[in] *pSrc points to the block of input data. @@ -3478,14 +3401,13 @@ void arm_rfft_fast_f32( * @return none */ - void arm_fir_decimate_f32( - const arm_fir_decimate_instance_f32 * S, - float32_t * pSrc, - float32_t * pDst, - uint32_t blockSize); - + void arm_fir_decimate_f32( + const arm_fir_decimate_instance_f32 *S, + float32_t *pSrc, + float32_t *pDst, + uint32_t blockSize); - /** + /** * @brief Initialization function for the floating-point FIR decimator. * @param[in,out] *S points to an instance of the floating-point FIR decimator structure. * @param[in] numTaps number of coefficients in the filter. @@ -3497,15 +3419,15 @@ void arm_rfft_fast_f32( * <code>blockSize</code> is not a multiple of <code>M</code>. */ - arm_status arm_fir_decimate_init_f32( - arm_fir_decimate_instance_f32 * S, - uint16_t numTaps, - uint8_t M, - float32_t * pCoeffs, - float32_t * pState, - uint32_t blockSize); + arm_status arm_fir_decimate_init_f32( + arm_fir_decimate_instance_f32 *S, + uint16_t numTaps, + uint8_t M, + float32_t *pCoeffs, + float32_t *pState, + uint32_t blockSize); - /** + /** * @brief Processing function for the Q15 FIR decimator. * @param[in] *S points to an instance of the Q15 FIR decimator structure. * @param[in] *pSrc points to the block of input data. @@ -3514,13 +3436,13 @@ void arm_rfft_fast_f32( * @return none */ - void arm_fir_decimate_q15( - const arm_fir_decimate_instance_q15 * S, - q15_t * pSrc, - q15_t * pDst, - uint32_t blockSize); + void arm_fir_decimate_q15( + const arm_fir_decimate_instance_q15 *S, + q15_t *pSrc, + q15_t *pDst, + uint32_t blockSize); - /** + /** * @brief Processing function for the Q15 FIR decimator (fast variant) for Cortex-M3 and Cortex-M4. * @param[in] *S points to an instance of the Q15 FIR decimator structure. * @param[in] *pSrc points to the block of input data. @@ -3529,15 +3451,13 @@ void arm_rfft_fast_f32( * @return none */ - void arm_fir_decimate_fast_q15( - const arm_fir_decimate_instance_q15 * S, - q15_t * pSrc, - q15_t * pDst, - uint32_t blockSize); + void arm_fir_decimate_fast_q15( + const arm_fir_decimate_instance_q15 *S, + q15_t *pSrc, + q15_t *pDst, + uint32_t blockSize); - - - /** + /** * @brief Initialization function for the Q15 FIR decimator. * @param[in,out] *S points to an instance of the Q15 FIR decimator structure. * @param[in] numTaps number of coefficients in the filter. @@ -3549,15 +3469,15 @@ void arm_rfft_fast_f32( * <code>blockSize</code> is not a multiple of <code>M</code>. */ - arm_status arm_fir_decimate_init_q15( - arm_fir_decimate_instance_q15 * S, - uint16_t numTaps, - uint8_t M, - q15_t * pCoeffs, - q15_t * pState, - uint32_t blockSize); + arm_status arm_fir_decimate_init_q15( + arm_fir_decimate_instance_q15 *S, + uint16_t numTaps, + uint8_t M, + q15_t *pCoeffs, + q15_t *pState, + uint32_t blockSize); - /** + /** * @brief Processing function for the Q31 FIR decimator. * @param[in] *S points to an instance of the Q31 FIR decimator structure. * @param[in] *pSrc points to the block of input data. @@ -3566,13 +3486,13 @@ void arm_rfft_fast_f32( * @return none */ - void arm_fir_decimate_q31( - const arm_fir_decimate_instance_q31 * S, - q31_t * pSrc, - q31_t * pDst, - uint32_t blockSize); + void arm_fir_decimate_q31( + const arm_fir_decimate_instance_q31 *S, + q31_t *pSrc, + q31_t *pDst, + uint32_t blockSize); - /** + /** * @brief Processing function for the Q31 FIR decimator (fast variant) for Cortex-M3 and Cortex-M4. * @param[in] *S points to an instance of the Q31 FIR decimator structure. * @param[in] *pSrc points to the block of input data. @@ -3581,14 +3501,13 @@ void arm_rfft_fast_f32( * @return none */ - void arm_fir_decimate_fast_q31( - arm_fir_decimate_instance_q31 * S, - q31_t * pSrc, - q31_t * pDst, - uint32_t blockSize); - + void arm_fir_decimate_fast_q31( + arm_fir_decimate_instance_q31 *S, + q31_t *pSrc, + q31_t *pDst, + uint32_t blockSize); - /** + /** * @brief Initialization function for the Q31 FIR decimator. * @param[in,out] *S points to an instance of the Q31 FIR decimator structure. * @param[in] numTaps number of coefficients in the filter. @@ -3600,54 +3519,51 @@ void arm_rfft_fast_f32( * <code>blockSize</code> is not a multiple of <code>M</code>. */ - arm_status arm_fir_decimate_init_q31( - arm_fir_decimate_instance_q31 * S, - uint16_t numTaps, - uint8_t M, - q31_t * pCoeffs, - q31_t * pState, - uint32_t blockSize); - + arm_status arm_fir_decimate_init_q31( + arm_fir_decimate_instance_q31 *S, + uint16_t numTaps, + uint8_t M, + q31_t *pCoeffs, + q31_t *pState, + uint32_t blockSize); - - /** + /** * @brief Instance structure for the Q15 FIR interpolator. */ - typedef struct - { - uint8_t L; /**< upsample factor. */ - uint16_t phaseLength; /**< length of each polyphase filter component. */ - q15_t *pCoeffs; /**< points to the coefficient array. The array is of length L*phaseLength. */ - q15_t *pState; /**< points to the state variable array. The array is of length blockSize+phaseLength-1. */ - } arm_fir_interpolate_instance_q15; + typedef struct + { + uint8_t L; /**< upsample factor. */ + uint16_t phaseLength; /**< length of each polyphase filter component. */ + q15_t *pCoeffs; /**< points to the coefficient array. The array is of length L*phaseLength. */ + q15_t *pState; /**< points to the state variable array. The array is of length blockSize+phaseLength-1. */ + } arm_fir_interpolate_instance_q15; - /** + /** * @brief Instance structure for the Q31 FIR interpolator. */ - typedef struct - { - uint8_t L; /**< upsample factor. */ - uint16_t phaseLength; /**< length of each polyphase filter component. */ - q31_t *pCoeffs; /**< points to the coefficient array. The array is of length L*phaseLength. */ - q31_t *pState; /**< points to the state variable array. The array is of length blockSize+phaseLength-1. */ - } arm_fir_interpolate_instance_q31; + typedef struct + { + uint8_t L; /**< upsample factor. */ + uint16_t phaseLength; /**< length of each polyphase filter component. */ + q31_t *pCoeffs; /**< points to the coefficient array. The array is of length L*phaseLength. */ + q31_t *pState; /**< points to the state variable array. The array is of length blockSize+phaseLength-1. */ + } arm_fir_interpolate_instance_q31; - /** + /** * @brief Instance structure for the floating-point FIR interpolator. */ - typedef struct - { - uint8_t L; /**< upsample factor. */ - uint16_t phaseLength; /**< length of each polyphase filter component. */ - float32_t *pCoeffs; /**< points to the coefficient array. The array is of length L*phaseLength. */ - float32_t *pState; /**< points to the state variable array. The array is of length phaseLength+numTaps-1. */ - } arm_fir_interpolate_instance_f32; - + typedef struct + { + uint8_t L; /**< upsample factor. */ + uint16_t phaseLength; /**< length of each polyphase filter component. */ + float32_t *pCoeffs; /**< points to the coefficient array. The array is of length L*phaseLength. */ + float32_t *pState; /**< points to the state variable array. The array is of length phaseLength+numTaps-1. */ + } arm_fir_interpolate_instance_f32; - /** + /** * @brief Processing function for the Q15 FIR interpolator. * @param[in] *S points to an instance of the Q15 FIR interpolator structure. * @param[in] *pSrc points to the block of input data. @@ -3656,14 +3572,13 @@ void arm_rfft_fast_f32( * @return none. */ - void arm_fir_interpolate_q15( - const arm_fir_interpolate_instance_q15 * S, - q15_t * pSrc, - q15_t * pDst, - uint32_t blockSize); - + void arm_fir_interpolate_q15( + const arm_fir_interpolate_instance_q15 *S, + q15_t *pSrc, + q15_t *pDst, + uint32_t blockSize); - /** + /** * @brief Initialization function for the Q15 FIR interpolator. * @param[in,out] *S points to an instance of the Q15 FIR interpolator structure. * @param[in] L upsample factor. @@ -3675,15 +3590,15 @@ void arm_rfft_fast_f32( * the filter length <code>numTaps</code> is not a multiple of the interpolation factor <code>L</code>. */ - arm_status arm_fir_interpolate_init_q15( - arm_fir_interpolate_instance_q15 * S, - uint8_t L, - uint16_t numTaps, - q15_t * pCoeffs, - q15_t * pState, - uint32_t blockSize); + arm_status arm_fir_interpolate_init_q15( + arm_fir_interpolate_instance_q15 *S, + uint8_t L, + uint16_t numTaps, + q15_t *pCoeffs, + q15_t *pState, + uint32_t blockSize); - /** + /** * @brief Processing function for the Q31 FIR interpolator. * @param[in] *S points to an instance of the Q15 FIR interpolator structure. * @param[in] *pSrc points to the block of input data. @@ -3692,13 +3607,13 @@ void arm_rfft_fast_f32( * @return none. */ - void arm_fir_interpolate_q31( - const arm_fir_interpolate_instance_q31 * S, - q31_t * pSrc, - q31_t * pDst, - uint32_t blockSize); + void arm_fir_interpolate_q31( + const arm_fir_interpolate_instance_q31 *S, + q31_t *pSrc, + q31_t *pDst, + uint32_t blockSize); - /** + /** * @brief Initialization function for the Q31 FIR interpolator. * @param[in,out] *S points to an instance of the Q31 FIR interpolator structure. * @param[in] L upsample factor. @@ -3710,16 +3625,15 @@ void arm_rfft_fast_f32( * the filter length <code>numTaps</code> is not a multiple of the interpolation factor <code>L</code>. */ - arm_status arm_fir_interpolate_init_q31( - arm_fir_interpolate_instance_q31 * S, - uint8_t L, - uint16_t numTaps, - q31_t * pCoeffs, - q31_t * pState, - uint32_t blockSize); + arm_status arm_fir_interpolate_init_q31( + arm_fir_interpolate_instance_q31 *S, + uint8_t L, + uint16_t numTaps, + q31_t *pCoeffs, + q31_t *pState, + uint32_t blockSize); - - /** + /** * @brief Processing function for the floating-point FIR interpolator. * @param[in] *S points to an instance of the floating-point FIR interpolator structure. * @param[in] *pSrc points to the block of input data. @@ -3728,13 +3642,13 @@ void arm_rfft_fast_f32( * @return none. */ - void arm_fir_interpolate_f32( - const arm_fir_interpolate_instance_f32 * S, - float32_t * pSrc, - float32_t * pDst, - uint32_t blockSize); + void arm_fir_interpolate_f32( + const arm_fir_interpolate_instance_f32 *S, + float32_t *pSrc, + float32_t *pDst, + uint32_t blockSize); - /** + /** * @brief Initialization function for the floating-point FIR interpolator. * @param[in,out] *S points to an instance of the floating-point FIR interpolator structure. * @param[in] L upsample factor. @@ -3746,29 +3660,28 @@ void arm_rfft_fast_f32( * the filter length <code>numTaps</code> is not a multiple of the interpolation factor <code>L</code>. */ - arm_status arm_fir_interpolate_init_f32( - arm_fir_interpolate_instance_f32 * S, - uint8_t L, - uint16_t numTaps, - float32_t * pCoeffs, - float32_t * pState, - uint32_t blockSize); + arm_status arm_fir_interpolate_init_f32( + arm_fir_interpolate_instance_f32 *S, + uint8_t L, + uint16_t numTaps, + float32_t *pCoeffs, + float32_t *pState, + uint32_t blockSize); - /** + /** * @brief Instance structure for the high precision Q31 Biquad cascade filter. */ - typedef struct - { - uint8_t numStages; /**< number of 2nd order stages in the filter. Overall order is 2*numStages. */ - q63_t *pState; /**< points to the array of state coefficients. The array is of length 4*numStages. */ - q31_t *pCoeffs; /**< points to the array of coefficients. The array is of length 5*numStages. */ - uint8_t postShift; /**< additional shift, in bits, applied to each output sample. */ - - } arm_biquad_cas_df1_32x64_ins_q31; + typedef struct + { + uint8_t numStages; /**< number of 2nd order stages in the filter. Overall order is 2*numStages. */ + q63_t *pState; /**< points to the array of state coefficients. The array is of length 4*numStages. */ + q31_t *pCoeffs; /**< points to the array of coefficients. The array is of length 5*numStages. */ + uint8_t postShift; /**< additional shift, in bits, applied to each output sample. */ + } arm_biquad_cas_df1_32x64_ins_q31; - /** + /** * @param[in] *S points to an instance of the high precision Q31 Biquad cascade filter structure. * @param[in] *pSrc points to the block of input data. * @param[out] *pDst points to the block of output data @@ -3776,14 +3689,13 @@ void arm_rfft_fast_f32( * @return none. */ - void arm_biquad_cas_df1_32x64_q31( - const arm_biquad_cas_df1_32x64_ins_q31 * S, - q31_t * pSrc, - q31_t * pDst, - uint32_t blockSize); - + void arm_biquad_cas_df1_32x64_q31( + const arm_biquad_cas_df1_32x64_ins_q31 *S, + q31_t *pSrc, + q31_t *pDst, + uint32_t blockSize); - /** + /** * @param[in,out] *S points to an instance of the high precision Q31 Biquad cascade filter structure. * @param[in] numStages number of 2nd order stages in the filter. * @param[in] *pCoeffs points to the filter coefficients. @@ -3792,54 +3704,47 @@ void arm_rfft_fast_f32( * @return none */ - void arm_biquad_cas_df1_32x64_init_q31( - arm_biquad_cas_df1_32x64_ins_q31 * S, - uint8_t numStages, - q31_t * pCoeffs, - q63_t * pState, - uint8_t postShift); - - + void arm_biquad_cas_df1_32x64_init_q31( + arm_biquad_cas_df1_32x64_ins_q31 *S, + uint8_t numStages, + q31_t *pCoeffs, + q63_t *pState, + uint8_t postShift); - /** + /** * @brief Instance structure for the floating-point transposed direct form II Biquad cascade filter. */ - typedef struct - { - uint8_t numStages; /**< number of 2nd order stages in the filter. Overall order is 2*numStages. */ - float32_t *pState; /**< points to the array of state coefficients. The array is of length 2*numStages. */ - float32_t *pCoeffs; /**< points to the array of coefficients. The array is of length 5*numStages. */ - } arm_biquad_cascade_df2T_instance_f32; - - + typedef struct + { + uint8_t numStages; /**< number of 2nd order stages in the filter. Overall order is 2*numStages. */ + float32_t *pState; /**< points to the array of state coefficients. The array is of length 2*numStages. */ + float32_t *pCoeffs; /**< points to the array of coefficients. The array is of length 5*numStages. */ + } arm_biquad_cascade_df2T_instance_f32; - /** + /** * @brief Instance structure for the floating-point transposed direct form II Biquad cascade filter. */ - typedef struct - { - uint8_t numStages; /**< number of 2nd order stages in the filter. Overall order is 2*numStages. */ - float32_t *pState; /**< points to the array of state coefficients. The array is of length 4*numStages. */ - float32_t *pCoeffs; /**< points to the array of coefficients. The array is of length 5*numStages. */ - } arm_biquad_cascade_stereo_df2T_instance_f32; - - + typedef struct + { + uint8_t numStages; /**< number of 2nd order stages in the filter. Overall order is 2*numStages. */ + float32_t *pState; /**< points to the array of state coefficients. The array is of length 4*numStages. */ + float32_t *pCoeffs; /**< points to the array of coefficients. The array is of length 5*numStages. */ + } arm_biquad_cascade_stereo_df2T_instance_f32; - /** + /** * @brief Instance structure for the floating-point transposed direct form II Biquad cascade filter. */ - typedef struct - { - uint8_t numStages; /**< number of 2nd order stages in the filter. Overall order is 2*numStages. */ - float64_t *pState; /**< points to the array of state coefficients. The array is of length 2*numStages. */ - float64_t *pCoeffs; /**< points to the array of coefficients. The array is of length 5*numStages. */ - } arm_biquad_cascade_df2T_instance_f64; - + typedef struct + { + uint8_t numStages; /**< number of 2nd order stages in the filter. Overall order is 2*numStages. */ + float64_t *pState; /**< points to the array of state coefficients. The array is of length 2*numStages. */ + float64_t *pCoeffs; /**< points to the array of coefficients. The array is of length 5*numStages. */ + } arm_biquad_cascade_df2T_instance_f64; - /** + /** * @brief Processing function for the floating-point transposed direct form II Biquad cascade filter. * @param[in] *S points to an instance of the filter data structure. * @param[in] *pSrc points to the block of input data. @@ -3848,14 +3753,13 @@ void arm_rfft_fast_f32( * @return none. */ - void arm_biquad_cascade_df2T_f32( - const arm_biquad_cascade_df2T_instance_f32 * S, - float32_t * pSrc, - float32_t * pDst, - uint32_t blockSize); - + void arm_biquad_cascade_df2T_f32( + const arm_biquad_cascade_df2T_instance_f32 *S, + float32_t *pSrc, + float32_t *pDst, + uint32_t blockSize); - /** + /** * @brief Processing function for the floating-point transposed direct form II Biquad cascade filter. 2 channels * @param[in] *S points to an instance of the filter data structure. * @param[in] *pSrc points to the block of input data. @@ -3864,13 +3768,13 @@ void arm_rfft_fast_f32( * @return none. */ - void arm_biquad_cascade_stereo_df2T_f32( - const arm_biquad_cascade_stereo_df2T_instance_f32 * S, - float32_t * pSrc, - float32_t * pDst, - uint32_t blockSize); + void arm_biquad_cascade_stereo_df2T_f32( + const arm_biquad_cascade_stereo_df2T_instance_f32 *S, + float32_t *pSrc, + float32_t *pDst, + uint32_t blockSize); - /** + /** * @brief Processing function for the floating-point transposed direct form II Biquad cascade filter. * @param[in] *S points to an instance of the filter data structure. * @param[in] *pSrc points to the block of input data. @@ -3879,14 +3783,13 @@ void arm_rfft_fast_f32( * @return none. */ - void arm_biquad_cascade_df2T_f64( - const arm_biquad_cascade_df2T_instance_f64 * S, - float64_t * pSrc, - float64_t * pDst, - uint32_t blockSize); + void arm_biquad_cascade_df2T_f64( + const arm_biquad_cascade_df2T_instance_f64 *S, + float64_t *pSrc, + float64_t *pDst, + uint32_t blockSize); - - /** + /** * @brief Initialization function for the floating-point transposed direct form II Biquad cascade filter. * @param[in,out] *S points to an instance of the filter data structure. * @param[in] numStages number of 2nd order stages in the filter. @@ -3895,14 +3798,13 @@ void arm_rfft_fast_f32( * @return none */ - void arm_biquad_cascade_df2T_init_f32( - arm_biquad_cascade_df2T_instance_f32 * S, - uint8_t numStages, - float32_t * pCoeffs, - float32_t * pState); + void arm_biquad_cascade_df2T_init_f32( + arm_biquad_cascade_df2T_instance_f32 *S, + uint8_t numStages, + float32_t *pCoeffs, + float32_t *pState); - - /** + /** * @brief Initialization function for the floating-point transposed direct form II Biquad cascade filter. * @param[in,out] *S points to an instance of the filter data structure. * @param[in] numStages number of 2nd order stages in the filter. @@ -3911,14 +3813,13 @@ void arm_rfft_fast_f32( * @return none */ - void arm_biquad_cascade_stereo_df2T_init_f32( - arm_biquad_cascade_stereo_df2T_instance_f32 * S, - uint8_t numStages, - float32_t * pCoeffs, - float32_t * pState); - + void arm_biquad_cascade_stereo_df2T_init_f32( + arm_biquad_cascade_stereo_df2T_instance_f32 *S, + uint8_t numStages, + float32_t *pCoeffs, + float32_t *pState); - /** + /** * @brief Initialization function for the floating-point transposed direct form II Biquad cascade filter. * @param[in,out] *S points to an instance of the filter data structure. * @param[in] numStages number of 2nd order stages in the filter. @@ -3927,48 +3828,46 @@ void arm_rfft_fast_f32( * @return none */ - void arm_biquad_cascade_df2T_init_f64( - arm_biquad_cascade_df2T_instance_f64 * S, - uint8_t numStages, - float64_t * pCoeffs, - float64_t * pState); - + void arm_biquad_cascade_df2T_init_f64( + arm_biquad_cascade_df2T_instance_f64 *S, + uint8_t numStages, + float64_t *pCoeffs, + float64_t *pState); - - /** + /** * @brief Instance structure for the Q15 FIR lattice filter. */ - typedef struct - { - uint16_t numStages; /**< number of filter stages. */ - q15_t *pState; /**< points to the state variable array. The array is of length numStages. */ - q15_t *pCoeffs; /**< points to the coefficient array. The array is of length numStages. */ - } arm_fir_lattice_instance_q15; + typedef struct + { + uint16_t numStages; /**< number of filter stages. */ + q15_t *pState; /**< points to the state variable array. The array is of length numStages. */ + q15_t *pCoeffs; /**< points to the coefficient array. The array is of length numStages. */ + } arm_fir_lattice_instance_q15; - /** + /** * @brief Instance structure for the Q31 FIR lattice filter. */ - typedef struct - { - uint16_t numStages; /**< number of filter stages. */ - q31_t *pState; /**< points to the state variable array. The array is of length numStages. */ - q31_t *pCoeffs; /**< points to the coefficient array. The array is of length numStages. */ - } arm_fir_lattice_instance_q31; + typedef struct + { + uint16_t numStages; /**< number of filter stages. */ + q31_t *pState; /**< points to the state variable array. The array is of length numStages. */ + q31_t *pCoeffs; /**< points to the coefficient array. The array is of length numStages. */ + } arm_fir_lattice_instance_q31; - /** + /** * @brief Instance structure for the floating-point FIR lattice filter. */ - typedef struct - { - uint16_t numStages; /**< number of filter stages. */ - float32_t *pState; /**< points to the state variable array. The array is of length numStages. */ - float32_t *pCoeffs; /**< points to the coefficient array. The array is of length numStages. */ - } arm_fir_lattice_instance_f32; + typedef struct + { + uint16_t numStages; /**< number of filter stages. */ + float32_t *pState; /**< points to the state variable array. The array is of length numStages. */ + float32_t *pCoeffs; /**< points to the coefficient array. The array is of length numStages. */ + } arm_fir_lattice_instance_f32; - /** + /** * @brief Initialization function for the Q15 FIR lattice filter. * @param[in] *S points to an instance of the Q15 FIR lattice structure. * @param[in] numStages number of filter stages. @@ -3977,14 +3876,13 @@ void arm_rfft_fast_f32( * @return none. */ - void arm_fir_lattice_init_q15( - arm_fir_lattice_instance_q15 * S, - uint16_t numStages, - q15_t * pCoeffs, - q15_t * pState); - + void arm_fir_lattice_init_q15( + arm_fir_lattice_instance_q15 *S, + uint16_t numStages, + q15_t *pCoeffs, + q15_t *pState); - /** + /** * @brief Processing function for the Q15 FIR lattice filter. * @param[in] *S points to an instance of the Q15 FIR lattice structure. * @param[in] *pSrc points to the block of input data. @@ -3992,13 +3890,13 @@ void arm_rfft_fast_f32( * @param[in] blockSize number of samples to process. * @return none. */ - void arm_fir_lattice_q15( - const arm_fir_lattice_instance_q15 * S, - q15_t * pSrc, - q15_t * pDst, - uint32_t blockSize); + void arm_fir_lattice_q15( + const arm_fir_lattice_instance_q15 *S, + q15_t *pSrc, + q15_t *pDst, + uint32_t blockSize); - /** + /** * @brief Initialization function for the Q31 FIR lattice filter. * @param[in] *S points to an instance of the Q31 FIR lattice structure. * @param[in] numStages number of filter stages. @@ -4007,14 +3905,13 @@ void arm_rfft_fast_f32( * @return none. */ - void arm_fir_lattice_init_q31( - arm_fir_lattice_instance_q31 * S, - uint16_t numStages, - q31_t * pCoeffs, - q31_t * pState); - + void arm_fir_lattice_init_q31( + arm_fir_lattice_instance_q31 *S, + uint16_t numStages, + q31_t *pCoeffs, + q31_t *pState); - /** + /** * @brief Processing function for the Q31 FIR lattice filter. * @param[in] *S points to an instance of the Q31 FIR lattice structure. * @param[in] *pSrc points to the block of input data. @@ -4023,13 +3920,13 @@ void arm_rfft_fast_f32( * @return none. */ - void arm_fir_lattice_q31( - const arm_fir_lattice_instance_q31 * S, - q31_t * pSrc, - q31_t * pDst, - uint32_t blockSize); + void arm_fir_lattice_q31( + const arm_fir_lattice_instance_q31 *S, + q31_t *pSrc, + q31_t *pDst, + uint32_t blockSize); -/** + /** * @brief Initialization function for the floating-point FIR lattice filter. * @param[in] *S points to an instance of the floating-point FIR lattice structure. * @param[in] numStages number of filter stages. @@ -4038,13 +3935,13 @@ void arm_rfft_fast_f32( * @return none. */ - void arm_fir_lattice_init_f32( - arm_fir_lattice_instance_f32 * S, - uint16_t numStages, - float32_t * pCoeffs, - float32_t * pState); + void arm_fir_lattice_init_f32( + arm_fir_lattice_instance_f32 *S, + uint16_t numStages, + float32_t *pCoeffs, + float32_t *pState); - /** + /** * @brief Processing function for the floating-point FIR lattice filter. * @param[in] *S points to an instance of the floating-point FIR lattice structure. * @param[in] *pSrc points to the block of input data. @@ -4053,46 +3950,46 @@ void arm_rfft_fast_f32( * @return none. */ - void arm_fir_lattice_f32( - const arm_fir_lattice_instance_f32 * S, - float32_t * pSrc, - float32_t * pDst, - uint32_t blockSize); + void arm_fir_lattice_f32( + const arm_fir_lattice_instance_f32 *S, + float32_t *pSrc, + float32_t *pDst, + uint32_t blockSize); - /** + /** * @brief Instance structure for the Q15 IIR lattice filter. */ - typedef struct - { - uint16_t numStages; /**< number of stages in the filter. */ - q15_t *pState; /**< points to the state variable array. The array is of length numStages+blockSize. */ - q15_t *pkCoeffs; /**< points to the reflection coefficient array. The array is of length numStages. */ - q15_t *pvCoeffs; /**< points to the ladder coefficient array. The array is of length numStages+1. */ - } arm_iir_lattice_instance_q15; + typedef struct + { + uint16_t numStages; /**< number of stages in the filter. */ + q15_t *pState; /**< points to the state variable array. The array is of length numStages+blockSize. */ + q15_t *pkCoeffs; /**< points to the reflection coefficient array. The array is of length numStages. */ + q15_t *pvCoeffs; /**< points to the ladder coefficient array. The array is of length numStages+1. */ + } arm_iir_lattice_instance_q15; - /** + /** * @brief Instance structure for the Q31 IIR lattice filter. */ - typedef struct - { - uint16_t numStages; /**< number of stages in the filter. */ - q31_t *pState; /**< points to the state variable array. The array is of length numStages+blockSize. */ - q31_t *pkCoeffs; /**< points to the reflection coefficient array. The array is of length numStages. */ - q31_t *pvCoeffs; /**< points to the ladder coefficient array. The array is of length numStages+1. */ - } arm_iir_lattice_instance_q31; + typedef struct + { + uint16_t numStages; /**< number of stages in the filter. */ + q31_t *pState; /**< points to the state variable array. The array is of length numStages+blockSize. */ + q31_t *pkCoeffs; /**< points to the reflection coefficient array. The array is of length numStages. */ + q31_t *pvCoeffs; /**< points to the ladder coefficient array. The array is of length numStages+1. */ + } arm_iir_lattice_instance_q31; - /** + /** * @brief Instance structure for the floating-point IIR lattice filter. */ - typedef struct - { - uint16_t numStages; /**< number of stages in the filter. */ - float32_t *pState; /**< points to the state variable array. The array is of length numStages+blockSize. */ - float32_t *pkCoeffs; /**< points to the reflection coefficient array. The array is of length numStages. */ - float32_t *pvCoeffs; /**< points to the ladder coefficient array. The array is of length numStages+1. */ - } arm_iir_lattice_instance_f32; + typedef struct + { + uint16_t numStages; /**< number of stages in the filter. */ + float32_t *pState; /**< points to the state variable array. The array is of length numStages+blockSize. */ + float32_t *pkCoeffs; /**< points to the reflection coefficient array. The array is of length numStages. */ + float32_t *pvCoeffs; /**< points to the ladder coefficient array. The array is of length numStages+1. */ + } arm_iir_lattice_instance_f32; - /** + /** * @brief Processing function for the floating-point IIR lattice filter. * @param[in] *S points to an instance of the floating-point IIR lattice structure. * @param[in] *pSrc points to the block of input data. @@ -4101,13 +3998,13 @@ void arm_rfft_fast_f32( * @return none. */ - void arm_iir_lattice_f32( - const arm_iir_lattice_instance_f32 * S, - float32_t * pSrc, - float32_t * pDst, - uint32_t blockSize); + void arm_iir_lattice_f32( + const arm_iir_lattice_instance_f32 *S, + float32_t *pSrc, + float32_t *pDst, + uint32_t blockSize); - /** + /** * @brief Initialization function for the floating-point IIR lattice filter. * @param[in] *S points to an instance of the floating-point IIR lattice structure. * @param[in] numStages number of stages in the filter. @@ -4118,16 +4015,15 @@ void arm_rfft_fast_f32( * @return none. */ - void arm_iir_lattice_init_f32( - arm_iir_lattice_instance_f32 * S, - uint16_t numStages, - float32_t * pkCoeffs, - float32_t * pvCoeffs, - float32_t * pState, - uint32_t blockSize); - + void arm_iir_lattice_init_f32( + arm_iir_lattice_instance_f32 *S, + uint16_t numStages, + float32_t *pkCoeffs, + float32_t *pvCoeffs, + float32_t *pState, + uint32_t blockSize); - /** + /** * @brief Processing function for the Q31 IIR lattice filter. * @param[in] *S points to an instance of the Q31 IIR lattice structure. * @param[in] *pSrc points to the block of input data. @@ -4136,14 +4032,13 @@ void arm_rfft_fast_f32( * @return none. */ - void arm_iir_lattice_q31( - const arm_iir_lattice_instance_q31 * S, - q31_t * pSrc, - q31_t * pDst, - uint32_t blockSize); - + void arm_iir_lattice_q31( + const arm_iir_lattice_instance_q31 *S, + q31_t *pSrc, + q31_t *pDst, + uint32_t blockSize); - /** + /** * @brief Initialization function for the Q31 IIR lattice filter. * @param[in] *S points to an instance of the Q31 IIR lattice structure. * @param[in] numStages number of stages in the filter. @@ -4154,16 +4049,15 @@ void arm_rfft_fast_f32( * @return none. */ - void arm_iir_lattice_init_q31( - arm_iir_lattice_instance_q31 * S, - uint16_t numStages, - q31_t * pkCoeffs, - q31_t * pvCoeffs, - q31_t * pState, - uint32_t blockSize); + void arm_iir_lattice_init_q31( + arm_iir_lattice_instance_q31 *S, + uint16_t numStages, + q31_t *pkCoeffs, + q31_t *pvCoeffs, + q31_t *pState, + uint32_t blockSize); - - /** + /** * @brief Processing function for the Q15 IIR lattice filter. * @param[in] *S points to an instance of the Q15 IIR lattice structure. * @param[in] *pSrc points to the block of input data. @@ -4172,14 +4066,13 @@ void arm_rfft_fast_f32( * @return none. */ - void arm_iir_lattice_q15( - const arm_iir_lattice_instance_q15 * S, - q15_t * pSrc, - q15_t * pDst, - uint32_t blockSize); - + void arm_iir_lattice_q15( + const arm_iir_lattice_instance_q15 *S, + q15_t *pSrc, + q15_t *pDst, + uint32_t blockSize); -/** + /** * @brief Initialization function for the Q15 IIR lattice filter. * @param[in] *S points to an instance of the fixed-point Q15 IIR lattice structure. * @param[in] numStages number of stages in the filter. @@ -4190,27 +4083,27 @@ void arm_rfft_fast_f32( * @return none. */ - void arm_iir_lattice_init_q15( - arm_iir_lattice_instance_q15 * S, - uint16_t numStages, - q15_t * pkCoeffs, - q15_t * pvCoeffs, - q15_t * pState, - uint32_t blockSize); + void arm_iir_lattice_init_q15( + arm_iir_lattice_instance_q15 *S, + uint16_t numStages, + q15_t *pkCoeffs, + q15_t *pvCoeffs, + q15_t *pState, + uint32_t blockSize); - /** + /** * @brief Instance structure for the floating-point LMS filter. */ - typedef struct - { - uint16_t numTaps; /**< number of coefficients in the filter. */ - float32_t *pState; /**< points to the state variable array. The array is of length numTaps+blockSize-1. */ - float32_t *pCoeffs; /**< points to the coefficient array. The array is of length numTaps. */ - float32_t mu; /**< step size that controls filter coefficient updates. */ - } arm_lms_instance_f32; + typedef struct + { + uint16_t numTaps; /**< number of coefficients in the filter. */ + float32_t *pState; /**< points to the state variable array. The array is of length numTaps+blockSize-1. */ + float32_t *pCoeffs; /**< points to the coefficient array. The array is of length numTaps. */ + float32_t mu; /**< step size that controls filter coefficient updates. */ + } arm_lms_instance_f32; - /** + /** * @brief Processing function for floating-point LMS filter. * @param[in] *S points to an instance of the floating-point LMS filter structure. * @param[in] *pSrc points to the block of input data. @@ -4221,15 +4114,15 @@ void arm_rfft_fast_f32( * @return none. */ - void arm_lms_f32( - const arm_lms_instance_f32 * S, - float32_t * pSrc, - float32_t * pRef, - float32_t * pOut, - float32_t * pErr, - uint32_t blockSize); + void arm_lms_f32( + const arm_lms_instance_f32 *S, + float32_t *pSrc, + float32_t *pRef, + float32_t *pOut, + float32_t *pErr, + uint32_t blockSize); - /** + /** * @brief Initialization function for floating-point LMS filter. * @param[in] *S points to an instance of the floating-point LMS filter structure. * @param[in] numTaps number of filter coefficients. @@ -4240,29 +4133,28 @@ void arm_rfft_fast_f32( * @return none. */ - void arm_lms_init_f32( - arm_lms_instance_f32 * S, - uint16_t numTaps, - float32_t * pCoeffs, - float32_t * pState, - float32_t mu, - uint32_t blockSize); + void arm_lms_init_f32( + arm_lms_instance_f32 *S, + uint16_t numTaps, + float32_t *pCoeffs, + float32_t *pState, + float32_t mu, + uint32_t blockSize); - /** + /** * @brief Instance structure for the Q15 LMS filter. */ - typedef struct - { - uint16_t numTaps; /**< number of coefficients in the filter. */ - q15_t *pState; /**< points to the state variable array. The array is of length numTaps+blockSize-1. */ - q15_t *pCoeffs; /**< points to the coefficient array. The array is of length numTaps. */ - q15_t mu; /**< step size that controls filter coefficient updates. */ - uint32_t postShift; /**< bit shift applied to coefficients. */ - } arm_lms_instance_q15; - + typedef struct + { + uint16_t numTaps; /**< number of coefficients in the filter. */ + q15_t *pState; /**< points to the state variable array. The array is of length numTaps+blockSize-1. */ + q15_t *pCoeffs; /**< points to the coefficient array. The array is of length numTaps. */ + q15_t mu; /**< step size that controls filter coefficient updates. */ + uint32_t postShift; /**< bit shift applied to coefficients. */ + } arm_lms_instance_q15; - /** + /** * @brief Initialization function for the Q15 LMS filter. * @param[in] *S points to an instance of the Q15 LMS filter structure. * @param[in] numTaps number of filter coefficients. @@ -4274,16 +4166,16 @@ void arm_rfft_fast_f32( * @return none. */ - void arm_lms_init_q15( - arm_lms_instance_q15 * S, - uint16_t numTaps, - q15_t * pCoeffs, - q15_t * pState, - q15_t mu, - uint32_t blockSize, - uint32_t postShift); + void arm_lms_init_q15( + arm_lms_instance_q15 *S, + uint16_t numTaps, + q15_t *pCoeffs, + q15_t *pState, + q15_t mu, + uint32_t blockSize, + uint32_t postShift); - /** + /** * @brief Processing function for Q15 LMS filter. * @param[in] *S points to an instance of the Q15 LMS filter structure. * @param[in] *pSrc points to the block of input data. @@ -4294,30 +4186,29 @@ void arm_rfft_fast_f32( * @return none. */ - void arm_lms_q15( - const arm_lms_instance_q15 * S, - q15_t * pSrc, - q15_t * pRef, - q15_t * pOut, - q15_t * pErr, - uint32_t blockSize); - + void arm_lms_q15( + const arm_lms_instance_q15 *S, + q15_t *pSrc, + q15_t *pRef, + q15_t *pOut, + q15_t *pErr, + uint32_t blockSize); - /** + /** * @brief Instance structure for the Q31 LMS filter. */ - typedef struct - { - uint16_t numTaps; /**< number of coefficients in the filter. */ - q31_t *pState; /**< points to the state variable array. The array is of length numTaps+blockSize-1. */ - q31_t *pCoeffs; /**< points to the coefficient array. The array is of length numTaps. */ - q31_t mu; /**< step size that controls filter coefficient updates. */ - uint32_t postShift; /**< bit shift applied to coefficients. */ + typedef struct + { + uint16_t numTaps; /**< number of coefficients in the filter. */ + q31_t *pState; /**< points to the state variable array. The array is of length numTaps+blockSize-1. */ + q31_t *pCoeffs; /**< points to the coefficient array. The array is of length numTaps. */ + q31_t mu; /**< step size that controls filter coefficient updates. */ + uint32_t postShift; /**< bit shift applied to coefficients. */ - } arm_lms_instance_q31; + } arm_lms_instance_q31; - /** + /** * @brief Processing function for Q31 LMS filter. * @param[in] *S points to an instance of the Q15 LMS filter structure. * @param[in] *pSrc points to the block of input data. @@ -4328,15 +4219,15 @@ void arm_rfft_fast_f32( * @return none. */ - void arm_lms_q31( - const arm_lms_instance_q31 * S, - q31_t * pSrc, - q31_t * pRef, - q31_t * pOut, - q31_t * pErr, - uint32_t blockSize); + void arm_lms_q31( + const arm_lms_instance_q31 *S, + q31_t *pSrc, + q31_t *pRef, + q31_t *pOut, + q31_t *pErr, + uint32_t blockSize); - /** + /** * @brief Initialization function for Q31 LMS filter. * @param[in] *S points to an instance of the Q31 LMS filter structure. * @param[in] numTaps number of filter coefficients. @@ -4348,30 +4239,30 @@ void arm_rfft_fast_f32( * @return none. */ - void arm_lms_init_q31( - arm_lms_instance_q31 * S, - uint16_t numTaps, - q31_t * pCoeffs, - q31_t * pState, - q31_t mu, - uint32_t blockSize, - uint32_t postShift); + void arm_lms_init_q31( + arm_lms_instance_q31 *S, + uint16_t numTaps, + q31_t *pCoeffs, + q31_t *pState, + q31_t mu, + uint32_t blockSize, + uint32_t postShift); - /** + /** * @brief Instance structure for the floating-point normalized LMS filter. */ - typedef struct - { - uint16_t numTaps; /**< number of coefficients in the filter. */ - float32_t *pState; /**< points to the state variable array. The array is of length numTaps+blockSize-1. */ - float32_t *pCoeffs; /**< points to the coefficient array. The array is of length numTaps. */ - float32_t mu; /**< step size that control filter coefficient updates. */ - float32_t energy; /**< saves previous frame energy. */ - float32_t x0; /**< saves previous input sample. */ - } arm_lms_norm_instance_f32; + typedef struct + { + uint16_t numTaps; /**< number of coefficients in the filter. */ + float32_t *pState; /**< points to the state variable array. The array is of length numTaps+blockSize-1. */ + float32_t *pCoeffs; /**< points to the coefficient array. The array is of length numTaps. */ + float32_t mu; /**< step size that control filter coefficient updates. */ + float32_t energy; /**< saves previous frame energy. */ + float32_t x0; /**< saves previous input sample. */ + } arm_lms_norm_instance_f32; - /** + /** * @brief Processing function for floating-point normalized LMS filter. * @param[in] *S points to an instance of the floating-point normalized LMS filter structure. * @param[in] *pSrc points to the block of input data. @@ -4382,15 +4273,15 @@ void arm_rfft_fast_f32( * @return none. */ - void arm_lms_norm_f32( - arm_lms_norm_instance_f32 * S, - float32_t * pSrc, - float32_t * pRef, - float32_t * pOut, - float32_t * pErr, - uint32_t blockSize); + void arm_lms_norm_f32( + arm_lms_norm_instance_f32 *S, + float32_t *pSrc, + float32_t *pRef, + float32_t *pOut, + float32_t *pErr, + uint32_t blockSize); - /** + /** * @brief Initialization function for floating-point normalized LMS filter. * @param[in] *S points to an instance of the floating-point LMS filter structure. * @param[in] numTaps number of filter coefficients. @@ -4401,31 +4292,30 @@ void arm_rfft_fast_f32( * @return none. */ - void arm_lms_norm_init_f32( - arm_lms_norm_instance_f32 * S, - uint16_t numTaps, - float32_t * pCoeffs, - float32_t * pState, - float32_t mu, - uint32_t blockSize); + void arm_lms_norm_init_f32( + arm_lms_norm_instance_f32 *S, + uint16_t numTaps, + float32_t *pCoeffs, + float32_t *pState, + float32_t mu, + uint32_t blockSize); - - /** + /** * @brief Instance structure for the Q31 normalized LMS filter. */ - typedef struct - { - uint16_t numTaps; /**< number of coefficients in the filter. */ - q31_t *pState; /**< points to the state variable array. The array is of length numTaps+blockSize-1. */ - q31_t *pCoeffs; /**< points to the coefficient array. The array is of length numTaps. */ - q31_t mu; /**< step size that controls filter coefficient updates. */ - uint8_t postShift; /**< bit shift applied to coefficients. */ - q31_t *recipTable; /**< points to the reciprocal initial value table. */ - q31_t energy; /**< saves previous frame energy. */ - q31_t x0; /**< saves previous input sample. */ - } arm_lms_norm_instance_q31; + typedef struct + { + uint16_t numTaps; /**< number of coefficients in the filter. */ + q31_t *pState; /**< points to the state variable array. The array is of length numTaps+blockSize-1. */ + q31_t *pCoeffs; /**< points to the coefficient array. The array is of length numTaps. */ + q31_t mu; /**< step size that controls filter coefficient updates. */ + uint8_t postShift; /**< bit shift applied to coefficients. */ + q31_t *recipTable; /**< points to the reciprocal initial value table. */ + q31_t energy; /**< saves previous frame energy. */ + q31_t x0; /**< saves previous input sample. */ + } arm_lms_norm_instance_q31; - /** + /** * @brief Processing function for Q31 normalized LMS filter. * @param[in] *S points to an instance of the Q31 normalized LMS filter structure. * @param[in] *pSrc points to the block of input data. @@ -4436,15 +4326,15 @@ void arm_rfft_fast_f32( * @return none. */ - void arm_lms_norm_q31( - arm_lms_norm_instance_q31 * S, - q31_t * pSrc, - q31_t * pRef, - q31_t * pOut, - q31_t * pErr, - uint32_t blockSize); + void arm_lms_norm_q31( + arm_lms_norm_instance_q31 *S, + q31_t *pSrc, + q31_t *pRef, + q31_t *pOut, + q31_t *pErr, + uint32_t blockSize); - /** + /** * @brief Initialization function for Q31 normalized LMS filter. * @param[in] *S points to an instance of the Q31 normalized LMS filter structure. * @param[in] numTaps number of filter coefficients. @@ -4456,32 +4346,32 @@ void arm_rfft_fast_f32( * @return none. */ - void arm_lms_norm_init_q31( - arm_lms_norm_instance_q31 * S, - uint16_t numTaps, - q31_t * pCoeffs, - q31_t * pState, - q31_t mu, - uint32_t blockSize, - uint8_t postShift); + void arm_lms_norm_init_q31( + arm_lms_norm_instance_q31 *S, + uint16_t numTaps, + q31_t *pCoeffs, + q31_t *pState, + q31_t mu, + uint32_t blockSize, + uint8_t postShift); - /** + /** * @brief Instance structure for the Q15 normalized LMS filter. */ - typedef struct - { - uint16_t numTaps; /**< Number of coefficients in the filter. */ - q15_t *pState; /**< points to the state variable array. The array is of length numTaps+blockSize-1. */ - q15_t *pCoeffs; /**< points to the coefficient array. The array is of length numTaps. */ - q15_t mu; /**< step size that controls filter coefficient updates. */ - uint8_t postShift; /**< bit shift applied to coefficients. */ - q15_t *recipTable; /**< Points to the reciprocal initial value table. */ - q15_t energy; /**< saves previous frame energy. */ - q15_t x0; /**< saves previous input sample. */ - } arm_lms_norm_instance_q15; + typedef struct + { + uint16_t numTaps; /**< Number of coefficients in the filter. */ + q15_t *pState; /**< points to the state variable array. The array is of length numTaps+blockSize-1. */ + q15_t *pCoeffs; /**< points to the coefficient array. The array is of length numTaps. */ + q15_t mu; /**< step size that controls filter coefficient updates. */ + uint8_t postShift; /**< bit shift applied to coefficients. */ + q15_t *recipTable; /**< Points to the reciprocal initial value table. */ + q15_t energy; /**< saves previous frame energy. */ + q15_t x0; /**< saves previous input sample. */ + } arm_lms_norm_instance_q15; - /** + /** * @brief Processing function for Q15 normalized LMS filter. * @param[in] *S points to an instance of the Q15 normalized LMS filter structure. * @param[in] *pSrc points to the block of input data. @@ -4492,16 +4382,15 @@ void arm_rfft_fast_f32( * @return none. */ - void arm_lms_norm_q15( - arm_lms_norm_instance_q15 * S, - q15_t * pSrc, - q15_t * pRef, - q15_t * pOut, - q15_t * pErr, - uint32_t blockSize); + void arm_lms_norm_q15( + arm_lms_norm_instance_q15 *S, + q15_t *pSrc, + q15_t *pRef, + q15_t *pOut, + q15_t *pErr, + uint32_t blockSize); - - /** + /** * @brief Initialization function for Q15 normalized LMS filter. * @param[in] *S points to an instance of the Q15 normalized LMS filter structure. * @param[in] numTaps number of filter coefficients. @@ -4513,16 +4402,16 @@ void arm_rfft_fast_f32( * @return none. */ - void arm_lms_norm_init_q15( - arm_lms_norm_instance_q15 * S, - uint16_t numTaps, - q15_t * pCoeffs, - q15_t * pState, - q15_t mu, - uint32_t blockSize, - uint8_t postShift); + void arm_lms_norm_init_q15( + arm_lms_norm_instance_q15 *S, + uint16_t numTaps, + q15_t *pCoeffs, + q15_t *pState, + q15_t mu, + uint32_t blockSize, + uint8_t postShift); - /** + /** * @brief Correlation of floating-point sequences. * @param[in] *pSrcA points to the first input sequence. * @param[in] srcALen length of the first input sequence. @@ -4532,15 +4421,14 @@ void arm_rfft_fast_f32( * @return none. */ - void arm_correlate_f32( - float32_t * pSrcA, - uint32_t srcALen, - float32_t * pSrcB, - uint32_t srcBLen, - float32_t * pDst); - + void arm_correlate_f32( + float32_t *pSrcA, + uint32_t srcALen, + float32_t *pSrcB, + uint32_t srcBLen, + float32_t *pDst); - /** + /** * @brief Correlation of Q15 sequences * @param[in] *pSrcA points to the first input sequence. * @param[in] srcALen length of the first input sequence. @@ -4550,16 +4438,15 @@ void arm_rfft_fast_f32( * @param[in] *pScratch points to scratch buffer of size max(srcALen, srcBLen) + 2*min(srcALen, srcBLen) - 2. * @return none. */ - void arm_correlate_opt_q15( - q15_t * pSrcA, - uint32_t srcALen, - q15_t * pSrcB, - uint32_t srcBLen, - q15_t * pDst, - q15_t * pScratch); + void arm_correlate_opt_q15( + q15_t *pSrcA, + uint32_t srcALen, + q15_t *pSrcB, + uint32_t srcBLen, + q15_t *pDst, + q15_t *pScratch); - - /** + /** * @brief Correlation of Q15 sequences. * @param[in] *pSrcA points to the first input sequence. * @param[in] srcALen length of the first input sequence. @@ -4569,14 +4456,14 @@ void arm_rfft_fast_f32( * @return none. */ - void arm_correlate_q15( - q15_t * pSrcA, - uint32_t srcALen, - q15_t * pSrcB, - uint32_t srcBLen, - q15_t * pDst); + void arm_correlate_q15( + q15_t *pSrcA, + uint32_t srcALen, + q15_t *pSrcB, + uint32_t srcBLen, + q15_t *pDst); - /** + /** * @brief Correlation of Q15 sequences (fast version) for Cortex-M3 and Cortex-M4. * @param[in] *pSrcA points to the first input sequence. * @param[in] srcALen length of the first input sequence. @@ -4586,16 +4473,14 @@ void arm_rfft_fast_f32( * @return none. */ - void arm_correlate_fast_q15( - q15_t * pSrcA, - uint32_t srcALen, - q15_t * pSrcB, - uint32_t srcBLen, - q15_t * pDst); + void arm_correlate_fast_q15( + q15_t *pSrcA, + uint32_t srcALen, + q15_t *pSrcB, + uint32_t srcBLen, + q15_t *pDst); - - - /** + /** * @brief Correlation of Q15 sequences (fast version) for Cortex-M3 and Cortex-M4. * @param[in] *pSrcA points to the first input sequence. * @param[in] srcALen length of the first input sequence. @@ -4606,15 +4491,15 @@ void arm_rfft_fast_f32( * @return none. */ - void arm_correlate_fast_opt_q15( - q15_t * pSrcA, - uint32_t srcALen, - q15_t * pSrcB, - uint32_t srcBLen, - q15_t * pDst, - q15_t * pScratch); + void arm_correlate_fast_opt_q15( + q15_t *pSrcA, + uint32_t srcALen, + q15_t *pSrcB, + uint32_t srcBLen, + q15_t *pDst, + q15_t *pScratch); - /** + /** * @brief Correlation of Q31 sequences. * @param[in] *pSrcA points to the first input sequence. * @param[in] srcALen length of the first input sequence. @@ -4624,14 +4509,14 @@ void arm_rfft_fast_f32( * @return none. */ - void arm_correlate_q31( - q31_t * pSrcA, - uint32_t srcALen, - q31_t * pSrcB, - uint32_t srcBLen, - q31_t * pDst); + void arm_correlate_q31( + q31_t *pSrcA, + uint32_t srcALen, + q31_t *pSrcB, + uint32_t srcBLen, + q31_t *pDst); - /** + /** * @brief Correlation of Q31 sequences (fast version) for Cortex-M3 and Cortex-M4 * @param[in] *pSrcA points to the first input sequence. * @param[in] srcALen length of the first input sequence. @@ -4641,16 +4526,14 @@ void arm_rfft_fast_f32( * @return none. */ - void arm_correlate_fast_q31( - q31_t * pSrcA, - uint32_t srcALen, - q31_t * pSrcB, - uint32_t srcBLen, - q31_t * pDst); - - + void arm_correlate_fast_q31( + q31_t *pSrcA, + uint32_t srcALen, + q31_t *pSrcB, + uint32_t srcBLen, + q31_t *pDst); - /** + /** * @brief Correlation of Q7 sequences. * @param[in] *pSrcA points to the first input sequence. * @param[in] srcALen length of the first input sequence. @@ -4662,17 +4545,16 @@ void arm_rfft_fast_f32( * @return none. */ - void arm_correlate_opt_q7( - q7_t * pSrcA, - uint32_t srcALen, - q7_t * pSrcB, - uint32_t srcBLen, - q7_t * pDst, - q15_t * pScratch1, - q15_t * pScratch2); - + void arm_correlate_opt_q7( + q7_t *pSrcA, + uint32_t srcALen, + q7_t *pSrcB, + uint32_t srcBLen, + q7_t *pDst, + q15_t *pScratch1, + q15_t *pScratch2); - /** + /** * @brief Correlation of Q7 sequences. * @param[in] *pSrcA points to the first input sequence. * @param[in] srcALen length of the first input sequence. @@ -4682,70 +4564,69 @@ void arm_rfft_fast_f32( * @return none. */ - void arm_correlate_q7( - q7_t * pSrcA, - uint32_t srcALen, - q7_t * pSrcB, - uint32_t srcBLen, - q7_t * pDst); + void arm_correlate_q7( + q7_t *pSrcA, + uint32_t srcALen, + q7_t *pSrcB, + uint32_t srcBLen, + q7_t *pDst); - - /** + /** * @brief Instance structure for the floating-point sparse FIR filter. */ - typedef struct - { - uint16_t numTaps; /**< number of coefficients in the filter. */ - uint16_t stateIndex; /**< state buffer index. Points to the oldest sample in the state buffer. */ - float32_t *pState; /**< points to the state buffer array. The array is of length maxDelay+blockSize-1. */ - float32_t *pCoeffs; /**< points to the coefficient array. The array is of length numTaps.*/ - uint16_t maxDelay; /**< maximum offset specified by the pTapDelay array. */ - int32_t *pTapDelay; /**< points to the array of delay values. The array is of length numTaps. */ - } arm_fir_sparse_instance_f32; + typedef struct + { + uint16_t numTaps; /**< number of coefficients in the filter. */ + uint16_t stateIndex; /**< state buffer index. Points to the oldest sample in the state buffer. */ + float32_t *pState; /**< points to the state buffer array. The array is of length maxDelay+blockSize-1. */ + float32_t *pCoeffs; /**< points to the coefficient array. The array is of length numTaps.*/ + uint16_t maxDelay; /**< maximum offset specified by the pTapDelay array. */ + int32_t *pTapDelay; /**< points to the array of delay values. The array is of length numTaps. */ + } arm_fir_sparse_instance_f32; - /** + /** * @brief Instance structure for the Q31 sparse FIR filter. */ - typedef struct - { - uint16_t numTaps; /**< number of coefficients in the filter. */ - uint16_t stateIndex; /**< state buffer index. Points to the oldest sample in the state buffer. */ - q31_t *pState; /**< points to the state buffer array. The array is of length maxDelay+blockSize-1. */ - q31_t *pCoeffs; /**< points to the coefficient array. The array is of length numTaps.*/ - uint16_t maxDelay; /**< maximum offset specified by the pTapDelay array. */ - int32_t *pTapDelay; /**< points to the array of delay values. The array is of length numTaps. */ - } arm_fir_sparse_instance_q31; + typedef struct + { + uint16_t numTaps; /**< number of coefficients in the filter. */ + uint16_t stateIndex; /**< state buffer index. Points to the oldest sample in the state buffer. */ + q31_t *pState; /**< points to the state buffer array. The array is of length maxDelay+blockSize-1. */ + q31_t *pCoeffs; /**< points to the coefficient array. The array is of length numTaps.*/ + uint16_t maxDelay; /**< maximum offset specified by the pTapDelay array. */ + int32_t *pTapDelay; /**< points to the array of delay values. The array is of length numTaps. */ + } arm_fir_sparse_instance_q31; - /** + /** * @brief Instance structure for the Q15 sparse FIR filter. */ - typedef struct - { - uint16_t numTaps; /**< number of coefficients in the filter. */ - uint16_t stateIndex; /**< state buffer index. Points to the oldest sample in the state buffer. */ - q15_t *pState; /**< points to the state buffer array. The array is of length maxDelay+blockSize-1. */ - q15_t *pCoeffs; /**< points to the coefficient array. The array is of length numTaps.*/ - uint16_t maxDelay; /**< maximum offset specified by the pTapDelay array. */ - int32_t *pTapDelay; /**< points to the array of delay values. The array is of length numTaps. */ - } arm_fir_sparse_instance_q15; + typedef struct + { + uint16_t numTaps; /**< number of coefficients in the filter. */ + uint16_t stateIndex; /**< state buffer index. Points to the oldest sample in the state buffer. */ + q15_t *pState; /**< points to the state buffer array. The array is of length maxDelay+blockSize-1. */ + q15_t *pCoeffs; /**< points to the coefficient array. The array is of length numTaps.*/ + uint16_t maxDelay; /**< maximum offset specified by the pTapDelay array. */ + int32_t *pTapDelay; /**< points to the array of delay values. The array is of length numTaps. */ + } arm_fir_sparse_instance_q15; - /** + /** * @brief Instance structure for the Q7 sparse FIR filter. */ - typedef struct - { - uint16_t numTaps; /**< number of coefficients in the filter. */ - uint16_t stateIndex; /**< state buffer index. Points to the oldest sample in the state buffer. */ - q7_t *pState; /**< points to the state buffer array. The array is of length maxDelay+blockSize-1. */ - q7_t *pCoeffs; /**< points to the coefficient array. The array is of length numTaps.*/ - uint16_t maxDelay; /**< maximum offset specified by the pTapDelay array. */ - int32_t *pTapDelay; /**< points to the array of delay values. The array is of length numTaps. */ - } arm_fir_sparse_instance_q7; + typedef struct + { + uint16_t numTaps; /**< number of coefficients in the filter. */ + uint16_t stateIndex; /**< state buffer index. Points to the oldest sample in the state buffer. */ + q7_t *pState; /**< points to the state buffer array. The array is of length maxDelay+blockSize-1. */ + q7_t *pCoeffs; /**< points to the coefficient array. The array is of length numTaps.*/ + uint16_t maxDelay; /**< maximum offset specified by the pTapDelay array. */ + int32_t *pTapDelay; /**< points to the array of delay values. The array is of length numTaps. */ + } arm_fir_sparse_instance_q7; - /** + /** * @brief Processing function for the floating-point sparse FIR filter. * @param[in] *S points to an instance of the floating-point sparse FIR structure. * @param[in] *pSrc points to the block of input data. @@ -4755,14 +4636,14 @@ void arm_rfft_fast_f32( * @return none. */ - void arm_fir_sparse_f32( - arm_fir_sparse_instance_f32 * S, - float32_t * pSrc, - float32_t * pDst, - float32_t * pScratchIn, - uint32_t blockSize); + void arm_fir_sparse_f32( + arm_fir_sparse_instance_f32 *S, + float32_t *pSrc, + float32_t *pDst, + float32_t *pScratchIn, + uint32_t blockSize); - /** + /** * @brief Initialization function for the floating-point sparse FIR filter. * @param[in,out] *S points to an instance of the floating-point sparse FIR structure. * @param[in] numTaps number of nonzero coefficients in the filter. @@ -4774,16 +4655,16 @@ void arm_rfft_fast_f32( * @return none */ - void arm_fir_sparse_init_f32( - arm_fir_sparse_instance_f32 * S, - uint16_t numTaps, - float32_t * pCoeffs, - float32_t * pState, - int32_t * pTapDelay, - uint16_t maxDelay, - uint32_t blockSize); + void arm_fir_sparse_init_f32( + arm_fir_sparse_instance_f32 *S, + uint16_t numTaps, + float32_t *pCoeffs, + float32_t *pState, + int32_t *pTapDelay, + uint16_t maxDelay, + uint32_t blockSize); - /** + /** * @brief Processing function for the Q31 sparse FIR filter. * @param[in] *S points to an instance of the Q31 sparse FIR structure. * @param[in] *pSrc points to the block of input data. @@ -4793,14 +4674,14 @@ void arm_rfft_fast_f32( * @return none. */ - void arm_fir_sparse_q31( - arm_fir_sparse_instance_q31 * S, - q31_t * pSrc, - q31_t * pDst, - q31_t * pScratchIn, - uint32_t blockSize); + void arm_fir_sparse_q31( + arm_fir_sparse_instance_q31 *S, + q31_t *pSrc, + q31_t *pDst, + q31_t *pScratchIn, + uint32_t blockSize); - /** + /** * @brief Initialization function for the Q31 sparse FIR filter. * @param[in,out] *S points to an instance of the Q31 sparse FIR structure. * @param[in] numTaps number of nonzero coefficients in the filter. @@ -4812,16 +4693,16 @@ void arm_rfft_fast_f32( * @return none */ - void arm_fir_sparse_init_q31( - arm_fir_sparse_instance_q31 * S, - uint16_t numTaps, - q31_t * pCoeffs, - q31_t * pState, - int32_t * pTapDelay, - uint16_t maxDelay, - uint32_t blockSize); + void arm_fir_sparse_init_q31( + arm_fir_sparse_instance_q31 *S, + uint16_t numTaps, + q31_t *pCoeffs, + q31_t *pState, + int32_t *pTapDelay, + uint16_t maxDelay, + uint32_t blockSize); - /** + /** * @brief Processing function for the Q15 sparse FIR filter. * @param[in] *S points to an instance of the Q15 sparse FIR structure. * @param[in] *pSrc points to the block of input data. @@ -4832,16 +4713,15 @@ void arm_rfft_fast_f32( * @return none. */ - void arm_fir_sparse_q15( - arm_fir_sparse_instance_q15 * S, - q15_t * pSrc, - q15_t * pDst, - q15_t * pScratchIn, - q31_t * pScratchOut, - uint32_t blockSize); - + void arm_fir_sparse_q15( + arm_fir_sparse_instance_q15 *S, + q15_t *pSrc, + q15_t *pDst, + q15_t *pScratchIn, + q31_t *pScratchOut, + uint32_t blockSize); - /** + /** * @brief Initialization function for the Q15 sparse FIR filter. * @param[in,out] *S points to an instance of the Q15 sparse FIR structure. * @param[in] numTaps number of nonzero coefficients in the filter. @@ -4853,16 +4733,16 @@ void arm_rfft_fast_f32( * @return none */ - void arm_fir_sparse_init_q15( - arm_fir_sparse_instance_q15 * S, - uint16_t numTaps, - q15_t * pCoeffs, - q15_t * pState, - int32_t * pTapDelay, - uint16_t maxDelay, - uint32_t blockSize); + void arm_fir_sparse_init_q15( + arm_fir_sparse_instance_q15 *S, + uint16_t numTaps, + q15_t *pCoeffs, + q15_t *pState, + int32_t *pTapDelay, + uint16_t maxDelay, + uint32_t blockSize); - /** + /** * @brief Processing function for the Q7 sparse FIR filter. * @param[in] *S points to an instance of the Q7 sparse FIR structure. * @param[in] *pSrc points to the block of input data. @@ -4873,15 +4753,15 @@ void arm_rfft_fast_f32( * @return none. */ - void arm_fir_sparse_q7( - arm_fir_sparse_instance_q7 * S, - q7_t * pSrc, - q7_t * pDst, - q7_t * pScratchIn, - q31_t * pScratchOut, - uint32_t blockSize); + void arm_fir_sparse_q7( + arm_fir_sparse_instance_q7 *S, + q7_t *pSrc, + q7_t *pDst, + q7_t *pScratchIn, + q31_t *pScratchOut, + uint32_t blockSize); - /** + /** * @brief Initialization function for the Q7 sparse FIR filter. * @param[in,out] *S points to an instance of the Q7 sparse FIR structure. * @param[in] numTaps number of nonzero coefficients in the filter. @@ -4893,17 +4773,16 @@ void arm_rfft_fast_f32( * @return none */ - void arm_fir_sparse_init_q7( - arm_fir_sparse_instance_q7 * S, - uint16_t numTaps, - q7_t * pCoeffs, - q7_t * pState, - int32_t * pTapDelay, - uint16_t maxDelay, - uint32_t blockSize); - + void arm_fir_sparse_init_q7( + arm_fir_sparse_instance_q7 *S, + uint16_t numTaps, + q7_t *pCoeffs, + q7_t *pState, + int32_t *pTapDelay, + uint16_t maxDelay, + uint32_t blockSize); - /* + /* * @brief Floating-point sin_cos function. * @param[in] theta input value in degrees * @param[out] *pSinVal points to the processed sine output. @@ -4911,12 +4790,12 @@ void arm_rfft_fast_f32( * @return none. */ - void arm_sin_cos_f32( - float32_t theta, - float32_t * pSinVal, - float32_t * pCcosVal); + void arm_sin_cos_f32( + float32_t theta, + float32_t *pSinVal, + float32_t *pCcosVal); - /* + /* * @brief Q31 sin_cos function. * @param[in] theta scaled input value in degrees * @param[out] *pSinVal points to the processed sine output. @@ -4924,13 +4803,12 @@ void arm_rfft_fast_f32( * @return none. */ - void arm_sin_cos_q31( - q31_t theta, - q31_t * pSinVal, - q31_t * pCosVal); + void arm_sin_cos_q31( + q31_t theta, + q31_t *pSinVal, + q31_t *pCosVal); - - /** + /** * @brief Floating-point complex conjugate. * @param[in] *pSrc points to the input vector * @param[out] *pDst points to the output vector @@ -4938,12 +4816,12 @@ void arm_rfft_fast_f32( * @return none. */ - void arm_cmplx_conj_f32( - float32_t * pSrc, - float32_t * pDst, - uint32_t numSamples); + void arm_cmplx_conj_f32( + float32_t *pSrc, + float32_t *pDst, + uint32_t numSamples); - /** + /** * @brief Q31 complex conjugate. * @param[in] *pSrc points to the input vector * @param[out] *pDst points to the output vector @@ -4951,12 +4829,12 @@ void arm_rfft_fast_f32( * @return none. */ - void arm_cmplx_conj_q31( - q31_t * pSrc, - q31_t * pDst, - uint32_t numSamples); + void arm_cmplx_conj_q31( + q31_t *pSrc, + q31_t *pDst, + uint32_t numSamples); - /** + /** * @brief Q15 complex conjugate. * @param[in] *pSrc points to the input vector * @param[out] *pDst points to the output vector @@ -4964,14 +4842,12 @@ void arm_rfft_fast_f32( * @return none. */ - void arm_cmplx_conj_q15( - q15_t * pSrc, - q15_t * pDst, - uint32_t numSamples); + void arm_cmplx_conj_q15( + q15_t *pSrc, + q15_t *pDst, + uint32_t numSamples); - - - /** + /** * @brief Floating-point complex magnitude squared * @param[in] *pSrc points to the complex input vector * @param[out] *pDst points to the real output vector @@ -4979,12 +4855,12 @@ void arm_rfft_fast_f32( * @return none. */ - void arm_cmplx_mag_squared_f32( - float32_t * pSrc, - float32_t * pDst, - uint32_t numSamples); + void arm_cmplx_mag_squared_f32( + float32_t *pSrc, + float32_t *pDst, + uint32_t numSamples); - /** + /** * @brief Q31 complex magnitude squared * @param[in] *pSrc points to the complex input vector * @param[out] *pDst points to the real output vector @@ -4992,12 +4868,12 @@ void arm_rfft_fast_f32( * @return none. */ - void arm_cmplx_mag_squared_q31( - q31_t * pSrc, - q31_t * pDst, - uint32_t numSamples); + void arm_cmplx_mag_squared_q31( + q31_t *pSrc, + q31_t *pDst, + uint32_t numSamples); - /** + /** * @brief Q15 complex magnitude squared * @param[in] *pSrc points to the complex input vector * @param[out] *pDst points to the real output vector @@ -5005,17 +4881,16 @@ void arm_rfft_fast_f32( * @return none. */ - void arm_cmplx_mag_squared_q15( - q15_t * pSrc, - q15_t * pDst, - uint32_t numSamples); + void arm_cmplx_mag_squared_q15( + q15_t *pSrc, + q15_t *pDst, + uint32_t numSamples); - - /** + /** * @ingroup groupController */ - /** + /** * @defgroup PID PID Motor Control * * A Proportional Integral Derivative (PID) controller is a generic feedback control @@ -5072,40 +4947,38 @@ void arm_rfft_fast_f32( * Refer to the function specific documentation below for usage guidelines. */ - /** + /** * @addtogroup PID * @{ */ - /** + /** * @brief Process function for the floating-point PID Control. * @param[in,out] *S is an instance of the floating-point PID Control structure * @param[in] in input sample to process * @return out processed output sample. */ + static __INLINE float32_t arm_pid_f32( + arm_pid_instance_f32 *S, + float32_t in) + { + float32_t out; - static __INLINE float32_t arm_pid_f32( - arm_pid_instance_f32 * S, - float32_t in) - { - float32_t out; - - /* y[n] = y[n-1] + A0 * x[n] + A1 * x[n-1] + A2 * x[n-2] */ - out = (S->A0 * in) + - (S->A1 * S->state[0]) + (S->A2 * S->state[1]) + (S->state[2]); - - /* Update state */ - S->state[1] = S->state[0]; - S->state[0] = in; - S->state[2] = out; + /* y[n] = y[n-1] + A0 * x[n] + A1 * x[n-1] + A2 * x[n-2] */ + out = (S->A0 * in) + + (S->A1 * S->state[0]) + (S->A2 * S->state[1]) + (S->state[2]); - /* return to application */ - return (out); + /* Update state */ + S->state[1] = S->state[0]; + S->state[0] = in; + S->state[2] = out; - } + /* return to application */ + return (out); + } - /** + /** * @brief Process function for the Q31 PID Control. * @param[in,out] *S points to an instance of the Q31 PID Control structure * @param[in] in input sample to process @@ -5120,39 +4993,38 @@ void arm_rfft_fast_f32( * After all multiply-accumulates are performed, the 2.62 accumulator is truncated to 1.32 format and then saturated to 1.31 format. */ - static __INLINE q31_t arm_pid_q31( - arm_pid_instance_q31 * S, - q31_t in) - { - q63_t acc; - q31_t out; - - /* acc = A0 * x[n] */ - acc = (q63_t) S->A0 * in; + static __INLINE q31_t arm_pid_q31( + arm_pid_instance_q31 *S, + q31_t in) + { + q63_t acc; + q31_t out; - /* acc += A1 * x[n-1] */ - acc += (q63_t) S->A1 * S->state[0]; + /* acc = A0 * x[n] */ + acc = (q63_t)S->A0 * in; - /* acc += A2 * x[n-2] */ - acc += (q63_t) S->A2 * S->state[1]; + /* acc += A1 * x[n-1] */ + acc += (q63_t)S->A1 * S->state[0]; - /* convert output to 1.31 format to add y[n-1] */ - out = (q31_t) (acc >> 31u); + /* acc += A2 * x[n-2] */ + acc += (q63_t)S->A2 * S->state[1]; - /* out += y[n-1] */ - out += S->state[2]; + /* convert output to 1.31 format to add y[n-1] */ + out = (q31_t)(acc >> 31u); - /* Update state */ - S->state[1] = S->state[0]; - S->state[0] = in; - S->state[2] = out; + /* out += y[n-1] */ + out += S->state[2]; - /* return to application */ - return (out); + /* Update state */ + S->state[1] = S->state[0]; + S->state[0] = in; + S->state[2] = out; - } + /* return to application */ + return (out); + } - /** + /** * @brief Process function for the Q15 PID Control. * @param[in,out] *S points to an instance of the Q15 PID Control structure * @param[in] in input sample to process @@ -5168,57 +5040,55 @@ void arm_rfft_fast_f32( * Lastly, the accumulator is saturated to yield a result in 1.15 format. */ - static __INLINE q15_t arm_pid_q15( - arm_pid_instance_q15 * S, - q15_t in) - { - q63_t acc; - q15_t out; + static __INLINE q15_t arm_pid_q15( + arm_pid_instance_q15 *S, + q15_t in) + { + q63_t acc; + q15_t out; #ifndef ARM_MATH_CM0_FAMILY - __SIMD32_TYPE *vstate; + __SIMD32_TYPE *vstate; - /* Implementation of PID controller */ + /* Implementation of PID controller */ - /* acc = A0 * x[n] */ - acc = (q31_t) __SMUAD(S->A0, in); + /* acc = A0 * x[n] */ + acc = (q31_t)__SMUAD(S->A0, in); - /* acc += A1 * x[n-1] + A2 * x[n-2] */ - vstate = __SIMD32_CONST(S->state); - acc = __SMLALD(S->A1, (q31_t) *vstate, acc); + /* acc += A1 * x[n-1] + A2 * x[n-2] */ + vstate = __SIMD32_CONST(S->state); + acc = __SMLALD(S->A1, (q31_t)*vstate, acc); #else /* acc = A0 * x[n] */ - acc = ((q31_t) S->A0) * in; + acc = ((q31_t)S->A0) * in; /* acc += A1 * x[n-1] + A2 * x[n-2] */ - acc += (q31_t) S->A1 * S->state[0]; - acc += (q31_t) S->A2 * S->state[1]; + acc += (q31_t)S->A1 * S->state[0]; + acc += (q31_t)S->A2 * S->state[1]; #endif - /* acc += y[n-1] */ - acc += (q31_t) S->state[2] << 15; + /* acc += y[n-1] */ + acc += (q31_t)S->state[2] << 15; - /* saturate the output */ - out = (q15_t) (__SSAT((acc >> 15), 16)); + /* saturate the output */ + out = (q15_t)(__SSAT((acc >> 15), 16)); - /* Update state */ - S->state[1] = S->state[0]; - S->state[0] = in; - S->state[2] = out; + /* Update state */ + S->state[1] = S->state[0]; + S->state[0] = in; + S->state[2] = out; - /* return to application */ - return (out); - - } + /* return to application */ + return (out); + } - /** + /** * @} end of PID group */ - - /** + /** * @brief Floating-point matrix inverse. * @param[in] *src points to the instance of the input floating-point matrix structure. * @param[out] *dst points to the instance of the output floating-point matrix structure. @@ -5226,12 +5096,11 @@ void arm_rfft_fast_f32( * If the input matrix is singular (does not have an inverse), then the algorithm terminates and returns error status ARM_MATH_SINGULAR. */ - arm_status arm_mat_inverse_f32( - const arm_matrix_instance_f32 * src, - arm_matrix_instance_f32 * dst); - + arm_status arm_mat_inverse_f32( + const arm_matrix_instance_f32 *src, + arm_matrix_instance_f32 *dst); - /** + /** * @brief Floating-point matrix inverse. * @param[in] *src points to the instance of the input floating-point matrix structure. * @param[out] *dst points to the instance of the output floating-point matrix structure. @@ -5239,18 +5108,15 @@ void arm_rfft_fast_f32( * If the input matrix is singular (does not have an inverse), then the algorithm terminates and returns error status ARM_MATH_SINGULAR. */ - arm_status arm_mat_inverse_f64( - const arm_matrix_instance_f64 * src, - arm_matrix_instance_f64 * dst); + arm_status arm_mat_inverse_f64( + const arm_matrix_instance_f64 *src, + arm_matrix_instance_f64 *dst); - - - /** + /** * @ingroup groupController */ - - /** + /** * @defgroup clarke Vector Clarke Transform * Forward Clarke transform converts the instantaneous stator phases into a two-coordinate time invariant vector. * Generally the Clarke transform uses three-phase currents <code>Ia, Ib and Ic</code> to calculate currents @@ -5272,12 +5138,12 @@ void arm_rfft_fast_f32( * Refer to the function specific documentation below for usage guidelines. */ - /** + /** * @addtogroup clarke * @{ */ - /** + /** * * @brief Floating-point Clarke transform * @param[in] Ia input three-phase coordinate <code>a</code> @@ -5287,22 +5153,21 @@ void arm_rfft_fast_f32( * @return none. */ - static __INLINE void arm_clarke_f32( - float32_t Ia, - float32_t Ib, - float32_t * pIalpha, - float32_t * pIbeta) - { - /* Calculate pIalpha using the equation, pIalpha = Ia */ - *pIalpha = Ia; - - /* Calculate pIbeta using the equation, pIbeta = (1/sqrt(3)) * Ia + (2/sqrt(3)) * Ib */ - *pIbeta = - ((float32_t) 0.57735026919 * Ia + (float32_t) 1.15470053838 * Ib); + static __INLINE void arm_clarke_f32( + float32_t Ia, + float32_t Ib, + float32_t *pIalpha, + float32_t *pIbeta) + { + /* Calculate pIalpha using the equation, pIalpha = Ia */ + *pIalpha = Ia; - } + /* Calculate pIbeta using the equation, pIbeta = (1/sqrt(3)) * Ia + (2/sqrt(3)) * Ib */ + *pIbeta = + ((float32_t)0.57735026919 * Ia + (float32_t)1.15470053838 * Ib); + } - /** + /** * @brief Clarke transform for Q31 version * @param[in] Ia input three-phase coordinate <code>a</code> * @param[in] Ib input three-phase coordinate <code>b</code> @@ -5317,51 +5182,48 @@ void arm_rfft_fast_f32( * There is saturation on the addition, hence there is no risk of overflow. */ - static __INLINE void arm_clarke_q31( - q31_t Ia, - q31_t Ib, - q31_t * pIalpha, - q31_t * pIbeta) - { - q31_t product1, product2; /* Temporary variables used to store intermediate results */ + static __INLINE void arm_clarke_q31( + q31_t Ia, + q31_t Ib, + q31_t *pIalpha, + q31_t *pIbeta) + { + q31_t product1, product2; /* Temporary variables used to store intermediate results */ - /* Calculating pIalpha from Ia by equation pIalpha = Ia */ - *pIalpha = Ia; + /* Calculating pIalpha from Ia by equation pIalpha = Ia */ + *pIalpha = Ia; - /* Intermediate product is calculated by (1/(sqrt(3)) * Ia) */ - product1 = (q31_t) (((q63_t) Ia * 0x24F34E8B) >> 30); + /* Intermediate product is calculated by (1/(sqrt(3)) * Ia) */ + product1 = (q31_t)(((q63_t)Ia * 0x24F34E8B) >> 30); - /* Intermediate product is calculated by (2/sqrt(3) * Ib) */ - product2 = (q31_t) (((q63_t) Ib * 0x49E69D16) >> 30); + /* Intermediate product is calculated by (2/sqrt(3) * Ib) */ + product2 = (q31_t)(((q63_t)Ib * 0x49E69D16) >> 30); - /* pIbeta is calculated by adding the intermediate products */ - *pIbeta = __QADD(product1, product2); - } + /* pIbeta is calculated by adding the intermediate products */ + *pIbeta = __QADD(product1, product2); + } - /** + /** * @} end of clarke group */ - /** + /** * @brief Converts the elements of the Q7 vector to Q31 vector. * @param[in] *pSrc input pointer * @param[out] *pDst output pointer * @param[in] blockSize number of samples to process * @return none. */ - void arm_q7_to_q31( - q7_t * pSrc, - q31_t * pDst, - uint32_t blockSize); - + void arm_q7_to_q31( + q7_t *pSrc, + q31_t *pDst, + uint32_t blockSize); - - - /** + /** * @ingroup groupController */ - /** + /** * @defgroup inv_clarke Vector Inverse Clarke Transform * Inverse Clarke transform converts the two-coordinate time invariant vector into instantaneous stator phases. * @@ -5377,12 +5239,12 @@ void arm_rfft_fast_f32( * Refer to the function specific documentation below for usage guidelines. */ - /** + /** * @addtogroup inv_clarke * @{ */ - /** + /** * @brief Floating-point Inverse Clarke transform * @param[in] Ialpha input two-phase orthogonal vector axis alpha * @param[in] Ibeta input two-phase orthogonal vector axis beta @@ -5391,22 +5253,20 @@ void arm_rfft_fast_f32( * @return none. */ + static __INLINE void arm_inv_clarke_f32( + float32_t Ialpha, + float32_t Ibeta, + float32_t *pIa, + float32_t *pIb) + { + /* Calculating pIa from Ialpha by equation pIa = Ialpha */ + *pIa = Ialpha; - static __INLINE void arm_inv_clarke_f32( - float32_t Ialpha, - float32_t Ibeta, - float32_t * pIa, - float32_t * pIb) - { - /* Calculating pIa from Ialpha by equation pIa = Ialpha */ - *pIa = Ialpha; - - /* Calculating pIb from Ialpha and Ibeta by equation pIb = -(1/2) * Ialpha + (sqrt(3)/2) * Ibeta */ - *pIb = -0.5 * Ialpha + (float32_t) 0.8660254039 *Ibeta; - - } + /* Calculating pIb from Ialpha and Ibeta by equation pIb = -(1/2) * Ialpha + (sqrt(3)/2) * Ibeta */ + *pIb = -0.5 * Ialpha + (float32_t)0.8660254039 * Ibeta; + } - /** + /** * @brief Inverse Clarke transform for Q31 version * @param[in] Ialpha input two-phase orthogonal vector axis alpha * @param[in] Ibeta input two-phase orthogonal vector axis beta @@ -5421,51 +5281,48 @@ void arm_rfft_fast_f32( * There is saturation on the subtraction, hence there is no risk of overflow. */ - static __INLINE void arm_inv_clarke_q31( - q31_t Ialpha, - q31_t Ibeta, - q31_t * pIa, - q31_t * pIb) - { - q31_t product1, product2; /* Temporary variables used to store intermediate results */ - - /* Calculating pIa from Ialpha by equation pIa = Ialpha */ - *pIa = Ialpha; + static __INLINE void arm_inv_clarke_q31( + q31_t Ialpha, + q31_t Ibeta, + q31_t *pIa, + q31_t *pIb) + { + q31_t product1, product2; /* Temporary variables used to store intermediate results */ - /* Intermediate product is calculated by (1/(2*sqrt(3)) * Ia) */ - product1 = (q31_t) (((q63_t) (Ialpha) * (0x40000000)) >> 31); + /* Calculating pIa from Ialpha by equation pIa = Ialpha */ + *pIa = Ialpha; - /* Intermediate product is calculated by (1/sqrt(3) * pIb) */ - product2 = (q31_t) (((q63_t) (Ibeta) * (0x6ED9EBA1)) >> 31); + /* Intermediate product is calculated by (1/(2*sqrt(3)) * Ia) */ + product1 = (q31_t)(((q63_t)(Ialpha) * (0x40000000)) >> 31); - /* pIb is calculated by subtracting the products */ - *pIb = __QSUB(product2, product1); + /* Intermediate product is calculated by (1/sqrt(3) * pIb) */ + product2 = (q31_t)(((q63_t)(Ibeta) * (0x6ED9EBA1)) >> 31); - } + /* pIb is calculated by subtracting the products */ + *pIb = __QSUB(product2, product1); + } - /** + /** * @} end of inv_clarke group */ - /** + /** * @brief Converts the elements of the Q7 vector to Q15 vector. * @param[in] *pSrc input pointer * @param[out] *pDst output pointer * @param[in] blockSize number of samples to process * @return none. */ - void arm_q7_to_q15( - q7_t * pSrc, - q15_t * pDst, - uint32_t blockSize); + void arm_q7_to_q15( + q7_t *pSrc, + q15_t *pDst, + uint32_t blockSize); - - - /** + /** * @ingroup groupController */ - /** + /** * @defgroup park Vector Park Transform * * Forward Park transform converts the input two-coordinate vector to flux and torque components. @@ -5489,17 +5346,17 @@ void arm_rfft_fast_f32( * Refer to the function specific documentation below for usage guidelines. */ - /** + /** * @addtogroup park * @{ */ - /** + /** * @brief Floating-point Park transform * @param[in] Ialpha input two-phase vector coordinate alpha * @param[in] Ibeta input two-phase vector coordinate beta - * @param[out] *pId points to output rotor reference frame d - * @param[out] *pIq points to output rotor reference frame q + * @param[out] *pId points to output rotor reference frame d + * @param[out] *pIq points to output rotor reference frame q * @param[in] sinVal sine value of rotation angle theta * @param[in] cosVal cosine value of rotation angle theta * @return none. @@ -5508,23 +5365,22 @@ void arm_rfft_fast_f32( * */ - static __INLINE void arm_park_f32( - float32_t Ialpha, - float32_t Ibeta, - float32_t * pId, - float32_t * pIq, - float32_t sinVal, - float32_t cosVal) - { - /* Calculate pId using the equation, pId = Ialpha * cosVal + Ibeta * sinVal */ - *pId = Ialpha * cosVal + Ibeta * sinVal; - - /* Calculate pIq using the equation, pIq = - Ialpha * sinVal + Ibeta * cosVal */ - *pIq = -Ialpha * sinVal + Ibeta * cosVal; + static __INLINE void arm_park_f32( + float32_t Ialpha, + float32_t Ibeta, + float32_t *pId, + float32_t *pIq, + float32_t sinVal, + float32_t cosVal) + { + /* Calculate pId using the equation, pId = Ialpha * cosVal + Ibeta * sinVal */ + *pId = Ialpha * cosVal + Ibeta * sinVal; - } + /* Calculate pIq using the equation, pIq = - Ialpha * sinVal + Ibeta * cosVal */ + *pIq = -Ialpha * sinVal + Ibeta * cosVal; + } - /** + /** * @brief Park transform for Q31 version * @param[in] Ialpha input two-phase vector coordinate alpha * @param[in] Ibeta input two-phase vector coordinate beta @@ -5541,60 +5397,57 @@ void arm_rfft_fast_f32( * There is saturation on the addition and subtraction, hence there is no risk of overflow. */ + static __INLINE void arm_park_q31( + q31_t Ialpha, + q31_t Ibeta, + q31_t *pId, + q31_t *pIq, + q31_t sinVal, + q31_t cosVal) + { + q31_t product1, product2; /* Temporary variables used to store intermediate results */ + q31_t product3, product4; /* Temporary variables used to store intermediate results */ - static __INLINE void arm_park_q31( - q31_t Ialpha, - q31_t Ibeta, - q31_t * pId, - q31_t * pIq, - q31_t sinVal, - q31_t cosVal) - { - q31_t product1, product2; /* Temporary variables used to store intermediate results */ - q31_t product3, product4; /* Temporary variables used to store intermediate results */ - - /* Intermediate product is calculated by (Ialpha * cosVal) */ - product1 = (q31_t) (((q63_t) (Ialpha) * (cosVal)) >> 31); - - /* Intermediate product is calculated by (Ibeta * sinVal) */ - product2 = (q31_t) (((q63_t) (Ibeta) * (sinVal)) >> 31); + /* Intermediate product is calculated by (Ialpha * cosVal) */ + product1 = (q31_t)(((q63_t)(Ialpha) * (cosVal)) >> 31); + /* Intermediate product is calculated by (Ibeta * sinVal) */ + product2 = (q31_t)(((q63_t)(Ibeta) * (sinVal)) >> 31); - /* Intermediate product is calculated by (Ialpha * sinVal) */ - product3 = (q31_t) (((q63_t) (Ialpha) * (sinVal)) >> 31); + /* Intermediate product is calculated by (Ialpha * sinVal) */ + product3 = (q31_t)(((q63_t)(Ialpha) * (sinVal)) >> 31); - /* Intermediate product is calculated by (Ibeta * cosVal) */ - product4 = (q31_t) (((q63_t) (Ibeta) * (cosVal)) >> 31); + /* Intermediate product is calculated by (Ibeta * cosVal) */ + product4 = (q31_t)(((q63_t)(Ibeta) * (cosVal)) >> 31); - /* Calculate pId by adding the two intermediate products 1 and 2 */ - *pId = __QADD(product1, product2); + /* Calculate pId by adding the two intermediate products 1 and 2 */ + *pId = __QADD(product1, product2); - /* Calculate pIq by subtracting the two intermediate products 3 from 4 */ - *pIq = __QSUB(product4, product3); - } + /* Calculate pIq by subtracting the two intermediate products 3 from 4 */ + *pIq = __QSUB(product4, product3); + } - /** + /** * @} end of park group */ - /** + /** * @brief Converts the elements of the Q7 vector to floating-point vector. * @param[in] *pSrc is input pointer * @param[out] *pDst is output pointer * @param[in] blockSize is the number of samples to process * @return none. */ - void arm_q7_to_float( - q7_t * pSrc, - float32_t * pDst, - uint32_t blockSize); - + void arm_q7_to_float( + q7_t *pSrc, + float32_t *pDst, + uint32_t blockSize); - /** + /** * @ingroup groupController */ - /** + /** * @defgroup inv_park Vector Inverse Park transform * Inverse Park transform converts the input flux and torque components to two-coordinate vector. * @@ -5611,12 +5464,12 @@ void arm_rfft_fast_f32( * Refer to the function specific documentation below for usage guidelines. */ - /** + /** * @addtogroup inv_park * @{ */ - /** + /** * @brief Floating-point Inverse Park transform * @param[in] Id input coordinate of rotor reference frame d * @param[in] Iq input coordinate of rotor reference frame q @@ -5627,25 +5480,23 @@ void arm_rfft_fast_f32( * @return none. */ - static __INLINE void arm_inv_park_f32( - float32_t Id, - float32_t Iq, - float32_t * pIalpha, - float32_t * pIbeta, - float32_t sinVal, - float32_t cosVal) - { - /* Calculate pIalpha using the equation, pIalpha = Id * cosVal - Iq * sinVal */ - *pIalpha = Id * cosVal - Iq * sinVal; - - /* Calculate pIbeta using the equation, pIbeta = Id * sinVal + Iq * cosVal */ - *pIbeta = Id * sinVal + Iq * cosVal; - - } + static __INLINE void arm_inv_park_f32( + float32_t Id, + float32_t Iq, + float32_t *pIalpha, + float32_t *pIbeta, + float32_t sinVal, + float32_t cosVal) + { + /* Calculate pIalpha using the equation, pIalpha = Id * cosVal - Iq * sinVal */ + *pIalpha = Id * cosVal - Iq * sinVal; + /* Calculate pIbeta using the equation, pIbeta = Id * sinVal + Iq * cosVal */ + *pIbeta = Id * sinVal + Iq * cosVal; + } - /** - * @brief Inverse Park transform for Q31 version + /** + * @brief Inverse Park transform for Q31 version * @param[in] Id input coordinate of rotor reference frame d * @param[in] Iq input coordinate of rotor reference frame q * @param[out] *pIalpha points to output two-phase orthogonal vector axis alpha @@ -5661,61 +5512,57 @@ void arm_rfft_fast_f32( * There is saturation on the addition, hence there is no risk of overflow. */ + static __INLINE void arm_inv_park_q31( + q31_t Id, + q31_t Iq, + q31_t *pIalpha, + q31_t *pIbeta, + q31_t sinVal, + q31_t cosVal) + { + q31_t product1, product2; /* Temporary variables used to store intermediate results */ + q31_t product3, product4; /* Temporary variables used to store intermediate results */ - static __INLINE void arm_inv_park_q31( - q31_t Id, - q31_t Iq, - q31_t * pIalpha, - q31_t * pIbeta, - q31_t sinVal, - q31_t cosVal) - { - q31_t product1, product2; /* Temporary variables used to store intermediate results */ - q31_t product3, product4; /* Temporary variables used to store intermediate results */ - - /* Intermediate product is calculated by (Id * cosVal) */ - product1 = (q31_t) (((q63_t) (Id) * (cosVal)) >> 31); - - /* Intermediate product is calculated by (Iq * sinVal) */ - product2 = (q31_t) (((q63_t) (Iq) * (sinVal)) >> 31); - + /* Intermediate product is calculated by (Id * cosVal) */ + product1 = (q31_t)(((q63_t)(Id) * (cosVal)) >> 31); - /* Intermediate product is calculated by (Id * sinVal) */ - product3 = (q31_t) (((q63_t) (Id) * (sinVal)) >> 31); + /* Intermediate product is calculated by (Iq * sinVal) */ + product2 = (q31_t)(((q63_t)(Iq) * (sinVal)) >> 31); - /* Intermediate product is calculated by (Iq * cosVal) */ - product4 = (q31_t) (((q63_t) (Iq) * (cosVal)) >> 31); + /* Intermediate product is calculated by (Id * sinVal) */ + product3 = (q31_t)(((q63_t)(Id) * (sinVal)) >> 31); - /* Calculate pIalpha by using the two intermediate products 1 and 2 */ - *pIalpha = __QSUB(product1, product2); + /* Intermediate product is calculated by (Iq * cosVal) */ + product4 = (q31_t)(((q63_t)(Iq) * (cosVal)) >> 31); - /* Calculate pIbeta by using the two intermediate products 3 and 4 */ - *pIbeta = __QADD(product4, product3); + /* Calculate pIalpha by using the two intermediate products 1 and 2 */ + *pIalpha = __QSUB(product1, product2); - } + /* Calculate pIbeta by using the two intermediate products 3 and 4 */ + *pIbeta = __QADD(product4, product3); + } - /** + /** * @} end of Inverse park group */ - - /** + /** * @brief Converts the elements of the Q31 vector to floating-point vector. * @param[in] *pSrc is input pointer * @param[out] *pDst is output pointer * @param[in] blockSize is the number of samples to process * @return none. */ - void arm_q31_to_float( - q31_t * pSrc, - float32_t * pDst, - uint32_t blockSize); + void arm_q31_to_float( + q31_t *pSrc, + float32_t *pDst, + uint32_t blockSize); - /** + /** * @ingroup groupInterpolation */ - /** + /** * @defgroup LinearInterpolate Linear Interpolation * * Linear interpolation is a method of curve fitting using linear polynomials. @@ -5747,12 +5594,12 @@ void arm_rfft_fast_f32( * if x is below input range and returns last value of table if x is above range. */ - /** + /** * @addtogroup LinearInterpolate * @{ */ - /** + /** * @brief Process function for the floating-point Linear Interpolation Function. * @param[in,out] *S is an instance of the floating-point Linear Interpolation structure * @param[in] x input sample to process @@ -5760,51 +5607,50 @@ void arm_rfft_fast_f32( * */ - static __INLINE float32_t arm_linear_interp_f32( - arm_linear_interp_instance_f32 * S, - float32_t x) - { + static __INLINE float32_t arm_linear_interp_f32( + arm_linear_interp_instance_f32 *S, + float32_t x) + { - float32_t y; - float32_t x0, x1; /* Nearest input values */ - float32_t y0, y1; /* Nearest output values */ - float32_t xSpacing = S->xSpacing; /* spacing between input values */ - int32_t i; /* Index variable */ - float32_t *pYData = S->pYData; /* pointer to output table */ + float32_t y; + float32_t x0, x1; /* Nearest input values */ + float32_t y0, y1; /* Nearest output values */ + float32_t xSpacing = S->xSpacing; /* spacing between input values */ + int32_t i; /* Index variable */ + float32_t *pYData = S->pYData; /* pointer to output table */ - /* Calculation of index */ - i = (int32_t) ((x - S->x1) / xSpacing); + /* Calculation of index */ + i = (int32_t)((x - S->x1) / xSpacing); - if(i < 0) - { - /* Iniatilize output for below specified range as least output value of table */ - y = pYData[0]; - } - else if((uint32_t)i >= S->nValues) - { - /* Iniatilize output for above specified range as last output value of table */ - y = pYData[S->nValues - 1]; - } - else - { - /* Calculation of nearest input values */ - x0 = S->x1 + i * xSpacing; - x1 = S->x1 + (i + 1) * xSpacing; + if (i < 0) + { + /* Iniatilize output for below specified range as least output value of table */ + y = pYData[0]; + } + else if ((uint32_t)i >= S->nValues) + { + /* Iniatilize output for above specified range as last output value of table */ + y = pYData[S->nValues - 1]; + } + else + { + /* Calculation of nearest input values */ + x0 = S->x1 + i * xSpacing; + x1 = S->x1 + (i + 1) * xSpacing; - /* Read of nearest output values */ - y0 = pYData[i]; - y1 = pYData[i + 1]; + /* Read of nearest output values */ + y0 = pYData[i]; + y1 = pYData[i + 1]; - /* Calculation of output */ - y = y0 + (x - x0) * ((y1 - y0) / (x1 - x0)); + /* Calculation of output */ + y = y0 + (x - x0) * ((y1 - y0) / (x1 - x0)); + } + /* returns output value */ + return (y); } - /* returns output value */ - return (y); - } - - /** + /** * * @brief Process function for the Q31 Linear Interpolation Function. * @param[in] *pYData pointer to Q31 Linear Interpolation table @@ -5818,55 +5664,52 @@ void arm_rfft_fast_f32( * */ - - static __INLINE q31_t arm_linear_interp_q31( - q31_t * pYData, - q31_t x, - uint32_t nValues) - { - q31_t y; /* output */ - q31_t y0, y1; /* Nearest output values */ - q31_t fract; /* fractional part */ - int32_t index; /* Index to read nearest output values */ - - /* Input is in 12.20 format */ - /* 12 bits for the table index */ - /* Index value calculation */ - index = ((x & 0xFFF00000) >> 20); - - if(index >= (int32_t)(nValues - 1)) - { - return (pYData[nValues - 1]); - } - else if(index < 0) - { - return (pYData[0]); - } - else + static __INLINE q31_t arm_linear_interp_q31( + q31_t *pYData, + q31_t x, + uint32_t nValues) { + q31_t y; /* output */ + q31_t y0, y1; /* Nearest output values */ + q31_t fract; /* fractional part */ + int32_t index; /* Index to read nearest output values */ - /* 20 bits for the fractional part */ - /* shift left by 11 to keep fract in 1.31 format */ - fract = (x & 0x000FFFFF) << 11; + /* Input is in 12.20 format */ + /* 12 bits for the table index */ + /* Index value calculation */ + index = ((x & 0xFFF00000) >> 20); - /* Read two nearest output values from the index in 1.31(q31) format */ - y0 = pYData[index]; - y1 = pYData[index + 1u]; + if (index >= (int32_t)(nValues - 1)) + { + return (pYData[nValues - 1]); + } + else if (index < 0) + { + return (pYData[0]); + } + else + { - /* Calculation of y0 * (1-fract) and y is in 2.30 format */ - y = ((q31_t) ((q63_t) y0 * (0x7FFFFFFF - fract) >> 32)); + /* 20 bits for the fractional part */ + /* shift left by 11 to keep fract in 1.31 format */ + fract = (x & 0x000FFFFF) << 11; - /* Calculation of y0 * (1-fract) + y1 *fract and y is in 2.30 format */ - y += ((q31_t) (((q63_t) y1 * fract) >> 32)); + /* Read two nearest output values from the index in 1.31(q31) format */ + y0 = pYData[index]; + y1 = pYData[index + 1u]; - /* Convert y to 1.31 format */ - return (y << 1u); + /* Calculation of y0 * (1-fract) and y is in 2.30 format */ + y = ((q31_t)((q63_t)y0 * (0x7FFFFFFF - fract) >> 32)); - } + /* Calculation of y0 * (1-fract) + y1 *fract and y is in 2.30 format */ + y += ((q31_t)(((q63_t)y1 * fract) >> 32)); - } + /* Convert y to 1.31 format */ + return (y << 1u); + } + } - /** + /** * * @brief Process function for the Q15 Linear Interpolation Function. * @param[in] *pYData pointer to Q15 Linear Interpolation table @@ -5880,54 +5723,51 @@ void arm_rfft_fast_f32( * */ - - static __INLINE q15_t arm_linear_interp_q15( - q15_t * pYData, - q31_t x, - uint32_t nValues) - { - q63_t y; /* output */ - q15_t y0, y1; /* Nearest output values */ - q31_t fract; /* fractional part */ - int32_t index; /* Index to read nearest output values */ - - /* Input is in 12.20 format */ - /* 12 bits for the table index */ - /* Index value calculation */ - index = ((x & 0xFFF00000) >> 20u); - - if(index >= (int32_t)(nValues - 1)) + static __INLINE q15_t arm_linear_interp_q15( + q15_t *pYData, + q31_t x, + uint32_t nValues) { - return (pYData[nValues - 1]); - } - else if(index < 0) - { - return (pYData[0]); - } - else - { - /* 20 bits for the fractional part */ - /* fract is in 12.20 format */ - fract = (x & 0x000FFFFF); + q63_t y; /* output */ + q15_t y0, y1; /* Nearest output values */ + q31_t fract; /* fractional part */ + int32_t index; /* Index to read nearest output values */ - /* Read two nearest output values from the index */ - y0 = pYData[index]; - y1 = pYData[index + 1u]; + /* Input is in 12.20 format */ + /* 12 bits for the table index */ + /* Index value calculation */ + index = ((x & 0xFFF00000) >> 20u); - /* Calculation of y0 * (1-fract) and y is in 13.35 format */ - y = ((q63_t) y0 * (0xFFFFF - fract)); + if (index >= (int32_t)(nValues - 1)) + { + return (pYData[nValues - 1]); + } + else if (index < 0) + { + return (pYData[0]); + } + else + { + /* 20 bits for the fractional part */ + /* fract is in 12.20 format */ + fract = (x & 0x000FFFFF); - /* Calculation of (y0 * (1-fract) + y1 * fract) and y is in 13.35 format */ - y += ((q63_t) y1 * (fract)); + /* Read two nearest output values from the index */ + y0 = pYData[index]; + y1 = pYData[index + 1u]; - /* convert y to 1.15 format */ - return (y >> 20); - } + /* Calculation of y0 * (1-fract) and y is in 13.35 format */ + y = ((q63_t)y0 * (0xFFFFF - fract)); + /* Calculation of (y0 * (1-fract) + y1 * fract) and y is in 13.35 format */ + y += ((q63_t)y1 * (fract)); - } + /* convert y to 1.15 format */ + return (y >> 20); + } + } - /** + /** * * @brief Process function for the Q7 Linear Interpolation Function. * @param[in] *pYData pointer to Q7 Linear Interpolation table @@ -5940,119 +5780,113 @@ void arm_rfft_fast_f32( * This function can support maximum of table size 2^12. */ - - static __INLINE q7_t arm_linear_interp_q7( - q7_t * pYData, - q31_t x, - uint32_t nValues) - { - q31_t y; /* output */ - q7_t y0, y1; /* Nearest output values */ - q31_t fract; /* fractional part */ - uint32_t index; /* Index to read nearest output values */ - - /* Input is in 12.20 format */ - /* 12 bits for the table index */ - /* Index value calculation */ - if (x < 0) + static __INLINE q7_t arm_linear_interp_q7( + q7_t *pYData, + q31_t x, + uint32_t nValues) { - return (pYData[0]); - } - index = (x >> 20) & 0xfff; - + q31_t y; /* output */ + q7_t y0, y1; /* Nearest output values */ + q31_t fract; /* fractional part */ + uint32_t index; /* Index to read nearest output values */ - if(index >= (nValues - 1)) - { - return (pYData[nValues - 1]); - } - else - { + /* Input is in 12.20 format */ + /* 12 bits for the table index */ + /* Index value calculation */ + if (x < 0) + { + return (pYData[0]); + } + index = (x >> 20) & 0xfff; - /* 20 bits for the fractional part */ - /* fract is in 12.20 format */ - fract = (x & 0x000FFFFF); + if (index >= (nValues - 1)) + { + return (pYData[nValues - 1]); + } + else + { - /* Read two nearest output values from the index and are in 1.7(q7) format */ - y0 = pYData[index]; - y1 = pYData[index + 1u]; + /* 20 bits for the fractional part */ + /* fract is in 12.20 format */ + fract = (x & 0x000FFFFF); - /* Calculation of y0 * (1-fract ) and y is in 13.27(q27) format */ - y = ((y0 * (0xFFFFF - fract))); + /* Read two nearest output values from the index and are in 1.7(q7) format */ + y0 = pYData[index]; + y1 = pYData[index + 1u]; - /* Calculation of y1 * fract + y0 * (1-fract) and y is in 13.27(q27) format */ - y += (y1 * fract); + /* Calculation of y0 * (1-fract ) and y is in 13.27(q27) format */ + y = ((y0 * (0xFFFFF - fract))); - /* convert y to 1.7(q7) format */ - return (y >> 20u); + /* Calculation of y1 * fract + y0 * (1-fract) and y is in 13.27(q27) format */ + y += (y1 * fract); + /* convert y to 1.7(q7) format */ + return (y >> 20u); + } } - - } - /** + /** * @} end of LinearInterpolate group */ - /** + /** * @brief Fast approximation to the trigonometric sine function for floating-point data. * @param[in] x input value in radians. * @return sin(x). */ - float32_t arm_sin_f32( - float32_t x); + float32_t arm_sin_f32( + float32_t x); - /** + /** * @brief Fast approximation to the trigonometric sine function for Q31 data. * @param[in] x Scaled input value in radians. * @return sin(x). */ - q31_t arm_sin_q31( - q31_t x); + q31_t arm_sin_q31( + q31_t x); - /** + /** * @brief Fast approximation to the trigonometric sine function for Q15 data. * @param[in] x Scaled input value in radians. * @return sin(x). */ - q15_t arm_sin_q15( - q15_t x); + q15_t arm_sin_q15( + q15_t x); - /** + /** * @brief Fast approximation to the trigonometric cosine function for floating-point data. * @param[in] x input value in radians. * @return cos(x). */ - float32_t arm_cos_f32( - float32_t x); + float32_t arm_cos_f32( + float32_t x); - /** + /** * @brief Fast approximation to the trigonometric cosine function for Q31 data. * @param[in] x Scaled input value in radians. * @return cos(x). */ - q31_t arm_cos_q31( - q31_t x); + q31_t arm_cos_q31( + q31_t x); - /** + /** * @brief Fast approximation to the trigonometric cosine function for Q15 data. * @param[in] x Scaled input value in radians. * @return cos(x). */ - q15_t arm_cos_q15( - q15_t x); + q15_t arm_cos_q15( + q15_t x); - - /** + /** * @ingroup groupFastMath */ - - /** + /** * @defgroup SQRT Square Root * * Computes the square root of a number. @@ -6072,13 +5906,12 @@ void arm_rfft_fast_f32( * </pre> */ - - /** + /** * @addtogroup SQRT * @{ */ - /** + /** * @brief Floating-point square root function. * @param[in] in input value. * @param[out] *pOut square root of input value. @@ -6086,367 +5919,352 @@ void arm_rfft_fast_f32( * <code>in</code> is negative value and returns zero output for negative values. */ - static __INLINE arm_status arm_sqrt_f32( - float32_t in, - float32_t * pOut) - { - if(in > 0) + static __INLINE arm_status arm_sqrt_f32( + float32_t in, + float32_t *pOut) { + if (in > 0) + { // #if __FPU_USED -#if (__FPU_USED == 1) && defined ( __CC_ARM ) - *pOut = __sqrtf(in); +#if (__FPU_USED == 1) && defined(__CC_ARM) + *pOut = __sqrtf(in); #else - *pOut = sqrtf(in); + *pOut = sqrtf(in); #endif - return (ARM_MATH_SUCCESS); - } - else - { - *pOut = 0.0f; - return (ARM_MATH_ARGUMENT_ERROR); + return (ARM_MATH_SUCCESS); + } + else + { + *pOut = 0.0f; + return (ARM_MATH_ARGUMENT_ERROR); + } } - } - - - /** + /** * @brief Q31 square root function. * @param[in] in input value. The range of the input value is [0 +1) or 0x00000000 to 0x7FFFFFFF. * @param[out] *pOut square root of input value. * @return The function returns ARM_MATH_SUCCESS if input value is positive value or ARM_MATH_ARGUMENT_ERROR if * <code>in</code> is negative value and returns zero output for negative values. */ - arm_status arm_sqrt_q31( - q31_t in, - q31_t * pOut); + arm_status arm_sqrt_q31( + q31_t in, + q31_t *pOut); - /** + /** * @brief Q15 square root function. * @param[in] in input value. The range of the input value is [0 +1) or 0x0000 to 0x7FFF. * @param[out] *pOut square root of input value. * @return The function returns ARM_MATH_SUCCESS if input value is positive value or ARM_MATH_ARGUMENT_ERROR if * <code>in</code> is negative value and returns zero output for negative values. */ - arm_status arm_sqrt_q15( - q15_t in, - q15_t * pOut); + arm_status arm_sqrt_q15( + q15_t in, + q15_t *pOut); - /** + /** * @} end of SQRT group */ - - - - - - /** + /** * @brief floating-point Circular write function. */ - static __INLINE void arm_circularWrite_f32( - int32_t * circBuffer, - int32_t L, - uint16_t * writeOffset, - int32_t bufferInc, - const int32_t * src, - int32_t srcInc, - uint32_t blockSize) - { - uint32_t i = 0u; - int32_t wOffset; + static __INLINE void arm_circularWrite_f32( + int32_t *circBuffer, + int32_t L, + uint16_t *writeOffset, + int32_t bufferInc, + const int32_t *src, + int32_t srcInc, + uint32_t blockSize) + { + uint32_t i = 0u; + int32_t wOffset; - /* Copy the value of Index pointer that points + /* Copy the value of Index pointer that points * to the current location where the input samples to be copied */ - wOffset = *writeOffset; - - /* Loop over the blockSize */ - i = blockSize; - - while(i > 0u) - { - /* copy the input sample to the circular buffer */ - circBuffer[wOffset] = *src; + wOffset = *writeOffset; - /* Update the input pointer */ - src += srcInc; + /* Loop over the blockSize */ + i = blockSize; - /* Circularly update wOffset. Watch out for positive and negative value */ - wOffset += bufferInc; - if(wOffset >= L) - wOffset -= L; + while (i > 0u) + { + /* copy the input sample to the circular buffer */ + circBuffer[wOffset] = *src; - /* Decrement the loop counter */ - i--; - } + /* Update the input pointer */ + src += srcInc; - /* Update the index pointer */ - *writeOffset = wOffset; - } + /* Circularly update wOffset. Watch out for positive and negative value */ + wOffset += bufferInc; + if (wOffset >= L) + wOffset -= L; + /* Decrement the loop counter */ + i--; + } + /* Update the index pointer */ + *writeOffset = wOffset; + } - /** + /** * @brief floating-point Circular Read function. */ - static __INLINE void arm_circularRead_f32( - int32_t * circBuffer, - int32_t L, - int32_t * readOffset, - int32_t bufferInc, - int32_t * dst, - int32_t * dst_base, - int32_t dst_length, - int32_t dstInc, - uint32_t blockSize) - { - uint32_t i = 0u; - int32_t rOffset, dst_end; + static __INLINE void arm_circularRead_f32( + int32_t *circBuffer, + int32_t L, + int32_t *readOffset, + int32_t bufferInc, + int32_t *dst, + int32_t *dst_base, + int32_t dst_length, + int32_t dstInc, + uint32_t blockSize) + { + uint32_t i = 0u; + int32_t rOffset, dst_end; - /* Copy the value of Index pointer that points + /* Copy the value of Index pointer that points * to the current location from where the input samples to be read */ - rOffset = *readOffset; - dst_end = (int32_t) (dst_base + dst_length); + rOffset = *readOffset; + dst_end = (int32_t)(dst_base + dst_length); - /* Loop over the blockSize */ - i = blockSize; + /* Loop over the blockSize */ + i = blockSize; - while(i > 0u) - { - /* copy the sample from the circular buffer to the destination buffer */ - *dst = circBuffer[rOffset]; + while (i > 0u) + { + /* copy the sample from the circular buffer to the destination buffer */ + *dst = circBuffer[rOffset]; - /* Update the input pointer */ - dst += dstInc; + /* Update the input pointer */ + dst += dstInc; - if(dst == (int32_t *) dst_end) - { - dst = dst_base; - } + if (dst == (int32_t *)dst_end) + { + dst = dst_base; + } - /* Circularly update rOffset. Watch out for positive and negative value */ - rOffset += bufferInc; + /* Circularly update rOffset. Watch out for positive and negative value */ + rOffset += bufferInc; - if(rOffset >= L) - { - rOffset -= L; - } + if (rOffset >= L) + { + rOffset -= L; + } - /* Decrement the loop counter */ - i--; - } + /* Decrement the loop counter */ + i--; + } - /* Update the index pointer */ - *readOffset = rOffset; - } + /* Update the index pointer */ + *readOffset = rOffset; + } - /** + /** * @brief Q15 Circular write function. */ - static __INLINE void arm_circularWrite_q15( - q15_t * circBuffer, - int32_t L, - uint16_t * writeOffset, - int32_t bufferInc, - const q15_t * src, - int32_t srcInc, - uint32_t blockSize) - { - uint32_t i = 0u; - int32_t wOffset; + static __INLINE void arm_circularWrite_q15( + q15_t *circBuffer, + int32_t L, + uint16_t *writeOffset, + int32_t bufferInc, + const q15_t *src, + int32_t srcInc, + uint32_t blockSize) + { + uint32_t i = 0u; + int32_t wOffset; - /* Copy the value of Index pointer that points + /* Copy the value of Index pointer that points * to the current location where the input samples to be copied */ - wOffset = *writeOffset; - - /* Loop over the blockSize */ - i = blockSize; + wOffset = *writeOffset; - while(i > 0u) - { - /* copy the input sample to the circular buffer */ - circBuffer[wOffset] = *src; - - /* Update the input pointer */ - src += srcInc; + /* Loop over the blockSize */ + i = blockSize; - /* Circularly update wOffset. Watch out for positive and negative value */ - wOffset += bufferInc; - if(wOffset >= L) - wOffset -= L; + while (i > 0u) + { + /* copy the input sample to the circular buffer */ + circBuffer[wOffset] = *src; - /* Decrement the loop counter */ - i--; - } + /* Update the input pointer */ + src += srcInc; - /* Update the index pointer */ - *writeOffset = wOffset; - } + /* Circularly update wOffset. Watch out for positive and negative value */ + wOffset += bufferInc; + if (wOffset >= L) + wOffset -= L; + /* Decrement the loop counter */ + i--; + } + /* Update the index pointer */ + *writeOffset = wOffset; + } - /** + /** * @brief Q15 Circular Read function. */ - static __INLINE void arm_circularRead_q15( - q15_t * circBuffer, - int32_t L, - int32_t * readOffset, - int32_t bufferInc, - q15_t * dst, - q15_t * dst_base, - int32_t dst_length, - int32_t dstInc, - uint32_t blockSize) - { - uint32_t i = 0; - int32_t rOffset, dst_end; + static __INLINE void arm_circularRead_q15( + q15_t *circBuffer, + int32_t L, + int32_t *readOffset, + int32_t bufferInc, + q15_t *dst, + q15_t *dst_base, + int32_t dst_length, + int32_t dstInc, + uint32_t blockSize) + { + uint32_t i = 0; + int32_t rOffset, dst_end; - /* Copy the value of Index pointer that points + /* Copy the value of Index pointer that points * to the current location from where the input samples to be read */ - rOffset = *readOffset; + rOffset = *readOffset; - dst_end = (int32_t) (dst_base + dst_length); + dst_end = (int32_t)(dst_base + dst_length); - /* Loop over the blockSize */ - i = blockSize; + /* Loop over the blockSize */ + i = blockSize; - while(i > 0u) - { - /* copy the sample from the circular buffer to the destination buffer */ - *dst = circBuffer[rOffset]; + while (i > 0u) + { + /* copy the sample from the circular buffer to the destination buffer */ + *dst = circBuffer[rOffset]; - /* Update the input pointer */ - dst += dstInc; + /* Update the input pointer */ + dst += dstInc; - if(dst == (q15_t *) dst_end) - { - dst = dst_base; - } + if (dst == (q15_t *)dst_end) + { + dst = dst_base; + } - /* Circularly update wOffset. Watch out for positive and negative value */ - rOffset += bufferInc; + /* Circularly update wOffset. Watch out for positive and negative value */ + rOffset += bufferInc; - if(rOffset >= L) - { - rOffset -= L; - } + if (rOffset >= L) + { + rOffset -= L; + } - /* Decrement the loop counter */ - i--; - } - - /* Update the index pointer */ - *readOffset = rOffset; - } + /* Decrement the loop counter */ + i--; + } + /* Update the index pointer */ + *readOffset = rOffset; + } - /** + /** * @brief Q7 Circular write function. */ - static __INLINE void arm_circularWrite_q7( - q7_t * circBuffer, - int32_t L, - uint16_t * writeOffset, - int32_t bufferInc, - const q7_t * src, - int32_t srcInc, - uint32_t blockSize) - { - uint32_t i = 0u; - int32_t wOffset; + static __INLINE void arm_circularWrite_q7( + q7_t *circBuffer, + int32_t L, + uint16_t *writeOffset, + int32_t bufferInc, + const q7_t *src, + int32_t srcInc, + uint32_t blockSize) + { + uint32_t i = 0u; + int32_t wOffset; - /* Copy the value of Index pointer that points + /* Copy the value of Index pointer that points * to the current location where the input samples to be copied */ - wOffset = *writeOffset; - - /* Loop over the blockSize */ - i = blockSize; + wOffset = *writeOffset; - while(i > 0u) - { - /* copy the input sample to the circular buffer */ - circBuffer[wOffset] = *src; - - /* Update the input pointer */ - src += srcInc; + /* Loop over the blockSize */ + i = blockSize; - /* Circularly update wOffset. Watch out for positive and negative value */ - wOffset += bufferInc; - if(wOffset >= L) - wOffset -= L; + while (i > 0u) + { + /* copy the input sample to the circular buffer */ + circBuffer[wOffset] = *src; - /* Decrement the loop counter */ - i--; - } + /* Update the input pointer */ + src += srcInc; - /* Update the index pointer */ - *writeOffset = wOffset; - } + /* Circularly update wOffset. Watch out for positive and negative value */ + wOffset += bufferInc; + if (wOffset >= L) + wOffset -= L; + /* Decrement the loop counter */ + i--; + } + /* Update the index pointer */ + *writeOffset = wOffset; + } - /** + /** * @brief Q7 Circular Read function. */ - static __INLINE void arm_circularRead_q7( - q7_t * circBuffer, - int32_t L, - int32_t * readOffset, - int32_t bufferInc, - q7_t * dst, - q7_t * dst_base, - int32_t dst_length, - int32_t dstInc, - uint32_t blockSize) - { - uint32_t i = 0; - int32_t rOffset, dst_end; + static __INLINE void arm_circularRead_q7( + q7_t *circBuffer, + int32_t L, + int32_t *readOffset, + int32_t bufferInc, + q7_t *dst, + q7_t *dst_base, + int32_t dst_length, + int32_t dstInc, + uint32_t blockSize) + { + uint32_t i = 0; + int32_t rOffset, dst_end; - /* Copy the value of Index pointer that points + /* Copy the value of Index pointer that points * to the current location from where the input samples to be read */ - rOffset = *readOffset; + rOffset = *readOffset; - dst_end = (int32_t) (dst_base + dst_length); + dst_end = (int32_t)(dst_base + dst_length); - /* Loop over the blockSize */ - i = blockSize; + /* Loop over the blockSize */ + i = blockSize; - while(i > 0u) - { - /* copy the sample from the circular buffer to the destination buffer */ - *dst = circBuffer[rOffset]; + while (i > 0u) + { + /* copy the sample from the circular buffer to the destination buffer */ + *dst = circBuffer[rOffset]; - /* Update the input pointer */ - dst += dstInc; + /* Update the input pointer */ + dst += dstInc; - if(dst == (q7_t *) dst_end) - { - dst = dst_base; - } + if (dst == (q7_t *)dst_end) + { + dst = dst_base; + } - /* Circularly update rOffset. Watch out for positive and negative value */ - rOffset += bufferInc; + /* Circularly update rOffset. Watch out for positive and negative value */ + rOffset += bufferInc; - if(rOffset >= L) - { - rOffset -= L; - } + if (rOffset >= L) + { + rOffset -= L; + } - /* Decrement the loop counter */ - i--; - } - - /* Update the index pointer */ - *readOffset = rOffset; - } + /* Decrement the loop counter */ + i--; + } + /* Update the index pointer */ + *readOffset = rOffset; + } - /** + /** * @brief Sum of the squares of the elements of a Q31 vector. * @param[in] *pSrc is input pointer * @param[in] blockSize is the number of samples to process @@ -6454,12 +6272,12 @@ void arm_rfft_fast_f32( * @return none. */ - void arm_power_q31( - q31_t * pSrc, - uint32_t blockSize, - q63_t * pResult); + void arm_power_q31( + q31_t *pSrc, + uint32_t blockSize, + q63_t *pResult); - /** + /** * @brief Sum of the squares of the elements of a floating-point vector. * @param[in] *pSrc is input pointer * @param[in] blockSize is the number of samples to process @@ -6467,12 +6285,12 @@ void arm_rfft_fast_f32( * @return none. */ - void arm_power_f32( - float32_t * pSrc, - uint32_t blockSize, - float32_t * pResult); + void arm_power_f32( + float32_t *pSrc, + uint32_t blockSize, + float32_t *pResult); - /** + /** * @brief Sum of the squares of the elements of a Q15 vector. * @param[in] *pSrc is input pointer * @param[in] blockSize is the number of samples to process @@ -6480,12 +6298,12 @@ void arm_rfft_fast_f32( * @return none. */ - void arm_power_q15( - q15_t * pSrc, - uint32_t blockSize, - q63_t * pResult); + void arm_power_q15( + q15_t *pSrc, + uint32_t blockSize, + q63_t *pResult); - /** + /** * @brief Sum of the squares of the elements of a Q7 vector. * @param[in] *pSrc is input pointer * @param[in] blockSize is the number of samples to process @@ -6493,12 +6311,12 @@ void arm_rfft_fast_f32( * @return none. */ - void arm_power_q7( - q7_t * pSrc, - uint32_t blockSize, - q31_t * pResult); + void arm_power_q7( + q7_t *pSrc, + uint32_t blockSize, + q31_t *pResult); - /** + /** * @brief Mean value of a Q7 vector. * @param[in] *pSrc is input pointer * @param[in] blockSize is the number of samples to process @@ -6506,48 +6324,48 @@ void arm_rfft_fast_f32( * @return none. */ - void arm_mean_q7( - q7_t * pSrc, - uint32_t blockSize, - q7_t * pResult); + void arm_mean_q7( + q7_t *pSrc, + uint32_t blockSize, + q7_t *pResult); - /** + /** * @brief Mean value of a Q15 vector. * @param[in] *pSrc is input pointer * @param[in] blockSize is the number of samples to process * @param[out] *pResult is output value. * @return none. */ - void arm_mean_q15( - q15_t * pSrc, - uint32_t blockSize, - q15_t * pResult); + void arm_mean_q15( + q15_t *pSrc, + uint32_t blockSize, + q15_t *pResult); - /** + /** * @brief Mean value of a Q31 vector. * @param[in] *pSrc is input pointer * @param[in] blockSize is the number of samples to process * @param[out] *pResult is output value. * @return none. */ - void arm_mean_q31( - q31_t * pSrc, - uint32_t blockSize, - q31_t * pResult); + void arm_mean_q31( + q31_t *pSrc, + uint32_t blockSize, + q31_t *pResult); - /** + /** * @brief Mean value of a floating-point vector. * @param[in] *pSrc is input pointer * @param[in] blockSize is the number of samples to process * @param[out] *pResult is output value. * @return none. */ - void arm_mean_f32( - float32_t * pSrc, - uint32_t blockSize, - float32_t * pResult); + void arm_mean_f32( + float32_t *pSrc, + uint32_t blockSize, + float32_t *pResult); - /** + /** * @brief Variance of the elements of a floating-point vector. * @param[in] *pSrc is input pointer * @param[in] blockSize is the number of samples to process @@ -6555,12 +6373,12 @@ void arm_rfft_fast_f32( * @return none. */ - void arm_var_f32( - float32_t * pSrc, - uint32_t blockSize, - float32_t * pResult); + void arm_var_f32( + float32_t *pSrc, + uint32_t blockSize, + float32_t *pResult); - /** + /** * @brief Variance of the elements of a Q31 vector. * @param[in] *pSrc is input pointer * @param[in] blockSize is the number of samples to process @@ -6568,12 +6386,12 @@ void arm_rfft_fast_f32( * @return none. */ - void arm_var_q31( - q31_t * pSrc, - uint32_t blockSize, - q31_t * pResult); + void arm_var_q31( + q31_t *pSrc, + uint32_t blockSize, + q31_t *pResult); - /** + /** * @brief Variance of the elements of a Q15 vector. * @param[in] *pSrc is input pointer * @param[in] blockSize is the number of samples to process @@ -6581,12 +6399,12 @@ void arm_rfft_fast_f32( * @return none. */ - void arm_var_q15( - q15_t * pSrc, - uint32_t blockSize, - q15_t * pResult); + void arm_var_q15( + q15_t *pSrc, + uint32_t blockSize, + q15_t *pResult); - /** + /** * @brief Root Mean Square of the elements of a floating-point vector. * @param[in] *pSrc is input pointer * @param[in] blockSize is the number of samples to process @@ -6594,12 +6412,12 @@ void arm_rfft_fast_f32( * @return none. */ - void arm_rms_f32( - float32_t * pSrc, - uint32_t blockSize, - float32_t * pResult); + void arm_rms_f32( + float32_t *pSrc, + uint32_t blockSize, + float32_t *pResult); - /** + /** * @brief Root Mean Square of the elements of a Q31 vector. * @param[in] *pSrc is input pointer * @param[in] blockSize is the number of samples to process @@ -6607,12 +6425,12 @@ void arm_rfft_fast_f32( * @return none. */ - void arm_rms_q31( - q31_t * pSrc, - uint32_t blockSize, - q31_t * pResult); + void arm_rms_q31( + q31_t *pSrc, + uint32_t blockSize, + q31_t *pResult); - /** + /** * @brief Root Mean Square of the elements of a Q15 vector. * @param[in] *pSrc is input pointer * @param[in] blockSize is the number of samples to process @@ -6620,12 +6438,12 @@ void arm_rfft_fast_f32( * @return none. */ - void arm_rms_q15( - q15_t * pSrc, - uint32_t blockSize, - q15_t * pResult); + void arm_rms_q15( + q15_t *pSrc, + uint32_t blockSize, + q15_t *pResult); - /** + /** * @brief Standard deviation of the elements of a floating-point vector. * @param[in] *pSrc is input pointer * @param[in] blockSize is the number of samples to process @@ -6633,12 +6451,12 @@ void arm_rfft_fast_f32( * @return none. */ - void arm_std_f32( - float32_t * pSrc, - uint32_t blockSize, - float32_t * pResult); + void arm_std_f32( + float32_t *pSrc, + uint32_t blockSize, + float32_t *pResult); - /** + /** * @brief Standard deviation of the elements of a Q31 vector. * @param[in] *pSrc is input pointer * @param[in] blockSize is the number of samples to process @@ -6646,12 +6464,12 @@ void arm_rfft_fast_f32( * @return none. */ - void arm_std_q31( - q31_t * pSrc, - uint32_t blockSize, - q31_t * pResult); + void arm_std_q31( + q31_t *pSrc, + uint32_t blockSize, + q31_t *pResult); - /** + /** * @brief Standard deviation of the elements of a Q15 vector. * @param[in] *pSrc is input pointer * @param[in] blockSize is the number of samples to process @@ -6659,12 +6477,12 @@ void arm_rfft_fast_f32( * @return none. */ - void arm_std_q15( - q15_t * pSrc, - uint32_t blockSize, - q15_t * pResult); + void arm_std_q15( + q15_t *pSrc, + uint32_t blockSize, + q15_t *pResult); - /** + /** * @brief Floating-point complex magnitude * @param[in] *pSrc points to the complex input vector * @param[out] *pDst points to the real output vector @@ -6672,12 +6490,12 @@ void arm_rfft_fast_f32( * @return none. */ - void arm_cmplx_mag_f32( - float32_t * pSrc, - float32_t * pDst, - uint32_t numSamples); + void arm_cmplx_mag_f32( + float32_t *pSrc, + float32_t *pDst, + uint32_t numSamples); - /** + /** * @brief Q31 complex magnitude * @param[in] *pSrc points to the complex input vector * @param[out] *pDst points to the real output vector @@ -6685,12 +6503,12 @@ void arm_rfft_fast_f32( * @return none. */ - void arm_cmplx_mag_q31( - q31_t * pSrc, - q31_t * pDst, - uint32_t numSamples); + void arm_cmplx_mag_q31( + q31_t *pSrc, + q31_t *pDst, + uint32_t numSamples); - /** + /** * @brief Q15 complex magnitude * @param[in] *pSrc points to the complex input vector * @param[out] *pDst points to the real output vector @@ -6698,12 +6516,12 @@ void arm_rfft_fast_f32( * @return none. */ - void arm_cmplx_mag_q15( - q15_t * pSrc, - q15_t * pDst, - uint32_t numSamples); + void arm_cmplx_mag_q15( + q15_t *pSrc, + q15_t *pDst, + uint32_t numSamples); - /** + /** * @brief Q15 complex dot product * @param[in] *pSrcA points to the first input vector * @param[in] *pSrcB points to the second input vector @@ -6713,14 +6531,14 @@ void arm_rfft_fast_f32( * @return none. */ - void arm_cmplx_dot_prod_q15( - q15_t * pSrcA, - q15_t * pSrcB, - uint32_t numSamples, - q31_t * realResult, - q31_t * imagResult); + void arm_cmplx_dot_prod_q15( + q15_t *pSrcA, + q15_t *pSrcB, + uint32_t numSamples, + q31_t *realResult, + q31_t *imagResult); - /** + /** * @brief Q31 complex dot product * @param[in] *pSrcA points to the first input vector * @param[in] *pSrcB points to the second input vector @@ -6730,14 +6548,14 @@ void arm_rfft_fast_f32( * @return none. */ - void arm_cmplx_dot_prod_q31( - q31_t * pSrcA, - q31_t * pSrcB, - uint32_t numSamples, - q63_t * realResult, - q63_t * imagResult); + void arm_cmplx_dot_prod_q31( + q31_t *pSrcA, + q31_t *pSrcB, + uint32_t numSamples, + q63_t *realResult, + q63_t *imagResult); - /** + /** * @brief Floating-point complex dot product * @param[in] *pSrcA points to the first input vector * @param[in] *pSrcB points to the second input vector @@ -6747,14 +6565,14 @@ void arm_rfft_fast_f32( * @return none. */ - void arm_cmplx_dot_prod_f32( - float32_t * pSrcA, - float32_t * pSrcB, - uint32_t numSamples, - float32_t * realResult, - float32_t * imagResult); + void arm_cmplx_dot_prod_f32( + float32_t *pSrcA, + float32_t *pSrcB, + uint32_t numSamples, + float32_t *realResult, + float32_t *imagResult); - /** + /** * @brief Q15 complex-by-real multiplication * @param[in] *pSrcCmplx points to the complex input vector * @param[in] *pSrcReal points to the real input vector @@ -6763,13 +6581,13 @@ void arm_rfft_fast_f32( * @return none. */ - void arm_cmplx_mult_real_q15( - q15_t * pSrcCmplx, - q15_t * pSrcReal, - q15_t * pCmplxDst, - uint32_t numSamples); + void arm_cmplx_mult_real_q15( + q15_t *pSrcCmplx, + q15_t *pSrcReal, + q15_t *pCmplxDst, + uint32_t numSamples); - /** + /** * @brief Q31 complex-by-real multiplication * @param[in] *pSrcCmplx points to the complex input vector * @param[in] *pSrcReal points to the real input vector @@ -6778,13 +6596,13 @@ void arm_rfft_fast_f32( * @return none. */ - void arm_cmplx_mult_real_q31( - q31_t * pSrcCmplx, - q31_t * pSrcReal, - q31_t * pCmplxDst, - uint32_t numSamples); + void arm_cmplx_mult_real_q31( + q31_t *pSrcCmplx, + q31_t *pSrcReal, + q31_t *pCmplxDst, + uint32_t numSamples); - /** + /** * @brief Floating-point complex-by-real multiplication * @param[in] *pSrcCmplx points to the complex input vector * @param[in] *pSrcReal points to the real input vector @@ -6793,13 +6611,13 @@ void arm_rfft_fast_f32( * @return none. */ - void arm_cmplx_mult_real_f32( - float32_t * pSrcCmplx, - float32_t * pSrcReal, - float32_t * pCmplxDst, - uint32_t numSamples); + void arm_cmplx_mult_real_f32( + float32_t *pSrcCmplx, + float32_t *pSrcReal, + float32_t *pCmplxDst, + uint32_t numSamples); - /** + /** * @brief Minimum value of a Q7 vector. * @param[in] *pSrc is input pointer * @param[in] blockSize is the number of samples to process @@ -6808,13 +6626,13 @@ void arm_rfft_fast_f32( * @return none. */ - void arm_min_q7( - q7_t * pSrc, - uint32_t blockSize, - q7_t * result, - uint32_t * index); + void arm_min_q7( + q7_t *pSrc, + uint32_t blockSize, + q7_t *result, + uint32_t *index); - /** + /** * @brief Minimum value of a Q15 vector. * @param[in] *pSrc is input pointer * @param[in] blockSize is the number of samples to process @@ -6823,13 +6641,13 @@ void arm_rfft_fast_f32( * @return none. */ - void arm_min_q15( - q15_t * pSrc, - uint32_t blockSize, - q15_t * pResult, - uint32_t * pIndex); + void arm_min_q15( + q15_t *pSrc, + uint32_t blockSize, + q15_t *pResult, + uint32_t *pIndex); - /** + /** * @brief Minimum value of a Q31 vector. * @param[in] *pSrc is input pointer * @param[in] blockSize is the number of samples to process @@ -6837,13 +6655,13 @@ void arm_rfft_fast_f32( * @param[out] *pIndex is the array index of the minimum value in the input buffer. * @return none. */ - void arm_min_q31( - q31_t * pSrc, - uint32_t blockSize, - q31_t * pResult, - uint32_t * pIndex); + void arm_min_q31( + q31_t *pSrc, + uint32_t blockSize, + q31_t *pResult, + uint32_t *pIndex); - /** + /** * @brief Minimum value of a floating-point vector. * @param[in] *pSrc is input pointer * @param[in] blockSize is the number of samples to process @@ -6852,13 +6670,13 @@ void arm_rfft_fast_f32( * @return none. */ - void arm_min_f32( - float32_t * pSrc, - uint32_t blockSize, - float32_t * pResult, - uint32_t * pIndex); + void arm_min_f32( + float32_t *pSrc, + uint32_t blockSize, + float32_t *pResult, + uint32_t *pIndex); -/** + /** * @brief Maximum value of a Q7 vector. * @param[in] *pSrc points to the input buffer * @param[in] blockSize length of the input vector @@ -6867,13 +6685,13 @@ void arm_rfft_fast_f32( * @return none. */ - void arm_max_q7( - q7_t * pSrc, - uint32_t blockSize, - q7_t * pResult, - uint32_t * pIndex); + void arm_max_q7( + q7_t *pSrc, + uint32_t blockSize, + q7_t *pResult, + uint32_t *pIndex); -/** + /** * @brief Maximum value of a Q15 vector. * @param[in] *pSrc points to the input buffer * @param[in] blockSize length of the input vector @@ -6882,13 +6700,13 @@ void arm_rfft_fast_f32( * @return none. */ - void arm_max_q15( - q15_t * pSrc, - uint32_t blockSize, - q15_t * pResult, - uint32_t * pIndex); + void arm_max_q15( + q15_t *pSrc, + uint32_t blockSize, + q15_t *pResult, + uint32_t *pIndex); -/** + /** * @brief Maximum value of a Q31 vector. * @param[in] *pSrc points to the input buffer * @param[in] blockSize length of the input vector @@ -6897,13 +6715,13 @@ void arm_rfft_fast_f32( * @return none. */ - void arm_max_q31( - q31_t * pSrc, - uint32_t blockSize, - q31_t * pResult, - uint32_t * pIndex); + void arm_max_q31( + q31_t *pSrc, + uint32_t blockSize, + q31_t *pResult, + uint32_t *pIndex); -/** + /** * @brief Maximum value of a floating-point vector. * @param[in] *pSrc points to the input buffer * @param[in] blockSize length of the input vector @@ -6912,13 +6730,13 @@ void arm_rfft_fast_f32( * @return none. */ - void arm_max_f32( - float32_t * pSrc, - uint32_t blockSize, - float32_t * pResult, - uint32_t * pIndex); + void arm_max_f32( + float32_t *pSrc, + uint32_t blockSize, + float32_t *pResult, + uint32_t *pIndex); - /** + /** * @brief Q15 complex-by-complex multiplication * @param[in] *pSrcA points to the first input vector * @param[in] *pSrcB points to the second input vector @@ -6927,13 +6745,13 @@ void arm_rfft_fast_f32( * @return none. */ - void arm_cmplx_mult_cmplx_q15( - q15_t * pSrcA, - q15_t * pSrcB, - q15_t * pDst, - uint32_t numSamples); + void arm_cmplx_mult_cmplx_q15( + q15_t *pSrcA, + q15_t *pSrcB, + q15_t *pDst, + uint32_t numSamples); - /** + /** * @brief Q31 complex-by-complex multiplication * @param[in] *pSrcA points to the first input vector * @param[in] *pSrcB points to the second input vector @@ -6942,13 +6760,13 @@ void arm_rfft_fast_f32( * @return none. */ - void arm_cmplx_mult_cmplx_q31( - q31_t * pSrcA, - q31_t * pSrcB, - q31_t * pDst, - uint32_t numSamples); + void arm_cmplx_mult_cmplx_q31( + q31_t *pSrcA, + q31_t *pSrcB, + q31_t *pDst, + uint32_t numSamples); - /** + /** * @brief Floating-point complex-by-complex multiplication * @param[in] *pSrcA points to the first input vector * @param[in] *pSrcB points to the second input vector @@ -6957,117 +6775,113 @@ void arm_rfft_fast_f32( * @return none. */ - void arm_cmplx_mult_cmplx_f32( - float32_t * pSrcA, - float32_t * pSrcB, - float32_t * pDst, - uint32_t numSamples); + void arm_cmplx_mult_cmplx_f32( + float32_t *pSrcA, + float32_t *pSrcB, + float32_t *pDst, + uint32_t numSamples); - /** + /** * @brief Converts the elements of the floating-point vector to Q31 vector. * @param[in] *pSrc points to the floating-point input vector * @param[out] *pDst points to the Q31 output vector * @param[in] blockSize length of the input vector * @return none. */ - void arm_float_to_q31( - float32_t * pSrc, - q31_t * pDst, - uint32_t blockSize); + void arm_float_to_q31( + float32_t *pSrc, + q31_t *pDst, + uint32_t blockSize); - /** + /** * @brief Converts the elements of the floating-point vector to Q15 vector. * @param[in] *pSrc points to the floating-point input vector * @param[out] *pDst points to the Q15 output vector * @param[in] blockSize length of the input vector * @return none */ - void arm_float_to_q15( - float32_t * pSrc, - q15_t * pDst, - uint32_t blockSize); + void arm_float_to_q15( + float32_t *pSrc, + q15_t *pDst, + uint32_t blockSize); - /** + /** * @brief Converts the elements of the floating-point vector to Q7 vector. * @param[in] *pSrc points to the floating-point input vector * @param[out] *pDst points to the Q7 output vector * @param[in] blockSize length of the input vector * @return none */ - void arm_float_to_q7( - float32_t * pSrc, - q7_t * pDst, - uint32_t blockSize); - + void arm_float_to_q7( + float32_t *pSrc, + q7_t *pDst, + uint32_t blockSize); - /** + /** * @brief Converts the elements of the Q31 vector to Q15 vector. * @param[in] *pSrc is input pointer * @param[out] *pDst is output pointer * @param[in] blockSize is the number of samples to process * @return none. */ - void arm_q31_to_q15( - q31_t * pSrc, - q15_t * pDst, - uint32_t blockSize); + void arm_q31_to_q15( + q31_t *pSrc, + q15_t *pDst, + uint32_t blockSize); - /** + /** * @brief Converts the elements of the Q31 vector to Q7 vector. * @param[in] *pSrc is input pointer * @param[out] *pDst is output pointer * @param[in] blockSize is the number of samples to process * @return none. */ - void arm_q31_to_q7( - q31_t * pSrc, - q7_t * pDst, - uint32_t blockSize); + void arm_q31_to_q7( + q31_t *pSrc, + q7_t *pDst, + uint32_t blockSize); - /** + /** * @brief Converts the elements of the Q15 vector to floating-point vector. * @param[in] *pSrc is input pointer * @param[out] *pDst is output pointer * @param[in] blockSize is the number of samples to process * @return none. */ - void arm_q15_to_float( - q15_t * pSrc, - float32_t * pDst, - uint32_t blockSize); + void arm_q15_to_float( + q15_t *pSrc, + float32_t *pDst, + uint32_t blockSize); - - /** + /** * @brief Converts the elements of the Q15 vector to Q31 vector. * @param[in] *pSrc is input pointer * @param[out] *pDst is output pointer * @param[in] blockSize is the number of samples to process * @return none. */ - void arm_q15_to_q31( - q15_t * pSrc, - q31_t * pDst, - uint32_t blockSize); + void arm_q15_to_q31( + q15_t *pSrc, + q31_t *pDst, + uint32_t blockSize); - - /** + /** * @brief Converts the elements of the Q15 vector to Q7 vector. * @param[in] *pSrc is input pointer * @param[out] *pDst is output pointer * @param[in] blockSize is the number of samples to process * @return none. */ - void arm_q15_to_q7( - q15_t * pSrc, - q7_t * pDst, - uint32_t blockSize); - + void arm_q15_to_q7( + q15_t *pSrc, + q7_t *pDst, + uint32_t blockSize); - /** + /** * @ingroup groupInterpolation */ - /** + /** * @defgroup BilinearInterpolate Bilinear Interpolation * * Bilinear interpolation is an extension of linear interpolation applied to a two dimensional grid. @@ -7119,12 +6933,12 @@ void arm_rfft_fast_f32( * if (x,y) are outside of the table boundary, Bilinear interpolation returns zero output. */ - /** + /** * @addtogroup BilinearInterpolate * @{ */ - /** + /** * * @brief Floating-point bilinear interpolation. * @param[in,out] *S points to an instance of the interpolation structure. @@ -7133,67 +6947,62 @@ void arm_rfft_fast_f32( * @return out interpolated value. */ - - static __INLINE float32_t arm_bilinear_interp_f32( - const arm_bilinear_interp_instance_f32 * S, - float32_t X, - float32_t Y) - { - float32_t out; - float32_t f00, f01, f10, f11; - float32_t *pData = S->pData; - int32_t xIndex, yIndex, index; - float32_t xdiff, ydiff; - float32_t b1, b2, b3, b4; - - xIndex = (int32_t) X; - yIndex = (int32_t) Y; - - /* Care taken for table outside boundary */ - /* Returns zero output when values are outside table boundary */ - if(xIndex < 0 || xIndex > (S->numRows - 1) || yIndex < 0 - || yIndex > (S->numCols - 1)) + static __INLINE float32_t arm_bilinear_interp_f32( + const arm_bilinear_interp_instance_f32 *S, + float32_t X, + float32_t Y) { - return (0); - } + float32_t out; + float32_t f00, f01, f10, f11; + float32_t *pData = S->pData; + int32_t xIndex, yIndex, index; + float32_t xdiff, ydiff; + float32_t b1, b2, b3, b4; - /* Calculation of index for two nearest points in X-direction */ - index = (xIndex - 1) + (yIndex - 1) * S->numCols; + xIndex = (int32_t)X; + yIndex = (int32_t)Y; + /* Care taken for table outside boundary */ + /* Returns zero output when values are outside table boundary */ + if (xIndex < 0 || xIndex > (S->numRows - 1) || yIndex < 0 || yIndex > (S->numCols - 1)) + { + return (0); + } - /* Read two nearest points in X-direction */ - f00 = pData[index]; - f01 = pData[index + 1]; + /* Calculation of index for two nearest points in X-direction */ + index = (xIndex - 1) + (yIndex - 1) * S->numCols; - /* Calculation of index for two nearest points in Y-direction */ - index = (xIndex - 1) + (yIndex) * S->numCols; + /* Read two nearest points in X-direction */ + f00 = pData[index]; + f01 = pData[index + 1]; + /* Calculation of index for two nearest points in Y-direction */ + index = (xIndex - 1) + (yIndex)*S->numCols; - /* Read two nearest points in Y-direction */ - f10 = pData[index]; - f11 = pData[index + 1]; + /* Read two nearest points in Y-direction */ + f10 = pData[index]; + f11 = pData[index + 1]; - /* Calculation of intermediate values */ - b1 = f00; - b2 = f01 - f00; - b3 = f10 - f00; - b4 = f00 - f01 - f10 + f11; + /* Calculation of intermediate values */ + b1 = f00; + b2 = f01 - f00; + b3 = f10 - f00; + b4 = f00 - f01 - f10 + f11; - /* Calculation of fractional part in X */ - xdiff = X - xIndex; + /* Calculation of fractional part in X */ + xdiff = X - xIndex; - /* Calculation of fractional part in Y */ - ydiff = Y - yIndex; + /* Calculation of fractional part in Y */ + ydiff = Y - yIndex; - /* Calculation of bi-linear interpolated output */ - out = b1 + b2 * xdiff + b3 * ydiff + b4 * xdiff * ydiff; + /* Calculation of bi-linear interpolated output */ + out = b1 + b2 * xdiff + b3 * ydiff + b4 * xdiff * ydiff; - /* return to application */ - return (out); - - } + /* return to application */ + return (out); + } - /** + /** * * @brief Q31 bilinear interpolation. * @param[in,out] *S points to an instance of the interpolation structure. @@ -7202,75 +7011,73 @@ void arm_rfft_fast_f32( * @return out interpolated value. */ - static __INLINE q31_t arm_bilinear_interp_q31( - arm_bilinear_interp_instance_q31 * S, - q31_t X, - q31_t Y) - { - q31_t out; /* Temporary output */ - q31_t acc = 0; /* output */ - q31_t xfract, yfract; /* X, Y fractional parts */ - q31_t x1, x2, y1, y2; /* Nearest output values */ - int32_t rI, cI; /* Row and column indices */ - q31_t *pYData = S->pData; /* pointer to output table values */ - uint32_t nCols = S->numCols; /* num of rows */ - - - /* Input is in 12.20 format */ - /* 12 bits for the table index */ - /* Index value calculation */ - rI = ((X & 0xFFF00000) >> 20u); + static __INLINE q31_t arm_bilinear_interp_q31( + arm_bilinear_interp_instance_q31 *S, + q31_t X, + q31_t Y) + { + q31_t out; /* Temporary output */ + q31_t acc = 0; /* output */ + q31_t xfract, yfract; /* X, Y fractional parts */ + q31_t x1, x2, y1, y2; /* Nearest output values */ + int32_t rI, cI; /* Row and column indices */ + q31_t *pYData = S->pData; /* pointer to output table values */ + uint32_t nCols = S->numCols; /* num of rows */ - /* Input is in 12.20 format */ - /* 12 bits for the table index */ - /* Index value calculation */ - cI = ((Y & 0xFFF00000) >> 20u); + /* Input is in 12.20 format */ + /* 12 bits for the table index */ + /* Index value calculation */ + rI = ((X & 0xFFF00000) >> 20u); - /* Care taken for table outside boundary */ - /* Returns zero output when values are outside table boundary */ - if(rI < 0 || rI > (S->numRows - 1) || cI < 0 || cI > (S->numCols - 1)) - { - return (0); - } + /* Input is in 12.20 format */ + /* 12 bits for the table index */ + /* Index value calculation */ + cI = ((Y & 0xFFF00000) >> 20u); - /* 20 bits for the fractional part */ - /* shift left xfract by 11 to keep 1.31 format */ - xfract = (X & 0x000FFFFF) << 11u; + /* Care taken for table outside boundary */ + /* Returns zero output when values are outside table boundary */ + if (rI < 0 || rI > (S->numRows - 1) || cI < 0 || cI > (S->numCols - 1)) + { + return (0); + } - /* Read two nearest output values from the index */ - x1 = pYData[(rI) + nCols * (cI)]; - x2 = pYData[(rI) + nCols * (cI) + 1u]; + /* 20 bits for the fractional part */ + /* shift left xfract by 11 to keep 1.31 format */ + xfract = (X & 0x000FFFFF) << 11u; - /* 20 bits for the fractional part */ - /* shift left yfract by 11 to keep 1.31 format */ - yfract = (Y & 0x000FFFFF) << 11u; + /* Read two nearest output values from the index */ + x1 = pYData[(rI) + nCols * (cI)]; + x2 = pYData[(rI) + nCols * (cI) + 1u]; - /* Read two nearest output values from the index */ - y1 = pYData[(rI) + nCols * (cI + 1)]; - y2 = pYData[(rI) + nCols * (cI + 1) + 1u]; + /* 20 bits for the fractional part */ + /* shift left yfract by 11 to keep 1.31 format */ + yfract = (Y & 0x000FFFFF) << 11u; - /* Calculation of x1 * (1-xfract ) * (1-yfract) and acc is in 3.29(q29) format */ - out = ((q31_t) (((q63_t) x1 * (0x7FFFFFFF - xfract)) >> 32)); - acc = ((q31_t) (((q63_t) out * (0x7FFFFFFF - yfract)) >> 32)); + /* Read two nearest output values from the index */ + y1 = pYData[(rI) + nCols * (cI + 1)]; + y2 = pYData[(rI) + nCols * (cI + 1) + 1u]; - /* x2 * (xfract) * (1-yfract) in 3.29(q29) and adding to acc */ - out = ((q31_t) ((q63_t) x2 * (0x7FFFFFFF - yfract) >> 32)); - acc += ((q31_t) ((q63_t) out * (xfract) >> 32)); + /* Calculation of x1 * (1-xfract ) * (1-yfract) and acc is in 3.29(q29) format */ + out = ((q31_t)(((q63_t)x1 * (0x7FFFFFFF - xfract)) >> 32)); + acc = ((q31_t)(((q63_t)out * (0x7FFFFFFF - yfract)) >> 32)); - /* y1 * (1 - xfract) * (yfract) in 3.29(q29) and adding to acc */ - out = ((q31_t) ((q63_t) y1 * (0x7FFFFFFF - xfract) >> 32)); - acc += ((q31_t) ((q63_t) out * (yfract) >> 32)); + /* x2 * (xfract) * (1-yfract) in 3.29(q29) and adding to acc */ + out = ((q31_t)((q63_t)x2 * (0x7FFFFFFF - yfract) >> 32)); + acc += ((q31_t)((q63_t)out * (xfract) >> 32)); - /* y2 * (xfract) * (yfract) in 3.29(q29) and adding to acc */ - out = ((q31_t) ((q63_t) y2 * (xfract) >> 32)); - acc += ((q31_t) ((q63_t) out * (yfract) >> 32)); + /* y1 * (1 - xfract) * (yfract) in 3.29(q29) and adding to acc */ + out = ((q31_t)((q63_t)y1 * (0x7FFFFFFF - xfract) >> 32)); + acc += ((q31_t)((q63_t)out * (yfract) >> 32)); - /* Convert acc to 1.31(q31) format */ - return (acc << 2u); + /* y2 * (xfract) * (yfract) in 3.29(q29) and adding to acc */ + out = ((q31_t)((q63_t)y2 * (xfract) >> 32)); + acc += ((q31_t)((q63_t)out * (yfract) >> 32)); - } + /* Convert acc to 1.31(q31) format */ + return (acc << 2u); + } - /** + /** * @brief Q15 bilinear interpolation. * @param[in,out] *S points to an instance of the interpolation structure. * @param[in] X interpolation coordinate in 12.20 format. @@ -7278,79 +7085,77 @@ void arm_rfft_fast_f32( * @return out interpolated value. */ - static __INLINE q15_t arm_bilinear_interp_q15( - arm_bilinear_interp_instance_q15 * S, - q31_t X, - q31_t Y) - { - q63_t acc = 0; /* output */ - q31_t out; /* Temporary output */ - q15_t x1, x2, y1, y2; /* Nearest output values */ - q31_t xfract, yfract; /* X, Y fractional parts */ - int32_t rI, cI; /* Row and column indices */ - q15_t *pYData = S->pData; /* pointer to output table values */ - uint32_t nCols = S->numCols; /* num of rows */ - - /* Input is in 12.20 format */ - /* 12 bits for the table index */ - /* Index value calculation */ - rI = ((X & 0xFFF00000) >> 20); - - /* Input is in 12.20 format */ - /* 12 bits for the table index */ - /* Index value calculation */ - cI = ((Y & 0xFFF00000) >> 20); - - /* Care taken for table outside boundary */ - /* Returns zero output when values are outside table boundary */ - if(rI < 0 || rI > (S->numRows - 1) || cI < 0 || cI > (S->numCols - 1)) + static __INLINE q15_t arm_bilinear_interp_q15( + arm_bilinear_interp_instance_q15 *S, + q31_t X, + q31_t Y) { - return (0); - } + q63_t acc = 0; /* output */ + q31_t out; /* Temporary output */ + q15_t x1, x2, y1, y2; /* Nearest output values */ + q31_t xfract, yfract; /* X, Y fractional parts */ + int32_t rI, cI; /* Row and column indices */ + q15_t *pYData = S->pData; /* pointer to output table values */ + uint32_t nCols = S->numCols; /* num of rows */ - /* 20 bits for the fractional part */ - /* xfract should be in 12.20 format */ - xfract = (X & 0x000FFFFF); + /* Input is in 12.20 format */ + /* 12 bits for the table index */ + /* Index value calculation */ + rI = ((X & 0xFFF00000) >> 20); - /* Read two nearest output values from the index */ - x1 = pYData[(rI) + nCols * (cI)]; - x2 = pYData[(rI) + nCols * (cI) + 1u]; + /* Input is in 12.20 format */ + /* 12 bits for the table index */ + /* Index value calculation */ + cI = ((Y & 0xFFF00000) >> 20); + /* Care taken for table outside boundary */ + /* Returns zero output when values are outside table boundary */ + if (rI < 0 || rI > (S->numRows - 1) || cI < 0 || cI > (S->numCols - 1)) + { + return (0); + } - /* 20 bits for the fractional part */ - /* yfract should be in 12.20 format */ - yfract = (Y & 0x000FFFFF); + /* 20 bits for the fractional part */ + /* xfract should be in 12.20 format */ + xfract = (X & 0x000FFFFF); - /* Read two nearest output values from the index */ - y1 = pYData[(rI) + nCols * (cI + 1)]; - y2 = pYData[(rI) + nCols * (cI + 1) + 1u]; + /* Read two nearest output values from the index */ + x1 = pYData[(rI) + nCols * (cI)]; + x2 = pYData[(rI) + nCols * (cI) + 1u]; - /* Calculation of x1 * (1-xfract ) * (1-yfract) and acc is in 13.51 format */ + /* 20 bits for the fractional part */ + /* yfract should be in 12.20 format */ + yfract = (Y & 0x000FFFFF); - /* x1 is in 1.15(q15), xfract in 12.20 format and out is in 13.35 format */ - /* convert 13.35 to 13.31 by right shifting and out is in 1.31 */ - out = (q31_t) (((q63_t) x1 * (0xFFFFF - xfract)) >> 4u); - acc = ((q63_t) out * (0xFFFFF - yfract)); + /* Read two nearest output values from the index */ + y1 = pYData[(rI) + nCols * (cI + 1)]; + y2 = pYData[(rI) + nCols * (cI + 1) + 1u]; - /* x2 * (xfract) * (1-yfract) in 1.51 and adding to acc */ - out = (q31_t) (((q63_t) x2 * (0xFFFFF - yfract)) >> 4u); - acc += ((q63_t) out * (xfract)); + /* Calculation of x1 * (1-xfract ) * (1-yfract) and acc is in 13.51 format */ - /* y1 * (1 - xfract) * (yfract) in 1.51 and adding to acc */ - out = (q31_t) (((q63_t) y1 * (0xFFFFF - xfract)) >> 4u); - acc += ((q63_t) out * (yfract)); + /* x1 is in 1.15(q15), xfract in 12.20 format and out is in 13.35 format */ + /* convert 13.35 to 13.31 by right shifting and out is in 1.31 */ + out = (q31_t)(((q63_t)x1 * (0xFFFFF - xfract)) >> 4u); + acc = ((q63_t)out * (0xFFFFF - yfract)); - /* y2 * (xfract) * (yfract) in 1.51 and adding to acc */ - out = (q31_t) (((q63_t) y2 * (xfract)) >> 4u); - acc += ((q63_t) out * (yfract)); + /* x2 * (xfract) * (1-yfract) in 1.51 and adding to acc */ + out = (q31_t)(((q63_t)x2 * (0xFFFFF - yfract)) >> 4u); + acc += ((q63_t)out * (xfract)); - /* acc is in 13.51 format and down shift acc by 36 times */ - /* Convert out to 1.15 format */ - return (acc >> 36); + /* y1 * (1 - xfract) * (yfract) in 1.51 and adding to acc */ + out = (q31_t)(((q63_t)y1 * (0xFFFFF - xfract)) >> 4u); + acc += ((q63_t)out * (yfract)); - } + /* y2 * (xfract) * (yfract) in 1.51 and adding to acc */ + out = (q31_t)(((q63_t)y2 * (xfract)) >> 4u); + acc += ((q63_t)out * (yfract)); - /** + /* acc is in 13.51 format and down shift acc by 36 times */ + /* Convert out to 1.15 format */ + return (acc >> 36); + } + + /** * @brief Q7 bilinear interpolation. * @param[in,out] *S points to an instance of the interpolation structure. * @param[in] X interpolation coordinate in 12.20 format. @@ -7358,164 +7163,160 @@ void arm_rfft_fast_f32( * @return out interpolated value. */ - static __INLINE q7_t arm_bilinear_interp_q7( - arm_bilinear_interp_instance_q7 * S, - q31_t X, - q31_t Y) - { - q63_t acc = 0; /* output */ - q31_t out; /* Temporary output */ - q31_t xfract, yfract; /* X, Y fractional parts */ - q7_t x1, x2, y1, y2; /* Nearest output values */ - int32_t rI, cI; /* Row and column indices */ - q7_t *pYData = S->pData; /* pointer to output table values */ - uint32_t nCols = S->numCols; /* num of rows */ - - /* Input is in 12.20 format */ - /* 12 bits for the table index */ - /* Index value calculation */ - rI = ((X & 0xFFF00000) >> 20); - - /* Input is in 12.20 format */ - /* 12 bits for the table index */ - /* Index value calculation */ - cI = ((Y & 0xFFF00000) >> 20); - - /* Care taken for table outside boundary */ - /* Returns zero output when values are outside table boundary */ - if(rI < 0 || rI > (S->numRows - 1) || cI < 0 || cI > (S->numCols - 1)) + static __INLINE q7_t arm_bilinear_interp_q7( + arm_bilinear_interp_instance_q7 *S, + q31_t X, + q31_t Y) { - return (0); - } + q63_t acc = 0; /* output */ + q31_t out; /* Temporary output */ + q31_t xfract, yfract; /* X, Y fractional parts */ + q7_t x1, x2, y1, y2; /* Nearest output values */ + int32_t rI, cI; /* Row and column indices */ + q7_t *pYData = S->pData; /* pointer to output table values */ + uint32_t nCols = S->numCols; /* num of rows */ - /* 20 bits for the fractional part */ - /* xfract should be in 12.20 format */ - xfract = (X & 0x000FFFFF); + /* Input is in 12.20 format */ + /* 12 bits for the table index */ + /* Index value calculation */ + rI = ((X & 0xFFF00000) >> 20); - /* Read two nearest output values from the index */ - x1 = pYData[(rI) + nCols * (cI)]; - x2 = pYData[(rI) + nCols * (cI) + 1u]; + /* Input is in 12.20 format */ + /* 12 bits for the table index */ + /* Index value calculation */ + cI = ((Y & 0xFFF00000) >> 20); + /* Care taken for table outside boundary */ + /* Returns zero output when values are outside table boundary */ + if (rI < 0 || rI > (S->numRows - 1) || cI < 0 || cI > (S->numCols - 1)) + { + return (0); + } - /* 20 bits for the fractional part */ - /* yfract should be in 12.20 format */ - yfract = (Y & 0x000FFFFF); + /* 20 bits for the fractional part */ + /* xfract should be in 12.20 format */ + xfract = (X & 0x000FFFFF); - /* Read two nearest output values from the index */ - y1 = pYData[(rI) + nCols * (cI + 1)]; - y2 = pYData[(rI) + nCols * (cI + 1) + 1u]; + /* Read two nearest output values from the index */ + x1 = pYData[(rI) + nCols * (cI)]; + x2 = pYData[(rI) + nCols * (cI) + 1u]; - /* Calculation of x1 * (1-xfract ) * (1-yfract) and acc is in 16.47 format */ - out = ((x1 * (0xFFFFF - xfract))); - acc = (((q63_t) out * (0xFFFFF - yfract))); + /* 20 bits for the fractional part */ + /* yfract should be in 12.20 format */ + yfract = (Y & 0x000FFFFF); - /* x2 * (xfract) * (1-yfract) in 2.22 and adding to acc */ - out = ((x2 * (0xFFFFF - yfract))); - acc += (((q63_t) out * (xfract))); + /* Read two nearest output values from the index */ + y1 = pYData[(rI) + nCols * (cI + 1)]; + y2 = pYData[(rI) + nCols * (cI + 1) + 1u]; - /* y1 * (1 - xfract) * (yfract) in 2.22 and adding to acc */ - out = ((y1 * (0xFFFFF - xfract))); - acc += (((q63_t) out * (yfract))); + /* Calculation of x1 * (1-xfract ) * (1-yfract) and acc is in 16.47 format */ + out = ((x1 * (0xFFFFF - xfract))); + acc = (((q63_t)out * (0xFFFFF - yfract))); - /* y2 * (xfract) * (yfract) in 2.22 and adding to acc */ - out = ((y2 * (yfract))); - acc += (((q63_t) out * (xfract))); + /* x2 * (xfract) * (1-yfract) in 2.22 and adding to acc */ + out = ((x2 * (0xFFFFF - yfract))); + acc += (((q63_t)out * (xfract))); - /* acc in 16.47 format and down shift by 40 to convert to 1.7 format */ - return (acc >> 40); + /* y1 * (1 - xfract) * (yfract) in 2.22 and adding to acc */ + out = ((y1 * (0xFFFFF - xfract))); + acc += (((q63_t)out * (yfract))); - } + /* y2 * (xfract) * (yfract) in 2.22 and adding to acc */ + out = ((y2 * (yfract))); + acc += (((q63_t)out * (xfract))); - /** + /* acc in 16.47 format and down shift by 40 to convert to 1.7 format */ + return (acc >> 40); + } + + /** * @} end of BilinearInterpolate group */ - //SMMLAR #define multAcc_32x32_keep32_R(a, x, y) \ - a = (q31_t) (((((q63_t) a) << 32) + ((q63_t) x * y) + 0x80000000LL ) >> 32) + a = (q31_t)(((((q63_t)a) << 32) + ((q63_t)x * y) + 0x80000000LL) >> 32) //SMMLSR #define multSub_32x32_keep32_R(a, x, y) \ - a = (q31_t) (((((q63_t) a) << 32) - ((q63_t) x * y) + 0x80000000LL ) >> 32) + a = (q31_t)(((((q63_t)a) << 32) - ((q63_t)x * y) + 0x80000000LL) >> 32) //SMMULR #define mult_32x32_keep32_R(a, x, y) \ - a = (q31_t) (((q63_t) x * y + 0x80000000LL ) >> 32) + a = (q31_t)(((q63_t)x * y + 0x80000000LL) >> 32) //SMMLA #define multAcc_32x32_keep32(a, x, y) \ - a += (q31_t) (((q63_t) x * y) >> 32) + a += (q31_t)(((q63_t)x * y) >> 32) //SMMLS #define multSub_32x32_keep32(a, x, y) \ - a -= (q31_t) (((q63_t) x * y) >> 32) + a -= (q31_t)(((q63_t)x * y) >> 32) //SMMUL #define mult_32x32_keep32(a, x, y) \ - a = (q31_t) (((q63_t) x * y ) >> 32) + a = (q31_t)(((q63_t)x * y) >> 32) +#if defined(__CC_ARM) //Keil -#if defined ( __CC_ARM ) //Keil - -//Enter low optimization region - place directly above function definition - #ifdef ARM_MATH_CM4 - #define LOW_OPTIMIZATION_ENTER \ - _Pragma ("push") \ - _Pragma ("O1") - #else - #define LOW_OPTIMIZATION_ENTER - #endif + //Enter low optimization region - place directly above function definition +#ifdef ARM_MATH_CM4 +#define LOW_OPTIMIZATION_ENTER \ + _Pragma("push") \ + _Pragma("O1") +#else +#define LOW_OPTIMIZATION_ENTER +#endif -//Exit low optimization region - place directly after end of function definition - #ifdef ARM_MATH_CM4 - #define LOW_OPTIMIZATION_EXIT \ - _Pragma ("pop") - #else - #define LOW_OPTIMIZATION_EXIT - #endif + //Exit low optimization region - place directly after end of function definition +#ifdef ARM_MATH_CM4 +#define LOW_OPTIMIZATION_EXIT \ + _Pragma("pop") +#else +#define LOW_OPTIMIZATION_EXIT +#endif -//Enter low optimization region - place directly above function definition - #define IAR_ONLY_LOW_OPTIMIZATION_ENTER + //Enter low optimization region - place directly above function definition +#define IAR_ONLY_LOW_OPTIMIZATION_ENTER -//Exit low optimization region - place directly after end of function definition - #define IAR_ONLY_LOW_OPTIMIZATION_EXIT + //Exit low optimization region - place directly after end of function definition +#define IAR_ONLY_LOW_OPTIMIZATION_EXIT #elif defined(__ICCARM__) //IAR //Enter low optimization region - place directly above function definition - #ifdef ARM_MATH_CM4 - #define LOW_OPTIMIZATION_ENTER \ - _Pragma ("optimize=low") - #else - #define LOW_OPTIMIZATION_ENTER - #endif +#ifdef ARM_MATH_CM4 +#define LOW_OPTIMIZATION_ENTER \ + _Pragma("optimize=low") +#else +#define LOW_OPTIMIZATION_ENTER +#endif //Exit low optimization region - place directly after end of function definition - #define LOW_OPTIMIZATION_EXIT +#define LOW_OPTIMIZATION_EXIT //Enter low optimization region - place directly above function definition - #ifdef ARM_MATH_CM4 - #define IAR_ONLY_LOW_OPTIMIZATION_ENTER \ - _Pragma ("optimize=low") - #else - #define IAR_ONLY_LOW_OPTIMIZATION_ENTER - #endif +#ifdef ARM_MATH_CM4 +#define IAR_ONLY_LOW_OPTIMIZATION_ENTER \ + _Pragma("optimize=low") +#else +#define IAR_ONLY_LOW_OPTIMIZATION_ENTER +#endif //Exit low optimization region - place directly after end of function definition - #define IAR_ONLY_LOW_OPTIMIZATION_EXIT +#define IAR_ONLY_LOW_OPTIMIZATION_EXIT #elif defined(__GNUC__) - #define LOW_OPTIMIZATION_ENTER __attribute__(( optimize("-O1") )) +#define LOW_OPTIMIZATION_ENTER __attribute__((optimize("-O1"))) - #define LOW_OPTIMIZATION_EXIT +#define LOW_OPTIMIZATION_EXIT - #define IAR_ONLY_LOW_OPTIMIZATION_ENTER +#define IAR_ONLY_LOW_OPTIMIZATION_ENTER - #define IAR_ONLY_LOW_OPTIMIZATION_EXIT +#define IAR_ONLY_LOW_OPTIMIZATION_EXIT -#elif defined(__CSMC__) // Cosmic +#elif defined(__CSMC__) // Cosmic #define LOW_OPTIMIZATION_ENTER #define LOW_OPTIMIZATION_EXIT @@ -7524,12 +7325,10 @@ void arm_rfft_fast_f32( #endif - -#ifdef __cplusplus +#ifdef __cplusplus } #endif - #endif /* _ARM_MATH_H */ /** diff --git a/bsp/swm320-lq100/Libraries/CMSIS/CoreSupport/core_cm0.h b/bsp/swm320-lq100/Libraries/CMSIS/CoreSupport/core_cm0.h index 5186cb4838..da584c05a6 100644 --- a/bsp/swm320-lq100/Libraries/CMSIS/CoreSupport/core_cm0.h +++ b/bsp/swm320-lq100/Libraries/CMSIS/CoreSupport/core_cm0.h @@ -1,4 +1,4 @@ -/**************************************************************************//** +/**************************************************************************/ /** * @file core_cm0.h * @brief CMSIS Cortex-M0 Core Peripheral Access Layer Header File * @version V4.00 @@ -34,16 +34,16 @@ POSSIBILITY OF SUCH DAMAGE. ---------------------------------------------------------------------------*/ - -#if defined ( __ICCARM__ ) - #pragma system_include /* treat file as system include file for MISRA check */ +#if defined(__ICCARM__) +#pragma system_include /* treat file as system include file for MISRA check */ #endif #ifndef __CORE_CM0_H_GENERIC #define __CORE_CM0_H_GENERIC #ifdef __cplusplus - extern "C" { +extern "C" +{ #endif /** \page CMSIS_MISRA_Exceptions MISRA-C:2004 Compliance Exceptions @@ -59,7 +59,6 @@ Function-like macros are used to allow more efficient code. */ - /******************************************************************************* * CMSIS definitions ******************************************************************************/ @@ -68,85 +67,84 @@ */ /* CMSIS CM0 definitions */ -#define __CM0_CMSIS_VERSION_MAIN (0x04) /*!< [31:16] CMSIS HAL main version */ -#define __CM0_CMSIS_VERSION_SUB (0x00) /*!< [15:0] CMSIS HAL sub version */ -#define __CM0_CMSIS_VERSION ((__CM0_CMSIS_VERSION_MAIN << 16) | \ - __CM0_CMSIS_VERSION_SUB ) /*!< CMSIS HAL version number */ +#define __CM0_CMSIS_VERSION_MAIN (0x04) /*!< [31:16] CMSIS HAL main version */ +#define __CM0_CMSIS_VERSION_SUB (0x00) /*!< [15:0] CMSIS HAL sub version */ +#define __CM0_CMSIS_VERSION ((__CM0_CMSIS_VERSION_MAIN << 16) | \ + __CM0_CMSIS_VERSION_SUB) /*!< CMSIS HAL version number */ -#define __CORTEX_M (0x00) /*!< Cortex-M Core */ +#define __CORTEX_M (0x00) /*!< Cortex-M Core */ +#if defined(__CC_ARM) +#define __ASM __asm /*!< asm keyword for ARM Compiler */ +#define __INLINE __inline /*!< inline keyword for ARM Compiler */ +#define __STATIC_INLINE static __inline -#if defined ( __CC_ARM ) - #define __ASM __asm /*!< asm keyword for ARM Compiler */ - #define __INLINE __inline /*!< inline keyword for ARM Compiler */ - #define __STATIC_INLINE static __inline +#elif defined(__GNUC__) +#define __ASM __asm /*!< asm keyword for GNU Compiler */ +#define __INLINE inline /*!< inline keyword for GNU Compiler */ +#define __STATIC_INLINE static inline -#elif defined ( __GNUC__ ) - #define __ASM __asm /*!< asm keyword for GNU Compiler */ - #define __INLINE inline /*!< inline keyword for GNU Compiler */ - #define __STATIC_INLINE static inline +#elif defined(__ICCARM__) +#define __ASM __asm /*!< asm keyword for IAR Compiler */ +#define __INLINE inline /*!< inline keyword for IAR Compiler. Only available in High optimization mode! */ +#define __STATIC_INLINE static inline -#elif defined ( __ICCARM__ ) - #define __ASM __asm /*!< asm keyword for IAR Compiler */ - #define __INLINE inline /*!< inline keyword for IAR Compiler. Only available in High optimization mode! */ - #define __STATIC_INLINE static inline +#elif defined(__TMS470__) +#define __ASM __asm /*!< asm keyword for TI CCS Compiler */ +#define __STATIC_INLINE static inline -#elif defined ( __TMS470__ ) - #define __ASM __asm /*!< asm keyword for TI CCS Compiler */ - #define __STATIC_INLINE static inline +#elif defined(__TASKING__) +#define __ASM __asm /*!< asm keyword for TASKING Compiler */ +#define __INLINE inline /*!< inline keyword for TASKING Compiler */ +#define __STATIC_INLINE static inline -#elif defined ( __TASKING__ ) - #define __ASM __asm /*!< asm keyword for TASKING Compiler */ - #define __INLINE inline /*!< inline keyword for TASKING Compiler */ - #define __STATIC_INLINE static inline - -#elif defined ( __CSMC__ ) - #define __packed - #define __ASM _asm /*!< asm keyword for COSMIC Compiler */ - #define __INLINE inline /*use -pc99 on compile line !< inline keyword for COSMIC Compiler */ - #define __STATIC_INLINE static inline +#elif defined(__CSMC__) +#define __packed +#define __ASM _asm /*!< asm keyword for COSMIC Compiler */ +#define __INLINE inline /*use -pc99 on compile line !< inline keyword for COSMIC Compiler */ +#define __STATIC_INLINE static inline #endif /** __FPU_USED indicates whether an FPU is used or not. This core does not support an FPU at all */ -#define __FPU_USED 0 +#define __FPU_USED 0 -#if defined ( __CC_ARM ) - #if defined __TARGET_FPU_VFP - #warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" - #endif +#if defined(__CC_ARM) +#if defined __TARGET_FPU_VFP +#warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" +#endif -#elif defined ( __GNUC__ ) - #if defined (__VFP_FP__) && !defined(__SOFTFP__) - #warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" - #endif +#elif defined(__GNUC__) +#if defined(__VFP_FP__) && !defined(__SOFTFP__) +#warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" +#endif -#elif defined ( __ICCARM__ ) - #if defined __ARMVFP__ - #warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" - #endif +#elif defined(__ICCARM__) +#if defined __ARMVFP__ +#warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" +#endif -#elif defined ( __TMS470__ ) - #if defined __TI__VFP_SUPPORT____ - #warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" - #endif +#elif defined(__TMS470__) +#if defined __TI__VFP_SUPPORT____ +#warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" +#endif -#elif defined ( __TASKING__ ) - #if defined __FPU_VFP__ - #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" - #endif +#elif defined(__TASKING__) +#if defined __FPU_VFP__ +#error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" +#endif -#elif defined ( __CSMC__ ) /* Cosmic */ - #if ( __CSMC__ & 0x400) // FPU present for parser - #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" - #endif +#elif defined(__CSMC__) /* Cosmic */ +#if (__CSMC__ & 0x400) // FPU present for parser +#error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" +#endif #endif -#include <stdint.h> /* standard types definitions */ -#include <core_cmInstr.h> /* Core Instruction Access */ -#include <core_cmFunc.h> /* Core Function Access */ +#include <stdint.h> /* standard types definitions */ +#include <core_cmInstr.h> /* Core Instruction Access */ +#include <core_cmFunc.h> /* Core Function Access */ #ifdef __cplusplus } @@ -160,25 +158,26 @@ #define __CORE_CM0_H_DEPENDANT #ifdef __cplusplus - extern "C" { +extern "C" +{ #endif /* check device defines and use defaults */ #if defined __CHECK_DEVICE_DEFINES - #ifndef __CM0_REV - #define __CM0_REV 0x0000 - #warning "__CM0_REV not defined in device header file; using default!" - #endif +#ifndef __CM0_REV +#define __CM0_REV 0x0000 +#warning "__CM0_REV not defined in device header file; using default!" +#endif - #ifndef __NVIC_PRIO_BITS - #define __NVIC_PRIO_BITS 2 - #warning "__NVIC_PRIO_BITS not defined in device header file; using default!" - #endif +#ifndef __NVIC_PRIO_BITS +#define __NVIC_PRIO_BITS 2 +#warning "__NVIC_PRIO_BITS not defined in device header file; using default!" +#endif - #ifndef __Vendor_SysTickConfig - #define __Vendor_SysTickConfig 0 - #warning "__Vendor_SysTickConfig not defined in device header file; using default!" - #endif +#ifndef __Vendor_SysTickConfig +#define __Vendor_SysTickConfig 0 +#warning "__Vendor_SysTickConfig not defined in device header file; using default!" +#endif #endif /* IO definitions (access restrictions to peripheral registers) */ @@ -190,18 +189,16 @@ \li for automatic generation of peripheral register debug information. */ #ifdef __cplusplus - #define __I volatile /*!< Defines 'read only' permissions */ +#define __I volatile /*!< Defines 'read only' permissions */ #else - #define __I volatile const /*!< Defines 'read only' permissions */ +#define __I volatile const /*!< Defines 'read only' permissions */ #endif -#define __O volatile /*!< Defines 'write only' permissions */ -#define __IO volatile /*!< Defines 'read / write' permissions */ - -/*@} end of group Cortex_M0 */ +#define __O volatile /*!< Defines 'write only' permissions */ +#define __IO volatile /*!< Defines 'read / write' permissions */ + /*@} end of group Cortex_M0 */ - -/******************************************************************************* + /******************************************************************************* * Register Abstraction Core Register contain: - Core Register @@ -209,275 +206,268 @@ - Core SCB Register - Core SysTick Register ******************************************************************************/ -/** \defgroup CMSIS_core_register Defines and Type Definitions + /** \defgroup CMSIS_core_register Defines and Type Definitions \brief Type definitions and defines for Cortex-M processor based devices. */ -/** \ingroup CMSIS_core_register + /** \ingroup CMSIS_core_register \defgroup CMSIS_CORE Status and Control Registers \brief Core Register type definitions. @{ */ -/** \brief Union type to access the Application Program Status Register (APSR). + /** \brief Union type to access the Application Program Status Register (APSR). */ -typedef union -{ - struct - { + typedef union + { + struct + { #if (__CORTEX_M != 0x04) - uint32_t _reserved0:27; /*!< bit: 0..26 Reserved */ + uint32_t _reserved0 : 27; /*!< bit: 0..26 Reserved */ #else - uint32_t _reserved0:16; /*!< bit: 0..15 Reserved */ - uint32_t GE:4; /*!< bit: 16..19 Greater than or Equal flags */ - uint32_t _reserved1:7; /*!< bit: 20..26 Reserved */ + uint32_t _reserved0 : 16; /*!< bit: 0..15 Reserved */ + uint32_t GE : 4; /*!< bit: 16..19 Greater than or Equal flags */ + uint32_t _reserved1 : 7; /*!< bit: 20..26 Reserved */ #endif - uint32_t Q:1; /*!< bit: 27 Saturation condition flag */ - uint32_t V:1; /*!< bit: 28 Overflow condition code flag */ - uint32_t C:1; /*!< bit: 29 Carry condition code flag */ - uint32_t Z:1; /*!< bit: 30 Zero condition code flag */ - uint32_t N:1; /*!< bit: 31 Negative condition code flag */ - } b; /*!< Structure used for bit access */ - uint32_t w; /*!< Type used for word access */ -} APSR_Type; + uint32_t Q : 1; /*!< bit: 27 Saturation condition flag */ + uint32_t V : 1; /*!< bit: 28 Overflow condition code flag */ + uint32_t C : 1; /*!< bit: 29 Carry condition code flag */ + uint32_t Z : 1; /*!< bit: 30 Zero condition code flag */ + uint32_t N : 1; /*!< bit: 31 Negative condition code flag */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ + } APSR_Type; - -/** \brief Union type to access the Interrupt Program Status Register (IPSR). + /** \brief Union type to access the Interrupt Program Status Register (IPSR). */ -typedef union -{ - struct - { - uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */ - uint32_t _reserved0:23; /*!< bit: 9..31 Reserved */ - } b; /*!< Structure used for bit access */ - uint32_t w; /*!< Type used for word access */ -} IPSR_Type; - + typedef union + { + struct + { + uint32_t ISR : 9; /*!< bit: 0.. 8 Exception number */ + uint32_t _reserved0 : 23; /*!< bit: 9..31 Reserved */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ + } IPSR_Type; -/** \brief Union type to access the Special-Purpose Program Status Registers (xPSR). + /** \brief Union type to access the Special-Purpose Program Status Registers (xPSR). */ -typedef union -{ - struct - { - uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */ + typedef union + { + struct + { + uint32_t ISR : 9; /*!< bit: 0.. 8 Exception number */ #if (__CORTEX_M != 0x04) - uint32_t _reserved0:15; /*!< bit: 9..23 Reserved */ + uint32_t _reserved0 : 15; /*!< bit: 9..23 Reserved */ #else - uint32_t _reserved0:7; /*!< bit: 9..15 Reserved */ - uint32_t GE:4; /*!< bit: 16..19 Greater than or Equal flags */ - uint32_t _reserved1:4; /*!< bit: 20..23 Reserved */ + uint32_t _reserved0 : 7; /*!< bit: 9..15 Reserved */ + uint32_t GE : 4; /*!< bit: 16..19 Greater than or Equal flags */ + uint32_t _reserved1 : 4; /*!< bit: 20..23 Reserved */ #endif - uint32_t T:1; /*!< bit: 24 Thumb bit (read 0) */ - uint32_t IT:2; /*!< bit: 25..26 saved IT state (read 0) */ - uint32_t Q:1; /*!< bit: 27 Saturation condition flag */ - uint32_t V:1; /*!< bit: 28 Overflow condition code flag */ - uint32_t C:1; /*!< bit: 29 Carry condition code flag */ - uint32_t Z:1; /*!< bit: 30 Zero condition code flag */ - uint32_t N:1; /*!< bit: 31 Negative condition code flag */ - } b; /*!< Structure used for bit access */ - uint32_t w; /*!< Type used for word access */ -} xPSR_Type; - + uint32_t T : 1; /*!< bit: 24 Thumb bit (read 0) */ + uint32_t IT : 2; /*!< bit: 25..26 saved IT state (read 0) */ + uint32_t Q : 1; /*!< bit: 27 Saturation condition flag */ + uint32_t V : 1; /*!< bit: 28 Overflow condition code flag */ + uint32_t C : 1; /*!< bit: 29 Carry condition code flag */ + uint32_t Z : 1; /*!< bit: 30 Zero condition code flag */ + uint32_t N : 1; /*!< bit: 31 Negative condition code flag */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ + } xPSR_Type; -/** \brief Union type to access the Control Registers (CONTROL). + /** \brief Union type to access the Control Registers (CONTROL). */ -typedef union -{ - struct - { - uint32_t nPRIV:1; /*!< bit: 0 Execution privilege in Thread mode */ - uint32_t SPSEL:1; /*!< bit: 1 Stack to be used */ - uint32_t FPCA:1; /*!< bit: 2 FP extension active flag */ - uint32_t _reserved0:29; /*!< bit: 3..31 Reserved */ - } b; /*!< Structure used for bit access */ - uint32_t w; /*!< Type used for word access */ -} CONTROL_Type; - -/*@} end of group CMSIS_CORE */ + typedef union + { + struct + { + uint32_t nPRIV : 1; /*!< bit: 0 Execution privilege in Thread mode */ + uint32_t SPSEL : 1; /*!< bit: 1 Stack to be used */ + uint32_t FPCA : 1; /*!< bit: 2 FP extension active flag */ + uint32_t _reserved0 : 29; /*!< bit: 3..31 Reserved */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ + } CONTROL_Type; + /*@} end of group CMSIS_CORE */ -/** \ingroup CMSIS_core_register + /** \ingroup CMSIS_core_register \defgroup CMSIS_NVIC Nested Vectored Interrupt Controller (NVIC) \brief Type definitions for the NVIC Registers @{ */ -/** \brief Structure type to access the Nested Vectored Interrupt Controller (NVIC). + /** \brief Structure type to access the Nested Vectored Interrupt Controller (NVIC). */ -typedef struct -{ - __IO uint32_t ISER[1]; /*!< Offset: 0x000 (R/W) Interrupt Set Enable Register */ - uint32_t RESERVED0[31]; - __IO uint32_t ICER[1]; /*!< Offset: 0x080 (R/W) Interrupt Clear Enable Register */ - uint32_t RSERVED1[31]; - __IO uint32_t ISPR[1]; /*!< Offset: 0x100 (R/W) Interrupt Set Pending Register */ - uint32_t RESERVED2[31]; - __IO uint32_t ICPR[1]; /*!< Offset: 0x180 (R/W) Interrupt Clear Pending Register */ - uint32_t RESERVED3[31]; - uint32_t RESERVED4[64]; - __IO uint32_t IP[8]; /*!< Offset: 0x300 (R/W) Interrupt Priority Register */ -} NVIC_Type; + typedef struct + { + __IO uint32_t ISER[1]; /*!< Offset: 0x000 (R/W) Interrupt Set Enable Register */ + uint32_t RESERVED0[31]; + __IO uint32_t ICER[1]; /*!< Offset: 0x080 (R/W) Interrupt Clear Enable Register */ + uint32_t RSERVED1[31]; + __IO uint32_t ISPR[1]; /*!< Offset: 0x100 (R/W) Interrupt Set Pending Register */ + uint32_t RESERVED2[31]; + __IO uint32_t ICPR[1]; /*!< Offset: 0x180 (R/W) Interrupt Clear Pending Register */ + uint32_t RESERVED3[31]; + uint32_t RESERVED4[64]; + __IO uint32_t IP[8]; /*!< Offset: 0x300 (R/W) Interrupt Priority Register */ + } NVIC_Type; -/*@} end of group CMSIS_NVIC */ + /*@} end of group CMSIS_NVIC */ - -/** \ingroup CMSIS_core_register + /** \ingroup CMSIS_core_register \defgroup CMSIS_SCB System Control Block (SCB) \brief Type definitions for the System Control Block Registers @{ */ -/** \brief Structure type to access the System Control Block (SCB). + /** \brief Structure type to access the System Control Block (SCB). */ -typedef struct -{ - __I uint32_t CPUID; /*!< Offset: 0x000 (R/ ) CPUID Base Register */ - __IO uint32_t ICSR; /*!< Offset: 0x004 (R/W) Interrupt Control and State Register */ - uint32_t RESERVED0; - __IO uint32_t AIRCR; /*!< Offset: 0x00C (R/W) Application Interrupt and Reset Control Register */ - __IO uint32_t SCR; /*!< Offset: 0x010 (R/W) System Control Register */ - __IO uint32_t CCR; /*!< Offset: 0x014 (R/W) Configuration Control Register */ - uint32_t RESERVED1; - __IO uint32_t SHP[2]; /*!< Offset: 0x01C (R/W) System Handlers Priority Registers. [0] is RESERVED */ - __IO uint32_t SHCSR; /*!< Offset: 0x024 (R/W) System Handler Control and State Register */ -} SCB_Type; + typedef struct + { + __I uint32_t CPUID; /*!< Offset: 0x000 (R/ ) CPUID Base Register */ + __IO uint32_t ICSR; /*!< Offset: 0x004 (R/W) Interrupt Control and State Register */ + uint32_t RESERVED0; + __IO uint32_t AIRCR; /*!< Offset: 0x00C (R/W) Application Interrupt and Reset Control Register */ + __IO uint32_t SCR; /*!< Offset: 0x010 (R/W) System Control Register */ + __IO uint32_t CCR; /*!< Offset: 0x014 (R/W) Configuration Control Register */ + uint32_t RESERVED1; + __IO uint32_t SHP[2]; /*!< Offset: 0x01C (R/W) System Handlers Priority Registers. [0] is RESERVED */ + __IO uint32_t SHCSR; /*!< Offset: 0x024 (R/W) System Handler Control and State Register */ + } SCB_Type; /* SCB CPUID Register Definitions */ -#define SCB_CPUID_IMPLEMENTER_Pos 24 /*!< SCB CPUID: IMPLEMENTER Position */ -#define SCB_CPUID_IMPLEMENTER_Msk (0xFFUL << SCB_CPUID_IMPLEMENTER_Pos) /*!< SCB CPUID: IMPLEMENTER Mask */ +#define SCB_CPUID_IMPLEMENTER_Pos 24 /*!< SCB CPUID: IMPLEMENTER Position */ +#define SCB_CPUID_IMPLEMENTER_Msk (0xFFUL << SCB_CPUID_IMPLEMENTER_Pos) /*!< SCB CPUID: IMPLEMENTER Mask */ -#define SCB_CPUID_VARIANT_Pos 20 /*!< SCB CPUID: VARIANT Position */ -#define SCB_CPUID_VARIANT_Msk (0xFUL << SCB_CPUID_VARIANT_Pos) /*!< SCB CPUID: VARIANT Mask */ +#define SCB_CPUID_VARIANT_Pos 20 /*!< SCB CPUID: VARIANT Position */ +#define SCB_CPUID_VARIANT_Msk (0xFUL << SCB_CPUID_VARIANT_Pos) /*!< SCB CPUID: VARIANT Mask */ -#define SCB_CPUID_ARCHITECTURE_Pos 16 /*!< SCB CPUID: ARCHITECTURE Position */ -#define SCB_CPUID_ARCHITECTURE_Msk (0xFUL << SCB_CPUID_ARCHITECTURE_Pos) /*!< SCB CPUID: ARCHITECTURE Mask */ +#define SCB_CPUID_ARCHITECTURE_Pos 16 /*!< SCB CPUID: ARCHITECTURE Position */ +#define SCB_CPUID_ARCHITECTURE_Msk (0xFUL << SCB_CPUID_ARCHITECTURE_Pos) /*!< SCB CPUID: ARCHITECTURE Mask */ -#define SCB_CPUID_PARTNO_Pos 4 /*!< SCB CPUID: PARTNO Position */ -#define SCB_CPUID_PARTNO_Msk (0xFFFUL << SCB_CPUID_PARTNO_Pos) /*!< SCB CPUID: PARTNO Mask */ +#define SCB_CPUID_PARTNO_Pos 4 /*!< SCB CPUID: PARTNO Position */ +#define SCB_CPUID_PARTNO_Msk (0xFFFUL << SCB_CPUID_PARTNO_Pos) /*!< SCB CPUID: PARTNO Mask */ -#define SCB_CPUID_REVISION_Pos 0 /*!< SCB CPUID: REVISION Position */ -#define SCB_CPUID_REVISION_Msk (0xFUL << SCB_CPUID_REVISION_Pos) /*!< SCB CPUID: REVISION Mask */ +#define SCB_CPUID_REVISION_Pos 0 /*!< SCB CPUID: REVISION Position */ +#define SCB_CPUID_REVISION_Msk (0xFUL << SCB_CPUID_REVISION_Pos) /*!< SCB CPUID: REVISION Mask */ /* SCB Interrupt Control State Register Definitions */ -#define SCB_ICSR_NMIPENDSET_Pos 31 /*!< SCB ICSR: NMIPENDSET Position */ -#define SCB_ICSR_NMIPENDSET_Msk (1UL << SCB_ICSR_NMIPENDSET_Pos) /*!< SCB ICSR: NMIPENDSET Mask */ +#define SCB_ICSR_NMIPENDSET_Pos 31 /*!< SCB ICSR: NMIPENDSET Position */ +#define SCB_ICSR_NMIPENDSET_Msk (1UL << SCB_ICSR_NMIPENDSET_Pos) /*!< SCB ICSR: NMIPENDSET Mask */ -#define SCB_ICSR_PENDSVSET_Pos 28 /*!< SCB ICSR: PENDSVSET Position */ -#define SCB_ICSR_PENDSVSET_Msk (1UL << SCB_ICSR_PENDSVSET_Pos) /*!< SCB ICSR: PENDSVSET Mask */ +#define SCB_ICSR_PENDSVSET_Pos 28 /*!< SCB ICSR: PENDSVSET Position */ +#define SCB_ICSR_PENDSVSET_Msk (1UL << SCB_ICSR_PENDSVSET_Pos) /*!< SCB ICSR: PENDSVSET Mask */ -#define SCB_ICSR_PENDSVCLR_Pos 27 /*!< SCB ICSR: PENDSVCLR Position */ -#define SCB_ICSR_PENDSVCLR_Msk (1UL << SCB_ICSR_PENDSVCLR_Pos) /*!< SCB ICSR: PENDSVCLR Mask */ +#define SCB_ICSR_PENDSVCLR_Pos 27 /*!< SCB ICSR: PENDSVCLR Position */ +#define SCB_ICSR_PENDSVCLR_Msk (1UL << SCB_ICSR_PENDSVCLR_Pos) /*!< SCB ICSR: PENDSVCLR Mask */ -#define SCB_ICSR_PENDSTSET_Pos 26 /*!< SCB ICSR: PENDSTSET Position */ -#define SCB_ICSR_PENDSTSET_Msk (1UL << SCB_ICSR_PENDSTSET_Pos) /*!< SCB ICSR: PENDSTSET Mask */ +#define SCB_ICSR_PENDSTSET_Pos 26 /*!< SCB ICSR: PENDSTSET Position */ +#define SCB_ICSR_PENDSTSET_Msk (1UL << SCB_ICSR_PENDSTSET_Pos) /*!< SCB ICSR: PENDSTSET Mask */ -#define SCB_ICSR_PENDSTCLR_Pos 25 /*!< SCB ICSR: PENDSTCLR Position */ -#define SCB_ICSR_PENDSTCLR_Msk (1UL << SCB_ICSR_PENDSTCLR_Pos) /*!< SCB ICSR: PENDSTCLR Mask */ +#define SCB_ICSR_PENDSTCLR_Pos 25 /*!< SCB ICSR: PENDSTCLR Position */ +#define SCB_ICSR_PENDSTCLR_Msk (1UL << SCB_ICSR_PENDSTCLR_Pos) /*!< SCB ICSR: PENDSTCLR Mask */ -#define SCB_ICSR_ISRPREEMPT_Pos 23 /*!< SCB ICSR: ISRPREEMPT Position */ -#define SCB_ICSR_ISRPREEMPT_Msk (1UL << SCB_ICSR_ISRPREEMPT_Pos) /*!< SCB ICSR: ISRPREEMPT Mask */ +#define SCB_ICSR_ISRPREEMPT_Pos 23 /*!< SCB ICSR: ISRPREEMPT Position */ +#define SCB_ICSR_ISRPREEMPT_Msk (1UL << SCB_ICSR_ISRPREEMPT_Pos) /*!< SCB ICSR: ISRPREEMPT Mask */ -#define SCB_ICSR_ISRPENDING_Pos 22 /*!< SCB ICSR: ISRPENDING Position */ -#define SCB_ICSR_ISRPENDING_Msk (1UL << SCB_ICSR_ISRPENDING_Pos) /*!< SCB ICSR: ISRPENDING Mask */ +#define SCB_ICSR_ISRPENDING_Pos 22 /*!< SCB ICSR: ISRPENDING Position */ +#define SCB_ICSR_ISRPENDING_Msk (1UL << SCB_ICSR_ISRPENDING_Pos) /*!< SCB ICSR: ISRPENDING Mask */ -#define SCB_ICSR_VECTPENDING_Pos 12 /*!< SCB ICSR: VECTPENDING Position */ -#define SCB_ICSR_VECTPENDING_Msk (0x1FFUL << SCB_ICSR_VECTPENDING_Pos) /*!< SCB ICSR: VECTPENDING Mask */ +#define SCB_ICSR_VECTPENDING_Pos 12 /*!< SCB ICSR: VECTPENDING Position */ +#define SCB_ICSR_VECTPENDING_Msk (0x1FFUL << SCB_ICSR_VECTPENDING_Pos) /*!< SCB ICSR: VECTPENDING Mask */ -#define SCB_ICSR_VECTACTIVE_Pos 0 /*!< SCB ICSR: VECTACTIVE Position */ -#define SCB_ICSR_VECTACTIVE_Msk (0x1FFUL << SCB_ICSR_VECTACTIVE_Pos) /*!< SCB ICSR: VECTACTIVE Mask */ +#define SCB_ICSR_VECTACTIVE_Pos 0 /*!< SCB ICSR: VECTACTIVE Position */ +#define SCB_ICSR_VECTACTIVE_Msk (0x1FFUL << SCB_ICSR_VECTACTIVE_Pos) /*!< SCB ICSR: VECTACTIVE Mask */ /* SCB Application Interrupt and Reset Control Register Definitions */ -#define SCB_AIRCR_VECTKEY_Pos 16 /*!< SCB AIRCR: VECTKEY Position */ -#define SCB_AIRCR_VECTKEY_Msk (0xFFFFUL << SCB_AIRCR_VECTKEY_Pos) /*!< SCB AIRCR: VECTKEY Mask */ +#define SCB_AIRCR_VECTKEY_Pos 16 /*!< SCB AIRCR: VECTKEY Position */ +#define SCB_AIRCR_VECTKEY_Msk (0xFFFFUL << SCB_AIRCR_VECTKEY_Pos) /*!< SCB AIRCR: VECTKEY Mask */ -#define SCB_AIRCR_VECTKEYSTAT_Pos 16 /*!< SCB AIRCR: VECTKEYSTAT Position */ -#define SCB_AIRCR_VECTKEYSTAT_Msk (0xFFFFUL << SCB_AIRCR_VECTKEYSTAT_Pos) /*!< SCB AIRCR: VECTKEYSTAT Mask */ +#define SCB_AIRCR_VECTKEYSTAT_Pos 16 /*!< SCB AIRCR: VECTKEYSTAT Position */ +#define SCB_AIRCR_VECTKEYSTAT_Msk (0xFFFFUL << SCB_AIRCR_VECTKEYSTAT_Pos) /*!< SCB AIRCR: VECTKEYSTAT Mask */ -#define SCB_AIRCR_ENDIANESS_Pos 15 /*!< SCB AIRCR: ENDIANESS Position */ -#define SCB_AIRCR_ENDIANESS_Msk (1UL << SCB_AIRCR_ENDIANESS_Pos) /*!< SCB AIRCR: ENDIANESS Mask */ +#define SCB_AIRCR_ENDIANESS_Pos 15 /*!< SCB AIRCR: ENDIANESS Position */ +#define SCB_AIRCR_ENDIANESS_Msk (1UL << SCB_AIRCR_ENDIANESS_Pos) /*!< SCB AIRCR: ENDIANESS Mask */ -#define SCB_AIRCR_SYSRESETREQ_Pos 2 /*!< SCB AIRCR: SYSRESETREQ Position */ -#define SCB_AIRCR_SYSRESETREQ_Msk (1UL << SCB_AIRCR_SYSRESETREQ_Pos) /*!< SCB AIRCR: SYSRESETREQ Mask */ +#define SCB_AIRCR_SYSRESETREQ_Pos 2 /*!< SCB AIRCR: SYSRESETREQ Position */ +#define SCB_AIRCR_SYSRESETREQ_Msk (1UL << SCB_AIRCR_SYSRESETREQ_Pos) /*!< SCB AIRCR: SYSRESETREQ Mask */ -#define SCB_AIRCR_VECTCLRACTIVE_Pos 1 /*!< SCB AIRCR: VECTCLRACTIVE Position */ -#define SCB_AIRCR_VECTCLRACTIVE_Msk (1UL << SCB_AIRCR_VECTCLRACTIVE_Pos) /*!< SCB AIRCR: VECTCLRACTIVE Mask */ +#define SCB_AIRCR_VECTCLRACTIVE_Pos 1 /*!< SCB AIRCR: VECTCLRACTIVE Position */ +#define SCB_AIRCR_VECTCLRACTIVE_Msk (1UL << SCB_AIRCR_VECTCLRACTIVE_Pos) /*!< SCB AIRCR: VECTCLRACTIVE Mask */ /* SCB System Control Register Definitions */ -#define SCB_SCR_SEVONPEND_Pos 4 /*!< SCB SCR: SEVONPEND Position */ -#define SCB_SCR_SEVONPEND_Msk (1UL << SCB_SCR_SEVONPEND_Pos) /*!< SCB SCR: SEVONPEND Mask */ +#define SCB_SCR_SEVONPEND_Pos 4 /*!< SCB SCR: SEVONPEND Position */ +#define SCB_SCR_SEVONPEND_Msk (1UL << SCB_SCR_SEVONPEND_Pos) /*!< SCB SCR: SEVONPEND Mask */ -#define SCB_SCR_SLEEPDEEP_Pos 2 /*!< SCB SCR: SLEEPDEEP Position */ -#define SCB_SCR_SLEEPDEEP_Msk (1UL << SCB_SCR_SLEEPDEEP_Pos) /*!< SCB SCR: SLEEPDEEP Mask */ +#define SCB_SCR_SLEEPDEEP_Pos 2 /*!< SCB SCR: SLEEPDEEP Position */ +#define SCB_SCR_SLEEPDEEP_Msk (1UL << SCB_SCR_SLEEPDEEP_Pos) /*!< SCB SCR: SLEEPDEEP Mask */ -#define SCB_SCR_SLEEPONEXIT_Pos 1 /*!< SCB SCR: SLEEPONEXIT Position */ -#define SCB_SCR_SLEEPONEXIT_Msk (1UL << SCB_SCR_SLEEPONEXIT_Pos) /*!< SCB SCR: SLEEPONEXIT Mask */ +#define SCB_SCR_SLEEPONEXIT_Pos 1 /*!< SCB SCR: SLEEPONEXIT Position */ +#define SCB_SCR_SLEEPONEXIT_Msk (1UL << SCB_SCR_SLEEPONEXIT_Pos) /*!< SCB SCR: SLEEPONEXIT Mask */ /* SCB Configuration Control Register Definitions */ -#define SCB_CCR_STKALIGN_Pos 9 /*!< SCB CCR: STKALIGN Position */ -#define SCB_CCR_STKALIGN_Msk (1UL << SCB_CCR_STKALIGN_Pos) /*!< SCB CCR: STKALIGN Mask */ +#define SCB_CCR_STKALIGN_Pos 9 /*!< SCB CCR: STKALIGN Position */ +#define SCB_CCR_STKALIGN_Msk (1UL << SCB_CCR_STKALIGN_Pos) /*!< SCB CCR: STKALIGN Mask */ -#define SCB_CCR_UNALIGN_TRP_Pos 3 /*!< SCB CCR: UNALIGN_TRP Position */ -#define SCB_CCR_UNALIGN_TRP_Msk (1UL << SCB_CCR_UNALIGN_TRP_Pos) /*!< SCB CCR: UNALIGN_TRP Mask */ +#define SCB_CCR_UNALIGN_TRP_Pos 3 /*!< SCB CCR: UNALIGN_TRP Position */ +#define SCB_CCR_UNALIGN_TRP_Msk (1UL << SCB_CCR_UNALIGN_TRP_Pos) /*!< SCB CCR: UNALIGN_TRP Mask */ /* SCB System Handler Control and State Register Definitions */ -#define SCB_SHCSR_SVCALLPENDED_Pos 15 /*!< SCB SHCSR: SVCALLPENDED Position */ -#define SCB_SHCSR_SVCALLPENDED_Msk (1UL << SCB_SHCSR_SVCALLPENDED_Pos) /*!< SCB SHCSR: SVCALLPENDED Mask */ +#define SCB_SHCSR_SVCALLPENDED_Pos 15 /*!< SCB SHCSR: SVCALLPENDED Position */ +#define SCB_SHCSR_SVCALLPENDED_Msk (1UL << SCB_SHCSR_SVCALLPENDED_Pos) /*!< SCB SHCSR: SVCALLPENDED Mask */ -/*@} end of group CMSIS_SCB */ + /*@} end of group CMSIS_SCB */ - -/** \ingroup CMSIS_core_register + /** \ingroup CMSIS_core_register \defgroup CMSIS_SysTick System Tick Timer (SysTick) \brief Type definitions for the System Timer Registers. @{ */ -/** \brief Structure type to access the System Timer (SysTick). + /** \brief Structure type to access the System Timer (SysTick). */ -typedef struct -{ - __IO uint32_t CTRL; /*!< Offset: 0x000 (R/W) SysTick Control and Status Register */ - __IO uint32_t LOAD; /*!< Offset: 0x004 (R/W) SysTick Reload Value Register */ - __IO uint32_t VAL; /*!< Offset: 0x008 (R/W) SysTick Current Value Register */ - __I uint32_t CALIB; /*!< Offset: 0x00C (R/ ) SysTick Calibration Register */ -} SysTick_Type; + typedef struct + { + __IO uint32_t CTRL; /*!< Offset: 0x000 (R/W) SysTick Control and Status Register */ + __IO uint32_t LOAD; /*!< Offset: 0x004 (R/W) SysTick Reload Value Register */ + __IO uint32_t VAL; /*!< Offset: 0x008 (R/W) SysTick Current Value Register */ + __I uint32_t CALIB; /*!< Offset: 0x00C (R/ ) SysTick Calibration Register */ + } SysTick_Type; /* SysTick Control / Status Register Definitions */ -#define SysTick_CTRL_COUNTFLAG_Pos 16 /*!< SysTick CTRL: COUNTFLAG Position */ -#define SysTick_CTRL_COUNTFLAG_Msk (1UL << SysTick_CTRL_COUNTFLAG_Pos) /*!< SysTick CTRL: COUNTFLAG Mask */ +#define SysTick_CTRL_COUNTFLAG_Pos 16 /*!< SysTick CTRL: COUNTFLAG Position */ +#define SysTick_CTRL_COUNTFLAG_Msk (1UL << SysTick_CTRL_COUNTFLAG_Pos) /*!< SysTick CTRL: COUNTFLAG Mask */ -#define SysTick_CTRL_CLKSOURCE_Pos 2 /*!< SysTick CTRL: CLKSOURCE Position */ -#define SysTick_CTRL_CLKSOURCE_Msk (1UL << SysTick_CTRL_CLKSOURCE_Pos) /*!< SysTick CTRL: CLKSOURCE Mask */ +#define SysTick_CTRL_CLKSOURCE_Pos 2 /*!< SysTick CTRL: CLKSOURCE Position */ +#define SysTick_CTRL_CLKSOURCE_Msk (1UL << SysTick_CTRL_CLKSOURCE_Pos) /*!< SysTick CTRL: CLKSOURCE Mask */ -#define SysTick_CTRL_TICKINT_Pos 1 /*!< SysTick CTRL: TICKINT Position */ -#define SysTick_CTRL_TICKINT_Msk (1UL << SysTick_CTRL_TICKINT_Pos) /*!< SysTick CTRL: TICKINT Mask */ +#define SysTick_CTRL_TICKINT_Pos 1 /*!< SysTick CTRL: TICKINT Position */ +#define SysTick_CTRL_TICKINT_Msk (1UL << SysTick_CTRL_TICKINT_Pos) /*!< SysTick CTRL: TICKINT Mask */ -#define SysTick_CTRL_ENABLE_Pos 0 /*!< SysTick CTRL: ENABLE Position */ -#define SysTick_CTRL_ENABLE_Msk (1UL << SysTick_CTRL_ENABLE_Pos) /*!< SysTick CTRL: ENABLE Mask */ +#define SysTick_CTRL_ENABLE_Pos 0 /*!< SysTick CTRL: ENABLE Position */ +#define SysTick_CTRL_ENABLE_Msk (1UL << SysTick_CTRL_ENABLE_Pos) /*!< SysTick CTRL: ENABLE Mask */ /* SysTick Reload Register Definitions */ -#define SysTick_LOAD_RELOAD_Pos 0 /*!< SysTick LOAD: RELOAD Position */ -#define SysTick_LOAD_RELOAD_Msk (0xFFFFFFUL << SysTick_LOAD_RELOAD_Pos) /*!< SysTick LOAD: RELOAD Mask */ +#define SysTick_LOAD_RELOAD_Pos 0 /*!< SysTick LOAD: RELOAD Position */ +#define SysTick_LOAD_RELOAD_Msk (0xFFFFFFUL << SysTick_LOAD_RELOAD_Pos) /*!< SysTick LOAD: RELOAD Mask */ /* SysTick Current Register Definitions */ -#define SysTick_VAL_CURRENT_Pos 0 /*!< SysTick VAL: CURRENT Position */ -#define SysTick_VAL_CURRENT_Msk (0xFFFFFFUL << SysTick_VAL_CURRENT_Pos) /*!< SysTick VAL: CURRENT Mask */ +#define SysTick_VAL_CURRENT_Pos 0 /*!< SysTick VAL: CURRENT Position */ +#define SysTick_VAL_CURRENT_Msk (0xFFFFFFUL << SysTick_VAL_CURRENT_Pos) /*!< SysTick VAL: CURRENT Mask */ /* SysTick Calibration Register Definitions */ -#define SysTick_CALIB_NOREF_Pos 31 /*!< SysTick CALIB: NOREF Position */ -#define SysTick_CALIB_NOREF_Msk (1UL << SysTick_CALIB_NOREF_Pos) /*!< SysTick CALIB: NOREF Mask */ +#define SysTick_CALIB_NOREF_Pos 31 /*!< SysTick CALIB: NOREF Position */ +#define SysTick_CALIB_NOREF_Msk (1UL << SysTick_CALIB_NOREF_Pos) /*!< SysTick CALIB: NOREF Mask */ -#define SysTick_CALIB_SKEW_Pos 30 /*!< SysTick CALIB: SKEW Position */ -#define SysTick_CALIB_SKEW_Msk (1UL << SysTick_CALIB_SKEW_Pos) /*!< SysTick CALIB: SKEW Mask */ +#define SysTick_CALIB_SKEW_Pos 30 /*!< SysTick CALIB: SKEW Position */ +#define SysTick_CALIB_SKEW_Msk (1UL << SysTick_CALIB_SKEW_Pos) /*!< SysTick CALIB: SKEW Mask */ -#define SysTick_CALIB_TENMS_Pos 0 /*!< SysTick CALIB: TENMS Position */ -#define SysTick_CALIB_TENMS_Msk (0xFFFFFFUL << SysTick_CALIB_TENMS_Pos) /*!< SysTick CALIB: TENMS Mask */ +#define SysTick_CALIB_TENMS_Pos 0 /*!< SysTick CALIB: TENMS Position */ +#define SysTick_CALIB_TENMS_Msk (0xFFFFFFUL << SysTick_CALIB_TENMS_Pos) /*!< SysTick CALIB: TENMS Mask */ /*@} end of group CMSIS_SysTick */ - /** \ingroup CMSIS_core_register \defgroup CMSIS_CoreDebug Core Debug Registers (CoreDebug) \brief Cortex-M0 Core Debug Registers (DCB registers, SHCSR, and DFSR) @@ -487,7 +477,6 @@ typedef struct */ /*@} end of group CMSIS_CoreDebug */ - /** \ingroup CMSIS_core_register \defgroup CMSIS_core_base Core Definitions \brief Definitions for base addresses, unions, and structures. @@ -495,20 +484,17 @@ typedef struct */ /* Memory mapping of Cortex-M0 Hardware */ -#define SCS_BASE (0xE000E000UL) /*!< System Control Space Base Address */ -#define SysTick_BASE (SCS_BASE + 0x0010UL) /*!< SysTick Base Address */ -#define NVIC_BASE (SCS_BASE + 0x0100UL) /*!< NVIC Base Address */ -#define SCB_BASE (SCS_BASE + 0x0D00UL) /*!< System Control Block Base Address */ - -#define SCB ((SCB_Type *) SCB_BASE ) /*!< SCB configuration struct */ -#define SysTick ((SysTick_Type *) SysTick_BASE ) /*!< SysTick configuration struct */ -#define NVIC ((NVIC_Type *) NVIC_BASE ) /*!< NVIC configuration struct */ +#define SCS_BASE (0xE000E000UL) /*!< System Control Space Base Address */ +#define SysTick_BASE (SCS_BASE + 0x0010UL) /*!< SysTick Base Address */ +#define NVIC_BASE (SCS_BASE + 0x0100UL) /*!< NVIC Base Address */ +#define SCB_BASE (SCS_BASE + 0x0D00UL) /*!< System Control Block Base Address */ +#define SCB ((SCB_Type *)SCB_BASE) /*!< SCB configuration struct */ +#define SysTick ((SysTick_Type *)SysTick_BASE) /*!< SysTick configuration struct */ +#define NVIC ((NVIC_Type *)NVIC_BASE) /*!< NVIC configuration struct */ /*@} */ - - /******************************************************************************* * Hardware Abstraction Layer Core Function Interface contains: @@ -519,8 +505,6 @@ typedef struct /** \defgroup CMSIS_Core_FunctionInterface Functions and Instructions Reference */ - - /* ########################## NVIC functions #################################### */ /** \ingroup CMSIS_Core_FunctionInterface \defgroup CMSIS_Core_NVICFunctions NVIC Functions @@ -530,36 +514,33 @@ typedef struct /* Interrupt Priorities are WORD accessible only under ARMv6M */ /* The following MACROS handle generation of the register offset and byte masks */ -#define _BIT_SHIFT(IRQn) ( (((uint32_t)(IRQn) ) & 0x03) * 8 ) -#define _SHP_IDX(IRQn) ( ((((uint32_t)(IRQn) & 0x0F)-8) >> 2) ) -#define _IP_IDX(IRQn) ( ((uint32_t)(IRQn) >> 2) ) - +#define _BIT_SHIFT(IRQn) ((((uint32_t)(IRQn)) & 0x03) * 8) +#define _SHP_IDX(IRQn) (((((uint32_t)(IRQn)&0x0F) - 8) >> 2)) +#define _IP_IDX(IRQn) (((uint32_t)(IRQn) >> 2)) -/** \brief Enable External Interrupt + /** \brief Enable External Interrupt The function enables a device-specific interrupt in the NVIC interrupt controller. \param [in] IRQn External interrupt number. Value cannot be negative. */ -__STATIC_INLINE void NVIC_EnableIRQ(IRQn_Type IRQn) -{ - NVIC->ISER[0] = (1 << ((uint32_t)(IRQn) & 0x1F)); -} + __STATIC_INLINE void NVIC_EnableIRQ(IRQn_Type IRQn) + { + NVIC->ISER[0] = (1 << ((uint32_t)(IRQn)&0x1F)); + } - -/** \brief Disable External Interrupt + /** \brief Disable External Interrupt The function disables a device-specific interrupt in the NVIC interrupt controller. \param [in] IRQn External interrupt number. Value cannot be negative. */ -__STATIC_INLINE void NVIC_DisableIRQ(IRQn_Type IRQn) -{ - NVIC->ICER[0] = (1 << ((uint32_t)(IRQn) & 0x1F)); -} - + __STATIC_INLINE void NVIC_DisableIRQ(IRQn_Type IRQn) + { + NVIC->ICER[0] = (1 << ((uint32_t)(IRQn)&0x1F)); + } -/** \brief Get Pending Interrupt + /** \brief Get Pending Interrupt The function reads the pending register in the NVIC and returns the pending bit for the specified interrupt. @@ -569,37 +550,34 @@ __STATIC_INLINE void NVIC_DisableIRQ(IRQn_Type IRQn) \return 0 Interrupt status is not pending. \return 1 Interrupt status is pending. */ -__STATIC_INLINE uint32_t NVIC_GetPendingIRQ(IRQn_Type IRQn) -{ - return((uint32_t) ((NVIC->ISPR[0] & (1 << ((uint32_t)(IRQn) & 0x1F)))?1:0)); -} - + __STATIC_INLINE uint32_t NVIC_GetPendingIRQ(IRQn_Type IRQn) + { + return ((uint32_t)((NVIC->ISPR[0] & (1 << ((uint32_t)(IRQn)&0x1F))) ? 1 : 0)); + } -/** \brief Set Pending Interrupt + /** \brief Set Pending Interrupt The function sets the pending bit of an external interrupt. \param [in] IRQn Interrupt number. Value cannot be negative. */ -__STATIC_INLINE void NVIC_SetPendingIRQ(IRQn_Type IRQn) -{ - NVIC->ISPR[0] = (1 << ((uint32_t)(IRQn) & 0x1F)); -} + __STATIC_INLINE void NVIC_SetPendingIRQ(IRQn_Type IRQn) + { + NVIC->ISPR[0] = (1 << ((uint32_t)(IRQn)&0x1F)); + } - -/** \brief Clear Pending Interrupt + /** \brief Clear Pending Interrupt The function clears the pending bit of an external interrupt. \param [in] IRQn External interrupt number. Value cannot be negative. */ -__STATIC_INLINE void NVIC_ClearPendingIRQ(IRQn_Type IRQn) -{ - NVIC->ICPR[0] = (1 << ((uint32_t)(IRQn) & 0x1F)); /* Clear pending interrupt */ -} - + __STATIC_INLINE void NVIC_ClearPendingIRQ(IRQn_Type IRQn) + { + NVIC->ICPR[0] = (1 << ((uint32_t)(IRQn)&0x1F)); /* Clear pending interrupt */ + } -/** \brief Set Interrupt Priority + /** \brief Set Interrupt Priority The function sets the priority of an interrupt. @@ -608,18 +586,21 @@ __STATIC_INLINE void NVIC_ClearPendingIRQ(IRQn_Type IRQn) \param [in] IRQn Interrupt number. \param [in] priority Priority to set. */ -__STATIC_INLINE void NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority) -{ - if(IRQn < 0) { - SCB->SHP[_SHP_IDX(IRQn)] = (SCB->SHP[_SHP_IDX(IRQn)] & ~(0xFF << _BIT_SHIFT(IRQn))) | - (((priority << (8 - __NVIC_PRIO_BITS)) & 0xFF) << _BIT_SHIFT(IRQn)); } - else { - NVIC->IP[_IP_IDX(IRQn)] = (NVIC->IP[_IP_IDX(IRQn)] & ~(0xFF << _BIT_SHIFT(IRQn))) | - (((priority << (8 - __NVIC_PRIO_BITS)) & 0xFF) << _BIT_SHIFT(IRQn)); } -} - + __STATIC_INLINE void NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority) + { + if (IRQn < 0) + { + SCB->SHP[_SHP_IDX(IRQn)] = (SCB->SHP[_SHP_IDX(IRQn)] & ~(0xFF << _BIT_SHIFT(IRQn))) | + (((priority << (8 - __NVIC_PRIO_BITS)) & 0xFF) << _BIT_SHIFT(IRQn)); + } + else + { + NVIC->IP[_IP_IDX(IRQn)] = (NVIC->IP[_IP_IDX(IRQn)] & ~(0xFF << _BIT_SHIFT(IRQn))) | + (((priority << (8 - __NVIC_PRIO_BITS)) & 0xFF) << _BIT_SHIFT(IRQn)); + } + } -/** \brief Get Interrupt Priority + /** \brief Get Interrupt Priority The function reads the priority of an interrupt. The interrupt number can be positive to specify an external (device specific) @@ -630,36 +611,38 @@ __STATIC_INLINE void NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority) \return Interrupt Priority. Value is aligned automatically to the implemented priority bits of the microcontroller. */ -__STATIC_INLINE uint32_t NVIC_GetPriority(IRQn_Type IRQn) -{ - - if(IRQn < 0) { - return((uint32_t)(((SCB->SHP[_SHP_IDX(IRQn)] >> _BIT_SHIFT(IRQn) ) & 0xFF) >> (8 - __NVIC_PRIO_BITS))); } /* get priority for Cortex-M0 system interrupts */ - else { - return((uint32_t)(((NVIC->IP[ _IP_IDX(IRQn)] >> _BIT_SHIFT(IRQn) ) & 0xFF) >> (8 - __NVIC_PRIO_BITS))); } /* get priority for device specific interrupts */ -} + __STATIC_INLINE uint32_t NVIC_GetPriority(IRQn_Type IRQn) + { + if (IRQn < 0) + { + return ((uint32_t)(((SCB->SHP[_SHP_IDX(IRQn)] >> _BIT_SHIFT(IRQn)) & 0xFF) >> (8 - __NVIC_PRIO_BITS))); + } /* get priority for Cortex-M0 system interrupts */ + else + { + return ((uint32_t)(((NVIC->IP[_IP_IDX(IRQn)] >> _BIT_SHIFT(IRQn)) & 0xFF) >> (8 - __NVIC_PRIO_BITS))); + } /* get priority for device specific interrupts */ + } -/** \brief System Reset + /** \brief System Reset The function initiates a system reset request to reset the MCU. */ -__STATIC_INLINE void NVIC_SystemReset(void) -{ - __DSB(); /* Ensure all outstanding memory accesses included + __STATIC_INLINE void NVIC_SystemReset(void) + { + __DSB(); /* Ensure all outstanding memory accesses included buffered write are completed before reset */ - SCB->AIRCR = ((0x5FA << SCB_AIRCR_VECTKEY_Pos) | - SCB_AIRCR_SYSRESETREQ_Msk); - __DSB(); /* Ensure completion of memory access */ - while(1); /* wait until reset */ -} - -/*@} end of CMSIS_Core_NVICFunctions */ - + SCB->AIRCR = ((0x5FA << SCB_AIRCR_VECTKEY_Pos) | + SCB_AIRCR_SYSRESETREQ_Msk); + __DSB(); /* Ensure completion of memory access */ + while (1) + ; /* wait until reset */ + } + /*@} end of CMSIS_Core_NVICFunctions */ -/* ################################## SysTick function ############################################ */ -/** \ingroup CMSIS_Core_FunctionInterface + /* ################################## SysTick function ############################################ */ + /** \ingroup CMSIS_Core_FunctionInterface \defgroup CMSIS_Core_SysTickFunctions SysTick Functions \brief Functions that configure the System. @{ @@ -667,7 +650,7 @@ __STATIC_INLINE void NVIC_SystemReset(void) #if (__Vendor_SysTickConfig == 0) -/** \brief System Tick Configuration + /** \brief System Tick Configuration The function initializes the System Timer and its interrupt, and starts the System Tick Timer. Counter is in free running mode to generate periodic interrupts. @@ -682,25 +665,23 @@ __STATIC_INLINE void NVIC_SystemReset(void) must contain a vendor-specific implementation of this function. */ -__STATIC_INLINE uint32_t SysTick_Config(uint32_t ticks) -{ - if ((ticks - 1) > SysTick_LOAD_RELOAD_Msk) return (1); /* Reload value impossible */ + __STATIC_INLINE uint32_t SysTick_Config(uint32_t ticks) + { + if ((ticks - 1) > SysTick_LOAD_RELOAD_Msk) + return (1); /* Reload value impossible */ - SysTick->LOAD = ticks - 1; /* set reload register */ - NVIC_SetPriority (SysTick_IRQn, (1<<__NVIC_PRIO_BITS) - 1); /* set Priority for Systick Interrupt */ - SysTick->VAL = 0; /* Load the SysTick Counter Value */ - SysTick->CTRL = SysTick_CTRL_CLKSOURCE_Msk | - SysTick_CTRL_TICKINT_Msk | - SysTick_CTRL_ENABLE_Msk; /* Enable SysTick IRQ and SysTick Timer */ - return (0); /* Function successful */ -} + SysTick->LOAD = ticks - 1; /* set reload register */ + NVIC_SetPriority(SysTick_IRQn, (1 << __NVIC_PRIO_BITS) - 1); /* set Priority for Systick Interrupt */ + SysTick->VAL = 0; /* Load the SysTick Counter Value */ + SysTick->CTRL = SysTick_CTRL_CLKSOURCE_Msk | + SysTick_CTRL_TICKINT_Msk | + SysTick_CTRL_ENABLE_Msk; /* Enable SysTick IRQ and SysTick Timer */ + return (0); /* Function successful */ + } #endif -/*@} end of CMSIS_Core_SysTickFunctions */ - - - + /*@} end of CMSIS_Core_SysTickFunctions */ #ifdef __cplusplus } diff --git a/bsp/swm320-lq100/Libraries/CMSIS/CoreSupport/core_cm0plus.h b/bsp/swm320-lq100/Libraries/CMSIS/CoreSupport/core_cm0plus.h index 17e43984fc..a8af6dba6d 100644 --- a/bsp/swm320-lq100/Libraries/CMSIS/CoreSupport/core_cm0plus.h +++ b/bsp/swm320-lq100/Libraries/CMSIS/CoreSupport/core_cm0plus.h @@ -1,4 +1,4 @@ -/**************************************************************************//** +/**************************************************************************/ /** * @file core_cm0plus.h * @brief CMSIS Cortex-M0+ Core Peripheral Access Layer Header File * @version V4.00 @@ -34,16 +34,16 @@ POSSIBILITY OF SUCH DAMAGE. ---------------------------------------------------------------------------*/ - -#if defined ( __ICCARM__ ) - #pragma system_include /* treat file as system include file for MISRA check */ +#if defined(__ICCARM__) +#pragma system_include /* treat file as system include file for MISRA check */ #endif #ifndef __CORE_CM0PLUS_H_GENERIC #define __CORE_CM0PLUS_H_GENERIC #ifdef __cplusplus - extern "C" { +extern "C" +{ #endif /** \page CMSIS_MISRA_Exceptions MISRA-C:2004 Compliance Exceptions @@ -59,7 +59,6 @@ Function-like macros are used to allow more efficient code. */ - /******************************************************************************* * CMSIS definitions ******************************************************************************/ @@ -68,85 +67,84 @@ */ /* CMSIS CM0P definitions */ -#define __CM0PLUS_CMSIS_VERSION_MAIN (0x04) /*!< [31:16] CMSIS HAL main version */ -#define __CM0PLUS_CMSIS_VERSION_SUB (0x00) /*!< [15:0] CMSIS HAL sub version */ -#define __CM0PLUS_CMSIS_VERSION ((__CM0PLUS_CMSIS_VERSION_MAIN << 16) | \ - __CM0PLUS_CMSIS_VERSION_SUB) /*!< CMSIS HAL version number */ +#define __CM0PLUS_CMSIS_VERSION_MAIN (0x04) /*!< [31:16] CMSIS HAL main version */ +#define __CM0PLUS_CMSIS_VERSION_SUB (0x00) /*!< [15:0] CMSIS HAL sub version */ +#define __CM0PLUS_CMSIS_VERSION ((__CM0PLUS_CMSIS_VERSION_MAIN << 16) | \ + __CM0PLUS_CMSIS_VERSION_SUB) /*!< CMSIS HAL version number */ -#define __CORTEX_M (0x00) /*!< Cortex-M Core */ +#define __CORTEX_M (0x00) /*!< Cortex-M Core */ +#if defined(__CC_ARM) +#define __ASM __asm /*!< asm keyword for ARM Compiler */ +#define __INLINE __inline /*!< inline keyword for ARM Compiler */ +#define __STATIC_INLINE static __inline -#if defined ( __CC_ARM ) - #define __ASM __asm /*!< asm keyword for ARM Compiler */ - #define __INLINE __inline /*!< inline keyword for ARM Compiler */ - #define __STATIC_INLINE static __inline +#elif defined(__GNUC__) +#define __ASM __asm /*!< asm keyword for GNU Compiler */ +#define __INLINE inline /*!< inline keyword for GNU Compiler */ +#define __STATIC_INLINE static inline -#elif defined ( __GNUC__ ) - #define __ASM __asm /*!< asm keyword for GNU Compiler */ - #define __INLINE inline /*!< inline keyword for GNU Compiler */ - #define __STATIC_INLINE static inline +#elif defined(__ICCARM__) +#define __ASM __asm /*!< asm keyword for IAR Compiler */ +#define __INLINE inline /*!< inline keyword for IAR Compiler. Only available in High optimization mode! */ +#define __STATIC_INLINE static inline -#elif defined ( __ICCARM__ ) - #define __ASM __asm /*!< asm keyword for IAR Compiler */ - #define __INLINE inline /*!< inline keyword for IAR Compiler. Only available in High optimization mode! */ - #define __STATIC_INLINE static inline +#elif defined(__TMS470__) +#define __ASM __asm /*!< asm keyword for TI CCS Compiler */ +#define __STATIC_INLINE static inline -#elif defined ( __TMS470__ ) - #define __ASM __asm /*!< asm keyword for TI CCS Compiler */ - #define __STATIC_INLINE static inline +#elif defined(__TASKING__) +#define __ASM __asm /*!< asm keyword for TASKING Compiler */ +#define __INLINE inline /*!< inline keyword for TASKING Compiler */ +#define __STATIC_INLINE static inline -#elif defined ( __TASKING__ ) - #define __ASM __asm /*!< asm keyword for TASKING Compiler */ - #define __INLINE inline /*!< inline keyword for TASKING Compiler */ - #define __STATIC_INLINE static inline - -#elif defined ( __CSMC__ ) - #define __packed - #define __ASM _asm /*!< asm keyword for COSMIC Compiler */ - #define __INLINE inline /*use -pc99 on compile line !< inline keyword for COSMIC Compiler */ - #define __STATIC_INLINE static inline +#elif defined(__CSMC__) +#define __packed +#define __ASM _asm /*!< asm keyword for COSMIC Compiler */ +#define __INLINE inline /*use -pc99 on compile line !< inline keyword for COSMIC Compiler */ +#define __STATIC_INLINE static inline #endif /** __FPU_USED indicates whether an FPU is used or not. This core does not support an FPU at all */ -#define __FPU_USED 0 +#define __FPU_USED 0 -#if defined ( __CC_ARM ) - #if defined __TARGET_FPU_VFP - #warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" - #endif +#if defined(__CC_ARM) +#if defined __TARGET_FPU_VFP +#warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" +#endif -#elif defined ( __GNUC__ ) - #if defined (__VFP_FP__) && !defined(__SOFTFP__) - #warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" - #endif +#elif defined(__GNUC__) +#if defined(__VFP_FP__) && !defined(__SOFTFP__) +#warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" +#endif -#elif defined ( __ICCARM__ ) - #if defined __ARMVFP__ - #warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" - #endif +#elif defined(__ICCARM__) +#if defined __ARMVFP__ +#warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" +#endif -#elif defined ( __TMS470__ ) - #if defined __TI__VFP_SUPPORT____ - #warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" - #endif +#elif defined(__TMS470__) +#if defined __TI__VFP_SUPPORT____ +#warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" +#endif -#elif defined ( __TASKING__ ) - #if defined __FPU_VFP__ - #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" - #endif +#elif defined(__TASKING__) +#if defined __FPU_VFP__ +#error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" +#endif -#elif defined ( __CSMC__ ) /* Cosmic */ - #if ( __CSMC__ & 0x400) // FPU present for parser - #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" - #endif +#elif defined(__CSMC__) /* Cosmic */ +#if (__CSMC__ & 0x400) // FPU present for parser +#error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" +#endif #endif -#include <stdint.h> /* standard types definitions */ -#include <core_cmInstr.h> /* Core Instruction Access */ -#include <core_cmFunc.h> /* Core Function Access */ +#include <stdint.h> /* standard types definitions */ +#include <core_cmInstr.h> /* Core Instruction Access */ +#include <core_cmFunc.h> /* Core Function Access */ #ifdef __cplusplus } @@ -160,35 +158,36 @@ #define __CORE_CM0PLUS_H_DEPENDANT #ifdef __cplusplus - extern "C" { +extern "C" +{ #endif /* check device defines and use defaults */ #if defined __CHECK_DEVICE_DEFINES - #ifndef __CM0PLUS_REV - #define __CM0PLUS_REV 0x0000 - #warning "__CM0PLUS_REV not defined in device header file; using default!" - #endif +#ifndef __CM0PLUS_REV +#define __CM0PLUS_REV 0x0000 +#warning "__CM0PLUS_REV not defined in device header file; using default!" +#endif - #ifndef __MPU_PRESENT - #define __MPU_PRESENT 0 - #warning "__MPU_PRESENT not defined in device header file; using default!" - #endif +#ifndef __MPU_PRESENT +#define __MPU_PRESENT 0 +#warning "__MPU_PRESENT not defined in device header file; using default!" +#endif - #ifndef __VTOR_PRESENT - #define __VTOR_PRESENT 0 - #warning "__VTOR_PRESENT not defined in device header file; using default!" - #endif +#ifndef __VTOR_PRESENT +#define __VTOR_PRESENT 0 +#warning "__VTOR_PRESENT not defined in device header file; using default!" +#endif - #ifndef __NVIC_PRIO_BITS - #define __NVIC_PRIO_BITS 2 - #warning "__NVIC_PRIO_BITS not defined in device header file; using default!" - #endif +#ifndef __NVIC_PRIO_BITS +#define __NVIC_PRIO_BITS 2 +#warning "__NVIC_PRIO_BITS not defined in device header file; using default!" +#endif - #ifndef __Vendor_SysTickConfig - #define __Vendor_SysTickConfig 0 - #warning "__Vendor_SysTickConfig not defined in device header file; using default!" - #endif +#ifndef __Vendor_SysTickConfig +#define __Vendor_SysTickConfig 0 +#warning "__Vendor_SysTickConfig not defined in device header file; using default!" +#endif #endif /* IO definitions (access restrictions to peripheral registers) */ @@ -200,18 +199,16 @@ \li for automatic generation of peripheral register debug information. */ #ifdef __cplusplus - #define __I volatile /*!< Defines 'read only' permissions */ +#define __I volatile /*!< Defines 'read only' permissions */ #else - #define __I volatile const /*!< Defines 'read only' permissions */ +#define __I volatile const /*!< Defines 'read only' permissions */ #endif -#define __O volatile /*!< Defines 'write only' permissions */ -#define __IO volatile /*!< Defines 'read / write' permissions */ - -/*@} end of group Cortex-M0+ */ +#define __O volatile /*!< Defines 'write only' permissions */ +#define __IO volatile /*!< Defines 'read / write' permissions */ + /*@} end of group Cortex-M0+ */ - -/******************************************************************************* + /******************************************************************************* * Register Abstraction Core Register contain: - Core Register @@ -220,371 +217,364 @@ - Core SysTick Register - Core MPU Register ******************************************************************************/ -/** \defgroup CMSIS_core_register Defines and Type Definitions + /** \defgroup CMSIS_core_register Defines and Type Definitions \brief Type definitions and defines for Cortex-M processor based devices. */ -/** \ingroup CMSIS_core_register + /** \ingroup CMSIS_core_register \defgroup CMSIS_CORE Status and Control Registers \brief Core Register type definitions. @{ */ -/** \brief Union type to access the Application Program Status Register (APSR). + /** \brief Union type to access the Application Program Status Register (APSR). */ -typedef union -{ - struct - { + typedef union + { + struct + { #if (__CORTEX_M != 0x04) - uint32_t _reserved0:27; /*!< bit: 0..26 Reserved */ + uint32_t _reserved0 : 27; /*!< bit: 0..26 Reserved */ #else - uint32_t _reserved0:16; /*!< bit: 0..15 Reserved */ - uint32_t GE:4; /*!< bit: 16..19 Greater than or Equal flags */ - uint32_t _reserved1:7; /*!< bit: 20..26 Reserved */ + uint32_t _reserved0 : 16; /*!< bit: 0..15 Reserved */ + uint32_t GE : 4; /*!< bit: 16..19 Greater than or Equal flags */ + uint32_t _reserved1 : 7; /*!< bit: 20..26 Reserved */ #endif - uint32_t Q:1; /*!< bit: 27 Saturation condition flag */ - uint32_t V:1; /*!< bit: 28 Overflow condition code flag */ - uint32_t C:1; /*!< bit: 29 Carry condition code flag */ - uint32_t Z:1; /*!< bit: 30 Zero condition code flag */ - uint32_t N:1; /*!< bit: 31 Negative condition code flag */ - } b; /*!< Structure used for bit access */ - uint32_t w; /*!< Type used for word access */ -} APSR_Type; - + uint32_t Q : 1; /*!< bit: 27 Saturation condition flag */ + uint32_t V : 1; /*!< bit: 28 Overflow condition code flag */ + uint32_t C : 1; /*!< bit: 29 Carry condition code flag */ + uint32_t Z : 1; /*!< bit: 30 Zero condition code flag */ + uint32_t N : 1; /*!< bit: 31 Negative condition code flag */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ + } APSR_Type; -/** \brief Union type to access the Interrupt Program Status Register (IPSR). + /** \brief Union type to access the Interrupt Program Status Register (IPSR). */ -typedef union -{ - struct - { - uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */ - uint32_t _reserved0:23; /*!< bit: 9..31 Reserved */ - } b; /*!< Structure used for bit access */ - uint32_t w; /*!< Type used for word access */ -} IPSR_Type; - + typedef union + { + struct + { + uint32_t ISR : 9; /*!< bit: 0.. 8 Exception number */ + uint32_t _reserved0 : 23; /*!< bit: 9..31 Reserved */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ + } IPSR_Type; -/** \brief Union type to access the Special-Purpose Program Status Registers (xPSR). + /** \brief Union type to access the Special-Purpose Program Status Registers (xPSR). */ -typedef union -{ - struct - { - uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */ + typedef union + { + struct + { + uint32_t ISR : 9; /*!< bit: 0.. 8 Exception number */ #if (__CORTEX_M != 0x04) - uint32_t _reserved0:15; /*!< bit: 9..23 Reserved */ + uint32_t _reserved0 : 15; /*!< bit: 9..23 Reserved */ #else - uint32_t _reserved0:7; /*!< bit: 9..15 Reserved */ - uint32_t GE:4; /*!< bit: 16..19 Greater than or Equal flags */ - uint32_t _reserved1:4; /*!< bit: 20..23 Reserved */ + uint32_t _reserved0 : 7; /*!< bit: 9..15 Reserved */ + uint32_t GE : 4; /*!< bit: 16..19 Greater than or Equal flags */ + uint32_t _reserved1 : 4; /*!< bit: 20..23 Reserved */ #endif - uint32_t T:1; /*!< bit: 24 Thumb bit (read 0) */ - uint32_t IT:2; /*!< bit: 25..26 saved IT state (read 0) */ - uint32_t Q:1; /*!< bit: 27 Saturation condition flag */ - uint32_t V:1; /*!< bit: 28 Overflow condition code flag */ - uint32_t C:1; /*!< bit: 29 Carry condition code flag */ - uint32_t Z:1; /*!< bit: 30 Zero condition code flag */ - uint32_t N:1; /*!< bit: 31 Negative condition code flag */ - } b; /*!< Structure used for bit access */ - uint32_t w; /*!< Type used for word access */ -} xPSR_Type; - + uint32_t T : 1; /*!< bit: 24 Thumb bit (read 0) */ + uint32_t IT : 2; /*!< bit: 25..26 saved IT state (read 0) */ + uint32_t Q : 1; /*!< bit: 27 Saturation condition flag */ + uint32_t V : 1; /*!< bit: 28 Overflow condition code flag */ + uint32_t C : 1; /*!< bit: 29 Carry condition code flag */ + uint32_t Z : 1; /*!< bit: 30 Zero condition code flag */ + uint32_t N : 1; /*!< bit: 31 Negative condition code flag */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ + } xPSR_Type; -/** \brief Union type to access the Control Registers (CONTROL). + /** \brief Union type to access the Control Registers (CONTROL). */ -typedef union -{ - struct - { - uint32_t nPRIV:1; /*!< bit: 0 Execution privilege in Thread mode */ - uint32_t SPSEL:1; /*!< bit: 1 Stack to be used */ - uint32_t FPCA:1; /*!< bit: 2 FP extension active flag */ - uint32_t _reserved0:29; /*!< bit: 3..31 Reserved */ - } b; /*!< Structure used for bit access */ - uint32_t w; /*!< Type used for word access */ -} CONTROL_Type; + typedef union + { + struct + { + uint32_t nPRIV : 1; /*!< bit: 0 Execution privilege in Thread mode */ + uint32_t SPSEL : 1; /*!< bit: 1 Stack to be used */ + uint32_t FPCA : 1; /*!< bit: 2 FP extension active flag */ + uint32_t _reserved0 : 29; /*!< bit: 3..31 Reserved */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ + } CONTROL_Type; -/*@} end of group CMSIS_CORE */ + /*@} end of group CMSIS_CORE */ - -/** \ingroup CMSIS_core_register + /** \ingroup CMSIS_core_register \defgroup CMSIS_NVIC Nested Vectored Interrupt Controller (NVIC) \brief Type definitions for the NVIC Registers @{ */ -/** \brief Structure type to access the Nested Vectored Interrupt Controller (NVIC). + /** \brief Structure type to access the Nested Vectored Interrupt Controller (NVIC). */ -typedef struct -{ - __IO uint32_t ISER[1]; /*!< Offset: 0x000 (R/W) Interrupt Set Enable Register */ - uint32_t RESERVED0[31]; - __IO uint32_t ICER[1]; /*!< Offset: 0x080 (R/W) Interrupt Clear Enable Register */ - uint32_t RSERVED1[31]; - __IO uint32_t ISPR[1]; /*!< Offset: 0x100 (R/W) Interrupt Set Pending Register */ - uint32_t RESERVED2[31]; - __IO uint32_t ICPR[1]; /*!< Offset: 0x180 (R/W) Interrupt Clear Pending Register */ - uint32_t RESERVED3[31]; - uint32_t RESERVED4[64]; - __IO uint32_t IP[8]; /*!< Offset: 0x300 (R/W) Interrupt Priority Register */ -} NVIC_Type; - -/*@} end of group CMSIS_NVIC */ + typedef struct + { + __IO uint32_t ISER[1]; /*!< Offset: 0x000 (R/W) Interrupt Set Enable Register */ + uint32_t RESERVED0[31]; + __IO uint32_t ICER[1]; /*!< Offset: 0x080 (R/W) Interrupt Clear Enable Register */ + uint32_t RSERVED1[31]; + __IO uint32_t ISPR[1]; /*!< Offset: 0x100 (R/W) Interrupt Set Pending Register */ + uint32_t RESERVED2[31]; + __IO uint32_t ICPR[1]; /*!< Offset: 0x180 (R/W) Interrupt Clear Pending Register */ + uint32_t RESERVED3[31]; + uint32_t RESERVED4[64]; + __IO uint32_t IP[8]; /*!< Offset: 0x300 (R/W) Interrupt Priority Register */ + } NVIC_Type; + /*@} end of group CMSIS_NVIC */ -/** \ingroup CMSIS_core_register + /** \ingroup CMSIS_core_register \defgroup CMSIS_SCB System Control Block (SCB) \brief Type definitions for the System Control Block Registers @{ */ -/** \brief Structure type to access the System Control Block (SCB). + /** \brief Structure type to access the System Control Block (SCB). */ -typedef struct -{ - __I uint32_t CPUID; /*!< Offset: 0x000 (R/ ) CPUID Base Register */ - __IO uint32_t ICSR; /*!< Offset: 0x004 (R/W) Interrupt Control and State Register */ + typedef struct + { + __I uint32_t CPUID; /*!< Offset: 0x000 (R/ ) CPUID Base Register */ + __IO uint32_t ICSR; /*!< Offset: 0x004 (R/W) Interrupt Control and State Register */ #if (__VTOR_PRESENT == 1) - __IO uint32_t VTOR; /*!< Offset: 0x008 (R/W) Vector Table Offset Register */ + __IO uint32_t VTOR; /*!< Offset: 0x008 (R/W) Vector Table Offset Register */ #else - uint32_t RESERVED0; + uint32_t RESERVED0; #endif - __IO uint32_t AIRCR; /*!< Offset: 0x00C (R/W) Application Interrupt and Reset Control Register */ - __IO uint32_t SCR; /*!< Offset: 0x010 (R/W) System Control Register */ - __IO uint32_t CCR; /*!< Offset: 0x014 (R/W) Configuration Control Register */ - uint32_t RESERVED1; - __IO uint32_t SHP[2]; /*!< Offset: 0x01C (R/W) System Handlers Priority Registers. [0] is RESERVED */ - __IO uint32_t SHCSR; /*!< Offset: 0x024 (R/W) System Handler Control and State Register */ -} SCB_Type; + __IO uint32_t AIRCR; /*!< Offset: 0x00C (R/W) Application Interrupt and Reset Control Register */ + __IO uint32_t SCR; /*!< Offset: 0x010 (R/W) System Control Register */ + __IO uint32_t CCR; /*!< Offset: 0x014 (R/W) Configuration Control Register */ + uint32_t RESERVED1; + __IO uint32_t SHP[2]; /*!< Offset: 0x01C (R/W) System Handlers Priority Registers. [0] is RESERVED */ + __IO uint32_t SHCSR; /*!< Offset: 0x024 (R/W) System Handler Control and State Register */ + } SCB_Type; /* SCB CPUID Register Definitions */ -#define SCB_CPUID_IMPLEMENTER_Pos 24 /*!< SCB CPUID: IMPLEMENTER Position */ -#define SCB_CPUID_IMPLEMENTER_Msk (0xFFUL << SCB_CPUID_IMPLEMENTER_Pos) /*!< SCB CPUID: IMPLEMENTER Mask */ +#define SCB_CPUID_IMPLEMENTER_Pos 24 /*!< SCB CPUID: IMPLEMENTER Position */ +#define SCB_CPUID_IMPLEMENTER_Msk (0xFFUL << SCB_CPUID_IMPLEMENTER_Pos) /*!< SCB CPUID: IMPLEMENTER Mask */ -#define SCB_CPUID_VARIANT_Pos 20 /*!< SCB CPUID: VARIANT Position */ -#define SCB_CPUID_VARIANT_Msk (0xFUL << SCB_CPUID_VARIANT_Pos) /*!< SCB CPUID: VARIANT Mask */ +#define SCB_CPUID_VARIANT_Pos 20 /*!< SCB CPUID: VARIANT Position */ +#define SCB_CPUID_VARIANT_Msk (0xFUL << SCB_CPUID_VARIANT_Pos) /*!< SCB CPUID: VARIANT Mask */ -#define SCB_CPUID_ARCHITECTURE_Pos 16 /*!< SCB CPUID: ARCHITECTURE Position */ -#define SCB_CPUID_ARCHITECTURE_Msk (0xFUL << SCB_CPUID_ARCHITECTURE_Pos) /*!< SCB CPUID: ARCHITECTURE Mask */ +#define SCB_CPUID_ARCHITECTURE_Pos 16 /*!< SCB CPUID: ARCHITECTURE Position */ +#define SCB_CPUID_ARCHITECTURE_Msk (0xFUL << SCB_CPUID_ARCHITECTURE_Pos) /*!< SCB CPUID: ARCHITECTURE Mask */ -#define SCB_CPUID_PARTNO_Pos 4 /*!< SCB CPUID: PARTNO Position */ -#define SCB_CPUID_PARTNO_Msk (0xFFFUL << SCB_CPUID_PARTNO_Pos) /*!< SCB CPUID: PARTNO Mask */ +#define SCB_CPUID_PARTNO_Pos 4 /*!< SCB CPUID: PARTNO Position */ +#define SCB_CPUID_PARTNO_Msk (0xFFFUL << SCB_CPUID_PARTNO_Pos) /*!< SCB CPUID: PARTNO Mask */ -#define SCB_CPUID_REVISION_Pos 0 /*!< SCB CPUID: REVISION Position */ -#define SCB_CPUID_REVISION_Msk (0xFUL << SCB_CPUID_REVISION_Pos) /*!< SCB CPUID: REVISION Mask */ +#define SCB_CPUID_REVISION_Pos 0 /*!< SCB CPUID: REVISION Position */ +#define SCB_CPUID_REVISION_Msk (0xFUL << SCB_CPUID_REVISION_Pos) /*!< SCB CPUID: REVISION Mask */ /* SCB Interrupt Control State Register Definitions */ -#define SCB_ICSR_NMIPENDSET_Pos 31 /*!< SCB ICSR: NMIPENDSET Position */ -#define SCB_ICSR_NMIPENDSET_Msk (1UL << SCB_ICSR_NMIPENDSET_Pos) /*!< SCB ICSR: NMIPENDSET Mask */ +#define SCB_ICSR_NMIPENDSET_Pos 31 /*!< SCB ICSR: NMIPENDSET Position */ +#define SCB_ICSR_NMIPENDSET_Msk (1UL << SCB_ICSR_NMIPENDSET_Pos) /*!< SCB ICSR: NMIPENDSET Mask */ -#define SCB_ICSR_PENDSVSET_Pos 28 /*!< SCB ICSR: PENDSVSET Position */ -#define SCB_ICSR_PENDSVSET_Msk (1UL << SCB_ICSR_PENDSVSET_Pos) /*!< SCB ICSR: PENDSVSET Mask */ +#define SCB_ICSR_PENDSVSET_Pos 28 /*!< SCB ICSR: PENDSVSET Position */ +#define SCB_ICSR_PENDSVSET_Msk (1UL << SCB_ICSR_PENDSVSET_Pos) /*!< SCB ICSR: PENDSVSET Mask */ -#define SCB_ICSR_PENDSVCLR_Pos 27 /*!< SCB ICSR: PENDSVCLR Position */ -#define SCB_ICSR_PENDSVCLR_Msk (1UL << SCB_ICSR_PENDSVCLR_Pos) /*!< SCB ICSR: PENDSVCLR Mask */ +#define SCB_ICSR_PENDSVCLR_Pos 27 /*!< SCB ICSR: PENDSVCLR Position */ +#define SCB_ICSR_PENDSVCLR_Msk (1UL << SCB_ICSR_PENDSVCLR_Pos) /*!< SCB ICSR: PENDSVCLR Mask */ -#define SCB_ICSR_PENDSTSET_Pos 26 /*!< SCB ICSR: PENDSTSET Position */ -#define SCB_ICSR_PENDSTSET_Msk (1UL << SCB_ICSR_PENDSTSET_Pos) /*!< SCB ICSR: PENDSTSET Mask */ +#define SCB_ICSR_PENDSTSET_Pos 26 /*!< SCB ICSR: PENDSTSET Position */ +#define SCB_ICSR_PENDSTSET_Msk (1UL << SCB_ICSR_PENDSTSET_Pos) /*!< SCB ICSR: PENDSTSET Mask */ -#define SCB_ICSR_PENDSTCLR_Pos 25 /*!< SCB ICSR: PENDSTCLR Position */ -#define SCB_ICSR_PENDSTCLR_Msk (1UL << SCB_ICSR_PENDSTCLR_Pos) /*!< SCB ICSR: PENDSTCLR Mask */ +#define SCB_ICSR_PENDSTCLR_Pos 25 /*!< SCB ICSR: PENDSTCLR Position */ +#define SCB_ICSR_PENDSTCLR_Msk (1UL << SCB_ICSR_PENDSTCLR_Pos) /*!< SCB ICSR: PENDSTCLR Mask */ -#define SCB_ICSR_ISRPREEMPT_Pos 23 /*!< SCB ICSR: ISRPREEMPT Position */ -#define SCB_ICSR_ISRPREEMPT_Msk (1UL << SCB_ICSR_ISRPREEMPT_Pos) /*!< SCB ICSR: ISRPREEMPT Mask */ +#define SCB_ICSR_ISRPREEMPT_Pos 23 /*!< SCB ICSR: ISRPREEMPT Position */ +#define SCB_ICSR_ISRPREEMPT_Msk (1UL << SCB_ICSR_ISRPREEMPT_Pos) /*!< SCB ICSR: ISRPREEMPT Mask */ -#define SCB_ICSR_ISRPENDING_Pos 22 /*!< SCB ICSR: ISRPENDING Position */ -#define SCB_ICSR_ISRPENDING_Msk (1UL << SCB_ICSR_ISRPENDING_Pos) /*!< SCB ICSR: ISRPENDING Mask */ +#define SCB_ICSR_ISRPENDING_Pos 22 /*!< SCB ICSR: ISRPENDING Position */ +#define SCB_ICSR_ISRPENDING_Msk (1UL << SCB_ICSR_ISRPENDING_Pos) /*!< SCB ICSR: ISRPENDING Mask */ -#define SCB_ICSR_VECTPENDING_Pos 12 /*!< SCB ICSR: VECTPENDING Position */ -#define SCB_ICSR_VECTPENDING_Msk (0x1FFUL << SCB_ICSR_VECTPENDING_Pos) /*!< SCB ICSR: VECTPENDING Mask */ +#define SCB_ICSR_VECTPENDING_Pos 12 /*!< SCB ICSR: VECTPENDING Position */ +#define SCB_ICSR_VECTPENDING_Msk (0x1FFUL << SCB_ICSR_VECTPENDING_Pos) /*!< SCB ICSR: VECTPENDING Mask */ -#define SCB_ICSR_VECTACTIVE_Pos 0 /*!< SCB ICSR: VECTACTIVE Position */ -#define SCB_ICSR_VECTACTIVE_Msk (0x1FFUL << SCB_ICSR_VECTACTIVE_Pos) /*!< SCB ICSR: VECTACTIVE Mask */ +#define SCB_ICSR_VECTACTIVE_Pos 0 /*!< SCB ICSR: VECTACTIVE Position */ +#define SCB_ICSR_VECTACTIVE_Msk (0x1FFUL << SCB_ICSR_VECTACTIVE_Pos) /*!< SCB ICSR: VECTACTIVE Mask */ #if (__VTOR_PRESENT == 1) /* SCB Interrupt Control State Register Definitions */ -#define SCB_VTOR_TBLOFF_Pos 8 /*!< SCB VTOR: TBLOFF Position */ -#define SCB_VTOR_TBLOFF_Msk (0xFFFFFFUL << SCB_VTOR_TBLOFF_Pos) /*!< SCB VTOR: TBLOFF Mask */ +#define SCB_VTOR_TBLOFF_Pos 8 /*!< SCB VTOR: TBLOFF Position */ +#define SCB_VTOR_TBLOFF_Msk (0xFFFFFFUL << SCB_VTOR_TBLOFF_Pos) /*!< SCB VTOR: TBLOFF Mask */ #endif /* SCB Application Interrupt and Reset Control Register Definitions */ -#define SCB_AIRCR_VECTKEY_Pos 16 /*!< SCB AIRCR: VECTKEY Position */ -#define SCB_AIRCR_VECTKEY_Msk (0xFFFFUL << SCB_AIRCR_VECTKEY_Pos) /*!< SCB AIRCR: VECTKEY Mask */ +#define SCB_AIRCR_VECTKEY_Pos 16 /*!< SCB AIRCR: VECTKEY Position */ +#define SCB_AIRCR_VECTKEY_Msk (0xFFFFUL << SCB_AIRCR_VECTKEY_Pos) /*!< SCB AIRCR: VECTKEY Mask */ -#define SCB_AIRCR_VECTKEYSTAT_Pos 16 /*!< SCB AIRCR: VECTKEYSTAT Position */ -#define SCB_AIRCR_VECTKEYSTAT_Msk (0xFFFFUL << SCB_AIRCR_VECTKEYSTAT_Pos) /*!< SCB AIRCR: VECTKEYSTAT Mask */ +#define SCB_AIRCR_VECTKEYSTAT_Pos 16 /*!< SCB AIRCR: VECTKEYSTAT Position */ +#define SCB_AIRCR_VECTKEYSTAT_Msk (0xFFFFUL << SCB_AIRCR_VECTKEYSTAT_Pos) /*!< SCB AIRCR: VECTKEYSTAT Mask */ -#define SCB_AIRCR_ENDIANESS_Pos 15 /*!< SCB AIRCR: ENDIANESS Position */ -#define SCB_AIRCR_ENDIANESS_Msk (1UL << SCB_AIRCR_ENDIANESS_Pos) /*!< SCB AIRCR: ENDIANESS Mask */ +#define SCB_AIRCR_ENDIANESS_Pos 15 /*!< SCB AIRCR: ENDIANESS Position */ +#define SCB_AIRCR_ENDIANESS_Msk (1UL << SCB_AIRCR_ENDIANESS_Pos) /*!< SCB AIRCR: ENDIANESS Mask */ -#define SCB_AIRCR_SYSRESETREQ_Pos 2 /*!< SCB AIRCR: SYSRESETREQ Position */ -#define SCB_AIRCR_SYSRESETREQ_Msk (1UL << SCB_AIRCR_SYSRESETREQ_Pos) /*!< SCB AIRCR: SYSRESETREQ Mask */ +#define SCB_AIRCR_SYSRESETREQ_Pos 2 /*!< SCB AIRCR: SYSRESETREQ Position */ +#define SCB_AIRCR_SYSRESETREQ_Msk (1UL << SCB_AIRCR_SYSRESETREQ_Pos) /*!< SCB AIRCR: SYSRESETREQ Mask */ -#define SCB_AIRCR_VECTCLRACTIVE_Pos 1 /*!< SCB AIRCR: VECTCLRACTIVE Position */ -#define SCB_AIRCR_VECTCLRACTIVE_Msk (1UL << SCB_AIRCR_VECTCLRACTIVE_Pos) /*!< SCB AIRCR: VECTCLRACTIVE Mask */ +#define SCB_AIRCR_VECTCLRACTIVE_Pos 1 /*!< SCB AIRCR: VECTCLRACTIVE Position */ +#define SCB_AIRCR_VECTCLRACTIVE_Msk (1UL << SCB_AIRCR_VECTCLRACTIVE_Pos) /*!< SCB AIRCR: VECTCLRACTIVE Mask */ /* SCB System Control Register Definitions */ -#define SCB_SCR_SEVONPEND_Pos 4 /*!< SCB SCR: SEVONPEND Position */ -#define SCB_SCR_SEVONPEND_Msk (1UL << SCB_SCR_SEVONPEND_Pos) /*!< SCB SCR: SEVONPEND Mask */ +#define SCB_SCR_SEVONPEND_Pos 4 /*!< SCB SCR: SEVONPEND Position */ +#define SCB_SCR_SEVONPEND_Msk (1UL << SCB_SCR_SEVONPEND_Pos) /*!< SCB SCR: SEVONPEND Mask */ -#define SCB_SCR_SLEEPDEEP_Pos 2 /*!< SCB SCR: SLEEPDEEP Position */ -#define SCB_SCR_SLEEPDEEP_Msk (1UL << SCB_SCR_SLEEPDEEP_Pos) /*!< SCB SCR: SLEEPDEEP Mask */ +#define SCB_SCR_SLEEPDEEP_Pos 2 /*!< SCB SCR: SLEEPDEEP Position */ +#define SCB_SCR_SLEEPDEEP_Msk (1UL << SCB_SCR_SLEEPDEEP_Pos) /*!< SCB SCR: SLEEPDEEP Mask */ -#define SCB_SCR_SLEEPONEXIT_Pos 1 /*!< SCB SCR: SLEEPONEXIT Position */ -#define SCB_SCR_SLEEPONEXIT_Msk (1UL << SCB_SCR_SLEEPONEXIT_Pos) /*!< SCB SCR: SLEEPONEXIT Mask */ +#define SCB_SCR_SLEEPONEXIT_Pos 1 /*!< SCB SCR: SLEEPONEXIT Position */ +#define SCB_SCR_SLEEPONEXIT_Msk (1UL << SCB_SCR_SLEEPONEXIT_Pos) /*!< SCB SCR: SLEEPONEXIT Mask */ /* SCB Configuration Control Register Definitions */ -#define SCB_CCR_STKALIGN_Pos 9 /*!< SCB CCR: STKALIGN Position */ -#define SCB_CCR_STKALIGN_Msk (1UL << SCB_CCR_STKALIGN_Pos) /*!< SCB CCR: STKALIGN Mask */ +#define SCB_CCR_STKALIGN_Pos 9 /*!< SCB CCR: STKALIGN Position */ +#define SCB_CCR_STKALIGN_Msk (1UL << SCB_CCR_STKALIGN_Pos) /*!< SCB CCR: STKALIGN Mask */ -#define SCB_CCR_UNALIGN_TRP_Pos 3 /*!< SCB CCR: UNALIGN_TRP Position */ -#define SCB_CCR_UNALIGN_TRP_Msk (1UL << SCB_CCR_UNALIGN_TRP_Pos) /*!< SCB CCR: UNALIGN_TRP Mask */ +#define SCB_CCR_UNALIGN_TRP_Pos 3 /*!< SCB CCR: UNALIGN_TRP Position */ +#define SCB_CCR_UNALIGN_TRP_Msk (1UL << SCB_CCR_UNALIGN_TRP_Pos) /*!< SCB CCR: UNALIGN_TRP Mask */ /* SCB System Handler Control and State Register Definitions */ -#define SCB_SHCSR_SVCALLPENDED_Pos 15 /*!< SCB SHCSR: SVCALLPENDED Position */ -#define SCB_SHCSR_SVCALLPENDED_Msk (1UL << SCB_SHCSR_SVCALLPENDED_Pos) /*!< SCB SHCSR: SVCALLPENDED Mask */ - -/*@} end of group CMSIS_SCB */ +#define SCB_SHCSR_SVCALLPENDED_Pos 15 /*!< SCB SHCSR: SVCALLPENDED Position */ +#define SCB_SHCSR_SVCALLPENDED_Msk (1UL << SCB_SHCSR_SVCALLPENDED_Pos) /*!< SCB SHCSR: SVCALLPENDED Mask */ + /*@} end of group CMSIS_SCB */ -/** \ingroup CMSIS_core_register + /** \ingroup CMSIS_core_register \defgroup CMSIS_SysTick System Tick Timer (SysTick) \brief Type definitions for the System Timer Registers. @{ */ -/** \brief Structure type to access the System Timer (SysTick). + /** \brief Structure type to access the System Timer (SysTick). */ -typedef struct -{ - __IO uint32_t CTRL; /*!< Offset: 0x000 (R/W) SysTick Control and Status Register */ - __IO uint32_t LOAD; /*!< Offset: 0x004 (R/W) SysTick Reload Value Register */ - __IO uint32_t VAL; /*!< Offset: 0x008 (R/W) SysTick Current Value Register */ - __I uint32_t CALIB; /*!< Offset: 0x00C (R/ ) SysTick Calibration Register */ -} SysTick_Type; + typedef struct + { + __IO uint32_t CTRL; /*!< Offset: 0x000 (R/W) SysTick Control and Status Register */ + __IO uint32_t LOAD; /*!< Offset: 0x004 (R/W) SysTick Reload Value Register */ + __IO uint32_t VAL; /*!< Offset: 0x008 (R/W) SysTick Current Value Register */ + __I uint32_t CALIB; /*!< Offset: 0x00C (R/ ) SysTick Calibration Register */ + } SysTick_Type; /* SysTick Control / Status Register Definitions */ -#define SysTick_CTRL_COUNTFLAG_Pos 16 /*!< SysTick CTRL: COUNTFLAG Position */ -#define SysTick_CTRL_COUNTFLAG_Msk (1UL << SysTick_CTRL_COUNTFLAG_Pos) /*!< SysTick CTRL: COUNTFLAG Mask */ +#define SysTick_CTRL_COUNTFLAG_Pos 16 /*!< SysTick CTRL: COUNTFLAG Position */ +#define SysTick_CTRL_COUNTFLAG_Msk (1UL << SysTick_CTRL_COUNTFLAG_Pos) /*!< SysTick CTRL: COUNTFLAG Mask */ -#define SysTick_CTRL_CLKSOURCE_Pos 2 /*!< SysTick CTRL: CLKSOURCE Position */ -#define SysTick_CTRL_CLKSOURCE_Msk (1UL << SysTick_CTRL_CLKSOURCE_Pos) /*!< SysTick CTRL: CLKSOURCE Mask */ +#define SysTick_CTRL_CLKSOURCE_Pos 2 /*!< SysTick CTRL: CLKSOURCE Position */ +#define SysTick_CTRL_CLKSOURCE_Msk (1UL << SysTick_CTRL_CLKSOURCE_Pos) /*!< SysTick CTRL: CLKSOURCE Mask */ -#define SysTick_CTRL_TICKINT_Pos 1 /*!< SysTick CTRL: TICKINT Position */ -#define SysTick_CTRL_TICKINT_Msk (1UL << SysTick_CTRL_TICKINT_Pos) /*!< SysTick CTRL: TICKINT Mask */ +#define SysTick_CTRL_TICKINT_Pos 1 /*!< SysTick CTRL: TICKINT Position */ +#define SysTick_CTRL_TICKINT_Msk (1UL << SysTick_CTRL_TICKINT_Pos) /*!< SysTick CTRL: TICKINT Mask */ -#define SysTick_CTRL_ENABLE_Pos 0 /*!< SysTick CTRL: ENABLE Position */ -#define SysTick_CTRL_ENABLE_Msk (1UL << SysTick_CTRL_ENABLE_Pos) /*!< SysTick CTRL: ENABLE Mask */ +#define SysTick_CTRL_ENABLE_Pos 0 /*!< SysTick CTRL: ENABLE Position */ +#define SysTick_CTRL_ENABLE_Msk (1UL << SysTick_CTRL_ENABLE_Pos) /*!< SysTick CTRL: ENABLE Mask */ /* SysTick Reload Register Definitions */ -#define SysTick_LOAD_RELOAD_Pos 0 /*!< SysTick LOAD: RELOAD Position */ -#define SysTick_LOAD_RELOAD_Msk (0xFFFFFFUL << SysTick_LOAD_RELOAD_Pos) /*!< SysTick LOAD: RELOAD Mask */ +#define SysTick_LOAD_RELOAD_Pos 0 /*!< SysTick LOAD: RELOAD Position */ +#define SysTick_LOAD_RELOAD_Msk (0xFFFFFFUL << SysTick_LOAD_RELOAD_Pos) /*!< SysTick LOAD: RELOAD Mask */ /* SysTick Current Register Definitions */ -#define SysTick_VAL_CURRENT_Pos 0 /*!< SysTick VAL: CURRENT Position */ -#define SysTick_VAL_CURRENT_Msk (0xFFFFFFUL << SysTick_VAL_CURRENT_Pos) /*!< SysTick VAL: CURRENT Mask */ +#define SysTick_VAL_CURRENT_Pos 0 /*!< SysTick VAL: CURRENT Position */ +#define SysTick_VAL_CURRENT_Msk (0xFFFFFFUL << SysTick_VAL_CURRENT_Pos) /*!< SysTick VAL: CURRENT Mask */ /* SysTick Calibration Register Definitions */ -#define SysTick_CALIB_NOREF_Pos 31 /*!< SysTick CALIB: NOREF Position */ -#define SysTick_CALIB_NOREF_Msk (1UL << SysTick_CALIB_NOREF_Pos) /*!< SysTick CALIB: NOREF Mask */ +#define SysTick_CALIB_NOREF_Pos 31 /*!< SysTick CALIB: NOREF Position */ +#define SysTick_CALIB_NOREF_Msk (1UL << SysTick_CALIB_NOREF_Pos) /*!< SysTick CALIB: NOREF Mask */ -#define SysTick_CALIB_SKEW_Pos 30 /*!< SysTick CALIB: SKEW Position */ -#define SysTick_CALIB_SKEW_Msk (1UL << SysTick_CALIB_SKEW_Pos) /*!< SysTick CALIB: SKEW Mask */ +#define SysTick_CALIB_SKEW_Pos 30 /*!< SysTick CALIB: SKEW Position */ +#define SysTick_CALIB_SKEW_Msk (1UL << SysTick_CALIB_SKEW_Pos) /*!< SysTick CALIB: SKEW Mask */ -#define SysTick_CALIB_TENMS_Pos 0 /*!< SysTick CALIB: TENMS Position */ -#define SysTick_CALIB_TENMS_Msk (0xFFFFFFUL << SysTick_CALIB_TENMS_Pos) /*!< SysTick CALIB: TENMS Mask */ +#define SysTick_CALIB_TENMS_Pos 0 /*!< SysTick CALIB: TENMS Position */ +#define SysTick_CALIB_TENMS_Msk (0xFFFFFFUL << SysTick_CALIB_TENMS_Pos) /*!< SysTick CALIB: TENMS Mask */ -/*@} end of group CMSIS_SysTick */ + /*@} end of group CMSIS_SysTick */ #if (__MPU_PRESENT == 1) -/** \ingroup CMSIS_core_register + /** \ingroup CMSIS_core_register \defgroup CMSIS_MPU Memory Protection Unit (MPU) \brief Type definitions for the Memory Protection Unit (MPU) @{ */ -/** \brief Structure type to access the Memory Protection Unit (MPU). + /** \brief Structure type to access the Memory Protection Unit (MPU). */ -typedef struct -{ - __I uint32_t TYPE; /*!< Offset: 0x000 (R/ ) MPU Type Register */ - __IO uint32_t CTRL; /*!< Offset: 0x004 (R/W) MPU Control Register */ - __IO uint32_t RNR; /*!< Offset: 0x008 (R/W) MPU Region RNRber Register */ - __IO uint32_t RBAR; /*!< Offset: 0x00C (R/W) MPU Region Base Address Register */ - __IO uint32_t RASR; /*!< Offset: 0x010 (R/W) MPU Region Attribute and Size Register */ -} MPU_Type; + typedef struct + { + __I uint32_t TYPE; /*!< Offset: 0x000 (R/ ) MPU Type Register */ + __IO uint32_t CTRL; /*!< Offset: 0x004 (R/W) MPU Control Register */ + __IO uint32_t RNR; /*!< Offset: 0x008 (R/W) MPU Region RNRber Register */ + __IO uint32_t RBAR; /*!< Offset: 0x00C (R/W) MPU Region Base Address Register */ + __IO uint32_t RASR; /*!< Offset: 0x010 (R/W) MPU Region Attribute and Size Register */ + } MPU_Type; /* MPU Type Register */ -#define MPU_TYPE_IREGION_Pos 16 /*!< MPU TYPE: IREGION Position */ -#define MPU_TYPE_IREGION_Msk (0xFFUL << MPU_TYPE_IREGION_Pos) /*!< MPU TYPE: IREGION Mask */ +#define MPU_TYPE_IREGION_Pos 16 /*!< MPU TYPE: IREGION Position */ +#define MPU_TYPE_IREGION_Msk (0xFFUL << MPU_TYPE_IREGION_Pos) /*!< MPU TYPE: IREGION Mask */ -#define MPU_TYPE_DREGION_Pos 8 /*!< MPU TYPE: DREGION Position */ -#define MPU_TYPE_DREGION_Msk (0xFFUL << MPU_TYPE_DREGION_Pos) /*!< MPU TYPE: DREGION Mask */ +#define MPU_TYPE_DREGION_Pos 8 /*!< MPU TYPE: DREGION Position */ +#define MPU_TYPE_DREGION_Msk (0xFFUL << MPU_TYPE_DREGION_Pos) /*!< MPU TYPE: DREGION Mask */ -#define MPU_TYPE_SEPARATE_Pos 0 /*!< MPU TYPE: SEPARATE Position */ -#define MPU_TYPE_SEPARATE_Msk (1UL << MPU_TYPE_SEPARATE_Pos) /*!< MPU TYPE: SEPARATE Mask */ +#define MPU_TYPE_SEPARATE_Pos 0 /*!< MPU TYPE: SEPARATE Position */ +#define MPU_TYPE_SEPARATE_Msk (1UL << MPU_TYPE_SEPARATE_Pos) /*!< MPU TYPE: SEPARATE Mask */ /* MPU Control Register */ -#define MPU_CTRL_PRIVDEFENA_Pos 2 /*!< MPU CTRL: PRIVDEFENA Position */ -#define MPU_CTRL_PRIVDEFENA_Msk (1UL << MPU_CTRL_PRIVDEFENA_Pos) /*!< MPU CTRL: PRIVDEFENA Mask */ +#define MPU_CTRL_PRIVDEFENA_Pos 2 /*!< MPU CTRL: PRIVDEFENA Position */ +#define MPU_CTRL_PRIVDEFENA_Msk (1UL << MPU_CTRL_PRIVDEFENA_Pos) /*!< MPU CTRL: PRIVDEFENA Mask */ -#define MPU_CTRL_HFNMIENA_Pos 1 /*!< MPU CTRL: HFNMIENA Position */ -#define MPU_CTRL_HFNMIENA_Msk (1UL << MPU_CTRL_HFNMIENA_Pos) /*!< MPU CTRL: HFNMIENA Mask */ +#define MPU_CTRL_HFNMIENA_Pos 1 /*!< MPU CTRL: HFNMIENA Position */ +#define MPU_CTRL_HFNMIENA_Msk (1UL << MPU_CTRL_HFNMIENA_Pos) /*!< MPU CTRL: HFNMIENA Mask */ -#define MPU_CTRL_ENABLE_Pos 0 /*!< MPU CTRL: ENABLE Position */ -#define MPU_CTRL_ENABLE_Msk (1UL << MPU_CTRL_ENABLE_Pos) /*!< MPU CTRL: ENABLE Mask */ +#define MPU_CTRL_ENABLE_Pos 0 /*!< MPU CTRL: ENABLE Position */ +#define MPU_CTRL_ENABLE_Msk (1UL << MPU_CTRL_ENABLE_Pos) /*!< MPU CTRL: ENABLE Mask */ /* MPU Region Number Register */ -#define MPU_RNR_REGION_Pos 0 /*!< MPU RNR: REGION Position */ -#define MPU_RNR_REGION_Msk (0xFFUL << MPU_RNR_REGION_Pos) /*!< MPU RNR: REGION Mask */ +#define MPU_RNR_REGION_Pos 0 /*!< MPU RNR: REGION Position */ +#define MPU_RNR_REGION_Msk (0xFFUL << MPU_RNR_REGION_Pos) /*!< MPU RNR: REGION Mask */ /* MPU Region Base Address Register */ -#define MPU_RBAR_ADDR_Pos 8 /*!< MPU RBAR: ADDR Position */ -#define MPU_RBAR_ADDR_Msk (0xFFFFFFUL << MPU_RBAR_ADDR_Pos) /*!< MPU RBAR: ADDR Mask */ +#define MPU_RBAR_ADDR_Pos 8 /*!< MPU RBAR: ADDR Position */ +#define MPU_RBAR_ADDR_Msk (0xFFFFFFUL << MPU_RBAR_ADDR_Pos) /*!< MPU RBAR: ADDR Mask */ -#define MPU_RBAR_VALID_Pos 4 /*!< MPU RBAR: VALID Position */ -#define MPU_RBAR_VALID_Msk (1UL << MPU_RBAR_VALID_Pos) /*!< MPU RBAR: VALID Mask */ +#define MPU_RBAR_VALID_Pos 4 /*!< MPU RBAR: VALID Position */ +#define MPU_RBAR_VALID_Msk (1UL << MPU_RBAR_VALID_Pos) /*!< MPU RBAR: VALID Mask */ -#define MPU_RBAR_REGION_Pos 0 /*!< MPU RBAR: REGION Position */ -#define MPU_RBAR_REGION_Msk (0xFUL << MPU_RBAR_REGION_Pos) /*!< MPU RBAR: REGION Mask */ +#define MPU_RBAR_REGION_Pos 0 /*!< MPU RBAR: REGION Position */ +#define MPU_RBAR_REGION_Msk (0xFUL << MPU_RBAR_REGION_Pos) /*!< MPU RBAR: REGION Mask */ /* MPU Region Attribute and Size Register */ -#define MPU_RASR_ATTRS_Pos 16 /*!< MPU RASR: MPU Region Attribute field Position */ -#define MPU_RASR_ATTRS_Msk (0xFFFFUL << MPU_RASR_ATTRS_Pos) /*!< MPU RASR: MPU Region Attribute field Mask */ +#define MPU_RASR_ATTRS_Pos 16 /*!< MPU RASR: MPU Region Attribute field Position */ +#define MPU_RASR_ATTRS_Msk (0xFFFFUL << MPU_RASR_ATTRS_Pos) /*!< MPU RASR: MPU Region Attribute field Mask */ -#define MPU_RASR_XN_Pos 28 /*!< MPU RASR: ATTRS.XN Position */ -#define MPU_RASR_XN_Msk (1UL << MPU_RASR_XN_Pos) /*!< MPU RASR: ATTRS.XN Mask */ +#define MPU_RASR_XN_Pos 28 /*!< MPU RASR: ATTRS.XN Position */ +#define MPU_RASR_XN_Msk (1UL << MPU_RASR_XN_Pos) /*!< MPU RASR: ATTRS.XN Mask */ -#define MPU_RASR_AP_Pos 24 /*!< MPU RASR: ATTRS.AP Position */ -#define MPU_RASR_AP_Msk (0x7UL << MPU_RASR_AP_Pos) /*!< MPU RASR: ATTRS.AP Mask */ +#define MPU_RASR_AP_Pos 24 /*!< MPU RASR: ATTRS.AP Position */ +#define MPU_RASR_AP_Msk (0x7UL << MPU_RASR_AP_Pos) /*!< MPU RASR: ATTRS.AP Mask */ -#define MPU_RASR_TEX_Pos 19 /*!< MPU RASR: ATTRS.TEX Position */ -#define MPU_RASR_TEX_Msk (0x7UL << MPU_RASR_TEX_Pos) /*!< MPU RASR: ATTRS.TEX Mask */ +#define MPU_RASR_TEX_Pos 19 /*!< MPU RASR: ATTRS.TEX Position */ +#define MPU_RASR_TEX_Msk (0x7UL << MPU_RASR_TEX_Pos) /*!< MPU RASR: ATTRS.TEX Mask */ -#define MPU_RASR_S_Pos 18 /*!< MPU RASR: ATTRS.S Position */ -#define MPU_RASR_S_Msk (1UL << MPU_RASR_S_Pos) /*!< MPU RASR: ATTRS.S Mask */ +#define MPU_RASR_S_Pos 18 /*!< MPU RASR: ATTRS.S Position */ +#define MPU_RASR_S_Msk (1UL << MPU_RASR_S_Pos) /*!< MPU RASR: ATTRS.S Mask */ -#define MPU_RASR_C_Pos 17 /*!< MPU RASR: ATTRS.C Position */ -#define MPU_RASR_C_Msk (1UL << MPU_RASR_C_Pos) /*!< MPU RASR: ATTRS.C Mask */ +#define MPU_RASR_C_Pos 17 /*!< MPU RASR: ATTRS.C Position */ +#define MPU_RASR_C_Msk (1UL << MPU_RASR_C_Pos) /*!< MPU RASR: ATTRS.C Mask */ -#define MPU_RASR_B_Pos 16 /*!< MPU RASR: ATTRS.B Position */ -#define MPU_RASR_B_Msk (1UL << MPU_RASR_B_Pos) /*!< MPU RASR: ATTRS.B Mask */ +#define MPU_RASR_B_Pos 16 /*!< MPU RASR: ATTRS.B Position */ +#define MPU_RASR_B_Msk (1UL << MPU_RASR_B_Pos) /*!< MPU RASR: ATTRS.B Mask */ -#define MPU_RASR_SRD_Pos 8 /*!< MPU RASR: Sub-Region Disable Position */ -#define MPU_RASR_SRD_Msk (0xFFUL << MPU_RASR_SRD_Pos) /*!< MPU RASR: Sub-Region Disable Mask */ +#define MPU_RASR_SRD_Pos 8 /*!< MPU RASR: Sub-Region Disable Position */ +#define MPU_RASR_SRD_Msk (0xFFUL << MPU_RASR_SRD_Pos) /*!< MPU RASR: Sub-Region Disable Mask */ -#define MPU_RASR_SIZE_Pos 1 /*!< MPU RASR: Region Size Field Position */ -#define MPU_RASR_SIZE_Msk (0x1FUL << MPU_RASR_SIZE_Pos) /*!< MPU RASR: Region Size Field Mask */ +#define MPU_RASR_SIZE_Pos 1 /*!< MPU RASR: Region Size Field Position */ +#define MPU_RASR_SIZE_Msk (0x1FUL << MPU_RASR_SIZE_Pos) /*!< MPU RASR: Region Size Field Mask */ -#define MPU_RASR_ENABLE_Pos 0 /*!< MPU RASR: Region enable bit Position */ -#define MPU_RASR_ENABLE_Msk (1UL << MPU_RASR_ENABLE_Pos) /*!< MPU RASR: Region enable bit Disable Mask */ +#define MPU_RASR_ENABLE_Pos 0 /*!< MPU RASR: Region enable bit Position */ +#define MPU_RASR_ENABLE_Msk (1UL << MPU_RASR_ENABLE_Pos) /*!< MPU RASR: Region enable bit Disable Mask */ /*@} end of group CMSIS_MPU */ #endif - /** \ingroup CMSIS_core_register \defgroup CMSIS_CoreDebug Core Debug Registers (CoreDebug) \brief Cortex-M0+ Core Debug Registers (DCB registers, SHCSR, and DFSR) @@ -594,7 +584,6 @@ typedef struct */ /*@} end of group CMSIS_CoreDebug */ - /** \ingroup CMSIS_core_register \defgroup CMSIS_core_base Core Definitions \brief Definitions for base addresses, unions, and structures. @@ -602,24 +591,22 @@ typedef struct */ /* Memory mapping of Cortex-M0+ Hardware */ -#define SCS_BASE (0xE000E000UL) /*!< System Control Space Base Address */ -#define SysTick_BASE (SCS_BASE + 0x0010UL) /*!< SysTick Base Address */ -#define NVIC_BASE (SCS_BASE + 0x0100UL) /*!< NVIC Base Address */ -#define SCB_BASE (SCS_BASE + 0x0D00UL) /*!< System Control Block Base Address */ +#define SCS_BASE (0xE000E000UL) /*!< System Control Space Base Address */ +#define SysTick_BASE (SCS_BASE + 0x0010UL) /*!< SysTick Base Address */ +#define NVIC_BASE (SCS_BASE + 0x0100UL) /*!< NVIC Base Address */ +#define SCB_BASE (SCS_BASE + 0x0D00UL) /*!< System Control Block Base Address */ -#define SCB ((SCB_Type *) SCB_BASE ) /*!< SCB configuration struct */ -#define SysTick ((SysTick_Type *) SysTick_BASE ) /*!< SysTick configuration struct */ -#define NVIC ((NVIC_Type *) NVIC_BASE ) /*!< NVIC configuration struct */ +#define SCB ((SCB_Type *)SCB_BASE) /*!< SCB configuration struct */ +#define SysTick ((SysTick_Type *)SysTick_BASE) /*!< SysTick configuration struct */ +#define NVIC ((NVIC_Type *)NVIC_BASE) /*!< NVIC configuration struct */ #if (__MPU_PRESENT == 1) - #define MPU_BASE (SCS_BASE + 0x0D90UL) /*!< Memory Protection Unit */ - #define MPU ((MPU_Type *) MPU_BASE ) /*!< Memory Protection Unit */ +#define MPU_BASE (SCS_BASE + 0x0D90UL) /*!< Memory Protection Unit */ +#define MPU ((MPU_Type *)MPU_BASE) /*!< Memory Protection Unit */ #endif /*@} */ - - /******************************************************************************* * Hardware Abstraction Layer Core Function Interface contains: @@ -630,8 +617,6 @@ typedef struct /** \defgroup CMSIS_Core_FunctionInterface Functions and Instructions Reference */ - - /* ########################## NVIC functions #################################### */ /** \ingroup CMSIS_Core_FunctionInterface \defgroup CMSIS_Core_NVICFunctions NVIC Functions @@ -641,36 +626,33 @@ typedef struct /* Interrupt Priorities are WORD accessible only under ARMv6M */ /* The following MACROS handle generation of the register offset and byte masks */ -#define _BIT_SHIFT(IRQn) ( (((uint32_t)(IRQn) ) & 0x03) * 8 ) -#define _SHP_IDX(IRQn) ( ((((uint32_t)(IRQn) & 0x0F)-8) >> 2) ) -#define _IP_IDX(IRQn) ( ((uint32_t)(IRQn) >> 2) ) - +#define _BIT_SHIFT(IRQn) ((((uint32_t)(IRQn)) & 0x03) * 8) +#define _SHP_IDX(IRQn) (((((uint32_t)(IRQn)&0x0F) - 8) >> 2)) +#define _IP_IDX(IRQn) (((uint32_t)(IRQn) >> 2)) -/** \brief Enable External Interrupt + /** \brief Enable External Interrupt The function enables a device-specific interrupt in the NVIC interrupt controller. \param [in] IRQn External interrupt number. Value cannot be negative. */ -__STATIC_INLINE void NVIC_EnableIRQ(IRQn_Type IRQn) -{ - NVIC->ISER[0] = (1 << ((uint32_t)(IRQn) & 0x1F)); -} - + __STATIC_INLINE void NVIC_EnableIRQ(IRQn_Type IRQn) + { + NVIC->ISER[0] = (1 << ((uint32_t)(IRQn)&0x1F)); + } -/** \brief Disable External Interrupt + /** \brief Disable External Interrupt The function disables a device-specific interrupt in the NVIC interrupt controller. \param [in] IRQn External interrupt number. Value cannot be negative. */ -__STATIC_INLINE void NVIC_DisableIRQ(IRQn_Type IRQn) -{ - NVIC->ICER[0] = (1 << ((uint32_t)(IRQn) & 0x1F)); -} - + __STATIC_INLINE void NVIC_DisableIRQ(IRQn_Type IRQn) + { + NVIC->ICER[0] = (1 << ((uint32_t)(IRQn)&0x1F)); + } -/** \brief Get Pending Interrupt + /** \brief Get Pending Interrupt The function reads the pending register in the NVIC and returns the pending bit for the specified interrupt. @@ -680,37 +662,34 @@ __STATIC_INLINE void NVIC_DisableIRQ(IRQn_Type IRQn) \return 0 Interrupt status is not pending. \return 1 Interrupt status is pending. */ -__STATIC_INLINE uint32_t NVIC_GetPendingIRQ(IRQn_Type IRQn) -{ - return((uint32_t) ((NVIC->ISPR[0] & (1 << ((uint32_t)(IRQn) & 0x1F)))?1:0)); -} + __STATIC_INLINE uint32_t NVIC_GetPendingIRQ(IRQn_Type IRQn) + { + return ((uint32_t)((NVIC->ISPR[0] & (1 << ((uint32_t)(IRQn)&0x1F))) ? 1 : 0)); + } - -/** \brief Set Pending Interrupt + /** \brief Set Pending Interrupt The function sets the pending bit of an external interrupt. \param [in] IRQn Interrupt number. Value cannot be negative. */ -__STATIC_INLINE void NVIC_SetPendingIRQ(IRQn_Type IRQn) -{ - NVIC->ISPR[0] = (1 << ((uint32_t)(IRQn) & 0x1F)); -} - + __STATIC_INLINE void NVIC_SetPendingIRQ(IRQn_Type IRQn) + { + NVIC->ISPR[0] = (1 << ((uint32_t)(IRQn)&0x1F)); + } -/** \brief Clear Pending Interrupt + /** \brief Clear Pending Interrupt The function clears the pending bit of an external interrupt. \param [in] IRQn External interrupt number. Value cannot be negative. */ -__STATIC_INLINE void NVIC_ClearPendingIRQ(IRQn_Type IRQn) -{ - NVIC->ICPR[0] = (1 << ((uint32_t)(IRQn) & 0x1F)); /* Clear pending interrupt */ -} - + __STATIC_INLINE void NVIC_ClearPendingIRQ(IRQn_Type IRQn) + { + NVIC->ICPR[0] = (1 << ((uint32_t)(IRQn)&0x1F)); /* Clear pending interrupt */ + } -/** \brief Set Interrupt Priority + /** \brief Set Interrupt Priority The function sets the priority of an interrupt. @@ -719,18 +698,21 @@ __STATIC_INLINE void NVIC_ClearPendingIRQ(IRQn_Type IRQn) \param [in] IRQn Interrupt number. \param [in] priority Priority to set. */ -__STATIC_INLINE void NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority) -{ - if(IRQn < 0) { - SCB->SHP[_SHP_IDX(IRQn)] = (SCB->SHP[_SHP_IDX(IRQn)] & ~(0xFF << _BIT_SHIFT(IRQn))) | - (((priority << (8 - __NVIC_PRIO_BITS)) & 0xFF) << _BIT_SHIFT(IRQn)); } - else { - NVIC->IP[_IP_IDX(IRQn)] = (NVIC->IP[_IP_IDX(IRQn)] & ~(0xFF << _BIT_SHIFT(IRQn))) | - (((priority << (8 - __NVIC_PRIO_BITS)) & 0xFF) << _BIT_SHIFT(IRQn)); } -} + __STATIC_INLINE void NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority) + { + if (IRQn < 0) + { + SCB->SHP[_SHP_IDX(IRQn)] = (SCB->SHP[_SHP_IDX(IRQn)] & ~(0xFF << _BIT_SHIFT(IRQn))) | + (((priority << (8 - __NVIC_PRIO_BITS)) & 0xFF) << _BIT_SHIFT(IRQn)); + } + else + { + NVIC->IP[_IP_IDX(IRQn)] = (NVIC->IP[_IP_IDX(IRQn)] & ~(0xFF << _BIT_SHIFT(IRQn))) | + (((priority << (8 - __NVIC_PRIO_BITS)) & 0xFF) << _BIT_SHIFT(IRQn)); + } + } - -/** \brief Get Interrupt Priority + /** \brief Get Interrupt Priority The function reads the priority of an interrupt. The interrupt number can be positive to specify an external (device specific) @@ -741,36 +723,38 @@ __STATIC_INLINE void NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority) \return Interrupt Priority. Value is aligned automatically to the implemented priority bits of the microcontroller. */ -__STATIC_INLINE uint32_t NVIC_GetPriority(IRQn_Type IRQn) -{ + __STATIC_INLINE uint32_t NVIC_GetPriority(IRQn_Type IRQn) + { - if(IRQn < 0) { - return((uint32_t)(((SCB->SHP[_SHP_IDX(IRQn)] >> _BIT_SHIFT(IRQn) ) & 0xFF) >> (8 - __NVIC_PRIO_BITS))); } /* get priority for Cortex-M0 system interrupts */ - else { - return((uint32_t)(((NVIC->IP[ _IP_IDX(IRQn)] >> _BIT_SHIFT(IRQn) ) & 0xFF) >> (8 - __NVIC_PRIO_BITS))); } /* get priority for device specific interrupts */ -} + if (IRQn < 0) + { + return ((uint32_t)(((SCB->SHP[_SHP_IDX(IRQn)] >> _BIT_SHIFT(IRQn)) & 0xFF) >> (8 - __NVIC_PRIO_BITS))); + } /* get priority for Cortex-M0 system interrupts */ + else + { + return ((uint32_t)(((NVIC->IP[_IP_IDX(IRQn)] >> _BIT_SHIFT(IRQn)) & 0xFF) >> (8 - __NVIC_PRIO_BITS))); + } /* get priority for device specific interrupts */ + } - -/** \brief System Reset + /** \brief System Reset The function initiates a system reset request to reset the MCU. */ -__STATIC_INLINE void NVIC_SystemReset(void) -{ - __DSB(); /* Ensure all outstanding memory accesses included + __STATIC_INLINE void NVIC_SystemReset(void) + { + __DSB(); /* Ensure all outstanding memory accesses included buffered write are completed before reset */ - SCB->AIRCR = ((0x5FA << SCB_AIRCR_VECTKEY_Pos) | - SCB_AIRCR_SYSRESETREQ_Msk); - __DSB(); /* Ensure completion of memory access */ - while(1); /* wait until reset */ -} - -/*@} end of CMSIS_Core_NVICFunctions */ - + SCB->AIRCR = ((0x5FA << SCB_AIRCR_VECTKEY_Pos) | + SCB_AIRCR_SYSRESETREQ_Msk); + __DSB(); /* Ensure completion of memory access */ + while (1) + ; /* wait until reset */ + } + /*@} end of CMSIS_Core_NVICFunctions */ -/* ################################## SysTick function ############################################ */ -/** \ingroup CMSIS_Core_FunctionInterface + /* ################################## SysTick function ############################################ */ + /** \ingroup CMSIS_Core_FunctionInterface \defgroup CMSIS_Core_SysTickFunctions SysTick Functions \brief Functions that configure the System. @{ @@ -778,7 +762,7 @@ __STATIC_INLINE void NVIC_SystemReset(void) #if (__Vendor_SysTickConfig == 0) -/** \brief System Tick Configuration + /** \brief System Tick Configuration The function initializes the System Timer and its interrupt, and starts the System Tick Timer. Counter is in free running mode to generate periodic interrupts. @@ -793,25 +777,23 @@ __STATIC_INLINE void NVIC_SystemReset(void) must contain a vendor-specific implementation of this function. */ -__STATIC_INLINE uint32_t SysTick_Config(uint32_t ticks) -{ - if ((ticks - 1) > SysTick_LOAD_RELOAD_Msk) return (1); /* Reload value impossible */ + __STATIC_INLINE uint32_t SysTick_Config(uint32_t ticks) + { + if ((ticks - 1) > SysTick_LOAD_RELOAD_Msk) + return (1); /* Reload value impossible */ - SysTick->LOAD = ticks - 1; /* set reload register */ - NVIC_SetPriority (SysTick_IRQn, (1<<__NVIC_PRIO_BITS) - 1); /* set Priority for Systick Interrupt */ - SysTick->VAL = 0; /* Load the SysTick Counter Value */ - SysTick->CTRL = SysTick_CTRL_CLKSOURCE_Msk | - SysTick_CTRL_TICKINT_Msk | - SysTick_CTRL_ENABLE_Msk; /* Enable SysTick IRQ and SysTick Timer */ - return (0); /* Function successful */ -} + SysTick->LOAD = ticks - 1; /* set reload register */ + NVIC_SetPriority(SysTick_IRQn, (1 << __NVIC_PRIO_BITS) - 1); /* set Priority for Systick Interrupt */ + SysTick->VAL = 0; /* Load the SysTick Counter Value */ + SysTick->CTRL = SysTick_CTRL_CLKSOURCE_Msk | + SysTick_CTRL_TICKINT_Msk | + SysTick_CTRL_ENABLE_Msk; /* Enable SysTick IRQ and SysTick Timer */ + return (0); /* Function successful */ + } #endif -/*@} end of CMSIS_Core_SysTickFunctions */ - - - + /*@} end of CMSIS_Core_SysTickFunctions */ #ifdef __cplusplus } diff --git a/bsp/swm320-lq100/Libraries/CMSIS/CoreSupport/core_cm3.h b/bsp/swm320-lq100/Libraries/CMSIS/CoreSupport/core_cm3.h index e1357c6735..2e6ec11a45 100644 --- a/bsp/swm320-lq100/Libraries/CMSIS/CoreSupport/core_cm3.h +++ b/bsp/swm320-lq100/Libraries/CMSIS/CoreSupport/core_cm3.h @@ -1,4 +1,4 @@ -/**************************************************************************//** +/**************************************************************************/ /** * @file core_cm3.h * @brief CMSIS Cortex-M3 Core Peripheral Access Layer Header File * @version V4.00 @@ -34,16 +34,16 @@ POSSIBILITY OF SUCH DAMAGE. ---------------------------------------------------------------------------*/ - -#if defined ( __ICCARM__ ) - #pragma system_include /* treat file as system include file for MISRA check */ +#if defined(__ICCARM__) +#pragma system_include /* treat file as system include file for MISRA check */ #endif #ifndef __CORE_CM3_H_GENERIC #define __CORE_CM3_H_GENERIC #ifdef __cplusplus - extern "C" { +extern "C" +{ #endif /** \page CMSIS_MISRA_Exceptions MISRA-C:2004 Compliance Exceptions @@ -59,7 +59,6 @@ Function-like macros are used to allow more efficient code. */ - /******************************************************************************* * CMSIS definitions ******************************************************************************/ @@ -68,85 +67,84 @@ */ /* CMSIS CM3 definitions */ -#define __CM3_CMSIS_VERSION_MAIN (0x04) /*!< [31:16] CMSIS HAL main version */ -#define __CM3_CMSIS_VERSION_SUB (0x00) /*!< [15:0] CMSIS HAL sub version */ -#define __CM3_CMSIS_VERSION ((__CM3_CMSIS_VERSION_MAIN << 16) | \ - __CM3_CMSIS_VERSION_SUB ) /*!< CMSIS HAL version number */ - -#define __CORTEX_M (0x03) /*!< Cortex-M Core */ +#define __CM3_CMSIS_VERSION_MAIN (0x04) /*!< [31:16] CMSIS HAL main version */ +#define __CM3_CMSIS_VERSION_SUB (0x00) /*!< [15:0] CMSIS HAL sub version */ +#define __CM3_CMSIS_VERSION ((__CM3_CMSIS_VERSION_MAIN << 16) | \ + __CM3_CMSIS_VERSION_SUB) /*!< CMSIS HAL version number */ +#define __CORTEX_M (0x03) /*!< Cortex-M Core */ -#if defined ( __CC_ARM ) - #define __ASM __asm /*!< asm keyword for ARM Compiler */ - #define __INLINE __inline /*!< inline keyword for ARM Compiler */ - #define __STATIC_INLINE static __inline +#if defined(__CC_ARM) +#define __ASM __asm /*!< asm keyword for ARM Compiler */ +#define __INLINE __inline /*!< inline keyword for ARM Compiler */ +#define __STATIC_INLINE static __inline -#elif defined ( __GNUC__ ) - #define __ASM __asm /*!< asm keyword for GNU Compiler */ - #define __INLINE inline /*!< inline keyword for GNU Compiler */ - #define __STATIC_INLINE static inline +#elif defined(__GNUC__) +#define __ASM __asm /*!< asm keyword for GNU Compiler */ +#define __INLINE inline /*!< inline keyword for GNU Compiler */ +#define __STATIC_INLINE static inline -#elif defined ( __ICCARM__ ) - #define __ASM __asm /*!< asm keyword for IAR Compiler */ - #define __INLINE inline /*!< inline keyword for IAR Compiler. Only available in High optimization mode! */ - #define __STATIC_INLINE static inline +#elif defined(__ICCARM__) +#define __ASM __asm /*!< asm keyword for IAR Compiler */ +#define __INLINE inline /*!< inline keyword for IAR Compiler. Only available in High optimization mode! */ +#define __STATIC_INLINE static inline -#elif defined ( __TMS470__ ) - #define __ASM __asm /*!< asm keyword for TI CCS Compiler */ - #define __STATIC_INLINE static inline +#elif defined(__TMS470__) +#define __ASM __asm /*!< asm keyword for TI CCS Compiler */ +#define __STATIC_INLINE static inline -#elif defined ( __TASKING__ ) - #define __ASM __asm /*!< asm keyword for TASKING Compiler */ - #define __INLINE inline /*!< inline keyword for TASKING Compiler */ - #define __STATIC_INLINE static inline +#elif defined(__TASKING__) +#define __ASM __asm /*!< asm keyword for TASKING Compiler */ +#define __INLINE inline /*!< inline keyword for TASKING Compiler */ +#define __STATIC_INLINE static inline -#elif defined ( __CSMC__ ) - #define __packed - #define __ASM _asm /*!< asm keyword for COSMIC Compiler */ - #define __INLINE inline /*use -pc99 on compile line !< inline keyword for COSMIC Compiler */ - #define __STATIC_INLINE static inline +#elif defined(__CSMC__) +#define __packed +#define __ASM _asm /*!< asm keyword for COSMIC Compiler */ +#define __INLINE inline /*use -pc99 on compile line !< inline keyword for COSMIC Compiler */ +#define __STATIC_INLINE static inline #endif /** __FPU_USED indicates whether an FPU is used or not. This core does not support an FPU at all */ -#define __FPU_USED 0 +#define __FPU_USED 0 -#if defined ( __CC_ARM ) - #if defined __TARGET_FPU_VFP - #warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" - #endif +#if defined(__CC_ARM) +#if defined __TARGET_FPU_VFP +#warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" +#endif -#elif defined ( __GNUC__ ) - #if defined (__VFP_FP__) && !defined(__SOFTFP__) - #warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" - #endif +#elif defined(__GNUC__) +#if defined(__VFP_FP__) && !defined(__SOFTFP__) +#warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" +#endif -#elif defined ( __ICCARM__ ) - #if defined __ARMVFP__ - #warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" - #endif +#elif defined(__ICCARM__) +#if defined __ARMVFP__ +#warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" +#endif -#elif defined ( __TMS470__ ) - #if defined __TI__VFP_SUPPORT____ - #warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" - #endif +#elif defined(__TMS470__) +#if defined __TI__VFP_SUPPORT____ +#warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" +#endif -#elif defined ( __TASKING__ ) - #if defined __FPU_VFP__ - #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" - #endif +#elif defined(__TASKING__) +#if defined __FPU_VFP__ +#error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" +#endif -#elif defined ( __CSMC__ ) /* Cosmic */ - #if ( __CSMC__ & 0x400) // FPU present for parser - #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" - #endif +#elif defined(__CSMC__) /* Cosmic */ +#if (__CSMC__ & 0x400) // FPU present for parser +#error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" +#endif #endif -#include <stdint.h> /* standard types definitions */ -#include <core_cmInstr.h> /* Core Instruction Access */ -#include <core_cmFunc.h> /* Core Function Access */ +#include <stdint.h> /* standard types definitions */ +#include <core_cmInstr.h> /* Core Instruction Access */ +#include <core_cmFunc.h> /* Core Function Access */ #ifdef __cplusplus } @@ -160,30 +158,31 @@ #define __CORE_CM3_H_DEPENDANT #ifdef __cplusplus - extern "C" { +extern "C" +{ #endif /* check device defines and use defaults */ #if defined __CHECK_DEVICE_DEFINES - #ifndef __CM3_REV - #define __CM3_REV 0x0200 - #warning "__CM3_REV not defined in device header file; using default!" - #endif +#ifndef __CM3_REV +#define __CM3_REV 0x0200 +#warning "__CM3_REV not defined in device header file; using default!" +#endif - #ifndef __MPU_PRESENT - #define __MPU_PRESENT 0 - #warning "__MPU_PRESENT not defined in device header file; using default!" - #endif +#ifndef __MPU_PRESENT +#define __MPU_PRESENT 0 +#warning "__MPU_PRESENT not defined in device header file; using default!" +#endif - #ifndef __NVIC_PRIO_BITS - #define __NVIC_PRIO_BITS 4 - #warning "__NVIC_PRIO_BITS not defined in device header file; using default!" - #endif +#ifndef __NVIC_PRIO_BITS +#define __NVIC_PRIO_BITS 4 +#warning "__NVIC_PRIO_BITS not defined in device header file; using default!" +#endif - #ifndef __Vendor_SysTickConfig - #define __Vendor_SysTickConfig 0 - #warning "__Vendor_SysTickConfig not defined in device header file; using default!" - #endif +#ifndef __Vendor_SysTickConfig +#define __Vendor_SysTickConfig 0 +#warning "__Vendor_SysTickConfig not defined in device header file; using default!" +#endif #endif /* IO definitions (access restrictions to peripheral registers) */ @@ -195,18 +194,16 @@ \li for automatic generation of peripheral register debug information. */ #ifdef __cplusplus - #define __I volatile /*!< Defines 'read only' permissions */ +#define __I volatile /*!< Defines 'read only' permissions */ #else - #define __I volatile const /*!< Defines 'read only' permissions */ +#define __I volatile const /*!< Defines 'read only' permissions */ #endif -#define __O volatile /*!< Defines 'write only' permissions */ -#define __IO volatile /*!< Defines 'read / write' permissions */ - -/*@} end of group Cortex_M3 */ +#define __O volatile /*!< Defines 'write only' permissions */ +#define __IO volatile /*!< Defines 'read / write' permissions */ + /*@} end of group Cortex_M3 */ - -/******************************************************************************* + /******************************************************************************* * Register Abstraction Core Register contain: - Core Register @@ -216,1034 +213,1021 @@ - Core Debug Register - Core MPU Register ******************************************************************************/ -/** \defgroup CMSIS_core_register Defines and Type Definitions + /** \defgroup CMSIS_core_register Defines and Type Definitions \brief Type definitions and defines for Cortex-M processor based devices. */ -/** \ingroup CMSIS_core_register + /** \ingroup CMSIS_core_register \defgroup CMSIS_CORE Status and Control Registers \brief Core Register type definitions. @{ */ -/** \brief Union type to access the Application Program Status Register (APSR). + /** \brief Union type to access the Application Program Status Register (APSR). */ -typedef union -{ - struct - { + typedef union + { + struct + { #if (__CORTEX_M != 0x04) - uint32_t _reserved0:27; /*!< bit: 0..26 Reserved */ + uint32_t _reserved0 : 27; /*!< bit: 0..26 Reserved */ #else - uint32_t _reserved0:16; /*!< bit: 0..15 Reserved */ - uint32_t GE:4; /*!< bit: 16..19 Greater than or Equal flags */ - uint32_t _reserved1:7; /*!< bit: 20..26 Reserved */ + uint32_t _reserved0 : 16; /*!< bit: 0..15 Reserved */ + uint32_t GE : 4; /*!< bit: 16..19 Greater than or Equal flags */ + uint32_t _reserved1 : 7; /*!< bit: 20..26 Reserved */ #endif - uint32_t Q:1; /*!< bit: 27 Saturation condition flag */ - uint32_t V:1; /*!< bit: 28 Overflow condition code flag */ - uint32_t C:1; /*!< bit: 29 Carry condition code flag */ - uint32_t Z:1; /*!< bit: 30 Zero condition code flag */ - uint32_t N:1; /*!< bit: 31 Negative condition code flag */ - } b; /*!< Structure used for bit access */ - uint32_t w; /*!< Type used for word access */ -} APSR_Type; - + uint32_t Q : 1; /*!< bit: 27 Saturation condition flag */ + uint32_t V : 1; /*!< bit: 28 Overflow condition code flag */ + uint32_t C : 1; /*!< bit: 29 Carry condition code flag */ + uint32_t Z : 1; /*!< bit: 30 Zero condition code flag */ + uint32_t N : 1; /*!< bit: 31 Negative condition code flag */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ + } APSR_Type; -/** \brief Union type to access the Interrupt Program Status Register (IPSR). + /** \brief Union type to access the Interrupt Program Status Register (IPSR). */ -typedef union -{ - struct - { - uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */ - uint32_t _reserved0:23; /*!< bit: 9..31 Reserved */ - } b; /*!< Structure used for bit access */ - uint32_t w; /*!< Type used for word access */ -} IPSR_Type; - + typedef union + { + struct + { + uint32_t ISR : 9; /*!< bit: 0.. 8 Exception number */ + uint32_t _reserved0 : 23; /*!< bit: 9..31 Reserved */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ + } IPSR_Type; -/** \brief Union type to access the Special-Purpose Program Status Registers (xPSR). + /** \brief Union type to access the Special-Purpose Program Status Registers (xPSR). */ -typedef union -{ - struct - { - uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */ + typedef union + { + struct + { + uint32_t ISR : 9; /*!< bit: 0.. 8 Exception number */ #if (__CORTEX_M != 0x04) - uint32_t _reserved0:15; /*!< bit: 9..23 Reserved */ + uint32_t _reserved0 : 15; /*!< bit: 9..23 Reserved */ #else - uint32_t _reserved0:7; /*!< bit: 9..15 Reserved */ - uint32_t GE:4; /*!< bit: 16..19 Greater than or Equal flags */ - uint32_t _reserved1:4; /*!< bit: 20..23 Reserved */ + uint32_t _reserved0 : 7; /*!< bit: 9..15 Reserved */ + uint32_t GE : 4; /*!< bit: 16..19 Greater than or Equal flags */ + uint32_t _reserved1 : 4; /*!< bit: 20..23 Reserved */ #endif - uint32_t T:1; /*!< bit: 24 Thumb bit (read 0) */ - uint32_t IT:2; /*!< bit: 25..26 saved IT state (read 0) */ - uint32_t Q:1; /*!< bit: 27 Saturation condition flag */ - uint32_t V:1; /*!< bit: 28 Overflow condition code flag */ - uint32_t C:1; /*!< bit: 29 Carry condition code flag */ - uint32_t Z:1; /*!< bit: 30 Zero condition code flag */ - uint32_t N:1; /*!< bit: 31 Negative condition code flag */ - } b; /*!< Structure used for bit access */ - uint32_t w; /*!< Type used for word access */ -} xPSR_Type; + uint32_t T : 1; /*!< bit: 24 Thumb bit (read 0) */ + uint32_t IT : 2; /*!< bit: 25..26 saved IT state (read 0) */ + uint32_t Q : 1; /*!< bit: 27 Saturation condition flag */ + uint32_t V : 1; /*!< bit: 28 Overflow condition code flag */ + uint32_t C : 1; /*!< bit: 29 Carry condition code flag */ + uint32_t Z : 1; /*!< bit: 30 Zero condition code flag */ + uint32_t N : 1; /*!< bit: 31 Negative condition code flag */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ + } xPSR_Type; - -/** \brief Union type to access the Control Registers (CONTROL). + /** \brief Union type to access the Control Registers (CONTROL). */ -typedef union -{ - struct - { - uint32_t nPRIV:1; /*!< bit: 0 Execution privilege in Thread mode */ - uint32_t SPSEL:1; /*!< bit: 1 Stack to be used */ - uint32_t FPCA:1; /*!< bit: 2 FP extension active flag */ - uint32_t _reserved0:29; /*!< bit: 3..31 Reserved */ - } b; /*!< Structure used for bit access */ - uint32_t w; /*!< Type used for word access */ -} CONTROL_Type; - -/*@} end of group CMSIS_CORE */ + typedef union + { + struct + { + uint32_t nPRIV : 1; /*!< bit: 0 Execution privilege in Thread mode */ + uint32_t SPSEL : 1; /*!< bit: 1 Stack to be used */ + uint32_t FPCA : 1; /*!< bit: 2 FP extension active flag */ + uint32_t _reserved0 : 29; /*!< bit: 3..31 Reserved */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ + } CONTROL_Type; + /*@} end of group CMSIS_CORE */ -/** \ingroup CMSIS_core_register + /** \ingroup CMSIS_core_register \defgroup CMSIS_NVIC Nested Vectored Interrupt Controller (NVIC) \brief Type definitions for the NVIC Registers @{ */ -/** \brief Structure type to access the Nested Vectored Interrupt Controller (NVIC). + /** \brief Structure type to access the Nested Vectored Interrupt Controller (NVIC). */ -typedef struct -{ - __IO uint32_t ISER[8]; /*!< Offset: 0x000 (R/W) Interrupt Set Enable Register */ - uint32_t RESERVED0[24]; - __IO uint32_t ICER[8]; /*!< Offset: 0x080 (R/W) Interrupt Clear Enable Register */ - uint32_t RSERVED1[24]; - __IO uint32_t ISPR[8]; /*!< Offset: 0x100 (R/W) Interrupt Set Pending Register */ - uint32_t RESERVED2[24]; - __IO uint32_t ICPR[8]; /*!< Offset: 0x180 (R/W) Interrupt Clear Pending Register */ - uint32_t RESERVED3[24]; - __IO uint32_t IABR[8]; /*!< Offset: 0x200 (R/W) Interrupt Active bit Register */ - uint32_t RESERVED4[56]; - __IO uint8_t IP[240]; /*!< Offset: 0x300 (R/W) Interrupt Priority Register (8Bit wide) */ - uint32_t RESERVED5[644]; - __O uint32_t STIR; /*!< Offset: 0xE00 ( /W) Software Trigger Interrupt Register */ -} NVIC_Type; + typedef struct + { + __IO uint32_t ISER[8]; /*!< Offset: 0x000 (R/W) Interrupt Set Enable Register */ + uint32_t RESERVED0[24]; + __IO uint32_t ICER[8]; /*!< Offset: 0x080 (R/W) Interrupt Clear Enable Register */ + uint32_t RSERVED1[24]; + __IO uint32_t ISPR[8]; /*!< Offset: 0x100 (R/W) Interrupt Set Pending Register */ + uint32_t RESERVED2[24]; + __IO uint32_t ICPR[8]; /*!< Offset: 0x180 (R/W) Interrupt Clear Pending Register */ + uint32_t RESERVED3[24]; + __IO uint32_t IABR[8]; /*!< Offset: 0x200 (R/W) Interrupt Active bit Register */ + uint32_t RESERVED4[56]; + __IO uint8_t IP[240]; /*!< Offset: 0x300 (R/W) Interrupt Priority Register (8Bit wide) */ + uint32_t RESERVED5[644]; + __O uint32_t STIR; /*!< Offset: 0xE00 ( /W) Software Trigger Interrupt Register */ + } NVIC_Type; /* Software Triggered Interrupt Register Definitions */ -#define NVIC_STIR_INTID_Pos 0 /*!< STIR: INTLINESNUM Position */ -#define NVIC_STIR_INTID_Msk (0x1FFUL << NVIC_STIR_INTID_Pos) /*!< STIR: INTLINESNUM Mask */ +#define NVIC_STIR_INTID_Pos 0 /*!< STIR: INTLINESNUM Position */ +#define NVIC_STIR_INTID_Msk (0x1FFUL << NVIC_STIR_INTID_Pos) /*!< STIR: INTLINESNUM Mask */ -/*@} end of group CMSIS_NVIC */ + /*@} end of group CMSIS_NVIC */ - -/** \ingroup CMSIS_core_register + /** \ingroup CMSIS_core_register \defgroup CMSIS_SCB System Control Block (SCB) \brief Type definitions for the System Control Block Registers @{ */ -/** \brief Structure type to access the System Control Block (SCB). + /** \brief Structure type to access the System Control Block (SCB). */ -typedef struct -{ - __I uint32_t CPUID; /*!< Offset: 0x000 (R/ ) CPUID Base Register */ - __IO uint32_t ICSR; /*!< Offset: 0x004 (R/W) Interrupt Control and State Register */ - __IO uint32_t VTOR; /*!< Offset: 0x008 (R/W) Vector Table Offset Register */ - __IO uint32_t AIRCR; /*!< Offset: 0x00C (R/W) Application Interrupt and Reset Control Register */ - __IO uint32_t SCR; /*!< Offset: 0x010 (R/W) System Control Register */ - __IO uint32_t CCR; /*!< Offset: 0x014 (R/W) Configuration Control Register */ - __IO uint8_t SHP[12]; /*!< Offset: 0x018 (R/W) System Handlers Priority Registers (4-7, 8-11, 12-15) */ - __IO uint32_t SHCSR; /*!< Offset: 0x024 (R/W) System Handler Control and State Register */ - __IO uint32_t CFSR; /*!< Offset: 0x028 (R/W) Configurable Fault Status Register */ - __IO uint32_t HFSR; /*!< Offset: 0x02C (R/W) HardFault Status Register */ - __IO uint32_t DFSR; /*!< Offset: 0x030 (R/W) Debug Fault Status Register */ - __IO uint32_t MMFAR; /*!< Offset: 0x034 (R/W) MemManage Fault Address Register */ - __IO uint32_t BFAR; /*!< Offset: 0x038 (R/W) BusFault Address Register */ - __IO uint32_t AFSR; /*!< Offset: 0x03C (R/W) Auxiliary Fault Status Register */ - __I uint32_t PFR[2]; /*!< Offset: 0x040 (R/ ) Processor Feature Register */ - __I uint32_t DFR; /*!< Offset: 0x048 (R/ ) Debug Feature Register */ - __I uint32_t ADR; /*!< Offset: 0x04C (R/ ) Auxiliary Feature Register */ - __I uint32_t MMFR[4]; /*!< Offset: 0x050 (R/ ) Memory Model Feature Register */ - __I uint32_t ISAR[5]; /*!< Offset: 0x060 (R/ ) Instruction Set Attributes Register */ - uint32_t RESERVED0[5]; - __IO uint32_t CPACR; /*!< Offset: 0x088 (R/W) Coprocessor Access Control Register */ -} SCB_Type; + typedef struct + { + __I uint32_t CPUID; /*!< Offset: 0x000 (R/ ) CPUID Base Register */ + __IO uint32_t ICSR; /*!< Offset: 0x004 (R/W) Interrupt Control and State Register */ + __IO uint32_t VTOR; /*!< Offset: 0x008 (R/W) Vector Table Offset Register */ + __IO uint32_t AIRCR; /*!< Offset: 0x00C (R/W) Application Interrupt and Reset Control Register */ + __IO uint32_t SCR; /*!< Offset: 0x010 (R/W) System Control Register */ + __IO uint32_t CCR; /*!< Offset: 0x014 (R/W) Configuration Control Register */ + __IO uint8_t SHP[12]; /*!< Offset: 0x018 (R/W) System Handlers Priority Registers (4-7, 8-11, 12-15) */ + __IO uint32_t SHCSR; /*!< Offset: 0x024 (R/W) System Handler Control and State Register */ + __IO uint32_t CFSR; /*!< Offset: 0x028 (R/W) Configurable Fault Status Register */ + __IO uint32_t HFSR; /*!< Offset: 0x02C (R/W) HardFault Status Register */ + __IO uint32_t DFSR; /*!< Offset: 0x030 (R/W) Debug Fault Status Register */ + __IO uint32_t MMFAR; /*!< Offset: 0x034 (R/W) MemManage Fault Address Register */ + __IO uint32_t BFAR; /*!< Offset: 0x038 (R/W) BusFault Address Register */ + __IO uint32_t AFSR; /*!< Offset: 0x03C (R/W) Auxiliary Fault Status Register */ + __I uint32_t PFR[2]; /*!< Offset: 0x040 (R/ ) Processor Feature Register */ + __I uint32_t DFR; /*!< Offset: 0x048 (R/ ) Debug Feature Register */ + __I uint32_t ADR; /*!< Offset: 0x04C (R/ ) Auxiliary Feature Register */ + __I uint32_t MMFR[4]; /*!< Offset: 0x050 (R/ ) Memory Model Feature Register */ + __I uint32_t ISAR[5]; /*!< Offset: 0x060 (R/ ) Instruction Set Attributes Register */ + uint32_t RESERVED0[5]; + __IO uint32_t CPACR; /*!< Offset: 0x088 (R/W) Coprocessor Access Control Register */ + } SCB_Type; /* SCB CPUID Register Definitions */ -#define SCB_CPUID_IMPLEMENTER_Pos 24 /*!< SCB CPUID: IMPLEMENTER Position */ -#define SCB_CPUID_IMPLEMENTER_Msk (0xFFUL << SCB_CPUID_IMPLEMENTER_Pos) /*!< SCB CPUID: IMPLEMENTER Mask */ +#define SCB_CPUID_IMPLEMENTER_Pos 24 /*!< SCB CPUID: IMPLEMENTER Position */ +#define SCB_CPUID_IMPLEMENTER_Msk (0xFFUL << SCB_CPUID_IMPLEMENTER_Pos) /*!< SCB CPUID: IMPLEMENTER Mask */ -#define SCB_CPUID_VARIANT_Pos 20 /*!< SCB CPUID: VARIANT Position */ -#define SCB_CPUID_VARIANT_Msk (0xFUL << SCB_CPUID_VARIANT_Pos) /*!< SCB CPUID: VARIANT Mask */ +#define SCB_CPUID_VARIANT_Pos 20 /*!< SCB CPUID: VARIANT Position */ +#define SCB_CPUID_VARIANT_Msk (0xFUL << SCB_CPUID_VARIANT_Pos) /*!< SCB CPUID: VARIANT Mask */ -#define SCB_CPUID_ARCHITECTURE_Pos 16 /*!< SCB CPUID: ARCHITECTURE Position */ -#define SCB_CPUID_ARCHITECTURE_Msk (0xFUL << SCB_CPUID_ARCHITECTURE_Pos) /*!< SCB CPUID: ARCHITECTURE Mask */ +#define SCB_CPUID_ARCHITECTURE_Pos 16 /*!< SCB CPUID: ARCHITECTURE Position */ +#define SCB_CPUID_ARCHITECTURE_Msk (0xFUL << SCB_CPUID_ARCHITECTURE_Pos) /*!< SCB CPUID: ARCHITECTURE Mask */ -#define SCB_CPUID_PARTNO_Pos 4 /*!< SCB CPUID: PARTNO Position */ -#define SCB_CPUID_PARTNO_Msk (0xFFFUL << SCB_CPUID_PARTNO_Pos) /*!< SCB CPUID: PARTNO Mask */ +#define SCB_CPUID_PARTNO_Pos 4 /*!< SCB CPUID: PARTNO Position */ +#define SCB_CPUID_PARTNO_Msk (0xFFFUL << SCB_CPUID_PARTNO_Pos) /*!< SCB CPUID: PARTNO Mask */ -#define SCB_CPUID_REVISION_Pos 0 /*!< SCB CPUID: REVISION Position */ -#define SCB_CPUID_REVISION_Msk (0xFUL << SCB_CPUID_REVISION_Pos) /*!< SCB CPUID: REVISION Mask */ +#define SCB_CPUID_REVISION_Pos 0 /*!< SCB CPUID: REVISION Position */ +#define SCB_CPUID_REVISION_Msk (0xFUL << SCB_CPUID_REVISION_Pos) /*!< SCB CPUID: REVISION Mask */ /* SCB Interrupt Control State Register Definitions */ -#define SCB_ICSR_NMIPENDSET_Pos 31 /*!< SCB ICSR: NMIPENDSET Position */ -#define SCB_ICSR_NMIPENDSET_Msk (1UL << SCB_ICSR_NMIPENDSET_Pos) /*!< SCB ICSR: NMIPENDSET Mask */ +#define SCB_ICSR_NMIPENDSET_Pos 31 /*!< SCB ICSR: NMIPENDSET Position */ +#define SCB_ICSR_NMIPENDSET_Msk (1UL << SCB_ICSR_NMIPENDSET_Pos) /*!< SCB ICSR: NMIPENDSET Mask */ -#define SCB_ICSR_PENDSVSET_Pos 28 /*!< SCB ICSR: PENDSVSET Position */ -#define SCB_ICSR_PENDSVSET_Msk (1UL << SCB_ICSR_PENDSVSET_Pos) /*!< SCB ICSR: PENDSVSET Mask */ +#define SCB_ICSR_PENDSVSET_Pos 28 /*!< SCB ICSR: PENDSVSET Position */ +#define SCB_ICSR_PENDSVSET_Msk (1UL << SCB_ICSR_PENDSVSET_Pos) /*!< SCB ICSR: PENDSVSET Mask */ -#define SCB_ICSR_PENDSVCLR_Pos 27 /*!< SCB ICSR: PENDSVCLR Position */ -#define SCB_ICSR_PENDSVCLR_Msk (1UL << SCB_ICSR_PENDSVCLR_Pos) /*!< SCB ICSR: PENDSVCLR Mask */ +#define SCB_ICSR_PENDSVCLR_Pos 27 /*!< SCB ICSR: PENDSVCLR Position */ +#define SCB_ICSR_PENDSVCLR_Msk (1UL << SCB_ICSR_PENDSVCLR_Pos) /*!< SCB ICSR: PENDSVCLR Mask */ -#define SCB_ICSR_PENDSTSET_Pos 26 /*!< SCB ICSR: PENDSTSET Position */ -#define SCB_ICSR_PENDSTSET_Msk (1UL << SCB_ICSR_PENDSTSET_Pos) /*!< SCB ICSR: PENDSTSET Mask */ +#define SCB_ICSR_PENDSTSET_Pos 26 /*!< SCB ICSR: PENDSTSET Position */ +#define SCB_ICSR_PENDSTSET_Msk (1UL << SCB_ICSR_PENDSTSET_Pos) /*!< SCB ICSR: PENDSTSET Mask */ -#define SCB_ICSR_PENDSTCLR_Pos 25 /*!< SCB ICSR: PENDSTCLR Position */ -#define SCB_ICSR_PENDSTCLR_Msk (1UL << SCB_ICSR_PENDSTCLR_Pos) /*!< SCB ICSR: PENDSTCLR Mask */ +#define SCB_ICSR_PENDSTCLR_Pos 25 /*!< SCB ICSR: PENDSTCLR Position */ +#define SCB_ICSR_PENDSTCLR_Msk (1UL << SCB_ICSR_PENDSTCLR_Pos) /*!< SCB ICSR: PENDSTCLR Mask */ -#define SCB_ICSR_ISRPREEMPT_Pos 23 /*!< SCB ICSR: ISRPREEMPT Position */ -#define SCB_ICSR_ISRPREEMPT_Msk (1UL << SCB_ICSR_ISRPREEMPT_Pos) /*!< SCB ICSR: ISRPREEMPT Mask */ +#define SCB_ICSR_ISRPREEMPT_Pos 23 /*!< SCB ICSR: ISRPREEMPT Position */ +#define SCB_ICSR_ISRPREEMPT_Msk (1UL << SCB_ICSR_ISRPREEMPT_Pos) /*!< SCB ICSR: ISRPREEMPT Mask */ -#define SCB_ICSR_ISRPENDING_Pos 22 /*!< SCB ICSR: ISRPENDING Position */ -#define SCB_ICSR_ISRPENDING_Msk (1UL << SCB_ICSR_ISRPENDING_Pos) /*!< SCB ICSR: ISRPENDING Mask */ +#define SCB_ICSR_ISRPENDING_Pos 22 /*!< SCB ICSR: ISRPENDING Position */ +#define SCB_ICSR_ISRPENDING_Msk (1UL << SCB_ICSR_ISRPENDING_Pos) /*!< SCB ICSR: ISRPENDING Mask */ -#define SCB_ICSR_VECTPENDING_Pos 12 /*!< SCB ICSR: VECTPENDING Position */ -#define SCB_ICSR_VECTPENDING_Msk (0x1FFUL << SCB_ICSR_VECTPENDING_Pos) /*!< SCB ICSR: VECTPENDING Mask */ +#define SCB_ICSR_VECTPENDING_Pos 12 /*!< SCB ICSR: VECTPENDING Position */ +#define SCB_ICSR_VECTPENDING_Msk (0x1FFUL << SCB_ICSR_VECTPENDING_Pos) /*!< SCB ICSR: VECTPENDING Mask */ -#define SCB_ICSR_RETTOBASE_Pos 11 /*!< SCB ICSR: RETTOBASE Position */ -#define SCB_ICSR_RETTOBASE_Msk (1UL << SCB_ICSR_RETTOBASE_Pos) /*!< SCB ICSR: RETTOBASE Mask */ +#define SCB_ICSR_RETTOBASE_Pos 11 /*!< SCB ICSR: RETTOBASE Position */ +#define SCB_ICSR_RETTOBASE_Msk (1UL << SCB_ICSR_RETTOBASE_Pos) /*!< SCB ICSR: RETTOBASE Mask */ -#define SCB_ICSR_VECTACTIVE_Pos 0 /*!< SCB ICSR: VECTACTIVE Position */ -#define SCB_ICSR_VECTACTIVE_Msk (0x1FFUL << SCB_ICSR_VECTACTIVE_Pos) /*!< SCB ICSR: VECTACTIVE Mask */ +#define SCB_ICSR_VECTACTIVE_Pos 0 /*!< SCB ICSR: VECTACTIVE Position */ +#define SCB_ICSR_VECTACTIVE_Msk (0x1FFUL << SCB_ICSR_VECTACTIVE_Pos) /*!< SCB ICSR: VECTACTIVE Mask */ /* SCB Vector Table Offset Register Definitions */ -#if (__CM3_REV < 0x0201) /* core r2p1 */ -#define SCB_VTOR_TBLBASE_Pos 29 /*!< SCB VTOR: TBLBASE Position */ -#define SCB_VTOR_TBLBASE_Msk (1UL << SCB_VTOR_TBLBASE_Pos) /*!< SCB VTOR: TBLBASE Mask */ +#if (__CM3_REV < 0x0201) /* core r2p1 */ +#define SCB_VTOR_TBLBASE_Pos 29 /*!< SCB VTOR: TBLBASE Position */ +#define SCB_VTOR_TBLBASE_Msk (1UL << SCB_VTOR_TBLBASE_Pos) /*!< SCB VTOR: TBLBASE Mask */ -#define SCB_VTOR_TBLOFF_Pos 7 /*!< SCB VTOR: TBLOFF Position */ -#define SCB_VTOR_TBLOFF_Msk (0x3FFFFFUL << SCB_VTOR_TBLOFF_Pos) /*!< SCB VTOR: TBLOFF Mask */ +#define SCB_VTOR_TBLOFF_Pos 7 /*!< SCB VTOR: TBLOFF Position */ +#define SCB_VTOR_TBLOFF_Msk (0x3FFFFFUL << SCB_VTOR_TBLOFF_Pos) /*!< SCB VTOR: TBLOFF Mask */ #else -#define SCB_VTOR_TBLOFF_Pos 7 /*!< SCB VTOR: TBLOFF Position */ -#define SCB_VTOR_TBLOFF_Msk (0x1FFFFFFUL << SCB_VTOR_TBLOFF_Pos) /*!< SCB VTOR: TBLOFF Mask */ +#define SCB_VTOR_TBLOFF_Pos 7 /*!< SCB VTOR: TBLOFF Position */ +#define SCB_VTOR_TBLOFF_Msk (0x1FFFFFFUL << SCB_VTOR_TBLOFF_Pos) /*!< SCB VTOR: TBLOFF Mask */ #endif /* SCB Application Interrupt and Reset Control Register Definitions */ -#define SCB_AIRCR_VECTKEY_Pos 16 /*!< SCB AIRCR: VECTKEY Position */ -#define SCB_AIRCR_VECTKEY_Msk (0xFFFFUL << SCB_AIRCR_VECTKEY_Pos) /*!< SCB AIRCR: VECTKEY Mask */ +#define SCB_AIRCR_VECTKEY_Pos 16 /*!< SCB AIRCR: VECTKEY Position */ +#define SCB_AIRCR_VECTKEY_Msk (0xFFFFUL << SCB_AIRCR_VECTKEY_Pos) /*!< SCB AIRCR: VECTKEY Mask */ -#define SCB_AIRCR_VECTKEYSTAT_Pos 16 /*!< SCB AIRCR: VECTKEYSTAT Position */ -#define SCB_AIRCR_VECTKEYSTAT_Msk (0xFFFFUL << SCB_AIRCR_VECTKEYSTAT_Pos) /*!< SCB AIRCR: VECTKEYSTAT Mask */ +#define SCB_AIRCR_VECTKEYSTAT_Pos 16 /*!< SCB AIRCR: VECTKEYSTAT Position */ +#define SCB_AIRCR_VECTKEYSTAT_Msk (0xFFFFUL << SCB_AIRCR_VECTKEYSTAT_Pos) /*!< SCB AIRCR: VECTKEYSTAT Mask */ -#define SCB_AIRCR_ENDIANESS_Pos 15 /*!< SCB AIRCR: ENDIANESS Position */ -#define SCB_AIRCR_ENDIANESS_Msk (1UL << SCB_AIRCR_ENDIANESS_Pos) /*!< SCB AIRCR: ENDIANESS Mask */ +#define SCB_AIRCR_ENDIANESS_Pos 15 /*!< SCB AIRCR: ENDIANESS Position */ +#define SCB_AIRCR_ENDIANESS_Msk (1UL << SCB_AIRCR_ENDIANESS_Pos) /*!< SCB AIRCR: ENDIANESS Mask */ -#define SCB_AIRCR_PRIGROUP_Pos 8 /*!< SCB AIRCR: PRIGROUP Position */ -#define SCB_AIRCR_PRIGROUP_Msk (7UL << SCB_AIRCR_PRIGROUP_Pos) /*!< SCB AIRCR: PRIGROUP Mask */ +#define SCB_AIRCR_PRIGROUP_Pos 8 /*!< SCB AIRCR: PRIGROUP Position */ +#define SCB_AIRCR_PRIGROUP_Msk (7UL << SCB_AIRCR_PRIGROUP_Pos) /*!< SCB AIRCR: PRIGROUP Mask */ -#define SCB_AIRCR_SYSRESETREQ_Pos 2 /*!< SCB AIRCR: SYSRESETREQ Position */ -#define SCB_AIRCR_SYSRESETREQ_Msk (1UL << SCB_AIRCR_SYSRESETREQ_Pos) /*!< SCB AIRCR: SYSRESETREQ Mask */ +#define SCB_AIRCR_SYSRESETREQ_Pos 2 /*!< SCB AIRCR: SYSRESETREQ Position */ +#define SCB_AIRCR_SYSRESETREQ_Msk (1UL << SCB_AIRCR_SYSRESETREQ_Pos) /*!< SCB AIRCR: SYSRESETREQ Mask */ -#define SCB_AIRCR_VECTCLRACTIVE_Pos 1 /*!< SCB AIRCR: VECTCLRACTIVE Position */ -#define SCB_AIRCR_VECTCLRACTIVE_Msk (1UL << SCB_AIRCR_VECTCLRACTIVE_Pos) /*!< SCB AIRCR: VECTCLRACTIVE Mask */ +#define SCB_AIRCR_VECTCLRACTIVE_Pos 1 /*!< SCB AIRCR: VECTCLRACTIVE Position */ +#define SCB_AIRCR_VECTCLRACTIVE_Msk (1UL << SCB_AIRCR_VECTCLRACTIVE_Pos) /*!< SCB AIRCR: VECTCLRACTIVE Mask */ -#define SCB_AIRCR_VECTRESET_Pos 0 /*!< SCB AIRCR: VECTRESET Position */ -#define SCB_AIRCR_VECTRESET_Msk (1UL << SCB_AIRCR_VECTRESET_Pos) /*!< SCB AIRCR: VECTRESET Mask */ +#define SCB_AIRCR_VECTRESET_Pos 0 /*!< SCB AIRCR: VECTRESET Position */ +#define SCB_AIRCR_VECTRESET_Msk (1UL << SCB_AIRCR_VECTRESET_Pos) /*!< SCB AIRCR: VECTRESET Mask */ /* SCB System Control Register Definitions */ -#define SCB_SCR_SEVONPEND_Pos 4 /*!< SCB SCR: SEVONPEND Position */ -#define SCB_SCR_SEVONPEND_Msk (1UL << SCB_SCR_SEVONPEND_Pos) /*!< SCB SCR: SEVONPEND Mask */ +#define SCB_SCR_SEVONPEND_Pos 4 /*!< SCB SCR: SEVONPEND Position */ +#define SCB_SCR_SEVONPEND_Msk (1UL << SCB_SCR_SEVONPEND_Pos) /*!< SCB SCR: SEVONPEND Mask */ -#define SCB_SCR_SLEEPDEEP_Pos 2 /*!< SCB SCR: SLEEPDEEP Position */ -#define SCB_SCR_SLEEPDEEP_Msk (1UL << SCB_SCR_SLEEPDEEP_Pos) /*!< SCB SCR: SLEEPDEEP Mask */ +#define SCB_SCR_SLEEPDEEP_Pos 2 /*!< SCB SCR: SLEEPDEEP Position */ +#define SCB_SCR_SLEEPDEEP_Msk (1UL << SCB_SCR_SLEEPDEEP_Pos) /*!< SCB SCR: SLEEPDEEP Mask */ -#define SCB_SCR_SLEEPONEXIT_Pos 1 /*!< SCB SCR: SLEEPONEXIT Position */ -#define SCB_SCR_SLEEPONEXIT_Msk (1UL << SCB_SCR_SLEEPONEXIT_Pos) /*!< SCB SCR: SLEEPONEXIT Mask */ +#define SCB_SCR_SLEEPONEXIT_Pos 1 /*!< SCB SCR: SLEEPONEXIT Position */ +#define SCB_SCR_SLEEPONEXIT_Msk (1UL << SCB_SCR_SLEEPONEXIT_Pos) /*!< SCB SCR: SLEEPONEXIT Mask */ /* SCB Configuration Control Register Definitions */ -#define SCB_CCR_STKALIGN_Pos 9 /*!< SCB CCR: STKALIGN Position */ -#define SCB_CCR_STKALIGN_Msk (1UL << SCB_CCR_STKALIGN_Pos) /*!< SCB CCR: STKALIGN Mask */ +#define SCB_CCR_STKALIGN_Pos 9 /*!< SCB CCR: STKALIGN Position */ +#define SCB_CCR_STKALIGN_Msk (1UL << SCB_CCR_STKALIGN_Pos) /*!< SCB CCR: STKALIGN Mask */ -#define SCB_CCR_BFHFNMIGN_Pos 8 /*!< SCB CCR: BFHFNMIGN Position */ -#define SCB_CCR_BFHFNMIGN_Msk (1UL << SCB_CCR_BFHFNMIGN_Pos) /*!< SCB CCR: BFHFNMIGN Mask */ +#define SCB_CCR_BFHFNMIGN_Pos 8 /*!< SCB CCR: BFHFNMIGN Position */ +#define SCB_CCR_BFHFNMIGN_Msk (1UL << SCB_CCR_BFHFNMIGN_Pos) /*!< SCB CCR: BFHFNMIGN Mask */ -#define SCB_CCR_DIV_0_TRP_Pos 4 /*!< SCB CCR: DIV_0_TRP Position */ -#define SCB_CCR_DIV_0_TRP_Msk (1UL << SCB_CCR_DIV_0_TRP_Pos) /*!< SCB CCR: DIV_0_TRP Mask */ +#define SCB_CCR_DIV_0_TRP_Pos 4 /*!< SCB CCR: DIV_0_TRP Position */ +#define SCB_CCR_DIV_0_TRP_Msk (1UL << SCB_CCR_DIV_0_TRP_Pos) /*!< SCB CCR: DIV_0_TRP Mask */ -#define SCB_CCR_UNALIGN_TRP_Pos 3 /*!< SCB CCR: UNALIGN_TRP Position */ -#define SCB_CCR_UNALIGN_TRP_Msk (1UL << SCB_CCR_UNALIGN_TRP_Pos) /*!< SCB CCR: UNALIGN_TRP Mask */ +#define SCB_CCR_UNALIGN_TRP_Pos 3 /*!< SCB CCR: UNALIGN_TRP Position */ +#define SCB_CCR_UNALIGN_TRP_Msk (1UL << SCB_CCR_UNALIGN_TRP_Pos) /*!< SCB CCR: UNALIGN_TRP Mask */ -#define SCB_CCR_USERSETMPEND_Pos 1 /*!< SCB CCR: USERSETMPEND Position */ -#define SCB_CCR_USERSETMPEND_Msk (1UL << SCB_CCR_USERSETMPEND_Pos) /*!< SCB CCR: USERSETMPEND Mask */ +#define SCB_CCR_USERSETMPEND_Pos 1 /*!< SCB CCR: USERSETMPEND Position */ +#define SCB_CCR_USERSETMPEND_Msk (1UL << SCB_CCR_USERSETMPEND_Pos) /*!< SCB CCR: USERSETMPEND Mask */ -#define SCB_CCR_NONBASETHRDENA_Pos 0 /*!< SCB CCR: NONBASETHRDENA Position */ -#define SCB_CCR_NONBASETHRDENA_Msk (1UL << SCB_CCR_NONBASETHRDENA_Pos) /*!< SCB CCR: NONBASETHRDENA Mask */ +#define SCB_CCR_NONBASETHRDENA_Pos 0 /*!< SCB CCR: NONBASETHRDENA Position */ +#define SCB_CCR_NONBASETHRDENA_Msk (1UL << SCB_CCR_NONBASETHRDENA_Pos) /*!< SCB CCR: NONBASETHRDENA Mask */ /* SCB System Handler Control and State Register Definitions */ -#define SCB_SHCSR_USGFAULTENA_Pos 18 /*!< SCB SHCSR: USGFAULTENA Position */ -#define SCB_SHCSR_USGFAULTENA_Msk (1UL << SCB_SHCSR_USGFAULTENA_Pos) /*!< SCB SHCSR: USGFAULTENA Mask */ +#define SCB_SHCSR_USGFAULTENA_Pos 18 /*!< SCB SHCSR: USGFAULTENA Position */ +#define SCB_SHCSR_USGFAULTENA_Msk (1UL << SCB_SHCSR_USGFAULTENA_Pos) /*!< SCB SHCSR: USGFAULTENA Mask */ -#define SCB_SHCSR_BUSFAULTENA_Pos 17 /*!< SCB SHCSR: BUSFAULTENA Position */ -#define SCB_SHCSR_BUSFAULTENA_Msk (1UL << SCB_SHCSR_BUSFAULTENA_Pos) /*!< SCB SHCSR: BUSFAULTENA Mask */ +#define SCB_SHCSR_BUSFAULTENA_Pos 17 /*!< SCB SHCSR: BUSFAULTENA Position */ +#define SCB_SHCSR_BUSFAULTENA_Msk (1UL << SCB_SHCSR_BUSFAULTENA_Pos) /*!< SCB SHCSR: BUSFAULTENA Mask */ -#define SCB_SHCSR_MEMFAULTENA_Pos 16 /*!< SCB SHCSR: MEMFAULTENA Position */ -#define SCB_SHCSR_MEMFAULTENA_Msk (1UL << SCB_SHCSR_MEMFAULTENA_Pos) /*!< SCB SHCSR: MEMFAULTENA Mask */ +#define SCB_SHCSR_MEMFAULTENA_Pos 16 /*!< SCB SHCSR: MEMFAULTENA Position */ +#define SCB_SHCSR_MEMFAULTENA_Msk (1UL << SCB_SHCSR_MEMFAULTENA_Pos) /*!< SCB SHCSR: MEMFAULTENA Mask */ -#define SCB_SHCSR_SVCALLPENDED_Pos 15 /*!< SCB SHCSR: SVCALLPENDED Position */ -#define SCB_SHCSR_SVCALLPENDED_Msk (1UL << SCB_SHCSR_SVCALLPENDED_Pos) /*!< SCB SHCSR: SVCALLPENDED Mask */ +#define SCB_SHCSR_SVCALLPENDED_Pos 15 /*!< SCB SHCSR: SVCALLPENDED Position */ +#define SCB_SHCSR_SVCALLPENDED_Msk (1UL << SCB_SHCSR_SVCALLPENDED_Pos) /*!< SCB SHCSR: SVCALLPENDED Mask */ -#define SCB_SHCSR_BUSFAULTPENDED_Pos 14 /*!< SCB SHCSR: BUSFAULTPENDED Position */ -#define SCB_SHCSR_BUSFAULTPENDED_Msk (1UL << SCB_SHCSR_BUSFAULTPENDED_Pos) /*!< SCB SHCSR: BUSFAULTPENDED Mask */ +#define SCB_SHCSR_BUSFAULTPENDED_Pos 14 /*!< SCB SHCSR: BUSFAULTPENDED Position */ +#define SCB_SHCSR_BUSFAULTPENDED_Msk (1UL << SCB_SHCSR_BUSFAULTPENDED_Pos) /*!< SCB SHCSR: BUSFAULTPENDED Mask */ -#define SCB_SHCSR_MEMFAULTPENDED_Pos 13 /*!< SCB SHCSR: MEMFAULTPENDED Position */ -#define SCB_SHCSR_MEMFAULTPENDED_Msk (1UL << SCB_SHCSR_MEMFAULTPENDED_Pos) /*!< SCB SHCSR: MEMFAULTPENDED Mask */ +#define SCB_SHCSR_MEMFAULTPENDED_Pos 13 /*!< SCB SHCSR: MEMFAULTPENDED Position */ +#define SCB_SHCSR_MEMFAULTPENDED_Msk (1UL << SCB_SHCSR_MEMFAULTPENDED_Pos) /*!< SCB SHCSR: MEMFAULTPENDED Mask */ -#define SCB_SHCSR_USGFAULTPENDED_Pos 12 /*!< SCB SHCSR: USGFAULTPENDED Position */ -#define SCB_SHCSR_USGFAULTPENDED_Msk (1UL << SCB_SHCSR_USGFAULTPENDED_Pos) /*!< SCB SHCSR: USGFAULTPENDED Mask */ +#define SCB_SHCSR_USGFAULTPENDED_Pos 12 /*!< SCB SHCSR: USGFAULTPENDED Position */ +#define SCB_SHCSR_USGFAULTPENDED_Msk (1UL << SCB_SHCSR_USGFAULTPENDED_Pos) /*!< SCB SHCSR: USGFAULTPENDED Mask */ -#define SCB_SHCSR_SYSTICKACT_Pos 11 /*!< SCB SHCSR: SYSTICKACT Position */ -#define SCB_SHCSR_SYSTICKACT_Msk (1UL << SCB_SHCSR_SYSTICKACT_Pos) /*!< SCB SHCSR: SYSTICKACT Mask */ +#define SCB_SHCSR_SYSTICKACT_Pos 11 /*!< SCB SHCSR: SYSTICKACT Position */ +#define SCB_SHCSR_SYSTICKACT_Msk (1UL << SCB_SHCSR_SYSTICKACT_Pos) /*!< SCB SHCSR: SYSTICKACT Mask */ -#define SCB_SHCSR_PENDSVACT_Pos 10 /*!< SCB SHCSR: PENDSVACT Position */ -#define SCB_SHCSR_PENDSVACT_Msk (1UL << SCB_SHCSR_PENDSVACT_Pos) /*!< SCB SHCSR: PENDSVACT Mask */ +#define SCB_SHCSR_PENDSVACT_Pos 10 /*!< SCB SHCSR: PENDSVACT Position */ +#define SCB_SHCSR_PENDSVACT_Msk (1UL << SCB_SHCSR_PENDSVACT_Pos) /*!< SCB SHCSR: PENDSVACT Mask */ -#define SCB_SHCSR_MONITORACT_Pos 8 /*!< SCB SHCSR: MONITORACT Position */ -#define SCB_SHCSR_MONITORACT_Msk (1UL << SCB_SHCSR_MONITORACT_Pos) /*!< SCB SHCSR: MONITORACT Mask */ +#define SCB_SHCSR_MONITORACT_Pos 8 /*!< SCB SHCSR: MONITORACT Position */ +#define SCB_SHCSR_MONITORACT_Msk (1UL << SCB_SHCSR_MONITORACT_Pos) /*!< SCB SHCSR: MONITORACT Mask */ -#define SCB_SHCSR_SVCALLACT_Pos 7 /*!< SCB SHCSR: SVCALLACT Position */ -#define SCB_SHCSR_SVCALLACT_Msk (1UL << SCB_SHCSR_SVCALLACT_Pos) /*!< SCB SHCSR: SVCALLACT Mask */ +#define SCB_SHCSR_SVCALLACT_Pos 7 /*!< SCB SHCSR: SVCALLACT Position */ +#define SCB_SHCSR_SVCALLACT_Msk (1UL << SCB_SHCSR_SVCALLACT_Pos) /*!< SCB SHCSR: SVCALLACT Mask */ -#define SCB_SHCSR_USGFAULTACT_Pos 3 /*!< SCB SHCSR: USGFAULTACT Position */ -#define SCB_SHCSR_USGFAULTACT_Msk (1UL << SCB_SHCSR_USGFAULTACT_Pos) /*!< SCB SHCSR: USGFAULTACT Mask */ +#define SCB_SHCSR_USGFAULTACT_Pos 3 /*!< SCB SHCSR: USGFAULTACT Position */ +#define SCB_SHCSR_USGFAULTACT_Msk (1UL << SCB_SHCSR_USGFAULTACT_Pos) /*!< SCB SHCSR: USGFAULTACT Mask */ -#define SCB_SHCSR_BUSFAULTACT_Pos 1 /*!< SCB SHCSR: BUSFAULTACT Position */ -#define SCB_SHCSR_BUSFAULTACT_Msk (1UL << SCB_SHCSR_BUSFAULTACT_Pos) /*!< SCB SHCSR: BUSFAULTACT Mask */ +#define SCB_SHCSR_BUSFAULTACT_Pos 1 /*!< SCB SHCSR: BUSFAULTACT Position */ +#define SCB_SHCSR_BUSFAULTACT_Msk (1UL << SCB_SHCSR_BUSFAULTACT_Pos) /*!< SCB SHCSR: BUSFAULTACT Mask */ -#define SCB_SHCSR_MEMFAULTACT_Pos 0 /*!< SCB SHCSR: MEMFAULTACT Position */ -#define SCB_SHCSR_MEMFAULTACT_Msk (1UL << SCB_SHCSR_MEMFAULTACT_Pos) /*!< SCB SHCSR: MEMFAULTACT Mask */ +#define SCB_SHCSR_MEMFAULTACT_Pos 0 /*!< SCB SHCSR: MEMFAULTACT Position */ +#define SCB_SHCSR_MEMFAULTACT_Msk (1UL << SCB_SHCSR_MEMFAULTACT_Pos) /*!< SCB SHCSR: MEMFAULTACT Mask */ /* SCB Configurable Fault Status Registers Definitions */ -#define SCB_CFSR_USGFAULTSR_Pos 16 /*!< SCB CFSR: Usage Fault Status Register Position */ -#define SCB_CFSR_USGFAULTSR_Msk (0xFFFFUL << SCB_CFSR_USGFAULTSR_Pos) /*!< SCB CFSR: Usage Fault Status Register Mask */ +#define SCB_CFSR_USGFAULTSR_Pos 16 /*!< SCB CFSR: Usage Fault Status Register Position */ +#define SCB_CFSR_USGFAULTSR_Msk (0xFFFFUL << SCB_CFSR_USGFAULTSR_Pos) /*!< SCB CFSR: Usage Fault Status Register Mask */ -#define SCB_CFSR_BUSFAULTSR_Pos 8 /*!< SCB CFSR: Bus Fault Status Register Position */ -#define SCB_CFSR_BUSFAULTSR_Msk (0xFFUL << SCB_CFSR_BUSFAULTSR_Pos) /*!< SCB CFSR: Bus Fault Status Register Mask */ +#define SCB_CFSR_BUSFAULTSR_Pos 8 /*!< SCB CFSR: Bus Fault Status Register Position */ +#define SCB_CFSR_BUSFAULTSR_Msk (0xFFUL << SCB_CFSR_BUSFAULTSR_Pos) /*!< SCB CFSR: Bus Fault Status Register Mask */ -#define SCB_CFSR_MEMFAULTSR_Pos 0 /*!< SCB CFSR: Memory Manage Fault Status Register Position */ -#define SCB_CFSR_MEMFAULTSR_Msk (0xFFUL << SCB_CFSR_MEMFAULTSR_Pos) /*!< SCB CFSR: Memory Manage Fault Status Register Mask */ +#define SCB_CFSR_MEMFAULTSR_Pos 0 /*!< SCB CFSR: Memory Manage Fault Status Register Position */ +#define SCB_CFSR_MEMFAULTSR_Msk (0xFFUL << SCB_CFSR_MEMFAULTSR_Pos) /*!< SCB CFSR: Memory Manage Fault Status Register Mask */ /* SCB Hard Fault Status Registers Definitions */ -#define SCB_HFSR_DEBUGEVT_Pos 31 /*!< SCB HFSR: DEBUGEVT Position */ -#define SCB_HFSR_DEBUGEVT_Msk (1UL << SCB_HFSR_DEBUGEVT_Pos) /*!< SCB HFSR: DEBUGEVT Mask */ +#define SCB_HFSR_DEBUGEVT_Pos 31 /*!< SCB HFSR: DEBUGEVT Position */ +#define SCB_HFSR_DEBUGEVT_Msk (1UL << SCB_HFSR_DEBUGEVT_Pos) /*!< SCB HFSR: DEBUGEVT Mask */ -#define SCB_HFSR_FORCED_Pos 30 /*!< SCB HFSR: FORCED Position */ -#define SCB_HFSR_FORCED_Msk (1UL << SCB_HFSR_FORCED_Pos) /*!< SCB HFSR: FORCED Mask */ +#define SCB_HFSR_FORCED_Pos 30 /*!< SCB HFSR: FORCED Position */ +#define SCB_HFSR_FORCED_Msk (1UL << SCB_HFSR_FORCED_Pos) /*!< SCB HFSR: FORCED Mask */ -#define SCB_HFSR_VECTTBL_Pos 1 /*!< SCB HFSR: VECTTBL Position */ -#define SCB_HFSR_VECTTBL_Msk (1UL << SCB_HFSR_VECTTBL_Pos) /*!< SCB HFSR: VECTTBL Mask */ +#define SCB_HFSR_VECTTBL_Pos 1 /*!< SCB HFSR: VECTTBL Position */ +#define SCB_HFSR_VECTTBL_Msk (1UL << SCB_HFSR_VECTTBL_Pos) /*!< SCB HFSR: VECTTBL Mask */ /* SCB Debug Fault Status Register Definitions */ -#define SCB_DFSR_EXTERNAL_Pos 4 /*!< SCB DFSR: EXTERNAL Position */ -#define SCB_DFSR_EXTERNAL_Msk (1UL << SCB_DFSR_EXTERNAL_Pos) /*!< SCB DFSR: EXTERNAL Mask */ +#define SCB_DFSR_EXTERNAL_Pos 4 /*!< SCB DFSR: EXTERNAL Position */ +#define SCB_DFSR_EXTERNAL_Msk (1UL << SCB_DFSR_EXTERNAL_Pos) /*!< SCB DFSR: EXTERNAL Mask */ -#define SCB_DFSR_VCATCH_Pos 3 /*!< SCB DFSR: VCATCH Position */ -#define SCB_DFSR_VCATCH_Msk (1UL << SCB_DFSR_VCATCH_Pos) /*!< SCB DFSR: VCATCH Mask */ +#define SCB_DFSR_VCATCH_Pos 3 /*!< SCB DFSR: VCATCH Position */ +#define SCB_DFSR_VCATCH_Msk (1UL << SCB_DFSR_VCATCH_Pos) /*!< SCB DFSR: VCATCH Mask */ -#define SCB_DFSR_DWTTRAP_Pos 2 /*!< SCB DFSR: DWTTRAP Position */ -#define SCB_DFSR_DWTTRAP_Msk (1UL << SCB_DFSR_DWTTRAP_Pos) /*!< SCB DFSR: DWTTRAP Mask */ +#define SCB_DFSR_DWTTRAP_Pos 2 /*!< SCB DFSR: DWTTRAP Position */ +#define SCB_DFSR_DWTTRAP_Msk (1UL << SCB_DFSR_DWTTRAP_Pos) /*!< SCB DFSR: DWTTRAP Mask */ -#define SCB_DFSR_BKPT_Pos 1 /*!< SCB DFSR: BKPT Position */ -#define SCB_DFSR_BKPT_Msk (1UL << SCB_DFSR_BKPT_Pos) /*!< SCB DFSR: BKPT Mask */ +#define SCB_DFSR_BKPT_Pos 1 /*!< SCB DFSR: BKPT Position */ +#define SCB_DFSR_BKPT_Msk (1UL << SCB_DFSR_BKPT_Pos) /*!< SCB DFSR: BKPT Mask */ -#define SCB_DFSR_HALTED_Pos 0 /*!< SCB DFSR: HALTED Position */ -#define SCB_DFSR_HALTED_Msk (1UL << SCB_DFSR_HALTED_Pos) /*!< SCB DFSR: HALTED Mask */ +#define SCB_DFSR_HALTED_Pos 0 /*!< SCB DFSR: HALTED Position */ +#define SCB_DFSR_HALTED_Msk (1UL << SCB_DFSR_HALTED_Pos) /*!< SCB DFSR: HALTED Mask */ -/*@} end of group CMSIS_SCB */ + /*@} end of group CMSIS_SCB */ - -/** \ingroup CMSIS_core_register + /** \ingroup CMSIS_core_register \defgroup CMSIS_SCnSCB System Controls not in SCB (SCnSCB) \brief Type definitions for the System Control and ID Register not in the SCB @{ */ -/** \brief Structure type to access the System Control and ID Register not in the SCB. + /** \brief Structure type to access the System Control and ID Register not in the SCB. */ -typedef struct -{ - uint32_t RESERVED0[1]; - __I uint32_t ICTR; /*!< Offset: 0x004 (R/ ) Interrupt Controller Type Register */ + typedef struct + { + uint32_t RESERVED0[1]; + __I uint32_t ICTR; /*!< Offset: 0x004 (R/ ) Interrupt Controller Type Register */ #if ((defined __CM3_REV) && (__CM3_REV >= 0x200)) - __IO uint32_t ACTLR; /*!< Offset: 0x008 (R/W) Auxiliary Control Register */ + __IO uint32_t ACTLR; /*!< Offset: 0x008 (R/W) Auxiliary Control Register */ #else - uint32_t RESERVED1[1]; + uint32_t RESERVED1[1]; #endif -} SCnSCB_Type; + } SCnSCB_Type; /* Interrupt Controller Type Register Definitions */ -#define SCnSCB_ICTR_INTLINESNUM_Pos 0 /*!< ICTR: INTLINESNUM Position */ -#define SCnSCB_ICTR_INTLINESNUM_Msk (0xFUL << SCnSCB_ICTR_INTLINESNUM_Pos) /*!< ICTR: INTLINESNUM Mask */ - -/* Auxiliary Control Register Definitions */ +#define SCnSCB_ICTR_INTLINESNUM_Pos 0 /*!< ICTR: INTLINESNUM Position */ +#define SCnSCB_ICTR_INTLINESNUM_Msk (0xFUL << SCnSCB_ICTR_INTLINESNUM_Pos) /*!< ICTR: INTLINESNUM Mask */ -#define SCnSCB_ACTLR_DISFOLD_Pos 2 /*!< ACTLR: DISFOLD Position */ -#define SCnSCB_ACTLR_DISFOLD_Msk (1UL << SCnSCB_ACTLR_DISFOLD_Pos) /*!< ACTLR: DISFOLD Mask */ + /* Auxiliary Control Register Definitions */ -#define SCnSCB_ACTLR_DISDEFWBUF_Pos 1 /*!< ACTLR: DISDEFWBUF Position */ -#define SCnSCB_ACTLR_DISDEFWBUF_Msk (1UL << SCnSCB_ACTLR_DISDEFWBUF_Pos) /*!< ACTLR: DISDEFWBUF Mask */ +#define SCnSCB_ACTLR_DISFOLD_Pos 2 /*!< ACTLR: DISFOLD Position */ +#define SCnSCB_ACTLR_DISFOLD_Msk (1UL << SCnSCB_ACTLR_DISFOLD_Pos) /*!< ACTLR: DISFOLD Mask */ -#define SCnSCB_ACTLR_DISMCYCINT_Pos 0 /*!< ACTLR: DISMCYCINT Position */ -#define SCnSCB_ACTLR_DISMCYCINT_Msk (1UL << SCnSCB_ACTLR_DISMCYCINT_Pos) /*!< ACTLR: DISMCYCINT Mask */ +#define SCnSCB_ACTLR_DISDEFWBUF_Pos 1 /*!< ACTLR: DISDEFWBUF Position */ +#define SCnSCB_ACTLR_DISDEFWBUF_Msk (1UL << SCnSCB_ACTLR_DISDEFWBUF_Pos) /*!< ACTLR: DISDEFWBUF Mask */ -/*@} end of group CMSIS_SCnotSCB */ +#define SCnSCB_ACTLR_DISMCYCINT_Pos 0 /*!< ACTLR: DISMCYCINT Position */ +#define SCnSCB_ACTLR_DISMCYCINT_Msk (1UL << SCnSCB_ACTLR_DISMCYCINT_Pos) /*!< ACTLR: DISMCYCINT Mask */ + /*@} end of group CMSIS_SCnotSCB */ -/** \ingroup CMSIS_core_register + /** \ingroup CMSIS_core_register \defgroup CMSIS_SysTick System Tick Timer (SysTick) \brief Type definitions for the System Timer Registers. @{ */ -/** \brief Structure type to access the System Timer (SysTick). + /** \brief Structure type to access the System Timer (SysTick). */ -typedef struct -{ - __IO uint32_t CTRL; /*!< Offset: 0x000 (R/W) SysTick Control and Status Register */ - __IO uint32_t LOAD; /*!< Offset: 0x004 (R/W) SysTick Reload Value Register */ - __IO uint32_t VAL; /*!< Offset: 0x008 (R/W) SysTick Current Value Register */ - __I uint32_t CALIB; /*!< Offset: 0x00C (R/ ) SysTick Calibration Register */ -} SysTick_Type; + typedef struct + { + __IO uint32_t CTRL; /*!< Offset: 0x000 (R/W) SysTick Control and Status Register */ + __IO uint32_t LOAD; /*!< Offset: 0x004 (R/W) SysTick Reload Value Register */ + __IO uint32_t VAL; /*!< Offset: 0x008 (R/W) SysTick Current Value Register */ + __I uint32_t CALIB; /*!< Offset: 0x00C (R/ ) SysTick Calibration Register */ + } SysTick_Type; /* SysTick Control / Status Register Definitions */ -#define SysTick_CTRL_COUNTFLAG_Pos 16 /*!< SysTick CTRL: COUNTFLAG Position */ -#define SysTick_CTRL_COUNTFLAG_Msk (1UL << SysTick_CTRL_COUNTFLAG_Pos) /*!< SysTick CTRL: COUNTFLAG Mask */ +#define SysTick_CTRL_COUNTFLAG_Pos 16 /*!< SysTick CTRL: COUNTFLAG Position */ +#define SysTick_CTRL_COUNTFLAG_Msk (1UL << SysTick_CTRL_COUNTFLAG_Pos) /*!< SysTick CTRL: COUNTFLAG Mask */ -#define SysTick_CTRL_CLKSOURCE_Pos 2 /*!< SysTick CTRL: CLKSOURCE Position */ -#define SysTick_CTRL_CLKSOURCE_Msk (1UL << SysTick_CTRL_CLKSOURCE_Pos) /*!< SysTick CTRL: CLKSOURCE Mask */ +#define SysTick_CTRL_CLKSOURCE_Pos 2 /*!< SysTick CTRL: CLKSOURCE Position */ +#define SysTick_CTRL_CLKSOURCE_Msk (1UL << SysTick_CTRL_CLKSOURCE_Pos) /*!< SysTick CTRL: CLKSOURCE Mask */ -#define SysTick_CTRL_TICKINT_Pos 1 /*!< SysTick CTRL: TICKINT Position */ -#define SysTick_CTRL_TICKINT_Msk (1UL << SysTick_CTRL_TICKINT_Pos) /*!< SysTick CTRL: TICKINT Mask */ +#define SysTick_CTRL_TICKINT_Pos 1 /*!< SysTick CTRL: TICKINT Position */ +#define SysTick_CTRL_TICKINT_Msk (1UL << SysTick_CTRL_TICKINT_Pos) /*!< SysTick CTRL: TICKINT Mask */ -#define SysTick_CTRL_ENABLE_Pos 0 /*!< SysTick CTRL: ENABLE Position */ -#define SysTick_CTRL_ENABLE_Msk (1UL << SysTick_CTRL_ENABLE_Pos) /*!< SysTick CTRL: ENABLE Mask */ +#define SysTick_CTRL_ENABLE_Pos 0 /*!< SysTick CTRL: ENABLE Position */ +#define SysTick_CTRL_ENABLE_Msk (1UL << SysTick_CTRL_ENABLE_Pos) /*!< SysTick CTRL: ENABLE Mask */ /* SysTick Reload Register Definitions */ -#define SysTick_LOAD_RELOAD_Pos 0 /*!< SysTick LOAD: RELOAD Position */ -#define SysTick_LOAD_RELOAD_Msk (0xFFFFFFUL << SysTick_LOAD_RELOAD_Pos) /*!< SysTick LOAD: RELOAD Mask */ +#define SysTick_LOAD_RELOAD_Pos 0 /*!< SysTick LOAD: RELOAD Position */ +#define SysTick_LOAD_RELOAD_Msk (0xFFFFFFUL << SysTick_LOAD_RELOAD_Pos) /*!< SysTick LOAD: RELOAD Mask */ /* SysTick Current Register Definitions */ -#define SysTick_VAL_CURRENT_Pos 0 /*!< SysTick VAL: CURRENT Position */ -#define SysTick_VAL_CURRENT_Msk (0xFFFFFFUL << SysTick_VAL_CURRENT_Pos) /*!< SysTick VAL: CURRENT Mask */ +#define SysTick_VAL_CURRENT_Pos 0 /*!< SysTick VAL: CURRENT Position */ +#define SysTick_VAL_CURRENT_Msk (0xFFFFFFUL << SysTick_VAL_CURRENT_Pos) /*!< SysTick VAL: CURRENT Mask */ /* SysTick Calibration Register Definitions */ -#define SysTick_CALIB_NOREF_Pos 31 /*!< SysTick CALIB: NOREF Position */ -#define SysTick_CALIB_NOREF_Msk (1UL << SysTick_CALIB_NOREF_Pos) /*!< SysTick CALIB: NOREF Mask */ - -#define SysTick_CALIB_SKEW_Pos 30 /*!< SysTick CALIB: SKEW Position */ -#define SysTick_CALIB_SKEW_Msk (1UL << SysTick_CALIB_SKEW_Pos) /*!< SysTick CALIB: SKEW Mask */ +#define SysTick_CALIB_NOREF_Pos 31 /*!< SysTick CALIB: NOREF Position */ +#define SysTick_CALIB_NOREF_Msk (1UL << SysTick_CALIB_NOREF_Pos) /*!< SysTick CALIB: NOREF Mask */ -#define SysTick_CALIB_TENMS_Pos 0 /*!< SysTick CALIB: TENMS Position */ -#define SysTick_CALIB_TENMS_Msk (0xFFFFFFUL << SysTick_CALIB_TENMS_Pos) /*!< SysTick CALIB: TENMS Mask */ +#define SysTick_CALIB_SKEW_Pos 30 /*!< SysTick CALIB: SKEW Position */ +#define SysTick_CALIB_SKEW_Msk (1UL << SysTick_CALIB_SKEW_Pos) /*!< SysTick CALIB: SKEW Mask */ -/*@} end of group CMSIS_SysTick */ +#define SysTick_CALIB_TENMS_Pos 0 /*!< SysTick CALIB: TENMS Position */ +#define SysTick_CALIB_TENMS_Msk (0xFFFFFFUL << SysTick_CALIB_TENMS_Pos) /*!< SysTick CALIB: TENMS Mask */ + /*@} end of group CMSIS_SysTick */ -/** \ingroup CMSIS_core_register + /** \ingroup CMSIS_core_register \defgroup CMSIS_ITM Instrumentation Trace Macrocell (ITM) \brief Type definitions for the Instrumentation Trace Macrocell (ITM) @{ */ -/** \brief Structure type to access the Instrumentation Trace Macrocell Register (ITM). + /** \brief Structure type to access the Instrumentation Trace Macrocell Register (ITM). */ -typedef struct -{ - __O union - { - __O uint8_t u8; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 8-bit */ - __O uint16_t u16; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 16-bit */ - __O uint32_t u32; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 32-bit */ - } PORT [32]; /*!< Offset: 0x000 ( /W) ITM Stimulus Port Registers */ - uint32_t RESERVED0[864]; - __IO uint32_t TER; /*!< Offset: 0xE00 (R/W) ITM Trace Enable Register */ - uint32_t RESERVED1[15]; - __IO uint32_t TPR; /*!< Offset: 0xE40 (R/W) ITM Trace Privilege Register */ - uint32_t RESERVED2[15]; - __IO uint32_t TCR; /*!< Offset: 0xE80 (R/W) ITM Trace Control Register */ - uint32_t RESERVED3[29]; - __O uint32_t IWR; /*!< Offset: 0xEF8 ( /W) ITM Integration Write Register */ - __I uint32_t IRR; /*!< Offset: 0xEFC (R/ ) ITM Integration Read Register */ - __IO uint32_t IMCR; /*!< Offset: 0xF00 (R/W) ITM Integration Mode Control Register */ - uint32_t RESERVED4[43]; - __O uint32_t LAR; /*!< Offset: 0xFB0 ( /W) ITM Lock Access Register */ - __I uint32_t LSR; /*!< Offset: 0xFB4 (R/ ) ITM Lock Status Register */ - uint32_t RESERVED5[6]; - __I uint32_t PID4; /*!< Offset: 0xFD0 (R/ ) ITM Peripheral Identification Register #4 */ - __I uint32_t PID5; /*!< Offset: 0xFD4 (R/ ) ITM Peripheral Identification Register #5 */ - __I uint32_t PID6; /*!< Offset: 0xFD8 (R/ ) ITM Peripheral Identification Register #6 */ - __I uint32_t PID7; /*!< Offset: 0xFDC (R/ ) ITM Peripheral Identification Register #7 */ - __I uint32_t PID0; /*!< Offset: 0xFE0 (R/ ) ITM Peripheral Identification Register #0 */ - __I uint32_t PID1; /*!< Offset: 0xFE4 (R/ ) ITM Peripheral Identification Register #1 */ - __I uint32_t PID2; /*!< Offset: 0xFE8 (R/ ) ITM Peripheral Identification Register #2 */ - __I uint32_t PID3; /*!< Offset: 0xFEC (R/ ) ITM Peripheral Identification Register #3 */ - __I uint32_t CID0; /*!< Offset: 0xFF0 (R/ ) ITM Component Identification Register #0 */ - __I uint32_t CID1; /*!< Offset: 0xFF4 (R/ ) ITM Component Identification Register #1 */ - __I uint32_t CID2; /*!< Offset: 0xFF8 (R/ ) ITM Component Identification Register #2 */ - __I uint32_t CID3; /*!< Offset: 0xFFC (R/ ) ITM Component Identification Register #3 */ -} ITM_Type; + typedef struct + { + __O union + { + __O uint8_t u8; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 8-bit */ + __O uint16_t u16; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 16-bit */ + __O uint32_t u32; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 32-bit */ + } PORT[32]; /*!< Offset: 0x000 ( /W) ITM Stimulus Port Registers */ + uint32_t RESERVED0[864]; + __IO uint32_t TER; /*!< Offset: 0xE00 (R/W) ITM Trace Enable Register */ + uint32_t RESERVED1[15]; + __IO uint32_t TPR; /*!< Offset: 0xE40 (R/W) ITM Trace Privilege Register */ + uint32_t RESERVED2[15]; + __IO uint32_t TCR; /*!< Offset: 0xE80 (R/W) ITM Trace Control Register */ + uint32_t RESERVED3[29]; + __O uint32_t IWR; /*!< Offset: 0xEF8 ( /W) ITM Integration Write Register */ + __I uint32_t IRR; /*!< Offset: 0xEFC (R/ ) ITM Integration Read Register */ + __IO uint32_t IMCR; /*!< Offset: 0xF00 (R/W) ITM Integration Mode Control Register */ + uint32_t RESERVED4[43]; + __O uint32_t LAR; /*!< Offset: 0xFB0 ( /W) ITM Lock Access Register */ + __I uint32_t LSR; /*!< Offset: 0xFB4 (R/ ) ITM Lock Status Register */ + uint32_t RESERVED5[6]; + __I uint32_t PID4; /*!< Offset: 0xFD0 (R/ ) ITM Peripheral Identification Register #4 */ + __I uint32_t PID5; /*!< Offset: 0xFD4 (R/ ) ITM Peripheral Identification Register #5 */ + __I uint32_t PID6; /*!< Offset: 0xFD8 (R/ ) ITM Peripheral Identification Register #6 */ + __I uint32_t PID7; /*!< Offset: 0xFDC (R/ ) ITM Peripheral Identification Register #7 */ + __I uint32_t PID0; /*!< Offset: 0xFE0 (R/ ) ITM Peripheral Identification Register #0 */ + __I uint32_t PID1; /*!< Offset: 0xFE4 (R/ ) ITM Peripheral Identification Register #1 */ + __I uint32_t PID2; /*!< Offset: 0xFE8 (R/ ) ITM Peripheral Identification Register #2 */ + __I uint32_t PID3; /*!< Offset: 0xFEC (R/ ) ITM Peripheral Identification Register #3 */ + __I uint32_t CID0; /*!< Offset: 0xFF0 (R/ ) ITM Component Identification Register #0 */ + __I uint32_t CID1; /*!< Offset: 0xFF4 (R/ ) ITM Component Identification Register #1 */ + __I uint32_t CID2; /*!< Offset: 0xFF8 (R/ ) ITM Component Identification Register #2 */ + __I uint32_t CID3; /*!< Offset: 0xFFC (R/ ) ITM Component Identification Register #3 */ + } ITM_Type; /* ITM Trace Privilege Register Definitions */ -#define ITM_TPR_PRIVMASK_Pos 0 /*!< ITM TPR: PRIVMASK Position */ -#define ITM_TPR_PRIVMASK_Msk (0xFUL << ITM_TPR_PRIVMASK_Pos) /*!< ITM TPR: PRIVMASK Mask */ +#define ITM_TPR_PRIVMASK_Pos 0 /*!< ITM TPR: PRIVMASK Position */ +#define ITM_TPR_PRIVMASK_Msk (0xFUL << ITM_TPR_PRIVMASK_Pos) /*!< ITM TPR: PRIVMASK Mask */ /* ITM Trace Control Register Definitions */ -#define ITM_TCR_BUSY_Pos 23 /*!< ITM TCR: BUSY Position */ -#define ITM_TCR_BUSY_Msk (1UL << ITM_TCR_BUSY_Pos) /*!< ITM TCR: BUSY Mask */ +#define ITM_TCR_BUSY_Pos 23 /*!< ITM TCR: BUSY Position */ +#define ITM_TCR_BUSY_Msk (1UL << ITM_TCR_BUSY_Pos) /*!< ITM TCR: BUSY Mask */ -#define ITM_TCR_TraceBusID_Pos 16 /*!< ITM TCR: ATBID Position */ -#define ITM_TCR_TraceBusID_Msk (0x7FUL << ITM_TCR_TraceBusID_Pos) /*!< ITM TCR: ATBID Mask */ +#define ITM_TCR_TraceBusID_Pos 16 /*!< ITM TCR: ATBID Position */ +#define ITM_TCR_TraceBusID_Msk (0x7FUL << ITM_TCR_TraceBusID_Pos) /*!< ITM TCR: ATBID Mask */ -#define ITM_TCR_GTSFREQ_Pos 10 /*!< ITM TCR: Global timestamp frequency Position */ -#define ITM_TCR_GTSFREQ_Msk (3UL << ITM_TCR_GTSFREQ_Pos) /*!< ITM TCR: Global timestamp frequency Mask */ +#define ITM_TCR_GTSFREQ_Pos 10 /*!< ITM TCR: Global timestamp frequency Position */ +#define ITM_TCR_GTSFREQ_Msk (3UL << ITM_TCR_GTSFREQ_Pos) /*!< ITM TCR: Global timestamp frequency Mask */ -#define ITM_TCR_TSPrescale_Pos 8 /*!< ITM TCR: TSPrescale Position */ -#define ITM_TCR_TSPrescale_Msk (3UL << ITM_TCR_TSPrescale_Pos) /*!< ITM TCR: TSPrescale Mask */ +#define ITM_TCR_TSPrescale_Pos 8 /*!< ITM TCR: TSPrescale Position */ +#define ITM_TCR_TSPrescale_Msk (3UL << ITM_TCR_TSPrescale_Pos) /*!< ITM TCR: TSPrescale Mask */ -#define ITM_TCR_SWOENA_Pos 4 /*!< ITM TCR: SWOENA Position */ -#define ITM_TCR_SWOENA_Msk (1UL << ITM_TCR_SWOENA_Pos) /*!< ITM TCR: SWOENA Mask */ +#define ITM_TCR_SWOENA_Pos 4 /*!< ITM TCR: SWOENA Position */ +#define ITM_TCR_SWOENA_Msk (1UL << ITM_TCR_SWOENA_Pos) /*!< ITM TCR: SWOENA Mask */ -#define ITM_TCR_DWTENA_Pos 3 /*!< ITM TCR: DWTENA Position */ -#define ITM_TCR_DWTENA_Msk (1UL << ITM_TCR_DWTENA_Pos) /*!< ITM TCR: DWTENA Mask */ +#define ITM_TCR_DWTENA_Pos 3 /*!< ITM TCR: DWTENA Position */ +#define ITM_TCR_DWTENA_Msk (1UL << ITM_TCR_DWTENA_Pos) /*!< ITM TCR: DWTENA Mask */ -#define ITM_TCR_SYNCENA_Pos 2 /*!< ITM TCR: SYNCENA Position */ -#define ITM_TCR_SYNCENA_Msk (1UL << ITM_TCR_SYNCENA_Pos) /*!< ITM TCR: SYNCENA Mask */ +#define ITM_TCR_SYNCENA_Pos 2 /*!< ITM TCR: SYNCENA Position */ +#define ITM_TCR_SYNCENA_Msk (1UL << ITM_TCR_SYNCENA_Pos) /*!< ITM TCR: SYNCENA Mask */ -#define ITM_TCR_TSENA_Pos 1 /*!< ITM TCR: TSENA Position */ -#define ITM_TCR_TSENA_Msk (1UL << ITM_TCR_TSENA_Pos) /*!< ITM TCR: TSENA Mask */ +#define ITM_TCR_TSENA_Pos 1 /*!< ITM TCR: TSENA Position */ +#define ITM_TCR_TSENA_Msk (1UL << ITM_TCR_TSENA_Pos) /*!< ITM TCR: TSENA Mask */ -#define ITM_TCR_ITMENA_Pos 0 /*!< ITM TCR: ITM Enable bit Position */ -#define ITM_TCR_ITMENA_Msk (1UL << ITM_TCR_ITMENA_Pos) /*!< ITM TCR: ITM Enable bit Mask */ +#define ITM_TCR_ITMENA_Pos 0 /*!< ITM TCR: ITM Enable bit Position */ +#define ITM_TCR_ITMENA_Msk (1UL << ITM_TCR_ITMENA_Pos) /*!< ITM TCR: ITM Enable bit Mask */ /* ITM Integration Write Register Definitions */ -#define ITM_IWR_ATVALIDM_Pos 0 /*!< ITM IWR: ATVALIDM Position */ -#define ITM_IWR_ATVALIDM_Msk (1UL << ITM_IWR_ATVALIDM_Pos) /*!< ITM IWR: ATVALIDM Mask */ +#define ITM_IWR_ATVALIDM_Pos 0 /*!< ITM IWR: ATVALIDM Position */ +#define ITM_IWR_ATVALIDM_Msk (1UL << ITM_IWR_ATVALIDM_Pos) /*!< ITM IWR: ATVALIDM Mask */ /* ITM Integration Read Register Definitions */ -#define ITM_IRR_ATREADYM_Pos 0 /*!< ITM IRR: ATREADYM Position */ -#define ITM_IRR_ATREADYM_Msk (1UL << ITM_IRR_ATREADYM_Pos) /*!< ITM IRR: ATREADYM Mask */ +#define ITM_IRR_ATREADYM_Pos 0 /*!< ITM IRR: ATREADYM Position */ +#define ITM_IRR_ATREADYM_Msk (1UL << ITM_IRR_ATREADYM_Pos) /*!< ITM IRR: ATREADYM Mask */ /* ITM Integration Mode Control Register Definitions */ -#define ITM_IMCR_INTEGRATION_Pos 0 /*!< ITM IMCR: INTEGRATION Position */ -#define ITM_IMCR_INTEGRATION_Msk (1UL << ITM_IMCR_INTEGRATION_Pos) /*!< ITM IMCR: INTEGRATION Mask */ +#define ITM_IMCR_INTEGRATION_Pos 0 /*!< ITM IMCR: INTEGRATION Position */ +#define ITM_IMCR_INTEGRATION_Msk (1UL << ITM_IMCR_INTEGRATION_Pos) /*!< ITM IMCR: INTEGRATION Mask */ /* ITM Lock Status Register Definitions */ -#define ITM_LSR_ByteAcc_Pos 2 /*!< ITM LSR: ByteAcc Position */ -#define ITM_LSR_ByteAcc_Msk (1UL << ITM_LSR_ByteAcc_Pos) /*!< ITM LSR: ByteAcc Mask */ +#define ITM_LSR_ByteAcc_Pos 2 /*!< ITM LSR: ByteAcc Position */ +#define ITM_LSR_ByteAcc_Msk (1UL << ITM_LSR_ByteAcc_Pos) /*!< ITM LSR: ByteAcc Mask */ -#define ITM_LSR_Access_Pos 1 /*!< ITM LSR: Access Position */ -#define ITM_LSR_Access_Msk (1UL << ITM_LSR_Access_Pos) /*!< ITM LSR: Access Mask */ +#define ITM_LSR_Access_Pos 1 /*!< ITM LSR: Access Position */ +#define ITM_LSR_Access_Msk (1UL << ITM_LSR_Access_Pos) /*!< ITM LSR: Access Mask */ -#define ITM_LSR_Present_Pos 0 /*!< ITM LSR: Present Position */ -#define ITM_LSR_Present_Msk (1UL << ITM_LSR_Present_Pos) /*!< ITM LSR: Present Mask */ +#define ITM_LSR_Present_Pos 0 /*!< ITM LSR: Present Position */ +#define ITM_LSR_Present_Msk (1UL << ITM_LSR_Present_Pos) /*!< ITM LSR: Present Mask */ -/*@}*/ /* end of group CMSIS_ITM */ + /*@}*/ /* end of group CMSIS_ITM */ - -/** \ingroup CMSIS_core_register + /** \ingroup CMSIS_core_register \defgroup CMSIS_DWT Data Watchpoint and Trace (DWT) \brief Type definitions for the Data Watchpoint and Trace (DWT) @{ */ -/** \brief Structure type to access the Data Watchpoint and Trace Register (DWT). + /** \brief Structure type to access the Data Watchpoint and Trace Register (DWT). */ -typedef struct -{ - __IO uint32_t CTRL; /*!< Offset: 0x000 (R/W) Control Register */ - __IO uint32_t CYCCNT; /*!< Offset: 0x004 (R/W) Cycle Count Register */ - __IO uint32_t CPICNT; /*!< Offset: 0x008 (R/W) CPI Count Register */ - __IO uint32_t EXCCNT; /*!< Offset: 0x00C (R/W) Exception Overhead Count Register */ - __IO uint32_t SLEEPCNT; /*!< Offset: 0x010 (R/W) Sleep Count Register */ - __IO uint32_t LSUCNT; /*!< Offset: 0x014 (R/W) LSU Count Register */ - __IO uint32_t FOLDCNT; /*!< Offset: 0x018 (R/W) Folded-instruction Count Register */ - __I uint32_t PCSR; /*!< Offset: 0x01C (R/ ) Program Counter Sample Register */ - __IO uint32_t COMP0; /*!< Offset: 0x020 (R/W) Comparator Register 0 */ - __IO uint32_t MASK0; /*!< Offset: 0x024 (R/W) Mask Register 0 */ - __IO uint32_t FUNCTION0; /*!< Offset: 0x028 (R/W) Function Register 0 */ - uint32_t RESERVED0[1]; - __IO uint32_t COMP1; /*!< Offset: 0x030 (R/W) Comparator Register 1 */ - __IO uint32_t MASK1; /*!< Offset: 0x034 (R/W) Mask Register 1 */ - __IO uint32_t FUNCTION1; /*!< Offset: 0x038 (R/W) Function Register 1 */ - uint32_t RESERVED1[1]; - __IO uint32_t COMP2; /*!< Offset: 0x040 (R/W) Comparator Register 2 */ - __IO uint32_t MASK2; /*!< Offset: 0x044 (R/W) Mask Register 2 */ - __IO uint32_t FUNCTION2; /*!< Offset: 0x048 (R/W) Function Register 2 */ - uint32_t RESERVED2[1]; - __IO uint32_t COMP3; /*!< Offset: 0x050 (R/W) Comparator Register 3 */ - __IO uint32_t MASK3; /*!< Offset: 0x054 (R/W) Mask Register 3 */ - __IO uint32_t FUNCTION3; /*!< Offset: 0x058 (R/W) Function Register 3 */ -} DWT_Type; + typedef struct + { + __IO uint32_t CTRL; /*!< Offset: 0x000 (R/W) Control Register */ + __IO uint32_t CYCCNT; /*!< Offset: 0x004 (R/W) Cycle Count Register */ + __IO uint32_t CPICNT; /*!< Offset: 0x008 (R/W) CPI Count Register */ + __IO uint32_t EXCCNT; /*!< Offset: 0x00C (R/W) Exception Overhead Count Register */ + __IO uint32_t SLEEPCNT; /*!< Offset: 0x010 (R/W) Sleep Count Register */ + __IO uint32_t LSUCNT; /*!< Offset: 0x014 (R/W) LSU Count Register */ + __IO uint32_t FOLDCNT; /*!< Offset: 0x018 (R/W) Folded-instruction Count Register */ + __I uint32_t PCSR; /*!< Offset: 0x01C (R/ ) Program Counter Sample Register */ + __IO uint32_t COMP0; /*!< Offset: 0x020 (R/W) Comparator Register 0 */ + __IO uint32_t MASK0; /*!< Offset: 0x024 (R/W) Mask Register 0 */ + __IO uint32_t FUNCTION0; /*!< Offset: 0x028 (R/W) Function Register 0 */ + uint32_t RESERVED0[1]; + __IO uint32_t COMP1; /*!< Offset: 0x030 (R/W) Comparator Register 1 */ + __IO uint32_t MASK1; /*!< Offset: 0x034 (R/W) Mask Register 1 */ + __IO uint32_t FUNCTION1; /*!< Offset: 0x038 (R/W) Function Register 1 */ + uint32_t RESERVED1[1]; + __IO uint32_t COMP2; /*!< Offset: 0x040 (R/W) Comparator Register 2 */ + __IO uint32_t MASK2; /*!< Offset: 0x044 (R/W) Mask Register 2 */ + __IO uint32_t FUNCTION2; /*!< Offset: 0x048 (R/W) Function Register 2 */ + uint32_t RESERVED2[1]; + __IO uint32_t COMP3; /*!< Offset: 0x050 (R/W) Comparator Register 3 */ + __IO uint32_t MASK3; /*!< Offset: 0x054 (R/W) Mask Register 3 */ + __IO uint32_t FUNCTION3; /*!< Offset: 0x058 (R/W) Function Register 3 */ + } DWT_Type; /* DWT Control Register Definitions */ -#define DWT_CTRL_NUMCOMP_Pos 28 /*!< DWT CTRL: NUMCOMP Position */ -#define DWT_CTRL_NUMCOMP_Msk (0xFUL << DWT_CTRL_NUMCOMP_Pos) /*!< DWT CTRL: NUMCOMP Mask */ +#define DWT_CTRL_NUMCOMP_Pos 28 /*!< DWT CTRL: NUMCOMP Position */ +#define DWT_CTRL_NUMCOMP_Msk (0xFUL << DWT_CTRL_NUMCOMP_Pos) /*!< DWT CTRL: NUMCOMP Mask */ -#define DWT_CTRL_NOTRCPKT_Pos 27 /*!< DWT CTRL: NOTRCPKT Position */ -#define DWT_CTRL_NOTRCPKT_Msk (0x1UL << DWT_CTRL_NOTRCPKT_Pos) /*!< DWT CTRL: NOTRCPKT Mask */ +#define DWT_CTRL_NOTRCPKT_Pos 27 /*!< DWT CTRL: NOTRCPKT Position */ +#define DWT_CTRL_NOTRCPKT_Msk (0x1UL << DWT_CTRL_NOTRCPKT_Pos) /*!< DWT CTRL: NOTRCPKT Mask */ -#define DWT_CTRL_NOEXTTRIG_Pos 26 /*!< DWT CTRL: NOEXTTRIG Position */ -#define DWT_CTRL_NOEXTTRIG_Msk (0x1UL << DWT_CTRL_NOEXTTRIG_Pos) /*!< DWT CTRL: NOEXTTRIG Mask */ +#define DWT_CTRL_NOEXTTRIG_Pos 26 /*!< DWT CTRL: NOEXTTRIG Position */ +#define DWT_CTRL_NOEXTTRIG_Msk (0x1UL << DWT_CTRL_NOEXTTRIG_Pos) /*!< DWT CTRL: NOEXTTRIG Mask */ -#define DWT_CTRL_NOCYCCNT_Pos 25 /*!< DWT CTRL: NOCYCCNT Position */ -#define DWT_CTRL_NOCYCCNT_Msk (0x1UL << DWT_CTRL_NOCYCCNT_Pos) /*!< DWT CTRL: NOCYCCNT Mask */ +#define DWT_CTRL_NOCYCCNT_Pos 25 /*!< DWT CTRL: NOCYCCNT Position */ +#define DWT_CTRL_NOCYCCNT_Msk (0x1UL << DWT_CTRL_NOCYCCNT_Pos) /*!< DWT CTRL: NOCYCCNT Mask */ -#define DWT_CTRL_NOPRFCNT_Pos 24 /*!< DWT CTRL: NOPRFCNT Position */ -#define DWT_CTRL_NOPRFCNT_Msk (0x1UL << DWT_CTRL_NOPRFCNT_Pos) /*!< DWT CTRL: NOPRFCNT Mask */ +#define DWT_CTRL_NOPRFCNT_Pos 24 /*!< DWT CTRL: NOPRFCNT Position */ +#define DWT_CTRL_NOPRFCNT_Msk (0x1UL << DWT_CTRL_NOPRFCNT_Pos) /*!< DWT CTRL: NOPRFCNT Mask */ -#define DWT_CTRL_CYCEVTENA_Pos 22 /*!< DWT CTRL: CYCEVTENA Position */ -#define DWT_CTRL_CYCEVTENA_Msk (0x1UL << DWT_CTRL_CYCEVTENA_Pos) /*!< DWT CTRL: CYCEVTENA Mask */ +#define DWT_CTRL_CYCEVTENA_Pos 22 /*!< DWT CTRL: CYCEVTENA Position */ +#define DWT_CTRL_CYCEVTENA_Msk (0x1UL << DWT_CTRL_CYCEVTENA_Pos) /*!< DWT CTRL: CYCEVTENA Mask */ -#define DWT_CTRL_FOLDEVTENA_Pos 21 /*!< DWT CTRL: FOLDEVTENA Position */ -#define DWT_CTRL_FOLDEVTENA_Msk (0x1UL << DWT_CTRL_FOLDEVTENA_Pos) /*!< DWT CTRL: FOLDEVTENA Mask */ +#define DWT_CTRL_FOLDEVTENA_Pos 21 /*!< DWT CTRL: FOLDEVTENA Position */ +#define DWT_CTRL_FOLDEVTENA_Msk (0x1UL << DWT_CTRL_FOLDEVTENA_Pos) /*!< DWT CTRL: FOLDEVTENA Mask */ -#define DWT_CTRL_LSUEVTENA_Pos 20 /*!< DWT CTRL: LSUEVTENA Position */ -#define DWT_CTRL_LSUEVTENA_Msk (0x1UL << DWT_CTRL_LSUEVTENA_Pos) /*!< DWT CTRL: LSUEVTENA Mask */ +#define DWT_CTRL_LSUEVTENA_Pos 20 /*!< DWT CTRL: LSUEVTENA Position */ +#define DWT_CTRL_LSUEVTENA_Msk (0x1UL << DWT_CTRL_LSUEVTENA_Pos) /*!< DWT CTRL: LSUEVTENA Mask */ -#define DWT_CTRL_SLEEPEVTENA_Pos 19 /*!< DWT CTRL: SLEEPEVTENA Position */ -#define DWT_CTRL_SLEEPEVTENA_Msk (0x1UL << DWT_CTRL_SLEEPEVTENA_Pos) /*!< DWT CTRL: SLEEPEVTENA Mask */ +#define DWT_CTRL_SLEEPEVTENA_Pos 19 /*!< DWT CTRL: SLEEPEVTENA Position */ +#define DWT_CTRL_SLEEPEVTENA_Msk (0x1UL << DWT_CTRL_SLEEPEVTENA_Pos) /*!< DWT CTRL: SLEEPEVTENA Mask */ -#define DWT_CTRL_EXCEVTENA_Pos 18 /*!< DWT CTRL: EXCEVTENA Position */ -#define DWT_CTRL_EXCEVTENA_Msk (0x1UL << DWT_CTRL_EXCEVTENA_Pos) /*!< DWT CTRL: EXCEVTENA Mask */ +#define DWT_CTRL_EXCEVTENA_Pos 18 /*!< DWT CTRL: EXCEVTENA Position */ +#define DWT_CTRL_EXCEVTENA_Msk (0x1UL << DWT_CTRL_EXCEVTENA_Pos) /*!< DWT CTRL: EXCEVTENA Mask */ -#define DWT_CTRL_CPIEVTENA_Pos 17 /*!< DWT CTRL: CPIEVTENA Position */ -#define DWT_CTRL_CPIEVTENA_Msk (0x1UL << DWT_CTRL_CPIEVTENA_Pos) /*!< DWT CTRL: CPIEVTENA Mask */ +#define DWT_CTRL_CPIEVTENA_Pos 17 /*!< DWT CTRL: CPIEVTENA Position */ +#define DWT_CTRL_CPIEVTENA_Msk (0x1UL << DWT_CTRL_CPIEVTENA_Pos) /*!< DWT CTRL: CPIEVTENA Mask */ -#define DWT_CTRL_EXCTRCENA_Pos 16 /*!< DWT CTRL: EXCTRCENA Position */ -#define DWT_CTRL_EXCTRCENA_Msk (0x1UL << DWT_CTRL_EXCTRCENA_Pos) /*!< DWT CTRL: EXCTRCENA Mask */ +#define DWT_CTRL_EXCTRCENA_Pos 16 /*!< DWT CTRL: EXCTRCENA Position */ +#define DWT_CTRL_EXCTRCENA_Msk (0x1UL << DWT_CTRL_EXCTRCENA_Pos) /*!< DWT CTRL: EXCTRCENA Mask */ -#define DWT_CTRL_PCSAMPLENA_Pos 12 /*!< DWT CTRL: PCSAMPLENA Position */ -#define DWT_CTRL_PCSAMPLENA_Msk (0x1UL << DWT_CTRL_PCSAMPLENA_Pos) /*!< DWT CTRL: PCSAMPLENA Mask */ +#define DWT_CTRL_PCSAMPLENA_Pos 12 /*!< DWT CTRL: PCSAMPLENA Position */ +#define DWT_CTRL_PCSAMPLENA_Msk (0x1UL << DWT_CTRL_PCSAMPLENA_Pos) /*!< DWT CTRL: PCSAMPLENA Mask */ -#define DWT_CTRL_SYNCTAP_Pos 10 /*!< DWT CTRL: SYNCTAP Position */ -#define DWT_CTRL_SYNCTAP_Msk (0x3UL << DWT_CTRL_SYNCTAP_Pos) /*!< DWT CTRL: SYNCTAP Mask */ +#define DWT_CTRL_SYNCTAP_Pos 10 /*!< DWT CTRL: SYNCTAP Position */ +#define DWT_CTRL_SYNCTAP_Msk (0x3UL << DWT_CTRL_SYNCTAP_Pos) /*!< DWT CTRL: SYNCTAP Mask */ -#define DWT_CTRL_CYCTAP_Pos 9 /*!< DWT CTRL: CYCTAP Position */ -#define DWT_CTRL_CYCTAP_Msk (0x1UL << DWT_CTRL_CYCTAP_Pos) /*!< DWT CTRL: CYCTAP Mask */ +#define DWT_CTRL_CYCTAP_Pos 9 /*!< DWT CTRL: CYCTAP Position */ +#define DWT_CTRL_CYCTAP_Msk (0x1UL << DWT_CTRL_CYCTAP_Pos) /*!< DWT CTRL: CYCTAP Mask */ -#define DWT_CTRL_POSTINIT_Pos 5 /*!< DWT CTRL: POSTINIT Position */ -#define DWT_CTRL_POSTINIT_Msk (0xFUL << DWT_CTRL_POSTINIT_Pos) /*!< DWT CTRL: POSTINIT Mask */ +#define DWT_CTRL_POSTINIT_Pos 5 /*!< DWT CTRL: POSTINIT Position */ +#define DWT_CTRL_POSTINIT_Msk (0xFUL << DWT_CTRL_POSTINIT_Pos) /*!< DWT CTRL: POSTINIT Mask */ -#define DWT_CTRL_POSTPRESET_Pos 1 /*!< DWT CTRL: POSTPRESET Position */ -#define DWT_CTRL_POSTPRESET_Msk (0xFUL << DWT_CTRL_POSTPRESET_Pos) /*!< DWT CTRL: POSTPRESET Mask */ +#define DWT_CTRL_POSTPRESET_Pos 1 /*!< DWT CTRL: POSTPRESET Position */ +#define DWT_CTRL_POSTPRESET_Msk (0xFUL << DWT_CTRL_POSTPRESET_Pos) /*!< DWT CTRL: POSTPRESET Mask */ -#define DWT_CTRL_CYCCNTENA_Pos 0 /*!< DWT CTRL: CYCCNTENA Position */ -#define DWT_CTRL_CYCCNTENA_Msk (0x1UL << DWT_CTRL_CYCCNTENA_Pos) /*!< DWT CTRL: CYCCNTENA Mask */ +#define DWT_CTRL_CYCCNTENA_Pos 0 /*!< DWT CTRL: CYCCNTENA Position */ +#define DWT_CTRL_CYCCNTENA_Msk (0x1UL << DWT_CTRL_CYCCNTENA_Pos) /*!< DWT CTRL: CYCCNTENA Mask */ /* DWT CPI Count Register Definitions */ -#define DWT_CPICNT_CPICNT_Pos 0 /*!< DWT CPICNT: CPICNT Position */ -#define DWT_CPICNT_CPICNT_Msk (0xFFUL << DWT_CPICNT_CPICNT_Pos) /*!< DWT CPICNT: CPICNT Mask */ +#define DWT_CPICNT_CPICNT_Pos 0 /*!< DWT CPICNT: CPICNT Position */ +#define DWT_CPICNT_CPICNT_Msk (0xFFUL << DWT_CPICNT_CPICNT_Pos) /*!< DWT CPICNT: CPICNT Mask */ /* DWT Exception Overhead Count Register Definitions */ -#define DWT_EXCCNT_EXCCNT_Pos 0 /*!< DWT EXCCNT: EXCCNT Position */ -#define DWT_EXCCNT_EXCCNT_Msk (0xFFUL << DWT_EXCCNT_EXCCNT_Pos) /*!< DWT EXCCNT: EXCCNT Mask */ +#define DWT_EXCCNT_EXCCNT_Pos 0 /*!< DWT EXCCNT: EXCCNT Position */ +#define DWT_EXCCNT_EXCCNT_Msk (0xFFUL << DWT_EXCCNT_EXCCNT_Pos) /*!< DWT EXCCNT: EXCCNT Mask */ /* DWT Sleep Count Register Definitions */ -#define DWT_SLEEPCNT_SLEEPCNT_Pos 0 /*!< DWT SLEEPCNT: SLEEPCNT Position */ -#define DWT_SLEEPCNT_SLEEPCNT_Msk (0xFFUL << DWT_SLEEPCNT_SLEEPCNT_Pos) /*!< DWT SLEEPCNT: SLEEPCNT Mask */ +#define DWT_SLEEPCNT_SLEEPCNT_Pos 0 /*!< DWT SLEEPCNT: SLEEPCNT Position */ +#define DWT_SLEEPCNT_SLEEPCNT_Msk (0xFFUL << DWT_SLEEPCNT_SLEEPCNT_Pos) /*!< DWT SLEEPCNT: SLEEPCNT Mask */ /* DWT LSU Count Register Definitions */ -#define DWT_LSUCNT_LSUCNT_Pos 0 /*!< DWT LSUCNT: LSUCNT Position */ -#define DWT_LSUCNT_LSUCNT_Msk (0xFFUL << DWT_LSUCNT_LSUCNT_Pos) /*!< DWT LSUCNT: LSUCNT Mask */ +#define DWT_LSUCNT_LSUCNT_Pos 0 /*!< DWT LSUCNT: LSUCNT Position */ +#define DWT_LSUCNT_LSUCNT_Msk (0xFFUL << DWT_LSUCNT_LSUCNT_Pos) /*!< DWT LSUCNT: LSUCNT Mask */ /* DWT Folded-instruction Count Register Definitions */ -#define DWT_FOLDCNT_FOLDCNT_Pos 0 /*!< DWT FOLDCNT: FOLDCNT Position */ -#define DWT_FOLDCNT_FOLDCNT_Msk (0xFFUL << DWT_FOLDCNT_FOLDCNT_Pos) /*!< DWT FOLDCNT: FOLDCNT Mask */ +#define DWT_FOLDCNT_FOLDCNT_Pos 0 /*!< DWT FOLDCNT: FOLDCNT Position */ +#define DWT_FOLDCNT_FOLDCNT_Msk (0xFFUL << DWT_FOLDCNT_FOLDCNT_Pos) /*!< DWT FOLDCNT: FOLDCNT Mask */ /* DWT Comparator Mask Register Definitions */ -#define DWT_MASK_MASK_Pos 0 /*!< DWT MASK: MASK Position */ -#define DWT_MASK_MASK_Msk (0x1FUL << DWT_MASK_MASK_Pos) /*!< DWT MASK: MASK Mask */ +#define DWT_MASK_MASK_Pos 0 /*!< DWT MASK: MASK Position */ +#define DWT_MASK_MASK_Msk (0x1FUL << DWT_MASK_MASK_Pos) /*!< DWT MASK: MASK Mask */ /* DWT Comparator Function Register Definitions */ -#define DWT_FUNCTION_MATCHED_Pos 24 /*!< DWT FUNCTION: MATCHED Position */ -#define DWT_FUNCTION_MATCHED_Msk (0x1UL << DWT_FUNCTION_MATCHED_Pos) /*!< DWT FUNCTION: MATCHED Mask */ - -#define DWT_FUNCTION_DATAVADDR1_Pos 16 /*!< DWT FUNCTION: DATAVADDR1 Position */ -#define DWT_FUNCTION_DATAVADDR1_Msk (0xFUL << DWT_FUNCTION_DATAVADDR1_Pos) /*!< DWT FUNCTION: DATAVADDR1 Mask */ +#define DWT_FUNCTION_MATCHED_Pos 24 /*!< DWT FUNCTION: MATCHED Position */ +#define DWT_FUNCTION_MATCHED_Msk (0x1UL << DWT_FUNCTION_MATCHED_Pos) /*!< DWT FUNCTION: MATCHED Mask */ -#define DWT_FUNCTION_DATAVADDR0_Pos 12 /*!< DWT FUNCTION: DATAVADDR0 Position */ -#define DWT_FUNCTION_DATAVADDR0_Msk (0xFUL << DWT_FUNCTION_DATAVADDR0_Pos) /*!< DWT FUNCTION: DATAVADDR0 Mask */ +#define DWT_FUNCTION_DATAVADDR1_Pos 16 /*!< DWT FUNCTION: DATAVADDR1 Position */ +#define DWT_FUNCTION_DATAVADDR1_Msk (0xFUL << DWT_FUNCTION_DATAVADDR1_Pos) /*!< DWT FUNCTION: DATAVADDR1 Mask */ -#define DWT_FUNCTION_DATAVSIZE_Pos 10 /*!< DWT FUNCTION: DATAVSIZE Position */ -#define DWT_FUNCTION_DATAVSIZE_Msk (0x3UL << DWT_FUNCTION_DATAVSIZE_Pos) /*!< DWT FUNCTION: DATAVSIZE Mask */ +#define DWT_FUNCTION_DATAVADDR0_Pos 12 /*!< DWT FUNCTION: DATAVADDR0 Position */ +#define DWT_FUNCTION_DATAVADDR0_Msk (0xFUL << DWT_FUNCTION_DATAVADDR0_Pos) /*!< DWT FUNCTION: DATAVADDR0 Mask */ -#define DWT_FUNCTION_LNK1ENA_Pos 9 /*!< DWT FUNCTION: LNK1ENA Position */ -#define DWT_FUNCTION_LNK1ENA_Msk (0x1UL << DWT_FUNCTION_LNK1ENA_Pos) /*!< DWT FUNCTION: LNK1ENA Mask */ +#define DWT_FUNCTION_DATAVSIZE_Pos 10 /*!< DWT FUNCTION: DATAVSIZE Position */ +#define DWT_FUNCTION_DATAVSIZE_Msk (0x3UL << DWT_FUNCTION_DATAVSIZE_Pos) /*!< DWT FUNCTION: DATAVSIZE Mask */ -#define DWT_FUNCTION_DATAVMATCH_Pos 8 /*!< DWT FUNCTION: DATAVMATCH Position */ -#define DWT_FUNCTION_DATAVMATCH_Msk (0x1UL << DWT_FUNCTION_DATAVMATCH_Pos) /*!< DWT FUNCTION: DATAVMATCH Mask */ +#define DWT_FUNCTION_LNK1ENA_Pos 9 /*!< DWT FUNCTION: LNK1ENA Position */ +#define DWT_FUNCTION_LNK1ENA_Msk (0x1UL << DWT_FUNCTION_LNK1ENA_Pos) /*!< DWT FUNCTION: LNK1ENA Mask */ -#define DWT_FUNCTION_CYCMATCH_Pos 7 /*!< DWT FUNCTION: CYCMATCH Position */ -#define DWT_FUNCTION_CYCMATCH_Msk (0x1UL << DWT_FUNCTION_CYCMATCH_Pos) /*!< DWT FUNCTION: CYCMATCH Mask */ +#define DWT_FUNCTION_DATAVMATCH_Pos 8 /*!< DWT FUNCTION: DATAVMATCH Position */ +#define DWT_FUNCTION_DATAVMATCH_Msk (0x1UL << DWT_FUNCTION_DATAVMATCH_Pos) /*!< DWT FUNCTION: DATAVMATCH Mask */ -#define DWT_FUNCTION_EMITRANGE_Pos 5 /*!< DWT FUNCTION: EMITRANGE Position */ -#define DWT_FUNCTION_EMITRANGE_Msk (0x1UL << DWT_FUNCTION_EMITRANGE_Pos) /*!< DWT FUNCTION: EMITRANGE Mask */ +#define DWT_FUNCTION_CYCMATCH_Pos 7 /*!< DWT FUNCTION: CYCMATCH Position */ +#define DWT_FUNCTION_CYCMATCH_Msk (0x1UL << DWT_FUNCTION_CYCMATCH_Pos) /*!< DWT FUNCTION: CYCMATCH Mask */ -#define DWT_FUNCTION_FUNCTION_Pos 0 /*!< DWT FUNCTION: FUNCTION Position */ -#define DWT_FUNCTION_FUNCTION_Msk (0xFUL << DWT_FUNCTION_FUNCTION_Pos) /*!< DWT FUNCTION: FUNCTION Mask */ +#define DWT_FUNCTION_EMITRANGE_Pos 5 /*!< DWT FUNCTION: EMITRANGE Position */ +#define DWT_FUNCTION_EMITRANGE_Msk (0x1UL << DWT_FUNCTION_EMITRANGE_Pos) /*!< DWT FUNCTION: EMITRANGE Mask */ -/*@}*/ /* end of group CMSIS_DWT */ +#define DWT_FUNCTION_FUNCTION_Pos 0 /*!< DWT FUNCTION: FUNCTION Position */ +#define DWT_FUNCTION_FUNCTION_Msk (0xFUL << DWT_FUNCTION_FUNCTION_Pos) /*!< DWT FUNCTION: FUNCTION Mask */ + /*@}*/ /* end of group CMSIS_DWT */ -/** \ingroup CMSIS_core_register + /** \ingroup CMSIS_core_register \defgroup CMSIS_TPI Trace Port Interface (TPI) \brief Type definitions for the Trace Port Interface (TPI) @{ */ -/** \brief Structure type to access the Trace Port Interface Register (TPI). + /** \brief Structure type to access the Trace Port Interface Register (TPI). */ -typedef struct -{ - __IO uint32_t SSPSR; /*!< Offset: 0x000 (R/ ) Supported Parallel Port Size Register */ - __IO uint32_t CSPSR; /*!< Offset: 0x004 (R/W) Current Parallel Port Size Register */ - uint32_t RESERVED0[2]; - __IO uint32_t ACPR; /*!< Offset: 0x010 (R/W) Asynchronous Clock Prescaler Register */ - uint32_t RESERVED1[55]; - __IO uint32_t SPPR; /*!< Offset: 0x0F0 (R/W) Selected Pin Protocol Register */ - uint32_t RESERVED2[131]; - __I uint32_t FFSR; /*!< Offset: 0x300 (R/ ) Formatter and Flush Status Register */ - __IO uint32_t FFCR; /*!< Offset: 0x304 (R/W) Formatter and Flush Control Register */ - __I uint32_t FSCR; /*!< Offset: 0x308 (R/ ) Formatter Synchronization Counter Register */ - uint32_t RESERVED3[759]; - __I uint32_t TRIGGER; /*!< Offset: 0xEE8 (R/ ) TRIGGER */ - __I uint32_t FIFO0; /*!< Offset: 0xEEC (R/ ) Integration ETM Data */ - __I uint32_t ITATBCTR2; /*!< Offset: 0xEF0 (R/ ) ITATBCTR2 */ - uint32_t RESERVED4[1]; - __I uint32_t ITATBCTR0; /*!< Offset: 0xEF8 (R/ ) ITATBCTR0 */ - __I uint32_t FIFO1; /*!< Offset: 0xEFC (R/ ) Integration ITM Data */ - __IO uint32_t ITCTRL; /*!< Offset: 0xF00 (R/W) Integration Mode Control */ - uint32_t RESERVED5[39]; - __IO uint32_t CLAIMSET; /*!< Offset: 0xFA0 (R/W) Claim tag set */ - __IO uint32_t CLAIMCLR; /*!< Offset: 0xFA4 (R/W) Claim tag clear */ - uint32_t RESERVED7[8]; - __I uint32_t DEVID; /*!< Offset: 0xFC8 (R/ ) TPIU_DEVID */ - __I uint32_t DEVTYPE; /*!< Offset: 0xFCC (R/ ) TPIU_DEVTYPE */ -} TPI_Type; + typedef struct + { + __IO uint32_t SSPSR; /*!< Offset: 0x000 (R/ ) Supported Parallel Port Size Register */ + __IO uint32_t CSPSR; /*!< Offset: 0x004 (R/W) Current Parallel Port Size Register */ + uint32_t RESERVED0[2]; + __IO uint32_t ACPR; /*!< Offset: 0x010 (R/W) Asynchronous Clock Prescaler Register */ + uint32_t RESERVED1[55]; + __IO uint32_t SPPR; /*!< Offset: 0x0F0 (R/W) Selected Pin Protocol Register */ + uint32_t RESERVED2[131]; + __I uint32_t FFSR; /*!< Offset: 0x300 (R/ ) Formatter and Flush Status Register */ + __IO uint32_t FFCR; /*!< Offset: 0x304 (R/W) Formatter and Flush Control Register */ + __I uint32_t FSCR; /*!< Offset: 0x308 (R/ ) Formatter Synchronization Counter Register */ + uint32_t RESERVED3[759]; + __I uint32_t TRIGGER; /*!< Offset: 0xEE8 (R/ ) TRIGGER */ + __I uint32_t FIFO0; /*!< Offset: 0xEEC (R/ ) Integration ETM Data */ + __I uint32_t ITATBCTR2; /*!< Offset: 0xEF0 (R/ ) ITATBCTR2 */ + uint32_t RESERVED4[1]; + __I uint32_t ITATBCTR0; /*!< Offset: 0xEF8 (R/ ) ITATBCTR0 */ + __I uint32_t FIFO1; /*!< Offset: 0xEFC (R/ ) Integration ITM Data */ + __IO uint32_t ITCTRL; /*!< Offset: 0xF00 (R/W) Integration Mode Control */ + uint32_t RESERVED5[39]; + __IO uint32_t CLAIMSET; /*!< Offset: 0xFA0 (R/W) Claim tag set */ + __IO uint32_t CLAIMCLR; /*!< Offset: 0xFA4 (R/W) Claim tag clear */ + uint32_t RESERVED7[8]; + __I uint32_t DEVID; /*!< Offset: 0xFC8 (R/ ) TPIU_DEVID */ + __I uint32_t DEVTYPE; /*!< Offset: 0xFCC (R/ ) TPIU_DEVTYPE */ + } TPI_Type; /* TPI Asynchronous Clock Prescaler Register Definitions */ -#define TPI_ACPR_PRESCALER_Pos 0 /*!< TPI ACPR: PRESCALER Position */ -#define TPI_ACPR_PRESCALER_Msk (0x1FFFUL << TPI_ACPR_PRESCALER_Pos) /*!< TPI ACPR: PRESCALER Mask */ +#define TPI_ACPR_PRESCALER_Pos 0 /*!< TPI ACPR: PRESCALER Position */ +#define TPI_ACPR_PRESCALER_Msk (0x1FFFUL << TPI_ACPR_PRESCALER_Pos) /*!< TPI ACPR: PRESCALER Mask */ /* TPI Selected Pin Protocol Register Definitions */ -#define TPI_SPPR_TXMODE_Pos 0 /*!< TPI SPPR: TXMODE Position */ -#define TPI_SPPR_TXMODE_Msk (0x3UL << TPI_SPPR_TXMODE_Pos) /*!< TPI SPPR: TXMODE Mask */ +#define TPI_SPPR_TXMODE_Pos 0 /*!< TPI SPPR: TXMODE Position */ +#define TPI_SPPR_TXMODE_Msk (0x3UL << TPI_SPPR_TXMODE_Pos) /*!< TPI SPPR: TXMODE Mask */ /* TPI Formatter and Flush Status Register Definitions */ -#define TPI_FFSR_FtNonStop_Pos 3 /*!< TPI FFSR: FtNonStop Position */ -#define TPI_FFSR_FtNonStop_Msk (0x1UL << TPI_FFSR_FtNonStop_Pos) /*!< TPI FFSR: FtNonStop Mask */ +#define TPI_FFSR_FtNonStop_Pos 3 /*!< TPI FFSR: FtNonStop Position */ +#define TPI_FFSR_FtNonStop_Msk (0x1UL << TPI_FFSR_FtNonStop_Pos) /*!< TPI FFSR: FtNonStop Mask */ -#define TPI_FFSR_TCPresent_Pos 2 /*!< TPI FFSR: TCPresent Position */ -#define TPI_FFSR_TCPresent_Msk (0x1UL << TPI_FFSR_TCPresent_Pos) /*!< TPI FFSR: TCPresent Mask */ +#define TPI_FFSR_TCPresent_Pos 2 /*!< TPI FFSR: TCPresent Position */ +#define TPI_FFSR_TCPresent_Msk (0x1UL << TPI_FFSR_TCPresent_Pos) /*!< TPI FFSR: TCPresent Mask */ -#define TPI_FFSR_FtStopped_Pos 1 /*!< TPI FFSR: FtStopped Position */ -#define TPI_FFSR_FtStopped_Msk (0x1UL << TPI_FFSR_FtStopped_Pos) /*!< TPI FFSR: FtStopped Mask */ +#define TPI_FFSR_FtStopped_Pos 1 /*!< TPI FFSR: FtStopped Position */ +#define TPI_FFSR_FtStopped_Msk (0x1UL << TPI_FFSR_FtStopped_Pos) /*!< TPI FFSR: FtStopped Mask */ -#define TPI_FFSR_FlInProg_Pos 0 /*!< TPI FFSR: FlInProg Position */ -#define TPI_FFSR_FlInProg_Msk (0x1UL << TPI_FFSR_FlInProg_Pos) /*!< TPI FFSR: FlInProg Mask */ +#define TPI_FFSR_FlInProg_Pos 0 /*!< TPI FFSR: FlInProg Position */ +#define TPI_FFSR_FlInProg_Msk (0x1UL << TPI_FFSR_FlInProg_Pos) /*!< TPI FFSR: FlInProg Mask */ /* TPI Formatter and Flush Control Register Definitions */ -#define TPI_FFCR_TrigIn_Pos 8 /*!< TPI FFCR: TrigIn Position */ -#define TPI_FFCR_TrigIn_Msk (0x1UL << TPI_FFCR_TrigIn_Pos) /*!< TPI FFCR: TrigIn Mask */ +#define TPI_FFCR_TrigIn_Pos 8 /*!< TPI FFCR: TrigIn Position */ +#define TPI_FFCR_TrigIn_Msk (0x1UL << TPI_FFCR_TrigIn_Pos) /*!< TPI FFCR: TrigIn Mask */ -#define TPI_FFCR_EnFCont_Pos 1 /*!< TPI FFCR: EnFCont Position */ -#define TPI_FFCR_EnFCont_Msk (0x1UL << TPI_FFCR_EnFCont_Pos) /*!< TPI FFCR: EnFCont Mask */ +#define TPI_FFCR_EnFCont_Pos 1 /*!< TPI FFCR: EnFCont Position */ +#define TPI_FFCR_EnFCont_Msk (0x1UL << TPI_FFCR_EnFCont_Pos) /*!< TPI FFCR: EnFCont Mask */ /* TPI TRIGGER Register Definitions */ -#define TPI_TRIGGER_TRIGGER_Pos 0 /*!< TPI TRIGGER: TRIGGER Position */ -#define TPI_TRIGGER_TRIGGER_Msk (0x1UL << TPI_TRIGGER_TRIGGER_Pos) /*!< TPI TRIGGER: TRIGGER Mask */ +#define TPI_TRIGGER_TRIGGER_Pos 0 /*!< TPI TRIGGER: TRIGGER Position */ +#define TPI_TRIGGER_TRIGGER_Msk (0x1UL << TPI_TRIGGER_TRIGGER_Pos) /*!< TPI TRIGGER: TRIGGER Mask */ /* TPI Integration ETM Data Register Definitions (FIFO0) */ -#define TPI_FIFO0_ITM_ATVALID_Pos 29 /*!< TPI FIFO0: ITM_ATVALID Position */ -#define TPI_FIFO0_ITM_ATVALID_Msk (0x3UL << TPI_FIFO0_ITM_ATVALID_Pos) /*!< TPI FIFO0: ITM_ATVALID Mask */ +#define TPI_FIFO0_ITM_ATVALID_Pos 29 /*!< TPI FIFO0: ITM_ATVALID Position */ +#define TPI_FIFO0_ITM_ATVALID_Msk (0x3UL << TPI_FIFO0_ITM_ATVALID_Pos) /*!< TPI FIFO0: ITM_ATVALID Mask */ -#define TPI_FIFO0_ITM_bytecount_Pos 27 /*!< TPI FIFO0: ITM_bytecount Position */ -#define TPI_FIFO0_ITM_bytecount_Msk (0x3UL << TPI_FIFO0_ITM_bytecount_Pos) /*!< TPI FIFO0: ITM_bytecount Mask */ +#define TPI_FIFO0_ITM_bytecount_Pos 27 /*!< TPI FIFO0: ITM_bytecount Position */ +#define TPI_FIFO0_ITM_bytecount_Msk (0x3UL << TPI_FIFO0_ITM_bytecount_Pos) /*!< TPI FIFO0: ITM_bytecount Mask */ -#define TPI_FIFO0_ETM_ATVALID_Pos 26 /*!< TPI FIFO0: ETM_ATVALID Position */ -#define TPI_FIFO0_ETM_ATVALID_Msk (0x3UL << TPI_FIFO0_ETM_ATVALID_Pos) /*!< TPI FIFO0: ETM_ATVALID Mask */ +#define TPI_FIFO0_ETM_ATVALID_Pos 26 /*!< TPI FIFO0: ETM_ATVALID Position */ +#define TPI_FIFO0_ETM_ATVALID_Msk (0x3UL << TPI_FIFO0_ETM_ATVALID_Pos) /*!< TPI FIFO0: ETM_ATVALID Mask */ -#define TPI_FIFO0_ETM_bytecount_Pos 24 /*!< TPI FIFO0: ETM_bytecount Position */ -#define TPI_FIFO0_ETM_bytecount_Msk (0x3UL << TPI_FIFO0_ETM_bytecount_Pos) /*!< TPI FIFO0: ETM_bytecount Mask */ +#define TPI_FIFO0_ETM_bytecount_Pos 24 /*!< TPI FIFO0: ETM_bytecount Position */ +#define TPI_FIFO0_ETM_bytecount_Msk (0x3UL << TPI_FIFO0_ETM_bytecount_Pos) /*!< TPI FIFO0: ETM_bytecount Mask */ -#define TPI_FIFO0_ETM2_Pos 16 /*!< TPI FIFO0: ETM2 Position */ -#define TPI_FIFO0_ETM2_Msk (0xFFUL << TPI_FIFO0_ETM2_Pos) /*!< TPI FIFO0: ETM2 Mask */ +#define TPI_FIFO0_ETM2_Pos 16 /*!< TPI FIFO0: ETM2 Position */ +#define TPI_FIFO0_ETM2_Msk (0xFFUL << TPI_FIFO0_ETM2_Pos) /*!< TPI FIFO0: ETM2 Mask */ -#define TPI_FIFO0_ETM1_Pos 8 /*!< TPI FIFO0: ETM1 Position */ -#define TPI_FIFO0_ETM1_Msk (0xFFUL << TPI_FIFO0_ETM1_Pos) /*!< TPI FIFO0: ETM1 Mask */ +#define TPI_FIFO0_ETM1_Pos 8 /*!< TPI FIFO0: ETM1 Position */ +#define TPI_FIFO0_ETM1_Msk (0xFFUL << TPI_FIFO0_ETM1_Pos) /*!< TPI FIFO0: ETM1 Mask */ -#define TPI_FIFO0_ETM0_Pos 0 /*!< TPI FIFO0: ETM0 Position */ -#define TPI_FIFO0_ETM0_Msk (0xFFUL << TPI_FIFO0_ETM0_Pos) /*!< TPI FIFO0: ETM0 Mask */ +#define TPI_FIFO0_ETM0_Pos 0 /*!< TPI FIFO0: ETM0 Position */ +#define TPI_FIFO0_ETM0_Msk (0xFFUL << TPI_FIFO0_ETM0_Pos) /*!< TPI FIFO0: ETM0 Mask */ /* TPI ITATBCTR2 Register Definitions */ -#define TPI_ITATBCTR2_ATREADY_Pos 0 /*!< TPI ITATBCTR2: ATREADY Position */ -#define TPI_ITATBCTR2_ATREADY_Msk (0x1UL << TPI_ITATBCTR2_ATREADY_Pos) /*!< TPI ITATBCTR2: ATREADY Mask */ +#define TPI_ITATBCTR2_ATREADY_Pos 0 /*!< TPI ITATBCTR2: ATREADY Position */ +#define TPI_ITATBCTR2_ATREADY_Msk (0x1UL << TPI_ITATBCTR2_ATREADY_Pos) /*!< TPI ITATBCTR2: ATREADY Mask */ /* TPI Integration ITM Data Register Definitions (FIFO1) */ -#define TPI_FIFO1_ITM_ATVALID_Pos 29 /*!< TPI FIFO1: ITM_ATVALID Position */ -#define TPI_FIFO1_ITM_ATVALID_Msk (0x3UL << TPI_FIFO1_ITM_ATVALID_Pos) /*!< TPI FIFO1: ITM_ATVALID Mask */ +#define TPI_FIFO1_ITM_ATVALID_Pos 29 /*!< TPI FIFO1: ITM_ATVALID Position */ +#define TPI_FIFO1_ITM_ATVALID_Msk (0x3UL << TPI_FIFO1_ITM_ATVALID_Pos) /*!< TPI FIFO1: ITM_ATVALID Mask */ -#define TPI_FIFO1_ITM_bytecount_Pos 27 /*!< TPI FIFO1: ITM_bytecount Position */ -#define TPI_FIFO1_ITM_bytecount_Msk (0x3UL << TPI_FIFO1_ITM_bytecount_Pos) /*!< TPI FIFO1: ITM_bytecount Mask */ +#define TPI_FIFO1_ITM_bytecount_Pos 27 /*!< TPI FIFO1: ITM_bytecount Position */ +#define TPI_FIFO1_ITM_bytecount_Msk (0x3UL << TPI_FIFO1_ITM_bytecount_Pos) /*!< TPI FIFO1: ITM_bytecount Mask */ -#define TPI_FIFO1_ETM_ATVALID_Pos 26 /*!< TPI FIFO1: ETM_ATVALID Position */ -#define TPI_FIFO1_ETM_ATVALID_Msk (0x3UL << TPI_FIFO1_ETM_ATVALID_Pos) /*!< TPI FIFO1: ETM_ATVALID Mask */ +#define TPI_FIFO1_ETM_ATVALID_Pos 26 /*!< TPI FIFO1: ETM_ATVALID Position */ +#define TPI_FIFO1_ETM_ATVALID_Msk (0x3UL << TPI_FIFO1_ETM_ATVALID_Pos) /*!< TPI FIFO1: ETM_ATVALID Mask */ -#define TPI_FIFO1_ETM_bytecount_Pos 24 /*!< TPI FIFO1: ETM_bytecount Position */ -#define TPI_FIFO1_ETM_bytecount_Msk (0x3UL << TPI_FIFO1_ETM_bytecount_Pos) /*!< TPI FIFO1: ETM_bytecount Mask */ +#define TPI_FIFO1_ETM_bytecount_Pos 24 /*!< TPI FIFO1: ETM_bytecount Position */ +#define TPI_FIFO1_ETM_bytecount_Msk (0x3UL << TPI_FIFO1_ETM_bytecount_Pos) /*!< TPI FIFO1: ETM_bytecount Mask */ -#define TPI_FIFO1_ITM2_Pos 16 /*!< TPI FIFO1: ITM2 Position */ -#define TPI_FIFO1_ITM2_Msk (0xFFUL << TPI_FIFO1_ITM2_Pos) /*!< TPI FIFO1: ITM2 Mask */ +#define TPI_FIFO1_ITM2_Pos 16 /*!< TPI FIFO1: ITM2 Position */ +#define TPI_FIFO1_ITM2_Msk (0xFFUL << TPI_FIFO1_ITM2_Pos) /*!< TPI FIFO1: ITM2 Mask */ -#define TPI_FIFO1_ITM1_Pos 8 /*!< TPI FIFO1: ITM1 Position */ -#define TPI_FIFO1_ITM1_Msk (0xFFUL << TPI_FIFO1_ITM1_Pos) /*!< TPI FIFO1: ITM1 Mask */ +#define TPI_FIFO1_ITM1_Pos 8 /*!< TPI FIFO1: ITM1 Position */ +#define TPI_FIFO1_ITM1_Msk (0xFFUL << TPI_FIFO1_ITM1_Pos) /*!< TPI FIFO1: ITM1 Mask */ -#define TPI_FIFO1_ITM0_Pos 0 /*!< TPI FIFO1: ITM0 Position */ -#define TPI_FIFO1_ITM0_Msk (0xFFUL << TPI_FIFO1_ITM0_Pos) /*!< TPI FIFO1: ITM0 Mask */ +#define TPI_FIFO1_ITM0_Pos 0 /*!< TPI FIFO1: ITM0 Position */ +#define TPI_FIFO1_ITM0_Msk (0xFFUL << TPI_FIFO1_ITM0_Pos) /*!< TPI FIFO1: ITM0 Mask */ /* TPI ITATBCTR0 Register Definitions */ -#define TPI_ITATBCTR0_ATREADY_Pos 0 /*!< TPI ITATBCTR0: ATREADY Position */ -#define TPI_ITATBCTR0_ATREADY_Msk (0x1UL << TPI_ITATBCTR0_ATREADY_Pos) /*!< TPI ITATBCTR0: ATREADY Mask */ +#define TPI_ITATBCTR0_ATREADY_Pos 0 /*!< TPI ITATBCTR0: ATREADY Position */ +#define TPI_ITATBCTR0_ATREADY_Msk (0x1UL << TPI_ITATBCTR0_ATREADY_Pos) /*!< TPI ITATBCTR0: ATREADY Mask */ /* TPI Integration Mode Control Register Definitions */ -#define TPI_ITCTRL_Mode_Pos 0 /*!< TPI ITCTRL: Mode Position */ -#define TPI_ITCTRL_Mode_Msk (0x1UL << TPI_ITCTRL_Mode_Pos) /*!< TPI ITCTRL: Mode Mask */ +#define TPI_ITCTRL_Mode_Pos 0 /*!< TPI ITCTRL: Mode Position */ +#define TPI_ITCTRL_Mode_Msk (0x1UL << TPI_ITCTRL_Mode_Pos) /*!< TPI ITCTRL: Mode Mask */ /* TPI DEVID Register Definitions */ -#define TPI_DEVID_NRZVALID_Pos 11 /*!< TPI DEVID: NRZVALID Position */ -#define TPI_DEVID_NRZVALID_Msk (0x1UL << TPI_DEVID_NRZVALID_Pos) /*!< TPI DEVID: NRZVALID Mask */ +#define TPI_DEVID_NRZVALID_Pos 11 /*!< TPI DEVID: NRZVALID Position */ +#define TPI_DEVID_NRZVALID_Msk (0x1UL << TPI_DEVID_NRZVALID_Pos) /*!< TPI DEVID: NRZVALID Mask */ -#define TPI_DEVID_MANCVALID_Pos 10 /*!< TPI DEVID: MANCVALID Position */ -#define TPI_DEVID_MANCVALID_Msk (0x1UL << TPI_DEVID_MANCVALID_Pos) /*!< TPI DEVID: MANCVALID Mask */ +#define TPI_DEVID_MANCVALID_Pos 10 /*!< TPI DEVID: MANCVALID Position */ +#define TPI_DEVID_MANCVALID_Msk (0x1UL << TPI_DEVID_MANCVALID_Pos) /*!< TPI DEVID: MANCVALID Mask */ -#define TPI_DEVID_PTINVALID_Pos 9 /*!< TPI DEVID: PTINVALID Position */ -#define TPI_DEVID_PTINVALID_Msk (0x1UL << TPI_DEVID_PTINVALID_Pos) /*!< TPI DEVID: PTINVALID Mask */ +#define TPI_DEVID_PTINVALID_Pos 9 /*!< TPI DEVID: PTINVALID Position */ +#define TPI_DEVID_PTINVALID_Msk (0x1UL << TPI_DEVID_PTINVALID_Pos) /*!< TPI DEVID: PTINVALID Mask */ -#define TPI_DEVID_MinBufSz_Pos 6 /*!< TPI DEVID: MinBufSz Position */ -#define TPI_DEVID_MinBufSz_Msk (0x7UL << TPI_DEVID_MinBufSz_Pos) /*!< TPI DEVID: MinBufSz Mask */ +#define TPI_DEVID_MinBufSz_Pos 6 /*!< TPI DEVID: MinBufSz Position */ +#define TPI_DEVID_MinBufSz_Msk (0x7UL << TPI_DEVID_MinBufSz_Pos) /*!< TPI DEVID: MinBufSz Mask */ -#define TPI_DEVID_AsynClkIn_Pos 5 /*!< TPI DEVID: AsynClkIn Position */ -#define TPI_DEVID_AsynClkIn_Msk (0x1UL << TPI_DEVID_AsynClkIn_Pos) /*!< TPI DEVID: AsynClkIn Mask */ +#define TPI_DEVID_AsynClkIn_Pos 5 /*!< TPI DEVID: AsynClkIn Position */ +#define TPI_DEVID_AsynClkIn_Msk (0x1UL << TPI_DEVID_AsynClkIn_Pos) /*!< TPI DEVID: AsynClkIn Mask */ -#define TPI_DEVID_NrTraceInput_Pos 0 /*!< TPI DEVID: NrTraceInput Position */ -#define TPI_DEVID_NrTraceInput_Msk (0x1FUL << TPI_DEVID_NrTraceInput_Pos) /*!< TPI DEVID: NrTraceInput Mask */ +#define TPI_DEVID_NrTraceInput_Pos 0 /*!< TPI DEVID: NrTraceInput Position */ +#define TPI_DEVID_NrTraceInput_Msk (0x1FUL << TPI_DEVID_NrTraceInput_Pos) /*!< TPI DEVID: NrTraceInput Mask */ /* TPI DEVTYPE Register Definitions */ -#define TPI_DEVTYPE_SubType_Pos 0 /*!< TPI DEVTYPE: SubType Position */ -#define TPI_DEVTYPE_SubType_Msk (0xFUL << TPI_DEVTYPE_SubType_Pos) /*!< TPI DEVTYPE: SubType Mask */ - -#define TPI_DEVTYPE_MajorType_Pos 4 /*!< TPI DEVTYPE: MajorType Position */ -#define TPI_DEVTYPE_MajorType_Msk (0xFUL << TPI_DEVTYPE_MajorType_Pos) /*!< TPI DEVTYPE: MajorType Mask */ +#define TPI_DEVTYPE_SubType_Pos 0 /*!< TPI DEVTYPE: SubType Position */ +#define TPI_DEVTYPE_SubType_Msk (0xFUL << TPI_DEVTYPE_SubType_Pos) /*!< TPI DEVTYPE: SubType Mask */ -/*@}*/ /* end of group CMSIS_TPI */ +#define TPI_DEVTYPE_MajorType_Pos 4 /*!< TPI DEVTYPE: MajorType Position */ +#define TPI_DEVTYPE_MajorType_Msk (0xFUL << TPI_DEVTYPE_MajorType_Pos) /*!< TPI DEVTYPE: MajorType Mask */ + /*@}*/ /* end of group CMSIS_TPI */ #if (__MPU_PRESENT == 1) -/** \ingroup CMSIS_core_register + /** \ingroup CMSIS_core_register \defgroup CMSIS_MPU Memory Protection Unit (MPU) \brief Type definitions for the Memory Protection Unit (MPU) @{ */ -/** \brief Structure type to access the Memory Protection Unit (MPU). + /** \brief Structure type to access the Memory Protection Unit (MPU). */ -typedef struct -{ - __I uint32_t TYPE; /*!< Offset: 0x000 (R/ ) MPU Type Register */ - __IO uint32_t CTRL; /*!< Offset: 0x004 (R/W) MPU Control Register */ - __IO uint32_t RNR; /*!< Offset: 0x008 (R/W) MPU Region RNRber Register */ - __IO uint32_t RBAR; /*!< Offset: 0x00C (R/W) MPU Region Base Address Register */ - __IO uint32_t RASR; /*!< Offset: 0x010 (R/W) MPU Region Attribute and Size Register */ - __IO uint32_t RBAR_A1; /*!< Offset: 0x014 (R/W) MPU Alias 1 Region Base Address Register */ - __IO uint32_t RASR_A1; /*!< Offset: 0x018 (R/W) MPU Alias 1 Region Attribute and Size Register */ - __IO uint32_t RBAR_A2; /*!< Offset: 0x01C (R/W) MPU Alias 2 Region Base Address Register */ - __IO uint32_t RASR_A2; /*!< Offset: 0x020 (R/W) MPU Alias 2 Region Attribute and Size Register */ - __IO uint32_t RBAR_A3; /*!< Offset: 0x024 (R/W) MPU Alias 3 Region Base Address Register */ - __IO uint32_t RASR_A3; /*!< Offset: 0x028 (R/W) MPU Alias 3 Region Attribute and Size Register */ -} MPU_Type; + typedef struct + { + __I uint32_t TYPE; /*!< Offset: 0x000 (R/ ) MPU Type Register */ + __IO uint32_t CTRL; /*!< Offset: 0x004 (R/W) MPU Control Register */ + __IO uint32_t RNR; /*!< Offset: 0x008 (R/W) MPU Region RNRber Register */ + __IO uint32_t RBAR; /*!< Offset: 0x00C (R/W) MPU Region Base Address Register */ + __IO uint32_t RASR; /*!< Offset: 0x010 (R/W) MPU Region Attribute and Size Register */ + __IO uint32_t RBAR_A1; /*!< Offset: 0x014 (R/W) MPU Alias 1 Region Base Address Register */ + __IO uint32_t RASR_A1; /*!< Offset: 0x018 (R/W) MPU Alias 1 Region Attribute and Size Register */ + __IO uint32_t RBAR_A2; /*!< Offset: 0x01C (R/W) MPU Alias 2 Region Base Address Register */ + __IO uint32_t RASR_A2; /*!< Offset: 0x020 (R/W) MPU Alias 2 Region Attribute and Size Register */ + __IO uint32_t RBAR_A3; /*!< Offset: 0x024 (R/W) MPU Alias 3 Region Base Address Register */ + __IO uint32_t RASR_A3; /*!< Offset: 0x028 (R/W) MPU Alias 3 Region Attribute and Size Register */ + } MPU_Type; /* MPU Type Register */ -#define MPU_TYPE_IREGION_Pos 16 /*!< MPU TYPE: IREGION Position */ -#define MPU_TYPE_IREGION_Msk (0xFFUL << MPU_TYPE_IREGION_Pos) /*!< MPU TYPE: IREGION Mask */ +#define MPU_TYPE_IREGION_Pos 16 /*!< MPU TYPE: IREGION Position */ +#define MPU_TYPE_IREGION_Msk (0xFFUL << MPU_TYPE_IREGION_Pos) /*!< MPU TYPE: IREGION Mask */ -#define MPU_TYPE_DREGION_Pos 8 /*!< MPU TYPE: DREGION Position */ -#define MPU_TYPE_DREGION_Msk (0xFFUL << MPU_TYPE_DREGION_Pos) /*!< MPU TYPE: DREGION Mask */ +#define MPU_TYPE_DREGION_Pos 8 /*!< MPU TYPE: DREGION Position */ +#define MPU_TYPE_DREGION_Msk (0xFFUL << MPU_TYPE_DREGION_Pos) /*!< MPU TYPE: DREGION Mask */ -#define MPU_TYPE_SEPARATE_Pos 0 /*!< MPU TYPE: SEPARATE Position */ -#define MPU_TYPE_SEPARATE_Msk (1UL << MPU_TYPE_SEPARATE_Pos) /*!< MPU TYPE: SEPARATE Mask */ +#define MPU_TYPE_SEPARATE_Pos 0 /*!< MPU TYPE: SEPARATE Position */ +#define MPU_TYPE_SEPARATE_Msk (1UL << MPU_TYPE_SEPARATE_Pos) /*!< MPU TYPE: SEPARATE Mask */ /* MPU Control Register */ -#define MPU_CTRL_PRIVDEFENA_Pos 2 /*!< MPU CTRL: PRIVDEFENA Position */ -#define MPU_CTRL_PRIVDEFENA_Msk (1UL << MPU_CTRL_PRIVDEFENA_Pos) /*!< MPU CTRL: PRIVDEFENA Mask */ +#define MPU_CTRL_PRIVDEFENA_Pos 2 /*!< MPU CTRL: PRIVDEFENA Position */ +#define MPU_CTRL_PRIVDEFENA_Msk (1UL << MPU_CTRL_PRIVDEFENA_Pos) /*!< MPU CTRL: PRIVDEFENA Mask */ -#define MPU_CTRL_HFNMIENA_Pos 1 /*!< MPU CTRL: HFNMIENA Position */ -#define MPU_CTRL_HFNMIENA_Msk (1UL << MPU_CTRL_HFNMIENA_Pos) /*!< MPU CTRL: HFNMIENA Mask */ +#define MPU_CTRL_HFNMIENA_Pos 1 /*!< MPU CTRL: HFNMIENA Position */ +#define MPU_CTRL_HFNMIENA_Msk (1UL << MPU_CTRL_HFNMIENA_Pos) /*!< MPU CTRL: HFNMIENA Mask */ -#define MPU_CTRL_ENABLE_Pos 0 /*!< MPU CTRL: ENABLE Position */ -#define MPU_CTRL_ENABLE_Msk (1UL << MPU_CTRL_ENABLE_Pos) /*!< MPU CTRL: ENABLE Mask */ +#define MPU_CTRL_ENABLE_Pos 0 /*!< MPU CTRL: ENABLE Position */ +#define MPU_CTRL_ENABLE_Msk (1UL << MPU_CTRL_ENABLE_Pos) /*!< MPU CTRL: ENABLE Mask */ /* MPU Region Number Register */ -#define MPU_RNR_REGION_Pos 0 /*!< MPU RNR: REGION Position */ -#define MPU_RNR_REGION_Msk (0xFFUL << MPU_RNR_REGION_Pos) /*!< MPU RNR: REGION Mask */ +#define MPU_RNR_REGION_Pos 0 /*!< MPU RNR: REGION Position */ +#define MPU_RNR_REGION_Msk (0xFFUL << MPU_RNR_REGION_Pos) /*!< MPU RNR: REGION Mask */ /* MPU Region Base Address Register */ -#define MPU_RBAR_ADDR_Pos 5 /*!< MPU RBAR: ADDR Position */ -#define MPU_RBAR_ADDR_Msk (0x7FFFFFFUL << MPU_RBAR_ADDR_Pos) /*!< MPU RBAR: ADDR Mask */ +#define MPU_RBAR_ADDR_Pos 5 /*!< MPU RBAR: ADDR Position */ +#define MPU_RBAR_ADDR_Msk (0x7FFFFFFUL << MPU_RBAR_ADDR_Pos) /*!< MPU RBAR: ADDR Mask */ -#define MPU_RBAR_VALID_Pos 4 /*!< MPU RBAR: VALID Position */ -#define MPU_RBAR_VALID_Msk (1UL << MPU_RBAR_VALID_Pos) /*!< MPU RBAR: VALID Mask */ +#define MPU_RBAR_VALID_Pos 4 /*!< MPU RBAR: VALID Position */ +#define MPU_RBAR_VALID_Msk (1UL << MPU_RBAR_VALID_Pos) /*!< MPU RBAR: VALID Mask */ -#define MPU_RBAR_REGION_Pos 0 /*!< MPU RBAR: REGION Position */ -#define MPU_RBAR_REGION_Msk (0xFUL << MPU_RBAR_REGION_Pos) /*!< MPU RBAR: REGION Mask */ +#define MPU_RBAR_REGION_Pos 0 /*!< MPU RBAR: REGION Position */ +#define MPU_RBAR_REGION_Msk (0xFUL << MPU_RBAR_REGION_Pos) /*!< MPU RBAR: REGION Mask */ /* MPU Region Attribute and Size Register */ -#define MPU_RASR_ATTRS_Pos 16 /*!< MPU RASR: MPU Region Attribute field Position */ -#define MPU_RASR_ATTRS_Msk (0xFFFFUL << MPU_RASR_ATTRS_Pos) /*!< MPU RASR: MPU Region Attribute field Mask */ +#define MPU_RASR_ATTRS_Pos 16 /*!< MPU RASR: MPU Region Attribute field Position */ +#define MPU_RASR_ATTRS_Msk (0xFFFFUL << MPU_RASR_ATTRS_Pos) /*!< MPU RASR: MPU Region Attribute field Mask */ -#define MPU_RASR_XN_Pos 28 /*!< MPU RASR: ATTRS.XN Position */ -#define MPU_RASR_XN_Msk (1UL << MPU_RASR_XN_Pos) /*!< MPU RASR: ATTRS.XN Mask */ +#define MPU_RASR_XN_Pos 28 /*!< MPU RASR: ATTRS.XN Position */ +#define MPU_RASR_XN_Msk (1UL << MPU_RASR_XN_Pos) /*!< MPU RASR: ATTRS.XN Mask */ -#define MPU_RASR_AP_Pos 24 /*!< MPU RASR: ATTRS.AP Position */ -#define MPU_RASR_AP_Msk (0x7UL << MPU_RASR_AP_Pos) /*!< MPU RASR: ATTRS.AP Mask */ +#define MPU_RASR_AP_Pos 24 /*!< MPU RASR: ATTRS.AP Position */ +#define MPU_RASR_AP_Msk (0x7UL << MPU_RASR_AP_Pos) /*!< MPU RASR: ATTRS.AP Mask */ -#define MPU_RASR_TEX_Pos 19 /*!< MPU RASR: ATTRS.TEX Position */ -#define MPU_RASR_TEX_Msk (0x7UL << MPU_RASR_TEX_Pos) /*!< MPU RASR: ATTRS.TEX Mask */ +#define MPU_RASR_TEX_Pos 19 /*!< MPU RASR: ATTRS.TEX Position */ +#define MPU_RASR_TEX_Msk (0x7UL << MPU_RASR_TEX_Pos) /*!< MPU RASR: ATTRS.TEX Mask */ -#define MPU_RASR_S_Pos 18 /*!< MPU RASR: ATTRS.S Position */ -#define MPU_RASR_S_Msk (1UL << MPU_RASR_S_Pos) /*!< MPU RASR: ATTRS.S Mask */ +#define MPU_RASR_S_Pos 18 /*!< MPU RASR: ATTRS.S Position */ +#define MPU_RASR_S_Msk (1UL << MPU_RASR_S_Pos) /*!< MPU RASR: ATTRS.S Mask */ -#define MPU_RASR_C_Pos 17 /*!< MPU RASR: ATTRS.C Position */ -#define MPU_RASR_C_Msk (1UL << MPU_RASR_C_Pos) /*!< MPU RASR: ATTRS.C Mask */ +#define MPU_RASR_C_Pos 17 /*!< MPU RASR: ATTRS.C Position */ +#define MPU_RASR_C_Msk (1UL << MPU_RASR_C_Pos) /*!< MPU RASR: ATTRS.C Mask */ -#define MPU_RASR_B_Pos 16 /*!< MPU RASR: ATTRS.B Position */ -#define MPU_RASR_B_Msk (1UL << MPU_RASR_B_Pos) /*!< MPU RASR: ATTRS.B Mask */ +#define MPU_RASR_B_Pos 16 /*!< MPU RASR: ATTRS.B Position */ +#define MPU_RASR_B_Msk (1UL << MPU_RASR_B_Pos) /*!< MPU RASR: ATTRS.B Mask */ -#define MPU_RASR_SRD_Pos 8 /*!< MPU RASR: Sub-Region Disable Position */ -#define MPU_RASR_SRD_Msk (0xFFUL << MPU_RASR_SRD_Pos) /*!< MPU RASR: Sub-Region Disable Mask */ +#define MPU_RASR_SRD_Pos 8 /*!< MPU RASR: Sub-Region Disable Position */ +#define MPU_RASR_SRD_Msk (0xFFUL << MPU_RASR_SRD_Pos) /*!< MPU RASR: Sub-Region Disable Mask */ -#define MPU_RASR_SIZE_Pos 1 /*!< MPU RASR: Region Size Field Position */ -#define MPU_RASR_SIZE_Msk (0x1FUL << MPU_RASR_SIZE_Pos) /*!< MPU RASR: Region Size Field Mask */ +#define MPU_RASR_SIZE_Pos 1 /*!< MPU RASR: Region Size Field Position */ +#define MPU_RASR_SIZE_Msk (0x1FUL << MPU_RASR_SIZE_Pos) /*!< MPU RASR: Region Size Field Mask */ -#define MPU_RASR_ENABLE_Pos 0 /*!< MPU RASR: Region enable bit Position */ -#define MPU_RASR_ENABLE_Msk (1UL << MPU_RASR_ENABLE_Pos) /*!< MPU RASR: Region enable bit Disable Mask */ +#define MPU_RASR_ENABLE_Pos 0 /*!< MPU RASR: Region enable bit Position */ +#define MPU_RASR_ENABLE_Msk (1UL << MPU_RASR_ENABLE_Pos) /*!< MPU RASR: Region enable bit Disable Mask */ /*@} end of group CMSIS_MPU */ #endif - -/** \ingroup CMSIS_core_register + /** \ingroup CMSIS_core_register \defgroup CMSIS_CoreDebug Core Debug Registers (CoreDebug) \brief Type definitions for the Core Debug Registers @{ */ -/** \brief Structure type to access the Core Debug Register (CoreDebug). + /** \brief Structure type to access the Core Debug Register (CoreDebug). */ -typedef struct -{ - __IO uint32_t DHCSR; /*!< Offset: 0x000 (R/W) Debug Halting Control and Status Register */ - __O uint32_t DCRSR; /*!< Offset: 0x004 ( /W) Debug Core Register Selector Register */ - __IO uint32_t DCRDR; /*!< Offset: 0x008 (R/W) Debug Core Register Data Register */ - __IO uint32_t DEMCR; /*!< Offset: 0x00C (R/W) Debug Exception and Monitor Control Register */ -} CoreDebug_Type; + typedef struct + { + __IO uint32_t DHCSR; /*!< Offset: 0x000 (R/W) Debug Halting Control and Status Register */ + __O uint32_t DCRSR; /*!< Offset: 0x004 ( /W) Debug Core Register Selector Register */ + __IO uint32_t DCRDR; /*!< Offset: 0x008 (R/W) Debug Core Register Data Register */ + __IO uint32_t DEMCR; /*!< Offset: 0x00C (R/W) Debug Exception and Monitor Control Register */ + } CoreDebug_Type; /* Debug Halting Control and Status Register */ -#define CoreDebug_DHCSR_DBGKEY_Pos 16 /*!< CoreDebug DHCSR: DBGKEY Position */ -#define CoreDebug_DHCSR_DBGKEY_Msk (0xFFFFUL << CoreDebug_DHCSR_DBGKEY_Pos) /*!< CoreDebug DHCSR: DBGKEY Mask */ +#define CoreDebug_DHCSR_DBGKEY_Pos 16 /*!< CoreDebug DHCSR: DBGKEY Position */ +#define CoreDebug_DHCSR_DBGKEY_Msk (0xFFFFUL << CoreDebug_DHCSR_DBGKEY_Pos) /*!< CoreDebug DHCSR: DBGKEY Mask */ -#define CoreDebug_DHCSR_S_RESET_ST_Pos 25 /*!< CoreDebug DHCSR: S_RESET_ST Position */ -#define CoreDebug_DHCSR_S_RESET_ST_Msk (1UL << CoreDebug_DHCSR_S_RESET_ST_Pos) /*!< CoreDebug DHCSR: S_RESET_ST Mask */ +#define CoreDebug_DHCSR_S_RESET_ST_Pos 25 /*!< CoreDebug DHCSR: S_RESET_ST Position */ +#define CoreDebug_DHCSR_S_RESET_ST_Msk (1UL << CoreDebug_DHCSR_S_RESET_ST_Pos) /*!< CoreDebug DHCSR: S_RESET_ST Mask */ -#define CoreDebug_DHCSR_S_RETIRE_ST_Pos 24 /*!< CoreDebug DHCSR: S_RETIRE_ST Position */ -#define CoreDebug_DHCSR_S_RETIRE_ST_Msk (1UL << CoreDebug_DHCSR_S_RETIRE_ST_Pos) /*!< CoreDebug DHCSR: S_RETIRE_ST Mask */ +#define CoreDebug_DHCSR_S_RETIRE_ST_Pos 24 /*!< CoreDebug DHCSR: S_RETIRE_ST Position */ +#define CoreDebug_DHCSR_S_RETIRE_ST_Msk (1UL << CoreDebug_DHCSR_S_RETIRE_ST_Pos) /*!< CoreDebug DHCSR: S_RETIRE_ST Mask */ -#define CoreDebug_DHCSR_S_LOCKUP_Pos 19 /*!< CoreDebug DHCSR: S_LOCKUP Position */ -#define CoreDebug_DHCSR_S_LOCKUP_Msk (1UL << CoreDebug_DHCSR_S_LOCKUP_Pos) /*!< CoreDebug DHCSR: S_LOCKUP Mask */ +#define CoreDebug_DHCSR_S_LOCKUP_Pos 19 /*!< CoreDebug DHCSR: S_LOCKUP Position */ +#define CoreDebug_DHCSR_S_LOCKUP_Msk (1UL << CoreDebug_DHCSR_S_LOCKUP_Pos) /*!< CoreDebug DHCSR: S_LOCKUP Mask */ -#define CoreDebug_DHCSR_S_SLEEP_Pos 18 /*!< CoreDebug DHCSR: S_SLEEP Position */ -#define CoreDebug_DHCSR_S_SLEEP_Msk (1UL << CoreDebug_DHCSR_S_SLEEP_Pos) /*!< CoreDebug DHCSR: S_SLEEP Mask */ +#define CoreDebug_DHCSR_S_SLEEP_Pos 18 /*!< CoreDebug DHCSR: S_SLEEP Position */ +#define CoreDebug_DHCSR_S_SLEEP_Msk (1UL << CoreDebug_DHCSR_S_SLEEP_Pos) /*!< CoreDebug DHCSR: S_SLEEP Mask */ -#define CoreDebug_DHCSR_S_HALT_Pos 17 /*!< CoreDebug DHCSR: S_HALT Position */ -#define CoreDebug_DHCSR_S_HALT_Msk (1UL << CoreDebug_DHCSR_S_HALT_Pos) /*!< CoreDebug DHCSR: S_HALT Mask */ +#define CoreDebug_DHCSR_S_HALT_Pos 17 /*!< CoreDebug DHCSR: S_HALT Position */ +#define CoreDebug_DHCSR_S_HALT_Msk (1UL << CoreDebug_DHCSR_S_HALT_Pos) /*!< CoreDebug DHCSR: S_HALT Mask */ -#define CoreDebug_DHCSR_S_REGRDY_Pos 16 /*!< CoreDebug DHCSR: S_REGRDY Position */ -#define CoreDebug_DHCSR_S_REGRDY_Msk (1UL << CoreDebug_DHCSR_S_REGRDY_Pos) /*!< CoreDebug DHCSR: S_REGRDY Mask */ +#define CoreDebug_DHCSR_S_REGRDY_Pos 16 /*!< CoreDebug DHCSR: S_REGRDY Position */ +#define CoreDebug_DHCSR_S_REGRDY_Msk (1UL << CoreDebug_DHCSR_S_REGRDY_Pos) /*!< CoreDebug DHCSR: S_REGRDY Mask */ -#define CoreDebug_DHCSR_C_SNAPSTALL_Pos 5 /*!< CoreDebug DHCSR: C_SNAPSTALL Position */ -#define CoreDebug_DHCSR_C_SNAPSTALL_Msk (1UL << CoreDebug_DHCSR_C_SNAPSTALL_Pos) /*!< CoreDebug DHCSR: C_SNAPSTALL Mask */ +#define CoreDebug_DHCSR_C_SNAPSTALL_Pos 5 /*!< CoreDebug DHCSR: C_SNAPSTALL Position */ +#define CoreDebug_DHCSR_C_SNAPSTALL_Msk (1UL << CoreDebug_DHCSR_C_SNAPSTALL_Pos) /*!< CoreDebug DHCSR: C_SNAPSTALL Mask */ -#define CoreDebug_DHCSR_C_MASKINTS_Pos 3 /*!< CoreDebug DHCSR: C_MASKINTS Position */ -#define CoreDebug_DHCSR_C_MASKINTS_Msk (1UL << CoreDebug_DHCSR_C_MASKINTS_Pos) /*!< CoreDebug DHCSR: C_MASKINTS Mask */ +#define CoreDebug_DHCSR_C_MASKINTS_Pos 3 /*!< CoreDebug DHCSR: C_MASKINTS Position */ +#define CoreDebug_DHCSR_C_MASKINTS_Msk (1UL << CoreDebug_DHCSR_C_MASKINTS_Pos) /*!< CoreDebug DHCSR: C_MASKINTS Mask */ -#define CoreDebug_DHCSR_C_STEP_Pos 2 /*!< CoreDebug DHCSR: C_STEP Position */ -#define CoreDebug_DHCSR_C_STEP_Msk (1UL << CoreDebug_DHCSR_C_STEP_Pos) /*!< CoreDebug DHCSR: C_STEP Mask */ +#define CoreDebug_DHCSR_C_STEP_Pos 2 /*!< CoreDebug DHCSR: C_STEP Position */ +#define CoreDebug_DHCSR_C_STEP_Msk (1UL << CoreDebug_DHCSR_C_STEP_Pos) /*!< CoreDebug DHCSR: C_STEP Mask */ -#define CoreDebug_DHCSR_C_HALT_Pos 1 /*!< CoreDebug DHCSR: C_HALT Position */ -#define CoreDebug_DHCSR_C_HALT_Msk (1UL << CoreDebug_DHCSR_C_HALT_Pos) /*!< CoreDebug DHCSR: C_HALT Mask */ +#define CoreDebug_DHCSR_C_HALT_Pos 1 /*!< CoreDebug DHCSR: C_HALT Position */ +#define CoreDebug_DHCSR_C_HALT_Msk (1UL << CoreDebug_DHCSR_C_HALT_Pos) /*!< CoreDebug DHCSR: C_HALT Mask */ -#define CoreDebug_DHCSR_C_DEBUGEN_Pos 0 /*!< CoreDebug DHCSR: C_DEBUGEN Position */ -#define CoreDebug_DHCSR_C_DEBUGEN_Msk (1UL << CoreDebug_DHCSR_C_DEBUGEN_Pos) /*!< CoreDebug DHCSR: C_DEBUGEN Mask */ +#define CoreDebug_DHCSR_C_DEBUGEN_Pos 0 /*!< CoreDebug DHCSR: C_DEBUGEN Position */ +#define CoreDebug_DHCSR_C_DEBUGEN_Msk (1UL << CoreDebug_DHCSR_C_DEBUGEN_Pos) /*!< CoreDebug DHCSR: C_DEBUGEN Mask */ /* Debug Core Register Selector Register */ -#define CoreDebug_DCRSR_REGWnR_Pos 16 /*!< CoreDebug DCRSR: REGWnR Position */ -#define CoreDebug_DCRSR_REGWnR_Msk (1UL << CoreDebug_DCRSR_REGWnR_Pos) /*!< CoreDebug DCRSR: REGWnR Mask */ +#define CoreDebug_DCRSR_REGWnR_Pos 16 /*!< CoreDebug DCRSR: REGWnR Position */ +#define CoreDebug_DCRSR_REGWnR_Msk (1UL << CoreDebug_DCRSR_REGWnR_Pos) /*!< CoreDebug DCRSR: REGWnR Mask */ -#define CoreDebug_DCRSR_REGSEL_Pos 0 /*!< CoreDebug DCRSR: REGSEL Position */ -#define CoreDebug_DCRSR_REGSEL_Msk (0x1FUL << CoreDebug_DCRSR_REGSEL_Pos) /*!< CoreDebug DCRSR: REGSEL Mask */ +#define CoreDebug_DCRSR_REGSEL_Pos 0 /*!< CoreDebug DCRSR: REGSEL Position */ +#define CoreDebug_DCRSR_REGSEL_Msk (0x1FUL << CoreDebug_DCRSR_REGSEL_Pos) /*!< CoreDebug DCRSR: REGSEL Mask */ /* Debug Exception and Monitor Control Register */ -#define CoreDebug_DEMCR_TRCENA_Pos 24 /*!< CoreDebug DEMCR: TRCENA Position */ -#define CoreDebug_DEMCR_TRCENA_Msk (1UL << CoreDebug_DEMCR_TRCENA_Pos) /*!< CoreDebug DEMCR: TRCENA Mask */ +#define CoreDebug_DEMCR_TRCENA_Pos 24 /*!< CoreDebug DEMCR: TRCENA Position */ +#define CoreDebug_DEMCR_TRCENA_Msk (1UL << CoreDebug_DEMCR_TRCENA_Pos) /*!< CoreDebug DEMCR: TRCENA Mask */ -#define CoreDebug_DEMCR_MON_REQ_Pos 19 /*!< CoreDebug DEMCR: MON_REQ Position */ -#define CoreDebug_DEMCR_MON_REQ_Msk (1UL << CoreDebug_DEMCR_MON_REQ_Pos) /*!< CoreDebug DEMCR: MON_REQ Mask */ +#define CoreDebug_DEMCR_MON_REQ_Pos 19 /*!< CoreDebug DEMCR: MON_REQ Position */ +#define CoreDebug_DEMCR_MON_REQ_Msk (1UL << CoreDebug_DEMCR_MON_REQ_Pos) /*!< CoreDebug DEMCR: MON_REQ Mask */ -#define CoreDebug_DEMCR_MON_STEP_Pos 18 /*!< CoreDebug DEMCR: MON_STEP Position */ -#define CoreDebug_DEMCR_MON_STEP_Msk (1UL << CoreDebug_DEMCR_MON_STEP_Pos) /*!< CoreDebug DEMCR: MON_STEP Mask */ +#define CoreDebug_DEMCR_MON_STEP_Pos 18 /*!< CoreDebug DEMCR: MON_STEP Position */ +#define CoreDebug_DEMCR_MON_STEP_Msk (1UL << CoreDebug_DEMCR_MON_STEP_Pos) /*!< CoreDebug DEMCR: MON_STEP Mask */ -#define CoreDebug_DEMCR_MON_PEND_Pos 17 /*!< CoreDebug DEMCR: MON_PEND Position */ -#define CoreDebug_DEMCR_MON_PEND_Msk (1UL << CoreDebug_DEMCR_MON_PEND_Pos) /*!< CoreDebug DEMCR: MON_PEND Mask */ +#define CoreDebug_DEMCR_MON_PEND_Pos 17 /*!< CoreDebug DEMCR: MON_PEND Position */ +#define CoreDebug_DEMCR_MON_PEND_Msk (1UL << CoreDebug_DEMCR_MON_PEND_Pos) /*!< CoreDebug DEMCR: MON_PEND Mask */ -#define CoreDebug_DEMCR_MON_EN_Pos 16 /*!< CoreDebug DEMCR: MON_EN Position */ -#define CoreDebug_DEMCR_MON_EN_Msk (1UL << CoreDebug_DEMCR_MON_EN_Pos) /*!< CoreDebug DEMCR: MON_EN Mask */ +#define CoreDebug_DEMCR_MON_EN_Pos 16 /*!< CoreDebug DEMCR: MON_EN Position */ +#define CoreDebug_DEMCR_MON_EN_Msk (1UL << CoreDebug_DEMCR_MON_EN_Pos) /*!< CoreDebug DEMCR: MON_EN Mask */ -#define CoreDebug_DEMCR_VC_HARDERR_Pos 10 /*!< CoreDebug DEMCR: VC_HARDERR Position */ -#define CoreDebug_DEMCR_VC_HARDERR_Msk (1UL << CoreDebug_DEMCR_VC_HARDERR_Pos) /*!< CoreDebug DEMCR: VC_HARDERR Mask */ +#define CoreDebug_DEMCR_VC_HARDERR_Pos 10 /*!< CoreDebug DEMCR: VC_HARDERR Position */ +#define CoreDebug_DEMCR_VC_HARDERR_Msk (1UL << CoreDebug_DEMCR_VC_HARDERR_Pos) /*!< CoreDebug DEMCR: VC_HARDERR Mask */ -#define CoreDebug_DEMCR_VC_INTERR_Pos 9 /*!< CoreDebug DEMCR: VC_INTERR Position */ -#define CoreDebug_DEMCR_VC_INTERR_Msk (1UL << CoreDebug_DEMCR_VC_INTERR_Pos) /*!< CoreDebug DEMCR: VC_INTERR Mask */ +#define CoreDebug_DEMCR_VC_INTERR_Pos 9 /*!< CoreDebug DEMCR: VC_INTERR Position */ +#define CoreDebug_DEMCR_VC_INTERR_Msk (1UL << CoreDebug_DEMCR_VC_INTERR_Pos) /*!< CoreDebug DEMCR: VC_INTERR Mask */ -#define CoreDebug_DEMCR_VC_BUSERR_Pos 8 /*!< CoreDebug DEMCR: VC_BUSERR Position */ -#define CoreDebug_DEMCR_VC_BUSERR_Msk (1UL << CoreDebug_DEMCR_VC_BUSERR_Pos) /*!< CoreDebug DEMCR: VC_BUSERR Mask */ +#define CoreDebug_DEMCR_VC_BUSERR_Pos 8 /*!< CoreDebug DEMCR: VC_BUSERR Position */ +#define CoreDebug_DEMCR_VC_BUSERR_Msk (1UL << CoreDebug_DEMCR_VC_BUSERR_Pos) /*!< CoreDebug DEMCR: VC_BUSERR Mask */ -#define CoreDebug_DEMCR_VC_STATERR_Pos 7 /*!< CoreDebug DEMCR: VC_STATERR Position */ -#define CoreDebug_DEMCR_VC_STATERR_Msk (1UL << CoreDebug_DEMCR_VC_STATERR_Pos) /*!< CoreDebug DEMCR: VC_STATERR Mask */ +#define CoreDebug_DEMCR_VC_STATERR_Pos 7 /*!< CoreDebug DEMCR: VC_STATERR Position */ +#define CoreDebug_DEMCR_VC_STATERR_Msk (1UL << CoreDebug_DEMCR_VC_STATERR_Pos) /*!< CoreDebug DEMCR: VC_STATERR Mask */ -#define CoreDebug_DEMCR_VC_CHKERR_Pos 6 /*!< CoreDebug DEMCR: VC_CHKERR Position */ -#define CoreDebug_DEMCR_VC_CHKERR_Msk (1UL << CoreDebug_DEMCR_VC_CHKERR_Pos) /*!< CoreDebug DEMCR: VC_CHKERR Mask */ +#define CoreDebug_DEMCR_VC_CHKERR_Pos 6 /*!< CoreDebug DEMCR: VC_CHKERR Position */ +#define CoreDebug_DEMCR_VC_CHKERR_Msk (1UL << CoreDebug_DEMCR_VC_CHKERR_Pos) /*!< CoreDebug DEMCR: VC_CHKERR Mask */ -#define CoreDebug_DEMCR_VC_NOCPERR_Pos 5 /*!< CoreDebug DEMCR: VC_NOCPERR Position */ -#define CoreDebug_DEMCR_VC_NOCPERR_Msk (1UL << CoreDebug_DEMCR_VC_NOCPERR_Pos) /*!< CoreDebug DEMCR: VC_NOCPERR Mask */ +#define CoreDebug_DEMCR_VC_NOCPERR_Pos 5 /*!< CoreDebug DEMCR: VC_NOCPERR Position */ +#define CoreDebug_DEMCR_VC_NOCPERR_Msk (1UL << CoreDebug_DEMCR_VC_NOCPERR_Pos) /*!< CoreDebug DEMCR: VC_NOCPERR Mask */ -#define CoreDebug_DEMCR_VC_MMERR_Pos 4 /*!< CoreDebug DEMCR: VC_MMERR Position */ -#define CoreDebug_DEMCR_VC_MMERR_Msk (1UL << CoreDebug_DEMCR_VC_MMERR_Pos) /*!< CoreDebug DEMCR: VC_MMERR Mask */ +#define CoreDebug_DEMCR_VC_MMERR_Pos 4 /*!< CoreDebug DEMCR: VC_MMERR Position */ +#define CoreDebug_DEMCR_VC_MMERR_Msk (1UL << CoreDebug_DEMCR_VC_MMERR_Pos) /*!< CoreDebug DEMCR: VC_MMERR Mask */ -#define CoreDebug_DEMCR_VC_CORERESET_Pos 0 /*!< CoreDebug DEMCR: VC_CORERESET Position */ -#define CoreDebug_DEMCR_VC_CORERESET_Msk (1UL << CoreDebug_DEMCR_VC_CORERESET_Pos) /*!< CoreDebug DEMCR: VC_CORERESET Mask */ +#define CoreDebug_DEMCR_VC_CORERESET_Pos 0 /*!< CoreDebug DEMCR: VC_CORERESET Position */ +#define CoreDebug_DEMCR_VC_CORERESET_Msk (1UL << CoreDebug_DEMCR_VC_CORERESET_Pos) /*!< CoreDebug DEMCR: VC_CORERESET Mask */ /*@} end of group CMSIS_CoreDebug */ - /** \ingroup CMSIS_core_register \defgroup CMSIS_core_base Core Definitions \brief Definitions for base addresses, unions, and structures. @@ -1251,34 +1235,32 @@ typedef struct */ /* Memory mapping of Cortex-M3 Hardware */ -#define SCS_BASE (0xE000E000UL) /*!< System Control Space Base Address */ -#define ITM_BASE (0xE0000000UL) /*!< ITM Base Address */ -#define DWT_BASE (0xE0001000UL) /*!< DWT Base Address */ -#define TPI_BASE (0xE0040000UL) /*!< TPI Base Address */ -#define CoreDebug_BASE (0xE000EDF0UL) /*!< Core Debug Base Address */ -#define SysTick_BASE (SCS_BASE + 0x0010UL) /*!< SysTick Base Address */ -#define NVIC_BASE (SCS_BASE + 0x0100UL) /*!< NVIC Base Address */ -#define SCB_BASE (SCS_BASE + 0x0D00UL) /*!< System Control Block Base Address */ +#define SCS_BASE (0xE000E000UL) /*!< System Control Space Base Address */ +#define ITM_BASE (0xE0000000UL) /*!< ITM Base Address */ +#define DWT_BASE (0xE0001000UL) /*!< DWT Base Address */ +#define TPI_BASE (0xE0040000UL) /*!< TPI Base Address */ +#define CoreDebug_BASE (0xE000EDF0UL) /*!< Core Debug Base Address */ +#define SysTick_BASE (SCS_BASE + 0x0010UL) /*!< SysTick Base Address */ +#define NVIC_BASE (SCS_BASE + 0x0100UL) /*!< NVIC Base Address */ +#define SCB_BASE (SCS_BASE + 0x0D00UL) /*!< System Control Block Base Address */ -#define SCnSCB ((SCnSCB_Type *) SCS_BASE ) /*!< System control Register not in SCB */ -#define SCB ((SCB_Type *) SCB_BASE ) /*!< SCB configuration struct */ -#define SysTick ((SysTick_Type *) SysTick_BASE ) /*!< SysTick configuration struct */ -#define NVIC ((NVIC_Type *) NVIC_BASE ) /*!< NVIC configuration struct */ -#define ITM ((ITM_Type *) ITM_BASE ) /*!< ITM configuration struct */ -#define DWT ((DWT_Type *) DWT_BASE ) /*!< DWT configuration struct */ -#define TPI ((TPI_Type *) TPI_BASE ) /*!< TPI configuration struct */ -#define CoreDebug ((CoreDebug_Type *) CoreDebug_BASE) /*!< Core Debug configuration struct */ +#define SCnSCB ((SCnSCB_Type *)SCS_BASE) /*!< System control Register not in SCB */ +#define SCB ((SCB_Type *)SCB_BASE) /*!< SCB configuration struct */ +#define SysTick ((SysTick_Type *)SysTick_BASE) /*!< SysTick configuration struct */ +#define NVIC ((NVIC_Type *)NVIC_BASE) /*!< NVIC configuration struct */ +#define ITM ((ITM_Type *)ITM_BASE) /*!< ITM configuration struct */ +#define DWT ((DWT_Type *)DWT_BASE) /*!< DWT configuration struct */ +#define TPI ((TPI_Type *)TPI_BASE) /*!< TPI configuration struct */ +#define CoreDebug ((CoreDebug_Type *)CoreDebug_BASE) /*!< Core Debug configuration struct */ #if (__MPU_PRESENT == 1) - #define MPU_BASE (SCS_BASE + 0x0D90UL) /*!< Memory Protection Unit */ - #define MPU ((MPU_Type *) MPU_BASE ) /*!< Memory Protection Unit */ +#define MPU_BASE (SCS_BASE + 0x0D90UL) /*!< Memory Protection Unit */ +#define MPU ((MPU_Type *)MPU_BASE) /*!< Memory Protection Unit */ #endif -/*@} */ - + /*@} */ - -/******************************************************************************* + /******************************************************************************* * Hardware Abstraction Layer Core Function Interface contains: - Core NVIC Functions @@ -1286,19 +1268,17 @@ typedef struct - Core Debug Functions - Core Register Access Functions ******************************************************************************/ -/** \defgroup CMSIS_Core_FunctionInterface Functions and Instructions Reference + /** \defgroup CMSIS_Core_FunctionInterface Functions and Instructions Reference */ - - -/* ########################## NVIC functions #################################### */ -/** \ingroup CMSIS_Core_FunctionInterface + /* ########################## NVIC functions #################################### */ + /** \ingroup CMSIS_Core_FunctionInterface \defgroup CMSIS_Core_NVICFunctions NVIC Functions \brief Functions that manage interrupts and exceptions via the NVIC. @{ */ -/** \brief Set Priority Grouping + /** \brief Set Priority Grouping The function sets the priority grouping field using the required unlock sequence. The parameter PriorityGroup is assigned to the field SCB->AIRCR [10:8] PRIGROUP field. @@ -1308,57 +1288,53 @@ typedef struct \param [in] PriorityGroup Priority grouping field. */ -__STATIC_INLINE void NVIC_SetPriorityGrouping(uint32_t PriorityGroup) -{ - uint32_t reg_value; - uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07); /* only values 0..7 are used */ + __STATIC_INLINE void NVIC_SetPriorityGrouping(uint32_t PriorityGroup) + { + uint32_t reg_value; + uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07); /* only values 0..7 are used */ - reg_value = SCB->AIRCR; /* read old register configuration */ - reg_value &= ~(SCB_AIRCR_VECTKEY_Msk | SCB_AIRCR_PRIGROUP_Msk); /* clear bits to change */ - reg_value = (reg_value | - ((uint32_t)0x5FA << SCB_AIRCR_VECTKEY_Pos) | - (PriorityGroupTmp << 8)); /* Insert write key and priorty group */ - SCB->AIRCR = reg_value; -} + reg_value = SCB->AIRCR; /* read old register configuration */ + reg_value &= ~(SCB_AIRCR_VECTKEY_Msk | SCB_AIRCR_PRIGROUP_Msk); /* clear bits to change */ + reg_value = (reg_value | + ((uint32_t)0x5FA << SCB_AIRCR_VECTKEY_Pos) | + (PriorityGroupTmp << 8)); /* Insert write key and priorty group */ + SCB->AIRCR = reg_value; + } - -/** \brief Get Priority Grouping + /** \brief Get Priority Grouping The function reads the priority grouping field from the NVIC Interrupt Controller. \return Priority grouping field (SCB->AIRCR [10:8] PRIGROUP field). */ -__STATIC_INLINE uint32_t NVIC_GetPriorityGrouping(void) -{ - return ((SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) >> SCB_AIRCR_PRIGROUP_Pos); /* read priority grouping field */ -} - + __STATIC_INLINE uint32_t NVIC_GetPriorityGrouping(void) + { + return ((SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) >> SCB_AIRCR_PRIGROUP_Pos); /* read priority grouping field */ + } -/** \brief Enable External Interrupt + /** \brief Enable External Interrupt The function enables a device-specific interrupt in the NVIC interrupt controller. \param [in] IRQn External interrupt number. Value cannot be negative. */ -__STATIC_INLINE void NVIC_EnableIRQ(IRQn_Type IRQn) -{ - NVIC->ISER[((uint32_t)(IRQn) >> 5)] = (1 << ((uint32_t)(IRQn) & 0x1F)); /* enable interrupt */ -} - + __STATIC_INLINE void NVIC_EnableIRQ(IRQn_Type IRQn) + { + NVIC->ISER[((uint32_t)(IRQn) >> 5)] = (1 << ((uint32_t)(IRQn)&0x1F)); /* enable interrupt */ + } -/** \brief Disable External Interrupt + /** \brief Disable External Interrupt The function disables a device-specific interrupt in the NVIC interrupt controller. \param [in] IRQn External interrupt number. Value cannot be negative. */ -__STATIC_INLINE void NVIC_DisableIRQ(IRQn_Type IRQn) -{ - NVIC->ICER[((uint32_t)(IRQn) >> 5)] = (1 << ((uint32_t)(IRQn) & 0x1F)); /* disable interrupt */ -} - + __STATIC_INLINE void NVIC_DisableIRQ(IRQn_Type IRQn) + { + NVIC->ICER[((uint32_t)(IRQn) >> 5)] = (1 << ((uint32_t)(IRQn)&0x1F)); /* disable interrupt */ + } -/** \brief Get Pending Interrupt + /** \brief Get Pending Interrupt The function reads the pending register in the NVIC and returns the pending bit for the specified interrupt. @@ -1368,37 +1344,34 @@ __STATIC_INLINE void NVIC_DisableIRQ(IRQn_Type IRQn) \return 0 Interrupt status is not pending. \return 1 Interrupt status is pending. */ -__STATIC_INLINE uint32_t NVIC_GetPendingIRQ(IRQn_Type IRQn) -{ - return((uint32_t) ((NVIC->ISPR[(uint32_t)(IRQn) >> 5] & (1 << ((uint32_t)(IRQn) & 0x1F)))?1:0)); /* Return 1 if pending else 0 */ -} - + __STATIC_INLINE uint32_t NVIC_GetPendingIRQ(IRQn_Type IRQn) + { + return ((uint32_t)((NVIC->ISPR[(uint32_t)(IRQn) >> 5] & (1 << ((uint32_t)(IRQn)&0x1F))) ? 1 : 0)); /* Return 1 if pending else 0 */ + } -/** \brief Set Pending Interrupt + /** \brief Set Pending Interrupt The function sets the pending bit of an external interrupt. \param [in] IRQn Interrupt number. Value cannot be negative. */ -__STATIC_INLINE void NVIC_SetPendingIRQ(IRQn_Type IRQn) -{ - NVIC->ISPR[((uint32_t)(IRQn) >> 5)] = (1 << ((uint32_t)(IRQn) & 0x1F)); /* set interrupt pending */ -} + __STATIC_INLINE void NVIC_SetPendingIRQ(IRQn_Type IRQn) + { + NVIC->ISPR[((uint32_t)(IRQn) >> 5)] = (1 << ((uint32_t)(IRQn)&0x1F)); /* set interrupt pending */ + } - -/** \brief Clear Pending Interrupt + /** \brief Clear Pending Interrupt The function clears the pending bit of an external interrupt. \param [in] IRQn External interrupt number. Value cannot be negative. */ -__STATIC_INLINE void NVIC_ClearPendingIRQ(IRQn_Type IRQn) -{ - NVIC->ICPR[((uint32_t)(IRQn) >> 5)] = (1 << ((uint32_t)(IRQn) & 0x1F)); /* Clear pending interrupt */ -} - + __STATIC_INLINE void NVIC_ClearPendingIRQ(IRQn_Type IRQn) + { + NVIC->ICPR[((uint32_t)(IRQn) >> 5)] = (1 << ((uint32_t)(IRQn)&0x1F)); /* Clear pending interrupt */ + } -/** \brief Get Active Interrupt + /** \brief Get Active Interrupt The function reads the active register in NVIC and returns the active bit. @@ -1407,13 +1380,12 @@ __STATIC_INLINE void NVIC_ClearPendingIRQ(IRQn_Type IRQn) \return 0 Interrupt status is not active. \return 1 Interrupt status is active. */ -__STATIC_INLINE uint32_t NVIC_GetActive(IRQn_Type IRQn) -{ - return((uint32_t)((NVIC->IABR[(uint32_t)(IRQn) >> 5] & (1 << ((uint32_t)(IRQn) & 0x1F)))?1:0)); /* Return 1 if active else 0 */ -} - + __STATIC_INLINE uint32_t NVIC_GetActive(IRQn_Type IRQn) + { + return ((uint32_t)((NVIC->IABR[(uint32_t)(IRQn) >> 5] & (1 << ((uint32_t)(IRQn)&0x1F))) ? 1 : 0)); /* Return 1 if active else 0 */ + } -/** \brief Set Interrupt Priority + /** \brief Set Interrupt Priority The function sets the priority of an interrupt. @@ -1422,16 +1394,19 @@ __STATIC_INLINE uint32_t NVIC_GetActive(IRQn_Type IRQn) \param [in] IRQn Interrupt number. \param [in] priority Priority to set. */ -__STATIC_INLINE void NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority) -{ - if(IRQn < 0) { - SCB->SHP[((uint32_t)(IRQn) & 0xF)-4] = ((priority << (8 - __NVIC_PRIO_BITS)) & 0xff); } /* set Priority for Cortex-M System Interrupts */ - else { - NVIC->IP[(uint32_t)(IRQn)] = ((priority << (8 - __NVIC_PRIO_BITS)) & 0xff); } /* set Priority for device specific Interrupts */ -} - + __STATIC_INLINE void NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority) + { + if (IRQn < 0) + { + SCB->SHP[((uint32_t)(IRQn)&0xF) - 4] = ((priority << (8 - __NVIC_PRIO_BITS)) & 0xff); + } /* set Priority for Cortex-M System Interrupts */ + else + { + NVIC->IP[(uint32_t)(IRQn)] = ((priority << (8 - __NVIC_PRIO_BITS)) & 0xff); + } /* set Priority for device specific Interrupts */ + } -/** \brief Get Interrupt Priority + /** \brief Get Interrupt Priority The function reads the priority of an interrupt. The interrupt number can be positive to specify an external (device specific) @@ -1442,17 +1417,20 @@ __STATIC_INLINE void NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority) \return Interrupt Priority. Value is aligned automatically to the implemented priority bits of the microcontroller. */ -__STATIC_INLINE uint32_t NVIC_GetPriority(IRQn_Type IRQn) -{ - - if(IRQn < 0) { - return((uint32_t)(SCB->SHP[((uint32_t)(IRQn) & 0xF)-4] >> (8 - __NVIC_PRIO_BITS))); } /* get priority for Cortex-M system interrupts */ - else { - return((uint32_t)(NVIC->IP[(uint32_t)(IRQn)] >> (8 - __NVIC_PRIO_BITS))); } /* get priority for device specific interrupts */ -} + __STATIC_INLINE uint32_t NVIC_GetPriority(IRQn_Type IRQn) + { + if (IRQn < 0) + { + return ((uint32_t)(SCB->SHP[((uint32_t)(IRQn)&0xF) - 4] >> (8 - __NVIC_PRIO_BITS))); + } /* get priority for Cortex-M system interrupts */ + else + { + return ((uint32_t)(NVIC->IP[(uint32_t)(IRQn)] >> (8 - __NVIC_PRIO_BITS))); + } /* get priority for device specific interrupts */ + } -/** \brief Encode Priority + /** \brief Encode Priority The function encodes the priority for an interrupt with the given priority group, preemptive priority value, and subpriority value. @@ -1464,23 +1442,21 @@ __STATIC_INLINE uint32_t NVIC_GetPriority(IRQn_Type IRQn) \param [in] SubPriority Subpriority value (starting from 0). \return Encoded priority. Value can be used in the function \ref NVIC_SetPriority(). */ -__STATIC_INLINE uint32_t NVIC_EncodePriority (uint32_t PriorityGroup, uint32_t PreemptPriority, uint32_t SubPriority) -{ - uint32_t PriorityGroupTmp = (PriorityGroup & 0x07); /* only values 0..7 are used */ - uint32_t PreemptPriorityBits; - uint32_t SubPriorityBits; + __STATIC_INLINE uint32_t NVIC_EncodePriority(uint32_t PriorityGroup, uint32_t PreemptPriority, uint32_t SubPriority) + { + uint32_t PriorityGroupTmp = (PriorityGroup & 0x07); /* only values 0..7 are used */ + uint32_t PreemptPriorityBits; + uint32_t SubPriorityBits; - PreemptPriorityBits = ((7 - PriorityGroupTmp) > __NVIC_PRIO_BITS) ? __NVIC_PRIO_BITS : 7 - PriorityGroupTmp; - SubPriorityBits = ((PriorityGroupTmp + __NVIC_PRIO_BITS) < 7) ? 0 : PriorityGroupTmp - 7 + __NVIC_PRIO_BITS; + PreemptPriorityBits = ((7 - PriorityGroupTmp) > __NVIC_PRIO_BITS) ? __NVIC_PRIO_BITS : 7 - PriorityGroupTmp; + SubPriorityBits = ((PriorityGroupTmp + __NVIC_PRIO_BITS) < 7) ? 0 : PriorityGroupTmp - 7 + __NVIC_PRIO_BITS; - return ( - ((PreemptPriority & ((1 << (PreemptPriorityBits)) - 1)) << SubPriorityBits) | - ((SubPriority & ((1 << (SubPriorityBits )) - 1))) - ); -} + return ( + ((PreemptPriority & ((1 << (PreemptPriorityBits)) - 1)) << SubPriorityBits) | + ((SubPriority & ((1 << (SubPriorityBits)) - 1)))); + } - -/** \brief Decode Priority + /** \brief Decode Priority The function decodes an interrupt priority value with a given priority group to preemptive priority value and subpriority value. @@ -1492,41 +1468,39 @@ __STATIC_INLINE uint32_t NVIC_EncodePriority (uint32_t PriorityGroup, uint32_t P \param [out] pPreemptPriority Preemptive priority value (starting from 0). \param [out] pSubPriority Subpriority value (starting from 0). */ -__STATIC_INLINE void NVIC_DecodePriority (uint32_t Priority, uint32_t PriorityGroup, uint32_t* pPreemptPriority, uint32_t* pSubPriority) -{ - uint32_t PriorityGroupTmp = (PriorityGroup & 0x07); /* only values 0..7 are used */ - uint32_t PreemptPriorityBits; - uint32_t SubPriorityBits; + __STATIC_INLINE void NVIC_DecodePriority(uint32_t Priority, uint32_t PriorityGroup, uint32_t *pPreemptPriority, uint32_t *pSubPriority) + { + uint32_t PriorityGroupTmp = (PriorityGroup & 0x07); /* only values 0..7 are used */ + uint32_t PreemptPriorityBits; + uint32_t SubPriorityBits; - PreemptPriorityBits = ((7 - PriorityGroupTmp) > __NVIC_PRIO_BITS) ? __NVIC_PRIO_BITS : 7 - PriorityGroupTmp; - SubPriorityBits = ((PriorityGroupTmp + __NVIC_PRIO_BITS) < 7) ? 0 : PriorityGroupTmp - 7 + __NVIC_PRIO_BITS; + PreemptPriorityBits = ((7 - PriorityGroupTmp) > __NVIC_PRIO_BITS) ? __NVIC_PRIO_BITS : 7 - PriorityGroupTmp; + SubPriorityBits = ((PriorityGroupTmp + __NVIC_PRIO_BITS) < 7) ? 0 : PriorityGroupTmp - 7 + __NVIC_PRIO_BITS; - *pPreemptPriority = (Priority >> SubPriorityBits) & ((1 << (PreemptPriorityBits)) - 1); - *pSubPriority = (Priority ) & ((1 << (SubPriorityBits )) - 1); -} + *pPreemptPriority = (Priority >> SubPriorityBits) & ((1 << (PreemptPriorityBits)) - 1); + *pSubPriority = (Priority) & ((1 << (SubPriorityBits)) - 1); + } - -/** \brief System Reset + /** \brief System Reset The function initiates a system reset request to reset the MCU. */ -__STATIC_INLINE void NVIC_SystemReset(void) -{ - __DSB(); /* Ensure all outstanding memory accesses included + __STATIC_INLINE void NVIC_SystemReset(void) + { + __DSB(); /* Ensure all outstanding memory accesses included buffered write are completed before reset */ - SCB->AIRCR = ((0x5FA << SCB_AIRCR_VECTKEY_Pos) | - (SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) | - SCB_AIRCR_SYSRESETREQ_Msk); /* Keep priority group unchanged */ - __DSB(); /* Ensure completion of memory access */ - while(1); /* wait until reset */ -} + SCB->AIRCR = ((0x5FA << SCB_AIRCR_VECTKEY_Pos) | + (SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) | + SCB_AIRCR_SYSRESETREQ_Msk); /* Keep priority group unchanged */ + __DSB(); /* Ensure completion of memory access */ + while (1) + ; /* wait until reset */ + } -/*@} end of CMSIS_Core_NVICFunctions */ + /*@} end of CMSIS_Core_NVICFunctions */ - - -/* ################################## SysTick function ############################################ */ -/** \ingroup CMSIS_Core_FunctionInterface + /* ################################## SysTick function ############################################ */ + /** \ingroup CMSIS_Core_FunctionInterface \defgroup CMSIS_Core_SysTickFunctions SysTick Functions \brief Functions that configure the System. @{ @@ -1534,7 +1508,7 @@ __STATIC_INLINE void NVIC_SystemReset(void) #if (__Vendor_SysTickConfig == 0) -/** \brief System Tick Configuration + /** \brief System Tick Configuration The function initializes the System Timer and its interrupt, and starts the System Tick Timer. Counter is in free running mode to generate periodic interrupts. @@ -1549,37 +1523,35 @@ __STATIC_INLINE void NVIC_SystemReset(void) must contain a vendor-specific implementation of this function. */ -__STATIC_INLINE uint32_t SysTick_Config(uint32_t ticks) -{ - if ((ticks - 1) > SysTick_LOAD_RELOAD_Msk) return (1); /* Reload value impossible */ + __STATIC_INLINE uint32_t SysTick_Config(uint32_t ticks) + { + if ((ticks - 1) > SysTick_LOAD_RELOAD_Msk) + return (1); /* Reload value impossible */ - SysTick->LOAD = ticks - 1; /* set reload register */ - NVIC_SetPriority (SysTick_IRQn, (1<<__NVIC_PRIO_BITS) - 1); /* set Priority for Systick Interrupt */ - SysTick->VAL = 0; /* Load the SysTick Counter Value */ - SysTick->CTRL = SysTick_CTRL_CLKSOURCE_Msk | - SysTick_CTRL_TICKINT_Msk | - SysTick_CTRL_ENABLE_Msk; /* Enable SysTick IRQ and SysTick Timer */ - return (0); /* Function successful */ -} + SysTick->LOAD = ticks - 1; /* set reload register */ + NVIC_SetPriority(SysTick_IRQn, (1 << __NVIC_PRIO_BITS) - 1); /* set Priority for Systick Interrupt */ + SysTick->VAL = 0; /* Load the SysTick Counter Value */ + SysTick->CTRL = SysTick_CTRL_CLKSOURCE_Msk | + SysTick_CTRL_TICKINT_Msk | + SysTick_CTRL_ENABLE_Msk; /* Enable SysTick IRQ and SysTick Timer */ + return (0); /* Function successful */ + } #endif -/*@} end of CMSIS_Core_SysTickFunctions */ - + /*@} end of CMSIS_Core_SysTickFunctions */ - -/* ##################################### Debug In/Output function ########################################### */ -/** \ingroup CMSIS_Core_FunctionInterface + /* ##################################### Debug In/Output function ########################################### */ + /** \ingroup CMSIS_Core_FunctionInterface \defgroup CMSIS_core_DebugFunctions ITM Functions \brief Functions that access the ITM debug interface. @{ */ -extern volatile int32_t ITM_RxBuffer; /*!< External variable to receive characters. */ -#define ITM_RXBUFFER_EMPTY 0x5AA55AA5 /*!< Value identifying \ref ITM_RxBuffer is ready for next character. */ - + extern volatile int32_t ITM_RxBuffer; /*!< External variable to receive characters. */ +#define ITM_RXBUFFER_EMPTY 0x5AA55AA5 /*!< Value identifying \ref ITM_RxBuffer is ready for next character. */ -/** \brief ITM Send Character + /** \brief ITM Send Character The function transmits a character via the ITM channel 0, and \li Just returns when no debugger is connected that has booked the output. @@ -1589,57 +1561,59 @@ extern volatile int32_t ITM_RxBuffer; /*!< External variable \returns Character to transmit. */ -__STATIC_INLINE uint32_t ITM_SendChar (uint32_t ch) -{ - if ((ITM->TCR & ITM_TCR_ITMENA_Msk) && /* ITM enabled */ - (ITM->TER & (1UL << 0) ) ) /* ITM Port #0 enabled */ - { - while (ITM->PORT[0].u32 == 0); - ITM->PORT[0].u8 = (uint8_t) ch; - } - return (ch); -} - + __STATIC_INLINE uint32_t ITM_SendChar(uint32_t ch) + { + if ((ITM->TCR & ITM_TCR_ITMENA_Msk) && /* ITM enabled */ + (ITM->TER & (1UL << 0))) /* ITM Port #0 enabled */ + { + while (ITM->PORT[0].u32 == 0) + ; + ITM->PORT[0].u8 = (uint8_t)ch; + } + return (ch); + } -/** \brief ITM Receive Character + /** \brief ITM Receive Character The function inputs a character via the external variable \ref ITM_RxBuffer. \return Received character. \return -1 No character pending. */ -__STATIC_INLINE int32_t ITM_ReceiveChar (void) { - int32_t ch = -1; /* no character available */ + __STATIC_INLINE int32_t ITM_ReceiveChar(void) + { + int32_t ch = -1; /* no character available */ - if (ITM_RxBuffer != ITM_RXBUFFER_EMPTY) { - ch = ITM_RxBuffer; - ITM_RxBuffer = ITM_RXBUFFER_EMPTY; /* ready for next character */ - } - - return (ch); -} + if (ITM_RxBuffer != ITM_RXBUFFER_EMPTY) + { + ch = ITM_RxBuffer; + ITM_RxBuffer = ITM_RXBUFFER_EMPTY; /* ready for next character */ + } + return (ch); + } -/** \brief ITM Check Character + /** \brief ITM Check Character The function checks whether a character is pending for reading in the variable \ref ITM_RxBuffer. \return 0 No character available. \return 1 Character available. */ -__STATIC_INLINE int32_t ITM_CheckChar (void) { - - if (ITM_RxBuffer == ITM_RXBUFFER_EMPTY) { - return (0); /* no character available */ - } else { - return (1); /* character available */ - } -} - -/*@} end of CMSIS_core_DebugFunctions */ - + __STATIC_INLINE int32_t ITM_CheckChar(void) + { + if (ITM_RxBuffer == ITM_RXBUFFER_EMPTY) + { + return (0); /* no character available */ + } + else + { + return (1); /* character available */ + } + } + /*@} end of CMSIS_core_DebugFunctions */ #ifdef __cplusplus } diff --git a/bsp/swm320-lq100/Libraries/CMSIS/CoreSupport/core_cm4.h b/bsp/swm320-lq100/Libraries/CMSIS/CoreSupport/core_cm4.h index bb6be1305d..178cf5b3ea 100644 --- a/bsp/swm320-lq100/Libraries/CMSIS/CoreSupport/core_cm4.h +++ b/bsp/swm320-lq100/Libraries/CMSIS/CoreSupport/core_cm4.h @@ -1,4 +1,4 @@ -/**************************************************************************//** +/**************************************************************************/ /** * @file core_cm4.h * @brief CMSIS Cortex-M4 Core Peripheral Access Layer Header File * @version V4.00 @@ -34,16 +34,16 @@ POSSIBILITY OF SUCH DAMAGE. ---------------------------------------------------------------------------*/ - -#if defined ( __ICCARM__ ) - #pragma system_include /* treat file as system include file for MISRA check */ +#if defined(__ICCARM__) +#pragma system_include /* treat file as system include file for MISRA check */ #endif #ifndef __CORE_CM4_H_GENERIC #define __CORE_CM4_H_GENERIC #ifdef __cplusplus - extern "C" { +extern "C" +{ #endif /** \page CMSIS_MISRA_Exceptions MISRA-C:2004 Compliance Exceptions @@ -59,7 +59,6 @@ Function-like macros are used to allow more efficient code. */ - /******************************************************************************* * CMSIS definitions ******************************************************************************/ @@ -68,126 +67,125 @@ */ /* CMSIS CM4 definitions */ -#define __CM4_CMSIS_VERSION_MAIN (0x04) /*!< [31:16] CMSIS HAL main version */ -#define __CM4_CMSIS_VERSION_SUB (0x00) /*!< [15:0] CMSIS HAL sub version */ -#define __CM4_CMSIS_VERSION ((__CM4_CMSIS_VERSION_MAIN << 16) | \ - __CM4_CMSIS_VERSION_SUB ) /*!< CMSIS HAL version number */ +#define __CM4_CMSIS_VERSION_MAIN (0x04) /*!< [31:16] CMSIS HAL main version */ +#define __CM4_CMSIS_VERSION_SUB (0x00) /*!< [15:0] CMSIS HAL sub version */ +#define __CM4_CMSIS_VERSION ((__CM4_CMSIS_VERSION_MAIN << 16) | \ + __CM4_CMSIS_VERSION_SUB) /*!< CMSIS HAL version number */ -#define __CORTEX_M (0x04) /*!< Cortex-M Core */ +#define __CORTEX_M (0x04) /*!< Cortex-M Core */ +#if defined(__CC_ARM) +#define __ASM __asm /*!< asm keyword for ARM Compiler */ +#define __INLINE __inline /*!< inline keyword for ARM Compiler */ +#define __STATIC_INLINE static __inline -#if defined ( __CC_ARM ) - #define __ASM __asm /*!< asm keyword for ARM Compiler */ - #define __INLINE __inline /*!< inline keyword for ARM Compiler */ - #define __STATIC_INLINE static __inline +#elif defined(__GNUC__) +#define __ASM __asm /*!< asm keyword for GNU Compiler */ +#define __INLINE inline /*!< inline keyword for GNU Compiler */ +#define __STATIC_INLINE static inline -#elif defined ( __GNUC__ ) - #define __ASM __asm /*!< asm keyword for GNU Compiler */ - #define __INLINE inline /*!< inline keyword for GNU Compiler */ - #define __STATIC_INLINE static inline +#elif defined(__ICCARM__) +#define __ASM __asm /*!< asm keyword for IAR Compiler */ +#define __INLINE inline /*!< inline keyword for IAR Compiler. Only available in High optimization mode! */ +#define __STATIC_INLINE static inline -#elif defined ( __ICCARM__ ) - #define __ASM __asm /*!< asm keyword for IAR Compiler */ - #define __INLINE inline /*!< inline keyword for IAR Compiler. Only available in High optimization mode! */ - #define __STATIC_INLINE static inline +#elif defined(__TMS470__) +#define __ASM __asm /*!< asm keyword for TI CCS Compiler */ +#define __STATIC_INLINE static inline -#elif defined ( __TMS470__ ) - #define __ASM __asm /*!< asm keyword for TI CCS Compiler */ - #define __STATIC_INLINE static inline +#elif defined(__TASKING__) +#define __ASM __asm /*!< asm keyword for TASKING Compiler */ +#define __INLINE inline /*!< inline keyword for TASKING Compiler */ +#define __STATIC_INLINE static inline -#elif defined ( __TASKING__ ) - #define __ASM __asm /*!< asm keyword for TASKING Compiler */ - #define __INLINE inline /*!< inline keyword for TASKING Compiler */ - #define __STATIC_INLINE static inline - -#elif defined ( __CSMC__ ) - #define __packed - #define __ASM _asm /*!< asm keyword for COSMIC Compiler */ - #define __INLINE inline /*use -pc99 on compile line !< inline keyword for COSMIC Compiler */ - #define __STATIC_INLINE static inline +#elif defined(__CSMC__) +#define __packed +#define __ASM _asm /*!< asm keyword for COSMIC Compiler */ +#define __INLINE inline /*use -pc99 on compile line !< inline keyword for COSMIC Compiler */ +#define __STATIC_INLINE static inline #endif /** __FPU_USED indicates whether an FPU is used or not. For this, __FPU_PRESENT has to be checked prior to making use of FPU specific registers and functions. */ -#if defined ( __CC_ARM ) - #if defined __TARGET_FPU_VFP - #if (__FPU_PRESENT == 1) - #define __FPU_USED 1 - #else - #warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" - #define __FPU_USED 0 - #endif - #else - #define __FPU_USED 0 - #endif +#if defined(__CC_ARM) +#if defined __TARGET_FPU_VFP +#if (__FPU_PRESENT == 1) +#define __FPU_USED 1 +#else +#warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" +#define __FPU_USED 0 +#endif +#else +#define __FPU_USED 0 +#endif -#elif defined ( __GNUC__ ) - #if defined (__VFP_FP__) && !defined(__SOFTFP__) - #if (__FPU_PRESENT == 1) - #define __FPU_USED 1 - #else - #warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" - #define __FPU_USED 0 - #endif - #else - #define __FPU_USED 0 - #endif +#elif defined(__GNUC__) +#if defined(__VFP_FP__) && !defined(__SOFTFP__) +#if (__FPU_PRESENT == 1) +#define __FPU_USED 1 +#else +#warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" +#define __FPU_USED 0 +#endif +#else +#define __FPU_USED 0 +#endif -#elif defined ( __ICCARM__ ) - #if defined __ARMVFP__ - #if (__FPU_PRESENT == 1) - #define __FPU_USED 1 - #else - #warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" - #define __FPU_USED 0 - #endif - #else - #define __FPU_USED 0 - #endif +#elif defined(__ICCARM__) +#if defined __ARMVFP__ +#if (__FPU_PRESENT == 1) +#define __FPU_USED 1 +#else +#warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" +#define __FPU_USED 0 +#endif +#else +#define __FPU_USED 0 +#endif -#elif defined ( __TMS470__ ) - #if defined __TI_VFP_SUPPORT__ - #if (__FPU_PRESENT == 1) - #define __FPU_USED 1 - #else - #warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" - #define __FPU_USED 0 - #endif - #else - #define __FPU_USED 0 - #endif +#elif defined(__TMS470__) +#if defined __TI_VFP_SUPPORT__ +#if (__FPU_PRESENT == 1) +#define __FPU_USED 1 +#else +#warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" +#define __FPU_USED 0 +#endif +#else +#define __FPU_USED 0 +#endif -#elif defined ( __TASKING__ ) - #if defined __FPU_VFP__ - #if (__FPU_PRESENT == 1) - #define __FPU_USED 1 - #else - #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" - #define __FPU_USED 0 - #endif - #else - #define __FPU_USED 0 - #endif +#elif defined(__TASKING__) +#if defined __FPU_VFP__ +#if (__FPU_PRESENT == 1) +#define __FPU_USED 1 +#else +#error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" +#define __FPU_USED 0 +#endif +#else +#define __FPU_USED 0 +#endif -#elif defined ( __CSMC__ ) /* Cosmic */ - #if ( __CSMC__ & 0x400) // FPU present for parser - #if (__FPU_PRESENT == 1) - #define __FPU_USED 1 - #else - #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" - #define __FPU_USED 0 - #endif - #else - #define __FPU_USED 0 - #endif +#elif defined(__CSMC__) /* Cosmic */ +#if (__CSMC__ & 0x400) // FPU present for parser +#if (__FPU_PRESENT == 1) +#define __FPU_USED 1 +#else +#error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" +#define __FPU_USED 0 +#endif +#else +#define __FPU_USED 0 +#endif #endif -#include <stdint.h> /* standard types definitions */ -#include <core_cmInstr.h> /* Core Instruction Access */ -#include <core_cmFunc.h> /* Core Function Access */ -#include <core_cmSimd.h> /* Compiler specific SIMD Intrinsics */ +#include <stdint.h> /* standard types definitions */ +#include <core_cmInstr.h> /* Core Instruction Access */ +#include <core_cmFunc.h> /* Core Function Access */ +#include <core_cmSimd.h> /* Compiler specific SIMD Intrinsics */ #ifdef __cplusplus } @@ -201,35 +199,36 @@ #define __CORE_CM4_H_DEPENDANT #ifdef __cplusplus - extern "C" { +extern "C" +{ #endif /* check device defines and use defaults */ #if defined __CHECK_DEVICE_DEFINES - #ifndef __CM4_REV - #define __CM4_REV 0x0000 - #warning "__CM4_REV not defined in device header file; using default!" - #endif +#ifndef __CM4_REV +#define __CM4_REV 0x0000 +#warning "__CM4_REV not defined in device header file; using default!" +#endif - #ifndef __FPU_PRESENT - #define __FPU_PRESENT 0 - #warning "__FPU_PRESENT not defined in device header file; using default!" - #endif +#ifndef __FPU_PRESENT +#define __FPU_PRESENT 0 +#warning "__FPU_PRESENT not defined in device header file; using default!" +#endif - #ifndef __MPU_PRESENT - #define __MPU_PRESENT 0 - #warning "__MPU_PRESENT not defined in device header file; using default!" - #endif +#ifndef __MPU_PRESENT +#define __MPU_PRESENT 0 +#warning "__MPU_PRESENT not defined in device header file; using default!" +#endif - #ifndef __NVIC_PRIO_BITS - #define __NVIC_PRIO_BITS 4 - #warning "__NVIC_PRIO_BITS not defined in device header file; using default!" - #endif +#ifndef __NVIC_PRIO_BITS +#define __NVIC_PRIO_BITS 4 +#warning "__NVIC_PRIO_BITS not defined in device header file; using default!" +#endif - #ifndef __Vendor_SysTickConfig - #define __Vendor_SysTickConfig 0 - #warning "__Vendor_SysTickConfig not defined in device header file; using default!" - #endif +#ifndef __Vendor_SysTickConfig +#define __Vendor_SysTickConfig 0 +#warning "__Vendor_SysTickConfig not defined in device header file; using default!" +#endif #endif /* IO definitions (access restrictions to peripheral registers) */ @@ -241,18 +240,16 @@ \li for automatic generation of peripheral register debug information. */ #ifdef __cplusplus - #define __I volatile /*!< Defines 'read only' permissions */ +#define __I volatile /*!< Defines 'read only' permissions */ #else - #define __I volatile const /*!< Defines 'read only' permissions */ +#define __I volatile const /*!< Defines 'read only' permissions */ #endif -#define __O volatile /*!< Defines 'write only' permissions */ -#define __IO volatile /*!< Defines 'read / write' permissions */ - -/*@} end of group Cortex_M4 */ - +#define __O volatile /*!< Defines 'write only' permissions */ +#define __IO volatile /*!< Defines 'read / write' permissions */ + /*@} end of group Cortex_M4 */ -/******************************************************************************* + /******************************************************************************* * Register Abstraction Core Register contain: - Core Register @@ -263,1133 +260,1119 @@ - Core MPU Register - Core FPU Register ******************************************************************************/ -/** \defgroup CMSIS_core_register Defines and Type Definitions + /** \defgroup CMSIS_core_register Defines and Type Definitions \brief Type definitions and defines for Cortex-M processor based devices. */ -/** \ingroup CMSIS_core_register + /** \ingroup CMSIS_core_register \defgroup CMSIS_CORE Status and Control Registers \brief Core Register type definitions. @{ */ -/** \brief Union type to access the Application Program Status Register (APSR). + /** \brief Union type to access the Application Program Status Register (APSR). */ -typedef union -{ - struct - { + typedef union + { + struct + { #if (__CORTEX_M != 0x04) - uint32_t _reserved0:27; /*!< bit: 0..26 Reserved */ + uint32_t _reserved0 : 27; /*!< bit: 0..26 Reserved */ #else - uint32_t _reserved0:16; /*!< bit: 0..15 Reserved */ - uint32_t GE:4; /*!< bit: 16..19 Greater than or Equal flags */ - uint32_t _reserved1:7; /*!< bit: 20..26 Reserved */ + uint32_t _reserved0 : 16; /*!< bit: 0..15 Reserved */ + uint32_t GE : 4; /*!< bit: 16..19 Greater than or Equal flags */ + uint32_t _reserved1 : 7; /*!< bit: 20..26 Reserved */ #endif - uint32_t Q:1; /*!< bit: 27 Saturation condition flag */ - uint32_t V:1; /*!< bit: 28 Overflow condition code flag */ - uint32_t C:1; /*!< bit: 29 Carry condition code flag */ - uint32_t Z:1; /*!< bit: 30 Zero condition code flag */ - uint32_t N:1; /*!< bit: 31 Negative condition code flag */ - } b; /*!< Structure used for bit access */ - uint32_t w; /*!< Type used for word access */ -} APSR_Type; - + uint32_t Q : 1; /*!< bit: 27 Saturation condition flag */ + uint32_t V : 1; /*!< bit: 28 Overflow condition code flag */ + uint32_t C : 1; /*!< bit: 29 Carry condition code flag */ + uint32_t Z : 1; /*!< bit: 30 Zero condition code flag */ + uint32_t N : 1; /*!< bit: 31 Negative condition code flag */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ + } APSR_Type; -/** \brief Union type to access the Interrupt Program Status Register (IPSR). + /** \brief Union type to access the Interrupt Program Status Register (IPSR). */ -typedef union -{ - struct - { - uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */ - uint32_t _reserved0:23; /*!< bit: 9..31 Reserved */ - } b; /*!< Structure used for bit access */ - uint32_t w; /*!< Type used for word access */ -} IPSR_Type; - + typedef union + { + struct + { + uint32_t ISR : 9; /*!< bit: 0.. 8 Exception number */ + uint32_t _reserved0 : 23; /*!< bit: 9..31 Reserved */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ + } IPSR_Type; -/** \brief Union type to access the Special-Purpose Program Status Registers (xPSR). + /** \brief Union type to access the Special-Purpose Program Status Registers (xPSR). */ -typedef union -{ - struct - { - uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */ + typedef union + { + struct + { + uint32_t ISR : 9; /*!< bit: 0.. 8 Exception number */ #if (__CORTEX_M != 0x04) - uint32_t _reserved0:15; /*!< bit: 9..23 Reserved */ + uint32_t _reserved0 : 15; /*!< bit: 9..23 Reserved */ #else - uint32_t _reserved0:7; /*!< bit: 9..15 Reserved */ - uint32_t GE:4; /*!< bit: 16..19 Greater than or Equal flags */ - uint32_t _reserved1:4; /*!< bit: 20..23 Reserved */ + uint32_t _reserved0 : 7; /*!< bit: 9..15 Reserved */ + uint32_t GE : 4; /*!< bit: 16..19 Greater than or Equal flags */ + uint32_t _reserved1 : 4; /*!< bit: 20..23 Reserved */ #endif - uint32_t T:1; /*!< bit: 24 Thumb bit (read 0) */ - uint32_t IT:2; /*!< bit: 25..26 saved IT state (read 0) */ - uint32_t Q:1; /*!< bit: 27 Saturation condition flag */ - uint32_t V:1; /*!< bit: 28 Overflow condition code flag */ - uint32_t C:1; /*!< bit: 29 Carry condition code flag */ - uint32_t Z:1; /*!< bit: 30 Zero condition code flag */ - uint32_t N:1; /*!< bit: 31 Negative condition code flag */ - } b; /*!< Structure used for bit access */ - uint32_t w; /*!< Type used for word access */ -} xPSR_Type; - + uint32_t T : 1; /*!< bit: 24 Thumb bit (read 0) */ + uint32_t IT : 2; /*!< bit: 25..26 saved IT state (read 0) */ + uint32_t Q : 1; /*!< bit: 27 Saturation condition flag */ + uint32_t V : 1; /*!< bit: 28 Overflow condition code flag */ + uint32_t C : 1; /*!< bit: 29 Carry condition code flag */ + uint32_t Z : 1; /*!< bit: 30 Zero condition code flag */ + uint32_t N : 1; /*!< bit: 31 Negative condition code flag */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ + } xPSR_Type; -/** \brief Union type to access the Control Registers (CONTROL). + /** \brief Union type to access the Control Registers (CONTROL). */ -typedef union -{ - struct - { - uint32_t nPRIV:1; /*!< bit: 0 Execution privilege in Thread mode */ - uint32_t SPSEL:1; /*!< bit: 1 Stack to be used */ - uint32_t FPCA:1; /*!< bit: 2 FP extension active flag */ - uint32_t _reserved0:29; /*!< bit: 3..31 Reserved */ - } b; /*!< Structure used for bit access */ - uint32_t w; /*!< Type used for word access */ -} CONTROL_Type; - -/*@} end of group CMSIS_CORE */ + typedef union + { + struct + { + uint32_t nPRIV : 1; /*!< bit: 0 Execution privilege in Thread mode */ + uint32_t SPSEL : 1; /*!< bit: 1 Stack to be used */ + uint32_t FPCA : 1; /*!< bit: 2 FP extension active flag */ + uint32_t _reserved0 : 29; /*!< bit: 3..31 Reserved */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ + } CONTROL_Type; + /*@} end of group CMSIS_CORE */ -/** \ingroup CMSIS_core_register + /** \ingroup CMSIS_core_register \defgroup CMSIS_NVIC Nested Vectored Interrupt Controller (NVIC) \brief Type definitions for the NVIC Registers @{ */ -/** \brief Structure type to access the Nested Vectored Interrupt Controller (NVIC). + /** \brief Structure type to access the Nested Vectored Interrupt Controller (NVIC). */ -typedef struct -{ - __IO uint32_t ISER[8]; /*!< Offset: 0x000 (R/W) Interrupt Set Enable Register */ - uint32_t RESERVED0[24]; - __IO uint32_t ICER[8]; /*!< Offset: 0x080 (R/W) Interrupt Clear Enable Register */ - uint32_t RSERVED1[24]; - __IO uint32_t ISPR[8]; /*!< Offset: 0x100 (R/W) Interrupt Set Pending Register */ - uint32_t RESERVED2[24]; - __IO uint32_t ICPR[8]; /*!< Offset: 0x180 (R/W) Interrupt Clear Pending Register */ - uint32_t RESERVED3[24]; - __IO uint32_t IABR[8]; /*!< Offset: 0x200 (R/W) Interrupt Active bit Register */ - uint32_t RESERVED4[56]; - __IO uint8_t IP[240]; /*!< Offset: 0x300 (R/W) Interrupt Priority Register (8Bit wide) */ - uint32_t RESERVED5[644]; - __O uint32_t STIR; /*!< Offset: 0xE00 ( /W) Software Trigger Interrupt Register */ -} NVIC_Type; + typedef struct + { + __IO uint32_t ISER[8]; /*!< Offset: 0x000 (R/W) Interrupt Set Enable Register */ + uint32_t RESERVED0[24]; + __IO uint32_t ICER[8]; /*!< Offset: 0x080 (R/W) Interrupt Clear Enable Register */ + uint32_t RSERVED1[24]; + __IO uint32_t ISPR[8]; /*!< Offset: 0x100 (R/W) Interrupt Set Pending Register */ + uint32_t RESERVED2[24]; + __IO uint32_t ICPR[8]; /*!< Offset: 0x180 (R/W) Interrupt Clear Pending Register */ + uint32_t RESERVED3[24]; + __IO uint32_t IABR[8]; /*!< Offset: 0x200 (R/W) Interrupt Active bit Register */ + uint32_t RESERVED4[56]; + __IO uint8_t IP[240]; /*!< Offset: 0x300 (R/W) Interrupt Priority Register (8Bit wide) */ + uint32_t RESERVED5[644]; + __O uint32_t STIR; /*!< Offset: 0xE00 ( /W) Software Trigger Interrupt Register */ + } NVIC_Type; /* Software Triggered Interrupt Register Definitions */ -#define NVIC_STIR_INTID_Pos 0 /*!< STIR: INTLINESNUM Position */ -#define NVIC_STIR_INTID_Msk (0x1FFUL << NVIC_STIR_INTID_Pos) /*!< STIR: INTLINESNUM Mask */ +#define NVIC_STIR_INTID_Pos 0 /*!< STIR: INTLINESNUM Position */ +#define NVIC_STIR_INTID_Msk (0x1FFUL << NVIC_STIR_INTID_Pos) /*!< STIR: INTLINESNUM Mask */ -/*@} end of group CMSIS_NVIC */ + /*@} end of group CMSIS_NVIC */ - -/** \ingroup CMSIS_core_register + /** \ingroup CMSIS_core_register \defgroup CMSIS_SCB System Control Block (SCB) \brief Type definitions for the System Control Block Registers @{ */ -/** \brief Structure type to access the System Control Block (SCB). + /** \brief Structure type to access the System Control Block (SCB). */ -typedef struct -{ - __I uint32_t CPUID; /*!< Offset: 0x000 (R/ ) CPUID Base Register */ - __IO uint32_t ICSR; /*!< Offset: 0x004 (R/W) Interrupt Control and State Register */ - __IO uint32_t VTOR; /*!< Offset: 0x008 (R/W) Vector Table Offset Register */ - __IO uint32_t AIRCR; /*!< Offset: 0x00C (R/W) Application Interrupt and Reset Control Register */ - __IO uint32_t SCR; /*!< Offset: 0x010 (R/W) System Control Register */ - __IO uint32_t CCR; /*!< Offset: 0x014 (R/W) Configuration Control Register */ - __IO uint8_t SHP[12]; /*!< Offset: 0x018 (R/W) System Handlers Priority Registers (4-7, 8-11, 12-15) */ - __IO uint32_t SHCSR; /*!< Offset: 0x024 (R/W) System Handler Control and State Register */ - __IO uint32_t CFSR; /*!< Offset: 0x028 (R/W) Configurable Fault Status Register */ - __IO uint32_t HFSR; /*!< Offset: 0x02C (R/W) HardFault Status Register */ - __IO uint32_t DFSR; /*!< Offset: 0x030 (R/W) Debug Fault Status Register */ - __IO uint32_t MMFAR; /*!< Offset: 0x034 (R/W) MemManage Fault Address Register */ - __IO uint32_t BFAR; /*!< Offset: 0x038 (R/W) BusFault Address Register */ - __IO uint32_t AFSR; /*!< Offset: 0x03C (R/W) Auxiliary Fault Status Register */ - __I uint32_t PFR[2]; /*!< Offset: 0x040 (R/ ) Processor Feature Register */ - __I uint32_t DFR; /*!< Offset: 0x048 (R/ ) Debug Feature Register */ - __I uint32_t ADR; /*!< Offset: 0x04C (R/ ) Auxiliary Feature Register */ - __I uint32_t MMFR[4]; /*!< Offset: 0x050 (R/ ) Memory Model Feature Register */ - __I uint32_t ISAR[5]; /*!< Offset: 0x060 (R/ ) Instruction Set Attributes Register */ - uint32_t RESERVED0[5]; - __IO uint32_t CPACR; /*!< Offset: 0x088 (R/W) Coprocessor Access Control Register */ -} SCB_Type; + typedef struct + { + __I uint32_t CPUID; /*!< Offset: 0x000 (R/ ) CPUID Base Register */ + __IO uint32_t ICSR; /*!< Offset: 0x004 (R/W) Interrupt Control and State Register */ + __IO uint32_t VTOR; /*!< Offset: 0x008 (R/W) Vector Table Offset Register */ + __IO uint32_t AIRCR; /*!< Offset: 0x00C (R/W) Application Interrupt and Reset Control Register */ + __IO uint32_t SCR; /*!< Offset: 0x010 (R/W) System Control Register */ + __IO uint32_t CCR; /*!< Offset: 0x014 (R/W) Configuration Control Register */ + __IO uint8_t SHP[12]; /*!< Offset: 0x018 (R/W) System Handlers Priority Registers (4-7, 8-11, 12-15) */ + __IO uint32_t SHCSR; /*!< Offset: 0x024 (R/W) System Handler Control and State Register */ + __IO uint32_t CFSR; /*!< Offset: 0x028 (R/W) Configurable Fault Status Register */ + __IO uint32_t HFSR; /*!< Offset: 0x02C (R/W) HardFault Status Register */ + __IO uint32_t DFSR; /*!< Offset: 0x030 (R/W) Debug Fault Status Register */ + __IO uint32_t MMFAR; /*!< Offset: 0x034 (R/W) MemManage Fault Address Register */ + __IO uint32_t BFAR; /*!< Offset: 0x038 (R/W) BusFault Address Register */ + __IO uint32_t AFSR; /*!< Offset: 0x03C (R/W) Auxiliary Fault Status Register */ + __I uint32_t PFR[2]; /*!< Offset: 0x040 (R/ ) Processor Feature Register */ + __I uint32_t DFR; /*!< Offset: 0x048 (R/ ) Debug Feature Register */ + __I uint32_t ADR; /*!< Offset: 0x04C (R/ ) Auxiliary Feature Register */ + __I uint32_t MMFR[4]; /*!< Offset: 0x050 (R/ ) Memory Model Feature Register */ + __I uint32_t ISAR[5]; /*!< Offset: 0x060 (R/ ) Instruction Set Attributes Register */ + uint32_t RESERVED0[5]; + __IO uint32_t CPACR; /*!< Offset: 0x088 (R/W) Coprocessor Access Control Register */ + } SCB_Type; /* SCB CPUID Register Definitions */ -#define SCB_CPUID_IMPLEMENTER_Pos 24 /*!< SCB CPUID: IMPLEMENTER Position */ -#define SCB_CPUID_IMPLEMENTER_Msk (0xFFUL << SCB_CPUID_IMPLEMENTER_Pos) /*!< SCB CPUID: IMPLEMENTER Mask */ +#define SCB_CPUID_IMPLEMENTER_Pos 24 /*!< SCB CPUID: IMPLEMENTER Position */ +#define SCB_CPUID_IMPLEMENTER_Msk (0xFFUL << SCB_CPUID_IMPLEMENTER_Pos) /*!< SCB CPUID: IMPLEMENTER Mask */ -#define SCB_CPUID_VARIANT_Pos 20 /*!< SCB CPUID: VARIANT Position */ -#define SCB_CPUID_VARIANT_Msk (0xFUL << SCB_CPUID_VARIANT_Pos) /*!< SCB CPUID: VARIANT Mask */ +#define SCB_CPUID_VARIANT_Pos 20 /*!< SCB CPUID: VARIANT Position */ +#define SCB_CPUID_VARIANT_Msk (0xFUL << SCB_CPUID_VARIANT_Pos) /*!< SCB CPUID: VARIANT Mask */ -#define SCB_CPUID_ARCHITECTURE_Pos 16 /*!< SCB CPUID: ARCHITECTURE Position */ -#define SCB_CPUID_ARCHITECTURE_Msk (0xFUL << SCB_CPUID_ARCHITECTURE_Pos) /*!< SCB CPUID: ARCHITECTURE Mask */ +#define SCB_CPUID_ARCHITECTURE_Pos 16 /*!< SCB CPUID: ARCHITECTURE Position */ +#define SCB_CPUID_ARCHITECTURE_Msk (0xFUL << SCB_CPUID_ARCHITECTURE_Pos) /*!< SCB CPUID: ARCHITECTURE Mask */ -#define SCB_CPUID_PARTNO_Pos 4 /*!< SCB CPUID: PARTNO Position */ -#define SCB_CPUID_PARTNO_Msk (0xFFFUL << SCB_CPUID_PARTNO_Pos) /*!< SCB CPUID: PARTNO Mask */ +#define SCB_CPUID_PARTNO_Pos 4 /*!< SCB CPUID: PARTNO Position */ +#define SCB_CPUID_PARTNO_Msk (0xFFFUL << SCB_CPUID_PARTNO_Pos) /*!< SCB CPUID: PARTNO Mask */ -#define SCB_CPUID_REVISION_Pos 0 /*!< SCB CPUID: REVISION Position */ -#define SCB_CPUID_REVISION_Msk (0xFUL << SCB_CPUID_REVISION_Pos) /*!< SCB CPUID: REVISION Mask */ +#define SCB_CPUID_REVISION_Pos 0 /*!< SCB CPUID: REVISION Position */ +#define SCB_CPUID_REVISION_Msk (0xFUL << SCB_CPUID_REVISION_Pos) /*!< SCB CPUID: REVISION Mask */ /* SCB Interrupt Control State Register Definitions */ -#define SCB_ICSR_NMIPENDSET_Pos 31 /*!< SCB ICSR: NMIPENDSET Position */ -#define SCB_ICSR_NMIPENDSET_Msk (1UL << SCB_ICSR_NMIPENDSET_Pos) /*!< SCB ICSR: NMIPENDSET Mask */ +#define SCB_ICSR_NMIPENDSET_Pos 31 /*!< SCB ICSR: NMIPENDSET Position */ +#define SCB_ICSR_NMIPENDSET_Msk (1UL << SCB_ICSR_NMIPENDSET_Pos) /*!< SCB ICSR: NMIPENDSET Mask */ -#define SCB_ICSR_PENDSVSET_Pos 28 /*!< SCB ICSR: PENDSVSET Position */ -#define SCB_ICSR_PENDSVSET_Msk (1UL << SCB_ICSR_PENDSVSET_Pos) /*!< SCB ICSR: PENDSVSET Mask */ +#define SCB_ICSR_PENDSVSET_Pos 28 /*!< SCB ICSR: PENDSVSET Position */ +#define SCB_ICSR_PENDSVSET_Msk (1UL << SCB_ICSR_PENDSVSET_Pos) /*!< SCB ICSR: PENDSVSET Mask */ -#define SCB_ICSR_PENDSVCLR_Pos 27 /*!< SCB ICSR: PENDSVCLR Position */ -#define SCB_ICSR_PENDSVCLR_Msk (1UL << SCB_ICSR_PENDSVCLR_Pos) /*!< SCB ICSR: PENDSVCLR Mask */ +#define SCB_ICSR_PENDSVCLR_Pos 27 /*!< SCB ICSR: PENDSVCLR Position */ +#define SCB_ICSR_PENDSVCLR_Msk (1UL << SCB_ICSR_PENDSVCLR_Pos) /*!< SCB ICSR: PENDSVCLR Mask */ -#define SCB_ICSR_PENDSTSET_Pos 26 /*!< SCB ICSR: PENDSTSET Position */ -#define SCB_ICSR_PENDSTSET_Msk (1UL << SCB_ICSR_PENDSTSET_Pos) /*!< SCB ICSR: PENDSTSET Mask */ +#define SCB_ICSR_PENDSTSET_Pos 26 /*!< SCB ICSR: PENDSTSET Position */ +#define SCB_ICSR_PENDSTSET_Msk (1UL << SCB_ICSR_PENDSTSET_Pos) /*!< SCB ICSR: PENDSTSET Mask */ -#define SCB_ICSR_PENDSTCLR_Pos 25 /*!< SCB ICSR: PENDSTCLR Position */ -#define SCB_ICSR_PENDSTCLR_Msk (1UL << SCB_ICSR_PENDSTCLR_Pos) /*!< SCB ICSR: PENDSTCLR Mask */ +#define SCB_ICSR_PENDSTCLR_Pos 25 /*!< SCB ICSR: PENDSTCLR Position */ +#define SCB_ICSR_PENDSTCLR_Msk (1UL << SCB_ICSR_PENDSTCLR_Pos) /*!< SCB ICSR: PENDSTCLR Mask */ -#define SCB_ICSR_ISRPREEMPT_Pos 23 /*!< SCB ICSR: ISRPREEMPT Position */ -#define SCB_ICSR_ISRPREEMPT_Msk (1UL << SCB_ICSR_ISRPREEMPT_Pos) /*!< SCB ICSR: ISRPREEMPT Mask */ +#define SCB_ICSR_ISRPREEMPT_Pos 23 /*!< SCB ICSR: ISRPREEMPT Position */ +#define SCB_ICSR_ISRPREEMPT_Msk (1UL << SCB_ICSR_ISRPREEMPT_Pos) /*!< SCB ICSR: ISRPREEMPT Mask */ -#define SCB_ICSR_ISRPENDING_Pos 22 /*!< SCB ICSR: ISRPENDING Position */ -#define SCB_ICSR_ISRPENDING_Msk (1UL << SCB_ICSR_ISRPENDING_Pos) /*!< SCB ICSR: ISRPENDING Mask */ +#define SCB_ICSR_ISRPENDING_Pos 22 /*!< SCB ICSR: ISRPENDING Position */ +#define SCB_ICSR_ISRPENDING_Msk (1UL << SCB_ICSR_ISRPENDING_Pos) /*!< SCB ICSR: ISRPENDING Mask */ -#define SCB_ICSR_VECTPENDING_Pos 12 /*!< SCB ICSR: VECTPENDING Position */ -#define SCB_ICSR_VECTPENDING_Msk (0x1FFUL << SCB_ICSR_VECTPENDING_Pos) /*!< SCB ICSR: VECTPENDING Mask */ +#define SCB_ICSR_VECTPENDING_Pos 12 /*!< SCB ICSR: VECTPENDING Position */ +#define SCB_ICSR_VECTPENDING_Msk (0x1FFUL << SCB_ICSR_VECTPENDING_Pos) /*!< SCB ICSR: VECTPENDING Mask */ -#define SCB_ICSR_RETTOBASE_Pos 11 /*!< SCB ICSR: RETTOBASE Position */ -#define SCB_ICSR_RETTOBASE_Msk (1UL << SCB_ICSR_RETTOBASE_Pos) /*!< SCB ICSR: RETTOBASE Mask */ +#define SCB_ICSR_RETTOBASE_Pos 11 /*!< SCB ICSR: RETTOBASE Position */ +#define SCB_ICSR_RETTOBASE_Msk (1UL << SCB_ICSR_RETTOBASE_Pos) /*!< SCB ICSR: RETTOBASE Mask */ -#define SCB_ICSR_VECTACTIVE_Pos 0 /*!< SCB ICSR: VECTACTIVE Position */ -#define SCB_ICSR_VECTACTIVE_Msk (0x1FFUL << SCB_ICSR_VECTACTIVE_Pos) /*!< SCB ICSR: VECTACTIVE Mask */ +#define SCB_ICSR_VECTACTIVE_Pos 0 /*!< SCB ICSR: VECTACTIVE Position */ +#define SCB_ICSR_VECTACTIVE_Msk (0x1FFUL << SCB_ICSR_VECTACTIVE_Pos) /*!< SCB ICSR: VECTACTIVE Mask */ /* SCB Vector Table Offset Register Definitions */ -#define SCB_VTOR_TBLOFF_Pos 7 /*!< SCB VTOR: TBLOFF Position */ -#define SCB_VTOR_TBLOFF_Msk (0x1FFFFFFUL << SCB_VTOR_TBLOFF_Pos) /*!< SCB VTOR: TBLOFF Mask */ +#define SCB_VTOR_TBLOFF_Pos 7 /*!< SCB VTOR: TBLOFF Position */ +#define SCB_VTOR_TBLOFF_Msk (0x1FFFFFFUL << SCB_VTOR_TBLOFF_Pos) /*!< SCB VTOR: TBLOFF Mask */ /* SCB Application Interrupt and Reset Control Register Definitions */ -#define SCB_AIRCR_VECTKEY_Pos 16 /*!< SCB AIRCR: VECTKEY Position */ -#define SCB_AIRCR_VECTKEY_Msk (0xFFFFUL << SCB_AIRCR_VECTKEY_Pos) /*!< SCB AIRCR: VECTKEY Mask */ +#define SCB_AIRCR_VECTKEY_Pos 16 /*!< SCB AIRCR: VECTKEY Position */ +#define SCB_AIRCR_VECTKEY_Msk (0xFFFFUL << SCB_AIRCR_VECTKEY_Pos) /*!< SCB AIRCR: VECTKEY Mask */ -#define SCB_AIRCR_VECTKEYSTAT_Pos 16 /*!< SCB AIRCR: VECTKEYSTAT Position */ -#define SCB_AIRCR_VECTKEYSTAT_Msk (0xFFFFUL << SCB_AIRCR_VECTKEYSTAT_Pos) /*!< SCB AIRCR: VECTKEYSTAT Mask */ +#define SCB_AIRCR_VECTKEYSTAT_Pos 16 /*!< SCB AIRCR: VECTKEYSTAT Position */ +#define SCB_AIRCR_VECTKEYSTAT_Msk (0xFFFFUL << SCB_AIRCR_VECTKEYSTAT_Pos) /*!< SCB AIRCR: VECTKEYSTAT Mask */ -#define SCB_AIRCR_ENDIANESS_Pos 15 /*!< SCB AIRCR: ENDIANESS Position */ -#define SCB_AIRCR_ENDIANESS_Msk (1UL << SCB_AIRCR_ENDIANESS_Pos) /*!< SCB AIRCR: ENDIANESS Mask */ +#define SCB_AIRCR_ENDIANESS_Pos 15 /*!< SCB AIRCR: ENDIANESS Position */ +#define SCB_AIRCR_ENDIANESS_Msk (1UL << SCB_AIRCR_ENDIANESS_Pos) /*!< SCB AIRCR: ENDIANESS Mask */ -#define SCB_AIRCR_PRIGROUP_Pos 8 /*!< SCB AIRCR: PRIGROUP Position */ -#define SCB_AIRCR_PRIGROUP_Msk (7UL << SCB_AIRCR_PRIGROUP_Pos) /*!< SCB AIRCR: PRIGROUP Mask */ +#define SCB_AIRCR_PRIGROUP_Pos 8 /*!< SCB AIRCR: PRIGROUP Position */ +#define SCB_AIRCR_PRIGROUP_Msk (7UL << SCB_AIRCR_PRIGROUP_Pos) /*!< SCB AIRCR: PRIGROUP Mask */ -#define SCB_AIRCR_SYSRESETREQ_Pos 2 /*!< SCB AIRCR: SYSRESETREQ Position */ -#define SCB_AIRCR_SYSRESETREQ_Msk (1UL << SCB_AIRCR_SYSRESETREQ_Pos) /*!< SCB AIRCR: SYSRESETREQ Mask */ +#define SCB_AIRCR_SYSRESETREQ_Pos 2 /*!< SCB AIRCR: SYSRESETREQ Position */ +#define SCB_AIRCR_SYSRESETREQ_Msk (1UL << SCB_AIRCR_SYSRESETREQ_Pos) /*!< SCB AIRCR: SYSRESETREQ Mask */ -#define SCB_AIRCR_VECTCLRACTIVE_Pos 1 /*!< SCB AIRCR: VECTCLRACTIVE Position */ -#define SCB_AIRCR_VECTCLRACTIVE_Msk (1UL << SCB_AIRCR_VECTCLRACTIVE_Pos) /*!< SCB AIRCR: VECTCLRACTIVE Mask */ +#define SCB_AIRCR_VECTCLRACTIVE_Pos 1 /*!< SCB AIRCR: VECTCLRACTIVE Position */ +#define SCB_AIRCR_VECTCLRACTIVE_Msk (1UL << SCB_AIRCR_VECTCLRACTIVE_Pos) /*!< SCB AIRCR: VECTCLRACTIVE Mask */ -#define SCB_AIRCR_VECTRESET_Pos 0 /*!< SCB AIRCR: VECTRESET Position */ -#define SCB_AIRCR_VECTRESET_Msk (1UL << SCB_AIRCR_VECTRESET_Pos) /*!< SCB AIRCR: VECTRESET Mask */ +#define SCB_AIRCR_VECTRESET_Pos 0 /*!< SCB AIRCR: VECTRESET Position */ +#define SCB_AIRCR_VECTRESET_Msk (1UL << SCB_AIRCR_VECTRESET_Pos) /*!< SCB AIRCR: VECTRESET Mask */ /* SCB System Control Register Definitions */ -#define SCB_SCR_SEVONPEND_Pos 4 /*!< SCB SCR: SEVONPEND Position */ -#define SCB_SCR_SEVONPEND_Msk (1UL << SCB_SCR_SEVONPEND_Pos) /*!< SCB SCR: SEVONPEND Mask */ +#define SCB_SCR_SEVONPEND_Pos 4 /*!< SCB SCR: SEVONPEND Position */ +#define SCB_SCR_SEVONPEND_Msk (1UL << SCB_SCR_SEVONPEND_Pos) /*!< SCB SCR: SEVONPEND Mask */ -#define SCB_SCR_SLEEPDEEP_Pos 2 /*!< SCB SCR: SLEEPDEEP Position */ -#define SCB_SCR_SLEEPDEEP_Msk (1UL << SCB_SCR_SLEEPDEEP_Pos) /*!< SCB SCR: SLEEPDEEP Mask */ +#define SCB_SCR_SLEEPDEEP_Pos 2 /*!< SCB SCR: SLEEPDEEP Position */ +#define SCB_SCR_SLEEPDEEP_Msk (1UL << SCB_SCR_SLEEPDEEP_Pos) /*!< SCB SCR: SLEEPDEEP Mask */ -#define SCB_SCR_SLEEPONEXIT_Pos 1 /*!< SCB SCR: SLEEPONEXIT Position */ -#define SCB_SCR_SLEEPONEXIT_Msk (1UL << SCB_SCR_SLEEPONEXIT_Pos) /*!< SCB SCR: SLEEPONEXIT Mask */ +#define SCB_SCR_SLEEPONEXIT_Pos 1 /*!< SCB SCR: SLEEPONEXIT Position */ +#define SCB_SCR_SLEEPONEXIT_Msk (1UL << SCB_SCR_SLEEPONEXIT_Pos) /*!< SCB SCR: SLEEPONEXIT Mask */ /* SCB Configuration Control Register Definitions */ -#define SCB_CCR_STKALIGN_Pos 9 /*!< SCB CCR: STKALIGN Position */ -#define SCB_CCR_STKALIGN_Msk (1UL << SCB_CCR_STKALIGN_Pos) /*!< SCB CCR: STKALIGN Mask */ +#define SCB_CCR_STKALIGN_Pos 9 /*!< SCB CCR: STKALIGN Position */ +#define SCB_CCR_STKALIGN_Msk (1UL << SCB_CCR_STKALIGN_Pos) /*!< SCB CCR: STKALIGN Mask */ -#define SCB_CCR_BFHFNMIGN_Pos 8 /*!< SCB CCR: BFHFNMIGN Position */ -#define SCB_CCR_BFHFNMIGN_Msk (1UL << SCB_CCR_BFHFNMIGN_Pos) /*!< SCB CCR: BFHFNMIGN Mask */ +#define SCB_CCR_BFHFNMIGN_Pos 8 /*!< SCB CCR: BFHFNMIGN Position */ +#define SCB_CCR_BFHFNMIGN_Msk (1UL << SCB_CCR_BFHFNMIGN_Pos) /*!< SCB CCR: BFHFNMIGN Mask */ -#define SCB_CCR_DIV_0_TRP_Pos 4 /*!< SCB CCR: DIV_0_TRP Position */ -#define SCB_CCR_DIV_0_TRP_Msk (1UL << SCB_CCR_DIV_0_TRP_Pos) /*!< SCB CCR: DIV_0_TRP Mask */ +#define SCB_CCR_DIV_0_TRP_Pos 4 /*!< SCB CCR: DIV_0_TRP Position */ +#define SCB_CCR_DIV_0_TRP_Msk (1UL << SCB_CCR_DIV_0_TRP_Pos) /*!< SCB CCR: DIV_0_TRP Mask */ -#define SCB_CCR_UNALIGN_TRP_Pos 3 /*!< SCB CCR: UNALIGN_TRP Position */ -#define SCB_CCR_UNALIGN_TRP_Msk (1UL << SCB_CCR_UNALIGN_TRP_Pos) /*!< SCB CCR: UNALIGN_TRP Mask */ +#define SCB_CCR_UNALIGN_TRP_Pos 3 /*!< SCB CCR: UNALIGN_TRP Position */ +#define SCB_CCR_UNALIGN_TRP_Msk (1UL << SCB_CCR_UNALIGN_TRP_Pos) /*!< SCB CCR: UNALIGN_TRP Mask */ -#define SCB_CCR_USERSETMPEND_Pos 1 /*!< SCB CCR: USERSETMPEND Position */ -#define SCB_CCR_USERSETMPEND_Msk (1UL << SCB_CCR_USERSETMPEND_Pos) /*!< SCB CCR: USERSETMPEND Mask */ +#define SCB_CCR_USERSETMPEND_Pos 1 /*!< SCB CCR: USERSETMPEND Position */ +#define SCB_CCR_USERSETMPEND_Msk (1UL << SCB_CCR_USERSETMPEND_Pos) /*!< SCB CCR: USERSETMPEND Mask */ -#define SCB_CCR_NONBASETHRDENA_Pos 0 /*!< SCB CCR: NONBASETHRDENA Position */ -#define SCB_CCR_NONBASETHRDENA_Msk (1UL << SCB_CCR_NONBASETHRDENA_Pos) /*!< SCB CCR: NONBASETHRDENA Mask */ +#define SCB_CCR_NONBASETHRDENA_Pos 0 /*!< SCB CCR: NONBASETHRDENA Position */ +#define SCB_CCR_NONBASETHRDENA_Msk (1UL << SCB_CCR_NONBASETHRDENA_Pos) /*!< SCB CCR: NONBASETHRDENA Mask */ /* SCB System Handler Control and State Register Definitions */ -#define SCB_SHCSR_USGFAULTENA_Pos 18 /*!< SCB SHCSR: USGFAULTENA Position */ -#define SCB_SHCSR_USGFAULTENA_Msk (1UL << SCB_SHCSR_USGFAULTENA_Pos) /*!< SCB SHCSR: USGFAULTENA Mask */ +#define SCB_SHCSR_USGFAULTENA_Pos 18 /*!< SCB SHCSR: USGFAULTENA Position */ +#define SCB_SHCSR_USGFAULTENA_Msk (1UL << SCB_SHCSR_USGFAULTENA_Pos) /*!< SCB SHCSR: USGFAULTENA Mask */ -#define SCB_SHCSR_BUSFAULTENA_Pos 17 /*!< SCB SHCSR: BUSFAULTENA Position */ -#define SCB_SHCSR_BUSFAULTENA_Msk (1UL << SCB_SHCSR_BUSFAULTENA_Pos) /*!< SCB SHCSR: BUSFAULTENA Mask */ +#define SCB_SHCSR_BUSFAULTENA_Pos 17 /*!< SCB SHCSR: BUSFAULTENA Position */ +#define SCB_SHCSR_BUSFAULTENA_Msk (1UL << SCB_SHCSR_BUSFAULTENA_Pos) /*!< SCB SHCSR: BUSFAULTENA Mask */ -#define SCB_SHCSR_MEMFAULTENA_Pos 16 /*!< SCB SHCSR: MEMFAULTENA Position */ -#define SCB_SHCSR_MEMFAULTENA_Msk (1UL << SCB_SHCSR_MEMFAULTENA_Pos) /*!< SCB SHCSR: MEMFAULTENA Mask */ +#define SCB_SHCSR_MEMFAULTENA_Pos 16 /*!< SCB SHCSR: MEMFAULTENA Position */ +#define SCB_SHCSR_MEMFAULTENA_Msk (1UL << SCB_SHCSR_MEMFAULTENA_Pos) /*!< SCB SHCSR: MEMFAULTENA Mask */ -#define SCB_SHCSR_SVCALLPENDED_Pos 15 /*!< SCB SHCSR: SVCALLPENDED Position */ -#define SCB_SHCSR_SVCALLPENDED_Msk (1UL << SCB_SHCSR_SVCALLPENDED_Pos) /*!< SCB SHCSR: SVCALLPENDED Mask */ +#define SCB_SHCSR_SVCALLPENDED_Pos 15 /*!< SCB SHCSR: SVCALLPENDED Position */ +#define SCB_SHCSR_SVCALLPENDED_Msk (1UL << SCB_SHCSR_SVCALLPENDED_Pos) /*!< SCB SHCSR: SVCALLPENDED Mask */ -#define SCB_SHCSR_BUSFAULTPENDED_Pos 14 /*!< SCB SHCSR: BUSFAULTPENDED Position */ -#define SCB_SHCSR_BUSFAULTPENDED_Msk (1UL << SCB_SHCSR_BUSFAULTPENDED_Pos) /*!< SCB SHCSR: BUSFAULTPENDED Mask */ +#define SCB_SHCSR_BUSFAULTPENDED_Pos 14 /*!< SCB SHCSR: BUSFAULTPENDED Position */ +#define SCB_SHCSR_BUSFAULTPENDED_Msk (1UL << SCB_SHCSR_BUSFAULTPENDED_Pos) /*!< SCB SHCSR: BUSFAULTPENDED Mask */ -#define SCB_SHCSR_MEMFAULTPENDED_Pos 13 /*!< SCB SHCSR: MEMFAULTPENDED Position */ -#define SCB_SHCSR_MEMFAULTPENDED_Msk (1UL << SCB_SHCSR_MEMFAULTPENDED_Pos) /*!< SCB SHCSR: MEMFAULTPENDED Mask */ +#define SCB_SHCSR_MEMFAULTPENDED_Pos 13 /*!< SCB SHCSR: MEMFAULTPENDED Position */ +#define SCB_SHCSR_MEMFAULTPENDED_Msk (1UL << SCB_SHCSR_MEMFAULTPENDED_Pos) /*!< SCB SHCSR: MEMFAULTPENDED Mask */ -#define SCB_SHCSR_USGFAULTPENDED_Pos 12 /*!< SCB SHCSR: USGFAULTPENDED Position */ -#define SCB_SHCSR_USGFAULTPENDED_Msk (1UL << SCB_SHCSR_USGFAULTPENDED_Pos) /*!< SCB SHCSR: USGFAULTPENDED Mask */ +#define SCB_SHCSR_USGFAULTPENDED_Pos 12 /*!< SCB SHCSR: USGFAULTPENDED Position */ +#define SCB_SHCSR_USGFAULTPENDED_Msk (1UL << SCB_SHCSR_USGFAULTPENDED_Pos) /*!< SCB SHCSR: USGFAULTPENDED Mask */ -#define SCB_SHCSR_SYSTICKACT_Pos 11 /*!< SCB SHCSR: SYSTICKACT Position */ -#define SCB_SHCSR_SYSTICKACT_Msk (1UL << SCB_SHCSR_SYSTICKACT_Pos) /*!< SCB SHCSR: SYSTICKACT Mask */ +#define SCB_SHCSR_SYSTICKACT_Pos 11 /*!< SCB SHCSR: SYSTICKACT Position */ +#define SCB_SHCSR_SYSTICKACT_Msk (1UL << SCB_SHCSR_SYSTICKACT_Pos) /*!< SCB SHCSR: SYSTICKACT Mask */ -#define SCB_SHCSR_PENDSVACT_Pos 10 /*!< SCB SHCSR: PENDSVACT Position */ -#define SCB_SHCSR_PENDSVACT_Msk (1UL << SCB_SHCSR_PENDSVACT_Pos) /*!< SCB SHCSR: PENDSVACT Mask */ +#define SCB_SHCSR_PENDSVACT_Pos 10 /*!< SCB SHCSR: PENDSVACT Position */ +#define SCB_SHCSR_PENDSVACT_Msk (1UL << SCB_SHCSR_PENDSVACT_Pos) /*!< SCB SHCSR: PENDSVACT Mask */ -#define SCB_SHCSR_MONITORACT_Pos 8 /*!< SCB SHCSR: MONITORACT Position */ -#define SCB_SHCSR_MONITORACT_Msk (1UL << SCB_SHCSR_MONITORACT_Pos) /*!< SCB SHCSR: MONITORACT Mask */ +#define SCB_SHCSR_MONITORACT_Pos 8 /*!< SCB SHCSR: MONITORACT Position */ +#define SCB_SHCSR_MONITORACT_Msk (1UL << SCB_SHCSR_MONITORACT_Pos) /*!< SCB SHCSR: MONITORACT Mask */ -#define SCB_SHCSR_SVCALLACT_Pos 7 /*!< SCB SHCSR: SVCALLACT Position */ -#define SCB_SHCSR_SVCALLACT_Msk (1UL << SCB_SHCSR_SVCALLACT_Pos) /*!< SCB SHCSR: SVCALLACT Mask */ +#define SCB_SHCSR_SVCALLACT_Pos 7 /*!< SCB SHCSR: SVCALLACT Position */ +#define SCB_SHCSR_SVCALLACT_Msk (1UL << SCB_SHCSR_SVCALLACT_Pos) /*!< SCB SHCSR: SVCALLACT Mask */ -#define SCB_SHCSR_USGFAULTACT_Pos 3 /*!< SCB SHCSR: USGFAULTACT Position */ -#define SCB_SHCSR_USGFAULTACT_Msk (1UL << SCB_SHCSR_USGFAULTACT_Pos) /*!< SCB SHCSR: USGFAULTACT Mask */ +#define SCB_SHCSR_USGFAULTACT_Pos 3 /*!< SCB SHCSR: USGFAULTACT Position */ +#define SCB_SHCSR_USGFAULTACT_Msk (1UL << SCB_SHCSR_USGFAULTACT_Pos) /*!< SCB SHCSR: USGFAULTACT Mask */ -#define SCB_SHCSR_BUSFAULTACT_Pos 1 /*!< SCB SHCSR: BUSFAULTACT Position */ -#define SCB_SHCSR_BUSFAULTACT_Msk (1UL << SCB_SHCSR_BUSFAULTACT_Pos) /*!< SCB SHCSR: BUSFAULTACT Mask */ +#define SCB_SHCSR_BUSFAULTACT_Pos 1 /*!< SCB SHCSR: BUSFAULTACT Position */ +#define SCB_SHCSR_BUSFAULTACT_Msk (1UL << SCB_SHCSR_BUSFAULTACT_Pos) /*!< SCB SHCSR: BUSFAULTACT Mask */ -#define SCB_SHCSR_MEMFAULTACT_Pos 0 /*!< SCB SHCSR: MEMFAULTACT Position */ -#define SCB_SHCSR_MEMFAULTACT_Msk (1UL << SCB_SHCSR_MEMFAULTACT_Pos) /*!< SCB SHCSR: MEMFAULTACT Mask */ +#define SCB_SHCSR_MEMFAULTACT_Pos 0 /*!< SCB SHCSR: MEMFAULTACT Position */ +#define SCB_SHCSR_MEMFAULTACT_Msk (1UL << SCB_SHCSR_MEMFAULTACT_Pos) /*!< SCB SHCSR: MEMFAULTACT Mask */ /* SCB Configurable Fault Status Registers Definitions */ -#define SCB_CFSR_USGFAULTSR_Pos 16 /*!< SCB CFSR: Usage Fault Status Register Position */ -#define SCB_CFSR_USGFAULTSR_Msk (0xFFFFUL << SCB_CFSR_USGFAULTSR_Pos) /*!< SCB CFSR: Usage Fault Status Register Mask */ +#define SCB_CFSR_USGFAULTSR_Pos 16 /*!< SCB CFSR: Usage Fault Status Register Position */ +#define SCB_CFSR_USGFAULTSR_Msk (0xFFFFUL << SCB_CFSR_USGFAULTSR_Pos) /*!< SCB CFSR: Usage Fault Status Register Mask */ -#define SCB_CFSR_BUSFAULTSR_Pos 8 /*!< SCB CFSR: Bus Fault Status Register Position */ -#define SCB_CFSR_BUSFAULTSR_Msk (0xFFUL << SCB_CFSR_BUSFAULTSR_Pos) /*!< SCB CFSR: Bus Fault Status Register Mask */ +#define SCB_CFSR_BUSFAULTSR_Pos 8 /*!< SCB CFSR: Bus Fault Status Register Position */ +#define SCB_CFSR_BUSFAULTSR_Msk (0xFFUL << SCB_CFSR_BUSFAULTSR_Pos) /*!< SCB CFSR: Bus Fault Status Register Mask */ -#define SCB_CFSR_MEMFAULTSR_Pos 0 /*!< SCB CFSR: Memory Manage Fault Status Register Position */ -#define SCB_CFSR_MEMFAULTSR_Msk (0xFFUL << SCB_CFSR_MEMFAULTSR_Pos) /*!< SCB CFSR: Memory Manage Fault Status Register Mask */ +#define SCB_CFSR_MEMFAULTSR_Pos 0 /*!< SCB CFSR: Memory Manage Fault Status Register Position */ +#define SCB_CFSR_MEMFAULTSR_Msk (0xFFUL << SCB_CFSR_MEMFAULTSR_Pos) /*!< SCB CFSR: Memory Manage Fault Status Register Mask */ /* SCB Hard Fault Status Registers Definitions */ -#define SCB_HFSR_DEBUGEVT_Pos 31 /*!< SCB HFSR: DEBUGEVT Position */ -#define SCB_HFSR_DEBUGEVT_Msk (1UL << SCB_HFSR_DEBUGEVT_Pos) /*!< SCB HFSR: DEBUGEVT Mask */ +#define SCB_HFSR_DEBUGEVT_Pos 31 /*!< SCB HFSR: DEBUGEVT Position */ +#define SCB_HFSR_DEBUGEVT_Msk (1UL << SCB_HFSR_DEBUGEVT_Pos) /*!< SCB HFSR: DEBUGEVT Mask */ -#define SCB_HFSR_FORCED_Pos 30 /*!< SCB HFSR: FORCED Position */ -#define SCB_HFSR_FORCED_Msk (1UL << SCB_HFSR_FORCED_Pos) /*!< SCB HFSR: FORCED Mask */ +#define SCB_HFSR_FORCED_Pos 30 /*!< SCB HFSR: FORCED Position */ +#define SCB_HFSR_FORCED_Msk (1UL << SCB_HFSR_FORCED_Pos) /*!< SCB HFSR: FORCED Mask */ -#define SCB_HFSR_VECTTBL_Pos 1 /*!< SCB HFSR: VECTTBL Position */ -#define SCB_HFSR_VECTTBL_Msk (1UL << SCB_HFSR_VECTTBL_Pos) /*!< SCB HFSR: VECTTBL Mask */ +#define SCB_HFSR_VECTTBL_Pos 1 /*!< SCB HFSR: VECTTBL Position */ +#define SCB_HFSR_VECTTBL_Msk (1UL << SCB_HFSR_VECTTBL_Pos) /*!< SCB HFSR: VECTTBL Mask */ /* SCB Debug Fault Status Register Definitions */ -#define SCB_DFSR_EXTERNAL_Pos 4 /*!< SCB DFSR: EXTERNAL Position */ -#define SCB_DFSR_EXTERNAL_Msk (1UL << SCB_DFSR_EXTERNAL_Pos) /*!< SCB DFSR: EXTERNAL Mask */ +#define SCB_DFSR_EXTERNAL_Pos 4 /*!< SCB DFSR: EXTERNAL Position */ +#define SCB_DFSR_EXTERNAL_Msk (1UL << SCB_DFSR_EXTERNAL_Pos) /*!< SCB DFSR: EXTERNAL Mask */ -#define SCB_DFSR_VCATCH_Pos 3 /*!< SCB DFSR: VCATCH Position */ -#define SCB_DFSR_VCATCH_Msk (1UL << SCB_DFSR_VCATCH_Pos) /*!< SCB DFSR: VCATCH Mask */ +#define SCB_DFSR_VCATCH_Pos 3 /*!< SCB DFSR: VCATCH Position */ +#define SCB_DFSR_VCATCH_Msk (1UL << SCB_DFSR_VCATCH_Pos) /*!< SCB DFSR: VCATCH Mask */ -#define SCB_DFSR_DWTTRAP_Pos 2 /*!< SCB DFSR: DWTTRAP Position */ -#define SCB_DFSR_DWTTRAP_Msk (1UL << SCB_DFSR_DWTTRAP_Pos) /*!< SCB DFSR: DWTTRAP Mask */ +#define SCB_DFSR_DWTTRAP_Pos 2 /*!< SCB DFSR: DWTTRAP Position */ +#define SCB_DFSR_DWTTRAP_Msk (1UL << SCB_DFSR_DWTTRAP_Pos) /*!< SCB DFSR: DWTTRAP Mask */ -#define SCB_DFSR_BKPT_Pos 1 /*!< SCB DFSR: BKPT Position */ -#define SCB_DFSR_BKPT_Msk (1UL << SCB_DFSR_BKPT_Pos) /*!< SCB DFSR: BKPT Mask */ +#define SCB_DFSR_BKPT_Pos 1 /*!< SCB DFSR: BKPT Position */ +#define SCB_DFSR_BKPT_Msk (1UL << SCB_DFSR_BKPT_Pos) /*!< SCB DFSR: BKPT Mask */ -#define SCB_DFSR_HALTED_Pos 0 /*!< SCB DFSR: HALTED Position */ -#define SCB_DFSR_HALTED_Msk (1UL << SCB_DFSR_HALTED_Pos) /*!< SCB DFSR: HALTED Mask */ +#define SCB_DFSR_HALTED_Pos 0 /*!< SCB DFSR: HALTED Position */ +#define SCB_DFSR_HALTED_Msk (1UL << SCB_DFSR_HALTED_Pos) /*!< SCB DFSR: HALTED Mask */ -/*@} end of group CMSIS_SCB */ + /*@} end of group CMSIS_SCB */ - -/** \ingroup CMSIS_core_register + /** \ingroup CMSIS_core_register \defgroup CMSIS_SCnSCB System Controls not in SCB (SCnSCB) \brief Type definitions for the System Control and ID Register not in the SCB @{ */ -/** \brief Structure type to access the System Control and ID Register not in the SCB. + /** \brief Structure type to access the System Control and ID Register not in the SCB. */ -typedef struct -{ - uint32_t RESERVED0[1]; - __I uint32_t ICTR; /*!< Offset: 0x004 (R/ ) Interrupt Controller Type Register */ - __IO uint32_t ACTLR; /*!< Offset: 0x008 (R/W) Auxiliary Control Register */ -} SCnSCB_Type; + typedef struct + { + uint32_t RESERVED0[1]; + __I uint32_t ICTR; /*!< Offset: 0x004 (R/ ) Interrupt Controller Type Register */ + __IO uint32_t ACTLR; /*!< Offset: 0x008 (R/W) Auxiliary Control Register */ + } SCnSCB_Type; /* Interrupt Controller Type Register Definitions */ -#define SCnSCB_ICTR_INTLINESNUM_Pos 0 /*!< ICTR: INTLINESNUM Position */ -#define SCnSCB_ICTR_INTLINESNUM_Msk (0xFUL << SCnSCB_ICTR_INTLINESNUM_Pos) /*!< ICTR: INTLINESNUM Mask */ +#define SCnSCB_ICTR_INTLINESNUM_Pos 0 /*!< ICTR: INTLINESNUM Position */ +#define SCnSCB_ICTR_INTLINESNUM_Msk (0xFUL << SCnSCB_ICTR_INTLINESNUM_Pos) /*!< ICTR: INTLINESNUM Mask */ /* Auxiliary Control Register Definitions */ -#define SCnSCB_ACTLR_DISOOFP_Pos 9 /*!< ACTLR: DISOOFP Position */ -#define SCnSCB_ACTLR_DISOOFP_Msk (1UL << SCnSCB_ACTLR_DISOOFP_Pos) /*!< ACTLR: DISOOFP Mask */ +#define SCnSCB_ACTLR_DISOOFP_Pos 9 /*!< ACTLR: DISOOFP Position */ +#define SCnSCB_ACTLR_DISOOFP_Msk (1UL << SCnSCB_ACTLR_DISOOFP_Pos) /*!< ACTLR: DISOOFP Mask */ -#define SCnSCB_ACTLR_DISFPCA_Pos 8 /*!< ACTLR: DISFPCA Position */ -#define SCnSCB_ACTLR_DISFPCA_Msk (1UL << SCnSCB_ACTLR_DISFPCA_Pos) /*!< ACTLR: DISFPCA Mask */ +#define SCnSCB_ACTLR_DISFPCA_Pos 8 /*!< ACTLR: DISFPCA Position */ +#define SCnSCB_ACTLR_DISFPCA_Msk (1UL << SCnSCB_ACTLR_DISFPCA_Pos) /*!< ACTLR: DISFPCA Mask */ -#define SCnSCB_ACTLR_DISFOLD_Pos 2 /*!< ACTLR: DISFOLD Position */ -#define SCnSCB_ACTLR_DISFOLD_Msk (1UL << SCnSCB_ACTLR_DISFOLD_Pos) /*!< ACTLR: DISFOLD Mask */ +#define SCnSCB_ACTLR_DISFOLD_Pos 2 /*!< ACTLR: DISFOLD Position */ +#define SCnSCB_ACTLR_DISFOLD_Msk (1UL << SCnSCB_ACTLR_DISFOLD_Pos) /*!< ACTLR: DISFOLD Mask */ -#define SCnSCB_ACTLR_DISDEFWBUF_Pos 1 /*!< ACTLR: DISDEFWBUF Position */ -#define SCnSCB_ACTLR_DISDEFWBUF_Msk (1UL << SCnSCB_ACTLR_DISDEFWBUF_Pos) /*!< ACTLR: DISDEFWBUF Mask */ +#define SCnSCB_ACTLR_DISDEFWBUF_Pos 1 /*!< ACTLR: DISDEFWBUF Position */ +#define SCnSCB_ACTLR_DISDEFWBUF_Msk (1UL << SCnSCB_ACTLR_DISDEFWBUF_Pos) /*!< ACTLR: DISDEFWBUF Mask */ -#define SCnSCB_ACTLR_DISMCYCINT_Pos 0 /*!< ACTLR: DISMCYCINT Position */ -#define SCnSCB_ACTLR_DISMCYCINT_Msk (1UL << SCnSCB_ACTLR_DISMCYCINT_Pos) /*!< ACTLR: DISMCYCINT Mask */ +#define SCnSCB_ACTLR_DISMCYCINT_Pos 0 /*!< ACTLR: DISMCYCINT Position */ +#define SCnSCB_ACTLR_DISMCYCINT_Msk (1UL << SCnSCB_ACTLR_DISMCYCINT_Pos) /*!< ACTLR: DISMCYCINT Mask */ -/*@} end of group CMSIS_SCnotSCB */ + /*@} end of group CMSIS_SCnotSCB */ - -/** \ingroup CMSIS_core_register + /** \ingroup CMSIS_core_register \defgroup CMSIS_SysTick System Tick Timer (SysTick) \brief Type definitions for the System Timer Registers. @{ */ -/** \brief Structure type to access the System Timer (SysTick). + /** \brief Structure type to access the System Timer (SysTick). */ -typedef struct -{ - __IO uint32_t CTRL; /*!< Offset: 0x000 (R/W) SysTick Control and Status Register */ - __IO uint32_t LOAD; /*!< Offset: 0x004 (R/W) SysTick Reload Value Register */ - __IO uint32_t VAL; /*!< Offset: 0x008 (R/W) SysTick Current Value Register */ - __I uint32_t CALIB; /*!< Offset: 0x00C (R/ ) SysTick Calibration Register */ -} SysTick_Type; + typedef struct + { + __IO uint32_t CTRL; /*!< Offset: 0x000 (R/W) SysTick Control and Status Register */ + __IO uint32_t LOAD; /*!< Offset: 0x004 (R/W) SysTick Reload Value Register */ + __IO uint32_t VAL; /*!< Offset: 0x008 (R/W) SysTick Current Value Register */ + __I uint32_t CALIB; /*!< Offset: 0x00C (R/ ) SysTick Calibration Register */ + } SysTick_Type; /* SysTick Control / Status Register Definitions */ -#define SysTick_CTRL_COUNTFLAG_Pos 16 /*!< SysTick CTRL: COUNTFLAG Position */ -#define SysTick_CTRL_COUNTFLAG_Msk (1UL << SysTick_CTRL_COUNTFLAG_Pos) /*!< SysTick CTRL: COUNTFLAG Mask */ +#define SysTick_CTRL_COUNTFLAG_Pos 16 /*!< SysTick CTRL: COUNTFLAG Position */ +#define SysTick_CTRL_COUNTFLAG_Msk (1UL << SysTick_CTRL_COUNTFLAG_Pos) /*!< SysTick CTRL: COUNTFLAG Mask */ -#define SysTick_CTRL_CLKSOURCE_Pos 2 /*!< SysTick CTRL: CLKSOURCE Position */ -#define SysTick_CTRL_CLKSOURCE_Msk (1UL << SysTick_CTRL_CLKSOURCE_Pos) /*!< SysTick CTRL: CLKSOURCE Mask */ +#define SysTick_CTRL_CLKSOURCE_Pos 2 /*!< SysTick CTRL: CLKSOURCE Position */ +#define SysTick_CTRL_CLKSOURCE_Msk (1UL << SysTick_CTRL_CLKSOURCE_Pos) /*!< SysTick CTRL: CLKSOURCE Mask */ -#define SysTick_CTRL_TICKINT_Pos 1 /*!< SysTick CTRL: TICKINT Position */ -#define SysTick_CTRL_TICKINT_Msk (1UL << SysTick_CTRL_TICKINT_Pos) /*!< SysTick CTRL: TICKINT Mask */ +#define SysTick_CTRL_TICKINT_Pos 1 /*!< SysTick CTRL: TICKINT Position */ +#define SysTick_CTRL_TICKINT_Msk (1UL << SysTick_CTRL_TICKINT_Pos) /*!< SysTick CTRL: TICKINT Mask */ -#define SysTick_CTRL_ENABLE_Pos 0 /*!< SysTick CTRL: ENABLE Position */ -#define SysTick_CTRL_ENABLE_Msk (1UL << SysTick_CTRL_ENABLE_Pos) /*!< SysTick CTRL: ENABLE Mask */ +#define SysTick_CTRL_ENABLE_Pos 0 /*!< SysTick CTRL: ENABLE Position */ +#define SysTick_CTRL_ENABLE_Msk (1UL << SysTick_CTRL_ENABLE_Pos) /*!< SysTick CTRL: ENABLE Mask */ /* SysTick Reload Register Definitions */ -#define SysTick_LOAD_RELOAD_Pos 0 /*!< SysTick LOAD: RELOAD Position */ -#define SysTick_LOAD_RELOAD_Msk (0xFFFFFFUL << SysTick_LOAD_RELOAD_Pos) /*!< SysTick LOAD: RELOAD Mask */ +#define SysTick_LOAD_RELOAD_Pos 0 /*!< SysTick LOAD: RELOAD Position */ +#define SysTick_LOAD_RELOAD_Msk (0xFFFFFFUL << SysTick_LOAD_RELOAD_Pos) /*!< SysTick LOAD: RELOAD Mask */ /* SysTick Current Register Definitions */ -#define SysTick_VAL_CURRENT_Pos 0 /*!< SysTick VAL: CURRENT Position */ -#define SysTick_VAL_CURRENT_Msk (0xFFFFFFUL << SysTick_VAL_CURRENT_Pos) /*!< SysTick VAL: CURRENT Mask */ +#define SysTick_VAL_CURRENT_Pos 0 /*!< SysTick VAL: CURRENT Position */ +#define SysTick_VAL_CURRENT_Msk (0xFFFFFFUL << SysTick_VAL_CURRENT_Pos) /*!< SysTick VAL: CURRENT Mask */ /* SysTick Calibration Register Definitions */ -#define SysTick_CALIB_NOREF_Pos 31 /*!< SysTick CALIB: NOREF Position */ -#define SysTick_CALIB_NOREF_Msk (1UL << SysTick_CALIB_NOREF_Pos) /*!< SysTick CALIB: NOREF Mask */ +#define SysTick_CALIB_NOREF_Pos 31 /*!< SysTick CALIB: NOREF Position */ +#define SysTick_CALIB_NOREF_Msk (1UL << SysTick_CALIB_NOREF_Pos) /*!< SysTick CALIB: NOREF Mask */ -#define SysTick_CALIB_SKEW_Pos 30 /*!< SysTick CALIB: SKEW Position */ -#define SysTick_CALIB_SKEW_Msk (1UL << SysTick_CALIB_SKEW_Pos) /*!< SysTick CALIB: SKEW Mask */ +#define SysTick_CALIB_SKEW_Pos 30 /*!< SysTick CALIB: SKEW Position */ +#define SysTick_CALIB_SKEW_Msk (1UL << SysTick_CALIB_SKEW_Pos) /*!< SysTick CALIB: SKEW Mask */ -#define SysTick_CALIB_TENMS_Pos 0 /*!< SysTick CALIB: TENMS Position */ -#define SysTick_CALIB_TENMS_Msk (0xFFFFFFUL << SysTick_CALIB_TENMS_Pos) /*!< SysTick CALIB: TENMS Mask */ +#define SysTick_CALIB_TENMS_Pos 0 /*!< SysTick CALIB: TENMS Position */ +#define SysTick_CALIB_TENMS_Msk (0xFFFFFFUL << SysTick_CALIB_TENMS_Pos) /*!< SysTick CALIB: TENMS Mask */ -/*@} end of group CMSIS_SysTick */ + /*@} end of group CMSIS_SysTick */ - -/** \ingroup CMSIS_core_register + /** \ingroup CMSIS_core_register \defgroup CMSIS_ITM Instrumentation Trace Macrocell (ITM) \brief Type definitions for the Instrumentation Trace Macrocell (ITM) @{ */ -/** \brief Structure type to access the Instrumentation Trace Macrocell Register (ITM). + /** \brief Structure type to access the Instrumentation Trace Macrocell Register (ITM). */ -typedef struct -{ - __O union - { - __O uint8_t u8; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 8-bit */ - __O uint16_t u16; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 16-bit */ - __O uint32_t u32; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 32-bit */ - } PORT [32]; /*!< Offset: 0x000 ( /W) ITM Stimulus Port Registers */ - uint32_t RESERVED0[864]; - __IO uint32_t TER; /*!< Offset: 0xE00 (R/W) ITM Trace Enable Register */ - uint32_t RESERVED1[15]; - __IO uint32_t TPR; /*!< Offset: 0xE40 (R/W) ITM Trace Privilege Register */ - uint32_t RESERVED2[15]; - __IO uint32_t TCR; /*!< Offset: 0xE80 (R/W) ITM Trace Control Register */ - uint32_t RESERVED3[29]; - __O uint32_t IWR; /*!< Offset: 0xEF8 ( /W) ITM Integration Write Register */ - __I uint32_t IRR; /*!< Offset: 0xEFC (R/ ) ITM Integration Read Register */ - __IO uint32_t IMCR; /*!< Offset: 0xF00 (R/W) ITM Integration Mode Control Register */ - uint32_t RESERVED4[43]; - __O uint32_t LAR; /*!< Offset: 0xFB0 ( /W) ITM Lock Access Register */ - __I uint32_t LSR; /*!< Offset: 0xFB4 (R/ ) ITM Lock Status Register */ - uint32_t RESERVED5[6]; - __I uint32_t PID4; /*!< Offset: 0xFD0 (R/ ) ITM Peripheral Identification Register #4 */ - __I uint32_t PID5; /*!< Offset: 0xFD4 (R/ ) ITM Peripheral Identification Register #5 */ - __I uint32_t PID6; /*!< Offset: 0xFD8 (R/ ) ITM Peripheral Identification Register #6 */ - __I uint32_t PID7; /*!< Offset: 0xFDC (R/ ) ITM Peripheral Identification Register #7 */ - __I uint32_t PID0; /*!< Offset: 0xFE0 (R/ ) ITM Peripheral Identification Register #0 */ - __I uint32_t PID1; /*!< Offset: 0xFE4 (R/ ) ITM Peripheral Identification Register #1 */ - __I uint32_t PID2; /*!< Offset: 0xFE8 (R/ ) ITM Peripheral Identification Register #2 */ - __I uint32_t PID3; /*!< Offset: 0xFEC (R/ ) ITM Peripheral Identification Register #3 */ - __I uint32_t CID0; /*!< Offset: 0xFF0 (R/ ) ITM Component Identification Register #0 */ - __I uint32_t CID1; /*!< Offset: 0xFF4 (R/ ) ITM Component Identification Register #1 */ - __I uint32_t CID2; /*!< Offset: 0xFF8 (R/ ) ITM Component Identification Register #2 */ - __I uint32_t CID3; /*!< Offset: 0xFFC (R/ ) ITM Component Identification Register #3 */ -} ITM_Type; + typedef struct + { + __O union + { + __O uint8_t u8; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 8-bit */ + __O uint16_t u16; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 16-bit */ + __O uint32_t u32; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 32-bit */ + } PORT[32]; /*!< Offset: 0x000 ( /W) ITM Stimulus Port Registers */ + uint32_t RESERVED0[864]; + __IO uint32_t TER; /*!< Offset: 0xE00 (R/W) ITM Trace Enable Register */ + uint32_t RESERVED1[15]; + __IO uint32_t TPR; /*!< Offset: 0xE40 (R/W) ITM Trace Privilege Register */ + uint32_t RESERVED2[15]; + __IO uint32_t TCR; /*!< Offset: 0xE80 (R/W) ITM Trace Control Register */ + uint32_t RESERVED3[29]; + __O uint32_t IWR; /*!< Offset: 0xEF8 ( /W) ITM Integration Write Register */ + __I uint32_t IRR; /*!< Offset: 0xEFC (R/ ) ITM Integration Read Register */ + __IO uint32_t IMCR; /*!< Offset: 0xF00 (R/W) ITM Integration Mode Control Register */ + uint32_t RESERVED4[43]; + __O uint32_t LAR; /*!< Offset: 0xFB0 ( /W) ITM Lock Access Register */ + __I uint32_t LSR; /*!< Offset: 0xFB4 (R/ ) ITM Lock Status Register */ + uint32_t RESERVED5[6]; + __I uint32_t PID4; /*!< Offset: 0xFD0 (R/ ) ITM Peripheral Identification Register #4 */ + __I uint32_t PID5; /*!< Offset: 0xFD4 (R/ ) ITM Peripheral Identification Register #5 */ + __I uint32_t PID6; /*!< Offset: 0xFD8 (R/ ) ITM Peripheral Identification Register #6 */ + __I uint32_t PID7; /*!< Offset: 0xFDC (R/ ) ITM Peripheral Identification Register #7 */ + __I uint32_t PID0; /*!< Offset: 0xFE0 (R/ ) ITM Peripheral Identification Register #0 */ + __I uint32_t PID1; /*!< Offset: 0xFE4 (R/ ) ITM Peripheral Identification Register #1 */ + __I uint32_t PID2; /*!< Offset: 0xFE8 (R/ ) ITM Peripheral Identification Register #2 */ + __I uint32_t PID3; /*!< Offset: 0xFEC (R/ ) ITM Peripheral Identification Register #3 */ + __I uint32_t CID0; /*!< Offset: 0xFF0 (R/ ) ITM Component Identification Register #0 */ + __I uint32_t CID1; /*!< Offset: 0xFF4 (R/ ) ITM Component Identification Register #1 */ + __I uint32_t CID2; /*!< Offset: 0xFF8 (R/ ) ITM Component Identification Register #2 */ + __I uint32_t CID3; /*!< Offset: 0xFFC (R/ ) ITM Component Identification Register #3 */ + } ITM_Type; /* ITM Trace Privilege Register Definitions */ -#define ITM_TPR_PRIVMASK_Pos 0 /*!< ITM TPR: PRIVMASK Position */ -#define ITM_TPR_PRIVMASK_Msk (0xFUL << ITM_TPR_PRIVMASK_Pos) /*!< ITM TPR: PRIVMASK Mask */ +#define ITM_TPR_PRIVMASK_Pos 0 /*!< ITM TPR: PRIVMASK Position */ +#define ITM_TPR_PRIVMASK_Msk (0xFUL << ITM_TPR_PRIVMASK_Pos) /*!< ITM TPR: PRIVMASK Mask */ /* ITM Trace Control Register Definitions */ -#define ITM_TCR_BUSY_Pos 23 /*!< ITM TCR: BUSY Position */ -#define ITM_TCR_BUSY_Msk (1UL << ITM_TCR_BUSY_Pos) /*!< ITM TCR: BUSY Mask */ +#define ITM_TCR_BUSY_Pos 23 /*!< ITM TCR: BUSY Position */ +#define ITM_TCR_BUSY_Msk (1UL << ITM_TCR_BUSY_Pos) /*!< ITM TCR: BUSY Mask */ -#define ITM_TCR_TraceBusID_Pos 16 /*!< ITM TCR: ATBID Position */ -#define ITM_TCR_TraceBusID_Msk (0x7FUL << ITM_TCR_TraceBusID_Pos) /*!< ITM TCR: ATBID Mask */ +#define ITM_TCR_TraceBusID_Pos 16 /*!< ITM TCR: ATBID Position */ +#define ITM_TCR_TraceBusID_Msk (0x7FUL << ITM_TCR_TraceBusID_Pos) /*!< ITM TCR: ATBID Mask */ -#define ITM_TCR_GTSFREQ_Pos 10 /*!< ITM TCR: Global timestamp frequency Position */ -#define ITM_TCR_GTSFREQ_Msk (3UL << ITM_TCR_GTSFREQ_Pos) /*!< ITM TCR: Global timestamp frequency Mask */ +#define ITM_TCR_GTSFREQ_Pos 10 /*!< ITM TCR: Global timestamp frequency Position */ +#define ITM_TCR_GTSFREQ_Msk (3UL << ITM_TCR_GTSFREQ_Pos) /*!< ITM TCR: Global timestamp frequency Mask */ -#define ITM_TCR_TSPrescale_Pos 8 /*!< ITM TCR: TSPrescale Position */ -#define ITM_TCR_TSPrescale_Msk (3UL << ITM_TCR_TSPrescale_Pos) /*!< ITM TCR: TSPrescale Mask */ +#define ITM_TCR_TSPrescale_Pos 8 /*!< ITM TCR: TSPrescale Position */ +#define ITM_TCR_TSPrescale_Msk (3UL << ITM_TCR_TSPrescale_Pos) /*!< ITM TCR: TSPrescale Mask */ -#define ITM_TCR_SWOENA_Pos 4 /*!< ITM TCR: SWOENA Position */ -#define ITM_TCR_SWOENA_Msk (1UL << ITM_TCR_SWOENA_Pos) /*!< ITM TCR: SWOENA Mask */ +#define ITM_TCR_SWOENA_Pos 4 /*!< ITM TCR: SWOENA Position */ +#define ITM_TCR_SWOENA_Msk (1UL << ITM_TCR_SWOENA_Pos) /*!< ITM TCR: SWOENA Mask */ -#define ITM_TCR_DWTENA_Pos 3 /*!< ITM TCR: DWTENA Position */ -#define ITM_TCR_DWTENA_Msk (1UL << ITM_TCR_DWTENA_Pos) /*!< ITM TCR: DWTENA Mask */ +#define ITM_TCR_DWTENA_Pos 3 /*!< ITM TCR: DWTENA Position */ +#define ITM_TCR_DWTENA_Msk (1UL << ITM_TCR_DWTENA_Pos) /*!< ITM TCR: DWTENA Mask */ -#define ITM_TCR_SYNCENA_Pos 2 /*!< ITM TCR: SYNCENA Position */ -#define ITM_TCR_SYNCENA_Msk (1UL << ITM_TCR_SYNCENA_Pos) /*!< ITM TCR: SYNCENA Mask */ +#define ITM_TCR_SYNCENA_Pos 2 /*!< ITM TCR: SYNCENA Position */ +#define ITM_TCR_SYNCENA_Msk (1UL << ITM_TCR_SYNCENA_Pos) /*!< ITM TCR: SYNCENA Mask */ -#define ITM_TCR_TSENA_Pos 1 /*!< ITM TCR: TSENA Position */ -#define ITM_TCR_TSENA_Msk (1UL << ITM_TCR_TSENA_Pos) /*!< ITM TCR: TSENA Mask */ +#define ITM_TCR_TSENA_Pos 1 /*!< ITM TCR: TSENA Position */ +#define ITM_TCR_TSENA_Msk (1UL << ITM_TCR_TSENA_Pos) /*!< ITM TCR: TSENA Mask */ -#define ITM_TCR_ITMENA_Pos 0 /*!< ITM TCR: ITM Enable bit Position */ -#define ITM_TCR_ITMENA_Msk (1UL << ITM_TCR_ITMENA_Pos) /*!< ITM TCR: ITM Enable bit Mask */ +#define ITM_TCR_ITMENA_Pos 0 /*!< ITM TCR: ITM Enable bit Position */ +#define ITM_TCR_ITMENA_Msk (1UL << ITM_TCR_ITMENA_Pos) /*!< ITM TCR: ITM Enable bit Mask */ /* ITM Integration Write Register Definitions */ -#define ITM_IWR_ATVALIDM_Pos 0 /*!< ITM IWR: ATVALIDM Position */ -#define ITM_IWR_ATVALIDM_Msk (1UL << ITM_IWR_ATVALIDM_Pos) /*!< ITM IWR: ATVALIDM Mask */ +#define ITM_IWR_ATVALIDM_Pos 0 /*!< ITM IWR: ATVALIDM Position */ +#define ITM_IWR_ATVALIDM_Msk (1UL << ITM_IWR_ATVALIDM_Pos) /*!< ITM IWR: ATVALIDM Mask */ /* ITM Integration Read Register Definitions */ -#define ITM_IRR_ATREADYM_Pos 0 /*!< ITM IRR: ATREADYM Position */ -#define ITM_IRR_ATREADYM_Msk (1UL << ITM_IRR_ATREADYM_Pos) /*!< ITM IRR: ATREADYM Mask */ +#define ITM_IRR_ATREADYM_Pos 0 /*!< ITM IRR: ATREADYM Position */ +#define ITM_IRR_ATREADYM_Msk (1UL << ITM_IRR_ATREADYM_Pos) /*!< ITM IRR: ATREADYM Mask */ /* ITM Integration Mode Control Register Definitions */ -#define ITM_IMCR_INTEGRATION_Pos 0 /*!< ITM IMCR: INTEGRATION Position */ -#define ITM_IMCR_INTEGRATION_Msk (1UL << ITM_IMCR_INTEGRATION_Pos) /*!< ITM IMCR: INTEGRATION Mask */ +#define ITM_IMCR_INTEGRATION_Pos 0 /*!< ITM IMCR: INTEGRATION Position */ +#define ITM_IMCR_INTEGRATION_Msk (1UL << ITM_IMCR_INTEGRATION_Pos) /*!< ITM IMCR: INTEGRATION Mask */ /* ITM Lock Status Register Definitions */ -#define ITM_LSR_ByteAcc_Pos 2 /*!< ITM LSR: ByteAcc Position */ -#define ITM_LSR_ByteAcc_Msk (1UL << ITM_LSR_ByteAcc_Pos) /*!< ITM LSR: ByteAcc Mask */ +#define ITM_LSR_ByteAcc_Pos 2 /*!< ITM LSR: ByteAcc Position */ +#define ITM_LSR_ByteAcc_Msk (1UL << ITM_LSR_ByteAcc_Pos) /*!< ITM LSR: ByteAcc Mask */ -#define ITM_LSR_Access_Pos 1 /*!< ITM LSR: Access Position */ -#define ITM_LSR_Access_Msk (1UL << ITM_LSR_Access_Pos) /*!< ITM LSR: Access Mask */ +#define ITM_LSR_Access_Pos 1 /*!< ITM LSR: Access Position */ +#define ITM_LSR_Access_Msk (1UL << ITM_LSR_Access_Pos) /*!< ITM LSR: Access Mask */ -#define ITM_LSR_Present_Pos 0 /*!< ITM LSR: Present Position */ -#define ITM_LSR_Present_Msk (1UL << ITM_LSR_Present_Pos) /*!< ITM LSR: Present Mask */ +#define ITM_LSR_Present_Pos 0 /*!< ITM LSR: Present Position */ +#define ITM_LSR_Present_Msk (1UL << ITM_LSR_Present_Pos) /*!< ITM LSR: Present Mask */ -/*@}*/ /* end of group CMSIS_ITM */ + /*@}*/ /* end of group CMSIS_ITM */ - -/** \ingroup CMSIS_core_register + /** \ingroup CMSIS_core_register \defgroup CMSIS_DWT Data Watchpoint and Trace (DWT) \brief Type definitions for the Data Watchpoint and Trace (DWT) @{ */ -/** \brief Structure type to access the Data Watchpoint and Trace Register (DWT). + /** \brief Structure type to access the Data Watchpoint and Trace Register (DWT). */ -typedef struct -{ - __IO uint32_t CTRL; /*!< Offset: 0x000 (R/W) Control Register */ - __IO uint32_t CYCCNT; /*!< Offset: 0x004 (R/W) Cycle Count Register */ - __IO uint32_t CPICNT; /*!< Offset: 0x008 (R/W) CPI Count Register */ - __IO uint32_t EXCCNT; /*!< Offset: 0x00C (R/W) Exception Overhead Count Register */ - __IO uint32_t SLEEPCNT; /*!< Offset: 0x010 (R/W) Sleep Count Register */ - __IO uint32_t LSUCNT; /*!< Offset: 0x014 (R/W) LSU Count Register */ - __IO uint32_t FOLDCNT; /*!< Offset: 0x018 (R/W) Folded-instruction Count Register */ - __I uint32_t PCSR; /*!< Offset: 0x01C (R/ ) Program Counter Sample Register */ - __IO uint32_t COMP0; /*!< Offset: 0x020 (R/W) Comparator Register 0 */ - __IO uint32_t MASK0; /*!< Offset: 0x024 (R/W) Mask Register 0 */ - __IO uint32_t FUNCTION0; /*!< Offset: 0x028 (R/W) Function Register 0 */ - uint32_t RESERVED0[1]; - __IO uint32_t COMP1; /*!< Offset: 0x030 (R/W) Comparator Register 1 */ - __IO uint32_t MASK1; /*!< Offset: 0x034 (R/W) Mask Register 1 */ - __IO uint32_t FUNCTION1; /*!< Offset: 0x038 (R/W) Function Register 1 */ - uint32_t RESERVED1[1]; - __IO uint32_t COMP2; /*!< Offset: 0x040 (R/W) Comparator Register 2 */ - __IO uint32_t MASK2; /*!< Offset: 0x044 (R/W) Mask Register 2 */ - __IO uint32_t FUNCTION2; /*!< Offset: 0x048 (R/W) Function Register 2 */ - uint32_t RESERVED2[1]; - __IO uint32_t COMP3; /*!< Offset: 0x050 (R/W) Comparator Register 3 */ - __IO uint32_t MASK3; /*!< Offset: 0x054 (R/W) Mask Register 3 */ - __IO uint32_t FUNCTION3; /*!< Offset: 0x058 (R/W) Function Register 3 */ -} DWT_Type; + typedef struct + { + __IO uint32_t CTRL; /*!< Offset: 0x000 (R/W) Control Register */ + __IO uint32_t CYCCNT; /*!< Offset: 0x004 (R/W) Cycle Count Register */ + __IO uint32_t CPICNT; /*!< Offset: 0x008 (R/W) CPI Count Register */ + __IO uint32_t EXCCNT; /*!< Offset: 0x00C (R/W) Exception Overhead Count Register */ + __IO uint32_t SLEEPCNT; /*!< Offset: 0x010 (R/W) Sleep Count Register */ + __IO uint32_t LSUCNT; /*!< Offset: 0x014 (R/W) LSU Count Register */ + __IO uint32_t FOLDCNT; /*!< Offset: 0x018 (R/W) Folded-instruction Count Register */ + __I uint32_t PCSR; /*!< Offset: 0x01C (R/ ) Program Counter Sample Register */ + __IO uint32_t COMP0; /*!< Offset: 0x020 (R/W) Comparator Register 0 */ + __IO uint32_t MASK0; /*!< Offset: 0x024 (R/W) Mask Register 0 */ + __IO uint32_t FUNCTION0; /*!< Offset: 0x028 (R/W) Function Register 0 */ + uint32_t RESERVED0[1]; + __IO uint32_t COMP1; /*!< Offset: 0x030 (R/W) Comparator Register 1 */ + __IO uint32_t MASK1; /*!< Offset: 0x034 (R/W) Mask Register 1 */ + __IO uint32_t FUNCTION1; /*!< Offset: 0x038 (R/W) Function Register 1 */ + uint32_t RESERVED1[1]; + __IO uint32_t COMP2; /*!< Offset: 0x040 (R/W) Comparator Register 2 */ + __IO uint32_t MASK2; /*!< Offset: 0x044 (R/W) Mask Register 2 */ + __IO uint32_t FUNCTION2; /*!< Offset: 0x048 (R/W) Function Register 2 */ + uint32_t RESERVED2[1]; + __IO uint32_t COMP3; /*!< Offset: 0x050 (R/W) Comparator Register 3 */ + __IO uint32_t MASK3; /*!< Offset: 0x054 (R/W) Mask Register 3 */ + __IO uint32_t FUNCTION3; /*!< Offset: 0x058 (R/W) Function Register 3 */ + } DWT_Type; /* DWT Control Register Definitions */ -#define DWT_CTRL_NUMCOMP_Pos 28 /*!< DWT CTRL: NUMCOMP Position */ -#define DWT_CTRL_NUMCOMP_Msk (0xFUL << DWT_CTRL_NUMCOMP_Pos) /*!< DWT CTRL: NUMCOMP Mask */ +#define DWT_CTRL_NUMCOMP_Pos 28 /*!< DWT CTRL: NUMCOMP Position */ +#define DWT_CTRL_NUMCOMP_Msk (0xFUL << DWT_CTRL_NUMCOMP_Pos) /*!< DWT CTRL: NUMCOMP Mask */ -#define DWT_CTRL_NOTRCPKT_Pos 27 /*!< DWT CTRL: NOTRCPKT Position */ -#define DWT_CTRL_NOTRCPKT_Msk (0x1UL << DWT_CTRL_NOTRCPKT_Pos) /*!< DWT CTRL: NOTRCPKT Mask */ +#define DWT_CTRL_NOTRCPKT_Pos 27 /*!< DWT CTRL: NOTRCPKT Position */ +#define DWT_CTRL_NOTRCPKT_Msk (0x1UL << DWT_CTRL_NOTRCPKT_Pos) /*!< DWT CTRL: NOTRCPKT Mask */ -#define DWT_CTRL_NOEXTTRIG_Pos 26 /*!< DWT CTRL: NOEXTTRIG Position */ -#define DWT_CTRL_NOEXTTRIG_Msk (0x1UL << DWT_CTRL_NOEXTTRIG_Pos) /*!< DWT CTRL: NOEXTTRIG Mask */ +#define DWT_CTRL_NOEXTTRIG_Pos 26 /*!< DWT CTRL: NOEXTTRIG Position */ +#define DWT_CTRL_NOEXTTRIG_Msk (0x1UL << DWT_CTRL_NOEXTTRIG_Pos) /*!< DWT CTRL: NOEXTTRIG Mask */ -#define DWT_CTRL_NOCYCCNT_Pos 25 /*!< DWT CTRL: NOCYCCNT Position */ -#define DWT_CTRL_NOCYCCNT_Msk (0x1UL << DWT_CTRL_NOCYCCNT_Pos) /*!< DWT CTRL: NOCYCCNT Mask */ +#define DWT_CTRL_NOCYCCNT_Pos 25 /*!< DWT CTRL: NOCYCCNT Position */ +#define DWT_CTRL_NOCYCCNT_Msk (0x1UL << DWT_CTRL_NOCYCCNT_Pos) /*!< DWT CTRL: NOCYCCNT Mask */ -#define DWT_CTRL_NOPRFCNT_Pos 24 /*!< DWT CTRL: NOPRFCNT Position */ -#define DWT_CTRL_NOPRFCNT_Msk (0x1UL << DWT_CTRL_NOPRFCNT_Pos) /*!< DWT CTRL: NOPRFCNT Mask */ +#define DWT_CTRL_NOPRFCNT_Pos 24 /*!< DWT CTRL: NOPRFCNT Position */ +#define DWT_CTRL_NOPRFCNT_Msk (0x1UL << DWT_CTRL_NOPRFCNT_Pos) /*!< DWT CTRL: NOPRFCNT Mask */ -#define DWT_CTRL_CYCEVTENA_Pos 22 /*!< DWT CTRL: CYCEVTENA Position */ -#define DWT_CTRL_CYCEVTENA_Msk (0x1UL << DWT_CTRL_CYCEVTENA_Pos) /*!< DWT CTRL: CYCEVTENA Mask */ +#define DWT_CTRL_CYCEVTENA_Pos 22 /*!< DWT CTRL: CYCEVTENA Position */ +#define DWT_CTRL_CYCEVTENA_Msk (0x1UL << DWT_CTRL_CYCEVTENA_Pos) /*!< DWT CTRL: CYCEVTENA Mask */ -#define DWT_CTRL_FOLDEVTENA_Pos 21 /*!< DWT CTRL: FOLDEVTENA Position */ -#define DWT_CTRL_FOLDEVTENA_Msk (0x1UL << DWT_CTRL_FOLDEVTENA_Pos) /*!< DWT CTRL: FOLDEVTENA Mask */ +#define DWT_CTRL_FOLDEVTENA_Pos 21 /*!< DWT CTRL: FOLDEVTENA Position */ +#define DWT_CTRL_FOLDEVTENA_Msk (0x1UL << DWT_CTRL_FOLDEVTENA_Pos) /*!< DWT CTRL: FOLDEVTENA Mask */ -#define DWT_CTRL_LSUEVTENA_Pos 20 /*!< DWT CTRL: LSUEVTENA Position */ -#define DWT_CTRL_LSUEVTENA_Msk (0x1UL << DWT_CTRL_LSUEVTENA_Pos) /*!< DWT CTRL: LSUEVTENA Mask */ +#define DWT_CTRL_LSUEVTENA_Pos 20 /*!< DWT CTRL: LSUEVTENA Position */ +#define DWT_CTRL_LSUEVTENA_Msk (0x1UL << DWT_CTRL_LSUEVTENA_Pos) /*!< DWT CTRL: LSUEVTENA Mask */ -#define DWT_CTRL_SLEEPEVTENA_Pos 19 /*!< DWT CTRL: SLEEPEVTENA Position */ -#define DWT_CTRL_SLEEPEVTENA_Msk (0x1UL << DWT_CTRL_SLEEPEVTENA_Pos) /*!< DWT CTRL: SLEEPEVTENA Mask */ +#define DWT_CTRL_SLEEPEVTENA_Pos 19 /*!< DWT CTRL: SLEEPEVTENA Position */ +#define DWT_CTRL_SLEEPEVTENA_Msk (0x1UL << DWT_CTRL_SLEEPEVTENA_Pos) /*!< DWT CTRL: SLEEPEVTENA Mask */ -#define DWT_CTRL_EXCEVTENA_Pos 18 /*!< DWT CTRL: EXCEVTENA Position */ -#define DWT_CTRL_EXCEVTENA_Msk (0x1UL << DWT_CTRL_EXCEVTENA_Pos) /*!< DWT CTRL: EXCEVTENA Mask */ +#define DWT_CTRL_EXCEVTENA_Pos 18 /*!< DWT CTRL: EXCEVTENA Position */ +#define DWT_CTRL_EXCEVTENA_Msk (0x1UL << DWT_CTRL_EXCEVTENA_Pos) /*!< DWT CTRL: EXCEVTENA Mask */ -#define DWT_CTRL_CPIEVTENA_Pos 17 /*!< DWT CTRL: CPIEVTENA Position */ -#define DWT_CTRL_CPIEVTENA_Msk (0x1UL << DWT_CTRL_CPIEVTENA_Pos) /*!< DWT CTRL: CPIEVTENA Mask */ +#define DWT_CTRL_CPIEVTENA_Pos 17 /*!< DWT CTRL: CPIEVTENA Position */ +#define DWT_CTRL_CPIEVTENA_Msk (0x1UL << DWT_CTRL_CPIEVTENA_Pos) /*!< DWT CTRL: CPIEVTENA Mask */ -#define DWT_CTRL_EXCTRCENA_Pos 16 /*!< DWT CTRL: EXCTRCENA Position */ -#define DWT_CTRL_EXCTRCENA_Msk (0x1UL << DWT_CTRL_EXCTRCENA_Pos) /*!< DWT CTRL: EXCTRCENA Mask */ +#define DWT_CTRL_EXCTRCENA_Pos 16 /*!< DWT CTRL: EXCTRCENA Position */ +#define DWT_CTRL_EXCTRCENA_Msk (0x1UL << DWT_CTRL_EXCTRCENA_Pos) /*!< DWT CTRL: EXCTRCENA Mask */ -#define DWT_CTRL_PCSAMPLENA_Pos 12 /*!< DWT CTRL: PCSAMPLENA Position */ -#define DWT_CTRL_PCSAMPLENA_Msk (0x1UL << DWT_CTRL_PCSAMPLENA_Pos) /*!< DWT CTRL: PCSAMPLENA Mask */ +#define DWT_CTRL_PCSAMPLENA_Pos 12 /*!< DWT CTRL: PCSAMPLENA Position */ +#define DWT_CTRL_PCSAMPLENA_Msk (0x1UL << DWT_CTRL_PCSAMPLENA_Pos) /*!< DWT CTRL: PCSAMPLENA Mask */ -#define DWT_CTRL_SYNCTAP_Pos 10 /*!< DWT CTRL: SYNCTAP Position */ -#define DWT_CTRL_SYNCTAP_Msk (0x3UL << DWT_CTRL_SYNCTAP_Pos) /*!< DWT CTRL: SYNCTAP Mask */ +#define DWT_CTRL_SYNCTAP_Pos 10 /*!< DWT CTRL: SYNCTAP Position */ +#define DWT_CTRL_SYNCTAP_Msk (0x3UL << DWT_CTRL_SYNCTAP_Pos) /*!< DWT CTRL: SYNCTAP Mask */ -#define DWT_CTRL_CYCTAP_Pos 9 /*!< DWT CTRL: CYCTAP Position */ -#define DWT_CTRL_CYCTAP_Msk (0x1UL << DWT_CTRL_CYCTAP_Pos) /*!< DWT CTRL: CYCTAP Mask */ +#define DWT_CTRL_CYCTAP_Pos 9 /*!< DWT CTRL: CYCTAP Position */ +#define DWT_CTRL_CYCTAP_Msk (0x1UL << DWT_CTRL_CYCTAP_Pos) /*!< DWT CTRL: CYCTAP Mask */ -#define DWT_CTRL_POSTINIT_Pos 5 /*!< DWT CTRL: POSTINIT Position */ -#define DWT_CTRL_POSTINIT_Msk (0xFUL << DWT_CTRL_POSTINIT_Pos) /*!< DWT CTRL: POSTINIT Mask */ +#define DWT_CTRL_POSTINIT_Pos 5 /*!< DWT CTRL: POSTINIT Position */ +#define DWT_CTRL_POSTINIT_Msk (0xFUL << DWT_CTRL_POSTINIT_Pos) /*!< DWT CTRL: POSTINIT Mask */ -#define DWT_CTRL_POSTPRESET_Pos 1 /*!< DWT CTRL: POSTPRESET Position */ -#define DWT_CTRL_POSTPRESET_Msk (0xFUL << DWT_CTRL_POSTPRESET_Pos) /*!< DWT CTRL: POSTPRESET Mask */ +#define DWT_CTRL_POSTPRESET_Pos 1 /*!< DWT CTRL: POSTPRESET Position */ +#define DWT_CTRL_POSTPRESET_Msk (0xFUL << DWT_CTRL_POSTPRESET_Pos) /*!< DWT CTRL: POSTPRESET Mask */ -#define DWT_CTRL_CYCCNTENA_Pos 0 /*!< DWT CTRL: CYCCNTENA Position */ -#define DWT_CTRL_CYCCNTENA_Msk (0x1UL << DWT_CTRL_CYCCNTENA_Pos) /*!< DWT CTRL: CYCCNTENA Mask */ +#define DWT_CTRL_CYCCNTENA_Pos 0 /*!< DWT CTRL: CYCCNTENA Position */ +#define DWT_CTRL_CYCCNTENA_Msk (0x1UL << DWT_CTRL_CYCCNTENA_Pos) /*!< DWT CTRL: CYCCNTENA Mask */ /* DWT CPI Count Register Definitions */ -#define DWT_CPICNT_CPICNT_Pos 0 /*!< DWT CPICNT: CPICNT Position */ -#define DWT_CPICNT_CPICNT_Msk (0xFFUL << DWT_CPICNT_CPICNT_Pos) /*!< DWT CPICNT: CPICNT Mask */ +#define DWT_CPICNT_CPICNT_Pos 0 /*!< DWT CPICNT: CPICNT Position */ +#define DWT_CPICNT_CPICNT_Msk (0xFFUL << DWT_CPICNT_CPICNT_Pos) /*!< DWT CPICNT: CPICNT Mask */ /* DWT Exception Overhead Count Register Definitions */ -#define DWT_EXCCNT_EXCCNT_Pos 0 /*!< DWT EXCCNT: EXCCNT Position */ -#define DWT_EXCCNT_EXCCNT_Msk (0xFFUL << DWT_EXCCNT_EXCCNT_Pos) /*!< DWT EXCCNT: EXCCNT Mask */ +#define DWT_EXCCNT_EXCCNT_Pos 0 /*!< DWT EXCCNT: EXCCNT Position */ +#define DWT_EXCCNT_EXCCNT_Msk (0xFFUL << DWT_EXCCNT_EXCCNT_Pos) /*!< DWT EXCCNT: EXCCNT Mask */ /* DWT Sleep Count Register Definitions */ -#define DWT_SLEEPCNT_SLEEPCNT_Pos 0 /*!< DWT SLEEPCNT: SLEEPCNT Position */ -#define DWT_SLEEPCNT_SLEEPCNT_Msk (0xFFUL << DWT_SLEEPCNT_SLEEPCNT_Pos) /*!< DWT SLEEPCNT: SLEEPCNT Mask */ +#define DWT_SLEEPCNT_SLEEPCNT_Pos 0 /*!< DWT SLEEPCNT: SLEEPCNT Position */ +#define DWT_SLEEPCNT_SLEEPCNT_Msk (0xFFUL << DWT_SLEEPCNT_SLEEPCNT_Pos) /*!< DWT SLEEPCNT: SLEEPCNT Mask */ /* DWT LSU Count Register Definitions */ -#define DWT_LSUCNT_LSUCNT_Pos 0 /*!< DWT LSUCNT: LSUCNT Position */ -#define DWT_LSUCNT_LSUCNT_Msk (0xFFUL << DWT_LSUCNT_LSUCNT_Pos) /*!< DWT LSUCNT: LSUCNT Mask */ +#define DWT_LSUCNT_LSUCNT_Pos 0 /*!< DWT LSUCNT: LSUCNT Position */ +#define DWT_LSUCNT_LSUCNT_Msk (0xFFUL << DWT_LSUCNT_LSUCNT_Pos) /*!< DWT LSUCNT: LSUCNT Mask */ /* DWT Folded-instruction Count Register Definitions */ -#define DWT_FOLDCNT_FOLDCNT_Pos 0 /*!< DWT FOLDCNT: FOLDCNT Position */ -#define DWT_FOLDCNT_FOLDCNT_Msk (0xFFUL << DWT_FOLDCNT_FOLDCNT_Pos) /*!< DWT FOLDCNT: FOLDCNT Mask */ +#define DWT_FOLDCNT_FOLDCNT_Pos 0 /*!< DWT FOLDCNT: FOLDCNT Position */ +#define DWT_FOLDCNT_FOLDCNT_Msk (0xFFUL << DWT_FOLDCNT_FOLDCNT_Pos) /*!< DWT FOLDCNT: FOLDCNT Mask */ /* DWT Comparator Mask Register Definitions */ -#define DWT_MASK_MASK_Pos 0 /*!< DWT MASK: MASK Position */ -#define DWT_MASK_MASK_Msk (0x1FUL << DWT_MASK_MASK_Pos) /*!< DWT MASK: MASK Mask */ +#define DWT_MASK_MASK_Pos 0 /*!< DWT MASK: MASK Position */ +#define DWT_MASK_MASK_Msk (0x1FUL << DWT_MASK_MASK_Pos) /*!< DWT MASK: MASK Mask */ /* DWT Comparator Function Register Definitions */ -#define DWT_FUNCTION_MATCHED_Pos 24 /*!< DWT FUNCTION: MATCHED Position */ -#define DWT_FUNCTION_MATCHED_Msk (0x1UL << DWT_FUNCTION_MATCHED_Pos) /*!< DWT FUNCTION: MATCHED Mask */ +#define DWT_FUNCTION_MATCHED_Pos 24 /*!< DWT FUNCTION: MATCHED Position */ +#define DWT_FUNCTION_MATCHED_Msk (0x1UL << DWT_FUNCTION_MATCHED_Pos) /*!< DWT FUNCTION: MATCHED Mask */ -#define DWT_FUNCTION_DATAVADDR1_Pos 16 /*!< DWT FUNCTION: DATAVADDR1 Position */ -#define DWT_FUNCTION_DATAVADDR1_Msk (0xFUL << DWT_FUNCTION_DATAVADDR1_Pos) /*!< DWT FUNCTION: DATAVADDR1 Mask */ +#define DWT_FUNCTION_DATAVADDR1_Pos 16 /*!< DWT FUNCTION: DATAVADDR1 Position */ +#define DWT_FUNCTION_DATAVADDR1_Msk (0xFUL << DWT_FUNCTION_DATAVADDR1_Pos) /*!< DWT FUNCTION: DATAVADDR1 Mask */ -#define DWT_FUNCTION_DATAVADDR0_Pos 12 /*!< DWT FUNCTION: DATAVADDR0 Position */ -#define DWT_FUNCTION_DATAVADDR0_Msk (0xFUL << DWT_FUNCTION_DATAVADDR0_Pos) /*!< DWT FUNCTION: DATAVADDR0 Mask */ +#define DWT_FUNCTION_DATAVADDR0_Pos 12 /*!< DWT FUNCTION: DATAVADDR0 Position */ +#define DWT_FUNCTION_DATAVADDR0_Msk (0xFUL << DWT_FUNCTION_DATAVADDR0_Pos) /*!< DWT FUNCTION: DATAVADDR0 Mask */ -#define DWT_FUNCTION_DATAVSIZE_Pos 10 /*!< DWT FUNCTION: DATAVSIZE Position */ -#define DWT_FUNCTION_DATAVSIZE_Msk (0x3UL << DWT_FUNCTION_DATAVSIZE_Pos) /*!< DWT FUNCTION: DATAVSIZE Mask */ +#define DWT_FUNCTION_DATAVSIZE_Pos 10 /*!< DWT FUNCTION: DATAVSIZE Position */ +#define DWT_FUNCTION_DATAVSIZE_Msk (0x3UL << DWT_FUNCTION_DATAVSIZE_Pos) /*!< DWT FUNCTION: DATAVSIZE Mask */ -#define DWT_FUNCTION_LNK1ENA_Pos 9 /*!< DWT FUNCTION: LNK1ENA Position */ -#define DWT_FUNCTION_LNK1ENA_Msk (0x1UL << DWT_FUNCTION_LNK1ENA_Pos) /*!< DWT FUNCTION: LNK1ENA Mask */ +#define DWT_FUNCTION_LNK1ENA_Pos 9 /*!< DWT FUNCTION: LNK1ENA Position */ +#define DWT_FUNCTION_LNK1ENA_Msk (0x1UL << DWT_FUNCTION_LNK1ENA_Pos) /*!< DWT FUNCTION: LNK1ENA Mask */ -#define DWT_FUNCTION_DATAVMATCH_Pos 8 /*!< DWT FUNCTION: DATAVMATCH Position */ -#define DWT_FUNCTION_DATAVMATCH_Msk (0x1UL << DWT_FUNCTION_DATAVMATCH_Pos) /*!< DWT FUNCTION: DATAVMATCH Mask */ +#define DWT_FUNCTION_DATAVMATCH_Pos 8 /*!< DWT FUNCTION: DATAVMATCH Position */ +#define DWT_FUNCTION_DATAVMATCH_Msk (0x1UL << DWT_FUNCTION_DATAVMATCH_Pos) /*!< DWT FUNCTION: DATAVMATCH Mask */ -#define DWT_FUNCTION_CYCMATCH_Pos 7 /*!< DWT FUNCTION: CYCMATCH Position */ -#define DWT_FUNCTION_CYCMATCH_Msk (0x1UL << DWT_FUNCTION_CYCMATCH_Pos) /*!< DWT FUNCTION: CYCMATCH Mask */ +#define DWT_FUNCTION_CYCMATCH_Pos 7 /*!< DWT FUNCTION: CYCMATCH Position */ +#define DWT_FUNCTION_CYCMATCH_Msk (0x1UL << DWT_FUNCTION_CYCMATCH_Pos) /*!< DWT FUNCTION: CYCMATCH Mask */ -#define DWT_FUNCTION_EMITRANGE_Pos 5 /*!< DWT FUNCTION: EMITRANGE Position */ -#define DWT_FUNCTION_EMITRANGE_Msk (0x1UL << DWT_FUNCTION_EMITRANGE_Pos) /*!< DWT FUNCTION: EMITRANGE Mask */ +#define DWT_FUNCTION_EMITRANGE_Pos 5 /*!< DWT FUNCTION: EMITRANGE Position */ +#define DWT_FUNCTION_EMITRANGE_Msk (0x1UL << DWT_FUNCTION_EMITRANGE_Pos) /*!< DWT FUNCTION: EMITRANGE Mask */ -#define DWT_FUNCTION_FUNCTION_Pos 0 /*!< DWT FUNCTION: FUNCTION Position */ -#define DWT_FUNCTION_FUNCTION_Msk (0xFUL << DWT_FUNCTION_FUNCTION_Pos) /*!< DWT FUNCTION: FUNCTION Mask */ +#define DWT_FUNCTION_FUNCTION_Pos 0 /*!< DWT FUNCTION: FUNCTION Position */ +#define DWT_FUNCTION_FUNCTION_Msk (0xFUL << DWT_FUNCTION_FUNCTION_Pos) /*!< DWT FUNCTION: FUNCTION Mask */ -/*@}*/ /* end of group CMSIS_DWT */ + /*@}*/ /* end of group CMSIS_DWT */ - -/** \ingroup CMSIS_core_register + /** \ingroup CMSIS_core_register \defgroup CMSIS_TPI Trace Port Interface (TPI) \brief Type definitions for the Trace Port Interface (TPI) @{ */ -/** \brief Structure type to access the Trace Port Interface Register (TPI). + /** \brief Structure type to access the Trace Port Interface Register (TPI). */ -typedef struct -{ - __IO uint32_t SSPSR; /*!< Offset: 0x000 (R/ ) Supported Parallel Port Size Register */ - __IO uint32_t CSPSR; /*!< Offset: 0x004 (R/W) Current Parallel Port Size Register */ - uint32_t RESERVED0[2]; - __IO uint32_t ACPR; /*!< Offset: 0x010 (R/W) Asynchronous Clock Prescaler Register */ - uint32_t RESERVED1[55]; - __IO uint32_t SPPR; /*!< Offset: 0x0F0 (R/W) Selected Pin Protocol Register */ - uint32_t RESERVED2[131]; - __I uint32_t FFSR; /*!< Offset: 0x300 (R/ ) Formatter and Flush Status Register */ - __IO uint32_t FFCR; /*!< Offset: 0x304 (R/W) Formatter and Flush Control Register */ - __I uint32_t FSCR; /*!< Offset: 0x308 (R/ ) Formatter Synchronization Counter Register */ - uint32_t RESERVED3[759]; - __I uint32_t TRIGGER; /*!< Offset: 0xEE8 (R/ ) TRIGGER */ - __I uint32_t FIFO0; /*!< Offset: 0xEEC (R/ ) Integration ETM Data */ - __I uint32_t ITATBCTR2; /*!< Offset: 0xEF0 (R/ ) ITATBCTR2 */ - uint32_t RESERVED4[1]; - __I uint32_t ITATBCTR0; /*!< Offset: 0xEF8 (R/ ) ITATBCTR0 */ - __I uint32_t FIFO1; /*!< Offset: 0xEFC (R/ ) Integration ITM Data */ - __IO uint32_t ITCTRL; /*!< Offset: 0xF00 (R/W) Integration Mode Control */ - uint32_t RESERVED5[39]; - __IO uint32_t CLAIMSET; /*!< Offset: 0xFA0 (R/W) Claim tag set */ - __IO uint32_t CLAIMCLR; /*!< Offset: 0xFA4 (R/W) Claim tag clear */ - uint32_t RESERVED7[8]; - __I uint32_t DEVID; /*!< Offset: 0xFC8 (R/ ) TPIU_DEVID */ - __I uint32_t DEVTYPE; /*!< Offset: 0xFCC (R/ ) TPIU_DEVTYPE */ -} TPI_Type; + typedef struct + { + __IO uint32_t SSPSR; /*!< Offset: 0x000 (R/ ) Supported Parallel Port Size Register */ + __IO uint32_t CSPSR; /*!< Offset: 0x004 (R/W) Current Parallel Port Size Register */ + uint32_t RESERVED0[2]; + __IO uint32_t ACPR; /*!< Offset: 0x010 (R/W) Asynchronous Clock Prescaler Register */ + uint32_t RESERVED1[55]; + __IO uint32_t SPPR; /*!< Offset: 0x0F0 (R/W) Selected Pin Protocol Register */ + uint32_t RESERVED2[131]; + __I uint32_t FFSR; /*!< Offset: 0x300 (R/ ) Formatter and Flush Status Register */ + __IO uint32_t FFCR; /*!< Offset: 0x304 (R/W) Formatter and Flush Control Register */ + __I uint32_t FSCR; /*!< Offset: 0x308 (R/ ) Formatter Synchronization Counter Register */ + uint32_t RESERVED3[759]; + __I uint32_t TRIGGER; /*!< Offset: 0xEE8 (R/ ) TRIGGER */ + __I uint32_t FIFO0; /*!< Offset: 0xEEC (R/ ) Integration ETM Data */ + __I uint32_t ITATBCTR2; /*!< Offset: 0xEF0 (R/ ) ITATBCTR2 */ + uint32_t RESERVED4[1]; + __I uint32_t ITATBCTR0; /*!< Offset: 0xEF8 (R/ ) ITATBCTR0 */ + __I uint32_t FIFO1; /*!< Offset: 0xEFC (R/ ) Integration ITM Data */ + __IO uint32_t ITCTRL; /*!< Offset: 0xF00 (R/W) Integration Mode Control */ + uint32_t RESERVED5[39]; + __IO uint32_t CLAIMSET; /*!< Offset: 0xFA0 (R/W) Claim tag set */ + __IO uint32_t CLAIMCLR; /*!< Offset: 0xFA4 (R/W) Claim tag clear */ + uint32_t RESERVED7[8]; + __I uint32_t DEVID; /*!< Offset: 0xFC8 (R/ ) TPIU_DEVID */ + __I uint32_t DEVTYPE; /*!< Offset: 0xFCC (R/ ) TPIU_DEVTYPE */ + } TPI_Type; /* TPI Asynchronous Clock Prescaler Register Definitions */ -#define TPI_ACPR_PRESCALER_Pos 0 /*!< TPI ACPR: PRESCALER Position */ -#define TPI_ACPR_PRESCALER_Msk (0x1FFFUL << TPI_ACPR_PRESCALER_Pos) /*!< TPI ACPR: PRESCALER Mask */ +#define TPI_ACPR_PRESCALER_Pos 0 /*!< TPI ACPR: PRESCALER Position */ +#define TPI_ACPR_PRESCALER_Msk (0x1FFFUL << TPI_ACPR_PRESCALER_Pos) /*!< TPI ACPR: PRESCALER Mask */ /* TPI Selected Pin Protocol Register Definitions */ -#define TPI_SPPR_TXMODE_Pos 0 /*!< TPI SPPR: TXMODE Position */ -#define TPI_SPPR_TXMODE_Msk (0x3UL << TPI_SPPR_TXMODE_Pos) /*!< TPI SPPR: TXMODE Mask */ +#define TPI_SPPR_TXMODE_Pos 0 /*!< TPI SPPR: TXMODE Position */ +#define TPI_SPPR_TXMODE_Msk (0x3UL << TPI_SPPR_TXMODE_Pos) /*!< TPI SPPR: TXMODE Mask */ /* TPI Formatter and Flush Status Register Definitions */ -#define TPI_FFSR_FtNonStop_Pos 3 /*!< TPI FFSR: FtNonStop Position */ -#define TPI_FFSR_FtNonStop_Msk (0x1UL << TPI_FFSR_FtNonStop_Pos) /*!< TPI FFSR: FtNonStop Mask */ +#define TPI_FFSR_FtNonStop_Pos 3 /*!< TPI FFSR: FtNonStop Position */ +#define TPI_FFSR_FtNonStop_Msk (0x1UL << TPI_FFSR_FtNonStop_Pos) /*!< TPI FFSR: FtNonStop Mask */ -#define TPI_FFSR_TCPresent_Pos 2 /*!< TPI FFSR: TCPresent Position */ -#define TPI_FFSR_TCPresent_Msk (0x1UL << TPI_FFSR_TCPresent_Pos) /*!< TPI FFSR: TCPresent Mask */ +#define TPI_FFSR_TCPresent_Pos 2 /*!< TPI FFSR: TCPresent Position */ +#define TPI_FFSR_TCPresent_Msk (0x1UL << TPI_FFSR_TCPresent_Pos) /*!< TPI FFSR: TCPresent Mask */ -#define TPI_FFSR_FtStopped_Pos 1 /*!< TPI FFSR: FtStopped Position */ -#define TPI_FFSR_FtStopped_Msk (0x1UL << TPI_FFSR_FtStopped_Pos) /*!< TPI FFSR: FtStopped Mask */ +#define TPI_FFSR_FtStopped_Pos 1 /*!< TPI FFSR: FtStopped Position */ +#define TPI_FFSR_FtStopped_Msk (0x1UL << TPI_FFSR_FtStopped_Pos) /*!< TPI FFSR: FtStopped Mask */ -#define TPI_FFSR_FlInProg_Pos 0 /*!< TPI FFSR: FlInProg Position */ -#define TPI_FFSR_FlInProg_Msk (0x1UL << TPI_FFSR_FlInProg_Pos) /*!< TPI FFSR: FlInProg Mask */ +#define TPI_FFSR_FlInProg_Pos 0 /*!< TPI FFSR: FlInProg Position */ +#define TPI_FFSR_FlInProg_Msk (0x1UL << TPI_FFSR_FlInProg_Pos) /*!< TPI FFSR: FlInProg Mask */ /* TPI Formatter and Flush Control Register Definitions */ -#define TPI_FFCR_TrigIn_Pos 8 /*!< TPI FFCR: TrigIn Position */ -#define TPI_FFCR_TrigIn_Msk (0x1UL << TPI_FFCR_TrigIn_Pos) /*!< TPI FFCR: TrigIn Mask */ +#define TPI_FFCR_TrigIn_Pos 8 /*!< TPI FFCR: TrigIn Position */ +#define TPI_FFCR_TrigIn_Msk (0x1UL << TPI_FFCR_TrigIn_Pos) /*!< TPI FFCR: TrigIn Mask */ -#define TPI_FFCR_EnFCont_Pos 1 /*!< TPI FFCR: EnFCont Position */ -#define TPI_FFCR_EnFCont_Msk (0x1UL << TPI_FFCR_EnFCont_Pos) /*!< TPI FFCR: EnFCont Mask */ +#define TPI_FFCR_EnFCont_Pos 1 /*!< TPI FFCR: EnFCont Position */ +#define TPI_FFCR_EnFCont_Msk (0x1UL << TPI_FFCR_EnFCont_Pos) /*!< TPI FFCR: EnFCont Mask */ /* TPI TRIGGER Register Definitions */ -#define TPI_TRIGGER_TRIGGER_Pos 0 /*!< TPI TRIGGER: TRIGGER Position */ -#define TPI_TRIGGER_TRIGGER_Msk (0x1UL << TPI_TRIGGER_TRIGGER_Pos) /*!< TPI TRIGGER: TRIGGER Mask */ +#define TPI_TRIGGER_TRIGGER_Pos 0 /*!< TPI TRIGGER: TRIGGER Position */ +#define TPI_TRIGGER_TRIGGER_Msk (0x1UL << TPI_TRIGGER_TRIGGER_Pos) /*!< TPI TRIGGER: TRIGGER Mask */ /* TPI Integration ETM Data Register Definitions (FIFO0) */ -#define TPI_FIFO0_ITM_ATVALID_Pos 29 /*!< TPI FIFO0: ITM_ATVALID Position */ -#define TPI_FIFO0_ITM_ATVALID_Msk (0x3UL << TPI_FIFO0_ITM_ATVALID_Pos) /*!< TPI FIFO0: ITM_ATVALID Mask */ +#define TPI_FIFO0_ITM_ATVALID_Pos 29 /*!< TPI FIFO0: ITM_ATVALID Position */ +#define TPI_FIFO0_ITM_ATVALID_Msk (0x3UL << TPI_FIFO0_ITM_ATVALID_Pos) /*!< TPI FIFO0: ITM_ATVALID Mask */ -#define TPI_FIFO0_ITM_bytecount_Pos 27 /*!< TPI FIFO0: ITM_bytecount Position */ -#define TPI_FIFO0_ITM_bytecount_Msk (0x3UL << TPI_FIFO0_ITM_bytecount_Pos) /*!< TPI FIFO0: ITM_bytecount Mask */ +#define TPI_FIFO0_ITM_bytecount_Pos 27 /*!< TPI FIFO0: ITM_bytecount Position */ +#define TPI_FIFO0_ITM_bytecount_Msk (0x3UL << TPI_FIFO0_ITM_bytecount_Pos) /*!< TPI FIFO0: ITM_bytecount Mask */ -#define TPI_FIFO0_ETM_ATVALID_Pos 26 /*!< TPI FIFO0: ETM_ATVALID Position */ -#define TPI_FIFO0_ETM_ATVALID_Msk (0x3UL << TPI_FIFO0_ETM_ATVALID_Pos) /*!< TPI FIFO0: ETM_ATVALID Mask */ +#define TPI_FIFO0_ETM_ATVALID_Pos 26 /*!< TPI FIFO0: ETM_ATVALID Position */ +#define TPI_FIFO0_ETM_ATVALID_Msk (0x3UL << TPI_FIFO0_ETM_ATVALID_Pos) /*!< TPI FIFO0: ETM_ATVALID Mask */ -#define TPI_FIFO0_ETM_bytecount_Pos 24 /*!< TPI FIFO0: ETM_bytecount Position */ -#define TPI_FIFO0_ETM_bytecount_Msk (0x3UL << TPI_FIFO0_ETM_bytecount_Pos) /*!< TPI FIFO0: ETM_bytecount Mask */ +#define TPI_FIFO0_ETM_bytecount_Pos 24 /*!< TPI FIFO0: ETM_bytecount Position */ +#define TPI_FIFO0_ETM_bytecount_Msk (0x3UL << TPI_FIFO0_ETM_bytecount_Pos) /*!< TPI FIFO0: ETM_bytecount Mask */ -#define TPI_FIFO0_ETM2_Pos 16 /*!< TPI FIFO0: ETM2 Position */ -#define TPI_FIFO0_ETM2_Msk (0xFFUL << TPI_FIFO0_ETM2_Pos) /*!< TPI FIFO0: ETM2 Mask */ +#define TPI_FIFO0_ETM2_Pos 16 /*!< TPI FIFO0: ETM2 Position */ +#define TPI_FIFO0_ETM2_Msk (0xFFUL << TPI_FIFO0_ETM2_Pos) /*!< TPI FIFO0: ETM2 Mask */ -#define TPI_FIFO0_ETM1_Pos 8 /*!< TPI FIFO0: ETM1 Position */ -#define TPI_FIFO0_ETM1_Msk (0xFFUL << TPI_FIFO0_ETM1_Pos) /*!< TPI FIFO0: ETM1 Mask */ +#define TPI_FIFO0_ETM1_Pos 8 /*!< TPI FIFO0: ETM1 Position */ +#define TPI_FIFO0_ETM1_Msk (0xFFUL << TPI_FIFO0_ETM1_Pos) /*!< TPI FIFO0: ETM1 Mask */ -#define TPI_FIFO0_ETM0_Pos 0 /*!< TPI FIFO0: ETM0 Position */ -#define TPI_FIFO0_ETM0_Msk (0xFFUL << TPI_FIFO0_ETM0_Pos) /*!< TPI FIFO0: ETM0 Mask */ +#define TPI_FIFO0_ETM0_Pos 0 /*!< TPI FIFO0: ETM0 Position */ +#define TPI_FIFO0_ETM0_Msk (0xFFUL << TPI_FIFO0_ETM0_Pos) /*!< TPI FIFO0: ETM0 Mask */ /* TPI ITATBCTR2 Register Definitions */ -#define TPI_ITATBCTR2_ATREADY_Pos 0 /*!< TPI ITATBCTR2: ATREADY Position */ -#define TPI_ITATBCTR2_ATREADY_Msk (0x1UL << TPI_ITATBCTR2_ATREADY_Pos) /*!< TPI ITATBCTR2: ATREADY Mask */ +#define TPI_ITATBCTR2_ATREADY_Pos 0 /*!< TPI ITATBCTR2: ATREADY Position */ +#define TPI_ITATBCTR2_ATREADY_Msk (0x1UL << TPI_ITATBCTR2_ATREADY_Pos) /*!< TPI ITATBCTR2: ATREADY Mask */ /* TPI Integration ITM Data Register Definitions (FIFO1) */ -#define TPI_FIFO1_ITM_ATVALID_Pos 29 /*!< TPI FIFO1: ITM_ATVALID Position */ -#define TPI_FIFO1_ITM_ATVALID_Msk (0x3UL << TPI_FIFO1_ITM_ATVALID_Pos) /*!< TPI FIFO1: ITM_ATVALID Mask */ +#define TPI_FIFO1_ITM_ATVALID_Pos 29 /*!< TPI FIFO1: ITM_ATVALID Position */ +#define TPI_FIFO1_ITM_ATVALID_Msk (0x3UL << TPI_FIFO1_ITM_ATVALID_Pos) /*!< TPI FIFO1: ITM_ATVALID Mask */ -#define TPI_FIFO1_ITM_bytecount_Pos 27 /*!< TPI FIFO1: ITM_bytecount Position */ -#define TPI_FIFO1_ITM_bytecount_Msk (0x3UL << TPI_FIFO1_ITM_bytecount_Pos) /*!< TPI FIFO1: ITM_bytecount Mask */ +#define TPI_FIFO1_ITM_bytecount_Pos 27 /*!< TPI FIFO1: ITM_bytecount Position */ +#define TPI_FIFO1_ITM_bytecount_Msk (0x3UL << TPI_FIFO1_ITM_bytecount_Pos) /*!< TPI FIFO1: ITM_bytecount Mask */ -#define TPI_FIFO1_ETM_ATVALID_Pos 26 /*!< TPI FIFO1: ETM_ATVALID Position */ -#define TPI_FIFO1_ETM_ATVALID_Msk (0x3UL << TPI_FIFO1_ETM_ATVALID_Pos) /*!< TPI FIFO1: ETM_ATVALID Mask */ +#define TPI_FIFO1_ETM_ATVALID_Pos 26 /*!< TPI FIFO1: ETM_ATVALID Position */ +#define TPI_FIFO1_ETM_ATVALID_Msk (0x3UL << TPI_FIFO1_ETM_ATVALID_Pos) /*!< TPI FIFO1: ETM_ATVALID Mask */ -#define TPI_FIFO1_ETM_bytecount_Pos 24 /*!< TPI FIFO1: ETM_bytecount Position */ -#define TPI_FIFO1_ETM_bytecount_Msk (0x3UL << TPI_FIFO1_ETM_bytecount_Pos) /*!< TPI FIFO1: ETM_bytecount Mask */ +#define TPI_FIFO1_ETM_bytecount_Pos 24 /*!< TPI FIFO1: ETM_bytecount Position */ +#define TPI_FIFO1_ETM_bytecount_Msk (0x3UL << TPI_FIFO1_ETM_bytecount_Pos) /*!< TPI FIFO1: ETM_bytecount Mask */ -#define TPI_FIFO1_ITM2_Pos 16 /*!< TPI FIFO1: ITM2 Position */ -#define TPI_FIFO1_ITM2_Msk (0xFFUL << TPI_FIFO1_ITM2_Pos) /*!< TPI FIFO1: ITM2 Mask */ +#define TPI_FIFO1_ITM2_Pos 16 /*!< TPI FIFO1: ITM2 Position */ +#define TPI_FIFO1_ITM2_Msk (0xFFUL << TPI_FIFO1_ITM2_Pos) /*!< TPI FIFO1: ITM2 Mask */ -#define TPI_FIFO1_ITM1_Pos 8 /*!< TPI FIFO1: ITM1 Position */ -#define TPI_FIFO1_ITM1_Msk (0xFFUL << TPI_FIFO1_ITM1_Pos) /*!< TPI FIFO1: ITM1 Mask */ +#define TPI_FIFO1_ITM1_Pos 8 /*!< TPI FIFO1: ITM1 Position */ +#define TPI_FIFO1_ITM1_Msk (0xFFUL << TPI_FIFO1_ITM1_Pos) /*!< TPI FIFO1: ITM1 Mask */ -#define TPI_FIFO1_ITM0_Pos 0 /*!< TPI FIFO1: ITM0 Position */ -#define TPI_FIFO1_ITM0_Msk (0xFFUL << TPI_FIFO1_ITM0_Pos) /*!< TPI FIFO1: ITM0 Mask */ +#define TPI_FIFO1_ITM0_Pos 0 /*!< TPI FIFO1: ITM0 Position */ +#define TPI_FIFO1_ITM0_Msk (0xFFUL << TPI_FIFO1_ITM0_Pos) /*!< TPI FIFO1: ITM0 Mask */ /* TPI ITATBCTR0 Register Definitions */ -#define TPI_ITATBCTR0_ATREADY_Pos 0 /*!< TPI ITATBCTR0: ATREADY Position */ -#define TPI_ITATBCTR0_ATREADY_Msk (0x1UL << TPI_ITATBCTR0_ATREADY_Pos) /*!< TPI ITATBCTR0: ATREADY Mask */ +#define TPI_ITATBCTR0_ATREADY_Pos 0 /*!< TPI ITATBCTR0: ATREADY Position */ +#define TPI_ITATBCTR0_ATREADY_Msk (0x1UL << TPI_ITATBCTR0_ATREADY_Pos) /*!< TPI ITATBCTR0: ATREADY Mask */ /* TPI Integration Mode Control Register Definitions */ -#define TPI_ITCTRL_Mode_Pos 0 /*!< TPI ITCTRL: Mode Position */ -#define TPI_ITCTRL_Mode_Msk (0x1UL << TPI_ITCTRL_Mode_Pos) /*!< TPI ITCTRL: Mode Mask */ +#define TPI_ITCTRL_Mode_Pos 0 /*!< TPI ITCTRL: Mode Position */ +#define TPI_ITCTRL_Mode_Msk (0x1UL << TPI_ITCTRL_Mode_Pos) /*!< TPI ITCTRL: Mode Mask */ /* TPI DEVID Register Definitions */ -#define TPI_DEVID_NRZVALID_Pos 11 /*!< TPI DEVID: NRZVALID Position */ -#define TPI_DEVID_NRZVALID_Msk (0x1UL << TPI_DEVID_NRZVALID_Pos) /*!< TPI DEVID: NRZVALID Mask */ +#define TPI_DEVID_NRZVALID_Pos 11 /*!< TPI DEVID: NRZVALID Position */ +#define TPI_DEVID_NRZVALID_Msk (0x1UL << TPI_DEVID_NRZVALID_Pos) /*!< TPI DEVID: NRZVALID Mask */ -#define TPI_DEVID_MANCVALID_Pos 10 /*!< TPI DEVID: MANCVALID Position */ -#define TPI_DEVID_MANCVALID_Msk (0x1UL << TPI_DEVID_MANCVALID_Pos) /*!< TPI DEVID: MANCVALID Mask */ +#define TPI_DEVID_MANCVALID_Pos 10 /*!< TPI DEVID: MANCVALID Position */ +#define TPI_DEVID_MANCVALID_Msk (0x1UL << TPI_DEVID_MANCVALID_Pos) /*!< TPI DEVID: MANCVALID Mask */ -#define TPI_DEVID_PTINVALID_Pos 9 /*!< TPI DEVID: PTINVALID Position */ -#define TPI_DEVID_PTINVALID_Msk (0x1UL << TPI_DEVID_PTINVALID_Pos) /*!< TPI DEVID: PTINVALID Mask */ +#define TPI_DEVID_PTINVALID_Pos 9 /*!< TPI DEVID: PTINVALID Position */ +#define TPI_DEVID_PTINVALID_Msk (0x1UL << TPI_DEVID_PTINVALID_Pos) /*!< TPI DEVID: PTINVALID Mask */ -#define TPI_DEVID_MinBufSz_Pos 6 /*!< TPI DEVID: MinBufSz Position */ -#define TPI_DEVID_MinBufSz_Msk (0x7UL << TPI_DEVID_MinBufSz_Pos) /*!< TPI DEVID: MinBufSz Mask */ +#define TPI_DEVID_MinBufSz_Pos 6 /*!< TPI DEVID: MinBufSz Position */ +#define TPI_DEVID_MinBufSz_Msk (0x7UL << TPI_DEVID_MinBufSz_Pos) /*!< TPI DEVID: MinBufSz Mask */ -#define TPI_DEVID_AsynClkIn_Pos 5 /*!< TPI DEVID: AsynClkIn Position */ -#define TPI_DEVID_AsynClkIn_Msk (0x1UL << TPI_DEVID_AsynClkIn_Pos) /*!< TPI DEVID: AsynClkIn Mask */ +#define TPI_DEVID_AsynClkIn_Pos 5 /*!< TPI DEVID: AsynClkIn Position */ +#define TPI_DEVID_AsynClkIn_Msk (0x1UL << TPI_DEVID_AsynClkIn_Pos) /*!< TPI DEVID: AsynClkIn Mask */ -#define TPI_DEVID_NrTraceInput_Pos 0 /*!< TPI DEVID: NrTraceInput Position */ -#define TPI_DEVID_NrTraceInput_Msk (0x1FUL << TPI_DEVID_NrTraceInput_Pos) /*!< TPI DEVID: NrTraceInput Mask */ +#define TPI_DEVID_NrTraceInput_Pos 0 /*!< TPI DEVID: NrTraceInput Position */ +#define TPI_DEVID_NrTraceInput_Msk (0x1FUL << TPI_DEVID_NrTraceInput_Pos) /*!< TPI DEVID: NrTraceInput Mask */ /* TPI DEVTYPE Register Definitions */ -#define TPI_DEVTYPE_SubType_Pos 0 /*!< TPI DEVTYPE: SubType Position */ -#define TPI_DEVTYPE_SubType_Msk (0xFUL << TPI_DEVTYPE_SubType_Pos) /*!< TPI DEVTYPE: SubType Mask */ +#define TPI_DEVTYPE_SubType_Pos 0 /*!< TPI DEVTYPE: SubType Position */ +#define TPI_DEVTYPE_SubType_Msk (0xFUL << TPI_DEVTYPE_SubType_Pos) /*!< TPI DEVTYPE: SubType Mask */ -#define TPI_DEVTYPE_MajorType_Pos 4 /*!< TPI DEVTYPE: MajorType Position */ -#define TPI_DEVTYPE_MajorType_Msk (0xFUL << TPI_DEVTYPE_MajorType_Pos) /*!< TPI DEVTYPE: MajorType Mask */ - -/*@}*/ /* end of group CMSIS_TPI */ +#define TPI_DEVTYPE_MajorType_Pos 4 /*!< TPI DEVTYPE: MajorType Position */ +#define TPI_DEVTYPE_MajorType_Msk (0xFUL << TPI_DEVTYPE_MajorType_Pos) /*!< TPI DEVTYPE: MajorType Mask */ + /*@}*/ /* end of group CMSIS_TPI */ #if (__MPU_PRESENT == 1) -/** \ingroup CMSIS_core_register + /** \ingroup CMSIS_core_register \defgroup CMSIS_MPU Memory Protection Unit (MPU) \brief Type definitions for the Memory Protection Unit (MPU) @{ */ -/** \brief Structure type to access the Memory Protection Unit (MPU). + /** \brief Structure type to access the Memory Protection Unit (MPU). */ -typedef struct -{ - __I uint32_t TYPE; /*!< Offset: 0x000 (R/ ) MPU Type Register */ - __IO uint32_t CTRL; /*!< Offset: 0x004 (R/W) MPU Control Register */ - __IO uint32_t RNR; /*!< Offset: 0x008 (R/W) MPU Region RNRber Register */ - __IO uint32_t RBAR; /*!< Offset: 0x00C (R/W) MPU Region Base Address Register */ - __IO uint32_t RASR; /*!< Offset: 0x010 (R/W) MPU Region Attribute and Size Register */ - __IO uint32_t RBAR_A1; /*!< Offset: 0x014 (R/W) MPU Alias 1 Region Base Address Register */ - __IO uint32_t RASR_A1; /*!< Offset: 0x018 (R/W) MPU Alias 1 Region Attribute and Size Register */ - __IO uint32_t RBAR_A2; /*!< Offset: 0x01C (R/W) MPU Alias 2 Region Base Address Register */ - __IO uint32_t RASR_A2; /*!< Offset: 0x020 (R/W) MPU Alias 2 Region Attribute and Size Register */ - __IO uint32_t RBAR_A3; /*!< Offset: 0x024 (R/W) MPU Alias 3 Region Base Address Register */ - __IO uint32_t RASR_A3; /*!< Offset: 0x028 (R/W) MPU Alias 3 Region Attribute and Size Register */ -} MPU_Type; + typedef struct + { + __I uint32_t TYPE; /*!< Offset: 0x000 (R/ ) MPU Type Register */ + __IO uint32_t CTRL; /*!< Offset: 0x004 (R/W) MPU Control Register */ + __IO uint32_t RNR; /*!< Offset: 0x008 (R/W) MPU Region RNRber Register */ + __IO uint32_t RBAR; /*!< Offset: 0x00C (R/W) MPU Region Base Address Register */ + __IO uint32_t RASR; /*!< Offset: 0x010 (R/W) MPU Region Attribute and Size Register */ + __IO uint32_t RBAR_A1; /*!< Offset: 0x014 (R/W) MPU Alias 1 Region Base Address Register */ + __IO uint32_t RASR_A1; /*!< Offset: 0x018 (R/W) MPU Alias 1 Region Attribute and Size Register */ + __IO uint32_t RBAR_A2; /*!< Offset: 0x01C (R/W) MPU Alias 2 Region Base Address Register */ + __IO uint32_t RASR_A2; /*!< Offset: 0x020 (R/W) MPU Alias 2 Region Attribute and Size Register */ + __IO uint32_t RBAR_A3; /*!< Offset: 0x024 (R/W) MPU Alias 3 Region Base Address Register */ + __IO uint32_t RASR_A3; /*!< Offset: 0x028 (R/W) MPU Alias 3 Region Attribute and Size Register */ + } MPU_Type; /* MPU Type Register */ -#define MPU_TYPE_IREGION_Pos 16 /*!< MPU TYPE: IREGION Position */ -#define MPU_TYPE_IREGION_Msk (0xFFUL << MPU_TYPE_IREGION_Pos) /*!< MPU TYPE: IREGION Mask */ +#define MPU_TYPE_IREGION_Pos 16 /*!< MPU TYPE: IREGION Position */ +#define MPU_TYPE_IREGION_Msk (0xFFUL << MPU_TYPE_IREGION_Pos) /*!< MPU TYPE: IREGION Mask */ -#define MPU_TYPE_DREGION_Pos 8 /*!< MPU TYPE: DREGION Position */ -#define MPU_TYPE_DREGION_Msk (0xFFUL << MPU_TYPE_DREGION_Pos) /*!< MPU TYPE: DREGION Mask */ +#define MPU_TYPE_DREGION_Pos 8 /*!< MPU TYPE: DREGION Position */ +#define MPU_TYPE_DREGION_Msk (0xFFUL << MPU_TYPE_DREGION_Pos) /*!< MPU TYPE: DREGION Mask */ -#define MPU_TYPE_SEPARATE_Pos 0 /*!< MPU TYPE: SEPARATE Position */ -#define MPU_TYPE_SEPARATE_Msk (1UL << MPU_TYPE_SEPARATE_Pos) /*!< MPU TYPE: SEPARATE Mask */ +#define MPU_TYPE_SEPARATE_Pos 0 /*!< MPU TYPE: SEPARATE Position */ +#define MPU_TYPE_SEPARATE_Msk (1UL << MPU_TYPE_SEPARATE_Pos) /*!< MPU TYPE: SEPARATE Mask */ /* MPU Control Register */ -#define MPU_CTRL_PRIVDEFENA_Pos 2 /*!< MPU CTRL: PRIVDEFENA Position */ -#define MPU_CTRL_PRIVDEFENA_Msk (1UL << MPU_CTRL_PRIVDEFENA_Pos) /*!< MPU CTRL: PRIVDEFENA Mask */ +#define MPU_CTRL_PRIVDEFENA_Pos 2 /*!< MPU CTRL: PRIVDEFENA Position */ +#define MPU_CTRL_PRIVDEFENA_Msk (1UL << MPU_CTRL_PRIVDEFENA_Pos) /*!< MPU CTRL: PRIVDEFENA Mask */ -#define MPU_CTRL_HFNMIENA_Pos 1 /*!< MPU CTRL: HFNMIENA Position */ -#define MPU_CTRL_HFNMIENA_Msk (1UL << MPU_CTRL_HFNMIENA_Pos) /*!< MPU CTRL: HFNMIENA Mask */ +#define MPU_CTRL_HFNMIENA_Pos 1 /*!< MPU CTRL: HFNMIENA Position */ +#define MPU_CTRL_HFNMIENA_Msk (1UL << MPU_CTRL_HFNMIENA_Pos) /*!< MPU CTRL: HFNMIENA Mask */ -#define MPU_CTRL_ENABLE_Pos 0 /*!< MPU CTRL: ENABLE Position */ -#define MPU_CTRL_ENABLE_Msk (1UL << MPU_CTRL_ENABLE_Pos) /*!< MPU CTRL: ENABLE Mask */ +#define MPU_CTRL_ENABLE_Pos 0 /*!< MPU CTRL: ENABLE Position */ +#define MPU_CTRL_ENABLE_Msk (1UL << MPU_CTRL_ENABLE_Pos) /*!< MPU CTRL: ENABLE Mask */ /* MPU Region Number Register */ -#define MPU_RNR_REGION_Pos 0 /*!< MPU RNR: REGION Position */ -#define MPU_RNR_REGION_Msk (0xFFUL << MPU_RNR_REGION_Pos) /*!< MPU RNR: REGION Mask */ +#define MPU_RNR_REGION_Pos 0 /*!< MPU RNR: REGION Position */ +#define MPU_RNR_REGION_Msk (0xFFUL << MPU_RNR_REGION_Pos) /*!< MPU RNR: REGION Mask */ /* MPU Region Base Address Register */ -#define MPU_RBAR_ADDR_Pos 5 /*!< MPU RBAR: ADDR Position */ -#define MPU_RBAR_ADDR_Msk (0x7FFFFFFUL << MPU_RBAR_ADDR_Pos) /*!< MPU RBAR: ADDR Mask */ +#define MPU_RBAR_ADDR_Pos 5 /*!< MPU RBAR: ADDR Position */ +#define MPU_RBAR_ADDR_Msk (0x7FFFFFFUL << MPU_RBAR_ADDR_Pos) /*!< MPU RBAR: ADDR Mask */ -#define MPU_RBAR_VALID_Pos 4 /*!< MPU RBAR: VALID Position */ -#define MPU_RBAR_VALID_Msk (1UL << MPU_RBAR_VALID_Pos) /*!< MPU RBAR: VALID Mask */ +#define MPU_RBAR_VALID_Pos 4 /*!< MPU RBAR: VALID Position */ +#define MPU_RBAR_VALID_Msk (1UL << MPU_RBAR_VALID_Pos) /*!< MPU RBAR: VALID Mask */ -#define MPU_RBAR_REGION_Pos 0 /*!< MPU RBAR: REGION Position */ -#define MPU_RBAR_REGION_Msk (0xFUL << MPU_RBAR_REGION_Pos) /*!< MPU RBAR: REGION Mask */ +#define MPU_RBAR_REGION_Pos 0 /*!< MPU RBAR: REGION Position */ +#define MPU_RBAR_REGION_Msk (0xFUL << MPU_RBAR_REGION_Pos) /*!< MPU RBAR: REGION Mask */ /* MPU Region Attribute and Size Register */ -#define MPU_RASR_ATTRS_Pos 16 /*!< MPU RASR: MPU Region Attribute field Position */ -#define MPU_RASR_ATTRS_Msk (0xFFFFUL << MPU_RASR_ATTRS_Pos) /*!< MPU RASR: MPU Region Attribute field Mask */ +#define MPU_RASR_ATTRS_Pos 16 /*!< MPU RASR: MPU Region Attribute field Position */ +#define MPU_RASR_ATTRS_Msk (0xFFFFUL << MPU_RASR_ATTRS_Pos) /*!< MPU RASR: MPU Region Attribute field Mask */ -#define MPU_RASR_XN_Pos 28 /*!< MPU RASR: ATTRS.XN Position */ -#define MPU_RASR_XN_Msk (1UL << MPU_RASR_XN_Pos) /*!< MPU RASR: ATTRS.XN Mask */ +#define MPU_RASR_XN_Pos 28 /*!< MPU RASR: ATTRS.XN Position */ +#define MPU_RASR_XN_Msk (1UL << MPU_RASR_XN_Pos) /*!< MPU RASR: ATTRS.XN Mask */ -#define MPU_RASR_AP_Pos 24 /*!< MPU RASR: ATTRS.AP Position */ -#define MPU_RASR_AP_Msk (0x7UL << MPU_RASR_AP_Pos) /*!< MPU RASR: ATTRS.AP Mask */ +#define MPU_RASR_AP_Pos 24 /*!< MPU RASR: ATTRS.AP Position */ +#define MPU_RASR_AP_Msk (0x7UL << MPU_RASR_AP_Pos) /*!< MPU RASR: ATTRS.AP Mask */ -#define MPU_RASR_TEX_Pos 19 /*!< MPU RASR: ATTRS.TEX Position */ -#define MPU_RASR_TEX_Msk (0x7UL << MPU_RASR_TEX_Pos) /*!< MPU RASR: ATTRS.TEX Mask */ +#define MPU_RASR_TEX_Pos 19 /*!< MPU RASR: ATTRS.TEX Position */ +#define MPU_RASR_TEX_Msk (0x7UL << MPU_RASR_TEX_Pos) /*!< MPU RASR: ATTRS.TEX Mask */ -#define MPU_RASR_S_Pos 18 /*!< MPU RASR: ATTRS.S Position */ -#define MPU_RASR_S_Msk (1UL << MPU_RASR_S_Pos) /*!< MPU RASR: ATTRS.S Mask */ +#define MPU_RASR_S_Pos 18 /*!< MPU RASR: ATTRS.S Position */ +#define MPU_RASR_S_Msk (1UL << MPU_RASR_S_Pos) /*!< MPU RASR: ATTRS.S Mask */ -#define MPU_RASR_C_Pos 17 /*!< MPU RASR: ATTRS.C Position */ -#define MPU_RASR_C_Msk (1UL << MPU_RASR_C_Pos) /*!< MPU RASR: ATTRS.C Mask */ +#define MPU_RASR_C_Pos 17 /*!< MPU RASR: ATTRS.C Position */ +#define MPU_RASR_C_Msk (1UL << MPU_RASR_C_Pos) /*!< MPU RASR: ATTRS.C Mask */ -#define MPU_RASR_B_Pos 16 /*!< MPU RASR: ATTRS.B Position */ -#define MPU_RASR_B_Msk (1UL << MPU_RASR_B_Pos) /*!< MPU RASR: ATTRS.B Mask */ +#define MPU_RASR_B_Pos 16 /*!< MPU RASR: ATTRS.B Position */ +#define MPU_RASR_B_Msk (1UL << MPU_RASR_B_Pos) /*!< MPU RASR: ATTRS.B Mask */ -#define MPU_RASR_SRD_Pos 8 /*!< MPU RASR: Sub-Region Disable Position */ -#define MPU_RASR_SRD_Msk (0xFFUL << MPU_RASR_SRD_Pos) /*!< MPU RASR: Sub-Region Disable Mask */ +#define MPU_RASR_SRD_Pos 8 /*!< MPU RASR: Sub-Region Disable Position */ +#define MPU_RASR_SRD_Msk (0xFFUL << MPU_RASR_SRD_Pos) /*!< MPU RASR: Sub-Region Disable Mask */ -#define MPU_RASR_SIZE_Pos 1 /*!< MPU RASR: Region Size Field Position */ -#define MPU_RASR_SIZE_Msk (0x1FUL << MPU_RASR_SIZE_Pos) /*!< MPU RASR: Region Size Field Mask */ +#define MPU_RASR_SIZE_Pos 1 /*!< MPU RASR: Region Size Field Position */ +#define MPU_RASR_SIZE_Msk (0x1FUL << MPU_RASR_SIZE_Pos) /*!< MPU RASR: Region Size Field Mask */ -#define MPU_RASR_ENABLE_Pos 0 /*!< MPU RASR: Region enable bit Position */ -#define MPU_RASR_ENABLE_Msk (1UL << MPU_RASR_ENABLE_Pos) /*!< MPU RASR: Region enable bit Disable Mask */ +#define MPU_RASR_ENABLE_Pos 0 /*!< MPU RASR: Region enable bit Position */ +#define MPU_RASR_ENABLE_Msk (1UL << MPU_RASR_ENABLE_Pos) /*!< MPU RASR: Region enable bit Disable Mask */ /*@} end of group CMSIS_MPU */ #endif - #if (__FPU_PRESENT == 1) -/** \ingroup CMSIS_core_register + /** \ingroup CMSIS_core_register \defgroup CMSIS_FPU Floating Point Unit (FPU) \brief Type definitions for the Floating Point Unit (FPU) @{ */ -/** \brief Structure type to access the Floating Point Unit (FPU). + /** \brief Structure type to access the Floating Point Unit (FPU). */ -typedef struct -{ - uint32_t RESERVED0[1]; - __IO uint32_t FPCCR; /*!< Offset: 0x004 (R/W) Floating-Point Context Control Register */ - __IO uint32_t FPCAR; /*!< Offset: 0x008 (R/W) Floating-Point Context Address Register */ - __IO uint32_t FPDSCR; /*!< Offset: 0x00C (R/W) Floating-Point Default Status Control Register */ - __I uint32_t MVFR0; /*!< Offset: 0x010 (R/ ) Media and FP Feature Register 0 */ - __I uint32_t MVFR1; /*!< Offset: 0x014 (R/ ) Media and FP Feature Register 1 */ -} FPU_Type; + typedef struct + { + uint32_t RESERVED0[1]; + __IO uint32_t FPCCR; /*!< Offset: 0x004 (R/W) Floating-Point Context Control Register */ + __IO uint32_t FPCAR; /*!< Offset: 0x008 (R/W) Floating-Point Context Address Register */ + __IO uint32_t FPDSCR; /*!< Offset: 0x00C (R/W) Floating-Point Default Status Control Register */ + __I uint32_t MVFR0; /*!< Offset: 0x010 (R/ ) Media and FP Feature Register 0 */ + __I uint32_t MVFR1; /*!< Offset: 0x014 (R/ ) Media and FP Feature Register 1 */ + } FPU_Type; /* Floating-Point Context Control Register */ -#define FPU_FPCCR_ASPEN_Pos 31 /*!< FPCCR: ASPEN bit Position */ -#define FPU_FPCCR_ASPEN_Msk (1UL << FPU_FPCCR_ASPEN_Pos) /*!< FPCCR: ASPEN bit Mask */ +#define FPU_FPCCR_ASPEN_Pos 31 /*!< FPCCR: ASPEN bit Position */ +#define FPU_FPCCR_ASPEN_Msk (1UL << FPU_FPCCR_ASPEN_Pos) /*!< FPCCR: ASPEN bit Mask */ -#define FPU_FPCCR_LSPEN_Pos 30 /*!< FPCCR: LSPEN Position */ -#define FPU_FPCCR_LSPEN_Msk (1UL << FPU_FPCCR_LSPEN_Pos) /*!< FPCCR: LSPEN bit Mask */ +#define FPU_FPCCR_LSPEN_Pos 30 /*!< FPCCR: LSPEN Position */ +#define FPU_FPCCR_LSPEN_Msk (1UL << FPU_FPCCR_LSPEN_Pos) /*!< FPCCR: LSPEN bit Mask */ -#define FPU_FPCCR_MONRDY_Pos 8 /*!< FPCCR: MONRDY Position */ -#define FPU_FPCCR_MONRDY_Msk (1UL << FPU_FPCCR_MONRDY_Pos) /*!< FPCCR: MONRDY bit Mask */ +#define FPU_FPCCR_MONRDY_Pos 8 /*!< FPCCR: MONRDY Position */ +#define FPU_FPCCR_MONRDY_Msk (1UL << FPU_FPCCR_MONRDY_Pos) /*!< FPCCR: MONRDY bit Mask */ -#define FPU_FPCCR_BFRDY_Pos 6 /*!< FPCCR: BFRDY Position */ -#define FPU_FPCCR_BFRDY_Msk (1UL << FPU_FPCCR_BFRDY_Pos) /*!< FPCCR: BFRDY bit Mask */ +#define FPU_FPCCR_BFRDY_Pos 6 /*!< FPCCR: BFRDY Position */ +#define FPU_FPCCR_BFRDY_Msk (1UL << FPU_FPCCR_BFRDY_Pos) /*!< FPCCR: BFRDY bit Mask */ -#define FPU_FPCCR_MMRDY_Pos 5 /*!< FPCCR: MMRDY Position */ -#define FPU_FPCCR_MMRDY_Msk (1UL << FPU_FPCCR_MMRDY_Pos) /*!< FPCCR: MMRDY bit Mask */ +#define FPU_FPCCR_MMRDY_Pos 5 /*!< FPCCR: MMRDY Position */ +#define FPU_FPCCR_MMRDY_Msk (1UL << FPU_FPCCR_MMRDY_Pos) /*!< FPCCR: MMRDY bit Mask */ -#define FPU_FPCCR_HFRDY_Pos 4 /*!< FPCCR: HFRDY Position */ -#define FPU_FPCCR_HFRDY_Msk (1UL << FPU_FPCCR_HFRDY_Pos) /*!< FPCCR: HFRDY bit Mask */ +#define FPU_FPCCR_HFRDY_Pos 4 /*!< FPCCR: HFRDY Position */ +#define FPU_FPCCR_HFRDY_Msk (1UL << FPU_FPCCR_HFRDY_Pos) /*!< FPCCR: HFRDY bit Mask */ -#define FPU_FPCCR_THREAD_Pos 3 /*!< FPCCR: processor mode bit Position */ -#define FPU_FPCCR_THREAD_Msk (1UL << FPU_FPCCR_THREAD_Pos) /*!< FPCCR: processor mode active bit Mask */ +#define FPU_FPCCR_THREAD_Pos 3 /*!< FPCCR: processor mode bit Position */ +#define FPU_FPCCR_THREAD_Msk (1UL << FPU_FPCCR_THREAD_Pos) /*!< FPCCR: processor mode active bit Mask */ -#define FPU_FPCCR_USER_Pos 1 /*!< FPCCR: privilege level bit Position */ -#define FPU_FPCCR_USER_Msk (1UL << FPU_FPCCR_USER_Pos) /*!< FPCCR: privilege level bit Mask */ +#define FPU_FPCCR_USER_Pos 1 /*!< FPCCR: privilege level bit Position */ +#define FPU_FPCCR_USER_Msk (1UL << FPU_FPCCR_USER_Pos) /*!< FPCCR: privilege level bit Mask */ -#define FPU_FPCCR_LSPACT_Pos 0 /*!< FPCCR: Lazy state preservation active bit Position */ -#define FPU_FPCCR_LSPACT_Msk (1UL << FPU_FPCCR_LSPACT_Pos) /*!< FPCCR: Lazy state preservation active bit Mask */ +#define FPU_FPCCR_LSPACT_Pos 0 /*!< FPCCR: Lazy state preservation active bit Position */ +#define FPU_FPCCR_LSPACT_Msk (1UL << FPU_FPCCR_LSPACT_Pos) /*!< FPCCR: Lazy state preservation active bit Mask */ /* Floating-Point Context Address Register */ -#define FPU_FPCAR_ADDRESS_Pos 3 /*!< FPCAR: ADDRESS bit Position */ -#define FPU_FPCAR_ADDRESS_Msk (0x1FFFFFFFUL << FPU_FPCAR_ADDRESS_Pos) /*!< FPCAR: ADDRESS bit Mask */ +#define FPU_FPCAR_ADDRESS_Pos 3 /*!< FPCAR: ADDRESS bit Position */ +#define FPU_FPCAR_ADDRESS_Msk (0x1FFFFFFFUL << FPU_FPCAR_ADDRESS_Pos) /*!< FPCAR: ADDRESS bit Mask */ /* Floating-Point Default Status Control Register */ -#define FPU_FPDSCR_AHP_Pos 26 /*!< FPDSCR: AHP bit Position */ -#define FPU_FPDSCR_AHP_Msk (1UL << FPU_FPDSCR_AHP_Pos) /*!< FPDSCR: AHP bit Mask */ +#define FPU_FPDSCR_AHP_Pos 26 /*!< FPDSCR: AHP bit Position */ +#define FPU_FPDSCR_AHP_Msk (1UL << FPU_FPDSCR_AHP_Pos) /*!< FPDSCR: AHP bit Mask */ -#define FPU_FPDSCR_DN_Pos 25 /*!< FPDSCR: DN bit Position */ -#define FPU_FPDSCR_DN_Msk (1UL << FPU_FPDSCR_DN_Pos) /*!< FPDSCR: DN bit Mask */ +#define FPU_FPDSCR_DN_Pos 25 /*!< FPDSCR: DN bit Position */ +#define FPU_FPDSCR_DN_Msk (1UL << FPU_FPDSCR_DN_Pos) /*!< FPDSCR: DN bit Mask */ -#define FPU_FPDSCR_FZ_Pos 24 /*!< FPDSCR: FZ bit Position */ -#define FPU_FPDSCR_FZ_Msk (1UL << FPU_FPDSCR_FZ_Pos) /*!< FPDSCR: FZ bit Mask */ +#define FPU_FPDSCR_FZ_Pos 24 /*!< FPDSCR: FZ bit Position */ +#define FPU_FPDSCR_FZ_Msk (1UL << FPU_FPDSCR_FZ_Pos) /*!< FPDSCR: FZ bit Mask */ -#define FPU_FPDSCR_RMode_Pos 22 /*!< FPDSCR: RMode bit Position */ -#define FPU_FPDSCR_RMode_Msk (3UL << FPU_FPDSCR_RMode_Pos) /*!< FPDSCR: RMode bit Mask */ +#define FPU_FPDSCR_RMode_Pos 22 /*!< FPDSCR: RMode bit Position */ +#define FPU_FPDSCR_RMode_Msk (3UL << FPU_FPDSCR_RMode_Pos) /*!< FPDSCR: RMode bit Mask */ /* Media and FP Feature Register 0 */ -#define FPU_MVFR0_FP_rounding_modes_Pos 28 /*!< MVFR0: FP rounding modes bits Position */ -#define FPU_MVFR0_FP_rounding_modes_Msk (0xFUL << FPU_MVFR0_FP_rounding_modes_Pos) /*!< MVFR0: FP rounding modes bits Mask */ +#define FPU_MVFR0_FP_rounding_modes_Pos 28 /*!< MVFR0: FP rounding modes bits Position */ +#define FPU_MVFR0_FP_rounding_modes_Msk (0xFUL << FPU_MVFR0_FP_rounding_modes_Pos) /*!< MVFR0: FP rounding modes bits Mask */ -#define FPU_MVFR0_Short_vectors_Pos 24 /*!< MVFR0: Short vectors bits Position */ -#define FPU_MVFR0_Short_vectors_Msk (0xFUL << FPU_MVFR0_Short_vectors_Pos) /*!< MVFR0: Short vectors bits Mask */ +#define FPU_MVFR0_Short_vectors_Pos 24 /*!< MVFR0: Short vectors bits Position */ +#define FPU_MVFR0_Short_vectors_Msk (0xFUL << FPU_MVFR0_Short_vectors_Pos) /*!< MVFR0: Short vectors bits Mask */ -#define FPU_MVFR0_Square_root_Pos 20 /*!< MVFR0: Square root bits Position */ -#define FPU_MVFR0_Square_root_Msk (0xFUL << FPU_MVFR0_Square_root_Pos) /*!< MVFR0: Square root bits Mask */ +#define FPU_MVFR0_Square_root_Pos 20 /*!< MVFR0: Square root bits Position */ +#define FPU_MVFR0_Square_root_Msk (0xFUL << FPU_MVFR0_Square_root_Pos) /*!< MVFR0: Square root bits Mask */ -#define FPU_MVFR0_Divide_Pos 16 /*!< MVFR0: Divide bits Position */ -#define FPU_MVFR0_Divide_Msk (0xFUL << FPU_MVFR0_Divide_Pos) /*!< MVFR0: Divide bits Mask */ +#define FPU_MVFR0_Divide_Pos 16 /*!< MVFR0: Divide bits Position */ +#define FPU_MVFR0_Divide_Msk (0xFUL << FPU_MVFR0_Divide_Pos) /*!< MVFR0: Divide bits Mask */ -#define FPU_MVFR0_FP_excep_trapping_Pos 12 /*!< MVFR0: FP exception trapping bits Position */ -#define FPU_MVFR0_FP_excep_trapping_Msk (0xFUL << FPU_MVFR0_FP_excep_trapping_Pos) /*!< MVFR0: FP exception trapping bits Mask */ +#define FPU_MVFR0_FP_excep_trapping_Pos 12 /*!< MVFR0: FP exception trapping bits Position */ +#define FPU_MVFR0_FP_excep_trapping_Msk (0xFUL << FPU_MVFR0_FP_excep_trapping_Pos) /*!< MVFR0: FP exception trapping bits Mask */ -#define FPU_MVFR0_Double_precision_Pos 8 /*!< MVFR0: Double-precision bits Position */ -#define FPU_MVFR0_Double_precision_Msk (0xFUL << FPU_MVFR0_Double_precision_Pos) /*!< MVFR0: Double-precision bits Mask */ +#define FPU_MVFR0_Double_precision_Pos 8 /*!< MVFR0: Double-precision bits Position */ +#define FPU_MVFR0_Double_precision_Msk (0xFUL << FPU_MVFR0_Double_precision_Pos) /*!< MVFR0: Double-precision bits Mask */ -#define FPU_MVFR0_Single_precision_Pos 4 /*!< MVFR0: Single-precision bits Position */ -#define FPU_MVFR0_Single_precision_Msk (0xFUL << FPU_MVFR0_Single_precision_Pos) /*!< MVFR0: Single-precision bits Mask */ +#define FPU_MVFR0_Single_precision_Pos 4 /*!< MVFR0: Single-precision bits Position */ +#define FPU_MVFR0_Single_precision_Msk (0xFUL << FPU_MVFR0_Single_precision_Pos) /*!< MVFR0: Single-precision bits Mask */ -#define FPU_MVFR0_A_SIMD_registers_Pos 0 /*!< MVFR0: A_SIMD registers bits Position */ -#define FPU_MVFR0_A_SIMD_registers_Msk (0xFUL << FPU_MVFR0_A_SIMD_registers_Pos) /*!< MVFR0: A_SIMD registers bits Mask */ +#define FPU_MVFR0_A_SIMD_registers_Pos 0 /*!< MVFR0: A_SIMD registers bits Position */ +#define FPU_MVFR0_A_SIMD_registers_Msk (0xFUL << FPU_MVFR0_A_SIMD_registers_Pos) /*!< MVFR0: A_SIMD registers bits Mask */ /* Media and FP Feature Register 1 */ -#define FPU_MVFR1_FP_fused_MAC_Pos 28 /*!< MVFR1: FP fused MAC bits Position */ -#define FPU_MVFR1_FP_fused_MAC_Msk (0xFUL << FPU_MVFR1_FP_fused_MAC_Pos) /*!< MVFR1: FP fused MAC bits Mask */ +#define FPU_MVFR1_FP_fused_MAC_Pos 28 /*!< MVFR1: FP fused MAC bits Position */ +#define FPU_MVFR1_FP_fused_MAC_Msk (0xFUL << FPU_MVFR1_FP_fused_MAC_Pos) /*!< MVFR1: FP fused MAC bits Mask */ -#define FPU_MVFR1_FP_HPFP_Pos 24 /*!< MVFR1: FP HPFP bits Position */ -#define FPU_MVFR1_FP_HPFP_Msk (0xFUL << FPU_MVFR1_FP_HPFP_Pos) /*!< MVFR1: FP HPFP bits Mask */ +#define FPU_MVFR1_FP_HPFP_Pos 24 /*!< MVFR1: FP HPFP bits Position */ +#define FPU_MVFR1_FP_HPFP_Msk (0xFUL << FPU_MVFR1_FP_HPFP_Pos) /*!< MVFR1: FP HPFP bits Mask */ -#define FPU_MVFR1_D_NaN_mode_Pos 4 /*!< MVFR1: D_NaN mode bits Position */ -#define FPU_MVFR1_D_NaN_mode_Msk (0xFUL << FPU_MVFR1_D_NaN_mode_Pos) /*!< MVFR1: D_NaN mode bits Mask */ +#define FPU_MVFR1_D_NaN_mode_Pos 4 /*!< MVFR1: D_NaN mode bits Position */ +#define FPU_MVFR1_D_NaN_mode_Msk (0xFUL << FPU_MVFR1_D_NaN_mode_Pos) /*!< MVFR1: D_NaN mode bits Mask */ -#define FPU_MVFR1_FtZ_mode_Pos 0 /*!< MVFR1: FtZ mode bits Position */ -#define FPU_MVFR1_FtZ_mode_Msk (0xFUL << FPU_MVFR1_FtZ_mode_Pos) /*!< MVFR1: FtZ mode bits Mask */ +#define FPU_MVFR1_FtZ_mode_Pos 0 /*!< MVFR1: FtZ mode bits Position */ +#define FPU_MVFR1_FtZ_mode_Msk (0xFUL << FPU_MVFR1_FtZ_mode_Pos) /*!< MVFR1: FtZ mode bits Mask */ /*@} end of group CMSIS_FPU */ #endif - -/** \ingroup CMSIS_core_register + /** \ingroup CMSIS_core_register \defgroup CMSIS_CoreDebug Core Debug Registers (CoreDebug) \brief Type definitions for the Core Debug Registers @{ */ -/** \brief Structure type to access the Core Debug Register (CoreDebug). + /** \brief Structure type to access the Core Debug Register (CoreDebug). */ -typedef struct -{ - __IO uint32_t DHCSR; /*!< Offset: 0x000 (R/W) Debug Halting Control and Status Register */ - __O uint32_t DCRSR; /*!< Offset: 0x004 ( /W) Debug Core Register Selector Register */ - __IO uint32_t DCRDR; /*!< Offset: 0x008 (R/W) Debug Core Register Data Register */ - __IO uint32_t DEMCR; /*!< Offset: 0x00C (R/W) Debug Exception and Monitor Control Register */ -} CoreDebug_Type; + typedef struct + { + __IO uint32_t DHCSR; /*!< Offset: 0x000 (R/W) Debug Halting Control and Status Register */ + __O uint32_t DCRSR; /*!< Offset: 0x004 ( /W) Debug Core Register Selector Register */ + __IO uint32_t DCRDR; /*!< Offset: 0x008 (R/W) Debug Core Register Data Register */ + __IO uint32_t DEMCR; /*!< Offset: 0x00C (R/W) Debug Exception and Monitor Control Register */ + } CoreDebug_Type; /* Debug Halting Control and Status Register */ -#define CoreDebug_DHCSR_DBGKEY_Pos 16 /*!< CoreDebug DHCSR: DBGKEY Position */ -#define CoreDebug_DHCSR_DBGKEY_Msk (0xFFFFUL << CoreDebug_DHCSR_DBGKEY_Pos) /*!< CoreDebug DHCSR: DBGKEY Mask */ +#define CoreDebug_DHCSR_DBGKEY_Pos 16 /*!< CoreDebug DHCSR: DBGKEY Position */ +#define CoreDebug_DHCSR_DBGKEY_Msk (0xFFFFUL << CoreDebug_DHCSR_DBGKEY_Pos) /*!< CoreDebug DHCSR: DBGKEY Mask */ -#define CoreDebug_DHCSR_S_RESET_ST_Pos 25 /*!< CoreDebug DHCSR: S_RESET_ST Position */ -#define CoreDebug_DHCSR_S_RESET_ST_Msk (1UL << CoreDebug_DHCSR_S_RESET_ST_Pos) /*!< CoreDebug DHCSR: S_RESET_ST Mask */ +#define CoreDebug_DHCSR_S_RESET_ST_Pos 25 /*!< CoreDebug DHCSR: S_RESET_ST Position */ +#define CoreDebug_DHCSR_S_RESET_ST_Msk (1UL << CoreDebug_DHCSR_S_RESET_ST_Pos) /*!< CoreDebug DHCSR: S_RESET_ST Mask */ -#define CoreDebug_DHCSR_S_RETIRE_ST_Pos 24 /*!< CoreDebug DHCSR: S_RETIRE_ST Position */ -#define CoreDebug_DHCSR_S_RETIRE_ST_Msk (1UL << CoreDebug_DHCSR_S_RETIRE_ST_Pos) /*!< CoreDebug DHCSR: S_RETIRE_ST Mask */ +#define CoreDebug_DHCSR_S_RETIRE_ST_Pos 24 /*!< CoreDebug DHCSR: S_RETIRE_ST Position */ +#define CoreDebug_DHCSR_S_RETIRE_ST_Msk (1UL << CoreDebug_DHCSR_S_RETIRE_ST_Pos) /*!< CoreDebug DHCSR: S_RETIRE_ST Mask */ -#define CoreDebug_DHCSR_S_LOCKUP_Pos 19 /*!< CoreDebug DHCSR: S_LOCKUP Position */ -#define CoreDebug_DHCSR_S_LOCKUP_Msk (1UL << CoreDebug_DHCSR_S_LOCKUP_Pos) /*!< CoreDebug DHCSR: S_LOCKUP Mask */ +#define CoreDebug_DHCSR_S_LOCKUP_Pos 19 /*!< CoreDebug DHCSR: S_LOCKUP Position */ +#define CoreDebug_DHCSR_S_LOCKUP_Msk (1UL << CoreDebug_DHCSR_S_LOCKUP_Pos) /*!< CoreDebug DHCSR: S_LOCKUP Mask */ -#define CoreDebug_DHCSR_S_SLEEP_Pos 18 /*!< CoreDebug DHCSR: S_SLEEP Position */ -#define CoreDebug_DHCSR_S_SLEEP_Msk (1UL << CoreDebug_DHCSR_S_SLEEP_Pos) /*!< CoreDebug DHCSR: S_SLEEP Mask */ +#define CoreDebug_DHCSR_S_SLEEP_Pos 18 /*!< CoreDebug DHCSR: S_SLEEP Position */ +#define CoreDebug_DHCSR_S_SLEEP_Msk (1UL << CoreDebug_DHCSR_S_SLEEP_Pos) /*!< CoreDebug DHCSR: S_SLEEP Mask */ -#define CoreDebug_DHCSR_S_HALT_Pos 17 /*!< CoreDebug DHCSR: S_HALT Position */ -#define CoreDebug_DHCSR_S_HALT_Msk (1UL << CoreDebug_DHCSR_S_HALT_Pos) /*!< CoreDebug DHCSR: S_HALT Mask */ +#define CoreDebug_DHCSR_S_HALT_Pos 17 /*!< CoreDebug DHCSR: S_HALT Position */ +#define CoreDebug_DHCSR_S_HALT_Msk (1UL << CoreDebug_DHCSR_S_HALT_Pos) /*!< CoreDebug DHCSR: S_HALT Mask */ -#define CoreDebug_DHCSR_S_REGRDY_Pos 16 /*!< CoreDebug DHCSR: S_REGRDY Position */ -#define CoreDebug_DHCSR_S_REGRDY_Msk (1UL << CoreDebug_DHCSR_S_REGRDY_Pos) /*!< CoreDebug DHCSR: S_REGRDY Mask */ +#define CoreDebug_DHCSR_S_REGRDY_Pos 16 /*!< CoreDebug DHCSR: S_REGRDY Position */ +#define CoreDebug_DHCSR_S_REGRDY_Msk (1UL << CoreDebug_DHCSR_S_REGRDY_Pos) /*!< CoreDebug DHCSR: S_REGRDY Mask */ -#define CoreDebug_DHCSR_C_SNAPSTALL_Pos 5 /*!< CoreDebug DHCSR: C_SNAPSTALL Position */ -#define CoreDebug_DHCSR_C_SNAPSTALL_Msk (1UL << CoreDebug_DHCSR_C_SNAPSTALL_Pos) /*!< CoreDebug DHCSR: C_SNAPSTALL Mask */ +#define CoreDebug_DHCSR_C_SNAPSTALL_Pos 5 /*!< CoreDebug DHCSR: C_SNAPSTALL Position */ +#define CoreDebug_DHCSR_C_SNAPSTALL_Msk (1UL << CoreDebug_DHCSR_C_SNAPSTALL_Pos) /*!< CoreDebug DHCSR: C_SNAPSTALL Mask */ -#define CoreDebug_DHCSR_C_MASKINTS_Pos 3 /*!< CoreDebug DHCSR: C_MASKINTS Position */ -#define CoreDebug_DHCSR_C_MASKINTS_Msk (1UL << CoreDebug_DHCSR_C_MASKINTS_Pos) /*!< CoreDebug DHCSR: C_MASKINTS Mask */ +#define CoreDebug_DHCSR_C_MASKINTS_Pos 3 /*!< CoreDebug DHCSR: C_MASKINTS Position */ +#define CoreDebug_DHCSR_C_MASKINTS_Msk (1UL << CoreDebug_DHCSR_C_MASKINTS_Pos) /*!< CoreDebug DHCSR: C_MASKINTS Mask */ -#define CoreDebug_DHCSR_C_STEP_Pos 2 /*!< CoreDebug DHCSR: C_STEP Position */ -#define CoreDebug_DHCSR_C_STEP_Msk (1UL << CoreDebug_DHCSR_C_STEP_Pos) /*!< CoreDebug DHCSR: C_STEP Mask */ +#define CoreDebug_DHCSR_C_STEP_Pos 2 /*!< CoreDebug DHCSR: C_STEP Position */ +#define CoreDebug_DHCSR_C_STEP_Msk (1UL << CoreDebug_DHCSR_C_STEP_Pos) /*!< CoreDebug DHCSR: C_STEP Mask */ -#define CoreDebug_DHCSR_C_HALT_Pos 1 /*!< CoreDebug DHCSR: C_HALT Position */ -#define CoreDebug_DHCSR_C_HALT_Msk (1UL << CoreDebug_DHCSR_C_HALT_Pos) /*!< CoreDebug DHCSR: C_HALT Mask */ +#define CoreDebug_DHCSR_C_HALT_Pos 1 /*!< CoreDebug DHCSR: C_HALT Position */ +#define CoreDebug_DHCSR_C_HALT_Msk (1UL << CoreDebug_DHCSR_C_HALT_Pos) /*!< CoreDebug DHCSR: C_HALT Mask */ -#define CoreDebug_DHCSR_C_DEBUGEN_Pos 0 /*!< CoreDebug DHCSR: C_DEBUGEN Position */ -#define CoreDebug_DHCSR_C_DEBUGEN_Msk (1UL << CoreDebug_DHCSR_C_DEBUGEN_Pos) /*!< CoreDebug DHCSR: C_DEBUGEN Mask */ +#define CoreDebug_DHCSR_C_DEBUGEN_Pos 0 /*!< CoreDebug DHCSR: C_DEBUGEN Position */ +#define CoreDebug_DHCSR_C_DEBUGEN_Msk (1UL << CoreDebug_DHCSR_C_DEBUGEN_Pos) /*!< CoreDebug DHCSR: C_DEBUGEN Mask */ /* Debug Core Register Selector Register */ -#define CoreDebug_DCRSR_REGWnR_Pos 16 /*!< CoreDebug DCRSR: REGWnR Position */ -#define CoreDebug_DCRSR_REGWnR_Msk (1UL << CoreDebug_DCRSR_REGWnR_Pos) /*!< CoreDebug DCRSR: REGWnR Mask */ +#define CoreDebug_DCRSR_REGWnR_Pos 16 /*!< CoreDebug DCRSR: REGWnR Position */ +#define CoreDebug_DCRSR_REGWnR_Msk (1UL << CoreDebug_DCRSR_REGWnR_Pos) /*!< CoreDebug DCRSR: REGWnR Mask */ -#define CoreDebug_DCRSR_REGSEL_Pos 0 /*!< CoreDebug DCRSR: REGSEL Position */ -#define CoreDebug_DCRSR_REGSEL_Msk (0x1FUL << CoreDebug_DCRSR_REGSEL_Pos) /*!< CoreDebug DCRSR: REGSEL Mask */ +#define CoreDebug_DCRSR_REGSEL_Pos 0 /*!< CoreDebug DCRSR: REGSEL Position */ +#define CoreDebug_DCRSR_REGSEL_Msk (0x1FUL << CoreDebug_DCRSR_REGSEL_Pos) /*!< CoreDebug DCRSR: REGSEL Mask */ /* Debug Exception and Monitor Control Register */ -#define CoreDebug_DEMCR_TRCENA_Pos 24 /*!< CoreDebug DEMCR: TRCENA Position */ -#define CoreDebug_DEMCR_TRCENA_Msk (1UL << CoreDebug_DEMCR_TRCENA_Pos) /*!< CoreDebug DEMCR: TRCENA Mask */ +#define CoreDebug_DEMCR_TRCENA_Pos 24 /*!< CoreDebug DEMCR: TRCENA Position */ +#define CoreDebug_DEMCR_TRCENA_Msk (1UL << CoreDebug_DEMCR_TRCENA_Pos) /*!< CoreDebug DEMCR: TRCENA Mask */ -#define CoreDebug_DEMCR_MON_REQ_Pos 19 /*!< CoreDebug DEMCR: MON_REQ Position */ -#define CoreDebug_DEMCR_MON_REQ_Msk (1UL << CoreDebug_DEMCR_MON_REQ_Pos) /*!< CoreDebug DEMCR: MON_REQ Mask */ +#define CoreDebug_DEMCR_MON_REQ_Pos 19 /*!< CoreDebug DEMCR: MON_REQ Position */ +#define CoreDebug_DEMCR_MON_REQ_Msk (1UL << CoreDebug_DEMCR_MON_REQ_Pos) /*!< CoreDebug DEMCR: MON_REQ Mask */ -#define CoreDebug_DEMCR_MON_STEP_Pos 18 /*!< CoreDebug DEMCR: MON_STEP Position */ -#define CoreDebug_DEMCR_MON_STEP_Msk (1UL << CoreDebug_DEMCR_MON_STEP_Pos) /*!< CoreDebug DEMCR: MON_STEP Mask */ +#define CoreDebug_DEMCR_MON_STEP_Pos 18 /*!< CoreDebug DEMCR: MON_STEP Position */ +#define CoreDebug_DEMCR_MON_STEP_Msk (1UL << CoreDebug_DEMCR_MON_STEP_Pos) /*!< CoreDebug DEMCR: MON_STEP Mask */ -#define CoreDebug_DEMCR_MON_PEND_Pos 17 /*!< CoreDebug DEMCR: MON_PEND Position */ -#define CoreDebug_DEMCR_MON_PEND_Msk (1UL << CoreDebug_DEMCR_MON_PEND_Pos) /*!< CoreDebug DEMCR: MON_PEND Mask */ +#define CoreDebug_DEMCR_MON_PEND_Pos 17 /*!< CoreDebug DEMCR: MON_PEND Position */ +#define CoreDebug_DEMCR_MON_PEND_Msk (1UL << CoreDebug_DEMCR_MON_PEND_Pos) /*!< CoreDebug DEMCR: MON_PEND Mask */ -#define CoreDebug_DEMCR_MON_EN_Pos 16 /*!< CoreDebug DEMCR: MON_EN Position */ -#define CoreDebug_DEMCR_MON_EN_Msk (1UL << CoreDebug_DEMCR_MON_EN_Pos) /*!< CoreDebug DEMCR: MON_EN Mask */ +#define CoreDebug_DEMCR_MON_EN_Pos 16 /*!< CoreDebug DEMCR: MON_EN Position */ +#define CoreDebug_DEMCR_MON_EN_Msk (1UL << CoreDebug_DEMCR_MON_EN_Pos) /*!< CoreDebug DEMCR: MON_EN Mask */ -#define CoreDebug_DEMCR_VC_HARDERR_Pos 10 /*!< CoreDebug DEMCR: VC_HARDERR Position */ -#define CoreDebug_DEMCR_VC_HARDERR_Msk (1UL << CoreDebug_DEMCR_VC_HARDERR_Pos) /*!< CoreDebug DEMCR: VC_HARDERR Mask */ +#define CoreDebug_DEMCR_VC_HARDERR_Pos 10 /*!< CoreDebug DEMCR: VC_HARDERR Position */ +#define CoreDebug_DEMCR_VC_HARDERR_Msk (1UL << CoreDebug_DEMCR_VC_HARDERR_Pos) /*!< CoreDebug DEMCR: VC_HARDERR Mask */ -#define CoreDebug_DEMCR_VC_INTERR_Pos 9 /*!< CoreDebug DEMCR: VC_INTERR Position */ -#define CoreDebug_DEMCR_VC_INTERR_Msk (1UL << CoreDebug_DEMCR_VC_INTERR_Pos) /*!< CoreDebug DEMCR: VC_INTERR Mask */ +#define CoreDebug_DEMCR_VC_INTERR_Pos 9 /*!< CoreDebug DEMCR: VC_INTERR Position */ +#define CoreDebug_DEMCR_VC_INTERR_Msk (1UL << CoreDebug_DEMCR_VC_INTERR_Pos) /*!< CoreDebug DEMCR: VC_INTERR Mask */ -#define CoreDebug_DEMCR_VC_BUSERR_Pos 8 /*!< CoreDebug DEMCR: VC_BUSERR Position */ -#define CoreDebug_DEMCR_VC_BUSERR_Msk (1UL << CoreDebug_DEMCR_VC_BUSERR_Pos) /*!< CoreDebug DEMCR: VC_BUSERR Mask */ +#define CoreDebug_DEMCR_VC_BUSERR_Pos 8 /*!< CoreDebug DEMCR: VC_BUSERR Position */ +#define CoreDebug_DEMCR_VC_BUSERR_Msk (1UL << CoreDebug_DEMCR_VC_BUSERR_Pos) /*!< CoreDebug DEMCR: VC_BUSERR Mask */ -#define CoreDebug_DEMCR_VC_STATERR_Pos 7 /*!< CoreDebug DEMCR: VC_STATERR Position */ -#define CoreDebug_DEMCR_VC_STATERR_Msk (1UL << CoreDebug_DEMCR_VC_STATERR_Pos) /*!< CoreDebug DEMCR: VC_STATERR Mask */ +#define CoreDebug_DEMCR_VC_STATERR_Pos 7 /*!< CoreDebug DEMCR: VC_STATERR Position */ +#define CoreDebug_DEMCR_VC_STATERR_Msk (1UL << CoreDebug_DEMCR_VC_STATERR_Pos) /*!< CoreDebug DEMCR: VC_STATERR Mask */ -#define CoreDebug_DEMCR_VC_CHKERR_Pos 6 /*!< CoreDebug DEMCR: VC_CHKERR Position */ -#define CoreDebug_DEMCR_VC_CHKERR_Msk (1UL << CoreDebug_DEMCR_VC_CHKERR_Pos) /*!< CoreDebug DEMCR: VC_CHKERR Mask */ +#define CoreDebug_DEMCR_VC_CHKERR_Pos 6 /*!< CoreDebug DEMCR: VC_CHKERR Position */ +#define CoreDebug_DEMCR_VC_CHKERR_Msk (1UL << CoreDebug_DEMCR_VC_CHKERR_Pos) /*!< CoreDebug DEMCR: VC_CHKERR Mask */ -#define CoreDebug_DEMCR_VC_NOCPERR_Pos 5 /*!< CoreDebug DEMCR: VC_NOCPERR Position */ -#define CoreDebug_DEMCR_VC_NOCPERR_Msk (1UL << CoreDebug_DEMCR_VC_NOCPERR_Pos) /*!< CoreDebug DEMCR: VC_NOCPERR Mask */ +#define CoreDebug_DEMCR_VC_NOCPERR_Pos 5 /*!< CoreDebug DEMCR: VC_NOCPERR Position */ +#define CoreDebug_DEMCR_VC_NOCPERR_Msk (1UL << CoreDebug_DEMCR_VC_NOCPERR_Pos) /*!< CoreDebug DEMCR: VC_NOCPERR Mask */ -#define CoreDebug_DEMCR_VC_MMERR_Pos 4 /*!< CoreDebug DEMCR: VC_MMERR Position */ -#define CoreDebug_DEMCR_VC_MMERR_Msk (1UL << CoreDebug_DEMCR_VC_MMERR_Pos) /*!< CoreDebug DEMCR: VC_MMERR Mask */ +#define CoreDebug_DEMCR_VC_MMERR_Pos 4 /*!< CoreDebug DEMCR: VC_MMERR Position */ +#define CoreDebug_DEMCR_VC_MMERR_Msk (1UL << CoreDebug_DEMCR_VC_MMERR_Pos) /*!< CoreDebug DEMCR: VC_MMERR Mask */ -#define CoreDebug_DEMCR_VC_CORERESET_Pos 0 /*!< CoreDebug DEMCR: VC_CORERESET Position */ -#define CoreDebug_DEMCR_VC_CORERESET_Msk (1UL << CoreDebug_DEMCR_VC_CORERESET_Pos) /*!< CoreDebug DEMCR: VC_CORERESET Mask */ +#define CoreDebug_DEMCR_VC_CORERESET_Pos 0 /*!< CoreDebug DEMCR: VC_CORERESET Position */ +#define CoreDebug_DEMCR_VC_CORERESET_Msk (1UL << CoreDebug_DEMCR_VC_CORERESET_Pos) /*!< CoreDebug DEMCR: VC_CORERESET Mask */ /*@} end of group CMSIS_CoreDebug */ - /** \ingroup CMSIS_core_register \defgroup CMSIS_core_base Core Definitions \brief Definitions for base addresses, unions, and structures. @@ -1397,39 +1380,37 @@ typedef struct */ /* Memory mapping of Cortex-M4 Hardware */ -#define SCS_BASE (0xE000E000UL) /*!< System Control Space Base Address */ -#define ITM_BASE (0xE0000000UL) /*!< ITM Base Address */ -#define DWT_BASE (0xE0001000UL) /*!< DWT Base Address */ -#define TPI_BASE (0xE0040000UL) /*!< TPI Base Address */ -#define CoreDebug_BASE (0xE000EDF0UL) /*!< Core Debug Base Address */ -#define SysTick_BASE (SCS_BASE + 0x0010UL) /*!< SysTick Base Address */ -#define NVIC_BASE (SCS_BASE + 0x0100UL) /*!< NVIC Base Address */ -#define SCB_BASE (SCS_BASE + 0x0D00UL) /*!< System Control Block Base Address */ +#define SCS_BASE (0xE000E000UL) /*!< System Control Space Base Address */ +#define ITM_BASE (0xE0000000UL) /*!< ITM Base Address */ +#define DWT_BASE (0xE0001000UL) /*!< DWT Base Address */ +#define TPI_BASE (0xE0040000UL) /*!< TPI Base Address */ +#define CoreDebug_BASE (0xE000EDF0UL) /*!< Core Debug Base Address */ +#define SysTick_BASE (SCS_BASE + 0x0010UL) /*!< SysTick Base Address */ +#define NVIC_BASE (SCS_BASE + 0x0100UL) /*!< NVIC Base Address */ +#define SCB_BASE (SCS_BASE + 0x0D00UL) /*!< System Control Block Base Address */ -#define SCnSCB ((SCnSCB_Type *) SCS_BASE ) /*!< System control Register not in SCB */ -#define SCB ((SCB_Type *) SCB_BASE ) /*!< SCB configuration struct */ -#define SysTick ((SysTick_Type *) SysTick_BASE ) /*!< SysTick configuration struct */ -#define NVIC ((NVIC_Type *) NVIC_BASE ) /*!< NVIC configuration struct */ -#define ITM ((ITM_Type *) ITM_BASE ) /*!< ITM configuration struct */ -#define DWT ((DWT_Type *) DWT_BASE ) /*!< DWT configuration struct */ -#define TPI ((TPI_Type *) TPI_BASE ) /*!< TPI configuration struct */ -#define CoreDebug ((CoreDebug_Type *) CoreDebug_BASE) /*!< Core Debug configuration struct */ +#define SCnSCB ((SCnSCB_Type *)SCS_BASE) /*!< System control Register not in SCB */ +#define SCB ((SCB_Type *)SCB_BASE) /*!< SCB configuration struct */ +#define SysTick ((SysTick_Type *)SysTick_BASE) /*!< SysTick configuration struct */ +#define NVIC ((NVIC_Type *)NVIC_BASE) /*!< NVIC configuration struct */ +#define ITM ((ITM_Type *)ITM_BASE) /*!< ITM configuration struct */ +#define DWT ((DWT_Type *)DWT_BASE) /*!< DWT configuration struct */ +#define TPI ((TPI_Type *)TPI_BASE) /*!< TPI configuration struct */ +#define CoreDebug ((CoreDebug_Type *)CoreDebug_BASE) /*!< Core Debug configuration struct */ #if (__MPU_PRESENT == 1) - #define MPU_BASE (SCS_BASE + 0x0D90UL) /*!< Memory Protection Unit */ - #define MPU ((MPU_Type *) MPU_BASE ) /*!< Memory Protection Unit */ +#define MPU_BASE (SCS_BASE + 0x0D90UL) /*!< Memory Protection Unit */ +#define MPU ((MPU_Type *)MPU_BASE) /*!< Memory Protection Unit */ #endif #if (__FPU_PRESENT == 1) - #define FPU_BASE (SCS_BASE + 0x0F30UL) /*!< Floating Point Unit */ - #define FPU ((FPU_Type *) FPU_BASE ) /*!< Floating Point Unit */ +#define FPU_BASE (SCS_BASE + 0x0F30UL) /*!< Floating Point Unit */ +#define FPU ((FPU_Type *)FPU_BASE) /*!< Floating Point Unit */ #endif -/*@} */ - - + /*@} */ -/******************************************************************************* + /******************************************************************************* * Hardware Abstraction Layer Core Function Interface contains: - Core NVIC Functions @@ -1437,19 +1418,17 @@ typedef struct - Core Debug Functions - Core Register Access Functions ******************************************************************************/ -/** \defgroup CMSIS_Core_FunctionInterface Functions and Instructions Reference + /** \defgroup CMSIS_Core_FunctionInterface Functions and Instructions Reference */ - - -/* ########################## NVIC functions #################################### */ -/** \ingroup CMSIS_Core_FunctionInterface + /* ########################## NVIC functions #################################### */ + /** \ingroup CMSIS_Core_FunctionInterface \defgroup CMSIS_Core_NVICFunctions NVIC Functions \brief Functions that manage interrupts and exceptions via the NVIC. @{ */ -/** \brief Set Priority Grouping + /** \brief Set Priority Grouping The function sets the priority grouping field using the required unlock sequence. The parameter PriorityGroup is assigned to the field SCB->AIRCR [10:8] PRIGROUP field. @@ -1459,58 +1438,54 @@ typedef struct \param [in] PriorityGroup Priority grouping field. */ -__STATIC_INLINE void NVIC_SetPriorityGrouping(uint32_t PriorityGroup) -{ - uint32_t reg_value; - uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07); /* only values 0..7 are used */ - - reg_value = SCB->AIRCR; /* read old register configuration */ - reg_value &= ~(SCB_AIRCR_VECTKEY_Msk | SCB_AIRCR_PRIGROUP_Msk); /* clear bits to change */ - reg_value = (reg_value | - ((uint32_t)0x5FA << SCB_AIRCR_VECTKEY_Pos) | - (PriorityGroupTmp << 8)); /* Insert write key and priorty group */ - SCB->AIRCR = reg_value; -} + __STATIC_INLINE void NVIC_SetPriorityGrouping(uint32_t PriorityGroup) + { + uint32_t reg_value; + uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07); /* only values 0..7 are used */ + reg_value = SCB->AIRCR; /* read old register configuration */ + reg_value &= ~(SCB_AIRCR_VECTKEY_Msk | SCB_AIRCR_PRIGROUP_Msk); /* clear bits to change */ + reg_value = (reg_value | + ((uint32_t)0x5FA << SCB_AIRCR_VECTKEY_Pos) | + (PriorityGroupTmp << 8)); /* Insert write key and priorty group */ + SCB->AIRCR = reg_value; + } -/** \brief Get Priority Grouping + /** \brief Get Priority Grouping The function reads the priority grouping field from the NVIC Interrupt Controller. \return Priority grouping field (SCB->AIRCR [10:8] PRIGROUP field). */ -__STATIC_INLINE uint32_t NVIC_GetPriorityGrouping(void) -{ - return ((SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) >> SCB_AIRCR_PRIGROUP_Pos); /* read priority grouping field */ -} + __STATIC_INLINE uint32_t NVIC_GetPriorityGrouping(void) + { + return ((SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) >> SCB_AIRCR_PRIGROUP_Pos); /* read priority grouping field */ + } - -/** \brief Enable External Interrupt + /** \brief Enable External Interrupt The function enables a device-specific interrupt in the NVIC interrupt controller. \param [in] IRQn External interrupt number. Value cannot be negative. */ -__STATIC_INLINE void NVIC_EnableIRQ(IRQn_Type IRQn) -{ -/* NVIC->ISER[((uint32_t)(IRQn) >> 5)] = (1 << ((uint32_t)(IRQn) & 0x1F)); enable interrupt */ - NVIC->ISER[(uint32_t)((int32_t)IRQn) >> 5] = (uint32_t)(1 << ((uint32_t)((int32_t)IRQn) & (uint32_t)0x1F)); /* enable interrupt */ -} - + __STATIC_INLINE void NVIC_EnableIRQ(IRQn_Type IRQn) + { + /* NVIC->ISER[((uint32_t)(IRQn) >> 5)] = (1 << ((uint32_t)(IRQn) & 0x1F)); enable interrupt */ + NVIC->ISER[(uint32_t)((int32_t)IRQn) >> 5] = (uint32_t)(1 << ((uint32_t)((int32_t)IRQn) & (uint32_t)0x1F)); /* enable interrupt */ + } -/** \brief Disable External Interrupt + /** \brief Disable External Interrupt The function disables a device-specific interrupt in the NVIC interrupt controller. \param [in] IRQn External interrupt number. Value cannot be negative. */ -__STATIC_INLINE void NVIC_DisableIRQ(IRQn_Type IRQn) -{ - NVIC->ICER[((uint32_t)(IRQn) >> 5)] = (1 << ((uint32_t)(IRQn) & 0x1F)); /* disable interrupt */ -} + __STATIC_INLINE void NVIC_DisableIRQ(IRQn_Type IRQn) + { + NVIC->ICER[((uint32_t)(IRQn) >> 5)] = (1 << ((uint32_t)(IRQn)&0x1F)); /* disable interrupt */ + } - -/** \brief Get Pending Interrupt + /** \brief Get Pending Interrupt The function reads the pending register in the NVIC and returns the pending bit for the specified interrupt. @@ -1520,37 +1495,34 @@ __STATIC_INLINE void NVIC_DisableIRQ(IRQn_Type IRQn) \return 0 Interrupt status is not pending. \return 1 Interrupt status is pending. */ -__STATIC_INLINE uint32_t NVIC_GetPendingIRQ(IRQn_Type IRQn) -{ - return((uint32_t) ((NVIC->ISPR[(uint32_t)(IRQn) >> 5] & (1 << ((uint32_t)(IRQn) & 0x1F)))?1:0)); /* Return 1 if pending else 0 */ -} - + __STATIC_INLINE uint32_t NVIC_GetPendingIRQ(IRQn_Type IRQn) + { + return ((uint32_t)((NVIC->ISPR[(uint32_t)(IRQn) >> 5] & (1 << ((uint32_t)(IRQn)&0x1F))) ? 1 : 0)); /* Return 1 if pending else 0 */ + } -/** \brief Set Pending Interrupt + /** \brief Set Pending Interrupt The function sets the pending bit of an external interrupt. \param [in] IRQn Interrupt number. Value cannot be negative. */ -__STATIC_INLINE void NVIC_SetPendingIRQ(IRQn_Type IRQn) -{ - NVIC->ISPR[((uint32_t)(IRQn) >> 5)] = (1 << ((uint32_t)(IRQn) & 0x1F)); /* set interrupt pending */ -} + __STATIC_INLINE void NVIC_SetPendingIRQ(IRQn_Type IRQn) + { + NVIC->ISPR[((uint32_t)(IRQn) >> 5)] = (1 << ((uint32_t)(IRQn)&0x1F)); /* set interrupt pending */ + } - -/** \brief Clear Pending Interrupt + /** \brief Clear Pending Interrupt The function clears the pending bit of an external interrupt. \param [in] IRQn External interrupt number. Value cannot be negative. */ -__STATIC_INLINE void NVIC_ClearPendingIRQ(IRQn_Type IRQn) -{ - NVIC->ICPR[((uint32_t)(IRQn) >> 5)] = (1 << ((uint32_t)(IRQn) & 0x1F)); /* Clear pending interrupt */ -} - + __STATIC_INLINE void NVIC_ClearPendingIRQ(IRQn_Type IRQn) + { + NVIC->ICPR[((uint32_t)(IRQn) >> 5)] = (1 << ((uint32_t)(IRQn)&0x1F)); /* Clear pending interrupt */ + } -/** \brief Get Active Interrupt + /** \brief Get Active Interrupt The function reads the active register in NVIC and returns the active bit. @@ -1559,13 +1531,12 @@ __STATIC_INLINE void NVIC_ClearPendingIRQ(IRQn_Type IRQn) \return 0 Interrupt status is not active. \return 1 Interrupt status is active. */ -__STATIC_INLINE uint32_t NVIC_GetActive(IRQn_Type IRQn) -{ - return((uint32_t)((NVIC->IABR[(uint32_t)(IRQn) >> 5] & (1 << ((uint32_t)(IRQn) & 0x1F)))?1:0)); /* Return 1 if active else 0 */ -} - + __STATIC_INLINE uint32_t NVIC_GetActive(IRQn_Type IRQn) + { + return ((uint32_t)((NVIC->IABR[(uint32_t)(IRQn) >> 5] & (1 << ((uint32_t)(IRQn)&0x1F))) ? 1 : 0)); /* Return 1 if active else 0 */ + } -/** \brief Set Interrupt Priority + /** \brief Set Interrupt Priority The function sets the priority of an interrupt. @@ -1574,16 +1545,19 @@ __STATIC_INLINE uint32_t NVIC_GetActive(IRQn_Type IRQn) \param [in] IRQn Interrupt number. \param [in] priority Priority to set. */ -__STATIC_INLINE void NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority) -{ - if(IRQn < 0) { - SCB->SHP[((uint32_t)(IRQn) & 0xF)-4] = ((priority << (8 - __NVIC_PRIO_BITS)) & 0xff); } /* set Priority for Cortex-M System Interrupts */ - else { - NVIC->IP[(uint32_t)(IRQn)] = ((priority << (8 - __NVIC_PRIO_BITS)) & 0xff); } /* set Priority for device specific Interrupts */ -} + __STATIC_INLINE void NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority) + { + if (IRQn < 0) + { + SCB->SHP[((uint32_t)(IRQn)&0xF) - 4] = ((priority << (8 - __NVIC_PRIO_BITS)) & 0xff); + } /* set Priority for Cortex-M System Interrupts */ + else + { + NVIC->IP[(uint32_t)(IRQn)] = ((priority << (8 - __NVIC_PRIO_BITS)) & 0xff); + } /* set Priority for device specific Interrupts */ + } - -/** \brief Get Interrupt Priority + /** \brief Get Interrupt Priority The function reads the priority of an interrupt. The interrupt number can be positive to specify an external (device specific) @@ -1594,17 +1568,20 @@ __STATIC_INLINE void NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority) \return Interrupt Priority. Value is aligned automatically to the implemented priority bits of the microcontroller. */ -__STATIC_INLINE uint32_t NVIC_GetPriority(IRQn_Type IRQn) -{ - - if(IRQn < 0) { - return((uint32_t)(SCB->SHP[((uint32_t)(IRQn) & 0xF)-4] >> (8 - __NVIC_PRIO_BITS))); } /* get priority for Cortex-M system interrupts */ - else { - return((uint32_t)(NVIC->IP[(uint32_t)(IRQn)] >> (8 - __NVIC_PRIO_BITS))); } /* get priority for device specific interrupts */ -} + __STATIC_INLINE uint32_t NVIC_GetPriority(IRQn_Type IRQn) + { + if (IRQn < 0) + { + return ((uint32_t)(SCB->SHP[((uint32_t)(IRQn)&0xF) - 4] >> (8 - __NVIC_PRIO_BITS))); + } /* get priority for Cortex-M system interrupts */ + else + { + return ((uint32_t)(NVIC->IP[(uint32_t)(IRQn)] >> (8 - __NVIC_PRIO_BITS))); + } /* get priority for device specific interrupts */ + } -/** \brief Encode Priority + /** \brief Encode Priority The function encodes the priority for an interrupt with the given priority group, preemptive priority value, and subpriority value. @@ -1616,23 +1593,21 @@ __STATIC_INLINE uint32_t NVIC_GetPriority(IRQn_Type IRQn) \param [in] SubPriority Subpriority value (starting from 0). \return Encoded priority. Value can be used in the function \ref NVIC_SetPriority(). */ -__STATIC_INLINE uint32_t NVIC_EncodePriority (uint32_t PriorityGroup, uint32_t PreemptPriority, uint32_t SubPriority) -{ - uint32_t PriorityGroupTmp = (PriorityGroup & 0x07); /* only values 0..7 are used */ - uint32_t PreemptPriorityBits; - uint32_t SubPriorityBits; - - PreemptPriorityBits = ((7 - PriorityGroupTmp) > __NVIC_PRIO_BITS) ? __NVIC_PRIO_BITS : 7 - PriorityGroupTmp; - SubPriorityBits = ((PriorityGroupTmp + __NVIC_PRIO_BITS) < 7) ? 0 : PriorityGroupTmp - 7 + __NVIC_PRIO_BITS; + __STATIC_INLINE uint32_t NVIC_EncodePriority(uint32_t PriorityGroup, uint32_t PreemptPriority, uint32_t SubPriority) + { + uint32_t PriorityGroupTmp = (PriorityGroup & 0x07); /* only values 0..7 are used */ + uint32_t PreemptPriorityBits; + uint32_t SubPriorityBits; - return ( - ((PreemptPriority & ((1 << (PreemptPriorityBits)) - 1)) << SubPriorityBits) | - ((SubPriority & ((1 << (SubPriorityBits )) - 1))) - ); -} + PreemptPriorityBits = ((7 - PriorityGroupTmp) > __NVIC_PRIO_BITS) ? __NVIC_PRIO_BITS : 7 - PriorityGroupTmp; + SubPriorityBits = ((PriorityGroupTmp + __NVIC_PRIO_BITS) < 7) ? 0 : PriorityGroupTmp - 7 + __NVIC_PRIO_BITS; + return ( + ((PreemptPriority & ((1 << (PreemptPriorityBits)) - 1)) << SubPriorityBits) | + ((SubPriority & ((1 << (SubPriorityBits)) - 1)))); + } -/** \brief Decode Priority + /** \brief Decode Priority The function decodes an interrupt priority value with a given priority group to preemptive priority value and subpriority value. @@ -1644,41 +1619,39 @@ __STATIC_INLINE uint32_t NVIC_EncodePriority (uint32_t PriorityGroup, uint32_t P \param [out] pPreemptPriority Preemptive priority value (starting from 0). \param [out] pSubPriority Subpriority value (starting from 0). */ -__STATIC_INLINE void NVIC_DecodePriority (uint32_t Priority, uint32_t PriorityGroup, uint32_t* pPreemptPriority, uint32_t* pSubPriority) -{ - uint32_t PriorityGroupTmp = (PriorityGroup & 0x07); /* only values 0..7 are used */ - uint32_t PreemptPriorityBits; - uint32_t SubPriorityBits; + __STATIC_INLINE void NVIC_DecodePriority(uint32_t Priority, uint32_t PriorityGroup, uint32_t *pPreemptPriority, uint32_t *pSubPriority) + { + uint32_t PriorityGroupTmp = (PriorityGroup & 0x07); /* only values 0..7 are used */ + uint32_t PreemptPriorityBits; + uint32_t SubPriorityBits; - PreemptPriorityBits = ((7 - PriorityGroupTmp) > __NVIC_PRIO_BITS) ? __NVIC_PRIO_BITS : 7 - PriorityGroupTmp; - SubPriorityBits = ((PriorityGroupTmp + __NVIC_PRIO_BITS) < 7) ? 0 : PriorityGroupTmp - 7 + __NVIC_PRIO_BITS; - - *pPreemptPriority = (Priority >> SubPriorityBits) & ((1 << (PreemptPriorityBits)) - 1); - *pSubPriority = (Priority ) & ((1 << (SubPriorityBits )) - 1); -} + PreemptPriorityBits = ((7 - PriorityGroupTmp) > __NVIC_PRIO_BITS) ? __NVIC_PRIO_BITS : 7 - PriorityGroupTmp; + SubPriorityBits = ((PriorityGroupTmp + __NVIC_PRIO_BITS) < 7) ? 0 : PriorityGroupTmp - 7 + __NVIC_PRIO_BITS; + *pPreemptPriority = (Priority >> SubPriorityBits) & ((1 << (PreemptPriorityBits)) - 1); + *pSubPriority = (Priority) & ((1 << (SubPriorityBits)) - 1); + } -/** \brief System Reset + /** \brief System Reset The function initiates a system reset request to reset the MCU. */ -__STATIC_INLINE void NVIC_SystemReset(void) -{ - __DSB(); /* Ensure all outstanding memory accesses included + __STATIC_INLINE void NVIC_SystemReset(void) + { + __DSB(); /* Ensure all outstanding memory accesses included buffered write are completed before reset */ - SCB->AIRCR = ((0x5FA << SCB_AIRCR_VECTKEY_Pos) | - (SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) | - SCB_AIRCR_SYSRESETREQ_Msk); /* Keep priority group unchanged */ - __DSB(); /* Ensure completion of memory access */ - while(1); /* wait until reset */ -} + SCB->AIRCR = ((0x5FA << SCB_AIRCR_VECTKEY_Pos) | + (SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) | + SCB_AIRCR_SYSRESETREQ_Msk); /* Keep priority group unchanged */ + __DSB(); /* Ensure completion of memory access */ + while (1) + ; /* wait until reset */ + } -/*@} end of CMSIS_Core_NVICFunctions */ + /*@} end of CMSIS_Core_NVICFunctions */ - - -/* ################################## SysTick function ############################################ */ -/** \ingroup CMSIS_Core_FunctionInterface + /* ################################## SysTick function ############################################ */ + /** \ingroup CMSIS_Core_FunctionInterface \defgroup CMSIS_Core_SysTickFunctions SysTick Functions \brief Functions that configure the System. @{ @@ -1686,7 +1659,7 @@ __STATIC_INLINE void NVIC_SystemReset(void) #if (__Vendor_SysTickConfig == 0) -/** \brief System Tick Configuration + /** \brief System Tick Configuration The function initializes the System Timer and its interrupt, and starts the System Tick Timer. Counter is in free running mode to generate periodic interrupts. @@ -1701,37 +1674,35 @@ __STATIC_INLINE void NVIC_SystemReset(void) must contain a vendor-specific implementation of this function. */ -__STATIC_INLINE uint32_t SysTick_Config(uint32_t ticks) -{ - if ((ticks - 1) > SysTick_LOAD_RELOAD_Msk) return (1); /* Reload value impossible */ + __STATIC_INLINE uint32_t SysTick_Config(uint32_t ticks) + { + if ((ticks - 1) > SysTick_LOAD_RELOAD_Msk) + return (1); /* Reload value impossible */ - SysTick->LOAD = ticks - 1; /* set reload register */ - NVIC_SetPriority (SysTick_IRQn, (1<<__NVIC_PRIO_BITS) - 1); /* set Priority for Systick Interrupt */ - SysTick->VAL = 0; /* Load the SysTick Counter Value */ - SysTick->CTRL = SysTick_CTRL_CLKSOURCE_Msk | - SysTick_CTRL_TICKINT_Msk | - SysTick_CTRL_ENABLE_Msk; /* Enable SysTick IRQ and SysTick Timer */ - return (0); /* Function successful */ -} + SysTick->LOAD = ticks - 1; /* set reload register */ + NVIC_SetPriority(SysTick_IRQn, (1 << __NVIC_PRIO_BITS) - 1); /* set Priority for Systick Interrupt */ + SysTick->VAL = 0; /* Load the SysTick Counter Value */ + SysTick->CTRL = SysTick_CTRL_CLKSOURCE_Msk | + SysTick_CTRL_TICKINT_Msk | + SysTick_CTRL_ENABLE_Msk; /* Enable SysTick IRQ and SysTick Timer */ + return (0); /* Function successful */ + } #endif -/*@} end of CMSIS_Core_SysTickFunctions */ + /*@} end of CMSIS_Core_SysTickFunctions */ - - -/* ##################################### Debug In/Output function ########################################### */ -/** \ingroup CMSIS_Core_FunctionInterface + /* ##################################### Debug In/Output function ########################################### */ + /** \ingroup CMSIS_Core_FunctionInterface \defgroup CMSIS_core_DebugFunctions ITM Functions \brief Functions that access the ITM debug interface. @{ */ -extern volatile int32_t ITM_RxBuffer; /*!< External variable to receive characters. */ -#define ITM_RXBUFFER_EMPTY 0x5AA55AA5 /*!< Value identifying \ref ITM_RxBuffer is ready for next character. */ + extern volatile int32_t ITM_RxBuffer; /*!< External variable to receive characters. */ +#define ITM_RXBUFFER_EMPTY 0x5AA55AA5 /*!< Value identifying \ref ITM_RxBuffer is ready for next character. */ - -/** \brief ITM Send Character + /** \brief ITM Send Character The function transmits a character via the ITM channel 0, and \li Just returns when no debugger is connected that has booked the output. @@ -1741,57 +1712,59 @@ extern volatile int32_t ITM_RxBuffer; /*!< External variable \returns Character to transmit. */ -__STATIC_INLINE uint32_t ITM_SendChar (uint32_t ch) -{ - if ((ITM->TCR & ITM_TCR_ITMENA_Msk) && /* ITM enabled */ - (ITM->TER & (1UL << 0) ) ) /* ITM Port #0 enabled */ - { - while (ITM->PORT[0].u32 == 0); - ITM->PORT[0].u8 = (uint8_t) ch; - } - return (ch); -} - + __STATIC_INLINE uint32_t ITM_SendChar(uint32_t ch) + { + if ((ITM->TCR & ITM_TCR_ITMENA_Msk) && /* ITM enabled */ + (ITM->TER & (1UL << 0))) /* ITM Port #0 enabled */ + { + while (ITM->PORT[0].u32 == 0) + ; + ITM->PORT[0].u8 = (uint8_t)ch; + } + return (ch); + } -/** \brief ITM Receive Character + /** \brief ITM Receive Character The function inputs a character via the external variable \ref ITM_RxBuffer. \return Received character. \return -1 No character pending. */ -__STATIC_INLINE int32_t ITM_ReceiveChar (void) { - int32_t ch = -1; /* no character available */ + __STATIC_INLINE int32_t ITM_ReceiveChar(void) + { + int32_t ch = -1; /* no character available */ - if (ITM_RxBuffer != ITM_RXBUFFER_EMPTY) { - ch = ITM_RxBuffer; - ITM_RxBuffer = ITM_RXBUFFER_EMPTY; /* ready for next character */ - } - - return (ch); -} + if (ITM_RxBuffer != ITM_RXBUFFER_EMPTY) + { + ch = ITM_RxBuffer; + ITM_RxBuffer = ITM_RXBUFFER_EMPTY; /* ready for next character */ + } + return (ch); + } -/** \brief ITM Check Character + /** \brief ITM Check Character The function checks whether a character is pending for reading in the variable \ref ITM_RxBuffer. \return 0 No character available. \return 1 Character available. */ -__STATIC_INLINE int32_t ITM_CheckChar (void) { - - if (ITM_RxBuffer == ITM_RXBUFFER_EMPTY) { - return (0); /* no character available */ - } else { - return (1); /* character available */ - } -} - -/*@} end of CMSIS_core_DebugFunctions */ - + __STATIC_INLINE int32_t ITM_CheckChar(void) + { + if (ITM_RxBuffer == ITM_RXBUFFER_EMPTY) + { + return (0); /* no character available */ + } + else + { + return (1); /* character available */ + } + } + /*@} end of CMSIS_core_DebugFunctions */ #ifdef __cplusplus } diff --git a/bsp/swm320-lq100/Libraries/CMSIS/CoreSupport/core_cm7.h b/bsp/swm320-lq100/Libraries/CMSIS/CoreSupport/core_cm7.h index 242540f8b1..265d3bc735 100644 --- a/bsp/swm320-lq100/Libraries/CMSIS/CoreSupport/core_cm7.h +++ b/bsp/swm320-lq100/Libraries/CMSIS/CoreSupport/core_cm7.h @@ -1,4 +1,4 @@ -/**************************************************************************//** +/**************************************************************************/ /** * @file core_cm7.h * @brief CMSIS Cortex-M7 Core Peripheral Access Layer Header File * @version V4.00 @@ -34,16 +34,16 @@ POSSIBILITY OF SUCH DAMAGE. ---------------------------------------------------------------------------*/ - -#if defined ( __ICCARM__ ) - #pragma system_include /* treat file as system include file for MISRA check */ +#if defined(__ICCARM__) +#pragma system_include /* treat file as system include file for MISRA check */ #endif #ifndef __CORE_CM7_H_GENERIC #define __CORE_CM7_H_GENERIC #ifdef __cplusplus - extern "C" { +extern "C" +{ #endif /** \page CMSIS_MISRA_Exceptions MISRA-C:2004 Compliance Exceptions @@ -59,7 +59,6 @@ Function-like macros are used to allow more efficient code. */ - /******************************************************************************* * CMSIS definitions ******************************************************************************/ @@ -68,126 +67,125 @@ */ /* CMSIS CM7 definitions */ -#define __CM7_CMSIS_VERSION_MAIN (0x04) /*!< [31:16] CMSIS HAL main version */ -#define __CM7_CMSIS_VERSION_SUB (0x00) /*!< [15:0] CMSIS HAL sub version */ -#define __CM7_CMSIS_VERSION ((__CM7_CMSIS_VERSION_MAIN << 16) | \ - __CM7_CMSIS_VERSION_SUB ) /*!< CMSIS HAL version number */ +#define __CM7_CMSIS_VERSION_MAIN (0x04) /*!< [31:16] CMSIS HAL main version */ +#define __CM7_CMSIS_VERSION_SUB (0x00) /*!< [15:0] CMSIS HAL sub version */ +#define __CM7_CMSIS_VERSION ((__CM7_CMSIS_VERSION_MAIN << 16) | \ + __CM7_CMSIS_VERSION_SUB) /*!< CMSIS HAL version number */ -#define __CORTEX_M (0x07) /*!< Cortex-M Core */ +#define __CORTEX_M (0x07) /*!< Cortex-M Core */ +#if defined(__CC_ARM) +#define __ASM __asm /*!< asm keyword for ARM Compiler */ +#define __INLINE __inline /*!< inline keyword for ARM Compiler */ +#define __STATIC_INLINE static __inline -#if defined ( __CC_ARM ) - #define __ASM __asm /*!< asm keyword for ARM Compiler */ - #define __INLINE __inline /*!< inline keyword for ARM Compiler */ - #define __STATIC_INLINE static __inline +#elif defined(__GNUC__) +#define __ASM __asm /*!< asm keyword for GNU Compiler */ +#define __INLINE inline /*!< inline keyword for GNU Compiler */ +#define __STATIC_INLINE static inline -#elif defined ( __GNUC__ ) - #define __ASM __asm /*!< asm keyword for GNU Compiler */ - #define __INLINE inline /*!< inline keyword for GNU Compiler */ - #define __STATIC_INLINE static inline +#elif defined(__ICCARM__) +#define __ASM __asm /*!< asm keyword for IAR Compiler */ +#define __INLINE inline /*!< inline keyword for IAR Compiler. Only available in High optimization mode! */ +#define __STATIC_INLINE static inline -#elif defined ( __ICCARM__ ) - #define __ASM __asm /*!< asm keyword for IAR Compiler */ - #define __INLINE inline /*!< inline keyword for IAR Compiler. Only available in High optimization mode! */ - #define __STATIC_INLINE static inline +#elif defined(__TMS470__) +#define __ASM __asm /*!< asm keyword for TI CCS Compiler */ +#define __STATIC_INLINE static inline -#elif defined ( __TMS470__ ) - #define __ASM __asm /*!< asm keyword for TI CCS Compiler */ - #define __STATIC_INLINE static inline +#elif defined(__TASKING__) +#define __ASM __asm /*!< asm keyword for TASKING Compiler */ +#define __INLINE inline /*!< inline keyword for TASKING Compiler */ +#define __STATIC_INLINE static inline -#elif defined ( __TASKING__ ) - #define __ASM __asm /*!< asm keyword for TASKING Compiler */ - #define __INLINE inline /*!< inline keyword for TASKING Compiler */ - #define __STATIC_INLINE static inline - -#elif defined ( __CSMC__ ) - #define __packed - #define __ASM _asm /*!< asm keyword for COSMIC Compiler */ - #define __INLINE inline /*use -pc99 on compile line !< inline keyword for COSMIC Compiler */ - #define __STATIC_INLINE static inline +#elif defined(__CSMC__) +#define __packed +#define __ASM _asm /*!< asm keyword for COSMIC Compiler */ +#define __INLINE inline /*use -pc99 on compile line !< inline keyword for COSMIC Compiler */ +#define __STATIC_INLINE static inline #endif /** __FPU_USED indicates whether an FPU is used or not. For this, __FPU_PRESENT has to be checked prior to making use of FPU specific registers and functions. */ -#if defined ( __CC_ARM ) - #if defined __TARGET_FPU_VFP - #if (__FPU_PRESENT == 1) - #define __FPU_USED 1 - #else - #warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" - #define __FPU_USED 0 - #endif - #else - #define __FPU_USED 0 - #endif +#if defined(__CC_ARM) +#if defined __TARGET_FPU_VFP +#if (__FPU_PRESENT == 1) +#define __FPU_USED 1 +#else +#warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" +#define __FPU_USED 0 +#endif +#else +#define __FPU_USED 0 +#endif -#elif defined ( __GNUC__ ) - #if defined (__VFP_FP__) && !defined(__SOFTFP__) - #if (__FPU_PRESENT == 1) - #define __FPU_USED 1 - #else - #warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" - #define __FPU_USED 0 - #endif - #else - #define __FPU_USED 0 - #endif +#elif defined(__GNUC__) +#if defined(__VFP_FP__) && !defined(__SOFTFP__) +#if (__FPU_PRESENT == 1) +#define __FPU_USED 1 +#else +#warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" +#define __FPU_USED 0 +#endif +#else +#define __FPU_USED 0 +#endif -#elif defined ( __ICCARM__ ) - #if defined __ARMVFP__ - #if (__FPU_PRESENT == 1) - #define __FPU_USED 1 - #else - #warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" - #define __FPU_USED 0 - #endif - #else - #define __FPU_USED 0 - #endif +#elif defined(__ICCARM__) +#if defined __ARMVFP__ +#if (__FPU_PRESENT == 1) +#define __FPU_USED 1 +#else +#warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" +#define __FPU_USED 0 +#endif +#else +#define __FPU_USED 0 +#endif -#elif defined ( __TMS470__ ) - #if defined __TI_VFP_SUPPORT__ - #if (__FPU_PRESENT == 1) - #define __FPU_USED 1 - #else - #warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" - #define __FPU_USED 0 - #endif - #else - #define __FPU_USED 0 - #endif +#elif defined(__TMS470__) +#if defined __TI_VFP_SUPPORT__ +#if (__FPU_PRESENT == 1) +#define __FPU_USED 1 +#else +#warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" +#define __FPU_USED 0 +#endif +#else +#define __FPU_USED 0 +#endif -#elif defined ( __TASKING__ ) - #if defined __FPU_VFP__ - #if (__FPU_PRESENT == 1) - #define __FPU_USED 1 - #else - #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" - #define __FPU_USED 0 - #endif - #else - #define __FPU_USED 0 - #endif +#elif defined(__TASKING__) +#if defined __FPU_VFP__ +#if (__FPU_PRESENT == 1) +#define __FPU_USED 1 +#else +#error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" +#define __FPU_USED 0 +#endif +#else +#define __FPU_USED 0 +#endif -#elif defined ( __CSMC__ ) /* Cosmic */ - #if ( __CSMC__ & 0x400) // FPU present for parser - #if (__FPU_PRESENT == 1) - #define __FPU_USED 1 - #else - #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" - #define __FPU_USED 0 - #endif - #else - #define __FPU_USED 0 - #endif +#elif defined(__CSMC__) /* Cosmic */ +#if (__CSMC__ & 0x400) // FPU present for parser +#if (__FPU_PRESENT == 1) +#define __FPU_USED 1 +#else +#error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" +#define __FPU_USED 0 +#endif +#else +#define __FPU_USED 0 +#endif #endif -#include <stdint.h> /* standard types definitions */ -#include <core_cmInstr.h> /* Core Instruction Access */ -#include <core_cmFunc.h> /* Core Function Access */ -#include <core_cmSimd.h> /* Compiler specific SIMD Intrinsics */ +#include <stdint.h> /* standard types definitions */ +#include <core_cmInstr.h> /* Core Instruction Access */ +#include <core_cmFunc.h> /* Core Function Access */ +#include <core_cmSimd.h> /* Compiler specific SIMD Intrinsics */ #ifdef __cplusplus } @@ -201,50 +199,51 @@ #define __CORE_CM7_H_DEPENDANT #ifdef __cplusplus - extern "C" { +extern "C" +{ #endif /* check device defines and use defaults */ #if defined __CHECK_DEVICE_DEFINES - #ifndef __CM7_REV - #define __CM7_REV 0x0000 - #warning "__CM7_REV not defined in device header file; using default!" - #endif +#ifndef __CM7_REV +#define __CM7_REV 0x0000 +#warning "__CM7_REV not defined in device header file; using default!" +#endif - #ifndef __FPU_PRESENT - #define __FPU_PRESENT 0 - #warning "__FPU_PRESENT not defined in device header file; using default!" - #endif +#ifndef __FPU_PRESENT +#define __FPU_PRESENT 0 +#warning "__FPU_PRESENT not defined in device header file; using default!" +#endif - #ifndef __MPU_PRESENT - #define __MPU_PRESENT 0 - #warning "__MPU_PRESENT not defined in device header file; using default!" - #endif +#ifndef __MPU_PRESENT +#define __MPU_PRESENT 0 +#warning "__MPU_PRESENT not defined in device header file; using default!" +#endif - #ifndef __ICACHE_PRESENT - #define __ICACHE_PRESENT 0 - #warning "__ICACHE_PRESENT not defined in device header file; using default!" - #endif +#ifndef __ICACHE_PRESENT +#define __ICACHE_PRESENT 0 +#warning "__ICACHE_PRESENT not defined in device header file; using default!" +#endif - #ifndef __DCACHE_PRESENT - #define __DCACHE_PRESENT 0 - #warning "__DCACHE_PRESENT not defined in device header file; using default!" - #endif +#ifndef __DCACHE_PRESENT +#define __DCACHE_PRESENT 0 +#warning "__DCACHE_PRESENT not defined in device header file; using default!" +#endif - #ifndef __DTCM_PRESENT - #define __DTCM_PRESENT 0 - #warning "__DTCM_PRESENT not defined in device header file; using default!" - #endif +#ifndef __DTCM_PRESENT +#define __DTCM_PRESENT 0 +#warning "__DTCM_PRESENT not defined in device header file; using default!" +#endif - #ifndef __NVIC_PRIO_BITS - #define __NVIC_PRIO_BITS 3 - #warning "__NVIC_PRIO_BITS not defined in device header file; using default!" - #endif +#ifndef __NVIC_PRIO_BITS +#define __NVIC_PRIO_BITS 3 +#warning "__NVIC_PRIO_BITS not defined in device header file; using default!" +#endif - #ifndef __Vendor_SysTickConfig - #define __Vendor_SysTickConfig 0 - #warning "__Vendor_SysTickConfig not defined in device header file; using default!" - #endif +#ifndef __Vendor_SysTickConfig +#define __Vendor_SysTickConfig 0 +#warning "__Vendor_SysTickConfig not defined in device header file; using default!" +#endif #endif /* IO definitions (access restrictions to peripheral registers) */ @@ -256,18 +255,16 @@ \li for automatic generation of peripheral register debug information. */ #ifdef __cplusplus - #define __I volatile /*!< Defines 'read only' permissions */ +#define __I volatile /*!< Defines 'read only' permissions */ #else - #define __I volatile const /*!< Defines 'read only' permissions */ +#define __I volatile const /*!< Defines 'read only' permissions */ #endif -#define __O volatile /*!< Defines 'write only' permissions */ -#define __IO volatile /*!< Defines 'read / write' permissions */ - -/*@} end of group Cortex_M7 */ +#define __O volatile /*!< Defines 'write only' permissions */ +#define __IO volatile /*!< Defines 'read / write' permissions */ + /*@} end of group Cortex_M7 */ - -/******************************************************************************* + /******************************************************************************* * Register Abstraction Core Register contain: - Core Register @@ -278,1305 +275,1291 @@ - Core MPU Register - Core FPU Register ******************************************************************************/ -/** \defgroup CMSIS_core_register Defines and Type Definitions + /** \defgroup CMSIS_core_register Defines and Type Definitions \brief Type definitions and defines for Cortex-M processor based devices. */ -/** \ingroup CMSIS_core_register + /** \ingroup CMSIS_core_register \defgroup CMSIS_CORE Status and Control Registers \brief Core Register type definitions. @{ */ -/** \brief Union type to access the Application Program Status Register (APSR). + /** \brief Union type to access the Application Program Status Register (APSR). */ -typedef union -{ - struct - { + typedef union + { + struct + { #if (__CORTEX_M != 0x07) - uint32_t _reserved0:27; /*!< bit: 0..26 Reserved */ + uint32_t _reserved0 : 27; /*!< bit: 0..26 Reserved */ #else - uint32_t _reserved0:16; /*!< bit: 0..15 Reserved */ - uint32_t GE:4; /*!< bit: 16..19 Greater than or Equal flags */ - uint32_t _reserved1:7; /*!< bit: 20..26 Reserved */ + uint32_t _reserved0 : 16; /*!< bit: 0..15 Reserved */ + uint32_t GE : 4; /*!< bit: 16..19 Greater than or Equal flags */ + uint32_t _reserved1 : 7; /*!< bit: 20..26 Reserved */ #endif - uint32_t Q:1; /*!< bit: 27 Saturation condition flag */ - uint32_t V:1; /*!< bit: 28 Overflow condition code flag */ - uint32_t C:1; /*!< bit: 29 Carry condition code flag */ - uint32_t Z:1; /*!< bit: 30 Zero condition code flag */ - uint32_t N:1; /*!< bit: 31 Negative condition code flag */ - } b; /*!< Structure used for bit access */ - uint32_t w; /*!< Type used for word access */ -} APSR_Type; - + uint32_t Q : 1; /*!< bit: 27 Saturation condition flag */ + uint32_t V : 1; /*!< bit: 28 Overflow condition code flag */ + uint32_t C : 1; /*!< bit: 29 Carry condition code flag */ + uint32_t Z : 1; /*!< bit: 30 Zero condition code flag */ + uint32_t N : 1; /*!< bit: 31 Negative condition code flag */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ + } APSR_Type; -/** \brief Union type to access the Interrupt Program Status Register (IPSR). + /** \brief Union type to access the Interrupt Program Status Register (IPSR). */ -typedef union -{ - struct - { - uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */ - uint32_t _reserved0:23; /*!< bit: 9..31 Reserved */ - } b; /*!< Structure used for bit access */ - uint32_t w; /*!< Type used for word access */ -} IPSR_Type; + typedef union + { + struct + { + uint32_t ISR : 9; /*!< bit: 0.. 8 Exception number */ + uint32_t _reserved0 : 23; /*!< bit: 9..31 Reserved */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ + } IPSR_Type; - -/** \brief Union type to access the Special-Purpose Program Status Registers (xPSR). + /** \brief Union type to access the Special-Purpose Program Status Registers (xPSR). */ -typedef union -{ - struct - { - uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */ + typedef union + { + struct + { + uint32_t ISR : 9; /*!< bit: 0.. 8 Exception number */ #if (__CORTEX_M != 0x07) - uint32_t _reserved0:15; /*!< bit: 9..23 Reserved */ + uint32_t _reserved0 : 15; /*!< bit: 9..23 Reserved */ #else - uint32_t _reserved0:7; /*!< bit: 9..15 Reserved */ - uint32_t GE:4; /*!< bit: 16..19 Greater than or Equal flags */ - uint32_t _reserved1:4; /*!< bit: 20..23 Reserved */ + uint32_t _reserved0 : 7; /*!< bit: 9..15 Reserved */ + uint32_t GE : 4; /*!< bit: 16..19 Greater than or Equal flags */ + uint32_t _reserved1 : 4; /*!< bit: 20..23 Reserved */ #endif - uint32_t T:1; /*!< bit: 24 Thumb bit (read 0) */ - uint32_t IT:2; /*!< bit: 25..26 saved IT state (read 0) */ - uint32_t Q:1; /*!< bit: 27 Saturation condition flag */ - uint32_t V:1; /*!< bit: 28 Overflow condition code flag */ - uint32_t C:1; /*!< bit: 29 Carry condition code flag */ - uint32_t Z:1; /*!< bit: 30 Zero condition code flag */ - uint32_t N:1; /*!< bit: 31 Negative condition code flag */ - } b; /*!< Structure used for bit access */ - uint32_t w; /*!< Type used for word access */ -} xPSR_Type; - + uint32_t T : 1; /*!< bit: 24 Thumb bit (read 0) */ + uint32_t IT : 2; /*!< bit: 25..26 saved IT state (read 0) */ + uint32_t Q : 1; /*!< bit: 27 Saturation condition flag */ + uint32_t V : 1; /*!< bit: 28 Overflow condition code flag */ + uint32_t C : 1; /*!< bit: 29 Carry condition code flag */ + uint32_t Z : 1; /*!< bit: 30 Zero condition code flag */ + uint32_t N : 1; /*!< bit: 31 Negative condition code flag */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ + } xPSR_Type; -/** \brief Union type to access the Control Registers (CONTROL). + /** \brief Union type to access the Control Registers (CONTROL). */ -typedef union -{ - struct - { - uint32_t nPRIV:1; /*!< bit: 0 Execution privilege in Thread mode */ - uint32_t SPSEL:1; /*!< bit: 1 Stack to be used */ - uint32_t FPCA:1; /*!< bit: 2 FP extension active flag */ - uint32_t _reserved0:29; /*!< bit: 3..31 Reserved */ - } b; /*!< Structure used for bit access */ - uint32_t w; /*!< Type used for word access */ -} CONTROL_Type; - -/*@} end of group CMSIS_CORE */ + typedef union + { + struct + { + uint32_t nPRIV : 1; /*!< bit: 0 Execution privilege in Thread mode */ + uint32_t SPSEL : 1; /*!< bit: 1 Stack to be used */ + uint32_t FPCA : 1; /*!< bit: 2 FP extension active flag */ + uint32_t _reserved0 : 29; /*!< bit: 3..31 Reserved */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ + } CONTROL_Type; + /*@} end of group CMSIS_CORE */ -/** \ingroup CMSIS_core_register + /** \ingroup CMSIS_core_register \defgroup CMSIS_NVIC Nested Vectored Interrupt Controller (NVIC) \brief Type definitions for the NVIC Registers @{ */ -/** \brief Structure type to access the Nested Vectored Interrupt Controller (NVIC). + /** \brief Structure type to access the Nested Vectored Interrupt Controller (NVIC). */ -typedef struct -{ - __IO uint32_t ISER[8]; /*!< Offset: 0x000 (R/W) Interrupt Set Enable Register */ - uint32_t RESERVED0[24]; - __IO uint32_t ICER[8]; /*!< Offset: 0x080 (R/W) Interrupt Clear Enable Register */ - uint32_t RSERVED1[24]; - __IO uint32_t ISPR[8]; /*!< Offset: 0x100 (R/W) Interrupt Set Pending Register */ - uint32_t RESERVED2[24]; - __IO uint32_t ICPR[8]; /*!< Offset: 0x180 (R/W) Interrupt Clear Pending Register */ - uint32_t RESERVED3[24]; - __IO uint32_t IABR[8]; /*!< Offset: 0x200 (R/W) Interrupt Active bit Register */ - uint32_t RESERVED4[56]; - __IO uint8_t IP[240]; /*!< Offset: 0x300 (R/W) Interrupt Priority Register (8Bit wide) */ - uint32_t RESERVED5[644]; - __O uint32_t STIR; /*!< Offset: 0xE00 ( /W) Software Trigger Interrupt Register */ -} NVIC_Type; + typedef struct + { + __IO uint32_t ISER[8]; /*!< Offset: 0x000 (R/W) Interrupt Set Enable Register */ + uint32_t RESERVED0[24]; + __IO uint32_t ICER[8]; /*!< Offset: 0x080 (R/W) Interrupt Clear Enable Register */ + uint32_t RSERVED1[24]; + __IO uint32_t ISPR[8]; /*!< Offset: 0x100 (R/W) Interrupt Set Pending Register */ + uint32_t RESERVED2[24]; + __IO uint32_t ICPR[8]; /*!< Offset: 0x180 (R/W) Interrupt Clear Pending Register */ + uint32_t RESERVED3[24]; + __IO uint32_t IABR[8]; /*!< Offset: 0x200 (R/W) Interrupt Active bit Register */ + uint32_t RESERVED4[56]; + __IO uint8_t IP[240]; /*!< Offset: 0x300 (R/W) Interrupt Priority Register (8Bit wide) */ + uint32_t RESERVED5[644]; + __O uint32_t STIR; /*!< Offset: 0xE00 ( /W) Software Trigger Interrupt Register */ + } NVIC_Type; /* Software Triggered Interrupt Register Definitions */ -#define NVIC_STIR_INTID_Pos 0 /*!< STIR: INTLINESNUM Position */ -#define NVIC_STIR_INTID_Msk (0x1FFUL << NVIC_STIR_INTID_Pos) /*!< STIR: INTLINESNUM Mask */ - -/*@} end of group CMSIS_NVIC */ +#define NVIC_STIR_INTID_Pos 0 /*!< STIR: INTLINESNUM Position */ +#define NVIC_STIR_INTID_Msk (0x1FFUL << NVIC_STIR_INTID_Pos) /*!< STIR: INTLINESNUM Mask */ + /*@} end of group CMSIS_NVIC */ -/** \ingroup CMSIS_core_register + /** \ingroup CMSIS_core_register \defgroup CMSIS_SCB System Control Block (SCB) \brief Type definitions for the System Control Block Registers @{ */ -/** \brief Structure type to access the System Control Block (SCB). + /** \brief Structure type to access the System Control Block (SCB). */ -typedef struct -{ - __I uint32_t CPUID; /*!< Offset: 0x000 (R/ ) CPUID Base Register */ - __IO uint32_t ICSR; /*!< Offset: 0x004 (R/W) Interrupt Control and State Register */ - __IO uint32_t VTOR; /*!< Offset: 0x008 (R/W) Vector Table Offset Register */ - __IO uint32_t AIRCR; /*!< Offset: 0x00C (R/W) Application Interrupt and Reset Control Register */ - __IO uint32_t SCR; /*!< Offset: 0x010 (R/W) System Control Register */ - __IO uint32_t CCR; /*!< Offset: 0x014 (R/W) Configuration Control Register */ - __IO uint8_t SHPR[12]; /*!< Offset: 0x018 (R/W) System Handlers Priority Registers (4-7, 8-11, 12-15) */ - __IO uint32_t SHCSR; /*!< Offset: 0x024 (R/W) System Handler Control and State Register */ - __IO uint32_t CFSR; /*!< Offset: 0x028 (R/W) Configurable Fault Status Register */ - __IO uint32_t HFSR; /*!< Offset: 0x02C (R/W) HardFault Status Register */ - __IO uint32_t DFSR; /*!< Offset: 0x030 (R/W) Debug Fault Status Register */ - __IO uint32_t MMFAR; /*!< Offset: 0x034 (R/W) MemManage Fault Address Register */ - __IO uint32_t BFAR; /*!< Offset: 0x038 (R/W) BusFault Address Register */ - __IO uint32_t AFSR; /*!< Offset: 0x03C (R/W) Auxiliary Fault Status Register */ - __I uint32_t ID_PFR[2]; /*!< Offset: 0x040 (R/ ) Processor Feature Register */ - __I uint32_t ID_DFR; /*!< Offset: 0x048 (R/ ) Debug Feature Register */ - __I uint32_t ID_AFR; /*!< Offset: 0x04C (R/ ) Auxiliary Feature Register */ - __I uint32_t ID_MFR[4]; /*!< Offset: 0x050 (R/ ) Memory Model Feature Register */ - __I uint32_t ID_ISAR[5]; /*!< Offset: 0x060 (R/ ) Instruction Set Attributes Register */ - uint32_t RESERVED0[1]; - __I uint32_t CLIDR; /*!< Offset: 0x078 (R/ ) Cache Level ID register */ - __I uint32_t CTR; /*!< Offset: 0x07C (R/ ) Cache Type register */ - __I uint32_t CCSIDR; /*!< Offset: 0x080 (R/ ) Cache Size ID Register */ - __IO uint32_t CSSELR; /*!< Offset: 0x084 (R/W) Cache Size Selection Register */ - __IO uint32_t CPACR; /*!< Offset: 0x088 (R/W) Coprocessor Access Control Register */ - uint32_t RESERVED3[93]; - __O uint32_t STIR; /*!< Offset: 0x200 ( /W) Software Triggered Interrupt Register */ - uint32_t RESERVED4[15]; - __I uint32_t MVFR0; /*!< Offset: 0x240 (R/ ) Media and VFP Feature Register 0 */ - __I uint32_t MVFR1; /*!< Offset: 0x244 (R/ ) Media and VFP Feature Register 1 */ - __I uint32_t MVFR2; /*!< Offset: 0x248 (R/ ) Media and VFP Feature Register 1 */ - uint32_t RESERVED5[1]; - __O uint32_t ICIALLU; /*!< Offset: 0x250 ( /W) I-Cache Invalidate All to PoU */ - uint32_t RESERVED6[1]; - __O uint32_t ICIMVAU; /*!< Offset: 0x258 ( /W) I-Cache Invalidate by MVA to PoU */ - __O uint32_t DCIMVAU; /*!< Offset: 0x25C ( /W) D-Cache Invalidate by MVA to PoC */ - __O uint32_t DCISW; /*!< Offset: 0x260 ( /W) D-Cache Invalidate by Set-way */ - __O uint32_t DCCMVAU; /*!< Offset: 0x264 ( /W) D-Cache Clean by MVA to PoU */ - __O uint32_t DCCMVAC; /*!< Offset: 0x268 ( /W) D-Cache Clean by MVA to PoC */ - __O uint32_t DCCSW; /*!< Offset: 0x26C ( /W) D-Cache Clean by Set-way */ - __O uint32_t DCCIMVAC; /*!< Offset: 0x270 ( /W) D-Cache Clean and Invalidate by MVA to PoC */ - __O uint32_t DCCISW; /*!< Offset: 0x274 ( /W) D-Cache Clean and Invalidate by Set-way */ - uint32_t RESERVED7[6]; - __IO uint32_t ITCMCR; /*!< Offset: 0x290 (R/W) Instruction Tightly-Coupled Memory Control Register */ - __IO uint32_t DTCMCR; /*!< Offset: 0x294 (R/W) Data Tightly-Coupled Memory Control Registers */ - __IO uint32_t AHBPCR; /*!< Offset: 0x298 (R/W) AHBP Control Register */ - __IO uint32_t CACR; /*!< Offset: 0x29C (R/W) L1 Cache Control Register */ - __IO uint32_t AHBSCR; /*!< Offset: 0x2A0 (R/W) AHB Slave Control Register */ - uint32_t RESERVED8[1]; - __IO uint32_t ABFSR; /*!< Offset: 0x2A8 (R/W) Auxiliary Bus Fault Status Register */ -} SCB_Type; + typedef struct + { + __I uint32_t CPUID; /*!< Offset: 0x000 (R/ ) CPUID Base Register */ + __IO uint32_t ICSR; /*!< Offset: 0x004 (R/W) Interrupt Control and State Register */ + __IO uint32_t VTOR; /*!< Offset: 0x008 (R/W) Vector Table Offset Register */ + __IO uint32_t AIRCR; /*!< Offset: 0x00C (R/W) Application Interrupt and Reset Control Register */ + __IO uint32_t SCR; /*!< Offset: 0x010 (R/W) System Control Register */ + __IO uint32_t CCR; /*!< Offset: 0x014 (R/W) Configuration Control Register */ + __IO uint8_t SHPR[12]; /*!< Offset: 0x018 (R/W) System Handlers Priority Registers (4-7, 8-11, 12-15) */ + __IO uint32_t SHCSR; /*!< Offset: 0x024 (R/W) System Handler Control and State Register */ + __IO uint32_t CFSR; /*!< Offset: 0x028 (R/W) Configurable Fault Status Register */ + __IO uint32_t HFSR; /*!< Offset: 0x02C (R/W) HardFault Status Register */ + __IO uint32_t DFSR; /*!< Offset: 0x030 (R/W) Debug Fault Status Register */ + __IO uint32_t MMFAR; /*!< Offset: 0x034 (R/W) MemManage Fault Address Register */ + __IO uint32_t BFAR; /*!< Offset: 0x038 (R/W) BusFault Address Register */ + __IO uint32_t AFSR; /*!< Offset: 0x03C (R/W) Auxiliary Fault Status Register */ + __I uint32_t ID_PFR[2]; /*!< Offset: 0x040 (R/ ) Processor Feature Register */ + __I uint32_t ID_DFR; /*!< Offset: 0x048 (R/ ) Debug Feature Register */ + __I uint32_t ID_AFR; /*!< Offset: 0x04C (R/ ) Auxiliary Feature Register */ + __I uint32_t ID_MFR[4]; /*!< Offset: 0x050 (R/ ) Memory Model Feature Register */ + __I uint32_t ID_ISAR[5]; /*!< Offset: 0x060 (R/ ) Instruction Set Attributes Register */ + uint32_t RESERVED0[1]; + __I uint32_t CLIDR; /*!< Offset: 0x078 (R/ ) Cache Level ID register */ + __I uint32_t CTR; /*!< Offset: 0x07C (R/ ) Cache Type register */ + __I uint32_t CCSIDR; /*!< Offset: 0x080 (R/ ) Cache Size ID Register */ + __IO uint32_t CSSELR; /*!< Offset: 0x084 (R/W) Cache Size Selection Register */ + __IO uint32_t CPACR; /*!< Offset: 0x088 (R/W) Coprocessor Access Control Register */ + uint32_t RESERVED3[93]; + __O uint32_t STIR; /*!< Offset: 0x200 ( /W) Software Triggered Interrupt Register */ + uint32_t RESERVED4[15]; + __I uint32_t MVFR0; /*!< Offset: 0x240 (R/ ) Media and VFP Feature Register 0 */ + __I uint32_t MVFR1; /*!< Offset: 0x244 (R/ ) Media and VFP Feature Register 1 */ + __I uint32_t MVFR2; /*!< Offset: 0x248 (R/ ) Media and VFP Feature Register 1 */ + uint32_t RESERVED5[1]; + __O uint32_t ICIALLU; /*!< Offset: 0x250 ( /W) I-Cache Invalidate All to PoU */ + uint32_t RESERVED6[1]; + __O uint32_t ICIMVAU; /*!< Offset: 0x258 ( /W) I-Cache Invalidate by MVA to PoU */ + __O uint32_t DCIMVAU; /*!< Offset: 0x25C ( /W) D-Cache Invalidate by MVA to PoC */ + __O uint32_t DCISW; /*!< Offset: 0x260 ( /W) D-Cache Invalidate by Set-way */ + __O uint32_t DCCMVAU; /*!< Offset: 0x264 ( /W) D-Cache Clean by MVA to PoU */ + __O uint32_t DCCMVAC; /*!< Offset: 0x268 ( /W) D-Cache Clean by MVA to PoC */ + __O uint32_t DCCSW; /*!< Offset: 0x26C ( /W) D-Cache Clean by Set-way */ + __O uint32_t DCCIMVAC; /*!< Offset: 0x270 ( /W) D-Cache Clean and Invalidate by MVA to PoC */ + __O uint32_t DCCISW; /*!< Offset: 0x274 ( /W) D-Cache Clean and Invalidate by Set-way */ + uint32_t RESERVED7[6]; + __IO uint32_t ITCMCR; /*!< Offset: 0x290 (R/W) Instruction Tightly-Coupled Memory Control Register */ + __IO uint32_t DTCMCR; /*!< Offset: 0x294 (R/W) Data Tightly-Coupled Memory Control Registers */ + __IO uint32_t AHBPCR; /*!< Offset: 0x298 (R/W) AHBP Control Register */ + __IO uint32_t CACR; /*!< Offset: 0x29C (R/W) L1 Cache Control Register */ + __IO uint32_t AHBSCR; /*!< Offset: 0x2A0 (R/W) AHB Slave Control Register */ + uint32_t RESERVED8[1]; + __IO uint32_t ABFSR; /*!< Offset: 0x2A8 (R/W) Auxiliary Bus Fault Status Register */ + } SCB_Type; /* SCB CPUID Register Definitions */ -#define SCB_CPUID_IMPLEMENTER_Pos 24 /*!< SCB CPUID: IMPLEMENTER Position */ -#define SCB_CPUID_IMPLEMENTER_Msk (0xFFUL << SCB_CPUID_IMPLEMENTER_Pos) /*!< SCB CPUID: IMPLEMENTER Mask */ +#define SCB_CPUID_IMPLEMENTER_Pos 24 /*!< SCB CPUID: IMPLEMENTER Position */ +#define SCB_CPUID_IMPLEMENTER_Msk (0xFFUL << SCB_CPUID_IMPLEMENTER_Pos) /*!< SCB CPUID: IMPLEMENTER Mask */ -#define SCB_CPUID_VARIANT_Pos 20 /*!< SCB CPUID: VARIANT Position */ -#define SCB_CPUID_VARIANT_Msk (0xFUL << SCB_CPUID_VARIANT_Pos) /*!< SCB CPUID: VARIANT Mask */ +#define SCB_CPUID_VARIANT_Pos 20 /*!< SCB CPUID: VARIANT Position */ +#define SCB_CPUID_VARIANT_Msk (0xFUL << SCB_CPUID_VARIANT_Pos) /*!< SCB CPUID: VARIANT Mask */ -#define SCB_CPUID_ARCHITECTURE_Pos 16 /*!< SCB CPUID: ARCHITECTURE Position */ -#define SCB_CPUID_ARCHITECTURE_Msk (0xFUL << SCB_CPUID_ARCHITECTURE_Pos) /*!< SCB CPUID: ARCHITECTURE Mask */ +#define SCB_CPUID_ARCHITECTURE_Pos 16 /*!< SCB CPUID: ARCHITECTURE Position */ +#define SCB_CPUID_ARCHITECTURE_Msk (0xFUL << SCB_CPUID_ARCHITECTURE_Pos) /*!< SCB CPUID: ARCHITECTURE Mask */ -#define SCB_CPUID_PARTNO_Pos 4 /*!< SCB CPUID: PARTNO Position */ -#define SCB_CPUID_PARTNO_Msk (0xFFFUL << SCB_CPUID_PARTNO_Pos) /*!< SCB CPUID: PARTNO Mask */ +#define SCB_CPUID_PARTNO_Pos 4 /*!< SCB CPUID: PARTNO Position */ +#define SCB_CPUID_PARTNO_Msk (0xFFFUL << SCB_CPUID_PARTNO_Pos) /*!< SCB CPUID: PARTNO Mask */ -#define SCB_CPUID_REVISION_Pos 0 /*!< SCB CPUID: REVISION Position */ -#define SCB_CPUID_REVISION_Msk (0xFUL << SCB_CPUID_REVISION_Pos) /*!< SCB CPUID: REVISION Mask */ +#define SCB_CPUID_REVISION_Pos 0 /*!< SCB CPUID: REVISION Position */ +#define SCB_CPUID_REVISION_Msk (0xFUL << SCB_CPUID_REVISION_Pos) /*!< SCB CPUID: REVISION Mask */ /* SCB Interrupt Control State Register Definitions */ -#define SCB_ICSR_NMIPENDSET_Pos 31 /*!< SCB ICSR: NMIPENDSET Position */ -#define SCB_ICSR_NMIPENDSET_Msk (1UL << SCB_ICSR_NMIPENDSET_Pos) /*!< SCB ICSR: NMIPENDSET Mask */ +#define SCB_ICSR_NMIPENDSET_Pos 31 /*!< SCB ICSR: NMIPENDSET Position */ +#define SCB_ICSR_NMIPENDSET_Msk (1UL << SCB_ICSR_NMIPENDSET_Pos) /*!< SCB ICSR: NMIPENDSET Mask */ -#define SCB_ICSR_PENDSVSET_Pos 28 /*!< SCB ICSR: PENDSVSET Position */ -#define SCB_ICSR_PENDSVSET_Msk (1UL << SCB_ICSR_PENDSVSET_Pos) /*!< SCB ICSR: PENDSVSET Mask */ +#define SCB_ICSR_PENDSVSET_Pos 28 /*!< SCB ICSR: PENDSVSET Position */ +#define SCB_ICSR_PENDSVSET_Msk (1UL << SCB_ICSR_PENDSVSET_Pos) /*!< SCB ICSR: PENDSVSET Mask */ -#define SCB_ICSR_PENDSVCLR_Pos 27 /*!< SCB ICSR: PENDSVCLR Position */ -#define SCB_ICSR_PENDSVCLR_Msk (1UL << SCB_ICSR_PENDSVCLR_Pos) /*!< SCB ICSR: PENDSVCLR Mask */ +#define SCB_ICSR_PENDSVCLR_Pos 27 /*!< SCB ICSR: PENDSVCLR Position */ +#define SCB_ICSR_PENDSVCLR_Msk (1UL << SCB_ICSR_PENDSVCLR_Pos) /*!< SCB ICSR: PENDSVCLR Mask */ -#define SCB_ICSR_PENDSTSET_Pos 26 /*!< SCB ICSR: PENDSTSET Position */ -#define SCB_ICSR_PENDSTSET_Msk (1UL << SCB_ICSR_PENDSTSET_Pos) /*!< SCB ICSR: PENDSTSET Mask */ +#define SCB_ICSR_PENDSTSET_Pos 26 /*!< SCB ICSR: PENDSTSET Position */ +#define SCB_ICSR_PENDSTSET_Msk (1UL << SCB_ICSR_PENDSTSET_Pos) /*!< SCB ICSR: PENDSTSET Mask */ -#define SCB_ICSR_PENDSTCLR_Pos 25 /*!< SCB ICSR: PENDSTCLR Position */ -#define SCB_ICSR_PENDSTCLR_Msk (1UL << SCB_ICSR_PENDSTCLR_Pos) /*!< SCB ICSR: PENDSTCLR Mask */ +#define SCB_ICSR_PENDSTCLR_Pos 25 /*!< SCB ICSR: PENDSTCLR Position */ +#define SCB_ICSR_PENDSTCLR_Msk (1UL << SCB_ICSR_PENDSTCLR_Pos) /*!< SCB ICSR: PENDSTCLR Mask */ -#define SCB_ICSR_ISRPREEMPT_Pos 23 /*!< SCB ICSR: ISRPREEMPT Position */ -#define SCB_ICSR_ISRPREEMPT_Msk (1UL << SCB_ICSR_ISRPREEMPT_Pos) /*!< SCB ICSR: ISRPREEMPT Mask */ +#define SCB_ICSR_ISRPREEMPT_Pos 23 /*!< SCB ICSR: ISRPREEMPT Position */ +#define SCB_ICSR_ISRPREEMPT_Msk (1UL << SCB_ICSR_ISRPREEMPT_Pos) /*!< SCB ICSR: ISRPREEMPT Mask */ -#define SCB_ICSR_ISRPENDING_Pos 22 /*!< SCB ICSR: ISRPENDING Position */ -#define SCB_ICSR_ISRPENDING_Msk (1UL << SCB_ICSR_ISRPENDING_Pos) /*!< SCB ICSR: ISRPENDING Mask */ +#define SCB_ICSR_ISRPENDING_Pos 22 /*!< SCB ICSR: ISRPENDING Position */ +#define SCB_ICSR_ISRPENDING_Msk (1UL << SCB_ICSR_ISRPENDING_Pos) /*!< SCB ICSR: ISRPENDING Mask */ -#define SCB_ICSR_VECTPENDING_Pos 12 /*!< SCB ICSR: VECTPENDING Position */ -#define SCB_ICSR_VECTPENDING_Msk (0x1FFUL << SCB_ICSR_VECTPENDING_Pos) /*!< SCB ICSR: VECTPENDING Mask */ +#define SCB_ICSR_VECTPENDING_Pos 12 /*!< SCB ICSR: VECTPENDING Position */ +#define SCB_ICSR_VECTPENDING_Msk (0x1FFUL << SCB_ICSR_VECTPENDING_Pos) /*!< SCB ICSR: VECTPENDING Mask */ -#define SCB_ICSR_RETTOBASE_Pos 11 /*!< SCB ICSR: RETTOBASE Position */ -#define SCB_ICSR_RETTOBASE_Msk (1UL << SCB_ICSR_RETTOBASE_Pos) /*!< SCB ICSR: RETTOBASE Mask */ +#define SCB_ICSR_RETTOBASE_Pos 11 /*!< SCB ICSR: RETTOBASE Position */ +#define SCB_ICSR_RETTOBASE_Msk (1UL << SCB_ICSR_RETTOBASE_Pos) /*!< SCB ICSR: RETTOBASE Mask */ -#define SCB_ICSR_VECTACTIVE_Pos 0 /*!< SCB ICSR: VECTACTIVE Position */ -#define SCB_ICSR_VECTACTIVE_Msk (0x1FFUL << SCB_ICSR_VECTACTIVE_Pos) /*!< SCB ICSR: VECTACTIVE Mask */ +#define SCB_ICSR_VECTACTIVE_Pos 0 /*!< SCB ICSR: VECTACTIVE Position */ +#define SCB_ICSR_VECTACTIVE_Msk (0x1FFUL << SCB_ICSR_VECTACTIVE_Pos) /*!< SCB ICSR: VECTACTIVE Mask */ /* SCB Vector Table Offset Register Definitions */ -#define SCB_VTOR_TBLOFF_Pos 7 /*!< SCB VTOR: TBLOFF Position */ -#define SCB_VTOR_TBLOFF_Msk (0x1FFFFFFUL << SCB_VTOR_TBLOFF_Pos) /*!< SCB VTOR: TBLOFF Mask */ +#define SCB_VTOR_TBLOFF_Pos 7 /*!< SCB VTOR: TBLOFF Position */ +#define SCB_VTOR_TBLOFF_Msk (0x1FFFFFFUL << SCB_VTOR_TBLOFF_Pos) /*!< SCB VTOR: TBLOFF Mask */ /* SCB Application Interrupt and Reset Control Register Definitions */ -#define SCB_AIRCR_VECTKEY_Pos 16 /*!< SCB AIRCR: VECTKEY Position */ -#define SCB_AIRCR_VECTKEY_Msk (0xFFFFUL << SCB_AIRCR_VECTKEY_Pos) /*!< SCB AIRCR: VECTKEY Mask */ +#define SCB_AIRCR_VECTKEY_Pos 16 /*!< SCB AIRCR: VECTKEY Position */ +#define SCB_AIRCR_VECTKEY_Msk (0xFFFFUL << SCB_AIRCR_VECTKEY_Pos) /*!< SCB AIRCR: VECTKEY Mask */ -#define SCB_AIRCR_VECTKEYSTAT_Pos 16 /*!< SCB AIRCR: VECTKEYSTAT Position */ -#define SCB_AIRCR_VECTKEYSTAT_Msk (0xFFFFUL << SCB_AIRCR_VECTKEYSTAT_Pos) /*!< SCB AIRCR: VECTKEYSTAT Mask */ +#define SCB_AIRCR_VECTKEYSTAT_Pos 16 /*!< SCB AIRCR: VECTKEYSTAT Position */ +#define SCB_AIRCR_VECTKEYSTAT_Msk (0xFFFFUL << SCB_AIRCR_VECTKEYSTAT_Pos) /*!< SCB AIRCR: VECTKEYSTAT Mask */ -#define SCB_AIRCR_ENDIANESS_Pos 15 /*!< SCB AIRCR: ENDIANESS Position */ -#define SCB_AIRCR_ENDIANESS_Msk (1UL << SCB_AIRCR_ENDIANESS_Pos) /*!< SCB AIRCR: ENDIANESS Mask */ +#define SCB_AIRCR_ENDIANESS_Pos 15 /*!< SCB AIRCR: ENDIANESS Position */ +#define SCB_AIRCR_ENDIANESS_Msk (1UL << SCB_AIRCR_ENDIANESS_Pos) /*!< SCB AIRCR: ENDIANESS Mask */ -#define SCB_AIRCR_PRIGROUP_Pos 8 /*!< SCB AIRCR: PRIGROUP Position */ -#define SCB_AIRCR_PRIGROUP_Msk (7UL << SCB_AIRCR_PRIGROUP_Pos) /*!< SCB AIRCR: PRIGROUP Mask */ +#define SCB_AIRCR_PRIGROUP_Pos 8 /*!< SCB AIRCR: PRIGROUP Position */ +#define SCB_AIRCR_PRIGROUP_Msk (7UL << SCB_AIRCR_PRIGROUP_Pos) /*!< SCB AIRCR: PRIGROUP Mask */ -#define SCB_AIRCR_SYSRESETREQ_Pos 2 /*!< SCB AIRCR: SYSRESETREQ Position */ -#define SCB_AIRCR_SYSRESETREQ_Msk (1UL << SCB_AIRCR_SYSRESETREQ_Pos) /*!< SCB AIRCR: SYSRESETREQ Mask */ +#define SCB_AIRCR_SYSRESETREQ_Pos 2 /*!< SCB AIRCR: SYSRESETREQ Position */ +#define SCB_AIRCR_SYSRESETREQ_Msk (1UL << SCB_AIRCR_SYSRESETREQ_Pos) /*!< SCB AIRCR: SYSRESETREQ Mask */ -#define SCB_AIRCR_VECTCLRACTIVE_Pos 1 /*!< SCB AIRCR: VECTCLRACTIVE Position */ -#define SCB_AIRCR_VECTCLRACTIVE_Msk (1UL << SCB_AIRCR_VECTCLRACTIVE_Pos) /*!< SCB AIRCR: VECTCLRACTIVE Mask */ +#define SCB_AIRCR_VECTCLRACTIVE_Pos 1 /*!< SCB AIRCR: VECTCLRACTIVE Position */ +#define SCB_AIRCR_VECTCLRACTIVE_Msk (1UL << SCB_AIRCR_VECTCLRACTIVE_Pos) /*!< SCB AIRCR: VECTCLRACTIVE Mask */ -#define SCB_AIRCR_VECTRESET_Pos 0 /*!< SCB AIRCR: VECTRESET Position */ -#define SCB_AIRCR_VECTRESET_Msk (1UL << SCB_AIRCR_VECTRESET_Pos) /*!< SCB AIRCR: VECTRESET Mask */ +#define SCB_AIRCR_VECTRESET_Pos 0 /*!< SCB AIRCR: VECTRESET Position */ +#define SCB_AIRCR_VECTRESET_Msk (1UL << SCB_AIRCR_VECTRESET_Pos) /*!< SCB AIRCR: VECTRESET Mask */ /* SCB System Control Register Definitions */ -#define SCB_SCR_SEVONPEND_Pos 4 /*!< SCB SCR: SEVONPEND Position */ -#define SCB_SCR_SEVONPEND_Msk (1UL << SCB_SCR_SEVONPEND_Pos) /*!< SCB SCR: SEVONPEND Mask */ +#define SCB_SCR_SEVONPEND_Pos 4 /*!< SCB SCR: SEVONPEND Position */ +#define SCB_SCR_SEVONPEND_Msk (1UL << SCB_SCR_SEVONPEND_Pos) /*!< SCB SCR: SEVONPEND Mask */ -#define SCB_SCR_SLEEPDEEP_Pos 2 /*!< SCB SCR: SLEEPDEEP Position */ -#define SCB_SCR_SLEEPDEEP_Msk (1UL << SCB_SCR_SLEEPDEEP_Pos) /*!< SCB SCR: SLEEPDEEP Mask */ +#define SCB_SCR_SLEEPDEEP_Pos 2 /*!< SCB SCR: SLEEPDEEP Position */ +#define SCB_SCR_SLEEPDEEP_Msk (1UL << SCB_SCR_SLEEPDEEP_Pos) /*!< SCB SCR: SLEEPDEEP Mask */ -#define SCB_SCR_SLEEPONEXIT_Pos 1 /*!< SCB SCR: SLEEPONEXIT Position */ -#define SCB_SCR_SLEEPONEXIT_Msk (1UL << SCB_SCR_SLEEPONEXIT_Pos) /*!< SCB SCR: SLEEPONEXIT Mask */ +#define SCB_SCR_SLEEPONEXIT_Pos 1 /*!< SCB SCR: SLEEPONEXIT Position */ +#define SCB_SCR_SLEEPONEXIT_Msk (1UL << SCB_SCR_SLEEPONEXIT_Pos) /*!< SCB SCR: SLEEPONEXIT Mask */ /* SCB Configuration Control Register Definitions */ -#define SCB_CCR_BP_Pos 18 /*!< SCB CCR: Branch prediction enable bit Position */ -#define SCB_CCR_BP_Msk (1UL << SCB_CCR_BP_Pos) /*!< SCB CCR: Branch prediction enable bit Mask */ +#define SCB_CCR_BP_Pos 18 /*!< SCB CCR: Branch prediction enable bit Position */ +#define SCB_CCR_BP_Msk (1UL << SCB_CCR_BP_Pos) /*!< SCB CCR: Branch prediction enable bit Mask */ -#define SCB_CCR_IC_Pos 17 /*!< SCB CCR: Instruction cache enable bit Position */ -#define SCB_CCR_IC_Msk (1UL << SCB_CCR_IC_Pos) /*!< SCB CCR: Instruction cache enable bit Mask */ +#define SCB_CCR_IC_Pos 17 /*!< SCB CCR: Instruction cache enable bit Position */ +#define SCB_CCR_IC_Msk (1UL << SCB_CCR_IC_Pos) /*!< SCB CCR: Instruction cache enable bit Mask */ -#define SCB_CCR_DC_Pos 16 /*!< SCB CCR: Cache enable bit Position */ -#define SCB_CCR_DC_Msk (1UL << SCB_CCR_DC_Pos) /*!< SCB CCR: Cache enable bit Mask */ +#define SCB_CCR_DC_Pos 16 /*!< SCB CCR: Cache enable bit Position */ +#define SCB_CCR_DC_Msk (1UL << SCB_CCR_DC_Pos) /*!< SCB CCR: Cache enable bit Mask */ -#define SCB_CCR_STKALIGN_Pos 9 /*!< SCB CCR: STKALIGN Position */ -#define SCB_CCR_STKALIGN_Msk (1UL << SCB_CCR_STKALIGN_Pos) /*!< SCB CCR: STKALIGN Mask */ +#define SCB_CCR_STKALIGN_Pos 9 /*!< SCB CCR: STKALIGN Position */ +#define SCB_CCR_STKALIGN_Msk (1UL << SCB_CCR_STKALIGN_Pos) /*!< SCB CCR: STKALIGN Mask */ -#define SCB_CCR_BFHFNMIGN_Pos 8 /*!< SCB CCR: BFHFNMIGN Position */ -#define SCB_CCR_BFHFNMIGN_Msk (1UL << SCB_CCR_BFHFNMIGN_Pos) /*!< SCB CCR: BFHFNMIGN Mask */ +#define SCB_CCR_BFHFNMIGN_Pos 8 /*!< SCB CCR: BFHFNMIGN Position */ +#define SCB_CCR_BFHFNMIGN_Msk (1UL << SCB_CCR_BFHFNMIGN_Pos) /*!< SCB CCR: BFHFNMIGN Mask */ -#define SCB_CCR_DIV_0_TRP_Pos 4 /*!< SCB CCR: DIV_0_TRP Position */ -#define SCB_CCR_DIV_0_TRP_Msk (1UL << SCB_CCR_DIV_0_TRP_Pos) /*!< SCB CCR: DIV_0_TRP Mask */ +#define SCB_CCR_DIV_0_TRP_Pos 4 /*!< SCB CCR: DIV_0_TRP Position */ +#define SCB_CCR_DIV_0_TRP_Msk (1UL << SCB_CCR_DIV_0_TRP_Pos) /*!< SCB CCR: DIV_0_TRP Mask */ -#define SCB_CCR_UNALIGN_TRP_Pos 3 /*!< SCB CCR: UNALIGN_TRP Position */ -#define SCB_CCR_UNALIGN_TRP_Msk (1UL << SCB_CCR_UNALIGN_TRP_Pos) /*!< SCB CCR: UNALIGN_TRP Mask */ +#define SCB_CCR_UNALIGN_TRP_Pos 3 /*!< SCB CCR: UNALIGN_TRP Position */ +#define SCB_CCR_UNALIGN_TRP_Msk (1UL << SCB_CCR_UNALIGN_TRP_Pos) /*!< SCB CCR: UNALIGN_TRP Mask */ -#define SCB_CCR_USERSETMPEND_Pos 1 /*!< SCB CCR: USERSETMPEND Position */ -#define SCB_CCR_USERSETMPEND_Msk (1UL << SCB_CCR_USERSETMPEND_Pos) /*!< SCB CCR: USERSETMPEND Mask */ +#define SCB_CCR_USERSETMPEND_Pos 1 /*!< SCB CCR: USERSETMPEND Position */ +#define SCB_CCR_USERSETMPEND_Msk (1UL << SCB_CCR_USERSETMPEND_Pos) /*!< SCB CCR: USERSETMPEND Mask */ -#define SCB_CCR_NONBASETHRDENA_Pos 0 /*!< SCB CCR: NONBASETHRDENA Position */ -#define SCB_CCR_NONBASETHRDENA_Msk (1UL << SCB_CCR_NONBASETHRDENA_Pos) /*!< SCB CCR: NONBASETHRDENA Mask */ +#define SCB_CCR_NONBASETHRDENA_Pos 0 /*!< SCB CCR: NONBASETHRDENA Position */ +#define SCB_CCR_NONBASETHRDENA_Msk (1UL << SCB_CCR_NONBASETHRDENA_Pos) /*!< SCB CCR: NONBASETHRDENA Mask */ /* SCB System Handler Control and State Register Definitions */ -#define SCB_SHCSR_USGFAULTENA_Pos 18 /*!< SCB SHCSR: USGFAULTENA Position */ -#define SCB_SHCSR_USGFAULTENA_Msk (1UL << SCB_SHCSR_USGFAULTENA_Pos) /*!< SCB SHCSR: USGFAULTENA Mask */ +#define SCB_SHCSR_USGFAULTENA_Pos 18 /*!< SCB SHCSR: USGFAULTENA Position */ +#define SCB_SHCSR_USGFAULTENA_Msk (1UL << SCB_SHCSR_USGFAULTENA_Pos) /*!< SCB SHCSR: USGFAULTENA Mask */ -#define SCB_SHCSR_BUSFAULTENA_Pos 17 /*!< SCB SHCSR: BUSFAULTENA Position */ -#define SCB_SHCSR_BUSFAULTENA_Msk (1UL << SCB_SHCSR_BUSFAULTENA_Pos) /*!< SCB SHCSR: BUSFAULTENA Mask */ +#define SCB_SHCSR_BUSFAULTENA_Pos 17 /*!< SCB SHCSR: BUSFAULTENA Position */ +#define SCB_SHCSR_BUSFAULTENA_Msk (1UL << SCB_SHCSR_BUSFAULTENA_Pos) /*!< SCB SHCSR: BUSFAULTENA Mask */ -#define SCB_SHCSR_MEMFAULTENA_Pos 16 /*!< SCB SHCSR: MEMFAULTENA Position */ -#define SCB_SHCSR_MEMFAULTENA_Msk (1UL << SCB_SHCSR_MEMFAULTENA_Pos) /*!< SCB SHCSR: MEMFAULTENA Mask */ +#define SCB_SHCSR_MEMFAULTENA_Pos 16 /*!< SCB SHCSR: MEMFAULTENA Position */ +#define SCB_SHCSR_MEMFAULTENA_Msk (1UL << SCB_SHCSR_MEMFAULTENA_Pos) /*!< SCB SHCSR: MEMFAULTENA Mask */ -#define SCB_SHCSR_SVCALLPENDED_Pos 15 /*!< SCB SHCSR: SVCALLPENDED Position */ -#define SCB_SHCSR_SVCALLPENDED_Msk (1UL << SCB_SHCSR_SVCALLPENDED_Pos) /*!< SCB SHCSR: SVCALLPENDED Mask */ +#define SCB_SHCSR_SVCALLPENDED_Pos 15 /*!< SCB SHCSR: SVCALLPENDED Position */ +#define SCB_SHCSR_SVCALLPENDED_Msk (1UL << SCB_SHCSR_SVCALLPENDED_Pos) /*!< SCB SHCSR: SVCALLPENDED Mask */ -#define SCB_SHCSR_BUSFAULTPENDED_Pos 14 /*!< SCB SHCSR: BUSFAULTPENDED Position */ -#define SCB_SHCSR_BUSFAULTPENDED_Msk (1UL << SCB_SHCSR_BUSFAULTPENDED_Pos) /*!< SCB SHCSR: BUSFAULTPENDED Mask */ +#define SCB_SHCSR_BUSFAULTPENDED_Pos 14 /*!< SCB SHCSR: BUSFAULTPENDED Position */ +#define SCB_SHCSR_BUSFAULTPENDED_Msk (1UL << SCB_SHCSR_BUSFAULTPENDED_Pos) /*!< SCB SHCSR: BUSFAULTPENDED Mask */ -#define SCB_SHCSR_MEMFAULTPENDED_Pos 13 /*!< SCB SHCSR: MEMFAULTPENDED Position */ -#define SCB_SHCSR_MEMFAULTPENDED_Msk (1UL << SCB_SHCSR_MEMFAULTPENDED_Pos) /*!< SCB SHCSR: MEMFAULTPENDED Mask */ +#define SCB_SHCSR_MEMFAULTPENDED_Pos 13 /*!< SCB SHCSR: MEMFAULTPENDED Position */ +#define SCB_SHCSR_MEMFAULTPENDED_Msk (1UL << SCB_SHCSR_MEMFAULTPENDED_Pos) /*!< SCB SHCSR: MEMFAULTPENDED Mask */ -#define SCB_SHCSR_USGFAULTPENDED_Pos 12 /*!< SCB SHCSR: USGFAULTPENDED Position */ -#define SCB_SHCSR_USGFAULTPENDED_Msk (1UL << SCB_SHCSR_USGFAULTPENDED_Pos) /*!< SCB SHCSR: USGFAULTPENDED Mask */ +#define SCB_SHCSR_USGFAULTPENDED_Pos 12 /*!< SCB SHCSR: USGFAULTPENDED Position */ +#define SCB_SHCSR_USGFAULTPENDED_Msk (1UL << SCB_SHCSR_USGFAULTPENDED_Pos) /*!< SCB SHCSR: USGFAULTPENDED Mask */ -#define SCB_SHCSR_SYSTICKACT_Pos 11 /*!< SCB SHCSR: SYSTICKACT Position */ -#define SCB_SHCSR_SYSTICKACT_Msk (1UL << SCB_SHCSR_SYSTICKACT_Pos) /*!< SCB SHCSR: SYSTICKACT Mask */ +#define SCB_SHCSR_SYSTICKACT_Pos 11 /*!< SCB SHCSR: SYSTICKACT Position */ +#define SCB_SHCSR_SYSTICKACT_Msk (1UL << SCB_SHCSR_SYSTICKACT_Pos) /*!< SCB SHCSR: SYSTICKACT Mask */ -#define SCB_SHCSR_PENDSVACT_Pos 10 /*!< SCB SHCSR: PENDSVACT Position */ -#define SCB_SHCSR_PENDSVACT_Msk (1UL << SCB_SHCSR_PENDSVACT_Pos) /*!< SCB SHCSR: PENDSVACT Mask */ +#define SCB_SHCSR_PENDSVACT_Pos 10 /*!< SCB SHCSR: PENDSVACT Position */ +#define SCB_SHCSR_PENDSVACT_Msk (1UL << SCB_SHCSR_PENDSVACT_Pos) /*!< SCB SHCSR: PENDSVACT Mask */ -#define SCB_SHCSR_MONITORACT_Pos 8 /*!< SCB SHCSR: MONITORACT Position */ -#define SCB_SHCSR_MONITORACT_Msk (1UL << SCB_SHCSR_MONITORACT_Pos) /*!< SCB SHCSR: MONITORACT Mask */ +#define SCB_SHCSR_MONITORACT_Pos 8 /*!< SCB SHCSR: MONITORACT Position */ +#define SCB_SHCSR_MONITORACT_Msk (1UL << SCB_SHCSR_MONITORACT_Pos) /*!< SCB SHCSR: MONITORACT Mask */ -#define SCB_SHCSR_SVCALLACT_Pos 7 /*!< SCB SHCSR: SVCALLACT Position */ -#define SCB_SHCSR_SVCALLACT_Msk (1UL << SCB_SHCSR_SVCALLACT_Pos) /*!< SCB SHCSR: SVCALLACT Mask */ +#define SCB_SHCSR_SVCALLACT_Pos 7 /*!< SCB SHCSR: SVCALLACT Position */ +#define SCB_SHCSR_SVCALLACT_Msk (1UL << SCB_SHCSR_SVCALLACT_Pos) /*!< SCB SHCSR: SVCALLACT Mask */ -#define SCB_SHCSR_USGFAULTACT_Pos 3 /*!< SCB SHCSR: USGFAULTACT Position */ -#define SCB_SHCSR_USGFAULTACT_Msk (1UL << SCB_SHCSR_USGFAULTACT_Pos) /*!< SCB SHCSR: USGFAULTACT Mask */ +#define SCB_SHCSR_USGFAULTACT_Pos 3 /*!< SCB SHCSR: USGFAULTACT Position */ +#define SCB_SHCSR_USGFAULTACT_Msk (1UL << SCB_SHCSR_USGFAULTACT_Pos) /*!< SCB SHCSR: USGFAULTACT Mask */ -#define SCB_SHCSR_BUSFAULTACT_Pos 1 /*!< SCB SHCSR: BUSFAULTACT Position */ -#define SCB_SHCSR_BUSFAULTACT_Msk (1UL << SCB_SHCSR_BUSFAULTACT_Pos) /*!< SCB SHCSR: BUSFAULTACT Mask */ +#define SCB_SHCSR_BUSFAULTACT_Pos 1 /*!< SCB SHCSR: BUSFAULTACT Position */ +#define SCB_SHCSR_BUSFAULTACT_Msk (1UL << SCB_SHCSR_BUSFAULTACT_Pos) /*!< SCB SHCSR: BUSFAULTACT Mask */ -#define SCB_SHCSR_MEMFAULTACT_Pos 0 /*!< SCB SHCSR: MEMFAULTACT Position */ -#define SCB_SHCSR_MEMFAULTACT_Msk (1UL << SCB_SHCSR_MEMFAULTACT_Pos) /*!< SCB SHCSR: MEMFAULTACT Mask */ +#define SCB_SHCSR_MEMFAULTACT_Pos 0 /*!< SCB SHCSR: MEMFAULTACT Position */ +#define SCB_SHCSR_MEMFAULTACT_Msk (1UL << SCB_SHCSR_MEMFAULTACT_Pos) /*!< SCB SHCSR: MEMFAULTACT Mask */ /* SCB Configurable Fault Status Registers Definitions */ -#define SCB_CFSR_USGFAULTSR_Pos 16 /*!< SCB CFSR: Usage Fault Status Register Position */ -#define SCB_CFSR_USGFAULTSR_Msk (0xFFFFUL << SCB_CFSR_USGFAULTSR_Pos) /*!< SCB CFSR: Usage Fault Status Register Mask */ +#define SCB_CFSR_USGFAULTSR_Pos 16 /*!< SCB CFSR: Usage Fault Status Register Position */ +#define SCB_CFSR_USGFAULTSR_Msk (0xFFFFUL << SCB_CFSR_USGFAULTSR_Pos) /*!< SCB CFSR: Usage Fault Status Register Mask */ -#define SCB_CFSR_BUSFAULTSR_Pos 8 /*!< SCB CFSR: Bus Fault Status Register Position */ -#define SCB_CFSR_BUSFAULTSR_Msk (0xFFUL << SCB_CFSR_BUSFAULTSR_Pos) /*!< SCB CFSR: Bus Fault Status Register Mask */ +#define SCB_CFSR_BUSFAULTSR_Pos 8 /*!< SCB CFSR: Bus Fault Status Register Position */ +#define SCB_CFSR_BUSFAULTSR_Msk (0xFFUL << SCB_CFSR_BUSFAULTSR_Pos) /*!< SCB CFSR: Bus Fault Status Register Mask */ -#define SCB_CFSR_MEMFAULTSR_Pos 0 /*!< SCB CFSR: Memory Manage Fault Status Register Position */ -#define SCB_CFSR_MEMFAULTSR_Msk (0xFFUL << SCB_CFSR_MEMFAULTSR_Pos) /*!< SCB CFSR: Memory Manage Fault Status Register Mask */ +#define SCB_CFSR_MEMFAULTSR_Pos 0 /*!< SCB CFSR: Memory Manage Fault Status Register Position */ +#define SCB_CFSR_MEMFAULTSR_Msk (0xFFUL << SCB_CFSR_MEMFAULTSR_Pos) /*!< SCB CFSR: Memory Manage Fault Status Register Mask */ /* SCB Hard Fault Status Registers Definitions */ -#define SCB_HFSR_DEBUGEVT_Pos 31 /*!< SCB HFSR: DEBUGEVT Position */ -#define SCB_HFSR_DEBUGEVT_Msk (1UL << SCB_HFSR_DEBUGEVT_Pos) /*!< SCB HFSR: DEBUGEVT Mask */ +#define SCB_HFSR_DEBUGEVT_Pos 31 /*!< SCB HFSR: DEBUGEVT Position */ +#define SCB_HFSR_DEBUGEVT_Msk (1UL << SCB_HFSR_DEBUGEVT_Pos) /*!< SCB HFSR: DEBUGEVT Mask */ -#define SCB_HFSR_FORCED_Pos 30 /*!< SCB HFSR: FORCED Position */ -#define SCB_HFSR_FORCED_Msk (1UL << SCB_HFSR_FORCED_Pos) /*!< SCB HFSR: FORCED Mask */ +#define SCB_HFSR_FORCED_Pos 30 /*!< SCB HFSR: FORCED Position */ +#define SCB_HFSR_FORCED_Msk (1UL << SCB_HFSR_FORCED_Pos) /*!< SCB HFSR: FORCED Mask */ -#define SCB_HFSR_VECTTBL_Pos 1 /*!< SCB HFSR: VECTTBL Position */ -#define SCB_HFSR_VECTTBL_Msk (1UL << SCB_HFSR_VECTTBL_Pos) /*!< SCB HFSR: VECTTBL Mask */ +#define SCB_HFSR_VECTTBL_Pos 1 /*!< SCB HFSR: VECTTBL Position */ +#define SCB_HFSR_VECTTBL_Msk (1UL << SCB_HFSR_VECTTBL_Pos) /*!< SCB HFSR: VECTTBL Mask */ /* SCB Debug Fault Status Register Definitions */ -#define SCB_DFSR_EXTERNAL_Pos 4 /*!< SCB DFSR: EXTERNAL Position */ -#define SCB_DFSR_EXTERNAL_Msk (1UL << SCB_DFSR_EXTERNAL_Pos) /*!< SCB DFSR: EXTERNAL Mask */ +#define SCB_DFSR_EXTERNAL_Pos 4 /*!< SCB DFSR: EXTERNAL Position */ +#define SCB_DFSR_EXTERNAL_Msk (1UL << SCB_DFSR_EXTERNAL_Pos) /*!< SCB DFSR: EXTERNAL Mask */ -#define SCB_DFSR_VCATCH_Pos 3 /*!< SCB DFSR: VCATCH Position */ -#define SCB_DFSR_VCATCH_Msk (1UL << SCB_DFSR_VCATCH_Pos) /*!< SCB DFSR: VCATCH Mask */ +#define SCB_DFSR_VCATCH_Pos 3 /*!< SCB DFSR: VCATCH Position */ +#define SCB_DFSR_VCATCH_Msk (1UL << SCB_DFSR_VCATCH_Pos) /*!< SCB DFSR: VCATCH Mask */ -#define SCB_DFSR_DWTTRAP_Pos 2 /*!< SCB DFSR: DWTTRAP Position */ -#define SCB_DFSR_DWTTRAP_Msk (1UL << SCB_DFSR_DWTTRAP_Pos) /*!< SCB DFSR: DWTTRAP Mask */ +#define SCB_DFSR_DWTTRAP_Pos 2 /*!< SCB DFSR: DWTTRAP Position */ +#define SCB_DFSR_DWTTRAP_Msk (1UL << SCB_DFSR_DWTTRAP_Pos) /*!< SCB DFSR: DWTTRAP Mask */ -#define SCB_DFSR_BKPT_Pos 1 /*!< SCB DFSR: BKPT Position */ -#define SCB_DFSR_BKPT_Msk (1UL << SCB_DFSR_BKPT_Pos) /*!< SCB DFSR: BKPT Mask */ +#define SCB_DFSR_BKPT_Pos 1 /*!< SCB DFSR: BKPT Position */ +#define SCB_DFSR_BKPT_Msk (1UL << SCB_DFSR_BKPT_Pos) /*!< SCB DFSR: BKPT Mask */ -#define SCB_DFSR_HALTED_Pos 0 /*!< SCB DFSR: HALTED Position */ -#define SCB_DFSR_HALTED_Msk (1UL << SCB_DFSR_HALTED_Pos) /*!< SCB DFSR: HALTED Mask */ +#define SCB_DFSR_HALTED_Pos 0 /*!< SCB DFSR: HALTED Position */ +#define SCB_DFSR_HALTED_Msk (1UL << SCB_DFSR_HALTED_Pos) /*!< SCB DFSR: HALTED Mask */ /* Cache Level ID register */ -#define SCB_CLIDR_LOUU_Pos 27 /*!< SCB CLIDR: LoUU Position */ -#define SCB_CLIDR_LOUU_Msk (7UL << SCB_CLIDR_LOUU_Pos) /*!< SCB CLIDR: LoUU Mask */ +#define SCB_CLIDR_LOUU_Pos 27 /*!< SCB CLIDR: LoUU Position */ +#define SCB_CLIDR_LOUU_Msk (7UL << SCB_CLIDR_LOUU_Pos) /*!< SCB CLIDR: LoUU Mask */ -#define SCB_CLIDR_LOC_Pos 24 /*!< SCB CLIDR: LoC Position */ -#define SCB_CLIDR_LOC_Msk (7UL << SCB_CLIDR_FORMAT_Pos) /*!< SCB CLIDR: LoC Mask */ +#define SCB_CLIDR_LOC_Pos 24 /*!< SCB CLIDR: LoC Position */ +#define SCB_CLIDR_LOC_Msk (7UL << SCB_CLIDR_FORMAT_Pos) /*!< SCB CLIDR: LoC Mask */ /* Cache Type register */ -#define SCB_CTR_FORMAT_Pos 29 /*!< SCB CTR: Format Position */ -#define SCB_CTR_FORMAT_Msk (7UL << SCB_CTR_FORMAT_Pos) /*!< SCB CTR: Format Mask */ +#define SCB_CTR_FORMAT_Pos 29 /*!< SCB CTR: Format Position */ +#define SCB_CTR_FORMAT_Msk (7UL << SCB_CTR_FORMAT_Pos) /*!< SCB CTR: Format Mask */ -#define SCB_CTR_CWG_Pos 24 /*!< SCB CTR: CWG Position */ -#define SCB_CTR_CWG_Msk (0xFUL << SCB_CTR_CWG_Pos) /*!< SCB CTR: CWG Mask */ +#define SCB_CTR_CWG_Pos 24 /*!< SCB CTR: CWG Position */ +#define SCB_CTR_CWG_Msk (0xFUL << SCB_CTR_CWG_Pos) /*!< SCB CTR: CWG Mask */ -#define SCB_CTR_ERG_Pos 20 /*!< SCB CTR: ERG Position */ -#define SCB_CTR_ERG_Msk (0xFUL << SCB_CTR_ERG_Pos) /*!< SCB CTR: ERG Mask */ +#define SCB_CTR_ERG_Pos 20 /*!< SCB CTR: ERG Position */ +#define SCB_CTR_ERG_Msk (0xFUL << SCB_CTR_ERG_Pos) /*!< SCB CTR: ERG Mask */ -#define SCB_CTR_DMINLINE_Pos 16 /*!< SCB CTR: DminLine Position */ -#define SCB_CTR_DMINLINE_Msk (0xFUL << SCB_CTR_DMINLINE_Pos) /*!< SCB CTR: DminLine Mask */ +#define SCB_CTR_DMINLINE_Pos 16 /*!< SCB CTR: DminLine Position */ +#define SCB_CTR_DMINLINE_Msk (0xFUL << SCB_CTR_DMINLINE_Pos) /*!< SCB CTR: DminLine Mask */ -#define SCB_CTR_IMINLINE_Pos 0 /*!< SCB CTR: ImInLine Position */ -#define SCB_CTR_IMINLINE_Msk (0xFUL << SCB_CTR_IMINLINE_Pos) /*!< SCB CTR: ImInLine Mask */ +#define SCB_CTR_IMINLINE_Pos 0 /*!< SCB CTR: ImInLine Position */ +#define SCB_CTR_IMINLINE_Msk (0xFUL << SCB_CTR_IMINLINE_Pos) /*!< SCB CTR: ImInLine Mask */ /* Cache Size ID Register */ -#define SCB_CCSIDR_WT_Pos 31 /*!< SCB CCSIDR: WT Position */ -#define SCB_CCSIDR_WT_Msk (7UL << SCB_CCSIDR_WT_Pos) /*!< SCB CCSIDR: WT Mask */ +#define SCB_CCSIDR_WT_Pos 31 /*!< SCB CCSIDR: WT Position */ +#define SCB_CCSIDR_WT_Msk (7UL << SCB_CCSIDR_WT_Pos) /*!< SCB CCSIDR: WT Mask */ -#define SCB_CCSIDR_WB_Pos 30 /*!< SCB CCSIDR: WB Position */ -#define SCB_CCSIDR_WB_Msk (7UL << SCB_CCSIDR_WB_Pos) /*!< SCB CCSIDR: WB Mask */ +#define SCB_CCSIDR_WB_Pos 30 /*!< SCB CCSIDR: WB Position */ +#define SCB_CCSIDR_WB_Msk (7UL << SCB_CCSIDR_WB_Pos) /*!< SCB CCSIDR: WB Mask */ -#define SCB_CCSIDR_RA_Pos 29 /*!< SCB CCSIDR: RA Position */ -#define SCB_CCSIDR_RA_Msk (7UL << SCB_CCSIDR_RA_Pos) /*!< SCB CCSIDR: RA Mask */ +#define SCB_CCSIDR_RA_Pos 29 /*!< SCB CCSIDR: RA Position */ +#define SCB_CCSIDR_RA_Msk (7UL << SCB_CCSIDR_RA_Pos) /*!< SCB CCSIDR: RA Mask */ -#define SCB_CCSIDR_WA_Pos 28 /*!< SCB CCSIDR: WA Position */ -#define SCB_CCSIDR_WA_Msk (7UL << SCB_CCSIDR_WA_Pos) /*!< SCB CCSIDR: WA Mask */ +#define SCB_CCSIDR_WA_Pos 28 /*!< SCB CCSIDR: WA Position */ +#define SCB_CCSIDR_WA_Msk (7UL << SCB_CCSIDR_WA_Pos) /*!< SCB CCSIDR: WA Mask */ -#define SCB_CCSIDR_NUMSETS_Pos 13 /*!< SCB CCSIDR: NumSets Position */ -#define SCB_CCSIDR_NUMSETS_Msk (0x7FFFUL << SCB_CCSIDR_NUMSETS_Pos) /*!< SCB CCSIDR: NumSets Mask */ +#define SCB_CCSIDR_NUMSETS_Pos 13 /*!< SCB CCSIDR: NumSets Position */ +#define SCB_CCSIDR_NUMSETS_Msk (0x7FFFUL << SCB_CCSIDR_NUMSETS_Pos) /*!< SCB CCSIDR: NumSets Mask */ -#define SCB_CCSIDR_ASSOCIATIVITY_Pos 3 /*!< SCB CCSIDR: Associativity Position */ -#define SCB_CCSIDR_ASSOCIATIVITY_Msk (0x3FFUL << SCB_CCSIDR_ASSOCIATIVITY_Pos) /*!< SCB CCSIDR: Associativity Mask */ +#define SCB_CCSIDR_ASSOCIATIVITY_Pos 3 /*!< SCB CCSIDR: Associativity Position */ +#define SCB_CCSIDR_ASSOCIATIVITY_Msk (0x3FFUL << SCB_CCSIDR_ASSOCIATIVITY_Pos) /*!< SCB CCSIDR: Associativity Mask */ -#define SCB_CCSIDR_LINESIZE_Pos 0 /*!< SCB CCSIDR: LineSize Position */ -#define SCB_CCSIDR_LINESIZE_Msk (7UL << SCB_CCSIDR_LINESIZE_Pos) /*!< SCB CCSIDR: LineSize Mask */ +#define SCB_CCSIDR_LINESIZE_Pos 0 /*!< SCB CCSIDR: LineSize Position */ +#define SCB_CCSIDR_LINESIZE_Msk (7UL << SCB_CCSIDR_LINESIZE_Pos) /*!< SCB CCSIDR: LineSize Mask */ /* Cache Size Selection Register */ -#define SCB_CSSELR_LEVEL_Pos 0 /*!< SCB CSSELR: Level Position */ -#define SCB_CSSELR_LEVEL_Msk (1UL << SCB_CSSELR_LEVEL_Pos) /*!< SCB CSSELR: Level Mask */ +#define SCB_CSSELR_LEVEL_Pos 0 /*!< SCB CSSELR: Level Position */ +#define SCB_CSSELR_LEVEL_Msk (1UL << SCB_CSSELR_LEVEL_Pos) /*!< SCB CSSELR: Level Mask */ -#define SCB_CSSELR_IND_Pos 0 /*!< SCB CSSELR: InD Position */ -#define SCB_CSSELR_IND_Msk (1UL << SCB_CSSELR_IND_Pos) /*!< SCB CSSELR: InD Mask */ +#define SCB_CSSELR_IND_Pos 0 /*!< SCB CSSELR: InD Position */ +#define SCB_CSSELR_IND_Msk (1UL << SCB_CSSELR_IND_Pos) /*!< SCB CSSELR: InD Mask */ /* SCB Software Triggered Interrupt Register */ -#define SCB_STIR_INTID_Pos 0 /*!< SCB STIR: INTID Position */ -#define SCB_STIR_INTID_Msk (0x1FFUL << SCB_STIR_INTID_Pos) /*!< SCB STIR: INTID Mask */ +#define SCB_STIR_INTID_Pos 0 /*!< SCB STIR: INTID Position */ +#define SCB_STIR_INTID_Msk (0x1FFUL << SCB_STIR_INTID_Pos) /*!< SCB STIR: INTID Mask */ /* Instruction Tightly-Coupled Memory Control Register*/ -#define SCB_ITCMCR_SZ_Pos 3 /*!< SCB ITCMCR: SZ Position */ -#define SCB_ITCMCR_SZ_Msk (0xFUL << SCB_ITCMCR_SZ_Pos) /*!< SCB ITCMCR: SZ Mask */ +#define SCB_ITCMCR_SZ_Pos 3 /*!< SCB ITCMCR: SZ Position */ +#define SCB_ITCMCR_SZ_Msk (0xFUL << SCB_ITCMCR_SZ_Pos) /*!< SCB ITCMCR: SZ Mask */ -#define SCB_ITCMCR_RETEN_Pos 2 /*!< SCB ITCMCR: RETEN Position */ -#define SCB_ITCMCR_RETEN_Msk (1FFUL << SCB_ITCMCR_RETEN_Pos) /*!< SCB ITCMCR: RETEN Mask */ +#define SCB_ITCMCR_RETEN_Pos 2 /*!< SCB ITCMCR: RETEN Position */ +#define SCB_ITCMCR_RETEN_Msk (1FFUL << SCB_ITCMCR_RETEN_Pos) /*!< SCB ITCMCR: RETEN Mask */ -#define SCB_ITCMCR_RMW_Pos 1 /*!< SCB ITCMCR: RMW Position */ -#define SCB_ITCMCR_RMW_Msk (1FFUL << SCB_ITCMCR_RMW_Pos) /*!< SCB ITCMCR: RMW Mask */ +#define SCB_ITCMCR_RMW_Pos 1 /*!< SCB ITCMCR: RMW Position */ +#define SCB_ITCMCR_RMW_Msk (1FFUL << SCB_ITCMCR_RMW_Pos) /*!< SCB ITCMCR: RMW Mask */ -#define SCB_ITCMCR_EN_Pos 0 /*!< SCB ITCMCR: EN Position */ -#define SCB_ITCMCR_EN_Msk (1FFUL << SCB_ITCMCR_EN_Pos) /*!< SCB ITCMCR: EN Mask */ +#define SCB_ITCMCR_EN_Pos 0 /*!< SCB ITCMCR: EN Position */ +#define SCB_ITCMCR_EN_Msk (1FFUL << SCB_ITCMCR_EN_Pos) /*!< SCB ITCMCR: EN Mask */ /* Data Tightly-Coupled Memory Control Registers */ -#define SCB_DTCMCR_SZ_Pos 3 /*!< SCB DTCMCR: SZ Position */ -#define SCB_DTCMCR_SZ_Msk (0xFUL << SCB_DTCMCR_SZ_Pos) /*!< SCB DTCMCR: SZ Mask */ +#define SCB_DTCMCR_SZ_Pos 3 /*!< SCB DTCMCR: SZ Position */ +#define SCB_DTCMCR_SZ_Msk (0xFUL << SCB_DTCMCR_SZ_Pos) /*!< SCB DTCMCR: SZ Mask */ -#define SCB_DTCMCR_RETEN_Pos 2 /*!< SCB DTCMCR: RETEN Position */ -#define SCB_DTCMCR_RETEN_Msk (1UL << SCB_DTCMCR_RETEN_Pos) /*!< SCB DTCMCR: RETEN Mask */ +#define SCB_DTCMCR_RETEN_Pos 2 /*!< SCB DTCMCR: RETEN Position */ +#define SCB_DTCMCR_RETEN_Msk (1UL << SCB_DTCMCR_RETEN_Pos) /*!< SCB DTCMCR: RETEN Mask */ -#define SCB_DTCMCR_RMW_Pos 1 /*!< SCB DTCMCR: RMW Position */ -#define SCB_DTCMCR_RMW_Msk (1UL << SCB_DTCMCR_RMW_Pos) /*!< SCB DTCMCR: RMW Mask */ +#define SCB_DTCMCR_RMW_Pos 1 /*!< SCB DTCMCR: RMW Position */ +#define SCB_DTCMCR_RMW_Msk (1UL << SCB_DTCMCR_RMW_Pos) /*!< SCB DTCMCR: RMW Mask */ -#define SCB_DTCMCR_EN_Pos 0 /*!< SCB DTCMCR: EN Position */ -#define SCB_DTCMCR_EN_Msk (1UL << SCB_DTCMCR_EN_Pos) /*!< SCB DTCMCR: EN Mask */ +#define SCB_DTCMCR_EN_Pos 0 /*!< SCB DTCMCR: EN Position */ +#define SCB_DTCMCR_EN_Msk (1UL << SCB_DTCMCR_EN_Pos) /*!< SCB DTCMCR: EN Mask */ /* AHBP Control Register */ -#define SCB_AHBPCR_SZ_Pos 1 /*!< SCB AHBPCR: SZ Position */ -#define SCB_AHBPCR_SZ_Msk (7UL << SCB_AHBPCR_SZ_Pos) /*!< SCB AHBPCR: SZ Mask */ +#define SCB_AHBPCR_SZ_Pos 1 /*!< SCB AHBPCR: SZ Position */ +#define SCB_AHBPCR_SZ_Msk (7UL << SCB_AHBPCR_SZ_Pos) /*!< SCB AHBPCR: SZ Mask */ -#define SCB_AHBPCR_EN_Pos 0 /*!< SCB AHBPCR: EN Position */ -#define SCB_AHBPCR_EN_Msk (1UL << SCB_AHBPCR_EN_Pos) /*!< SCB AHBPCR: EN Mask */ +#define SCB_AHBPCR_EN_Pos 0 /*!< SCB AHBPCR: EN Position */ +#define SCB_AHBPCR_EN_Msk (1UL << SCB_AHBPCR_EN_Pos) /*!< SCB AHBPCR: EN Mask */ /* L1 Cache Control Register */ -#define SCB_CACR_FORCEWT_Pos 2 /*!< SCB CACR: FORCEWT Position */ -#define SCB_CACR_FORCEWT_Msk (1UL << SCB_CACR_FORCEWT_Pos) /*!< SCB CACR: FORCEWT Mask */ +#define SCB_CACR_FORCEWT_Pos 2 /*!< SCB CACR: FORCEWT Position */ +#define SCB_CACR_FORCEWT_Msk (1UL << SCB_CACR_FORCEWT_Pos) /*!< SCB CACR: FORCEWT Mask */ -#define SCB_CACR_ECCEN_Pos 1 /*!< SCB CACR: ECCEN Position */ -#define SCB_CACR_ECCEN_Msk (1UL << SCB_CACR_ECCEN_Pos) /*!< SCB CACR: ECCEN Mask */ +#define SCB_CACR_ECCEN_Pos 1 /*!< SCB CACR: ECCEN Position */ +#define SCB_CACR_ECCEN_Msk (1UL << SCB_CACR_ECCEN_Pos) /*!< SCB CACR: ECCEN Mask */ -#define SCB_CACR_SIWT_Pos 0 /*!< SCB CACR: SIWT Position */ -#define SCB_CACR_SIWT_Msk (1UL << SCB_CACR_SIWT_Pos) /*!< SCB CACR: SIWT Mask */ +#define SCB_CACR_SIWT_Pos 0 /*!< SCB CACR: SIWT Position */ +#define SCB_CACR_SIWT_Msk (1UL << SCB_CACR_SIWT_Pos) /*!< SCB CACR: SIWT Mask */ /* AHBS control register */ -#define SCB_AHBSCR_INITCOUNT_Pos 11 /*!< SCB AHBSCR: INITCOUNT Position */ -#define SCB_AHBSCR_INITCOUNT_Msk (0x1FUL << SCB_AHBPCR_INITCOUNT_Pos) /*!< SCB AHBSCR: INITCOUNT Mask */ +#define SCB_AHBSCR_INITCOUNT_Pos 11 /*!< SCB AHBSCR: INITCOUNT Position */ +#define SCB_AHBSCR_INITCOUNT_Msk (0x1FUL << SCB_AHBPCR_INITCOUNT_Pos) /*!< SCB AHBSCR: INITCOUNT Mask */ -#define SCB_AHBSCR_TPRI_Pos 2 /*!< SCB AHBSCR: TPRI Position */ -#define SCB_AHBSCR_TPRI_Msk (0x1FFUL << SCB_AHBPCR_TPRI_Pos) /*!< SCB AHBSCR: TPRI Mask */ +#define SCB_AHBSCR_TPRI_Pos 2 /*!< SCB AHBSCR: TPRI Position */ +#define SCB_AHBSCR_TPRI_Msk (0x1FFUL << SCB_AHBPCR_TPRI_Pos) /*!< SCB AHBSCR: TPRI Mask */ -#define SCB_AHBSCR_CTL_Pos 0 /*!< SCB AHBSCR: CTL Position*/ -#define SCB_AHBSCR_CTL_Msk (3UL << SCB_AHBPCR_CTL_Pos) /*!< SCB AHBSCR: CTL Mask */ +#define SCB_AHBSCR_CTL_Pos 0 /*!< SCB AHBSCR: CTL Position*/ +#define SCB_AHBSCR_CTL_Msk (3UL << SCB_AHBPCR_CTL_Pos) /*!< SCB AHBSCR: CTL Mask */ /* Auxiliary Bus Fault Status Register */ -#define SCB_ABFSR_AXIMTYPE_Pos 8 /*!< SCB ABFSR: AXIMTYPE Position*/ -#define SCB_ABFSR_AXIMTYPE_Msk (3UL << SCB_ABFSR_AXIMTYPE_Pos) /*!< SCB ABFSR: AXIMTYPE Mask */ - -#define SCB_ABFSR_EPPB_Pos 4 /*!< SCB ABFSR: EPPB Position*/ -#define SCB_ABFSR_EPPB_Msk (1UL << SCB_ABFSR_EPPB_Pos) /*!< SCB ABFSR: EPPB Mask */ +#define SCB_ABFSR_AXIMTYPE_Pos 8 /*!< SCB ABFSR: AXIMTYPE Position*/ +#define SCB_ABFSR_AXIMTYPE_Msk (3UL << SCB_ABFSR_AXIMTYPE_Pos) /*!< SCB ABFSR: AXIMTYPE Mask */ -#define SCB_ABFSR_AXIM_Pos 3 /*!< SCB ABFSR: AXIM Position*/ -#define SCB_ABFSR_AXIM_Msk (1UL << SCB_ABFSR_AXIM_Pos) /*!< SCB ABFSR: AXIM Mask */ +#define SCB_ABFSR_EPPB_Pos 4 /*!< SCB ABFSR: EPPB Position*/ +#define SCB_ABFSR_EPPB_Msk (1UL << SCB_ABFSR_EPPB_Pos) /*!< SCB ABFSR: EPPB Mask */ -#define SCB_ABFSR_AHBP_Pos 2 /*!< SCB ABFSR: AHBP Position*/ -#define SCB_ABFSR_AHBP_Msk (1UL << SCB_ABFSR_AHBP_Pos) /*!< SCB ABFSR: AHBP Mask */ +#define SCB_ABFSR_AXIM_Pos 3 /*!< SCB ABFSR: AXIM Position*/ +#define SCB_ABFSR_AXIM_Msk (1UL << SCB_ABFSR_AXIM_Pos) /*!< SCB ABFSR: AXIM Mask */ -#define SCB_ABFSR_DTCM_Pos 1 /*!< SCB ABFSR: DTCM Position*/ -#define SCB_ABFSR_DTCM_Msk (1UL << SCB_ABFSR_DTCM_Pos) /*!< SCB ABFSR: DTCM Mask */ +#define SCB_ABFSR_AHBP_Pos 2 /*!< SCB ABFSR: AHBP Position*/ +#define SCB_ABFSR_AHBP_Msk (1UL << SCB_ABFSR_AHBP_Pos) /*!< SCB ABFSR: AHBP Mask */ -#define SCB_ABFSR_ITCM_Pos 0 /*!< SCB ABFSR: ITCM Position*/ -#define SCB_ABFSR_ITCM_Msk (1UL << SCB_ABFSR_ITCM_Pos) /*!< SCB ABFSR: ITCM Mask */ +#define SCB_ABFSR_DTCM_Pos 1 /*!< SCB ABFSR: DTCM Position*/ +#define SCB_ABFSR_DTCM_Msk (1UL << SCB_ABFSR_DTCM_Pos) /*!< SCB ABFSR: DTCM Mask */ -/*@} end of group CMSIS_SCB */ +#define SCB_ABFSR_ITCM_Pos 0 /*!< SCB ABFSR: ITCM Position*/ +#define SCB_ABFSR_ITCM_Msk (1UL << SCB_ABFSR_ITCM_Pos) /*!< SCB ABFSR: ITCM Mask */ + /*@} end of group CMSIS_SCB */ -/** \ingroup CMSIS_core_register + /** \ingroup CMSIS_core_register \defgroup CMSIS_SCnSCB System Controls not in SCB (SCnSCB) \brief Type definitions for the System Control and ID Register not in the SCB @{ */ -/** \brief Structure type to access the System Control and ID Register not in the SCB. + /** \brief Structure type to access the System Control and ID Register not in the SCB. */ -typedef struct -{ - uint32_t RESERVED0[1]; - __I uint32_t ICTR; /*!< Offset: 0x004 (R/ ) Interrupt Controller Type Register */ - __IO uint32_t ACTLR; /*!< Offset: 0x008 (R/W) Auxiliary Control Register */ -} SCnSCB_Type; + typedef struct + { + uint32_t RESERVED0[1]; + __I uint32_t ICTR; /*!< Offset: 0x004 (R/ ) Interrupt Controller Type Register */ + __IO uint32_t ACTLR; /*!< Offset: 0x008 (R/W) Auxiliary Control Register */ + } SCnSCB_Type; /* Interrupt Controller Type Register Definitions */ -#define SCnSCB_ICTR_INTLINESNUM_Pos 0 /*!< ICTR: INTLINESNUM Position */ -#define SCnSCB_ICTR_INTLINESNUM_Msk (0xFUL << SCnSCB_ICTR_INTLINESNUM_Pos) /*!< ICTR: INTLINESNUM Mask */ +#define SCnSCB_ICTR_INTLINESNUM_Pos 0 /*!< ICTR: INTLINESNUM Position */ +#define SCnSCB_ICTR_INTLINESNUM_Msk (0xFUL << SCnSCB_ICTR_INTLINESNUM_Pos) /*!< ICTR: INTLINESNUM Mask */ /* Auxiliary Control Register Definitions */ -#define SCnSCB_ACTLR_DISITMATBFLUSH_Pos 12 /*!< ACTLR: DISITMATBFLUSH Position */ -#define SCnSCB_ACTLR_DISITMATBFLUSH_Msk (1UL << SCnSCB_ACTLR_DISITMATBFLUSH_Pos) /*!< ACTLR: DISITMATBFLUSH Mask */ +#define SCnSCB_ACTLR_DISITMATBFLUSH_Pos 12 /*!< ACTLR: DISITMATBFLUSH Position */ +#define SCnSCB_ACTLR_DISITMATBFLUSH_Msk (1UL << SCnSCB_ACTLR_DISITMATBFLUSH_Pos) /*!< ACTLR: DISITMATBFLUSH Mask */ -#define SCnSCB_ACTLR_DISRAMODE_Pos 11 /*!< ACTLR: DISRAMODE Position */ -#define SCnSCB_ACTLR_DISRAMODE_Msk (1UL << SCnSCB_ACTLR_DISRAMODE_Pos) /*!< ACTLR: DISRAMODE Mask */ +#define SCnSCB_ACTLR_DISRAMODE_Pos 11 /*!< ACTLR: DISRAMODE Position */ +#define SCnSCB_ACTLR_DISRAMODE_Msk (1UL << SCnSCB_ACTLR_DISRAMODE_Pos) /*!< ACTLR: DISRAMODE Mask */ -#define SCnSCB_ACTLR_FPEXCODIS_Pos 10 /*!< ACTLR: FPEXCODIS Position */ -#define SCnSCB_ACTLR_FPEXCODIS_Msk (1UL << SCnSCB_ACTLR_FPEXCODIS_Pos) /*!< ACTLR: FPEXCODIS Mask */ +#define SCnSCB_ACTLR_FPEXCODIS_Pos 10 /*!< ACTLR: FPEXCODIS Position */ +#define SCnSCB_ACTLR_FPEXCODIS_Msk (1UL << SCnSCB_ACTLR_FPEXCODIS_Pos) /*!< ACTLR: FPEXCODIS Mask */ -#define SCnSCB_ACTLR_DISFOLD_Pos 2 /*!< ACTLR: DISFOLD Position */ -#define SCnSCB_ACTLR_DISFOLD_Msk (1UL << SCnSCB_ACTLR_DISFOLD_Pos) /*!< ACTLR: DISFOLD Mask */ +#define SCnSCB_ACTLR_DISFOLD_Pos 2 /*!< ACTLR: DISFOLD Position */ +#define SCnSCB_ACTLR_DISFOLD_Msk (1UL << SCnSCB_ACTLR_DISFOLD_Pos) /*!< ACTLR: DISFOLD Mask */ -#define SCnSCB_ACTLR_DISMCYCINT_Pos 0 /*!< ACTLR: DISMCYCINT Position */ -#define SCnSCB_ACTLR_DISMCYCINT_Msk (1UL << SCnSCB_ACTLR_DISMCYCINT_Pos) /*!< ACTLR: DISMCYCINT Mask */ +#define SCnSCB_ACTLR_DISMCYCINT_Pos 0 /*!< ACTLR: DISMCYCINT Position */ +#define SCnSCB_ACTLR_DISMCYCINT_Msk (1UL << SCnSCB_ACTLR_DISMCYCINT_Pos) /*!< ACTLR: DISMCYCINT Mask */ -/*@} end of group CMSIS_SCnotSCB */ + /*@} end of group CMSIS_SCnotSCB */ - -/** \ingroup CMSIS_core_register + /** \ingroup CMSIS_core_register \defgroup CMSIS_SysTick System Tick Timer (SysTick) \brief Type definitions for the System Timer Registers. @{ */ -/** \brief Structure type to access the System Timer (SysTick). + /** \brief Structure type to access the System Timer (SysTick). */ -typedef struct -{ - __IO uint32_t CTRL; /*!< Offset: 0x000 (R/W) SysTick Control and Status Register */ - __IO uint32_t LOAD; /*!< Offset: 0x004 (R/W) SysTick Reload Value Register */ - __IO uint32_t VAL; /*!< Offset: 0x008 (R/W) SysTick Current Value Register */ - __I uint32_t CALIB; /*!< Offset: 0x00C (R/ ) SysTick Calibration Register */ -} SysTick_Type; + typedef struct + { + __IO uint32_t CTRL; /*!< Offset: 0x000 (R/W) SysTick Control and Status Register */ + __IO uint32_t LOAD; /*!< Offset: 0x004 (R/W) SysTick Reload Value Register */ + __IO uint32_t VAL; /*!< Offset: 0x008 (R/W) SysTick Current Value Register */ + __I uint32_t CALIB; /*!< Offset: 0x00C (R/ ) SysTick Calibration Register */ + } SysTick_Type; /* SysTick Control / Status Register Definitions */ -#define SysTick_CTRL_COUNTFLAG_Pos 16 /*!< SysTick CTRL: COUNTFLAG Position */ -#define SysTick_CTRL_COUNTFLAG_Msk (1UL << SysTick_CTRL_COUNTFLAG_Pos) /*!< SysTick CTRL: COUNTFLAG Mask */ +#define SysTick_CTRL_COUNTFLAG_Pos 16 /*!< SysTick CTRL: COUNTFLAG Position */ +#define SysTick_CTRL_COUNTFLAG_Msk (1UL << SysTick_CTRL_COUNTFLAG_Pos) /*!< SysTick CTRL: COUNTFLAG Mask */ -#define SysTick_CTRL_CLKSOURCE_Pos 2 /*!< SysTick CTRL: CLKSOURCE Position */ -#define SysTick_CTRL_CLKSOURCE_Msk (1UL << SysTick_CTRL_CLKSOURCE_Pos) /*!< SysTick CTRL: CLKSOURCE Mask */ +#define SysTick_CTRL_CLKSOURCE_Pos 2 /*!< SysTick CTRL: CLKSOURCE Position */ +#define SysTick_CTRL_CLKSOURCE_Msk (1UL << SysTick_CTRL_CLKSOURCE_Pos) /*!< SysTick CTRL: CLKSOURCE Mask */ -#define SysTick_CTRL_TICKINT_Pos 1 /*!< SysTick CTRL: TICKINT Position */ -#define SysTick_CTRL_TICKINT_Msk (1UL << SysTick_CTRL_TICKINT_Pos) /*!< SysTick CTRL: TICKINT Mask */ +#define SysTick_CTRL_TICKINT_Pos 1 /*!< SysTick CTRL: TICKINT Position */ +#define SysTick_CTRL_TICKINT_Msk (1UL << SysTick_CTRL_TICKINT_Pos) /*!< SysTick CTRL: TICKINT Mask */ -#define SysTick_CTRL_ENABLE_Pos 0 /*!< SysTick CTRL: ENABLE Position */ -#define SysTick_CTRL_ENABLE_Msk (1UL << SysTick_CTRL_ENABLE_Pos) /*!< SysTick CTRL: ENABLE Mask */ +#define SysTick_CTRL_ENABLE_Pos 0 /*!< SysTick CTRL: ENABLE Position */ +#define SysTick_CTRL_ENABLE_Msk (1UL << SysTick_CTRL_ENABLE_Pos) /*!< SysTick CTRL: ENABLE Mask */ /* SysTick Reload Register Definitions */ -#define SysTick_LOAD_RELOAD_Pos 0 /*!< SysTick LOAD: RELOAD Position */ -#define SysTick_LOAD_RELOAD_Msk (0xFFFFFFUL << SysTick_LOAD_RELOAD_Pos) /*!< SysTick LOAD: RELOAD Mask */ +#define SysTick_LOAD_RELOAD_Pos 0 /*!< SysTick LOAD: RELOAD Position */ +#define SysTick_LOAD_RELOAD_Msk (0xFFFFFFUL << SysTick_LOAD_RELOAD_Pos) /*!< SysTick LOAD: RELOAD Mask */ /* SysTick Current Register Definitions */ -#define SysTick_VAL_CURRENT_Pos 0 /*!< SysTick VAL: CURRENT Position */ -#define SysTick_VAL_CURRENT_Msk (0xFFFFFFUL << SysTick_VAL_CURRENT_Pos) /*!< SysTick VAL: CURRENT Mask */ +#define SysTick_VAL_CURRENT_Pos 0 /*!< SysTick VAL: CURRENT Position */ +#define SysTick_VAL_CURRENT_Msk (0xFFFFFFUL << SysTick_VAL_CURRENT_Pos) /*!< SysTick VAL: CURRENT Mask */ /* SysTick Calibration Register Definitions */ -#define SysTick_CALIB_NOREF_Pos 31 /*!< SysTick CALIB: NOREF Position */ -#define SysTick_CALIB_NOREF_Msk (1UL << SysTick_CALIB_NOREF_Pos) /*!< SysTick CALIB: NOREF Mask */ - -#define SysTick_CALIB_SKEW_Pos 30 /*!< SysTick CALIB: SKEW Position */ -#define SysTick_CALIB_SKEW_Msk (1UL << SysTick_CALIB_SKEW_Pos) /*!< SysTick CALIB: SKEW Mask */ +#define SysTick_CALIB_NOREF_Pos 31 /*!< SysTick CALIB: NOREF Position */ +#define SysTick_CALIB_NOREF_Msk (1UL << SysTick_CALIB_NOREF_Pos) /*!< SysTick CALIB: NOREF Mask */ -#define SysTick_CALIB_TENMS_Pos 0 /*!< SysTick CALIB: TENMS Position */ -#define SysTick_CALIB_TENMS_Msk (0xFFFFFFUL << SysTick_CALIB_TENMS_Pos) /*!< SysTick CALIB: TENMS Mask */ +#define SysTick_CALIB_SKEW_Pos 30 /*!< SysTick CALIB: SKEW Position */ +#define SysTick_CALIB_SKEW_Msk (1UL << SysTick_CALIB_SKEW_Pos) /*!< SysTick CALIB: SKEW Mask */ -/*@} end of group CMSIS_SysTick */ +#define SysTick_CALIB_TENMS_Pos 0 /*!< SysTick CALIB: TENMS Position */ +#define SysTick_CALIB_TENMS_Msk (0xFFFFFFUL << SysTick_CALIB_TENMS_Pos) /*!< SysTick CALIB: TENMS Mask */ + /*@} end of group CMSIS_SysTick */ -/** \ingroup CMSIS_core_register + /** \ingroup CMSIS_core_register \defgroup CMSIS_ITM Instrumentation Trace Macrocell (ITM) \brief Type definitions for the Instrumentation Trace Macrocell (ITM) @{ */ -/** \brief Structure type to access the Instrumentation Trace Macrocell Register (ITM). + /** \brief Structure type to access the Instrumentation Trace Macrocell Register (ITM). */ -typedef struct -{ - __O union - { - __O uint8_t u8; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 8-bit */ - __O uint16_t u16; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 16-bit */ - __O uint32_t u32; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 32-bit */ - } PORT [32]; /*!< Offset: 0x000 ( /W) ITM Stimulus Port Registers */ - uint32_t RESERVED0[864]; - __IO uint32_t TER; /*!< Offset: 0xE00 (R/W) ITM Trace Enable Register */ - uint32_t RESERVED1[15]; - __IO uint32_t TPR; /*!< Offset: 0xE40 (R/W) ITM Trace Privilege Register */ - uint32_t RESERVED2[15]; - __IO uint32_t TCR; /*!< Offset: 0xE80 (R/W) ITM Trace Control Register */ - uint32_t RESERVED3[29]; - __O uint32_t IWR; /*!< Offset: 0xEF8 ( /W) ITM Integration Write Register */ - __I uint32_t IRR; /*!< Offset: 0xEFC (R/ ) ITM Integration Read Register */ - __IO uint32_t IMCR; /*!< Offset: 0xF00 (R/W) ITM Integration Mode Control Register */ - uint32_t RESERVED4[43]; - __O uint32_t LAR; /*!< Offset: 0xFB0 ( /W) ITM Lock Access Register */ - __I uint32_t LSR; /*!< Offset: 0xFB4 (R/ ) ITM Lock Status Register */ - uint32_t RESERVED5[6]; - __I uint32_t PID4; /*!< Offset: 0xFD0 (R/ ) ITM Peripheral Identification Register #4 */ - __I uint32_t PID5; /*!< Offset: 0xFD4 (R/ ) ITM Peripheral Identification Register #5 */ - __I uint32_t PID6; /*!< Offset: 0xFD8 (R/ ) ITM Peripheral Identification Register #6 */ - __I uint32_t PID7; /*!< Offset: 0xFDC (R/ ) ITM Peripheral Identification Register #7 */ - __I uint32_t PID0; /*!< Offset: 0xFE0 (R/ ) ITM Peripheral Identification Register #0 */ - __I uint32_t PID1; /*!< Offset: 0xFE4 (R/ ) ITM Peripheral Identification Register #1 */ - __I uint32_t PID2; /*!< Offset: 0xFE8 (R/ ) ITM Peripheral Identification Register #2 */ - __I uint32_t PID3; /*!< Offset: 0xFEC (R/ ) ITM Peripheral Identification Register #3 */ - __I uint32_t CID0; /*!< Offset: 0xFF0 (R/ ) ITM Component Identification Register #0 */ - __I uint32_t CID1; /*!< Offset: 0xFF4 (R/ ) ITM Component Identification Register #1 */ - __I uint32_t CID2; /*!< Offset: 0xFF8 (R/ ) ITM Component Identification Register #2 */ - __I uint32_t CID3; /*!< Offset: 0xFFC (R/ ) ITM Component Identification Register #3 */ -} ITM_Type; + typedef struct + { + __O union + { + __O uint8_t u8; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 8-bit */ + __O uint16_t u16; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 16-bit */ + __O uint32_t u32; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 32-bit */ + } PORT[32]; /*!< Offset: 0x000 ( /W) ITM Stimulus Port Registers */ + uint32_t RESERVED0[864]; + __IO uint32_t TER; /*!< Offset: 0xE00 (R/W) ITM Trace Enable Register */ + uint32_t RESERVED1[15]; + __IO uint32_t TPR; /*!< Offset: 0xE40 (R/W) ITM Trace Privilege Register */ + uint32_t RESERVED2[15]; + __IO uint32_t TCR; /*!< Offset: 0xE80 (R/W) ITM Trace Control Register */ + uint32_t RESERVED3[29]; + __O uint32_t IWR; /*!< Offset: 0xEF8 ( /W) ITM Integration Write Register */ + __I uint32_t IRR; /*!< Offset: 0xEFC (R/ ) ITM Integration Read Register */ + __IO uint32_t IMCR; /*!< Offset: 0xF00 (R/W) ITM Integration Mode Control Register */ + uint32_t RESERVED4[43]; + __O uint32_t LAR; /*!< Offset: 0xFB0 ( /W) ITM Lock Access Register */ + __I uint32_t LSR; /*!< Offset: 0xFB4 (R/ ) ITM Lock Status Register */ + uint32_t RESERVED5[6]; + __I uint32_t PID4; /*!< Offset: 0xFD0 (R/ ) ITM Peripheral Identification Register #4 */ + __I uint32_t PID5; /*!< Offset: 0xFD4 (R/ ) ITM Peripheral Identification Register #5 */ + __I uint32_t PID6; /*!< Offset: 0xFD8 (R/ ) ITM Peripheral Identification Register #6 */ + __I uint32_t PID7; /*!< Offset: 0xFDC (R/ ) ITM Peripheral Identification Register #7 */ + __I uint32_t PID0; /*!< Offset: 0xFE0 (R/ ) ITM Peripheral Identification Register #0 */ + __I uint32_t PID1; /*!< Offset: 0xFE4 (R/ ) ITM Peripheral Identification Register #1 */ + __I uint32_t PID2; /*!< Offset: 0xFE8 (R/ ) ITM Peripheral Identification Register #2 */ + __I uint32_t PID3; /*!< Offset: 0xFEC (R/ ) ITM Peripheral Identification Register #3 */ + __I uint32_t CID0; /*!< Offset: 0xFF0 (R/ ) ITM Component Identification Register #0 */ + __I uint32_t CID1; /*!< Offset: 0xFF4 (R/ ) ITM Component Identification Register #1 */ + __I uint32_t CID2; /*!< Offset: 0xFF8 (R/ ) ITM Component Identification Register #2 */ + __I uint32_t CID3; /*!< Offset: 0xFFC (R/ ) ITM Component Identification Register #3 */ + } ITM_Type; /* ITM Trace Privilege Register Definitions */ -#define ITM_TPR_PRIVMASK_Pos 0 /*!< ITM TPR: PRIVMASK Position */ -#define ITM_TPR_PRIVMASK_Msk (0xFUL << ITM_TPR_PRIVMASK_Pos) /*!< ITM TPR: PRIVMASK Mask */ +#define ITM_TPR_PRIVMASK_Pos 0 /*!< ITM TPR: PRIVMASK Position */ +#define ITM_TPR_PRIVMASK_Msk (0xFUL << ITM_TPR_PRIVMASK_Pos) /*!< ITM TPR: PRIVMASK Mask */ /* ITM Trace Control Register Definitions */ -#define ITM_TCR_BUSY_Pos 23 /*!< ITM TCR: BUSY Position */ -#define ITM_TCR_BUSY_Msk (1UL << ITM_TCR_BUSY_Pos) /*!< ITM TCR: BUSY Mask */ +#define ITM_TCR_BUSY_Pos 23 /*!< ITM TCR: BUSY Position */ +#define ITM_TCR_BUSY_Msk (1UL << ITM_TCR_BUSY_Pos) /*!< ITM TCR: BUSY Mask */ -#define ITM_TCR_TraceBusID_Pos 16 /*!< ITM TCR: ATBID Position */ -#define ITM_TCR_TraceBusID_Msk (0x7FUL << ITM_TCR_TraceBusID_Pos) /*!< ITM TCR: ATBID Mask */ +#define ITM_TCR_TraceBusID_Pos 16 /*!< ITM TCR: ATBID Position */ +#define ITM_TCR_TraceBusID_Msk (0x7FUL << ITM_TCR_TraceBusID_Pos) /*!< ITM TCR: ATBID Mask */ -#define ITM_TCR_GTSFREQ_Pos 10 /*!< ITM TCR: Global timestamp frequency Position */ -#define ITM_TCR_GTSFREQ_Msk (3UL << ITM_TCR_GTSFREQ_Pos) /*!< ITM TCR: Global timestamp frequency Mask */ +#define ITM_TCR_GTSFREQ_Pos 10 /*!< ITM TCR: Global timestamp frequency Position */ +#define ITM_TCR_GTSFREQ_Msk (3UL << ITM_TCR_GTSFREQ_Pos) /*!< ITM TCR: Global timestamp frequency Mask */ -#define ITM_TCR_TSPrescale_Pos 8 /*!< ITM TCR: TSPrescale Position */ -#define ITM_TCR_TSPrescale_Msk (3UL << ITM_TCR_TSPrescale_Pos) /*!< ITM TCR: TSPrescale Mask */ +#define ITM_TCR_TSPrescale_Pos 8 /*!< ITM TCR: TSPrescale Position */ +#define ITM_TCR_TSPrescale_Msk (3UL << ITM_TCR_TSPrescale_Pos) /*!< ITM TCR: TSPrescale Mask */ -#define ITM_TCR_SWOENA_Pos 4 /*!< ITM TCR: SWOENA Position */ -#define ITM_TCR_SWOENA_Msk (1UL << ITM_TCR_SWOENA_Pos) /*!< ITM TCR: SWOENA Mask */ +#define ITM_TCR_SWOENA_Pos 4 /*!< ITM TCR: SWOENA Position */ +#define ITM_TCR_SWOENA_Msk (1UL << ITM_TCR_SWOENA_Pos) /*!< ITM TCR: SWOENA Mask */ -#define ITM_TCR_DWTENA_Pos 3 /*!< ITM TCR: DWTENA Position */ -#define ITM_TCR_DWTENA_Msk (1UL << ITM_TCR_DWTENA_Pos) /*!< ITM TCR: DWTENA Mask */ +#define ITM_TCR_DWTENA_Pos 3 /*!< ITM TCR: DWTENA Position */ +#define ITM_TCR_DWTENA_Msk (1UL << ITM_TCR_DWTENA_Pos) /*!< ITM TCR: DWTENA Mask */ -#define ITM_TCR_SYNCENA_Pos 2 /*!< ITM TCR: SYNCENA Position */ -#define ITM_TCR_SYNCENA_Msk (1UL << ITM_TCR_SYNCENA_Pos) /*!< ITM TCR: SYNCENA Mask */ +#define ITM_TCR_SYNCENA_Pos 2 /*!< ITM TCR: SYNCENA Position */ +#define ITM_TCR_SYNCENA_Msk (1UL << ITM_TCR_SYNCENA_Pos) /*!< ITM TCR: SYNCENA Mask */ -#define ITM_TCR_TSENA_Pos 1 /*!< ITM TCR: TSENA Position */ -#define ITM_TCR_TSENA_Msk (1UL << ITM_TCR_TSENA_Pos) /*!< ITM TCR: TSENA Mask */ +#define ITM_TCR_TSENA_Pos 1 /*!< ITM TCR: TSENA Position */ +#define ITM_TCR_TSENA_Msk (1UL << ITM_TCR_TSENA_Pos) /*!< ITM TCR: TSENA Mask */ -#define ITM_TCR_ITMENA_Pos 0 /*!< ITM TCR: ITM Enable bit Position */ -#define ITM_TCR_ITMENA_Msk (1UL << ITM_TCR_ITMENA_Pos) /*!< ITM TCR: ITM Enable bit Mask */ +#define ITM_TCR_ITMENA_Pos 0 /*!< ITM TCR: ITM Enable bit Position */ +#define ITM_TCR_ITMENA_Msk (1UL << ITM_TCR_ITMENA_Pos) /*!< ITM TCR: ITM Enable bit Mask */ /* ITM Integration Write Register Definitions */ -#define ITM_IWR_ATVALIDM_Pos 0 /*!< ITM IWR: ATVALIDM Position */ -#define ITM_IWR_ATVALIDM_Msk (1UL << ITM_IWR_ATVALIDM_Pos) /*!< ITM IWR: ATVALIDM Mask */ +#define ITM_IWR_ATVALIDM_Pos 0 /*!< ITM IWR: ATVALIDM Position */ +#define ITM_IWR_ATVALIDM_Msk (1UL << ITM_IWR_ATVALIDM_Pos) /*!< ITM IWR: ATVALIDM Mask */ /* ITM Integration Read Register Definitions */ -#define ITM_IRR_ATREADYM_Pos 0 /*!< ITM IRR: ATREADYM Position */ -#define ITM_IRR_ATREADYM_Msk (1UL << ITM_IRR_ATREADYM_Pos) /*!< ITM IRR: ATREADYM Mask */ +#define ITM_IRR_ATREADYM_Pos 0 /*!< ITM IRR: ATREADYM Position */ +#define ITM_IRR_ATREADYM_Msk (1UL << ITM_IRR_ATREADYM_Pos) /*!< ITM IRR: ATREADYM Mask */ /* ITM Integration Mode Control Register Definitions */ -#define ITM_IMCR_INTEGRATION_Pos 0 /*!< ITM IMCR: INTEGRATION Position */ -#define ITM_IMCR_INTEGRATION_Msk (1UL << ITM_IMCR_INTEGRATION_Pos) /*!< ITM IMCR: INTEGRATION Mask */ +#define ITM_IMCR_INTEGRATION_Pos 0 /*!< ITM IMCR: INTEGRATION Position */ +#define ITM_IMCR_INTEGRATION_Msk (1UL << ITM_IMCR_INTEGRATION_Pos) /*!< ITM IMCR: INTEGRATION Mask */ /* ITM Lock Status Register Definitions */ -#define ITM_LSR_ByteAcc_Pos 2 /*!< ITM LSR: ByteAcc Position */ -#define ITM_LSR_ByteAcc_Msk (1UL << ITM_LSR_ByteAcc_Pos) /*!< ITM LSR: ByteAcc Mask */ - -#define ITM_LSR_Access_Pos 1 /*!< ITM LSR: Access Position */ -#define ITM_LSR_Access_Msk (1UL << ITM_LSR_Access_Pos) /*!< ITM LSR: Access Mask */ +#define ITM_LSR_ByteAcc_Pos 2 /*!< ITM LSR: ByteAcc Position */ +#define ITM_LSR_ByteAcc_Msk (1UL << ITM_LSR_ByteAcc_Pos) /*!< ITM LSR: ByteAcc Mask */ -#define ITM_LSR_Present_Pos 0 /*!< ITM LSR: Present Position */ -#define ITM_LSR_Present_Msk (1UL << ITM_LSR_Present_Pos) /*!< ITM LSR: Present Mask */ +#define ITM_LSR_Access_Pos 1 /*!< ITM LSR: Access Position */ +#define ITM_LSR_Access_Msk (1UL << ITM_LSR_Access_Pos) /*!< ITM LSR: Access Mask */ -/*@}*/ /* end of group CMSIS_ITM */ +#define ITM_LSR_Present_Pos 0 /*!< ITM LSR: Present Position */ +#define ITM_LSR_Present_Msk (1UL << ITM_LSR_Present_Pos) /*!< ITM LSR: Present Mask */ + /*@}*/ /* end of group CMSIS_ITM */ -/** \ingroup CMSIS_core_register + /** \ingroup CMSIS_core_register \defgroup CMSIS_DWT Data Watchpoint and Trace (DWT) \brief Type definitions for the Data Watchpoint and Trace (DWT) @{ */ -/** \brief Structure type to access the Data Watchpoint and Trace Register (DWT). + /** \brief Structure type to access the Data Watchpoint and Trace Register (DWT). */ -typedef struct -{ - __IO uint32_t CTRL; /*!< Offset: 0x000 (R/W) Control Register */ - __IO uint32_t CYCCNT; /*!< Offset: 0x004 (R/W) Cycle Count Register */ - __IO uint32_t CPICNT; /*!< Offset: 0x008 (R/W) CPI Count Register */ - __IO uint32_t EXCCNT; /*!< Offset: 0x00C (R/W) Exception Overhead Count Register */ - __IO uint32_t SLEEPCNT; /*!< Offset: 0x010 (R/W) Sleep Count Register */ - __IO uint32_t LSUCNT; /*!< Offset: 0x014 (R/W) LSU Count Register */ - __IO uint32_t FOLDCNT; /*!< Offset: 0x018 (R/W) Folded-instruction Count Register */ - __I uint32_t PCSR; /*!< Offset: 0x01C (R/ ) Program Counter Sample Register */ - __IO uint32_t COMP0; /*!< Offset: 0x020 (R/W) Comparator Register 0 */ - __IO uint32_t MASK0; /*!< Offset: 0x024 (R/W) Mask Register 0 */ - __IO uint32_t FUNCTION0; /*!< Offset: 0x028 (R/W) Function Register 0 */ - uint32_t RESERVED0[1]; - __IO uint32_t COMP1; /*!< Offset: 0x030 (R/W) Comparator Register 1 */ - __IO uint32_t MASK1; /*!< Offset: 0x034 (R/W) Mask Register 1 */ - __IO uint32_t FUNCTION1; /*!< Offset: 0x038 (R/W) Function Register 1 */ - uint32_t RESERVED1[1]; - __IO uint32_t COMP2; /*!< Offset: 0x040 (R/W) Comparator Register 2 */ - __IO uint32_t MASK2; /*!< Offset: 0x044 (R/W) Mask Register 2 */ - __IO uint32_t FUNCTION2; /*!< Offset: 0x048 (R/W) Function Register 2 */ - uint32_t RESERVED2[1]; - __IO uint32_t COMP3; /*!< Offset: 0x050 (R/W) Comparator Register 3 */ - __IO uint32_t MASK3; /*!< Offset: 0x054 (R/W) Mask Register 3 */ - __IO uint32_t FUNCTION3; /*!< Offset: 0x058 (R/W) Function Register 3 */ - uint32_t RESERVED3[981]; - __O uint32_t LAR; /*!< Offset: 0xFB0 ( W) Lock Access Register */ - __I uint32_t LSR; /*!< Offset: 0xFB4 (R ) Lock Status Register */ -} DWT_Type; + typedef struct + { + __IO uint32_t CTRL; /*!< Offset: 0x000 (R/W) Control Register */ + __IO uint32_t CYCCNT; /*!< Offset: 0x004 (R/W) Cycle Count Register */ + __IO uint32_t CPICNT; /*!< Offset: 0x008 (R/W) CPI Count Register */ + __IO uint32_t EXCCNT; /*!< Offset: 0x00C (R/W) Exception Overhead Count Register */ + __IO uint32_t SLEEPCNT; /*!< Offset: 0x010 (R/W) Sleep Count Register */ + __IO uint32_t LSUCNT; /*!< Offset: 0x014 (R/W) LSU Count Register */ + __IO uint32_t FOLDCNT; /*!< Offset: 0x018 (R/W) Folded-instruction Count Register */ + __I uint32_t PCSR; /*!< Offset: 0x01C (R/ ) Program Counter Sample Register */ + __IO uint32_t COMP0; /*!< Offset: 0x020 (R/W) Comparator Register 0 */ + __IO uint32_t MASK0; /*!< Offset: 0x024 (R/W) Mask Register 0 */ + __IO uint32_t FUNCTION0; /*!< Offset: 0x028 (R/W) Function Register 0 */ + uint32_t RESERVED0[1]; + __IO uint32_t COMP1; /*!< Offset: 0x030 (R/W) Comparator Register 1 */ + __IO uint32_t MASK1; /*!< Offset: 0x034 (R/W) Mask Register 1 */ + __IO uint32_t FUNCTION1; /*!< Offset: 0x038 (R/W) Function Register 1 */ + uint32_t RESERVED1[1]; + __IO uint32_t COMP2; /*!< Offset: 0x040 (R/W) Comparator Register 2 */ + __IO uint32_t MASK2; /*!< Offset: 0x044 (R/W) Mask Register 2 */ + __IO uint32_t FUNCTION2; /*!< Offset: 0x048 (R/W) Function Register 2 */ + uint32_t RESERVED2[1]; + __IO uint32_t COMP3; /*!< Offset: 0x050 (R/W) Comparator Register 3 */ + __IO uint32_t MASK3; /*!< Offset: 0x054 (R/W) Mask Register 3 */ + __IO uint32_t FUNCTION3; /*!< Offset: 0x058 (R/W) Function Register 3 */ + uint32_t RESERVED3[981]; + __O uint32_t LAR; /*!< Offset: 0xFB0 ( W) Lock Access Register */ + __I uint32_t LSR; /*!< Offset: 0xFB4 (R ) Lock Status Register */ + } DWT_Type; /* DWT Control Register Definitions */ -#define DWT_CTRL_NUMCOMP_Pos 28 /*!< DWT CTRL: NUMCOMP Position */ -#define DWT_CTRL_NUMCOMP_Msk (0xFUL << DWT_CTRL_NUMCOMP_Pos) /*!< DWT CTRL: NUMCOMP Mask */ +#define DWT_CTRL_NUMCOMP_Pos 28 /*!< DWT CTRL: NUMCOMP Position */ +#define DWT_CTRL_NUMCOMP_Msk (0xFUL << DWT_CTRL_NUMCOMP_Pos) /*!< DWT CTRL: NUMCOMP Mask */ -#define DWT_CTRL_NOTRCPKT_Pos 27 /*!< DWT CTRL: NOTRCPKT Position */ -#define DWT_CTRL_NOTRCPKT_Msk (0x1UL << DWT_CTRL_NOTRCPKT_Pos) /*!< DWT CTRL: NOTRCPKT Mask */ +#define DWT_CTRL_NOTRCPKT_Pos 27 /*!< DWT CTRL: NOTRCPKT Position */ +#define DWT_CTRL_NOTRCPKT_Msk (0x1UL << DWT_CTRL_NOTRCPKT_Pos) /*!< DWT CTRL: NOTRCPKT Mask */ -#define DWT_CTRL_NOEXTTRIG_Pos 26 /*!< DWT CTRL: NOEXTTRIG Position */ -#define DWT_CTRL_NOEXTTRIG_Msk (0x1UL << DWT_CTRL_NOEXTTRIG_Pos) /*!< DWT CTRL: NOEXTTRIG Mask */ +#define DWT_CTRL_NOEXTTRIG_Pos 26 /*!< DWT CTRL: NOEXTTRIG Position */ +#define DWT_CTRL_NOEXTTRIG_Msk (0x1UL << DWT_CTRL_NOEXTTRIG_Pos) /*!< DWT CTRL: NOEXTTRIG Mask */ -#define DWT_CTRL_NOCYCCNT_Pos 25 /*!< DWT CTRL: NOCYCCNT Position */ -#define DWT_CTRL_NOCYCCNT_Msk (0x1UL << DWT_CTRL_NOCYCCNT_Pos) /*!< DWT CTRL: NOCYCCNT Mask */ +#define DWT_CTRL_NOCYCCNT_Pos 25 /*!< DWT CTRL: NOCYCCNT Position */ +#define DWT_CTRL_NOCYCCNT_Msk (0x1UL << DWT_CTRL_NOCYCCNT_Pos) /*!< DWT CTRL: NOCYCCNT Mask */ -#define DWT_CTRL_NOPRFCNT_Pos 24 /*!< DWT CTRL: NOPRFCNT Position */ -#define DWT_CTRL_NOPRFCNT_Msk (0x1UL << DWT_CTRL_NOPRFCNT_Pos) /*!< DWT CTRL: NOPRFCNT Mask */ +#define DWT_CTRL_NOPRFCNT_Pos 24 /*!< DWT CTRL: NOPRFCNT Position */ +#define DWT_CTRL_NOPRFCNT_Msk (0x1UL << DWT_CTRL_NOPRFCNT_Pos) /*!< DWT CTRL: NOPRFCNT Mask */ -#define DWT_CTRL_CYCEVTENA_Pos 22 /*!< DWT CTRL: CYCEVTENA Position */ -#define DWT_CTRL_CYCEVTENA_Msk (0x1UL << DWT_CTRL_CYCEVTENA_Pos) /*!< DWT CTRL: CYCEVTENA Mask */ +#define DWT_CTRL_CYCEVTENA_Pos 22 /*!< DWT CTRL: CYCEVTENA Position */ +#define DWT_CTRL_CYCEVTENA_Msk (0x1UL << DWT_CTRL_CYCEVTENA_Pos) /*!< DWT CTRL: CYCEVTENA Mask */ -#define DWT_CTRL_FOLDEVTENA_Pos 21 /*!< DWT CTRL: FOLDEVTENA Position */ -#define DWT_CTRL_FOLDEVTENA_Msk (0x1UL << DWT_CTRL_FOLDEVTENA_Pos) /*!< DWT CTRL: FOLDEVTENA Mask */ +#define DWT_CTRL_FOLDEVTENA_Pos 21 /*!< DWT CTRL: FOLDEVTENA Position */ +#define DWT_CTRL_FOLDEVTENA_Msk (0x1UL << DWT_CTRL_FOLDEVTENA_Pos) /*!< DWT CTRL: FOLDEVTENA Mask */ -#define DWT_CTRL_LSUEVTENA_Pos 20 /*!< DWT CTRL: LSUEVTENA Position */ -#define DWT_CTRL_LSUEVTENA_Msk (0x1UL << DWT_CTRL_LSUEVTENA_Pos) /*!< DWT CTRL: LSUEVTENA Mask */ +#define DWT_CTRL_LSUEVTENA_Pos 20 /*!< DWT CTRL: LSUEVTENA Position */ +#define DWT_CTRL_LSUEVTENA_Msk (0x1UL << DWT_CTRL_LSUEVTENA_Pos) /*!< DWT CTRL: LSUEVTENA Mask */ -#define DWT_CTRL_SLEEPEVTENA_Pos 19 /*!< DWT CTRL: SLEEPEVTENA Position */ -#define DWT_CTRL_SLEEPEVTENA_Msk (0x1UL << DWT_CTRL_SLEEPEVTENA_Pos) /*!< DWT CTRL: SLEEPEVTENA Mask */ +#define DWT_CTRL_SLEEPEVTENA_Pos 19 /*!< DWT CTRL: SLEEPEVTENA Position */ +#define DWT_CTRL_SLEEPEVTENA_Msk (0x1UL << DWT_CTRL_SLEEPEVTENA_Pos) /*!< DWT CTRL: SLEEPEVTENA Mask */ -#define DWT_CTRL_EXCEVTENA_Pos 18 /*!< DWT CTRL: EXCEVTENA Position */ -#define DWT_CTRL_EXCEVTENA_Msk (0x1UL << DWT_CTRL_EXCEVTENA_Pos) /*!< DWT CTRL: EXCEVTENA Mask */ +#define DWT_CTRL_EXCEVTENA_Pos 18 /*!< DWT CTRL: EXCEVTENA Position */ +#define DWT_CTRL_EXCEVTENA_Msk (0x1UL << DWT_CTRL_EXCEVTENA_Pos) /*!< DWT CTRL: EXCEVTENA Mask */ -#define DWT_CTRL_CPIEVTENA_Pos 17 /*!< DWT CTRL: CPIEVTENA Position */ -#define DWT_CTRL_CPIEVTENA_Msk (0x1UL << DWT_CTRL_CPIEVTENA_Pos) /*!< DWT CTRL: CPIEVTENA Mask */ +#define DWT_CTRL_CPIEVTENA_Pos 17 /*!< DWT CTRL: CPIEVTENA Position */ +#define DWT_CTRL_CPIEVTENA_Msk (0x1UL << DWT_CTRL_CPIEVTENA_Pos) /*!< DWT CTRL: CPIEVTENA Mask */ -#define DWT_CTRL_EXCTRCENA_Pos 16 /*!< DWT CTRL: EXCTRCENA Position */ -#define DWT_CTRL_EXCTRCENA_Msk (0x1UL << DWT_CTRL_EXCTRCENA_Pos) /*!< DWT CTRL: EXCTRCENA Mask */ +#define DWT_CTRL_EXCTRCENA_Pos 16 /*!< DWT CTRL: EXCTRCENA Position */ +#define DWT_CTRL_EXCTRCENA_Msk (0x1UL << DWT_CTRL_EXCTRCENA_Pos) /*!< DWT CTRL: EXCTRCENA Mask */ -#define DWT_CTRL_PCSAMPLENA_Pos 12 /*!< DWT CTRL: PCSAMPLENA Position */ -#define DWT_CTRL_PCSAMPLENA_Msk (0x1UL << DWT_CTRL_PCSAMPLENA_Pos) /*!< DWT CTRL: PCSAMPLENA Mask */ +#define DWT_CTRL_PCSAMPLENA_Pos 12 /*!< DWT CTRL: PCSAMPLENA Position */ +#define DWT_CTRL_PCSAMPLENA_Msk (0x1UL << DWT_CTRL_PCSAMPLENA_Pos) /*!< DWT CTRL: PCSAMPLENA Mask */ -#define DWT_CTRL_SYNCTAP_Pos 10 /*!< DWT CTRL: SYNCTAP Position */ -#define DWT_CTRL_SYNCTAP_Msk (0x3UL << DWT_CTRL_SYNCTAP_Pos) /*!< DWT CTRL: SYNCTAP Mask */ +#define DWT_CTRL_SYNCTAP_Pos 10 /*!< DWT CTRL: SYNCTAP Position */ +#define DWT_CTRL_SYNCTAP_Msk (0x3UL << DWT_CTRL_SYNCTAP_Pos) /*!< DWT CTRL: SYNCTAP Mask */ -#define DWT_CTRL_CYCTAP_Pos 9 /*!< DWT CTRL: CYCTAP Position */ -#define DWT_CTRL_CYCTAP_Msk (0x1UL << DWT_CTRL_CYCTAP_Pos) /*!< DWT CTRL: CYCTAP Mask */ +#define DWT_CTRL_CYCTAP_Pos 9 /*!< DWT CTRL: CYCTAP Position */ +#define DWT_CTRL_CYCTAP_Msk (0x1UL << DWT_CTRL_CYCTAP_Pos) /*!< DWT CTRL: CYCTAP Mask */ -#define DWT_CTRL_POSTINIT_Pos 5 /*!< DWT CTRL: POSTINIT Position */ -#define DWT_CTRL_POSTINIT_Msk (0xFUL << DWT_CTRL_POSTINIT_Pos) /*!< DWT CTRL: POSTINIT Mask */ +#define DWT_CTRL_POSTINIT_Pos 5 /*!< DWT CTRL: POSTINIT Position */ +#define DWT_CTRL_POSTINIT_Msk (0xFUL << DWT_CTRL_POSTINIT_Pos) /*!< DWT CTRL: POSTINIT Mask */ -#define DWT_CTRL_POSTPRESET_Pos 1 /*!< DWT CTRL: POSTPRESET Position */ -#define DWT_CTRL_POSTPRESET_Msk (0xFUL << DWT_CTRL_POSTPRESET_Pos) /*!< DWT CTRL: POSTPRESET Mask */ +#define DWT_CTRL_POSTPRESET_Pos 1 /*!< DWT CTRL: POSTPRESET Position */ +#define DWT_CTRL_POSTPRESET_Msk (0xFUL << DWT_CTRL_POSTPRESET_Pos) /*!< DWT CTRL: POSTPRESET Mask */ -#define DWT_CTRL_CYCCNTENA_Pos 0 /*!< DWT CTRL: CYCCNTENA Position */ -#define DWT_CTRL_CYCCNTENA_Msk (0x1UL << DWT_CTRL_CYCCNTENA_Pos) /*!< DWT CTRL: CYCCNTENA Mask */ +#define DWT_CTRL_CYCCNTENA_Pos 0 /*!< DWT CTRL: CYCCNTENA Position */ +#define DWT_CTRL_CYCCNTENA_Msk (0x1UL << DWT_CTRL_CYCCNTENA_Pos) /*!< DWT CTRL: CYCCNTENA Mask */ /* DWT CPI Count Register Definitions */ -#define DWT_CPICNT_CPICNT_Pos 0 /*!< DWT CPICNT: CPICNT Position */ -#define DWT_CPICNT_CPICNT_Msk (0xFFUL << DWT_CPICNT_CPICNT_Pos) /*!< DWT CPICNT: CPICNT Mask */ +#define DWT_CPICNT_CPICNT_Pos 0 /*!< DWT CPICNT: CPICNT Position */ +#define DWT_CPICNT_CPICNT_Msk (0xFFUL << DWT_CPICNT_CPICNT_Pos) /*!< DWT CPICNT: CPICNT Mask */ /* DWT Exception Overhead Count Register Definitions */ -#define DWT_EXCCNT_EXCCNT_Pos 0 /*!< DWT EXCCNT: EXCCNT Position */ -#define DWT_EXCCNT_EXCCNT_Msk (0xFFUL << DWT_EXCCNT_EXCCNT_Pos) /*!< DWT EXCCNT: EXCCNT Mask */ +#define DWT_EXCCNT_EXCCNT_Pos 0 /*!< DWT EXCCNT: EXCCNT Position */ +#define DWT_EXCCNT_EXCCNT_Msk (0xFFUL << DWT_EXCCNT_EXCCNT_Pos) /*!< DWT EXCCNT: EXCCNT Mask */ /* DWT Sleep Count Register Definitions */ -#define DWT_SLEEPCNT_SLEEPCNT_Pos 0 /*!< DWT SLEEPCNT: SLEEPCNT Position */ -#define DWT_SLEEPCNT_SLEEPCNT_Msk (0xFFUL << DWT_SLEEPCNT_SLEEPCNT_Pos) /*!< DWT SLEEPCNT: SLEEPCNT Mask */ +#define DWT_SLEEPCNT_SLEEPCNT_Pos 0 /*!< DWT SLEEPCNT: SLEEPCNT Position */ +#define DWT_SLEEPCNT_SLEEPCNT_Msk (0xFFUL << DWT_SLEEPCNT_SLEEPCNT_Pos) /*!< DWT SLEEPCNT: SLEEPCNT Mask */ /* DWT LSU Count Register Definitions */ -#define DWT_LSUCNT_LSUCNT_Pos 0 /*!< DWT LSUCNT: LSUCNT Position */ -#define DWT_LSUCNT_LSUCNT_Msk (0xFFUL << DWT_LSUCNT_LSUCNT_Pos) /*!< DWT LSUCNT: LSUCNT Mask */ +#define DWT_LSUCNT_LSUCNT_Pos 0 /*!< DWT LSUCNT: LSUCNT Position */ +#define DWT_LSUCNT_LSUCNT_Msk (0xFFUL << DWT_LSUCNT_LSUCNT_Pos) /*!< DWT LSUCNT: LSUCNT Mask */ /* DWT Folded-instruction Count Register Definitions */ -#define DWT_FOLDCNT_FOLDCNT_Pos 0 /*!< DWT FOLDCNT: FOLDCNT Position */ -#define DWT_FOLDCNT_FOLDCNT_Msk (0xFFUL << DWT_FOLDCNT_FOLDCNT_Pos) /*!< DWT FOLDCNT: FOLDCNT Mask */ +#define DWT_FOLDCNT_FOLDCNT_Pos 0 /*!< DWT FOLDCNT: FOLDCNT Position */ +#define DWT_FOLDCNT_FOLDCNT_Msk (0xFFUL << DWT_FOLDCNT_FOLDCNT_Pos) /*!< DWT FOLDCNT: FOLDCNT Mask */ /* DWT Comparator Mask Register Definitions */ -#define DWT_MASK_MASK_Pos 0 /*!< DWT MASK: MASK Position */ -#define DWT_MASK_MASK_Msk (0x1FUL << DWT_MASK_MASK_Pos) /*!< DWT MASK: MASK Mask */ +#define DWT_MASK_MASK_Pos 0 /*!< DWT MASK: MASK Position */ +#define DWT_MASK_MASK_Msk (0x1FUL << DWT_MASK_MASK_Pos) /*!< DWT MASK: MASK Mask */ /* DWT Comparator Function Register Definitions */ -#define DWT_FUNCTION_MATCHED_Pos 24 /*!< DWT FUNCTION: MATCHED Position */ -#define DWT_FUNCTION_MATCHED_Msk (0x1UL << DWT_FUNCTION_MATCHED_Pos) /*!< DWT FUNCTION: MATCHED Mask */ - -#define DWT_FUNCTION_DATAVADDR1_Pos 16 /*!< DWT FUNCTION: DATAVADDR1 Position */ -#define DWT_FUNCTION_DATAVADDR1_Msk (0xFUL << DWT_FUNCTION_DATAVADDR1_Pos) /*!< DWT FUNCTION: DATAVADDR1 Mask */ +#define DWT_FUNCTION_MATCHED_Pos 24 /*!< DWT FUNCTION: MATCHED Position */ +#define DWT_FUNCTION_MATCHED_Msk (0x1UL << DWT_FUNCTION_MATCHED_Pos) /*!< DWT FUNCTION: MATCHED Mask */ -#define DWT_FUNCTION_DATAVADDR0_Pos 12 /*!< DWT FUNCTION: DATAVADDR0 Position */ -#define DWT_FUNCTION_DATAVADDR0_Msk (0xFUL << DWT_FUNCTION_DATAVADDR0_Pos) /*!< DWT FUNCTION: DATAVADDR0 Mask */ +#define DWT_FUNCTION_DATAVADDR1_Pos 16 /*!< DWT FUNCTION: DATAVADDR1 Position */ +#define DWT_FUNCTION_DATAVADDR1_Msk (0xFUL << DWT_FUNCTION_DATAVADDR1_Pos) /*!< DWT FUNCTION: DATAVADDR1 Mask */ -#define DWT_FUNCTION_DATAVSIZE_Pos 10 /*!< DWT FUNCTION: DATAVSIZE Position */ -#define DWT_FUNCTION_DATAVSIZE_Msk (0x3UL << DWT_FUNCTION_DATAVSIZE_Pos) /*!< DWT FUNCTION: DATAVSIZE Mask */ +#define DWT_FUNCTION_DATAVADDR0_Pos 12 /*!< DWT FUNCTION: DATAVADDR0 Position */ +#define DWT_FUNCTION_DATAVADDR0_Msk (0xFUL << DWT_FUNCTION_DATAVADDR0_Pos) /*!< DWT FUNCTION: DATAVADDR0 Mask */ -#define DWT_FUNCTION_LNK1ENA_Pos 9 /*!< DWT FUNCTION: LNK1ENA Position */ -#define DWT_FUNCTION_LNK1ENA_Msk (0x1UL << DWT_FUNCTION_LNK1ENA_Pos) /*!< DWT FUNCTION: LNK1ENA Mask */ +#define DWT_FUNCTION_DATAVSIZE_Pos 10 /*!< DWT FUNCTION: DATAVSIZE Position */ +#define DWT_FUNCTION_DATAVSIZE_Msk (0x3UL << DWT_FUNCTION_DATAVSIZE_Pos) /*!< DWT FUNCTION: DATAVSIZE Mask */ -#define DWT_FUNCTION_DATAVMATCH_Pos 8 /*!< DWT FUNCTION: DATAVMATCH Position */ -#define DWT_FUNCTION_DATAVMATCH_Msk (0x1UL << DWT_FUNCTION_DATAVMATCH_Pos) /*!< DWT FUNCTION: DATAVMATCH Mask */ +#define DWT_FUNCTION_LNK1ENA_Pos 9 /*!< DWT FUNCTION: LNK1ENA Position */ +#define DWT_FUNCTION_LNK1ENA_Msk (0x1UL << DWT_FUNCTION_LNK1ENA_Pos) /*!< DWT FUNCTION: LNK1ENA Mask */ -#define DWT_FUNCTION_CYCMATCH_Pos 7 /*!< DWT FUNCTION: CYCMATCH Position */ -#define DWT_FUNCTION_CYCMATCH_Msk (0x1UL << DWT_FUNCTION_CYCMATCH_Pos) /*!< DWT FUNCTION: CYCMATCH Mask */ +#define DWT_FUNCTION_DATAVMATCH_Pos 8 /*!< DWT FUNCTION: DATAVMATCH Position */ +#define DWT_FUNCTION_DATAVMATCH_Msk (0x1UL << DWT_FUNCTION_DATAVMATCH_Pos) /*!< DWT FUNCTION: DATAVMATCH Mask */ -#define DWT_FUNCTION_EMITRANGE_Pos 5 /*!< DWT FUNCTION: EMITRANGE Position */ -#define DWT_FUNCTION_EMITRANGE_Msk (0x1UL << DWT_FUNCTION_EMITRANGE_Pos) /*!< DWT FUNCTION: EMITRANGE Mask */ +#define DWT_FUNCTION_CYCMATCH_Pos 7 /*!< DWT FUNCTION: CYCMATCH Position */ +#define DWT_FUNCTION_CYCMATCH_Msk (0x1UL << DWT_FUNCTION_CYCMATCH_Pos) /*!< DWT FUNCTION: CYCMATCH Mask */ -#define DWT_FUNCTION_FUNCTION_Pos 0 /*!< DWT FUNCTION: FUNCTION Position */ -#define DWT_FUNCTION_FUNCTION_Msk (0xFUL << DWT_FUNCTION_FUNCTION_Pos) /*!< DWT FUNCTION: FUNCTION Mask */ +#define DWT_FUNCTION_EMITRANGE_Pos 5 /*!< DWT FUNCTION: EMITRANGE Position */ +#define DWT_FUNCTION_EMITRANGE_Msk (0x1UL << DWT_FUNCTION_EMITRANGE_Pos) /*!< DWT FUNCTION: EMITRANGE Mask */ -/*@}*/ /* end of group CMSIS_DWT */ +#define DWT_FUNCTION_FUNCTION_Pos 0 /*!< DWT FUNCTION: FUNCTION Position */ +#define DWT_FUNCTION_FUNCTION_Msk (0xFUL << DWT_FUNCTION_FUNCTION_Pos) /*!< DWT FUNCTION: FUNCTION Mask */ + /*@}*/ /* end of group CMSIS_DWT */ -/** \ingroup CMSIS_core_register + /** \ingroup CMSIS_core_register \defgroup CMSIS_TPI Trace Port Interface (TPI) \brief Type definitions for the Trace Port Interface (TPI) @{ */ -/** \brief Structure type to access the Trace Port Interface Register (TPI). + /** \brief Structure type to access the Trace Port Interface Register (TPI). */ -typedef struct -{ - __IO uint32_t SSPSR; /*!< Offset: 0x000 (R/ ) Supported Parallel Port Size Register */ - __IO uint32_t CSPSR; /*!< Offset: 0x004 (R/W) Current Parallel Port Size Register */ - uint32_t RESERVED0[2]; - __IO uint32_t ACPR; /*!< Offset: 0x010 (R/W) Asynchronous Clock Prescaler Register */ - uint32_t RESERVED1[55]; - __IO uint32_t SPPR; /*!< Offset: 0x0F0 (R/W) Selected Pin Protocol Register */ - uint32_t RESERVED2[131]; - __I uint32_t FFSR; /*!< Offset: 0x300 (R/ ) Formatter and Flush Status Register */ - __IO uint32_t FFCR; /*!< Offset: 0x304 (R/W) Formatter and Flush Control Register */ - __I uint32_t FSCR; /*!< Offset: 0x308 (R/ ) Formatter Synchronization Counter Register */ - uint32_t RESERVED3[759]; - __I uint32_t TRIGGER; /*!< Offset: 0xEE8 (R/ ) TRIGGER */ - __I uint32_t FIFO0; /*!< Offset: 0xEEC (R/ ) Integration ETM Data */ - __I uint32_t ITATBCTR2; /*!< Offset: 0xEF0 (R/ ) ITATBCTR2 */ - uint32_t RESERVED4[1]; - __I uint32_t ITATBCTR0; /*!< Offset: 0xEF8 (R/ ) ITATBCTR0 */ - __I uint32_t FIFO1; /*!< Offset: 0xEFC (R/ ) Integration ITM Data */ - __IO uint32_t ITCTRL; /*!< Offset: 0xF00 (R/W) Integration Mode Control */ - uint32_t RESERVED5[39]; - __IO uint32_t CLAIMSET; /*!< Offset: 0xFA0 (R/W) Claim tag set */ - __IO uint32_t CLAIMCLR; /*!< Offset: 0xFA4 (R/W) Claim tag clear */ - uint32_t RESERVED7[8]; - __I uint32_t DEVID; /*!< Offset: 0xFC8 (R/ ) TPIU_DEVID */ - __I uint32_t DEVTYPE; /*!< Offset: 0xFCC (R/ ) TPIU_DEVTYPE */ -} TPI_Type; + typedef struct + { + __IO uint32_t SSPSR; /*!< Offset: 0x000 (R/ ) Supported Parallel Port Size Register */ + __IO uint32_t CSPSR; /*!< Offset: 0x004 (R/W) Current Parallel Port Size Register */ + uint32_t RESERVED0[2]; + __IO uint32_t ACPR; /*!< Offset: 0x010 (R/W) Asynchronous Clock Prescaler Register */ + uint32_t RESERVED1[55]; + __IO uint32_t SPPR; /*!< Offset: 0x0F0 (R/W) Selected Pin Protocol Register */ + uint32_t RESERVED2[131]; + __I uint32_t FFSR; /*!< Offset: 0x300 (R/ ) Formatter and Flush Status Register */ + __IO uint32_t FFCR; /*!< Offset: 0x304 (R/W) Formatter and Flush Control Register */ + __I uint32_t FSCR; /*!< Offset: 0x308 (R/ ) Formatter Synchronization Counter Register */ + uint32_t RESERVED3[759]; + __I uint32_t TRIGGER; /*!< Offset: 0xEE8 (R/ ) TRIGGER */ + __I uint32_t FIFO0; /*!< Offset: 0xEEC (R/ ) Integration ETM Data */ + __I uint32_t ITATBCTR2; /*!< Offset: 0xEF0 (R/ ) ITATBCTR2 */ + uint32_t RESERVED4[1]; + __I uint32_t ITATBCTR0; /*!< Offset: 0xEF8 (R/ ) ITATBCTR0 */ + __I uint32_t FIFO1; /*!< Offset: 0xEFC (R/ ) Integration ITM Data */ + __IO uint32_t ITCTRL; /*!< Offset: 0xF00 (R/W) Integration Mode Control */ + uint32_t RESERVED5[39]; + __IO uint32_t CLAIMSET; /*!< Offset: 0xFA0 (R/W) Claim tag set */ + __IO uint32_t CLAIMCLR; /*!< Offset: 0xFA4 (R/W) Claim tag clear */ + uint32_t RESERVED7[8]; + __I uint32_t DEVID; /*!< Offset: 0xFC8 (R/ ) TPIU_DEVID */ + __I uint32_t DEVTYPE; /*!< Offset: 0xFCC (R/ ) TPIU_DEVTYPE */ + } TPI_Type; /* TPI Asynchronous Clock Prescaler Register Definitions */ -#define TPI_ACPR_PRESCALER_Pos 0 /*!< TPI ACPR: PRESCALER Position */ -#define TPI_ACPR_PRESCALER_Msk (0x1FFFUL << TPI_ACPR_PRESCALER_Pos) /*!< TPI ACPR: PRESCALER Mask */ +#define TPI_ACPR_PRESCALER_Pos 0 /*!< TPI ACPR: PRESCALER Position */ +#define TPI_ACPR_PRESCALER_Msk (0x1FFFUL << TPI_ACPR_PRESCALER_Pos) /*!< TPI ACPR: PRESCALER Mask */ /* TPI Selected Pin Protocol Register Definitions */ -#define TPI_SPPR_TXMODE_Pos 0 /*!< TPI SPPR: TXMODE Position */ -#define TPI_SPPR_TXMODE_Msk (0x3UL << TPI_SPPR_TXMODE_Pos) /*!< TPI SPPR: TXMODE Mask */ +#define TPI_SPPR_TXMODE_Pos 0 /*!< TPI SPPR: TXMODE Position */ +#define TPI_SPPR_TXMODE_Msk (0x3UL << TPI_SPPR_TXMODE_Pos) /*!< TPI SPPR: TXMODE Mask */ /* TPI Formatter and Flush Status Register Definitions */ -#define TPI_FFSR_FtNonStop_Pos 3 /*!< TPI FFSR: FtNonStop Position */ -#define TPI_FFSR_FtNonStop_Msk (0x1UL << TPI_FFSR_FtNonStop_Pos) /*!< TPI FFSR: FtNonStop Mask */ +#define TPI_FFSR_FtNonStop_Pos 3 /*!< TPI FFSR: FtNonStop Position */ +#define TPI_FFSR_FtNonStop_Msk (0x1UL << TPI_FFSR_FtNonStop_Pos) /*!< TPI FFSR: FtNonStop Mask */ -#define TPI_FFSR_TCPresent_Pos 2 /*!< TPI FFSR: TCPresent Position */ -#define TPI_FFSR_TCPresent_Msk (0x1UL << TPI_FFSR_TCPresent_Pos) /*!< TPI FFSR: TCPresent Mask */ +#define TPI_FFSR_TCPresent_Pos 2 /*!< TPI FFSR: TCPresent Position */ +#define TPI_FFSR_TCPresent_Msk (0x1UL << TPI_FFSR_TCPresent_Pos) /*!< TPI FFSR: TCPresent Mask */ -#define TPI_FFSR_FtStopped_Pos 1 /*!< TPI FFSR: FtStopped Position */ -#define TPI_FFSR_FtStopped_Msk (0x1UL << TPI_FFSR_FtStopped_Pos) /*!< TPI FFSR: FtStopped Mask */ +#define TPI_FFSR_FtStopped_Pos 1 /*!< TPI FFSR: FtStopped Position */ +#define TPI_FFSR_FtStopped_Msk (0x1UL << TPI_FFSR_FtStopped_Pos) /*!< TPI FFSR: FtStopped Mask */ -#define TPI_FFSR_FlInProg_Pos 0 /*!< TPI FFSR: FlInProg Position */ -#define TPI_FFSR_FlInProg_Msk (0x1UL << TPI_FFSR_FlInProg_Pos) /*!< TPI FFSR: FlInProg Mask */ +#define TPI_FFSR_FlInProg_Pos 0 /*!< TPI FFSR: FlInProg Position */ +#define TPI_FFSR_FlInProg_Msk (0x1UL << TPI_FFSR_FlInProg_Pos) /*!< TPI FFSR: FlInProg Mask */ /* TPI Formatter and Flush Control Register Definitions */ -#define TPI_FFCR_TrigIn_Pos 8 /*!< TPI FFCR: TrigIn Position */ -#define TPI_FFCR_TrigIn_Msk (0x1UL << TPI_FFCR_TrigIn_Pos) /*!< TPI FFCR: TrigIn Mask */ +#define TPI_FFCR_TrigIn_Pos 8 /*!< TPI FFCR: TrigIn Position */ +#define TPI_FFCR_TrigIn_Msk (0x1UL << TPI_FFCR_TrigIn_Pos) /*!< TPI FFCR: TrigIn Mask */ -#define TPI_FFCR_EnFCont_Pos 1 /*!< TPI FFCR: EnFCont Position */ -#define TPI_FFCR_EnFCont_Msk (0x1UL << TPI_FFCR_EnFCont_Pos) /*!< TPI FFCR: EnFCont Mask */ +#define TPI_FFCR_EnFCont_Pos 1 /*!< TPI FFCR: EnFCont Position */ +#define TPI_FFCR_EnFCont_Msk (0x1UL << TPI_FFCR_EnFCont_Pos) /*!< TPI FFCR: EnFCont Mask */ /* TPI TRIGGER Register Definitions */ -#define TPI_TRIGGER_TRIGGER_Pos 0 /*!< TPI TRIGGER: TRIGGER Position */ -#define TPI_TRIGGER_TRIGGER_Msk (0x1UL << TPI_TRIGGER_TRIGGER_Pos) /*!< TPI TRIGGER: TRIGGER Mask */ +#define TPI_TRIGGER_TRIGGER_Pos 0 /*!< TPI TRIGGER: TRIGGER Position */ +#define TPI_TRIGGER_TRIGGER_Msk (0x1UL << TPI_TRIGGER_TRIGGER_Pos) /*!< TPI TRIGGER: TRIGGER Mask */ /* TPI Integration ETM Data Register Definitions (FIFO0) */ -#define TPI_FIFO0_ITM_ATVALID_Pos 29 /*!< TPI FIFO0: ITM_ATVALID Position */ -#define TPI_FIFO0_ITM_ATVALID_Msk (0x3UL << TPI_FIFO0_ITM_ATVALID_Pos) /*!< TPI FIFO0: ITM_ATVALID Mask */ +#define TPI_FIFO0_ITM_ATVALID_Pos 29 /*!< TPI FIFO0: ITM_ATVALID Position */ +#define TPI_FIFO0_ITM_ATVALID_Msk (0x3UL << TPI_FIFO0_ITM_ATVALID_Pos) /*!< TPI FIFO0: ITM_ATVALID Mask */ -#define TPI_FIFO0_ITM_bytecount_Pos 27 /*!< TPI FIFO0: ITM_bytecount Position */ -#define TPI_FIFO0_ITM_bytecount_Msk (0x3UL << TPI_FIFO0_ITM_bytecount_Pos) /*!< TPI FIFO0: ITM_bytecount Mask */ +#define TPI_FIFO0_ITM_bytecount_Pos 27 /*!< TPI FIFO0: ITM_bytecount Position */ +#define TPI_FIFO0_ITM_bytecount_Msk (0x3UL << TPI_FIFO0_ITM_bytecount_Pos) /*!< TPI FIFO0: ITM_bytecount Mask */ -#define TPI_FIFO0_ETM_ATVALID_Pos 26 /*!< TPI FIFO0: ETM_ATVALID Position */ -#define TPI_FIFO0_ETM_ATVALID_Msk (0x3UL << TPI_FIFO0_ETM_ATVALID_Pos) /*!< TPI FIFO0: ETM_ATVALID Mask */ +#define TPI_FIFO0_ETM_ATVALID_Pos 26 /*!< TPI FIFO0: ETM_ATVALID Position */ +#define TPI_FIFO0_ETM_ATVALID_Msk (0x3UL << TPI_FIFO0_ETM_ATVALID_Pos) /*!< TPI FIFO0: ETM_ATVALID Mask */ -#define TPI_FIFO0_ETM_bytecount_Pos 24 /*!< TPI FIFO0: ETM_bytecount Position */ -#define TPI_FIFO0_ETM_bytecount_Msk (0x3UL << TPI_FIFO0_ETM_bytecount_Pos) /*!< TPI FIFO0: ETM_bytecount Mask */ +#define TPI_FIFO0_ETM_bytecount_Pos 24 /*!< TPI FIFO0: ETM_bytecount Position */ +#define TPI_FIFO0_ETM_bytecount_Msk (0x3UL << TPI_FIFO0_ETM_bytecount_Pos) /*!< TPI FIFO0: ETM_bytecount Mask */ -#define TPI_FIFO0_ETM2_Pos 16 /*!< TPI FIFO0: ETM2 Position */ -#define TPI_FIFO0_ETM2_Msk (0xFFUL << TPI_FIFO0_ETM2_Pos) /*!< TPI FIFO0: ETM2 Mask */ +#define TPI_FIFO0_ETM2_Pos 16 /*!< TPI FIFO0: ETM2 Position */ +#define TPI_FIFO0_ETM2_Msk (0xFFUL << TPI_FIFO0_ETM2_Pos) /*!< TPI FIFO0: ETM2 Mask */ -#define TPI_FIFO0_ETM1_Pos 8 /*!< TPI FIFO0: ETM1 Position */ -#define TPI_FIFO0_ETM1_Msk (0xFFUL << TPI_FIFO0_ETM1_Pos) /*!< TPI FIFO0: ETM1 Mask */ +#define TPI_FIFO0_ETM1_Pos 8 /*!< TPI FIFO0: ETM1 Position */ +#define TPI_FIFO0_ETM1_Msk (0xFFUL << TPI_FIFO0_ETM1_Pos) /*!< TPI FIFO0: ETM1 Mask */ -#define TPI_FIFO0_ETM0_Pos 0 /*!< TPI FIFO0: ETM0 Position */ -#define TPI_FIFO0_ETM0_Msk (0xFFUL << TPI_FIFO0_ETM0_Pos) /*!< TPI FIFO0: ETM0 Mask */ +#define TPI_FIFO0_ETM0_Pos 0 /*!< TPI FIFO0: ETM0 Position */ +#define TPI_FIFO0_ETM0_Msk (0xFFUL << TPI_FIFO0_ETM0_Pos) /*!< TPI FIFO0: ETM0 Mask */ /* TPI ITATBCTR2 Register Definitions */ -#define TPI_ITATBCTR2_ATREADY_Pos 0 /*!< TPI ITATBCTR2: ATREADY Position */ -#define TPI_ITATBCTR2_ATREADY_Msk (0x1UL << TPI_ITATBCTR2_ATREADY_Pos) /*!< TPI ITATBCTR2: ATREADY Mask */ +#define TPI_ITATBCTR2_ATREADY_Pos 0 /*!< TPI ITATBCTR2: ATREADY Position */ +#define TPI_ITATBCTR2_ATREADY_Msk (0x1UL << TPI_ITATBCTR2_ATREADY_Pos) /*!< TPI ITATBCTR2: ATREADY Mask */ /* TPI Integration ITM Data Register Definitions (FIFO1) */ -#define TPI_FIFO1_ITM_ATVALID_Pos 29 /*!< TPI FIFO1: ITM_ATVALID Position */ -#define TPI_FIFO1_ITM_ATVALID_Msk (0x3UL << TPI_FIFO1_ITM_ATVALID_Pos) /*!< TPI FIFO1: ITM_ATVALID Mask */ +#define TPI_FIFO1_ITM_ATVALID_Pos 29 /*!< TPI FIFO1: ITM_ATVALID Position */ +#define TPI_FIFO1_ITM_ATVALID_Msk (0x3UL << TPI_FIFO1_ITM_ATVALID_Pos) /*!< TPI FIFO1: ITM_ATVALID Mask */ -#define TPI_FIFO1_ITM_bytecount_Pos 27 /*!< TPI FIFO1: ITM_bytecount Position */ -#define TPI_FIFO1_ITM_bytecount_Msk (0x3UL << TPI_FIFO1_ITM_bytecount_Pos) /*!< TPI FIFO1: ITM_bytecount Mask */ +#define TPI_FIFO1_ITM_bytecount_Pos 27 /*!< TPI FIFO1: ITM_bytecount Position */ +#define TPI_FIFO1_ITM_bytecount_Msk (0x3UL << TPI_FIFO1_ITM_bytecount_Pos) /*!< TPI FIFO1: ITM_bytecount Mask */ -#define TPI_FIFO1_ETM_ATVALID_Pos 26 /*!< TPI FIFO1: ETM_ATVALID Position */ -#define TPI_FIFO1_ETM_ATVALID_Msk (0x3UL << TPI_FIFO1_ETM_ATVALID_Pos) /*!< TPI FIFO1: ETM_ATVALID Mask */ +#define TPI_FIFO1_ETM_ATVALID_Pos 26 /*!< TPI FIFO1: ETM_ATVALID Position */ +#define TPI_FIFO1_ETM_ATVALID_Msk (0x3UL << TPI_FIFO1_ETM_ATVALID_Pos) /*!< TPI FIFO1: ETM_ATVALID Mask */ -#define TPI_FIFO1_ETM_bytecount_Pos 24 /*!< TPI FIFO1: ETM_bytecount Position */ -#define TPI_FIFO1_ETM_bytecount_Msk (0x3UL << TPI_FIFO1_ETM_bytecount_Pos) /*!< TPI FIFO1: ETM_bytecount Mask */ +#define TPI_FIFO1_ETM_bytecount_Pos 24 /*!< TPI FIFO1: ETM_bytecount Position */ +#define TPI_FIFO1_ETM_bytecount_Msk (0x3UL << TPI_FIFO1_ETM_bytecount_Pos) /*!< TPI FIFO1: ETM_bytecount Mask */ -#define TPI_FIFO1_ITM2_Pos 16 /*!< TPI FIFO1: ITM2 Position */ -#define TPI_FIFO1_ITM2_Msk (0xFFUL << TPI_FIFO1_ITM2_Pos) /*!< TPI FIFO1: ITM2 Mask */ +#define TPI_FIFO1_ITM2_Pos 16 /*!< TPI FIFO1: ITM2 Position */ +#define TPI_FIFO1_ITM2_Msk (0xFFUL << TPI_FIFO1_ITM2_Pos) /*!< TPI FIFO1: ITM2 Mask */ -#define TPI_FIFO1_ITM1_Pos 8 /*!< TPI FIFO1: ITM1 Position */ -#define TPI_FIFO1_ITM1_Msk (0xFFUL << TPI_FIFO1_ITM1_Pos) /*!< TPI FIFO1: ITM1 Mask */ +#define TPI_FIFO1_ITM1_Pos 8 /*!< TPI FIFO1: ITM1 Position */ +#define TPI_FIFO1_ITM1_Msk (0xFFUL << TPI_FIFO1_ITM1_Pos) /*!< TPI FIFO1: ITM1 Mask */ -#define TPI_FIFO1_ITM0_Pos 0 /*!< TPI FIFO1: ITM0 Position */ -#define TPI_FIFO1_ITM0_Msk (0xFFUL << TPI_FIFO1_ITM0_Pos) /*!< TPI FIFO1: ITM0 Mask */ +#define TPI_FIFO1_ITM0_Pos 0 /*!< TPI FIFO1: ITM0 Position */ +#define TPI_FIFO1_ITM0_Msk (0xFFUL << TPI_FIFO1_ITM0_Pos) /*!< TPI FIFO1: ITM0 Mask */ /* TPI ITATBCTR0 Register Definitions */ -#define TPI_ITATBCTR0_ATREADY_Pos 0 /*!< TPI ITATBCTR0: ATREADY Position */ -#define TPI_ITATBCTR0_ATREADY_Msk (0x1UL << TPI_ITATBCTR0_ATREADY_Pos) /*!< TPI ITATBCTR0: ATREADY Mask */ +#define TPI_ITATBCTR0_ATREADY_Pos 0 /*!< TPI ITATBCTR0: ATREADY Position */ +#define TPI_ITATBCTR0_ATREADY_Msk (0x1UL << TPI_ITATBCTR0_ATREADY_Pos) /*!< TPI ITATBCTR0: ATREADY Mask */ /* TPI Integration Mode Control Register Definitions */ -#define TPI_ITCTRL_Mode_Pos 0 /*!< TPI ITCTRL: Mode Position */ -#define TPI_ITCTRL_Mode_Msk (0x1UL << TPI_ITCTRL_Mode_Pos) /*!< TPI ITCTRL: Mode Mask */ +#define TPI_ITCTRL_Mode_Pos 0 /*!< TPI ITCTRL: Mode Position */ +#define TPI_ITCTRL_Mode_Msk (0x1UL << TPI_ITCTRL_Mode_Pos) /*!< TPI ITCTRL: Mode Mask */ /* TPI DEVID Register Definitions */ -#define TPI_DEVID_NRZVALID_Pos 11 /*!< TPI DEVID: NRZVALID Position */ -#define TPI_DEVID_NRZVALID_Msk (0x1UL << TPI_DEVID_NRZVALID_Pos) /*!< TPI DEVID: NRZVALID Mask */ +#define TPI_DEVID_NRZVALID_Pos 11 /*!< TPI DEVID: NRZVALID Position */ +#define TPI_DEVID_NRZVALID_Msk (0x1UL << TPI_DEVID_NRZVALID_Pos) /*!< TPI DEVID: NRZVALID Mask */ -#define TPI_DEVID_MANCVALID_Pos 10 /*!< TPI DEVID: MANCVALID Position */ -#define TPI_DEVID_MANCVALID_Msk (0x1UL << TPI_DEVID_MANCVALID_Pos) /*!< TPI DEVID: MANCVALID Mask */ +#define TPI_DEVID_MANCVALID_Pos 10 /*!< TPI DEVID: MANCVALID Position */ +#define TPI_DEVID_MANCVALID_Msk (0x1UL << TPI_DEVID_MANCVALID_Pos) /*!< TPI DEVID: MANCVALID Mask */ -#define TPI_DEVID_PTINVALID_Pos 9 /*!< TPI DEVID: PTINVALID Position */ -#define TPI_DEVID_PTINVALID_Msk (0x1UL << TPI_DEVID_PTINVALID_Pos) /*!< TPI DEVID: PTINVALID Mask */ +#define TPI_DEVID_PTINVALID_Pos 9 /*!< TPI DEVID: PTINVALID Position */ +#define TPI_DEVID_PTINVALID_Msk (0x1UL << TPI_DEVID_PTINVALID_Pos) /*!< TPI DEVID: PTINVALID Mask */ -#define TPI_DEVID_MinBufSz_Pos 6 /*!< TPI DEVID: MinBufSz Position */ -#define TPI_DEVID_MinBufSz_Msk (0x7UL << TPI_DEVID_MinBufSz_Pos) /*!< TPI DEVID: MinBufSz Mask */ +#define TPI_DEVID_MinBufSz_Pos 6 /*!< TPI DEVID: MinBufSz Position */ +#define TPI_DEVID_MinBufSz_Msk (0x7UL << TPI_DEVID_MinBufSz_Pos) /*!< TPI DEVID: MinBufSz Mask */ -#define TPI_DEVID_AsynClkIn_Pos 5 /*!< TPI DEVID: AsynClkIn Position */ -#define TPI_DEVID_AsynClkIn_Msk (0x1UL << TPI_DEVID_AsynClkIn_Pos) /*!< TPI DEVID: AsynClkIn Mask */ +#define TPI_DEVID_AsynClkIn_Pos 5 /*!< TPI DEVID: AsynClkIn Position */ +#define TPI_DEVID_AsynClkIn_Msk (0x1UL << TPI_DEVID_AsynClkIn_Pos) /*!< TPI DEVID: AsynClkIn Mask */ -#define TPI_DEVID_NrTraceInput_Pos 0 /*!< TPI DEVID: NrTraceInput Position */ -#define TPI_DEVID_NrTraceInput_Msk (0x1FUL << TPI_DEVID_NrTraceInput_Pos) /*!< TPI DEVID: NrTraceInput Mask */ +#define TPI_DEVID_NrTraceInput_Pos 0 /*!< TPI DEVID: NrTraceInput Position */ +#define TPI_DEVID_NrTraceInput_Msk (0x1FUL << TPI_DEVID_NrTraceInput_Pos) /*!< TPI DEVID: NrTraceInput Mask */ /* TPI DEVTYPE Register Definitions */ -#define TPI_DEVTYPE_SubType_Pos 0 /*!< TPI DEVTYPE: SubType Position */ -#define TPI_DEVTYPE_SubType_Msk (0xFUL << TPI_DEVTYPE_SubType_Pos) /*!< TPI DEVTYPE: SubType Mask */ +#define TPI_DEVTYPE_SubType_Pos 0 /*!< TPI DEVTYPE: SubType Position */ +#define TPI_DEVTYPE_SubType_Msk (0xFUL << TPI_DEVTYPE_SubType_Pos) /*!< TPI DEVTYPE: SubType Mask */ -#define TPI_DEVTYPE_MajorType_Pos 4 /*!< TPI DEVTYPE: MajorType Position */ -#define TPI_DEVTYPE_MajorType_Msk (0xFUL << TPI_DEVTYPE_MajorType_Pos) /*!< TPI DEVTYPE: MajorType Mask */ - -/*@}*/ /* end of group CMSIS_TPI */ +#define TPI_DEVTYPE_MajorType_Pos 4 /*!< TPI DEVTYPE: MajorType Position */ +#define TPI_DEVTYPE_MajorType_Msk (0xFUL << TPI_DEVTYPE_MajorType_Pos) /*!< TPI DEVTYPE: MajorType Mask */ + /*@}*/ /* end of group CMSIS_TPI */ #if (__MPU_PRESENT == 1) -/** \ingroup CMSIS_core_register + /** \ingroup CMSIS_core_register \defgroup CMSIS_MPU Memory Protection Unit (MPU) \brief Type definitions for the Memory Protection Unit (MPU) @{ */ -/** \brief Structure type to access the Memory Protection Unit (MPU). + /** \brief Structure type to access the Memory Protection Unit (MPU). */ -typedef struct -{ - __I uint32_t TYPE; /*!< Offset: 0x000 (R/ ) MPU Type Register */ - __IO uint32_t CTRL; /*!< Offset: 0x004 (R/W) MPU Control Register */ - __IO uint32_t RNR; /*!< Offset: 0x008 (R/W) MPU Region RNRber Register */ - __IO uint32_t RBAR; /*!< Offset: 0x00C (R/W) MPU Region Base Address Register */ - __IO uint32_t RASR; /*!< Offset: 0x010 (R/W) MPU Region Attribute and Size Register */ - __IO uint32_t RBAR_A1; /*!< Offset: 0x014 (R/W) MPU Alias 1 Region Base Address Register */ - __IO uint32_t RASR_A1; /*!< Offset: 0x018 (R/W) MPU Alias 1 Region Attribute and Size Register */ - __IO uint32_t RBAR_A2; /*!< Offset: 0x01C (R/W) MPU Alias 2 Region Base Address Register */ - __IO uint32_t RASR_A2; /*!< Offset: 0x020 (R/W) MPU Alias 2 Region Attribute and Size Register */ - __IO uint32_t RBAR_A3; /*!< Offset: 0x024 (R/W) MPU Alias 3 Region Base Address Register */ - __IO uint32_t RASR_A3; /*!< Offset: 0x028 (R/W) MPU Alias 3 Region Attribute and Size Register */ -} MPU_Type; + typedef struct + { + __I uint32_t TYPE; /*!< Offset: 0x000 (R/ ) MPU Type Register */ + __IO uint32_t CTRL; /*!< Offset: 0x004 (R/W) MPU Control Register */ + __IO uint32_t RNR; /*!< Offset: 0x008 (R/W) MPU Region RNRber Register */ + __IO uint32_t RBAR; /*!< Offset: 0x00C (R/W) MPU Region Base Address Register */ + __IO uint32_t RASR; /*!< Offset: 0x010 (R/W) MPU Region Attribute and Size Register */ + __IO uint32_t RBAR_A1; /*!< Offset: 0x014 (R/W) MPU Alias 1 Region Base Address Register */ + __IO uint32_t RASR_A1; /*!< Offset: 0x018 (R/W) MPU Alias 1 Region Attribute and Size Register */ + __IO uint32_t RBAR_A2; /*!< Offset: 0x01C (R/W) MPU Alias 2 Region Base Address Register */ + __IO uint32_t RASR_A2; /*!< Offset: 0x020 (R/W) MPU Alias 2 Region Attribute and Size Register */ + __IO uint32_t RBAR_A3; /*!< Offset: 0x024 (R/W) MPU Alias 3 Region Base Address Register */ + __IO uint32_t RASR_A3; /*!< Offset: 0x028 (R/W) MPU Alias 3 Region Attribute and Size Register */ + } MPU_Type; /* MPU Type Register */ -#define MPU_TYPE_IREGION_Pos 16 /*!< MPU TYPE: IREGION Position */ -#define MPU_TYPE_IREGION_Msk (0xFFUL << MPU_TYPE_IREGION_Pos) /*!< MPU TYPE: IREGION Mask */ +#define MPU_TYPE_IREGION_Pos 16 /*!< MPU TYPE: IREGION Position */ +#define MPU_TYPE_IREGION_Msk (0xFFUL << MPU_TYPE_IREGION_Pos) /*!< MPU TYPE: IREGION Mask */ -#define MPU_TYPE_DREGION_Pos 8 /*!< MPU TYPE: DREGION Position */ -#define MPU_TYPE_DREGION_Msk (0xFFUL << MPU_TYPE_DREGION_Pos) /*!< MPU TYPE: DREGION Mask */ +#define MPU_TYPE_DREGION_Pos 8 /*!< MPU TYPE: DREGION Position */ +#define MPU_TYPE_DREGION_Msk (0xFFUL << MPU_TYPE_DREGION_Pos) /*!< MPU TYPE: DREGION Mask */ -#define MPU_TYPE_SEPARATE_Pos 0 /*!< MPU TYPE: SEPARATE Position */ -#define MPU_TYPE_SEPARATE_Msk (1UL << MPU_TYPE_SEPARATE_Pos) /*!< MPU TYPE: SEPARATE Mask */ +#define MPU_TYPE_SEPARATE_Pos 0 /*!< MPU TYPE: SEPARATE Position */ +#define MPU_TYPE_SEPARATE_Msk (1UL << MPU_TYPE_SEPARATE_Pos) /*!< MPU TYPE: SEPARATE Mask */ /* MPU Control Register */ -#define MPU_CTRL_PRIVDEFENA_Pos 2 /*!< MPU CTRL: PRIVDEFENA Position */ -#define MPU_CTRL_PRIVDEFENA_Msk (1UL << MPU_CTRL_PRIVDEFENA_Pos) /*!< MPU CTRL: PRIVDEFENA Mask */ +#define MPU_CTRL_PRIVDEFENA_Pos 2 /*!< MPU CTRL: PRIVDEFENA Position */ +#define MPU_CTRL_PRIVDEFENA_Msk (1UL << MPU_CTRL_PRIVDEFENA_Pos) /*!< MPU CTRL: PRIVDEFENA Mask */ -#define MPU_CTRL_HFNMIENA_Pos 1 /*!< MPU CTRL: HFNMIENA Position */ -#define MPU_CTRL_HFNMIENA_Msk (1UL << MPU_CTRL_HFNMIENA_Pos) /*!< MPU CTRL: HFNMIENA Mask */ +#define MPU_CTRL_HFNMIENA_Pos 1 /*!< MPU CTRL: HFNMIENA Position */ +#define MPU_CTRL_HFNMIENA_Msk (1UL << MPU_CTRL_HFNMIENA_Pos) /*!< MPU CTRL: HFNMIENA Mask */ -#define MPU_CTRL_ENABLE_Pos 0 /*!< MPU CTRL: ENABLE Position */ -#define MPU_CTRL_ENABLE_Msk (1UL << MPU_CTRL_ENABLE_Pos) /*!< MPU CTRL: ENABLE Mask */ +#define MPU_CTRL_ENABLE_Pos 0 /*!< MPU CTRL: ENABLE Position */ +#define MPU_CTRL_ENABLE_Msk (1UL << MPU_CTRL_ENABLE_Pos) /*!< MPU CTRL: ENABLE Mask */ /* MPU Region Number Register */ -#define MPU_RNR_REGION_Pos 0 /*!< MPU RNR: REGION Position */ -#define MPU_RNR_REGION_Msk (0xFFUL << MPU_RNR_REGION_Pos) /*!< MPU RNR: REGION Mask */ +#define MPU_RNR_REGION_Pos 0 /*!< MPU RNR: REGION Position */ +#define MPU_RNR_REGION_Msk (0xFFUL << MPU_RNR_REGION_Pos) /*!< MPU RNR: REGION Mask */ /* MPU Region Base Address Register */ -#define MPU_RBAR_ADDR_Pos 5 /*!< MPU RBAR: ADDR Position */ -#define MPU_RBAR_ADDR_Msk (0x7FFFFFFUL << MPU_RBAR_ADDR_Pos) /*!< MPU RBAR: ADDR Mask */ +#define MPU_RBAR_ADDR_Pos 5 /*!< MPU RBAR: ADDR Position */ +#define MPU_RBAR_ADDR_Msk (0x7FFFFFFUL << MPU_RBAR_ADDR_Pos) /*!< MPU RBAR: ADDR Mask */ -#define MPU_RBAR_VALID_Pos 4 /*!< MPU RBAR: VALID Position */ -#define MPU_RBAR_VALID_Msk (1UL << MPU_RBAR_VALID_Pos) /*!< MPU RBAR: VALID Mask */ +#define MPU_RBAR_VALID_Pos 4 /*!< MPU RBAR: VALID Position */ +#define MPU_RBAR_VALID_Msk (1UL << MPU_RBAR_VALID_Pos) /*!< MPU RBAR: VALID Mask */ -#define MPU_RBAR_REGION_Pos 0 /*!< MPU RBAR: REGION Position */ -#define MPU_RBAR_REGION_Msk (0xFUL << MPU_RBAR_REGION_Pos) /*!< MPU RBAR: REGION Mask */ +#define MPU_RBAR_REGION_Pos 0 /*!< MPU RBAR: REGION Position */ +#define MPU_RBAR_REGION_Msk (0xFUL << MPU_RBAR_REGION_Pos) /*!< MPU RBAR: REGION Mask */ /* MPU Region Attribute and Size Register */ -#define MPU_RASR_ATTRS_Pos 16 /*!< MPU RASR: MPU Region Attribute field Position */ -#define MPU_RASR_ATTRS_Msk (0xFFFFUL << MPU_RASR_ATTRS_Pos) /*!< MPU RASR: MPU Region Attribute field Mask */ +#define MPU_RASR_ATTRS_Pos 16 /*!< MPU RASR: MPU Region Attribute field Position */ +#define MPU_RASR_ATTRS_Msk (0xFFFFUL << MPU_RASR_ATTRS_Pos) /*!< MPU RASR: MPU Region Attribute field Mask */ -#define MPU_RASR_XN_Pos 28 /*!< MPU RASR: ATTRS.XN Position */ -#define MPU_RASR_XN_Msk (1UL << MPU_RASR_XN_Pos) /*!< MPU RASR: ATTRS.XN Mask */ +#define MPU_RASR_XN_Pos 28 /*!< MPU RASR: ATTRS.XN Position */ +#define MPU_RASR_XN_Msk (1UL << MPU_RASR_XN_Pos) /*!< MPU RASR: ATTRS.XN Mask */ -#define MPU_RASR_AP_Pos 24 /*!< MPU RASR: ATTRS.AP Position */ -#define MPU_RASR_AP_Msk (0x7UL << MPU_RASR_AP_Pos) /*!< MPU RASR: ATTRS.AP Mask */ +#define MPU_RASR_AP_Pos 24 /*!< MPU RASR: ATTRS.AP Position */ +#define MPU_RASR_AP_Msk (0x7UL << MPU_RASR_AP_Pos) /*!< MPU RASR: ATTRS.AP Mask */ -#define MPU_RASR_TEX_Pos 19 /*!< MPU RASR: ATTRS.TEX Position */ -#define MPU_RASR_TEX_Msk (0x7UL << MPU_RASR_TEX_Pos) /*!< MPU RASR: ATTRS.TEX Mask */ +#define MPU_RASR_TEX_Pos 19 /*!< MPU RASR: ATTRS.TEX Position */ +#define MPU_RASR_TEX_Msk (0x7UL << MPU_RASR_TEX_Pos) /*!< MPU RASR: ATTRS.TEX Mask */ -#define MPU_RASR_S_Pos 18 /*!< MPU RASR: ATTRS.S Position */ -#define MPU_RASR_S_Msk (1UL << MPU_RASR_S_Pos) /*!< MPU RASR: ATTRS.S Mask */ +#define MPU_RASR_S_Pos 18 /*!< MPU RASR: ATTRS.S Position */ +#define MPU_RASR_S_Msk (1UL << MPU_RASR_S_Pos) /*!< MPU RASR: ATTRS.S Mask */ -#define MPU_RASR_C_Pos 17 /*!< MPU RASR: ATTRS.C Position */ -#define MPU_RASR_C_Msk (1UL << MPU_RASR_C_Pos) /*!< MPU RASR: ATTRS.C Mask */ +#define MPU_RASR_C_Pos 17 /*!< MPU RASR: ATTRS.C Position */ +#define MPU_RASR_C_Msk (1UL << MPU_RASR_C_Pos) /*!< MPU RASR: ATTRS.C Mask */ -#define MPU_RASR_B_Pos 16 /*!< MPU RASR: ATTRS.B Position */ -#define MPU_RASR_B_Msk (1UL << MPU_RASR_B_Pos) /*!< MPU RASR: ATTRS.B Mask */ +#define MPU_RASR_B_Pos 16 /*!< MPU RASR: ATTRS.B Position */ +#define MPU_RASR_B_Msk (1UL << MPU_RASR_B_Pos) /*!< MPU RASR: ATTRS.B Mask */ -#define MPU_RASR_SRD_Pos 8 /*!< MPU RASR: Sub-Region Disable Position */ -#define MPU_RASR_SRD_Msk (0xFFUL << MPU_RASR_SRD_Pos) /*!< MPU RASR: Sub-Region Disable Mask */ +#define MPU_RASR_SRD_Pos 8 /*!< MPU RASR: Sub-Region Disable Position */ +#define MPU_RASR_SRD_Msk (0xFFUL << MPU_RASR_SRD_Pos) /*!< MPU RASR: Sub-Region Disable Mask */ -#define MPU_RASR_SIZE_Pos 1 /*!< MPU RASR: Region Size Field Position */ -#define MPU_RASR_SIZE_Msk (0x1FUL << MPU_RASR_SIZE_Pos) /*!< MPU RASR: Region Size Field Mask */ +#define MPU_RASR_SIZE_Pos 1 /*!< MPU RASR: Region Size Field Position */ +#define MPU_RASR_SIZE_Msk (0x1FUL << MPU_RASR_SIZE_Pos) /*!< MPU RASR: Region Size Field Mask */ -#define MPU_RASR_ENABLE_Pos 0 /*!< MPU RASR: Region enable bit Position */ -#define MPU_RASR_ENABLE_Msk (1UL << MPU_RASR_ENABLE_Pos) /*!< MPU RASR: Region enable bit Disable Mask */ +#define MPU_RASR_ENABLE_Pos 0 /*!< MPU RASR: Region enable bit Position */ +#define MPU_RASR_ENABLE_Msk (1UL << MPU_RASR_ENABLE_Pos) /*!< MPU RASR: Region enable bit Disable Mask */ /*@} end of group CMSIS_MPU */ #endif - #if (__FPU_PRESENT == 1) -/** \ingroup CMSIS_core_register + /** \ingroup CMSIS_core_register \defgroup CMSIS_FPU Floating Point Unit (FPU) \brief Type definitions for the Floating Point Unit (FPU) @{ */ -/** \brief Structure type to access the Floating Point Unit (FPU). + /** \brief Structure type to access the Floating Point Unit (FPU). */ -typedef struct -{ - uint32_t RESERVED0[1]; - __IO uint32_t FPCCR; /*!< Offset: 0x004 (R/W) Floating-Point Context Control Register */ - __IO uint32_t FPCAR; /*!< Offset: 0x008 (R/W) Floating-Point Context Address Register */ - __IO uint32_t FPDSCR; /*!< Offset: 0x00C (R/W) Floating-Point Default Status Control Register */ - __I uint32_t MVFR0; /*!< Offset: 0x010 (R/ ) Media and FP Feature Register 0 */ - __I uint32_t MVFR1; /*!< Offset: 0x014 (R/ ) Media and FP Feature Register 1 */ - __I uint32_t MVFR2; /*!< Offset: 0x018 (R/ ) Media and FP Feature Register 2 */ -} FPU_Type; + typedef struct + { + uint32_t RESERVED0[1]; + __IO uint32_t FPCCR; /*!< Offset: 0x004 (R/W) Floating-Point Context Control Register */ + __IO uint32_t FPCAR; /*!< Offset: 0x008 (R/W) Floating-Point Context Address Register */ + __IO uint32_t FPDSCR; /*!< Offset: 0x00C (R/W) Floating-Point Default Status Control Register */ + __I uint32_t MVFR0; /*!< Offset: 0x010 (R/ ) Media and FP Feature Register 0 */ + __I uint32_t MVFR1; /*!< Offset: 0x014 (R/ ) Media and FP Feature Register 1 */ + __I uint32_t MVFR2; /*!< Offset: 0x018 (R/ ) Media and FP Feature Register 2 */ + } FPU_Type; /* Floating-Point Context Control Register */ -#define FPU_FPCCR_ASPEN_Pos 31 /*!< FPCCR: ASPEN bit Position */ -#define FPU_FPCCR_ASPEN_Msk (1UL << FPU_FPCCR_ASPEN_Pos) /*!< FPCCR: ASPEN bit Mask */ +#define FPU_FPCCR_ASPEN_Pos 31 /*!< FPCCR: ASPEN bit Position */ +#define FPU_FPCCR_ASPEN_Msk (1UL << FPU_FPCCR_ASPEN_Pos) /*!< FPCCR: ASPEN bit Mask */ -#define FPU_FPCCR_LSPEN_Pos 30 /*!< FPCCR: LSPEN Position */ -#define FPU_FPCCR_LSPEN_Msk (1UL << FPU_FPCCR_LSPEN_Pos) /*!< FPCCR: LSPEN bit Mask */ +#define FPU_FPCCR_LSPEN_Pos 30 /*!< FPCCR: LSPEN Position */ +#define FPU_FPCCR_LSPEN_Msk (1UL << FPU_FPCCR_LSPEN_Pos) /*!< FPCCR: LSPEN bit Mask */ -#define FPU_FPCCR_MONRDY_Pos 8 /*!< FPCCR: MONRDY Position */ -#define FPU_FPCCR_MONRDY_Msk (1UL << FPU_FPCCR_MONRDY_Pos) /*!< FPCCR: MONRDY bit Mask */ +#define FPU_FPCCR_MONRDY_Pos 8 /*!< FPCCR: MONRDY Position */ +#define FPU_FPCCR_MONRDY_Msk (1UL << FPU_FPCCR_MONRDY_Pos) /*!< FPCCR: MONRDY bit Mask */ -#define FPU_FPCCR_BFRDY_Pos 6 /*!< FPCCR: BFRDY Position */ -#define FPU_FPCCR_BFRDY_Msk (1UL << FPU_FPCCR_BFRDY_Pos) /*!< FPCCR: BFRDY bit Mask */ +#define FPU_FPCCR_BFRDY_Pos 6 /*!< FPCCR: BFRDY Position */ +#define FPU_FPCCR_BFRDY_Msk (1UL << FPU_FPCCR_BFRDY_Pos) /*!< FPCCR: BFRDY bit Mask */ -#define FPU_FPCCR_MMRDY_Pos 5 /*!< FPCCR: MMRDY Position */ -#define FPU_FPCCR_MMRDY_Msk (1UL << FPU_FPCCR_MMRDY_Pos) /*!< FPCCR: MMRDY bit Mask */ +#define FPU_FPCCR_MMRDY_Pos 5 /*!< FPCCR: MMRDY Position */ +#define FPU_FPCCR_MMRDY_Msk (1UL << FPU_FPCCR_MMRDY_Pos) /*!< FPCCR: MMRDY bit Mask */ -#define FPU_FPCCR_HFRDY_Pos 4 /*!< FPCCR: HFRDY Position */ -#define FPU_FPCCR_HFRDY_Msk (1UL << FPU_FPCCR_HFRDY_Pos) /*!< FPCCR: HFRDY bit Mask */ +#define FPU_FPCCR_HFRDY_Pos 4 /*!< FPCCR: HFRDY Position */ +#define FPU_FPCCR_HFRDY_Msk (1UL << FPU_FPCCR_HFRDY_Pos) /*!< FPCCR: HFRDY bit Mask */ -#define FPU_FPCCR_THREAD_Pos 3 /*!< FPCCR: processor mode bit Position */ -#define FPU_FPCCR_THREAD_Msk (1UL << FPU_FPCCR_THREAD_Pos) /*!< FPCCR: processor mode active bit Mask */ +#define FPU_FPCCR_THREAD_Pos 3 /*!< FPCCR: processor mode bit Position */ +#define FPU_FPCCR_THREAD_Msk (1UL << FPU_FPCCR_THREAD_Pos) /*!< FPCCR: processor mode active bit Mask */ -#define FPU_FPCCR_USER_Pos 1 /*!< FPCCR: privilege level bit Position */ -#define FPU_FPCCR_USER_Msk (1UL << FPU_FPCCR_USER_Pos) /*!< FPCCR: privilege level bit Mask */ +#define FPU_FPCCR_USER_Pos 1 /*!< FPCCR: privilege level bit Position */ +#define FPU_FPCCR_USER_Msk (1UL << FPU_FPCCR_USER_Pos) /*!< FPCCR: privilege level bit Mask */ -#define FPU_FPCCR_LSPACT_Pos 0 /*!< FPCCR: Lazy state preservation active bit Position */ -#define FPU_FPCCR_LSPACT_Msk (1UL << FPU_FPCCR_LSPACT_Pos) /*!< FPCCR: Lazy state preservation active bit Mask */ +#define FPU_FPCCR_LSPACT_Pos 0 /*!< FPCCR: Lazy state preservation active bit Position */ +#define FPU_FPCCR_LSPACT_Msk (1UL << FPU_FPCCR_LSPACT_Pos) /*!< FPCCR: Lazy state preservation active bit Mask */ /* Floating-Point Context Address Register */ -#define FPU_FPCAR_ADDRESS_Pos 3 /*!< FPCAR: ADDRESS bit Position */ -#define FPU_FPCAR_ADDRESS_Msk (0x1FFFFFFFUL << FPU_FPCAR_ADDRESS_Pos) /*!< FPCAR: ADDRESS bit Mask */ +#define FPU_FPCAR_ADDRESS_Pos 3 /*!< FPCAR: ADDRESS bit Position */ +#define FPU_FPCAR_ADDRESS_Msk (0x1FFFFFFFUL << FPU_FPCAR_ADDRESS_Pos) /*!< FPCAR: ADDRESS bit Mask */ /* Floating-Point Default Status Control Register */ -#define FPU_FPDSCR_AHP_Pos 26 /*!< FPDSCR: AHP bit Position */ -#define FPU_FPDSCR_AHP_Msk (1UL << FPU_FPDSCR_AHP_Pos) /*!< FPDSCR: AHP bit Mask */ +#define FPU_FPDSCR_AHP_Pos 26 /*!< FPDSCR: AHP bit Position */ +#define FPU_FPDSCR_AHP_Msk (1UL << FPU_FPDSCR_AHP_Pos) /*!< FPDSCR: AHP bit Mask */ -#define FPU_FPDSCR_DN_Pos 25 /*!< FPDSCR: DN bit Position */ -#define FPU_FPDSCR_DN_Msk (1UL << FPU_FPDSCR_DN_Pos) /*!< FPDSCR: DN bit Mask */ +#define FPU_FPDSCR_DN_Pos 25 /*!< FPDSCR: DN bit Position */ +#define FPU_FPDSCR_DN_Msk (1UL << FPU_FPDSCR_DN_Pos) /*!< FPDSCR: DN bit Mask */ -#define FPU_FPDSCR_FZ_Pos 24 /*!< FPDSCR: FZ bit Position */ -#define FPU_FPDSCR_FZ_Msk (1UL << FPU_FPDSCR_FZ_Pos) /*!< FPDSCR: FZ bit Mask */ +#define FPU_FPDSCR_FZ_Pos 24 /*!< FPDSCR: FZ bit Position */ +#define FPU_FPDSCR_FZ_Msk (1UL << FPU_FPDSCR_FZ_Pos) /*!< FPDSCR: FZ bit Mask */ -#define FPU_FPDSCR_RMode_Pos 22 /*!< FPDSCR: RMode bit Position */ -#define FPU_FPDSCR_RMode_Msk (3UL << FPU_FPDSCR_RMode_Pos) /*!< FPDSCR: RMode bit Mask */ +#define FPU_FPDSCR_RMode_Pos 22 /*!< FPDSCR: RMode bit Position */ +#define FPU_FPDSCR_RMode_Msk (3UL << FPU_FPDSCR_RMode_Pos) /*!< FPDSCR: RMode bit Mask */ /* Media and FP Feature Register 0 */ -#define FPU_MVFR0_FP_rounding_modes_Pos 28 /*!< MVFR0: FP rounding modes bits Position */ -#define FPU_MVFR0_FP_rounding_modes_Msk (0xFUL << FPU_MVFR0_FP_rounding_modes_Pos) /*!< MVFR0: FP rounding modes bits Mask */ +#define FPU_MVFR0_FP_rounding_modes_Pos 28 /*!< MVFR0: FP rounding modes bits Position */ +#define FPU_MVFR0_FP_rounding_modes_Msk (0xFUL << FPU_MVFR0_FP_rounding_modes_Pos) /*!< MVFR0: FP rounding modes bits Mask */ -#define FPU_MVFR0_Short_vectors_Pos 24 /*!< MVFR0: Short vectors bits Position */ -#define FPU_MVFR0_Short_vectors_Msk (0xFUL << FPU_MVFR0_Short_vectors_Pos) /*!< MVFR0: Short vectors bits Mask */ +#define FPU_MVFR0_Short_vectors_Pos 24 /*!< MVFR0: Short vectors bits Position */ +#define FPU_MVFR0_Short_vectors_Msk (0xFUL << FPU_MVFR0_Short_vectors_Pos) /*!< MVFR0: Short vectors bits Mask */ -#define FPU_MVFR0_Square_root_Pos 20 /*!< MVFR0: Square root bits Position */ -#define FPU_MVFR0_Square_root_Msk (0xFUL << FPU_MVFR0_Square_root_Pos) /*!< MVFR0: Square root bits Mask */ +#define FPU_MVFR0_Square_root_Pos 20 /*!< MVFR0: Square root bits Position */ +#define FPU_MVFR0_Square_root_Msk (0xFUL << FPU_MVFR0_Square_root_Pos) /*!< MVFR0: Square root bits Mask */ -#define FPU_MVFR0_Divide_Pos 16 /*!< MVFR0: Divide bits Position */ -#define FPU_MVFR0_Divide_Msk (0xFUL << FPU_MVFR0_Divide_Pos) /*!< MVFR0: Divide bits Mask */ +#define FPU_MVFR0_Divide_Pos 16 /*!< MVFR0: Divide bits Position */ +#define FPU_MVFR0_Divide_Msk (0xFUL << FPU_MVFR0_Divide_Pos) /*!< MVFR0: Divide bits Mask */ -#define FPU_MVFR0_FP_excep_trapping_Pos 12 /*!< MVFR0: FP exception trapping bits Position */ -#define FPU_MVFR0_FP_excep_trapping_Msk (0xFUL << FPU_MVFR0_FP_excep_trapping_Pos) /*!< MVFR0: FP exception trapping bits Mask */ +#define FPU_MVFR0_FP_excep_trapping_Pos 12 /*!< MVFR0: FP exception trapping bits Position */ +#define FPU_MVFR0_FP_excep_trapping_Msk (0xFUL << FPU_MVFR0_FP_excep_trapping_Pos) /*!< MVFR0: FP exception trapping bits Mask */ -#define FPU_MVFR0_Double_precision_Pos 8 /*!< MVFR0: Double-precision bits Position */ -#define FPU_MVFR0_Double_precision_Msk (0xFUL << FPU_MVFR0_Double_precision_Pos) /*!< MVFR0: Double-precision bits Mask */ +#define FPU_MVFR0_Double_precision_Pos 8 /*!< MVFR0: Double-precision bits Position */ +#define FPU_MVFR0_Double_precision_Msk (0xFUL << FPU_MVFR0_Double_precision_Pos) /*!< MVFR0: Double-precision bits Mask */ -#define FPU_MVFR0_Single_precision_Pos 4 /*!< MVFR0: Single-precision bits Position */ -#define FPU_MVFR0_Single_precision_Msk (0xFUL << FPU_MVFR0_Single_precision_Pos) /*!< MVFR0: Single-precision bits Mask */ +#define FPU_MVFR0_Single_precision_Pos 4 /*!< MVFR0: Single-precision bits Position */ +#define FPU_MVFR0_Single_precision_Msk (0xFUL << FPU_MVFR0_Single_precision_Pos) /*!< MVFR0: Single-precision bits Mask */ -#define FPU_MVFR0_A_SIMD_registers_Pos 0 /*!< MVFR0: A_SIMD registers bits Position */ -#define FPU_MVFR0_A_SIMD_registers_Msk (0xFUL << FPU_MVFR0_A_SIMD_registers_Pos) /*!< MVFR0: A_SIMD registers bits Mask */ +#define FPU_MVFR0_A_SIMD_registers_Pos 0 /*!< MVFR0: A_SIMD registers bits Position */ +#define FPU_MVFR0_A_SIMD_registers_Msk (0xFUL << FPU_MVFR0_A_SIMD_registers_Pos) /*!< MVFR0: A_SIMD registers bits Mask */ /* Media and FP Feature Register 1 */ -#define FPU_MVFR1_FP_fused_MAC_Pos 28 /*!< MVFR1: FP fused MAC bits Position */ -#define FPU_MVFR1_FP_fused_MAC_Msk (0xFUL << FPU_MVFR1_FP_fused_MAC_Pos) /*!< MVFR1: FP fused MAC bits Mask */ +#define FPU_MVFR1_FP_fused_MAC_Pos 28 /*!< MVFR1: FP fused MAC bits Position */ +#define FPU_MVFR1_FP_fused_MAC_Msk (0xFUL << FPU_MVFR1_FP_fused_MAC_Pos) /*!< MVFR1: FP fused MAC bits Mask */ -#define FPU_MVFR1_FP_HPFP_Pos 24 /*!< MVFR1: FP HPFP bits Position */ -#define FPU_MVFR1_FP_HPFP_Msk (0xFUL << FPU_MVFR1_FP_HPFP_Pos) /*!< MVFR1: FP HPFP bits Mask */ +#define FPU_MVFR1_FP_HPFP_Pos 24 /*!< MVFR1: FP HPFP bits Position */ +#define FPU_MVFR1_FP_HPFP_Msk (0xFUL << FPU_MVFR1_FP_HPFP_Pos) /*!< MVFR1: FP HPFP bits Mask */ -#define FPU_MVFR1_D_NaN_mode_Pos 4 /*!< MVFR1: D_NaN mode bits Position */ -#define FPU_MVFR1_D_NaN_mode_Msk (0xFUL << FPU_MVFR1_D_NaN_mode_Pos) /*!< MVFR1: D_NaN mode bits Mask */ +#define FPU_MVFR1_D_NaN_mode_Pos 4 /*!< MVFR1: D_NaN mode bits Position */ +#define FPU_MVFR1_D_NaN_mode_Msk (0xFUL << FPU_MVFR1_D_NaN_mode_Pos) /*!< MVFR1: D_NaN mode bits Mask */ -#define FPU_MVFR1_FtZ_mode_Pos 0 /*!< MVFR1: FtZ mode bits Position */ -#define FPU_MVFR1_FtZ_mode_Msk (0xFUL << FPU_MVFR1_FtZ_mode_Pos) /*!< MVFR1: FtZ mode bits Mask */ +#define FPU_MVFR1_FtZ_mode_Pos 0 /*!< MVFR1: FtZ mode bits Position */ +#define FPU_MVFR1_FtZ_mode_Msk (0xFUL << FPU_MVFR1_FtZ_mode_Pos) /*!< MVFR1: FtZ mode bits Mask */ /* Media and FP Feature Register 2 */ /*@} end of group CMSIS_FPU */ #endif - -/** \ingroup CMSIS_core_register + /** \ingroup CMSIS_core_register \defgroup CMSIS_CoreDebug Core Debug Registers (CoreDebug) \brief Type definitions for the Core Debug Registers @{ */ -/** \brief Structure type to access the Core Debug Register (CoreDebug). + /** \brief Structure type to access the Core Debug Register (CoreDebug). */ -typedef struct -{ - __IO uint32_t DHCSR; /*!< Offset: 0x000 (R/W) Debug Halting Control and Status Register */ - __O uint32_t DCRSR; /*!< Offset: 0x004 ( /W) Debug Core Register Selector Register */ - __IO uint32_t DCRDR; /*!< Offset: 0x008 (R/W) Debug Core Register Data Register */ - __IO uint32_t DEMCR; /*!< Offset: 0x00C (R/W) Debug Exception and Monitor Control Register */ -} CoreDebug_Type; + typedef struct + { + __IO uint32_t DHCSR; /*!< Offset: 0x000 (R/W) Debug Halting Control and Status Register */ + __O uint32_t DCRSR; /*!< Offset: 0x004 ( /W) Debug Core Register Selector Register */ + __IO uint32_t DCRDR; /*!< Offset: 0x008 (R/W) Debug Core Register Data Register */ + __IO uint32_t DEMCR; /*!< Offset: 0x00C (R/W) Debug Exception and Monitor Control Register */ + } CoreDebug_Type; /* Debug Halting Control and Status Register */ -#define CoreDebug_DHCSR_DBGKEY_Pos 16 /*!< CoreDebug DHCSR: DBGKEY Position */ -#define CoreDebug_DHCSR_DBGKEY_Msk (0xFFFFUL << CoreDebug_DHCSR_DBGKEY_Pos) /*!< CoreDebug DHCSR: DBGKEY Mask */ +#define CoreDebug_DHCSR_DBGKEY_Pos 16 /*!< CoreDebug DHCSR: DBGKEY Position */ +#define CoreDebug_DHCSR_DBGKEY_Msk (0xFFFFUL << CoreDebug_DHCSR_DBGKEY_Pos) /*!< CoreDebug DHCSR: DBGKEY Mask */ -#define CoreDebug_DHCSR_S_RESET_ST_Pos 25 /*!< CoreDebug DHCSR: S_RESET_ST Position */ -#define CoreDebug_DHCSR_S_RESET_ST_Msk (1UL << CoreDebug_DHCSR_S_RESET_ST_Pos) /*!< CoreDebug DHCSR: S_RESET_ST Mask */ +#define CoreDebug_DHCSR_S_RESET_ST_Pos 25 /*!< CoreDebug DHCSR: S_RESET_ST Position */ +#define CoreDebug_DHCSR_S_RESET_ST_Msk (1UL << CoreDebug_DHCSR_S_RESET_ST_Pos) /*!< CoreDebug DHCSR: S_RESET_ST Mask */ -#define CoreDebug_DHCSR_S_RETIRE_ST_Pos 24 /*!< CoreDebug DHCSR: S_RETIRE_ST Position */ -#define CoreDebug_DHCSR_S_RETIRE_ST_Msk (1UL << CoreDebug_DHCSR_S_RETIRE_ST_Pos) /*!< CoreDebug DHCSR: S_RETIRE_ST Mask */ +#define CoreDebug_DHCSR_S_RETIRE_ST_Pos 24 /*!< CoreDebug DHCSR: S_RETIRE_ST Position */ +#define CoreDebug_DHCSR_S_RETIRE_ST_Msk (1UL << CoreDebug_DHCSR_S_RETIRE_ST_Pos) /*!< CoreDebug DHCSR: S_RETIRE_ST Mask */ -#define CoreDebug_DHCSR_S_LOCKUP_Pos 19 /*!< CoreDebug DHCSR: S_LOCKUP Position */ -#define CoreDebug_DHCSR_S_LOCKUP_Msk (1UL << CoreDebug_DHCSR_S_LOCKUP_Pos) /*!< CoreDebug DHCSR: S_LOCKUP Mask */ +#define CoreDebug_DHCSR_S_LOCKUP_Pos 19 /*!< CoreDebug DHCSR: S_LOCKUP Position */ +#define CoreDebug_DHCSR_S_LOCKUP_Msk (1UL << CoreDebug_DHCSR_S_LOCKUP_Pos) /*!< CoreDebug DHCSR: S_LOCKUP Mask */ -#define CoreDebug_DHCSR_S_SLEEP_Pos 18 /*!< CoreDebug DHCSR: S_SLEEP Position */ -#define CoreDebug_DHCSR_S_SLEEP_Msk (1UL << CoreDebug_DHCSR_S_SLEEP_Pos) /*!< CoreDebug DHCSR: S_SLEEP Mask */ +#define CoreDebug_DHCSR_S_SLEEP_Pos 18 /*!< CoreDebug DHCSR: S_SLEEP Position */ +#define CoreDebug_DHCSR_S_SLEEP_Msk (1UL << CoreDebug_DHCSR_S_SLEEP_Pos) /*!< CoreDebug DHCSR: S_SLEEP Mask */ -#define CoreDebug_DHCSR_S_HALT_Pos 17 /*!< CoreDebug DHCSR: S_HALT Position */ -#define CoreDebug_DHCSR_S_HALT_Msk (1UL << CoreDebug_DHCSR_S_HALT_Pos) /*!< CoreDebug DHCSR: S_HALT Mask */ +#define CoreDebug_DHCSR_S_HALT_Pos 17 /*!< CoreDebug DHCSR: S_HALT Position */ +#define CoreDebug_DHCSR_S_HALT_Msk (1UL << CoreDebug_DHCSR_S_HALT_Pos) /*!< CoreDebug DHCSR: S_HALT Mask */ -#define CoreDebug_DHCSR_S_REGRDY_Pos 16 /*!< CoreDebug DHCSR: S_REGRDY Position */ -#define CoreDebug_DHCSR_S_REGRDY_Msk (1UL << CoreDebug_DHCSR_S_REGRDY_Pos) /*!< CoreDebug DHCSR: S_REGRDY Mask */ +#define CoreDebug_DHCSR_S_REGRDY_Pos 16 /*!< CoreDebug DHCSR: S_REGRDY Position */ +#define CoreDebug_DHCSR_S_REGRDY_Msk (1UL << CoreDebug_DHCSR_S_REGRDY_Pos) /*!< CoreDebug DHCSR: S_REGRDY Mask */ -#define CoreDebug_DHCSR_C_SNAPSTALL_Pos 5 /*!< CoreDebug DHCSR: C_SNAPSTALL Position */ -#define CoreDebug_DHCSR_C_SNAPSTALL_Msk (1UL << CoreDebug_DHCSR_C_SNAPSTALL_Pos) /*!< CoreDebug DHCSR: C_SNAPSTALL Mask */ +#define CoreDebug_DHCSR_C_SNAPSTALL_Pos 5 /*!< CoreDebug DHCSR: C_SNAPSTALL Position */ +#define CoreDebug_DHCSR_C_SNAPSTALL_Msk (1UL << CoreDebug_DHCSR_C_SNAPSTALL_Pos) /*!< CoreDebug DHCSR: C_SNAPSTALL Mask */ -#define CoreDebug_DHCSR_C_MASKINTS_Pos 3 /*!< CoreDebug DHCSR: C_MASKINTS Position */ -#define CoreDebug_DHCSR_C_MASKINTS_Msk (1UL << CoreDebug_DHCSR_C_MASKINTS_Pos) /*!< CoreDebug DHCSR: C_MASKINTS Mask */ +#define CoreDebug_DHCSR_C_MASKINTS_Pos 3 /*!< CoreDebug DHCSR: C_MASKINTS Position */ +#define CoreDebug_DHCSR_C_MASKINTS_Msk (1UL << CoreDebug_DHCSR_C_MASKINTS_Pos) /*!< CoreDebug DHCSR: C_MASKINTS Mask */ -#define CoreDebug_DHCSR_C_STEP_Pos 2 /*!< CoreDebug DHCSR: C_STEP Position */ -#define CoreDebug_DHCSR_C_STEP_Msk (1UL << CoreDebug_DHCSR_C_STEP_Pos) /*!< CoreDebug DHCSR: C_STEP Mask */ +#define CoreDebug_DHCSR_C_STEP_Pos 2 /*!< CoreDebug DHCSR: C_STEP Position */ +#define CoreDebug_DHCSR_C_STEP_Msk (1UL << CoreDebug_DHCSR_C_STEP_Pos) /*!< CoreDebug DHCSR: C_STEP Mask */ -#define CoreDebug_DHCSR_C_HALT_Pos 1 /*!< CoreDebug DHCSR: C_HALT Position */ -#define CoreDebug_DHCSR_C_HALT_Msk (1UL << CoreDebug_DHCSR_C_HALT_Pos) /*!< CoreDebug DHCSR: C_HALT Mask */ +#define CoreDebug_DHCSR_C_HALT_Pos 1 /*!< CoreDebug DHCSR: C_HALT Position */ +#define CoreDebug_DHCSR_C_HALT_Msk (1UL << CoreDebug_DHCSR_C_HALT_Pos) /*!< CoreDebug DHCSR: C_HALT Mask */ -#define CoreDebug_DHCSR_C_DEBUGEN_Pos 0 /*!< CoreDebug DHCSR: C_DEBUGEN Position */ -#define CoreDebug_DHCSR_C_DEBUGEN_Msk (1UL << CoreDebug_DHCSR_C_DEBUGEN_Pos) /*!< CoreDebug DHCSR: C_DEBUGEN Mask */ +#define CoreDebug_DHCSR_C_DEBUGEN_Pos 0 /*!< CoreDebug DHCSR: C_DEBUGEN Position */ +#define CoreDebug_DHCSR_C_DEBUGEN_Msk (1UL << CoreDebug_DHCSR_C_DEBUGEN_Pos) /*!< CoreDebug DHCSR: C_DEBUGEN Mask */ /* Debug Core Register Selector Register */ -#define CoreDebug_DCRSR_REGWnR_Pos 16 /*!< CoreDebug DCRSR: REGWnR Position */ -#define CoreDebug_DCRSR_REGWnR_Msk (1UL << CoreDebug_DCRSR_REGWnR_Pos) /*!< CoreDebug DCRSR: REGWnR Mask */ +#define CoreDebug_DCRSR_REGWnR_Pos 16 /*!< CoreDebug DCRSR: REGWnR Position */ +#define CoreDebug_DCRSR_REGWnR_Msk (1UL << CoreDebug_DCRSR_REGWnR_Pos) /*!< CoreDebug DCRSR: REGWnR Mask */ -#define CoreDebug_DCRSR_REGSEL_Pos 0 /*!< CoreDebug DCRSR: REGSEL Position */ -#define CoreDebug_DCRSR_REGSEL_Msk (0x1FUL << CoreDebug_DCRSR_REGSEL_Pos) /*!< CoreDebug DCRSR: REGSEL Mask */ +#define CoreDebug_DCRSR_REGSEL_Pos 0 /*!< CoreDebug DCRSR: REGSEL Position */ +#define CoreDebug_DCRSR_REGSEL_Msk (0x1FUL << CoreDebug_DCRSR_REGSEL_Pos) /*!< CoreDebug DCRSR: REGSEL Mask */ /* Debug Exception and Monitor Control Register */ -#define CoreDebug_DEMCR_TRCENA_Pos 24 /*!< CoreDebug DEMCR: TRCENA Position */ -#define CoreDebug_DEMCR_TRCENA_Msk (1UL << CoreDebug_DEMCR_TRCENA_Pos) /*!< CoreDebug DEMCR: TRCENA Mask */ +#define CoreDebug_DEMCR_TRCENA_Pos 24 /*!< CoreDebug DEMCR: TRCENA Position */ +#define CoreDebug_DEMCR_TRCENA_Msk (1UL << CoreDebug_DEMCR_TRCENA_Pos) /*!< CoreDebug DEMCR: TRCENA Mask */ -#define CoreDebug_DEMCR_MON_REQ_Pos 19 /*!< CoreDebug DEMCR: MON_REQ Position */ -#define CoreDebug_DEMCR_MON_REQ_Msk (1UL << CoreDebug_DEMCR_MON_REQ_Pos) /*!< CoreDebug DEMCR: MON_REQ Mask */ +#define CoreDebug_DEMCR_MON_REQ_Pos 19 /*!< CoreDebug DEMCR: MON_REQ Position */ +#define CoreDebug_DEMCR_MON_REQ_Msk (1UL << CoreDebug_DEMCR_MON_REQ_Pos) /*!< CoreDebug DEMCR: MON_REQ Mask */ -#define CoreDebug_DEMCR_MON_STEP_Pos 18 /*!< CoreDebug DEMCR: MON_STEP Position */ -#define CoreDebug_DEMCR_MON_STEP_Msk (1UL << CoreDebug_DEMCR_MON_STEP_Pos) /*!< CoreDebug DEMCR: MON_STEP Mask */ +#define CoreDebug_DEMCR_MON_STEP_Pos 18 /*!< CoreDebug DEMCR: MON_STEP Position */ +#define CoreDebug_DEMCR_MON_STEP_Msk (1UL << CoreDebug_DEMCR_MON_STEP_Pos) /*!< CoreDebug DEMCR: MON_STEP Mask */ -#define CoreDebug_DEMCR_MON_PEND_Pos 17 /*!< CoreDebug DEMCR: MON_PEND Position */ -#define CoreDebug_DEMCR_MON_PEND_Msk (1UL << CoreDebug_DEMCR_MON_PEND_Pos) /*!< CoreDebug DEMCR: MON_PEND Mask */ +#define CoreDebug_DEMCR_MON_PEND_Pos 17 /*!< CoreDebug DEMCR: MON_PEND Position */ +#define CoreDebug_DEMCR_MON_PEND_Msk (1UL << CoreDebug_DEMCR_MON_PEND_Pos) /*!< CoreDebug DEMCR: MON_PEND Mask */ -#define CoreDebug_DEMCR_MON_EN_Pos 16 /*!< CoreDebug DEMCR: MON_EN Position */ -#define CoreDebug_DEMCR_MON_EN_Msk (1UL << CoreDebug_DEMCR_MON_EN_Pos) /*!< CoreDebug DEMCR: MON_EN Mask */ +#define CoreDebug_DEMCR_MON_EN_Pos 16 /*!< CoreDebug DEMCR: MON_EN Position */ +#define CoreDebug_DEMCR_MON_EN_Msk (1UL << CoreDebug_DEMCR_MON_EN_Pos) /*!< CoreDebug DEMCR: MON_EN Mask */ -#define CoreDebug_DEMCR_VC_HARDERR_Pos 10 /*!< CoreDebug DEMCR: VC_HARDERR Position */ -#define CoreDebug_DEMCR_VC_HARDERR_Msk (1UL << CoreDebug_DEMCR_VC_HARDERR_Pos) /*!< CoreDebug DEMCR: VC_HARDERR Mask */ +#define CoreDebug_DEMCR_VC_HARDERR_Pos 10 /*!< CoreDebug DEMCR: VC_HARDERR Position */ +#define CoreDebug_DEMCR_VC_HARDERR_Msk (1UL << CoreDebug_DEMCR_VC_HARDERR_Pos) /*!< CoreDebug DEMCR: VC_HARDERR Mask */ -#define CoreDebug_DEMCR_VC_INTERR_Pos 9 /*!< CoreDebug DEMCR: VC_INTERR Position */ -#define CoreDebug_DEMCR_VC_INTERR_Msk (1UL << CoreDebug_DEMCR_VC_INTERR_Pos) /*!< CoreDebug DEMCR: VC_INTERR Mask */ +#define CoreDebug_DEMCR_VC_INTERR_Pos 9 /*!< CoreDebug DEMCR: VC_INTERR Position */ +#define CoreDebug_DEMCR_VC_INTERR_Msk (1UL << CoreDebug_DEMCR_VC_INTERR_Pos) /*!< CoreDebug DEMCR: VC_INTERR Mask */ -#define CoreDebug_DEMCR_VC_BUSERR_Pos 8 /*!< CoreDebug DEMCR: VC_BUSERR Position */ -#define CoreDebug_DEMCR_VC_BUSERR_Msk (1UL << CoreDebug_DEMCR_VC_BUSERR_Pos) /*!< CoreDebug DEMCR: VC_BUSERR Mask */ +#define CoreDebug_DEMCR_VC_BUSERR_Pos 8 /*!< CoreDebug DEMCR: VC_BUSERR Position */ +#define CoreDebug_DEMCR_VC_BUSERR_Msk (1UL << CoreDebug_DEMCR_VC_BUSERR_Pos) /*!< CoreDebug DEMCR: VC_BUSERR Mask */ -#define CoreDebug_DEMCR_VC_STATERR_Pos 7 /*!< CoreDebug DEMCR: VC_STATERR Position */ -#define CoreDebug_DEMCR_VC_STATERR_Msk (1UL << CoreDebug_DEMCR_VC_STATERR_Pos) /*!< CoreDebug DEMCR: VC_STATERR Mask */ +#define CoreDebug_DEMCR_VC_STATERR_Pos 7 /*!< CoreDebug DEMCR: VC_STATERR Position */ +#define CoreDebug_DEMCR_VC_STATERR_Msk (1UL << CoreDebug_DEMCR_VC_STATERR_Pos) /*!< CoreDebug DEMCR: VC_STATERR Mask */ -#define CoreDebug_DEMCR_VC_CHKERR_Pos 6 /*!< CoreDebug DEMCR: VC_CHKERR Position */ -#define CoreDebug_DEMCR_VC_CHKERR_Msk (1UL << CoreDebug_DEMCR_VC_CHKERR_Pos) /*!< CoreDebug DEMCR: VC_CHKERR Mask */ +#define CoreDebug_DEMCR_VC_CHKERR_Pos 6 /*!< CoreDebug DEMCR: VC_CHKERR Position */ +#define CoreDebug_DEMCR_VC_CHKERR_Msk (1UL << CoreDebug_DEMCR_VC_CHKERR_Pos) /*!< CoreDebug DEMCR: VC_CHKERR Mask */ -#define CoreDebug_DEMCR_VC_NOCPERR_Pos 5 /*!< CoreDebug DEMCR: VC_NOCPERR Position */ -#define CoreDebug_DEMCR_VC_NOCPERR_Msk (1UL << CoreDebug_DEMCR_VC_NOCPERR_Pos) /*!< CoreDebug DEMCR: VC_NOCPERR Mask */ +#define CoreDebug_DEMCR_VC_NOCPERR_Pos 5 /*!< CoreDebug DEMCR: VC_NOCPERR Position */ +#define CoreDebug_DEMCR_VC_NOCPERR_Msk (1UL << CoreDebug_DEMCR_VC_NOCPERR_Pos) /*!< CoreDebug DEMCR: VC_NOCPERR Mask */ -#define CoreDebug_DEMCR_VC_MMERR_Pos 4 /*!< CoreDebug DEMCR: VC_MMERR Position */ -#define CoreDebug_DEMCR_VC_MMERR_Msk (1UL << CoreDebug_DEMCR_VC_MMERR_Pos) /*!< CoreDebug DEMCR: VC_MMERR Mask */ +#define CoreDebug_DEMCR_VC_MMERR_Pos 4 /*!< CoreDebug DEMCR: VC_MMERR Position */ +#define CoreDebug_DEMCR_VC_MMERR_Msk (1UL << CoreDebug_DEMCR_VC_MMERR_Pos) /*!< CoreDebug DEMCR: VC_MMERR Mask */ -#define CoreDebug_DEMCR_VC_CORERESET_Pos 0 /*!< CoreDebug DEMCR: VC_CORERESET Position */ -#define CoreDebug_DEMCR_VC_CORERESET_Msk (1UL << CoreDebug_DEMCR_VC_CORERESET_Pos) /*!< CoreDebug DEMCR: VC_CORERESET Mask */ +#define CoreDebug_DEMCR_VC_CORERESET_Pos 0 /*!< CoreDebug DEMCR: VC_CORERESET Position */ +#define CoreDebug_DEMCR_VC_CORERESET_Msk (1UL << CoreDebug_DEMCR_VC_CORERESET_Pos) /*!< CoreDebug DEMCR: VC_CORERESET Mask */ /*@} end of group CMSIS_CoreDebug */ - /** \ingroup CMSIS_core_register \defgroup CMSIS_core_base Core Definitions \brief Definitions for base addresses, unions, and structures. @@ -1584,39 +1567,37 @@ typedef struct */ /* Memory mapping of Cortex-M4 Hardware */ -#define SCS_BASE (0xE000E000UL) /*!< System Control Space Base Address */ -#define ITM_BASE (0xE0000000UL) /*!< ITM Base Address */ -#define DWT_BASE (0xE0001000UL) /*!< DWT Base Address */ -#define TPI_BASE (0xE0040000UL) /*!< TPI Base Address */ -#define CoreDebug_BASE (0xE000EDF0UL) /*!< Core Debug Base Address */ -#define SysTick_BASE (SCS_BASE + 0x0010UL) /*!< SysTick Base Address */ -#define NVIC_BASE (SCS_BASE + 0x0100UL) /*!< NVIC Base Address */ -#define SCB_BASE (SCS_BASE + 0x0D00UL) /*!< System Control Block Base Address */ +#define SCS_BASE (0xE000E000UL) /*!< System Control Space Base Address */ +#define ITM_BASE (0xE0000000UL) /*!< ITM Base Address */ +#define DWT_BASE (0xE0001000UL) /*!< DWT Base Address */ +#define TPI_BASE (0xE0040000UL) /*!< TPI Base Address */ +#define CoreDebug_BASE (0xE000EDF0UL) /*!< Core Debug Base Address */ +#define SysTick_BASE (SCS_BASE + 0x0010UL) /*!< SysTick Base Address */ +#define NVIC_BASE (SCS_BASE + 0x0100UL) /*!< NVIC Base Address */ +#define SCB_BASE (SCS_BASE + 0x0D00UL) /*!< System Control Block Base Address */ -#define SCnSCB ((SCnSCB_Type *) SCS_BASE ) /*!< System control Register not in SCB */ -#define SCB ((SCB_Type *) SCB_BASE ) /*!< SCB configuration struct */ -#define SysTick ((SysTick_Type *) SysTick_BASE ) /*!< SysTick configuration struct */ -#define NVIC ((NVIC_Type *) NVIC_BASE ) /*!< NVIC configuration struct */ -#define ITM ((ITM_Type *) ITM_BASE ) /*!< ITM configuration struct */ -#define DWT ((DWT_Type *) DWT_BASE ) /*!< DWT configuration struct */ -#define TPI ((TPI_Type *) TPI_BASE ) /*!< TPI configuration struct */ -#define CoreDebug ((CoreDebug_Type *) CoreDebug_BASE) /*!< Core Debug configuration struct */ +#define SCnSCB ((SCnSCB_Type *)SCS_BASE) /*!< System control Register not in SCB */ +#define SCB ((SCB_Type *)SCB_BASE) /*!< SCB configuration struct */ +#define SysTick ((SysTick_Type *)SysTick_BASE) /*!< SysTick configuration struct */ +#define NVIC ((NVIC_Type *)NVIC_BASE) /*!< NVIC configuration struct */ +#define ITM ((ITM_Type *)ITM_BASE) /*!< ITM configuration struct */ +#define DWT ((DWT_Type *)DWT_BASE) /*!< DWT configuration struct */ +#define TPI ((TPI_Type *)TPI_BASE) /*!< TPI configuration struct */ +#define CoreDebug ((CoreDebug_Type *)CoreDebug_BASE) /*!< Core Debug configuration struct */ #if (__MPU_PRESENT == 1) - #define MPU_BASE (SCS_BASE + 0x0D90UL) /*!< Memory Protection Unit */ - #define MPU ((MPU_Type *) MPU_BASE ) /*!< Memory Protection Unit */ +#define MPU_BASE (SCS_BASE + 0x0D90UL) /*!< Memory Protection Unit */ +#define MPU ((MPU_Type *)MPU_BASE) /*!< Memory Protection Unit */ #endif #if (__FPU_PRESENT == 1) - #define FPU_BASE (SCS_BASE + 0x0F30UL) /*!< Floating Point Unit */ - #define FPU ((FPU_Type *) FPU_BASE ) /*!< Floating Point Unit */ +#define FPU_BASE (SCS_BASE + 0x0F30UL) /*!< Floating Point Unit */ +#define FPU ((FPU_Type *)FPU_BASE) /*!< Floating Point Unit */ #endif -/*@} */ - + /*@} */ - -/******************************************************************************* + /******************************************************************************* * Hardware Abstraction Layer Core Function Interface contains: - Core NVIC Functions @@ -1624,19 +1605,17 @@ typedef struct - Core Debug Functions - Core Register Access Functions ******************************************************************************/ -/** \defgroup CMSIS_Core_FunctionInterface Functions and Instructions Reference + /** \defgroup CMSIS_Core_FunctionInterface Functions and Instructions Reference */ - - -/* ########################## NVIC functions #################################### */ -/** \ingroup CMSIS_Core_FunctionInterface + /* ########################## NVIC functions #################################### */ + /** \ingroup CMSIS_Core_FunctionInterface \defgroup CMSIS_Core_NVICFunctions NVIC Functions \brief Functions that manage interrupts and exceptions via the NVIC. @{ */ -/** \brief Set Priority Grouping + /** \brief Set Priority Grouping The function sets the priority grouping field using the required unlock sequence. The parameter PriorityGroup is assigned to the field SCB->AIRCR [10:8] PRIGROUP field. @@ -1646,58 +1625,54 @@ typedef struct \param [in] PriorityGroup Priority grouping field. */ -__STATIC_INLINE void NVIC_SetPriorityGrouping(uint32_t PriorityGroup) -{ - uint32_t reg_value; - uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07); /* only values 0..7 are used */ - - reg_value = SCB->AIRCR; /* read old register configuration */ - reg_value &= ~(SCB_AIRCR_VECTKEY_Msk | SCB_AIRCR_PRIGROUP_Msk); /* clear bits to change */ - reg_value = (reg_value | - ((uint32_t)0x5FA << SCB_AIRCR_VECTKEY_Pos) | - (PriorityGroupTmp << 8)); /* Insert write key and priorty group */ - SCB->AIRCR = reg_value; -} + __STATIC_INLINE void NVIC_SetPriorityGrouping(uint32_t PriorityGroup) + { + uint32_t reg_value; + uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07); /* only values 0..7 are used */ + reg_value = SCB->AIRCR; /* read old register configuration */ + reg_value &= ~(SCB_AIRCR_VECTKEY_Msk | SCB_AIRCR_PRIGROUP_Msk); /* clear bits to change */ + reg_value = (reg_value | + ((uint32_t)0x5FA << SCB_AIRCR_VECTKEY_Pos) | + (PriorityGroupTmp << 8)); /* Insert write key and priorty group */ + SCB->AIRCR = reg_value; + } -/** \brief Get Priority Grouping + /** \brief Get Priority Grouping The function reads the priority grouping field from the NVIC Interrupt Controller. \return Priority grouping field (SCB->AIRCR [10:8] PRIGROUP field). */ -__STATIC_INLINE uint32_t NVIC_GetPriorityGrouping(void) -{ - return ((SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) >> SCB_AIRCR_PRIGROUP_Pos); /* read priority grouping field */ -} + __STATIC_INLINE uint32_t NVIC_GetPriorityGrouping(void) + { + return ((SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) >> SCB_AIRCR_PRIGROUP_Pos); /* read priority grouping field */ + } - -/** \brief Enable External Interrupt + /** \brief Enable External Interrupt The function enables a device-specific interrupt in the NVIC interrupt controller. \param [in] IRQn External interrupt number. Value cannot be negative. */ -__STATIC_INLINE void NVIC_EnableIRQ(IRQn_Type IRQn) -{ -/* NVIC->ISER[((uint32_t)(IRQn) >> 5)] = (1 << ((uint32_t)(IRQn) & 0x1F)); enable interrupt */ - NVIC->ISER[(uint32_t)((int32_t)IRQn) >> 5] = (uint32_t)(1 << ((uint32_t)((int32_t)IRQn) & (uint32_t)0x1F)); /* enable interrupt */ -} + __STATIC_INLINE void NVIC_EnableIRQ(IRQn_Type IRQn) + { + /* NVIC->ISER[((uint32_t)(IRQn) >> 5)] = (1 << ((uint32_t)(IRQn) & 0x1F)); enable interrupt */ + NVIC->ISER[(uint32_t)((int32_t)IRQn) >> 5] = (uint32_t)(1 << ((uint32_t)((int32_t)IRQn) & (uint32_t)0x1F)); /* enable interrupt */ + } - -/** \brief Disable External Interrupt + /** \brief Disable External Interrupt The function disables a device-specific interrupt in the NVIC interrupt controller. \param [in] IRQn External interrupt number. Value cannot be negative. */ -__STATIC_INLINE void NVIC_DisableIRQ(IRQn_Type IRQn) -{ - NVIC->ICER[((uint32_t)(IRQn) >> 5)] = (1 << ((uint32_t)(IRQn) & 0x1F)); /* disable interrupt */ -} + __STATIC_INLINE void NVIC_DisableIRQ(IRQn_Type IRQn) + { + NVIC->ICER[((uint32_t)(IRQn) >> 5)] = (1 << ((uint32_t)(IRQn)&0x1F)); /* disable interrupt */ + } - -/** \brief Get Pending Interrupt + /** \brief Get Pending Interrupt The function reads the pending register in the NVIC and returns the pending bit for the specified interrupt. @@ -1707,37 +1682,34 @@ __STATIC_INLINE void NVIC_DisableIRQ(IRQn_Type IRQn) \return 0 Interrupt status is not pending. \return 1 Interrupt status is pending. */ -__STATIC_INLINE uint32_t NVIC_GetPendingIRQ(IRQn_Type IRQn) -{ - return((uint32_t) ((NVIC->ISPR[(uint32_t)(IRQn) >> 5] & (1 << ((uint32_t)(IRQn) & 0x1F)))?1:0)); /* Return 1 if pending else 0 */ -} + __STATIC_INLINE uint32_t NVIC_GetPendingIRQ(IRQn_Type IRQn) + { + return ((uint32_t)((NVIC->ISPR[(uint32_t)(IRQn) >> 5] & (1 << ((uint32_t)(IRQn)&0x1F))) ? 1 : 0)); /* Return 1 if pending else 0 */ + } - -/** \brief Set Pending Interrupt + /** \brief Set Pending Interrupt The function sets the pending bit of an external interrupt. \param [in] IRQn Interrupt number. Value cannot be negative. */ -__STATIC_INLINE void NVIC_SetPendingIRQ(IRQn_Type IRQn) -{ - NVIC->ISPR[((uint32_t)(IRQn) >> 5)] = (1 << ((uint32_t)(IRQn) & 0x1F)); /* set interrupt pending */ -} - + __STATIC_INLINE void NVIC_SetPendingIRQ(IRQn_Type IRQn) + { + NVIC->ISPR[((uint32_t)(IRQn) >> 5)] = (1 << ((uint32_t)(IRQn)&0x1F)); /* set interrupt pending */ + } -/** \brief Clear Pending Interrupt + /** \brief Clear Pending Interrupt The function clears the pending bit of an external interrupt. \param [in] IRQn External interrupt number. Value cannot be negative. */ -__STATIC_INLINE void NVIC_ClearPendingIRQ(IRQn_Type IRQn) -{ - NVIC->ICPR[((uint32_t)(IRQn) >> 5)] = (1 << ((uint32_t)(IRQn) & 0x1F)); /* Clear pending interrupt */ -} - + __STATIC_INLINE void NVIC_ClearPendingIRQ(IRQn_Type IRQn) + { + NVIC->ICPR[((uint32_t)(IRQn) >> 5)] = (1 << ((uint32_t)(IRQn)&0x1F)); /* Clear pending interrupt */ + } -/** \brief Get Active Interrupt + /** \brief Get Active Interrupt The function reads the active register in NVIC and returns the active bit. @@ -1746,13 +1718,12 @@ __STATIC_INLINE void NVIC_ClearPendingIRQ(IRQn_Type IRQn) \return 0 Interrupt status is not active. \return 1 Interrupt status is active. */ -__STATIC_INLINE uint32_t NVIC_GetActive(IRQn_Type IRQn) -{ - return((uint32_t)((NVIC->IABR[(uint32_t)(IRQn) >> 5] & (1 << ((uint32_t)(IRQn) & 0x1F)))?1:0)); /* Return 1 if active else 0 */ -} - + __STATIC_INLINE uint32_t NVIC_GetActive(IRQn_Type IRQn) + { + return ((uint32_t)((NVIC->IABR[(uint32_t)(IRQn) >> 5] & (1 << ((uint32_t)(IRQn)&0x1F))) ? 1 : 0)); /* Return 1 if active else 0 */ + } -/** \brief Set Interrupt Priority + /** \brief Set Interrupt Priority The function sets the priority of an interrupt. @@ -1761,16 +1732,19 @@ __STATIC_INLINE uint32_t NVIC_GetActive(IRQn_Type IRQn) \param [in] IRQn Interrupt number. \param [in] priority Priority to set. */ -__STATIC_INLINE void NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority) -{ - if(IRQn < 0) { - SCB->SHPR[((uint32_t)(IRQn) & 0xF)-4] = ((priority << (8 - __NVIC_PRIO_BITS)) & 0xff); } /* set Priority for Cortex-M System Interrupts */ - else { - NVIC->IP[(uint32_t)(IRQn)] = ((priority << (8 - __NVIC_PRIO_BITS)) & 0xff); } /* set Priority for device specific Interrupts */ -} - + __STATIC_INLINE void NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority) + { + if (IRQn < 0) + { + SCB->SHPR[((uint32_t)(IRQn)&0xF) - 4] = ((priority << (8 - __NVIC_PRIO_BITS)) & 0xff); + } /* set Priority for Cortex-M System Interrupts */ + else + { + NVIC->IP[(uint32_t)(IRQn)] = ((priority << (8 - __NVIC_PRIO_BITS)) & 0xff); + } /* set Priority for device specific Interrupts */ + } -/** \brief Get Interrupt Priority + /** \brief Get Interrupt Priority The function reads the priority of an interrupt. The interrupt number can be positive to specify an external (device specific) @@ -1781,17 +1755,20 @@ __STATIC_INLINE void NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority) \return Interrupt Priority. Value is aligned automatically to the implemented priority bits of the microcontroller. */ -__STATIC_INLINE uint32_t NVIC_GetPriority(IRQn_Type IRQn) -{ - - if(IRQn < 0) { - return((uint32_t)(SCB->SHPR[((uint32_t)(IRQn) & 0xF)-4] >> (8 - __NVIC_PRIO_BITS))); } /* get priority for Cortex-M system interrupts */ - else { - return((uint32_t)(NVIC->IP[(uint32_t)(IRQn)] >> (8 - __NVIC_PRIO_BITS))); } /* get priority for device specific interrupts */ -} + __STATIC_INLINE uint32_t NVIC_GetPriority(IRQn_Type IRQn) + { + if (IRQn < 0) + { + return ((uint32_t)(SCB->SHPR[((uint32_t)(IRQn)&0xF) - 4] >> (8 - __NVIC_PRIO_BITS))); + } /* get priority for Cortex-M system interrupts */ + else + { + return ((uint32_t)(NVIC->IP[(uint32_t)(IRQn)] >> (8 - __NVIC_PRIO_BITS))); + } /* get priority for device specific interrupts */ + } -/** \brief Encode Priority + /** \brief Encode Priority The function encodes the priority for an interrupt with the given priority group, preemptive priority value, and subpriority value. @@ -1803,23 +1780,21 @@ __STATIC_INLINE uint32_t NVIC_GetPriority(IRQn_Type IRQn) \param [in] SubPriority Subpriority value (starting from 0). \return Encoded priority. Value can be used in the function \ref NVIC_SetPriority(). */ -__STATIC_INLINE uint32_t NVIC_EncodePriority (uint32_t PriorityGroup, uint32_t PreemptPriority, uint32_t SubPriority) -{ - uint32_t PriorityGroupTmp = (PriorityGroup & 0x07); /* only values 0..7 are used */ - uint32_t PreemptPriorityBits; - uint32_t SubPriorityBits; - - PreemptPriorityBits = ((7 - PriorityGroupTmp) > __NVIC_PRIO_BITS) ? __NVIC_PRIO_BITS : 7 - PriorityGroupTmp; - SubPriorityBits = ((PriorityGroupTmp + __NVIC_PRIO_BITS) < 7) ? 0 : PriorityGroupTmp - 7 + __NVIC_PRIO_BITS; + __STATIC_INLINE uint32_t NVIC_EncodePriority(uint32_t PriorityGroup, uint32_t PreemptPriority, uint32_t SubPriority) + { + uint32_t PriorityGroupTmp = (PriorityGroup & 0x07); /* only values 0..7 are used */ + uint32_t PreemptPriorityBits; + uint32_t SubPriorityBits; - return ( - ((PreemptPriority & ((1 << (PreemptPriorityBits)) - 1)) << SubPriorityBits) | - ((SubPriority & ((1 << (SubPriorityBits )) - 1))) - ); -} + PreemptPriorityBits = ((7 - PriorityGroupTmp) > __NVIC_PRIO_BITS) ? __NVIC_PRIO_BITS : 7 - PriorityGroupTmp; + SubPriorityBits = ((PriorityGroupTmp + __NVIC_PRIO_BITS) < 7) ? 0 : PriorityGroupTmp - 7 + __NVIC_PRIO_BITS; + return ( + ((PreemptPriority & ((1 << (PreemptPriorityBits)) - 1)) << SubPriorityBits) | + ((SubPriority & ((1 << (SubPriorityBits)) - 1)))); + } -/** \brief Decode Priority + /** \brief Decode Priority The function decodes an interrupt priority value with a given priority group to preemptive priority value and subpriority value. @@ -1831,38 +1806,37 @@ __STATIC_INLINE uint32_t NVIC_EncodePriority (uint32_t PriorityGroup, uint32_t P \param [out] pPreemptPriority Preemptive priority value (starting from 0). \param [out] pSubPriority Subpriority value (starting from 0). */ -__STATIC_INLINE void NVIC_DecodePriority (uint32_t Priority, uint32_t PriorityGroup, uint32_t* pPreemptPriority, uint32_t* pSubPriority) -{ - uint32_t PriorityGroupTmp = (PriorityGroup & 0x07); /* only values 0..7 are used */ - uint32_t PreemptPriorityBits; - uint32_t SubPriorityBits; - - PreemptPriorityBits = ((7 - PriorityGroupTmp) > __NVIC_PRIO_BITS) ? __NVIC_PRIO_BITS : 7 - PriorityGroupTmp; - SubPriorityBits = ((PriorityGroupTmp + __NVIC_PRIO_BITS) < 7) ? 0 : PriorityGroupTmp - 7 + __NVIC_PRIO_BITS; + __STATIC_INLINE void NVIC_DecodePriority(uint32_t Priority, uint32_t PriorityGroup, uint32_t *pPreemptPriority, uint32_t *pSubPriority) + { + uint32_t PriorityGroupTmp = (PriorityGroup & 0x07); /* only values 0..7 are used */ + uint32_t PreemptPriorityBits; + uint32_t SubPriorityBits; - *pPreemptPriority = (Priority >> SubPriorityBits) & ((1 << (PreemptPriorityBits)) - 1); - *pSubPriority = (Priority ) & ((1 << (SubPriorityBits )) - 1); -} + PreemptPriorityBits = ((7 - PriorityGroupTmp) > __NVIC_PRIO_BITS) ? __NVIC_PRIO_BITS : 7 - PriorityGroupTmp; + SubPriorityBits = ((PriorityGroupTmp + __NVIC_PRIO_BITS) < 7) ? 0 : PriorityGroupTmp - 7 + __NVIC_PRIO_BITS; + *pPreemptPriority = (Priority >> SubPriorityBits) & ((1 << (PreemptPriorityBits)) - 1); + *pSubPriority = (Priority) & ((1 << (SubPriorityBits)) - 1); + } -/** \brief System Reset + /** \brief System Reset The function initiates a system reset request to reset the MCU. */ -__STATIC_INLINE void NVIC_SystemReset(void) -{ - __DSB(); /* Ensure all outstanding memory accesses included + __STATIC_INLINE void NVIC_SystemReset(void) + { + __DSB(); /* Ensure all outstanding memory accesses included buffered write are completed before reset */ - SCB->AIRCR = ((0x5FA << SCB_AIRCR_VECTKEY_Pos) | - (SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) | - SCB_AIRCR_SYSRESETREQ_Msk); /* Keep priority group unchanged */ - __DSB(); /* Ensure completion of memory access */ - while(1); /* wait until reset */ -} + SCB->AIRCR = ((0x5FA << SCB_AIRCR_VECTKEY_Pos) | + (SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) | + SCB_AIRCR_SYSRESETREQ_Msk); /* Keep priority group unchanged */ + __DSB(); /* Ensure completion of memory access */ + while (1) + ; /* wait until reset */ + } /*@} end of CMSIS_Core_NVICFunctions */ - /* ########################## Cache functions #################################### */ /** \ingroup CMSIS_Core_FunctionInterface \defgroup CMSIS_Core_CacheFunctions Cache Functions @@ -1871,233 +1845,231 @@ __STATIC_INLINE void NVIC_SystemReset(void) */ /* Cache Size ID Register Macros */ -#define CCSIDR_WAYS(x) (((x) & SCB_CCSIDR_ASSOCIATIVITY_Msk) >> SCB_CCSIDR_ASSOCIATIVITY_Pos) -#define CCSIDR_SETS(x) (((x) & SCB_CCSIDR_NUMSETS_Msk ) >> SCB_CCSIDR_NUMSETS_Pos ) -#define CCSIDR_LSSHIFT(x) (((x) & SCB_CCSIDR_LINESIZE_Msk ) >> SCB_CCSIDR_LINESIZE_Pos ) - +#define CCSIDR_WAYS(x) (((x)&SCB_CCSIDR_ASSOCIATIVITY_Msk) >> SCB_CCSIDR_ASSOCIATIVITY_Pos) +#define CCSIDR_SETS(x) (((x)&SCB_CCSIDR_NUMSETS_Msk) >> SCB_CCSIDR_NUMSETS_Pos) +#define CCSIDR_LSSHIFT(x) (((x)&SCB_CCSIDR_LINESIZE_Msk) >> SCB_CCSIDR_LINESIZE_Pos) -/** \brief Enable I-Cache + /** \brief Enable I-Cache The function turns on I-Cache */ -__STATIC_INLINE void SCB_EnableICache(void) -{ - #if (__ICACHE_PRESENT == 1) - __DSB(); - __ISB(); - SCB->ICIALLU = 0; // invalidate I-Cache - SCB->CCR |= SCB_CCR_IC_Msk; // enable I-Cache - __DSB(); - __ISB(); - #endif -} - + __STATIC_INLINE void SCB_EnableICache(void) + { +#if (__ICACHE_PRESENT == 1) + __DSB(); + __ISB(); + SCB->ICIALLU = 0; // invalidate I-Cache + SCB->CCR |= SCB_CCR_IC_Msk; // enable I-Cache + __DSB(); + __ISB(); +#endif + } -/** \brief Disable I-Cache + /** \brief Disable I-Cache The function turns off I-Cache */ -__STATIC_INLINE void SCB_DisableICache(void) -{ - #if (__ICACHE_PRESENT == 1) - __DSB(); - __ISB(); - SCB->CCR &= ~SCB_CCR_IC_Msk; // disable I-Cache - SCB->ICIALLU = 0; // invalidate I-Cache - __DSB(); - __ISB(); - #endif -} - + __STATIC_INLINE void SCB_DisableICache(void) + { +#if (__ICACHE_PRESENT == 1) + __DSB(); + __ISB(); + SCB->CCR &= ~SCB_CCR_IC_Msk; // disable I-Cache + SCB->ICIALLU = 0; // invalidate I-Cache + __DSB(); + __ISB(); +#endif + } -/** \brief Invalidate I-Cache + /** \brief Invalidate I-Cache The function invalidates I-Cache */ -__STATIC_INLINE void SCB_InvalidateICache(void) -{ - #if (__ICACHE_PRESENT == 1) - __DSB(); - __ISB(); - SCB->ICIALLU = 0; - __DSB(); - __ISB(); - #endif -} - + __STATIC_INLINE void SCB_InvalidateICache(void) + { +#if (__ICACHE_PRESENT == 1) + __DSB(); + __ISB(); + SCB->ICIALLU = 0; + __DSB(); + __ISB(); +#endif + } -/** \brief Enable D-Cache + /** \brief Enable D-Cache The function turns on D-Cache */ -__STATIC_INLINE void SCB_EnableDCache(void) -{ - #if (__DCACHE_PRESENT == 1) - uint32_t ccsidr, sshift, wshift, sw; - uint32_t sets, ways; + __STATIC_INLINE void SCB_EnableDCache(void) + { +#if (__DCACHE_PRESENT == 1) + uint32_t ccsidr, sshift, wshift, sw; + uint32_t sets, ways; - ccsidr = SCB->CCSIDR; - sets = CCSIDR_SETS(ccsidr); - sshift = CCSIDR_LSSHIFT(ccsidr) + 4; - ways = CCSIDR_WAYS(ccsidr); - wshift = __CLZ(ways) & 0x1f; + ccsidr = SCB->CCSIDR; + sets = CCSIDR_SETS(ccsidr); + sshift = CCSIDR_LSSHIFT(ccsidr) + 4; + ways = CCSIDR_WAYS(ccsidr); + wshift = __CLZ(ways) & 0x1f; - __DSB(); + __DSB(); - do { // invalidate D-Cache - int32_t tmpways = ways; - do { - sw = ((tmpways << wshift) | (sets << sshift)); - SCB->DCISW = sw; - } while(tmpways--); - } while(sets--); - __DSB(); + do + { // invalidate D-Cache + int32_t tmpways = ways; + do + { + sw = ((tmpways << wshift) | (sets << sshift)); + SCB->DCISW = sw; + } while (tmpways--); + } while (sets--); + __DSB(); - SCB->CCR |= SCB_CCR_DC_Msk; // enable D-Cache - - __DSB(); - __ISB(); - #endif -} + SCB->CCR |= SCB_CCR_DC_Msk; // enable D-Cache + __DSB(); + __ISB(); +#endif + } -/** \brief Disable D-Cache + /** \brief Disable D-Cache The function turns off D-Cache */ -__STATIC_INLINE void SCB_DisableDCache(void) -{ - #if (__DCACHE_PRESENT == 1) - uint32_t ccsidr, sshift, wshift, sw; - uint32_t sets, ways; - - ccsidr = SCB->CCSIDR; - sets = CCSIDR_SETS(ccsidr); - sshift = CCSIDR_LSSHIFT(ccsidr) + 4; - ways = CCSIDR_WAYS(ccsidr); - wshift = __CLZ(ways) & 0x1f; - - __DSB(); + __STATIC_INLINE void SCB_DisableDCache(void) + { +#if (__DCACHE_PRESENT == 1) + uint32_t ccsidr, sshift, wshift, sw; + uint32_t sets, ways; - SCB->CCR &= ~SCB_CCR_DC_Msk; // disable D-Cache + ccsidr = SCB->CCSIDR; + sets = CCSIDR_SETS(ccsidr); + sshift = CCSIDR_LSSHIFT(ccsidr) + 4; + ways = CCSIDR_WAYS(ccsidr); + wshift = __CLZ(ways) & 0x1f; - do { // clean & invalidate D-Cache - int32_t tmpways = ways; - do { - sw = ((tmpways << wshift) | (sets << sshift)); - SCB->DCCISW = sw; - } while(tmpways--); - } while(sets--); + __DSB(); + SCB->CCR &= ~SCB_CCR_DC_Msk; // disable D-Cache - __DSB(); - __ISB(); - #endif -} + do + { // clean & invalidate D-Cache + int32_t tmpways = ways; + do + { + sw = ((tmpways << wshift) | (sets << sshift)); + SCB->DCCISW = sw; + } while (tmpways--); + } while (sets--); + __DSB(); + __ISB(); +#endif + } -/** \brief Invalidate D-Cache + /** \brief Invalidate D-Cache The function invalidates D-Cache */ -__STATIC_INLINE void SCB_InvalidateDCache(void) -{ - #if (__DCACHE_PRESENT == 1) - uint32_t ccsidr, sshift, wshift, sw; - uint32_t sets, ways; + __STATIC_INLINE void SCB_InvalidateDCache(void) + { +#if (__DCACHE_PRESENT == 1) + uint32_t ccsidr, sshift, wshift, sw; + uint32_t sets, ways; - ccsidr = SCB->CCSIDR; - sets = CCSIDR_SETS(ccsidr); - sshift = CCSIDR_LSSHIFT(ccsidr) + 4; - ways = CCSIDR_WAYS(ccsidr); - wshift = __CLZ(ways) & 0x1f; + ccsidr = SCB->CCSIDR; + sets = CCSIDR_SETS(ccsidr); + sshift = CCSIDR_LSSHIFT(ccsidr) + 4; + ways = CCSIDR_WAYS(ccsidr); + wshift = __CLZ(ways) & 0x1f; - __DSB(); + __DSB(); - do { // invalidate D-Cache - int32_t tmpways = ways; - do { - sw = ((tmpways << wshift) | (sets << sshift)); - SCB->DCISW = sw; - } while(tmpways--); - } while(sets--); - - __DSB(); - __ISB(); - #endif -} + do + { // invalidate D-Cache + int32_t tmpways = ways; + do + { + sw = ((tmpways << wshift) | (sets << sshift)); + SCB->DCISW = sw; + } while (tmpways--); + } while (sets--); + __DSB(); + __ISB(); +#endif + } -/** \brief Clean D-Cache + /** \brief Clean D-Cache The function cleans D-Cache */ -__STATIC_INLINE void SCB_CleanDCache(void) -{ - #if (__DCACHE_PRESENT == 1) - uint32_t ccsidr, sshift, wshift, sw; - uint32_t sets, ways; - - ccsidr = SCB->CCSIDR; - sets = CCSIDR_SETS(ccsidr); - sshift = CCSIDR_LSSHIFT(ccsidr) + 4; - ways = CCSIDR_WAYS(ccsidr); - wshift = __CLZ(ways) & 0x1f; + __STATIC_INLINE void SCB_CleanDCache(void) + { +#if (__DCACHE_PRESENT == 1) + uint32_t ccsidr, sshift, wshift, sw; + uint32_t sets, ways; - __DSB(); + ccsidr = SCB->CCSIDR; + sets = CCSIDR_SETS(ccsidr); + sshift = CCSIDR_LSSHIFT(ccsidr) + 4; + ways = CCSIDR_WAYS(ccsidr); + wshift = __CLZ(ways) & 0x1f; - do { // clean D-Cache - int32_t tmpways = ways; - do { - sw = ((tmpways << wshift) | (sets << sshift)); - SCB->DCCSW = sw; - } while(tmpways--); - } while(sets--); + __DSB(); - __DSB(); - __ISB(); - #endif -} + do + { // clean D-Cache + int32_t tmpways = ways; + do + { + sw = ((tmpways << wshift) | (sets << sshift)); + SCB->DCCSW = sw; + } while (tmpways--); + } while (sets--); + __DSB(); + __ISB(); +#endif + } -/** \brief Clean & Invalidate D-Cache + /** \brief Clean & Invalidate D-Cache The function cleans and Invalidates D-Cache */ -__STATIC_INLINE void SCB_CleanInvalidateDCache(void) -{ - #if (__DCACHE_PRESENT == 1) - uint32_t ccsidr, sshift, wshift, sw; - uint32_t sets, ways; + __STATIC_INLINE void SCB_CleanInvalidateDCache(void) + { +#if (__DCACHE_PRESENT == 1) + uint32_t ccsidr, sshift, wshift, sw; + uint32_t sets, ways; - ccsidr = SCB->CCSIDR; - sets = CCSIDR_SETS(ccsidr); - sshift = CCSIDR_LSSHIFT(ccsidr) + 4; - ways = CCSIDR_WAYS(ccsidr); - wshift = __CLZ(ways) & 0x1f; + ccsidr = SCB->CCSIDR; + sets = CCSIDR_SETS(ccsidr); + sshift = CCSIDR_LSSHIFT(ccsidr) + 4; + ways = CCSIDR_WAYS(ccsidr); + wshift = __CLZ(ways) & 0x1f; - __DSB(); + __DSB(); - do { // clean & invalidate D-Cache - int32_t tmpways = ways; - do { - sw = ((tmpways << wshift) | (sets << sshift)); - SCB->DCCISW = sw; - } while(tmpways--); - } while(sets--); - - __DSB(); - __ISB(); - #endif -} - - -/*@} end of CMSIS_Core_CacheFunctions */ + do + { // clean & invalidate D-Cache + int32_t tmpways = ways; + do + { + sw = ((tmpways << wshift) | (sets << sshift)); + SCB->DCCISW = sw; + } while (tmpways--); + } while (sets--); + __DSB(); + __ISB(); +#endif + } + /*@} end of CMSIS_Core_CacheFunctions */ -/* ################################## SysTick function ############################################ */ -/** \ingroup CMSIS_Core_FunctionInterface + /* ################################## SysTick function ############################################ */ + /** \ingroup CMSIS_Core_FunctionInterface \defgroup CMSIS_Core_SysTickFunctions SysTick Functions \brief Functions that configure the System. @{ @@ -2105,7 +2077,7 @@ __STATIC_INLINE void SCB_CleanInvalidateDCache(void) #if (__Vendor_SysTickConfig == 0) -/** \brief System Tick Configuration + /** \brief System Tick Configuration The function initializes the System Timer and its interrupt, and starts the System Tick Timer. Counter is in free running mode to generate periodic interrupts. @@ -2120,37 +2092,35 @@ __STATIC_INLINE void SCB_CleanInvalidateDCache(void) must contain a vendor-specific implementation of this function. */ -__STATIC_INLINE uint32_t SysTick_Config(uint32_t ticks) -{ - if ((ticks - 1) > SysTick_LOAD_RELOAD_Msk) return (1); /* Reload value impossible */ + __STATIC_INLINE uint32_t SysTick_Config(uint32_t ticks) + { + if ((ticks - 1) > SysTick_LOAD_RELOAD_Msk) + return (1); /* Reload value impossible */ - SysTick->LOAD = ticks - 1; /* set reload register */ - NVIC_SetPriority (SysTick_IRQn, (1<<__NVIC_PRIO_BITS) - 1); /* set Priority for Systick Interrupt */ - SysTick->VAL = 0; /* Load the SysTick Counter Value */ - SysTick->CTRL = SysTick_CTRL_CLKSOURCE_Msk | - SysTick_CTRL_TICKINT_Msk | - SysTick_CTRL_ENABLE_Msk; /* Enable SysTick IRQ and SysTick Timer */ - return (0); /* Function successful */ -} + SysTick->LOAD = ticks - 1; /* set reload register */ + NVIC_SetPriority(SysTick_IRQn, (1 << __NVIC_PRIO_BITS) - 1); /* set Priority for Systick Interrupt */ + SysTick->VAL = 0; /* Load the SysTick Counter Value */ + SysTick->CTRL = SysTick_CTRL_CLKSOURCE_Msk | + SysTick_CTRL_TICKINT_Msk | + SysTick_CTRL_ENABLE_Msk; /* Enable SysTick IRQ and SysTick Timer */ + return (0); /* Function successful */ + } #endif -/*@} end of CMSIS_Core_SysTickFunctions */ - + /*@} end of CMSIS_Core_SysTickFunctions */ - -/* ##################################### Debug In/Output function ########################################### */ -/** \ingroup CMSIS_Core_FunctionInterface + /* ##################################### Debug In/Output function ########################################### */ + /** \ingroup CMSIS_Core_FunctionInterface \defgroup CMSIS_core_DebugFunctions ITM Functions \brief Functions that access the ITM debug interface. @{ */ -extern volatile int32_t ITM_RxBuffer; /*!< External variable to receive characters. */ -#define ITM_RXBUFFER_EMPTY 0x5AA55AA5 /*!< Value identifying \ref ITM_RxBuffer is ready for next character. */ + extern volatile int32_t ITM_RxBuffer; /*!< External variable to receive characters. */ +#define ITM_RXBUFFER_EMPTY 0x5AA55AA5 /*!< Value identifying \ref ITM_RxBuffer is ready for next character. */ - -/** \brief ITM Send Character + /** \brief ITM Send Character The function transmits a character via the ITM channel 0, and \li Just returns when no debugger is connected that has booked the output. @@ -2160,57 +2130,59 @@ extern volatile int32_t ITM_RxBuffer; /*!< External variable \returns Character to transmit. */ -__STATIC_INLINE uint32_t ITM_SendChar (uint32_t ch) -{ - if ((ITM->TCR & ITM_TCR_ITMENA_Msk) && /* ITM enabled */ - (ITM->TER & (1UL << 0) ) ) /* ITM Port #0 enabled */ - { - while (ITM->PORT[0].u32 == 0); - ITM->PORT[0].u8 = (uint8_t) ch; - } - return (ch); -} + __STATIC_INLINE uint32_t ITM_SendChar(uint32_t ch) + { + if ((ITM->TCR & ITM_TCR_ITMENA_Msk) && /* ITM enabled */ + (ITM->TER & (1UL << 0))) /* ITM Port #0 enabled */ + { + while (ITM->PORT[0].u32 == 0) + ; + ITM->PORT[0].u8 = (uint8_t)ch; + } + return (ch); + } - -/** \brief ITM Receive Character + /** \brief ITM Receive Character The function inputs a character via the external variable \ref ITM_RxBuffer. \return Received character. \return -1 No character pending. */ -__STATIC_INLINE int32_t ITM_ReceiveChar (void) { - int32_t ch = -1; /* no character available */ - - if (ITM_RxBuffer != ITM_RXBUFFER_EMPTY) { - ch = ITM_RxBuffer; - ITM_RxBuffer = ITM_RXBUFFER_EMPTY; /* ready for next character */ - } + __STATIC_INLINE int32_t ITM_ReceiveChar(void) + { + int32_t ch = -1; /* no character available */ - return (ch); -} + if (ITM_RxBuffer != ITM_RXBUFFER_EMPTY) + { + ch = ITM_RxBuffer; + ITM_RxBuffer = ITM_RXBUFFER_EMPTY; /* ready for next character */ + } + return (ch); + } -/** \brief ITM Check Character + /** \brief ITM Check Character The function checks whether a character is pending for reading in the variable \ref ITM_RxBuffer. \return 0 No character available. \return 1 Character available. */ -__STATIC_INLINE int32_t ITM_CheckChar (void) { - - if (ITM_RxBuffer == ITM_RXBUFFER_EMPTY) { - return (0); /* no character available */ - } else { - return (1); /* character available */ - } -} - -/*@} end of CMSIS_core_DebugFunctions */ - + __STATIC_INLINE int32_t ITM_CheckChar(void) + { + if (ITM_RxBuffer == ITM_RXBUFFER_EMPTY) + { + return (0); /* no character available */ + } + else + { + return (1); /* character available */ + } + } + /*@} end of CMSIS_core_DebugFunctions */ #ifdef __cplusplus } diff --git a/bsp/swm320-lq100/Libraries/CMSIS/CoreSupport/core_cmFunc.h b/bsp/swm320-lq100/Libraries/CMSIS/CoreSupport/core_cmFunc.h index 01089f1333..1ccdd1cb91 100644 --- a/bsp/swm320-lq100/Libraries/CMSIS/CoreSupport/core_cmFunc.h +++ b/bsp/swm320-lq100/Libraries/CMSIS/CoreSupport/core_cmFunc.h @@ -1,4 +1,4 @@ -/**************************************************************************//** +/**************************************************************************/ /** * @file core_cmFunc.h * @brief CMSIS Cortex-M Core Function Access Header File * @version V4.00 @@ -34,22 +34,20 @@ POSSIBILITY OF SUCH DAMAGE. ---------------------------------------------------------------------------*/ - #ifndef __CORE_CMFUNC_H #define __CORE_CMFUNC_H - /* ########################### Core Function Access ########################### */ /** \ingroup CMSIS_Core_FunctionInterface \defgroup CMSIS_Core_RegAccFunctions CMSIS Core Register Access Functions @{ */ -#if defined ( __CC_ARM ) /*------------------RealView Compiler -----------------*/ +#if defined(__CC_ARM) /*------------------RealView Compiler -----------------*/ /* ARM armcc specific functions */ #if (__ARMCC_VERSION < 400677) - #error "Please use ARM Compiler Toolchain V4.0.677 or later!" +#error "Please use ARM Compiler Toolchain V4.0.677 or later!" #endif /* intrinsic void __enable_irq(); */ @@ -63,11 +61,10 @@ */ __STATIC_INLINE uint32_t __get_CONTROL(void) { - register uint32_t __regControl __ASM("control"); - return(__regControl); + register uint32_t __regControl __ASM("control"); + return (__regControl); } - /** \brief Set Control Register This function writes the given value to the Control Register. @@ -76,11 +73,10 @@ __STATIC_INLINE uint32_t __get_CONTROL(void) */ __STATIC_INLINE void __set_CONTROL(uint32_t control) { - register uint32_t __regControl __ASM("control"); - __regControl = control; + register uint32_t __regControl __ASM("control"); + __regControl = control; } - /** \brief Get IPSR Register This function returns the content of the IPSR Register. @@ -89,11 +85,10 @@ __STATIC_INLINE void __set_CONTROL(uint32_t control) */ __STATIC_INLINE uint32_t __get_IPSR(void) { - register uint32_t __regIPSR __ASM("ipsr"); - return(__regIPSR); + register uint32_t __regIPSR __ASM("ipsr"); + return (__regIPSR); } - /** \brief Get APSR Register This function returns the content of the APSR Register. @@ -102,11 +97,10 @@ __STATIC_INLINE uint32_t __get_IPSR(void) */ __STATIC_INLINE uint32_t __get_APSR(void) { - register uint32_t __regAPSR __ASM("apsr"); - return(__regAPSR); + register uint32_t __regAPSR __ASM("apsr"); + return (__regAPSR); } - /** \brief Get xPSR Register This function returns the content of the xPSR Register. @@ -115,11 +109,10 @@ __STATIC_INLINE uint32_t __get_APSR(void) */ __STATIC_INLINE uint32_t __get_xPSR(void) { - register uint32_t __regXPSR __ASM("xpsr"); - return(__regXPSR); + register uint32_t __regXPSR __ASM("xpsr"); + return (__regXPSR); } - /** \brief Get Process Stack Pointer This function returns the current value of the Process Stack Pointer (PSP). @@ -128,11 +121,10 @@ __STATIC_INLINE uint32_t __get_xPSR(void) */ __STATIC_INLINE uint32_t __get_PSP(void) { - register uint32_t __regProcessStackPointer __ASM("psp"); - return(__regProcessStackPointer); + register uint32_t __regProcessStackPointer __ASM("psp"); + return (__regProcessStackPointer); } - /** \brief Set Process Stack Pointer This function assigns the given value to the Process Stack Pointer (PSP). @@ -141,11 +133,10 @@ __STATIC_INLINE uint32_t __get_PSP(void) */ __STATIC_INLINE void __set_PSP(uint32_t topOfProcStack) { - register uint32_t __regProcessStackPointer __ASM("psp"); - __regProcessStackPointer = topOfProcStack; + register uint32_t __regProcessStackPointer __ASM("psp"); + __regProcessStackPointer = topOfProcStack; } - /** \brief Get Main Stack Pointer This function returns the current value of the Main Stack Pointer (MSP). @@ -154,11 +145,10 @@ __STATIC_INLINE void __set_PSP(uint32_t topOfProcStack) */ __STATIC_INLINE uint32_t __get_MSP(void) { - register uint32_t __regMainStackPointer __ASM("msp"); - return(__regMainStackPointer); + register uint32_t __regMainStackPointer __ASM("msp"); + return (__regMainStackPointer); } - /** \brief Set Main Stack Pointer This function assigns the given value to the Main Stack Pointer (MSP). @@ -167,11 +157,10 @@ __STATIC_INLINE uint32_t __get_MSP(void) */ __STATIC_INLINE void __set_MSP(uint32_t topOfMainStack) { - register uint32_t __regMainStackPointer __ASM("msp"); - __regMainStackPointer = topOfMainStack; + register uint32_t __regMainStackPointer __ASM("msp"); + __regMainStackPointer = topOfMainStack; } - /** \brief Get Priority Mask This function returns the current state of the priority mask bit from the Priority Mask Register. @@ -180,11 +169,10 @@ __STATIC_INLINE void __set_MSP(uint32_t topOfMainStack) */ __STATIC_INLINE uint32_t __get_PRIMASK(void) { - register uint32_t __regPriMask __ASM("primask"); - return(__regPriMask); + register uint32_t __regPriMask __ASM("primask"); + return (__regPriMask); } - /** \brief Set Priority Mask This function assigns the given value to the Priority Mask Register. @@ -193,28 +181,25 @@ __STATIC_INLINE uint32_t __get_PRIMASK(void) */ __STATIC_INLINE void __set_PRIMASK(uint32_t priMask) { - register uint32_t __regPriMask __ASM("primask"); - __regPriMask = (priMask); + register uint32_t __regPriMask __ASM("primask"); + __regPriMask = (priMask); } - -#if (__CORTEX_M >= 0x03) || (__CORTEX_SC >= 300) +#if (__CORTEX_M >= 0x03) || (__CORTEX_SC >= 300) /** \brief Enable FIQ This function enables FIQ interrupts by clearing the F-bit in the CPSR. Can only be executed in Privileged modes. */ -#define __enable_fault_irq __enable_fiq - +#define __enable_fault_irq __enable_fiq /** \brief Disable FIQ This function disables FIQ interrupts by setting the F-bit in the CPSR. Can only be executed in Privileged modes. */ -#define __disable_fault_irq __disable_fiq - +#define __disable_fault_irq __disable_fiq /** \brief Get Base Priority @@ -222,13 +207,12 @@ __STATIC_INLINE void __set_PRIMASK(uint32_t priMask) \return Base Priority register value */ -__STATIC_INLINE uint32_t __get_BASEPRI(void) +__STATIC_INLINE uint32_t __get_BASEPRI(void) { - register uint32_t __regBasePri __ASM("basepri"); - return(__regBasePri); + register uint32_t __regBasePri __ASM("basepri"); + return (__regBasePri); } - /** \brief Set Base Priority This function assigns the given value to the Base Priority register. @@ -237,11 +221,10 @@ __STATIC_INLINE uint32_t __get_BASEPRI(void) */ __STATIC_INLINE void __set_BASEPRI(uint32_t basePri) { - register uint32_t __regBasePri __ASM("basepri"); - __regBasePri = (basePri & 0xff); + register uint32_t __regBasePri __ASM("basepri"); + __regBasePri = (basePri & 0xff); } - /** \brief Get Fault Mask This function returns the current value of the Fault Mask register. @@ -250,11 +233,10 @@ __STATIC_INLINE void __set_BASEPRI(uint32_t basePri) */ __STATIC_INLINE uint32_t __get_FAULTMASK(void) { - register uint32_t __regFaultMask __ASM("faultmask"); - return(__regFaultMask); + register uint32_t __regFaultMask __ASM("faultmask"); + return (__regFaultMask); } - /** \brief Set Fault Mask This function assigns the given value to the Fault Mask register. @@ -263,14 +245,13 @@ __STATIC_INLINE uint32_t __get_FAULTMASK(void) */ __STATIC_INLINE void __set_FAULTMASK(uint32_t faultMask) { - register uint32_t __regFaultMask __ASM("faultmask"); - __regFaultMask = (faultMask & (uint32_t)1); + register uint32_t __regFaultMask __ASM("faultmask"); + __regFaultMask = (faultMask & (uint32_t)1); } #endif /* (__CORTEX_M >= 0x03) || (__CORTEX_SC >= 300) */ - -#if (__CORTEX_M == 0x04) || (__CORTEX_M == 0x07) +#if (__CORTEX_M == 0x04) || (__CORTEX_M == 0x07) /** \brief Get FPSCR @@ -281,14 +262,13 @@ __STATIC_INLINE void __set_FAULTMASK(uint32_t faultMask) __STATIC_INLINE uint32_t __get_FPSCR(void) { #if (__FPU_PRESENT == 1) && (__FPU_USED == 1) - register uint32_t __regfpscr __ASM("fpscr"); - return(__regfpscr); + register uint32_t __regfpscr __ASM("fpscr"); + return (__regfpscr); #else - return(0); + return (0); #endif } - /** \brief Set FPSCR This function assigns the given value to the Floating Point Status/Control register. @@ -298,15 +278,14 @@ __STATIC_INLINE uint32_t __get_FPSCR(void) __STATIC_INLINE void __set_FPSCR(uint32_t fpscr) { #if (__FPU_PRESENT == 1) && (__FPU_USED == 1) - register uint32_t __regfpscr __ASM("fpscr"); - __regfpscr = (fpscr); + register uint32_t __regfpscr __ASM("fpscr"); + __regfpscr = (fpscr); #endif } #endif /* (__CORTEX_M == 0x04) || (__CORTEX_M == 0x07) */ - -#elif defined ( __GNUC__ ) /*------------------ GNU Compiler ---------------------*/ +#elif defined(__GNUC__) /*------------------ GNU Compiler ---------------------*/ /* GNU gcc specific functions */ /** \brief Enable IRQ Interrupts @@ -314,257 +293,277 @@ __STATIC_INLINE void __set_FPSCR(uint32_t fpscr) This function enables IRQ interrupts by clearing the I-bit in the CPSR. Can only be executed in Privileged modes. */ -__attribute__( ( always_inline ) ) __STATIC_INLINE void __enable_irq(void) +__attribute__((always_inline)) __STATIC_INLINE void __enable_irq(void) { - __ASM volatile ("cpsie i" : : : "memory"); + __ASM volatile("cpsie i" + : + : + : "memory"); } - /** \brief Disable IRQ Interrupts This function disables IRQ interrupts by setting the I-bit in the CPSR. Can only be executed in Privileged modes. */ -__attribute__( ( always_inline ) ) __STATIC_INLINE void __disable_irq(void) +__attribute__((always_inline)) __STATIC_INLINE void __disable_irq(void) { - __ASM volatile ("cpsid i" : : : "memory"); + __ASM volatile("cpsid i" + : + : + : "memory"); } - /** \brief Get Control Register This function returns the content of the Control Register. \return Control Register value */ -__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_CONTROL(void) +__attribute__((always_inline)) __STATIC_INLINE uint32_t __get_CONTROL(void) { - uint32_t result; + uint32_t result; - __ASM volatile ("MRS %0, control" : "=r" (result) ); - return(result); + __ASM volatile("MRS %0, control" + : "=r"(result)); + return (result); } - /** \brief Set Control Register This function writes the given value to the Control Register. \param [in] control Control Register value to set */ -__attribute__( ( always_inline ) ) __STATIC_INLINE void __set_CONTROL(uint32_t control) +__attribute__((always_inline)) __STATIC_INLINE void __set_CONTROL(uint32_t control) { - __ASM volatile ("MSR control, %0" : : "r" (control) : "memory"); + __ASM volatile("MSR control, %0" + : + : "r"(control) + : "memory"); } - /** \brief Get IPSR Register This function returns the content of the IPSR Register. \return IPSR Register value */ -__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_IPSR(void) +__attribute__((always_inline)) __STATIC_INLINE uint32_t __get_IPSR(void) { - uint32_t result; + uint32_t result; - __ASM volatile ("MRS %0, ipsr" : "=r" (result) ); - return(result); + __ASM volatile("MRS %0, ipsr" + : "=r"(result)); + return (result); } - /** \brief Get APSR Register This function returns the content of the APSR Register. \return APSR Register value */ -__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_APSR(void) +__attribute__((always_inline)) __STATIC_INLINE uint32_t __get_APSR(void) { - uint32_t result; + uint32_t result; - __ASM volatile ("MRS %0, apsr" : "=r" (result) ); - return(result); + __ASM volatile("MRS %0, apsr" + : "=r"(result)); + return (result); } - /** \brief Get xPSR Register This function returns the content of the xPSR Register. \return xPSR Register value */ -__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_xPSR(void) +__attribute__((always_inline)) __STATIC_INLINE uint32_t __get_xPSR(void) { - uint32_t result; + uint32_t result; - __ASM volatile ("MRS %0, xpsr" : "=r" (result) ); - return(result); + __ASM volatile("MRS %0, xpsr" + : "=r"(result)); + return (result); } - /** \brief Get Process Stack Pointer This function returns the current value of the Process Stack Pointer (PSP). \return PSP Register value */ -__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_PSP(void) +__attribute__((always_inline)) __STATIC_INLINE uint32_t __get_PSP(void) { - register uint32_t result; + register uint32_t result; - __ASM volatile ("MRS %0, psp\n" : "=r" (result) ); - return(result); + __ASM volatile("MRS %0, psp\n" + : "=r"(result)); + return (result); } - /** \brief Set Process Stack Pointer This function assigns the given value to the Process Stack Pointer (PSP). \param [in] topOfProcStack Process Stack Pointer value to set */ -__attribute__( ( always_inline ) ) __STATIC_INLINE void __set_PSP(uint32_t topOfProcStack) +__attribute__((always_inline)) __STATIC_INLINE void __set_PSP(uint32_t topOfProcStack) { - __ASM volatile ("MSR psp, %0\n" : : "r" (topOfProcStack) : "sp"); + __ASM volatile("MSR psp, %0\n" + : + : "r"(topOfProcStack) + : "sp"); } - /** \brief Get Main Stack Pointer This function returns the current value of the Main Stack Pointer (MSP). \return MSP Register value */ -__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_MSP(void) +__attribute__((always_inline)) __STATIC_INLINE uint32_t __get_MSP(void) { - register uint32_t result; + register uint32_t result; - __ASM volatile ("MRS %0, msp\n" : "=r" (result) ); - return(result); + __ASM volatile("MRS %0, msp\n" + : "=r"(result)); + return (result); } - /** \brief Set Main Stack Pointer This function assigns the given value to the Main Stack Pointer (MSP). \param [in] topOfMainStack Main Stack Pointer value to set */ -__attribute__( ( always_inline ) ) __STATIC_INLINE void __set_MSP(uint32_t topOfMainStack) +__attribute__((always_inline)) __STATIC_INLINE void __set_MSP(uint32_t topOfMainStack) { - __ASM volatile ("MSR msp, %0\n" : : "r" (topOfMainStack) : "sp"); + __ASM volatile("MSR msp, %0\n" + : + : "r"(topOfMainStack) + : "sp"); } - /** \brief Get Priority Mask This function returns the current state of the priority mask bit from the Priority Mask Register. \return Priority Mask value */ -__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_PRIMASK(void) +__attribute__((always_inline)) __STATIC_INLINE uint32_t __get_PRIMASK(void) { - uint32_t result; + uint32_t result; - __ASM volatile ("MRS %0, primask" : "=r" (result) ); - return(result); + __ASM volatile("MRS %0, primask" + : "=r"(result)); + return (result); } - /** \brief Set Priority Mask This function assigns the given value to the Priority Mask Register. \param [in] priMask Priority Mask */ -__attribute__( ( always_inline ) ) __STATIC_INLINE void __set_PRIMASK(uint32_t priMask) +__attribute__((always_inline)) __STATIC_INLINE void __set_PRIMASK(uint32_t priMask) { - __ASM volatile ("MSR primask, %0" : : "r" (priMask) : "memory"); + __ASM volatile("MSR primask, %0" + : + : "r"(priMask) + : "memory"); } - -#if (__CORTEX_M >= 0x03) +#if (__CORTEX_M >= 0x03) /** \brief Enable FIQ This function enables FIQ interrupts by clearing the F-bit in the CPSR. Can only be executed in Privileged modes. */ -__attribute__( ( always_inline ) ) __STATIC_INLINE void __enable_fault_irq(void) +__attribute__((always_inline)) __STATIC_INLINE void __enable_fault_irq(void) { - __ASM volatile ("cpsie f" : : : "memory"); + __ASM volatile("cpsie f" + : + : + : "memory"); } - /** \brief Disable FIQ This function disables FIQ interrupts by setting the F-bit in the CPSR. Can only be executed in Privileged modes. */ -__attribute__( ( always_inline ) ) __STATIC_INLINE void __disable_fault_irq(void) +__attribute__((always_inline)) __STATIC_INLINE void __disable_fault_irq(void) { - __ASM volatile ("cpsid f" : : : "memory"); + __ASM volatile("cpsid f" + : + : + : "memory"); } - /** \brief Get Base Priority This function returns the current value of the Base Priority register. \return Base Priority register value */ -__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_BASEPRI(void) +__attribute__((always_inline)) __STATIC_INLINE uint32_t __get_BASEPRI(void) { - uint32_t result; + uint32_t result; - __ASM volatile ("MRS %0, basepri_max" : "=r" (result) ); - return(result); + __ASM volatile("MRS %0, basepri_max" + : "=r"(result)); + return (result); } - /** \brief Set Base Priority This function assigns the given value to the Base Priority register. \param [in] basePri Base Priority value to set */ -__attribute__( ( always_inline ) ) __STATIC_INLINE void __set_BASEPRI(uint32_t value) +__attribute__((always_inline)) __STATIC_INLINE void __set_BASEPRI(uint32_t value) { - __ASM volatile ("MSR basepri, %0" : : "r" (value) : "memory"); + __ASM volatile("MSR basepri, %0" + : + : "r"(value) + : "memory"); } - /** \brief Get Fault Mask This function returns the current value of the Fault Mask register. \return Fault Mask register value */ -__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_FAULTMASK(void) +__attribute__((always_inline)) __STATIC_INLINE uint32_t __get_FAULTMASK(void) { - uint32_t result; + uint32_t result; - __ASM volatile ("MRS %0, faultmask" : "=r" (result) ); - return(result); + __ASM volatile("MRS %0, faultmask" + : "=r"(result)); + return (result); } - /** \brief Set Fault Mask This function assigns the given value to the Fault Mask register. \param [in] faultMask Fault Mask value to set */ -__attribute__( ( always_inline ) ) __STATIC_INLINE void __set_FAULTMASK(uint32_t faultMask) +__attribute__((always_inline)) __STATIC_INLINE void __set_FAULTMASK(uint32_t faultMask) { - __ASM volatile ("MSR faultmask, %0" : : "r" (faultMask) : "memory"); + __ASM volatile("MSR faultmask, %0" + : + : "r"(faultMask) + : "memory"); } #endif /* (__CORTEX_M >= 0x03) */ - -#if (__CORTEX_M == 0x04) || (__CORTEX_M == 0x07) +#if (__CORTEX_M == 0x04) || (__CORTEX_M == 0x07) /** \brief Get FPSCR @@ -572,52 +571,52 @@ __attribute__( ( always_inline ) ) __STATIC_INLINE void __set_FAULTMASK(uint32_t \return Floating Point Status/Control register value */ -__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_FPSCR(void) +__attribute__((always_inline)) __STATIC_INLINE uint32_t __get_FPSCR(void) { #if (__FPU_PRESENT == 1) && (__FPU_USED == 1) - uint32_t result; + uint32_t result; - /* Empty asm statement works as a scheduling barrier */ - __ASM volatile (""); - __ASM volatile ("VMRS %0, fpscr" : "=r" (result) ); - __ASM volatile (""); - return(result); + /* Empty asm statement works as a scheduling barrier */ + __ASM volatile(""); + __ASM volatile("VMRS %0, fpscr" + : "=r"(result)); + __ASM volatile(""); + return (result); #else - return(0); + return (0); #endif } - /** \brief Set FPSCR This function assigns the given value to the Floating Point Status/Control register. \param [in] fpscr Floating Point Status/Control value to set */ -__attribute__( ( always_inline ) ) __STATIC_INLINE void __set_FPSCR(uint32_t fpscr) +__attribute__((always_inline)) __STATIC_INLINE void __set_FPSCR(uint32_t fpscr) { #if (__FPU_PRESENT == 1) && (__FPU_USED == 1) - /* Empty asm statement works as a scheduling barrier */ - __ASM volatile (""); - __ASM volatile ("VMSR fpscr, %0" : : "r" (fpscr) : "vfpcc"); - __ASM volatile (""); + /* Empty asm statement works as a scheduling barrier */ + __ASM volatile(""); + __ASM volatile("VMSR fpscr, %0" + : + : "r"(fpscr) + : "vfpcc"); + __ASM volatile(""); #endif } #endif /* (__CORTEX_M == 0x04) || (__CORTEX_M == 0x07) */ - -#elif defined ( __ICCARM__ ) /*------------------ ICC Compiler -------------------*/ +#elif defined(__ICCARM__) /*------------------ ICC Compiler -------------------*/ /* IAR iccarm specific functions */ #include <cmsis_iar.h> - -#elif defined ( __TMS470__ ) /*---------------- TI CCS Compiler ------------------*/ +#elif defined(__TMS470__) /*---------------- TI CCS Compiler ------------------*/ /* TI CCS specific functions */ #include <cmsis_ccs.h> - -#elif defined ( __TASKING__ ) /*------------------ TASKING Compiler --------------*/ +#elif defined(__TASKING__) /*------------------ TASKING Compiler --------------*/ /* TASKING carm specific functions */ /* * The CMSIS functions have been implemented as intrinsics in the compiler. @@ -625,8 +624,7 @@ __attribute__( ( always_inline ) ) __STATIC_INLINE void __set_FPSCR(uint32_t fps * Including the CMSIS ones. */ - -#elif defined ( __CSMC__ ) /*------------------ COSMIC Compiler -------------------*/ +#elif defined(__CSMC__) /*------------------ COSMIC Compiler -------------------*/ /* Cosmic specific functions */ #include <cmsis_csm.h> diff --git a/bsp/swm320-lq100/Libraries/CMSIS/CoreSupport/core_cmInstr.h b/bsp/swm320-lq100/Libraries/CMSIS/CoreSupport/core_cmInstr.h index d14110b2ab..6d1a9e9f8f 100644 --- a/bsp/swm320-lq100/Libraries/CMSIS/CoreSupport/core_cmInstr.h +++ b/bsp/swm320-lq100/Libraries/CMSIS/CoreSupport/core_cmInstr.h @@ -1,4 +1,4 @@ -/**************************************************************************//** +/**************************************************************************/ /** * @file core_cmInstr.h * @brief CMSIS Cortex-M Core Instruction Access Header File * @version V4.00 @@ -34,54 +34,47 @@ POSSIBILITY OF SUCH DAMAGE. ---------------------------------------------------------------------------*/ - #ifndef __CORE_CMINSTR_H #define __CORE_CMINSTR_H - /* ########################## Core Instruction Access ######################### */ /** \defgroup CMSIS_Core_InstructionInterface CMSIS Core Instruction Interface Access to dedicated instructions @{ */ -#if defined ( __CC_ARM ) /*------------------RealView Compiler -----------------*/ +#if defined(__CC_ARM) /*------------------RealView Compiler -----------------*/ /* ARM armcc specific functions */ #if (__ARMCC_VERSION < 400677) - #error "Please use ARM Compiler Toolchain V4.0.677 or later!" +#error "Please use ARM Compiler Toolchain V4.0.677 or later!" #endif - /** \brief No Operation No Operation does nothing. This instruction can be used for code alignment purposes. */ -#define __NOP __nop - +#define __NOP __nop /** \brief Wait For Interrupt Wait For Interrupt is a hint instruction that suspends execution until one of a number of events occurs. */ -#define __WFI __wfi - +#define __WFI __wfi /** \brief Wait For Event Wait For Event is a hint instruction that permits the processor to enter a low-power state until one of a number of events occurs. */ -#define __WFE __wfe - +#define __WFE __wfe /** \brief Send Event Send Event is a hint instruction. It causes an event to be signaled to the CPU. */ -#define __SEV __sev - +#define __SEV __sev /** \brief Instruction Synchronization Barrier @@ -89,24 +82,21 @@ so that all instructions following the ISB are fetched from cache or memory, after the instruction has been completed. */ -#define __ISB() __isb(0xF) - +#define __ISB() __isb(0xF) /** \brief Data Synchronization Barrier This function acts as a special kind of Data Memory Barrier. It completes when all explicit memory accesses before this instruction complete. */ -#define __DSB() __dsb(0xF) - +#define __DSB() __dsb(0xF) /** \brief Data Memory Barrier This function ensures the apparent order of the explicit memory operations before and after the instruction, without ensuring their completion. */ -#define __DMB() __dmb(0xF) - +#define __DMB() __dmb(0xF) /** \brief Reverse byte order (32 bit) @@ -115,8 +105,7 @@ \param [in] value Value to reverse \return Reversed value */ -#define __REV __rev - +#define __REV __rev /** \brief Reverse byte order (16 bit) @@ -128,8 +117,8 @@ #ifndef __NO_EMBEDDED_ASM __attribute__((section(".rev16_text"))) __STATIC_INLINE __ASM uint32_t __REV16(uint32_t value) { - rev16 r0, r0 - bx lr + rev16 r0, r0 + bx lr } #endif @@ -143,12 +132,11 @@ __attribute__((section(".rev16_text"))) __STATIC_INLINE __ASM uint32_t __REV16(u #ifndef __NO_EMBEDDED_ASM __attribute__((section(".revsh_text"))) __STATIC_INLINE __ASM int32_t __REVSH(int32_t value) { - revsh r0, r0 - bx lr + revsh r0, r0 + bx lr } #endif - /** \brief Rotate Right in unsigned value (32 bit) This function Rotate Right (immediate) provides the value of the contents of a register rotated by a variable number of bits. @@ -157,8 +145,7 @@ __attribute__((section(".revsh_text"))) __STATIC_INLINE __ASM int32_t __REVSH(in \param [in] value Number of Bits to rotate \return Rotated value */ -#define __ROR __ror - +#define __ROR __ror /** \brief Breakpoint @@ -168,10 +155,9 @@ __attribute__((section(".revsh_text"))) __STATIC_INLINE __ASM int32_t __REVSH(in \param [in] value is ignored by the processor. If required, a debugger can use it to store additional information about the breakpoint. */ -#define __BKPT(value) __breakpoint(value) +#define __BKPT(value) __breakpoint(value) - -#if (__CORTEX_M >= 0x03) || (__CORTEX_SC >= 300) +#if (__CORTEX_M >= 0x03) || (__CORTEX_SC >= 300) /** \brief Reverse bit order of value @@ -180,8 +166,7 @@ __attribute__((section(".revsh_text"))) __STATIC_INLINE __ASM int32_t __REVSH(in \param [in] value Value to reverse \return Reversed value */ -#define __RBIT __rbit - +#define __RBIT __rbit /** \brief LDR Exclusive (8 bit) @@ -190,8 +175,7 @@ __attribute__((section(".revsh_text"))) __STATIC_INLINE __ASM int32_t __REVSH(in \param [in] ptr Pointer to data \return value of type uint8_t at (*ptr) */ -#define __LDREXB(ptr) ((uint8_t ) __ldrex(ptr)) - +#define __LDREXB(ptr) ((uint8_t)__ldrex(ptr)) /** \brief LDR Exclusive (16 bit) @@ -200,8 +184,7 @@ __attribute__((section(".revsh_text"))) __STATIC_INLINE __ASM int32_t __REVSH(in \param [in] ptr Pointer to data \return value of type uint16_t at (*ptr) */ -#define __LDREXH(ptr) ((uint16_t) __ldrex(ptr)) - +#define __LDREXH(ptr) ((uint16_t)__ldrex(ptr)) /** \brief LDR Exclusive (32 bit) @@ -210,8 +193,7 @@ __attribute__((section(".revsh_text"))) __STATIC_INLINE __ASM int32_t __REVSH(in \param [in] ptr Pointer to data \return value of type uint32_t at (*ptr) */ -#define __LDREXW(ptr) ((uint32_t ) __ldrex(ptr)) - +#define __LDREXW(ptr) ((uint32_t)__ldrex(ptr)) /** \brief STR Exclusive (8 bit) @@ -222,8 +204,7 @@ __attribute__((section(".revsh_text"))) __STATIC_INLINE __ASM int32_t __REVSH(in \return 0 Function succeeded \return 1 Function failed */ -#define __STREXB(value, ptr) __strex(value, ptr) - +#define __STREXB(value, ptr) __strex(value, ptr) /** \brief STR Exclusive (16 bit) @@ -234,8 +215,7 @@ __attribute__((section(".revsh_text"))) __STATIC_INLINE __ASM int32_t __REVSH(in \return 0 Function succeeded \return 1 Function failed */ -#define __STREXH(value, ptr) __strex(value, ptr) - +#define __STREXH(value, ptr) __strex(value, ptr) /** \brief STR Exclusive (32 bit) @@ -246,16 +226,14 @@ __attribute__((section(".revsh_text"))) __STATIC_INLINE __ASM int32_t __REVSH(in \return 0 Function succeeded \return 1 Function failed */ -#define __STREXW(value, ptr) __strex(value, ptr) - +#define __STREXW(value, ptr) __strex(value, ptr) /** \brief Remove the exclusive lock This function removes the exclusive lock which is created by LDREX. */ -#define __CLREX __clrex - +#define __CLREX __clrex /** \brief Signed Saturate @@ -265,8 +243,7 @@ __attribute__((section(".revsh_text"))) __STATIC_INLINE __ASM int32_t __REVSH(in \param [in] sat Bit position to saturate to (1..32) \return Saturated value */ -#define __SSAT __ssat - +#define __SSAT __ssat /** \brief Unsigned Saturate @@ -276,8 +253,7 @@ __attribute__((section(".revsh_text"))) __STATIC_INLINE __ASM int32_t __REVSH(in \param [in] sat Bit position to saturate to (0..31) \return Saturated value */ -#define __USAT __usat - +#define __USAT __usat /** \brief Count leading zeros @@ -286,8 +262,7 @@ __attribute__((section(".revsh_text"))) __STATIC_INLINE __ASM int32_t __REVSH(in \param [in] value Value to count the leading zeros \return number of leading zeros in value */ -#define __CLZ __clz - +#define __CLZ __clz /** \brief Rotate Right with Extend (32 bit) @@ -299,12 +274,11 @@ __attribute__((section(".revsh_text"))) __STATIC_INLINE __ASM int32_t __REVSH(in #ifndef __NO_EMBEDDED_ASM __attribute__((section(".rrx_text"))) __STATIC_INLINE __ASM uint32_t __RRX(uint32_t value) { - rrx r0, r0 - bx lr + rrx r0, r0 + bx lr } #endif - /** \brief LDRT Unprivileged (8 bit) This function executes a Unprivileged LDRT instruction for 8 bit value. @@ -312,8 +286,7 @@ __attribute__((section(".rrx_text"))) __STATIC_INLINE __ASM uint32_t __RRX(uint3 \param [in] ptr Pointer to data \return value of type uint8_t at (*ptr) */ -#define __LDRBT(ptr) ((uint8_t ) __ldrt(ptr)) - +#define __LDRBT(ptr) ((uint8_t)__ldrt(ptr)) /** \brief LDRT Unprivileged (16 bit) @@ -322,8 +295,7 @@ __attribute__((section(".rrx_text"))) __STATIC_INLINE __ASM uint32_t __RRX(uint3 \param [in] ptr Pointer to data \return value of type uint16_t at (*ptr) */ -#define __LDRHT(ptr) ((uint16_t) __ldrt(ptr)) - +#define __LDRHT(ptr) ((uint16_t)__ldrt(ptr)) /** \brief LDRT Unprivileged (32 bit) @@ -332,8 +304,7 @@ __attribute__((section(".rrx_text"))) __STATIC_INLINE __ASM uint32_t __RRX(uint3 \param [in] ptr Pointer to data \return value of type uint32_t at (*ptr) */ -#define __LDRT(ptr) ((uint32_t ) __ldrt(ptr)) - +#define __LDRT(ptr) ((uint32_t)__ldrt(ptr)) /** \brief STRT Unprivileged (8 bit) @@ -342,8 +313,7 @@ __attribute__((section(".rrx_text"))) __STATIC_INLINE __ASM uint32_t __RRX(uint3 \param [in] value Value to store \param [in] ptr Pointer to location */ -#define __STRBT(value, ptr) __strt(value, ptr) - +#define __STRBT(value, ptr) __strt(value, ptr) /** \brief STRT Unprivileged (16 bit) @@ -352,8 +322,7 @@ __attribute__((section(".rrx_text"))) __STATIC_INLINE __ASM uint32_t __RRX(uint3 \param [in] value Value to store \param [in] ptr Pointer to location */ -#define __STRHT(value, ptr) __strt(value, ptr) - +#define __STRHT(value, ptr) __strt(value, ptr) /** \brief STRT Unprivileged (32 bit) @@ -362,101 +331,93 @@ __attribute__((section(".rrx_text"))) __STATIC_INLINE __ASM uint32_t __RRX(uint3 \param [in] value Value to store \param [in] ptr Pointer to location */ -#define __STRT(value, ptr) __strt(value, ptr) +#define __STRT(value, ptr) __strt(value, ptr) #endif /* (__CORTEX_M >= 0x03) || (__CORTEX_SC >= 300) */ - -#elif defined ( __GNUC__ ) /*------------------ GNU Compiler ---------------------*/ +#elif defined(__GNUC__) /*------------------ GNU Compiler ---------------------*/ /* GNU gcc specific functions */ /* Define macros for porting to both thumb1 and thumb2. * For thumb1, use low register (r0-r7), specified by constrant "l" * Otherwise, use general registers, specified by constrant "r" */ -#if defined (__thumb__) && !defined (__thumb2__) -#define __CMSIS_GCC_OUT_REG(r) "=l" (r) -#define __CMSIS_GCC_USE_REG(r) "l" (r) +#if defined(__thumb__) && !defined(__thumb2__) +#define __CMSIS_GCC_OUT_REG(r) "=l"(r) +#define __CMSIS_GCC_USE_REG(r) "l"(r) #else -#define __CMSIS_GCC_OUT_REG(r) "=r" (r) -#define __CMSIS_GCC_USE_REG(r) "r" (r) +#define __CMSIS_GCC_OUT_REG(r) "=r"(r) +#define __CMSIS_GCC_USE_REG(r) "r"(r) #endif /** \brief No Operation No Operation does nothing. This instruction can be used for code alignment purposes. */ -__attribute__( ( always_inline ) ) __STATIC_INLINE void __NOP(void) +__attribute__((always_inline)) __STATIC_INLINE void __NOP(void) { - __ASM volatile ("nop"); + __ASM volatile("nop"); } - /** \brief Wait For Interrupt Wait For Interrupt is a hint instruction that suspends execution until one of a number of events occurs. */ -__attribute__( ( always_inline ) ) __STATIC_INLINE void __WFI(void) +__attribute__((always_inline)) __STATIC_INLINE void __WFI(void) { - __ASM volatile ("wfi"); + __ASM volatile("wfi"); } - /** \brief Wait For Event Wait For Event is a hint instruction that permits the processor to enter a low-power state until one of a number of events occurs. */ -__attribute__( ( always_inline ) ) __STATIC_INLINE void __WFE(void) +__attribute__((always_inline)) __STATIC_INLINE void __WFE(void) { - __ASM volatile ("wfe"); + __ASM volatile("wfe"); } - /** \brief Send Event Send Event is a hint instruction. It causes an event to be signaled to the CPU. */ -__attribute__( ( always_inline ) ) __STATIC_INLINE void __SEV(void) +__attribute__((always_inline)) __STATIC_INLINE void __SEV(void) { - __ASM volatile ("sev"); + __ASM volatile("sev"); } - /** \brief Instruction Synchronization Barrier Instruction Synchronization Barrier flushes the pipeline in the processor, so that all instructions following the ISB are fetched from cache or memory, after the instruction has been completed. */ -__attribute__( ( always_inline ) ) __STATIC_INLINE void __ISB(void) +__attribute__((always_inline)) __STATIC_INLINE void __ISB(void) { - __ASM volatile ("isb"); + __ASM volatile("isb"); } - /** \brief Data Synchronization Barrier This function acts as a special kind of Data Memory Barrier. It completes when all explicit memory accesses before this instruction complete. */ -__attribute__( ( always_inline ) ) __STATIC_INLINE void __DSB(void) +__attribute__((always_inline)) __STATIC_INLINE void __DSB(void) { - __ASM volatile ("dsb"); + __ASM volatile("dsb"); } - /** \brief Data Memory Barrier This function ensures the apparent order of the explicit memory operations before and after the instruction, without ensuring their completion. */ -__attribute__( ( always_inline ) ) __STATIC_INLINE void __DMB(void) +__attribute__((always_inline)) __STATIC_INLINE void __DMB(void) { - __ASM volatile ("dmb"); + __ASM volatile("dmb"); } - /** \brief Reverse byte order (32 bit) This function reverses the byte order in integer value. @@ -464,19 +425,20 @@ __attribute__( ( always_inline ) ) __STATIC_INLINE void __DMB(void) \param [in] value Value to reverse \return Reversed value */ -__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __REV(uint32_t value) +__attribute__((always_inline)) __STATIC_INLINE uint32_t __REV(uint32_t value) { #if (__GNUC__ > 4) || (__GNUC__ == 4 && __GNUC_MINOR__ >= 5) - return __builtin_bswap32(value); + return __builtin_bswap32(value); #else - uint32_t result; + uint32_t result; - __ASM volatile ("rev %0, %1" : __CMSIS_GCC_OUT_REG (result) : __CMSIS_GCC_USE_REG (value) ); - return(result); + __ASM volatile("rev %0, %1" + : __CMSIS_GCC_OUT_REG(result) + : __CMSIS_GCC_USE_REG(value)); + return (result); #endif } - /** \brief Reverse byte order (16 bit) This function reverses the byte order in two unsigned short values. @@ -484,15 +446,16 @@ __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __REV(uint32_t value \param [in] value Value to reverse \return Reversed value */ -__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __REV16(uint32_t value) +__attribute__((always_inline)) __STATIC_INLINE uint32_t __REV16(uint32_t value) { - uint32_t result; + uint32_t result; - __ASM volatile ("rev16 %0, %1" : __CMSIS_GCC_OUT_REG (result) : __CMSIS_GCC_USE_REG (value) ); - return(result); + __ASM volatile("rev16 %0, %1" + : __CMSIS_GCC_OUT_REG(result) + : __CMSIS_GCC_USE_REG(value)); + return (result); } - /** \brief Reverse byte order in signed short value This function reverses the byte order in a signed short value with sign extension to integer. @@ -500,19 +463,20 @@ __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __REV16(uint32_t val \param [in] value Value to reverse \return Reversed value */ -__attribute__( ( always_inline ) ) __STATIC_INLINE int32_t __REVSH(int32_t value) +__attribute__((always_inline)) __STATIC_INLINE int32_t __REVSH(int32_t value) { #if (__GNUC__ > 4) || (__GNUC__ == 4 && __GNUC_MINOR__ >= 8) - return (short)__builtin_bswap16(value); + return (short)__builtin_bswap16(value); #else - uint32_t result; + uint32_t result; - __ASM volatile ("revsh %0, %1" : __CMSIS_GCC_OUT_REG (result) : __CMSIS_GCC_USE_REG (value) ); - return(result); + __ASM volatile("revsh %0, %1" + : __CMSIS_GCC_OUT_REG(result) + : __CMSIS_GCC_USE_REG(value)); + return (result); #endif } - /** \brief Rotate Right in unsigned value (32 bit) This function Rotate Right (immediate) provides the value of the contents of a register rotated by a variable number of bits. @@ -521,12 +485,11 @@ __attribute__( ( always_inline ) ) __STATIC_INLINE int32_t __REVSH(int32_t value \param [in] value Number of Bits to rotate \return Rotated value */ -__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __ROR(uint32_t op1, uint32_t op2) +__attribute__((always_inline)) __STATIC_INLINE uint32_t __ROR(uint32_t op1, uint32_t op2) { - return (op1 >> op2) | (op1 << (32 - op2)); + return (op1 >> op2) | (op1 << (32 - op2)); } - /** \brief Breakpoint This function causes the processor to enter Debug state. @@ -535,10 +498,9 @@ __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __ROR(uint32_t op1, \param [in] value is ignored by the processor. If required, a debugger can use it to store additional information about the breakpoint. */ -#define __BKPT(value) __ASM volatile ("bkpt "#value) - +#define __BKPT(value) __ASM volatile("bkpt " #value) -#if (__CORTEX_M >= 0x03) || (__CORTEX_SC >= 300) +#if (__CORTEX_M >= 0x03) || (__CORTEX_SC >= 300) /** \brief Reverse bit order of value @@ -547,15 +509,16 @@ __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __ROR(uint32_t op1, \param [in] value Value to reverse \return Reversed value */ -__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __RBIT(uint32_t value) +__attribute__((always_inline)) __STATIC_INLINE uint32_t __RBIT(uint32_t value) { - uint32_t result; + uint32_t result; - __ASM volatile ("rbit %0, %1" : "=r" (result) : "r" (value) ); - return(result); + __ASM volatile("rbit %0, %1" + : "=r"(result) + : "r"(value)); + return (result); } - /** \brief LDR Exclusive (8 bit) This function executes a exclusive LDR instruction for 8 bit value. @@ -563,22 +526,26 @@ __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __RBIT(uint32_t valu \param [in] ptr Pointer to data \return value of type uint8_t at (*ptr) */ -__attribute__( ( always_inline ) ) __STATIC_INLINE uint8_t __LDREXB(volatile uint8_t *addr) +__attribute__((always_inline)) __STATIC_INLINE uint8_t __LDREXB(volatile uint8_t *addr) { uint32_t result; #if (__GNUC__ > 4) || (__GNUC__ == 4 && __GNUC_MINOR__ >= 8) - __ASM volatile ("ldrexb %0, %1" : "=r" (result) : "Q" (*addr) ); + __ASM volatile("ldrexb %0, %1" + : "=r"(result) + : "Q"(*addr)); #else /* Prior to GCC 4.8, "Q" will be expanded to [rx, #0] which is not accepted by assembler. So has to use following less efficient pattern. */ - __ASM volatile ("ldrexb %0, [%1]" : "=r" (result) : "r" (addr) : "memory" ); + __ASM volatile("ldrexb %0, [%1]" + : "=r"(result) + : "r"(addr) + : "memory"); #endif - return ((uint8_t) result); /* Add explicit type cast here */ + return ((uint8_t)result); /* Add explicit type cast here */ } - /** \brief LDR Exclusive (16 bit) This function executes a exclusive LDR instruction for 16 bit values. @@ -586,22 +553,26 @@ __attribute__( ( always_inline ) ) __STATIC_INLINE uint8_t __LDREXB(volatile uin \param [in] ptr Pointer to data \return value of type uint16_t at (*ptr) */ -__attribute__( ( always_inline ) ) __STATIC_INLINE uint16_t __LDREXH(volatile uint16_t *addr) +__attribute__((always_inline)) __STATIC_INLINE uint16_t __LDREXH(volatile uint16_t *addr) { uint32_t result; #if (__GNUC__ > 4) || (__GNUC__ == 4 && __GNUC_MINOR__ >= 8) - __ASM volatile ("ldrexh %0, %1" : "=r" (result) : "Q" (*addr) ); + __ASM volatile("ldrexh %0, %1" + : "=r"(result) + : "Q"(*addr)); #else /* Prior to GCC 4.8, "Q" will be expanded to [rx, #0] which is not accepted by assembler. So has to use following less efficient pattern. */ - __ASM volatile ("ldrexh %0, [%1]" : "=r" (result) : "r" (addr) : "memory" ); + __ASM volatile("ldrexh %0, [%1]" + : "=r"(result) + : "r"(addr) + : "memory"); #endif - return ((uint16_t) result); /* Add explicit type cast here */ + return ((uint16_t)result); /* Add explicit type cast here */ } - /** \brief LDR Exclusive (32 bit) This function executes a exclusive LDR instruction for 32 bit values. @@ -609,15 +580,16 @@ __attribute__( ( always_inline ) ) __STATIC_INLINE uint16_t __LDREXH(volatile ui \param [in] ptr Pointer to data \return value of type uint32_t at (*ptr) */ -__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __LDREXW(volatile uint32_t *addr) +__attribute__((always_inline)) __STATIC_INLINE uint32_t __LDREXW(volatile uint32_t *addr) { uint32_t result; - __ASM volatile ("ldrex %0, %1" : "=r" (result) : "Q" (*addr) ); - return(result); + __ASM volatile("ldrex %0, %1" + : "=r"(result) + : "Q"(*addr)); + return (result); } - /** \brief STR Exclusive (8 bit) This function executes a exclusive STR instruction for 8 bit values. @@ -627,15 +599,16 @@ __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __LDREXW(volatile ui \return 0 Function succeeded \return 1 Function failed */ -__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __STREXB(uint8_t value, volatile uint8_t *addr) +__attribute__((always_inline)) __STATIC_INLINE uint32_t __STREXB(uint8_t value, volatile uint8_t *addr) { - uint32_t result; + uint32_t result; - __ASM volatile ("strexb %0, %2, %1" : "=&r" (result), "=Q" (*addr) : "r" ((uint32_t)value) ); - return(result); + __ASM volatile("strexb %0, %2, %1" + : "=&r"(result), "=Q"(*addr) + : "r"((uint32_t)value)); + return (result); } - /** \brief STR Exclusive (16 bit) This function executes a exclusive STR instruction for 16 bit values. @@ -645,15 +618,16 @@ __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __STREXB(uint8_t val \return 0 Function succeeded \return 1 Function failed */ -__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __STREXH(uint16_t value, volatile uint16_t *addr) +__attribute__((always_inline)) __STATIC_INLINE uint32_t __STREXH(uint16_t value, volatile uint16_t *addr) { - uint32_t result; + uint32_t result; - __ASM volatile ("strexh %0, %2, %1" : "=&r" (result), "=Q" (*addr) : "r" ((uint32_t)value) ); - return(result); + __ASM volatile("strexh %0, %2, %1" + : "=&r"(result), "=Q"(*addr) + : "r"((uint32_t)value)); + return (result); } - /** \brief STR Exclusive (32 bit) This function executes a exclusive STR instruction for 32 bit values. @@ -663,26 +637,27 @@ __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __STREXH(uint16_t va \return 0 Function succeeded \return 1 Function failed */ -__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __STREXW(uint32_t value, volatile uint32_t *addr) +__attribute__((always_inline)) __STATIC_INLINE uint32_t __STREXW(uint32_t value, volatile uint32_t *addr) { - uint32_t result; + uint32_t result; - __ASM volatile ("strex %0, %2, %1" : "=&r" (result), "=Q" (*addr) : "r" (value) ); - return(result); + __ASM volatile("strex %0, %2, %1" + : "=&r"(result), "=Q"(*addr) + : "r"(value)); + return (result); } - /** \brief Remove the exclusive lock This function removes the exclusive lock which is created by LDREX. */ -__attribute__( ( always_inline ) ) __STATIC_INLINE void __CLREX(void) +__attribute__((always_inline)) __STATIC_INLINE void __CLREX(void) { - __ASM volatile ("clrex" ::: "memory"); + __ASM volatile("clrex" :: + : "memory"); } - /** \brief Signed Saturate This function saturates a signed value. @@ -691,13 +666,15 @@ __attribute__( ( always_inline ) ) __STATIC_INLINE void __CLREX(void) \param [in] sat Bit position to saturate to (1..32) \return Saturated value */ -#define __SSAT(ARG1,ARG2) \ -({ \ - uint32_t __RES, __ARG1 = (ARG1); \ - __ASM ("ssat %0, %1, %2" : "=r" (__RES) : "I" (ARG2), "r" (__ARG1) ); \ - __RES; \ - }) - +#define __SSAT(ARG1, ARG2) \ + ( \ + { \ + uint32_t __RES, __ARG1 = (ARG1); \ + __ASM("ssat %0, %1, %2" \ + : "=r"(__RES) \ + : "I"(ARG2), "r"(__ARG1)); \ + __RES; \ + }) /** \brief Unsigned Saturate @@ -707,13 +684,15 @@ __attribute__( ( always_inline ) ) __STATIC_INLINE void __CLREX(void) \param [in] sat Bit position to saturate to (0..31) \return Saturated value */ -#define __USAT(ARG1,ARG2) \ -({ \ - uint32_t __RES, __ARG1 = (ARG1); \ - __ASM ("usat %0, %1, %2" : "=r" (__RES) : "I" (ARG2), "r" (__ARG1) ); \ - __RES; \ - }) - +#define __USAT(ARG1, ARG2) \ + ( \ + { \ + uint32_t __RES, __ARG1 = (ARG1); \ + __ASM("usat %0, %1, %2" \ + : "=r"(__RES) \ + : "I"(ARG2), "r"(__ARG1)); \ + __RES; \ + }) /** \brief Count leading zeros @@ -722,15 +701,16 @@ __attribute__( ( always_inline ) ) __STATIC_INLINE void __CLREX(void) \param [in] value Value to count the leading zeros \return number of leading zeros in value */ -__attribute__( ( always_inline ) ) __STATIC_INLINE uint8_t __CLZ(uint32_t value) +__attribute__((always_inline)) __STATIC_INLINE uint8_t __CLZ(uint32_t value) { - uint32_t result; + uint32_t result; - __ASM volatile ("clz %0, %1" : "=r" (result) : "r" (value) ); - return ((uint8_t) result); /* Add explicit type cast here */ + __ASM volatile("clz %0, %1" + : "=r"(result) + : "r"(value)); + return ((uint8_t)result); /* Add explicit type cast here */ } - /** \brief Rotate Right with Extend (32 bit) This function moves each bit of a bitstring right by one bit. The carry input is shifted in at the left end of the bitstring. @@ -738,15 +718,16 @@ __attribute__( ( always_inline ) ) __STATIC_INLINE uint8_t __CLZ(uint32_t value) \param [in] value Value to rotate \return Rotated value */ -__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __RRX(uint32_t value) +__attribute__((always_inline)) __STATIC_INLINE uint32_t __RRX(uint32_t value) { - uint32_t result; + uint32_t result; - __ASM volatile ("rrx %0, %1" : __CMSIS_GCC_OUT_REG (result) : __CMSIS_GCC_USE_REG (value) ); - return(result); + __ASM volatile("rrx %0, %1" + : __CMSIS_GCC_OUT_REG(result) + : __CMSIS_GCC_USE_REG(value)); + return (result); } - /** \brief LDRT Unprivileged (8 bit) This function executes a Unprivileged LDRT instruction for 8 bit value. @@ -754,22 +735,26 @@ __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __RRX(uint32_t value \param [in] ptr Pointer to data \return value of type uint8_t at (*ptr) */ -__attribute__( ( always_inline ) ) __STATIC_INLINE uint8_t __LDRBT(volatile uint8_t *addr) +__attribute__((always_inline)) __STATIC_INLINE uint8_t __LDRBT(volatile uint8_t *addr) { uint32_t result; #if (__GNUC__ > 4) || (__GNUC__ == 4 && __GNUC_MINOR__ >= 8) - __ASM volatile ("ldrbt %0, %1" : "=r" (result) : "Q" (*addr) ); + __ASM volatile("ldrbt %0, %1" + : "=r"(result) + : "Q"(*addr)); #else /* Prior to GCC 4.8, "Q" will be expanded to [rx, #0] which is not accepted by assembler. So has to use following less efficient pattern. */ - __ASM volatile ("ldrbt %0, [%1]" : "=r" (result) : "r" (addr) : "memory" ); + __ASM volatile("ldrbt %0, [%1]" + : "=r"(result) + : "r"(addr) + : "memory"); #endif - return ((uint8_t) result); /* Add explicit type cast here */ + return ((uint8_t)result); /* Add explicit type cast here */ } - /** \brief LDRT Unprivileged (16 bit) This function executes a Unprivileged LDRT instruction for 16 bit values. @@ -777,22 +762,26 @@ __attribute__( ( always_inline ) ) __STATIC_INLINE uint8_t __LDRBT(volatile uint \param [in] ptr Pointer to data \return value of type uint16_t at (*ptr) */ -__attribute__( ( always_inline ) ) __STATIC_INLINE uint16_t __LDRHT(volatile uint16_t *addr) +__attribute__((always_inline)) __STATIC_INLINE uint16_t __LDRHT(volatile uint16_t *addr) { uint32_t result; #if (__GNUC__ > 4) || (__GNUC__ == 4 && __GNUC_MINOR__ >= 8) - __ASM volatile ("ldrht %0, %1" : "=r" (result) : "Q" (*addr) ); + __ASM volatile("ldrht %0, %1" + : "=r"(result) + : "Q"(*addr)); #else /* Prior to GCC 4.8, "Q" will be expanded to [rx, #0] which is not accepted by assembler. So has to use following less efficient pattern. */ - __ASM volatile ("ldrht %0, [%1]" : "=r" (result) : "r" (addr) : "memory" ); + __ASM volatile("ldrht %0, [%1]" + : "=r"(result) + : "r"(addr) + : "memory"); #endif - return ((uint16_t) result); /* Add explicit type cast here */ + return ((uint16_t)result); /* Add explicit type cast here */ } - /** \brief LDRT Unprivileged (32 bit) This function executes a Unprivileged LDRT instruction for 32 bit values. @@ -800,15 +789,16 @@ __attribute__( ( always_inline ) ) __STATIC_INLINE uint16_t __LDRHT(volatile uin \param [in] ptr Pointer to data \return value of type uint32_t at (*ptr) */ -__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __LDRT(volatile uint32_t *addr) +__attribute__((always_inline)) __STATIC_INLINE uint32_t __LDRT(volatile uint32_t *addr) { uint32_t result; - __ASM volatile ("ldrt %0, %1" : "=r" (result) : "Q" (*addr) ); - return(result); + __ASM volatile("ldrt %0, %1" + : "=r"(result) + : "Q"(*addr)); + return (result); } - /** \brief STRT Unprivileged (8 bit) This function executes a Unprivileged STRT instruction for 8 bit values. @@ -816,12 +806,13 @@ __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __LDRT(volatile uint \param [in] value Value to store \param [in] ptr Pointer to location */ -__attribute__( ( always_inline ) ) __STATIC_INLINE void __STRBT(uint8_t value, volatile uint8_t *addr) +__attribute__((always_inline)) __STATIC_INLINE void __STRBT(uint8_t value, volatile uint8_t *addr) { - __ASM volatile ("strbt %1, %0" : "=Q" (*addr) : "r" ((uint32_t)value) ); + __ASM volatile("strbt %1, %0" + : "=Q"(*addr) + : "r"((uint32_t)value)); } - /** \brief STRT Unprivileged (16 bit) This function executes a Unprivileged STRT instruction for 16 bit values. @@ -829,12 +820,13 @@ __attribute__( ( always_inline ) ) __STATIC_INLINE void __STRBT(uint8_t value, v \param [in] value Value to store \param [in] ptr Pointer to location */ -__attribute__( ( always_inline ) ) __STATIC_INLINE void __STRHT(uint16_t value, volatile uint16_t *addr) +__attribute__((always_inline)) __STATIC_INLINE void __STRHT(uint16_t value, volatile uint16_t *addr) { - __ASM volatile ("strht %1, %0" : "=Q" (*addr) : "r" ((uint32_t)value) ); + __ASM volatile("strht %1, %0" + : "=Q"(*addr) + : "r"((uint32_t)value)); } - /** \brief STRT Unprivileged (32 bit) This function executes a Unprivileged STRT instruction for 32 bit values. @@ -842,25 +834,24 @@ __attribute__( ( always_inline ) ) __STATIC_INLINE void __STRHT(uint16_t value, \param [in] value Value to store \param [in] ptr Pointer to location */ -__attribute__( ( always_inline ) ) __STATIC_INLINE void __STRT(uint32_t value, volatile uint32_t *addr) +__attribute__((always_inline)) __STATIC_INLINE void __STRT(uint32_t value, volatile uint32_t *addr) { - __ASM volatile ("strt %1, %0" : "=Q" (*addr) : "r" (value) ); + __ASM volatile("strt %1, %0" + : "=Q"(*addr) + : "r"(value)); } #endif /* (__CORTEX_M >= 0x03) || (__CORTEX_SC >= 300) */ - -#elif defined ( __ICCARM__ ) /*------------------ ICC Compiler -------------------*/ +#elif defined(__ICCARM__) /*------------------ ICC Compiler -------------------*/ /* IAR iccarm specific functions */ #include <cmsis_iar.h> - -#elif defined ( __TMS470__ ) /*---------------- TI CCS Compiler ------------------*/ +#elif defined(__TMS470__) /*---------------- TI CCS Compiler ------------------*/ /* TI CCS specific functions */ #include <cmsis_ccs.h> - -#elif defined ( __TASKING__ ) /*------------------ TASKING Compiler --------------*/ +#elif defined(__TASKING__) /*------------------ TASKING Compiler --------------*/ /* TASKING carm specific functions */ /* * The CMSIS functions have been implemented as intrinsics in the compiler. @@ -868,8 +859,7 @@ __attribute__( ( always_inline ) ) __STATIC_INLINE void __STRT(uint32_t value, v * Including the CMSIS ones. */ - -#elif defined ( __CSMC__ ) /*------------------ COSMIC Compiler -------------------*/ +#elif defined(__CSMC__) /*------------------ COSMIC Compiler -------------------*/ /* Cosmic specific functions */ #include <cmsis_csm.h> diff --git a/bsp/swm320-lq100/Libraries/CMSIS/CoreSupport/core_cmSimd.h b/bsp/swm320-lq100/Libraries/CMSIS/CoreSupport/core_cmSimd.h index ee58eee56d..1997067d11 100644 --- a/bsp/swm320-lq100/Libraries/CMSIS/CoreSupport/core_cmSimd.h +++ b/bsp/swm320-lq100/Libraries/CMSIS/CoreSupport/core_cmSimd.h @@ -1,4 +1,4 @@ -/**************************************************************************//** +/**************************************************************************/ /** * @file core_cmSimd.h * @brief CMSIS Cortex-M SIMD Header File * @version V4.00 @@ -34,661 +34,794 @@ POSSIBILITY OF SUCH DAMAGE. ---------------------------------------------------------------------------*/ - -#if defined ( __ICCARM__ ) - #pragma system_include /* treat file as system include file for MISRA check */ +#if defined(__ICCARM__) +#pragma system_include /* treat file as system include file for MISRA check */ #endif #ifndef __CORE_CMSIMD_H #define __CORE_CMSIMD_H #ifdef __cplusplus - extern "C" { +extern "C" +{ #endif - -/******************************************************************************* + /******************************************************************************* * Hardware Abstraction Layer ******************************************************************************/ - -/* ################### Compiler specific Intrinsics ########################### */ -/** \defgroup CMSIS_SIMD_intrinsics CMSIS SIMD Intrinsics + /* ################### Compiler specific Intrinsics ########################### */ + /** \defgroup CMSIS_SIMD_intrinsics CMSIS SIMD Intrinsics Access to dedicated SIMD instructions @{ */ -#if defined ( __CC_ARM ) /*------------------RealView Compiler -----------------*/ +#if defined(__CC_ARM) /*------------------RealView Compiler -----------------*/ /* ARM armcc specific functions */ -#define __SADD8 __sadd8 -#define __QADD8 __qadd8 -#define __SHADD8 __shadd8 -#define __UADD8 __uadd8 -#define __UQADD8 __uqadd8 -#define __UHADD8 __uhadd8 -#define __SSUB8 __ssub8 -#define __QSUB8 __qsub8 -#define __SHSUB8 __shsub8 -#define __USUB8 __usub8 -#define __UQSUB8 __uqsub8 -#define __UHSUB8 __uhsub8 -#define __SADD16 __sadd16 -#define __QADD16 __qadd16 -#define __SHADD16 __shadd16 -#define __UADD16 __uadd16 -#define __UQADD16 __uqadd16 -#define __UHADD16 __uhadd16 -#define __SSUB16 __ssub16 -#define __QSUB16 __qsub16 -#define __SHSUB16 __shsub16 -#define __USUB16 __usub16 -#define __UQSUB16 __uqsub16 -#define __UHSUB16 __uhsub16 -#define __SASX __sasx -#define __QASX __qasx -#define __SHASX __shasx -#define __UASX __uasx -#define __UQASX __uqasx -#define __UHASX __uhasx -#define __SSAX __ssax -#define __QSAX __qsax -#define __SHSAX __shsax -#define __USAX __usax -#define __UQSAX __uqsax -#define __UHSAX __uhsax -#define __USAD8 __usad8 -#define __USADA8 __usada8 -#define __SSAT16 __ssat16 -#define __USAT16 __usat16 -#define __UXTB16 __uxtb16 -#define __UXTAB16 __uxtab16 -#define __SXTB16 __sxtb16 -#define __SXTAB16 __sxtab16 -#define __SMUAD __smuad -#define __SMUADX __smuadx -#define __SMLAD __smlad -#define __SMLADX __smladx -#define __SMLALD __smlald -#define __SMLALDX __smlaldx -#define __SMUSD __smusd -#define __SMUSDX __smusdx -#define __SMLSD __smlsd -#define __SMLSDX __smlsdx -#define __SMLSLD __smlsld -#define __SMLSLDX __smlsldx -#define __SEL __sel -#define __QADD __qadd -#define __QSUB __qsub - -#define __PKHBT(ARG1,ARG2,ARG3) ( ((((uint32_t)(ARG1)) ) & 0x0000FFFFUL) | \ - ((((uint32_t)(ARG2)) << (ARG3)) & 0xFFFF0000UL) ) +#define __SADD8 __sadd8 +#define __QADD8 __qadd8 +#define __SHADD8 __shadd8 +#define __UADD8 __uadd8 +#define __UQADD8 __uqadd8 +#define __UHADD8 __uhadd8 +#define __SSUB8 __ssub8 +#define __QSUB8 __qsub8 +#define __SHSUB8 __shsub8 +#define __USUB8 __usub8 +#define __UQSUB8 __uqsub8 +#define __UHSUB8 __uhsub8 +#define __SADD16 __sadd16 +#define __QADD16 __qadd16 +#define __SHADD16 __shadd16 +#define __UADD16 __uadd16 +#define __UQADD16 __uqadd16 +#define __UHADD16 __uhadd16 +#define __SSUB16 __ssub16 +#define __QSUB16 __qsub16 +#define __SHSUB16 __shsub16 +#define __USUB16 __usub16 +#define __UQSUB16 __uqsub16 +#define __UHSUB16 __uhsub16 +#define __SASX __sasx +#define __QASX __qasx +#define __SHASX __shasx +#define __UASX __uasx +#define __UQASX __uqasx +#define __UHASX __uhasx +#define __SSAX __ssax +#define __QSAX __qsax +#define __SHSAX __shsax +#define __USAX __usax +#define __UQSAX __uqsax +#define __UHSAX __uhsax +#define __USAD8 __usad8 +#define __USADA8 __usada8 +#define __SSAT16 __ssat16 +#define __USAT16 __usat16 +#define __UXTB16 __uxtb16 +#define __UXTAB16 __uxtab16 +#define __SXTB16 __sxtb16 +#define __SXTAB16 __sxtab16 +#define __SMUAD __smuad +#define __SMUADX __smuadx +#define __SMLAD __smlad +#define __SMLADX __smladx +#define __SMLALD __smlald +#define __SMLALDX __smlaldx +#define __SMUSD __smusd +#define __SMUSDX __smusdx +#define __SMLSD __smlsd +#define __SMLSDX __smlsdx +#define __SMLSLD __smlsld +#define __SMLSLDX __smlsldx +#define __SEL __sel +#define __QADD __qadd +#define __QSUB __qsub -#define __PKHTB(ARG1,ARG2,ARG3) ( ((((uint32_t)(ARG1)) ) & 0xFFFF0000UL) | \ - ((((uint32_t)(ARG2)) >> (ARG3)) & 0x0000FFFFUL) ) +#define __PKHBT(ARG1, ARG2, ARG3) (((((uint32_t)(ARG1))) & 0x0000FFFFUL) | \ + ((((uint32_t)(ARG2)) << (ARG3)) & 0xFFFF0000UL)) -#define __SMMLA(ARG1,ARG2,ARG3) ( (int32_t)((((int64_t)(ARG1) * (ARG2)) + \ - ((int64_t)(ARG3) << 32) ) >> 32)) +#define __PKHTB(ARG1, ARG2, ARG3) (((((uint32_t)(ARG1))) & 0xFFFF0000UL) | \ + ((((uint32_t)(ARG2)) >> (ARG3)) & 0x0000FFFFUL)) +#define __SMMLA(ARG1, ARG2, ARG3) ((int32_t)((((int64_t)(ARG1) * (ARG2)) + \ + ((int64_t)(ARG3) << 32)) >> \ + 32)) -#elif defined ( __GNUC__ ) /*------------------ GNU Compiler ---------------------*/ +#elif defined(__GNUC__) /*------------------ GNU Compiler ---------------------*/ /* GNU gcc specific functions */ -__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SADD8(uint32_t op1, uint32_t op2) +__attribute__((always_inline)) __STATIC_INLINE uint32_t __SADD8(uint32_t op1, uint32_t op2) { - uint32_t result; + uint32_t result; - __ASM volatile ("sadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); - return(result); + __ASM volatile("sadd8 %0, %1, %2" + : "=r"(result) + : "r"(op1), "r"(op2)); + return (result); } -__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __QADD8(uint32_t op1, uint32_t op2) +__attribute__((always_inline)) __STATIC_INLINE uint32_t __QADD8(uint32_t op1, uint32_t op2) { - uint32_t result; + uint32_t result; - __ASM volatile ("qadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); - return(result); + __ASM volatile("qadd8 %0, %1, %2" + : "=r"(result) + : "r"(op1), "r"(op2)); + return (result); } -__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SHADD8(uint32_t op1, uint32_t op2) +__attribute__((always_inline)) __STATIC_INLINE uint32_t __SHADD8(uint32_t op1, uint32_t op2) { - uint32_t result; + uint32_t result; - __ASM volatile ("shadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); - return(result); + __ASM volatile("shadd8 %0, %1, %2" + : "=r"(result) + : "r"(op1), "r"(op2)); + return (result); } -__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __UADD8(uint32_t op1, uint32_t op2) +__attribute__((always_inline)) __STATIC_INLINE uint32_t __UADD8(uint32_t op1, uint32_t op2) { - uint32_t result; + uint32_t result; - __ASM volatile ("uadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); - return(result); + __ASM volatile("uadd8 %0, %1, %2" + : "=r"(result) + : "r"(op1), "r"(op2)); + return (result); } -__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __UQADD8(uint32_t op1, uint32_t op2) +__attribute__((always_inline)) __STATIC_INLINE uint32_t __UQADD8(uint32_t op1, uint32_t op2) { - uint32_t result; + uint32_t result; - __ASM volatile ("uqadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); - return(result); + __ASM volatile("uqadd8 %0, %1, %2" + : "=r"(result) + : "r"(op1), "r"(op2)); + return (result); } -__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __UHADD8(uint32_t op1, uint32_t op2) +__attribute__((always_inline)) __STATIC_INLINE uint32_t __UHADD8(uint32_t op1, uint32_t op2) { - uint32_t result; + uint32_t result; - __ASM volatile ("uhadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); - return(result); + __ASM volatile("uhadd8 %0, %1, %2" + : "=r"(result) + : "r"(op1), "r"(op2)); + return (result); } - -__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SSUB8(uint32_t op1, uint32_t op2) +__attribute__((always_inline)) __STATIC_INLINE uint32_t __SSUB8(uint32_t op1, uint32_t op2) { - uint32_t result; + uint32_t result; - __ASM volatile ("ssub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); - return(result); + __ASM volatile("ssub8 %0, %1, %2" + : "=r"(result) + : "r"(op1), "r"(op2)); + return (result); } -__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __QSUB8(uint32_t op1, uint32_t op2) +__attribute__((always_inline)) __STATIC_INLINE uint32_t __QSUB8(uint32_t op1, uint32_t op2) { - uint32_t result; + uint32_t result; - __ASM volatile ("qsub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); - return(result); + __ASM volatile("qsub8 %0, %1, %2" + : "=r"(result) + : "r"(op1), "r"(op2)); + return (result); } -__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SHSUB8(uint32_t op1, uint32_t op2) +__attribute__((always_inline)) __STATIC_INLINE uint32_t __SHSUB8(uint32_t op1, uint32_t op2) { - uint32_t result; + uint32_t result; - __ASM volatile ("shsub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); - return(result); + __ASM volatile("shsub8 %0, %1, %2" + : "=r"(result) + : "r"(op1), "r"(op2)); + return (result); } -__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __USUB8(uint32_t op1, uint32_t op2) +__attribute__((always_inline)) __STATIC_INLINE uint32_t __USUB8(uint32_t op1, uint32_t op2) { - uint32_t result; + uint32_t result; - __ASM volatile ("usub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); - return(result); + __ASM volatile("usub8 %0, %1, %2" + : "=r"(result) + : "r"(op1), "r"(op2)); + return (result); } -__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __UQSUB8(uint32_t op1, uint32_t op2) +__attribute__((always_inline)) __STATIC_INLINE uint32_t __UQSUB8(uint32_t op1, uint32_t op2) { - uint32_t result; + uint32_t result; - __ASM volatile ("uqsub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); - return(result); + __ASM volatile("uqsub8 %0, %1, %2" + : "=r"(result) + : "r"(op1), "r"(op2)); + return (result); } -__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __UHSUB8(uint32_t op1, uint32_t op2) +__attribute__((always_inline)) __STATIC_INLINE uint32_t __UHSUB8(uint32_t op1, uint32_t op2) { - uint32_t result; + uint32_t result; - __ASM volatile ("uhsub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); - return(result); + __ASM volatile("uhsub8 %0, %1, %2" + : "=r"(result) + : "r"(op1), "r"(op2)); + return (result); } - -__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SADD16(uint32_t op1, uint32_t op2) +__attribute__((always_inline)) __STATIC_INLINE uint32_t __SADD16(uint32_t op1, uint32_t op2) { - uint32_t result; + uint32_t result; - __ASM volatile ("sadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); - return(result); + __ASM volatile("sadd16 %0, %1, %2" + : "=r"(result) + : "r"(op1), "r"(op2)); + return (result); } -__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __QADD16(uint32_t op1, uint32_t op2) +__attribute__((always_inline)) __STATIC_INLINE uint32_t __QADD16(uint32_t op1, uint32_t op2) { - uint32_t result; + uint32_t result; - __ASM volatile ("qadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); - return(result); + __ASM volatile("qadd16 %0, %1, %2" + : "=r"(result) + : "r"(op1), "r"(op2)); + return (result); } -__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SHADD16(uint32_t op1, uint32_t op2) +__attribute__((always_inline)) __STATIC_INLINE uint32_t __SHADD16(uint32_t op1, uint32_t op2) { - uint32_t result; + uint32_t result; - __ASM volatile ("shadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); - return(result); + __ASM volatile("shadd16 %0, %1, %2" + : "=r"(result) + : "r"(op1), "r"(op2)); + return (result); } -__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __UADD16(uint32_t op1, uint32_t op2) +__attribute__((always_inline)) __STATIC_INLINE uint32_t __UADD16(uint32_t op1, uint32_t op2) { - uint32_t result; + uint32_t result; - __ASM volatile ("uadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); - return(result); + __ASM volatile("uadd16 %0, %1, %2" + : "=r"(result) + : "r"(op1), "r"(op2)); + return (result); } -__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __UQADD16(uint32_t op1, uint32_t op2) +__attribute__((always_inline)) __STATIC_INLINE uint32_t __UQADD16(uint32_t op1, uint32_t op2) { - uint32_t result; + uint32_t result; - __ASM volatile ("uqadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); - return(result); + __ASM volatile("uqadd16 %0, %1, %2" + : "=r"(result) + : "r"(op1), "r"(op2)); + return (result); } -__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __UHADD16(uint32_t op1, uint32_t op2) +__attribute__((always_inline)) __STATIC_INLINE uint32_t __UHADD16(uint32_t op1, uint32_t op2) { - uint32_t result; + uint32_t result; - __ASM volatile ("uhadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); - return(result); + __ASM volatile("uhadd16 %0, %1, %2" + : "=r"(result) + : "r"(op1), "r"(op2)); + return (result); } -__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SSUB16(uint32_t op1, uint32_t op2) +__attribute__((always_inline)) __STATIC_INLINE uint32_t __SSUB16(uint32_t op1, uint32_t op2) { - uint32_t result; + uint32_t result; - __ASM volatile ("ssub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); - return(result); + __ASM volatile("ssub16 %0, %1, %2" + : "=r"(result) + : "r"(op1), "r"(op2)); + return (result); } -__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __QSUB16(uint32_t op1, uint32_t op2) +__attribute__((always_inline)) __STATIC_INLINE uint32_t __QSUB16(uint32_t op1, uint32_t op2) { - uint32_t result; + uint32_t result; - __ASM volatile ("qsub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); - return(result); + __ASM volatile("qsub16 %0, %1, %2" + : "=r"(result) + : "r"(op1), "r"(op2)); + return (result); } -__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SHSUB16(uint32_t op1, uint32_t op2) +__attribute__((always_inline)) __STATIC_INLINE uint32_t __SHSUB16(uint32_t op1, uint32_t op2) { - uint32_t result; + uint32_t result; - __ASM volatile ("shsub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); - return(result); + __ASM volatile("shsub16 %0, %1, %2" + : "=r"(result) + : "r"(op1), "r"(op2)); + return (result); } -__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __USUB16(uint32_t op1, uint32_t op2) +__attribute__((always_inline)) __STATIC_INLINE uint32_t __USUB16(uint32_t op1, uint32_t op2) { - uint32_t result; + uint32_t result; - __ASM volatile ("usub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); - return(result); + __ASM volatile("usub16 %0, %1, %2" + : "=r"(result) + : "r"(op1), "r"(op2)); + return (result); } -__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __UQSUB16(uint32_t op1, uint32_t op2) +__attribute__((always_inline)) __STATIC_INLINE uint32_t __UQSUB16(uint32_t op1, uint32_t op2) { - uint32_t result; + uint32_t result; - __ASM volatile ("uqsub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); - return(result); + __ASM volatile("uqsub16 %0, %1, %2" + : "=r"(result) + : "r"(op1), "r"(op2)); + return (result); } -__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __UHSUB16(uint32_t op1, uint32_t op2) +__attribute__((always_inline)) __STATIC_INLINE uint32_t __UHSUB16(uint32_t op1, uint32_t op2) { - uint32_t result; + uint32_t result; - __ASM volatile ("uhsub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); - return(result); + __ASM volatile("uhsub16 %0, %1, %2" + : "=r"(result) + : "r"(op1), "r"(op2)); + return (result); } -__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SASX(uint32_t op1, uint32_t op2) +__attribute__((always_inline)) __STATIC_INLINE uint32_t __SASX(uint32_t op1, uint32_t op2) { - uint32_t result; + uint32_t result; - __ASM volatile ("sasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); - return(result); + __ASM volatile("sasx %0, %1, %2" + : "=r"(result) + : "r"(op1), "r"(op2)); + return (result); } -__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __QASX(uint32_t op1, uint32_t op2) +__attribute__((always_inline)) __STATIC_INLINE uint32_t __QASX(uint32_t op1, uint32_t op2) { - uint32_t result; + uint32_t result; - __ASM volatile ("qasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); - return(result); + __ASM volatile("qasx %0, %1, %2" + : "=r"(result) + : "r"(op1), "r"(op2)); + return (result); } -__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SHASX(uint32_t op1, uint32_t op2) +__attribute__((always_inline)) __STATIC_INLINE uint32_t __SHASX(uint32_t op1, uint32_t op2) { - uint32_t result; + uint32_t result; - __ASM volatile ("shasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); - return(result); + __ASM volatile("shasx %0, %1, %2" + : "=r"(result) + : "r"(op1), "r"(op2)); + return (result); } -__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __UASX(uint32_t op1, uint32_t op2) +__attribute__((always_inline)) __STATIC_INLINE uint32_t __UASX(uint32_t op1, uint32_t op2) { - uint32_t result; + uint32_t result; - __ASM volatile ("uasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); - return(result); + __ASM volatile("uasx %0, %1, %2" + : "=r"(result) + : "r"(op1), "r"(op2)); + return (result); } -__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __UQASX(uint32_t op1, uint32_t op2) +__attribute__((always_inline)) __STATIC_INLINE uint32_t __UQASX(uint32_t op1, uint32_t op2) { - uint32_t result; + uint32_t result; - __ASM volatile ("uqasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); - return(result); + __ASM volatile("uqasx %0, %1, %2" + : "=r"(result) + : "r"(op1), "r"(op2)); + return (result); } -__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __UHASX(uint32_t op1, uint32_t op2) +__attribute__((always_inline)) __STATIC_INLINE uint32_t __UHASX(uint32_t op1, uint32_t op2) { - uint32_t result; + uint32_t result; - __ASM volatile ("uhasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); - return(result); + __ASM volatile("uhasx %0, %1, %2" + : "=r"(result) + : "r"(op1), "r"(op2)); + return (result); } -__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SSAX(uint32_t op1, uint32_t op2) +__attribute__((always_inline)) __STATIC_INLINE uint32_t __SSAX(uint32_t op1, uint32_t op2) { - uint32_t result; + uint32_t result; - __ASM volatile ("ssax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); - return(result); + __ASM volatile("ssax %0, %1, %2" + : "=r"(result) + : "r"(op1), "r"(op2)); + return (result); } -__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __QSAX(uint32_t op1, uint32_t op2) +__attribute__((always_inline)) __STATIC_INLINE uint32_t __QSAX(uint32_t op1, uint32_t op2) { - uint32_t result; + uint32_t result; - __ASM volatile ("qsax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); - return(result); + __ASM volatile("qsax %0, %1, %2" + : "=r"(result) + : "r"(op1), "r"(op2)); + return (result); } -__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SHSAX(uint32_t op1, uint32_t op2) +__attribute__((always_inline)) __STATIC_INLINE uint32_t __SHSAX(uint32_t op1, uint32_t op2) { - uint32_t result; + uint32_t result; - __ASM volatile ("shsax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); - return(result); + __ASM volatile("shsax %0, %1, %2" + : "=r"(result) + : "r"(op1), "r"(op2)); + return (result); } -__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __USAX(uint32_t op1, uint32_t op2) +__attribute__((always_inline)) __STATIC_INLINE uint32_t __USAX(uint32_t op1, uint32_t op2) { - uint32_t result; + uint32_t result; - __ASM volatile ("usax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); - return(result); + __ASM volatile("usax %0, %1, %2" + : "=r"(result) + : "r"(op1), "r"(op2)); + return (result); } -__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __UQSAX(uint32_t op1, uint32_t op2) +__attribute__((always_inline)) __STATIC_INLINE uint32_t __UQSAX(uint32_t op1, uint32_t op2) { - uint32_t result; + uint32_t result; - __ASM volatile ("uqsax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); - return(result); + __ASM volatile("uqsax %0, %1, %2" + : "=r"(result) + : "r"(op1), "r"(op2)); + return (result); } -__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __UHSAX(uint32_t op1, uint32_t op2) +__attribute__((always_inline)) __STATIC_INLINE uint32_t __UHSAX(uint32_t op1, uint32_t op2) { - uint32_t result; + uint32_t result; - __ASM volatile ("uhsax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); - return(result); + __ASM volatile("uhsax %0, %1, %2" + : "=r"(result) + : "r"(op1), "r"(op2)); + return (result); } -__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __USAD8(uint32_t op1, uint32_t op2) +__attribute__((always_inline)) __STATIC_INLINE uint32_t __USAD8(uint32_t op1, uint32_t op2) { - uint32_t result; + uint32_t result; - __ASM volatile ("usad8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); - return(result); + __ASM volatile("usad8 %0, %1, %2" + : "=r"(result) + : "r"(op1), "r"(op2)); + return (result); } -__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __USADA8(uint32_t op1, uint32_t op2, uint32_t op3) +__attribute__((always_inline)) __STATIC_INLINE uint32_t __USADA8(uint32_t op1, uint32_t op2, uint32_t op3) { - uint32_t result; + uint32_t result; - __ASM volatile ("usada8 %0, %1, %2, %3" : "=r" (result) : "r" (op1), "r" (op2), "r" (op3) ); - return(result); + __ASM volatile("usada8 %0, %1, %2, %3" + : "=r"(result) + : "r"(op1), "r"(op2), "r"(op3)); + return (result); } -#define __SSAT16(ARG1,ARG2) \ -({ \ - uint32_t __RES, __ARG1 = (ARG1); \ - __ASM ("ssat16 %0, %1, %2" : "=r" (__RES) : "I" (ARG2), "r" (__ARG1) ); \ - __RES; \ - }) +#define __SSAT16(ARG1, ARG2) \ + ( \ + { \ + uint32_t __RES, __ARG1 = (ARG1); \ + __ASM("ssat16 %0, %1, %2" \ + : "=r"(__RES) \ + : "I"(ARG2), "r"(__ARG1)); \ + __RES; \ + }) -#define __USAT16(ARG1,ARG2) \ -({ \ - uint32_t __RES, __ARG1 = (ARG1); \ - __ASM ("usat16 %0, %1, %2" : "=r" (__RES) : "I" (ARG2), "r" (__ARG1) ); \ - __RES; \ - }) +#define __USAT16(ARG1, ARG2) \ + ( \ + { \ + uint32_t __RES, __ARG1 = (ARG1); \ + __ASM("usat16 %0, %1, %2" \ + : "=r"(__RES) \ + : "I"(ARG2), "r"(__ARG1)); \ + __RES; \ + }) -__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __UXTB16(uint32_t op1) +__attribute__((always_inline)) __STATIC_INLINE uint32_t __UXTB16(uint32_t op1) { - uint32_t result; + uint32_t result; - __ASM volatile ("uxtb16 %0, %1" : "=r" (result) : "r" (op1)); - return(result); + __ASM volatile("uxtb16 %0, %1" + : "=r"(result) + : "r"(op1)); + return (result); } -__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __UXTAB16(uint32_t op1, uint32_t op2) +__attribute__((always_inline)) __STATIC_INLINE uint32_t __UXTAB16(uint32_t op1, uint32_t op2) { - uint32_t result; + uint32_t result; - __ASM volatile ("uxtab16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); - return(result); + __ASM volatile("uxtab16 %0, %1, %2" + : "=r"(result) + : "r"(op1), "r"(op2)); + return (result); } -__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SXTB16(uint32_t op1) +__attribute__((always_inline)) __STATIC_INLINE uint32_t __SXTB16(uint32_t op1) { - uint32_t result; + uint32_t result; - __ASM volatile ("sxtb16 %0, %1" : "=r" (result) : "r" (op1)); - return(result); + __ASM volatile("sxtb16 %0, %1" + : "=r"(result) + : "r"(op1)); + return (result); } -__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SXTAB16(uint32_t op1, uint32_t op2) +__attribute__((always_inline)) __STATIC_INLINE uint32_t __SXTAB16(uint32_t op1, uint32_t op2) { - uint32_t result; + uint32_t result; - __ASM volatile ("sxtab16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); - return(result); + __ASM volatile("sxtab16 %0, %1, %2" + : "=r"(result) + : "r"(op1), "r"(op2)); + return (result); } -__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SMUAD (uint32_t op1, uint32_t op2) +__attribute__((always_inline)) __STATIC_INLINE uint32_t __SMUAD(uint32_t op1, uint32_t op2) { - uint32_t result; + uint32_t result; - __ASM volatile ("smuad %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); - return(result); + __ASM volatile("smuad %0, %1, %2" + : "=r"(result) + : "r"(op1), "r"(op2)); + return (result); } -__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SMUADX (uint32_t op1, uint32_t op2) +__attribute__((always_inline)) __STATIC_INLINE uint32_t __SMUADX(uint32_t op1, uint32_t op2) { - uint32_t result; + uint32_t result; - __ASM volatile ("smuadx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); - return(result); + __ASM volatile("smuadx %0, %1, %2" + : "=r"(result) + : "r"(op1), "r"(op2)); + return (result); } -__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SMLAD (uint32_t op1, uint32_t op2, uint32_t op3) +__attribute__((always_inline)) __STATIC_INLINE uint32_t __SMLAD(uint32_t op1, uint32_t op2, uint32_t op3) { - uint32_t result; + uint32_t result; - __ASM volatile ("smlad %0, %1, %2, %3" : "=r" (result) : "r" (op1), "r" (op2), "r" (op3) ); - return(result); + __ASM volatile("smlad %0, %1, %2, %3" + : "=r"(result) + : "r"(op1), "r"(op2), "r"(op3)); + return (result); } -__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SMLADX (uint32_t op1, uint32_t op2, uint32_t op3) +__attribute__((always_inline)) __STATIC_INLINE uint32_t __SMLADX(uint32_t op1, uint32_t op2, uint32_t op3) { - uint32_t result; + uint32_t result; - __ASM volatile ("smladx %0, %1, %2, %3" : "=r" (result) : "r" (op1), "r" (op2), "r" (op3) ); - return(result); + __ASM volatile("smladx %0, %1, %2, %3" + : "=r"(result) + : "r"(op1), "r"(op2), "r"(op3)); + return (result); } -__attribute__( ( always_inline ) ) __STATIC_INLINE uint64_t __SMLALD (uint32_t op1, uint32_t op2, uint64_t acc) +__attribute__((always_inline)) __STATIC_INLINE uint64_t __SMLALD(uint32_t op1, uint32_t op2, uint64_t acc) { - union llreg_u{ - uint32_t w32[2]; - uint64_t w64; - } llr; - llr.w64 = acc; + union llreg_u + { + uint32_t w32[2]; + uint64_t w64; + } llr; + llr.w64 = acc; -#ifndef __ARMEB__ // Little endian - __ASM volatile ("smlald %0, %1, %2, %3" : "=r" (llr.w32[0]), "=r" (llr.w32[1]): "r" (op1), "r" (op2) , "0" (llr.w32[0]), "1" (llr.w32[1]) ); -#else // Big endian - __ASM volatile ("smlald %0, %1, %2, %3" : "=r" (llr.w32[1]), "=r" (llr.w32[0]): "r" (op1), "r" (op2) , "0" (llr.w32[1]), "1" (llr.w32[0]) ); +#ifndef __ARMEB__ // Little endian + __ASM volatile("smlald %0, %1, %2, %3" + : "=r"(llr.w32[0]), "=r"(llr.w32[1]) + : "r"(op1), "r"(op2), "0"(llr.w32[0]), "1"(llr.w32[1])); +#else // Big endian + __ASM volatile("smlald %0, %1, %2, %3" + : "=r"(llr.w32[1]), "=r"(llr.w32[0]) + : "r"(op1), "r"(op2), "0"(llr.w32[1]), "1"(llr.w32[0])); #endif - return(llr.w64); + return (llr.w64); } -__attribute__( ( always_inline ) ) __STATIC_INLINE uint64_t __SMLALDX (uint32_t op1, uint32_t op2, uint64_t acc) +__attribute__((always_inline)) __STATIC_INLINE uint64_t __SMLALDX(uint32_t op1, uint32_t op2, uint64_t acc) { - union llreg_u{ - uint32_t w32[2]; - uint64_t w64; - } llr; - llr.w64 = acc; + union llreg_u + { + uint32_t w32[2]; + uint64_t w64; + } llr; + llr.w64 = acc; -#ifndef __ARMEB__ // Little endian - __ASM volatile ("smlaldx %0, %1, %2, %3" : "=r" (llr.w32[0]), "=r" (llr.w32[1]): "r" (op1), "r" (op2) , "0" (llr.w32[0]), "1" (llr.w32[1]) ); -#else // Big endian - __ASM volatile ("smlaldx %0, %1, %2, %3" : "=r" (llr.w32[1]), "=r" (llr.w32[0]): "r" (op1), "r" (op2) , "0" (llr.w32[1]), "1" (llr.w32[0]) ); +#ifndef __ARMEB__ // Little endian + __ASM volatile("smlaldx %0, %1, %2, %3" + : "=r"(llr.w32[0]), "=r"(llr.w32[1]) + : "r"(op1), "r"(op2), "0"(llr.w32[0]), "1"(llr.w32[1])); +#else // Big endian + __ASM volatile("smlaldx %0, %1, %2, %3" + : "=r"(llr.w32[1]), "=r"(llr.w32[0]) + : "r"(op1), "r"(op2), "0"(llr.w32[1]), "1"(llr.w32[0])); #endif - return(llr.w64); + return (llr.w64); } -__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SMUSD (uint32_t op1, uint32_t op2) +__attribute__((always_inline)) __STATIC_INLINE uint32_t __SMUSD(uint32_t op1, uint32_t op2) { - uint32_t result; + uint32_t result; - __ASM volatile ("smusd %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); - return(result); + __ASM volatile("smusd %0, %1, %2" + : "=r"(result) + : "r"(op1), "r"(op2)); + return (result); } -__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SMUSDX (uint32_t op1, uint32_t op2) +__attribute__((always_inline)) __STATIC_INLINE uint32_t __SMUSDX(uint32_t op1, uint32_t op2) { - uint32_t result; + uint32_t result; - __ASM volatile ("smusdx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); - return(result); + __ASM volatile("smusdx %0, %1, %2" + : "=r"(result) + : "r"(op1), "r"(op2)); + return (result); } -__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SMLSD (uint32_t op1, uint32_t op2, uint32_t op3) +__attribute__((always_inline)) __STATIC_INLINE uint32_t __SMLSD(uint32_t op1, uint32_t op2, uint32_t op3) { - uint32_t result; + uint32_t result; - __ASM volatile ("smlsd %0, %1, %2, %3" : "=r" (result) : "r" (op1), "r" (op2), "r" (op3) ); - return(result); + __ASM volatile("smlsd %0, %1, %2, %3" + : "=r"(result) + : "r"(op1), "r"(op2), "r"(op3)); + return (result); } -__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SMLSDX (uint32_t op1, uint32_t op2, uint32_t op3) +__attribute__((always_inline)) __STATIC_INLINE uint32_t __SMLSDX(uint32_t op1, uint32_t op2, uint32_t op3) { - uint32_t result; + uint32_t result; - __ASM volatile ("smlsdx %0, %1, %2, %3" : "=r" (result) : "r" (op1), "r" (op2), "r" (op3) ); - return(result); + __ASM volatile("smlsdx %0, %1, %2, %3" + : "=r"(result) + : "r"(op1), "r"(op2), "r"(op3)); + return (result); } -__attribute__( ( always_inline ) ) __STATIC_INLINE uint64_t __SMLSLD (uint32_t op1, uint32_t op2, uint64_t acc) +__attribute__((always_inline)) __STATIC_INLINE uint64_t __SMLSLD(uint32_t op1, uint32_t op2, uint64_t acc) { - union llreg_u{ - uint32_t w32[2]; - uint64_t w64; - } llr; - llr.w64 = acc; + union llreg_u + { + uint32_t w32[2]; + uint64_t w64; + } llr; + llr.w64 = acc; -#ifndef __ARMEB__ // Little endian - __ASM volatile ("smlsld %0, %1, %2, %3" : "=r" (llr.w32[0]), "=r" (llr.w32[1]): "r" (op1), "r" (op2) , "0" (llr.w32[0]), "1" (llr.w32[1]) ); -#else // Big endian - __ASM volatile ("smlsld %0, %1, %2, %3" : "=r" (llr.w32[1]), "=r" (llr.w32[0]): "r" (op1), "r" (op2) , "0" (llr.w32[1]), "1" (llr.w32[0]) ); +#ifndef __ARMEB__ // Little endian + __ASM volatile("smlsld %0, %1, %2, %3" + : "=r"(llr.w32[0]), "=r"(llr.w32[1]) + : "r"(op1), "r"(op2), "0"(llr.w32[0]), "1"(llr.w32[1])); +#else // Big endian + __ASM volatile("smlsld %0, %1, %2, %3" + : "=r"(llr.w32[1]), "=r"(llr.w32[0]) + : "r"(op1), "r"(op2), "0"(llr.w32[1]), "1"(llr.w32[0])); #endif - return(llr.w64); + return (llr.w64); } -__attribute__( ( always_inline ) ) __STATIC_INLINE uint64_t __SMLSLDX (uint32_t op1, uint32_t op2, uint64_t acc) +__attribute__((always_inline)) __STATIC_INLINE uint64_t __SMLSLDX(uint32_t op1, uint32_t op2, uint64_t acc) { - union llreg_u{ - uint32_t w32[2]; - uint64_t w64; - } llr; - llr.w64 = acc; + union llreg_u + { + uint32_t w32[2]; + uint64_t w64; + } llr; + llr.w64 = acc; -#ifndef __ARMEB__ // Little endian - __ASM volatile ("smlsldx %0, %1, %2, %3" : "=r" (llr.w32[0]), "=r" (llr.w32[1]): "r" (op1), "r" (op2) , "0" (llr.w32[0]), "1" (llr.w32[1]) ); -#else // Big endian - __ASM volatile ("smlsldx %0, %1, %2, %3" : "=r" (llr.w32[1]), "=r" (llr.w32[0]): "r" (op1), "r" (op2) , "0" (llr.w32[1]), "1" (llr.w32[0]) ); +#ifndef __ARMEB__ // Little endian + __ASM volatile("smlsldx %0, %1, %2, %3" + : "=r"(llr.w32[0]), "=r"(llr.w32[1]) + : "r"(op1), "r"(op2), "0"(llr.w32[0]), "1"(llr.w32[1])); +#else // Big endian + __ASM volatile("smlsldx %0, %1, %2, %3" + : "=r"(llr.w32[1]), "=r"(llr.w32[0]) + : "r"(op1), "r"(op2), "0"(llr.w32[1]), "1"(llr.w32[0])); #endif - return(llr.w64); + return (llr.w64); } -__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SEL (uint32_t op1, uint32_t op2) +__attribute__((always_inline)) __STATIC_INLINE uint32_t __SEL(uint32_t op1, uint32_t op2) { - uint32_t result; + uint32_t result; - __ASM volatile ("sel %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); - return(result); + __ASM volatile("sel %0, %1, %2" + : "=r"(result) + : "r"(op1), "r"(op2)); + return (result); } -__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __QADD(uint32_t op1, uint32_t op2) +__attribute__((always_inline)) __STATIC_INLINE uint32_t __QADD(uint32_t op1, uint32_t op2) { - uint32_t result; + uint32_t result; - __ASM volatile ("qadd %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); - return(result); + __ASM volatile("qadd %0, %1, %2" + : "=r"(result) + : "r"(op1), "r"(op2)); + return (result); } -__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __QSUB(uint32_t op1, uint32_t op2) +__attribute__((always_inline)) __STATIC_INLINE uint32_t __QSUB(uint32_t op1, uint32_t op2) { - uint32_t result; + uint32_t result; - __ASM volatile ("qsub %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); - return(result); + __ASM volatile("qsub %0, %1, %2" + : "=r"(result) + : "r"(op1), "r"(op2)); + return (result); } -#define __PKHBT(ARG1,ARG2,ARG3) \ -({ \ - uint32_t __RES, __ARG1 = (ARG1), __ARG2 = (ARG2); \ - __ASM ("pkhbt %0, %1, %2, lsl %3" : "=r" (__RES) : "r" (__ARG1), "r" (__ARG2), "I" (ARG3) ); \ - __RES; \ - }) +#define __PKHBT(ARG1, ARG2, ARG3) \ + ( \ + { \ + uint32_t __RES, __ARG1 = (ARG1), __ARG2 = (ARG2); \ + __ASM("pkhbt %0, %1, %2, lsl %3" \ + : "=r"(__RES) \ + : "r"(__ARG1), "r"(__ARG2), "I"(ARG3)); \ + __RES; \ + }) -#define __PKHTB(ARG1,ARG2,ARG3) \ -({ \ - uint32_t __RES, __ARG1 = (ARG1), __ARG2 = (ARG2); \ - if (ARG3 == 0) \ - __ASM ("pkhtb %0, %1, %2" : "=r" (__RES) : "r" (__ARG1), "r" (__ARG2) ); \ - else \ - __ASM ("pkhtb %0, %1, %2, asr %3" : "=r" (__RES) : "r" (__ARG1), "r" (__ARG2), "I" (ARG3) ); \ - __RES; \ - }) +#define __PKHTB(ARG1, ARG2, ARG3) \ + ( \ + { \ + uint32_t __RES, __ARG1 = (ARG1), __ARG2 = (ARG2); \ + if (ARG3 == 0) \ + __ASM("pkhtb %0, %1, %2" \ + : "=r"(__RES) \ + : "r"(__ARG1), "r"(__ARG2)); \ + else \ + __ASM("pkhtb %0, %1, %2, asr %3" \ + : "=r"(__RES) \ + : "r"(__ARG1), "r"(__ARG2), "I"(ARG3)); \ + __RES; \ + }) -__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SMMLA (int32_t op1, int32_t op2, int32_t op3) +__attribute__((always_inline)) __STATIC_INLINE uint32_t __SMMLA(int32_t op1, int32_t op2, int32_t op3) { - int32_t result; + int32_t result; - __ASM volatile ("smmla %0, %1, %2, %3" : "=r" (result): "r" (op1), "r" (op2), "r" (op3) ); - return(result); + __ASM volatile("smmla %0, %1, %2, %3" + : "=r"(result) + : "r"(op1), "r"(op2), "r"(op3)); + return (result); } - -#elif defined ( __ICCARM__ ) /*------------------ ICC Compiler -------------------*/ +#elif defined(__ICCARM__) /*------------------ ICC Compiler -------------------*/ /* IAR iccarm specific functions */ #include <cmsis_iar.h> - -#elif defined ( __TMS470__ ) /*---------------- TI CCS Compiler ------------------*/ +#elif defined(__TMS470__) /*---------------- TI CCS Compiler ------------------*/ /* TI CCS specific functions */ #include <cmsis_ccs.h> - -#elif defined ( __TASKING__ ) /*------------------ TASKING Compiler --------------*/ +#elif defined(__TASKING__) /*------------------ TASKING Compiler --------------*/ /* TASKING carm specific functions */ /* not yet supported */ - -#elif defined ( __CSMC__ ) /*------------------ COSMIC Compiler -------------------*/ +#elif defined(__CSMC__) /*------------------ COSMIC Compiler -------------------*/ /* Cosmic specific functions */ #include <cmsis_csm.h> #endif -/*@} end of group CMSIS_SIMD_intrinsics */ - + /*@} end of group CMSIS_SIMD_intrinsics */ #ifdef __cplusplus } diff --git a/bsp/swm320-lq100/Libraries/CMSIS/DeviceSupport/SWM320.h b/bsp/swm320-lq100/Libraries/CMSIS/DeviceSupport/SWM320.h index 79d9baa156..8e4a3e041c 100644 --- a/bsp/swm320-lq100/Libraries/CMSIS/DeviceSupport/SWM320.h +++ b/bsp/swm320-lq100/Libraries/CMSIS/DeviceSupport/SWM320.h @@ -68,7 +68,7 @@ typedef enum IRQn SPI0_IRQn = 46, ADC0_IRQn = 47, RTC_IRQn = 48, - ANAC_IRQn = 49, + BOD_IRQn = 49, SDIO_IRQn = 50, GPIOA_IRQn = 51, GPIOB_IRQn = 52, @@ -96,16 +96,16 @@ typedef enum IRQn /* Configuration of the Cortex-M0 Processor and Core Peripherals */ #define __CM4_REV 0x0001 /*!< Core revision r0p1 */ #define __MPU_PRESENT 1 /*!< SWM320 provides an MPU */ -#define __NVIC_PRIO_BITS 4 /*!< SWM320 uses 4 Bits for the Priority Levels */ +#define __NVIC_PRIO_BITS 3 /*!< SWM320 uses 3 Bits for the Priority Levels */ #define __Vendor_SysTickConfig 0 /*!< Set to 1 if different SysTick Config is used */ -#define __FPU_PRESENT 1 /*!< FPU present */ +#define __FPU_PRESENT 0 /*!< FPU present */ #if defined(__CC_ARM) - #pragma anon_unions +#pragma anon_unions #endif #include <stdio.h> -#include "core_cm4.h" /* Cortex-M0 processor and core peripherals */ +#include "core_cm4.h" /* Cortex-M0 processor and core peripherals */ #include "system_SWM320.h" /******************************************************************************/ @@ -123,9 +123,9 @@ typedef struct uint32_t RESERVED0[6]; - __IO uint32_t RTCBKP_ISO; //[0] 1 RTC闁跨喐鏋婚幏鐑芥晸閹归顣幏閿嬬爱闁跨喐鏋婚幏鐑芥晸閼哄倿娼婚幏鐑芥晸閺傘倖瀚归悩鑸碘偓锟� 0 RTC闁跨喐鏋婚幏鐑芥晸閹归顣幏閿嬬爱闁跨喐鏋婚幏椋庡幖闁跨喐鏋婚幏鐑芥晸閿燂拷 + __IO uint32_t RTCBKP_ISO; //[0] 1 RTC备份电源域处于隔离状态 0 RTC备份电源域可访问 - __IO uint32_t RTCWKEN; //[0] 1 娴ｅ潡鏁撻弬銈嗗RTC闁跨喐鏋婚幏鐑芥晸缁愭牜娅㈤幏鐑芥晸閺傘倖瀚� + __IO uint32_t RTCWKEN; //[0] 1 使能RTC唤醒功能 uint32_t RESERVED[52 + 64]; @@ -135,25 +135,23 @@ typedef struct uint32_t RESERVED2[1 + 4]; - __IO uint32_t PAWKSR; //Port A Wakeup Status Register闁跨喐鏋婚幏宄板晸1闁跨喐鏋婚幏鐑芥晸閺傘倖瀚� + __IO uint32_t PAWKSR; //Port A Wakeup Status Register，写1清零 __IO uint32_t PBWKSR; __IO uint32_t PCWKSR; - uint32_t RESERVED3[64 - 11]; - - __IO uint32_t REMAP; //0 闁跨喐鏋婚幏鐑芥晸閺傘倖瀚归柨鐔告灮閹风úOM闁跨喐鏋婚幏閿嬪⒔闁跨喐鏋婚幏锟� 1 闁跨喐鏋婚幏鐑芥晸閺傘倖瀚归柨鐔告灮閹风éLASH闁跨喐鏋婚幏閿嬪⒔闁跨喐鏋婚幏锟� + uint32_t RESERVED3[64 - 10]; __IO uint32_t RSTCR; //Reset Control Register __IO uint32_t RSTSR; //Reset Status Register uint32_t RESERVED4[61 + 64]; - __IO uint32_t BKP[3]; //闁跨喐鏋婚幏鐑芥晸閹归攱鍞婚幏鐑芥晸閹瑰嘲鐦庢潏鐐闁跨喐鏋婚幏锟� + __IO uint32_t BKP[3]; //数据备份寄存器 //RTC Power Domain: 0x4001E000 uint32_t RESERVED5[(0x4001E000 - 0x40000508) / 4 - 1]; - __IO uint32_t RTCBKP[8]; //RTC闁跨喐鏋婚幏閿嬬爱闁跨喐鏋婚幏鐑芥晸閺傘倖瀚归柨鐔稿祹閹插瀚归柨鐔稿祹鐎靛嫯鎻幏鐑芥晸閺傘倖瀚� + __IO uint32_t RTCBKP[8]; //RTC电源域数据备份寄存器 __IO uint32_t LRCCR; //Low speed RC Control Register __IO uint32_t LRCTRIM0; //Low speed RC Trim @@ -166,45 +164,37 @@ typedef struct //Analog Control: 0x40031000 uint32_t RESERVED7[(0x40031000 - 0x4001E030) / 4 - 1]; - __IO uint32_t HRCCR; //High speed RC Control Register - __IO uint32_t HRC20M; //[24:0] High speed RC Trim Value for 20MHz - __IO uint32_t HRC40M; //[24:0] High speed RC Trim Value for 40MHz - - uint32_t RESERVED8[3]; + __IO uint32_t HRCCR; //High speed RC Control Register - __IO uint32_t BGTRIM; - - __IO uint32_t TEMPCR; //闁跨喖鎽惔锕佹彧閹风兘鏁撻弬銈嗗闁跨喐鏋婚幏鐑芥晸閺傘倖瀚归柨鐔哄珱鐎靛嫯鎻幏鐑芥晸閺傘倖瀚� + uint32_t RESERVED8[7]; __IO uint32_t XTALCR; __IO uint32_t PLLCR; __IO uint32_t PLLDIV; __IO uint32_t PLLSET; - __IO uint32_t PLLLOCK; //[0] 1 PLL闁跨喐鏋婚幏鐑芥晸閺傘倖瀚归柨鐔告灮閹凤拷 + __IO uint32_t PLLLOCK; //[0] 1 PLL已锁定 __IO uint32_t BODIE; __IO uint32_t BODIF; __IO uint32_t ADC1IN7; - - __IO uint32_t BODCR; } SYS_TypeDef; -#define SYS_CLKSEL_LFCK_Pos 0 //Low Frequency Clock Source 0 LRC 1 PLL +#define SYS_CLKSEL_LFCK_Pos 0 //Low Frequency Clock Source 0 LRC 1 PLL #define SYS_CLKSEL_LFCK_Msk (0x01 << SYS_CLKSEL_LFCK_Pos) -#define SYS_CLKSEL_HFCK_Pos 1 //High Frequency Clock Source 0 HRC 1 XTAL +#define SYS_CLKSEL_HFCK_Pos 1 //High Frequency Clock Source 0 HRC 1 XTAL #define SYS_CLKSEL_HFCK_Msk (0x01 << SYS_CLKSEL_HFCK_Pos) -#define SYS_CLKSEL_SYS_Pos 2 //缁崵绮洪弮鍫曟晸閺傘倖瀚归柅澶愭晸閺傘倖瀚� 0 LFCK 1 HFCK +#define SYS_CLKSEL_SYS_Pos 2 //系统时钟选择 0 LFCK 1 HFCK #define SYS_CLKSEL_SYS_Msk (0x01 << SYS_CLKSEL_SYS_Pos) -#define SYS_CLKDIV_SYS_Pos 0 //缁崵绮洪弮鍫曟晸閹恒儱鍤栭幏鐑筋暥 0 1闁跨喐鏋婚幏鐑筋暥 1 2闁跨喐鏋婚幏鐑筋暥 +#define SYS_CLKDIV_SYS_Pos 0 //系统时钟分频 0 1分频 1 2分频 #define SYS_CLKDIV_SYS_Msk (0x01 << SYS_CLKDIV_SYS_Pos) -#define SYS_CLKDIV_PWM_Pos 1 //PWM 閺冨爼鏁撻幒銉ュ殩閹风兘顣� 0 1闁跨喐鏋婚幏鐑筋暥 1 8闁跨喐鏋婚幏鐑筋暥 +#define SYS_CLKDIV_PWM_Pos 1 //PWM 时钟分频 0 1分频 1 8分频 #define SYS_CLKDIV_PWM_Msk (0x01 << SYS_CLKDIV_PWM_Pos) -#define SYS_CLKDIV_SDRAM_Pos 2 //SDRAM閺冨爼鏁撻幒銉ュ殩閹风兘顣� 0 1闁跨喐鏋婚幏鐑筋暥 1 2闁跨喐鏋婚幏鐑筋暥 2 4闁跨喐鏋婚幏鐑筋暥 +#define SYS_CLKDIV_SDRAM_Pos 2 //SDRAM时钟分频 0 1分频 1 2分频 2 4分频 #define SYS_CLKDIV_SDRAM_Msk (0x03 << SYS_CLKDIV_SDRAM_Pos) -#define SYS_CLKDIV_SDIO_Pos 4 //SDIO閺冨爼鏁撻幒銉ュ殩閹风兘顣� 0 1闁跨喐鏋婚幏鐑筋暥 1 2闁跨喐鏋婚幏鐑筋暥 2 4闁跨喐鏋婚幏鐑筋暥 3 8闁跨喐鏋婚幏鐑筋暥 +#define SYS_CLKDIV_SDIO_Pos 4 //SDIO时钟分频 0 1分频 1 2分频 2 4分频 3 8分频 #define SYS_CLKDIV_SDIO_Msk (0x03 << SYS_CLKDIV_SDIO_Pos) #define SYS_CLKEN_GPIOA_Pos 0 @@ -249,7 +239,7 @@ typedef struct #define SYS_CLKEN_LCD_Msk (0x01 << SYS_CLKEN_LCD_Pos) #define SYS_CLKEN_GPIOP_Pos 21 #define SYS_CLKEN_GPIOP_Msk (0x01 << SYS_CLKEN_GPIOP_Pos) -#define SYS_CLKEN_ANAC_Pos 22 //濡繝鏁撻弬銈嗗闁跨喐鏋婚幏鐑筋暥闁跨喓娈曢鈺傚敾閹风兘鏁撶紒鐐垫閹风兘鏁撻敓锟� +#define SYS_CLKEN_ANAC_Pos 22 //模拟控制单元时钟使能 #define SYS_CLKEN_ANAC_Msk (0x01 << SYS_CLKEN_ANAC_Pos) #define SYS_CLKEN_CRC_Pos 23 #define SYS_CLKEN_CRC_Msk (0x01 << SYS_CLKEN_CRC_Pos) @@ -267,59 +257,59 @@ typedef struct #define SYS_CLKEN_SDIO_Msk (0x01 << SYS_CLKEN_SDIO_Pos) #define SYS_CLKEN_ADC1_Pos 30 #define SYS_CLKEN_ADC1_Msk (0x01 << SYS_CLKEN_ADC1_Pos) -#define SYS_CLKEN_ALIVE_Pos 31 //CHIPALIVE闁跨喐鏋婚幏閿嬬爱闁跨喐鏋婚幏椋庨兇缂佺喐妞傞柨鐔告灮閹疯渹濞囬柨鐔告灮閹凤拷 +#define SYS_CLKEN_ALIVE_Pos 31 //CHIPALIVE电源域系统时钟使能 #define SYS_CLKEN_ALIVE_Msk (0x01 << SYS_CLKEN_ALIVE_Pos) -#define SYS_SLEEP_SLEEP_Pos 0 //闁跨喐鏋婚幏鐑芥晸閺傘倖瀚规担宥夋晸閺傘倖瀚�1闁跨喐鏋婚幏椋庨兇缂佺喖鏁撻弬銈嗗闁跨喐鏋婚幏鐑芥晸閺傘倖瀚筍LEEP濡€崇础 +#define SYS_SLEEP_SLEEP_Pos 0 //将该位置1后，系统将进入SLEEP模式 #define SYS_SLEEP_SLEEP_Msk (0x01 << SYS_SLEEP_SLEEP_Pos) -#define SYS_SLEEP_DEEP_Pos 1 //闁跨喐鏋婚幏鐑芥晸閺傘倖瀚规担宥夋晸閺傘倖瀚�1闁跨喐鏋婚幏椋庨兇缂佺喖鏁撻弬銈嗗闁跨喐鏋婚幏鐑芥晸閺傘倖瀚筍TOP SLEEP濡€崇础 +#define SYS_SLEEP_DEEP_Pos 1 //将该位置1后，系统将进入STOP SLEEP模式 #define SYS_SLEEP_DEEP_Msk (0x01 << SYS_SLEEP_DEEP_Pos) -#define SYS_RSTCR_SYS_Pos 0 //閸愶拷1闁跨喐鏋婚幏鐑芥晸閺傘倖瀚圭化鑽ょ埠闁跨喐鏋婚幏铚傜秴闁跨喐鏋婚幏椋庘€栭柨鐔告灮閹风兘鏁撻惃鍡氼啇閹风兘鏁撻弬銈嗗闁跨喐鏋婚幏锟� +#define SYS_RSTCR_SYS_Pos 0 //写1进行系统复位，硬件自动清零 #define SYS_RSTCR_SYS_Msk (0x01 << SYS_RSTCR_SYS_Pos) -#define SYS_RSTCR_FLASH_Pos 1 //閸愶拷1闁跨喐鏋婚幏绋ASH闁跨喐鏋婚幏鐑芥晸閺傘倖瀚归柨鐔告灮閹风兘鏁撻弬銈嗗闁跨喐鏋婚幏铚傜闁跨喕濞囬棃鈺傚娴ｅ秹鏁撻弬銈嗗绾剟鏁撻弬銈嗗闁跨喓娈曠拋瑙勫闁跨喐鏋婚幏鐑芥晸閺傘倖瀚� +#define SYS_RSTCR_FLASH_Pos 1 //写1对FLASH控制器进行一次复位，硬件自动清零 #define SYS_RSTCR_FLASH_Msk (0x01 << SYS_RSTCR_FLASH_Pos) -#define SYS_RSTCR_PWM_Pos 2 //閸愶拷1闁跨喐鏋婚幏绋癢M闁跨喐鏋婚幏鐑芥晸閺傘倖瀚规稉鈧柨鐔诲▏闂堚晜瀚规担宥夋晸閺傘倖瀚圭涵顒勬晸閺傘倖瀚归柨鐔烘畷鐠佽瀚归柨鐔告灮閹风兘鏁撻弬銈嗗 +#define SYS_RSTCR_PWM_Pos 2 //写1对PWM进行一次复位，硬件自动清零 #define SYS_RSTCR_PWM_Msk (0x01 << SYS_RSTCR_PWM_Pos) -#define SYS_RSTCR_CPU_Pos 3 //閸愶拷1闁跨喐鏋婚幏绋U闁跨喐鏋婚幏鐑芥晸閺傘倖瀚规稉鈧柨鐔诲▏闂堚晜瀚规担宥夋晸閺傘倖瀚圭涵顒勬晸閺傘倖瀚归柨鐔烘畷鐠佽瀚归柨鐔告灮閹风兘鏁撻弬銈嗗 +#define SYS_RSTCR_CPU_Pos 3 //写1对CPU进行一次复位，硬件自动清零 #define SYS_RSTCR_CPU_Msk (0x01 << SYS_RSTCR_CPU_Pos) -#define SYS_RSTCR_DMA_Pos 4 //閸愶拷1闁跨喐鏋婚幏绋A闁跨喐鏋婚幏鐑芥晸閺傘倖瀚规稉鈧柨鐔诲▏闂堚晜瀚规担宥夋晸閺傘倖瀚圭涵顒勬晸閺傘倖瀚归柨鐔烘畷鐠佽瀚归柨鐔告灮閹风兘鏁撻弬銈嗗 +#define SYS_RSTCR_DMA_Pos 4 //写1对DMA进行一次复位，硬件自动清零 #define SYS_RSTCR_DMA_Msk (0x01 << SYS_RSTCR_DMA_Pos) -#define SYS_RSTCR_NORFLASH_Pos 5 //閸愶拷1闁跨喐鏋婚幏绋甇R Flash闁跨喐鏋婚幏鐑芥晸閺傘倖瀚归柨鐔告灮閹风兘鏁撻弬銈嗗闁跨喐鏋婚幏铚傜闁跨喕濞囬棃鈺傚娴ｅ秹鏁撻弬銈嗗绾剟鏁撻弬銈嗗闁跨喓娈曠拋瑙勫闁跨喐鏋婚幏鐑芥晸閺傘倖瀚� +#define SYS_RSTCR_NORFLASH_Pos 5 //写1对NOR Flash控制器进行一次复位，硬件自动清零 #define SYS_RSTCR_NORFLASH_Msk (0x01 << SYS_RSTCR_NORFLASH_Pos) -#define SYS_RSTCR_SRAM_Pos 6 //閸愶拷1闁跨喐鏋婚幏绋碦AM闁跨喐鏋婚幏鐑芥晸閺傘倖瀚归柨鐔告灮閹风兘鏁撻弬銈嗗闁跨喐鏋婚幏铚傜闁跨喕濞囬棃鈺傚娴ｅ秹鏁撻弬銈嗗绾剟鏁撻弬銈嗗闁跨喓娈曠拋瑙勫闁跨喐鏋婚幏鐑芥晸閺傘倖瀚� +#define SYS_RSTCR_SRAM_Pos 6 //写1对SRAM控制器进行一次复位，硬件自动清零 #define SYS_RSTCR_SRAM_Msk (0x01 << SYS_RSTCR_SRAM_Pos) -#define SYS_RSTCR_SDRAM_Pos 7 //閸愶拷1闁跨喐鏋婚幏绋碊RAM闁跨喐鏋婚幏鐑芥晸閺傘倖瀚归柨鐔告灮閹风兘鏁撻弬銈嗗闁跨喐鏋婚幏铚傜闁跨喕濞囬棃鈺傚娴ｅ秹鏁撻弬銈嗗绾剟鏁撻弬銈嗗闁跨喓娈曠拋瑙勫闁跨喐鏋婚幏鐑芥晸閺傘倖瀚� +#define SYS_RSTCR_SDRAM_Pos 7 //写1对SDRAM控制器进行一次复位，硬件自动清零 #define SYS_RSTCR_SDRAM_Msk (0x01 << SYS_RSTCR_SDRAM_Pos) -#define SYS_RSTCR_SDIO_Pos 8 //閸愶拷1闁跨喐鏋婚幏绋碊IO闁跨喐鏋婚幏鐑芥晸閺傘倖瀚规稉鈧柨鐔诲▏闂堚晜瀚规担宥夋晸閺傘倖瀚圭涵顒勬晸閺傘倖瀚归柨鐔烘畷鐠佽瀚归柨鐔告灮閹风兘鏁撻弬銈嗗 +#define SYS_RSTCR_SDIO_Pos 8 //写1对SDIO进行一次复位，硬件自动清零 #define SYS_RSTCR_SDIO_Msk (0x01 << SYS_RSTCR_SDIO_Pos) -#define SYS_RSTCR_LCD_Pos 9 //閸愶拷1闁跨喐鏋婚幏绋珻D闁跨喐鏋婚幏鐑芥晸閺傘倖瀚规稉鈧柨鐔诲▏闂堚晜瀚规担宥夋晸閺傘倖瀚圭涵顒勬晸閺傘倖瀚归柨鐔烘畷鐠佽瀚归柨鐔告灮閹风兘鏁撻弬銈嗗 +#define SYS_RSTCR_LCD_Pos 9 //写1对LCD进行一次复位，硬件自动清零 #define SYS_RSTCR_LCD_Msk (0x01 << SYS_RSTCR_LCD_Pos) -#define SYS_RSTCR_CAN_Pos 10 //閸愶拷1闁跨喐鏋婚幏绋N闁跨喐鏋婚幏鐑芥晸閺傘倖瀚规稉鈧柨鐔诲▏闂堚晜瀚规担宥夋晸閺傘倖瀚圭涵顒勬晸閺傘倖瀚归柨鐔烘畷鐠佽瀚归柨鐔告灮閹风兘鏁撻弬銈嗗 +#define SYS_RSTCR_CAN_Pos 10 //写1对CAN进行一次复位，硬件自动清零 #define SYS_RSTCR_CAN_Msk (0x01 << SYS_RSTCR_CAN_Pos) -#define SYS_RSTSR_POR_Pos 0 //1 闁跨喐鏋婚幏鐑芥晸鐞涙娅㈤幏绋癘R闁跨喐鏋婚幏铚傜秴闁跨喐鏋婚幏宄板晸1闁跨喐鏋婚幏鐑芥晸閺傘倖瀚� +#define SYS_RSTSR_POR_Pos 0 //1 出现过POR复位，写1清零 #define SYS_RSTSR_POR_Msk (0x01 << SYS_RSTSR_POR_Pos) -#define SYS_RSTSR_BOD_Pos 1 //1 闁跨喐鏋婚幏鐑芥晸鐞涙娅㈤幏绋D闁跨喐鏋婚幏铚傜秴闁跨喐鏋婚幏宄板晸1闁跨喐鏋婚幏鐑芥晸閺傘倖瀚� +#define SYS_RSTSR_BOD_Pos 1 //1 出现过BOD复位，写1清零 #define SYS_RSTSR_BOD_Msk (0x01 << SYS_RSTSR_BOD_Pos) -#define SYS_RSTSR_PIN_Pos 2 //1 闁跨喐鏋婚幏鐑芥晸鐞涙娅㈤幏鐑芥晸鐟欙綁鍎撮柨鐔告灮閹风兘鏁撻懘姘舵交閹疯渹缍呴柨鐔告灮閹峰嘲鍟�1闁跨喐鏋婚幏鐑芥晸閺傘倖瀚� +#define SYS_RSTSR_PIN_Pos 2 //1 出现过外部引脚复位，写1清零 #define SYS_RSTSR_PIN_Msk (0x01 << SYS_RSTSR_PIN_Pos) -#define SYS_RSTSR_WDT_Pos 3 //1 闁跨喐鏋婚幏鐑芥晸鐞涙娅㈤幏绋篋T闁跨喐鏋婚幏铚傜秴闁跨喐鏋婚幏宄板晸1闁跨喐鏋婚幏鐑芥晸閺傘倖瀚� +#define SYS_RSTSR_WDT_Pos 3 //1 出现过WDT复位，写1清零 #define SYS_RSTSR_WDT_Msk (0x01 << SYS_RSTSR_WDT_Pos) -#define SYS_RSTSR_SWRST_Pos 4 //Software Reset, 1 闁跨喐鏋婚幏鐑芥晸鐞涙娅㈤幏鐑芥晸閺傘倖瀚归柨鐔告灮閹风兘鏁撴潪澶哥串閹风兘鏁撻崣顐嫹1闁跨喐鏋婚幏鐑芥晸閺傘倖瀚� +#define SYS_RSTSR_SWRST_Pos 4 //Software Reset, 1 出现过软件复位，写1清零 #define SYS_RSTSR_SWRST_Msk (0x01 << SYS_RSTSR_SWRST_Pos) #define SYS_LRCCR_OFF_Pos 0 //Low Speed RC Off #define SYS_LRCCR_OFF_Msk (0x01 << SYS_LRCCR_OFF_Pos) -#define SYS_LRCTRIM0_R_Pos 0 //LRC闁跨喕顢滅喊澶嬪闁跨喐鏋婚幏鐑芥晸閺傘倖瀚规担锟� +#define SYS_LRCTRIM0_R_Pos 0 //LRC粗调控制位 #define SYS_LRCTRIM0_R_Msk (0x7FFF << SYS_LRCTRIM0_R_Pos) -#define SYS_LRCTRIM0_M_Pos 15 //LRC闁跨喎褰ㄧ喊澶嬪闁跨喐鏋婚幏鐑芥晸閺傘倖瀚规担锟� +#define SYS_LRCTRIM0_M_Pos 15 //LRC中调控制位 #define SYS_LRCTRIM0_M_Msk (0x3F << SYS_LRCTRIM2_M_Pos) -#define SYS_LRCTRIM0_F_Pos 21 //LRC缂佸棝鏁撻弬銈嗗闁跨喐鏋婚幏鐑芥晸閺傘倖瀚规担锟� +#define SYS_LRCTRIM0_F_Pos 21 //LRC细调控制位 #define SYS_LRCTRIM0_F_Msk (0x7FF << SYS_LRCTRIM0_F_Pos) -#define SYS_LRCTRIM1_U_Pos 0 //LRC U闁跨喐鏋婚幏鐑芥晸閺傘倖瀚归柨鐔告灮閹疯渹缍� +#define SYS_LRCTRIM1_U_Pos 0 //LRC U调控制位 #define SYS_LRCTRIM1_U_Msk (0x7FFF << SYS_LRCTRIM1_U_Pos) #define SYS_HRCCR_DBL_Pos 0 //Double Frequency 0 20MHz 1 40MHz @@ -327,42 +317,27 @@ typedef struct #define SYS_HRCCR_OFF_Pos 1 //High speed RC Off #define SYS_HRCCR_OFF_Msk (0x01 << SYS_HRCCR_OFF_Pos) -#define SYS_HRC20M_R_Pos 0 //HRC 20MHz闁跨喕顢滅喊澶嬪闁跨喐鏋婚幏鐑芥晸閺傘倖瀚规担锟� -#define SYS_HRC20M_R_Msk (0x3FFF << SYS_HRC20M_R_Pos) -#define SYS_HRC20M_F_Pos 16 //HRC 20MHz缂佸棝鏁撻弬銈嗗闁跨喐鏋婚幏鐑芥晸閺傘倖瀚规担锟� -#define SYS_HRC20M_F_Msk (0x7FF << SYS_HRC20M_F_Pos) - -#define SYS_HRC40M_R_Pos 0 //HRC 40MHz闁跨喕顢滅喊澶嬪闁跨喐鏋婚幏鐑芥晸閺傘倖瀚规担锟� -#define SYS_HRC40M_R_Msk (0x3FFF << SYS_HRC40M_R_Pos) -#define SYS_HRC40M_F_Pos 16 //HRC 40MHz缂佸棝鏁撻弬銈嗗闁跨喐鏋婚幏鐑芥晸閺傘倖瀚规担锟� -#define SYS_HRC40M_F_Msk (0x7FF << SYS_HRC40M_F_Pos) - -#define SYS_TEMPCR_OFF_Pos 0 //闁跨喖鎽惔锕佹彧閹风兘鏁撻弬銈嗗闁跨喐鏋婚幏鐑芥晸閹搭亝鍞婚幏锟� -#define SYS_TEMPCR_OFF_Msk (0x01 << SYS_TEMPCR_OFF_Pos) -#define SYS_TEMPCR_TRIM_Pos 4 //闁跨喖鎽惔锕佹彧閹风兘鏁撻弬銈嗗闁跨喐鏋婚幏绋礡IM -#define SYS_TEMPCR_TRIM_Msk (0x3F << SYS_TEMPCR_TRIM_Pos) - #define SYS_XTALCR_EN_Pos 0 #define SYS_XTALCR_EN_Msk (0x01 << SYS_XTALCR_EN_Pos) -#define SYS_PLLCR_OUTEN_Pos 0 //閸欘亪鏁撻弬銈嗗LOCK闁跨喐鏋婚幏鐑芥晸閺傘倖瀚归柨鐔告灮閹凤拷 +#define SYS_PLLCR_OUTEN_Pos 0 //只能LOCK后设置 #define SYS_PLLCR_OUTEN_Msk (0x01 << SYS_PLLCR_OUTEN_Pos) #define SYS_PLLCR_INSEL_Pos 1 //0 XTAL 1 HRC #define SYS_PLLCR_INSEL_Msk (0x01 << SYS_PLLCR_INSEL_Pos) #define SYS_PLLCR_OFF_Pos 2 #define SYS_PLLCR_OFF_Msk (0x01 << SYS_PLLCR_OFF_Pos) -#define SYS_PLLDIV_FBDIV_Pos 0 //PLL FeedBack闁跨喐鏋婚幏鐑筋暥闁跨喍鑼庢潏鐐闁跨喐鏋婚幏锟� -//VCO闁跨喐鏋婚幏鐑芥晸閻欙紕顣幏鐑芥晸閿燂拷 = PLL闁跨喐鏋婚幏鐑芥晸閺傘倖瀚归弮鍫曟晸閺傘倖瀚� / INDIV * 4 * FBDIV -//PLL闁跨喐鏋婚幏鐑芥晸閻欙紕顣幏鐑芥晸閿燂拷 = PLL闁跨喐鏋婚幏鐑芥晸閺傘倖瀚归弮鍫曟晸閺傘倖瀚� / INDIV * 4 * FBDIV / OUTDIV = VCO闁跨喐鏋婚幏鐑芥晸閻欙紕顣幏鐑芥晸閿燂拷 / OUTDIV +#define SYS_PLLDIV_FBDIV_Pos 0 /* PLL FeedBack分频寄存器 \ + VCO输出频率 = PLL输入时钟 / INDIV * 4 * FBDIV \ + PLL输出频率 = PLL输入时钟 / INDIV * 4 * FBDIV / OUTDIV = VCO输出频率 / OUTDIV */ #define SYS_PLLDIV_FBDIV_Msk (0x1FF << SYS_PLLDIV_FBDIV_Pos) -#define SYS_PLLDIV_ADDIV_Pos 9 //ADC閺冨爼鏁撻幒銉ょ串閹风兘鏁撻弬銈嗗闁跨喐鏋婚幏绋窩O闁跨喐鏋婚幏鐑芥晸閺傘倖瀚归柨鐔哄珱绾板瀚归柨鐔告灮閹烽攱妞傞柨鐔稿复閿濆繑瀚归柨鐔告灮閹风DDIV闁跨喐鏋婚幏鐑筋暥闁跨喐鏋婚幏鐑芥晸閺傘倖瀚规稉绡圖C闁跨喐鏋婚幏鐤祮闁跨喐鏋婚幏閿嬫闁跨喐鏋婚幏锟� +#define SYS_PLLDIV_ADDIV_Pos 9 //ADC时钟基（即VCO输出分频后的时钟）经ADDIV分频后作为ADC的转换时钟 #define SYS_PLLDIV_ADDIV_Msk (0x1F << SYS_PLLDIV_ADDIV_Pos) -#define SYS_PLLDIV_ADVCO_Pos 14 //0 VCO闁跨喐鏋婚幏鐑芥晸閿燂拷16闁跨喐鏋婚幏鐑筋暥闁跨喐鏋婚幏铚傝礋ADC閺冨爼鏁撻幒銉ょ串閹凤拷 1 VCO闁跨喐鏋婚幏鐑芥晸閺傘倖瀚归柨鐔告灮閹风兘鏁撻敓锟�32闁跨喐鏋婚幏鐑筋暥闁跨喐鏋婚幏铚傝礋ADC閺冨爼鏁撻幒銉ょ串閹凤拷 2 VCO闁跨喐鏋婚幏鐑芥晸閺傘倖瀚归柨鐔告灮閹风兘鏁撻敓锟�64闁跨喐鏋婚幏鐑筋暥闁跨喐鏋婚幏铚傝礋ADC閺冨爼鏁撻幒銉ょ串閹凤拷 +#define SYS_PLLDIV_ADVCO_Pos 14 //0 VCO输出16分频作为ADC时钟基 1 VCO输出经过32分频作为ADC时钟基 2 VCO输出经过64分频作为ADC时钟基 #define SYS_PLLDIV_ADVCO_Msk (0x03 << SYS_PLLDIV_ADVCO_Pos) -#define SYS_PLLDIV_INDIV_Pos 16 //PLL 闁跨喐鏋婚幏鐑芥晸閺傘倖瀚瑰┃鎰闁跨喐甯撮崙銈嗗妫帮拷 +#define SYS_PLLDIV_INDIV_Pos 16 //PLL 输入源时钟分频 #define SYS_PLLDIV_INDIV_Msk (0x1F << SYS_PLLDIV_INDIV_Pos) -#define SYS_PLLDIV_OUTDIV_Pos 24 //PLL 闁跨喐鏋婚幏鐑芥晸閺傘倖瀚归柨鐔哄珱绾板瀚归柨鐕傛嫹0 8闁跨喐鏋婚幏鐑筋暥 1 4闁跨喐鏋婚幏鐑筋暥 0 2闁跨喐鏋婚幏鐑筋暥 +#define SYS_PLLDIV_OUTDIV_Pos 24 //PLL 输出分频，0 8分频 1 4分频 0 2分频 #define SYS_PLLDIV_OUTDIV_Msk (0x03 << SYS_PLLDIV_OUTDIV_Pos) #define SYS_PLLSET_LPFBW_Pos 0 //PLL Low Pass Filter Bandwidth @@ -376,28 +351,21 @@ typedef struct #define SYS_PLLSET_CHPADJM_Pos 11 //PLL charge pump MSB current Adjustment #define SYS_PLLSET_CHPADJM_Msk (0x03 << SYS_PLLSET_CHPADJM_Pos) -#define SYS_BODIE_1V9_Pos 0 //BOD 1.9V闁跨喖銈虹涵閿嬪闁跨喐鏋婚幏鐑芥晸閺傘倖瀚归柨鐔峰建鐠佽瀚规担鍧楁晸閺傘倖瀚� -#define SYS_BODIE_1V9_Msk (0x01 << SYS_BODIE_1V9_Pos) -#define SYS_BODIE_2V2_Pos 1 //BOD 2.2V闁跨喖銈虹涵閿嬪闁跨喐鏋婚幏鐑芥晸閺傘倖瀚归柨鐔峰建鐠佽瀚规担鍧楁晸閺傘倖瀚� +#define SYS_BODIE_2V2_Pos 1 //BOD 2.2V等级触发中断使能 #define SYS_BODIE_2V2_Msk (0x01 << SYS_BODIE_2V2_Pos) -#define SYS_BODIF_1V9_Pos 0 //BOD 1.9V闁跨喖銈虹涵閿嬪闁跨喐鏋婚幏鐑芥晸閺傘倖瀚归柨鐔峰建鐠佽瀚归悩鑸碘偓渚€鏁撻弬銈嗗閸愶拷1闁跨喐鏋婚幏鐑芥晸閺傘倖瀚� -#define SYS_BODIF_1V9_Msk (0x01 << SYS_BODIF_1V9_Pos) -#define SYS_BODIF_2V2_Pos 1 //BOD 2.2V闁跨喖銈虹涵閿嬪闁跨喐鏋婚幏鐑芥晸閺傘倖瀚归柨鐔峰建鐠佽瀚归悩鑸碘偓渚€鏁撻弬銈嗗閸愶拷1闁跨喐鏋婚幏鐑芥晸閺傘倖瀚� +#define SYS_BODIF_2V2_Pos 1 //BOD 2.2V等级触发中断状态，写1清零 #define SYS_BODIF_2V2_Msk (0x01 << SYS_BODIF_2V2_Pos) -#define SYS_ADC1IN7_SEL_Pos 0 //ADC1濡繝鏁撻弬銈嗗濡繝鏁撻弬銈嗗闁岸鏁撻弬銈嗗7闁跨喐鏋婚幏锟�1 闁跨喖鎽惔锕佹彧閹风兘鏁撻弬銈嗗闁跨喐鏋婚幏锟� 2 闁跨喐鏋婚幏閿嬬毉闁跨喓鐛ら敓锟� 3 RTC闁跨喐鏋婚幏閿嬬爱闁跨喐鏋婚幏绋 4 闁跨喐鏋婚幏鐑芥晸閺傘倖瀚瑰┃鎰版晸閺傘倖瀚笲G 5 PDM33 +#define SYS_ADC1IN7_SEL_Pos 0 //ADC1模块模拟通道7，1 温度传感器 2 电池电压 3 RTC电源域BG 4 主电源域BG 5 PDM33 #define SYS_ADC1IN7_SEL_Msk (0x0F << SYS_ADC1IN7_SEL_Pos) -#define SYS_ADC1IN7_IOON_Pos 4 //ADC1濡繝鏁撻弬銈嗗濡繝鏁撻弬銈嗗闁岸鏁撻弬銈嗗7闁跨喐鏋婚幏鐑芥晸閺傘倖瀚笽O闁跨喐鏋婚幏鐑芥晸閺傘倖瀚� +#define SYS_ADC1IN7_IOON_Pos 4 //ADC1模块模拟通道7所用IO开关 #define SYS_ADC1IN7_IOON_Msk (0x01 << SYS_ADC1IN7_IOON_Pos) -#define SYS_BODCR_EN_Pos 0 -#define SYS_BODCR_EN_Msk (0x01 << SYS_BODCR_EN_Pos) - typedef struct { - __IO uint32_t PORTA_SEL; //闁跨喐鏋婚幏绋癘RTA_SEL[2n+2:2n]闁跨喐鏋婚幏鐑芥晸閺傘倖瀚规惔鏃堟晸閺傘倖瀚归崐濂告晸閺傘倖瀚归柨鐔告灮閹风òORTA.PINn闁跨喐鏋婚幏鐑芥晸閺傘倖瀚归柨鐔告灮閹风兘鏁撻惌顐ゎ劜閹风ěPIO闁跨喐鏋婚幏閿嬆侀柨鐔恍掗妴渚€鏁撻弬銈嗗闁跨喕顢滅粵澶屾閹风兘鏁撻弬銈嗗 - //闁跨喐鏋婚幏鐑芥晸閺傘倖瀚归崐闂磋礋PORTA_PINn_FUNMUX閺冨爼鏁撻弬銈嗗PORTA.PINn闁跨喐鏋婚幏鐑芥晸閼存艾灏呴幏鐑解偓姘舵晸閺傘倖瀚筆ORTA_MUX闁跨喍鑼庢潏鐐闁跨喐鏋婚幏鐑芥晸閺傘倖瀚归柨鐔稿复绾板瀚归柨鐔告灮閹风兘鏁撻弬銈嗗闁跨喐鏋婚幏鐑芥晸閺傘倖瀚归柨鐔告灮閹风兘鏁撻弬銈嗗 + __IO uint32_t PORTA_SEL; /*给PORTA_SEL[2n+2:2n]赋相应的值，将PORTA.PINn引脚配置成GPIO、模拟、数字等功能 + 当赋值为PORTA_PINn_FUNMUX时，PORTA.PINn引脚可通过PORTA_MUX寄存器连接到各种数字外设 */ __IO uint32_t PORTB_SEL; __IO uint32_t PORTC_SEL; @@ -466,7 +434,7 @@ typedef struct uint32_t RESERVED9[28]; - __IO uint32_t PORTA_PULLU; //闁跨喐鏋婚幏鐑芥晸閺傘倖瀚规担鍧楁晸閺傘倖瀚� + __IO uint32_t PORTA_PULLU; //上拉使能 uint32_t RESERVED10[3]; @@ -482,7 +450,7 @@ typedef struct uint32_t RESERVED13[51]; - __IO uint32_t PORTB_PULLD; //闁跨喐鏋婚幏鐑芥晸閺傘倖瀚规担鍧楁晸閺傘倖瀚� + __IO uint32_t PORTB_PULLD; //下拉使能 uint32_t RESERVED14[3]; @@ -494,7 +462,7 @@ typedef struct uint32_t RESERVED16[135]; - __IO uint32_t PORTM_DRIVS; //闁跨喐鏋婚幏鐑芥晸閺傘倖瀚瑰娲晸閺傘倖瀚� + __IO uint32_t PORTM_DRIVS; //驱动强度 uint32_t RESERVED17[3]; @@ -506,7 +474,7 @@ typedef struct uint32_t RESERVED19[39]; - __IO uint32_t PORTA_INEN; //闁跨喐鏋婚幏鐑芥晸閺傘倖瀚规担鍧楁晸閺傘倖瀚� + __IO uint32_t PORTA_INEN; //输入使能 uint32_t RESERVED20[3]; @@ -529,6 +497,645 @@ typedef struct __IO uint32_t PORTP_INEN; } PORT_TypeDef; +#define PORT_PORTA_PULLU_PIN0_Pos 0 +#define PORT_PORTA_PULLU_PIN0_Msk (0x01 << PORT_PORTA_PULLU_PIN0_Pos) +#define PORT_PORTA_PULLU_PIN1_Pos 1 +#define PORT_PORTA_PULLU_PIN1_Msk (0x01 << PORT_PORTA_PULLU_PIN1_Pos) +#define PORT_PORTA_PULLU_PIN2_Pos 2 +#define PORT_PORTA_PULLU_PIN2_Msk (0x01 << PORT_PORTA_PULLU_PIN2_Pos) +#define PORT_PORTA_PULLU_PIN3_Pos 3 +#define PORT_PORTA_PULLU_PIN3_Msk (0x01 << PORT_PORTA_PULLU_PIN3_Pos) +#define PORT_PORTA_PULLU_PIN4_Pos 4 +#define PORT_PORTA_PULLU_PIN4_Msk (0x01 << PORT_PORTA_PULLU_PIN4_Pos) +#define PORT_PORTA_PULLU_PIN5_Pos 5 +#define PORT_PORTA_PULLU_PIN5_Msk (0x01 << PORT_PORTA_PULLU_PIN5_Pos) +#define PORT_PORTA_PULLU_PIN6_Pos 6 +#define PORT_PORTA_PULLU_PIN6_Msk (0x01 << PORT_PORTA_PULLU_PIN6_Pos) +#define PORT_PORTA_PULLU_PIN7_Pos 7 +#define PORT_PORTA_PULLU_PIN7_Msk (0x01 << PORT_PORTA_PULLU_PIN7_Pos) +#define PORT_PORTA_PULLU_PIN8_Pos 8 +#define PORT_PORTA_PULLU_PIN8_Msk (0x01 << PORT_PORTA_PULLU_PIN8_Pos) +#define PORT_PORTA_PULLU_PIN9_Pos 9 +#define PORT_PORTA_PULLU_PIN9_Msk (0x01 << PORT_PORTA_PULLU_PIN9_Pos) +#define PORT_PORTA_PULLU_PIN10_Pos 10 +#define PORT_PORTA_PULLU_PIN10_Msk (0x01 << PORT_PORTA_PULLU_PIN10_Pos) +#define PORT_PORTA_PULLU_PIN11_Pos 11 +#define PORT_PORTA_PULLU_PIN11_Msk (0x01 << PORT_PORTA_PULLU_PIN11_Pos) +#define PORT_PORTA_PULLU_PIN12_Pos 12 +#define PORT_PORTA_PULLU_PIN12_Msk (0x01 << PORT_PORTA_PULLU_PIN12_Pos) +#define PORT_PORTA_PULLU_PIN13_Pos 13 +#define PORT_PORTA_PULLU_PIN13_Msk (0x01 << PORT_PORTA_PULLU_PIN13_Pos) +#define PORT_PORTA_PULLU_PIN14_Pos 14 +#define PORT_PORTA_PULLU_PIN14_Msk (0x01 << PORT_PORTA_PULLU_PIN14_Pos) +#define PORT_PORTA_PULLU_PIN15_Pos 15 +#define PORT_PORTA_PULLU_PIN15_Msk (0x01 << PORT_PORTA_PULLU_PIN15_Pos) + +#define PORT_PORTC_PULLU_PIN0_Pos 0 +#define PORT_PORTC_PULLU_PIN0_Msk (0x01 << PORT_PORTC_PULLU_PIN0_Pos) +#define PORT_PORTC_PULLU_PIN1_Pos 1 +#define PORT_PORTC_PULLU_PIN1_Msk (0x01 << PORT_PORTC_PULLU_PIN1_Pos) +#define PORT_PORTC_PULLU_PIN2_Pos 2 +#define PORT_PORTC_PULLU_PIN2_Msk (0x01 << PORT_PORTC_PULLU_PIN2_Pos) +#define PORT_PORTC_PULLU_PIN3_Pos 3 +#define PORT_PORTC_PULLU_PIN3_Msk (0x01 << PORT_PORTC_PULLU_PIN3_Pos) +#define PORT_PORTC_PULLU_PIN4_Pos 4 +#define PORT_PORTC_PULLU_PIN4_Msk (0x01 << PORT_PORTC_PULLU_PIN4_Pos) +#define PORT_PORTC_PULLU_PIN5_Pos 5 +#define PORT_PORTC_PULLU_PIN5_Msk (0x01 << PORT_PORTC_PULLU_PIN5_Pos) +#define PORT_PORTC_PULLU_PIN6_Pos 6 +#define PORT_PORTC_PULLU_PIN6_Msk (0x01 << PORT_PORTC_PULLU_PIN6_Pos) +#define PORT_PORTC_PULLU_PIN7_Pos 7 +#define PORT_PORTC_PULLU_PIN7_Msk (0x01 << PORT_PORTC_PULLU_PIN7_Pos) +#define PORT_PORTC_PULLU_PIN8_Pos 8 +#define PORT_PORTC_PULLU_PIN8_Msk (0x01 << PORT_PORTC_PULLU_PIN8_Pos) +#define PORT_PORTC_PULLU_PIN9_Pos 9 +#define PORT_PORTC_PULLU_PIN9_Msk (0x01 << PORT_PORTC_PULLU_PIN9_Pos) +#define PORT_PORTC_PULLU_PIN10_Pos 10 +#define PORT_PORTC_PULLU_PIN10_Msk (0x01 << PORT_PORTC_PULLU_PIN10_Pos) +#define PORT_PORTC_PULLU_PIN11_Pos 11 +#define PORT_PORTC_PULLU_PIN11_Msk (0x01 << PORT_PORTC_PULLU_PIN11_Pos) +#define PORT_PORTC_PULLU_PIN12_Pos 12 +#define PORT_PORTC_PULLU_PIN12_Msk (0x01 << PORT_PORTC_PULLU_PIN12_Pos) +#define PORT_PORTC_PULLU_PIN13_Pos 13 +#define PORT_PORTC_PULLU_PIN13_Msk (0x01 << PORT_PORTC_PULLU_PIN13_Pos) +#define PORT_PORTC_PULLU_PIN14_Pos 14 +#define PORT_PORTC_PULLU_PIN14_Msk (0x01 << PORT_PORTC_PULLU_PIN14_Pos) +#define PORT_PORTC_PULLU_PIN15_Pos 15 +#define PORT_PORTC_PULLU_PIN15_Msk (0x01 << PORT_PORTC_PULLU_PIN15_Pos) + +#define PORT_PORTM_PULLU_PIN0_Pos 0 +#define PORT_PORTM_PULLU_PIN0_Msk (0x01 << PORT_PORTM_PULLU_PIN0_Pos) +#define PORT_PORTM_PULLU_PIN1_Pos 1 +#define PORT_PORTM_PULLU_PIN1_Msk (0x01 << PORT_PORTM_PULLU_PIN1_Pos) +#define PORT_PORTM_PULLU_PIN2_Pos 2 +#define PORT_PORTM_PULLU_PIN2_Msk (0x01 << PORT_PORTM_PULLU_PIN2_Pos) +#define PORT_PORTM_PULLU_PIN3_Pos 3 +#define PORT_PORTM_PULLU_PIN3_Msk (0x01 << PORT_PORTM_PULLU_PIN3_Pos) +#define PORT_PORTM_PULLU_PIN4_Pos 4 +#define PORT_PORTM_PULLU_PIN4_Msk (0x01 << PORT_PORTM_PULLU_PIN4_Pos) +#define PORT_PORTM_PULLU_PIN5_Pos 5 +#define PORT_PORTM_PULLU_PIN5_Msk (0x01 << PORT_PORTM_PULLU_PIN5_Pos) +#define PORT_PORTM_PULLU_PIN6_Pos 6 +#define PORT_PORTM_PULLU_PIN6_Msk (0x01 << PORT_PORTM_PULLU_PIN6_Pos) +#define PORT_PORTM_PULLU_PIN7_Pos 7 +#define PORT_PORTM_PULLU_PIN7_Msk (0x01 << PORT_PORTM_PULLU_PIN7_Pos) +#define PORT_PORTM_PULLU_PIN8_Pos 8 +#define PORT_PORTM_PULLU_PIN8_Msk (0x01 << PORT_PORTM_PULLU_PIN8_Pos) +#define PORT_PORTM_PULLU_PIN9_Pos 9 +#define PORT_PORTM_PULLU_PIN9_Msk (0x01 << PORT_PORTM_PULLU_PIN9_Pos) +#define PORT_PORTM_PULLU_PIN10_Pos 10 +#define PORT_PORTM_PULLU_PIN10_Msk (0x01 << PORT_PORTM_PULLU_PIN10_Pos) +#define PORT_PORTM_PULLU_PIN11_Pos 11 +#define PORT_PORTM_PULLU_PIN11_Msk (0x01 << PORT_PORTM_PULLU_PIN11_Pos) +#define PORT_PORTM_PULLU_PIN12_Pos 12 +#define PORT_PORTM_PULLU_PIN12_Msk (0x01 << PORT_PORTM_PULLU_PIN12_Pos) +#define PORT_PORTM_PULLU_PIN13_Pos 13 +#define PORT_PORTM_PULLU_PIN13_Msk (0x01 << PORT_PORTM_PULLU_PIN13_Pos) +#define PORT_PORTM_PULLU_PIN14_Pos 14 +#define PORT_PORTM_PULLU_PIN14_Msk (0x01 << PORT_PORTM_PULLU_PIN14_Pos) +#define PORT_PORTM_PULLU_PIN15_Pos 15 +#define PORT_PORTM_PULLU_PIN15_Msk (0x01 << PORT_PORTM_PULLU_PIN15_Pos) +#define PORT_PORTM_PULLU_PIN16_Pos 16 +#define PORT_PORTM_PULLU_PIN16_Msk (0x01 << PORT_PORTM_PULLU_PIN16_Pos) +#define PORT_PORTM_PULLU_PIN17_Pos 17 +#define PORT_PORTM_PULLU_PIN17_Msk (0x01 << PORT_PORTM_PULLU_PIN17_Pos) +#define PORT_PORTM_PULLU_PIN18_Pos 18 +#define PORT_PORTM_PULLU_PIN18_Msk (0x01 << PORT_PORTM_PULLU_PIN18_Pos) +#define PORT_PORTM_PULLU_PIN19_Pos 19 +#define PORT_PORTM_PULLU_PIN19_Msk (0x01 << PORT_PORTM_PULLU_PIN19_Pos) +#define PORT_PORTM_PULLU_PIN20_Pos 20 +#define PORT_PORTM_PULLU_PIN20_Msk (0x01 << PORT_PORTM_PULLU_PIN20_Pos) +#define PORT_PORTM_PULLU_PIN21_Pos 21 +#define PORT_PORTM_PULLU_PIN21_Msk (0x01 << PORT_PORTM_PULLU_PIN21_Pos) +#define PORT_PORTM_PULLU_PIN22_Pos 22 +#define PORT_PORTM_PULLU_PIN22_Msk (0x01 << PORT_PORTM_PULLU_PIN22_Pos) +#define PORT_PORTM_PULLU_PIN23_Pos 23 +#define PORT_PORTM_PULLU_PIN23_Msk (0x01 << PORT_PORTM_PULLU_PIN23_Pos) + +#define PORT_PORTP_PULLU_PIN0_Pos 0 +#define PORT_PORTP_PULLU_PIN0_Msk (0x01 << PORT_PORTP_PULLU_PIN0_Pos) +#define PORT_PORTP_PULLU_PIN1_Pos 1 +#define PORT_PORTP_PULLU_PIN1_Msk (0x01 << PORT_PORTP_PULLU_PIN1_Pos) +#define PORT_PORTP_PULLU_PIN2_Pos 2 +#define PORT_PORTP_PULLU_PIN2_Msk (0x01 << PORT_PORTP_PULLU_PIN2_Pos) +#define PORT_PORTP_PULLU_PIN3_Pos 3 +#define PORT_PORTP_PULLU_PIN3_Msk (0x01 << PORT_PORTP_PULLU_PIN3_Pos) +#define PORT_PORTP_PULLU_PIN4_Pos 4 +#define PORT_PORTP_PULLU_PIN4_Msk (0x01 << PORT_PORTP_PULLU_PIN4_Pos) +#define PORT_PORTP_PULLU_PIN5_Pos 5 +#define PORT_PORTP_PULLU_PIN5_Msk (0x01 << PORT_PORTP_PULLU_PIN5_Pos) +#define PORT_PORTP_PULLU_PIN6_Pos 6 +#define PORT_PORTP_PULLU_PIN6_Msk (0x01 << PORT_PORTP_PULLU_PIN6_Pos) +#define PORT_PORTP_PULLU_PIN7_Pos 7 +#define PORT_PORTP_PULLU_PIN7_Msk (0x01 << PORT_PORTP_PULLU_PIN7_Pos) +#define PORT_PORTP_PULLU_PIN8_Pos 8 +#define PORT_PORTP_PULLU_PIN8_Msk (0x01 << PORT_PORTP_PULLU_PIN8_Pos) +#define PORT_PORTP_PULLU_PIN9_Pos 9 +#define PORT_PORTP_PULLU_PIN9_Msk (0x01 << PORT_PORTP_PULLU_PIN9_Pos) +#define PORT_PORTP_PULLU_PIN10_Pos 10 +#define PORT_PORTP_PULLU_PIN10_Msk (0x01 << PORT_PORTP_PULLU_PIN10_Pos) +#define PORT_PORTP_PULLU_PIN11_Pos 11 +#define PORT_PORTP_PULLU_PIN11_Msk (0x01 << PORT_PORTP_PULLU_PIN11_Pos) +#define PORT_PORTP_PULLU_PIN12_Pos 12 +#define PORT_PORTP_PULLU_PIN12_Msk (0x01 << PORT_PORTP_PULLU_PIN12_Pos) +#define PORT_PORTP_PULLU_PIN13_Pos 13 +#define PORT_PORTP_PULLU_PIN13_Msk (0x01 << PORT_PORTP_PULLU_PIN13_Pos) +#define PORT_PORTP_PULLU_PIN14_Pos 14 +#define PORT_PORTP_PULLU_PIN14_Msk (0x01 << PORT_PORTP_PULLU_PIN14_Pos) +#define PORT_PORTP_PULLU_PIN15_Pos 15 +#define PORT_PORTP_PULLU_PIN15_Msk (0x01 << PORT_PORTP_PULLU_PIN15_Pos) +#define PORT_PORTP_PULLU_PIN16_Pos 16 +#define PORT_PORTP_PULLU_PIN16_Msk (0x01 << PORT_PORTP_PULLU_PIN16_Pos) +#define PORT_PORTP_PULLU_PIN17_Pos 17 +#define PORT_PORTP_PULLU_PIN17_Msk (0x01 << PORT_PORTP_PULLU_PIN17_Pos) +#define PORT_PORTP_PULLU_PIN18_Pos 18 +#define PORT_PORTP_PULLU_PIN18_Msk (0x01 << PORT_PORTP_PULLU_PIN18_Pos) +#define PORT_PORTP_PULLU_PIN19_Pos 19 +#define PORT_PORTP_PULLU_PIN19_Msk (0x01 << PORT_PORTP_PULLU_PIN19_Pos) +#define PORT_PORTP_PULLU_PIN20_Pos 20 +#define PORT_PORTP_PULLU_PIN20_Msk (0x01 << PORT_PORTP_PULLU_PIN20_Pos) +#define PORT_PORTP_PULLU_PIN21_Pos 21 +#define PORT_PORTP_PULLU_PIN21_Msk (0x01 << PORT_PORTP_PULLU_PIN21_Pos) +#define PORT_PORTP_PULLU_PIN22_Pos 22 +#define PORT_PORTP_PULLU_PIN22_Msk (0x01 << PORT_PORTP_PULLU_PIN22_Pos) +#define PORT_PORTP_PULLU_PIN23_Pos 23 +#define PORT_PORTP_PULLU_PIN23_Msk (0x01 << PORT_PORTP_PULLU_PIN23_Pos) + +#define PORT_PORTB_PULLD_PIN0_Pos 0 +#define PORT_PORTB_PULLD_PIN0_Msk (0x01 << PORT_PORTB_PULLD_PIN0_Pos) +#define PORT_PORTB_PULLD_PIN1_Pos 1 +#define PORT_PORTB_PULLD_PIN1_Msk (0x01 << PORT_PORTB_PULLD_PIN1_Pos) +#define PORT_PORTB_PULLD_PIN2_Pos 2 +#define PORT_PORTB_PULLD_PIN2_Msk (0x01 << PORT_PORTB_PULLD_PIN2_Pos) +#define PORT_PORTB_PULLD_PIN3_Pos 3 +#define PORT_PORTB_PULLD_PIN3_Msk (0x01 << PORT_PORTB_PULLD_PIN3_Pos) +#define PORT_PORTB_PULLD_PIN4_Pos 4 +#define PORT_PORTB_PULLD_PIN4_Msk (0x01 << PORT_PORTB_PULLD_PIN4_Pos) +#define PORT_PORTB_PULLD_PIN5_Pos 5 +#define PORT_PORTB_PULLD_PIN5_Msk (0x01 << PORT_PORTB_PULLD_PIN5_Pos) +#define PORT_PORTB_PULLD_PIN6_Pos 6 +#define PORT_PORTB_PULLD_PIN6_Msk (0x01 << PORT_PORTB_PULLD_PIN6_Pos) +#define PORT_PORTB_PULLD_PIN7_Pos 7 +#define PORT_PORTB_PULLD_PIN7_Msk (0x01 << PORT_PORTB_PULLD_PIN7_Pos) +#define PORT_PORTB_PULLD_PIN8_Pos 8 +#define PORT_PORTB_PULLD_PIN8_Msk (0x01 << PORT_PORTB_PULLD_PIN8_Pos) +#define PORT_PORTB_PULLD_PIN9_Pos 9 +#define PORT_PORTB_PULLD_PIN9_Msk (0x01 << PORT_PORTB_PULLD_PIN9_Pos) +#define PORT_PORTB_PULLD_PIN10_Pos 10 +#define PORT_PORTB_PULLD_PIN10_Msk (0x01 << PORT_PORTB_PULLD_PIN10_Pos) +#define PORT_PORTB_PULLD_PIN11_Pos 11 +#define PORT_PORTB_PULLD_PIN11_Msk (0x01 << PORT_PORTB_PULLD_PIN11_Pos) +#define PORT_PORTB_PULLD_PIN12_Pos 12 +#define PORT_PORTB_PULLD_PIN12_Msk (0x01 << PORT_PORTB_PULLD_PIN12_Pos) +#define PORT_PORTB_PULLD_PIN13_Pos 13 +#define PORT_PORTB_PULLD_PIN13_Msk (0x01 << PORT_PORTB_PULLD_PIN13_Pos) +#define PORT_PORTB_PULLD_PIN14_Pos 14 +#define PORT_PORTB_PULLD_PIN14_Msk (0x01 << PORT_PORTB_PULLD_PIN14_Pos) +#define PORT_PORTB_PULLD_PIN15_Pos 15 +#define PORT_PORTB_PULLD_PIN15_Msk (0x01 << PORT_PORTB_PULLD_PIN15_Pos) + +#define PORT_PORTN_PULLD_PIN0_Pos 0 +#define PORT_PORTN_PULLD_PIN0_Msk (0x01 << PORT_PORTN_PULLD_PIN0_Pos) +#define PORT_PORTN_PULLD_PIN1_Pos 1 +#define PORT_PORTN_PULLD_PIN1_Msk (0x01 << PORT_PORTN_PULLD_PIN1_Pos) +#define PORT_PORTN_PULLD_PIN2_Pos 2 +#define PORT_PORTN_PULLD_PIN2_Msk (0x01 << PORT_PORTN_PULLD_PIN2_Pos) +#define PORT_PORTN_PULLD_PIN3_Pos 3 +#define PORT_PORTN_PULLD_PIN3_Msk (0x01 << PORT_PORTN_PULLD_PIN3_Pos) +#define PORT_PORTN_PULLD_PIN4_Pos 4 +#define PORT_PORTN_PULLD_PIN4_Msk (0x01 << PORT_PORTN_PULLD_PIN4_Pos) +#define PORT_PORTN_PULLD_PIN5_Pos 5 +#define PORT_PORTN_PULLD_PIN5_Msk (0x01 << PORT_PORTN_PULLD_PIN5_Pos) +#define PORT_PORTN_PULLD_PIN6_Pos 6 +#define PORT_PORTN_PULLD_PIN6_Msk (0x01 << PORT_PORTN_PULLD_PIN6_Pos) +#define PORT_PORTN_PULLD_PIN7_Pos 7 +#define PORT_PORTN_PULLD_PIN7_Msk (0x01 << PORT_PORTN_PULLD_PIN7_Pos) +#define PORT_PORTN_PULLD_PIN8_Pos 8 +#define PORT_PORTN_PULLD_PIN8_Msk (0x01 << PORT_PORTN_PULLD_PIN8_Pos) +#define PORT_PORTN_PULLD_PIN9_Pos 9 +#define PORT_PORTN_PULLD_PIN9_Msk (0x01 << PORT_PORTN_PULLD_PIN9_Pos) +#define PORT_PORTN_PULLD_PIN10_Pos 10 +#define PORT_PORTN_PULLD_PIN10_Msk (0x01 << PORT_PORTN_PULLD_PIN10_Pos) +#define PORT_PORTN_PULLD_PIN11_Pos 11 +#define PORT_PORTN_PULLD_PIN11_Msk (0x01 << PORT_PORTN_PULLD_PIN11_Pos) +#define PORT_PORTN_PULLD_PIN12_Pos 12 +#define PORT_PORTN_PULLD_PIN12_Msk (0x01 << PORT_PORTN_PULLD_PIN12_Pos) +#define PORT_PORTN_PULLD_PIN13_Pos 13 +#define PORT_PORTN_PULLD_PIN13_Msk (0x01 << PORT_PORTN_PULLD_PIN13_Pos) +#define PORT_PORTN_PULLD_PIN14_Pos 14 +#define PORT_PORTN_PULLD_PIN14_Msk (0x01 << PORT_PORTN_PULLD_PIN14_Pos) +#define PORT_PORTN_PULLD_PIN15_Pos 15 +#define PORT_PORTN_PULLD_PIN15_Msk (0x01 << PORT_PORTN_PULLD_PIN15_Pos) +#define PORT_PORTN_PULLD_PIN16_Pos 16 +#define PORT_PORTN_PULLD_PIN16_Msk (0x01 << PORT_PORTN_PULLD_PIN16_Pos) +#define PORT_PORTN_PULLD_PIN17_Pos 17 +#define PORT_PORTN_PULLD_PIN17_Msk (0x01 << PORT_PORTN_PULLD_PIN17_Pos) +#define PORT_PORTN_PULLD_PIN18_Pos 18 +#define PORT_PORTN_PULLD_PIN18_Msk (0x01 << PORT_PORTN_PULLD_PIN18_Pos) +#define PORT_PORTN_PULLD_PIN19_Pos 19 +#define PORT_PORTN_PULLD_PIN19_Msk (0x01 << PORT_PORTN_PULLD_PIN19_Pos) +#define PORT_PORTN_PULLD_PIN20_Pos 20 +#define PORT_PORTN_PULLD_PIN20_Msk (0x01 << PORT_PORTN_PULLD_PIN20_Pos) +#define PORT_PORTN_PULLD_PIN21_Pos 21 +#define PORT_PORTN_PULLD_PIN21_Msk (0x01 << PORT_PORTN_PULLD_PIN21_Pos) +#define PORT_PORTN_PULLD_PIN22_Pos 22 +#define PORT_PORTN_PULLD_PIN22_Msk (0x01 << PORT_PORTN_PULLD_PIN22_Pos) +#define PORT_PORTN_PULLD_PIN23_Pos 23 +#define PORT_PORTN_PULLD_PIN23_Msk (0x01 << PORT_PORTN_PULLD_PIN23_Pos) + +#define PORT_PORTM_DRIVS_PIN0_Pos 0 +#define PORT_PORTM_DRIVS_PIN0_Msk (0x01 << PORT_PORTM_DRIVS_PIN0_Pos) +#define PORT_PORTM_DRIVS_PIN1_Pos 1 +#define PORT_PORTM_DRIVS_PIN1_Msk (0x01 << PORT_PORTM_DRIVS_PIN1_Pos) +#define PORT_PORTM_DRIVS_PIN2_Pos 2 +#define PORT_PORTM_DRIVS_PIN2_Msk (0x01 << PORT_PORTM_DRIVS_PIN2_Pos) +#define PORT_PORTM_DRIVS_PIN3_Pos 3 +#define PORT_PORTM_DRIVS_PIN3_Msk (0x01 << PORT_PORTM_DRIVS_PIN3_Pos) +#define PORT_PORTM_DRIVS_PIN4_Pos 4 +#define PORT_PORTM_DRIVS_PIN4_Msk (0x01 << PORT_PORTM_DRIVS_PIN4_Pos) +#define PORT_PORTM_DRIVS_PIN5_Pos 5 +#define PORT_PORTM_DRIVS_PIN5_Msk (0x01 << PORT_PORTM_DRIVS_PIN5_Pos) +#define PORT_PORTM_DRIVS_PIN6_Pos 6 +#define PORT_PORTM_DRIVS_PIN6_Msk (0x01 << PORT_PORTM_DRIVS_PIN6_Pos) +#define PORT_PORTM_DRIVS_PIN7_Pos 7 +#define PORT_PORTM_DRIVS_PIN7_Msk (0x01 << PORT_PORTM_DRIVS_PIN7_Pos) +#define PORT_PORTM_DRIVS_PIN8_Pos 8 +#define PORT_PORTM_DRIVS_PIN8_Msk (0x01 << PORT_PORTM_DRIVS_PIN8_Pos) +#define PORT_PORTM_DRIVS_PIN9_Pos 9 +#define PORT_PORTM_DRIVS_PIN9_Msk (0x01 << PORT_PORTM_DRIVS_PIN9_Pos) +#define PORT_PORTM_DRIVS_PIN10_Pos 10 +#define PORT_PORTM_DRIVS_PIN10_Msk (0x01 << PORT_PORTM_DRIVS_PIN10_Pos) +#define PORT_PORTM_DRIVS_PIN11_Pos 11 +#define PORT_PORTM_DRIVS_PIN11_Msk (0x01 << PORT_PORTM_DRIVS_PIN11_Pos) +#define PORT_PORTM_DRIVS_PIN12_Pos 12 +#define PORT_PORTM_DRIVS_PIN12_Msk (0x01 << PORT_PORTM_DRIVS_PIN12_Pos) +#define PORT_PORTM_DRIVS_PIN13_Pos 13 +#define PORT_PORTM_DRIVS_PIN13_Msk (0x01 << PORT_PORTM_DRIVS_PIN13_Pos) +#define PORT_PORTM_DRIVS_PIN14_Pos 14 +#define PORT_PORTM_DRIVS_PIN14_Msk (0x01 << PORT_PORTM_DRIVS_PIN14_Pos) +#define PORT_PORTM_DRIVS_PIN15_Pos 15 +#define PORT_PORTM_DRIVS_PIN15_Msk (0x01 << PORT_PORTM_DRIVS_PIN15_Pos) +#define PORT_PORTM_DRIVS_PIN16_Pos 16 +#define PORT_PORTM_DRIVS_PIN16_Msk (0x01 << PORT_PORTM_DRIVS_PIN16_Pos) +#define PORT_PORTM_DRIVS_PIN17_Pos 17 +#define PORT_PORTM_DRIVS_PIN17_Msk (0x01 << PORT_PORTM_DRIVS_PIN17_Pos) +#define PORT_PORTM_DRIVS_PIN18_Pos 18 +#define PORT_PORTM_DRIVS_PIN18_Msk (0x01 << PORT_PORTM_DRIVS_PIN18_Pos) +#define PORT_PORTM_DRIVS_PIN19_Pos 19 +#define PORT_PORTM_DRIVS_PIN19_Msk (0x01 << PORT_PORTM_DRIVS_PIN19_Pos) +#define PORT_PORTM_DRIVS_PIN20_Pos 20 +#define PORT_PORTM_DRIVS_PIN20_Msk (0x01 << PORT_PORTM_DRIVS_PIN20_Pos) +#define PORT_PORTM_DRIVS_PIN21_Pos 21 +#define PORT_PORTM_DRIVS_PIN21_Msk (0x01 << PORT_PORTM_DRIVS_PIN21_Pos) +#define PORT_PORTM_DRIVS_PIN22_Pos 22 +#define PORT_PORTM_DRIVS_PIN22_Msk (0x01 << PORT_PORTM_DRIVS_PIN22_Pos) +#define PORT_PORTM_DRIVS_PIN23_Pos 23 +#define PORT_PORTM_DRIVS_PIN23_Msk (0x01 << PORT_PORTM_DRIVS_PIN23_Pos) + +#define PORT_PORTN_DRIVS_PIN0_Pos 0 +#define PORT_PORTN_DRIVS_PIN0_Msk (0x01 << PORT_PORTN_DRIVS_PIN0_Pos) +#define PORT_PORTN_DRIVS_PIN1_Pos 1 +#define PORT_PORTN_DRIVS_PIN1_Msk (0x01 << PORT_PORTN_DRIVS_PIN1_Pos) +#define PORT_PORTN_DRIVS_PIN2_Pos 2 +#define PORT_PORTN_DRIVS_PIN2_Msk (0x01 << PORT_PORTN_DRIVS_PIN2_Pos) +#define PORT_PORTN_DRIVS_PIN3_Pos 3 +#define PORT_PORTN_DRIVS_PIN3_Msk (0x01 << PORT_PORTN_DRIVS_PIN3_Pos) +#define PORT_PORTN_DRIVS_PIN4_Pos 4 +#define PORT_PORTN_DRIVS_PIN4_Msk (0x01 << PORT_PORTN_DRIVS_PIN4_Pos) +#define PORT_PORTN_DRIVS_PIN5_Pos 5 +#define PORT_PORTN_DRIVS_PIN5_Msk (0x01 << PORT_PORTN_DRIVS_PIN5_Pos) +#define PORT_PORTN_DRIVS_PIN6_Pos 6 +#define PORT_PORTN_DRIVS_PIN6_Msk (0x01 << PORT_PORTN_DRIVS_PIN6_Pos) +#define PORT_PORTN_DRIVS_PIN7_Pos 7 +#define PORT_PORTN_DRIVS_PIN7_Msk (0x01 << PORT_PORTN_DRIVS_PIN7_Pos) +#define PORT_PORTN_DRIVS_PIN8_Pos 8 +#define PORT_PORTN_DRIVS_PIN8_Msk (0x01 << PORT_PORTN_DRIVS_PIN8_Pos) +#define PORT_PORTN_DRIVS_PIN9_Pos 9 +#define PORT_PORTN_DRIVS_PIN9_Msk (0x01 << PORT_PORTN_DRIVS_PIN9_Pos) +#define PORT_PORTN_DRIVS_PIN10_Pos 10 +#define PORT_PORTN_DRIVS_PIN10_Msk (0x01 << PORT_PORTN_DRIVS_PIN10_Pos) +#define PORT_PORTN_DRIVS_PIN11_Pos 11 +#define PORT_PORTN_DRIVS_PIN11_Msk (0x01 << PORT_PORTN_DRIVS_PIN11_Pos) +#define PORT_PORTN_DRIVS_PIN12_Pos 12 +#define PORT_PORTN_DRIVS_PIN12_Msk (0x01 << PORT_PORTN_DRIVS_PIN12_Pos) +#define PORT_PORTN_DRIVS_PIN13_Pos 13 +#define PORT_PORTN_DRIVS_PIN13_Msk (0x01 << PORT_PORTN_DRIVS_PIN13_Pos) +#define PORT_PORTN_DRIVS_PIN14_Pos 14 +#define PORT_PORTN_DRIVS_PIN14_Msk (0x01 << PORT_PORTN_DRIVS_PIN14_Pos) +#define PORT_PORTN_DRIVS_PIN15_Pos 15 +#define PORT_PORTN_DRIVS_PIN15_Msk (0x01 << PORT_PORTN_DRIVS_PIN15_Pos) +#define PORT_PORTN_DRIVS_PIN16_Pos 16 +#define PORT_PORTN_DRIVS_PIN16_Msk (0x01 << PORT_PORTN_DRIVS_PIN16_Pos) +#define PORT_PORTN_DRIVS_PIN17_Pos 17 +#define PORT_PORTN_DRIVS_PIN17_Msk (0x01 << PORT_PORTN_DRIVS_PIN17_Pos) +#define PORT_PORTN_DRIVS_PIN18_Pos 18 +#define PORT_PORTN_DRIVS_PIN18_Msk (0x01 << PORT_PORTN_DRIVS_PIN18_Pos) +#define PORT_PORTN_DRIVS_PIN19_Pos 19 +#define PORT_PORTN_DRIVS_PIN19_Msk (0x01 << PORT_PORTN_DRIVS_PIN19_Pos) +#define PORT_PORTN_DRIVS_PIN20_Pos 20 +#define PORT_PORTN_DRIVS_PIN20_Msk (0x01 << PORT_PORTN_DRIVS_PIN20_Pos) +#define PORT_PORTN_DRIVS_PIN21_Pos 21 +#define PORT_PORTN_DRIVS_PIN21_Msk (0x01 << PORT_PORTN_DRIVS_PIN21_Pos) +#define PORT_PORTN_DRIVS_PIN22_Pos 22 +#define PORT_PORTN_DRIVS_PIN22_Msk (0x01 << PORT_PORTN_DRIVS_PIN22_Pos) +#define PORT_PORTN_DRIVS_PIN23_Pos 23 +#define PORT_PORTN_DRIVS_PIN23_Msk (0x01 << PORT_PORTN_DRIVS_PIN23_Pos) + +#define PORT_PORTP_DRIVS_PIN0_Pos 0 +#define PORT_PORTP_DRIVS_PIN0_Msk (0x01 << PORT_PORTP_DRIVS_PIN0_Pos) +#define PORT_PORTP_DRIVS_PIN1_Pos 1 +#define PORT_PORTP_DRIVS_PIN1_Msk (0x01 << PORT_PORTP_DRIVS_PIN1_Pos) +#define PORT_PORTP_DRIVS_PIN2_Pos 2 +#define PORT_PORTP_DRIVS_PIN2_Msk (0x01 << PORT_PORTP_DRIVS_PIN2_Pos) +#define PORT_PORTP_DRIVS_PIN3_Pos 3 +#define PORT_PORTP_DRIVS_PIN3_Msk (0x01 << PORT_PORTP_DRIVS_PIN3_Pos) +#define PORT_PORTP_DRIVS_PIN4_Pos 4 +#define PORT_PORTP_DRIVS_PIN4_Msk (0x01 << PORT_PORTP_DRIVS_PIN4_Pos) +#define PORT_PORTP_DRIVS_PIN5_Pos 5 +#define PORT_PORTP_DRIVS_PIN5_Msk (0x01 << PORT_PORTP_DRIVS_PIN5_Pos) +#define PORT_PORTP_DRIVS_PIN6_Pos 6 +#define PORT_PORTP_DRIVS_PIN6_Msk (0x01 << PORT_PORTP_DRIVS_PIN6_Pos) +#define PORT_PORTP_DRIVS_PIN7_Pos 7 +#define PORT_PORTP_DRIVS_PIN7_Msk (0x01 << PORT_PORTP_DRIVS_PIN7_Pos) +#define PORT_PORTP_DRIVS_PIN8_Pos 8 +#define PORT_PORTP_DRIVS_PIN8_Msk (0x01 << PORT_PORTP_DRIVS_PIN8_Pos) +#define PORT_PORTP_DRIVS_PIN9_Pos 9 +#define PORT_PORTP_DRIVS_PIN9_Msk (0x01 << PORT_PORTP_DRIVS_PIN9_Pos) +#define PORT_PORTP_DRIVS_PIN10_Pos 10 +#define PORT_PORTP_DRIVS_PIN10_Msk (0x01 << PORT_PORTP_DRIVS_PIN10_Pos) +#define PORT_PORTP_DRIVS_PIN11_Pos 11 +#define PORT_PORTP_DRIVS_PIN11_Msk (0x01 << PORT_PORTP_DRIVS_PIN11_Pos) +#define PORT_PORTP_DRIVS_PIN12_Pos 12 +#define PORT_PORTP_DRIVS_PIN12_Msk (0x01 << PORT_PORTP_DRIVS_PIN12_Pos) +#define PORT_PORTP_DRIVS_PIN13_Pos 13 +#define PORT_PORTP_DRIVS_PIN13_Msk (0x01 << PORT_PORTP_DRIVS_PIN13_Pos) +#define PORT_PORTP_DRIVS_PIN14_Pos 14 +#define PORT_PORTP_DRIVS_PIN14_Msk (0x01 << PORT_PORTP_DRIVS_PIN14_Pos) +#define PORT_PORTP_DRIVS_PIN15_Pos 15 +#define PORT_PORTP_DRIVS_PIN15_Msk (0x01 << PORT_PORTP_DRIVS_PIN15_Pos) +#define PORT_PORTP_DRIVS_PIN16_Pos 16 +#define PORT_PORTP_DRIVS_PIN16_Msk (0x01 << PORT_PORTP_DRIVS_PIN16_Pos) +#define PORT_PORTP_DRIVS_PIN17_Pos 17 +#define PORT_PORTP_DRIVS_PIN17_Msk (0x01 << PORT_PORTP_DRIVS_PIN17_Pos) +#define PORT_PORTP_DRIVS_PIN18_Pos 18 +#define PORT_PORTP_DRIVS_PIN18_Msk (0x01 << PORT_PORTP_DRIVS_PIN18_Pos) +#define PORT_PORTP_DRIVS_PIN19_Pos 19 +#define PORT_PORTP_DRIVS_PIN19_Msk (0x01 << PORT_PORTP_DRIVS_PIN19_Pos) +#define PORT_PORTP_DRIVS_PIN20_Pos 20 +#define PORT_PORTP_DRIVS_PIN20_Msk (0x01 << PORT_PORTP_DRIVS_PIN20_Pos) +#define PORT_PORTP_DRIVS_PIN21_Pos 21 +#define PORT_PORTP_DRIVS_PIN21_Msk (0x01 << PORT_PORTP_DRIVS_PIN21_Pos) +#define PORT_PORTP_DRIVS_PIN22_Pos 22 +#define PORT_PORTP_DRIVS_PIN22_Msk (0x01 << PORT_PORTP_DRIVS_PIN22_Pos) +#define PORT_PORTP_DRIVS_PIN23_Pos 23 +#define PORT_PORTP_DRIVS_PIN23_Msk (0x01 << PORT_PORTP_DRIVS_PIN23_Pos) + +#define PORT_PORTA_INEN_PIN0_Pos 0 +#define PORT_PORTA_INEN_PIN0_Msk (0x01 << PORT_PORTA_INEN_PIN0_Pos) +#define PORT_PORTA_INEN_PIN1_Pos 1 +#define PORT_PORTA_INEN_PIN1_Msk (0x01 << PORT_PORTA_INEN_PIN1_Pos) +#define PORT_PORTA_INEN_PIN2_Pos 2 +#define PORT_PORTA_INEN_PIN2_Msk (0x01 << PORT_PORTA_INEN_PIN2_Pos) +#define PORT_PORTA_INEN_PIN3_Pos 3 +#define PORT_PORTA_INEN_PIN3_Msk (0x01 << PORT_PORTA_INEN_PIN3_Pos) +#define PORT_PORTA_INEN_PIN4_Pos 4 +#define PORT_PORTA_INEN_PIN4_Msk (0x01 << PORT_PORTA_INEN_PIN4_Pos) +#define PORT_PORTA_INEN_PIN5_Pos 5 +#define PORT_PORTA_INEN_PIN5_Msk (0x01 << PORT_PORTA_INEN_PIN5_Pos) +#define PORT_PORTA_INEN_PIN6_Pos 6 +#define PORT_PORTA_INEN_PIN6_Msk (0x01 << PORT_PORTA_INEN_PIN6_Pos) +#define PORT_PORTA_INEN_PIN7_Pos 7 +#define PORT_PORTA_INEN_PIN7_Msk (0x01 << PORT_PORTA_INEN_PIN7_Pos) +#define PORT_PORTA_INEN_PIN8_Pos 8 +#define PORT_PORTA_INEN_PIN8_Msk (0x01 << PORT_PORTA_INEN_PIN8_Pos) +#define PORT_PORTA_INEN_PIN9_Pos 9 +#define PORT_PORTA_INEN_PIN9_Msk (0x01 << PORT_PORTA_INEN_PIN9_Pos) +#define PORT_PORTA_INEN_PIN10_Pos 10 +#define PORT_PORTA_INEN_PIN10_Msk (0x01 << PORT_PORTA_INEN_PIN10_Pos) +#define PORT_PORTA_INEN_PIN11_Pos 11 +#define PORT_PORTA_INEN_PIN11_Msk (0x01 << PORT_PORTA_INEN_PIN11_Pos) +#define PORT_PORTA_INEN_PIN12_Pos 12 +#define PORT_PORTA_INEN_PIN12_Msk (0x01 << PORT_PORTA_INEN_PIN12_Pos) +#define PORT_PORTA_INEN_PIN13_Pos 13 +#define PORT_PORTA_INEN_PIN13_Msk (0x01 << PORT_PORTA_INEN_PIN13_Pos) +#define PORT_PORTA_INEN_PIN14_Pos 14 +#define PORT_PORTA_INEN_PIN14_Msk (0x01 << PORT_PORTA_INEN_PIN14_Pos) +#define PORT_PORTA_INEN_PIN15_Pos 15 +#define PORT_PORTA_INEN_PIN15_Msk (0x01 << PORT_PORTA_INEN_PIN15_Pos) + +#define PORT_PORTB_INEN_PIN0_Pos 0 +#define PORT_PORTB_INEN_PIN0_Msk (0x01 << PORT_PORTB_INEN_PIN0_Pos) +#define PORT_PORTB_INEN_PIN1_Pos 1 +#define PORT_PORTB_INEN_PIN1_Msk (0x01 << PORT_PORTB_INEN_PIN1_Pos) +#define PORT_PORTB_INEN_PIN2_Pos 2 +#define PORT_PORTB_INEN_PIN2_Msk (0x01 << PORT_PORTB_INEN_PIN2_Pos) +#define PORT_PORTB_INEN_PIN3_Pos 3 +#define PORT_PORTB_INEN_PIN3_Msk (0x01 << PORT_PORTB_INEN_PIN3_Pos) +#define PORT_PORTB_INEN_PIN4_Pos 4 +#define PORT_PORTB_INEN_PIN4_Msk (0x01 << PORT_PORTB_INEN_PIN4_Pos) +#define PORT_PORTB_INEN_PIN5_Pos 5 +#define PORT_PORTB_INEN_PIN5_Msk (0x01 << PORT_PORTB_INEN_PIN5_Pos) +#define PORT_PORTB_INEN_PIN6_Pos 6 +#define PORT_PORTB_INEN_PIN6_Msk (0x01 << PORT_PORTB_INEN_PIN6_Pos) +#define PORT_PORTB_INEN_PIN7_Pos 7 +#define PORT_PORTB_INEN_PIN7_Msk (0x01 << PORT_PORTB_INEN_PIN7_Pos) +#define PORT_PORTB_INEN_PIN8_Pos 8 +#define PORT_PORTB_INEN_PIN8_Msk (0x01 << PORT_PORTB_INEN_PIN8_Pos) +#define PORT_PORTB_INEN_PIN9_Pos 9 +#define PORT_PORTB_INEN_PIN9_Msk (0x01 << PORT_PORTB_INEN_PIN9_Pos) +#define PORT_PORTB_INEN_PIN10_Pos 10 +#define PORT_PORTB_INEN_PIN10_Msk (0x01 << PORT_PORTB_INEN_PIN10_Pos) +#define PORT_PORTB_INEN_PIN11_Pos 11 +#define PORT_PORTB_INEN_PIN11_Msk (0x01 << PORT_PORTB_INEN_PIN11_Pos) +#define PORT_PORTB_INEN_PIN12_Pos 12 +#define PORT_PORTB_INEN_PIN12_Msk (0x01 << PORT_PORTB_INEN_PIN12_Pos) +#define PORT_PORTB_INEN_PIN13_Pos 13 +#define PORT_PORTB_INEN_PIN13_Msk (0x01 << PORT_PORTB_INEN_PIN13_Pos) +#define PORT_PORTB_INEN_PIN14_Pos 14 +#define PORT_PORTB_INEN_PIN14_Msk (0x01 << PORT_PORTB_INEN_PIN14_Pos) +#define PORT_PORTB_INEN_PIN15_Pos 15 +#define PORT_PORTB_INEN_PIN15_Msk (0x01 << PORT_PORTB_INEN_PIN15_Pos) + +#define PORT_PORTC_INEN_PIN0_Pos 0 +#define PORT_PORTC_INEN_PIN0_Msk (0x01 << PORT_PORTC_INEN_PIN0_Pos) +#define PORT_PORTC_INEN_PIN1_Pos 1 +#define PORT_PORTC_INEN_PIN1_Msk (0x01 << PORT_PORTC_INEN_PIN1_Pos) +#define PORT_PORTC_INEN_PIN2_Pos 2 +#define PORT_PORTC_INEN_PIN2_Msk (0x01 << PORT_PORTC_INEN_PIN2_Pos) +#define PORT_PORTC_INEN_PIN3_Pos 3 +#define PORT_PORTC_INEN_PIN3_Msk (0x01 << PORT_PORTC_INEN_PIN3_Pos) +#define PORT_PORTC_INEN_PIN4_Pos 4 +#define PORT_PORTC_INEN_PIN4_Msk (0x01 << PORT_PORTC_INEN_PIN4_Pos) +#define PORT_PORTC_INEN_PIN5_Pos 5 +#define PORT_PORTC_INEN_PIN5_Msk (0x01 << PORT_PORTC_INEN_PIN5_Pos) +#define PORT_PORTC_INEN_PIN6_Pos 6 +#define PORT_PORTC_INEN_PIN6_Msk (0x01 << PORT_PORTC_INEN_PIN6_Pos) +#define PORT_PORTC_INEN_PIN7_Pos 7 +#define PORT_PORTC_INEN_PIN7_Msk (0x01 << PORT_PORTC_INEN_PIN7_Pos) +#define PORT_PORTC_INEN_PIN8_Pos 8 +#define PORT_PORTC_INEN_PIN8_Msk (0x01 << PORT_PORTC_INEN_PIN8_Pos) +#define PORT_PORTC_INEN_PIN9_Pos 9 +#define PORT_PORTC_INEN_PIN9_Msk (0x01 << PORT_PORTC_INEN_PIN9_Pos) +#define PORT_PORTC_INEN_PIN10_Pos 10 +#define PORT_PORTC_INEN_PIN10_Msk (0x01 << PORT_PORTC_INEN_PIN10_Pos) +#define PORT_PORTC_INEN_PIN11_Pos 11 +#define PORT_PORTC_INEN_PIN11_Msk (0x01 << PORT_PORTC_INEN_PIN11_Pos) +#define PORT_PORTC_INEN_PIN12_Pos 12 +#define PORT_PORTC_INEN_PIN12_Msk (0x01 << PORT_PORTC_INEN_PIN12_Pos) +#define PORT_PORTC_INEN_PIN13_Pos 13 +#define PORT_PORTC_INEN_PIN13_Msk (0x01 << PORT_PORTC_INEN_PIN13_Pos) +#define PORT_PORTC_INEN_PIN14_Pos 14 +#define PORT_PORTC_INEN_PIN14_Msk (0x01 << PORT_PORTC_INEN_PIN14_Pos) +#define PORT_PORTC_INEN_PIN15_Pos 15 +#define PORT_PORTC_INEN_PIN15_Msk (0x01 << PORT_PORTC_INEN_PIN15_Pos) + +#define PORT_PORTM_INEN_PIN0_Pos 0 +#define PORT_PORTM_INEN_PIN0_Msk (0x01 << PORT_PORTM_INEN_PIN0_Pos) +#define PORT_PORTM_INEN_PIN1_Pos 1 +#define PORT_PORTM_INEN_PIN1_Msk (0x01 << PORT_PORTM_INEN_PIN1_Pos) +#define PORT_PORTM_INEN_PIN2_Pos 2 +#define PORT_PORTM_INEN_PIN2_Msk (0x01 << PORT_PORTM_INEN_PIN2_Pos) +#define PORT_PORTM_INEN_PIN3_Pos 3 +#define PORT_PORTM_INEN_PIN3_Msk (0x01 << PORT_PORTM_INEN_PIN3_Pos) +#define PORT_PORTM_INEN_PIN4_Pos 4 +#define PORT_PORTM_INEN_PIN4_Msk (0x01 << PORT_PORTM_INEN_PIN4_Pos) +#define PORT_PORTM_INEN_PIN5_Pos 5 +#define PORT_PORTM_INEN_PIN5_Msk (0x01 << PORT_PORTM_INEN_PIN5_Pos) +#define PORT_PORTM_INEN_PIN6_Pos 6 +#define PORT_PORTM_INEN_PIN6_Msk (0x01 << PORT_PORTM_INEN_PIN6_Pos) +#define PORT_PORTM_INEN_PIN7_Pos 7 +#define PORT_PORTM_INEN_PIN7_Msk (0x01 << PORT_PORTM_INEN_PIN7_Pos) +#define PORT_PORTM_INEN_PIN8_Pos 8 +#define PORT_PORTM_INEN_PIN8_Msk (0x01 << PORT_PORTM_INEN_PIN8_Pos) +#define PORT_PORTM_INEN_PIN9_Pos 9 +#define PORT_PORTM_INEN_PIN9_Msk (0x01 << PORT_PORTM_INEN_PIN9_Pos) +#define PORT_PORTM_INEN_PIN10_Pos 10 +#define PORT_PORTM_INEN_PIN10_Msk (0x01 << PORT_PORTM_INEN_PIN10_Pos) +#define PORT_PORTM_INEN_PIN11_Pos 11 +#define PORT_PORTM_INEN_PIN11_Msk (0x01 << PORT_PORTM_INEN_PIN11_Pos) +#define PORT_PORTM_INEN_PIN12_Pos 12 +#define PORT_PORTM_INEN_PIN12_Msk (0x01 << PORT_PORTM_INEN_PIN12_Pos) +#define PORT_PORTM_INEN_PIN13_Pos 13 +#define PORT_PORTM_INEN_PIN13_Msk (0x01 << PORT_PORTM_INEN_PIN13_Pos) +#define PORT_PORTM_INEN_PIN14_Pos 14 +#define PORT_PORTM_INEN_PIN14_Msk (0x01 << PORT_PORTM_INEN_PIN14_Pos) +#define PORT_PORTM_INEN_PIN15_Pos 15 +#define PORT_PORTM_INEN_PIN15_Msk (0x01 << PORT_PORTM_INEN_PIN15_Pos) +#define PORT_PORTM_INEN_PIN16_Pos 16 +#define PORT_PORTM_INEN_PIN16_Msk (0x01 << PORT_PORTM_INEN_PIN16_Pos) +#define PORT_PORTM_INEN_PIN17_Pos 17 +#define PORT_PORTM_INEN_PIN17_Msk (0x01 << PORT_PORTM_INEN_PIN17_Pos) +#define PORT_PORTM_INEN_PIN18_Pos 18 +#define PORT_PORTM_INEN_PIN18_Msk (0x01 << PORT_PORTM_INEN_PIN18_Pos) +#define PORT_PORTM_INEN_PIN19_Pos 19 +#define PORT_PORTM_INEN_PIN19_Msk (0x01 << PORT_PORTM_INEN_PIN19_Pos) +#define PORT_PORTM_INEN_PIN20_Pos 20 +#define PORT_PORTM_INEN_PIN20_Msk (0x01 << PORT_PORTM_INEN_PIN20_Pos) +#define PORT_PORTM_INEN_PIN21_Pos 21 +#define PORT_PORTM_INEN_PIN21_Msk (0x01 << PORT_PORTM_INEN_PIN21_Pos) +#define PORT_PORTM_INEN_PIN22_Pos 22 +#define PORT_PORTM_INEN_PIN22_Msk (0x01 << PORT_PORTM_INEN_PIN22_Pos) +#define PORT_PORTM_INEN_PIN23_Pos 23 +#define PORT_PORTM_INEN_PIN23_Msk (0x01 << PORT_PORTM_INEN_PIN23_Pos) + +#define PORT_PORTN_INEN_PIN0_Pos 0 +#define PORT_PORTN_INEN_PIN0_Msk (0x01 << PORT_PORTN_INEN_PIN0_Pos) +#define PORT_PORTN_INEN_PIN1_Pos 1 +#define PORT_PORTN_INEN_PIN1_Msk (0x01 << PORT_PORTN_INEN_PIN1_Pos) +#define PORT_PORTN_INEN_PIN2_Pos 2 +#define PORT_PORTN_INEN_PIN2_Msk (0x01 << PORT_PORTN_INEN_PIN2_Pos) +#define PORT_PORTN_INEN_PIN3_Pos 3 +#define PORT_PORTN_INEN_PIN3_Msk (0x01 << PORT_PORTN_INEN_PIN3_Pos) +#define PORT_PORTN_INEN_PIN4_Pos 4 +#define PORT_PORTN_INEN_PIN4_Msk (0x01 << PORT_PORTN_INEN_PIN4_Pos) +#define PORT_PORTN_INEN_PIN5_Pos 5 +#define PORT_PORTN_INEN_PIN5_Msk (0x01 << PORT_PORTN_INEN_PIN5_Pos) +#define PORT_PORTN_INEN_PIN6_Pos 6 +#define PORT_PORTN_INEN_PIN6_Msk (0x01 << PORT_PORTN_INEN_PIN6_Pos) +#define PORT_PORTN_INEN_PIN7_Pos 7 +#define PORT_PORTN_INEN_PIN7_Msk (0x01 << PORT_PORTN_INEN_PIN7_Pos) +#define PORT_PORTN_INEN_PIN8_Pos 8 +#define PORT_PORTN_INEN_PIN8_Msk (0x01 << PORT_PORTN_INEN_PIN8_Pos) +#define PORT_PORTN_INEN_PIN9_Pos 9 +#define PORT_PORTN_INEN_PIN9_Msk (0x01 << PORT_PORTN_INEN_PIN9_Pos) +#define PORT_PORTN_INEN_PIN10_Pos 10 +#define PORT_PORTN_INEN_PIN10_Msk (0x01 << PORT_PORTN_INEN_PIN10_Pos) +#define PORT_PORTN_INEN_PIN11_Pos 11 +#define PORT_PORTN_INEN_PIN11_Msk (0x01 << PORT_PORTN_INEN_PIN11_Pos) +#define PORT_PORTN_INEN_PIN12_Pos 12 +#define PORT_PORTN_INEN_PIN12_Msk (0x01 << PORT_PORTN_INEN_PIN12_Pos) +#define PORT_PORTN_INEN_PIN13_Pos 13 +#define PORT_PORTN_INEN_PIN13_Msk (0x01 << PORT_PORTN_INEN_PIN13_Pos) +#define PORT_PORTN_INEN_PIN14_Pos 14 +#define PORT_PORTN_INEN_PIN14_Msk (0x01 << PORT_PORTN_INEN_PIN14_Pos) +#define PORT_PORTN_INEN_PIN15_Pos 15 +#define PORT_PORTN_INEN_PIN15_Msk (0x01 << PORT_PORTN_INEN_PIN15_Pos) +#define PORT_PORTN_INEN_PIN16_Pos 16 +#define PORT_PORTN_INEN_PIN16_Msk (0x01 << PORT_PORTN_INEN_PIN16_Pos) +#define PORT_PORTN_INEN_PIN17_Pos 17 +#define PORT_PORTN_INEN_PIN17_Msk (0x01 << PORT_PORTN_INEN_PIN17_Pos) +#define PORT_PORTN_INEN_PIN18_Pos 18 +#define PORT_PORTN_INEN_PIN18_Msk (0x01 << PORT_PORTN_INEN_PIN18_Pos) +#define PORT_PORTN_INEN_PIN19_Pos 19 +#define PORT_PORTN_INEN_PIN19_Msk (0x01 << PORT_PORTN_INEN_PIN19_Pos) +#define PORT_PORTN_INEN_PIN20_Pos 20 +#define PORT_PORTN_INEN_PIN20_Msk (0x01 << PORT_PORTN_INEN_PIN20_Pos) +#define PORT_PORTN_INEN_PIN21_Pos 21 +#define PORT_PORTN_INEN_PIN21_Msk (0x01 << PORT_PORTN_INEN_PIN21_Pos) +#define PORT_PORTN_INEN_PIN22_Pos 22 +#define PORT_PORTN_INEN_PIN22_Msk (0x01 << PORT_PORTN_INEN_PIN22_Pos) +#define PORT_PORTN_INEN_PIN23_Pos 23 +#define PORT_PORTN_INEN_PIN23_Msk (0x01 << PORT_PORTN_INEN_PIN23_Pos) + +#define PORT_PORTP_INEN_PIN0_Pos 0 +#define PORT_PORTP_INEN_PIN0_Msk (0x01 << PORT_PORTP_INEN_PIN0_Pos) +#define PORT_PORTP_INEN_PIN1_Pos 1 +#define PORT_PORTP_INEN_PIN1_Msk (0x01 << PORT_PORTP_INEN_PIN1_Pos) +#define PORT_PORTP_INEN_PIN2_Pos 2 +#define PORT_PORTP_INEN_PIN2_Msk (0x01 << PORT_PORTP_INEN_PIN2_Pos) +#define PORT_PORTP_INEN_PIN3_Pos 3 +#define PORT_PORTP_INEN_PIN3_Msk (0x01 << PORT_PORTP_INEN_PIN3_Pos) +#define PORT_PORTP_INEN_PIN4_Pos 4 +#define PORT_PORTP_INEN_PIN4_Msk (0x01 << PORT_PORTP_INEN_PIN4_Pos) +#define PORT_PORTP_INEN_PIN5_Pos 5 +#define PORT_PORTP_INEN_PIN5_Msk (0x01 << PORT_PORTP_INEN_PIN5_Pos) +#define PORT_PORTP_INEN_PIN6_Pos 6 +#define PORT_PORTP_INEN_PIN6_Msk (0x01 << PORT_PORTP_INEN_PIN6_Pos) +#define PORT_PORTP_INEN_PIN7_Pos 7 +#define PORT_PORTP_INEN_PIN7_Msk (0x01 << PORT_PORTP_INEN_PIN7_Pos) +#define PORT_PORTP_INEN_PIN8_Pos 8 +#define PORT_PORTP_INEN_PIN8_Msk (0x01 << PORT_PORTP_INEN_PIN8_Pos) +#define PORT_PORTP_INEN_PIN9_Pos 9 +#define PORT_PORTP_INEN_PIN9_Msk (0x01 << PORT_PORTP_INEN_PIN9_Pos) +#define PORT_PORTP_INEN_PIN10_Pos 10 +#define PORT_PORTP_INEN_PIN10_Msk (0x01 << PORT_PORTP_INEN_PIN10_Pos) +#define PORT_PORTP_INEN_PIN11_Pos 11 +#define PORT_PORTP_INEN_PIN11_Msk (0x01 << PORT_PORTP_INEN_PIN11_Pos) +#define PORT_PORTP_INEN_PIN12_Pos 12 +#define PORT_PORTP_INEN_PIN12_Msk (0x01 << PORT_PORTP_INEN_PIN12_Pos) +#define PORT_PORTP_INEN_PIN13_Pos 13 +#define PORT_PORTP_INEN_PIN13_Msk (0x01 << PORT_PORTP_INEN_PIN13_Pos) +#define PORT_PORTP_INEN_PIN14_Pos 14 +#define PORT_PORTP_INEN_PIN14_Msk (0x01 << PORT_PORTP_INEN_PIN14_Pos) +#define PORT_PORTP_INEN_PIN15_Pos 15 +#define PORT_PORTP_INEN_PIN15_Msk (0x01 << PORT_PORTP_INEN_PIN15_Pos) +#define PORT_PORTP_INEN_PIN16_Pos 16 +#define PORT_PORTP_INEN_PIN16_Msk (0x01 << PORT_PORTP_INEN_PIN16_Pos) +#define PORT_PORTP_INEN_PIN17_Pos 17 +#define PORT_PORTP_INEN_PIN17_Msk (0x01 << PORT_PORTP_INEN_PIN17_Pos) +#define PORT_PORTP_INEN_PIN18_Pos 18 +#define PORT_PORTP_INEN_PIN18_Msk (0x01 << PORT_PORTP_INEN_PIN18_Pos) +#define PORT_PORTP_INEN_PIN19_Pos 19 +#define PORT_PORTP_INEN_PIN19_Msk (0x01 << PORT_PORTP_INEN_PIN19_Pos) +#define PORT_PORTP_INEN_PIN20_Pos 20 +#define PORT_PORTP_INEN_PIN20_Msk (0x01 << PORT_PORTP_INEN_PIN20_Pos) +#define PORT_PORTP_INEN_PIN21_Pos 21 +#define PORT_PORTP_INEN_PIN21_Msk (0x01 << PORT_PORTP_INEN_PIN21_Pos) +#define PORT_PORTP_INEN_PIN22_Pos 22 +#define PORT_PORTP_INEN_PIN22_Msk (0x01 << PORT_PORTP_INEN_PIN22_Pos) +#define PORT_PORTP_INEN_PIN23_Pos 23 +#define PORT_PORTP_INEN_PIN23_Msk (0x01 << PORT_PORTP_INEN_PIN23_Pos) + typedef struct { __IO uint32_t DATA; @@ -558,44 +1165,44 @@ typedef struct #define PIN23 23 #define PIN24 24 - __IO uint32_t DIR; //0 闁跨喐鏋婚幏鐑芥晸閺傘倖瀚� 1 闁跨喐鏋婚幏鐑芥晸閿燂拷 + __IO uint32_t DIR; //0 输入 1 输出 - __IO uint32_t INTLVLTRG; //Interrupt Level Trigger 1 闁跨喐鏋婚幏宄伴挬闁跨喐鏋婚幏鐑芥晸閺傘倖瀚归柨鐔峰建鐠佽瀚� 0 闁跨喐鏋婚幏鐑芥晸閹搭亣鎻幏鐑芥晸閺傘倖瀚归柨鐔峰建鐠佽瀚� + __IO uint32_t INTLVLTRG; //Interrupt Level Trigger 1 电平触发中断 0 边沿触发中断 - __IO uint32_t INTBE; //Both Edge闁跨喐鏋婚幏鐑芥晸閺傘倖瀚笽NTLVLTRG闁跨喐鏋婚幏铚傝礋闁跨喐鏋婚幏鐑芥晸閹搭亣鎻幏鐑芥晸閺傘倖瀚归柨鐔峰建鐠佽瀚归弮鍫曟晸閺傘倖瀚归柨鐔告灮閹疯渹缍呴柨鐔告灮閹凤拷1闁跨喐鏋婚幏椋庛仛闁跨喐鏋婚幏鐑芥晸閺傘倖瀚归柨鐔稿焻閻氬瓨瀚归柨鐔兼應閺傘倖瀚归柨鐔稿焻鐠佽瀚归柨鐔告灮閹风兘鏁撻弬銈嗗闁跨喎褰ㄩ弬顓ㄧ秶閹风兘鏁撻弬銈嗗0閺冨爼鏁撻弬銈嗗闁跨喐鏋婚幏鐑芥晸閺傘倖瀚归柨鐔告灮閹风兘鏁撻弬銈嗗INTRISEEN闁鏁撻弬銈嗗 + __IO uint32_t INTBE; //Both Edge，当INTLVLTRG设为边沿触发中断时，此位置1表示上升沿和下降沿都触发中断，置0时触发边沿由INTRISEEN选择 - __IO uint32_t INTRISEEN; //Interrupt Rise Edge Enable 1 闁跨喐鏋婚幏鐑芥晸閺傘倖瀚归柨鐔告灮閹凤拷/闁跨喓顏喊澶嬪楠炴娊鏁撻弬銈嗗闁跨喐鏋婚幏鐑芥晸閸欘偉顔愰幏锟� 0 闁跨喖鎽弬銈嗗闁跨喐鏋婚幏锟�/闁跨喖鍙虹喊澶嬪楠炴娊鏁撻弬銈嗗闁跨喐鏋婚幏鐑芥晸閸欘偉顔愰幏锟� + __IO uint32_t INTRISEEN; //Interrupt Rise Edge Enable 1 上升沿/高电平触发中断 0 下降沿/低电平触发中断 - __IO uint32_t INTEN; //1 闁跨喎褰ㄧ拋瑙勫娴ｅ潡鏁撻弬銈嗗 0 闁跨喎褰ㄩ弬顓熸灮閹烽攱顒� + __IO uint32_t INTEN; //1 中断使能 0 中断禁止 - __IO uint32_t INTRAWSTAT; //闁跨喎褰ㄩ弬顓犮€嬮幏椋庡禃閵夋棏浜烽幏閿嬬懞闁跨喐鏋婚幏椋庡禃閺傘倖瀚归懜婊堟晸閺傘倖瀚归柨鐔告灮閹峰嘲宓忕化濠氭晸閺傘倖瀚归柨鐔告灮閹风兘鏁撻敓锟� 1 闁跨喐鏋婚幏椋庡禃閺傘倖瀚归柨鐔告灮閹峰嘲宓忓ú妤呮晸閺傘倖瀚归柨鐔告灮閹风兘鏁撻弬銈嗗闁跨噦鎷� 0 濞岋繝鏁撻崣顐ゃ€嬮幏椋庡禃閺傘倖瀚归崡鍛婄闁跨喐鏋婚幏鐑芥晸閺傘倖瀚归柨鐔告灮閹风兘鏁撻敓锟� + __IO uint32_t INTRAWSTAT; //中断检测单元是否检测到了触发中断的条件 1 检测到了中断触发条件 0 没有检测到中断触发条件 __IO uint32_t INTSTAT; //INTSTAT.PIN0 = INTRAWSTAT.PIN0 & INTEN.PIN0 - __IO uint32_t INTCLR; //閸愶拷1闁跨喐鏋婚幏鐑芥晸閺傘倖瀚归崡绋款€掗柨鐔活敎閹惧懏瀚归柨鐔活敎娴兼瑦瀚归崨姗€鏁撻弬銈嗗閸楊噣鏁撻弬銈嗗闁跨喐鏋婚幏宄板祻闁跨喐鏋婚幏鐑芥晸閺傘倖瀚归柨鐕傛嫹 + __IO uint32_t INTCLR; //写1清除中断标志，只对边沿触发中断有用 } GPIO_TypeDef; typedef struct { - __IO uint32_t LDVAL; //闁跨喐鏋婚幏閿嬫闁跨喐鏋婚幏鐑芥晸閺傘倖瀚归柨鐔告灮閹峰嘲鈧ジ鏁撻弬銈嗗娴ｅ潡鏁撻弶鎵皑閹烽攱妞傞柨鐔告灮閹风兘鏁撻幒銉ㄦ彧閹风兘鏁撻弬銈嗗閸婂ジ鏁撻弬銈嗗婵鏁撻弬銈嗗闁跨喖鎽柅鎺斻€嬮幏鐑芥晸閺傘倖瀚归柨鐔告灮閹凤拷 + __IO uint32_t LDVAL; //定时器加载值，使能后定时器从此数值开始向下递减计数 - __I uint32_t CVAL; //闁跨喐鏋婚幏閿嬫闁跨喐鏋婚幏鐑芥晸閺傘倖瀚归崜宥呪偓濂告晸閺傘倖瀚筁DVAL-CVAL 闁跨喓鍗崇涵閿嬪闁跨喐鏋婚幏鐑芥晸閺傘倖瀚归柨鐔虹哺缁楁梹鍞婚幏鐑芥晸閿燂拷 + __I uint32_t CVAL; //定时器当前值，LDVAL-CVAL 可计算出计时时长 __IO uint32_t CTRL; } TIMR_TypeDef; -#define TIMR_CTRL_EN_Pos 0 //闁跨喐鏋婚幏铚傜秴闁跨喐鏋婚幏锟�1闁跨喐鏋婚幏鐑芥晸閺傘倖瀚筎IMR闁跨喐鏋婚幏绋珼VAL闁跨喐鏋婚幏宄邦潗闁跨喐鏋婚幏鐑芥晸闁句即鈧帞銆嬮幏鐑芥晸閺傘倖瀚归柨鐔告灮閹凤拷 +#define TIMR_CTRL_EN_Pos 0 //此位赋1导致TIMR从LDVAL开始向下递减计数 #define TIMR_CTRL_EN_Msk (0x01 << TIMR_CTRL_EN_Pos) -#define TIMR_CTRL_CLKSRC_Pos 1 //閺冨爼鏁撻弬銈嗗濠ф劙鏁撻弬銈嗗0 闁跨喕濡拠褎瀚圭化鑽ょ埠閺冨爼鏁撻弬銈嗗 1 闁跨喕袙闁劑鏁撻弬銈嗗闁跨喐鏋婚幏鐑芥晸閺傘倖瀚归柨鐔告灮閹风兘鏁撻弬銈嗗闁跨噦鎷� +#define TIMR_CTRL_CLKSRC_Pos 1 //时钟源：0 内部系统时钟 1 外部引脚脉冲计数 #define TIMR_CTRL_CLKSRC_Msk (0x01 << TIMR_CTRL_CLKSRC_Pos) -#define TIMR_CTRL_CASCADE_Pos 2 //1 TIMRx闁跨喍鑼庣涵閿嬪闁跨喐鏋婚幏閿嬫闁跨喐鏋婚幏铚傝礋TIMRx-1闁跨喐鏋婚幏鐑芥晸閺傘倖瀚归柨鐔告灮閹风柉妫旈柨鐕傛嫹 +#define TIMR_CTRL_CASCADE_Pos 2 //1 TIMRx的计数时钟为TIMRx-1的溢出信号 #define TIMR_CTRL_CASCADE_Msk (0x01 << TIMR_CTRL_CASCADE_Pos) typedef struct { - __IO uint32_t PCTRL; //Pulse Control闁跨喐鏋婚幏鐑芥晸閺傘倖瀚归柨鐔告灮閹风兘鏁撻弬銈嗗闁跨喍鑼庨敐蹇斿闁跨喐鏋婚幏鐑芥晸閻欌€崇槑鏉堢偓瀚归柨鐔告灮閹凤拷 + __IO uint32_t PCTRL; //Pulse Control，脉宽测量模块控制寄存器 - __I uint32_t PCVAL; //闁跨喐鏋婚幏鐑芥晸閺傘倖瀚归柨鐔告灮閹风兘鏁撻弬銈嗗闁跨喓绮搁幉瀣闁跨喐鏋婚幏鐑芥晸鐟欐帞鍩滈敓锟� + __I uint32_t PCVAL; //脉宽测量定时器当前值 uint32_t RESERVED[2]; @@ -606,11 +1213,11 @@ typedef struct __IO uint32_t HALT; } TIMRG_TypeDef; -#define TIMRG_PCTRL_EN_Pos 0 //闁跨喐鏋婚幏宄邦潗闁跨喐鏋婚幏鐑芥晸閺傘倖瀚归柨鐔告灮閹风兘鏁撻弬銈嗗闁跨喐鏋婚幏鐑芥晸閺傘倖瀚归柨鐔告灮閹凤拷32娴ｅ秹鏁撻弬銈嗗闁跨喐鏋婚幏鐑芥晸閺傘倖瀚归柨鐔告灮閹凤拷0闁跨喐鏋婚幏宄邦潗闁跨喐鏋婚幏鐑芥晸鏉堝啰銆嬮幏鐑芥晸閺傘倖瀚� +#define TIMRG_PCTRL_EN_Pos 0 //开始测量脉宽，脉宽内32位计数器从0开始向上计数 #define TIMRG_PCTRL_EN_Msk (0x01 << TIMRG_PCTRL_EN_Pos) -#define TIMRG_PCTRL_HIGH_Pos 1 //0 闁跨喐鏋婚幏鐑芥晸閺傘倖瀚归柨鐔煎徍绾板瀚归獮鎶芥晸閺傘倖瀚归柨鐔告灮閹凤拷 1 闁跨喐鏋婚幏鐑芥晸閺傘倖瀚归柨鐔侯仾绾板瀚归獮鎶芥晸閺傘倖瀚归柨鐔告灮閹凤拷 +#define TIMRG_PCTRL_HIGH_Pos 1 //0 测量低电平长度 1 测量高电平长度 #define TIMRG_PCTRL_HIGH_Msk (0x01 << TIMRG_PCTRL_HIGH_Pos) -#define TIMRG_PCTRL_CLKSRC_Pos 2 //閺冨爼鏁撻弬銈嗗濠ф劙鏁撻弬銈嗗0 闁跨喕濡拠褎瀚圭化鑽ょ埠閺冨爼鏁撻弬銈嗗 1 闁跨喐鏋婚幏鐑芥晸閺傘倖瀚归柨鐔告灮閹风兘鏁撴笟銉秶閹风兘鏁撻弬銈嗗闁跨喐褰导娆愬闁跨喐鏋婚幏鐑芥晸閺傘倖瀚归柨鐔告灮閹风兘鏁撻弬銈嗗闁跨喐鏋婚幏鐑芥晸閺傘倖瀚归崐顒勬晸閺傘倖瀚归柨鐔告灮閹风兘鏁撻弬銈嗗闁跨喐鏋婚幏鐑芥晸閺傘倖瀚归柨鐔告灮閹风兘鏁撻弬銈嗗 +#define TIMRG_PCTRL_CLKSRC_Pos 2 //时钟源：0 内部系统时钟 1 脉宽测量模块变成一个计数器，不再具有脉宽测量功能 #define TIMRG_PCTRL_CLKSRC_Msk (0x01 << TIMRG_PCTRL_CLKSRC_Pos) #define TIMRG_IE_TIMR0_Pos 0 @@ -628,7 +1235,7 @@ typedef struct #define TIMRG_IE_PULSE_Pos 16 #define TIMRG_IE_PULSE_Msk (0x01 << TIMRG_IE_PULSE_Pos) -#define TIMRG_IF_TIMR0_Pos 0 //閸愶拷1闁跨喐鏋婚幏鐑芥晸閺傘倖瀚� +#define TIMRG_IF_TIMR0_Pos 0 //写1清零 #define TIMRG_IF_TIMR0_Msk (0x01 << TIMRG_IF_TIMR0_Pos) #define TIMRG_IF_TIMR1_Pos 1 #define TIMRG_IF_TIMR1_Msk (0x01 << TIMRG_IF_TIMR1_Pos) @@ -643,7 +1250,7 @@ typedef struct #define TIMRG_IF_PULSE_Pos 16 #define TIMRG_IF_PULSE_Msk (0x01 << TIMRG_IF_PULSE_Pos) -#define TIMRG_HALT_TIMR0_Pos 0 //1 闁跨喐鏋婚幏宄颁粻闁跨喐鏋婚幏鐑芥晸閺傘倖瀚� +#define TIMRG_HALT_TIMR0_Pos 0 //1 暂停计数 #define TIMRG_HALT_TIMR0_Msk (0x01 << TIMRG_HALT_TIMR0_Pos) #define TIMRG_HALT_TIMR1_Pos 1 #define TIMRG_HALT_TIMR1_Msk (0x01 << TIMRG_HALT_TIMR1_Pos) @@ -678,116 +1285,114 @@ typedef struct #define UART_DATA_DATA_Pos 0 #define UART_DATA_DATA_Msk (0x1FF << UART_DATA_DATA_Pos) -#define UART_DATA_VALID_Pos 9 //闁跨喐鏋婚幏绋TA闁跨喕顢滅拋瑙勫闁跨喐鏋婚幏鐑芥晸閺傘倖瀚归弫鍫ユ晸娓氥儲鏋婚幏鐑芥晸閺傘倖瀚归柨鐔告灮閹风兘鏁撻弬銈嗗閺冨爼鏁撻弬銈嗗闁跨喐鏋婚幏铚傜秴绾剟鏁撻弬銈嗗闁跨喐鏋婚幏锟�1闁跨喐鏋婚幏鐑芥晸閺傘倖瀚归崣鏍晸閺傘倖瀚归柨鐔稿祹閻氬瓨瀚归柨鐔烘畷鐠佽瀚归柨鐔告灮閹风兘鏁撻弬銈嗗 +#define UART_DATA_VALID_Pos 9 //当DATA字段有有效的接收数据时，该位硬件置1，读取数据后自动清零 #define UART_DATA_VALID_Msk (0x01 << UART_DATA_VALID_Pos) #define UART_DATA_PAERR_Pos 10 //Parity Error #define UART_DATA_PAERR_Msk (0x01 << UART_DATA_PAERR_Pos) -#define UART_CTRL_TXIDLE_Pos 0 //TX IDLE: 0 闁跨喐鏋婚幏鐑芥晸閼哄倸鍤栭幏鐑芥晸閺傘倖瀚归柨鐔告灮閹风兘鏁撻弬銈嗗 1 闁跨喐鏋婚幏鐑芥晸閺傘倖瀚归悩鑸碘偓渚€鏁撻弬銈嗗濞岋繝鏁撻弬銈嗗闁跨喐鏋婚幏鐑芥晸閹瑰嘲鍤栭幏鐑芥晸閺傘倖瀚� +#define UART_CTRL_TXIDLE_Pos 0 //TX IDLE: 0 正在发送数据 1 空闲状态，没有数据发送 #define UART_CTRL_TXIDLE_Msk (0x01 << UART_CTRL_TXIDLE_Pos) #define UART_CTRL_TXFF_Pos 1 //TX FIFO Full #define UART_CTRL_TXFF_Msk (0x01 << UART_CTRL_TXFF_Pos) -#define UART_CTRL_TXIE_Pos 2 //TX 闁跨喎褰ㄧ拋瑙勫娴ｅ潡鏁撻弬銈嗗: 1 TX FF 闁跨喐鏋婚幏鐑芥晸閺傘倖瀚归柨鐔告灮閹风兘鏁撻弬銈嗗闁跨喐鏋婚幏鐑芥晸閸婄喎鐣鹃柨鐔告灮閹风兘鏁撻弬銈嗗閺冨爼鏁撻弬銈嗗闁跨喐鏋婚幏鐑芥晸閸欘偉顔愰幏锟� +#define UART_CTRL_TXIE_Pos 2 //TX 中断使能: 1 TX FF 中数据少于设定个数时产生中断 #define UART_CTRL_TXIE_Msk (0x01 << UART_CTRL_TXIE_Pos) #define UART_CTRL_RXNE_Pos 3 //RX FIFO Not Empty #define UART_CTRL_RXNE_Msk (0x01 << UART_CTRL_RXNE_Pos) -#define UART_CTRL_RXIE_Pos 4 //RX 闁跨喎褰ㄧ拋瑙勫娴ｅ潡鏁撻弬銈嗗: 1 RX FF 闁跨喐鏋婚幏鐑芥晸閺傘倖瀚归柨鐔稿祹鏉堟儳鍩岄柨鐔封偓鐔风暰闁跨喐鏋婚幏鐑芥晸閺傘倖瀚归弮鍫曟晸閺傘倖瀚归柨鐔告灮閹风兘鏁撻崣顐ヮ啇閹凤拷 +#define UART_CTRL_RXIE_Pos 4 //RX 中断使能: 1 RX FF 中数据达到设定个数时产生中断 #define UART_CTRL_RXIE_Msk (0x01 << UART_CTRL_RXIE_Pos) -#define UART_CTRL_RXOV_Pos 5 //RX FIFO Overflow闁跨喐鏋婚幏宄板晸1闁跨喐鏋婚幏鐑芥晸閺傘倖瀚� +#define UART_CTRL_RXOV_Pos 5 //RX FIFO Overflow，写1清零 #define UART_CTRL_RXOV_Msk (0x01 << UART_CTRL_RXOV_Pos) -#define UART_CTRL_TXDOIE_Pos 6 //TX Done 闁跨喎褰ㄧ拋瑙勫娴ｅ潡鏁撻弶甯秶閹风兘鏁撻弬銈嗗闁跨喐鏋婚幏绋FO闁跨喐鏋婚幏鐑芥晸閹活厼鍤栭幏鐑芥晸闁伴潧鍤栭幏鐑芥晸閺傘倖瀚归柨鐔告灮閹疯渹缍呴柨鐔惰寧鏉堢偓瀚归柨鐔告灮閹风兘鏁撶粣鏍ㄦ灮閹风兘鏁撻弬銈嗗闁跨喐褰弲鍐х串閹风兘鏁撻弬銈嗗缂佺喖鏁撴鐚存嫹 +#define UART_CTRL_TXDOIE_Pos 6 //TX Done 中断使能，发送FIFO空且发送发送移位寄存器已将最后一位发送出去 #define UART_CTRL_TXDOIE_Msk (0x01 << UART_CTRL_TXDOIE_Pos) #define UART_CTRL_EN_Pos 9 #define UART_CTRL_EN_Msk (0x01 << UART_CTRL_EN_Pos) #define UART_CTRL_LOOP_Pos 10 #define UART_CTRL_LOOP_Msk (0x01 << UART_CTRL_LOOP_Pos) -#define UART_CTRL_BAUDEN_Pos 13 //闁跨喐鏋婚幏鐑芥晸閺傘倖瀚归崘锟�1 +#define UART_CTRL_BAUDEN_Pos 13 //必须写1 #define UART_CTRL_BAUDEN_Msk (0x01 << UART_CTRL_BAUDEN_Pos) -#define UART_CTRL_TOIE_Pos 14 //TimeOut 闁跨喎褰ㄧ拋瑙勫娴ｅ潡鏁撻弶甯秶閹风兘鏁撻弬銈嗗闁跨喓笑绾板瀚归柨鐔荤窛闂堚晜瀚归柨鐔活敎閸戙倖瀚归柨鐔活殼閿涘瞼顒查幏鐑芥晸閺傘倖瀚� TOTIME/BAUDRAUD 闁跨喐鏋婚幏閿嬬梾闁跨喎褰ㄩ弬銈嗗闁跨喓笑绾板瀚归柨鐔兼應绾板瀚归柨鐔告灮閹风兘鏁撻弬銈嗗 +#define UART_CTRL_TOIE_Pos 14 //TimeOut 中断使能，接收到上个字符后，超过 TOTIME/BAUDRAUD 秒没有接收到新的数据 #define UART_CTRL_TOIE_Msk (0x01 << UART_CTRL_TOIE_Pos) -#define UART_CTRL_BRKDET_Pos 15 //LIN Break Detect闁跨喐鏋婚幏鐑芥晸閺傘倖瀚归悰鍓хオIN Break闁跨喐鏋婚幏鐑芥晸閺傘倖瀚筊X闁跨喐鏋婚幏鐑芥晸鏉堝啰銆嬮幏椋庡禃閺傘倖瀚归柨鐔告灮閹风兘鏁撻敓锟�11娴ｅ秹鏁撻柊鐢殿暜閹峰嘲閽� +#define UART_CTRL_BRKDET_Pos 15 //LIN Break Detect，检测到LIN Break，即RX线上检测到连续11位低电平 #define UART_CTRL_BRKDET_Msk (0x01 << UART_CTRL_BRKDET_Pos) -#define UART_CTRL_BRKIE_Pos 16 //LIN Break Detect 闁跨喎褰ㄧ拋瑙勫娴ｅ潡鏁撻弬銈嗗 +#define UART_CTRL_BRKIE_Pos 16 //LIN Break Detect 中断使能 #define UART_CTRL_BRKIE_Msk (0x01 << UART_CTRL_BRKIE_Pos) -#define UART_CTRL_GENBRK_Pos 17 //Generate LIN Break闁跨喐鏋婚幏鐑芥晸閺傘倖瀚归柨鐔告灮閹风ìIN Break +#define UART_CTRL_GENBRK_Pos 17 //Generate LIN Break，发送LIN Break #define UART_CTRL_GENBRK_Msk (0x01 << UART_CTRL_GENBRK_Pos) -#define UART_CTRL_DATA9b_Pos 18 //1 9娴ｅ秹鏁撻弬銈嗗闁跨喐鏋婚幏铚傜秴 0 8娴ｅ秹鏁撻弬銈嗗闁跨喐鏋婚幏铚傜秴 +#define UART_CTRL_DATA9b_Pos 18 //1 9位数据位 0 8位数据位 #define UART_CTRL_DATA9b_Msk (0x01 << UART_CTRL_DATA9b_Pos) -#define UART_CTRL_PARITY_Pos 19 //000 闁跨喐鏋婚幏閿嬬墡闁跨喐鏋婚幏锟� 001 闁跨喐鏋婚幏閿嬬墡闁跨喐鏋婚幏锟� 011 閸嬭埖鐗庨柨鐔告灮閹凤拷 101 闁跨喐鏆€鐠佽瀚规稉锟�1 111 闁跨喐鏆€鐠佽瀚规稉锟�0 +#define UART_CTRL_PARITY_Pos 19 //000 无校验 001 奇校验 011 偶校验 101 固定为1 111 固定为0 #define UART_CTRL_PARITY_Msk (0x07 << UART_CTRL_PARITY_Pos) -#define UART_CTRL_STOP2b_Pos 22 //1 2娴ｅ秴浠犲顫秴 0 1娴ｅ秴浠犲顫秴 +#define UART_CTRL_STOP2b_Pos 22 //1 2位停止位 0 1位停止位 #define UART_CTRL_STOP2b_Msk (0x03 << UART_CTRL_STOP2b_Pos) -#define UART_CTRL_TOTIME_Pos 24 //TimeOut 閺冨爼鏁撻弬銈嗗 = TOTIME/(BAUDRAUD/10) 闁跨喐鏋婚幏锟� -//#define UART_CTRL_TOTIME_Msk (0xFF << UART_CTRL_TOTIME_Pos) 闁跨喐鏋婚幏鐑芥晸閺傘倖瀚归柨鐔告灮閹风兘鏁撻弬銈嗗闁跨喕濮ら敍锟� integer operation result is out of range -#define UART_CTRL_TOTIME_Msk ((uint32_t)0xFF << UART_CTRL_TOTIME_Pos) +#define UART_CTRL_TOTIME_Pos 24 //TimeOut 时长 = TOTIME/(BAUDRAUD/10) 秒 +#define UART_CTRL_TOTIME_Msk (0xFFu << UART_CTRL_TOTIME_Pos) -#define UART_BAUD_BAUD_Pos 0 //闁跨喐鏋婚幏鐑芥晸閼哄倽顕滈幏鐑芥晸閺傘倖瀚归柨鐔告灮閹凤拷 = SYS_Freq/16/BAUD - 1 +#define UART_BAUD_BAUD_Pos 0 //串口波特率 = SYS_Freq/16/BAUD - 1 #define UART_BAUD_BAUD_Msk (0x3FFF << UART_BAUD_BAUD_Pos) -#define UART_BAUD_TXD_Pos 14 //闁岸鏁撻弬銈嗗闁跨喐鏋婚幏铚傜秴闁跨喐鏋婚幏椋庢纯闁跨喐甯寸拋瑙勫閸欐牠鏁撻弬銈嗗闁跨喐鏋婚幏绋礨D闁跨喐鏋婚幏鐑芥晸閺傘倖瀚归柨鐔荤窛閻ㄥ嫮顣幏宄伴挬 +#define UART_BAUD_TXD_Pos 14 //通过此位可直接读取串口TXD引脚上的电平 #define UART_BAUD_TXD_Msk (0x01 << UART_BAUD_TXD_Pos) -#define UART_BAUD_RXD_Pos 15 //闁岸鏁撻弬銈嗗闁跨喐鏋婚幏铚傜秴闁跨喐鏋婚幏椋庢纯闁跨喐甯寸拋瑙勫閸欐牠鏁撻弬銈嗗闁跨喐鏋婚幏绋瞂D闁跨喐鏋婚幏鐑芥晸閺傘倖瀚归柨鐔荤窛閻ㄥ嫮顣幏宄伴挬 +#define UART_BAUD_RXD_Pos 15 //通过此位可直接读取串口RXD引脚上的电平 #define UART_BAUD_RXD_Msk (0x01 << UART_BAUD_RXD_Pos) -#define UART_BAUD_RXTOIF_Pos 16 //闁跨喐鏋婚幏鐑芥晸閺傘倖瀚�&闁跨喐鏋婚幏閿嬫闁跨喐鏋婚幏鐑芥晸閸欘偅鏌囬幉瀣韫囷拷 = RXIF | TOIF +#define UART_BAUD_RXTOIF_Pos 16 //接收&超时的中断标志 = RXIF | TOIF #define UART_BAUD_RXTOIF_Msk (0x01 << UART_BAUD_RXTOIF_Pos) -#define UART_BAUD_TXIF_Pos 17 //闁跨喐鏋婚幏鐑芥晸閺傘倖瀚归柨鐔峰建閺傤厽鍞婚幏宄扮箶 = TXTHRF & TXIE +#define UART_BAUD_TXIF_Pos 17 //发送中断标志 = TXTHRF & TXIE #define UART_BAUD_TXIF_Msk (0x01 << UART_BAUD_TXIF_Pos) -#define UART_BAUD_BRKIF_Pos 18 //LIN Break Detect 闁跨喎褰ㄩ弬顓熷敾閹峰嘲绻旈柨鐔告灮閹风兘鏁撻弬銈嗗閻涘墽绁狪N Break閺冨爼鏁撻弬銈嗗BRKIE=1闁跨喐鏋婚幏鐑芥晸閺傘倖瀚规担宥夋晸閺傘倖瀚圭涵顒勬晸閺傘倖瀚归柨鐔告灮閹疯渹缍� +#define UART_BAUD_BRKIF_Pos 18 //LIN Break Detect 中断标志，检测到LIN Break时若BRKIE=1，此位由硬件置位 #define UART_BAUD_BRKIF_Msk (0x01 << UART_BAUD_BRKIF_Pos) -#define UART_BAUD_RXTHRF_Pos 19 //RX FIFO Threshold Flag闁跨喐鏋婚幏绋瞂 FIFO闁跨喐鏋婚幏鐑芥晸閺傘倖瀚归柨鐔稿祹鏉堟儳鍩岄柨鐔封偓鐔风暰闁跨喐鏋婚幏鐑芥晸閺傘倖瀚归柨鐔告灮閹风úXLVL >= RXTHR闁跨喐鏋婚幏閿嬫绾剟鏁撻弬銈嗗闁跨喐鏋婚幏锟�1 +#define UART_BAUD_RXTHRF_Pos 19 //RX FIFO Threshold Flag，RX FIFO中数据达到设定个数（RXLVL >= RXTHR）时硬件置1 #define UART_BAUD_RXTHRF_Msk (0x01 << UART_BAUD_RXTHRF_Pos) -#define UART_BAUD_TXTHRF_Pos 20 //TX FIFO Threshold Flag闁跨喐鏋婚幏绋礨 FIFO闁跨喐鏋婚幏鐑芥晸閺傘倖瀚归柨鐔告灮閹风兘鏁撻弬銈嗗闁跨喐鏋婚幏鐑芥晸閸婄喎鐣鹃柨鐔告灮閹风兘鏁撻弬銈嗗闁跨喐鏋婚幏绋礨LVL <= TXTHR闁跨喐鏋婚幏閿嬫绾剟鏁撻弬銈嗗闁跨喐鏋婚幏锟�1 +#define UART_BAUD_TXTHRF_Pos 20 //TX FIFO Threshold Flag，TX FIFO中数据少于设定个数（TXLVL <= TXTHR）时硬件置1 #define UART_BAUD_TXTHRF_Msk (0x01 << UART_BAUD_TXTHRF_Pos) -#define UART_BAUD_TOIF_Pos 21 //TimeOut 闁跨喎褰ㄩ弬顓熷敾閹峰嘲绻旈柨鐔告灮閹风兘鏁撻弬銈嗗闁跨喐鏋婚幏锟� TOTIME/BAUDRAUD 闁跨喐鏋婚幏閿嬬梾闁跨喎褰ㄩ弬銈嗗闁跨喓笑绾板瀚归柨鐔兼應绾板瀚归柨鐔告灮閹风兘鏁撻弬銈嗗閺冨爼鏁撻弬銈嗗TOIE=1闁跨喐鏋婚幏鐑芥晸閺傘倖瀚规担宥夋晸閺傘倖瀚圭涵顒勬晸閺傘倖瀚归柨鐔告灮閹疯渹缍� +#define UART_BAUD_TOIF_Pos 21 //TimeOut 中断标志，超过 TOTIME/BAUDRAUD 秒没有接收到新的数据时若TOIE=1，此位由硬件置位 #define UART_BAUD_TOIF_Msk (0x01 << UART_BAUD_TOIF_Pos) -#define UART_BAUD_RXIF_Pos 22 //闁跨喐鏋婚幏鐑芥晸閺傘倖瀚归柨鐔峰建閺傤厽鍞婚幏宄扮箶 = RXTHRF & RXIE +#define UART_BAUD_RXIF_Pos 22 //接收中断标志 = RXTHRF & RXIE #define UART_BAUD_RXIF_Msk (0x01 << UART_BAUD_RXIF_Pos) -#define UART_BAUD_ABREN_Pos 23 //Auto Baudrate Enable闁跨喐鏋婚幏宄板晸1闁跨喐鏋婚幏鐑芥晸閻ㄥ棜顔愰幏鐑芥晸閺傘倖瀚归柨鐔告灮閹风兘鏁撻弬銈嗗閺嶁€冲櫙闁跨喐鏋婚幏鐑芥晸閺傘倖瀚归悵濠囨晸閺傘倖瀚规潻婊堟晸閺傘倖瀚归柨鐔告灮閹风兘鏁撻敓锟� +#define UART_BAUD_ABREN_Pos 23 //Auto Baudrate Enable，写1启动自动波特率校准，完成后自动清零 #define UART_BAUD_ABREN_Msk (0x01 << UART_BAUD_ABREN_Pos) -#define UART_BAUD_ABRBIT_Pos 24 //Auto Baudrate Bit闁跨喐鏋婚幏鐑芥晸閺傘倖瀚归柨鐔诲Ν绾攱瀚归柨鐔奉潟濞夈垽鏁撻弬銈嗗闁跨喓绮搁惃鍕€嬮幏鐑芥晸鏉炲じ绱幏鐑芥晸閺傘倖瀚归柨鐕傛嫹0 1娴ｅ秹鏁撻弬銈嗗闁岸鏁撻弬銈嗗闁跨喐鏋婚幏鐑芥晸閺傘倖瀚规慨瀣╃秴 闁跨喐鏋婚幏鐑芥晸閺傘倖瀚归柨鐔告灮閹烽攱鍋為…鎺撳闁跨喐鏋婚幏宄板⒖闁跨喐褰搴㈠闁跨喐鏋婚幏閿嬪閺堟棃鏁撻弬銈嗗闁跨噦鎷�0xFF -// 1 2娴ｅ秹鏁撻弬銈嗗闁岸鏁撻弬銈嗗闁跨喐鏋婚幏鐑芥晸閺傘倖瀚规慨瀣╃秴闁跨喐鏋婚幏锟�1娴ｅ秹鏁撻弬銈嗗闁跨喐鏋婚幏铚傜秴闁跨喐鏋婚幏鐑芥晸閺傘倖瀚归柨鐔告灮閹烽攱鍋為…鎺撳闁跨喐鏋婚幏宄板⒖闁跨喐褰搴㈠闁跨喐鏋婚幏閿嬪閺堟棃鏁撻弬銈嗗闁跨噦鎷�0xFE -// 1 4娴ｅ秹鏁撻弬銈嗗闁岸鏁撻弬銈嗗闁跨喐鏋婚幏鐑芥晸閺傘倖瀚规慨瀣╃秴闁跨喐鏋婚幏锟�3娴ｅ秹鏁撻弬銈嗗闁跨喐鏋婚幏铚傜秴闁跨喐鏋婚幏鐑芥晸閺傘倖瀚归柨鐔告灮閹烽攱鍋為…鎺撳闁跨喐鏋婚幏宄板⒖闁跨喐褰搴㈠闁跨喐鏋婚幏閿嬪閺堟棃鏁撻弬銈嗗闁跨噦鎷�0xF8 -// 1 8娴ｅ秹鏁撻弬銈嗗闁岸鏁撻弬銈嗗闁跨喐鏋婚幏鐑芥晸閺傘倖瀚规慨瀣╃秴闁跨喐鏋婚幏锟�7娴ｅ秹鏁撻弬銈嗗闁跨喐鏋婚幏铚傜秴闁跨喐鏋婚幏鐑芥晸閺傘倖瀚归柨鐔告灮閹烽攱鍋為…鎺撳闁跨喐鏋婚幏宄板⒖闁跨喐褰搴㈠闁跨喐鏋婚幏閿嬪閺堟棃鏁撻弬銈嗗闁跨噦鎷�0x80 +#define UART_BAUD_ABRBIT_Pos 24 /*Auto Baudrate Bit，用于计算波特率的检测位长，0 1位，通过测起始位 脉宽计算波特率，要求发送端发送0xFF \ + // 1 2位，通过测起始位加1位数据位脉宽计算波特率，要求发送端发送0xFE \ + // 1 4位，通过测起始位加3位数据位脉宽计算波特率，要求发送端发送0xF8 \ + // 1 8位，通过测起始位加7位数据位脉宽计算波特率，要求发送端发送0x80 */ #define UART_BAUD_ABRBIT_Msk (0x03 << UART_BAUD_ABRBIT_Pos) -#define UART_BAUD_ABRERR_Pos 26 //Auto Baudrate Error闁跨喐鏋婚幏锟�0 闁跨喓娈曠拋瑙勫闁跨喐鏋婚幏鐑芥晸閺傘倖瀚归柨鐔告灮閹烽攱鐗庨崙鍡涙晸缂傚娅㈤幏锟� 1 闁跨喓娈曠拋瑙勫闁跨喐鏋婚幏鐑芥晸閺傘倖瀚归柨鐔告灮閹烽攱鐗庨崙鍡椼亼闁跨喐鏋婚幏锟� +#define UART_BAUD_ABRERR_Pos 26 //Auto Baudrate Error，0 自动波特率校准成功 1 自动波特率校准失败 #define UART_BAUD_ABRERR_Msk (0x01 << UART_BAUD_ABRERR_Pos) -#define UART_BAUD_TXDOIF_Pos 27 //TX Done 闁跨喎褰ㄩ弬顓熷敾閹峰嘲绻旈柨鐔告灮閹风兘鏁撻弬銈嗗闁跨喐鏋婚幏绋FO闁跨喐鏋婚幏鐑芥晸閹活厼鍤栭幏鐑芥晸闁伴潧鍤栭幏鐑芥晸閺傘倖瀚归柨鐔告灮閹疯渹缍呴柨鐔惰寧鏉堢偓瀚归柨鐔告灮閹风兘鏁撶粣鏍ㄦ灮閹风兘鏁撻弬銈嗗闁跨喐褰弲鍐х串閹风兘鏁撻弬銈嗗缂佺喖鏁撴鐚存嫹 +#define UART_BAUD_TXDOIF_Pos 27 //TX Done 中断标志，发送FIFO空且发送发送移位寄存器已将最后一位发送出去 #define UART_BAUD_TXDOIF_Msk (0x01 << UART_BAUD_TXDOIF_Pos) -#define UART_FIFO_RXLVL_Pos 0 //RX FIFO Level闁跨喐鏋婚幏绋瞂 FIFO 闁跨喐鏋婚幏鐑芥晸鐞涙鍤栭幏鐑芥晸閺傘倖瀚归柨鐔告灮閹凤拷 +#define UART_FIFO_RXLVL_Pos 0 //RX FIFO Level，RX FIFO 中字符个数 #define UART_FIFO_RXLVL_Msk (0xFF << UART_FIFO_RXLVL_Pos) -#define UART_FIFO_TXLVL_Pos 8 //TX FIFO Level闁跨喐鏋婚幏绋礨 FIFO 闁跨喐鏋婚幏鐑芥晸鐞涙鍤栭幏鐑芥晸閺傘倖瀚归柨鐔告灮閹凤拷 +#define UART_FIFO_TXLVL_Pos 8 //TX FIFO Level，TX FIFO 中字符个数 #define UART_FIFO_TXLVL_Msk (0xFF << UART_FIFO_TXLVL_Pos) -#define UART_FIFO_RXTHR_Pos 16 //RX FIFO Threshold闁跨喐鏋婚幏绋瞂闁跨喎褰ㄩ弬顓℃彧閹风兘鏁撻弬銈嗗闁跨喐鏋婚幏鐑芥晸閻偓缍囬幏鐑芥晸閸欘偉顔愰幏铚傚▏闁跨喐鏋婚幏閿嬫 RXLVL >= RXTHR 闁跨喐鏋婚幏鐑芥晸閺傘倖瀚筊X闁跨喎褰ㄧ拋瑙勫 +#define UART_FIFO_RXTHR_Pos 16 //RX FIFO Threshold，RX中断触发门限，中断使能时 RXLVL >= RXTHR 触发RX中断 #define UART_FIFO_RXTHR_Msk (0xFF << UART_FIFO_RXTHR_Pos) -#define UART_FIFO_TXTHR_Pos 24 //TX FIFO Threshold闁跨喐鏋婚幏绋礨闁跨喎褰ㄩ弬顓℃彧閹风兘鏁撻弬銈嗗闁跨喐鏋婚幏鐑芥晸閻偓缍囬幏鐑芥晸閸欘偉顔愰幏铚傚▏闁跨喐鏋婚幏閿嬫 TXLVL <= TXTHR 闁跨喐鏋婚幏鐑芥晸閺傘倖瀚筎X闁跨喎褰ㄧ拋瑙勫 -//#define UART_FIFO_TXTHR_Msk (0xFF << UART_FIFO_TXTHR_Pos) 闁跨喐鏋婚幏鐑芥晸閺傘倖瀚归柨鐔告灮閹风兘鏁撻弬銈嗗闁跨喕濮ら敍锟� integer operation result is out of range -#define UART_FIFO_TXTHR_Msk ((uint32_t)0xFF << UART_FIFO_TXTHR_Pos) +#define UART_FIFO_TXTHR_Pos 24 //TX FIFO Threshold，TX中断触发门限，中断使能时 TXLVL <= TXTHR 触发TX中断 +#define UART_FIFO_TXTHR_Msk (0xFFu << UART_FIFO_TXTHR_Pos) -#define UART_LINCR_BRKDETIE_Pos 0 //闁跨喐鏋婚幏椋庡禃缁插儐N Break闁跨喎褰ㄧ拋瑙勫娴ｅ潡鏁撻弬銈嗗 -#define UART_LINCR_BRKDETIE_Msk (0xFF << UART_LINCR_BRKDETIE_Pos) -#define UART_LINCR_BRKDETIF_Pos 1 //闁跨喐鏋婚幏椋庡禃缁插儐N Break闁跨喎褰ㄧ拋瑙勫閻樿埖鈧拷 -#define UART_LINCR_BRKDETIF_Msk (0xFF << UART_LINCR_BRKDETIF_Pos) -#define UART_LINCR_GENBRKIE_Pos 2 //闁跨喐鏋婚幏鐑芥晸閺傘倖瀚筁IN Break闁跨喐鏋婚幏鐑芥晸閺傘倖瀚归崡鎼佹晸缂佺偟娅㈤幏鐑芥晸閿燂拷 -#define UART_LINCR_GENBRKIE_Msk (0xFF << UART_LINCR_GENBRKIE_Pos) -#define UART_LINCR_GENBRKIF_Pos 3 //闁跨喐鏋婚幏鐑芥晸閺傘倖瀚筁IN Break闁跨喐鏋婚幏鐑芥晸閺傘倖瀚归崡鎼佹晸闂冭泛鍩￠敓锟� -#define UART_LINCR_GENBRKIF_Msk (0xFF << UART_LINCR_GENBRKIF_Pos) -#define UART_LINCR_GENBRK_Pos 4 //闁跨喐鏋婚幏鐑芥晸閺傘倖瀚筁IN Break闁跨喐鏋婚幏鐑芥晸閺傘倖瀚归柨鐔告灮閹风兘鏁撻弬銈嗗闁跨喐鏋婚幏鐤箼闁跨喐鏋婚幏鐑芥晸閺傘倖瀚归柨鐕傛嫹 -#define UART_LINCR_GENBRK_Msk (0xFF << UART_LINCR_GENBRK_Pos) +#define UART_LINCR_BRKDETIE_Pos 0 //检测到LIN Break中断使能 +#define UART_LINCR_BRKDETIE_Msk (0x01 << UART_LINCR_BRKDETIE_Pos) +#define UART_LINCR_BRKDETIF_Pos 1 //检测到LIN Break中断状态 +#define UART_LINCR_BRKDETIF_Msk (0x01 << UART_LINCR_BRKDETIF_Pos) +#define UART_LINCR_GENBRKIE_Pos 2 //发送LIN Break完成中断使能 +#define UART_LINCR_GENBRKIE_Msk (0x01 << UART_LINCR_GENBRKIE_Pos) +#define UART_LINCR_GENBRKIF_Pos 3 //发送LIN Break完成中断状态 +#define UART_LINCR_GENBRKIF_Msk (0x01 << UART_LINCR_GENBRKIF_Pos) +#define UART_LINCR_GENBRK_Pos 4 //发送LIN Break，发送完成自动清零 +#define UART_LINCR_GENBRK_Msk (0x01 << UART_LINCR_GENBRK_Pos) -#define UART_CTSCR_EN_Pos 0 //CTS闁跨喐鏋婚幏鐑芥晸閺傘倖瀚规担鍧楁晸閺傘倖瀚� +#define UART_CTSCR_EN_Pos 0 //CTS流控使能 #define UART_CTSCR_EN_Msk (0x01 << UART_CTSCR_EN_Pos) -#define UART_CTSCR_POL_Pos 2 //CTS闁跨喕鍓奸崣椋庛€嬮幏鐑芥晸閻ㄥ棴缍囬幏锟�0 闁跨喐鏋婚幏鐑芥晸閺傘倖瀚归弫鍫ユ晸閺傘倖瀚笴TS闁跨喐鏋婚幏鐑芥晸閺傘倖瀚规稉娲晸闁板灚鍞婚幏椋庛仛闁跨喐鏋婚幏鐑芥晸閻ㄥ棗鍤栭幏鐑芥晸閺傘倖瀚归柨鐔告灮閹风兘鏁撻弬銈嗗 +#define UART_CTSCR_POL_Pos 2 //CTS信号极性，0 低有效，CTS输入为低表示可以发送数据 #define UART_CTSCR_POL_Msk (0x01 << UART_CTSCR_POL_Pos) -#define UART_CTSCR_STAT_Pos 7 //CTS闁跨喕鍓奸崣椋庢畱绾板瀚归崜宥囧Ц閹拷 +#define UART_CTSCR_STAT_Pos 7 //CTS信号的当前状态 #define UART_CTSCR_STAT_Msk (0x01 << UART_CTSCR_STAT_Pos) -#define UART_RTSCR_EN_Pos 1 //RTS闁跨喐鏋婚幏鐑芥晸閺傘倖瀚规担鍧楁晸閺傘倖瀚� +#define UART_RTSCR_EN_Pos 1 //RTS流控使能 #define UART_RTSCR_EN_Msk (0x01 << UART_RTSCR_EN_Pos) -#define UART_RTSCR_POL_Pos 3 //RTS闁跨喕鍓奸崣椋庛€嬮幏鐑芥晸閺傘倖瀚� 0 闁跨喐鏋婚幏鐑芥晸閺傘倖瀚归弫鍫ユ晸閺傘倖瀚筊TS闁跨喐鏋婚幏鐑芥晸閺傘倖瀚规稉娲晸闁板灚鍞婚幏椋庛仛闁跨喐鏋婚幏鐑芥晸閻ㄥ棙鏋婚幏鐑芥晸閺傘倖瀚归柨鐔告灮閹风兘鏁撻弬銈嗗 +#define UART_RTSCR_POL_Pos 3 //RTS信号极性 0 低有效，RTS输入为低表示可以接收数据 #define UART_RTSCR_POL_Msk (0x01 << UART_RTSCR_POL_Pos) -#define UART_RTSCR_THR_Pos 4 //RTS闁跨喐鏋婚幏鐑芥晸閹搭亞娈戞潏鐐闁跨喐鏋婚幏鐑芥晸閺傘倖瀚归崐锟� 0 1闁跨喕顢滈弬銈嗗 1 2闁跨喕顢滈弬銈嗗 2 4闁跨喕顢滈弬銈嗗 3 6闁跨喕顢滈弬銈嗗 +#define UART_RTSCR_THR_Pos 4 //RTS流控的触发阈值 0 1字节 1 2字节 2 4字节 3 6字节 #define UART_RTSCR_THR_Msk (0x07 << UART_RTSCR_THR_Pos) -#define UART_RTSCR_STAT_Pos 8 //RTS闁跨喕鍓奸崣椋庢畱绾板瀚归崜宥囧Ц閹拷 +#define UART_RTSCR_STAT_Pos 8 //RTS信号的当前状态 #define UART_RTSCR_STAT_Msk (0x01 << UART_RTSCR_STAT_Pos) typedef struct @@ -803,46 +1408,46 @@ typedef struct __IO uint32_t IF; } SPI_TypeDef; -#define SPI_CTRL_CLKDIV_Pos 0 //Clock Divider, SPI闁跨喐鏋婚幏鐑芥晸閺傘倖瀚归弮鍫曟晸閺傘倖瀚� = SYS_Freq/pow(2, CLKDIV+2) +#define SPI_CTRL_CLKDIV_Pos 0 //Clock Divider, SPI工作时钟 = SYS_Freq/pow(2, CLKDIV+2) #define SPI_CTRL_CLKDIV_Msk (0x07 << SPI_CTRL_CLKDIV_Pos) #define SPI_CTRL_EN_Pos 3 #define SPI_CTRL_EN_Msk (0x01 << SPI_CTRL_EN_Pos) -#define SPI_CTRL_SIZE_Pos 4 //Data Size Select, 閸欐牕鈧拷3--15闁跨喐鏋婚幏鐑芥晸閺傘倖瀚圭粈锟�4--16娴ｏ拷 +#define SPI_CTRL_SIZE_Pos 4 //Data Size Select, 取值3--15，表示4--16位 #define SPI_CTRL_SIZE_Msk (0x0F << SPI_CTRL_SIZE_Pos) -#define SPI_CTRL_CPHA_Pos 8 //0 闁跨喐鏋婚幏绋碈LK闁跨喍鑼庣喊澶嬪娑撯偓闁跨喐鏋婚幏鐑芥晸閺傘倖瀚归柨鐔告灮閹风兘鏁撻幋顏囶嚋閹风兘鏁撻弬銈嗗闁跨喐鏋婚幏鐑芥晸閺傘倖瀚� 1 闁跨喐鏋婚幏绋碈LK闁跨喍鑼庣粭顒冾啇閹风兘鏁撻弬銈嗗闁跨喐鏋婚幏鐑芥晸閺傘倖瀚归柨鐔稿焻鐠囇勫闁跨喐鏋婚幏鐑芥晸閺傘倖瀚归柨鐔告灮閹凤拷 +#define SPI_CTRL_CPHA_Pos 8 //0 在SCLK的第一个跳变沿采样数据 1 在SCLK的第二个跳变沿采样数据 #define SPI_CTRL_CPHA_Msk (0x01 << SPI_CTRL_CPHA_Pos) -#define SPI_CTRL_CPOL_Pos 9 //0 闁跨喐鏋婚幏鐑芥晸閺傘倖瀚归悩鑸碘偓渚€鏁撻弬銈嗗SCLK娑撴椽鏁撻柊鐢殿暜閹峰嘲閽� 1 闁跨喐鏋婚幏鐑芥晸閺傘倖瀚归悩鑸碘偓渚€鏁撻弬銈嗗SCLK娑撴椽鏁撶粩顓狀暜閹峰嘲閽� +#define SPI_CTRL_CPOL_Pos 9 //0 空闲状态下SCLK为低电平 1 空闲状态下SCLK为高电平 #define SPI_CTRL_CPOL_Msk (0x01 << SPI_CTRL_CPOL_Pos) #define SPI_CTRL_FFS_Pos 10 //Frame Format Select, 0 SPI 1 TI SSI 2 SPI 3 SPI #define SPI_CTRL_FFS_Msk (0x03 << SPI_CTRL_FFS_Pos) -#define SPI_CTRL_MSTR_Pos 12 //Master, 1 闁跨喐鏋婚幏閿嬆佸锟� 0 闁跨喐鏋婚幏閿嬆佸锟� +#define SPI_CTRL_MSTR_Pos 12 //Master, 1 主模式 0 从模式 #define SPI_CTRL_MSTR_Msk (0x01 << SPI_CTRL_MSTR_Pos) -#define SPI_CTRL_FAST_Pos 13 //1 SPI闁跨喐鏋婚幏鐑芥晸閺傘倖瀚归弮鍫曟晸閺傘倖瀚� = SYS_Freq/2 0 SPI闁跨喐鏋婚幏鐑芥晸閺傘倖瀚归弮鍫曟晸閺傘倖瀚归柨鐔告灮閹风ùPI->CTRL.CLKDIV闁跨喐鏋婚幏鐑芥晸閺傘倖瀚� +#define SPI_CTRL_FAST_Pos 13 //1 SPI工作时钟 = SYS_Freq/2 0 SPI工作时钟由SPI->CTRL.CLKDIV设置 #define SPI_CTRL_FAST_Msk (0x01 << SPI_CTRL_FAST_Pos) -#define SPI_CTRL_FILTE_Pos 16 //1 闁跨喐鏋婚幏绋碢I闁跨喐鏋婚幏鐑芥晸閺傘倖瀚归柨鐔诲壖閸欓攱鏋婚幏鐑芥晸閺傘倖瀚归崢濠氭晸閺傘倖瀚归柨鐔告灮閹风兘鏁撻弬銈嗗 0 闁跨喐鏋婚幏绋碢I闁跨喐鏋婚幏鐑芥晸閺傘倖瀚归柨鐔诲壖閸欑柉顕滈幏鐑芥晸閺傘倖瀚归柨鐔告灮閹峰嘲骞撻柨鐔告灮閹风兘鏁撻弬銈嗗闁跨喐鏋婚幏锟� +#define SPI_CTRL_FILTE_Pos 16 //1 对SPI输入信号进行去抖操作 0 对SPI输入信号不进行去抖操作 #define SPI_CTRL_FILTE_Msk (0x01 << SPI_CTRL_FILTE_Pos) -#define SPI_CTRL_SSN_H_Pos 17 //0 闁跨喐鏋婚幏鐑芥晸閺傘倖瀚归柨鐔告灮閹风兘鏁撻弬銈嗗闁跨喓绁砈N婵鏁撻弬銈嗗娑擄拷0 1 闁跨喐鏋婚幏鐑芥晸閺傘倖瀚归柨鐔告灮閹风兘鏁撻弬銈嗗闁跨喓鐓崠鈩冨閸р偓闁跨喕顢滈鍡樺闁跨喓绮ㄧ亸鍝燬N闁跨喐鏋婚幏鐑芥晸缁旑厼搴滈幏鐑芥晸缁插LK闁跨喐鏋婚幏鐑芥晸閺傘倖瀚� +#define SPI_CTRL_SSN_H_Pos 17 //0 传输过程中SSN始终为0 1 传输过程中每字符之间会将SSN拉高半个SCLK周期 #define SPI_CTRL_SSN_H_Msk (0x01 << SPI_CTRL_SSN_H_Pos) #define SPI_CTRL_TFCLR_Pos 24 //TX FIFO Clear #define SPI_CTRL_TFCLR_Msk (0x01 << SPI_CTRL_TFCLR_Pos) #define SPI_CTRL_RFCLR_Pos 25 //RX FIFO Clear #define SPI_CTRL_RFCLR_Msk (0x01 << SPI_CTRL_RFCLR_Pos) -#define SPI_STAT_WTC_Pos 0 //Word Transmit Complete闁跨喐鏋婚幏閿嬬槨闁跨喐鏋婚幏鐑芥晸閺傘倖瀚归柨鐔告灮閹风兘鏁撻幓顓濈串閹风兘鏁撻弬銈嗗闁跨喐鏋婚幏鐑芥晸閺傘倖瀚归柨鐔告灮閹风兘鏁撻幒銉嚋閹风兘鏁撻弬銈嗗闁跨噦鎷�1闁跨喐鏋婚幏鐑芥晸閺傘倖瀚归柨鐔峰建閿燂拷1闁跨喐鏋婚幏鐑芥晸閺傘倖瀚� +#define SPI_STAT_WTC_Pos 0 //Word Transmit Complete，每传输完成一个数据字由硬件置1，软件写1清零 #define SPI_STAT_WTC_Msk (0x01 << SPI_STAT_WTC_Pos) -#define SPI_STAT_TFE_Pos 1 //闁跨喐鏋婚幏鐑芥晸閺傘倖瀚笷IFO Empty +#define SPI_STAT_TFE_Pos 1 //发送FIFO Empty #define SPI_STAT_TFE_Msk (0x01 << SPI_STAT_TFE_Pos) -#define SPI_STAT_TFNF_Pos 2 //闁跨喐鏋婚幏鐑芥晸閺傘倖瀚笷IFO Not Full +#define SPI_STAT_TFNF_Pos 2 //发送FIFO Not Full #define SPI_STAT_TFNF_Msk (0x01 << SPI_STAT_TFNF_Pos) -#define SPI_STAT_RFNE_Pos 3 //闁跨喐鏋婚幏鐑芥晸閺傘倖瀚笷IFO Not Empty +#define SPI_STAT_RFNE_Pos 3 //接收FIFO Not Empty #define SPI_STAT_RFNE_Msk (0x01 << SPI_STAT_RFNE_Pos) -#define SPI_STAT_RFF_Pos 4 //闁跨喐鏋婚幏鐑芥晸閺傘倖瀚笷IFO Full +#define SPI_STAT_RFF_Pos 4 //接收FIFO Full #define SPI_STAT_RFF_Msk (0x01 << SPI_STAT_RFF_Pos) -#define SPI_STAT_RFOVF_Pos 5 //闁跨喐鏋婚幏鐑芥晸閺傘倖瀚笷IFO Overflow +#define SPI_STAT_RFOVF_Pos 5 //接收FIFO Overflow #define SPI_STAT_RFOVF_Msk (0x01 << SPI_STAT_RFOVF_Pos) -#define SPI_STAT_TFLVL_Pos 6 //闁跨喐鏋婚幏鐑芥晸閺傘倖瀚笷IFO闁跨喐鏋婚幏鐑芥晸閺傘倖瀚归柨鐔稿祹闂堚晜瀚归柨鐔告灮閹风兘鏁撻弬銈嗗 0 TFNF=0閺冨爼鏁撻弬銈嗗缁€绡嶪FO闁跨喐鏋婚幏鐑芥晸閺傘倖瀚�8闁跨喐鏋婚幏鐑芥晸閺傘倖瀚归柨鐔稿祹閿濆繑瀚筎FNF=1閺冨爼鏁撻弬銈嗗缁€绡嶪FO闁跨喐鏋婚幏鐑芥晸閺傘倖瀚�0闁跨喐鏋婚幏鐑芥晸閺傘倖瀚归柨鐔告灮閹凤拷 1--7 FIFO闁跨喐鏋婚幏鐑芥晸閺傘倖瀚�1--7闁跨喐鏋婚幏鐑芥晸閺傘倖瀚归柨鐔告灮閹凤拷 +#define SPI_STAT_TFLVL_Pos 6 //发送FIFO中数据个数， 0 TFNF=0时表示FIFO内有8个数据，TFNF=1时表示FIFO内有0个数据 1--7 FIFO内有1--7个数据 #define SPI_STAT_TFLVL_Msk (0x07 << SPI_STAT_TFLVL_Pos) -#define SPI_STAT_RFLVL_Pos 9 //闁跨喐鏋婚幏鐑芥晸閺傘倖瀚笷IFO闁跨喐鏋婚幏鐑芥晸閺傘倖瀚归柨鐔稿祹闂堚晜瀚归柨鐔告灮閹风兘鏁撻弬銈嗗 0 RFF=1閺冨爼鏁撻弬銈嗗缁€绡嶪FO闁跨喐鏋婚幏鐑芥晸閺傘倖瀚�8闁跨喐鏋婚幏鐑芥晸閺傘倖瀚归柨鐔稿祹閿濆繑瀚� RFF=0閺冨爼鏁撻弬銈嗗缁€绡嶪FO闁跨喐鏋婚幏鐑芥晸閺傘倖瀚�0闁跨喐鏋婚幏鐑芥晸閺傘倖瀚归柨鐔告灮閹凤拷 1--7 FIFO闁跨喐鏋婚幏鐑芥晸閺傘倖瀚�1--7闁跨喐鏋婚幏鐑芥晸閺傘倖瀚归柨鐔告灮閹凤拷 +#define SPI_STAT_RFLVL_Pos 9 //接收FIFO中数据个数， 0 RFF=1时表示FIFO内有8个数据， RFF=0时表示FIFO内有0个数据 1--7 FIFO内有1--7个数据 #define SPI_STAT_RFLVL_Msk (0x07 << SPI_STAT_RFLVL_Pos) #define SPI_STAT_BUSY_Pos 15 #define SPI_STAT_BUSY_Msk (0x01 << SPI_STAT_BUSY_Pos) @@ -862,7 +1467,7 @@ typedef struct #define SPI_IE_FTC_Pos 9 //Frame Transmit Complete #define SPI_IE_FTC_Msk (0x01 << SPI_IE_FTC_Pos) -#define SPI_IF_RFOVF_Pos 0 //閸愶拷1闁跨喐鏋婚幏鐑芥晸閺傘倖瀚� +#define SPI_IF_RFOVF_Pos 0 //写1清零 #define SPI_IF_RFOVF_Msk (0x01 << SPI_IF_RFOVF_Pos) #define SPI_IF_RFF_Pos 1 #define SPI_IF_RFF_Msk (0x01 << SPI_IF_RFF_Pos) @@ -872,14 +1477,14 @@ typedef struct #define SPI_IF_TFE_Msk (0x01 << SPI_IF_TFE_Pos) #define SPI_IF_TFHF_Pos 4 #define SPI_IF_TFHF_Msk (0x01 << SPI_IF_TFHF_Pos) -#define SPI_IF_WTC_Pos 8 //Word Transmit Complete闁跨喐鏋婚幏閿嬬槨闁跨喐鏋婚幏鐑芥晸閺傘倖瀚归柨鐔告灮閹风兘鏁撻幓顓濈串閹风兘鏁撻弬銈嗗闁跨喐鏋婚幏鐑芥晸閺傘倖瀚归柨鐔告灮閹风兘鏁撻幒銉嚋閹风兘鏁撻弬銈嗗闁跨噦鎷�1 +#define SPI_IF_WTC_Pos 8 //Word Transmit Complete，每传输完成一个数据字由硬件置1 #define SPI_IF_WTC_Msk (0x01 << SPI_IF_WTC_Pos) -#define SPI_IF_FTC_Pos 9 //Frame Transmit Complete闁跨喐鏋婚幏绋篢C闁跨喐鏋婚幏铚傜秴閺冨爼鏁撻弬銈嗗TX FIFO闁跨喕顫楃粚铏规畱閿濆繑瀚归柨鐔告灮閹风éTC闁跨喐鏋婚幏铚傜秴 +#define SPI_IF_FTC_Pos 9 //Frame Transmit Complete，WTC置位时若TX FIFO是空的，则FTC置位 #define SPI_IF_FTC_Msk (0x01 << SPI_IF_FTC_Pos) typedef struct { - __IO uint32_t CLKDIV; //[15:0] 闁跨喕顕犵亸鍡涙晸閼哄倽顕滈幏鐑芥晸閺傘倖瀚归柨鐔告灮閹风兘顣堕柨鐔虹哺閸掑棛顣幏绋碈L妫版垿鏁撶紒鐐殿暜閹凤拷5闁跨喐鏋婚幏鐑芥晸閺傘倖瀚归柨鐔告灮閹风áLKDIV = SYS_Freq/5/SCL_Freq - 1 + __IO uint32_t CLKDIV; //[15:0] 须将内部工作频率分到SCL频率的5倍，即CLKDIV = SYS_Freq/5/SCL_Freq - 1 __IO uint32_t CTRL; @@ -901,61 +1506,61 @@ typedef struct #define I2C_CTRL_EN_Pos 7 #define I2C_CTRL_EN_Msk (0x01 << I2C_CTRL_EN_Pos) -#define I2C_MSTCMD_IF_Pos 0 //1 闁跨喎褰ㄧ粵澶庢彧閹风兘鏁撻弬銈嗗闁跨喐鏋婚幏鐑芥晸閺傘倖瀚归崡绋跨瑖闁跨喎褰ㄩ敓锟�1闁跨喐鏋婚幏鐑芥晸閺傘倖瀚� 闁跨喐鏋婚幏鐑芥晸閺傘倖瀚归柨鐔告灮閹风兘鏁撻弬銈嗗闁跨喐鏋婚幏鐑界氨闁跨喕濞囬幐銉嚋閹风兘鏁撻弬銈嗗闁跨喕濞囨导娆愬闁跨噦鎷�1闁跨喐鏋婚幏铚傜闁跨喐鏋婚幏鐑芥晸鐞涙濡潏鐐闁跨喐鏋婚幏鐑芥晸閺傘倖瀚归柨鐕傛嫹 2闁跨喐鏋婚幏鐑芥晸閺傘倖瀚归柨鐔侯仾閸戙倖瀚归柨鐔告灮閹烽攱娼堥柨鐔告灮閹峰嘲銇� +#define I2C_MSTCMD_IF_Pos 0 //1 有等待处理的中断，写1清零 有两种情况下此位硬件置位：1、一个字节传输完成 2、总线访问权丢失 #define I2C_MSTCMD_IF_Msk (0x01 << I2C_MSTCMD_IF_Pos) #define I2C_MSTCMD_TIP_Pos 1 //Transmission In Process #define I2C_MSTCMD_TIP_Msk (0x01 << I2C_MSTCMD_TIP_Pos) -#define I2C_MSTCMD_ACK_Pos 3 //闁跨喐鏋婚幏鐑芥晸閺傘倖瀚瑰Ο鈥崇础闁跨喖鎽敐蹇斿0 闁跨喐鏋婚幏鐑芥晸闁扮數顏崙銈嗗闁跨喐鏋婚幏绋烠K 1 闁跨喐鏋婚幏鐑芥晸闁扮數顏崙銈嗗闁跨喐鏋婚幏绋瓵CK +#define I2C_MSTCMD_ACK_Pos 3 //接收模式下，0 向发送端反馈ACK 1 向发送端反馈NACK #define I2C_MSTCMD_ACK_Msk (0x01 << I2C_MSTCMD_ACK_Pos) -#define I2C_MSTCMD_WR_Pos 4 // 闁跨喐鏋婚幏绋磍ave閸愭瑩鏁撻弬銈嗗闁跨喐鏋婚幏閿嬫闁跨喐鏋婚幏鐑芥晸閺傘倖瀚归柨鐔告灮閹疯渹绔存担宥呭晸1闁跨喐鏋婚幏鐑芥晸閻ㄥ棜顔愰幏鐑芥晸閺傘倖瀚归柨鐔告灮閹凤拷 +#define I2C_MSTCMD_WR_Pos 4 // 向Slave写数据时，把这一位写1，自动清零 #define I2C_MSTCMD_WR_Msk (0x01 << I2C_MSTCMD_WR_Pos) -#define I2C_MSTCMD_RD_Pos 5 //閸愭瑩鏁撻弬銈嗗闁跨喐鏋婚幏绋磍ave闁跨喐鏋婚幏鐑芥晸閺傘倖瀚归柨鐔告灮閹烽攱妞傞柨鐔告灮閹风兘鏁撻弬銈嗗闁跨喐鏋婚幏铚傜娴ｅ秴鍟�1闁跨喐鏋婚幏鐑芥晸閻ㄥ棜顔愰幏鐑芥晸閺傘倖瀚归柨鐔告灮閹凤拷 闁跨喐鏋婚幏鐑芥晸閺傘倖瀚归柨鐔告灮閹风ī2C濡繝鏁撻弬銈嗗婢跺崬骞撻柨鐔告灮閹风兘鏁撶粩顓犳畱閸戙倖瀚归柨鐔告灮閹烽攱娼堥弮鍓佲€栭柨鐔告灮閹风兘鏁撻弬銈嗗1 +#define I2C_MSTCMD_RD_Pos 5 //写：从Slave读数据时，把这一位写1，自动清零 读：当I2C模块失去总线的访问权时硬件置1 #define I2C_MSTCMD_RD_Msk (0x01 << I2C_MSTCMD_RD_Pos) -#define I2C_MSTCMD_BUSY_Pos 6 //闁跨喐鏋婚幏鐑芥晸閺傘倖瀚归柨鐔告灮閹风兘鏁撻弬銈嗗閻涘墽绁砊ART娑斿鏁撻弬銈嗗闁跨喐鏋婚幏铚傜娴ｅ秹鏁撻弬銈嗗1闁跨喐鏋婚幏鐑芥晸閺傘倖瀚归柨鐔告灮閹烽宓曠徊濂P娑斿鏁撻弬銈嗗闁跨喐鏋婚幏铚傜娴ｅ秹鏁撻弬銈嗗0 +#define I2C_MSTCMD_BUSY_Pos 6 //读：当检测到START之后，这一位变1；当检测到STOP之后，这一位变0 #define I2C_MSTCMD_BUSY_Msk (0x01 << I2C_MSTCMD_BUSY_Pos) -#define I2C_MSTCMD_STO_Pos 6 //閸愭瑩鏁撻弬銈嗗闁跨喐鏋婚幏鐑芥晸閺傘倖瀚筍TOP闁跨喐鏋婚幏鐑芥晸閻ㄥ棜顔愰幏鐑芥晸閺傘倖瀚归柨鐔告灮閹凤拷 +#define I2C_MSTCMD_STO_Pos 6 //写：产生STOP，自动清零 #define I2C_MSTCMD_STO_Msk (0x01 << I2C_MSTCMD_STO_Pos) -#define I2C_MSTCMD_RXACK_Pos 7 //闁跨喐鏋婚幏鐑芥晸閺傘倖瀚归柨鐔告灮閹风兘鏁撶粔鍝ヮ暜閹风兘鏁撻弬銈嗗Slave闁跨喐鏋婚幏绋烠K娴ｅ秹鏁撻弬銈嗗0 闁跨喓笑绾板瀚笰CK 1 闁跨喓笑绾板瀚筃ACK +#define I2C_MSTCMD_RXACK_Pos 7 //读：接收到的Slave的ACK位，0 收到ACK 1 收到NACK #define I2C_MSTCMD_RXACK_Msk (0x01 << I2C_MSTCMD_RXACK_Pos) -#define I2C_MSTCMD_STA_Pos 7 //閸愭瑩鏁撻弬銈嗗闁跨喐鏋婚幏鐑芥晸閺傘倖瀚筍TART闁跨喐鏋婚幏鐑芥晸閻ㄥ棜顔愰幏鐑芥晸閺傘倖瀚归柨鐔告灮閹凤拷 +#define I2C_MSTCMD_STA_Pos 7 //写：产生START，自动清零 #define I2C_MSTCMD_STA_Msk (0x01 << I2C_MSTCMD_STA_Pos) -#define I2C_SLVCR_IM_RXEND_Pos 0 //闁跨喐鏋婚幏鐑芥晸閺傘倖瀚归柨鐔告灮閹风兘鏁撻弬銈嗗閸楁瓕绶伴柨鐔活敎閿燂拷 +#define I2C_SLVCR_IM_RXEND_Pos 0 //接收完成中断禁止 #define I2C_SLVCR_IM_RXEND_Msk (0x01 << I2C_SLVCR_IM_RXEND_Pos) -#define I2C_SLVCR_IM_TXEND_Pos 1 //闁跨喐鏋婚幏鐑芥晸閺傘倖瀚归柨鐔告灮閹风兘鏁撻弬銈嗗閸楁瓕绶伴柨鐔活敎閿燂拷 +#define I2C_SLVCR_IM_TXEND_Pos 1 //发送完成中断禁止 #define I2C_SLVCR_IM_TXEND_Msk (0x01 << I2C_SLVCR_IM_TXEND_Pos) -#define I2C_SLVCR_IM_STADET_Pos 2 //闁跨喐鏋婚幏椋庡禃閺傘倖瀚归柨鐔虹哺绾攱瀚归崡姝岀钒闁跨喕顢滈敓锟� +#define I2C_SLVCR_IM_STADET_Pos 2 //检测到起始中断禁止 #define I2C_SLVCR_IM_STADET_Msk (0x01 << I2C_SLVCR_IM_STADET_Pos) -#define I2C_SLVCR_IM_STODET_Pos 3 //闁跨喐鏋婚幏椋庡禃闁扮绾ч惂鍛婂閸楁瓕绶伴柨鐔活敎閿燂拷 +#define I2C_SLVCR_IM_STODET_Pos 3 //检测到停止中断禁止 #define I2C_SLVCR_IM_STODET_Msk (0x01 << I2C_SLVCR_IM_STODET_Pos) -#define I2C_SLVCR_IM_RDREQ_Pos 4 //闁跨喐鏋婚幏鐑芥晸缁夊摜顣幏鐑芥晸閺傘倖瀚归柨鐔告灮閹风兘鏁撻弬銈嗗闁跨喎褰ㄩ弬顓熸灮閹烽攱顒� +#define I2C_SLVCR_IM_RDREQ_Pos 4 //接收到读请求中断禁止 #define I2C_SLVCR_IM_RDREQ_Msk (0x01 << I2C_SLVCR_IM_RDREQ_Pos) -#define I2C_SLVCR_IM_WRREQ_Pos 5 //闁跨喐鏋婚幏鐑芥晸缁夊摜顣幏宄板晸闁跨喐鏋婚幏鐑芥晸閺傘倖瀚归柨鐔峰建閺傤厽鏋婚幏閿嬵剾 +#define I2C_SLVCR_IM_WRREQ_Pos 5 //接收到写请求中断禁止 #define I2C_SLVCR_IM_WRREQ_Msk (0x01 << I2C_SLVCR_IM_WRREQ_Pos) -#define I2C_SLVCR_ADDR7b_Pos 16 //1 7娴ｅ秹鏁撻弬銈嗗閸р偓濡€崇础 0 10娴ｅ秹鏁撻弬銈嗗閸р偓濡€崇础 +#define I2C_SLVCR_ADDR7b_Pos 16 //1 7位地址模式 0 10位地址模式 #define I2C_SLVCR_ADDR7b_Msk (0x01 << I2C_SLVCR_ADDR7b_Pos) -#define I2C_SLVCR_ACK_Pos 17 //1 鎼存棃鏁撻弬銈嗗ACK 0 鎼存棃鏁撻弬銈嗗NACK +#define I2C_SLVCR_ACK_Pos 17 //1 应答ACK 0 应答NACK #define I2C_SLVCR_ACK_Msk (0x01 << I2C_SLVCR_ACK_Pos) -#define I2C_SLVCR_SLAVE_Pos 18 //1 闁跨喐甯存导娆愬濡€崇础 0 闁跨喐鏋婚幏鐑芥晸閺傘倖瀚瑰Ο鈥崇础 +#define I2C_SLVCR_SLAVE_Pos 18 //1 从机模式 0 主机模式 #define I2C_SLVCR_SLAVE_Msk (0x01 << I2C_SLVCR_SLAVE_Pos) -#define I2C_SLVCR_DEBOUNCE_Pos 19 //閸樺鏁撻弬銈嗗闁跨喐鏋婚幏铚傚▏闁跨喐鏋婚幏锟� +#define I2C_SLVCR_DEBOUNCE_Pos 19 //去抖动使能 #define I2C_SLVCR_DEBOUNCE_Msk (0x01 << I2C_SLVCR_DEBOUNCE_Pos) -#define I2C_SLVCR_ADDR_Pos 20 //闁跨喐甯存导娆愬闁跨喐鏋婚幏宄版絻 +#define I2C_SLVCR_ADDR_Pos 20 //从机地址 #define I2C_SLVCR_ADDR_Msk (0x3FF << I2C_SLVCR_ADDR_Pos) -#define I2C_SLVIF_RXEND_Pos 0 //闁跨喐鏋婚幏鐑芥晸閺傘倖瀚归柨鐔告灮閹风兘鏁撻弬銈嗗閸楃ǹ顎掗柨鐔活敎閹惧懏瀚归柨鐔峰建閿燂拷1闁跨喐鏋婚幏鐑芥晸閺傘倖瀚� +#define I2C_SLVIF_RXEND_Pos 0 //接收完成中断标志，写1清零 #define I2C_SLVIF_RXEND_Msk (0x01 << I2C_SLVIF_RXEND_Pos) -#define I2C_SLVIF_TXEND_Pos 1 //闁跨喐鏋婚幏鐑芥晸閺傘倖瀚归柨鐔告灮閹风兘鏁撻弬銈嗗閸楃ǹ顎掗柨鐔活敎閹惧懏瀚归柨鐔峰建閿燂拷1闁跨喐鏋婚幏鐑芥晸閺傘倖瀚� +#define I2C_SLVIF_TXEND_Pos 1 //发送完成中断标志，写1清零 #define I2C_SLVIF_TXEND_Msk (0x01 << I2C_SLVIF_TXEND_Pos) -#define I2C_SLVIF_STADET_Pos 2 //闁跨喐鏋婚幏椋庡禃閺傘倖瀚归柨鐔虹哺绾攱瀚归崡绋款€掗柨鐔活敎閹惧懏瀚归柨鐔峰建閿燂拷1闁跨喐鏋婚幏鐑芥晸閺傘倖瀚� +#define I2C_SLVIF_STADET_Pos 2 //检测到起始中断标志，写1清零 #define I2C_SLVIF_STADET_Msk (0x01 << I2C_SLVIF_STADET_Pos) -#define I2C_SLVIF_STODET_Pos 3 //闁跨喐鏋婚幏椋庡禃闁扮绾ч惂鍛婂閸楃ǹ顎掗柨鐔活敎閹惧懏瀚归柨鐔峰建閿燂拷1闁跨喐鏋婚幏鐑芥晸閺傘倖瀚� +#define I2C_SLVIF_STODET_Pos 3 //检测到停止中断标志，写1清零 #define I2C_SLVIF_STODET_Msk (0x01 << I2C_SLVIF_STODET_Pos) -#define I2C_SLVIF_RDREQ_Pos 4 //闁跨喐鏋婚幏鐑芥晸缁夊摜顣幏鐑芥晸閺傘倖瀚归柨鐔告灮閹风兘鏁撻弬銈嗗闁跨喎褰ㄩ弬顓熷敾閹峰嘲绻� +#define I2C_SLVIF_RDREQ_Pos 4 //接收到读请求中断标志 #define I2C_SLVIF_RDREQ_Msk (0x01 << I2C_SLVIF_RDREQ_Pos) -#define I2C_SLVIF_WRREQ_Pos 5 //闁跨喐鏋婚幏鐑芥晸缁夊摜顣幏宄板晸闁跨喐鏋婚幏鐑芥晸閺傘倖瀚归柨鐔峰建閺傤厽鍞婚幏宄扮箶 +#define I2C_SLVIF_WRREQ_Pos 5 //接收到写请求中断标志 #define I2C_SLVIF_WRREQ_Msk (0x01 << I2C_SLVIF_WRREQ_Pos) -#define I2C_SLVIF_ACTIVE_Pos 6 //slave 闁跨喐鏋婚幏閿嬫櫏 +#define I2C_SLVIF_ACTIVE_Pos 6 //slave 有效 #define I2C_SLVIF_ACTIVE_Msk (0x01 << I2C_SLVIF_ACTIVE_Pos) typedef struct @@ -988,7 +1593,7 @@ typedef struct __IO uint32_t CALIBEN; } ADC_TypeDef; -#define ADC_CTRL_CH0_Pos 0 //闁岸鏁撻弬銈嗗闁鏁撻弬銈嗗 +#define ADC_CTRL_CH0_Pos 0 //通道选中 #define ADC_CTRL_CH0_Msk (0x01 << ADC_CTRL_CH0_Pos) #define ADC_CTRL_CH1_Pos 1 #define ADC_CTRL_CH1_Msk (0x01 << ADC_CTRL_CH1_Pos) @@ -1004,20 +1609,20 @@ typedef struct #define ADC_CTRL_CH6_Msk (0x01 << ADC_CTRL_CH6_Pos) #define ADC_CTRL_CH7_Pos 7 #define ADC_CTRL_CH7_Msk (0x01 << ADC_CTRL_CH7_Pos) -#define ADC_CTRL_AVG_Pos 8 //0 1闁跨喕濞囩拠褎瀚归柨鐔告灮閹凤拷 1 2闁跨喕濞囩拠褎瀚归柨鐔告灮閹峰嘲褰囬獮鎶芥晸閺傘倖瀚归崐锟� 3 4闁跨喕濞囩拠褎瀚归柨鐔告灮閹峰嘲褰囬獮鎶芥晸閺傘倖瀚归崐锟� 7 8闁跨喕濞囩拠褎瀚归柨鐔告灮閹峰嘲褰囬獮鎶芥晸閺傘倖瀚归崐锟� 15 16闁跨喕濞囩拠褎瀚归柨鐔告灮閹峰嘲褰囬獮鎶芥晸閺傘倖瀚归崐锟� +#define ADC_CTRL_AVG_Pos 8 //0 1次采样 1 2次采样取平均值 3 4次采样取平均值 7 8次采样取平均值 15 16次采样取平均值 #define ADC_CTRL_AVG_Msk (0x0F << ADC_CTRL_AVG_Pos) #define ADC_CTRL_EN_Pos 12 #define ADC_CTRL_EN_Msk (0x01 << ADC_CTRL_EN_Pos) -#define ADC_CTRL_CONT_Pos 13 //Continuous conversion闁跨喐鏋婚幏宄板涧闁跨喐鏋婚幏鐑芥晸閺傘倖瀚归柨鐔告灮閹风兘鏁撴笟銉悏閺傘倖瀚归柨鐔告灮閹风兘鏁撻崣顐庡秵瀚归柨鐕傛嫹0 闁跨喐鏋婚幏鐑芥晸閺傘倖瀚规潪顒勬晸閺傘倖瀚归柨鐔告灮閹风柉娴嗛柨鐔告灮閹风兘鏁撻弬銈嗗閻濆﹪鏁撶徊濂RT娴ｅ秹鏁撻惃鍡氼啇閹风兘鏁撻弬銈嗗闁跨喖鍙洪敍鑸碉細椤忓孩瀚归柨鐕傛嫹 -#define ADC_CTRL_CONT_Msk (0x01 << ADC_CTRL_CONT_Pos) // 1 闁跨喐鏋婚幏鐑芥晸閺傘倖瀚规潪顒勬晸閺傘倖瀚归柨鐔告灮閹风兘鏁撻弬銈嗗闁跨喐褰幁銏″敾閹风兘鏁撻弬銈嗗闁跨喐鏋婚幏鐑芥晸闂冮浜烽幏鐑芥晸閺傘倖瀚归柨鐔活敎閹插瀚归柨鐔告灮閹风兘鏁撻弬銈嗗闁跨喐鏋婚幏鐑芥晸缁插ィART娴ｏ拷 -#define ADC_CTRL_TRIG_Pos 14 //鏉烆剟鏁撻弬銈嗗闁跨喐鏋婚幏鐑芥晸閺傘倖瀚归柨鐔告灮閹峰嘲绱￠柨鐔告灮閹凤拷0 闁跨喐鏋婚幏鐑芥晸閺傘倖瀚归柨鐔兼▉椤忓孩瀚归柨鐕傛嫹 1 PWM闁跨喐鏋婚幏鐑芥晸閺傘倖瀚� +#define ADC_CTRL_CONT_Pos 13 //Continuous conversion，只在软件启动模式下有效，0 单次转换，转换完成后START位自动清除停止转换 +#define ADC_CTRL_CONT_Msk (0x01 << ADC_CTRL_CONT_Pos) // 1 连续转换，启动后一直采样、转换，直到软件清除START位 +#define ADC_CTRL_TRIG_Pos 14 //转换触发方式：0 软件启动转换 1 PWM触发 #define ADC_CTRL_TRIG_Msk (0x01 << ADC_CTRL_TRIG_Pos) #define ADC_CTRL_CLKSRC_Pos 15 //0 VCO 1 HRC #define ADC_CTRL_CLKSRC_Msk (0x01 << ADC_CTRL_CLKSRC_Pos) #define ADC_CTRL_FIFOCLR_Pos 24 //[24] CH0_FIFO_CLR [25] CH1_FIFO_CLR ... [31] CH7_FIFO_CLR -#define ADC_CTRL_FIFOCLR_Msk (((uint32_t)0xFF) << ADC_CTRL_FIFOCLR_Pos) +#define ADC_CTRL_FIFOCLR_Msk (0xFFu << ADC_CTRL_FIFOCLR_Pos) -#define ADC_START_GO_Pos 0 //闁跨喐鏋婚幏鐑芥晸閺傘倖瀚归柨鐔告灮閹风兘鏁撴笟銉悏閺傘倖瀚归幏銏ゆ晸閸欘偓鎷�1闁跨喐鏋婚幏绋烡C闁跨喐鏋婚幏鐑芥晸閺傘倖瀚归柨鐔告灮閹风柉娴嗛柨鐔告灮閹风兘鏁撻弬銈嗗闁跨喕濡喊澶嬪闁跨喐鏋婚幏閿嬆佸蹇涙晸閺傘倖瀚规潪顒勬晸閺傘倖瀚归柨鐔告灮閹烽寮烽柨鐔稿复鐠囇勫闁跨喐鏋婚幏鐤箼闁跨喐鏋婚幏鐑芥晸閺傘倖瀚归幃鏍村墾閹风兘鏁撶紓鎼厜閹风兘鏁撴笟銉悏閺傘倖瀚归崡銈夋晸閺傘倖瀚归柨鐔告灮閹风兘鏁撻弬銈嗗閸愶拷0閸嬫粍顒汚DC鏉烆剟鏁撻弬銈嗗 +#define ADC_START_GO_Pos 0 //软件触发模式下，写1启动ADC采样和转换，在单次模式下转换完成后硬件自动清零，在扫描模式下必须软件写0停止ADC转换 #define ADC_START_GO_Msk (0x01 << ADC_START_GO_Pos) #define ADC_START_BUSY_Pos 4 #define ADC_START_BUSY_Msk (0x01 << ADC_START_BUSY_Pos) @@ -1085,16 +1690,15 @@ typedef struct #define ADC_IE_CH7HFULL_Pos 30 #define ADC_IE_CH7HFULL_Msk (0x01 << ADC_IE_CH7HFULL_Pos) #define ADC_IE_CH7FULL_Pos 31 -//#define ADC_IE_CH7FULL_Msk (0x01 << ADC_IE_CH7FULL_Pos) 闁跨喐鏋婚幏鐑芥晸閺傘倖瀚归柨鐔告灮閹风兘鏁撻弬銈嗗闁跨喕濮ら敍锟� integer operation result is out of range -#define ADC_IE_CH7FULL_Msk ((uint32_t)0x01 << ADC_IE_CH7FULL_Pos) +#define ADC_IE_CH7FULL_Msk (0x01u << ADC_IE_CH7FULL_Pos) -#define ADC_IF_CH0EOC_Pos 0 //閸愶拷1闁跨喐鏋婚幏鐑芥晸閺傘倖瀚� +#define ADC_IF_CH0EOC_Pos 0 //写1清零 #define ADC_IF_CH0EOC_Msk (0x01 << ADC_IF_CH0EOC_Pos) -#define ADC_IF_CH0OVF_Pos 1 //閸愶拷1闁跨喐鏋婚幏鐑芥晸閺傘倖瀚� +#define ADC_IF_CH0OVF_Pos 1 //写1清零 #define ADC_IF_CH0OVF_Msk (0x01 << ADC_IF_CH0OVF_Pos) -#define ADC_IF_CH0HFULL_Pos 2 //閸愶拷1闁跨喐鏋婚幏鐑芥晸閺傘倖瀚� +#define ADC_IF_CH0HFULL_Pos 2 //写1清零 #define ADC_IF_CH0HFULL_Msk (0x01 << ADC_IF_CH0HFULL_Pos) -#define ADC_IF_CH0FULL_Pos 3 //閸愶拷1闁跨喐鏋婚幏鐑芥晸閺傘倖瀚� +#define ADC_IF_CH0FULL_Pos 3 //写1清零 #define ADC_IF_CH0FULL_Msk (0x01 << ADC_IF_CH0FULL_Pos) #define ADC_IF_CH1EOC_Pos 4 #define ADC_IF_CH1EOC_Msk (0x01 << ADC_IF_CH1EOC_Pos) @@ -1153,9 +1757,9 @@ typedef struct #define ADC_IF_CH7FULL_Pos 31 #define ADC_IF_CH7FULL_Msk (0x01 << ADC_IF_CH7FULL_Pos) -#define ADC_STAT_EOC_Pos 0 //閸愶拷1闁跨喐鏋婚幏鐑芥晸閺傘倖瀚� +#define ADC_STAT_EOC_Pos 0 //写1清零 #define ADC_STAT_EOC_Msk (0x01 << ADC_STAT_EOC_Pos) -#define ADC_STAT_OVF_Pos 1 //闁跨喐鏋婚幏鐑芥晸閺傘倖瀚归柨鐔稿祹鐎靛嫯鎻幏鐑芥晸閺傘倖瀚归柨鐔告灮閹风兘鏁撻敓锟� +#define ADC_STAT_OVF_Pos 1 //读数据寄存器清除 #define ADC_STAT_OVF_Msk (0x01 << ADC_STAT_OVF_Pos) #define ADC_STAT_HFULL_Pos 2 #define ADC_STAT_HFULL_Msk (0x01 << ADC_STAT_HFULL_Pos) @@ -1164,23 +1768,23 @@ typedef struct #define ADC_STAT_EMPTY_Pos 4 #define ADC_STAT_EMPTY_Msk (0x01 << ADC_STAT_EMPTY_Pos) -#define ADC_CTRL1_RIN_Pos 4 //闁跨喐鏋婚幏鐑芥晸閺傘倖瀚归柨鐔封偓鐔稿闁跨喐鏋婚幏锟�0 闁跨喐鏋婚幏鐑芥晸閺傘倖瀚归柨鐕傛嫹 1 105K 2 90K 3 75K 4 60K 5 45K 6 30K 7 15K +#define ADC_CTRL1_RIN_Pos 4 //输入阻抗：0 无穷大 1 105K 2 90K 3 75K 4 60K 5 45K 6 30K 7 15K #define ADC_CTRL1_RIN_Msk (0x07 << ADC_CTRL1_RIN_Pos) -#define ADC_CTRL2_RESET_Pos 0 //闁跨喐鏋婚幏鐑芥晸鐞涙顣幏鐤熅闁跨喐鏋婚幏铚傜秴 +#define ADC_CTRL2_RESET_Pos 0 //数字电路复位 #define ADC_CTRL2_RESET_Msk (0x01 << ADC_CTRL2_RESET_Pos) -#define ADC_CTRL2_ADCEVCM_Pos 1 //ADC External VCM闁跨喐鏋婚幏绋烡C闁跨喐鏋婚幏绋癎A闁跨喐鏋婚幏鐑芥晸閺傘倖瀚归柨鐔惰寧閿濆繑瀚归柨鐔哄珱缁愭牑妲勯幏鐑芥晸閿燂拷 +#define ADC_CTRL2_ADCEVCM_Pos 1 //ADC External VCM，ADC与PGA输出共模电平选择 #define ADC_CTRL2_ADCEVCM_Msk (0x01 << ADC_CTRL2_ADCEVCM_Pos) -#define ADC_CTRL2_PGAIVCM_Pos 2 //PGA Internal VCM闁跨喐鏋婚幏绋癎A闁跨喐鏋婚幏鐑芥晸鐠囶偄鍙″Ο锟犳晸閺傘倖瀚归獮鎶解偓澶愭晸閺傘倖瀚� +#define ADC_CTRL2_PGAIVCM_Pos 2 //PGA Internal VCM，PGA输入共模电平选择 #define ADC_CTRL2_PGAIVCM_Msk (0x01 << ADC_CTRL2_PGAIVCM_Pos) #define ADC_CTRL2_PGAGAIN_Pos 3 //0 25.1dB 1 21.6dB 2 11.1dB 3 3.5dB 4 0dB(1.8V) 5 -2.9dB 6 -5.3dB #define ADC_CTRL2_PGAGAIN_Msk (0x07 << ADC_CTRL2_PGAGAIN_Pos) -#define ADC_CTRL2_REFPOUT_Pos 23 //1 ADC 闁跨喕濡拠褎瀚� 1.2V REFP闁跨喐鏋婚幏宄板竾闁跨喐鏋婚幏鐑芥晸閺傘倖瀚归柨鐔告灮閹烽宕扮缓宀碏P闁跨喐鏋婚幏鐑芥晸閼存熬缍囬幏鐑芥晸閺傘倖瀚归柨鐔诲Ν鐠囇勫闁跨喐鏋婚幏鐑芥晸閺傘倖瀚归柨鐔告灮閹风兘鏁撻弬銈嗗闁跨喐鏋婚幏鐤洣1.2V闁跨喕袙闁墽EFP閺冨爼鏁撻弬銈嗗閻線鏁撶紓瀛樺敾閹凤拷 +#define ADC_CTRL2_REFPOUT_Pos 23 //1 ADC 内部 1.2V REFP电压输出到外部REFP引脚，用于测量，或在需要1.2V外部REFP时节省成本 #define ADC_CTRL2_REFPOUT_Msk (0x01 << ADC_CTRL2_REFPOUT_Pos -#define ADC_CTRL2_CLKDIV_Pos 24 //閺冨爼鏁撻幒銉ュ殩閹风兘顣堕柨鐔告灮閹峰嘲褰ч柨鐔告灮閹烽攱妞傞柨鐔告灮閹烽攱绨稉绡怰C閺冨爼鏁撻弬銈嗗閺侊拷 +#define ADC_CTRL2_CLKDIV_Pos 24 //时钟分频，只在时钟源为HRC时有效 #define ADC_CTRL2_CLKDIV_Msk (0x1F << ADC_CTRL2_CLKDIV_Pos) #define ADC_CTRL2_PGAVCM_Pos 29 -#define ADC_CTRL2_PGAVCM_Msk (((uint32_t)0x07) << ADC_CTRL2_PGAVCM_Pos) +#define ADC_CTRL2_PGAVCM_Msk (0x07u << ADC_CTRL2_PGAVCM_Pos) #define ADC_CALIBSET_OFFSET_Pos 0 #define ADC_CALIBSET_OFFSET_Msk (0x1FF << ADC_CALIBSET_OFFSET_Pos) @@ -1194,17 +1798,17 @@ typedef struct typedef struct { - __IO uint32_t MODE; //0 闁跨喐鏋婚幏鐑解偓姘佸蹇涙晸閺傘倖瀚笰闁跨喐鏋婚幏绋￠柨鐔告灮閹风柉鐭鹃柨鐔告灮閹风兘鏁撻弬銈嗗闁跨喐鏋婚幏鐑芥晸閺傘倖瀚归柨鐔告灮閹凤拷 - //1 闁跨喐鏋婚幏鐑芥晸閺傘倖瀚瑰Ο鈥崇础闁跨喐鏋婚幏绋熼柨鐔告灮閹风ā闁跨喐鏋婚幏鐤熅闁跨喐鏋婚幏鐑芥晸閺傘倖瀚归柨鐔告灮閹风兘鏁撶徊鍢怰A闁跨喐鏋婚幏绋↖GHA闁跨喐鏋婚幏鐑芥晸閻欌槄缍囬幏绋＄捄顖炴晸閺傘倖瀚归柨鐔告灮閹风兘鏁撶槐姝岀熅闁跨喐鏋婚幏鐑芥晸閺傘倖瀚归柨鐔告灮閹风兘鏁撻弬銈嗗閸犳崘鎻幏鐑芥晸閺傘倖瀚归柨鐔烘たZA闁跨喐鏋婚幏绋B闁跨喐鏋婚幏鐑芥晸閺傘倖瀚笰闁跨喐鏋婚幏绋＄捄顖炴晸閺傘倖瀚归柨鐔告灮閹风兘鏁撻弬銈嗗闁跨喐鏋婚幏鐑芥晸閺傘倖瀚归惉銉╂晸缂佺偞鍞婚幏鐑芥晸閿燂拷 - //2 闁跨喐鏋婚幏鐑芥晸閺傘倖瀚瑰Ο鈥崇础闁跨喐鏋婚幏宄版倱闁跨喐鏋婚幏鐑解偓姘佸蹇涙晸閺傘倖瀚归柨鐔告灮閹疯渹绔撮柨鐔告灮閹风兘鏁撻弬銈嗗闁跨喕濡悮瀛樺闁跨喓娈曠拋瑙勫閸嬫粍顒� - //3 闁跨喓娈曠粵瑙勫濡€崇础闁跨喐鏋婚幏绋熼柨鐔告灮閹风ā闁跨喐鏋婚幏鐤熅闁跨喐鏋婚幏鐑芥晸閺傘倖瀚归柨鐔告灮閹风兘鏁撻弬銈嗗闁跨喐鏋婚幏鐑芥晸閺傘倖瀚归柨鐔告灮閹风兘鏁撻弬銈嗗闁跨喐鏋婚幏鐑芥晸閺傘倖瀚归柨鐔告灮閹风兘鏁撻弬銈嗗闁跨喕濡拠褎瀚归柨鐔告灮閹疯渹绔撮柨鐔告灮閹风兘鏁撻弬銈嗗闁跨喐鏋婚幏鐑芥晸閺傘倖瀚归柨鐔告灮閹风兘鏁撻弬銈嗗閸愩垽鏁撻弬銈嗗閻╂挳鏁撻弬銈嗗闁跨喐鏋婚幏鐑芥晸閺傘倖瀚归柨鐔稿疆娴兼瑦瀚归柨鐔告灮閹风兘鏁撻悪锛勵暜閹峰嘲绱￠柨鐔告灮閹风兘鏁撻幓顓濈串閹风兘鏁撻敓锟� - //4 闁跨喓娈曠粔棰佺串閹风兘鏁撻弬銈嗗濡€崇础闁跨喐鏋婚幏鐑芥晸閻ㄥ棛顒查幏閿嬆佸蹇涙晸闁板吀绱幏鐑芥晸閺傘倖瀚瑰Ο鈥崇础闁跨喐鏋婚幏鐑芥晸濡楁梻灏ㄩ幏锟� + __IO uint32_t MODE; //0 普通模式，A、B两路输出互相独立 + //1 互补模式，A、B两路输出都由PERA、HIGHA控制，B路输出与A路输出极性相反，且DZA、DZB控制A、B路输出上升沿推迟时间 + //2 单次模式，同普通模式，但一个周期后自动停止 + //3 对称模式，A、B两路输出互相独立，以两个计数周期产生一个波形输出周期，分辨率提升一倍、频率降低一倍 + //4 对称互补模式，对称模式和互补模式的综合 - __IO uint32_t PERA; //[15:0] 闁跨喐鏋婚幏鐑芥晸閺傘倖瀚� + __IO uint32_t PERA; //[15:0] 周期 - __IO uint32_t HIGHA; //[15:0] 闁跨喓顏喊澶嬪楠炴娊鏁撻弬銈嗗闁跨喐鏋婚幏閿嬫闁跨喐鏋婚幏锟� + __IO uint32_t HIGHA; //[15:0] 高电平持续时长 - __IO uint32_t DZA; //[9:0] 闁跨喐鏋婚幏鐑芥晸閺傘倖瀚归柨鐔告灮閹风兘鏁撻弬銈嗗闁跨喐鏋婚幏鐑芥晸閺傘倖瀚归柨鐔告灮閹风兘鏁撻悪锛勵劜閹烽攱妞傞柨鐔告灮閹风兘鏁撻弬銈嗗闁跨喐鏋婚幏鐑芥晸閺傘倖瀚圭亸蹇涙晸閺傘倖瀚笻IGHA + __IO uint32_t DZA; //[9:0] 死区，即上升沿推迟时长，必须小于HIGHA __IO uint32_t PERB; @@ -1212,7 +1816,7 @@ typedef struct __IO uint32_t DZB; - __IO uint32_t INIOUT; //Init Output level闁跨喐鏋婚幏鐑芥晸閺傘倖瀚规慨瀣晸閺傘倖瀚归柨鐔告灮閹风兘鏁撻悪鈽呮嫹 + __IO uint32_t INIOUT; //Init Output level，初始输出电平 } PWM_TypeDef; #define PWM_INIOUT_PWMA_Pos 0 @@ -1244,7 +1848,7 @@ typedef struct uint32_t RESERVED[3]; - __IO uint32_t HALT; //閸掑綊鏁撻弬銈嗗闁跨喐鏋婚幏鐑芥晸閺傘倖瀚� + __IO uint32_t HALT; //刹车控制 __IO uint32_t CHEN; @@ -1272,7 +1876,7 @@ typedef struct #define PWMG_ADTRG_VALUE_Pos 0 #define PWMG_ADTRG_VALUE_Msk (0xFFFF << PWMG_ADTRG0A_VALUE_Pos) -#define PWMG_ADTRG_EVEN_Pos 16 //1 閸嬪爼鏁撻弬銈嗗闁跨喐鏋婚幏鐑芥晸閺傘倖瀚归柨鐔告灮閹烽攱鏅� 0 闁跨喐鏋婚幏鐑芥晸閺傘倖瀚归柨鐔告灮閹风兘鏁撻弬銈嗗闁跨喐鏋婚幏閿嬫櫏 +#define PWMG_ADTRG_EVEN_Pos 16 //1 偶数周期生效 0 奇数周期生效 #define PWMG_ADTRG_EVEN_Msk (0x01 << PWMG_ADTRG0A_EVEN_Pos) #define PWMG_ADTRG_EN_Pos 17 #define PWMG_ADTRG_EN_Msk (0x01 << PWMG_ADTRG0A_EN_Pos) @@ -1291,13 +1895,13 @@ typedef struct #define PWMG_HALT_PWM4_Msk (0x01 << PWMG_HALT_PWM4_Pos) #define PWMG_HALT_PWM5_Pos 6 #define PWMG_HALT_PWM5_Msk (0x01 << PWMG_HALT_PWM5_Pos) -#define PWMG_HALT_STOPCNT_Pos 7 //1 閸掑綊鏁撻弬銈嗗閺冨爼鏁撻弬銈嗗PWM闁跨喐鏋婚幏鐑芥晸閺傘倖瀚归柨鐔告灮閹风兘鏁撻弬銈嗗闁跨喎顫曢敍灞戒粻濮濄垽鏁撻弬銈嗗闁跨喐鏋婚幏锟� 0 閸掑綊鏁撻弬銈嗗閺冨爼鏁撻弬銈嗗PWM闁跨喐鏋婚幏鐑芥晸閺傘倖瀚归柨鐔告灮閹风兘鏁撻弬銈嗗闁跨喐鏋婚幏鐑芥晸閺傘倖瀚归柨鐔告灮閹凤拷 +#define PWMG_HALT_STOPCNT_Pos 7 //1 刹车时将PWM计数器清零，停止计数 0 刹车时，PWM计数器继续计数 #define PWMG_HALT_STOPCNT_Msk (0x01 << PWMG_HALT_STOPCNT_Pos) -#define PWMG_HALT_INLVL_Pos 8 //1 閸掑綊鏁撻弬銈嗗闁跨喐鏋婚幏鐑芥晸閺傘倖瀚归崣鈺呮晸閻欌剝鏋婚幏鐑芥晸閸欘偓鎷� +#define PWMG_HALT_INLVL_Pos 8 //1 刹车输入高电平有效 #define PWMG_HALT_INLVL_Msk (0x01 << PWMG_HALT_INLVL_Pos) -#define PWMG_HALT_OUTLVL_Pos 9 //1 閸掑綊鏁撻弬銈嗗闁跨喐鏋婚幏鐑芥晸閺傘倖瀚归柨鐔告灮閹风兘鏁撻弬銈嗗闁跨喐鏋婚幏宄板渐闁跨喓瀚涢敓锟� +#define PWMG_HALT_OUTLVL_Pos 9 //1 刹车过程中输出高电平 #define PWMG_HALT_OUTLVL_Msk (0x01 << PWMG_HALT_OUTLVL_Pos) -#define PWMG_HALT_STAT_Pos 10 //1 闁跨喐鏋婚幏鐑芥晸閺傘倖瀚归崚褰掓晸閺傘倖瀚� +#define PWMG_HALT_STAT_Pos 10 //1 正在刹车 #define PWMG_HALT_STAT_Msk (0x01 << PWMG_HALT_STAT_Pos) #define PWMG_CHEN_PWM0A_Pos 0 @@ -1533,11 +2137,11 @@ typedef struct { __IO uint32_t EN; //[0] ENABLE - __IO uint32_t IE; //閸欘亪鏁撻弬銈嗗娑擄拷1閺冨爼鏁撻弬銈嗗IF[CHx]闁跨喐鏋婚幏绋A闁跨喐鏋婚幏鐑芥晸閺傘倖瀚归柨鐔告灮閹风兘鏁撶紒鐐村敾閹风兘鏁撻弬銈嗗姒ф瑩鏁撴潪鍖℃嫹1闁跨喐鏋婚幏鐑芥晸閺傘倖瀚归柨鐔告灮閹疯渹绔撮惄鎾晸閺傘倖瀚归柨鐔告灮閹风兘鏁撻弬銈嗗0 + __IO uint32_t IE; //只有为1时，IF[CHx]在DMA传输结束时才能变为1，否则将一直保持在0 - __IO uint32_t IM; //闁跨喐鏋婚幏铚傝礋1閺冨爼鏁撻弬銈嗗闁跨喐鏋婚幏铚傚▏IF[CHx]娑擄拷1闁跨喐鏋婚幏绌宮a_int娑旂喖鏁撻弬銈嗗闁跨喐鏋婚幏鐑芥晸閺傘倖瀚归崥顕€鏁撻敓锟�1 + __IO uint32_t IM; //当为1时，即使IF[CHx]为1，dma_int也不会因此变1 - __IO uint32_t IF; //閸愶拷1闁跨喐鏋婚幏鐑芥晸閺傘倖瀚� + __IO uint32_t IF; //写1清零 uint32_t RESERVED[12]; @@ -1549,23 +2153,23 @@ typedef struct __IO uint32_t SRC; - __IO uint32_t SRCSGADDR1; //閸欘亪鏁撻弬銈嗗Scatter Gather濡€崇础闁跨喐鏋婚幏铚傚▏闁跨喐鏋婚幏锟� + __IO uint32_t SRCSGADDR1; //只在Scatter Gather模式下使用 - __IO uint32_t SRCSGADDR2; //閸欘亪鏁撻弬銈嗗Scatter Gather濡€崇础闁跨喐鏋婚幏铚傚▏闁跨喐鏋婚幏锟� + __IO uint32_t SRCSGADDR2; //只在Scatter Gather模式下使用 - __IO uint32_t SRCSGADDR3; //閸欘亪鏁撻弬銈嗗Scatter Gather濡€崇础闁跨喐鏋婚幏铚傚▏闁跨喐鏋婚幏锟� + __IO uint32_t SRCSGADDR3; //只在Scatter Gather模式下使用 - __IO uint32_t SRCSGLEN; //閸欘亪鏁撻弬銈嗗Scatter Gather濡€崇础闁跨喐鏋婚幏铚傚▏闁跨喐鏋婚幏锟� + __IO uint32_t SRCSGLEN; //只在Scatter Gather模式下使用 __IO uint32_t DST; - __IO uint32_t DSTSGADDR1; //閸欘亪鏁撻弬銈嗗Scatter Gather濡€崇础闁跨喐鏋婚幏铚傚▏闁跨喐鏋婚幏锟� + __IO uint32_t DSTSGADDR1; //只在Scatter Gather模式下使用 - __IO uint32_t DSTSGADDR2; //閸欘亪鏁撻弬銈嗗Scatter Gather濡€崇础闁跨喐鏋婚幏铚傚▏闁跨喐鏋婚幏锟� + __IO uint32_t DSTSGADDR2; //只在Scatter Gather模式下使用 - __IO uint32_t DSTSGADDR3; //閸欘亪鏁撻弬銈嗗Scatter Gather濡€崇础闁跨喐鏋婚幏铚傚▏闁跨喐鏋婚幏锟� + __IO uint32_t DSTSGADDR3; //只在Scatter Gather模式下使用 - __IO uint32_t DSTSGLEN; //閸欘亪鏁撻弬銈嗗Scatter Gather濡€崇础闁跨喐鏋婚幏铚傚▏闁跨喐鏋婚幏锟� + __IO uint32_t DSTSGLEN; //只在Scatter Gather模式下使用 uint32_t RESERVED[4]; } CH[3]; @@ -1622,16 +2226,16 @@ typedef struct #define DMA_IF_CH7_Pos 7 #define DMA_IF_CH7_Msk (0x01 << DMA_IF_CH7_Pos) -#define DMA_CR_LEN_Pos 0 //闁跨喐鏋婚幏鐑解偓姘舵晸閺傘倖瀚归柨鐔告灮閹风兘鏁撻弬銈嗗闁跨喐婢冪粵瑙勫闁跨喖銈洪敐蹇斿0闁跨喐鏋婚幏宄扮安1闁跨喕顢滈懞鍌︾秶閹风兘鏁撻弬銈嗗闁跨噦鎷�4096闁跨喕顢滈弬銈嗗 +#define DMA_CR_LEN_Pos 0 //此通道传输总长度，0对应1字节，最大4096字节 #define DMA_CR_LEN_Msk (0xFFF << DMA_CR_LEN_Pos) #define DMA_CR_RXEN_Pos 16 #define DMA_CR_RXEN_Msk (0x01 << DMA_CR_RXEN_Pos) #define DMA_CR_TXEN_Pos 17 #define DMA_CR_TXEN_Msk (0x01 << DMA_CR_TXEN_Pos) -#define DMA_CR_AUTORE_Pos 18 //Auto Restart, 闁岸鏁撻弬銈嗗闁跨喕濡潏鐐闁跨喐鏋婚幏鐑芥晸閺傘倖瀚归悵濠囨晸閺傘倖瀚瑰▎鐘绘晸閺傘倖瀚规潻婊堟晸閺傘倖瀚归柨鐔告灮閹风兘鏁撻弬銈嗗闁跨噦鎷� +#define DMA_CR_AUTORE_Pos 18 //Auto Restart, 通道在传输完成后，是否自动重新启动 #define DMA_CR_AUTORE_Msk (0x01 << DMA_CR_AUTORE_Pos) -#define DMA_AM_SRCAM_Pos 0 //Address Mode 0 闁跨喐鏋婚幏宄版絻闁跨喐鏆€鐠佽瀚� 1 闁跨喐鏋婚幏宄版絻闁跨喐鏋婚幏鐑芥晸閺傘倖瀚� 2 scatter gather濡€崇础 +#define DMA_AM_SRCAM_Pos 0 //Address Mode 0 地址固定 1 地址递增 2 scatter gather模式 #define DMA_AM_SRCAM_Msk (0x03 << DMA_AM_SRCAM_Pos) #define DMA_AM_DSTAM_Pos 8 #define DMA_AM_DSTAM_Msk (0x03 << DMA_AM_DSTAM_Pos) @@ -1646,7 +2250,7 @@ typedef struct __I uint32_t SR; //Status Register - __I uint32_t IF; //Interrupt Flag + __I uint32_t IF; //Interrupt Flag，读取清零 __IO uint32_t IE; //Interrupt Enable @@ -1658,51 +2262,41 @@ typedef struct uint32_t RESERVED2[3]; - __I uint32_t ALC; //Arbitration Lost Capture, 闁跨喎濮憗浣筋啇閹峰嘲銇戦柨鐔告灮閹烽攱宕� + __I uint32_t ALC; //Arbitration Lost Capture, 仲裁丢失捕捉 - __I uint32_t ECC; //Error code capture, 闁跨喐鏋婚幏鐑芥晸閺傘倖瀚归柨鐔告灮閹烽攱鐧岄煫璇ф嫹 + __I uint32_t ECC; //Error code capture, 错误代码捕捉 - __IO uint32_t EWLIM; //Error Warning Limit, 闁跨喐鏋婚幏鐑芥晸鐟楃喐濮ら幘鍛闁跨喐鏋婚幏鐑芥晸閺傘倖瀚� + __IO uint32_t EWLIM; //Error Warning Limit, 错误报警限制 - __IO uint32_t RXERR; //RX闁跨喐鏋婚幏鐑芥晸閺傘倖瀚归柨鐔告灮閹风兘鏁撻敓锟� + __IO uint32_t RXERR; //RX错误计数 - __IO uint32_t TXERR; //TX闁跨喐鏋婚幏鐑芥晸閺傘倖瀚归柨鐔告灮閹风兘鏁撻敓锟� + __IO uint32_t TXERR; //TX错误计数 union { - struct //闁跨喕濡棃鈺傚娴ｅ秵妞傞柨鐔哄嵆鐠佽瀚归崘娆撴晸閺傘倖瀚归柨鐔告灮閹风兘鏁撻弬銈嗗闁跨喐鏋婚幏鐑芥晸閺傘倖瀚瑰Ο鈥崇础闁跨喖鎽拠褎瀚归柨鐔哄嵆閸戙倖瀚归柨鐔告灮閹凤拷 - { - __IO uint32_t ACR[4]; //Acceptance Check Register, 闁跨喐鏋婚幏鐑芥晸缁夌ǹ鐦庢潏鐐闁跨喐鏋婚幏锟� + struct + { //在复位时可读写，正常工作模式下不可访问 + __IO uint32_t ACR[4]; //Acceptance Check Register, 验收寄存器 - __IO uint32_t AMR[4]; //Acceptance Mask Register, 闁跨喐鏋婚幏鐑芥晸閺傘倖瀚归柨鐔告灮閹风兘鏁撴潪鍨槑鏉堢偓瀚归柨鐔告灮閹风兘鏁撻弬銈嗗闁跨喐鏋婚幏宄扮安娴ｅ秴鍟�0闁跨喐鏋婚幏绋〥闁跨喐鏋婚幏鐑芥晸閺傘倖瀚归柨鐔告灮閹风兘鏁撻弬銈嗗閸楃姵濯烽柨鐔告灮閹风兘鏁撻悪掳鍎婚幏鐑芥晸閿燂拷 + __IO uint32_t AMR[4]; //Acceptance Mask Register, 验收屏蔽寄存器；对应位写0，ID必须和验收寄存器匹配 uint32_t RESERVED[5]; } FILTER; - union //闁跨喐鏋婚幏鐑芥晸閺傘倖瀚归柨鐔告灮閹风兘鏁撻弬銈嗗闁跨喐鏋婚幏閿嬆佸蹇涙晸闁炬澘褰茬拋瑙勫閸愭瑩鏁撻弬銈嗗闁跨喐鏋婚幏铚傜秴閺冨爼鏁撻弬銈嗗闁跨喓鍗抽崙銈嗗闁跨喐鏋婚幏锟� - { - struct - { - __O uint32_t INFO; - - __O uint32_t DATA[12]; - } TXFRAME; + struct + { //在正常工作模式下可读写，复位时不可访问 + __IO uint32_t INFO; - struct - { - __I uint32_t INFO; - - __I uint32_t DATA[12]; - } RXFRAME; - }; + __IO uint32_t DATA[12]; + } FRAME; }; __I uint32_t RMCNT; //Receive Message Count uint32_t RESERVED3[66]; - struct //TXFRAME闁跨喍鑼庣拋瑙勫闁跨喐甯撮崠鈩冨 - { + struct + { //TXFRAME的读接口 __I uint32_t INFO; __I uint32_t DATA[12]; @@ -1713,14 +2307,12 @@ typedef struct #define CAN_CR_RST_Msk (0x01 << CAN_CR_RST_Pos) #define CAN_CR_LOM_Pos 1 //Listen Only Mode #define CAN_CR_LOM_Msk (0x01 << CAN_CR_LOM_Pos) -#define CAN_CR_STM_Pos 2 //Self Test Mode, 闁跨喐鏋婚幏閿嬆佸蹇涙晸闁炬壆銆嬮幏铚傚▏濞岋繝鏁撻弬銈嗗鎼存棃鏁撻弬銈嗗CAN闁跨喐鏋婚幏鐑芥晸閺傘倖瀚归柨鐔告灮閹疯渹绡冮柨鐔告灮閹风兘鏁撻惃鍡樺灇閻у憡瀚归柨鐔告灮閹风兘鏁撻弬銈嗗 +#define CAN_CR_STM_Pos 2 //Self Test Mode, 此模式下即使没有应答，CAN控制器也可以成功发送 #define CAN_CR_STM_Msk (0x01 << CAN_CR_STM_Pos) -#define CAN_CR_AFM_Pos 3 //Acceptance Filter Mode, 1 闁跨喐鏋婚幏鐑芥晸閺傘倖瀚归柨鐔告灮閹风兘鏁撻弬銈嗗闁跨喎澹欑拠褎瀚归柨鐔告灮閹风兘鏁撻弬銈嗗32娴ｅ秹鏁撻弬銈嗗 0 闁跨喐鏋婚幏鐑芥晸閺傘倖瀚归柨鐔告灮閹风兘鏁撻弬銈嗗闁跨喎澹欑拠褎瀚归柨鐔告灮閹风兘鏁撻弬銈嗗16娴ｅ秹鏁撻弬銈嗗 +#define CAN_CR_AFM_Pos 3 //Acceptance Filter Mode, 1 单个验收滤波器（32位） 0 两个验收滤波器（16位） #define CAN_CR_AFM_Msk (0x01 << CAN_CR_AFM_Pos) -#define CAN_CR_SLEEP_Pos 4 //閸愶拷1闁跨喐鏋婚幏鐑芥晸閺傘倖瀚归惈锟犳晸閺傘倖瀚瑰Ο鈥崇础闁跨喐鏋婚幏鐑芥晸閺傘倖瀚归柨鐔告灮閹风兘鏁撶粩顓熸た閸斻劑鏁撻弬銈嗗闁跨喎褰ㄧ拋瑙勫閺冨爼鏁撻弬銈嗗闁跨喓鐛ょ拠褎瀚归柨鐔烘畷鐠佽瀚归柨鐔告灮閹风兘鏁撻弬銈嗗闁跨喕濞囬敓锟� +#define CAN_CR_SLEEP_Pos 4 //写1进入睡眠模式，有总线活动或中断时唤醒并自动清零此位 #define CAN_CR_SLEEP_Msk (0x01 << CAN_CR_SLEEP_Pos) -#define CAN_CR_DMAEN_Pos 5 -#define CAN_CR_DMAEN_Msk (0x01 << CAN_CR_DMAEN_Pos) #define CAN_CMD_TXREQ_Pos 0 //Transmission Request #define CAN_CMD_TXREQ_Msk (0x01 << CAN_CMD_TXREQ_Pos) @@ -1733,38 +2325,38 @@ typedef struct #define CAN_CMD_SRR_Pos 4 //Self Reception Request #define CAN_CMD_SRR_Msk (0x01 << CAN_CMD_SRR_Pos) -#define CAN_SR_RXDA_Pos 0 //Receive Data Available闁跨喐鏋婚幏鐑芥晸閺傘倖瀚归柨鐔告灮閹风éIFO闁跨喐鏋婚幏鐑芥晸閺傘倖瀚归柨鐔告灮閹风兘鏁撻弬銈嗗闁跨喐鏋婚幏閿嬩紖闁跨喐鏋婚幏鐑芥晸閻ㄥ棜顔愰幏宄板絿 +#define CAN_SR_RXDA_Pos 0 //Receive Data Available，接收FIFO中有完整消息可以读取 #define CAN_SR_RXDA_Msk (0x01 << CAN_SR_RXDA_Pos) -#define CAN_SR_RXOV_Pos 1 //Receive FIFO Overrun闁跨喐鏋婚幏鐑芥晸闁剧増鏋婚幏鐑芥晸缁夊摜顣幏鐑芥晸閺傘倖瀚归幁顖炴晸閺傘倖瀚归柨鐔诲Ν閺傘倖瀚归柨鐔告灮閹风éIFO闁跨喐鏋婚幏鐑芥晸閺傘倖瀚归柨鐔告灮閹风兘鏁撻弬銈嗗闁跨喐鏋婚幏锟� +#define CAN_SR_RXOV_Pos 1 //Receive FIFO Overrun，新接收的信息由于接收FIFO已满而丢掉 #define CAN_SR_RXOV_Msk (0x01 << CAN_SR_RXOV_Pos) -#define CAN_SR_TXBR_Pos 2 //Transmit Buffer Release闁跨喐鏋婚幏锟�0 闁跨喐鏋婚幏鐑芥晸閼哄倽鎻幏鐑芥晸閺傘倖瀚归崜宥夋晸閺傘倖瀚规慨鍡涙晸閺傘倖瀚归崑婊堟晸閺傘倖瀚归柨鐔告灮閹风柉鐦柨鐔告灮閹风兘鏁撻崣顐ユ彧閹烽顣遍柨鐔告灮閹风兘鏁撴潏鍐挎嫹 1 闁跨喐鏋婚幏鐑芥晸閺傘倖瀚归崘娆撴晸閺傘倖瀚归柨鐔兼應绾板瀚归柨鐔告灮閹烽攱浼呴柨鐔告灮閹风兘鏁撻弬銈嗗 +#define CAN_SR_TXBR_Pos 2 //Transmit Buffer Release，0 正在处理前面的发送，现在不能写新的消息 1 可以写入新的消息发送 #define CAN_SR_TXBR_Msk (0x01 << CAN_SR_TXBR_Pos) -#define CAN_SR_TXOK_Pos 3 //Transmit OK闁跨喐鏋婚幏绌漸ccessfully completed +#define CAN_SR_TXOK_Pos 3 //Transmit OK，successfully completed #define CAN_SR_TXOK_Msk (0x01 << CAN_SR_TXOK_Pos) -#define CAN_SR_RXBUSY_Pos 4 //Receive Busy闁跨喐鏋婚幏鐑芥晸閺傘倖瀚归柨鐔诲Ν閺傘倖瀚归柨鐔告灮閹凤拷 +#define CAN_SR_RXBUSY_Pos 4 //Receive Busy，正在接收 #define CAN_SR_RXBUSY_Msk (0x01 << CAN_SR_RXBUSY_Pos) -#define CAN_SR_TXBUSY_Pos 5 //Transmit Busy闁跨喐鏋婚幏鐑芥晸閺傘倖瀚归柨鐔诲Ν閸戙倖瀚归柨鐔告灮閹凤拷 +#define CAN_SR_TXBUSY_Pos 5 //Transmit Busy，正在发送 #define CAN_SR_TXBUSY_Msk (0x01 << CAN_SR_TXBUSY_Pos) -#define CAN_SR_ERRWARN_Pos 6 //1 闁跨喐鏋婚幏鐑芥晸閺傘倖瀚规稉鈧柨鐔告灮閹风兘鏁撻弬銈嗗闁跨喐鏋婚幏鐑芥晸閺傘倖瀚归柨鐔告灮閹风兘鏁撻弬銈嗗闁垮骏鎷� Warning Limit +#define CAN_SR_ERRWARN_Pos 6 //1 至少一个错误计数器达到 Warning Limit #define CAN_SR_ERRWARN_Msk (0x01 << CAN_SR_ERRWARN_Pos) -#define CAN_SR_BUSOFF_Pos 7 //1 CAN 闁跨喐鏋婚幏鐑芥晸閺傘倖瀚归柨鐔告灮閹风兘鏁撻弬銈嗗闁跨喐鏋婚幏鐑芥晸閺傘倖瀚归柨鐔侯仾閸忚櫕鍞婚幏椋庡Ц閹線鏁撻弬銈嗗濞岋繝鏁撻崣顐ヮ嚋閹风兘鏁撶拠顐㈠煂闁跨喐鏋婚幏鐑芥晸缁旑厽妞块崝锟� +#define CAN_SR_BUSOFF_Pos 7 //1 CAN 控制器处于总线关闭状态，没有参与到总线活动 #define CAN_SR_BUSOFF_Msk (0x01 << CAN_SR_BUSOFF_Pos) #define CAN_IF_RXDA_Pos 0 //IF.RXDA = SR.RXDA & IE.RXDA #define CAN_IF_RXDA_Msk (0x01 << CAN_IF_RXDA_Pos) -#define CAN_IF_TXBR_Pos 1 //闁跨喐鏋婚幏绋〦.TXBR=1閺冨爼鏁撻弬銈嗗SR.TXBR闁跨喐鏋婚幏锟�0闁跨喐鏋婚幏鐑芥晸閿燂拷1闁跨喐鏋婚幏鐑芥晸閺傘倖瀚规担宥夋晸閺傘倖瀚规担锟� +#define CAN_IF_TXBR_Pos 1 //当IE.TXBR=1时，SR.TXBR由0变成1将置位此位 #define CAN_IF_TXBR_Msk (0x01 << CAN_IF_TXBR_Pos) -#define CAN_IF_ERRWARN_Pos 2 //闁跨喐鏋婚幏绋〦.ERRWARN=1閺冨爼鏁撻弬銈嗗SR.ERRWARN闁跨喐鏋婚幏绋碦.BUSOFF 0-to-1 闁跨喐鏋婚幏锟� 1-to-0闁跨喐鏋婚幏鐑芥晸閺傘倖瀚规担宥夋晸閺傘倖瀚规担锟� +#define CAN_IF_ERRWARN_Pos 2 //当IE.ERRWARN=1时，SR.ERRWARN或SR.BUSOFF 0-to-1 或 1-to-0将置位此位 #define CAN_IF_ERRWARN_Msk (0x01 << CAN_IF_ERRWARN_Pos) #define CAN_IF_RXOV_Pos 3 //IF.RXOV = SR.RXOV & IE.RXOV #define CAN_IF_RXOV_Msk (0x01 << CAN_IF_RXOV_Pos) -#define CAN_IF_WKUP_Pos 4 //闁跨喐鏋婚幏绋〦.WKUP=1閺冨爼鏁撻弬銈嗗闁跨喐鏋婚幏椋庢蒋闁跨喐鏋婚幏閿嬆佸蹇涙晸闁炬壆顣幏绋N闁跨喐鏋婚幏鐑芥晸閺傘倖瀚归柨鐔告灮閹风兘鏁撻弬銈嗗閻涚偓鏋婚幏鐑芥晸閺傘倖瀚归崨瀣澔椤曞灝绨㈢拠褎瀚归柨鐔告灮閹风兘鏁撴潪鍖℃嫹 +#define CAN_IF_WKUP_Pos 4 //当IE.WKUP=1时，在睡眠模式下的CAN控制器检测到总线活动时硬件置位 #define CAN_IF_WKUP_Msk (0x01 << CAN_IF_WKUP_Pos) #define CAN_IF_ERRPASS_Pos 5 // #define CAN_IF_ERRPASS_Msk (0x01 << CAN_IF_ERRPASS_Pos) -#define CAN_IF_ARBLOST_Pos 6 //Arbitration Lost闁跨喐鏋婚幏鐑芥晸閺傘倖瀚笽E.ARBLOST=1閺冨爼鏁撻弬銈嗗CAN闁跨喐鏋婚幏鐑芥晸閺傘倖瀚归柨鐔告灮閹风兘鏁撻弬銈嗗婢堕亶鏁撻崝顐ヮ梿閹插瀚圭仦閬嶆晸閺傘倖瀚规潏妤呮晸缂佺偛绨㈢拠褎瀚归柨鐔告灮閹风兘鏁撴潪鍖℃嫹 +#define CAN_IF_ARBLOST_Pos 6 //Arbitration Lost，当IE.ARBLOST=1时，CAN控制器丢失仲裁变成接收方时硬件置位 #define CAN_IF_ARBLOST_Msk (0x01 << CAN_IF_ARBLOST_Pos) -#define CAN_IF_BUSERR_Pos 7 //闁跨喐鏋婚幏绋〦.BUSERR=1閺冨爼鏁撻弬銈嗗CAN闁跨喐鏋婚幏鐑芥晸閺傘倖瀚归柨鐔告灮閹风兘鏁撻弬銈嗗閻涚偓鏋婚幏鐑芥晸閺傘倖瀚归崣浠嬫晸閺傘倖瀚归柨鐔虹哺鎼村洩顕滈幏鐑芥晸閺傘倖瀚归柨鐔诲▏閿燂拷 +#define CAN_IF_BUSERR_Pos 7 //当IE.BUSERR=1时，CAN控制器检测到总线错误时硬件置位 #define CAN_IF_BUSERR_Msk (0x01 << CAN_IF_BUSERR_Pos) #define CAN_IE_RXDA_Pos 0 @@ -1784,78 +2376,67 @@ typedef struct #define CAN_IE_BUSERR_Pos 7 #define CAN_IE_BUSERR_Msk (0x01 << CAN_IE_BUSERR_Pos) -#define CAN_BT0_BRP_Pos 0 //Baud Rate Prescaler闁跨喐鏋婚幏绋N閺冨爼鏁撻幋鎺戝礋娴ｏ拷=2*Tsysclk*(BRP+1) +#define CAN_BT0_BRP_Pos 0 //Baud Rate Prescaler，CAN时间单位=2*Tsysclk*(BRP+1) #define CAN_BT0_BRP_Msk (0x3F << CAN_BT0_BRP_Pos) #define CAN_BT0_SJW_Pos 6 //Synchronization Jump Width #define CAN_BT0_SJW_Msk (0x03 << CAN_BT0_SJW_Pos) -#define CAN_BT1_TSEG1_Pos 0 //t_tseg1 = CAN閺冨爼鏁撻幋鎺戝礋娴ｏ拷 * (TSEG1+1) +#define CAN_BT1_TSEG1_Pos 0 //t_tseg1 = CAN时间单位 * (TSEG1+1) #define CAN_BT1_TSEG1_Msk (0x0F << CAN_BT1_TSEG1_Pos) -#define CAN_BT1_TSEG2_Pos 4 //t_tseg2 = CAN閺冨爼鏁撻幋鎺戝礋娴ｏ拷 * (TSEG2+1) +#define CAN_BT1_TSEG2_Pos 4 //t_tseg2 = CAN时间单位 * (TSEG2+1) #define CAN_BT1_TSEG2_Msk (0x07 << CAN_BT1_TSEG2_Pos) -#define CAN_BT1_SAM_Pos 7 //闁跨喐鏋婚幏鐑芥晸閺傘倖瀚归柨鐔告灮閹风兘鏁撻弬銈嗗 0: sampled once 1: sampled three times +#define CAN_BT1_SAM_Pos 7 //采样次数 0: sampled once 1: sampled three times #define CAN_BT1_SAM_Msk (0x01 << CAN_BT1_SAM_Pos) #define CAN_ECC_SEGCODE_Pos 0 //Segment Code -#define CAN_ECC_SEGCODE_Msk (0x0F << CAN_ECC_SEGCODE_Pos) -#define CAN_ECC_DIR_Pos 4 //0 error occurred during transmission 1 during reception +#define CAN_ECC_SEGCODE_Msk (0x1F << CAN_ECC_SEGCODE_Pos) +#define CAN_ECC_DIR_Pos 5 //0 error occurred during transmission 1 during reception #define CAN_ECC_DIR_Msk (0x01 << CAN_ECC_DIR_Pos) -#define CAN_ECC_ERRCODE_Pos 5 //Error Code闁跨喐鏋婚幏锟�0 Bit error 1 Form error 2 Stuff error 3 other error +#define CAN_ECC_ERRCODE_Pos 6 //Error Code：0 Bit error 1 Form error 2 Stuff error 3 other error #define CAN_ECC_ERRCODE_Msk (0x03 << CAN_ECC_ERRCODE_Pos) #define CAN_INFO_DLC_Pos 0 //Data Length Control #define CAN_INFO_DLC_Msk (0x0F << CAN_INFO_DLC_Pos) -#define CAN_INFO_RTR_Pos 6 //Remote Frame闁跨喐鏋婚幏锟�1 鏉╂粓鏁撻弬銈嗗鐢拷 0 闁跨喐鏋婚幏鐑芥晸閺傘倖瀚圭敮锟� +#define CAN_INFO_RTR_Pos 6 //Remote Frame，1 远程帧 0 数据帧 #define CAN_INFO_RTR_Msk (0x01 << CAN_INFO_RTR_Pos) -#define CAN_INFO_FF_Pos 7 //Frame Format闁跨喐鏋婚幏锟�0 闁跨喐鏋婚幏宄板櫙鐢囨晸閺傘倖瀚瑰锟� 1 闁跨喐鏋婚幏宄扮潔鐢囨晸閺傘倖瀚瑰锟� +#define CAN_INFO_FF_Pos 7 //Frame Format，0 标准帧格式 1 扩展帧格式 #define CAN_INFO_FF_Msk (0x01 << CAN_INFO_FF_Pos) typedef struct { - __IO uint32_t IE; //[0] 娑擄拷0闁跨喐鏋婚幏閿嬫闁跨喐鏋婚幏绋〧[0]缂佹挳鏁撻弬銈嗗娑擄拷0 + __IO uint32_t IE; //[0] 为0的时候，IF[0]维持为0 - __IO uint32_t IF; //[0] 闁跨喐鏋婚幏鐑芥晸閺傘倖瀚归柨鐔活敎闂堚晜瀚归柨鐔告灮閹风兘鏁撻弬銈嗗妤ｅ﹪鏁撻弬銈嗗闁跨喐鏋婚幏鐤禂闁跨喐鏋婚幏鐑芥晸缂佺偞鍞婚幏鐑芥晸閿燂拷1闁跨喐鏋婚幏宄板晸1闁跨喐鏋婚幏鐑芥晸閺傘倖瀚� + __IO uint32_t IF; //[0] 当完成指定长度的数据传输时置1，写1清零 - __IO uint32_t IM; //[0] 闁跨喐鏋婚幏鐑芥晸閻偄鐦庢潏鐐闁跨喐鏋婚幏铚傝礋1閺冨爼鏁撻弬銈嗗LCDC闁跨喐鏋婚幏鐑芥晸閸欘偅鏌囩拠褎瀚归柨鐔告灮閹风兘鏁撻弬銈嗗闁跨喐鏋婚幏鐑芥晸鏉堝啩缍嗙粵瑙勫闁跨喐鏋婚幏宄板祻瀹勶繝鏁撻弬銈嗗閽€宥嗗闁跨喐鏋婚幏鐑芥晸閿燂拷 + __IO uint32_t IM; //[0] 当该寄存器为1时，LCDC的中断不会输出给系统的中断控制寄存器 __IO uint32_t START; - __IO uint32_t SRCADDR; //闁跨喐鏋婚幏鐑芥晸閺傘倖瀚瑰┃鎰版晸閺傘倖瀚归崸鈧柨鐔惰寧鏉堢偓瀚归柨鐔告灮閹风兘鏁撻弬銈嗗30娴ｅ秹鏁撻弬銈嗗闁跨喐鏋婚幏鐑芥晸閺傘倖瀚规担宥夋晸閻ㄥ棜顔愰幏鐑芥晸閺傘倖瀚归柨鐔告灮閹凤拷 + __IO uint32_t SRCADDR; //数据源地址寄存器，必须字对齐（即地址的低2位必须是0） __IO uint32_t CR0; __IO uint32_t CR1; - __IO uint32_t PRECMDV; //闁跨喐鏋婚幏绋璓U闁跨喐甯撮崠鈩冨闁跨喎褰ㄩ敐蹇斿闁跨喐鏋婚幏鐑芥晸閺傘倖瀚归柨鐔告灮閹风兘鏁撻弬銈嗗閸撳秹鏁撻弬銈嗗RS闁跨喐鏋婚幏鐑芥晸闁扮數顣幏鐑芥晸閺傘倖瀚规稉鈧柨鐔惰寧閿濆繑瀚归柨鐔告灮閹风兘鏁撻弬銈嗗闁跨喐鏋婚幏鐑芥晸閺傘倖瀚归柨鐔荤窛绾板瀚归崐锟� + __IO uint32_t PRECMDV; //在MPU接口中，发送数据前，RS拉低的那一拍，数据总线上的值 } LCD_TypeDef; -#define LCD_START_MPUEN_Pos 0 //0 RGB闁跨喐甯撮崠鈩冨 1 MPU闁跨喐甯撮崠鈩冨 -#define LCD_START_MPUEN_Msk (0x01 << LCD_START_MPUEN_Pos) -#define LCD_START_GO_Pos 1 //閸愶拷1闁跨喐鏋婚幏宄邦潗闁跨喐鏋婚幏鐑芥晸閺傘倖瀚归柨鐔告灮閹风兘鏁撻幑鍑ょ秶閹风兘鏁撻弬銈嗗闁跨喐宓庢潏鐐闁跨喐鏋婚幏鐑芥晸閺傘倖瀚归柨鐔告灮閹风兘鏁撻弬銈嗗鏉╂粓鏁撻弬銈嗗闁跨喐鏋婚幏鐑芥晸閿燂拷 +#define LCD_START_GO_Pos 1 //写1开始传输数据，数据传输结束后自动清零 #define LCD_START_GO_Msk (0x01 << LCD_START_GO_Pos) #define LCD_START_BURST_Pos 2 #define LCD_START_BURST_Msk (0x01 << LCD_START_BURST_Pos) -#define LCD_START_POSTCMDE_Pos 3 //闁跨喐鏋婚幏铚傜昂闁跨喐鏋婚幏鐤洣闁跨喐鏋婚幏鐑芥晸閺傘倖瀚归崘娆撴晸閺傘倖瀚归幏鍥晸閺傘倖瀚归柨鐔活敎椤曞棙瀚归摶鍜佸劉闁跨喐褰搴㈠闁跨喐褰导娆愬闁跨噦鎷�0x80闁跨喐鏋婚幏鐑芥晸閺傘倖瀚归柨鐔告灮閹风兘鏁撻弬銈嗗闁跨喐鏋婚幏鐑芥晸鐞涙鎷� -#define LCD_START_POSTCMDE_Msk (0x01 << LCD_START_POSTCMDE_Pos) -#define LCD_START_POSTCMDV_Pos 4 //闁跨喐鏋婚幏鐑芥晸閺傘倖瀚归柨鐔告灮閹风兘鏁撻弬銈嗗闁跨喐鏋婚幏鐑芥晸鐞涙鎷濋幏鐑芥晸閺傘倖瀚归崘銏ゆ晸閺傘倖瀚归柨鐔告灮閹风兘鏁撻弬銈嗗闁跨喐鏋婚幏鐑芥晸閺傘倖瀚圭化濠氭晸鐞涙顣幏鐑芥晸娓氥儺鍓ㄩ幏鐑芥晸閺傘倖瀚归柨鐕傛嫹0x80闁跨喐鏋婚幏鐑芥晸閺傘倖瀚归柨鐔告灮閹风兘鏁撻弬銈嗗闁跨喐鏋婚幏鐤洣闁跨喐鏋婚幏鐑芥晸閺傘倖瀚归柨鐔告灮閹凤拷 -#define LCD_START_POSTCMDV_Msk (0xFFFF << LCD_START_POSTCMDV_Pos) -#define LCD_CR0_VPIX_Pos 0 //闁跨喐鏋婚幏绌歰rtrait娑擄拷0閺冨爼鏁撻弬銈嗗闁跨喐鏋婚幏椋庛仛闁跨喐鏋婚幏椋庢纯闁跨喐鏋婚幏鐑芥晸閺傘倖瀚归柨鐔告灮閹风兘鏁撻弬銈嗗妫ｆ鏁撻弬銈嗗闁跨喐鏋婚幏鐑芥晸閿燂拷0闁跨喐鏋婚幏椋庛仛1闁跨喐鏋婚幏鐑芥晸閺傘倖瀚归柨鐔告灮閹风兘鏁撴潪鍖℃嫹767 -//闁跨喐鏋婚幏绌歰rtrait娑擄拷1閺冨爼鏁撻弬銈嗗闁跨喐鏋婚幏椋庛仛濮樻潙閽╅柨鐔告灮閹风兘鏁撻弬銈嗗闁跨喐鏋婚幏鐑芥晸閺傘倖瀚规＃妤呮晸閺傘倖瀚归柨鐔告灮閹风兘鏁撻敓锟�0闁跨喐鏋婚幏椋庛仛1闁跨喐鏋婚幏鐑芥晸閺傘倖瀚归柨鐔告灮閹风兘鏁撴潪鍖℃嫹767 +#define LCD_CR0_VPIX_Pos 0 /*当portrait为0时，表示垂直方向的像素个数，0表示1个，最大为767 \ + //当portrait为1时，表示水平方向的像素个数，0表示1个，最大为767 */ #define LCD_CR0_VPIX_Msk (0x3FF << LCD_CR0_VPIX_Pos) -#define LCD_CR0_HPIX_Pos 10 //闁跨喐鏋婚幏绌歰rtrait娑擄拷0閺冨爼鏁撻弬銈嗗闁跨喐鏋婚幏椋庛仛濮樻潙閽╅柨鐔告灮閹风兘鏁撻弬銈嗗闁跨喐鏋婚幏鐑芥晸閺傘倖瀚规＃妤呮晸閺傘倖瀚归柨鐔告灮閹风兘鏁撻敓锟�0闁跨喐鏋婚幏椋庛仛1闁跨喐鏋婚幏鐑芥晸閺傘倖瀚归柨鐔告灮閹风兘鏁撴潪鍖℃嫹1023 -//闁跨喐鏋婚幏绌歰rtrait娑擄拷1閺冨爼鏁撻弬銈嗗闁跨喐鏋婚幏椋庛仛闁跨喐鏋婚幏椋庢纯闁跨喐鏋婚幏鐑芥晸閺傘倖瀚归柨鐔告灮閹风兘鏁撻弬銈嗗妫ｆ鏁撻弬銈嗗闁跨喐鏋婚幏鐑芥晸閿燂拷0闁跨喐鏋婚幏椋庛仛1闁跨喐鏋婚幏鐑芥晸閺傘倖瀚归柨鐔告灮閹风兘鏁撴潪鍖℃嫹1023 +#define LCD_CR0_HPIX_Pos 10 /*当portrait为0时，表示水平方向的像素个数，0表示1个，最大为1023 \ + //当portrait为1时，表示垂直方向的像素个数，0表示1个，最大为1023 */ #define LCD_CR0_HPIX_Msk (0x3FF << LCD_CR0_HPIX_Pos) -#define LCD_CR0_DCLK_Pos 20 //0 DOTCLK娑撯偓閻╂挳鏁撻弬銈嗗鏉烇拷 1 DOTCLK闁跨喕濡崠鈩冨闁跨喐鏋婚幏閿嬫閸嬫粓鏁撻弬銈嗗1 +#define LCD_CR0_DCLK_Pos 20 //0 DOTCLK一直翻转 1 DOTCLK在空闲时停在1 #define LCD_CR0_DCLK_Msk (0x01 << LCD_CR0_DCLK_Pos) -#define LCD_CR0_HLOW_Pos 21 //闁跨喐鏋婚幏鐑芥晸缁辩笌YNC闁跨喖鍙虹喊澶嬪楠炴娊鏁撻弬銈嗗闁跨喐鏋婚幏鐑芥晸閺傘倖瀚归柨鐔峰Л闂堚晜瀚笵OTCLK闁跨喐鏋婚幏鐑芥晸閼哄偊缍囬幏锟�0闁跨喐鏋婚幏椋庛仛1闁跨喐鏋婚幏鐑芥晸閺傘倖瀚归柨鐔告灮閹凤拷 +#define LCD_CR0_HLOW_Pos 21 //输出HSYNC低电平持续多少个DOTCLK周期，0表示1个周期 #define LCD_CR0_HLOW_Msk (0x03 << LCD_CR0_HLOW_Pos) -#define LCD_CR0_DLEN_Pos 0 //MPU闁跨喐甯撮崠鈩冨閺冨爼鏁撻弬銈嗗闁跨喎澹欏▎陇顕滈幏鐑芥晸閺傘倖瀚归柨鐔告灮閹风兘鏁撻弬銈嗗闁跨喐宓庣粵瑙勫闁跨喖銈洪敐蹇斿闁跨喐鏋婚幏铚傜秴娑撴椽鏁撶悰妤勫Ν閿濆繑瀚�0闁跨喐鏋婚幏椋庛仛1闁跨喐鏋婚幏锟� -#define LCD_CR0_DLEN_Msk (0x1FFFFF << LCD_CR0_DLEN_Pos) - -#define LCD_CR1_DIRV_Pos 0 //0 portrait=0闁跨喐鏋婚幏鐑芥晸閺傘倖瀚归柨鐔告灮閹烽攱膩瀵拷 1 portrait=1闁跨喐鏋婚幏鐑芥晸閺傘倖瀚归柨鐔告灮閹烽攱膩瀵拷 -#define LCD_CR1_DIRV_Msk (0x01 << LCD_CR1_DIRV_Pos) #define LCD_CR1_VFP_Pos 1 #define LCD_CR1_VFP_Msk (0x07 << LCD_CR1_VFP_Pos) #define LCD_CR1_VBP_Pos 4 @@ -1864,26 +2445,11 @@ typedef struct #define LCD_CR1_HFP_Msk (0x1F << LCD_CR1_HFP_Pos) #define LCD_CR1_HBP_Pos 14 #define LCD_CR1_HBP_Msk (0x7F << LCD_CR1_HBP_Pos) -#define LCD_CR1_DCLKDIV_Pos 21 //DOTCLK闁跨喐鏋婚幏鐑芥晸閺傘倖瀚归柨鐔惰寧閿濆繑瀚归柨鐔虹哺閹插瀚归幏銉ヮ潒闁跨喓瀚涚喊澶嬪姒鏁撻敓锟�0闁跨喐鏋婚幏椋庛仛2闁跨喐鏋婚幏鐑筋暥闁跨喐鏋婚幏锟�1闁跨喐鏋婚幏椋庛仛4闁跨喐鏋婚幏鐑筋暥 ... +#define LCD_CR1_DCLKDIV_Pos 21 //DOTCLK相对于模块时钟的分频比，0表示2分频，1表示4分频 ... #define LCD_CR1_DCLKDIV_Msk (0x1F << LCD_CR1_DCLKDIV_Pos) -#define LCD_CR1_DCLKINV_Pos 26 //1 闁跨喐鏋婚幏鐑芥晸缁辩睋TCLK闁跨喐鏋婚幏鐑芥晸閺傘倖瀚规惔鏃堟晸閺傘倖瀚归柨鐔告灮閹风兘鏁撻弬銈嗗DOTCLK闁跨喖鎽弬銈嗗闁跨喐鍩呯拠褎瀚归柨鐔告灮閹风兘鏁撻弬銈嗗闁跨喐宓庣喊澶嬪闁跨喐鏋婚幏锟� +#define LCD_CR1_DCLKINV_Pos 26 //1 输出DOTCLK反向，应用于用DOTCLK下降沿采样数据的屏 #define LCD_CR1_DCLKINV_Msk (0x01 << LCD_CR1_DCLKINV_Pos) -#define LCD_CR1_REG_Pos 0 //LCD_CR1_CMD_Pos閸欐牕鈧拷1閺冨爼鏁撻弬銈嗗闁跨喍鑼庢潏鐐闁跨喐鏋婚幏鐑芥晸閺傘倖瀚归柨鐔告灮閹峰嘲鈧拷 -#define LCD_CR1_REG_Msk (0xFFFF << LCD_CR1_REG_Pos) -#define LCD_CR1_I80_Pos 16 //1 闁跨喐甯撮崠鈩冨娑撶瘨80 0 闁跨喐甯撮崠鈩冨娑撶瘲68 -#define LCD_CR1_I80_Msk (0x01 << LCD_CR1_I80_Pos) -#define LCD_CR1_CMD_Pos 17 //0 闁跨喐鏋婚幏鐑芥晸閹圭柉鎻幏鐑芥晸閹存帪绱濋柨鐔告灮閹风úS娑撴椽鏁撶粩顓狀暜閹峰嘲閽� 1 闁跨喐鏋婚幏鐑芥晸缁涘绱堕柨鐔稿灊閿涘矂鏁撻弬銈嗗闁跨喐鏋婚幏鐑芥晸閺傘倖瀚归幏鍥晸閺傘倖瀚归柨鐔告灮閹风兘鏁撻弬銈嗗闁跨喐鏋婚幏鐑芥晸閺傘倖瀚归柨鐔虹ゲS娑撴椽鏁撻柊鐢殿暜閹峰嘲閽� -#define LCD_CR1_CMD_Msk (0x01 << LCD_CR1_CMD_Pos) -#define LCD_CR1_TTAIL_Pos 18 //CSn闁跨喐鏋婚幏鐑芥晸閺傘倖瀚归柨鐔稿焻绾板瀚笴Sn闁跨喖鎽弬銈嗗闁跨喐鍩呯喊澶嬪閺冨爼鏁撻弬銈嗗 -#define LCD_CR1_TTAIL_Msk (0x07 << LCD_CR1_TTAIL_Pos) -#define LCD_CR1_TAH_Pos 21 //WRn闁跨喐鏋婚幏鐑芥晸閺傘倖瀚归柨鐔稿焻绾板瀚笴Sn闁跨喐鏋婚幏鐑芥晸閺傘倖瀚归柨鐔稿焻绾板瀚归弮鍫曟晸閺傘倖瀚� -#define LCD_CR1_TAH_Msk (0x03 << LCD_CR1_TAH_Pos) -#define LCD_CR1_TPWLW_Pos 23 //WRn闁跨喖鍙虹喊澶嬪楠炴娊鏁撴笟銉ь劜閹风兘鏁撻弬銈嗗閺冨爼鏁撻弬銈嗗 -#define LCD_CR1_TPWLW_Msk (0x07 << LCD_CR1_TPWLW_Pos) -#define LCD_CR1_TAS_Pos 26 //CSn闁跨喖鎽弬銈嗗闁跨喐鍩呯喊澶嬪WRn闁跨喖鎽弬銈嗗闁跨喐鍩呯喊澶嬪閺冨爼鏁撻弬銈嗗 -#define LCD_CR1_TAS_Msk (0x03 << LCD_CR1_TAS_Pos) - typedef struct { __IO uint32_t DMA_MEM_ADDR; @@ -1906,9 +2472,9 @@ typedef struct __IO uint32_t IF; - __IO uint32_t IE; + __IO uint32_t IFE; //Interrupt Flag Enable - __IO uint32_t IM; + __IO uint32_t IE; //Interrupt Enalbe __IO uint32_t CMD12ERR; @@ -1917,9 +2483,9 @@ typedef struct __IO uint32_t MAXCURR; } SDIO_TypeDef; -#define SDIO_BLK_SIZE_Pos 0 //0x200 512闁跨喕顢滈弬銈嗗 0x400 1024闁跨喕顢滈弬銈嗗 0x800 2048闁跨喕顢滈弬銈嗗 +#define SDIO_BLK_SIZE_Pos 0 //0x200 512字节 0x400 1024字节 0x800 2048字节 #define SDIO_BLK_SIZE_Msk (0xFFF << SDIO_BLK_SIZE_Pos) -#define SDIO_BLK_COUNT_Pos 16 //0 Stop Transfer 1 1闁跨喐鏋婚幏锟� 2 2闁跨喐鏋婚幏锟� ... ... +#define SDIO_BLK_COUNT_Pos 16 //0 Stop Transfer 1 1块 2 2块 ... ... #define SDIO_BLK_COUNT_Msk (0xFFF << SDIO_BLK_COUNT_Pos) #define SDIO_CMD_DMAEN_Pos 0 @@ -1932,7 +2498,7 @@ typedef struct #define SDIO_CMD_DIRREAD_Msk (0x01 << SDIO_CMD_DIRREAD_Pos) #define SDIO_CMD_MULTBLK_Pos 5 //0 Single Block 1 Multiple Block #define SDIO_CMD_MULTBLK_Msk (0x01 << SDIO_CMD_MULTBLK_Pos) -#define SDIO_CMD_RESPTYPE_Pos 16 //闁跨喐鏋婚幏宄扮安闁跨喐鏋婚幏鐑芥晸闁扮缍囬幏锟�0 闁跨喐鏋婚幏鐑芥晸閺傘倖瀚规惔锟� 1 136娴ｅ秹鏁撻弬銈嗗鎼达拷 2 48娴ｅ秹鏁撻弬銈嗗鎼达拷 3 48娴ｅ秹鏁撻弬銈嗗鎼存棃鏁撻弬銈嗗Busy after response +#define SDIO_CMD_RESPTYPE_Pos 16 //响应类型，0 无响应 1 136位响应 2 48位响应 3 48位响应，Busy after response #define SDIO_CMD_RESPTYPE_Msk (0x03 << SDIO_CMD_RESPTYPE_Pos) #define SDIO_CMD_CRCCHECK_Pos 19 //Command CRC Check Enable #define SDIO_CMD_CRCCHECK_Msk (0x01 << SDIO_CMD_CRCCHECK_Pos) @@ -1942,7 +2508,7 @@ typedef struct #define SDIO_CMD_HAVEDATA_Msk (0x01 << SDIO_CMD_HAVEDATA_Pos) #define SDIO_CMD_CMDTYPE_Pos 22 //0 NORMAL 1 SUSPEND 2 RESUME 3 ABORT #define SDIO_CMD_CMDTYPE_Msk (0x03 << SDIO_CMD_CMDTYPE_Pos) -#define SDIO_CMD_CMDINDX_Pos 24 //Command Index闁跨喐鏋婚幏绋D0-63闁跨喐鏋婚幏绋烠MD0-63 +#define SDIO_CMD_CMDINDX_Pos 24 //Command Index，CMD0-63、ACMD0-63 #define SDIO_CMD_CMDINDX_Msk (0x3F << SDIO_CMD_CMDINDX_Pos) #define SDIO_CR1_4BIT_Pos 1 //1 4 bit mode 0 1 bit mode @@ -1951,7 +2517,7 @@ typedef struct #define SDIO_CR1_8BIT_Msk (0x01 << SDIO_CR1_8BIT_Pos) #define SDIO_CR1_CDBIT_Pos 6 //0 No Card 1 Card Inserted #define SDIO_CR1_CDBIT_Msk (0x01 << SDIO_CR1_CDBIT_Pos) -#define SDIO_CR1_CDSRC_Pos 7 //Card Detect Source, 1 CR1.CDBIT娴ｏ拷 0 SD_Detect闁跨喐鏋婚幏鐑芥晸閺傘倖瀚� +#define SDIO_CR1_CDSRC_Pos 7 //Card Detect Source, 1 CR1.CDBIT位 0 SD_Detect引脚 #define SDIO_CR1_CDSRC_Msk (0x01 << SDIO_CR1_CDSRC_Pos) #define SDIO_CR1_PWRON_Pos 8 //1 Power on 0 Power off #define SDIO_CR1_PWRON_Msk (0x01 << SDIO_CR1_PWRON_Pos) @@ -1964,9 +2530,9 @@ typedef struct #define SDIO_CR2_CLKRDY_Msk (0x01 << SDIO_CR2_CLKRDY_Pos) #define SDIO_CR2_SDCLKEN_Pos 2 //SDCLK Enable #define SDIO_CR2_SDCLKEN_Msk (0x01 << SDIO_CR2_SDCLKEN_Pos) -#define SDIO_CR2_SDCLKDIV_Pos 8 //SDCLK Frequency Div, 0x00 闁跨喐鏋婚幏鐑芥晸閺傘倖瀚规０锟� 0x01 2闁跨喐鏋婚幏鐑筋暥 0x02 4闁跨喐鏋婚幏鐑筋暥 0x04 8闁跨喐鏋婚幏鐑筋暥 0x08 16闁跨喐鏋婚幏鐑筋暥 ... 0x80 256闁跨喐鏋婚幏鐑筋暥 +#define SDIO_CR2_SDCLKDIV_Pos 8 //SDCLK Frequency Div, 0x00 不分频 0x01 2分频 0x02 4分频 0x04 8分频 0x08 16分频 ... 0x80 256分频 #define SDIO_CR2_SDCLKDIV_Msk (0xFF << SDIO_CR2_SDCLKDIV_Pos) -#define SDIO_CR2_TIMEOUT_Pos 16 //0000 TMCLK*2^13 +#define SDIO_CR2_TIMEOUT_Pos 16 //0 TMCLK*2^13 1 TMCLK*2^14 ... 14 TMCLK*2^27 #define SDIO_CR2_TIMEOUT_Msk (0x0F << SDIO_CR2_TIMEOUT_Pos) #define SDIO_CR2_RSTALL_Pos 24 //Software Reset for All #define SDIO_CR2_RSTALL_Msk (0x01 << SDIO_CR2_RSTALL_Pos) @@ -2104,7 +2670,7 @@ typedef struct { __IO uint32_t DATA; __IO uint32_t ADDR; - __IO uint32_t ERASE; + __IO uint32_t SWM_ERASE; __IO uint32_t CACHE; __IO uint32_t CFG0; __IO uint32_t CFG1; @@ -2114,7 +2680,7 @@ typedef struct } FLASH_Typedef; #define FLASH_ERASE_REQ_Pos 31 -#define FLASH_ERASE_REQ_Msk ((uint32_t)0x01 << FLASH_ERASE_REQ_Pos) +#define FLASH_ERASE_REQ_Msk (0x01u << FLASH_ERASE_REQ_Pos) #define FLASH_CACHE_PROG_Pos 2 #define FLASH_CACHE_PROG_Msk (0x01 << FLASH_CACHE_PROG_Pos) @@ -2135,11 +2701,11 @@ typedef struct __IO uint32_t CR; } SRAMC_TypeDef; -#define SRAMC_CR_RWTIME_Pos 0 //闁跨喐鏋婚幏宄板晸闁跨喐鏋婚幏鐑芥晸閺傘倖瀚归柨鐔告灮閹风兘鏁撻弬銈嗗闁跨喐鏋婚幏鐑芥晸閸旑偊娼婚幏閿嬫闁跨喐鏋婚幏鐑芥晸閺傘倖瀚归柨鐔诲Ν閳藉懏瀚�0闁跨喐鏋婚幏椋庛仛1闁跨喐鏋婚幏閿嬫闁跨喐鏋婚幏鐑芥晸閺傘倖瀚归柨鐔诲Ν閳藉懏瀚归柨鐔告灮閹峰嘲鐨柨鐔告灮閹风兘鏁撻弬銈嗗娑擄拷4 +#define SRAMC_CR_RWTIME_Pos 0 //读写操作持续多少个时钟周期。0表示1个时钟周期。最小设置为4 #define SRAMC_CR_RWTIME_Msk (0x0F << SRAMC_CR_RWTIME_Pos) -#define SRAMC_CR_BYTEIF_Pos 4 //闁跨喕袙闁娍RAM闁跨喐鏋婚幏鐑芥晸閹瑰嘲灏呴幏鐑界伐闁跨噦鎷�0 16娴ｏ拷 1 8娴ｏ拷 +#define SRAMC_CR_BYTEIF_Pos 4 //外部SRAM数据宽度，0 16位 1 8位 #define SRAMC_CR_BYTEIF_Msk (0x01 << SRAMC_CR_BYTEIF_Pos) -#define SRAMC_CR_HBLBDIS_Pos 5 //1 ADDR[23:22]娑撴椽鏁撻弬銈嗗閸р偓闁跨喐鏋婚幏锟� 0 ADDR[23]娑撴椽鏁撻弬銈嗗闁跨喕顢滈弬銈嗗娴ｅ潡鏁撻弶甯秶閹风DDR[22]娑撴椽鏁撻弬銈嗗闁跨喕顢滈弬銈嗗娴ｅ潡鏁撻弬銈嗗 +#define SRAMC_CR_HBLBDIS_Pos 5 //1 ADDR[23:22]为地址线 0 ADDR[23]为高字节使能，ADDR[22]为低字节使能 #define SRAMC_CR_HBLBDIS_Msk (0x01 << SRAMC_CR_HBLBDIS_Pos) typedef struct @@ -2150,16 +2716,16 @@ typedef struct __IO uint32_t REFRESH; - __IO uint32_t NOPNUM; //[15:0] 闁跨喐鏋婚幏宄邦潗闁跨喐鏋婚幏鐑芥晸閺傘倖瀚归悵濠囨晸閺傘倖瀚归柨鐔告灮閹风兘鏁撻弬銈嗗闁跨喐鏋婚幏鐑芥晸閺傘倖瀚归柨鐔活敎椤旂偛搴滈幏鐑芥晸閺傘倖瀚归柨鐔告灮閹烽攱濮囬柨鐔告灮閹疯渹绻庨柨鐔虹ガOP闁跨喐鏋婚幏鐑芥晸閺傘倖瀚� + __IO uint32_t NOPNUM; //[15:0] 初始化完成后，在正常操作之前，发送多少个NOP命令 __IO uint32_t LATCH; - __IO uint32_t REFDONE; //[0] Frefresh Done闁跨喐鏋婚幏鐑芥晸鏉堝啰顣幏鐑芥晸缂佺偟銆嬮幏鐑芥晸閺傘倖瀚归柨鐔告灮閹凤拷 + __IO uint32_t REFDONE; //[0] Frefresh Done，上电初始化完成 } SDRAMC_TypeDef; -#define SDRAMC_CR0_BURSTLEN_Pos 0 //闁跨喐鏋婚幏鐑芥晸閺傘倖瀚归崣锟�2闁跨喐鏋婚幏鐑芥晸閺傘倖瀚圭粈绡塽rst Length娑擄拷4 +#define SDRAMC_CR0_BURSTLEN_Pos 0 //必须取2，表示Burst Length为4 #define SDRAMC_CR0_BURSTLEN_Msk (0x07 << SDRAMC_CR0_BURSTLEN_Pos) -#define SDRAMC_CR0_CASDELAY_Pos 4 //CAS Latency闁跨喐鏋婚幏锟� 2 2 3 3 +#define SDRAMC_CR0_CASDELAY_Pos 4 //CAS Latency， 2 2 3 3 #define SDRAMC_CR0_CASDELAY_Msk (0x07 << SDRAMC_CR0_CASDELAY_Pos) #define SDRAMC_CR1_TRP_Pos 0 @@ -2174,15 +2740,15 @@ typedef struct #define SDRAMC_CR1_TRRD_Msk (0x03 << SDRAMC_CR1_TRRD_Pos) #define SDRAMC_CR1_TMRD_Pos 15 #define SDRAMC_CR1_TMRD_Msk (0x07 << SDRAMC_CR1_TMRD_Pos) -#define SDRAMC_CR1_32BIT_Pos 18 //SDRAMC闁跨喍鑼庨幒銉ュ皡閹风兘鏁撻弬銈嗗闁跨喐鏋婚幏铚傜秴闁跨喐鏋婚幏锟�1 32bit 0 16bit +#define SDRAMC_CR1_32BIT_Pos 18 //SDRAMC的接口数据位宽，1 32bit 0 16bit #define SDRAMC_CR1_32BIT_Msk (0x01 << SDRAMC_CR1_32BIT_Pos) -#define SDRAMC_CR1_BANK_Pos 19 //SDRAM濮ｅ繘鏁撻弬銈嗗闁跨喐鏋婚幏鐑芥晸閺傘倖瀚归柨鐔峰建绾攱瀚归柨鐔告灮閹风⿰ank闁跨喐鏋婚幏锟�0 2 banks 1 4 banks +#define SDRAMC_CR1_BANK_Pos 19 //SDRAM每个颗粒有几个bank，0 2 banks 1 4 banks #define SDRAMC_CR1_BANK_Msk (0x01 << SDRAMC_CR1_BANK_Pos) -#define SDRAMC_CR1_CELL32BIT_Pos 20 //SDRAM闁跨喐鏋婚幏鐑芥晸閺傘倖瀚归柨鐔告灮閹疯渹缍呴柨鐔告灮閹凤拷1 32bit 0 16bit +#define SDRAMC_CR1_CELL32BIT_Pos 20 //SDRAM颗粒的位宽，1 32bit 0 16bit #define SDRAMC_CR1_CELL32BIT_Msk (0x01 << SDRAMC_CR1_CELL32BIT_Pos) -#define SDRAMC_CR1_CELLSIZE_Pos 21 //SDRAM闁跨喐鏋婚幏鐑芥晸閺傘倖瀚归柨鐔告灮閹风兘鏁撻弬銈嗗闁跨喐鏋婚幏鐑芥晸閺傘倖瀚�0 64Mb 1 128Mb 2 256Mb 3 16Mb +#define SDRAMC_CR1_CELLSIZE_Pos 21 //SDRAM颗粒的容量，0 64Mb 1 128Mb 2 256Mb 3 16Mb #define SDRAMC_CR1_CELLSIZE_Msk (0x03 << SDRAMC_CR1_CELLSIZE_Pos) -#define SDRAMC_CR1_HIGHSPEED_Pos 23 //闁跨喐鏋婚幏绌恈lk闁跨喐鏋婚幏鐑芥晸閺傘倖瀚�100MHz閺冨爼鏁撻弬銈嗗闁跨喐鏋婚幏铚傜娴ｅ秹鏁撻弬銈嗗闁跨喐鏋婚幏鐑芥晸閺傘倖瀚归柨鐔告灮閹疯渹璐�1闁跨喐鏋婚幏鐑芥晸閺傘倖瀚归柨鐔告灮閹疯渹璐�0 +#define SDRAMC_CR1_HIGHSPEED_Pos 23 //当hclk大于100MHz时，这一位必须配置为1，否则为0 #define SDRAMC_CR1_HIGHSPEED_Msk (0x01 << SDRAMC_CR1_HIGHSPEED_Pos) #define SDRAMC_REFRESH_RATE_Pos 0 @@ -2190,9 +2756,9 @@ typedef struct #define SDRAMC_REFRESH_EN_Pos 12 #define SDRAMC_REFRESH_EN_Msk (0x01 << SDRAMC_REFRESH_EN_Pos) -#define SDRAMC_LATCH_INEDGE_Pos 0 //闁跨喍鑼庨棃鈺傚闁跨喐鏋婚幏鐑芥晸閺傘倖瀚归柨鐔告灮閹风兘鏁撻弬銈嗗闁跨喓绁矰RAM闁跨喎褰ㄧ拋瑙勫闁跨喐鍩呯喊澶嬪闁跨喐鏋婚幏鐑芥晸閹瑰嚖缍囬幏锟�0 闁跨喐鏋婚幏鐑芥晸閺傘倖瀚归柨鐔告灮閹凤拷 1 闁跨喖鎽弬銈嗗闁跨喐鏋婚幏锟� +#define SDRAMC_LATCH_INEDGE_Pos 0 //哪个沿来锁存从SDRAM中读回的数据，0 上升沿 1 下降沿 #define SDRAMC_LATCH_INEDGE_Msk (0x01 << SDRAMC_LATCH_INEDGE_Pos) -#define SDRAMC_LATCH_OUTEDGE_Pos 1 //闁跨喍鑼庨棃鈺傚闁跨喐鏋婚幏宄板箵闁跨喐鏋婚幏鐑芥晸閺傘倖瀚归柨鐔煎徍闂堚晜瀚筍DRAM闁跨喐鏋婚幏鐑芥晸閺傘倖瀚归柨鐔稿祹閿濆繑瀚�1 闁跨喐鏋婚幏鐑芥晸閺傘倖瀚归柨鐔告灮閹凤拷 0 闁跨喖鎽弬銈嗗闁跨喐鏋婚幏锟� +#define SDRAMC_LATCH_OUTEDGE_Pos 1 //哪个沿去锁存送给SDRAM的数据，1 上升沿 0 下降沿 #define SDRAMC_LATCH_OUTEDGE_Msk (0x01 << SDRAMC_LATCH_OUTEDGE_Pos) #define SDRAMC_LATCH_WAITST_Pos 2 #define SDRAMC_LATCH_WAITST_Msk (0x01 << SDRAMC_LATCH_WAITST_Pos) @@ -2201,7 +2767,7 @@ typedef struct { __IO uint32_t IE; - __IO uint32_t IF; //閸愶拷1闁跨喐鏋婚幏鐑芥晸閺傘倖瀚� + __IO uint32_t IF; //写1清零 __IO uint32_t IM; @@ -2227,16 +2793,16 @@ typedef struct #define NORFLC_IM_TIMEOUT_Pos 1 #define NORFLC_IM_TIMEOUT_Msk (0x01 << NORFLC_IM_TIMEOUT_Pos) -#define NORFLC_CR_RDTIME_Pos 0 //Oen闁跨喖鎽弬銈嗗闁跨喐鍩呴悮瀛樺闁跨喐鏋婚幏铚傜箮闁跨喓绮搁幉瀣闁跨喐鏋婚幏鐑芥晸閺傘倖瀚圭拠銈夋晸閺傘倖瀚归柨鐔告灮閹风兘鏁撻弬銈嗗闁跨喐鍩呯喊澶嬪闁跨喐鏋婚幏鐑芥晸閹瑰皝妲勯幏锟�0闁跨喐鏋婚幏椋庛仛1闁跨喐鏋婚幏閿嬫闁跨喐鏋婚幏鐑芥晸閺傘倖瀚归柨鐔告灮閹凤拷 +#define NORFLC_CR_RDTIME_Pos 0 //Oen下降沿后多少个时钟周期后采样读回的数据。0表示1个时钟周期 #define NORFLC_CR_RDTIME_Msk (0x1F << NORFLC_CR_RDTIME_Pos) -#define NORFLC_CR_WRTIME_Pos 5 //闁跨喐鏋婚幏鐑芥晸缁插穲n闁跨喍鑼庢担搴ｎ暜閹峰嘲閽╅柨鐔告灮閹峰嘲褰囬柨鐕傛嫹0闁跨喐鏋婚幏椋庛仛1闁跨喐鏋婚幏閿嬫闁跨喐鏋婚幏鐑芥晸閺傘倖瀚归柨鐔告灮閹凤拷 +#define NORFLC_CR_WRTIME_Pos 5 //输出Wen的低电平宽度。0表示1个时钟周期 #define NORFLC_CR_WRTIME_Msk (0x07 << NORFLC_CR_WRTIME_Pos) -#define NORFLC_CR_BYTEIF_Pos 8 //闁跨喕袙闁垷OR FLASH闁跨喐鏋婚幏鐑芥晸閹瑰嘲灏呴幏鐑界伐闁跨噦鎷�1 8娴ｏ拷 0 16娴ｏ拷 +#define NORFLC_CR_BYTEIF_Pos 8 //外部NOR FLASH数据宽度，1 8位 0 16位 #define NORFLC_CR_BYTEIF_Msk (0x01 << NORFLC_CR_BYTEIF_Pos) -#define NORFLC_CMD_DATA_Pos 0 //闁跨喐鏋婚幏绋癛OGRAM闁跨喐鏋婚幏鐑芥晸閺傘倖瀚归柨鐔峰建閿濆繑瀚笵ATA闁跨喐鏋婚幏鐤洣閸愭瑩鏁撻弬銈嗗NOR FLASH闁跨喐鏋婚幏鐑芥晸閺傘倖瀚归柨鐔稿祹閿濆繑瀚归柨鐔告灮閹风úEAD闁跨喐鏋婚幏鐑芥晸閺傘倖瀚归柨鐔峰建閿濆繑瀚笵ATA闁跨喕顫楁潏鐐NOR FLASH闁跨喐鏋婚幏鐑芥晸閹搭亞顣幏鐑芥晸閺傘倖瀚归柨鐔告灮閹凤拷 +#define NORFLC_CMD_DATA_Pos 0 //在PROGRAM命令中，DATA是要写入NOR FLASH的数据；在READ命令中，DATA是从NOR FLASH读回的数据 #define NORFLC_CMD_DATA_Msk (0xFFFF << NORFLC_CMD_DATA_Pos) -#define NORFLC_CMD_CMD_Pos 16 //闁跨喐鏋婚幏鐤洣閹笛囨晸閸欘偆顣幏鐑芥晸閺傘倖瀚归柨鐔虹摂閿涳拷0 READ 1 RESET 2 AUTOMATIC SELECT 3 PROGRAM 4 CHIP ERASE 5 SECTOR ERASE +#define NORFLC_CMD_CMD_Pos 16 //需要执行的命令，0 READ 1 RESET 2 AUTOMATIC SELECT 3 PROGRAM 4 CHIP ERASE 5 SECTOR ERASE #define NORFLC_CMD_CMD_Msk (0x07 << NORFLC_CMD_CMD_Pos) typedef struct @@ -2252,42 +2818,42 @@ typedef struct #define CRC_CR_EN_Pos 0 #define CRC_CR_EN_Msk (0x01 << CRC_CR_EN_Pos) -#define CRC_CR_OREV_Pos 1 //闁跨喐鏋婚幏鐑芥晸閺傘倖瀚归柨鐔告灮閹风兘鏁撶憴鎺戝殩閹风柉娴� +#define CRC_CR_OREV_Pos 1 //输出结果是否翻转 #define CRC_CR_OREV_Msk (0x01 << CRC_CR_OREV_Pos) -#define CRC_CR_ONOT_Pos 2 //闁跨喐鏋婚幏鐑芥晸閺傘倖瀚归柨鐔告灮閹风兘鏁撶憴鎺戝殩閹峰嘲褰囬柨鐔告灮閹凤拷 +#define CRC_CR_ONOT_Pos 2 //输出结果是否取反 #define CRC_CR_ONOT_Msk (0x01 << CRC_CR_ONOT_Pos) #define CRC_CR_CRC16_Pos 3 //1 CRC16 0 CRC32 #define CRC_CR_CRC16_Msk (0x01 << CRC_CR_CRC16_Pos) -#define CRC_CR_IBITS_Pos 4 //闁跨喐鏋婚幏鐑芥晸閺傘倖瀚归柨鐔告灮閹风兘鏁撻弬銈嗗闁跨喐鏋婚幏閿嬫櫏娴ｅ秹鏁撻弬銈嗗 0 32娴ｏ拷 1 16娴ｏ拷 2 8娴ｏ拷 +#define CRC_CR_IBITS_Pos 4 //输入数据有效位数 0 32位 1 16位 2 8位 #define CRC_CR_IBITS_Msk (0x03 << CRC_CR_IBITS_Pos) typedef struct { - __IO uint32_t MINSEC; //闁跨喐鏋婚幏鐑芥晸閺傘倖瀚归柨鐔告灮閹风兘鏁撻敓锟� + __IO uint32_t MINSEC; //分秒计数 - __IO uint32_t DATHUR; //闁跨喐鏋婚幏閿嬫闁跨喐鏋婚幏鐑芥晸閺傘倖瀚� + __IO uint32_t DATHUR; //日时计数 - __IO uint32_t MONDAY; //闁跨喐鏋婚幏鐑芥晸閺夋壆銆嬮幏鐑芥晸閺傘倖瀚� + __IO uint32_t MONDAY; //月周计数 - __IO uint32_t YEAR; //[11:0] 闁跨喐鏋婚幏鐑芥晸閺傘倖瀚归柨鐔告灮閹风兘鏁撶悰妞﹀秵瀚归柨鐕傛嫹1901-2199 + __IO uint32_t YEAR; //[11:0] 年计数，支持1901-2199 - __IO uint32_t MINSECAL; //闁跨喐鏋婚幏鐑芥晸閺傘倖瀚归柨鐔告灮閹风兘鏁撻弬銈嗗闁跨喐鏋婚幏鐑芥晸閺傘倖瀚� + __IO uint32_t MINSECAL; //分秒闹铃设置 - __IO uint32_t DAYHURAL; //闁跨喐鏋婚幏閿嬫闁跨喐鏋婚幏鐑芥晸閺傘倖瀚归柨鐔告灮閹风兘鏁撻弬銈嗗 + __IO uint32_t DAYHURAL; //周时闹铃设置 - __IO uint32_t LOAD; //闁跨喐鏋婚幏鐑芥晸閺傘倖瀚归柨鐔虹叓鐎靛嫯鎻幏鐑芥晸閺傘倖瀚归柨鐔峰建绾板瀚归崐鐓庢倱闁跨喐鏋婚幏鐑芥晸閺傘倖瀚筊TC闁跨喎褰ㄩ敐蹇斿閸氬矂鏁撻弬銈嗗闁跨喐鏋婚幏鐑芥晸閺傘倖瀚规潻婊堟晸閺傘倖瀚归柨鐔告灮閹风兘鏁撻敓锟� + __IO uint32_t LOAD; //将设置寄存器中的值同步到RTC中，同步完成自动清零 __IO uint32_t IE; - __IO uint32_t IF; //閸愶拷1闁跨喐鏋婚幏鐑芥晸閺傘倖瀚� + __IO uint32_t IF; //写1清零 - __IO uint32_t EN; //[0] 1 RTC娴ｅ潡鏁撻弬銈嗗 + __IO uint32_t EN; //[0] 1 RTC使能 - __IO uint32_t CFGABLE; //[0] 1 RTC闁跨喐鏋婚幏鐑芥晸閺傘倖瀚归柨鐔告灮閹凤拷 + __IO uint32_t CFGABLE; //[0] 1 RTC可配置 - __IO uint32_t TRIM; //閺冨爼鏁撻幒銉ь暜閹风兘鏁撻弬銈嗗 + __IO uint32_t TRIM; //时钟调整 - __IO uint32_t TRIMM; //閺冨爼鏁撻弬銈嗗瀵邦噣鏁撻弬銈嗗闁跨喐鏋婚幏锟� + __IO uint32_t TRIMM; //时钟微调整 } RTC_TypeDef; #define RTC_LOAD_TIME_Pos 0 @@ -2295,44 +2861,44 @@ typedef struct #define RTC_LOAD_ALARM_Pos 1 #define RTC_LOAD_ALARM_Msk (0x01 << RTC_LOAD_ALARM_Pos) -#define RTC_MINSEC_SEC_Pos 0 //闁跨喐鏋婚幏鐑芥晸閺傘倖瀚归柨鐕傛嫹 +#define RTC_MINSEC_SEC_Pos 0 //秒计数，取值0--59 #define RTC_MINSEC_SEC_Msk (0x3F << RTC_MINSEC_SEC_Pos) -#define RTC_MINSEC_MIN_Pos 6 //闁跨喐鏋婚幏鐑芥晸閹恒儳銆嬮幏鐑芥晸閺傘倖瀚� +#define RTC_MINSEC_MIN_Pos 6 //分钟计数，取值0--59 #define RTC_MINSEC_MIN_Msk (0x3F << RTC_MINSEC_MIN_Pos) -#define RTC_DATHUR_HOUR_Pos 0 //鐏忓繑妞傞柨鐔告灮閹风兘鏁撻弬銈嗗 +#define RTC_DATHUR_HOUR_Pos 0 //小时计数，取值0--23 #define RTC_DATHUR_HOUR_Msk (0x1F << RTC_DATHUR_HOUR_Pos) -#define RTC_DATHUR_DATE_Pos 5 //date of month +#define RTC_DATHUR_DATE_Pos 5 //date of month，取值1--31 #define RTC_DATHUR_DATE_Msk (0x1F << RTC_DATHUR_DATE_Pos) -#define RTC_MONDAY_DAY_Pos 0 //day of week +#define RTC_MONDAY_DAY_Pos 0 //day of week，取值0--6 #define RTC_MONDAY_DAY_Msk (0x07 << RTC_MONDAY_DAY_Pos) -#define RTC_MONDAY_MON_Pos 3 //闁跨喖鎽禒鐣屻€嬮幏鐑芥晸閺傘倖瀚� +#define RTC_MONDAY_MON_Pos 3 //月份计数，取值1--12 #define RTC_MONDAY_MON_Msk (0x0F << RTC_MONDAY_MON_Pos) -#define RTC_MINSECAL_SEC_Pos 0 //闁跨喐鏋婚幏鐑芥晸閺傘倖瀚归柨鐔告灮閹风兘鏁撻弬銈嗗闁跨喐鏋婚幏锟� +#define RTC_MINSECAL_SEC_Pos 0 //闹钟秒设置 #define RTC_MINSECAL_SEC_Msk (0x3F << RTC_MINSECAL_SEC_Pos) -#define RTC_MINSECAL_MIN_Pos 6 //闁跨喐鏋婚幏鐑芥晸閹恒儱鍤栭幏鐑芥晸閺傘倖瀚归柨鐔告灮閹风兘鏁撻弬銈嗗 +#define RTC_MINSECAL_MIN_Pos 6 //闹钟分钟设置 #define RTC_MINSECAL_MIN_Msk (0x3F << RTC_MINSECAL_MIN_Pos) -#define RTC_DAYHURAL_HOUR_Pos 0 //闁跨喐鏋婚幏鐑芥晸閺傘倖瀚圭亸蹇旀闁跨喐鏋婚幏鐑芥晸閺傘倖瀚� +#define RTC_DAYHURAL_HOUR_Pos 0 //闹钟小时设置 #define RTC_DAYHURAL_HOUR_Msk (0x1F << RTC_DAYHURAL_HOUR_Pos) -#define RTC_DAYHURAL_SUN_Pos 5 //闁跨喐鏋婚幏鐑芥晸閺傘倖瀚归柨鐔告灮閹风兘鏁撻弬銈嗗闁跨喐鏋婚幏閿嬫櫏 +#define RTC_DAYHURAL_SUN_Pos 5 //周日闹钟有效 #define RTC_DAYHURAL_SUN_Msk (0x01 << RTC_DAYHURAL_SUN_Pos) -#define RTC_DAYHURAL_MON_Pos 6 //闁跨喐鏋婚幏铚傜闁跨喐鏋婚幏鐑芥晸閺傘倖瀚归柨鐔告灮閹烽攱鏅� +#define RTC_DAYHURAL_MON_Pos 6 //周一闹钟有效 #define RTC_DAYHURAL_MON_Msk (0x01 << RTC_DAYHURAL_MON_Pos) -#define RTC_DAYHURAL_TUE_Pos 7 //闁跨喐婢冪拋瑙勫闁跨喐鏋婚幏鐑芥晸閺傘倖瀚归柨鐔告灮閹烽攱鏅� +#define RTC_DAYHURAL_TUE_Pos 7 //周二闹钟有效 #define RTC_DAYHURAL_TUE_Msk (0x01 << RTC_DAYHURAL_TUE_Pos) -#define RTC_DAYHURAL_WED_Pos 8 //闁跨喐鏋婚幏鐑芥晸閺傘倖瀚归柨鐔告灮閹风兘鏁撻弬銈嗗闁跨喐鏋婚幏閿嬫櫏 +#define RTC_DAYHURAL_WED_Pos 8 //周三闹钟有效 #define RTC_DAYHURAL_WED_Msk (0x01 << RTC_DAYHURAL_WED_Pos) -#define RTC_DAYHURAL_THU_Pos 9 //闁跨喐鏋婚幏鐑芥晸閺傘倖瀚归柨鐔告灮閹风兘鏁撻弬銈嗗闁跨喐鏋婚幏閿嬫櫏 +#define RTC_DAYHURAL_THU_Pos 9 //周四闹钟有效 #define RTC_DAYHURAL_THU_Msk (0x01 << RTC_DAYHURAL_THU_Pos) -#define RTC_DAYHURAL_FRI_Pos 10 //闁跨喐鏋婚幏鐑芥晸閺傘倖瀚归柨鐔告灮閹风兘鏁撻弬銈嗗闁跨喐鏋婚幏閿嬫櫏 +#define RTC_DAYHURAL_FRI_Pos 10 //周五闹钟有效 #define RTC_DAYHURAL_FRI_Msk (0x01 << RTC_DAYHURAL_FRI_Pos) -#define RTC_DAYHURAL_SAT_Pos 11 //闁跨喐鏋婚幏鐑芥晸閺傘倖瀚归柨鐔告灮閹风兘鏁撻弬銈嗗闁跨喐鏋婚幏閿嬫櫏 +#define RTC_DAYHURAL_SAT_Pos 11 //周六闹钟有效 #define RTC_DAYHURAL_SAT_Msk (0x01 << RTC_DAYHURAL_SAT_Pos) -#define RTC_IE_SEC_Pos 0 //闁跨喐鏋婚幏鐑芥晸閸欘偉顔愰幏铚傚▏闁跨喐鏋婚幏锟� +#define RTC_IE_SEC_Pos 0 //秒中断使能 #define RTC_IE_SEC_Msk (0x01 << RTC_IE_SEC_Pos) #define RTC_IE_MIN_Pos 1 #define RTC_IE_MIN_Msk (0x01 << RTC_IE_MIN_Pos) @@ -2343,7 +2909,7 @@ typedef struct #define RTC_IE_ALARM_Pos 4 #define RTC_IE_ALARM_Msk (0x01 << RTC_IE_ALARM_Pos) -#define RTC_IF_SEC_Pos 0 //閸愶拷1闁跨喐鏋婚幏鐑芥晸閺傘倖瀚� +#define RTC_IF_SEC_Pos 0 //写1清零 #define RTC_IF_SEC_Msk (0x01 << RTC_IF_SEC_Pos) #define RTC_IF_MIN_Pos 1 #define RTC_IF_MIN_Msk (0x01 << RTC_IF_MIN_Pos) @@ -2354,28 +2920,28 @@ typedef struct #define RTC_IF_ALARM_Pos 4 #define RTC_IF_ALARM_Msk (0x01 << RTC_IF_ALARM_Pos) -#define RTC_TRIM_ADJ_Pos 0 //闁跨喐鏋婚幏鐑芥晸閼哄倻顣幏鐑芥晸閺傘倖瀚笲ASECNT闁跨喍鑼庣涵閿嬪闁跨喐鏋婚幏鐑芥晸閺傘倖瀚归柨鐔诲Ν閿濆繑瀚规姗€鏁撻弬銈嗗娑擄拷32768闁跨喐鏋婚幏鐑芥晸閺傘倖瀚归柨鐔烘たEC娑擄拷1闁跨喐鏋婚幏鐑芥晸閺傘倖瀚归柨鐔告灮閹风兘鏁撻弬銈嗗闁跨喐鏋婚幏鐤樁闁跨喐鏋婚幏鐑芥晸鏉炲尅鎷�32768-ADJ闁跨喐鏋婚幏鐑芥晸閺傘倖瀚归柨鐔告灮閹风兘鏁撻弬銈嗗闁跨喕濞囬敓锟�32768+ADJ +#define RTC_TRIM_ADJ_Pos 0 //用于调整BASECNT的计数周期，默认为32768，如果DEC为1，则计数周期调整为32768-ADJ，否则调整为32768+ADJ #define RTC_TRIM_ADJ_Msk (0xFF << RTC_TRIM_ADJ_Pos) #define RTC_TRIM_DEC_Pos 8 #define RTC_TRIM_DEC_Msk (0x01 << RTC_TRIM_DEC_Pos) -#define RTC_TRIMM_CYCLE_Pos 0 //闁跨喐鏋婚幏鐑芥晸閼哄倻銆嬮幏鐑芥晸閺傘倖瀚归柨鐔告灮閹风兘鏁撻弬銈嗗瀵邦噣鏁撻弬銈嗗闁跨喐鏋婚幏鐑芥晸閺傘倖瀚归柨鐔虹イNC娑擄拷1闁跨喐鏋婚幏鐑芥晸閺傘倖瀚归柨鐔哄崟闁跨喐鏋婚幏鐑芥晸閺傘倖瀚归柨鐔告灮閹风兘鏁撻弬銈嗗闁跨喕濡喊澶嬪闁跨喐鏋婚幏铚傝礋(32768闁跨喐鏋婚幏绋烡J)+1,闁跨喐鏋婚幏鐑芥晸閺傘倖瀚归柨鐔告灮閹风兘鏁撴潪鍖℃嫹(32768闁跨喐鏋婚幏绋烡J)-1 -//cycles=0閺冨爼鏁撻弬銈嗗闁跨喐鏋婚幏鐑芥晸閺傘倖瀚归柨鐔告灮閹峰嘲浜曢柨鐔告灮閹风兘鏁撻弬銈嗗闁跨喐鏋婚幏绌媦cles=1闁跨喐鏋婚幏鐑芥晸閺傘倖瀚筺娑擄拷2闁跨喐鏋婚幏绌媦cles=7闁跨喐鏋婚幏鐑芥晸閺傘倖瀚筺娑擄拷8闁跨喐鏋婚幏鐑芥晸閻ㄥ棜鎻幏鐑芥晸閺傘倖瀚归柨鐔告灮閹凤拷 +#define RTC_TRIMM_CYCLE_Pos 0 /* 用于计数周期微调，如果INC为1，则第n个计数周期调整为(32768±ADJ)+1,否则调整为(32768±ADJ)-1 \ + //cycles=0时，不进行微调整；cycles=1，则n为2；cycles=7，则n为8；以此类推 */ #define RTC_TRIMM_CYCLE_Msk (0x07 << RTC_TRIMM_CYCLE_Pos) #define RTC_TRIMM_INC_Pos 3 #define RTC_TRIMM_INC_Msk (0x01 << RTC_TRIMM_INC_Pos) typedef struct { - __IO uint32_t LOAD; //閸犲倿鏁撻弬銈嗗娴ｅ潡鏁撻弬銈嗗闁跨喐鏋婚幏鐑芥晸閺傘倖瀚圭憗鍛存晸閺傘倖瀚筁OAD閸婏拷 + __IO uint32_t LOAD; //喂狗使计数器装载LOAD值 __I uint32_t VALUE; __IO uint32_t CR; - __IO uint32_t IF; //闁跨喐鏋婚幏鐑芥晸閺傘倖瀚归柨鐔告灮閹凤拷0閺冨墎鈥栭柨鐔告灮閹风兘鏁撻弬銈嗗娴ｅ秹鏁撻弬銈嗗闁跨喐鏋婚幏鐑芥晸閸欘偓鎷�1闁跨喐鏋婚幏鐑芥晸閺傘倖瀚归柨鐔活敎閿燂拷 + __IO uint32_t IF; //计数到0时硬件置位，软件写1清除标志 - __IO uint32_t FEED; //閸愶拷0x55閸犲倿鏁撻弬銈嗗 + __IO uint32_t FEED; //写0x55喂狗 } WDT_TypeDef; #define WDT_CR_EN_Pos 0 @@ -2525,6 +3091,8 @@ typedef struct #define SDRAMC ((SDRAMC_TypeDef *)SDRAMC_BASE) +typedef void (*Func_void_void)(void); + #include "SWM320_port.h" #include "SWM320_gpio.h" #include "SWM320_exti.h" @@ -2541,6 +3109,7 @@ typedef struct #include "SWM320_flash.h" #include "SWM320_norflash.h" #include "SWM320_sdram.h" +#include "SWM320_sram.h" #include "SWM320_crc.h" #include "SWM320_rtc.h" #include "SWM320_wdt.h" diff --git a/bsp/swm320-lq100/Libraries/CMSIS/DeviceSupport/startup/arm/startup_SWM320.s b/bsp/swm320-lq100/Libraries/CMSIS/DeviceSupport/startup/arm/startup_SWM320.s index 025782b081..1a16ebc768 100644 --- a/bsp/swm320-lq100/Libraries/CMSIS/DeviceSupport/startup/arm/startup_SWM320.s +++ b/bsp/swm320-lq100/Libraries/CMSIS/DeviceSupport/startup/arm/startup_SWM320.s @@ -1,10 +1,10 @@ ;****************************************************************************************************************************************** -; �ļ�����: startup_SWM2400.s -; ����˵��: SWM2400��Ƭ���������ļ� -; ����֧��: http://www.synwit.com.cn/e/tool/gbook/?bid=1 -; ע������: -; �汾����: V1.1.0 2017��10��25�� -; ������¼: +; 文件名称: startup_SWM320.s +; 功能说明: SWM2400单片机的启动文件 +; 技术支持: http://www.synwit.com.cn/e/tool/gbook/?bid=1 +; 注意事项: +; 版本日期: V1.1.0 2017年10月25日 +; 升级记录: ; ; ;****************************************************************************************************************************************** @@ -25,7 +25,7 @@ ; <o> Stack Size (in Bytes) <0x0-0xFFFFFFFF:8> ; </h> -Stack_Size EQU 0x00000400 +Stack_Size EQU 0x00001000 AREA STACK, NOINIT, READWRITE, ALIGN=3 Stack_Mem SPACE Stack_Size @@ -36,7 +36,7 @@ __initial_sp ; <o> Heap Size (in Bytes) <0x0-0xFFFFFFFF:8> ; </h> -Heap_Size EQU 0x00000200 +Heap_Size EQU 0x00000000 AREA HEAP, NOINIT, READWRITE, ALIGN=3 __heap_base @@ -94,7 +94,7 @@ __Vectors DCD __initial_sp ; Top of Stack DCD GPIOC4_Handler DCD GPIOC5_Handler DCD GPIOC6_Handler - DCD GPIOC7_Handler + DCD GPIOC7_Handler DCD GPIOM0_Handler DCD GPIOM1_Handler DCD GPIOM2_Handler @@ -102,25 +102,25 @@ __Vectors DCD __initial_sp ; Top of Stack DCD GPIOM4_Handler DCD GPIOM5_Handler DCD GPIOM6_Handler - DCD GPIOM7_Handler - DCD DMA_Handler + DCD GPIOM7_Handler + DCD DMA_Handler DCD LCD_Handler DCD NORFLC_Handler - DCD CAN_Handler + DCD CAN_Handler DCD PULSE_Handler DCD WDT_Handler DCD PWM_Handler DCD UART0_Handler - DCD UART1_Handler - DCD UART2_Handler - DCD UART3_Handler - DCD 0 - DCD I2C0_Handler + DCD UART1_Handler + DCD UART2_Handler + DCD UART3_Handler + DCD 0 + DCD I2C0_Handler DCD I2C1_Handler DCD SPI0_Handler DCD ADC0_Handler DCD RTC_Handler - DCD ANAC_Handler + DCD BOD_Handler DCD SDIO_Handler DCD GPIOA_Handler DCD GPIOB_Handler @@ -130,13 +130,13 @@ __Vectors DCD __initial_sp ; Top of Stack DCD GPIOP_Handler DCD ADC1_Handler DCD FPU_Handler - DCD SPI1_Handler - DCD TIMR0_Handler - DCD TIMR1_Handler - DCD TIMR2_Handler - DCD TIMR3_Handler - DCD TIMR4_Handler - DCD TIMR5_Handler + DCD SPI1_Handler + DCD TIMR0_Handler + DCD TIMR1_Handler + DCD TIMR2_Handler + DCD TIMR3_Handler + DCD TIMR4_Handler + DCD TIMR5_Handler __Vectors_End @@ -157,262 +157,262 @@ Reset_Handler PROC ; Dummy Exception Handlers (infinite loops which can be modified) NMI_Handler PROC - EXPORT NMI_Handler [WEAK] + EXPORT NMI_Handler [WEAK] B . ENDP HardFault_Handler PROC - EXPORT HardFault_Handler [WEAK] + EXPORT HardFault_Handler [WEAK] B . ENDP MemManage_Handler PROC - EXPORT MemManage_Handler [WEAK] + EXPORT MemManage_Handler [WEAK] B . ENDP BusFault_Handler PROC - EXPORT BusFault_Handler [WEAK] + EXPORT BusFault_Handler [WEAK] B . ENDP UsageFault_Handler PROC - EXPORT UsageFault_Handler [WEAK] + EXPORT UsageFault_Handler [WEAK] B . ENDP SVC_Handler PROC - EXPORT SVC_Handler [WEAK] + EXPORT SVC_Handler [WEAK] B . ENDP DebugMon_Handler PROC - EXPORT DebugMon_Handler [WEAK] + EXPORT DebugMon_Handler [WEAK] B . ENDP PendSV_Handler PROC - EXPORT PendSV_Handler [WEAK] + EXPORT PendSV_Handler [WEAK] B . ENDP SysTick_Handler PROC - EXPORT SysTick_Handler [WEAK] + EXPORT SysTick_Handler [WEAK] B . ENDP GPIOA0_Handler PROC - EXPORT GPIOA0_Handler [WEAK] + EXPORT GPIOA0_Handler [WEAK] B . ENDP GPIOA1_Handler PROC - EXPORT GPIOA1_Handler [WEAK] + EXPORT GPIOA1_Handler [WEAK] B . ENDP GPIOA2_Handler PROC - EXPORT GPIOA2_Handler [WEAK] + EXPORT GPIOA2_Handler [WEAK] B . ENDP GPIOA3_Handler PROC - EXPORT GPIOA3_Handler [WEAK] + EXPORT GPIOA3_Handler [WEAK] B . ENDP GPIOA4_Handler PROC - EXPORT GPIOA4_Handler [WEAK] + EXPORT GPIOA4_Handler [WEAK] B . ENDP GPIOA5_Handler PROC - EXPORT GPIOA5_Handler [WEAK] + EXPORT GPIOA5_Handler [WEAK] B . ENDP GPIOA6_Handler PROC - EXPORT GPIOA6_Handler [WEAK] + EXPORT GPIOA6_Handler [WEAK] B . ENDP GPIOA7_Handler PROC - EXPORT GPIOA7_Handler [WEAK] + EXPORT GPIOA7_Handler [WEAK] B . ENDP GPIOB0_Handler PROC - EXPORT GPIOB0_Handler [WEAK] + EXPORT GPIOB0_Handler [WEAK] B . ENDP GPIOB1_Handler PROC - EXPORT GPIOB1_Handler [WEAK] + EXPORT GPIOB1_Handler [WEAK] B . ENDP GPIOB2_Handler PROC - EXPORT GPIOB2_Handler [WEAK] + EXPORT GPIOB2_Handler [WEAK] B . ENDP GPIOB3_Handler PROC - EXPORT GPIOB3_Handler [WEAK] + EXPORT GPIOB3_Handler [WEAK] B . ENDP GPIOB4_Handler PROC - EXPORT GPIOB4_Handler [WEAK] + EXPORT GPIOB4_Handler [WEAK] B . ENDP GPIOB5_Handler PROC - EXPORT GPIOB5_Handler [WEAK] + EXPORT GPIOB5_Handler [WEAK] B . ENDP GPIOB6_Handler PROC - EXPORT GPIOB6_Handler [WEAK] + EXPORT GPIOB6_Handler [WEAK] B . ENDP GPIOB7_Handler PROC - EXPORT GPIOB7_Handler [WEAK] + EXPORT GPIOB7_Handler [WEAK] B . ENDP GPIOC0_Handler PROC - EXPORT GPIOC0_Handler [WEAK] + EXPORT GPIOC0_Handler [WEAK] B . ENDP GPIOC1_Handler PROC - EXPORT GPIOC1_Handler [WEAK] + EXPORT GPIOC1_Handler [WEAK] B . ENDP GPIOC2_Handler PROC - EXPORT GPIOC2_Handler [WEAK] + EXPORT GPIOC2_Handler [WEAK] B . ENDP GPIOC3_Handler PROC - EXPORT GPIOC3_Handler [WEAK] + EXPORT GPIOC3_Handler [WEAK] B . ENDP GPIOC4_Handler PROC - EXPORT GPIOC4_Handler [WEAK] + EXPORT GPIOC4_Handler [WEAK] B . ENDP GPIOC5_Handler PROC - EXPORT GPIOC5_Handler [WEAK] + EXPORT GPIOC5_Handler [WEAK] B . ENDP GPIOC6_Handler PROC - EXPORT GPIOC6_Handler [WEAK] + EXPORT GPIOC6_Handler [WEAK] B . ENDP GPIOC7_Handler PROC - EXPORT GPIOC7_Handler [WEAK] + EXPORT GPIOC7_Handler [WEAK] B . ENDP GPIOM0_Handler PROC - EXPORT GPIOM0_Handler [WEAK] + EXPORT GPIOM0_Handler [WEAK] B . ENDP GPIOM1_Handler PROC - EXPORT GPIOM1_Handler [WEAK] + EXPORT GPIOM1_Handler [WEAK] B . ENDP GPIOM2_Handler PROC - EXPORT GPIOM2_Handler [WEAK] + EXPORT GPIOM2_Handler [WEAK] B . ENDP GPIOM3_Handler PROC - EXPORT GPIOM3_Handler [WEAK] + EXPORT GPIOM3_Handler [WEAK] B . ENDP GPIOM4_Handler PROC - EXPORT GPIOM4_Handler [WEAK] + EXPORT GPIOM4_Handler [WEAK] B . ENDP GPIOM5_Handler PROC - EXPORT GPIOM5_Handler [WEAK] + EXPORT GPIOM5_Handler [WEAK] B . ENDP GPIOM6_Handler PROC - EXPORT GPIOM6_Handler [WEAK] + EXPORT GPIOM6_Handler [WEAK] B . ENDP GPIOM7_Handler PROC - EXPORT GPIOM7_Handler [WEAK] + EXPORT GPIOM7_Handler [WEAK] B . ENDP DMA_Handler PROC - EXPORT DMA_Handler [WEAK] + EXPORT DMA_Handler [WEAK] B . ENDP LCD_Handler PROC - EXPORT LCD_Handler [WEAK] + EXPORT LCD_Handler [WEAK] B . ENDP NORFLC_Handler PROC - EXPORT NORFLC_Handler [WEAK] + EXPORT NORFLC_Handler [WEAK] B . ENDP CAN_Handler PROC - EXPORT CAN_Handler [WEAK] + EXPORT CAN_Handler [WEAK] B . ENDP PULSE_Handler PROC - EXPORT PULSE_Handler [WEAK] + EXPORT PULSE_Handler [WEAK] B . ENDP WDT_Handler PROC - EXPORT WDT_Handler [WEAK] + EXPORT WDT_Handler [WEAK] B . ENDP PWM_Handler PROC - EXPORT PWM_Handler [WEAK] + EXPORT PWM_Handler [WEAK] B . ENDP UART0_Handler PROC - EXPORT UART0_Handler [WEAK] + EXPORT UART0_Handler [WEAK] B . ENDP UART1_Handler PROC - EXPORT UART1_Handler [WEAK] + EXPORT UART1_Handler [WEAK] B . ENDP UART2_Handler PROC - EXPORT UART2_Handler [WEAK] + EXPORT UART2_Handler [WEAK] B . ENDP UART3_Handler PROC - EXPORT UART3_Handler [WEAK] + EXPORT UART3_Handler [WEAK] B . ENDP @@ -437,12 +437,12 @@ ADC0_Handler PROC ENDP RTC_Handler PROC - EXPORT RTC_Handler [WEAK] + EXPORT RTC_Handler [WEAK] B . ENDP -ANAC_Handler PROC - EXPORT ANAC_Handler [WEAK] +BOD_Handler PROC + EXPORT BOD_Handler [WEAK] B . ENDP @@ -452,32 +452,32 @@ SDIO_Handler PROC ENDP GPIOA_Handler PROC - EXPORT GPIOA_Handler [WEAK] + EXPORT GPIOA_Handler [WEAK] B . ENDP GPIOB_Handler PROC - EXPORT GPIOB_Handler [WEAK] + EXPORT GPIOB_Handler [WEAK] B . ENDP GPIOC_Handler PROC - EXPORT GPIOC_Handler [WEAK] + EXPORT GPIOC_Handler [WEAK] B . ENDP GPIOM_Handler PROC - EXPORT GPIOM_Handler [WEAK] + EXPORT GPIOM_Handler [WEAK] B . ENDP GPION_Handler PROC - EXPORT GPION_Handler [WEAK] + EXPORT GPION_Handler [WEAK] B . ENDP GPIOP_Handler PROC - EXPORT GPIOP_Handler [WEAK] + EXPORT GPIOP_Handler [WEAK] B . ENDP @@ -487,7 +487,7 @@ ADC1_Handler PROC ENDP FPU_Handler PROC - EXPORT FPU_Handler [WEAK] + EXPORT FPU_Handler [WEAK] B . ENDP diff --git a/bsp/swm320-lq100/Libraries/CMSIS/DeviceSupport/startup/iar/startup_SWM320.s b/bsp/swm320-lq100/Libraries/CMSIS/DeviceSupport/startup/iar/startup_SWM320.s index baecc70d02..a7a4d89f50 100644 --- a/bsp/swm320-lq100/Libraries/CMSIS/DeviceSupport/startup/iar/startup_SWM320.s +++ b/bsp/swm320-lq100/Libraries/CMSIS/DeviceSupport/startup/iar/startup_SWM320.s @@ -57,7 +57,7 @@ __vector_table DCD GPIOA5_Handler DCD GPIOA6_Handler DCD GPIOA7_Handler - DCD GPIOB0_Handler + DCD GPIOB0_Handler DCD GPIOB1_Handler DCD GPIOB2_Handler DCD GPIOB3_Handler @@ -72,7 +72,7 @@ __vector_table DCD GPIOC4_Handler DCD GPIOC5_Handler DCD GPIOC6_Handler - DCD GPIOC7_Handler + DCD GPIOC7_Handler DCD GPIOM0_Handler DCD GPIOM1_Handler DCD GPIOM2_Handler @@ -80,25 +80,25 @@ __vector_table DCD GPIOM4_Handler DCD GPIOM5_Handler DCD GPIOM6_Handler - DCD GPIOM7_Handler - DCD DMA_Handler + DCD GPIOM7_Handler + DCD DMA_Handler DCD LCD_Handler DCD NORFLC_Handler - DCD CAN_Handler - DCD TIMR_Handler + DCD CAN_Handler + DCD PULSE_Handler DCD WDT_Handler DCD PWM_Handler DCD UART0_Handler - DCD UART1_Handler - DCD UART2_Handler - DCD UART3_Handler - DCD 0 - DCD I2C0_Handler + DCD UART1_Handler + DCD UART2_Handler + DCD UART3_Handler + DCD 0 + DCD I2C0_Handler DCD I2C1_Handler DCD SPI0_Handler DCD ADC0_Handler DCD RTC_Handler - DCD ANAC_Handler + DCD BOD_Handler DCD SDIO_Handler DCD GPIOA_Handler DCD GPIOB_Handler @@ -108,7 +108,13 @@ __vector_table DCD GPIOP_Handler DCD ADC1_Handler DCD FPU_Handler - DCD SPI1_Handler + DCD SPI1_Handler + DCD TIMR0_Handler + DCD TIMR1_Handler + DCD TIMR2_Handler + DCD TIMR3_Handler + DCD TIMR4_Handler + DCD TIMR5_Handler THUMB @@ -345,10 +351,10 @@ NORFLC_Handler CAN_Handler B CAN_Handler - PUBWEAK TIMR_Handler + PUBWEAK PULSE_Handler SECTION .text:CODE:REORDER:NOROOT(1) -TIMR_Handler - B TIMR_Handler +PULSE_Handler + B PULSE_Handler PUBWEAK WDT_Handler SECTION .text:CODE:REORDER:NOROOT(1) @@ -405,10 +411,10 @@ ADC0_Handler RTC_Handler B RTC_Handler - PUBWEAK ANAC_Handler + PUBWEAK BOD_Handler SECTION .text:CODE:REORDER:NOROOT(1) -ANAC_Handler - B ANAC_Handler +BOD_Handler + B BOD_Handler PUBWEAK SDIO_Handler SECTION .text:CODE:REORDER:NOROOT(1) @@ -459,6 +465,36 @@ FPU_Handler SECTION .text:CODE:REORDER:NOROOT(1) SPI1_Handler B SPI1_Handler + + PUBWEAK TIMR0_Handler + SECTION .text:CODE:REORDER:NOROOT(1) +TIMR0_Handler + B TIMR0_Handler + + PUBWEAK TIMR1_Handler + SECTION .text:CODE:REORDER:NOROOT(1) +TIMR1_Handler + B TIMR1_Handler + + PUBWEAK TIMR2_Handler + SECTION .text:CODE:REORDER:NOROOT(1) +TIMR2_Handler + B TIMR2_Handler + + PUBWEAK TIMR3_Handler + SECTION .text:CODE:REORDER:NOROOT(1) +TIMR3_Handler + B TIMR3_Handler + + PUBWEAK TIMR4_Handler + SECTION .text:CODE:REORDER:NOROOT(1) +TIMR4_Handler + B TIMR4_Handler + + PUBWEAK TIMR5_Handler + SECTION .text:CODE:REORDER:NOROOT(1) +TIMR5_Handler + B TIMR5_Handler END diff --git a/bsp/swm320-lq100/Libraries/CMSIS/DeviceSupport/system_SWM320.c b/bsp/swm320-lq100/Libraries/CMSIS/DeviceSupport/system_SWM320.c index d6e7c61809..578d15da79 100644 --- a/bsp/swm320-lq100/Libraries/CMSIS/DeviceSupport/system_SWM320.c +++ b/bsp/swm320-lq100/Libraries/CMSIS/DeviceSupport/system_SWM320.c @@ -38,14 +38,15 @@ #define SYS_CLK_DIV SYS_CLK_DIV_1 #define __HSI (20000000UL) //高速内部时钟 -#define __LSI (32000UL) //低速内部时钟 +#define __LSI (32000UL) //低速内部时钟 #define __HSE (20000000UL) //高速外部时钟 /********************************** PLL 设定 ********************************************** * VCO输出频率 = PLL输入时钟 / INDIV * 4 * FBDIV * PLL输出频率 = PLL输入时钟 / INDIV * 4 * FBDIV / OUTDIV = VCO输出频率 / OUTDIV + * 注意：VCO输出频率需要在 [600MHz, 1200MHz] 之间 *****************************************************************************************/ -#define SYS_PLL_SRC SYS_CLK_XTAL //可取值SYS_CLK_20MHz、SYS_CLK_XTAL +#define SYS_PLL_SRC SYS_CLK_20MHz //可取值SYS_CLK_20MHz、SYS_CLK_XTAL #define PLL_IN_DIV 5 @@ -57,8 +58,8 @@ #define PLL_OUT_DIV PLL_OUT_DIV8 -uint32_t SystemCoreClock = (120000000UL); //System Clock Frequency (Core Clock) -uint32_t CyclesPerUs = ((120000000UL) / 1000000); //Cycles per micro second +uint32_t SystemCoreClock = __HSI; //System Clock Frequency (Core Clock) +uint32_t CyclesPerUs = (__HSI / 1000000); //Cycles per micro second /****************************************************************************************************************************************** * 函数名称: @@ -110,6 +111,8 @@ void SystemCoreClockUpdate(void) if (SYS->CLKDIV & SYS_CLKDIV_SYS_Msk) SystemCoreClock /= 2; + + CyclesPerUs = SystemCoreClock / 1000000; } /****************************************************************************************************************************************** @@ -121,56 +124,30 @@ void SystemCoreClockUpdate(void) ******************************************************************************************************************************************/ void SystemInit(void) { - uint32_t i; - SYS->CLKEN |= (1 << SYS_CLKEN_ANAC_Pos); + Flash_Param_at_xMHz(120); + switch (SYS_CLK) { case SYS_CLK_20MHz: //0 内部高频20MHz RC振荡器 - SYS->HRCCR = (0 << SYS_HRCCR_OFF_Pos) | - (0 << SYS_HRCCR_DBL_Pos); //HRC = 20MHz - - SYS->CLKSEL &= ~SYS_CLKSEL_HFCK_Msk; //HFCK <= HRC - SYS->CLKSEL |= (1 << SYS_CLKSEL_SYS_Pos); //SYS_CLK <= HFCK + switchCLK_20MHz(); break; case SYS_CLK_40MHz: //1 内部高频40MHz RC振荡器 - SYS->HRCCR = (0 << SYS_HRCCR_OFF_Pos) | - (1 << SYS_HRCCR_DBL_Pos); //HRC = 40MHz - - SYS->CLKSEL &= ~SYS_CLKSEL_HFCK_Msk; //HFCK <= HRC - SYS->CLKSEL |= (1 << SYS_CLKSEL_SYS_Pos); //SYS_CLK <= HFCK + switchCLK_40MHz(); break; case SYS_CLK_32KHz: //2 内部低频32KHz RC振荡器 - SYS->CLKEN |= (1 << SYS_CLKEN_RTCBKP_Pos); - - SYS->LRCCR &= ~(1 << SYS_LRCCR_OFF_Pos); - - for (i = 0; i < 20000; i++) - ; - - SYS->CLKSEL &= ~SYS_CLKSEL_LFCK_Msk; //LFCK <= LRC - SYS->CLKSEL &= ~SYS_CLKSEL_SYS_Msk; //SYS_CLK <= LFCK + switchCLK_32KHz(); break; case SYS_CLK_XTAL: //3 外部晶体振荡器（2-30MHz） - SYS->XTALCR = (1 << SYS_XTALCR_EN_Pos); - - for (i = 0; i < 20000; i++) - ; - - SYS->CLKSEL |= (1 << SYS_CLKSEL_HFCK_Pos); //HFCK <= XTAL - SYS->CLKSEL |= (1 << SYS_CLKSEL_SYS_Pos); //SYS_CLK <= HFCK + switchCLK_XTAL(); break; case SYS_CLK_PLL: //4 片内锁相环输出 - PLLInit(); - SYS->PLLCR |= (1 << SYS_PLLCR_OUTEN_Pos); - - SYS->CLKSEL |= (1 << SYS_CLKSEL_LFCK_Pos); //LFCK <= PLL - SYS->CLKSEL &= ~SYS_CLKSEL_SYS_Msk; //SYS_CLK <= LFCK + switchCLK_PLL(); break; } @@ -178,25 +155,114 @@ void SystemInit(void) SYS->CLKDIV |= (SYS_CLK_DIV << SYS_CLKDIV_SYS_Pos); SystemCoreClockUpdate(); + + if (SystemCoreClock > 80000000) + { + Flash_Param_at_xMHz(120); + } + else if (SystemCoreClock > 40000000) + { + Flash_Param_at_xMHz(80); + } + else if (SystemCoreClock > 30000000) + { + Flash_Param_at_xMHz(40); + } + else + { + Flash_Param_at_xMHz(30); + } } -void PLLInit(void) +static void delay_3ms(void) { uint32_t i; + if (((SYS->CLKSEL & SYS_CLKSEL_SYS_Msk) == 0) && + ((SYS->CLKSEL & SYS_CLKSEL_LFCK_Msk) == 0)) //32KHz + { + for (i = 0; i < 20; i++) + __NOP(); + } + else + { + for (i = 0; i < 20000; i++) + __NOP(); + } +} + +void switchCLK_20MHz(void) +{ + SYS->HRCCR = (0 << SYS_HRCCR_OFF_Pos) | + (0 << SYS_HRCCR_DBL_Pos); //HRC = 20MHz + + delay_3ms(); + + SYS->CLKSEL &= ~SYS_CLKSEL_HFCK_Msk; //HFCK <= HRC + SYS->CLKSEL |= (1 << SYS_CLKSEL_SYS_Pos); //SYS_CLK <= HFCK +} + +void switchCLK_40MHz(void) +{ + SYS->HRCCR = (0 << SYS_HRCCR_OFF_Pos) | + (1 << SYS_HRCCR_DBL_Pos); //HRC = 40MHz + + delay_3ms(); + + SYS->CLKSEL &= ~SYS_CLKSEL_HFCK_Msk; //HFCK <= HRC + SYS->CLKSEL |= (1 << SYS_CLKSEL_SYS_Pos); //SYS_CLK <= HFCK +} + +void switchCLK_32KHz(void) +{ + SYS->CLKEN |= (1 << SYS_CLKEN_RTCBKP_Pos); + + SYS->LRCCR &= ~(1 << SYS_LRCCR_OFF_Pos); + + delay_3ms(); + + SYS->CLKSEL &= ~SYS_CLKSEL_LFCK_Msk; //LFCK <= LRC + SYS->CLKSEL &= ~SYS_CLKSEL_SYS_Msk; //SYS_CLK <= LFCK +} + +void switchCLK_XTAL(void) +{ + SYS->XTALCR = (1 << SYS_XTALCR_EN_Pos); + + delay_3ms(); + delay_3ms(); + + SYS->CLKSEL |= (1 << SYS_CLKSEL_HFCK_Pos); //HFCK <= XTAL + SYS->CLKSEL |= (1 << SYS_CLKSEL_SYS_Pos); //SYS_CLK <= HFCK +} + +void switchCLK_PLL(void) +{ + PLLInit(); + + SYS->PLLCR |= (1 << SYS_PLLCR_OUTEN_Pos); + + SYS->CLKSEL |= (1 << SYS_CLKSEL_LFCK_Pos); //LFCK <= PLL + SYS->CLKSEL &= ~SYS_CLKSEL_SYS_Msk; //SYS_CLK <= LFCK +} + +void PLLInit(void) +{ if (SYS_PLL_SRC == SYS_CLK_20MHz) { SYS->HRCCR = (0 << SYS_HRCCR_OFF_Pos) | (0 << SYS_HRCCR_DBL_Pos); //HRC = 20MHz + delay_3ms(); + SYS->PLLCR |= (1 << SYS_PLLCR_INSEL_Pos); //PLL_SRC <= HRC } else if (SYS_PLL_SRC == SYS_CLK_XTAL) { SYS->XTALCR = (1 << SYS_XTALCR_EN_Pos); - for (i = 0; i < 20000; i++) - ; + delay_3ms(); + delay_3ms(); SYS->PLLCR &= ~(1 << SYS_PLLCR_INSEL_Pos); //PLL_SRC <= XTAL } diff --git a/bsp/swm320-lq100/Libraries/CMSIS/DeviceSupport/system_SWM320.h b/bsp/swm320-lq100/Libraries/CMSIS/DeviceSupport/system_SWM320.h index 4f44ccd3ab..4db7f29433 100644 --- a/bsp/swm320-lq100/Libraries/CMSIS/DeviceSupport/system_SWM320.h +++ b/bsp/swm320-lq100/Libraries/CMSIS/DeviceSupport/system_SWM320.h @@ -2,20 +2,24 @@ #define __SYSTEM_SWM320_H__ #ifdef __cplusplus -extern "C" { +extern "C" +{ #endif + extern uint32_t SystemCoreClock; // System Clock Frequency (Core Clock) + extern uint32_t CyclesPerUs; // Cycles per micro second -extern uint32_t SystemCoreClock; // System Clock Frequency (Core Clock) -extern uint32_t CyclesPerUs; // Cycles per micro second + extern void SystemInit(void); + extern void SystemCoreClockUpdate(void); -extern void SystemInit(void); - -extern void SystemCoreClockUpdate(void); - -extern void PLLInit(void); + extern void switchCLK_20MHz(void); + extern void switchCLK_40MHz(void); + extern void switchCLK_32KHz(void); + extern void switchCLK_XTAL(void); + extern void switchCLK_PLL(void); + extern void PLLInit(void); #ifdef __cplusplus } diff --git a/bsp/swm320-lq100/Libraries/SWM320_StdPeriph_Driver/SWM320_adc.c b/bsp/swm320-lq100/Libraries/SWM320_StdPeriph_Driver/SWM320_adc.c index d6c48b10d4..0fcd4d1eb1 100644 --- a/bsp/swm320-lq100/Libraries/SWM320_StdPeriph_Driver/SWM320_adc.c +++ b/bsp/swm320-lq100/Libraries/SWM320_StdPeriph_Driver/SWM320_adc.c @@ -22,7 +22,7 @@ /****************************************************************************************************************************************** * 函数名称: ADC_Init() * 功能说明: ADC模数转换器初始化 -* 输 入: ADC_TypeDef * ADCx 指定要被设置的ADC，有效值包括ADC0、ADC1 +* 输 入: ADC_TypeDef * ADCx 指定要被设置的ADC，有效值包括ADC0、ADC1 * ADC_InitStructure * initStruct 包含ADC各相关定值的结构体 * 输 出: 无 * 注意事项: 无 @@ -63,9 +63,12 @@ void ADC_Init(ADC_TypeDef *ADCx, ADC_InitStructure *initStruct) SYS->PLLDIV |= (initStruct->clk_div << SYS_PLLDIV_ADDIV_Pos); } + ADCx->CALIBSET = (ADCx == ADC0) ? SYS->BKP[0] : SYS->BKP[1]; + ADCx->CALIBEN = (1 << ADC_CALIBEN_OFFSET_Pos) | (1 << ADC_CALIBEN_K_Pos); + ADCx->CTRL2 &= ~(ADC_CTRL2_ADCEVCM_Msk | ADC_CTRL2_PGAIVCM_Msk | ADC_CTRL2_PGAGAIN_Msk | ADC_CTRL2_PGAVCM_Msk); ADCx->CTRL2 |= (0 << ADC_CTRL2_ADCEVCM_Pos) | - (PGA_VCM_INTERNAL << ADC_CTRL2_PGAIVCM_Pos) | + (initStruct->pga_ref << ADC_CTRL2_PGAIVCM_Pos) | (6 << ADC_CTRL2_PGAGAIN_Pos) | ((uint32_t)6 << ADC_CTRL2_PGAVCM_Pos); @@ -152,7 +155,7 @@ void ADC_Init(ADC_TypeDef *ADCx, ADC_InitStructure *initStruct) /****************************************************************************************************************************************** * 函数名称: ADC_Open() * 功能说明: ADC开启，可以软件启动、或硬件触发ADC转换 -* 输 入: ADC_TypeDef * ADCx 指定要被设置的ADC，可取值包括ADC +* 输 入: ADC_TypeDef * ADCx 指定要被设置的ADC，可取值包括ADC * 输 出: 无 * 注意事项: 无 ******************************************************************************************************************************************/ @@ -164,7 +167,7 @@ void ADC_Open(ADC_TypeDef *ADCx) /****************************************************************************************************************************************** * 函数名称: ADC_Close() * 功能说明: ADC关闭，无法软件启动、或硬件触发ADC转换 -* 输 入: ADC_TypeDef * ADCx 指定要被设置的ADC，可取值包括ADC +* 输 入: ADC_TypeDef * ADCx 指定要被设置的ADC，可取值包括ADC * 输 出: 无 * 注意事项: 无 ******************************************************************************************************************************************/ @@ -176,7 +179,7 @@ void ADC_Close(ADC_TypeDef *ADCx) /****************************************************************************************************************************************** * 函数名称: ADC_Start() * 功能说明: 软件触发模式下启动ADC转换 -* 输 入: ADC_TypeDef * ADCx 指定要被设置的ADC，可取值包括ADC +* 输 入: ADC_TypeDef * ADCx 指定要被设置的ADC，可取值包括ADC * 输 出: 无 * 注意事项: 无 ******************************************************************************************************************************************/ @@ -188,7 +191,7 @@ void ADC_Start(ADC_TypeDef *ADCx) /****************************************************************************************************************************************** * 函数名称: ADC_Stop() * 功能说明: 软件触发模式下停止ADC转换 -* 输 入: ADC_TypeDef * ADCx 指定要被设置的ADC，可取值包括ADC +* 输 入: ADC_TypeDef * ADCx 指定要被设置的ADC，可取值包括ADC * 输 出: 无 * 注意事项: 无 ******************************************************************************************************************************************/ @@ -235,9 +238,9 @@ static uint32_t chn2idx(uint32_t chn) /****************************************************************************************************************************************** * 函数名称: ADC_Read() * 功能说明: 从指定通道读取转换结果 -* 输 入: ADC_TypeDef * ADCx 指定要被设置的ADC，可取值包括ADC +* 输 入: ADC_TypeDef * ADCx 指定要被设置的ADC，可取值包括ADC * uint32_t chn 要读取转换结果的通道，有效值ADC_CH0、ADC_CH1、... ... 、ADC_CH7 -* 输 出: uint32_t 读取到的转换结果 +* 输 出: uint32_t 读取到的转换结果 * 注意事项: 无 ******************************************************************************************************************************************/ uint32_t ADC_Read(ADC_TypeDef *ADCx, uint32_t chn) @@ -255,9 +258,9 @@ uint32_t ADC_Read(ADC_TypeDef *ADCx, uint32_t chn) /****************************************************************************************************************************************** * 函数名称: ADC_IsEOC() * 功能说明: 指定通道是否End Of Conversion -* 输 入: ADC_TypeDef * ADCx 指定要被设置的ADC，可取值包括ADC +* 输 入: ADC_TypeDef * ADCx 指定要被设置的ADC，可取值包括ADC * uint32_t chn 要查询状态的通道，有效值ADC_CH0、ADC_CH1、... ... 、ADC_CH7 -* 输 出: uint32_t 1 该通道完成了转换 0 该通道未完成转换 +* 输 出: uint32_t 1 该通道完成了转换 0 该通道未完成转换 * 注意事项: 无 ******************************************************************************************************************************************/ uint32_t ADC_IsEOC(ADC_TypeDef *ADCx, uint32_t chn) @@ -270,7 +273,7 @@ uint32_t ADC_IsEOC(ADC_TypeDef *ADCx, uint32_t chn) /****************************************************************************************************************************************** * 函数名称: ADC_ChnSelect() * 功能说明: ADC通道选通，模数转换会在选通的通道上依次采样转换 -* 输 入: ADC_TypeDef * ADCx 指定要被设置的ADC，可取值包括ADC +* 输 入: ADC_TypeDef * ADCx 指定要被设置的ADC，可取值包括ADC * uint32_t chns 要选通的通道，有效值ADC_CH0、ADC_CH1、... ... 、ADC_CH7及其组合（即“按位或”运算） * 输 出: 无 * 注意事项: 无 @@ -284,7 +287,7 @@ void ADC_ChnSelect(ADC_TypeDef *ADCx, uint32_t chns) /****************************************************************************************************************************************** * 函数名称: ADC_IntEOCEn() * 功能说明: 转换完成中断使能 -* 输 入: ADC_TypeDef * ADCx 指定要被设置的ADC，可取值包括ADC +* 输 入: ADC_TypeDef * ADCx 指定要被设置的ADC，可取值包括ADC * uint32_t chn 要设置的通道，有效值ADC_CH0、ADC_CH1、... ... 、ADC_CH7 * 输 出: 无 * 注意事项: 无 @@ -299,7 +302,7 @@ void ADC_IntEOCEn(ADC_TypeDef *ADCx, uint32_t chn) /****************************************************************************************************************************************** * 函数名称: ADC_IntEOCDis() * 功能说明: 转换完成中断禁止 -* 输 入: ADC_TypeDef * ADCx 指定要被设置的ADC，可取值包括ADC +* 输 入: ADC_TypeDef * ADCx 指定要被设置的ADC，可取值包括ADC * uint32_t chn 要设置的通道，有效值ADC_CH0、ADC_CH1、... ... 、ADC_CH7 * 输 出: 无 * 注意事项: 无 @@ -314,7 +317,7 @@ void ADC_IntEOCDis(ADC_TypeDef *ADCx, uint32_t chn) /****************************************************************************************************************************************** * 函数名称: ADC_IntEOCClr() * 功能说明: 转换完成中断标志清除 -* 输 入: ADC_TypeDef * ADCx 指定要被设置的ADC，可取值包括ADC +* 输 入: ADC_TypeDef * ADCx 指定要被设置的ADC，可取值包括ADC * uint32_t chn 要设置的通道，有效值ADC_CH0、ADC_CH1、... ... 、ADC_CH7 * 输 出: 无 * 注意事项: 无 @@ -329,9 +332,9 @@ void ADC_IntEOCClr(ADC_TypeDef *ADCx, uint32_t chn) /****************************************************************************************************************************************** * 函数名称: ADC_IntEOCStat() * 功能说明: 转换完成中断状态 -* 输 入: ADC_TypeDef * ADCx 指定要被设置的ADC，可取值包括ADC +* 输 入: ADC_TypeDef * ADCx 指定要被设置的ADC，可取值包括ADC * uint32_t chn 要查询的通道，有效值ADC_CH0、ADC_CH1、... ... 、ADC_CH7 -* 输 出: uint32_t 1 该通道完成了转换 0 该通道未完成转换 +* 输 出: uint32_t 1 该通道完成了转换 0 该通道未完成转换 * 注意事项: 无 ******************************************************************************************************************************************/ uint32_t ADC_IntEOCStat(ADC_TypeDef *ADCx, uint32_t chn) @@ -344,7 +347,7 @@ uint32_t ADC_IntEOCStat(ADC_TypeDef *ADCx, uint32_t chn) /****************************************************************************************************************************************** * 函数名称: ADC_IntOVFEn() * 功能说明: 数据溢出中断使能 -* 输 入: ADC_TypeDef * ADCx 指定要被设置的ADC，可取值包括ADC +* 输 入: ADC_TypeDef * ADCx 指定要被设置的ADC，可取值包括ADC * uint32_t chn 要设置的通道，有效值ADC_CH0、ADC_CH1、... ... 、ADC_CH7 * 输 出: 无 * 注意事项: 无 @@ -359,7 +362,7 @@ void ADC_IntOVFEn(ADC_TypeDef *ADCx, uint32_t chn) /****************************************************************************************************************************************** * 函数名称: ADC_IntOVFDis() * 功能说明: 数据溢出中断禁止 -* 输 入: ADC_TypeDef * ADCx 指定要被设置的ADC，可取值包括ADC +* 输 入: ADC_TypeDef * ADCx 指定要被设置的ADC，可取值包括ADC * uint32_t chn 要设置的通道，有效值ADC_CH0、ADC_CH1、... ... 、ADC_CH7 * 输 出: 无 * 注意事项: 无 @@ -374,7 +377,7 @@ void ADC_IntOVFDis(ADC_TypeDef *ADCx, uint32_t chn) /****************************************************************************************************************************************** * 函数名称: ADC_IntOVFClr() * 功能说明: 数据溢出中断标志清除 -* 输 入: ADC_TypeDef * ADCx 指定要被设置的ADC，可取值包括ADC +* 输 入: ADC_TypeDef * ADCx 指定要被设置的ADC，可取值包括ADC * uint32_t chn 要设置的通道，有效值ADC_CH0、ADC_CH1、... ... 、ADC_CH7 * 输 出: 无 * 注意事项: 无 @@ -389,9 +392,9 @@ void ADC_IntOVFClr(ADC_TypeDef *ADCx, uint32_t chn) /****************************************************************************************************************************************** * 函数名称: ADC_IntOVFStat() * 功能说明: 数据溢出中断状态 -* 输 入: ADC_TypeDef * ADCx 指定要被设置的ADC，可取值包括ADC +* 输 入: ADC_TypeDef * ADCx 指定要被设置的ADC，可取值包括ADC * uint32_t chn 要查询的通道，有效值ADC_CH0、ADC_CH1、... ... 、ADC_CH7 -* 输 出: uint32_t 1 该通道完成了转换 0 该通道未完成转换 +* 输 出: uint32_t 1 该通道完成了转换 0 该通道未完成转换 * 注意事项: 无 ******************************************************************************************************************************************/ uint32_t ADC_IntOVFStat(ADC_TypeDef *ADCx, uint32_t chn) @@ -404,7 +407,7 @@ uint32_t ADC_IntOVFStat(ADC_TypeDef *ADCx, uint32_t chn) /****************************************************************************************************************************************** * 函数名称: ADC_IntHFULLEn() * 功能说明: FIFO半满中断使能 -* 输 入: ADC_TypeDef * ADCx 指定要被设置的ADC，可取值包括ADC +* 输 入: ADC_TypeDef * ADCx 指定要被设置的ADC，可取值包括ADC * uint32_t chn 要设置的通道，有效值ADC_CH0、ADC_CH1、... ... 、ADC_CH7 * 输 出: 无 * 注意事项: 无 @@ -419,7 +422,7 @@ void ADC_IntHFULLEn(ADC_TypeDef *ADCx, uint32_t chn) /****************************************************************************************************************************************** * 函数名称: ADC_IntHFULLDis() * 功能说明: FIFO半满中断禁止 -* 输 入: ADC_TypeDef * ADCx 指定要被设置的ADC，可取值包括ADC +* 输 入: ADC_TypeDef * ADCx 指定要被设置的ADC，可取值包括ADC * uint32_t chn 要设置的通道，有效值ADC_CH0、ADC_CH1、... ... 、ADC_CH7 * 输 出: 无 * 注意事项: 无 @@ -434,7 +437,7 @@ void ADC_IntHFULLDis(ADC_TypeDef *ADCx, uint32_t chn) /****************************************************************************************************************************************** * 函数名称: ADC_IntHFULLClr() * 功能说明: FIFO半满中断标志清除 -* 输 入: ADC_TypeDef * ADCx 指定要被设置的ADC，可取值包括ADC +* 输 入: ADC_TypeDef * ADCx 指定要被设置的ADC，可取值包括ADC * uint32_t chn 要设置的通道，有效值ADC_CH0、ADC_CH1、... ... 、ADC_CH7 * 输 出: 无 * 注意事项: 无 @@ -449,9 +452,9 @@ void ADC_IntHFULLClr(ADC_TypeDef *ADCx, uint32_t chn) /****************************************************************************************************************************************** * 函数名称: ADC_IntHFULLStat() * 功能说明: FIFO半满中断状态 -* 输 入: ADC_TypeDef * ADCx 指定要被设置的ADC，可取值包括ADC +* 输 入: ADC_TypeDef * ADCx 指定要被设置的ADC，可取值包括ADC * uint32_t chn 要查询的通道，有效值ADC_CH0、ADC_CH1、... ... 、ADC_CH7 -* 输 出: uint32_t 1 该通道完成了转换 0 该通道未完成转换 +* 输 出: uint32_t 1 该通道完成了转换 0 该通道未完成转换 * 注意事项: 无 ******************************************************************************************************************************************/ uint32_t ADC_IntHFULLStat(ADC_TypeDef *ADCx, uint32_t chn) @@ -464,7 +467,7 @@ uint32_t ADC_IntHFULLStat(ADC_TypeDef *ADCx, uint32_t chn) /****************************************************************************************************************************************** * 函数名称: ADC_IntFULLEn() * 功能说明: FIFO满中断使能 -* 输 入: ADC_TypeDef * ADCx 指定要被设置的ADC，可取值包括ADC +* 输 入: ADC_TypeDef * ADCx 指定要被设置的ADC，可取值包括ADC * uint32_t chn 要设置的通道，有效值ADC_CH0、ADC_CH1、... ... 、ADC_CH7 * 输 出: 无 * 注意事项: 无 @@ -479,7 +482,7 @@ void ADC_IntFULLEn(ADC_TypeDef *ADCx, uint32_t chn) /****************************************************************************************************************************************** * 函数名称: ADC_IntFULLDis() * 功能说明: FIFO满中断禁止 -* 输 入: ADC_TypeDef * ADCx 指定要被设置的ADC，可取值包括ADC +* 输 入: ADC_TypeDef * ADCx 指定要被设置的ADC，可取值包括ADC * uint32_t chn 要设置的通道，有效值ADC_CH0、ADC_CH1、... ... 、ADC_CH7 * 输 出: 无 * 注意事项: 无 @@ -494,7 +497,7 @@ void ADC_IntFULLDis(ADC_TypeDef *ADCx, uint32_t chn) /****************************************************************************************************************************************** * 函数名称: ADC_IntFULLClr() * 功能说明: FIFO满中断标志清除 -* 输 入: ADC_TypeDef * ADCx 指定要被设置的ADC，可取值包括ADC +* 输 入: ADC_TypeDef * ADCx 指定要被设置的ADC，可取值包括ADC * uint32_t chn 要设置的通道，有效值ADC_CH0、ADC_CH1、... ... 、ADC_CH7 * 输 出: 无 * 注意事项: 无 @@ -509,9 +512,9 @@ void ADC_IntFULLClr(ADC_TypeDef *ADCx, uint32_t chn) /****************************************************************************************************************************************** * 函数名称: ADC_IntFULLStat() * 功能说明: FIFO满中断状态 -* 输 入: ADC_TypeDef * ADCx 指定要被设置的ADC，可取值包括ADC +* 输 入: ADC_TypeDef * ADCx 指定要被设置的ADC，可取值包括ADC * uint32_t chn 要查询的通道，有效值ADC_CH0、ADC_CH1、... ... 、ADC_CH7 -* 输 出: uint32_t 1 该通道完成了转换 0 该通道未完成转换 +* 输 出: uint32_t 1 该通道完成了转换 0 该通道未完成转换 * 注意事项: 无 ******************************************************************************************************************************************/ uint32_t ADC_IntFULLStat(ADC_TypeDef *ADCx, uint32_t chn) diff --git a/bsp/swm320-lq100/Libraries/SWM320_StdPeriph_Driver/SWM320_adc.h b/bsp/swm320-lq100/Libraries/SWM320_StdPeriph_Driver/SWM320_adc.h index b5906af908..10b4437527 100644 --- a/bsp/swm320-lq100/Libraries/SWM320_StdPeriph_Driver/SWM320_adc.h +++ b/bsp/swm320-lq100/Libraries/SWM320_StdPeriph_Driver/SWM320_adc.h @@ -3,13 +3,14 @@ typedef struct { - uint8_t clk_src; //ADC转换时钟源：ADC_CLKSRC_HRC、ADC_CLKSRC_VCO_DIV16、ADC_CLKSRC_VCO_DIV32、ADC_CLKSRC_VCO_DIV32 - uint8_t clk_div; //ADC转换时钟分频，取值1--31 - uint8_t channels; //ADC转换通道选中，ADC_CH0、ADC_CH1、... ... 、ADC_CH7及其组合（即“按位或”运算） - uint8_t samplAvg; //采样取平均，触发启动ADC转换后，ADC在一个通道上连续采样、转换多次，并将它们的平均值作为该通道转换结果 - uint8_t trig_src; //ADC触发方式：ADC_TRIGSRC_SW、ADC_TRIGSRC_PWM、ADC_TRIGSRC_TIMR2、ADC_TRIGSRC_TIMR3 - uint8_t Continue; //在软件触发模式下：1 连续转换模式，启动后一直采样、转换，直到软件清除START位 - // 0 单次转换模式，转换完成后START位自动清除停止转换 + uint8_t clk_src; //ADC转换时钟源：ADC_CLKSRC_HRC、ADC_CLKSRC_VCO_DIV16、ADC_CLKSRC_VCO_DIV32、ADC_CLKSRC_VCO_DIV32 + uint8_t clk_div; //ADC转换时钟分频，取值1--31 + uint8_t pga_ref; //PGA基准：PGA_REF_INTERNAL、PGA_REF_EXTERNAL + uint8_t channels; //ADC转换通道选中，ADC_CH0、ADC_CH1、... ... 、ADC_CH7及其组合（即“按位或”运算） + uint8_t samplAvg; //采样取平均，触发启动ADC转换后，ADC在一个通道上连续采样、转换多次，并将它们的平均值作为该通道转换结果 + uint8_t trig_src; //ADC触发方式：ADC_TRIGSRC_SW、ADC_TRIGSRC_PWM、ADC_TRIGSRC_TIMR2、ADC_TRIGSRC_TIMR3 + uint8_t Continue; //在软件触发模式下：1 连续转换模式，启动后一直采样、转换，直到软件清除START位 + // 0 单次转换模式，转换完成后START位自动清除停止转换 uint8_t EOC_IEn; //EOC中断使能，可针对每个通道设置，其有效值为ADC_CH0、ADC_CH1、... ... 、ADC_CH7及其组合（即“按位或”运算） uint8_t OVF_IEn; //OVF中断使能，可针对每个通道设置，其有效值为ADC_CH0、ADC_CH1、... ... 、ADC_CH7及其组合（即“按位或”运算） uint8_t HFULL_IEn; //FIFO半满中断使能，可针对每个通道设置，其有效值为ADC_CH0、ADC_CH1、... ... 、ADC_CH7及其组合（即“按位或”运算） @@ -39,8 +40,8 @@ typedef struct #define ADC_TRIGSRC_SW 0 //软件触发，即ADC->START.GO写1启动转换 #define ADC_TRIGSRC_PWM 1 -#define PGA_VCM_INTERNAL 1 //PGA输入共模电平由内部电路产生，ADC_REFP和ADC_REFN可悬空 -#define PGA_VCM_EXTERNAL 0 //PGA输入共模电平由外部引脚提供，(ADC_REFP + ADC_REFN) 电平值须与量程相同 +#define PGA_REF_INTERNAL 1 //PGA输入共模电平由内部电路产生，ADC_REFP和ADC_REFN可悬空 +#define PGA_REF_EXTERNAL 0 //PGA输入共模电平由外部引脚提供，(ADC_REFP + ADC_REFN) 电平值须与量程相同 void ADC_Init(ADC_TypeDef *ADCx, ADC_InitStructure *initStruct); //ADC模数转换器初始化 void ADC_Open(ADC_TypeDef *ADCx); //ADC开启，可以软件启动、或硬件触发ADC转换 @@ -73,11 +74,4 @@ void ADC_IntFULLDis(ADC_TypeDef *ADCx, uint32_t chn); //FIFO满中断禁止 void ADC_IntFULLClr(ADC_TypeDef *ADCx, uint32_t chn); //FIFO满中断标志清除 uint32_t ADC_IntFULLStat(ADC_TypeDef *ADCx, uint32_t chn); //FIFO满中断状态 -/* ADC 内部 1.2V REFP电压输出到外部REFP引脚，用于测量，或在需要1.2V外部REFP时节省成本 */ -#define ADC_TEST_INNER_REFP_OUT_EN(ADCx) (ADCx->CTRL3 |= (1 << ADC_CTRL3_REFP_OUT_Pos)) -#define ADC_TEST_INNER_REFP_OUT_DIS(ADCx) (ADCx->CTRL3 &= ~(1 << ADC_CTRL3_REFP_OUT_Pos)) - -#define ADC_TEST_ADC_PGA_EXT_VCM_EN(ADCx) (ADCx->CTRL3 |= (1 << ADC_CTRL3_EXTVCM_Pos)) -#define ADC_TEST_ADC_PGA_EXT_VCM_DIS(ADCx) (ADCx->CTRL3 &= ~(1 << ADC_CTRL3_EXTVCM_Pos)) - #endif //__SWM320_ADC_H__ diff --git a/bsp/swm320-lq100/Libraries/SWM320_StdPeriph_Driver/SWM320_can.c b/bsp/swm320-lq100/Libraries/SWM320_StdPeriph_Driver/SWM320_can.c index 2f9a345b21..85d1a81d07 100644 --- a/bsp/swm320-lq100/Libraries/SWM320_StdPeriph_Driver/SWM320_can.c +++ b/bsp/swm320-lq100/Libraries/SWM320_StdPeriph_Driver/SWM320_can.c @@ -24,7 +24,7 @@ /****************************************************************************************************************************************** * 函数名称: CAN_Init() * 功能说明: CAN接口初始化 -* 输 入: CAN_TypeDef * CANx 指定要被设置的CAN接口，有效值包括CAN +* 输 入: CAN_TypeDef * CANx 指定要被设置的CAN接口，有效值包括CAN * CAN_InitStructure * initStruct 包含CAN接口相关设定值的结构体 * 输 出: 无 * 注意事项: 无 @@ -87,7 +87,7 @@ void CAN_Init(CAN_TypeDef *CANx, CAN_InitStructure *initStruct) /****************************************************************************************************************************************** * 函数名称: CAN_Open() * 功能说明: CAN接口打开 -* 输 入: CAN_TypeDef * CANx 指定要被设置的CAN接口，有效值包括CAN +* 输 入: CAN_TypeDef * CANx 指定要被设置的CAN接口，有效值包括CAN * 输 出: 无 * 注意事项: 无 ******************************************************************************************************************************************/ @@ -99,7 +99,7 @@ void CAN_Open(CAN_TypeDef *CANx) /****************************************************************************************************************************************** * 函数名称: CAN_Close() * 功能说明: CAN接口关闭 -* 输 入: CAN_TypeDef * CANx 指定要被设置的CAN接口，有效值包括CAN +* 输 入: CAN_TypeDef * CANx 指定要被设置的CAN接口，有效值包括CAN * 输 出: 无 * 注意事项: 无 ******************************************************************************************************************************************/ @@ -111,7 +111,7 @@ void CAN_Close(CAN_TypeDef *CANx) /****************************************************************************************************************************************** * 函数名称: CAN_Transmit() * 功能说明: CAN发送数据 -* 输 入: CAN_TypeDef * CANx 指定要被设置的CAN接口，有效值包括CAN +* 输 入: CAN_TypeDef * CANx 指定要被设置的CAN接口，有效值包括CAN * uint32_t format CAN_FRAME_STD 标准帧 CAN_FRAME_EXT 扩展帧 * uint32_t id 消息ID * uint8_t data[] 要发送的数据 @@ -126,32 +126,32 @@ void CAN_Transmit(CAN_TypeDef *CANx, uint32_t format, uint32_t id, uint8_t data[ if (format == CAN_FRAME_STD) { - CANx->TXFRAME.INFO = (0 << CAN_INFO_FF_Pos) | - (0 << CAN_INFO_RTR_Pos) | - (size << CAN_INFO_DLC_Pos); + CANx->FRAME.INFO = (0 << CAN_INFO_FF_Pos) | + (0 << CAN_INFO_RTR_Pos) | + (size << CAN_INFO_DLC_Pos); - CANx->TXFRAME.DATA[0] = id >> 3; - CANx->TXFRAME.DATA[1] = id << 5; + CANx->FRAME.DATA[0] = id >> 3; + CANx->FRAME.DATA[1] = id << 5; for (i = 0; i < size; i++) { - CANx->TXFRAME.DATA[i + 2] = data[i]; + CANx->FRAME.DATA[i + 2] = data[i]; } } else //if(format == CAN_FRAME_EXT) { - CANx->TXFRAME.INFO = (1 << CAN_INFO_FF_Pos) | - (0 << CAN_INFO_RTR_Pos) | - (size << CAN_INFO_DLC_Pos); + CANx->FRAME.INFO = (1 << CAN_INFO_FF_Pos) | + (0 << CAN_INFO_RTR_Pos) | + (size << CAN_INFO_DLC_Pos); - CANx->TXFRAME.DATA[0] = id >> 21; - CANx->TXFRAME.DATA[1] = id >> 13; - CANx->TXFRAME.DATA[2] = id >> 5; - CANx->TXFRAME.DATA[3] = id << 3; + CANx->FRAME.DATA[0] = id >> 21; + CANx->FRAME.DATA[1] = id >> 13; + CANx->FRAME.DATA[2] = id >> 5; + CANx->FRAME.DATA[3] = id << 3; for (i = 0; i < size; i++) { - CANx->TXFRAME.DATA[i + 4] = data[i]; + CANx->FRAME.DATA[i + 4] = data[i]; } } @@ -175,7 +175,7 @@ void CAN_Transmit(CAN_TypeDef *CANx, uint32_t format, uint32_t id, uint8_t data[ /****************************************************************************************************************************************** * 函数名称: CAN_TransmitRequest() * 功能说明: CAN发送远程请求，请求远程节点发送数据 -* 输 入: CAN_TypeDef * CANx 指定要被设置的CAN接口，有效值包括CAN +* 输 入: CAN_TypeDef * CANx 指定要被设置的CAN接口，有效值包括CAN * uint32_t format CAN_FRAME_STD 标准帧 CAN_FRAME_EXT 扩展帧 * uint32_t id 消息ID * uint32_t once 只发送一次，即使发送失败（仲裁丢失、发送出错、NAK）也不尝试重发 @@ -186,23 +186,23 @@ void CAN_TransmitRequest(CAN_TypeDef *CANx, uint32_t format, uint32_t id, uint32 { if (format == CAN_FRAME_STD) { - CANx->TXFRAME.INFO = (0 << CAN_INFO_FF_Pos) | - (1 << CAN_INFO_RTR_Pos) | - (0 << CAN_INFO_DLC_Pos); + CANx->FRAME.INFO = (0 << CAN_INFO_FF_Pos) | + (1 << CAN_INFO_RTR_Pos) | + (0 << CAN_INFO_DLC_Pos); - CANx->TXFRAME.DATA[0] = id >> 3; - CANx->TXFRAME.DATA[1] = id << 5; + CANx->FRAME.DATA[0] = id >> 3; + CANx->FRAME.DATA[1] = id << 5; } else //if(format == CAN_FRAME_EXT) { - CANx->TXFRAME.INFO = (1 << CAN_INFO_FF_Pos) | - (1 << CAN_INFO_RTR_Pos) | - (0 << CAN_INFO_DLC_Pos); + CANx->FRAME.INFO = (1 << CAN_INFO_FF_Pos) | + (1 << CAN_INFO_RTR_Pos) | + (0 << CAN_INFO_DLC_Pos); - CANx->TXFRAME.DATA[0] = id >> 21; - CANx->TXFRAME.DATA[1] = id >> 13; - CANx->TXFRAME.DATA[2] = id >> 5; - CANx->TXFRAME.DATA[3] = id << 3; + CANx->FRAME.DATA[0] = id >> 21; + CANx->FRAME.DATA[1] = id >> 13; + CANx->FRAME.DATA[2] = id >> 5; + CANx->FRAME.DATA[3] = id << 3; } if (once == 0) @@ -218,7 +218,7 @@ void CAN_TransmitRequest(CAN_TypeDef *CANx, uint32_t format, uint32_t id, uint32 /****************************************************************************************************************************************** * 函数名称: CAN_Receive() * 功能说明: CAN接收数据 -* 输 入: CAN_TypeDef * CANx 指定要被设置的CAN接口，有效值包括CAN +* 输 入: CAN_TypeDef * CANx 指定要被设置的CAN接口，有效值包括CAN * CAN_RXMessage *msg 接收到的消息存储在此结构体变量中 * 输 出: 无 * 注意事项: 无 @@ -226,27 +226,27 @@ void CAN_TransmitRequest(CAN_TypeDef *CANx, uint32_t format, uint32_t id, uint32 void CAN_Receive(CAN_TypeDef *CANx, CAN_RXMessage *msg) { uint32_t i; - uint32_t format = (CANx->RXFRAME.INFO & CAN_INFO_FF_Msk) >> CAN_INFO_FF_Pos; + msg->format = (CANx->FRAME.INFO & CAN_INFO_FF_Msk) >> CAN_INFO_FF_Pos; - msg->remote = (CANx->RXFRAME.INFO & CAN_INFO_RTR_Msk) >> CAN_INFO_RTR_Pos; - msg->size = (CANx->RXFRAME.INFO & CAN_INFO_DLC_Msk) >> CAN_INFO_DLC_Pos; + msg->remote = (CANx->FRAME.INFO & CAN_INFO_RTR_Msk) >> CAN_INFO_RTR_Pos; + msg->size = (CANx->FRAME.INFO & CAN_INFO_DLC_Msk) >> CAN_INFO_DLC_Pos; - if (format == CAN_FRAME_STD) + if (msg->format == CAN_FRAME_STD) { - msg->id = (CANx->RXFRAME.DATA[0] << 3) | (CANx->RXFRAME.DATA[1] >> 5); + msg->id = (CANx->FRAME.DATA[0] << 3) | (CANx->FRAME.DATA[1] >> 5); for (i = 0; i < msg->size; i++) { - msg->data[i] = CANx->RXFRAME.DATA[i + 2]; + msg->data[i] = CANx->FRAME.DATA[i + 2]; } } - else //if(format == CAN_FRAME_EXT) + else //if(msg->format == CAN_FRAME_EXT) { - msg->id = (CANx->RXFRAME.DATA[0] << 21) | (CANx->RXFRAME.DATA[1] << 13) | (CANx->RXFRAME.DATA[2] << 5) | (CANx->RXFRAME.DATA[3] >> 3); + msg->id = (CANx->FRAME.DATA[0] << 21) | (CANx->FRAME.DATA[1] << 13) | (CANx->FRAME.DATA[2] << 5) | (CANx->FRAME.DATA[3] >> 3); for (i = 0; i < msg->size; i++) { - msg->data[i] = CANx->RXFRAME.DATA[i + 4]; + msg->data[i] = CANx->FRAME.DATA[i + 4]; } } @@ -256,8 +256,8 @@ void CAN_Receive(CAN_TypeDef *CANx, CAN_RXMessage *msg) /****************************************************************************************************************************************** * 函数名称: CAN_TXComplete() * 功能说明: 发送是否完成 -* 输 入: CAN_TypeDef * CANx 指定要被设置的CAN接口，有效值包括CAN -* 输 出: uint32_t 1 已经完成 0 还未完成 +* 输 入: CAN_TypeDef * CANx 指定要被设置的CAN接口，有效值包括CAN +* 输 出: uint32_t 1 已经完成 0 还未完成 * 注意事项: 发送被Abort也会触发发送完成，但不会触发发送成功 ******************************************************************************************************************************************/ uint32_t CAN_TXComplete(CAN_TypeDef *CANx) @@ -268,8 +268,8 @@ uint32_t CAN_TXComplete(CAN_TypeDef *CANx) /****************************************************************************************************************************************** * 函数名称: CAN_TXSuccess() * 功能说明: 发送是否成功 -* 输 入: CAN_TypeDef * CANx 指定要被设置的CAN接口，有效值包括CAN -* 输 出: uint32_t 1 发送成功 0 发送失败 +* 输 入: CAN_TypeDef * CANx 指定要被设置的CAN接口，有效值包括CAN +* 输 出: uint32_t 1 发送成功 0 发送失败 * 注意事项: 无 ******************************************************************************************************************************************/ uint32_t CAN_TXSuccess(CAN_TypeDef *CANx) @@ -280,7 +280,7 @@ uint32_t CAN_TXSuccess(CAN_TypeDef *CANx) /****************************************************************************************************************************************** * 函数名称: CAN_AbortTransmit() * 功能说明: 终止发送 -* 输 入: CAN_TypeDef * CANx 指定要被设置的CAN接口，有效值包括CAN +* 输 入: CAN_TypeDef * CANx 指定要被设置的CAN接口，有效值包括CAN * 输 出: 无 * 注意事项: 正在进行的发送无法终止，但执行此命令后若发送失败不会再重发 ******************************************************************************************************************************************/ @@ -292,8 +292,8 @@ void CAN_AbortTransmit(CAN_TypeDef *CANx) /****************************************************************************************************************************************** * 函数名称: CAN_TXBufferReady() * 功能说明: TX Buffer是否准备好可以写入消息 -* 输 入: CAN_TypeDef * CANx 指定要被设置的CAN接口，有效值包括CAN -* 输 出: uint32_t 1 已准备好 0 未准备好 +* 输 入: CAN_TypeDef * CANx 指定要被设置的CAN接口，有效值包括CAN +* 输 出: uint32_t 1 已准备好 0 未准备好 * 注意事项: 无 ******************************************************************************************************************************************/ uint32_t CAN_TXBufferReady(CAN_TypeDef *CANx) @@ -304,8 +304,8 @@ uint32_t CAN_TXBufferReady(CAN_TypeDef *CANx) /****************************************************************************************************************************************** * 函数名称: CAN_RXDataAvailable() * 功能说明: RX FIFO中是否有数据可读出 -* 输 入: CAN_TypeDef * CANx 指定要被设置的CAN接口，有效值包括CAN -* 输 出: uint32_t 1 有数据可读出 0 没有数据 +* 输 入: CAN_TypeDef * CANx 指定要被设置的CAN接口，有效值包括CAN +* 输 出: uint32_t 1 有数据可读出 0 没有数据 * 注意事项: 无 ******************************************************************************************************************************************/ uint32_t CAN_RXDataAvailable(CAN_TypeDef *CANx) @@ -316,7 +316,7 @@ uint32_t CAN_RXDataAvailable(CAN_TypeDef *CANx) /****************************************************************************************************************************************** * 函数名称: CAN_SetBaudrate() * 功能说明: 设置波特率 -* 输 入: CAN_TypeDef * CANx 指定要被设置的CAN接口，有效值包括CAN +* 输 入: CAN_TypeDef * CANx 指定要被设置的CAN接口，有效值包括CAN * uint32_t baudrate 波特率，即位传输速率 * uint32_t CAN_BS1 CAN_BS1_1tq、CAN_BS1_2tq、... ... 、CAN_BS1_16tq * uint32_t CAN_BS2 CAN_BS2_1tq、CAN_BS2_2tq、... ... 、CAN_BS2_8tq @@ -337,7 +337,7 @@ void CAN_SetBaudrate(CAN_TypeDef *CANx, uint32_t baudrate, uint32_t CAN_BS1, uin /****************************************************************************************************************************************** * 函数名称: CAN_SetFilter32b() * 功能说明: 设置接收滤波器，1个32位滤波器 -* 输 入: CAN_TypeDef * CANx 指定要被设置的CAN接口，有效值包括CAN +* 输 入: CAN_TypeDef * CANx 指定要被设置的CAN接口，有效值包括CAN * uint32_t check 与mask一起决定了接收到的Message是否是自己需要的：check & (~mask) == ID & (~mask)的Message通过过滤 * uint32_t mask * 输 出: 无 @@ -348,21 +348,21 @@ void CAN_SetFilter32b(CAN_TypeDef *CANx, uint32_t check, uint32_t mask) CANx->CR &= ~CAN_CR_AFM_Msk; CANx->CR |= (CAN_FILTER_32b << CAN_CR_AFM_Pos); - CANx->FILTER.AMR[0] = mask & 0xFF; - CANx->FILTER.AMR[1] = (mask >> 8) & 0xFF; - CANx->FILTER.AMR[2] = (mask >> 16) & 0xFF; - CANx->FILTER.AMR[3] = (mask >> 24) & 0xFF; + CANx->FILTER.AMR[3] = mask & 0xFF; + CANx->FILTER.AMR[2] = (mask >> 8) & 0xFF; + CANx->FILTER.AMR[1] = (mask >> 16) & 0xFF; + CANx->FILTER.AMR[0] = (mask >> 24) & 0xFF; - CANx->FILTER.ACR[0] = check & 0xFF; - CANx->FILTER.ACR[1] = (check >> 8) & 0xFF; - CANx->FILTER.ACR[2] = (check >> 16) & 0xFF; - CANx->FILTER.ACR[3] = (check >> 24) & 0xFF; + CANx->FILTER.ACR[3] = check & 0xFF; + CANx->FILTER.ACR[2] = (check >> 8) & 0xFF; + CANx->FILTER.ACR[1] = (check >> 16) & 0xFF; + CANx->FILTER.ACR[0] = (check >> 24) & 0xFF; } /****************************************************************************************************************************************** * 函数名称: CAN_SetFilter16b() * 功能说明: 设置接收滤波器，2个16位滤波器 -* 输 入: CAN_TypeDef * CANx 指定要被设置的CAN接口，有效值包括CAN +* 输 入: CAN_TypeDef * CANx 指定要被设置的CAN接口，有效值包括CAN * uint16_t check1 与mask一起决定了接收到的Message是否是自己需要的：check & (~mask) == ID & (~mask)的Message通过过滤 * uint16_t mask1 * uint16_t check2 @@ -375,21 +375,21 @@ void CAN_SetFilter16b(CAN_TypeDef *CANx, uint16_t check1, uint16_t mask1, uint16 CANx->CR &= ~CAN_CR_AFM_Msk; CANx->CR |= (CAN_FILTER_16b << CAN_CR_AFM_Pos); - CANx->FILTER.AMR[0] = mask1 & 0xFF; - CANx->FILTER.AMR[1] = (mask1 >> 8) & 0xFF; - CANx->FILTER.AMR[2] = mask2 & 0xFF; - CANx->FILTER.AMR[3] = (mask2 >> 8) & 0xFF; + CANx->FILTER.AMR[3] = mask1 & 0xFF; + CANx->FILTER.AMR[2] = (mask1 >> 8) & 0xFF; + CANx->FILTER.AMR[1] = mask2 & 0xFF; + CANx->FILTER.AMR[0] = (mask2 >> 8) & 0xFF; - CANx->FILTER.ACR[0] = check1 & 0xFF; - CANx->FILTER.ACR[1] = (check1 >> 8) & 0xFF; - CANx->FILTER.ACR[2] = check2 & 0xFF; - CANx->FILTER.ACR[3] = (check2 >> 8) & 0xFF; + CANx->FILTER.ACR[3] = check1 & 0xFF; + CANx->FILTER.ACR[2] = (check1 >> 8) & 0xFF; + CANx->FILTER.ACR[1] = check2 & 0xFF; + CANx->FILTER.ACR[0] = (check2 >> 8) & 0xFF; } /****************************************************************************************************************************************** * 函数名称: CAN_INTRXNotEmptyEn() * 功能说明: 当RX FIFO中有数据时（非空）触发中断使能 -* 输 入: CAN_TypeDef * CANx 指定要被设置的CAN接口，有效值包括CAN +* 输 入: CAN_TypeDef * CANx 指定要被设置的CAN接口，有效值包括CAN * 输 出: 无 * 注意事项: 无 ******************************************************************************************************************************************/ @@ -401,7 +401,7 @@ void CAN_INTRXNotEmptyEn(CAN_TypeDef *CANx) /****************************************************************************************************************************************** * 函数名称: CAN_INTRXNotEmptyDis() * 功能说明: 当RX FIFO中有数据时（非空）触发中断禁止 -* 输 入: CAN_TypeDef * CANx 指定要被设置的CAN接口，有效值包括CAN +* 输 入: CAN_TypeDef * CANx 指定要被设置的CAN接口，有效值包括CAN * 输 出: 无 * 注意事项: 无 ******************************************************************************************************************************************/ @@ -411,21 +411,9 @@ void CAN_INTRXNotEmptyDis(CAN_TypeDef *CANx) } /****************************************************************************************************************************************** -* 函数名称: CAN_INTRXNotEmptyStat() -* 功能说明: RX FIFO非空中断是否触发 -* 输 入: CAN_TypeDef * CANx 指定要被设置的CAN接口，有效值包括CAN -* 输 出: uint32_t 1 已触发 0 未触发 -* 注意事项: 无 -******************************************************************************************************************************************/ -uint32_t CAN_INTRXNotEmptyStat(CAN_TypeDef *CANx) -{ - return (CANx->IF & CAN_IF_RXDA_Msk) ? 1 : 0; -} - -/****************************************************************************************************************************************** * 函数名称: CAN_INTTXBufEmptyEn() * 功能说明: 当TX Buffer空时触发中断使能 -* 输 入: CAN_TypeDef * CANx 指定要被设置的CAN接口，有效值包括CAN +* 输 入: CAN_TypeDef * CANx 指定要被设置的CAN接口，有效值包括CAN * 输 出: 无 * 注意事项: 无 ******************************************************************************************************************************************/ @@ -437,7 +425,7 @@ void CAN_INTTXBufEmptyEn(CAN_TypeDef *CANx) /****************************************************************************************************************************************** * 函数名称: CAN_INTTXBufEmptyDis() * 功能说明: 当TX Buffer空时触发中断禁止 -* 输 入: CAN_TypeDef * CANx 指定要被设置的CAN接口，有效值包括CAN +* 输 入: CAN_TypeDef * CANx 指定要被设置的CAN接口，有效值包括CAN * 输 出: 无 * 注意事项: 无 ******************************************************************************************************************************************/ @@ -447,21 +435,9 @@ void CAN_INTTXBufEmptyDis(CAN_TypeDef *CANx) } /****************************************************************************************************************************************** -* 函数名称: CAN_INTTXBufEmptyStat() -* 功能说明: TX Buffer空中断是否触发 -* 输 入: CAN_TypeDef * CANx 指定要被设置的CAN接口，有效值包括CAN -* 输 出: uint32_t 1 已触发 0 未触发 -* 注意事项: 无 -******************************************************************************************************************************************/ -uint32_t CAN_INTTXBufEmptyStat(CAN_TypeDef *CANx) -{ - return (CANx->IF & CAN_IF_TXBR_Msk) ? 1 : 0; -} - -/****************************************************************************************************************************************** * 函数名称: CAN_INTErrWarningEn() * 功能说明: TXERR/RXERR计数值达到Error Warning Limit时触发中断使能 -* 输 入: CAN_TypeDef * CANx 指定要被设置的CAN接口，有效值包括CAN +* 输 入: CAN_TypeDef * CANx 指定要被设置的CAN接口，有效值包括CAN * 输 出: 无 * 注意事项: 无 ******************************************************************************************************************************************/ @@ -473,7 +449,7 @@ void CAN_INTErrWarningEn(CAN_TypeDef *CANx) /****************************************************************************************************************************************** * 函数名称: CAN_INTErrWarningDis() * 功能说明: TXERR/RXERR计数值达到Error Warning Limit时触发中断禁止 -* 输 入: CAN_TypeDef * CANx 指定要被设置的CAN接口，有效值包括CAN +* 输 入: CAN_TypeDef * CANx 指定要被设置的CAN接口，有效值包括CAN * 输 出: 无 * 注意事项: 无 ******************************************************************************************************************************************/ @@ -483,21 +459,9 @@ void CAN_INTErrWarningDis(CAN_TypeDef *CANx) } /****************************************************************************************************************************************** -* 函数名称: CAN_INTErrWarningStat() -* 功能说明: TXERR/RXERR计数值达到Error Warning Limit中断是否触发 -* 输 入: CAN_TypeDef * CANx 指定要被设置的CAN接口，有效值包括CAN -* 输 出: uint32_t 1 已触发 0 未触发 -* 注意事项: 无 -******************************************************************************************************************************************/ -uint32_t CAN_INTErrWarningStat(CAN_TypeDef *CANx) -{ - return (CANx->IF & CAN_IF_ERRWARN_Msk) ? 1 : 0; -} - -/****************************************************************************************************************************************** * 函数名称: CAN_INTRXOverflowEn() * 功能说明: RX FIFO 溢出时触发中断使能 -* 输 入: CAN_TypeDef * CANx 指定要被设置的CAN接口，有效值包括CAN +* 输 入: CAN_TypeDef * CANx 指定要被设置的CAN接口，有效值包括CAN * 输 出: 无 * 注意事项: 无 ******************************************************************************************************************************************/ @@ -509,7 +473,7 @@ void CAN_INTRXOverflowEn(CAN_TypeDef *CANx) /****************************************************************************************************************************************** * 函数名称: CAN_INTRXOverflowDis() * 功能说明: RX FIFO 溢出时触发中断禁止 -* 输 入: CAN_TypeDef * CANx 指定要被设置的CAN接口，有效值包括CAN +* 输 入: CAN_TypeDef * CANx 指定要被设置的CAN接口，有效值包括CAN * 输 出: 无 * 注意事项: 无 ******************************************************************************************************************************************/ @@ -519,21 +483,9 @@ void CAN_INTRXOverflowDis(CAN_TypeDef *CANx) } /****************************************************************************************************************************************** -* 函数名称: CAN_INTRXOverflowStat() -* 功能说明: RX FIFO 溢出中断是否触发 -* 输 入: CAN_TypeDef * CANx 指定要被设置的CAN接口，有效值包括CAN -* 输 出: uint32_t 1 已触发 0 未触发 -* 注意事项: 无 -******************************************************************************************************************************************/ -uint32_t CAN_INTRXOverflowStat(CAN_TypeDef *CANx) -{ - return (CANx->IF & CAN_IF_RXOV_Msk) ? 1 : 0; -} - -/****************************************************************************************************************************************** * 函数名称: CAN_INTRXOverflowClear() * 功能说明: RX FIFO 溢出中断清除 -* 输 入: CAN_TypeDef * CANx 指定要被设置的CAN接口，有效值包括CAN +* 输 入: CAN_TypeDef * CANx 指定要被设置的CAN接口，有效值包括CAN * 输 出: 无 * 注意事项: 无 ******************************************************************************************************************************************/ @@ -545,7 +497,7 @@ void CAN_INTRXOverflowClear(CAN_TypeDef *CANx) /****************************************************************************************************************************************** * 函数名称: CAN_INTWakeupEn() * 功能说明: 唤醒事件触发中断使能 -* 输 入: CAN_TypeDef * CANx 指定要被设置的CAN接口，有效值包括CAN +* 输 入: CAN_TypeDef * CANx 指定要被设置的CAN接口，有效值包括CAN * 输 出: 无 * 注意事项: 无 ******************************************************************************************************************************************/ @@ -557,7 +509,7 @@ void CAN_INTWakeupEn(CAN_TypeDef *CANx) /****************************************************************************************************************************************** * 函数名称: CAN_INTWakeupDis() * 功能说明: 唤醒事件触发中断禁止 -* 输 入: CAN_TypeDef * CANx 指定要被设置的CAN接口，有效值包括CAN +* 输 入: CAN_TypeDef * CANx 指定要被设置的CAN接口，有效值包括CAN * 输 出: 无 * 注意事项: 无 ******************************************************************************************************************************************/ @@ -567,21 +519,9 @@ void CAN_INTWakeupDis(CAN_TypeDef *CANx) } /****************************************************************************************************************************************** -* 函数名称: CAN_INTWakeupStat() -* 功能说明: 唤醒事件中断是否触发 -* 输 入: CAN_TypeDef * CANx 指定要被设置的CAN接口，有效值包括CAN -* 输 出: uint32_t 1 已触发 0 未触发 -* 注意事项: 无 -******************************************************************************************************************************************/ -uint32_t CAN_INTWakeupStat(CAN_TypeDef *CANx) -{ - return (CANx->IF & CAN_IF_WKUP_Msk) ? 1 : 0; -} - -/****************************************************************************************************************************************** * 函数名称: CAN_INTErrPassiveEn() * 功能说明: TXERR/RXERR计数值达到127时中断使能 -* 输 入: CAN_TypeDef * CANx 指定要被设置的CAN接口，有效值包括CAN +* 输 入: CAN_TypeDef * CANx 指定要被设置的CAN接口，有效值包括CAN * 输 出: 无 * 注意事项: 无 ******************************************************************************************************************************************/ @@ -593,7 +533,7 @@ void CAN_INTErrPassiveEn(CAN_TypeDef *CANx) /****************************************************************************************************************************************** * 函数名称: CAN_INTErrPassiveDis() * 功能说明: TXERR/RXERR计数值达到127时中断禁止 -* 输 入: CAN_TypeDef * CANx 指定要被设置的CAN接口，有效值包括CAN +* 输 入: CAN_TypeDef * CANx 指定要被设置的CAN接口，有效值包括CAN * 输 出: 无 * 注意事项: 无 ******************************************************************************************************************************************/ @@ -603,21 +543,9 @@ void CAN_INTErrPassiveDis(CAN_TypeDef *CANx) } /****************************************************************************************************************************************** -* 函数名称: CAN_INTErrPassiveStat() -* 功能说明: TXERR/RXERR计数值达到127中断是否触发 -* 输 入: CAN_TypeDef * CANx 指定要被设置的CAN接口，有效值包括CAN -* 输 出: uint32_t 1 已触发 0 未触发 -* 注意事项: 无 -******************************************************************************************************************************************/ -uint32_t CAN_INTErrPassiveStat(CAN_TypeDef *CANx) -{ - return (CANx->IF & CAN_IF_ERRPASS_Msk) ? 1 : 0; -} - -/****************************************************************************************************************************************** * 函数名称: CAN_INTArbitrLostEn() * 功能说明: 仲裁失败中断使能 -* 输 入: CAN_TypeDef * CANx 指定要被设置的CAN接口，有效值包括CAN +* 输 入: CAN_TypeDef * CANx 指定要被设置的CAN接口，有效值包括CAN * 输 出: 无 * 注意事项: 无 ******************************************************************************************************************************************/ @@ -629,7 +557,7 @@ void CAN_INTArbitrLostEn(CAN_TypeDef *CANx) /****************************************************************************************************************************************** * 函数名称: CAN_INTArbitrLostDis() * 功能说明: 仲裁失败中断禁止 -* 输 入: CAN_TypeDef * CANx 指定要被设置的CAN接口，有效值包括CAN +* 输 入: CAN_TypeDef * CANx 指定要被设置的CAN接口，有效值包括CAN * 输 出: 无 * 注意事项: 无 ******************************************************************************************************************************************/ @@ -639,21 +567,9 @@ void CAN_INTArbitrLostDis(CAN_TypeDef *CANx) } /****************************************************************************************************************************************** -* 函数名称: CAN_INTArbitrLostStat() -* 功能说明: 仲裁失败中断是否触发 -* 输 入: CAN_TypeDef * CANx 指定要被设置的CAN接口，有效值包括CAN -* 输 出: uint32_t 1 已触发 0 未触发 -* 注意事项: 无 -******************************************************************************************************************************************/ -uint32_t CAN_INTArbitrLostStat(CAN_TypeDef *CANx) -{ - return (CANx->IF & CAN_IF_ARBLOST_Msk) ? 1 : 0; -} - -/****************************************************************************************************************************************** * 函数名称: CAN_INTBusErrorEn() * 功能说明: 总线错误中断使能 -* 输 入: CAN_TypeDef * CANx 指定要被设置的CAN接口，有效值包括CAN +* 输 入: CAN_TypeDef * CANx 指定要被设置的CAN接口，有效值包括CAN * 输 出: 无 * 注意事项: 无 ******************************************************************************************************************************************/ @@ -665,7 +581,7 @@ void CAN_INTBusErrorEn(CAN_TypeDef *CANx) /****************************************************************************************************************************************** * 函数名称: CAN_INTBusErrorDis() * 功能说明: 总线错误中断禁止 -* 输 入: CAN_TypeDef * CANx 指定要被设置的CAN接口，有效值包括CAN +* 输 入: CAN_TypeDef * CANx 指定要被设置的CAN接口，有效值包括CAN * 输 出: 无 * 注意事项: 无 ******************************************************************************************************************************************/ @@ -675,13 +591,13 @@ void CAN_INTBusErrorDis(CAN_TypeDef *CANx) } /****************************************************************************************************************************************** -* 函数名称: CAN_INTBusErrorStat() -* 功能说明: 总线错误中断是否触发 -* 输 入: CAN_TypeDef * CANx 指定要被设置的CAN接口，有效值包括CAN -* 输 出: uint32_t 1 已触发 0 未触发 -* 注意事项: 无 +* 函数名称: CAN_INTStat() +* 功能说明: 查询中断状态 +* 输 入: CAN_TypeDef * CANx 指定要被设置的CAN接口，有效值包括CAN +* 输 出: uint32_t 当前中断状态 +* 注意事项: CANx->IF读取清零，因此在中断ISR中只能读取一次，不能多次读取 ******************************************************************************************************************************************/ -uint32_t CAN_INTBusErrorStat(CAN_TypeDef *CANx) +uint32_t CAN_INTStat(CAN_TypeDef *CANx) { - return (CANx->IF & CAN_IF_BUSERR_Msk) ? 1 : 0; + return CANx->IF; } diff --git a/bsp/swm320-lq100/Libraries/SWM320_StdPeriph_Driver/SWM320_can.h b/bsp/swm320-lq100/Libraries/SWM320_StdPeriph_Driver/SWM320_can.h index 6a239c84b3..2b31a97c7d 100644 --- a/bsp/swm320-lq100/Libraries/SWM320_StdPeriph_Driver/SWM320_can.h +++ b/bsp/swm320-lq100/Libraries/SWM320_StdPeriph_Driver/SWM320_can.h @@ -1,22 +1,22 @@ #ifndef __SWM320_CAN_H__ #define __SWM320_CAN_H__ -#define CAN_FRAME_STD 0 -#define CAN_FRAME_EXT 1 +#define CAN_FRAME_STD 0 +#define CAN_FRAME_EXT 1 typedef struct { - uint8_t Mode; //CAN_MODE_NORMAL��CAN_MODE_LISTEN��CAN_MODE_SELFTEST - uint8_t CAN_BS1; //CAN_BS1_1tq��CAN_BS1_2tq��... ... ��CAN_BS1_16tq - uint8_t CAN_BS2; //CAN_BS2_1tq��CAN_BS2_2tq��... ... ��CAN_BS2_8tq - uint8_t CAN_SJW; //CAN_SJW_1tq��CAN_SJW_2tq��CAN_SJW_3tq��CAN_SJW_4tq - uint32_t Baudrate; //�����ʣ���λ�������ʣ�ȡֵ1--1000000 - uint8_t FilterMode; //CAN_FILTER_16b��CAN_FILTER_32b + uint8_t Mode; //CAN_MODE_NORMAL、CAN_MODE_LISTEN、CAN_MODE_SELFTEST + uint8_t CAN_BS1; //CAN_BS1_1tq、CAN_BS1_2tq、... ... 、CAN_BS1_16tq + uint8_t CAN_BS2; //CAN_BS2_1tq、CAN_BS2_2tq、... ... 、CAN_BS2_8tq + uint8_t CAN_SJW; //CAN_SJW_1tq、CAN_SJW_2tq、CAN_SJW_3tq、CAN_SJW_4tq + uint32_t Baudrate; //波特率，即位传输速率，取值1--1000000 + uint8_t FilterMode; //CAN_FILTER_16b、CAN_FILTER_32b union { - uint32_t FilterMask32b; //FilterCheck & (~FilterMask) == ID & (~FilterMask)��Messageͨ������ - struct // 0 must match 1 don't care - { + uint32_t FilterMask32b; //FilterCheck & (~FilterMask) == ID & (~FilterMask)的Message通过过滤 + struct + { // 0 must match 1 don't care uint16_t FilterMask16b1; uint16_t FilterMask16b2; }; @@ -30,59 +30,59 @@ typedef struct uint16_t FilterCheck16b2; }; }; - uint8_t RXNotEmptyIEn; //����FIFO�ǿգ������ݿɶ� - uint8_t RXOverflowIEn; //����FIFO����������ݶ�ʧ - uint8_t ArbitrLostIEn; //��������ʧ�ٲñ�ɽ��շ� - uint8_t ErrPassiveIEn; //����/���ʹ������ֵ�ﵽ127 + uint8_t RXNotEmptyIEn; //接收FIFO非空，有数据可读 + uint8_t RXOverflowIEn; //接收FIFO溢出，有数据丢失 + uint8_t ArbitrLostIEn; //控制器丢失仲裁变成接收方 + uint8_t ErrPassiveIEn; //接收/发送错误计数值达到127 } CAN_InitStructure; -#define CAN_MODE_NORMAL 0 //����ģʽ -#define CAN_MODE_LISTEN 1 //����ģʽ -#define CAN_MODE_SELFTEST 2 //�Բ�ģʽ +#define CAN_MODE_NORMAL 0 //常规模式 +#define CAN_MODE_LISTEN 1 //监听模式 +#define CAN_MODE_SELFTEST 2 //自测模式 -#define CAN_BS1_1tq 0 -#define CAN_BS1_2tq 1 -#define CAN_BS1_3tq 2 -#define CAN_BS1_4tq 3 -#define CAN_BS1_5tq 4 -#define CAN_BS1_6tq 5 -#define CAN_BS1_7tq 6 -#define CAN_BS1_8tq 7 -#define CAN_BS1_9tq 8 -#define CAN_BS1_10tq 9 -#define CAN_BS1_11tq 10 -#define CAN_BS1_12tq 11 -#define CAN_BS1_13tq 12 -#define CAN_BS1_14tq 13 -#define CAN_BS1_15tq 14 -#define CAN_BS1_16tq 15 +#define CAN_BS1_1tq 0 +#define CAN_BS1_2tq 1 +#define CAN_BS1_3tq 2 +#define CAN_BS1_4tq 3 +#define CAN_BS1_5tq 4 +#define CAN_BS1_6tq 5 +#define CAN_BS1_7tq 6 +#define CAN_BS1_8tq 7 +#define CAN_BS1_9tq 8 +#define CAN_BS1_10tq 9 +#define CAN_BS1_11tq 10 +#define CAN_BS1_12tq 11 +#define CAN_BS1_13tq 12 +#define CAN_BS1_14tq 13 +#define CAN_BS1_15tq 14 +#define CAN_BS1_16tq 15 -#define CAN_BS2_1tq 0 -#define CAN_BS2_2tq 1 -#define CAN_BS2_3tq 2 -#define CAN_BS2_4tq 3 -#define CAN_BS2_5tq 4 -#define CAN_BS2_6tq 5 -#define CAN_BS2_7tq 6 -#define CAN_BS2_8tq 7 +#define CAN_BS2_1tq 0 +#define CAN_BS2_2tq 1 +#define CAN_BS2_3tq 2 +#define CAN_BS2_4tq 3 +#define CAN_BS2_5tq 4 +#define CAN_BS2_6tq 5 +#define CAN_BS2_7tq 6 +#define CAN_BS2_8tq 7 -#define CAN_SJW_1tq 0 -#define CAN_SJW_2tq 1 -#define CAN_SJW_3tq 2 -#define CAN_SJW_4tq 3 +#define CAN_SJW_1tq 0 +#define CAN_SJW_2tq 1 +#define CAN_SJW_3tq 2 +#define CAN_SJW_4tq 3 -#define CAN_FILTER_16b 0 //����16λ������ -#define CAN_FILTER_32b 1 //һ��32λ������ +#define CAN_FILTER_16b 0 //两个16位过滤器 +#define CAN_FILTER_32b 1 //一个32位过滤器 typedef struct { - uint32_t id; //��ϢID - uint8_t remote; //��Ϣ�Ƿ�ΪԶ��֡ - uint8_t data[8]; //���յ������� - uint8_t size; //���յ������ݸ��� + uint32_t id; //消息ID + uint8_t format; //帧格式：CAN_FRAME_STD、CAN_FRAME_EXT + uint8_t remote; //消息是否为远程帧 + uint8_t size; //接收到的数据个数 + uint8_t data[8]; //接收到的数据 } CAN_RXMessage; - void CAN_Init(CAN_TypeDef *CANx, CAN_InitStructure *initStruct); void CAN_Open(CAN_TypeDef *CANx); void CAN_Close(CAN_TypeDef *CANx); @@ -104,38 +104,31 @@ void CAN_SetBaudrate(CAN_TypeDef *CANx, uint32_t baudrate, uint32_t CAN_BS1, uin void CAN_SetFilter32b(CAN_TypeDef *CANx, uint32_t check, uint32_t mask); void CAN_SetFilter16b(CAN_TypeDef *CANx, uint16_t check1, uint16_t mask1, uint16_t check2, uint16_t mask2); - void CAN_INTRXNotEmptyEn(CAN_TypeDef *CANx); void CAN_INTRXNotEmptyDis(CAN_TypeDef *CANx); -uint32_t CAN_INTRXNotEmptyStat(CAN_TypeDef *CANx); void CAN_INTTXBufEmptyEn(CAN_TypeDef *CANx); void CAN_INTTXBufEmptyDis(CAN_TypeDef *CANx); -uint32_t CAN_INTTXBufEmptyStat(CAN_TypeDef *CANx); void CAN_INTErrWarningEn(CAN_TypeDef *CANx); void CAN_INTErrWarningDis(CAN_TypeDef *CANx); -uint32_t CAN_INTErrWarningStat(CAN_TypeDef *CANx); void CAN_INTRXOverflowEn(CAN_TypeDef *CANx); void CAN_INTRXOverflowDis(CAN_TypeDef *CANx); -uint32_t CAN_INTRXOverflowStat(CAN_TypeDef *CANx); void CAN_INTRXOverflowClear(CAN_TypeDef *CANx); void CAN_INTWakeupEn(CAN_TypeDef *CANx); void CAN_INTWakeupDis(CAN_TypeDef *CANx); -uint32_t CAN_INTWakeupStat(CAN_TypeDef *CANx); void CAN_INTErrPassiveEn(CAN_TypeDef *CANx); void CAN_INTErrPassiveDis(CAN_TypeDef *CANx); -uint32_t CAN_INTErrPassiveStat(CAN_TypeDef *CANx); void CAN_INTArbitrLostEn(CAN_TypeDef *CANx); void CAN_INTArbitrLostDis(CAN_TypeDef *CANx); -uint32_t CAN_INTArbitrLostStat(CAN_TypeDef *CANx); void CAN_INTBusErrorEn(CAN_TypeDef *CANx); void CAN_INTBusErrorDis(CAN_TypeDef *CANx); -uint32_t CAN_INTBusErrorStat(CAN_TypeDef *CANx); + +uint32_t CAN_INTStat(CAN_TypeDef *CANx); #endif //__SWM320_CAN_H__ diff --git a/bsp/swm320-lq100/Libraries/SWM320_StdPeriph_Driver/SWM320_crc.c b/bsp/swm320-lq100/Libraries/SWM320_StdPeriph_Driver/SWM320_crc.c index 0258c90382..1255d3093e 100644 --- a/bsp/swm320-lq100/Libraries/SWM320_StdPeriph_Driver/SWM320_crc.c +++ b/bsp/swm320-lq100/Libraries/SWM320_StdPeriph_Driver/SWM320_crc.c @@ -1,10 +1,10 @@ /****************************************************************************************************************************************** -* �ļ�����: SWM320_crc.c -* ����˵��: SWM320��Ƭ����CRCģ�������� -* ����֧��: http://www.synwit.com.cn/e/tool/gbook/?bid=1 -* ע������: -* �汾����: V1.1.0 2017��10��25�� -* ������¼: +* 文件名称: SWM320_crc.c +* 功能说明: SWM320单片机的CRC模块驱动库 +* 技术支持: http://www.synwit.com.cn/e/tool/gbook/?bid=1 +* 注意事项: +* 版本日期: V1.1.0 2017年10月25日 +* 升级记录: * * ******************************************************************************************************************************************* @@ -21,17 +21,16 @@ #include "SWM320.h" #include "SWM320_crc.h" - /****************************************************************************************************************************************** -* ��������: CRC_Init() -* ����˵��: CRC ��ʼ�� -* �� ��: CRC_TypeDef * CRCx ָ��Ҫ�����õ�CRC�ӿڣ���Чֵ����CRC -* uint32_t mode ����ģʽ����Чֵ�У�CRC32_IN32��CRC32_IN16��CRC32_IN8��CRC16_IN16��CRC16_IN8 -* uint32_t out_not �������Ƿ�ȡ�� -* uint32_t out_rev �������Ƿ�ת -* uint32_t ini_val CRC��ʼֵ -* �� ��: �� -* ע������: �� +* 函数名称: CRC_Init() +* 功能说明: CRC 初始化 +* 输 入: CRC_TypeDef * CRCx 指定要被设置的CRC接口，有效值包括CRC +* uint32_t mode 工作模式，有效值有：CRC32_IN32、CRC32_IN16、CRC32_IN8、CRC16_IN16、CRC16_IN8 +* uint32_t out_not 输出结果是否取反 +* uint32_t out_rev 输出结果是否翻转 +* uint32_t ini_val CRC初始值 +* 输 出: 无 +* 注意事项: 无 ******************************************************************************************************************************************/ void CRC_Init(CRC_TypeDef *CRCx, uint32_t mode, uint32_t out_not, uint32_t out_rev, uint32_t ini_val) { diff --git a/bsp/swm320-lq100/Libraries/SWM320_StdPeriph_Driver/SWM320_crc.h b/bsp/swm320-lq100/Libraries/SWM320_StdPeriph_Driver/SWM320_crc.h index 947bf85455..54de1301b2 100644 --- a/bsp/swm320-lq100/Libraries/SWM320_StdPeriph_Driver/SWM320_crc.h +++ b/bsp/swm320-lq100/Libraries/SWM320_StdPeriph_Driver/SWM320_crc.h @@ -1,23 +1,20 @@ #ifndef __SWM320_CRC_H__ #define __SWM320_CRC_H__ - -#define CRC32_IN32 0 //CRC32�㷨����������32λ -#define CRC32_IN16 2 //CRC32�㷨����������16λ -#define CRC32_IN8 4 //CRC32�㷨���������� 8λ -#define CRC16_IN16 3 //CRC16�㷨����������16λ -#define CRC16_IN8 5 //CRC16�㷨���������� 8λ - +#define CRC32_IN32 0 //CRC32算法，输入数据32位 +#define CRC32_IN16 2 //CRC32算法，输入数据16位 +#define CRC32_IN8 4 //CRC32算法，输入数据 8位 +#define CRC16_IN16 3 //CRC16算法，输入数据16位 +#define CRC16_IN8 5 //CRC16算法，输入数据 8位 void CRC_Init(CRC_TypeDef *CRCx, uint32_t mode, uint32_t out_not, uint32_t out_rev, uint32_t ini_val); - /****************************************************************************************************************************************** -* ��������: CRC_Write() -* ����˵��: CRCд������ -* �� ��: uint32_t data Ҫд������� -* �� ��: �� -* ע������: �� +* 函数名称: CRC_Write() +* 功能说明: CRC写入数据 +* 输 入: uint32_t data 要写入的数据 +* 输 出: 无 +* 注意事项: 无 ******************************************************************************************************************************************/ static __INLINE void CRC_Write(uint32_t data) { @@ -25,11 +22,11 @@ static __INLINE void CRC_Write(uint32_t data) } /****************************************************************************************************************************************** -* ��������: CRC_Result() -* ����˵��: ��ȡCRC������ -* �� ��: �� -* �� ��: uint32_t CRC ������ -* ע������: �� +* 函数名称: CRC_Result() +* 功能说明: 获取CRC计算结果 +* 输 入: 无 +* 输 出: uint32_t CRC 计算结果 +* 注意事项: 无 ******************************************************************************************************************************************/ static __INLINE uint32_t CRC_Result(void) { diff --git a/bsp/swm320-lq100/Libraries/SWM320_StdPeriph_Driver/SWM320_dma.c b/bsp/swm320-lq100/Libraries/SWM320_StdPeriph_Driver/SWM320_dma.c index 3abb4c4b3a..70e7ac559b 100644 --- a/bsp/swm320-lq100/Libraries/SWM320_StdPeriph_Driver/SWM320_dma.c +++ b/bsp/swm320-lq100/Libraries/SWM320_StdPeriph_Driver/SWM320_dma.c @@ -1,10 +1,10 @@ /****************************************************************************************************************************************** -* �ļ�����: SWM320_dma.c -* ����˵��: SWM320��Ƭ����DMA���������� -* ����֧��: http://www.synwit.com.cn/e/tool/gbook/?bid=1 -* ע������: -* �汾����: V1.1.0 2017��10��25�� -* ������¼: +* 文件名称: SWM320_dma.c +* 功能说明: SWM320单片机的DMA功能驱动库 +* 技术支持: http://www.synwit.com.cn/e/tool/gbook/?bid=1 +* 注意事项: +* 版本日期: V1.1.0 2017年10月25日 +* 升级记录: * * ******************************************************************************************************************************************* @@ -22,23 +22,23 @@ #include "SWM320_dma.h" /****************************************************************************************************************************************** -* ��������: DMA_CHM_Config() -* ����˵��: DMAͨ�����ã����ڴ洢���䣨��Flash��RAM�䣩�������� -* �� ��: uint32_t chn ָ��Ҫ���õ�ͨ������Чֵ��DMA_CH0��DMA_CH1��DMA_CH1 -* uint32_t src_addr Դ��ַ�������ֶ��룬����ַ�����2λ������00 -* uint32_t src_addr_incr 0 �̶���ַ 1 ��ַ���� -* uint32_t dst_addr Ŀ�ĵ�ַ�������ֶ��룬����ַ�����2λ������00 -* uint32_t dst_addr_incr 0 �̶���ַ 1 ��ַ���� -* uint32_t num_word Ҫ���˵��������������1024 -* uint32_t int_en �ж�ʹ�ܣ�1 ���ݰ�����ɺ�����ж� 0 ���ݰ�����ɺ����ж� -* �� ��: �� -* ע������: ��������������Ϊ��Ԫ�������ֽ� +* 函数名称: DMA_CHM_Config() +* 功能说明: DMA通道配置，用于存储器间（如Flash和RAM间）搬运数据 +* 输 入: uint32_t chn 指定要配置的通道，有效值有DMA_CH0、DMA_CH1、DMA_CH2 +* uint32_t src_addr 源地址，必须字对齐，即地址的最低2位必须是00 +* uint32_t src_addr_incr 0 固定地址 1 地址递增 +* uint32_t dst_addr 目的地址，必须字对齐，即地址的最低2位必须是00 +* uint32_t dst_addr_incr 0 固定地址 1 地址递增 +* uint32_t num_word 要搬运的数据字数，最大1024 +* uint32_t int_en 中断使能，1 数据搬运完成后产生中断 0 数据搬运完成后不产生中断 +* 输 出: 无 +* 注意事项: 搬运数据量以字为单元，不是字节 ******************************************************************************************************************************************/ void DMA_CHM_Config(uint32_t chn, uint32_t src_addr, uint32_t src_addr_incr, uint32_t dst_addr, uint32_t dst_addr_incr, uint32_t num_word, uint32_t int_en) { - DMA->EN = 1; //ÿ��ͨ�������Լ������Ŀ��ؿ��ƣ������ܿ��ؿ�����һֱ������ + DMA->EN = 1; //每个通道都有自己独立的开关控制，所以总开关可以是一直开启的 - DMA_CH_Close(chn); //����ǰ�ȹرո�ͨ�� + DMA_CH_Close(chn); //配置前先关闭该通道 DMA->CH[chn].SRC = src_addr; DMA->CH[chn].DST = dst_addr; @@ -50,10 +50,12 @@ void DMA_CHM_Config(uint32_t chn, uint32_t src_addr, uint32_t src_addr_incr, uin (dst_addr_incr << DMA_AM_DSTAM_Pos) | (0 << DMA_AM_BURST_Pos); - DMA->IF = (1 << chn); //����жϱ�־ + DMA->IF = (1 << chn); //清除中断标志 DMA->IE |= (1 << chn); - if (int_en) DMA->IM &= ~(1 << chn); - else DMA->IM |= (1 << chn); + if (int_en) + DMA->IM &= ~(1 << chn); + else + DMA->IM |= (1 << chn); if (int_en) { @@ -61,16 +63,16 @@ void DMA_CHM_Config(uint32_t chn, uint32_t src_addr, uint32_t src_addr_incr, uin } else { - //���ܵ���NVIC_DisalbeIRQ(DMA_IRQn)����Ϊ����ͨ������ʹ��DMA�ж� + //不能调用NVIC_DisalbeIRQ(DMA_IRQn)，因为其他通道可能使用DMA中断 } } /****************************************************************************************************************************************** -* ��������: DMA_CH_Open() -* ����˵��: DMAͨ���� -* �� ��: uint32_t chn ָ��Ҫ���õ�ͨ������Чֵ��DMA_CH0��DMA_CH1��DMA_CH1 -* �� ��: �� -* ע������: �� +* 函数名称: DMA_CH_Open() +* 功能说明: DMA通道打开 +* 输 入: uint32_t chn 指定要配置的通道，有效值有DMA_CH0、DMA_CH1、DMA_CH2 +* 输 出: 无 +* 注意事项: 无 ******************************************************************************************************************************************/ void DMA_CH_Open(uint32_t chn) { @@ -78,11 +80,11 @@ void DMA_CH_Open(uint32_t chn) } /****************************************************************************************************************************************** -* ��������: DMA_CH_Close() -* ����˵��: DMAͨ���ر� -* �� ��: uint32_t chn ָ��Ҫ���õ�ͨ������Чֵ��DMA_CH0��DMA_CH1��DMA_CH1 -* �� ��: �� -* ע������: �� +* 函数名称: DMA_CH_Close() +* 功能说明: DMA通道关闭 +* 输 入: uint32_t chn 指定要配置的通道，有效值有DMA_CH0、DMA_CH1、DMA_CH2 +* 输 出: 无 +* 注意事项: 无 ******************************************************************************************************************************************/ void DMA_CH_Close(uint32_t chn) { @@ -90,11 +92,11 @@ void DMA_CH_Close(uint32_t chn) } /****************************************************************************************************************************************** -* ��������: DMA_CH_INTEn() -* ����˵��: DMA�ж�ʹ�ܣ����ݰ�����ɺ��ж� -* �� ��: uint32_t chn ָ��Ҫ���õ�ͨ������Чֵ��DMA_CH0��DMA_CH1��DMA_CH1 -* �� ��: �� -* ע������: �� +* 函数名称: DMA_CH_INTEn() +* 功能说明: DMA中断使能，数据搬运完成后触发中断 +* 输 入: uint32_t chn 指定要配置的通道，有效值有DMA_CH0、DMA_CH1、DMA_CH2 +* 输 出: 无 +* 注意事项: 无 ******************************************************************************************************************************************/ void DMA_CH_INTEn(uint32_t chn) { @@ -102,11 +104,11 @@ void DMA_CH_INTEn(uint32_t chn) } /****************************************************************************************************************************************** -* ��������: DMA_CH_INTDis() -* ����˵��: DMA�жϽ�ֹ�����ݰ�����ɺ����ж� -* �� ��: uint32_t chn ָ��Ҫ���õ�ͨ������Чֵ��DMA_CH0��DMA_CH1��DMA_CH1 -* �� ��: �� -* ע������: �� +* 函数名称: DMA_CH_INTDis() +* 功能说明: DMA中断禁止，数据搬运完成后不触发中断 +* 输 入: uint32_t chn 指定要配置的通道，有效值有DMA_CH0、DMA_CH1、DMA_CH2 +* 输 出: 无 +* 注意事项: 无 ******************************************************************************************************************************************/ void DMA_CH_INTDis(uint32_t chn) { @@ -114,11 +116,11 @@ void DMA_CH_INTDis(uint32_t chn) } /****************************************************************************************************************************************** -* ��������: DMA_CH_INTClr() -* ����˵��: DMA�жϱ�־��� -* �� ��: uint32_t chn ָ��Ҫ���õ�ͨ������Чֵ��DMA_CH0��DMA_CH1��DMA_CH1 -* �� ��: �� -* ע������: �� +* 函数名称: DMA_CH_INTClr() +* 功能说明: DMA中断标志清除 +* 输 入: uint32_t chn 指定要配置的通道，有效值有DMA_CH0、DMA_CH1、DMA_CH2 +* 输 出: 无 +* 注意事项: 无 ******************************************************************************************************************************************/ void DMA_CH_INTClr(uint32_t chn) { @@ -126,11 +128,11 @@ void DMA_CH_INTClr(uint32_t chn) } /****************************************************************************************************************************************** -* ��������: DMA_CH_INTStat() -* ����˵��: DMA�ж�״̬��ѯ -* �� ��: uint32_t chn ָ��Ҫ���õ�ͨ������Чֵ��DMA_CH0��DMA_CH1��DMA_CH1 -* �� ��: uint32_t 1 ���ݰ������ 0 ���ݰ���δ��� -* ע������: �� +* 函数名称: DMA_CH_INTStat() +* 功能说明: DMA中断状态查询 +* 输 入: uint32_t chn 指定要配置的通道，有效值有DMA_CH0、DMA_CH1、DMA_CH2 +* 输 出: uint32_t 1 数据搬运完成 0 数据搬运未完成 +* 注意事项: 无 ******************************************************************************************************************************************/ uint32_t DMA_CH_INTStat(uint32_t chn) { diff --git a/bsp/swm320-lq100/Libraries/SWM320_StdPeriph_Driver/SWM320_dma.h b/bsp/swm320-lq100/Libraries/SWM320_StdPeriph_Driver/SWM320_dma.h index fc4cd98ca8..b7391a0e9e 100644 --- a/bsp/swm320-lq100/Libraries/SWM320_StdPeriph_Driver/SWM320_dma.h +++ b/bsp/swm320-lq100/Libraries/SWM320_StdPeriph_Driver/SWM320_dma.h @@ -1,20 +1,17 @@ #ifndef __SWM320_DMA_H__ #define __SWM320_DMA_H__ +#define DMA_CH0 0 +#define DMA_CH1 1 +#define DMA_CH2 2 -#define DMA_CH0 0 -#define DMA_CH1 1 -#define DMA_CH2 2 - - -void DMA_CHM_Config(uint32_t chn, uint32_t src_addr, uint32_t src_addr_incr, uint32_t dst_addr, uint32_t dst_addr_incr, uint32_t num_word, uint32_t int_en); //DMAͨ�����ã����ڴ洢���䣨��Flash��RAM�䣩�������� -void DMA_CH_Open(uint32_t chn); //DMAͨ���� -void DMA_CH_Close(uint32_t chn); //DMAͨ���ر� - -void DMA_CH_INTEn(uint32_t chn); //DMA�ж�ʹ�ܣ����ݰ�����ɺ��ж� -void DMA_CH_INTDis(uint32_t chn); //DMA�жϽ�ֹ�����ݰ�����ɺ����ж� -void DMA_CH_INTClr(uint32_t chn); //DMA�жϱ�־��� -uint32_t DMA_CH_INTStat(uint32_t chn); //DMA�ж�״̬��ѯ��1 ���ݰ������ 0 ���ݰ���δ��� +void DMA_CHM_Config(uint32_t chn, uint32_t src_addr, uint32_t src_addr_incr, uint32_t dst_addr, uint32_t dst_addr_incr, uint32_t num_word, uint32_t int_en); //DMA通道配置，用于存储器间（如Flash和RAM间）搬运数据 +void DMA_CH_Open(uint32_t chn); //DMA通道打开 +void DMA_CH_Close(uint32_t chn); //DMA通道关闭 +void DMA_CH_INTEn(uint32_t chn); //DMA中断使能，数据搬运完成后触发中断 +void DMA_CH_INTDis(uint32_t chn); //DMA中断禁止，数据搬运完成后不触发中断 +void DMA_CH_INTClr(uint32_t chn); //DMA中断标志清除 +uint32_t DMA_CH_INTStat(uint32_t chn); //DMA中断状态查询，1 数据搬运完成 0 数据搬运未完成 #endif //__SWM320_DMA_H__ diff --git a/bsp/swm320-lq100/Libraries/SWM320_StdPeriph_Driver/SWM320_exti.c b/bsp/swm320-lq100/Libraries/SWM320_StdPeriph_Driver/SWM320_exti.c index 0214767e6b..6bebc75601 100644 --- a/bsp/swm320-lq100/Libraries/SWM320_StdPeriph_Driver/SWM320_exti.c +++ b/bsp/swm320-lq100/Libraries/SWM320_StdPeriph_Driver/SWM320_exti.c @@ -1,10 +1,10 @@ /****************************************************************************************************************************************** -* �ļ�����: SWM320_exti.c -* ����˵��: SWM320��Ƭ�����ⲿ�жϹ��������� -* ����֧��: http://www.synwit.com.cn/e/tool/gbook/?bid=1 -* ע������: -* �汾����: V1.1.0 2017��10��25�� -* ������¼: +* 文件名称: SWM320_exti.c +* 功能说明: SWM320单片机的外部中断功能驱动库 +* 技术支持: http://www.synwit.com.cn/e/tool/gbook/?bid=1 +* 注意事项: +* 版本日期: V1.1.0 2017年10月25日 +* 升级记录: * ******************************************************************************************************************************************* * @attention @@ -21,57 +21,57 @@ #include "SWM320_exti.h" /****************************************************************************************************************************************** -* ��������: EXTI_Init() -* ����˵��: ָ�������ⲿ�жϳ�ʼ�� -* �� ��: GPIO_TypeDef * GPIOx ָ�������ⲿ�жϵ�GPIO�˿ڣ���Чֵ����GPIOA��GPIOB��GPIOC��GPIOM��GPION��GPIOP -* uint32_t n ָ�������ⲿ�жϵ�GPIO���ţ���Чֵ����PIN0��PIN1��PIN2��... ... PIN22��PIN23 -* uint32_t mode ��Чֵ��EXTI_FALL_EDGE��EXTI_RISE_EDGE��EXTI_BOTH_EDGE��EXTI_LOW_LEVEL��EXTI_HIGH_LEVEL -* �� ��: �� -* ע������: ����GPIOA��GPIOB��GPIOC��GPIOM��PIN0--7���ż����Խ���NVIC�е������жϣ���GPIOA0_IRQn����Ҳ���Խ���NVIC�����жϣ�GPIOA_IRQn���� -* ���Բ��ڴ˺����е���NVIC_EnableIRQ()ʹ��NVIC�жϣ��Ӷ����Ը�����Ҫ����NVIC_EnableIRQ(GPIOA0_IRQn)��NVIC_EnableIRQ(GPIOA_IRQn) +* 函数名称: EXTI_Init() +* 功能说明: 指定引脚外部中断初始化 +* 输 入: GPIO_TypeDef * GPIOx 指定产生外部中断的GPIO端口，有效值包括GPIOA、GPIOB、GPIOC、GPIOM、GPION、GPIOP +* uint32_t n 指定产生外部中断的GPIO引脚，有效值包括PIN0、PIN1、PIN2、... ... PIN22、PIN23 +* uint32_t mode 有效值有EXTI_FALL_EDGE、EXTI_RISE_EDGE、EXTI_BOTH_EDGE、EXTI_LOW_LEVEL、EXTI_HIGH_LEVEL +* 输 出: 无 +* 注意事项: 由于GPIOA、GPIOB、GPIOC、GPIOM的PIN0--7引脚即可以接入NVIC中的引脚中断（如GPIOA0_IRQn），也可以接入NVIC的组中断（GPIOA_IRQn）， +* 所以不在此函数中调用NVIC_EnableIRQ()使能NVIC中断，从而可以根据需要调用NVIC_EnableIRQ(GPIOA0_IRQn)和NVIC_EnableIRQ(GPIOA_IRQn) ******************************************************************************************************************************************/ void EXTI_Init(GPIO_TypeDef *GPIOx, uint32_t n, uint32_t mode) { - EXTI_Close(GPIOx, n); //���ùؼ��Ĵ���ǰ�ȹر� + EXTI_Close(GPIOx, n); //配置关键寄存器前先关闭 if (mode & 0x10) { - GPIOx->INTLVLTRG |= (0x01 << n); //��ƽ���� + GPIOx->INTLVLTRG |= (0x01 << n); //电平触发 if (mode & 0x01) - GPIOx->INTRISEEN |= (0x01 << n); //�ߵ�ƽ���� + GPIOx->INTRISEEN |= (0x01 << n); //高电平触发 else - GPIOx->INTRISEEN &= ~(0x01 << n); //�͵�ƽ���� + GPIOx->INTRISEEN &= ~(0x01 << n); //低电平触发 } else { - GPIOx->INTLVLTRG &= ~(0x01 << n); //���ش��� + GPIOx->INTLVLTRG &= ~(0x01 << n); //边沿触发 if (mode & 0x02) { - GPIOx->INTBE |= (0x01 << n); //˫���ش��� + GPIOx->INTBE |= (0x01 << n); //双边沿触发 } else { - GPIOx->INTBE &= ~(0x01 << n); //�����ش��� + GPIOx->INTBE &= ~(0x01 << n); //单边沿触发 if (mode & 0x01) - GPIOx->INTRISEEN |= (0x01 << n); //�����ش��� + GPIOx->INTRISEEN |= (0x01 << n); //上升沿触发 else - GPIOx->INTRISEEN &= ~(0x01 << n); //�½��ش��� + GPIOx->INTRISEEN &= ~(0x01 << n); //下降沿触发 } } - GPIOx->INTCLR = (1 << n); //�������Ϊģʽ���ÿ��ܲ������ж� + GPIOx->INTCLR = (1 << n); //清除掉因为模式配置可能产生的中断 } /****************************************************************************************************************************************** -* ��������: EXTI_Open() -* ����˵��: ָ�������ⲿ�жϴ���ʹ�ܣ� -* �� ��: GPIO_TypeDef * GPIOx ָ�������ⲿ�жϵ�GPIO�˿ڣ���Чֵ����GPIOA��GPIOB��GPIOC��GPIOM��GPION��GPIOP -* uint32_t n ָ�������ⲿ�жϵ�GPIO���ţ���Чֵ����PIN0��PIN1��PIN2��... ... PIN22��PIN23 -* �� ��: �� -* ע������: �� +* 函数名称: EXTI_Open() +* 功能说明: 指定引脚外部中断打开（即使能） +* 输 入: GPIO_TypeDef * GPIOx 指定产生外部中断的GPIO端口，有效值包括GPIOA、GPIOB、GPIOC、GPIOM、GPION、GPIOP +* uint32_t n 指定产生外部中断的GPIO引脚，有效值包括PIN0、PIN1、PIN2、... ... PIN22、PIN23 +* 输 出: 无 +* 注意事项: 无 ******************************************************************************************************************************************/ void EXTI_Open(GPIO_TypeDef *GPIOx, uint32_t n) { @@ -79,12 +79,12 @@ void EXTI_Open(GPIO_TypeDef *GPIOx, uint32_t n) } /****************************************************************************************************************************************** -* ��������: EXTI_Close() -* ����˵��: ָ�������ⲿ�жϹرգ������ܣ� -* �� ��: GPIO_TypeDef * GPIOx ָ�������ⲿ�жϵ�GPIO�˿ڣ���Чֵ����GPIOA��GPIOB��GPIOC��GPIOM��GPION��GPIOP -* uint32_t n ָ�������ⲿ�жϵ�GPIO���ţ���Чֵ����PIN0��PIN1��PIN2��... ... PIN22��PIN23 -* �� ��: �� -* ע������: �� +* 函数名称: EXTI_Close() +* 功能说明: 指定引脚外部中断关闭（即禁能） +* 输 入: GPIO_TypeDef * GPIOx 指定产生外部中断的GPIO端口，有效值包括GPIOA、GPIOB、GPIOC、GPIOM、GPION、GPIOP +* uint32_t n 指定产生外部中断的GPIO引脚，有效值包括PIN0、PIN1、PIN2、... ... PIN22、PIN23 +* 输 出: 无 +* 注意事项: 无 ******************************************************************************************************************************************/ void EXTI_Close(GPIO_TypeDef *GPIOx, uint32_t n) { @@ -92,12 +92,12 @@ void EXTI_Close(GPIO_TypeDef *GPIOx, uint32_t n) } /****************************************************************************************************************************************** -* ��������: EXTI_State() -* ����˵��: ָ�������Ƿ����ж� -* �� ��: GPIO_TypeDef * GPIOx ָ�������ⲿ�жϵ�GPIO�˿ڣ���Чֵ����GPIOA��GPIOB��GPIOC��GPIOM��GPION��GPIOP -* uint32_t n ָ�������ⲿ�жϵ�GPIO���ţ���Чֵ����PIN0��PIN1��PIN2��... ... PIN22��PIN23 -* �� ��: uint32_t 1 �����Ŵ������ж� 0 ������δ�����ж� -* ע������: �� +* 函数名称: EXTI_State() +* 功能说明: 指定引脚是否触发了中断 +* 输 入: GPIO_TypeDef * GPIOx 指定产生外部中断的GPIO端口，有效值包括GPIOA、GPIOB、GPIOC、GPIOM、GPION、GPIOP +* uint32_t n 指定产生外部中断的GPIO引脚，有效值包括PIN0、PIN1、PIN2、... ... PIN22、PIN23 +* 输 出: uint32_t 1 此引脚触发了中断 0 此引脚未触发中断 +* 注意事项: 无 ******************************************************************************************************************************************/ uint32_t EXTI_State(GPIO_TypeDef *GPIOx, uint32_t n) { @@ -105,25 +105,25 @@ uint32_t EXTI_State(GPIO_TypeDef *GPIOx, uint32_t n) } /****************************************************************************************************************************************** -* ��������: EXTI_RawState() -* ����˵��: ָ�������Ƿ������/���жϴ��������������жϹر�ʱ��ͨ�����ô˺����Բ�ѯ�ķ�ʽ����������Ƿ������/���жϴ������� -* �� ��: GPIO_TypeDef * GPIOx ָ�������ⲿ�жϵ�GPIO�˿ڣ���Чֵ����GPIOA��GPIOB��GPIOC��GPIOM��GPION��GPIOP -* uint32_t n ָ�������ⲿ�жϵ�GPIO���ţ���Чֵ����PIN0��PIN1��PIN2��... ... PIN22��PIN23 -* �� ��: uint32_t 1 �����������/���жϴ������� 0 ������δ�����/���жϴ������� -* ע������: �� +* 函数名称: EXTI_RawState() +* 功能说明: 指定引脚是否满足过/了中断触发条件，当此中断关闭时可通过调用此函数以查询的方式检测引脚上是否满足过/了中断触发条件 +* 输 入: GPIO_TypeDef * GPIOx 指定产生外部中断的GPIO端口，有效值包括GPIOA、GPIOB、GPIOC、GPIOM、GPION、GPIOP +* uint32_t n 指定产生外部中断的GPIO引脚，有效值包括PIN0、PIN1、PIN2、... ... PIN22、PIN23 +* 输 出: uint32_t 1 此引脚满足过/了中断触发条件 0 此引脚未满足过/了中断触发条件 +* 注意事项: 无 ******************************************************************************************************************************************/ uint32_t EXTI_RawState(GPIO_TypeDef *GPIOx, uint32_t n) { - return (GPIOx->INTRAWSTAT >> 1) & 0x01; + return (GPIOx->INTRAWSTAT >> n) & 0x01; } /****************************************************************************************************************************************** -* ��������: EXTI_Clear() -* ����˵��: ָ�������ⲿ�ж������������жϱ�־�������ٴν�����жϣ� -* �� ��: GPIO_TypeDef * GPIOx ָ�������ⲿ�жϵ�GPIO�˿ڣ���Чֵ����GPIOA��GPIOB��GPIOC��GPIOM��GPION��GPIOP -* uint32_t n ָ�������ⲿ�жϵ�GPIO���ţ���Чֵ����PIN0��PIN1��PIN2��... ... PIN22��PIN23 -* �� ��: �� -* ע������: ֻ��������ش����жϵı�־����ƽ�����жϵı�־�������ֻ�������ŵ�ƽ�������жϴ���������Ӳ���Զ���� +* 函数名称: EXTI_Clear() +* 功能说明: 指定引脚外部中断清除（即清除中断标志，以免再次进入此中断） +* 输 入: GPIO_TypeDef * GPIOx 指定产生外部中断的GPIO端口，有效值包括GPIOA、GPIOB、GPIOC、GPIOM、GPION、GPIOP +* uint32_t n 指定产生外部中断的GPIO引脚，有效值包括PIN0、PIN1、PIN2、... ... PIN22、PIN23 +* 输 出: 无 +* 注意事项: 只能清除边沿触发中断的标志，电平触发中断的标志无法清除，只能在引脚电平不符合中断触发条件后硬件自动清除 ******************************************************************************************************************************************/ void EXTI_Clear(GPIO_TypeDef *GPIOx, uint32_t n) { diff --git a/bsp/swm320-lq100/Libraries/SWM320_StdPeriph_Driver/SWM320_exti.h b/bsp/swm320-lq100/Libraries/SWM320_StdPeriph_Driver/SWM320_exti.h index f645fa69f8..818d647745 100644 --- a/bsp/swm320-lq100/Libraries/SWM320_StdPeriph_Driver/SWM320_exti.h +++ b/bsp/swm320-lq100/Libraries/SWM320_StdPeriph_Driver/SWM320_exti.h @@ -1,20 +1,18 @@ #ifndef __SWM320_EXTI_H__ #define __SWM320_EXTI_H__ -void EXTI_Init(GPIO_TypeDef *GPIOx, uint32_t n, uint32_t mode); //ָ�������ⲿ�жϳ�ʼ�� -void EXTI_Open(GPIO_TypeDef *GPIOx, uint32_t n); //ָ�������ⲿ�жϴ���ʹ�ܣ� -void EXTI_Close(GPIO_TypeDef *GPIOx, uint32_t n); //ָ�������ⲿ�жϹرգ������ܣ� +void EXTI_Init(GPIO_TypeDef *GPIOx, uint32_t n, uint32_t mode); //指定引脚外部中断初始化 +void EXTI_Open(GPIO_TypeDef *GPIOx, uint32_t n); //指定引脚外部中断打开（即使能） +void EXTI_Close(GPIO_TypeDef *GPIOx, uint32_t n); //指定引脚外部中断关闭（即禁能） -uint32_t EXTI_State(GPIO_TypeDef *GPIOx, uint32_t n); //ָ�������Ƿ����ж� -uint32_t EXTI_RawState(GPIO_TypeDef *GPIOx, uint32_t n); //ָ�������Ƿ������/���жϴ��������������жϹر�ʱ��ͨ�����ô˺����Բ�ѯ�ķ�ʽ����������Ƿ������/���жϴ������� -void EXTI_Clear(GPIO_TypeDef *GPIOx, uint32_t n); //ָ�������ⲿ�ж������������жϱ�־�������ٴν�����жϣ� - - -#define EXTI_FALL_EDGE 0x00 //�½��ش����ж� -#define EXTI_RISE_EDGE 0x01 //�����ش����ж� -#define EXTI_BOTH_EDGE 0x02 //˫���ش����ж� -#define EXTI_LOW_LEVEL 0x10 //�͵�ƽ�����ж� -#define EXTI_HIGH_LEVEL 0x11 //�ߵ�ƽ�����ж� +uint32_t EXTI_State(GPIO_TypeDef *GPIOx, uint32_t n); //指定引脚是否触发了中断 +uint32_t EXTI_RawState(GPIO_TypeDef *GPIOx, uint32_t n); //指定引脚是否满足过/了中断触发条件，当此中断关闭时可通过调用此函数以查询的方式检测引脚上是否满足过/了中断触发条件 +void EXTI_Clear(GPIO_TypeDef *GPIOx, uint32_t n); //指定引脚外部中断清除（即清除中断标志，以免再次进入此中断） +#define EXTI_FALL_EDGE 0x00 //下降沿触发中断 +#define EXTI_RISE_EDGE 0x01 //上升沿触发中断 +#define EXTI_BOTH_EDGE 0x02 //双边沿触发中断 +#define EXTI_LOW_LEVEL 0x10 //低电平触发中断 +#define EXTI_HIGH_LEVEL 0x11 //高电平触发中断 #endif //__SWM320_EXTI_H__ diff --git a/bsp/swm320-lq100/Libraries/SWM320_StdPeriph_Driver/SWM320_flash.c b/bsp/swm320-lq100/Libraries/SWM320_StdPeriph_Driver/SWM320_flash.c index fa619e566c..6cb6e125d4 100644 --- a/bsp/swm320-lq100/Libraries/SWM320_StdPeriph_Driver/SWM320_flash.c +++ b/bsp/swm320-lq100/Libraries/SWM320_StdPeriph_Driver/SWM320_flash.c @@ -1,10 +1,10 @@ /****************************************************************************************************************************************** -* �ļ�����: SWM320_flash.c -* ����˵��: ʹ��оƬ��IAP���ܽ�Ƭ��Flashģ���EEPROM���������ݣ������ʧ -* ����֧��: http://www.synwit.com.cn/e/tool/gbook/?bid=1 -* ע������: -* �汾����: V1.1.0 2017��10��25�� -* ������¼: +* 文件名称: SWM320_flash.c +* 功能说明: 使用芯片的IAP功能将片上Flash模拟成EEPROM来保存数据，掉电后不丢失 +* 技术支持: http://www.synwit.com.cn/e/tool/gbook/?bid=1 +* 注意事项: +* 版本日期: V1.1.0 2017年10月25日 +* 升级记录: ******************************************************************************************************************************************* * @attention * @@ -19,77 +19,77 @@ #include "SWM320.h" #include "SWM320_flash.h" +IAP_Cache_Reset_t IAP_Cache_Reset = (IAP_Cache_Reset_t)0x11000601; +IAP_Flash_Param_t IAP_Flash_Param = (IAP_Flash_Param_t)0x11000681; +IAP_Flash_Erase_t IAP_Flash_Erase = (IAP_Flash_Erase_t)0x11000781; +IAP_Flash_Write_t IAP_Flash_Write = (IAP_Flash_Write_t)0x11000801; -__attribute__((section("PlaceInRAM"))) -static void switchTo80M(void) +/****************************************************************************************************************************************** +* 函数名称: FLASH_Erase() +* 功能说明: 片内Flash擦除 +* 输 入: uint32_t addr 擦除地址，扇区大小为4K Byte +* 输 出: 无 +* 注意事项: 无 +******************************************************************************************************************************************/ +void FLASH_Erase(uint32_t addr) { - uint32_t i; + __disable_irq(); - for (i = 0; i < 50; i++) __NOP(); + IAP_Flash_Erase(addr / 0x1000); - FLASH->CFG0 = 0x4bf; - FLASH->CFG1 = 0xabfc7a6e; + IAP_Cache_Reset(); - for (i = 0; i < 50; i++) __NOP(); + __enable_irq(); } /****************************************************************************************************************************************** -* ��������: FLASH_Erase() -* ����˵��: Ƭ��Flash���� -* �� ��: uint32_t addr ������ַ -* �� ��: �� -* ע������: �� +* 函数名称: FLASH_Write() +* 功能说明: 片内Flash写入 +* 输 入: uint32_t addr 写入地址 +* uint32_t buff[] 要写入的数据 +* uint32_t count 要写入数据的个数，以字为单位，且必须是4的整数倍，即最少写入4个字 +* 输 出: 无 +* 注意事项: 写入数据个数必须是4的整数倍，即最少写入4个字 ******************************************************************************************************************************************/ -void FLASH_Erase(uint32_t addr) +void FLASH_Write(uint32_t addr, uint32_t buff[], uint32_t count) { -// switchTo80M(); + __disable_irq(); - FLASH->ERASE = addr | ((uint32_t)1 << FLASH_ERASE_REQ_Pos); - while ((FLASH->STAT & FLASH_STAT_ERASE_GOING_Msk) == 0); - while ((FLASH->STAT & FLASH_STAT_ERASE_GOING_Msk) == 1); + IAP_Flash_Write(addr, (uint32_t)buff, count / 4); - FLASH->ERASE = 0; + IAP_Cache_Reset(); -// switchTo40M(); + __enable_irq(); } /****************************************************************************************************************************************** -* ��������: FLASH_Write() -* ����˵��: Ƭ��Flashд�� -* �� ��: uint32_t addr д���ַ -* uint32_t buff[] Ҫд������� -* uint32_t size Ҫд�����ݵĸ�������Ϊ��λ -* �� ��: �� -* ע������: �� +* 函数名称: Flash_Param_at_xMHz() +* 功能说明: 将Flash参数设置成xMHz主频下运行时所需的参数 +* 输 入: uint32_t x 可取值 +* 输 出: 无 +* 注意事项: 无 ******************************************************************************************************************************************/ -void FLASH_Write(uint32_t addr, uint32_t buff[], uint32_t size) +void Flash_Param_at_xMHz(uint32_t x) { - uint32_t i, j; - - switchTo80M(); - - FLASH->CACHE |= (1 << FLASH_CACHE_PROG_Pos); - - for (i = 0; i < size / 4; i++) - { - FLASH->ADDR = addr + i * 4 * 4; - - for (j = 0; j < 4; j++) - FLASH->DATA = buff[i * 4 + j]; - while ((FLASH->STAT & FLASH_STAT_FIFO_EMPTY_Msk) == 0) __NOP(); - } - if ((size % 4) != 0) + __disable_irq(); + switch (x) { - FLASH->ADDR = addr + i * 4 * 4; + case 30: + IAP_Flash_Param(0x489, 0xabf41f25); + break; - for (j = 0; j < size % 4; j++) - FLASH->DATA = buff[i * 4 + j]; - while ((FLASH->STAT & FLASH_STAT_FIFO_EMPTY_Msk) == 0) __NOP(); - } - while (FLASH->STAT & FLASH_STAT_PROG_GOING_Msk); + case 40: + IAP_Flash_Param(0x489, 0xabf42929); + break; - FLASH->CACHE |= (1 << FLASH_CACHE_CLEAR_Pos); - FLASH->CACHE = 0; + case 80: + IAP_Flash_Param(0x489, 0xabf8524d); + break; -// switchTo40M(); + case 120: + default: + IAP_Flash_Param(0x48a, 0xabfc7a6e); + break; + } + __enable_irq(); } diff --git a/bsp/swm320-lq100/Libraries/SWM320_StdPeriph_Driver/SWM320_flash.h b/bsp/swm320-lq100/Libraries/SWM320_StdPeriph_Driver/SWM320_flash.h index 5a4bfbb89f..0352eeef82 100644 --- a/bsp/swm320-lq100/Libraries/SWM320_StdPeriph_Driver/SWM320_flash.h +++ b/bsp/swm320-lq100/Libraries/SWM320_StdPeriph_Driver/SWM320_flash.h @@ -1,9 +1,19 @@ #ifndef __SWM320_FLASH_H__ #define __SWM320_FLASH_H__ - void FLASH_Erase(uint32_t addr); -void FLASH_Write(uint32_t addr, uint32_t buff[], uint32_t size); +void FLASH_Write(uint32_t addr, uint32_t buff[], uint32_t count); + +void Flash_Param_at_xMHz(uint32_t x); + +typedef void (*IAP_Cache_Reset_t)(void); +typedef void (*IAP_Flash_Param_t)(uint32_t cfg0, uint32_t cfg1); +typedef void (*IAP_Flash_Erase_t)(uint32_t sector); +typedef void (*IAP_Flash_Write_t)(uint32_t flash_addr, uint32_t ram_addr, uint32_t count); +extern IAP_Cache_Reset_t IAP_Cache_Reset; +extern IAP_Flash_Param_t IAP_Flash_Param; +extern IAP_Flash_Erase_t IAP_Flash_Erase; +extern IAP_Flash_Write_t IAP_Flash_Write; #endif //__SWM320_FLASH_H__ diff --git a/bsp/swm320-lq100/Libraries/SWM320_StdPeriph_Driver/SWM320_gpio.c b/bsp/swm320-lq100/Libraries/SWM320_StdPeriph_Driver/SWM320_gpio.c index dd81e75952..5ec03c48f6 100644 --- a/bsp/swm320-lq100/Libraries/SWM320_StdPeriph_Driver/SWM320_gpio.c +++ b/bsp/swm320-lq100/Libraries/SWM320_StdPeriph_Driver/SWM320_gpio.c @@ -1,10 +1,10 @@ /****************************************************************************************************************************************** -* �ļ�����: SWM320_gpio.c -* ����˵��: SWM320��Ƭ����ͨ������������������� -* ����֧��: http://www.synwit.com.cn/e/tool/gbook/?bid=1 -* ע������: -* �汾����: V1.1.0 2017��10��25�� -* ������¼: +* 文件名称: SWM320_gpio.c +* 功能说明: SWM320单片机的通用输入输出功能驱动库 +* 技术支持: http://www.synwit.com.cn/e/tool/gbook/?bid=1 +* 注意事项: +* 版本日期: V1.1.0 2017年10月25日 +* 升级记录: * * ******************************************************************************************************************************************* @@ -21,17 +21,16 @@ #include "SWM320.h" #include "SWM320_gpio.h" - /****************************************************************************************************************************************** -* ��������: GPIO_Init() -* ����˵��: ���ų�ʼ�����������ŷ����������衢�������衢��©��� -* �� ��: GPIO_TypeDef * GPIOx ָ��GPIO�˿ڣ���Чֵ����GPIOA��GPIOB��GPIOC��GPIOM��GPION��GPIOP -* uint32_t n ָ��GPIO���ţ���Чֵ����PIN0��PIN1��PIN2��... ... PIN22��PIN23 -* uint32_t dir ���ŷ���0 ���� 1 ��� -* uint32_t pull_up �������裬0 �ر����� 1 �������� -* uint32_t pull_down �������裬0 �ر����� 1 �������� -* �� ��: �� -* ע������: �� +* 函数名称: GPIO_Init() +* 功能说明: 引脚初始化，包含引脚方向、上拉电阻、下拉电阻 +* 输 入: GPIO_TypeDef * GPIOx 指定GPIO端口，有效值包括GPIOA、GPIOB、GPIOC、GPIOM、GPION、GPIOP +* uint32_t n 指定GPIO引脚，有效值包括PIN0、PIN1、PIN2、... ... PIN22、PIN23 +* uint32_t dir 引脚方向，0 输入 1 输出 +* uint32_t pull_up 上拉电阻，0 关闭上拉 1 开启上拉 +* uint32_t pull_down 下拉电阻，0 关闭下拉 1 开启下拉 +* 输 出: 无 +* 注意事项: GPIOA、GPIOC、GPIOM、GPIOP只有上拉，GPIOB、GPION只有下拉（PN0、PN1、PN2三个引脚有上拉没下拉） ******************************************************************************************************************************************/ void GPIO_Init(GPIO_TypeDef *GPIOx, uint32_t n, uint32_t dir, uint32_t pull_up, uint32_t pull_down) { @@ -40,7 +39,7 @@ void GPIO_Init(GPIO_TypeDef *GPIOx, uint32_t n, uint32_t dir, uint32_t pull_up, case ((uint32_t)GPIOA): SYS->CLKEN |= (0x01 << SYS_CLKEN_GPIOA_Pos); - PORT_Init(PORTA, n, 0, 1); //PORTA.PINn��������ΪGPIO���ܣ��������뿪�� + PORT_Init(PORTA, n, 0, 1); //PORTA.PINn引脚配置为GPIO功能，数字输入开启 if (dir == 1) { GPIOA->DIR |= (0x01 << n); @@ -59,7 +58,7 @@ void GPIO_Init(GPIO_TypeDef *GPIOx, uint32_t n, uint32_t dir, uint32_t pull_up, case ((uint32_t)GPIOB): SYS->CLKEN |= (0x01 << SYS_CLKEN_GPIOB_Pos); - PORT_Init(PORTB, n, 0, 1); //PORTB.PINn��������ΪGPIO���ܣ��������뿪�� + PORT_Init(PORTB, n, 0, 1); //PORTB.PINn引脚配置为GPIO功能，数字输入开启 if (dir == 1) { GPIOB->DIR |= (0x01 << n); @@ -78,7 +77,7 @@ void GPIO_Init(GPIO_TypeDef *GPIOx, uint32_t n, uint32_t dir, uint32_t pull_up, case ((uint32_t)GPIOC): SYS->CLKEN |= (0x01 << SYS_CLKEN_GPIOC_Pos); - PORT_Init(PORTC, n, 0, 1); //PORTC.PINn��������ΪGPIO���ܣ��������뿪�� + PORT_Init(PORTC, n, 0, 1); //PORTC.PINn引脚配置为GPIO功能，数字输入开启 if (dir == 1) { GPIOC->DIR |= (0x01 << n); @@ -97,7 +96,7 @@ void GPIO_Init(GPIO_TypeDef *GPIOx, uint32_t n, uint32_t dir, uint32_t pull_up, case ((uint32_t)GPIOM): SYS->CLKEN |= (0x01 << SYS_CLKEN_GPIOM_Pos); - PORT_Init(PORTM, n, 0, 1); //PORTM.PINn��������ΪGPIO���ܣ��������뿪�� + PORT_Init(PORTM, n, 0, 1); //PORTM.PINn引脚配置为GPIO功能，数字输入开启 if (dir == 1) { GPIOM->DIR |= (0x01 << n); @@ -116,7 +115,7 @@ void GPIO_Init(GPIO_TypeDef *GPIOx, uint32_t n, uint32_t dir, uint32_t pull_up, case ((uint32_t)GPION): SYS->CLKEN |= (0x01 << SYS_CLKEN_GPION_Pos); - PORT_Init(PORTN, n, 0, 1); //PORTN.PINn��������ΪGPIO���ܣ��������뿪�� + PORT_Init(PORTN, n, 0, 1); //PORTN.PINn引脚配置为GPIO功能，数字输入开启 if (dir == 1) { GPION->DIR |= (0x01 << n); @@ -135,7 +134,7 @@ void GPIO_Init(GPIO_TypeDef *GPIOx, uint32_t n, uint32_t dir, uint32_t pull_up, case ((uint32_t)GPIOP): SYS->CLKEN |= (0x01 << SYS_CLKEN_GPIOP_Pos); - PORT_Init(PORTP, n, 0, 1); //PORTP.PINn��������ΪGPIO���ܣ��������뿪�� + PORT_Init(PORTP, n, 0, 1); //PORTP.PINn引脚配置为GPIO功能，数字输入开启 if (dir == 1) { GPIOP->DIR |= (0x01 << n); @@ -154,12 +153,12 @@ void GPIO_Init(GPIO_TypeDef *GPIOx, uint32_t n, uint32_t dir, uint32_t pull_up, } /****************************************************************************************************************************************** -* ��������: GPIO_SetBit() -* ����˵��: ������ָ�������ŵ�ƽ�ø� -* �� ��: GPIO_TypeDef * GPIOx ָ��GPIO�˿ڣ���Чֵ����GPIOA��GPIOB��GPIOC��GPIOM��GPION��GPIOP -* uint32_t n ָ��GPIO���ţ���Чֵ����PIN0��PIN1��PIN2��... ... PIN22��PIN23 -* �� ��: �� -* ע������: �� +* 函数名称: GPIO_SetBit() +* 功能说明: 将参数指定的引脚电平置高 +* 输 入: GPIO_TypeDef * GPIOx 指定GPIO端口，有效值包括GPIOA、GPIOB、GPIOC、GPIOM、GPION、GPIOP +* uint32_t n 指定GPIO引脚，有效值包括PIN0、PIN1、PIN2、... ... PIN22、PIN23 +* 输 出: 无 +* 注意事项: 无 ******************************************************************************************************************************************/ void GPIO_SetBit(GPIO_TypeDef *GPIOx, uint32_t n) { @@ -167,12 +166,12 @@ void GPIO_SetBit(GPIO_TypeDef *GPIOx, uint32_t n) } /****************************************************************************************************************************************** -* ��������: GPIO_ClrBit() -* ����˵��: ������ָ�������ŵ�ƽ�õ� -* �� ��: GPIO_TypeDef * GPIOx ָ��GPIO�˿ڣ���Чֵ����GPIOA��GPIOB��GPIOC��GPIOM��GPION��GPIOP -* uint32_t n ָ��GPIO���ţ���Чֵ����PIN0��PIN1��PIN2��... ... PIN22��PIN23 -* �� ��: �� -* ע������: �� +* 函数名称: GPIO_ClrBit() +* 功能说明: 将参数指定的引脚电平置低 +* 输 入: GPIO_TypeDef * GPIOx 指定GPIO端口，有效值包括GPIOA、GPIOB、GPIOC、GPIOM、GPION、GPIOP +* uint32_t n 指定GPIO引脚，有效值包括PIN0、PIN1、PIN2、... ... PIN22、PIN23 +* 输 出: 无 +* 注意事项: 无 ******************************************************************************************************************************************/ void GPIO_ClrBit(GPIO_TypeDef *GPIOx, uint32_t n) { @@ -180,12 +179,12 @@ void GPIO_ClrBit(GPIO_TypeDef *GPIOx, uint32_t n) } /****************************************************************************************************************************************** -* ��������: GPIO_InvBit() -* ����˵��: ������ָ�������ŵ�ƽ��ת -* �� ��: GPIO_TypeDef * GPIOx ָ��GPIO�˿ڣ���Чֵ����GPIOA��GPIOB��GPIOC��GPIOM��GPION��GPIOP -* uint32_t n ָ��GPIO���ţ���Чֵ����PIN0��PIN1��PIN2��... ... PIN22��PIN23 -* �� ��: �� -* ע������: �� +* 函数名称: GPIO_InvBit() +* 功能说明: 将参数指定的引脚电平反转 +* 输 入: GPIO_TypeDef * GPIOx 指定GPIO端口，有效值包括GPIOA、GPIOB、GPIOC、GPIOM、GPION、GPIOP +* uint32_t n 指定GPIO引脚，有效值包括PIN0、PIN1、PIN2、... ... PIN22、PIN23 +* 输 出: 无 +* 注意事项: 无 ******************************************************************************************************************************************/ void GPIO_InvBit(GPIO_TypeDef *GPIOx, uint32_t n) { @@ -193,12 +192,12 @@ void GPIO_InvBit(GPIO_TypeDef *GPIOx, uint32_t n) } /****************************************************************************************************************************************** -* ��������: GPIO_GetBit() -* ����˵��: ��ȡ����ָ�������ŵĵ�ƽ״̬ -* �� ��: GPIO_TypeDef * GPIOx ָ��GPIO�˿ڣ���Чֵ����GPIOA��GPIOB��GPIOC��GPIOM��GPION��GPIOP -* uint32_t n ָ��GPIO���ţ���Чֵ����PIN0��PIN1��PIN2��... ... PIN22��PIN23 -* �� ��: ����ָ�������ŵĵ�ƽ״̬ 0 �͵�ƽ 1 �ߵ�ƽ -* ע������: �� +* 函数名称: GPIO_GetBit() +* 功能说明: 读取参数指定的引脚的电平状态 +* 输 入: GPIO_TypeDef * GPIOx 指定GPIO端口，有效值包括GPIOA、GPIOB、GPIOC、GPIOM、GPION、GPIOP +* uint32_t n 指定GPIO引脚，有效值包括PIN0、PIN1、PIN2、... ... PIN22、PIN23 +* 输 出: 参数指定的引脚的电平状态 0 低电平 1 高电平 +* 注意事项: 无 ******************************************************************************************************************************************/ uint32_t GPIO_GetBit(GPIO_TypeDef *GPIOx, uint32_t n) { @@ -206,13 +205,13 @@ uint32_t GPIO_GetBit(GPIO_TypeDef *GPIOx, uint32_t n) } /****************************************************************************************************************************************** -* ��������: GPIO_SetBits() -* ����˵��: ������ָ���Ĵ�n��ʼ��wλ�������ŵĵ�ƽ�ø� -* �� ��: GPIO_TypeDef * GPIOx ָ��GPIO�˿ڣ���Чֵ����GPIOA��GPIOB��GPIOC��GPIOM��GPION��GPIOP -* uint32_t n ָ��GPIO���ţ���Чֵ����PIN0��PIN1��PIN2��... ... PIN22��PIN23 -* uint32_t w ָ��Ҫ�����ŵ�ƽ�øߵ����ŵĸ��� -* �� ��: �� -* ע������: �� +* 函数名称: GPIO_SetBits() +* 功能说明: 将参数指定的从n开始的w位连续引脚的电平置高 +* 输 入: GPIO_TypeDef * GPIOx 指定GPIO端口，有效值包括GPIOA、GPIOB、GPIOC、GPIOM、GPION、GPIOP +* uint32_t n 指定GPIO引脚，有效值包括PIN0、PIN1、PIN2、... ... PIN22、PIN23 +* uint32_t w 指定要将引脚电平置高的引脚的个数 +* 输 出: 无 +* 注意事项: 无 ******************************************************************************************************************************************/ void GPIO_SetBits(GPIO_TypeDef *GPIOx, uint32_t n, uint32_t w) { @@ -224,13 +223,13 @@ void GPIO_SetBits(GPIO_TypeDef *GPIOx, uint32_t n, uint32_t w) } /****************************************************************************************************************************************** -* ��������: GPIO_ClrBits() -* ����˵��: ������ָ���Ĵ�n��ʼ��wλ�������ŵĵ�ƽ�õ� -* �� ��: GPIO_TypeDef * GPIOx ָ��GPIO�˿ڣ���Чֵ����GPIOA��GPIOB��GPIOC��GPIOM��GPION��GPIOP -* uint32_t n ָ��GPIO���ţ���Чֵ����PIN0��PIN1��PIN2��... ... PIN22��PIN23 -* uint32_t w ָ��Ҫ�����ŵ�ƽ�õ͵����ŵĸ��� -* �� ��: �� -* ע������: �� +* 函数名称: GPIO_ClrBits() +* 功能说明: 将参数指定的从n开始的w位连续引脚的电平置低 +* 输 入: GPIO_TypeDef * GPIOx 指定GPIO端口，有效值包括GPIOA、GPIOB、GPIOC、GPIOM、GPION、GPIOP +* uint32_t n 指定GPIO引脚，有效值包括PIN0、PIN1、PIN2、... ... PIN22、PIN23 +* uint32_t w 指定要将引脚电平置低的引脚的个数 +* 输 出: 无 +* 注意事项: 无 ******************************************************************************************************************************************/ void GPIO_ClrBits(GPIO_TypeDef *GPIOx, uint32_t n, uint32_t w) { @@ -242,13 +241,13 @@ void GPIO_ClrBits(GPIO_TypeDef *GPIOx, uint32_t n, uint32_t w) } /****************************************************************************************************************************************** -* ��������: GPIO_InvBits() -* ����˵��: ������ָ���Ĵ�n��ʼ��wλ�������ŵĵ�ƽ��ת -* �� ��: GPIO_TypeDef * GPIOx ָ��GPIO�˿ڣ���Чֵ����GPIOA��GPIOB��GPIOC��GPIOM��GPION��GPIOP -* uint32_t n ָ��GPIO���ţ���Чֵ����PIN0��PIN1��PIN2��... ... PIN22��PIN23 -* uint32_t w ָ��Ҫ�����ŵ�ƽ��ת�����ŵĸ��� -* �� ��: �� -* ע������: �� +* 函数名称: GPIO_InvBits() +* 功能说明: 将参数指定的从n开始的w位连续引脚的电平反转 +* 输 入: GPIO_TypeDef * GPIOx 指定GPIO端口，有效值包括GPIOA、GPIOB、GPIOC、GPIOM、GPION、GPIOP +* uint32_t n 指定GPIO引脚，有效值包括PIN0、PIN1、PIN2、... ... PIN22、PIN23 +* uint32_t w 指定要将引脚电平反转的引脚的个数 +* 输 出: 无 +* 注意事项: 无 ******************************************************************************************************************************************/ void GPIO_InvBits(GPIO_TypeDef *GPIOx, uint32_t n, uint32_t w) { @@ -260,14 +259,14 @@ void GPIO_InvBits(GPIO_TypeDef *GPIOx, uint32_t n, uint32_t w) } /****************************************************************************************************************************************** -* ��������: GPIO_GetBits() -* ����˵��: ��ȡ����ָ���Ĵ�n��ʼ��wλ�������ŵĵ�ƽ״̬ -* �� ��: GPIO_TypeDef * GPIOx ָ��GPIO�˿ڣ���Чֵ����GPIOA��GPIOB��GPIOC��GPIOM��GPION��GPIOP -* uint32_t n ָ��GPIO���ţ���Чֵ����PIN0��PIN1��PIN2��... ... PIN22��PIN23 -* uint32_t w ָ��Ҫ�����ŵ�ƽ�øߵ����ŵĸ��� -* �� ��: ����ָ���Ĵ�n��ʼ��wλ�������ŵĵ�ƽ״̬ 0 �͵�ƽ 1 �ߵ�ƽ -* ����ֵ�ĵ�0λ��ʾ����n�ĵ�ƽ״̬������ֵ�ĵ�1λ��ʾ����n+1�ĵ�ƽ״̬... ...����ֵ�ĵ�wλ��ʾ����n+w�ĵ�ƽ״̬ -* ע������: �� +* 函数名称: GPIO_GetBits() +* 功能说明: 读取参数指定的从n开始的w位连续引脚的电平状态 +* 输 入: GPIO_TypeDef * GPIOx 指定GPIO端口，有效值包括GPIOA、GPIOB、GPIOC、GPIOM、GPION、GPIOP +* uint32_t n 指定GPIO引脚，有效值包括PIN0、PIN1、PIN2、... ... PIN22、PIN23 +* uint32_t w 指定要将引脚电平置高的引脚的个数 +* 输 出: 参数指定的从n开始的w位连续引脚的电平状态 0 低电平 1 高电平 +* 返回值的第0位表示引脚n的电平状态、返回值的第1位表示引脚n+1的电平状态... ...返回值的第w位表示引脚n+w的电平状态 +* 注意事项: 无 ******************************************************************************************************************************************/ uint32_t GPIO_GetBits(GPIO_TypeDef *GPIOx, uint32_t n, uint32_t w) { @@ -277,3 +276,102 @@ uint32_t GPIO_GetBits(GPIO_TypeDef *GPIOx, uint32_t n, uint32_t w) return ((GPIOx->DATA >> n) & bits); } + +/****************************************************************************************************************************************** +* 函数名称: GPIO_AtomicSetBit() +* 功能说明: 将参数指定的引脚电平置高，确保引脚”读-改-写“操作的原子性（不被中断ISR打断） +* 输 入: GPIO_TypeDef * GPIOx 指定GPIO端口，有效值包括GPIOA、GPIOB、GPIOC、GPIOD +* uint32_t n 指定GPIO引脚，有效值包括PIN0、PIN1、PIN2、... ... PIN14、PIN15 +* 输 出: 无 +* 注意事项: 当GPIOx的16个引脚中，有些在主循环中操作，有些在中断ISR中操作时，GPIOx的引脚必须都用GPIO_Atomic类型函数操作 +******************************************************************************************************************************************/ +void GPIO_AtomicSetBit(GPIO_TypeDef *GPIOx, uint32_t n) +{ + *((volatile uint32_t *)(0x42000000 + ((uint32_t)&GPIOx->DATA - 0x40000000) * 32 + n * 4)) = 1; +} + +/****************************************************************************************************************************************** +* 函数名称: GPIO_AtomicClrBit() +* 功能说明: 将参数指定的引脚电平置低，确保引脚”读-改-写“操作的原子性（不被中断ISR打断） +* 输 入: GPIO_TypeDef * GPIOx 指定GPIO端口，有效值包括GPIOA、GPIOB、GPIOC、GPIOD +* uint32_t n 指定GPIO引脚，有效值包括PIN0、PIN1、PIN2、... ... PIN14、PIN15 +* 输 出: 无 +* 注意事项: 当GPIOx的16个引脚中，有些在主循环中操作，有些在中断ISR中操作时，GPIOx的引脚必须都用GPIO_Atomic类型函数操作 +******************************************************************************************************************************************/ +void GPIO_AtomicClrBit(GPIO_TypeDef *GPIOx, uint32_t n) +{ + *((volatile uint32_t *)(0x42000000 + ((uint32_t)&GPIOx->DATA - 0x40000000) * 32 + n * 4)) = 0; +} + +/****************************************************************************************************************************************** +* 函数名称: GPIO_AtomicInvBit() +* 功能说明: 将参数指定的引脚电平反转，确保引脚”读-改-写“操作的原子性（不被中断ISR打断） +* 输 入: GPIO_TypeDef * GPIOx 指定GPIO端口，有效值包括GPIOA、GPIOB、GPIOC、GPIOD +* uint32_t n 指定GPIO引脚，有效值包括PIN0、PIN1、PIN2、... ... PIN14、PIN15 +* 输 出: 无 +* 注意事项: 当GPIOx的16个引脚中，有些在主循环中操作，有些在中断ISR中操作时，GPIOx的引脚必须都用GPIO_Atomic类型函数操作 +******************************************************************************************************************************************/ +void GPIO_AtomicInvBit(GPIO_TypeDef *GPIOx, uint32_t n) +{ + *((volatile uint32_t *)(0x42000000 + ((uint32_t)&GPIOx->DATA - 0x40000000) * 32 + n * 4)) = 1 - *((volatile uint32_t *)(0x42000000 + ((uint32_t)&GPIOx->DATA - 0x40000000) * 32 + n * 4)); +} + +/****************************************************************************************************************************************** +* 函数名称: GPIO_AtomicSetBits() +* 功能说明: 将参数指定的从n开始的w位连续引脚的电平置高，确保引脚”读-改-写“操作的原子性（不被中断ISR打断） +* 输 入: GPIO_TypeDef * GPIOx 指定GPIO端口，有效值包括GPIOA、GPIOB、GPIOC、GPIOD +* uint32_t n 指定GPIO引脚，有效值包括PIN0、PIN1、PIN2、... ... PIN14、PIN15 +* uint32_t w 指定要将引脚电平置高的引脚的个数 +* 输 出: 无 +* 注意事项: 当GPIOx的16个引脚中，有些在主循环中操作，有些在中断ISR中操作时，GPIOx的引脚必须都用GPIO_Atomic类型函数操作 +******************************************************************************************************************************************/ +void GPIO_AtomicSetBits(GPIO_TypeDef *GPIOx, uint32_t n, uint32_t w) +{ + uint32_t bits; + + bits = 0xFFFFFF >> (24 - w); + + __disable_irq(); + GPIOx->DATA |= (bits << n); + __enable_irq(); +} + +/****************************************************************************************************************************************** +* 函数名称: GPIO_AtomicClrBits() +* 功能说明: 将参数指定的从n开始的w位连续引脚的电平置低，确保引脚”读-改-写“操作的原子性（不被中断ISR打断） +* 输 入: GPIO_TypeDef * GPIOx 指定GPIO端口，有效值包括GPIOA、GPIOB、GPIOC、GPIOD +* uint32_t n 指定GPIO引脚，有效值包括PIN0、PIN1、PIN2、... ... PIN14、PIN15 +* uint32_t w 指定要将引脚电平置低的引脚的个数 +* 输 出: 无 +* 注意事项: 当GPIOx的16个引脚中，有些在主循环中操作，有些在中断ISR中操作时，GPIOx的引脚必须都用GPIO_Atomic类型函数操作 +******************************************************************************************************************************************/ +void GPIO_AtomicClrBits(GPIO_TypeDef *GPIOx, uint32_t n, uint32_t w) +{ + uint32_t bits; + + bits = 0xFFFFFF >> (24 - w); + + __disable_irq(); + GPIOx->DATA &= ~(bits << n); + __enable_irq(); +} + +/****************************************************************************************************************************************** +* 函数名称: GPIO_AtomicInvBits() +* 功能说明: 将参数指定的从n开始的w位连续引脚的电平反转，确保引脚”读-改-写“操作的原子性（不被中断ISR打断） +* 输 入: GPIO_TypeDef * GPIOx 指定GPIO端口，有效值包括GPIOA、GPIOB、GPIOC、GPIOD +* uint32_t n 指定GPIO引脚，有效值包括PIN0、PIN1、PIN2、... ... PIN14、PIN15 +* uint32_t w 指定要将引脚电平反转的引脚的个数 +* 输 出: 无 +* 注意事项: 当GPIOx的16个引脚中，有些在主循环中操作，有些在中断ISR中操作时，GPIOx的引脚必须都用GPIO_Atomic类型函数操作 +******************************************************************************************************************************************/ +void GPIO_AtomicInvBits(GPIO_TypeDef *GPIOx, uint32_t n, uint32_t w) +{ + uint32_t bits; + + bits = 0xFFFFFF >> (24 - w); + + __disable_irq(); + GPIOx->DATA ^= (bits << n); + __enable_irq(); +} diff --git a/bsp/swm320-lq100/Libraries/SWM320_StdPeriph_Driver/SWM320_gpio.h b/bsp/swm320-lq100/Libraries/SWM320_StdPeriph_Driver/SWM320_gpio.h index a0f84999bd..056f17b07b 100644 --- a/bsp/swm320-lq100/Libraries/SWM320_StdPeriph_Driver/SWM320_gpio.h +++ b/bsp/swm320-lq100/Libraries/SWM320_StdPeriph_Driver/SWM320_gpio.h @@ -1,17 +1,22 @@ #ifndef __SWM320_GPIO_H__ #define __SWM320_GPIO_H__ +void GPIO_Init(GPIO_TypeDef *GPIOx, uint32_t n, uint32_t dir, uint32_t pull_up, uint32_t pull_down); //引脚初始化，包含引脚方向、上拉电阻、下拉电阻 -void GPIO_Init(GPIO_TypeDef *GPIOx, uint32_t n, uint32_t dir, uint32_t pull_up, uint32_t pull_down); //���ų�ʼ�����������ŷ����������衢�������� - -void GPIO_SetBit(GPIO_TypeDef *GPIOx, uint32_t n); //������ָ�������ŵ�ƽ�ø� -void GPIO_ClrBit(GPIO_TypeDef *GPIOx, uint32_t n); //������ָ�������ŵ�ƽ�õ� -void GPIO_InvBit(GPIO_TypeDef *GPIOx, uint32_t n); //������ָ�������ŵ�ƽ��ת -uint32_t GPIO_GetBit(GPIO_TypeDef *GPIOx, uint32_t n); //��ȡ����ָ�������ŵĵ�ƽ״̬ -void GPIO_SetBits(GPIO_TypeDef *GPIOx, uint32_t n, uint32_t w); //������ָ���Ĵ�n��ʼ��wλ�������ŵĵ�ƽ�ø� -void GPIO_ClrBits(GPIO_TypeDef *GPIOx, uint32_t n, uint32_t w); //������ָ���Ĵ�n��ʼ��wλ�������ŵĵ�ƽ�õ� -void GPIO_InvBits(GPIO_TypeDef *GPIOx, uint32_t n, uint32_t w); //������ָ���Ĵ�n��ʼ��wλ�������ŵĵ�ƽ��ת -uint32_t GPIO_GetBits(GPIO_TypeDef *GPIOx, uint32_t n, uint32_t w); //��ȡ����ָ���Ĵ�n��ʼ��wλ�������ŵĵ�ƽ״̬ +void GPIO_SetBit(GPIO_TypeDef *GPIOx, uint32_t n); //将参数指定的引脚电平置高 +void GPIO_ClrBit(GPIO_TypeDef *GPIOx, uint32_t n); //将参数指定的引脚电平置低 +void GPIO_InvBit(GPIO_TypeDef *GPIOx, uint32_t n); //将参数指定的引脚电平反转 +uint32_t GPIO_GetBit(GPIO_TypeDef *GPIOx, uint32_t n); //读取参数指定的引脚的电平状态 +void GPIO_SetBits(GPIO_TypeDef *GPIOx, uint32_t n, uint32_t w); //将参数指定的从n开始的w位连续引脚的电平置高 +void GPIO_ClrBits(GPIO_TypeDef *GPIOx, uint32_t n, uint32_t w); //将参数指定的从n开始的w位连续引脚的电平置低 +void GPIO_InvBits(GPIO_TypeDef *GPIOx, uint32_t n, uint32_t w); //将参数指定的从n开始的w位连续引脚的电平反转 +uint32_t GPIO_GetBits(GPIO_TypeDef *GPIOx, uint32_t n, uint32_t w); //读取参数指定的从n开始的w位连续引脚的电平状态 +void GPIO_AtomicSetBit(GPIO_TypeDef *GPIOx, uint32_t n); +void GPIO_AtomicClrBit(GPIO_TypeDef *GPIOx, uint32_t n); +void GPIO_AtomicInvBit(GPIO_TypeDef *GPIOx, uint32_t n); +void GPIO_AtomicSetBits(GPIO_TypeDef *GPIOx, uint32_t n, uint32_t w); +void GPIO_AtomicClrBits(GPIO_TypeDef *GPIOx, uint32_t n, uint32_t w); +void GPIO_AtomicInvBits(GPIO_TypeDef *GPIOx, uint32_t n, uint32_t w); #endif //__SWM320_GPIO_H__ diff --git a/bsp/swm320-lq100/Libraries/SWM320_StdPeriph_Driver/SWM320_i2c.c b/bsp/swm320-lq100/Libraries/SWM320_StdPeriph_Driver/SWM320_i2c.c index 34de5c5610..c69378ca1a 100644 --- a/bsp/swm320-lq100/Libraries/SWM320_StdPeriph_Driver/SWM320_i2c.c +++ b/bsp/swm320-lq100/Libraries/SWM320_StdPeriph_Driver/SWM320_i2c.c @@ -1,10 +1,10 @@ /****************************************************************************************************************************************** -* �ļ�����: SWM320_i2c.c -* ����˵��: SWM320��Ƭ����I2C���нӿڹ��������� -* ����֧��: http://www.synwit.com.cn/e/tool/gbook/?bid=1 -* ע������: -* �汾����: V1.1.0 2017��10��25�� -* ������¼: +* 文件名称: SWM320_i2c.c +* 功能说明: SWM320单片机的I2C串行接口功能驱动库 +* 技术支持: http://www.synwit.com.cn/e/tool/gbook/?bid=1 +* 注意事项: +* 版本日期: V1.1.0 2017年10月25日 +* 升级记录: * * ******************************************************************************************************************************************* @@ -22,12 +22,12 @@ #include "SWM320_i2c.h" /****************************************************************************************************************************************** -* ��������: I2C_Init() -* ����˵��: I2C��ʼ�� -* �� ��: I2C_TypeDef * I2Cx ָ��Ҫ�����õ�I2C����Чֵ����I2C0��I2C1 -* I2C_InitStructure * initStruct ����I2C����趨ֵ�Ľṹ�� -* �� ��: �� -* ע������: ģ��ֻ�ܹ���������ģʽ +* 函数名称: I2C_Init() +* 功能说明: I2C初始化 +* 输 入: I2C_TypeDef * I2Cx 指定要被设置的I2C，有效值包括I2C0、I2C1 +* I2C_InitStructure * initStruct 包含I2C相关设定值的结构体 +* 输 出: 无 +* 注意事项: 模块只能工作于主机模式 ******************************************************************************************************************************************/ void I2C_Init(I2C_TypeDef *I2Cx, I2C_InitStructure *initStruct) { @@ -42,13 +42,13 @@ void I2C_Init(I2C_TypeDef *I2Cx, I2C_InitStructure *initStruct) break; } - I2C_Close(I2Cx); //һЩ�ؼ��Ĵ���ֻ����I2C�ر�ʱ���� + I2C_Close(I2Cx); //一些关键寄存器只能在I2C关闭时设置 if (initStruct->Master == 1) { I2Cx->CLKDIV = SystemCoreClock / 5 / initStruct->MstClk; - I2Cx->MSTCMD = (I2Cx->MSTCMD & (~I2C_MSTCMD_IF_Msk)) | (1 << I2C_MSTCMD_IF_Pos); //ʹ���ж�֮ǰ������жϱ�־ + I2Cx->MSTCMD = (I2Cx->MSTCMD & (~I2C_MSTCMD_IF_Msk)) | (1 << I2C_MSTCMD_IF_Pos); //使能中断之前先清除中断标志 I2Cx->CTRL &= ~I2C_CTRL_MSTIE_Msk; I2Cx->CTRL |= (initStruct->MstIEn << I2C_CTRL_MSTIE_Pos); @@ -86,21 +86,21 @@ void I2C_Init(I2C_TypeDef *I2Cx, I2C_InitStructure *initStruct) (initStruct->Addr7b << I2C_SLVCR_ADDR7b_Pos) | (initStruct->SlvAddr << I2C_SLVCR_ADDR_Pos); - I2Cx->SLVIF = I2C_SLVIF_RXEND_Msk | I2C_SLVIF_TXEND_Msk | I2C_SLVIF_STADET_Msk | I2C_SLVIF_STODET_Msk; //���жϱ�־ + I2Cx->SLVIF = I2C_SLVIF_RXEND_Msk | I2C_SLVIF_TXEND_Msk | I2C_SLVIF_STADET_Msk | I2C_SLVIF_STODET_Msk; //清中断标志 I2Cx->SLVCR &= ~(I2C_SLVCR_IM_RXEND_Msk | I2C_SLVCR_IM_TXEND_Msk | I2C_SLVCR_IM_STADET_Msk | I2C_SLVCR_IM_STODET_Msk | I2C_SLVCR_IM_RDREQ_Msk | I2C_SLVCR_IM_WRREQ_Msk); - I2Cx->SLVCR |= ((initStruct->SlvRxEndIEn ? 0 : 1) << I2C_SLVCR_IM_RXEND_Pos) | - ((initStruct->SlvTxEndIEn ? 0 : 1) << I2C_SLVCR_IM_TXEND_Pos) | + I2Cx->SLVCR |= ((initStruct->SlvRxEndIEn ? 0 : 1) << I2C_SLVCR_IM_RXEND_Pos) | + ((initStruct->SlvTxEndIEn ? 0 : 1) << I2C_SLVCR_IM_TXEND_Pos) | ((initStruct->SlvSTADetIEn ? 0 : 1) << I2C_SLVCR_IM_STADET_Pos) | ((initStruct->SlvSTODetIEn ? 0 : 1) << I2C_SLVCR_IM_STODET_Pos) | - ((initStruct->SlvRdReqIEn ? 0 : 1) << I2C_SLVCR_IM_RDREQ_Pos) | - ((initStruct->SlvWrReqIEn ? 0 : 1) << I2C_SLVCR_IM_WRREQ_Pos); + ((initStruct->SlvRdReqIEn ? 0 : 1) << I2C_SLVCR_IM_RDREQ_Pos) | + ((initStruct->SlvWrReqIEn ? 0 : 1) << I2C_SLVCR_IM_WRREQ_Pos); switch ((uint32_t)I2Cx) { case ((uint32_t)I2C0): if (initStruct->SlvRxEndIEn | initStruct->SlvTxEndIEn | initStruct->SlvSTADetIEn | - initStruct->SlvSTODetIEn | initStruct->SlvRdReqIEn | initStruct->SlvWrReqIEn) + initStruct->SlvSTODetIEn | initStruct->SlvRdReqIEn | initStruct->SlvWrReqIEn) { NVIC_EnableIRQ(I2C0_IRQn); } @@ -112,7 +112,7 @@ void I2C_Init(I2C_TypeDef *I2Cx, I2C_InitStructure *initStruct) case ((uint32_t)I2C1): if (initStruct->SlvRxEndIEn | initStruct->SlvTxEndIEn | initStruct->SlvSTADetIEn | - initStruct->SlvSTODetIEn | initStruct->SlvRdReqIEn | initStruct->SlvWrReqIEn) + initStruct->SlvSTODetIEn | initStruct->SlvRdReqIEn | initStruct->SlvWrReqIEn) { NVIC_EnableIRQ(I2C1_IRQn); } @@ -126,11 +126,11 @@ void I2C_Init(I2C_TypeDef *I2Cx, I2C_InitStructure *initStruct) } /****************************************************************************************************************************************** -* ��������: I2C_Open() -* ����˵��: I2C�������շ� -* �� ��: I2C_TypeDef * I2Cx ָ��Ҫ�����õ�I2C����Чֵ����I2C0��I2C1 -* �� ��: �� -* ע������: �� +* 函数名称: I2C_Open() +* 功能说明: I2C打开，允许收发 +* 输 入: I2C_TypeDef * I2Cx 指定要被设置的I2C，有效值包括I2C0、I2C1 +* 输 出: 无 +* 注意事项: 无 ******************************************************************************************************************************************/ void I2C_Open(I2C_TypeDef *I2Cx) { @@ -138,13 +138,82 @@ void I2C_Open(I2C_TypeDef *I2Cx) } /****************************************************************************************************************************************** -* ��������: I2C_Close() -* ����˵��: I2C�رգ���ֹ�շ� -* �� ��: I2C_TypeDef * I2Cx ָ��Ҫ�����õ�I2C����Чֵ����I2C0��I2C1 -* �� ��: �� -* ע������: �� +* 函数名称: I2C_Close() +* 功能说明: I2C关闭，禁止收发 +* 输 入: I2C_TypeDef * I2Cx 指定要被设置的I2C，有效值包括I2C0、I2C1 +* 输 出: 无 +* 注意事项: 无 ******************************************************************************************************************************************/ void I2C_Close(I2C_TypeDef *I2Cx) { I2Cx->CTRL &= ~I2C_CTRL_EN_Msk; } + +/****************************************************************************************************************************************** +* 函数名称: I2C_Start() +* 功能说明: 产生起始信号并发送设备地址 +* 输 入: I2C_TypeDef * I2Cx 指定要被设置的I2C，有效值包括I2C0、I2C1 +* uint8_t addr 设备地址 +* 输 出: uint8_t 1 接收到ACK 0 接收到NACK +* 注意事项: 无 +******************************************************************************************************************************************/ +uint8_t I2C_Start(I2C_TypeDef *I2Cx, uint8_t addr) +{ + I2Cx->MSTDAT = addr; + I2Cx->MSTCMD = (1 << I2C_MSTCMD_STA_Pos) | + (1 << I2C_MSTCMD_WR_Pos); //发送起始位和从机地址 + while (I2Cx->MSTCMD & I2C_MSTCMD_TIP_Msk) + __NOP(); //等待发送完成 + + return (I2Cx->MSTCMD & I2C_MSTCMD_RXACK_Msk) ? 0 : 1; +} + +/****************************************************************************************************************************************** +* 函数名称: I2C_Stop() +* 功能说明: 产生停止信号 +* 输 入: I2C_TypeDef * I2Cx 指定要被设置的I2C，有效值包括I2C0、I2C1 +* 输 出: 无 +* 注意事项: 无 +******************************************************************************************************************************************/ +void I2C_Stop(I2C_TypeDef *I2Cx) +{ + I2Cx->MSTCMD = (1 << I2C_MSTCMD_STO_Pos); + while (I2Cx->MSTCMD & I2C_MSTCMD_TIP_Msk) + __NOP(); //等待发送完成 +} + +/****************************************************************************************************************************************** +* 函数名称: I2C_Write() +* 功能说明: 写入一个数据 +* 输 入: I2C_TypeDef * I2Cx 指定要被设置的I2C，有效值包括I2C0、I2C1 +* uint8_t data 要写的数据 +* 输 出: uint8_t 1 接收到ACK 0 接收到NACK +* 注意事项: 无 +******************************************************************************************************************************************/ +uint8_t I2C_Write(I2C_TypeDef *I2Cx, uint8_t data) +{ + I2Cx->MSTDAT = data; + I2Cx->MSTCMD = (1 << I2C_MSTCMD_WR_Pos); + while (I2Cx->MSTCMD & I2C_MSTCMD_TIP_Msk) + __NOP(); //等待发送完成 + + return (I2Cx->MSTCMD & I2C_MSTCMD_RXACK_Msk) ? 0 : 1; +} + +/****************************************************************************************************************************************** +* 函数名称: I2C_Read() +* 功能说明: 读取一个数据 +* 输 入: I2C_TypeDef * I2Cx 指定要被设置的I2C，有效值包括I2C0、I2C1 +* uint8_t ack 1 发送ACK 0 发送NACK +* 输 出: uint8_t 读取到的数据 +* 注意事项: 无 +******************************************************************************************************************************************/ +uint8_t I2C_Read(I2C_TypeDef *I2Cx, uint8_t ack) +{ + I2Cx->MSTCMD = (1 << I2C_MSTCMD_RD_Pos) | + ((ack ? 0 : 1) << I2C_MSTCMD_ACK_Pos); + while (I2Cx->MSTCMD & I2C_MSTCMD_TIP_Msk) + __NOP(); //等待接收完成 + + return I2Cx->MSTDAT; +} diff --git a/bsp/swm320-lq100/Libraries/SWM320_StdPeriph_Driver/SWM320_i2c.h b/bsp/swm320-lq100/Libraries/SWM320_StdPeriph_Driver/SWM320_i2c.h index 769f5a2b55..8547328b35 100644 --- a/bsp/swm320-lq100/Libraries/SWM320_StdPeriph_Driver/SWM320_i2c.h +++ b/bsp/swm320-lq100/Libraries/SWM320_StdPeriph_Driver/SWM320_i2c.h @@ -3,25 +3,29 @@ typedef struct { - uint8_t Master; //1 ����ģʽ - uint8_t Addr7b; //1 7λ��ַ 0 10λ��ַ + uint8_t Master; //1 主机模式 + uint8_t Addr7b; //1 7位地址 0 10位地址 - uint32_t MstClk; //��������ʱ��Ƶ�� - uint8_t MstIEn; //����ģʽ�ж�ʹ�� + uint32_t MstClk; //主机传输时钟频率 + uint8_t MstIEn; //主机模式中断使能 - uint16_t SlvAddr; //�ӻ���ַ - uint8_t SlvRxEndIEn; //�ӻ���������ж�ʹ�� - uint8_t SlvTxEndIEn; //�ӻ���������ж�ʹ�� - uint8_t SlvSTADetIEn; //�ӻ�����ʼ�ж�ʹ�� - uint8_t SlvSTODetIEn; //�ӻ�����ֹ�ж�ʹ�� - uint8_t SlvRdReqIEn; //�ӻ����յ��������ж�ʹ�� - uint8_t SlvWrReqIEn; //�ӻ����յ�д�����ж�ʹ�� + uint16_t SlvAddr; //从机地址 + uint8_t SlvRxEndIEn; //从机接收完成中断使能 + uint8_t SlvTxEndIEn; //从机发送完成中断使能 + uint8_t SlvSTADetIEn; //从机检测到起始中断使能 + uint8_t SlvSTODetIEn; //从机检测到终止中断使能 + uint8_t SlvRdReqIEn; //从机接收到读请求中断使能 + uint8_t SlvWrReqIEn; //从机接收到写请求中断使能 } I2C_InitStructure; - void I2C_Init(I2C_TypeDef *I2Cx, I2C_InitStructure *initStruct); void I2C_Open(I2C_TypeDef *I2Cx); void I2C_Close(I2C_TypeDef *I2Cx); +uint8_t I2C_Start(I2C_TypeDef *I2Cx, uint8_t addr); +void I2C_Stop(I2C_TypeDef *I2Cx); +uint8_t I2C_Write(I2C_TypeDef *I2Cx, uint8_t data); +uint8_t I2C_Read(I2C_TypeDef *I2Cx, uint8_t ack); + #endif //__SWM320_I2C_H__ diff --git a/bsp/swm320-lq100/Libraries/SWM320_StdPeriph_Driver/SWM320_lcd.c b/bsp/swm320-lq100/Libraries/SWM320_StdPeriph_Driver/SWM320_lcd.c index 742c5b35dd..af2f2d7c38 100644 --- a/bsp/swm320-lq100/Libraries/SWM320_StdPeriph_Driver/SWM320_lcd.c +++ b/bsp/swm320-lq100/Libraries/SWM320_StdPeriph_Driver/SWM320_lcd.c @@ -1,10 +1,10 @@ /****************************************************************************************************************************************** -* �ļ�����: SWM320_lcd.c -* ����˵��: SWM320��Ƭ����LCD���������� -* ����֧��: http://www.synwit.com.cn/e/tool/gbook/?bid=1 -* ע������: -* �汾����: V1.1.0 2017��10��25�� -* ������¼: +* 文件名称: SWM320_lcd.c +* 功能说明: SWM320单片机的LCD功能驱动库 +* 技术支持: http://www.synwit.com.cn/e/tool/gbook/?bid=1 +* 注意事项: +* 版本日期: V1.1.0 2017年10月25日 +* 升级记录: * * ******************************************************************************************************************************************* @@ -24,12 +24,12 @@ #include <string.h> /****************************************************************************************************************************************** -* ��������: LCD_Init() -* ����˵��: LCD��ʼ�� -* �� ��: LCD_TypeDef * LCDx ָ��Ҫ�����õ�LCD����Чֵ����LCD -* LCD_InitStructure * initStruct ����LCD����趨ֵ�Ľṹ�� -* �� ��: �� -* ע������: �� +* 函数名称: LCD_Init() +* 功能说明: LCD初始化 +* 输 入: LCD_TypeDef * LCDx 指定要被设置的LCD，有效值包括LCD +* LCD_InitStructure * initStruct 包含LCD相关设定值的结构体 +* 输 出: 无 +* 注意事项: 无 ******************************************************************************************************************************************/ void LCD_Init(LCD_TypeDef *LCDx, LCD_InitStructure *initStruct) { @@ -40,56 +40,24 @@ void LCD_Init(LCD_TypeDef *LCDx, LCD_InitStructure *initStruct) break; } - if (initStruct->Interface == LCD_INTERFACE_RGB) - { - LCDx->START = (0 << LCD_START_MPUEN_Pos); - - if (initStruct->Dir == LCD_DIR_LANDSCAPE) - { - LCDx->CR0 = ((initStruct->HnPixel - 1) << LCD_CR0_HPIX_Pos) | - ((initStruct->VnPixel - 1) << LCD_CR0_VPIX_Pos) | - (initStruct->ClkAlways << LCD_CR0_DCLK_Pos) | - (initStruct->HsyncWidth << LCD_CR0_HLOW_Pos); - - LCDx->CR1 = (initStruct->Dir << LCD_CR1_DIRV_Pos) | - ((initStruct->Hfp - 1) << LCD_CR1_HFP_Pos) | - ((initStruct->Hbp - 1) << LCD_CR1_HBP_Pos) | - ((initStruct->Vfp - 1) << LCD_CR1_VFP_Pos) | - ((initStruct->Vbp - 1) << LCD_CR1_VBP_Pos) | - (initStruct->ClkDiv << LCD_CR1_DCLKDIV_Pos) | - (initStruct->SamplEdge << LCD_CR1_DCLKINV_Pos); - } - else - { - LCDx->CR0 = ((initStruct->HnPixel - 1) << LCD_CR0_VPIX_Pos) | - ((initStruct->VnPixel - 1) << LCD_CR0_HPIX_Pos) | - (initStruct->ClkAlways << LCD_CR0_DCLK_Pos) | - (initStruct->HsyncWidth << LCD_CR0_HLOW_Pos); - - LCDx->CR1 = (initStruct->Dir << LCD_CR1_DIRV_Pos) | - ((initStruct->Hfp - 1) << LCD_CR1_VFP_Pos) | - ((initStruct->Hbp - 1) << LCD_CR1_VBP_Pos) | - ((initStruct->Vfp - 1) << LCD_CR1_HFP_Pos) | - ((initStruct->Vbp - 1) << LCD_CR1_HBP_Pos) | - (initStruct->ClkDiv << LCD_CR1_DCLKDIV_Pos) | - (initStruct->SamplEdge << LCD_CR1_DCLKINV_Pos); - } - } - else if (initStruct->Interface == LCD_INTERFACE_I80) - { - LCDx->START = (1 << LCD_START_MPUEN_Pos); + LCDx->CR0 = ((initStruct->HnPixel - 1) << LCD_CR0_HPIX_Pos) | + ((initStruct->VnPixel - 1) << LCD_CR0_VPIX_Pos) | + (initStruct->ClkAlways << LCD_CR0_DCLK_Pos) | + (initStruct->HsyncWidth << LCD_CR0_HLOW_Pos); - LCDx->CR1 = (1 << LCD_CR1_I80_Pos) | - (initStruct->T_CSf_WRf << LCD_CR1_TAS_Pos) | - (initStruct->T_WRnHold << LCD_CR1_TPWLW_Pos) | - (initStruct->T_WRr_CSr << LCD_CR1_TAH_Pos) | - (initStruct->T_CSr_CSf << LCD_CR1_TTAIL_Pos); - } + LCDx->CR1 = ((initStruct->Hfp - 1) << LCD_CR1_HFP_Pos) | + ((initStruct->Hbp - 1) << LCD_CR1_HBP_Pos) | + ((initStruct->Vfp - 1) << LCD_CR1_VFP_Pos) | + ((initStruct->Vbp - 1) << LCD_CR1_VBP_Pos) | + (initStruct->ClkDiv << LCD_CR1_DCLKDIV_Pos) | + (initStruct->SamplEdge << LCD_CR1_DCLKINV_Pos); LCDx->IE = 1; - LCDx->IF = 1; //�����־ - if (initStruct->IntEOTEn) LCD_INTEn(LCDx); - else LCD_INTDis(LCDx); + LCDx->IF = 1; //清除标志 + if (initStruct->IntEOTEn) + LCD_INTEn(LCDx); + else + LCD_INTDis(LCDx); switch ((uint32_t)LCDx) { @@ -107,23 +75,23 @@ void LCD_Init(LCD_TypeDef *LCDx, LCD_InitStructure *initStruct) } /****************************************************************************************************************************************** -* ��������: LCD_Start() -* ����˵��: ����һ�����ݴ��� -* �� ��: LCD_TypeDef * LCDx ָ��Ҫ�����õ�LCD����Чֵ����LCD -* �� ��: �� -* ע������: �� +* 函数名称: LCD_Start() +* 功能说明: 启动一次数据传输 +* 输 入: LCD_TypeDef * LCDx 指定要被设置的LCD，有效值包括LCD +* 输 出: 无 +* 注意事项: 无 ******************************************************************************************************************************************/ void LCD_Start(LCD_TypeDef *LCDx) { - LCDx->START |= (1 << LCD_START_GO_Pos); + LCDx->START |= (1 << LCD_START_GO_Pos) | (1 << LCD_START_BURST_Pos); } /****************************************************************************************************************************************** -* ��������: LCD_IsBusy() -* ����˵��: �Ƿ����ڽ������ݴ��� -* �� ��: LCD_TypeDef * LCDx ָ��Ҫ�����õ�LCD����Чֵ����LCD -* �� ��: uint32_t 1 ���ڴ������� 0 ���ݴ�������� -* ע������: �� +* 函数名称: LCD_IsBusy() +* 功能说明: 是否正在进行数据传输 +* 输 入: LCD_TypeDef * LCDx 指定要被设置的LCD，有效值包括LCD +* 输 出: uint32_t 1 正在传输数据 0 数据传输已完成 +* 注意事项: 无 ******************************************************************************************************************************************/ uint32_t LCD_IsBusy(LCD_TypeDef *LCDx) { @@ -131,91 +99,11 @@ uint32_t LCD_IsBusy(LCD_TypeDef *LCDx) } /****************************************************************************************************************************************** -* ��������: LCD_I80_WriteReg() -* ����˵��: MPU�ӿ�ʱ��д�Ĵ��� -* �� ��: LCD_TypeDef * LCDx ָ��Ҫ�����õ�LCD����Чֵ����LCD -* uint16_t reg Ҫд�ļĴ�����ʵ��ַ����ַ���� -* uint16_t val[] �Ĵ���ֵ�������ַ�����Զ��� -* uint16_t cnt Ҫд�ļĴ������� -* �� ��: �� -* ע������: �� -******************************************************************************************************************************************/ -void LCD_I80_WriteReg(LCD_TypeDef *LCDx, uint16_t reg, uint16_t val[], uint16_t cnt) -{ - LCD->SRCADDR = (uint32_t)val; - LCD->CR0 &= ~LCD_CR0_DLEN_Msk; - LCD->CR0 |= ((cnt - 1) << LCD_CR0_DLEN_Pos); - - LCD->CR1 |= (1 << LCD_CR1_CMD_Pos); - LCD->CR1 &= ~LCD_CR1_REG_Msk; - LCD->CR1 |= (reg << LCD_CR1_REG_Pos); - - LCD_Start(LCDx); - while (LCD_IsBusy(LCDx)); -} - -/****************************************************************************************************************************************** -* ��������: LCD_I80_WriteOneReg() -* ����˵��: MPU�ӿ�ʱ��д�Ĵ��� -* �� ��: LCD_TypeDef * LCDx ָ��Ҫ�����õ�LCD����Чֵ����LCD -* uint16_t reg Ҫд�ļĴ�����ʵ��ַ -* uint16_t val �Ĵ���ֵ -* �� ��: �� -* ע������: �� -******************************************************************************************************************************************/ -void LCD_I80_WriteOneReg(LCD_TypeDef *LCDx, uint16_t reg, uint16_t val) -{ - uint16_t buf[1] __attribute__((aligned(4))); - - buf[0] = val; - - LCD_I80_WriteReg(LCDx, reg, buf, 1); -} - -/****************************************************************************************************************************************** -* ��������: LCD_I80_WriteData() -* ����˵��: MPU�ӿ�ʱ��д���� -* �� ��: LCD_TypeDef * LCDx ָ��Ҫ�����õ�LCD����Чֵ����LCD -* uint16_t val[] Ҫд�����ݣ������ַ�����Զ��� -* uint16_t cnt Ҫд�����ݸ��� -* �� ��: �� -* ע������: �� -******************************************************************************************************************************************/ -void LCD_I80_WriteData(LCD_TypeDef *LCDx, uint16_t val[], uint16_t cnt) -{ - LCD->SRCADDR = (uint32_t)val; - LCD->CR0 &= ~LCD_CR0_DLEN_Msk; - LCD->CR0 |= ((cnt - 1) << LCD_CR0_DLEN_Pos); - - LCD->CR1 &= ~(1 << LCD_CR1_CMD_Pos); - - LCD_Start(LCDx); - while (LCD_IsBusy(LCDx)); -} - -/****************************************************************************************************************************************** -* ��������: LCD_I80_WriteOneData() -* ����˵��: MPU�ӿ�ʱ��д���� -* �� ��: LCD_TypeDef * LCDx ָ��Ҫ�����õ�LCD����Чֵ����LCD -* uint16_t val Ҫд������ -* �� ��: �� -* ע������: �� -******************************************************************************************************************************************/ -void LCD_I80_WriteOneData(LCD_TypeDef *LCDx, uint16_t val) -{ - uint16_t buf[1] __attribute__((aligned(4))); - - buf[0] = val; - - LCD_I80_WriteData(LCDx, buf, 2); -} - -/****************************************************************************************************************************************** -* ��������: LCD_INTEn() -* ����˵��: LCD�ж�ʹ�ܣ����ָ�����ȵ����ݴ���ʱ�����ж� -* �� ��: LCD_TypeDef * LCDx ָ��Ҫ�����õ�LCD����Чֵ����LCD -* �� ��: �� -* ע������: �� +* 函数名称: LCD_INTEn() +* 功能说明: LCD中断使能，完成指定长度的数据传输时触发中断 +* 输 入: LCD_TypeDef * LCDx 指定要被设置的LCD，有效值包括LCD +* 输 出: 无 +* 注意事项: 无 ******************************************************************************************************************************************/ void LCD_INTEn(LCD_TypeDef *LCDx) { @@ -223,11 +111,11 @@ void LCD_INTEn(LCD_TypeDef *LCDx) } /****************************************************************************************************************************************** -* ��������: LCD_INTDis() -* ����˵��: LCD�жϽ�ֹ�����ָ�����ȵ����ݴ���ʱ�������ж� -* �� ��: LCD_TypeDef * LCDx ָ��Ҫ�����õ�LCD����Чֵ����LCD -* �� ��: �� -* ע������: �� +* 函数名称: LCD_INTDis() +* 功能说明: LCD中断禁止，完成指定长度的数据传输时不触发中断 +* 输 入: LCD_TypeDef * LCDx 指定要被设置的LCD，有效值包括LCD +* 输 出: 无 +* 注意事项: 无 ******************************************************************************************************************************************/ void LCD_INTDis(LCD_TypeDef *LCDx) { @@ -235,11 +123,11 @@ void LCD_INTDis(LCD_TypeDef *LCDx) } /****************************************************************************************************************************************** -* ��������: LCD_INTClr() -* ����˵��: LCD�жϱ�־��� -* �� ��: LCD_TypeDef * LCDx ָ��Ҫ�����õ�LCD����Чֵ����LCD -* �� ��: �� -* ע������: �� +* 函数名称: LCD_INTClr() +* 功能说明: LCD中断标志清除 +* 输 入: LCD_TypeDef * LCDx 指定要被设置的LCD，有效值包括LCD +* 输 出: 无 +* 注意事项: 无 ******************************************************************************************************************************************/ void LCD_INTClr(LCD_TypeDef *LCDx) { @@ -247,11 +135,11 @@ void LCD_INTClr(LCD_TypeDef *LCDx) } /****************************************************************************************************************************************** -* ��������: LCD_INTStat() -* ����˵��: LCD�ж�״̬��ѯ -* �� ��: LCD_TypeDef * LCDx ָ��Ҫ�����õ�LCD����Чֵ����LCD -* �� ��: uint32_t 1 ���ָ�����ȵ����ݴ��� 0 δ���ָ�����ȵ����ݴ��� -* ע������: �� +* 函数名称: LCD_INTStat() +* 功能说明: LCD中断状态查询 +* 输 入: LCD_TypeDef * LCDx 指定要被设置的LCD，有效值包括LCD +* 输 出: uint32_t 1 完成指定长度的数据传输 0 未完成指定长度的数据传输 +* 注意事项: 无 ******************************************************************************************************************************************/ uint32_t LCD_INTStat(LCD_TypeDef *LCDx) { diff --git a/bsp/swm320-lq100/Libraries/SWM320_StdPeriph_Driver/SWM320_lcd.h b/bsp/swm320-lq100/Libraries/SWM320_StdPeriph_Driver/SWM320_lcd.h index 0b9d9b53c3..d9c78f8d1f 100644 --- a/bsp/swm320-lq100/Libraries/SWM320_StdPeriph_Driver/SWM320_lcd.h +++ b/bsp/swm320-lq100/Libraries/SWM320_StdPeriph_Driver/SWM320_lcd.h @@ -1,96 +1,70 @@ #ifndef __SWM320_LCD_H__ #define __SWM320_LCD_H__ - typedef struct { - uint8_t Interface; //LCD���ӿڣ�LCD_INTERFACE_RGB��LCD_INTERFACE_I80��LCD_INTERFACE_M68 - - /* RGBͬ���ӿڲ��� */ - uint8_t Dir; //LCD_DIR_LANDSCAPE ���� LCD_DIR_PORTRAIT ���� - uint16_t HnPixel; //ˮƽ�������ظ��������ȡֵ1024 - uint16_t VnPixel; //��ֱ�������ظ��������ȡֵ 768 - uint8_t Hfp; //horizonal front porch�����ȡֵ32 - uint8_t Hbp; //horizonal back porch�� ���ȡֵ128 - uint8_t Vfp; //vertical front porch�� ���ȡֵ8 - uint8_t Vbp; //vertical back porch�� ���ȡֵ32 - uint8_t ClkDiv; //ϵͳʱ�Ӿ�ClkDiv��Ƶ�����DOCCLK��0 2��Ƶ 1 4��Ƶ 2 6��Ƶ ... ... 31 64��Ƶ - uint8_t SamplEdge; //��Ļ��DOTCLK���ĸ����ز������ݣ�LCD_SAMPLEDGE_RISE��LCD_SAMPLEDGE_FALL - uint8_t ClkAlways; //1 һֱ���DOTCLK 0 ֻ�ڴ�������ʱ���DOTCLK - uint8_t HsyncWidth; //HSYNC�͵�ƽ�������ٸ�DOTCLK��ȡֵ��LCD_HSYNC_1DOTCLK��LCD_HSYNC_2DOTCLK��LCD_HSYNC_3DOTCLK��LCD_HSYNC_4DOTCLK - - /* MPU��8080���ӿڲ��� */ - uint8_t T_CSf_WRf; //CSn�½��ص�WRn�½��ص�ʱ�䣬ȡֵ0--3 - uint8_t T_WRnHold; //WRn�͵�ƽ�ij���ʱ�䣬 ȡֵ0--7 - uint8_t T_WRr_CSr; //WRn�����ص�CSn�����ص�ʱ�䣬ȡֵ0--3 - uint8_t T_CSr_CSf; //CSn�����ص�CSn�½��ص�ʱ�䣬ȡֵ0--7 + uint16_t HnPixel; //水平方向像素个数，最大取值1024 + uint16_t VnPixel; //垂直方向像素个数，最大取值 768 + uint8_t Hfp; //horizonal front porch，最大取值32 + uint8_t Hbp; //horizonal back porch， 最大取值128 + uint8_t Vfp; //vertical front porch， 最大取值8 + uint8_t Vbp; //vertical back porch， 最大取值32 + uint8_t ClkDiv; //系统时钟经ClkDiv分频后产生DOCCLK，0 2分频 1 4分频 2 6分频 ... ... 31 64分频 + uint8_t SamplEdge; //屏幕在DOTCLK的哪个边沿采样数据：LCD_SAMPLEDGE_RISE、LCD_SAMPLEDGE_FALL + uint8_t ClkAlways; //1 一直输出DOTCLK 0 只在传输数据时输出DOTCLK + uint8_t HsyncWidth; //HSYNC低电平持续多少个DOTCLK，取值：LCD_HSYNC_1DOTCLK、LCD_HSYNC_2DOTCLK、LCD_HSYNC_3DOTCLK、LCD_HSYNC_4DOTCLK - uint8_t IntEOTEn; //End of Transter��������ɣ��ж�ʹ�� + uint8_t IntEOTEn; //End of Transter（传输完成）中断使能 } LCD_InitStructure; +#define LCD_SAMPLEDGE_RISE 0 //屏幕在DOTCLK的上升沿采样数据 +#define LCD_SAMPLEDGE_FALL 1 //屏幕在DOTCLK的下降沿采样数据 -#define LCD_INTERFACE_RGB 0 -#define LCD_INTERFACE_I80 1 -#define LCD_INTERFACE_M68 2 - -#define LCD_DIR_LANDSCAPE 0 //���� -#define LCD_DIR_PORTRAIT 1 //���� - -#define LCD_SAMPLEDGE_RISE 0 //��Ļ��DOTCLK�������ز������� -#define LCD_SAMPLEDGE_FALL 1 //��Ļ��DOTCLK���½��ز������� - -#define LCD_HSYNC_1DOTCLK 0 //1��DOTCLK -#define LCD_HSYNC_2DOTCLK 1 -#define LCD_HSYNC_3DOTCLK 2 -#define LCD_HSYNC_4DOTCLK 3 - -#define LCD_CLKDIV_2 0 -#define LCD_CLKDIV_4 1 -#define LCD_CLKDIV_6 2 -#define LCD_CLKDIV_8 3 -#define LCD_CLKDIV_10 4 -#define LCD_CLKDIV_12 5 -#define LCD_CLKDIV_14 6 -#define LCD_CLKDIV_16 7 -#define LCD_CLKDIV_18 8 -#define LCD_CLKDIV_20 9 -#define LCD_CLKDIV_22 10 -#define LCD_CLKDIV_24 11 -#define LCD_CLKDIV_26 12 -#define LCD_CLKDIV_28 13 -#define LCD_CLKDIV_30 14 -#define LCD_CLKDIV_32 15 -#define LCD_CLKDIV_34 16 -#define LCD_CLKDIV_36 17 -#define LCD_CLKDIV_38 18 -#define LCD_CLKDIV_40 19 -#define LCD_CLKDIV_42 20 -#define LCD_CLKDIV_44 21 -#define LCD_CLKDIV_46 22 -#define LCD_CLKDIV_48 23 -#define LCD_CLKDIV_50 24 -#define LCD_CLKDIV_52 25 -#define LCD_CLKDIV_54 26 -#define LCD_CLKDIV_56 27 -#define LCD_CLKDIV_58 28 -#define LCD_CLKDIV_60 29 -#define LCD_CLKDIV_62 30 -#define LCD_CLKDIV_64 31 +#define LCD_HSYNC_1DOTCLK 0 //1个DOTCLK +#define LCD_HSYNC_2DOTCLK 1 +#define LCD_HSYNC_3DOTCLK 2 +#define LCD_HSYNC_4DOTCLK 3 +#define LCD_CLKDIV_2 0 +#define LCD_CLKDIV_4 1 +#define LCD_CLKDIV_6 2 +#define LCD_CLKDIV_8 3 +#define LCD_CLKDIV_10 4 +#define LCD_CLKDIV_12 5 +#define LCD_CLKDIV_14 6 +#define LCD_CLKDIV_16 7 +#define LCD_CLKDIV_18 8 +#define LCD_CLKDIV_20 9 +#define LCD_CLKDIV_22 10 +#define LCD_CLKDIV_24 11 +#define LCD_CLKDIV_26 12 +#define LCD_CLKDIV_28 13 +#define LCD_CLKDIV_30 14 +#define LCD_CLKDIV_32 15 +#define LCD_CLKDIV_34 16 +#define LCD_CLKDIV_36 17 +#define LCD_CLKDIV_38 18 +#define LCD_CLKDIV_40 19 +#define LCD_CLKDIV_42 20 +#define LCD_CLKDIV_44 21 +#define LCD_CLKDIV_46 22 +#define LCD_CLKDIV_48 23 +#define LCD_CLKDIV_50 24 +#define LCD_CLKDIV_52 25 +#define LCD_CLKDIV_54 26 +#define LCD_CLKDIV_56 27 +#define LCD_CLKDIV_58 28 +#define LCD_CLKDIV_60 29 +#define LCD_CLKDIV_62 30 +#define LCD_CLKDIV_64 31 void LCD_Init(LCD_TypeDef *LCDx, LCD_InitStructure *initStruct); void LCD_Start(LCD_TypeDef *LCDx); uint32_t LCD_IsBusy(LCD_TypeDef *LCDx); -void LCD_I80_WriteReg(LCD_TypeDef *LCDx, uint16_t reg, uint16_t val[], uint16_t cnt); -void LCD_I80_WriteOneReg(LCD_TypeDef *LCDx, uint16_t reg, uint16_t val); -void LCD_I80_WriteData(LCD_TypeDef *LCDx, uint16_t data[], uint16_t cnt); -void LCD_I80_WriteOneData(LCD_TypeDef *LCDx, uint16_t val); - void LCD_INTEn(LCD_TypeDef *LCDx); void LCD_INTDis(LCD_TypeDef *LCDx); void LCD_INTClr(LCD_TypeDef *LCDx); uint32_t LCD_INTStat(LCD_TypeDef *LCDx); - #endif //__SWM320_LCD_H__ diff --git a/bsp/swm320-lq100/Libraries/SWM320_StdPeriph_Driver/SWM320_norflash.c b/bsp/swm320-lq100/Libraries/SWM320_StdPeriph_Driver/SWM320_norflash.c index 0d183cee36..f9e306d6fb 100644 --- a/bsp/swm320-lq100/Libraries/SWM320_StdPeriph_Driver/SWM320_norflash.c +++ b/bsp/swm320-lq100/Libraries/SWM320_StdPeriph_Driver/SWM320_norflash.c @@ -1,10 +1,10 @@ /****************************************************************************************************************************************** -* �ļ�����: SWM320_norflash.c -* ����˵��: SWM320��Ƭ����NOR Flash�������� -* ����֧��: http://www.synwit.com.cn/e/tool/gbook/?bid=1 -* ע������: -* �汾����: V1.1.0 2017��10��25�� -* ������¼: +* 文件名称: SWM320_norflash.c +* 功能说明: SWM320单片机的NOR Flash驱动程序 +* 技术支持: http://www.synwit.com.cn/e/tool/gbook/?bid=1 +* 注意事项: +* 版本日期: V1.1.0 2017年10月25日 +* 升级记录: * * ******************************************************************************************************************************************* @@ -21,30 +21,30 @@ #include "SWM320.h" #include "SWM320_norflash.h" - /****************************************************************************************************************************************** -* ��������: NORFL_Init() -* ����˵��: NOR Flash��������ʼ�� -* �� ��: NORFL_InitStructure * initStruct ����NOR Flash����������趨ֵ�Ľṹ�� -* �� ��: �� -* ע������: �� +* 函数名称: NORFL_Init() +* 功能说明: NOR Flash控制器初始化 +* 输 入: NORFL_InitStructure * initStruct 包含NOR Flash控制器相关设定值的结构体 +* 输 出: 无 +* 注意事项: 无 ******************************************************************************************************************************************/ void NORFL_Init(NORFL_InitStructure *initStruct) { uint32_t i; - // ����SRAMǰ��Ҫˢ����SDRAM������ + // 配置SRAM前需要刷新下SDRAM控制器 do { SYS->CLKEN |= (1 << SYS_CLKEN_SDRAM_Pos); - while (SDRAMC->REFDONE == 0); + while (SDRAMC->REFDONE == 0) + ; SDRAMC->REFRESH &= ~(1 << SDRAMC_REFRESH_EN_Pos); - for (i = 0; i < 1000; i++) __NOP(); + for (i = 0; i < 1000; i++) + __NOP(); SYS->CLKEN &= ~(1 << SYS_CLKEN_SDRAM_Pos); - } - while (0); + } while (0); SYS->CLKEN |= (1 << SYS_CLKEN_NORFL_Pos); @@ -53,19 +53,23 @@ void NORFL_Init(NORFL_InitStructure *initStruct) (initStruct->OEPreValidTime << NORFLC_CR_RDTIME_Pos); NORFLC->IE = 3; - NORFLC->IF = 3; // ����жϱ�־ - if (initStruct->OperFinishIEn) NORFLC->IM &= ~(1 << NORFLC_IM_FINISH_Pos); - else NORFLC->IM |= (1 << NORFLC_IM_FINISH_Pos); - if (initStruct->OperTimeoutIEn) NORFLC->IM &= ~(1 << NORFLC_IM_TIMEOUT_Pos); - else NORFLC->IM |= (1 << NORFLC_IM_TIMEOUT_Pos); + NORFLC->IF = 3; // 清除中断标志 + if (initStruct->OperFinishIEn) + NORFLC->IM &= ~(1 << NORFLC_IM_FINISH_Pos); + else + NORFLC->IM |= (1 << NORFLC_IM_FINISH_Pos); + if (initStruct->OperTimeoutIEn) + NORFLC->IM &= ~(1 << NORFLC_IM_TIMEOUT_Pos); + else + NORFLC->IM |= (1 << NORFLC_IM_TIMEOUT_Pos); } /****************************************************************************************************************************************** -* ��������: NORFL_ChipErase() -* ����˵��: NOR Flash��Ƭ���� -* �� ��: �� -* �� ��: uint32_t 0 �����ɹ� 1 ������ʱ -* ע������: �� +* 函数名称: NORFL_ChipErase() +* 功能说明: NOR Flash整片擦除 +* 输 入: 无 +* 输 出: uint32_t 0 擦除成功 1 擦除超时 +* 注意事项: 无 ******************************************************************************************************************************************/ uint32_t NORFL_ChipErase(void) { @@ -74,10 +78,13 @@ uint32_t NORFL_ChipErase(void) NORFLC->CMD = (NORFL_CMD_CHIP_ERASE << NORFLC_CMD_CMD_Pos); while (((NORFLC->IF & NORFLC_IF_FINISH_Msk) == 0) && - ((NORFLC->IF & NORFLC_IF_TIMEOUT_Msk) == 0)) __NOP(); + ((NORFLC->IF & NORFLC_IF_TIMEOUT_Msk) == 0)) + __NOP(); - if (NORFLC->IF & NORFLC_IF_FINISH_Msk) res = 0; - else res = 1; + if (NORFLC->IF & NORFLC_IF_FINISH_Msk) + res = 0; + else + res = 1; NORFLC->IF = NORFLC_IF_FINISH_Msk | NORFLC_IF_TIMEOUT_Msk; @@ -85,11 +92,11 @@ uint32_t NORFL_ChipErase(void) } /****************************************************************************************************************************************** -* ��������: NORFL_SectorErase() -* ����˵��: NOR Flash�������� -* �� ��: uint32_t addr Ҫ������������ʼ��ַ -* �� ��: uint32_t 0 �����ɹ� 1 ������ʱ -* ע������: MX29LV128DB ǰ8����Ϊ8K����255����Ϊ64K MX29LV128DT ǰ255����Ϊ64K����8����Ϊ8K +* 函数名称: NORFL_SectorErase() +* 功能说明: NOR Flash扇区擦除 +* 输 入: uint32_t addr 要擦除扇区的起始地址 +* 输 出: uint32_t 0 擦除成功 1 擦除超时 +* 注意事项: MX29LV128DB 前8扇区为8K、后255扇区为64K MX29LV128DT 前255扇区为64K、后8扇区为8K ******************************************************************************************************************************************/ uint32_t NORFL_SectorErase(uint32_t addr) { @@ -99,10 +106,13 @@ uint32_t NORFL_SectorErase(uint32_t addr) NORFLC->CMD = (NORFL_CMD_SECTOR_ERASE << NORFLC_CMD_CMD_Pos); while (((NORFLC->IF & NORFLC_IF_FINISH_Msk) == 0) && - ((NORFLC->IF & NORFLC_IF_TIMEOUT_Msk) == 0)) __NOP(); + ((NORFLC->IF & NORFLC_IF_TIMEOUT_Msk) == 0)) + __NOP(); - if (NORFLC->IF & NORFLC_IF_FINISH_Msk) res = 0; - else res = 1; + if (NORFLC->IF & NORFLC_IF_FINISH_Msk) + res = 0; + else + res = 1; NORFLC->IF = NORFLC_IF_FINISH_Msk | NORFLC_IF_TIMEOUT_Msk; @@ -110,12 +120,12 @@ uint32_t NORFL_SectorErase(uint32_t addr) } /****************************************************************************************************************************************** -* ��������: NORFL_Write() -* ����˵��: NOR Flashд -* �� ��: uint32_t addr ����Ҫд��ĵ�ַ -* uint32_t data Ҫд������� -* �� ��: uint32_t 0 д��ɹ� 1 д�볬ʱ -* ע������: Ӳ�����ӣ�������Ϊ16λʱ������д�룻������Ϊ8λʱ���ֽ�д�� +* 函数名称: NORFL_Write() +* 功能说明: NOR Flash写 +* 输 入: uint32_t addr 数据要写入的地址 +* uint32_t data 要写入的数据 +* 输 出: uint32_t 0 写入成功 1 写入超时 +* 注意事项: 硬件连接，数据线为16位时，半字写入；数据线为8位时，字节写入 ******************************************************************************************************************************************/ uint32_t NORFL_Write(uint32_t addr, uint32_t data) { @@ -125,10 +135,13 @@ uint32_t NORFL_Write(uint32_t addr, uint32_t data) NORFLC->CMD = (NORFL_CMD_PROGRAM << NORFLC_CMD_CMD_Pos) | (data << NORFLC_CMD_DATA_Pos); while (((NORFLC->IF & NORFLC_IF_FINISH_Msk) == 0) && - ((NORFLC->IF & NORFLC_IF_TIMEOUT_Msk) == 0)) __NOP(); + ((NORFLC->IF & NORFLC_IF_TIMEOUT_Msk) == 0)) + __NOP(); - if (NORFLC->IF & NORFLC_IF_FINISH_Msk) res = 0; - else res = 1; + if (NORFLC->IF & NORFLC_IF_FINISH_Msk) + res = 0; + else + res = 1; NORFLC->IF = NORFLC_IF_FINISH_Msk | NORFLC_IF_TIMEOUT_Msk; @@ -136,11 +149,11 @@ uint32_t NORFL_Write(uint32_t addr, uint32_t data) } /****************************************************************************************************************************************** -* ��������: NORFL_Read() -* ����˵��: NOR Flash�� -* �� ��: uint32_t addr ����Ҫ�����ĵ�ַ -* �� ��: uint32_t ���������� -* ע������: Ӳ�����ӣ�������Ϊ16λʱ�����ֶ�����������Ϊ8λʱ���ֽڶ��� +* 函数名称: NORFL_Read() +* 功能说明: NOR Flash读 +* 输 入: uint32_t addr 数据要读出的地址 +* 输 出: uint32_t 读出的数据 +* 注意事项: 硬件连接，数据线为16位时，半字读出；数据线为8位时，字节读出 ******************************************************************************************************************************************/ uint32_t NORFL_Read(uint32_t addr) { @@ -151,11 +164,11 @@ uint32_t NORFL_Read(uint32_t addr) } /****************************************************************************************************************************************** -* ��������: NORFL_ReadID() -* ����˵��: NOR Flash��ID -* �� ��: uint32_t id_addr ID��ַ���˲�����оƬ��صģ�ÿ��оƬ����ͬ -* �� ��: uint16_t ��ȡ����ID -* ע������: �� +* 函数名称: NORFL_ReadID() +* 功能说明: NOR Flash读ID +* 输 入: uint32_t id_addr ID地址，此参数是芯片相关的，每种芯片都不同 +* 输 出: uint16_t 读取到的ID +* 注意事项: 无 ******************************************************************************************************************************************/ uint16_t NORFL_ReadID(uint32_t id_addr) { @@ -168,7 +181,7 @@ uint16_t NORFL_ReadID(uint32_t id_addr) id = NORFLC->CMD & NORFLC_CMD_DATA_Msk; - NORFLC->CMD = (NORFL_CMD_RESET << NORFLC_CMD_CMD_Pos); // �˳�ID��ȡģʽ + NORFLC->CMD = (NORFL_CMD_RESET << NORFLC_CMD_CMD_Pos); // 退出ID读取模式 return id; } diff --git a/bsp/swm320-lq100/Libraries/SWM320_StdPeriph_Driver/SWM320_norflash.h b/bsp/swm320-lq100/Libraries/SWM320_StdPeriph_Driver/SWM320_norflash.h index fc859268fb..77fb034557 100644 --- a/bsp/swm320-lq100/Libraries/SWM320_StdPeriph_Driver/SWM320_norflash.h +++ b/bsp/swm320-lq100/Libraries/SWM320_StdPeriph_Driver/SWM320_norflash.h @@ -3,17 +3,15 @@ typedef struct { - uint8_t DataWidth; // 8��16 + uint8_t DataWidth; // 8、16 - uint8_t WELowPulseTime; // WE# pulse width����λΪϵͳʱ�����ڣ����ֵΪ7 - uint8_t OEPreValidTime; // Valid data output after OE# low����λΪϵͳʱ�����ڣ����ֵΪ15 + uint8_t WELowPulseTime; // WE# pulse width，单位为系统时钟周期，最大值为7 + uint8_t OEPreValidTime; // Valid data output after OE# low，单位为系统时钟周期，最大值为15 - uint8_t OperFinishIEn; // ����(д�롢����)����ж�ʹ�� + uint8_t OperFinishIEn; // 操作(写入、擦除)完成中断使能 uint8_t OperTimeoutIEn; } NORFL_InitStructure; - - void NORFL_Init(NORFL_InitStructure *initStruct); uint32_t NORFL_ChipErase(void); uint32_t NORFL_SectorErase(uint32_t addr); @@ -21,19 +19,16 @@ uint32_t NORFL_Write(uint32_t addr, uint32_t data); uint32_t NORFL_Read(uint32_t addr); uint16_t NORFL_ReadID(uint32_t id_addr); +/* 当前版本总线读只支持字读 +#define NORFL_Read8(addr) *((volatile uint8_t *)(NORFLM_BASE + addr)) +#define NORFL_Read16(addr) *((volatile uint16_t *)(NORFLM_BASE + addr)) */ +#define NORFL_Read32(addr) *((volatile uint32_t *)(NORFLM_BASE + addr)) -/* ��ǰ�汾���߶�ֻ֧���ֶ� -#define NORFL_Read8(addr) *((volatile uint8_t *)(NORFLM_BASE + addr)) -#define NORFL_Read16(addr) *((volatile uint16_t *)(NORFLM_BASE + addr)) */ -#define NORFL_Read32(addr) *((volatile uint32_t *)(NORFLM_BASE + addr)) - - - -#define NORFL_CMD_READ 0 -#define NORFL_CMD_RESET 1 -#define NORFL_CMD_AUTO_SELECT 2 -#define NORFL_CMD_PROGRAM 3 -#define NORFL_CMD_CHIP_ERASE 4 -#define NORFL_CMD_SECTOR_ERASE 5 +#define NORFL_CMD_READ 0 +#define NORFL_CMD_RESET 1 +#define NORFL_CMD_AUTO_SELECT 2 +#define NORFL_CMD_PROGRAM 3 +#define NORFL_CMD_CHIP_ERASE 4 +#define NORFL_CMD_SECTOR_ERASE 5 #endif // __SWM320_NORFLASH_H__ diff --git a/bsp/swm320-lq100/Libraries/SWM320_StdPeriph_Driver/SWM320_port.c b/bsp/swm320-lq100/Libraries/SWM320_StdPeriph_Driver/SWM320_port.c index bc7a555a30..5fa0be4ada 100644 --- a/bsp/swm320-lq100/Libraries/SWM320_StdPeriph_Driver/SWM320_port.c +++ b/bsp/swm320-lq100/Libraries/SWM320_StdPeriph_Driver/SWM320_port.c @@ -1,10 +1,10 @@ /****************************************************************************************************************************************** -* �ļ�����: SWM320_port.c -* ����˵��: SWM320��Ƭ���Ķ˿����Ź���ѡ��⺯�� -* ����֧��: http://www.synwit.com.cn/e/tool/gbook/?bid=1 -* ע������: -* �汾����: V1.1.0 2017��10��25�� -* ������¼: +* 文件名称: SWM320_port.c +* 功能说明: SWM320单片机的端口引脚功能选择库函数 +* 技术支持: http://www.synwit.com.cn/e/tool/gbook/?bid=1 +* 注意事项: +* 版本日期: V1.1.0 2017年10月25日 +* 升级记录: * * ******************************************************************************************************************************************* @@ -21,17 +21,16 @@ #include "SWM320.h" #include "SWM320_port.h" - /****************************************************************************************************************************************** -* ��������: PORT_Init() -* ����˵��: �˿����Ź���ѡ���õĹ��ܼ�"SWM320_port.h"�ļ� -* �� ��: uint32_t PORTx ָ��PORT�˿ڣ���Чֵ����PORTA��PORTB��PORTC��PORTM��PORTN��PORTP -* uint32_t n ָ��PORT���ţ���Чֵ����PIN0��PIN1��PIN2��... ... PIN22��PIN23 -* uint32_t func ָ���˿�����Ҫ�趨�Ĺ��ܣ����ȡֵ��"SWM320_port.h"�ļ� -* uint32_t digit_in_en ��������ʹ�� -* �� ��: �� -* ע������: �����ű��nΪż��ʱ��funcȡֵֻ����FUNMUX0��ͷ�ģ���FUNMUX0_UART0_RXD -* �����ű��nΪ����ʱ��funcȡֵֻ����FUNMUX1��ͷ�ģ���FUNMUX1_UART0_TXD +* 函数名称: PORT_Init() +* 功能说明: 端口引脚功能选择，可用的功能见"SWM320_port.h"文件 +* 输 入: uint32_t PORTx 指定PORT端口，有效值包括PORTA、PORTB、PORTC、PORTM、PORTN、PORTP +* uint32_t n 指定PORT引脚，有效值包括PIN0、PIN1、PIN2、... ... PIN22、PIN23 +* uint32_t func 指定端口引脚要设定的功能，其可取值见"SWM320_port.h"文件 +* uint32_t digit_in_en 数字输入使能 +* 输 出: 无 +* 注意事项: 当引脚标号n为偶数时，func取值只能是FUNMUX0开头的，如FUNMUX0_UART0_RXD +* 当引脚标号n为奇数时，func取值只能是FUNMUX1开头的，如FUNMUX1_UART0_TXD ******************************************************************************************************************************************/ void PORT_Init(uint32_t PORTx, uint32_t n, uint32_t func, uint32_t digit_in_en) { diff --git a/bsp/swm320-lq100/Libraries/SWM320_StdPeriph_Driver/SWM320_port.h b/bsp/swm320-lq100/Libraries/SWM320_StdPeriph_Driver/SWM320_port.h index ff0fd9cdc9..0d1ec56db1 100644 --- a/bsp/swm320-lq100/Libraries/SWM320_StdPeriph_Driver/SWM320_port.h +++ b/bsp/swm320-lq100/Libraries/SWM320_StdPeriph_Driver/SWM320_port.h @@ -1,482 +1,474 @@ #ifndef __SWM320_PORT_H__ #define __SWM320_PORT_H__ -void PORT_Init(uint32_t PORTx, uint32_t n, uint32_t func, uint32_t digit_in_en); //�˿����Ź���ѡ�����ȡֵ���£� +void PORT_Init(uint32_t PORTx, uint32_t n, uint32_t func, uint32_t digit_in_en); //端口引脚功能选择，其可取值如下： -#define PORTA 0 -#define PORTB 1 -#define PORTC 2 -#define PORTM 3 -#define PORTN 4 -#define PORTP 5 +#define PORTA 0 +#define PORTB 1 +#define PORTC 2 +#define PORTM 3 +#define PORTN 4 +#define PORTP 5 -#define PORTA_PIN0_GPIO 0 -#define PORTA_PIN0_FUNMUX 1 -#define PORTA_PIN0_SWCLK 2 +#define PORTA_PIN0_GPIO 0 +#define PORTA_PIN0_FUNMUX 1 +#define PORTA_PIN0_SWCLK 2 -#define PORTA_PIN1_GPIO 0 -#define PORTA_PIN1_FUNMUX 1 -#define PORTA_PIN1_SWDIO 2 +#define PORTA_PIN1_GPIO 0 +#define PORTA_PIN1_FUNMUX 1 +#define PORTA_PIN1_SWDIO 2 -#define PORTA_PIN2_GPIO 0 -#define PORTA_PIN2_FUNMUX 1 +#define PORTA_PIN2_GPIO 0 +#define PORTA_PIN2_FUNMUX 1 -#define PORTA_PIN3_GPIO 0 -#define PORTA_PIN3_FUNMUX 1 +#define PORTA_PIN3_GPIO 0 +#define PORTA_PIN3_FUNMUX 1 -#define PORTA_PIN4_GPIO 0 -#define PORTA_PIN4_FUNMUX 1 +#define PORTA_PIN4_GPIO 0 +#define PORTA_PIN4_FUNMUX 1 -#define PORTA_PIN5_GPIO 0 -#define PORTA_PIN5_FUNMUX 1 +#define PORTA_PIN5_GPIO 0 +#define PORTA_PIN5_FUNMUX 1 -#define PORTA_PIN6_GPIO 0 -#define PORTA_PIN6_FUNMUX 1 +#define PORTA_PIN6_GPIO 0 +#define PORTA_PIN6_FUNMUX 1 -#define PORTA_PIN7_GPIO 0 -#define PORTA_PIN7_FUNMUX 1 +#define PORTA_PIN7_GPIO 0 +#define PORTA_PIN7_FUNMUX 1 -#define PORTA_PIN8_GPIO 0 -#define PORTA_PIN8_FUNMUX 1 +#define PORTA_PIN8_GPIO 0 +#define PORTA_PIN8_FUNMUX 1 -#define PORTA_PIN9_GPIO 0 -#define PORTA_PIN9_FUNMUX 1 -#define PORTA_PIN9_ADC0_IN7 3 +#define PORTA_PIN9_GPIO 0 +#define PORTA_PIN9_FUNMUX 1 +#define PORTA_PIN9_ADC0_IN7 3 -#define PORTA_PIN10_GPIO 0 -#define PORTA_PIN10_FUNMUX 1 -#define PORTA_PIN10_ADC0_IN6 3 +#define PORTA_PIN10_GPIO 0 +#define PORTA_PIN10_FUNMUX 1 +#define PORTA_PIN10_ADC0_IN6 3 -#define PORTA_PIN11_GPIO 0 -#define PORTA_PIN11_FUNMUX 1 -#define PORTA_PIN11_ADC0_IN5 3 +#define PORTA_PIN11_GPIO 0 +#define PORTA_PIN11_FUNMUX 1 +#define PORTA_PIN11_ADC0_IN5 3 -#define PORTA_PIN12_GPIO 0 -#define PORTA_PIN12_ADC0_IN4 3 +#define PORTA_PIN12_GPIO 0 +#define PORTA_PIN12_ADC0_IN4 3 +#define PORTB_PIN0_GPIO 0 +#define PORTB_PIN0_FUNMUX 1 +#define PORTB_PIN0_SD_DETECT 2 -#define PORTB_PIN0_GPIO 0 -#define PORTB_PIN0_FUNMUX 1 -#define PORTB_PIN0_SD_DETECT 2 +#define PORTB_PIN1_GPIO 0 +#define PORTB_PIN1_FUNMUX 1 +#define PORTB_PIN1_SD_CLK 2 -#define PORTB_PIN1_GPIO 0 -#define PORTB_PIN1_FUNMUX 1 -#define PORTB_PIN1_SD_CLK 2 +#define PORTB_PIN2_GPIO 0 +#define PORTB_PIN2_FUNMUX 1 +#define PORTB_PIN2_SD_CMD 2 -#define PORTB_PIN2_GPIO 0 -#define PORTB_PIN2_FUNMUX 1 -#define PORTB_PIN2_SD_CMD 2 +#define PORTB_PIN3_GPIO 0 +#define PORTB_PIN3_FUNMUX 1 +#define PORTB_PIN3_SD_D0 2 -#define PORTB_PIN3_GPIO 0 -#define PORTB_PIN3_FUNMUX 1 -#define PORTB_PIN3_SD_D0 2 +#define PORTB_PIN4_GPIO 0 +#define PORTB_PIN4_FUNMUX 1 +#define PORTB_PIN4_SD_D1 2 -#define PORTB_PIN4_GPIO 0 -#define PORTB_PIN4_FUNMUX 1 -#define PORTB_PIN4_SD_D1 2 +#define PORTB_PIN5_GPIO 0 +#define PORTB_PIN5_FUNMUX 1 +#define PORTB_PIN5_SD_D2 2 -#define PORTB_PIN5_GPIO 0 -#define PORTB_PIN5_FUNMUX 1 -#define PORTB_PIN5_SD_D2 2 +#define PORTB_PIN6_GPIO 0 +#define PORTB_PIN6_FUNMUX 1 +#define PORTB_PIN6_SD_D3 2 -#define PORTB_PIN6_GPIO 0 -#define PORTB_PIN6_FUNMUX 1 -#define PORTB_PIN6_SD_D3 2 +#define PORTB_PIN7_GPIO 0 +#define PORTB_PIN7_FUNMUX 1 +#define PORTB_PIN7_SD_D4 2 -#define PORTB_PIN7_GPIO 0 -#define PORTB_PIN7_FUNMUX 1 -#define PORTB_PIN7_SD_D4 2 +#define PORTB_PIN8_GPIO 0 +#define PORTB_PIN8_FUNMUX 1 +#define PORTB_PIN8_SD_D5 2 -#define PORTB_PIN8_GPIO 0 -#define PORTB_PIN8_FUNMUX 1 -#define PORTB_PIN8_SD_D5 2 +#define PORTB_PIN9_GPIO 0 +#define PORTB_PIN9_FUNMUX 1 +#define PORTB_PIN9_SD_D6 2 -#define PORTB_PIN9_GPIO 0 -#define PORTB_PIN9_FUNMUX 1 -#define PORTB_PIN9_SD_D6 2 +#define PORTB_PIN10_GPIO 0 +#define PORTB_PIN10_FUNMUX 1 +#define PORTB_PIN10_SD_D7 2 -#define PORTB_PIN10_GPIO 0 -#define PORTB_PIN10_FUNMUX 1 -#define PORTB_PIN10_SD_D7 2 +#define PORTB_PIN11_GPIO 0 +#define PORTB_PIN11_FUNMUX 1 -#define PORTB_PIN11_GPIO 0 -#define PORTB_PIN11_FUNMUX 1 +#define PORTB_PIN12_GPIO 0 -#define PORTB_PIN12_GPIO 0 +#define PORTC_PIN0_GPIO 0 +#define PORTC_PIN0_FUNMUX 1 +#define PORTC_PIN1_GPIO 0 +#define PORTC_PIN1_FUNMUX 1 -#define PORTC_PIN0_GPIO 0 -#define PORTC_PIN0_FUNMUX 1 +#define PORTC_PIN2_GPIO 0 +#define PORTC_PIN2_FUNMUX 1 -#define PORTC_PIN1_GPIO 0 -#define PORTC_PIN1_FUNMUX 1 +#define PORTC_PIN3_GPIO 0 +#define PORTC_PIN3_FUNMUX 1 -#define PORTC_PIN2_GPIO 0 -#define PORTC_PIN2_FUNMUX 1 +#define PORTC_PIN4_GPIO 0 +#define PORTC_PIN4_FUNMUX 1 +#define PORTC_PIN4_ADC1_IN3 3 -#define PORTC_PIN3_GPIO 0 -#define PORTC_PIN3_FUNMUX 1 +#define PORTC_PIN5_GPIO 0 +#define PORTC_PIN5_FUNMUX 1 +#define PORTC_PIN5_ADC1_IN2 3 -#define PORTC_PIN4_GPIO 0 -#define PORTC_PIN4_FUNMUX 1 -#define PORTC_PIN4_ADC1_IN3 3 +#define PORTC_PIN6_GPIO 0 +#define PORTC_PIN6_FUNMUX 1 +#define PORTC_PIN6_ADC1_IN1 3 -#define PORTC_PIN5_GPIO 0 -#define PORTC_PIN5_FUNMUX 1 -#define PORTC_PIN5_ADC1_IN2 3 +#define PORTC_PIN7_GPIO 0 +#define PORTC_PIN7_FUNMUX 1 +#define PORTC_PIN7_ADC1_IN0 3 -#define PORTC_PIN6_GPIO 0 -#define PORTC_PIN6_FUNMUX 1 -#define PORTC_PIN6_ADC1_IN1 3 +#define PORTM_PIN0_GPIO 0 +#define PORTM_PIN0_FUNMUX 1 +#define PORTM_PIN0_NORFL_D15 2 -#define PORTC_PIN7_GPIO 0 -#define PORTC_PIN7_FUNMUX 1 -#define PORTC_PIN7_ADC1_IN0 3 +#define PORTM_PIN1_GPIO 0 +#define PORTM_PIN1_FUNMUX 1 +#define PORTM_PIN1_NORFL_D14 2 +#define PORTM_PIN2_GPIO 0 +#define PORTM_PIN2_FUNMUX 1 +#define PORTM_PIN2_NORFL_D13 2 -#define PORTM_PIN0_GPIO 0 -#define PORTM_PIN0_FUNMUX 1 -#define PORTM_PIN0_NORFL_D15 2 +#define PORTM_PIN3_GPIO 0 +#define PORTM_PIN3_FUNMUX 1 +#define PORTM_PIN3_NORFL_D12 2 -#define PORTM_PIN1_GPIO 0 -#define PORTM_PIN1_FUNMUX 1 -#define PORTM_PIN1_NORFL_D14 2 +#define PORTM_PIN4_GPIO 0 +#define PORTM_PIN4_FUNMUX 1 +#define PORTM_PIN4_NORFL_D11 2 -#define PORTM_PIN2_GPIO 0 -#define PORTM_PIN2_FUNMUX 1 -#define PORTM_PIN2_NORFL_D13 2 +#define PORTM_PIN5_GPIO 0 +#define PORTM_PIN5_FUNMUX 1 +#define PORTM_PIN5_NORFL_D10 2 -#define PORTM_PIN3_GPIO 0 -#define PORTM_PIN3_FUNMUX 1 -#define PORTM_PIN3_NORFL_D12 2 +#define PORTM_PIN6_GPIO 0 +#define PORTM_PIN6_FUNMUX 1 +#define PORTM_PIN6_NORFL_D9 2 -#define PORTM_PIN4_GPIO 0 -#define PORTM_PIN4_FUNMUX 1 -#define PORTM_PIN4_NORFL_D11 2 +#define PORTM_PIN7_GPIO 0 +#define PORTM_PIN7_FUNMUX 1 +#define PORTM_PIN7_NORFL_D8 2 -#define PORTM_PIN5_GPIO 0 -#define PORTM_PIN5_FUNMUX 1 -#define PORTM_PIN5_NORFL_D10 2 +#define PORTM_PIN8_GPIO 0 +#define PORTM_PIN8_FUNMUX 1 +#define PORTM_PIN8_NORFL_D7 2 -#define PORTM_PIN6_GPIO 0 -#define PORTM_PIN6_FUNMUX 1 -#define PORTM_PIN6_NORFL_D9 2 +#define PORTM_PIN9_GPIO 0 +#define PORTM_PIN9_FUNMUX 1 +#define PORTM_PIN9_NORFL_D6 2 -#define PORTM_PIN7_GPIO 0 -#define PORTM_PIN7_FUNMUX 1 -#define PORTM_PIN7_NORFL_D8 2 +#define PORTM_PIN10_GPIO 0 +#define PORTM_PIN10_FUNMUX 1 +#define PORTM_PIN10_NORFL_D5 2 -#define PORTM_PIN8_GPIO 0 -#define PORTM_PIN8_FUNMUX 1 -#define PORTM_PIN8_NORFL_D7 2 +#define PORTM_PIN11_GPIO 0 +#define PORTM_PIN11_FUNMUX 1 +#define PORTM_PIN11_NORFL_D4 2 -#define PORTM_PIN9_GPIO 0 -#define PORTM_PIN9_FUNMUX 1 -#define PORTM_PIN9_NORFL_D6 2 +#define PORTM_PIN12_GPIO 0 +#define PORTM_PIN12_FUNMUX 1 +#define PORTM_PIN12_NORFL_D3 2 -#define PORTM_PIN10_GPIO 0 -#define PORTM_PIN10_FUNMUX 1 -#define PORTM_PIN10_NORFL_D5 2 +#define PORTM_PIN13_GPIO 0 +#define PORTM_PIN13_FUNMUX 1 +#define PORTM_PIN13_NORFL_D2 2 -#define PORTM_PIN11_GPIO 0 -#define PORTM_PIN11_FUNMUX 1 -#define PORTM_PIN11_NORFL_D4 2 +#define PORTM_PIN14_GPIO 0 +#define PORTM_PIN14_FUNMUX 1 +#define PORTM_PIN14_NORFL_D1 2 -#define PORTM_PIN12_GPIO 0 -#define PORTM_PIN12_FUNMUX 1 -#define PORTM_PIN12_NORFL_D3 2 +#define PORTM_PIN15_GPIO 0 +#define PORTM_PIN15_FUNMUX 1 +#define PORTM_PIN15_NORFL_D0 2 -#define PORTM_PIN13_GPIO 0 -#define PORTM_PIN13_FUNMUX 1 -#define PORTM_PIN13_NORFL_D2 2 +#define PORTM_PIN16_GPIO 0 +#define PORTM_PIN16_FUNMUX 1 +#define PORTM_PIN16_NORFL_OEN 2 -#define PORTM_PIN14_GPIO 0 -#define PORTM_PIN14_FUNMUX 1 -#define PORTM_PIN14_NORFL_D1 2 +#define PORTM_PIN17_GPIO 0 +#define PORTM_PIN17_FUNMUX 1 +#define PORTM_PIN17_NORFL_WEN 2 -#define PORTM_PIN15_GPIO 0 -#define PORTM_PIN15_FUNMUX 1 -#define PORTM_PIN15_NORFL_D0 2 +#define PORTM_PIN18_GPIO 0 +#define PORTM_PIN18_FUNMUX 1 +#define PORTM_PIN18_NORFL_CSN 2 -#define PORTM_PIN16_GPIO 0 -#define PORTM_PIN16_FUNMUX 1 -#define PORTM_PIN16_NORFL_OEN 2 +#define PORTM_PIN19_GPIO 0 +#define PORTM_PIN19_FUNMUX 1 +#define PORTM_PIN19_SDRAM_CSN 2 -#define PORTM_PIN17_GPIO 0 -#define PORTM_PIN17_FUNMUX 1 -#define PORTM_PIN17_NORFL_WEN 2 +#define PORTM_PIN20_GPIO 0 +#define PORTM_PIN20_FUNMUX 1 +#define PORTM_PIN20_SRAM_CSN 2 -#define PORTM_PIN18_GPIO 0 -#define PORTM_PIN18_FUNMUX 1 -#define PORTM_PIN18_NORFL_CSN 2 +#define PORTM_PIN21_GPIO 0 +#define PORTM_PIN21_FUNMUX 1 +#define PORTM_PIN21_SDRAM_CKE 2 -#define PORTM_PIN19_GPIO 0 -#define PORTM_PIN19_FUNMUX 1 -#define PORTM_PIN19_SDRAM_CSN 2 +#define PORTN_PIN0_GPIO 0 +#define PORTN_PIN0_FUNMUX 1 +#define PORTN_PIN0_LCD_D0 2 +#define PORTN_PIN0_ADC1_IN4 3 -#define PORTM_PIN20_GPIO 0 -#define PORTM_PIN20_FUNMUX 1 -#define PORTM_PIN20_SRAM_CSN 2 +#define PORTN_PIN1_GPIO 0 +#define PORTN_PIN1_FUNMUX 1 +#define PORTN_PIN1_LCD_D1 2 +#define PORTN_PIN1_ADC1_IN5 3 -#define PORTM_PIN21_GPIO 0 -#define PORTM_PIN21_FUNMUX 1 -#define PORTM_PIN21_SDRAM_CKE 2 +#define PORTN_PIN2_GPIO 0 +#define PORTN_PIN2_FUNMUX 1 +#define PORTN_PIN2_LCD_D2 2 +#define PORTN_PIN2_ADC1_IN6 3 +#define PORTN_PIN3_GPIO 0 +#define PORTN_PIN3_FUNMUX 1 +#define PORTN_PIN3_LCD_D3 2 -#define PORTN_PIN0_GPIO 0 -#define PORTN_PIN0_FUNMUX 1 -#define PORTN_PIN0_LCD_D0 2 -#define PORTN_PIN0_ADC1_IN4 3 +#define PORTN_PIN4_GPIO 0 +#define PORTN_PIN4_FUNMUX 1 +#define PORTN_PIN4_LCD_D4 2 -#define PORTN_PIN1_GPIO 0 -#define PORTN_PIN1_FUNMUX 1 -#define PORTN_PIN1_LCD_D1 2 -#define PORTN_PIN1_ADC1_IN5 3 +#define PORTN_PIN5_GPIO 0 +#define PORTN_PIN5_FUNMUX 1 +#define PORTN_PIN5_LCD_D5 2 -#define PORTN_PIN2_GPIO 0 -#define PORTN_PIN2_FUNMUX 1 -#define PORTN_PIN2_LCD_D2 2 -#define PORTN_PIN2_ADC1_IN6 3 +#define PORTN_PIN6_GPIO 0 +#define PORTN_PIN6_FUNMUX 1 +#define PORTN_PIN6_LCD_D6 2 -#define PORTN_PIN3_GPIO 0 -#define PORTN_PIN3_FUNMUX 1 -#define PORTN_PIN3_LCD_D3 2 +#define PORTN_PIN7_GPIO 0 +#define PORTN_PIN7_FUNMUX 1 +#define PORTN_PIN7_LCD_D7 2 -#define PORTN_PIN4_GPIO 0 -#define PORTN_PIN4_FUNMUX 1 -#define PORTN_PIN4_LCD_D4 2 +#define PORTN_PIN8_GPIO 0 +#define PORTN_PIN8_FUNMUX 1 +#define PORTN_PIN8_LCD_D8 2 -#define PORTN_PIN5_GPIO 0 -#define PORTN_PIN5_FUNMUX 1 -#define PORTN_PIN5_LCD_D5 2 +#define PORTN_PIN9_GPIO 0 +#define PORTN_PIN9_FUNMUX 1 +#define PORTN_PIN9_LCD_D9 2 -#define PORTN_PIN6_GPIO 0 -#define PORTN_PIN6_FUNMUX 1 -#define PORTN_PIN6_LCD_D6 2 +#define PORTN_PIN10_GPIO 0 +#define PORTN_PIN10_FUNMUX 1 +#define PORTN_PIN10_LCD_D10 2 -#define PORTN_PIN7_GPIO 0 -#define PORTN_PIN7_FUNMUX 1 -#define PORTN_PIN7_LCD_D7 2 +#define PORTN_PIN11_GPIO 0 +#define PORTN_PIN11_FUNMUX 1 +#define PORTN_PIN11_LCD_D11 2 -#define PORTN_PIN8_GPIO 0 -#define PORTN_PIN8_FUNMUX 1 -#define PORTN_PIN8_LCD_D8 2 +#define PORTN_PIN12_GPIO 0 +#define PORTN_PIN12_FUNMUX 1 +#define PORTN_PIN12_LCD_D12 2 -#define PORTN_PIN9_GPIO 0 -#define PORTN_PIN9_FUNMUX 1 -#define PORTN_PIN9_LCD_D9 2 +#define PORTN_PIN13_GPIO 0 +#define PORTN_PIN13_FUNMUX 1 +#define PORTN_PIN13_LCD_D13 2 -#define PORTN_PIN10_GPIO 0 -#define PORTN_PIN10_FUNMUX 1 -#define PORTN_PIN10_LCD_D10 2 +#define PORTN_PIN14_GPIO 0 +#define PORTN_PIN14_FUNMUX 1 +#define PORTN_PIN14_LCD_D14 2 -#define PORTN_PIN11_GPIO 0 -#define PORTN_PIN11_FUNMUX 1 -#define PORTN_PIN11_LCD_D11 2 +#define PORTN_PIN15_GPIO 0 +#define PORTN_PIN15_FUNMUX 1 +#define PORTN_PIN15_LCD_D15 2 -#define PORTN_PIN12_GPIO 0 -#define PORTN_PIN12_FUNMUX 1 -#define PORTN_PIN12_LCD_D12 2 +#define PORTN_PIN16_GPIO 0 +#define PORTN_PIN16_FUNMUX 1 +#define PORTN_PIN16_LCD_RD 2 +#define PORTN_PIN16_LCD_DOTCK 2 -#define PORTN_PIN13_GPIO 0 -#define PORTN_PIN13_FUNMUX 1 -#define PORTN_PIN13_LCD_D13 2 +#define PORTN_PIN17_GPIO 0 +#define PORTN_PIN17_FUNMUX 1 +#define PORTN_PIN17_LCD_CS 2 +#define PORTN_PIN17_LCD_VSYNC 2 -#define PORTN_PIN14_GPIO 0 -#define PORTN_PIN14_FUNMUX 1 -#define PORTN_PIN14_LCD_D14 2 +#define PORTN_PIN18_GPIO 0 +#define PORTN_PIN18_LCD_RS 2 +#define PORTN_PIN18_LCD_DATEN 2 //Data Enable -#define PORTN_PIN15_GPIO 0 -#define PORTN_PIN15_FUNMUX 1 -#define PORTN_PIN15_LCD_D15 2 +#define PORTN_PIN19_GPIO 0 +#define PORTN_PIN19_LCD_WR 2 +#define PORTN_PIN19_LCD_HSYNC 2 -#define PORTN_PIN16_GPIO 0 -#define PORTN_PIN16_FUNMUX 1 -#define PORTN_PIN16_LCD_RD 2 -#define PORTN_PIN16_LCD_DOTCK 2 +#define PORTP_PIN0_GPIO 0 +#define PORTP_PIN0_FUNMUX 1 +#define PORTP_PIN0_NORFL_A0 2 -#define PORTN_PIN17_GPIO 0 -#define PORTN_PIN17_FUNMUX 1 -#define PORTN_PIN17_LCD_CS 2 -#define PORTN_PIN17_LCD_VSYNC 2 +#define PORTP_PIN1_GPIO 0 +#define PORTP_PIN1_FUNMUX 1 +#define PORTP_PIN1_NORFL_A1 2 -#define PORTN_PIN18_GPIO 0 -#define PORTN_PIN18_LCD_RS 2 -#define PORTN_PIN18_LCD_DATEN 2 //Data Enable +#define PORTP_PIN2_GPIO 0 +#define PORTP_PIN2_FUNMUX 1 +#define PORTP_PIN2_NORFL_A2 2 +#define PORTP_PIN2_SD_D7 3 -#define PORTN_PIN19_GPIO 0 -#define PORTN_PIN19_LCD_WR 2 -#define PORTN_PIN19_LCD_HSYNC 2 +#define PORTP_PIN3_GPIO 0 +#define PORTP_PIN3_FUNMUX 1 +#define PORTP_PIN3_NORFL_A3 2 +#define PORTP_PIN3_SD_D6 3 +#define PORTP_PIN4_GPIO 0 +#define PORTP_PIN4_FUNMUX 1 +#define PORTP_PIN4_NORFL_A4 2 +#define PORTP_PIN4_SD_D5 3 -#define PORTP_PIN0_GPIO 0 -#define PORTP_PIN0_FUNMUX 1 -#define PORTP_PIN0_NORFL_A0 2 +#define PORTP_PIN5_GPIO 0 +#define PORTP_PIN5_FUNMUX 1 +#define PORTP_PIN5_NORFL_A5 2 +#define PORTP_PIN5_SD_D4 3 -#define PORTP_PIN1_GPIO 0 -#define PORTP_PIN1_FUNMUX 1 -#define PORTP_PIN1_NORFL_A1 2 +#define PORTP_PIN6_GPIO 0 +#define PORTP_PIN6_FUNMUX 1 +#define PORTP_PIN6_NORFL_A6 2 +#define PORTP_PIN6_SD_D3 3 -#define PORTP_PIN2_GPIO 0 -#define PORTP_PIN2_FUNMUX 1 -#define PORTP_PIN2_NORFL_A2 2 -#define PORTP_PIN2_SD_D7 3 +#define PORTP_PIN7_GPIO 0 +#define PORTP_PIN7_FUNMUX 1 +#define PORTP_PIN7_NORFL_A7 2 +#define PORTP_PIN7_SD_D2 3 -#define PORTP_PIN3_GPIO 0 -#define PORTP_PIN3_FUNMUX 1 -#define PORTP_PIN3_NORFL_A3 2 -#define PORTP_PIN3_SD_D6 3 +#define PORTP_PIN8_GPIO 0 +#define PORTP_PIN8_FUNMUX 1 +#define PORTP_PIN8_NORFL_A8 2 +#define PORTP_PIN8_SD_D1 3 -#define PORTP_PIN4_GPIO 0 -#define PORTP_PIN4_FUNMUX 1 -#define PORTP_PIN4_NORFL_A4 2 -#define PORTP_PIN4_SD_D5 3 +#define PORTP_PIN9_GPIO 0 +#define PORTP_PIN9_FUNMUX 1 +#define PORTP_PIN9_NORFL_A9 2 +#define PORTP_PIN9_SD_D0 3 -#define PORTP_PIN5_GPIO 0 -#define PORTP_PIN5_FUNMUX 1 -#define PORTP_PIN5_NORFL_A5 2 -#define PORTP_PIN5_SD_D4 3 +#define PORTP_PIN10_GPIO 0 +#define PORTP_PIN10_FUNMUX 1 +#define PORTP_PIN10_NORFL_A10 2 +#define PORTP_PIN10_SD_CMD 3 -#define PORTP_PIN6_GPIO 0 -#define PORTP_PIN6_FUNMUX 1 -#define PORTP_PIN6_NORFL_A6 2 -#define PORTP_PIN6_SD_D3 3 +#define PORTP_PIN11_GPIO 0 +#define PORTP_PIN11_FUNMUX 1 +#define PORTP_PIN11_NORFL_A11 2 +#define PORTP_PIN11_SD_CLK 3 -#define PORTP_PIN7_GPIO 0 -#define PORTP_PIN7_FUNMUX 1 -#define PORTP_PIN7_NORFL_A7 2 -#define PORTP_PIN7_SD_D2 3 +#define PORTP_PIN12_GPIO 0 +#define PORTP_PIN12_FUNMUX 1 +#define PORTP_PIN12_NORFL_A12 2 +#define PORTP_PIN12_SD_DETECT 3 -#define PORTP_PIN8_GPIO 0 -#define PORTP_PIN8_FUNMUX 1 -#define PORTP_PIN8_NORFL_A8 2 -#define PORTP_PIN8_SD_D1 3 +#define PORTP_PIN13_GPIO 0 +#define PORTP_PIN13_FUNMUX 1 +#define PORTP_PIN13_NORFL_A13 2 +#define PORTP_PIN13_SDRAM_CLK 2 -#define PORTP_PIN9_GPIO 0 -#define PORTP_PIN9_FUNMUX 1 -#define PORTP_PIN9_NORFL_A9 2 -#define PORTP_PIN9_SD_D0 3 +#define PORTP_PIN14_GPIO 0 +#define PORTP_PIN14_FUNMUX 1 +#define PORTP_PIN14_NORFL_A14 2 +#define PORTP_PIN14_SDRAM_CAS 2 -#define PORTP_PIN10_GPIO 0 -#define PORTP_PIN10_FUNMUX 1 -#define PORTP_PIN10_NORFL_A10 2 -#define PORTP_PIN10_SD_CMD 3 +#define PORTP_PIN15_GPIO 0 +#define PORTP_PIN15_FUNMUX 1 +#define PORTP_PIN15_NORFL_A15 2 +#define PORTP_PIN15_SDRAM_RAS 2 -#define PORTP_PIN11_GPIO 0 -#define PORTP_PIN11_FUNMUX 1 -#define PORTP_PIN11_NORFL_A11 2 -#define PORTP_PIN11_SD_CLK 3 +#define PORTP_PIN16_GPIO 0 +#define PORTP_PIN16_FUNMUX 1 +#define PORTP_PIN16_NORFL_A16 2 +#define PORTP_PIN16_SDRAM_LDQ 2 -#define PORTP_PIN12_GPIO 0 -#define PORTP_PIN12_FUNMUX 1 -#define PORTP_PIN12_NORFL_A12 2 -#define PORTP_PIN12_SD_DETECT 3 +#define PORTP_PIN17_GPIO 0 +#define PORTP_PIN17_FUNMUX 1 +#define PORTP_PIN17_NORFL_A17 2 +#define PORTP_PIN17_SDRAM_UDQ 2 -#define PORTP_PIN13_GPIO 0 -#define PORTP_PIN13_FUNMUX 1 -#define PORTP_PIN13_NORFL_A13 2 -#define PORTP_PIN13_SDRAM_CLK 2 +#define PORTP_PIN18_GPIO 0 +#define PORTP_PIN18_FUNMUX 1 +#define PORTP_PIN18_NORFL_A18 2 -#define PORTP_PIN14_GPIO 0 -#define PORTP_PIN14_FUNMUX 1 -#define PORTP_PIN14_NORFL_A14 2 -#define PORTP_PIN14_SDRAM_CAS 2 +#define PORTP_PIN19_GPIO 0 +#define PORTP_PIN19_FUNMUX 1 +#define PORTP_PIN19_NORFL_A19 2 -#define PORTP_PIN15_GPIO 0 -#define PORTP_PIN15_FUNMUX 1 -#define PORTP_PIN15_NORFL_A15 2 -#define PORTP_PIN15_SDRAM_RAS 2 +#define PORTP_PIN20_GPIO 0 +#define PORTP_PIN20_FUNMUX 1 +#define PORTP_PIN20_NORFL_A20 2 +#define PORTP_PIN20_SDRAM_BA0 2 -#define PORTP_PIN16_GPIO 0 -#define PORTP_PIN16_FUNMUX 1 -#define PORTP_PIN16_NORFL_A16 2 -#define PORTP_PIN16_SDRAM_LDQ 2 +#define PORTP_PIN21_GPIO 0 +#define PORTP_PIN21_FUNMUX 1 +#define PORTP_PIN21_NORFL_A21 2 +#define PORTP_PIN21_SDRAM_BA1 2 -#define PORTP_PIN17_GPIO 0 -#define PORTP_PIN17_FUNMUX 1 -#define PORTP_PIN17_NORFL_A17 2 -#define PORTP_PIN17_SDRAM_UDQ 2 +#define PORTP_PIN22_GPIO 0 +#define PORTP_PIN22_FUNMUX 1 +#define PORTP_PIN22_NORFL_A22 2 -#define PORTP_PIN18_GPIO 0 -#define PORTP_PIN18_FUNMUX 1 -#define PORTP_PIN18_NORFL_A18 2 +#define PORTP_PIN23_GPIO 0 +#define PORTP_PIN23_FUNMUX 1 +#define PORTP_PIN23_NORFL_A23 2 -#define PORTP_PIN19_GPIO 0 -#define PORTP_PIN19_FUNMUX 1 -#define PORTP_PIN19_NORFL_A19 2 - -#define PORTP_PIN20_GPIO 0 -#define PORTP_PIN20_FUNMUX 1 -#define PORTP_PIN20_NORFL_A20 2 -#define PORTP_PIN20_SDRAM_BA0 2 - -#define PORTP_PIN21_GPIO 0 -#define PORTP_PIN21_FUNMUX 1 -#define PORTP_PIN21_NORFL_A21 2 -#define PORTP_PIN21_SDRAM_BA1 2 - -#define PORTP_PIN22_GPIO 0 -#define PORTP_PIN22_FUNMUX 1 -#define PORTP_PIN22_NORFL_A22 2 - -#define PORTP_PIN23_GPIO 0 -#define PORTP_PIN23_FUNMUX 1 -#define PORTP_PIN23_NORFL_A23 2 - - - -/* ����궨���ȡֵȫ������ȷֵ�Ļ����ϡ���100��������������궨���ֵ���Ӷ�����⺯���ı�д*/ -/* ������Щֵ��ż��������ŵĹ���ȡֵ����PIN0��PIN2��... */ -#define FUNMUX0_UART0_RXD 100 -#define FUNMUX0_UART1_RXD 101 -#define FUNMUX0_UART2_RXD 102 -#define FUNMUX0_UART3_RXD 103 -#define FUNMUX0_I2C0_SCL 105 -#define FUNMUX0_I2C1_SCL 106 -#define FUNMUX0_PWM0A_OUT 107 -#define FUNMUX0_PWM2A_OUT 108 -#define FUNMUX0_PWM4A_OUT 109 -#define FUNMUX0_PWM0B_OUT 110 -#define FUNMUX0_PWM2B_OUT 111 -#define FUNMUX0_PWM4B_OUT 112 -#define FUNMUX0_PWM_BREAK 113 -#define FUNMUX0_TIMR0_IN 114 -#define FUNMUX0_TIMR2_IN 115 -#define FUNMUX0_CAN_RX 116 -#define FUNMUX0_SPI0_SSEL 117 -#define FUNMUX0_SPI0_MOSI 118 -#define FUNMUX0_SPI1_SSEL 119 -#define FUNMUX0_SPI1_MOSI 120 -#define FUNMUX0_UART0_CTS 121 -#define FUNMUX0_UART1_CTS 122 -#define FUNMUX0_UART2_CTS 123 -#define FUNMUX0_UART3_CTS 124 - -/* ������Щֵ������������ŵĹ���ȡֵ����PIN1��PIN3��... */ -#define FUNMUX1_UART0_TXD 100 -#define FUNMUX1_UART1_TXD 101 -#define FUNMUX1_UART2_TXD 102 -#define FUNMUX1_UART3_TXD 103 -#define FUNMUX1_I2C0_SDA 105 -#define FUNMUX1_I2C1_SDA 106 -#define FUNMUX1_PWM1A_OUT 107 -#define FUNMUX1_PWM3A_OUT 108 -#define FUNMUX1_PWM5A_OUT 109 -#define FUNMUX1_PWM1B_OUT 110 -#define FUNMUX1_PWM3B_OUT 111 -#define FUNMUX1_PWM5B_OUT 112 -#define FUNMUX1_PULSE_IN 113 -#define FUNMUX1_TIMR1_IN 114 -#define FUNMUX1_TIMR3_IN 115 -#define FUNMUX1_CAN_TX 116 -#define FUNMUX1_SPI0_SCLK 117 -#define FUNMUX1_SPI0_MISO 118 -#define FUNMUX1_SPI1_SCLK 119 -#define FUNMUX1_SPI1_MISO 120 -#define FUNMUX1_UART0_RTS 121 -#define FUNMUX1_UART1_RTS 122 -#define FUNMUX1_UART2_RTS 123 -#define FUNMUX1_UART3_RTS 124 +/* 下面宏定义的取值全部在正确值的基础上“加100”，以区分上面宏定义的值，从而方便库函数的编写*/ +/* 下面这些值是偶数编号引脚的功能取值，如PIN0、PIN2、... */ +#define FUNMUX0_UART0_RXD 100 +#define FUNMUX0_UART1_RXD 101 +#define FUNMUX0_UART2_RXD 102 +#define FUNMUX0_UART3_RXD 103 +#define FUNMUX0_I2C0_SCL 105 +#define FUNMUX0_I2C1_SCL 106 +#define FUNMUX0_PWM0A_OUT 107 +#define FUNMUX0_PWM2A_OUT 108 +#define FUNMUX0_PWM4A_OUT 109 +#define FUNMUX0_PWM0B_OUT 110 +#define FUNMUX0_PWM2B_OUT 111 +#define FUNMUX0_PWM4B_OUT 112 +#define FUNMUX0_PWM_BREAK 113 +#define FUNMUX0_TIMR0_IN 114 +#define FUNMUX0_TIMR2_IN 115 +#define FUNMUX0_CAN_RX 116 +#define FUNMUX0_SPI0_SSEL 117 +#define FUNMUX0_SPI0_MOSI 118 +#define FUNMUX0_SPI1_SSEL 119 +#define FUNMUX0_SPI1_MOSI 120 +#define FUNMUX0_UART0_CTS 121 +#define FUNMUX0_UART1_CTS 122 +#define FUNMUX0_UART2_CTS 123 +#define FUNMUX0_UART3_CTS 124 +/* 下面这些值是奇数编号引脚的功能取值，如PIN1、PIN3、... */ +#define FUNMUX1_UART0_TXD 100 +#define FUNMUX1_UART1_TXD 101 +#define FUNMUX1_UART2_TXD 102 +#define FUNMUX1_UART3_TXD 103 +#define FUNMUX1_I2C0_SDA 105 +#define FUNMUX1_I2C1_SDA 106 +#define FUNMUX1_PWM1A_OUT 107 +#define FUNMUX1_PWM3A_OUT 108 +#define FUNMUX1_PWM5A_OUT 109 +#define FUNMUX1_PWM1B_OUT 110 +#define FUNMUX1_PWM3B_OUT 111 +#define FUNMUX1_PWM5B_OUT 112 +#define FUNMUX1_PULSE_IN 113 +#define FUNMUX1_TIMR1_IN 114 +#define FUNMUX1_TIMR3_IN 115 +#define FUNMUX1_CAN_TX 116 +#define FUNMUX1_SPI0_SCLK 117 +#define FUNMUX1_SPI0_MISO 118 +#define FUNMUX1_SPI1_SCLK 119 +#define FUNMUX1_SPI1_MISO 120 +#define FUNMUX1_UART0_RTS 121 +#define FUNMUX1_UART1_RTS 122 +#define FUNMUX1_UART2_RTS 123 +#define FUNMUX1_UART3_RTS 124 #endif //__SWM320_PORT_H__ diff --git a/bsp/swm320-lq100/Libraries/SWM320_StdPeriph_Driver/SWM320_pwm.c b/bsp/swm320-lq100/Libraries/SWM320_StdPeriph_Driver/SWM320_pwm.c index 454d19e197..0d965e4792 100644 --- a/bsp/swm320-lq100/Libraries/SWM320_StdPeriph_Driver/SWM320_pwm.c +++ b/bsp/swm320-lq100/Libraries/SWM320_StdPeriph_Driver/SWM320_pwm.c @@ -24,7 +24,7 @@ /****************************************************************************************************************************************** * 函数名称: PWM_Init() * 功能说明: PWM初始化 -* 输 入: PWM_TypeDef * PWMx 指定要被设置的PWM，有效值包括PWM0、PWM1、PWM2、PWM3、PWM4、PWM5 +* 输 入: PWM_TypeDef * PWMx 指定要被设置的PWM，有效值包括PWM0、PWM1、PWM2、PWM3、PWM4、PWM5 * PWM_InitStructure * initStruct 包含PWM相关设定值的结构体 * 输 出: 无 * 注意事项: 无 @@ -101,9 +101,9 @@ void PWM_Init(PWM_TypeDef *PWMx, PWM_InitStructure *initStruct) /****************************************************************************************************************************************** * 函数名称: PWM_Start() * 功能说明: 启动PWM，开始PWM输出 -* 输 入: PWM_TypeDef * PWMx 指定要被设置的PWM，有效值包括PWM0、PWM1、PWM2、PWM3、PWM4、PWM5 -* uint32_t chA 0 通道A不启动 1 通道A启动 -* uint32_t chB 0 通道B不启动 1 通道B启动 +* 输 入: PWM_TypeDef * PWMx 指定要被设置的PWM，有效值包括PWM0、PWM1、PWM2、PWM3、PWM4、PWM5 +* uint32_t chA 0 通道A不启动 1 通道A启动 +* uint32_t chB 0 通道B不启动 1 通道B启动 * 输 出: 无 * 注意事项: 无 ******************************************************************************************************************************************/ @@ -140,9 +140,9 @@ void PWM_Start(PWM_TypeDef *PWMx, uint32_t chA, uint32_t chB) /****************************************************************************************************************************************** * 函数名称: PWM_Stop() * 功能说明: 关闭PWM，停止PWM输出 -* 输 入: PWM_TypeDef * PWMx 指定要被设置的PWM，有效值包括PWM0、PWM1、PWM2、PWM3、PWM4、PWM5 -* uint32_t chA 0 通道A不关闭 1 通道A关闭 -* uint32_t chB 0 通道B不关闭 1 通道B关闭 +* 输 入: PWM_TypeDef * PWMx 指定要被设置的PWM，有效值包括PWM0、PWM1、PWM2、PWM3、PWM4、PWM5 +* uint32_t chA 0 通道A不关闭 1 通道A关闭 +* uint32_t chB 0 通道B不关闭 1 通道B关闭 * 输 出: 无 * 注意事项: 无 ******************************************************************************************************************************************/ @@ -179,7 +179,7 @@ void PWM_Stop(PWM_TypeDef *PWMx, uint32_t chA, uint32_t chB) /****************************************************************************************************************************************** * 函数名称: PWM_SetCycle() * 功能说明: 设置周期 -* 输 入: PWM_TypeDef * PWMx 指定要被设置的PWM，有效值包括PWM0、PWM1、PWM2、PWM3、PWM4、PWM5 +* 输 入: PWM_TypeDef * PWMx 指定要被设置的PWM，有效值包括PWM0、PWM1、PWM2、PWM3、PWM4、PWM5 * uint32_t chn 选择要设置哪个通道，有效值：PWM_CH_A、PWM_CH_B * uint16_t cycle 要设定的周期值 * 输 出: 无 @@ -196,9 +196,9 @@ void PWM_SetCycle(PWM_TypeDef *PWMx, uint32_t chn, uint16_t cycle) /****************************************************************************************************************************************** * 函数名称: PWM_GetCycle() * 功能说明: 获取周期 -* 输 入: PWM_TypeDef * PWMx 指定要被设置的PWM，有效值包括PWM0、PWM1、PWM2、PWM3、PWM4、PWM5 +* 输 入: PWM_TypeDef * PWMx 指定要被设置的PWM，有效值包括PWM0、PWM1、PWM2、PWM3、PWM4、PWM5 * uint32_t chn 选择要查询哪个通道，有效值：PWM_CH_A、PWM_CH_B -* 输 出: uint16_t 获取到的周期值 +* 输 出: uint16_t 获取到的周期值 * 注意事项: 无 ******************************************************************************************************************************************/ uint16_t PWM_GetCycle(PWM_TypeDef *PWMx, uint32_t chn) @@ -216,7 +216,7 @@ uint16_t PWM_GetCycle(PWM_TypeDef *PWMx, uint32_t chn) /****************************************************************************************************************************************** * 函数名称: PWM_SetHDuty() * 功能说明: 设置高电平时长 -* 输 入: PWM_TypeDef * PWMx 指定要被设置的PWM，有效值包括PWM0、PWM1、PWM2、PWM3、PWM4、PWM5 +* 输 入: PWM_TypeDef * PWMx 指定要被设置的PWM，有效值包括PWM0、PWM1、PWM2、PWM3、PWM4、PWM5 * uint32_t chn 选择要设置哪个通道，有效值：PWM_CH_A、PWM_CH_B * uint16_t hduty 要设定的高电平时长 * 输 出: 无 @@ -233,9 +233,9 @@ void PWM_SetHDuty(PWM_TypeDef *PWMx, uint32_t chn, uint16_t hduty) /****************************************************************************************************************************************** * 函数名称: PWM_GetHDuty() * 功能说明: 获取高电平时长 -* 输 入: PWM_TypeDef * PWMx 指定要被设置的PWM，有效值包括PWM0、PWM1、PWM2、PWM3、PWM4、PWM5 +* 输 入: PWM_TypeDef * PWMx 指定要被设置的PWM，有效值包括PWM0、PWM1、PWM2、PWM3、PWM4、PWM5 * uint32_t chn 选择要查询哪个通道，有效值：PWM_CH_A、PWM_CH_B -* 输 出: uint16_t 获取到的高电平时长 +* 输 出: uint16_t 获取到的高电平时长 * 注意事项: 无 ******************************************************************************************************************************************/ uint16_t PWM_GetHDuty(PWM_TypeDef *PWMx, uint32_t chn) @@ -253,7 +253,7 @@ uint16_t PWM_GetHDuty(PWM_TypeDef *PWMx, uint32_t chn) /****************************************************************************************************************************************** * 函数名称: PWM_SetDeadzone() * 功能说明: 设置死区时长 -* 输 入: PWM_TypeDef * PWMx 指定要被设置的PWM，有效值包括PWM0、PWM1、PWM2、PWM3、PWM4、PWM5 +* 输 入: PWM_TypeDef * PWMx 指定要被设置的PWM，有效值包括PWM0、PWM1、PWM2、PWM3、PWM4、PWM5 * uint32_t chn 选择要设置哪个通道，有效值：PWM_CH_A、PWM_CH_B * uint8_t deadzone 要设定的死区时长 * 输 出: 无 @@ -270,9 +270,9 @@ void PWM_SetDeadzone(PWM_TypeDef *PWMx, uint32_t chn, uint8_t deadzone) /****************************************************************************************************************************************** * 函数名称: PWM_GetDeadzone() * 功能说明: 获取死区时长 -* 输 入: PWM_TypeDef * PWMx 指定要被设置的PWM，有效值包括PWM0、PWM1、PWM2、PWM3、PWM4、PWM5 +* 输 入: PWM_TypeDef * PWMx 指定要被设置的PWM，有效值包括PWM0、PWM1、PWM2、PWM3、PWM4、PWM5 * uint32_t chn 选择要查询哪个通道，有效值：PWM_CH_A、PWM_CH_B -* 输 出: uint8_t 获取到的死区时长 +* 输 出: uint8_t 获取到的死区时长 * 注意事项: 无 ******************************************************************************************************************************************/ uint8_t PWM_GetDeadzone(PWM_TypeDef *PWMx, uint32_t chn) @@ -290,7 +290,7 @@ uint8_t PWM_GetDeadzone(PWM_TypeDef *PWMx, uint32_t chn) /****************************************************************************************************************************************** * 函数名称: PWM_IntNCycleEn() * 功能说明: 新周期开始中断使能 -* 输 入: PWM_TypeDef * PWMx 指定要被设置的PWM，有效值包括PWM0、PWM1、PWM2、PWM3、PWM4、PWM5 +* 输 入: PWM_TypeDef * PWMx 指定要被设置的PWM，有效值包括PWM0、PWM1、PWM2、PWM3、PWM4、PWM5 * uint32_t chn 选择要设置哪个通道，有效值：PWM_CH_A、PWM_CH_B * 输 出: 无 * 注意事项: 无 @@ -346,7 +346,7 @@ void PWM_IntNCycleEn(PWM_TypeDef *PWMx, uint32_t chn) /****************************************************************************************************************************************** * 函数名称: PWM_IntNCycleDis() * 功能说明: 新周期开始中断禁能 -* 输 入: PWM_TypeDef * PWMx 指定要被设置的PWM，有效值包括PWM0、PWM1、PWM2、PWM3、PWM4、PWM5 +* 输 入: PWM_TypeDef * PWMx 指定要被设置的PWM，有效值包括PWM0、PWM1、PWM2、PWM3、PWM4、PWM5 * uint32_t chn 选择要设置哪个通道，有效值：PWM_CH_A、PWM_CH_B * 输 出: 无 * 注意事项: 无 @@ -402,7 +402,7 @@ void PWM_IntNCycleDis(PWM_TypeDef *PWMx, uint32_t chn) /****************************************************************************************************************************************** * 函数名称: PWM_IntNCycleClr() * 功能说明: 新周期开始中断标志清除 -* 输 入: PWM_TypeDef * PWMx 指定要被设置的PWM，有效值包括PWM0、PWM1、PWM2、PWM3、PWM4、PWM5 +* 输 入: PWM_TypeDef * PWMx 指定要被设置的PWM，有效值包括PWM0、PWM1、PWM2、PWM3、PWM4、PWM5 * uint32_t chn 选择要设置哪个通道，有效值：PWM_CH_A、PWM_CH_B * 输 出: 无 * 注意事项: 无 @@ -458,9 +458,9 @@ void PWM_IntNCycleClr(PWM_TypeDef *PWMx, uint32_t chn) /****************************************************************************************************************************************** * 函数名称: PWM_IntNCycleStat() * 功能说明: 新周期开始中断是否发生 -* 输 入: PWM_TypeDef * PWMx 指定要被设置的PWM，有效值包括PWM0、PWM1、PWM2、PWM3、PWM4、PWM5 +* 输 入: PWM_TypeDef * PWMx 指定要被设置的PWM，有效值包括PWM0、PWM1、PWM2、PWM3、PWM4、PWM5 * uint32_t chn 选择要设置哪个通道，有效值：PWM_CH_A、PWM_CH_B -* 输 出: uint32_t 1 新周期开始中断已发生 0 新周期开始中断未发生 +* 输 出: uint32_t 1 新周期开始中断已发生 0 新周期开始中断未发生 * 注意事项: 无 ******************************************************************************************************************************************/ uint32_t PWM_IntNCycleStat(PWM_TypeDef *PWMx, uint32_t chn) @@ -518,7 +518,7 @@ uint32_t PWM_IntNCycleStat(PWM_TypeDef *PWMx, uint32_t chn) /****************************************************************************************************************************************** * 函数名称: PWM_IntHEndEn() * 功能说明: 高电平结束中断使能 -* 输 入: PWM_TypeDef * PWMx 指定要被设置的PWM，有效值包括PWM0、PWM1、PWM2、PWM3、PWM4、PWM5 +* 输 入: PWM_TypeDef * PWMx 指定要被设置的PWM，有效值包括PWM0、PWM1、PWM2、PWM3、PWM4、PWM5 * uint32_t chn 选择要设置哪个通道，有效值：PWM_CH_A、PWM_CH_B * 输 出: 无 * 注意事项: 无 @@ -574,7 +574,7 @@ void PWM_IntHEndEn(PWM_TypeDef *PWMx, uint32_t chn) /****************************************************************************************************************************************** * 函数名称: PWM_IntHEndDis() * 功能说明: 高电平结束中断禁能 -* 输 入: PWM_TypeDef * PWMx 指定要被设置的PWM，有效值包括PWM0、PWM1、PWM2、PWM3、PWM4、PWM5 +* 输 入: PWM_TypeDef * PWMx 指定要被设置的PWM，有效值包括PWM0、PWM1、PWM2、PWM3、PWM4、PWM5 * uint32_t chn 选择要设置哪个通道，有效值：PWM_CH_A、PWM_CH_B * 输 出: 无 * 注意事项: 无 @@ -630,7 +630,7 @@ void PWM_IntHEndDis(PWM_TypeDef *PWMx, uint32_t chn) /****************************************************************************************************************************************** * 函数名称: PWM_IntHEndClr() * 功能说明: 高电平结束中断标志清除 -* 输 入: PWM_TypeDef * PWMx 指定要被设置的PWM，有效值包括PWM0、PWM1、PWM2、PWM3、PWM4、PWM5 +* 输 入: PWM_TypeDef * PWMx 指定要被设置的PWM，有效值包括PWM0、PWM1、PWM2、PWM3、PWM4、PWM5 * uint32_t chn 选择要设置哪个通道，有效值：PWM_CH_A、PWM_CH_B * 输 出: 无 * 注意事项: 无 @@ -686,9 +686,9 @@ void PWM_IntHEndClr(PWM_TypeDef *PWMx, uint32_t chn) /****************************************************************************************************************************************** * 函数名称: PWM_IntHEndStat() * 功能说明: 高电平结束中断是否发生 -* 输 入: PWM_TypeDef * PWMx 指定要被设置的PWM，有效值包括PWM0、PWM1、PWM2、PWM3、PWM4、PWM5 +* 输 入: PWM_TypeDef * PWMx 指定要被设置的PWM，有效值包括PWM0、PWM1、PWM2、PWM3、PWM4、PWM5 * uint32_t chn 选择要设置哪个通道，有效值：PWM_CH_A、PWM_CH_B -* 输 出: uint32_t 1 高电平结束中断已发生 0 高电平结束中断未发生 +* 输 出: uint32_t 1 高电平结束中断已发生 0 高电平结束中断未发生 * 注意事项: 无 ******************************************************************************************************************************************/ uint32_t PWM_IntHEndStat(PWM_TypeDef *PWMx, uint32_t chn) diff --git a/bsp/swm320-lq100/Libraries/SWM320_StdPeriph_Driver/SWM320_rtc.c b/bsp/swm320-lq100/Libraries/SWM320_StdPeriph_Driver/SWM320_rtc.c index 60958799ed..b2cb77a5f3 100644 --- a/bsp/swm320-lq100/Libraries/SWM320_StdPeriph_Driver/SWM320_rtc.c +++ b/bsp/swm320-lq100/Libraries/SWM320_StdPeriph_Driver/SWM320_rtc.c @@ -1,10 +1,10 @@ /****************************************************************************************************************************************** -* �ļ�����: SWM320_rtc.c -* ����˵��: SWM320��Ƭ����RTC������ -* ����֧��: http://www.synwit.com.cn/e/tool/gbook/?bid=1 -* ע������: -* �汾����: V1.1.0 2017��10��25�� -* ������¼: +* 文件名称: SWM320_rtc.c +* 功能说明: SWM320单片机的RTC驱动库 +* 技术支持: http://www.synwit.com.cn/e/tool/gbook/?bid=1 +* 注意事项: +* 版本日期: V1.1.0 2017年10月25日 +* 升级记录: * * ******************************************************************************************************************************************* @@ -21,39 +21,39 @@ #include "SWM320.h" #include "SWM320_rtc.h" - static uint32_t calcWeekDay(uint32_t year, uint32_t month, uint32_t date); /****************************************************************************************************************************************** -* ��������: RTC_Init() -* ����˵��: RTC��ʼ�� -* �� ��: RTC_TypeDef * RTCx ָ��Ҫ�����õ�RTC����Чֵ����RTC -* RTC_InitStructure * initStruct ����RTC����趨ֵ�Ľṹ�� -* �� ��: �� -* ע������: �� +* 函数名称: RTC_Init() +* 功能说明: RTC初始化 +* 输 入: RTC_TypeDef * RTCx 指定要被设置的RTC，有效值包括RTC +* RTC_InitStructure * initStruct 包含RTC相关设定值的结构体 +* 输 出: 无 +* 注意事项: 无 ******************************************************************************************************************************************/ void RTC_Init(RTC_TypeDef *RTCx, RTC_InitStructure *initStruct) { SYS->CLKEN |= (1 << SYS_CLKEN_RTCBKP_Pos); - SYS->LRCCR &= ~(1 << SYS_LRCCR_OFF_Pos); //RTCʹ��32KHz RCʱ�� + SYS->LRCCR &= ~(1 << SYS_LRCCR_OFF_Pos); //RTC使用32KHz RC时钟 SYS->CLKEN |= (1 << SYS_CLKEN_RTC_Pos) | ((uint32_t)1 << SYS_CLKEN_ALIVE_Pos); RTC_Stop(RTCx); - while (RTCx->CFGABLE == 0); + while (RTCx->CFGABLE == 0) + ; RTCx->MINSEC = (initStruct->Second << RTC_MINSEC_SEC_Pos) | (initStruct->Minute << RTC_MINSEC_MIN_Pos); RTCx->DATHUR = (initStruct->Hour << RTC_DATHUR_HOUR_Pos) | - ((initStruct->Date - 1) << RTC_DATHUR_DATE_Pos); + (initStruct->Date << RTC_DATHUR_DATE_Pos); RTCx->MONDAY = (calcWeekDay(initStruct->Year, initStruct->Month, initStruct->Date) << RTC_MONDAY_DAY_Pos) | - ((initStruct->Month - 1) << RTC_MONDAY_MON_Pos); + (initStruct->Month << RTC_MONDAY_MON_Pos); - RTCx->YEAR = initStruct->Year - 1901; + RTCx->YEAR = initStruct->Year; RTCx->LOAD = 1 << RTC_LOAD_TIME_Pos; @@ -72,11 +72,11 @@ void RTC_Init(RTC_TypeDef *RTCx, RTC_InitStructure *initStruct) } /****************************************************************************************************************************************** -* ��������: RTC_Start() -* ����˵��: ����RTC -* �� ��: RTC_TypeDef * RTCx ָ��Ҫ�����õ�RTC����ȡֵ����RTC -* �� ��: �� -* ע������: �� +* 函数名称: RTC_Start() +* 功能说明: 启动RTC +* 输 入: RTC_TypeDef * RTCx 指定要被设置的RTC，可取值包括RTC +* 输 出: 无 +* 注意事项: 无 ******************************************************************************************************************************************/ void RTC_Start(RTC_TypeDef *RTCx) { @@ -84,11 +84,11 @@ void RTC_Start(RTC_TypeDef *RTCx) } /****************************************************************************************************************************************** -* ��������: RTC_Stop() -* ����˵��: ֹͣRTC -* �� ��: RTC_TypeDef * RTCx ָ��Ҫ�����õ�RTC����ȡֵ����RTC -* �� ��: �� -* ע������: �� +* 函数名称: RTC_Stop() +* 功能说明: 停止RTC +* 输 入: RTC_TypeDef * RTCx 指定要被设置的RTC，可取值包括RTC +* 输 出: 无 +* 注意事项: 无 ******************************************************************************************************************************************/ void RTC_Stop(RTC_TypeDef *RTCx) { @@ -96,18 +96,18 @@ void RTC_Stop(RTC_TypeDef *RTCx) } /****************************************************************************************************************************************** -* ��������: RTC_GetDateTime() -* ����˵��: ��ȡ��ǰ��ʱ������� -* �� ��: RTC_TypeDef * RTCx ָ��Ҫ�����õ�RTC����Чֵ����RTC -* RTC_DateTime * dateTime ��ȡ����ʱ�䡢����ֵ�����ָ��ָ��Ľṹ�� -* �� ��: �� -* ע������: �� +* 函数名称: RTC_GetDateTime() +* 功能说明: 获取当前的时间和日期 +* 输 入: RTC_TypeDef * RTCx 指定要被设置的RTC，有效值包括RTC +* RTC_DateTime * dateTime 获取到的时间、日期值存入此指针指向的结构体 +* 输 出: 无 +* 注意事项: 无 ******************************************************************************************************************************************/ void RTC_GetDateTime(RTC_TypeDef *RTCx, RTC_DateTime *dateTime) { - dateTime->Year = RTCx->YEAR + 1901; - dateTime->Month = ((RTCx->MONDAY & RTC_MONDAY_MON_Msk) >> RTC_MONDAY_MON_Pos) + 1; - dateTime->Date = ((RTCx->DATHUR & RTC_DATHUR_DATE_Msk) >> RTC_DATHUR_DATE_Pos) + 1; + dateTime->Year = RTCx->YEAR; + dateTime->Month = (RTCx->MONDAY & RTC_MONDAY_MON_Msk) >> RTC_MONDAY_MON_Pos; + dateTime->Date = (RTCx->DATHUR & RTC_DATHUR_DATE_Msk) >> RTC_DATHUR_DATE_Pos; dateTime->Day = 1 << ((RTCx->MONDAY & RTC_MONDAY_DAY_Msk) >> RTC_MONDAY_DAY_Pos); dateTime->Hour = (RTCx->DATHUR & RTC_DATHUR_HOUR_Msk) >> RTC_DATHUR_HOUR_Pos; dateTime->Minute = (RTCx->MINSEC & RTC_MINSEC_MIN_Msk) >> RTC_MINSEC_MIN_Pos; @@ -115,16 +115,17 @@ void RTC_GetDateTime(RTC_TypeDef *RTCx, RTC_DateTime *dateTime) } /****************************************************************************************************************************************** -* ��������: RTC_AlarmSetup() -* ����˵��: RTC�����趨 -* �� ��: RTC_TypeDef * RTCx ָ��Ҫ�����õ�RTC����Чֵ����RTC -* RTC_AlarmStructure * alarmStruct ����RTC�����趨ֵ�Ľṹ�� -* �� ��: �� -* ע������: �� +* 函数名称: RTC_AlarmSetup() +* 功能说明: RTC闹钟设定 +* 输 入: RTC_TypeDef * RTCx 指定要被设置的RTC，有效值包括RTC +* RTC_AlarmStructure * alarmStruct 包含RTC闹钟设定值的结构体 +* 输 出: 无 +* 注意事项: 无 ******************************************************************************************************************************************/ void RTC_AlarmSetup(RTC_TypeDef *RTCx, RTC_AlarmStructure *alarmStruct) { - while (RTCx->CFGABLE == 0); + while (RTCx->CFGABLE == 0) + ; RTCx->MINSECAL = (alarmStruct->Second << RTC_MINSECAL_SEC_Pos) | (alarmStruct->Minute << RTC_MINSECAL_MIN_Pos); @@ -133,51 +134,56 @@ void RTC_AlarmSetup(RTC_TypeDef *RTCx, RTC_AlarmStructure *alarmStruct) (alarmStruct->Days << RTC_DAYHURAL_SUN_Pos); RTCx->LOAD = 1 << RTC_LOAD_ALARM_Pos; - while (RTCx->LOAD & RTC_LOAD_ALARM_Msk); + while (RTCx->LOAD & RTC_LOAD_ALARM_Msk) + ; RTCx->IF = (1 << RTC_IF_ALARM_Pos); RTCx->IE &= ~RTC_IE_ALARM_Msk; RTCx->IE |= (alarmStruct->AlarmIEn << RTC_IE_ALARM_Pos); - if (alarmStruct->AlarmIEn) NVIC_EnableIRQ(RTC_IRQn); + if (alarmStruct->AlarmIEn) + NVIC_EnableIRQ(RTC_IRQn); } /****************************************************************************************************************************************** -* ��������: calcWeekDay() -* ����˵��: ����ָ���ꡢ�¡��������ڼ� -* �� ��: uint32_t year �� -* uint32_t month �� -* uint32_t date �� -* �� ��: uint32_t 0 ������ 1 ����һ ... ... 6 ������ -* ע������: �� +* 函数名称: calcWeekDay() +* 功能说明: 计算指定年、月、日是星期几 +* 输 入: uint32_t year 年 +* uint32_t month 月 +* uint32_t date 日 +* 输 出: uint32_t 0 星期日 1 星期一 ... ... 6 星期六 +* 注意事项: 无 ******************************************************************************************************************************************/ static uint32_t calcWeekDay(uint32_t year, uint32_t month, uint32_t date) { uint32_t i, cnt = 0; const uint32_t daysOfMonth[13] = {0, 31, 28, 31, 30, 31, 30, 31, 31, 30, 31, 30, 31}; - for (i = 1; i < month; i++) cnt += daysOfMonth[i]; + for (i = 1; i < month; i++) + cnt += daysOfMonth[i]; cnt += date; - if ((year % 4 == 0) && ((year % 100 != 0) || (year % 400 == 0)) && (month >= 3)) cnt += 1; + if ((year % 4 == 0) && ((year % 100 != 0) || (year % 400 == 0)) && (month >= 3)) + cnt += 1; cnt += (year - 1901) * 365; for (i = 1901; i < year; i++) { - if ((i % 4 == 0) && ((i % 100 != 0) || (i % 400 == 0))) cnt += 1; + if ((i % 4 == 0) && ((i % 100 != 0) || (i % 400 == 0))) + cnt += 1; } return (cnt + 1) % 7; } /****************************************************************************************************************************************** -* ��������: RTC_IntSecondEn() -* ����˵��: ���ж�ʹ�� -* �� ��: RTC_TypeDef * RTCx ָ��Ҫ�����õ�RTC����ȡֵ����RTC -* �� ��: �� -* ע������: �� +* 函数名称: RTC_IntSecondEn() +* 功能说明: 秒中断使能 +* 输 入: RTC_TypeDef * RTCx 指定要被设置的RTC，可取值包括RTC +* 输 出: 无 +* 注意事项: 无 ******************************************************************************************************************************************/ void RTC_IntSecondEn(RTC_TypeDef *RTCx) { @@ -185,11 +191,11 @@ void RTC_IntSecondEn(RTC_TypeDef *RTCx) } /****************************************************************************************************************************************** -* ��������: RTC_IntSecondDis() -* ����˵��: ���жϽ�ֹ -* �� ��: RTC_TypeDef * RTCx ָ��Ҫ�����õ�RTC����ȡֵ����RTC -* �� ��: �� -* ע������: �� +* 函数名称: RTC_IntSecondDis() +* 功能说明: 秒中断禁止 +* 输 入: RTC_TypeDef * RTCx 指定要被设置的RTC，可取值包括RTC +* 输 出: 无 +* 注意事项: 无 ******************************************************************************************************************************************/ void RTC_IntSecondDis(RTC_TypeDef *RTCx) { @@ -197,11 +203,11 @@ void RTC_IntSecondDis(RTC_TypeDef *RTCx) } /****************************************************************************************************************************************** -* ��������: RTC_IntSecondClr() -* ����˵��: ���жϱ�־��� -* �� ��: RTC_TypeDef * RTCx ָ��Ҫ�����õ�RTC����ȡֵ����RTC -* �� ��: �� -* ע������: �� +* 函数名称: RTC_IntSecondClr() +* 功能说明: 秒中断标志清除 +* 输 入: RTC_TypeDef * RTCx 指定要被设置的RTC，可取值包括RTC +* 输 出: 无 +* 注意事项: 无 ******************************************************************************************************************************************/ void RTC_IntSecondClr(RTC_TypeDef *RTCx) { @@ -209,11 +215,11 @@ void RTC_IntSecondClr(RTC_TypeDef *RTCx) } /****************************************************************************************************************************************** -* ��������: RTC_IntSecondStat() -* ����˵��: ���ж�״̬ -* �� ��: RTC_TypeDef * RTCx ָ��Ҫ�����õ�RTC����ȡֵ����RTC -* �� ��: uint32_t 1 ���жϷ��� 0 ���ж�δ���� -* ע������: �� +* 函数名称: RTC_IntSecondStat() +* 功能说明: 秒中断状态 +* 输 入: RTC_TypeDef * RTCx 指定要被设置的RTC，可取值包括RTC +* 输 出: uint32_t 1 秒中断发生 0 秒中断未发生 +* 注意事项: 无 ******************************************************************************************************************************************/ uint32_t RTC_IntSecondStat(RTC_TypeDef *RTCx) { @@ -221,11 +227,11 @@ uint32_t RTC_IntSecondStat(RTC_TypeDef *RTCx) } /****************************************************************************************************************************************** -* ��������: RTC_IntMinuteEn() -* ����˵��: ���ж�ʹ�� -* �� ��: RTC_TypeDef * RTCx ָ��Ҫ�����õ�RTC����ȡֵ����RTC -* �� ��: �� -* ע������: �� +* 函数名称: RTC_IntMinuteEn() +* 功能说明: 分中断使能 +* 输 入: RTC_TypeDef * RTCx 指定要被设置的RTC，可取值包括RTC +* 输 出: 无 +* 注意事项: 无 ******************************************************************************************************************************************/ void RTC_IntMinuteEn(RTC_TypeDef *RTCx) { @@ -233,11 +239,11 @@ void RTC_IntMinuteEn(RTC_TypeDef *RTCx) } /****************************************************************************************************************************************** -* ��������: RTC_IntMinuteDis() -* ����˵��: ���жϽ�ֹ -* �� ��: RTC_TypeDef * RTCx ָ��Ҫ�����õ�RTC����ȡֵ����RTC -* �� ��: �� -* ע������: �� +* 函数名称: RTC_IntMinuteDis() +* 功能说明: 分中断禁止 +* 输 入: RTC_TypeDef * RTCx 指定要被设置的RTC，可取值包括RTC +* 输 出: 无 +* 注意事项: 无 ******************************************************************************************************************************************/ void RTC_IntMinuteDis(RTC_TypeDef *RTCx) { @@ -245,11 +251,11 @@ void RTC_IntMinuteDis(RTC_TypeDef *RTCx) } /****************************************************************************************************************************************** -* ��������: RTC_IntMinuteClr() -* ����˵��: ���жϱ�־��� -* �� ��: RTC_TypeDef * RTCx ָ��Ҫ�����õ�RTC����ȡֵ����RTC -* �� ��: �� -* ע������: �� +* 函数名称: RTC_IntMinuteClr() +* 功能说明: 分中断标志清除 +* 输 入: RTC_TypeDef * RTCx 指定要被设置的RTC，可取值包括RTC +* 输 出: 无 +* 注意事项: 无 ******************************************************************************************************************************************/ void RTC_IntMinuteClr(RTC_TypeDef *RTCx) { @@ -257,11 +263,11 @@ void RTC_IntMinuteClr(RTC_TypeDef *RTCx) } /****************************************************************************************************************************************** -* ��������: RTC_IntMinuteStat() -* ����˵��: ���ж�״̬ -* �� ��: RTC_TypeDef * RTCx ָ��Ҫ�����õ�RTC����ȡֵ����RTC -* �� ��: uint32_t 1 ���жϷ��� 0 ���ж�δ���� -* ע������: �� +* 函数名称: RTC_IntMinuteStat() +* 功能说明: 分中断状态 +* 输 入: RTC_TypeDef * RTCx 指定要被设置的RTC，可取值包括RTC +* 输 出: uint32_t 1 分中断发生 0 分中断未发生 +* 注意事项: 无 ******************************************************************************************************************************************/ uint32_t RTC_IntMinuteStat(RTC_TypeDef *RTCx) { @@ -269,11 +275,11 @@ uint32_t RTC_IntMinuteStat(RTC_TypeDef *RTCx) } /****************************************************************************************************************************************** -* ��������: RTC_IntHourEn() -* ����˵��: ʱ�ж�ʹ�� -* �� ��: RTC_TypeDef * RTCx ָ��Ҫ�����õ�RTC����ȡֵ����RTC -* �� ��: �� -* ע������: �� +* 函数名称: RTC_IntHourEn() +* 功能说明: 时中断使能 +* 输 入: RTC_TypeDef * RTCx 指定要被设置的RTC，可取值包括RTC +* 输 出: 无 +* 注意事项: 无 ******************************************************************************************************************************************/ void RTC_IntHourEn(RTC_TypeDef *RTCx) { @@ -281,11 +287,11 @@ void RTC_IntHourEn(RTC_TypeDef *RTCx) } /****************************************************************************************************************************************** -* ��������: RTC_IntHourDis() -* ����˵��: ʱ�жϽ�ֹ -* �� ��: RTC_TypeDef * RTCx ָ��Ҫ�����õ�RTC����ȡֵ����RTC -* �� ��: �� -* ע������: �� +* 函数名称: RTC_IntHourDis() +* 功能说明: 时中断禁止 +* 输 入: RTC_TypeDef * RTCx 指定要被设置的RTC，可取值包括RTC +* 输 出: 无 +* 注意事项: 无 ******************************************************************************************************************************************/ void RTC_IntHourDis(RTC_TypeDef *RTCx) { @@ -293,11 +299,11 @@ void RTC_IntHourDis(RTC_TypeDef *RTCx) } /****************************************************************************************************************************************** -* ��������: RTC_IntHourClr() -* ����˵��: ʱ�жϱ�־��� -* �� ��: RTC_TypeDef * RTCx ָ��Ҫ�����õ�RTC����ȡֵ����RTC -* �� ��: �� -* ע������: �� +* 函数名称: RTC_IntHourClr() +* 功能说明: 时中断标志清除 +* 输 入: RTC_TypeDef * RTCx 指定要被设置的RTC，可取值包括RTC +* 输 出: 无 +* 注意事项: 无 ******************************************************************************************************************************************/ void RTC_IntHourClr(RTC_TypeDef *RTCx) { @@ -305,11 +311,11 @@ void RTC_IntHourClr(RTC_TypeDef *RTCx) } /****************************************************************************************************************************************** -* ��������: RTC_IntHourStat() -* ����˵��: ʱ�ж�״̬ -* �� ��: RTC_TypeDef * RTCx ָ��Ҫ�����õ�RTC����ȡֵ����RTC -* �� ��: uint32_t 1 ʱ�жϷ��� 0 ʱ�ж�δ���� -* ע������: �� +* 函数名称: RTC_IntHourStat() +* 功能说明: 时中断状态 +* 输 入: RTC_TypeDef * RTCx 指定要被设置的RTC，可取值包括RTC +* 输 出: uint32_t 1 时中断发生 0 时中断未发生 +* 注意事项: 无 ******************************************************************************************************************************************/ uint32_t RTC_IntHourStat(RTC_TypeDef *RTCx) { @@ -317,11 +323,11 @@ uint32_t RTC_IntHourStat(RTC_TypeDef *RTCx) } /****************************************************************************************************************************************** -* ��������: RTC_IntDateEn() -* ����˵��: ���ж�ʹ�� -* �� ��: RTC_TypeDef * RTCx ָ��Ҫ�����õ�RTC����ȡֵ����RTC -* �� ��: �� -* ע������: �� +* 函数名称: RTC_IntDateEn() +* 功能说明: 日中断使能 +* 输 入: RTC_TypeDef * RTCx 指定要被设置的RTC，可取值包括RTC +* 输 出: 无 +* 注意事项: 无 ******************************************************************************************************************************************/ void RTC_IntDateEn(RTC_TypeDef *RTCx) { @@ -329,11 +335,11 @@ void RTC_IntDateEn(RTC_TypeDef *RTCx) } /****************************************************************************************************************************************** -* ��������: RTC_IntDateDis() -* ����˵��: ���жϽ�ֹ -* �� ��: RTC_TypeDef * RTCx ָ��Ҫ�����õ�RTC����ȡֵ����RTC -* �� ��: �� -* ע������: �� +* 函数名称: RTC_IntDateDis() +* 功能说明: 日中断禁止 +* 输 入: RTC_TypeDef * RTCx 指定要被设置的RTC，可取值包括RTC +* 输 出: 无 +* 注意事项: 无 ******************************************************************************************************************************************/ void RTC_IntDateDis(RTC_TypeDef *RTCx) { @@ -341,11 +347,11 @@ void RTC_IntDateDis(RTC_TypeDef *RTCx) } /****************************************************************************************************************************************** -* ��������: RTC_IntDateClr() -* ����˵��: ���жϱ�־��� -* �� ��: RTC_TypeDef * RTCx ָ��Ҫ�����õ�RTC����ȡֵ����RTC -* �� ��: �� -* ע������: �� +* 函数名称: RTC_IntDateClr() +* 功能说明: 日中断标志清除 +* 输 入: RTC_TypeDef * RTCx 指定要被设置的RTC，可取值包括RTC +* 输 出: 无 +* 注意事项: 无 ******************************************************************************************************************************************/ void RTC_IntDateClr(RTC_TypeDef *RTCx) { @@ -353,11 +359,11 @@ void RTC_IntDateClr(RTC_TypeDef *RTCx) } /****************************************************************************************************************************************** -* ��������: RTC_IntDateStat() -* ����˵��: ���ж�״̬ -* �� ��: RTC_TypeDef * RTCx ָ��Ҫ�����õ�RTC����ȡֵ����RTC -* �� ��: uint32_t 1 ���жϷ��� 0 ���ж�δ���� -* ע������: �� +* 函数名称: RTC_IntDateStat() +* 功能说明: 日中断状态 +* 输 入: RTC_TypeDef * RTCx 指定要被设置的RTC，可取值包括RTC +* 输 出: uint32_t 1 日中断发生 0 日中断未发生 +* 注意事项: 无 ******************************************************************************************************************************************/ uint32_t RTC_IntDateStat(RTC_TypeDef *RTCx) { @@ -365,11 +371,11 @@ uint32_t RTC_IntDateStat(RTC_TypeDef *RTCx) } /****************************************************************************************************************************************** -* ��������: RTC_IntAlarmEn() -* ����˵��: �����ж�ʹ�� -* �� ��: RTC_TypeDef * RTCx ָ��Ҫ�����õ�RTC����ȡֵ����RTC -* �� ��: �� -* ע������: �� +* 函数名称: RTC_IntAlarmEn() +* 功能说明: 闹钟中断使能 +* 输 入: RTC_TypeDef * RTCx 指定要被设置的RTC，可取值包括RTC +* 输 出: 无 +* 注意事项: 无 ******************************************************************************************************************************************/ void RTC_IntAlarmEn(RTC_TypeDef *RTCx) { @@ -377,11 +383,11 @@ void RTC_IntAlarmEn(RTC_TypeDef *RTCx) } /****************************************************************************************************************************************** -* ��������: RTC_IntAlarmDis() -* ����˵��: �����жϽ�ֹ -* �� ��: RTC_TypeDef * RTCx ָ��Ҫ�����õ�RTC����ȡֵ����RTC -* �� ��: �� -* ע������: �� +* 函数名称: RTC_IntAlarmDis() +* 功能说明: 闹钟中断禁止 +* 输 入: RTC_TypeDef * RTCx 指定要被设置的RTC，可取值包括RTC +* 输 出: 无 +* 注意事项: 无 ******************************************************************************************************************************************/ void RTC_IntAlarmDis(RTC_TypeDef *RTCx) { @@ -389,11 +395,11 @@ void RTC_IntAlarmDis(RTC_TypeDef *RTCx) } /****************************************************************************************************************************************** -* ��������: RTC_IntAlarmClr() -* ����˵��: �����жϱ�־��� -* �� ��: RTC_TypeDef * RTCx ָ��Ҫ�����õ�RTC����ȡֵ����RTC -* �� ��: �� -* ע������: �� +* 函数名称: RTC_IntAlarmClr() +* 功能说明: 闹钟中断标志清除 +* 输 入: RTC_TypeDef * RTCx 指定要被设置的RTC，可取值包括RTC +* 输 出: 无 +* 注意事项: 无 ******************************************************************************************************************************************/ void RTC_IntAlarmClr(RTC_TypeDef *RTCx) { @@ -401,11 +407,11 @@ void RTC_IntAlarmClr(RTC_TypeDef *RTCx) } /****************************************************************************************************************************************** -* ��������: RTC_IntAlarmStat() -* ����˵��: �����ж�״̬ -* �� ��: RTC_TypeDef * RTCx ָ��Ҫ�����õ�RTC����ȡֵ����RTC -* �� ��: uint32_t 1 �����жϷ��� 0 �����ж�δ���� -* ע������: �� +* 函数名称: RTC_IntAlarmStat() +* 功能说明: 闹钟中断状态 +* 输 入: RTC_TypeDef * RTCx 指定要被设置的RTC，可取值包括RTC +* 输 出: uint32_t 1 闹钟中断发生 0 闹钟中断未发生 +* 注意事项: 无 ******************************************************************************************************************************************/ uint32_t RTC_IntAlarmStat(RTC_TypeDef *RTCx) { diff --git a/bsp/swm320-lq100/Libraries/SWM320_StdPeriph_Driver/SWM320_rtc.h b/bsp/swm320-lq100/Libraries/SWM320_StdPeriph_Driver/SWM320_rtc.h index 8c5d6f5d63..d534fa4788 100644 --- a/bsp/swm320-lq100/Libraries/SWM320_StdPeriph_Driver/SWM320_rtc.h +++ b/bsp/swm320-lq100/Libraries/SWM320_StdPeriph_Driver/SWM320_rtc.h @@ -1,46 +1,44 @@ #ifndef __SWM320_RTC_H__ #define __SWM320_RTC_H__ - -#define RTC_SUN 0x01 -#define RTC_MON 0x02 -#define RTC_TUE 0x04 -#define RTC_WED 0x08 -#define RTC_THU 0x10 -#define RTC_FRI 0x20 -#define RTC_SAT 0x40 - +#define RTC_SUN 0x01 +#define RTC_MON 0x02 +#define RTC_TUE 0x04 +#define RTC_WED 0x08 +#define RTC_THU 0x10 +#define RTC_FRI 0x20 +#define RTC_SAT 0x40 typedef struct { uint16_t Year; - uint8_t Month; - uint8_t Date; - uint8_t Hour; - uint8_t Minute; - uint8_t Second; - uint8_t SecondIEn; - uint8_t MinuteIEn; + uint8_t Month; //取值1--12 + uint8_t Date; //取值1--31 + uint8_t Hour; //取值0--23 + uint8_t Minute; //取值0--59 + uint8_t Second; //取值0--59 + uint8_t SecondIEn; + uint8_t MinuteIEn; } RTC_InitStructure; typedef struct { - uint8_t Days; //RTC_SUN��RTC_MON��RTC_TUE��RTC_WED��RTC_THU��RTC_FRI��RTC_SAT������������ - uint8_t Hour; - uint8_t Minute; - uint8_t Second; - uint8_t AlarmIEn; + uint8_t Days; //RTC_SUN、RTC_MON、RTC_TUE、RTC_WED、RTC_THU、RTC_FRI、RTC_SAT及其或运算组合 + uint8_t Hour; + uint8_t Minute; + uint8_t Second; + uint8_t AlarmIEn; } RTC_AlarmStructure; typedef struct { uint16_t Year; - uint8_t Month; - uint8_t Date; - uint8_t Day; //RTC_SUN��RTC_MON��RTC_TUE��RTC_WED��RTC_THU��RTC_FRI��RTC_SAT - uint8_t Hour; - uint8_t Minute; - uint8_t Second; + uint8_t Month; + uint8_t Date; + uint8_t Day; //RTC_SUN、RTC_MON、RTC_TUE、RTC_WED、RTC_THU、RTC_FRI、RTC_SAT + uint8_t Hour; + uint8_t Minute; + uint8_t Second; } RTC_DateTime; void RTC_Init(RTC_TypeDef *RTCx, RTC_InitStructure *initStruct); @@ -51,7 +49,6 @@ void RTC_GetDateTime(RTC_TypeDef *RTCx, RTC_DateTime *dateTime); void RTC_AlarmSetup(RTC_TypeDef *RTCx, RTC_AlarmStructure *alarmStruct); - void RTC_IntSecondEn(RTC_TypeDef *RTCx); void RTC_IntSecondDis(RTC_TypeDef *RTCx); void RTC_IntSecondClr(RTC_TypeDef *RTCx); diff --git a/bsp/swm320-lq100/Libraries/SWM320_StdPeriph_Driver/SWM320_sdio.c b/bsp/swm320-lq100/Libraries/SWM320_StdPeriph_Driver/SWM320_sdio.c index 305ab42733..849193110c 100644 --- a/bsp/swm320-lq100/Libraries/SWM320_StdPeriph_Driver/SWM320_sdio.c +++ b/bsp/swm320-lq100/Libraries/SWM320_StdPeriph_Driver/SWM320_sdio.c @@ -1,10 +1,10 @@ /****************************************************************************************************************************************** -* �ļ�����: SWM320_sdio.c -* ����˵��: SWM320��Ƭ����SDIO�ӿ������� -* ����֧��: http://www.synwit.com.cn/e/tool/gbook/?bid=1 -* ע������: Ϊ��ͨ���ԡ������ԡ������ԣ�ֻ֧����512�ֽ�Ϊ��λ�Ķ�д -* �汾����: V1.1.0 2017��10��25�� -* ������¼: +* 文件名称: SWM320_sdio.c +* 功能说明: SWM320单片机的SDIO接口驱动库 +* 技术支持: http://www.synwit.com.cn/e/tool/gbook/?bid=1 +* 注意事项: 为了通用性、兼容性、易用性，只支持以512字节为单位的读写 +* 版本日期: V1.1.0 2017年10月25日 +* 升级记录: * * ******************************************************************************************************************************************* @@ -21,104 +21,104 @@ #include "SWM320.h" #include "SWM320_sdio.h" - SD_CardInfo SD_cardInfo; /****************************************************************************************************************************************** -* ��������: SDIO_Init() -* ����˵��: SDIO��дSD����ʼ������ʼ���ɸ���4��ģʽ����д��512�ֽڴ�С���� -* �� ��: �� -* �� ��: �� -* ע������: �� +* 函数名称: SDIO_Init() +* 功能说明: SDIO读写SD卡初始化，初始化成高速4线模式、读写以512字节大小进行 +* 输 入: uint32_t freq SDIO_CLK时钟频率 +* 输 出: uint32_t SD_RES_OK 操作成功 SD_RES_ERR 操作失败 SD_RES_TIMEOUT 操作超时 +* 注意事项: 无 ******************************************************************************************************************************************/ -uint32_t SDIO_Init(void) +uint32_t SDIO_Init(uint32_t freq) { + uint32_t res; uint32_t resp, resps[4]; SYS->CLKDIV &= ~SYS_CLKDIV_SDIO_Msk; - if (SystemCoreClock > 80000000) //SDIOʱ����ҪС��52MHz - SYS->CLKDIV |= (2 << SYS_CLKDIV_SDIO_Pos); //SDCLK = SYSCLK / 4 + if (SystemCoreClock > 80000000) //SDIO时钟需要小于52MHz + SYS->CLKDIV |= (2 << SYS_CLKDIV_SDIO_Pos); //SDCLK = SYSCLK / 4 else - SYS->CLKDIV |= (1 << SYS_CLKDIV_SDIO_Pos); //SDCLK = SYSCLK / 2 + SYS->CLKDIV |= (1 << SYS_CLKDIV_SDIO_Pos); //SDCLK = SYSCLK / 2 SYS->CLKEN |= (0x01 << SYS_CLKEN_SDIO_Pos); SDIO->CR2 = (1 << SDIO_CR2_RSTALL_Pos); SDIO->CR1 = (1 << SDIO_CR1_CDSRC_Pos) | - (0 << SDIO_CR1_8BIT_Pos) | - (0 << SDIO_CR1_4BIT_Pos) | + (0 << SDIO_CR1_8BIT_Pos) | + (0 << SDIO_CR1_4BIT_Pos) | (1 << SDIO_CR1_PWRON_Pos) | (7 << SDIO_CR1_VOLT_Pos); SDIO->CR2 = (1 << SDIO_CR2_CLKEN_Pos) | (1 << SDIO_CR2_SDCLKEN_Pos) | - (calcSDCLKDiv(SD_CLK_400KHz) << SDIO_CR2_SDCLKDIV_Pos) | - (0xC << SDIO_CR2_TIMEOUT_Pos); - - while ((SDIO->CR2 & SDIO_CR2_CLKRDY_Msk) == 0); - - SDIO->IE = 0xFFFF01FF; - SDIO->IM = 0x00FF00FF; + (calcSDCLKDiv(100000) << SDIO_CR2_SDCLKDIV_Pos) | + (0xC << SDIO_CR2_TIMEOUT_Pos); // 2**25 SDIO_CLK - SDIO_SendCmd(SD_CMD_GO_IDLE_STATE, 0x00, SD_RESP_NO, 0, 0, 0); //CMD0: GO_IDLE_STATE + while ((SDIO->CR2 & SDIO_CR2_CLKRDY_Msk) == 0) + ; + SDIO->IFE = 0xFFFFFFFF; - SDIO_SendCmd(SD_CMD_SEND_IF_COND, 0x1AA, SD_RESP_32b, &resp, 0, 0); //CMD8: SEND_IF_COND, ������ѹ������Ƿ�֧��SD 2.0 + SDIO_SendCmd(SD_CMD_GO_IDLE_STATE, 0x00, SD_RESP_NO, 0); //CMD0: GO_IDLE_STATE - if (resp == 0x1AA) SD_cardInfo.CardType = SDIO_STD_CAPACITY_SD_CARD_V2_0; - else SD_cardInfo.CardType = SDIO_STD_CAPACITY_SD_CARD_V1_1; + res = SDIO_SendCmd(SD_CMD_SEND_IF_COND, 0x1AA, SD_RESP_32b, &resp); //CMD8: SEND_IF_COND, 检测工作电压、检测是否支持SD 2.0 + if (res != SD_RES_OK) + return res; + if (resp == 0x1AA) + SD_cardInfo.CardType = SDIO_STD_CAPACITY_SD_CARD_V2_0; + else + SD_cardInfo.CardType = SDIO_STD_CAPACITY_SD_CARD_V1_1; - do //ACMD41: SD_CMD_SD_APP_OP_COND + do //ACMD41: SD_CMD_SD_APP_OP_COND { - SDIO_SendCmd(SD_CMD_APP_CMD, 0x00, SD_RESP_32b, &resp, 0, 0); + res = SDIO_SendCmd(SD_CMD_APP_CMD, 0x00, SD_RESP_32b, &resp); + if (res != SD_RES_OK) + return res; - if (resp != 0x120) return SD_RES_ERR; //����SD����������MMC�� + if (resp != 0x120) + return SD_RES_ERR; //不是SD卡，可能是MMC卡 if (SD_cardInfo.CardType == SDIO_STD_CAPACITY_SD_CARD_V2_0) - SDIO_SendCmd(SD_CMD_SD_APP_OP_COND, 0x80100000 | 0x40000000, SD_RESP_32b, &resp, 0, 0); + SDIO_SendCmd(SD_CMD_SD_APP_OP_COND, 0x80100000 | 0x40000000, SD_RESP_32b, &resp); else - SDIO_SendCmd(SD_CMD_SD_APP_OP_COND, 0x80100000 | 0x00000000, SD_RESP_32b, &resp, 0, 0); - } - while (((resp >> 31) & 0x01) == 0); //�ϵ�û���ʱresp[31] == 0 - - if (((resp >> 30) & 0x01) == 1) SD_cardInfo.CardType = SDIO_HIGH_CAPACITY_SD_CARD; + SDIO_SendCmd(SD_CMD_SD_APP_OP_COND, 0x80100000 | 0x00000000, SD_RESP_32b, &resp); + } while (((resp >> 31) & 0x01) == 0); //上电没完成时resp[31] == 0 + if (((resp >> 30) & 0x01) == 1) + SD_cardInfo.CardType = SDIO_HIGH_CAPACITY_SD_CARD; - SDIO_SendCmd(SD_CMD_ALL_SEND_CID, 0x00, SD_RESP_128b, resps, 0, 0); //CMD2: SD_CMD_ALL_SEND_CID����ȡCID + SDIO_SendCmd(SD_CMD_ALL_SEND_CID, 0x00, SD_RESP_128b, resps); //CMD2: SD_CMD_ALL_SEND_CID，获取CID parseCID(resps); - - SDIO_SendCmd(SD_CMD_SET_REL_ADDR, 0x00, SD_RESP_32b, &resp, 0, 0); //CMD3: SD_CMD_SET_REL_ADDR������RCA + SDIO_SendCmd(SD_CMD_SET_REL_ADDR, 0x00, SD_RESP_32b, &resp); //CMD3: SD_CMD_SET_REL_ADDR，设置RCA SD_cardInfo.RCA = resp >> 16; - - SDIO_SendCmd(SD_CMD_SEND_CSD, SD_cardInfo.RCA << 16, SD_RESP_128b, resps, 0, 0); //CMD9: SD_CMD_SEND_CSD����ȡCSD + SDIO_SendCmd(SD_CMD_SEND_CSD, SD_cardInfo.RCA << 16, SD_RESP_128b, resps); //CMD9: SD_CMD_SEND_CSD，获取CSD parseCSD(resps); - if (SD_cardInfo.CardBlockSize < 0x200) return SD_RES_ERR; //������ֻ֧����512�ֽ�Ϊ��λ�Ķ�д����������д��λ���벻С��512 - + if (SD_cardInfo.CardBlockSize < 0x200) + return SD_RES_ERR; //本驱动只支持以512字节为单位的读写，所以最大读写单位必须不小于512 SDIO->CR2 &= ~(SDIO_CR2_SDCLKEN_Msk | SDIO_CR2_SDCLKDIV_Msk); SDIO->CR2 |= (1 << SDIO_CR2_SDCLKEN_Pos) | - (calcSDCLKDiv(SD_CLK_20MHz) << SDIO_CR2_SDCLKDIV_Pos); //��ʼ����ɣ�SDCLK�л������� - - - SDIO_SendCmd(SD_CMD_SEL_DESEL_CARD, SD_cardInfo.RCA << 16, SD_RESP_32b_busy, &resp, 0, 0); //CMD7: ѡ�п�����Standyģʽ����Transferģʽ + (calcSDCLKDiv(freq) << SDIO_CR2_SDCLKDIV_Pos); //初始化完成，SDCLK切换到高速 + SDIO_SendCmd(SD_CMD_SEL_DESEL_CARD, SD_cardInfo.RCA << 16, SD_RESP_32b_busy, &resp); //CMD7: 选中卡，从Standy模式进入Transfer模式 + SDIO->IF = SDIO_IF_TRXDONE_Msk; - SDIO_SendCmd(SD_CMD_APP_CMD, SD_cardInfo.RCA << 16, SD_RESP_32b, &resp, 0, 0); + SDIO_SendCmd(SD_CMD_APP_CMD, SD_cardInfo.RCA << 16, SD_RESP_32b, &resp); - SDIO_SendCmd(SD_CMD_APP_SD_SET_BUSWIDTH, SD_BUSWIDTH_4b, SD_RESP_32b, &resp, 0, 0); //�л���4λ����ģʽ + SDIO_SendCmd(SD_CMD_APP_SD_SET_BUSWIDTH, SD_BUSWIDTH_4b, SD_RESP_32b, &resp); //切换成4位总线模式 SDIO->CR1 |= (1 << SDIO_CR1_4BIT_Pos); - - SDIO_SendCmd(SD_CMD_SET_BLOCKLEN, 512, SD_RESP_32b, &resp, 0, 0); //�̶����Сλ512�ֽ� + SDIO_SendCmd(SD_CMD_SET_BLOCKLEN, 512, SD_RESP_32b, &resp); //固定块大小位512字节 SDIO->BLK = 512; @@ -126,84 +126,268 @@ uint32_t SDIO_Init(void) } /****************************************************************************************************************************************** -* ��������: SDIO_BlockWrite() -* ����˵��: ��SD��д������ -* �� ��: uint32_t block_addr SD�����ַ��ÿ��512�ֽ� -* uint32_t buff[] Ҫд������� -* �� ��: �� -* ע������: �� +* 函数名称: SDIO_BlockWrite() +* 功能说明: 向SD卡写入数据 +* 输 入: uint32_t block_addr SD卡块地址，每块512字节 +* uint32_t buff[] 要写入的数据 +* 输 出: uint32_t SD_RES_OK 操作成功 SD_RES_ERR 操作失败 SD_RES_TIMEOUT 操作超时 +* 注意事项: 无 ******************************************************************************************************************************************/ -void SDIO_BlockWrite(uint32_t block_addr, uint32_t buff[]) +uint32_t SDIO_BlockWrite(uint32_t block_addr, uint32_t buff[]) { - uint32_t i, resp, addr; + uint32_t res, i; + uint32_t addr, resp; - if (SD_cardInfo.CardType == SDIO_HIGH_CAPACITY_SD_CARD) addr = block_addr; - else addr = block_addr * 512; + if (SD_cardInfo.CardType == SDIO_HIGH_CAPACITY_SD_CARD) + addr = block_addr; + else + addr = block_addr * 512; - SDIO_SendCmd(SD_CMD_WRITE_SINGLE_BLOCK, addr, SD_RESP_32b, &resp, 1, 0); + res = SDIO_SendCmdWithData(SD_CMD_WRITE_SINGLE_BLOCK, addr, SD_RESP_32b, &resp, 0, 1); + if (res != SD_RES_OK) + return res; - while ((SDIO->IF & SDIO_IF_BUFWRRDY_Msk) == 0); + while ((SDIO->IF & SDIO_IF_BUFWRRDY_Msk) == 0) + __NOP(); SDIO->IF = SDIO_IF_BUFWRRDY_Msk; - for (i = 0; i < 512 / 4; i++) SDIO->DATA = buff[i]; + for (i = 0; i < 512 / 4; i++) + SDIO->DATA = buff[i]; - SDIO->IF = SDIO_IF_TRXDONE_Msk; //?? ��������� - while ((SDIO->IF & SDIO_IF_TRXDONE_Msk) == 0); + while ((SDIO->IF & SDIO_IF_TRXDONE_Msk) == 0) + __NOP(); SDIO->IF = SDIO_IF_TRXDONE_Msk; + + return SD_RES_OK; } /****************************************************************************************************************************************** -* ��������: SDIO_BlockRead() -* ����˵��: ��SD���������� -* �� ��: uint32_t block_addr SD�����ַ��ÿ��512�ֽ� -* uint32_t buff[] ���������� -* �� ��: �� -* ע������: �� +* 函数名称: SDIO_MultiBlockWrite() +* 功能说明: 向SD卡写入多块数据 +* 输 入: uint32_t block_addr SD卡块地址，每块512字节 +* uint16_t block_cnt 要写入的块数 +* uint32_t buff[] 要写入的数据 +* 输 出: uint32_t SD_RES_OK 操作成功 SD_RES_ERR 操作失败 SD_RES_TIMEOUT 操作超时 +* 注意事项: 无 ******************************************************************************************************************************************/ -void SDIO_BlockRead(uint32_t block_addr, uint32_t buff[]) +uint32_t SDIO_MultiBlockWrite(uint32_t block_addr, uint16_t block_cnt, uint32_t buff[]) { - uint32_t i, resp, addr; + uint32_t res, i, j; + uint32_t addr, resp; + + if (SD_cardInfo.CardType == SDIO_HIGH_CAPACITY_SD_CARD) + addr = block_addr; + else + addr = block_addr * 512; - if (SD_cardInfo.CardType == SDIO_HIGH_CAPACITY_SD_CARD) addr = block_addr; - else addr = block_addr * 512; + res = SDIO_SendCmdWithData(SD_CMD_WRITE_MULT_BLOCK, addr, SD_RESP_32b, &resp, 0, block_cnt); + if (res != SD_RES_OK) + return res; - SDIO_SendCmd(SD_CMD_READ_SINGLE_BLOCK, addr, SD_RESP_32b, &resp, 1, 1); + for (i = 0; i < block_cnt; i++) + { + while ((SDIO->IF & SDIO_IF_BUFWRRDY_Msk) == 0) + __NOP(); + SDIO->IF = SDIO_IF_BUFWRRDY_Msk; + + for (j = 0; j < 512 / 4; j++) + SDIO->DATA = buff[i * (512 / 4) + j]; + } + + while ((SDIO->IF & SDIO_IF_TRXDONE_Msk) == 0) + __NOP(); + SDIO->IF = SDIO_IF_TRXDONE_Msk; + + return SD_RES_OK; +} + +/****************************************************************************************************************************************** +* 函数名称: SDIO_DMABlockWrite() +* 功能说明: 通过DMA向SD卡写入多块数据 +* 输 入: uint32_t block_addr SD卡块地址，每块512字节 +* uint16_t block_cnt 要写入的块数 +* uint32_t buff[] 要写入的数据 +* 输 出: uint32_t SD_RES_OK 操作成功 SD_RES_ERR 操作失败 SD_RES_TIMEOUT 操作超时 +* 注意事项: 无 +******************************************************************************************************************************************/ +uint32_t SDIO_DMABlockWrite(uint32_t block_addr, uint16_t block_cnt, uint32_t buff[]) +{ + uint32_t res; + uint32_t addr, resp; + + if (SD_cardInfo.CardType == SDIO_HIGH_CAPACITY_SD_CARD) + addr = block_addr; + else + addr = block_addr * 512; + + SDIO->DMA_MEM_ADDR = (uint32_t)buff; + + res = SDIO_SendCmdWithDataByDMA(SD_CMD_WRITE_MULT_BLOCK, addr, SD_RESP_32b, &resp, 0, block_cnt); + if (res != SD_RES_OK) + return res; + + while ((SDIO->IF & SDIO_IF_TRXDONE_Msk) == 0) + __NOP(); + SDIO->IF = SDIO_IF_TRXDONE_Msk; + + return SD_RES_OK; +} + +/****************************************************************************************************************************************** +* 函数名称: SDIO_BlockRead() +* 功能说明: 从SD卡读出数据 +* 输 入: uint32_t block_addr SD卡块地址，每块512字节 +* uint32_t buff[] 读出的数据 +* 输 出: uint32_t SD_RES_OK 操作成功 SD_RES_ERR 操作失败 SD_RES_TIMEOUT 操作超时 +* 注意事项: 无 +******************************************************************************************************************************************/ +uint32_t SDIO_BlockRead(uint32_t block_addr, uint32_t buff[]) +{ + uint32_t res, i; + uint32_t addr, resp; + + if (SD_cardInfo.CardType == SDIO_HIGH_CAPACITY_SD_CARD) + addr = block_addr; + else + addr = block_addr * 512; - while ((SDIO->IF & SDIO_IF_BUFRDRDY_Msk) == 0); + res = SDIO_SendCmdWithData(SD_CMD_READ_SINGLE_BLOCK, addr, SD_RESP_32b, &resp, 1, 1); + if (res != SD_RES_OK) + return res; + + while ((SDIO->IF & SDIO_IF_BUFRDRDY_Msk) == 0) + __NOP(); SDIO->IF = SDIO_IF_BUFRDRDY_Msk; - for (i = 0; i < 512 / 4; i++) buff[i] = SDIO->DATA; + for (i = 0; i < 512 / 4; i++) + buff[i] = SDIO->DATA; + + while ((SDIO->IF & SDIO_IF_TRXDONE_Msk) == 0) + __NOP(); + SDIO->IF = SDIO_IF_TRXDONE_Msk; + + return SD_RES_OK; +} + +/****************************************************************************************************************************************** +* 函数名称: SDIO_MultiBlockRead() +* 功能说明: 从SD卡读出多块数据 +* 输 入: uint32_t block_addr SD卡块地址，每块512字节 +* uint16_t block_cnt 要读出的块数 +* uint32_t buff[] 读出的数据 +* 输 出: uint32_t SD_RES_OK 操作成功 SD_RES_ERR 操作失败 SD_RES_TIMEOUT 操作超时 +* 注意事项: 无 +******************************************************************************************************************************************/ +uint32_t SDIO_MultiBlockRead(uint32_t block_addr, uint16_t block_cnt, uint32_t buff[]) +{ + uint32_t res, i, j; + uint32_t addr, resp; + + if (SD_cardInfo.CardType == SDIO_HIGH_CAPACITY_SD_CARD) + addr = block_addr; + else + addr = block_addr * 512; + + res = SDIO_SendCmdWithData(SD_CMD_READ_MULT_BLOCK, addr, SD_RESP_32b, &resp, 1, block_cnt); + if (res != SD_RES_OK) + return res; + + for (i = 0; i < block_cnt; i++) + { + while ((SDIO->IF & SDIO_IF_BUFRDRDY_Msk) == 0) + __NOP(); + SDIO->IF = SDIO_IF_BUFRDRDY_Msk; + + for (j = 0; j < 512 / 4; j++) + buff[i * (512 / 4) + j] = SDIO->DATA; + } + + while ((SDIO->IF & SDIO_IF_TRXDONE_Msk) == 0) + __NOP(); + SDIO->IF = SDIO_IF_TRXDONE_Msk; + + return SD_RES_OK; +} + +/****************************************************************************************************************************************** +* 函数名称: SDIO_DMABlockRead() +* 功能说明: 通过DMA从SD卡读出多块数据 +* 输 入: uint32_t block_addr SD卡块地址，每块512字节 +* uint16_t block_cnt 要读出的块数 +* uint32_t buff[] 读出的数据 +* 输 出: uint32_t SD_RES_OK 操作成功 SD_RES_ERR 操作失败 SD_RES_TIMEOUT 操作超时 +* 注意事项: 无 +******************************************************************************************************************************************/ +uint32_t SDIO_DMABlockRead(uint32_t block_addr, uint16_t block_cnt, uint32_t buff[]) +{ + uint32_t res; + uint32_t addr, resp; + + if (SD_cardInfo.CardType == SDIO_HIGH_CAPACITY_SD_CARD) + addr = block_addr; + else + addr = block_addr * 512; - while ((SDIO->IF & SDIO_IF_TRXDONE_Msk) == 0); + SDIO->DMA_MEM_ADDR = (uint32_t)buff; + + res = SDIO_SendCmdWithDataByDMA(SD_CMD_READ_MULT_BLOCK, addr, SD_RESP_32b, &resp, 1, block_cnt); + if (res != SD_RES_OK) + return res; + + while ((SDIO->IF & SDIO_IF_TRXDONE_Msk) == 0) + __NOP(); SDIO->IF = SDIO_IF_TRXDONE_Msk; + + return SD_RES_OK; } /****************************************************************************************************************************************** -* ��������: SDIO_SendCmd() -* ����˵��: SDIO��SD���������� -* �� ��: uint32_t cmd �������� -* uint32_t arg ������� -* uint32_t resp_type ��Ӧ���ͣ�ȡֵSD_RESP_NO��SD_RESP_32b��SD_RESP_128b��SD_RESP_32b_busy -* uint32_t *resp_data ��Ӧ���� -* uint32_t have_data �Ƿ������ݴ��� -* uint32_t data_read 1 ��SD�� 0 дSD�� -* �� ��: �� -* ע������: �� +* 函数名称: _SDIO_SendCmd() +* 功能说明: SDIO向SD卡发送命令 +* 输 入: uint32_t cmd 命令索引 +* uint32_t arg 命令参数 +* uint32_t resp_type 响应类型，取值SD_RESP_NO、SD_RESP_32b、SD_RESP_128b、SD_RESP_32b_busy +* uint32_t *resp_data 响应内容 +* uint32_t have_data 是否有数据传输 +* uint32_t data_read 1 读SD卡 0 写SD卡 +* uint16_t block_cnt 读写块个数 +* uint32_t use_dma 1 使用DMA搬运数据 +* 输 出: uint32_t SD_RES_OK 操作成功 SD_RES_ERR 操作失败 SD_RES_TIMEOUT 操作超时 +* 注意事项: 无 ******************************************************************************************************************************************/ -void SDIO_SendCmd(uint32_t cmd, uint32_t arg, uint32_t resp_type, uint32_t *resp_data, uint32_t have_data, uint32_t data_read) +uint32_t _SDIO_SendCmd(uint32_t cmd, uint32_t arg, uint32_t resp_type, uint32_t *resp_data, uint32_t have_data, uint32_t data_read, uint16_t block_cnt, uint32_t use_dma) { + SDIO->BLK &= ~SDIO_BLK_COUNT_Msk; + SDIO->BLK |= (block_cnt << SDIO_BLK_COUNT_Pos); + SDIO->ARG = arg; SDIO->CMD = (cmd << SDIO_CMD_CMDINDX_Pos) | - (0 << SDIO_CMD_CMDTYPE_Pos) | - (have_data << SDIO_CMD_HAVEDATA_Pos) | - (0 << SDIO_CMD_IDXCHECK_Pos) | - (0 << SDIO_CMD_CRCCHECK_Pos) | + (0 << SDIO_CMD_CMDTYPE_Pos) | + (0 << SDIO_CMD_IDXCHECK_Pos) | + (0 << SDIO_CMD_CRCCHECK_Pos) | (resp_type << SDIO_CMD_RESPTYPE_Pos) | - (0 << SDIO_CMD_MULTBLK_Pos) | - (data_read << SDIO_CMD_DIRREAD_Pos) | - (0 << SDIO_CMD_BLKCNTEN_Pos); + (have_data << SDIO_CMD_HAVEDATA_Pos) | + (data_read << SDIO_CMD_DIRREAD_Pos) | + ((block_cnt > 1) << SDIO_CMD_MULTBLK_Pos) | + ((block_cnt > 1) << SDIO_CMD_BLKCNTEN_Pos) | + ((block_cnt > 1) << SDIO_CMD_AUTOCMD12_Pos) | + (use_dma << SDIO_CMD_DMAEN_Pos); + + while ((SDIO->IF & SDIO_IF_CMDDONE_Msk) == 0) + { + if (SDIO->IF & SDIO_IF_CMDTIMEOUT_Msk) + { + SDIO->IF = SDIO_IF_CMDTIMEOUT_Msk; + + return SD_RES_TIMEOUT; + } + else if (SDIO->IF & SDIO_IF_ERROR_Msk) + { + SDIO->IF = 0xFFFFFFFF; - while ((SDIO->IF & SDIO_IF_CMDDONE_Msk) == 0); + return SD_RES_ERR; + } + } SDIO->IF = SDIO_IF_CMDDONE_Msk; if (resp_type == SD_RESP_32b) @@ -212,15 +396,16 @@ void SDIO_SendCmd(uint32_t cmd, uint32_t arg, uint32_t resp_type, uint32_t *resp } else if (resp_type == SD_RESP_128b) { - //�Ĵ����н�CID/CSD[127-8]���δ������RESP3-0[119-0]�����λ��CRC������ - //��������ʱ������˳��CID/CSD[127-8]�����resp_data0-3[127-8]�����8λ���0x00 + //寄存器中将CID/CSD[127-8]依次存放在了RESP3-0[119-0]，最低位的CRC被丢掉 + //读出数据时调整了顺序，将CID/CSD[127-8]存放在resp_data0-3[127-8]，最低8位填充0x00 resp_data[0] = (SDIO->RESP[3] << 8) + ((SDIO->RESP[2] >> 24) & 0xFF); resp_data[1] = (SDIO->RESP[2] << 8) + ((SDIO->RESP[1] >> 24) & 0xFF); resp_data[2] = (SDIO->RESP[1] << 8) + ((SDIO->RESP[0] >> 24) & 0xFF); resp_data[3] = (SDIO->RESP[0] << 8) + 0x00; } -} + return SD_RES_OK; +} void parseCID(uint32_t CID_Tab[4]) { @@ -328,7 +513,7 @@ void parseCSD(uint32_t CSD_Tab[4]) SD_cardInfo.SD_csd.Reserved2 = 0; /*!< Reserved */ if ((SD_cardInfo.CardType == SDIO_STD_CAPACITY_SD_CARD_V1_1) || - (SD_cardInfo.CardType == SDIO_STD_CAPACITY_SD_CARD_V2_0)) + (SD_cardInfo.CardType == SDIO_STD_CAPACITY_SD_CARD_V2_0)) { SD_cardInfo.SD_csd.DeviceSize = (tmp & 0x03) << 10; @@ -352,7 +537,7 @@ void parseCSD(uint32_t CSD_Tab[4]) tmp = (uint8_t)((CSD_Tab[2] & 0x0000FF00) >> 8); SD_cardInfo.SD_csd.DeviceSizeMul |= (tmp & 0x80) >> 7; - SD_cardInfo.CardCapacity = (SD_cardInfo.SD_csd.DeviceSize + 1) ; + SD_cardInfo.CardCapacity = (SD_cardInfo.SD_csd.DeviceSize + 1); SD_cardInfo.CardCapacity *= (1 << (SD_cardInfo.SD_csd.DeviceSizeMul + 2)); SD_cardInfo.CardBlockSize = 1 << (SD_cardInfo.SD_csd.RdBlockLen); SD_cardInfo.CardCapacity *= SD_cardInfo.CardBlockSize; @@ -376,7 +561,7 @@ void parseCSD(uint32_t CSD_Tab[4]) /*!< Byte 10 */ tmp = (uint8_t)((CSD_Tab[2] & 0x0000FF00) >> 8); - SD_cardInfo.CardCapacity = (SD_cardInfo.SD_csd.DeviceSize + 1) * 512 * 1024; + SD_cardInfo.CardCapacity = (uint64_t)(SD_cardInfo.SD_csd.DeviceSize + 1) * 512 * 1024; SD_cardInfo.CardBlockSize = 512; } @@ -412,25 +597,30 @@ void parseCSD(uint32_t CSD_Tab[4]) SD_cardInfo.SD_csd.ECC = (tmp & 0x03); } -uint32_t calcSDCLKDiv(uint32_t freq_sel) +uint32_t calcSDCLKDiv(uint32_t freq) { + uint32_t prediv = ((SYS->CLKDIV & SYS_CLKDIV_SDIO_Msk) >> SYS_CLKDIV_SDIO_Pos); + uint32_t clkdiv = (SystemCoreClock / (1 << prediv)) / freq; uint32_t regdiv = 0; - uint32_t clkdiv = 0; - if (((SYS->CLKDIV & SYS_CLKDIV_SDIO_Msk) >> SYS_CLKDIV_SDIO_Pos) == 1) - clkdiv = SystemCoreClock / 2 / ((freq_sel == SD_CLK_400KHz) ? 300000 : 15000000); - else if (((SYS->CLKDIV & SYS_CLKDIV_SDIO_Msk) >> SYS_CLKDIV_SDIO_Pos) == 2) - clkdiv = SystemCoreClock / 4 / ((freq_sel == SD_CLK_400KHz) ? 300000 : 15000000); - - if (clkdiv > 128) regdiv = 0x80; - else if (clkdiv > 64) regdiv = 0x40; - else if (clkdiv > 32) regdiv = 0x20; - else if (clkdiv > 16) regdiv = 0x10; - else if (clkdiv > 8) regdiv = 0x08; - else if (clkdiv > 4) regdiv = 0x04; - else if (clkdiv > 2) regdiv = 0x02; - else if (clkdiv > 1) regdiv = 0x01; - else regdiv = 0x00; + if (clkdiv > 128) + regdiv = 0x80; + else if (clkdiv > 64) + regdiv = 0x40; + else if (clkdiv > 32) + regdiv = 0x20; + else if (clkdiv > 16) + regdiv = 0x10; + else if (clkdiv > 8) + regdiv = 0x08; + else if (clkdiv > 4) + regdiv = 0x04; + else if (clkdiv > 2) + regdiv = 0x02; + else if (clkdiv > 1) + regdiv = 0x01; + else + regdiv = 0x00; return regdiv; } diff --git a/bsp/swm320-lq100/Libraries/SWM320_StdPeriph_Driver/SWM320_sdio.h b/bsp/swm320-lq100/Libraries/SWM320_StdPeriph_Driver/SWM320_sdio.h index 1df6602159..d9834291ac 100644 --- a/bsp/swm320-lq100/Libraries/SWM320_StdPeriph_Driver/SWM320_sdio.h +++ b/bsp/swm320-lq100/Libraries/SWM320_StdPeriph_Driver/SWM320_sdio.h @@ -1,116 +1,109 @@ #ifndef __SWM320_SDIO_H__ #define __SWM320_SDIO_H__ - -#define SD_CMD_GO_IDLE_STATE ((uint8_t)0) -#define SD_CMD_SEND_OP_COND ((uint8_t)1) -#define SD_CMD_ALL_SEND_CID ((uint8_t)2) -#define SD_CMD_SET_REL_ADDR ((uint8_t)3) -#define SD_CMD_SET_DSR ((uint8_t)4) -#define SD_CMD_HS_SWITCH ((uint8_t)6) -#define SD_CMD_SEL_DESEL_CARD ((uint8_t)7) -#define SD_CMD_SEND_IF_COND ((uint8_t)8) -#define SD_CMD_SEND_CSD ((uint8_t)9) -#define SD_CMD_SEND_CID ((uint8_t)10) -#define SD_CMD_STOP_TRANSMISSION ((uint8_t)12) -#define SD_CMD_SEND_STATUS ((uint8_t)13) -#define SD_CMD_SET_BLOCKLEN ((uint8_t)16) -#define SD_CMD_READ_SINGLE_BLOCK ((uint8_t)17) -#define SD_CMD_READ_MULT_BLOCK ((uint8_t)18) -#define SD_CMD_WRITE_SINGLE_BLOCK ((uint8_t)24) -#define SD_CMD_WRITE_MULT_BLOCK ((uint8_t)25) -#define SD_CMD_PROG_CID ((uint8_t)26) -#define SD_CMD_PROG_CSD ((uint8_t)27) -#define SD_CMD_APP_CMD ((uint8_t)55) +#define SD_CMD_GO_IDLE_STATE ((uint8_t)0) +#define SD_CMD_SEND_OP_COND ((uint8_t)1) +#define SD_CMD_ALL_SEND_CID ((uint8_t)2) +#define SD_CMD_SET_REL_ADDR ((uint8_t)3) +#define SD_CMD_SET_DSR ((uint8_t)4) +#define SD_CMD_HS_SWITCH ((uint8_t)6) +#define SD_CMD_SEL_DESEL_CARD ((uint8_t)7) +#define SD_CMD_SEND_IF_COND ((uint8_t)8) +#define SD_CMD_SEND_CSD ((uint8_t)9) +#define SD_CMD_SEND_CID ((uint8_t)10) +#define SD_CMD_STOP_TRANSMISSION ((uint8_t)12) +#define SD_CMD_SEND_STATUS ((uint8_t)13) +#define SD_CMD_SET_BLOCKLEN ((uint8_t)16) +#define SD_CMD_READ_SINGLE_BLOCK ((uint8_t)17) +#define SD_CMD_READ_MULT_BLOCK ((uint8_t)18) +#define SD_CMD_WRITE_SINGLE_BLOCK ((uint8_t)24) +#define SD_CMD_WRITE_MULT_BLOCK ((uint8_t)25) +#define SD_CMD_PROG_CID ((uint8_t)26) +#define SD_CMD_PROG_CSD ((uint8_t)27) +#define SD_CMD_APP_CMD ((uint8_t)55) /*Following commands are SD Card Specific commands. SDIO_APP_CMD should be sent before sending these commands. */ -#define SD_CMD_APP_SD_SET_BUSWIDTH ((uint8_t)6) -#define SD_CMD_SD_APP_STAUS ((uint8_t)13) -#define SD_CMD_SD_APP_SEND_NUM_WRITE_BLOCKS ((uint8_t)22) -#define SD_CMD_SD_APP_OP_COND ((uint8_t)41) -#define SD_CMD_SD_APP_SET_CLR_CARD_DETECT ((uint8_t)42) -#define SD_CMD_SD_APP_SEND_SCR ((uint8_t)51) -#define SD_CMD_SDIO_RW_DIRECT ((uint8_t)52) -#define SD_CMD_SDIO_RW_EXTENDED ((uint8_t)53) - - -#define SD_RESP_NO 0 //0 ����Ӧ -#define SD_RESP_32b 2 //2 32λ��Ӧ -#define SD_RESP_128b 1 //1 128λ��Ӧ -#define SD_RESP_32b_busy 3 //3 32λ��Ӧ��check Busy after response +#define SD_CMD_APP_SD_SET_BUSWIDTH ((uint8_t)6) +#define SD_CMD_SD_APP_STAUS ((uint8_t)13) +#define SD_CMD_SD_APP_SEND_NUM_WRITE_BLOCKS ((uint8_t)22) +#define SD_CMD_SD_APP_OP_COND ((uint8_t)41) +#define SD_CMD_SD_APP_SET_CLR_CARD_DETECT ((uint8_t)42) +#define SD_CMD_SD_APP_SEND_SCR ((uint8_t)51) +#define SD_CMD_SDIO_RW_DIRECT ((uint8_t)52) +#define SD_CMD_SDIO_RW_EXTENDED ((uint8_t)53) -#define SD_CLK_400KHz 0 -#define SD_CLK_20MHz 1 +#define SD_RESP_NO 0 //0 无响应 +#define SD_RESP_32b 2 //2 32位响应 +#define SD_RESP_128b 1 //1 128位响应 +#define SD_RESP_32b_busy 3 //3 32位响应，check Busy after response -#define SD_BUSWIDTH_1b 0 -#define SD_BUSWIDTH_4b 2 - -#define SD_RES_OK 0 -#define SD_RES_ERR 1 +#define SD_BUSWIDTH_1b 0 +#define SD_BUSWIDTH_4b 2 +#define SD_RES_OK 0 +#define SD_RES_ERR 1 +#define SD_RES_TIMEOUT 2 typedef struct { - __IO uint8_t CSDStruct; // CSD structure - __IO uint8_t SysSpecVersion; // System specification version - __IO uint8_t Reserved1; // Reserved - __IO uint8_t TAAC; // Data read access-time 1 - __IO uint8_t NSAC; // Data read access-time 2 in CLK cycles - __IO uint8_t MaxBusClkFrec; // Max. bus clock frequency - __IO uint16_t CardComdClasses; //< Card command classes - __IO uint8_t RdBlockLen; // Max. read data block length - __IO uint8_t PartBlockRead; // Partial blocks for read allowed - __IO uint8_t WrBlockMisalign; // Write block misalignment - __IO uint8_t RdBlockMisalign; // Read block misalignment - __IO uint8_t DSRImpl; // DSR implemented - __IO uint8_t Reserved2; // Reserved - __IO uint32_t DeviceSize; // Device Size - __IO uint8_t MaxRdCurrentVDDMin; // Max. read current @ VDD min - __IO uint8_t MaxRdCurrentVDDMax; // Max. read current @ VDD max - __IO uint8_t MaxWrCurrentVDDMin; // Max. write current @ VDD min - __IO uint8_t MaxWrCurrentVDDMax; // Max. write current @ VDD max - __IO uint8_t DeviceSizeMul; // Device size multiplier - __IO uint8_t EraseGrSize; // Erase group size - __IO uint8_t EraseGrMul; // Erase group size multiplier - __IO uint8_t WrProtectGrSize; // Write protect group size - __IO uint8_t WrProtectGrEnable; // Write protect group enable - __IO uint8_t ManDeflECC; // Manufacturer default ECC - __IO uint8_t WrSpeedFact; // Write speed factor - __IO uint8_t MaxWrBlockLen; // Max. write data block length - __IO uint8_t WriteBlockPaPartial; // Partial blocks for write allowed - __IO uint8_t Reserved3; // Reserded - __IO uint8_t ContentProtectAppli; // Content protection application - __IO uint8_t FileFormatGrouop; // File format group - __IO uint8_t CopyFlag; // Copy flag (OTP) - __IO uint8_t PermWrProtect; // Permanent write protection - __IO uint8_t TempWrProtect; // Temporary write protection - __IO uint8_t FileFormat; // File Format - __IO uint8_t ECC; // ECC code + __IO uint8_t CSDStruct; // CSD structure + __IO uint8_t SysSpecVersion; // System specification version + __IO uint8_t Reserved1; // Reserved + __IO uint8_t TAAC; // Data read access-time 1 + __IO uint8_t NSAC; // Data read access-time 2 in CLK cycles + __IO uint8_t MaxBusClkFrec; // Max. bus clock frequency + __IO uint16_t CardComdClasses; //< Card command classes + __IO uint8_t RdBlockLen; // Max. read data block length + __IO uint8_t PartBlockRead; // Partial blocks for read allowed + __IO uint8_t WrBlockMisalign; // Write block misalignment + __IO uint8_t RdBlockMisalign; // Read block misalignment + __IO uint8_t DSRImpl; // DSR implemented + __IO uint8_t Reserved2; // Reserved + __IO uint32_t DeviceSize; // Device Size + __IO uint8_t MaxRdCurrentVDDMin; // Max. read current @ VDD min + __IO uint8_t MaxRdCurrentVDDMax; // Max. read current @ VDD max + __IO uint8_t MaxWrCurrentVDDMin; // Max. write current @ VDD min + __IO uint8_t MaxWrCurrentVDDMax; // Max. write current @ VDD max + __IO uint8_t DeviceSizeMul; // Device size multiplier + __IO uint8_t EraseGrSize; // Erase group size + __IO uint8_t EraseGrMul; // Erase group size multiplier + __IO uint8_t WrProtectGrSize; // Write protect group size + __IO uint8_t WrProtectGrEnable; // Write protect group enable + __IO uint8_t ManDeflECC; // Manufacturer default ECC + __IO uint8_t WrSpeedFact; // Write speed factor + __IO uint8_t MaxWrBlockLen; // Max. write data block length + __IO uint8_t WriteBlockPaPartial; // Partial blocks for write allowed + __IO uint8_t Reserved3; // Reserded + __IO uint8_t ContentProtectAppli; // Content protection application + __IO uint8_t FileFormatGrouop; // File format group + __IO uint8_t CopyFlag; // Copy flag (OTP) + __IO uint8_t PermWrProtect; // Permanent write protection + __IO uint8_t TempWrProtect; // Temporary write protection + __IO uint8_t FileFormat; // File Format + __IO uint8_t ECC; // ECC code } SD_CSD; typedef struct { - __IO uint8_t ManufacturerID; // ManufacturerID - __IO uint16_t OEM_AppliID; // OEM/Application ID - __IO uint32_t ProdName1; // Product Name part1 - __IO uint8_t ProdName2; // Product Name part2 - __IO uint8_t ProdRev; // Product Revision - __IO uint32_t ProdSN; // Product Serial Number - __IO uint8_t Reserved1; // Reserved1 - __IO uint16_t ManufactDate; // Manufacturing Date + __IO uint8_t ManufacturerID; // ManufacturerID + __IO uint16_t OEM_AppliID; // OEM/Application ID + __IO uint32_t ProdName1; // Product Name part1 + __IO uint8_t ProdName2; // Product Name part2 + __IO uint8_t ProdRev; // Product Revision + __IO uint32_t ProdSN; // Product Serial Number + __IO uint8_t Reserved1; // Reserved1 + __IO uint16_t ManufactDate; // Manufacturing Date } SD_CID; - -#define SDIO_STD_CAPACITY_SD_CARD_V1_1 ((uint32_t)0x00000000) -#define SDIO_STD_CAPACITY_SD_CARD_V2_0 ((uint32_t)0x00000001) -#define SDIO_HIGH_CAPACITY_SD_CARD ((uint32_t)0x00000002) -#define SDIO_MULTIMEDIA_CARD ((uint32_t)0x00000003) -#define SDIO_SECURE_DIGITAL_IO_CARD ((uint32_t)0x00000004) -#define SDIO_HIGH_SPEED_MULTIMEDIA_CARD ((uint32_t)0x00000005) -#define SDIO_SECURE_DIGITAL_IO_COMBO_CARD ((uint32_t)0x00000006) -#define SDIO_HIGH_CAPACITY_MMC_CARD ((uint32_t)0x00000007) - +#define SDIO_STD_CAPACITY_SD_CARD_V1_1 ((uint32_t)0x00000000) +#define SDIO_STD_CAPACITY_SD_CARD_V2_0 ((uint32_t)0x00000001) +#define SDIO_HIGH_CAPACITY_SD_CARD ((uint32_t)0x00000002) +#define SDIO_MULTIMEDIA_CARD ((uint32_t)0x00000003) +#define SDIO_SECURE_DIGITAL_IO_CARD ((uint32_t)0x00000004) +#define SDIO_HIGH_SPEED_MULTIMEDIA_CARD ((uint32_t)0x00000005) +#define SDIO_SECURE_DIGITAL_IO_COMBO_CARD ((uint32_t)0x00000006) +#define SDIO_HIGH_CAPACITY_MMC_CARD ((uint32_t)0x00000007) typedef struct { @@ -122,14 +115,23 @@ typedef struct uint8_t CardType; } SD_CardInfo; - extern SD_CardInfo SD_cardInfo; -uint32_t SDIO_Init(void); -void SDIO_BlockWrite(uint32_t block_addr, uint32_t buff[]); -void SDIO_BlockRead(uint32_t block_addr, uint32_t buff[]); +uint32_t SDIO_Init(uint32_t freq); +uint32_t SDIO_BlockWrite(uint32_t block_addr, uint32_t buff[]); +uint32_t SDIO_BlockRead(uint32_t block_addr, uint32_t buff[]); + +uint32_t SDIO_MultiBlockWrite(uint32_t block_addr, uint16_t block_cnt, uint32_t buff[]); +uint32_t SDIO_MultiBlockRead(uint32_t block_addr, uint16_t block_cnt, uint32_t buff[]); + +uint32_t SDIO_DMABlockWrite(uint32_t block_addr, uint16_t block_cnt, uint32_t buff[]); +uint32_t SDIO_DMABlockRead(uint32_t block_addr, uint16_t block_cnt, uint32_t buff[]); + +uint32_t _SDIO_SendCmd(uint32_t cmd, uint32_t arg, uint32_t resp_type, uint32_t *resp_data, uint32_t have_data, uint32_t data_read, uint16_t block_cnt, uint32_t use_dma); -void SDIO_SendCmd(uint32_t cmd, uint32_t arg, uint32_t resp_type, uint32_t *resp_data, uint32_t have_data, uint32_t data_read); +#define SDIO_SendCmd(cmd, arg, resp_type, resp_data) _SDIO_SendCmd(cmd, arg, resp_type, resp_data, 0, 0, 0, 0) +#define SDIO_SendCmdWithData(cmd, arg, resp_type, resp_data, data_read, block_cnt) _SDIO_SendCmd(cmd, arg, resp_type, resp_data, 1, data_read, block_cnt, 0) +#define SDIO_SendCmdWithDataByDMA(cmd, arg, resp_type, resp_data, data_read, block_cnt) _SDIO_SendCmd(cmd, arg, resp_type, resp_data, 1, data_read, block_cnt, 1) void parseCID(uint32_t CID_Tab[4]); void parseCSD(uint32_t CID_Tab[4]); diff --git a/bsp/swm320-lq100/Libraries/SWM320_StdPeriph_Driver/SWM320_sdram.c b/bsp/swm320-lq100/Libraries/SWM320_StdPeriph_Driver/SWM320_sdram.c index f07af4ee51..bc5751f079 100644 --- a/bsp/swm320-lq100/Libraries/SWM320_StdPeriph_Driver/SWM320_sdram.c +++ b/bsp/swm320-lq100/Libraries/SWM320_StdPeriph_Driver/SWM320_sdram.c @@ -1,10 +1,10 @@ /****************************************************************************************************************************************** -* �ļ�����: SWM320_sdram.c -* ����˵��: SWM320��Ƭ����SDRAM�������� -* ����֧��: http://www.synwit.com.cn/e/tool/gbook/?bid=1 -* ע������: -* �汾����: V1.1.0 2017��10��25�� -* ������¼: +* 文件名称: SWM320_sdram.c +* 功能说明: SWM320单片机的SDRAM驱动程序 +* 技术支持: http://www.synwit.com.cn/e/tool/gbook/?bid=1 +* 注意事项: +* 版本日期: V1.1.0 2017年10月25日 +* 升级记录: * * ******************************************************************************************************************************************* @@ -22,37 +22,95 @@ #include "SWM320_sdram.h" /****************************************************************************************************************************************** -* ��������: SDRAM_Init() -* ����˵��: SDRAM��������ʼ�� -* �� ��: SDRAM_InitStructure * initStruct ����NOR Flash����������趨ֵ�Ľṹ�� -* �� ��: �� -* ע������: �� +* 函数名称: SDRAM_Init() +* 功能说明: SDRAM控制器初始化 +* 输 入: SDRAM_InitStructure * initStruct 包含 SDRAM 控制器相关设定值的结构体 +* 输 出: 无 +* 注意事项: 无 ******************************************************************************************************************************************/ void SDRAM_Init(SDRAM_InitStructure *initStruct) { + uint32_t row_n; + SYS->CLKEN |= (1 << SYS_CLKEN_SDRAM_Pos); SYS->CLKDIV &= ~SYS_CLKDIV_SDRAM_Msk; - SYS->CLKDIV |= (1 << SYS_CLKDIV_SDRAM_Pos); //2��Ƶ + SYS->CLKDIV |= (1 << SYS_CLKDIV_SDRAM_Pos); //2分频 - SDRAMC->CR0 = (2 << SDRAMC_CR0_BURSTLEN_Pos) | //2 Burst LengthΪ4 - (2 << SDRAMC_CR0_CASDELAY_Pos); + SDRAMC->CR0 = (2 << SDRAMC_CR0_BURSTLEN_Pos) | //2 Burst Length为4 + (initStruct->CASLatency << SDRAMC_CR0_CASDELAY_Pos); SDRAMC->CR1 = (initStruct->CellSize << SDRAMC_CR1_CELLSIZE_Pos) | - ((initStruct->CellWidth == 16 ? 0 : 1) << SDRAMC_CR1_CELL32BIT_Pos) | + (initStruct->CellWidth << SDRAMC_CR1_CELL32BIT_Pos) | (initStruct->CellBank << SDRAMC_CR1_BANK_Pos) | - ((initStruct->DataWidth == 16 ? 0 : 1) << SDRAMC_CR1_32BIT_Pos) | - (7 << SDRAMC_CR1_TMRD_Pos) | - (3 << SDRAMC_CR1_TRRD_Pos) | - (7 << SDRAMC_CR1_TRAS_Pos) | - (8 << SDRAMC_CR1_TRC_Pos) | - (3 << SDRAMC_CR1_TRCD_Pos) | - (3 << SDRAMC_CR1_TRP_Pos); + (0 << SDRAMC_CR1_32BIT_Pos) | + (initStruct->TimeTMRD << SDRAMC_CR1_TMRD_Pos) | + (initStruct->TimeTRRD << SDRAMC_CR1_TRRD_Pos) | + (initStruct->TimeTRAS << SDRAMC_CR1_TRAS_Pos) | + (initStruct->TimeTRC << SDRAMC_CR1_TRC_Pos) | + (initStruct->TimeTRCD << SDRAMC_CR1_TRCD_Pos) | + (initStruct->TimeTRP << SDRAMC_CR1_TRP_Pos); SDRAMC->LATCH = 0x02; + switch (initStruct->CellSize) + { + case SDRAM_CELLSIZE_16Mb: + row_n = 11; + break; + case SDRAM_CELLSIZE_64Mb: + row_n = 12; + break; + case SDRAM_CELLSIZE_128Mb: + row_n = 12; + break; + case SDRAM_CELLSIZE_256Mb: + row_n = 13; + break; + default: + row_n = 13; + break; + } + SDRAMC->REFRESH = (1 << SDRAMC_REFRESH_EN_Pos) | - (0x0FA << SDRAMC_REFRESH_RATE_Pos); + (((SystemCoreClock / 2) / 1000 * 64 / (1 << row_n)) << SDRAMC_REFRESH_RATE_Pos); + + while (SDRAMC->REFDONE == 0) + ; +} + +/****************************************************************************************************************************************** +* 函数名称: SDRAM_Enable() +* 功能说明: SDRAM使能，使能后可读写SDRAM +* 输 入: 无 +* 输 出: 无 +* 注意事项: 无 +******************************************************************************************************************************************/ +void SDRAM_Enable(void) +{ + uint32_t i; + + SYS->CLKEN |= (1 << SYS_CLKEN_SDRAM_Pos); + SDRAMC->REFRESH |= (1 << SDRAMC_REFRESH_EN_Pos); + + for (i = 0; i < 100; i++) + __NOP(); +} + +/****************************************************************************************************************************************** +* 函数名称: SDRAM_Disable() +* 功能说明: SDRAM禁能，禁能后SDRAM颗粒进入低功耗模式、并自刷新，不可读写 +* 输 入: 无 +* 输 出: 无 +* 注意事项: 无 +******************************************************************************************************************************************/ +void SDRAM_Disable(void) +{ + uint32_t i; + + SYS->CLKEN |= (1 << SYS_CLKEN_SDRAM_Pos); + SDRAMC->REFRESH &= ~(1 << SDRAMC_REFRESH_EN_Pos); - while (SDRAMC->REFDONE == 0); + for (i = 0; i < 100; i++) + __NOP(); } diff --git a/bsp/swm320-lq100/Libraries/SWM320_StdPeriph_Driver/SWM320_sdram.h b/bsp/swm320-lq100/Libraries/SWM320_StdPeriph_Driver/SWM320_sdram.h index c10d82fc12..cf8ca88a7c 100644 --- a/bsp/swm320-lq100/Libraries/SWM320_StdPeriph_Driver/SWM320_sdram.h +++ b/bsp/swm320-lq100/Libraries/SWM320_StdPeriph_Driver/SWM320_sdram.h @@ -3,21 +3,79 @@ typedef struct { - uint8_t DataWidth; // 16��32 + uint8_t CellSize; // SDRAM颗粒的容量，SDRAM_CELLSIZE_16Mb、SDRAM_CELLSIZE_64Mb、SDRAM_CELLSIZE_128Mb、SDRAM_CELLSIZE_256Mb + uint8_t CellBank; // SDRAM颗粒有几个bank，SDRAM_CELLBANK_2、SDRAM_CELLBANK_4 + uint8_t CellWidth; // SDRAM颗粒的位宽，SDRAM_CELLWIDTH_16、SDRAM_CELLWIDTH_32 + uint8_t CASLatency; // 列地址到有效数据输出间隔，SDRAM_CASLATENCY_2、SDRAM_CASLATENCY_3 - uint8_t CellSize; // SDRAM���������� - uint8_t CellBank; // SDRAM�����м���bank - uint8_t CellWidth; // SDRAM������λ�� 16��32 + uint8_t TimeTMRD; // MRS to New Command + uint8_t TimeTRRD; // Activate to activate on different banks + uint8_t TimeTRAS; // Self refresh time，最小Self-refresh周期 + uint8_t TimeTRC; // Row cycle delay，Refresh命令到Activate命令间延时，也是两个连续Refresh命令间延时 + uint8_t TimeTRCD; // Row to column delay，行地址到列地址间延时，也即Activate命令到读写命令间延时 + uint8_t TimeTRP; // Row precharge delay，Precharge命令到另一个命令间延时 } SDRAM_InitStructure; -#define SDRAM_CELLSIZE_16Mb 3 -#define SDRAM_CELLSIZE_64Mb 0 -#define SDRAM_CELLSIZE_128Mb 1 -#define SDRAM_CELLSIZE_256Mb 2 +#define SDRAM_CELLSIZE_16Mb 3 +#define SDRAM_CELLSIZE_64Mb 0 +#define SDRAM_CELLSIZE_128Mb 1 +#define SDRAM_CELLSIZE_256Mb 2 -#define SDRAM_CELLBANK_2 0 -#define SDRAM_CELLBANK_4 1 +#define SDRAM_CELLBANK_2 0 +#define SDRAM_CELLBANK_4 1 + +#define SDRAM_CELLWIDTH_16 0 +#define SDRAM_CELLWIDTH_32 1 + +#define SDRAM_CASLATENCY_2 2 +#define SDRAM_CASLATENCY_3 3 + +#define SDRAM_TMRD_3 3 +#define SDRAM_TMRD_4 4 +#define SDRAM_TMRD_5 5 +#define SDRAM_TMRD_6 6 +#define SDRAM_TMRD_7 7 + +#define SDRAM_TRRD_2 2 +#define SDRAM_TRRD_3 3 + +#define SDRAM_TRAS_2 2 +#define SDRAM_TRAS_3 3 +#define SDRAM_TRAS_4 4 +#define SDRAM_TRAS_5 5 +#define SDRAM_TRAS_6 6 +#define SDRAM_TRAS_7 7 + +#define SDRAM_TRC_2 2 +#define SDRAM_TRC_3 3 +#define SDRAM_TRC_4 4 +#define SDRAM_TRC_5 5 +#define SDRAM_TRC_6 6 +#define SDRAM_TRC_7 7 +#define SDRAM_TRC_8 8 +#define SDRAM_TRC_9 9 +#define SDRAM_TRC_10 10 +#define SDRAM_TRC_11 11 +#define SDRAM_TRC_12 12 +#define SDRAM_TRC_13 13 +#define SDRAM_TRC_14 14 +#define SDRAM_TRC_15 15 + +#define SDRAM_TRCD_3 3 +#define SDRAM_TRCD_4 4 +#define SDRAM_TRCD_5 5 +#define SDRAM_TRCD_6 6 +#define SDRAM_TRCD_7 7 + +#define SDRAM_TRP_3 3 +#define SDRAM_TRP_4 4 +#define SDRAM_TRP_5 5 +#define SDRAM_TRP_6 6 +#define SDRAM_TRP_7 7 void SDRAM_Init(SDRAM_InitStructure *initStruct); +void SDRAM_Enable(void); +void SDRAM_Disable(void); + #endif //__SWM320_SDRAM_H__ diff --git a/bsp/swm320-lq100/Libraries/SWM320_StdPeriph_Driver/SWM320_spi.c b/bsp/swm320-lq100/Libraries/SWM320_StdPeriph_Driver/SWM320_spi.c index 6c88ada224..09430547eb 100644 --- a/bsp/swm320-lq100/Libraries/SWM320_StdPeriph_Driver/SWM320_spi.c +++ b/bsp/swm320-lq100/Libraries/SWM320_StdPeriph_Driver/SWM320_spi.c @@ -1,10 +1,10 @@ /****************************************************************************************************************************************** -* �ļ�����: SWM320_spi.c -* ����˵��: SWM320��Ƭ����SPI���������� -* ����֧��: http://www.synwit.com.cn/e/tool/gbook/?bid=1 -* ע������: -* �汾����: V1.1.0 2017��10��25�� -* ������¼: +* 文件名称: SWM320_spi.c +* 功能说明: SWM320单片机的SPI功能驱动库 +* 技术支持: http://www.synwit.com.cn/e/tool/gbook/?bid=1 +* 注意事项: +* 版本日期: V1.1.0 2017年10月25日 +* 升级记录: * * ******************************************************************************************************************************************* @@ -21,14 +21,13 @@ #include "SWM320.h" #include "SWM320_spi.h" - /****************************************************************************************************************************************** -* ��������: SPI_Init() -* ����˵��: SPIͬ�����нӿڳ�ʼ��������֡�����趨��ʱ���趨���ٶ��趨���ж��趨��FIFO�����趨 -* �� ��: SPI_TypeDef * SPIx ָ��Ҫ�����õ�SPI����Чֵ����SPI0��SPI1 -* SPI_InitStructure * initStruct ����SPI����趨ֵ�Ľṹ�� -* �� ��: �� -* ע������: �� +* 函数名称: SPI_Init() +* 功能说明: SPI同步串行接口初始化，包括帧长度设定、时序设定、速度设定、中断设定、FIFO触发设定 +* 输 入: SPI_TypeDef * SPIx 指定要被设置的SPI，有效值包括SPI0、SPI1 +* SPI_InitStructure * initStruct 包含SPI相关设定值的结构体 +* 输 出: 无 +* 注意事项: 无 ******************************************************************************************************************************************/ void SPI_Init(SPI_TypeDef *SPIx, SPI_InitStructure *initStruct) { @@ -39,23 +38,23 @@ void SPI_Init(SPI_TypeDef *SPIx, SPI_InitStructure *initStruct) break; case ((uint32_t)SPI1): - SYS->CLKEN |= (0x01 << SYS_CLKEN_SPI0_Pos); //��SPI0ʹ��ͬһλʱ��ʹ�� + SYS->CLKEN |= (0x01 << SYS_CLKEN_SPI0_Pos); //与SPI0使用同一位时钟使能 break; } - SPI_Close(SPIx); //һЩ�ؼ��Ĵ���ֻ����SPI�ر�ʱ���� + SPI_Close(SPIx); //一些关键寄存器只能在SPI关闭时设置 SPIx->CTRL &= ~(SPI_CTRL_FFS_Msk | SPI_CTRL_CPHA_Msk | SPI_CTRL_CPOL_Msk | SPI_CTRL_SIZE_Msk | SPI_CTRL_MSTR_Msk | SPI_CTRL_CLKDIV_Msk | SPI_CTRL_SSN_H_Msk); - SPIx->CTRL |= (initStruct->FrameFormat << SPI_CTRL_FFS_Pos) | - (initStruct->SampleEdge << SPI_CTRL_CPHA_Pos) | - (initStruct->IdleLevel << SPI_CTRL_CPOL_Pos) | - ((initStruct->WordSize - 1) << SPI_CTRL_SIZE_Pos) | - (initStruct->Master << SPI_CTRL_MSTR_Pos) | - (initStruct->clkDiv << SPI_CTRL_CLKDIV_Pos) | - (0 << SPI_CTRL_SSN_H_Pos); + SPIx->CTRL |= (initStruct->FrameFormat << SPI_CTRL_FFS_Pos) | + (initStruct->SampleEdge << SPI_CTRL_CPHA_Pos) | + (initStruct->IdleLevel << SPI_CTRL_CPOL_Pos) | + ((initStruct->WordSize - 1) << SPI_CTRL_SIZE_Pos) | + (initStruct->Master << SPI_CTRL_MSTR_Pos) | + (initStruct->clkDiv << SPI_CTRL_CLKDIV_Pos) | + (0 << SPI_CTRL_SSN_H_Pos); - SPIx->IF = (0x01 << SPI_IF_RFOVF_Pos); //����жϱ�־ + SPIx->IF = (0x01 << SPI_IF_RFOVF_Pos); //清除中断标志 SPIx->IE &= ~(SPI_IE_RFHF_Msk | SPI_IE_TFHF_Msk | SPI_IE_FTC_Msk); SPIx->IE |= (initStruct->RXHFullIEn << SPI_IE_RFHF_Pos) | (initStruct->TXEmptyIEn << SPI_IE_TFHF_Pos) | @@ -88,11 +87,11 @@ void SPI_Init(SPI_TypeDef *SPIx, SPI_InitStructure *initStruct) } /****************************************************************************************************************************************** -* ��������: SPI_Open() -* ����˵��: SPI�������շ� -* �� ��: SPI_TypeDef * SPIx ָ��Ҫ�����õ�SPI����Чֵ����SPI0��SPI1 -* �� ��: �� -* ע������: �� +* 函数名称: SPI_Open() +* 功能说明: SPI打开，允许收发 +* 输 入: SPI_TypeDef * SPIx 指定要被设置的SPI，有效值包括SPI0、SPI1 +* 输 出: 无 +* 注意事项: 无 ******************************************************************************************************************************************/ void SPI_Open(SPI_TypeDef *SPIx) { @@ -100,11 +99,11 @@ void SPI_Open(SPI_TypeDef *SPIx) } /****************************************************************************************************************************************** -* ��������: SPI_Close() -* ����˵��: SPI�رգ���ֹ�շ� -* �� ��: SPI_TypeDef * SPIx ָ��Ҫ�����õ�SPI����Чֵ����SPI0��SPI1 -* �� ��: �� -* ע������: �� +* 函数名称: SPI_Close() +* 功能说明: SPI关闭，禁止收发 +* 输 入: SPI_TypeDef * SPIx 指定要被设置的SPI，有效值包括SPI0、SPI1 +* 输 出: 无 +* 注意事项: 无 ******************************************************************************************************************************************/ void SPI_Close(SPI_TypeDef *SPIx) { @@ -112,11 +111,11 @@ void SPI_Close(SPI_TypeDef *SPIx) } /****************************************************************************************************************************************** -* ��������: SPI_Read() -* ����˵��: ��ȡһ������ -* �� ��: SPI_TypeDef * SPIx ָ��Ҫ�����õ�SPI����Чֵ����SPI0��SPI1 -* �� ��: uint32_t ��ȡ�������� -* ע������: �� +* 函数名称: SPI_Read() +* 功能说明: 读取一个数据 +* 输 入: SPI_TypeDef * SPIx 指定要被设置的SPI，有效值包括SPI0、SPI1 +* 输 出: uint32_t 读取到的数据 +* 注意事项: 无 ******************************************************************************************************************************************/ uint32_t SPI_Read(SPI_TypeDef *SPIx) { @@ -124,12 +123,12 @@ uint32_t SPI_Read(SPI_TypeDef *SPIx) } /****************************************************************************************************************************************** -* ��������: SPI_Write() -* ����˵��: д��һ������ -* �� ��: SPI_TypeDef * SPIx ָ��Ҫ�����õ�SPI����Чֵ����SPI0��SPI1 -* uint32_t Ҫд������� -* �� ��: �� -* ע������: �� +* 函数名称: SPI_Write() +* 功能说明: 写入一个数据 +* 输 入: SPI_TypeDef * SPIx 指定要被设置的SPI，有效值包括SPI0、SPI1 +* uint32_t 要写入的数据 +* 输 出: 无 +* 注意事项: 无 ******************************************************************************************************************************************/ void SPI_Write(SPI_TypeDef *SPIx, uint32_t data) { @@ -137,12 +136,12 @@ void SPI_Write(SPI_TypeDef *SPIx, uint32_t data) } /****************************************************************************************************************************************** -* ��������: SPI_WriteWithWait() -* ����˵��: д��һ�����ݲ��ȴ�������ȫ���ͳ�ȥ -* �� ��: SPI_TypeDef * SPIx ָ��Ҫ�����õ�SPI����Чֵ����SPI0��SPI1��SPI1 -* uint32_t Ҫд������� -* �� ��: �� -* ע������: �� +* 函数名称: SPI_WriteWithWait() +* 功能说明: 写入一个数据并等待数据完全发送出去 +* 输 入: SPI_TypeDef * SPIx 指定要被设置的SPI，有效值包括SPI0、SPI1、SPI1 +* uint32_t 要写入的数据 +* 输 出: 无 +* 注意事项: 无 ******************************************************************************************************************************************/ void SPI_WriteWithWait(SPI_TypeDef *SPIx, uint32_t data) { @@ -150,31 +149,33 @@ void SPI_WriteWithWait(SPI_TypeDef *SPIx, uint32_t data) SPIx->DATA = data; - while ((SPIx->STAT & SPI_STAT_WTC_Msk) == 0); + while ((SPIx->STAT & SPI_STAT_WTC_Msk) == 0) + ; } /****************************************************************************************************************************************** -* ��������: SPI_ReadWrite() -* ����˵��: ����һ�����ݣ������ط������н��յ��� -* �� ��: SPI_TypeDef * SPIx ָ��Ҫ�����õ�SPI����Чֵ����SPI0��SPI1 -* uint32_t data Ҫ���͵����� -* �� ��: uint32_t ���յ������� -* ע������: ����ͬһ��SPIģ�飬�˺�����Ӧ��SPI_Write()�����ã���ΪSPI_Write()�����SPI_STAT_RFNE״̬ +* 函数名称: SPI_ReadWrite() +* 功能说明: 发送一个数据，并返回发送过程中接收到的 +* 输 入: SPI_TypeDef * SPIx 指定要被设置的SPI，有效值包括SPI0、SPI1 +* uint32_t data 要发送的数据 +* 输 出: uint32_t 接收到的数据 +* 注意事项: 对于同一个SPI模块，此函数不应与SPI_Write()混着用，因为SPI_Write()不清除SPI_STAT_RFNE状态 ******************************************************************************************************************************************/ uint32_t SPI_ReadWrite(SPI_TypeDef *SPIx, uint32_t data) { SPIx->DATA = data; - while (!(SPIx->STAT & SPI_STAT_RFNE_Msk)); + while (!(SPIx->STAT & SPI_STAT_RFNE_Msk)) + ; return SPIx->DATA; } /****************************************************************************************************************************************** -* ��������: SPI_IsRXEmpty() -* ����˵��: ����FIFO�Ƿ�գ������������Լ���SPI_Read() -* �� ��: SPI_TypeDef * SPIx ָ��Ҫ�����õ�SPI����Чֵ����SPI0��SPI1 -* �� ��: uint32_t 1 ����FIFO�� 0 ����FIFO�ǿ� -* ע������: �� +* 函数名称: SPI_IsRXEmpty() +* 功能说明: 接收FIFO是否空，如果不空则可以继续SPI_Read() +* 输 入: SPI_TypeDef * SPIx 指定要被设置的SPI，有效值包括SPI0、SPI1 +* 输 出: uint32_t 1 接收FIFO空 0 接收FIFO非空 +* 注意事项: 无 ******************************************************************************************************************************************/ uint32_t SPI_IsRXEmpty(SPI_TypeDef *SPIx) { @@ -182,11 +183,11 @@ uint32_t SPI_IsRXEmpty(SPI_TypeDef *SPIx) } /****************************************************************************************************************************************** -* ��������: SPI_IsTXFull() -* ����˵��: ����FIFO�Ƿ����������������Լ���SPI_Write() -* �� ��: SPI_TypeDef * SPIx ָ��Ҫ�����õ�SPI����Чֵ����SPI0��SPI1 -* �� ��: uint32_t 1 ����FIFO�� 0 ����FIFO���� -* ע������: �� +* 函数名称: SPI_IsTXFull() +* 功能说明: 发送FIFO是否满，如果不满则可以继续SPI_Write() +* 输 入: SPI_TypeDef * SPIx 指定要被设置的SPI，有效值包括SPI0、SPI1 +* 输 出: uint32_t 1 发送FIFO满 0 发送FIFO不满 +* 注意事项: 无 ******************************************************************************************************************************************/ uint32_t SPI_IsTXFull(SPI_TypeDef *SPIx) { @@ -194,24 +195,23 @@ uint32_t SPI_IsTXFull(SPI_TypeDef *SPIx) } /****************************************************************************************************************************************** -* ��������: SPI_IsTXEmpty() -* ����˵��: ����FIFO�Ƿ�� -* �� ��: SPI_TypeDef * SPIx ָ��Ҫ�����õ�SPI����Чֵ����SPI0��SPI1 -* �� ��: uint32_t 1 ����FIFO�� 0 ����FIFO�ǿ� -* ע������: �� +* 函数名称: SPI_IsTXEmpty() +* 功能说明: 发送FIFO是否空 +* 输 入: SPI_TypeDef * SPIx 指定要被设置的SPI，有效值包括SPI0、SPI1 +* 输 出: uint32_t 1 发送FIFO空 0 发送FIFO非空 +* 注意事项: 无 ******************************************************************************************************************************************/ uint32_t SPI_IsTXEmpty(SPI_TypeDef *SPIx) { return (SPIx->STAT & SPI_STAT_TFE_Msk) ? 1 : 0; } - /****************************************************************************************************************************************** -* ��������: SPI_INTRXHalfFullEn() -* ����˵��: ����FIFO�����ж�ʹ�� -* �� ��: SPI_TypeDef * SPIx ָ��Ҫ�����õ�SPI����Чֵ����SPI0��SPI1 -* �� ��: �� -* ע������: �� +* 函数名称: SPI_INTRXHalfFullEn() +* 功能说明: 接收FIFO半满中断使能 +* 输 入: SPI_TypeDef * SPIx 指定要被设置的SPI，有效值包括SPI0、SPI1 +* 输 出: 无 +* 注意事项: 无 ******************************************************************************************************************************************/ void SPI_INTRXHalfFullEn(SPI_TypeDef *SPIx) { @@ -219,11 +219,11 @@ void SPI_INTRXHalfFullEn(SPI_TypeDef *SPIx) } /****************************************************************************************************************************************** -* ��������: SPI_INTRXHalfFullDis() -* ����˵��: ����FIFO�����жϽ�ֹ -* �� ��: SPI_TypeDef * SPIx ָ��Ҫ�����õ�SPI����Чֵ����SPI0��SPI1 -* �� ��: �� -* ע������: �� +* 函数名称: SPI_INTRXHalfFullDis() +* 功能说明: 接收FIFO半满中断禁止 +* 输 入: SPI_TypeDef * SPIx 指定要被设置的SPI，有效值包括SPI0、SPI1 +* 输 出: 无 +* 注意事项: 无 ******************************************************************************************************************************************/ void SPI_INTRXHalfFullDis(SPI_TypeDef *SPIx) { @@ -231,11 +231,23 @@ void SPI_INTRXHalfFullDis(SPI_TypeDef *SPIx) } /****************************************************************************************************************************************** -* ��������: SPI_INTRXHalfFullStat() -* ����˵��: ����FIFO�����ж�״̬ -* �� ��: SPI_TypeDef * SPIx ָ��Ҫ�����õ�SPI����Чֵ����SPI0��SPI1 -* �� ��: uint32_t 1 ����FIFO�ﵽ���� 0 ����FIFOδ�ﵽ���� -* ע������: �� +* 函数名称: SPI_INTRXHalfFullClr() +* 功能说明: 接收FIFO半满中断标志清除 +* 输 入: SPI_TypeDef * SPIx 指定要被设置的SPI，有效值包括SPI0、SPI1 +* 输 出: 无 +* 注意事项: 无 +******************************************************************************************************************************************/ +void SPI_INTRXHalfFullClr(SPI_TypeDef *SPIx) +{ + SPIx->IF = (1 << SPI_IF_RFHF_Pos); +} + +/****************************************************************************************************************************************** +* 函数名称: SPI_INTRXHalfFullStat() +* 功能说明: 接收FIFO半满中断状态 +* 输 入: SPI_TypeDef * SPIx 指定要被设置的SPI，有效值包括SPI0、SPI1 +* 输 出: uint32_t 1 接收FIFO达到半满 0 接收FIFO未达到半满 +* 注意事项: 无 ******************************************************************************************************************************************/ uint32_t SPI_INTRXHalfFullStat(SPI_TypeDef *SPIx) { @@ -243,11 +255,11 @@ uint32_t SPI_INTRXHalfFullStat(SPI_TypeDef *SPIx) } /****************************************************************************************************************************************** -* ��������: SPI_INTRXFullEn() -* ����˵��: ����FIFO���ж�ʹ�� -* �� ��: SPI_TypeDef * SPIx ָ��Ҫ�����õ�SPI����Чֵ����SPI0��SPI1 -* �� ��: �� -* ע������: �� +* 函数名称: SPI_INTRXFullEn() +* 功能说明: 接收FIFO满中断使能 +* 输 入: SPI_TypeDef * SPIx 指定要被设置的SPI，有效值包括SPI0、SPI1 +* 输 出: 无 +* 注意事项: 无 ******************************************************************************************************************************************/ void SPI_INTRXFullEn(SPI_TypeDef *SPIx) { @@ -255,11 +267,11 @@ void SPI_INTRXFullEn(SPI_TypeDef *SPIx) } /****************************************************************************************************************************************** -* ��������: SPI_INTRXFullDis() -* ����˵��: ����FIFO���жϽ�ֹ -* �� ��: SPI_TypeDef * SPIx ָ��Ҫ�����õ�SPI����Чֵ����SPI0��SPI1 -* �� ��: �� -* ע������: �� +* 函数名称: SPI_INTRXFullDis() +* 功能说明: 接收FIFO满中断禁止 +* 输 入: SPI_TypeDef * SPIx 指定要被设置的SPI，有效值包括SPI0、SPI1 +* 输 出: 无 +* 注意事项: 无 ******************************************************************************************************************************************/ void SPI_INTRXFullDis(SPI_TypeDef *SPIx) { @@ -267,11 +279,23 @@ void SPI_INTRXFullDis(SPI_TypeDef *SPIx) } /****************************************************************************************************************************************** -* ��������: SPI_INTRXFullStat() -* ����˵��: ����FIFO���ж�״̬ -* �� ��: SPI_TypeDef * SPIx ָ��Ҫ�����õ�SPI����Чֵ����SPI0��SPI1 -* �� ��: uint32_t 1 ����FIFO�� 0 ����FIFOδ�� -* ע������: �� +* 函数名称: SPI_INTRXFullClr() +* 功能说明: 接收FIFO满中断标志清除 +* 输 入: SPI_TypeDef * SPIx 指定要被设置的SPI，有效值包括SPI0、SPI1 +* 输 出: 无 +* 注意事项: 无 +******************************************************************************************************************************************/ +void SPI_INTRXFullClr(SPI_TypeDef *SPIx) +{ + SPIx->IF = (1 << SPI_IF_RFF_Pos); +} + +/****************************************************************************************************************************************** +* 函数名称: SPI_INTRXFullStat() +* 功能说明: 接收FIFO满中断状态 +* 输 入: SPI_TypeDef * SPIx 指定要被设置的SPI，有效值包括SPI0、SPI1 +* 输 出: uint32_t 1 接收FIFO满 0 接收FIFO未满 +* 注意事项: 无 ******************************************************************************************************************************************/ uint32_t SPI_INTRXFullStat(SPI_TypeDef *SPIx) { @@ -279,11 +303,11 @@ uint32_t SPI_INTRXFullStat(SPI_TypeDef *SPIx) } /****************************************************************************************************************************************** -* ��������: SPI_INTRXOverflowEn() -* ����˵��: ����FIFO����ж�ʹ�� -* �� ��: SPI_TypeDef * SPIx ָ��Ҫ�����õ�SPI����Чֵ����SPI0��SPI1 -* �� ��: �� -* ע������: �� +* 函数名称: SPI_INTRXOverflowEn() +* 功能说明: 接收FIFO溢出中断使能 +* 输 入: SPI_TypeDef * SPIx 指定要被设置的SPI，有效值包括SPI0、SPI1 +* 输 出: 无 +* 注意事项: 无 ******************************************************************************************************************************************/ void SPI_INTRXOverflowEn(SPI_TypeDef *SPIx) { @@ -291,11 +315,11 @@ void SPI_INTRXOverflowEn(SPI_TypeDef *SPIx) } /****************************************************************************************************************************************** -* ��������: SPI_INTRXOverflowDis() -* ����˵��: ����FIFO����жϽ�ֹ -* �� ��: SPI_TypeDef * SPIx ָ��Ҫ�����õ�SPI����Чֵ����SPI0��SPI1 -* �� ��: �� -* ע������: �� +* 函数名称: SPI_INTRXOverflowDis() +* 功能说明: 接收FIFO溢出中断禁止 +* 输 入: SPI_TypeDef * SPIx 指定要被设置的SPI，有效值包括SPI0、SPI1 +* 输 出: 无 +* 注意事项: 无 ******************************************************************************************************************************************/ void SPI_INTRXOverflowDis(SPI_TypeDef *SPIx) { @@ -303,11 +327,11 @@ void SPI_INTRXOverflowDis(SPI_TypeDef *SPIx) } /****************************************************************************************************************************************** -* ��������: SPI_INTRXOverflowClr() -* ����˵��: ����FIFO����жϱ�־��� -* �� ��: SPI_TypeDef * SPIx ָ��Ҫ�����õ�SPI����Чֵ����SPI0��SPI1 -* �� ��: �� -* ע������: �� +* 函数名称: SPI_INTRXOverflowClr() +* 功能说明: 接收FIFO溢出中断标志清除 +* 输 入: SPI_TypeDef * SPIx 指定要被设置的SPI，有效值包括SPI0、SPI1 +* 输 出: 无 +* 注意事项: 无 ******************************************************************************************************************************************/ void SPI_INTRXOverflowClr(SPI_TypeDef *SPIx) { @@ -315,11 +339,11 @@ void SPI_INTRXOverflowClr(SPI_TypeDef *SPIx) } /****************************************************************************************************************************************** -* ��������: SPI_INTRXOverflowStat() -* ����˵��: ����FIFO����ж�״̬ -* �� ��: SPI_TypeDef * SPIx ָ��Ҫ�����õ�SPI����Чֵ����SPI0��SPI1 -* �� ��: uint32_t 1 ����FIFO��� 0 ����FIFOδ��� -* ע������: �� +* 函数名称: SPI_INTRXOverflowStat() +* 功能说明: 接收FIFO溢出中断状态 +* 输 入: SPI_TypeDef * SPIx 指定要被设置的SPI，有效值包括SPI0、SPI1 +* 输 出: uint32_t 1 接收FIFO溢出 0 接收FIFO未溢出 +* 注意事项: 无 ******************************************************************************************************************************************/ uint32_t SPI_INTRXOverflowStat(SPI_TypeDef *SPIx) { @@ -327,11 +351,11 @@ uint32_t SPI_INTRXOverflowStat(SPI_TypeDef *SPIx) } /****************************************************************************************************************************************** -* ��������: SPI_INTTXHalfFullEn() -* ����˵��: ����FIFO�����ж�ʹ�� -* �� ��: SPI_TypeDef * SPIx ָ��Ҫ�����õ�SPI����Чֵ����SPI0��SPI1 -* �� ��: �� -* ע������: �� +* 函数名称: SPI_INTTXHalfFullEn() +* 功能说明: 发送FIFO半满中断使能 +* 输 入: SPI_TypeDef * SPIx 指定要被设置的SPI，有效值包括SPI0、SPI1 +* 输 出: 无 +* 注意事项: 无 ******************************************************************************************************************************************/ void SPI_INTTXHalfFullEn(SPI_TypeDef *SPIx) { @@ -339,11 +363,11 @@ void SPI_INTTXHalfFullEn(SPI_TypeDef *SPIx) } /****************************************************************************************************************************************** -* ��������: SPI_INTTXHalfFullDis() -* ����˵��: ����FIFO�����жϽ�ֹ -* �� ��: SPI_TypeDef * SPIx ָ��Ҫ�����õ�SPI����Чֵ����SPI0��SPI1 -* �� ��: �� -* ע������: �� +* 函数名称: SPI_INTTXHalfFullDis() +* 功能说明: 发送FIFO半满中断禁止 +* 输 入: SPI_TypeDef * SPIx 指定要被设置的SPI，有效值包括SPI0、SPI1 +* 输 出: 无 +* 注意事项: 无 ******************************************************************************************************************************************/ void SPI_INTTXHalfFullDis(SPI_TypeDef *SPIx) { @@ -351,11 +375,23 @@ void SPI_INTTXHalfFullDis(SPI_TypeDef *SPIx) } /****************************************************************************************************************************************** -* ��������: SPI_INTTXHalfFullStat() -* ����˵��: ����FIFO�����ж�״̬ -* �� ��: SPI_TypeDef * SPIx ָ��Ҫ�����õ�SPI����Чֵ����SPI0��SPI1 -* �� ��: uint32_t 1 ����FIFO�ﵽ���� 0 ����FIFOδ�ﵽ���� -* ע������: �� +* 函数名称: SPI_INTTXHalfFullClr() +* 功能说明: 发送FIFO半满中断标志清除 +* 输 入: SPI_TypeDef * SPIx 指定要被设置的SPI，有效值包括SPI0、SPI1 +* 输 出: 无 +* 注意事项: 无 +******************************************************************************************************************************************/ +void SPI_INTTXHalfFullClr(SPI_TypeDef *SPIx) +{ + SPIx->IF = (1 << SPI_IF_TFHF_Pos); +} + +/****************************************************************************************************************************************** +* 函数名称: SPI_INTTXHalfFullStat() +* 功能说明: 发送FIFO半满中断状态 +* 输 入: SPI_TypeDef * SPIx 指定要被设置的SPI，有效值包括SPI0、SPI1 +* 输 出: uint32_t 1 发送FIFO达到半满 0 发送FIFO未达到半满 +* 注意事项: 无 ******************************************************************************************************************************************/ uint32_t SPI_INTTXHalfFullStat(SPI_TypeDef *SPIx) { @@ -363,11 +399,11 @@ uint32_t SPI_INTTXHalfFullStat(SPI_TypeDef *SPIx) } /****************************************************************************************************************************************** -* ��������: SPI_INTTXEmptyEn() -* ����˵��: ����FIFO���ж�ʹ�� -* �� ��: SPI_TypeDef * SPIx ָ��Ҫ�����õ�SPI����Чֵ����SPI0��SPI1 -* �� ��: �� -* ע������: �� +* 函数名称: SPI_INTTXEmptyEn() +* 功能说明: 发送FIFO空中断使能 +* 输 入: SPI_TypeDef * SPIx 指定要被设置的SPI，有效值包括SPI0、SPI1 +* 输 出: 无 +* 注意事项: 无 ******************************************************************************************************************************************/ void SPI_INTTXEmptyEn(SPI_TypeDef *SPIx) { @@ -375,11 +411,11 @@ void SPI_INTTXEmptyEn(SPI_TypeDef *SPIx) } /****************************************************************************************************************************************** -* ��������: SPI_INTTXEmptyDis() -* ����˵��: ����FIFO���жϽ�ֹ -* �� ��: SPI_TypeDef * SPIx ָ��Ҫ�����õ�SPI����Чֵ����SPI0��SPI1 -* �� ��: �� -* ע������: �� +* 函数名称: SPI_INTTXEmptyDis() +* 功能说明: 发送FIFO空中断禁止 +* 输 入: SPI_TypeDef * SPIx 指定要被设置的SPI，有效值包括SPI0、SPI1 +* 输 出: 无 +* 注意事项: 无 ******************************************************************************************************************************************/ void SPI_INTTXEmptyDis(SPI_TypeDef *SPIx) { @@ -387,11 +423,23 @@ void SPI_INTTXEmptyDis(SPI_TypeDef *SPIx) } /****************************************************************************************************************************************** -* ��������: SPI_INTTXEmptyStat() -* ����˵��: ����FIFO���ж�״̬ -* �� ��: SPI_TypeDef * SPIx ָ��Ҫ�����õ�SPI����Чֵ����SPI0��SPI1 -* �� ��: uint32_t 1 ����FIFO�� 0 ����FIFO�ǿ� -* ע������: �� +* 函数名称: SPI_INTTXEmptyClr() +* 功能说明: 发送FIFO空中断标志清除 +* 输 入: SPI_TypeDef * SPIx 指定要被设置的SPI，有效值包括SPI0、SPI1 +* 输 出: 无 +* 注意事项: 无 +******************************************************************************************************************************************/ +void SPI_INTTXEmptyClr(SPI_TypeDef *SPIx) +{ + SPIx->IF = (1 << SPI_IF_TFE_Pos); +} + +/****************************************************************************************************************************************** +* 函数名称: SPI_INTTXEmptyStat() +* 功能说明: 发送FIFO空中断状态 +* 输 入: SPI_TypeDef * SPIx 指定要被设置的SPI，有效值包括SPI0、SPI1 +* 输 出: uint32_t 1 发送FIFO空 0 发送FIFO非空 +* 注意事项: 无 ******************************************************************************************************************************************/ uint32_t SPI_INTTXEmptyStat(SPI_TypeDef *SPIx) { @@ -399,11 +447,11 @@ uint32_t SPI_INTTXEmptyStat(SPI_TypeDef *SPIx) } /****************************************************************************************************************************************** -* ��������: SPI_INTTXCompleteEn() -* ����˵��: ����FIFO���ҷ�����λ�Ĵ������ж�ʹ�� -* �� ��: SPI_TypeDef * SPIx ָ��Ҫ�����õ�SPI����Чֵ����SPI0��SPI1 -* �� ��: �� -* ע������: �� +* 函数名称: SPI_INTTXCompleteEn() +* 功能说明: 发送FIFO空且发送移位寄存器空中断使能 +* 输 入: SPI_TypeDef * SPIx 指定要被设置的SPI，有效值包括SPI0、SPI1 +* 输 出: 无 +* 注意事项: 无 ******************************************************************************************************************************************/ void SPI_INTTXCompleteEn(SPI_TypeDef *SPIx) { @@ -411,11 +459,11 @@ void SPI_INTTXCompleteEn(SPI_TypeDef *SPIx) } /****************************************************************************************************************************************** -* ��������: SPI_INTTXCompleteDis() -* ����˵��: ����FIFO���ҷ�����λ�Ĵ������жϽ�ֹ -* �� ��: SPI_TypeDef * SPIx ָ��Ҫ�����õ�SPI����Чֵ����SPI0��SPI1 -* �� ��: �� -* ע������: �� +* 函数名称: SPI_INTTXCompleteDis() +* 功能说明: 发送FIFO空且发送移位寄存器空中断禁止 +* 输 入: SPI_TypeDef * SPIx 指定要被设置的SPI，有效值包括SPI0、SPI1 +* 输 出: 无 +* 注意事项: 无 ******************************************************************************************************************************************/ void SPI_INTTXCompleteDis(SPI_TypeDef *SPIx) { @@ -423,11 +471,11 @@ void SPI_INTTXCompleteDis(SPI_TypeDef *SPIx) } /****************************************************************************************************************************************** -* ��������: SPI_INTTXCompleteClr() -* ����˵��: ����FIFO���ҷ�����λ�Ĵ������ж�״̬��� -* �� ��: SPI_TypeDef * SPIx ָ��Ҫ�����õ�SPI����Чֵ����SPI0��SPI1 -* �� ��: �� -* ע������: �� +* 函数名称: SPI_INTTXCompleteClr() +* 功能说明: 发送FIFO空且发送移位寄存器空中断状态清除 +* 输 入: SPI_TypeDef * SPIx 指定要被设置的SPI，有效值包括SPI0、SPI1 +* 输 出: 无 +* 注意事项: 无 ******************************************************************************************************************************************/ void SPI_INTTXCompleteClr(SPI_TypeDef *SPIx) { @@ -435,13 +483,61 @@ void SPI_INTTXCompleteClr(SPI_TypeDef *SPIx) } /****************************************************************************************************************************************** -* ��������: SPI_INTTXCompleteStat() -* ����˵��: ����FIFO���ҷ�����λ�Ĵ������ж�״̬ -* �� ��: SPI_TypeDef * SPIx ָ��Ҫ�����õ�SPI����Чֵ����SPI0��SPI1 -* �� ��: uint32_t 1 ����FIFO���ҷ�����λ�Ĵ����� 0 ����FIFO������λ�Ĵ����ǿ� -* ע������: �� +* 函数名称: SPI_INTTXCompleteStat() +* 功能说明: 发送FIFO空且发送移位寄存器空中断状态 +* 输 入: SPI_TypeDef * SPIx 指定要被设置的SPI，有效值包括SPI0、SPI1 +* 输 出: uint32_t 1 发送FIFO空且发送移位寄存器空 0 发送FIFO或发送移位寄存器非空 +* 注意事项: 无 ******************************************************************************************************************************************/ uint32_t SPI_INTTXCompleteStat(SPI_TypeDef *SPIx) { return (SPIx->IF & SPI_IF_FTC_Msk) ? 1 : 0; } + +/****************************************************************************************************************************************** +* 函数名称: SPI_INTTXWordCompleteEn() +* 功能说明: 发送FIFO字发送完成中断使能 +* 输 入: SPI_TypeDef * SPIx 指定要被设置的SPI，有效值包括SPI0、SPI1 +* 输 出: 无 +* 注意事项: 无 +******************************************************************************************************************************************/ +void SPI_INTTXWordCompleteEn(SPI_TypeDef *SPIx) +{ + SPIx->IE |= (0x01 << SPI_IE_WTC_Pos); +} + +/****************************************************************************************************************************************** +* 函数名称: SPI_INTTXWordCompleteDis() +* 功能说明: 发送FIFO字发送完成中断禁止 +* 输 入: SPI_TypeDef * SPIx 指定要被设置的SPI，有效值包括SPI0、SPI1 +* 输 出: 无 +* 注意事项: 无 +******************************************************************************************************************************************/ +void SPI_INTTXWordCompleteDis(SPI_TypeDef *SPIx) +{ + SPIx->IE &= ~(0x01 << SPI_IE_WTC_Pos); +} + +/****************************************************************************************************************************************** +* 函数名称: SPI_INTTXWordCompleteClr() +* 功能说明: 发送FIFO字发送完成中断标志清除 +* 输 入: SPI_TypeDef * SPIx 指定要被设置的SPI，有效值包括SPI0、SPI1 +* 输 出: 无 +* 注意事项: 无 +******************************************************************************************************************************************/ +void SPI_INTTXWordCompleteClr(SPI_TypeDef *SPIx) +{ + SPIx->IF = (1 << SPI_IF_WTC_Pos); +} + +/****************************************************************************************************************************************** +* 函数名称: SPI_INTTXWordCompleteStat() +* 功能说明: 发送FIFO字发送完成中断状态 +* 输 入: SPI_TypeDef * SPIx 指定要被设置的SPI，有效值包括SPI0、SPI1 +* 输 出: uint32_t 1 发送完成中断已发生 0 发送完成中断未发生 +* 注意事项: 无 +******************************************************************************************************************************************/ +uint32_t SPI_INTTXWordCompleteStat(SPI_TypeDef *SPIx) +{ + return (SPIx->IF & SPI_IF_WTC_Msk) ? 1 : 0; +} diff --git a/bsp/swm320-lq100/Libraries/SWM320_StdPeriph_Driver/SWM320_spi.h b/bsp/swm320-lq100/Libraries/SWM320_StdPeriph_Driver/SWM320_spi.h index 3230c4a774..db024d6bca 100644 --- a/bsp/swm320-lq100/Libraries/SWM320_StdPeriph_Driver/SWM320_spi.h +++ b/bsp/swm320-lq100/Libraries/SWM320_StdPeriph_Driver/SWM320_spi.h @@ -3,57 +3,56 @@ typedef struct { - uint8_t FrameFormat; //֡��ʽ��SPI_FORMAT_SPI��SPI_FORMAT_TI_SSI - uint8_t SampleEdge; //��SPI֡��ʽ�£�ѡ�����ݲ������أ�SPI_FIRST_EDGE��SPI_SECOND_EDGE - uint8_t IdleLevel; //��SPI֡��ʽ�£�ѡ�����ʱ�������ݴ���ʱ��ʱ���ߵĵ�ƽ��SPI_LOW_LEVEL��SPI_HIGH_LEVEL - uint8_t WordSize; //�ֳ���, ��Чֵ4-16 - uint8_t Master; //1 ����ģʽ 0 �ӻ�ģʽ - uint8_t clkDiv; //SPI_CLK = SYS_CLK / clkDiv����Чֵ��SPI_CLKDIV_4��SPI_CLKDIV_8��... ... ��SPI_CLKDIV_512 + uint8_t FrameFormat; //帧格式：SPI_FORMAT_SPI、SPI_FORMAT_TI_SSI + uint8_t SampleEdge; //在SPI帧格式下，选择数据采样边沿：SPI_FIRST_EDGE、SPI_SECOND_EDGE + uint8_t IdleLevel; //在SPI帧格式下，选择空闲时（无数据传输时）时钟线的电平：SPI_LOW_LEVEL、SPI_HIGH_LEVEL + uint8_t WordSize; //字长度, 有效值4-16 + uint8_t Master; //1 主机模式 0 从机模式 + uint8_t clkDiv; //SPI_CLK = SYS_CLK / clkDiv，有效值：SPI_CLKDIV_4、SPI_CLKDIV_8、... ... 、SPI_CLKDIV_512 - uint8_t RXHFullIEn; //����FIFO�����ж�ʹ�� - uint8_t TXEmptyIEn; //����FIFO ���ж�ʹ�� - uint8_t TXCompleteIEn; //����FIFO ���ҷ�����λ�Ĵ������ж�ʹ�� + uint8_t RXHFullIEn; //接收FIFO半满中断使能 + uint8_t TXEmptyIEn; //发送FIFO 空中断使能 + uint8_t TXCompleteIEn; //发送FIFO 空且发送移位寄存器空中断使能 } SPI_InitStructure; -#define SPI_FORMAT_SPI 0 //Motorola SPI ��ʽ -#define SPI_FORMAT_TI_SSI 1 //TI SSI ��ʽ +#define SPI_FORMAT_SPI 0 //Motorola SPI 格式 +#define SPI_FORMAT_TI_SSI 1 //TI SSI 格式 -#define SPI_FIRST_EDGE 0 //��һ��ʱ���ؿ�ʼ���� -#define SPI_SECOND_EDGE 1 //�ڶ���ʱ���ؿ�ʼ���� +#define SPI_FIRST_EDGE 0 //第一个时钟沿开始采样 +#define SPI_SECOND_EDGE 1 //第二个时钟沿开始采样 -#define SPI_LOW_LEVEL 0 //����ʱʱ���߱��ֵ͵�ƽ -#define SPI_HIGH_LEVEL 1 //����ʱʱ���߱��ָߵ�ƽ +#define SPI_LOW_LEVEL 0 //空闲时时钟线保持低电平 +#define SPI_HIGH_LEVEL 1 //空闲时时钟线保持高电平 -#define SPI_CLKDIV_4 0 -#define SPI_CLKDIV_8 1 -#define SPI_CLKDIV_16 2 -#define SPI_CLKDIV_32 3 -#define SPI_CLKDIV_64 4 -#define SPI_CLKDIV_128 5 -#define SPI_CLKDIV_256 6 -#define SPI_CLKDIV_512 7 +#define SPI_CLKDIV_4 0 +#define SPI_CLKDIV_8 1 +#define SPI_CLKDIV_16 2 +#define SPI_CLKDIV_32 3 +#define SPI_CLKDIV_64 4 +#define SPI_CLKDIV_128 5 +#define SPI_CLKDIV_256 6 +#define SPI_CLKDIV_512 7 - - -void SPI_Init(SPI_TypeDef *SPIx, SPI_InitStructure *initStruct); //SPI��ʼ�� -void SPI_Open(SPI_TypeDef *SPIx); //SPI�������շ� -void SPI_Close(SPI_TypeDef *SPIx); //SPI�رգ���ֹ�շ� +void SPI_Init(SPI_TypeDef *SPIx, SPI_InitStructure *initStruct); //SPI初始化 +void SPI_Open(SPI_TypeDef *SPIx); //SPI打开，允许收发 +void SPI_Close(SPI_TypeDef *SPIx); //SPI关闭，禁止收发 uint32_t SPI_Read(SPI_TypeDef *SPIx); void SPI_Write(SPI_TypeDef *SPIx, uint32_t data); void SPI_WriteWithWait(SPI_TypeDef *SPIx, uint32_t data); uint32_t SPI_ReadWrite(SPI_TypeDef *SPIx, uint32_t data); -uint32_t SPI_IsRXEmpty(SPI_TypeDef *SPIx); //����FIFO�Ƿ�գ������������Լ���SPI_Read() -uint32_t SPI_IsTXFull(SPI_TypeDef *SPIx); //����FIFO�Ƿ����������������Լ���SPI_Write() -uint32_t SPI_IsTXEmpty(SPI_TypeDef *SPIx); //����FIFO�Ƿ�� - +uint32_t SPI_IsRXEmpty(SPI_TypeDef *SPIx); //接收FIFO是否空，如果不空则可以继续SPI_Read() +uint32_t SPI_IsTXFull(SPI_TypeDef *SPIx); //发送FIFO是否满，如果不满则可以继续SPI_Write() +uint32_t SPI_IsTXEmpty(SPI_TypeDef *SPIx); //发送FIFO是否空 void SPI_INTRXHalfFullEn(SPI_TypeDef *SPIx); void SPI_INTRXHalfFullDis(SPI_TypeDef *SPIx); +void SPI_INTRXHalfFullClr(SPI_TypeDef *SPIx); uint32_t SPI_INTRXHalfFullStat(SPI_TypeDef *SPIx); void SPI_INTRXFullEn(SPI_TypeDef *SPIx); void SPI_INTRXFullDis(SPI_TypeDef *SPIx); +void SPI_INTRXFullClr(SPI_TypeDef *SPIx); uint32_t SPI_INTRXFullStat(SPI_TypeDef *SPIx); void SPI_INTRXOverflowEn(SPI_TypeDef *SPIx); void SPI_INTRXOverflowDis(SPI_TypeDef *SPIx); @@ -62,14 +61,20 @@ uint32_t SPI_INTRXOverflowStat(SPI_TypeDef *SPIx); void SPI_INTTXHalfFullEn(SPI_TypeDef *SPIx); void SPI_INTTXHalfFullDis(SPI_TypeDef *SPIx); +void SPI_INTTXHalfFullClr(SPI_TypeDef *SPIx); uint32_t SPI_INTTXHalfFullStat(SPI_TypeDef *SPIx); void SPI_INTTXEmptyEn(SPI_TypeDef *SPIx); void SPI_INTTXEmptyDis(SPI_TypeDef *SPIx); +void SPI_INTTXEmptyClr(SPI_TypeDef *SPIx); uint32_t SPI_INTTXEmptyStat(SPI_TypeDef *SPIx); void SPI_INTTXCompleteEn(SPI_TypeDef *SPIx); void SPI_INTTXCompleteDis(SPI_TypeDef *SPIx); void SPI_INTTXCompleteClr(SPI_TypeDef *SPIx); uint32_t SPI_INTTXCompleteStat(SPI_TypeDef *SPIx); +void SPI_INTTXWordCompleteEn(SPI_TypeDef *SPIx); +void SPI_INTTXWordCompleteDis(SPI_TypeDef *SPIx); +void SPI_INTTXWordCompleteClr(SPI_TypeDef *SPIx); +uint32_t SPI_INTTXWordCompleteStat(SPI_TypeDef *SPIx); #endif //__SWM320_SPI_H__ diff --git a/bsp/swm320-lq100/Libraries/SWM320_StdPeriph_Driver/SWM320_sram.c b/bsp/swm320-lq100/Libraries/SWM320_StdPeriph_Driver/SWM320_sram.c new file mode 100644 index 0000000000..8d0ad56d90 --- /dev/null +++ b/bsp/swm320-lq100/Libraries/SWM320_StdPeriph_Driver/SWM320_sram.c @@ -0,0 +1,56 @@ +/****************************************************************************************************************************************** +* 文件名称: SWM320_sram.c +* 功能说明: SWM320单片机的SRAM驱动程序 +* 技术支持: http://www.synwit.com.cn/e/tool/gbook/?bid=1 +* 注意事项: +* 版本日期: V1.1.0 2017年10月25日 +* 升级记录: +* +* +******************************************************************************************************************************************* +* @attention +* +* THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS WITH CODING INFORMATION +* REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE TIME. AS A RESULT, SYNWIT SHALL NOT BE HELD LIABLE +* FOR ANY DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING FROM THE CONTENT +* OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE CODING INFORMATION CONTAINED HEREIN IN CONN- +* -ECTION WITH THEIR PRODUCTS. +* +* COPYRIGHT 2012 Synwit Technology +*******************************************************************************************************************************************/ +#include "SWM320.h" +#include "SWM320_sram.h" + +/****************************************************************************************************************************************** +* 函数名称: SRAM_Init() +* 功能说明: SRAM控制器初始化 +* 输 入: SRAM_InitStructure * initStruct 包含 SRAM 控制器相关设定值的结构体 +* 输 出: 无 +* 注意事项: 无 +******************************************************************************************************************************************/ +void SRAM_Init(SRAM_InitStructure *initStruct) +{ + uint32_t i; + + // 配置SRAM前需要刷新下SDRAM控制器 + do + { + SYS->CLKEN |= (1 << SYS_CLKEN_SDRAM_Pos); + + while (SDRAMC->REFDONE == 0) + ; + SDRAMC->REFRESH &= ~(1 << SDRAMC_REFRESH_EN_Pos); + + for (i = 0; i < 1000; i++) + __NOP(); + SYS->CLKEN &= ~(1 << SYS_CLKEN_SDRAM_Pos); + } while (0); + + SYS->CLKEN |= (1 << SYS_CLKEN_RAMC_Pos); + for (i = 0; i < 10; i++) + __NOP(); + + SRAMC->CR = (initStruct->ClkDiv << SRAMC_CR_RWTIME_Pos) | + (initStruct->DataWidth << SRAMC_CR_BYTEIF_Pos) | + (0 << SRAMC_CR_HBLBDIS_Pos); // 使能字节、半字访问 +} diff --git a/bsp/swm320-lq100/Libraries/SWM320_StdPeriph_Driver/SWM320_sram.h b/bsp/swm320-lq100/Libraries/SWM320_StdPeriph_Driver/SWM320_sram.h new file mode 100644 index 0000000000..ca3aa92dcc --- /dev/null +++ b/bsp/swm320-lq100/Libraries/SWM320_StdPeriph_Driver/SWM320_sram.h @@ -0,0 +1,29 @@ +#ifndef __SWM320_SRAM_H__ +#define __SWM320_SRAM_H__ + +typedef struct +{ + uint8_t ClkDiv; //SRAM_CLKDIV_5...SRAM_CLKDIV_16，根据SRAM芯片所能跑的最高频率选择合适分频 + uint8_t DataWidth; //SRAM_DATAWIDTH_8、SRAM_DATAWIDTH_16 +} SRAM_InitStructure; + +#define SRAM_CLKDIV_4 3 +#define SRAM_CLKDIV_5 4 +#define SRAM_CLKDIV_6 5 +#define SRAM_CLKDIV_7 6 +#define SRAM_CLKDIV_8 7 +#define SRAM_CLKDIV_9 8 +#define SRAM_CLKDIV_10 9 +#define SRAM_CLKDIV_11 10 +#define SRAM_CLKDIV_12 11 +#define SRAM_CLKDIV_13 12 +#define SRAM_CLKDIV_14 13 +#define SRAM_CLKDIV_15 14 +#define SRAM_CLKDIV_16 15 + +#define SRAM_DATAWIDTH_8 1 +#define SRAM_DATAWIDTH_16 0 + +void SRAM_Init(SRAM_InitStructure *initStruct); + +#endif //__SWM320_SRAM_H__ diff --git a/bsp/swm320-lq100/Libraries/SWM320_StdPeriph_Driver/SWM320_timr.c b/bsp/swm320-lq100/Libraries/SWM320_StdPeriph_Driver/SWM320_timr.c index 769cc2e779..6e51b0b868 100644 --- a/bsp/swm320-lq100/Libraries/SWM320_StdPeriph_Driver/SWM320_timr.c +++ b/bsp/swm320-lq100/Libraries/SWM320_StdPeriph_Driver/SWM320_timr.c @@ -1,10 +1,10 @@ /****************************************************************************************************************************************** -* �ļ�����: SWM320_timr.c -* ����˵��: SWM320��Ƭ���ļ�����/��ʱ������������ -* ����֧��: http://www.synwit.com.cn/e/tool/gbook/?bid=1 -* ע������: -* �汾����: V1.1.0 2017��10��25�� -* ������¼: +* 文件名称: SWM320_timr.c +* 功能说明: SWM320单片机的计数器/定时器功能驱动库 +* 技术支持: http://www.synwit.com.cn/e/tool/gbook/?bid=1 +* 注意事项: +* 版本日期: V1.1.0 2017年10月25日 +* 升级记录: * * ******************************************************************************************************************************************* @@ -21,22 +21,21 @@ #include "SWM320.h" #include "SWM320_timr.h" - /****************************************************************************************************************************************** -* ��������: TIMR_Init() -* ����˵��: TIMR��ʱ��/��������ʼ�� -* �� ��: TIMR_TypeDef * TIMRx ָ��Ҫ�����õĶ�ʱ������Чֵ����TIMR0��TIMR1��TIMR2��TIMR3��TIMR4��TIMR5 -* uint32_t mode TIMR_MODE_TIMER ��ʱ��ģʽ TIMR_MODE_COUNTER ������ģʽ -* uint32_t period ��ʱ/�������� -* uint32_t int_en �ж�ʹ�� -* �� ��: �� -* ע������: �� +* 函数名称: TIMR_Init() +* 功能说明: TIMR定时器/计数器初始化 +* 输 入: TIMR_TypeDef * TIMRx 指定要被设置的定时器，有效值包括TIMR0、TIMR1、TIMR2、TIMR3、TIMR4、TIMR5 +* uint32_t mode TIMR_MODE_TIMER 定时器模式 TIMR_MODE_COUNTER 计数器模式 +* uint32_t period 定时/计数周期 +* uint32_t int_en 中断使能 +* 输 出: 无 +* 注意事项: 无 ******************************************************************************************************************************************/ void TIMR_Init(TIMR_TypeDef *TIMRx, uint32_t mode, uint32_t period, uint32_t int_en) { SYS->CLKEN |= (0x01 << SYS_CLKEN_TIMR_Pos); - TIMR_Stop(TIMRx); //һЩ�ؼ��Ĵ���ֻ���ڶ�ʱ��ֹͣʱ���� + TIMR_Stop(TIMRx); //一些关键寄存器只能在定时器停止时设置 TIMRx->CTRL &= ~TIMR_CTRL_CLKSRC_Msk; TIMRx->CTRL |= mode << TIMR_CTRL_CLKSRC_Pos; @@ -46,11 +45,12 @@ void TIMR_Init(TIMR_TypeDef *TIMRx, uint32_t mode, uint32_t period, uint32_t int switch ((uint32_t)TIMRx) { case ((uint32_t)TIMR0): - TIMRG->IF = (1 << TIMRG_IF_TIMR0_Pos); //ʹ���ж�ǰ����жϱ�־ + TIMRG->IF = (1 << TIMRG_IF_TIMR0_Pos); //使能中断前清除中断标志 TIMRG->IE &= ~TIMRG_IE_TIMR0_Msk; TIMRG->IE |= (int_en << TIMRG_IE_TIMR0_Pos); - if (int_en) NVIC_EnableIRQ(TIMR0_IRQn); + if (int_en) + NVIC_EnableIRQ(TIMR0_IRQn); break; case ((uint32_t)TIMR1): @@ -58,7 +58,8 @@ void TIMR_Init(TIMR_TypeDef *TIMRx, uint32_t mode, uint32_t period, uint32_t int TIMRG->IE &= ~TIMRG_IE_TIMR1_Msk; TIMRG->IE |= (int_en << TIMRG_IE_TIMR1_Pos); - if (int_en) NVIC_EnableIRQ(TIMR1_IRQn); + if (int_en) + NVIC_EnableIRQ(TIMR1_IRQn); break; case ((uint32_t)TIMR2): @@ -66,7 +67,8 @@ void TIMR_Init(TIMR_TypeDef *TIMRx, uint32_t mode, uint32_t period, uint32_t int TIMRG->IE &= ~TIMRG_IE_TIMR2_Msk; TIMRG->IE |= (int_en << TIMRG_IE_TIMR2_Pos); - if (int_en) NVIC_EnableIRQ(TIMR2_IRQn); + if (int_en) + NVIC_EnableIRQ(TIMR2_IRQn); break; case ((uint32_t)TIMR3): @@ -74,7 +76,8 @@ void TIMR_Init(TIMR_TypeDef *TIMRx, uint32_t mode, uint32_t period, uint32_t int TIMRG->IE &= ~TIMRG_IE_TIMR3_Msk; TIMRG->IE |= (int_en << TIMRG_IE_TIMR3_Pos); - if (int_en) NVIC_EnableIRQ(TIMR3_IRQn); + if (int_en) + NVIC_EnableIRQ(TIMR3_IRQn); break; case ((uint32_t)TIMR4): @@ -82,7 +85,8 @@ void TIMR_Init(TIMR_TypeDef *TIMRx, uint32_t mode, uint32_t period, uint32_t int TIMRG->IE &= ~TIMRG_IE_TIMR4_Msk; TIMRG->IE |= (int_en << TIMRG_IE_TIMR4_Pos); - if (int_en) NVIC_EnableIRQ(TIMR4_IRQn); + if (int_en) + NVIC_EnableIRQ(TIMR4_IRQn); break; case ((uint32_t)TIMR5): @@ -90,17 +94,18 @@ void TIMR_Init(TIMR_TypeDef *TIMRx, uint32_t mode, uint32_t period, uint32_t int TIMRG->IE &= ~TIMRG_IE_TIMR5_Msk; TIMRG->IE |= (int_en << TIMRG_IE_TIMR5_Pos); - if (int_en) NVIC_EnableIRQ(TIMR5_IRQn); + if (int_en) + NVIC_EnableIRQ(TIMR5_IRQn); break; } } /****************************************************************************************************************************************** -* ��������: TIMR_Start() -* ����˵��: ������ʱ�����ӳ�ʼֵ��ʼ��ʱ/���� -* �� ��: TIMR_TypeDef * TIMRx ָ��Ҫ�����õĶ�ʱ������ȡֵ����TIMR0��TIMR1��TIMR2��TIMR3��TIMR4��TIMR5 -* �� ��: �� -* ע������: �� +* 函数名称: TIMR_Start() +* 功能说明: 启动定时器，从初始值开始计时/计数 +* 输 入: TIMR_TypeDef * TIMRx 指定要被设置的定时器，可取值包括TIMR0、TIMR1、TIMR2、TIMR3、TIMR4、TIMR5 +* 输 出: 无 +* 注意事项: 无 ******************************************************************************************************************************************/ void TIMR_Start(TIMR_TypeDef *TIMRx) { @@ -108,11 +113,11 @@ void TIMR_Start(TIMR_TypeDef *TIMRx) } /****************************************************************************************************************************************** -* ��������: TIMR_Stop() -* ����˵��: ֹͣ��ʱ�� -* �� ��: TIMR_TypeDef * TIMRx ָ��Ҫ�����õĶ�ʱ������ȡֵ����TIMR0��TIMR1��TIMR2��TIMR3��TIMR4��TIMR5 -* �� ��: �� -* ע������: �� +* 函数名称: TIMR_Stop() +* 功能说明: 停止定时器 +* 输 入: TIMR_TypeDef * TIMRx 指定要被设置的定时器，可取值包括TIMR0、TIMR1、TIMR2、TIMR3、TIMR4、TIMR5 +* 输 出: 无 +* 注意事项: 无 ******************************************************************************************************************************************/ void TIMR_Stop(TIMR_TypeDef *TIMRx) { @@ -120,11 +125,11 @@ void TIMR_Stop(TIMR_TypeDef *TIMRx) } /****************************************************************************************************************************************** -* ��������: TIMR_Halt() -* ����˵��: ��ͣ��ʱ��������ֵ���ֲ��� -* �� ��: TIMR_TypeDef * TIMRx ָ��Ҫ�����õĶ�ʱ������ȡֵ����TIMR0��TIMR1��TIMR2��TIMR3��TIMR4��TIMR5 -* �� ��: �� -* ע������: �� +* 函数名称: TIMR_Halt() +* 功能说明: 暂停定时器，计数值保持不变 +* 输 入: TIMR_TypeDef * TIMRx 指定要被设置的定时器，可取值包括TIMR0、TIMR1、TIMR2、TIMR3、TIMR4、TIMR5 +* 输 出: 无 +* 注意事项: 无 ******************************************************************************************************************************************/ void TIMR_Halt(TIMR_TypeDef *TIMRx) { @@ -157,11 +162,11 @@ void TIMR_Halt(TIMR_TypeDef *TIMRx) } /****************************************************************************************************************************************** -* ��������: TIMR_Resume() -* ����˵��: �ָ���ʱ��������ͣ���������� -* �� ��: TIMR_TypeDef * TIMRx ָ��Ҫ�����õĶ�ʱ������ȡֵ����TIMR0��TIMR1��TIMR2��TIMR3��TIMR4��TIMR5 -* �� ��: �� -* ע������: �� +* 函数名称: TIMR_Resume() +* 功能说明: 恢复定时器，从暂停处继续计数 +* 输 入: TIMR_TypeDef * TIMRx 指定要被设置的定时器，可取值包括TIMR0、TIMR1、TIMR2、TIMR3、TIMR4、TIMR5 +* 输 出: 无 +* 注意事项: 无 ******************************************************************************************************************************************/ void TIMR_Resume(TIMR_TypeDef *TIMRx) { @@ -194,12 +199,12 @@ void TIMR_Resume(TIMR_TypeDef *TIMRx) } /****************************************************************************************************************************************** -* ��������: TIMR_SetPeriod() -* ����˵��: ���ö�ʱ/�������� -* �� ��: TIMR_TypeDef * TIMRx ָ��Ҫ�����õĶ�ʱ������ȡֵ����TIMR0��TIMR1��TIMR2��TIMR3��TIMR4��TIMR5 -* uint32_t period ��ʱ/�������� -* �� ��: �� -* ע������: �� +* 函数名称: TIMR_SetPeriod() +* 功能说明: 设置定时/计数周期 +* 输 入: TIMR_TypeDef * TIMRx 指定要被设置的定时器，可取值包括TIMR0、TIMR1、TIMR2、TIMR3、TIMR4、TIMR5 +* uint32_t period 定时/计数周期 +* 输 出: 无 +* 注意事项: 无 ******************************************************************************************************************************************/ void TIMR_SetPeriod(TIMR_TypeDef *TIMRx, uint32_t period) { @@ -207,11 +212,11 @@ void TIMR_SetPeriod(TIMR_TypeDef *TIMRx, uint32_t period) } /****************************************************************************************************************************************** -* ��������: TIMR_GetPeriod() -* ����˵��: ��ȡ��ʱ/�������� -* �� ��: TIMR_TypeDef * TIMRx ָ��Ҫ�����õĶ�ʱ������ȡֵ����TIMR0��TIMR1��TIMR2��TIMR3��TIMR4��TIMR5 -* �� ��: uint32_t ��ǰ��ʱ/�������� -* ע������: �� +* 函数名称: TIMR_GetPeriod() +* 功能说明: 获取定时/计数周期 +* 输 入: TIMR_TypeDef * TIMRx 指定要被设置的定时器，可取值包括TIMR0、TIMR1、TIMR2、TIMR3、TIMR4、TIMR5 +* 输 出: uint32_t 当前定时/计数周期 +* 注意事项: 无 ******************************************************************************************************************************************/ uint32_t TIMR_GetPeriod(TIMR_TypeDef *TIMRx) { @@ -219,11 +224,11 @@ uint32_t TIMR_GetPeriod(TIMR_TypeDef *TIMRx) } /****************************************************************************************************************************************** -* ��������: TIMR_GetCurValue() -* ����˵��: ��ȡ��ǰ����ֵ -* �� ��: TIMR_TypeDef * TIMRx ָ��Ҫ�����õĶ�ʱ������ȡֵ����TIMR0��TIMR1��TIMR2��TIMR3��TIMR4��TIMR5 -* �� ��: uint32_t ��ǰ����ֵ -* ע������: �� +* 函数名称: TIMR_GetCurValue() +* 功能说明: 获取当前计数值 +* 输 入: TIMR_TypeDef * TIMRx 指定要被设置的定时器，可取值包括TIMR0、TIMR1、TIMR2、TIMR3、TIMR4、TIMR5 +* 输 出: uint32_t 当前计数值 +* 注意事项: 无 ******************************************************************************************************************************************/ uint32_t TIMR_GetCurValue(TIMR_TypeDef *TIMRx) { @@ -231,11 +236,11 @@ uint32_t TIMR_GetCurValue(TIMR_TypeDef *TIMRx) } /****************************************************************************************************************************************** -* ��������: TIMR_INTEn() -* ����˵��: ʹ���ж� -* �� ��: TIMR_TypeDef * TIMRx ָ��Ҫ�����õĶ�ʱ������ȡֵ����TIMR0��TIMR1��TIMR2��TIMR3��TIMR4��TIMR5 -* �� ��: �� -* ע������: �� +* 函数名称: TIMR_INTEn() +* 功能说明: 使能中断 +* 输 入: TIMR_TypeDef * TIMRx 指定要被设置的定时器，可取值包括TIMR0、TIMR1、TIMR2、TIMR3、TIMR4、TIMR5 +* 输 出: 无 +* 注意事项: 无 ******************************************************************************************************************************************/ void TIMR_INTEn(TIMR_TypeDef *TIMRx) { @@ -274,11 +279,11 @@ void TIMR_INTEn(TIMR_TypeDef *TIMRx) } /****************************************************************************************************************************************** -* ��������: TIMR_INTDis() -* ����˵��: �����ж� -* �� ��: TIMR_TypeDef * TIMRx ָ��Ҫ�����õĶ�ʱ������ȡֵ����TIMR0��TIMR1��TIMR2��TIMR3��TIMR4��TIMR5 -* �� ��: �� -* ע������: �� +* 函数名称: TIMR_INTDis() +* 功能说明: 禁能中断 +* 输 入: TIMR_TypeDef * TIMRx 指定要被设置的定时器，可取值包括TIMR0、TIMR1、TIMR2、TIMR3、TIMR4、TIMR5 +* 输 出: 无 +* 注意事项: 无 ******************************************************************************************************************************************/ void TIMR_INTDis(TIMR_TypeDef *TIMRx) { @@ -311,11 +316,11 @@ void TIMR_INTDis(TIMR_TypeDef *TIMRx) } /****************************************************************************************************************************************** -* ��������: TIMR_INTClr() -* ����˵��: ����жϱ�־ -* �� ��: TIMR_TypeDef * TIMRx ָ��Ҫ�����õĶ�ʱ������ȡֵ����TIMR0��TIMR1��TIMR2��TIMR3��TIMR4��TIMR5 -* �� ��: �� -* ע������: �� +* 函数名称: TIMR_INTClr() +* 功能说明: 清除中断标志 +* 输 入: TIMR_TypeDef * TIMRx 指定要被设置的定时器，可取值包括TIMR0、TIMR1、TIMR2、TIMR3、TIMR4、TIMR5 +* 输 出: 无 +* 注意事项: 无 ******************************************************************************************************************************************/ void TIMR_INTClr(TIMR_TypeDef *TIMRx) { @@ -348,11 +353,11 @@ void TIMR_INTClr(TIMR_TypeDef *TIMRx) } /****************************************************************************************************************************************** -* ��������: TIMR_INTStat() -* ����˵��: ��ȡ�ж�״̬ -* �� ��: TIMR_TypeDef * TIMRx ָ��Ҫ�����õĶ�ʱ������ȡֵ����TIMR0��TIMR1��TIMR2��TIMR3��TIMR4��TIMR5 -* �� ��: uint32_t 0 TIMRxδ�����ж� 1 TIMRx�������ж� -* ע������: �� +* 函数名称: TIMR_INTStat() +* 功能说明: 获取中断状态 +* 输 入: TIMR_TypeDef * TIMRx 指定要被设置的定时器，可取值包括TIMR0、TIMR1、TIMR2、TIMR3、TIMR4、TIMR5 +* 输 出: uint32_t 0 TIMRx未产生中断 1 TIMRx产生了中断 +* 注意事项: 无 ******************************************************************************************************************************************/ uint32_t TIMR_INTStat(TIMR_TypeDef *TIMRx) { @@ -379,3 +384,58 @@ uint32_t TIMR_INTStat(TIMR_TypeDef *TIMRx) return 0; } + +/****************************************************************************************************************************************** +* 函数名称: Pulse_Init() +* 功能说明: 脉宽测量功能初始化 +* 输 入: uint32_t pulse PULSE_LOW 测量低脉冲宽度 PULSE_HIGH 测量高脉冲宽度 +* uint32_t int_en 是否使能脉冲测量完成中断 +* 输 出: 无 +* 注意事项: 无 +******************************************************************************************************************************************/ +void Pulse_Init(uint32_t pulse, uint32_t int_en) +{ + SYS->CLKEN |= (0x01 << SYS_CLKEN_TIMR_Pos); + + TIMRG->PCTRL = (0 << TIMRG_PCTRL_CLKSRC_Pos) | // 系统时钟作为时钟源 + (pulse << TIMRG_PCTRL_HIGH_Pos) | + (0 << TIMRG_PCTRL_EN_Pos); + + TIMRG->IE |= (1 << TIMRG_IE_PULSE_Pos); //使能才能查询中断标志 + + if (int_en) + NVIC_EnableIRQ(PULSE_IRQn); +} + +/****************************************************************************************************************************************** +* 函数名称: Pulse_Start() +* 功能说明: 脉宽测量功能启动，测量到脉宽后会自动关闭测量功能 +* 输 入: 无 +* 输 出: 无 +* 注意事项: 无 +******************************************************************************************************************************************/ +void Pulse_Start(void) +{ + TIMRG->PCTRL |= (1 << TIMRG_PCTRL_EN_Pos); +} + +/****************************************************************************************************************************************** +* 函数名称: Pulse_Done() +* 功能说明: 脉宽测量是否完成 +* 输 入: 无 +* 输 出: uint32_t 1 测量已完成 0 测量未完成 +* 注意事项: 无 +******************************************************************************************************************************************/ +uint32_t Pulse_Done(void) +{ + if (TIMRG->IF & TIMRG_IF_PULSE_Msk) + { + TIMRG->IF = TIMRG_IF_PULSE_Msk; // 清除中断标志 + + return 1; + } + else + { + return 0; + } +} diff --git a/bsp/swm320-lq100/Libraries/SWM320_StdPeriph_Driver/SWM320_timr.h b/bsp/swm320-lq100/Libraries/SWM320_StdPeriph_Driver/SWM320_timr.h index f92c0eaa73..38eaffacd8 100644 --- a/bsp/swm320-lq100/Libraries/SWM320_StdPeriph_Driver/SWM320_timr.h +++ b/bsp/swm320-lq100/Libraries/SWM320_StdPeriph_Driver/SWM320_timr.h @@ -1,23 +1,29 @@ #ifndef __SWM320_TIMR_H__ #define __SWM320_TIMR_H__ -#define TIMR_MODE_TIMER 0 -#define TIMR_MODE_COUNTER 1 +#define TIMR_MODE_TIMER 0 +#define TIMR_MODE_COUNTER 1 -void TIMR_Init(TIMR_TypeDef *TIMRx, uint32_t mode, uint32_t period, uint32_t int_en); //��ʱ��/��������ʼ�� -void TIMR_Start(TIMR_TypeDef *TIMRx); //������ʱ�����ӳ�ʼֵ��ʼ��ʱ/���� -void TIMR_Stop(TIMR_TypeDef *TIMRx); //ֹͣ��ʱ�� -void TIMR_Halt(TIMR_TypeDef *TIMRx); //��ͣ��ʱ��������ֵ���ֲ��� -void TIMR_Resume(TIMR_TypeDef *TIMRx); //�ָ���ʱ��������ͣ���������� +void TIMR_Init(TIMR_TypeDef *TIMRx, uint32_t mode, uint32_t period, uint32_t int_en); //定时器/计数器初始化 +void TIMR_Start(TIMR_TypeDef *TIMRx); //启动定时器，从初始值开始计时/计数 +void TIMR_Stop(TIMR_TypeDef *TIMRx); //停止定时器 +void TIMR_Halt(TIMR_TypeDef *TIMRx); //暂停定时器，计数值保持不变 +void TIMR_Resume(TIMR_TypeDef *TIMRx); //恢复定时器，从暂停处继续计数 -void TIMR_SetPeriod(TIMR_TypeDef *TIMRx, uint32_t period); //���ö�ʱ/�������� -uint32_t TIMR_GetPeriod(TIMR_TypeDef *TIMRx); //��ȡ��ʱ/�������� -uint32_t TIMR_GetCurValue(TIMR_TypeDef *TIMRx); //��ȡ��ǰ����ֵ +void TIMR_SetPeriod(TIMR_TypeDef *TIMRx, uint32_t period); //设置定时/计数周期 +uint32_t TIMR_GetPeriod(TIMR_TypeDef *TIMRx); //获取定时/计数周期 +uint32_t TIMR_GetCurValue(TIMR_TypeDef *TIMRx); //获取当前计数值 -void TIMR_INTEn(TIMR_TypeDef *TIMRx); //ʹ���ж� -void TIMR_INTDis(TIMR_TypeDef *TIMRx); //�����ж� -void TIMR_INTClr(TIMR_TypeDef *TIMRx); //����жϱ�־ -uint32_t TIMR_INTStat(TIMR_TypeDef *TIMRx); //��ȡ�ж�״̬ +void TIMR_INTEn(TIMR_TypeDef *TIMRx); //使能中断 +void TIMR_INTDis(TIMR_TypeDef *TIMRx); //禁能中断 +void TIMR_INTClr(TIMR_TypeDef *TIMRx); //清除中断标志 +uint32_t TIMR_INTStat(TIMR_TypeDef *TIMRx); //获取中断状态 +#define PULSE_LOW 0 +#define PULSE_HIGH 1 + +void Pulse_Init(uint32_t pulse, uint32_t int_en); +void Pulse_Start(void); +uint32_t Pulse_Done(void); #endif //__SWM320_TIMR_H__ diff --git a/bsp/swm320-lq100/Libraries/SWM320_StdPeriph_Driver/SWM320_uart.c b/bsp/swm320-lq100/Libraries/SWM320_StdPeriph_Driver/SWM320_uart.c index 46242efa01..c60b7fa825 100644 --- a/bsp/swm320-lq100/Libraries/SWM320_StdPeriph_Driver/SWM320_uart.c +++ b/bsp/swm320-lq100/Libraries/SWM320_StdPeriph_Driver/SWM320_uart.c @@ -1,10 +1,10 @@ /****************************************************************************************************************************************** -* �ļ�����: SWM320_uart.c -* ����˵��: SWM320��Ƭ����UART���ڹ��������� -* ����֧��: http://www.synwit.com.cn/e/tool/gbook/?bid=1 -* ע������: û�б�дLIN������صĺ��� -* �汾����: V1.1.0 2017��10��25�� -* ������¼: +* 文件名称: SWM320_uart.c +* 功能说明: SWM320单片机的UART串口功能驱动库 +* 技术支持: http://www.synwit.com.cn/e/tool/gbook/?bid=1 +* 注意事项: 没有编写LIN功能相关的函数 +* 版本日期: V1.1.0 2017年10月25日 +* 升级记录: * * ******************************************************************************************************************************************* @@ -21,14 +21,13 @@ #include "SWM320.h" #include "SWM320_uart.h" - /****************************************************************************************************************************************** -* ��������: UART_Init() -* ����˵��: UART���ڳ�ʼ�� -* �� ��: UART_TypeDef * UARTx ָ��Ҫ�����õ�UART���ڣ���Чֵ����UART0��UART1��UART2��UART3 -* UART_InitStructure * initStruct ����UART��������趨ֵ�Ľṹ�� -* �� ��: �� -* ע������: �� +* 函数名称: UART_Init() +* 功能说明: UART串口初始化 +* 输 入: UART_TypeDef * UARTx 指定要被设置的UART串口，有效值包括UART0、UART1、UART2、UART3 +* UART_InitStructure * initStruct 包含UART串口相关设定值的结构体 +* 输 出: 无 +* 注意事项: 无 ******************************************************************************************************************************************/ void UART_Init(UART_TypeDef *UARTx, UART_InitStructure *initStruct) { @@ -51,7 +50,7 @@ void UART_Init(UART_TypeDef *UARTx, UART_InitStructure *initStruct) break; } - UART_Close(UARTx); //һЩ�ؼ��Ĵ���ֻ���ڴ��ڹر�ʱ���� + UART_Close(UARTx); //一些关键寄存器只能在串口关闭时设置 UARTx->CTRL |= (0x01 << UART_CTRL_BAUDEN_Pos); UARTx->BAUD &= ~UART_BAUD_BAUD_Msk; @@ -59,11 +58,29 @@ void UART_Init(UART_TypeDef *UARTx, UART_InitStructure *initStruct) UARTx->CTRL &= ~(UART_CTRL_DATA9b_Msk | UART_CTRL_PARITY_Msk | UART_CTRL_STOP2b_Msk); UARTx->CTRL |= (initStruct->DataBits << UART_CTRL_DATA9b_Pos) | - (initStruct->Parity << UART_CTRL_PARITY_Pos) | + (initStruct->Parity << UART_CTRL_PARITY_Pos) | (initStruct->StopBits << UART_CTRL_STOP2b_Pos); + /* 在SWM320中，当 RXLVL >= RXTHR 时触发中断，如果RXTHR设置为0的话，在未接收到数据时就会一直触发中断； + 其他芯片中，当 RXLVL > RXTHR 时触发中断，为解决SWM320中RXTHR不能为0的问题，并统一库函数API，这里将RXTHR设置值加一 + */ + switch ((uint32_t)UARTx) // 软件复位不能清零 NVIC 寄存器，若不手动清除，下面的代码清零 RXTHR 时会导致一直进入 ISR + { + case ((uint32_t)UART0): + NVIC_DisableIRQ(UART0_IRQn); + break; + case ((uint32_t)UART1): + NVIC_DisableIRQ(UART1_IRQn); + break; + case ((uint32_t)UART2): + NVIC_DisableIRQ(UART2_IRQn); + break; + case ((uint32_t)UART3): + NVIC_DisableIRQ(UART3_IRQn); + break; + } UARTx->FIFO &= ~(UART_FIFO_RXTHR_Msk | UART_FIFO_TXTHR_Msk); - UARTx->FIFO |= (initStruct->RXThreshold << UART_FIFO_RXTHR_Pos) | + UARTx->FIFO |= ((initStruct->RXThreshold + 1) << UART_FIFO_RXTHR_Pos) | (initStruct->TXThreshold << UART_FIFO_TXTHR_Pos); UARTx->CTRL &= ~UART_CTRL_TOTIME_Msk; @@ -123,11 +140,11 @@ void UART_Init(UART_TypeDef *UARTx, UART_InitStructure *initStruct) } /****************************************************************************************************************************************** -* ��������: UART_Open() -* ����˵��: UART���ڴ� -* �� ��: UART_TypeDef * UARTx ָ��Ҫ�����õ�UART���ڣ���Чֵ����UART0��UART1��UART2��UART3 -* �� ��: �� -* ע������: �� +* 函数名称: UART_Open() +* 功能说明: UART串口打开 +* 输 入: UART_TypeDef * UARTx 指定要被设置的UART串口，有效值包括UART0、UART1、UART2、UART3 +* 输 出: 无 +* 注意事项: 无 ******************************************************************************************************************************************/ void UART_Open(UART_TypeDef *UARTx) { @@ -135,11 +152,11 @@ void UART_Open(UART_TypeDef *UARTx) } /****************************************************************************************************************************************** -* ��������: UART_Close() -* ����˵��: UART���ڹر� -* �� ��: UART_TypeDef * UARTx ָ��Ҫ�����õ�UART���ڣ���Чֵ����UART0��UART1��UART2��UART3 -* �� ��: �� -* ע������: �� +* 函数名称: UART_Close() +* 功能说明: UART串口关闭 +* 输 入: UART_TypeDef * UARTx 指定要被设置的UART串口，有效值包括UART0、UART1、UART2、UART3 +* 输 出: 无 +* 注意事项: 无 ******************************************************************************************************************************************/ void UART_Close(UART_TypeDef *UARTx) { @@ -147,25 +164,25 @@ void UART_Close(UART_TypeDef *UARTx) } /****************************************************************************************************************************************** -* ��������: UART_WriteByte() -* ����˵��: ����һ���ֽ����� -* �� ��: UART_TypeDef * UARTx ָ��Ҫ�����õ�UART���ڣ���ȡֵ����UART0��UART1��UART2��UART3��UART4 -* uint8_t data Ҫ���͵��ֽ� -* �� ��: �� -* ע������: �� +* 函数名称: UART_WriteByte() +* 功能说明: 发送一个字节数据 +* 输 入: UART_TypeDef * UARTx 指定要被设置的UART串口，可取值包括UART0、UART1、UART2、UART3、UART4 +* uint32_t data 要发送的字节 +* 输 出: 无 +* 注意事项: 无 ******************************************************************************************************************************************/ -void UART_WriteByte(UART_TypeDef *UARTx, uint8_t data) +void UART_WriteByte(UART_TypeDef *UARTx, uint32_t data) { UARTx->DATA = data; } /****************************************************************************************************************************************** -* ��������: UART_ReadByte() -* ����˵��: ��ȡһ���ֽ����ݣ���ָ�������Ƿ�Valid -* �� ��: UART_TypeDef * UARTx ָ��Ҫ�����õ�UART���ڣ���ȡֵ����UART0��UART1��UART2��UART3��UART4 -* uint32_t * data ���յ������� -* �� ��: uint32_t 0 ���� UART_ERR_PARITY ��żУ����� -* ע������: �� +* 函数名称: UART_ReadByte() +* 功能说明: 读取一个字节数据，并指出数据是否Valid +* 输 入: UART_TypeDef * UARTx 指定要被设置的UART串口，可取值包括UART0、UART1、UART2、UART3、UART4 +* uint32_t * data 接收到的数据 +* 输 出: uint32_t 0 无错误 UART_ERR_PARITY 奇偶校验错误 +* 注意事项: 无 ******************************************************************************************************************************************/ uint32_t UART_ReadByte(UART_TypeDef *UARTx, uint32_t *data) { @@ -173,17 +190,18 @@ uint32_t UART_ReadByte(UART_TypeDef *UARTx, uint32_t *data) *data = (reg & UART_DATA_DATA_Msk); - if (reg & UART_DATA_PAERR_Msk) return UART_ERR_PARITY; + if (reg & UART_DATA_PAERR_Msk) + return UART_ERR_PARITY; return 0; } /****************************************************************************************************************************************** -* ��������: UART_IsTXBusy() -* ����˵��: UART�Ƿ����ڷ������� -* �� ��: UART_TypeDef * UARTx ָ��Ҫ�����õ�UART���ڣ���Чֵ����UART0��UART1��UART2��UART3 -* �� ��: uint32_t 1 UART���ڷ������� 0 �����ѷ��� -* ע������: �� +* 函数名称: UART_IsTXBusy() +* 功能说明: UART是否正在发送数据 +* 输 入: UART_TypeDef * UARTx 指定要被设置的UART串口，有效值包括UART0、UART1、UART2、UART3 +* 输 出: uint32_t 1 UART正在发送数据 0 数据已发完 +* 注意事项: 无 ******************************************************************************************************************************************/ uint32_t UART_IsTXBusy(UART_TypeDef *UARTx) { @@ -191,11 +209,11 @@ uint32_t UART_IsTXBusy(UART_TypeDef *UARTx) } /****************************************************************************************************************************************** -* ��������: UART_IsRXFIFOEmpty() -* ����˵��: ����FIFO�Ƿ�Ϊ�գ����������˵�����������ݿ��Զ�ȡ -* �� ��: UART_TypeDef * UARTx ָ��Ҫ�����õ�UART���ڣ���Чֵ����UART0��UART1��UART2��UART3 -* �� ��: uint32_t 1 ����FIFO�� 0 ����FIFO�ǿ� -* ע������: �� +* 函数名称: UART_IsRXFIFOEmpty() +* 功能说明: 接收FIFO是否为空，如果不空则说明其中有数据可以读取 +* 输 入: UART_TypeDef * UARTx 指定要被设置的UART串口，有效值包括UART0、UART1、UART2、UART3 +* 输 出: uint32_t 1 接收FIFO空 0 接收FIFO非空 +* 注意事项: 无 ******************************************************************************************************************************************/ uint32_t UART_IsRXFIFOEmpty(UART_TypeDef *UARTx) { @@ -203,11 +221,11 @@ uint32_t UART_IsRXFIFOEmpty(UART_TypeDef *UARTx) } /****************************************************************************************************************************************** -* ��������: UART_IsTXFIFOFull() -* ����˵��: ����FIFO�Ƿ�Ϊ���������������Լ���������д������ -* �� ��: UART_TypeDef * UARTx ָ��Ҫ�����õ�UART���ڣ���Чֵ����UART0��UART1��UART2��UART3 -* �� ��: uint32_t 1 ����FIFO�� 0 ����FIFO���� -* ע������: �� +* 函数名称: UART_IsTXFIFOFull() +* 功能说明: 发送FIFO是否为满，如果不满则可以继续向其中写入数据 +* 输 入: UART_TypeDef * UARTx 指定要被设置的UART串口，有效值包括UART0、UART1、UART2、UART3 +* 输 出: uint32_t 1 发送FIFO满 0 发送FIFO不满 +* 注意事项: 无 ******************************************************************************************************************************************/ uint32_t UART_IsTXFIFOFull(UART_TypeDef *UARTx) { @@ -215,53 +233,53 @@ uint32_t UART_IsTXFIFOFull(UART_TypeDef *UARTx) } /****************************************************************************************************************************************** -* ��������: UART_SetBaudrate() -* ����˵��: ���ò����� -* �� ��: UART_TypeDef * UARTx ָ��Ҫ�����õ�UART���ڣ���Чֵ����UART0��UART1��UART2��UART3 -* uint32_t baudrate Ҫ���õIJ����� -* �� ��: �� -* ע������: ��Ҫ�ڴ��ڹ���ʱ���IJ����ʣ�ʹ�ô˺���ǰ���ȵ���UART_Close()�رմ��� +* 函数名称: UART_SetBaudrate() +* 功能说明: 设置波特率 +* 输 入: UART_TypeDef * UARTx 指定要被设置的UART串口，有效值包括UART0、UART1、UART2、UART3 +* uint32_t baudrate 要设置的波特率 +* 输 出: 无 +* 注意事项: 不要在串口工作时更改波特率，使用此函数前请先调用UART_Close()关闭串口 ******************************************************************************************************************************************/ void UART_SetBaudrate(UART_TypeDef *UARTx, uint32_t baudrate) { UARTx->BAUD &= ~UART_BAUD_BAUD_Msk; - UARTx->BAUD |= ((SystemCoreClock / 16 / baudrate) << UART_BAUD_BAUD_Pos); + UARTx->BAUD |= ((SystemCoreClock / 16 / baudrate - 1) << UART_BAUD_BAUD_Pos); } /****************************************************************************************************************************************** -* ��������: UART_GetBaudrate() -* ����˵��: ��ѯ������ -* �� ��: UART_TypeDef * UARTx ָ��Ҫ�����õ�UART���ڣ���Чֵ����UART0��UART1��UART2��UART3 -* �� ��: uint32_t ��ǰ������ -* ע������: �� +* 函数名称: UART_GetBaudrate() +* 功能说明: 查询波特率 +* 输 入: UART_TypeDef * UARTx 指定要被设置的UART串口，有效值包括UART0、UART1、UART2、UART3 +* 输 出: uint32_t 当前波特率 +* 注意事项: 无 ******************************************************************************************************************************************/ uint32_t UART_GetBaudrate(UART_TypeDef *UARTx) { - return (UARTx->BAUD & UART_BAUD_BAUD_Msk); + return SystemCoreClock / 16 / (((UARTx->BAUD & UART_BAUD_BAUD_Msk) >> UART_BAUD_BAUD_Pos) + 1); } /****************************************************************************************************************************************** -* ��������: UART_CTSConfig() -* ����˵��: UART CTS�������� -* �� ��: UART_TypeDef * UARTx ָ��Ҫ�����õ�UART���ڣ���Чֵ����UART0��UART1��UART2��UART3 -* uint32_t enable 1 ʹ��CTS���� 0 ��ֹCTS���� -* uint32_t polarity 0 CTS����Ϊ�ͱ�ʾ���Է������� 1 CTS����Ϊ�߱�ʾ���Է������� -* �� ��: �� -* ע������: �� +* 函数名称: UART_CTSConfig() +* 功能说明: UART CTS流控配置 +* 输 入: UART_TypeDef * UARTx 指定要被设置的UART串口，有效值包括UART0、UART1、UART2、UART3 +* uint32_t enable 1 使能CTS流控 0 禁止CTS流控 +* uint32_t polarity 0 CTS输入为低表示可以发送数据 1 CTS输入为高表示可以发送数据 +* 输 出: 无 +* 注意事项: 无 ******************************************************************************************************************************************/ void UART_CTSConfig(UART_TypeDef *UARTx, uint32_t enable, uint32_t polarity) { UARTx->CTSCR &= ~(UART_CTSCR_EN_Msk | UART_CTSCR_POL_Msk); - UARTx->CTSCR |= (enable << UART_CTSCR_EN_Pos) | + UARTx->CTSCR |= (enable << UART_CTSCR_EN_Pos) | (polarity << UART_CTSCR_POL_Pos); } /****************************************************************************************************************************************** -* ��������: UART_CTSLineState() -* ����˵��: UART CTS�ߵ�ǰ״̬ -* �� ��: UART_TypeDef * UARTx ָ��Ҫ�����õ�UART���ڣ���Чֵ����UART0��UART1��UART2��UART3 -* �� ��: uint32_t 0 CTS�ߵ�ǰΪ�͵�ƽ 1 CTS�ߵ�ǰΪ�ߵ�ƽ -* ע������: �� +* 函数名称: UART_CTSLineState() +* 功能说明: UART CTS线当前状态 +* 输 入: UART_TypeDef * UARTx 指定要被设置的UART串口，有效值包括UART0、UART1、UART2、UART3 +* 输 出: uint32_t 0 CTS线当前为低电平 1 CTS线当前为高电平 +* 注意事项: 无 ******************************************************************************************************************************************/ uint32_t UART_CTSLineState(UART_TypeDef *UARTx) { @@ -269,29 +287,29 @@ uint32_t UART_CTSLineState(UART_TypeDef *UARTx) } /****************************************************************************************************************************************** -* ��������: UART_RTSConfig() -* ����˵��: UART RTS�������� -* �� ��: UART_TypeDef * UARTx ָ��Ҫ�����õ�UART���ڣ���Чֵ����UART0��UART1��UART2��UART3 -* uint32_t enable 1 ʹ��RTS���� 0 ��ֹRTS���� -* uint32_t polarity 0 RTS����ͱ�ʾ���Խ������� 1 RTS����߱�ʾ���Խ������� -* uint32_t threshold RTS���صĴ�����ֵ����ȡֵUART_RTS_1BYTE��UART_RTS_2BYTE��UART_RTS_4BYTE��UART_RTS_6BYTE -* �� ��: �� -* ע������: �� +* 函数名称: UART_RTSConfig() +* 功能说明: UART RTS流控配置 +* 输 入: UART_TypeDef * UARTx 指定要被设置的UART串口，有效值包括UART0、UART1、UART2、UART3 +* uint32_t enable 1 使能RTS流控 0 禁止RTS流控 +* uint32_t polarity 0 RTS输出低表示可以接收数据 1 RTS输出高表示可以接收数据 +* uint32_t threshold RTS流控的触发阈值，可取值UART_RTS_1BYTE、UART_RTS_2BYTE、UART_RTS_4BYTE、UART_RTS_6BYTE +* 输 出: 无 +* 注意事项: 无 ******************************************************************************************************************************************/ void UART_RTSConfig(UART_TypeDef *UARTx, uint32_t enable, uint32_t polarity, uint32_t threshold) { UARTx->RTSCR &= ~(UART_RTSCR_EN_Msk | UART_RTSCR_POL_Msk | UART_RTSCR_THR_Msk); - UARTx->RTSCR |= (enable << UART_RTSCR_EN_Pos) | - (polarity << UART_RTSCR_POL_Pos) | + UARTx->RTSCR |= (enable << UART_RTSCR_EN_Pos) | + (polarity << UART_RTSCR_POL_Pos) | (threshold << UART_RTSCR_THR_Pos); } /****************************************************************************************************************************************** -* ��������: UART_RTSLineState() -* ����˵��: UART RTS�ߵ�ǰ״̬ -* �� ��: UART_TypeDef * UARTx ָ��Ҫ�����õ�UART���ڣ���Чֵ����UART0��UART1��UART2��UART3 -* �� ��: uint32_t 0 RTS�ߵ�ǰΪ�͵�ƽ 1 RTS�ߵ�ǰΪ�ߵ�ƽ -* ע������: �� +* 函数名称: UART_RTSLineState() +* 功能说明: UART RTS线当前状态 +* 输 入: UART_TypeDef * UARTx 指定要被设置的UART串口，有效值包括UART0、UART1、UART2、UART3 +* 输 出: uint32_t 0 RTS线当前为低电平 1 RTS线当前为高电平 +* 注意事项: 无 ******************************************************************************************************************************************/ uint32_t UART_RTSLineState(UART_TypeDef *UARTx) { @@ -299,27 +317,27 @@ uint32_t UART_RTSLineState(UART_TypeDef *UARTx) } /****************************************************************************************************************************************** -* ��������: UART_LINConfig() -* ����˵��: UART LIN�������� -* �� ��: UART_TypeDef * UARTx ָ��Ҫ�����õ�UART���ڣ���Чֵ����UART0��UART1��UART2��UART3 -* uint32_t detectedIEn ��Break�ж�ʹ�� -* uint32_t generatedIEn Break��������ж�ʹ�� -* �� ��: �� -* ע������: �� +* 函数名称: UART_LINConfig() +* 功能说明: UART LIN功能配置 +* 输 入: UART_TypeDef * UARTx 指定要被设置的UART串口，有效值包括UART0、UART1、UART2、UART3 +* uint32_t detectedIEn 检测到Break中断使能 +* uint32_t generatedIEn Break发送完成中断使能 +* 输 出: 无 +* 注意事项: 无 ******************************************************************************************************************************************/ void UART_LINConfig(UART_TypeDef *UARTx, uint32_t detectedIEn, uint32_t generatedIEn) { UARTx->LINCR &= ~(UART_LINCR_BRKDETIE_Msk | UART_LINCR_GENBRKIE_Msk); - UARTx->LINCR |= (detectedIEn << UART_LINCR_BRKDETIE_Pos) | + UARTx->LINCR |= (detectedIEn << UART_LINCR_BRKDETIE_Pos) | (generatedIEn << UART_LINCR_GENBRKIE_Pos); } /****************************************************************************************************************************************** -* ��������: UART_LINGenerate() -* ����˵��: UART LIN����/����Break -* �� ��: UART_TypeDef * UARTx ָ��Ҫ�����õ�UART���ڣ���Чֵ����UART0��UART1��UART2��UART3 -* �� ��: �� -* ע������: �� +* 函数名称: UART_LINGenerate() +* 功能说明: UART LIN产生/发送Break +* 输 入: UART_TypeDef * UARTx 指定要被设置的UART串口，有效值包括UART0、UART1、UART2、UART3 +* 输 出: 无 +* 注意事项: 无 ******************************************************************************************************************************************/ void UART_LINGenerate(UART_TypeDef *UARTx) { @@ -327,23 +345,23 @@ void UART_LINGenerate(UART_TypeDef *UARTx) } /****************************************************************************************************************************************** -* ��������: UART_LINIsDetected() -* ����˵��: UART LIN�Ƿ��Break -* �� ��: UART_TypeDef * UARTx ָ��Ҫ�����õ�UART���ڣ���Чֵ����UART0��UART1��UART2��UART3 -* �� ��: uint32_t 1 ��LIN Break 0 δ��LIN Break -* ע������: �� +* 函数名称: UART_LINIsDetected() +* 功能说明: UART LIN是否检测到Break +* 输 入: UART_TypeDef * UARTx 指定要被设置的UART串口，有效值包括UART0、UART1、UART2、UART3 +* 输 出: uint32_t 1 检测到LIN Break 0 未检测到LIN Break +* 注意事项: 无 ******************************************************************************************************************************************/ uint32_t UART_LINIsDetected(UART_TypeDef *UARTx) { - return (UARTx->LINCR & UART_LINCR_BRKDETIE_Msk) ? 1 : 0; + return (UARTx->LINCR & UART_LINCR_BRKDETIF_Msk) ? 1 : 0; } /****************************************************************************************************************************************** -* ��������: UART_LINIsGenerated() -* ����˵��: UART LIN Break�Ƿ������ -* �� ��: UART_TypeDef * UARTx ָ��Ҫ�����õ�UART���ڣ���Чֵ����UART0��UART1��UART2��UART3 -* �� ��: uint32_t 1 LIN Break ������� 0 LIN Break����δ��� -* ע������: �� +* 函数名称: UART_LINIsGenerated() +* 功能说明: UART LIN Break是否发送完成 +* 输 入: UART_TypeDef * UARTx 指定要被设置的UART串口，有效值包括UART0、UART1、UART2、UART3 +* 输 出: uint32_t 1 LIN Break 发送完成 0 LIN Break发送未完成 +* 注意事项: 无 ******************************************************************************************************************************************/ uint32_t UART_LINIsGenerated(UART_TypeDef *UARTx) { @@ -351,36 +369,42 @@ uint32_t UART_LINIsGenerated(UART_TypeDef *UARTx) } /****************************************************************************************************************************************** -* ��������: UART_ABRStart() -* ����˵��: UART �Զ������ʼ�ʼ -* �� ��: UART_TypeDef * UARTx ָ��Ҫ�����õ�UART���ڣ���Чֵ����UART0��UART1��UART2��UART3 -* uint32_t detectChar �����Զ���⡢���㲨���ʵļ���ַ� -* 8λ����ʱ��ȡֵ��0xFF��0xFE��0xF8��0x80���ֱ��ʾ���ͷ����뷢��0xFF��0xFE��0xF8��0x80 -* 9λ����ʱ��ȡֵ��0x1FF��0x1FE��0x1F8��0x180���ֱ��ʾ���ͷ����뷢��0x1FF��0x1FE��0x1F8��0x180 -* �� ��: �� -* ע������: �Զ������ʼ��ʱ���ܿ�����żУ�� +* 函数名称: UART_ABRStart() +* 功能说明: UART 自动波特率检测开始 +* 输 入: UART_TypeDef * UARTx 指定要被设置的UART串口，有效值包括UART0、UART1、UART2、UART3 +* uint32_t detectChar 用于自动检测、计算波特率的检测字符 +* 8位数据时可取值：0xFF、0xFE、0xF8、0x80，分别表示发送方必须发送0xFF、0xFE、0xF8、0x80 +* 9位数据时可取值：0x1FF、0x1FE、0x1F8、0x180，分别表示发送方必须发送0x1FF、0x1FE、0x1F8、0x180 +* 输 出: 无 +* 注意事项: 自动波特率检测时不能开启奇偶校验 ******************************************************************************************************************************************/ void UART_ABRStart(UART_TypeDef *UARTx, uint32_t detectChar) { uint32_t bits; - if ((detectChar == 0xFF) || (detectChar == 0x1FF)) bits = 0; - else if ((detectChar == 0xFE) || (detectChar == 0x1FE)) bits = 1; - else if ((detectChar == 0xF8) || (detectChar == 0x1F8)) bits = 2; - else if ((detectChar == 0x80) || (detectChar == 0x180)) bits = 3; - else while (1); + if ((detectChar == 0xFF) || (detectChar == 0x1FF)) + bits = 0; + else if ((detectChar == 0xFE) || (detectChar == 0x1FE)) + bits = 1; + else if ((detectChar == 0xF8) || (detectChar == 0x1F8)) + bits = 2; + else if ((detectChar == 0x80) || (detectChar == 0x180)) + bits = 3; + else + while (1) + ; UARTx->BAUD &= ~(UART_BAUD_ABREN_Msk | UART_BAUD_ABRBIT_Msk); - UARTx->BAUD |= (1 << UART_BAUD_ABREN_Pos) | + UARTx->BAUD |= (1 << UART_BAUD_ABREN_Pos) | (bits << UART_BAUD_ABRBIT_Pos); } /****************************************************************************************************************************************** -* ��������: UART_ABRIsDone() -* ����˵��: UART �Զ��������Ƿ���� -* �� ��: UART_TypeDef * UARTx ָ��Ҫ�����õ�UART���ڣ���Чֵ����UART0��UART1��UART2��UART3 -* �� ��: uint32_t 0 δ��� UART_ABR_RES_OK ����ɣ��ҳɹ� UART_ABR_RES_ERR ����ɣ���ʧ�ܡ����� -* ע������: �� +* 函数名称: UART_ABRIsDone() +* 功能说明: UART 自动波特率是否完成 +* 输 入: UART_TypeDef * UARTx 指定要被设置的UART串口，有效值包括UART0、UART1、UART2、UART3 +* 输 出: uint32_t 0 未完成 UART_ABR_RES_OK 已完成，且成功 UART_ABR_RES_ERR 已完成，但失败、出错 +* 注意事项: 无 ******************************************************************************************************************************************/ uint32_t UART_ABRIsDone(UART_TypeDef *UARTx) { @@ -399,11 +423,11 @@ uint32_t UART_ABRIsDone(UART_TypeDef *UARTx) } /****************************************************************************************************************************************** -* ��������: UART_INTRXThresholdEn() -* ����˵��: ��RX FIFO�����ݸ��� >= RXThresholdʱ �����ж� -* �� ��: UART_TypeDef * UARTx ָ��Ҫ�����õ�UART���ڣ���Чֵ����UART0��UART1��UART2��UART3 -* �� ��: �� -* ע������: �� +* 函数名称: UART_INTRXThresholdEn() +* 功能说明: 当RX FIFO中数据个数 >= RXThreshold时 触发中断 +* 输 入: UART_TypeDef * UARTx 指定要被设置的UART串口，有效值包括UART0、UART1、UART2、UART3 +* 输 出: 无 +* 注意事项: 无 ******************************************************************************************************************************************/ void UART_INTRXThresholdEn(UART_TypeDef *UARTx) { @@ -411,11 +435,11 @@ void UART_INTRXThresholdEn(UART_TypeDef *UARTx) } /****************************************************************************************************************************************** -* ��������: UART_INTRXThresholdDis() -* ����˵��: ��RX FIFO�����ݸ��� >= RXThresholdʱ �������ж� -* �� ��: UART_TypeDef * UARTx ָ��Ҫ�����õ�UART���ڣ���Чֵ����UART0��UART1��UART2��UART3 -* �� ��: �� -* ע������: �� +* 函数名称: UART_INTRXThresholdDis() +* 功能说明: 当RX FIFO中数据个数 >= RXThreshold时 不触发中断 +* 输 入: UART_TypeDef * UARTx 指定要被设置的UART串口，有效值包括UART0、UART1、UART2、UART3 +* 输 出: 无 +* 注意事项: 无 ******************************************************************************************************************************************/ void UART_INTRXThresholdDis(UART_TypeDef *UARTx) { @@ -423,11 +447,11 @@ void UART_INTRXThresholdDis(UART_TypeDef *UARTx) } /****************************************************************************************************************************************** -* ��������: UART_INTRXThresholdStat() -* ����˵��: �Ƿ�RX FIFO�����ݸ��� >= RXThreshold -* �� ��: UART_TypeDef * UARTx ָ��Ҫ�����õ�UART���ڣ���Чֵ����UART0��UART1��UART2��UART3 -* �� ��: uint32_t 1 RX FIFO�����ݸ��� >= RXThreshold 0 RX FIFO�����ݸ��� < RXThreshold -* ע������: RXIF = RXTHRF & RXIE +* 函数名称: UART_INTRXThresholdStat() +* 功能说明: 是否RX FIFO中数据个数 >= RXThreshold +* 输 入: UART_TypeDef * UARTx 指定要被设置的UART串口，有效值包括UART0、UART1、UART2、UART3 +* 输 出: uint32_t 1 RX FIFO中数据个数 >= RXThreshold 0 RX FIFO中数据个数 < RXThreshold +* 注意事项: RXIF = RXTHRF & RXIE ******************************************************************************************************************************************/ uint32_t UART_INTRXThresholdStat(UART_TypeDef *UARTx) { @@ -435,11 +459,11 @@ uint32_t UART_INTRXThresholdStat(UART_TypeDef *UARTx) } /****************************************************************************************************************************************** -* ��������: UART_INTTXThresholdEn() -* ����˵��: ��TX FIFO�����ݸ��� <= TXThresholdʱ �����ж� -* �� ��: UART_TypeDef * UARTx ָ��Ҫ�����õ�UART���ڣ���Чֵ����UART0��UART1��UART2��UART3 -* �� ��: �� -* ע������: �� +* 函数名称: UART_INTTXThresholdEn() +* 功能说明: 当TX FIFO中数据个数 <= TXThreshold时 触发中断 +* 输 入: UART_TypeDef * UARTx 指定要被设置的UART串口，有效值包括UART0、UART1、UART2、UART3 +* 输 出: 无 +* 注意事项: 无 ******************************************************************************************************************************************/ void UART_INTTXThresholdEn(UART_TypeDef *UARTx) { @@ -447,11 +471,11 @@ void UART_INTTXThresholdEn(UART_TypeDef *UARTx) } /****************************************************************************************************************************************** -* ��������: UART_INTTXThresholdDis() -* ����˵��: ��TX FIFO�����ݸ��� <= TXThresholdʱ �������ж� -* �� ��: UART_TypeDef * UARTx ָ��Ҫ�����õ�UART���ڣ���Чֵ����UART0��UART1��UART2��UART3 -* �� ��: �� -* ע������: �� +* 函数名称: UART_INTTXThresholdDis() +* 功能说明: 当TX FIFO中数据个数 <= TXThreshold时 不触发中断 +* 输 入: UART_TypeDef * UARTx 指定要被设置的UART串口，有效值包括UART0、UART1、UART2、UART3 +* 输 出: 无 +* 注意事项: 无 ******************************************************************************************************************************************/ void UART_INTTXThresholdDis(UART_TypeDef *UARTx) { @@ -459,11 +483,11 @@ void UART_INTTXThresholdDis(UART_TypeDef *UARTx) } /****************************************************************************************************************************************** -* ��������: UART_INTTXThresholdStat() -* ����˵��: �Ƿ�TX FIFO�����ݸ��� <= TXThreshold -* �� ��: UART_TypeDef * UARTx ָ��Ҫ�����õ�UART���ڣ���Чֵ����UART0��UART1��UART2��UART3 -* �� ��: uint32_t 1 TX FIFO�����ݸ��� <= TXThreshold 0 TX FIFO�����ݸ��� > TXThreshold -* ע������: TXIF = TXTHRF & TXIE +* 函数名称: UART_INTTXThresholdStat() +* 功能说明: 是否TX FIFO中数据个数 <= TXThreshold +* 输 入: UART_TypeDef * UARTx 指定要被设置的UART串口，有效值包括UART0、UART1、UART2、UART3 +* 输 出: uint32_t 1 TX FIFO中数据个数 <= TXThreshold 0 TX FIFO中数据个数 > TXThreshold +* 注意事项: TXIF = TXTHRF & TXIE ******************************************************************************************************************************************/ uint32_t UART_INTTXThresholdStat(UART_TypeDef *UARTx) { @@ -471,11 +495,11 @@ uint32_t UART_INTTXThresholdStat(UART_TypeDef *UARTx) } /****************************************************************************************************************************************** -* ��������: UART_INTTimeoutEn() -* ����˵��: ���շ�����ʱʱ �����ж� -* �� ��: UART_TypeDef * UARTx ָ��Ҫ�����õ�UART���ڣ���Чֵ����UART0��UART1��UART2��UART3 -* �� ��: �� -* ע������: �� +* 函数名称: UART_INTTimeoutEn() +* 功能说明: 接收发生超时时 触发中断 +* 输 入: UART_TypeDef * UARTx 指定要被设置的UART串口，有效值包括UART0、UART1、UART2、UART3 +* 输 出: 无 +* 注意事项: 无 ******************************************************************************************************************************************/ void UART_INTTimeoutEn(UART_TypeDef *UARTx) { @@ -483,11 +507,11 @@ void UART_INTTimeoutEn(UART_TypeDef *UARTx) } /****************************************************************************************************************************************** -* ��������: UART_INTTimeoutDis() -* ����˵��: ���շ�����ʱʱ �������ж� -* �� ��: UART_TypeDef * UARTx ָ��Ҫ�����õ�UART���ڣ���Чֵ����UART0��UART1��UART2��UART3 -* �� ��: �� -* ע������: �� +* 函数名称: UART_INTTimeoutDis() +* 功能说明: 接收发生超时时 不触发中断 +* 输 入: UART_TypeDef * UARTx 指定要被设置的UART串口，有效值包括UART0、UART1、UART2、UART3 +* 输 出: 无 +* 注意事项: 无 ******************************************************************************************************************************************/ void UART_INTTimeoutDis(UART_TypeDef *UARTx) { @@ -495,11 +519,11 @@ void UART_INTTimeoutDis(UART_TypeDef *UARTx) } /****************************************************************************************************************************************** -* ��������: UART_INTTimeoutStat() -* ����˵��: �Ƿ����˽��ճ�ʱ�������� TimeoutTime/(Baudrate/10) ��û����RX���Ͻ��յ�����ʱ�����ж� -* �� ��: UART_TypeDef * UARTx ָ��Ҫ�����õ�UART���ڣ���Чֵ����UART0��UART1��UART2��UART3 -* �� ��: uint32_t 1 �����˽��ճ�ʱ 0 δ�������ճ�ʱ -* ע������: �� +* 函数名称: UART_INTTimeoutStat() +* 功能说明: 是否发生了接收超时，即超过 TimeoutTime/(Baudrate/10) 秒没有在RX线上接收到数据时触发中断 +* 输 入: UART_TypeDef * UARTx 指定要被设置的UART串口，有效值包括UART0、UART1、UART2、UART3 +* 输 出: uint32_t 1 发生了接收超时 0 未发生接收超时 +* 注意事项: 无 ******************************************************************************************************************************************/ uint32_t UART_INTTimeoutStat(UART_TypeDef *UARTx) { @@ -507,11 +531,11 @@ uint32_t UART_INTTimeoutStat(UART_TypeDef *UARTx) } /****************************************************************************************************************************************** -* ��������: UART_INTTXDoneEn() -* ����˵��: ����FIFO���ҷ�����λ�Ĵ������ж�ʹ�� -* �� ��: UART_TypeDef * UARTx ָ��Ҫ�����õ�UART���ڣ���Чֵ����UART0��UART1��UART2��UART3 -* �� ��: �� -* ע������: �� +* 函数名称: UART_INTTXDoneEn() +* 功能说明: 发送FIFO空且发送移位寄存器空中断使能 +* 输 入: UART_TypeDef * UARTx 指定要被设置的UART串口，有效值包括UART0、UART1、UART2、UART3 +* 输 出: 无 +* 注意事项: 无 ******************************************************************************************************************************************/ void UART_INTTXDoneEn(UART_TypeDef *UARTx) { @@ -519,11 +543,11 @@ void UART_INTTXDoneEn(UART_TypeDef *UARTx) } /****************************************************************************************************************************************** -* ��������: UART_INTTXDoneDis() -* ����˵��: ����FIFO���ҷ�����λ�Ĵ������жϽ�ֹ -* �� ��: UART_TypeDef * UARTx ָ��Ҫ�����õ�UART���ڣ���Чֵ����UART0��UART1��UART2��UART3 -* �� ��: �� -* ע������: �� +* 函数名称: UART_INTTXDoneDis() +* 功能说明: 发送FIFO空且发送移位寄存器空中断禁止 +* 输 入: UART_TypeDef * UARTx 指定要被设置的UART串口，有效值包括UART0、UART1、UART2、UART3 +* 输 出: 无 +* 注意事项: 无 ******************************************************************************************************************************************/ void UART_INTTXDoneDis(UART_TypeDef *UARTx) { @@ -531,11 +555,11 @@ void UART_INTTXDoneDis(UART_TypeDef *UARTx) } /****************************************************************************************************************************************** -* ��������: UART_INTTXDoneStat() -* ����˵��: ����FIFO���ҷ�����λ�Ĵ������ж�״̬ -* �� ��: UART_TypeDef * UARTx ָ��Ҫ�����õ�UART���ڣ���Чֵ����UART0��UART1��UART2��UART3 -* �� ��: uint32_t 1 ����FIFO���ҷ�����λ�Ĵ����� 0 ����FIFO������λ�Ĵ���δ�� -* ע������: �� +* 函数名称: UART_INTTXDoneStat() +* 功能说明: 发送FIFO空且发送移位寄存器空中断状态 +* 输 入: UART_TypeDef * UARTx 指定要被设置的UART串口，有效值包括UART0、UART1、UART2、UART3 +* 输 出: uint32_t 1 发送FIFO空且发送移位寄存器空 0 发送FIFO或发送移位寄存器未空 +* 注意事项: 无 ******************************************************************************************************************************************/ uint32_t UART_INTTXDoneStat(UART_TypeDef *UARTx) { diff --git a/bsp/swm320-lq100/Libraries/SWM320_StdPeriph_Driver/SWM320_uart.h b/bsp/swm320-lq100/Libraries/SWM320_StdPeriph_Driver/SWM320_uart.h index 1bc2ad3edc..08bd6f805b 100644 --- a/bsp/swm320-lq100/Libraries/SWM320_StdPeriph_Driver/SWM320_uart.h +++ b/bsp/swm320-lq100/Libraries/SWM320_StdPeriph_Driver/SWM320_uart.h @@ -5,62 +5,59 @@ typedef struct { uint32_t Baudrate; - uint8_t DataBits; //����λλ������ȡֵUART_DATA_8BIT��UART_DATA_9BIT + uint8_t DataBits; //数据位位数，可取值UART_DATA_8BIT、UART_DATA_9BIT - uint8_t Parity; //��żУ��λ����ȡֵUART_PARITY_NONE��UART_PARITY_ODD��UART_PARITY_EVEN��UART_PARITY_ONE��UART_PARITY_ZERO + uint8_t Parity; //奇偶校验位，可取值UART_PARITY_NONE、UART_PARITY_ODD、UART_PARITY_EVEN、UART_PARITY_ONE、UART_PARITY_ZERO - uint8_t StopBits; //ֹͣλλ������ȡֵUART_STOP_1BIT��UART_STOP_2BIT + uint8_t StopBits; //停止位位数，可取值UART_STOP_1BIT、UART_STOP_2BIT - uint8_t RXThreshold; //ȡֵ0--7 - uint8_t RXThresholdIEn; //��RX FIFO�����ݸ��� >= RXThresholdʱ�����ж� + uint8_t RXThreshold; //取值0--7 + uint8_t RXThresholdIEn; //当RX FIFO中数据个数 > RXThreshold时触发中断 - uint8_t TXThreshold; //ȡֵ0--7 - uint8_t TXThresholdIEn; //��TX FIFO�����ݸ��� <= TXThresholdʱ�����ж� + uint8_t TXThreshold; //取值0--7 + uint8_t TXThresholdIEn; //当TX FIFO中数据个数 <= TXThreshold时触发中断 - uint8_t TimeoutTime; //��ʱʱ�� = TimeoutTime/(Baudrate/10) �� - uint8_t TimeoutIEn; //��ʱ�жϣ����� TimeoutTime/(Baudrate/10) ��û����RX���Ͻ��յ�����ʱ�����ж� + uint8_t TimeoutTime; //超时时长 = TimeoutTime/(Baudrate/10) 秒 + uint8_t TimeoutIEn; //超时中断，RX FIFO非空，且超过 TimeoutTime/(Baudrate/10) 秒没有在RX线上接收到数据时触发中断 } UART_InitStructure; +#define UART_DATA_8BIT 0 +#define UART_DATA_9BIT 1 -#define UART_DATA_8BIT 0 -#define UART_DATA_9BIT 1 +#define UART_PARITY_NONE 0 +#define UART_PARITY_ODD 1 +#define UART_PARITY_EVEN 3 +#define UART_PARITY_ONE 5 +#define UART_PARITY_ZERO 7 -#define UART_PARITY_NONE 0 -#define UART_PARITY_ODD 1 -#define UART_PARITY_EVEN 3 -#define UART_PARITY_ONE 5 -#define UART_PARITY_ZERO 7 +#define UART_STOP_1BIT 0 +#define UART_STOP_2BIT 1 -#define UART_STOP_1BIT 0 -#define UART_STOP_2BIT 1 +#define UART_RTS_1BYTE 0 +#define UART_RTS_2BYTE 1 +#define UART_RTS_4BYTE 2 +#define UART_RTS_6BYTE 3 -#define UART_RTS_1BYTE 0 -#define UART_RTS_2BYTE 1 -#define UART_RTS_4BYTE 2 -#define UART_RTS_6BYTE 3 +#define UART_ABR_RES_OK 1 +#define UART_ABR_RES_ERR 2 -#define UART_ABR_RES_OK 1 -#define UART_ABR_RES_ERR 2 +#define UART_ERR_FRAME 1 +#define UART_ERR_PARITY 2 +#define UART_ERR_NOISE 3 -#define UART_ERR_FRAME 1 -#define UART_ERR_PARITY 2 -#define UART_ERR_NOISE 3 - - -void UART_Init(UART_TypeDef *UARTx, UART_InitStructure *initStruct); //UART���ڳ�ʼ�� +void UART_Init(UART_TypeDef *UARTx, UART_InitStructure *initStruct); //UART串口初始化 void UART_Open(UART_TypeDef *UARTx); void UART_Close(UART_TypeDef *UARTx); -void UART_WriteByte(UART_TypeDef *UARTx, uint8_t data); //����һ���ֽ����� -uint32_t UART_ReadByte(UART_TypeDef *UARTx, uint32_t *data); //��ȡһ���ֽ����ݣ���ָ�������Ƿ�Valid +void UART_WriteByte(UART_TypeDef *UARTx, uint32_t data); //发送一个字节数据 +uint32_t UART_ReadByte(UART_TypeDef *UARTx, uint32_t *data); //读取一个字节数据，并指出数据是否Valid uint32_t UART_IsTXBusy(UART_TypeDef *UARTx); -uint32_t UART_IsRXFIFOEmpty(UART_TypeDef *UARTx); //����FIFO�Ƿ�գ������������Լ���UART_ReadByte() -uint32_t UART_IsTXFIFOFull(UART_TypeDef *UARTx); //����FIFO�Ƿ����������������Լ���UART_WriteByte() - +uint32_t UART_IsRXFIFOEmpty(UART_TypeDef *UARTx); //接收FIFO是否空，如果不空则可以继续UART_ReadByte() +uint32_t UART_IsTXFIFOFull(UART_TypeDef *UARTx); //发送FIFO是否满，如果不满则可以继续UART_WriteByte() -void UART_SetBaudrate(UART_TypeDef *UARTx, uint32_t baudrate); //���ò����� -uint32_t UART_GetBaudrate(UART_TypeDef *UARTx); //��ȡ��ǰʹ�õIJ����� +void UART_SetBaudrate(UART_TypeDef *UARTx, uint32_t baudrate); //设置波特率 +uint32_t UART_GetBaudrate(UART_TypeDef *UARTx); //获取当前使用的波特率 void UART_CTSConfig(UART_TypeDef *UARTx, uint32_t enable, uint32_t polarity); uint32_t UART_CTSLineState(UART_TypeDef *UARTx); @@ -76,7 +73,6 @@ uint32_t UART_LINIsGenerated(UART_TypeDef *UARTx); void UART_ABRStart(UART_TypeDef *UARTx, uint32_t detectChar); uint32_t UART_ABRIsDone(UART_TypeDef *UARTx); - void UART_INTRXThresholdEn(UART_TypeDef *UARTx); void UART_INTRXThresholdDis(UART_TypeDef *UARTx); uint32_t UART_INTRXThresholdStat(UART_TypeDef *UARTx); @@ -91,5 +87,4 @@ void UART_INTTXDoneEn(UART_TypeDef *UARTx); void UART_INTTXDoneDis(UART_TypeDef *UARTx); uint32_t UART_INTTXDoneStat(UART_TypeDef *UARTx); - #endif //__SWM320_UART_H__ diff --git a/bsp/swm320-lq100/Libraries/SWM320_StdPeriph_Driver/SWM320_wdt.c b/bsp/swm320-lq100/Libraries/SWM320_StdPeriph_Driver/SWM320_wdt.c index 04faf947d7..db6d7cef28 100644 --- a/bsp/swm320-lq100/Libraries/SWM320_StdPeriph_Driver/SWM320_wdt.c +++ b/bsp/swm320-lq100/Libraries/SWM320_StdPeriph_Driver/SWM320_wdt.c @@ -1,10 +1,10 @@ /****************************************************************************************************************************************** -* �ļ�����: SWM320_wdt.c -* ����˵��: SWM320��Ƭ����WDT���Ź����������� -* ����֧��: http://www.synwit.com.cn/e/tool/gbook/?bid=1 -* ע������: -* �汾����: V1.1.0 2017��10��25�� -* ������¼: +* 文件名称: SWM320_wdt.c +* 功能说明: SWM320单片机的WDT看门狗功能驱动库 +* 技术支持: http://www.synwit.com.cn/e/tool/gbook/?bid=1 +* 注意事项: +* 版本日期: V1.1.0 2017年10月25日 +* 升级记录: * * ******************************************************************************************************************************************* @@ -21,32 +21,33 @@ #include "SWM320.h" #include "SWM320_wdt.h" - /****************************************************************************************************************************************** -* ��������: WDT_Init() -* ����˵��: WDT���Ź���ʼ�� -* �� ��: WDT_TypeDef * WDTx ָ��Ҫ�����õĿ��Ź�����Чֵ����WDT -* uint32_t peroid ȡֵ0--4294967295����λΪ��Ƭ��ϵͳʱ������ -* uint32_t mode WDT_MODE_RESET ��ʱ������λ WDT_MODE_INTERRUPT ��ʱ�����ж� -* �� ��: �� -* ע������: ��λʹ��ʱ�жϲ������ã���Ϊ�������ڽ���ʱоƬֱ�Ӹ�λ�ˣ�����Ӧ�ж� +* 函数名称: WDT_Init() +* 功能说明: WDT看门狗初始化 +* 输 入: WDT_TypeDef * WDTx 指定要被设置的看门狗，有效值包括WDT +* uint32_t peroid 取值0--4294967295，单位为单片机系统时钟周期 +* uint32_t mode WDT_MODE_RESET 超时产生复位 WDT_MODE_INTERRUPT 超时产生中断 +* 输 出: 无 +* 注意事项: 无 ******************************************************************************************************************************************/ void WDT_Init(WDT_TypeDef *WDTx, uint32_t peroid, uint32_t mode) { SYS->CLKEN |= (0x01 << SYS_CLKEN_WDT_Pos); - WDT_Stop(WDTx); //����ǰ�ȹر� - - WDTx->LOAD = peroid; + WDT_Stop(WDTx); //设置前先关闭 if (mode == WDT_MODE_RESET) { + WDTx->LOAD = peroid / 2; //第一个计数周期置位中断标志、第二个计数周期将芯片复位 + NVIC_DisableIRQ(WDT_IRQn); WDTx->CR |= (1 << WDT_CR_RSTEN_Pos); } else //mode == WDT_MODE_INTERRUPT { + WDTx->LOAD = peroid; + NVIC_EnableIRQ(WDT_IRQn); WDTx->CR &= ~(1 << WDT_CR_RSTEN_Pos); @@ -54,11 +55,11 @@ void WDT_Init(WDT_TypeDef *WDTx, uint32_t peroid, uint32_t mode) } /****************************************************************************************************************************************** -* ��������: WDT_Start() -* ����˵��: ����ָ��WDT����ʼ����ʱ -* �� ��: WDT_TypeDef * WDTx ָ��Ҫ�����õĿ��Ź�����Чֵ����WDT -* �� ��: �� -* ע������: �� +* 函数名称: WDT_Start() +* 功能说明: 启动指定WDT，开始倒计时 +* 输 入: WDT_TypeDef * WDTx 指定要被设置的看门狗，有效值包括WDT +* 输 出: 无 +* 注意事项: 无 ******************************************************************************************************************************************/ void WDT_Start(WDT_TypeDef *WDTx) { @@ -66,11 +67,11 @@ void WDT_Start(WDT_TypeDef *WDTx) } /****************************************************************************************************************************************** -* ��������: WDT_Stop() -* ����˵��: �ر�ָ��WDT��ֹͣ����ʱ -* �� ��: WDT_TypeDef * WDTx ָ��Ҫ�����õĿ��Ź�����Чֵ����WDT -* �� ��: �� -* ע������: �� +* 函数名称: WDT_Stop() +* 功能说明: 关闭指定WDT，停止倒计时 +* 输 入: WDT_TypeDef * WDTx 指定要被设置的看门狗，有效值包括WDT +* 输 出: 无 +* 注意事项: 无 ******************************************************************************************************************************************/ void WDT_Stop(WDT_TypeDef *WDTx) { @@ -78,11 +79,11 @@ void WDT_Stop(WDT_TypeDef *WDTx) } /****************************************************************************************************************************************** -* ��������: WDT_Feed() -* ����˵��: ι�������´�װ��ֵ��ʼ����ʱ -* �� ��: WDT_TypeDef * WDTx ָ��Ҫ�����õĿ��Ź�����Чֵ����WDT -* �� ��: �� -* ע������: �� +* 函数名称: WDT_Feed() +* 功能说明: 喂狗，重新从装载值开始倒计时 +* 输 入: WDT_TypeDef * WDTx 指定要被设置的看门狗，有效值包括WDT +* 输 出: 无 +* 注意事项: 无 ******************************************************************************************************************************************/ void WDT_Feed(WDT_TypeDef *WDTx) { @@ -90,11 +91,11 @@ void WDT_Feed(WDT_TypeDef *WDTx) } /****************************************************************************************************************************************** -* ��������: WDT_GetValue() -* ����˵��: ��ȡָ�����Ź���ʱ���ĵ�ǰ����ʱֵ -* �� ��: WDT_TypeDef * WDTx ָ��Ҫ�����õĿ��Ź�����Чֵ����WDT -* �� ��: int32_t ���Ź���ǰ����ֵ -* ע������: �� +* 函数名称: WDT_GetValue() +* 功能说明: 获取指定看门狗定时器的当前倒计时值 +* 输 入: WDT_TypeDef * WDTx 指定要被设置的看门狗，有效值包括WDT +* 输 出: int32_t 看门狗当前计数值 +* 注意事项: 无 ******************************************************************************************************************************************/ int32_t WDT_GetValue(WDT_TypeDef *WDTx) { @@ -102,11 +103,11 @@ int32_t WDT_GetValue(WDT_TypeDef *WDTx) } /****************************************************************************************************************************************** -* ��������: WDT_INTClr() -* ����˵��: �жϱ�־��� -* �� ��: WDT_TypeDef * WDTx ָ��Ҫ�����õĿ��Ź�����Чֵ����WDT -* �� ��: �� -* ע������: �� +* 函数名称: WDT_INTClr() +* 功能说明: 中断标志清除 +* 输 入: WDT_TypeDef * WDTx 指定要被设置的看门狗，有效值包括WDT +* 输 出: 无 +* 注意事项: 无 ******************************************************************************************************************************************/ void WDT_INTClr(WDT_TypeDef *WDTx) { @@ -114,11 +115,11 @@ void WDT_INTClr(WDT_TypeDef *WDTx) } /****************************************************************************************************************************************** -* ��������: WDT_INTStat() -* ����˵��: �ж�״̬��ѯ -* �� ��: WDT_TypeDef * WDTx ָ��Ҫ�����õĿ��Ź�����Чֵ����WDT -* �� ��: int32_t 1 �����ж���� 0 δ�����ж���� -* ע������: �� +* 函数名称: WDT_INTStat() +* 功能说明: 中断状态查询 +* 输 入: WDT_TypeDef * WDTx 指定要被设置的看门狗，有效值包括WDT +* 输 出: int32_t 1 发生中断溢出 0 未发生中断溢出 +* 注意事项: 无 ******************************************************************************************************************************************/ uint32_t WDT_INTStat(WDT_TypeDef *WDTx) { diff --git a/bsp/swm320-lq100/Libraries/SWM320_StdPeriph_Driver/SWM320_wdt.h b/bsp/swm320-lq100/Libraries/SWM320_StdPeriph_Driver/SWM320_wdt.h index fd435c170e..692d1fe65b 100644 --- a/bsp/swm320-lq100/Libraries/SWM320_StdPeriph_Driver/SWM320_wdt.h +++ b/bsp/swm320-lq100/Libraries/SWM320_StdPeriph_Driver/SWM320_wdt.h @@ -1,19 +1,18 @@ #ifndef __SWM320_WDT_H__ #define __SWM320_WDT_H__ -#define WDT_MODE_RESET 0 -#define WDT_MODE_INTERRUPT 1 +#define WDT_MODE_RESET 0 +#define WDT_MODE_INTERRUPT 1 -void WDT_Init(WDT_TypeDef *WDTx, uint32_t peroid, uint32_t mode); //WDT���Ź���ʼ�� -void WDT_Start(WDT_TypeDef *WDTx); //����ָ��WDT����ʼ����ʱ -void WDT_Stop(WDT_TypeDef *WDTx); //�ر�ָ��WDT��ֹͣ����ʱ +void WDT_Init(WDT_TypeDef *WDTx, uint32_t peroid, uint32_t mode); //WDT看门狗初始化 +void WDT_Start(WDT_TypeDef *WDTx); //启动指定WDT，开始倒计时 +void WDT_Stop(WDT_TypeDef *WDTx); //关闭指定WDT，停止倒计时 -void WDT_Feed(WDT_TypeDef *WDTx); //ι�������´�װ��ֵ��ʼ����ʱ +void WDT_Feed(WDT_TypeDef *WDTx); //喂狗，重新从装载值开始倒计时 -int32_t WDT_GetValue(WDT_TypeDef *WDTx); //��ȡָ�����Ź���ʱ���ĵ�ǰ����ʱֵ +int32_t WDT_GetValue(WDT_TypeDef *WDTx); //获取指定看门狗定时器的当前倒计时值 - -void WDT_INTClr(WDT_TypeDef *WDTx); //�жϱ�־��� -uint32_t WDT_INTStat(WDT_TypeDef *WDTx); //�ж�״̬��ѯ +void WDT_INTClr(WDT_TypeDef *WDTx); //中断标志清除 +uint32_t WDT_INTStat(WDT_TypeDef *WDTx); //中断状态查询 #endif //__SWM320_WDT_H__ diff --git a/bsp/swm320-lq100/README.md b/bsp/swm320-lq100/README.md index 119b9e7b4b..ef571daaa0 100644 --- a/bsp/swm320-lq100/README.md +++ b/bsp/swm320-lq100/README.md @@ -31,7 +31,7 @@ SWXT-LQ100-32102 V1.1 开发板板载资源如下： - 常用接口：USB打印接口，TFT LCD接口，SD卡接口 - 调试接口：SWD -更多详细信息请咨询[华芯微特技术支持][http://www.synwit.cn/support.html] +更多详细信息请咨询[华芯微特技术支持](https://www.synwit.cn) ### 1.2 MCU 简介 @@ -89,36 +89,30 @@ msh /> ## 4. 驱动支持情况及计划 -|**板载外设** |**支持情况**|**备注** | -| ----------------- | :----------: | ----------------------- | -| Nor Flash | 支持 | | -| SDIO TF 卡 | 暂不支持 | | -| SRAM | 支持 | | -| TFT-LCD | 暂不支持 | 即将支持 | -|**片上外设** |**支持情况** |**备注** | -| GPIO | 支持 | PIN：1...100 | -| UART | 支持 | UART0 / UART1 / UART2 / UART3 | -| SPI | 支持 | SPI0 / SPI1 | -| I2C | 支持 | I2C0 IO模拟 | -| ADC | 暂不支持 | 即将支持 | -| PWM | 支持 | PWM0 / PWM1 /PWM2 /PWM3 其余两个后续补充| -| IWG | 支持 | | -| TIMER | 支持 | | -| RTC | 支持 | | -| CAN | 暂不支持 | | +| **片上外设** | **支持情况** | **备注** | +| :----------------- | :----------: | :----------------------------------- | +| GPIO | 支持 | PA0, PA1... PP23 ---> PIN: 0, 1...100 | +| UART | 支持 | UART0/1/2/3 | +| ADC | 支持 | ADC0/1 | +| TIM | 支持 | TIM0/1/2/3/4/5 | +| I2C | 支持 | 软件 I2C0/1 | +| PWM | 支持 | PWM0/1/2/3/4/5 | +| RTC | 支持 | RTC | +| SPI | 支持 | SPI0/1 | +| WDT | 支持 | WDT | +| CRC | 支持 | CRC | +| SDIO | 支持 | SDIO | +| SRAM | 支持 | SRAM | +| NOR FLASH | 支持 | NOR FLASH | +| CAN | 暂不支持 | | ## 5. 联系人信息 -维护人： +- [yanmowudi](https://github.com/yanmowudi) +- [邮箱]([email protected]) --[Zohar_Lee](https://github.com/zohar123) email: [email protected] +## 参考资料 -## 6. 参考 +* [RT-Thread 文档中心](https://www.rt-thread.org/document/site/) -- 芯片[SWM320系列数据手册][http://www.synwit.cn/Public/Uploads/2018-11-05/5bdff49b396d1.pdf] - -- [ SWM320_LQFP100原理图](http://www.synwit.cn/Public/Uploads/2018-11-01/5bdab8ad2e5b9.pdf) - -- [ SWM320_LQFP64原理图](http://www.synwit.cn/Public/Uploads/2018-11-05/5bdfea74d5712.pdf) - -- [ keil pack及其他资料](http://www.synwit.cn/support-1/2.html) +* [SWM320数据手册](https://www.synwit.cn/col.jsp?id=155) diff --git a/bsp/swm320-lq100/SConscript b/bsp/swm320-lq100/SConscript index 1b1c7506a4..c7ef7659ec 100644 --- a/bsp/swm320-lq100/SConscript +++ b/bsp/swm320-lq100/SConscript @@ -1,11 +1,14 @@ +# for module compiling +import os from building import * cwd = GetCurrentDir() - objs = [] list = os.listdir(cwd) + for d in list: path = os.path.join(cwd, d) if os.path.isfile(os.path.join(path, 'SConscript')): objs = objs + SConscript(os.path.join(d, 'SConscript')) + Return('objs') diff --git a/bsp/swm320-lq100/SConstruct b/bsp/swm320-lq100/SConstruct index 8418d596c0..c11cd41bc7 100644 --- a/bsp/swm320-lq100/SConstruct +++ b/bsp/swm320-lq100/SConstruct @@ -8,6 +8,7 @@ else: RTT_ROOT = os.path.normpath(os.getcwd() + '/../..') sys.path = sys.path + [os.path.join(RTT_ROOT, 'tools')] + try: from building import * except: @@ -17,18 +18,18 @@ except: TARGET = 'rtthread.' + rtconfig.TARGET_EXT -DefaultEnvironment(tools=[]) env = Environment(tools = ['mingw'], - AS = rtconfig.AS, ASFLAGS = rtconfig.AFLAGS, - CC = rtconfig.CC, CCFLAGS = rtconfig.CFLAGS, - AR = rtconfig.AR, ARFLAGS = '-rc', - LINK = rtconfig.LINK, LINKFLAGS = rtconfig.LFLAGS) + AS = rtconfig.AS, ASFLAGS = rtconfig.AFLAGS, + CC = rtconfig.CC, CCFLAGS = rtconfig.CFLAGS, + CXX = rtconfig.CXX, CXXFLAGS = rtconfig.CXXFLAGS, + AR = rtconfig.AR, ARFLAGS = '-rc', + LINK = rtconfig.LINK, LINKFLAGS = rtconfig.LFLAGS) env.PrependENVPath('PATH', rtconfig.EXEC_PATH) if rtconfig.PLATFORM == 'iar': env.Replace(CCCOM = ['$CC $CCFLAGS $CPPFLAGS $_CPPDEFFLAGS $_CPPINCFLAGS -o $TARGET $SOURCES']) env.Replace(ARFLAGS = ['']) - env.Replace(LINKCOM = env["LINKCOM"] + ' --map project.map') + env.Replace(LINKCOM = env["LINKCOM"] + ' --map rtthread.map') Export('RTT_ROOT') Export('rtconfig') diff --git a/bsp/swm320-lq100/applications/main.c b/bsp/swm320-lq100/applications/main.c index 004867b45c..3761e8c14d 100644 --- a/bsp/swm320-lq100/applications/main.c +++ b/bsp/swm320-lq100/applications/main.c @@ -1,31 +1,571 @@ /* - * Copyright (c) 2006-2018, Synwit Technology Co.,Ltd. + * Copyright (c) 2006-2021, RT-Thread Development Team * * SPDX-License-Identifier: Apache-2.0 * * Change Logs: * Date Author Notes - * 2018-12-10 Zohar_Lee first version */ #include <rtthread.h> #include <rtdevice.h> -/* defined the LED pin: PA12 */ -#define LED_PIN 100 + +#define LED_PIN 11 int main(void) { int count = 1; - /* set LED4 pin mode to output */ - rt_pin_mode(LED_PIN, PIN_MODE_OUTPUT); + rt_pin_mode(LED_PIN, PIN_MODE_OUTPUT); while (count++) { rt_pin_write(LED_PIN, PIN_HIGH); - rt_thread_mdelay(500); + rt_thread_mdelay(1000); rt_pin_write(LED_PIN, PIN_LOW); - rt_thread_mdelay(500); + rt_thread_mdelay(1000); + } + + return RT_EOK; +} + +// #ifdef RT_USING_PIN +// #define KEY1_PIN 31 +// void key1_cb(void *args) +// { +// rt_kprintf("key1 irq!\n"); +// } +// static int pin_sample(int argc, char *argv[]) +// { +// rt_pin_mode(KEY1_PIN, PIN_IRQ_MODE_FALLING); +// rt_pin_attach_irq(KEY1_PIN, PIN_IRQ_MODE_FALLING, key1_cb, RT_NULL); +// rt_pin_irq_enable(KEY1_PIN, PIN_IRQ_ENABLE); + +// return RT_EOK; +// } +// MSH_CMD_EXPORT(pin_sample, pin sample); +// #endif + +#ifdef RT_USING_ADC +#define ADC_DEV_NAME "adc1" +#define ADC_DEV_CHANNEL 0 +#define REFER_VOLTAGE 330 +#define CONVERT_BITS (1 << 12) + +static int adc_vol_sample(int argc, char *argv[]) +{ + rt_adc_device_t adc_dev; + rt_uint32_t value, vol; + rt_err_t ret = RT_EOK; + + adc_dev = (rt_adc_device_t)rt_device_find(ADC_DEV_NAME); + if (adc_dev == RT_NULL) + { + rt_kprintf("adc sample run failed! can't find %s device!\n", ADC_DEV_NAME); + return RT_ERROR; } + ret = rt_adc_enable(adc_dev, ADC_DEV_CHANNEL); + + value = rt_adc_read(adc_dev, ADC_DEV_CHANNEL); + rt_kprintf("the value is :%d,", value); + + vol = value * REFER_VOLTAGE / CONVERT_BITS; + rt_kprintf("the voltage is :%d.%02d \n", vol / 100, vol % 100); + + ret = rt_adc_disable(adc_dev, ADC_DEV_CHANNEL); + + return ret; +} +MSH_CMD_EXPORT(adc_vol_sample, adc voltage convert sample); +#endif + +#ifdef RT_USING_HWTIMER +#define HWTIMER_DEV_NAME "timer0" + +static rt_err_t timeout_cb(rt_device_t dev, rt_size_t size) +{ + rt_kprintf("this is hwtimer timeout callback fucntion!\n"); + rt_kprintf("tick is :%d !\n", rt_tick_get()); + + return 0; +} + +static int hwtimer_sample(int argc, char *argv[]) +{ + rt_err_t ret = RT_EOK; + rt_hwtimerval_t timeout_s; + rt_device_t hw_dev = RT_NULL; + rt_hwtimer_mode_t mode; + + hw_dev = rt_device_find(HWTIMER_DEV_NAME); + if (hw_dev == RT_NULL) + { + rt_kprintf("hwtimer sample run failed! can't find %s device!\n", HWTIMER_DEV_NAME); + return RT_ERROR; + } + + ret = rt_device_open(hw_dev, RT_DEVICE_OFLAG_RDWR); + if (ret != RT_EOK) + { + rt_kprintf("open %s device failed!\n", HWTIMER_DEV_NAME); + return ret; + } + + rt_device_set_rx_indicate(hw_dev, timeout_cb); + + mode = HWTIMER_MODE_PERIOD; + //mode = HWTIMER_MODE_ONESHOT; + ret = rt_device_control(hw_dev, HWTIMER_CTRL_MODE_SET, &mode); + if (ret != RT_EOK) + { + rt_kprintf("set mode failed! ret is :%d\n", ret); + return ret; + } + + timeout_s.sec = 2; + timeout_s.usec = 0; + + if (rt_device_write(hw_dev, 0, &timeout_s, sizeof(timeout_s)) != sizeof(timeout_s)) + { + rt_kprintf("set timeout value failed\n"); + return RT_ERROR; + } + + rt_thread_mdelay(3500); + + rt_device_read(hw_dev, 0, &timeout_s, sizeof(timeout_s)); + rt_kprintf("Read: Sec = %d, Usec = %d\n", timeout_s.sec, timeout_s.usec); + + return ret; +} +MSH_CMD_EXPORT(hwtimer_sample, hwtimer sample); +#endif + +#ifdef RT_USING_PWM +#define PWM_DEV_NAME "pwm0" /* PWM设备名称 */ +#define PWM_DEV_CHANNEL 0 /* PWM通道 */ + +struct rt_device_pwm *pwm_dev; /* PWM设备句柄 */ + +static int pwm_sample(int argc, char *argv[]) +{ + rt_uint32_t period, pulse; + + period = 500000; /* 周期为0.5ms,单位为纳秒ns */ + pulse = 250000; /* PWM脉冲宽度值,单位为纳秒ns */ + + pwm_dev = (struct rt_device_pwm *)rt_device_find(PWM_DEV_NAME); + if (pwm_dev == RT_NULL) + { + rt_kprintf("pwm sample run failed! can't find %s device!\n", PWM_DEV_NAME); + return RT_ERROR; + } + + rt_pwm_set(pwm_dev, PWM_DEV_CHANNEL, period, pulse); + rt_pwm_enable(pwm_dev, PWM_DEV_CHANNEL); + return RT_EOK; +} +MSH_CMD_EXPORT(pwm_sample, pwm sample); +#endif + +#ifdef RT_USING_RTC +#include <time.h> +static int rtc_sample(int argc, char *argv[]) +{ + rt_err_t ret = RT_EOK; + time_t now; + + ret = set_date(2020, 2, 28); + if (ret != RT_EOK) + { + rt_kprintf("set RTC date failed\n"); + return ret; + } + + ret = set_time(23, 59, 55); + if (ret != RT_EOK) + { + rt_kprintf("set RTC time failed\n"); + return ret; + } + + //rt_thread_mdelay(3000); + now = time(RT_NULL); + rt_kprintf("%s\n", ctime(&now)); + + return ret; +} +MSH_CMD_EXPORT(rtc_sample, rtc sample); +#endif + +#ifdef RT_USING_WDT +#define WDT_DEVICE_NAME "wdt" + +static rt_device_t wdg_dev; + +static void idle_hook(void) +{ + rt_device_control(wdg_dev, RT_DEVICE_CTRL_WDT_KEEPALIVE, RT_NULL); + rt_kprintf("feed the dog!\n "); +} + +static int wdt_sample(int argc, char *argv[]) +{ + rt_err_t ret = RT_EOK; + rt_uint32_t timeout = 1; + char device_name[RT_NAME_MAX]; + + if (argc == 2) + { + rt_strncpy(device_name, argv[1], RT_NAME_MAX); + } + else + { + rt_strncpy(device_name, WDT_DEVICE_NAME, RT_NAME_MAX); + } + wdg_dev = rt_device_find(device_name); + if (!wdg_dev) + { + rt_kprintf("find %s failed!\n", device_name); + return RT_ERROR; + } + ret = rt_device_init(wdg_dev); + if (ret != RT_EOK) + { + rt_kprintf("initialize %s failed!\n", device_name); + return RT_ERROR; + } + ret = rt_device_control(wdg_dev, RT_DEVICE_CTRL_WDT_SET_TIMEOUT, &timeout); + if (ret != RT_EOK) + { + rt_kprintf("set %s timeout failed!\n", device_name); + return RT_ERROR; + } + ret = rt_device_control(wdg_dev, RT_DEVICE_CTRL_WDT_START, RT_NULL); + if (ret != RT_EOK) + { + rt_kprintf("start %s failed!\n", device_name); + return -RT_ERROR; + } + // rt_thread_idle_sethook(idle_hook); + + return ret; +} +MSH_CMD_EXPORT(wdt_sample, wdt sample); +#endif + +#ifdef RT_USING_SPI +#define W25Q_SPI_DEVICE_NAME "spi00" +#define W25Q_FLASH_NAME "norflash0" + +#include "drv_spi.h" +#include "spi_flash_sfud.h" +#include "dfs_posix.h" + +static int rt_hw_spi_flash_init(void) +{ + rt_hw_spi_device_attach("spi0", "spi00", GPIOP, PIN22); + + if (RT_NULL == rt_sfud_flash_probe(W25Q_FLASH_NAME, W25Q_SPI_DEVICE_NAME)) + { + return -RT_ERROR; + }; + return RT_EOK; } +INIT_COMPONENT_EXPORT(rt_hw_spi_flash_init); + +static void spi_w25q_sample(int argc, char *argv[]) +{ + struct rt_spi_device *spi_dev_w25q; + char name[RT_NAME_MAX]; + rt_uint8_t w25x_read_id = 0x90; + rt_uint8_t id[5] = {0}; + + if (argc == 2) + { + rt_strncpy(name, argv[1], RT_NAME_MAX); + } + else + { + rt_strncpy(name, W25Q_SPI_DEVICE_NAME, RT_NAME_MAX); + } + + /* 查找 spi 设备获取设备句柄 */ + spi_dev_w25q = (struct rt_spi_device *)rt_device_find(name); + struct rt_spi_configuration cfg; + cfg.data_width = 8; + cfg.mode = RT_SPI_MASTER | RT_SPI_MODE_0 | RT_SPI_MSB; + cfg.max_hz = 30 * 1000 * 1000; /* 20M */ + + rt_spi_configure(spi_dev_w25q, &cfg); + if (!spi_dev_w25q) + { + rt_kprintf("spi sample run failed! can't find %s device!\n", name); + } + else + { + /* 方式1：使用 rt_spi_send_then_recv()发送命令读取ID */ + rt_spi_send_then_recv(spi_dev_w25q, &w25x_read_id, 1, id, 5); + rt_kprintf("use rt_spi_send_then_recv() read w25q ID is:%x%x\n", id[3], id[4]); + + /* 方式2：使用 rt_spi_transfer_message()发送命令读取ID */ + struct rt_spi_message msg1, msg2; + + msg1.send_buf = &w25x_read_id; + msg1.recv_buf = RT_NULL; + msg1.length = 1; + msg1.cs_take = 1; + msg1.cs_release = 0; + msg1.next = &msg2; + + msg2.send_buf = RT_NULL; + msg2.recv_buf = id; + msg2.length = 5; + msg2.cs_take = 0; + msg2.cs_release = 1; + msg2.next = RT_NULL; + + rt_spi_transfer_message(spi_dev_w25q, &msg1); + rt_kprintf("use rt_spi_transfer_message() read w25q ID is:%x%x\n", id[3], id[4]); + } +} +static void spi_flash_elmfat_sample(void) +{ + int fd, size; + struct statfs elm_stat; + char str[] = "elmfat mount to W25Q flash.\r\n", buf[80]; + + if (dfs_mkfs("elm", W25Q_FLASH_NAME) == 0) + rt_kprintf("make elmfat filesystem success.\n"); + + if (dfs_mount(W25Q_FLASH_NAME, "/", "elm", 0, 0) == 0) + rt_kprintf("elmfat filesystem mount success.\n"); + + if (statfs("/", &elm_stat) == 0) + rt_kprintf("elmfat filesystem block size: %d, total blocks: %d, free blocks: %d.\n", + elm_stat.f_bsize, elm_stat.f_blocks, elm_stat.f_bfree); + + if (mkdir("/user", 0x777) == 0) + rt_kprintf("make a directory: '/user'.\n"); + + rt_kprintf("Write string '%s' to /user/test.txt.\n", str); + + fd = open("/user/test.txt", O_WRONLY | O_CREAT); + if (fd >= 0) + { + if (write(fd, str, sizeof(str)) == sizeof(str)) + rt_kprintf("Write data done.\n"); + + close(fd); + } + + fd = open("/user/test.txt", O_RDONLY); + if (fd >= 0) + { + size = read(fd, buf, sizeof(buf)); + + close(fd); + + if (size == sizeof(str)) + rt_kprintf("Read data from file test.txt(size: %d): %s \n", size, buf); + } +} +MSH_CMD_EXPORT(spi_flash_elmfat_sample, spi flash elmfat sample); +MSH_CMD_EXPORT(spi_w25q_sample, spi w25q sample); +#endif + +//#ifdef RT_USING_SPI +//#define SD_SPI_DEVICE_NAME "spi10" +//#define SDCARD_NAME "sd0" + +//#include "drv_spi.h" +//#include "dfs_posix.h" +//#include "spi_msd.h" + +//static int rt_hw_spi1_tfcard(void) +//{ +// rt_hw_spi_device_attach("spi1", SD_SPI_DEVICE_NAME, GPIOB, PIN6); +// return msd_init(SDCARD_NAME, SD_SPI_DEVICE_NAME); +//} +//INIT_DEVICE_EXPORT(rt_hw_spi1_tfcard); + +//static void elmfat_sample(void) +//{ +// int fd, size; +// struct statfs elm_stat; +// char str[] = "elmfat mount to sdcard.", buf[80]; + +// if (dfs_mkfs("elm", SDCARD_NAME) == 0) +// rt_kprintf("make elmfat filesystem success.\n"); + +// if (dfs_mount(SDCARD_NAME, "/", "elm", 0, 0) == 0) +// rt_kprintf("elmfat filesystem mount success.\n"); + +// if (statfs("/", &elm_stat) == 0) +// rt_kprintf("elmfat filesystem block size: %d, total blocks: %d, free blocks: %d.\n", +// elm_stat.f_bsize, elm_stat.f_blocks, elm_stat.f_bfree); + +// if (mkdir("/user", 0x777) == 0) +// rt_kprintf("make a directory: '/user'.\n"); + +// rt_kprintf("Write string '%s' to /user/test.txt.\n", str); + +// fd = open("/user/test.txt", O_WRONLY | O_CREAT); +// if (fd >= 0) +// { +// if (write(fd, str, sizeof(str)) == sizeof(str)) +// rt_kprintf("Write data done.\n"); + +// close(fd); +// } + +// fd = open("/user/test.txt", O_RDONLY); +// if (fd >= 0) +// { +// size = read(fd, buf, sizeof(buf)); + +// close(fd); + +// if (size == sizeof(str)) +// rt_kprintf("Read data from file test.txt(size: %d): %s \n", size, buf); +// } +//} +//MSH_CMD_EXPORT(elmfat_sample, elmfat sample); +//#endif + +#ifdef RT_USING_SDIO +#define SDCARD_NAME "sd0" + +#include "dfs_posix.h" + +static void sdio_elmfat_sample(void) +{ + int fd, size; + struct statfs elm_stat; + char str[] = "elmfat mount to sdcard.\n", buf[80]; + + if (dfs_mkfs("elm", SDCARD_NAME) == 0) + rt_kprintf("make elmfat filesystem success.\n"); + + if (dfs_mount(SDCARD_NAME, "/", "elm", 0, 0) == 0) + rt_kprintf("elmfat filesystem mount success.\n"); + + if (statfs("/", &elm_stat) == 0) + rt_kprintf("elmfat filesystem block size: %d, total blocks: %d, free blocks: %d.\n", + elm_stat.f_bsize, elm_stat.f_blocks, elm_stat.f_bfree); + + if (mkdir("/user", 0x777) == 0) + rt_kprintf("make a directory: '/user'.\n"); + + rt_kprintf("Write string '%s' to /user/test.txt.\n", str); + + fd = open("/user/test.txt", O_WRONLY | O_CREAT); + if (fd >= 0) + { + if (write(fd, str, sizeof(str)) == sizeof(str)) + rt_kprintf("Write data done.\n"); + + close(fd); + } + + fd = open("/user/test.txt", O_RDONLY); + if (fd >= 0) + { + size = read(fd, buf, sizeof(buf)); + + close(fd); + + if (size == sizeof(str)) + rt_kprintf("Read data from file test.txt(size: %d): %s \n", size, buf); + } +} +MSH_CMD_EXPORT(sdio_elmfat_sample, sdio elmfat sample); +#endif + +#ifdef RT_USING_HWCRYPTO +static void crypto_sample(void) +{ + rt_uint8_t temp[] = {0, 1, 2, 3, 4, 5, 6, 7}; + struct rt_hwcrypto_ctx *ctx; + rt_uint32_t result = 0; + struct hwcrypto_crc_cfg cfg = + { + .last_val = 0x0, + .poly = 0x04C11DB7, + .width = 8, + .xorout = 0x00000000, + .flags = 0, + }; + + ctx = rt_hwcrypto_crc_create(rt_hwcrypto_dev_default(), HWCRYPTO_CRC_CRC32); + rt_hwcrypto_crc_cfg(ctx, &cfg); + result = rt_hwcrypto_crc_update(ctx, temp, sizeof(temp)); + rt_kprintf("result: 0x%08x \n", result); + rt_hwcrypto_crc_destroy(ctx); +} +MSH_CMD_EXPORT(crypto_sample, crypto sample); +#endif + +#ifdef BSP_USING_NOR_FLASH +#define NORFLASH_DEV_NAME "nor" +static int norflash_sample(int argc, char *argv[]) +{ + rt_err_t ret = RT_EOK; + rt_device_t hw_dev = RT_NULL; + + hw_dev = rt_device_find(NORFLASH_DEV_NAME); + if (hw_dev == RT_NULL) + { + rt_kprintf("norflash sample run failed! can't find %s device!\n", NORFLASH_DEV_NAME); + return RT_ERROR; + } + else + { + rt_kprintf("norflash sample run success! find %s device!\n", NORFLASH_DEV_NAME); + } + + ret = rt_device_open(hw_dev, RT_DEVICE_OFLAG_RDWR); + if (ret != RT_EOK) + { + rt_kprintf("open %s device failed!\n", NORFLASH_DEV_NAME); + return ret; + } + else + { + rt_kprintf("open %s device success!\n", NORFLASH_DEV_NAME); + } + + struct rt_mtd_nor_device *hw_nor; + hw_nor = RT_MTD_NOR_DEVICE(hw_dev); + long id = hw_nor->ops->read_id(hw_nor); + rt_kprintf("id = %08x!\n", id); + // rt_device_set_rx_indicate(hw_dev, timeout_cb); + + // mode = HWTIMER_MODE_PERIOD; + // //mode = HWTIMER_MODE_ONESHOT; + // ret = rt_device_control(hw_dev, HWTIMER_CTRL_MODE_SET, &mode); + // if (ret != RT_EOK) + // { + // rt_kprintf("set mode failed! ret is :%d\n", ret); + // return ret; + // } + + // timeout_s.sec = 2; + // timeout_s.usec = 0; + + // if (rt_device_write(hw_dev, 0, &timeout_s, sizeof(timeout_s)) != sizeof(timeout_s)) + // { + // rt_kprintf("set timeout value failed\n"); + // return RT_ERROR; + // } + + // rt_thread_mdelay(3500); + + // rt_device_read(hw_dev, 0, &timeout_s, sizeof(timeout_s)); + // rt_kprintf("Read: Sec = %d, Usec = %d\n", timeout_s.sec, timeout_s.usec); + + return ret; +} +MSH_CMD_EXPORT(norflash_sample, norflash sample); +#endif diff --git a/bsp/swm320-lq100/drivers/Kconfig b/bsp/swm320-lq100/drivers/Kconfig index 64d5c99241..2ad515ae90 100644 --- a/bsp/swm320-lq100/drivers/Kconfig +++ b/bsp/swm320-lq100/drivers/Kconfig @@ -1,169 +1,306 @@ menu "Hardware Drivers Config" - menu "On-chip Peripheral Drivers" - config BSP_USING_GPIO - bool "Enable GPIO" - select RT_USING_PIN - default y - - config BSP_USING_WDT - bool "Enable Watch Dog" - select RT_USING_WDT - default n +config SOC_SWM320 + bool + select RT_USING_COMPONENTS_INIT + select RT_USING_USER_MAIN + default y - menu "UART Drivers" - config BSP_USING_UART0 - bool "Enable UART0 PA2/3(R/T)" - select RT_USING_SERIAL - default y +menu "On-chip Peripheral Drivers" + menuconfig BSP_USING_UART + bool "Enable UART" + default y + select RT_USING_SERIAL + if BSP_USING_UART + config BSP_USING_UART0 + bool "Enable UART0 (A2/RX,A3/TX)" + default y config BSP_USING_UART1 - bool "Enable UART1 PC2/3(R/T)" - select RT_USING_SERIAL + bool "Enable UART1 (C2/RX,C3/TX)" default n - config BSP_USING_UART2 - bool "Enable UART2 PC4/5(R/T)" - select RT_USING_SERIAL + bool "Enable UART2 (C4/RX,C5/TX)" default n - config BSP_USING_UART3 - bool "Enable UART3 PC6/7(R/T)" - select RT_USING_SERIAL - default n - endmenu + bool "Enable UART3 (C6/RX,C7/TX)" + default n + endif - menu "SPI Drivers" - config BSP_USING_SPI0 - bool "Enable SPI0 BUS PC4/5/6(C/O/I)" - select RT_USING_SPI - select RT_USING_PIN - default n + config BSP_USING_GPIO + bool "Enable GPIO" + select RT_USING_PIN + default y - config BSP_USING_SPI1 - bool "Enable SPI1 BUS PM5/C2/C3(C/O/I)" - select RT_USING_SPI - select RT_USING_PIN + menuconfig BSP_USING_ADC + bool "Enable ADC" + default n + select RT_USING_ADC + if BSP_USING_ADC + config BSP_USING_ADC0 + bool "Enable ADC0" default n - endmenu - - menu "I2C Drivers" - config BSP_USING_I2C - bool "Enable I2C BUS" - select RT_USING_I2C - select RT_USING_PIN - select RT_USING_I2C_BITOPS + if BSP_USING_ADC0 + config BSP_USING_ADC0_CHN0 + bool "Enable ADC0_CHN0" + default n + config BSP_USING_ADC0_CHN1 + bool "Enable ADC0_CHN1" + default n + config BSP_USING_ADC0_CHN2 + bool "Enable ADC0_CHN2" + default n + config BSP_USING_ADC0_CHN3 + bool "Enable ADC0_CHN3" + default n + config BSP_USING_ADC0_CHN4 + bool "Enable ADC0_CHN4(A12)" + default n + config BSP_USING_ADC0_CHN5 + bool "Enable ADC0_CHN5(A11)" + default n + config BSP_USING_ADC0_CHN6 + bool "Enable ADC0_CHN6(A10)" + default n + config BSP_USING_ADC0_CHN7 + bool "Enable ADC0_CHN7(A9)" + default n + endif + config BSP_USING_ADC1 + bool "Enable ADC1" default n - - if BSP_USING_I2C - - config BSP_I2C_SCL - int "I2C SCL Pin index" - default 98 - - config BSP_I2C_SDA - int "I2C SDA Pin index" - default 99 - - config BSP_I2C_BUS_NAME - string "i2c bus name" - default "i2c0" + if BSP_USING_ADC1 + config BSP_USING_ADC1_CHN0 + bool "Enable ADC1_CHN0(C7)" + default n + config BSP_USING_ADC1_CHN1 + bool "Enable ADC1_CHN1(C6)" + default n + config BSP_USING_ADC1_CHN2 + bool "Enable ADC1_CHN2(C5)" + default n + config BSP_USING_ADC1_CHN3 + bool "Enable ADC1_CHN3(C4)" + default n + config BSP_USING_ADC1_CHN4 + bool "Enable ADC1_CHN4(N0)" + default n + config BSP_USING_ADC1_CHN5 + bool "Enable ADC1_CHN5(N1)" + default n + config BSP_USING_ADC1_CHN6 + bool "Enable ADC1_CHN6(N2)" + default n + config BSP_USING_ADC1_CHN7 + bool "Enable ADC1_CHN7" + default n endif - endmenu + endif - menu "PWM Drivers" - config BSP_USING_PWM0 - bool "Using PWM0 PA4/10(A/B)" - select RT_USING_PWM - default n - - config BSP_USING_PWM1 - bool "Using PWM1 PA5/9(A/B)" - select RT_USING_PWM - default n + menuconfig BSP_USING_TIM + bool "Enable HWTIMER" + default n + select RT_USING_HWTIMER + if BSP_USING_TIM + config BSP_USING_TIM0 + bool "Enable TIM0" + default n + config BSP_USING_TIM1 + bool "Enable TIM1" + default n + config BSP_USING_TIM2 + bool "Enable TIM2" + default n + config BSP_USING_TIM3 + bool "Enable TIM3" + default n - config BSP_USING_PWM2 - bool "Using PWM2 PP0/2(A/B)" - select RT_USING_PWM - default n + config BSP_USING_TIM4 + bool "Enable TIM4" + default n + config BSP_USING_TIM5 + bool "Enable TIM5" + default n + endif - config BSP_USING_PWM3 - bool "Using PWM3 PP1/3(A/B)" - select RT_USING_PWM - default n - endmenu + menuconfig BSP_USING_I2C + bool "Enable I2C BUS (software simulation)" + default n + select RT_USING_I2C + select RT_USING_I2C_BITOPS + select RT_USING_PIN + if BSP_USING_I2C + config BSP_USING_I2C0 + bool "Enable I2C0" + default n + if BSP_USING_I2C0 + comment "Notice: PC2 --> 28; PC3 --> 29" + config BSP_I2C0_SCL_PIN + int "I2C0 scl pin number" + range 0 99 + default 28 + config BSP_I2C0_SDA_PIN + int "I2C0 sda pin number" + range 0 99 + default 29 + endif + config BSP_USING_I2C1 + bool "Enable I2C1" + default n + if BSP_USING_I2C1 + comment "Notice: PC6 --> 32; PC7 --> 33" + config BSP_I2C1_SCL_PIN + int "I2C1 scl pin number" + range 0 99 + default 32 + config BSP_I2C1_SDA_PIN + int "I2C1 sda pin number" + range 0 99 + default 33 + endif + endif - menu "RTC Drivers" - config BSP_USING_RTC - bool "Using RTC" - select RT_USING_RTC - default n - endmenu + menuconfig BSP_USING_PWM + bool "Enable PWM" + default n + select RT_USING_PWM + if BSP_USING_PWM + config BSP_USING_PWM0 + bool "Enable PWM0" + default n + if BSP_USING_PWM0 + config BSP_USING_PWM0A + bool "Enable PWM0A (C2)" + default n + config BSP_USING_PWM0B + bool "Enable PWM0B (C4)" + default n + endif + config BSP_USING_PWM1 + bool "Enable PWM1" + default n + if BSP_USING_PWM1 + config BSP_USING_PWM1A + bool "Enable PWM1A (C3)" + default n + config BSP_USING_PWM1B + bool "Enable PWM1B (C5)" + default n + endif + config BSP_USING_PWM2 + bool "Enable PWM2" + default n + if BSP_USING_PWM2 + config BSP_USING_PWM2A + bool "Enable PWM2A (N4)" + default n + config BSP_USING_PWM2B + bool "Enable PWM2B (N6)" + default n + endif + config BSP_USING_PWM3 + bool "Enable PWM3" + default n + if BSP_USING_PWM3 + config BSP_USING_PWM3A + bool "Enable PWM3A (N3)" + default n + config BSP_USING_PWM3B + bool "Enable PWM3B (N5)" + default n + endif + config BSP_USING_PWM4 + bool "Enable PWM4" + default n + if BSP_USING_PWM4 + config BSP_USING_PWM4A + bool "Enable PWM4A (N8)" + default n + config BSP_USING_PWM4B + bool "Enable PWM4B (N10)" + default n + endif + config BSP_USING_PWM5 + bool "Enable PWM5" + default n + if BSP_USING_PWM5 + config BSP_USING_PWM5A + bool "Enable PWM5A (N7)" + default n + config BSP_USING_PWM5B + bool "Enable PWM5B (N9)" + default n + endif + endif - menu "HWtimer Drivers" - config BSP_USING_HWTIMER0 - bool "Using timer0" - select RT_USING_HWTIMER - default n + config BSP_USING_RTC + bool "Enable RTC" + select RT_USING_RTC + select RT_USING_LIBC + default n - config BSP_USING_HWTIMER1 - bool "Using timer1" - select RT_USING_HWTIMER + menuconfig BSP_USING_SPI + bool "Enable SPI BUS" + default n + select RT_USING_SPI + if BSP_USING_SPI + config BSP_USING_SPI0 + bool "Enable SPI0 BUS(CS/P22,MISO/P19,MOSI/P18,CLK/P23)" default n - config BSP_USING_HWTIMER2 - bool "Using timer2" - select RT_USING_HWTIMER + config BSP_USING_SPI1 + bool "Enable SPI1 BUS(CS/B6,MISO/B3,MOSI/B2,CLK/B1)" default n + endif - config BSP_USING_HWTIMER3 - bool "Using timer3" - select RT_USING_HWTIMER - default n + config BSP_USING_WDT + bool "Enable Watchdog Timer" + select RT_USING_WDT + default n - config BSP_USING_HWTIMER4 - bool "Using timer4" - select RT_USING_HWTIMER - default n + config BSP_USING_CRC + bool "Enable CRC (CRC-32 0x04C11DB7 Polynomial)" + select RT_USING_HWCRYPTO + select RT_HWCRYPTO_USING_CRC + default n +endmenu - config BSP_USING_HWTIMER5 - bool "Using timer5" - select RT_USING_HWTIMER - default n - endmenu - endmenu - - menu "Onboard Peripheral Drivers" - menuconfig BSP_USING_EXT_SRAM - bool "Enable external sram" - select RT_USING_MEMHEAP - select RT_USING_MEMHEAP_AS_HEAP - default n +menu "Onboard Peripheral Drivers" + config BSP_USING_SDIO + bool "Enable SDCARD (sdio)" + select RT_USING_SDIO + select RT_USING_DFS + select RT_USING_DFS_ELMFAT + default n - if BSP_USING_EXT_SRAM - config BSP_EXT_SRAM_SIZE - hex "external sram size" - default 0x100000 - endif + menuconfig BSP_USING_EXT_SRAM + bool "Enable external sram" + select RT_USING_MEMHEAP + select RT_USING_MEMHEAP_AS_HEAP + default n + if BSP_USING_EXT_SRAM + config BSP_EXT_SRAM_SIZE + hex "external sram size" + default 0x100000 + endif menuconfig BSP_USING_NOR_FLASH - bool "Enable mtd nor flash" - select RT_USING_MTD_NOR - select PKG_USING_FTL_SRC - default n + bool "Enable mtd nor flash" + select RT_USING_MTD_NOR + select PKG_USING_FTL_SRC + default n + if BSP_USING_NOR_FLASH + config BSP_NOR_FLASH_SIZE + hex "mtd nor flash size" + default 0x1000000 + config BSP_NOR_FLASH_SECTOR_SIZE + hex "mtd nor flsah sector" + default 0x10000 + endif +endmenu - if BSP_USING_NOR_FLASH - config BSP_NOR_FLASH_SIZE - hex "mtd nor flash size" - default 0x1000000 - config BSP_NOR_FLASH_SECTOR_SIZE - hex "mtd nor flsah sector" - default 0x10000 - endif - endmenu - - menu "Offboard Peripheral Drivers" +menu "Offboard Peripheral Drivers" + +endmenu - endmenu - endmenu diff --git a/bsp/swm320-lq100/drivers/SConscript b/bsp/swm320-lq100/drivers/SConscript index 0d9187d78a..cddf8cc0b7 100644 --- a/bsp/swm320-lq100/drivers/SConscript +++ b/bsp/swm320-lq100/drivers/SConscript @@ -1,55 +1,51 @@ -# RT-Thread building script for component - from building import * -cwd = GetCurrentDir() +cwd = GetCurrentDir() -# add the general drivers. -src = Split(""" -board.c -""") +CPPPATH = [cwd] -# add gpio driver code -if GetDepend(['BSP_USING_GPIO']): - src += ['drv_gpio.c'] +src = Split(''' + board.c + ''') -# add serial driver code -if GetDepend('BSP_USING_UART0') or GetDepend('BSP_USING_UART1') or GetDepend('BSP_USING_UART2') or GetDepend('BSP_USING_UART3'): +if GetDepend(['RT_USING_SERIAL']): src += ['drv_uart.c'] -# add spi driver code -if GetDepend('BSP_USING_SPI0') or GetDepend('BSP_USING_SPI1'): - src += ['drv_spi.c'] +if GetDepend(['RT_USING_PIN']): + src += ['drv_gpio.c'] -# add i2c driver code -if GetDepend(['BSP_USING_I2C']): - src += ['drv_i2c.c'] +if GetDepend(['RT_USING_ADC']): + src += ['drv_adc.c'] -# add sram driver code -if GetDepend(['BSP_USING_EXT_SRAM']): - src += ['drv_sram.c'] +if GetDepend(['RT_USING_HWTIMER']): + src += ['drv_hwtimer.c'] -# add nor flash driver code -if GetDepend(['BSP_USING_NOR_FLASH']): - src += ['drv_nor_flash.c'] +if GetDepend(['RT_USING_I2C']): + src += ['drv_soft_i2c.c'] -# add pwm driver code -if GetDepend('BSP_USING_PWM0') or GetDepend('BSP_USING_PWM1') or GetDepend('BSP_USING_PWM2') or GetDepend('BSP_USING_PWM3'): +if GetDepend(['RT_USING_PWM']): src += ['drv_pwm.c'] -# add rtc driver code -if GetDepend(['BSP_USING_RTC']): +if GetDepend(['RT_USING_RTC']): src += ['drv_rtc.c'] -# add hwtimer driver code -if GetDepend(['BSP_USING_WDT']): - src += ['drv_iwg.c'] +if GetDepend(['RT_USING_SPI']): + src += ['drv_spi.c'] -# add hwtimer driver code -if GetDepend('BSP_USING_HWTIMER0') or GetDepend('BSP_USING_HWTIMER1') or GetDepend('BSP_USING_HWTIMER2') or GetDepend('BSP_USING_HWTIMER3') or GetDepend('BSP_USING_HWTIMER4') or GetDepend('BSP_USING_HWTIMER5'): - src += ['drv_hwtimer.c'] +if GetDepend(['RT_USING_WDT']): + src += ['drv_wdt.c'] -CPPPATH = [cwd] +if GetDepend(['RT_USING_SDIO']): + src += ['drv_sdio.c'] + +if GetDepend(['RT_USING_HWCRYPTO']): + src += ['drv_crypto.c'] + +if GetDepend(['BSP_USING_EXT_SRAM']): + src += ['drv_sram.c'] + +if GetDepend(['BSP_USING_NOR_FLASH']): + src += ['drv_nor_flash.c'] group = DefineGroup('Drivers', src, depend = [''], CPPPATH = CPPPATH) diff --git a/bsp/swm320-lq100/drivers/board.c b/bsp/swm320-lq100/drivers/board.c index 36e6a8f4ea..f42bd98986 100644 --- a/bsp/swm320-lq100/drivers/board.c +++ b/bsp/swm320-lq100/drivers/board.c @@ -9,16 +9,15 @@ * 2018-12-10 Zohar_Lee format file */ -#include <board.h> -#if defined(BSP_USING_EXT_SRAM) && defined(RT_USING_MEMHEAP_AS_HEAP) - static struct rt_memheap system_heap; -#endif +#include "board.h" + static void bsp_clock_config(void) { SystemInit(); SysTick_Config(SystemCoreClock / RT_TICK_PER_SECOND); SysTick->CTRL |= 0x00000004UL; } + void SysTick_Handler(void) { /* enter interrupt */ @@ -29,20 +28,47 @@ void SysTick_Handler(void) /* leave interrupt */ rt_interrupt_leave(); } -#ifdef BSP_USING_EXT_SRAM - extern int rt_hw_sram_init(void); -#endif + +/** + * This function will delay for some us. + * + * @param us the delay time of us + */ +void rt_hw_us_delay(rt_uint32_t us) +{ + rt_uint32_t ticks; + rt_uint32_t told, tnow, tcnt = 0; + rt_uint32_t reload = SysTick->LOAD; + + ticks = us * reload / (1000000 / RT_TICK_PER_SECOND); + told = SysTick->VAL; + while (1) + { + tnow = SysTick->VAL; + if (tnow != told) + { + if (tnow < told) + { + tcnt += told - tnow; + } + else + { + tcnt += reload - tnow + told; + } + told = tnow; + if (tcnt >= ticks) + { + break; + } + } + } +} + void rt_hw_board_init() { bsp_clock_config(); -#ifdef BSP_USING_EXT_SRAM - rt_hw_sram_init(); -#endif -#if defined(BSP_USING_EXT_SRAM) && defined(RT_USING_MEMHEAP_AS_HEAP) - rt_system_heap_init((void *)EXT_SRAM_BEGIN, (void *)EXT_SRAM_END); - rt_memheap_init(&system_heap, "sram", (void *)HEAP_BEGIN, HEAP_SIZE); -#elif defined(RT_USING_HEAP) +#ifdef RT_USING_HEAP rt_system_heap_init((void *)HEAP_BEGIN, (void *)HEAP_END); #endif #ifdef RT_USING_COMPONENTS_INIT diff --git a/bsp/swm320-lq100/drivers/board.h b/bsp/swm320-lq100/drivers/board.h index a754b5b8d1..223018920f 100644 --- a/bsp/swm320-lq100/drivers/board.h +++ b/bsp/swm320-lq100/drivers/board.h @@ -9,32 +9,49 @@ * 2018-12-10 Zohar_Lee format file */ -#ifndef BOARD_H__ -#define BOARD_H__ +#ifndef __BOARD_H__ +#define __BOARD_H__ + #include <rtthread.h> +#include <rthw.h> +#include <rtdevice.h> +#include <string.h> #include <SWM320.h> + +#ifdef __cplusplus +extern "C" +{ +#endif + #define SRAM_BASE 0x20000000 #define SRAM_SIZE 0x20000 +#define SRAM_END (SRAM_BASE + SRAM_SIZE) #ifdef BSP_USING_EXT_SRAM - #define EXT_SRAM_BASE SRAMM_BASE - #define EXT_SRAM_SIZE BSP_EXT_SRAM_SIZE - #define EXT_SRAM_BEGIN EXT_SRAM_BASE - #define EXT_SRAM_END (EXT_SRAM_BASE + EXT_SRAM_SIZE) +#define EXT_SRAM_BASE SRAMM_BASE +#define EXT_SRAM_SIZE BSP_EXT_SRAM_SIZE +#define EXT_SRAM_BEGIN EXT_SRAM_BASE +#define EXT_SRAM_END (EXT_SRAM_BASE + EXT_SRAM_SIZE) #endif -#define SRAM_END (SRAM_BASE + SRAM_SIZE) #if defined(__CC_ARM) || defined(__CLANG_ARM) extern int Image$$RW_IRAM1$$ZI$$Limit; - #define HEAP_BEGIN ((void *)&Image$$RW_IRAM1$$ZI$$Limit) +#define HEAP_BEGIN ((void *)&Image$$RW_IRAM1$$ZI$$Limit) #elif __ICCARM__ - #pragma section = "HEAP" - #define HEAP_BEGIN (__segment_end("HEAP")) +#pragma section = "HEAP" +#define HEAP_BEGIN (__segment_end("HEAP")) #else - extern int __bss_end; - #define HEAP_BEGIN ((void *)&__bss_end) +extern int __bss_end; +#define HEAP_BEGIN ((void *)&__bss_end) #endif + #define HEAP_END SRAM_END #define HEAP_SIZE (HEAP_END - (rt_uint32_t)HEAP_BEGIN) -extern void rt_hw_board_init(void); + + void rt_hw_board_init(void); + +#ifdef __cplusplus +} #endif + +#endif /* __BOARD_H__ */ diff --git a/bsp/swm320-lq100/drivers/drv_adc.c b/bsp/swm320-lq100/drivers/drv_adc.c new file mode 100644 index 0000000000..fa557fda46 --- /dev/null +++ b/bsp/swm320-lq100/drivers/drv_adc.c @@ -0,0 +1,217 @@ +/* + * Copyright (c) 2006-2018, Synwit Technology Co.,Ltd. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Change Logs: + * Date Author Notes + * 2020-5-26 lik first version + */ + +#include "drv_adc.h" + +#ifdef RT_USING_ADC +#ifdef BSP_USING_ADC + +//#define DRV_DEBUG +#define LOG_TAG "drv.adc" +#include <drv_log.h> + +static struct swm_adc_cfg adc_cfg[] = + { +#ifdef BSP_USING_ADC0 + ADC0_CFG, +#endif +#ifdef BSP_USING_ADC1 + ADC1_CFG, +#endif + +}; + +static struct swm_adc adc_drv[sizeof(adc_cfg) / sizeof(adc_cfg[0])]; + +static rt_err_t swm_adc_enabled(struct rt_adc_device *adc_device, rt_uint32_t channel, rt_bool_t enabled) +{ + struct swm_adc_cfg *cfg = RT_NULL; + RT_ASSERT(adc_device != RT_NULL); + cfg = adc_device->parent.user_data; + + if (enabled) + { + ADC_Open(cfg->ADCx); + } + else + { + ADC_Close(cfg->ADCx); + } + + return RT_EOK; +} + +static rt_uint32_t swm_adc_get_channel(rt_uint32_t channel) +{ + rt_uint32_t swm_channel = 0; + + switch (channel) + { + case 0: + swm_channel = ADC_CH0; + break; + case 1: + swm_channel = ADC_CH1; + break; + case 2: + swm_channel = ADC_CH2; + break; + case 3: + swm_channel = ADC_CH3; + break; + case 4: + swm_channel = ADC_CH4; + break; + case 5: + swm_channel = ADC_CH5; + break; + case 6: + swm_channel = ADC_CH6; + break; + case 7: + swm_channel = ADC_CH7; + break; + } + + return swm_channel; +} + +static rt_err_t swm_get_adc_value(struct rt_adc_device *adc_device, rt_uint32_t channel, rt_uint32_t *value) +{ + uint32_t adc_chn; + struct swm_adc_cfg *cfg = RT_NULL; + RT_ASSERT(adc_device != RT_NULL); + RT_ASSERT(value != RT_NULL); + cfg = adc_device->parent.user_data; + + if (channel < 8) + { + /* set stm32 ADC channel */ + adc_chn = swm_adc_get_channel(channel); + } + else + { + LOG_E("ADC channel must be between 0 and 7."); + return -RT_ERROR; + } + + /* start ADC */ + ADC_Start(cfg->ADCx); + /* Wait for the ADC to convert */ + while ((cfg->ADCx->CH[channel].STAT & 0x01) == 0) + ; + + /* get ADC value */ + *value = (rt_uint32_t)ADC_Read(cfg->ADCx, adc_chn); + + return RT_EOK; +} + +static const struct rt_adc_ops swm_adc_ops = + { + .enabled = swm_adc_enabled, + .convert = swm_get_adc_value, +}; + +static int rt_hw_adc_init(void) +{ + int i = 0; + int result = RT_EOK; + + for (i = 0; i < sizeof(adc_cfg) / sizeof(adc_cfg[0]); i++) + { + /* ADC init */ + adc_drv[i].cfg = &adc_cfg[i]; + + if (adc_drv[i].cfg->ADCx == ADC0) + { +#ifdef BSP_USING_ADC0_CHN0 + adc_drv[i].cfg->adc_initstruct.channels |= ADC_CH0; +#endif +#ifdef BSP_USING_ADC0_CHN1 + adc_drv[i].cfg->adc_initstruct.channels |= ADC_CH1; +#endif +#ifdef BSP_USING_ADC0_CHN2 + adc_drv[i].cfg->adc_initstruct.channels |= ADC_CH2; +#endif +#ifdef BSP_USING_ADC0_CHN3 + adc_drv[i].cfg->adc_initstruct.channels |= ADC_CH3; +#endif +#ifdef BSP_USING_ADC0_CHN4 + adc_drv[i].cfg->adc_initstruct.channels |= ADC_CH4; + PORT_Init(PORTA, PIN12, PORTA_PIN12_ADC0_IN4, 0); //PA.12 => ADC0.CH4 +#endif +#ifdef BSP_USING_ADC0_CHN5 + adc_drv[i].cfg->adc_initstruct.channels |= ADC_CH5; + PORT_Init(PORTA, PIN11, PORTA_PIN11_ADC0_IN5, 0); //PA.11 => ADC0.CH5 +#endif +#ifdef BSP_USING_ADC0_CHN6 + adc_drv[i].cfg->adc_initstruct.channels |= ADC_CH6; + PORT_Init(PORTA, PIN10, PORTA_PIN10_ADC0_IN6, 0); //PA.10 => ADC0.CH6 +#endif +#ifdef BSP_USING_ADC0_CHN7 + adc_drv[i].cfg->adc_initstruct.channels |= ADC_CH7; + PORT_Init(PORTA, PIN9, PORTA_PIN9_ADC0_IN7, 0); //PA.9 => ADC0.CH7 +#endif + } + else if (adc_drv[i].cfg->ADCx == ADC1) + { +#ifdef BSP_USING_ADC1_CHN0 + adc_drv[i].cfg->adc_initstruct.channels |= ADC_CH0; + PORT_Init(PORTC, PIN7, PORTC_PIN7_ADC1_IN0, 0); //PC.7 => ADC1.CH0 +#endif +#ifdef BSP_USING_ADC1_CHN1 + adc_drv[i].cfg->adc_initstruct.channels |= ADC_CH1; + PORT_Init(PORTC, PIN6, PORTC_PIN6_ADC1_IN1, 0); //PC.6 => ADC1.CH1 +#endif +#ifdef BSP_USING_ADC1_CHN2 + adc_drv[i].cfg->adc_initstruct.channels |= ADC_CH2; + PORT_Init(PORTC, PIN5, PORTC_PIN5_ADC1_IN2, 0); //PC.5 => ADC1.CH2 +#endif +#ifdef BSP_USING_ADC1_CHN3 + adc_drv[i].cfg->adc_initstruct.channels |= ADC_CH3; + PORT_Init(PORTC, PIN4, PORTC_PIN4_ADC1_IN3, 0); //PC.4 => ADC1.CH3 +#endif +#ifdef BSP_USING_ADC1_CHN4 + adc_drv[i].cfg->adc_initstruct.channels |= ADC_CH4; + PORT_Init(PORTN, PIN0, PORTN_PIN0_ADC1_IN4, 0); //PN.0 => ADC1.CH4 +#endif +#ifdef BSP_USING_ADC1_CHN5 + adc_drv[i].cfg->adc_initstruct.channels |= ADC_CH5; + PORT_Init(PORTN, PIN1, PORTN_PIN1_ADC1_IN5, 0); //PN.1 => ADC1.CH5 +#endif +#ifdef BSP_USING_ADC1_CHN6 + adc_drv[i].cfg->adc_initstruct.channels |= ADC_CH6; + PORT_Init(PORTN, PIN2, PORTN_PIN2_ADC1_IN6, 0); //PN.2 => ADC1.CH6 +#endif +#ifdef BSP_USING_ADC1_CHN7 + adc_drv[i].cfg->adc_initstruct.channels |= ADC_CH7; +#endif + } + + ADC_Init(adc_drv[i].cfg->ADCx, &(adc_drv[i].cfg->adc_initstruct)); + ADC_Open(adc_drv[i].cfg->ADCx); + /* register ADC device */ + if (rt_hw_adc_register(&adc_drv[i].adc_device, adc_drv[i].cfg->name, &swm_adc_ops, adc_drv[i].cfg) == RT_EOK) + { + LOG_D("%s init success", adc_drv[i].cfg->name); + } + else + { + LOG_E("%s register failed", adc_drv[i].cfg->name); + result = -RT_ERROR; + } + } + + return result; +} +INIT_BOARD_EXPORT(rt_hw_adc_init); +#endif /* BSP_USING_ADC */ +#endif /* RT_USING_ADC */ diff --git a/bsp/swm320-lq100/drivers/drv_adc.h b/bsp/swm320-lq100/drivers/drv_adc.h new file mode 100644 index 0000000000..04cf207137 --- /dev/null +++ b/bsp/swm320-lq100/drivers/drv_adc.h @@ -0,0 +1,71 @@ +/* + * Copyright (c) 2006-2018, Synwit Technology Co.,Ltd. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Change Logs: + * Date Author Notes + * 2020-5-26 lik first version + */ + +#ifndef __DRV_ADC_H__ +#define __DRV_ADC_H__ + +#include "board.h" + +struct swm_adc_cfg +{ + const char *name; + ADC_TypeDef *ADCx; + ADC_InitStructure adc_initstruct; +}; + +struct swm_adc +{ + struct swm_adc_cfg *cfg; + struct rt_adc_device adc_device; +}; + +#ifdef BSP_USING_ADC0 +#ifndef ADC0_CFG +#define ADC0_CFG \ + { \ + .name = "adc0", \ + .ADCx = ADC0, \ + .adc_initstruct.clk_src = ADC_CLKSRC_VCO_DIV64, \ + .adc_initstruct.clk_div = 25, \ + .adc_initstruct.pga_ref = PGA_REF_INTERNAL, \ + .adc_initstruct.channels = 0, \ + .adc_initstruct.samplAvg = ADC_AVG_SAMPLE1, \ + .adc_initstruct.trig_src = ADC_TRIGSRC_SW, \ + .adc_initstruct.Continue = 0, \ + .adc_initstruct.EOC_IEn = 0, \ + .adc_initstruct.OVF_IEn = 0, \ + .adc_initstruct.HFULL_IEn = 0, \ + .adc_initstruct.FULL_IEn = 0, \ + } +#endif /* ADC0_CFG */ +#endif /* BSP_USING_ADC0 */ + +#ifdef BSP_USING_ADC1 +#ifndef ADC1_CFG +#define ADC1_CFG \ + { \ + .name = "adc1", \ + .ADCx = ADC1, \ + .adc_initstruct.clk_src = ADC_CLKSRC_VCO_DIV64, \ + .adc_initstruct.clk_div = 25, \ + .adc_initstruct.pga_ref = PGA_REF_INTERNAL, \ + .adc_initstruct.channels = 0, \ + .adc_initstruct.samplAvg = ADC_AVG_SAMPLE1, \ + .adc_initstruct.trig_src = ADC_TRIGSRC_SW, \ + .adc_initstruct.Continue = 0, \ + .adc_initstruct.EOC_IEn = 0, \ + .adc_initstruct.OVF_IEn = 0, \ + .adc_initstruct.HFULL_IEn = 0, \ + .adc_initstruct.FULL_IEn = 0, \ + } +#endif /* ADC1_CFG */ +#endif /* BSP_USING_ADC1 */ + +#endif /* __DRV_ADC_H__ */ diff --git a/bsp/swm320-lq100/drivers/drv_crypto.c b/bsp/swm320-lq100/drivers/drv_crypto.c new file mode 100644 index 0000000000..5e97ff987e --- /dev/null +++ b/bsp/swm320-lq100/drivers/drv_crypto.c @@ -0,0 +1,226 @@ +/* + * Copyright (c) 2006-2018, Synwit Technology Co.,Ltd. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Change Logs: + * Date Author Notes + * 2020-07-10 lik first version + */ + +#include "drv_crypto.h" +#include <string.h> + +#ifdef RT_USING_HWCRYPTO + +struct swm_hwcrypto_device +{ + struct rt_hwcrypto_device dev; + struct rt_mutex mutex; +}; + +#ifdef BSP_USING_CRC + +static struct hwcrypto_crc_cfg crc_backup_cfg; + +static rt_uint32_t _crc_update(struct hwcrypto_crc *ctx, const rt_uint8_t *in, rt_size_t length) +{ + rt_uint32_t result = 0; + struct swm_hwcrypto_device *swm_hw_dev = (struct swm_hwcrypto_device *)ctx->parent.device->user_data; + + struct swm_crc_cfg *hw_crc_cfg = (struct swm_crc_cfg *)(ctx->parent.contex); + + rt_mutex_take(&swm_hw_dev->mutex, RT_WAITING_FOREVER); + + if (memcmp(&crc_backup_cfg, &ctx->crc_cfg, sizeof(struct hwcrypto_crc_cfg)) != 0) + { + hw_crc_cfg->CRCx = CRC; + + hw_crc_cfg->inival = ctx->crc_cfg.last_val; + + switch (ctx->crc_cfg.width) + { + case 8: + hw_crc_cfg->crc_inbits = 2; + break; + case 16: + hw_crc_cfg->crc_inbits = 1; + break; + case 32: + hw_crc_cfg->crc_inbits = 0; + break; + default: + goto _exit; + } + switch (ctx->crc_cfg.poly) + { + case 0x1021: + hw_crc_cfg->crc_1632 = 1; + break; + case 0x04C11DB7: + hw_crc_cfg->crc_1632 = 0; + break; + default: + goto _exit; + } + + hw_crc_cfg->crc_out_not = 0; + + switch (ctx->crc_cfg.flags) + { + case 0: + case CRC_FLAG_REFIN: + hw_crc_cfg->crc_out_rev = 0; + break; + case CRC_FLAG_REFOUT: + case CRC_FLAG_REFIN | CRC_FLAG_REFOUT: + hw_crc_cfg->crc_out_rev = 1; + break; + default: + goto _exit; + } + + CRC_Init(hw_crc_cfg->CRCx, (hw_crc_cfg->crc_inbits << 1) | hw_crc_cfg->crc_1632, hw_crc_cfg->crc_out_not, hw_crc_cfg->crc_out_rev, hw_crc_cfg->inival); + memcpy(&crc_backup_cfg, &ctx->crc_cfg, sizeof(struct hwcrypto_crc_cfg)); + } + + for (uint32_t i = 0; i < length; i++) + CRC_Write((uint32_t)in[i]); + result = CRC_Result(); + + ctx->crc_cfg.last_val = result; + + crc_backup_cfg.last_val = ctx->crc_cfg.last_val; + result = (result ? result ^ (ctx->crc_cfg.xorout) : result); + +_exit: + rt_mutex_release(&swm_hw_dev->mutex); + + return result; +} + +static const struct hwcrypto_crc_ops crc_ops = + { + .update = _crc_update, +}; +#endif /* BSP_USING_CRC */ + +static rt_err_t _crypto_create(struct rt_hwcrypto_ctx *ctx) +{ + rt_err_t res = RT_EOK; + + switch (ctx->type & HWCRYPTO_MAIN_TYPE_MASK) + { +#if defined(BSP_USING_CRC) + case HWCRYPTO_TYPE_CRC: + { + struct swm_crc_cfg *contex = rt_calloc(1, sizeof(struct swm_crc_cfg)); + if (RT_NULL == contex) + { + res = -RT_ERROR; + break; + } + contex->CRCx = DEFAULT_CRC; + contex->inival = DEFAULT_INIVAL; + contex->crc_inbits = DEFAULT_INBITS; + contex->crc_1632 = DEFAULT_CRC1632; + contex->crc_out_not = DEFAULT_OUT_NOT; + contex->crc_out_rev = DEFAULT_OUT_REV; + + ctx->contex = contex; + ((struct hwcrypto_crc *)ctx)->ops = &crc_ops; + break; + } +#endif /* BSP_USING_CRC */ + default: + res = -RT_ERROR; + break; + } + return res; +} + +static void _crypto_destroy(struct rt_hwcrypto_ctx *ctx) +{ + struct swm_crc_cfg *hw_crc_cfg = (struct swm_crc_cfg *)(ctx->contex); + switch (ctx->type & HWCRYPTO_MAIN_TYPE_MASK) + { +#if defined(BSP_USING_CRC) + case HWCRYPTO_TYPE_CRC: + hw_crc_cfg->CRCx->CR &= ~CRC_CR_EN_Msk; + break; +#endif /* BSP_USING_CRC */ + default: + break; + } + + rt_free(ctx->contex); +} + +static rt_err_t _crypto_clone(struct rt_hwcrypto_ctx *des, const struct rt_hwcrypto_ctx *src) +{ + rt_err_t res = RT_EOK; + + switch (src->type & HWCRYPTO_MAIN_TYPE_MASK) + { +#if defined(BSP_USING_CRC) + case HWCRYPTO_TYPE_CRC: + if (des->contex && src->contex) + { + rt_memcpy(des->contex, src->contex, sizeof(struct swm_crc_cfg)); + } + break; +#endif /* BSP_USING_CRC */ + default: + res = -RT_ERROR; + break; + } + return res; +} + +static void _crypto_reset(struct rt_hwcrypto_ctx *ctx) +{ + struct swm_crc_cfg *hw_crc_cfg = (struct swm_crc_cfg *)(ctx->contex); + switch (ctx->type & HWCRYPTO_MAIN_TYPE_MASK) + { +#if defined(BSP_USING_CRC) + case HWCRYPTO_TYPE_CRC: + hw_crc_cfg->CRCx->CR &= ~CRC_CR_EN_Msk; + break; +#endif /* BSP_USING_CRC */ + default: + break; + } +} + +static const struct rt_hwcrypto_ops _ops = + { + .create = _crypto_create, + .destroy = _crypto_destroy, + .copy = _crypto_clone, + .reset = _crypto_reset, +}; + +int rt_hw_crypto_init(void) +{ + static struct swm_hwcrypto_device _crypto_dev; + rt_uint32_t cpuid[2] = {0}; + + _crypto_dev.dev.ops = &_ops; + + cpuid[0] = SCB->CPUID; + _crypto_dev.dev.id = 0; + rt_memcpy(&_crypto_dev.dev.id, cpuid, 8); + + _crypto_dev.dev.user_data = &_crypto_dev; + + if (rt_hwcrypto_register(&_crypto_dev.dev, RT_HWCRYPTO_DEFAULT_NAME) != RT_EOK) + { + return -1; + } + rt_mutex_init(&_crypto_dev.mutex, RT_HWCRYPTO_DEFAULT_NAME, RT_IPC_FLAG_FIFO); + return 0; +} +INIT_BOARD_EXPORT(rt_hw_crypto_init); + + +#endif /* RT_USING_HWCRYPTO */ diff --git a/bsp/swm320-lq100/drivers/drv_crypto.h b/bsp/swm320-lq100/drivers/drv_crypto.h new file mode 100644 index 0000000000..3f301f4553 --- /dev/null +++ b/bsp/swm320-lq100/drivers/drv_crypto.h @@ -0,0 +1,40 @@ +/* + * Copyright (c) 2006-2018, Synwit Technology Co.,Ltd. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Change Logs: + * Date Author Notes + * 2020-07-10 lik first version + */ + +#ifndef __DRV_CRYPTO_H__ +#define __DRV_CRYPTO_H__ + +#include "board.h" + +/* swm config class */ +struct swm_crc_cfg +{ + CRC_TypeDef *CRCx; + uint32_t inival; + uint8_t crc_inbits; + uint8_t crc_1632; + uint8_t crc_out_not; + uint8_t crc_out_rev; +}; + +#ifdef BSP_USING_CRC + +#define DEFAULT_CRC (CRC) +#define DEFAULT_INIVAL (0x00000000) +#define DEFAULT_INBITS (2) +#define DEFAULT_CRC1632 (0) +#define DEFAULT_OUT_NOT (0) +#define DEFAULT_OUT_REV (0) + +#endif /* BSP_USING_CRC */ + +int rt_hw_crypto_init(void); + +#endif /* __DRV_CRYPTO_H__ */ diff --git a/bsp/swm320-lq100/drivers/drv_gpio.c b/bsp/swm320-lq100/drivers/drv_gpio.c index 439f36f379..91f0e94f02 100644 --- a/bsp/swm320-lq100/drivers/drv_gpio.c +++ b/bsp/swm320-lq100/drivers/drv_gpio.c @@ -6,162 +6,250 @@ * Change Logs: * Date Author Notes * 2018-05-31 ZYH first version - * 2018-12-10 Zohar_Lee 修复bug + * 2018-12-10 Zohar_Lee fix bug + * 2020-07-10 lik rewrite */ -#include <rtthread.h> -#include <rtdevice.h> -#include <board.h> -#include <SWM320_port.h> -#include <SWM320_gpio.h> -#include <SWM320_exti.h> -#include <rthw.h> +#include "drv_gpio.h" -typedef void (*pin_callback_t)(void *args); -struct pin -{ - uint32_t package_index; - const char *name; - GPIO_TypeDef *port; - uint32_t group_index; - IRQn_Type irq; - rt_uint32_t irq_mode; - pin_callback_t callback; - void *callback_args; -}; -typedef struct pin pin_t; +#ifdef RT_USING_PIN +#ifdef BSP_USING_GPIO -#define SWM32_PIN(a, b, c, d) \ - { \ - a, #b, GPIO##c, d, GPIO##c##_IRQn \ - } -#define GPIO0 ((GPIO_TypeDef *)(0)) -#define GPIO0_IRQn (GPIOA0_IRQn) +static const struct swm_pin_index pins[] = + { + __SWM_PIN(0, A, 0), + __SWM_PIN(1, A, 1), + __SWM_PIN(2, A, 2), + __SWM_PIN(3, A, 3), + __SWM_PIN(4, A, 4), + __SWM_PIN(5, A, 5), + __SWM_PIN(6, A, 6), + __SWM_PIN(7, A, 7), + __SWM_PIN(8, A, 8), + __SWM_PIN(9, A, 9), + __SWM_PIN(10, A, 10), + __SWM_PIN(11, A, 11), + __SWM_PIN(12, A, 12), + + __SWM_PIN(13, B, 0), + __SWM_PIN(14, B, 1), + __SWM_PIN(15, B, 2), + __SWM_PIN(16, B, 3), + __SWM_PIN(17, B, 4), + __SWM_PIN(18, B, 5), + __SWM_PIN(19, B, 6), + __SWM_PIN(20, B, 7), + __SWM_PIN(21, B, 8), + __SWM_PIN(22, B, 9), + __SWM_PIN(23, B, 10), + __SWM_PIN(24, B, 11), + __SWM_PIN(25, B, 12), + + __SWM_PIN(26, C, 0), + __SWM_PIN(27, C, 1), + __SWM_PIN(28, C, 2), + __SWM_PIN(29, C, 3), + __SWM_PIN(30, C, 4), + __SWM_PIN(31, C, 5), + __SWM_PIN(32, C, 6), + __SWM_PIN(33, C, 7), + + __SWM_PIN(34, M, 0), + __SWM_PIN(35, M, 1), + __SWM_PIN(36, M, 2), + __SWM_PIN(37, M, 3), + __SWM_PIN(38, M, 4), + __SWM_PIN(39, M, 5), + __SWM_PIN(40, M, 6), + __SWM_PIN(41, M, 7), + __SWM_PIN(42, M, 8), + __SWM_PIN(43, M, 9), + __SWM_PIN(44, M, 10), + __SWM_PIN(45, M, 11), + __SWM_PIN(46, M, 12), + __SWM_PIN(47, M, 13), + __SWM_PIN(48, M, 14), + __SWM_PIN(49, M, 15), + __SWM_PIN(50, M, 16), + __SWM_PIN(51, M, 17), + __SWM_PIN(52, M, 18), + __SWM_PIN(53, M, 19), + __SWM_PIN(54, M, 20), + __SWM_PIN(55, M, 21), + + __SWM_PIN(56, N, 0), + __SWM_PIN(57, N, 1), + __SWM_PIN(58, N, 2), + __SWM_PIN(59, N, 3), + __SWM_PIN(60, N, 4), + __SWM_PIN(61, N, 5), + __SWM_PIN(62, N, 6), + __SWM_PIN(63, N, 7), + __SWM_PIN(64, N, 8), + __SWM_PIN(65, N, 9), + __SWM_PIN(66, N, 10), + __SWM_PIN(67, N, 11), + __SWM_PIN(68, N, 12), + __SWM_PIN(69, N, 13), + __SWM_PIN(70, N, 14), + __SWM_PIN(71, N, 15), + __SWM_PIN(72, N, 16), + __SWM_PIN(73, N, 17), + __SWM_PIN(74, N, 18), + __SWM_PIN(75, N, 19), + + __SWM_PIN(76, P, 0), + __SWM_PIN(77, P, 1), + __SWM_PIN(78, P, 2), + __SWM_PIN(79, P, 3), + __SWM_PIN(80, P, 4), + __SWM_PIN(81, P, 5), + __SWM_PIN(82, P, 6), + __SWM_PIN(83, P, 7), + __SWM_PIN(84, P, 8), + __SWM_PIN(85, P, 9), + __SWM_PIN(86, P, 10), + __SWM_PIN(87, P, 11), + __SWM_PIN(88, P, 12), + __SWM_PIN(89, P, 13), + __SWM_PIN(90, P, 14), + __SWM_PIN(91, P, 15), + __SWM_PIN(92, P, 16), + __SWM_PIN(93, P, 17), + __SWM_PIN(94, P, 18), + __SWM_PIN(95, P, 19), + __SWM_PIN(96, P, 20), + __SWM_PIN(97, P, 21), + __SWM_PIN(98, P, 22), + __SWM_PIN(99, P, 23)}; + +static struct rt_pin_irq_hdr pin_irq_hdr_tab[] = + { + {0, 0, RT_NULL, RT_NULL}, + {1, 0, RT_NULL, RT_NULL}, + {2, 0, RT_NULL, RT_NULL}, + {3, 0, RT_NULL, RT_NULL}, + {4, 0, RT_NULL, RT_NULL}, + {5, 0, RT_NULL, RT_NULL}, + {6, 0, RT_NULL, RT_NULL}, + {7, 0, RT_NULL, RT_NULL}, + {8, 0, RT_NULL, RT_NULL}, + {9, 0, RT_NULL, RT_NULL}, + {10, 0, RT_NULL, RT_NULL}, + {11, 0, RT_NULL, RT_NULL}, + {12, 0, RT_NULL, RT_NULL}, + {13, 0, RT_NULL, RT_NULL}, + {14, 0, RT_NULL, RT_NULL}, + {15, 0, RT_NULL, RT_NULL}, + {16, 0, RT_NULL, RT_NULL}, + {17, 0, RT_NULL, RT_NULL}, + {18, 0, RT_NULL, RT_NULL}, + {19, 0, RT_NULL, RT_NULL}, + {20, 0, RT_NULL, RT_NULL}, + {21, 0, RT_NULL, RT_NULL}, + {22, 0, RT_NULL, RT_NULL}, + {23, 0, RT_NULL, RT_NULL}, + {24, 0, RT_NULL, RT_NULL}, + {25, 0, RT_NULL, RT_NULL}, + {26, 0, RT_NULL, RT_NULL}, + {27, 0, RT_NULL, RT_NULL}, + {28, 0, RT_NULL, RT_NULL}, + {29, 0, RT_NULL, RT_NULL}, + {30, 0, RT_NULL, RT_NULL}, + {31, 0, RT_NULL, RT_NULL}, + {32, 0, RT_NULL, RT_NULL}, + {33, 0, RT_NULL, RT_NULL}, + {34, 0, RT_NULL, RT_NULL}, + {35, 0, RT_NULL, RT_NULL}, + {36, 0, RT_NULL, RT_NULL}, + {37, 0, RT_NULL, RT_NULL}, + {38, 0, RT_NULL, RT_NULL}, + {39, 0, RT_NULL, RT_NULL}, + {40, 0, RT_NULL, RT_NULL}, + {41, 0, RT_NULL, RT_NULL}, + {42, 0, RT_NULL, RT_NULL}, + {43, 0, RT_NULL, RT_NULL}, + {44, 0, RT_NULL, RT_NULL}, + {45, 0, RT_NULL, RT_NULL}, + {46, 0, RT_NULL, RT_NULL}, + {47, 0, RT_NULL, RT_NULL}, + {48, 0, RT_NULL, RT_NULL}, + {49, 0, RT_NULL, RT_NULL}, + {50, 0, RT_NULL, RT_NULL}, + {51, 0, RT_NULL, RT_NULL}, + {52, 0, RT_NULL, RT_NULL}, + {53, 0, RT_NULL, RT_NULL}, + {54, 0, RT_NULL, RT_NULL}, + {55, 0, RT_NULL, RT_NULL}, + {56, 0, RT_NULL, RT_NULL}, + {57, 0, RT_NULL, RT_NULL}, + {58, 0, RT_NULL, RT_NULL}, + {59, 0, RT_NULL, RT_NULL}, + {60, 0, RT_NULL, RT_NULL}, + {61, 0, RT_NULL, RT_NULL}, + {62, 0, RT_NULL, RT_NULL}, + {63, 0, RT_NULL, RT_NULL}, + {64, 0, RT_NULL, RT_NULL}, + {65, 0, RT_NULL, RT_NULL}, + {66, 0, RT_NULL, RT_NULL}, + {67, 0, RT_NULL, RT_NULL}, + {68, 0, RT_NULL, RT_NULL}, + {69, 0, RT_NULL, RT_NULL}, + {70, 0, RT_NULL, RT_NULL}, + {71, 0, RT_NULL, RT_NULL}, + {72, 0, RT_NULL, RT_NULL}, + {73, 0, RT_NULL, RT_NULL}, + {74, 0, RT_NULL, RT_NULL}, + {75, 0, RT_NULL, RT_NULL}, + {76, 0, RT_NULL, RT_NULL}, + {77, 0, RT_NULL, RT_NULL}, + {78, 0, RT_NULL, RT_NULL}, + {79, 0, RT_NULL, RT_NULL}, + {80, 0, RT_NULL, RT_NULL}, + {81, 0, RT_NULL, RT_NULL}, + {82, 0, RT_NULL, RT_NULL}, + {83, 0, RT_NULL, RT_NULL}, + {84, 0, RT_NULL, RT_NULL}, + {85, 0, RT_NULL, RT_NULL}, + {86, 0, RT_NULL, RT_NULL}, + {87, 0, RT_NULL, RT_NULL}, + {88, 0, RT_NULL, RT_NULL}, + {89, 0, RT_NULL, RT_NULL}, + {90, 0, RT_NULL, RT_NULL}, + {91, 0, RT_NULL, RT_NULL}, + {92, 0, RT_NULL, RT_NULL}, + {93, 0, RT_NULL, RT_NULL}, + {94, 0, RT_NULL, RT_NULL}, + {95, 0, RT_NULL, RT_NULL}, + {96, 0, RT_NULL, RT_NULL}, + {97, 0, RT_NULL, RT_NULL}, + {98, 0, RT_NULL, RT_NULL}, + {99, 0, RT_NULL, RT_NULL}}; -const static pin_t swm32_pin_map[] = -{ - SWM32_PIN(0, None, 0, 0), - SWM32_PIN(1, ADC0 CH3, 0, 0), - SWM32_PIN(2, ADC0 REFP, 0, 0), - SWM32_PIN(3, Cap0, 0, 0), - SWM32_PIN(4, B12, B, 12), - SWM32_PIN(5, RTC VDD, 0, 0), - SWM32_PIN(6, N14, N, 14), - SWM32_PIN(7, N13, N, 13), - SWM32_PIN(8, N12, N, 12), - SWM32_PIN(9, N11, N, 11), - SWM32_PIN(10, VDD 3.3V, 0, 0), - SWM32_PIN(11, VSS 3.3V, 0, 0), - SWM32_PIN(12, Cap 2, 0, 0), - SWM32_PIN(13, N9, N, 9), - SWM32_PIN(14, N10, N, 10), - SWM32_PIN(15, Cap 1, 0, 0), - SWM32_PIN(16, AVSS, 0, 0), - SWM32_PIN(17, AVDD, 0, 0), - SWM32_PIN(18, N2, N, 2), - SWM32_PIN(19, N1, N, 1), - SWM32_PIN(20, N0, N, 0), - SWM32_PIN(21, C4, C, 4), - SWM32_PIN(22, C5, C, 5), - SWM32_PIN(23, C6, C, 6), - SWM32_PIN(24, C7, C, 7), - SWM32_PIN(25, C2, C, 2), - SWM32_PIN(26, C3, C, 3), - SWM32_PIN(27, XHIN, 0, 0), - SWM32_PIN(28, XHOUT, 0, 0), - SWM32_PIN(29, RESET, 0, 0), - SWM32_PIN(30, M2, M, 2), - SWM32_PIN(31, M3, M, 3), - SWM32_PIN(32, M4, M, 4), - SWM32_PIN(33, M5, M, 5), - SWM32_PIN(34, M6, M, 6), - SWM32_PIN(35, M7, M, 7), - SWM32_PIN(36, M8, M, 8), - SWM32_PIN(37, M9, M, 9), - SWM32_PIN(38, M10, M, 10), - SWM32_PIN(39, M11, M, 11), - SWM32_PIN(40, M12, M, 12), - SWM32_PIN(41, M13, M, 13), - SWM32_PIN(42, M14, M, 14), - SWM32_PIN(43, M15, M, 15), - SWM32_PIN(44, M16, M, 16), - SWM32_PIN(45, M17, M, 17), - SWM32_PIN(46, M18, M, 18), - SWM32_PIN(47, M19, M, 19), - SWM32_PIN(48, M20, M, 20), - SWM32_PIN(49, M21, M, 21), - SWM32_PIN(50, VDDIO, 0, 0), - SWM32_PIN(51, M1, M, 1), - SWM32_PIN(52, M0, M, 0), - SWM32_PIN(53, P0, P, 0), - SWM32_PIN(54, P1, P, 1), - SWM32_PIN(55, P2, P, 2), - SWM32_PIN(56, P3, P, 3), - SWM32_PIN(57, P4, P, 4), - SWM32_PIN(58, P5, P, 5), - SWM32_PIN(59, P6, P, 6), - SWM32_PIN(60, P7, P, 7), - SWM32_PIN(61, P8, P, 8), - SWM32_PIN(62, P9, P, 9), - SWM32_PIN(63, P10, P, 10), - SWM32_PIN(64, P11, P, 11), - SWM32_PIN(65, P12, P, 12), - SWM32_PIN(66, P13, P, 13), - SWM32_PIN(67, P14, P, 14), - SWM32_PIN(68, P15, P, 15), - SWM32_PIN(69, P16, P, 16), - SWM32_PIN(70, P17, P, 17), - SWM32_PIN(71, P18, P, 18), - SWM32_PIN(72, P19, P, 19), - SWM32_PIN(73, P20, P, 20), - SWM32_PIN(74, P21, P, 21), - SWM32_PIN(75, P22, P, 22), - SWM32_PIN(76, P23, P, 23), - SWM32_PIN(77, B0, B, 0), - SWM32_PIN(78, A0, A, 0), - SWM32_PIN(79, A1, A, 1), - SWM32_PIN(80, A2, A, 2), - SWM32_PIN(81, A3, A, 3), - SWM32_PIN(82, A4, A, 4), - SWM32_PIN(83, A5, A, 5), - SWM32_PIN(84, VSSIO, 0, 0), - SWM32_PIN(85, C1, C, 1), - SWM32_PIN(86, N19, N, 19), - SWM32_PIN(87, N18, N, 18), - SWM32_PIN(88, N17, N, 17), - SWM32_PIN(89, N16, N, 16), - SWM32_PIN(90, N15, N, 15), - SWM32_PIN(91, N8, N, 8), - SWM32_PIN(92, N7, N, 7), - SWM32_PIN(93, N6, N, 6), - SWM32_PIN(94, N5, N, 5), - SWM32_PIN(95, N4, N, 4), - SWM32_PIN(96, N3, N, 3), - SWM32_PIN(97, A9, A, 9), - SWM32_PIN(98, A10, A, 10), - SWM32_PIN(99, A11, A, 11), - SWM32_PIN(100, A12, A, 12) -}; #define ITEM_NUM(items) sizeof(items) / sizeof(items[0]) -static pin_t *get_pin(uint8_t pin) + +static const struct swm_pin_index *get_pin(uint8_t pin) { - pin_t *index; - if (pin < ITEM_NUM(swm32_pin_map)) + const struct swm_pin_index *index; + + if (pin < ITEM_NUM(pins)) { - index = (pin_t *)&swm32_pin_map[pin]; - if (index->port == GPIO0) + index = &pins[pin]; + if (index->gpio == GPIO0) index = RT_NULL; } else { index = RT_NULL; } + return index; -}; +} -static void swm320_pin_write(rt_device_t dev, rt_base_t pin, rt_base_t value) +static void swm_pin_write(rt_device_t dev, rt_base_t pin, rt_base_t value) { - pin_t *index; + const struct swm_pin_index *index; + index = get_pin(pin); if (index == RT_NULL) { @@ -169,201 +257,206 @@ static void swm320_pin_write(rt_device_t dev, rt_base_t pin, rt_base_t value) } if (value) { - GPIO_SetBit(index->port, index->group_index); + GPIO_SetBit(index->gpio, index->pin); } else { - GPIO_ClrBit(index->port, index->group_index); + GPIO_ClrBit(index->gpio, index->pin); } } -static int swm320_pin_read(rt_device_t dev, rt_base_t pin) +static int swm_pin_read(rt_device_t dev, rt_base_t pin) { - pin_t *index; + const struct swm_pin_index *index; + index = get_pin(pin); if (index == RT_NULL) { return PIN_LOW; } - return GPIO_GetBit(index->port, index->group_index); + return (int)GPIO_GetBit(index->gpio, index->pin); } -static void swm320_pin_mode(rt_device_t dev, rt_base_t pin, rt_base_t mode) +static void swm_pin_mode(rt_device_t dev, rt_base_t pin, rt_base_t mode) { - pin_t *index; + const struct swm_pin_index *index; int dir = 0; int pull_up = 0; int pull_down = 0; + index = get_pin(pin); if (index == RT_NULL) { return; } /* Configure GPIO_InitStructure */ - if (mode == PIN_MODE_OUTPUT) + switch (mode) { + case PIN_MODE_OUTPUT: /* output setting */ dir = 1; - } - else if (mode == PIN_MODE_INPUT) - { + break; + case PIN_MODE_INPUT: /* input setting: not pull. */ dir = 0; - } - else if (mode == PIN_MODE_INPUT_PULLUP) - { + break; + case PIN_MODE_INPUT_PULLUP: /* input setting: pull up. */ dir = 0; pull_up = 1; - } - else if (mode == PIN_MODE_INPUT_PULLDOWN) - { + break; + case PIN_MODE_INPUT_PULLDOWN: /* input setting: pull down. */ dir = 0; pull_down = 1; - } - else if (mode == PIN_MODE_OUTPUT_OD) - { + break; + case PIN_MODE_OUTPUT_OD: /* output setting: od. */ dir = 1; pull_up = 1; + break; } - GPIO_Init(index->port, index->group_index, dir, pull_up, pull_down); + + GPIO_Init(index->gpio, index->pin, dir, pull_up, pull_down); } -static rt_err_t swm320_pin_attach_irq(struct rt_device *device, - rt_int32_t pin, - rt_uint32_t mode, - pin_callback_t cb, - void *args) +static rt_err_t swm_pin_attach_irq(struct rt_device *device, + rt_int32_t pin, + rt_uint32_t mode, + void (*hdr)(void *args), + void *args) { - pin_t *index; + const struct swm_pin_index *index; rt_base_t level; + index = get_pin(pin); if (index == RT_NULL) { - return RT_EINVAL; + return RT_ENOSYS; } - level = rt_hw_interrupt_disable(); - index->callback = cb; - index->callback_args = args; - index->irq_mode = mode; + level = rt_hw_interrupt_disable(); + if (pin_irq_hdr_tab[pin].pin == pin && + pin_irq_hdr_tab[pin].mode == mode && + pin_irq_hdr_tab[pin].hdr == hdr && + pin_irq_hdr_tab[pin].args == args) + { + rt_hw_interrupt_enable(level); + return RT_EOK; + } + pin_irq_hdr_tab[pin].pin = pin; + pin_irq_hdr_tab[pin].mode = mode; + pin_irq_hdr_tab[pin].hdr = hdr; + pin_irq_hdr_tab[pin].args = args; rt_hw_interrupt_enable(level); return RT_EOK; } -static rt_err_t swm320_pin_detach_irq(struct rt_device *device, rt_int32_t pin) +static rt_err_t swm_pin_detach_irq(struct rt_device *device, rt_int32_t pin) { - pin_t *index; + const struct swm_pin_index *index; rt_base_t level; + index = get_pin(pin); if (index == RT_NULL) { - return RT_EINVAL; + return RT_ENOSYS; } + level = rt_hw_interrupt_disable(); - index->callback = 0; - index->callback_args = 0; - index->irq_mode = 0; + pin_irq_hdr_tab[pin].mode = 0; + pin_irq_hdr_tab[pin].hdr = RT_NULL; + pin_irq_hdr_tab[pin].args = RT_NULL; rt_hw_interrupt_enable(level); return RT_EOK; } -static rt_err_t swm320_pin_irq_enable(struct rt_device *device, - rt_base_t pin, - rt_uint32_t enabled) +static rt_err_t swm_pin_irq_enable(struct rt_device *device, + rt_base_t pin, + rt_uint32_t enabled) { - pin_t *index; + const struct swm_pin_index *index; rt_base_t level = 0; + index = get_pin(pin); if (index == RT_NULL) { - return RT_EINVAL; + return RT_ENOSYS; } + if (enabled == PIN_IRQ_ENABLE) { - switch (index->irq_mode) + switch (pin_irq_hdr_tab[pin].mode) { case PIN_IRQ_MODE_RISING: - GPIO_Init(index->port, index->group_index, 0, 0, 1); - EXTI_Init(index->port, index->group_index, EXTI_RISE_EDGE); + GPIO_Init(index->gpio, index->pin, 0, 0, 1); + EXTI_Init(index->gpio, index->pin, EXTI_RISE_EDGE); break; case PIN_IRQ_MODE_FALLING: - GPIO_Init(index->port, index->group_index, 0, 1, 0); - EXTI_Init(index->port, index->group_index, EXTI_FALL_EDGE); + GPIO_Init(index->gpio, index->pin, 0, 1, 0); + EXTI_Init(index->gpio, index->pin, EXTI_FALL_EDGE); break; case PIN_IRQ_MODE_RISING_FALLING: - GPIO_Init(index->port, index->group_index, 0, 1, 1); - EXTI_Init(index->port, index->group_index, EXTI_BOTH_EDGE); + GPIO_Init(index->gpio, index->pin, 0, 1, 1); + EXTI_Init(index->gpio, index->pin, EXTI_BOTH_EDGE); break; case PIN_IRQ_MODE_HIGH_LEVEL: - GPIO_Init(index->port, index->group_index, 0, 0, 1); - EXTI_Init(index->port, index->group_index, EXTI_HIGH_LEVEL); + GPIO_Init(index->gpio, index->pin, 0, 0, 1); + EXTI_Init(index->gpio, index->pin, EXTI_HIGH_LEVEL); break; case PIN_IRQ_MODE_LOW_LEVEL: - GPIO_Init(index->port, index->group_index, 0, 1, 0); - EXTI_Init(index->port, index->group_index, EXTI_LOW_LEVEL); + GPIO_Init(index->gpio, index->pin, 0, 1, 0); + EXTI_Init(index->gpio, index->pin, EXTI_LOW_LEVEL); break; default: - rt_hw_interrupt_enable(level); return RT_EINVAL; } level = rt_hw_interrupt_disable(); NVIC_EnableIRQ(index->irq); - EXTI_Open(index->port, index->group_index); + EXTI_Open(index->gpio, index->pin); rt_hw_interrupt_enable(level); } else if (enabled == PIN_IRQ_DISABLE) { + level = rt_hw_interrupt_disable(); NVIC_DisableIRQ(index->irq); - EXTI_Close(index->port, index->group_index); + EXTI_Close(index->gpio, index->pin); + rt_hw_interrupt_enable(level); } else { - return RT_ENOSYS; + return -RT_ENOSYS; } return RT_EOK; } -const static struct rt_pin_ops swm320_pin_ops = -{ - swm320_pin_mode, - swm320_pin_write, - swm320_pin_read, - swm320_pin_attach_irq, - swm320_pin_detach_irq, - swm320_pin_irq_enable, - RT_NULL, -}; - -int rt_hw_pin_init(void) -{ - int result; - result = rt_device_pin_register("pin", &swm320_pin_ops, RT_NULL); - return result; -} -INIT_BOARD_EXPORT(rt_hw_pin_init); +const static struct rt_pin_ops swm_pin_ops = + { + .pin_mode = swm_pin_mode, + .pin_write = swm_pin_write, + .pin_read = swm_pin_read, + .pin_attach_irq = swm_pin_attach_irq, + .pin_detach_irq = swm_pin_detach_irq, + .pin_irq_enable = swm_pin_irq_enable}; -void GPIOA_Handler(void) +static void rt_hw_pin_isr(GPIO_TypeDef *GPIOx) { static int gpio[24]; int index = 0; static int init = 0; - pin_t *pin; - /* enter interrupt */ - rt_interrupt_enter(); + const struct swm_pin_index *pin; + if (init == 0) { init = 1; - for (pin = (pin_t *)&swm32_pin_map[1]; - pin->package_index < ITEM_NUM(swm32_pin_map); - pin++) + for (pin = &pins[0]; + pin->index < ITEM_NUM(pins); + pin++) { - if (pin->port == GPIOA) + if (pin->gpio == GPIOx) { - gpio[index] = pin->package_index; + gpio[index] = pin->index; index++; RT_ASSERT(index <= 24) } @@ -372,228 +465,64 @@ void GPIOA_Handler(void) for (index = 0; index < 24; index++) { pin = get_pin(gpio[index]); - if (index != RT_NULL) + if (EXTI_State(pin->gpio, pin->pin)) { - if (EXTI_State(pin->port, pin->group_index)) + EXTI_Clear(pin->gpio, pin->pin); + if (pin_irq_hdr_tab[pin->index].hdr) { - EXTI_Clear(pin->port, pin->group_index); - if (pin->callback) - { - pin->callback(pin->callback_args); - } + pin_irq_hdr_tab[pin->index].hdr(pin_irq_hdr_tab[pin->index].args); } } } - /* leave interrupt */ +} + +void GPIOA_Handler(void) +{ + rt_interrupt_enter(); + rt_hw_pin_isr(GPIOA); rt_interrupt_leave(); } void GPIOB_Handler(void) { - static int gpio[24]; - int index = 0; - static int init = 0; - pin_t *pin; - /* enter interrupt */ rt_interrupt_enter(); - if (init == 0) - { - init = 1; - for (pin = (pin_t *)&swm32_pin_map[1]; - pin->package_index < ITEM_NUM(swm32_pin_map); - pin++) - { - if (pin->port == GPIOB) - { - gpio[index] = pin->package_index; - index++; - RT_ASSERT(index <= 24) - } - } - } - for (index = 0; index < 24; index++) - { - pin = get_pin(gpio[index]); - if (index != RT_NULL) - { - if (EXTI_State(pin->port, pin->group_index)) - { - EXTI_Clear(pin->port, pin->group_index); - if (pin->callback) - { - pin->callback(pin->callback_args); - } - } - } - } - /* leave interrupt */ + rt_hw_pin_isr(GPIOB); rt_interrupt_leave(); } void GPIOC_Handler(void) { - static int gpio[24]; - int index = 0; - static int init = 0; - pin_t *pin; - /* enter interrupt */ rt_interrupt_enter(); - if (init == 0) - { - init = 1; - for (pin = (pin_t *)&swm32_pin_map[1]; - pin->package_index < ITEM_NUM(swm32_pin_map); - pin++) - { - if (pin->port == GPIOC) - { - gpio[index] = pin->package_index; - index++; - RT_ASSERT(index <= 24) - } - } - } - for (index = 0; index < 24; index++) - { - pin = get_pin(gpio[index]); - if (index != RT_NULL) - { - if (EXTI_State(pin->port, pin->group_index)) - { - EXTI_Clear(pin->port, pin->group_index); - if (pin->callback) - { - pin->callback(pin->callback_args); - } - } - } - } - /* leave interrupt */ + rt_hw_pin_isr(GPIOC); rt_interrupt_leave(); } void GPIOM_Handler(void) { - static int gpio[24]; - int index = 0; - static int init = 0; - pin_t *pin; - /* enter interrupt */ rt_interrupt_enter(); - if (init == 0) - { - init = 1; - for (pin = (pin_t *)&swm32_pin_map[1]; - pin->package_index < ITEM_NUM(swm32_pin_map); - pin++) - { - if (pin->port == GPIOM) - { - gpio[index] = pin->package_index; - index++; - RT_ASSERT(index <= 24) - } - } - } - for (index = 0; index < 24; index++) - { - pin = get_pin(gpio[index]); - if (index != RT_NULL) - { - if (EXTI_State(pin->port, pin->group_index)) - { - EXTI_Clear(pin->port, pin->group_index); - if (pin->callback) - { - pin->callback(pin->callback_args); - } - } - } - } - /* leave interrupt */ + rt_hw_pin_isr(GPIOM); rt_interrupt_leave(); } void GPION_Handler(void) { - static int gpio[24]; - int index = 0; - static int init = 0; - pin_t *pin; - /* enter interrupt */ rt_interrupt_enter(); - if (init == 0) - { - init = 1; - for (pin = (pin_t *)&swm32_pin_map[1]; - pin->package_index < ITEM_NUM(swm32_pin_map); - pin++) - { - if (pin->port == GPION) - { - gpio[index] = pin->package_index; - index++; - RT_ASSERT(index <= 24) - } - } - } - for (index = 0; index < 24; index++) - { - pin = get_pin(gpio[index]); - if (index != RT_NULL) - { - if (EXTI_State(pin->port, pin->group_index)) - { - EXTI_Clear(pin->port, pin->group_index); - if (pin->callback) - { - pin->callback(pin->callback_args); - } - } - } - } - /* leave interrupt */ + rt_hw_pin_isr(GPION); rt_interrupt_leave(); } void GPIOP_Handler(void) { - static int gpio[24]; - int index = 0; - static int init = 0; - pin_t *pin; - /* enter interrupt */ rt_interrupt_enter(); - if (init == 0) - { - init = 1; - for (pin = (pin_t *)&swm32_pin_map[1]; - pin->package_index < ITEM_NUM(swm32_pin_map); - pin++) - { - if (pin->port == GPIOP) - { - gpio[index] = pin->package_index; - index++; - RT_ASSERT(index <= 24) - } - } - } - for (index = 0; index < 24; index++) - { - pin = get_pin(gpio[index]); - if (index != RT_NULL) - { - if (EXTI_State(pin->port, pin->group_index)) - { - EXTI_Clear(pin->port, pin->group_index); - if (pin->callback) - { - pin->callback(pin->callback_args); - } - } - } - } - /* leave interrupt */ + rt_hw_pin_isr(GPIOP); rt_interrupt_leave(); } + +int rt_hw_pin_init(void) +{ + return rt_device_pin_register("pin", &swm_pin_ops, RT_NULL); +} +INIT_BOARD_EXPORT(rt_hw_pin_init); + +#endif /* BSP_USING_GPIO */ +#endif /* RT_USING_PIN */ diff --git a/bsp/swm320-lq100/drivers/drv_gpio.h b/bsp/swm320-lq100/drivers/drv_gpio.h index 4993272726..9e67c2127f 100644 --- a/bsp/swm320-lq100/drivers/drv_gpio.h +++ b/bsp/swm320-lq100/drivers/drv_gpio.h @@ -6,11 +6,30 @@ * Change Logs: * Date Author Notes * 2018-12-10 Zohar_Lee first version + * 2020-07-10 lik rewrite */ -#ifndef DRV_GPIO_H__ -#define DRV_GPIO_H__ +#ifndef __DRV_GPIO_H__ +#define __DRV_GPIO_H__ + +#include "board.h" + +#define __SWM_PIN(index, gpio, pin_index) \ + { \ + index, GPIO##gpio, PIN##pin_index, GPIO##gpio##_IRQn \ + } +#define GPIO0 ((GPIO_TypeDef *)(0)) +#define GPIO0_IRQn (GPIOA0_IRQn) + +struct swm_pin_index +{ + uint32_t index; + GPIO_TypeDef *gpio; + uint32_t pin; + IRQn_Type irq; +}; +typedef struct swm_pin_index pin_t; int rt_hw_pin_init(void); -#endif +#endif /* __DRV_GPIO_H__ */ diff --git a/bsp/swm320-lq100/drivers/drv_hwtimer.c b/bsp/swm320-lq100/drivers/drv_hwtimer.c index b5f76660d5..6881b7170e 100644 --- a/bsp/swm320-lq100/drivers/drv_hwtimer.c +++ b/bsp/swm320-lq100/drivers/drv_hwtimer.c @@ -6,257 +6,251 @@ * Change Logs: * Date Author Notes * 2018-12-10 Zohar_Lee first version + * 2020-07-10 lik format file */ -#include <rthw.h> -#include <rtthread.h> -#include <rtdevice.h> -#include <board.h> +#include "drv_hwtimer.h" -#define SWM320_HWTIMER_DEVICE(hwtimer) (struct swm320_hwtimer_dev *)(hwtimer) +#ifdef RT_USING_HWTIMER +#ifdef BSP_USING_TIM -struct swm320_hwtimer_dev +enum { - rt_hwtimer_t parent; - TIMR_TypeDef *hwtimer_periph; +#ifdef BSP_USING_TIM0 + TIM0_INDEX, +#endif +#ifdef BSP_USING_TIM1 + TIM1_INDEX, +#endif +#ifdef BSP_USING_TIM2 + TIM2_INDEX, +#endif +#ifdef BSP_USING_TIM3 + TIM3_INDEX, +#endif +#ifdef BSP_USING_TIM4 + TIM4_INDEX, +#endif +#ifdef BSP_USING_TIM5 + TIM5_INDEX, +#endif }; -#ifdef BSP_USING_HWTIMER0 -static struct swm320_hwtimer_dev hwtimer0; - -void TIMR0_Handler(void) -{ - TIMR_INTClr(TIMR0); - rt_device_hwtimer_isr(&hwtimer0.parent); - - if (HWTIMER_MODE_ONESHOT == hwtimer0.parent.mode) +static struct swm_hwtimer_cfg hwtimer_cfg[] = { - TIMR_Stop(hwtimer0.hwtimer_periph); - } -} -#endif //BSP_USING_HWTIMER0 +#ifdef BSP_USING_TIM0 + TIM0_CFG, +#endif +#ifdef BSP_USING_TIM1 + TIM1_CFG, +#endif +#ifdef BSP_USING_TIM2 + TIM2_CFG, +#endif +#ifdef BSP_USING_TIM3 + TIM3_CFG, +#endif +#ifdef BSP_USING_TIM4 + TIM4_CFG, +#endif +#ifdef BSP_USING_TIM5 + TIM5_CFG, +#endif +}; -#ifdef BSP_USING_HWTIMER1 -static struct swm320_hwtimer_dev hwtimer1; +static struct swm_hwtimer hwtimer_drv[sizeof(hwtimer_cfg) / sizeof(hwtimer_cfg[0])] = {0}; -void TIMR1_Handler(void) +static void swm_timer_init(struct rt_hwtimer_device *timer_device, rt_uint32_t state) { - TIMR_INTClr(TIMR1); - rt_device_hwtimer_isr(&hwtimer1.parent); + struct swm_hwtimer_cfg *cfg = RT_NULL; + RT_ASSERT(timer_device != RT_NULL); - if (HWTIMER_MODE_ONESHOT == hwtimer1.parent.mode) + if (state) { - TIMR_Stop(hwtimer1.hwtimer_periph); - } + cfg = timer_device->parent.user_data; + TIMR_Init(cfg->TIMRx, TIMR_MODE_TIMER, SystemCoreClock, 1); + timer_device->freq = SystemCoreClock; + } } -#endif //BSP_USING_HWTIMER1 - -#ifdef BSP_USING_HWTIMER2 -static struct swm320_hwtimer_dev hwtimer2; -void TIMR2_Handler(void) +static rt_err_t swm_timer_start(rt_hwtimer_t *timer_device, rt_uint32_t cnt, rt_hwtimer_mode_t opmode) { - TIMR_INTClr(TIMR2); - rt_device_hwtimer_isr(&hwtimer2.parent); - - if (HWTIMER_MODE_ONESHOT == hwtimer2.parent.mode) - { - TIMR_Stop(hwtimer2.hwtimer_periph); - } -} -#endif //BSP_USING_HWTIMER2 - -#ifdef BSP_USING_HWTIMER3 -static struct swm320_hwtimer_dev hwtimer3; + rt_err_t result = RT_EOK; + struct swm_hwtimer_cfg *cfg = RT_NULL; + RT_ASSERT(timer_device != RT_NULL); + cfg = timer_device->parent.user_data; -void TIMR3_Handler(void) -{ - TIMR_INTClr(TIMR3); - rt_device_hwtimer_isr(&hwtimer3.parent); - - if (HWTIMER_MODE_ONESHOT == hwtimer3.parent.mode) + if (opmode == HWTIMER_MODE_ONESHOT) { - TIMR_Stop(hwtimer3.hwtimer_periph); + /* set timer to single mode */ + timer_device->mode = HWTIMER_MODE_ONESHOT; } -} -#endif //BSP_USING_HWTIMER3 - -#ifdef BSP_USING_HWTIMER4 -static struct swm320_hwtimer_dev hwtimer4; - -void TIMR4_Handler(void) -{ - TIMR_INTClr(TIMR4); - rt_device_hwtimer_isr(&hwtimer4.parent); - - if (HWTIMER_MODE_ONESHOT == hwtimer4.parent.mode) + else { - TIMR_Stop(hwtimer4.hwtimer_periph); + timer_device->mode = HWTIMER_MODE_PERIOD; } -} -#endif //BSP_USING_HWTIMER4 + TIMR_SetPeriod(cfg->TIMRx, cnt); + TIMR_Stop(cfg->TIMRx); + TIMR_Start(cfg->TIMRx); -#ifdef BSP_USING_HWTIMER5 -static struct swm320_hwtimer_dev hwtimer5; + return result; +} -void TIMR5_Handler(void) +static void swm_timer_stop(rt_hwtimer_t *timer_device) { - TIMR_INTClr(TIMR5); - rt_device_hwtimer_isr(&hwtimer5.parent); - - if (HWTIMER_MODE_ONESHOT == hwtimer5.parent.mode) - { - TIMR_Stop(hwtimer5.hwtimer_periph); - } + struct swm_hwtimer_cfg *cfg = RT_NULL; + RT_ASSERT(timer_device != RT_NULL); + cfg = timer_device->parent.user_data; + + /* stop timer */ + TIMR_Stop(cfg->TIMRx); } -#endif //BSP_USING_HWTIMER5 -static struct rt_hwtimer_info swm320_hwtimer_info = +static rt_uint32_t swm_timer_count_get(rt_hwtimer_t *timer_device) { - 120000000, /*时钟源为系统时钟*/ - 120000000, - 4294967295, /*32位计数器，2的32次方*/ - HWTIMER_CNTMODE_DW -}; + struct swm_hwtimer_cfg *cfg = RT_NULL; + RT_ASSERT(timer_device != RT_NULL); + cfg = timer_device->parent.user_data; -static void swm320_hwtimer_init(rt_hwtimer_t *timer, rt_uint32_t state) + return TIMR_GetCurValue(cfg->TIMRx); +} + +static rt_err_t swm_timer_ctrl(rt_hwtimer_t *timer_device, rt_uint32_t cmd, void *args) { - struct swm320_hwtimer_dev *hwtimer = SWM320_HWTIMER_DEVICE(timer->parent.user_data); + struct swm_hwtimer_cfg *cfg = RT_NULL; + rt_err_t result = RT_EOK; + RT_ASSERT(timer_device != RT_NULL); + RT_ASSERT(args != RT_NULL); + cfg = timer_device->parent.user_data; - RT_ASSERT(hwtimer != RT_NULL); + switch (cmd) + { + case HWTIMER_CTRL_FREQ_SET: + { + rt_uint32_t freq; + freq = *(rt_uint32_t *)args; - if (1 == state) + TIMR_Init(cfg->TIMRx, TIMR_MODE_TIMER, SystemCoreClock / freq, 1); + } + break; + default: { - TIMR_Init(hwtimer->hwtimer_periph, - TIMR_MODE_TIMER, - SystemCoreClock, - 1); + result = -RT_ENOSYS; } - hwtimer->parent.freq = SystemCoreClock; - swm320_hwtimer_info.maxfreq = SystemCoreClock; - swm320_hwtimer_info.minfreq = SystemCoreClock; + break; + } + + return result; } -static rt_err_t swm320_hwtimer_start(rt_hwtimer_t *timer, - rt_uint32_t cnt, - rt_hwtimer_mode_t mode) -{ - struct swm320_hwtimer_dev *hwtimer = SWM320_HWTIMER_DEVICE(timer->parent.user_data); +static const struct rt_hwtimer_info _info = TIM_DEV_INFO_CONFIG; - RT_ASSERT(hwtimer != RT_NULL); +static struct rt_hwtimer_ops swm_hwtimer_ops = + { + .init = swm_timer_init, + .start = swm_timer_start, + .stop = swm_timer_stop, + .count_get = swm_timer_count_get, + .control = swm_timer_ctrl}; - TIMR_SetPeriod(hwtimer->hwtimer_periph, cnt); - TIMR_Start(hwtimer->hwtimer_periph); +void rt_hw_hwtimer_isr(rt_hwtimer_t *timer_device) +{ + struct swm_hwtimer_cfg *cfg = RT_NULL; + RT_ASSERT(timer_device != RT_NULL); + cfg = timer_device->parent.user_data; - return RT_EOK; + TIMR_INTClr(cfg->TIMRx); + rt_device_hwtimer_isr(timer_device); } - -static void swm320_hwtimer_stop(rt_hwtimer_t *timer) +#ifdef BSP_USING_TIM0 +void TIMR0_Handler(void) { - struct swm320_hwtimer_dev *hwtimer = SWM320_HWTIMER_DEVICE(timer->parent.user_data); - - RT_ASSERT(hwtimer != RT_NULL); - - TIMR_Stop(hwtimer->hwtimer_periph); + /* enter interrupt */ + rt_interrupt_enter(); + rt_hw_hwtimer_isr(&(hwtimer_drv[TIM0_INDEX].time_device)); + /* leave interrupt */ + rt_interrupt_leave(); } +#endif //BSP_USING_TIM0 -static rt_uint32_t swm320_hwtimer_count_get(rt_hwtimer_t *timer) +#ifdef BSP_USING_TIM1 +void TIMR1_Handler(void) { - struct swm320_hwtimer_dev *hwtimer = SWM320_HWTIMER_DEVICE(timer->parent.user_data); - uint32_t hwtimer_count = 0; + /* enter interrupt */ + rt_interrupt_enter(); + rt_hw_hwtimer_isr(&(hwtimer_drv[TIM1_INDEX].time_device)); + /* leave interrupt */ + rt_interrupt_leave(); +} +#endif //BSP_USING_TIM1 - RT_ASSERT(hwtimer != RT_NULL); +#ifdef BSP_USING_TIM2 +void TIMR2_Handler(void) +{ + /* enter interrupt */ + rt_interrupt_enter(); + rt_hw_hwtimer_isr(&(hwtimer_drv[TIM2_INDEX].time_device)); + /* leave interrupt */ + rt_interrupt_leave(); +} +#endif //BSP_USING_TIM2 - hwtimer_count = TIMR_GetCurValue(hwtimer->hwtimer_periph); +#ifdef BSP_USING_TIM3 +void TIMR3_Handler(void) +{ + /* enter interrupt */ + rt_interrupt_enter(); + rt_hw_hwtimer_isr(&(hwtimer_drv[TIM3_INDEX].time_device)); + /* leave interrupt */ + rt_interrupt_leave(); +} +#endif //BSP_USING_TIM3 - return hwtimer_count; +#ifdef BSP_USING_TIM4 +void TIMR4_Handler(void) +{ + /* enter interrupt */ + rt_interrupt_enter(); + rt_hw_hwtimer_isr(&(hwtimer_drv[TIM4_INDEX].time_device)); + /* leave interrupt */ + rt_interrupt_leave(); } +#endif //BSP_USING_TIM4 -static rt_err_t swm320_hwtimer_control(rt_hwtimer_t *timer, - rt_uint32_t cmd, - void *args) +#ifdef BSP_USING_TIM5 +void TIMR5_Handler(void) { - rt_err_t ret = RT_EOK; - rt_uint32_t freq = 0; - struct swm320_hwtimer_dev *hwtimer = SWM320_HWTIMER_DEVICE(timer->parent.user_data); + /* enter interrupt */ + rt_interrupt_enter(); + rt_hw_hwtimer_isr(&(hwtimer_drv[TIM5_INDEX].time_device)); + /* leave interrupt */ + rt_interrupt_leave(); +} +#endif //BSP_USING_TIM5 - RT_ASSERT(hwtimer != RT_NULL); +static int rt_hw_hwtimer_init(void) +{ + int i = 0; + int result = RT_EOK; - switch (cmd) + for (i = 0; i < sizeof(hwtimer_cfg) / sizeof(hwtimer_cfg[0]); i++) { - case HWTIMER_CTRL_FREQ_SET: - freq = *(rt_uint32_t*)args; - if (freq != SystemCoreClock) + hwtimer_drv[i].cfg = &hwtimer_cfg[i]; + hwtimer_drv[i].time_device.info = &_info; + hwtimer_drv[i].time_device.ops = &swm_hwtimer_ops; + if (rt_device_hwtimer_register(&hwtimer_drv[i].time_device, hwtimer_drv[i].cfg->name, hwtimer_drv[i].cfg) == RT_EOK) { - ret = RT_EINVAL; + ; + } + else + { + result = -RT_ERROR; } - break; - case HWTIMER_CTRL_STOP: - TIMR_Stop(hwtimer->hwtimer_periph); - break; - default: - ret = RT_EINVAL; - break; } - return ret; -} - -static struct rt_hwtimer_ops swm320_hwtimer_ops = -{ - swm320_hwtimer_init, - swm320_hwtimer_start, - swm320_hwtimer_stop, - swm320_hwtimer_count_get, - swm320_hwtimer_control -}; - -int rt_hw_hwtimer_init(void) -{ - rt_err_t ret = RT_EOK; - -#ifdef BSP_USING_HWTIMER0 - hwtimer0.hwtimer_periph = TIMR0; - hwtimer0.parent.info = &swm320_hwtimer_info; - hwtimer0.parent.ops = &swm320_hwtimer_ops; - ret = rt_device_hwtimer_register(&hwtimer0.parent, "timer0", &hwtimer0); -#endif //BSP_USING_HWTIMER0 - -#ifdef BSP_USING_HWTIMER1 - hwtimer1.hwtimer_periph = TIMR1; - hwtimer1.parent.info = &swm320_hwtimer_info; - hwtimer1.parent.ops = &swm320_hwtimer_ops; - ret = rt_device_hwtimer_register(&hwtimer1.parent, "timer1", &hwtimer1); -#endif //BSP_USING_HWTIMER1 - -#ifdef BSP_USING_HWTIMER2 - hwtimer2.hwtimer_periph = TIMR2; - hwtimer2.parent.info = &swm320_hwtimer_info; - hwtimer2.parent.ops = &swm320_hwtimer_ops; - ret = rt_device_hwtimer_register(&hwtimer2.parent, "timer2", &hwtimer2); -#endif //BSP_USING_HWTIMER2 - -#ifdef BSP_USING_HWTIMER3 - hwtimer3.hwtimer_periph = TIMR3; - hwtimer3.parent.info = &swm320_hwtimer_info; - hwtimer3.parent.ops = &swm320_hwtimer_ops; - ret = rt_device_hwtimer_register(&hwtimer3.parent, "timer3", &hwtimer3); -#endif //BSP_USING_HWTIMER3 - -#ifdef BSP_USING_HWTIMER4 - hwtimer4.hwtimer_periph = TIMR4; - hwtimer4.parent.info = &swm320_hwtimer_info; - hwtimer4.parent.ops = &swm320_hwtimer_ops; - ret = rt_device_hwtimer_register(&hwtimer4.parent, "timer4", &hwtimer4); -#endif //BSP_USING_HWTIMER4 - -#ifdef BSP_USING_HWTIMER5 - hwtimer5.hwtimer_periph = TIMR5; - hwtimer5.parent.info = &swm320_hwtimer_info; - hwtimer5.parent.ops = &swm320_hwtimer_ops; - ret = rt_device_hwtimer_register(&hwtimer5.parent, "timer5", &hwtimer5); -#endif //BSP_USING_HWTIMER5 - - return ret; + return result; } INIT_BOARD_EXPORT(rt_hw_hwtimer_init); + +#endif /* BSP_USING_TIM */ +#endif /* RT_USING_HWTIMER */ diff --git a/bsp/swm320-lq100/drivers/drv_hwtimer.h b/bsp/swm320-lq100/drivers/drv_hwtimer.h index 6ec07dedde..05d586ac44 100644 --- a/bsp/swm320-lq100/drivers/drv_hwtimer.h +++ b/bsp/swm320-lq100/drivers/drv_hwtimer.h @@ -6,11 +6,96 @@ * Change Logs: * Date Author Notes * 2018-12-10 Zohar_Lee first version + * 2020-07-10 lik rewrite */ -#ifndef DRV_HWTIMER_H__ -#define DRV_HWTIMER_H__ +#ifndef __DRV_HWTIMER_H__ +#define __DRV_HWTIMER_H__ + +#include "board.h" + +struct swm_hwtimer_cfg +{ + char *name; + TIMR_TypeDef *TIMRx; +}; + +struct swm_hwtimer +{ + struct swm_hwtimer_cfg *cfg; + rt_hwtimer_t time_device; +}; + +#ifndef TIM_DEV_INFO_CONFIG +#define TIM_DEV_INFO_CONFIG \ + { \ + .maxfreq = 120000000, \ + .minfreq = 120000000, \ + .maxcnt = 0xFFFFFFFF, \ + .cntmode = HWTIMER_CNTMODE_DW, \ + } +#endif /* TIM_DEV_INFO_CONFIG */ + +#ifdef BSP_USING_TIM0 +#ifndef TIM0_CFG +#define TIM0_CFG \ + { \ + .name = "timer0", \ + .TIMRx = TIMR0, \ + } +#endif /* TIM0_CFG */ +#endif /* BSP_USING_TIM0 */ + +#ifdef BSP_USING_TIM1 +#ifndef TIM1_CFG +#define TIM1_CFG \ + { \ + .name = "timer1", \ + .TIMRx = TIMR1, \ + } +#endif /* TIM1_CFG */ +#endif /* BSP_USING_TIM1 */ + +#ifdef BSP_USING_TIM2 +#ifndef TIM2_CFG +#define TIM2_CFG \ + { \ + .name = "timer2", \ + .TIMRx = TIMR2, \ + } +#endif /* TIM2_CFG */ +#endif /* BSP_USING_TIM2 */ + +#ifdef BSP_USING_TIM3 +#ifndef TIM3_CFG +#define TIM3_CFG \ + { \ + .name = "timer3", \ + .TIMRx = TIMR3, \ + } +#endif /* TIM3_CFG */ +#endif /* BSP_USING_TIM3 */ + +#ifdef BSP_USING_TIM4 +#ifndef TIM4_CFG +#define TIM4_CFG \ + { \ + .name = "timer4", \ + .TIMRx = TIMR4, \ + } +#endif /* TIM4_CFG */ +#endif /* BSP_USING_TIM4 */ + +#ifdef BSP_USING_TIM5 +#ifndef TIM5_CFG +#define TIM5_CFG \ + { \ + .name = "timer5", \ + .TIMRx = TIMR5, \ + } +#endif /* TIM5_CFG */ +#endif /* BSP_USING_TIM5 */ int rt_hw_hwtimer_init(void); -#endif +#endif /* __DRV_HWTIMER_H__ */ diff --git a/bsp/swm320-lq100/drivers/drv_i2c.c b/bsp/swm320-lq100/drivers/drv_i2c.c deleted file mode 100644 index 322d735a68..0000000000 --- a/bsp/swm320-lq100/drivers/drv_i2c.c +++ /dev/null @@ -1,70 +0,0 @@ -/* - * Copyright (c) 2006-2018, Synwit Technology Co.,Ltd. - * - * SPDX-License-Identifier: Apache-2.0 - * - * Change Logs: - * Date Author Notes - * 2018-05-31 ZYH first version - * 2018-12-10 Zohar_Lee format file - */ - -#include <rthw.h> -#include <rtthread.h> -#include <rtdevice.h> -#include <board.h> - -static void drv_set_sda(void *data, rt_int32_t state) -{ - rt_pin_mode(BSP_I2C_SDA, PIN_MODE_OUTPUT); - rt_pin_write(BSP_I2C_SDA, state); -} - -static void drv_set_scl(void *data, rt_int32_t state) -{ - rt_pin_mode(BSP_I2C_SCL, PIN_MODE_OUTPUT); - rt_pin_write(BSP_I2C_SCL, state); -} - -static rt_int32_t drv_get_sda(void *data) -{ - rt_pin_mode(BSP_I2C_SDA, PIN_MODE_INPUT_PULLUP); - return rt_pin_read(BSP_I2C_SDA); -} - -static rt_int32_t drv_get_scl(void *data) -{ - rt_pin_mode(BSP_I2C_SCL, PIN_MODE_INPUT_PULLUP); - return rt_pin_read(BSP_I2C_SCL); -} - -static void drv_udelay(rt_uint32_t us) -{ - int i = (SystemCoreClock / 4000000 * us); - while (i) - { - i--; - } -} - -static const struct rt_i2c_bit_ops drv_bit_ops = -{ - RT_NULL, - drv_set_sda, - drv_set_scl, - drv_get_sda, - drv_get_scl, - drv_udelay, - 1, - 100 -}; - -int rt_hw_i2c_init(void) -{ - static struct rt_i2c_bus_device i2c2_bus; - rt_memset((void *)&i2c2_bus, 0, sizeof(struct rt_i2c_bus_device)); - i2c2_bus.priv = (void *)&drv_bit_ops; - rt_i2c_bit_add_bus(&i2c2_bus, BSP_I2C_BUS_NAME); - return RT_EOK; -} -INIT_DEVICE_EXPORT(rt_hw_i2c_init); diff --git a/bsp/swm320-lq100/drivers/drv_i2c.h b/bsp/swm320-lq100/drivers/drv_i2c.h deleted file mode 100644 index 01cbcd7669..0000000000 --- a/bsp/swm320-lq100/drivers/drv_i2c.h +++ /dev/null @@ -1,16 +0,0 @@ -/* - * Copyright (c) 2006-2018, Synwit Technology Co.,Ltd. - * - * SPDX-License-Identifier: Apache-2.0 - * - * Change Logs: - * Date Author Notes - * 2018-12-10 Zohar_Lee first version - */ - -#ifndef DRV_I2C_H__ -#define DRV_I2C_H__ - -int rt_hw_i2c_init(void); - -#endif diff --git a/bsp/swm320-lq100/drivers/drv_iwg.c b/bsp/swm320-lq100/drivers/drv_iwg.c deleted file mode 100644 index 55af428641..0000000000 --- a/bsp/swm320-lq100/drivers/drv_iwg.c +++ /dev/null @@ -1,77 +0,0 @@ -/* - * Copyright (c) 2006-2018, Synwit Technology Co.,Ltd. - * - * SPDX-License-Identifier: Apache-2.0 - * - * Change Logs: - * Date Author Notes - * 2018-12-10 Zohar_Lee first version - */ - -#include <board.h> -#include "rtthread.h" -#include "rtdevice.h" - -static rt_err_t swm320_wdt_init(rt_watchdog_t *wdt) -{ - WDT_Init(WDT, SystemCoreClock / 2, WDT_MODE_INTERRUPT); - - return RT_EOK; -} - -static rt_err_t swm320_wdt_control(rt_watchdog_t *wdt, int cmd, void *arg) -{ - switch (cmd) - { - case RT_DEVICE_CTRL_WDT_GET_TIMEOUT: - *(uint32_t *)arg = WDT->LOAD; - break; - case RT_DEVICE_CTRL_WDT_SET_TIMEOUT: - WDT_Stop(WDT); - WDT->LOAD = SystemCoreClock / 1000 * (*(uint32_t *)arg); - break; - case RT_DEVICE_CTRL_WDT_GET_TIMELEFT: - *(uint32_t *)arg = WDT_GetValue(WDT); - break; - case RT_DEVICE_CTRL_WDT_KEEPALIVE: - WDT_Feed(WDT); - break; - case RT_DEVICE_CTRL_WDT_START: - WDT_Start(WDT); - break; - case RT_DEVICE_CTRL_WDT_STOP: - WDT_Stop(WDT); - break; - default: - break; - } - - return RT_EOK; -} - -rt_watchdog_t swm320_wdt; -const static struct rt_watchdog_ops swm320_wdt_ops = -{ - swm320_wdt_init, - swm320_wdt_control -}; - -int rt_hw_wdt_init(void) -{ - rt_err_t result = RT_EOK; - - swm320_wdt.ops = &swm320_wdt_ops; - - result = rt_hw_watchdog_register(&swm320_wdt, - "wdt", - RT_DEVICE_FLAG_RDWR, - WDT); - - return result; -} -INIT_BOARD_EXPORT(rt_hw_wdt_init); - -void WDT_Handler(void) -{ - WDT_INTClr(WDT); -} diff --git a/bsp/swm320-lq100/drivers/drv_iwg.h b/bsp/swm320-lq100/drivers/drv_iwg.h deleted file mode 100644 index f4e85df8a7..0000000000 --- a/bsp/swm320-lq100/drivers/drv_iwg.h +++ /dev/null @@ -1,16 +0,0 @@ -/* - * Copyright (c) 2006-2018, Synwit Technology Co.,Ltd. - * - * SPDX-License-Identifier: Apache-2.0 - * - * Change Logs: - * Date Author Notes - * 2018-12-10 Zohar_Lee first version - */ - -#ifndef DRV_IWG_H__ -#define DRV_IWG_H__ - -int rt_hw_wdt_init(void); - -#endif diff --git a/bsp/swm320-lq100/drivers/drv_log.h b/bsp/swm320-lq100/drivers/drv_log.h new file mode 100644 index 0000000000..52e560cc12 --- /dev/null +++ b/bsp/swm320-lq100/drivers/drv_log.h @@ -0,0 +1,27 @@ +/* + * Copyright (c) 2006-2021, RT-Thread Development Team + * + * SPDX-License-Identifier: Apache-2.0 + * + * Change Logs: + * Date Author Notes + * 2018-11-15 SummerGift first version + */ + +/* + * NOTE: DO NOT include this file on the header file. + */ + +#ifndef LOG_TAG +#define DBG_TAG "drv" +#else +#define DBG_TAG LOG_TAG +#endif /* LOG_TAG */ + +#ifdef DRV_DEBUG +#define DBG_LVL DBG_LOG +#else +#define DBG_LVL DBG_INFO +#endif /* DRV_DEBUG */ + +#include <rtdbg.h> diff --git a/bsp/swm320-lq100/drivers/drv_nor_flash.c b/bsp/swm320-lq100/drivers/drv_nor_flash.c index e229d3b7ce..6940cd54d0 100644 --- a/bsp/swm320-lq100/drivers/drv_nor_flash.c +++ b/bsp/swm320-lq100/drivers/drv_nor_flash.c @@ -7,67 +7,44 @@ * Date Author Notes * 2018-05-31 ZYH first version * 2018-12-10 Zohar_Lee format file + * 2020-07-10 lik rewrite */ -#include <rtdevice.h> -#include <stdio.h> -#include <string.h> -#include <stdlib.h> -#include <SWM320.h> +#include "drv_nor_flash.h" -#define BLOCK_SIZE (64 * 1024) -#define FLASH_SIZE (BSP_NOR_FLASH_SIZE) -#define BLOCK_COUNTER (FLASH_SIZE / BLOCK_SIZE) +#ifdef BSP_USING_NOR_FLASH + +#define DRV_DEBUG +#define LOG_TAG "drv.norflash" +#include <drv_log.h> static struct rt_mutex flash_lock; /* RT-Thread MTD device interface */ -static long swm320_read_id(struct rt_mtd_nor_device *device) +static long swm_norflash_read_id(struct rt_mtd_nor_device *device) { return 0xdeadbeef; } -static rt_size_t swm320_read(struct rt_mtd_nor_device *device, - rt_off_t position, - rt_uint8_t *data, - rt_size_t size) +static rt_size_t swm_norflash_read(struct rt_mtd_nor_device *device, + rt_off_t position, + rt_uint8_t *data, + rt_uint32_t size) { - int ret = rt_mutex_take(&flash_lock, RT_WAITING_FOREVER); - if (ret == -RT_ETIMEOUT) - { - rt_kprintf("Take mutex time out.\n"); - return ret; - } - else if (ret == -RT_ERROR) - { - rt_kprintf("Take mutex error.\n"); - return ret; - } - + rt_mutex_take(&flash_lock, RT_WAITING_FOREVER); memcpy(data, ((const void *)(NORFLM_BASE + position)), size); rt_mutex_release(&flash_lock); return size; } -static rt_size_t swm320_write(struct rt_mtd_nor_device *device, - rt_off_t position, - const rt_uint8_t *data, - rt_size_t size) +static rt_size_t swm_norflash_write(struct rt_mtd_nor_device *device, + rt_off_t position, + const rt_uint8_t *data, + rt_uint32_t size) { rt_size_t i; const rt_uint16_t *hwdata = (const rt_uint16_t *)data; - int ret = rt_mutex_take(&flash_lock, RT_WAITING_FOREVER); - if (ret == -RT_ETIMEOUT) - { - rt_kprintf("Take mutex time out.\n"); - return ret; - } - else if (ret == -RT_ERROR) - { - rt_kprintf("Take mutex error.\n"); - return ret; - } - + rt_mutex_take(&flash_lock, RT_WAITING_FOREVER); for (i = 0; i < size / 2; i++) { NORFL_Write(position, hwdata[i]); @@ -77,45 +54,35 @@ static rt_size_t swm320_write(struct rt_mtd_nor_device *device, return size; } -static rt_err_t swm320_erase_block(struct rt_mtd_nor_device *device, - rt_off_t offset, - rt_uint32_t length) +static rt_err_t swm_norflash_erase_block(struct rt_mtd_nor_device *device, + rt_off_t offset, + rt_uint32_t length) { - rt_err_t ret = rt_mutex_take(&flash_lock, RT_WAITING_FOREVER); - if (ret == -RT_ETIMEOUT) - { - rt_kprintf("Take mutex time out.\n"); - return ret; - } - else if (ret == -RT_ERROR) - { - rt_kprintf("Take mutex error.\n"); - return ret; - } - + rt_mutex_take(&flash_lock, RT_WAITING_FOREVER); NORFL_SectorErase(offset); rt_mutex_release(&flash_lock); return RT_EOK; } const static struct rt_mtd_nor_driver_ops mtd_ops = -{ - swm320_read_id, - swm320_read, - swm320_write, - swm320_erase_block -}; + { + swm_norflash_read_id, + swm_norflash_read, + swm_norflash_write, + swm_norflash_erase_block}; -static rt_err_t hw_init() +static struct rt_mtd_nor_device mtd; +int rt_hw_norflash_init(void) { NORFL_InitStructure NORFL_InitStruct; + PORT->PORTP_SEL0 = 0xAAAAAAAA; //PP0-23 => ADDR0-23 PORT->PORTP_SEL1 = 0xAAAA; PORT->PORTM_SEL0 = 0xAAAAAAAA; //PM0-15 => DATA15-0 PORT->PORTM_INEN = 0xFFFF; - PORT->PORTM_SEL1 = 0x2AA; //PM16 => OEN, PM17 => WEN, PM18 => NORFL_CSN,PM19 => SDRAM_CSN, PM20 => SRAM_CSN, PM21 => SDRAM_CKE + PORT->PORTM_SEL1 = 0xAAA; //PM16 => OEN、PM17 => WEN、PM18 => NORFL_CSN、PM19 => SDRAM_CSN、PM20 => SRAM_CSN、PM21 => SDRAM_CKE NORFL_InitStruct.DataWidth = 16; NORFL_InitStruct.WELowPulseTime = 5; @@ -123,12 +90,7 @@ static rt_err_t hw_init() NORFL_InitStruct.OperFinishIEn = 0; NORFL_InitStruct.OperTimeoutIEn = 0; NORFL_Init(&NORFL_InitStruct); - return RT_EOK; -} -static struct rt_mtd_nor_device mtd; -int rt_hw_norflash_init(void) -{ - hw_init(); + /* set page size and block size */ mtd.block_size = BLOCK_SIZE; /* 64kByte */ mtd.ops = &mtd_ops; @@ -148,11 +110,4 @@ int rt_hw_norflash_init(void) } INIT_DEVICE_EXPORT(rt_hw_norflash_init); -#ifdef RT_USING_FINSH -#include <finsh.h> -void nor_erase(void) -{ - NORFL_ChipErase(); -} -MSH_CMD_EXPORT(nor_erase, erase all block in SPI flash); -#endif +#endif /* BSP_USING_NOR_FLASH */ diff --git a/bsp/swm320-lq100/drivers/drv_nor_flash.h b/bsp/swm320-lq100/drivers/drv_nor_flash.h index 86260be87e..170917c44d 100644 --- a/bsp/swm320-lq100/drivers/drv_nor_flash.h +++ b/bsp/swm320-lq100/drivers/drv_nor_flash.h @@ -6,11 +6,18 @@ * Change Logs: * Date Author Notes * 2018-12-10 Zohar_Lee first version + * 2020-07-10 lik rewrite */ #ifndef DRV_NOR_FLASH_H__ #define DRV_NOR_FLASH_H__ +#include "board.h" + +#define BLOCK_SIZE (64 * 1024) +#define FLASH_SIZE (BSP_NOR_FLASH_SIZE) +#define BLOCK_COUNTER (FLASH_SIZE / BLOCK_SIZE) + int rt_hw_norflash_init(void); #endif diff --git a/bsp/swm320-lq100/drivers/drv_pwm.c b/bsp/swm320-lq100/drivers/drv_pwm.c index 3d6f9203ef..23b2aeca0f 100644 --- a/bsp/swm320-lq100/drivers/drv_pwm.c +++ b/bsp/swm320-lq100/drivers/drv_pwm.c @@ -6,185 +6,228 @@ * Change Logs: * Date Author Notes * 2018-12-10 Zohar_Lee first version + * 2020-07-10 lik format file */ -#include <rthw.h> -#include <rtthread.h> -#include <rtdevice.h> -#include <board.h> +#include "drv_pwm.h" -#define SWM320_PWM_DEVICE(pwm) (struct swm320_pwm_dev *)(pwm) +#ifdef RT_USING_PWM +#ifdef BSP_USING_PWM -#define SWM320_PWM_TIMER_SET(time) ((time) / 1000.0 * 120) +//#define DRV_DEBUG +#define LOG_TAG "drv.pwm" +#include <drv_log.h> -struct swm320_pwm_dev -{ - struct rt_device_pwm parent; - PWM_TypeDef *pwm_periph; +#define MIN_PERIOD 2 +#define MIN_PULSE 1 + +static struct swm_pwm_cfg pwm_cfg[] = + { +#ifdef BSP_USING_PWM0 + PWM0_CFG, +#endif +#ifdef BSP_USING_PWM1 + PWM1_CFG, +#endif +#ifdef BSP_USING_PWM2 + PWM2_CFG, +#endif +#ifdef BSP_USING_PWM3 + PWM3_CFG, +#endif +#ifdef BSP_USING_PWM4 + PWM4_CFG, +#endif +#ifdef BSP_USING_PWM5 + PWM5_CFG, +#endif }; -static rt_err_t swm320_pwm_enable(void *user_data, - struct rt_pwm_configuration *cfg, - rt_bool_t enable) +static struct swm_pwm pwm_drv[sizeof(pwm_cfg) / sizeof(pwm_cfg[0])] = {0}; + +static rt_err_t swm_pwm_control(struct rt_device_pwm *pwm_device, int cmd, void *arg); +static struct rt_pwm_ops pwm_ops = + { + swm_pwm_control}; + +static rt_err_t swm_pwm_enable(struct rt_device_pwm *pwm_device, struct rt_pwm_configuration *configuration, rt_bool_t enable) { - rt_err_t ret = RT_EOK; + struct swm_pwm_cfg *cfg = RT_NULL; + RT_ASSERT(pwm_device != RT_NULL); + cfg = pwm_device->parent.user_data; - if (RT_TRUE == enable) + if (!enable) { - if (2 == cfg->channel) + if (PWM_CH_A == configuration->channel) { - PWM_Start((PWM_TypeDef *)user_data, 1, 1); + PWM_Stop(cfg->PWMx, 1, 0); } - if (1 == cfg->channel) + if (PWM_CH_B == configuration->channel) { - PWM_Start((PWM_TypeDef *)user_data, 0, 1); - } - if (0 == cfg->channel) - { - PWM_Start((PWM_TypeDef *)user_data, 1, 0); - } - if (3 == cfg->channel) - { - PWM_Start((PWM_TypeDef *)user_data, 0, 0); + PWM_Stop(cfg->PWMx, 0, 1); } } - else if (RT_FALSE == enable) + else { - if (2 == cfg->channel) + if (PWM_CH_A == configuration->channel) { - PWM_Stop((PWM_TypeDef *)user_data, 1, 1); + PWM_Start(cfg->PWMx, 1, 0); } - if (1 == cfg->channel) + if (PWM_CH_B == configuration->channel) { - PWM_Stop((PWM_TypeDef *)user_data, 0, 1); - } - if (0 == cfg->channel) - { - PWM_Stop((PWM_TypeDef *)user_data, 1, 0); - } - if (3 == cfg->channel) - { - PWM_Stop((PWM_TypeDef *)user_data, 0, 0); + PWM_Start(cfg->PWMx, 0, 1); } } - else + + return RT_EOK; +} + +static rt_err_t swm_pwm_get(struct rt_device_pwm *pwm_device, struct rt_pwm_configuration *configuration) +{ + rt_uint64_t tim_clock; + tim_clock = SystemCoreClock / 8; + + struct swm_pwm_cfg *cfg = RT_NULL; + RT_ASSERT(pwm_device != RT_NULL); + cfg = pwm_device->parent.user_data; + + /* Convert nanosecond to frequency and duty cycle. 1s = 1 * 1000 * 1000 * 1000 ns */ + tim_clock /= 1000000UL; + configuration->period = PWM_GetCycle(cfg->PWMx, configuration->channel) * 1000UL / tim_clock; + configuration->pulse = PWM_GetHDuty(cfg->PWMx, configuration->channel) * 1000UL / tim_clock; + + return RT_EOK; +} + +static rt_err_t swm_pwm_set(struct rt_device_pwm *pwm_device, struct rt_pwm_configuration *configuration) +{ + rt_uint32_t period, pulse; + rt_uint64_t tim_clock; + tim_clock = SystemCoreClock / 8; + + struct swm_pwm_cfg *cfg = RT_NULL; + RT_ASSERT(pwm_device != RT_NULL); + cfg = pwm_device->parent.user_data; + + /* Convert nanosecond to frequency and duty cycle. 1s = 1 * 1000 * 1000 * 1000 ns */ + /* when SystemCoreClock = 120MHz, configuration->period max 4.369ms */ + /* when SystemCoreClock = 20MHz, configuration->period max 26.214ms */ + tim_clock /= 1000000UL; + period = (unsigned long long)configuration->period * tim_clock / 1000ULL; + pulse = (unsigned long long)configuration->pulse * tim_clock / 1000ULL; + if (period < MIN_PERIOD) { - ret = RT_ERROR; + period = MIN_PERIOD; } + if (pulse < MIN_PULSE) + { + pulse = MIN_PULSE; + } + PWM_SetCycle(cfg->PWMx, configuration->channel, period); + PWM_SetHDuty(cfg->PWMx, configuration->channel, pulse); - return ret; + return RT_EOK; } -static rt_err_t swm320_pwm_control(struct rt_device_pwm *device, - int cmd, - void *arg) +static rt_err_t swm_pwm_control(struct rt_device_pwm *pwm_device, int cmd, void *arg) { - rt_err_t ret = RT_EOK; - struct swm320_pwm_dev *pwm = SWM320_PWM_DEVICE(device->parent.user_data); - struct rt_pwm_configuration *cfg = (struct rt_pwm_configuration *)arg; + RT_ASSERT(pwm_device != RT_NULL); - RT_ASSERT(pwm != RT_NULL); + struct rt_pwm_configuration *configuration = (struct rt_pwm_configuration *)arg; switch (cmd) { case PWM_CMD_ENABLE: - - ret = swm320_pwm_enable((void *)pwm->pwm_periph, cfg, RT_TRUE); - break; + return swm_pwm_enable(pwm_device, configuration, RT_TRUE); case PWM_CMD_DISABLE: - - ret = swm320_pwm_enable((void *)pwm->pwm_periph, cfg, RT_FALSE); - break; + return swm_pwm_enable(pwm_device, configuration, RT_FALSE); case PWM_CMD_SET: - PWM_SetHDuty(pwm->pwm_periph, - cfg->channel, - SWM320_PWM_TIMER_SET(cfg->pulse)); - PWM_SetCycle(pwm->pwm_periph, - cfg->channel, - SWM320_PWM_TIMER_SET(cfg->period)); - break; + return swm_pwm_set(pwm_device, configuration); case PWM_CMD_GET: - cfg->pulse = PWM_GetHDuty(pwm->pwm_periph, cfg->channel); - break; + return swm_pwm_get(pwm_device, configuration); default: - break; + return RT_EINVAL; } - - return ret; } -const static struct rt_pwm_ops swm320_pwm_ops = -{ - swm320_pwm_control -}; - int rt_hw_pwm_init(void) { - rt_err_t ret = RT_EOK; - PWM_InitStructure PWM_initStruct; + int i = 0; + int result = RT_EOK; - PWM_initStruct.clk_div = PWM_CLKDIV_1; /* F_PWM = 120M/1 = 120M */ - PWM_initStruct.mode = PWM_MODE_INDEP; /* A路和B路独立输出 */ - PWM_initStruct.cycleA = SWM320_PWM_TIMER_SET(1000); - PWM_initStruct.hdutyA = SWM320_PWM_TIMER_SET(500); - PWM_initStruct.initLevelA = 1; - PWM_initStruct.cycleB = SWM320_PWM_TIMER_SET(1000); - PWM_initStruct.hdutyB = SWM320_PWM_TIMER_SET(250); - PWM_initStruct.initLevelB = 1; - PWM_initStruct.HEndAIEn = 0; - PWM_initStruct.NCycleAIEn = 0; - PWM_initStruct.HEndBIEn = 0; - PWM_initStruct.NCycleBIEn = 0; - -#ifdef BSP_USING_PWM0 - static struct swm320_pwm_dev pwm_dev0; - pwm_dev0.pwm_periph = PWM0; - PWM_Init(pwm_dev0.pwm_periph, &PWM_initStruct); - PORT_Init(PORTA, PIN4, FUNMUX0_PWM0A_OUT, 0); - PORT_Init(PORTA, PIN10, FUNMUX0_PWM0B_OUT, 0); - ret = rt_device_pwm_register(&pwm_dev0.parent, - "pwm0", - &swm320_pwm_ops, - &pwm_dev0); + for (i = 0; i < sizeof(pwm_cfg) / sizeof(pwm_cfg[0]); i++) + { + pwm_drv[i].cfg = &pwm_cfg[i]; + if (pwm_drv[i].cfg->PWMx == PWM0) + { +#ifdef BSP_USING_PWM0A + PORT_Init(PORTC, PIN2, FUNMUX0_PWM0A_OUT, 0); #endif - -#ifdef BSP_USING_PWM1 - static struct swm320_pwm_dev pwm_dev1; - pwm_dev1.pwm_periph = PWM1; - PWM_Init(pwm_dev1.pwm_periph, &PWM_initStruct); - PORT_Init(PORTA, PIN5, FUNMUX1_PWM1A_OUT, 0); - PORT_Init(PORTA, PIN9, FUNMUX1_PWM1B_OUT, 0); - ret = rt_device_pwm_register(&pwm_dev1.parent, - "pwm1", - &swm320_pwm_ops, - &pwm_dev1); +#ifdef BSP_USING_PWM0B + PORT_Init(PORTC, PIN4, FUNMUX0_PWM0B_OUT, 0); #endif - -#ifdef BSP_USING_PWM2 - static struct swm320_pwm_dev pwm_dev2; - pwm_dev2.pwm_periph = PWM2; - PWM_Init(pwm_dev2.pwm_periph, &PWM_initStruct); - PORT_Init(PORTP, PIN0, FUNMUX0_PWM2A_OUT, 0); - PORT_Init(PORTP, PIN2, FUNMUX0_PWM2B_OUT, 0); - ret = rt_device_pwm_register(&pwm_dev2.parent, - "pwm2", - &swm320_pwm_ops, - &pwm_dev2); + } + else if (pwm_drv[i].cfg->PWMx == PWM1) + { +#ifdef BSP_USING_PWM1A + PORT_Init(PORTC, PIN3, FUNMUX1_PWM1A_OUT, 0); #endif - -#ifdef BSP_USING_PWM3 - static struct swm320_pwm_dev pwm_dev3; - pwm_dev3.pwm_periph = PWM3; - PWM_Init(pwm_dev3.pwm_periph, &PWM_initStruct); - PORT_Init(PORTP, PIN1, FUNMUX1_PWM3A_OUT, 0); - PORT_Init(PORTP, PIN3, FUNMUX1_PWM3B_OUT, 0); - ret = rt_device_pwm_register(&pwm_dev3.parent, - "pwm3", - &swm320_pwm_ops, - &pwm_dev3); +#ifdef BSP_USING_PWM1B + PORT_Init(PORTC, PIN5, FUNMUX1_PWM1B_OUT, 0); +#endif + } + else if (pwm_drv[i].cfg->PWMx == PWM2) + { +#ifdef BSP_USING_PWM2A + PORT_Init(PORTN, PIN4, FUNMUX0_PWM2A_OUT, 0); #endif +#ifdef BSP_USING_PWM2B + PORT_Init(PORTN, PIN6, FUNMUX0_PWM2B_OUT, 0); +#endif + } + else if (pwm_drv[i].cfg->PWMx == PWM3) + { +#ifdef BSP_USING_PWM3A + PORT_Init(PORTN, PIN3, FUNMUX1_PWM3A_OUT, 0); +#endif +#ifdef BSP_USING_PWM3B + PORT_Init(PORTN, PIN5, FUNMUX1_PWM3B_OUT, 0); +#endif + } + else if (pwm_drv[i].cfg->PWMx == PWM4) + { +#ifdef BSP_USING_PWM4A + PORT_Init(PORTN, PIN8, FUNMUX0_PWM4A_OUT, 0); +#endif +#ifdef BSP_USING_PWM4B + PORT_Init(PORTN, PIN10, FUNMUX0_PWM4B_OUT, 0); +#endif + } + else if (pwm_drv[i].cfg->PWMx == PWM5) + { +#ifdef BSP_USING_PWM5A + PORT_Init(PORTN, PIN7, FUNMUX1_PWM5A_OUT, 0); +#endif +#ifdef BSP_USING_PWM5B + PORT_Init(PORTN, PIN9, FUNMUX1_PWM5B_OUT, 0); +#endif + } - return ret; + PWM_Init(pwm_drv[i].cfg->PWMx, &(pwm_drv[i].cfg->pwm_initstruct)); + if (rt_device_pwm_register(&pwm_drv[i].pwm_device, pwm_drv[i].cfg->name, &pwm_ops, pwm_drv[i].cfg) == RT_EOK) + { + LOG_D("%s register success", pwm_drv[i].cfg->name); + } + else + { + LOG_E("%s register failed", pwm_drv[i].cfg->name); + result = -RT_ERROR; + } + } + return result; } INIT_DEVICE_EXPORT(rt_hw_pwm_init); + +#endif /* BSP_USING_PWM */ +#endif /* RT_USING_PWM */ diff --git a/bsp/swm320-lq100/drivers/drv_pwm.h b/bsp/swm320-lq100/drivers/drv_pwm.h index 94bbf0c750..0e27cb2e7b 100644 --- a/bsp/swm320-lq100/drivers/drv_pwm.h +++ b/bsp/swm320-lq100/drivers/drv_pwm.h @@ -6,11 +6,159 @@ * Change Logs: * Date Author Notes * 2018-12-10 Zohar_Lee first version + * 2020-07-10 lik rewrite */ -#ifndef DRV_PWM_H__ -#define DRV_PWM_H__ +#ifndef __DRV_PWM_H__ +#define __DRV_PWM_H__ + +#include "board.h" + +struct swm_pwm_cfg +{ + const char *name; + PWM_TypeDef *PWMx; + PWM_InitStructure pwm_initstruct; +}; + +struct swm_pwm +{ + struct swm_pwm_cfg *cfg; + struct rt_device_pwm pwm_device; +}; + +#ifdef BSP_USING_PWM0 +#ifndef PWM0_CFG +#define PWM0_CFG \ + { \ + .name = "pwm0", \ + .PWMx = PWM0, \ + .pwm_initstruct.clk_div = PWM_CLKDIV_8, \ + .pwm_initstruct.mode = PWM_MODE_INDEP, \ + .pwm_initstruct.cycleA = 10000, \ + .pwm_initstruct.hdutyA = 5000, \ + .pwm_initstruct.initLevelA = 1, \ + .pwm_initstruct.cycleB = 10000, \ + .pwm_initstruct.hdutyB = 5000, \ + .pwm_initstruct.initLevelB = 1, \ + .pwm_initstruct.HEndAIEn = 0, \ + .pwm_initstruct.NCycleAIEn = 0, \ + .pwm_initstruct.HEndBIEn = 0, \ + .pwm_initstruct.NCycleBIEn = 0, \ + } +#endif /* PWM0_CFG */ +#endif /* BSP_USING_PWM0 */ + +#ifdef BSP_USING_PWM1 +#ifndef PWM1_CFG +#define PWM1_CFG \ + { \ + .name = "pwm1", \ + .PWMx = PWM1, \ + .pwm_initstruct.clk_div = PWM_CLKDIV_8, \ + .pwm_initstruct.mode = PWM_MODE_INDEP, \ + .pwm_initstruct.cycleA = 10000, \ + .pwm_initstruct.hdutyA = 5000, \ + .pwm_initstruct.initLevelA = 1, \ + .pwm_initstruct.cycleB = 10000, \ + .pwm_initstruct.hdutyB = 5000, \ + .pwm_initstruct.initLevelB = 1, \ + .pwm_initstruct.HEndAIEn = 0, \ + .pwm_initstruct.NCycleAIEn = 0, \ + .pwm_initstruct.HEndBIEn = 0, \ + .pwm_initstruct.NCycleBIEn = 0, \ + } +#endif /* PWM1_CFG */ +#endif /* BSP_USING_PWM1 */ + +#ifdef BSP_USING_PWM2 +#ifndef PWM2_CFG +#define PWM2_CFG \ + { \ + .name = "pwm2", \ + .PWMx = PWM2, \ + .pwm_initstruct.clk_div = PWM_CLKDIV_8, \ + .pwm_initstruct.mode = PWM_MODE_INDEP, \ + .pwm_initstruct.cycleA = 10000, \ + .pwm_initstruct.hdutyA = 5000, \ + .pwm_initstruct.initLevelA = 1, \ + .pwm_initstruct.cycleB = 10000, \ + .pwm_initstruct.hdutyB = 5000, \ + .pwm_initstruct.initLevelB = 1, \ + .pwm_initstruct.HEndAIEn = 0, \ + .pwm_initstruct.NCycleAIEn = 0, \ + .pwm_initstruct.HEndBIEn = 0, \ + .pwm_initstruct.NCycleBIEn = 0, \ + } +#endif /* PWM2_CFG */ +#endif /* BSP_USING_PWM2 */ + +#ifdef BSP_USING_PWM3 +#ifndef PWM3_CFG +#define PWM3_CFG \ + { \ + .name = "pwm3", \ + .PWMx = PWM3, \ + .pwm_initstruct.clk_div = PWM_CLKDIV_8, \ + .pwm_initstruct.mode = PWM_MODE_INDEP, \ + .pwm_initstruct.cycleA = 10000, \ + .pwm_initstruct.hdutyA = 5000, \ + .pwm_initstruct.initLevelA = 1, \ + .pwm_initstruct.cycleB = 10000, \ + .pwm_initstruct.hdutyB = 5000, \ + .pwm_initstruct.initLevelB = 1, \ + .pwm_initstruct.HEndAIEn = 0, \ + .pwm_initstruct.NCycleAIEn = 0, \ + .pwm_initstruct.HEndBIEn = 0, \ + .pwm_initstruct.NCycleBIEn = 0, \ + } +#endif /* PWM3_CFG */ +#endif /* BSP_USING_PWM3 */ + +#ifdef BSP_USING_PWM4 +#ifndef PWM4_CFG +#define PWM4_CFG \ + { \ + .name = "pwm4", \ + .PWMx = PWM4, \ + .pwm_initstruct.clk_div = PWM_CLKDIV_8, \ + .pwm_initstruct.mode = PWM_MODE_INDEP, \ + .pwm_initstruct.cycleA = 10000, \ + .pwm_initstruct.hdutyA = 5000, \ + .pwm_initstruct.initLevelA = 1, \ + .pwm_initstruct.cycleB = 10000, \ + .pwm_initstruct.hdutyB = 5000, \ + .pwm_initstruct.initLevelB = 1, \ + .pwm_initstruct.HEndAIEn = 0, \ + .pwm_initstruct.NCycleAIEn = 0, \ + .pwm_initstruct.HEndBIEn = 0, \ + .pwm_initstruct.NCycleBIEn = 0, \ + } +#endif /* PWM4_CFG */ +#endif /* BSP_USING_PWM4 */ + +#ifdef BSP_USING_PWM5 +#ifndef PWM5_CFG +#define PWM5_CFG \ + { \ + .name = "pwm5", \ + .PWMx = PWM5, \ + .pwm_initstruct.clk_div = PWM_CLKDIV_8, \ + .pwm_initstruct.mode = PWM_MODE_INDEP, \ + .pwm_initstruct.cycleA = 10000, \ + .pwm_initstruct.hdutyA = 5000, \ + .pwm_initstruct.initLevelA = 1, \ + .pwm_initstruct.cycleB = 10000, \ + .pwm_initstruct.hdutyB = 5000, \ + .pwm_initstruct.initLevelB = 1, \ + .pwm_initstruct.HEndAIEn = 0, \ + .pwm_initstruct.NCycleAIEn = 0, \ + .pwm_initstruct.HEndBIEn = 0, \ + .pwm_initstruct.NCycleBIEn = 0, \ + } +#endif /* PWM5_CFG */ +#endif /* BSP_USING_PWM5 */ int rt_hw_pwm_init(void); -#endif +#endif /* __DRV_PWM_H__ */ diff --git a/bsp/swm320-lq100/drivers/drv_rtc.c b/bsp/swm320-lq100/drivers/drv_rtc.c index 5219a5b013..74d41a2752 100644 --- a/bsp/swm320-lq100/drivers/drv_rtc.c +++ b/bsp/swm320-lq100/drivers/drv_rtc.c @@ -6,26 +6,19 @@ * Change Logs: * Date Author Notes * 2018-12-10 Zohar_Lee first version + * 2020-07-10 lik format file */ -#include <rthw.h> -#include <rtthread.h> -#include <rtdevice.h> -#include <board.h> -#include <string.h> +#include "drv_rtc.h" #include <sys/time.h> -/** - * This function will get the weed day from a date. - * - * @param year the year of time - * @param month the month of time - * @param date the date of time - * - * @return the week day 0 ~ 6 : sun ~ sat - * - * @note No - */ +#ifdef RT_USING_RTC +#ifdef BSP_USING_RTC + +//#define DRV_DEBUG +#define LOG_TAG "drv.rtc" +#include <drv_log.h> + static uint32_t calcWeekDay(uint32_t year, uint32_t month, uint32_t date) { uint32_t i, cnt = 0; @@ -36,8 +29,7 @@ static uint32_t calcWeekDay(uint32_t year, uint32_t month, uint32_t date) cnt += date; - if ((year % 4 == 0) && ((year % 100 != 0) || (year % 400 == 0)) && - (month >= 3)) + if ((year % 4 == 0) && ((year % 100 != 0) || (year % 400 == 0)) && (month >= 3)) cnt += 1; cnt += (year - 1901) * 365; @@ -51,127 +43,123 @@ static uint32_t calcWeekDay(uint32_t year, uint32_t month, uint32_t date) return (cnt + 1) % 7; } -static void RTC_SetDateTime(RTC_TypeDef *RTCx, RTC_DateTime *dateTime) +static time_t swm_get_rtc_time_stamp(void) { - RTC_Stop(RTCx); + RTC_DateTime get_datetime = {0}; + struct tm tm_new; - while (RTCx->CFGABLE == 0); + RTC_GetDateTime(RTC, &get_datetime); - RTCx->MINSEC = (dateTime->Second << RTC_MINSEC_SEC_Pos) | - (dateTime->Minute << RTC_MINSEC_MIN_Pos); + tm_new.tm_sec = get_datetime.Second; + tm_new.tm_min = get_datetime.Minute; + tm_new.tm_hour = get_datetime.Hour; + tm_new.tm_mday = get_datetime.Date; + tm_new.tm_mon = get_datetime.Month; + tm_new.tm_year = get_datetime.Year; - RTCx->DATHUR = (dateTime->Hour << RTC_DATHUR_HOUR_Pos) | - ((dateTime->Date - 1) << RTC_DATHUR_DATE_Pos); - - RTCx->MONDAY = (calcWeekDay(dateTime->Year, dateTime->Month, dateTime->Date) - << RTC_MONDAY_DAY_Pos) | - ((dateTime->Month - 1) << RTC_MONDAY_MON_Pos); + LOG_D("get rtc time."); + return mktime(&tm_new); +} +static rt_err_t swm_set_rtc_time_stamp(time_t time_stamp) +{ + RTC_DateTime set_datetime = {0}; + struct tm *p_tm; - RTCx->YEAR = dateTime->Year - 1901; + p_tm = gmtime(&time_stamp); - RTCx->LOAD = 1 << RTC_LOAD_TIME_Pos; + set_datetime.Second = p_tm->tm_sec; + set_datetime.Minute = p_tm->tm_min; + set_datetime.Hour = p_tm->tm_hour; + set_datetime.Date = p_tm->tm_mday; + set_datetime.Month = p_tm->tm_mon; + set_datetime.Year = p_tm->tm_year; + // set_datetime.Day = p_tm->tm_wday; + RTC_Stop(RTC); + while (RTC->CFGABLE == 0) + ; + RTC->MINSEC = (set_datetime.Second << RTC_MINSEC_SEC_Pos) | + (set_datetime.Minute << RTC_MINSEC_MIN_Pos); + RTC->DATHUR = (set_datetime.Hour << RTC_DATHUR_HOUR_Pos) | + ((set_datetime.Date) << RTC_DATHUR_DATE_Pos); + RTC->MONDAY = (calcWeekDay(set_datetime.Year, set_datetime.Month, set_datetime.Date) + << RTC_MONDAY_DAY_Pos) | + ((set_datetime.Month) << RTC_MONDAY_MON_Pos); + RTC->YEAR = set_datetime.Year; + RTC->LOAD = 1 << RTC_LOAD_TIME_Pos; RTC_Start(RTC); + + LOG_D("set rtc time."); + return RT_EOK; } -static rt_err_t swm320_rtc_control(rt_device_t dev, int cmd, void *args) +static rt_err_t swm_rtc_init(void) { - rt_err_t result = RT_EOK; + RTC_InitStructure rtc_initstruct; - struct tm time_temp; - struct tm *pNow; - RTC_DateTime dateTime; + rtc_initstruct.Year = 2020; + rtc_initstruct.Month = 6; + rtc_initstruct.Date = 8; + rtc_initstruct.Hour = 12; + rtc_initstruct.Minute = 0; + rtc_initstruct.Second = 0; + rtc_initstruct.SecondIEn = 0; + rtc_initstruct.MinuteIEn = 0; + RTC_Init(RTC, &rtc_initstruct); + RTC_Start(RTC); - switch (cmd) - { - case RT_DEVICE_CTRL_RTC_GET_TIME: - RTC_GetDateTime(RTC, &dateTime); - time_temp.tm_sec = dateTime.Second; - time_temp.tm_min = dateTime.Minute; - time_temp.tm_hour = dateTime.Hour; - time_temp.tm_mday = dateTime.Date; - time_temp.tm_mon = dateTime.Month - 1; - time_temp.tm_year = dateTime.Year - 1900; - *((time_t *)args) = timegm(&time_temp); - break; - case RT_DEVICE_CTRL_RTC_SET_TIME: - rt_enter_critical(); - /* converts calendar time time into local time. */ - pNow = gmtime((const time_t *)args); - /* copy the statically located variable */ - memcpy(&time_temp, pNow, sizeof(struct tm)); - /* unlock scheduler. */ - rt_exit_critical(); + return RT_EOK; +} - dateTime.Hour = time_temp.tm_hour; - dateTime.Minute = time_temp.tm_min; - dateTime.Second = time_temp.tm_sec; - dateTime.Year = time_temp.tm_year + 1900; - dateTime.Month = time_temp.tm_mon + 1; - dateTime.Date = time_temp.tm_mday; - RTC_SetDateTime(RTC, &dateTime); - break; - case RT_DEVICE_CTRL_RTC_GET_ALARM: +static rt_err_t swm_rtc_get_secs(void *args) +{ + *(rt_uint32_t *)args = swm_get_rtc_time_stamp(); + LOG_D("RTC: get rtc_time %x\n", *(rt_uint32_t *)args); - break; - case RT_DEVICE_CTRL_RTC_SET_ALARM: + return RT_EOK; +} - break; - default: - break; +static rt_err_t swm_rtc_set_secs(void *args) +{ + rt_err_t result = RT_EOK; + + if (swm_set_rtc_time_stamp(*(rt_uint32_t *)args)) + { + result = -RT_ERROR; } + LOG_D("RTC: set rtc_time %x\n", *(rt_uint32_t *)args); return result; } -#ifdef RT_USING_DEVICE_OPS -const static struct rt_device_ops swm320_rtc_ops = +static const struct rt_rtc_ops swm_rtc_ops = { + swm_rtc_init, + swm_rtc_get_secs, + swm_rtc_set_secs, RT_NULL, RT_NULL, RT_NULL, RT_NULL, - RT_NULL, - swm320_rtc_control }; -#endif + +static rt_rtc_dev_t swm_rtc_device; int rt_hw_rtc_init(void) { - rt_err_t ret = RT_EOK; - static struct rt_device rtc_dev; - RTC_InitStructure RTC_initStruct; - - RTC_initStruct.Year = 2018; - RTC_initStruct.Month = 1; - RTC_initStruct.Date = 1; - RTC_initStruct.Hour = 12; - RTC_initStruct.Minute = 0; - RTC_initStruct.Second = 0; - RTC_initStruct.SecondIEn = 0; - RTC_initStruct.MinuteIEn = 0; - RTC_Init(RTC, &RTC_initStruct); - RTC_Start(RTC); + rt_err_t result; - rtc_dev.type = RT_Device_Class_RTC; - rtc_dev.rx_indicate = RT_NULL; - rtc_dev.tx_complete = RT_NULL; - -#ifdef RT_USING_DEVICE_OPS - rtc_dev.ops = &swm320_rtc_ops; -#else - rtc_dev.init = RT_NULL; - rtc_dev.open = RT_NULL; - rtc_dev.close = RT_NULL; - rtc_dev.read = RT_NULL; - rtc_dev.write = RT_NULL; - rtc_dev.control = swm320_rtc_control; -#endif - - rtc_dev.user_data = RTC; - - ret = rt_device_register(&rtc_dev, "rtc", RT_DEVICE_FLAG_RDWR); - - return ret; + swm_rtc_device.ops = &swm_rtc_ops; + result = rt_hw_rtc_register(&swm_rtc_device, "rtc", RT_DEVICE_FLAG_RDWR,RT_NULL); + if (result != RT_EOK) + { + LOG_E("rtc register err code: %d", result); + return result; + } + LOG_D("rtc init success"); + return RT_EOK; } INIT_DEVICE_EXPORT(rt_hw_rtc_init); + +#endif /* BSP_USING_RTC */ +#endif /* RT_USING_RTC */ diff --git a/bsp/swm320-lq100/drivers/drv_rtc.h b/bsp/swm320-lq100/drivers/drv_rtc.h index f72d3d3d94..7a649c98af 100644 --- a/bsp/swm320-lq100/drivers/drv_rtc.h +++ b/bsp/swm320-lq100/drivers/drv_rtc.h @@ -6,11 +6,14 @@ * Change Logs: * Date Author Notes * 2018-12-10 Zohar_Lee first version + * 2020-07-10 lik rewrite */ -#ifndef DRV_RTC_H__ -#define DRV_RTC_H__ +#ifndef __DRV_RTC_H__ +#define __DRV_RTC_H__ + +#include "board.h" int rt_hw_rtc_init(void); -#endif +#endif /* __DRV_RTC_H__ */ diff --git a/bsp/swm320-lq100/drivers/drv_sdio.c b/bsp/swm320-lq100/drivers/drv_sdio.c new file mode 100644 index 0000000000..1fbbf3bce4 --- /dev/null +++ b/bsp/swm320-lq100/drivers/drv_sdio.c @@ -0,0 +1,664 @@ +/* + * Copyright (c) 2006-2018, Synwit Technology Co.,Ltd. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Change Logs: + * Date Author Notes + * 2020-07-10 lik first version + */ + +#include "drv_sdio.h" + +#ifdef RT_USING_SDIO +#ifdef BSP_USING_SDIO + +//#define DRV_DEBUG +#define LOG_TAG "drv.sdio" +#include <drv_log.h> + +static struct rt_mmcsd_host *host; + +#define RTHW_SDIO_LOCK(_sdio) rt_mutex_take(&_sdio->mutex, RT_WAITING_FOREVER) +#define RTHW_SDIO_UNLOCK(_sdio) rt_mutex_release(&_sdio->mutex); + +struct rthw_sdio +{ + struct rt_mmcsd_host *host; + struct swm_sdio_des sdio_des; + struct rt_event event; + struct rt_mutex mutex; + struct sdio_pkg *pkg; +}; + +ALIGN(SDIO_ALIGN_LEN) +static rt_uint8_t cache_buf[SDIO_BUFF_SIZE]; + +/** + * @brief This function wait sdio completed. + * @param sdio rthw_sdio + * @retval None + */ +static void rthw_sdio_wait_completed(struct rthw_sdio *sdio) +{ + rt_uint32_t status; + struct rt_mmcsd_cmd *cmd = sdio->pkg->cmd; + struct rt_mmcsd_data *data = cmd->data; + SDIO_TypeDef *hw_sdio = sdio->sdio_des.hw_sdio; + + if (rt_event_recv(&sdio->event, 0xffffffff, RT_EVENT_FLAG_OR | RT_EVENT_FLAG_CLEAR, + rt_tick_from_millisecond(1000), &status) != RT_EOK) + { + LOG_E("wait completed timeout"); + cmd->err = -RT_ETIMEOUT; + return; + } + + if (sdio->pkg == RT_NULL) + { + return; + } + + if (resp_type(cmd) == RESP_NONE) + { + ; + } + else if (resp_type(cmd) == RESP_R2) + { + cmd->resp[0] = (hw_sdio->RESP[3] << 8) + ((hw_sdio->RESP[2] >> 24) & 0xFF); + cmd->resp[1] = (hw_sdio->RESP[2] << 8) + ((hw_sdio->RESP[1] >> 24) & 0xFF); + cmd->resp[2] = (hw_sdio->RESP[1] << 8) + ((hw_sdio->RESP[0] >> 24) & 0xFF); + cmd->resp[3] = (hw_sdio->RESP[0] << 8) + 0x00; + } + else + { + cmd->resp[0] = hw_sdio->RESP[0]; + } + + if (status & SDIO_IF_ERROR_Msk) + { + if ((status & SDIO_IF_CMDCRCERR_Msk) && (resp_type(cmd) & (RESP_R3 | RESP_R4))) + { + cmd->err = RT_EOK; + } + else + { + cmd->err = -RT_ERROR; + } + + if (status & SDIO_IF_CMDTIMEOUT_Msk) + { + cmd->err = -RT_ETIMEOUT; + } + + if (status & SDIO_IF_DATCRCERR_Msk) + { + data->err = -RT_ERROR; + } + + if (status & SDIO_IF_DATTIMEOUT_Msk) + { + data->err = -RT_ETIMEOUT; + } + + if (cmd->err == RT_EOK) + { + LOG_D("sta:0x%08X [%08X %08X %08X %08X]", status, cmd->resp[0], cmd->resp[1], cmd->resp[2], cmd->resp[3]); + } + else + { + LOG_D("err:0x%08x, %s cmd:%d arg:0x%08x rw:%c len:%d blksize:%d", + status, + status == 0 ? "NULL" : "", + cmd->cmd_code, + cmd->arg, + data ? (data->flags & DATA_DIR_WRITE ? 'w' : 'r') : '-', + data ? data->blks * data->blksize : 0, + data ? data->blksize : 0); + } + } + else + { + cmd->err = RT_EOK; + LOG_D("sta:0x%08X [%08X %08X %08X %08X]", status, cmd->resp[0], cmd->resp[1], cmd->resp[2], cmd->resp[3]); + } +} + +/** + * @brief This function transfer data by dma. + * @param sdio rthw_sdio + * @param pkg sdio package + * @retval None + */ +static void rthw_sdio_transfer(struct rthw_sdio *sdio, struct sdio_pkg *pkg) +{ + struct rt_mmcsd_data *data; + int size; + void *buff; + + if ((RT_NULL == pkg) || (RT_NULL == sdio)) + { + LOG_E("rthw_sdio_transfer invalid args"); + return; + } + + data = pkg->cmd->data; + if (RT_NULL == data) + { + LOG_E("rthw_sdio_transfer invalid args"); + return; + } + + buff = pkg->buff; + if (RT_NULL == buff) + { + LOG_E("rthw_sdio_transfer invalid args"); + return; + } + + size = data->blks * data->blksize; + + if (data->flags & DATA_DIR_WRITE) + { + sdio->sdio_des.txconfig(pkg, (rt_uint32_t *)buff, size); + } + else if (data->flags & DATA_DIR_READ) + { + sdio->sdio_des.rxconfig(pkg, (rt_uint32_t *)buff, size); + } +} + +/** + * @brief This function send command. + * @param sdio rthw_sdio + * @param pkg sdio package + * @retval None + */ +static void rthw_sdio_send_command(struct rthw_sdio *sdio, struct sdio_pkg *pkg) +{ + struct rt_mmcsd_cmd *cmd = pkg->cmd; + struct rt_mmcsd_data *data = cmd->data; + SDIO_TypeDef *hw_sdio = sdio->sdio_des.hw_sdio; + rt_uint32_t reg_cmd; + + /* save pkg */ + sdio->pkg = pkg; + + LOG_D("CMD:%d ARG:0x%08x RES:%s%s%s%s%s%s%s%s%s rw:%c len:%d blksize:%d", + cmd->cmd_code, + cmd->arg, + resp_type(cmd) == RESP_NONE ? "NONE" : "", + resp_type(cmd) == RESP_R1 ? "R1" : "", + resp_type(cmd) == RESP_R1B ? "R1B" : "", + resp_type(cmd) == RESP_R2 ? "R2" : "", + resp_type(cmd) == RESP_R3 ? "R3" : "", + resp_type(cmd) == RESP_R4 ? "R4" : "", + resp_type(cmd) == RESP_R5 ? "R5" : "", + resp_type(cmd) == RESP_R6 ? "R6" : "", + resp_type(cmd) == RESP_R7 ? "R7" : "", + data ? (data->flags & DATA_DIR_WRITE ? 'w' : 'r') : '-', + data ? data->blks * data->blksize : 0, + data ? data->blksize : 0); + + /* config cmd reg */ + reg_cmd = (cmd->cmd_code << SDIO_CMD_CMDINDX_Pos) | + (0 << SDIO_CMD_CMDTYPE_Pos) | + (0 << SDIO_CMD_IDXCHECK_Pos) | + (0 << SDIO_CMD_CRCCHECK_Pos) | + (0 << SDIO_CMD_DMAEN_Pos); + if (resp_type(cmd) == RESP_NONE) + reg_cmd |= SD_RESP_NO << SDIO_CMD_RESPTYPE_Pos; + else if (resp_type(cmd) == RESP_R2) + reg_cmd |= SD_RESP_128b << SDIO_CMD_RESPTYPE_Pos; + else + reg_cmd |= SD_RESP_32b << SDIO_CMD_RESPTYPE_Pos; + + /* config data reg */ + if (data != RT_NULL) + { + rt_uint32_t dir = 0; + dir = (data->flags & DATA_DIR_READ) ? 1 : 0; + + hw_sdio->BLK = (data->blks << SDIO_BLK_COUNT_Pos) | (data->blksize << SDIO_BLK_SIZE_Pos); + + reg_cmd |= (1 << SDIO_CMD_HAVEDATA_Pos) | + (dir << SDIO_CMD_DIRREAD_Pos) | + ((data->blks > 1) << SDIO_CMD_MULTBLK_Pos) | + ((data->blks > 1) << SDIO_CMD_BLKCNTEN_Pos) | + (0 << SDIO_CMD_AUTOCMD12_Pos); + } + else + { + reg_cmd |= (0 << SDIO_CMD_HAVEDATA_Pos); + } + + if (cmd->cmd_code != SD_IO_SEND_OP_COND) + { + /* send cmd */ + hw_sdio->ARG = cmd->arg; + hw_sdio->CMD = reg_cmd; + } + + /* transfer config */ + if (data != RT_NULL) + { + rthw_sdio_transfer(sdio, pkg); + } + + /* wait completed */ + rthw_sdio_wait_completed(sdio); + + /* clear pkg */ + sdio->pkg = RT_NULL; +} + +/** + * @brief This function send sdio request. + * @param sdio rthw_sdio + * @param req request + * @retval None + */ +static void rthw_sdio_request(struct rt_mmcsd_host *host, struct rt_mmcsd_req *req) +{ + struct sdio_pkg pkg; + struct rthw_sdio *sdio = host->private_data; + struct rt_mmcsd_data *data; + + RTHW_SDIO_LOCK(sdio); + + if (req->cmd != RT_NULL) + { + rt_memset(&pkg, 0, sizeof(pkg)); + data = req->cmd->data; + pkg.cmd = req->cmd; + + if (data != RT_NULL) + { + rt_uint32_t size = data->blks * data->blksize; + + RT_ASSERT(size <= SDIO_BUFF_SIZE); + + pkg.buff = data->buf; + if ((rt_uint32_t)data->buf & (SDIO_ALIGN_LEN - 1)) + { + pkg.buff = cache_buf; + if (data->flags & DATA_DIR_WRITE) + { + rt_memcpy(cache_buf, data->buf, size); + } + } + } + + rthw_sdio_send_command(sdio, &pkg); + + if ((data != RT_NULL) && (data->flags & DATA_DIR_READ) && ((rt_uint32_t)data->buf & (SDIO_ALIGN_LEN - 1))) + { + rt_memcpy(data->buf, cache_buf, data->blksize * data->blks); + } + } + + if (req->stop != RT_NULL) + { + rt_memset(&pkg, 0, sizeof(pkg)); + pkg.cmd = req->stop; + rthw_sdio_send_command(sdio, &pkg); + } + + RTHW_SDIO_UNLOCK(sdio); + + mmcsd_req_complete(sdio->host); +} + +/** + * @brief This function config sdio. + * @param host rt_mmcsd_host + * @param io_cfg rt_mmcsd_io_cfg + * @retval None + */ +static void rthw_sdio_iocfg(struct rt_mmcsd_host *host, struct rt_mmcsd_io_cfg *io_cfg) +{ + rt_uint32_t clkcr, div, clk_src; + rt_uint32_t clk = io_cfg->clock; + struct rthw_sdio *sdio = host->private_data; + SDIO_TypeDef *hw_sdio = sdio->sdio_des.hw_sdio; + + clk_src = sdio->sdio_des.clk_get(sdio->sdio_des.hw_sdio); + if (clk_src < 400 * 1000) + { + LOG_E("The clock rate is too low! rata:%d", clk_src); + return; + } + + if (clk > host->freq_max) + clk = host->freq_max; + + if (clk > clk_src) + { + LOG_W("Setting rate is greater than clock source rate."); + clk = clk_src; + } + + LOG_D("clk:%d width:%s%s%s power:%s%s%s", + clk, + io_cfg->bus_width == MMCSD_BUS_WIDTH_8 ? "8" : "", + io_cfg->bus_width == MMCSD_BUS_WIDTH_4 ? "4" : "", + io_cfg->bus_width == MMCSD_BUS_WIDTH_1 ? "1" : "", + io_cfg->power_mode == MMCSD_POWER_OFF ? "OFF" : "", + io_cfg->power_mode == MMCSD_POWER_UP ? "UP" : "", + io_cfg->power_mode == MMCSD_POWER_ON ? "ON" : ""); + + RTHW_SDIO_LOCK(sdio); + + hw_sdio->CR1 = (1 << SDIO_CR1_CDSRC_Pos) | (7 << SDIO_CR1_VOLT_Pos); + if (io_cfg->bus_width == MMCSD_BUS_WIDTH_8) + { + hw_sdio->CR1 |= (1 << SDIO_CR1_8BIT_Pos); + } + else + { + hw_sdio->CR1 &= ~SDIO_CR1_8BIT_Msk; + if (io_cfg->bus_width == MMCSD_BUS_WIDTH_4) + { + hw_sdio->CR1 |= (1 << SDIO_CR1_4BIT_Pos); + } + else + { + hw_sdio->CR1 &= ~SDIO_CR1_4BIT_Msk; + } + } + switch (io_cfg->power_mode) + { + case MMCSD_POWER_OFF: + hw_sdio->CR1 &= ~SDIO_CR1_PWRON_Msk; + break; + case MMCSD_POWER_UP: + case MMCSD_POWER_ON: + hw_sdio->CR1 |= (1 << SDIO_CR1_PWRON_Pos); + break; + default: + LOG_W("unknown power_mode %d", io_cfg->power_mode); + break; + } + + div = clk_src / clk; + if ((clk == 0) || (div == 0)) + { + clkcr = 0; + } + else + { + if (div > 128) + clkcr = 0x80; + else if (div > 64) + clkcr = 0x40; + else if (div > 32) + clkcr = 0x20; + else if (div > 16) + clkcr = 0x10; + else if (div > 8) + clkcr = 0x08; + else if (div > 4) + clkcr = 0x04; + else if (div > 2) + clkcr = 0x02; + else if (div > 1) + clkcr = 0x01; + else + clkcr = 0x00; + } + + SDIO->CR2 = (1 << SDIO_CR2_CLKEN_Pos) | + (1 << SDIO_CR2_SDCLKEN_Pos) | + (clkcr << SDIO_CR2_SDCLKDIV_Pos) | + (0xC << SDIO_CR2_TIMEOUT_Pos); // 2**25 SDIO_CLK + + while ((SDIO->CR2 & SDIO_CR2_CLKRDY_Msk) == 0) + ; + + RTHW_SDIO_UNLOCK(sdio); +} + +/** + * @brief This function delect sdcard. + * @param host rt_mmcsd_host + * @retval 0x01 + */ +static rt_int32_t rthw_sdio_delect(struct rt_mmcsd_host *host) +{ + LOG_D("try to detect device"); + return 0x01; +} + +/** + * @brief This function update sdio interrupt. + * @param host rt_mmcsd_host + * @param enable + * @retval None + */ +void rthw_sdio_irq_update(struct rt_mmcsd_host *host, rt_int32_t enable) +{ + struct rthw_sdio *sdio = host->private_data; + SDIO_TypeDef *hw_sdio = sdio->sdio_des.hw_sdio; + + if (enable) + { + LOG_D("enable sdio irq"); + hw_sdio->IFE = 0xFFFFFFFF; + hw_sdio->IE = 0xFFFF000F; + } + else + { + LOG_D("disable sdio irq"); + hw_sdio->IFE &= ~0xFFFFFFFF; + hw_sdio->IE &= ~0xFFFFFFFF; + } +} + +static const struct rt_mmcsd_host_ops swm_sdio_ops = + { + rthw_sdio_request, + rthw_sdio_iocfg, + rthw_sdio_delect, + rthw_sdio_irq_update, +}; + +struct rt_mmcsd_host *sdio_host_create(struct swm_sdio_des *sdio_des) +{ + struct rt_mmcsd_host *host; + struct rthw_sdio *sdio = RT_NULL; + + if ((sdio_des == RT_NULL) || (sdio_des->txconfig == RT_NULL) || (sdio_des->rxconfig == RT_NULL)) + { + LOG_E("L:%d F:%s %s %s %s", + (sdio_des == RT_NULL ? "sdio_des is NULL" : ""), + (sdio_des ? (sdio_des->txconfig ? "txconfig is NULL" : "") : ""), + (sdio_des ? (sdio_des->rxconfig ? "rxconfig is NULL" : "") : "")); + return RT_NULL; + } + + sdio = rt_malloc(sizeof(struct rthw_sdio)); + if (sdio == RT_NULL) + { + LOG_E("L:%d F:%s malloc rthw_sdio fail"); + return RT_NULL; + } + rt_memset(sdio, 0, sizeof(struct rthw_sdio)); + + host = mmcsd_alloc_host(); + if (host == RT_NULL) + { + LOG_E("L:%d F:%s mmcsd alloc host fail"); + rt_free(sdio); + return RT_NULL; + } + + rt_memcpy(&sdio->sdio_des, sdio_des, sizeof(struct swm_sdio_des)); + + rt_event_init(&sdio->event, "sdio", RT_IPC_FLAG_FIFO); + rt_mutex_init(&sdio->mutex, "sdio", RT_IPC_FLAG_FIFO); + + /* set host defautl attributes */ + host->ops = &swm_sdio_ops; + host->freq_min = 400 * 1000; + host->freq_max = SDIO_MAX_FREQ; + host->valid_ocr = 0X00FFFF80; /* The voltage range supported is 1.65v-3.6v */ +#ifndef SDIO_USING_1_BIT + host->flags = MMCSD_BUSWIDTH_4 | MMCSD_MUTBLKWRITE | MMCSD_SUP_SDIO_IRQ; +#else + host->flags = MMCSD_MUTBLKWRITE | MMCSD_SUP_SDIO_IRQ; +#endif + host->max_seg_size = SDIO_BUFF_SIZE; + host->max_dma_segs = 1; + host->max_blk_size = 512; + host->max_blk_count = 512; + + /* link up host and sdio */ + sdio->host = host; + host->private_data = sdio; + + rthw_sdio_irq_update(host, 1); + + /* ready to change */ + mmcsd_change(host); + + return host; +} + +static rt_uint32_t swm_sdio_clock_get(SDIO_TypeDef *hw_sdio) +{ + uint32_t prediv = ((SYS->CLKDIV & SYS_CLKDIV_SDIO_Msk) >> SYS_CLKDIV_SDIO_Pos); + return (SystemCoreClock / (1 << prediv)); +} + +static rt_err_t swm_sdio_rxconfig(struct sdio_pkg *pkg, rt_uint32_t *buff, int size) +{ + struct rt_mmcsd_cmd *cmd = pkg->cmd; + struct rt_mmcsd_data *data = cmd->data; + for (uint32_t i = 0; i < data->blks; i++) + { + while ((SDIO->IF & SDIO_IF_BUFRDRDY_Msk) == 0) + __NOP(); + SDIO->IF = SDIO_IF_BUFRDRDY_Msk; + for (uint32_t j = 0; j < data->blksize / 4; j++) + buff[j] = SDIO->DATA; + } + return RT_EOK; +} + +static rt_err_t swm_sdio_txconfig(struct sdio_pkg *pkg, rt_uint32_t *buff, int size) +{ + struct rt_mmcsd_cmd *cmd = pkg->cmd; + struct rt_mmcsd_data *data = cmd->data; + for (uint32_t i = 0; i < data->blks; i++) + { + while ((SDIO->IF & SDIO_IF_BUFWRRDY_Msk) == 0) + __NOP(); + SDIO->IF = SDIO_IF_BUFWRRDY_Msk; + for (uint32_t j = 0; j < data->blksize / 4; j++) + SDIO->DATA = buff[j]; + } + return RT_EOK; +} + +/** + * @brief This function interrupt process function. + * @param host rt_mmcsd_host + * @retval None + */ +void rthw_sdio_irq_process(struct rt_mmcsd_host *host) +{ + int complete = 0; + struct rthw_sdio *sdio = host->private_data; + SDIO_TypeDef *hw_sdio = sdio->sdio_des.hw_sdio; + rt_uint32_t intstatus = hw_sdio->IF; + + if (intstatus & SDIO_IF_ERROR_Msk) + { + hw_sdio->IF = 0xFFFFFFFF; + complete = 1; + } + else + { + if (intstatus & SDIO_IF_CMDDONE_Msk) + { + hw_sdio->IF = SDIO_IF_CMDDONE_Msk; + if (sdio->pkg != RT_NULL) + { + if (!sdio->pkg->cmd->data) + { + complete = 1; + } + } + } + + if (intstatus & SDIO_IF_TRXDONE_Msk) + { + hw_sdio->IF = SDIO_IF_TRXDONE_Msk; + complete = 1; + } + } + + if (complete) + { + rt_event_send(&sdio->event, intstatus); + } +} + +void SDIO_Handler(void) +{ + /* enter interrupt */ + rt_interrupt_enter(); + /* Process All SDIO Interrupt Sources */ + rthw_sdio_irq_process(host); + /* leave interrupt */ + rt_interrupt_leave(); +} + +int rt_hw_sdio_init(void) +{ + struct swm_sdio_des sdio_des; + +#if 0 + PORT_Init(PORTB, PIN1, PORTB_PIN1_SD_CLK, 0); + PORT_Init(PORTB, PIN2, PORTB_PIN2_SD_CMD, 1); + PORT_Init(PORTB, PIN3, PORTB_PIN3_SD_D0, 1); + PORT_Init(PORTB, PIN4, PORTB_PIN4_SD_D1, 1); + PORT_Init(PORTB, PIN5, PORTB_PIN5_SD_D2, 1); + PORT_Init(PORTB, PIN6, PORTB_PIN6_SD_D3, 1); +#else + PORT_Init(PORTP, PIN11, PORTP_PIN11_SD_CLK, 0); + PORT_Init(PORTP, PIN10, PORTP_PIN10_SD_CMD, 1); + PORT_Init(PORTP, PIN9, PORTP_PIN9_SD_D0, 1); + PORT_Init(PORTP, PIN8, PORTP_PIN8_SD_D1, 1); + PORT_Init(PORTP, PIN7, PORTP_PIN7_SD_D2, 1); + PORT_Init(PORTP, PIN6, PORTP_PIN6_SD_D3, 1); +#endif + NVIC_EnableIRQ(SDIO_IRQn); + SYS->CLKDIV &= ~SYS_CLKDIV_SDIO_Msk; + if (SystemCoreClock > 80000000) //SDIO时钟需要小于52MHz + SYS->CLKDIV |= (2 << SYS_CLKDIV_SDIO_Pos); //SDCLK = SYSCLK / 4 + else + SYS->CLKDIV |= (1 << SYS_CLKDIV_SDIO_Pos); //SDCLK = SYSCLK / 2 + + SYS->CLKEN |= (0x01 << SYS_CLKEN_SDIO_Pos); + + SDIO->CR2 = (1 << SDIO_CR2_RSTALL_Pos); + + NVIC_EnableIRQ(SDIO_IRQn); + sdio_des.clk_get = swm_sdio_clock_get; + sdio_des.hw_sdio = SDIO; + sdio_des.rxconfig = swm_sdio_rxconfig; + sdio_des.txconfig = swm_sdio_txconfig; + + host = sdio_host_create(&sdio_des); + if (host == RT_NULL) + { + LOG_E("host create fail"); + return -1; + } + return 0; +} +INIT_DEVICE_EXPORT(rt_hw_sdio_init); + +#endif /* BSP_USING_SDIO */ +#endif /* RT_USING_SDIO */ diff --git a/bsp/swm320-lq100/drivers/drv_sdio.h b/bsp/swm320-lq100/drivers/drv_sdio.h new file mode 100644 index 0000000000..16f2420344 --- /dev/null +++ b/bsp/swm320-lq100/drivers/drv_sdio.h @@ -0,0 +1,42 @@ +/* + * Copyright (c) 2006-2018, Synwit Technology Co.,Ltd. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Change Logs: + * Date Author Notes + * 2020-07-10 lik first version + */ + +#ifndef __DRV_SDIO_H__ +#define __DRV_SDIO_H__ + +#include "board.h" + +#define SDIO_BUFF_SIZE 4096 +#define SDIO_ALIGN_LEN 4 + +#ifndef SDIO_MAX_FREQ +#define SDIO_MAX_FREQ (30000000) +#endif + +struct sdio_pkg +{ + struct rt_mmcsd_cmd *cmd; + void *buff; + rt_uint32_t flag; +}; + +typedef rt_err_t (*sdio_txconfig)(struct sdio_pkg *pkg, rt_uint32_t *buff, int size); +typedef rt_err_t (*sdio_rxconfig)(struct sdio_pkg *pkg, rt_uint32_t *buff, int size); +typedef rt_uint32_t (*sdio_clk_get)(SDIO_TypeDef *hw_sdio); + +struct swm_sdio_des +{ + SDIO_TypeDef *hw_sdio; + sdio_txconfig txconfig; + sdio_rxconfig rxconfig; + sdio_clk_get clk_get; +}; + +#endif /* __DRV_SDIO_H__ */ diff --git a/bsp/swm320-lq100/drivers/drv_soft_i2c.c b/bsp/swm320-lq100/drivers/drv_soft_i2c.c new file mode 100644 index 0000000000..d63b7ca35c --- /dev/null +++ b/bsp/swm320-lq100/drivers/drv_soft_i2c.c @@ -0,0 +1,197 @@ +/* + * Copyright (c) 2006-2018, Synwit Technology Co.,Ltd. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Change Logs: + * Date Author Notes + * 2018-05-31 ZYH first version + * 2018-12-10 Zohar_Lee format file + * 2020-07-10 lik rewrite + */ + +#include "drv_soft_i2c.h" + +#ifdef RT_USING_I2C +#ifdef BSP_USING_I2C + +/*************************************************************** +*!!!!!!!!!!!!!!!!!!!!!!!!!!!!NOTICE!!!!!!!!!!!!!!!!!!!!!!!!!!!!! +*In order to use swm drv_soft_i2c,you need to commented out +line 114 (SDA_H(ops);) and line 167 (SDA_H(ops);) in i2c-bit-ops.c +At the same time, add one line (SDA_L(ops);)after line 154 (SCL_L(ops);) +in i2c-bit-ops.c +***************************************************************/ + +//#define DRV_DEBUG +#define LOG_TAG "drv.i2c" +#include <drv_log.h> + +#if !defined(BSP_USING_I2C0) && !defined(BSP_USING_I2C1) +#error "Please define at least one BSP_USING_I2Cx" +/* this driver can be disabled at menuconfig ? RT-Thread Components ? Device Drivers */ +#endif + +static const struct swm_soft_i2c_cfg soft_i2c_cfg[] = + { +#ifdef BSP_USING_I2C0 + I2C0_BUS_CFG, +#endif +#ifdef BSP_USING_I2C1 + I2C1_BUS_CFG, +#endif +}; + +static struct swm_i2c i2c_drv[sizeof(soft_i2c_cfg) / sizeof(soft_i2c_cfg[0])]; + +/** + * This function initializes the i2c pin. + * + * @param swm i2c dirver class. + */ +static void swm_i2c_gpio_init(struct swm_i2c *i2c) +{ + struct swm_soft_i2c_cfg *cfg = (struct swm_soft_i2c_cfg *)i2c->ops.data; + + rt_pin_mode(cfg->scl, PIN_MODE_OUTPUT_OD); + rt_pin_mode(cfg->sda, PIN_MODE_OUTPUT_OD); + + rt_pin_write(cfg->scl, PIN_HIGH); + rt_pin_write(cfg->sda, PIN_HIGH); +} + +/** + * This function sets the sda pin. + * + * @param swm config class. + * @param The sda pin state. + */ +static void swm_set_sda(void *data, rt_int32_t state) +{ + struct swm_soft_i2c_cfg *cfg = (struct swm_soft_i2c_cfg *)data; + rt_pin_mode(cfg->sda, PIN_MODE_OUTPUT_OD); + if (state) + { + rt_pin_write(cfg->sda, PIN_HIGH); + } + else + { + rt_pin_write(cfg->sda, PIN_LOW); + } +} + +/** + * This function sets the scl pin. + * + * @param swm config class. + * @param The scl pin state. + */ +static void swm_set_scl(void *data, rt_int32_t state) +{ + struct swm_soft_i2c_cfg *cfg = (struct swm_soft_i2c_cfg *)data; + rt_pin_mode(cfg->scl, PIN_MODE_OUTPUT_OD); + if (state) + { + rt_pin_write(cfg->scl, PIN_HIGH); + } + else + { + rt_pin_write(cfg->scl, PIN_LOW); + } +} + +/** + * This function gets the sda pin state. + * + * @param The sda pin state. + */ +static rt_int32_t swm_get_sda(void *data) +{ + struct swm_soft_i2c_cfg *cfg = (struct swm_soft_i2c_cfg *)data; + rt_pin_mode(cfg->sda, PIN_MODE_INPUT_PULLUP); + return rt_pin_read(cfg->sda); +} + +/** + * This function gets the scl pin state. + * + * @param The scl pin state. + */ +static rt_int32_t swm_get_scl(void *data) +{ + struct swm_soft_i2c_cfg *cfg = (struct swm_soft_i2c_cfg *)data; + rt_pin_mode(cfg->scl, PIN_MODE_INPUT_PULLUP); + return rt_pin_read(cfg->scl); +} + +/** + * The time delay function. + * + * @param microseconds. + */ +static void swm_udelay(rt_uint32_t us) +{ + rt_uint32_t ticks; + rt_uint32_t told, tnow, tcnt = 0; + rt_uint32_t reload = SysTick->LOAD; + + ticks = us * reload / (1000000 / RT_TICK_PER_SECOND); + told = SysTick->VAL; + while (1) + { + tnow = SysTick->VAL; + if (tnow != told) + { + if (tnow < told) + { + tcnt += told - tnow; + } + else + { + tcnt += reload - tnow + told; + } + told = tnow; + if (tcnt >= ticks) + { + break; + } + } + } +} + +static const struct rt_i2c_bit_ops swm_bit_ops = + { + .data = RT_NULL, + .set_sda = swm_set_sda, + .set_scl = swm_set_scl, + .get_sda = swm_get_sda, + .get_scl = swm_get_scl, + .udelay = swm_udelay, + .delay_us = 1, + .timeout = 100}; + +/* I2C initialization function */ +int rt_hw_i2c_init(void) +{ + rt_err_t result; + + for (int i = 0; i < sizeof(i2c_drv) / sizeof(struct swm_i2c); i++) + { + i2c_drv[i].ops = swm_bit_ops; + i2c_drv[i].ops.data = (void *)&soft_i2c_cfg[i]; + i2c_drv[i].i2c2_bus.priv = &i2c_drv[i].ops; + swm_i2c_gpio_init(&i2c_drv[i]); + result = rt_i2c_bit_add_bus(&i2c_drv[i].i2c2_bus, soft_i2c_cfg[i].name); + RT_ASSERT(result == RT_EOK); + + LOG_D("software simulation %s init done, pin scl: %d, pin sda %d", + soft_i2c_cfg[i].name, + soft_i2c_cfg[i].scl, + soft_i2c_cfg[i].sda); + } + + return RT_EOK; +} +INIT_DEVICE_EXPORT(rt_hw_i2c_init); +#endif /* BSP_USING_I2C */ +#endif /* RT_USING_I2C */ diff --git a/bsp/swm320-lq100/drivers/drv_soft_i2c.h b/bsp/swm320-lq100/drivers/drv_soft_i2c.h new file mode 100644 index 0000000000..f22922c7d0 --- /dev/null +++ b/bsp/swm320-lq100/drivers/drv_soft_i2c.h @@ -0,0 +1,51 @@ +/* + * Copyright (c) 2006-2018, Synwit Technology Co.,Ltd. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Change Logs: + * Date Author Notes + * 2018-12-10 Zohar_Lee first version + * 2020-07-10 lik rewrite + */ + +#ifndef __DRV_SOFT_I2C_H__ +#define __DRV_SOFT_I2C_H__ + +#include "board.h" + +/* swm config class */ +struct swm_soft_i2c_cfg +{ + rt_uint8_t scl; + rt_uint8_t sda; + const char *name; +}; +/* swm i2c dirver class */ +struct swm_i2c +{ + struct rt_i2c_bit_ops ops; + struct rt_i2c_bus_device i2c2_bus; +}; + +#ifdef BSP_USING_I2C0 +#define I2C0_BUS_CFG \ + { \ + .scl = BSP_I2C0_SCL_PIN, \ + .sda = BSP_I2C0_SDA_PIN, \ + .name = "i2c0", \ + } +#endif + +#ifdef BSP_USING_I2C1 +#define I2C1_BUS_CFG \ + { \ + .scl = BSP_I2C1_SCL_PIN, \ + .sda = BSP_I2C1_SDA_PIN, \ + .name = "i2c1", \ + } +#endif + +int rt_hw_i2c_init(void); + +#endif /* __DRV_SOFT_I2C_H__ */ diff --git a/bsp/swm320-lq100/drivers/drv_spi.c b/bsp/swm320-lq100/drivers/drv_spi.c index e766f0ea81..20ea69cb85 100644 --- a/bsp/swm320-lq100/drivers/drv_spi.c +++ b/bsp/swm320-lq100/drivers/drv_spi.c @@ -7,109 +7,119 @@ * Date Author Notes * 2018-05-31 ZYH first version * 2018-12-10 Zohar_Lee format file + * 2020-07-10 lik format file */ -#include <board.h> -#include <rtthread.h> -#include <rtdevice.h> -#include <SWM320_port.h> -#include <rthw.h> -#include <drv_spi.h> +#include "drv_spi.h" -#define SPIRXEVENT 0x01 -#define SPITXEVENT 0x02 -#define SPITIMEOUT 2 -#define SPICRCEN 0 +#ifdef RT_USING_SPI +#ifdef BSP_USING_SPI -struct swm320_spi -{ - SPI_TypeDef *swm320_spi; - struct rt_spi_configuration *cfg; +//#define DRV_DEBUG +#define LOG_TAG "drv.spi" +#include <drv_log.h> + +static struct swm_spi_cfg spi_cfg[] = + { +#ifdef BSP_USING_SPI0 + SPI0_BUS_CONFIG, +#endif +#ifdef BSP_USING_SPI1 + SPI1_BUS_CONFIG, +#endif }; -static rt_err_t swm320_spi_init(SPI_TypeDef *spix, - struct rt_spi_configuration *cfg) +static struct swm_spi spi_bus_drv[sizeof(spi_cfg) / sizeof(spi_cfg[0])] = {0}; + +static rt_err_t swm_spi_init(struct swm_spi *spi_drv, struct rt_spi_configuration *configure) { - SPI_InitStructure SPI_initStruct; - if (cfg->mode & RT_SPI_SLAVE) + RT_ASSERT(spi_drv != RT_NULL); + RT_ASSERT(configure != RT_NULL); + + struct swm_spi_cfg *cfg = spi_drv->cfg; + + if (configure->mode & RT_SPI_SLAVE) { - SPI_initStruct.Master = 0; + cfg->spi_initstruct.Master = 0; } else { - SPI_initStruct.Master = 1; + cfg->spi_initstruct.Master = 1; } - if (cfg->mode & RT_SPI_3WIRE) + + if (configure->mode & RT_SPI_3WIRE) { return RT_EINVAL; } - if (cfg->data_width == 8) + + if (configure->data_width == 8) { - SPI_initStruct.WordSize = 8; + cfg->spi_initstruct.WordSize = 8; } - else if (cfg->data_width == 16) + else if (configure->data_width == 16) { - SPI_initStruct.WordSize = 16; + cfg->spi_initstruct.WordSize = 16; } else { - return RT_EINVAL; + return RT_EIO; } - if (cfg->mode & RT_SPI_CPHA) + + if (configure->mode & RT_SPI_CPHA) { - SPI_initStruct.SampleEdge = SPI_SECOND_EDGE; + cfg->spi_initstruct.SampleEdge = SPI_SECOND_EDGE; } else { - SPI_initStruct.SampleEdge = SPI_FIRST_EDGE; + cfg->spi_initstruct.SampleEdge = SPI_FIRST_EDGE; } - if (cfg->mode & RT_SPI_CPOL) + + if (configure->mode & RT_SPI_CPOL) { - SPI_initStruct.IdleLevel = SPI_HIGH_LEVEL; + cfg->spi_initstruct.IdleLevel = SPI_HIGH_LEVEL; } else { - SPI_initStruct.IdleLevel = SPI_LOW_LEVEL; + cfg->spi_initstruct.IdleLevel = SPI_LOW_LEVEL; } - if (cfg->max_hz >= SystemCoreClock / 4) + + if (configure->max_hz >= SystemCoreClock / 4) { - SPI_initStruct.clkDiv = SPI_CLKDIV_4; + cfg->spi_initstruct.clkDiv = SPI_CLKDIV_4; } - else if (cfg->max_hz >= SystemCoreClock / 8) + else if (configure->max_hz >= SystemCoreClock / 8) { - SPI_initStruct.clkDiv = SPI_CLKDIV_8; + cfg->spi_initstruct.clkDiv = SPI_CLKDIV_8; } - else if (cfg->max_hz >= SystemCoreClock / 16) + else if (configure->max_hz >= SystemCoreClock / 16) { - SPI_initStruct.clkDiv = SPI_CLKDIV_16; + cfg->spi_initstruct.clkDiv = SPI_CLKDIV_16; } - else if (cfg->max_hz >= SystemCoreClock / 32) + else if (configure->max_hz >= SystemCoreClock / 32) { - SPI_initStruct.clkDiv = SPI_CLKDIV_32; + cfg->spi_initstruct.clkDiv = SPI_CLKDIV_32; } - else if (cfg->max_hz >= SystemCoreClock / 64) + else if (configure->max_hz >= SystemCoreClock / 64) { - SPI_initStruct.clkDiv = SPI_CLKDIV_64; + cfg->spi_initstruct.clkDiv = SPI_CLKDIV_64; } - else if (cfg->max_hz >= SystemCoreClock / 128) + else if (configure->max_hz >= SystemCoreClock / 128) { - SPI_initStruct.clkDiv = SPI_CLKDIV_128; + cfg->spi_initstruct.clkDiv = SPI_CLKDIV_128; } - else if (cfg->max_hz >= SystemCoreClock / 256) + else if (configure->max_hz >= SystemCoreClock / 256) { - SPI_initStruct.clkDiv = SPI_CLKDIV_256; + cfg->spi_initstruct.clkDiv = SPI_CLKDIV_256; } else { /* min prescaler 512 */ - SPI_initStruct.clkDiv = SPI_CLKDIV_512; + cfg->spi_initstruct.clkDiv = SPI_CLKDIV_512; } - SPI_initStruct.FrameFormat = SPI_FORMAT_SPI; - SPI_initStruct.RXHFullIEn = 0; - SPI_initStruct.TXEmptyIEn = 0; - SPI_initStruct.TXCompleteIEn = 0; - SPI_Init(spix, &SPI_initStruct); - SPI_Open(spix); + + SPI_Init(cfg->SPIx, &(cfg->spi_initstruct)); + SPI_Open(cfg->SPIx); + LOG_D("%s init done", cfg->name); return RT_EOK; } @@ -139,7 +149,7 @@ static rt_err_t swm320_spi_init(SPI_TypeDef *spix, } \ } while (0) -static rt_err_t spitxrx1b(struct swm320_spi *hspi, void *rcvb, const void *sndb) +static rt_err_t spitxrx1b(struct swm_spi *spi_drv, void *rcvb, const void *sndb) { rt_uint32_t padrcv = 0; rt_uint32_t padsnd = 0xFF; @@ -155,39 +165,51 @@ static rt_err_t spitxrx1b(struct swm320_spi *hspi, void *rcvb, const void *sndb) { sndb = &padsnd; } - while (SPI_IsTXFull(hspi->swm320_spi)); - SPISEND_1(hspi->swm320_spi->DATA, sndb, hspi->cfg->data_width); - while (SPI_IsRXEmpty(hspi->swm320_spi)); - SPIRECV_1(hspi->swm320_spi->DATA, rcvb, hspi->cfg->data_width); + while (SPI_IsTXFull(spi_drv->cfg->SPIx)) + ; + SPISEND_1(spi_drv->cfg->SPIx->DATA, sndb, spi_drv->cfg->spi_initstruct.WordSize); + while (SPI_IsRXEmpty(spi_drv->cfg->SPIx)) + ; + SPIRECV_1(spi_drv->cfg->SPIx->DATA, rcvb, spi_drv->cfg->spi_initstruct.WordSize); return RT_EOK; } -static rt_uint32_t swm320_spi_xfer(struct rt_spi_device *device, - struct rt_spi_message *message) +static rt_uint32_t swm_spi_xfer(struct rt_spi_device *device, struct rt_spi_message *message) { rt_err_t res; - struct swm320_spi *hspi = (struct swm320_spi *)device->bus->parent.user_data; - struct swm320_spi_cs *cs = device->parent.user_data; - const rt_uint8_t *sndb = message->send_buf; - rt_uint8_t *rcvb = message->recv_buf; - rt_int32_t length = message->length; + RT_ASSERT(device != RT_NULL); RT_ASSERT(device->bus != RT_NULL); RT_ASSERT(device->bus->parent.user_data != RT_NULL); + RT_ASSERT(message != RT_NULL); + + struct swm_spi *spi_drv = rt_container_of(device->bus, struct swm_spi, spi_bus); + struct swm_spi_cfg *cfg = spi_drv->cfg; + struct swm_spi_cs *cs = device->parent.user_data; + if (message->cs_take) { - rt_pin_write(cs->pin, 0); + GPIO_ClrBit(cs->GPIOx, cs->gpio_pin); } + + LOG_D("%s transfer prepare and start", cfg->name); + LOG_D("%s sendbuf: %X, recvbuf: %X, length: %d", + cfg->name, (uint32_t)message->send_buf, (uint32_t)message->recv_buf, message->length); + + const rt_uint8_t *sndb = message->send_buf; + rt_uint8_t *rcvb = message->recv_buf; + rt_int32_t length = message->length; + while (length) { - res = spitxrx1b(hspi, rcvb, sndb); + res = spitxrx1b(spi_drv, rcvb, sndb); if (rcvb) { - rcvb += SPISTEP(hspi->cfg->data_width); + rcvb += SPISTEP(cfg->spi_initstruct.WordSize); } if (sndb) { - sndb += SPISTEP(hspi->cfg->data_width); + sndb += SPISTEP(cfg->spi_initstruct.WordSize); } if (res != RT_EOK) { @@ -196,93 +218,90 @@ static rt_uint32_t swm320_spi_xfer(struct rt_spi_device *device, length--; } /* Wait until Busy flag is reset before disabling SPI */ - while (!SPI_IsTXEmpty(hspi->swm320_spi) && !SPI_IsRXEmpty(hspi->swm320_spi)); + while (!SPI_IsTXEmpty(cfg->SPIx) && !SPI_IsRXEmpty(cfg->SPIx)) + ; if (message->cs_release) { - rt_pin_write(cs->pin, 1); + GPIO_SetBit(cs->GPIOx, cs->gpio_pin); } return message->length - length; } -static rt_err_t swm320_spi_configure(struct rt_spi_device *device, - struct rt_spi_configuration *configuration) +static rt_err_t swm_spi_configure(struct rt_spi_device *device, + struct rt_spi_configuration *configure) { - struct swm320_spi *hspi = (struct swm320_spi *)device->bus->parent.user_data; - hspi->cfg = configuration; - return swm320_spi_init(hspi->swm320_spi, configuration); -} -const static struct rt_spi_ops swm320_spi_ops = -{ - .configure = swm320_spi_configure, - .xfer = swm320_spi_xfer, -}; - -#ifdef BSP_USING_SPI0 - static struct rt_spi_bus swm320_spi_bus0; - static struct swm320_spi swm320_spi0; -#endif //BSP_USING_SPI0 + RT_ASSERT(device != RT_NULL); + RT_ASSERT(configure != RT_NULL); -#ifdef BSP_USING_SPI1 - static struct rt_spi_bus swm320_spi_bus1; - static struct swm320_spi swm320_spi1; -#endif //BSP_USING_SPI1 + struct swm_spi *spi_drv = rt_container_of(device->bus, struct swm_spi, spi_bus); + spi_drv->configure = configure; -static int swm320_spi_register_bus(SPI_TypeDef *SPIx, const char *name) -{ - struct rt_spi_bus *spi_bus; - struct swm320_spi *swm320_spi; - if (SPIx == SPI0) - { - PORT_Init(PORTC, PIN5, FUNMUX1_SPI0_SCLK, 0); - PORT_Init(PORTC, PIN6, FUNMUX0_SPI0_MOSI, 0); - PORT_Init(PORTC, PIN7, FUNMUX1_SPI0_MISO, 1); - spi_bus = &swm320_spi_bus0; - swm320_spi = &swm320_spi0; - } - else if (SPIx == SPI1) - { - PORT_Init(PORTM, PIN5, FUNMUX1_SPI1_SCLK, 0); - PORT_Init(PORTC, PIN2, FUNMUX0_SPI1_MOSI, 0); - PORT_Init(PORTC, PIN3, FUNMUX1_SPI1_MISO, 1); - spi_bus = &swm320_spi_bus1; - swm320_spi = &swm320_spi1; - } - else - { - return -1; - } - swm320_spi->swm320_spi = SPIx; - spi_bus->parent.user_data = swm320_spi; - return rt_spi_bus_register(spi_bus, name, &swm320_spi_ops); + return swm_spi_init(spi_drv, configure); } +const static struct rt_spi_ops swm_spi_ops = + { + .configure = swm_spi_configure, + .xfer = swm_spi_xfer, +}; //cannot be used before completion init -static rt_err_t swm320_spi_bus_attach_device(rt_uint32_t pin, - const char *bus_name, - const char *device_name) +rt_err_t rt_hw_spi_device_attach(const char *bus_name, const char *device_name, GPIO_TypeDef *cs_gpiox, uint32_t cs_gpio_pin) { - struct rt_spi_device *spi_device = (struct rt_spi_device *)rt_malloc(sizeof(struct rt_spi_device)); + RT_ASSERT(bus_name != RT_NULL); + RT_ASSERT(device_name != RT_NULL); + + rt_err_t result; + struct rt_spi_device *spi_device; + struct swm_spi_cs *cs_pin; + + GPIO_Init(cs_gpiox, cs_gpio_pin, 1, 0, 0); + GPIO_SetBit(cs_gpiox, cs_gpio_pin); + + spi_device = (struct rt_spi_device *)rt_malloc(sizeof(struct rt_spi_device)); RT_ASSERT(spi_device != RT_NULL); - struct swm320_spi_cs *cs_pin = (struct swm320_spi_cs *)rt_malloc(sizeof(struct swm320_spi_cs)); + cs_pin = (struct swm_spi_cs *)rt_malloc(sizeof(struct swm_spi_cs)); RT_ASSERT(cs_pin != RT_NULL); - cs_pin->pin = pin; - rt_pin_mode(pin, PIN_MODE_OUTPUT); - rt_pin_write(pin, 1); - return rt_spi_bus_attach_device(spi_device, - device_name, - bus_name, - (void *)cs_pin); + cs_pin->GPIOx = cs_gpiox; + cs_pin->gpio_pin = cs_gpio_pin; + + result = rt_spi_bus_attach_device(spi_device, device_name, bus_name, (void *)cs_pin); + if (result != RT_EOK) + { + LOG_E("%s attach to %s faild, %d\n", device_name, bus_name, result); + } + RT_ASSERT(result == RT_EOK); + LOG_D("%s attach to %s done", device_name, bus_name); + return result; } int rt_hw_spi_init(void) { - int result = 0; + rt_err_t result; + #ifdef BSP_USING_SPI0 - result = swm320_spi_register_bus(SPI0, "spi0"); -#endif + PORT_Init(PORTP, PIN23, FUNMUX1_SPI0_SCLK, 0); + PORT_Init(PORTP, PIN18, FUNMUX0_SPI0_MOSI, 0); + PORT_Init(PORTP, PIN19, FUNMUX1_SPI0_MISO, 1); +#endif //BSP_USING_SPI0 + #ifdef BSP_USING_SPI1 - result = swm320_spi_register_bus(SPI1, "spi1"); -#endif + PORT_Init(PORTB, PIN1, FUNMUX1_SPI1_SCLK, 0); + PORT_Init(PORTB, PIN2, FUNMUX0_SPI1_MOSI, 0); + PORT_Init(PORTB, PIN3, FUNMUX1_SPI1_MISO, 1); +#endif //BSP_USING_SPI1 + for (int i = 0; i < sizeof(spi_cfg) / sizeof(spi_cfg[0]); i++) + { + spi_bus_drv[i].cfg = &spi_cfg[i]; + spi_bus_drv[i].spi_bus.parent.user_data = &spi_cfg[i]; + result = rt_spi_bus_register(&spi_bus_drv[i].spi_bus, spi_cfg[i].name, &swm_spi_ops); + RT_ASSERT(result == RT_EOK); + + LOG_D("%s bus init done", spi_config[i].bus_name); + } + return result; } INIT_BOARD_EXPORT(rt_hw_spi_init); + +#endif /* BSP_USING_SPI */ +#endif /* RT_USING_SPI */ diff --git a/bsp/swm320-lq100/drivers/drv_spi.h b/bsp/swm320-lq100/drivers/drv_spi.h index 7e5366ab58..7af96779d2 100644 --- a/bsp/swm320-lq100/drivers/drv_spi.h +++ b/bsp/swm320-lq100/drivers/drv_spi.h @@ -6,22 +6,75 @@ * Change Logs: * Date Author Notes * 2018-12-10 Zohar_Lee first version + * 2020-07-10 lik rewrite */ -#ifndef DRV_SPI_H__ -#define DRV_SPI_H__ +#ifndef __DRV_SPI_H__ +#define __DRV_SPI_H__ -#include <rtthread.h> +#include "board.h" -struct swm320_spi_cs +struct swm_spi_cs { - rt_uint32_t pin; + GPIO_TypeDef *GPIOx; + uint32_t gpio_pin; }; +struct swm_spi_cfg +{ + const char *name; + SPI_TypeDef *SPIx; + SPI_InitStructure spi_initstruct; +}; + +/* swm spi dirver class */ +struct swm_spi +{ + struct swm_spi_cfg *cfg; + struct rt_spi_configuration *configure; + struct rt_spi_bus spi_bus; +}; + +#ifdef BSP_USING_SPI0 +#ifndef SPI0_BUS_CONFIG +#define SPI0_BUS_CONFIG \ + { \ + .name = "spi0", \ + .SPIx = SPI0, \ + .spi_initstruct.clkDiv = SPI_CLKDIV_32, \ + .spi_initstruct.FrameFormat = SPI_FORMAT_SPI, \ + .spi_initstruct.SampleEdge = SPI_SECOND_EDGE, \ + .spi_initstruct.IdleLevel = SPI_HIGH_LEVEL, \ + .spi_initstruct.WordSize = 8, \ + .spi_initstruct.Master = 1, \ + .spi_initstruct.RXHFullIEn = 0, \ + .spi_initstruct.TXEmptyIEn = 0, \ + .spi_initstruct.TXCompleteIEn = 0, \ + } +#endif /* SPI1_BUS_CONFIG */ +#endif /* BSP_USING_SPI1 */ + +#ifdef BSP_USING_SPI1 +#ifndef SPI1_BUS_CONFIG +#define SPI1_BUS_CONFIG \ + { \ + .name = "spi1", \ + .SPIx = SPI1, \ + .spi_initstruct.clkDiv = SPI_CLKDIV_32, \ + .spi_initstruct.FrameFormat = SPI_FORMAT_SPI, \ + .spi_initstruct.SampleEdge = SPI_SECOND_EDGE, \ + .spi_initstruct.IdleLevel = SPI_HIGH_LEVEL, \ + .spi_initstruct.WordSize = 8, \ + .spi_initstruct.Master = 1, \ + .spi_initstruct.RXHFullIEn = 0, \ + .spi_initstruct.TXEmptyIEn = 0, \ + .spi_initstruct.TXCompleteIEn = 0, \ + } +#endif /* SPI1_BUS_CONFIG */ +#endif /* BSP_USING_SPI1 */ + //cannot be used before completion init -static rt_err_t swm320_spi_bus_attach_device(rt_uint32_t pin, - const char *bus_name, - const char *device_name); +rt_err_t rt_hw_spi_device_attach(const char *bus_name, const char *device_name, GPIO_TypeDef *GPIOx, uint32_t n); int rt_hw_spi_init(void); -#endif +#endif /* __DRV_SPI_H__ */ diff --git a/bsp/swm320-lq100/drivers/drv_sram.c b/bsp/swm320-lq100/drivers/drv_sram.c index b23c76beac..90c2d94676 100644 --- a/bsp/swm320-lq100/drivers/drv_sram.c +++ b/bsp/swm320-lq100/drivers/drv_sram.c @@ -7,40 +7,44 @@ * Date Author Notes * 2018-05-31 ZYH first version * 2018-12-10 Zohar_Lee format file + * 2020-07-10 lik rewrite */ -#include <board.h> -#include <rtthread.h> -#include <rtdevice.h> -#include <SWM320_port.h> -#include <rthw.h> +#include "drv_sram.h" -int rt_hw_sram_init(void) -{ - int i; - PORT->PORTP_SEL0 = 0xAAAAAAAA; /* PP0-23 => ADDR0-23 */ - PORT->PORTP_SEL1 = 0xAAAA; - PORT->PORTM_SEL0 = 0xAAAAAAAA; /* PM0-15 => DATA15-0 */ - PORT->PORTM_INEN |= 0xFFFF; - PORT->PORTM_SEL1 = 0x2AA; /* PM16 => OEN、PM17 => WEN、PM18 => NORFL_CSN、PM19 => SDRAM_CSN、PM20 => SRAM_CSN、PM21 => SDRAM_CKE */ +#ifdef BSP_USING_EXT_SRAM - /* 配置SRAM前需要刷新下SDRAM控制器 */ +#define DRV_DEBUG +#define LOG_TAG "drv.ext_sram" +#include <drv_log.h> - SYS->CLKEN |= (1 << SYS_CLKEN_SDRAM_Pos); +#ifdef RT_USING_MEMHEAP_AS_HEAP +static struct rt_memheap system_heap; +#endif - while (SDRAMC->REFDONE == 0); - SDRAMC->REFRESH &= ~(1 << SDRAMC_REFRESH_EN_Pos); +static int rt_hw_sram_init(void) +{ + SRAM_InitStructure SRAM_InitStruct; - for (i = 0; i < 1000; i++) - { - } - SYS->CLKEN &= ~(1 << SYS_CLKEN_SDRAM_Pos); + PORT->PORTP_SEL0 = 0xAAAAAAAA; //PP0-23 => ADDR0-23 + PORT->PORTP_SEL1 = 0xAAAA; - SYS->CLKEN |= (1 << SYS_CLKEN_RAMC_Pos); + PORT->PORTM_SEL0 = 0xAAAAAAAA; //PM0-15 => DATA15-0 + PORT->PORTM_INEN = 0xFFFF; - SRAMC->CR = (9 << SRAMC_CR_RWTIME_Pos) | - (0 << SRAMC_CR_BYTEIF_Pos) | // 16位接口 - (0 << SRAMC_CR_HBLBDIS_Pos); // 使能字节、半字访问 + PORT->PORTM_SEL1 = 0xAAA; //PM16 => OEN,PM17 => WEN,PM18 => NORFL_CSN,PM19 => SDRAM_CSN,PM20 => SRAM_CSN,PM21 => SDRAM_CKE + + SRAM_InitStruct.ClkDiv = SRAM_CLKDIV_8; + SRAM_InitStruct.DataWidth = SRAM_DATAWIDTH_16; + SRAM_Init(&SRAM_InitStruct); + +#ifdef RT_USING_MEMHEAP_AS_HEAP + /* If RT_USING_MEMHEAP_AS_HEAP is enabled, SRAM is initialized to the heap */ + rt_memheap_init(&system_heap, "sram", (void *)EXT_SRAM_BEGIN, EXT_SRAM_SIZE); +#endif return 0; } +INIT_BOARD_EXPORT(rt_hw_sram_init); + +#endif /* BSP_USING_EXT_SRAM */ diff --git a/bsp/swm320-lq100/drivers/drv_sram.h b/bsp/swm320-lq100/drivers/drv_sram.h index 5f81319733..043de498e2 100644 --- a/bsp/swm320-lq100/drivers/drv_sram.h +++ b/bsp/swm320-lq100/drivers/drv_sram.h @@ -6,11 +6,19 @@ * Change Logs: * Date Author Notes * 2018-12-10 Zohar_Lee first version + * 2020-07-10 lik rewrite */ #ifndef DRV_SRAM_H__ #define DRV_SRAM_H__ +#include "board.h" + +#define EXT_SRAM_BASE SRAMM_BASE +#define EXT_SRAM_SIZE BSP_EXT_SRAM_SIZE +#define EXT_SRAM_BEGIN EXT_SRAM_BASE +#define EXT_SRAM_END (EXT_SRAM_BASE + EXT_SRAM_SIZE) + int rt_hw_sram_init(void); #endif diff --git a/bsp/swm320-lq100/drivers/drv_uart.c b/bsp/swm320-lq100/drivers/drv_uart.c index fe02c4da55..d193eb1238 100644 --- a/bsp/swm320-lq100/drivers/drv_uart.c +++ b/bsp/swm320-lq100/drivers/drv_uart.c @@ -7,193 +7,253 @@ * Date Author Notes * 2018-05-31 ZYH first version * 2018-12-10 Zohar_Lee format file + * 2020-07-10 lik format file */ -#include <rtthread.h> -#include <rtdevice.h> -#include <board.h> -#include <SWM320_port.h> -#include <SWM320_uart.h> +#include "drv_uart.h" -struct swm320_uart +#ifdef RT_USING_SERIAL +#ifdef BSP_USING_UART + +//#define DRV_DEBUG +#define LOG_TAG "drv.uart" +#include <drv_log.h> + +#if !defined(BSP_USING_UART0) && !defined(BSP_USING_UART1) && !defined(BSP_USING_UART2) && \ + !defined(BSP_USING_UART3) +#error "Please define at least one BSP_USING_UARTx" +/* this driver can be disabled at menuconfig -> RT-Thread Components -> Device Drivers */ +#endif + +enum { - UART_TypeDef *uart; - IRQn_Type irq; +#ifdef BSP_USING_UART0 + UART0_INDEX, +#endif +#ifdef BSP_USING_UART1 + UART1_INDEX, +#endif +#ifdef BSP_USING_UART2 + UART2_INDEX, +#endif +#ifdef BSP_USING_UART3 + UART3_INDEX, +#endif +}; + +static struct swm_uart_cfg uart_cfg[] = + { +#ifdef BSP_USING_UART0 + UART0_CFG, +#endif +#ifdef BSP_USING_UART1 + UART1_CFG, +#endif +#ifdef BSP_USING_UART2 + UART2_CFG, +#endif +#ifdef BSP_USING_UART3 + UART3_CFG, +#endif }; -static rt_err_t swm320_uart_configure(struct rt_serial_device *serial, - struct serial_configure *cfg) +static struct swm_uart uart_drv[sizeof(uart_cfg) / sizeof(uart_cfg[0])] = {0}; + +static rt_err_t swm_uart_init(struct rt_serial_device *serial_device, struct serial_configure *configure) { - struct swm320_uart *uart; - UART_InitStructure UART_initStruct; - RT_ASSERT(serial != RT_NULL); - RT_ASSERT(cfg != RT_NULL); - uart = (struct swm320_uart *)serial->parent.user_data; - NVIC_DisableIRQ(uart->irq); - UART_initStruct.Baudrate = cfg->baud_rate; - UART_initStruct.RXThreshold = 1; - UART_initStruct.RXThresholdIEn = 1; - UART_initStruct.TXThresholdIEn = 0; - UART_initStruct.TimeoutTime = 10; - UART_initStruct.TimeoutIEn = 0; - switch (cfg->data_bits) + struct swm_uart_cfg *cfg; + RT_ASSERT(serial_device != RT_NULL); + RT_ASSERT(configure != RT_NULL); + cfg = serial_device->parent.user_data; + + cfg->uart_initstruct.Baudrate = configure->baud_rate; + switch (configure->data_bits) { + case DATA_BITS_8: + cfg->uart_initstruct.DataBits = UART_DATA_8BIT; + break; case DATA_BITS_9: - UART_initStruct.DataBits = UART_DATA_9BIT; + cfg->uart_initstruct.DataBits = UART_DATA_9BIT; break; default: - UART_initStruct.DataBits = UART_DATA_8BIT; + cfg->uart_initstruct.DataBits = UART_DATA_8BIT; break; } - switch (cfg->stop_bits) + switch (configure->stop_bits) { + case STOP_BITS_1: + cfg->uart_initstruct.StopBits = UART_STOP_1BIT; + break; case STOP_BITS_2: - UART_initStruct.StopBits = UART_STOP_2BIT; + cfg->uart_initstruct.StopBits = UART_STOP_2BIT; break; default: - UART_initStruct.StopBits = UART_STOP_1BIT; + cfg->uart_initstruct.StopBits = UART_STOP_1BIT; break; } - switch (cfg->parity) + switch (configure->parity) { + case PARITY_NONE: + cfg->uart_initstruct.Parity = UART_PARITY_NONE; + break; case PARITY_ODD: - UART_initStruct.Parity = UART_PARITY_ODD; + cfg->uart_initstruct.Parity = UART_PARITY_ODD; break; case PARITY_EVEN: - UART_initStruct.Parity = UART_PARITY_EVEN; + cfg->uart_initstruct.Parity = UART_PARITY_EVEN; + break; + default: + cfg->uart_initstruct.Parity = UART_PARITY_NONE; + break; + } + switch ((uint32_t)cfg->UARTx) + { + case ((uint32_t)UART0): + PORT_Init(PORTA, PIN2, FUNMUX0_UART0_RXD, 1); + PORT_Init(PORTA, PIN3, FUNMUX1_UART0_TXD, 0); + break; + case ((uint32_t)UART1): + PORT_Init(PORTC, PIN2, FUNMUX0_UART1_RXD, 1); + PORT_Init(PORTC, PIN3, FUNMUX1_UART1_TXD, 0); + break; + case ((uint32_t)UART2): + PORT_Init(PORTC, PIN4, FUNMUX0_UART2_RXD, 1); + PORT_Init(PORTC, PIN5, FUNMUX1_UART2_TXD, 0); + break; + case ((uint32_t)UART3): + PORT_Init(PORTC, PIN6, FUNMUX0_UART3_RXD, 1); + PORT_Init(PORTC, PIN7, FUNMUX1_UART3_TXD, 0); break; default: - UART_initStruct.Parity = UART_PARITY_NONE; break; } - UART_Init(uart->uart, &UART_initStruct); - UART_Open(uart->uart); + UART_Init(cfg->UARTx, &(cfg->uart_initstruct)); + UART_Open(cfg->UARTx); return RT_EOK; } -static rt_err_t swm320_uart_control(struct rt_serial_device *serial, - int cmd, void *arg) +static rt_err_t swm_uart_control(struct rt_serial_device *serial_device, int cmd, void *arg) { - struct swm320_uart *uart; - RT_ASSERT(serial != RT_NULL); - uart = (struct swm320_uart *)serial->parent.user_data; + struct swm_uart_cfg *cfg; + RT_ASSERT(serial_device != RT_NULL); + cfg = serial_device->parent.user_data; + switch (cmd) { case RT_DEVICE_CTRL_CLR_INT: /* disable rx irq */ - NVIC_DisableIRQ(uart->irq); + NVIC_DisableIRQ(cfg->irq); break; case RT_DEVICE_CTRL_SET_INT: /* enable rx irq */ - NVIC_EnableIRQ(uart->irq); + NVIC_EnableIRQ(cfg->irq); break; } return RT_EOK; } -static int swm320_uart_putc(struct rt_serial_device *serial, char c) +static int swm_uart_putc(struct rt_serial_device *serial_device, char c) { - struct swm320_uart *uart; - RT_ASSERT(serial != RT_NULL); - uart = (struct swm320_uart *)serial->parent.user_data; - while (UART_IsTXBusy(uart->uart)); - uart->uart->DATA = c; + struct swm_uart_cfg *cfg; + RT_ASSERT(serial_device != RT_NULL); + cfg = serial_device->parent.user_data; + + while (UART_IsTXFIFOFull(cfg->UARTx)) + ; + UART_WriteByte(cfg->UARTx, c); + while (UART_IsTXBusy(cfg->UARTx)) + ; return 1; } -static int swm320_uart_getc(struct rt_serial_device *serial) +static int swm_uart_getc(struct rt_serial_device *serial_device) { int ch; - struct swm320_uart *uart; - RT_ASSERT(serial != RT_NULL); - uart = (struct swm320_uart *)serial->parent.user_data; + struct swm_uart_cfg *cfg; + RT_ASSERT(serial_device != RT_NULL); + cfg = serial_device->parent.user_data; + ch = -1; - if (UART_IsRXFIFOEmpty(uart->uart) == 0) + if (UART_IsRXFIFOEmpty(cfg->UARTx) == 0) { - UART_ReadByte(uart->uart, (uint32_t *)&ch); + UART_ReadByte(cfg->UARTx, (uint32_t *)&ch); } return ch; } -static const struct rt_uart_ops swm320_uart_ops = +static const struct rt_uart_ops swm_uart_ops = + { + .configure = swm_uart_init, + .control = swm_uart_control, + .putc = swm_uart_putc, + .getc = swm_uart_getc, + .dma_transmit = RT_NULL}; + +/** + * Uart common interrupt process. This need add to uart ISR. + * + * @param serial serial device + */ +static void rt_hw_uart_isr(struct rt_serial_device *serial_device) { - swm320_uart_configure, - swm320_uart_control, - swm320_uart_putc, - swm320_uart_getc, -}; + struct swm_uart_cfg *cfg; + RT_ASSERT(serial_device != RT_NULL); + cfg = serial_device->parent.user_data; + + /* UART in mode Receiver -------------------------------------------------*/ + if (UART_INTRXThresholdStat(cfg->UARTx) || UART_INTTimeoutStat(cfg->UARTx)) + { + rt_hw_serial_isr(serial_device, RT_SERIAL_EVENT_RX_IND); + } +} #if defined(BSP_USING_UART0) -/* UART0 device driver structure */ -static struct swm320_uart uart0; -static struct rt_serial_device serial0; void UART0_Handler(void) { /* enter interrupt */ rt_interrupt_enter(); - /* UART in mode Receiver */ - if (UART_INTRXThresholdStat(uart0.uart) || UART_INTTimeoutStat(uart0.uart)) - { - rt_hw_serial_isr(&serial0, RT_SERIAL_EVENT_RX_IND); - } + rt_hw_uart_isr(&(uart_drv[UART0_INDEX].serial_device)); + /* leave interrupt */ rt_interrupt_leave(); } #endif /* BSP_USING_UART0 */ #if defined(BSP_USING_UART1) -/* UART1 device driver structure */ -static struct swm320_uart uart1; -static struct rt_serial_device serial1; void UART1_Handler(void) { /* enter interrupt */ rt_interrupt_enter(); - /* UART in mode Receiver */ - if (UART_INTRXThresholdStat(uart1.uart) || UART_INTTimeoutStat(uart1.uart)) - { - rt_hw_serial_isr(&serial1, RT_SERIAL_EVENT_RX_IND); - } + rt_hw_uart_isr(&(uart_drv[UART1_INDEX].serial_device)); + /* leave interrupt */ rt_interrupt_leave(); } #endif /* BSP_USING_UART1 */ #if defined(BSP_USING_UART2) -/* UART2 device driver structure */ -static struct swm320_uart uart2; -static struct rt_serial_device serial2; void UART2_Handler(void) { /* enter interrupt */ rt_interrupt_enter(); - /* UART in mode Receiver */ - if (UART_INTRXThresholdStat(uart2.uart) || UART_INTTimeoutStat(uart2.uart)) - { - rt_hw_serial_isr(&serial2, RT_SERIAL_EVENT_RX_IND); - } + rt_hw_uart_isr(&(uart_drv[UART2_INDEX].serial_device)); + /* leave interrupt */ rt_interrupt_leave(); } #endif /* BSP_USING_UART2 */ #if defined(BSP_USING_UART3) -/* UART3 device driver structure */ -static struct swm320_uart uart3; -static struct rt_serial_device serial3; void UART3_Handler(void) { /* enter interrupt */ rt_interrupt_enter(); - /* UART in mode Receiver */ - if (UART_INTRXThresholdStat(uart3.uart) || UART_INTTimeoutStat(uart3.uart)) - { - rt_hw_serial_isr(&serial3, RT_SERIAL_EVENT_RX_IND); - } + rt_hw_uart_isr(&(uart_drv[UART3_INDEX].serial_device)); + /* leave interrupt */ rt_interrupt_leave(); } @@ -201,60 +261,24 @@ void UART3_Handler(void) int rt_hw_uart_init(void) { - struct swm320_uart *uart; - struct serial_configure config = RT_SERIAL_CONFIG_DEFAULT; -#ifdef BSP_USING_UART0 - PORT_Init(PORTA, PIN2, FUNMUX0_UART0_RXD, 1); - PORT_Init(PORTA, PIN3, FUNMUX1_UART0_TXD, 0); - uart = &uart0; - uart->uart = UART0; - uart->irq = UART0_IRQn; - serial0.ops = &swm320_uart_ops; - serial0.config = config; - /* register UART0 device */ - rt_hw_serial_register(&serial0, "uart0", - RT_DEVICE_FLAG_RDWR | RT_DEVICE_FLAG_INT_RX, - uart); -#endif /* BSP_USING_UART0 */ -#ifdef BSP_USING_UART1 - PORT_Init(PORTC, PIN2, FUNMUX0_UART1_RXD, 1); - PORT_Init(PORTC, PIN3, FUNMUX1_UART1_TXD, 0); - uart = &uart1; - uart->uart = UART1; - uart->irq = UART1_IRQn; - serial1.ops = &swm320_uart_ops; - serial1.config = config; - /* register UART1 device */ - rt_hw_serial_register(&serial1, "uart1", - RT_DEVICE_FLAG_RDWR | RT_DEVICE_FLAG_INT_RX, - uart); -#endif /* BSP_USING_UART1 */ -#ifdef BSP_USING_UART2 - PORT_Init(PORTC, PIN4, FUNMUX0_UART2_RXD, 1); - PORT_Init(PORTC, PIN5, FUNMUX1_UART2_TXD, 0); - uart = &uart2; - uart->uart = UART2; - uart->irq = UART2_IRQn; - serial2.ops = &swm320_uart_ops; - serial2.config = config; - /* register UART2 device */ - rt_hw_serial_register(&serial2, "uart2", - RT_DEVICE_FLAG_RDWR | RT_DEVICE_FLAG_INT_RX, - uart); -#endif /* BSP_USING_UART2 */ -#ifdef BSP_USING_UART3 - PORT_Init(PORTC, PIN6, FUNMUX0_UART3_RXD, 1); - PORT_Init(PORTC, PIN7, FUNMUX1_UART3_TXD, 0); - uart = &uart3; - uart->uart = UART3; - uart->irq = UART3_IRQn; - serial3.ops = &swm320_uart_ops; - serial3.config = config; - /* register UART3 device */ - rt_hw_serial_register(&serial3, "uart3", - RT_DEVICE_FLAG_RDWR | RT_DEVICE_FLAG_INT_RX, - uart); -#endif /* BSP_USING_UART3 */ - return 0; + struct serial_configure cfg = RT_SERIAL_CONFIG_DEFAULT; + int i = 0; + rt_err_t result = RT_EOK; + + for (i = 0; i < sizeof(uart_cfg) / sizeof(uart_cfg[0]); i++) + { + uart_drv[i].cfg = &uart_cfg[i]; + uart_drv[i].serial_device.ops = &swm_uart_ops; + uart_drv[i].serial_device.config = cfg; + /* register UART device */ + result = rt_hw_serial_register(&uart_drv[i].serial_device, uart_drv[i].cfg->name, + RT_DEVICE_FLAG_RDWR | RT_DEVICE_FLAG_INT_RX, uart_drv[i].cfg); + RT_ASSERT(result == RT_EOK); + } + + return result; } INIT_BOARD_EXPORT(rt_hw_uart_init); + +#endif /* BSP_USING_UART */ +#endif /* RT_USING_SERIAL */ diff --git a/bsp/swm320-lq100/drivers/drv_uart.h b/bsp/swm320-lq100/drivers/drv_uart.h index 67193a45d4..66c6535a5b 100644 --- a/bsp/swm320-lq100/drivers/drv_uart.h +++ b/bsp/swm320-lq100/drivers/drv_uart.h @@ -6,11 +6,110 @@ * Change Logs: * Date Author Notes * 2018-12-10 Zohar_Lee first version + * 2020-07-10 lik rewrite */ -#ifndef DRV_UART_H__ -#define DRV_UART_H__ +#ifndef __DRV_UART_H__ +#define __DRV_UART_H__ -int rt_hw_uart_init(void); +#include "board.h" -#endif +/* swm config class */ +struct swm_uart_cfg +{ + const char *name; + UART_TypeDef *UARTx; + IRQn_Type irq; + UART_InitStructure uart_initstruct; +}; + +/* swm uart dirver class */ +struct swm_uart +{ + struct swm_uart_cfg *cfg; + struct rt_serial_device serial_device; +}; + +#ifdef BSP_USING_UART0 +#ifndef UART0_CFG +#define UART0_CFG \ + { \ + .name = "uart0", \ + .UARTx = UART0, \ + .irq = UART0_IRQn, \ + .uart_initstruct.Baudrate = 115200, \ + .uart_initstruct.DataBits = UART_DATA_8BIT, \ + .uart_initstruct.Parity = UART_PARITY_NONE, \ + .uart_initstruct.StopBits = UART_STOP_1BIT, \ + .uart_initstruct.RXThreshold = 0, \ + .uart_initstruct.RXThresholdIEn = 1, \ + .uart_initstruct.TXThresholdIEn = 0, \ + .uart_initstruct.TimeoutTime = 10, \ + .uart_initstruct.TimeoutIEn = 1, \ + } +#endif /* UART0_CFG */ +#endif /* BSP_USING_UART0 */ + +#ifdef BSP_USING_UART1 +#ifndef UART1_CFG +#define UART1_CFG \ + { \ + .name = "uart1", \ + .UARTx = UART1, \ + .irq = UART1_IRQn, \ + .uart_initstruct.Baudrate = 115200, \ + .uart_initstruct.DataBits = UART_DATA_8BIT, \ + .uart_initstruct.Parity = UART_PARITY_NONE, \ + .uart_initstruct.StopBits = UART_STOP_1BIT, \ + .uart_initstruct.RXThreshold = 0, \ + .uart_initstruct.RXThresholdIEn = 1, \ + .uart_initstruct.TXThresholdIEn = 0, \ + .uart_initstruct.TimeoutTime = 10, \ + .uart_initstruct.TimeoutIEn = 1, \ + } +#endif /* UART1_CFG */ +#endif /* BSP_USING_UART1 */ + +#ifdef BSP_USING_UART2 +#ifndef UART2_CFG +#define UART2_CFG \ + { \ + .name = "uart2", \ + .UARTx = UART2, \ + .irq = UART2_IRQn, \ + .uart_initstruct.Baudrate = 115200, \ + .uart_initstruct.DataBits = UART_DATA_8BIT, \ + .uart_initstruct.Parity = UART_PARITY_NONE, \ + .uart_initstruct.StopBits = UART_STOP_1BIT, \ + .uart_initstruct.RXThreshold = 0, \ + .uart_initstruct.RXThresholdIEn = 1, \ + .uart_initstruct.TXThresholdIEn = 0, \ + .uart_initstruct.TimeoutTime = 10, \ + .uart_initstruct.TimeoutIEn = 1, \ + } +#endif /* UART2_CFG */ +#endif /* BSP_USING_UART2 */ + +#ifdef BSP_USING_UART3 +#ifndef UART3_CFG +#define UART3_CFG \ + { \ + .name = "uart3", \ + .UARTx = UART3, \ + .irq = UART3_IRQn, \ + .uart_initstruct.Baudrate = 115200, \ + .uart_initstruct.DataBits = UART_DATA_8BIT, \ + .uart_initstruct.Parity = UART_PARITY_NONE, \ + .uart_initstruct.StopBits = UART_STOP_1BIT, \ + .uart_initstruct.RXThreshold = 0, \ + .uart_initstruct.RXThresholdIEn = 1, \ + .uart_initstruct.TXThresholdIEn = 0, \ + .uart_initstruct.TimeoutTime = 10, \ + .uart_initstruct.TimeoutIEn = 1, \ + } +#endif /* UART3_CFG */ +#endif /* BSP_USING_UART3 */ + +int rt_hw_serial_init(void); + +#endif /* __DRV_UART_H__ */ diff --git a/bsp/swm320-lq100/drivers/drv_wdt.c b/bsp/swm320-lq100/drivers/drv_wdt.c new file mode 100644 index 0000000000..36d5fde26d --- /dev/null +++ b/bsp/swm320-lq100/drivers/drv_wdt.c @@ -0,0 +1,88 @@ +/* + * Copyright (c) 2006-2018, Synwit Technology Co.,Ltd. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Change Logs: + * Date Author Notes + * 2018-12-10 Zohar_Lee first version + * 2020-07-10 lik format file + */ + +#include "drv_wdt.h" + +#ifdef RT_USING_WDT +#ifdef BSP_USING_WDT +//#define DRV_DEBUG +#define LOG_TAG "drv.wdt" +#include <drv_log.h> + +static struct swm_wdt_cfg wdt_cfg = + { + .name = "wdt", + .WDTx = WDT, +}; + +static struct swm_wdt wdt_drv; + +static rt_err_t swm_wdt_init(rt_watchdog_t *wdt_device) +{ + return RT_EOK; +} + +static rt_err_t swm_wdt_control(rt_watchdog_t *wdt_device, int cmd, void *arg) +{ + struct swm_wdt_cfg *cfg; + RT_ASSERT(wdt_device != RT_NULL); + cfg = wdt_device->parent.user_data; + + switch (cmd) + { + case RT_DEVICE_CTRL_WDT_KEEPALIVE: + WDT_Feed(cfg->WDTx); + break; + case RT_DEVICE_CTRL_WDT_SET_TIMEOUT: + WDT_Init(cfg->WDTx, (SystemCoreClock * (*(rt_uint32_t *)arg)), WDT_MODE_RESET); + break; + case RT_DEVICE_CTRL_WDT_GET_TIMEOUT: + *(rt_uint32_t *)arg = (cfg->WDTx->LOAD) / SystemCoreClock; + break; + case RT_DEVICE_CTRL_WDT_GET_TIMELEFT: + *(rt_uint32_t *)arg = WDT_GetValue(cfg->WDTx) / SystemCoreClock; + break; + case RT_DEVICE_CTRL_WDT_START: + WDT_Start(cfg->WDTx); + break; + case RT_DEVICE_CTRL_WDT_STOP: + WDT_Stop(cfg->WDTx); + break; + default: + LOG_W("This command is not supported."); + return -RT_ERROR; + } + + return RT_EOK; +} + +const static struct rt_watchdog_ops swm_wdt_ops = + { + swm_wdt_init, + swm_wdt_control}; + +int rt_hw_wdt_init(void) +{ + wdt_drv.cfg = &wdt_cfg; + wdt_drv.wdt_device.ops = &swm_wdt_ops; + + if (rt_hw_watchdog_register(&wdt_drv.wdt_device, wdt_drv.cfg->name, RT_DEVICE_FLAG_RDWR, wdt_drv.cfg) != RT_EOK) + { + LOG_E("wdt device register failed."); + return -RT_ERROR; + } + LOG_D("wdt device register success."); + return RT_EOK; +} +INIT_BOARD_EXPORT(rt_hw_wdt_init); + +#endif /* BSP_USING_WDT */ +#endif /* RT_USING_WDT */ diff --git a/bsp/swm320-lq100/drivers/drv_wdt.h b/bsp/swm320-lq100/drivers/drv_wdt.h new file mode 100644 index 0000000000..28be110f01 --- /dev/null +++ b/bsp/swm320-lq100/drivers/drv_wdt.h @@ -0,0 +1,31 @@ +/* + * Copyright (c) 2006-2018, Synwit Technology Co.,Ltd. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Change Logs: + * Date Author Notes + * 2018-12-10 Zohar_Lee first version + * 2020-07-10 lik rewrite + */ + +#ifndef __DRV_WDT_H__ +#define __DRV_WDT_H__ + +#include "board.h" + +struct swm_wdt_cfg +{ + const char *name; + WDT_TypeDef *WDTx; +}; + +struct swm_wdt +{ + struct swm_wdt_cfg *cfg; + struct rt_watchdog_device wdt_device; +}; + +int rt_hw_wdt_init(void); + +#endif /* __DRV_WDT_H__ */ diff --git a/bsp/swm320-lq100/keilkill.bat b/bsp/swm320-lq100/keilkill.bat new file mode 100644 index 0000000000..52d5f3375a --- /dev/null +++ b/bsp/swm320-lq100/keilkill.bat @@ -0,0 +1,37 @@ +del *.bak /s
+del *.ddk /s
+del *.edk /s
+del *.lst /s
+::del *.lnp /s
+del *.mpf /s
+del *.mpj /s
+del *.obj /s
+del *.omf /s
+::del *.opt /s ::不允许删除JLINK的设置
+del *.plg /s
+del *.rpt /s
+del *.tmp /s
+::del *.__i /s
+::del *._ia /s
+del *.crf /s
+del *.o /s
+del *.d /s
+del *.axf /s
+del *.tra /s
+del *.dep /s
+::del JLinkLog.txt /s
+
+del *.iex /s
+del *.htm /s
+::del *.sct /s
+del *.map /s
+
+del *.whsj2 /s
+del *.SYNWIT_Lik /s
+del *.whsj2 /s
+del *.scvd /s
+
+rmdir /s/q .git
+rmdir /s/q .vscode
+
+exit
diff --git a/bsp/swm320-lq100/project.ewd b/bsp/swm320-lq100/project.ewd index 52cc221b07..e94c83ed06 100644 --- a/bsp/swm320-lq100/project.ewd +++ b/bsp/swm320-lq100/project.ewd @@ -44,7 +44,7 @@ </option> <option> <name>MemFile</name> - <state>$TOOLKIT_DIR$\CONFIG\debugger\Synwit\SWM320.ddf</state> + <state>$TOOLKIT_DIR$\CONFIG\debugger\ST\STM32F407ZG.ddf</state> </option> <option> <name>RunToEnable</name> @@ -80,7 +80,7 @@ </option> <option> <name>OCProductVersion</name> - <state>8.20.1.14181</state> + <state>8.11.3.13977</state> </option> <option> <name>OCDynDriverList</name> @@ -88,7 +88,7 @@ </option> <option> <name>OCLastSavedByProductVersion</name> - <state>8.20.1.14181</state> + <state>8.11.3.13977</state> </option> <option> <name>UseFlashLoader</name> @@ -112,7 +112,7 @@ </option> <option> <name>FlashLoadersV3</name> - <state>$TOOLKIT_DIR$\config\flashloader\Synwit\FlashSWM320xE.board</state> + <state>$TOOLKIT_DIR$\config\flashloader\ST\FlashSTM32F4xxx.board</state> </option> <option> <name>OCImagesSuppressCheck1</name> @@ -892,7 +892,7 @@ </option> <option> <name>CCCpuClockEdit</name> - <state></state> + <state>168.0</state> </option> <option> <name>CCSwoClockAuto</name> @@ -1403,11 +1403,11 @@ <loadFlag>1</loadFlag> </plugin> <plugin> - <file>$EW_DIR$\common\plugins\Orti\Orti.ENU.ewplugin</file> + <file>$EW_DIR$\common\plugins\IARProbe\IarProbePlugin.ENU.ewplugin</file> <loadFlag>0</loadFlag> </plugin> <plugin> - <file>$EW_DIR$\common\plugins\TargetAccessServer\TargetAccessServer.ENU.ewplugin</file> + <file>$EW_DIR$\common\plugins\Orti\Orti.ENU.ewplugin</file> <loadFlag>0</loadFlag> </plugin> <plugin> @@ -1495,7 +1495,7 @@ </option> <option> <name>OCProductVersion</name> - <state>8.20.1.14181</state> + <state>8.11.3.13977</state> </option> <option> <name>OCDynDriverList</name> @@ -2818,11 +2818,11 @@ <loadFlag>1</loadFlag> </plugin> <plugin> - <file>$EW_DIR$\common\plugins\Orti\Orti.ENU.ewplugin</file> + <file>$EW_DIR$\common\plugins\IARProbe\IarProbePlugin.ENU.ewplugin</file> <loadFlag>0</loadFlag> </plugin> <plugin> - <file>$EW_DIR$\common\plugins\TargetAccessServer\TargetAccessServer.ENU.ewplugin</file> + <file>$EW_DIR$\common\plugins\Orti\Orti.ENU.ewplugin</file> <loadFlag>0</loadFlag> </plugin> <plugin> diff --git a/bsp/swm320-lq100/project.ewp b/bsp/swm320-lq100/project.ewp index 3c89d9260b..517effb86b 100644 --- a/bsp/swm320-lq100/project.ewp +++ b/bsp/swm320-lq100/project.ewp @@ -1,2289 +1,2231 @@ -<project>
- <fileVersion>3</fileVersion>
- <configuration>
- <name>rt-thread</name>
- <toolchain>
- <name>ARM</name>
- </toolchain>
- <debug>1</debug>
- <settings>
- <name>General</name>
- <archiveVersion>3</archiveVersion>
- <data>
- <version>29</version>
- <wantNonLocal>1</wantNonLocal>
- <debug>1</debug>
- <option>
- <name>ExePath</name>
- <state>build\iar\Exe</state>
- </option>
- <option>
- <name>ObjPath</name>
- <state>build\iar\Obj</state>
- </option>
- <option>
- <name>ListPath</name>
- <state>build\iar\List</state>
- </option>
- <option>
- <name>GEndianMode</name>
- <state>0</state>
- </option>
- <option>
- <name>Input description</name>
- <state>Automatic choice of formatter, without multibyte support.</state>
- </option>
- <option>
- <name>Output description</name>
- <state>Automatic choice of formatter, without multibyte support.</state>
- </option>
- <option>
- <name>GOutputBinary</name>
- <state>0</state>
- </option>
- <option>
- <name>OGCoreOrChip</name>
- <state>1</state>
- </option>
- <option>
- <name>GRuntimeLibSelect</name>
- <version>0</version>
- <state>1</state>
- </option>
- <option>
- <name>GRuntimeLibSelectSlave</name>
- <version>0</version>
- <state>1</state>
- </option>
- <option>
- <name>RTDescription</name>
- <state>Use the normal configuration of the C/C++ runtime library. No locale interface, C locale, no file descriptor support, no multibytes in printf and scanf, and no hex floats in strtod.</state>
- </option>
- <option>
- <name>OGProductVersion</name>
- <state>6.30.6.53380</state>
- </option>
- <option>
- <name>OGLastSavedByProductVersion</name>
- <state>8.11.3.13977</state>
- </option>
- <option>
- <name>GeneralEnableMisra</name>
- <state>0</state>
- </option>
- <option>
- <name>GeneralMisraVerbose</name>
- <state>0</state>
- </option>
- <option>
- <name>OGChipSelectEditMenu</name>
- <state>SWM320xE Synwit SWM320xE</state>
- </option>
- <option>
- <name>GenLowLevelInterface</name>
- <state>1</state>
- </option>
- <option>
- <name>GEndianModeBE</name>
- <state>1</state>
- </option>
- <option>
- <name>OGBufferedTerminalOutput</name>
- <state>0</state>
- </option>
- <option>
- <name>GenStdoutInterface</name>
- <state>0</state>
- </option>
- <option>
- <name>GeneralMisraRules98</name>
- <version>0</version>
- <state>1000111110110101101110011100111111101110011011000101110111101101100111111111111100110011111001110111001111111111111111111111111</state>
- </option>
- <option>
- <name>GeneralMisraVer</name>
- <state>0</state>
- </option>
- <option>
- <name>GeneralMisraRules04</name>
- <version>0</version>
- <state>111101110010111111111000110111111111111111111111111110010111101111010101111111111111111111111111101111111011111001111011111011111111111111111</state>
- </option>
- <option>
- <name>RTConfigPath2</name>
- <state>$TOOLKIT_DIR$\INC\c\DLib_Config_Normal.h</state>
- </option>
- <option>
- <name>GBECoreSlave</name>
- <version>25</version>
- <state>39</state>
- </option>
- <option>
- <name>OGUseCmsis</name>
- <state>0</state>
- </option>
- <option>
- <name>OGUseCmsisDspLib</name>
- <state>0</state>
- </option>
- <option>
- <name>GRuntimeLibThreads</name>
- <state>0</state>
- </option>
- <option>
- <name>CoreVariant</name>
- <version>25</version>
- <state>39</state>
- </option>
- <option>
- <name>GFPUDeviceSlave</name>
- <state>SWM320xE Synwit SWM320xE</state>
- </option>
- <option>
- <name>FPU2</name>
- <version>0</version>
- <state>4</state>
- </option>
- <option>
- <name>NrRegs</name>
- <version>0</version>
- <state>1</state>
- </option>
- <option>
- <name>NEON</name>
- <state>0</state>
- </option>
- <option>
- <name>GFPUCoreSlave2</name>
- <version>25</version>
- <state>39</state>
- </option>
- <option>
- <name>OGCMSISPackSelectDevice</name>
- </option>
- <option>
- <name>OgLibHeap</name>
- <state>0</state>
- </option>
- <option>
- <name>OGLibAdditionalLocale</name>
- <state>0</state>
- </option>
- <option>
- <name>OGPrintfVariant</name>
- <version>0</version>
- <state>0</state>
- </option>
- <option>
- <name>OGPrintfMultibyteSupport</name>
- <state>0</state>
- </option>
- <option>
- <name>OGScanfVariant</name>
- <version>0</version>
- <state>0</state>
- </option>
- <option>
- <name>OGScanfMultibyteSupport</name>
- <state>0</state>
- </option>
- <option>
- <name>GenLocaleTags</name>
- <state />
- </option>
- <option>
- <name>GenLocaleDisplayOnly</name>
- <state />
- </option>
- <option>
- <name>DSPExtension</name>
- <state>1</state>
- </option>
- </data>
- </settings>
- <settings>
- <name>ICCARM</name>
- <archiveVersion>2</archiveVersion>
- <data>
- <version>34</version>
- <wantNonLocal>1</wantNonLocal>
- <debug>1</debug>
- <option>
- <name>CCOptimizationNoSizeConstraints</name>
- <state>0</state>
- </option>
- <option>
- <name>CCDefines</name>
- <state />
- </option>
- <option>
- <name>CCPreprocFile</name>
- <state>0</state>
- </option>
- <option>
- <name>CCPreprocComments</name>
- <state>0</state>
- </option>
- <option>
- <name>CCPreprocLine</name>
- <state>0</state>
- </option>
- <option>
- <name>CCListCFile</name>
- <state>0</state>
- </option>
- <option>
- <name>CCListCMnemonics</name>
- <state>0</state>
- </option>
- <option>
- <name>CCListCMessages</name>
- <state>0</state>
- </option>
- <option>
- <name>CCListAssFile</name>
- <state>0</state>
- </option>
- <option>
- <name>CCListAssSource</name>
- <state>0</state>
- </option>
- <option>
- <name>CCEnableRemarks</name>
- <state>0</state>
- </option>
- <option>
- <name>CCDiagSuppress</name>
- <state>Pa050</state>
- </option>
- <option>
- <name>CCDiagRemark</name>
- <state />
- </option>
- <option>
- <name>CCDiagWarning</name>
- <state />
- </option>
- <option>
- <name>CCDiagError</name>
- <state />
- </option>
- <option>
- <name>CCObjPrefix</name>
- <state>1</state>
- </option>
- <option>
- <name>CCAllowList</name>
- <version>1</version>
- <state>00000000</state>
- </option>
- <option>
- <name>CCDebugInfo</name>
- <state>1</state>
- </option>
- <option>
- <name>IEndianMode</name>
- <state>1</state>
- </option>
- <option>
- <name>IProcessor</name>
- <state>1</state>
- </option>
- <option>
- <name>IExtraOptionsCheck</name>
- <state>0</state>
- </option>
- <option>
- <name>IExtraOptions</name>
- <state />
- </option>
- <option>
- <name>CCLangConformance</name>
- <state>0</state>
- </option>
- <option>
- <name>CCSignedPlainChar</name>
- <state>1</state>
- </option>
- <option>
- <name>CCRequirePrototypes</name>
- <state>0</state>
- </option>
- <option>
- <name>CCDiagWarnAreErr</name>
- <state>0</state>
- </option>
- <option>
- <name>CCCompilerRuntimeInfo</name>
- <state>0</state>
- </option>
- <option>
- <name>IFpuProcessor</name>
- <state>1</state>
- </option>
- <option>
- <name>OutputFile</name>
- <state>$FILE_BNAME$.o</state>
- </option>
- <option>
- <name>CCLibConfigHeader</name>
- <state>1</state>
- </option>
- <option>
- <name>PreInclude</name>
- <state />
- </option>
- <option>
- <name>CompilerMisraOverride</name>
- <state>0</state>
- </option>
- <option>
- <name>CCIncludePath2</name>
- <state />
- <state>$PROJ_DIR$\applications</state>
- <state>$PROJ_DIR$\Libraries\CMSIS\DeviceSupport</state>
- <state>$PROJ_DIR$\Libraries\SWM320_StdPeriph_Driver</state>
- <state>$PROJ_DIR$\drivers</state>
- <state>$PROJ_DIR$\..\..\components\libc\compilers\common</state>
- <state>$PROJ_DIR$\.</state>
- <state>$PROJ_DIR$\..\..\include</state>
- <state>$PROJ_DIR$\..\..\libcpu\arm\cortex-m4</state>
- <state>$PROJ_DIR$\..\..\components\drivers\include</state>
- <state>$PROJ_DIR$\..\..\libcpu\arm\common</state>
- <state>$PROJ_DIR$\..\..\components\finsh</state>
- <state>$PROJ_DIR$\Libraries\CMSIS\CoreSupport</state>
- </option>
- <option>
- <name>CCStdIncCheck</name>
- <state>0</state>
- </option>
- <option>
- <name>CCCodeSection</name>
- <state>.text</state>
- </option>
- <option>
- <name>IProcessorMode2</name>
- <state>1</state>
- </option>
- <option>
- <name>CCOptLevel</name>
- <state>1</state>
- </option>
- <option>
- <name>CCOptStrategy</name>
- <version>0</version>
- <state>0</state>
- </option>
- <option>
- <name>CCOptLevelSlave</name>
- <state>1</state>
- </option>
- <option>
- <name>CompilerMisraRules98</name>
- <version>0</version>
- <state>1000111110110101101110011100111111101110011011000101110111101101100111111111111100110011111001110111001111111111111111111111111</state>
- </option>
- <option>
- <name>CompilerMisraRules04</name>
- <version>0</version>
- <state>111101110010111111111000110111111111111111111111111110010111101111010101111111111111111111111111101111111011111001111011111011111111111111111</state>
- </option>
- <option>
- <name>CCPosIndRopi</name>
- <state>0</state>
- </option>
- <option>
- <name>CCPosIndRwpi</name>
- <state>0</state>
- </option>
- <option>
- <name>CCPosIndNoDynInit</name>
- <state>0</state>
- </option>
- <option>
- <name>IccLang</name>
- <state>0</state>
- </option>
- <option>
- <name>IccCDialect</name>
- <state>1</state>
- </option>
- <option>
- <name>IccAllowVLA</name>
- <state>0</state>
- </option>
- <option>
- <name>IccStaticDestr</name>
- <state>1</state>
- </option>
- <option>
- <name>IccCppInlineSemantics</name>
- <state>0</state>
- </option>
- <option>
- <name>IccCmsis</name>
- <state>1</state>
- </option>
- <option>
- <name>IccFloatSemantics</name>
- <state>0</state>
- </option>
- <option>
- <name>CCNoLiteralPool</name>
- <state>0</state>
- </option>
- <option>
- <name>CCOptStrategySlave</name>
- <version>0</version>
- <state>0</state>
- </option>
- <option>
- <name>CCGuardCalls</name>
- <state>1</state>
- </option>
- <option>
- <name>CCEncSource</name>
- <state>0</state>
- </option>
- <option>
- <name>CCEncOutput</name>
- <state>0</state>
- </option>
- <option>
- <name>CCEncOutputBom</name>
- <state>1</state>
- </option>
- <option>
- <name>CCEncInput</name>
- <state>0</state>
- </option>
- <option>
- <name>IccExceptions2</name>
- <state>0</state>
- </option>
- <option>
- <name>IccRTTI2</name>
- <state>0</state>
- </option>
- </data>
- </settings>
- <settings>
- <name>AARM</name>
- <archiveVersion>2</archiveVersion>
- <data>
- <version>10</version>
- <wantNonLocal>1</wantNonLocal>
- <debug>1</debug>
- <option>
- <name>AObjPrefix</name>
- <state>1</state>
- </option>
- <option>
- <name>AEndian</name>
- <state>1</state>
- </option>
- <option>
- <name>ACaseSensitivity</name>
- <state>1</state>
- </option>
- <option>
- <name>MacroChars</name>
- <version>0</version>
- <state>0</state>
- </option>
- <option>
- <name>AWarnEnable</name>
- <state>0</state>
- </option>
- <option>
- <name>AWarnWhat</name>
- <state>0</state>
- </option>
- <option>
- <name>AWarnOne</name>
- <state />
- </option>
- <option>
- <name>AWarnRange1</name>
- <state />
- </option>
- <option>
- <name>AWarnRange2</name>
- <state />
- </option>
- <option>
- <name>ADebug</name>
- <state>1</state>
- </option>
- <option>
- <name>AltRegisterNames</name>
- <state>0</state>
- </option>
- <option>
- <name>ADefines</name>
- <state />
- </option>
- <option>
- <name>AList</name>
- <state>0</state>
- </option>
- <option>
- <name>AListHeader</name>
- <state>1</state>
- </option>
- <option>
- <name>AListing</name>
- <state>1</state>
- </option>
- <option>
- <name>Includes</name>
- <state>0</state>
- </option>
- <option>
- <name>MacDefs</name>
- <state>0</state>
- </option>
- <option>
- <name>MacExps</name>
- <state>1</state>
- </option>
- <option>
- <name>MacExec</name>
- <state>0</state>
- </option>
- <option>
- <name>OnlyAssed</name>
- <state>0</state>
- </option>
- <option>
- <name>MultiLine</name>
- <state>0</state>
- </option>
- <option>
- <name>PageLengthCheck</name>
- <state>0</state>
- </option>
- <option>
- <name>PageLength</name>
- <state>80</state>
- </option>
- <option>
- <name>TabSpacing</name>
- <state>8</state>
- </option>
- <option>
- <name>AXRef</name>
- <state>0</state>
- </option>
- <option>
- <name>AXRefDefines</name>
- <state>0</state>
- </option>
- <option>
- <name>AXRefInternal</name>
- <state>0</state>
- </option>
- <option>
- <name>AXRefDual</name>
- <state>0</state>
- </option>
- <option>
- <name>AProcessor</name>
- <state>1</state>
- </option>
- <option>
- <name>AFpuProcessor</name>
- <state>1</state>
- </option>
- <option>
- <name>AOutputFile</name>
- <state>$FILE_BNAME$.o</state>
- </option>
- <option>
- <name>ALimitErrorsCheck</name>
- <state>0</state>
- </option>
- <option>
- <name>ALimitErrorsEdit</name>
- <state>100</state>
- </option>
- <option>
- <name>AIgnoreStdInclude</name>
- <state>0</state>
- </option>
- <option>
- <name>AUserIncludes</name>
- <state />
- </option>
- <option>
- <name>AExtraOptionsCheckV2</name>
- <state>0</state>
- </option>
- <option>
- <name>AExtraOptionsV2</name>
- <state />
- </option>
- <option>
- <name>AsmNoLiteralPool</name>
- <state>0</state>
- </option>
- </data>
- </settings>
- <settings>
- <name>OBJCOPY</name>
- <archiveVersion>0</archiveVersion>
- <data>
- <version>1</version>
- <wantNonLocal>1</wantNonLocal>
- <debug>1</debug>
- <option>
- <name>OOCOutputFormat</name>
- <version>3</version>
- <state>3</state>
- </option>
- <option>
- <name>OCOutputOverride</name>
- <state>1</state>
- </option>
- <option>
- <name>OOCOutputFile</name>
- <state>../../../rtthread.bin</state>
- </option>
- <option>
- <name>OOCCommandLineProducer</name>
- <state>1</state>
- </option>
- <option>
- <name>OOCObjCopyEnable</name>
- <state>1</state>
- </option>
- </data>
- </settings>
- <settings>
- <name>CUSTOM</name>
- <archiveVersion>3</archiveVersion>
- <data>
- <extensions />
- <cmdline />
- <hasPrio>0</hasPrio>
- </data>
- </settings>
- <settings>
- <name>BICOMP</name>
- <archiveVersion>0</archiveVersion>
- <data />
- </settings>
- <settings>
- <name>BUILDACTION</name>
- <archiveVersion>1</archiveVersion>
- <data>
- <prebuild />
- <postbuild />
- </data>
- </settings>
- <settings>
- <name>ILINK</name>
- <archiveVersion>0</archiveVersion>
- <data>
- <version>20</version>
- <wantNonLocal>1</wantNonLocal>
- <debug>1</debug>
- <option>
- <name>IlinkLibIOConfig</name>
- <state>1</state>
- </option>
- <option>
- <name>XLinkMisraHandler</name>
- <state>0</state>
- </option>
- <option>
- <name>IlinkInputFileSlave</name>
- <state>0</state>
- </option>
- <option>
- <name>IlinkOutputFile</name>
- <state>rtthread.out</state>
- </option>
- <option>
- <name>IlinkDebugInfoEnable</name>
- <state>1</state>
- </option>
- <option>
- <name>IlinkKeepSymbols</name>
- <state />
- </option>
- <option>
- <name>IlinkRawBinaryFile</name>
- <state />
- </option>
- <option>
- <name>IlinkRawBinarySymbol</name>
- <state />
- </option>
- <option>
- <name>IlinkRawBinarySegment</name>
- <state />
- </option>
- <option>
- <name>IlinkRawBinaryAlign</name>
- <state />
- </option>
- <option>
- <name>IlinkDefines</name>
- <state />
- </option>
- <option>
- <name>IlinkConfigDefines</name>
- <state />
- </option>
- <option>
- <name>IlinkMapFile</name>
- <state>0</state>
- </option>
- <option>
- <name>IlinkLogFile</name>
- <state>0</state>
- </option>
- <option>
- <name>IlinkLogInitialization</name>
- <state>0</state>
- </option>
- <option>
- <name>IlinkLogModule</name>
- <state>0</state>
- </option>
- <option>
- <name>IlinkLogSection</name>
- <state>0</state>
- </option>
- <option>
- <name>IlinkLogVeneer</name>
- <state>0</state>
- </option>
- <option>
- <name>IlinkIcfOverride</name>
- <state>1</state>
- </option>
- <option>
- <name>IlinkIcfFile</name>
- <state>$PROJ_DIR$\drivers\linker_scripts\link.icf</state>
- </option>
- <option>
- <name>IlinkIcfFileSlave</name>
- <state />
- </option>
- <option>
- <name>IlinkEnableRemarks</name>
- <state>0</state>
- </option>
- <option>
- <name>IlinkSuppressDiags</name>
- <state />
- </option>
- <option>
- <name>IlinkTreatAsRem</name>
- <state />
- </option>
- <option>
- <name>IlinkTreatAsWarn</name>
- <state />
- </option>
- <option>
- <name>IlinkTreatAsErr</name>
- <state />
- </option>
- <option>
- <name>IlinkWarningsAreErrors</name>
- <state>0</state>
- </option>
- <option>
- <name>IlinkUseExtraOptions</name>
- <state>0</state>
- </option>
- <option>
- <name>IlinkExtraOptions</name>
- <state />
- </option>
- <option>
- <name>IlinkLowLevelInterfaceSlave</name>
- <state>1</state>
- </option>
- <option>
- <name>IlinkAutoLibEnable</name>
- <state>1</state>
- </option>
- <option>
- <name>IlinkAdditionalLibs</name>
- <state />
- </option>
- <option>
- <name>IlinkOverrideProgramEntryLabel</name>
- <state>0</state>
- </option>
- <option>
- <name>IlinkProgramEntryLabelSelect</name>
- <state>0</state>
- </option>
- <option>
- <name>IlinkProgramEntryLabel</name>
- <state>__iar_program_start</state>
- </option>
- <option>
- <name>DoFill</name>
- <state>0</state>
- </option>
- <option>
- <name>FillerByte</name>
- <state>0xFF</state>
- </option>
- <option>
- <name>FillerStart</name>
- <state>0x0</state>
- </option>
- <option>
- <name>FillerEnd</name>
- <state>0x0</state>
- </option>
- <option>
- <name>CrcSize</name>
- <version>0</version>
- <state>1</state>
- </option>
- <option>
- <name>CrcAlign</name>
- <state>1</state>
- </option>
- <option>
- <name>CrcPoly</name>
- <state>0x11021</state>
- </option>
- <option>
- <name>CrcCompl</name>
- <version>0</version>
- <state>0</state>
- </option>
- <option>
- <name>CrcBitOrder</name>
- <version>0</version>
- <state>0</state>
- </option>
- <option>
- <name>CrcInitialValue</name>
- <state>0x0</state>
- </option>
- <option>
- <name>DoCrc</name>
- <state>0</state>
- </option>
- <option>
- <name>IlinkBE8Slave</name>
- <state>1</state>
- </option>
- <option>
- <name>IlinkBufferedTerminalOutput</name>
- <state>1</state>
- </option>
- <option>
- <name>IlinkStdoutInterfaceSlave</name>
- <state>1</state>
- </option>
- <option>
- <name>CrcFullSize</name>
- <state>0</state>
- </option>
- <option>
- <name>IlinkIElfToolPostProcess</name>
- <state>0</state>
- </option>
- <option>
- <name>IlinkLogAutoLibSelect</name>
- <state>0</state>
- </option>
- <option>
- <name>IlinkLogRedirSymbols</name>
- <state>0</state>
- </option>
- <option>
- <name>IlinkLogUnusedFragments</name>
- <state>0</state>
- </option>
- <option>
- <name>IlinkCrcReverseByteOrder</name>
- <state>0</state>
- </option>
- <option>
- <name>IlinkCrcUseAsInput</name>
- <state>1</state>
- </option>
- <option>
- <name>IlinkOptInline</name>
- <state>0</state>
- </option>
- <option>
- <name>IlinkOptExceptionsAllow</name>
- <state>1</state>
- </option>
- <option>
- <name>IlinkOptExceptionsForce</name>
- <state>0</state>
- </option>
- <option>
- <name>IlinkCmsis</name>
- <state>1</state>
- </option>
- <option>
- <name>IlinkOptMergeDuplSections</name>
- <state>0</state>
- </option>
- <option>
- <name>IlinkOptUseVfe</name>
- <state>1</state>
- </option>
- <option>
- <name>IlinkOptForceVfe</name>
- <state>0</state>
- </option>
- <option>
- <name>IlinkStackAnalysisEnable</name>
- <state>0</state>
- </option>
- <option>
- <name>IlinkStackControlFile</name>
- <state />
- </option>
- <option>
- <name>IlinkStackCallGraphFile</name>
- <state />
- </option>
- <option>
- <name>CrcAlgorithm</name>
- <version>1</version>
- <state>1</state>
- </option>
- <option>
- <name>CrcUnitSize</name>
- <version>0</version>
- <state>0</state>
- </option>
- <option>
- <name>IlinkThreadsSlave</name>
- <state>1</state>
- </option>
- <option>
- <name>IlinkLogCallGraph</name>
- <state>0</state>
- </option>
- <option>
- <name>IlinkIcfFile_AltDefault</name>
- <state />
- </option>
- <option>
- <name>IlinkEncInput</name>
- <state>0</state>
- </option>
- <option>
- <name>IlinkEncOutput</name>
- <state>0</state>
- </option>
- <option>
- <name>IlinkEncOutputBom</name>
- <state>1</state>
- </option>
- <option>
- <name>IlinkHeapSelect</name>
- <state>1</state>
- </option>
- <option>
- <name>IlinkLocaleSelect</name>
- <state>1</state>
- </option>
- </data>
- </settings>
- <settings>
- <name>IARCHIVE</name>
- <archiveVersion>0</archiveVersion>
- <data>
- <version>0</version>
- <wantNonLocal>1</wantNonLocal>
- <debug>1</debug>
- <option>
- <name>IarchiveInputs</name>
- <state />
- </option>
- <option>
- <name>IarchiveOverride</name>
- <state>0</state>
- </option>
- <option>
- <name>IarchiveOutput</name>
- <state>###Unitialized###</state>
- </option>
- </data>
- </settings>
- <settings>
- <name>BILINK</name>
- <archiveVersion>0</archiveVersion>
- <data />
- </settings>
- </configuration>
- <configuration>
- <name>Release</name>
- <toolchain>
- <name>ARM</name>
- </toolchain>
- <debug>0</debug>
- <settings>
- <name>General</name>
- <archiveVersion>3</archiveVersion>
- <data>
- <version>29</version>
- <wantNonLocal>1</wantNonLocal>
- <debug>0</debug>
- <option>
- <name>ExePath</name>
- <state>Release\Exe</state>
- </option>
- <option>
- <name>ObjPath</name>
- <state>Release\Obj</state>
- </option>
- <option>
- <name>ListPath</name>
- <state>Release\List</state>
- </option>
- <option>
- <name>GEndianMode</name>
- <state>0</state>
- </option>
- <option>
- <name>Input description</name>
- <state />
- </option>
- <option>
- <name>Output description</name>
- <state />
- </option>
- <option>
- <name>GOutputBinary</name>
- <state>0</state>
- </option>
- <option>
- <name>OGCoreOrChip</name>
- <state>0</state>
- </option>
- <option>
- <name>GRuntimeLibSelect</name>
- <version>0</version>
- <state>1</state>
- </option>
- <option>
- <name>GRuntimeLibSelectSlave</name>
- <version>0</version>
- <state>1</state>
- </option>
- <option>
- <name>RTDescription</name>
- <state />
- </option>
- <option>
- <name>OGProductVersion</name>
- <state>6.30.6.53380</state>
- </option>
- <option>
- <name>OGLastSavedByProductVersion</name>
- <state>8.11.3.13977</state>
- </option>
- <option>
- <name>GeneralEnableMisra</name>
- <state>0</state>
- </option>
- <option>
- <name>GeneralMisraVerbose</name>
- <state>0</state>
- </option>
- <option>
- <name>OGChipSelectEditMenu</name>
- <state>Default None</state>
- </option>
- <option>
- <name>GenLowLevelInterface</name>
- <state>0</state>
- </option>
- <option>
- <name>GEndianModeBE</name>
- <state>0</state>
- </option>
- <option>
- <name>OGBufferedTerminalOutput</name>
- <state>0</state>
- </option>
- <option>
- <name>GenStdoutInterface</name>
- <state>0</state>
- </option>
- <option>
- <name>GeneralMisraRules98</name>
- <version>0</version>
- <state>1000111110110101101110011100111111101110011011000101110111101101100111111111111100110011111001110111001111111111111111111111111</state>
- </option>
- <option>
- <name>GeneralMisraVer</name>
- <state>0</state>
- </option>
- <option>
- <name>GeneralMisraRules04</name>
- <version>0</version>
- <state>111101110010111111111000110111111111111111111111111110010111101111010101111111111111111111111111101111111011111001111011111011111111111111111</state>
- </option>
- <option>
- <name>RTConfigPath2</name>
- <state />
- </option>
- <option>
- <name>GBECoreSlave</name>
- <version>25</version>
- <state>1</state>
- </option>
- <option>
- <name>OGUseCmsis</name>
- <state>0</state>
- </option>
- <option>
- <name>OGUseCmsisDspLib</name>
- <state>0</state>
- </option>
- <option>
- <name>GRuntimeLibThreads</name>
- <state>0</state>
- </option>
- <option>
- <name>CoreVariant</name>
- <version>25</version>
- <state>0</state>
- </option>
- <option>
- <name>GFPUDeviceSlave</name>
- <state>Default None</state>
- </option>
- <option>
- <name>FPU2</name>
- <version>0</version>
- <state>0</state>
- </option>
- <option>
- <name>NrRegs</name>
- <version>0</version>
- <state>0</state>
- </option>
- <option>
- <name>NEON</name>
- <state>0</state>
- </option>
- <option>
- <name>GFPUCoreSlave2</name>
- <version>25</version>
- <state>0</state>
- </option>
- <option>
- <name>OGCMSISPackSelectDevice</name>
- </option>
- <option>
- <name>OgLibHeap</name>
- <state>0</state>
- </option>
- <option>
- <name>OGLibAdditionalLocale</name>
- <state>0</state>
- </option>
- <option>
- <name>OGPrintfVariant</name>
- <version>0</version>
- <state>0</state>
- </option>
- <option>
- <name>OGPrintfMultibyteSupport</name>
- <state>0</state>
- </option>
- <option>
- <name>OGScanfVariant</name>
- <version>0</version>
- <state>0</state>
- </option>
- <option>
- <name>OGScanfMultibyteSupport</name>
- <state>0</state>
- </option>
- <option>
- <name>GenLocaleTags</name>
- <state />
- </option>
- <option>
- <name>GenLocaleDisplayOnly</name>
- <state />
- </option>
- <option>
- <name>DSPExtension</name>
- <state>0</state>
- </option>
- </data>
- </settings>
- <settings>
- <name>ICCARM</name>
- <archiveVersion>2</archiveVersion>
- <data>
- <version>34</version>
- <wantNonLocal>1</wantNonLocal>
- <debug>0</debug>
- <option>
- <name>CCOptimizationNoSizeConstraints</name>
- <state>0</state>
- </option>
- <option>
- <name>CCDefines</name>
- <state />
- </option>
- <option>
- <name>CCPreprocFile</name>
- <state>0</state>
- </option>
- <option>
- <name>CCPreprocComments</name>
- <state>0</state>
- </option>
- <option>
- <name>CCPreprocLine</name>
- <state>0</state>
- </option>
- <option>
- <name>CCListCFile</name>
- <state>0</state>
- </option>
- <option>
- <name>CCListCMnemonics</name>
- <state>0</state>
- </option>
- <option>
- <name>CCListCMessages</name>
- <state>0</state>
- </option>
- <option>
- <name>CCListAssFile</name>
- <state>0</state>
- </option>
- <option>
- <name>CCListAssSource</name>
- <state>0</state>
- </option>
- <option>
- <name>CCEnableRemarks</name>
- <state>0</state>
- </option>
- <option>
- <name>CCDiagSuppress</name>
- <state />
- </option>
- <option>
- <name>CCDiagRemark</name>
- <state />
- </option>
- <option>
- <name>CCDiagWarning</name>
- <state />
- </option>
- <option>
- <name>CCDiagError</name>
- <state />
- </option>
- <option>
- <name>CCObjPrefix</name>
- <state>1</state>
- </option>
- <option>
- <name>CCAllowList</name>
- <version>1</version>
- <state>11111110</state>
- </option>
- <option>
- <name>CCDebugInfo</name>
- <state>0</state>
- </option>
- <option>
- <name>IEndianMode</name>
- <state>1</state>
- </option>
- <option>
- <name>IProcessor</name>
- <state>1</state>
- </option>
- <option>
- <name>IExtraOptionsCheck</name>
- <state>0</state>
- </option>
- <option>
- <name>IExtraOptions</name>
- <state />
- </option>
- <option>
- <name>CCLangConformance</name>
- <state>0</state>
- </option>
- <option>
- <name>CCSignedPlainChar</name>
- <state>1</state>
- </option>
- <option>
- <name>CCRequirePrototypes</name>
- <state>0</state>
- </option>
- <option>
- <name>CCDiagWarnAreErr</name>
- <state>0</state>
- </option>
- <option>
- <name>CCCompilerRuntimeInfo</name>
- <state>0</state>
- </option>
- <option>
- <name>IFpuProcessor</name>
- <state>1</state>
- </option>
- <option>
- <name>OutputFile</name>
- <state />
- </option>
- <option>
- <name>CCLibConfigHeader</name>
- <state>1</state>
- </option>
- <option>
- <name>PreInclude</name>
- <state />
- </option>
- <option>
- <name>CompilerMisraOverride</name>
- <state>0</state>
- </option>
- <option>
- <name>CCIncludePath2</name>
- <state />
- <state>$PROJ_DIR$\applications</state>
- <state>$PROJ_DIR$\Libraries\CMSIS\DeviceSupport</state>
- <state>$PROJ_DIR$\Libraries\SWM320_StdPeriph_Driver</state>
- <state>$PROJ_DIR$\drivers</state>
- <state>$PROJ_DIR$\..\..\components\libc\compilers\common</state>
- <state>$PROJ_DIR$\.</state>
- <state>$PROJ_DIR$\..\..\include</state>
- <state>$PROJ_DIR$\..\..\libcpu\arm\cortex-m4</state>
- <state>$PROJ_DIR$\..\..\components\drivers\include</state>
- <state>$PROJ_DIR$\..\..\libcpu\arm\common</state>
- <state>$PROJ_DIR$\..\..\components\finsh</state>
- <state>$PROJ_DIR$\Libraries\CMSIS\CoreSupport</state>
- </option>
- <option>
- <name>CCStdIncCheck</name>
- <state>0</state>
- </option>
- <option>
- <name>CCCodeSection</name>
- <state>.text</state>
- </option>
- <option>
- <name>IProcessorMode2</name>
- <state>1</state>
- </option>
- <option>
- <name>CCOptLevel</name>
- <state>3</state>
- </option>
- <option>
- <name>CCOptStrategy</name>
- <version>0</version>
- <state>0</state>
- </option>
- <option>
- <name>CCOptLevelSlave</name>
- <state>1</state>
- </option>
- <option>
- <name>CompilerMisraRules98</name>
- <version>0</version>
- <state>1000111110110101101110011100111111101110011011000101110111101101100111111111111100110011111001110111001111111111111111111111111</state>
- </option>
- <option>
- <name>CompilerMisraRules04</name>
- <version>0</version>
- <state>111101110010111111111000110111111111111111111111111110010111101111010101111111111111111111111111101111111011111001111011111011111111111111111</state>
- </option>
- <option>
- <name>CCPosIndRopi</name>
- <state>0</state>
- </option>
- <option>
- <name>CCPosIndRwpi</name>
- <state>0</state>
- </option>
- <option>
- <name>CCPosIndNoDynInit</name>
- <state>0</state>
- </option>
- <option>
- <name>IccLang</name>
- <state>0</state>
- </option>
- <option>
- <name>IccCDialect</name>
- <state>1</state>
- </option>
- <option>
- <name>IccAllowVLA</name>
- <state>0</state>
- </option>
- <option>
- <name>IccStaticDestr</name>
- <state>1</state>
- </option>
- <option>
- <name>IccCppInlineSemantics</name>
- <state>0</state>
- </option>
- <option>
- <name>IccCmsis</name>
- <state>1</state>
- </option>
- <option>
- <name>IccFloatSemantics</name>
- <state>0</state>
- </option>
- <option>
- <name>CCNoLiteralPool</name>
- <state>0</state>
- </option>
- <option>
- <name>CCOptStrategySlave</name>
- <version>0</version>
- <state>0</state>
- </option>
- <option>
- <name>CCGuardCalls</name>
- <state>1</state>
- </option>
- <option>
- <name>CCEncSource</name>
- <state>0</state>
- </option>
- <option>
- <name>CCEncOutput</name>
- <state>0</state>
- </option>
- <option>
- <name>CCEncOutputBom</name>
- <state>1</state>
- </option>
- <option>
- <name>CCEncInput</name>
- <state>0</state>
- </option>
- <option>
- <name>IccExceptions2</name>
- <state>0</state>
- </option>
- <option>
- <name>IccRTTI2</name>
- <state>0</state>
- </option>
- </data>
- </settings>
- <settings>
- <name>AARM</name>
- <archiveVersion>2</archiveVersion>
- <data>
- <version>10</version>
- <wantNonLocal>1</wantNonLocal>
- <debug>0</debug>
- <option>
- <name>AObjPrefix</name>
- <state>1</state>
- </option>
- <option>
- <name>AEndian</name>
- <state>1</state>
- </option>
- <option>
- <name>ACaseSensitivity</name>
- <state>1</state>
- </option>
- <option>
- <name>MacroChars</name>
- <version>0</version>
- <state>0</state>
- </option>
- <option>
- <name>AWarnEnable</name>
- <state>0</state>
- </option>
- <option>
- <name>AWarnWhat</name>
- <state>0</state>
- </option>
- <option>
- <name>AWarnOne</name>
- <state />
- </option>
- <option>
- <name>AWarnRange1</name>
- <state />
- </option>
- <option>
- <name>AWarnRange2</name>
- <state />
- </option>
- <option>
- <name>ADebug</name>
- <state>0</state>
- </option>
- <option>
- <name>AltRegisterNames</name>
- <state>0</state>
- </option>
- <option>
- <name>ADefines</name>
- <state />
- </option>
- <option>
- <name>AList</name>
- <state>0</state>
- </option>
- <option>
- <name>AListHeader</name>
- <state>1</state>
- </option>
- <option>
- <name>AListing</name>
- <state>1</state>
- </option>
- <option>
- <name>Includes</name>
- <state>0</state>
- </option>
- <option>
- <name>MacDefs</name>
- <state>0</state>
- </option>
- <option>
- <name>MacExps</name>
- <state>1</state>
- </option>
- <option>
- <name>MacExec</name>
- <state>0</state>
- </option>
- <option>
- <name>OnlyAssed</name>
- <state>0</state>
- </option>
- <option>
- <name>MultiLine</name>
- <state>0</state>
- </option>
- <option>
- <name>PageLengthCheck</name>
- <state>0</state>
- </option>
- <option>
- <name>PageLength</name>
- <state>80</state>
- </option>
- <option>
- <name>TabSpacing</name>
- <state>8</state>
- </option>
- <option>
- <name>AXRef</name>
- <state>0</state>
- </option>
- <option>
- <name>AXRefDefines</name>
- <state>0</state>
- </option>
- <option>
- <name>AXRefInternal</name>
- <state>0</state>
- </option>
- <option>
- <name>AXRefDual</name>
- <state>0</state>
- </option>
- <option>
- <name>AProcessor</name>
- <state>1</state>
- </option>
- <option>
- <name>AFpuProcessor</name>
- <state>1</state>
- </option>
- <option>
- <name>AOutputFile</name>
- <state />
- </option>
- <option>
- <name>ALimitErrorsCheck</name>
- <state>0</state>
- </option>
- <option>
- <name>ALimitErrorsEdit</name>
- <state>100</state>
- </option>
- <option>
- <name>AIgnoreStdInclude</name>
- <state>0</state>
- </option>
- <option>
- <name>AUserIncludes</name>
- <state />
- </option>
- <option>
- <name>AExtraOptionsCheckV2</name>
- <state>0</state>
- </option>
- <option>
- <name>AExtraOptionsV2</name>
- <state />
- </option>
- <option>
- <name>AsmNoLiteralPool</name>
- <state>0</state>
- </option>
- </data>
- </settings>
- <settings>
- <name>OBJCOPY</name>
- <archiveVersion>0</archiveVersion>
- <data>
- <version>1</version>
- <wantNonLocal>1</wantNonLocal>
- <debug>0</debug>
- <option>
- <name>OOCOutputFormat</name>
- <version>3</version>
- <state>0</state>
- </option>
- <option>
- <name>OCOutputOverride</name>
- <state>0</state>
- </option>
- <option>
- <name>OOCOutputFile</name>
- <state />
- </option>
- <option>
- <name>OOCCommandLineProducer</name>
- <state>1</state>
- </option>
- <option>
- <name>OOCObjCopyEnable</name>
- <state>0</state>
- </option>
- </data>
- </settings>
- <settings>
- <name>CUSTOM</name>
- <archiveVersion>3</archiveVersion>
- <data>
- <extensions />
- <cmdline />
- <hasPrio>0</hasPrio>
- </data>
- </settings>
- <settings>
- <name>BICOMP</name>
- <archiveVersion>0</archiveVersion>
- <data />
- </settings>
- <settings>
- <name>BUILDACTION</name>
- <archiveVersion>1</archiveVersion>
- <data>
- <prebuild />
- <postbuild />
- </data>
- </settings>
- <settings>
- <name>ILINK</name>
- <archiveVersion>0</archiveVersion>
- <data>
- <version>20</version>
- <wantNonLocal>1</wantNonLocal>
- <debug>0</debug>
- <option>
- <name>IlinkLibIOConfig</name>
- <state>1</state>
- </option>
- <option>
- <name>XLinkMisraHandler</name>
- <state>0</state>
- </option>
- <option>
- <name>IlinkInputFileSlave</name>
- <state>0</state>
- </option>
- <option>
- <name>IlinkOutputFile</name>
- <state>###Unitialized###</state>
- </option>
- <option>
- <name>IlinkDebugInfoEnable</name>
- <state>1</state>
- </option>
- <option>
- <name>IlinkKeepSymbols</name>
- <state />
- </option>
- <option>
- <name>IlinkRawBinaryFile</name>
- <state />
- </option>
- <option>
- <name>IlinkRawBinarySymbol</name>
- <state />
- </option>
- <option>
- <name>IlinkRawBinarySegment</name>
- <state />
- </option>
- <option>
- <name>IlinkRawBinaryAlign</name>
- <state />
- </option>
- <option>
- <name>IlinkDefines</name>
- <state />
- </option>
- <option>
- <name>IlinkConfigDefines</name>
- <state />
- </option>
- <option>
- <name>IlinkMapFile</name>
- <state>0</state>
- </option>
- <option>
- <name>IlinkLogFile</name>
- <state>0</state>
- </option>
- <option>
- <name>IlinkLogInitialization</name>
- <state>0</state>
- </option>
- <option>
- <name>IlinkLogModule</name>
- <state>0</state>
- </option>
- <option>
- <name>IlinkLogSection</name>
- <state>0</state>
- </option>
- <option>
- <name>IlinkLogVeneer</name>
- <state>0</state>
- </option>
- <option>
- <name>IlinkIcfOverride</name>
- <state>0</state>
- </option>
- <option>
- <name>IlinkIcfFile</name>
- <state>lnk0t.icf</state>
- </option>
- <option>
- <name>IlinkIcfFileSlave</name>
- <state />
- </option>
- <option>
- <name>IlinkEnableRemarks</name>
- <state>0</state>
- </option>
- <option>
- <name>IlinkSuppressDiags</name>
- <state />
- </option>
- <option>
- <name>IlinkTreatAsRem</name>
- <state />
- </option>
- <option>
- <name>IlinkTreatAsWarn</name>
- <state />
- </option>
- <option>
- <name>IlinkTreatAsErr</name>
- <state />
- </option>
- <option>
- <name>IlinkWarningsAreErrors</name>
- <state>0</state>
- </option>
- <option>
- <name>IlinkUseExtraOptions</name>
- <state>0</state>
- </option>
- <option>
- <name>IlinkExtraOptions</name>
- <state />
- </option>
- <option>
- <name>IlinkLowLevelInterfaceSlave</name>
- <state>1</state>
- </option>
- <option>
- <name>IlinkAutoLibEnable</name>
- <state>1</state>
- </option>
- <option>
- <name>IlinkAdditionalLibs</name>
- <state />
- </option>
- <option>
- <name>IlinkOverrideProgramEntryLabel</name>
- <state>0</state>
- </option>
- <option>
- <name>IlinkProgramEntryLabelSelect</name>
- <state>0</state>
- </option>
- <option>
- <name>IlinkProgramEntryLabel</name>
- <state />
- </option>
- <option>
- <name>DoFill</name>
- <state>0</state>
- </option>
- <option>
- <name>FillerByte</name>
- <state>0xFF</state>
- </option>
- <option>
- <name>FillerStart</name>
- <state>0x0</state>
- </option>
- <option>
- <name>FillerEnd</name>
- <state>0x0</state>
- </option>
- <option>
- <name>CrcSize</name>
- <version>0</version>
- <state>1</state>
- </option>
- <option>
- <name>CrcAlign</name>
- <state>1</state>
- </option>
- <option>
- <name>CrcPoly</name>
- <state>0x11021</state>
- </option>
- <option>
- <name>CrcCompl</name>
- <version>0</version>
- <state>0</state>
- </option>
- <option>
- <name>CrcBitOrder</name>
- <version>0</version>
- <state>0</state>
- </option>
- <option>
- <name>CrcInitialValue</name>
- <state>0x0</state>
- </option>
- <option>
- <name>DoCrc</name>
- <state>0</state>
- </option>
- <option>
- <name>IlinkBE8Slave</name>
- <state>1</state>
- </option>
- <option>
- <name>IlinkBufferedTerminalOutput</name>
- <state>1</state>
- </option>
- <option>
- <name>IlinkStdoutInterfaceSlave</name>
- <state>1</state>
- </option>
- <option>
- <name>CrcFullSize</name>
- <state>0</state>
- </option>
- <option>
- <name>IlinkIElfToolPostProcess</name>
- <state>0</state>
- </option>
- <option>
- <name>IlinkLogAutoLibSelect</name>
- <state>0</state>
- </option>
- <option>
- <name>IlinkLogRedirSymbols</name>
- <state>0</state>
- </option>
- <option>
- <name>IlinkLogUnusedFragments</name>
- <state>0</state>
- </option>
- <option>
- <name>IlinkCrcReverseByteOrder</name>
- <state>0</state>
- </option>
- <option>
- <name>IlinkCrcUseAsInput</name>
- <state>1</state>
- </option>
- <option>
- <name>IlinkOptInline</name>
- <state>1</state>
- </option>
- <option>
- <name>IlinkOptExceptionsAllow</name>
- <state>1</state>
- </option>
- <option>
- <name>IlinkOptExceptionsForce</name>
- <state>0</state>
- </option>
- <option>
- <name>IlinkCmsis</name>
- <state>1</state>
- </option>
- <option>
- <name>IlinkOptMergeDuplSections</name>
- <state>0</state>
- </option>
- <option>
- <name>IlinkOptUseVfe</name>
- <state>1</state>
- </option>
- <option>
- <name>IlinkOptForceVfe</name>
- <state>0</state>
- </option>
- <option>
- <name>IlinkStackAnalysisEnable</name>
- <state>0</state>
- </option>
- <option>
- <name>IlinkStackControlFile</name>
- <state />
- </option>
- <option>
- <name>IlinkStackCallGraphFile</name>
- <state />
- </option>
- <option>
- <name>CrcAlgorithm</name>
- <version>1</version>
- <state>1</state>
- </option>
- <option>
- <name>CrcUnitSize</name>
- <version>0</version>
- <state>0</state>
- </option>
- <option>
- <name>IlinkThreadsSlave</name>
- <state>1</state>
- </option>
- <option>
- <name>IlinkLogCallGraph</name>
- <state>0</state>
- </option>
- <option>
- <name>IlinkIcfFile_AltDefault</name>
- <state />
- </option>
- <option>
- <name>IlinkEncInput</name>
- <state>0</state>
- </option>
- <option>
- <name>IlinkEncOutput</name>
- <state>0</state>
- </option>
- <option>
- <name>IlinkEncOutputBom</name>
- <state>1</state>
- </option>
- <option>
- <name>IlinkHeapSelect</name>
- <state>1</state>
- </option>
- <option>
- <name>IlinkLocaleSelect</name>
- <state>1</state>
- </option>
- </data>
- </settings>
- <settings>
- <name>IARCHIVE</name>
- <archiveVersion>0</archiveVersion>
- <data>
- <version>0</version>
- <wantNonLocal>1</wantNonLocal>
- <debug>0</debug>
- <option>
- <name>IarchiveInputs</name>
- <state />
- </option>
- <option>
- <name>IarchiveOverride</name>
- <state>0</state>
- </option>
- <option>
- <name>IarchiveOutput</name>
- <state>###Unitialized###</state>
- </option>
- </data>
- </settings>
- <settings>
- <name>BILINK</name>
- <archiveVersion>0</archiveVersion>
- <data />
- </settings>
- </configuration>
- <group>
- <name>Kernel</name>
- <file>
- <name>$PROJ_DIR$\..\..\src\clock.c</name>
- </file>
- <file>
- <name>$PROJ_DIR$\..\..\src\components.c</name>
- </file>
- <file>
- <name>$PROJ_DIR$\..\..\src\cpu.c</name>
- </file>
- <file>
- <name>$PROJ_DIR$\..\..\src\device.c</name>
- </file>
- <file>
- <name>$PROJ_DIR$\..\..\src\idle.c</name>
- </file>
- <file>
- <name>$PROJ_DIR$\..\..\src\ipc.c</name>
- </file>
- <file>
- <name>$PROJ_DIR$\..\..\src\irq.c</name>
- </file>
- <file>
- <name>$PROJ_DIR$\..\..\src\kservice.c</name>
- </file>
- <file>
- <name>$PROJ_DIR$\..\..\src\mem.c</name>
- </file>
- <file>
- <name>$PROJ_DIR$\..\..\src\memheap.c</name>
- </file>
- <file>
- <name>$PROJ_DIR$\..\..\src\mempool.c</name>
- </file>
- <file>
- <name>$PROJ_DIR$\..\..\src\object.c</name>
- </file>
- <file>
- <name>$PROJ_DIR$\..\..\src\scheduler.c</name>
- </file>
- <file>
- <name>$PROJ_DIR$\..\..\src\signal.c</name>
- </file>
- <file>
- <name>$PROJ_DIR$\..\..\src\thread.c</name>
- </file>
- <file>
- <name>$PROJ_DIR$\..\..\src\timer.c</name>
- </file>
- </group>
- <group>
- <name>Applications</name>
- <file>
- <name>$PROJ_DIR$\applications\main.c</name>
- </file>
- </group>
- <group>
- <name>Drivers</name>
- <file>
- <name>$PROJ_DIR$\drivers\board.c</name>
- </file>
- <file>
- <name>$PROJ_DIR$\drivers\drv_gpio.c</name>
- </file>
- <file>
- <name>$PROJ_DIR$\drivers\drv_uart.c</name>
- </file>
- </group>
- <group>
- <name>Libraries</name>
- <file>
- <name>$PROJ_DIR$\Libraries\CMSIS\DeviceSupport\system_SWM320.c</name>
- </file>
- <file>
- <name>$PROJ_DIR$\Libraries\SWM320_StdPeriph_Driver\SWM320_adc.c</name>
- </file>
- <file>
- <name>$PROJ_DIR$\Libraries\SWM320_StdPeriph_Driver\SWM320_can.c</name>
- </file>
- <file>
- <name>$PROJ_DIR$\Libraries\SWM320_StdPeriph_Driver\SWM320_crc.c</name>
- </file>
- <file>
- <name>$PROJ_DIR$\Libraries\SWM320_StdPeriph_Driver\SWM320_dma.c</name>
- </file>
- <file>
- <name>$PROJ_DIR$\Libraries\SWM320_StdPeriph_Driver\SWM320_exti.c</name>
- </file>
- <file>
- <name>$PROJ_DIR$\Libraries\SWM320_StdPeriph_Driver\SWM320_flash.c</name>
- </file>
- <file>
- <name>$PROJ_DIR$\Libraries\SWM320_StdPeriph_Driver\SWM320_gpio.c</name>
- </file>
- <file>
- <name>$PROJ_DIR$\Libraries\SWM320_StdPeriph_Driver\SWM320_i2c.c</name>
- </file>
- <file>
- <name>$PROJ_DIR$\Libraries\SWM320_StdPeriph_Driver\SWM320_lcd.c</name>
- </file>
- <file>
- <name>$PROJ_DIR$\Libraries\SWM320_StdPeriph_Driver\SWM320_norflash.c</name>
- </file>
- <file>
- <name>$PROJ_DIR$\Libraries\SWM320_StdPeriph_Driver\SWM320_port.c</name>
- </file>
- <file>
- <name>$PROJ_DIR$\Libraries\SWM320_StdPeriph_Driver\SWM320_pwm.c</name>
- </file>
- <file>
- <name>$PROJ_DIR$\Libraries\SWM320_StdPeriph_Driver\SWM320_rtc.c</name>
- </file>
- <file>
- <name>$PROJ_DIR$\Libraries\SWM320_StdPeriph_Driver\SWM320_sdio.c</name>
- </file>
- <file>
- <name>$PROJ_DIR$\Libraries\SWM320_StdPeriph_Driver\SWM320_sdram.c</name>
- </file>
- <file>
- <name>$PROJ_DIR$\Libraries\SWM320_StdPeriph_Driver\SWM320_spi.c</name>
- </file>
- <file>
- <name>$PROJ_DIR$\Libraries\SWM320_StdPeriph_Driver\SWM320_timr.c</name>
- </file>
- <file>
- <name>$PROJ_DIR$\Libraries\SWM320_StdPeriph_Driver\SWM320_uart.c</name>
- </file>
- <file>
- <name>$PROJ_DIR$\Libraries\SWM320_StdPeriph_Driver\SWM320_wdt.c</name>
- </file>
- <file>
- <name>$PROJ_DIR$\Libraries\CMSIS\DeviceSupport\startup\iar\startup_SWM320.s</name>
- </file>
- </group>
- <group>
- <name>cpu</name>
- <file>
- <name>$PROJ_DIR$\..\..\libcpu\arm\common\backtrace.c</name>
- </file>
- <file>
- <name>$PROJ_DIR$\..\..\libcpu\arm\common\div0.c</name>
- </file>
- <file>
- <name>$PROJ_DIR$\..\..\libcpu\arm\common\showmem.c</name>
- </file>
- <file>
- <name>$PROJ_DIR$\..\..\libcpu\arm\cortex-m4\cpuport.c</name>
- </file>
- <file>
- <name>$PROJ_DIR$\..\..\libcpu\arm\cortex-m4\context_iar.S</name>
- </file>
- </group>
- <group>
- <name>DeviceDrivers</name>
- <file>
- <name>$PROJ_DIR$\..\..\components\drivers\hwtimer\hwtimer.c</name>
- </file>
- <file>
- <name>$PROJ_DIR$\..\..\components\drivers\misc\pin.c</name>
- </file>
- <file>
- <name>$PROJ_DIR$\..\..\components\drivers\misc\rt_drv_pwm.c</name>
- </file>
- <file>
- <name>$PROJ_DIR$\..\..\components\drivers\serial\serial.c</name>
- </file>
- <file>
- <name>$PROJ_DIR$\..\..\components\drivers\src\completion.c</name>
- </file>
- <file>
- <name>$PROJ_DIR$\..\..\components\drivers\src\dataqueue.c</name>
- </file>
- <file>
- <name>$PROJ_DIR$\..\..\components\drivers\src\pipe.c</name>
- </file>
- <file>
- <name>$PROJ_DIR$\..\..\components\drivers\src\ringblk_buf.c</name>
- </file>
- <file>
- <name>$PROJ_DIR$\..\..\components\drivers\src\ringbuffer.c</name>
- </file>
- <file>
- <name>$PROJ_DIR$\..\..\components\drivers\src\waitqueue.c</name>
- </file>
- <file>
- <name>$PROJ_DIR$\..\..\components\drivers\src\workqueue.c</name>
- </file>
- </group>
- <group>
- <name>finsh</name>
- <file>
- <name>$PROJ_DIR$\..\..\components\finsh\shell.c</name>
- </file>
- <file>
- <name>$PROJ_DIR$\..\..\components\finsh\cmd.c</name>
- </file>
- <file>
- <name>$PROJ_DIR$\..\..\components\finsh\msh.c</name>
- </file>
- <file>
- <name>$PROJ_DIR$\..\..\components\finsh\finsh_compiler.c</name>
- </file>
- <file>
- <name>$PROJ_DIR$\..\..\components\finsh\finsh_error.c</name>
- </file>
- <file>
- <name>$PROJ_DIR$\..\..\components\finsh\finsh_heap.c</name>
- </file>
- <file>
- <name>$PROJ_DIR$\..\..\components\finsh\finsh_init.c</name>
- </file>
- <file>
- <name>$PROJ_DIR$\..\..\components\finsh\finsh_node.c</name>
- </file>
- <file>
- <name>$PROJ_DIR$\..\..\components\finsh\finsh_ops.c</name>
- </file>
- <file>
- <name>$PROJ_DIR$\..\..\components\finsh\finsh_parser.c</name>
- </file>
- <file>
- <name>$PROJ_DIR$\..\..\components\finsh\finsh_var.c</name>
- </file>
- <file>
- <name>$PROJ_DIR$\..\..\components\finsh\finsh_vm.c</name>
- </file>
- <file>
- <name>$PROJ_DIR$\..\..\components\finsh\finsh_token.c</name>
- </file>
- </group>
- <group>
- <name>libc</name>
- </group>
-</project>
+<project> + <fileVersion>3</fileVersion> + <configuration> + <name>rtthread</name> + <toolchain> + <name>ARM</name> + </toolchain> + <debug>1</debug> + <settings> + <name>General</name> + <archiveVersion>3</archiveVersion> + <data> + <version>29</version> + <wantNonLocal>1</wantNonLocal> + <debug>1</debug> + <option> + <name>ExePath</name> + <state>build\iar\Exe</state> + </option> + <option> + <name>ObjPath</name> + <state>build\iar\Obj</state> + </option> + <option> + <name>ListPath</name> + <state>build\iar\List</state> + </option> + <option> + <name>GEndianMode</name> + <state>0</state> + </option> + <option> + <name>Input description</name> + <state>Automatic choice of formatter, without multibyte support.</state> + </option> + <option> + <name>Output description</name> + <state>Automatic choice of formatter, without multibyte support.</state> + </option> + <option> + <name>GOutputBinary</name> + <state>0</state> + </option> + <option> + <name>OGCoreOrChip</name> + <state>1</state> + </option> + <option> + <name>GRuntimeLibSelect</name> + <version>0</version> + <state>1</state> + </option> + <option> + <name>GRuntimeLibSelectSlave</name> + <version>0</version> + <state>1</state> + </option> + <option> + <name>RTDescription</name> + <state>Use the normal configuration of the C/C++ runtime library. No locale interface, C locale, no file descriptor support, no multibytes in printf and scanf, and no hex floats in strtod.</state> + </option> + <option> + <name>OGProductVersion</name> + <state>6.30.6.53380</state> + </option> + <option> + <name>OGLastSavedByProductVersion</name> + <state>8.11.3.13977</state> + </option> + <option> + <name>GeneralEnableMisra</name> + <state>0</state> + </option> + <option> + <name>GeneralMisraVerbose</name> + <state>0</state> + </option> + <option> + <name>OGChipSelectEditMenu</name> + <state>STM32F407ZG ST STM32F407ZG</state> + </option> + <option> + <name>GenLowLevelInterface</name> + <state>1</state> + </option> + <option> + <name>GEndianModeBE</name> + <state>1</state> + </option> + <option> + <name>OGBufferedTerminalOutput</name> + <state>0</state> + </option> + <option> + <name>GenStdoutInterface</name> + <state>0</state> + </option> + <option> + <name>GeneralMisraRules98</name> + <version>0</version> + <state>1000111110110101101110011100111111101110011011000101110111101101100111111111111100110011111001110111001111111111111111111111111</state> + </option> + <option> + <name>GeneralMisraVer</name> + <state>0</state> + </option> + <option> + <name>GeneralMisraRules04</name> + <version>0</version> + <state>111101110010111111111000110111111111111111111111111110010111101111010101111111111111111111111111101111111011111001111011111011111111111111111</state> + </option> + <option> + <name>RTConfigPath2</name> + <state>$TOOLKIT_DIR$\INC\c\DLib_Config_Normal.h</state> + </option> + <option> + <name>GBECoreSlave</name> + <version>25</version> + <state>39</state> + </option> + <option> + <name>OGUseCmsis</name> + <state>0</state> + </option> + <option> + <name>OGUseCmsisDspLib</name> + <state>0</state> + </option> + <option> + <name>GRuntimeLibThreads</name> + <state>0</state> + </option> + <option> + <name>CoreVariant</name> + <version>25</version> + <state>39</state> + </option> + <option> + <name>GFPUDeviceSlave</name> + <state>STM32F407ZG ST STM32F407ZG</state> + </option> + <option> + <name>FPU2</name> + <version>0</version> + <state>4</state> + </option> + <option> + <name>NrRegs</name> + <version>0</version> + <state>1</state> + </option> + <option> + <name>NEON</name> + <state>0</state> + </option> + <option> + <name>GFPUCoreSlave2</name> + <version>25</version> + <state>39</state> + </option> + <option> + <name>OGCMSISPackSelectDevice</name> + </option> + <option> + <name>OgLibHeap</name> + <state>0</state> + </option> + <option> + <name>OGLibAdditionalLocale</name> + <state>0</state> + </option> + <option> + <name>OGPrintfVariant</name> + <version>0</version> + <state>0</state> + </option> + <option> + <name>OGPrintfMultibyteSupport</name> + <state>0</state> + </option> + <option> + <name>OGScanfVariant</name> + <version>0</version> + <state>0</state> + </option> + <option> + <name>OGScanfMultibyteSupport</name> + <state>0</state> + </option> + <option> + <name>GenLocaleTags</name> + <state /> + </option> + <option> + <name>GenLocaleDisplayOnly</name> + <state /> + </option> + <option> + <name>DSPExtension</name> + <state>1</state> + </option> + </data> + </settings> + <settings> + <name>ICCARM</name> + <archiveVersion>2</archiveVersion> + <data> + <version>34</version> + <wantNonLocal>1</wantNonLocal> + <debug>1</debug> + <option> + <name>CCOptimizationNoSizeConstraints</name> + <state>0</state> + </option> + <option> + <name>CCDefines</name> + <state /> + </option> + <option> + <name>CCPreprocFile</name> + <state>0</state> + </option> + <option> + <name>CCPreprocComments</name> + <state>0</state> + </option> + <option> + <name>CCPreprocLine</name> + <state>0</state> + </option> + <option> + <name>CCListCFile</name> + <state>0</state> + </option> + <option> + <name>CCListCMnemonics</name> + <state>0</state> + </option> + <option> + <name>CCListCMessages</name> + <state>0</state> + </option> + <option> + <name>CCListAssFile</name> + <state>0</state> + </option> + <option> + <name>CCListAssSource</name> + <state>0</state> + </option> + <option> + <name>CCEnableRemarks</name> + <state>0</state> + </option> + <option> + <name>CCDiagSuppress</name> + <state>Pa050</state> + </option> + <option> + <name>CCDiagRemark</name> + <state /> + </option> + <option> + <name>CCDiagWarning</name> + <state /> + </option> + <option> + <name>CCDiagError</name> + <state /> + </option> + <option> + <name>CCObjPrefix</name> + <state>1</state> + </option> + <option> + <name>CCAllowList</name> + <version>1</version> + <state>00000000</state> + </option> + <option> + <name>CCDebugInfo</name> + <state>1</state> + </option> + <option> + <name>IEndianMode</name> + <state>1</state> + </option> + <option> + <name>IProcessor</name> + <state>1</state> + </option> + <option> + <name>IExtraOptionsCheck</name> + <state>0</state> + </option> + <option> + <name>IExtraOptions</name> + <state /> + </option> + <option> + <name>CCLangConformance</name> + <state>0</state> + </option> + <option> + <name>CCSignedPlainChar</name> + <state>1</state> + </option> + <option> + <name>CCRequirePrototypes</name> + <state>0</state> + </option> + <option> + <name>CCDiagWarnAreErr</name> + <state>0</state> + </option> + <option> + <name>CCCompilerRuntimeInfo</name> + <state>0</state> + </option> + <option> + <name>IFpuProcessor</name> + <state>1</state> + </option> + <option> + <name>OutputFile</name> + <state>$FILE_BNAME$.o</state> + </option> + <option> + <name>CCLibConfigHeader</name> + <state>1</state> + </option> + <option> + <name>PreInclude</name> + <state /> + </option> + <option> + <name>CompilerMisraOverride</name> + <state>0</state> + </option> + <option> + <name>CCIncludePath2</name> + <state /> + <state>$PROJ_DIR$\Libraries\XXX_StdPeriph_Driver</state> + <state>$PROJ_DIR$\applications</state> + <state>$PROJ_DIR$\Libraries\CMSIS\DeviceSupport</state> + <state>$PROJ_DIR$\drivers</state> + <state>$PROJ_DIR$\libcpu</state> + <state>$PROJ_DIR$\..\..\include</state> + <state>$PROJ_DIR$\..\..\libcpu\arm\cortex-m4</state> + <state>$PROJ_DIR$\..\..\components\drivers\include</state> + <state>$PROJ_DIR$\..\..\libcpu\arm\common</state> + <state>$PROJ_DIR$\.</state> + <state>$PROJ_DIR$\..\..\components\finsh</state> + <state>$PROJ_DIR$\Libraries\CMSIS\CoreSupport</state> + </option> + <option> + <name>CCStdIncCheck</name> + <state>0</state> + </option> + <option> + <name>CCCodeSection</name> + <state>.text</state> + </option> + <option> + <name>IProcessorMode2</name> + <state>1</state> + </option> + <option> + <name>CCOptLevel</name> + <state>1</state> + </option> + <option> + <name>CCOptStrategy</name> + <version>0</version> + <state>0</state> + </option> + <option> + <name>CCOptLevelSlave</name> + <state>1</state> + </option> + <option> + <name>CompilerMisraRules98</name> + <version>0</version> + <state>1000111110110101101110011100111111101110011011000101110111101101100111111111111100110011111001110111001111111111111111111111111</state> + </option> + <option> + <name>CompilerMisraRules04</name> + <version>0</version> + <state>111101110010111111111000110111111111111111111111111110010111101111010101111111111111111111111111101111111011111001111011111011111111111111111</state> + </option> + <option> + <name>CCPosIndRopi</name> + <state>0</state> + </option> + <option> + <name>CCPosIndRwpi</name> + <state>0</state> + </option> + <option> + <name>CCPosIndNoDynInit</name> + <state>0</state> + </option> + <option> + <name>IccLang</name> + <state>0</state> + </option> + <option> + <name>IccCDialect</name> + <state>1</state> + </option> + <option> + <name>IccAllowVLA</name> + <state>0</state> + </option> + <option> + <name>IccStaticDestr</name> + <state>1</state> + </option> + <option> + <name>IccCppInlineSemantics</name> + <state>0</state> + </option> + <option> + <name>IccCmsis</name> + <state>1</state> + </option> + <option> + <name>IccFloatSemantics</name> + <state>0</state> + </option> + <option> + <name>CCNoLiteralPool</name> + <state>0</state> + </option> + <option> + <name>CCOptStrategySlave</name> + <version>0</version> + <state>0</state> + </option> + <option> + <name>CCGuardCalls</name> + <state>1</state> + </option> + <option> + <name>CCEncSource</name> + <state>0</state> + </option> + <option> + <name>CCEncOutput</name> + <state>0</state> + </option> + <option> + <name>CCEncOutputBom</name> + <state>1</state> + </option> + <option> + <name>CCEncInput</name> + <state>0</state> + </option> + <option> + <name>IccExceptions2</name> + <state>0</state> + </option> + <option> + <name>IccRTTI2</name> + <state>0</state> + </option> + </data> + </settings> + <settings> + <name>AARM</name> + <archiveVersion>2</archiveVersion> + <data> + <version>10</version> + <wantNonLocal>1</wantNonLocal> + <debug>1</debug> + <option> + <name>AObjPrefix</name> + <state>1</state> + </option> + <option> + <name>AEndian</name> + <state>1</state> + </option> + <option> + <name>ACaseSensitivity</name> + <state>1</state> + </option> + <option> + <name>MacroChars</name> + <version>0</version> + <state>0</state> + </option> + <option> + <name>AWarnEnable</name> + <state>0</state> + </option> + <option> + <name>AWarnWhat</name> + <state>0</state> + </option> + <option> + <name>AWarnOne</name> + <state /> + </option> + <option> + <name>AWarnRange1</name> + <state /> + </option> + <option> + <name>AWarnRange2</name> + <state /> + </option> + <option> + <name>ADebug</name> + <state>1</state> + </option> + <option> + <name>AltRegisterNames</name> + <state>0</state> + </option> + <option> + <name>ADefines</name> + <state /> + </option> + <option> + <name>AList</name> + <state>0</state> + </option> + <option> + <name>AListHeader</name> + <state>1</state> + </option> + <option> + <name>AListing</name> + <state>1</state> + </option> + <option> + <name>Includes</name> + <state>0</state> + </option> + <option> + <name>MacDefs</name> + <state>0</state> + </option> + <option> + <name>MacExps</name> + <state>1</state> + </option> + <option> + <name>MacExec</name> + <state>0</state> + </option> + <option> + <name>OnlyAssed</name> + <state>0</state> + </option> + <option> + <name>MultiLine</name> + <state>0</state> + </option> + <option> + <name>PageLengthCheck</name> + <state>0</state> + </option> + <option> + <name>PageLength</name> + <state>80</state> + </option> + <option> + <name>TabSpacing</name> + <state>8</state> + </option> + <option> + <name>AXRef</name> + <state>0</state> + </option> + <option> + <name>AXRefDefines</name> + <state>0</state> + </option> + <option> + <name>AXRefInternal</name> + <state>0</state> + </option> + <option> + <name>AXRefDual</name> + <state>0</state> + </option> + <option> + <name>AProcessor</name> + <state>1</state> + </option> + <option> + <name>AFpuProcessor</name> + <state>1</state> + </option> + <option> + <name>AOutputFile</name> + <state>$FILE_BNAME$.o</state> + </option> + <option> + <name>ALimitErrorsCheck</name> + <state>0</state> + </option> + <option> + <name>ALimitErrorsEdit</name> + <state>100</state> + </option> + <option> + <name>AIgnoreStdInclude</name> + <state>0</state> + </option> + <option> + <name>AUserIncludes</name> + <state /> + </option> + <option> + <name>AExtraOptionsCheckV2</name> + <state>0</state> + </option> + <option> + <name>AExtraOptionsV2</name> + <state /> + </option> + <option> + <name>AsmNoLiteralPool</name> + <state>0</state> + </option> + </data> + </settings> + <settings> + <name>OBJCOPY</name> + <archiveVersion>0</archiveVersion> + <data> + <version>1</version> + <wantNonLocal>1</wantNonLocal> + <debug>1</debug> + <option> + <name>OOCOutputFormat</name> + <version>3</version> + <state>3</state> + </option> + <option> + <name>OCOutputOverride</name> + <state>1</state> + </option> + <option> + <name>OOCOutputFile</name> + <state>../../../rtthread.bin</state> + </option> + <option> + <name>OOCCommandLineProducer</name> + <state>1</state> + </option> + <option> + <name>OOCObjCopyEnable</name> + <state>1</state> + </option> + </data> + </settings> + <settings> + <name>CUSTOM</name> + <archiveVersion>3</archiveVersion> + <data> + <extensions /> + <cmdline /> + <hasPrio>0</hasPrio> + </data> + </settings> + <settings> + <name>BICOMP</name> + <archiveVersion>0</archiveVersion> + <data /> + </settings> + <settings> + <name>BUILDACTION</name> + <archiveVersion>1</archiveVersion> + <data> + <prebuild /> + <postbuild /> + </data> + </settings> + <settings> + <name>ILINK</name> + <archiveVersion>0</archiveVersion> + <data> + <version>20</version> + <wantNonLocal>1</wantNonLocal> + <debug>1</debug> + <option> + <name>IlinkLibIOConfig</name> + <state>1</state> + </option> + <option> + <name>XLinkMisraHandler</name> + <state>0</state> + </option> + <option> + <name>IlinkInputFileSlave</name> + <state>0</state> + </option> + <option> + <name>IlinkOutputFile</name> + <state>project.out</state> + </option> + <option> + <name>IlinkDebugInfoEnable</name> + <state>1</state> + </option> + <option> + <name>IlinkKeepSymbols</name> + <state /> + </option> + <option> + <name>IlinkRawBinaryFile</name> + <state /> + </option> + <option> + <name>IlinkRawBinarySymbol</name> + <state /> + </option> + <option> + <name>IlinkRawBinarySegment</name> + <state /> + </option> + <option> + <name>IlinkRawBinaryAlign</name> + <state /> + </option> + <option> + <name>IlinkDefines</name> + <state /> + </option> + <option> + <name>IlinkConfigDefines</name> + <state /> + </option> + <option> + <name>IlinkMapFile</name> + <state>0</state> + </option> + <option> + <name>IlinkLogFile</name> + <state>0</state> + </option> + <option> + <name>IlinkLogInitialization</name> + <state>0</state> + </option> + <option> + <name>IlinkLogModule</name> + <state>0</state> + </option> + <option> + <name>IlinkLogSection</name> + <state>0</state> + </option> + <option> + <name>IlinkLogVeneer</name> + <state>0</state> + </option> + <option> + <name>IlinkIcfOverride</name> + <state>1</state> + </option> + <option> + <name>IlinkIcfFile</name> + <state>$PROJ_DIR$\drivers\linker_scripts\link.icf</state> + </option> + <option> + <name>IlinkIcfFileSlave</name> + <state /> + </option> + <option> + <name>IlinkEnableRemarks</name> + <state>0</state> + </option> + <option> + <name>IlinkSuppressDiags</name> + <state /> + </option> + <option> + <name>IlinkTreatAsRem</name> + <state /> + </option> + <option> + <name>IlinkTreatAsWarn</name> + <state /> + </option> + <option> + <name>IlinkTreatAsErr</name> + <state /> + </option> + <option> + <name>IlinkWarningsAreErrors</name> + <state>0</state> + </option> + <option> + <name>IlinkUseExtraOptions</name> + <state>0</state> + </option> + <option> + <name>IlinkExtraOptions</name> + <state /> + </option> + <option> + <name>IlinkLowLevelInterfaceSlave</name> + <state>1</state> + </option> + <option> + <name>IlinkAutoLibEnable</name> + <state>1</state> + </option> + <option> + <name>IlinkAdditionalLibs</name> + <state /> + </option> + <option> + <name>IlinkOverrideProgramEntryLabel</name> + <state>0</state> + </option> + <option> + <name>IlinkProgramEntryLabelSelect</name> + <state>0</state> + </option> + <option> + <name>IlinkProgramEntryLabel</name> + <state>__iar_program_start</state> + </option> + <option> + <name>DoFill</name> + <state>0</state> + </option> + <option> + <name>FillerByte</name> + <state>0xFF</state> + </option> + <option> + <name>FillerStart</name> + <state>0x0</state> + </option> + <option> + <name>FillerEnd</name> + <state>0x0</state> + </option> + <option> + <name>CrcSize</name> + <version>0</version> + <state>1</state> + </option> + <option> + <name>CrcAlign</name> + <state>1</state> + </option> + <option> + <name>CrcPoly</name> + <state>0x11021</state> + </option> + <option> + <name>CrcCompl</name> + <version>0</version> + <state>0</state> + </option> + <option> + <name>CrcBitOrder</name> + <version>0</version> + <state>0</state> + </option> + <option> + <name>CrcInitialValue</name> + <state>0x0</state> + </option> + <option> + <name>DoCrc</name> + <state>0</state> + </option> + <option> + <name>IlinkBE8Slave</name> + <state>1</state> + </option> + <option> + <name>IlinkBufferedTerminalOutput</name> + <state>1</state> + </option> + <option> + <name>IlinkStdoutInterfaceSlave</name> + <state>1</state> + </option> + <option> + <name>CrcFullSize</name> + <state>0</state> + </option> + <option> + <name>IlinkIElfToolPostProcess</name> + <state>0</state> + </option> + <option> + <name>IlinkLogAutoLibSelect</name> + <state>0</state> + </option> + <option> + <name>IlinkLogRedirSymbols</name> + <state>0</state> + </option> + <option> + <name>IlinkLogUnusedFragments</name> + <state>0</state> + </option> + <option> + <name>IlinkCrcReverseByteOrder</name> + <state>0</state> + </option> + <option> + <name>IlinkCrcUseAsInput</name> + <state>1</state> + </option> + <option> + <name>IlinkOptInline</name> + <state>0</state> + </option> + <option> + <name>IlinkOptExceptionsAllow</name> + <state>1</state> + </option> + <option> + <name>IlinkOptExceptionsForce</name> + <state>0</state> + </option> + <option> + <name>IlinkCmsis</name> + <state>1</state> + </option> + <option> + <name>IlinkOptMergeDuplSections</name> + <state>0</state> + </option> + <option> + <name>IlinkOptUseVfe</name> + <state>1</state> + </option> + <option> + <name>IlinkOptForceVfe</name> + <state>0</state> + </option> + <option> + <name>IlinkStackAnalysisEnable</name> + <state>0</state> + </option> + <option> + <name>IlinkStackControlFile</name> + <state /> + </option> + <option> + <name>IlinkStackCallGraphFile</name> + <state /> + </option> + <option> + <name>CrcAlgorithm</name> + <version>1</version> + <state>1</state> + </option> + <option> + <name>CrcUnitSize</name> + <version>0</version> + <state>0</state> + </option> + <option> + <name>IlinkThreadsSlave</name> + <state>1</state> + </option> + <option> + <name>IlinkLogCallGraph</name> + <state>0</state> + </option> + <option> + <name>IlinkIcfFile_AltDefault</name> + <state /> + </option> + <option> + <name>IlinkEncInput</name> + <state>0</state> + </option> + <option> + <name>IlinkEncOutput</name> + <state>0</state> + </option> + <option> + <name>IlinkEncOutputBom</name> + <state>1</state> + </option> + <option> + <name>IlinkHeapSelect</name> + <state>1</state> + </option> + <option> + <name>IlinkLocaleSelect</name> + <state>1</state> + </option> + </data> + </settings> + <settings> + <name>IARCHIVE</name> + <archiveVersion>0</archiveVersion> + <data> + <version>0</version> + <wantNonLocal>1</wantNonLocal> + <debug>1</debug> + <option> + <name>IarchiveInputs</name> + <state /> + </option> + <option> + <name>IarchiveOverride</name> + <state>0</state> + </option> + <option> + <name>IarchiveOutput</name> + <state>###Unitialized###</state> + </option> + </data> + </settings> + <settings> + <name>BILINK</name> + <archiveVersion>0</archiveVersion> + <data /> + </settings> + </configuration> + <configuration> + <name>Release</name> + <toolchain> + <name>ARM</name> + </toolchain> + <debug>0</debug> + <settings> + <name>General</name> + <archiveVersion>3</archiveVersion> + <data> + <version>29</version> + <wantNonLocal>1</wantNonLocal> + <debug>0</debug> + <option> + <name>ExePath</name> + <state>Release\Exe</state> + </option> + <option> + <name>ObjPath</name> + <state>Release\Obj</state> + </option> + <option> + <name>ListPath</name> + <state>Release\List</state> + </option> + <option> + <name>GEndianMode</name> + <state>0</state> + </option> + <option> + <name>Input description</name> + <state /> + </option> + <option> + <name>Output description</name> + <state /> + </option> + <option> + <name>GOutputBinary</name> + <state>0</state> + </option> + <option> + <name>OGCoreOrChip</name> + <state>0</state> + </option> + <option> + <name>GRuntimeLibSelect</name> + <version>0</version> + <state>1</state> + </option> + <option> + <name>GRuntimeLibSelectSlave</name> + <version>0</version> + <state>1</state> + </option> + <option> + <name>RTDescription</name> + <state /> + </option> + <option> + <name>OGProductVersion</name> + <state>6.30.6.53380</state> + </option> + <option> + <name>OGLastSavedByProductVersion</name> + <state>8.11.3.13977</state> + </option> + <option> + <name>GeneralEnableMisra</name> + <state>0</state> + </option> + <option> + <name>GeneralMisraVerbose</name> + <state>0</state> + </option> + <option> + <name>OGChipSelectEditMenu</name> + <state>Default None</state> + </option> + <option> + <name>GenLowLevelInterface</name> + <state>0</state> + </option> + <option> + <name>GEndianModeBE</name> + <state>0</state> + </option> + <option> + <name>OGBufferedTerminalOutput</name> + <state>0</state> + </option> + <option> + <name>GenStdoutInterface</name> + <state>0</state> + </option> + <option> + <name>GeneralMisraRules98</name> + <version>0</version> + <state>1000111110110101101110011100111111101110011011000101110111101101100111111111111100110011111001110111001111111111111111111111111</state> + </option> + <option> + <name>GeneralMisraVer</name> + <state>0</state> + </option> + <option> + <name>GeneralMisraRules04</name> + <version>0</version> + <state>111101110010111111111000110111111111111111111111111110010111101111010101111111111111111111111111101111111011111001111011111011111111111111111</state> + </option> + <option> + <name>RTConfigPath2</name> + <state /> + </option> + <option> + <name>GBECoreSlave</name> + <version>25</version> + <state>1</state> + </option> + <option> + <name>OGUseCmsis</name> + <state>0</state> + </option> + <option> + <name>OGUseCmsisDspLib</name> + <state>0</state> + </option> + <option> + <name>GRuntimeLibThreads</name> + <state>0</state> + </option> + <option> + <name>CoreVariant</name> + <version>25</version> + <state>0</state> + </option> + <option> + <name>GFPUDeviceSlave</name> + <state>Default None</state> + </option> + <option> + <name>FPU2</name> + <version>0</version> + <state>0</state> + </option> + <option> + <name>NrRegs</name> + <version>0</version> + <state>0</state> + </option> + <option> + <name>NEON</name> + <state>0</state> + </option> + <option> + <name>GFPUCoreSlave2</name> + <version>25</version> + <state>0</state> + </option> + <option> + <name>OGCMSISPackSelectDevice</name> + </option> + <option> + <name>OgLibHeap</name> + <state>0</state> + </option> + <option> + <name>OGLibAdditionalLocale</name> + <state>0</state> + </option> + <option> + <name>OGPrintfVariant</name> + <version>0</version> + <state>0</state> + </option> + <option> + <name>OGPrintfMultibyteSupport</name> + <state>0</state> + </option> + <option> + <name>OGScanfVariant</name> + <version>0</version> + <state>0</state> + </option> + <option> + <name>OGScanfMultibyteSupport</name> + <state>0</state> + </option> + <option> + <name>GenLocaleTags</name> + <state /> + </option> + <option> + <name>GenLocaleDisplayOnly</name> + <state /> + </option> + <option> + <name>DSPExtension</name> + <state>0</state> + </option> + </data> + </settings> + <settings> + <name>ICCARM</name> + <archiveVersion>2</archiveVersion> + <data> + <version>34</version> + <wantNonLocal>1</wantNonLocal> + <debug>0</debug> + <option> + <name>CCOptimizationNoSizeConstraints</name> + <state>0</state> + </option> + <option> + <name>CCDefines</name> + </option> + <option> + <name>CCPreprocFile</name> + <state>0</state> + </option> + <option> + <name>CCPreprocComments</name> + <state>0</state> + </option> + <option> + <name>CCPreprocLine</name> + <state>0</state> + </option> + <option> + <name>CCListCFile</name> + <state>0</state> + </option> + <option> + <name>CCListCMnemonics</name> + <state>0</state> + </option> + <option> + <name>CCListCMessages</name> + <state>0</state> + </option> + <option> + <name>CCListAssFile</name> + <state>0</state> + </option> + <option> + <name>CCListAssSource</name> + <state>0</state> + </option> + <option> + <name>CCEnableRemarks</name> + <state>0</state> + </option> + <option> + <name>CCDiagSuppress</name> + <state /> + </option> + <option> + <name>CCDiagRemark</name> + <state /> + </option> + <option> + <name>CCDiagWarning</name> + <state /> + </option> + <option> + <name>CCDiagError</name> + <state /> + </option> + <option> + <name>CCObjPrefix</name> + <state>1</state> + </option> + <option> + <name>CCAllowList</name> + <version>1</version> + <state>11111110</state> + </option> + <option> + <name>CCDebugInfo</name> + <state>0</state> + </option> + <option> + <name>IEndianMode</name> + <state>1</state> + </option> + <option> + <name>IProcessor</name> + <state>1</state> + </option> + <option> + <name>IExtraOptionsCheck</name> + <state>0</state> + </option> + <option> + <name>IExtraOptions</name> + <state /> + </option> + <option> + <name>CCLangConformance</name> + <state>0</state> + </option> + <option> + <name>CCSignedPlainChar</name> + <state>1</state> + </option> + <option> + <name>CCRequirePrototypes</name> + <state>0</state> + </option> + <option> + <name>CCDiagWarnAreErr</name> + <state>0</state> + </option> + <option> + <name>CCCompilerRuntimeInfo</name> + <state>0</state> + </option> + <option> + <name>IFpuProcessor</name> + <state>1</state> + </option> + <option> + <name>OutputFile</name> + <state /> + </option> + <option> + <name>CCLibConfigHeader</name> + <state>1</state> + </option> + <option> + <name>PreInclude</name> + <state /> + </option> + <option> + <name>CompilerMisraOverride</name> + <state>0</state> + </option> + <option> + <name>CCIncludePath2</name> + <state /> + <state>$PROJ_DIR$\Libraries\XXX_StdPeriph_Driver</state> + <state>$PROJ_DIR$\applications</state> + <state>$PROJ_DIR$\Libraries\CMSIS\DeviceSupport</state> + <state>$PROJ_DIR$\drivers</state> + <state>$PROJ_DIR$\libcpu</state> + <state>$PROJ_DIR$\..\..\include</state> + <state>$PROJ_DIR$\..\..\libcpu\arm\cortex-m4</state> + <state>$PROJ_DIR$\..\..\components\drivers\include</state> + <state>$PROJ_DIR$\..\..\libcpu\arm\common</state> + <state>$PROJ_DIR$\.</state> + <state>$PROJ_DIR$\..\..\components\finsh</state> + <state>$PROJ_DIR$\Libraries\CMSIS\CoreSupport</state> + </option> + <option> + <name>CCStdIncCheck</name> + <state>0</state> + </option> + <option> + <name>CCCodeSection</name> + <state>.text</state> + </option> + <option> + <name>IProcessorMode2</name> + <state>1</state> + </option> + <option> + <name>CCOptLevel</name> + <state>3</state> + </option> + <option> + <name>CCOptStrategy</name> + <version>0</version> + <state>0</state> + </option> + <option> + <name>CCOptLevelSlave</name> + <state>1</state> + </option> + <option> + <name>CompilerMisraRules98</name> + <version>0</version> + <state>1000111110110101101110011100111111101110011011000101110111101101100111111111111100110011111001110111001111111111111111111111111</state> + </option> + <option> + <name>CompilerMisraRules04</name> + <version>0</version> + <state>111101110010111111111000110111111111111111111111111110010111101111010101111111111111111111111111101111111011111001111011111011111111111111111</state> + </option> + <option> + <name>CCPosIndRopi</name> + <state>0</state> + </option> + <option> + <name>CCPosIndRwpi</name> + <state>0</state> + </option> + <option> + <name>CCPosIndNoDynInit</name> + <state>0</state> + </option> + <option> + <name>IccLang</name> + <state>0</state> + </option> + <option> + <name>IccCDialect</name> + <state>1</state> + </option> + <option> + <name>IccAllowVLA</name> + <state>0</state> + </option> + <option> + <name>IccStaticDestr</name> + <state>1</state> + </option> + <option> + <name>IccCppInlineSemantics</name> + <state>0</state> + </option> + <option> + <name>IccCmsis</name> + <state>1</state> + </option> + <option> + <name>IccFloatSemantics</name> + <state>0</state> + </option> + <option> + <name>CCNoLiteralPool</name> + <state>0</state> + </option> + <option> + <name>CCOptStrategySlave</name> + <version>0</version> + <state>0</state> + </option> + <option> + <name>CCGuardCalls</name> + <state>1</state> + </option> + <option> + <name>CCEncSource</name> + <state>0</state> + </option> + <option> + <name>CCEncOutput</name> + <state>0</state> + </option> + <option> + <name>CCEncOutputBom</name> + <state>1</state> + </option> + <option> + <name>CCEncInput</name> + <state>0</state> + </option> + <option> + <name>IccExceptions2</name> + <state>0</state> + </option> + <option> + <name>IccRTTI2</name> + <state>0</state> + </option> + </data> + </settings> + <settings> + <name>AARM</name> + <archiveVersion>2</archiveVersion> + <data> + <version>10</version> + <wantNonLocal>1</wantNonLocal> + <debug>0</debug> + <option> + <name>AObjPrefix</name> + <state>1</state> + </option> + <option> + <name>AEndian</name> + <state>1</state> + </option> + <option> + <name>ACaseSensitivity</name> + <state>1</state> + </option> + <option> + <name>MacroChars</name> + <version>0</version> + <state>0</state> + </option> + <option> + <name>AWarnEnable</name> + <state>0</state> + </option> + <option> + <name>AWarnWhat</name> + <state>0</state> + </option> + <option> + <name>AWarnOne</name> + <state /> + </option> + <option> + <name>AWarnRange1</name> + <state /> + </option> + <option> + <name>AWarnRange2</name> + <state /> + </option> + <option> + <name>ADebug</name> + <state>0</state> + </option> + <option> + <name>AltRegisterNames</name> + <state>0</state> + </option> + <option> + <name>ADefines</name> + <state /> + </option> + <option> + <name>AList</name> + <state>0</state> + </option> + <option> + <name>AListHeader</name> + <state>1</state> + </option> + <option> + <name>AListing</name> + <state>1</state> + </option> + <option> + <name>Includes</name> + <state>0</state> + </option> + <option> + <name>MacDefs</name> + <state>0</state> + </option> + <option> + <name>MacExps</name> + <state>1</state> + </option> + <option> + <name>MacExec</name> + <state>0</state> + </option> + <option> + <name>OnlyAssed</name> + <state>0</state> + </option> + <option> + <name>MultiLine</name> + <state>0</state> + </option> + <option> + <name>PageLengthCheck</name> + <state>0</state> + </option> + <option> + <name>PageLength</name> + <state>80</state> + </option> + <option> + <name>TabSpacing</name> + <state>8</state> + </option> + <option> + <name>AXRef</name> + <state>0</state> + </option> + <option> + <name>AXRefDefines</name> + <state>0</state> + </option> + <option> + <name>AXRefInternal</name> + <state>0</state> + </option> + <option> + <name>AXRefDual</name> + <state>0</state> + </option> + <option> + <name>AProcessor</name> + <state>1</state> + </option> + <option> + <name>AFpuProcessor</name> + <state>1</state> + </option> + <option> + <name>AOutputFile</name> + <state /> + </option> + <option> + <name>ALimitErrorsCheck</name> + <state>0</state> + </option> + <option> + <name>ALimitErrorsEdit</name> + <state>100</state> + </option> + <option> + <name>AIgnoreStdInclude</name> + <state>0</state> + </option> + <option> + <name>AUserIncludes</name> + <state /> + </option> + <option> + <name>AExtraOptionsCheckV2</name> + <state>0</state> + </option> + <option> + <name>AExtraOptionsV2</name> + <state /> + </option> + <option> + <name>AsmNoLiteralPool</name> + <state>0</state> + </option> + </data> + </settings> + <settings> + <name>OBJCOPY</name> + <archiveVersion>0</archiveVersion> + <data> + <version>1</version> + <wantNonLocal>1</wantNonLocal> + <debug>0</debug> + <option> + <name>OOCOutputFormat</name> + <version>3</version> + <state>0</state> + </option> + <option> + <name>OCOutputOverride</name> + <state>0</state> + </option> + <option> + <name>OOCOutputFile</name> + <state /> + </option> + <option> + <name>OOCCommandLineProducer</name> + <state>1</state> + </option> + <option> + <name>OOCObjCopyEnable</name> + <state>0</state> + </option> + </data> + </settings> + <settings> + <name>CUSTOM</name> + <archiveVersion>3</archiveVersion> + <data> + <extensions /> + <cmdline /> + <hasPrio>0</hasPrio> + </data> + </settings> + <settings> + <name>BICOMP</name> + <archiveVersion>0</archiveVersion> + <data /> + </settings> + <settings> + <name>BUILDACTION</name> + <archiveVersion>1</archiveVersion> + <data> + <prebuild /> + <postbuild /> + </data> + </settings> + <settings> + <name>ILINK</name> + <archiveVersion>0</archiveVersion> + <data> + <version>20</version> + <wantNonLocal>1</wantNonLocal> + <debug>0</debug> + <option> + <name>IlinkLibIOConfig</name> + <state>1</state> + </option> + <option> + <name>XLinkMisraHandler</name> + <state>0</state> + </option> + <option> + <name>IlinkInputFileSlave</name> + <state>0</state> + </option> + <option> + <name>IlinkOutputFile</name> + <state>###Unitialized###</state> + </option> + <option> + <name>IlinkDebugInfoEnable</name> + <state>1</state> + </option> + <option> + <name>IlinkKeepSymbols</name> + <state /> + </option> + <option> + <name>IlinkRawBinaryFile</name> + <state /> + </option> + <option> + <name>IlinkRawBinarySymbol</name> + <state /> + </option> + <option> + <name>IlinkRawBinarySegment</name> + <state /> + </option> + <option> + <name>IlinkRawBinaryAlign</name> + <state /> + </option> + <option> + <name>IlinkDefines</name> + <state /> + </option> + <option> + <name>IlinkConfigDefines</name> + <state /> + </option> + <option> + <name>IlinkMapFile</name> + <state>0</state> + </option> + <option> + <name>IlinkLogFile</name> + <state>0</state> + </option> + <option> + <name>IlinkLogInitialization</name> + <state>0</state> + </option> + <option> + <name>IlinkLogModule</name> + <state>0</state> + </option> + <option> + <name>IlinkLogSection</name> + <state>0</state> + </option> + <option> + <name>IlinkLogVeneer</name> + <state>0</state> + </option> + <option> + <name>IlinkIcfOverride</name> + <state>0</state> + </option> + <option> + <name>IlinkIcfFile</name> + <state>lnk0t.icf</state> + </option> + <option> + <name>IlinkIcfFileSlave</name> + <state /> + </option> + <option> + <name>IlinkEnableRemarks</name> + <state>0</state> + </option> + <option> + <name>IlinkSuppressDiags</name> + <state /> + </option> + <option> + <name>IlinkTreatAsRem</name> + <state /> + </option> + <option> + <name>IlinkTreatAsWarn</name> + <state /> + </option> + <option> + <name>IlinkTreatAsErr</name> + <state /> + </option> + <option> + <name>IlinkWarningsAreErrors</name> + <state>0</state> + </option> + <option> + <name>IlinkUseExtraOptions</name> + <state>0</state> + </option> + <option> + <name>IlinkExtraOptions</name> + <state /> + </option> + <option> + <name>IlinkLowLevelInterfaceSlave</name> + <state>1</state> + </option> + <option> + <name>IlinkAutoLibEnable</name> + <state>1</state> + </option> + <option> + <name>IlinkAdditionalLibs</name> + <state /> + </option> + <option> + <name>IlinkOverrideProgramEntryLabel</name> + <state>0</state> + </option> + <option> + <name>IlinkProgramEntryLabelSelect</name> + <state>0</state> + </option> + <option> + <name>IlinkProgramEntryLabel</name> + <state /> + </option> + <option> + <name>DoFill</name> + <state>0</state> + </option> + <option> + <name>FillerByte</name> + <state>0xFF</state> + </option> + <option> + <name>FillerStart</name> + <state>0x0</state> + </option> + <option> + <name>FillerEnd</name> + <state>0x0</state> + </option> + <option> + <name>CrcSize</name> + <version>0</version> + <state>1</state> + </option> + <option> + <name>CrcAlign</name> + <state>1</state> + </option> + <option> + <name>CrcPoly</name> + <state>0x11021</state> + </option> + <option> + <name>CrcCompl</name> + <version>0</version> + <state>0</state> + </option> + <option> + <name>CrcBitOrder</name> + <version>0</version> + <state>0</state> + </option> + <option> + <name>CrcInitialValue</name> + <state>0x0</state> + </option> + <option> + <name>DoCrc</name> + <state>0</state> + </option> + <option> + <name>IlinkBE8Slave</name> + <state>1</state> + </option> + <option> + <name>IlinkBufferedTerminalOutput</name> + <state>1</state> + </option> + <option> + <name>IlinkStdoutInterfaceSlave</name> + <state>1</state> + </option> + <option> + <name>CrcFullSize</name> + <state>0</state> + </option> + <option> + <name>IlinkIElfToolPostProcess</name> + <state>0</state> + </option> + <option> + <name>IlinkLogAutoLibSelect</name> + <state>0</state> + </option> + <option> + <name>IlinkLogRedirSymbols</name> + <state>0</state> + </option> + <option> + <name>IlinkLogUnusedFragments</name> + <state>0</state> + </option> + <option> + <name>IlinkCrcReverseByteOrder</name> + <state>0</state> + </option> + <option> + <name>IlinkCrcUseAsInput</name> + <state>1</state> + </option> + <option> + <name>IlinkOptInline</name> + <state>1</state> + </option> + <option> + <name>IlinkOptExceptionsAllow</name> + <state>1</state> + </option> + <option> + <name>IlinkOptExceptionsForce</name> + <state>0</state> + </option> + <option> + <name>IlinkCmsis</name> + <state>1</state> + </option> + <option> + <name>IlinkOptMergeDuplSections</name> + <state>0</state> + </option> + <option> + <name>IlinkOptUseVfe</name> + <state>1</state> + </option> + <option> + <name>IlinkOptForceVfe</name> + <state>0</state> + </option> + <option> + <name>IlinkStackAnalysisEnable</name> + <state>0</state> + </option> + <option> + <name>IlinkStackControlFile</name> + <state /> + </option> + <option> + <name>IlinkStackCallGraphFile</name> + <state /> + </option> + <option> + <name>CrcAlgorithm</name> + <version>1</version> + <state>1</state> + </option> + <option> + <name>CrcUnitSize</name> + <version>0</version> + <state>0</state> + </option> + <option> + <name>IlinkThreadsSlave</name> + <state>1</state> + </option> + <option> + <name>IlinkLogCallGraph</name> + <state>0</state> + </option> + <option> + <name>IlinkIcfFile_AltDefault</name> + <state /> + </option> + <option> + <name>IlinkEncInput</name> + <state>0</state> + </option> + <option> + <name>IlinkEncOutput</name> + <state>0</state> + </option> + <option> + <name>IlinkEncOutputBom</name> + <state>1</state> + </option> + <option> + <name>IlinkHeapSelect</name> + <state>1</state> + </option> + <option> + <name>IlinkLocaleSelect</name> + <state>1</state> + </option> + </data> + </settings> + <settings> + <name>IARCHIVE</name> + <archiveVersion>0</archiveVersion> + <data> + <version>0</version> + <wantNonLocal>1</wantNonLocal> + <debug>0</debug> + <option> + <name>IarchiveInputs</name> + <state /> + </option> + <option> + <name>IarchiveOverride</name> + <state>0</state> + </option> + <option> + <name>IarchiveOutput</name> + <state>###Unitialized###</state> + </option> + </data> + </settings> + <settings> + <name>BILINK</name> + <archiveVersion>0</archiveVersion> + <data /> + </settings> + </configuration> + <group> + <name>Kernel</name> + <file> + <name>$PROJ_DIR$\..\..\src\clock.c</name> + </file> + <file> + <name>$PROJ_DIR$\..\..\src\components.c</name> + </file> + <file> + <name>$PROJ_DIR$\..\..\src\cpu.c</name> + </file> + <file> + <name>$PROJ_DIR$\..\..\src\device.c</name> + </file> + <file> + <name>$PROJ_DIR$\..\..\src\idle.c</name> + </file> + <file> + <name>$PROJ_DIR$\..\..\src\ipc.c</name> + </file> + <file> + <name>$PROJ_DIR$\..\..\src\irq.c</name> + </file> + <file> + <name>$PROJ_DIR$\..\..\src\kservice.c</name> + </file> + <file> + <name>$PROJ_DIR$\..\..\src\mem.c</name> + </file> + <file> + <name>$PROJ_DIR$\..\..\src\mempool.c</name> + </file> + <file> + <name>$PROJ_DIR$\..\..\src\object.c</name> + </file> + <file> + <name>$PROJ_DIR$\..\..\src\scheduler.c</name> + </file> + <file> + <name>$PROJ_DIR$\..\..\src\signal.c</name> + </file> + <file> + <name>$PROJ_DIR$\..\..\src\thread.c</name> + </file> + <file> + <name>$PROJ_DIR$\..\..\src\timer.c</name> + </file> + </group> + <group> + <name>Applications</name> + <file> + <name>$PROJ_DIR$\applications\main.c</name> + </file> + <file> + <name>$PROJ_DIR$\applications\mnt.c</name> + </file> + </group> + <group> + <name>Drivers</name> + <file> + <name>$PROJ_DIR$\drivers\board.c</name> + </file> + <file> + <name>$PROJ_DIR$\drivers\drv_uart.c</name> + </file> + </group> + <group> + <name>CPU</name> + <file> + <name>$PROJ_DIR$\libcpu\port.c</name> + </file> + </group> + <group> + <name>Libraries</name> + <file> + <name>$PROJ_DIR$\Libraries\CMSIS\startup_xxx.s</name> + </file> + </group> + <group> + <name>cpu</name> + <file> + <name>$PROJ_DIR$\..\..\libcpu\arm\common\backtrace.c</name> + </file> + <file> + <name>$PROJ_DIR$\..\..\libcpu\arm\common\div0.c</name> + </file> + <file> + <name>$PROJ_DIR$\..\..\libcpu\arm\common\showmem.c</name> + </file> + <file> + <name>$PROJ_DIR$\..\..\libcpu\arm\cortex-m4\cpuport.c</name> + </file> + <file> + <name>$PROJ_DIR$\..\..\libcpu\arm\cortex-m4\context_iar.S</name> + </file> + </group> + <group> + <name>DeviceDrivers</name> + <file> + <name>$PROJ_DIR$\..\..\components\drivers\misc\pin.c</name> + </file> + <file> + <name>$PROJ_DIR$\..\..\components\drivers\serial\serial.c</name> + </file> + <file> + <name>$PROJ_DIR$\..\..\components\drivers\src\completion.c</name> + </file> + <file> + <name>$PROJ_DIR$\..\..\components\drivers\src\dataqueue.c</name> + </file> + <file> + <name>$PROJ_DIR$\..\..\components\drivers\src\pipe.c</name> + </file> + <file> + <name>$PROJ_DIR$\..\..\components\drivers\src\ringblk_buf.c</name> + </file> + <file> + <name>$PROJ_DIR$\..\..\components\drivers\src\ringbuffer.c</name> + </file> + <file> + <name>$PROJ_DIR$\..\..\components\drivers\src\waitqueue.c</name> + </file> + <file> + <name>$PROJ_DIR$\..\..\components\drivers\src\workqueue.c</name> + </file> + </group> + <group> + <name>finsh</name> + <file> + <name>$PROJ_DIR$\..\..\components\finsh\shell.c</name> + </file> + <file> + <name>$PROJ_DIR$\..\..\components\finsh\symbol.c</name> + </file> + <file> + <name>$PROJ_DIR$\..\..\components\finsh\cmd.c</name> + </file> + <file> + <name>$PROJ_DIR$\..\..\components\finsh\msh.c</name> + </file> + <file> + <name>$PROJ_DIR$\..\..\components\finsh\msh_cmd.c</name> + </file> + <file> + <name>$PROJ_DIR$\..\..\components\finsh\msh_file.c</name> + </file> + <file> + <name>$PROJ_DIR$\..\..\components\finsh\finsh_compiler.c</name> + </file> + <file> + <name>$PROJ_DIR$\..\..\components\finsh\finsh_error.c</name> + </file> + <file> + <name>$PROJ_DIR$\..\..\components\finsh\finsh_heap.c</name> + </file> + <file> + <name>$PROJ_DIR$\..\..\components\finsh\finsh_init.c</name> + </file> + <file> + <name>$PROJ_DIR$\..\..\components\finsh\finsh_node.c</name> + </file> + <file> + <name>$PROJ_DIR$\..\..\components\finsh\finsh_ops.c</name> + </file> + <file> + <name>$PROJ_DIR$\..\..\components\finsh\finsh_parser.c</name> + </file> + <file> + <name>$PROJ_DIR$\..\..\components\finsh\finsh_var.c</name> + </file> + <file> + <name>$PROJ_DIR$\..\..\components\finsh\finsh_vm.c</name> + </file> + <file> + <name>$PROJ_DIR$\..\..\components\finsh\finsh_token.c</name> + </file> + </group> +</project> diff --git a/bsp/swm320-lq100/project.eww b/bsp/swm320-lq100/project.eww index c2cb02eb1e..faa93f37cd 100644 --- a/bsp/swm320-lq100/project.eww +++ b/bsp/swm320-lq100/project.eww @@ -1,10 +1,10 @@ -<?xml version="1.0" encoding="iso-8859-1"?>
-
-<workspace>
- <project>
- <path>$WS_DIR$\project.ewp</path>
- </project>
- <batchBuild/>
-</workspace>
-
-
+<?xml version="1.0" encoding="iso-8859-1"?> + +<workspace> + <project> + <path>$WS_DIR$\project.ewp</path> + </project> + <batchBuild/> +</workspace> + + diff --git a/bsp/swm320-lq100/project.uvopt b/bsp/swm320-lq100/project.uvopt new file mode 100644 index 0000000000..068ac9af69 --- /dev/null +++ b/bsp/swm320-lq100/project.uvopt @@ -0,0 +1,162 @@ +<?xml version="1.0" encoding="UTF-8" standalone="no" ?> +<ProjectOpt xmlns:xsi="http://www.w3.org/2001/XMLSchema-instance" xsi:noNamespaceSchemaLocation="project_opt.xsd"> + + <SchemaVersion>1.0</SchemaVersion> + + <Header>### uVision Project, (C) Keil Software</Header> + + <Extensions> + <cExt>*.c</cExt> + <aExt>*.s*; *.src; *.a*</aExt> + <oExt>*.obj</oExt> + <lExt>*.lib</lExt> + <tExt>*.txt; *.h; *.inc</tExt> + <pExt>*.plm</pExt> + <CppX>*.cpp</CppX> + </Extensions> + + <DaveTm> + <dwLowDateTime>0</dwLowDateTime> + <dwHighDateTime>0</dwHighDateTime> + </DaveTm> + + <Target> + <TargetName>rtthread</TargetName> + <ToolsetNumber>0x4</ToolsetNumber> + <ToolsetName>ARM-ADS</ToolsetName> + <TargetOption> + <CLKADS>25000000</CLKADS> + <OPTTT> + <gFlags>1</gFlags> + <BeepAtEnd>1</BeepAtEnd> + <RunSim>1</RunSim> + <RunTarget>0</RunTarget> + </OPTTT> + <OPTHX> + <HexSelection>1</HexSelection> + <FlashByte>65535</FlashByte> + <HexRangeLowAddress>0</HexRangeLowAddress> + <HexRangeHighAddress>0</HexRangeHighAddress> + <HexOffset>0</HexOffset> + </OPTHX> + <OPTLEX> + <PageWidth>79</PageWidth> + <PageLength>66</PageLength> + <TabStop>8</TabStop> + <ListingPath>.\build\keil\List\</ListingPath> + </OPTLEX> + <ListingPage> + <CreateCListing>1</CreateCListing> + <CreateAListing>1</CreateAListing> + <CreateLListing>1</CreateLListing> + <CreateIListing>0</CreateIListing> + <AsmCond>1</AsmCond> + <AsmSymb>1</AsmSymb> + <AsmXref>0</AsmXref> + <CCond>1</CCond> + <CCode>0</CCode> + <CListInc>0</CListInc> + <CSymb>0</CSymb> + <LinkerCodeListing>0</LinkerCodeListing> + </ListingPage> + <OPTXL> + <LMap>1</LMap> + <LComments>1</LComments> + <LGenerateSymbols>1</LGenerateSymbols> + <LLibSym>1</LLibSym> + <LLines>1</LLines> + <LLocSym>1</LLocSym> + <LPubSym>1</LPubSym> + <LXref>0</LXref> + <LExpSel>0</LExpSel> + </OPTXL> + <OPTFL> + <tvExp>0</tvExp> + <tvExpOptDlg>0</tvExpOptDlg> + <IsCurrentTarget>1</IsCurrentTarget> + </OPTFL> + <CpuCode>255</CpuCode> + <DebugOpt> + <uSim>0</uSim> + <uTrg>1</uTrg> + <sLdApp>1</sLdApp> + <sGomain>1</sGomain> + <sRbreak>1</sRbreak> + <sRwatch>1</sRwatch> + <sRmem>1</sRmem> + <sRfunc>1</sRfunc> + <sRbox>1</sRbox> + <tLdApp>1</tLdApp> + <tGomain>1</tGomain> + <tRbreak>1</tRbreak> + <tRwatch>1</tRwatch> + <tRmem>1</tRmem> + <tRfunc>0</tRfunc> + <tRbox>1</tRbox> + <tRtrace>0</tRtrace> + <sRSysVw>1</sRSysVw> + <tRSysVw>1</tRSysVw> + <tPdscDbg>0</tPdscDbg> + <sRunDeb>0</sRunDeb> + <sLrtime>0</sLrtime> + <nTsel>6</nTsel> + <sDll></sDll> + <sDllPa></sDllPa> + <sDlgDll></sDlgDll> + <sDlgPa></sDlgPa> + <sIfile></sIfile> + <tDll></tDll> + <tDllPa></tDllPa> + <tDlgDll></tDlgDll> + <tDlgPa></tDlgPa> + <tIfile></tIfile> + <pMon>Segger\JL2CM3.dll</pMon> + </DebugOpt> + <TargetDriverDllRegistry> + <SetRegEntry> + <Number>0</Number> + <Key>JL2CM3</Key> + <Name>-U30000299 -O207 -S0 -A0 -C0 -JU1 -JI127.0.0.1 -JP0 -RST0 -N00("ARM CoreSight SW-DP") -D00(2BA01477) -L00(0) -TO18 -TC10000000 -TP21 -TDS8001 -TDT0 -TDC1F -TIEFFFFFFFF -TIP8 -TB1 -TFE0 -FO15 -FD20000000 -FC800 -FN1 -FF0STM32F4xx_1024 -FS08000000 -FL0100000</Name> + </SetRegEntry> + <SetRegEntry> + <Number>0</Number> + <Key>UL2CM3</Key> + <Name>UL2CM3(-O207 -S0 -C0 -FO7 -FD20000000 -FC800 -FN1 -FF0STM32F4xx_1024 -FS08000000 -FL0100000)</Name> + </SetRegEntry> + </TargetDriverDllRegistry> + <Breakpoint/> + <Tracepoint> + <THDelay>0</THDelay> + </Tracepoint> + <DebugFlag> + <trace>0</trace> + <periodic>0</periodic> + <aLwin>0</aLwin> + <aCover>0</aCover> + <aSer1>0</aSer1> + <aSer2>0</aSer2> + <aPa>0</aPa> + <viewmode>0</viewmode> + <vrSel>0</vrSel> + <aSym>0</aSym> + <aTbox>0</aTbox> + <AscS1>0</AscS1> + <AscS2>0</AscS2> + <AscS3>0</AscS3> + <aSer3>0</aSer3> + <eProf>0</eProf> + <aLa>0</aLa> + <aPa1>0</aPa1> + <AscS4>0</AscS4> + <aSer4>0</aSer4> + <StkLoc>0</StkLoc> + <TrcWin>0</TrcWin> + <newCpu>0</newCpu> + <uProt>0</uProt> + </DebugFlag> + <LintExecutable></LintExecutable> + <LintConfigFile></LintConfigFile> + </TargetOption> + </Target> + +</ProjectOpt> diff --git a/bsp/swm320-lq100/project.uvoptx b/bsp/swm320-lq100/project.uvoptx index bc15f1d325..068d0fa5f4 100644 --- a/bsp/swm320-lq100/project.uvoptx +++ b/bsp/swm320-lq100/project.uvoptx @@ -10,7 +10,7 @@ <aExt>*.s*; *.src; *.a*</aExt> <oExt>*.obj; *.o</oExt> <lExt>*.lib</lExt> - <tExt>*.txt; *.h; *.inc</tExt> + <tExt>*.txt; *.h; *.inc; *.md</tExt> <pExt>*.plm</pExt> <CppX>*.cpp</CppX> <nMigrate>0</nMigrate> @@ -22,7 +22,7 @@ </DaveTm> <Target> - <TargetName>rt-thread</TargetName> + <TargetName>rtthread</TargetName> <ToolsetNumber>0x4</ToolsetNumber> <ToolsetName>ARM-ADS</ToolsetName> <TargetOption> @@ -45,7 +45,7 @@ <PageWidth>79</PageWidth> <PageLength>66</PageLength> <TabStop>8</TabStop> - <ListingPath>.\build\</ListingPath> + <ListingPath>.\build\keil\List\</ListingPath> </OPTLEX> <ListingPage> <CreateCListing>1</CreateCListing> @@ -73,7 +73,7 @@ <LExpSel>0</LExpSel> </OPTXL> <OPTFL> - <tvExp>0</tvExp> + <tvExp>1</tvExp> <tvExpOptDlg>0</tvExpOptDlg> <IsCurrentTarget>1</IsCurrentTarget> </OPTFL> @@ -120,12 +120,12 @@ <SetRegEntry> <Number>0</Number> <Key>UL2CM3</Key> - <Name>UL2CM3(-S0 -C0 -P0 -FN1 -FC1000 -FD20000000 -FF0SWM320xE -FL080000 -FS00 -FP0($$Device:SWM320xE$Flash\SWM320xE.FLM)</Name> + <Name>UL2CM3(-S0 -C0 -P0 ) -FN1 -FC1000 -FD20000000 -FF0SWM320xE -FL080000 -FS00 -FP0($$Device:SWM320xE$Flash\SWM320xE.FLM)</Name> </SetRegEntry> <SetRegEntry> <Number>0</Number> <Key>JL2CM3</Key> - <Name>-U30000299 -O78 -S2 -ZTIFSpeedSel5000 -A0 -C0 -JU1 -JI127.0.0.1 -JP0 -RST0 -N00("ARM CoreSight SW-DP") -D00(2BA01477) -L00(0) -TO18 -TC10000000 -TP21 -TDS8002 -TDT0 -TDC1F -TIEFFFFFFFF -TIP8 -TB1 -TFE0 -FO15 -FD20000000 -FC4000 -FN1 -FF0SWM320xE -FS00 -FL080000 -FP0($$Device:SWM320xE$Flash\SWM320xE.FLM)</Name> + <Name>-U30000299 -O78 -S2 -ZTIFSpeedSel5000 -A0 -C0 -JU1 -JI127.0.0.1 -JP0 -RST0 -N00("ARM CoreSight SW-DP") -D00(2BA01477) -L00(4) -TO18 -TC10000000 -TP21 -TDS8001 -TDT0 -TDC1F -TIEFFFFFFFF -TIP8 -TB1 -TFE0 -FO15 -FD20000000 -FC4000 -FN1 -FF0SWM320xE -FS00 -FL080000 -FP0($$Device:SWM320xE$Flash\SWM320xE.FLM)</Name> </SetRegEntry> </TargetDriverDllRegistry> <Breakpoint/> @@ -174,4 +174,800 @@ </TargetOption> </Target> + <Group> + <GroupName>Applications</GroupName> + <tvExp>0</tvExp> + <tvExpOptDlg>0</tvExpOptDlg> + <cbSel>0</cbSel> + <RteFlg>0</RteFlg> + <File> + <GroupNumber>1</GroupNumber> + <FileNumber>1</FileNumber> + <FileType>1</FileType> + <tvExp>0</tvExp> + <tvExpOptDlg>0</tvExpOptDlg> + <bDave2>0</bDave2> + <PathWithFileName>applications\main.c</PathWithFileName> + <FilenameWithoutPath>main.c</FilenameWithoutPath> + <RteFlg>0</RteFlg> + <bShared>0</bShared> + </File> + </Group> + + <Group> + <GroupName>CPU</GroupName> + <tvExp>0</tvExp> + <tvExpOptDlg>0</tvExpOptDlg> + <cbSel>0</cbSel> + <RteFlg>0</RteFlg> + <File> + <GroupNumber>2</GroupNumber> + <FileNumber>2</FileNumber> + <FileType>1</FileType> + <tvExp>0</tvExp> + <tvExpOptDlg>0</tvExpOptDlg> + <bDave2>0</bDave2> + <PathWithFileName>..\..\libcpu\arm\common\backtrace.c</PathWithFileName> + <FilenameWithoutPath>backtrace.c</FilenameWithoutPath> + <RteFlg>0</RteFlg> + <bShared>0</bShared> + </File> + <File> + <GroupNumber>2</GroupNumber> + <FileNumber>3</FileNumber> + <FileType>1</FileType> + <tvExp>0</tvExp> + <tvExpOptDlg>0</tvExpOptDlg> + <bDave2>0</bDave2> + <PathWithFileName>..\..\libcpu\arm\common\showmem.c</PathWithFileName> + <FilenameWithoutPath>showmem.c</FilenameWithoutPath> + <RteFlg>0</RteFlg> + <bShared>0</bShared> + </File> + <File> + <GroupNumber>2</GroupNumber> + <FileNumber>4</FileNumber> + <FileType>1</FileType> + <tvExp>0</tvExp> + <tvExpOptDlg>0</tvExpOptDlg> + <bDave2>0</bDave2> + <PathWithFileName>..\..\libcpu\arm\common\div0.c</PathWithFileName> + <FilenameWithoutPath>div0.c</FilenameWithoutPath> + <RteFlg>0</RteFlg> + <bShared>0</bShared> + </File> + <File> + <GroupNumber>2</GroupNumber> + <FileNumber>5</FileNumber> + <FileType>2</FileType> + <tvExp>0</tvExp> + <tvExpOptDlg>0</tvExpOptDlg> + <bDave2>0</bDave2> + <PathWithFileName>..\..\libcpu\arm\cortex-m4\context_rvds.S</PathWithFileName> + <FilenameWithoutPath>context_rvds.S</FilenameWithoutPath> + <RteFlg>0</RteFlg> + <bShared>0</bShared> + </File> + <File> + <GroupNumber>2</GroupNumber> + <FileNumber>6</FileNumber> + <FileType>1</FileType> + <tvExp>0</tvExp> + <tvExpOptDlg>0</tvExpOptDlg> + <bDave2>0</bDave2> + <PathWithFileName>..\..\libcpu\arm\cortex-m4\cpuport.c</PathWithFileName> + <FilenameWithoutPath>cpuport.c</FilenameWithoutPath> + <RteFlg>0</RteFlg> + <bShared>0</bShared> + </File> + </Group> + + <Group> + <GroupName>DeviceDrivers</GroupName> + <tvExp>0</tvExp> + <tvExpOptDlg>0</tvExpOptDlg> + <cbSel>0</cbSel> + <RteFlg>0</RteFlg> + <File> + <GroupNumber>3</GroupNumber> + <FileNumber>7</FileNumber> + <FileType>1</FileType> + <tvExp>0</tvExp> + <tvExpOptDlg>0</tvExpOptDlg> + <bDave2>0</bDave2> + <PathWithFileName>..\..\components\drivers\misc\pin.c</PathWithFileName> + <FilenameWithoutPath>pin.c</FilenameWithoutPath> + <RteFlg>0</RteFlg> + <bShared>0</bShared> + </File> + <File> + <GroupNumber>3</GroupNumber> + <FileNumber>8</FileNumber> + <FileType>1</FileType> + <tvExp>0</tvExp> + <tvExpOptDlg>0</tvExpOptDlg> + <bDave2>0</bDave2> + <PathWithFileName>..\..\components\drivers\serial\serial.c</PathWithFileName> + <FilenameWithoutPath>serial.c</FilenameWithoutPath> + <RteFlg>0</RteFlg> + <bShared>0</bShared> + </File> + <File> + <GroupNumber>3</GroupNumber> + <FileNumber>9</FileNumber> + <FileType>1</FileType> + <tvExp>0</tvExp> + <tvExpOptDlg>0</tvExpOptDlg> + <bDave2>0</bDave2> + <PathWithFileName>..\..\components\drivers\src\completion.c</PathWithFileName> + <FilenameWithoutPath>completion.c</FilenameWithoutPath> + <RteFlg>0</RteFlg> + <bShared>0</bShared> + </File> + <File> + <GroupNumber>3</GroupNumber> + <FileNumber>10</FileNumber> + <FileType>1</FileType> + <tvExp>0</tvExp> + <tvExpOptDlg>0</tvExpOptDlg> + <bDave2>0</bDave2> + <PathWithFileName>..\..\components\drivers\src\ringbuffer.c</PathWithFileName> + <FilenameWithoutPath>ringbuffer.c</FilenameWithoutPath> + <RteFlg>0</RteFlg> + <bShared>0</bShared> + </File> + <File> + <GroupNumber>3</GroupNumber> + <FileNumber>11</FileNumber> + <FileType>1</FileType> + <tvExp>0</tvExp> + <tvExpOptDlg>0</tvExpOptDlg> + <bDave2>0</bDave2> + <PathWithFileName>..\..\components\drivers\src\waitqueue.c</PathWithFileName> + <FilenameWithoutPath>waitqueue.c</FilenameWithoutPath> + <RteFlg>0</RteFlg> + <bShared>0</bShared> + </File> + <File> + <GroupNumber>3</GroupNumber> + <FileNumber>12</FileNumber> + <FileType>1</FileType> + <tvExp>0</tvExp> + <tvExpOptDlg>0</tvExpOptDlg> + <bDave2>0</bDave2> + <PathWithFileName>..\..\components\drivers\src\workqueue.c</PathWithFileName> + <FilenameWithoutPath>workqueue.c</FilenameWithoutPath> + <RteFlg>0</RteFlg> + <bShared>0</bShared> + </File> + <File> + <GroupNumber>3</GroupNumber> + <FileNumber>13</FileNumber> + <FileType>1</FileType> + <tvExp>0</tvExp> + <tvExpOptDlg>0</tvExpOptDlg> + <bDave2>0</bDave2> + <PathWithFileName>..\..\components\drivers\src\ringblk_buf.c</PathWithFileName> + <FilenameWithoutPath>ringblk_buf.c</FilenameWithoutPath> + <RteFlg>0</RteFlg> + <bShared>0</bShared> + </File> + <File> + <GroupNumber>3</GroupNumber> + <FileNumber>14</FileNumber> + <FileType>1</FileType> + <tvExp>0</tvExp> + <tvExpOptDlg>0</tvExpOptDlg> + <bDave2>0</bDave2> + <PathWithFileName>..\..\components\drivers\src\dataqueue.c</PathWithFileName> + <FilenameWithoutPath>dataqueue.c</FilenameWithoutPath> + <RteFlg>0</RteFlg> + <bShared>0</bShared> + </File> + <File> + <GroupNumber>3</GroupNumber> + <FileNumber>15</FileNumber> + <FileType>1</FileType> + <tvExp>0</tvExp> + <tvExpOptDlg>0</tvExpOptDlg> + <bDave2>0</bDave2> + <PathWithFileName>..\..\components\drivers\src\pipe.c</PathWithFileName> + <FilenameWithoutPath>pipe.c</FilenameWithoutPath> + <RteFlg>0</RteFlg> + <bShared>0</bShared> + </File> + </Group> + + <Group> + <GroupName>Drivers</GroupName> + <tvExp>0</tvExp> + <tvExpOptDlg>0</tvExpOptDlg> + <cbSel>0</cbSel> + <RteFlg>0</RteFlg> + <File> + <GroupNumber>4</GroupNumber> + <FileNumber>16</FileNumber> + <FileType>1</FileType> + <tvExp>0</tvExp> + <tvExpOptDlg>0</tvExpOptDlg> + <bDave2>0</bDave2> + <PathWithFileName>drivers\drv_gpio.c</PathWithFileName> + <FilenameWithoutPath>drv_gpio.c</FilenameWithoutPath> + <RteFlg>0</RteFlg> + <bShared>0</bShared> + </File> + <File> + <GroupNumber>4</GroupNumber> + <FileNumber>17</FileNumber> + <FileType>1</FileType> + <tvExp>0</tvExp> + <tvExpOptDlg>0</tvExpOptDlg> + <bDave2>0</bDave2> + <PathWithFileName>drivers\drv_uart.c</PathWithFileName> + <FilenameWithoutPath>drv_uart.c</FilenameWithoutPath> + <RteFlg>0</RteFlg> + <bShared>0</bShared> + </File> + <File> + <GroupNumber>4</GroupNumber> + <FileNumber>18</FileNumber> + <FileType>1</FileType> + <tvExp>0</tvExp> + <tvExpOptDlg>0</tvExpOptDlg> + <bDave2>0</bDave2> + <PathWithFileName>drivers\board.c</PathWithFileName> + <FilenameWithoutPath>board.c</FilenameWithoutPath> + <RteFlg>0</RteFlg> + <bShared>0</bShared> + </File> + </Group> + + <Group> + <GroupName>Finsh</GroupName> + <tvExp>0</tvExp> + <tvExpOptDlg>0</tvExpOptDlg> + <cbSel>0</cbSel> + <RteFlg>0</RteFlg> + <File> + <GroupNumber>5</GroupNumber> + <FileNumber>19</FileNumber> + <FileType>1</FileType> + <tvExp>0</tvExp> + <tvExpOptDlg>0</tvExpOptDlg> + <bDave2>0</bDave2> + <PathWithFileName>..\..\components\finsh\shell.c</PathWithFileName> + <FilenameWithoutPath>shell.c</FilenameWithoutPath> + <RteFlg>0</RteFlg> + <bShared>0</bShared> + </File> + <File> + <GroupNumber>5</GroupNumber> + <FileNumber>20</FileNumber> + <FileType>1</FileType> + <tvExp>0</tvExp> + <tvExpOptDlg>0</tvExpOptDlg> + <bDave2>0</bDave2> + <PathWithFileName>..\..\components\finsh\msh.c</PathWithFileName> + <FilenameWithoutPath>msh.c</FilenameWithoutPath> + <RteFlg>0</RteFlg> + <bShared>0</bShared> + </File> + <File> + <GroupNumber>5</GroupNumber> + <FileNumber>21</FileNumber> + <FileType>1</FileType> + <tvExp>0</tvExp> + <tvExpOptDlg>0</tvExpOptDlg> + <bDave2>0</bDave2> + <PathWithFileName>..\..\components\finsh\cmd.c</PathWithFileName> + <FilenameWithoutPath>cmd.c</FilenameWithoutPath> + <RteFlg>0</RteFlg> + <bShared>0</bShared> + </File> + </Group> + + <Group> + <GroupName>Kernel</GroupName> + <tvExp>0</tvExp> + <tvExpOptDlg>0</tvExpOptDlg> + <cbSel>0</cbSel> + <RteFlg>0</RteFlg> + <File> + <GroupNumber>6</GroupNumber> + <FileNumber>22</FileNumber> + <FileType>1</FileType> + <tvExp>0</tvExp> + <tvExpOptDlg>0</tvExpOptDlg> + <bDave2>0</bDave2> + <PathWithFileName>..\..\src\mempool.c</PathWithFileName> + <FilenameWithoutPath>mempool.c</FilenameWithoutPath> + <RteFlg>0</RteFlg> + <bShared>0</bShared> + </File> + <File> + <GroupNumber>6</GroupNumber> + <FileNumber>23</FileNumber> + <FileType>1</FileType> + <tvExp>0</tvExp> + <tvExpOptDlg>0</tvExpOptDlg> + <bDave2>0</bDave2> + <PathWithFileName>..\..\src\clock.c</PathWithFileName> + <FilenameWithoutPath>clock.c</FilenameWithoutPath> + <RteFlg>0</RteFlg> + <bShared>0</bShared> + </File> + <File> + <GroupNumber>6</GroupNumber> + <FileNumber>24</FileNumber> + <FileType>1</FileType> + <tvExp>0</tvExp> + <tvExpOptDlg>0</tvExpOptDlg> + <bDave2>0</bDave2> + <PathWithFileName>..\..\src\timer.c</PathWithFileName> + <FilenameWithoutPath>timer.c</FilenameWithoutPath> + <RteFlg>0</RteFlg> + <bShared>0</bShared> + </File> + <File> + <GroupNumber>6</GroupNumber> + <FileNumber>25</FileNumber> + <FileType>1</FileType> + <tvExp>0</tvExp> + <tvExpOptDlg>0</tvExpOptDlg> + <bDave2>0</bDave2> + <PathWithFileName>..\..\src\device.c</PathWithFileName> + <FilenameWithoutPath>device.c</FilenameWithoutPath> + <RteFlg>0</RteFlg> + <bShared>0</bShared> + </File> + <File> + <GroupNumber>6</GroupNumber> + <FileNumber>26</FileNumber> + <FileType>1</FileType> + <tvExp>0</tvExp> + <tvExpOptDlg>0</tvExpOptDlg> + <bDave2>0</bDave2> + <PathWithFileName>..\..\src\object.c</PathWithFileName> + <FilenameWithoutPath>object.c</FilenameWithoutPath> + <RteFlg>0</RteFlg> + <bShared>0</bShared> + </File> + <File> + <GroupNumber>6</GroupNumber> + <FileNumber>27</FileNumber> + <FileType>1</FileType> + <tvExp>0</tvExp> + <tvExpOptDlg>0</tvExpOptDlg> + <bDave2>0</bDave2> + <PathWithFileName>..\..\src\kservice.c</PathWithFileName> + <FilenameWithoutPath>kservice.c</FilenameWithoutPath> + <RteFlg>0</RteFlg> + <bShared>0</bShared> + </File> + <File> + <GroupNumber>6</GroupNumber> + <FileNumber>28</FileNumber> + <FileType>1</FileType> + <tvExp>0</tvExp> + <tvExpOptDlg>0</tvExpOptDlg> + <bDave2>0</bDave2> + <PathWithFileName>..\..\src\thread.c</PathWithFileName> + <FilenameWithoutPath>thread.c</FilenameWithoutPath> + <RteFlg>0</RteFlg> + <bShared>0</bShared> + </File> + <File> + <GroupNumber>6</GroupNumber> + <FileNumber>29</FileNumber> + <FileType>1</FileType> + <tvExp>0</tvExp> + <tvExpOptDlg>0</tvExpOptDlg> + <bDave2>0</bDave2> + <PathWithFileName>..\..\src\memheap.c</PathWithFileName> + <FilenameWithoutPath>memheap.c</FilenameWithoutPath> + <RteFlg>0</RteFlg> + <bShared>0</bShared> + </File> + <File> + <GroupNumber>6</GroupNumber> + <FileNumber>30</FileNumber> + <FileType>1</FileType> + <tvExp>0</tvExp> + <tvExpOptDlg>0</tvExpOptDlg> + <bDave2>0</bDave2> + <PathWithFileName>..\..\src\idle.c</PathWithFileName> + <FilenameWithoutPath>idle.c</FilenameWithoutPath> + <RteFlg>0</RteFlg> + <bShared>0</bShared> + </File> + <File> + <GroupNumber>6</GroupNumber> + <FileNumber>31</FileNumber> + <FileType>1</FileType> + <tvExp>0</tvExp> + <tvExpOptDlg>0</tvExpOptDlg> + <bDave2>0</bDave2> + <PathWithFileName>..\..\src\ipc.c</PathWithFileName> + <FilenameWithoutPath>ipc.c</FilenameWithoutPath> + <RteFlg>0</RteFlg> + <bShared>0</bShared> + </File> + <File> + <GroupNumber>6</GroupNumber> + <FileNumber>32</FileNumber> + <FileType>1</FileType> + <tvExp>0</tvExp> + <tvExpOptDlg>0</tvExpOptDlg> + <bDave2>0</bDave2> + <PathWithFileName>..\..\src\irq.c</PathWithFileName> + <FilenameWithoutPath>irq.c</FilenameWithoutPath> + <RteFlg>0</RteFlg> + <bShared>0</bShared> + </File> + <File> + <GroupNumber>6</GroupNumber> + <FileNumber>33</FileNumber> + <FileType>1</FileType> + <tvExp>0</tvExp> + <tvExpOptDlg>0</tvExpOptDlg> + <bDave2>0</bDave2> + <PathWithFileName>..\..\src\components.c</PathWithFileName> + <FilenameWithoutPath>components.c</FilenameWithoutPath> + <RteFlg>0</RteFlg> + <bShared>0</bShared> + </File> + <File> + <GroupNumber>6</GroupNumber> + <FileNumber>34</FileNumber> + <FileType>1</FileType> + <tvExp>0</tvExp> + <tvExpOptDlg>0</tvExpOptDlg> + <bDave2>0</bDave2> + <PathWithFileName>..\..\src\scheduler.c</PathWithFileName> + <FilenameWithoutPath>scheduler.c</FilenameWithoutPath> + <RteFlg>0</RteFlg> + <bShared>0</bShared> + </File> + </Group> + + <Group> + <GroupName>libc</GroupName> + <tvExp>0</tvExp> + <tvExpOptDlg>0</tvExpOptDlg> + <cbSel>0</cbSel> + <RteFlg>0</RteFlg> + <File> + <GroupNumber>7</GroupNumber> + <FileNumber>35</FileNumber> + <FileType>1</FileType> + <tvExp>0</tvExp> + <tvExpOptDlg>0</tvExpOptDlg> + <bDave2>0</bDave2> + <PathWithFileName>..\..\components\libc\compilers\armlibc\libc.c</PathWithFileName> + <FilenameWithoutPath>libc.c</FilenameWithoutPath> + <RteFlg>0</RteFlg> + <bShared>0</bShared> + </File> + <File> + <GroupNumber>7</GroupNumber> + <FileNumber>36</FileNumber> + <FileType>1</FileType> + <tvExp>0</tvExp> + <tvExpOptDlg>0</tvExpOptDlg> + <bDave2>0</bDave2> + <PathWithFileName>..\..\components\libc\compilers\armlibc\mem_std.c</PathWithFileName> + <FilenameWithoutPath>mem_std.c</FilenameWithoutPath> + <RteFlg>0</RteFlg> + <bShared>0</bShared> + </File> + <File> + <GroupNumber>7</GroupNumber> + <FileNumber>37</FileNumber> + <FileType>1</FileType> + <tvExp>0</tvExp> + <tvExpOptDlg>0</tvExpOptDlg> + <bDave2>0</bDave2> + <PathWithFileName>..\..\components\libc\compilers\armlibc\syscalls.c</PathWithFileName> + <FilenameWithoutPath>syscalls.c</FilenameWithoutPath> + <RteFlg>0</RteFlg> + <bShared>0</bShared> + </File> + <File> + <GroupNumber>7</GroupNumber> + <FileNumber>38</FileNumber> + <FileType>1</FileType> + <tvExp>0</tvExp> + <tvExpOptDlg>0</tvExpOptDlg> + <bDave2>0</bDave2> + <PathWithFileName>..\..\components\libc\compilers\common\time.c</PathWithFileName> + <FilenameWithoutPath>time.c</FilenameWithoutPath> + <RteFlg>0</RteFlg> + <bShared>0</bShared> + </File> + <File> + <GroupNumber>7</GroupNumber> + <FileNumber>39</FileNumber> + <FileType>1</FileType> + <tvExp>0</tvExp> + <tvExpOptDlg>0</tvExpOptDlg> + <bDave2>0</bDave2> + <PathWithFileName>..\..\components\libc\compilers\common\stdlib.c</PathWithFileName> + <FilenameWithoutPath>stdlib.c</FilenameWithoutPath> + <RteFlg>0</RteFlg> + <bShared>0</bShared> + </File> + </Group> + + <Group> + <GroupName>Libraries</GroupName> + <tvExp>0</tvExp> + <tvExpOptDlg>0</tvExpOptDlg> + <cbSel>0</cbSel> + <RteFlg>0</RteFlg> + <File> + <GroupNumber>8</GroupNumber> + <FileNumber>40</FileNumber> + <FileType>1</FileType> + <tvExp>0</tvExp> + <tvExpOptDlg>0</tvExpOptDlg> + <bDave2>0</bDave2> + <PathWithFileName>libraries\SWM320_StdPeriph_Driver\SWM320_adc.c</PathWithFileName> + <FilenameWithoutPath>SWM320_adc.c</FilenameWithoutPath> + <RteFlg>0</RteFlg> + <bShared>0</bShared> + </File> + <File> + <GroupNumber>8</GroupNumber> + <FileNumber>41</FileNumber> + <FileType>1</FileType> + <tvExp>0</tvExp> + <tvExpOptDlg>0</tvExpOptDlg> + <bDave2>0</bDave2> + <PathWithFileName>libraries\SWM320_StdPeriph_Driver\SWM320_port.c</PathWithFileName> + <FilenameWithoutPath>SWM320_port.c</FilenameWithoutPath> + <RteFlg>0</RteFlg> + <bShared>0</bShared> + </File> + <File> + <GroupNumber>8</GroupNumber> + <FileNumber>42</FileNumber> + <FileType>1</FileType> + <tvExp>0</tvExp> + <tvExpOptDlg>0</tvExpOptDlg> + <bDave2>0</bDave2> + <PathWithFileName>libraries\SWM320_StdPeriph_Driver\SWM320_crc.c</PathWithFileName> + <FilenameWithoutPath>SWM320_crc.c</FilenameWithoutPath> + <RteFlg>0</RteFlg> + <bShared>0</bShared> + </File> + <File> + <GroupNumber>8</GroupNumber> + <FileNumber>43</FileNumber> + <FileType>1</FileType> + <tvExp>0</tvExp> + <tvExpOptDlg>0</tvExpOptDlg> + <bDave2>0</bDave2> + <PathWithFileName>libraries\SWM320_StdPeriph_Driver\SWM320_spi.c</PathWithFileName> + <FilenameWithoutPath>SWM320_spi.c</FilenameWithoutPath> + <RteFlg>0</RteFlg> + <bShared>0</bShared> + </File> + <File> + <GroupNumber>8</GroupNumber> + <FileNumber>44</FileNumber> + <FileType>1</FileType> + <tvExp>0</tvExp> + <tvExpOptDlg>0</tvExpOptDlg> + <bDave2>0</bDave2> + <PathWithFileName>libraries\SWM320_StdPeriph_Driver\SWM320_uart.c</PathWithFileName> + <FilenameWithoutPath>SWM320_uart.c</FilenameWithoutPath> + <RteFlg>0</RteFlg> + <bShared>0</bShared> + </File> + <File> + <GroupNumber>8</GroupNumber> + <FileNumber>45</FileNumber> + <FileType>1</FileType> + <tvExp>0</tvExp> + <tvExpOptDlg>0</tvExpOptDlg> + <bDave2>0</bDave2> + <PathWithFileName>libraries\CMSIS\DeviceSupport\system_SWM320.c</PathWithFileName> + <FilenameWithoutPath>system_SWM320.c</FilenameWithoutPath> + <RteFlg>0</RteFlg> + <bShared>0</bShared> + </File> + <File> + <GroupNumber>8</GroupNumber> + <FileNumber>46</FileNumber> + <FileType>1</FileType> + <tvExp>0</tvExp> + <tvExpOptDlg>0</tvExpOptDlg> + <bDave2>0</bDave2> + <PathWithFileName>libraries\SWM320_StdPeriph_Driver\SWM320_flash.c</PathWithFileName> + <FilenameWithoutPath>SWM320_flash.c</FilenameWithoutPath> + <RteFlg>0</RteFlg> + <bShared>0</bShared> + </File> + <File> + <GroupNumber>8</GroupNumber> + <FileNumber>47</FileNumber> + <FileType>1</FileType> + <tvExp>0</tvExp> + <tvExpOptDlg>0</tvExpOptDlg> + <bDave2>0</bDave2> + <PathWithFileName>libraries\SWM320_StdPeriph_Driver\SWM320_can.c</PathWithFileName> + <FilenameWithoutPath>SWM320_can.c</FilenameWithoutPath> + <RteFlg>0</RteFlg> + <bShared>0</bShared> + </File> + <File> + <GroupNumber>8</GroupNumber> + <FileNumber>48</FileNumber> + <FileType>1</FileType> + <tvExp>0</tvExp> + <tvExpOptDlg>0</tvExpOptDlg> + <bDave2>0</bDave2> + <PathWithFileName>libraries\SWM320_StdPeriph_Driver\SWM320_sram.c</PathWithFileName> + <FilenameWithoutPath>SWM320_sram.c</FilenameWithoutPath> + <RteFlg>0</RteFlg> + <bShared>0</bShared> + </File> + <File> + <GroupNumber>8</GroupNumber> + <FileNumber>49</FileNumber> + <FileType>1</FileType> + <tvExp>0</tvExp> + <tvExpOptDlg>0</tvExpOptDlg> + <bDave2>0</bDave2> + <PathWithFileName>libraries\SWM320_StdPeriph_Driver\SWM320_exti.c</PathWithFileName> + <FilenameWithoutPath>SWM320_exti.c</FilenameWithoutPath> + <RteFlg>0</RteFlg> + <bShared>0</bShared> + </File> + <File> + <GroupNumber>8</GroupNumber> + <FileNumber>50</FileNumber> + <FileType>1</FileType> + <tvExp>0</tvExp> + <tvExpOptDlg>0</tvExpOptDlg> + <bDave2>0</bDave2> + <PathWithFileName>libraries\SWM320_StdPeriph_Driver\SWM320_sdram.c</PathWithFileName> + <FilenameWithoutPath>SWM320_sdram.c</FilenameWithoutPath> + <RteFlg>0</RteFlg> + <bShared>0</bShared> + </File> + <File> + <GroupNumber>8</GroupNumber> + <FileNumber>51</FileNumber> + <FileType>1</FileType> + <tvExp>0</tvExp> + <tvExpOptDlg>0</tvExpOptDlg> + <bDave2>0</bDave2> + <PathWithFileName>libraries\SWM320_StdPeriph_Driver\SWM320_i2c.c</PathWithFileName> + <FilenameWithoutPath>SWM320_i2c.c</FilenameWithoutPath> + <RteFlg>0</RteFlg> + <bShared>0</bShared> + </File> + <File> + <GroupNumber>8</GroupNumber> + <FileNumber>52</FileNumber> + <FileType>2</FileType> + <tvExp>0</tvExp> + <tvExpOptDlg>0</tvExpOptDlg> + <bDave2>0</bDave2> + <PathWithFileName>libraries\CMSIS\DeviceSupport\startup\arm\startup_SWM320.s</PathWithFileName> + <FilenameWithoutPath>startup_SWM320.s</FilenameWithoutPath> + <RteFlg>0</RteFlg> + <bShared>0</bShared> + </File> + <File> + <GroupNumber>8</GroupNumber> + <FileNumber>53</FileNumber> + <FileType>1</FileType> + <tvExp>0</tvExp> + <tvExpOptDlg>0</tvExpOptDlg> + <bDave2>0</bDave2> + <PathWithFileName>libraries\SWM320_StdPeriph_Driver\SWM320_dma.c</PathWithFileName> + <FilenameWithoutPath>SWM320_dma.c</FilenameWithoutPath> + <RteFlg>0</RteFlg> + <bShared>0</bShared> + </File> + <File> + <GroupNumber>8</GroupNumber> + <FileNumber>54</FileNumber> + <FileType>1</FileType> + <tvExp>0</tvExp> + <tvExpOptDlg>0</tvExpOptDlg> + <bDave2>0</bDave2> + <PathWithFileName>libraries\SWM320_StdPeriph_Driver\SWM320_rtc.c</PathWithFileName> + <FilenameWithoutPath>SWM320_rtc.c</FilenameWithoutPath> + <RteFlg>0</RteFlg> + <bShared>0</bShared> + </File> + <File> + <GroupNumber>8</GroupNumber> + <FileNumber>55</FileNumber> + <FileType>1</FileType> + <tvExp>0</tvExp> + <tvExpOptDlg>0</tvExpOptDlg> + <bDave2>0</bDave2> + <PathWithFileName>libraries\SWM320_StdPeriph_Driver\SWM320_sdio.c</PathWithFileName> + <FilenameWithoutPath>SWM320_sdio.c</FilenameWithoutPath> + <RteFlg>0</RteFlg> + <bShared>0</bShared> + </File> + <File> + <GroupNumber>8</GroupNumber> + <FileNumber>56</FileNumber> + <FileType>1</FileType> + <tvExp>0</tvExp> + <tvExpOptDlg>0</tvExpOptDlg> + <bDave2>0</bDave2> + <PathWithFileName>libraries\SWM320_StdPeriph_Driver\SWM320_norflash.c</PathWithFileName> + <FilenameWithoutPath>SWM320_norflash.c</FilenameWithoutPath> + <RteFlg>0</RteFlg> + <bShared>0</bShared> + </File> + <File> + <GroupNumber>8</GroupNumber> + <FileNumber>57</FileNumber> + <FileType>1</FileType> + <tvExp>0</tvExp> + <tvExpOptDlg>0</tvExpOptDlg> + <bDave2>0</bDave2> + <PathWithFileName>libraries\SWM320_StdPeriph_Driver\SWM320_pwm.c</PathWithFileName> + <FilenameWithoutPath>SWM320_pwm.c</FilenameWithoutPath> + <RteFlg>0</RteFlg> + <bShared>0</bShared> + </File> + <File> + <GroupNumber>8</GroupNumber> + <FileNumber>58</FileNumber> + <FileType>1</FileType> + <tvExp>0</tvExp> + <tvExpOptDlg>0</tvExpOptDlg> + <bDave2>0</bDave2> + <PathWithFileName>libraries\SWM320_StdPeriph_Driver\SWM320_timr.c</PathWithFileName> + <FilenameWithoutPath>SWM320_timr.c</FilenameWithoutPath> + <RteFlg>0</RteFlg> + <bShared>0</bShared> + </File> + <File> + <GroupNumber>8</GroupNumber> + <FileNumber>59</FileNumber> + <FileType>1</FileType> + <tvExp>0</tvExp> + <tvExpOptDlg>0</tvExpOptDlg> + <bDave2>0</bDave2> + <PathWithFileName>libraries\SWM320_StdPeriph_Driver\SWM320_wdt.c</PathWithFileName> + <FilenameWithoutPath>SWM320_wdt.c</FilenameWithoutPath> + <RteFlg>0</RteFlg> + <bShared>0</bShared> + </File> + <File> + <GroupNumber>8</GroupNumber> + <FileNumber>60</FileNumber> + <FileType>1</FileType> + <tvExp>0</tvExp> + <tvExpOptDlg>0</tvExpOptDlg> + <bDave2>0</bDave2> + <PathWithFileName>libraries\SWM320_StdPeriph_Driver\SWM320_gpio.c</PathWithFileName> + <FilenameWithoutPath>SWM320_gpio.c</FilenameWithoutPath> + <RteFlg>0</RteFlg> + <bShared>0</bShared> + </File> + <File> + <GroupNumber>8</GroupNumber> + <FileNumber>61</FileNumber> + <FileType>1</FileType> + <tvExp>0</tvExp> + <tvExpOptDlg>0</tvExpOptDlg> + <bDave2>0</bDave2> + <PathWithFileName>libraries\SWM320_StdPeriph_Driver\SWM320_lcd.c</PathWithFileName> + <FilenameWithoutPath>SWM320_lcd.c</FilenameWithoutPath> + <RteFlg>0</RteFlg> + <bShared>0</bShared> + </File> + </Group> + </ProjectOpt> diff --git a/bsp/swm320-lq100/project.uvproj b/bsp/swm320-lq100/project.uvproj new file mode 100644 index 0000000000..66eddd2602 --- /dev/null +++ b/bsp/swm320-lq100/project.uvproj @@ -0,0 +1,786 @@ +<?xml version="1.0" encoding="UTF-8" standalone="no" ?> +<Project xmlns:xsi="http://www.w3.org/2001/XMLSchema-instance" xsi:noNamespaceSchemaLocation="project_proj.xsd"> + <SchemaVersion>1.1</SchemaVersion> + <Header>### uVision Project, (C) Keil Software</Header> + <Targets> + <Target> + <TargetName>rtthread</TargetName> + <ToolsetNumber>0x4</ToolsetNumber> + <ToolsetName>ARM-ADS</ToolsetName> + <TargetOption> + <TargetCommonOption> + <Device>STM32F407ZG</Device> + <Vendor>STMicroelectronics</Vendor> + <Cpu>IRAM(0x20000000-0x2001FFFF) IRAM2(0x10000000-0x1000FFFF) IROM(0x8000000-0x80FFFFF) CLOCK(25000000) CPUTYPE("Cortex-M4") FPU2</Cpu> + <FlashUtilSpec /> + <StartupFile>"Startup\ST\STM32F4xx\startup_stm32f40_41xxx.s" ("STM32F40/41xxx Startup Code")</StartupFile> + <FlashDriverDll>UL2CM3(-O207 -S0 -C0 -FO7 -FD20000000 -FC800 -FN1 -FF0STM32F4xx_1024 -FS08000000 -FL0100000)</FlashDriverDll> + <DeviceId>6105</DeviceId> + <RegisterFile>stm32f4xx.h</RegisterFile> + <MemoryEnv /> + <Cmp /> + <Asm /> + <Linker /> + <OHString /> + <InfinionOptionDll /> + <SLE66CMisc>-DSTM32F40_41xxx</SLE66CMisc> + <SLE66AMisc /> + <SLE66LinkerMisc /> + <SFDFile>SFD\ST\STM32F4xx\STM32F40x.sfr</SFDFile> + <bCustSvd>0</bCustSvd> + <UseEnv>0</UseEnv> + <BinPath /> + <IncludePath /> + <LibPath /> + <RegisterFilePath>ST\STM32F4xx\</RegisterFilePath> + <DBRegisterFilePath>ST\STM32F4xx\</DBRegisterFilePath> + <TargetStatus> + <Error>0</Error> + <ExitCodeStop>0</ExitCodeStop> + <ButtonStop>0</ButtonStop> + <NotGenerated>0</NotGenerated> + <InvalidFlash>1</InvalidFlash> + </TargetStatus> + <OutputDirectory>.\build\keil\Obj\</OutputDirectory> + <OutputName>rt-thread</OutputName> + <CreateExecutable>1</CreateExecutable> + <CreateLib>0</CreateLib> + <CreateHexFile>0</CreateHexFile> + <DebugInformation>1</DebugInformation> + <BrowseInformation>0</BrowseInformation> + <ListingPath>.\build\keil\List\</ListingPath> + <HexFormatSelection>1</HexFormatSelection> + <Merge32K>0</Merge32K> + <CreateBatchFile>0</CreateBatchFile> + <BeforeCompile> + <RunUserProg1>0</RunUserProg1> + <RunUserProg2>0</RunUserProg2> + <UserProg1Name /> + <UserProg2Name /> + <UserProg1Dos16Mode>0</UserProg1Dos16Mode> + <UserProg2Dos16Mode>0</UserProg2Dos16Mode> + <nStopU1X>0</nStopU1X> + <nStopU2X>0</nStopU2X> + </BeforeCompile> + <BeforeMake> + <RunUserProg1>0</RunUserProg1> + <RunUserProg2>0</RunUserProg2> + <UserProg1Name /> + <UserProg2Name /> + <UserProg1Dos16Mode>0</UserProg1Dos16Mode> + <UserProg2Dos16Mode>0</UserProg2Dos16Mode> + </BeforeMake> + <AfterMake> + <RunUserProg1>1</RunUserProg1> + <RunUserProg2>0</RunUserProg2> + <UserProg1Name>fromelf --bin !L --output rtthread.bin</UserProg1Name> + <UserProg2Name /> + <UserProg1Dos16Mode>0</UserProg1Dos16Mode> + <UserProg2Dos16Mode>0</UserProg2Dos16Mode> + </AfterMake> + <SelectedForBatchBuild>0</SelectedForBatchBuild> + <SVCSIdString /> + </TargetCommonOption> + <CommonProperty> + <UseCPPCompiler>0</UseCPPCompiler> + <RVCTCodeConst>0</RVCTCodeConst> + <RVCTZI>0</RVCTZI> + <RVCTOtherData>0</RVCTOtherData> + <ModuleSelection>0</ModuleSelection> + <IncludeInBuild>1</IncludeInBuild> + <AlwaysBuild>0</AlwaysBuild> + <GenerateAssemblyFile>0</GenerateAssemblyFile> + <AssembleAssemblyFile>0</AssembleAssemblyFile> + <PublicsOnly>0</PublicsOnly> + <StopOnExitCode>3</StopOnExitCode> + <CustomArgument /> + <IncludeLibraryModules /> + <ComprImg>1</ComprImg> + </CommonProperty> + <DllOption> + <SimDllName>SARMCM3.DLL</SimDllName> + <SimDllArguments>-MPU -REMAP</SimDllArguments> + <SimDlgDll>DCM.DLL</SimDlgDll> + <SimDlgDllArguments>-pCM4</SimDlgDllArguments> + <TargetDllName>SARMCM3.DLL</TargetDllName> + <TargetDllArguments>-MPU</TargetDllArguments> + <TargetDlgDll>TCM.DLL</TargetDlgDll> + <TargetDlgDllArguments>-pCM4</TargetDlgDllArguments> + </DllOption> + <DebugOption> + <OPTHX> + <HexSelection>1</HexSelection> + <HexRangeLowAddress>0</HexRangeLowAddress> + <HexRangeHighAddress>0</HexRangeHighAddress> + <HexOffset>0</HexOffset> + <Oh166RecLen>16</Oh166RecLen> + </OPTHX> + <Simulator> + <UseSimulator>0</UseSimulator> + <LoadApplicationAtStartup>1</LoadApplicationAtStartup> + <RunToMain>1</RunToMain> + <RestoreBreakpoints>1</RestoreBreakpoints> + <RestoreWatchpoints>1</RestoreWatchpoints> + <RestoreMemoryDisplay>1</RestoreMemoryDisplay> + <RestoreFunctions>1</RestoreFunctions> + <RestoreToolbox>1</RestoreToolbox> + <LimitSpeedToRealTime>0</LimitSpeedToRealTime> + <RestoreSysVw>1</RestoreSysVw> + </Simulator> + <Target> + <UseTarget>1</UseTarget> + <LoadApplicationAtStartup>1</LoadApplicationAtStartup> + <RunToMain>1</RunToMain> + <RestoreBreakpoints>1</RestoreBreakpoints> + <RestoreWatchpoints>1</RestoreWatchpoints> + <RestoreMemoryDisplay>1</RestoreMemoryDisplay> + <RestoreFunctions>0</RestoreFunctions> + <RestoreToolbox>1</RestoreToolbox> + <RestoreTracepoints>0</RestoreTracepoints> + <RestoreSysVw>1</RestoreSysVw> + <UsePdscDebugDescription>0</UsePdscDebugDescription> + </Target> + <RunDebugAfterBuild>0</RunDebugAfterBuild> + <TargetSelection>6</TargetSelection> + <SimDlls> + <CpuDll /> + <CpuDllArguments /> + <PeripheralDll /> + <PeripheralDllArguments /> + <InitializationFile /> + </SimDlls> + <TargetDlls> + <CpuDll /> + <CpuDllArguments /> + <PeripheralDll /> + <PeripheralDllArguments /> + <InitializationFile /> + <Driver>Segger\JL2CM3.dll</Driver> + </TargetDlls> + </DebugOption> + <Utilities> + <Flash1> + <UseTargetDll>1</UseTargetDll> + <UseExternalTool>0</UseExternalTool> + <RunIndependent>0</RunIndependent> + <UpdateFlashBeforeDebugging>1</UpdateFlashBeforeDebugging> + <Capability>1</Capability> + <DriverSelection>4096</DriverSelection> + </Flash1> + <bUseTDR>1</bUseTDR> + <Flash2>BIN\UL2CM3.DLL</Flash2> + <Flash3>"" ()</Flash3> + <Flash4 /> + <pFcarmOut /> + <pFcarmGrp /> + <pFcArmRoot /> + <FcArmLst>0</FcArmLst> + </Utilities> + <TargetArmAds> + <ArmAdsMisc> + <GenerateListings>0</GenerateListings> + <asHll>1</asHll> + <asAsm>1</asAsm> + <asMacX>1</asMacX> + <asSyms>1</asSyms> + <asFals>1</asFals> + <asDbgD>1</asDbgD> + <asForm>1</asForm> + <ldLst>0</ldLst> + <ldmm>1</ldmm> + <ldXref>1</ldXref> + <BigEnd>0</BigEnd> + <AdsALst>1</AdsALst> + <AdsACrf>1</AdsACrf> + <AdsANop>0</AdsANop> + <AdsANot>0</AdsANot> + <AdsLLst>1</AdsLLst> + <AdsLmap>1</AdsLmap> + <AdsLcgr>1</AdsLcgr> + <AdsLsym>1</AdsLsym> + <AdsLszi>1</AdsLszi> + <AdsLtoi>1</AdsLtoi> + <AdsLsun>1</AdsLsun> + <AdsLven>1</AdsLven> + <AdsLsxf>1</AdsLsxf> + <RvctClst>0</RvctClst> + <GenPPlst>0</GenPPlst> + <AdsCpuType>"Cortex-M4"</AdsCpuType> + <RvctDeviceName /> + <mOS>0</mOS> + <uocRom>0</uocRom> + <uocRam>0</uocRam> + <hadIROM>1</hadIROM> + <hadIRAM>1</hadIRAM> + <hadXRAM>0</hadXRAM> + <uocXRam>0</uocXRam> + <RvdsVP>2</RvdsVP> + <hadIRAM2>1</hadIRAM2> + <hadIROM2>0</hadIROM2> + <StupSel>8</StupSel> + <useUlib>0</useUlib> + <EndSel>0</EndSel> + <uLtcg>0</uLtcg> + <RoSelD>3</RoSelD> + <RwSelD>3</RwSelD> + <CodeSel>0</CodeSel> + <OptFeed>0</OptFeed> + <NoZi1>0</NoZi1> + <NoZi2>0</NoZi2> + <NoZi3>0</NoZi3> + <NoZi4>0</NoZi4> + <NoZi5>0</NoZi5> + <Ro1Chk>0</Ro1Chk> + <Ro2Chk>0</Ro2Chk> + <Ro3Chk>0</Ro3Chk> + <Ir1Chk>1</Ir1Chk> + <Ir2Chk>0</Ir2Chk> + <Ra1Chk>0</Ra1Chk> + <Ra2Chk>0</Ra2Chk> + <Ra3Chk>0</Ra3Chk> + <Im1Chk>0</Im1Chk> + <Im2Chk>1</Im2Chk> + <OnChipMemories> + <Ocm1> + <Type>0</Type> + <StartAddress>0x0</StartAddress> + <Size>0x0</Size> + </Ocm1> + <Ocm2> + <Type>0</Type> + <StartAddress>0x0</StartAddress> + <Size>0x0</Size> + </Ocm2> + <Ocm3> + <Type>0</Type> + <StartAddress>0x0</StartAddress> + <Size>0x0</Size> + </Ocm3> + <Ocm4> + <Type>0</Type> + <StartAddress>0x0</StartAddress> + <Size>0x0</Size> + </Ocm4> + <Ocm5> + <Type>0</Type> + <StartAddress>0x0</StartAddress> + <Size>0x0</Size> + </Ocm5> + <Ocm6> + <Type>0</Type> + <StartAddress>0x0</StartAddress> + <Size>0x0</Size> + </Ocm6> + <IRAM> + <Type>0</Type> + <StartAddress>0x20000000</StartAddress> + <Size>0x20000</Size> + </IRAM> + <IROM> + <Type>1</Type> + <StartAddress>0x8000000</StartAddress> + <Size>0x100000</Size> + </IROM> + <XRAM> + <Type>0</Type> + <StartAddress>0x0</StartAddress> + <Size>0x0</Size> + </XRAM> + <OCR_RVCT1> + <Type>1</Type> + <StartAddress>0x0</StartAddress> + <Size>0x0</Size> + </OCR_RVCT1> + <OCR_RVCT2> + <Type>1</Type> + <StartAddress>0x0</StartAddress> + <Size>0x0</Size> + </OCR_RVCT2> + <OCR_RVCT3> + <Type>1</Type> + <StartAddress>0x0</StartAddress> + <Size>0x0</Size> + </OCR_RVCT3> + <OCR_RVCT4> + <Type>1</Type> + <StartAddress>0x8000000</StartAddress> + <Size>0x100000</Size> + </OCR_RVCT4> + <OCR_RVCT5> + <Type>1</Type> + <StartAddress>0x0</StartAddress> + <Size>0x0</Size> + </OCR_RVCT5> + <OCR_RVCT6> + <Type>0</Type> + <StartAddress>0x0</StartAddress> + <Size>0x0</Size> + </OCR_RVCT6> + <OCR_RVCT7> + <Type>0</Type> + <StartAddress>0x0</StartAddress> + <Size>0x0</Size> + </OCR_RVCT7> + <OCR_RVCT8> + <Type>0</Type> + <StartAddress>0x0</StartAddress> + <Size>0x0</Size> + </OCR_RVCT8> + <OCR_RVCT9> + <Type>0</Type> + <StartAddress>0x20000000</StartAddress> + <Size>0x20000</Size> + </OCR_RVCT9> + <OCR_RVCT10> + <Type>0</Type> + <StartAddress>0x10000000</StartAddress> + <Size>0x10000</Size> + </OCR_RVCT10> + </OnChipMemories> + <RvctStartVector /> + </ArmAdsMisc> + <Cads> + <interw>1</interw> + <Optim>1</Optim> + <oTime>0</oTime> + <SplitLS>0</SplitLS> + <OneElfS>1</OneElfS> + <Strict>0</Strict> + <EnumInt>0</EnumInt> + <PlainCh>0</PlainCh> + <Ropi>0</Ropi> + <Rwpi>0</Rwpi> + <wLevel>0</wLevel> + <uThumb>0</uThumb> + <uSurpInc>0</uSurpInc> + <uC99>1</uC99> + <useXO>0</useXO> + <VariousControls> + <MiscControls /> + <Define /> + <Undefine /> + <IncludePath>.;..\..\include;applications;drivers;libcpu;Libraries\CMSIS\CoreSupport;Libraries\CMSIS\DeviceSupport;Libraries\XXX_StdPeriph_Driver;..\..\libcpu\arm\common;..\..\libcpu\arm\cortex-m4;..\..\components\drivers\include;..\..\components\drivers\include;..\..\components\drivers\include;..\..\components\finsh</IncludePath> + </VariousControls> + </Cads> + <Aads> + <interw>1</interw> + <Ropi>0</Ropi> + <Rwpi>0</Rwpi> + <thumb>0</thumb> + <SplitLS>0</SplitLS> + <SwStkChk>0</SwStkChk> + <NoWarn>0</NoWarn> + <uSurpInc>0</uSurpInc> + <useXO>0</useXO> + <VariousControls> + <MiscControls /> + <Define /> + <Undefine /> + <IncludePath /> + </VariousControls> + </Aads> + <LDads> + <umfTarg>0</umfTarg> + <Ropi>0</Ropi> + <Rwpi>0</Rwpi> + <noStLib>0</noStLib> + <RepFail>1</RepFail> + <useFile>0</useFile> + <TextAddressRange>0x08000000</TextAddressRange> + <DataAddressRange>0x20000000</DataAddressRange> + <pXoBase /> + <ScatterFile>.\drivers\linker_scripts\link.sct</ScatterFile> + <IncludeLibs /> + <IncludeLibsPath /> + <Misc /> + <LinkerInputFile /> + <DisabledWarnings /> + </LDads> + </TargetArmAds> + </TargetOption> + <Groups> + <Group> + <GroupName>Kernel</GroupName> + <Files> + <File> + <FileName>clock.c</FileName> + <FileType>1</FileType> + <FilePath>..\..\src\clock.c</FilePath> + </File> + </Files> + <Files> + <File> + <FileName>components.c</FileName> + <FileType>1</FileType> + <FilePath>..\..\src\components.c</FilePath> + </File> + </Files> + <Files> + <File> + <FileName>cpu.c</FileName> + <FileType>1</FileType> + <FilePath>..\..\src\cpu.c</FilePath> + </File> + </Files> + <Files> + <File> + <FileName>device.c</FileName> + <FileType>1</FileType> + <FilePath>..\..\src\device.c</FilePath> + </File> + </Files> + <Files> + <File> + <FileName>idle.c</FileName> + <FileType>1</FileType> + <FilePath>..\..\src\idle.c</FilePath> + </File> + </Files> + <Files> + <File> + <FileName>ipc.c</FileName> + <FileType>1</FileType> + <FilePath>..\..\src\ipc.c</FilePath> + </File> + </Files> + <Files> + <File> + <FileName>irq.c</FileName> + <FileType>1</FileType> + <FilePath>..\..\src\irq.c</FilePath> + </File> + </Files> + <Files> + <File> + <FileName>kservice.c</FileName> + <FileType>1</FileType> + <FilePath>..\..\src\kservice.c</FilePath> + </File> + </Files> + <Files> + <File> + <FileName>mem.c</FileName> + <FileType>1</FileType> + <FilePath>..\..\src\mem.c</FilePath> + </File> + </Files> + <Files> + <File> + <FileName>mempool.c</FileName> + <FileType>1</FileType> + <FilePath>..\..\src\mempool.c</FilePath> + </File> + </Files> + <Files> + <File> + <FileName>object.c</FileName> + <FileType>1</FileType> + <FilePath>..\..\src\object.c</FilePath> + </File> + </Files> + <Files> + <File> + <FileName>scheduler.c</FileName> + <FileType>1</FileType> + <FilePath>..\..\src\scheduler.c</FilePath> + </File> + </Files> + <Files> + <File> + <FileName>signal.c</FileName> + <FileType>1</FileType> + <FilePath>..\..\src\signal.c</FilePath> + </File> + </Files> + <Files> + <File> + <FileName>thread.c</FileName> + <FileType>1</FileType> + <FilePath>..\..\src\thread.c</FilePath> + </File> + </Files> + <Files> + <File> + <FileName>timer.c</FileName> + <FileType>1</FileType> + <FilePath>..\..\src\timer.c</FilePath> + </File> + </Files> + </Group> + <Group> + <GroupName>Applications</GroupName> + <Files> + <File> + <FileName>main.c</FileName> + <FileType>1</FileType> + <FilePath>applications\main.c</FilePath> + </File> + </Files> + <Files> + <File> + <FileName>mnt.c</FileName> + <FileType>1</FileType> + <FilePath>applications\mnt.c</FilePath> + </File> + </Files> + </Group> + <Group> + <GroupName>Drivers</GroupName> + <Files> + <File> + <FileName>board.c</FileName> + <FileType>1</FileType> + <FilePath>drivers\board.c</FilePath> + </File> + </Files> + <Files> + <File> + <FileName>drv_uart.c</FileName> + <FileType>1</FileType> + <FilePath>drivers\drv_uart.c</FilePath> + </File> + </Files> + </Group> + <Group> + <GroupName>CPU</GroupName> + <Files> + <File> + <FileName>port.c</FileName> + <FileType>1</FileType> + <FilePath>libcpu\port.c</FilePath> + </File> + </Files> + </Group> + <Group> + <GroupName>Libraries</GroupName> + <Files> + <File> + <FileName>startup_xxx.s</FileName> + <FileType>2</FileType> + <FilePath>Libraries\CMSIS\startup_xxx.s</FilePath> + </File> + </Files> + </Group> + <Group> + <GroupName>cpu</GroupName> + <Files> + <File> + <FileName>backtrace.c</FileName> + <FileType>1</FileType> + <FilePath>..\..\libcpu\arm\common\backtrace.c</FilePath> + </File> + </Files> + <Files> + <File> + <FileName>div0.c</FileName> + <FileType>1</FileType> + <FilePath>..\..\libcpu\arm\common\div0.c</FilePath> + </File> + </Files> + <Files> + <File> + <FileName>showmem.c</FileName> + <FileType>1</FileType> + <FilePath>..\..\libcpu\arm\common\showmem.c</FilePath> + </File> + </Files> + <Files> + <File> + <FileName>cpuport.c</FileName> + <FileType>1</FileType> + <FilePath>..\..\libcpu\arm\cortex-m4\cpuport.c</FilePath> + </File> + </Files> + <Files> + <File> + <FileName>context_rvds.S</FileName> + <FileType>2</FileType> + <FilePath>..\..\libcpu\arm\cortex-m4\context_rvds.S</FilePath> + </File> + </Files> + </Group> + <Group> + <GroupName>DeviceDrivers</GroupName> + <Files> + <File> + <FileName>pin.c</FileName> + <FileType>1</FileType> + <FilePath>..\..\components\drivers\misc\pin.c</FilePath> + </File> + </Files> + <Files> + <File> + <FileName>serial.c</FileName> + <FileType>1</FileType> + <FilePath>..\..\components\drivers\serial\serial.c</FilePath> + </File> + </Files> + <Files> + <File> + <FileName>completion.c</FileName> + <FileType>1</FileType> + <FilePath>..\..\components\drivers\src\completion.c</FilePath> + </File> + </Files> + <Files> + <File> + <FileName>dataqueue.c</FileName> + <FileType>1</FileType> + <FilePath>..\..\components\drivers\src\dataqueue.c</FilePath> + </File> + </Files> + <Files> + <File> + <FileName>pipe.c</FileName> + <FileType>1</FileType> + <FilePath>..\..\components\drivers\src\pipe.c</FilePath> + </File> + </Files> + <Files> + <File> + <FileName>ringblk_buf.c</FileName> + <FileType>1</FileType> + <FilePath>..\..\components\drivers\src\ringblk_buf.c</FilePath> + </File> + </Files> + <Files> + <File> + <FileName>ringbuffer.c</FileName> + <FileType>1</FileType> + <FilePath>..\..\components\drivers\src\ringbuffer.c</FilePath> + </File> + </Files> + <Files> + <File> + <FileName>waitqueue.c</FileName> + <FileType>1</FileType> + <FilePath>..\..\components\drivers\src\waitqueue.c</FilePath> + </File> + </Files> + <Files> + <File> + <FileName>workqueue.c</FileName> + <FileType>1</FileType> + <FilePath>..\..\components\drivers\src\workqueue.c</FilePath> + </File> + </Files> + </Group> + <Group> + <GroupName>finsh</GroupName> + <Files> + <File> + <FileName>shell.c</FileName> + <FileType>1</FileType> + <FilePath>..\..\components\finsh\shell.c</FilePath> + </File> + </Files> + <Files> + <File> + <FileName>symbol.c</FileName> + <FileType>1</FileType> + <FilePath>..\..\components\finsh\symbol.c</FilePath> + </File> + </Files> + <Files> + <File> + <FileName>cmd.c</FileName> + <FileType>1</FileType> + <FilePath>..\..\components\finsh\cmd.c</FilePath> + </File> + </Files> + <Files> + <File> + <FileName>msh.c</FileName> + <FileType>1</FileType> + <FilePath>..\..\components\finsh\msh.c</FilePath> + </File> + </Files> + <Files> + <File> + <FileName>msh_cmd.c</FileName> + <FileType>1</FileType> + <FilePath>..\..\components\finsh\msh_cmd.c</FilePath> + </File> + </Files> + <Files> + <File> + <FileName>msh_file.c</FileName> + <FileType>1</FileType> + <FilePath>..\..\components\finsh\msh_file.c</FilePath> + </File> + </Files> + <Files> + <File> + <FileName>finsh_compiler.c</FileName> + <FileType>1</FileType> + <FilePath>..\..\components\finsh\finsh_compiler.c</FilePath> + </File> + </Files> + <Files> + <File> + <FileName>finsh_error.c</FileName> + <FileType>1</FileType> + <FilePath>..\..\components\finsh\finsh_error.c</FilePath> + </File> + </Files> + <Files> + <File> + <FileName>finsh_heap.c</FileName> + <FileType>1</FileType> + <FilePath>..\..\components\finsh\finsh_heap.c</FilePath> + </File> + </Files> + <Files> + <File> + <FileName>finsh_init.c</FileName> + <FileType>1</FileType> + <FilePath>..\..\components\finsh\finsh_init.c</FilePath> + </File> + </Files> + <Files> + <File> + <FileName>finsh_node.c</FileName> + <FileType>1</FileType> + <FilePath>..\..\components\finsh\finsh_node.c</FilePath> + </File> + </Files> + <Files> + <File> + <FileName>finsh_ops.c</FileName> + <FileType>1</FileType> + <FilePath>..\..\components\finsh\finsh_ops.c</FilePath> + </File> + </Files> + <Files> + <File> + <FileName>finsh_parser.c</FileName> + <FileType>1</FileType> + <FilePath>..\..\components\finsh\finsh_parser.c</FilePath> + </File> + </Files> + <Files> + <File> + <FileName>finsh_var.c</FileName> + <FileType>1</FileType> + <FilePath>..\..\components\finsh\finsh_var.c</FilePath> + </File> + </Files> + <Files> + <File> + <FileName>finsh_vm.c</FileName> + <FileType>1</FileType> + <FilePath>..\..\components\finsh\finsh_vm.c</FilePath> + </File> + </Files> + <Files> + <File> + <FileName>finsh_token.c</FileName> + <FileType>1</FileType> + <FilePath>..\..\components\finsh\finsh_token.c</FilePath> + </File> + </Files> + </Group> + </Groups> + </Target> + </Targets> +</Project> diff --git a/bsp/swm320-lq100/project.uvprojx b/bsp/swm320-lq100/project.uvprojx index a47e63c81f..e493d83fca 100644 --- a/bsp/swm320-lq100/project.uvprojx +++ b/bsp/swm320-lq100/project.uvprojx @@ -1,43 +1,46 @@ <?xml version="1.0" encoding="UTF-8" standalone="no" ?> <Project xmlns:xsi="http://www.w3.org/2001/XMLSchema-instance" xsi:noNamespaceSchemaLocation="project_projx.xsd"> + <SchemaVersion>2.1</SchemaVersion> + <Header>### uVision Project, (C) Keil Software</Header> + <Targets> <Target> - <TargetName>rt-thread</TargetName> + <TargetName>rtthread</TargetName> <ToolsetNumber>0x4</ToolsetNumber> <ToolsetName>ARM-ADS</ToolsetName> - <pCCUsed>5060528::V5.06 update 5 (build 528)::ARMCC</pCCUsed> + <pCCUsed>5060960::V5.06 update 7 (build 960)::.\ARMCC</pCCUsed> <uAC6>0</uAC6> <TargetOption> <TargetCommonOption> <Device>SWM320xE</Device> <Vendor>Synwit</Vendor> - <PackID>Synwit.SWM32_DFP.1.6.2</PackID> + <PackID>Synwit.SWM32_DFP.1.16.6</PackID> <PackURL>http://www.synwit.com/pack</PackURL> <Cpu>IRAM(0x20000000,0x20000) IROM(0x00000000,0x80000) CPUTYPE("Cortex-M4") CLOCK(12000000) ELITTLE</Cpu> - <FlashUtilSpec /> - <StartupFile /> + <FlashUtilSpec></FlashUtilSpec> + <StartupFile></StartupFile> <FlashDriverDll>UL2CM3(-S0 -C0 -P0 -FD20000000 -FC1000 -FN1 -FF0SWM320xE -FS00 -FL080000 -FP0($$Device:SWM320xE$Flash\SWM320xE.FLM))</FlashDriverDll> <DeviceId>0</DeviceId> <RegisterFile>$$Device:SWM320xE$CSL\SWM320\CMSIS\DeviceSupport\SWM320.h</RegisterFile> - <MemoryEnv /> - <Cmp /> - <Asm /> - <Linker /> - <OHString /> - <InfinionOptionDll /> - <SLE66CMisc /> - <SLE66AMisc /> - <SLE66LinkerMisc /> + <MemoryEnv></MemoryEnv> + <Cmp></Cmp> + <Asm></Asm> + <Linker></Linker> + <OHString></OHString> + <InfinionOptionDll></InfinionOptionDll> + <SLE66CMisc></SLE66CMisc> + <SLE66AMisc></SLE66AMisc> + <SLE66LinkerMisc></SLE66LinkerMisc> <SFDFile>$$Device:SWM320xE$SVD\SWM320.svd</SFDFile> <bCustSvd>0</bCustSvd> <UseEnv>0</UseEnv> - <BinPath /> - <IncludePath /> - <LibPath /> - <RegisterFilePath /> - <DBRegisterFilePath /> + <BinPath></BinPath> + <IncludePath></IncludePath> + <LibPath></LibPath> + <RegisterFilePath></RegisterFilePath> + <DBRegisterFilePath></DBRegisterFilePath> <TargetStatus> <Error>0</Error> <ExitCodeStop>0</ExitCodeStop> @@ -59,8 +62,8 @@ <BeforeCompile> <RunUserProg1>0</RunUserProg1> <RunUserProg2>0</RunUserProg2> - <UserProg1Name /> - <UserProg2Name /> + <UserProg1Name></UserProg1Name> + <UserProg2Name></UserProg2Name> <UserProg1Dos16Mode>0</UserProg1Dos16Mode> <UserProg2Dos16Mode>0</UserProg2Dos16Mode> <nStopU1X>0</nStopU1X> @@ -69,8 +72,8 @@ <BeforeMake> <RunUserProg1>0</RunUserProg1> <RunUserProg2>0</RunUserProg2> - <UserProg1Name /> - <UserProg2Name /> + <UserProg1Name></UserProg1Name> + <UserProg2Name></UserProg2Name> <UserProg1Dos16Mode>0</UserProg1Dos16Mode> <UserProg2Dos16Mode>0</UserProg2Dos16Mode> <nStopB1X>0</nStopB1X> @@ -80,14 +83,14 @@ <RunUserProg1>1</RunUserProg1> <RunUserProg2>0</RunUserProg2> <UserProg1Name>fromelf --bin !L --output rtthread.bin</UserProg1Name> - <UserProg2Name /> + <UserProg2Name></UserProg2Name> <UserProg1Dos16Mode>0</UserProg1Dos16Mode> <UserProg2Dos16Mode>0</UserProg2Dos16Mode> <nStopA1X>0</nStopA1X> <nStopA2X>0</nStopA2X> </AfterMake> <SelectedForBatchBuild>0</SelectedForBatchBuild> - <SVCSIdString /> + <SVCSIdString></SVCSIdString> </TargetCommonOption> <CommonProperty> <UseCPPCompiler>0</UseCPPCompiler> @@ -101,8 +104,8 @@ <AssembleAssemblyFile>0</AssembleAssemblyFile> <PublicsOnly>0</PublicsOnly> <StopOnExitCode>3</StopOnExitCode> - <CustomArgument /> - <IncludeLibraryModules /> + <CustomArgument></CustomArgument> + <IncludeLibraryModules></IncludeLibraryModules> <ComprImg>1</ComprImg> </CommonProperty> <DllOption> @@ -111,7 +114,7 @@ <SimDlgDll>DCM.DLL</SimDlgDll> <SimDlgDllArguments>-pCM4</SimDlgDllArguments> <TargetDllName>SARMCM3.DLL</TargetDllName> - <TargetDllArguments /> + <TargetDllArguments></TargetDllArguments> <TargetDlgDll>TCM.DLL</TargetDlgDll> <TargetDlgDllArguments>-pCM4</TargetDlgDllArguments> </DllOption> @@ -135,11 +138,11 @@ </Flash1> <bUseTDR>1</bUseTDR> <Flash2>BIN\UL2CM3.DLL</Flash2> - <Flash3 /> - <Flash4 /> - <pFcarmOut /> - <pFcarmGrp /> - <pFcArmRoot /> + <Flash3></Flash3> + <Flash4></Flash4> + <pFcarmOut></pFcarmOut> + <pFcarmGrp></pFcarmGrp> + <pFcArmRoot></pFcArmRoot> <FcArmLst>0</FcArmLst> </Utilities> <TargetArmAds> @@ -172,7 +175,7 @@ <RvctClst>0</RvctClst> <GenPPlst>0</GenPPlst> <AdsCpuType>"Cortex-M4"</AdsCpuType> - <RvctDeviceName /> + <RvctDeviceName></RvctDeviceName> <mOS>0</mOS> <uocRom>0</uocRom> <uocRam>0</uocRam> @@ -181,6 +184,8 @@ <hadXRAM>0</hadXRAM> <uocXRam>0</uocXRam> <RvdsVP>0</RvdsVP> + <RvdsMve>0</RvdsMve> + <RvdsCdeCp>0</RvdsCdeCp> <hadIRAM2>0</hadIRAM2> <hadIROM2>0</hadIROM2> <StupSel>8</StupSel> @@ -304,7 +309,7 @@ <Size>0x0</Size> </OCR_RVCT10> </OnChipMemories> - <RvctStartVector /> + <RvctStartVector></RvctStartVector> </ArmAdsMisc> <Cads> <interw>1</interw> @@ -317,23 +322,24 @@ <PlainCh>0</PlainCh> <Ropi>0</Ropi> <Rwpi>0</Rwpi> - <wLevel>0</wLevel> + <wLevel>2</wLevel> <uThumb>0</uThumb> <uSurpInc>0</uSurpInc> <uC99>1</uC99> + <uGnu>0</uGnu> <useXO>0</useXO> - <v6Lang>0</v6Lang> - <v6LangP>0</v6LangP> - <vShortEn>0</vShortEn> - <vShortWch>0</vShortWch> + <v6Lang>1</v6Lang> + <v6LangP>1</v6LangP> + <vShortEn>1</vShortEn> + <vShortWch>1</vShortWch> <v6Lto>0</v6Lto> <v6WtE>0</v6WtE> <v6Rtti>0</v6Rtti> <VariousControls> - <MiscControls /> - <Define /> - <Undefine /> - <IncludePath>.;..\..\include;applications;.;drivers;Libraries\CMSIS\CoreSupport;Libraries\CMSIS\DeviceSupport;Libraries\SWM320_StdPeriph_Driver;..\..\libcpu\arm\common;..\..\libcpu\arm\cortex-m4;..\..\components\drivers\include;..\..\components\drivers\include;..\..\components\drivers\include;..\..\components\drivers\include;..\..\components\finsh;..\..\components\libc\compilers\common</IncludePath> + <MiscControls></MiscControls> + <Define>RT_USING_ARM_LIBC, __RTTHREAD__, __CLK_TCK=RT_TICK_PER_SECOND</Define> + <Undefine></Undefine> + <IncludePath>applications;.;..\..\libcpu\arm\common;..\..\libcpu\arm\cortex-m4;..\..\components\drivers\include;..\..\components\drivers\include;..\..\components\drivers\include;drivers;..\..\components\finsh;.;..\..\include;..\..\components\libc\compilers\armlibc;..\..\components\libc\compilers\common;..\..\components\libc\compilers\common\nogcc;libraries\CMSIS\CoreSupport;libraries\CMSIS\DeviceSupport;libraries\SWM320_StdPeriph_Driver;..\..\examples\utest\testcases\kernel</IncludePath> </VariousControls> </Cads> <Aads> @@ -346,12 +352,12 @@ <NoWarn>0</NoWarn> <uSurpInc>0</uSurpInc> <useXO>0</useXO> - <uClangAs>0</uClangAs> + <ClangAsOpt>4</ClangAsOpt> <VariousControls> - <MiscControls /> - <Define /> - <Undefine /> - <IncludePath /> + <MiscControls></MiscControls> + <Define></Define> + <Undefine></Undefine> + <IncludePath></IncludePath> </VariousControls> </Aads> <LDads> @@ -361,141 +367,106 @@ <noStLib>0</noStLib> <RepFail>1</RepFail> <useFile>0</useFile> - <TextAddressRange>0x00000000</TextAddressRange> + <TextAddressRange>0x08000000</TextAddressRange> <DataAddressRange>0x20000000</DataAddressRange> - <pXoBase /> + <pXoBase></pXoBase> <ScatterFile>.\drivers\linker_scripts\link.sct</ScatterFile> - <IncludeLibs /> - <IncludeLibsPath /> - <Misc /> - <LinkerInputFile /> - <DisabledWarnings /> + <IncludeLibs></IncludeLibs> + <IncludeLibsPath></IncludeLibsPath> + <Misc></Misc> + <LinkerInputFile></LinkerInputFile> + <DisabledWarnings></DisabledWarnings> </LDads> </TargetArmAds> </TargetOption> <Groups> <Group> - <GroupName>Kernel</GroupName> - <Files> - <File> - <FileName>clock.c</FileName> - <FileType>1</FileType> - <FilePath>..\..\src\clock.c</FilePath> - </File> - </Files> - <Files> - <File> - <FileName>components.c</FileName> - <FileType>1</FileType> - <FilePath>..\..\src\components.c</FilePath> - </File> - </Files> + <GroupName>Applications</GroupName> <Files> <File> - <FileName>cpu.c</FileName> + <FileName>main.c</FileName> <FileType>1</FileType> - <FilePath>..\..\src\cpu.c</FilePath> + <FilePath>applications\main.c</FilePath> </File> </Files> + </Group> + <Group> + <GroupName>CPU</GroupName> <Files> <File> - <FileName>device.c</FileName> + <FileName>backtrace.c</FileName> <FileType>1</FileType> - <FilePath>..\..\src\device.c</FilePath> + <FilePath>..\..\libcpu\arm\common\backtrace.c</FilePath> </File> - </Files> - <Files> <File> - <FileName>idle.c</FileName> + <FileName>showmem.c</FileName> <FileType>1</FileType> - <FilePath>..\..\src\idle.c</FilePath> + <FilePath>..\..\libcpu\arm\common\showmem.c</FilePath> </File> - </Files> - <Files> <File> - <FileName>ipc.c</FileName> + <FileName>div0.c</FileName> <FileType>1</FileType> - <FilePath>..\..\src\ipc.c</FilePath> + <FilePath>..\..\libcpu\arm\common\div0.c</FilePath> </File> - </Files> - <Files> <File> - <FileName>irq.c</FileName> - <FileType>1</FileType> - <FilePath>..\..\src\irq.c</FilePath> + <FileName>context_rvds.S</FileName> + <FileType>2</FileType> + <FilePath>..\..\libcpu\arm\cortex-m4\context_rvds.S</FilePath> </File> - </Files> - <Files> <File> - <FileName>kservice.c</FileName> + <FileName>cpuport.c</FileName> <FileType>1</FileType> - <FilePath>..\..\src\kservice.c</FilePath> + <FilePath>..\..\libcpu\arm\cortex-m4\cpuport.c</FilePath> </File> </Files> + </Group> + <Group> + <GroupName>DeviceDrivers</GroupName> <Files> <File> - <FileName>mem.c</FileName> + <FileName>pin.c</FileName> <FileType>1</FileType> - <FilePath>..\..\src\mem.c</FilePath> + <FilePath>..\..\components\drivers\misc\pin.c</FilePath> </File> - </Files> - <Files> <File> - <FileName>memheap.c</FileName> + <FileName>serial.c</FileName> <FileType>1</FileType> - <FilePath>..\..\src\memheap.c</FilePath> + <FilePath>..\..\components\drivers\serial\serial.c</FilePath> </File> - </Files> - <Files> <File> - <FileName>mempool.c</FileName> + <FileName>completion.c</FileName> <FileType>1</FileType> - <FilePath>..\..\src\mempool.c</FilePath> + <FilePath>..\..\components\drivers\src\completion.c</FilePath> </File> - </Files> - <Files> <File> - <FileName>object.c</FileName> + <FileName>ringbuffer.c</FileName> <FileType>1</FileType> - <FilePath>..\..\src\object.c</FilePath> + <FilePath>..\..\components\drivers\src\ringbuffer.c</FilePath> </File> - </Files> - <Files> <File> - <FileName>scheduler.c</FileName> + <FileName>waitqueue.c</FileName> <FileType>1</FileType> - <FilePath>..\..\src\scheduler.c</FilePath> + <FilePath>..\..\components\drivers\src\waitqueue.c</FilePath> </File> - </Files> - <Files> <File> - <FileName>signal.c</FileName> + <FileName>workqueue.c</FileName> <FileType>1</FileType> - <FilePath>..\..\src\signal.c</FilePath> + <FilePath>..\..\components\drivers\src\workqueue.c</FilePath> </File> - </Files> - <Files> <File> - <FileName>thread.c</FileName> + <FileName>ringblk_buf.c</FileName> <FileType>1</FileType> - <FilePath>..\..\src\thread.c</FilePath> + <FilePath>..\..\components\drivers\src\ringblk_buf.c</FilePath> </File> - </Files> - <Files> <File> - <FileName>timer.c</FileName> + <FileName>dataqueue.c</FileName> <FileType>1</FileType> - <FilePath>..\..\src\timer.c</FilePath> + <FilePath>..\..\components\drivers\src\dataqueue.c</FilePath> </File> - </Files> - </Group> - <Group> - <GroupName>Applications</GroupName> - <Files> <File> - <FileName>main.c</FileName> + <FileName>pipe.c</FileName> <FileType>1</FileType> - <FilePath>applications\main.c</FilePath> + <FilePath>..\..\components\drivers\src\pipe.c</FilePath> </File> </Files> </Group> @@ -503,394 +474,265 @@ <GroupName>Drivers</GroupName> <Files> <File> - <FileName>board.c</FileName> - <FileType>1</FileType> - <FilePath>drivers\board.c</FilePath> - </File> - </Files> - <Files> - <File> <FileName>drv_gpio.c</FileName> <FileType>1</FileType> <FilePath>drivers\drv_gpio.c</FilePath> </File> - </Files> - <Files> <File> <FileName>drv_uart.c</FileName> <FileType>1</FileType> <FilePath>drivers\drv_uart.c</FilePath> </File> - </Files> - </Group> - <Group> - <GroupName>Libraries</GroupName> - <Files> - <File> - <FileName>system_SWM320.c</FileName> - <FileType>1</FileType> - <FilePath>Libraries\CMSIS\DeviceSupport\system_SWM320.c</FilePath> - </File> - </Files> - <Files> <File> - <FileName>SWM320_adc.c</FileName> - <FileType>1</FileType> - <FilePath>Libraries\SWM320_StdPeriph_Driver\SWM320_adc.c</FilePath> - </File> - </Files> - <Files> - <File> - <FileName>SWM320_can.c</FileName> + <FileName>board.c</FileName> <FileType>1</FileType> - <FilePath>Libraries\SWM320_StdPeriph_Driver\SWM320_can.c</FilePath> + <FilePath>drivers\board.c</FilePath> </File> </Files> + </Group> + <Group> + <GroupName>Finsh</GroupName> <Files> <File> - <FileName>SWM320_crc.c</FileName> + <FileName>shell.c</FileName> <FileType>1</FileType> - <FilePath>Libraries\SWM320_StdPeriph_Driver\SWM320_crc.c</FilePath> + <FilePath>..\..\components\finsh\shell.c</FilePath> </File> - </Files> - <Files> <File> - <FileName>SWM320_dma.c</FileName> + <FileName>msh.c</FileName> <FileType>1</FileType> - <FilePath>Libraries\SWM320_StdPeriph_Driver\SWM320_dma.c</FilePath> + <FilePath>..\..\components\finsh\msh.c</FilePath> </File> - </Files> - <Files> <File> - <FileName>SWM320_exti.c</FileName> + <FileName>cmd.c</FileName> <FileType>1</FileType> - <FilePath>Libraries\SWM320_StdPeriph_Driver\SWM320_exti.c</FilePath> + <FilePath>..\..\components\finsh\cmd.c</FilePath> </File> </Files> + </Group> + <Group> + <GroupName>Kernel</GroupName> <Files> <File> - <FileName>SWM320_flash.c</FileName> + <FileName>mempool.c</FileName> <FileType>1</FileType> - <FilePath>Libraries\SWM320_StdPeriph_Driver\SWM320_flash.c</FilePath> + <FilePath>..\..\src\mempool.c</FilePath> </File> - </Files> - <Files> <File> - <FileName>SWM320_gpio.c</FileName> + <FileName>clock.c</FileName> <FileType>1</FileType> - <FilePath>Libraries\SWM320_StdPeriph_Driver\SWM320_gpio.c</FilePath> + <FilePath>..\..\src\clock.c</FilePath> </File> - </Files> - <Files> <File> - <FileName>SWM320_i2c.c</FileName> + <FileName>timer.c</FileName> <FileType>1</FileType> - <FilePath>Libraries\SWM320_StdPeriph_Driver\SWM320_i2c.c</FilePath> + <FilePath>..\..\src\timer.c</FilePath> </File> - </Files> - <Files> <File> - <FileName>SWM320_lcd.c</FileName> + <FileName>device.c</FileName> <FileType>1</FileType> - <FilePath>Libraries\SWM320_StdPeriph_Driver\SWM320_lcd.c</FilePath> + <FilePath>..\..\src\device.c</FilePath> </File> - </Files> - <Files> <File> - <FileName>SWM320_norflash.c</FileName> - <FileType>1</FileType> - <FilePath>Libraries\SWM320_StdPeriph_Driver\SWM320_norflash.c</FilePath> - </File> - </Files> - <Files> - <File> - <FileName>SWM320_port.c</FileName> + <FileName>object.c</FileName> <FileType>1</FileType> - <FilePath>Libraries\SWM320_StdPeriph_Driver\SWM320_port.c</FilePath> + <FilePath>..\..\src\object.c</FilePath> </File> - </Files> - <Files> <File> - <FileName>SWM320_pwm.c</FileName> + <FileName>kservice.c</FileName> <FileType>1</FileType> - <FilePath>Libraries\SWM320_StdPeriph_Driver\SWM320_pwm.c</FilePath> + <FilePath>..\..\src\kservice.c</FilePath> </File> - </Files> - <Files> <File> - <FileName>SWM320_rtc.c</FileName> + <FileName>thread.c</FileName> <FileType>1</FileType> - <FilePath>Libraries\SWM320_StdPeriph_Driver\SWM320_rtc.c</FilePath> + <FilePath>..\..\src\thread.c</FilePath> </File> - </Files> - <Files> <File> - <FileName>SWM320_sdio.c</FileName> + <FileName>memheap.c</FileName> <FileType>1</FileType> - <FilePath>Libraries\SWM320_StdPeriph_Driver\SWM320_sdio.c</FilePath> + <FilePath>..\..\src\memheap.c</FilePath> </File> - </Files> - <Files> <File> - <FileName>SWM320_sdram.c</FileName> + <FileName>idle.c</FileName> <FileType>1</FileType> - <FilePath>Libraries\SWM320_StdPeriph_Driver\SWM320_sdram.c</FilePath> + <FilePath>..\..\src\idle.c</FilePath> </File> - </Files> - <Files> <File> - <FileName>SWM320_spi.c</FileName> + <FileName>ipc.c</FileName> <FileType>1</FileType> - <FilePath>Libraries\SWM320_StdPeriph_Driver\SWM320_spi.c</FilePath> + <FilePath>..\..\src\ipc.c</FilePath> </File> - </Files> - <Files> <File> - <FileName>SWM320_timr.c</FileName> + <FileName>irq.c</FileName> <FileType>1</FileType> - <FilePath>Libraries\SWM320_StdPeriph_Driver\SWM320_timr.c</FilePath> + <FilePath>..\..\src\irq.c</FilePath> </File> - </Files> - <Files> <File> - <FileName>SWM320_uart.c</FileName> + <FileName>components.c</FileName> <FileType>1</FileType> - <FilePath>Libraries\SWM320_StdPeriph_Driver\SWM320_uart.c</FilePath> + <FilePath>..\..\src\components.c</FilePath> </File> - </Files> - <Files> <File> - <FileName>SWM320_wdt.c</FileName> + <FileName>scheduler.c</FileName> <FileType>1</FileType> - <FilePath>Libraries\SWM320_StdPeriph_Driver\SWM320_wdt.c</FilePath> - </File> - </Files> - <Files> - <File> - <FileName>startup_SWM320.s</FileName> - <FileType>2</FileType> - <FilePath>Libraries\CMSIS\DeviceSupport\startup\arm\startup_SWM320.s</FilePath> + <FilePath>..\..\src\scheduler.c</FilePath> </File> </Files> </Group> <Group> - <GroupName>cpu</GroupName> + <GroupName>libc</GroupName> <Files> <File> - <FileName>backtrace.c</FileName> + <FileName>libc.c</FileName> <FileType>1</FileType> - <FilePath>..\..\libcpu\arm\common\backtrace.c</FilePath> + <FilePath>..\..\components\libc\compilers\armlibc\libc.c</FilePath> </File> - </Files> - <Files> <File> - <FileName>div0.c</FileName> + <FileName>mem_std.c</FileName> <FileType>1</FileType> - <FilePath>..\..\libcpu\arm\common\div0.c</FilePath> + <FilePath>..\..\components\libc\compilers\armlibc\mem_std.c</FilePath> </File> - </Files> - <Files> <File> - <FileName>showmem.c</FileName> + <FileName>syscalls.c</FileName> <FileType>1</FileType> - <FilePath>..\..\libcpu\arm\common\showmem.c</FilePath> + <FilePath>..\..\components\libc\compilers\armlibc\syscalls.c</FilePath> </File> - </Files> - <Files> <File> - <FileName>cpuport.c</FileName> + <FileName>time.c</FileName> <FileType>1</FileType> - <FilePath>..\..\libcpu\arm\cortex-m4\cpuport.c</FilePath> + <FilePath>..\..\components\libc\compilers\common\time.c</FilePath> </File> - </Files> - <Files> <File> - <FileName>context_rvds.S</FileName> - <FileType>2</FileType> - <FilePath>..\..\libcpu\arm\cortex-m4\context_rvds.S</FilePath> + <FileName>stdlib.c</FileName> + <FileType>1</FileType> + <FilePath>..\..\components\libc\compilers\common\stdlib.c</FilePath> </File> </Files> </Group> <Group> - <GroupName>DeviceDrivers</GroupName> - <Files> - <File> - <FileName>hwtimer.c</FileName> - <FileType>1</FileType> - <FilePath>..\..\components\drivers\hwtimer\hwtimer.c</FilePath> - </File> - </Files> - <Files> - <File> - <FileName>pin.c</FileName> - <FileType>1</FileType> - <FilePath>..\..\components\drivers\misc\pin.c</FilePath> - </File> - </Files> + <GroupName>Libraries</GroupName> <Files> <File> - <FileName>rt_drv_pwm.c</FileName> + <FileName>SWM320_adc.c</FileName> <FileType>1</FileType> - <FilePath>..\..\components\drivers\misc\rt_drv_pwm.c</FilePath> + <FilePath>libraries\SWM320_StdPeriph_Driver\SWM320_adc.c</FilePath> </File> - </Files> - <Files> <File> - <FileName>serial.c</FileName> + <FileName>SWM320_port.c</FileName> <FileType>1</FileType> - <FilePath>..\..\components\drivers\serial\serial.c</FilePath> + <FilePath>libraries\SWM320_StdPeriph_Driver\SWM320_port.c</FilePath> </File> - </Files> - <Files> <File> - <FileName>completion.c</FileName> + <FileName>SWM320_crc.c</FileName> <FileType>1</FileType> - <FilePath>..\..\components\drivers\src\completion.c</FilePath> + <FilePath>libraries\SWM320_StdPeriph_Driver\SWM320_crc.c</FilePath> </File> - </Files> - <Files> <File> - <FileName>dataqueue.c</FileName> + <FileName>SWM320_spi.c</FileName> <FileType>1</FileType> - <FilePath>..\..\components\drivers\src\dataqueue.c</FilePath> + <FilePath>libraries\SWM320_StdPeriph_Driver\SWM320_spi.c</FilePath> </File> - </Files> - <Files> <File> - <FileName>pipe.c</FileName> + <FileName>SWM320_uart.c</FileName> <FileType>1</FileType> - <FilePath>..\..\components\drivers\src\pipe.c</FilePath> + <FilePath>libraries\SWM320_StdPeriph_Driver\SWM320_uart.c</FilePath> </File> - </Files> - <Files> <File> - <FileName>ringblk_buf.c</FileName> + <FileName>system_SWM320.c</FileName> <FileType>1</FileType> - <FilePath>..\..\components\drivers\src\ringblk_buf.c</FilePath> + <FilePath>libraries\CMSIS\DeviceSupport\system_SWM320.c</FilePath> </File> - </Files> - <Files> <File> - <FileName>ringbuffer.c</FileName> + <FileName>SWM320_flash.c</FileName> <FileType>1</FileType> - <FilePath>..\..\components\drivers\src\ringbuffer.c</FilePath> + <FilePath>libraries\SWM320_StdPeriph_Driver\SWM320_flash.c</FilePath> </File> - </Files> - <Files> <File> - <FileName>waitqueue.c</FileName> + <FileName>SWM320_can.c</FileName> <FileType>1</FileType> - <FilePath>..\..\components\drivers\src\waitqueue.c</FilePath> + <FilePath>libraries\SWM320_StdPeriph_Driver\SWM320_can.c</FilePath> </File> - </Files> - <Files> <File> - <FileName>workqueue.c</FileName> + <FileName>SWM320_sram.c</FileName> <FileType>1</FileType> - <FilePath>..\..\components\drivers\src\workqueue.c</FilePath> + <FilePath>libraries\SWM320_StdPeriph_Driver\SWM320_sram.c</FilePath> </File> - </Files> - </Group> - <Group> - <GroupName>finsh</GroupName> - <Files> <File> - <FileName>shell.c</FileName> + <FileName>SWM320_exti.c</FileName> <FileType>1</FileType> - <FilePath>..\..\components\finsh\shell.c</FilePath> + <FilePath>libraries\SWM320_StdPeriph_Driver\SWM320_exti.c</FilePath> </File> - </Files> - <Files> <File> - <FileName>cmd.c</FileName> + <FileName>SWM320_sdram.c</FileName> <FileType>1</FileType> - <FilePath>..\..\components\finsh\cmd.c</FilePath> + <FilePath>libraries\SWM320_StdPeriph_Driver\SWM320_sdram.c</FilePath> </File> - </Files> - <Files> <File> - <FileName>msh.c</FileName> + <FileName>SWM320_i2c.c</FileName> <FileType>1</FileType> - <FilePath>..\..\components\finsh\msh.c</FilePath> + <FilePath>libraries\SWM320_StdPeriph_Driver\SWM320_i2c.c</FilePath> </File> - </Files> - <Files> <File> - <FileName>finsh_compiler.c</FileName> - <FileType>1</FileType> - <FilePath>..\..\components\finsh\finsh_compiler.c</FilePath> + <FileName>startup_SWM320.s</FileName> + <FileType>2</FileType> + <FilePath>libraries\CMSIS\DeviceSupport\startup\arm\startup_SWM320.s</FilePath> </File> - </Files> - <Files> <File> - <FileName>finsh_error.c</FileName> + <FileName>SWM320_dma.c</FileName> <FileType>1</FileType> - <FilePath>..\..\components\finsh\finsh_error.c</FilePath> + <FilePath>libraries\SWM320_StdPeriph_Driver\SWM320_dma.c</FilePath> </File> - </Files> - <Files> <File> - <FileName>finsh_heap.c</FileName> + <FileName>SWM320_rtc.c</FileName> <FileType>1</FileType> - <FilePath>..\..\components\finsh\finsh_heap.c</FilePath> + <FilePath>libraries\SWM320_StdPeriph_Driver\SWM320_rtc.c</FilePath> </File> - </Files> - <Files> <File> - <FileName>finsh_init.c</FileName> + <FileName>SWM320_sdio.c</FileName> <FileType>1</FileType> - <FilePath>..\..\components\finsh\finsh_init.c</FilePath> + <FilePath>libraries\SWM320_StdPeriph_Driver\SWM320_sdio.c</FilePath> </File> - </Files> - <Files> <File> - <FileName>finsh_node.c</FileName> + <FileName>SWM320_norflash.c</FileName> <FileType>1</FileType> - <FilePath>..\..\components\finsh\finsh_node.c</FilePath> + <FilePath>libraries\SWM320_StdPeriph_Driver\SWM320_norflash.c</FilePath> </File> - </Files> - <Files> <File> - <FileName>finsh_ops.c</FileName> + <FileName>SWM320_pwm.c</FileName> <FileType>1</FileType> - <FilePath>..\..\components\finsh\finsh_ops.c</FilePath> + <FilePath>libraries\SWM320_StdPeriph_Driver\SWM320_pwm.c</FilePath> </File> - </Files> - <Files> <File> - <FileName>finsh_parser.c</FileName> + <FileName>SWM320_timr.c</FileName> <FileType>1</FileType> - <FilePath>..\..\components\finsh\finsh_parser.c</FilePath> + <FilePath>libraries\SWM320_StdPeriph_Driver\SWM320_timr.c</FilePath> </File> - </Files> - <Files> <File> - <FileName>finsh_var.c</FileName> + <FileName>SWM320_wdt.c</FileName> <FileType>1</FileType> - <FilePath>..\..\components\finsh\finsh_var.c</FilePath> + <FilePath>libraries\SWM320_StdPeriph_Driver\SWM320_wdt.c</FilePath> </File> - </Files> - <Files> <File> - <FileName>finsh_vm.c</FileName> + <FileName>SWM320_gpio.c</FileName> <FileType>1</FileType> - <FilePath>..\..\components\finsh\finsh_vm.c</FilePath> + <FilePath>libraries\SWM320_StdPeriph_Driver\SWM320_gpio.c</FilePath> </File> - </Files> - <Files> <File> - <FileName>finsh_token.c</FileName> + <FileName>SWM320_lcd.c</FileName> <FileType>1</FileType> - <FilePath>..\..\components\finsh\finsh_token.c</FilePath> + <FilePath>libraries\SWM320_StdPeriph_Driver\SWM320_lcd.c</FilePath> </File> </Files> </Group> </Groups> </Target> </Targets> + <RTE> - <apis /> - <components /> - <files /> + <apis/> + <components/> + <files/> </RTE> + </Project> diff --git a/bsp/swm320-lq100/rtconfig.h b/bsp/swm320-lq100/rtconfig.h index 79097cad42..d037e16343 100644 --- a/bsp/swm320-lq100/rtconfig.h +++ b/bsp/swm320-lq100/rtconfig.h @@ -10,12 +10,15 @@ #define RT_ALIGN_SIZE 4 #define RT_THREAD_PRIORITY_32 #define RT_THREAD_PRIORITY_MAX 32 -#define RT_TICK_PER_SECOND 100 +#define RT_TICK_PER_SECOND 1000 #define RT_USING_OVERFLOW_CHECK #define RT_USING_HOOK #define RT_USING_IDLE_HOOK #define RT_IDLE_HOOK_LIST_SIZE 4 #define IDLE_THREAD_STACK_SIZE 256 + +/* kservice optimization */ + #define RT_DEBUG #define RT_DEBUG_COLOR @@ -31,7 +34,8 @@ #define RT_USING_MEMPOOL #define RT_USING_MEMHEAP -#define RT_USING_SMALL_MEM +#define RT_USING_MEMHEAP_AUTO_BINDING +#define RT_USING_MEMHEAP_AS_HEAP #define RT_USING_HEAP /* Kernel Device Object */ @@ -40,7 +44,11 @@ #define RT_USING_CONSOLE #define RT_CONSOLEBUF_SIZE 128 #define RT_CONSOLE_DEVICE_NAME "uart0" -#define RT_VER_NUM 0x40000 +#define RT_VER_NUM 0x40004 +#define ARCH_ARM +#define RT_USING_CPU_FFS +#define ARCH_ARM_CORTEX_M +#define ARCH_ARM_CORTEX_M4 /* RT-Thread Components */ @@ -55,16 +63,17 @@ /* Command shell */ #define RT_USING_FINSH +#define RT_USING_MSH +#define FINSH_USING_MSH #define FINSH_THREAD_NAME "tshell" +#define FINSH_THREAD_PRIORITY 20 +#define FINSH_THREAD_STACK_SIZE 4096 #define FINSH_USING_HISTORY #define FINSH_HISTORY_LINES 5 #define FINSH_USING_SYMTAB -#define FINSH_USING_DESCRIPTION -#define FINSH_THREAD_PRIORITY 20 -#define FINSH_THREAD_STACK_SIZE 4096 #define FINSH_CMD_SIZE 80 -#define FINSH_USING_MSH -#define FINSH_USING_MSH_DEFAULT +#define MSH_USING_BUILT_IN_COMMANDS +#define FINSH_USING_DESCRIPTION #define FINSH_ARG_MAX 10 /* Device virtual file system */ @@ -75,28 +84,28 @@ #define RT_USING_DEVICE_IPC #define RT_PIPE_BUFSZ 512 #define RT_USING_SERIAL -#define RT_USING_HWTIMER +#define RT_USING_SERIAL_V1 +#define RT_SERIAL_RB_BUFSZ 64 #define RT_USING_PIN -#define RT_USING_PWM - -/* Using WiFi */ - /* Using USB */ /* POSIX layer and C standard library */ +#define RT_USING_LIBC +#define RT_LIBC_USING_TIME +#define RT_LIBC_DEFAULT_TIMEZONE 8 /* Network */ /* Socket abstraction layer */ -/* light weight TCP/IP stack */ +/* Network interface device */ -/* Modbus master and slave stack */ +/* light weight TCP/IP stack */ /* AT commands */ @@ -108,6 +117,9 @@ /* Utilities */ +/* RT-Thread Utestcases */ + + /* RT-Thread online packages */ /* IoT - internet of things */ @@ -138,41 +150,35 @@ /* system packages */ +/* acceleration: Assembly language or algorithmic acceleration packages */ -/* peripheral libraries and drivers */ +/* Micrium: Micrium software products porting for RT-Thread */ -/* miscellaneous packages */ +/* peripheral libraries and drivers */ -/* samples: kernel and components samples */ - -#define SOC_SWM320VET7 - -/* Hardware Drivers Config */ - -/* On-chip Peripheral Drivers */ - -#define BSP_USING_GPIO - -/* UART Drivers */ -#define BSP_USING_UART0 +/* AI packages */ -/* SPI Drivers */ +/* miscellaneous packages */ -/* I2C Drivers */ +/* samples: kernel and components samples */ -/* PWM Drivers */ +/* entertainment: terminal games and other interesting software packages */ -/* RTC Drivers */ +/* Hardware Drivers Config */ +#define SOC_SWM320 -/* HWtimer Drivers */ +/* On-chip Peripheral Drivers */ +#define BSP_USING_UART +#define BSP_USING_UART0 +#define BSP_USING_GPIO /* Onboard Peripheral Drivers */ diff --git a/bsp/swm320-lq100/rtconfig.py b/bsp/swm320-lq100/rtconfig.py index 7d827e2ab2..f90b490392 100644 --- a/bsp/swm320-lq100/rtconfig.py +++ b/bsp/swm320-lq100/rtconfig.py @@ -1,29 +1,25 @@ -# BSP Note: For TI EK-TM4C1294XL Tiva C Series Connected LancuhPad (REV D) - import os -import sys + # toolchains options -CROSS_TOOL = 'gcc' +ARCH='arm' +CPU='cortex-m4' +CROSS_TOOL='gcc' if os.getenv('RTT_CC'): CROSS_TOOL = os.getenv('RTT_CC') -# device options -ARCH = 'arm' -CPU = 'cortex-m4' -FPU = 'fpv4-sp-d16' -FLOAT_ABI = 'softfp' +if os.getenv('RTT_ROOT'): + RTT_ROOT = os.getenv('RTT_ROOT') -# cross_tool provides the cross compiler -# EXEC_PATH is the compiler execute path, for example, CodeSourcery, Keil MDK, IAR -if CROSS_TOOL == 'gcc': - PLATFORM = 'gcc' - EXEC_PATH = '/Users/zhangyihong/.env/gcc-arm-none-eabi-5_4-2016q3/bin' +# EXEC_PATH is the compiler execute path, for example, GCC, Keil MDK, IAR +if CROSS_TOOL == 'gcc': + PLATFORM = 'gcc' + EXEC_PATH = r'C:\Users\XXYYZZ' elif CROSS_TOOL == 'keil': - PLATFORM = 'armcc' - EXEC_PATH = 'C:/Keil_v5' + PLATFORM = 'armcc' + EXEC_PATH = r'C:/Keil_v5' elif CROSS_TOOL == 'iar': - PLATFORM = 'iar' - EXEC_PATH = 'C:/Program Files (x86)/IAR Systems/Embedded Workbench 7.2' + PLATFORM = 'iar' + EXEC_PATH = r'C:/Program Files (x86)/IAR Systems/Embedded Workbench 8.0' if os.getenv('RTT_EXEC_PATH'): EXEC_PATH = os.getenv('RTT_EXEC_PATH') @@ -34,18 +30,17 @@ BUILD = 'debug' if PLATFORM == 'gcc': PREFIX = 'arm-none-eabi-' CC = PREFIX + 'gcc' - CXX = PREFIX + 'g++' AS = PREFIX + 'gcc' AR = PREFIX + 'ar' + CXX = PREFIX + 'g++' LINK = PREFIX + 'gcc' - TARGET_EXT = 'elf' SIZE = PREFIX + 'size' OBJDUMP = PREFIX + 'objdump' OBJCPY = PREFIX + 'objcopy' - DEVICE = ' -mcpu=' + CPU + ' -mthumb -mfpu=' + FPU + ' -mfloat-abi=' + \ - FLOAT_ABI + ' -ffunction-sections -fdata-sections' - CFLAGS = DEVICE + TARGET_EXT = 'elf' + DEVICE = ' -mcpu=' + CPU + ' -mthumb -ffunction-sections -fdata-sections' + CFLAGS = DEVICE + ' -g -Wall' AFLAGS = ' -c' + DEVICE + ' -x assembler-with-cpp -Wa,-mimplicit-it=thumb ' LFLAGS = DEVICE + ' -Wl,--gc-sections,-Map=rtthread.map,-cref,-u,Reset_Handler -T drivers/linker_scripts/link.lds' @@ -58,27 +53,30 @@ if PLATFORM == 'gcc': else: CFLAGS += ' -O2' + CXXFLAGS = CFLAGS + POST_ACTION = OBJCPY + ' -O binary $TARGET rtthread.bin\n' + SIZE + ' $TARGET \n' + elif PLATFORM == 'armcc': - # toolchains CC = 'armcc' + CXX = 'armcc' AS = 'armasm' AR = 'armar' LINK = 'armlink' TARGET_EXT = 'axf' - DEVICE = ' --cpu ' + CPU + '.fp ' - CFLAGS = '-c ' + DEVICE + ' --apcs=interwork --c99' + DEVICE = ' --cpu ' + CPU + CFLAGS = '-c ' + DEVICE + ' --apcs=interwork' AFLAGS = DEVICE + ' --apcs=interwork ' LFLAGS = DEVICE + ' --scatter "drivers/linker_scripts/link.sct" --info sizes --info totals --info unused --info veneers --list rtthread.map --strict' - CFLAGS += ' -I' + EXEC_PATH + '/ARM/ARMCC/INC' - LFLAGS += ' --libpath ' + EXEC_PATH + '/ARM/ARMCC/LIB' + CFLAGS += ' -I' + EXEC_PATH + '/ARM/ARMCC/include' + LFLAGS += ' --libpath=' + EXEC_PATH + '/ARM/ARMCC/lib' CFLAGS += ' -D__MICROLIB ' AFLAGS += ' --pd "__MICROLIB SETA 1" ' LFLAGS += ' --library_type=microlib ' - EXEC_PATH += '/arm/armcc/bin/' + EXEC_PATH += '/ARM/ARMCC/bin/' if BUILD == 'debug': CFLAGS += ' -g -O0' @@ -86,41 +84,41 @@ elif PLATFORM == 'armcc': else: CFLAGS += ' -O2' + CXXFLAGS = CFLAGS + CFLAGS += ' --c99' + POST_ACTION = 'fromelf --bin $TARGET --output rtthread.bin \nfromelf -z $TARGET' elif PLATFORM == 'iar': - # toolchains CC = 'iccarm' + CXX = 'iccarm' AS = 'iasmarm' AR = 'iarchive' LINK = 'ilinkarm' TARGET_EXT = 'out' - - DEVICE = '-Dewarm' # + ' -D' + PART_TYPE + DEVICE = '-Dewarm' CFLAGS = DEVICE CFLAGS += ' --diag_suppress Pa050' - CFLAGS += ' --no_cse' - CFLAGS += ' --no_unroll' - CFLAGS += ' --no_inline' - CFLAGS += ' --no_code_motion' - CFLAGS += ' --no_tbaa' - CFLAGS += ' --no_clustering' - CFLAGS += ' --no_scheduling' - - CFLAGS += ' --endian=little' - CFLAGS += ' --cpu=Cortex-M4' - CFLAGS += ' -e' - CFLAGS += ' --fpu=VFPv4_sp' - CFLAGS += ' --dlib_config "' + EXEC_PATH + '/arm/INC/c/DLib_Config_Normal.h"' + CFLAGS += ' --no_cse' + CFLAGS += ' --no_unroll' + CFLAGS += ' --no_inline' + CFLAGS += ' --no_code_motion' + CFLAGS += ' --no_tbaa' + CFLAGS += ' --no_clustering' + CFLAGS += ' --no_scheduling' + CFLAGS += ' --debug' + CFLAGS += ' --endian=little' + CFLAGS += ' --cpu=' + CPU + CFLAGS += ' -e' + CFLAGS += ' --dlib_config "' + EXEC_PATH + '/arm/INC/c/DLib_Config_Normal.h"' CFLAGS += ' --silent' - + AFLAGS = DEVICE - AFLAGS += ' -s+' - AFLAGS += ' -w+' - AFLAGS += ' -r' - AFLAGS += ' --cpu Cortex-M4' - AFLAGS += ' --fpu VFPv4_sp' + AFLAGS += ' -s+' + AFLAGS += ' -w+' + AFLAGS += ' -r' + AFLAGS += ' --cpu ' + CPU AFLAGS += ' -S' if BUILD == 'debug': @@ -129,9 +127,9 @@ elif PLATFORM == 'iar': else: CFLAGS += ' -Oh' + CXXFLAGS = CFLAGS LFLAGS = ' --config "drivers/linker_scripts/link.icf"' - LFLAGS += ' --entry __iar_program_start' - #LFLAGS += ' --silent' + LFLAGS += ' --entry __iar_program_start' EXEC_PATH = EXEC_PATH + '/arm/bin/' - POST_ACTION = '' + POST_ACTION = 'ielftool --bin $TARGET rtthread.bin' diff --git a/bsp/swm320-lq100/template.ewp b/bsp/swm320-lq100/template.ewp index 2ff75d9abc..7f8d4d4220 100644 --- a/bsp/swm320-lq100/template.ewp +++ b/bsp/swm320-lq100/template.ewp @@ -1,2032 +1,2031 @@ -<?xml version="1.0" encoding="UTF-8"?>
-<project>
- <fileVersion>3</fileVersion>
- <configuration>
- <name>rt-thread</name>
- <toolchain>
- <name>ARM</name>
- </toolchain>
- <debug>1</debug>
- <settings>
- <name>General</name>
- <archiveVersion>3</archiveVersion>
- <data>
- <version>29</version>
- <wantNonLocal>1</wantNonLocal>
- <debug>1</debug>
- <option>
- <name>ExePath</name>
- <state>build\iar\Exe</state>
- </option>
- <option>
- <name>ObjPath</name>
- <state>build\iar\Obj</state>
- </option>
- <option>
- <name>ListPath</name>
- <state>build\iar\List</state>
- </option>
- <option>
- <name>GEndianMode</name>
- <state>0</state>
- </option>
- <option>
- <name>Input description</name>
- <state>Automatic choice of formatter, without multibyte support.</state>
- </option>
- <option>
- <name>Output description</name>
- <state>Automatic choice of formatter, without multibyte support.</state>
- </option>
- <option>
- <name>GOutputBinary</name>
- <state>0</state>
- </option>
- <option>
- <name>OGCoreOrChip</name>
- <state>1</state>
- </option>
- <option>
- <name>GRuntimeLibSelect</name>
- <version>0</version>
- <state>1</state>
- </option>
- <option>
- <name>GRuntimeLibSelectSlave</name>
- <version>0</version>
- <state>1</state>
- </option>
- <option>
- <name>RTDescription</name>
- <state>Use the normal configuration of the C/C++ runtime library. No locale interface, C locale, no file descriptor support, no multibytes in printf and scanf, and no hex floats in strtod.</state>
- </option>
- <option>
- <name>OGProductVersion</name>
- <state>6.30.6.53380</state>
- </option>
- <option>
- <name>OGLastSavedByProductVersion</name>
- <state>8.11.3.13977</state>
- </option>
- <option>
- <name>GeneralEnableMisra</name>
- <state>0</state>
- </option>
- <option>
- <name>GeneralMisraVerbose</name>
- <state>0</state>
- </option>
- <option>
- <name>OGChipSelectEditMenu</name>
- <state>SWM320xE Synwit SWM320xE</state>
- </option>
- <option>
- <name>GenLowLevelInterface</name>
- <state>1</state>
- </option>
- <option>
- <name>GEndianModeBE</name>
- <state>1</state>
- </option>
- <option>
- <name>OGBufferedTerminalOutput</name>
- <state>0</state>
- </option>
- <option>
- <name>GenStdoutInterface</name>
- <state>0</state>
- </option>
- <option>
- <name>GeneralMisraRules98</name>
- <version>0</version>
- <state>1000111110110101101110011100111111101110011011000101110111101101100111111111111100110011111001110111001111111111111111111111111</state>
- </option>
- <option>
- <name>GeneralMisraVer</name>
- <state>0</state>
- </option>
- <option>
- <name>GeneralMisraRules04</name>
- <version>0</version>
- <state>111101110010111111111000110111111111111111111111111110010111101111010101111111111111111111111111101111111011111001111011111011111111111111111</state>
- </option>
- <option>
- <name>RTConfigPath2</name>
- <state>$TOOLKIT_DIR$\INC\c\DLib_Config_Normal.h</state>
- </option>
- <option>
- <name>GBECoreSlave</name>
- <version>25</version>
- <state>39</state>
- </option>
- <option>
- <name>OGUseCmsis</name>
- <state>0</state>
- </option>
- <option>
- <name>OGUseCmsisDspLib</name>
- <state>0</state>
- </option>
- <option>
- <name>GRuntimeLibThreads</name>
- <state>0</state>
- </option>
- <option>
- <name>CoreVariant</name>
- <version>25</version>
- <state>39</state>
- </option>
- <option>
- <name>GFPUDeviceSlave</name>
- <state>SWM320xE Synwit SWM320xE</state>
- </option>
- <option>
- <name>FPU2</name>
- <version>0</version>
- <state>4</state>
- </option>
- <option>
- <name>NrRegs</name>
- <version>0</version>
- <state>1</state>
- </option>
- <option>
- <name>NEON</name>
- <state>0</state>
- </option>
- <option>
- <name>GFPUCoreSlave2</name>
- <version>25</version>
- <state>39</state>
- </option>
- <option>
- <name>OGCMSISPackSelectDevice</name>
- </option>
- <option>
- <name>OgLibHeap</name>
- <state>0</state>
- </option>
- <option>
- <name>OGLibAdditionalLocale</name>
- <state>0</state>
- </option>
- <option>
- <name>OGPrintfVariant</name>
- <version>0</version>
- <state>0</state>
- </option>
- <option>
- <name>OGPrintfMultibyteSupport</name>
- <state>0</state>
- </option>
- <option>
- <name>OGScanfVariant</name>
- <version>0</version>
- <state>0</state>
- </option>
- <option>
- <name>OGScanfMultibyteSupport</name>
- <state>0</state>
- </option>
- <option>
- <name>GenLocaleTags</name>
- <state></state>
- </option>
- <option>
- <name>GenLocaleDisplayOnly</name>
- <state></state>
- </option>
- <option>
- <name>DSPExtension</name>
- <state>1</state>
- </option>
- </data>
- </settings>
- <settings>
- <name>ICCARM</name>
- <archiveVersion>2</archiveVersion>
- <data>
- <version>34</version>
- <wantNonLocal>1</wantNonLocal>
- <debug>1</debug>
- <option>
- <name>CCOptimizationNoSizeConstraints</name>
- <state>0</state>
- </option>
- <option>
- <name>CCDefines</name>
- <state></state>
- </option>
- <option>
- <name>CCPreprocFile</name>
- <state>0</state>
- </option>
- <option>
- <name>CCPreprocComments</name>
- <state>0</state>
- </option>
- <option>
- <name>CCPreprocLine</name>
- <state>0</state>
- </option>
- <option>
- <name>CCListCFile</name>
- <state>0</state>
- </option>
- <option>
- <name>CCListCMnemonics</name>
- <state>0</state>
- </option>
- <option>
- <name>CCListCMessages</name>
- <state>0</state>
- </option>
- <option>
- <name>CCListAssFile</name>
- <state>0</state>
- </option>
- <option>
- <name>CCListAssSource</name>
- <state>0</state>
- </option>
- <option>
- <name>CCEnableRemarks</name>
- <state>0</state>
- </option>
- <option>
- <name>CCDiagSuppress</name>
- <state>Pa050</state>
- </option>
- <option>
- <name>CCDiagRemark</name>
- <state></state>
- </option>
- <option>
- <name>CCDiagWarning</name>
- <state></state>
- </option>
- <option>
- <name>CCDiagError</name>
- <state></state>
- </option>
- <option>
- <name>CCObjPrefix</name>
- <state>1</state>
- </option>
- <option>
- <name>CCAllowList</name>
- <version>1</version>
- <state>00000000</state>
- </option>
- <option>
- <name>CCDebugInfo</name>
- <state>1</state>
- </option>
- <option>
- <name>IEndianMode</name>
- <state>1</state>
- </option>
- <option>
- <name>IProcessor</name>
- <state>1</state>
- </option>
- <option>
- <name>IExtraOptionsCheck</name>
- <state>0</state>
- </option>
- <option>
- <name>IExtraOptions</name>
- <state></state>
- </option>
- <option>
- <name>CCLangConformance</name>
- <state>0</state>
- </option>
- <option>
- <name>CCSignedPlainChar</name>
- <state>1</state>
- </option>
- <option>
- <name>CCRequirePrototypes</name>
- <state>0</state>
- </option>
- <option>
- <name>CCDiagWarnAreErr</name>
- <state>0</state>
- </option>
- <option>
- <name>CCCompilerRuntimeInfo</name>
- <state>0</state>
- </option>
- <option>
- <name>IFpuProcessor</name>
- <state>1</state>
- </option>
- <option>
- <name>OutputFile</name>
- <state>$FILE_BNAME$.o</state>
- </option>
- <option>
- <name>CCLibConfigHeader</name>
- <state>1</state>
- </option>
- <option>
- <name>PreInclude</name>
- <state></state>
- </option>
- <option>
- <name>CompilerMisraOverride</name>
- <state>0</state>
- </option>
- <option>
- <name>CCIncludePath2</name>
- <state></state>
- </option>
- <option>
- <name>CCStdIncCheck</name>
- <state>0</state>
- </option>
- <option>
- <name>CCCodeSection</name>
- <state>.text</state>
- </option>
- <option>
- <name>IProcessorMode2</name>
- <state>1</state>
- </option>
- <option>
- <name>CCOptLevel</name>
- <state>1</state>
- </option>
- <option>
- <name>CCOptStrategy</name>
- <version>0</version>
- <state>0</state>
- </option>
- <option>
- <name>CCOptLevelSlave</name>
- <state>1</state>
- </option>
- <option>
- <name>CompilerMisraRules98</name>
- <version>0</version>
- <state>1000111110110101101110011100111111101110011011000101110111101101100111111111111100110011111001110111001111111111111111111111111</state>
- </option>
- <option>
- <name>CompilerMisraRules04</name>
- <version>0</version>
- <state>111101110010111111111000110111111111111111111111111110010111101111010101111111111111111111111111101111111011111001111011111011111111111111111</state>
- </option>
- <option>
- <name>CCPosIndRopi</name>
- <state>0</state>
- </option>
- <option>
- <name>CCPosIndRwpi</name>
- <state>0</state>
- </option>
- <option>
- <name>CCPosIndNoDynInit</name>
- <state>0</state>
- </option>
- <option>
- <name>IccLang</name>
- <state>0</state>
- </option>
- <option>
- <name>IccCDialect</name>
- <state>1</state>
- </option>
- <option>
- <name>IccAllowVLA</name>
- <state>0</state>
- </option>
- <option>
- <name>IccStaticDestr</name>
- <state>1</state>
- </option>
- <option>
- <name>IccCppInlineSemantics</name>
- <state>0</state>
- </option>
- <option>
- <name>IccCmsis</name>
- <state>1</state>
- </option>
- <option>
- <name>IccFloatSemantics</name>
- <state>0</state>
- </option>
- <option>
- <name>CCNoLiteralPool</name>
- <state>0</state>
- </option>
- <option>
- <name>CCOptStrategySlave</name>
- <version>0</version>
- <state>0</state>
- </option>
- <option>
- <name>CCGuardCalls</name>
- <state>1</state>
- </option>
- <option>
- <name>CCEncSource</name>
- <state>0</state>
- </option>
- <option>
- <name>CCEncOutput</name>
- <state>0</state>
- </option>
- <option>
- <name>CCEncOutputBom</name>
- <state>1</state>
- </option>
- <option>
- <name>CCEncInput</name>
- <state>0</state>
- </option>
- <option>
- <name>IccExceptions2</name>
- <state>0</state>
- </option>
- <option>
- <name>IccRTTI2</name>
- <state>0</state>
- </option>
- </data>
- </settings>
- <settings>
- <name>AARM</name>
- <archiveVersion>2</archiveVersion>
- <data>
- <version>10</version>
- <wantNonLocal>1</wantNonLocal>
- <debug>1</debug>
- <option>
- <name>AObjPrefix</name>
- <state>1</state>
- </option>
- <option>
- <name>AEndian</name>
- <state>1</state>
- </option>
- <option>
- <name>ACaseSensitivity</name>
- <state>1</state>
- </option>
- <option>
- <name>MacroChars</name>
- <version>0</version>
- <state>0</state>
- </option>
- <option>
- <name>AWarnEnable</name>
- <state>0</state>
- </option>
- <option>
- <name>AWarnWhat</name>
- <state>0</state>
- </option>
- <option>
- <name>AWarnOne</name>
- <state></state>
- </option>
- <option>
- <name>AWarnRange1</name>
- <state></state>
- </option>
- <option>
- <name>AWarnRange2</name>
- <state></state>
- </option>
- <option>
- <name>ADebug</name>
- <state>1</state>
- </option>
- <option>
- <name>AltRegisterNames</name>
- <state>0</state>
- </option>
- <option>
- <name>ADefines</name>
- <state></state>
- </option>
- <option>
- <name>AList</name>
- <state>0</state>
- </option>
- <option>
- <name>AListHeader</name>
- <state>1</state>
- </option>
- <option>
- <name>AListing</name>
- <state>1</state>
- </option>
- <option>
- <name>Includes</name>
- <state>0</state>
- </option>
- <option>
- <name>MacDefs</name>
- <state>0</state>
- </option>
- <option>
- <name>MacExps</name>
- <state>1</state>
- </option>
- <option>
- <name>MacExec</name>
- <state>0</state>
- </option>
- <option>
- <name>OnlyAssed</name>
- <state>0</state>
- </option>
- <option>
- <name>MultiLine</name>
- <state>0</state>
- </option>
- <option>
- <name>PageLengthCheck</name>
- <state>0</state>
- </option>
- <option>
- <name>PageLength</name>
- <state>80</state>
- </option>
- <option>
- <name>TabSpacing</name>
- <state>8</state>
- </option>
- <option>
- <name>AXRef</name>
- <state>0</state>
- </option>
- <option>
- <name>AXRefDefines</name>
- <state>0</state>
- </option>
- <option>
- <name>AXRefInternal</name>
- <state>0</state>
- </option>
- <option>
- <name>AXRefDual</name>
- <state>0</state>
- </option>
- <option>
- <name>AProcessor</name>
- <state>1</state>
- </option>
- <option>
- <name>AFpuProcessor</name>
- <state>1</state>
- </option>
- <option>
- <name>AOutputFile</name>
- <state>$FILE_BNAME$.o</state>
- </option>
- <option>
- <name>ALimitErrorsCheck</name>
- <state>0</state>
- </option>
- <option>
- <name>ALimitErrorsEdit</name>
- <state>100</state>
- </option>
- <option>
- <name>AIgnoreStdInclude</name>
- <state>0</state>
- </option>
- <option>
- <name>AUserIncludes</name>
- <state></state>
- </option>
- <option>
- <name>AExtraOptionsCheckV2</name>
- <state>0</state>
- </option>
- <option>
- <name>AExtraOptionsV2</name>
- <state></state>
- </option>
- <option>
- <name>AsmNoLiteralPool</name>
- <state>0</state>
- </option>
- </data>
- </settings>
- <settings>
- <name>OBJCOPY</name>
- <archiveVersion>0</archiveVersion>
- <data>
- <version>1</version>
- <wantNonLocal>1</wantNonLocal>
- <debug>1</debug>
- <option>
- <name>OOCOutputFormat</name>
- <version>3</version>
- <state>3</state>
- </option>
- <option>
- <name>OCOutputOverride</name>
- <state>1</state>
- </option>
- <option>
- <name>OOCOutputFile</name>
- <state>../../../rtthread.bin</state>
- </option>
- <option>
- <name>OOCCommandLineProducer</name>
- <state>1</state>
- </option>
- <option>
- <name>OOCObjCopyEnable</name>
- <state>1</state>
- </option>
- </data>
- </settings>
- <settings>
- <name>CUSTOM</name>
- <archiveVersion>3</archiveVersion>
- <data>
- <extensions></extensions>
- <cmdline></cmdline>
- <hasPrio>0</hasPrio>
- </data>
- </settings>
- <settings>
- <name>BICOMP</name>
- <archiveVersion>0</archiveVersion>
- <data />
- </settings>
- <settings>
- <name>BUILDACTION</name>
- <archiveVersion>1</archiveVersion>
- <data>
- <prebuild></prebuild>
- <postbuild></postbuild>
- </data>
- </settings>
- <settings>
- <name>ILINK</name>
- <archiveVersion>0</archiveVersion>
- <data>
- <version>20</version>
- <wantNonLocal>1</wantNonLocal>
- <debug>1</debug>
- <option>
- <name>IlinkLibIOConfig</name>
- <state>1</state>
- </option>
- <option>
- <name>XLinkMisraHandler</name>
- <state>0</state>
- </option>
- <option>
- <name>IlinkInputFileSlave</name>
- <state>0</state>
- </option>
- <option>
- <name>IlinkOutputFile</name>
- <state>rtthread.out</state>
- </option>
- <option>
- <name>IlinkDebugInfoEnable</name>
- <state>1</state>
- </option>
- <option>
- <name>IlinkKeepSymbols</name>
- <state></state>
- </option>
- <option>
- <name>IlinkRawBinaryFile</name>
- <state></state>
- </option>
- <option>
- <name>IlinkRawBinarySymbol</name>
- <state></state>
- </option>
- <option>
- <name>IlinkRawBinarySegment</name>
- <state></state>
- </option>
- <option>
- <name>IlinkRawBinaryAlign</name>
- <state></state>
- </option>
- <option>
- <name>IlinkDefines</name>
- <state></state>
- </option>
- <option>
- <name>IlinkConfigDefines</name>
- <state></state>
- </option>
- <option>
- <name>IlinkMapFile</name>
- <state>0</state>
- </option>
- <option>
- <name>IlinkLogFile</name>
- <state>0</state>
- </option>
- <option>
- <name>IlinkLogInitialization</name>
- <state>0</state>
- </option>
- <option>
- <name>IlinkLogModule</name>
- <state>0</state>
- </option>
- <option>
- <name>IlinkLogSection</name>
- <state>0</state>
- </option>
- <option>
- <name>IlinkLogVeneer</name>
- <state>0</state>
- </option>
- <option>
- <name>IlinkIcfOverride</name>
- <state>1</state>
- </option>
- <option>
- <name>IlinkIcfFile</name>
- <state>$PROJ_DIR$\drivers\linker_scripts\link.icf</state>
- </option>
- <option>
- <name>IlinkIcfFileSlave</name>
- <state></state>
- </option>
- <option>
- <name>IlinkEnableRemarks</name>
- <state>0</state>
- </option>
- <option>
- <name>IlinkSuppressDiags</name>
- <state></state>
- </option>
- <option>
- <name>IlinkTreatAsRem</name>
- <state></state>
- </option>
- <option>
- <name>IlinkTreatAsWarn</name>
- <state></state>
- </option>
- <option>
- <name>IlinkTreatAsErr</name>
- <state></state>
- </option>
- <option>
- <name>IlinkWarningsAreErrors</name>
- <state>0</state>
- </option>
- <option>
- <name>IlinkUseExtraOptions</name>
- <state>0</state>
- </option>
- <option>
- <name>IlinkExtraOptions</name>
- <state></state>
- </option>
- <option>
- <name>IlinkLowLevelInterfaceSlave</name>
- <state>1</state>
- </option>
- <option>
- <name>IlinkAutoLibEnable</name>
- <state>1</state>
- </option>
- <option>
- <name>IlinkAdditionalLibs</name>
- <state></state>
- </option>
- <option>
- <name>IlinkOverrideProgramEntryLabel</name>
- <state>0</state>
- </option>
- <option>
- <name>IlinkProgramEntryLabelSelect</name>
- <state>0</state>
- </option>
- <option>
- <name>IlinkProgramEntryLabel</name>
- <state>__iar_program_start</state>
- </option>
- <option>
- <name>DoFill</name>
- <state>0</state>
- </option>
- <option>
- <name>FillerByte</name>
- <state>0xFF</state>
- </option>
- <option>
- <name>FillerStart</name>
- <state>0x0</state>
- </option>
- <option>
- <name>FillerEnd</name>
- <state>0x0</state>
- </option>
- <option>
- <name>CrcSize</name>
- <version>0</version>
- <state>1</state>
- </option>
- <option>
- <name>CrcAlign</name>
- <state>1</state>
- </option>
- <option>
- <name>CrcPoly</name>
- <state>0x11021</state>
- </option>
- <option>
- <name>CrcCompl</name>
- <version>0</version>
- <state>0</state>
- </option>
- <option>
- <name>CrcBitOrder</name>
- <version>0</version>
- <state>0</state>
- </option>
- <option>
- <name>CrcInitialValue</name>
- <state>0x0</state>
- </option>
- <option>
- <name>DoCrc</name>
- <state>0</state>
- </option>
- <option>
- <name>IlinkBE8Slave</name>
- <state>1</state>
- </option>
- <option>
- <name>IlinkBufferedTerminalOutput</name>
- <state>1</state>
- </option>
- <option>
- <name>IlinkStdoutInterfaceSlave</name>
- <state>1</state>
- </option>
- <option>
- <name>CrcFullSize</name>
- <state>0</state>
- </option>
- <option>
- <name>IlinkIElfToolPostProcess</name>
- <state>0</state>
- </option>
- <option>
- <name>IlinkLogAutoLibSelect</name>
- <state>0</state>
- </option>
- <option>
- <name>IlinkLogRedirSymbols</name>
- <state>0</state>
- </option>
- <option>
- <name>IlinkLogUnusedFragments</name>
- <state>0</state>
- </option>
- <option>
- <name>IlinkCrcReverseByteOrder</name>
- <state>0</state>
- </option>
- <option>
- <name>IlinkCrcUseAsInput</name>
- <state>1</state>
- </option>
- <option>
- <name>IlinkOptInline</name>
- <state>0</state>
- </option>
- <option>
- <name>IlinkOptExceptionsAllow</name>
- <state>1</state>
- </option>
- <option>
- <name>IlinkOptExceptionsForce</name>
- <state>0</state>
- </option>
- <option>
- <name>IlinkCmsis</name>
- <state>1</state>
- </option>
- <option>
- <name>IlinkOptMergeDuplSections</name>
- <state>0</state>
- </option>
- <option>
- <name>IlinkOptUseVfe</name>
- <state>1</state>
- </option>
- <option>
- <name>IlinkOptForceVfe</name>
- <state>0</state>
- </option>
- <option>
- <name>IlinkStackAnalysisEnable</name>
- <state>0</state>
- </option>
- <option>
- <name>IlinkStackControlFile</name>
- <state></state>
- </option>
- <option>
- <name>IlinkStackCallGraphFile</name>
- <state></state>
- </option>
- <option>
- <name>CrcAlgorithm</name>
- <version>1</version>
- <state>1</state>
- </option>
- <option>
- <name>CrcUnitSize</name>
- <version>0</version>
- <state>0</state>
- </option>
- <option>
- <name>IlinkThreadsSlave</name>
- <state>1</state>
- </option>
- <option>
- <name>IlinkLogCallGraph</name>
- <state>0</state>
- </option>
- <option>
- <name>IlinkIcfFile_AltDefault</name>
- <state></state>
- </option>
- <option>
- <name>IlinkEncInput</name>
- <state>0</state>
- </option>
- <option>
- <name>IlinkEncOutput</name>
- <state>0</state>
- </option>
- <option>
- <name>IlinkEncOutputBom</name>
- <state>1</state>
- </option>
- <option>
- <name>IlinkHeapSelect</name>
- <state>1</state>
- </option>
- <option>
- <name>IlinkLocaleSelect</name>
- <state>1</state>
- </option>
- </data>
- </settings>
- <settings>
- <name>IARCHIVE</name>
- <archiveVersion>0</archiveVersion>
- <data>
- <version>0</version>
- <wantNonLocal>1</wantNonLocal>
- <debug>1</debug>
- <option>
- <name>IarchiveInputs</name>
- <state></state>
- </option>
- <option>
- <name>IarchiveOverride</name>
- <state>0</state>
- </option>
- <option>
- <name>IarchiveOutput</name>
- <state>###Unitialized###</state>
- </option>
- </data>
- </settings>
- <settings>
- <name>BILINK</name>
- <archiveVersion>0</archiveVersion>
- <data />
- </settings>
- </configuration>
- <configuration>
- <name>Release</name>
- <toolchain>
- <name>ARM</name>
- </toolchain>
- <debug>0</debug>
- <settings>
- <name>General</name>
- <archiveVersion>3</archiveVersion>
- <data>
- <version>29</version>
- <wantNonLocal>1</wantNonLocal>
- <debug>0</debug>
- <option>
- <name>ExePath</name>
- <state>Release\Exe</state>
- </option>
- <option>
- <name>ObjPath</name>
- <state>Release\Obj</state>
- </option>
- <option>
- <name>ListPath</name>
- <state>Release\List</state>
- </option>
- <option>
- <name>GEndianMode</name>
- <state>0</state>
- </option>
- <option>
- <name>Input description</name>
- <state></state>
- </option>
- <option>
- <name>Output description</name>
- <state></state>
- </option>
- <option>
- <name>GOutputBinary</name>
- <state>0</state>
- </option>
- <option>
- <name>OGCoreOrChip</name>
- <state>0</state>
- </option>
- <option>
- <name>GRuntimeLibSelect</name>
- <version>0</version>
- <state>1</state>
- </option>
- <option>
- <name>GRuntimeLibSelectSlave</name>
- <version>0</version>
- <state>1</state>
- </option>
- <option>
- <name>RTDescription</name>
- <state></state>
- </option>
- <option>
- <name>OGProductVersion</name>
- <state>6.30.6.53380</state>
- </option>
- <option>
- <name>OGLastSavedByProductVersion</name>
- <state>8.11.3.13977</state>
- </option>
- <option>
- <name>GeneralEnableMisra</name>
- <state>0</state>
- </option>
- <option>
- <name>GeneralMisraVerbose</name>
- <state>0</state>
- </option>
- <option>
- <name>OGChipSelectEditMenu</name>
- <state>Default None</state>
- </option>
- <option>
- <name>GenLowLevelInterface</name>
- <state>0</state>
- </option>
- <option>
- <name>GEndianModeBE</name>
- <state>0</state>
- </option>
- <option>
- <name>OGBufferedTerminalOutput</name>
- <state>0</state>
- </option>
- <option>
- <name>GenStdoutInterface</name>
- <state>0</state>
- </option>
- <option>
- <name>GeneralMisraRules98</name>
- <version>0</version>
- <state>1000111110110101101110011100111111101110011011000101110111101101100111111111111100110011111001110111001111111111111111111111111</state>
- </option>
- <option>
- <name>GeneralMisraVer</name>
- <state>0</state>
- </option>
- <option>
- <name>GeneralMisraRules04</name>
- <version>0</version>
- <state>111101110010111111111000110111111111111111111111111110010111101111010101111111111111111111111111101111111011111001111011111011111111111111111</state>
- </option>
- <option>
- <name>RTConfigPath2</name>
- <state></state>
- </option>
- <option>
- <name>GBECoreSlave</name>
- <version>25</version>
- <state>1</state>
- </option>
- <option>
- <name>OGUseCmsis</name>
- <state>0</state>
- </option>
- <option>
- <name>OGUseCmsisDspLib</name>
- <state>0</state>
- </option>
- <option>
- <name>GRuntimeLibThreads</name>
- <state>0</state>
- </option>
- <option>
- <name>CoreVariant</name>
- <version>25</version>
- <state>0</state>
- </option>
- <option>
- <name>GFPUDeviceSlave</name>
- <state>Default None</state>
- </option>
- <option>
- <name>FPU2</name>
- <version>0</version>
- <state>0</state>
- </option>
- <option>
- <name>NrRegs</name>
- <version>0</version>
- <state>0</state>
- </option>
- <option>
- <name>NEON</name>
- <state>0</state>
- </option>
- <option>
- <name>GFPUCoreSlave2</name>
- <version>25</version>
- <state>0</state>
- </option>
- <option>
- <name>OGCMSISPackSelectDevice</name>
- </option>
- <option>
- <name>OgLibHeap</name>
- <state>0</state>
- </option>
- <option>
- <name>OGLibAdditionalLocale</name>
- <state>0</state>
- </option>
- <option>
- <name>OGPrintfVariant</name>
- <version>0</version>
- <state>0</state>
- </option>
- <option>
- <name>OGPrintfMultibyteSupport</name>
- <state>0</state>
- </option>
- <option>
- <name>OGScanfVariant</name>
- <version>0</version>
- <state>0</state>
- </option>
- <option>
- <name>OGScanfMultibyteSupport</name>
- <state>0</state>
- </option>
- <option>
- <name>GenLocaleTags</name>
- <state></state>
- </option>
- <option>
- <name>GenLocaleDisplayOnly</name>
- <state></state>
- </option>
- <option>
- <name>DSPExtension</name>
- <state>0</state>
- </option>
- </data>
- </settings>
- <settings>
- <name>ICCARM</name>
- <archiveVersion>2</archiveVersion>
- <data>
- <version>34</version>
- <wantNonLocal>1</wantNonLocal>
- <debug>0</debug>
- <option>
- <name>CCOptimizationNoSizeConstraints</name>
- <state>0</state>
- </option>
- <option>
- <name>CCDefines</name>
- <state></state>
- </option>
- <option>
- <name>CCPreprocFile</name>
- <state>0</state>
- </option>
- <option>
- <name>CCPreprocComments</name>
- <state>0</state>
- </option>
- <option>
- <name>CCPreprocLine</name>
- <state>0</state>
- </option>
- <option>
- <name>CCListCFile</name>
- <state>0</state>
- </option>
- <option>
- <name>CCListCMnemonics</name>
- <state>0</state>
- </option>
- <option>
- <name>CCListCMessages</name>
- <state>0</state>
- </option>
- <option>
- <name>CCListAssFile</name>
- <state>0</state>
- </option>
- <option>
- <name>CCListAssSource</name>
- <state>0</state>
- </option>
- <option>
- <name>CCEnableRemarks</name>
- <state>0</state>
- </option>
- <option>
- <name>CCDiagSuppress</name>
- <state></state>
- </option>
- <option>
- <name>CCDiagRemark</name>
- <state></state>
- </option>
- <option>
- <name>CCDiagWarning</name>
- <state></state>
- </option>
- <option>
- <name>CCDiagError</name>
- <state></state>
- </option>
- <option>
- <name>CCObjPrefix</name>
- <state>1</state>
- </option>
- <option>
- <name>CCAllowList</name>
- <version>1</version>
- <state>11111110</state>
- </option>
- <option>
- <name>CCDebugInfo</name>
- <state>0</state>
- </option>
- <option>
- <name>IEndianMode</name>
- <state>1</state>
- </option>
- <option>
- <name>IProcessor</name>
- <state>1</state>
- </option>
- <option>
- <name>IExtraOptionsCheck</name>
- <state>0</state>
- </option>
- <option>
- <name>IExtraOptions</name>
- <state></state>
- </option>
- <option>
- <name>CCLangConformance</name>
- <state>0</state>
- </option>
- <option>
- <name>CCSignedPlainChar</name>
- <state>1</state>
- </option>
- <option>
- <name>CCRequirePrototypes</name>
- <state>0</state>
- </option>
- <option>
- <name>CCDiagWarnAreErr</name>
- <state>0</state>
- </option>
- <option>
- <name>CCCompilerRuntimeInfo</name>
- <state>0</state>
- </option>
- <option>
- <name>IFpuProcessor</name>
- <state>1</state>
- </option>
- <option>
- <name>OutputFile</name>
- <state></state>
- </option>
- <option>
- <name>CCLibConfigHeader</name>
- <state>1</state>
- </option>
- <option>
- <name>PreInclude</name>
- <state></state>
- </option>
- <option>
- <name>CompilerMisraOverride</name>
- <state>0</state>
- </option>
- <option>
- <name>CCIncludePath2</name>
- <state></state>
- </option>
- <option>
- <name>CCStdIncCheck</name>
- <state>0</state>
- </option>
- <option>
- <name>CCCodeSection</name>
- <state>.text</state>
- </option>
- <option>
- <name>IProcessorMode2</name>
- <state>1</state>
- </option>
- <option>
- <name>CCOptLevel</name>
- <state>3</state>
- </option>
- <option>
- <name>CCOptStrategy</name>
- <version>0</version>
- <state>0</state>
- </option>
- <option>
- <name>CCOptLevelSlave</name>
- <state>1</state>
- </option>
- <option>
- <name>CompilerMisraRules98</name>
- <version>0</version>
- <state>1000111110110101101110011100111111101110011011000101110111101101100111111111111100110011111001110111001111111111111111111111111</state>
- </option>
- <option>
- <name>CompilerMisraRules04</name>
- <version>0</version>
- <state>111101110010111111111000110111111111111111111111111110010111101111010101111111111111111111111111101111111011111001111011111011111111111111111</state>
- </option>
- <option>
- <name>CCPosIndRopi</name>
- <state>0</state>
- </option>
- <option>
- <name>CCPosIndRwpi</name>
- <state>0</state>
- </option>
- <option>
- <name>CCPosIndNoDynInit</name>
- <state>0</state>
- </option>
- <option>
- <name>IccLang</name>
- <state>0</state>
- </option>
- <option>
- <name>IccCDialect</name>
- <state>1</state>
- </option>
- <option>
- <name>IccAllowVLA</name>
- <state>0</state>
- </option>
- <option>
- <name>IccStaticDestr</name>
- <state>1</state>
- </option>
- <option>
- <name>IccCppInlineSemantics</name>
- <state>0</state>
- </option>
- <option>
- <name>IccCmsis</name>
- <state>1</state>
- </option>
- <option>
- <name>IccFloatSemantics</name>
- <state>0</state>
- </option>
- <option>
- <name>CCNoLiteralPool</name>
- <state>0</state>
- </option>
- <option>
- <name>CCOptStrategySlave</name>
- <version>0</version>
- <state>0</state>
- </option>
- <option>
- <name>CCGuardCalls</name>
- <state>1</state>
- </option>
- <option>
- <name>CCEncSource</name>
- <state>0</state>
- </option>
- <option>
- <name>CCEncOutput</name>
- <state>0</state>
- </option>
- <option>
- <name>CCEncOutputBom</name>
- <state>1</state>
- </option>
- <option>
- <name>CCEncInput</name>
- <state>0</state>
- </option>
- <option>
- <name>IccExceptions2</name>
- <state>0</state>
- </option>
- <option>
- <name>IccRTTI2</name>
- <state>0</state>
- </option>
- </data>
- </settings>
- <settings>
- <name>AARM</name>
- <archiveVersion>2</archiveVersion>
- <data>
- <version>10</version>
- <wantNonLocal>1</wantNonLocal>
- <debug>0</debug>
- <option>
- <name>AObjPrefix</name>
- <state>1</state>
- </option>
- <option>
- <name>AEndian</name>
- <state>1</state>
- </option>
- <option>
- <name>ACaseSensitivity</name>
- <state>1</state>
- </option>
- <option>
- <name>MacroChars</name>
- <version>0</version>
- <state>0</state>
- </option>
- <option>
- <name>AWarnEnable</name>
- <state>0</state>
- </option>
- <option>
- <name>AWarnWhat</name>
- <state>0</state>
- </option>
- <option>
- <name>AWarnOne</name>
- <state></state>
- </option>
- <option>
- <name>AWarnRange1</name>
- <state></state>
- </option>
- <option>
- <name>AWarnRange2</name>
- <state></state>
- </option>
- <option>
- <name>ADebug</name>
- <state>0</state>
- </option>
- <option>
- <name>AltRegisterNames</name>
- <state>0</state>
- </option>
- <option>
- <name>ADefines</name>
- <state></state>
- </option>
- <option>
- <name>AList</name>
- <state>0</state>
- </option>
- <option>
- <name>AListHeader</name>
- <state>1</state>
- </option>
- <option>
- <name>AListing</name>
- <state>1</state>
- </option>
- <option>
- <name>Includes</name>
- <state>0</state>
- </option>
- <option>
- <name>MacDefs</name>
- <state>0</state>
- </option>
- <option>
- <name>MacExps</name>
- <state>1</state>
- </option>
- <option>
- <name>MacExec</name>
- <state>0</state>
- </option>
- <option>
- <name>OnlyAssed</name>
- <state>0</state>
- </option>
- <option>
- <name>MultiLine</name>
- <state>0</state>
- </option>
- <option>
- <name>PageLengthCheck</name>
- <state>0</state>
- </option>
- <option>
- <name>PageLength</name>
- <state>80</state>
- </option>
- <option>
- <name>TabSpacing</name>
- <state>8</state>
- </option>
- <option>
- <name>AXRef</name>
- <state>0</state>
- </option>
- <option>
- <name>AXRefDefines</name>
- <state>0</state>
- </option>
- <option>
- <name>AXRefInternal</name>
- <state>0</state>
- </option>
- <option>
- <name>AXRefDual</name>
- <state>0</state>
- </option>
- <option>
- <name>AProcessor</name>
- <state>1</state>
- </option>
- <option>
- <name>AFpuProcessor</name>
- <state>1</state>
- </option>
- <option>
- <name>AOutputFile</name>
- <state></state>
- </option>
- <option>
- <name>ALimitErrorsCheck</name>
- <state>0</state>
- </option>
- <option>
- <name>ALimitErrorsEdit</name>
- <state>100</state>
- </option>
- <option>
- <name>AIgnoreStdInclude</name>
- <state>0</state>
- </option>
- <option>
- <name>AUserIncludes</name>
- <state></state>
- </option>
- <option>
- <name>AExtraOptionsCheckV2</name>
- <state>0</state>
- </option>
- <option>
- <name>AExtraOptionsV2</name>
- <state></state>
- </option>
- <option>
- <name>AsmNoLiteralPool</name>
- <state>0</state>
- </option>
- </data>
- </settings>
- <settings>
- <name>OBJCOPY</name>
- <archiveVersion>0</archiveVersion>
- <data>
- <version>1</version>
- <wantNonLocal>1</wantNonLocal>
- <debug>0</debug>
- <option>
- <name>OOCOutputFormat</name>
- <version>3</version>
- <state>0</state>
- </option>
- <option>
- <name>OCOutputOverride</name>
- <state>0</state>
- </option>
- <option>
- <name>OOCOutputFile</name>
- <state></state>
- </option>
- <option>
- <name>OOCCommandLineProducer</name>
- <state>1</state>
- </option>
- <option>
- <name>OOCObjCopyEnable</name>
- <state>0</state>
- </option>
- </data>
- </settings>
- <settings>
- <name>CUSTOM</name>
- <archiveVersion>3</archiveVersion>
- <data>
- <extensions></extensions>
- <cmdline></cmdline>
- <hasPrio>0</hasPrio>
- </data>
- </settings>
- <settings>
- <name>BICOMP</name>
- <archiveVersion>0</archiveVersion>
- <data />
- </settings>
- <settings>
- <name>BUILDACTION</name>
- <archiveVersion>1</archiveVersion>
- <data>
- <prebuild></prebuild>
- <postbuild></postbuild>
- </data>
- </settings>
- <settings>
- <name>ILINK</name>
- <archiveVersion>0</archiveVersion>
- <data>
- <version>20</version>
- <wantNonLocal>1</wantNonLocal>
- <debug>0</debug>
- <option>
- <name>IlinkLibIOConfig</name>
- <state>1</state>
- </option>
- <option>
- <name>XLinkMisraHandler</name>
- <state>0</state>
- </option>
- <option>
- <name>IlinkInputFileSlave</name>
- <state>0</state>
- </option>
- <option>
- <name>IlinkOutputFile</name>
- <state>###Unitialized###</state>
- </option>
- <option>
- <name>IlinkDebugInfoEnable</name>
- <state>1</state>
- </option>
- <option>
- <name>IlinkKeepSymbols</name>
- <state></state>
- </option>
- <option>
- <name>IlinkRawBinaryFile</name>
- <state></state>
- </option>
- <option>
- <name>IlinkRawBinarySymbol</name>
- <state></state>
- </option>
- <option>
- <name>IlinkRawBinarySegment</name>
- <state></state>
- </option>
- <option>
- <name>IlinkRawBinaryAlign</name>
- <state></state>
- </option>
- <option>
- <name>IlinkDefines</name>
- <state></state>
- </option>
- <option>
- <name>IlinkConfigDefines</name>
- <state></state>
- </option>
- <option>
- <name>IlinkMapFile</name>
- <state>0</state>
- </option>
- <option>
- <name>IlinkLogFile</name>
- <state>0</state>
- </option>
- <option>
- <name>IlinkLogInitialization</name>
- <state>0</state>
- </option>
- <option>
- <name>IlinkLogModule</name>
- <state>0</state>
- </option>
- <option>
- <name>IlinkLogSection</name>
- <state>0</state>
- </option>
- <option>
- <name>IlinkLogVeneer</name>
- <state>0</state>
- </option>
- <option>
- <name>IlinkIcfOverride</name>
- <state>0</state>
- </option>
- <option>
- <name>IlinkIcfFile</name>
- <state>lnk0t.icf</state>
- </option>
- <option>
- <name>IlinkIcfFileSlave</name>
- <state></state>
- </option>
- <option>
- <name>IlinkEnableRemarks</name>
- <state>0</state>
- </option>
- <option>
- <name>IlinkSuppressDiags</name>
- <state></state>
- </option>
- <option>
- <name>IlinkTreatAsRem</name>
- <state></state>
- </option>
- <option>
- <name>IlinkTreatAsWarn</name>
- <state></state>
- </option>
- <option>
- <name>IlinkTreatAsErr</name>
- <state></state>
- </option>
- <option>
- <name>IlinkWarningsAreErrors</name>
- <state>0</state>
- </option>
- <option>
- <name>IlinkUseExtraOptions</name>
- <state>0</state>
- </option>
- <option>
- <name>IlinkExtraOptions</name>
- <state></state>
- </option>
- <option>
- <name>IlinkLowLevelInterfaceSlave</name>
- <state>1</state>
- </option>
- <option>
- <name>IlinkAutoLibEnable</name>
- <state>1</state>
- </option>
- <option>
- <name>IlinkAdditionalLibs</name>
- <state></state>
- </option>
- <option>
- <name>IlinkOverrideProgramEntryLabel</name>
- <state>0</state>
- </option>
- <option>
- <name>IlinkProgramEntryLabelSelect</name>
- <state>0</state>
- </option>
- <option>
- <name>IlinkProgramEntryLabel</name>
- <state></state>
- </option>
- <option>
- <name>DoFill</name>
- <state>0</state>
- </option>
- <option>
- <name>FillerByte</name>
- <state>0xFF</state>
- </option>
- <option>
- <name>FillerStart</name>
- <state>0x0</state>
- </option>
- <option>
- <name>FillerEnd</name>
- <state>0x0</state>
- </option>
- <option>
- <name>CrcSize</name>
- <version>0</version>
- <state>1</state>
- </option>
- <option>
- <name>CrcAlign</name>
- <state>1</state>
- </option>
- <option>
- <name>CrcPoly</name>
- <state>0x11021</state>
- </option>
- <option>
- <name>CrcCompl</name>
- <version>0</version>
- <state>0</state>
- </option>
- <option>
- <name>CrcBitOrder</name>
- <version>0</version>
- <state>0</state>
- </option>
- <option>
- <name>CrcInitialValue</name>
- <state>0x0</state>
- </option>
- <option>
- <name>DoCrc</name>
- <state>0</state>
- </option>
- <option>
- <name>IlinkBE8Slave</name>
- <state>1</state>
- </option>
- <option>
- <name>IlinkBufferedTerminalOutput</name>
- <state>1</state>
- </option>
- <option>
- <name>IlinkStdoutInterfaceSlave</name>
- <state>1</state>
- </option>
- <option>
- <name>CrcFullSize</name>
- <state>0</state>
- </option>
- <option>
- <name>IlinkIElfToolPostProcess</name>
- <state>0</state>
- </option>
- <option>
- <name>IlinkLogAutoLibSelect</name>
- <state>0</state>
- </option>
- <option>
- <name>IlinkLogRedirSymbols</name>
- <state>0</state>
- </option>
- <option>
- <name>IlinkLogUnusedFragments</name>
- <state>0</state>
- </option>
- <option>
- <name>IlinkCrcReverseByteOrder</name>
- <state>0</state>
- </option>
- <option>
- <name>IlinkCrcUseAsInput</name>
- <state>1</state>
- </option>
- <option>
- <name>IlinkOptInline</name>
- <state>1</state>
- </option>
- <option>
- <name>IlinkOptExceptionsAllow</name>
- <state>1</state>
- </option>
- <option>
- <name>IlinkOptExceptionsForce</name>
- <state>0</state>
- </option>
- <option>
- <name>IlinkCmsis</name>
- <state>1</state>
- </option>
- <option>
- <name>IlinkOptMergeDuplSections</name>
- <state>0</state>
- </option>
- <option>
- <name>IlinkOptUseVfe</name>
- <state>1</state>
- </option>
- <option>
- <name>IlinkOptForceVfe</name>
- <state>0</state>
- </option>
- <option>
- <name>IlinkStackAnalysisEnable</name>
- <state>0</state>
- </option>
- <option>
- <name>IlinkStackControlFile</name>
- <state></state>
- </option>
- <option>
- <name>IlinkStackCallGraphFile</name>
- <state></state>
- </option>
- <option>
- <name>CrcAlgorithm</name>
- <version>1</version>
- <state>1</state>
- </option>
- <option>
- <name>CrcUnitSize</name>
- <version>0</version>
- <state>0</state>
- </option>
- <option>
- <name>IlinkThreadsSlave</name>
- <state>1</state>
- </option>
- <option>
- <name>IlinkLogCallGraph</name>
- <state>0</state>
- </option>
- <option>
- <name>IlinkIcfFile_AltDefault</name>
- <state></state>
- </option>
- <option>
- <name>IlinkEncInput</name>
- <state>0</state>
- </option>
- <option>
- <name>IlinkEncOutput</name>
- <state>0</state>
- </option>
- <option>
- <name>IlinkEncOutputBom</name>
- <state>1</state>
- </option>
- <option>
- <name>IlinkHeapSelect</name>
- <state>1</state>
- </option>
- <option>
- <name>IlinkLocaleSelect</name>
- <state>1</state>
- </option>
- </data>
- </settings>
- <settings>
- <name>IARCHIVE</name>
- <archiveVersion>0</archiveVersion>
- <data>
- <version>0</version>
- <wantNonLocal>1</wantNonLocal>
- <debug>0</debug>
- <option>
- <name>IarchiveInputs</name>
- <state></state>
- </option>
- <option>
- <name>IarchiveOverride</name>
- <state>0</state>
- </option>
- <option>
- <name>IarchiveOutput</name>
- <state>###Unitialized###</state>
- </option>
- </data>
- </settings>
- <settings>
- <name>BILINK</name>
- <archiveVersion>0</archiveVersion>
- <data />
- </settings>
- </configuration>
-</project>
+<?xml version="1.0" encoding="UTF-8"?> +<project> + <fileVersion>3</fileVersion> + <configuration> + <name>rtthread</name> + <toolchain> + <name>ARM</name> + </toolchain> + <debug>1</debug> + <settings> + <name>General</name> + <archiveVersion>3</archiveVersion> + <data> + <version>29</version> + <wantNonLocal>1</wantNonLocal> + <debug>1</debug> + <option> + <name>ExePath</name> + <state>build\iar\Exe</state> + </option> + <option> + <name>ObjPath</name> + <state>build\iar\Obj</state> + </option> + <option> + <name>ListPath</name> + <state>build\iar\List</state> + </option> + <option> + <name>GEndianMode</name> + <state>0</state> + </option> + <option> + <name>Input description</name> + <state>Automatic choice of formatter, without multibyte support.</state> + </option> + <option> + <name>Output description</name> + <state>Automatic choice of formatter, without multibyte support.</state> + </option> + <option> + <name>GOutputBinary</name> + <state>0</state> + </option> + <option> + <name>OGCoreOrChip</name> + <state>1</state> + </option> + <option> + <name>GRuntimeLibSelect</name> + <version>0</version> + <state>1</state> + </option> + <option> + <name>GRuntimeLibSelectSlave</name> + <version>0</version> + <state>1</state> + </option> + <option> + <name>RTDescription</name> + <state>Use the normal configuration of the C/C++ runtime library. No locale interface, C locale, no file descriptor support, no multibytes in printf and scanf, and no hex floats in strtod.</state> + </option> + <option> + <name>OGProductVersion</name> + <state>6.30.6.53380</state> + </option> + <option> + <name>OGLastSavedByProductVersion</name> + <state>8.11.3.13977</state> + </option> + <option> + <name>GeneralEnableMisra</name> + <state>0</state> + </option> + <option> + <name>GeneralMisraVerbose</name> + <state>0</state> + </option> + <option> + <name>OGChipSelectEditMenu</name> + <state>STM32F407ZG ST STM32F407ZG</state> + </option> + <option> + <name>GenLowLevelInterface</name> + <state>1</state> + </option> + <option> + <name>GEndianModeBE</name> + <state>1</state> + </option> + <option> + <name>OGBufferedTerminalOutput</name> + <state>0</state> + </option> + <option> + <name>GenStdoutInterface</name> + <state>0</state> + </option> + <option> + <name>GeneralMisraRules98</name> + <version>0</version> + <state>1000111110110101101110011100111111101110011011000101110111101101100111111111111100110011111001110111001111111111111111111111111</state> + </option> + <option> + <name>GeneralMisraVer</name> + <state>0</state> + </option> + <option> + <name>GeneralMisraRules04</name> + <version>0</version> + <state>111101110010111111111000110111111111111111111111111110010111101111010101111111111111111111111111101111111011111001111011111011111111111111111</state> + </option> + <option> + <name>RTConfigPath2</name> + <state>$TOOLKIT_DIR$\INC\c\DLib_Config_Normal.h</state> + </option> + <option> + <name>GBECoreSlave</name> + <version>25</version> + <state>39</state> + </option> + <option> + <name>OGUseCmsis</name> + <state>0</state> + </option> + <option> + <name>OGUseCmsisDspLib</name> + <state>0</state> + </option> + <option> + <name>GRuntimeLibThreads</name> + <state>0</state> + </option> + <option> + <name>CoreVariant</name> + <version>25</version> + <state>39</state> + </option> + <option> + <name>GFPUDeviceSlave</name> + <state>STM32F407ZG ST STM32F407ZG</state> + </option> + <option> + <name>FPU2</name> + <version>0</version> + <state>4</state> + </option> + <option> + <name>NrRegs</name> + <version>0</version> + <state>1</state> + </option> + <option> + <name>NEON</name> + <state>0</state> + </option> + <option> + <name>GFPUCoreSlave2</name> + <version>25</version> + <state>39</state> + </option> + <option> + <name>OGCMSISPackSelectDevice</name> + </option> + <option> + <name>OgLibHeap</name> + <state>0</state> + </option> + <option> + <name>OGLibAdditionalLocale</name> + <state>0</state> + </option> + <option> + <name>OGPrintfVariant</name> + <version>0</version> + <state>0</state> + </option> + <option> + <name>OGPrintfMultibyteSupport</name> + <state>0</state> + </option> + <option> + <name>OGScanfVariant</name> + <version>0</version> + <state>0</state> + </option> + <option> + <name>OGScanfMultibyteSupport</name> + <state>0</state> + </option> + <option> + <name>GenLocaleTags</name> + <state></state> + </option> + <option> + <name>GenLocaleDisplayOnly</name> + <state></state> + </option> + <option> + <name>DSPExtension</name> + <state>1</state> + </option> + </data> + </settings> + <settings> + <name>ICCARM</name> + <archiveVersion>2</archiveVersion> + <data> + <version>34</version> + <wantNonLocal>1</wantNonLocal> + <debug>1</debug> + <option> + <name>CCOptimizationNoSizeConstraints</name> + <state>0</state> + </option> + <option> + <name>CCDefines</name> + <state></state> + </option> + <option> + <name>CCPreprocFile</name> + <state>0</state> + </option> + <option> + <name>CCPreprocComments</name> + <state>0</state> + </option> + <option> + <name>CCPreprocLine</name> + <state>0</state> + </option> + <option> + <name>CCListCFile</name> + <state>0</state> + </option> + <option> + <name>CCListCMnemonics</name> + <state>0</state> + </option> + <option> + <name>CCListCMessages</name> + <state>0</state> + </option> + <option> + <name>CCListAssFile</name> + <state>0</state> + </option> + <option> + <name>CCListAssSource</name> + <state>0</state> + </option> + <option> + <name>CCEnableRemarks</name> + <state>0</state> + </option> + <option> + <name>CCDiagSuppress</name> + <state>Pa050</state> + </option> + <option> + <name>CCDiagRemark</name> + <state></state> + </option> + <option> + <name>CCDiagWarning</name> + <state></state> + </option> + <option> + <name>CCDiagError</name> + <state></state> + </option> + <option> + <name>CCObjPrefix</name> + <state>1</state> + </option> + <option> + <name>CCAllowList</name> + <version>1</version> + <state>00000000</state> + </option> + <option> + <name>CCDebugInfo</name> + <state>1</state> + </option> + <option> + <name>IEndianMode</name> + <state>1</state> + </option> + <option> + <name>IProcessor</name> + <state>1</state> + </option> + <option> + <name>IExtraOptionsCheck</name> + <state>0</state> + </option> + <option> + <name>IExtraOptions</name> + <state></state> + </option> + <option> + <name>CCLangConformance</name> + <state>0</state> + </option> + <option> + <name>CCSignedPlainChar</name> + <state>1</state> + </option> + <option> + <name>CCRequirePrototypes</name> + <state>0</state> + </option> + <option> + <name>CCDiagWarnAreErr</name> + <state>0</state> + </option> + <option> + <name>CCCompilerRuntimeInfo</name> + <state>0</state> + </option> + <option> + <name>IFpuProcessor</name> + <state>1</state> + </option> + <option> + <name>OutputFile</name> + <state>$FILE_BNAME$.o</state> + </option> + <option> + <name>CCLibConfigHeader</name> + <state>1</state> + </option> + <option> + <name>PreInclude</name> + <state></state> + </option> + <option> + <name>CompilerMisraOverride</name> + <state>0</state> + </option> + <option> + <name>CCIncludePath2</name> + <state></state> + </option> + <option> + <name>CCStdIncCheck</name> + <state>0</state> + </option> + <option> + <name>CCCodeSection</name> + <state>.text</state> + </option> + <option> + <name>IProcessorMode2</name> + <state>1</state> + </option> + <option> + <name>CCOptLevel</name> + <state>1</state> + </option> + <option> + <name>CCOptStrategy</name> + <version>0</version> + <state>0</state> + </option> + <option> + <name>CCOptLevelSlave</name> + <state>1</state> + </option> + <option> + <name>CompilerMisraRules98</name> + <version>0</version> + <state>1000111110110101101110011100111111101110011011000101110111101101100111111111111100110011111001110111001111111111111111111111111</state> + </option> + <option> + <name>CompilerMisraRules04</name> + <version>0</version> + <state>111101110010111111111000110111111111111111111111111110010111101111010101111111111111111111111111101111111011111001111011111011111111111111111</state> + </option> + <option> + <name>CCPosIndRopi</name> + <state>0</state> + </option> + <option> + <name>CCPosIndRwpi</name> + <state>0</state> + </option> + <option> + <name>CCPosIndNoDynInit</name> + <state>0</state> + </option> + <option> + <name>IccLang</name> + <state>0</state> + </option> + <option> + <name>IccCDialect</name> + <state>1</state> + </option> + <option> + <name>IccAllowVLA</name> + <state>0</state> + </option> + <option> + <name>IccStaticDestr</name> + <state>1</state> + </option> + <option> + <name>IccCppInlineSemantics</name> + <state>0</state> + </option> + <option> + <name>IccCmsis</name> + <state>1</state> + </option> + <option> + <name>IccFloatSemantics</name> + <state>0</state> + </option> + <option> + <name>CCNoLiteralPool</name> + <state>0</state> + </option> + <option> + <name>CCOptStrategySlave</name> + <version>0</version> + <state>0</state> + </option> + <option> + <name>CCGuardCalls</name> + <state>1</state> + </option> + <option> + <name>CCEncSource</name> + <state>0</state> + </option> + <option> + <name>CCEncOutput</name> + <state>0</state> + </option> + <option> + <name>CCEncOutputBom</name> + <state>1</state> + </option> + <option> + <name>CCEncInput</name> + <state>0</state> + </option> + <option> + <name>IccExceptions2</name> + <state>0</state> + </option> + <option> + <name>IccRTTI2</name> + <state>0</state> + </option> + </data> + </settings> + <settings> + <name>AARM</name> + <archiveVersion>2</archiveVersion> + <data> + <version>10</version> + <wantNonLocal>1</wantNonLocal> + <debug>1</debug> + <option> + <name>AObjPrefix</name> + <state>1</state> + </option> + <option> + <name>AEndian</name> + <state>1</state> + </option> + <option> + <name>ACaseSensitivity</name> + <state>1</state> + </option> + <option> + <name>MacroChars</name> + <version>0</version> + <state>0</state> + </option> + <option> + <name>AWarnEnable</name> + <state>0</state> + </option> + <option> + <name>AWarnWhat</name> + <state>0</state> + </option> + <option> + <name>AWarnOne</name> + <state></state> + </option> + <option> + <name>AWarnRange1</name> + <state></state> + </option> + <option> + <name>AWarnRange2</name> + <state></state> + </option> + <option> + <name>ADebug</name> + <state>1</state> + </option> + <option> + <name>AltRegisterNames</name> + <state>0</state> + </option> + <option> + <name>ADefines</name> + <state></state> + </option> + <option> + <name>AList</name> + <state>0</state> + </option> + <option> + <name>AListHeader</name> + <state>1</state> + </option> + <option> + <name>AListing</name> + <state>1</state> + </option> + <option> + <name>Includes</name> + <state>0</state> + </option> + <option> + <name>MacDefs</name> + <state>0</state> + </option> + <option> + <name>MacExps</name> + <state>1</state> + </option> + <option> + <name>MacExec</name> + <state>0</state> + </option> + <option> + <name>OnlyAssed</name> + <state>0</state> + </option> + <option> + <name>MultiLine</name> + <state>0</state> + </option> + <option> + <name>PageLengthCheck</name> + <state>0</state> + </option> + <option> + <name>PageLength</name> + <state>80</state> + </option> + <option> + <name>TabSpacing</name> + <state>8</state> + </option> + <option> + <name>AXRef</name> + <state>0</state> + </option> + <option> + <name>AXRefDefines</name> + <state>0</state> + </option> + <option> + <name>AXRefInternal</name> + <state>0</state> + </option> + <option> + <name>AXRefDual</name> + <state>0</state> + </option> + <option> + <name>AProcessor</name> + <state>1</state> + </option> + <option> + <name>AFpuProcessor</name> + <state>1</state> + </option> + <option> + <name>AOutputFile</name> + <state>$FILE_BNAME$.o</state> + </option> + <option> + <name>ALimitErrorsCheck</name> + <state>0</state> + </option> + <option> + <name>ALimitErrorsEdit</name> + <state>100</state> + </option> + <option> + <name>AIgnoreStdInclude</name> + <state>0</state> + </option> + <option> + <name>AUserIncludes</name> + <state></state> + </option> + <option> + <name>AExtraOptionsCheckV2</name> + <state>0</state> + </option> + <option> + <name>AExtraOptionsV2</name> + <state></state> + </option> + <option> + <name>AsmNoLiteralPool</name> + <state>0</state> + </option> + </data> + </settings> + <settings> + <name>OBJCOPY</name> + <archiveVersion>0</archiveVersion> + <data> + <version>1</version> + <wantNonLocal>1</wantNonLocal> + <debug>1</debug> + <option> + <name>OOCOutputFormat</name> + <version>3</version> + <state>3</state> + </option> + <option> + <name>OCOutputOverride</name> + <state>1</state> + </option> + <option> + <name>OOCOutputFile</name> + <state>../../../rtthread.bin</state> + </option> + <option> + <name>OOCCommandLineProducer</name> + <state>1</state> + </option> + <option> + <name>OOCObjCopyEnable</name> + <state>1</state> + </option> + </data> + </settings> + <settings> + <name>CUSTOM</name> + <archiveVersion>3</archiveVersion> + <data> + <extensions></extensions> + <cmdline></cmdline> + <hasPrio>0</hasPrio> + </data> + </settings> + <settings> + <name>BICOMP</name> + <archiveVersion>0</archiveVersion> + <data /> + </settings> + <settings> + <name>BUILDACTION</name> + <archiveVersion>1</archiveVersion> + <data> + <prebuild></prebuild> + <postbuild></postbuild> + </data> + </settings> + <settings> + <name>ILINK</name> + <archiveVersion>0</archiveVersion> + <data> + <version>20</version> + <wantNonLocal>1</wantNonLocal> + <debug>1</debug> + <option> + <name>IlinkLibIOConfig</name> + <state>1</state> + </option> + <option> + <name>XLinkMisraHandler</name> + <state>0</state> + </option> + <option> + <name>IlinkInputFileSlave</name> + <state>0</state> + </option> + <option> + <name>IlinkOutputFile</name> + <state>project.out</state> + </option> + <option> + <name>IlinkDebugInfoEnable</name> + <state>1</state> + </option> + <option> + <name>IlinkKeepSymbols</name> + <state></state> + </option> + <option> + <name>IlinkRawBinaryFile</name> + <state></state> + </option> + <option> + <name>IlinkRawBinarySymbol</name> + <state></state> + </option> + <option> + <name>IlinkRawBinarySegment</name> + <state></state> + </option> + <option> + <name>IlinkRawBinaryAlign</name> + <state></state> + </option> + <option> + <name>IlinkDefines</name> + <state></state> + </option> + <option> + <name>IlinkConfigDefines</name> + <state></state> + </option> + <option> + <name>IlinkMapFile</name> + <state>0</state> + </option> + <option> + <name>IlinkLogFile</name> + <state>0</state> + </option> + <option> + <name>IlinkLogInitialization</name> + <state>0</state> + </option> + <option> + <name>IlinkLogModule</name> + <state>0</state> + </option> + <option> + <name>IlinkLogSection</name> + <state>0</state> + </option> + <option> + <name>IlinkLogVeneer</name> + <state>0</state> + </option> + <option> + <name>IlinkIcfOverride</name> + <state>1</state> + </option> + <option> + <name>IlinkIcfFile</name> + <state>$PROJ_DIR$\drivers\linker_scripts\link.icf</state> + </option> + <option> + <name>IlinkIcfFileSlave</name> + <state></state> + </option> + <option> + <name>IlinkEnableRemarks</name> + <state>0</state> + </option> + <option> + <name>IlinkSuppressDiags</name> + <state></state> + </option> + <option> + <name>IlinkTreatAsRem</name> + <state></state> + </option> + <option> + <name>IlinkTreatAsWarn</name> + <state></state> + </option> + <option> + <name>IlinkTreatAsErr</name> + <state></state> + </option> + <option> + <name>IlinkWarningsAreErrors</name> + <state>0</state> + </option> + <option> + <name>IlinkUseExtraOptions</name> + <state>0</state> + </option> + <option> + <name>IlinkExtraOptions</name> + <state></state> + </option> + <option> + <name>IlinkLowLevelInterfaceSlave</name> + <state>1</state> + </option> + <option> + <name>IlinkAutoLibEnable</name> + <state>1</state> + </option> + <option> + <name>IlinkAdditionalLibs</name> + <state></state> + </option> + <option> + <name>IlinkOverrideProgramEntryLabel</name> + <state>0</state> + </option> + <option> + <name>IlinkProgramEntryLabelSelect</name> + <state>0</state> + </option> + <option> + <name>IlinkProgramEntryLabel</name> + <state>__iar_program_start</state> + </option> + <option> + <name>DoFill</name> + <state>0</state> + </option> + <option> + <name>FillerByte</name> + <state>0xFF</state> + </option> + <option> + <name>FillerStart</name> + <state>0x0</state> + </option> + <option> + <name>FillerEnd</name> + <state>0x0</state> + </option> + <option> + <name>CrcSize</name> + <version>0</version> + <state>1</state> + </option> + <option> + <name>CrcAlign</name> + <state>1</state> + </option> + <option> + <name>CrcPoly</name> + <state>0x11021</state> + </option> + <option> + <name>CrcCompl</name> + <version>0</version> + <state>0</state> + </option> + <option> + <name>CrcBitOrder</name> + <version>0</version> + <state>0</state> + </option> + <option> + <name>CrcInitialValue</name> + <state>0x0</state> + </option> + <option> + <name>DoCrc</name> + <state>0</state> + </option> + <option> + <name>IlinkBE8Slave</name> + <state>1</state> + </option> + <option> + <name>IlinkBufferedTerminalOutput</name> + <state>1</state> + </option> + <option> + <name>IlinkStdoutInterfaceSlave</name> + <state>1</state> + </option> + <option> + <name>CrcFullSize</name> + <state>0</state> + </option> + <option> + <name>IlinkIElfToolPostProcess</name> + <state>0</state> + </option> + <option> + <name>IlinkLogAutoLibSelect</name> + <state>0</state> + </option> + <option> + <name>IlinkLogRedirSymbols</name> + <state>0</state> + </option> + <option> + <name>IlinkLogUnusedFragments</name> + <state>0</state> + </option> + <option> + <name>IlinkCrcReverseByteOrder</name> + <state>0</state> + </option> + <option> + <name>IlinkCrcUseAsInput</name> + <state>1</state> + </option> + <option> + <name>IlinkOptInline</name> + <state>0</state> + </option> + <option> + <name>IlinkOptExceptionsAllow</name> + <state>1</state> + </option> + <option> + <name>IlinkOptExceptionsForce</name> + <state>0</state> + </option> + <option> + <name>IlinkCmsis</name> + <state>1</state> + </option> + <option> + <name>IlinkOptMergeDuplSections</name> + <state>0</state> + </option> + <option> + <name>IlinkOptUseVfe</name> + <state>1</state> + </option> + <option> + <name>IlinkOptForceVfe</name> + <state>0</state> + </option> + <option> + <name>IlinkStackAnalysisEnable</name> + <state>0</state> + </option> + <option> + <name>IlinkStackControlFile</name> + <state></state> + </option> + <option> + <name>IlinkStackCallGraphFile</name> + <state></state> + </option> + <option> + <name>CrcAlgorithm</name> + <version>1</version> + <state>1</state> + </option> + <option> + <name>CrcUnitSize</name> + <version>0</version> + <state>0</state> + </option> + <option> + <name>IlinkThreadsSlave</name> + <state>1</state> + </option> + <option> + <name>IlinkLogCallGraph</name> + <state>0</state> + </option> + <option> + <name>IlinkIcfFile_AltDefault</name> + <state></state> + </option> + <option> + <name>IlinkEncInput</name> + <state>0</state> + </option> + <option> + <name>IlinkEncOutput</name> + <state>0</state> + </option> + <option> + <name>IlinkEncOutputBom</name> + <state>1</state> + </option> + <option> + <name>IlinkHeapSelect</name> + <state>1</state> + </option> + <option> + <name>IlinkLocaleSelect</name> + <state>1</state> + </option> + </data> + </settings> + <settings> + <name>IARCHIVE</name> + <archiveVersion>0</archiveVersion> + <data> + <version>0</version> + <wantNonLocal>1</wantNonLocal> + <debug>1</debug> + <option> + <name>IarchiveInputs</name> + <state></state> + </option> + <option> + <name>IarchiveOverride</name> + <state>0</state> + </option> + <option> + <name>IarchiveOutput</name> + <state>###Unitialized###</state> + </option> + </data> + </settings> + <settings> + <name>BILINK</name> + <archiveVersion>0</archiveVersion> + <data /> + </settings> + </configuration> + <configuration> + <name>Release</name> + <toolchain> + <name>ARM</name> + </toolchain> + <debug>0</debug> + <settings> + <name>General</name> + <archiveVersion>3</archiveVersion> + <data> + <version>29</version> + <wantNonLocal>1</wantNonLocal> + <debug>0</debug> + <option> + <name>ExePath</name> + <state>Release\Exe</state> + </option> + <option> + <name>ObjPath</name> + <state>Release\Obj</state> + </option> + <option> + <name>ListPath</name> + <state>Release\List</state> + </option> + <option> + <name>GEndianMode</name> + <state>0</state> + </option> + <option> + <name>Input description</name> + <state></state> + </option> + <option> + <name>Output description</name> + <state></state> + </option> + <option> + <name>GOutputBinary</name> + <state>0</state> + </option> + <option> + <name>OGCoreOrChip</name> + <state>0</state> + </option> + <option> + <name>GRuntimeLibSelect</name> + <version>0</version> + <state>1</state> + </option> + <option> + <name>GRuntimeLibSelectSlave</name> + <version>0</version> + <state>1</state> + </option> + <option> + <name>RTDescription</name> + <state></state> + </option> + <option> + <name>OGProductVersion</name> + <state>6.30.6.53380</state> + </option> + <option> + <name>OGLastSavedByProductVersion</name> + <state>8.11.3.13977</state> + </option> + <option> + <name>GeneralEnableMisra</name> + <state>0</state> + </option> + <option> + <name>GeneralMisraVerbose</name> + <state>0</state> + </option> + <option> + <name>OGChipSelectEditMenu</name> + <state>Default None</state> + </option> + <option> + <name>GenLowLevelInterface</name> + <state>0</state> + </option> + <option> + <name>GEndianModeBE</name> + <state>0</state> + </option> + <option> + <name>OGBufferedTerminalOutput</name> + <state>0</state> + </option> + <option> + <name>GenStdoutInterface</name> + <state>0</state> + </option> + <option> + <name>GeneralMisraRules98</name> + <version>0</version> + <state>1000111110110101101110011100111111101110011011000101110111101101100111111111111100110011111001110111001111111111111111111111111</state> + </option> + <option> + <name>GeneralMisraVer</name> + <state>0</state> + </option> + <option> + <name>GeneralMisraRules04</name> + <version>0</version> + <state>111101110010111111111000110111111111111111111111111110010111101111010101111111111111111111111111101111111011111001111011111011111111111111111</state> + </option> + <option> + <name>RTConfigPath2</name> + <state></state> + </option> + <option> + <name>GBECoreSlave</name> + <version>25</version> + <state>1</state> + </option> + <option> + <name>OGUseCmsis</name> + <state>0</state> + </option> + <option> + <name>OGUseCmsisDspLib</name> + <state>0</state> + </option> + <option> + <name>GRuntimeLibThreads</name> + <state>0</state> + </option> + <option> + <name>CoreVariant</name> + <version>25</version> + <state>0</state> + </option> + <option> + <name>GFPUDeviceSlave</name> + <state>Default None</state> + </option> + <option> + <name>FPU2</name> + <version>0</version> + <state>0</state> + </option> + <option> + <name>NrRegs</name> + <version>0</version> + <state>0</state> + </option> + <option> + <name>NEON</name> + <state>0</state> + </option> + <option> + <name>GFPUCoreSlave2</name> + <version>25</version> + <state>0</state> + </option> + <option> + <name>OGCMSISPackSelectDevice</name> + </option> + <option> + <name>OgLibHeap</name> + <state>0</state> + </option> + <option> + <name>OGLibAdditionalLocale</name> + <state>0</state> + </option> + <option> + <name>OGPrintfVariant</name> + <version>0</version> + <state>0</state> + </option> + <option> + <name>OGPrintfMultibyteSupport</name> + <state>0</state> + </option> + <option> + <name>OGScanfVariant</name> + <version>0</version> + <state>0</state> + </option> + <option> + <name>OGScanfMultibyteSupport</name> + <state>0</state> + </option> + <option> + <name>GenLocaleTags</name> + <state></state> + </option> + <option> + <name>GenLocaleDisplayOnly</name> + <state></state> + </option> + <option> + <name>DSPExtension</name> + <state>0</state> + </option> + </data> + </settings> + <settings> + <name>ICCARM</name> + <archiveVersion>2</archiveVersion> + <data> + <version>34</version> + <wantNonLocal>1</wantNonLocal> + <debug>0</debug> + <option> + <name>CCOptimizationNoSizeConstraints</name> + <state>0</state> + </option> + <option> + <name>CCDefines</name> + </option> + <option> + <name>CCPreprocFile</name> + <state>0</state> + </option> + <option> + <name>CCPreprocComments</name> + <state>0</state> + </option> + <option> + <name>CCPreprocLine</name> + <state>0</state> + </option> + <option> + <name>CCListCFile</name> + <state>0</state> + </option> + <option> + <name>CCListCMnemonics</name> + <state>0</state> + </option> + <option> + <name>CCListCMessages</name> + <state>0</state> + </option> + <option> + <name>CCListAssFile</name> + <state>0</state> + </option> + <option> + <name>CCListAssSource</name> + <state>0</state> + </option> + <option> + <name>CCEnableRemarks</name> + <state>0</state> + </option> + <option> + <name>CCDiagSuppress</name> + <state></state> + </option> + <option> + <name>CCDiagRemark</name> + <state></state> + </option> + <option> + <name>CCDiagWarning</name> + <state></state> + </option> + <option> + <name>CCDiagError</name> + <state></state> + </option> + <option> + <name>CCObjPrefix</name> + <state>1</state> + </option> + <option> + <name>CCAllowList</name> + <version>1</version> + <state>11111110</state> + </option> + <option> + <name>CCDebugInfo</name> + <state>0</state> + </option> + <option> + <name>IEndianMode</name> + <state>1</state> + </option> + <option> + <name>IProcessor</name> + <state>1</state> + </option> + <option> + <name>IExtraOptionsCheck</name> + <state>0</state> + </option> + <option> + <name>IExtraOptions</name> + <state></state> + </option> + <option> + <name>CCLangConformance</name> + <state>0</state> + </option> + <option> + <name>CCSignedPlainChar</name> + <state>1</state> + </option> + <option> + <name>CCRequirePrototypes</name> + <state>0</state> + </option> + <option> + <name>CCDiagWarnAreErr</name> + <state>0</state> + </option> + <option> + <name>CCCompilerRuntimeInfo</name> + <state>0</state> + </option> + <option> + <name>IFpuProcessor</name> + <state>1</state> + </option> + <option> + <name>OutputFile</name> + <state></state> + </option> + <option> + <name>CCLibConfigHeader</name> + <state>1</state> + </option> + <option> + <name>PreInclude</name> + <state></state> + </option> + <option> + <name>CompilerMisraOverride</name> + <state>0</state> + </option> + <option> + <name>CCIncludePath2</name> + <state></state> + </option> + <option> + <name>CCStdIncCheck</name> + <state>0</state> + </option> + <option> + <name>CCCodeSection</name> + <state>.text</state> + </option> + <option> + <name>IProcessorMode2</name> + <state>1</state> + </option> + <option> + <name>CCOptLevel</name> + <state>3</state> + </option> + <option> + <name>CCOptStrategy</name> + <version>0</version> + <state>0</state> + </option> + <option> + <name>CCOptLevelSlave</name> + <state>1</state> + </option> + <option> + <name>CompilerMisraRules98</name> + <version>0</version> + <state>1000111110110101101110011100111111101110011011000101110111101101100111111111111100110011111001110111001111111111111111111111111</state> + </option> + <option> + <name>CompilerMisraRules04</name> + <version>0</version> + <state>111101110010111111111000110111111111111111111111111110010111101111010101111111111111111111111111101111111011111001111011111011111111111111111</state> + </option> + <option> + <name>CCPosIndRopi</name> + <state>0</state> + </option> + <option> + <name>CCPosIndRwpi</name> + <state>0</state> + </option> + <option> + <name>CCPosIndNoDynInit</name> + <state>0</state> + </option> + <option> + <name>IccLang</name> + <state>0</state> + </option> + <option> + <name>IccCDialect</name> + <state>1</state> + </option> + <option> + <name>IccAllowVLA</name> + <state>0</state> + </option> + <option> + <name>IccStaticDestr</name> + <state>1</state> + </option> + <option> + <name>IccCppInlineSemantics</name> + <state>0</state> + </option> + <option> + <name>IccCmsis</name> + <state>1</state> + </option> + <option> + <name>IccFloatSemantics</name> + <state>0</state> + </option> + <option> + <name>CCNoLiteralPool</name> + <state>0</state> + </option> + <option> + <name>CCOptStrategySlave</name> + <version>0</version> + <state>0</state> + </option> + <option> + <name>CCGuardCalls</name> + <state>1</state> + </option> + <option> + <name>CCEncSource</name> + <state>0</state> + </option> + <option> + <name>CCEncOutput</name> + <state>0</state> + </option> + <option> + <name>CCEncOutputBom</name> + <state>1</state> + </option> + <option> + <name>CCEncInput</name> + <state>0</state> + </option> + <option> + <name>IccExceptions2</name> + <state>0</state> + </option> + <option> + <name>IccRTTI2</name> + <state>0</state> + </option> + </data> + </settings> + <settings> + <name>AARM</name> + <archiveVersion>2</archiveVersion> + <data> + <version>10</version> + <wantNonLocal>1</wantNonLocal> + <debug>0</debug> + <option> + <name>AObjPrefix</name> + <state>1</state> + </option> + <option> + <name>AEndian</name> + <state>1</state> + </option> + <option> + <name>ACaseSensitivity</name> + <state>1</state> + </option> + <option> + <name>MacroChars</name> + <version>0</version> + <state>0</state> + </option> + <option> + <name>AWarnEnable</name> + <state>0</state> + </option> + <option> + <name>AWarnWhat</name> + <state>0</state> + </option> + <option> + <name>AWarnOne</name> + <state></state> + </option> + <option> + <name>AWarnRange1</name> + <state></state> + </option> + <option> + <name>AWarnRange2</name> + <state></state> + </option> + <option> + <name>ADebug</name> + <state>0</state> + </option> + <option> + <name>AltRegisterNames</name> + <state>0</state> + </option> + <option> + <name>ADefines</name> + <state></state> + </option> + <option> + <name>AList</name> + <state>0</state> + </option> + <option> + <name>AListHeader</name> + <state>1</state> + </option> + <option> + <name>AListing</name> + <state>1</state> + </option> + <option> + <name>Includes</name> + <state>0</state> + </option> + <option> + <name>MacDefs</name> + <state>0</state> + </option> + <option> + <name>MacExps</name> + <state>1</state> + </option> + <option> + <name>MacExec</name> + <state>0</state> + </option> + <option> + <name>OnlyAssed</name> + <state>0</state> + </option> + <option> + <name>MultiLine</name> + <state>0</state> + </option> + <option> + <name>PageLengthCheck</name> + <state>0</state> + </option> + <option> + <name>PageLength</name> + <state>80</state> + </option> + <option> + <name>TabSpacing</name> + <state>8</state> + </option> + <option> + <name>AXRef</name> + <state>0</state> + </option> + <option> + <name>AXRefDefines</name> + <state>0</state> + </option> + <option> + <name>AXRefInternal</name> + <state>0</state> + </option> + <option> + <name>AXRefDual</name> + <state>0</state> + </option> + <option> + <name>AProcessor</name> + <state>1</state> + </option> + <option> + <name>AFpuProcessor</name> + <state>1</state> + </option> + <option> + <name>AOutputFile</name> + <state></state> + </option> + <option> + <name>ALimitErrorsCheck</name> + <state>0</state> + </option> + <option> + <name>ALimitErrorsEdit</name> + <state>100</state> + </option> + <option> + <name>AIgnoreStdInclude</name> + <state>0</state> + </option> + <option> + <name>AUserIncludes</name> + <state></state> + </option> + <option> + <name>AExtraOptionsCheckV2</name> + <state>0</state> + </option> + <option> + <name>AExtraOptionsV2</name> + <state></state> + </option> + <option> + <name>AsmNoLiteralPool</name> + <state>0</state> + </option> + </data> + </settings> + <settings> + <name>OBJCOPY</name> + <archiveVersion>0</archiveVersion> + <data> + <version>1</version> + <wantNonLocal>1</wantNonLocal> + <debug>0</debug> + <option> + <name>OOCOutputFormat</name> + <version>3</version> + <state>0</state> + </option> + <option> + <name>OCOutputOverride</name> + <state>0</state> + </option> + <option> + <name>OOCOutputFile</name> + <state></state> + </option> + <option> + <name>OOCCommandLineProducer</name> + <state>1</state> + </option> + <option> + <name>OOCObjCopyEnable</name> + <state>0</state> + </option> + </data> + </settings> + <settings> + <name>CUSTOM</name> + <archiveVersion>3</archiveVersion> + <data> + <extensions></extensions> + <cmdline></cmdline> + <hasPrio>0</hasPrio> + </data> + </settings> + <settings> + <name>BICOMP</name> + <archiveVersion>0</archiveVersion> + <data /> + </settings> + <settings> + <name>BUILDACTION</name> + <archiveVersion>1</archiveVersion> + <data> + <prebuild></prebuild> + <postbuild></postbuild> + </data> + </settings> + <settings> + <name>ILINK</name> + <archiveVersion>0</archiveVersion> + <data> + <version>20</version> + <wantNonLocal>1</wantNonLocal> + <debug>0</debug> + <option> + <name>IlinkLibIOConfig</name> + <state>1</state> + </option> + <option> + <name>XLinkMisraHandler</name> + <state>0</state> + </option> + <option> + <name>IlinkInputFileSlave</name> + <state>0</state> + </option> + <option> + <name>IlinkOutputFile</name> + <state>###Unitialized###</state> + </option> + <option> + <name>IlinkDebugInfoEnable</name> + <state>1</state> + </option> + <option> + <name>IlinkKeepSymbols</name> + <state></state> + </option> + <option> + <name>IlinkRawBinaryFile</name> + <state></state> + </option> + <option> + <name>IlinkRawBinarySymbol</name> + <state></state> + </option> + <option> + <name>IlinkRawBinarySegment</name> + <state></state> + </option> + <option> + <name>IlinkRawBinaryAlign</name> + <state></state> + </option> + <option> + <name>IlinkDefines</name> + <state></state> + </option> + <option> + <name>IlinkConfigDefines</name> + <state></state> + </option> + <option> + <name>IlinkMapFile</name> + <state>0</state> + </option> + <option> + <name>IlinkLogFile</name> + <state>0</state> + </option> + <option> + <name>IlinkLogInitialization</name> + <state>0</state> + </option> + <option> + <name>IlinkLogModule</name> + <state>0</state> + </option> + <option> + <name>IlinkLogSection</name> + <state>0</state> + </option> + <option> + <name>IlinkLogVeneer</name> + <state>0</state> + </option> + <option> + <name>IlinkIcfOverride</name> + <state>0</state> + </option> + <option> + <name>IlinkIcfFile</name> + <state>lnk0t.icf</state> + </option> + <option> + <name>IlinkIcfFileSlave</name> + <state></state> + </option> + <option> + <name>IlinkEnableRemarks</name> + <state>0</state> + </option> + <option> + <name>IlinkSuppressDiags</name> + <state></state> + </option> + <option> + <name>IlinkTreatAsRem</name> + <state></state> + </option> + <option> + <name>IlinkTreatAsWarn</name> + <state></state> + </option> + <option> + <name>IlinkTreatAsErr</name> + <state></state> + </option> + <option> + <name>IlinkWarningsAreErrors</name> + <state>0</state> + </option> + <option> + <name>IlinkUseExtraOptions</name> + <state>0</state> + </option> + <option> + <name>IlinkExtraOptions</name> + <state></state> + </option> + <option> + <name>IlinkLowLevelInterfaceSlave</name> + <state>1</state> + </option> + <option> + <name>IlinkAutoLibEnable</name> + <state>1</state> + </option> + <option> + <name>IlinkAdditionalLibs</name> + <state></state> + </option> + <option> + <name>IlinkOverrideProgramEntryLabel</name> + <state>0</state> + </option> + <option> + <name>IlinkProgramEntryLabelSelect</name> + <state>0</state> + </option> + <option> + <name>IlinkProgramEntryLabel</name> + <state></state> + </option> + <option> + <name>DoFill</name> + <state>0</state> + </option> + <option> + <name>FillerByte</name> + <state>0xFF</state> + </option> + <option> + <name>FillerStart</name> + <state>0x0</state> + </option> + <option> + <name>FillerEnd</name> + <state>0x0</state> + </option> + <option> + <name>CrcSize</name> + <version>0</version> + <state>1</state> + </option> + <option> + <name>CrcAlign</name> + <state>1</state> + </option> + <option> + <name>CrcPoly</name> + <state>0x11021</state> + </option> + <option> + <name>CrcCompl</name> + <version>0</version> + <state>0</state> + </option> + <option> + <name>CrcBitOrder</name> + <version>0</version> + <state>0</state> + </option> + <option> + <name>CrcInitialValue</name> + <state>0x0</state> + </option> + <option> + <name>DoCrc</name> + <state>0</state> + </option> + <option> + <name>IlinkBE8Slave</name> + <state>1</state> + </option> + <option> + <name>IlinkBufferedTerminalOutput</name> + <state>1</state> + </option> + <option> + <name>IlinkStdoutInterfaceSlave</name> + <state>1</state> + </option> + <option> + <name>CrcFullSize</name> + <state>0</state> + </option> + <option> + <name>IlinkIElfToolPostProcess</name> + <state>0</state> + </option> + <option> + <name>IlinkLogAutoLibSelect</name> + <state>0</state> + </option> + <option> + <name>IlinkLogRedirSymbols</name> + <state>0</state> + </option> + <option> + <name>IlinkLogUnusedFragments</name> + <state>0</state> + </option> + <option> + <name>IlinkCrcReverseByteOrder</name> + <state>0</state> + </option> + <option> + <name>IlinkCrcUseAsInput</name> + <state>1</state> + </option> + <option> + <name>IlinkOptInline</name> + <state>1</state> + </option> + <option> + <name>IlinkOptExceptionsAllow</name> + <state>1</state> + </option> + <option> + <name>IlinkOptExceptionsForce</name> + <state>0</state> + </option> + <option> + <name>IlinkCmsis</name> + <state>1</state> + </option> + <option> + <name>IlinkOptMergeDuplSections</name> + <state>0</state> + </option> + <option> + <name>IlinkOptUseVfe</name> + <state>1</state> + </option> + <option> + <name>IlinkOptForceVfe</name> + <state>0</state> + </option> + <option> + <name>IlinkStackAnalysisEnable</name> + <state>0</state> + </option> + <option> + <name>IlinkStackControlFile</name> + <state></state> + </option> + <option> + <name>IlinkStackCallGraphFile</name> + <state></state> + </option> + <option> + <name>CrcAlgorithm</name> + <version>1</version> + <state>1</state> + </option> + <option> + <name>CrcUnitSize</name> + <version>0</version> + <state>0</state> + </option> + <option> + <name>IlinkThreadsSlave</name> + <state>1</state> + </option> + <option> + <name>IlinkLogCallGraph</name> + <state>0</state> + </option> + <option> + <name>IlinkIcfFile_AltDefault</name> + <state></state> + </option> + <option> + <name>IlinkEncInput</name> + <state>0</state> + </option> + <option> + <name>IlinkEncOutput</name> + <state>0</state> + </option> + <option> + <name>IlinkEncOutputBom</name> + <state>1</state> + </option> + <option> + <name>IlinkHeapSelect</name> + <state>1</state> + </option> + <option> + <name>IlinkLocaleSelect</name> + <state>1</state> + </option> + </data> + </settings> + <settings> + <name>IARCHIVE</name> + <archiveVersion>0</archiveVersion> + <data> + <version>0</version> + <wantNonLocal>1</wantNonLocal> + <debug>0</debug> + <option> + <name>IarchiveInputs</name> + <state></state> + </option> + <option> + <name>IarchiveOverride</name> + <state>0</state> + </option> + <option> + <name>IarchiveOutput</name> + <state>###Unitialized###</state> + </option> + </data> + </settings> + <settings> + <name>BILINK</name> + <archiveVersion>0</archiveVersion> + <data /> + </settings> + </configuration> +</project> diff --git a/bsp/swm320-lq100/template.eww b/bsp/swm320-lq100/template.eww index bd036bb4c9..c62178f07a 100644 --- a/bsp/swm320-lq100/template.eww +++ b/bsp/swm320-lq100/template.eww @@ -1,10 +1,10 @@ -<?xml version="1.0" encoding="iso-8859-1"?>
-
-<workspace>
- <project>
- <path>$WS_DIR$\template.ewp</path>
- </project>
- <batchBuild/>
-</workspace>
-
-
+<?xml version="1.0" encoding="iso-8859-1"?> + +<workspace> + <project> + <path>$WS_DIR$\template.ewp</path> + </project> + <batchBuild/> +</workspace> + + diff --git a/bsp/swm320-lq100/template.uvopt b/bsp/swm320-lq100/template.uvopt index 0e93bee143..068ac9af69 100644 --- a/bsp/swm320-lq100/template.uvopt +++ b/bsp/swm320-lq100/template.uvopt @@ -21,7 +21,7 @@ </DaveTm> <Target> - <TargetName>rt-thread</TargetName> + <TargetName>rtthread</TargetName> <ToolsetNumber>0x4</ToolsetNumber> <ToolsetName>ARM-ADS</ToolsetName> <TargetOption> @@ -76,28 +76,6 @@ <IsCurrentTarget>1</IsCurrentTarget> </OPTFL> <CpuCode>255</CpuCode> - <Books> - <Book> - <Number>0</Number> - <Title>Datasheet</Title> - <Path>DATASHTS\ST\STM32F4xx\DM00053488.pdf</Path> - </Book> - <Book> - <Number>1</Number> - <Title>Reference Manual</Title> - <Path>DATASHTS\ST\STM32F4xx\DM00031020.pdf</Path> - </Book> - <Book> - <Number>2</Number> - <Title>Technical Reference Manual</Title> - <Path>datashts\arm\cortex_m4\r0p1\DDI0439C_CORTEX_M4_R0P1_TRM.PDF</Path> - </Book> - <Book> - <Number>3</Number> - <Title>Generic User Guide</Title> - <Path>datashts\arm\cortex_m4\r0p1\DUI0553A_CORTEX_M4_DGUG.PDF</Path> - </Book> - </Books> <DebugOpt> <uSim>0</uSim> <uTrg>1</uTrg> @@ -138,12 +116,12 @@ <SetRegEntry> <Number>0</Number> <Key>JL2CM3</Key> - <Name>-U20090928 -O207 -S0 -A0 -C0 -JU1 -JI127.0.0.1 -JP0 -RST0 -TO18 -TC10000000 -TP21 -TDS8001 -TDT0 -TDC1F -TIEFFFFFFFF -TIP8 -TB1 -TFE0 -FO15 -FD20000000 -FC800 -FN1 -FF0STM32F4xx_1024 -FS08000000 -FL0100000</Name> + <Name>-U30000299 -O207 -S0 -A0 -C0 -JU1 -JI127.0.0.1 -JP0 -RST0 -N00("ARM CoreSight SW-DP") -D00(2BA01477) -L00(0) -TO18 -TC10000000 -TP21 -TDS8001 -TDT0 -TDC1F -TIEFFFFFFFF -TIP8 -TB1 -TFE0 -FO15 -FD20000000 -FC800 -FN1 -FF0STM32F4xx_1024 -FS08000000 -FL0100000</Name> </SetRegEntry> <SetRegEntry> <Number>0</Number> <Key>UL2CM3</Key> - <Name>UL2CM3(-O207 -S0 -C0 -FO7 -FN1 -FC800 -FD20000000 -FF0STM32F4xx_1024 -FL0100000 -FS08000000</Name> + <Name>UL2CM3(-O207 -S0 -C0 -FO7 -FD20000000 -FC800 -FN1 -FF0STM32F4xx_1024 -FS08000000 -FL0100000)</Name> </SetRegEntry> </TargetDriverDllRegistry> <Breakpoint/> diff --git a/bsp/swm320-lq100/template.uvoptx b/bsp/swm320-lq100/template.uvoptx index bc15f1d325..920c51f443 100644 --- a/bsp/swm320-lq100/template.uvoptx +++ b/bsp/swm320-lq100/template.uvoptx @@ -22,7 +22,7 @@ </DaveTm> <Target> - <TargetName>rt-thread</TargetName> + <TargetName>rtthread</TargetName> <ToolsetNumber>0x4</ToolsetNumber> <ToolsetName>ARM-ADS</ToolsetName> <TargetOption> @@ -45,7 +45,7 @@ <PageWidth>79</PageWidth> <PageLength>66</PageLength> <TabStop>8</TabStop> - <ListingPath>.\build\</ListingPath> + <ListingPath>.\build\keil\List\</ListingPath> </OPTLEX> <ListingPage> <CreateCListing>1</CreateCListing> @@ -73,7 +73,7 @@ <LExpSel>0</LExpSel> </OPTXL> <OPTFL> - <tvExp>0</tvExp> + <tvExp>1</tvExp> <tvExpOptDlg>0</tvExpOptDlg> <IsCurrentTarget>1</IsCurrentTarget> </OPTFL> @@ -120,12 +120,12 @@ <SetRegEntry> <Number>0</Number> <Key>UL2CM3</Key> - <Name>UL2CM3(-S0 -C0 -P0 -FN1 -FC1000 -FD20000000 -FF0SWM320xE -FL080000 -FS00 -FP0($$Device:SWM320xE$Flash\SWM320xE.FLM)</Name> + <Name>UL2CM3(-S0 -C0 -P0 ) -FN1 -FC1000 -FD20000000 -FF0SWM320xE -FL080000 -FS00 -FP0($$Device:SWM320xE$Flash\SWM320xE.FLM)</Name> </SetRegEntry> <SetRegEntry> <Number>0</Number> <Key>JL2CM3</Key> - <Name>-U30000299 -O78 -S2 -ZTIFSpeedSel5000 -A0 -C0 -JU1 -JI127.0.0.1 -JP0 -RST0 -N00("ARM CoreSight SW-DP") -D00(2BA01477) -L00(0) -TO18 -TC10000000 -TP21 -TDS8002 -TDT0 -TDC1F -TIEFFFFFFFF -TIP8 -TB1 -TFE0 -FO15 -FD20000000 -FC4000 -FN1 -FF0SWM320xE -FS00 -FL080000 -FP0($$Device:SWM320xE$Flash\SWM320xE.FLM)</Name> + <Name>-U30000299 -O78 -S2 -ZTIFSpeedSel5000 -A0 -C0 -JU1 -JI127.0.0.1 -JP0 -RST0 -N00("ARM CoreSight SW-DP") -D00(2BA01477) -L00(4) -TO18 -TC10000000 -TP21 -TDS8001 -TDT0 -TDC1F -TIEFFFFFFFF -TIP8 -TB1 -TFE0 -FO15 -FD20000000 -FC4000 -FN1 -FF0SWM320xE -FS00 -FL080000 -FP0($$Device:SWM320xE$Flash\SWM320xE.FLM)</Name> </SetRegEntry> </TargetDriverDllRegistry> <Breakpoint/> @@ -174,4 +174,12 @@ </TargetOption> </Target> + <Group> + <GroupName>Source Group 1</GroupName> + <tvExp>0</tvExp> + <tvExpOptDlg>0</tvExpOptDlg> + <cbSel>0</cbSel> + <RteFlg>0</RteFlg> + </Group> + </ProjectOpt> diff --git a/bsp/swm320-lq100/template.uvproj b/bsp/swm320-lq100/template.uvproj new file mode 100644 index 0000000000..3312f50fca --- /dev/null +++ b/bsp/swm320-lq100/template.uvproj @@ -0,0 +1,407 @@ +<?xml version="1.0" encoding="UTF-8" standalone="no" ?> +<Project xmlns:xsi="http://www.w3.org/2001/XMLSchema-instance" xsi:noNamespaceSchemaLocation="project_proj.xsd"> + + <SchemaVersion>1.1</SchemaVersion> + + <Header>### uVision Project, (C) Keil Software</Header> + + <Targets> + <Target> + <TargetName>rtthread</TargetName> + <ToolsetNumber>0x4</ToolsetNumber> + <ToolsetName>ARM-ADS</ToolsetName> + <TargetOption> + <TargetCommonOption> + <Device>STM32F407ZG</Device> + <Vendor>STMicroelectronics</Vendor> + <Cpu>IRAM(0x20000000-0x2001FFFF) IRAM2(0x10000000-0x1000FFFF) IROM(0x8000000-0x80FFFFF) CLOCK(25000000) CPUTYPE("Cortex-M4") FPU2</Cpu> + <FlashUtilSpec></FlashUtilSpec> + <StartupFile>"Startup\ST\STM32F4xx\startup_stm32f40_41xxx.s" ("STM32F40/41xxx Startup Code")</StartupFile> + <FlashDriverDll>UL2CM3(-O207 -S0 -C0 -FO7 -FD20000000 -FC800 -FN1 -FF0STM32F4xx_1024 -FS08000000 -FL0100000)</FlashDriverDll> + <DeviceId>6105</DeviceId> + <RegisterFile>stm32f4xx.h</RegisterFile> + <MemoryEnv></MemoryEnv> + <Cmp></Cmp> + <Asm></Asm> + <Linker></Linker> + <OHString></OHString> + <InfinionOptionDll></InfinionOptionDll> + <SLE66CMisc>-DSTM32F40_41xxx</SLE66CMisc> + <SLE66AMisc></SLE66AMisc> + <SLE66LinkerMisc></SLE66LinkerMisc> + <SFDFile>SFD\ST\STM32F4xx\STM32F40x.sfr</SFDFile> + <bCustSvd>0</bCustSvd> + <UseEnv>0</UseEnv> + <BinPath></BinPath> + <IncludePath></IncludePath> + <LibPath></LibPath> + <RegisterFilePath>ST\STM32F4xx\</RegisterFilePath> + <DBRegisterFilePath>ST\STM32F4xx\</DBRegisterFilePath> + <TargetStatus> + <Error>0</Error> + <ExitCodeStop>0</ExitCodeStop> + <ButtonStop>0</ButtonStop> + <NotGenerated>0</NotGenerated> + <InvalidFlash>1</InvalidFlash> + </TargetStatus> + <OutputDirectory>.\build\keil\Obj\</OutputDirectory> + <OutputName>rt-thread</OutputName> + <CreateExecutable>1</CreateExecutable> + <CreateLib>0</CreateLib> + <CreateHexFile>0</CreateHexFile> + <DebugInformation>1</DebugInformation> + <BrowseInformation>0</BrowseInformation> + <ListingPath>.\build\keil\List\</ListingPath> + <HexFormatSelection>1</HexFormatSelection> + <Merge32K>0</Merge32K> + <CreateBatchFile>0</CreateBatchFile> + <BeforeCompile> + <RunUserProg1>0</RunUserProg1> + <RunUserProg2>0</RunUserProg2> + <UserProg1Name></UserProg1Name> + <UserProg2Name></UserProg2Name> + <UserProg1Dos16Mode>0</UserProg1Dos16Mode> + <UserProg2Dos16Mode>0</UserProg2Dos16Mode> + <nStopU1X>0</nStopU1X> + <nStopU2X>0</nStopU2X> + </BeforeCompile> + <BeforeMake> + <RunUserProg1>0</RunUserProg1> + <RunUserProg2>0</RunUserProg2> + <UserProg1Name></UserProg1Name> + <UserProg2Name></UserProg2Name> + <UserProg1Dos16Mode>0</UserProg1Dos16Mode> + <UserProg2Dos16Mode>0</UserProg2Dos16Mode> + </BeforeMake> + <AfterMake> + <RunUserProg1>1</RunUserProg1> + <RunUserProg2>0</RunUserProg2> + <UserProg1Name>fromelf --bin !L --output rtthread.bin</UserProg1Name> + <UserProg2Name></UserProg2Name> + <UserProg1Dos16Mode>0</UserProg1Dos16Mode> + <UserProg2Dos16Mode>0</UserProg2Dos16Mode> + </AfterMake> + <SelectedForBatchBuild>0</SelectedForBatchBuild> + <SVCSIdString></SVCSIdString> + </TargetCommonOption> + <CommonProperty> + <UseCPPCompiler>0</UseCPPCompiler> + <RVCTCodeConst>0</RVCTCodeConst> + <RVCTZI>0</RVCTZI> + <RVCTOtherData>0</RVCTOtherData> + <ModuleSelection>0</ModuleSelection> + <IncludeInBuild>1</IncludeInBuild> + <AlwaysBuild>0</AlwaysBuild> + <GenerateAssemblyFile>0</GenerateAssemblyFile> + <AssembleAssemblyFile>0</AssembleAssemblyFile> + <PublicsOnly>0</PublicsOnly> + <StopOnExitCode>3</StopOnExitCode> + <CustomArgument></CustomArgument> + <IncludeLibraryModules></IncludeLibraryModules> + <ComprImg>1</ComprImg> + </CommonProperty> + <DllOption> + <SimDllName>SARMCM3.DLL</SimDllName> + <SimDllArguments>-MPU -REMAP</SimDllArguments> + <SimDlgDll>DCM.DLL</SimDlgDll> + <SimDlgDllArguments>-pCM4</SimDlgDllArguments> + <TargetDllName>SARMCM3.DLL</TargetDllName> + <TargetDllArguments>-MPU</TargetDllArguments> + <TargetDlgDll>TCM.DLL</TargetDlgDll> + <TargetDlgDllArguments>-pCM4</TargetDlgDllArguments> + </DllOption> + <DebugOption> + <OPTHX> + <HexSelection>1</HexSelection> + <HexRangeLowAddress>0</HexRangeLowAddress> + <HexRangeHighAddress>0</HexRangeHighAddress> + <HexOffset>0</HexOffset> + <Oh166RecLen>16</Oh166RecLen> + </OPTHX> + <Simulator> + <UseSimulator>0</UseSimulator> + <LoadApplicationAtStartup>1</LoadApplicationAtStartup> + <RunToMain>1</RunToMain> + <RestoreBreakpoints>1</RestoreBreakpoints> + <RestoreWatchpoints>1</RestoreWatchpoints> + <RestoreMemoryDisplay>1</RestoreMemoryDisplay> + <RestoreFunctions>1</RestoreFunctions> + <RestoreToolbox>1</RestoreToolbox> + <LimitSpeedToRealTime>0</LimitSpeedToRealTime> + <RestoreSysVw>1</RestoreSysVw> + </Simulator> + <Target> + <UseTarget>1</UseTarget> + <LoadApplicationAtStartup>1</LoadApplicationAtStartup> + <RunToMain>1</RunToMain> + <RestoreBreakpoints>1</RestoreBreakpoints> + <RestoreWatchpoints>1</RestoreWatchpoints> + <RestoreMemoryDisplay>1</RestoreMemoryDisplay> + <RestoreFunctions>0</RestoreFunctions> + <RestoreToolbox>1</RestoreToolbox> + <RestoreTracepoints>0</RestoreTracepoints> + <RestoreSysVw>1</RestoreSysVw> + <UsePdscDebugDescription>0</UsePdscDebugDescription> + </Target> + <RunDebugAfterBuild>0</RunDebugAfterBuild> + <TargetSelection>6</TargetSelection> + <SimDlls> + <CpuDll></CpuDll> + <CpuDllArguments></CpuDllArguments> + <PeripheralDll></PeripheralDll> + <PeripheralDllArguments></PeripheralDllArguments> + <InitializationFile></InitializationFile> + </SimDlls> + <TargetDlls> + <CpuDll></CpuDll> + <CpuDllArguments></CpuDllArguments> + <PeripheralDll></PeripheralDll> + <PeripheralDllArguments></PeripheralDllArguments> + <InitializationFile></InitializationFile> + <Driver>Segger\JL2CM3.dll</Driver> + </TargetDlls> + </DebugOption> + <Utilities> + <Flash1> + <UseTargetDll>1</UseTargetDll> + <UseExternalTool>0</UseExternalTool> + <RunIndependent>0</RunIndependent> + <UpdateFlashBeforeDebugging>1</UpdateFlashBeforeDebugging> + <Capability>1</Capability> + <DriverSelection>4096</DriverSelection> + </Flash1> + <bUseTDR>1</bUseTDR> + <Flash2>BIN\UL2CM3.DLL</Flash2> + <Flash3>"" ()</Flash3> + <Flash4></Flash4> + <pFcarmOut></pFcarmOut> + <pFcarmGrp></pFcarmGrp> + <pFcArmRoot></pFcArmRoot> + <FcArmLst>0</FcArmLst> + </Utilities> + <TargetArmAds> + <ArmAdsMisc> + <GenerateListings>0</GenerateListings> + <asHll>1</asHll> + <asAsm>1</asAsm> + <asMacX>1</asMacX> + <asSyms>1</asSyms> + <asFals>1</asFals> + <asDbgD>1</asDbgD> + <asForm>1</asForm> + <ldLst>0</ldLst> + <ldmm>1</ldmm> + <ldXref>1</ldXref> + <BigEnd>0</BigEnd> + <AdsALst>1</AdsALst> + <AdsACrf>1</AdsACrf> + <AdsANop>0</AdsANop> + <AdsANot>0</AdsANot> + <AdsLLst>1</AdsLLst> + <AdsLmap>1</AdsLmap> + <AdsLcgr>1</AdsLcgr> + <AdsLsym>1</AdsLsym> + <AdsLszi>1</AdsLszi> + <AdsLtoi>1</AdsLtoi> + <AdsLsun>1</AdsLsun> + <AdsLven>1</AdsLven> + <AdsLsxf>1</AdsLsxf> + <RvctClst>0</RvctClst> + <GenPPlst>0</GenPPlst> + <AdsCpuType>"Cortex-M4"</AdsCpuType> + <RvctDeviceName></RvctDeviceName> + <mOS>0</mOS> + <uocRom>0</uocRom> + <uocRam>0</uocRam> + <hadIROM>1</hadIROM> + <hadIRAM>1</hadIRAM> + <hadXRAM>0</hadXRAM> + <uocXRam>0</uocXRam> + <RvdsVP>2</RvdsVP> + <hadIRAM2>1</hadIRAM2> + <hadIROM2>0</hadIROM2> + <StupSel>8</StupSel> + <useUlib>0</useUlib> + <EndSel>0</EndSel> + <uLtcg>0</uLtcg> + <RoSelD>3</RoSelD> + <RwSelD>3</RwSelD> + <CodeSel>0</CodeSel> + <OptFeed>0</OptFeed> + <NoZi1>0</NoZi1> + <NoZi2>0</NoZi2> + <NoZi3>0</NoZi3> + <NoZi4>0</NoZi4> + <NoZi5>0</NoZi5> + <Ro1Chk>0</Ro1Chk> + <Ro2Chk>0</Ro2Chk> + <Ro3Chk>0</Ro3Chk> + <Ir1Chk>1</Ir1Chk> + <Ir2Chk>0</Ir2Chk> + <Ra1Chk>0</Ra1Chk> + <Ra2Chk>0</Ra2Chk> + <Ra3Chk>0</Ra3Chk> + <Im1Chk>0</Im1Chk> + <Im2Chk>1</Im2Chk> + <OnChipMemories> + <Ocm1> + <Type>0</Type> + <StartAddress>0x0</StartAddress> + <Size>0x0</Size> + </Ocm1> + <Ocm2> + <Type>0</Type> + <StartAddress>0x0</StartAddress> + <Size>0x0</Size> + </Ocm2> + <Ocm3> + <Type>0</Type> + <StartAddress>0x0</StartAddress> + <Size>0x0</Size> + </Ocm3> + <Ocm4> + <Type>0</Type> + <StartAddress>0x0</StartAddress> + <Size>0x0</Size> + </Ocm4> + <Ocm5> + <Type>0</Type> + <StartAddress>0x0</StartAddress> + <Size>0x0</Size> + </Ocm5> + <Ocm6> + <Type>0</Type> + <StartAddress>0x0</StartAddress> + <Size>0x0</Size> + </Ocm6> + <IRAM> + <Type>0</Type> + <StartAddress>0x20000000</StartAddress> + <Size>0x20000</Size> + </IRAM> + <IROM> + <Type>1</Type> + <StartAddress>0x8000000</StartAddress> + <Size>0x100000</Size> + </IROM> + <XRAM> + <Type>0</Type> + <StartAddress>0x0</StartAddress> + <Size>0x0</Size> + </XRAM> + <OCR_RVCT1> + <Type>1</Type> + <StartAddress>0x0</StartAddress> + <Size>0x0</Size> + </OCR_RVCT1> + <OCR_RVCT2> + <Type>1</Type> + <StartAddress>0x0</StartAddress> + <Size>0x0</Size> + </OCR_RVCT2> + <OCR_RVCT3> + <Type>1</Type> + <StartAddress>0x0</StartAddress> + <Size>0x0</Size> + </OCR_RVCT3> + <OCR_RVCT4> + <Type>1</Type> + <StartAddress>0x8000000</StartAddress> + <Size>0x100000</Size> + </OCR_RVCT4> + <OCR_RVCT5> + <Type>1</Type> + <StartAddress>0x0</StartAddress> + <Size>0x0</Size> + </OCR_RVCT5> + <OCR_RVCT6> + <Type>0</Type> + <StartAddress>0x0</StartAddress> + <Size>0x0</Size> + </OCR_RVCT6> + <OCR_RVCT7> + <Type>0</Type> + <StartAddress>0x0</StartAddress> + <Size>0x0</Size> + </OCR_RVCT7> + <OCR_RVCT8> + <Type>0</Type> + <StartAddress>0x0</StartAddress> + <Size>0x0</Size> + </OCR_RVCT8> + <OCR_RVCT9> + <Type>0</Type> + <StartAddress>0x20000000</StartAddress> + <Size>0x20000</Size> + </OCR_RVCT9> + <OCR_RVCT10> + <Type>0</Type> + <StartAddress>0x10000000</StartAddress> + <Size>0x10000</Size> + </OCR_RVCT10> + </OnChipMemories> + <RvctStartVector></RvctStartVector> + </ArmAdsMisc> + <Cads> + <interw>1</interw> + <Optim>1</Optim> + <oTime>0</oTime> + <SplitLS>0</SplitLS> + <OneElfS>1</OneElfS> + <Strict>0</Strict> + <EnumInt>0</EnumInt> + <PlainCh>0</PlainCh> + <Ropi>0</Ropi> + <Rwpi>0</Rwpi> + <wLevel>0</wLevel> + <uThumb>0</uThumb> + <uSurpInc>0</uSurpInc> + <uC99>1</uC99> + <useXO>0</useXO> + <VariousControls> + <MiscControls></MiscControls> + <Define></Define> + <Undefine></Undefine> + <IncludePath></IncludePath> + </VariousControls> + </Cads> + <Aads> + <interw>1</interw> + <Ropi>0</Ropi> + <Rwpi>0</Rwpi> + <thumb>0</thumb> + <SplitLS>0</SplitLS> + <SwStkChk>0</SwStkChk> + <NoWarn>0</NoWarn> + <uSurpInc>0</uSurpInc> + <useXO>0</useXO> + <VariousControls> + <MiscControls></MiscControls> + <Define></Define> + <Undefine></Undefine> + <IncludePath></IncludePath> + </VariousControls> + </Aads> + <LDads> + <umfTarg>0</umfTarg> + <Ropi>0</Ropi> + <Rwpi>0</Rwpi> + <noStLib>0</noStLib> + <RepFail>1</RepFail> + <useFile>0</useFile> + <TextAddressRange>0x08000000</TextAddressRange> + <DataAddressRange>0x20000000</DataAddressRange> + <pXoBase></pXoBase> + <ScatterFile>.\drivers\linker_scripts\link.sct</ScatterFile> + <IncludeLibs></IncludeLibs> + <IncludeLibsPath></IncludeLibsPath> + <Misc></Misc> + <LinkerInputFile></LinkerInputFile> + <DisabledWarnings></DisabledWarnings> + </LDads> + </TargetArmAds> + </TargetOption> + </Target> + </Targets> + +</Project> diff --git a/bsp/swm320-lq100/template.uvprojx b/bsp/swm320-lq100/template.uvprojx index a8cdab71fc..68f1afd63e 100644 --- a/bsp/swm320-lq100/template.uvprojx +++ b/bsp/swm320-lq100/template.uvprojx @@ -7,16 +7,16 @@ <Targets> <Target> - <TargetName>rt-thread</TargetName> + <TargetName>rtthread</TargetName> <ToolsetNumber>0x4</ToolsetNumber> <ToolsetName>ARM-ADS</ToolsetName> - <pCCUsed>5060528::V5.06 update 5 (build 528)::ARMCC</pCCUsed> + <pCCUsed>5060750::V5.06 update 6 (build 750)::ARMCC</pCCUsed> <uAC6>0</uAC6> <TargetOption> <TargetCommonOption> <Device>SWM320xE</Device> <Vendor>Synwit</Vendor> - <PackID>Synwit.SWM32_DFP.1.6.2</PackID> + <PackID>Synwit.SWM32_DFP.1.11.2</PackID> <PackURL>http://www.synwit.com/pack</PackURL> <Cpu>IRAM(0x20000000,0x20000) IROM(0x00000000,0x80000) CPUTYPE("Cortex-M4") CLOCK(12000000) ELITTLE</Cpu> <FlashUtilSpec></FlashUtilSpec> @@ -184,6 +184,7 @@ <hadXRAM>0</hadXRAM> <uocXRam>0</uocXRam> <RvdsVP>0</RvdsVP> + <RvdsMve>0</RvdsMve> <hadIRAM2>0</hadIRAM2> <hadIROM2>0</hadIROM2> <StupSel>8</StupSel> @@ -320,15 +321,16 @@ <PlainCh>0</PlainCh> <Ropi>0</Ropi> <Rwpi>0</Rwpi> - <wLevel>0</wLevel> + <wLevel>2</wLevel> <uThumb>0</uThumb> <uSurpInc>0</uSurpInc> <uC99>1</uC99> + <uGnu>0</uGnu> <useXO>0</useXO> - <v6Lang>0</v6Lang> - <v6LangP>0</v6LangP> - <vShortEn>0</vShortEn> - <vShortWch>0</vShortWch> + <v6Lang>1</v6Lang> + <v6LangP>1</v6LangP> + <vShortEn>1</vShortEn> + <vShortWch>1</vShortWch> <v6Lto>0</v6Lto> <v6WtE>0</v6WtE> <v6Rtti>0</v6Rtti> @@ -364,7 +366,7 @@ <noStLib>0</noStLib> <RepFail>1</RepFail> <useFile>0</useFile> - <TextAddressRange>0x00000000</TextAddressRange> + <TextAddressRange>0x08000000</TextAddressRange> <DataAddressRange>0x20000000</DataAddressRange> <pXoBase></pXoBase> <ScatterFile>.\drivers\linker_scripts\link.sct</ScatterFile> @@ -376,6 +378,11 @@ </LDads> </TargetArmAds> </TargetOption> + <Groups> + <Group> + <GroupName>Source Group 1</GroupName> + </Group> + </Groups> </Target> </Targets> |