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-rw-r--r--bsp/hc32/ev_hc32f460_lqfp100_v2/board/Kconfig13
-rw-r--r--bsp/hc32/ev_hc32f460_lqfp100_v2/board/board_config.c31
-rw-r--r--bsp/hc32/ev_hc32f460_lqfp100_v2/board/board_config.h18
-rw-r--r--bsp/hc32/ev_hc32f460_lqfp100_v2/board/config/adc_config.h71
-rw-r--r--bsp/hc32/ev_hc32f460_lqfp100_v2/board/drv_config.h1
-rw-r--r--bsp/hc32/libraries/hc32_drivers/SConscript1
-rw-r--r--bsp/hc32/libraries/hc32_drivers/drv_adc.c46
7 files changed, 178 insertions, 3 deletions
diff --git a/bsp/hc32/ev_hc32f460_lqfp100_v2/board/Kconfig b/bsp/hc32/ev_hc32f460_lqfp100_v2/board/Kconfig
index aaa0b7648a..ccdec61780 100644
--- a/bsp/hc32/ev_hc32f460_lqfp100_v2/board/Kconfig
+++ b/bsp/hc32/ev_hc32f460_lqfp100_v2/board/Kconfig
@@ -88,6 +88,19 @@ menu "On-chip Peripheral Drivers"
bool "using can1"
default n
endif
+
+ menuconfig BSP_USING_ADC
+ bool "Enable ADC"
+ default n
+ select RT_USING_ADC
+ if BSP_USING_ADC
+ config BSP_USING_ADC1
+ bool "using adc1"
+ default n
+ config BSP_USING_ADC2
+ bool "using adc2"
+ default n
+ endif
menuconfig BSP_USING_RTC
bool "Enable RTC"
diff --git a/bsp/hc32/ev_hc32f460_lqfp100_v2/board/board_config.c b/bsp/hc32/ev_hc32f460_lqfp100_v2/board/board_config.c
index 71bedeeed2..b45aef030f 100644
--- a/bsp/hc32/ev_hc32f460_lqfp100_v2/board/board_config.c
+++ b/bsp/hc32/ev_hc32f460_lqfp100_v2/board/board_config.c
@@ -86,3 +86,34 @@ default:
return result;
}
#endif
+
+#if defined(RT_USING_ADC)
+rt_err_t rt_hw_board_adc_init(CM_ADC_TypeDef *ADCx)
+{
+ rt_err_t result = RT_EOK;
+ stc_gpio_init_t stcGpioInit;
+
+ (void)GPIO_StructInit(&stcGpioInit);
+ stcGpioInit.u16PinAttr = PIN_ATTR_ANALOG;
+ switch ((rt_uint32_t)ADCx)
+ {
+#if defined(BSP_USING_ADC1)
+ case (rt_uint32_t)CM_ADC1:
+ (void)GPIO_Init(ADC1_CH10_PORT, ADC1_CH10_PIN, &stcGpioInit);
+ (void)GPIO_Init(ADC1_CH12_PORT, ADC1_CH12_PIN, &stcGpioInit);
+ (void)GPIO_Init(ADC1_CH13_PORT, ADC1_CH13_PIN, &stcGpioInit);
+ break;
+#endif
+#if defined(BSP_USING_ADC2)
+ case (rt_uint32_t)CM_ADC2:
+ (void)GPIO_Init(ADC2_CH7_PORT, ADC2_CH7_PIN, &stcGpioInit);
+ break;
+#endif
+ default:
+ result = -RT_ERROR;
+ break;
+ }
+
+ return result;
+}
+#endif
diff --git a/bsp/hc32/ev_hc32f460_lqfp100_v2/board/board_config.h b/bsp/hc32/ev_hc32f460_lqfp100_v2/board/board_config.h
index 86667c8e31..c6689e7f77 100644
--- a/bsp/hc32/ev_hc32f460_lqfp100_v2/board/board_config.h
+++ b/bsp/hc32/ev_hc32f460_lqfp100_v2/board/board_config.h
@@ -65,4 +65,22 @@
#define CAN_STB_PIN (GPIO_PIN_15)
#endif
+/*********** ADC configure *********/
+#if defined(BSP_USING_ADC1)
+ #define ADC1_CH10_PORT (GPIO_PORT_C)
+ #define ADC1_CH10_PIN (GPIO_PIN_00)
+
+ #define ADC1_CH12_PORT (GPIO_PORT_C)
+ #define ADC1_CH12_PIN (GPIO_PIN_02)
+
+ #define ADC1_CH13_PORT (GPIO_PORT_C)
+ #define ADC1_CH13_PIN (GPIO_PIN_03)
+#endif
+
+#if defined(BSP_USING_ADC2)
+ //ADC2 has 7 channels CH0-CH7. ADC12_IN4-ADC12_IN11 means ADC2 CH0-CH7
+ #define ADC2_CH7_PORT (GPIO_PORT_C)
+ #define ADC2_CH7_PIN (GPIO_PIN_01)
+#endif
+
#endif
diff --git a/bsp/hc32/ev_hc32f460_lqfp100_v2/board/config/adc_config.h b/bsp/hc32/ev_hc32f460_lqfp100_v2/board/config/adc_config.h
new file mode 100644
index 0000000000..25c87f4828
--- /dev/null
+++ b/bsp/hc32/ev_hc32f460_lqfp100_v2/board/config/adc_config.h
@@ -0,0 +1,71 @@
+/*
+ * Copyright (c) 2006-2022, RT-Thread Development Team
+ * Copyright (c) 2022, Xiaohua Semiconductor Co., Ltd.
+ * Copyright (c) 2022, xiaoxiaolisunny
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Change Logs:
+ * Date Author Notes
+ * 2022-06-07 xiaoxiaolisunny first version
+ */
+
+#ifndef __ADC_CONFIG_H__
+#define __ADC_CONFIG_H__
+
+#include <rtthread.h>
+#include "irq_config.h"
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+#ifdef BSP_USING_ADC1
+#ifndef ADC1_INIT_PARAMS
+#define ADC1_INIT_PARAMS \
+ { \
+ .name = "adc1", \
+ .resolution = ADC_RESOLUTION_12BIT, \
+ .data_align = ADC_DATAALIGN_RIGHT, \
+ .eoc_poll_time_max = 100, \
+ .hard_trig_enable = RT_FALSE, \
+ .hard_trig_src = ADC_HARDTRIG_ADTRG_PIN, \
+ .internal_trig0_comtrg0_enable = RT_FALSE, \
+ .internal_trig0_comtrg1_enable = RT_FALSE, \
+ .internal_trig0_sel = EVT_SRC_MAX, \
+ .internal_trig1_comtrg0_enable = RT_FALSE, \
+ .internal_trig1_comtrg1_enable = RT_FALSE, \
+ .internal_trig1_sel = EVT_SRC_MAX, \
+ .continue_conv_mode_enable = RT_FALSE, \
+ .data_reg_auto_clear = RT_TRUE, \
+ }
+#endif /* ADC1_INIT_PARAMS */
+#endif /* BSP_USING_ADC1 */
+
+#ifdef BSP_USING_ADC2
+#ifndef ADC2_INIT_PARAMS
+#define ADC2_INIT_PARAMS \
+ { \
+ .name = "adc2", \
+ .resolution = ADC_RESOLUTION_12BIT, \
+ .data_align = ADC_DATAALIGN_RIGHT, \
+ .eoc_poll_time_max = 100, \
+ .hard_trig_enable = RT_FALSE, \
+ .hard_trig_src = ADC_HARDTRIG_ADTRG_PIN, \
+ .internal_trig0_comtrg0_enable = RT_FALSE, \
+ .internal_trig0_comtrg1_enable = RT_FALSE, \
+ .internal_trig0_sel = EVT_SRC_MAX, \
+ .internal_trig1_comtrg0_enable = RT_FALSE, \
+ .internal_trig1_comtrg1_enable = RT_FALSE, \
+ .internal_trig1_sel = EVT_SRC_MAX, \
+ .continue_conv_mode_enable = RT_FALSE, \
+ .data_reg_auto_clear = RT_TRUE, \
+ }
+#endif /* ADC2_INIT_PARAMS */
+#endif /* BSP_USING_ADC2 */
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* __ADC_CONFIG_H__ */
diff --git a/bsp/hc32/ev_hc32f460_lqfp100_v2/board/drv_config.h b/bsp/hc32/ev_hc32f460_lqfp100_v2/board/drv_config.h
index 7483427a11..aa9760cbcd 100644
--- a/bsp/hc32/ev_hc32f460_lqfp100_v2/board/drv_config.h
+++ b/bsp/hc32/ev_hc32f460_lqfp100_v2/board/drv_config.h
@@ -23,6 +23,7 @@ extern "C" {
#include "uart_config.h"
#include "gpio_config.h"
#include "can_config.h"
+#include "adc_config.h"
#ifdef __cplusplus
}
diff --git a/bsp/hc32/libraries/hc32_drivers/SConscript b/bsp/hc32/libraries/hc32_drivers/SConscript
index 41fc861fcb..ca0bf50bf8 100644
--- a/bsp/hc32/libraries/hc32_drivers/SConscript
+++ b/bsp/hc32/libraries/hc32_drivers/SConscript
@@ -30,7 +30,6 @@ if GetDepend(['RT_USING_ADC']):
if GetDepend(['RT_USING_CAN']):
src += ['drv_can.c']
-
path = [cwd]
group = DefineGroup('Drivers', src, depend = [''], CPPPATH = path)
diff --git a/bsp/hc32/libraries/hc32_drivers/drv_adc.c b/bsp/hc32/libraries/hc32_drivers/drv_adc.c
index 4becd5703b..def29c677c 100644
--- a/bsp/hc32/libraries/hc32_drivers/drv_adc.c
+++ b/bsp/hc32/libraries/hc32_drivers/drv_adc.c
@@ -5,8 +5,9 @@
* SPDX-License-Identifier: Apache-2.0
*
* Change Logs:
- * Date Author Notes
- * 2022-04-28 CDT first version
+ * Date Author Notes
+ * 2022-04-28 CDT first version
+ * 2022-06-08 xiaoxiaolisunny add hc32f460 series
*/
#include <board.h>
@@ -83,6 +84,22 @@ static void _adc_internal_trigger0_set(adc_device *p_adc_dev)
AOS_CommonTriggerCmd(u32TriggerSel, AOS_COMM_TRIG1, (en_functional_state_t)p_adc_dev->init.internal_trig0_comtrg0_enable);
AOS_CommonTriggerCmd(u32TriggerSel, AOS_COMM_TRIG2, (en_functional_state_t)p_adc_dev->init.internal_trig0_comtrg1_enable);
#endif
+
+#if defined(HC32F460)
+ switch ((rt_uint32_t)p_adc_dev->instance)
+ {
+ case (rt_uint32_t)CM_ADC1:
+ u32TriggerSel = AOS_ADC1_0;
+ break;
+ case (rt_uint32_t)CM_ADC2:
+ u32TriggerSel = AOS_ADC2_0;
+ break;
+ default:
+ break;
+ }
+ AOS_CommonTriggerCmd(u32TriggerSel, AOS_COMM_TRIG1, (en_functional_state_t)p_adc_dev->init.internal_trig0_comtrg0_enable);
+ AOS_CommonTriggerCmd(u32TriggerSel, AOS_COMM_TRIG2, (en_functional_state_t)p_adc_dev->init.internal_trig0_comtrg1_enable);
+#endif
AOS_SetTriggerEventSrc(u32TriggerSel, p_adc_dev->init.internal_trig0_sel);
}
@@ -114,6 +131,22 @@ static void _adc_internal_trigger1_set(adc_device *p_adc_dev)
AOS_CommonTriggerCmd(u32TriggerSel, AOS_COMM_TRIG1, (en_functional_state_t)p_adc_dev->init.internal_trig0_comtrg0_enable);
AOS_CommonTriggerCmd(u32TriggerSel, AOS_COMM_TRIG2, (en_functional_state_t)p_adc_dev->init.internal_trig0_comtrg1_enable);
#endif
+
+#if defined(HC32F460)
+ switch ((rt_uint32_t)p_adc_dev->instance)
+ {
+ case (rt_uint32_t)CM_ADC1:
+ u32TriggerSel = AOS_ADC1_1;
+ break;
+ case (rt_uint32_t)CM_ADC2:
+ u32TriggerSel = AOS_ADC2_1;
+ break;
+ default:
+ break;
+ }
+ AOS_CommonTriggerCmd(u32TriggerSel, AOS_COMM_TRIG1, (en_functional_state_t)p_adc_dev->init.internal_trig0_comtrg0_enable);
+ AOS_CommonTriggerCmd(u32TriggerSel, AOS_COMM_TRIG2, (en_functional_state_t)p_adc_dev->init.internal_trig0_comtrg1_enable);
+#endif
AOS_SetTriggerEventSrc(u32TriggerSel, p_adc_dev->init.internal_trig1_sel);
}
@@ -179,6 +212,15 @@ static void _adc_clock_enable(void)
FCG_Fcg3PeriphClockCmd(FCG3_PERIPH_ADC3, ENABLE);
#endif
#endif
+
+#if defined(HC32F460)
+#if defined(BSP_USING_ADC1)
+ FCG_Fcg3PeriphClockCmd(FCG3_PERIPH_ADC1, ENABLE);
+#endif
+#if defined(BSP_USING_ADC2)
+ FCG_Fcg3PeriphClockCmd(FCG3_PERIPH_ADC2, ENABLE);
+#endif
+#endif
}
extern rt_err_t rt_hw_board_adc_init(CM_ADC_TypeDef *ADCx);
generated by cgit v1.3.1 (git 2.54.0) at 2026-10-30 20:08:57 +0000