diff options
86 files changed, 10753 insertions, 15402 deletions
diff --git a/bsp/gd32450z-eval/Libraries/CMSIS/GD/GD32F4xx/Include/gd32f4xx.h b/bsp/gd32450z-eval/Libraries/CMSIS/GD/GD32F4xx/Include/gd32f4xx.h index 722e943b88..a901975bbd 100644 --- a/bsp/gd32450z-eval/Libraries/CMSIS/GD/GD32F4xx/Include/gd32f4xx.h +++ b/bsp/gd32450z-eval/Libraries/CMSIS/GD/GD32F4xx/Include/gd32f4xx.h @@ -1,27 +1,55 @@ /*! - \file gd32f4xx.h - \brief general definitions for GD32F4xx + \file gd32f4xx.h + \brief general definitions for GD32F4xx + + \version 2016-08-15, V1.0.0, firmware for GD32F4xx + \version 2018-12-12, V2.0.0, firmware for GD32F4xx + \version 2020-09-30, V2.1.0, firmware for GD32F4xx */ /* - Copyright (C) 2016 GigaDevice + Copyright (c) 2020, GigaDevice Semiconductor Inc. + + Redistribution and use in source and binary forms, with or without modification, +are permitted provided that the following conditions are met: + + 1. Redistributions of source code must retain the above copyright notice, this + list of conditions and the following disclaimer. + 2. Redistributions in binary form must reproduce the above copyright notice, + this list of conditions and the following disclaimer in the documentation + and/or other materials provided with the distribution. + 3. Neither the name of the copyright holder nor the names of its contributors + may be used to endorse or promote products derived from this software without + specific prior written permission. - 2016-08-15, V1.0.0, firmware update for GD32F4xx + THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED +WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. +IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, +INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT +NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR +PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, +WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY +OF SUCH DAMAGE. */ #ifndef GD32F4XX_H #define GD32F4XX_H -#ifdef cplusplus +#ifdef __cplusplus extern "C" { -#endif +#endif /* define GD32F4xx */ -#if !defined (GD32F4xx) - #define GD32F4xx +#if !defined (GD32F450) && !defined (GD32F405) && !defined (GD32F407) + /* #define GD32F450 */ + /* #define GD32F405 */ + /* #define GD32F407 */ #endif /* define GD32F4xx */ -#if !defined (GD32F4xx) - #error "Please select the target GD32F4xx device used in your application (in gd32f4xx.h file)" + +#if !defined (GD32F450) && !defined (GD32F405) && !defined (GD32F407) + #error "Please select the target GD32F4xx device in gd32f4xx.h file" #endif /* undefine GD32F4xx tip */ /* define value of high speed crystal oscillator (HXTAL) in Hz */ @@ -31,11 +59,11 @@ /* define startup timeout value of high speed crystal oscillator (HXTAL) */ #if !defined (HXTAL_STARTUP_TIMEOUT) -#define HXTAL_STARTUP_TIMEOUT ((uint16_t)0x0800) +#define HXTAL_STARTUP_TIMEOUT ((uint16_t)0xFFFF) #endif /* high speed crystal oscillator startup timeout */ /* define value of internal 16MHz RC oscillator (IRC16M) in Hz */ -#if !defined (IRC16M_VALUE) +#if !defined (IRC16M_VALUE) #define IRC16M_VALUE ((uint32_t)16000000) #endif /* internal 16MHz RC oscillator value */ @@ -45,12 +73,12 @@ #endif /* internal 16MHz RC oscillator startup timeout */ /* define value of internal 32KHz RC oscillator(IRC32K) in Hz */ -#if !defined (IRC32K_VALUE) +#if !defined (IRC32K_VALUE) #define IRC32K_VALUE ((uint32_t)32000) #endif /* internal 32KHz RC oscillator value */ /* define value of low speed crystal oscillator (LXTAL)in Hz */ -#if !defined (LXTAL_VALUE) +#if !defined (LXTAL_VALUE) #define LXTAL_VALUE ((uint32_t)32768) #endif /* low speed crystal oscillator value */ @@ -61,35 +89,35 @@ #define __GD32F4xx_STDPERIPH_VERSION_MAIN (0x03) /*!< [31:24] main version */ #define __GD32F4xx_STDPERIPH_VERSION_SUB1 (0x00) /*!< [23:16] sub1 version */ #define __GD32F4xx_STDPERIPH_VERSION_SUB2 (0x00) /*!< [15:8] sub2 version */ -#define __GD32F4xx_STDPERIPH_VERSION_RC (0x00) /*!< [7:0] release candidate */ +#define __GD32F4xx_STDPERIPH_VERSION_RC (0x00) /*!< [7:0] release candidate */ #define __GD32F4xx_STDPERIPH_VERSION ((__GD32F4xx_STDPERIPH_VERSION_MAIN << 24)\ |(__GD32F4xx_STDPERIPH_VERSION_SUB1 << 16)\ |(__GD32F4xx_STDPERIPH_VERSION_SUB2 << 8)\ |(__GD32F4xx_STDPERIPH_VERSION_RC)) -/* configuration of the Cortex-M4 processor and core peripherals */ -#define __CM4_REV 0x0001 /*!< Core revision r0p1 */ -#define __MPU_PRESENT 1 /*!< GD32F4xx do not provide MPU */ +/* configuration of the cortex-M4 processor and core peripherals */ +#define __CM4_REV 0x0001 /*!< core revision r0p1 */ +#define __MPU_PRESENT 1 /*!< GD32F4xx provide MPU */ #define __NVIC_PRIO_BITS 4 /*!< GD32F4xx uses 4 bits for the priority levels */ -#define __VENDOR_SYSTICKCONFIG 0 /*!< set to 1 if different sysTick config is used */ +#define __Vendor_SysTickConfig 0 /*!< set to 1 if different sysTick config is used */ #define __FPU_PRESENT 1 /*!< FPU present */ /* define interrupt number */ typedef enum IRQn { - /* Cortex-M4 processor exceptions numbers */ + /* cortex-M4 processor exceptions numbers */ NonMaskableInt_IRQn = -14, /*!< 2 non maskable interrupt */ - MemoryManagement_IRQn = -12, /*!< 4 Cortex-M4 memory management interrupt */ - BusFault_IRQn = -11, /*!< 5 Cortex-M4 bus fault interrupt */ - UsageFault_IRQn = -10, /*!< 6 Cortex-M4 usage fault interrupt */ - SVCall_IRQn = -5, /*!< 11 Cortex-M4 SV call interrupt */ - DebugMonitor_IRQn = -4, /*!< 12 Cortex-M4 debug monitor interrupt */ - PendSV_IRQn = -2, /*!< 14 Cortex-M4 pend SV interrupt */ - SysTick_IRQn = -1, /*!< 15 Cortex-M4 system tick interrupt */ + MemoryManagement_IRQn = -12, /*!< 4 cortex-M4 memory management interrupt */ + BusFault_IRQn = -11, /*!< 5 cortex-M4 bus fault interrupt */ + UsageFault_IRQn = -10, /*!< 6 cortex-M4 usage fault interrupt */ + SVCall_IRQn = -5, /*!< 11 cortex-M4 SV call interrupt */ + DebugMonitor_IRQn = -4, /*!< 12 cortex-M4 debug monitor interrupt */ + PendSV_IRQn = -2, /*!< 14 cortex-M4 pend SV interrupt */ + SysTick_IRQn = -1, /*!< 15 cortex-M4 system tick interrupt */ /* interruput numbers */ - WWDGT_IRQn = 0, /*!< window watchDog timer interrupt */ + WWDGT_IRQn = 0, /*!< window watchdog timer interrupt */ LVD_IRQn = 1, /*!< LVD through EXTI line detect interrupt */ - TAMPER_STAMP_IRQn = 2, /*!< Tamper and TimeStamp through EXTI Line detect */ - RTC_WKUP_IRQn = 3, /*!< RTC Wakeup through EXTI line interrupt */ + TAMPER_STAMP_IRQn = 2, /*!< tamper and timestamp through EXTI line detect */ + RTC_WKUP_IRQn = 3, /*!< RTC wakeup through EXTI line interrupt */ FMC_IRQn = 4, /*!< FMC interrupt */ RCU_CTC_IRQn = 5, /*!< RCU and CTC interrupt */ EXTI0_IRQn = 6, /*!< EXTI line 0 interrupts */ @@ -97,23 +125,23 @@ typedef enum IRQn EXTI2_IRQn = 8, /*!< EXTI line 2 interrupts */ EXTI3_IRQn = 9, /*!< EXTI line 3 interrupts */ EXTI4_IRQn = 10, /*!< EXTI line 4 interrupts */ - DMA0_Channel0_IRQn = 11, /*!< DMA0 Channel0 Interrupt */ - DMA0_Channel1_IRQn = 12, /*!< DMA0 Channel1 Interrupt */ - DMA0_Channel2_IRQn = 13, /*!< DMA0 Channel2 Interrupt */ - DMA0_Channel3_IRQn = 14, /*!< DMA0 Channel3 Interrupt */ - DMA0_Channel4_IRQn = 15, /*!< DMA0 Channel4 Interrupt */ - DMA0_Channel5_IRQn = 16, /*!< DMA0 Channel5 Interrupt */ - DMA0_Channel6_IRQn = 17, /*!< DMA0 Channel6 Interrupt */ + DMA0_Channel0_IRQn = 11, /*!< DMA0 channel0 Interrupt */ + DMA0_Channel1_IRQn = 12, /*!< DMA0 channel1 Interrupt */ + DMA0_Channel2_IRQn = 13, /*!< DMA0 channel2 interrupt */ + DMA0_Channel3_IRQn = 14, /*!< DMA0 channel3 interrupt */ + DMA0_Channel4_IRQn = 15, /*!< DMA0 channel4 interrupt */ + DMA0_Channel5_IRQn = 16, /*!< DMA0 channel5 interrupt */ + DMA0_Channel6_IRQn = 17, /*!< DMA0 channel6 interrupt */ ADC_IRQn = 18, /*!< ADC interrupt */ - CAN0_TX_IRQn = 19, /*!< CAN0 TX interrupts */ - CAN0_RX0_IRQn = 20, /*!< CAN0 RX0 interrupts */ - CAN0_RX1_IRQn = 21, /*!< CAN0 RX1 interrupts */ - CAN0_EWMC_IRQn = 22, /*!< CAN0 EWMC interrupts */ + CAN0_TX_IRQn = 19, /*!< CAN0 TX interrupt */ + CAN0_RX0_IRQn = 20, /*!< CAN0 RX0 interrupt */ + CAN0_RX1_IRQn = 21, /*!< CAN0 RX1 interrupt */ + CAN0_EWMC_IRQn = 22, /*!< CAN0 EWMC interrupt */ EXTI5_9_IRQn = 23, /*!< EXTI[9:5] interrupts */ - TIMER0_BRK_TIMER8_IRQn = 24, /*!< TIMER0 Break and TIMER8 interrupts */ - TIMER0_UP_TIMER9_IRQn = 25, /*!< TIMER0 Update and TIMER9 interrupts */ - TIMER0_TRG_CMT_TIMER10_IRQn = 26, /*!< TIMER0 Trigger and Commutation and TIMER10 interrupts */ - TIMER0_CC_IRQn = 27, /*!< TIMER0 Capture Compare interrupts */ + TIMER0_BRK_TIMER8_IRQn = 24, /*!< TIMER0 break and TIMER8 interrupts */ + TIMER0_UP_TIMER9_IRQn = 25, /*!< TIMER0 update and TIMER9 interrupts */ + TIMER0_TRG_CMT_TIMER10_IRQn = 26, /*!< TIMER0 trigger and commutation and TIMER10 interrupts */ + TIMER0_Channel_IRQn = 27, /*!< TIMER0 channel capture compare interrupt */ TIMER1_IRQn = 28, /*!< TIMER1 interrupt */ TIMER2_IRQn = 29, /*!< TIMER2 interrupt */ TIMER3_IRQn = 30, /*!< TIMER3 interrupts */ @@ -127,54 +155,127 @@ typedef enum IRQn USART1_IRQn = 38, /*!< USART1 interrupt */ USART2_IRQn = 39, /*!< USART2 interrupt */ EXTI10_15_IRQn = 40, /*!< EXTI[15:10] interrupts */ - RTC_Alarm_IRQn = 41, /*!< RTC Alarm interrupt */ - USBFS_WKUP_IRQn = 42, /*!< USBFS Wakeup interrupt */ - TIMER7_BRK_TIMER11_IRQn = 43, /*!< TIMER7 Break and TIMER11 interrupts */ - TIMER7_UP_TIMER12_IRQn = 44, /*!< TIMER7 Update and TIMER12 interrupts */ - TIMER7_TRG_CMT_TIMER13_IRQn = 45, /*!< TIMER7 Trigger and Commutation and TIMER13 interrupts */ - TIMER7_CC_IRQn = 46, /*!< TIMER7 Capture Compare interrupts */ - DMA0_Channel7_IRQn = 47, /*!< DMA0 Channel7 Interrupt */ - EXMC_IRQn = 48, /*!< EXMC Interrupt */ - SDIO_IRQn = 49, /*!< SDIO Interrupt */ - TIMER4_IRQn = 50, /*!< TIMER4 Interrupt */ - SPI2_IRQn = 51, /*!< SPI2 Interrupt */ - UART3_IRQn = 52, /*!< UART3 Interrupt */ - UART4_IRQn = 53, /*!< UART4 Interrupt */ - TIMER5_DAC_IRQn = 54, /*!< TIMER5 and DAC0 DAC1 Underrun error Interrupt */ - TIMER6_IRQn = 55, /*!< TIMER6 Interrupt */ - DMA1_Channel0_IRQn = 56, /*!< DMA1 Channel0 Interrupt */ - DMA1_Channel1_IRQn = 57, /*!< DMA1 Channel1 Interrupt */ - DMA1_Channel2_IRQn = 58, /*!< DMA1 Channel2 Interrupt */ - DMA1_Channel3_IRQn = 59, /*!< DMA1 Channel3 Interrupt */ - DMA1_Channel4_IRQn = 60, /*!< DMA1 Channel4 Interrupt */ - ENET_IRQn = 61, /*!< Ethernet Interrupt */ - ENET_WKUP_IRQn = 62, /*!< Ethernet Wakeup through EXTI Line Interrupt */ - CAN1_TX_IRQn = 63, /*!< CAN1 TX Interrupt */ - CAN1_RX0_IRQn = 64, /*!< CAN1 RX0 Interrupt */ - CAN1_RX1_IRQn = 65, /*!< CAN1 RX1 Interrupt */ - CAN1_EWMC_IRQn = 66, /*!< CAN1 EWMC Interrupt */ - USBFS_IRQn = 67, /*!< USBFS Interrupt */ - DMA1_Channel5_IRQn = 68, /*!< DMA1 Channel5 Interrupt */ - DMA1_Channel6_IRQn = 69, /*!< DMA1 Channel6 Interrupt */ - DMA1_Channel7_IRQn = 70, /*!< DMA1 Channel7 Interrupt */ - USART5_IRQn = 71, /*!< USART5 Interrupt */ - I2C2_EV_IRQn = 72, /*!< I2C2 Event Interrupt */ - I2C2_ER_IRQn = 73, /*!< I2C2 Error Interrupt */ - USBHS_EP1_Out_IRQn = 74, /*!< USBHS Endpoint 1 Out Interrupt */ - USBHS_EP1_In_IRQn = 75, /*!< USBHS Endpoint 1 in Interrupt */ - USBHS_WKUP_IRQn = 76, /*!< USBHS Wakeup through EXTI Line Interrupt */ - USBHS_IRQn = 77, /*!< USBHS Interrupt */ - DCI_IRQn = 78, /*!< DCI Interrupt */ - TRNG_IRQn = 80, /*!< TRNG Interrupt */ - FPU_IRQn = 81, /*!< FPU Interrupt */ - UART6_IRQn = 82, /*!< UART6 Interrupt */ - UART7_IRQn = 83, /*!< UART7 Interrupt */ - SPI3_IRQn = 84, /*!< SPI3 Interrupt */ - SPI4_IRQn = 85, /*!< SPI4 Interrupt */ - SPI5_IRQn = 86, /*!< SPI5 Interrupt */ - TLI_IRQn = 88, /*!< TLI Interrupt */ - TLI_ER_IRQn = 89, /*!< TLI Error Interrupt */ - IPA_IRQn = 90, /*!< IPA Interrupt */ + RTC_Alarm_IRQn = 41, /*!< RTC alarm interrupt */ + USBFS_WKUP_IRQn = 42, /*!< USBFS wakeup interrupt */ + TIMER7_BRK_TIMER11_IRQn = 43, /*!< TIMER7 break and TIMER11 interrupts */ + TIMER7_UP_TIMER12_IRQn = 44, /*!< TIMER7 update and TIMER12 interrupts */ + TIMER7_TRG_CMT_TIMER13_IRQn = 45, /*!< TIMER7 trigger and commutation and TIMER13 interrupts */ + TIMER7_Channel_IRQn = 46, /*!< TIMER7 channel capture compare interrupt */ + DMA0_Channel7_IRQn = 47, /*!< DMA0 channel7 interrupt */ + +#if defined (GD32F450) + EXMC_IRQn = 48, /*!< EXMC interrupt */ + SDIO_IRQn = 49, /*!< SDIO interrupt */ + TIMER4_IRQn = 50, /*!< TIMER4 interrupt */ + SPI2_IRQn = 51, /*!< SPI2 interrupt */ + UART3_IRQn = 52, /*!< UART3 interrupt */ + UART4_IRQn = 53, /*!< UART4 interrupt */ + TIMER5_DAC_IRQn = 54, /*!< TIMER5 and DAC0 DAC1 underrun error interrupts */ + TIMER6_IRQn = 55, /*!< TIMER6 interrupt */ + DMA1_Channel0_IRQn = 56, /*!< DMA1 channel0 interrupt */ + DMA1_Channel1_IRQn = 57, /*!< DMA1 channel1 interrupt */ + DMA1_Channel2_IRQn = 58, /*!< DMA1 channel2 interrupt */ + DMA1_Channel3_IRQn = 59, /*!< DMA1 channel3 interrupt */ + DMA1_Channel4_IRQn = 60, /*!< DMA1 channel4 interrupt */ + ENET_IRQn = 61, /*!< ENET interrupt */ + ENET_WKUP_IRQn = 62, /*!< ENET wakeup through EXTI line interrupt */ + CAN1_TX_IRQn = 63, /*!< CAN1 TX interrupt */ + CAN1_RX0_IRQn = 64, /*!< CAN1 RX0 interrupt */ + CAN1_RX1_IRQn = 65, /*!< CAN1 RX1 interrupt */ + CAN1_EWMC_IRQn = 66, /*!< CAN1 EWMC interrupt */ + USBFS_IRQn = 67, /*!< USBFS interrupt */ + DMA1_Channel5_IRQn = 68, /*!< DMA1 channel5 interrupt */ + DMA1_Channel6_IRQn = 69, /*!< DMA1 channel6 interrupt */ + DMA1_Channel7_IRQn = 70, /*!< DMA1 channel7 interrupt */ + USART5_IRQn = 71, /*!< USART5 interrupt */ + I2C2_EV_IRQn = 72, /*!< I2C2 event interrupt */ + I2C2_ER_IRQn = 73, /*!< I2C2 error interrupt */ + USBHS_EP1_Out_IRQn = 74, /*!< USBHS endpoint 1 out interrupt */ + USBHS_EP1_In_IRQn = 75, /*!< USBHS endpoint 1 in interrupt */ + USBHS_WKUP_IRQn = 76, /*!< USBHS wakeup through EXTI line interrupt */ + USBHS_IRQn = 77, /*!< USBHS interrupt */ + DCI_IRQn = 78, /*!< DCI interrupt */ + TRNG_IRQn = 80, /*!< TRNG interrupt */ + FPU_IRQn = 81, /*!< FPU interrupt */ + UART6_IRQn = 82, /*!< UART6 interrupt */ + UART7_IRQn = 83, /*!< UART7 interrupt */ + SPI3_IRQn = 84, /*!< SPI3 interrupt */ + SPI4_IRQn = 85, /*!< SPI4 interrupt */ + SPI5_IRQn = 86, /*!< SPI5 interrupt */ + TLI_IRQn = 88, /*!< TLI interrupt */ + TLI_ER_IRQn = 89, /*!< TLI error interrupt */ + IPA_IRQn = 90, /*!< IPA interrupt */ +#endif /* GD32F450 */ + +#if defined (GD32F405) + SDIO_IRQn = 49, /*!< SDIO interrupt */ + TIMER4_IRQn = 50, /*!< TIMER4 interrupt */ + SPI2_IRQn = 51, /*!< SPI2 interrupt */ + UART3_IRQn = 52, /*!< UART3 interrupt */ + UART4_IRQn = 53, /*!< UART4 interrupt */ + TIMER5_DAC_IRQn = 54, /*!< TIMER5 and DAC0 DAC1 underrun error interrupts */ + TIMER6_IRQn = 55, /*!< TIMER6 interrupt */ + DMA1_Channel0_IRQn = 56, /*!< DMA1 channel0 interrupt */ + DMA1_Channel1_IRQn = 57, /*!< DMA1 channel1 interrupt */ + DMA1_Channel2_IRQn = 58, /*!< DMA1 channel2 interrupt */ + DMA1_Channel3_IRQn = 59, /*!< DMA1 channel3 interrupt */ + DMA1_Channel4_IRQn = 60, /*!< DMA1 channel4 interrupt */ + CAN1_TX_IRQn = 63, /*!< CAN1 TX interrupt */ + CAN1_RX0_IRQn = 64, /*!< CAN1 RX0 interrupt */ + CAN1_RX1_IRQn = 65, /*!< CAN1 RX1 interrupt */ + CAN1_EWMC_IRQn = 66, /*!< CAN1 EWMC interrupt */ + USBFS_IRQn = 67, /*!< USBFS interrupt */ + DMA1_Channel5_IRQn = 68, /*!< DMA1 channel5 interrupt */ + DMA1_Channel6_IRQn = 69, /*!< DMA1 channel6 interrupt */ + DMA1_Channel7_IRQn = 70, /*!< DMA1 channel7 interrupt */ + USART5_IRQn = 71, /*!< USART5 interrupt */ + I2C2_EV_IRQn = 72, /*!< I2C2 event interrupt */ + I2C2_ER_IRQn = 73, /*!< I2C2 error interrupt */ + USBHS_EP1_Out_IRQn = 74, /*!< USBHS endpoint 1 Out interrupt */ + USBHS_EP1_In_IRQn = 75, /*!< USBHS endpoint 1 in interrupt */ + USBHS_WKUP_IRQn = 76, /*!< USBHS wakeup through EXTI line interrupt */ + USBHS_IRQn = 77, /*!< USBHS interrupt */ + DCI_IRQn = 78, /*!< DCI interrupt */ + TRNG_IRQn = 80, /*!< TRNG interrupt */ + FPU_IRQn = 81, /*!< FPU interrupt */ +#endif /* GD32F405 */ + +#if defined (GD32F407) + EXMC_IRQn = 48, /*!< EXMC interrupt */ + SDIO_IRQn = 49, /*!< SDIO interrupt */ + TIMER4_IRQn = 50, /*!< TIMER4 interrupt */ + SPI2_IRQn = 51, /*!< SPI2 interrupt */ + UART3_IRQn = 52, /*!< UART3 interrupt */ + UART4_IRQn = 53, /*!< UART4 interrupt */ + TIMER5_DAC_IRQn = 54, /*!< TIMER5 and DAC0 DAC1 underrun error interrupts */ + TIMER6_IRQn = 55, /*!< TIMER6 interrupt */ + DMA1_Channel0_IRQn = 56, /*!< DMA1 channel0 interrupt */ + DMA1_Channel1_IRQn = 57, /*!< DMA1 channel1 interrupt */ + DMA1_Channel2_IRQn = 58, /*!< DMA1 channel2 interrupt */ + DMA1_Channel3_IRQn = 59, /*!< DMA1 channel3 interrupt */ + DMA1_Channel4_IRQn = 60, /*!< DMA1 channel4 interrupt */ + ENET_IRQn = 61, /*!< ENET interrupt */ + ENET_WKUP_IRQn = 62, /*!< ENET wakeup through EXTI line interrupt */ + CAN1_TX_IRQn = 63, /*!< CAN1 TX interrupt */ + CAN1_RX0_IRQn = 64, /*!< CAN1 RX0 interrupt */ + CAN1_RX1_IRQn = 65, /*!< CAN1 RX1 interrupt */ + CAN1_EWMC_IRQn = 66, /*!< CAN1 EWMC interrupt */ + USBFS_IRQn = 67, /*!< USBFS interrupt */ + DMA1_Channel5_IRQn = 68, /*!< DMA1 channel5 interrupt */ + DMA1_Channel6_IRQn = 69, /*!< DMA1 channel6 interrupt */ + DMA1_Channel7_IRQn = 70, /*!< DMA1 channel7 interrupt */ + USART5_IRQn = 71, /*!< USART5 interrupt */ + I2C2_EV_IRQn = 72, /*!< I2C2 event interrupt */ + I2C2_ER_IRQn = 73, /*!< I2C2 error interrupt */ + USBHS_EP1_Out_IRQn = 74, /*!< USBHS endpoint 1 out interrupt */ + USBHS_EP1_In_IRQn = 75, /*!< USBHS endpoint 1 in interrupt */ + USBHS_WKUP_IRQn = 76, /*!< USBHS wakeup through EXTI line interrupt */ + USBHS_IRQn = 77, /*!< USBHS interrupt */ + DCI_IRQn = 78, /*!< DCI interrupt */ + TRNG_IRQn = 80, /*!< TRNG interrupt */ + FPU_IRQn = 81, /*!< FPU interrupt */ +#endif /* GD32F407 */ + } IRQn_Type; /* includes */ @@ -193,7 +294,7 @@ typedef enum {ERROR = 0, SUCCESS = !ERROR} ErrStatus; #define REG16(addr) (*(volatile uint16_t *)(uint32_t)(addr)) #define REG8(addr) (*(volatile uint8_t *)(uint32_t)(addr)) #define BIT(x) ((uint32_t)((uint32_t)0x01U<<(x))) -#define BITS(start, end) ((0xFFFFFFFFUL << (start)) & (0xFFFFFFFFUL >> (31U - (uint32_t)(end)))) +#define BITS(start, end) ((0xFFFFFFFFUL << (start)) & (0xFFFFFFFFUL >> (31U - (uint32_t)(end)))) #define GET_BITS(regval, start, end) (((regval) & BITS((start),(end))) >> (start)) /* main flash and SRAM memory map */ @@ -254,7 +355,7 @@ typedef enum {ERROR = 0, SUCCESS = !ERROR} ErrStatus; /* define marco USE_STDPERIPH_DRIVER */ #if !defined USE_STDPERIPH_DRIVER #define USE_STDPERIPH_DRIVER -#endif +#endif #ifdef USE_STDPERIPH_DRIVER #include "gd32f4xx_libopt.h" #endif /* USE_STDPERIPH_DRIVER */ @@ -262,4 +363,4 @@ typedef enum {ERROR = 0, SUCCESS = !ERROR} ErrStatus; #ifdef cplusplus } #endif -#endif +#endif diff --git a/bsp/gd32450z-eval/Libraries/CMSIS/GD/GD32F4xx/Source/system_gd32f4xx.c b/bsp/gd32450z-eval/Libraries/CMSIS/GD/GD32F4xx/Source/system_gd32f4xx.c index 6da45fa40e..2ea97ae3f8 100644 --- a/bsp/gd32450z-eval/Libraries/CMSIS/GD/GD32F4xx/Source/system_gd32f4xx.c +++ b/bsp/gd32450z-eval/Libraries/CMSIS/GD/GD32F4xx/Source/system_gd32f4xx.c @@ -56,6 +56,9 @@ #define SEL_IRC16M 0x00U #define SEL_HXTAL 0x01U #define SEL_PLLP 0x02U +#define RCU_MODIFY {volatile uint32_t i; \ + RCU_CFG0 |= RCU_AHB_CKSYS_DIV2; \ + for(i=0;i<50000;i++);} /* set the system clock frequency and declare the system clock configuration function */ #ifdef __SYSTEM_CLOCK_IRC16M @@ -109,10 +112,12 @@ void SystemInit (void) #if (__FPU_PRESENT == 1) && (__FPU_USED == 1) SCB->CPACR |= ((3UL << 10*2)|(3UL << 11*2)); /* set CP10 and CP11 Full Access */ #endif - /* Reset the RCC clock configuration to the default reset state ------------*/ + /* Reset the RCU clock configuration to the default reset state ------------*/ /* Set IRC16MEN bit */ RCU_CTL |= RCU_CTL_IRC16MEN; + RCU_MODIFY + /* Reset CFG0 register */ RCU_CFG0 = 0x00000000U; @@ -127,12 +132,10 @@ void SystemInit (void) /* Disable all interrupts */ RCU_INT = 0x00000000U; - - /* Configure the System clock source, PLL Multiplier and Divider factors, + + /* Configure the System clock source, PLL Multiplier and Divider factors, AHB/APBx prescalers and Flash settings ----------------------------------*/ system_clock_config(); - - } /*! \brief configure the system clock @@ -164,7 +167,7 @@ static void system_clock_config(void) system_clock_200m_8m_hxtal(); #elif defined (__SYSTEM_CLOCK_200M_PLL_25M_HXTAL) system_clock_200m_25m_hxtal(); -#endif /* __SYSTEM_CLOCK_IRC16M */ +#endif /* __SYSTEM_CLOCK_IRC16M */ } #ifdef __SYSTEM_CLOCK_IRC16M @@ -178,34 +181,33 @@ static void system_clock_16m_irc16m(void) { uint32_t timeout = 0U; uint32_t stab_flag = 0U; - + /* enable IRC16M */ RCU_CTL |= RCU_CTL_IRC16MEN; - + /* wait until IRC16M is stable or the startup time is longer than IRC16M_STARTUP_TIMEOUT */ do{ timeout++; stab_flag = (RCU_CTL & RCU_CTL_IRC16MSTB); - } - while((0U == stab_flag) && (IRC16M_STARTUP_TIMEOUT != timeout)); - + }while((0U == stab_flag) && (IRC16M_STARTUP_TIMEOUT != timeout)); + /* if fail */ if(0U == (RCU_CTL & RCU_CTL_IRC16MSTB)){ - while(1){ - } + while(1){ + } } - + /* AHB = SYSCLK */ RCU_CFG0 |= RCU_AHB_CKSYS_DIV1; /* APB2 = AHB */ RCU_CFG0 |= RCU_APB2_CKAHB_DIV1; /* APB1 = AHB */ RCU_CFG0 |= RCU_APB1_CKAHB_DIV1; - + /* select IRC16M as system clock */ RCU_CFG0 &= ~RCU_CFG0_SCS; RCU_CFG0 |= RCU_CKSYSSRC_IRC16M; - + /* wait until IRC16M is selected as system clock */ while(0 != (RCU_CFG0 & RCU_SCSS_IRC16M)){ } @@ -222,34 +224,33 @@ static void system_clock_hxtal(void) { uint32_t timeout = 0U; uint32_t stab_flag = 0U; - + /* enable HXTAL */ RCU_CTL |= RCU_CTL_HXTALEN; - + /* wait until HXTAL is stable or the startup time is longer than HXTAL_STARTUP_TIMEOUT */ do{ timeout++; stab_flag = (RCU_CTL & RCU_CTL_HXTALSTB); - } - while((0U == stab_flag) && (HXTAL_STARTUP_TIMEOUT != timeout)); - + }while((0U == stab_flag) && (HXTAL_STARTUP_TIMEOUT != timeout)); + /* if fail */ if(0U == (RCU_CTL & RCU_CTL_HXTALSTB)){ - while(1){ - } + while(1){ + } } - + /* AHB = SYSCLK */ RCU_CFG0 |= RCU_AHB_CKSYS_DIV1; /* APB2 = AHB */ RCU_CFG0 |= RCU_APB2_CKAHB_DIV1; /* APB1 = AHB */ RCU_CFG0 |= RCU_APB1_CKAHB_DIV1; - + /* select HXTAL as system clock */ RCU_CFG0 &= ~RCU_CFG0_SCS; RCU_CFG0 |= RCU_CKSYSSRC_HXTAL; - + /* wait until HXTAL is selected as system clock */ while(0 == (RCU_CFG0 & RCU_SCSS_HXTAL)){ } @@ -266,7 +267,7 @@ static void system_clock_120m_irc16m(void) { uint32_t timeout = 0U; uint32_t stab_flag = 0U; - + /* enable IRC16M */ RCU_CTL |= RCU_CTL_IRC16MEN; @@ -274,15 +275,14 @@ static void system_clock_120m_irc16m(void) do{ timeout++; stab_flag = (RCU_CTL & RCU_CTL_IRC16MSTB); - } - while((0U == stab_flag) && (IRC16M_STARTUP_TIMEOUT != timeout)); + }while((0U == stab_flag) && (IRC16M_STARTUP_TIMEOUT != timeout)); /* if fail */ if(0U == (RCU_CTL & RCU_CTL_IRC16MSTB)){ - while(1){ - } + while(1){ + } } - + RCU_APB1EN |= RCU_APB1EN_PMUEN; PMU_CTL |= PMU_CTL_LDOVS; @@ -294,7 +294,7 @@ static void system_clock_120m_irc16m(void) /* APB1 = AHB/4 */ RCU_CFG0 |= RCU_APB1_CKAHB_DIV4; - /* Configure the main PLL, PLL_M = 16, PLL_N = 240, PLL_P = 2, PLL_Q = 5 */ + /* Configure the main PLL, PSC = 16, PLL_N = 240, PLL_P = 2, PLL_Q = 5 */ RCU_PLL = (16U | (240U << 6U) | (((2U >> 1U) - 1U) << 16U) | (RCU_PLLSRC_IRC16M) | (5U << 24U)); @@ -304,19 +304,17 @@ static void system_clock_120m_irc16m(void) /* wait until PLL is stable */ while(0U == (RCU_CTL & RCU_CTL_PLLSTB)){ } - + /* Enable the high-drive to extend the clock frequency to 120 Mhz */ PMU_CTL |= PMU_CTL_HDEN; - while(0U == (PMU_CS & PMU_CS_HDRF)) - { + while(0U == (PMU_CS & PMU_CS_HDRF)){ } - + /* select the high-drive mode */ PMU_CTL |= PMU_CTL_HDS; - while(0U == (PMU_CS & PMU_CS_HDSRF)) - { - } - + while(0U == (PMU_CS & PMU_CS_HDSRF)){ + } + /* select PLL as system clock */ RCU_CFG0 &= ~RCU_CFG0_SCS; RCU_CFG0 |= RCU_CKSYSSRC_PLLP; @@ -337,7 +335,7 @@ static void system_clock_120m_8m_hxtal(void) { uint32_t timeout = 0U; uint32_t stab_flag = 0U; - + /* enable HXTAL */ RCU_CTL |= RCU_CTL_HXTALEN; @@ -345,15 +343,14 @@ static void system_clock_120m_8m_hxtal(void) do{ timeout++; stab_flag = (RCU_CTL & RCU_CTL_HXTALSTB); - } - while((0U == stab_flag) && (HXTAL_STARTUP_TIMEOUT != timeout)); + }while((0U == stab_flag) && (HXTAL_STARTUP_TIMEOUT != timeout)); /* if fail */ if(0U == (RCU_CTL & RCU_CTL_HXTALSTB)){ - while(1){ - } + while(1){ + } } - + RCU_APB1EN |= RCU_APB1EN_PMUEN; PMU_CTL |= PMU_CTL_LDOVS; @@ -365,7 +362,7 @@ static void system_clock_120m_8m_hxtal(void) /* APB1 = AHB/4 */ RCU_CFG0 |= RCU_APB1_CKAHB_DIV4; - /* Configure the main PLL, PLL_M = 8, PLL_N = 240, PLL_P = 2, PLL_Q = 5 */ + /* Configure the main PLL, PSC = 8, PLL_N = 240, PLL_P = 2, PLL_Q = 5 */ RCU_PLL = (8U | (240U << 6U) | (((2U >> 1U) - 1U) << 16U) | (RCU_PLLSRC_HXTAL) | (5U << 24U)); @@ -375,19 +372,17 @@ static void system_clock_120m_8m_hxtal(void) /* wait until PLL is stable */ while(0U == (RCU_CTL & RCU_CTL_PLLSTB)){ } - + /* Enable the high-drive to extend the clock frequency to 120 Mhz */ PMU_CTL |= PMU_CTL_HDEN; - while(0U == (PMU_CS & PMU_CS_HDRF)) - { + while(0U == (PMU_CS & PMU_CS_HDRF)){ } - + /* select the high-drive mode */ PMU_CTL |= PMU_CTL_HDS; - while(0U == (PMU_CS & PMU_CS_HDSRF)) - { - } - + while(0U == (PMU_CS & PMU_CS_HDSRF)){ + } + /* select PLL as system clock */ RCU_CFG0 &= ~RCU_CFG0_SCS; RCU_CFG0 |= RCU_CKSYSSRC_PLLP; @@ -408,7 +403,7 @@ static void system_clock_120m_25m_hxtal(void) { uint32_t timeout = 0U; uint32_t stab_flag = 0U; - + /* enable HXTAL */ RCU_CTL |= RCU_CTL_HXTALEN; @@ -416,15 +411,14 @@ static void system_clock_120m_25m_hxtal(void) do{ timeout++; stab_flag = (RCU_CTL & RCU_CTL_HXTALSTB); - } - while((0U == stab_flag) && (HXTAL_STARTUP_TIMEOUT != timeout)); + }while((0U == stab_flag) && (HXTAL_STARTUP_TIMEOUT != timeout)); /* if fail */ if(0U == (RCU_CTL & RCU_CTL_HXTALSTB)){ - while(1){ - } + while(1){ + } } - + RCU_APB1EN |= RCU_APB1EN_PMUEN; PMU_CTL |= PMU_CTL_LDOVS; @@ -436,7 +430,7 @@ static void system_clock_120m_25m_hxtal(void) /* APB1 = AHB/4 */ RCU_CFG0 |= RCU_APB1_CKAHB_DIV4; - /* Configure the main PLL, PLL_M = 25, PLL_N = 240, PLL_P = 2, PLL_Q = 5 */ + /* Configure the main PLL, PSC = 25, PLL_N = 240, PLL_P = 2, PLL_Q = 5 */ RCU_PLL = (25U | (240U << 6U) | (((2U >> 1U) - 1U) << 16U) | (RCU_PLLSRC_HXTAL) | (5U << 24U)); @@ -446,19 +440,17 @@ static void system_clock_120m_25m_hxtal(void) /* wait until PLL is stable */ while(0U == (RCU_CTL & RCU_CTL_PLLSTB)){ } - + /* Enable the high-drive to extend the clock frequency to 120 Mhz */ PMU_CTL |= PMU_CTL_HDEN; - while(0U == (PMU_CS & PMU_CS_HDRF)) - { + while(0U == (PMU_CS & PMU_CS_HDRF)){ } - + /* select the high-drive mode */ PMU_CTL |= PMU_CTL_HDS; - while(0U == (PMU_CS & PMU_CS_HDSRF)) - { - } - + while(0U == (PMU_CS & PMU_CS_HDSRF)){ + } + /* select PLL as system clock */ RCU_CFG0 &= ~RCU_CFG0_SCS; RCU_CFG0 |= RCU_CKSYSSRC_PLLP; @@ -479,7 +471,7 @@ static void system_clock_168m_irc16m(void) { uint32_t timeout = 0U; uint32_t stab_flag = 0U; - + /* enable IRC16M */ RCU_CTL |= RCU_CTL_IRC16MEN; @@ -487,15 +479,14 @@ static void system_clock_168m_irc16m(void) do{ timeout++; stab_flag = (RCU_CTL & RCU_CTL_IRC16MSTB); - } - while((0U == stab_flag) && (IRC16M_STARTUP_TIMEOUT != timeout)); + }while((0U == stab_flag) && (IRC16M_STARTUP_TIMEOUT != timeout)); /* if fail */ if(0U == (RCU_CTL & RCU_CTL_IRC16MSTB)){ - while(1){ - } + while(1){ + } } - + RCU_APB1EN |= RCU_APB1EN_PMUEN; PMU_CTL |= PMU_CTL_LDOVS; @@ -507,7 +498,7 @@ static void system_clock_168m_irc16m(void) /* APB1 = AHB/4 */ RCU_CFG0 |= RCU_APB1_CKAHB_DIV4; - /* Configure the main PLL, PLL_M = 16, PLL_N = 336, PLL_P = 2, PLL_Q = 7 */ + /* Configure the main PLL, PSC = 16, PLL_N = 336, PLL_P = 2, PLL_Q = 7 */ RCU_PLL = (16U | (336U << 6U) | (((2U >> 1U) - 1U) << 16U) | (RCU_PLLSRC_IRC16M) | (7U << 24U)); @@ -517,19 +508,17 @@ static void system_clock_168m_irc16m(void) /* wait until PLL is stable */ while(0U == (RCU_CTL & RCU_CTL_PLLSTB)){ } - + /* Enable the high-drive to extend the clock frequency to 168 Mhz */ PMU_CTL |= PMU_CTL_HDEN; - while(0U == (PMU_CS & PMU_CS_HDRF)) - { + while(0U == (PMU_CS & PMU_CS_HDRF)){ } - + /* select the high-drive mode */ PMU_CTL |= PMU_CTL_HDS; - while(0U == (PMU_CS & PMU_CS_HDSRF)) - { - } - + while(0U == (PMU_CS & PMU_CS_HDSRF)){ + } + /* select PLL as system clock */ RCU_CFG0 &= ~RCU_CFG0_SCS; RCU_CFG0 |= RCU_CKSYSSRC_PLLP; @@ -549,7 +538,7 @@ static void system_clock_168m_irc16m(void) static void system_clock_168m_8m_hxtal(void) { uint32_t timeout = 0U; - + /* enable HXTAL */ RCU_CTL |= RCU_CTL_HXTALEN; @@ -559,8 +548,8 @@ static void system_clock_168m_8m_hxtal(void) /* if fail */ if(0U == (RCU_CTL & RCU_CTL_HXTALSTB)){ - while(1){ - } + while(1){ + } } RCU_APB1EN |= RCU_APB1EN_PMUEN; @@ -573,7 +562,7 @@ static void system_clock_168m_8m_hxtal(void) /* APB1 = AHB/4 */ RCU_CFG0 |= RCU_APB1_CKAHB_DIV4; - /* Configure the main PLL, PLL_M = 8, PLL_N = 336, PLL_P = 2, PLL_Q = 7 */ + /* Configure the main PLL, PSC = 8, PLL_N = 336, PLL_P = 2, PLL_Q = 7 */ RCU_PLL = (8U | (336 << 6U) | (((2 >> 1U) -1U) << 16U) | (RCU_PLLSRC_HXTAL) | (7 << 24U)); @@ -583,17 +572,15 @@ static void system_clock_168m_8m_hxtal(void) /* wait until PLL is stable */ while(0U == (RCU_CTL & RCU_CTL_PLLSTB)){ } - + /* Enable the high-drive to extend the clock frequency to 168 Mhz */ PMU_CTL |= PMU_CTL_HDEN; - while(0U == (PMU_CS & PMU_CS_HDRF)) - { + while(0U == (PMU_CS & PMU_CS_HDRF)){ } - + /* select the high-drive mode */ PMU_CTL |= PMU_CTL_HDS; - while(0U == (PMU_CS & PMU_CS_HDSRF)) - { + while(0U == (PMU_CS & PMU_CS_HDSRF)){ } /* select PLL as system clock */ @@ -616,7 +603,7 @@ static void system_clock_168m_25m_hxtal(void) { uint32_t timeout = 0U; uint32_t stab_flag = 0U; - + /* enable HXTAL */ RCU_CTL |= RCU_CTL_HXTALEN; @@ -624,15 +611,14 @@ static void system_clock_168m_25m_hxtal(void) do{ timeout++; stab_flag = (RCU_CTL & RCU_CTL_HXTALSTB); - } - while((0U == stab_flag) && (HXTAL_STARTUP_TIMEOUT != timeout)); + }while((0U == stab_flag) && (HXTAL_STARTUP_TIMEOUT != timeout)); /* if fail */ if(0U == (RCU_CTL & RCU_CTL_HXTALSTB)){ - while(1){ - } + while(1){ + } } - + RCU_APB1EN |= RCU_APB1EN_PMUEN; PMU_CTL |= PMU_CTL_LDOVS; @@ -644,7 +630,7 @@ static void system_clock_168m_25m_hxtal(void) /* APB1 = AHB */ RCU_CFG0 |= RCU_APB1_CKAHB_DIV4; - /* Configure the main PLL, PLL_M = 25, PLL_N = 336, PLL_P = 2, PLL_Q = 7 */ + /* Configure the main PLL, PSC = 25, PLL_N = 336, PLL_P = 2, PLL_Q = 7 */ RCU_PLL = (25U | (336U << 6U) | (((2U >> 1U) - 1U) << 16U) | (RCU_PLLSRC_HXTAL) | (7U << 24U)); @@ -654,19 +640,17 @@ static void system_clock_168m_25m_hxtal(void) /* wait until PLL is stable */ while(0U == (RCU_CTL & RCU_CTL_PLLSTB)){ } - + /* Enable the high-drive to extend the clock frequency to 168 Mhz */ PMU_CTL |= PMU_CTL_HDEN; - while(0U == (PMU_CS & PMU_CS_HDRF)) - { + while(0U == (PMU_CS & PMU_CS_HDRF)){ } - + /* select the high-drive mode */ PMU_CTL |= PMU_CTL_HDS; - while(0U == (PMU_CS & PMU_CS_HDSRF)) - { - } - + while(0U == (PMU_CS & PMU_CS_HDSRF)){ + } + /* select PLL as system clock */ RCU_CFG0 &= ~RCU_CFG0_SCS; RCU_CFG0 |= RCU_CKSYSSRC_PLLP; @@ -687,7 +671,7 @@ static void system_clock_200m_irc16m(void) { uint32_t timeout = 0U; uint32_t stab_flag = 0U; - + /* enable IRC16M */ RCU_CTL |= RCU_CTL_IRC16MEN; @@ -695,15 +679,14 @@ static void system_clock_200m_irc16m(void) do{ timeout++; stab_flag = (RCU_CTL & RCU_CTL_IRC16MSTB); - } - while((0U == stab_flag) && (IRC16M_STARTUP_TIMEOUT != timeout)); + }while((0U == stab_flag) && (IRC16M_STARTUP_TIMEOUT != timeout)); /* if fail */ if(0U == (RCU_CTL & RCU_CTL_IRC16MSTB)){ - while(1){ - } + while(1){ + } } - + RCU_APB1EN |= RCU_APB1EN_PMUEN; PMU_CTL |= PMU_CTL_LDOVS; @@ -715,7 +698,7 @@ static void system_clock_200m_irc16m(void) /* APB1 = AHB/4 */ RCU_CFG0 |= RCU_APB1_CKAHB_DIV4; - /* Configure the main PLL, PLL_M = 16, PLL_N = 400, PLL_P = 2, PLL_Q = 9 */ + /* Configure the main PLL, PSC = 16, PLL_N = 400, PLL_P = 2, PLL_Q = 9 */ RCU_PLL = (16U | (400U << 6U) | (((2U >> 1U) - 1U) << 16U) | (RCU_PLLSRC_IRC16M) | (9U << 24U)); @@ -725,19 +708,17 @@ static void system_clock_200m_irc16m(void) /* wait until PLL is stable */ while(0U == (RCU_CTL & RCU_CTL_PLLSTB)){ } - + /* Enable the high-drive to extend the clock frequency to 200 Mhz */ PMU_CTL |= PMU_CTL_HDEN; - while(0U == (PMU_CS & PMU_CS_HDRF)) - { + while(0U == (PMU_CS & PMU_CS_HDRF)){ } - + /* select the high-drive mode */ PMU_CTL |= PMU_CTL_HDS; - while(0U == (PMU_CS & PMU_CS_HDSRF)) - { - } - + while(0U == (PMU_CS & PMU_CS_HDSRF)){ + } + /* select PLL as system clock */ RCU_CFG0 &= ~RCU_CFG0_SCS; RCU_CFG0 |= RCU_CKSYSSRC_PLLP; @@ -758,7 +739,7 @@ static void system_clock_200m_8m_hxtal(void) { uint32_t timeout = 0U; uint32_t stab_flag = 0U; - + /* enable HXTAL */ RCU_CTL |= RCU_CTL_HXTALEN; @@ -766,15 +747,14 @@ static void system_clock_200m_8m_hxtal(void) do{ timeout++; stab_flag = (RCU_CTL & RCU_CTL_HXTALSTB); - } - while((0U == stab_flag) && (HXTAL_STARTUP_TIMEOUT != timeout)); + }while((0U == stab_flag) && (HXTAL_STARTUP_TIMEOUT != timeout)); /* if fail */ if(0U == (RCU_CTL & RCU_CTL_HXTALSTB)){ - while(1){ - } + while(1){ + } } - + RCU_APB1EN |= RCU_APB1EN_PMUEN; PMU_CTL |= PMU_CTL_LDOVS; @@ -786,7 +766,7 @@ static void system_clock_200m_8m_hxtal(void) /* APB1 = AHB/4 */ RCU_CFG0 |= RCU_APB1_CKAHB_DIV4; - /* Configure the main PLL, PLL_M = 8, PLL_N = 400, PLL_P = 2, PLL_Q = 9 */ + /* Configure the main PLL, PSC = 8, PLL_N = 400, PLL_P = 2, PLL_Q = 9 */ RCU_PLL = (8U | (400U << 6U) | (((2U >> 1U) - 1U) << 16U) | (RCU_PLLSRC_HXTAL) | (9U << 24U)); @@ -796,19 +776,17 @@ static void system_clock_200m_8m_hxtal(void) /* wait until PLL is stable */ while(0U == (RCU_CTL & RCU_CTL_PLLSTB)){ } - + /* Enable the high-drive to extend the clock frequency to 200 Mhz */ PMU_CTL |= PMU_CTL_HDEN; - while(0U == (PMU_CS & PMU_CS_HDRF)) - { + while(0U == (PMU_CS & PMU_CS_HDRF)){ } - + /* select the high-drive mode */ PMU_CTL |= PMU_CTL_HDS; - while(0U == (PMU_CS & PMU_CS_HDSRF)) - { - } - + while(0U == (PMU_CS & PMU_CS_HDSRF)){ + } + /* select PLL as system clock */ RCU_CFG0 &= ~RCU_CFG0_SCS; RCU_CFG0 |= RCU_CKSYSSRC_PLLP; @@ -829,7 +807,7 @@ static void system_clock_200m_25m_hxtal(void) { uint32_t timeout = 0U; uint32_t stab_flag = 0U; - + /* enable HXTAL */ RCU_CTL |= RCU_CTL_HXTALEN; @@ -837,15 +815,14 @@ static void system_clock_200m_25m_hxtal(void) do{ timeout++; stab_flag = (RCU_CTL & RCU_CTL_HXTALSTB); - } - while((0U == stab_flag) && (HXTAL_STARTUP_TIMEOUT != timeout)); + }while((0U == stab_flag) && (HXTAL_STARTUP_TIMEOUT != timeout)); /* if fail */ if(0U == (RCU_CTL & RCU_CTL_HXTALSTB)){ - while(1){ - } + while(1){ + } } - + RCU_APB1EN |= RCU_APB1EN_PMUEN; PMU_CTL |= PMU_CTL_LDOVS; @@ -857,7 +834,7 @@ static void system_clock_200m_25m_hxtal(void) /* APB1 = AHB/4 */ RCU_CFG0 |= RCU_APB1_CKAHB_DIV4; - /* Configure the main PLL, PLL_M = 25, PLL_N = 400, PLL_P = 2, PLL_Q = 9 */ + /* Configure the main PLL, PSC = 25, PLL_N = 400, PLL_P = 2, PLL_Q = 9 */ RCU_PLL = (25U | (400U << 6U) | (((2U >> 1U) - 1U) << 16U) | (RCU_PLLSRC_HXTAL) | (9U << 24U)); @@ -867,19 +844,17 @@ static void system_clock_200m_25m_hxtal(void) /* wait until PLL is stable */ while(0U == (RCU_CTL & RCU_CTL_PLLSTB)){ } - + /* Enable the high-drive to extend the clock frequency to 200 Mhz */ PMU_CTL |= PMU_CTL_HDEN; - while(0U == (PMU_CS & PMU_CS_HDRF)) - { + while(0U == (PMU_CS & PMU_CS_HDRF)){ } - + /* select the high-drive mode */ PMU_CTL |= PMU_CTL_HDS; - while(0U == (PMU_CS & PMU_CS_HDSRF)) - { - } - + while(0U == (PMU_CS & PMU_CS_HDSRF)){ + } + /* select PLL as system clock */ RCU_CFG0 &= ~RCU_CFG0_SCS; RCU_CFG0 |= RCU_CKSYSSRC_PLLP; @@ -900,7 +875,7 @@ void SystemCoreClockUpdate (void) { uint32_t sws; uint32_t pllpsc, plln, pllsel, pllp, ck_src, idx, clk_exp; - + /* exponent of AHB, APB1 and APB2 clock divider */ const uint8_t ahb_exp[16] = {0, 0, 0, 0, 0, 0, 0, 0, 1, 2, 3, 4, 6, 7, 8, 9}; diff --git a/bsp/gd32450z-eval/Libraries/CMSIS/core_cm4.h b/bsp/gd32450z-eval/Libraries/CMSIS/core_cm4.h index d82841442c..e3cd89f728 100644 --- a/bsp/gd32450z-eval/Libraries/CMSIS/core_cm4.h +++ b/bsp/gd32450z-eval/Libraries/CMSIS/core_cm4.h @@ -100,7 +100,7 @@ #define __INLINE inline /*!< inline keyword for TASKING Compiler */ #define __STATIC_INLINE static inline -#elif defined ( __CSMC__ ) /* Cosmic */ +#elif defined ( __CSMC__ ) /* Cosmic */ #define __packed #define __ASM _asm /*!< asm keyword for COSMIC Compiler */ #define __INLINE inline /*use -pc99 on compile line !< inline keyword for COSMIC Compiler */ @@ -170,8 +170,8 @@ #define __FPU_USED 0 #endif -#elif defined ( __CSMC__ ) /* Cosmic */ - #if ( __CSMC__ & 0x400) // FPU present for parser +#elif defined ( __CSMC__ ) /* Cosmic */ + #if ( __CSMC__ & 0x400) // FPU present for parser #if (__FPU_PRESENT == 1) #define __FPU_USED 1 #else diff --git a/bsp/gd32450z-eval/Libraries/CMSIS/core_cmFunc.h b/bsp/gd32450z-eval/Libraries/CMSIS/core_cmFunc.h index b6ad0a4c5f..834bd17645 100644 --- a/bsp/gd32450z-eval/Libraries/CMSIS/core_cmFunc.h +++ b/bsp/gd32450z-eval/Libraries/CMSIS/core_cmFunc.h @@ -552,7 +552,7 @@ __attribute__( ( always_inline ) ) __STATIC_INLINE void __set_BASEPRI(uint32_t v /** \brief Set Base Priority with condition This function assigns the given value to the Base Priority register only if BASEPRI masking is disabled, - or the new value increases the BASEPRI priority level. + or the new value increases the BASEPRI priority level. \param [in] basePri Base Priority value to set */ diff --git a/bsp/gd32450z-eval/Libraries/GD32F4xx_standard_peripheral/Include/gd32f4xx_adc.h b/bsp/gd32450z-eval/Libraries/GD32F4xx_standard_peripheral/Include/gd32f4xx_adc.h index 694428f07c..4f6020a50a 100644 --- a/bsp/gd32450z-eval/Libraries/GD32F4xx_standard_peripheral/Include/gd32f4xx_adc.h +++ b/bsp/gd32450z-eval/Libraries/GD32F4xx_standard_peripheral/Include/gd32f4xx_adc.h @@ -1,12 +1,37 @@ /*! - \file gd32f4xx_adc.h - \brief definitions for the ADC + \file gd32f4xx_adc.h + \brief definitions for the ADC + + \version 2016-08-15, V1.0.0, firmware for GD32F4xx + \version 2018-12-12, V2.0.0, firmware for GD32F4xx + \version 2020-09-30, V2.1.0, firmware for GD32F4xx */ /* - Copyright (C) 2016 GigaDevice + Copyright (c) 2020, GigaDevice Semiconductor Inc. + + Redistribution and use in source and binary forms, with or without modification, +are permitted provided that the following conditions are met: + + 1. Redistributions of source code must retain the above copyright notice, this + list of conditions and the following disclaimer. + 2. Redistributions in binary form must reproduce the above copyright notice, + this list of conditions and the following disclaimer in the documentation + and/or other materials provided with the distribution. + 3. Neither the name of the copyright holder nor the names of its contributors + may be used to endorse or promote products derived from this software without + specific prior written permission. - 2016-08-15, V1.0.0, firmware for GD32F4xx + THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED +WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. +IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, +INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT +NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR +PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, +WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY +OF SUCH DAMAGE. */ #ifndef GD32F4XX_ADC_H @@ -68,7 +93,7 @@ #define ADC_CTL0_IWDEN BIT(22) /*!< analog watchdog enable on inserted channels */ #define ADC_CTL0_RWDEN BIT(23) /*!< analog watchdog enable on regular channels */ #define ADC_CTL0_DRES BITS(24,25) /*!< ADC data resolution */ -#define ADC_CTL0_ROVFIE BIT(26) /*!< interrupt enable for ROVF */ +#define ADC_CTL0_ROVFIE BIT(26) /*!< interrupt enable for ROVF */ /* ADC_CTL1 */ #define ADC_CTL1_ADCON BIT(0) /*!< ADC converter on */ @@ -152,65 +177,6 @@ #define ADC_SYNCDATA_SYNCDATA1 BITS(16,31) /*!< regular data2 in ADC synchronization mode */ /* constants definitions */ -/* ADC channel group definitions */ -#define ADC_REGULAR_CHANNEL ((uint8_t)0x00U) /*!< adc regular channel group */ -#define ADC_INSERTED_CHANNEL ((uint8_t)0x01U) /*!< adc inserted channel group */ -#define ADC_REGULAR_INSERTED_CHANNEL ((uint8_t)0x02U) /*!< both regular and inserted channel group */ - -/* external trigger mode for regular and inserted channel */ -#define EXTERNAL_TRIGGER_DISABLE ((uint32_t)0x00000000U) /*!< external trigger disable */ -#define EXTERNAL_TRIGGER_RISING ((uint32_t)0x00000001U) /*!< rising edge of external trigger */ -#define EXTERNAL_TRIGGER_FALLING ((uint32_t)0x00000002U) /*!< falling edge of external trigger */ -#define EXTERNAL_TRIGGER_RISING_FALLING ((uint32_t)0x00000003U) /*!< rising and falling edge of external trigger */ - -/* ADC inserted channel definitions */ -#define ADC_INSERTED_CHANNEL_0 ((uint8_t)0x00U) /*!< adc inserted channel 0 */ -#define ADC_INSERTED_CHANNEL_1 ((uint8_t)0x01U) /*!< adc inserted channel 1 */ -#define ADC_INSERTED_CHANNEL_2 ((uint8_t)0x02U) /*!< adc inserted channel 2 */ -#define ADC_INSERTED_CHANNEL_3 ((uint8_t)0x03U) /*!< adc inserted channel 3 */ - -/* ADC special function definitions */ -#define ADC_SCAN_MODE ((uint8_t)0x00U) /*!< scan mode */ -#define ADC_INSERTED_CHANNEL_AUTO ((uint8_t)0x01U) /*!< inserted channel group convert automatically */ -#define ADC_VBAT_CHANNEL_SWITCH ((uint8_t)0x02U) /*!< VBAT channel */ -#define ADC_TEMP_VREF_CHANNEL_SWITCH ((uint8_t)0x03U) /*!< Vref and Vtemp channel */ -#define ADC_CONTINUOUS_MODE ((uint8_t)0x04U) /*!< continuous mode */ - -/* ADC channel definitions */ -#define ADC_CHANNEL_0 ((uint8_t)0x00U) /*!< ADC channel 0 */ -#define ADC_CHANNEL_1 ((uint8_t)0x01U) /*!< ADC channel 1 */ -#define ADC_CHANNEL_2 ((uint8_t)0x02U) /*!< ADC channel 2 */ -#define ADC_CHANNEL_3 ((uint8_t)0x03U) /*!< ADC channel 3 */ -#define ADC_CHANNEL_4 ((uint8_t)0x04U) /*!< ADC channel 4 */ -#define ADC_CHANNEL_5 ((uint8_t)0x05U) /*!< ADC channel 5 */ -#define ADC_CHANNEL_6 ((uint8_t)0x06U) /*!< ADC channel 6 */ -#define ADC_CHANNEL_7 ((uint8_t)0x07U) /*!< ADC channel 7 */ -#define ADC_CHANNEL_8 ((uint8_t)0x08U) /*!< ADC channel 8 */ -#define ADC_CHANNEL_9 ((uint8_t)0x09U) /*!< ADC channel 9 */ -#define ADC_CHANNEL_10 ((uint8_t)0x0AU) /*!< ADC channel 10 */ -#define ADC_CHANNEL_11 ((uint8_t)0x0BU) /*!< ADC channel 11 */ -#define ADC_CHANNEL_12 ((uint8_t)0x0CU) /*!< ADC channel 12 */ -#define ADC_CHANNEL_13 ((uint8_t)0x0DU) /*!< ADC channel 13 */ -#define ADC_CHANNEL_14 ((uint8_t)0x0EU) /*!< ADC channel 14 */ -#define ADC_CHANNEL_15 ((uint8_t)0x0FU) /*!< ADC channel 15 */ -#define ADC_CHANNEL_16 ((uint8_t)0x10U) /*!< ADC channel 16 */ -#define ADC_CHANNEL_17 ((uint8_t)0x11U) /*!< ADC channel 17 */ -#define ADC_CHANNEL_18 ((uint8_t)0x12U) /*!< ADC channel 18 */ - -/* ADC channel sample time */ -#define ADC_SAMPLETIME_3 ((uint8_t)0x00U) /*!< 3 sampling cycles */ -#define ADC_SAMPLETIME_15 ((uint8_t)0x01U) /*!< 15 sampling cycles */ -#define ADC_SAMPLETIME_28 ((uint8_t)0x02U) /*!< 28 sampling cycles */ -#define ADC_SAMPLETIME_56 ((uint8_t)0x03U) /*!< 56 sampling cycles */ -#define ADC_SAMPLETIME_84 ((uint8_t)0x04U) /*!< 84 sampling cycles */ -#define ADC_SAMPLETIME_112 ((uint8_t)0x05U) /*!< 112 sampling cycles */ -#define ADC_SAMPLETIME_144 ((uint8_t)0x06U) /*!< 144 sampling cycles */ -#define ADC_SAMPLETIME_480 ((uint8_t)0x07U) /*!< 480 sampling cycles */ - -/* ADC data alignment */ -#define ADC_DATAALIGN_RIGHT ((uint8_t)0x00U) /*!< LSB alignment */ -#define ADC_DATAALIGN_LEFT ((uint8_t)0x01U) /*!< MSB alignment */ - /* ADC status flag */ #define ADC_FLAG_WDE ADC_STAT_WDE /*!< analog watchdog event flag */ #define ADC_FLAG_EOC ADC_STAT_EOC /*!< end of conversion */ @@ -219,18 +185,43 @@ #define ADC_FLAG_STRC ADC_STAT_STRC /*!< regular channel start flag */ #define ADC_FLAG_ROVF ADC_STAT_ROVF /*!< regular data register overflow */ -/* ADC interrupt flag */ -#define ADC_INT_WDE ADC_STAT_WDE /*!< analog watchdog event interrupt */ -#define ADC_INT_EOC ADC_STAT_EOC /*!< end of group conversion interrupt */ -#define ADC_INT_EOIC ADC_STAT_EOIC /*!< end of inserted group conversion interrupt */ -#define ADC_INT_ROVF ADC_STAT_ROVF /*!< regular data register overflow */ +/* adc_ctl0 register value */ +#define CTL0_DISNUM(regval) (BITS(13,15) & ((uint32_t)(regval) << 13)) /*!< write value to ADC_CTL0_DISNUM bit field */ + +/* ADC special function definitions */ +#define ADC_SCAN_MODE ADC_CTL0_SM /*!< scan mode */ +#define ADC_INSERTED_CHANNEL_AUTO ADC_CTL0_ICA /*!< inserted channel group convert automatically */ +#define ADC_CONTINUOUS_MODE ADC_CTL1_CTN /*!< continuous mode */ -/* ADC resolution definitions */ -#define CTL0_DRES(regval) (BITS(24,25) & ((uint32_t)(regval) << 24)) -#define ADC_RESOLUTION_12B CTL0_DRES(0) /*!< 12-bit ADC resolution */ -#define ADC_RESOLUTION_10B CTL0_DRES(1) /*!< 10-bit ADC resolution */ -#define ADC_RESOLUTION_8B CTL0_DRES(2) /*!< 8-bit ADC resolution */ -#define ADC_RESOLUTION_6B CTL0_DRES(3) /*!< 6-bit ADC resolution */ +/* temperature sensor channel, internal reference voltage channel, VBAT channel */ +#define ADC_VBAT_CHANNEL_SWITCH ADC_SYNCCTL_VBATEN /*!< VBAT channel */ +#define ADC_TEMP_VREF_CHANNEL_SWITCH ADC_SYNCCTL_TSVREN /*!< Vref and Vtemp channel */ + +/* ADC synchronization mode */ +#define SYNCCTL_SYNCM(regval) (BITS(0,4) & ((uint32_t)(regval))) /*!< write value to ADC_CTL0_SYNCM bit field */ +#define ADC_SYNC_MODE_INDEPENDENT SYNCCTL_SYNCM(0) /*!< ADC synchronization mode disabled.All the ADCs work independently */ +#define ADC_DAUL_REGULAL_PARALLEL_INSERTED_PARALLEL SYNCCTL_SYNCM(1) /*!< ADC0 and ADC1 work in combined regular parallel & inserted parallel mode. ADC2 works independently */ +#define ADC_DAUL_REGULAL_PARALLEL_INSERTED_ROTATION SYNCCTL_SYNCM(2) /*!< ADC0 and ADC1 work in combined regular parallel & trigger rotation mode. ADC2 works independently */ +#define ADC_DAUL_INSERTED_PARALLEL SYNCCTL_SYNCM(5) /*!< ADC0 and ADC1 work in inserted parallel mode. ADC2 works independently */ +#define ADC_DAUL_REGULAL_PARALLEL SYNCCTL_SYNCM(6) /*!< ADC0 and ADC1 work in regular parallel mode. ADC2 works independently */ +#define ADC_DAUL_REGULAL_FOLLOW_UP SYNCCTL_SYNCM(7) /*!< ADC0 and ADC1 work in follow-up mode. ADC2 works independently */ +#define ADC_DAUL_INSERTED_TRRIGGER_ROTATION SYNCCTL_SYNCM(9) /*!< ADC0 and ADC1 work in trigger rotation mode. ADC2 works independently */ +#define ADC_ALL_REGULAL_PARALLEL_INSERTED_PARALLEL SYNCCTL_SYNCM(17) /*!< all ADCs work in combined regular parallel & inserted parallel mode */ +#define ADC_ALL_REGULAL_PARALLEL_INSERTED_ROTATION SYNCCTL_SYNCM(18) /*!< all ADCs work in combined regular parallel & trigger rotation mode */ +#define ADC_ALL_INSERTED_PARALLEL SYNCCTL_SYNCM(21) /*!< all ADCs work in inserted parallel mode */ +#define ADC_ALL_REGULAL_PARALLEL SYNCCTL_SYNCM(22) /*!< all ADCs work in regular parallel mode */ +#define ADC_ALL_REGULAL_FOLLOW_UP SYNCCTL_SYNCM(23) /*!< all ADCs work in follow-up mode */ +#define ADC_ALL_INSERTED_TRRIGGER_ROTATION SYNCCTL_SYNCM(25) /*!< all ADCs work in trigger rotation mode */ + +/* ADC data alignment */ +#define ADC_DATAALIGN_RIGHT ((uint32_t)0x00000000U) /*!< LSB alignment */ +#define ADC_DATAALIGN_LEFT ADC_CTL1_DAL /*!< MSB alignment */ + +/* external trigger mode for regular and inserted channel */ +#define EXTERNAL_TRIGGER_DISABLE ((uint32_t)0x00000000U) /*!< external trigger disable */ +#define EXTERNAL_TRIGGER_RISING ((uint32_t)0x00000001U) /*!< rising edge of external trigger */ +#define EXTERNAL_TRIGGER_FALLING ((uint32_t)0x00000002U) /*!< falling edge of external trigger */ +#define EXTERNAL_TRIGGER_RISING_FALLING ((uint32_t)0x00000003U) /*!< rising and falling edge of external trigger */ /* ADC external trigger select for regular channel */ #define CTL1_ETSRC(regval) (BITS(24,27) & ((uint32_t)(regval) << 24)) @@ -270,32 +261,111 @@ #define ADC_EXTTRIG_INSERTED_T7_CH3 CTL1_ETSIC(14) /*!< timer7 capture compare 3 */ #define ADC_EXTTRIG_INSERTED_EXTI_15 CTL1_ETSIC(15) /*!< external interrupt line 15 */ -/* ADC oversampling mode */ -#define ADC_OVERSAMPLING_ALL_CONVERT 0U /*!< all oversampled conversions for a channel are done consecutively after a trigger */ -#define ADC_OVERSAMPLING_ONE_CONVERT 1U /*!< each oversampled conversion for a channel needs a trigger */ +/* ADC channel sample time */ +#define SAMPTX_SPT(regval) (BITS(0,2) & ((uint32_t)(regval) << 0)) /*!< write value to ADC_SAMPTX_SPT bit field */ +#define ADC_SAMPLETIME_3 SAMPTX_SPT(0) /*!< 3 sampling cycles */ +#define ADC_SAMPLETIME_15 SAMPTX_SPT(1) /*!< 15 sampling cycles */ +#define ADC_SAMPLETIME_28 SAMPTX_SPT(2) /*!< 28 sampling cycles */ +#define ADC_SAMPLETIME_56 SAMPTX_SPT(3) /*!< 56 sampling cycles */ +#define ADC_SAMPLETIME_84 SAMPTX_SPT(4) /*!< 84 sampling cycles */ +#define ADC_SAMPLETIME_112 SAMPTX_SPT(5) /*!< 112 sampling cycles */ +#define ADC_SAMPLETIME_144 SAMPTX_SPT(6) /*!< 144 sampling cycles */ +#define ADC_SAMPLETIME_480 SAMPTX_SPT(7) /*!< 480 sampling cycles */ + +/* adc_ioffx register value */ +#define IOFFX_IOFF(regval) (BITS(0,11) & ((uint32_t)(regval) << 0)) /*!< write value to ADC_IOFFX_IOFF bit field */ + +/* adc_wdht register value */ +#define WDHT_WDHT(regval) (BITS(0,11) & ((uint32_t)(regval) << 0)) /*!< write value to ADC_WDHT_WDHT bit field */ + +/* adc_wdlt register value */ +#define WDLT_WDLT(regval) (BITS(0,11) & ((uint32_t)(regval) << 0)) /*!< write value to ADC_WDLT_WDLT bit field */ + +/* adc_rsqx register value */ +#define RSQ0_RL(regval) (BITS(20,23) & ((uint32_t)(regval) << 20)) /*!< write value to ADC_RSQ0_RL bit field */ + +/* adc_isq register value */ +#define ISQ_IL(regval) (BITS(20,21) & ((uint32_t)(regval) << 20)) /*!< write value to ADC_ISQ_IL bit field */ + +/* adc_ovsampctl register value */ +/* ADC resolution */ +#define CTL0_DRES(regval) (BITS(24,25) & ((uint32_t)(regval) << 24)) /*!< write value to ADC_CTL0_DRES bit field */ +#define ADC_RESOLUTION_12B CTL0_DRES(0) /*!< 12-bit ADC resolution */ +#define ADC_RESOLUTION_10B CTL0_DRES(1) /*!< 10-bit ADC resolution */ +#define ADC_RESOLUTION_8B CTL0_DRES(2) /*!< 8-bit ADC resolution */ +#define ADC_RESOLUTION_6B CTL0_DRES(3) /*!< 6-bit ADC resolution */ + +/* oversampling shift */ +#define OVSAMPCTL_OVSS(regval) (BITS(5,8) & ((uint32_t)(regval) << 5)) /*!< write value to ADC_OVSAMPCTL_OVSS bit field */ +#define ADC_OVERSAMPLING_SHIFT_NONE OVSAMPCTL_OVSS(0) /*!< no oversampling shift */ +#define ADC_OVERSAMPLING_SHIFT_1B OVSAMPCTL_OVSS(1) /*!< 1-bit oversampling shift */ +#define ADC_OVERSAMPLING_SHIFT_2B OVSAMPCTL_OVSS(2) /*!< 2-bit oversampling shift */ +#define ADC_OVERSAMPLING_SHIFT_3B OVSAMPCTL_OVSS(3) /*!< 3-bit oversampling shift */ +#define ADC_OVERSAMPLING_SHIFT_4B OVSAMPCTL_OVSS(4) /*!< 4-bit oversampling shift */ +#define ADC_OVERSAMPLING_SHIFT_5B OVSAMPCTL_OVSS(5) /*!< 5-bit oversampling shift */ +#define ADC_OVERSAMPLING_SHIFT_6B OVSAMPCTL_OVSS(6) /*!< 6-bit oversampling shift */ +#define ADC_OVERSAMPLING_SHIFT_7B OVSAMPCTL_OVSS(7) /*!< 7-bit oversampling shift */ +#define ADC_OVERSAMPLING_SHIFT_8B OVSAMPCTL_OVSS(8) /*!< 8-bit oversampling shift */ + +/* oversampling ratio */ +#define OVSAMPCTL_OVSR(regval) (BITS(2,4) & ((uint32_t)(regval) << 2)) /*!< write value to ADC_OVSAMPCTL_OVSR bit field */ +#define ADC_OVERSAMPLING_RATIO_MUL2 OVSAMPCTL_OVSR(0) /*!< oversampling ratio multiple 2 */ +#define ADC_OVERSAMPLING_RATIO_MUL4 OVSAMPCTL_OVSR(1) /*!< oversampling ratio multiple 4 */ +#define ADC_OVERSAMPLING_RATIO_MUL8 OVSAMPCTL_OVSR(2) /*!< oversampling ratio multiple 8 */ +#define ADC_OVERSAMPLING_RATIO_MUL16 OVSAMPCTL_OVSR(3) /*!< oversampling ratio multiple 16 */ +#define ADC_OVERSAMPLING_RATIO_MUL32 OVSAMPCTL_OVSR(4) /*!< oversampling ratio multiple 32 */ +#define ADC_OVERSAMPLING_RATIO_MUL64 OVSAMPCTL_OVSR(5) /*!< oversampling ratio multiple 64 */ +#define ADC_OVERSAMPLING_RATIO_MUL128 OVSAMPCTL_OVSR(6) /*!< oversampling ratio multiple 128 */ +#define ADC_OVERSAMPLING_RATIO_MUL256 OVSAMPCTL_OVSR(7) /*!< oversampling ratio multiple 256 */ + +/* triggered Oversampling */ +#define ADC_OVERSAMPLING_ALL_CONVERT ((uint32_t)0x00000000U) /*!< all oversampled conversions for a channel are done consecutively after a trigger */ +#define ADC_OVERSAMPLING_ONE_CONVERT ADC_OVSAMPCTL_TOVS /*!< each oversampled conversion for a channel needs a trigger */ + +/* ADC channel group definitions */ +#define ADC_REGULAR_CHANNEL ((uint8_t)0x01U) /*!< adc regular channel group */ +#define ADC_INSERTED_CHANNEL ((uint8_t)0x02U) /*!< adc inserted channel group */ +#define ADC_REGULAR_INSERTED_CHANNEL ((uint8_t)0x03U) /*!< both regular and inserted channel group */ +#define ADC_CHANNEL_DISCON_DISABLE ((uint8_t)0x04U) /*!< disable discontinuous mode of regular & inserted channel */ + +/* ADC inserted channel definitions */ +#define ADC_INSERTED_CHANNEL_0 ((uint8_t)0x00U) /*!< adc inserted channel 0 */ +#define ADC_INSERTED_CHANNEL_1 ((uint8_t)0x01U) /*!< adc inserted channel 1 */ +#define ADC_INSERTED_CHANNEL_2 ((uint8_t)0x02U) /*!< adc inserted channel 2 */ +#define ADC_INSERTED_CHANNEL_3 ((uint8_t)0x03U) /*!< adc inserted channel 3 */ + +/* ADC channel definitions */ +#define ADC_CHANNEL_0 ((uint8_t)0x00U) /*!< ADC channel 0 */ +#define ADC_CHANNEL_1 ((uint8_t)0x01U) /*!< ADC channel 1 */ +#define ADC_CHANNEL_2 ((uint8_t)0x02U) /*!< ADC channel 2 */ +#define ADC_CHANNEL_3 ((uint8_t)0x03U) /*!< ADC channel 3 */ +#define ADC_CHANNEL_4 ((uint8_t)0x04U) /*!< ADC channel 4 */ +#define ADC_CHANNEL_5 ((uint8_t)0x05U) /*!< ADC channel 5 */ +#define ADC_CHANNEL_6 ((uint8_t)0x06U) /*!< ADC channel 6 */ +#define ADC_CHANNEL_7 ((uint8_t)0x07U) /*!< ADC channel 7 */ +#define ADC_CHANNEL_8 ((uint8_t)0x08U) /*!< ADC channel 8 */ +#define ADC_CHANNEL_9 ((uint8_t)0x09U) /*!< ADC channel 9 */ +#define ADC_CHANNEL_10 ((uint8_t)0x0AU) /*!< ADC channel 10 */ +#define ADC_CHANNEL_11 ((uint8_t)0x0BU) /*!< ADC channel 11 */ +#define ADC_CHANNEL_12 ((uint8_t)0x0CU) /*!< ADC channel 12 */ +#define ADC_CHANNEL_13 ((uint8_t)0x0DU) /*!< ADC channel 13 */ +#define ADC_CHANNEL_14 ((uint8_t)0x0EU) /*!< ADC channel 14 */ +#define ADC_CHANNEL_15 ((uint8_t)0x0FU) /*!< ADC channel 15 */ +#define ADC_CHANNEL_16 ((uint8_t)0x10U) /*!< ADC channel 16 */ +#define ADC_CHANNEL_17 ((uint8_t)0x11U) /*!< ADC channel 17 */ +#define ADC_CHANNEL_18 ((uint8_t)0x12U) /*!< ADC channel 18 */ -/* ADC oversampling shift */ -#define OVCTL_OVSS(regval) (BITS(5,8) & ((uint32_t)(regval) << 5)) -#define ADC_OVERSAMPLING_SHIFT_NONE OVCTL_OVSS(0) /*!< no oversampling shift */ -#define ADC_OVERSAMPLING_SHIFT_1B OVCTL_OVSS(1) /*!< 1-bit oversampling shift */ -#define ADC_OVERSAMPLING_SHIFT_2B OVCTL_OVSS(2) /*!< 2-bit oversampling shift */ -#define ADC_OVERSAMPLING_SHIFT_3B OVCTL_OVSS(3) /*!< 3-bit oversampling shift */ -#define ADC_OVERSAMPLING_SHIFT_4B OVCTL_OVSS(4) /*!< 4-bit oversampling shift */ -#define ADC_OVERSAMPLING_SHIFT_5B OVCTL_OVSS(5) /*!< 5-bit oversampling shift */ -#define ADC_OVERSAMPLING_SHIFT_6B OVCTL_OVSS(6) /*!< 6-bit oversampling shift */ -#define ADC_OVERSAMPLING_SHIFT_7B OVCTL_OVSS(7) /*!< 7-bit oversampling shift */ -#define ADC_OVERSAMPLING_SHIFT_8B OVCTL_OVSS(8) /*!< 8-bit oversampling shift */ +/* ADC interrupt flag */ +#define ADC_INT_WDE ADC_CTL0_WDEIE /*!< analog watchdog event interrupt */ +#define ADC_INT_EOC ADC_CTL0_EOCIE /*!< end of group conversion interrupt */ +#define ADC_INT_EOIC ADC_CTL0_EOICIE /*!< end of inserted group conversion interrupt */ +#define ADC_INT_ROVF ADC_CTL0_ROVFIE /*!< regular data register overflow */ -/* ADC oversampling ratio */ -#define OVCTL_OVSR(regval) (BITS(2,4) & ((uint32_t)(regval) << 2)) -#define ADC_OVERSAMPLING_RATIO_MUL2 OVCTL_OVSR(0) /*!< oversampling ratio multiple 2 */ -#define ADC_OVERSAMPLING_RATIO_MUL4 OVCTL_OVSR(1) /*!< oversampling ratio multiple 4 */ -#define ADC_OVERSAMPLING_RATIO_MUL8 OVCTL_OVSR(2) /*!< oversampling ratio multiple 8 */ -#define ADC_OVERSAMPLING_RATIO_MUL16 OVCTL_OVSR(3) /*!< oversampling ratio multiple 16 */ -#define ADC_OVERSAMPLING_RATIO_MUL32 OVCTL_OVSR(4) /*!< oversampling ratio multiple 32 */ -#define ADC_OVERSAMPLING_RATIO_MUL64 OVCTL_OVSR(5) /*!< oversampling ratio multiple 64 */ -#define ADC_OVERSAMPLING_RATIO_MUL128 OVCTL_OVSR(6) /*!< oversampling ratio multiple 128 */ -#define ADC_OVERSAMPLING_RATIO_MUL256 OVCTL_OVSR(7) /*!< oversampling ratio multiple 256 */ +/* ADC interrupt flag */ +#define ADC_INT_FLAG_WDE ADC_STAT_WDE /*!< analog watchdog event interrupt */ +#define ADC_INT_FLAG_EOC ADC_STAT_EOC /*!< end of group conversion interrupt */ +#define ADC_INT_FLAG_EOIC ADC_STAT_EOIC /*!< end of inserted group conversion interrupt */ +#define ADC_INT_FLAG_ROVF ADC_STAT_ROVF /*!< regular data register overflow */ /* configure the ADC clock for all the ADCs */ #define SYNCCTL_ADCCK(regval) (BITS(16,18) & ((uint32_t)(regval) << 16)) @@ -308,21 +378,6 @@ #define ADC_ADCCK_HCLK_DIV10 SYNCCTL_ADCCK(6) /*!< HCLK div10 */ #define ADC_ADCCK_HCLK_DIV20 SYNCCTL_ADCCK(7) /*!< HCLK div20 */ -/* ADC synchronization mode */ -#define ADC_SYNC_MODE_INDEPENDENT ((uint32_t)0x00000000U) /*!< ADC synchronization mode disabled.All the ADCs work independently */ -#define ADC_DAUL_REGULAL_PARALLEL_INSERTED_PARALLEL ((uint32_t)0x00000001U) /*!< ADC0 and ADC1 work in combined regular parallel & inserted parallel mode. ADC2 works independently */ -#define ADC_DAUL_REGULAL_PARALLEL_INSERTED_ROTATION ((uint32_t)0x00000002U) /*!< ADC0 and ADC1 work in combined regular parallel & trigger rotation mode. ADC2 works independently */ -#define ADC_DAUL_INSERTED_PARALLEL ((uint32_t)0x00000005U) /*!< ADC0 and ADC1 work in inserted parallel mode. ADC2 works independently */ -#define ADC_DAUL_REGULAL_PARALLEL ((uint32_t)0x00000006U) /*!< ADC0 and ADC1 work in regular parallel mode. ADC2 works independently */ -#define ADC_DAUL_REGULAL_FOLLOW_UP ((uint32_t)0x00000007U) /*!< ADC0 and ADC1 work in follow-up mode. ADC2 works independently */ -#define ADC_DAUL_INSERTED_TRRIGGER_ROTATION ((uint32_t)0x00000009U) /*!< ADC0 and ADC1 work in trigger rotation mode. ADC2 works independently */ -#define ADC_ALL_REGULAL_PARALLEL_INSERTED_PARALLEL ((uint32_t)0x00000011U) /*!< all ADCs work in combined regular parallel & inserted parallel mode */ -#define ADC_ALL_REGULAL_PARALLEL_INSERTED_ROTATION ((uint32_t)0x00000012U) /*!< all ADCs work in combined regular parallel & trigger rotation mode */ -#define ADC_ALL_INSERTED_PARALLEL ((uint32_t)0x00000015U) /*!< all ADCs work in inserted parallel mode */ -#define ADC_ALL_REGULAL_PARALLEL ((uint32_t)0x00000016U) /*!< all ADCs work in regular parallel mode */ -#define ADC_ALL_REGULAL_FOLLOW_UP ((uint32_t)0x00000017U) /*!< all ADCs work in follow-up mode */ -#define ADC_ALL_INSERTED_TRRIGGER_ROTATION ((uint32_t)0x00000019U) /*!< all ADCs work in trigger rotation mode */ - /* ADC synchronization delay */ #define ADC_SYNC_DELAY_5CYCLE ((uint32_t)0x00000000U) /*!< the delay between 2 sampling phases in ADC synchronization modes to 5 ADC clock cycles. */ #define ADC_SYNC_DELAY_6CYCLE ((uint32_t)0x00000100U) /*!< the delay between 2 sampling phases in ADC synchronization modes to 6 ADC clock cycles. */ @@ -351,99 +406,98 @@ #define ADC_EOC_SET_CONVERSION ((uint8_t)0x01U) /*!< at the end of each regular conversion, the EOC bit is set */ /* function declarations */ -/* ADC reset */ +/* initialization config */ +/* reset ADC */ void adc_deinit(void); +/* configure the ADC clock for all the ADCs */ +void adc_clock_config(uint32_t prescaler); +/* enable or disable ADC special function */ +void adc_special_function_config(uint32_t adc_periph , uint32_t function , ControlStatus newvalue); +/* configure ADC data alignment */ +void adc_data_alignment_config(uint32_t adc_periph , uint32_t data_alignment); /* enable ADC interface */ void adc_enable(uint32_t adc_periph); /* disable ADC interface */ void adc_disable(uint32_t adc_periph); -/* ADC data alignment config */ -void adc_data_alignment_config(uint32_t adc_periph , uint8_t data_alignment); -/* ADC resolution config */ -void adc_resolution_config(uint32_t adc_periph , uint32_t resolution); /* ADC calibration and reset calibration */ void adc_calibration_enable(uint32_t adc_periph); -/* ADC discontinuous mode config */ -void adc_discontinuous_mode_config(uint32_t adc_periph , uint8_t adc_channel_group , uint8_t length); -/* config end of conversion mode */ -void adc_end_of_conversion_config(uint32_t adc_periph , uint8_t end_selection); -/* ADC special function enable or disable */ -void adc_special_function_config(uint32_t adc_periph , uint8_t function , ControlStatus newvalue); -/* configure the ADC clock for all the ADCs */ -void adc_clock_config(uint32_t prescaler); +/* configure temperature sensor and internal reference voltage channel or VBAT channel function */ +void adc_channel_16_to_18(uint32_t function, ControlStatus newvalue); +/* configure ADC resolution */ +void adc_resolution_config(uint32_t adc_periph, uint32_t resolution); +/* configure ADC oversample mode */ +void adc_oversample_mode_config(uint32_t adc_periph, uint32_t mode, uint16_t shift, uint8_t ratio); +/* enable ADC oversample mode */ +void adc_oversample_mode_enable(uint32_t adc_periph); +/* disable ADC oversample mode */ +void adc_oversample_mode_disable(uint32_t adc_periph); -/* ADC channel */ -/* configure the ADC clock for all the ADCs */ -void adc_channel_16_to_18(uint8_t function,ControlStatus newvalue); -/* config the length of regular channel group or inserted channel group */ -void adc_channel_length_config(uint32_t adc_periph , uint8_t adc_channel_group , uint32_t length); +/* DMA config */ +/* enable DMA request */ +void adc_dma_mode_enable(uint32_t adc_periph); +/* disable DMA request */ +void adc_dma_mode_disable(uint32_t adc_periph); +/* when DMA=1, the DMA engine issues a request at end of each regular conversion */ +void adc_dma_request_after_last_enable(uint32_t adc_periph); +/* the DMA engine is disabled after the end of transfer signal from DMA controller is detected */ +void adc_dma_request_after_last_disable(uint32_t adc_periph); -/* ADC trigger */ -/* ADC external trigger enable */ -void adc_external_trigger_config(uint32_t adc_periph , uint8_t adc_channel_group , uint32_t trigger_mode); -/* ADC external trigger source config */ +/* regular group and inserted group config */ +/* configure ADC discontinuous mode */ +void adc_discontinuous_mode_config(uint32_t adc_periph , uint8_t adc_channel_group , uint8_t length); +/* configure the length of regular channel group or inserted channel group */ +void adc_channel_length_config(uint32_t adc_periph , uint8_t adc_channel_group , uint32_t length); +/* configure ADC regular channel */ +void adc_regular_channel_config(uint32_t adc_periph , uint8_t rank , uint8_t adc_channel , uint32_t sample_time); +/* configure ADC inserted channel */ +void adc_inserted_channel_config(uint32_t adc_periph , uint8_t rank , uint8_t adc_channel , uint32_t sample_time); +/* configure ADC inserted channel offset */ +void adc_inserted_channel_offset_config(uint32_t adc_periph , uint8_t inserted_channel , uint16_t offset); +/* configure ADC external trigger source */ void adc_external_trigger_source_config(uint32_t adc_periph , uint8_t adc_channel_group , uint32_t external_trigger_source); -/* ADC software trigger enable */ +/* enable ADC external trigger */ +void adc_external_trigger_config(uint32_t adc_periph , uint8_t adc_channel_group , uint32_t trigger_mode); +/* enable ADC software trigger */ void adc_software_trigger_enable(uint32_t adc_periph , uint8_t adc_channel_group); +/* configure end of conversion mode */ +void adc_end_of_conversion_config(uint32_t adc_periph , uint8_t end_selection); -/* ADC flag and interrupt */ +/* get channel data */ +/* read ADC regular group data register */ +uint16_t adc_regular_data_read(uint32_t adc_periph); +/* read ADC inserted group data register */ +uint16_t adc_inserted_data_read(uint32_t adc_periph , uint8_t inserted_channel); + +/* watchdog config */ +/* disable ADC analog watchdog single channel */ +void adc_watchdog_single_channel_disable(uint32_t adc_periph ); +/* enable ADC analog watchdog single channel */ +void adc_watchdog_single_channel_enable(uint32_t adc_periph , uint8_t adc_channel); +/* configure ADC analog watchdog group channel */ +void adc_watchdog_group_channel_enable(uint32_t adc_periph , uint8_t adc_channel_group); +/* disable ADC analog watchdog */ +void adc_watchdog_disable(uint32_t adc_periph , uint8_t adc_channel_group); +/* configure ADC analog watchdog threshold */ +void adc_watchdog_threshold_config(uint32_t adc_periph , uint16_t low_threshold , uint16_t high_threshold); + +/* interrupt & flag functions */ /* get the ADC flag bits */ FlagStatus adc_flag_get(uint32_t adc_periph , uint32_t adc_flag); /* clear the ADC flag bits */ void adc_flag_clear(uint32_t adc_periph , uint32_t adc_flag); +/* get the bit state of ADCx software start conversion */ +FlagStatus adc_regular_software_startconv_flag_get(uint32_t adc_periph); +/* get the bit state of ADCx software inserted channel start conversion */ +FlagStatus adc_inserted_software_startconv_flag_get(uint32_t adc_periph); /* get the ADC interrupt bits */ FlagStatus adc_interrupt_flag_get(uint32_t adc_periph , uint32_t adc_interrupt); /* clear the ADC flag */ void adc_interrupt_flag_clear(uint32_t adc_periph , uint32_t adc_interrupt); -/* ADC interrupt enable */ +/* enable ADC interrupt */ void adc_interrupt_enable(uint32_t adc_periph , uint32_t adc_interrupt); -/* ADC interrupt disable */ +/* disable ADC interrupt */ void adc_interrupt_disable(uint32_t adc_periph , uint32_t adc_interrupt); -/* ADC analog watchdog */ -/* ADC analog watchdog single channel disable */ -void adc_watchdog_single_channel_disable(uint32_t adc_periph ); -/* ADC analog watchdog single channel enable */ -void adc_watchdog_single_channel_enable(uint32_t adc_periph , uint8_t adc_channel); -/* adc analog watchdog group channel config */ -void adc_watchdog_enable(uint32_t adc_periph , uint8_t adc_channel_group); -/* ADC analog watchdog disable */ -void adc_watchdog_disable(uint32_t adc_periph , uint8_t adc_channel_group); -/* ADC analog watchdog threshold config */ -void adc_watchdog_threshold_config(uint32_t adc_periph , uint16_t low_threshold , uint16_t high_threshold); - -/* regular channel */ -/* ADC regular channel config */ -void adc_regular_channel_config(uint32_t adc_periph , uint8_t rank , uint8_t adc_channel , uint32_t sample_time); -/* ADC regular group data register read */ -uint16_t adc_regular_data_read(uint32_t adc_periph); - -/* inserted channel */ -/* ADC inserted channel config */ -void adc_inserted_channel_config(uint32_t adc_periph , uint8_t rank , uint8_t adc_channel , uint8_t sample_time); -/* ADC inserted channel offset config */ -void adc_inserted_channel_offset_config(uint32_t adc_periph , uint8_t inserted_channel , uint16_t offset); -/* ADC inserted group data register read */ -uint16_t adc_inserted_data_read(uint32_t adc_periph , uint8_t inserted_channel); - -/* ADC DMA */ -/* DMA request enable */ -void adc_dma_mode_enable(uint32_t adc_periph); -/* DMA request disable */ -void adc_dma_mode_disable(uint32_t adc_periph); -/* when DMA=1, the DMA engine issues a request at end of each regular conversion */ -void adc_dma_request_after_last_enable(uint32_t adc_periph); -/* the DMA engine is disabled after the end of transfer signal from DMA controller is detected */ -void adc_dma_request_after_last_disable(uint32_t adc_periph); - -/* ADC oversample */ -/* ADC oversample mode config */ -void adc_oversample_mode_config(uint32_t adc_periph , uint8_t mode , uint16_t shift , uint8_t ratio); -/* ADC oversample mode enable */ -void adc_oversample_mode_enable(uint32_t adc_periph ); -/* ADC oversample mode disable */ -void adc_oversample_mode_disable(uint32_t adc_periph ); - /* ADC synchronization */ /* configure the ADC sync mode */ void adc_sync_mode_config(uint32_t sync_mode); @@ -455,7 +509,7 @@ void adc_sync_dma_config(uint32_t dma_mode ); void adc_sync_dma_request_after_last_enable(void); /* configure ADC sync DMA engine issues requests according to the SYNCDMA bits */ void adc_sync_dma_request_after_last_disable(void); -/* ADC sync regular data register read */ +/* read ADC sync regular data register */ uint32_t adc_sync_regular_data_read(void); #endif /* GD32F4XX_ADC_H */ diff --git a/bsp/gd32450z-eval/Libraries/GD32F4xx_standard_peripheral/Include/gd32f4xx_can.h b/bsp/gd32450z-eval/Libraries/GD32F4xx_standard_peripheral/Include/gd32f4xx_can.h index 2be5832462..7310f63a75 100644 --- a/bsp/gd32450z-eval/Libraries/GD32F4xx_standard_peripheral/Include/gd32f4xx_can.h +++ b/bsp/gd32450z-eval/Libraries/GD32F4xx_standard_peripheral/Include/gd32f4xx_can.h @@ -1,12 +1,38 @@ /*! - \file gd32f4xx_can.h - \brief definitions for the CAN + \file gd32f4xx_can.h + \brief definitions for the CAN + + \version 2016-08-15, V1.0.0, firmware for GD32F4xx + \version 2018-12-12, V2.0.0, firmware for GD32F4xx + \version 2019-11-27, V2.0.1, firmware for GD32F4xx + \version 2020-09-30, V2.1.0, firmware for GD32F4xx */ /* - Copyright (C) 2016 GigaDevice + Copyright (c) 2020, GigaDevice Semiconductor Inc. + + Redistribution and use in source and binary forms, with or without modification, +are permitted provided that the following conditions are met: + + 1. Redistributions of source code must retain the above copyright notice, this + list of conditions and the following disclaimer. + 2. Redistributions in binary form must reproduce the above copyright notice, + this list of conditions and the following disclaimer in the documentation + and/or other materials provided with the distribution. + 3. Neither the name of the copyright holder nor the names of its contributors + may be used to endorse or promote products derived from this software without + specific prior written permission. - 2016-08-15, V1.0.0, firmware for GD32F4xx + THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED +WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. +IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, +INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT +NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR +PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, +WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY +OF SUCH DAMAGE. */ #ifndef GD32F4XX_CAN_H @@ -42,7 +68,7 @@ #define CAN_RFIFOMI0(canx) REG32((canx) + 0x1B0U) /*!< CAN receive FIFO0 mailbox identifier register */ #define CAN_RFIFOMP0(canx) REG32((canx) + 0x1B4U) /*!< CAN receive FIFO0 mailbox property register */ #define CAN_RFIFOMDATA00(canx) REG32((canx) + 0x1B8U) /*!< CAN receive FIFO0 mailbox data0 register */ -#define CAN_RFIFOMDATA10(canx) REG32((canx) + 0x1CCU) /*!< CAN receive FIFO0 mailbox data1 register */ +#define CAN_RFIFOMDATA10(canx) REG32((canx) + 0x1BCU) /*!< CAN receive FIFO0 mailbox data1 register */ #define CAN_RFIFOMI1(canx) REG32((canx) + 0x1C0U) /*!< CAN receive FIFO1 mailbox identifier register */ #define CAN_RFIFOMP1(canx) REG32((canx) + 0x1C4U) /*!< CAN receive FIFO1 mailbox property register */ #define CAN_RFIFOMDATA01(canx) REG32((canx) + 0x1C8U) /*!< CAN receive FIFO1 mailbox data0 register */ @@ -110,20 +136,20 @@ #define CAN_F27DATA1(canx) REG32((canx) + 0x31CU) /*!< CAN filter 27 data 1 register */ /* CAN transmit mailbox bank */ -#define CAN_TMI(canx, bank) REG32((canx) + 0x180U + ((bank) * 0x10U)) /*!< CAN transmit mailbox identifier register */ -#define CAN_TMP(canx, bank) REG32((canx) + 0x184U + ((bank) * 0x10U)) /*!< CAN transmit mailbox property register */ -#define CAN_TMDATA0(canx, bank) REG32((canx) + 0x188U + ((bank) * 0x10U)) /*!< CAN transmit mailbox data0 register */ -#define CAN_TMDATA1(canx, bank) REG32((canx) + 0x18CU + ((bank) * 0x10U)) /*!< CAN transmit mailbox data1 register */ +#define CAN_TMI(canx, bank) REG32((canx) + 0x180U + ((bank) * 0x10U)) /*!< CAN transmit mailbox identifier register */ +#define CAN_TMP(canx, bank) REG32((canx) + 0x184U + ((bank) * 0x10U)) /*!< CAN transmit mailbox property register */ +#define CAN_TMDATA0(canx, bank) REG32((canx) + 0x188U + ((bank) * 0x10U)) /*!< CAN transmit mailbox data0 register */ +#define CAN_TMDATA1(canx, bank) REG32((canx) + 0x18CU + ((bank) * 0x10U)) /*!< CAN transmit mailbox data1 register */ /* CAN filter bank */ -#define CAN_FDATA0(canx, bank) REG32((canx) + 0x240U + ((bank) * 0x8U) + 0x0U) /*!< CAN filter data 0 register */ -#define CAN_FDATA1(canx, bank) REG32((canx) + 0x240U + ((bank) * 0x8U) + 0x4U) /*!< CAN filter data 1 register */ +#define CAN_FDATA0(canx, bank) REG32((canx) + 0x240U + ((bank) * 0x8U) + 0x0U) /*!< CAN filter data 0 register */ +#define CAN_FDATA1(canx, bank) REG32((canx) + 0x240U + ((bank) * 0x8U) + 0x4U) /*!< CAN filter data 1 register */ /* CAN receive fifo mailbox bank */ -#define CAN_RFIFOMI(canx, bank) REG32((canx) + 0x1B0U + ((bank) * 0x10U)) /*!< CAN receive FIFO mailbox identifier register */ -#define CAN_RFIFOMP(canx, bank) REG32((canx) + 0x1B4U + ((bank) * 0x10U)) /*!< CAN receive FIFO mailbox property register */ -#define CAN_RFIFOMDATA0(canx, bank) REG32((canx) + 0x1B8U + ((bank) * 0x10U)) /*!< CAN receive FIFO mailbox data0 register */ -#define CAN_RFIFOMDATA1(canx, bank) REG32((canx) + 0x1BCU + ((bank) * 0x10U)) /*!< CAN receive FIFO mailbox data1 register */ +#define CAN_RFIFOMI(canx, bank) REG32((canx) + 0x1B0U + ((bank) * 0x10U)) /*!< CAN receive FIFO mailbox identifier register */ +#define CAN_RFIFOMP(canx, bank) REG32((canx) + 0x1B4U + ((bank) * 0x10U)) /*!< CAN receive FIFO mailbox property register */ +#define CAN_RFIFOMDATA0(canx, bank) REG32((canx) + 0x1B8U + ((bank) * 0x10U)) /*!< CAN receive FIFO mailbox data0 register */ +#define CAN_RFIFOMDATA1(canx, bank) REG32((canx) + 0x1BCU + ((bank) * 0x10U)) /*!< CAN receive FIFO mailbox data1 register */ /* bits definitions */ /* CAN_CTL */ @@ -198,7 +224,7 @@ #define CAN_INTEN_BOIE BIT(10) /*!< bus-off interrupt enable */ #define CAN_INTEN_ERRNIE BIT(11) /*!< error number interrupt enable */ #define CAN_INTEN_ERRIE BIT(15) /*!< error interrupt enable */ -#define CAN_INTEN_WUIE BIT(16) /*!< wakeup interrupt enable */ +#define CAN_INTEN_WIE BIT(16) /*!< wakeup interrupt enable */ #define CAN_INTEN_SLPWIE BIT(17) /*!< sleep working interrupt enable */ /* CAN_ERR */ @@ -280,11 +306,19 @@ /* CAN_FW */ #define CAN_FW_FW(regval) BIT(regval) /*!< filter working */ +/* CAN_FxDATAy */ +#define CAN_FDATA_FD(regval) BIT(regval) /*!< filter data */ + /* consts definitions */ /* define the CAN bit position and its register index offset */ -#define CAN_REGIDX_BIT(regidx, bitpos) (((uint32_t)(regidx) << 6) | (uint32_t)(bitpos)) -#define CAN_REG_VAL(canx, offset) (REG32((canx) + ((uint32_t)(offset) >> 6))) -#define CAN_BIT_POS(val) ((uint32_t)(val) & 0x1FU) +#define CAN_REGIDX_BIT(regidx, bitpos) (((uint32_t)(regidx) << 6) | (uint32_t)(bitpos)) +#define CAN_REG_VAL(canx, offset) (REG32((canx) + ((uint32_t)(offset) >> 6))) +#define CAN_BIT_POS(val) ((uint32_t)(val) & 0x1FU) + +#define CAN_REGIDX_BITS(regidx, bitpos0, bitpos1) (((uint32_t)(regidx) << 12) | ((uint32_t)(bitpos0) << 6) | (uint32_t)(bitpos1)) +#define CAN_REG_VALS(canx, offset) (REG32((canx) + ((uint32_t)(offset) >> 12))) +#define CAN_BIT_POS0(val) (((uint32_t)(val) >> 6) & 0x1FU) +#define CAN_BIT_POS1(val) ((uint32_t)(val) & 0x1FU) /* register offset */ #define STAT_REG_OFFSET ((uint8_t)0x04U) /*!< STAT register offset */ @@ -296,45 +330,84 @@ /* CAN flags */ typedef enum { + /* flags in STAT register */ + CAN_FLAG_RXL = CAN_REGIDX_BIT(STAT_REG_OFFSET, 11U), /*!< RX level */ + CAN_FLAG_LASTRX = CAN_REGIDX_BIT(STAT_REG_OFFSET, 10U), /*!< last sample value of RX pin */ + CAN_FLAG_RS = CAN_REGIDX_BIT(STAT_REG_OFFSET, 9U), /*!< receiving state */ + CAN_FLAG_TS = CAN_REGIDX_BIT(STAT_REG_OFFSET, 8U), /*!< transmitting state */ + CAN_FLAG_SLPIF = CAN_REGIDX_BIT(STAT_REG_OFFSET, 4U), /*!< status change flag of entering sleep working mode */ + CAN_FLAG_WUIF = CAN_REGIDX_BIT(STAT_REG_OFFSET, 3U), /*!< status change flag of wakeup from sleep working mode */ + CAN_FLAG_ERRIF = CAN_REGIDX_BIT(STAT_REG_OFFSET, 2U), /*!< error flag */ + CAN_FLAG_SLPWS = CAN_REGIDX_BIT(STAT_REG_OFFSET, 1U), /*!< sleep working state */ + CAN_FLAG_IWS = CAN_REGIDX_BIT(STAT_REG_OFFSET, 0U), /*!< initial working state */ /* flags in TSTAT register */ - CAN_FLAG_MTE2 = CAN_REGIDX_BIT(TSTAT_REG_OFFSET, 19U), /*!< mailbox 2 transmit error */ - CAN_FLAG_MTE1 = CAN_REGIDX_BIT(TSTAT_REG_OFFSET, 11U), /*!< mailbox 1 transmit error */ - CAN_FLAG_MTE0 = CAN_REGIDX_BIT(TSTAT_REG_OFFSET, 3U), /*!< mailbox 0 transmit error */ - CAN_FLAG_MTF2 = CAN_REGIDX_BIT(TSTAT_REG_OFFSET, 16U), /*!< mailbox 2 transmit finished */ - CAN_FLAG_MTF1 = CAN_REGIDX_BIT(TSTAT_REG_OFFSET, 8U), /*!< mailbox 1 transmit finished */ - CAN_FLAG_MTF0 = CAN_REGIDX_BIT(TSTAT_REG_OFFSET, 0U), /*!< mailbox 0 transmit finished */ + CAN_FLAG_TMLS2 = CAN_REGIDX_BIT(TSTAT_REG_OFFSET, 31U), /*!< transmit mailbox 2 last sending in Tx FIFO */ + CAN_FLAG_TMLS1 = CAN_REGIDX_BIT(TSTAT_REG_OFFSET, 30U), /*!< transmit mailbox 1 last sending in Tx FIFO */ + CAN_FLAG_TMLS0 = CAN_REGIDX_BIT(TSTAT_REG_OFFSET, 29U), /*!< transmit mailbox 0 last sending in Tx FIFO */ + CAN_FLAG_TME2 = CAN_REGIDX_BIT(TSTAT_REG_OFFSET, 28U), /*!< transmit mailbox 2 empty */ + CAN_FLAG_TME1 = CAN_REGIDX_BIT(TSTAT_REG_OFFSET, 27U), /*!< transmit mailbox 1 empty */ + CAN_FLAG_TME0 = CAN_REGIDX_BIT(TSTAT_REG_OFFSET, 26U), /*!< transmit mailbox 0 empty */ + CAN_FLAG_MTE2 = CAN_REGIDX_BIT(TSTAT_REG_OFFSET, 19U), /*!< mailbox 2 transmit error */ + CAN_FLAG_MTE1 = CAN_REGIDX_BIT(TSTAT_REG_OFFSET, 11U), /*!< mailbox 1 transmit error */ + CAN_FLAG_MTE0 = CAN_REGIDX_BIT(TSTAT_REG_OFFSET, 3U), /*!< mailbox 0 transmit error */ + CAN_FLAG_MAL2 = CAN_REGIDX_BIT(TSTAT_REG_OFFSET, 18U), /*!< mailbox 2 arbitration lost */ + CAN_FLAG_MAL1 = CAN_REGIDX_BIT(TSTAT_REG_OFFSET, 10U), /*!< mailbox 1 arbitration lost */ + CAN_FLAG_MAL0 = CAN_REGIDX_BIT(TSTAT_REG_OFFSET, 2U), /*!< mailbox 0 arbitration lost */ + CAN_FLAG_MTFNERR2 = CAN_REGIDX_BIT(TSTAT_REG_OFFSET, 17U), /*!< mailbox 2 transmit finished with no error */ + CAN_FLAG_MTFNERR1 = CAN_REGIDX_BIT(TSTAT_REG_OFFSET, 9U), /*!< mailbox 1 transmit finished with no error */ + CAN_FLAG_MTFNERR0 = CAN_REGIDX_BIT(TSTAT_REG_OFFSET, 1U), /*!< mailbox 0 transmit finished with no error */ + CAN_FLAG_MTF2 = CAN_REGIDX_BIT(TSTAT_REG_OFFSET, 16U), /*!< mailbox 2 transmit finished */ + CAN_FLAG_MTF1 = CAN_REGIDX_BIT(TSTAT_REG_OFFSET, 8U), /*!< mailbox 1 transmit finished */ + CAN_FLAG_MTF0 = CAN_REGIDX_BIT(TSTAT_REG_OFFSET, 0U), /*!< mailbox 0 transmit finished */ /* flags in RFIFO0 register */ - CAN_FLAG_RFO0 = CAN_REGIDX_BIT(RFIFO0_REG_OFFSET, 4U), /*!< receive FIFO0 overfull */ - CAN_FLAG_RFF0 = CAN_REGIDX_BIT(RFIFO0_REG_OFFSET, 3U), /*!< receive FIFO0 full */ + CAN_FLAG_RFO0 = CAN_REGIDX_BIT(RFIFO0_REG_OFFSET, 4U), /*!< receive FIFO0 overfull */ + CAN_FLAG_RFF0 = CAN_REGIDX_BIT(RFIFO0_REG_OFFSET, 3U), /*!< receive FIFO0 full */ /* flags in RFIFO1 register */ - CAN_FLAG_RFO1 = CAN_REGIDX_BIT(RFIFO1_REG_OFFSET, 4U), /*!< receive FIFO1 overfull */ - CAN_FLAG_RFF1 = CAN_REGIDX_BIT(RFIFO1_REG_OFFSET, 3U), /*!< receive FIFO1 full */ + CAN_FLAG_RFO1 = CAN_REGIDX_BIT(RFIFO1_REG_OFFSET, 4U), /*!< receive FIFO1 overfull */ + CAN_FLAG_RFF1 = CAN_REGIDX_BIT(RFIFO1_REG_OFFSET, 3U), /*!< receive FIFO1 full */ /* flags in ERR register */ - CAN_FLAG_BOERR = CAN_REGIDX_BIT(ERR_REG_OFFSET, 2U), /*!< bus-off error */ - CAN_FLAG_PERR = CAN_REGIDX_BIT(ERR_REG_OFFSET, 1U), /*!< passive error */ - CAN_FLAG_WERR = CAN_REGIDX_BIT(ERR_REG_OFFSET, 0U), /*!< warning error */ + CAN_FLAG_BOERR = CAN_REGIDX_BIT(ERR_REG_OFFSET, 2U), /*!< bus-off error */ + CAN_FLAG_PERR = CAN_REGIDX_BIT(ERR_REG_OFFSET, 1U), /*!< passive error */ + CAN_FLAG_WERR = CAN_REGIDX_BIT(ERR_REG_OFFSET, 0U), /*!< warning error */ }can_flag_enum; /* CAN interrupt flags */ typedef enum { /* interrupt flags in STAT register */ - CAN_INT_SLPIF = CAN_REGIDX_BIT(STAT_REG_OFFSET, 4U), /*!< status change interrupt flag of sleep working mode entering */ - CAN_INT_WUIF = CAN_REGIDX_BIT(STAT_REG_OFFSET, 3U), /*!< status change interrupt flag of wakeup from sleep working mode */ - CAN_INT_ERRIF = CAN_REGIDX_BIT(STAT_REG_OFFSET, 2U), /*!< error interrupt flag */ + CAN_INT_FLAG_SLPIF = CAN_REGIDX_BITS(STAT_REG_OFFSET, 4U, 17U), /*!< status change interrupt flag of sleep working mode entering */ + CAN_INT_FLAG_WUIF = CAN_REGIDX_BITS(STAT_REG_OFFSET, 3U, 16), /*!< status change interrupt flag of wakeup from sleep working mode */ + CAN_INT_FLAG_ERRIF = CAN_REGIDX_BITS(STAT_REG_OFFSET, 2U, 15), /*!< error interrupt flag */ + /* interrupt flags in TSTAT register */ + CAN_INT_FLAG_MTF2 = CAN_REGIDX_BITS(TSTAT_REG_OFFSET, 16U, 0U), /*!< mailbox 2 transmit finished interrupt flag */ + CAN_INT_FLAG_MTF1 = CAN_REGIDX_BITS(TSTAT_REG_OFFSET, 8U, 0U), /*!< mailbox 1 transmit finished interrupt flag */ + CAN_INT_FLAG_MTF0 = CAN_REGIDX_BITS(TSTAT_REG_OFFSET, 0U, 0U), /*!< mailbox 0 transmit finished interrupt flag */ + /* interrupt flags in RFIFO0 register */ + CAN_INT_FLAG_RFO0 = CAN_REGIDX_BITS(RFIFO0_REG_OFFSET, 4U, 3U), /*!< receive FIFO0 overfull interrupt flag */ + CAN_INT_FLAG_RFF0 = CAN_REGIDX_BITS(RFIFO0_REG_OFFSET, 3U, 2U), /*!< receive FIFO0 full interrupt flag */ + CAN_INT_FLAG_RFL0 = CAN_REGIDX_BITS(RFIFO0_REG_OFFSET, 2U, 1U), /*!< receive FIFO0 not empty interrupt flag */ + /* interrupt flags in RFIFO0 register */ + CAN_INT_FLAG_RFO1 = CAN_REGIDX_BITS(RFIFO1_REG_OFFSET, 4U, 6U), /*!< receive FIFO1 overfull interrupt flag */ + CAN_INT_FLAG_RFF1 = CAN_REGIDX_BITS(RFIFO1_REG_OFFSET, 3U, 5U), /*!< receive FIFO1 full interrupt flag */ + CAN_INT_FLAG_RFL1 = CAN_REGIDX_BITS(RFIFO1_REG_OFFSET, 2U, 4U), /*!< receive FIFO0 not empty interrupt flag */ + /* interrupt flags in ERR register */ + CAN_INT_FLAG_ERRN = CAN_REGIDX_BITS(ERR_REG_OFFSET, 3U, 11U), /*!< error number interrupt flag */ + CAN_INT_FLAG_BOERR = CAN_REGIDX_BITS(ERR_REG_OFFSET, 2U, 10U), /*!< bus-off error interrupt flag */ + CAN_INT_FLAG_PERR = CAN_REGIDX_BITS(ERR_REG_OFFSET, 1U, 9U), /*!< passive error interrupt flag */ + CAN_INT_FLAG_WERR = CAN_REGIDX_BITS(ERR_REG_OFFSET, 0U, 8U), /*!< warning error interrupt flag */ }can_interrupt_flag_enum; /* CAN initiliaze parameters struct */ typedef struct { - uint8_t working_mode; /*!< CAN working mode */ + uint8_t working_mode; /*!< CAN working mode */ uint8_t resync_jump_width; /*!< CAN resynchronization jump width */ uint8_t time_segment_1; /*!< time segment 1 */ uint8_t time_segment_2; /*!< time segment 2 */ ControlStatus time_triggered; /*!< time triggered communication mode */ ControlStatus auto_bus_off_recovery; /*!< automatic bus-off recovery */ ControlStatus auto_wake_up; /*!< automatic wake-up mode */ - ControlStatus auto_retrans; /*!< automatic retransmission mode */ + ControlStatus no_auto_retrans; /*!< automatic retransmission mode disable */ ControlStatus rec_fifo_overwrite; /*!< receive FIFO overwrite mode */ ControlStatus trans_fifo_order; /*!< transmit FIFO order */ uint16_t prescaler; /*!< baudrate prescaler */ @@ -387,18 +460,26 @@ typedef enum CAN_ERROR_BITRECESSIVE, /*!< bit recessive error */ CAN_ERROR_BITDOMINANTER, /*!< bit dominant error */ CAN_ERROR_CRC, /*!< CRC error */ - CAN_ERROR_SOFTWARECFG /*!< software configure */ + CAN_ERROR_SOFTWARECFG, /*!< software configure */ }can_error_enum; /* transmit states */ typedef enum { - CAN_TRANSMIT_FAILED = 0, /*!< CAN transmitted failure */ - CAN_TRANSMIT_OK = 1, /*!< CAN transmitted success */ - CAN_TRANSMIT_PENDING = 2, /*!< CAN transmitted pending */ - CAN_TRANSMIT_NOMAILBOX = 4, /*!< no empty mailbox to be used for CAN */ + CAN_TRANSMIT_FAILED = 0U, /*!< CAN transmitted failure */ + CAN_TRANSMIT_OK = 1U, /*!< CAN transmitted success */ + CAN_TRANSMIT_PENDING = 2U, /*!< CAN transmitted pending */ + CAN_TRANSMIT_NOMAILBOX = 4U, /*!< no empty mailbox to be used for CAN */ }can_transmit_state_enum; +typedef enum +{ + CAN_INIT_STRUCT = 0, /* CAN initiliaze parameters struct */ + CAN_FILTER_STRUCT, /* CAN filter parameters struct */ + CAN_TX_MESSAGE_STRUCT, /* CAN transmit message struct */ + CAN_RX_MESSAGE_STRUCT, /* CAN receive message struct */ +}can_struct_type_enum; + /* CAN baudrate prescaler*/ #define BT_BAUDPSC(regval) (BITS(0,9) & ((uint32_t)(regval) << 0)) @@ -438,66 +519,76 @@ typedef enum /* transmit data byte 2 */ #define TMDATA0_DB2(regval) (BITS(16,23) & ((uint32_t)(regval) << 16)) -/* transmit data byte 3 */ +/* transmit data byte 3 */ #define TMDATA0_DB3(regval) (BITS(24,31) & ((uint32_t)(regval) << 24)) -/* transmit data byte 4 */ +/* transmit data byte 4 */ #define TMDATA1_DB4(regval) (BITS(0,7) & ((uint32_t)(regval) << 0)) -/* transmit data byte 5 */ +/* transmit data byte 5 */ #define TMDATA1_DB5(regval) (BITS(8,15) & ((uint32_t)(regval) << 8)) -/* transmit data byte 6 */ +/* transmit data byte 6 */ #define TMDATA1_DB6(regval) (BITS(16,23) & ((uint32_t)(regval) << 16)) -/* transmit data byte 7 */ +/* transmit data byte 7 */ #define TMDATA1_DB7(regval) (BITS(24,31) & ((uint32_t)(regval) << 24)) /* receive mailbox extended identifier*/ -#define RFIFOMI_EFID(regval) GET_BITS((uint32_t)(regval), 3, 31) +#define GET_RFIFOMI_EFID(regval) GET_BITS((uint32_t)(regval), 3U, 31U) /* receive mailbox standrad identifier*/ -#define RFIFOMI_SFID(regval) GET_BITS((uint32_t)(regval), 21, 31) +#define GET_RFIFOMI_SFID(regval) GET_BITS((uint32_t)(regval), 21U, 31U) /* receive data length */ -#define RFIFOMP_DLENC(regval) GET_BITS((uint32_t)(regval), 0, 3) +#define GET_RFIFOMP_DLENC(regval) GET_BITS((uint32_t)(regval), 0U, 3U) -#define RFIFOMP_FI(regval) GET_BITS((uint32_t)(regval), 8, 15) +/* the index of the filter by which the frame is passed */ +#define GET_RFIFOMP_FI(regval) GET_BITS((uint32_t)(regval), 8U, 15U) /* receive data byte 0 */ -#define RFIFOMDATA0_DB0(regval) GET_BITS((uint32_t)(regval), 0, 7) +#define GET_RFIFOMDATA0_DB0(regval) GET_BITS((uint32_t)(regval), 0U, 7U) /* receive data byte 1 */ -#define RFIFOMDATA0_DB1(regval) GET_BITS((uint32_t)(regval), 8, 15) +#define GET_RFIFOMDATA0_DB1(regval) GET_BITS((uint32_t)(regval), 8U, 15U) /* receive data byte 2 */ -#define RFIFOMDATA0_DB2(regval) GET_BITS((uint32_t)(regval), 16, 23) +#define GET_RFIFOMDATA0_DB2(regval) GET_BITS((uint32_t)(regval), 16U, 23U) /* receive data byte 3 */ -#define RFIFOMDATA0_DB3(regval) GET_BITS((uint32_t)(regval), 24, 31) +#define GET_RFIFOMDATA0_DB3(regval) GET_BITS((uint32_t)(regval), 24U, 31U) /* receive data byte 4 */ -#define RFIFOMDATA1_DB4(regval) GET_BITS((uint32_t)(regval), 0, 7) +#define GET_RFIFOMDATA1_DB4(regval) GET_BITS((uint32_t)(regval), 0U, 7U) /* receive data byte 5 */ -#define RFIFOMDATA1_DB5(regval) GET_BITS((uint32_t)(regval), 8, 15) +#define GET_RFIFOMDATA1_DB5(regval) GET_BITS((uint32_t)(regval), 8U, 15U) /* receive data byte 6 */ -#define RFIFOMDATA1_DB6(regval) GET_BITS((uint32_t)(regval), 16, 23) +#define GET_RFIFOMDATA1_DB6(regval) GET_BITS((uint32_t)(regval), 16U, 23U) /* receive data byte 7 */ -#define RFIFOMDATA1_DB7(regval) GET_BITS((uint32_t)(regval), 24, 31) +#define GET_RFIFOMDATA1_DB7(regval) GET_BITS((uint32_t)(regval), 24U, 31U) + +/* error number */ +#define GET_ERR_ERRN(regval) GET_BITS((uint32_t)(regval), 4U, 6U) + +/* transmit error count */ +#define GET_ERR_TECNT(regval) GET_BITS((uint32_t)(regval), 16U, 23U) + +/* receive error count */ +#define GET_ERR_RECNT(regval) GET_BITS((uint32_t)(regval), 24U, 31U) /* CAN errors */ #define ERR_ERRN(regval) (BITS(4,6) & ((uint32_t)(regval) << 4)) -#define CAN_ERRN_0 ERR_ERRN(0) /* no error */ -#define CAN_ERRN_1 ERR_ERRN(1) /*!< fill error */ -#define CAN_ERRN_2 ERR_ERRN(2) /*!< format error */ -#define CAN_ERRN_3 ERR_ERRN(3) /*!< ACK error */ -#define CAN_ERRN_4 ERR_ERRN(4) /*!< bit recessive error */ -#define CAN_ERRN_5 ERR_ERRN(5) /*!< bit dominant error */ -#define CAN_ERRN_6 ERR_ERRN(6) /*!< CRC error */ -#define CAN_ERRN_7 ERR_ERRN(7) /*!< software error */ +#define CAN_ERRN_0 ERR_ERRN(0U) /* no error */ +#define CAN_ERRN_1 ERR_ERRN(1U) /*!< fill error */ +#define CAN_ERRN_2 ERR_ERRN(2U) /*!< format error */ +#define CAN_ERRN_3 ERR_ERRN(3U) /*!< ACK error */ +#define CAN_ERRN_4 ERR_ERRN(4U) /*!< bit recessive error */ +#define CAN_ERRN_5 ERR_ERRN(5U) /*!< bit dominant error */ +#define CAN_ERRN_6 ERR_ERRN(6U) /*!< CRC error */ +#define CAN_ERRN_7 ERR_ERRN(7U) /*!< software error */ #define CAN_STATE_PENDING ((uint32_t)0x00000000U) /*!< CAN pending */ @@ -556,7 +647,7 @@ typedef enum #define CAN_FIFO1 ((uint8_t)0x01U) /*!< receive FIFO1 */ /* frame number of receive fifo */ -#define CAN_RFIFO_RFL0_MASK ((uint32_t)0x00000003U) /*!< mask for frame number in receive FIFO0 */ +#define CAN_RFIF_RFL_MASK ((uint32_t)0x00000003U) /*!< mask for frame number in receive FIFOx */ #define CAN_SFID_MASK ((uint32_t)0x000007FFU) /*!< mask of standard identifier */ #define CAN_EFID_MASK ((uint32_t)0x1FFFFFFFU) /*!< mask of extended identifier */ @@ -575,7 +666,7 @@ typedef enum #define CAN_FILTERMODE_LIST ((uint8_t)0x01U) /*!< list mode */ /* filter 16 bits mask */ -#define CAN_FILTER_MASK_16BITS ((uint32_t)0x0000FFFFU) +#define CAN_FILTER_MASK_16BITS ((uint32_t)0x0000FFFFU) /*!< can filter 16 bits mask */ /* frame type */ #define CAN_FT_DATA ((uint32_t)0x00000000U) /*!< data frame */ @@ -584,62 +675,72 @@ typedef enum /* CAN timeout */ #define CAN_TIMEOUT ((uint32_t)0x0000FFFFU) /*!< timeout value */ +/* interrupt enable bits */ +#define CAN_INT_TME CAN_INTEN_TMEIE /*!< transmit mailbox empty interrupt enable */ +#define CAN_INT_RFNE0 CAN_INTEN_RFNEIE0 /*!< receive FIFO0 not empty interrupt enable */ +#define CAN_INT_RFF0 CAN_INTEN_RFFIE0 /*!< receive FIFO0 full interrupt enable */ +#define CAN_INT_RFO0 CAN_INTEN_RFOIE0 /*!< receive FIFO0 overfull interrupt enable */ +#define CAN_INT_RFNE1 CAN_INTEN_RFNEIE1 /*!< receive FIFO1 not empty interrupt enable */ +#define CAN_INT_RFF1 CAN_INTEN_RFFIE1 /*!< receive FIFO1 full interrupt enable */ +#define CAN_INT_RFO1 CAN_INTEN_RFOIE1 /*!< receive FIFO1 overfull interrupt enable */ +#define CAN_INT_WERR CAN_INTEN_WERRIE /*!< warning error interrupt enable */ +#define CAN_INT_PERR CAN_INTEN_PERRIE /*!< passive error interrupt enable */ +#define CAN_INT_BO CAN_INTEN_BOIE /*!< bus-off interrupt enable */ +#define CAN_INT_ERRN CAN_INTEN_ERRNIE /*!< error number interrupt enable */ +#define CAN_INT_ERR CAN_INTEN_ERRIE /*!< error interrupt enable */ +#define CAN_INT_WAKEUP CAN_INTEN_WIE /*!< wakeup interrupt enable */ +#define CAN_INT_SLPW CAN_INTEN_SLPWIE /*!< sleep working interrupt enable */ + /* function declarations */ -/* initialization functions */ -/* CAN deinit */ +/* deinitialize CAN */ void can_deinit(uint32_t can_periph); -/* CAN init */ +/* initialize CAN struct */ +void can_struct_para_init(can_struct_type_enum type, void* p_struct); +/* initialize CAN */ ErrStatus can_init(uint32_t can_periph, can_parameter_struct* can_parameter_init); - -/* transmit functions */ -/* CAN transmit message */ -uint8_t can_message_transmit(uint32_t can_periph, can_trasnmit_message_struct* transmit_message); -/* CAN transmit state */ -can_transmit_state_enum can_transmit_states(uint32_t can_periph, uint8_t mailbox_number); -/* CAN stop transmission */ -void can_transmission_stop(uint32_t can_periph, uint8_t mailbox_number); -/* CAN transmit error number */ -uint8_t can_transmit_error_number(uint32_t can_periph); - -/* filter functions */ /* CAN filter init */ void can_filter_init(can_filter_parameter_struct* can_filter_parameter_init); /* set can1 fliter start bank number */ void can1_filter_start_bank(uint8_t start_bank); - /* enable functions */ /* CAN debug freeze enable */ void can_debug_freeze_enable(uint32_t can_periph); /* CAN debug freeze disable */ void can_debug_freeze_disable(uint32_t can_periph); -/* CAN time triggle mode enable */ +/* CAN time trigger mode enable */ void can_time_trigger_mode_enable(uint32_t can_periph); -/* CAN time triggle mode disable */ +/* CAN time trigger mode disable */ void can_time_trigger_mode_disable(uint32_t can_periph); -/* CAN interrupt enable */ -void can_interrupt_enable(uint32_t can_periph, uint32_t interrupt); -/* CAN interrupt disable */ -void can_interrupt_disable(uint32_t can_periph, uint32_t interrupt); -/* receive functions */ +/* transmit functions */ +/* transmit CAN message */ +uint8_t can_message_transmit(uint32_t can_periph, can_trasnmit_message_struct* transmit_message); +/* get CAN transmit state */ +can_transmit_state_enum can_transmit_states(uint32_t can_periph, uint8_t mailbox_number); +/* stop CAN transmission */ +void can_transmission_stop(uint32_t can_periph, uint8_t mailbox_number); /* CAN receive message */ void can_message_receive(uint32_t can_periph, uint8_t fifo_number, can_receive_message_struct* receive_message); /* CAN release fifo */ void can_fifo_release(uint32_t can_periph, uint8_t fifo_number); /* CAN receive message length */ -uint8_t can_receive_message_length(uint32_t can_periph, uint8_t fifo_number); -/* CAN receive error number */ -uint8_t can_receive_error_number(uint32_t can_periph); - -/* mode functions */ +uint8_t can_receive_message_length_get(uint32_t can_periph, uint8_t fifo_number); /* CAN working mode */ ErrStatus can_working_mode_set(uint32_t can_periph, uint8_t working_mode); /* CAN wakeup from sleep mode */ ErrStatus can_wakeup(uint32_t can_periph); -/* flag functions */ /* CAN get error */ can_error_enum can_error_get(uint32_t can_periph); +/* get CAN receive error number */ +uint8_t can_receive_error_number_get(uint32_t can_periph); +/* get CAN transmit error number */ +uint8_t can_transmit_error_number_get(uint32_t can_periph); + +/* CAN interrupt enable */ +void can_interrupt_enable(uint32_t can_periph, uint32_t interrupt); +/* CAN interrupt disable */ +void can_interrupt_disable(uint32_t can_periph, uint32_t interrupt); /* CAN get flag state */ FlagStatus can_flag_get(uint32_t can_periph, can_flag_enum flag); /* CAN clear flag state */ diff --git a/bsp/gd32450z-eval/Libraries/GD32F4xx_standard_peripheral/Include/gd32f4xx_crc.h b/bsp/gd32450z-eval/Libraries/GD32F4xx_standard_peripheral/Include/gd32f4xx_crc.h index 983dd944a5..01f2c6bc3f 100644 --- a/bsp/gd32450z-eval/Libraries/GD32F4xx_standard_peripheral/Include/gd32f4xx_crc.h +++ b/bsp/gd32450z-eval/Libraries/GD32F4xx_standard_peripheral/Include/gd32f4xx_crc.h @@ -1,12 +1,37 @@ /*! - \file gd32f4xx_crc.h - \brief definitions for the CRC + \file gd32f4xx_crc.h + \brief definitions for the CRC + + \version 2016-08-15, V1.0.0, firmware for GD32F4xx + \version 2018-12-12, V2.0.0, firmware for GD32F4xx + \version 2020-09-30, V2.1.0, firmware for GD32F4xx */ /* - Copyright (C) 2016 GigaDevice + Copyright (c) 2020, GigaDevice Semiconductor Inc. + + Redistribution and use in source and binary forms, with or without modification, +are permitted provided that the following conditions are met: + + 1. Redistributions of source code must retain the above copyright notice, this + list of conditions and the following disclaimer. + 2. Redistributions in binary form must reproduce the above copyright notice, + this list of conditions and the following disclaimer in the documentation + and/or other materials provided with the distribution. + 3. Neither the name of the copyright holder nor the names of its contributors + may be used to endorse or promote products derived from this software without + specific prior written permission. - 2016-08-15, V1.0.0, firmware for GD32F4xx + THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED +WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. +IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, +INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT +NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR +PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, +WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY +OF SUCH DAMAGE. */ #ifndef GD32F4XX_CRC_H @@ -37,19 +62,19 @@ /* deinit CRC calculation unit */ void crc_deinit(void); -/* reset data register to the value of initializaiton data register */ +/* reset data register(CRC_DATA) to the value of 0xFFFFFFFF */ void crc_data_register_reset(void); -/* read the data register */ +/* read the value of the data register */ uint32_t crc_data_register_read(void); -/* read the free data register */ +/* read the value of the free data register */ uint8_t crc_free_data_register_read(void); -/* write the free data register */ +/* write data to the free data register */ void crc_free_data_register_write(uint8_t free_data); -/* CRC calculate a 32-bit data */ +/* calculate the CRC value of a 32-bit data */ uint32_t crc_single_data_calculate(uint32_t sdata); -/* CRC calculate a 32-bit data array */ +/* calculate the CRC value of an array of 32-bit values */ uint32_t crc_block_data_calculate(uint32_t array[], uint32_t size); #endif /* GD32F4XX_CRC_H */ diff --git a/bsp/gd32450z-eval/Libraries/GD32F4xx_standard_peripheral/Include/gd32f4xx_ctc.h b/bsp/gd32450z-eval/Libraries/GD32F4xx_standard_peripheral/Include/gd32f4xx_ctc.h index 605d5530d5..00e4e7f298 100644 --- a/bsp/gd32450z-eval/Libraries/GD32F4xx_standard_peripheral/Include/gd32f4xx_ctc.h +++ b/bsp/gd32450z-eval/Libraries/GD32F4xx_standard_peripheral/Include/gd32f4xx_ctc.h @@ -1,12 +1,37 @@ /*! - \file gd32f4xx_ctc.h - \brief definitions for the CTC + \file gd32f4xx_ctc.h + \brief definitions for the CTC + + \version 2016-08-15, V1.0.0, firmware for GD32F4xx + \version 2018-12-12, V2.0.0, firmware for GD32F4xx + \version 2020-09-30, V2.1.0, firmware for GD32F4xx */ /* - Copyright (C) 2016 GigaDevice + Copyright (c) 2020, GigaDevice Semiconductor Inc. + + Redistribution and use in source and binary forms, with or without modification, +are permitted provided that the following conditions are met: + + 1. Redistributions of source code must retain the above copyright notice, this + list of conditions and the following disclaimer. + 2. Redistributions in binary form must reproduce the above copyright notice, + this list of conditions and the following disclaimer in the documentation + and/or other materials provided with the distribution. + 3. Neither the name of the copyright holder nor the names of its contributors + may be used to endorse or promote products derived from this software without + specific prior written permission. - 2016-08-15, V1.0.0, firmware for GD32F4xx + THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED +WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. +IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, +INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT +NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR +PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, +WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY +OF SUCH DAMAGE. */ #ifndef GD32F4XX_CTC_H @@ -25,7 +50,7 @@ /* bits definitions */ /* CTC_CTL0 */ -#define CTC_CTL0_CKOKIE BIT(0) /*!< clock trim OK(CKOKIF) interrupt enable */ +#define CTC_CTL0_CKOKIE BIT(0) /*!< clock trim OK(CKOKIF) interrupt enable */ #define CTC_CTL0_CKWARNIE BIT(1) /*!< clock trim warning(CKWARNIF) interrupt enable */ #define CTC_CTL0_ERRIE BIT(2) /*!< error(ERRIF) interrupt enable */ #define CTC_CTL0_EREFIE BIT(3) /*!< EREFIF interrupt enable */ @@ -90,19 +115,19 @@ #define CTC_REFSOURCE_PSC_DIV128 CTL1_REFPSC(7) /*!< reference signal divided by 128 */ /* CTC interrupt enable definitions */ -#define CTC_INT_CKOKIE CTC_CTL0_CKOKIE /*!< clock trim OK interrupt enable */ -#define CTC_INT_CKWARNIE CTC_CTL0_CKWARNIE /*!< clock trim warning interrupt enable */ -#define CTC_INT_ERRIE CTC_CTL0_ERRIE /*!< error interrupt enable */ -#define CTC_INT_EREFIE CTC_CTL0_EREFIE /*!< expect reference interrupt enable */ +#define CTC_INT_CKOK CTC_CTL0_CKOKIE /*!< clock trim OK interrupt enable */ +#define CTC_INT_CKWARN CTC_CTL0_CKWARNIE /*!< clock trim warning interrupt enable */ +#define CTC_INT_ERR CTC_CTL0_ERRIE /*!< error interrupt enable */ +#define CTC_INT_EREF CTC_CTL0_EREFIE /*!< expect reference interrupt enable */ /* CTC interrupt source definitions */ -#define CTC_INT_CKOK CTC_STAT_CKOKIF /*!< clock trim OK interrupt flag */ -#define CTC_INT_CKWARN CTC_STAT_CKWARNIF /*!< clock trim warning interrupt flag */ -#define CTC_INT_ERR CTC_STAT_ERRIF /*!< error interrupt flag */ -#define CTC_INT_EREF CTC_STAT_EREFIF /*!< expect reference interrupt flag */ -#define CTC_INT_CKERR CTC_STAT_CKERR /*!< clock trim error bit */ -#define CTC_INT_REFMISS CTC_STAT_REFMISS /*!< reference sync pulse miss */ -#define CTC_INT_TRIMERR CTC_STAT_TRIMERR /*!< trim value error */ +#define CTC_INT_FLAG_CKOK CTC_STAT_CKOKIF /*!< clock trim OK interrupt flag */ +#define CTC_INT_FLAG_CKWARN CTC_STAT_CKWARNIF /*!< clock trim warning interrupt flag */ +#define CTC_INT_FLAG_ERR CTC_STAT_ERRIF /*!< error interrupt flag */ +#define CTC_INT_FLAG_EREF CTC_STAT_EREFIF /*!< expect reference interrupt flag */ +#define CTC_INT_FLAG_CKERR CTC_STAT_CKERR /*!< clock trim error bit */ +#define CTC_INT_FLAG_REFMISS CTC_STAT_REFMISS /*!< reference sync pulse miss */ +#define CTC_INT_FLAG_TRIMERR CTC_STAT_TRIMERR /*!< trim value error */ /* CTC flag definitions */ #define CTC_FLAG_CKOK CTC_STAT_CKOKIF /*!< clock trim OK flag */ @@ -116,45 +141,30 @@ /* function declarations */ /* reset ctc clock trim controller */ void ctc_deinit(void); - -/* enable the CTC interrupt */ -void ctc_interrupt_enable(uint32_t ctc_interrupt); -/* disable the CTC interrupt */ -void ctc_interrupt_disable(uint32_t ctc_interrupt); -/* get CTC interrupt flag */ -FlagStatus ctc_interrupt_flag_get(uint32_t ctc_interrupt); -/* clear CTC interrupt flag */ -void ctc_interrupt_flag_clear(uint32_t ctc_interrupt); - -/* get CTC flag */ -FlagStatus ctc_flag_get(uint32_t ctc_flag); -/* clear CTC flag */ -void ctc_flag_clear(uint32_t ctc_flag); +/* enable CTC trim counter */ +void ctc_counter_enable(void); +/* disable CTC trim counter */ +void ctc_counter_disable(void); /* configure the IRC48M trim value */ -void ctc_irc48m_trim_value_config(uint8_t ctc_trim_value); +void ctc_irc48m_trim_value_config(uint8_t trim_value); /* generate software reference source sync pulse */ void ctc_software_refsource_pulse_generate(void); /* configure hardware automatically trim mode */ -void ctc_hardware_trim_mode_config(uint32_t ctc_hardmode); - -/* enable CTC counter */ -void ctc_counter_enable(void); -/* disable CTC counter */ -void ctc_counter_disable(void); +void ctc_hardware_trim_mode_config(uint32_t hardmode); /* configure reference signal source polarity */ -void ctc_refsource_polarity_config(uint32_t ctc_polarity); +void ctc_refsource_polarity_config(uint32_t polarity); /* select USBFS or USBHS SOF signal */ -void ctc_usbsof_signal_select(uint32_t ctc_usbsof); +void ctc_usbsof_signal_select(uint32_t usbsof); /* select reference signal source */ -void ctc_refsource_signal_select(uint32_t ctc_refs); +void ctc_refsource_signal_select(uint32_t refs); /* configure reference signal source prescaler */ -void ctc_refsource_prescaler_config(uint32_t ctc_prescaler); +void ctc_refsource_prescaler_config(uint32_t prescaler); /* configure clock trim base limit value */ -void ctc_clock_limit_value_config(uint8_t ctc_limit_value); +void ctc_clock_limit_value_config(uint8_t limit_value); /* configure CTC counter reload value */ -void ctc_counter_reload_value_config(uint16_t ctc_reload_value); +void ctc_counter_reload_value_config(uint16_t reload_value); /* read CTC counter capture value when reference sync pulse occurred */ uint16_t ctc_counter_capture_value_read(void); @@ -165,4 +175,18 @@ uint16_t ctc_counter_reload_value_read(void); /* read the IRC48M trim value */ uint8_t ctc_irc48m_trim_value_read(void); +/* interrupt & flag functions */ +/* enable the CTC interrupt */ +void ctc_interrupt_enable(uint32_t interrupt); +/* disable the CTC interrupt */ +void ctc_interrupt_disable(uint32_t interrupt); +/* get CTC interrupt flag */ +FlagStatus ctc_interrupt_flag_get(uint32_t int_flag); +/* clear CTC interrupt flag */ +void ctc_interrupt_flag_clear(uint32_t int_flag); +/* get CTC flag */ +FlagStatus ctc_flag_get(uint32_t flag); +/* clear CTC flag */ +void ctc_flag_clear(uint32_t flag); + #endif /* GD32F4XX_CTC_H */ diff --git a/bsp/gd32450z-eval/Libraries/GD32F4xx_standard_peripheral/Include/gd32f4xx_dac.h b/bsp/gd32450z-eval/Libraries/GD32F4xx_standard_peripheral/Include/gd32f4xx_dac.h index 8a668fcc0c..573fb31336 100644 --- a/bsp/gd32450z-eval/Libraries/GD32F4xx_standard_peripheral/Include/gd32f4xx_dac.h +++ b/bsp/gd32450z-eval/Libraries/GD32F4xx_standard_peripheral/Include/gd32f4xx_dac.h @@ -1,12 +1,37 @@ /*! - \file gd32f4xx_dac.h - \brief definitions for the DAC + \file gd32f4xx_dac.h + \brief definitions for the DAC + + \version 2016-08-15, V1.0.0, firmware for GD32F4xx + \version 2018-12-12, V2.0.0, firmware for GD32F4xx + \version 2020-09-30, V2.1.0, firmware for GD32F4xx */ /* - Copyright (C) 2016 GigaDevice + Copyright (c) 2020, GigaDevice Semiconductor Inc. + + Redistribution and use in source and binary forms, with or without modification, +are permitted provided that the following conditions are met: - 2016-08-15, V1.0.0, firmware for GD32F4xx + 1. Redistributions of source code must retain the above copyright notice, this + list of conditions and the following disclaimer. + 2. Redistributions in binary form must reproduce the above copyright notice, + this list of conditions and the following disclaimer in the documentation + and/or other materials provided with the distribution. + 3. Neither the name of the copyright holder nor the names of its contributors + may be used to endorse or promote products derived from this software without + specific prior written permission. + + THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED +WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. +IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, +INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT +NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR +PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, +WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY +OF SUCH DAMAGE. */ #ifndef GD32F4XX_DAC_H @@ -20,152 +45,153 @@ #define DAC1 1U /* registers definitions */ -#define DAC_CTL REG32(DAC + 0x00U) /*!< DAC control register */ -#define DAC_SWT REG32(DAC + 0x04U) /*!< DAC software trigger register */ -#define DAC0_R12DH REG32(DAC + 0x08U) /*!< DAC0 12-bit right-aligned data holding register */ -#define DAC0_L12DH REG32(DAC + 0x0CU) /*!< DAC0 12-bit left-aligned data holding register */ -#define DAC0_R8DH REG32(DAC + 0x10U) /*!< DAC0 8-bit right-aligned data holding register */ -#define DAC1_R12DH REG32(DAC + 0x14U) /*!< DAC1 12-bit right-aligned data holding register */ -#define DAC1_L12DH REG32(DAC + 0x18U) /*!< DAC1 12-bit left-aligned data holding register */ -#define DAC1_R8DH REG32(DAC + 0x1CU) /*!< DAC1 8-bit right-aligned data holding register */ -#define DACC_R12DH REG32(DAC + 0x20U) /*!< DAC concurrent mode 12-bit right-aligned data holding register */ -#define DACC_L12DH REG32(DAC + 0x24U) /*!< DAC concurrent mode 12-bit left-aligned data holding register */ -#define DACC_R8DH REG32(DAC + 0x28U) /*!< DAC concurrent mode 8-bit right-aligned data holding register */ -#define DAC0_DO REG32(DAC + 0x2CU) /*!< DAC0 data output register */ -#define DAC1_DO REG32(DAC + 0x30U) /*!< DAC1 data output register */ -#define DAC_STAT REG32(DAC + 0x34U) /*!< DAC status register */ +#define DAC_CTL REG32(DAC + 0x00U) /*!< DAC control register */ +#define DAC_SWT REG32(DAC + 0x04U) /*!< DAC software trigger register */ +#define DAC0_R12DH REG32(DAC + 0x08U) /*!< DAC0 12-bit right-aligned data holding register */ +#define DAC0_L12DH REG32(DAC + 0x0CU) /*!< DAC0 12-bit left-aligned data holding register */ +#define DAC0_R8DH REG32(DAC + 0x10U) /*!< DAC0 8-bit right-aligned data holding register */ +#define DAC1_R12DH REG32(DAC + 0x14U) /*!< DAC1 12-bit right-aligned data holding register */ +#define DAC1_L12DH REG32(DAC + 0x18U) /*!< DAC1 12-bit left-aligned data holding register */ +#define DAC1_R8DH REG32(DAC + 0x1CU) /*!< DAC1 8-bit right-aligned data holding register */ +#define DACC_R12DH REG32(DAC + 0x20U) /*!< DAC concurrent mode 12-bit right-aligned data holding register */ +#define DACC_L12DH REG32(DAC + 0x24U) /*!< DAC concurrent mode 12-bit left-aligned data holding register */ +#define DACC_R8DH REG32(DAC + 0x28U) /*!< DAC concurrent mode 8-bit right-aligned data holding register */ +#define DAC0_DO REG32(DAC + 0x2CU) /*!< DAC0 data output register */ +#define DAC1_DO REG32(DAC + 0x30U) /*!< DAC1 data output register */ +#define DAC_STAT REG32(DAC + 0x34U) /*!< DAC status register */ /* bits definitions */ -/* DAC_CLT */ -#define DAC_CTL_DEN0 BIT(0) /*!< DAC0 enable/disable bit */ -#define DAC_CTL_DBOFF0 BIT(1) /*!< DAC0 output buffer turn on/turn off bit */ -#define DAC_CTL_DTEN0 BIT(2) /*!< DAC0 trigger enable/disable bit */ -#define DAC_CTL_DTSEL0 BITS(3,5) /*!< DAC0 trigger source selection enable/disable bits */ -#define DAC_CTL_DWM0 BITS(6,7) /*!< DAC0 noise wave mode */ -#define DAC_CTL_DWBW0 BITS(8,11) /*!< DAC0 noise wave bit width */ -#define DAC_CTL_DDMAEN0 BIT(12) /*!< DAC0 DMA enable/disanle bit */ -#define DAC_CTL_DDUDRIE0 BIT(13) /*!< DAC0 DMA underrun interrupt enable/disable bit */ -#define DAC_CTL_DEN1 BIT(16) /*!< DAC1 enable/disable bit */ -#define DAC_CTL_DBOFF1 BIT(17) /*!< DAC1 output buffer turn on/turn off bit */ -#define DAC_CTL_DTEN1 BIT(18) /*!< DAC1 trigger enable/disable bit */ -#define DAC_CTL_DTSEL1 BITS(19,21) /*!< DAC1 trigger source selection enable/disable bits */ -#define DAC_CTL_DWM1 BITS(22,23) /*!< DAC1 noise wave mode */ -#define DAC_CTL_DWBW1 BITS(24,27) /*!< DAC1 noise wave bit width */ -#define DAC_CTL_DDMAEN1 BIT(28) /*!< DAC1 DMA enable/disanle bit */ -#define DAC_CTL_DDUDRIE1 BIT(29) /*!< DAC1 DMA underrun interrupt enable/disable bit */ +/* DAC_CTL */ +#define DAC_CTL_DEN0 BIT(0) /*!< DAC0 enable/disable bit */ +#define DAC_CTL_DBOFF0 BIT(1) /*!< DAC0 output buffer turn on/turn off bit */ +#define DAC_CTL_DTEN0 BIT(2) /*!< DAC0 trigger enable/disable bit */ +#define DAC_CTL_DTSEL0 BITS(3,5) /*!< DAC0 trigger source selection enable/disable bits */ +#define DAC_CTL_DWM0 BITS(6,7) /*!< DAC0 noise wave mode */ +#define DAC_CTL_DWBW0 BITS(8,11) /*!< DAC0 noise wave bit width */ +#define DAC_CTL_DDMAEN0 BIT(12) /*!< DAC0 DMA enable/disable bit */ +#define DAC_CTL_DDUDRIE0 BIT(13) /*!< DAC0 DMA underrun interrupt enable/disable bit */ +#define DAC_CTL_DEN1 BIT(16) /*!< DAC1 enable/disable bit */ +#define DAC_CTL_DBOFF1 BIT(17) /*!< DAC1 output buffer turn on/turn off bit */ +#define DAC_CTL_DTEN1 BIT(18) /*!< DAC1 trigger enable/disable bit */ +#define DAC_CTL_DTSEL1 BITS(19,21) /*!< DAC1 trigger source selection enable/disable bits */ +#define DAC_CTL_DWM1 BITS(22,23) /*!< DAC1 noise wave mode */ +#define DAC_CTL_DWBW1 BITS(24,27) /*!< DAC1 noise wave bit width */ +#define DAC_CTL_DDMAEN1 BIT(28) /*!< DAC1 DMA enable/disable bit */ +#define DAC_CTL_DDUDRIE1 BIT(29) /*!< DAC1 DMA underrun interrupt enable/disable bit */ /* DAC_SWT */ -#define DAC_SWT_SWTR0 BIT(0) /*!< DAC0 software trigger bit, cleared by hardware */ -#define DAC_SWT_SWTR1 BIT(1) /*!< DAC1 software trigger bit, cleared by hardware */ +#define DAC_SWT_SWTR0 BIT(0) /*!< DAC0 software trigger bit, cleared by hardware */ +#define DAC_SWT_SWTR1 BIT(1) /*!< DAC1 software trigger bit, cleared by hardware */ /* DAC0_R12DH */ -#define DAC0_R12DH_DAC0_DH BITS(0,11) /*!< DAC0 12-bit right-aligned data bits */ +#define DAC0_R12DH_DAC0_DH BITS(0,11) /*!< DAC0 12-bit right-aligned data bits */ /* DAC0_L12DH */ -#define DAC0_L12DH_DAC0_DH BITS(4,15) /*!< DAC0 12-bit left-aligned data bits */ +#define DAC0_L12DH_DAC0_DH BITS(4,15) /*!< DAC0 12-bit left-aligned data bits */ /* DAC0_R8DH */ -#define DAC0_R8DH_DAC0_DH BITS(0,7) /*!< DAC0 8-bit right-aligned data bits */ +#define DAC0_R8DH_DAC0_DH BITS(0,7) /*!< DAC0 8-bit right-aligned data bits */ /* DAC1_R12DH */ -#define DAC1_R12DH_DAC1_DH BITS(0,11) /*!< DAC1 12-bit right-aligned data bits */ +#define DAC1_R12DH_DAC1_DH BITS(0,11) /*!< DAC1 12-bit right-aligned data bits */ /* DAC1_L12DH */ -#define DAC1_L12DH_DAC1_DH BITS(4,15) /*!< DAC1 12-bit left-aligned data bits */ +#define DAC1_L12DH_DAC1_DH BITS(4,15) /*!< DAC1 12-bit left-aligned data bits */ /* DAC1_R8DH */ -#define DAC1_R8DH_DAC1_DH BITS(0,7) /*!< DAC1 8-bit right-aligned data bits */ +#define DAC1_R8DH_DAC1_DH BITS(0,7) /*!< DAC1 8-bit right-aligned data bits */ /* DACC_R12DH */ -#define DACC_R12DH_DAC0_DH BITS(0,11) /*!< DAC concurrent mode DAC0 12-bit right-aligned data bits */ -#define DACC_R12DH_DAC1_DH BITS(16,27) /*!< DAC concurrent mode DAC1 12-bit right-aligned data bits */ +#define DACC_R12DH_DAC0_DH BITS(0,11) /*!< DAC concurrent mode DAC0 12-bit right-aligned data bits */ +#define DACC_R12DH_DAC1_DH BITS(16,27) /*!< DAC concurrent mode DAC1 12-bit right-aligned data bits */ /* DACC_L12DH */ -#define DACC_L12DH_DAC0_DH BITS(4,15) /*!< DAC concurrent mode DAC0 12-bit left-aligned data bits */ -#define DACC_L12DH_DAC1_DH BITS(20,31) /*!< DAC concurrent mode DAC1 12-bit left-aligned data bits */ +#define DACC_L12DH_DAC0_DH BITS(4,15) /*!< DAC concurrent mode DAC0 12-bit left-aligned data bits */ +#define DACC_L12DH_DAC1_DH BITS(20,31) /*!< DAC concurrent mode DAC1 12-bit left-aligned data bits */ /* DACC_R8DH */ -#define DACC_R8DH_DAC0_DH BITS(0,7) /*!< DAC concurrent mode DAC0 8-bit right-aligned data bits */ -#define DACC_R8DH_DAC1_DH BITS(16,23) /*!< DAC concurrent mode DAC1 8-bit right-aligned data bits */ +#define DACC_R8DH_DAC0_DH BITS(0,7) /*!< DAC concurrent mode DAC0 8-bit right-aligned data bits */ +#define DACC_R8DH_DAC1_DH BITS(8,15) /*!< DAC concurrent mode DAC1 8-bit right-aligned data bits */ /* DAC0_DO */ -#define DAC0_DO_DAC0_DO BITS(0,11) /*!< DAC0 12-bit output data bits */ +#define DAC0_DO_DAC0_DO BITS(0,11) /*!< DAC0 12-bit output data bits */ /* DAC1_DO */ -#define DAC1_DO_DAC1_DO BITS(0,11) /*!< DAC1 12-bit output data bits */ +#define DAC1_DO_DAC1_DO BITS(0,11) /*!< DAC1 12-bit output data bits */ /* DAC_STAT */ -#define DAC_STAT_DDUDR0 BIT(13) /*!< DAC0 DMA underrun flag */ -#define DAC_STAT_DDUDR1 BIT(29) /*!< DAC1 DMA underrun flag */ +#define DAC_STAT_DDUDR0 BIT(13) /*!< DAC0 DMA underrun flag */ +#define DAC_STAT_DDUDR1 BIT(29) /*!< DAC1 DMA underrun flag */ /* constants definitions */ /* DAC trigger source */ #define CTL_DTSEL(regval) (BITS(3,5) & ((uint32_t)(regval) << 3)) -#define DAC_TRIGGER_T5_TRGO CTL_DTSEL(0) /*!< TIMER5 TRGO */ -#define DAC_TRIGGER_T7_TRGO CTL_DTSEL(1) /*!< TIMER7 TRGO */ -#define DAC_TRIGGER_T6_TRGO CTL_DTSEL(2) /*!< TIMER6 TRGO */ -#define DAC_TRIGGER_T4_TRGO CTL_DTSEL(3) /*!< TIMER4 TRGO */ -#define DAC_TRIGGER_T1_TRGO CTL_DTSEL(4) /*!< TIMER1 TRGO */ -#define DAC_TRIGGER_T3_TRGO CTL_DTSEL(5) /*!< TIMER3 TRGO */ -#define DAC_TRIGGER_EXTI_9 CTL_DTSEL(6) /*!< EXTI interrupt line9 event */ -#define DAC_TRIGGER_SOFTWARE CTL_DTSEL(7) /*!< software trigger */ +#define DAC_TRIGGER_T5_TRGO CTL_DTSEL(0) /*!< TIMER5 TRGO */ +#define DAC_TRIGGER_T7_TRGO CTL_DTSEL(1) /*!< TIMER7 TRGO */ +#define DAC_TRIGGER_T6_TRGO CTL_DTSEL(2) /*!< TIMER6 TRGO */ +#define DAC_TRIGGER_T4_TRGO CTL_DTSEL(3) /*!< TIMER4 TRGO */ +#define DAC_TRIGGER_T1_TRGO CTL_DTSEL(4) /*!< TIMER1 TRGO */ +#define DAC_TRIGGER_T3_TRGO CTL_DTSEL(5) /*!< TIMER3 TRGO */ +#define DAC_TRIGGER_EXTI_9 CTL_DTSEL(6) /*!< EXTI interrupt line9 event */ +#define DAC_TRIGGER_SOFTWARE CTL_DTSEL(7) /*!< software trigger */ /* DAC noise wave mode */ #define CTL_DWM(regval) (BITS(6,7) & ((uint32_t)(regval) << 6)) -#define DAC_WAVE_DISABLE CTL_DWM(0) /*!< wave disable */ -#define DAC_WAVE_MODE_LFSR CTL_DWM(1) /*!< LFSR noise mode */ -#define DAC_WAVE_MODE_TRIANGLE CTL_DWM(2) /*!< triangle noise mode */ +#define DAC_WAVE_DISABLE CTL_DWM(0) /*!< wave disable */ +#define DAC_WAVE_MODE_LFSR CTL_DWM(1) /*!< LFSR noise mode */ +#define DAC_WAVE_MODE_TRIANGLE CTL_DWM(2) /*!< triangle noise mode */ /* DAC noise wave bit width */ #define DWBW(regval) (BITS(8,11) & ((uint32_t)(regval) << 8)) -#define DAC_WAVE_BIT_WIDTH_1 DWBW(0) /*!< bit width of the wave signal is 1 */ -#define DAC_WAVE_BIT_WIDTH_2 DWBW(1) /*!< bit width of the wave signal is 2 */ -#define DAC_WAVE_BIT_WIDTH_3 DWBW(2) /*!< bit width of the wave signal is 3 */ -#define DAC_WAVE_BIT_WIDTH_4 DWBW(3) /*!< bit width of the wave signal is 4 */ -#define DAC_WAVE_BIT_WIDTH_5 DWBW(4) /*!< bit width of the wave signal is 5 */ -#define DAC_WAVE_BIT_WIDTH_6 DWBW(5) /*!< bit width of the wave signal is 6 */ -#define DAC_WAVE_BIT_WIDTH_7 DWBW(6) /*!< bit width of the wave signal is 7 */ -#define DAC_WAVE_BIT_WIDTH_8 DWBW(7) /*!< bit width of the wave signal is 8 */ -#define DAC_WAVE_BIT_WIDTH_9 DWBW(8) /*!< bit width of the wave signal is 9 */ -#define DAC_WAVE_BIT_WIDTH_10 DWBW(9) /*!< bit width of the wave signal is 10 */ -#define DAC_WAVE_BIT_WIDTH_11 DWBW(10) /*!< bit width of the wave signal is 11 */ -#define DAC_WAVE_BIT_WIDTH_12 DWBW(11) /*!< bit width of the wave signal is 12 */ +#define DAC_WAVE_BIT_WIDTH_1 DWBW(0) /*!< bit width of the wave signal is 1 */ +#define DAC_WAVE_BIT_WIDTH_2 DWBW(1) /*!< bit width of the wave signal is 2 */ +#define DAC_WAVE_BIT_WIDTH_3 DWBW(2) /*!< bit width of the wave signal is 3 */ +#define DAC_WAVE_BIT_WIDTH_4 DWBW(3) /*!< bit width of the wave signal is 4 */ +#define DAC_WAVE_BIT_WIDTH_5 DWBW(4) /*!< bit width of the wave signal is 5 */ +#define DAC_WAVE_BIT_WIDTH_6 DWBW(5) /*!< bit width of the wave signal is 6 */ +#define DAC_WAVE_BIT_WIDTH_7 DWBW(6) /*!< bit width of the wave signal is 7 */ +#define DAC_WAVE_BIT_WIDTH_8 DWBW(7) /*!< bit width of the wave signal is 8 */ +#define DAC_WAVE_BIT_WIDTH_9 DWBW(8) /*!< bit width of the wave signal is 9 */ +#define DAC_WAVE_BIT_WIDTH_10 DWBW(9) /*!< bit width of the wave signal is 10 */ +#define DAC_WAVE_BIT_WIDTH_11 DWBW(10) /*!< bit width of the wave signal is 11 */ +#define DAC_WAVE_BIT_WIDTH_12 DWBW(11) /*!< bit width of the wave signal is 12 */ /* unmask LFSR bits in DAC LFSR noise mode */ -#define DAC_LFSR_BIT0 DAC_WAVE_BIT_WIDTH_1 /*!< unmask the LFSR bit0 */ -#define DAC_LFSR_BITS1_0 DAC_WAVE_BIT_WIDTH_2 /*!< unmask the LFSR bits[1:0] */ -#define DAC_LFSR_BITS2_0 DAC_WAVE_BIT_WIDTH_3 /*!< unmask the LFSR bits[2:0] */ -#define DAC_LFSR_BITS3_0 DAC_WAVE_BIT_WIDTH_4 /*!< unmask the LFSR bits[3:0] */ -#define DAC_LFSR_BITS4_0 DAC_WAVE_BIT_WIDTH_5 /*!< unmask the LFSR bits[4:0] */ -#define DAC_LFSR_BITS5_0 DAC_WAVE_BIT_WIDTH_6 /*!< unmask the LFSR bits[5:0] */ -#define DAC_LFSR_BITS6_0 DAC_WAVE_BIT_WIDTH_7 /*!< unmask the LFSR bits[6:0] */ -#define DAC_LFSR_BITS7_0 DAC_WAVE_BIT_WIDTH_8 /*!< unmask the LFSR bits[7:0] */ -#define DAC_LFSR_BITS8_0 DAC_WAVE_BIT_WIDTH_9 /*!< unmask the LFSR bits[8:0] */ -#define DAC_LFSR_BITS9_0 DAC_WAVE_BIT_WIDTH_10 /*!< unmask the LFSR bits[9:0] */ -#define DAC_LFSR_BITS10_0 DAC_WAVE_BIT_WIDTH_11 /*!< unmask the LFSR bits[10:0] */ -#define DAC_LFSR_BITS11_0 DAC_WAVE_BIT_WIDTH_12 /*!< unmask the LFSR bits[11:0] */ - -/* triangle amplitude in DAC triangle noise mode */ -#define DAC_TRIANGLE_AMPLITUDE_1 DAC_WAVE_BIT_WIDTH_1 /*!< triangle amplitude is 1 */ -#define DAC_TRIANGLE_AMPLITUDE_3 DAC_WAVE_BIT_WIDTH_2 /*!< triangle amplitude is 3 */ -#define DAC_TRIANGLE_AMPLITUDE_7 DAC_WAVE_BIT_WIDTH_3 /*!< triangle amplitude is 7 */ -#define DAC_TRIANGLE_AMPLITUDE_15 DAC_WAVE_BIT_WIDTH_4 /*!< triangle amplitude is 15 */ -#define DAC_TRIANGLE_AMPLITUDE_31 DAC_WAVE_BIT_WIDTH_5 /*!< triangle amplitude is 31 */ -#define DAC_TRIANGLE_AMPLITUDE_63 DAC_WAVE_BIT_WIDTH_6 /*!< triangle amplitude is 63 */ -#define DAC_TRIANGLE_AMPLITUDE_127 DAC_WAVE_BIT_WIDTH_7 /*!< triangle amplitude is 127 */ -#define DAC_TRIANGLE_AMPLITUDE_255 DAC_WAVE_BIT_WIDTH_8 /*!< triangle amplitude is 255 */ -#define DAC_TRIANGLE_AMPLITUDE_511 DAC_WAVE_BIT_WIDTH_9 /*!< triangle amplitude is 511 */ -#define DAC_TRIANGLE_AMPLITUDE_1023 DAC_WAVE_BIT_WIDTH_10 /*!< triangle amplitude is 1023 */ -#define DAC_TRIANGLE_AMPLITUDE_2047 DAC_WAVE_BIT_WIDTH_11 /*!< triangle amplitude is 2047 */ -#define DAC_TRIANGLE_AMPLITUDE_4095 DAC_WAVE_BIT_WIDTH_12 /*!< triangle amplitude is 4095 */ +#define DAC_LFSR_BIT0 DAC_WAVE_BIT_WIDTH_1 /*!< unmask the LFSR bit0 */ +#define DAC_LFSR_BITS1_0 DAC_WAVE_BIT_WIDTH_2 /*!< unmask the LFSR bits[1:0] */ +#define DAC_LFSR_BITS2_0 DAC_WAVE_BIT_WIDTH_3 /*!< unmask the LFSR bits[2:0] */ +#define DAC_LFSR_BITS3_0 DAC_WAVE_BIT_WIDTH_4 /*!< unmask the LFSR bits[3:0] */ +#define DAC_LFSR_BITS4_0 DAC_WAVE_BIT_WIDTH_5 /*!< unmask the LFSR bits[4:0] */ +#define DAC_LFSR_BITS5_0 DAC_WAVE_BIT_WIDTH_6 /*!< unmask the LFSR bits[5:0] */ +#define DAC_LFSR_BITS6_0 DAC_WAVE_BIT_WIDTH_7 /*!< unmask the LFSR bits[6:0] */ +#define DAC_LFSR_BITS7_0 DAC_WAVE_BIT_WIDTH_8 /*!< unmask the LFSR bits[7:0] */ +#define DAC_LFSR_BITS8_0 DAC_WAVE_BIT_WIDTH_9 /*!< unmask the LFSR bits[8:0] */ +#define DAC_LFSR_BITS9_0 DAC_WAVE_BIT_WIDTH_10 /*!< unmask the LFSR bits[9:0] */ +#define DAC_LFSR_BITS10_0 DAC_WAVE_BIT_WIDTH_11 /*!< unmask the LFSR bits[10:0] */ +#define DAC_LFSR_BITS11_0 DAC_WAVE_BIT_WIDTH_12 /*!< unmask the LFSR bits[11:0] */ /* DAC data alignment */ #define DATA_ALIGN(regval) (BITS(0,1) & ((uint32_t)(regval) << 0)) -#define DAC_ALIGN_12B_R DATA_ALIGN(0) /*!< data right 12b alignment */ -#define DAC_ALIGN_12B_L DATA_ALIGN(1) /*!< data left 12b alignment */ -#define DAC_ALIGN_8B_R DATA_ALIGN(2) /*!< data right 8b alignment */ +#define DAC_ALIGN_12B_R DATA_ALIGN(0) /*!< data right 12 bit alignment */ +#define DAC_ALIGN_12B_L DATA_ALIGN(1) /*!< data left 12 bit alignment */ +#define DAC_ALIGN_8B_R DATA_ALIGN(2) /*!< data right 8 bit alignment */ + +/* triangle amplitude in DAC triangle noise mode */ +#define DAC_TRIANGLE_AMPLITUDE_1 DAC_WAVE_BIT_WIDTH_1 /*!< triangle amplitude is 1 */ +#define DAC_TRIANGLE_AMPLITUDE_3 DAC_WAVE_BIT_WIDTH_2 /*!< triangle amplitude is 3 */ +#define DAC_TRIANGLE_AMPLITUDE_7 DAC_WAVE_BIT_WIDTH_3 /*!< triangle amplitude is 7 */ +#define DAC_TRIANGLE_AMPLITUDE_15 DAC_WAVE_BIT_WIDTH_4 /*!< triangle amplitude is 15 */ +#define DAC_TRIANGLE_AMPLITUDE_31 DAC_WAVE_BIT_WIDTH_5 /*!< triangle amplitude is 31 */ +#define DAC_TRIANGLE_AMPLITUDE_63 DAC_WAVE_BIT_WIDTH_6 /*!< triangle amplitude is 63 */ +#define DAC_TRIANGLE_AMPLITUDE_127 DAC_WAVE_BIT_WIDTH_7 /*!< triangle amplitude is 127 */ +#define DAC_TRIANGLE_AMPLITUDE_255 DAC_WAVE_BIT_WIDTH_8 /*!< triangle amplitude is 255 */ +#define DAC_TRIANGLE_AMPLITUDE_511 DAC_WAVE_BIT_WIDTH_9 /*!< triangle amplitude is 511 */ +#define DAC_TRIANGLE_AMPLITUDE_1023 DAC_WAVE_BIT_WIDTH_10 /*!< triangle amplitude is 1023 */ +#define DAC_TRIANGLE_AMPLITUDE_2047 DAC_WAVE_BIT_WIDTH_11 /*!< triangle amplitude is 2047 */ +#define DAC_TRIANGLE_AMPLITUDE_4095 DAC_WAVE_BIT_WIDTH_12 /*!< triangle amplitude is 4095 */ /* function declarations */ +/* initialization functions */ /* deinitialize DAC */ void dac_deinit(void); /* enable DAC */ @@ -175,26 +201,29 @@ void dac_disable(uint32_t dac_periph); /* enable DAC DMA */ void dac_dma_enable(uint32_t dac_periph); /* disable DAC DMA */ -void dac_dma_disable(uint32_t dac_periph); +void dac_dma_disable(uint32_t dac_periph); /* enable DAC output buffer */ void dac_output_buffer_enable(uint32_t dac_periph); /* disable DAC output buffer */ void dac_output_buffer_disable(uint32_t dac_periph); +/* get the last data output value */ +uint16_t dac_output_value_get(uint32_t dac_periph); +/* set DAC data holding register value */ +void dac_data_set(uint32_t dac_periph, uint32_t dac_align, uint16_t data); + +/* DAC trigger configuration */ /* enable DAC trigger */ void dac_trigger_enable(uint32_t dac_periph); /* disable DAC trigger */ void dac_trigger_disable(uint32_t dac_periph); +/* configure DAC trigger source */ +void dac_trigger_source_config(uint32_t dac_periph, uint32_t triggersource); /* enable DAC software trigger */ void dac_software_trigger_enable(uint32_t dac_periph); /* disable DAC software trigger */ void dac_software_trigger_disable(uint32_t dac_periph); -/* enable DAC interrupt(DAC0 DMA underrun interrupt) */ -void dac_interrupt_enable(uint32_t dac_periph); -/* disable DAC interrupt(DAC0 DMA underrun interrupt) */ -void dac_interrupt_disable(uint32_t dac_periph); -/* configure DAC trigger source */ -void dac_trigger_source_config(uint32_t dac_periph, uint32_t triggersource); +/* DAC wave mode configuration */ /* configure DAC wave mode */ void dac_wave_mode_config(uint32_t dac_periph, uint32_t wave_mode); /* configure DAC wave bit width */ @@ -203,14 +232,8 @@ void dac_wave_bit_width_config(uint32_t dac_periph, uint32_t bit_width); void dac_lfsr_noise_config(uint32_t dac_periph, uint32_t unmask_bits); /* configure DAC triangle noise mode */ void dac_triangle_noise_config(uint32_t dac_periph, uint32_t amplitude); -/* get the last data output value */ -uint16_t dac_output_value_get(uint32_t dac_periph); - -/* set DAC data holding register value */ -void dac_data_set(uint32_t dac_periph, uint32_t dac_align, uint16_t data); -/* set DAC concurrent mode data holding register value */ -void dac_concurrent_data_set(uint32_t dac_align, uint16_t data0, uint16_t data1); +/* DAC concurrent mode configuration */ /* enable DAC concurrent mode */ void dac_concurrent_enable(void); /* disable DAC concurrent mode */ @@ -223,11 +246,18 @@ void dac_concurrent_software_trigger_disable(void); void dac_concurrent_output_buffer_enable(void); /* disable DAC concurrent buffer function */ void dac_concurrent_output_buffer_disable(void); +/* set DAC concurrent mode data holding register value */ +void dac_concurrent_data_set(uint32_t dac_align, uint16_t data0, uint16_t data1); /* enable DAC concurrent interrupt */ void dac_concurrent_interrupt_enable(void); /* disable DAC concurrent interrupt */ void dac_concurrent_interrupt_disable(void); +/* DAC interrupt configuration */ +/* enable DAC interrupt(DAC DMA underrun interrupt) */ +void dac_interrupt_enable(uint32_t dac_periph); +/* disable DAC interrupt(DAC DMA underrun interrupt) */ +void dac_interrupt_disable(uint32_t dac_periph); /* get the specified DAC flag(DAC DMA underrun flag) */ FlagStatus dac_flag_get(uint32_t dac_periph); /* clear the specified DAC flag(DAC DMA underrun flag) */ diff --git a/bsp/gd32450z-eval/Libraries/GD32F4xx_standard_peripheral/Include/gd32f4xx_dbg.h b/bsp/gd32450z-eval/Libraries/GD32F4xx_standard_peripheral/Include/gd32f4xx_dbg.h index 273b13e7fb..fde91597f7 100644 --- a/bsp/gd32450z-eval/Libraries/GD32F4xx_standard_peripheral/Include/gd32f4xx_dbg.h +++ b/bsp/gd32450z-eval/Libraries/GD32F4xx_standard_peripheral/Include/gd32f4xx_dbg.h @@ -1,12 +1,37 @@ /*! - \file gd32f4xx_dbg.h - \brief definitions for the DBG + \file gd32f4xx_dbg.h + \brief definitions for the DBG + + \version 2016-08-15, V1.0.0, firmware for GD32F4xx + \version 2018-12-12, V2.0.0, firmware for GD32F4xx + \version 2020-09-30, V2.1.0, firmware for GD32F4xx */ /* - Copyright (C) 2016 GigaDevice + Copyright (c) 2020, GigaDevice Semiconductor Inc. + + Redistribution and use in source and binary forms, with or without modification, +are permitted provided that the following conditions are met: + + 1. Redistributions of source code must retain the above copyright notice, this + list of conditions and the following disclaimer. + 2. Redistributions in binary form must reproduce the above copyright notice, + this list of conditions and the following disclaimer in the documentation + and/or other materials provided with the distribution. + 3. Neither the name of the copyright holder nor the names of its contributors + may be used to endorse or promote products derived from this software without + specific prior written permission. - 2016-08-15, V1.0.0, firmware for GD32F4xx + THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED +WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. +IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, +INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT +NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR +PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, +WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY +OF SUCH DAMAGE. */ #ifndef GD32F4XX_DBG_H @@ -65,30 +90,43 @@ #define DBG_LOW_POWER_DEEPSLEEP DBG_CTL0_DSLP_HOLD /*!< keep debugger connection during deepsleep mode */ #define DBG_LOW_POWER_STANDBY DBG_CTL0_STB_HOLD /*!< keep debugger connection during standby mode */ +/* define the peripheral debug hold bit position and its register index offset */ +#define DBG_REGIDX_BIT(regidx, bitpos) (((regidx) << 6) | (bitpos)) +#define DBG_REG_VAL(periph) (REG32(DBG + ((uint32_t)(periph) >> 6))) +#define DBG_BIT_POS(val) ((uint32_t)(val) & 0x1FU) + +/* register index */ +enum dbg_reg_idx +{ + DBG_IDX_CTL0 = 0x04U, + DBG_IDX_CTL1 = 0x08U, + DBG_IDX_CTL2 = 0x0CU +}; + typedef enum { - DBG_TIMER1_HOLD = BIT(0), /*!< hold TIMER1 counter when core is halted */ - DBG_TIMER2_HOLD = BIT(1), /*!< hold TIMER2 counter when core is halted */ - DBG_TIMER3_HOLD = BIT(2), /*!< hold TIMER3 counter when core is halted */ - DBG_TIMER4_HOLD = BIT(3), /*!< hold TIMER4 counter when core is halted */ - DBG_TIMER5_HOLD = BIT(4), /*!< hold TIMER5 counter when core is halted */ - DBG_TIMER6_HOLD = BIT(5), /*!< hold TIMER6 counter when core is halted */ - DBG_TIMER11_HOLD = BIT(6), /*!< hold TIMER11 counter when core is halted */ - DBG_TIMER12_HOLD = BIT(7), /*!< hold TIMER12 counter when core is halted */ - DBG_TIMER13_HOLD = BIT(8), /*!< hold TIMER13 counter when core is halted */ - DBG_RTC_HOLD = BIT(10), /*!< hold RTC calendar and wakeup counter when core is halted */ - DBG_WWDGT_HOLD = BIT(11), /*!< debug WWDGT kept when core is halted */ - DBG_FWDGT_HOLD = BIT(12), /*!< debug FWDGT kept when core is halted */ - DBG_I2C0_HOLD = BIT(21), /*!< hold I2C0 smbus when core is halted */ - DBG_I2C1_HOLD = BIT(22), /*!< hold I2C1 smbus when core is halted */ - DBG_I2C2_HOLD = BIT(23), /*!< hold I2C2 smbus when core is halted */ - DBG_CAN0_HOLD = BIT(25), /*!< debug CAN0 kept when core is halted */ - DBG_CAN1_HOLD = BIT(26), /*!< debug CAN1 kept when core is halted */ - DBG_TIMER0_HOLD = (BIT(0) | BIT(30)), /*!< hold TIMER0 counter when core is halted */ - DBG_TIMER7_HOLD = (BIT(1) | BIT(30)), /*!< hold TIMER7 counter when core is halted */ - DBG_TIMER8_HOLD = (BIT(16) | BIT(30)), /*!< hold TIMER8 counter when core is halted */ - DBG_TIMER9_HOLD = (BIT(17) | BIT(30)), /*!< hold TIMER9 counter when core is halted */ - DBG_TIMER10_HOLD = (BIT(18) | BIT(30)), /*!< hold TIMER10 counter when core is halted */ + DBG_TIMER1_HOLD = DBG_REGIDX_BIT(DBG_IDX_CTL1, 0U), /*!< hold TIMER1 counter when core is halted */ + DBG_TIMER2_HOLD = DBG_REGIDX_BIT(DBG_IDX_CTL1, 1U), /*!< hold TIMER2 counter when core is halted */ + DBG_TIMER3_HOLD = DBG_REGIDX_BIT(DBG_IDX_CTL1, 2U), /*!< hold TIMER3 counter when core is halted */ + DBG_TIMER4_HOLD = DBG_REGIDX_BIT(DBG_IDX_CTL1, 3U), /*!< hold TIMER4 counter when core is halted */ + DBG_TIMER5_HOLD = DBG_REGIDX_BIT(DBG_IDX_CTL1, 4U), /*!< hold TIMER5 counter when core is halted */ + DBG_TIMER6_HOLD = DBG_REGIDX_BIT(DBG_IDX_CTL1, 5U), /*!< hold TIMER6 counter when core is halted */ + DBG_TIMER11_HOLD = DBG_REGIDX_BIT(DBG_IDX_CTL1, 6U), /*!< hold TIMER11 counter when core is halted */ + DBG_TIMER12_HOLD = DBG_REGIDX_BIT(DBG_IDX_CTL1, 7U), /*!< hold TIMER12 counter when core is halted */ + DBG_TIMER13_HOLD = DBG_REGIDX_BIT(DBG_IDX_CTL1, 8U), /*!< hold TIMER13 counter when core is halted */ + DBG_RTC_HOLD = DBG_REGIDX_BIT(DBG_IDX_CTL1, 10U), /*!< hold RTC calendar and wakeup counter when core is halted */ + DBG_WWDGT_HOLD = DBG_REGIDX_BIT(DBG_IDX_CTL1, 11U), /*!< debug WWDGT kept when core is halted */ + DBG_FWDGT_HOLD = DBG_REGIDX_BIT(DBG_IDX_CTL1, 12U), /*!< debug FWDGT kept when core is halted */ + DBG_I2C0_HOLD = DBG_REGIDX_BIT(DBG_IDX_CTL1, 21U), /*!< hold I2C0 smbus when core is halted */ + DBG_I2C1_HOLD = DBG_REGIDX_BIT(DBG_IDX_CTL1, 22U), /*!< hold I2C1 smbus when core is halted */ + DBG_I2C2_HOLD = DBG_REGIDX_BIT(DBG_IDX_CTL1, 23U), /*!< hold I2C2 smbus when core is halted */ + DBG_CAN0_HOLD = DBG_REGIDX_BIT(DBG_IDX_CTL1, 25U), /*!< debug CAN0 kept when core is halted */ + DBG_CAN1_HOLD = DBG_REGIDX_BIT(DBG_IDX_CTL1, 26U), /*!< debug CAN1 kept when core is halted */ + DBG_TIMER0_HOLD = DBG_REGIDX_BIT(DBG_IDX_CTL2, 0U), /*!< hold TIMER0 counter when core is halted */ + DBG_TIMER7_HOLD = DBG_REGIDX_BIT(DBG_IDX_CTL2, 1U), /*!< hold TIMER7 counter when core is halted */ + DBG_TIMER8_HOLD = DBG_REGIDX_BIT(DBG_IDX_CTL2, 16U), /*!< hold TIMER8 counter when core is halted */ + DBG_TIMER9_HOLD = DBG_REGIDX_BIT(DBG_IDX_CTL2, 17U), /*!< hold TIMER9 counter when core is halted */ + DBG_TIMER10_HOLD = DBG_REGIDX_BIT(DBG_IDX_CTL2, 18U) /*!< hold TIMER10 counter when core is halted */ }dbg_periph_enum; #define CTL0_TRACE_MODE(regval) (BITS(6,7)&((uint32_t)(regval)<<6)) @@ -98,6 +136,8 @@ typedef enum #define TRACE_MODE_SYNC_DATASIZE_4 CTL0_TRACE_MODE(3) /*!< trace pin used for sync mode and data size is 4 */ /* function declarations */ +/* deinitialize the DBG */ +void dbg_deinit(void); /* read DBG_ID code register */ uint32_t dbg_id_get(void); diff --git a/bsp/gd32450z-eval/Libraries/GD32F4xx_standard_peripheral/Include/gd32f4xx_dci.h b/bsp/gd32450z-eval/Libraries/GD32F4xx_standard_peripheral/Include/gd32f4xx_dci.h index 7c9b445138..4986d5afd4 100644 --- a/bsp/gd32450z-eval/Libraries/GD32F4xx_standard_peripheral/Include/gd32f4xx_dci.h +++ b/bsp/gd32450z-eval/Libraries/GD32F4xx_standard_peripheral/Include/gd32f4xx_dci.h @@ -1,12 +1,37 @@ /*! - \file gd32f4xx_dci.h - \brief definitions for the DCI + \file gd32f4xx_dci.h + \brief definitions for the DCI + + \version 2016-08-15, V1.0.0, firmware for GD32F4xx + \version 2018-12-12, V2.0.0, firmware for GD32F4xx + \version 2020-09-30, V2.1.0, firmware for GD32F4xx */ /* - Copyright (C) 2016 GigaDevice + Copyright (c) 2020, GigaDevice Semiconductor Inc. + + Redistribution and use in source and binary forms, with or without modification, +are permitted provided that the following conditions are met: + + 1. Redistributions of source code must retain the above copyright notice, this + list of conditions and the following disclaimer. + 2. Redistributions in binary form must reproduce the above copyright notice, + this list of conditions and the following disclaimer in the documentation + and/or other materials provided with the distribution. + 3. Neither the name of the copyright holder nor the names of its contributors + may be used to endorse or promote products derived from this software without + specific prior written permission. - 2016-08-15, V1.0.0, firmware for GD32F4xx + THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED +WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. +IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, +INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT +NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR +PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, +WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY +OF SUCH DAMAGE. */ #ifndef GD32F4XX_DCI_H @@ -32,17 +57,17 @@ /* bits definitions */ /* DCI_CTL */ -#define DCI_CTL_CAP BIT(0) /*!< capture enable */ -#define DCI_CTL_SNAP BIT(1) /*!< snapshot mode */ -#define DCI_CTL_WDEN BIT(2) /*!< window enable */ -#define DCI_CTL_JM BIT(3) /*!< jpeg mode */ -#define DCI_CTL_ESM BIT(4) /*!< embedded synchronous mode */ -#define DCI_CTL_CKS BIT(5) /*!< clock polarity selection */ -#define DCI_CTL_HPS BIT(6) /*!< horizontal polarity selection */ -#define DCI_CTL_VPS BIT(7) /*!< vertical polarity selection */ -#define DCI_CTL_FR BITS(8,9) /*!< frame rate */ -#define DCI_CTL_DCIF BITS(10,11) /*!< digital camera interface format */ -#define DCI_CTL_DCIEN BIT(14) /*!< dci enable */ +#define DCI_CTL_CAP BIT(0) /*!< capture enable */ +#define DCI_CTL_SNAP BIT(1) /*!< snapshot mode */ +#define DCI_CTL_WDEN BIT(2) /*!< window enable */ +#define DCI_CTL_JM BIT(3) /*!< JPEG mode */ +#define DCI_CTL_ESM BIT(4) /*!< embedded synchronous mode */ +#define DCI_CTL_CKS BIT(5) /*!< clock polarity selection */ +#define DCI_CTL_HPS BIT(6) /*!< horizontal polarity selection */ +#define DCI_CTL_VPS BIT(7) /*!< vertical polarity selection */ +#define DCI_CTL_FR BITS(8,9) /*!< frame rate */ +#define DCI_CTL_DCIF BITS(10,11) /*!< digital camera interface format */ +#define DCI_CTL_DCIEN BIT(14) /*!< DCI enable */ /* DCI_STAT0 */ #define DCI_STAT0_HS BIT(0) /*!< HS line status */ @@ -98,16 +123,16 @@ #define DCI_CWSZ_WVSZ BITS(16,29) /*!< window vertical size */ /* constants definitions */ -/* DCI parameter struct definitions */ +/* DCI parameter structure definitions */ typedef struct -{ +{ uint32_t capture_mode; /*!< DCI capture mode: continuous or snapshot */ uint32_t clock_polarity; /*!< clock polarity selection */ uint32_t hsync_polarity; /*!< horizontal polarity selection */ uint32_t vsync_polarity; /*!< vertical polarity selection */ uint32_t frame_rate; /*!< frame capture rate */ uint32_t interface_format; /*!< digital camera interface format */ -}dci_parameter_struct; +}dci_parameter_struct; #define DCI_CAPTURE_MODE_CONTINUOUS ((uint32_t)0x00000000U) /*!< continuous capture mode */ #define DCI_CAPTURE_MODE_SNAPSHOT DCI_CTL_SNAP /*!< snapshot capture mode */ @@ -120,36 +145,44 @@ typedef struct #define DCI_VSYNC_POLARITY_LOW ((uint32_t)0x00000000U) /*!< low level during blanking period */ #define DCI_VSYNC_POLARITY_HIGH DCI_CTL_VPS /*!< high level during blanking period*/ - -#define CTL_FR(regval) (BITS(8,9)&((uint32_t)(regval) << 8U)) + +#define CTL_FR(regval) (BITS(8,9)&((uint32_t)(regval) << 8U)) #define DCI_FRAME_RATE_ALL CTL_FR(0) /*!< capture all frames */ #define DCI_FRAME_RATE_1_2 CTL_FR(1) /*!< capture one in 2 frames */ #define DCI_FRAME_RATE_1_4 CTL_FR(2) /*!< capture one in 4 frames */ -#define CTL_DCIF(regval) (BITS(10,11)&((uint32_t)(regval) << 10U)) +#define CTL_DCIF(regval) (BITS(10,11)&((uint32_t)(regval) << 10U)) #define DCI_INTERFACE_FORMAT_8BITS CTL_DCIF(0) /*!< 8-bit data on every pixel clock */ #define DCI_INTERFACE_FORMAT_10BITS CTL_DCIF(1) /*!< 10-bit data on every pixel clock */ #define DCI_INTERFACE_FORMAT_12BITS CTL_DCIF(2) /*!< 12-bit data on every pixel clock */ #define DCI_INTERFACE_FORMAT_14BITS CTL_DCIF(3) /*!< 14-bit data on every pixel clock */ /* DCI interrupt constants definitions */ -#define DCI_INT_EF ((uint32_t)0x00000001U) /*!< end of frame interrupt */ -#define DCI_INT_OVR ((uint32_t)0x00000002U) /*!< FIFO overrun interrupt */ -#define DCI_INT_ESE ((uint32_t)0x00000004U) /*!< embedded synchronous error interrupt */ -#define DCI_INT_VS ((uint32_t)0x00000008U) /*!< vsync interrupt */ -#define DCI_INT_EL ((uint32_t)0x00000010U) /*!< end of line interrupt */ +#define DCI_INT_EF BIT(0) /*!< end of frame interrupt */ +#define DCI_INT_OVR BIT(1) /*!< FIFO overrun interrupt */ +#define DCI_INT_ESE BIT(2) /*!< embedded synchronous error interrupt */ +#define DCI_INT_VSYNC BIT(3) /*!< vsync interrupt */ +#define DCI_INT_EL BIT(4) /*!< end of line interrupt */ + +/* DCI interrupt flag definitions */ +#define DCI_INT_FLAG_EF BIT(0) /*!< end of frame interrupt flag */ +#define DCI_INT_FLAG_OVR BIT(1) /*!< FIFO overrun interrupt flag */ +#define DCI_INT_FLAG_ESE BIT(2) /*!< embedded synchronous error interrupt flag */ +#define DCI_INT_FLAG_VSYNC BIT(3) /*!< vsync interrupt flag */ +#define DCI_INT_FLAG_EL BIT(4) /*!< end of line interrupt flag */ -/* DCI flag definitions */ -#define DCI_FLAG_HS ((uint8_t)0x01U) /*!< HS line status */ -#define DCI_FLAG_VS ((uint8_t)0x02U) /*!< VS line status */ -#define DCI_FLAG_FV ((uint8_t)0x03U) /*!< FIFO valid */ -#define DCI_FLAG_EFF ((uint8_t)0x04U) /*!< end of frame flag */ -#define DCI_FLAG_OVRF ((uint8_t)0x05U) /*!< FIFO overrun flag */ -#define DCI_FLAG_ESEF ((uint8_t)0x06U) /*!< embedded synchronous error flag */ -#define DCI_FLAG_VSF ((uint8_t)0x07U) /*!< vsync flag */ -#define DCI_FLAG_ELF ((uint8_t)0x08U) /*!< end of line flag */ +/* DCI flag definitions */ +#define DCI_FLAG_HS DCI_STAT0_HS /*!< HS line status */ +#define DCI_FLAG_VS DCI_STAT0_VS /*!< VS line status */ +#define DCI_FLAG_FV DCI_STAT0_FV /*!< FIFO valid */ +#define DCI_FLAG_EF (DCI_STAT1_EFF | BIT(31)) /*!< end of frame flag */ +#define DCI_FLAG_OVR (DCI_STAT1_OVRF | BIT(31)) /*!< FIFO overrun flag */ +#define DCI_FLAG_ESE (DCI_STAT1_ESEF | BIT(31)) /*!< embedded synchronous error flag */ +#define DCI_FLAG_VSYNC (DCI_STAT1_VSF | BIT(31)) /*!< vsync flag */ +#define DCI_FLAG_EL (DCI_STAT1_ELF | BIT(31)) /*!< end of line flag */ /* function declarations */ +/* initialization functions */ /* DCI deinit */ void dci_deinit(void); /* initialize DCI registers */ @@ -157,44 +190,49 @@ void dci_init(dci_parameter_struct* dci_struct); /* enable DCI function */ void dci_enable(void); -/* disble DCI function */ +/* disable DCI function */ void dci_disable(void); /* enable DCI capture */ void dci_capture_enable(void); -/* disble DCI capture */ +/* disable DCI capture */ void dci_capture_disable(void); /* enable DCI jpeg mode */ void dci_jpeg_enable(void); -/* disble DCI jpeg mode */ +/* disable DCI jpeg mode */ void dci_jpeg_disable(void); +/* function configuration */ /* enable cropping window function */ void dci_crop_window_enable(void); -/* disble cropping window function */ +/* disable cropping window function */ void dci_crop_window_disable(void); -/* config DCI cropping window */ +/* configure DCI cropping window */ void dci_crop_window_config(uint16_t start_x, uint16_t start_y, uint16_t size_width, uint16_t size_height); -/* enable sync codes function */ -void dci_sync_codes_enable(void); -/* disble sync codes function */ -void dci_sync_codes_disable(void); -/* config sync codes */ +/* enable embedded synchronous mode */ +void dci_embedded_sync_enable(void); +/* disable embedded synchronous mode */ +void dci_embedded_sync_disable(void); +/* configure synchronous codes in embedded synchronous mode */ void dci_sync_codes_config(uint8_t frame_start, uint8_t line_start, uint8_t line_end, uint8_t frame_end); -/* config sync codes unmask */ +/* configure synchronous codes unmask in embedded synchronous mode */ void dci_sync_codes_unmask_config(uint8_t frame_start, uint8_t line_start, uint8_t line_end, uint8_t frame_end); /* read DCI data register */ uint32_t dci_data_read(void); +/* interrupt & flag functions */ +/* get specified flag */ +FlagStatus dci_flag_get(uint32_t flag); /* enable specified DCI interrupt */ void dci_interrupt_enable(uint32_t interrupt); -/* disble specified DCI interrupt */ +/* disable specified DCI interrupt */ void dci_interrupt_disable(uint32_t interrupt); -/* clear specified interrupt */ -void dci_interrupt_clear(uint32_t interrupt); -/* get specified flag */ -FlagStatus dci_flag_get(uint32_t flag); + + /* get specified interrupt flag */ -FlagStatus dci_interrupt_flag_get(uint32_t interrupt); +FlagStatus dci_interrupt_flag_get(uint32_t int_flag); +/* clear specified interrupt flag */ +void dci_interrupt_flag_clear(uint32_t int_flag); + #endif /* GD32F4XX_DCI_H */ diff --git a/bsp/gd32450z-eval/Libraries/GD32F4xx_standard_peripheral/Include/gd32f4xx_dma.h b/bsp/gd32450z-eval/Libraries/GD32F4xx_standard_peripheral/Include/gd32f4xx_dma.h index be59a229f6..cac70b85eb 100644 --- a/bsp/gd32450z-eval/Libraries/GD32F4xx_standard_peripheral/Include/gd32f4xx_dma.h +++ b/bsp/gd32450z-eval/Libraries/GD32F4xx_standard_peripheral/Include/gd32f4xx_dma.h @@ -1,12 +1,37 @@ /*! - \file gd32f4xx_dma.h - \brief definitions for the DMA + \file gd32f4xx_dma.c + \brief definitions for the DMA + + \version 2016-08-15, V1.0.0, firmware for GD32F4xx + \version 2018-12-12, V2.0.0, firmware for GD32F4xx + \version 2020-09-30, V2.1.0, firmware for GD32F4xx */ /* - Copyright (C) 2016 GigaDevice + Copyright (c) 2020, GigaDevice Semiconductor Inc. + + Redistribution and use in source and binary forms, with or without modification, +are permitted provided that the following conditions are met: - 2016-08-15, V1.0.0, firmware for GD32F4xx + 1. Redistributions of source code must retain the above copyright notice, this + list of conditions and the following disclaimer. + 2. Redistributions in binary form must reproduce the above copyright notice, + this list of conditions and the following disclaimer in the documentation + and/or other materials provided with the distribution. + 3. Neither the name of the copyright holder nor the names of its contributors + may be used to endorse or promote products derived from this software without + specific prior written permission. + + THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED +WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. +IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, +INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT +NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR +PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, +WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY +OF SUCH DAMAGE. */ #ifndef GD32F4XX_DMA_H @@ -123,10 +148,10 @@ #define DMA_CHXPADDR_PADDR BITS(0,31) /*!< peripheral base address */ /* DMA_CHxM0ADDR,x=0..7 */ -#define DMA_CHXM0ADDR_PADDR BITS(0,31) /*!< memory 0 base address */ +#define DMA_CHXM0ADDR_M0ADDR BITS(0,31) /*!< memory 0 base address */ /* DMA_CHxM1ADDR,x=0..7 */ -#define DMA_CHXM1ADDR_PADDR BITS(0,31) /*!< memory 1 base address */ +#define DMA_CHXM1ADDR_M0ADDR BITS(0,31) /*!< memory 1 base address */ /* DMA_CHxFCTL,x=0..7 */ #define DMA_CHXFCTL_FCCV BITS(0,1) /*!< FIFO counter critical value */ @@ -136,7 +161,7 @@ /* constants definitions */ /* DMA channel select */ -typedef enum +typedef enum { DMA_CH0 = 0, /*!< DMA Channel 0 */ DMA_CH1, /*!< DMA Channel 1 */ @@ -149,7 +174,7 @@ typedef enum } dma_channel_enum; /* DMA peripheral select */ -typedef enum +typedef enum { DMA_SUBPERI0 = 0, /*!< DMA Peripheral 0 */ DMA_SUBPERI1, /*!< DMA Peripheral 1 */ @@ -166,7 +191,7 @@ typedef struct { uint32_t periph_addr; /*!< peripheral base address */ uint32_t periph_width; /*!< transfer data size of peripheral */ - uint32_t periph_inc; /*!< peripheral increasing mode */ + uint32_t periph_inc; /*!< peripheral increasing mode */ uint32_t memory0_addr; /*!< memory 0 base address */ uint32_t memory_width; /*!< transfer data size of memory */ @@ -176,7 +201,7 @@ typedef struct uint32_t periph_burst_width; /*!< multi data mode enable */ uint32_t critical_value; /*!< FIFO critical */ - uint32_t circular_mode; + uint32_t circular_mode; /*!< DMA circular mode */ uint32_t direction; /*!< channel data transfer direction */ uint32_t number; /*!< channel transfer number */ uint32_t priority; /*!< channel priority level */ @@ -186,7 +211,7 @@ typedef struct typedef struct { uint32_t periph_addr; /*!< peripheral base address */ - uint32_t periph_inc; /*!< peripheral increasing mode */ + uint32_t periph_inc; /*!< peripheral increasing mode */ uint32_t memory0_addr; /*!< memory 0 base address */ uint32_t memory_inc; /*!< memory increasing mode */ @@ -296,85 +321,108 @@ typedef struct #define DMA_FIFO_STATUS_FULL ((uint32_t)0x00000005U) /*!< the data in the FIFO is full */ /* DMA reset value */ -#define DMA_CHCTL_RESET_VALUE ((uint32_t)0x00000000U) /*!< the reset value of DMA channel CHXCTL register */ -#define DMA_CHCNT_RESET_VALUE ((uint32_t)0x00000000U) /*!< the reset value of DMA channel CHXCNT register */ -#define DMA_CHPADDR_RESET_VALUE ((uint32_t)0x00000000U) /*!< the reset value of DMA channel CHXPADDR register */ -#define DMA_CHMADDR_RESET_VALUE ((uint32_t)0x00000000U) /*!< the reset value of DMA channel CHXMADDR register */ -#define DMA_CHINTF_RESET_VALUE ((uint32_t)0x0000003DU) /*!< clear DMA channel CHXINTFS register */ -#define DMA_CHFCTL_RESET_VALUE ((uint32_t)0x00000000U) /*!< the reset value of DMA channel CHXFCTL register */ +#define DMA_CHCTL_RESET_VALUE ((uint32_t)0x00000000U) /*!< the reset value of DMA channel CHXCTL register */ +#define DMA_CHCNT_RESET_VALUE ((uint32_t)0x00000000U) /*!< the reset value of DMA channel CHXCNT register */ +#define DMA_CHPADDR_RESET_VALUE ((uint32_t)0x00000000U) /*!< the reset value of DMA channel CHXPADDR register */ +#define DMA_CHMADDR_RESET_VALUE ((uint32_t)0x00000000U) /*!< the reset value of DMA channel CHXMADDR register */ +#define DMA_CHINTF_RESET_VALUE ((uint32_t)0x0000003DU) /*!< clear DMA channel CHXINTFS register */ +#define DMA_CHFCTL_RESET_VALUE ((uint32_t)0x00000000U) /*!< the reset value of DMA channel CHXFCTL register */ + +/* DMA_INTF register */ +/* interrupt flag bits */ +#define DMA_INT_FLAG_FEE DMA_INTF_FEEIF /*!< FIFO error and exception flag */ +#define DMA_INT_FLAG_SDE DMA_INTF_SDEIF /*!< single data mode exception flag */ +#define DMA_INT_FLAG_TAE DMA_INTF_TAEIF /*!< transfer access error flag */ +#define DMA_INT_FLAG_HTF DMA_INTF_HTFIF /*!< half transfer finish flag */ +#define DMA_INT_FLAG_FTF DMA_INTF_FTFIF /*!< full transfer finish flag */ + +/* flag bits */ +#define DMA_FLAG_FEE DMA_INTF_FEEIF /*!< FIFO error and exception flag */ +#define DMA_FLAG_SDE DMA_INTF_SDEIF /*!< single data mode exception flag */ +#define DMA_FLAG_TAE DMA_INTF_TAEIF /*!< transfer access error flag */ +#define DMA_FLAG_HTF DMA_INTF_HTFIF /*!< half transfer finish flag */ +#define DMA_FLAG_FTF DMA_INTF_FTFIF /*!< full transfer finish flag */ + /* function declarations */ +/* DMA deinitialization and initialization functions */ /* deinitialize DMA a channel registers */ -void dma_deinit(uint32_t dma_periph,dma_channel_enum channelx); +void dma_deinit(uint32_t dma_periph, dma_channel_enum channelx); +/* initialize the DMA single data mode parameters struct with the default values */ +void dma_single_data_para_struct_init(dma_single_data_parameter_struct* init_struct); +/* initialize the DMA multi data mode parameters struct with the default values */ +void dma_multi_data_para_struct_init(dma_multi_data_parameter_struct* init_struct); /* DMA single data mode initialize */ -void dma_single_data_mode_init(uint32_t dma_periph,dma_channel_enum channelx,dma_single_data_parameter_struct init_struct); +void dma_single_data_mode_init(uint32_t dma_periph, dma_channel_enum channelx, dma_single_data_parameter_struct* init_struct); /* DMA multi data mode initialize */ -void dma_multi_data_mode_init(uint32_t dma_periph,dma_channel_enum channelx,dma_multi_data_parameter_struct init_struct); +void dma_multi_data_mode_init(uint32_t dma_periph, dma_channel_enum channelx, dma_multi_data_parameter_struct* init_struct); +/* DMA configuration functions */ /* set DMA peripheral base address */ -void dma_periph_address_config(uint32_t dma_periph,dma_channel_enum channelx,uint32_t address); +void dma_periph_address_config(uint32_t dma_periph, dma_channel_enum channelx, uint32_t address); /* set DMA Memory base address */ -void dma_memory_address_config(uint32_t dma_periph,dma_channel_enum channelx,uint8_t memory_flag,uint32_t address); +void dma_memory_address_config(uint32_t dma_periph, dma_channel_enum channelx, uint8_t memory_flag, uint32_t address); /* set the number of remaining data to be transferred by the DMA */ -void dma_transfer_number_config(uint32_t dma_periph,dma_channel_enum channelx,uint32_t number); +void dma_transfer_number_config(uint32_t dma_periph,dma_channel_enum channelx, uint32_t number); /* get the number of remaining data to be transferred by the DMA */ -uint32_t dma_transfer_number_get(uint32_t dma_periph,dma_channel_enum channelx); +uint32_t dma_transfer_number_get(uint32_t dma_periph, dma_channel_enum channelx); /* configure priority level of DMA channel */ -void dma_priority_config(uint32_t dma_periph,dma_channel_enum channelx,uint32_t priority); +void dma_priority_config(uint32_t dma_periph, dma_channel_enum channelx, uint32_t priority); /* configure transfer burst beats of memory */ -void dma_memory_burst_beats_config (uint32_t dma_periph,dma_channel_enum channelx,uint32_t mbeat); +void dma_memory_burst_beats_config (uint32_t dma_periph, dma_channel_enum channelx, uint32_t mbeat); /* configure transfer burst beats of peripheral */ -void dma_periph_burst_beats_config (uint32_t dma_periph,dma_channel_enum channelx,uint32_t pbeat); +void dma_periph_burst_beats_config (uint32_t dma_periph, dma_channel_enum channelx, uint32_t pbeat); /* configure transfer data size of memory */ -void dma_memory_width_config (uint32_t dma_periph,dma_channel_enum channelx,uint32_t msize); +void dma_memory_width_config (uint32_t dma_periph, dma_channel_enum channelx, uint32_t msize); /* configure transfer data size of peripheral */ -void dma_periph_width_config (uint32_t dma_periph,dma_channel_enum channelx,uint32_t psize); +void dma_periph_width_config (uint32_t dma_periph, dma_channel_enum channelx, uint32_t psize); /* configure next address increasement algorithm of memory */ -void dma_memory_address_generation_config(uint32_t dma_periph,dma_channel_enum channelx,uint8_t generation_algorithm); +void dma_memory_address_generation_config(uint32_t dma_periph, dma_channel_enum channelx, uint8_t generation_algorithm); /* configure next address increasement algorithm of peripheral */ -void dma_peripheral_address_generation_config(uint32_t dma_periph,dma_channel_enum channelx,uint8_t generation_algorithm); +void dma_peripheral_address_generation_config(uint32_t dma_periph, dma_channel_enum channelx, uint8_t generation_algorithm); /* enable DMA circulation mode */ -void dma_circulation_enable(uint32_t dma_periph,dma_channel_enum channelx); +void dma_circulation_enable(uint32_t dma_periph, dma_channel_enum channelx); /* disable DMA circulation mode */ -void dma_circulation_disable(uint32_t dma_periph,dma_channel_enum channelx); +void dma_circulation_disable(uint32_t dma_periph, dma_channel_enum channelx); /* enable DMA channel */ -void dma_channel_enable(uint32_t dma_periph,dma_channel_enum channelx); +void dma_channel_enable(uint32_t dma_periph, dma_channel_enum channelx); /* disable DMA channel */ -void dma_channel_disable(uint32_t dma_periph,dma_channel_enum channelx); +void dma_channel_disable(uint32_t dma_periph, dma_channel_enum channelx); /* configure the direction of data transfer on the channel */ -void dma_transfer_direction_config(uint32_t dma_periph,dma_channel_enum channelx,uint8_t direction); +void dma_transfer_direction_config(uint32_t dma_periph, dma_channel_enum channelx, uint8_t direction); /* DMA switch buffer mode config */ -void dma_switch_buffer_mode_config(uint32_t dma_periph,dma_channel_enum channelx,uint32_t memory1_addr,uint32_t memory_select); +void dma_switch_buffer_mode_config(uint32_t dma_periph, dma_channel_enum channelx, uint32_t memory1_addr, uint32_t memory_select); /* DMA using memory get */ -uint32_t dma_using_memory_get(uint32_t dma_periph,dma_channel_enum channelx); +uint32_t dma_using_memory_get(uint32_t dma_periph, dma_channel_enum channelx); /* DMA channel peripheral select */ -void dma_channel_subperipheral_select(uint32_t dma_periph,dma_channel_enum channelx,dma_subperipheral_enum sub_periph); +void dma_channel_subperipheral_select(uint32_t dma_periph, dma_channel_enum channelx, dma_subperipheral_enum sub_periph); /* DMA flow controller configure */ -void dma_flow_controller_config(uint32_t dma_periph,dma_channel_enum channelx,uint32_t controller); +void dma_flow_controller_config(uint32_t dma_periph, dma_channel_enum channelx, uint32_t controller); /* DMA flow controller enable */ -void dma_switch_buffer_mode_enable(uint32_t dma_periph,dma_channel_enum channelx,ControlStatus newvalue); +void dma_switch_buffer_mode_enable(uint32_t dma_periph, dma_channel_enum channelx, ControlStatus newvalue); /* DMA FIFO status get */ -uint32_t dma_fifo_status_get(uint32_t dma_periph,dma_channel_enum channelx); +uint32_t dma_fifo_status_get(uint32_t dma_periph, dma_channel_enum channelx); +/* flag and interrupt functions */ /* check DMA flag is set or not */ -FlagStatus dma_flag_get(uint32_t dma_periph,dma_channel_enum channelx,uint32_t flag); +FlagStatus dma_flag_get(uint32_t dma_periph, dma_channel_enum channelx, uint32_t flag); /* clear DMA a channel flag */ -void dma_flag_clear(uint32_t dma_periph,dma_channel_enum channelx,uint32_t flag); +void dma_flag_clear(uint32_t dma_periph, dma_channel_enum channelx, uint32_t flag); /* check DMA flag is set or not */ -FlagStatus dma_interrupt_flag_get(uint32_t dma_periph,dma_channel_enum channelx,uint32_t interrupt); +FlagStatus dma_interrupt_flag_get(uint32_t dma_periph, dma_channel_enum channelx, uint32_t interrupt); /* clear DMA a channel flag */ -void dma_interrupt_flag_clear(uint32_t dma_periph,dma_channel_enum channelx,uint32_t interrupt); +void dma_interrupt_flag_clear(uint32_t dma_periph, dma_channel_enum channelx, uint32_t interrupt); /* enable DMA interrupt */ -void dma_interrupt_enable(uint32_t dma_periph,dma_channel_enum channelx,uint32_t source); +void dma_interrupt_enable(uint32_t dma_periph, dma_channel_enum channelx, uint32_t source); /* disable DMA interrupt */ -void dma_interrupt_disable(uint32_t dma_periph,dma_channel_enum channelx,uint32_t source); +void dma_interrupt_disable(uint32_t dma_periph, dma_channel_enum channelx, uint32_t source); #endif /* GD32F4XX_DMA_H */ diff --git a/bsp/gd32450z-eval/Libraries/GD32F4xx_standard_peripheral/Include/gd32f4xx_enet.h b/bsp/gd32450z-eval/Libraries/GD32F4xx_standard_peripheral/Include/gd32f4xx_enet.h index 7a0de03860..1dfc880d37 100644 --- a/bsp/gd32450z-eval/Libraries/GD32F4xx_standard_peripheral/Include/gd32f4xx_enet.h +++ b/bsp/gd32450z-eval/Libraries/GD32F4xx_standard_peripheral/Include/gd32f4xx_enet.h @@ -1,12 +1,37 @@ /*! - \file gd32f4xx_enet.h - \brief definitions for the ENET + \file gd32f4xx_enet.h + \brief definitions for the ENET + + \version 2016-08-15, V1.0.0, firmware for GD32F4xx + \version 2018-12-12, V2.0.0, firmware for GD32F4xx + \version 2020-09-30, V2.1.0, firmware for GD32F4xx */ /* - Copyright (C) 2016 GigaDevice + Copyright (c) 2020, GigaDevice Semiconductor Inc. + + Redistribution and use in source and binary forms, with or without modification, +are permitted provided that the following conditions are met: + + 1. Redistributions of source code must retain the above copyright notice, this + list of conditions and the following disclaimer. + 2. Redistributions in binary form must reproduce the above copyright notice, + this list of conditions and the following disclaimer in the documentation + and/or other materials provided with the distribution. + 3. Neither the name of the copyright holder nor the names of its contributors + may be used to endorse or promote products derived from this software without + specific prior written permission. - 2016-08-15, V1.0.1, firmware for GD32F4xx + THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED +WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. +IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, +INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT +NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR +PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, +WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY +OF SUCH DAMAGE. */ #ifndef GD32F4XX_ENET_H @@ -36,7 +61,7 @@ #define ENET_TXBUF_SIZE ENET_MAX_FRAME_SIZE /*!< ethernet transmit buffer size */ #endif -//#define SELECT_DESCRIPTORS_ENHANCED_MODE +//#define SELECT_DESCRIPTORS_ENHANCED_MODE //#define USE_DELAY @@ -47,7 +72,7 @@ #define PHY_ADDRESS ((uint16_t)1U) /*!< phy address determined by the hardware */ -/* PHY read write timeouts */ +/* PHY read write timeouts */ #define PHY_READ_TO ((uint32_t)0x0004FFFFU) /*!< PHY read timeout */ #define PHY_WRITE_TO ((uint32_t)0x0004FFFFU) /*!< PHY write timeout */ @@ -55,7 +80,7 @@ #define PHY_RESETDELAY ((uint32_t)0x008FFFFFU) /*!< PHY reset delay */ #define PHY_CONFIGDELAY ((uint32_t)0x00FFFFFFU) /*!< PHY configure delay */ -/* PHY register address */ +/* PHY register address */ #define PHY_REG_BCR 0U /*!< tranceiver basic control register */ #define PHY_REG_BSR 1U /*!< tranceiver basic status register */ @@ -76,7 +101,7 @@ #define PHY_LINKED_STATUS ((uint16_t)0x0004) /*!< valid link established */ #define PHY_JABBER_DETECTION ((uint16_t)0x0002) /*!< jabber condition detected */ -#if(PHY_TYPE == LAN8700) +#if(PHY_TYPE == LAN8700) #define PHY_SR 31U /*!< tranceiver status register */ #define PHY_SPEED_STATUS ((uint16_t)0x0004) /*!< configured information of speed: 10Mbit/s */ #define PHY_DUPLEX_STATUS ((uint16_t)0x0010) /*!< configured information of duplex: full-duplex */ @@ -93,55 +118,55 @@ #define ENET ENET_BASE /* registers definitions */ -#define ENET_MAC_CFG REG32((ENET) + 0x00U) /*!< ethernet MAC configuration register */ -#define ENET_MAC_FRMF REG32((ENET) + 0x04U) /*!< ethernet MAC frame filter register */ -#define ENET_MAC_HLH REG32((ENET) + 0x08U) /*!< ethernet MAC hash list high register */ -#define ENET_MAC_HLL REG32((ENET) + 0x0CU) /*!< ethernet MAC hash list low register */ -#define ENET_MAC_PHY_CTL REG32((ENET) + 0x10U) /*!< ethernet MAC PHY control register */ -#define ENET_MAC_PHY_DATA REG32((ENET) + 0x14U) /*!< ethernet MAC MII data register */ -#define ENET_MAC_FCTL REG32((ENET) + 0x18U) /*!< ethernet MAC flow control register */ -#define ENET_MAC_VLT REG32((ENET) + 0x1CU) /*!< ethernet MAC VLAN tag register */ -#define ENET_MAC_RWFF REG32((ENET) + 0x28U) /*!< ethernet MAC remote wakeup frame filter register */ -#define ENET_MAC_WUM REG32((ENET) + 0x2CU) /*!< ethernet MAC wakeup management register */ -#define ENET_MAC_DBG REG32((ENET) + 0x34U) /*!< ethernet MAC debug register */ -#define ENET_MAC_INTF REG32((ENET) + 0x38U) /*!< ethernet MAC interrupt flag register */ -#define ENET_MAC_INTMSK REG32((ENET) + 0x3CU) /*!< ethernet MAC interrupt mask register */ -#define ENET_MAC_ADDR0H REG32((ENET) + 0x40U) /*!< ethernet MAC address 0 high register */ -#define ENET_MAC_ADDR0L REG32((ENET) + 0x44U) /*!< ethernet MAC address 0 low register */ -#define ENET_MAC_ADDR1H REG32((ENET) + 0x48U) /*!< ethernet MAC address 1 high register */ -#define ENET_MAC_ADDR1L REG32((ENET) + 0x4CU) /*!< ethernet MAC address 1 low register */ -#define ENET_MAC_ADDT2H REG32((ENET) + 0x50U) /*!< ethernet MAC address 2 high register */ -#define ENET_MAC_ADDR2L REG32((ENET) + 0x54U) /*!< ethernet MAC address 2 low register */ -#define ENET_MAC_ADDR3H REG32((ENET) + 0x58U) /*!< ethernet MAC address 3 high register */ -#define ENET_MAC_ADDR3L REG32((ENET) + 0x5CU) /*!< ethernet MAC address 3 low register */ +#define ENET_MAC_CFG REG32((ENET) + 0x0000U) /*!< ethernet MAC configuration register */ +#define ENET_MAC_FRMF REG32((ENET) + 0x0004U) /*!< ethernet MAC frame filter register */ +#define ENET_MAC_HLH REG32((ENET) + 0x0008U) /*!< ethernet MAC hash list high register */ +#define ENET_MAC_HLL REG32((ENET) + 0x000CU) /*!< ethernet MAC hash list low register */ +#define ENET_MAC_PHY_CTL REG32((ENET) + 0x0010U) /*!< ethernet MAC PHY control register */ +#define ENET_MAC_PHY_DATA REG32((ENET) + 0x0014U) /*!< ethernet MAC MII data register */ +#define ENET_MAC_FCTL REG32((ENET) + 0x0018U) /*!< ethernet MAC flow control register */ +#define ENET_MAC_VLT REG32((ENET) + 0x001CU) /*!< ethernet MAC VLAN tag register */ +#define ENET_MAC_RWFF REG32((ENET) + 0x0028U) /*!< ethernet MAC remote wakeup frame filter register */ +#define ENET_MAC_WUM REG32((ENET) + 0x002CU) /*!< ethernet MAC wakeup management register */ +#define ENET_MAC_DBG REG32((ENET) + 0x0034U) /*!< ethernet MAC debug register */ +#define ENET_MAC_INTF REG32((ENET) + 0x0038U) /*!< ethernet MAC interrupt flag register */ +#define ENET_MAC_INTMSK REG32((ENET) + 0x003CU) /*!< ethernet MAC interrupt mask register */ +#define ENET_MAC_ADDR0H REG32((ENET) + 0x0040U) /*!< ethernet MAC address 0 high register */ +#define ENET_MAC_ADDR0L REG32((ENET) + 0x0044U) /*!< ethernet MAC address 0 low register */ +#define ENET_MAC_ADDR1H REG32((ENET) + 0x0048U) /*!< ethernet MAC address 1 high register */ +#define ENET_MAC_ADDR1L REG32((ENET) + 0x004CU) /*!< ethernet MAC address 1 low register */ +#define ENET_MAC_ADDT2H REG32((ENET) + 0x0050U) /*!< ethernet MAC address 2 high register */ +#define ENET_MAC_ADDR2L REG32((ENET) + 0x0054U) /*!< ethernet MAC address 2 low register */ +#define ENET_MAC_ADDR3H REG32((ENET) + 0x0058U) /*!< ethernet MAC address 3 high register */ +#define ENET_MAC_ADDR3L REG32((ENET) + 0x005CU) /*!< ethernet MAC address 3 low register */ #define ENET_MAC_FCTH REG32((ENET) + 0x1080U) /*!< ethernet MAC flow control threshold register */ -#define ENET_MSC_CTL REG32((ENET) + 0x100U) /*!< ethernet MSC control register */ -#define ENET_MSC_RINTF REG32((ENET) + 0x104U) /*!< ethernet MSC receive interrupt flag register */ -#define ENET_MSC_TINTF REG32((ENET) + 0x108U) /*!< ethernet MSC transmit interrupt flag register */ -#define ENET_MSC_RINTMSK REG32((ENET) + 0x10CU) /*!< ethernet MSC receive interrupt mask register */ -#define ENET_MSC_TINTMSK REG32((ENET) + 0x110U) /*!< ethernet MSC transmit interrupt mask register */ -#define ENET_MSC_SCCNT REG32((ENET) + 0x14CU) /*!< ethernet MSC transmitted good frames after a single collision counter register */ -#define ENET_MSC_MSCCNT REG32((ENET) + 0x150U) /*!< ethernet MSC transmitted good frames after more than a single collision counter register */ -#define ENET_MSC_TGFCNT REG32((ENET) + 0x168U) /*!< ethernet MSC transmitted good frames counter register */ -#define ENET_MSC_RFCECNT REG32((ENET) + 0x194U) /*!< ethernet MSC received frames with CRC error counter register */ -#define ENET_MSC_RFAECNT REG32((ENET) + 0x198U) /*!< ethernet MSC received frames with alignment error counter register */ -#define ENET_MSC_RGUFCNT REG32((ENET) + 0x1C4U) /*!< ethernet MSC received good unicast frames counter register */ +#define ENET_MSC_CTL REG32((ENET) + 0x0100U) /*!< ethernet MSC control register */ +#define ENET_MSC_RINTF REG32((ENET) + 0x0104U) /*!< ethernet MSC receive interrupt flag register */ +#define ENET_MSC_TINTF REG32((ENET) + 0x0108U) /*!< ethernet MSC transmit interrupt flag register */ +#define ENET_MSC_RINTMSK REG32((ENET) + 0x010CU) /*!< ethernet MSC receive interrupt mask register */ +#define ENET_MSC_TINTMSK REG32((ENET) + 0x0110U) /*!< ethernet MSC transmit interrupt mask register */ +#define ENET_MSC_SCCNT REG32((ENET) + 0x014CU) /*!< ethernet MSC transmitted good frames after a single collision counter register */ +#define ENET_MSC_MSCCNT REG32((ENET) + 0x0150U) /*!< ethernet MSC transmitted good frames after more than a single collision counter register */ +#define ENET_MSC_TGFCNT REG32((ENET) + 0x0168U) /*!< ethernet MSC transmitted good frames counter register */ +#define ENET_MSC_RFCECNT REG32((ENET) + 0x0194U) /*!< ethernet MSC received frames with CRC error counter register */ +#define ENET_MSC_RFAECNT REG32((ENET) + 0x0198U) /*!< ethernet MSC received frames with alignment error counter register */ +#define ENET_MSC_RGUFCNT REG32((ENET) + 0x01C4U) /*!< ethernet MSC received good unicast frames counter register */ -#define ENET_PTP_TSCTL REG32((ENET) + 0x700U) /*!< ethernet PTP time stamp control register */ -#define ENET_PTP_SSINC REG32((ENET) + 0x704U) /*!< ethernet PTP subsecond increment register */ -#define ENET_PTP_TSH REG32((ENET) + 0x708U) /*!< ethernet PTP time stamp high register */ -#define ENET_PTP_TSL REG32((ENET) + 0x70CU) /*!< ethernet PTP time stamp low register */ -#define ENET_PTP_TSUH REG32((ENET) + 0x710U) /*!< ethernet PTP time stamp update high register */ -#define ENET_PTP_TSUL REG32((ENET) + 0x714U) /*!< ethernet PTP time stamp update low register */ -#define ENET_PTP_TSADDEND REG32((ENET) + 0x718U) /*!< ethernet PTP time stamp addend register */ -#define ENET_PTP_ETH REG32((ENET) + 0x71CU) /*!< ethernet PTP expected time high register */ -#define ENET_PTP_ETL REG32((ENET) + 0x720U) /*!< ethernet PTP expected time low register */ -#define ENET_PTP_TSF REG32((ENET) + 0x728U) /*!< ethernet PTP time stamp flag register */ -#define ENET_PTP_PPSCTL REG32((ENET) + 0x72CU) /*!< ethernet PTP PPS control register */ +#define ENET_PTP_TSCTL REG32((ENET) + 0x0700U) /*!< ethernet PTP time stamp control register */ +#define ENET_PTP_SSINC REG32((ENET) + 0x0704U) /*!< ethernet PTP subsecond increment register */ +#define ENET_PTP_TSH REG32((ENET) + 0x0708U) /*!< ethernet PTP time stamp high register */ +#define ENET_PTP_TSL REG32((ENET) + 0x070CU) /*!< ethernet PTP time stamp low register */ +#define ENET_PTP_TSUH REG32((ENET) + 0x0710U) /*!< ethernet PTP time stamp update high register */ +#define ENET_PTP_TSUL REG32((ENET) + 0x0714U) /*!< ethernet PTP time stamp update low register */ +#define ENET_PTP_TSADDEND REG32((ENET) + 0x0718U) /*!< ethernet PTP time stamp addend register */ +#define ENET_PTP_ETH REG32((ENET) + 0x071CU) /*!< ethernet PTP expected time high register */ +#define ENET_PTP_ETL REG32((ENET) + 0x0720U) /*!< ethernet PTP expected time low register */ +#define ENET_PTP_TSF REG32((ENET) + 0x0728U) /*!< ethernet PTP time stamp flag register */ +#define ENET_PTP_PPSCTL REG32((ENET) + 0x072CU) /*!< ethernet PTP PPS control register */ #define ENET_DMA_BCTL REG32((ENET) + 0x1000U) /*!< ethernet DMA bus control register */ -#define ENET_DMA_TPEN REG32((ENET) + 0x1004U) /*!< ethernet DMA transmit poll enable register */ +#define ENET_DMA_TPEN REG32((ENET) + 0x1004U) /*!< ethernet DMA transmit poll enable register */ #define ENET_DMA_RPEN REG32((ENET) + 0x1008U) /*!< ethernet DMA receive poll enable register */ #define ENET_DMA_RDTADDR REG32((ENET) + 0x100CU) /*!< ethernet DMA receive descriptor table address register */ #define ENET_DMA_TDTADDR REG32((ENET) + 0x1010U) /*!< ethernet DMA transmit descriptor table address register */ @@ -150,7 +175,7 @@ #define ENET_DMA_INTEN REG32((ENET) + 0x101CU) /*!< ethernet DMA interrupt enable register */ #define ENET_DMA_MFBOCNT REG32((ENET) + 0x1020U) /*!< ethernet DMA missed frame and buffer overflow counter register */ #define ENET_DMA_RSWDC REG32((ENET) + 0x1024U) /*!< ethernet DMA receive state watchdog counter register */ -#define ENET_DMA_CTDADDR REG32((ENET) + 0x1048U) /*!< ethernet DMA current transmit descriptor address register */ +#define ENET_DMA_CTDADDR REG32((ENET) + 0x1048U) /*!< ethernet DMA current transmit descriptor address register */ #define ENET_DMA_CRDADDR REG32((ENET) + 0x104CU) /*!< ethernet DMA current receive descriptor address register */ #define ENET_DMA_CTBADDR REG32((ENET) + 0x1050U) /*!< ethernet DMA current transmit buffer address register */ #define ENET_DMA_CRBADDR REG32((ENET) + 0x1054U) /*!< ethernet DMA current receive buffer address register */ @@ -169,7 +194,7 @@ #define ENET_MAC_CFG_ROD BIT(13) /*!< receive own disable */ #define ENET_MAC_CFG_SPD BIT(14) /*!< fast eneternet speed */ #define ENET_MAC_CFG_CSD BIT(16) /*!< carrier sense disable */ -#define ENET_MAC_CFG_IGBS BITS(17,19) /*!< inter-frame gap bit selection */ +#define ENET_MAC_CFG_IGBS BITS(17,19) /*!< inter-frame gap bit selection */ #define ENET_MAC_CFG_JBD BIT(22) /*!< jabber disable */ #define ENET_MAC_CFG_WDD BIT(23) /*!< watchdog disable */ #define ENET_MAC_CFG_TFCD BIT(25) /*!< type frame CRC dropping */ @@ -177,49 +202,49 @@ /* ENET_MAC_FRMF */ #define ENET_MAC_FRMF_PM BIT(0) /*!< promiscuous mode */ #define ENET_MAC_FRMF_HUF BIT(1) /*!< hash unicast filter */ -#define ENET_MAC_FRMF_HMF BIT(2) /*!< hash multicast filter */ -#define ENET_MAC_FRMF_DAIFLT BIT(3) /*!< destination address inverse filtering enable */ -#define ENET_MAC_FRMF_MFD BIT(4) /*!< multicast filter disable */ -#define ENET_MAC_FRMF_BFRMD BIT(5) /*!< broadcast frame disable */ -#define ENET_MAC_FRMF_PCFRM BITS(6,7) /*!< pass control frames */ -#define ENET_MAC_FRMF_SAIFLT BIT(8) /*!< source address inverse filtering */ -#define ENET_MAC_FRMF_SAFLT BIT(9) /*!< source address filter */ -#define ENET_MAC_FRMF_HPFLT BIT(10) /*!< hash or perfect filter */ -#define ENET_MAC_FRMF_FAR BIT(31) /*!< frames all receive */ - +#define ENET_MAC_FRMF_HMF BIT(2) /*!< hash multicast filter */ +#define ENET_MAC_FRMF_DAIFLT BIT(3) /*!< destination address inverse filtering enable */ +#define ENET_MAC_FRMF_MFD BIT(4) /*!< multicast filter disable */ +#define ENET_MAC_FRMF_BFRMD BIT(5) /*!< broadcast frame disable */ +#define ENET_MAC_FRMF_PCFRM BITS(6,7) /*!< pass control frames */ +#define ENET_MAC_FRMF_SAIFLT BIT(8) /*!< source address inverse filtering */ +#define ENET_MAC_FRMF_SAFLT BIT(9) /*!< source address filter */ +#define ENET_MAC_FRMF_HPFLT BIT(10) /*!< hash or perfect filter */ +#define ENET_MAC_FRMF_FAR BIT(31) /*!< frames all receive */ + /* ENET_MAC_HLH */ #define ENET_MAC_HLH_HLH BITS(0,31) /*!< hash list high */ - + /* ENET_MAC_HLL */ #define ENET_MAC_HLL_HLL BITS(0,31) /*!< hash list low */ - + /* ENET_MAC_PHY_CTL */ -#define ENET_MAC_PHY_CTL_PB BIT(0) /*!< PHY busy */ -#define ENET_MAC_PHY_CTL_PW BIT(1) /*!< PHY write */ -#define ENET_MAC_PHY_CTL_CLR BITS(2,4) /*!< clock range */ -#define ENET_MAC_PHY_CTL_PR BITS(6,10) /*!< PHY register */ -#define ENET_MAC_PHY_CTL_PA BITS(11,15) /*!< PHY address */ - +#define ENET_MAC_PHY_CTL_PB BIT(0) /*!< PHY busy */ +#define ENET_MAC_PHY_CTL_PW BIT(1) /*!< PHY write */ +#define ENET_MAC_PHY_CTL_CLR BITS(2,4) /*!< clock range */ +#define ENET_MAC_PHY_CTL_PR BITS(6,10) /*!< PHY register */ +#define ENET_MAC_PHY_CTL_PA BITS(11,15) /*!< PHY address */ + /* ENET_MAC_PHY_DATA */ #define ENET_MAC_PHY_DATA_PD BITS(0,15) /*!< PHY data */ - + /* ENET_MAC_FCTL */ #define ENET_MAC_FCTL_FLCBBKPA BIT(0) /*!< flow control busy(in full duplex mode)/backpressure activate(in half duplex mode) */ #define ENET_MAC_FCTL_TFCEN BIT(1) /*!< transmit flow control enable */ #define ENET_MAC_FCTL_RFCEN BIT(2) /*!< receive flow control enable */ #define ENET_MAC_FCTL_UPFDT BIT(3) /*!< unicast pause frame detect */ -#define ENET_MAC_FCTL_PLTS BITS(4,5) /*!< pause low threshold */ +#define ENET_MAC_FCTL_PLTS BITS(4,5) /*!< pause low threshold */ #define ENET_MAC_FCTL_DZQP BIT(7) /*!< disable zero-quanta pause */ #define ENET_MAC_FCTL_PTM BITS(16,31) /*!< pause time */ - + /* ENET_MAC_VLT */ #define ENET_MAC_VLT_VLTI BITS(0,15) /*!< VLAN tag identifier(for receive frames) */ #define ENET_MAC_VLT_VLTC BIT(16) /*!< 12-bit VLAN tag comparison */ - + /* ENET_MAC_RWFF */ #define ENET_MAC_RWFF_DATA BITS(0,31) /*!< wakeup frame filter register data */ - -/* ENET_MAC_WUM */ + +/* ENET_MAC_WUM */ #define ENET_MAC_WUM_PWD BIT(0) /*!< power down */ #define ENET_MAC_WUM_MPEN BIT(1) /*!< magic packet enable */ #define ENET_MAC_WUM_WFEN BIT(2) /*!< wakeup frame enable */ @@ -228,7 +253,7 @@ #define ENET_MAC_WUM_GU BIT(9) /*!< global unicast */ #define ENET_MAC_WUM_WUFFRPR BIT(31) /*!< wakeup frame filter register pointer reset */ -/* ENET_MAC_DBG */ +/* ENET_MAC_DBG */ #define ENET_MAC_DBG_MRNI BIT(0) /*!< MAC receive state not idle */ #define ENET_MAC_DBG_RXAFS BITS(1,2) /*!< Rx asynchronous FIFO status */ #define ENET_MAC_DBG_RXFW BIT(4) /*!< RxFIFO is writing */ @@ -242,7 +267,7 @@ #define ENET_MAC_DBG_TXFNE BIT(24) /*!< TxFIFO not empty flag */ #define ENET_MAC_DBG_TXFF BIT(25) /*!< TxFIFO full flag */ -/* ENET_MAC_INTF */ +/* ENET_MAC_INTF */ #define ENET_MAC_INTF_WUM BIT(3) /*!< WUM status */ #define ENET_MAC_INTF_MSC BIT(4) /*!< MSC status */ #define ENET_MAC_INTF_MSCR BIT(5) /*!< MSC receive status */ @@ -256,28 +281,28 @@ /* ENET_MAC_ADDR0H */ #define ENET_MAC_ADDR0H_ADDR0H BITS(0,15) /*!< MAC address0 high */ #define ENET_MAC_ADDR0H_MO BIT(31) /*!< always read 1 and must be kept */ - + /* ENET_MAC_ADDR0L */ #define ENET_MAC_ADDR0L_ADDR0L BITS(0,31) /*!< MAC address0 low */ - + /* ENET_MAC_ADDR1H */ #define ENET_MAC_ADDR1H_ADDR1H BITS(0,15) /*!< MAC address1 high */ -#define ENET_MAC_ADDR1H_MB BITS(24,29) /*!< mask byte */ +#define ENET_MAC_ADDR1H_MB BITS(24,29) /*!< mask byte */ #define ENET_MAC_ADDR1H_SAF BIT(30) /*!< source address filter */ #define ENET_MAC_ADDR1H_AFE BIT(31) /*!< address filter enable */ - + /* ENET_MAC_ADDR1L */ #define ENET_MAC_ADDR1L_ADDR1L BITS(0,31) /*!< MAC address1 low */ - + /* ENET_MAC_ADDR2H */ #define ENET_MAC_ADDR2H_ADDR2H BITS(0,15) /*!< MAC address2 high */ #define ENET_MAC_ADDR2H_MB BITS(24,29) /*!< mask byte */ #define ENET_MAC_ADDR2H_SAF BIT(30) /*!< source address filter */ #define ENET_MAC_ADDR2H_AFE BIT(31) /*!< address filter enable */ - + /* ENET_MAC_ADDR2L */ #define ENET_MAC_ADDR2L_ADDR2L BITS(0,31) /*!< MAC address2 low */ - + /* ENET_MAC_ADDR3H */ #define ENET_MAC_ADDR3H_ADDR3H BITS(0,15) /*!< MAC address3 high */ #define ENET_MAC_ADDR3H_MB BITS(24,29) /*!< mask byte */ @@ -286,11 +311,11 @@ /* ENET_MAC_ADDR3L */ #define ENET_MAC_ADDR3L_ADDR3L BITS(0,31) /*!< MAC address3 low */ - + /* ENET_MAC_FCTH */ #define ENET_MAC_FCTH_RFA BITS(0,2) /*!< threshold of active flow control */ #define ENET_MAC_FCTH_RFD BITS(4,6) /*!< threshold of deactive flow control */ - + /* ENET_MSC_CTL */ #define ENET_MSC_CTL_CTR BIT(0) /*!< counter reset */ #define ENET_MSC_CTL_CTSR BIT(1) /*!< counter stop rollover */ @@ -303,7 +328,7 @@ #define ENET_MSC_RINTF_RFCE BIT(5) /*!< received frames CRC error */ #define ENET_MSC_RINTF_RFAE BIT(6) /*!< received frames alignment error */ #define ENET_MSC_RINTF_RGUF BIT(17) /*!< receive good unicast frames */ - + /* ENET_MSC_TINTF */ #define ENET_MSC_TINTF_TGFSC BIT(14) /*!< transmitted good frames single collision */ #define ENET_MSC_TINTF_TGFMSC BIT(15) /*!< transmitted good frames more single collision */ @@ -313,30 +338,30 @@ #define ENET_MSC_RINTMSK_RFCEIM BIT(5) /*!< received frame CRC error interrupt mask */ #define ENET_MSC_RINTMSK_RFAEIM BIT(6) /*!< received frames alignment error interrupt mask */ #define ENET_MSC_RINTMSK_RGUFIM BIT(17) /*!< received good unicast frames interrupt mask */ - + /* ENET_MSC_TINTMSK */ #define ENET_MSC_TINTMSK_TGFSCIM BIT(14) /*!< transmitted good frames single collision interrupt mask */ #define ENET_MSC_TINTMSK_TGFMSCIM BIT(15) /*!< transmitted good frames more single collision interrupt mask */ #define ENET_MSC_TINTMSK_TGFIM BIT(21) /*!< transmitted good frames interrupt mask */ - + /* ENET_MSC_SCCNT */ #define ENET_MSC_SCCNT_SCC BITS(0,31) /*!< transmitted good frames single collision counter */ - + /* ENET_MSC_MSCCNT */ #define ENET_MSC_MSCCNT_MSCC BITS(0,31) /*!< transmitted good frames more one single collision counter */ - + /* ENET_MSC_TGFCNT */ #define ENET_MSC_TGFCNT_TGF BITS(0,31) /*!< transmitted good frames counter */ - + /* ENET_MSC_RFCECNT */ #define ENET_MSC_RFCECNT_RFCER BITS(0,31) /*!< received frames with CRC error counter */ - + /* ENET_MSC_RFAECNT */ #define ENET_MSC_RFAECNT_RFAER BITS(0,31) /*!< received frames alignment error counter */ - + /* ENET_MSC_RGUFCNT */ #define ENET_MSC_RGUFCNT_RGUF BITS(0,31) /*!< received good unicast frames counter */ - + /* ENET_PTP_TSCTL */ #define PTP_TSCTL_CKNT(regval) (BITS(16,17) & ((uint32_t)(regval) << 16)) /*!< write value to ENET_PTP_TSCTL_CKNT bit field */ @@ -356,37 +381,37 @@ #define ENET_PTP_TSCTL_MNMSEN BIT(15) /*!< received master node message snapshot enable */ #define ENET_PTP_TSCTL_CKNT BITS(16,17) /*!< clock node type for time stamp */ #define ENET_PTP_TSCTL_MAFEN BIT(18) /*!< MAC address filter enable for PTP frame */ - + /* ENET_PTP_SSINC */ #define ENET_PTP_SSINC_STMSSI BITS(0,7) /*!< system time subsecond increment */ - + /* ENET_PTP_TSH */ #define ENET_PTP_TSH_STMS BITS(0,31) /*!< system time second */ - + /* ENET_PTP_TSL */ #define ENET_PTP_TSL_STMSS BITS(0,30) /*!< system time subseconds */ #define ENET_PTP_TSL_STS BIT(31) /*!< system time sign */ - + /* ENET_PTP_TSUH */ #define ENET_PTP_TSUH_TMSUS BITS(0,31) /*!< timestamp update seconds */ - + /* ENET_PTP_TSUL */ #define ENET_PTP_TSUL_TMSUSS BITS(0,30) /*!< timestamp update subseconds */ #define ENET_PTP_TSUL_TMSUPNS BIT(31) /*!< timestamp update positive or negative sign */ /* ENET_PTP_TSADDAND */ #define ENET_PTP_TSADDAND_TMSA BITS(0,31) /*!< timestamp addend */ - + /* ENET_PTP_ETH */ #define ENET_PTP_ETH_ETSH BITS(0,31) /*!< expected time high */ - + /* ENET_PTP_ETL */ #define ENET_PTP_ETL_ETSL BITS(0,31) /*!< expected time low */ - + /* ENET_PTP_TSF */ #define ENET_PTP_TSF_TSSCO BIT(0) /*!< timestamp second counter overflow */ #define ENET_PTP_TSF_TTM BIT(1) /*!< target time match */ - + /* ENET_PTP_PPSCTL */ #define ENET_PTP_PPSCTL_PPSOFC BITS(0,3) /*!< PPS output frequency configure */ @@ -403,19 +428,19 @@ #define ENET_DMA_BCTL_FPBL BIT(24) /*!< four times PGBL mode */ #define ENET_DMA_BCTL_AA BIT(25) /*!< address-aligned */ #define ENET_DMA_BCTL_MB BIT(26) /*!< mixed burst */ - + /* ENET_DMA_TPEN */ #define ENET_DMA_TPEN_TPE BITS(0,31) /*!< transmit poll enable */ - + /* ENET_DMA_RPEN */ #define ENET_DMA_RPEN_RPE BITS(0,31) /*!< receive poll enable */ /* ENET_DMA_RDTADDR */ #define ENET_DMA_RDTADDR_SRT BITS(0,31) /*!< start address of receive table */ - + /* ENET_DMA_TDTADDR */ #define ENET_DMA_TDTADDR_STT BITS(0,31) /*!< start address of transmit table */ - + /* ENET_DMA_STAT */ #define ENET_DMA_STAT_TS BIT(0) /*!< transmit status */ #define ENET_DMA_STAT_TPS BIT(1) /*!< transmit process stopped status */ @@ -438,7 +463,7 @@ #define ENET_DMA_STAT_MSC BIT(27) /*!< MSC status */ #define ENET_DMA_STAT_WUM BIT(28) /*!< WUM status */ #define ENET_DMA_STAT_TST BIT(29) /*!< timestamp trigger status */ - + /* ENET_DMA_CTL */ #define ENET_DMA_CTL_SRE BIT(1) /*!< start/stop receive enable */ #define ENET_DMA_CTL_OSF BIT(2) /*!< operate on second frame */ @@ -452,7 +477,7 @@ #define ENET_DMA_CTL_DAFRF BIT(24) /*!< disable flushing of received frames */ #define ENET_DMA_CTL_RSFD BIT(25) /*!< receive store-and-forward */ #define ENET_DMA_CTL_DTCERFD BIT(26) /*!< dropping of TCP/IP checksum error frames disable */ - + /* ENET_DMA_INTEN */ #define ENET_DMA_INTEN_TIE BIT(0) /*!< transmit interrupt enable */ #define ENET_DMA_INTEN_TPSIE BIT(1) /*!< transmit process stopped interrupt enable */ @@ -469,7 +494,7 @@ #define ENET_DMA_INTEN_ERIE BIT(14) /*!< early receive interrupt enable */ #define ENET_DMA_INTEN_AIE BIT(15) /*!< abnormal interrupt summary enable */ #define ENET_DMA_INTEN_NIE BIT(16) /*!< normal interrupt summary enable */ - + /* ENET_DMA_MFBOCNT */ #define ENET_DMA_MFBOCNT_MSFC BITS(0,15) /*!< missed frames by the controller */ #define ENET_DMA_MFBOCNT_MSFA BITS(17,27) /*!< missed frames by the application */ @@ -482,10 +507,10 @@ /* ENET_DMA_CRDADDR */ #define ENET_DMA_CRDADDR_RDAP BITS(0,31) /*!< receive descriptor address pointer */ - + /* ENET_DMA_CTBADDR */ #define ENET_DMA_CTBADDR_TBAP BITS(0,31) /*!< transmit buffer address pointer */ - + /* ENET_DMA_CRBADDR */ #define ENET_DMA_CRBADDR_RBAP BITS(0,31) /*!< receive buffer address pointer */ @@ -545,7 +570,7 @@ #define ENET_RDES0_LCO BIT(6) /*!< late collision */ #define ENET_RDES0_IPHERR BIT(7) /*!< IP frame header error */ #define ENET_RDES0_TSV BIT(7) /*!< timestamp valid */ -#define ENET_RDES0_LDES BIT(8) /*!< last descriptor */ +#define ENET_RDES0_LDES BIT(8) /*!< last descriptor */ #define ENET_RDES0_FDES BIT(9) /*!< first descriptor */ #define ENET_RDES0_VTAG BIT(10) /*!< VLAN tag */ #define ENET_RDES0_OERR BIT(11) /*!< overflow Error */ @@ -557,7 +582,7 @@ #define ENET_RDES0_DAFF BIT(30) /*!< destination address filter fail */ #define ENET_RDES0_DAV BIT(31) /*!< descriptor available */ -/* ENET DMA Rx descriptor RDES1 */ +/* ENET DMA Rx descriptor RDES1 */ #define ENET_RDES1_RB1S BITS(0,12) /*!< receive buffer 1 size */ #define ENET_RDES1_RCHM BIT(14) /*!< receive chained mode for second address */ #define ENET_RDES1_RERM BIT(15) /*!< receive end of ring mode*/ @@ -592,53 +617,53 @@ /* constants definitions */ /* define bit position and its register index offset */ #define ENET_REGIDX_BIT(regidx, bitpos) (((uint32_t)(regidx) << 6) | (uint32_t)(bitpos)) -#define ENET_REG_VAL(periph) (REG32(ENET + ((uint32_t)(periph)>>6))) +#define ENET_REG_VAL(periph) (REG32(ENET + ((uint32_t)(periph) >> 6))) #define ENET_BIT_POS(val) ((uint32_t)(val) & 0x1FU) /* ENET clock range judgement */ #define ENET_RANGE(hclk, n, m) (((hclk) >= (n))&&((hclk) < (m))) /* define MAC address configuration and reference address */ -#define ENET_SET_MACADDRH(p) (((uint32_t)(p)[5] << 8) | (uint32_t)(p)[4]) +#define ENET_SET_MACADDRH(p) (((uint32_t)(p)[5] << 8) | (uint32_t)(p)[4]) #define ENET_SET_MACADDRL(p) (((uint32_t)(p)[3] << 24) | ((uint32_t)(p)[2] << 16) | ((uint32_t)(p)[1] << 8) | (uint32_t)(p)[0]) #define ENET_ADDRH_BASE ((ENET) + 0x40U) #define ENET_ADDRL_BASE ((ENET) + 0x44U) #define ENET_GET_MACADDR(offset, n) ((uint8_t)((REG32((ENET_ADDRL_BASE + (offset)) - (((n) / 4U) * 4U)) >> (8U * ((n) % 4U))) & 0xFFU)) /* register offset */ -#define MAC_FCTL_REG_OFFSET 0x0018U /*!< MAC flow control register offset */ -#define MAC_WUM_REG_OFFSET 0x002CU /*!< MAC wakeup management register offset */ -#define MAC_INTF_REG_OFFSET 0x0038U /*!< MAC interrupt flag register offset */ -#define MAC_INTMSK_REG_OFFSET 0x003CU /*!< MAC interrupt mask register offset */ +#define MAC_FCTL_REG_OFFSET ((uint16_t)0x0018U) /*!< MAC flow control register offset */ +#define MAC_WUM_REG_OFFSET ((uint16_t)0x002CU) /*!< MAC wakeup management register offset */ +#define MAC_INTF_REG_OFFSET ((uint16_t)0x0038U) /*!< MAC interrupt flag register offset */ +#define MAC_INTMSK_REG_OFFSET ((uint16_t)0x003CU) /*!< MAC interrupt mask register offset */ + +#define MSC_RINTF_REG_OFFSET ((uint16_t)0x0104U) /*!< MSC receive interrupt flag register offset */ +#define MSC_TINTF_REG_OFFSET ((uint16_t)0x0108U) /*!< MSC transmit interrupt flag register offset */ +#define MSC_RINTMSK_REG_OFFSET ((uint16_t)0x010CU) /*!< MSC receive interrupt mask register offset */ +#define MSC_TINTMSK_REG_OFFSET ((uint16_t)0x0110U) /*!< MSC transmit interrupt mask register offset */ +#define MSC_SCCNT_REG_OFFSET ((uint16_t)0x014CU) /*!< MSC transmitted good frames after a single collision counter register offset */ +#define MSC_MSCCNT_REG_OFFSET ((uint16_t)0x0150U) /*!< MSC transmitted good frames after more than a single collision counter register offset */ +#define MSC_TGFCNT_REG_OFFSET ((uint16_t)0x0168U) /*!< MSC transmitted good frames counter register offset */ +#define MSC_RFCECNT_REG_OFFSET ((uint16_t)0x0194U) /*!< MSC received frames with CRC error counter register offset */ +#define MSC_RFAECNT_REG_OFFSET ((uint16_t)0x0198U) /*!< MSC received frames with alignment error counter register offset */ +#define MSC_RGUFCNT_REG_OFFSET ((uint16_t)0x01C4U) /*!< MSC received good unicast frames counter register offset */ -#define MSC_RINTF_REG_OFFSET 0x0104U /*!< MSC receive interrupt flag register offset */ -#define MSC_TINTF_REG_OFFSET 0x0108U /*!< MSC transmit interrupt flag register offset */ -#define MSC_RINTMSK_REG_OFFSET 0x010CU /*!< MSC receive interrupt mask register offset */ -#define MSC_TINTMSK_REG_OFFSET 0x0110U /*!< MSC transmit interrupt mask register offset */ -#define MSC_SCCNT_REG_OFFSET 0x014CU /*!< MSC transmitted good frames after a single collision counter register offset */ -#define MSC_MSCCNT_REG_OFFSET 0x0150U /*!< MSC transmitted good frames after more than a single collision counter register offset */ -#define MSC_TGFCNT_REG_OFFSET 0x0168U /*!< MSC transmitted good frames counter register offset */ -#define MSC_RFCECNT_REG_OFFSET 0x0194U /*!< MSC received frames with CRC error counter register offset */ -#define MSC_RFAECNT_REG_OFFSET 0x0198U /*!< MSC received frames with alignment error counter register offset */ -#define MSC_RGUFCNT_REG_OFFSET 0x01C4U /*!< MSC received good unicast frames counter register offset */ - -#define PTP_TSF_REG_OFFSET 0x0728U /*!< PTP time stamp flag register offset */ +#define PTP_TSF_REG_OFFSET ((uint16_t)0x0728U) /*!< PTP time stamp flag register offset */ -#define DMA_STAT_REG_OFFSET 0x1014U /*!< DMA status register offset */ -#define DMA_INTEN_REG_OFFSET 0x101CU /*!< DMA interrupt enable register offset */ -#define DMA_TDTADDR_REG_OFFSET 0x1010U /*!< DMA transmit descriptor table address register offset */ -#define DMA_CTDADDR_REG_OFFSET 0x1048U /*!< DMA current transmit descriptor address register */ -#define DMA_CTBADDR_REG_OFFSET 0x1050U /*!< DMA current transmit buffer address register */ -#define DMA_RDTADDR_REG_OFFSET 0x100CU /*!< DMA receive descriptor table address register */ -#define DMA_CRDADDR_REG_OFFSET 0x104CU /*!< DMA current receive descriptor address register */ -#define DMA_CRBADDR_REG_OFFSET 0x1054U /*!< DMA current receive buffer address register */ +#define DMA_STAT_REG_OFFSET ((uint16_t)0x1014U) /*!< DMA status register offset */ +#define DMA_INTEN_REG_OFFSET ((uint16_t)0x101CU) /*!< DMA interrupt enable register offset */ +#define DMA_TDTADDR_REG_OFFSET ((uint16_t)0x1010U) /*!< DMA transmit descriptor table address register offset */ +#define DMA_CTDADDR_REG_OFFSET ((uint16_t)0x1048U) /*!< DMA current transmit descriptor address register */ +#define DMA_CTBADDR_REG_OFFSET ((uint16_t)0x1050U) /*!< DMA current transmit buffer address register */ +#define DMA_RDTADDR_REG_OFFSET ((uint16_t)0x100CU) /*!< DMA receive descriptor table address register */ +#define DMA_CRDADDR_REG_OFFSET ((uint16_t)0x104CU) /*!< DMA current receive descriptor address register */ +#define DMA_CRBADDR_REG_OFFSET ((uint16_t)0x1054U) /*!< DMA current receive buffer address register */ /* ENET status flag get */ typedef enum { /* ENET_MAC_WUM register */ ENET_MAC_FLAG_MPKR = ENET_REGIDX_BIT(MAC_WUM_REG_OFFSET, 5U), /*!< magic packet received flag */ - ENET_MAC_FLAG_WUFR = ENET_REGIDX_BIT(MAC_WUM_REG_OFFSET, 6U), /*!< wakeup frame received flag */ + ENET_MAC_FLAG_WUFR = ENET_REGIDX_BIT(MAC_WUM_REG_OFFSET, 6U), /*!< wakeup frame received flag */ /* ENET_MAC_FCTL register */ ENET_MAC_FLAG_FLOWCONTROL = ENET_REGIDX_BIT(MAC_FCTL_REG_OFFSET, 0U), /*!< flow control status flag */ /* ENET_MAC_INTF register */ @@ -648,13 +673,13 @@ typedef enum ENET_MAC_FLAG_MSCT = ENET_REGIDX_BIT(MAC_INTF_REG_OFFSET, 6U), /*!< MSC transmit status flag */ ENET_MAC_FLAG_TMST = ENET_REGIDX_BIT(MAC_INTF_REG_OFFSET, 9U), /*!< timestamp trigger status flag */ /* ENET_PTP_TSF register */ - ENET_PTP_FLAG_TSSCO = ENET_REGIDX_BIT(PTP_TSF_REG_OFFSET, 0U), /*!< timestamp second counter overflow flag */ + ENET_PTP_FLAG_TSSCO = ENET_REGIDX_BIT(PTP_TSF_REG_OFFSET, 0U), /*!< timestamp second counter overflow flag */ ENET_PTP_FLAG_TTM = ENET_REGIDX_BIT(PTP_TSF_REG_OFFSET, 1U), /*!< target time match flag */ /* ENET_MSC_RINTF register */ ENET_MSC_FLAG_RFCE = ENET_REGIDX_BIT(MSC_RINTF_REG_OFFSET, 5U), /*!< received frames CRC error flag */ ENET_MSC_FLAG_RFAE = ENET_REGIDX_BIT(MSC_RINTF_REG_OFFSET, 6U), /*!< received frames alignment error flag */ ENET_MSC_FLAG_RGUF = ENET_REGIDX_BIT(MSC_RINTF_REG_OFFSET, 17U), /*!< received good unicast frames flag */ - /* ENET_MSC_TINTF register */ + /* ENET_MSC_TINTF register */ ENET_MSC_FLAG_TGFSC = ENET_REGIDX_BIT(MSC_TINTF_REG_OFFSET, 14U), /*!< transmitted good frames single collision flag */ ENET_MSC_FLAG_TGFMSC = ENET_REGIDX_BIT(MSC_TINTF_REG_OFFSET, 15U), /*!< transmitted good frames more single collision flag */ ENET_MSC_FLAG_TGF = ENET_REGIDX_BIT(MSC_TINTF_REG_OFFSET, 21U), /*!< transmitted good frames flag */ @@ -679,7 +704,7 @@ typedef enum ENET_DMA_FLAG_EB_ACCESS_ERROR = ENET_REGIDX_BIT(DMA_STAT_REG_OFFSET, 25U), /*!< error during data buffer/descriptor access flag */ ENET_DMA_FLAG_MSC = ENET_REGIDX_BIT(DMA_STAT_REG_OFFSET, 27U), /*!< MSC status flag */ ENET_DMA_FLAG_WUM = ENET_REGIDX_BIT(DMA_STAT_REG_OFFSET, 28U), /*!< WUM status flag */ - ENET_DMA_FLAG_TST = ENET_REGIDX_BIT(DMA_STAT_REG_OFFSET, 29U), /*!< timestamp trigger status flag */ + ENET_DMA_FLAG_TST = ENET_REGIDX_BIT(DMA_STAT_REG_OFFSET, 29U), /*!< timestamp trigger status flag */ }enet_flag_enum; /* ENET stutus flag clear */ @@ -700,7 +725,7 @@ typedef enum ENET_DMA_FLAG_FBE_CLR = ENET_REGIDX_BIT(DMA_STAT_REG_OFFSET, 13U), /*!< fatal bus error status flag */ ENET_DMA_FLAG_ER_CLR = ENET_REGIDX_BIT(DMA_STAT_REG_OFFSET, 14U), /*!< early receive status flag */ ENET_DMA_FLAG_AI_CLR = ENET_REGIDX_BIT(DMA_STAT_REG_OFFSET, 15U), /*!< abnormal interrupt summary flag */ - ENET_DMA_FLAG_NI_CLR = ENET_REGIDX_BIT(DMA_STAT_REG_OFFSET, 16U), /*!< normal interrupt summary flag */ + ENET_DMA_FLAG_NI_CLR = ENET_REGIDX_BIT(DMA_STAT_REG_OFFSET, 16U), /*!< normal interrupt summary flag */ }enet_flag_clear_enum; /* ENET interrupt enable/disable */ @@ -709,15 +734,15 @@ typedef enum /* ENET_MAC_INTMSK register */ ENET_MAC_INT_WUMIM = ENET_REGIDX_BIT(MAC_INTMSK_REG_OFFSET, 3U), /*!< WUM interrupt mask */ ENET_MAC_INT_TMSTIM = ENET_REGIDX_BIT(MAC_INTMSK_REG_OFFSET, 9U), /*!< timestamp trigger interrupt mask */ - /* ENET_MSC_RINTMSK register */ + /* ENET_MSC_RINTMSK register */ ENET_MSC_INT_RFCEIM = ENET_REGIDX_BIT(MSC_RINTMSK_REG_OFFSET, 5U), /*!< received frame CRC error interrupt mask */ ENET_MSC_INT_RFAEIM = ENET_REGIDX_BIT(MSC_RINTMSK_REG_OFFSET, 6U), /*!< received frames alignment error interrupt mask */ ENET_MSC_INT_RGUFIM = ENET_REGIDX_BIT(MSC_RINTMSK_REG_OFFSET, 17U), /*!< received good unicast frames interrupt mask */ - /* ENET_MSC_TINTMSK register */ + /* ENET_MSC_TINTMSK register */ ENET_MSC_INT_TGFSCIM = ENET_REGIDX_BIT(MSC_TINTMSK_REG_OFFSET, 14U), /*!< transmitted good frames single collision interrupt mask */ ENET_MSC_INT_TGFMSCIM = ENET_REGIDX_BIT(MSC_TINTMSK_REG_OFFSET, 15U), /*!< transmitted good frames more single collision interrupt mask */ ENET_MSC_INT_TGFIM = ENET_REGIDX_BIT(MSC_TINTMSK_REG_OFFSET, 21U), /*!< transmitted good frames interrupt mask */ - /* ENET_DMA_INTEN register */ + /* ENET_DMA_INTEN register */ ENET_DMA_INT_TIE = ENET_REGIDX_BIT(DMA_INTEN_REG_OFFSET, 0U), /*!< transmit interrupt enable */ ENET_DMA_INT_TPSIE = ENET_REGIDX_BIT(DMA_INTEN_REG_OFFSET, 1U), /*!< transmit process stopped interrupt enable */ ENET_DMA_INT_TBUIE = ENET_REGIDX_BIT(DMA_INTEN_REG_OFFSET, 2U), /*!< transmit buffer unavailable interrupt enable */ @@ -734,7 +759,7 @@ typedef enum ENET_DMA_INT_AIE = ENET_REGIDX_BIT(DMA_INTEN_REG_OFFSET, 15U), /*!< abnormal interrupt summary enable */ ENET_DMA_INT_NIE = ENET_REGIDX_BIT(DMA_INTEN_REG_OFFSET, 16U), /*!< normal interrupt summary enable */ }enet_int_enum; - + /* ENET interrupt flag get */ typedef enum { @@ -770,7 +795,7 @@ typedef enum ENET_DMA_INT_FLAG_NI = ENET_REGIDX_BIT(DMA_STAT_REG_OFFSET, 16U), /*!< normal interrupt summary flag */ ENET_DMA_INT_FLAG_MSC = ENET_REGIDX_BIT(DMA_STAT_REG_OFFSET, 27U), /*!< MSC status flag */ ENET_DMA_INT_FLAG_WUM = ENET_REGIDX_BIT(DMA_STAT_REG_OFFSET, 28U), /*!< WUM status flag */ - ENET_DMA_INT_FLAG_TST = ENET_REGIDX_BIT(DMA_STAT_REG_OFFSET, 29U), /*!< timestamp trigger status flag */ + ENET_DMA_INT_FLAG_TST = ENET_REGIDX_BIT(DMA_STAT_REG_OFFSET, 29U), /*!< timestamp trigger status flag */ }enet_int_flag_enum; /* ENET interrupt flag clear */ @@ -814,7 +839,7 @@ typedef enum ENET_MSC_RX_RFCECNT = MSC_RFCECNT_REG_OFFSET, /*!< MSC received frames with CRC error counter */ ENET_MSC_RX_RFAECNT = MSC_RFAECNT_REG_OFFSET, /*!< MSC received frames with alignment error counter */ ENET_MSC_RX_RGUFCNT = MSC_RGUFCNT_REG_OFFSET /*!< MSC received good unicast frames counter */ -}enet_msc_counter_enum; +}enet_msc_counter_enum; /* function option, used for ENET initialization */ typedef enum @@ -838,7 +863,7 @@ typedef enum /* phy mode and mac loopback configurations */ typedef enum { - ENET_AUTO_NEGOTIATION = 0x01u, /*!< PHY auto negotiation */ + ENET_AUTO_NEGOTIATION = 0x01U, /*!< PHY auto negotiation */ ENET_100M_FULLDUPLEX = (ENET_MAC_CFG_SPD | ENET_MAC_CFG_DPM), /*!< 100Mbit/s, full-duplex */ ENET_100M_HALFDUPLEX = ENET_MAC_CFG_SPD , /*!< 100Mbit/s, half-duplex */ ENET_10M_FULLDUPLEX = ENET_MAC_CFG_DPM, /*!< 10Mbit/s, full-duplex */ @@ -867,10 +892,10 @@ typedef enum /* register group value get */ typedef enum { - ALL_MAC_REG = 0, /*!< MAC register group */ - ALL_MSC_REG = 22, /*!< MSC register group */ - ALL_PTP_REG = 33, /*!< PTP register group */ - ALL_DMA_REG = 44, /*!< DMA register group */ + ALL_MAC_REG = 0U, /*!< MAC register group */ + ALL_MSC_REG = 22U, /*!< MSC register group */ + ALL_PTP_REG = 33U, /*!< PTP register group */ + ALL_DMA_REG = 44U, /*!< DMA register group */ }enet_registers_type_enum; /* dma direction select */ @@ -894,7 +919,7 @@ typedef enum ENET_REG_WRITE /*!< write register */ }enet_regdirection_enum; -/* ENET MAC addresses */ +/* ENET MAC addresses */ typedef enum { ENET_MAC_ADDRESS0 = ((uint32_t)0x00000000), /*!< MAC address0 */ @@ -928,7 +953,7 @@ typedef enum{ ENET_CKNT_END_TO_END = PTP_TSCTL_CKNT(2), /*!< type of end-to-end transparent clock node type for timestamp */ ENET_CKNT_PEER_TO_PEER = PTP_TSCTL_CKNT(3), /*!< type of peer-to-peer transparent clock node type for timestamp */ ENET_PTP_SYSTIME_INIT = ENET_PTP_TSCTL_TMSSTI, /*!< timestamp initialize */ - ENET_PTP_SYSTIME_UPDATE = ENET_PTP_TSCTL_TMSSTU, /*!< timestamp update */ + ENET_PTP_SYSTIME_UPDATE = ENET_PTP_TSCTL_TMSSTU, /*!< timestamp update */ ENET_PTP_ADDEND_UPDATE = ENET_PTP_TSCTL_TMSARU, /*!< addend register update */ ENET_PTP_FINEMODE = (int32_t)(ENET_PTP_TSCTL_TMSFCU| BIT(31)), /*!< the system timestamp uses the fine method for updating */ ENET_PTP_COARSEMODE = ENET_PTP_TSCTL_TMSFCU, /*!< the system timestamp uses the coarse method for updating */ @@ -946,24 +971,24 @@ typedef enum{ typedef struct { uint32_t option_enable; /*!< select which function to configure */ - uint32_t forward_frame; /*!< frame forward related parameters */ + uint32_t forward_frame; /*!< frame forward related parameters */ uint32_t dmabus_mode; /*!< DMA bus mode related parameters */ uint32_t dma_maxburst; /*!< DMA max burst related parameters */ uint32_t dma_arbitration; /*!< DMA Tx and Rx arbitration related parameters */ uint32_t store_forward_mode; /*!< store forward mode related parameters */ uint32_t dma_function; /*!< DMA control related parameters */ - uint32_t vlan_config; /*!< VLAN tag related parameters */ + uint32_t vlan_config; /*!< VLAN tag related parameters */ uint32_t flow_control; /*!< flow control related parameters */ uint32_t hashtable_high; /*!< hash list high 32-bit related parameters */ uint32_t hashtable_low; /*!< hash list low 32-bit related parameters */ uint32_t framesfilter_mode; /*!< frame filter control related parameters */ - uint32_t halfduplex_param; /*!< halfduplex related parameters */ + uint32_t halfduplex_param; /*!< halfduplex related parameters */ uint32_t timer_config; /*!< frame timer related parameters */ uint32_t interframegap; /*!< inter frame gap related parameters */ }enet_initpara_struct; -/* structure for ENET DMA desciptors */ -typedef struct +/* structure for ENET DMA desciptors */ +typedef struct { uint32_t status; /*!< status */ uint32_t control_buffer_size; /*!< control and buffer1, buffer2 lengths */ @@ -974,12 +999,12 @@ typedef struct uint32_t extended_status; /*!< extended status */ uint32_t reserved; /*!< reserved */ uint32_t timestamp_low; /*!< timestamp low */ - uint32_t timestamp_high; /*!< timestamp high */ -#endif /* SELECT_DESCRIPTORS_ENHANCED_MODE */ - + uint32_t timestamp_high; /*!< timestamp high */ +#endif /* SELECT_DESCRIPTORS_ENHANCED_MODE */ + } enet_descriptors_struct; -/* structure of PTP system time */ +/* structure of PTP system time */ typedef struct { uint32_t second; /*!< second of system time */ @@ -992,17 +1017,17 @@ typedef struct #define ENET_BACKOFFLIMIT_10 MAC_CFG_BOL(0) /*!< min (n, 10) */ #define ENET_BACKOFFLIMIT_8 MAC_CFG_BOL(1) /*!< min (n, 8) */ #define ENET_BACKOFFLIMIT_4 MAC_CFG_BOL(2) /*!< min (n, 4) */ -#define ENET_BACKOFFLIMIT_1 MAC_CFG_BOL(3) /*!< min (n, 1) */ +#define ENET_BACKOFFLIMIT_1 MAC_CFG_BOL(3) /*!< min (n, 1) */ #define MAC_CFG_IGBS(regval) (BITS(17,19) & ((uint32_t)(regval) << 17)) /*!< write value to ENET_MAC_CFG_IGBS bit field */ -#define ENET_INTERFRAMEGAP_96BIT MAC_CFG_IGBS(0) /*!< minimum 96 bit times */ +#define ENET_INTERFRAMEGAP_96BIT MAC_CFG_IGBS(0) /*!< minimum 96 bit times */ #define ENET_INTERFRAMEGAP_88BIT MAC_CFG_IGBS(1) /*!< minimum 88 bit times */ #define ENET_INTERFRAMEGAP_80BIT MAC_CFG_IGBS(2) /*!< minimum 80 bit times */ #define ENET_INTERFRAMEGAP_72BIT MAC_CFG_IGBS(3) /*!< minimum 72 bit times */ -#define ENET_INTERFRAMEGAP_64BIT MAC_CFG_IGBS(4) /*!< minimum 64 bit times */ +#define ENET_INTERFRAMEGAP_64BIT MAC_CFG_IGBS(4) /*!< minimum 64 bit times */ #define ENET_INTERFRAMEGAP_56BIT MAC_CFG_IGBS(5) /*!< minimum 56 bit times */ #define ENET_INTERFRAMEGAP_48BIT MAC_CFG_IGBS(6) /*!< minimum 48 bit times */ -#define ENET_INTERFRAMEGAP_40BIT MAC_CFG_IGBS(7) /*!< minimum 40 bit times */ +#define ENET_INTERFRAMEGAP_40BIT MAC_CFG_IGBS(7) /*!< minimum 40 bit times */ #define ENET_TYPEFRAME_CRC_DROP_ENABLE ENET_MAC_CFG_TFCD /*!< FCS field(last 4 bytes) of frame will be dropped before forwarding */ #define ENET_TYPEFRAME_CRC_DROP_DISABLE ((uint32_t)0x00000000U) /*!< FCS field(last 4 bytes) of frame will not be dropped before forwarding */ @@ -1010,13 +1035,13 @@ typedef struct #define ENET_WATCHDOG_ENABLE ((uint32_t)0x00000000U) /*!< the MAC allows no more than 2048 bytes of the frame being received */ #define ENET_WATCHDOG_DISABLE ENET_MAC_CFG_WDD /*!< the MAC disables the watchdog timer on the receiver, and can receive frames of up to 16384 bytes */ - + #define ENET_JABBER_ENABLE ((uint32_t)0x00000000U) /*!< the maximum transmission byte is 2048 */ #define ENET_JABBER_DISABLE ENET_MAC_CFG_JBD /*!< the maximum transmission byte can be 16384 */ #define ENET_CARRIERSENSE_ENABLE ((uint32_t)0x00000000U) /*!< the MAC transmitter generates carrier sense error and aborts the transmission */ #define ENET_CARRIERSENSE_DISABLE ENET_MAC_CFG_CSD /*!< the MAC transmitter ignores the MII CRS signal during frame transmission in half-duplex mode */ - + #define ENET_SPEEDMODE_10M ((uint32_t)0x00000000U) /*!< 10 Mbit/s */ #define ENET_SPEEDMODE_100M ENET_MAC_CFG_SPD /*!< 100 Mbit/s */ @@ -1048,10 +1073,10 @@ typedef struct #define ENET_PCFRM_PREVENT_PAUSEFRAME MAC_FRMF_PCFRM(1) /*!< MAC only forwards all other control frames except pause control frame */ #define ENET_PCFRM_FORWARD_ALL MAC_FRMF_PCFRM(2) /*!< MAC forwards all control frames to application even if they fail the address filter */ #define ENET_PCFRM_FORWARD_FILTERED MAC_FRMF_PCFRM(3) /*!< MAC forwards control frames that only pass the address filter */ - + #define ENET_RX_FILTER_DISABLE ENET_MAC_FRMF_FAR /*!< all received frame are forwarded to application */ #define ENET_RX_FILTER_ENABLE ((uint32_t)0x00000000U) /*!< only the frame passed the filter can be forwarded to application */ - + #define ENET_SRC_FILTER_NORMAL_ENABLE ENET_MAC_FRMF_SAFLT /*!< filter source address */ #define ENET_SRC_FILTER_INVERSE_ENABLE (ENET_MAC_FRMF_SAFLT | ENET_MAC_FRMF_SAIFLT) /*!< inverse source address filtering result */ #define ENET_SRC_FILTER_DISABLE ((uint32_t)0x00000000U) /*!< source address function in filter disable */ @@ -1060,14 +1085,14 @@ typedef struct #define ENET_BROADCASTFRAMES_ENABLE ((uint32_t)0x00000000U) /*!< the address filters pass all received broadcast frames */ #define ENET_BROADCASTFRAMES_DISABLE ENET_MAC_FRMF_BFRMD /*!< the address filters filter all incoming broadcast frames */ - + #define ENET_DEST_FILTER_INVERSE_ENABLE ENET_MAC_FRMF_DAIFLT /*!< inverse DA filtering result */ #define ENET_DEST_FILTER_INVERSE_DISABLE ((uint32_t)0x00000000U) /*!< not inverse DA filtering result */ #define ENET_DEST_FILTER_INVERSE ENET_MAC_FRMF_DAIFLT /*!< inverse DA filtering result function */ #define ENET_PROMISCUOUS_ENABLE ENET_MAC_FRMF_PM /*!< promiscuous mode enabled */ #define ENET_PROMISCUOUS_DISABLE ((uint32_t)0x00000000U) /*!< promiscuous mode disabled */ - + #define ENET_MULTICAST_FILTER_HASH_OR_PERFECT (ENET_MAC_FRMF_HMF | ENET_MAC_FRMF_HPFLT) /*!< pass multicast frames that match either the perfect or the hash filtering */ #define ENET_MULTICAST_FILTER_HASH ENET_MAC_FRMF_HMF /*!< pass multicast frames that match the hash filtering */ #define ENET_MULTICAST_FILTER_PERFECT ((uint32_t)0x00000000U) /*!< pass multicast frames that match the perfect filtering */ @@ -1101,7 +1126,7 @@ typedef struct #define ENET_PAUSETIME_MINUS4 MAC_FCTL_PLTS(0) /*!< pause time minus 4 slot times */ #define ENET_PAUSETIME_MINUS28 MAC_FCTL_PLTS(1) /*!< pause time minus 28 slot times */ #define ENET_PAUSETIME_MINUS144 MAC_FCTL_PLTS(2) /*!< pause time minus 144 slot times */ -#define ENET_PAUSETIME_MINUS256 MAC_FCTL_PLTS(3) /*!< pause time minus 256 slot times */ +#define ENET_PAUSETIME_MINUS256 MAC_FCTL_PLTS(3) /*!< pause time minus 256 slot times */ #define ENET_ZERO_QUANTA_PAUSE_ENABLE ((uint32_t)0x00000000U) /*!< enable the automatic zero-quanta generation function */ #define ENET_ZERO_QUANTA_PAUSE_DISABLE ENET_MAC_FCTL_DZQP /*!< disable the automatic zero-quanta generation function */ @@ -1109,7 +1134,7 @@ typedef struct #define ENET_MAC0_AND_UNIQUE_ADDRESS_PAUSEDETECT ENET_MAC_FCTL_UPFDT /*!< besides the unique multicast address, MAC also use the MAC0 address to detect pause frame */ #define ENET_UNIQUE_PAUSEDETECT ((uint32_t)0x00000000U) /*!< only the unique multicast address for pause frame which is specified in IEEE802.3 can be detected */ - + #define ENET_RX_FLOWCONTROL_ENABLE ENET_MAC_FCTL_RFCEN /*!< enable decoding function for the received pause frame and process it */ #define ENET_RX_FLOWCONTROL_DISABLE ((uint32_t)0x00000000U) /*!< decode function for pause frame is disabled */ #define ENET_RX_FLOWCONTROL ENET_MAC_FCTL_RFCEN /*!< decoding function for the received pause frame and process it */ @@ -1121,33 +1146,34 @@ typedef struct #define ENET_BACK_PRESSURE_ENABLE ENET_MAC_FCTL_FLCBBKPA /*!< enable the back pressure operation in the MAC */ #define ENET_BACK_PRESSURE_DISABLE ((uint32_t)0x00000000U) /*!< disable the back pressure operation in the MAC */ #define ENET_BACK_PRESSURE ENET_MAC_FCTL_FLCBBKPA /*!< the back pressure operation in the MAC */ - + #define MAC_FCTL_PTM(regval) (BITS(16,31) & ((uint32_t)(regval) << 16)) /*!< write value to ENET_MAC_FCTL_PTM bit field */ /* mac_vlt register value */ #define MAC_VLT_VLTI(regval) (BITS(0,15) & ((uint32_t)(regval) << 0)) /*!< write value to ENET_MAC_VLT_VLTI bit field */ - + #define ENET_VLANTAGCOMPARISON_12BIT ENET_MAC_VLT_VLTC /*!< only low 12 bits of the VLAN tag are used for comparison */ #define ENET_VLANTAGCOMPARISON_16BIT ((uint32_t)0x00000000U) /*!< all 16 bits of the VLAN tag are used for comparison */ -/* mac_wum register value */ +/* mac_wum register value */ #define ENET_WUM_FLAG_WUFFRPR ENET_MAC_WUM_WUFFRPR /*!< wakeup frame filter register poniter reset */ #define ENET_WUM_FLAG_WUFR ENET_MAC_WUM_WUFR /*!< wakeup frame received */ #define ENET_WUM_FLAG_MPKR ENET_MAC_WUM_MPKR /*!< magic packet received */ -#define ENET_WUM_POWER_DOWN ENET_MAC_WUM_PWD /*!< power down mode */ -#define ENET_WUM_MAGIC_PACKET_FRAME ENET_MAC_WUM_MPEN /*!< enable a wakeup event due to magic packet reception */ -#define ENET_WUM_WAKE_UP_FRAME ENET_MAC_WUM_WFEN /*!< enable a wakeup event due to wakeup frame reception */ +#define ENET_WUM_POWER_DOWN ENET_MAC_WUM_PWD /*!< power down mode */ +#define ENET_WUM_MAGIC_PACKET_FRAME ENET_MAC_WUM_MPEN /*!< enable a wakeup event due to magic packet reception */ +#define ENET_WUM_WAKE_UP_FRAME ENET_MAC_WUM_WFEN /*!< enable a wakeup event due to wakeup frame reception */ #define ENET_WUM_GLOBAL_UNICAST ENET_MAC_WUM_GU /*!< any received unicast frame passed filter is considered to be a wakeup frame */ + /* mac_dbg register value */ #define ENET_MAC_RECEIVER_NOT_IDLE ENET_MAC_DBG_MRNI /*!< MAC receiver is not in idle state */ #define ENET_RX_ASYNCHRONOUS_FIFO_STATE ENET_MAC_DBG_RXAFS /*!< Rx asynchronous FIFO status */ -#define ENET_RXFIFO_NOT_WRITING ENET_MAC_DBG_RXFW /*!< RxFIFO is not doing write operation */ +#define ENET_RXFIFO_WRITING ENET_MAC_DBG_RXFW /*!< RxFIFO is doing write operation */ #define ENET_RXFIFO_READ_STATUS ENET_MAC_DBG_RXFRS /*!< RxFIFO read operation status */ #define ENET_RXFIFO_STATE ENET_MAC_DBG_RXFS /*!< RxFIFO state */ #define ENET_MAC_TRANSMITTER_NOT_IDLE ENET_MAC_DBG_MTNI /*!< MAC transmitter is not in idle state */ #define ENET_MAC_TRANSMITTER_STATUS ENET_MAC_DBG_SOMT /*!< status of MAC transmitter */ #define ENET_PAUSE_CONDITION_STATUS ENET_MAC_DBG_PCS /*!< pause condition status */ #define ENET_TXFIFO_READ_STATUS ENET_MAC_DBG_TXFRS /*!< TxFIFO read operation status */ -#define ENET_TXFIFO_NOT_WRITING ENET_MAC_DBG_TXFW /*!< TxFIFO is not doing write operation */ +#define ENET_TXFIFO_WRITING ENET_MAC_DBG_TXFW /*!< TxFIFO is doing write operation */ #define ENET_TXFIFO_NOT_EMPTY ENET_MAC_DBG_TXFNE /*!< TxFIFO is not empty */ #define ENET_TXFIFO_FULL ENET_MAC_DBG_TXFF /*!< TxFIFO is full */ @@ -1176,7 +1202,7 @@ typedef struct #define ENET_ADDRESS_FILTER_SA BIT(30) /*!< use MAC address[47:0] is to compare with the SA fields of the received frame */ #define ENET_ADDRESS_FILTER_DA ((uint32_t)0x00000000) /*!< use MAC address[47:0] is to compare with the DA fields of the received frame */ - + /* mac_fcth register value */ #define MAC_FCTH_RFA(regval) ((BITS(0,2) & ((uint32_t)(regval) << 0))<<8) /*!< write value to ENET_MAC_FCTH_RFA bit field */ #define ENET_ACTIVE_THRESHOLD_256BYTES MAC_FCTH_RFA(0) /*!< threshold level is 256 bytes */ @@ -1215,7 +1241,7 @@ typedef struct /* ptp_tsl register value */ #define GET_PTP_TSL_STMSS(regval) GET_BITS((uint32_t)(regval),0,30) /*!< get value of ENET_PTP_TSL_STMSS bit field */ - + #define ENET_PTP_TIME_POSITIVE ((uint32_t)0x00000000) /*!< time value is positive */ #define ENET_PTP_TIME_NEGATIVE ENET_PTP_TSL_STS /*!< time value is negative */ @@ -1259,7 +1285,7 @@ typedef struct #define ENET_PGBL_4BEAT DMA_BCTL_PGBL(4) /*!< maximum number of beats is 4 */ #define ENET_PGBL_8BEAT DMA_BCTL_PGBL(8) /*!< maximum number of beats is 8 */ #define ENET_PGBL_16BEAT DMA_BCTL_PGBL(16) /*!< maximum number of beats is 16 */ -#define ENET_PGBL_32BEAT DMA_BCTL_PGBL(32) /*!< maximum number of beats is 32 */ +#define ENET_PGBL_32BEAT DMA_BCTL_PGBL(32) /*!< maximum number of beats is 32 */ #define ENET_PGBL_4xPGBL_4BEAT (DMA_BCTL_PGBL(1)|ENET_DMA_BCTL_FPBL) /*!< maximum number of beats is 4 */ #define ENET_PGBL_4xPGBL_8BEAT (DMA_BCTL_PGBL(2)|ENET_DMA_BCTL_FPBL) /*!< maximum number of beats is 8 */ #define ENET_PGBL_4xPGBL_16BEAT (DMA_BCTL_PGBL(4)|ENET_DMA_BCTL_FPBL) /*!< maximum number of beats is 16 */ @@ -1271,7 +1297,7 @@ typedef struct #define ENET_ARBITRATION_RXTX_1_1 DMA_BCTL_RTPR(0) /*!< receive and transmit priority ratio is 1:1*/ #define ENET_ARBITRATION_RXTX_2_1 DMA_BCTL_RTPR(1) /*!< receive and transmit priority ratio is 2:1*/ #define ENET_ARBITRATION_RXTX_3_1 DMA_BCTL_RTPR(2) /*!< receive and transmit priority ratio is 3:1 */ -#define ENET_ARBITRATION_RXTX_4_1 DMA_BCTL_RTPR(3) /*!< receive and transmit priority ratio is 4:1 */ +#define ENET_ARBITRATION_RXTX_4_1 DMA_BCTL_RTPR(3) /*!< receive and transmit priority ratio is 4:1 */ #define ENET_ARBITRATION_RXPRIORTX ENET_DMA_BCTL_DAB /*!< RxDMA has higher priority than TxDMA */ #define ENET_FIXED_BURST_ENABLE ENET_DMA_BCTL_FB /*!< AHB can only use SINGLE/INCR4/INCR8/INCR16 during start of normal burst transfers */ @@ -1283,13 +1309,13 @@ typedef struct #define ENET_RXDP_4BEAT DMA_BCTL_RXDP(4) /*!< maximum number of beats 4 */ #define ENET_RXDP_8BEAT DMA_BCTL_RXDP(8) /*!< maximum number of beats 8 */ #define ENET_RXDP_16BEAT DMA_BCTL_RXDP(16) /*!< maximum number of beats 16 */ -#define ENET_RXDP_32BEAT DMA_BCTL_RXDP(32) /*!< maximum number of beats 32 */ +#define ENET_RXDP_32BEAT DMA_BCTL_RXDP(32) /*!< maximum number of beats 32 */ #define ENET_RXDP_4xPGBL_4BEAT (DMA_BCTL_RXDP(1)|ENET_DMA_BCTL_FPBL) /*!< maximum number of beats 4 */ #define ENET_RXDP_4xPGBL_8BEAT (DMA_BCTL_RXDP(2)|ENET_DMA_BCTL_FPBL) /*!< maximum number of beats 8 */ #define ENET_RXDP_4xPGBL_16BEAT (DMA_BCTL_RXDP(4)|ENET_DMA_BCTL_FPBL) /*!< maximum number of beats 16 */ #define ENET_RXDP_4xPGBL_32BEAT (DMA_BCTL_RXDP(8)|ENET_DMA_BCTL_FPBL) /*!< maximum number of beats 32 */ #define ENET_RXDP_4xPGBL_64BEAT (DMA_BCTL_RXDP(16)|ENET_DMA_BCTL_FPBL) /*!< maximum number of beats 64 */ -#define ENET_RXDP_4xPGBL_128BEAT (DMA_BCTL_RXDP(32)|ENET_DMA_BCTL_FPBL) /*!< maximum number of beats 128 */ +#define ENET_RXDP_4xPGBL_128BEAT (DMA_BCTL_RXDP(32)|ENET_DMA_BCTL_FPBL) /*!< maximum number of beats 128 */ #define ENET_RXTX_DIFFERENT_PGBL ENET_DMA_BCTL_UIP /*!< RxDMA uses the RXDP[5:0], while TxDMA uses the PGBL[5:0] */ #define ENET_RXTX_SAME_PGBL ((uint32_t)0x00000000) /*!< RxDMA/TxDMA uses PGBL[5:0] */ @@ -1347,7 +1373,7 @@ typedef struct #define ENET_FLUSH_RXFRAME_ENABLE ((uint32_t)0x00000000) /*!< RxDMA flushes all frames */ #define ENET_FLUSH_RXFRAME_DISABLE ENET_DMA_CTL_DAFRF /*!< RxDMA does not flush any frames */ -#define ENET_FLUSH_RXFRAME ENET_DMA_CTL_DAFRF /*!< RxDMA flushes frames function */ +#define ENET_NO_FLUSH_RXFRAME ENET_DMA_CTL_DAFRF /*!< RxDMA flushes frames function */ #define ENET_TX_MODE_STOREFORWARD ENET_DMA_CTL_TSFD /*!< TxFIFO operates in store-and-forward mode */ #define ENET_TX_MODE_CUTTHROUGH ((uint32_t)0x00000000) /*!< TxFIFO operates in cut-through mode */ @@ -1357,7 +1383,7 @@ typedef struct #define ENET_FORWARD_ERRFRAMES (ENET_DMA_CTL_FERF<<2) /*!< the function that all frame received with error except runt error are forwarded to memory */ #define ENET_FORWARD_UNDERSZ_GOODFRAMES_ENABLE (ENET_DMA_CTL_FUF<<2) /*!< forward undersized good frames */ -#define ENET_FORWARD_UNDERSZ_GOODFRAMES_DISABLE ((uint32_t)0x00000000) /*!< RxFIFO drops all frames whose length is less than 64 bytes */ +#define ENET_FORWARD_UNDERSZ_GOODFRAMES_DISABLE ((uint32_t)0x00000000) /*!< RxFIFO drops all frames whose length is less than 64 bytes */ #define ENET_FORWARD_UNDERSZ_GOODFRAMES (ENET_DMA_CTL_FUF<<2) /*!< the function that forwarding undersized good frames */ #define ENET_SECONDFRAME_OPT_ENABLE ENET_DMA_CTL_OSF /*!< TxDMA controller operate on second frame mode enable*/ @@ -1376,10 +1402,10 @@ typedef struct #define GET_TDES0_COCNT(regval) GET_BITS((regval),3,6) /*!< get value of ENET DMA TDES0 CONT bit field */ #define TDES0_CM(regval) (BITS(22,23) & ((uint32_t)(regval) << 22)) /*!< write value to ENET DMA TDES0 CM bit field */ -#define ENET_CHECKSUM_DISABLE TDES0_CM(0) /*!< checksum insertion disabled */ -#define ENET_CHECKSUM_IPV4HEADER TDES0_CM(1) /*!< only IP header checksum calculation and insertion are enabled */ -#define ENET_CHECKSUM_TCPUDPICMP_SEGMENT TDES0_CM(2) /*!< TCP/UDP/ICMP checksum insertion calculated but pseudo-header */ -#define ENET_CHECKSUM_TCPUDPICMP_FULL TDES0_CM(3) /*!< TCP/UDP/ICMP checksum insertion fully calculated */ +#define ENET_CHECKSUM_DISABLE TDES0_CM(0) /*!< checksum insertion disabled */ +#define ENET_CHECKSUM_IPV4HEADER TDES0_CM(1) /*!< only IP header checksum calculation and insertion are enabled */ +#define ENET_CHECKSUM_TCPUDPICMP_SEGMENT TDES0_CM(2) /*!< TCP/UDP/ICMP checksum insertion calculated but pseudo-header */ +#define ENET_CHECKSUM_TCPUDPICMP_FULL TDES0_CM(3) /*!< TCP/UDP/ICMP checksum insertion fully calculated */ /* dma tx descriptor tdes1 register value */ #define TDES1_TB1S(regval) (BITS(0,12) & ((uint32_t)(regval) << 0)) /*!< write value to ENET DMA TDES1 TB1S bit field */ @@ -1413,18 +1439,18 @@ typedef struct #define ENET_MSC_PRESET_MASK (~(ENET_MSC_CTL_PMC | ENET_MSC_CTL_AFHPM)) /*!< ENET_MSC_CTL preset mask */ #ifdef SELECT_DESCRIPTORS_ENHANCED_MODE -#define ETH_DMATXDESC_SIZE 0x20U /*!< TxDMA enhanced descriptor size */ -#define ETH_DMARXDESC_SIZE 0x20U /*!< RxDMA enhanced descriptor size */ +#define ETH_DMATXDESC_SIZE ((uint32_t)0x00000020U) /*!< TxDMA enhanced descriptor size */ +#define ETH_DMARXDESC_SIZE ((uint32_t)0x00000020U) /*!< RxDMA enhanced descriptor size */ #else -#define ETH_DMATXDESC_SIZE 0x10U /*!< TxDMA descriptor size */ -#define ETH_DMARXDESC_SIZE 0x10U /*!< RxDMA descriptor size */ -#endif /* SELECT_DESCRIPTORS_ENHANCED_MODE */ +#define ETH_DMATXDESC_SIZE ((uint32_t)0x00000010U) /*!< TxDMA descriptor size */ +#define ETH_DMARXDESC_SIZE ((uint32_t)0x00000010U) /*!< RxDMA descriptor size */ +#endif /* SELECT_DESCRIPTORS_ENHANCED_MODE */ /* ENET remote wake-up frame register length */ #define ETH_WAKEUP_REGISTER_LENGTH 8U /*!< remote wake-up frame register length */ -/* ENET frame size */ -#define ENET_MAX_FRAME_SIZE 1524U /*!< header + frame_extra + payload + CRC */ +/* ENET frame size */ +#define ENET_MAX_FRAME_SIZE 1524U /*!< header + frame_extra + payload + CRC */ /* ENET delay timeout */ #define ENET_DELAY_TO ((uint32_t)0x0004FFFFU) /*!< ENET delay timeout */ @@ -1459,12 +1485,12 @@ ErrStatus enet_frame_transmit(uint8_t *buffer, uint32_t length); /* configure the transmit IP frame checksum offload calculation and insertion */ void enet_transmit_checksum_config(enet_descriptors_struct *desc, uint32_t checksum); /* ENET Tx and Rx function enable (include MAC and DMA module) */ -void enet_enable(void); +void enet_enable(void); /* ENET Tx and Rx function disable (include MAC and DMA module) */ void enet_disable(void); /* configure MAC address */ void enet_mac_address_set(enet_macaddress_enum mac_addr, uint8_t paddr[]); -/* get MAC address */ +/* get MAC address */ void enet_mac_address_get(enet_macaddress_enum mac_addr, uint8_t paddr[]); /* get the ENET MAC/MSC/PTP/DMA status flag */ @@ -1532,7 +1558,7 @@ void enet_flowcontrol_feature_disable(uint32_t feature); /* DMA function */ /* get the dma transmit/receive process state */ -uint32_t enet_dmaprocess_state_get(enet_dmadirection_enum direction); +uint32_t enet_dmaprocess_state_get(enet_dmadirection_enum direction); /* poll the dma transmission/reception enable */ void enet_dmaprocess_resume(enet_dmadirection_enum direction); /* check and recover the Rx process */ @@ -1552,7 +1578,7 @@ FlagStatus enet_desc_flag_get(enet_descriptors_struct *desc, uint32_t desc_flag) /* set the bit flag of ENET dma tx descriptor */ void enet_desc_flag_set(enet_descriptors_struct *desc, uint32_t desc_flag); /* clear the bit flag of ENET dma tx descriptor */ -void enet_desc_flag_clear(enet_descriptors_struct *desc, uint32_t desc_flag); +void enet_desc_flag_clear(enet_descriptors_struct *desc, uint32_t desc_flag); /* when receiving the completed, set RS bit in ENET_DMA_STAT register will immediately set */ void enet_rx_desc_immediate_receive_complete_interrupt(enet_descriptors_struct *desc); /* when receiving the completed, set RS bit in ENET_DMA_STAT register will is set after a configurable delay time */ @@ -1616,13 +1642,13 @@ void enet_wum_feature_disable(uint32_t feature); /* MSC function */ /* reset the MAC statistics counters */ void enet_msc_counters_reset(void); -/* enable the MAC statistics counter features */ +/* enable the MAC statistics counter features */ void enet_msc_feature_enable(uint32_t feature); -/* disable the MAC statistics counter features */ +/* disable the MAC statistics counter features */ void enet_msc_feature_disable(uint32_t feature); /* configure MAC statistics counters preset mode */ void enet_msc_counters_preset_config(enet_msc_preset_enum mode); -/* get MAC statistics counter */ +/* get MAC statistics counter */ uint32_t enet_msc_counters_get(enet_msc_counter_enum counter); /* PTP function */ @@ -1649,16 +1675,6 @@ void enet_ptp_pps_output_frequency_config(uint32_t freq); /* internal function */ /* reset the ENET initpara struct, call it before using enet_initpara_config() */ void enet_initpara_reset(void); -/* initialize ENET peripheral with generally concerned parameters, call it by enet_init() */ -static void enet_default_init(void); -#ifdef USE_DELAY -/* user can provide more timing precise _ENET_DELAY_ function */ -#define _ENET_DELAY_ delay_ms -#else -/* insert a delay time */ -static void enet_delay(uint32_t ncount); -/* default _ENET_DELAY_ function with less precise timing */ -#define _ENET_DELAY_ enet_delay -#endif + #endif /* GD32F4XX_ENET_H */ diff --git a/bsp/gd32450z-eval/Libraries/GD32F4xx_standard_peripheral/Include/gd32f4xx_exmc.h b/bsp/gd32450z-eval/Libraries/GD32F4xx_standard_peripheral/Include/gd32f4xx_exmc.h index 3844c699d2..94baf2f6f3 100644 --- a/bsp/gd32450z-eval/Libraries/GD32F4xx_standard_peripheral/Include/gd32f4xx_exmc.h +++ b/bsp/gd32450z-eval/Libraries/GD32F4xx_standard_peripheral/Include/gd32f4xx_exmc.h @@ -1,12 +1,37 @@ /*! - \file gd32f4xx_exmc.h - \brief definitions for the EXMC + \file gd32f4xx_exmc.h + \brief definitions for the EXMC + + \version 2016-08-15, V1.0.0, firmware for GD32F4xx + \version 2018-12-12, V2.0.0, firmware for GD32F4xx + \version 2020-09-30, V2.1.0, firmware for GD32F4xx */ /* - Copyright (C) 2016 GigaDevice + Copyright (c) 2020, GigaDevice Semiconductor Inc. + + Redistribution and use in source and binary forms, with or without modification, +are permitted provided that the following conditions are met: + + 1. Redistributions of source code must retain the above copyright notice, this + list of conditions and the following disclaimer. + 2. Redistributions in binary form must reproduce the above copyright notice, + this list of conditions and the following disclaimer in the documentation + and/or other materials provided with the distribution. + 3. Neither the name of the copyright holder nor the names of its contributors + may be used to endorse or promote products derived from this software without + specific prior written permission. - 2016-08-15, V1.0.0, firmware for GD32F4xx + THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED +WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. +IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, +INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT +NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR +PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, +WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY +OF SUCH DAMAGE. */ #ifndef GD32F4XX_EXMC_H @@ -15,224 +40,224 @@ #include "gd32f4xx.h" /* EXMC definitions */ -#define EXMC (EXMC_BASE) /*!< EXMC register base address */ -#define EXMC_NOR_PSRAM (EXMC_BASE - 0x40000000) /*!< EXMC NOR/PSRAM base address */ -#define EXMC_NAND (EXMC_BASE - 0x30000000) /*!< EXMC NAND base address */ -#define EXMC_PCCARD (EXMC_BASE - 0x10000000) /*!< EXMC PC card base address */ -#define EXMC_SDRAM (EXMC_BASE + 0x20000000) /*!< EXMC SDRAM base address */ +#define EXMC (EXMC_BASE) /*!< EXMC register base address */ +#define EXMC_NOR_PSRAM (EXMC_BASE - 0x40000000) /*!< EXMC NOR/PSRAM base address */ +#define EXMC_NAND (EXMC_BASE - 0x30000000) /*!< EXMC NAND base address */ +#define EXMC_PCCARD (EXMC_BASE - 0x10000000) /*!< EXMC PC card base address */ +#define EXMC_SDRAM (EXMC_BASE + 0x20000000) /*!< EXMC SDRAM base address */ /* registers definitions */ /* NOR/PSRAM */ -#define EXMC_SNCTL0 REG32(EXMC + 0x00U) /*!< EXMC SRAM/NOR flash control register */ -#define EXMC_SNTCFG0 REG32(EXMC + 0x04U) /*!< EXMC SRAM/NOR flash timing configuration register */ -#define EXMC_SNWTCFG0 REG32(EXMC + 0x104U) /*!< EXMC SRAM/NOR flash write timing configuration register */ +#define EXMC_SNCTL0 REG32(EXMC + 0x00U) /*!< EXMC SRAM/NOR flash control register for region0 */ +#define EXMC_SNTCFG0 REG32(EXMC + 0x04U) /*!< EXMC SRAM/NOR flash timing configuration register for region0 */ +#define EXMC_SNWTCFG0 REG32(EXMC + 0x104U) /*!< EXMC SRAM/NOR flash write timing configuration register for region0 */ -#define EXMC_SNCTL1 REG32(EXMC + 0x08U) /*!< EXMC SRAM/NOR flash control register */ -#define EXMC_SNTCFG1 REG32(EXMC + 0x0CU) /*!< EXMC SRAM/NOR flash timing configuration register */ -#define EXMC_SNWTCFG1 REG32(EXMC + 0x10CU) /*!< EXMC SRAM/NOR flash write timing configuration register */ +#define EXMC_SNCTL1 REG32(EXMC + 0x08U) /*!< EXMC SRAM/NOR flash control register for region1 */ +#define EXMC_SNTCFG1 REG32(EXMC + 0x0CU) /*!< EXMC SRAM/NOR flash timing configuration register for region1 */ +#define EXMC_SNWTCFG1 REG32(EXMC + 0x10CU) /*!< EXMC SRAM/NOR flash write timing configuration register for region1 */ -#define EXMC_SNCTL2 REG32(EXMC + 0x10U) /*!< EXMC SRAM/NOR flash control register */ -#define EXMC_SNTCFG2 REG32(EXMC + 0x14U) /*!< EXMC SRAM/NOR flash timing configuration register */ -#define EXMC_SNWTCFG2 REG32(EXMC + 0x114U) /*!< EXMC SRAM/NOR flash write timing configuration register */ +#define EXMC_SNCTL2 REG32(EXMC + 0x10U) /*!< EXMC SRAM/NOR flash control register for region2 */ +#define EXMC_SNTCFG2 REG32(EXMC + 0x14U) /*!< EXMC SRAM/NOR flash timing configuration register for region2 */ +#define EXMC_SNWTCFG2 REG32(EXMC + 0x114U) /*!< EXMC SRAM/NOR flash write timing configuration register for region2 */ -#define EXMC_SNCTL3 REG32(EXMC + 0x18U) /*!< EXMC SRAM/NOR flash control register */ -#define EXMC_SNTCFG3 REG32(EXMC + 0x1CU) /*!< EXMC SRAM/NOR flash timing configuration register */ -#define EXMC_SNWTCFG3 REG32(EXMC + 0x11CU) /*!< EXMC SRAM/NOR flash write timing configuration register */ +#define EXMC_SNCTL3 REG32(EXMC + 0x18U) /*!< EXMC SRAM/NOR flash control register for region3 */ +#define EXMC_SNTCFG3 REG32(EXMC + 0x1CU) /*!< EXMC SRAM/NOR flash timing configuration register for region3 */ +#define EXMC_SNWTCFG3 REG32(EXMC + 0x11CU) /*!< EXMC SRAM/NOR flash write timing configuration register for region3 */ /* NAND/PC card */ -#define EXMC_NPCTL1 REG32(EXMC + 0x40U) /*!< EXMC NAND/PC card control register */ -#define EXMC_NPINTEN1 REG32(EXMC + 0x44U) /*!< EXMC NAND/PC card interrupt enable register */ -#define EXMC_NPCTCFG1 REG32(EXMC + 0x48U) /*!< EXMC NAND/PC card common space timing configuration register */ -#define EXMC_NPATCFG1 REG32(EXMC + 0x4CU) /*!< EXMC NAND/PC card attribute space timing configuration register */ -#define EXMC_NECC1 REG32(EXMC + 0x54U) /*!< EXMC NAND ECC register */ +#define EXMC_NPCTL1 REG32(EXMC + 0x60U) /*!< EXMC NAND/PC card control register for bank1 */ +#define EXMC_NPINTEN1 REG32(EXMC + 0x64U) /*!< EXMC NAND/PC card interrupt enable register for bank1 */ +#define EXMC_NPCTCFG1 REG32(EXMC + 0x68U) /*!< EXMC NAND/PC card common space timing configuration register for bank1 */ +#define EXMC_NPATCFG1 REG32(EXMC + 0x6CU) /*!< EXMC NAND/PC card attribute space timing configuration register for bank1 */ +#define EXMC_NECC1 REG32(EXMC + 0x74U) /*!< EXMC NAND ECC register */ -#define EXMC_NPCTL2 REG32(EXMC + 0x60U) /*!< EXMC NAND/PC card control register */ -#define EXMC_NPINTEN2 REG32(EXMC + 0x64U) /*!< EXMC NAND/PC card interrupt enable register */ -#define EXMC_NPCTCFG2 REG32(EXMC + 0x68U) /*!< EXMC NAND/PC card common space timing configuration register */ -#define EXMC_NPATCFG2 REG32(EXMC + 0x6CU) /*!< EXMC NAND/PC card attribute space timing configuration register */ -#define EXMC_NECC2 REG32(EXMC + 0x74U) /*!< EXMC NAND ECC register */ +#define EXMC_NPCTL2 REG32(EXMC + 0x80U) /*!< EXMC NAND/PC card control register for bank2 */ +#define EXMC_NPINTEN2 REG32(EXMC + 0x84U) /*!< EXMC NAND/PC card interrupt enable register for bank2 */ +#define EXMC_NPCTCFG2 REG32(EXMC + 0x88U) /*!< EXMC NAND/PC card common space timing configuration register for bank2 */ +#define EXMC_NPATCFG2 REG32(EXMC + 0x8CU) /*!< EXMC NAND/PC card attribute space timing configuration register for bank2 */ +#define EXMC_NECC2 REG32(EXMC + 0x94U) /*!< EXMC NAND ECC register */ -#define EXMC_NPCTL3 REG32(EXMC + 0x80U) /*!< EXMC NAND/PC card control register */ -#define EXMC_NPINTEN3 REG32(EXMC + 0x84U) /*!< EXMC NAND/PC card interrupt enable register */ -#define EXMC_NPCTCFG3 REG32(EXMC + 0x88U) /*!< EXMC NAND/PC card common space timing configuration register */ -#define EXMC_NPATCFG3 REG32(EXMC + 0x8CU) /*!< EXMC NAND/PC card attribute space timing configuration register */ -#define EXMC_PIOTCFG3 REG32(EXMC + 0xB0U) /*!< EXMC PC card I/O space timing configuration register */ +#define EXMC_NPCTL3 REG32(EXMC + 0xA0U) /*!< EXMC NAND/PC card control register for bank3 */ +#define EXMC_NPINTEN3 REG32(EXMC + 0xA4U) /*!< EXMC NAND/PC card interrupt enable register for bank3 */ +#define EXMC_NPCTCFG3 REG32(EXMC + 0xA8U) /*!< EXMC NAND/PC card common space timing configuration register for bank3 */ +#define EXMC_NPATCFG3 REG32(EXMC + 0xACU) /*!< EXMC NAND/PC card attribute space timing configuration register for bank3 */ +#define EXMC_PIOTCFG3 REG32(EXMC + 0xB0U) /*!< EXMC PC card I/O space timing configuration register for bank3 */ /* SDRAM */ -#define EXMC_SDCTL0 REG32(EXMC + 0x140U) /*!< EXMC SDRAM control register */ -#define EXMC_SDTCFG0 REG32(EXMC + 0x148U) /*!< EXMC SDRAM timing configuration register register */ +#define EXMC_SDCTL0 REG32(EXMC + 0x140U) /*!< EXMC SDRAM control register for device0 */ +#define EXMC_SDTCFG0 REG32(EXMC + 0x148U) /*!< EXMC SDRAM timing configuration register register for device0 */ -#define EXMC_SDCTL1 REG32(EXMC + 0x144U) /*!< EXMC SDRAM control register */ -#define EXMC_SDTCFG1 REG32(EXMC + 0x14CU) /*!< EXMC SDRAM timing configuration register register */ +#define EXMC_SDCTL1 REG32(EXMC + 0x144U) /*!< EXMC SDRAM control register for device1 */ +#define EXMC_SDTCFG1 REG32(EXMC + 0x14CU) /*!< EXMC SDRAM timing configuration register register for device1 */ -#define EXMC_SDCMD REG32(EXMC + 0x150U) /*!< EXMC SDRAM command register */ -#define EXMC_SDARI REG32(EXMC + 0x154U) /*!< EXMC SDRAM auto-refresh interval register */ -#define EXMC_SDSTAT REG32(EXMC + 0x158U) /*!< EXMC SDRAM status register */ -#define EXMC_SDRSCTL REG32(EXMC + 0x180U) /*!< EXMC SDRAM read sample control register */ +#define EXMC_SDCMD REG32(EXMC + 0x150U) /*!< EXMC SDRAM command register */ +#define EXMC_SDARI REG32(EXMC + 0x154U) /*!< EXMC SDRAM auto-refresh interval register */ +#define EXMC_SDSTAT REG32(EXMC + 0x158U) /*!< EXMC SDRAM status register */ +#define EXMC_SDRSCTL REG32(EXMC + 0x180U) /*!< EXMC SDRAM read sample control register */ /* SQPI PSRAM */ -#define EXMC_SINIT REG32(EXMC + 0x310U) /*!< EXMC SPI initialization register */ -#define EXMC_SRCMD REG32(EXMC + 0x320U) /*!< EXMC SPI read command register */ -#define EXMC_SWCMD REG32(EXMC + 0x330U) /*!< EXMC SPI write command register */ -#define EXMC_SIDL REG32(EXMC + 0x340U) /*!< EXMC SPI ID low register */ -#define EXMC_SIDH REG32(EXMC + 0x350U) /*!< EXMC SPI ID high register */ +#define EXMC_SINIT REG32(EXMC + 0x310U) /*!< EXMC SPI initialization register */ +#define EXMC_SRCMD REG32(EXMC + 0x320U) /*!< EXMC SPI read command register */ +#define EXMC_SWCMD REG32(EXMC + 0x330U) /*!< EXMC SPI write command register */ +#define EXMC_SIDL REG32(EXMC + 0x340U) /*!< EXMC SPI ID low register */ +#define EXMC_SIDH REG32(EXMC + 0x350U) /*!< EXMC SPI ID high register */ /* bits definitions */ /* EXMC_SNCTLx,x=0..3 */ -#define EXMC_SNCTL_NRBKEN BIT(0) /*!< NOR bank enable */ -#define EXMC_SNCTL_NRMUX BIT(1) /*!< NOR bank memory address/data multiplexing */ -#define EXMC_SNCTL_NRTP BITS(2,3) /*!< NOR bank memory type */ -#define EXMC_SNCTL_NRW BITS(4,5) /*!< NOR bank memory data bus width */ -#define EXMC_SNCTL_NREN BIT(6) /*!< NOR flash access enable */ -#define EXMC_SNCTL_SBRSTEN BIT(8) /*!< synchronous burst enable */ -#define EXMC_SNCTL_NRWTPOL BIT(9) /*!< NWAIT signal polarity */ -#define EXMC_SNCTL_WRAPEN BIT(10) /*!< wrapped burst mode enable */ -#define EXMC_SNCTL_NRWTCFG BIT(11) /*!< NWAIT signal configuration, only work in synchronous mode */ -#define EXMC_SNCTL_WREN BIT(12) /*!< write enable */ -#define EXMC_SNCTL_NRWTEN BIT(13) /*!< NWAIT signal enable */ -#define EXMC_SNCTL_EXMODEN BIT(14) /*!< extended mode enable */ -#define EXMC_SNCTL_ASYNCWAIT BIT(15) /*!< asynchronous wait */ -#define EXMC_SNCTL_CPS BITS(16,18) /*!< CRAM page size */ -#define EXMC_SNCTL_SYNCWR BIT(19) /*!< synchronous write */ -#define EXMC_SNCTL_CCK BIT(20) /*!< consecutive clock */ +#define EXMC_SNCTL_NRBKEN BIT(0) /*!< NOR bank enable */ +#define EXMC_SNCTL_NRMUX BIT(1) /*!< NOR bank memory address/data multiplexing enable */ +#define EXMC_SNCTL_NRTP BITS(2,3) /*!< NOR bank memory type */ +#define EXMC_SNCTL_NRW BITS(4,5) /*!< NOR bank memory data bus width */ +#define EXMC_SNCTL_NREN BIT(6) /*!< NOR flash access enable */ +#define EXMC_SNCTL_SBRSTEN BIT(8) /*!< synchronous burst enable */ +#define EXMC_SNCTL_NRWTPOL BIT(9) /*!< NWAIT signal polarity */ +#define EXMC_SNCTL_WRAPEN BIT(10) /*!< wrapped burst mode enable */ +#define EXMC_SNCTL_NRWTCFG BIT(11) /*!< NWAIT signal configuration, only work in synchronous mode */ +#define EXMC_SNCTL_WREN BIT(12) /*!< write enable */ +#define EXMC_SNCTL_NRWTEN BIT(13) /*!< NWAIT signal enable */ +#define EXMC_SNCTL_EXMODEN BIT(14) /*!< extended mode enable */ +#define EXMC_SNCTL_ASYNCWAIT BIT(15) /*!< asynchronous wait enable */ +#define EXMC_SNCTL_CPS BITS(16,18) /*!< CRAM page size */ +#define EXMC_SNCTL_SYNCWR BIT(19) /*!< synchronous write config */ +#define EXMC_SNCTL_CCK BIT(20) /*!< consecutive clock config */ /* EXMC_SNTCFGx,x=0..3 */ -#define EXMC_SNTCFG_ASET BITS(0,3) /*!< address setup time */ -#define EXMC_SNTCFG_AHLD BITS(4,7) /*!< address hold time */ -#define EXMC_SNTCFG_DSET BITS(8,15) /*!< data setup time */ -#define EXMC_SNTCFG_BUSLAT BITS(16,19) /*!< bus latency */ -#define EXMC_SNTCFG_CKDIV BITS(20,23) /*!< synchronous clock divide ratio */ -#define EXMC_SNTCFG_DLAT BITS(24,27) /*!< data latency for NOR flash */ -#define EXMC_SNTCFG_ASYNCMOD BITS(28,29) /*!< asynchronous access mode */ +#define EXMC_SNTCFG_ASET BITS(0,3) /*!< asynchronous address setup time */ +#define EXMC_SNTCFG_AHLD BITS(4,7) /*!< asynchronous address hold time */ +#define EXMC_SNTCFG_DSET BITS(8,15) /*!< asynchronous data setup time */ +#define EXMC_SNTCFG_BUSLAT BITS(16,19) /*!< bus latency */ +#define EXMC_SNTCFG_CKDIV BITS(20,23) /*!< synchronous clock divide ratio */ +#define EXMC_SNTCFG_DLAT BITS(24,27) /*!< synchronous data latency for NOR flash */ +#define EXMC_SNTCFG_ASYNCMOD BITS(28,29) /*!< asynchronous access mode */ /* EXMC_SNWTCFGx,x=0..3 */ -#define EXMC_SNWTCFG_WASET BITS(0,3) /*!< address setup time */ -#define EXMC_SNWTCFG_WAHLD BITS(4,7) /*!< address hold time */ -#define EXMC_SNWTCFG_WDSET BITS(8,15) /*!< data setup time */ -#define EXMC_SNWTCFG_WBUSLAT BITS(16,19) /*!< bus latency */ -#define EXMC_SNWTCFG_WASYNCMOD BITS(28,29) /*!< asynchronous access mode */ +#define EXMC_SNWTCFG_WASET BITS(0,3) /*!< asynchronous address setup time */ +#define EXMC_SNWTCFG_WAHLD BITS(4,7) /*!< asynchronous address hold time */ +#define EXMC_SNWTCFG_WDSET BITS(8,15) /*!< asynchronous data setup time */ +#define EXMC_SNWTCFG_WBUSLAT BITS(16,19) /*!< bus latency */ +#define EXMC_SNWTCFG_WASYNCMOD BITS(28,29) /*!< asynchronous access mode */ /* EXMC_NPCTLx,x=1..3 */ -#define EXMC_NPCTL_NDWTEN BIT(1) /*!< wait feature enable */ -#define EXMC_NPCTL_NDBKEN BIT(2) /*!< NAND bank enable */ -#define EXMC_NPCTL_NDTP BIT(3) /*!< NAND bank memory type */ -#define EXMC_NPCTL_NDW BITS(4,5) /*!< NAND bank memory data bus width */ -#define EXMC_NPCTL_ECCEN BIT(6) /*!< ECC enable */ -#define EXMC_NPCTL_CTR BITS(9,12) /*!< CLE to RE delay */ -#define EXMC_NPCTL_ATR BITS(13,16) /*!< ALE to RE delay */ -#define EXMC_NPCTL_ECCSZ BITS(17,19) /*!< ECC size */ +#define EXMC_NPCTL_NDWTEN BIT(1) /*!< wait feature enable */ +#define EXMC_NPCTL_NDBKEN BIT(2) /*!< NAND bank enable */ +#define EXMC_NPCTL_NDTP BIT(3) /*!< NAND bank memory type */ +#define EXMC_NPCTL_NDW BITS(4,5) /*!< NAND bank memory data bus width */ +#define EXMC_NPCTL_ECCEN BIT(6) /*!< ECC enable */ +#define EXMC_NPCTL_CTR BITS(9,12) /*!< CLE to RE delay */ +#define EXMC_NPCTL_ATR BITS(13,16) /*!< ALE to RE delay */ +#define EXMC_NPCTL_ECCSZ BITS(17,19) /*!< ECC size */ /* EXMC_NPINTENx,x=1..3 */ -#define EXMC_NPINTEN_INTRS BIT(0) /*!< interrupt rising edge status */ -#define EXMC_NPINTEN_INTHS BIT(1) /*!< interrupt high-level status */ -#define EXMC_NPINTEN_INTFS BIT(2) /*!< interrupt falling edge status */ -#define EXMC_NPINTEN_INTREN BIT(3) /*!< interrupt rising edge detection enable */ -#define EXMC_NPINTEN_INTHEN BIT(4) /*!< interrupt high-level detection enable */ -#define EXMC_NPINTEN_INTFEN BIT(5) /*!< interrupt falling edge detection enable */ -#define EXMC_NPINTEN_INTEPT BIT(6) /*!< FIFO empty flag */ +#define EXMC_NPINTEN_INTRS BIT(0) /*!< interrupt rising edge status */ +#define EXMC_NPINTEN_INTHS BIT(1) /*!< interrupt high-level status */ +#define EXMC_NPINTEN_INTFS BIT(2) /*!< interrupt falling edge status */ +#define EXMC_NPINTEN_INTREN BIT(3) /*!< interrupt rising edge detection enable */ +#define EXMC_NPINTEN_INTHEN BIT(4) /*!< interrupt high-level detection enable */ +#define EXMC_NPINTEN_INTFEN BIT(5) /*!< interrupt falling edge detection enable */ +#define EXMC_NPINTEN_FFEPT BIT(6) /*!< FIFO empty flag */ /* EXMC_NPCTCFGx,x=1..3 */ -#define EXMC_NPCTCFG_COMSET BITS(0,7) /*!< common memory data bus HiZ time */ -#define EXMC_NPCTCFG_COMWAIT BITS(8,15) /*!< common memory hold time */ -#define EXMC_NPCTCFG_COMHLD BITS(16,23) /*!< common memory wait time */ -#define EXMC_NPCTCFG_COMHIZ BITS(24,31) /*!< common memory setup time */ +#define EXMC_NPCTCFG_COMSET BITS(0,7) /*!< common memory setup time */ +#define EXMC_NPCTCFG_COMWAIT BITS(8,15) /*!< common memory wait time */ +#define EXMC_NPCTCFG_COMHLD BITS(16,23) /*!< common memory hold time */ +#define EXMC_NPCTCFG_COMHIZ BITS(24,31) /*!< common memory data bus HiZ time */ /* EXMC_NPATCFGx,x=1..3 */ -#define EXMC_NPATCFG_ATTSET BITS(0,7) /*!< attribute memory data bus HiZ time */ -#define EXMC_NPATCFG_ATTWAIT BITS(8,15) /*!< attribute memory hold time */ -#define EXMC_NPATCFG_ATTHLD BITS(16,23) /*!< attribute memory wait time */ -#define EXMC_NPATCFG_ATTHIZ BITS(24,31) /*!< attribute memory setup time */ +#define EXMC_NPATCFG_ATTSET BITS(0,7) /*!< attribute memory setup time */ +#define EXMC_NPATCFG_ATTWAIT BITS(8,15) /*!< attribute memory wait time */ +#define EXMC_NPATCFG_ATTHLD BITS(16,23) /*!< attribute memory hold time */ +#define EXMC_NPATCFG_ATTHIZ BITS(24,31) /*!< attribute memory data bus HiZ time */ /* EXMC_PIOTCFG3 */ -#define EXMC_PIOTCFG3_IOSET BITS(0,7) /*!< IO space data bus HiZ time */ -#define EXMC_PIOTCFG3_IOWAIT BITS(8,15) /*!< IO space hold time */ -#define EXMC_PIOTCFG3_IOHLD BITS(16,23) /*!< IO space wait time */ -#define EXMC_PIOTCFG3_IOHIZ BITS(24,31) /*!< IO space setup time */ +#define EXMC_PIOTCFG3_IOSET BITS(0,7) /*!< IO space setup time */ +#define EXMC_PIOTCFG3_IOWAIT BITS(8,15) /*!< IO space wait time */ +#define EXMC_PIOTCFG3_IOHLD BITS(16,23) /*!< IO space hold time */ +#define EXMC_PIOTCFG3_IOHIZ BITS(24,31) /*!< IO space data bus HiZ time */ /* EXMC_NECCx,x=1..2 */ -#define EXMC_NECC_ECC BITS(0,31) /*!< ECC result */ +#define EXMC_NECC_ECC BITS(0,31) /*!< ECC result */ /* EXMC_SDCTLx,x=0..1 */ -#define EXMC_SDCTL_CAW BITS(0,1) /*!< column address bit width */ -#define EXMC_SDCTL_RAW BITS(2,3) /*!< row address bit width */ -#define EXMC_SDCTL_SDW BITS(4,5) /*!< SDRAM data bus width */ -#define EXMC_SDCTL_NBK BIT(6) /*!< number of banks */ -#define EXMC_SDCTL_CL BIT(7,8) /*!< CAS Latency */ -#define EXMC_SDCTL_WPEN BIT(9) /*!< write protection enable */ -#define EXMC_SDCTL_SDCLK BITS(10,11) /*!< SDRAM clock configuration */ -#define EXMC_SDCTL_BRSTRD BIT(12) /*!< burst read */ -#define EXMC_SDCTL_PIPED BITS(13,14) /*!< pipeline delay */ +#define EXMC_SDCTL_CAW BITS(0,1) /*!< column address bit width */ +#define EXMC_SDCTL_RAW BITS(2,3) /*!< row address bit width */ +#define EXMC_SDCTL_SDW BITS(4,5) /*!< SDRAM data bus width */ +#define EXMC_SDCTL_NBK BIT(6) /*!< number of banks */ +#define EXMC_SDCTL_CL BIT(7,8) /*!< CAS Latency */ +#define EXMC_SDCTL_WPEN BIT(9) /*!< write protection enable */ +#define EXMC_SDCTL_SDCLK BITS(10,11) /*!< SDRAM clock configuration */ +#define EXMC_SDCTL_BRSTRD BIT(12) /*!< burst read enable */ +#define EXMC_SDCTL_PIPED BITS(13,14) /*!< pipeline delay */ /* EXMC_SDTCFGx,x=0..1 */ -#define EXMC_SDTCFG_LMRD BITS(0,3) /*!< load mode register delay */ -#define EXMC_SDTCFG_XSRD BITS(4,7) /*!< exit self-refresh delay */ -#define EXMC_SDTCFG_RASD BITS(8,11) /*!< row address select delay */ -#define EXMC_SDTCFG_ARFD BITS(12,15) /*!< auto refresh delay */ -#define EXMC_SDTCFG_WRD BITS(16,19) /*!< write recovery delay */ -#define EXMC_SDTCFG_RPD BITS(20,23) /*!< row precharge delay */ -#define EXMC_SDTCFG_RCD BITS(24,27) /*!< row to column delay */ +#define EXMC_SDTCFG_LMRD BITS(0,3) /*!< load mode register delay */ +#define EXMC_SDTCFG_XSRD BITS(4,7) /*!< exit self-refresh delay */ +#define EXMC_SDTCFG_RASD BITS(8,11) /*!< row address select delay */ +#define EXMC_SDTCFG_ARFD BITS(12,15) /*!< auto refresh delay */ +#define EXMC_SDTCFG_WRD BITS(16,19) /*!< write recovery delay */ +#define EXMC_SDTCFG_RPD BITS(20,23) /*!< row precharge delay */ +#define EXMC_SDTCFG_RCD BITS(24,27) /*!< row to column delay */ /* EXMC_SDCMD */ -#define EXMC_SDCMD_CMD BITS(0,2) /*!< command */ -#define EXMC_SDCMD_DS1 BIT(3) /*!< device select 1 */ -#define EXMC_SDCMD_DS0 BIT(4) /*!< device select 0 */ -#define EXMC_SDCMD_NARF BITS(5,8) /*!< number of successive auto-refresh */ -#define EXMC_SDCMD_MRC BITS(9,21) /*!< mode register content */ +#define EXMC_SDCMD_CMD BITS(0,2) /*!< command */ +#define EXMC_SDCMD_DS1 BIT(3) /*!< select device1 */ +#define EXMC_SDCMD_DS0 BIT(4) /*!< select device0 */ +#define EXMC_SDCMD_NARF BITS(5,8) /*!< number of successive auto-refresh */ +#define EXMC_SDCMD_MRC BITS(9,21) /*!< mode register content */ /* EXMC_SDARI */ -#define EXMC_SDARI_REC BIT(0) /*!< refresh error flag clear */ -#define EXMC_SDARI_ARINTV BITS(1,13) /*!< auto-refresh interval */ -#define EXMC_SDARI_REIE BIT(14) /*!< interrupt refresh error enable */ +#define EXMC_SDARI_REC BIT(0) /*!< refresh error flag clear */ +#define EXMC_SDARI_ARINTV BITS(1,13) /*!< auto-refresh interval */ +#define EXMC_SDARI_REIE BIT(14) /*!< interrupt refresh error enable */ /* EXMC_SDSTAT */ -#define EXMC_SDSDAT_REIF BIT(0) /*!< refresh error interrupt flag */ -#define EXMC_SDSDAT_STA0 BITS(1,2) /*!< device 0 status */ -#define EXMC_SDSDAT_STA1 BITS(3,4) /*!< device 1 status */ -#define EXMC_SDSDAT_NRDY BIT(5) /*!< not ready status */ +#define EXMC_SDSDAT_REIF BIT(0) /*!< refresh error interrupt flag */ +#define EXMC_SDSDAT_STA0 BITS(1,2) /*!< device0 status */ +#define EXMC_SDSDAT_STA1 BITS(3,4) /*!< device1 status */ +#define EXMC_SDSDAT_NRDY BIT(5) /*!< not ready status */ /* EXMC_SDRSCTL */ -#define EXMC_SDRSCTL_RSEN BIT(0) /*!< read sample enable */ -#define EXMC_SDRSCTL_SSCR BIT(1) /*!< select sample cycle of read data */ -#define EXMC_SDRSCTL_SDSC BITS(4,7) /*!< select the delayed sample clock of read data */ +#define EXMC_SDRSCTL_RSEN BIT(0) /*!< read sample enable */ +#define EXMC_SDRSCTL_SSCR BIT(1) /*!< select sample cycle of read data */ +#define EXMC_SDRSCTL_SDSC BITS(4,7) /*!< select the delayed sample clock of read data */ /* EXMC_SINIT */ -#define EXMC_SINIT_CMDBIT BITS(16,17) /*!< bit number of SPI PSRAM command phase */ -#define EXMC_SINIT_ARDBIT BITS(24,28) /*!< bit number of SPI PSRAM address phase */ -#define EXMC_SINIT_IDL BITS(29,30) /*!< SPI PSRAM ID length */ -#define EXMC_SINIT_POL BIT(31) /*!< read data sample polarity */ +#define EXMC_SINIT_CMDBIT BITS(16,17) /*!< bit number of SPI PSRAM command phase */ +#define EXMC_SINIT_ARDBIT BITS(24,28) /*!< bit number of SPI PSRAM address phase */ +#define EXMC_SINIT_IDL BITS(29,30) /*!< SPI PSRAM ID length */ +#define EXMC_SINIT_POL BIT(31) /*!< read data sample polarity */ /* EXMC_SRCMD */ -#define EXMC_SRCMD_RCMD BITS(0,15) /*!< SPI read command for AHB read transfer */ -#define EXMC_SRCMD_RWAITCYCLE BITS(16,19) /*!< SPI read wait cycle number after address phase */ -#define EXMC_SRCMD_RMODE BITS(20,21) /*!< SPI PSRAM read command mode */ -#define EXMC_SRCMD_RDID BIT(31) /*!< send SPI read ID command */ +#define EXMC_SRCMD_RCMD BITS(0,15) /*!< SPI read command for AHB read transfer */ +#define EXMC_SRCMD_RWAITCYCLE BITS(16,19) /*!< SPI read wait cycle number after address phase */ +#define EXMC_SRCMD_RMODE BITS(20,21) /*!< SPI PSRAM read command mode */ +#define EXMC_SRCMD_RDID BIT(31) /*!< send SPI read ID command */ /* EXMC_SWCMD */ -#define EXMC_SWCMD_WCMD BITS(0,15) /*!< send SPI special command */ -#define EXMC_SWCMD_WWAITCYCLE BITS(16,19) /*!< SPI PSRAM write command mode */ -#define EXMC_SWCMD_WMODE BITS(20,21) /*!< SPI write wait cycle number after address phase */ -#define EXMC_SWCMD_SC BIT(31) /*!< SPI write command for AHB write transfer */ +#define EXMC_SWCMD_WCMD BITS(0,15) /*!< SPI write command for AHB write transfer */ +#define EXMC_SWCMD_WWAITCYCLE BITS(16,19) /*!< SPI write wait cycle number after address phase */ +#define EXMC_SWCMD_WMODE BITS(20,21) /*!< SPI PSRAM write command mode */ +#define EXMC_SWCMD_SC BIT(31) /*!< send SPI special command */ /* EXMC_SIDL */ -#define EXMC_SIDL_SIDL BITS(0,31) /*!< ID low data saved for SPI read ID command */ +#define EXMC_SIDL_SIDL BITS(0,31) /*!< ID low data saved for SPI read ID command */ /* EXMC_SIDH */ -#define EXMC_SIDL_SIDH BITS(0,31) /*!< ID high Data saved for SPI read ID command */ +#define EXMC_SIDL_SIDH BITS(0,31) /*!< ID high Data saved for SPI read ID command */ /* constants definitions */ -/* EXMC NOR/SRAM timing initialize struct */ +/* EXMC NOR/SRAM timing initialize structure */ typedef struct { uint32_t asyn_access_mode; /*!< asynchronous access mode */ uint32_t syn_data_latency; /*!< configure the data latency */ uint32_t syn_clk_division; /*!< configure the clock divide ratio */ uint32_t bus_latency; /*!< configure the bus latency */ - uint32_t asyn_data_setuptime; /*!< configure the data setup time,asynchronous access mode valid */ - uint32_t asyn_address_holdtime; /*!< configure the address hold time,asynchronous access mode valid */ - uint32_t asyn_address_setuptime; /*!< configure the data setup time,asynchronous access mode valid */ + uint32_t asyn_data_setuptime; /*!< configure the data setup time, asynchronous access mode valid */ + uint32_t asyn_address_holdtime; /*!< configure the address hold time, asynchronous access mode valid */ + uint32_t asyn_address_setuptime; /*!< configure the address setup time, asynchronous access mode valid */ }exmc_norsram_timing_parameter_struct; -/* EXMC NOR/SRAM initialize struct */ +/* EXMC NOR/SRAM initialize structure */ typedef struct { uint32_t norsram_region; /*!< select the region of EXMC NOR/SRAM bank */ @@ -248,7 +273,7 @@ typedef struct uint32_t databus_width; /*!< specifies the databus width of external memory */ uint32_t memory_type; /*!< specifies the type of external memory */ uint32_t address_data_mux; /*!< specifies whether the data bus and address bus are multiplexed */ - exmc_norsram_timing_parameter_struct* read_write_timing; /*!< timing parameters for read and write if the extendedmode is not used or the timing + exmc_norsram_timing_parameter_struct* read_write_timing; /*!< timing parameters for read and write if the extendedmode is not used or the timing parameters for read if the extendedmode is used. */ exmc_norsram_timing_parameter_struct* write_timing; /*!< timing parameters for write when the extendedmode is used. */ }exmc_norsram_parameter_struct; @@ -265,15 +290,15 @@ typedef struct /* EXMC NAND initialize struct */ typedef struct { - uint32_t nand_bank; /*!< select the bank of NAND */ + uint32_t nand_bank; /*!< select the bank of NAND */ uint32_t ecc_size; /*!< the page size for the ECC calculation */ uint32_t atr_latency; /*!< configure the latency of ALE low to RB low */ uint32_t ctr_latency; /*!< configure the latency of CLE low to RB low */ uint32_t ecc_logic; /*!< enable or disable the ECC calculation logic */ uint32_t databus_width; /*!< the NAND flash databus width */ - uint32_t wait_feature; /*!< enables or disables the wait feature */ - exmc_nand_pccard_timing_parameter_struct* common_space_timing; /*!< the timing parameters for NAND flash Common Space */ - exmc_nand_pccard_timing_parameter_struct* attribute_space_timing; /*!< the timing parameters for NAND flash Attribute Space */ + uint32_t wait_feature; /*!< enable or disable the wait feature */ + exmc_nand_pccard_timing_parameter_struct* common_space_timing; /*!< the timing parameters for NAND flash common space */ + exmc_nand_pccard_timing_parameter_struct* attribute_space_timing; /*!< the timing parameters for NAND flash attribute space */ }exmc_nand_parameter_struct; /* EXMC PC card initialize struct */ @@ -281,11 +306,11 @@ typedef struct { uint32_t atr_latency; /*!< configure the latency of ALE low to RB low */ uint32_t ctr_latency; /*!< configure the latency of CLE low to RB low */ - uint32_t wait_feature; /*!< enables or disables the Wait feature */ - exmc_nand_pccard_timing_parameter_struct* common_space_timing; /*!< the timing parameters for NAND flash Common Space */ - exmc_nand_pccard_timing_parameter_struct* attribute_space_timing; /*!< the timing parameters for NAND flash Attribute Space */ - exmc_nand_pccard_timing_parameter_struct* io_space_timing; /*!< the timing parameters for NAND flash IO Space */ -}exmc_pccard_parameter_struct;; + uint32_t wait_feature; /*!< enable or disable the wait feature */ + exmc_nand_pccard_timing_parameter_struct* common_space_timing; /*!< the timing parameters for PC card common space */ + exmc_nand_pccard_timing_parameter_struct* attribute_space_timing; /*!< the timing parameters for PC card attribute space */ + exmc_nand_pccard_timing_parameter_struct* io_space_timing; /*!< the timing parameters for PC card IO space */ +}exmc_pccard_parameter_struct; /* EXMC SDRAM timing initialize struct */ typedef struct @@ -293,7 +318,7 @@ typedef struct uint32_t row_to_column_delay; /*!< configure the row to column delay */ uint32_t row_precharge_delay; /*!< configure the row precharge delay */ uint32_t write_recovery_delay; /*!< configure the write recovery delay */ - uint32_t auto_refresh_delay; /*!< configure the auto refresh delay */ + uint32_t auto_refresh_delay; /*!< configure the auto refresh delay */ uint32_t row_address_select_delay; /*!< configure the row address select delay */ uint32_t exit_selfrefresh_delay; /*!< configure the exit self-refresh delay */ uint32_t load_mode_register_delay; /*!< configure the load mode register delay */ @@ -308,7 +333,7 @@ typedef struct uint32_t sdclock_config; /*!< the SDCLK memory clock for both SDRAM banks */ uint32_t write_protection; /*!< enable or disable SDRAM bank write protection function */ uint32_t cas_latency; /*!< configure the SDRAM CAS latency */ - uint32_t internal_bank_number; /*!< the number internal banks */ + uint32_t internal_bank_number; /*!< the number of internal bank */ uint32_t data_width; /*!< the databus width of SDRAM memory */ uint32_t row_address_width; /*!< the bit width of a row address */ uint32_t column_address_width; /*!< the bit width of a column address */ @@ -333,400 +358,414 @@ typedef struct{ }exmc_sqpipsram_parameter_struct; /* EXMC_register address */ -#define EXMC_SNCTL(bank) REG32(EXMC + 0x08U*((uint32_t)(bank))) /*!< EXMC SRAM/NOR flash control register */ -#define EXMC_SNTCFG(bank) REG32(EXMC + 0x04U + 0x08U*(bank)) /*!< EXMC SRAM/NOR flash timing configuration register */ -#define EXMC_SNWTCFG(bank) REG32(EXMC + 0x104U + 0x08U*(bank)) /*!< EXMC SRAM/NOR flash write timing configuration register */ +#define EXMC_SNCTL(region) REG32(EXMC + 0x08U*((uint32_t)(region))) /*!< EXMC SRAM/NOR flash control registers, region = 0,1,2,3 */ +#define EXMC_SNTCFG(region) REG32(EXMC + 0x04U + 0x08U*((uint32_t)(region))) /*!< EXMC SRAM/NOR flash timing configuration registers, region = 0,1,2,3 */ +#define EXMC_SNWTCFG(region) REG32(EXMC + 0x104U + 0x08U*((uint32_t)(region))) /*!< EXMC SRAM/NOR flash write timing configuration registers, region = 0,1,2,3 */ -#define EXMC_NPCTL(bank) REG32(EXMC + 0x40U + 0x20U*(bank)) /*!< EXMC NAND/PC card control register */ -#define EXMC_NPINTEN(bank) REG32(EXMC + 0x44U + 0x20U*(bank)) /*!< EXMC NAND/PC card interrupt enable register */ -#define EXMC_NPCTCFG(bank) REG32(EXMC + 0x48U + 0x20U*(bank)) /*!< EXMC NAND/PC card common space timing configuration register */ -#define EXMC_NPATCFG(bank) REG32(EXMC + 0x4CU + 0x20U*(bank)) /*!< EXMC NAND/PC card attribute space timing configuration register */ -#define EXMC_NECC(bank) REG32(EXMC + 0x54U + 0x20U*(bank)) /*!< EXMC NAND ECC register */ +#define EXMC_NPCTL(bank) REG32(EXMC + 0x40U + 0x20U*((uint32_t)(bank))) /*!< EXMC NAND/PC card control registers, bank = 1,2,3 */ +#define EXMC_NPINTEN(bank) REG32(EXMC + 0x44U + 0x20U*((uint32_t)(bank))) /*!< EXMC NAND/PC card interrupt enable registers, bank = 1,2,3 */ +#define EXMC_NPCTCFG(bank) REG32(EXMC + 0x48U + 0x20U*((uint32_t)(bank))) /*!< EXMC NAND/PC card common space timing configuration registers, bank = 1,2,3 */ +#define EXMC_NPATCFG(bank) REG32(EXMC + 0x4CU + 0x20U*((uint32_t)(bank))) /*!< EXMC NAND/PC card attribute space timing configuration registers, bank = 1,2,3 */ +#define EXMC_NECC(bank) REG32(EXMC + 0x54U + 0x20U*((uint32_t)(bank))) /*!< EXMC NAND ECC registers, bank = 1,2 */ -#define EXMC_SDCTL(bank) REG32(EXMC + 0x140U + 0x4U*((bank) - 0x4U)) /*!< EXMC SDRAM control register */ -#define EXMC_SDTCFG(bank) REG32(EXMC + 0x148U + 0x4U*((bank) - 0x4U)) /*!< EXMC SDRAM timing configuration register */ +#define EXMC_SDCTL(device) REG32(EXMC + 0x140U + 0x4U*(((uint32_t)(device)) - 0x4U)) /*!< EXMC SDRAM control registers,device = 0,1 */ +#define EXMC_SDTCFG(device) REG32(EXMC + 0x148U + 0x4U*(((uint32_t)(device)) - 0x4U)) /*!< EXMC SDRAM timing configuration registers,device = 0,1 */ /* CRAM page size */ -#define SNCTL_CPS(regval) (BITS(16,18) & ((uint32_t)(regval) << 16)) -#define EXMC_CRAM_AUTO_SPLIT SNCTL_CPS(0) /*!< automatic burst split on page boundary crossing */ -#define EXMC_CRAM_PAGE_SIZE_128_BYTES SNCTL_CPS(1) /*!< page size is 128 bytes */ -#define EXMC_CRAM_PAGE_SIZE_256_BYTES SNCTL_CPS(2) /*!< page size is 256 bytes */ -#define EXMC_CRAM_PAGE_SIZE_512_BYTES SNCTL_CPS(3) /*!< page size is 512 bytes */ -#define EXMC_CRAM_PAGE_SIZE_1024_BYTES SNCTL_CPS(4) /*!< page size is 1024 bytes */ +#define SNCTL_CPS(regval) (BITS(16,18) & ((uint32_t)(regval) << 16)) +#define EXMC_CRAM_AUTO_SPLIT SNCTL_CPS(0) /*!< automatic burst split on page boundary crossing */ +#define EXMC_CRAM_PAGE_SIZE_128_BYTES SNCTL_CPS(1) /*!< page size is 128 bytes */ +#define EXMC_CRAM_PAGE_SIZE_256_BYTES SNCTL_CPS(2) /*!< page size is 256 bytes */ +#define EXMC_CRAM_PAGE_SIZE_512_BYTES SNCTL_CPS(3) /*!< page size is 512 bytes */ +#define EXMC_CRAM_PAGE_SIZE_1024_BYTES SNCTL_CPS(4) /*!< page size is 1024 bytes */ /* NOR bank memory data bus width */ -#define SNCTL_NRW(regval) (BITS(4,5) & ((uint32_t)(regval) << 4)) -#define EXMC_NOR_DATABUS_WIDTH_8B SNCTL_NRW(0) /*!< NOR data width 8 bits */ -#define EXMC_NOR_DATABUS_WIDTH_16B SNCTL_NRW(1) /*!< NOR data width 16 bits */ +#define SNCTL_NRW(regval) (BITS(4,5) & ((uint32_t)(regval) << 4)) +#define EXMC_NOR_DATABUS_WIDTH_8B SNCTL_NRW(0) /*!< NOR data width is 8 bits */ +#define EXMC_NOR_DATABUS_WIDTH_16B SNCTL_NRW(1) /*!< NOR data width is 16 bits */ /* NOR bank memory type */ -#define SNCTL_NRTP(regval) (BITS(2,3) & ((uint32_t)(regval) << 2)) -#define EXMC_MEMORY_TYPE_SRAM SNCTL_NRTP(0) /*!< SRAM,ROM */ -#define EXMC_MEMORY_TYPE_PSRAM SNCTL_NRTP(1) /*!< PSRAM,CRAM */ -#define EXMC_MEMORY_TYPE_NOR SNCTL_NRTP(2) /*!< NOR flash */ +#define SNCTL_NRTP(regval) (BITS(2,3) & ((uint32_t)(regval) << 2)) +#define EXMC_MEMORY_TYPE_SRAM SNCTL_NRTP(0) /*!< SRAM,ROM */ +#define EXMC_MEMORY_TYPE_PSRAM SNCTL_NRTP(1) /*!< PSRAM,CRAM */ +#define EXMC_MEMORY_TYPE_NOR SNCTL_NRTP(2) /*!< NOR flash */ /* asynchronous access mode */ -#define SNTCFG_ASYNCMOD(regval) (BITS(28,29) & ((uint32_t)(regval) << 28)) -#define EXMC_ACCESS_MODE_A SNTCFG_ASYNCMOD(0) /*!< mode A access */ -#define EXMC_ACCESS_MODE_B SNTCFG_ASYNCMOD(1) /*!< mode B access */ -#define EXMC_ACCESS_MODE_C SNTCFG_ASYNCMOD(2) /*!< mode C access */ -#define EXMC_ACCESS_MODE_D SNTCFG_ASYNCMOD(3) /*!< mode D access */ +#define SNTCFG_ASYNCMOD(regval) (BITS(28,29) & ((uint32_t)(regval) << 28)) +#define EXMC_ACCESS_MODE_A SNTCFG_ASYNCMOD(0) /*!< mode A access */ +#define EXMC_ACCESS_MODE_B SNTCFG_ASYNCMOD(1) /*!< mode B access */ +#define EXMC_ACCESS_MODE_C SNTCFG_ASYNCMOD(2) /*!< mode C access */ +#define EXMC_ACCESS_MODE_D SNTCFG_ASYNCMOD(3) /*!< mode D access */ /* data latency for NOR flash */ -#define SNTCFG_DLAT(regval) (BITS(24,27) & ((uint32_t)(regval) << 24)) -#define EXMC_DATALAT_2_CLK SNTCFG_DLAT(0) /*!< data latency 2 EXMC_CLK */ -#define EXMC_DATALAT_3_CLK SNTCFG_DLAT(1) /*!< data latency 3 EXMC_CLK */ -#define EXMC_DATALAT_4_CLK SNTCFG_DLAT(2) /*!< data latency 4 EXMC_CLK */ -#define EXMC_DATALAT_5_CLK SNTCFG_DLAT(3) /*!< data latency 5 EXMC_CLK */ -#define EXMC_DATALAT_6_CLK SNTCFG_DLAT(4) /*!< data latency 6 EXMC_CLK */ -#define EXMC_DATALAT_7_CLK SNTCFG_DLAT(5) /*!< data latency 7 EXMC_CLK */ -#define EXMC_DATALAT_8_CLK SNTCFG_DLAT(6) /*!< data latency 8 EXMC_CLK */ -#define EXMC_DATALAT_9_CLK SNTCFG_DLAT(7) /*!< data latency 9 EXMC_CLK */ -#define EXMC_DATALAT_10_CLK SNTCFG_DLAT(8) /*!< data latency 10 EXMC_CLK */ -#define EXMC_DATALAT_11_CLK SNTCFG_DLAT(9) /*!< data latency 11 EXMC_CLK */ -#define EXMC_DATALAT_12_CLK SNTCFG_DLAT(10) /*!< data latency 12 EXMC_CLK */ -#define EXMC_DATALAT_13_CLK SNTCFG_DLAT(11) /*!< data latency 13 EXMC_CLK */ -#define EXMC_DATALAT_14_CLK SNTCFG_DLAT(12) /*!< data latency 14 EXMC_CLK */ -#define EXMC_DATALAT_15_CLK SNTCFG_DLAT(13) /*!< data latency 15 EXMC_CLK */ -#define EXMC_DATALAT_16_CLK SNTCFG_DLAT(14) /*!< data latency 16 EXMC_CLK */ -#define EXMC_DATALAT_17_CLK SNTCFG_DLAT(15) /*!< data latency 17 EXMC_CLK */ +#define SNTCFG_DLAT(regval) (BITS(24,27) & ((uint32_t)(regval) << 24)) +#define EXMC_DATALAT_2_CLK SNTCFG_DLAT(0) /*!< data latency of first burst access is 2 EXMC_CLK */ +#define EXMC_DATALAT_3_CLK SNTCFG_DLAT(1) /*!< data latency of first burst access is 3 EXMC_CLK */ +#define EXMC_DATALAT_4_CLK SNTCFG_DLAT(2) /*!< data latency of first burst access is 4 EXMC_CLK */ +#define EXMC_DATALAT_5_CLK SNTCFG_DLAT(3) /*!< data latency of first burst access is 5 EXMC_CLK */ +#define EXMC_DATALAT_6_CLK SNTCFG_DLAT(4) /*!< data latency of first burst access is 6 EXMC_CLK */ +#define EXMC_DATALAT_7_CLK SNTCFG_DLAT(5) /*!< data latency of first burst access is 7 EXMC_CLK */ +#define EXMC_DATALAT_8_CLK SNTCFG_DLAT(6) /*!< data latency of first burst access is 8 EXMC_CLK */ +#define EXMC_DATALAT_9_CLK SNTCFG_DLAT(7) /*!< data latency of first burst access is 9 EXMC_CLK */ +#define EXMC_DATALAT_10_CLK SNTCFG_DLAT(8) /*!< data latency of first burst access is 10 EXMC_CLK */ +#define EXMC_DATALAT_11_CLK SNTCFG_DLAT(9) /*!< data latency of first burst access is 11 EXMC_CLK */ +#define EXMC_DATALAT_12_CLK SNTCFG_DLAT(10) /*!< data latency of first burst access is 12 EXMC_CLK */ +#define EXMC_DATALAT_13_CLK SNTCFG_DLAT(11) /*!< data latency of first burst access is 13 EXMC_CLK */ +#define EXMC_DATALAT_14_CLK SNTCFG_DLAT(12) /*!< data latency of first burst access is 14 EXMC_CLK */ +#define EXMC_DATALAT_15_CLK SNTCFG_DLAT(13) /*!< data latency of first burst access is 15 EXMC_CLK */ +#define EXMC_DATALAT_16_CLK SNTCFG_DLAT(14) /*!< data latency of first burst access is 16 EXMC_CLK */ +#define EXMC_DATALAT_17_CLK SNTCFG_DLAT(15) /*!< data latency of first burst access is 17 EXMC_CLK */ /* synchronous clock divide ratio */ -#define SNTCFG_CKDIV(regval) (BITS(20,23) & ((uint32_t)(regval) << 20)) -#define EXMC_SYN_CLOCK_RATIO_DISABLE SNTCFG_CKDIV(0) /*!< EXMC_CLK disable */ -#define EXMC_SYN_CLOCK_RATIO_2_CLK SNTCFG_CKDIV(1) /*!< EXMC_CLK = 2*HCLK */ -#define EXMC_SYN_CLOCK_RATIO_3_CLK SNTCFG_CKDIV(2) /*!< EXMC_CLK = 3*HCLK */ -#define EXMC_SYN_CLOCK_RATIO_4_CLK SNTCFG_CKDIV(3) /*!< EXMC_CLK = 4*HCLK */ -#define EXMC_SYN_CLOCK_RATIO_5_CLK SNTCFG_CKDIV(4) /*!< EXMC_CLK = 5*HCLK */ -#define EXMC_SYN_CLOCK_RATIO_6_CLK SNTCFG_CKDIV(5) /*!< EXMC_CLK = 6*HCLK */ -#define EXMC_SYN_CLOCK_RATIO_7_CLK SNTCFG_CKDIV(6) /*!< EXMC_CLK = 7*HCLK */ -#define EXMC_SYN_CLOCK_RATIO_8_CLK SNTCFG_CKDIV(7) /*!< EXMC_CLK = 8*HCLK */ -#define EXMC_SYN_CLOCK_RATIO_9_CLK SNTCFG_CKDIV(8) /*!< EXMC_CLK = 9*HCLK */ -#define EXMC_SYN_CLOCK_RATIO_10_CLK SNTCFG_CKDIV(9) /*!< EXMC_CLK = 10*HCLK */ -#define EXMC_SYN_CLOCK_RATIO_11_CLK SNTCFG_CKDIV(10) /*!< EXMC_CLK = 11*HCLK */ -#define EXMC_SYN_CLOCK_RATIO_12_CLK SNTCFG_CKDIV(11) /*!< EXMC_CLK = 12*HCLK */ -#define EXMC_SYN_CLOCK_RATIO_13_CLK SNTCFG_CKDIV(12) /*!< EXMC_CLK = 13*HCLK */ -#define EXMC_SYN_CLOCK_RATIO_14_CLK SNTCFG_CKDIV(13) /*!< EXMC_CLK = 14*HCLK */ -#define EXMC_SYN_CLOCK_RATIO_15_CLK SNTCFG_CKDIV(14) /*!< EXMC_CLK = 15*HCLK */ -#define EXMC_SYN_CLOCK_RATIO_16_CLK SNTCFG_CKDIV(15) /*!< EXMC_CLK = 16*HCLK */ +#define SNTCFG_CKDIV(regval) (BITS(20,23) & ((uint32_t)(regval) << 20)) +#define EXMC_SYN_CLOCK_RATIO_2_CLK SNTCFG_CKDIV(1) /*!< EXMC_CLK = 2*HCLK */ +#define EXMC_SYN_CLOCK_RATIO_3_CLK SNTCFG_CKDIV(2) /*!< EXMC_CLK = 3*HCLK */ +#define EXMC_SYN_CLOCK_RATIO_4_CLK SNTCFG_CKDIV(3) /*!< EXMC_CLK = 4*HCLK */ +#define EXMC_SYN_CLOCK_RATIO_5_CLK SNTCFG_CKDIV(4) /*!< EXMC_CLK = 5*HCLK */ +#define EXMC_SYN_CLOCK_RATIO_6_CLK SNTCFG_CKDIV(5) /*!< EXMC_CLK = 6*HCLK */ +#define EXMC_SYN_CLOCK_RATIO_7_CLK SNTCFG_CKDIV(6) /*!< EXMC_CLK = 7*HCLK */ +#define EXMC_SYN_CLOCK_RATIO_8_CLK SNTCFG_CKDIV(7) /*!< EXMC_CLK = 8*HCLK */ +#define EXMC_SYN_CLOCK_RATIO_9_CLK SNTCFG_CKDIV(8) /*!< EXMC_CLK = 9*HCLK */ +#define EXMC_SYN_CLOCK_RATIO_10_CLK SNTCFG_CKDIV(9) /*!< EXMC_CLK = 10*HCLK */ +#define EXMC_SYN_CLOCK_RATIO_11_CLK SNTCFG_CKDIV(10) /*!< EXMC_CLK = 11*HCLK */ +#define EXMC_SYN_CLOCK_RATIO_12_CLK SNTCFG_CKDIV(11) /*!< EXMC_CLK = 12*HCLK */ +#define EXMC_SYN_CLOCK_RATIO_13_CLK SNTCFG_CKDIV(12) /*!< EXMC_CLK = 13*HCLK */ +#define EXMC_SYN_CLOCK_RATIO_14_CLK SNTCFG_CKDIV(13) /*!< EXMC_CLK = 14*HCLK */ +#define EXMC_SYN_CLOCK_RATIO_15_CLK SNTCFG_CKDIV(14) /*!< EXMC_CLK = 15*HCLK */ +#define EXMC_SYN_CLOCK_RATIO_16_CLK SNTCFG_CKDIV(15) /*!< EXMC_CLK = 16*HCLK */ /* ECC size */ -#define NPCTL_ECCSZ(regval) (BITS(17,19) & ((uint32_t)(regval) << 17)) -#define EXMC_ECC_SIZE_256BYTES NPCTL_ECCSZ(0) /* 256 bytes */ -#define EXMC_ECC_SIZE_512BYTES NPCTL_ECCSZ(1) /* 512 bytes */ -#define EXMC_ECC_SIZE_1024BYTES NPCTL_ECCSZ(2) /* 1024 bytes */ -#define EXMC_ECC_SIZE_2048BYTES NPCTL_ECCSZ(3) /* 2048 bytes */ -#define EXMC_ECC_SIZE_4096BYTES NPCTL_ECCSZ(4) /* 4096 bytes */ -#define EXMC_ECC_SIZE_8192BYTES NPCTL_ECCSZ(5) /* 8192 bytes */ +#define NPCTL_ECCSZ(regval) (BITS(17,19) & ((uint32_t)(regval) << 17)) +#define EXMC_ECC_SIZE_256BYTES NPCTL_ECCSZ(0) /* ECC size is 256 bytes */ +#define EXMC_ECC_SIZE_512BYTES NPCTL_ECCSZ(1) /* ECC size is 512 bytes */ +#define EXMC_ECC_SIZE_1024BYTES NPCTL_ECCSZ(2) /* ECC size is 1024 bytes */ +#define EXMC_ECC_SIZE_2048BYTES NPCTL_ECCSZ(3) /* ECC size is 2048 bytes */ +#define EXMC_ECC_SIZE_4096BYTES NPCTL_ECCSZ(4) /* ECC size is 4096 bytes */ +#define EXMC_ECC_SIZE_8192BYTES NPCTL_ECCSZ(5) /* ECC size is 8192 bytes */ /* ALE to RE delay */ -#define NPCTL_ATR(regval) (BITS(13,16) & ((uint32_t)(regval) << 13)) -#define EXMC_ALE_RE_DELAY_1_HCLK NPCTL_ATR(0) /* ALE to RE delay = 1*HCLK */ -#define EXMC_ALE_RE_DELAY_2_HCLK NPCTL_ATR(1) /* ALE to RE delay = 2*HCLK */ -#define EXMC_ALE_RE_DELAY_3_HCLK NPCTL_ATR(2) /* ALE to RE delay = 3*HCLK */ -#define EXMC_ALE_RE_DELAY_4_HCLK NPCTL_ATR(3) /* ALE to RE delay = 4*HCLK */ -#define EXMC_ALE_RE_DELAY_5_HCLK NPCTL_ATR(4) /* ALE to RE delay = 5*HCLK */ -#define EXMC_ALE_RE_DELAY_6_HCLK NPCTL_ATR(5) /* ALE to RE delay = 6*HCLK */ -#define EXMC_ALE_RE_DELAY_7_HCLK NPCTL_ATR(6) /* ALE to RE delay = 7*HCLK */ -#define EXMC_ALE_RE_DELAY_8_HCLK NPCTL_ATR(7) /* ALE to RE delay = 8*HCLK */ -#define EXMC_ALE_RE_DELAY_9_HCLK NPCTL_ATR(8) /* ALE to RE delay = 9*HCLK */ -#define EXMC_ALE_RE_DELAY_10_HCLK NPCTL_ATR(9) /* ALE to RE delay = 10*HCLK */ -#define EXMC_ALE_RE_DELAY_11_HCLK NPCTL_ATR(10) /* ALE to RE delay = 11*HCLK */ -#define EXMC_ALE_RE_DELAY_12_HCLK NPCTL_ATR(11) /* ALE to RE delay = 12*HCLK */ -#define EXMC_ALE_RE_DELAY_13_HCLK NPCTL_ATR(12) /* ALE to RE delay = 13*HCLK */ -#define EXMC_ALE_RE_DELAY_14_HCLK NPCTL_ATR(13) /* ALE to RE delay = 14*HCLK */ -#define EXMC_ALE_RE_DELAY_15_HCLK NPCTL_ATR(14) /* ALE to RE delay = 15*HCLK */ -#define EXMC_ALE_RE_DELAY_16_HCLK NPCTL_ATR(15) /* ALE to RE delay = 16*HCLK */ +#define NPCTL_ATR(regval) (BITS(13,16) & ((uint32_t)(regval) << 13)) +#define EXMC_ALE_RE_DELAY_1_HCLK NPCTL_ATR(0) /* ALE to RE delay = 1*HCLK */ +#define EXMC_ALE_RE_DELAY_2_HCLK NPCTL_ATR(1) /* ALE to RE delay = 2*HCLK */ +#define EXMC_ALE_RE_DELAY_3_HCLK NPCTL_ATR(2) /* ALE to RE delay = 3*HCLK */ +#define EXMC_ALE_RE_DELAY_4_HCLK NPCTL_ATR(3) /* ALE to RE delay = 4*HCLK */ +#define EXMC_ALE_RE_DELAY_5_HCLK NPCTL_ATR(4) /* ALE to RE delay = 5*HCLK */ +#define EXMC_ALE_RE_DELAY_6_HCLK NPCTL_ATR(5) /* ALE to RE delay = 6*HCLK */ +#define EXMC_ALE_RE_DELAY_7_HCLK NPCTL_ATR(6) /* ALE to RE delay = 7*HCLK */ +#define EXMC_ALE_RE_DELAY_8_HCLK NPCTL_ATR(7) /* ALE to RE delay = 8*HCLK */ +#define EXMC_ALE_RE_DELAY_9_HCLK NPCTL_ATR(8) /* ALE to RE delay = 9*HCLK */ +#define EXMC_ALE_RE_DELAY_10_HCLK NPCTL_ATR(9) /* ALE to RE delay = 10*HCLK */ +#define EXMC_ALE_RE_DELAY_11_HCLK NPCTL_ATR(10) /* ALE to RE delay = 11*HCLK */ +#define EXMC_ALE_RE_DELAY_12_HCLK NPCTL_ATR(11) /* ALE to RE delay = 12*HCLK */ +#define EXMC_ALE_RE_DELAY_13_HCLK NPCTL_ATR(12) /* ALE to RE delay = 13*HCLK */ +#define EXMC_ALE_RE_DELAY_14_HCLK NPCTL_ATR(13) /* ALE to RE delay = 14*HCLK */ +#define EXMC_ALE_RE_DELAY_15_HCLK NPCTL_ATR(14) /* ALE to RE delay = 15*HCLK */ +#define EXMC_ALE_RE_DELAY_16_HCLK NPCTL_ATR(15) /* ALE to RE delay = 16*HCLK */ /* CLE to RE delay */ -#define NPCTL_CTR(regval) (BITS(9,12) & ((uint32_t)(regval) << 9)) -#define EXMC_CLE_RE_DELAY_1_HCLK NPCTL_CTR(0) /* CLE to RE delay = 1*HCLK */ -#define EXMC_CLE_RE_DELAY_2_HCLK NPCTL_CTR(1) /* CLE to RE delay = 2*HCLK */ -#define EXMC_CLE_RE_DELAY_3_HCLK NPCTL_CTR(2) /* CLE to RE delay = 3*HCLK */ -#define EXMC_CLE_RE_DELAY_4_HCLK NPCTL_CTR(3) /* CLE to RE delay = 4*HCLK */ -#define EXMC_CLE_RE_DELAY_5_HCLK NPCTL_CTR(4) /* CLE to RE delay = 5*HCLK */ -#define EXMC_CLE_RE_DELAY_6_HCLK NPCTL_CTR(5) /* CLE to RE delay = 6*HCLK */ -#define EXMC_CLE_RE_DELAY_7_HCLK NPCTL_CTR(6) /* CLE to RE delay = 7*HCLK */ -#define EXMC_CLE_RE_DELAY_8_HCLK NPCTL_CTR(7) /* CLE to RE delay = 8*HCLK */ -#define EXMC_CLE_RE_DELAY_9_HCLK NPCTL_CTR(8) /* CLE to RE delay = 9*HCLK */ -#define EXMC_CLE_RE_DELAY_10_HCLK NPCTL_CTR(9) /* CLE to RE delay = 10*HCLK */ -#define EXMC_CLE_RE_DELAY_11_HCLK NPCTL_CTR(10) /* CLE to RE delay = 11*HCLK */ -#define EXMC_CLE_RE_DELAY_12_HCLK NPCTL_CTR(11) /* CLE to RE delay = 12*HCLK */ -#define EXMC_CLE_RE_DELAY_13_HCLK NPCTL_CTR(12) /* CLE to RE delay = 13*HCLK */ -#define EXMC_CLE_RE_DELAY_14_HCLK NPCTL_CTR(13) /* CLE to RE delay = 14*HCLK */ -#define EXMC_CLE_RE_DELAY_15_HCLK NPCTL_CTR(14) /* CLE to RE delay = 15*HCLK */ -#define EXMC_CLE_RE_DELAY_16_HCLK NPCTL_CTR(15) /* CLE to RE delay = 16*HCLK */ +#define NPCTL_CTR(regval) (BITS(9,12) & ((uint32_t)(regval) << 9)) +#define EXMC_CLE_RE_DELAY_1_HCLK NPCTL_CTR(0) /* CLE to RE delay = 1*HCLK */ +#define EXMC_CLE_RE_DELAY_2_HCLK NPCTL_CTR(1) /* CLE to RE delay = 2*HCLK */ +#define EXMC_CLE_RE_DELAY_3_HCLK NPCTL_CTR(2) /* CLE to RE delay = 3*HCLK */ +#define EXMC_CLE_RE_DELAY_4_HCLK NPCTL_CTR(3) /* CLE to RE delay = 4*HCLK */ +#define EXMC_CLE_RE_DELAY_5_HCLK NPCTL_CTR(4) /* CLE to RE delay = 5*HCLK */ +#define EXMC_CLE_RE_DELAY_6_HCLK NPCTL_CTR(5) /* CLE to RE delay = 6*HCLK */ +#define EXMC_CLE_RE_DELAY_7_HCLK NPCTL_CTR(6) /* CLE to RE delay = 7*HCLK */ +#define EXMC_CLE_RE_DELAY_8_HCLK NPCTL_CTR(7) /* CLE to RE delay = 8*HCLK */ +#define EXMC_CLE_RE_DELAY_9_HCLK NPCTL_CTR(8) /* CLE to RE delay = 9*HCLK */ +#define EXMC_CLE_RE_DELAY_10_HCLK NPCTL_CTR(9) /* CLE to RE delay = 10*HCLK */ +#define EXMC_CLE_RE_DELAY_11_HCLK NPCTL_CTR(10) /* CLE to RE delay = 11*HCLK */ +#define EXMC_CLE_RE_DELAY_12_HCLK NPCTL_CTR(11) /* CLE to RE delay = 12*HCLK */ +#define EXMC_CLE_RE_DELAY_13_HCLK NPCTL_CTR(12) /* CLE to RE delay = 13*HCLK */ +#define EXMC_CLE_RE_DELAY_14_HCLK NPCTL_CTR(13) /* CLE to RE delay = 14*HCLK */ +#define EXMC_CLE_RE_DELAY_15_HCLK NPCTL_CTR(14) /* CLE to RE delay = 15*HCLK */ +#define EXMC_CLE_RE_DELAY_16_HCLK NPCTL_CTR(15) /* CLE to RE delay = 16*HCLK */ /* NAND bank memory data bus width */ -#define NPCTL_NDW(regval) (BITS(4,5) & ((uint32_t)(regval) << 4)) -#define EXMC_NAND_DATABUS_WIDTH_8B NPCTL_NDW(0) /*!< NAND data width 8 bits */ -#define EXMC_NAND_DATABUS_WIDTH_16B NPCTL_NDW(1) /*!< NAND data width 16 bits */ +#define NPCTL_NDW(regval) (BITS(4,5) & ((uint32_t)(regval) << 4)) +#define EXMC_NAND_DATABUS_WIDTH_8B NPCTL_NDW(0) /*!< NAND data width is 8 bits */ +#define EXMC_NAND_DATABUS_WIDTH_16B NPCTL_NDW(1) /*!< NAND data width is 16 bits */ /* SDRAM pipeline delay */ -#define SDCTL_PIPED(regval) (BITS(13,14) & ((uint32_t)(regval) << 13)) -#define EXMC_PIPELINE_DELAY_0_HCLK SDCTL_PIPED(0) /*!< 0 HCLK clock cycle delay */ -#define EXMC_PIPELINE_DELAY_1_HCLK SDCTL_PIPED(1) /*!< 1 HCLK clock cycle delay */ -#define EXMC_PIPELINE_DELAY_2_HCLK SDCTL_PIPED(2) /*!< 2 HCLK clock cycle delay */ +#define SDCTL_PIPED(regval) (BITS(13,14) & ((uint32_t)(regval) << 13)) +#define EXMC_PIPELINE_DELAY_0_HCLK SDCTL_PIPED(0) /*!< 0 HCLK clock cycle delay */ +#define EXMC_PIPELINE_DELAY_1_HCLK SDCTL_PIPED(1) /*!< 1 HCLK clock cycle delay */ +#define EXMC_PIPELINE_DELAY_2_HCLK SDCTL_PIPED(2) /*!< 2 HCLK clock cycle delay */ /* SDRAM clock configuration */ -#define SDCTL_SDCLK(regval) (BITS(10,11) & ((uint32_t)(regval) << 10)) -#define EXMC_SDCLK_DISABLE SDCTL_SDCLK(0) /*!< SDCLK memory clock disabled */ -#define EXMC_SDCLK_PERIODS_2_HCLK SDCTL_SDCLK(2) /*!< SDCLK memory period = 2*HCLK */ -#define EXMC_SDCLK_PERIODS_3_HCLK SDCTL_SDCLK(3) /*!< SDCLK memory period = 3*HCLK */ +#define SDCTL_SDCLK(regval) (BITS(10,11) & ((uint32_t)(regval) << 10)) +#define EXMC_SDCLK_DISABLE SDCTL_SDCLK(0) /*!< SDCLK memory clock disabled */ +#define EXMC_SDCLK_PERIODS_2_HCLK SDCTL_SDCLK(2) /*!< SDCLK memory period = 2*HCLK */ +#define EXMC_SDCLK_PERIODS_3_HCLK SDCTL_SDCLK(3) /*!< SDCLK memory period = 3*HCLK */ /* CAS latency */ -#define SDCTL_CL(regval) (BITS(7,8) & ((uint32_t)(regval) << 7)) -#define EXMC_CAS_LATENCY_1_SDCLK SDCTL_CL(1) /*!< CAS latency is 1 memory clock cycle */ -#define EXMC_CAS_LATENCY_2_SDCLK SDCTL_CL(2) /*!< CAS latency is 2 memory clock cycle */ -#define EXMC_CAS_LATENCY_3_SDCLK SDCTL_CL(3) /*!< CAS latency is 3 memory clock cycle */ +#define SDCTL_CL(regval) (BITS(7,8) & ((uint32_t)(regval) << 7)) +#define EXMC_CAS_LATENCY_1_SDCLK SDCTL_CL(1) /*!< CAS latency is 1 memory clock cycle */ +#define EXMC_CAS_LATENCY_2_SDCLK SDCTL_CL(2) /*!< CAS latency is 2 memory clock cycle */ +#define EXMC_CAS_LATENCY_3_SDCLK SDCTL_CL(3) /*!< CAS latency is 3 memory clock cycle */ /* SDRAM data bus width */ -#define SDCTL_SDW(regval) (BITS(4,5) & ((uint32_t)(regval) << 4)) -#define EXMC_SDRAM_DATABUS_WIDTH_8B SDCTL_SDW(0) /*!< SDRAM data width 8 bits */ -#define EXMC_SDRAM_DATABUS_WIDTH_16B SDCTL_SDW(1) /*!< SDRAM data width 16 bits */ -#define EXMC_SDRAM_DATABUS_WIDTH_32B SDCTL_SDW(2) /*!< SDRAM data width 32 bits */ +#define SDCTL_SDW(regval) (BITS(4,5) & ((uint32_t)(regval) << 4)) +#define EXMC_SDRAM_DATABUS_WIDTH_8B SDCTL_SDW(0) /*!< SDRAM data width 8 bits */ +#define EXMC_SDRAM_DATABUS_WIDTH_16B SDCTL_SDW(1) /*!< SDRAM data width 16 bits */ +#define EXMC_SDRAM_DATABUS_WIDTH_32B SDCTL_SDW(2) /*!< SDRAM data width 32 bits */ /* SDRAM row address bit width */ -#define SDCTL_RAW(regval) (BITS(2,3) & ((uint32_t)(regval) << 2)) -#define EXMC_SDRAM_ROW_ADDRESS_11 SDCTL_RAW(0) /*!< row address bit width is 11 bits */ -#define EXMC_SDRAM_ROW_ADDRESS_12 SDCTL_RAW(1) /*!< row address bit width is 12 bits */ -#define EXMC_SDRAM_ROW_ADDRESS_13 SDCTL_RAW(2) /*!< row address bit width is 13 bits */ +#define SDCTL_RAW(regval) (BITS(2,3) & ((uint32_t)(regval) << 2)) +#define EXMC_SDRAM_ROW_ADDRESS_11 SDCTL_RAW(0) /*!< row address bit width is 11 bits */ +#define EXMC_SDRAM_ROW_ADDRESS_12 SDCTL_RAW(1) /*!< row address bit width is 12 bits */ +#define EXMC_SDRAM_ROW_ADDRESS_13 SDCTL_RAW(2) /*!< row address bit width is 13 bits */ /* SDRAM column address bit width */ -#define SDCTL_CAW(regval) (BITS(0,1) & ((uint32_t)(regval) << 0)) -#define EXMC_SDRAM_COW_ADDRESS_8 SDCTL_CAW(0) /*!< column address bit width is 8 bits */ -#define EXMC_SDRAM_COW_ADDRESS_9 SDCTL_CAW(1) /*!< column address bit width is 9 bits */ -#define EXMC_SDRAM_COW_ADDRESS_10 SDCTL_CAW(2) /*!< column address bit width is 10 bits */ -#define EXMC_SDRAM_COW_ADDRESS_11 SDCTL_CAW(3) /*!< column address bit width is 11 bits */ +#define SDCTL_CAW(regval) (BITS(0,1) & ((uint32_t)(regval) << 0)) +#define EXMC_SDRAM_COW_ADDRESS_8 SDCTL_CAW(0) /*!< column address bit width is 8 bits */ +#define EXMC_SDRAM_COW_ADDRESS_9 SDCTL_CAW(1) /*!< column address bit width is 9 bits */ +#define EXMC_SDRAM_COW_ADDRESS_10 SDCTL_CAW(2) /*!< column address bit width is 10 bits */ +#define EXMC_SDRAM_COW_ADDRESS_11 SDCTL_CAW(3) /*!< column address bit width is 11 bits */ /* SDRAM number of successive auto-refresh */ -#define SDCMD_NARF(regval) (BITS(5,8) & ((uint32_t)(regval) << 5)) -#define EXMC_SDRAM_AUTO_REFLESH_1_SDCLK SDCMD_NARF(0) /*!< 1 auto-refresh cycle */ -#define EXMC_SDRAM_AUTO_REFLESH_2_SDCLK SDCMD_NARF(1) /*!< 2 auto-refresh cycles */ -#define EXMC_SDRAM_AUTO_REFLESH_3_SDCLK SDCMD_NARF(2) /*!< 3 auto-refresh cycles */ -#define EXMC_SDRAM_AUTO_REFLESH_4_SDCLK SDCMD_NARF(3) /*!< 4 auto-refresh cycles */ -#define EXMC_SDRAM_AUTO_REFLESH_5_SDCLK SDCMD_NARF(4) /*!< 5 auto-refresh cycles */ -#define EXMC_SDRAM_AUTO_REFLESH_6_SDCLK SDCMD_NARF(5) /*!< 6 auto-refresh cycles */ -#define EXMC_SDRAM_AUTO_REFLESH_7_SDCLK SDCMD_NARF(6) /*!< 7 auto-refresh cycles */ -#define EXMC_SDRAM_AUTO_REFLESH_8_SDCLK SDCMD_NARF(7) /*!< 8 auto-refresh cycles */ -#define EXMC_SDRAM_AUTO_REFLESH_9_SDCLK SDCMD_NARF(8) /*!< 9 auto-refresh cycles */ -#define EXMC_SDRAM_AUTO_REFLESH_10_SDCLK SDCMD_NARF(9) /*!< 10 auto-refresh cycles */ -#define EXMC_SDRAM_AUTO_REFLESH_11_SDCLK SDCMD_NARF(10) /*!< 11 auto-refresh cycles */ -#define EXMC_SDRAM_AUTO_REFLESH_12_SDCLK SDCMD_NARF(11) /*!< 12 auto-refresh cycles */ -#define EXMC_SDRAM_AUTO_REFLESH_13_SDCLK SDCMD_NARF(12) /*!< 13 auto-refresh cycles */ -#define EXMC_SDRAM_AUTO_REFLESH_14_SDCLK SDCMD_NARF(13) /*!< 14 auto-refresh cycles */ -#define EXMC_SDRAM_AUTO_REFLESH_15_SDCLK SDCMD_NARF(14) /*!< 15 auto-refresh cycles */ +#define SDCMD_NARF(regval) (BITS(5,8) & ((uint32_t)(regval) << 5)) +#define EXMC_SDRAM_AUTO_REFLESH_1_SDCLK SDCMD_NARF(0) /*!< 1 auto-refresh cycle */ +#define EXMC_SDRAM_AUTO_REFLESH_2_SDCLK SDCMD_NARF(1) /*!< 2 auto-refresh cycles */ +#define EXMC_SDRAM_AUTO_REFLESH_3_SDCLK SDCMD_NARF(2) /*!< 3 auto-refresh cycles */ +#define EXMC_SDRAM_AUTO_REFLESH_4_SDCLK SDCMD_NARF(3) /*!< 4 auto-refresh cycles */ +#define EXMC_SDRAM_AUTO_REFLESH_5_SDCLK SDCMD_NARF(4) /*!< 5 auto-refresh cycles */ +#define EXMC_SDRAM_AUTO_REFLESH_6_SDCLK SDCMD_NARF(5) /*!< 6 auto-refresh cycles */ +#define EXMC_SDRAM_AUTO_REFLESH_7_SDCLK SDCMD_NARF(6) /*!< 7 auto-refresh cycles */ +#define EXMC_SDRAM_AUTO_REFLESH_8_SDCLK SDCMD_NARF(7) /*!< 8 auto-refresh cycles */ +#define EXMC_SDRAM_AUTO_REFLESH_9_SDCLK SDCMD_NARF(8) /*!< 9 auto-refresh cycles */ +#define EXMC_SDRAM_AUTO_REFLESH_10_SDCLK SDCMD_NARF(9) /*!< 10 auto-refresh cycles */ +#define EXMC_SDRAM_AUTO_REFLESH_11_SDCLK SDCMD_NARF(10) /*!< 11 auto-refresh cycles */ +#define EXMC_SDRAM_AUTO_REFLESH_12_SDCLK SDCMD_NARF(11) /*!< 12 auto-refresh cycles */ +#define EXMC_SDRAM_AUTO_REFLESH_13_SDCLK SDCMD_NARF(12) /*!< 13 auto-refresh cycles */ +#define EXMC_SDRAM_AUTO_REFLESH_14_SDCLK SDCMD_NARF(13) /*!< 14 auto-refresh cycles */ +#define EXMC_SDRAM_AUTO_REFLESH_15_SDCLK SDCMD_NARF(14) /*!< 15 auto-refresh cycles */ /* SDRAM command select */ -#define SDCMD_CMD(regval) (BITS(0,2) & ((uint32_t)(regval) << 0)) -#define EXMC_SDRAM_NORMAL_OPERATION SDCMD_CMD(0) /*!< normal operation command */ -#define EXMC_SDRAM_CLOCK_ENABLE SDCMD_CMD(1) /*!< clock enable command */ -#define EXMC_SDRAM_PRECHARGE_ALL SDCMD_CMD(2) /*!< precharge all command */ -#define EXMC_SDRAM_AUTO_REFRESH SDCMD_CMD(3) /*!< auto-refresh command */ -#define EXMC_SDRAM_LOAD_MODE_REGISTER SDCMD_CMD(4) /*!< load mode register command */ -#define EXMC_SDRAM_SELF_REFRESH SDCMD_CMD(5) /*!< self-refresh command */ -#define EXMC_SDRAM_POWERDOWN_ENTRY SDCMD_CMD(6) /*!< power-down entry command */ +#define SDCMD_CMD(regval) (BITS(0,2) & ((uint32_t)(regval) << 0)) +#define EXMC_SDRAM_NORMAL_OPERATION SDCMD_CMD(0) /*!< normal operation command */ +#define EXMC_SDRAM_CLOCK_ENABLE SDCMD_CMD(1) /*!< clock enable command */ +#define EXMC_SDRAM_PRECHARGE_ALL SDCMD_CMD(2) /*!< precharge all command */ +#define EXMC_SDRAM_AUTO_REFRESH SDCMD_CMD(3) /*!< auto-refresh command */ +#define EXMC_SDRAM_LOAD_MODE_REGISTER SDCMD_CMD(4) /*!< load mode register command */ +#define EXMC_SDRAM_SELF_REFRESH SDCMD_CMD(5) /*!< self-refresh command */ +#define EXMC_SDRAM_POWERDOWN_ENTRY SDCMD_CMD(6) /*!< power-down entry command */ /* SDRAM the delayed sample clock of read data */ -#define SDRSCTL_SDSC(regval) (BITS(4,7) & ((uint32_t)(regval) << 4)) -#define EXMC_SDRAM_0_DELAY_CELL SDRSCTL_SDSC(0) /*!< select the clock after 0 delay cell */ -#define EXMC_SDRAM_1_DELAY_CELL SDRSCTL_SDSC(1) /*!< select the clock after 1 delay cell */ -#define EXMC_SDRAM_2_DELAY_CELL SDRSCTL_SDSC(2) /*!< select the clock after 2 delay cell */ -#define EXMC_SDRAM_3_DELAY_CELL SDRSCTL_SDSC(3) /*!< select the clock after 3 delay cell */ -#define EXMC_SDRAM_4_DELAY_CELL SDRSCTL_SDSC(4) /*!< select the clock after 4 delay cell */ -#define EXMC_SDRAM_5_DELAY_CELL SDRSCTL_SDSC(5) /*!< select the clock after 5 delay cell */ -#define EXMC_SDRAM_6_DELAY_CELL SDRSCTL_SDSC(6) /*!< select the clock after 6 delay cell */ -#define EXMC_SDRAM_7_DELAY_CELL SDRSCTL_SDSC(7) /*!< select the clock after 7 delay cell */ -#define EXMC_SDRAM_8_DELAY_CELL SDRSCTL_SDSC(8) /*!< select the clock after 8 delay cell */ -#define EXMC_SDRAM_9_DELAY_CELL SDRSCTL_SDSC(9) /*!< select the clock after 9 delay cell */ -#define EXMC_SDRAM_10_DELAY_CELL SDRSCTL_SDSC(10) /*!< select the clock after 10 delay cell */ -#define EXMC_SDRAM_11_DELAY_CELL SDRSCTL_SDSC(11) /*!< select the clock after 11 delay cell */ -#define EXMC_SDRAM_12_DELAY_CELL SDRSCTL_SDSC(12) /*!< select the clock after 12 delay cell */ -#define EXMC_SDRAM_13_DELAY_CELL SDRSCTL_SDSC(13) /*!< select the clock after 13 delay cell */ -#define EXMC_SDRAM_14_DELAY_CELL SDRSCTL_SDSC(14) /*!< select the clock after 14 delay cell */ -#define EXMC_SDRAM_15_DELAY_CELL SDRSCTL_SDSC(15) /*!< select the clock after 15 delay cell */ +#define SDRSCTL_SDSC(regval) (BITS(4,7) & ((uint32_t)(regval) << 4)) +#define EXMC_SDRAM_0_DELAY_CELL SDRSCTL_SDSC(0) /*!< select the clock after 0 delay cell */ +#define EXMC_SDRAM_1_DELAY_CELL SDRSCTL_SDSC(1) /*!< select the clock after 1 delay cell */ +#define EXMC_SDRAM_2_DELAY_CELL SDRSCTL_SDSC(2) /*!< select the clock after 2 delay cell */ +#define EXMC_SDRAM_3_DELAY_CELL SDRSCTL_SDSC(3) /*!< select the clock after 3 delay cell */ +#define EXMC_SDRAM_4_DELAY_CELL SDRSCTL_SDSC(4) /*!< select the clock after 4 delay cell */ +#define EXMC_SDRAM_5_DELAY_CELL SDRSCTL_SDSC(5) /*!< select the clock after 5 delay cell */ +#define EXMC_SDRAM_6_DELAY_CELL SDRSCTL_SDSC(6) /*!< select the clock after 6 delay cell */ +#define EXMC_SDRAM_7_DELAY_CELL SDRSCTL_SDSC(7) /*!< select the clock after 7 delay cell */ +#define EXMC_SDRAM_8_DELAY_CELL SDRSCTL_SDSC(8) /*!< select the clock after 8 delay cell */ +#define EXMC_SDRAM_9_DELAY_CELL SDRSCTL_SDSC(9) /*!< select the clock after 9 delay cell */ +#define EXMC_SDRAM_10_DELAY_CELL SDRSCTL_SDSC(10) /*!< select the clock after 10 delay cell */ +#define EXMC_SDRAM_11_DELAY_CELL SDRSCTL_SDSC(11) /*!< select the clock after 11 delay cell */ +#define EXMC_SDRAM_12_DELAY_CELL SDRSCTL_SDSC(12) /*!< select the clock after 12 delay cell */ +#define EXMC_SDRAM_13_DELAY_CELL SDRSCTL_SDSC(13) /*!< select the clock after 13 delay cell */ +#define EXMC_SDRAM_14_DELAY_CELL SDRSCTL_SDSC(14) /*!< select the clock after 14 delay cell */ +#define EXMC_SDRAM_15_DELAY_CELL SDRSCTL_SDSC(15) /*!< select the clock after 15 delay cell */ /* SPI PSRAM ID length */ -#define SINIT_IDL(regval) (BITS(29,30) & ((uint32_t)(regval) << 29)) -#define EXMC_SQPIPSRAM_ID_LENGTH_64B SINIT_IDL(0) /*!< SPI PSRAM ID length is 64 bits */ -#define EXMC_SQPIPSRAM_ID_LENGTH_32B SINIT_IDL(1) /*!< SPI PSRAM ID length is 32 bits */ -#define EXMC_SQPIPSRAM_ID_LENGTH_16B SINIT_IDL(2) /*!< SPI PSRAM ID length is 16 bits */ -#define EXMC_SQPIPSRAM_ID_LENGTH_8B SINIT_IDL(3) /*!< SPI PSRAM ID length is 8 bits */ +#define SINIT_IDL(regval) (BITS(29,30) & ((uint32_t)(regval) << 29)) +#define EXMC_SQPIPSRAM_ID_LENGTH_64B SINIT_IDL(0) /*!< SPI PSRAM ID length is 64 bits */ +#define EXMC_SQPIPSRAM_ID_LENGTH_32B SINIT_IDL(1) /*!< SPI PSRAM ID length is 32 bits */ +#define EXMC_SQPIPSRAM_ID_LENGTH_16B SINIT_IDL(2) /*!< SPI PSRAM ID length is 16 bits */ +#define EXMC_SQPIPSRAM_ID_LENGTH_8B SINIT_IDL(3) /*!< SPI PSRAM ID length is 8 bits */ /* SPI PSRAM bit number of address phase */ -#define SINIT_ADRBIT(regval) (BITS(24,28) & ((uint32_t)(regval) << 24)) -#define EXMC_SQPIPSRAM_ADDR_LENGTH_1B SINIT_ADRBIT(1) /*!< SPI PSRAM address is 1 bit */ -#define EXMC_SQPIPSRAM_ADDR_LENGTH_2B SINIT_ADRBIT(2) /*!< SPI PSRAM address is 2 bits */ -#define EXMC_SQPIPSRAM_ADDR_LENGTH_3B SINIT_ADRBIT(3) /*!< SPI PSRAM address is 3 bits */ -#define EXMC_SQPIPSRAM_ADDR_LENGTH_4B SINIT_ADRBIT(4) /*!< SPI PSRAM address is 4 bits */ -#define EXMC_SQPIPSRAM_ADDR_LENGTH_5B SINIT_ADRBIT(5) /*!< SPI PSRAM address is 5 bits */ -#define EXMC_SQPIPSRAM_ADDR_LENGTH_6B SINIT_ADRBIT(6) /*!< SPI PSRAM address is 6 bits */ -#define EXMC_SQPIPSRAM_ADDR_LENGTH_7B SINIT_ADRBIT(7) /*!< SPI PSRAM address is 7 bits */ -#define EXMC_SQPIPSRAM_ADDR_LENGTH_8B SINIT_ADRBIT(8) /*!< SPI PSRAM address is 8 bits */ -#define EXMC_SQPIPSRAM_ADDR_LENGTH_9B SINIT_ADRBIT(9) /*!< SPI PSRAM address is 9 bits */ -#define EXMC_SQPIPSRAM_ADDR_LENGTH_10B SINIT_ADRBIT(10) /*!< SPI PSRAM address is 10 bits */ -#define EXMC_SQPIPSRAM_ADDR_LENGTH_11B SINIT_ADRBIT(11) /*!< SPI PSRAM address is 11 bits */ -#define EXMC_SQPIPSRAM_ADDR_LENGTH_12B SINIT_ADRBIT(12) /*!< SPI PSRAM address is 12 bits */ -#define EXMC_SQPIPSRAM_ADDR_LENGTH_13B SINIT_ADRBIT(13) /*!< SPI PSRAM address is 13 bits */ -#define EXMC_SQPIPSRAM_ADDR_LENGTH_14B SINIT_ADRBIT(14) /*!< SPI PSRAM address is 14 bits */ -#define EXMC_SQPIPSRAM_ADDR_LENGTH_15B SINIT_ADRBIT(15) /*!< SPI PSRAM address is 15 bits */ -#define EXMC_SQPIPSRAM_ADDR_LENGTH_16B SINIT_ADRBIT(16) /*!< SPI PSRAM address is 16 bits */ -#define EXMC_SQPIPSRAM_ADDR_LENGTH_17B SINIT_ADRBIT(17) /*!< SPI PSRAM address is 17 bits */ -#define EXMC_SQPIPSRAM_ADDR_LENGTH_18B SINIT_ADRBIT(18) /*!< SPI PSRAM address is 18 bits */ -#define EXMC_SQPIPSRAM_ADDR_LENGTH_19B SINIT_ADRBIT(19) /*!< SPI PSRAM address is 19 bits */ -#define EXMC_SQPIPSRAM_ADDR_LENGTH_20B SINIT_ADRBIT(20) /*!< SPI PSRAM address is 20 bits */ -#define EXMC_SQPIPSRAM_ADDR_LENGTH_21B SINIT_ADRBIT(21) /*!< SPI PSRAM address is 21 bits */ -#define EXMC_SQPIPSRAM_ADDR_LENGTH_22B SINIT_ADRBIT(22) /*!< SPI PSRAM address is 22 bits */ -#define EXMC_SQPIPSRAM_ADDR_LENGTH_23B SINIT_ADRBIT(23) /*!< SPI PSRAM address is 23 bits */ -#define EXMC_SQPIPSRAM_ADDR_LENGTH_24B SINIT_ADRBIT(24) /*!< SPI PSRAM address is 24 bits */ -#define EXMC_SQPIPSRAM_ADDR_LENGTH_25B SINIT_ADRBIT(25) /*!< SPI PSRAM address is 25 bits */ -#define EXMC_SQPIPSRAM_ADDR_LENGTH_26B SINIT_ADRBIT(26) /*!< SPI PSRAM address is 26 bits */ +#define SINIT_ADRBIT(regval) (BITS(24,28) & ((uint32_t)(regval) << 24)) +#define EXMC_SQPIPSRAM_ADDR_LENGTH_1B SINIT_ADRBIT(1) /*!< SPI PSRAM address is 1 bit */ +#define EXMC_SQPIPSRAM_ADDR_LENGTH_2B SINIT_ADRBIT(2) /*!< SPI PSRAM address is 2 bits */ +#define EXMC_SQPIPSRAM_ADDR_LENGTH_3B SINIT_ADRBIT(3) /*!< SPI PSRAM address is 3 bits */ +#define EXMC_SQPIPSRAM_ADDR_LENGTH_4B SINIT_ADRBIT(4) /*!< SPI PSRAM address is 4 bits */ +#define EXMC_SQPIPSRAM_ADDR_LENGTH_5B SINIT_ADRBIT(5) /*!< SPI PSRAM address is 5 bits */ +#define EXMC_SQPIPSRAM_ADDR_LENGTH_6B SINIT_ADRBIT(6) /*!< SPI PSRAM address is 6 bits */ +#define EXMC_SQPIPSRAM_ADDR_LENGTH_7B SINIT_ADRBIT(7) /*!< SPI PSRAM address is 7 bits */ +#define EXMC_SQPIPSRAM_ADDR_LENGTH_8B SINIT_ADRBIT(8) /*!< SPI PSRAM address is 8 bits */ +#define EXMC_SQPIPSRAM_ADDR_LENGTH_9B SINIT_ADRBIT(9) /*!< SPI PSRAM address is 9 bits */ +#define EXMC_SQPIPSRAM_ADDR_LENGTH_10B SINIT_ADRBIT(10) /*!< SPI PSRAM address is 10 bits */ +#define EXMC_SQPIPSRAM_ADDR_LENGTH_11B SINIT_ADRBIT(11) /*!< SPI PSRAM address is 11 bits */ +#define EXMC_SQPIPSRAM_ADDR_LENGTH_12B SINIT_ADRBIT(12) /*!< SPI PSRAM address is 12 bits */ +#define EXMC_SQPIPSRAM_ADDR_LENGTH_13B SINIT_ADRBIT(13) /*!< SPI PSRAM address is 13 bits */ +#define EXMC_SQPIPSRAM_ADDR_LENGTH_14B SINIT_ADRBIT(14) /*!< SPI PSRAM address is 14 bits */ +#define EXMC_SQPIPSRAM_ADDR_LENGTH_15B SINIT_ADRBIT(15) /*!< SPI PSRAM address is 15 bits */ +#define EXMC_SQPIPSRAM_ADDR_LENGTH_16B SINIT_ADRBIT(16) /*!< SPI PSRAM address is 16 bits */ +#define EXMC_SQPIPSRAM_ADDR_LENGTH_17B SINIT_ADRBIT(17) /*!< SPI PSRAM address is 17 bits */ +#define EXMC_SQPIPSRAM_ADDR_LENGTH_18B SINIT_ADRBIT(18) /*!< SPI PSRAM address is 18 bits */ +#define EXMC_SQPIPSRAM_ADDR_LENGTH_19B SINIT_ADRBIT(19) /*!< SPI PSRAM address is 19 bits */ +#define EXMC_SQPIPSRAM_ADDR_LENGTH_20B SINIT_ADRBIT(20) /*!< SPI PSRAM address is 20 bits */ +#define EXMC_SQPIPSRAM_ADDR_LENGTH_21B SINIT_ADRBIT(21) /*!< SPI PSRAM address is 21 bits */ +#define EXMC_SQPIPSRAM_ADDR_LENGTH_22B SINIT_ADRBIT(22) /*!< SPI PSRAM address is 22 bits */ +#define EXMC_SQPIPSRAM_ADDR_LENGTH_23B SINIT_ADRBIT(23) /*!< SPI PSRAM address is 23 bits */ +#define EXMC_SQPIPSRAM_ADDR_LENGTH_24B SINIT_ADRBIT(24) /*!< SPI PSRAM address is 24 bits */ +#define EXMC_SQPIPSRAM_ADDR_LENGTH_25B SINIT_ADRBIT(25) /*!< SPI PSRAM address is 25 bits */ +#define EXMC_SQPIPSRAM_ADDR_LENGTH_26B SINIT_ADRBIT(26) /*!< SPI PSRAM address is 26 bits */ /* SPI PSRAM bit number of command phase */ -#define SINIT_CMDBIT(regval) (BITS(16,17) & ((uint32_t)(regval) << 16)) -#define EXMC_SQPIPSRAM_COMMAND_LENGTH_4B SINIT_CMDBIT(0) /*!< SPI PSRAM command is 4 bits */ -#define EXMC_SQPIPSRAM_COMMAND_LENGTH_8B SINIT_CMDBIT(1) /*!< SPI PSRAM command is 8 bits */ -#define EXMC_SQPIPSRAM_COMMAND_LENGTH_16B SINIT_CMDBIT(2) /*!< SPI PSRAM command is 16 bits */ +#define SINIT_CMDBIT(regval) (BITS(16,17) & ((uint32_t)(regval) << 16)) +#define EXMC_SQPIPSRAM_COMMAND_LENGTH_4B SINIT_CMDBIT(0) /*!< SPI PSRAM command is 4 bits */ +#define EXMC_SQPIPSRAM_COMMAND_LENGTH_8B SINIT_CMDBIT(1) /*!< SPI PSRAM command is 8 bits */ +#define EXMC_SQPIPSRAM_COMMAND_LENGTH_16B SINIT_CMDBIT(2) /*!< SPI PSRAM command is 16 bits */ /* SPI PSRAM read command mode */ -#define SRCMD_RMODE(regval) (BITS(20,21) & ((uint32_t)(regval) << 20)) -#define EXMC_SQPIPSRAM_READ_MODE_DISABLE SRCMD_RMODE(0) /*!< not SPI mode */ -#define EXMC_SQPIPSRAM_READ_MODE_SPI SRCMD_RMODE(1) /*!< SPI mode */ -#define EXMC_SQPIPSRAM_READ_MODE_SQPI SRCMD_RMODE(2) /*!< SQPI mode */ -#define EXMC_SQPIPSRAM_READ_MODE_QPI SRCMD_RMODE(3) /*!< QPI mode */ +#define SRCMD_RMODE(regval) (BITS(20,21) & ((uint32_t)(regval) << 20)) +#define EXMC_SQPIPSRAM_READ_MODE_DISABLE SRCMD_RMODE(0) /*!< not SPI mode */ +#define EXMC_SQPIPSRAM_READ_MODE_SPI SRCMD_RMODE(1) /*!< SPI mode */ +#define EXMC_SQPIPSRAM_READ_MODE_SQPI SRCMD_RMODE(2) /*!< SQPI mode */ +#define EXMC_SQPIPSRAM_READ_MODE_QPI SRCMD_RMODE(3) /*!< QPI mode */ /* SPI PSRAM write command mode */ -#define SRCMD_WMODE(regval) (BITS(20,21) & ((uint32_t)(regval) << 20)) -#define EXMC_SQPIPSRAM_WRITE_MODE_DISABLE SRCMD_WMODE(0) /*!< not SPI mode */ -#define EXMC_SQPIPSRAM_WRITE_MODE_SPI SRCMD_WMODE(1) /*!< SPI mode */ -#define EXMC_SQPIPSRAM_WRITE_MODE_SQPI SRCMD_WMODE(2) /*!< SQPI mode */ -#define EXMC_SQPIPSRAM_WRITE_MODE_QPI SRCMD_WMODE(3) /*!< QPI mode */ +#define SRCMD_WMODE(regval) (BITS(20,21) & ((uint32_t)(regval) << 20)) +#define EXMC_SQPIPSRAM_WRITE_MODE_DISABLE SRCMD_WMODE(0) /*!< not SPI mode */ +#define EXMC_SQPIPSRAM_WRITE_MODE_SPI SRCMD_WMODE(1) /*!< SPI mode */ +#define EXMC_SQPIPSRAM_WRITE_MODE_SQPI SRCMD_WMODE(2) /*!< SQPI mode */ +#define EXMC_SQPIPSRAM_WRITE_MODE_QPI SRCMD_WMODE(3) /*!< QPI mode */ /* EXMC NOR/SRAM bank region definition */ -#define EXMC_BANK0_NORSRAM_REGION0 ((uint32_t)0x00000000U) /*!< bank0 NOR/SRAM region0 */ -#define EXMC_BANK0_NORSRAM_REGION1 ((uint32_t)0x00000001U) /*!< bank0 NOR/SRAM region1 */ -#define EXMC_BANK0_NORSRAM_REGION2 ((uint32_t)0x00000002U) /*!< bank0 NOR/SRAM region2 */ -#define EXMC_BANK0_NORSRAM_REGION3 ((uint32_t)0x00000003U) /*!< bank0 NOR/SRAM region3 */ +#define EXMC_BANK0_NORSRAM_REGION0 ((uint32_t)0x00000000U) /*!< bank0 NOR/SRAM region0 */ +#define EXMC_BANK0_NORSRAM_REGION1 ((uint32_t)0x00000001U) /*!< bank0 NOR/SRAM region1 */ +#define EXMC_BANK0_NORSRAM_REGION2 ((uint32_t)0x00000002U) /*!< bank0 NOR/SRAM region2 */ +#define EXMC_BANK0_NORSRAM_REGION3 ((uint32_t)0x00000003U) /*!< bank0 NOR/SRAM region3 */ /* EXMC consecutive clock */ -#define EXMC_CLOCK_SYN_MODE ((uint32_t)0x00000000U) /*!< EXMC_CLK is generated only during synchronous access */ -#define EXMC_CLOCK_UNCONDITIONALLY ((uint32_t)0x00010000U) /*!< EXMC_CLK is generated unconditionally */ +#define EXMC_CLOCK_SYN_MODE ((uint32_t)0x00000000U) /*!< EXMC_CLK is generated only during synchronous access */ +#define EXMC_CLOCK_UNCONDITIONALLY EXMC_SNCTL_CCK /*!< EXMC_CLK is generated unconditionally */ /* EXMC NOR/SRAM write mode */ -#define EXMC_ASYN_WRITE ((uint32_t)0x00000000U) /*!< asynchronous write mode */ -#define EXMC_SYN_WRITE ((uint32_t)0x00008000U) /*!< synchronous write mode */ +#define EXMC_ASYN_WRITE ((uint32_t)0x00000000U) /*!< asynchronous write mode */ +#define EXMC_SYN_WRITE EXMC_SNCTL_SYNCWR /*!< synchronous write mode */ /* EXMC NWAIT signal configuration */ -#define EXMC_NWAIT_CONFIG_BEFORE ((uint32_t)0x00000000U) /*!< NWAIT signal is active one data cycle before wait state */ -#define EXMC_NWAIT_CONFIG_DURING ((uint32_t)0x00000800U) /*!< NWAIT signal is active during wait state */ +#define EXMC_NWAIT_CONFIG_BEFORE ((uint32_t)0x00000000U) /*!< NWAIT signal is active one data cycle before wait state */ +#define EXMC_NWAIT_CONFIG_DURING EXMC_SNCTL_NRWTCFG /*!< NWAIT signal is active during wait state */ /* EXMC NWAIT signal polarity configuration */ -#define EXMC_NWAIT_POLARITY_LOW ((uint32_t)0x00000000U) /*!< low level is active of NWAIT */ -#define EXMC_NWAIT_POLARITY_HIGH ((uint32_t)0x00000200U) /*!< high level is active of NWAIT */ +#define EXMC_NWAIT_POLARITY_LOW ((uint32_t)0x00000000U) /*!< low level is active of NWAIT */ +#define EXMC_NWAIT_POLARITY_HIGH EXMC_SNCTL_NRWTPOL /*!< high level is active of NWAIT */ /* EXMC NAND/PC card bank definition */ -#define EXMC_BANK1_NAND ((uint32_t)0x00000001U) /*!< bank1 NAND flash */ -#define EXMC_BANK2_NAND ((uint32_t)0x00000002U) /*!< bank2 NAND flash */ -#define EXMC_BANK3_PCCARD ((uint32_t)0x00000003U) /*!< bank3 PC card */ +#define EXMC_BANK1_NAND ((uint32_t)0x00000001U) /*!< NAND flash bank1 */ +#define EXMC_BANK2_NAND ((uint32_t)0x00000002U) /*!< NAND flash bank2 */ +#define EXMC_BANK3_PCCARD ((uint32_t)0x00000003U) /*!< PC card bank3 */ /* EXMC SDRAM bank definition */ -#define EXMC_SDRAM_DEVICE0 ((uint32_t)0x00000004U) /*!< SDRAM device0 */ -#define EXMC_SDRAM_DEVICE1 ((uint32_t)0x00000005U) /*!< SDRAM device1 */ +#define EXMC_SDRAM_DEVICE0 ((uint32_t)0x00000004U) /*!< SDRAM device0 */ +#define EXMC_SDRAM_DEVICE1 ((uint32_t)0x00000005U) /*!< SDRAM device1 */ /* EXMC SDRAM internal banks */ -#define EXMC_SDRAM_2_INTER_BANK ((uint32_t)0x00000000U) /*!< 2 internal banks */ -#define EXMC_SDRAM_4_INTER_BANK ((uint32_t)0x00000040U) /*!< 4 internal banks */ +#define EXMC_SDRAM_2_INTER_BANK ((uint32_t)0x00000000U) /*!< 2 internal banks */ +#define EXMC_SDRAM_4_INTER_BANK EXMC_SDCTL_NBK /*!< 4 internal banks */ /* SDRAM device0 select */ -#define EXMC_SDRAM_DEVICE0_UNSELECT ((uint32_t)0x00000000U) /*!< NAND data width 8 bits */ -#define EXMC_SDRAM_DEVICE0_SELECT ((uint32_t)0x00000010U) /*!< NAND data width 16 bits */ +#define EXMC_SDRAM_DEVICE0_UNSELECT ((uint32_t)0x00000000U) /*!< SDRAM device0 unselect */ +#define EXMC_SDRAM_DEVICE0_SELECT EXMC_SDCMD_DS0 /*!< SDRAM device0 select */ /* SDRAM device1 select */ -#define EXMC_SDRAM_DEVICE1_UNSELECT ((uint32_t)0x00000000U) /*!< NAND data width 8 bits */ -#define EXMC_SDRAM_DEVICE1_SELECT ((uint32_t)0x00000008U) /*!< NAND data width 16 bits */ +#define EXMC_SDRAM_DEVICE1_UNSELECT ((uint32_t)0x00000000U) /*!< SDRAM device1 unselect */ +#define EXMC_SDRAM_DEVICE1_SELECT EXMC_SDCMD_DS1 /*!< SDRAM device1 select */ /* SDRAM device status */ -#define EXMC_SDRAM_DEVICE_NORMAL ((uint32_t)0x00000000U) /*!< normal status */ -#define EXMC_SDRAM_DEVICE_SELF_REFRESH ((uint32_t)0x00000001U) /*!< self refresh status */ -#define EXMC_SDRAM_DEVICE_POWER_DOWN ((uint32_t)0x00000002U) /*!< power down status */ +#define EXMC_SDRAM_DEVICE_NORMAL ((uint32_t)0x00000000U) /*!< normal status */ +#define EXMC_SDRAM_DEVICE_SELF_REFRESH ((uint32_t)0x00000001U) /*!< self refresh status */ +#define EXMC_SDRAM_DEVICE_POWER_DOWN ((uint32_t)0x00000002U) /*!< power down status */ /* sample cycle of read data */ -#define EXMC_SDRAM_READSAMPLE_0_EXTRAHCLK ((uint32_t)0x00000000U) /*!< add 0 extra HCLK cycle to the read data sample clock besides the delay chain */ -#define EXMC_SDRAM_READSAMPLE_1_EXTRAHCLK ((uint32_t)0x00000002U) /*!< add 1 extra HCLK cycle to the read data sample clock besides the delay chain */ +#define EXMC_SDRAM_READSAMPLE_0_EXTRAHCLK ((uint32_t)0x00000000U) /*!< add 0 extra HCLK cycle to the read data sample clock besides the delay chain */ +#define EXMC_SDRAM_READSAMPLE_1_EXTRAHCLK EXMC_SDRSCTL_SSCR /*!< add 1 extra HCLK cycle to the read data sample clock besides the delay chain */ /* read data sample polarity */ -#define EXMC_SDRAM_SAMPLE_RISING_EDGE ((uint32_t)0x00000000U) /*!< sample data at rising edge */ -#define EXMC_SDRAM_SAMPLE_FALLING_EDGE ((uint32_t)0x80000000U) /*!< sample data at falling edge */ +#define EXMC_SQPIPSRAM_SAMPLE_RISING_EDGE ((uint32_t)0x00000000U) /*!< sample data at rising edge */ +#define EXMC_SQPIPSRAM_SAMPLE_FALLING_EDGE EXMC_SINIT_POL /*!< sample data at falling edge */ /* SQPI SRAM command flag */ -#define EXMC_SEND_COMMAND_FLAG_RDID EXMC_SRCMD_RDID /*!< EXMC_SRCMD_RDID flag bit */ -#define EXMC_SEND_COMMAND_FLAG_SC EXMC_SWCMD_SC /*!< EXMC_SWCMD_SC flag bit */ +#define EXMC_SEND_COMMAND_FLAG_RDID EXMC_SRCMD_RDID /*!< EXMC_SRCMD_RDID flag bit */ +#define EXMC_SEND_COMMAND_FLAG_SC EXMC_SWCMD_SC /*!< EXMC_SWCMD_SC flag bit */ /* EXMC flag bits */ -#define EXMC_NAND_PCCARD_FLAG_RISE EXMC_NPINTENx_INTRS /*!< interrupt rising edge status */ -#define EXMC_NAND_PCCARD_FLAG_LEVEL EXMC_NPINTENx_INTHS /*!< interrupt high-level status */ -#define EXMC_NAND_PCCARD_FLAG_FALL EXMC_NPINTENx_INTFS /*!< interrupt falling edge status */ -#define EXMC_NAND_PCCARD_FLAG_FIFOE EXMC_NPINTENx_INTEPT /*!< FIFO empty flag */ -#define EXMC_SDRAM_FLAG_REFRESH EXMC_SDSDAT_REIF /*!< refresh error interrupt flag */ -#define EXMC_SDRAM_FLAG_NREADY EXMC_SDSDAT_NRDY /*!< not ready status */ +#define EXMC_NAND_PCCARD_FLAG_RISE EXMC_NPINTEN_INTRS /*!< interrupt rising edge status */ +#define EXMC_NAND_PCCARD_FLAG_LEVEL EXMC_NPINTEN_INTHS /*!< interrupt high-level status */ +#define EXMC_NAND_PCCARD_FLAG_FALL EXMC_NPINTEN_INTFS /*!< interrupt falling edge status */ +#define EXMC_NAND_PCCARD_FLAG_FIFOE EXMC_NPINTEN_FFEPT /*!< FIFO empty flag */ +#define EXMC_SDRAM_FLAG_REFRESH EXMC_SDSDAT_REIF /*!< refresh error interrupt flag */ +#define EXMC_SDRAM_FLAG_NREADY EXMC_SDSDAT_NRDY /*!< not ready status */ /* EXMC interrupt flag bits */ -#define EXMC_NAND_PCCARD_INT_RISE EXMC_NPINTENx_INTREN /*!< interrupt rising edge detection enable */ -#define EXMC_NAND_PCCARD_INT_LEVEL EXMC_NPINTENx_INTHEN /*!< interrupt high-level detection enable */ -#define EXMC_NAND_PCCARD_INT_FALL EXMC_NPINTENx_INTFEN /*!< interrupt falling edge detection enable */ -#define EXMC_SDRAM_INT_REFRESH EXMC_SDARI_REIE /*!< interrupt refresh error enable */ +#define EXMC_NAND_PCCARD_INT_FLAG_RISE EXMC_NPINTEN_INTREN /*!< rising edge interrupt and flag */ +#define EXMC_NAND_PCCARD_INT_FLAG_LEVEL EXMC_NPINTEN_INTHEN /*!< high-level interrupt and flag */ +#define EXMC_NAND_PCCARD_INT_FLAG_FALL EXMC_NPINTEN_INTFEN /*!< falling edge interrupt and flag */ +#define EXMC_SDRAM_INT_FLAG_REFRESH EXMC_SDARI_REIE /*!< refresh error interrupt and flag */ /* function declarations */ +/* initialization functions */ +/* NOR/SRAM */ /* deinitialize EXMC NOR/SRAM region */ void exmc_norsram_deinit(uint32_t exmc_norsram_region); +/* initialize exmc_norsram_parameter_struct with the default values */ +void exmc_norsram_struct_para_init(exmc_norsram_parameter_struct* exmc_norsram_init_struct); /* initialize EXMC NOR/SRAM region */ void exmc_norsram_init(exmc_norsram_parameter_struct* exmc_norsram_init_struct); -/* exmc_norsram_parameter_struct parameter initialize */ -void exmc_norsram_parameter_init(exmc_norsram_parameter_struct* exmc_norsram_init_struct); -/* consecutive clock configure */ -void exmc_norsram_consecutive_clock_config(uint32_t clock_mode); -/* CRAM page size configure */ -void exmc_norsram_page_size_config(uint32_t page_size); -/* EXMC NOR/SRAM bank enable */ +/* enable EXMC NOR/SRAM region */ void exmc_norsram_enable(uint32_t exmc_norsram_region); -/* EXMC NOR/SRAM bank disable */ +/* disable EXMC NOR/SRAM region */ void exmc_norsram_disable(uint32_t exmc_norsram_region); - - +/* NAND */ /* deinitialize EXMC NAND bank */ void exmc_nand_deinit(uint32_t exmc_nand_bank); +/* initialize exmc_norsram_parameter_struct with the default values */ +void exmc_nand_struct_para_init(exmc_nand_parameter_struct* exmc_nand_init_struct); /* initialize EXMC NAND bank */ void exmc_nand_init(exmc_nand_parameter_struct* exmc_nand_init_struct); -/* exmc_norsram_parameter_struct parameter initialize */ -void exmc_nand_parameter_init(exmc_nand_parameter_struct* exmc_nand_init_struct); -/* EXMC NAND bank enable */ +/* enable EXMC NAND bank */ void exmc_nand_enable(uint32_t exmc_nand_bank); -/* EXMC NAND bank disable */ +/* disable EXMC NAND bank */ void exmc_nand_disable(uint32_t exmc_nand_bank); -/* enable or disable the EXMC NAND ECC function */ -void exmc_nand_ecc_config(uint32_t exmc_nand_bank, ControlStatus newvalue); -/* get the EXMC ECC value */ -uint32_t exmc_ecc_get(uint32_t exmc_nand_bank); - - +/* PC card */ /* deinitialize EXMC PC card bank */ void exmc_pccard_deinit(void); +/* initialize exmc_pccard_parameter_struct with the default values */ +void exmc_pccard_struct_para_init(exmc_pccard_parameter_struct* exmc_pccard_init_struct); /* initialize EXMC PC card bank */ void exmc_pccard_init(exmc_pccard_parameter_struct* exmc_pccard_init_struct); -/* exmc_pccard_parameter_struct parameter initialize */ -void exmc_pccard_parameter_init(exmc_pccard_parameter_struct* exmc_pccard_init_struct); -/* EXMC PC card bank enable */ +/* enable EXMC PC card bank */ void exmc_pccard_enable(void); -/* EXMC PC card bank disable */ +/* disable EXMC PC card bank */ void exmc_pccard_disable(void); - - +/* SDRAM */ /* deinitialize EXMC SDRAM device */ void exmc_sdram_deinit(uint32_t exmc_sdram_device); +/* initialize exmc_sdram_parameter_struct with the default values */ +void exmc_sdram_struct_para_init(exmc_sdram_parameter_struct* exmc_sdram_init_struct); /* initialize EXMC SDRAM device */ void exmc_sdram_init(exmc_sdram_parameter_struct* exmc_sdram_init_struct); -/* exmc_sdram_parameter_struct parameter initialize */ -void exmc_sdram_parameter_init(exmc_sdram_parameter_struct* exmc_sdram_init_struct); +/* SQPIPSRAM */ +/* deinitialize EXMC SQPIPSRAM */ +void exmc_sqpipsram_deinit(void); +/* initialize exmc_sqpipsram_parameter_struct with the default values */ +void exmc_sqpipsram_struct_para_init(exmc_sqpipsram_parameter_struct* exmc_sqpipsram_init_struct); +/* initialize EXMC SQPIPSRAM */ +void exmc_sqpipsram_init(exmc_sqpipsram_parameter_struct* exmc_sqpipsram_init_struct); + +/* function configuration */ +/* NOR/SRAM */ +/* configure consecutive clock */ +void exmc_norsram_consecutive_clock_config(uint32_t clock_mode); +/* configure CRAM page size */ +void exmc_norsram_page_size_config(uint32_t exmc_norsram_region, uint32_t page_size); +/* NAND */ +/* enable or disable the EXMC NAND ECC function */ +void exmc_nand_ecc_config(uint32_t exmc_nand_bank, ControlStatus newvalue); +/* get the EXMC ECC value */ +uint32_t exmc_ecc_get(uint32_t exmc_nand_bank); +/* SDRAM */ +/* enable or disable read sample */ +void exmc_sdram_readsample_enable(ControlStatus newvalue); +/* configure the delayed sample clock of read data */ +void exmc_sdram_readsample_config(uint32_t delay_cell, uint32_t extra_hclk); /* configure the SDRAM memory command */ void exmc_sdram_command_config(exmc_sdram_command_parameter_struct* exmc_sdram_command_init_struct); /* set auto-refresh interval */ @@ -737,18 +776,7 @@ void exmc_sdram_autorefresh_number_set(uint32_t exmc_number); void exmc_sdram_write_protection_config(uint32_t exmc_sdram_device, ControlStatus newvalue); /* get the status of SDRAM device0 or device1 */ uint32_t exmc_sdram_bankstatus_get(uint32_t exmc_sdram_device); -/* configure the delayed sample clock of read data */ -void exmc_sdram_readsample_config(uint32_t delay_cell, uint32_t extra_hclk); -/* enable or disable read sample */ -void exmc_sdram_readsample_enable(ControlStatus newvalue); - - -/* deinitialize EXMC SQPIPSRAM */ -void exmc_sqpipsram_deinit(void); -/* initialize EXMC SQPIPSRAM */ -void exmc_sqpipsram_init(exmc_sqpipsram_parameter_struct* exmc_sqpipsram_init_struct); -/* exmc_sqpipsram_parameter_struct parameter initialize */ -void exmc_sqpipsram_parameter_init(exmc_sqpipsram_parameter_struct* exmc_sqpipsram_init_struct); +/* SQPIPSRAM */ /* set the read command */ void exmc_sqpipsram_read_command_set(uint32_t read_command_mode,uint32_t read_wait_cycle,uint32_t read_command_code); /* set the write command */ @@ -764,18 +792,18 @@ uint32_t exmc_sqpipsram_high_id_get(void); /* get the bit value of EXMC send write command bit or read ID command */ FlagStatus exmc_sqpipsram_send_command_state_get(uint32_t send_command_flag); - -/* check EXMC flag is set or not */ -FlagStatus exmc_flag_get(uint32_t exmc_bank,uint32_t flag); -/* clear EXMC flag */ -void exmc_flag_clear(uint32_t exmc_bank,uint32_t flag); -/* check EXMC flag is set or not */ -FlagStatus exmc_interrupt_flag_get(uint32_t exmc_bank,uint32_t interrupt_source); -/* clear EXMC one channel flag */ -void exmc_interrupt_flag_clear(uint32_t exmc_bank,uint32_t interrupt_source); +/* interrupt & flag functions */ /* enable EXMC interrupt */ -void exmc_interrupt_enable(uint32_t exmc_bank,uint32_t interrupt_source); +void exmc_interrupt_enable(uint32_t exmc_bank,uint32_t interrupt); /* disable EXMC interrupt */ -void exmc_interrupt_disable(uint32_t exmc_bank,uint32_t interrupt_source); +void exmc_interrupt_disable(uint32_t exmc_bank,uint32_t interrupt); +/* get EXMC flag status */ +FlagStatus exmc_flag_get(uint32_t exmc_bank,uint32_t flag); +/* clear EXMC flag status */ +void exmc_flag_clear(uint32_t exmc_bank,uint32_t flag); +/* get EXMC interrupt flag */ +FlagStatus exmc_interrupt_flag_get(uint32_t exmc_bank,uint32_t interrupt); +/* clear EXMC interrupt flag */ +void exmc_interrupt_flag_clear(uint32_t exmc_bank,uint32_t interrupt); #endif /* GD32F4XX_EXMC_H */ diff --git a/bsp/gd32450z-eval/Libraries/GD32F4xx_standard_peripheral/Include/gd32f4xx_exti.h b/bsp/gd32450z-eval/Libraries/GD32F4xx_standard_peripheral/Include/gd32f4xx_exti.h index a0ad59400a..3c2a27149d 100644 --- a/bsp/gd32450z-eval/Libraries/GD32F4xx_standard_peripheral/Include/gd32f4xx_exti.h +++ b/bsp/gd32450z-eval/Libraries/GD32F4xx_standard_peripheral/Include/gd32f4xx_exti.h @@ -1,12 +1,37 @@ /*! - \file gd32f4xx_exti.h - \brief definitions for the EXTI + \file gd32f4xx_exti.h + \brief definitions for the EXTI + + \version 2016-08-15, V1.0.0, firmware for GD32F4xx + \version 2018-12-12, V2.0.1, firmware for GD32F4xx + \version 2020-09-30, V2.1.0, firmware for GD32F4xx */ /* - Copyright (C) 2016 GigaDevice + Copyright (c) 2020, GigaDevice Semiconductor Inc. + + Redistribution and use in source and binary forms, with or without modification, +are permitted provided that the following conditions are met: + + 1. Redistributions of source code must retain the above copyright notice, this + list of conditions and the following disclaimer. + 2. Redistributions in binary form must reproduce the above copyright notice, + this list of conditions and the following disclaimer in the documentation + and/or other materials provided with the distribution. + 3. Neither the name of the copyright holder nor the names of its contributors + may be used to endorse or promote products derived from this software without + specific prior written permission. - 2016-08-15, V1.0.0, firmware for GD32F4xx + THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED +WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. +IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, +INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT +NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR +PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, +WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY +OF SUCH DAMAGE. */ #ifndef GD32F4XX_EXTI_H @@ -97,6 +122,7 @@ #define EXTI_RTEN_RTEN17 BIT(17) /*!< rising edge from line 17 */ #define EXTI_RTEN_RTEN18 BIT(18) /*!< rising edge from line 18 */ #define EXTI_RTEN_RTEN19 BIT(19) /*!< rising edge from line 19 */ +#define EXTI_RTEN_RTEN20 BIT(20) /*!< rising edge from line 20 */ #define EXTI_RTEN_RTEN21 BIT(21) /*!< rising edge from line 21 */ #define EXTI_RTEN_RTEN22 BIT(22) /*!< rising edge from line 22 */ @@ -121,6 +147,7 @@ #define EXTI_FTEN_FTEN17 BIT(17) /*!< falling edge from line 17 */ #define EXTI_FTEN_FTEN18 BIT(18) /*!< falling edge from line 18 */ #define EXTI_FTEN_FTEN19 BIT(19) /*!< falling edge from line 19 */ +#define EXTI_FTEN_FTEN20 BIT(20) /*!< falling edge from line 20 */ #define EXTI_FTEN_FTEN21 BIT(21) /*!< falling edge from line 21 */ #define EXTI_FTEN_FTEN22 BIT(22) /*!< falling edge from line 22 */ @@ -145,6 +172,7 @@ #define EXTI_SWIEV_SWIEV17 BIT(17) /*!< software interrupt/event request from line 17 */ #define EXTI_SWIEV_SWIEV18 BIT(18) /*!< software interrupt/event request from line 18 */ #define EXTI_SWIEV_SWIEV19 BIT(19) /*!< software interrupt/event request from line 19 */ +#define EXTI_SWIEV_SWIEV20 BIT(20) /*!< software interrupt/event request from line 20 */ #define EXTI_SWIEV_SWIEV21 BIT(21) /*!< software interrupt/event request from line 21 */ #define EXTI_SWIEV_SWIEV22 BIT(22) /*!< software interrupt/event request from line 22 */ @@ -169,13 +197,14 @@ #define EXTI_PD_PD17 BIT(17) /*!< interrupt/event pending status from line 17 */ #define EXTI_PD_PD18 BIT(18) /*!< interrupt/event pending status from line 18 */ #define EXTI_PD_PD19 BIT(19) /*!< interrupt/event pending status from line 19 */ +#define EXTI_PD_PD20 BIT(20) /*!< interrupt/event pending status from line 20 */ #define EXTI_PD_PD21 BIT(21) /*!< interrupt/event pending status from line 21 */ #define EXTI_PD_PD22 BIT(22) /*!< interrupt/event pending status from line 22 */ /* constants definitions */ /* EXTI line number */ typedef enum -{ +{ EXTI_0 = BIT(0), /*!< EXTI line 0 */ EXTI_1 = BIT(1), /*!< EXTI line 1 */ EXTI_2 = BIT(2), /*!< EXTI line 2 */ @@ -196,7 +225,7 @@ typedef enum EXTI_17 = BIT(17), /*!< EXTI line 17 */ EXTI_18 = BIT(18), /*!< EXTI line 18 */ EXTI_19 = BIT(19), /*!< EXTI line 19 */ - EXTI_20 = BIT(20), /*!< EXTI line 20 */ + EXTI_20 = BIT(20), /*!< EXTI line 20 */ EXTI_21 = BIT(21), /*!< EXTI line 21 */ EXTI_22 = BIT(22), /*!< EXTI line 22 */ }exti_line_enum; @@ -210,10 +239,11 @@ typedef enum /* interrupt trigger mode */ typedef enum -{ +{ EXTI_TRIG_RISING = 0, /*!< EXTI rising edge trigger */ EXTI_TRIG_FALLING, /*!< EXTI falling edge trigger */ - EXTI_TRIG_BOTH /*!< EXTI rising and falling edge trigger */ + EXTI_TRIG_BOTH, /*!< EXTI rising and falling edge trigger */ + EXTI_TRIG_NONE /*!< none EXTI edge trigger */ }exti_trig_type_enum; /* function declarations */ @@ -223,13 +253,18 @@ void exti_deinit(void); void exti_init(exti_line_enum linex, exti_mode_enum mode, exti_trig_type_enum trig_type); /* enable the interrupts from EXTI line x */ void exti_interrupt_enable(exti_line_enum linex); -/* enable the events from EXTI line x */ -void exti_event_enable(exti_line_enum linex); /* disable the interrupts from EXTI line x */ void exti_interrupt_disable(exti_line_enum linex); +/* enable the events from EXTI line x */ +void exti_event_enable(exti_line_enum linex); /* disable the events from EXTI line x */ void exti_event_disable(exti_line_enum linex); +/* EXTI software interrupt event enable */ +void exti_software_interrupt_enable(exti_line_enum linex); +/* EXTI software interrupt event disable */ +void exti_software_interrupt_disable(exti_line_enum linex); +/* interrupt & flag functions */ /* get EXTI lines pending flag */ FlagStatus exti_flag_get(exti_line_enum linex); /* clear EXTI lines pending flag */ @@ -238,9 +273,5 @@ void exti_flag_clear(exti_line_enum linex); FlagStatus exti_interrupt_flag_get(exti_line_enum linex); /* clear EXTI lines pending flag */ void exti_interrupt_flag_clear(exti_line_enum linex); -/* EXTI software interrupt event enable */ -void exti_software_interrupt_enable(exti_line_enum linex); -/* EXTI software interrupt event disable */ -void exti_software_interrupt_disable(exti_line_enum linex); #endif /* GD32F4XX_EXTI_H */ diff --git a/bsp/gd32450z-eval/Libraries/GD32F4xx_standard_peripheral/Include/gd32f4xx_fmc.h b/bsp/gd32450z-eval/Libraries/GD32F4xx_standard_peripheral/Include/gd32f4xx_fmc.h index c3b360ab02..9b1b82c083 100644 --- a/bsp/gd32450z-eval/Libraries/GD32F4xx_standard_peripheral/Include/gd32f4xx_fmc.h +++ b/bsp/gd32450z-eval/Libraries/GD32F4xx_standard_peripheral/Include/gd32f4xx_fmc.h @@ -1,13 +1,40 @@ /*! - \file gd32f4xx_fmc.h - \brief definitions for the FMC + \file gd32f4xx_fmc.h + \brief definitions for the FMC + + \version 2016-08-15, V1.0.0, firmware for GD32F4xx + \version 2018-12-12, V2.0.0, firmware for GD32F4xx + \version 2020-09-30, V2.1.0, firmware for GD32F4xx */ /* - Copyright (C) 2016 GigaDevice + Copyright (c) 2020, GigaDevice Semiconductor Inc. + + Redistribution and use in source and binary forms, with or without modification, +are permitted provided that the following conditions are met: + + 1. Redistributions of source code must retain the above copyright notice, this + list of conditions and the following disclaimer. + 2. Redistributions in binary form must reproduce the above copyright notice, + this list of conditions and the following disclaimer in the documentation + and/or other materials provided with the distribution. + 3. Neither the name of the copyright holder nor the names of its contributors + may be used to endorse or promote products derived from this software without + specific prior written permission. - 2016-08-15, V1.0.0, firmware for GD32F4xx + THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED +WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. +IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, +INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT +NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR +PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, +WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY +OF SUCH DAMAGE. */ + + #ifndef GD32F4XX_FMC_H #define GD32F4XX_FMC_H @@ -18,15 +45,15 @@ #define OB OB_BASE /*!< option byte base address */ /* registers definitions */ -#define FMC_WS REG32((FMC) + 0x00U) /*!< FMC wait state register */ -#define FMC_KEY REG32((FMC) + 0x04U) /*!< FMC unlock key register */ -#define FMC_OBKEY REG32((FMC) + 0x08U) /*!< FMC option byte unlock key register */ -#define FMC_STAT REG32((FMC) + 0x0CU) /*!< FMC status register */ -#define FMC_CTL REG32((FMC) + 0x10U) /*!< FMC control register */ -#define FMC_OBCTL0 REG32((FMC) + 0x14U) /*!< FMC option byte control register 0 */ -#define FMC_OBCTL1 REG32((FMC) + 0x18U) /*!< FMC option byte control register 1 */ -#define FMC_WSEN REG32((FMC) + 0xFCU) /*!< FMC wait state enable register */ -#define FMC_PID REG32((FMC) + 0x100U) /*!< FMC product ID register */ +#define FMC_WS REG32((FMC) + 0x0000U) /*!< FMC wait state register */ +#define FMC_KEY REG32((FMC) + 0x0004U) /*!< FMC unlock key register */ +#define FMC_OBKEY REG32((FMC) + 0x0008U) /*!< FMC option byte unlock key register */ +#define FMC_STAT REG32((FMC) + 0x000CU) /*!< FMC status register */ +#define FMC_CTL REG32((FMC) + 0x0010U) /*!< FMC control register */ +#define FMC_OBCTL0 REG32((FMC) + 0x0014U) /*!< FMC option byte control register 0 */ +#define FMC_OBCTL1 REG32((FMC) + 0x0018U) /*!< FMC option byte control register 1 */ +#define FMC_WSEN REG32((FMC) + 0x00FCU) /*!< FMC wait state enable register */ +#define FMC_PID REG32((FMC) + 0x0100U) /*!< FMC product ID register */ #define OB_WP1 REG32((OB) + 0x00000008U) /*!< option byte write protection 1 */ #define OB_USER REG32((OB) + 0x00010000U) /*!< option byte user value*/ @@ -98,7 +125,6 @@ typedef enum FMC_WPERR, /*!< erase/program protection error */ FMC_OPERR, /*!< operation error */ FMC_PGERR, /*!< program error */ - FMC_TOERR /*!< timeout error */ }fmc_state_enum; /* unlock key */ @@ -108,9 +134,6 @@ typedef enum #define OB_UNLOCK_KEY0 ((uint32_t)0x08192A3BU) /*!< ob unlock key 0 */ #define OB_UNLOCK_KEY1 ((uint32_t)0x4C5D6E7FU) /*!< ob unlock key 1 */ -/* FMC time out */ -#define FMC_TIMEOUT_COUNT ((uint32_t)0x000F0000) /*!< enable FMC error timeout */ - /* option byte write protection */ #define OB_LWP ((uint32_t)0x000000FFU) /*!< write protection low bits */ #define OB_HWP ((uint32_t)0x0000FF00U) /*!< write protection high bits */ @@ -146,7 +169,7 @@ typedef enum #define OB_BB_DISABLE OBCTL0_BB(0) /*!< boot from bank0 */ #define OB_BB_ENABLE OBCTL0_BB(1) /*!< boot from bank1 or bank0 if bank1 is void */ -/* option byte software/hardware free watch dog timer */ +/* option byte software/hardware free watch dog timer */ #define OBCTL0_NWDG_HW(regval) (BIT(5) & ((uint32_t)(regval))<< 5) #define OB_FWDGT_SW OBCTL0_NWDG_HW(1) /*!< software free watchdog */ #define OB_FWDGT_HW OBCTL0_NWDG_HW(0) /*!< hardware free watchdog */ @@ -179,19 +202,19 @@ typedef enum #define OB_WP_9 ((uint32_t)0x00000200U) /*!< erase/program protection of sector 9 */ #define OB_WP_10 ((uint32_t)0x00000400U) /*!< erase/program protection of sector 10 */ #define OB_WP_11 ((uint32_t)0x00000800U) /*!< erase/program protection of sector 11 */ -#define OB_WP_12 ((uint32_t)0x00000001U) /*!< erase/program protection of sector 12 */ -#define OB_WP_13 ((uint32_t)0x00000002U) /*!< erase/program protection of sector 13 */ -#define OB_WP_14 ((uint32_t)0x00000004U) /*!< erase/program protection of sector 14 */ -#define OB_WP_15 ((uint32_t)0x00000008U) /*!< erase/program protection of sector 15 */ -#define OB_WP_16 ((uint32_t)0x00000010U) /*!< erase/program protection of sector 16 */ -#define OB_WP_17 ((uint32_t)0x00000020U) /*!< erase/program protection of sector 17 */ -#define OB_WP_18 ((uint32_t)0x00000040U) /*!< erase/program protection of sector 18 */ -#define OB_WP_19 ((uint32_t)0x00000080U) /*!< erase/program protection of sector 19 */ -#define OB_WP_20 ((uint32_t)0x00000100U) /*!< erase/program protection of sector 20 */ -#define OB_WP_21 ((uint32_t)0x00000200U) /*!< erase/program protection of sector 21 */ -#define OB_WP_22 ((uint32_t)0x00000400U) /*!< erase/program protection of sector 22 */ -#define OB_WP_23_30 ((uint32_t)0x00000800U) /*!< erase/program protection of sector 23~30 */ -#define OB_WP_ALL ((uint32_t)0x00000FFFU) /*!< erase/program protection of all sectors */ +#define OB_WP_12 ((uint32_t)0x00010000U) /*!< erase/program protection of sector 12 */ +#define OB_WP_13 ((uint32_t)0x00020000U) /*!< erase/program protection of sector 13 */ +#define OB_WP_14 ((uint32_t)0x00040000U) /*!< erase/program protection of sector 14 */ +#define OB_WP_15 ((uint32_t)0x00080000U) /*!< erase/program protection of sector 15 */ +#define OB_WP_16 ((uint32_t)0x00100000U) /*!< erase/program protection of sector 16 */ +#define OB_WP_17 ((uint32_t)0x00200000U) /*!< erase/program protection of sector 17 */ +#define OB_WP_18 ((uint32_t)0x00400000U) /*!< erase/program protection of sector 18 */ +#define OB_WP_19 ((uint32_t)0x00800000U) /*!< erase/program protection of sector 19 */ +#define OB_WP_20 ((uint32_t)0x01000000U) /*!< erase/program protection of sector 20 */ +#define OB_WP_21 ((uint32_t)0x02000000U) /*!< erase/program protection of sector 21 */ +#define OB_WP_22 ((uint32_t)0x04000000U) /*!< erase/program protection of sector 22 */ +#define OB_WP_23_27 ((uint32_t)0x08000000U) /*!< erase/program protection of sector 23~27 */ +#define OB_WP_ALL ((uint32_t)0x0FFF0FFFU) /*!< erase/program protection of all sectors */ /* option bytes D-bus read protection */ #define OB_DRP_0 ((uint32_t)0x00000001U) /*!< D-bus read protection protection of sector 0 */ @@ -206,26 +229,25 @@ typedef enum #define OB_DRP_9 ((uint32_t)0x00000200U) /*!< D-bus read protection protection of sector 9 */ #define OB_DRP_10 ((uint32_t)0x00000400U) /*!< D-bus read protection protection of sector 10 */ #define OB_DRP_11 ((uint32_t)0x00000800U) /*!< D-bus read protection protection of sector 11 */ -#define OB_DRP_12 ((uint32_t)0x00000001U) /*!< D-bus read protection protection of sector 12 */ -#define OB_DRP_13 ((uint32_t)0x00000002U) /*!< D-bus read protection protection of sector 13 */ -#define OB_DRP_14 ((uint32_t)0x00000004U) /*!< D-bus read protection protection of sector 14 */ -#define OB_DRP_15 ((uint32_t)0x00000008U) /*!< D-bus read protection protection of sector 15 */ -#define OB_DRP_16 ((uint32_t)0x00000010U) /*!< D-bus read protection protection of sector 16 */ -#define OB_DRP_17 ((uint32_t)0x00000020U) /*!< D-bus read protection protection of sector 17 */ -#define OB_DRP_18 ((uint32_t)0x00000040U) /*!< D-bus read protection protection of sector 18 */ -#define OB_DRP_19 ((uint32_t)0x00000080U) /*!< D-bus read protection protection of sector 19 */ -#define OB_DRP_20 ((uint32_t)0x00000100U) /*!< D-bus read protection protection of sector 20 */ -#define OB_DRP_21 ((uint32_t)0x00000200U) /*!< D-bus read protection protection of sector 21 */ -#define OB_DRP_22 ((uint32_t)0x00000400U) /*!< D-bus read protection protection of sector 22 */ -#define OB_DRP_23_30 ((uint32_t)0x00000800U) /*!< D-bus read protection protection of sector 23~30 */ -#define OB_DRP_ALL ((uint32_t)0x00000FFFU) /*!< D-bus read protection protection of all sectors */ +#define OB_DRP_12 ((uint32_t)0x00010000U) /*!< D-bus read protection protection of sector 12 */ +#define OB_DRP_13 ((uint32_t)0x00020000U) /*!< D-bus read protection protection of sector 13 */ +#define OB_DRP_14 ((uint32_t)0x00040000U) /*!< D-bus read protection protection of sector 14 */ +#define OB_DRP_15 ((uint32_t)0x00080000U) /*!< D-bus read protection protection of sector 15 */ +#define OB_DRP_16 ((uint32_t)0x00100000U) /*!< D-bus read protection protection of sector 16 */ +#define OB_DRP_17 ((uint32_t)0x00200000U) /*!< D-bus read protection protection of sector 17 */ +#define OB_DRP_18 ((uint32_t)0x00400000U) /*!< D-bus read protection protection of sector 18 */ +#define OB_DRP_19 ((uint32_t)0x00800000U) /*!< D-bus read protection protection of sector 19 */ +#define OB_DRP_20 ((uint32_t)0x01000000U) /*!< D-bus read protection protection of sector 20 */ +#define OB_DRP_21 ((uint32_t)0x02000000U) /*!< D-bus read protection protection of sector 21 */ +#define OB_DRP_22 ((uint32_t)0x04000000U) /*!< D-bus read protection protection of sector 22 */ +#define OB_DRP_23_27 ((uint32_t)0x08000000U) /*!< D-bus read protection protection of sector 23~27 */ -/* double banks or single bank selection when flash size is 1M bytes */ +/* double banks or single bank selection when flash size is 1M bytes */ #define OBCTL0_DBS(regval) (BIT(30) & ((uint32_t)(regval)<<30)) #define OB_DBS_DISABLE OBCTL0_DBS(0) /*!< single bank when flash size is 1M bytes */ #define OB_DBS_ENABLE OBCTL0_DBS(1) /*!< double bank when flash size is 1M bytes */ -/* option bytes D-bus read protection mode */ +/* option bytes D-bus read protection mode */ #define OBCTL0_DRP(regval) (BIT(31) & ((uint32_t)(regval)<<31)) #define OB_DRP_DISABLE OBCTL0_DRP(0) /*!< the WPx bits used as erase/program protection of each sector */ #define OB_DRP_ENABLE OBCTL0_DRP(1) /*!< the WPx bits used as erase/program protection and D-bus read protection of each sector */ @@ -260,19 +282,17 @@ typedef enum #define CTL_SECTOR_NUMBER_21 CTL_SN(25) /*!< sector 21 */ #define CTL_SECTOR_NUMBER_22 CTL_SN(26) /*!< sector 22 */ #define CTL_SECTOR_NUMBER_23 CTL_SN(27) /*!< sector 23 */ -#define CTL_SECTOR_NUMBER_28 CTL_SN(28) /*!< sector 28 */ -#define CTL_SECTOR_NUMBER_29 CTL_SN(29) /*!< sector 29 */ -#define CTL_SECTOR_NUMBER_30 CTL_SN(30) /*!< sector 30 */ -/* FMC program size */ + +/* FMC program size */ #define CTL_PSZ(regval) (BITS(8,9) & ((uint32_t)(regval))<< 8) #define CTL_PSZ_BYTE CTL_PSZ(0) /*!< FMC program by byte access */ #define CTL_PSZ_HALF_WORD CTL_PSZ(1) /*!< FMC program by half-word access */ #define CTL_PSZ_WORD CTL_PSZ(2) /*!< FMC program by word access */ /* FMC interrupt enable */ -#define FMC_INTEN_END ((uint32_t)0x01000000U) /*!< enable FMC end of program interrupt */ -#define FMC_INTEN_ERR ((uint32_t)0x02000000U) /*!< enable FMC error interrupt */ +#define FMC_INT_END ((uint32_t)0x01000000U) /*!< enable FMC end of program interrupt */ +#define FMC_INT_ERR ((uint32_t)0x02000000U) /*!< enable FMC error interrupt */ /* FMC flags */ #define FMC_FLAG_END ((uint32_t)0x00000001U) /*!< FMC end of operation flag bit */ @@ -281,7 +301,7 @@ typedef enum #define FMC_FLAG_PGMERR ((uint32_t)0x00000040U) /*!< FMC program size not match error flag bit */ #define FMC_FLAG_PGSERR ((uint32_t)0x00000080U) /*!< FMC program sequence error flag bit */ #define FMC_FLAG_RDDERR ((uint32_t)0x00000100U) /*!< FMC read D-bus protection error flag bit */ -#define FMC_FLAG_BUSY ((uint32_t)0x00010000U) /*!< FMC busy flag */ +#define FMC_FLAG_BUSY ((uint32_t)0x00010000U) /*!< FMC busy flag */ /* function declarations */ /* FMC main memory programming functions */ @@ -313,25 +333,17 @@ void ob_unlock(void); void ob_lock(void); /* send option byte change command */ void ob_start(void); +/* erase option byte */ +void ob_erase(void); /* enable write protect */ -void ob_write_protection0_enable(uint32_t ob_wp); -/* disable write protect */ -void ob_write_protection0_disable(uint32_t ob_wp); -/* enable write protect */ -void ob_write_protection1_enable(uint32_t ob_wp); +void ob_write_protection_enable(uint32_t ob_wp); /* disable write protect */ -void ob_write_protection1_disable(uint32_t ob_wp); -/* configure the erase/program protection mode */ -void ob_drp_config(uint32_t ob_drp); -/* enable the erase/program protection mode */ -void ob_drp0_enable(uint32_t ob_drp); -/* disable the erase/program protection mode */ -void ob_drp0_disable(uint32_t ob_drp); -/* enable the erase/program protection mode */ -void ob_drp1_enable(uint32_t ob_drp); -/* disable the erase/program protection mode */ -void ob_drp1_disable(uint32_t ob_drp); -/* set the option byte security protection level */ +void ob_write_protection_disable(uint32_t ob_wp); +/* enable erase/program protection and D-bus read protection */ +void ob_drp_enable(uint32_t ob_drp); +/* disable erase/program protection and D-bus read protection */ +void ob_drp_disable(uint32_t ob_drp); +/* set the option byte security protection level */ void ob_security_protection_config(uint8_t ob_spc); /* write the FMC option byte user */ void ob_user_write(uint32_t ob_fwdgt, uint32_t ob_deepsleep, uint32_t ob_stdby); @@ -366,6 +378,6 @@ void fmc_flag_clear(uint32_t fmc_flag); /* return the FMC state */ fmc_state_enum fmc_state_get(void); /* check FMC ready or not */ -fmc_state_enum fmc_ready_wait(uint32_t count); +fmc_state_enum fmc_ready_wait(void); #endif /* GD32F4XX_FMC_H */ diff --git a/bsp/gd32450z-eval/Libraries/GD32F4xx_standard_peripheral/Include/gd32f4xx_fwdgt.h b/bsp/gd32450z-eval/Libraries/GD32F4xx_standard_peripheral/Include/gd32f4xx_fwdgt.h index b63efc9293..ebee04b637 100644 --- a/bsp/gd32450z-eval/Libraries/GD32F4xx_standard_peripheral/Include/gd32f4xx_fwdgt.h +++ b/bsp/gd32450z-eval/Libraries/GD32F4xx_standard_peripheral/Include/gd32f4xx_fwdgt.h @@ -1,12 +1,37 @@ /*! - \file gd32f4xx_fwdgt.h - \brief definitions for the FWDGT + \file gd32f4xx_fwdgt.h + \brief definitions for the FWDGT + + \version 2016-08-15, V1.0.0, firmware for GD32F4xx + \version 2018-12-12, V2.0.0, firmware for GD32F4xx + \version 2020-09-30, V2.1.0, firmware for GD32F4xx */ /* - Copyright (C) 2016 GigaDevice + Copyright (c) 2020, GigaDevice Semiconductor Inc. + + Redistribution and use in source and binary forms, with or without modification, +are permitted provided that the following conditions are met: - 2016-08-15, V1.0.0, firmware for GD32F4xx + 1. Redistributions of source code must retain the above copyright notice, this + list of conditions and the following disclaimer. + 2. Redistributions in binary form must reproduce the above copyright notice, + this list of conditions and the following disclaimer in the documentation + and/or other materials provided with the distribution. + 3. Neither the name of the copyright holder nor the names of its contributors + may be used to endorse or promote products derived from this software without + specific prior written permission. + + THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED +WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. +IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, +INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT +NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR +PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, +WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY +OF SUCH DAMAGE. */ #ifndef GD32F4XX_FWDGT_H @@ -58,7 +83,13 @@ #define FWDGT_PSC_TIMEOUT ((uint32_t)0x000FFFFFU) /*!< FWDGT_PSC register write operation state flag timeout */ #define FWDGT_RLD_TIMEOUT ((uint32_t)0x000FFFFFU) /*!< FWDGT_RLD register write operation state flag timeout */ +/* FWDGT flag definitions */ +#define FWDGT_FLAG_PUD FWDGT_STAT_PUD /*!< FWDGT prescaler divider value update flag */ +#define FWDGT_FLAG_RUD FWDGT_STAT_RUD /*!< FWDGT counter reload value update flag */ + /* function declarations */ +/* enable write access to FWDGT_PSC and FWDGT_RLD */ +void fwdgt_write_enable(void); /* disable write access to FWDGT_PSC and FWDGT_RLD */ void fwdgt_write_disable(void); /* start the free watchdog timer counter */ diff --git a/bsp/gd32450z-eval/Libraries/GD32F4xx_standard_peripheral/Include/gd32f4xx_gpio.h b/bsp/gd32450z-eval/Libraries/GD32F4xx_standard_peripheral/Include/gd32f4xx_gpio.h index 257962d6de..81da899427 100644 --- a/bsp/gd32450z-eval/Libraries/GD32F4xx_standard_peripheral/Include/gd32f4xx_gpio.h +++ b/bsp/gd32450z-eval/Libraries/GD32F4xx_standard_peripheral/Include/gd32f4xx_gpio.h @@ -1,12 +1,37 @@ /*! - \file gd32f4xx_gpio.h - \brief definitions for the GPIO + \file gd32f4xx_gpio.h + \brief definitions for the GPIO + + \version 2016-08-15, V1.0.0, firmware for GD32F4xx + \version 2018-12-12, V2.0.0, firmware for GD32F4xx + \version 2020-09-30, V2.1.0, firmware for GD32F4xx */ /* - Copyright (C) 2016 GigaDevice + Copyright (c) 2020, GigaDevice Semiconductor Inc. + + Redistribution and use in source and binary forms, with or without modification, +are permitted provided that the following conditions are met: - 2016-08-15, V1.0.0, firmware for GD32F4xx + 1. Redistributions of source code must retain the above copyright notice, this + list of conditions and the following disclaimer. + 2. Redistributions in binary form must reproduce the above copyright notice, + this list of conditions and the following disclaimer in the documentation + and/or other materials provided with the distribution. + 3. Neither the name of the copyright holder nor the names of its contributors + may be used to endorse or promote products derived from this software without + specific prior written permission. + + THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED +WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. +IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, +INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT +NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR +PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, +WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY +OF SUCH DAMAGE. */ #ifndef GD32F4XX_GPIO_H @@ -41,343 +66,343 @@ /* bits definitions */ /* GPIO_CTL */ -#define GPIO_CTL_CTL0 BITS(0,1) /*!< pin 0 configuration bits */ -#define GPIO_CTL_CTL1 BITS(2,3) /*!< pin 1 configuration bits */ -#define GPIO_CTL_CTL2 BITS(4,5) /*!< pin 2 configuration bits */ -#define GPIO_CTL_CTL3 BITS(6,7) /*!< pin 3 configuration bits */ -#define GPIO_CTL_CTL4 BITS(8,9) /*!< pin 4 configuration bits */ -#define GPIO_CTL_CTL5 BITS(10,11) /*!< pin 5 configuration bits */ -#define GPIO_CTL_CTL6 BITS(12,13) /*!< pin 6 configuration bits */ -#define GPIO_CTL_CTL7 BITS(14,15) /*!< pin 7 configuration bits */ -#define GPIO_CTL_CTL8 BITS(16,17) /*!< pin 8 configuration bits */ -#define GPIO_CTL_CTL9 BITS(18,19) /*!< pin 9 configuration bits */ -#define GPIO_CTL_CTL10 BITS(20,21) /*!< pin 10 configuration bits */ -#define GPIO_CTL_CTL11 BITS(22,23) /*!< pin 11 configuration bits */ -#define GPIO_CTL_CTL12 BITS(24,25) /*!< pin 12 configuration bits */ -#define GPIO_CTL_CTL13 BITS(26,27) /*!< pin 13 configuration bits */ -#define GPIO_CTL_CTL14 BITS(28,29) /*!< pin 14 configuration bits */ -#define GPIO_CTL_CTL15 BITS(30,31) /*!< pin 15 configuration bits */ +#define GPIO_CTL_CTL0 BITS(0,1) /*!< pin 0 configuration bits */ +#define GPIO_CTL_CTL1 BITS(2,3) /*!< pin 1 configuration bits */ +#define GPIO_CTL_CTL2 BITS(4,5) /*!< pin 2 configuration bits */ +#define GPIO_CTL_CTL3 BITS(6,7) /*!< pin 3 configuration bits */ +#define GPIO_CTL_CTL4 BITS(8,9) /*!< pin 4 configuration bits */ +#define GPIO_CTL_CTL5 BITS(10,11) /*!< pin 5 configuration bits */ +#define GPIO_CTL_CTL6 BITS(12,13) /*!< pin 6 configuration bits */ +#define GPIO_CTL_CTL7 BITS(14,15) /*!< pin 7 configuration bits */ +#define GPIO_CTL_CTL8 BITS(16,17) /*!< pin 8 configuration bits */ +#define GPIO_CTL_CTL9 BITS(18,19) /*!< pin 9 configuration bits */ +#define GPIO_CTL_CTL10 BITS(20,21) /*!< pin 10 configuration bits */ +#define GPIO_CTL_CTL11 BITS(22,23) /*!< pin 11 configuration bits */ +#define GPIO_CTL_CTL12 BITS(24,25) /*!< pin 12 configuration bits */ +#define GPIO_CTL_CTL13 BITS(26,27) /*!< pin 13 configuration bits */ +#define GPIO_CTL_CTL14 BITS(28,29) /*!< pin 14 configuration bits */ +#define GPIO_CTL_CTL15 BITS(30,31) /*!< pin 15 configuration bits */ /* GPIO_OMODE */ -#define GPIO_OMODE_OM0 BIT(0) /*!< pin 0 output mode bit */ -#define GPIO_OMODE_OM1 BIT(1) /*!< pin 1 output mode bit */ -#define GPIO_OMODE_OM2 BIT(2) /*!< pin 2 output mode bit */ -#define GPIO_OMODE_OM3 BIT(3) /*!< pin 3 output mode bit */ -#define GPIO_OMODE_OM4 BIT(4) /*!< pin 4 output mode bit */ -#define GPIO_OMODE_OM5 BIT(5) /*!< pin 5 output mode bit */ -#define GPIO_OMODE_OM6 BIT(6) /*!< pin 6 output mode bit */ -#define GPIO_OMODE_OM7 BIT(7) /*!< pin 7 output mode bit */ -#define GPIO_OMODE_OM8 BIT(8) /*!< pin 8 output mode bit */ -#define GPIO_OMODE_OM9 BIT(9) /*!< pin 9 output mode bit */ -#define GPIO_OMODE_OM10 BIT(10) /*!< pin 10 output mode bit */ -#define GPIO_OMODE_OM11 BIT(11) /*!< pin 11 output mode bit */ -#define GPIO_OMODE_OM12 BIT(12) /*!< pin 12 output mode bit */ -#define GPIO_OMODE_OM13 BIT(13) /*!< pin 13 output mode bit */ -#define GPIO_OMODE_OM14 BIT(14) /*!< pin 14 output mode bit */ -#define GPIO_OMODE_OM15 BIT(15) /*!< pin 15 output mode bit */ +#define GPIO_OMODE_OM0 BIT(0) /*!< pin 0 output mode bit */ +#define GPIO_OMODE_OM1 BIT(1) /*!< pin 1 output mode bit */ +#define GPIO_OMODE_OM2 BIT(2) /*!< pin 2 output mode bit */ +#define GPIO_OMODE_OM3 BIT(3) /*!< pin 3 output mode bit */ +#define GPIO_OMODE_OM4 BIT(4) /*!< pin 4 output mode bit */ +#define GPIO_OMODE_OM5 BIT(5) /*!< pin 5 output mode bit */ +#define GPIO_OMODE_OM6 BIT(6) /*!< pin 6 output mode bit */ +#define GPIO_OMODE_OM7 BIT(7) /*!< pin 7 output mode bit */ +#define GPIO_OMODE_OM8 BIT(8) /*!< pin 8 output mode bit */ +#define GPIO_OMODE_OM9 BIT(9) /*!< pin 9 output mode bit */ +#define GPIO_OMODE_OM10 BIT(10) /*!< pin 10 output mode bit */ +#define GPIO_OMODE_OM11 BIT(11) /*!< pin 11 output mode bit */ +#define GPIO_OMODE_OM12 BIT(12) /*!< pin 12 output mode bit */ +#define GPIO_OMODE_OM13 BIT(13) /*!< pin 13 output mode bit */ +#define GPIO_OMODE_OM14 BIT(14) /*!< pin 14 output mode bit */ +#define GPIO_OMODE_OM15 BIT(15) /*!< pin 15 output mode bit */ /* GPIO_OSPD */ -#define GPIO_OSPD_OSPD0 BITS(0,1) /*!< pin 0 output max speed bits */ -#define GPIO_OSPD_OSPD1 BITS(2,3) /*!< pin 1 output max speed bits */ -#define GPIO_OSPD_OSPD2 BITS(4,5) /*!< pin 2 output max speed bits */ -#define GPIO_OSPD_OSPD3 BITS(6,7) /*!< pin 3 output max speed bits */ -#define GPIO_OSPD_OSPD4 BITS(8,9) /*!< pin 4 output max speed bits */ -#define GPIO_OSPD_OSPD5 BITS(10,11) /*!< pin 5 output max speed bits */ -#define GPIO_OSPD_OSPD6 BITS(12,13) /*!< pin 6 output max speed bits */ -#define GPIO_OSPD_OSPD7 BITS(14,15) /*!< pin 7 output max speed bits */ -#define GPIO_OSPD_OSPD8 BITS(16,17) /*!< pin 8 output max speed bits */ -#define GPIO_OSPD_OSPD9 BITS(18,19) /*!< pin 9 output max speed bits */ -#define GPIO_OSPD_OSPD10 BITS(20,21) /*!< pin 10 output max speed bits */ -#define GPIO_OSPD_OSPD11 BITS(22,23) /*!< pin 11 output max speed bits */ -#define GPIO_OSPD_OSPD12 BITS(24,25) /*!< pin 12 output max speed bits */ -#define GPIO_OSPD_OSPD13 BITS(26,27) /*!< pin 13 output max speed bits */ -#define GPIO_OSPD_OSPD14 BITS(28,29) /*!< pin 14 output max speed bits */ -#define GPIO_OSPD_OSPD15 BITS(30,31) /*!< pin 15 output max speed bits */ +#define GPIO_OSPD_OSPD0 BITS(0,1) /*!< pin 0 output max speed bits */ +#define GPIO_OSPD_OSPD1 BITS(2,3) /*!< pin 1 output max speed bits */ +#define GPIO_OSPD_OSPD2 BITS(4,5) /*!< pin 2 output max speed bits */ +#define GPIO_OSPD_OSPD3 BITS(6,7) /*!< pin 3 output max speed bits */ +#define GPIO_OSPD_OSPD4 BITS(8,9) /*!< pin 4 output max speed bits */ +#define GPIO_OSPD_OSPD5 BITS(10,11) /*!< pin 5 output max speed bits */ +#define GPIO_OSPD_OSPD6 BITS(12,13) /*!< pin 6 output max speed bits */ +#define GPIO_OSPD_OSPD7 BITS(14,15) /*!< pin 7 output max speed bits */ +#define GPIO_OSPD_OSPD8 BITS(16,17) /*!< pin 8 output max speed bits */ +#define GPIO_OSPD_OSPD9 BITS(18,19) /*!< pin 9 output max speed bits */ +#define GPIO_OSPD_OSPD10 BITS(20,21) /*!< pin 10 output max speed bits */ +#define GPIO_OSPD_OSPD11 BITS(22,23) /*!< pin 11 output max speed bits */ +#define GPIO_OSPD_OSPD12 BITS(24,25) /*!< pin 12 output max speed bits */ +#define GPIO_OSPD_OSPD13 BITS(26,27) /*!< pin 13 output max speed bits */ +#define GPIO_OSPD_OSPD14 BITS(28,29) /*!< pin 14 output max speed bits */ +#define GPIO_OSPD_OSPD15 BITS(30,31) /*!< pin 15 output max speed bits */ /* GPIO_PUD */ -#define GPIO_PUD_PUD0 BITS(0,1) /*!< pin 0 pull-up or pull-down bits */ -#define GPIO_PUD_PUD1 BITS(2,3) /*!< pin 1 pull-up or pull-down bits */ -#define GPIO_PUD_PUD2 BITS(4,5) /*!< pin 2 pull-up or pull-down bits */ -#define GPIO_PUD_PUD3 BITS(6,7) /*!< pin 3 pull-up or pull-down bits */ -#define GPIO_PUD_PUD4 BITS(8,9) /*!< pin 4 pull-up or pull-down bits */ -#define GPIO_PUD_PUD5 BITS(10,11) /*!< pin 5 pull-up or pull-down bits */ -#define GPIO_PUD_PUD6 BITS(12,13) /*!< pin 6 pull-up or pull-down bits */ -#define GPIO_PUD_PUD7 BITS(14,15) /*!< pin 7 pull-up or pull-down bits */ -#define GPIO_PUD_PUD8 BITS(16,17) /*!< pin 8 pull-up or pull-down bits */ -#define GPIO_PUD_PUD9 BITS(18,19) /*!< pin 9 pull-up or pull-down bits */ -#define GPIO_PUD_PUD10 BITS(20,21) /*!< pin 10 pull-up or pull-down bits */ -#define GPIO_PUD_PUD11 BITS(22,23) /*!< pin 11 pull-up or pull-down bits */ -#define GPIO_PUD_PUD12 BITS(24,25) /*!< pin 12 pull-up or pull-down bits */ -#define GPIO_PUD_PUD13 BITS(26,27) /*!< pin 13 pull-up or pull-down bits */ -#define GPIO_PUD_PUD14 BITS(28,29) /*!< pin 14 pull-up or pull-down bits */ -#define GPIO_PUD_PUD15 BITS(30,31) /*!< pin 15 pull-up or pull-down bits */ +#define GPIO_PUD_PUD0 BITS(0,1) /*!< pin 0 pull-up or pull-down bits */ +#define GPIO_PUD_PUD1 BITS(2,3) /*!< pin 1 pull-up or pull-down bits */ +#define GPIO_PUD_PUD2 BITS(4,5) /*!< pin 2 pull-up or pull-down bits */ +#define GPIO_PUD_PUD3 BITS(6,7) /*!< pin 3 pull-up or pull-down bits */ +#define GPIO_PUD_PUD4 BITS(8,9) /*!< pin 4 pull-up or pull-down bits */ +#define GPIO_PUD_PUD5 BITS(10,11) /*!< pin 5 pull-up or pull-down bits */ +#define GPIO_PUD_PUD6 BITS(12,13) /*!< pin 6 pull-up or pull-down bits */ +#define GPIO_PUD_PUD7 BITS(14,15) /*!< pin 7 pull-up or pull-down bits */ +#define GPIO_PUD_PUD8 BITS(16,17) /*!< pin 8 pull-up or pull-down bits */ +#define GPIO_PUD_PUD9 BITS(18,19) /*!< pin 9 pull-up or pull-down bits */ +#define GPIO_PUD_PUD10 BITS(20,21) /*!< pin 10 pull-up or pull-down bits */ +#define GPIO_PUD_PUD11 BITS(22,23) /*!< pin 11 pull-up or pull-down bits */ +#define GPIO_PUD_PUD12 BITS(24,25) /*!< pin 12 pull-up or pull-down bits */ +#define GPIO_PUD_PUD13 BITS(26,27) /*!< pin 13 pull-up or pull-down bits */ +#define GPIO_PUD_PUD14 BITS(28,29) /*!< pin 14 pull-up or pull-down bits */ +#define GPIO_PUD_PUD15 BITS(30,31) /*!< pin 15 pull-up or pull-down bits */ /* GPIO_ISTAT */ -#define GPIO_ISTAT_ISTAT0 BIT(0) /*!< pin 0 input status */ -#define GPIO_ISTAT_ISTAT1 BIT(1) /*!< pin 1 input status */ -#define GPIO_ISTAT_ISTAT2 BIT(2) /*!< pin 2 input status */ -#define GPIO_ISTAT_ISTAT3 BIT(3) /*!< pin 3 input status */ -#define GPIO_ISTAT_ISTAT4 BIT(4) /*!< pin 4 input status */ -#define GPIO_ISTAT_ISTAT5 BIT(5) /*!< pin 5 input status */ -#define GPIO_ISTAT_ISTAT6 BIT(6) /*!< pin 6 input status */ -#define GPIO_ISTAT_ISTAT7 BIT(7) /*!< pin 7 input status */ -#define GPIO_ISTAT_ISTAT8 BIT(8) /*!< pin 8 input status */ -#define GPIO_ISTAT_ISTAT9 BIT(9) /*!< pin 9 input status */ -#define GPIO_ISTAT_ISTAT10 BIT(10) /*!< pin 10 input status */ -#define GPIO_ISTAT_ISTAT11 BIT(11) /*!< pin 11 input status */ -#define GPIO_ISTAT_ISTAT12 BIT(12) /*!< pin 12 input status */ -#define GPIO_ISTAT_ISTAT13 BIT(13) /*!< pin 13 input status */ -#define GPIO_ISTAT_ISTAT14 BIT(14) /*!< pin 14 input status */ -#define GPIO_ISTAT_ISTAT15 BIT(15) /*!< pin 15 input status */ +#define GPIO_ISTAT_ISTAT0 BIT(0) /*!< pin 0 input status */ +#define GPIO_ISTAT_ISTAT1 BIT(1) /*!< pin 1 input status */ +#define GPIO_ISTAT_ISTAT2 BIT(2) /*!< pin 2 input status */ +#define GPIO_ISTAT_ISTAT3 BIT(3) /*!< pin 3 input status */ +#define GPIO_ISTAT_ISTAT4 BIT(4) /*!< pin 4 input status */ +#define GPIO_ISTAT_ISTAT5 BIT(5) /*!< pin 5 input status */ +#define GPIO_ISTAT_ISTAT6 BIT(6) /*!< pin 6 input status */ +#define GPIO_ISTAT_ISTAT7 BIT(7) /*!< pin 7 input status */ +#define GPIO_ISTAT_ISTAT8 BIT(8) /*!< pin 8 input status */ +#define GPIO_ISTAT_ISTAT9 BIT(9) /*!< pin 9 input status */ +#define GPIO_ISTAT_ISTAT10 BIT(10) /*!< pin 10 input status */ +#define GPIO_ISTAT_ISTAT11 BIT(11) /*!< pin 11 input status */ +#define GPIO_ISTAT_ISTAT12 BIT(12) /*!< pin 12 input status */ +#define GPIO_ISTAT_ISTAT13 BIT(13) /*!< pin 13 input status */ +#define GPIO_ISTAT_ISTAT14 BIT(14) /*!< pin 14 input status */ +#define GPIO_ISTAT_ISTAT15 BIT(15) /*!< pin 15 input status */ /* GPIO_OCTL */ -#define GPIO_OCTL_OCTL0 BIT(0) /*!< pin 0 output bit */ -#define GPIO_OCTL_OCTL1 BIT(1) /*!< pin 1 output bit */ -#define GPIO_OCTL_OCTL2 BIT(2) /*!< pin 2 output bit */ -#define GPIO_OCTL_OCTL3 BIT(3) /*!< pin 3 output bit */ -#define GPIO_OCTL_OCTL4 BIT(4) /*!< pin 4 output bit */ -#define GPIO_OCTL_OCTL5 BIT(5) /*!< pin 5 output bit */ -#define GPIO_OCTL_OCTL6 BIT(6) /*!< pin 6 output bit */ -#define GPIO_OCTL_OCTL7 BIT(7) /*!< pin 7 output bit */ -#define GPIO_OCTL_OCTL8 BIT(8) /*!< pin 8 output bit */ -#define GPIO_OCTL_OCTL9 BIT(9) /*!< pin 9 output bit */ -#define GPIO_OCTL_OCTL10 BIT(10) /*!< pin 10 output bit */ -#define GPIO_OCTL_OCTL11 BIT(11) /*!< pin 11 output bit */ -#define GPIO_OCTL_OCTL12 BIT(12) /*!< pin 12 output bit */ -#define GPIO_OCTL_OCTL13 BIT(13) /*!< pin 13 output bit */ -#define GPIO_OCTL_OCTL14 BIT(14) /*!< pin 14 output bit */ -#define GPIO_OCTL_OCTL15 BIT(15) /*!< pin 15 output bit */ +#define GPIO_OCTL_OCTL0 BIT(0) /*!< pin 0 output bit */ +#define GPIO_OCTL_OCTL1 BIT(1) /*!< pin 1 output bit */ +#define GPIO_OCTL_OCTL2 BIT(2) /*!< pin 2 output bit */ +#define GPIO_OCTL_OCTL3 BIT(3) /*!< pin 3 output bit */ +#define GPIO_OCTL_OCTL4 BIT(4) /*!< pin 4 output bit */ +#define GPIO_OCTL_OCTL5 BIT(5) /*!< pin 5 output bit */ +#define GPIO_OCTL_OCTL6 BIT(6) /*!< pin 6 output bit */ +#define GPIO_OCTL_OCTL7 BIT(7) /*!< pin 7 output bit */ +#define GPIO_OCTL_OCTL8 BIT(8) /*!< pin 8 output bit */ +#define GPIO_OCTL_OCTL9 BIT(9) /*!< pin 9 output bit */ +#define GPIO_OCTL_OCTL10 BIT(10) /*!< pin 10 output bit */ +#define GPIO_OCTL_OCTL11 BIT(11) /*!< pin 11 output bit */ +#define GPIO_OCTL_OCTL12 BIT(12) /*!< pin 12 output bit */ +#define GPIO_OCTL_OCTL13 BIT(13) /*!< pin 13 output bit */ +#define GPIO_OCTL_OCTL14 BIT(14) /*!< pin 14 output bit */ +#define GPIO_OCTL_OCTL15 BIT(15) /*!< pin 15 output bit */ /* GPIO_BOP */ -#define GPIO_BOP_BOP0 BIT(0) /*!< pin 0 set bit */ -#define GPIO_BOP_BOP1 BIT(1) /*!< pin 1 set bit */ -#define GPIO_BOP_BOP2 BIT(2) /*!< pin 2 set bit */ -#define GPIO_BOP_BOP3 BIT(3) /*!< pin 3 set bit */ -#define GPIO_BOP_BOP4 BIT(4) /*!< pin 4 set bit */ -#define GPIO_BOP_BOP5 BIT(5) /*!< pin 5 set bit */ -#define GPIO_BOP_BOP6 BIT(6) /*!< pin 6 set bit */ -#define GPIO_BOP_BOP7 BIT(7) /*!< pin 7 set bit */ -#define GPIO_BOP_BOP8 BIT(8) /*!< pin 8 set bit */ -#define GPIO_BOP_BOP9 BIT(9) /*!< pin 9 set bit */ -#define GPIO_BOP_BOP10 BIT(10) /*!< pin 10 set bit */ -#define GPIO_BOP_BOP11 BIT(11) /*!< pin 11 set bit */ -#define GPIO_BOP_BOP12 BIT(12) /*!< pin 12 set bit */ -#define GPIO_BOP_BOP13 BIT(13) /*!< pin 13 set bit */ -#define GPIO_BOP_BOP14 BIT(14) /*!< pin 14 set bit */ -#define GPIO_BOP_BOP15 BIT(15) /*!< pin 15 set bit */ -#define GPIO_BOP_CR0 BIT(16) /*!< pin 0 clear bit */ -#define GPIO_BOP_CR1 BIT(17) /*!< pin 1 clear bit */ -#define GPIO_BOP_CR2 BIT(18) /*!< pin 2 clear bit */ -#define GPIO_BOP_CR3 BIT(19) /*!< pin 3 clear bit */ -#define GPIO_BOP_CR4 BIT(20) /*!< pin 4 clear bit */ -#define GPIO_BOP_CR5 BIT(21) /*!< pin 5 clear bit */ -#define GPIO_BOP_CR6 BIT(22) /*!< pin 6 clear bit */ -#define GPIO_BOP_CR7 BIT(23) /*!< pin 7 clear bit */ -#define GPIO_BOP_CR8 BIT(24) /*!< pin 8 clear bit */ -#define GPIO_BOP_CR9 BIT(25) /*!< pin 9 clear bit */ -#define GPIO_BOP_CR10 BIT(26) /*!< pin 10 clear bit */ -#define GPIO_BOP_CR11 BIT(27) /*!< pin 11 clear bit */ -#define GPIO_BOP_CR12 BIT(28) /*!< pin 12 clear bit */ -#define GPIO_BOP_CR13 BIT(29) /*!< pin 13 clear bit */ -#define GPIO_BOP_CR14 BIT(30) /*!< pin 14 clear bit */ -#define GPIO_BOP_CR15 BIT(31) /*!< pin 15 clear bit */ +#define GPIO_BOP_BOP0 BIT(0) /*!< pin 0 set bit */ +#define GPIO_BOP_BOP1 BIT(1) /*!< pin 1 set bit */ +#define GPIO_BOP_BOP2 BIT(2) /*!< pin 2 set bit */ +#define GPIO_BOP_BOP3 BIT(3) /*!< pin 3 set bit */ +#define GPIO_BOP_BOP4 BIT(4) /*!< pin 4 set bit */ +#define GPIO_BOP_BOP5 BIT(5) /*!< pin 5 set bit */ +#define GPIO_BOP_BOP6 BIT(6) /*!< pin 6 set bit */ +#define GPIO_BOP_BOP7 BIT(7) /*!< pin 7 set bit */ +#define GPIO_BOP_BOP8 BIT(8) /*!< pin 8 set bit */ +#define GPIO_BOP_BOP9 BIT(9) /*!< pin 9 set bit */ +#define GPIO_BOP_BOP10 BIT(10) /*!< pin 10 set bit */ +#define GPIO_BOP_BOP11 BIT(11) /*!< pin 11 set bit */ +#define GPIO_BOP_BOP12 BIT(12) /*!< pin 12 set bit */ +#define GPIO_BOP_BOP13 BIT(13) /*!< pin 13 set bit */ +#define GPIO_BOP_BOP14 BIT(14) /*!< pin 14 set bit */ +#define GPIO_BOP_BOP15 BIT(15) /*!< pin 15 set bit */ +#define GPIO_BOP_CR0 BIT(16) /*!< pin 0 clear bit */ +#define GPIO_BOP_CR1 BIT(17) /*!< pin 1 clear bit */ +#define GPIO_BOP_CR2 BIT(18) /*!< pin 2 clear bit */ +#define GPIO_BOP_CR3 BIT(19) /*!< pin 3 clear bit */ +#define GPIO_BOP_CR4 BIT(20) /*!< pin 4 clear bit */ +#define GPIO_BOP_CR5 BIT(21) /*!< pin 5 clear bit */ +#define GPIO_BOP_CR6 BIT(22) /*!< pin 6 clear bit */ +#define GPIO_BOP_CR7 BIT(23) /*!< pin 7 clear bit */ +#define GPIO_BOP_CR8 BIT(24) /*!< pin 8 clear bit */ +#define GPIO_BOP_CR9 BIT(25) /*!< pin 9 clear bit */ +#define GPIO_BOP_CR10 BIT(26) /*!< pin 10 clear bit */ +#define GPIO_BOP_CR11 BIT(27) /*!< pin 11 clear bit */ +#define GPIO_BOP_CR12 BIT(28) /*!< pin 12 clear bit */ +#define GPIO_BOP_CR13 BIT(29) /*!< pin 13 clear bit */ +#define GPIO_BOP_CR14 BIT(30) /*!< pin 14 clear bit */ +#define GPIO_BOP_CR15 BIT(31) /*!< pin 15 clear bit */ /* GPIO_LOCK */ -#define GPIO_LOCK_LK0 BIT(0) /*!< pin 0 lock bit */ -#define GPIO_LOCK_LK1 BIT(1) /*!< pin 1 lock bit */ -#define GPIO_LOCK_LK2 BIT(2) /*!< pin 2 lock bit */ -#define GPIO_LOCK_LK3 BIT(3) /*!< pin 3 lock bit */ -#define GPIO_LOCK_LK4 BIT(4) /*!< pin 4 lock bit */ -#define GPIO_LOCK_LK5 BIT(5) /*!< pin 5 lock bit */ -#define GPIO_LOCK_LK6 BIT(6) /*!< pin 6 lock bit */ -#define GPIO_LOCK_LK7 BIT(7) /*!< pin 7 lock bit */ -#define GPIO_LOCK_LK8 BIT(8) /*!< pin 8 lock bit */ -#define GPIO_LOCK_LK9 BIT(9) /*!< pin 9 lock bit */ -#define GPIO_LOCK_LK10 BIT(10) /*!< pin 10 lock bit */ -#define GPIO_LOCK_LK11 BIT(11) /*!< pin 11 lock bit */ -#define GPIO_LOCK_LK12 BIT(12) /*!< pin 12 lock bit */ -#define GPIO_LOCK_LK13 BIT(13) /*!< pin 13 lock bit */ -#define GPIO_LOCK_LK14 BIT(14) /*!< pin 14 lock bit */ -#define GPIO_LOCK_LK15 BIT(15) /*!< pin 15 lock bit */ -#define GPIO_LOCK_LKK BIT(16) /*!< pin sequence lock key */ +#define GPIO_LOCK_LK0 BIT(0) /*!< pin 0 lock bit */ +#define GPIO_LOCK_LK1 BIT(1) /*!< pin 1 lock bit */ +#define GPIO_LOCK_LK2 BIT(2) /*!< pin 2 lock bit */ +#define GPIO_LOCK_LK3 BIT(3) /*!< pin 3 lock bit */ +#define GPIO_LOCK_LK4 BIT(4) /*!< pin 4 lock bit */ +#define GPIO_LOCK_LK5 BIT(5) /*!< pin 5 lock bit */ +#define GPIO_LOCK_LK6 BIT(6) /*!< pin 6 lock bit */ +#define GPIO_LOCK_LK7 BIT(7) /*!< pin 7 lock bit */ +#define GPIO_LOCK_LK8 BIT(8) /*!< pin 8 lock bit */ +#define GPIO_LOCK_LK9 BIT(9) /*!< pin 9 lock bit */ +#define GPIO_LOCK_LK10 BIT(10) /*!< pin 10 lock bit */ +#define GPIO_LOCK_LK11 BIT(11) /*!< pin 11 lock bit */ +#define GPIO_LOCK_LK12 BIT(12) /*!< pin 12 lock bit */ +#define GPIO_LOCK_LK13 BIT(13) /*!< pin 13 lock bit */ +#define GPIO_LOCK_LK14 BIT(14) /*!< pin 14 lock bit */ +#define GPIO_LOCK_LK15 BIT(15) /*!< pin 15 lock bit */ +#define GPIO_LOCK_LKK BIT(16) /*!< pin sequence lock key */ /* GPIO_AFSEL0 */ -#define GPIO_AFSEL0_SEL0 BITS(0,3) /*!< pin 0 alternate function selected */ -#define GPIO_AFSEL0_SEL1 BITS(4,7) /*!< pin 1 alternate function selected */ -#define GPIO_AFSEL0_SEL2 BITS(8,11) /*!< pin 2 alternate function selected */ -#define GPIO_AFSEL0_SEL3 BITS(12,15) /*!< pin 3 alternate function selected */ -#define GPIO_AFSEL0_SEL4 BITS(16,19) /*!< pin 4 alternate function selected */ -#define GPIO_AFSEL0_SEL5 BITS(20,23) /*!< pin 5 alternate function selected */ -#define GPIO_AFSEL0_SEL6 BITS(24,27) /*!< pin 6 alternate function selected */ -#define GPIO_AFSEL0_SEL7 BITS(28,31) /*!< pin 7 alternate function selected */ +#define GPIO_AFSEL0_SEL0 BITS(0,3) /*!< pin 0 alternate function selected */ +#define GPIO_AFSEL0_SEL1 BITS(4,7) /*!< pin 1 alternate function selected */ +#define GPIO_AFSEL0_SEL2 BITS(8,11) /*!< pin 2 alternate function selected */ +#define GPIO_AFSEL0_SEL3 BITS(12,15) /*!< pin 3 alternate function selected */ +#define GPIO_AFSEL0_SEL4 BITS(16,19) /*!< pin 4 alternate function selected */ +#define GPIO_AFSEL0_SEL5 BITS(20,23) /*!< pin 5 alternate function selected */ +#define GPIO_AFSEL0_SEL6 BITS(24,27) /*!< pin 6 alternate function selected */ +#define GPIO_AFSEL0_SEL7 BITS(28,31) /*!< pin 7 alternate function selected */ /* GPIO_AFSEL1 */ -#define GPIO_AFSEL1_SEL8 BITS(0,3) /*!< pin 8 alternate function selected */ -#define GPIO_AFSEL1_SEL9 BITS(4,7) /*!< pin 9 alternate function selected */ -#define GPIO_AFSEL1_SEL10 BITS(8,11) /*!< pin 10 alternate function selected */ -#define GPIO_AFSEL1_SEL11 BITS(12,15) /*!< pin 11 alternate function selected */ -#define GPIO_AFSEL1_SEL12 BITS(16,19) /*!< pin 12 alternate function selected */ -#define GPIO_AFSEL1_SEL13 BITS(20,23) /*!< pin 13 alternate function selected */ -#define GPIO_AFSEL1_SEL14 BITS(24,27) /*!< pin 14 alternate function selected */ -#define GPIO_AFSEL1_SEL15 BITS(28,31) /*!< pin 15 alternate function selected */ +#define GPIO_AFSEL1_SEL8 BITS(0,3) /*!< pin 8 alternate function selected */ +#define GPIO_AFSEL1_SEL9 BITS(4,7) /*!< pin 9 alternate function selected */ +#define GPIO_AFSEL1_SEL10 BITS(8,11) /*!< pin 10 alternate function selected */ +#define GPIO_AFSEL1_SEL11 BITS(12,15) /*!< pin 11 alternate function selected */ +#define GPIO_AFSEL1_SEL12 BITS(16,19) /*!< pin 12 alternate function selected */ +#define GPIO_AFSEL1_SEL13 BITS(20,23) /*!< pin 13 alternate function selected */ +#define GPIO_AFSEL1_SEL14 BITS(24,27) /*!< pin 14 alternate function selected */ +#define GPIO_AFSEL1_SEL15 BITS(28,31) /*!< pin 15 alternate function selected */ /* GPIO_BC */ -#define GPIO_BC_CR0 BIT(0) /*!< pin 0 clear bit */ -#define GPIO_BC_CR1 BIT(1) /*!< pin 1 clear bit */ -#define GPIO_BC_CR2 BIT(2) /*!< pin 2 clear bit */ -#define GPIO_BC_CR3 BIT(3) /*!< pin 3 clear bit */ -#define GPIO_BC_CR4 BIT(4) /*!< pin 4 clear bit */ -#define GPIO_BC_CR5 BIT(5) /*!< pin 5 clear bit */ -#define GPIO_BC_CR6 BIT(6) /*!< pin 6 clear bit */ -#define GPIO_BC_CR7 BIT(7) /*!< pin 7 clear bit */ -#define GPIO_BC_CR8 BIT(8) /*!< pin 8 clear bit */ -#define GPIO_BC_CR9 BIT(9) /*!< pin 9 clear bit */ -#define GPIO_BC_CR10 BIT(10) /*!< pin 10 clear bit */ -#define GPIO_BC_CR11 BIT(11) /*!< pin 11 clear bit */ -#define GPIO_BC_CR12 BIT(12) /*!< pin 12 clear bit */ -#define GPIO_BC_CR13 BIT(13) /*!< pin 13 clear bit */ -#define GPIO_BC_CR14 BIT(14) /*!< pin 14 clear bit */ -#define GPIO_BC_CR15 BIT(15) /*!< pin 15 clear bit */ +#define GPIO_BC_CR0 BIT(0) /*!< pin 0 clear bit */ +#define GPIO_BC_CR1 BIT(1) /*!< pin 1 clear bit */ +#define GPIO_BC_CR2 BIT(2) /*!< pin 2 clear bit */ +#define GPIO_BC_CR3 BIT(3) /*!< pin 3 clear bit */ +#define GPIO_BC_CR4 BIT(4) /*!< pin 4 clear bit */ +#define GPIO_BC_CR5 BIT(5) /*!< pin 5 clear bit */ +#define GPIO_BC_CR6 BIT(6) /*!< pin 6 clear bit */ +#define GPIO_BC_CR7 BIT(7) /*!< pin 7 clear bit */ +#define GPIO_BC_CR8 BIT(8) /*!< pin 8 clear bit */ +#define GPIO_BC_CR9 BIT(9) /*!< pin 9 clear bit */ +#define GPIO_BC_CR10 BIT(10) /*!< pin 10 clear bit */ +#define GPIO_BC_CR11 BIT(11) /*!< pin 11 clear bit */ +#define GPIO_BC_CR12 BIT(12) /*!< pin 12 clear bit */ +#define GPIO_BC_CR13 BIT(13) /*!< pin 13 clear bit */ +#define GPIO_BC_CR14 BIT(14) /*!< pin 14 clear bit */ +#define GPIO_BC_CR15 BIT(15) /*!< pin 15 clear bit */ /* GPIO_TG */ -#define GPIO_TG_TG0 BIT(0) /*!< pin 0 toggle bit */ -#define GPIO_TG_TG1 BIT(1) /*!< pin 1 toggle bit */ -#define GPIO_TG_TG2 BIT(2) /*!< pin 2 toggle bit */ -#define GPIO_TG_TG3 BIT(3) /*!< pin 3 toggle bit */ -#define GPIO_TG_TG4 BIT(4) /*!< pin 4 toggle bit */ -#define GPIO_TG_TG5 BIT(5) /*!< pin 5 toggle bit */ -#define GPIO_TG_TG6 BIT(6) /*!< pin 6 toggle bit */ -#define GPIO_TG_TG7 BIT(7) /*!< pin 7 toggle bit */ -#define GPIO_TG_TG8 BIT(8) /*!< pin 8 toggle bit */ -#define GPIO_TG_TG9 BIT(9) /*!< pin 9 toggle bit */ -#define GPIO_TG_TG10 BIT(10) /*!< pin 10 toggle bit */ -#define GPIO_TG_TG11 BIT(11) /*!< pin 11 toggle bit */ -#define GPIO_TG_TG12 BIT(12) /*!< pin 12 toggle bit */ -#define GPIO_TG_TG13 BIT(13) /*!< pin 13 toggle bit */ -#define GPIO_TG_TG14 BIT(14) /*!< pin 14 toggle bit */ -#define GPIO_TG_TG15 BIT(15) /*!< pin 15 toggle bit */ +#define GPIO_TG_TG0 BIT(0) /*!< pin 0 toggle bit */ +#define GPIO_TG_TG1 BIT(1) /*!< pin 1 toggle bit */ +#define GPIO_TG_TG2 BIT(2) /*!< pin 2 toggle bit */ +#define GPIO_TG_TG3 BIT(3) /*!< pin 3 toggle bit */ +#define GPIO_TG_TG4 BIT(4) /*!< pin 4 toggle bit */ +#define GPIO_TG_TG5 BIT(5) /*!< pin 5 toggle bit */ +#define GPIO_TG_TG6 BIT(6) /*!< pin 6 toggle bit */ +#define GPIO_TG_TG7 BIT(7) /*!< pin 7 toggle bit */ +#define GPIO_TG_TG8 BIT(8) /*!< pin 8 toggle bit */ +#define GPIO_TG_TG9 BIT(9) /*!< pin 9 toggle bit */ +#define GPIO_TG_TG10 BIT(10) /*!< pin 10 toggle bit */ +#define GPIO_TG_TG11 BIT(11) /*!< pin 11 toggle bit */ +#define GPIO_TG_TG12 BIT(12) /*!< pin 12 toggle bit */ +#define GPIO_TG_TG13 BIT(13) /*!< pin 13 toggle bit */ +#define GPIO_TG_TG14 BIT(14) /*!< pin 14 toggle bit */ +#define GPIO_TG_TG15 BIT(15) /*!< pin 15 toggle bit */ /* constants definitions */ typedef FlagStatus bit_status; /* output mode definitions */ #define CTL_CLTR(regval) (BITS(0,1) & ((uint32_t)(regval) << 0)) -#define GPIO_MODE_INPUT CTL_CLTR(0) /*!< input mode */ -#define GPIO_MODE_OUTPUT CTL_CLTR(1) /*!< output mode */ -#define GPIO_MODE_AF CTL_CLTR(2) /*!< alternate function mode */ -#define GPIO_MODE_ANALOG CTL_CLTR(3) /*!< analog mode */ +#define GPIO_MODE_INPUT CTL_CLTR(0) /*!< input mode */ +#define GPIO_MODE_OUTPUT CTL_CLTR(1) /*!< output mode */ +#define GPIO_MODE_AF CTL_CLTR(2) /*!< alternate function mode */ +#define GPIO_MODE_ANALOG CTL_CLTR(3) /*!< analog mode */ -/* pull up pull down definitions */ +/* pull-up/ pull-down definitions */ #define PUD_PUPD(regval) (BITS(0,1) & ((uint32_t)(regval) << 0)) -#define GPIO_PUPD_NONE PUD_PUPD(0) /*!< without weak pull-up and pull-down resistors */ -#define GPIO_PUPD_PULLUP PUD_PUPD(1) /*!< with weak pull-up resistor */ -#define GPIO_PUPD_PULLDOWN PUD_PUPD(2) /*!< with weak pull-down resistor */ +#define GPIO_PUPD_NONE PUD_PUPD(0) /*!< floating mode, no pull-up and pull-down resistors */ +#define GPIO_PUPD_PULLUP PUD_PUPD(1) /*!< with pull-up resistor */ +#define GPIO_PUPD_PULLDOWN PUD_PUPD(2) /*!< with pull-down resistor */ -/* gpio pin definitions */ -#define GPIO_PIN_0 BIT(0) /*!< GPIO pin 0 */ -#define GPIO_PIN_1 BIT(1) /*!< GPIO pin 1 */ -#define GPIO_PIN_2 BIT(2) /*!< GPIO pin 2 */ -#define GPIO_PIN_3 BIT(3) /*!< GPIO pin 3 */ -#define GPIO_PIN_4 BIT(4) /*!< GPIO pin 4 */ -#define GPIO_PIN_5 BIT(5) /*!< GPIO pin 5 */ -#define GPIO_PIN_6 BIT(6) /*!< GPIO pin 6 */ -#define GPIO_PIN_7 BIT(7) /*!< GPIO pin 7 */ -#define GPIO_PIN_8 BIT(8) /*!< GPIO pin 8 */ -#define GPIO_PIN_9 BIT(9) /*!< GPIO pin 9 */ -#define GPIO_PIN_10 BIT(10) /*!< GPIO pin 10 */ -#define GPIO_PIN_11 BIT(11) /*!< GPIO pin 11 */ -#define GPIO_PIN_12 BIT(12) /*!< GPIO pin 12 */ -#define GPIO_PIN_13 BIT(13) /*!< GPIO pin 13 */ -#define GPIO_PIN_14 BIT(14) /*!< GPIO pin 14 */ -#define GPIO_PIN_15 BIT(15) /*!< GPIO pin 15 */ -#define GPIO_PIN_ALL ((uint32_t)(0xFFFF)) /*!< GPIO pin all */ +/* GPIO pin definitions */ +#define GPIO_PIN_0 BIT(0) /*!< GPIO pin 0 */ +#define GPIO_PIN_1 BIT(1) /*!< GPIO pin 1 */ +#define GPIO_PIN_2 BIT(2) /*!< GPIO pin 2 */ +#define GPIO_PIN_3 BIT(3) /*!< GPIO pin 3 */ +#define GPIO_PIN_4 BIT(4) /*!< GPIO pin 4 */ +#define GPIO_PIN_5 BIT(5) /*!< GPIO pin 5 */ +#define GPIO_PIN_6 BIT(6) /*!< GPIO pin 6 */ +#define GPIO_PIN_7 BIT(7) /*!< GPIO pin 7 */ +#define GPIO_PIN_8 BIT(8) /*!< GPIO pin 8 */ +#define GPIO_PIN_9 BIT(9) /*!< GPIO pin 9 */ +#define GPIO_PIN_10 BIT(10) /*!< GPIO pin 10 */ +#define GPIO_PIN_11 BIT(11) /*!< GPIO pin 11 */ +#define GPIO_PIN_12 BIT(12) /*!< GPIO pin 12 */ +#define GPIO_PIN_13 BIT(13) /*!< GPIO pin 13 */ +#define GPIO_PIN_14 BIT(14) /*!< GPIO pin 14 */ +#define GPIO_PIN_15 BIT(15) /*!< GPIO pin 15 */ +#define GPIO_PIN_ALL BITS(0,15) /*!< GPIO pin all */ -/* gpio ctlr values */ +/* GPIO mode configuration values */ #define GPIO_MODE_SET(n, mode) ((uint32_t)((uint32_t)(mode) << (2U * (n)))) #define GPIO_MODE_MASK(n) (0x3U << (2U * (n))) -/* gpio pull up pull down values */ +/* GPIO pull-up/ pull-down values */ #define GPIO_PUPD_SET(n, pupd) ((uint32_t)((uint32_t)(pupd) << (2U * (n)))) #define GPIO_PUPD_MASK(n) (0x3U << (2U * (n))) -/* gpio output speed values */ +/* GPIO output speed values */ #define GPIO_OSPEED_SET(n, speed) ((uint32_t)((uint32_t)(speed) << (2U * (n)))) #define GPIO_OSPEED_MASK(n) (0x3U << (2U * (n))) -/* gpio output type */ -#define GPIO_OTYPE_PP ((uint8_t)(0x00)) /*!< push pull mode */ -#define GPIO_OTYPE_OD ((uint8_t)(0x01)) /*!< open drain mode */ +/* GPIO output type */ +#define GPIO_OTYPE_PP ((uint8_t)(0x00U)) /*!< push pull mode */ +#define GPIO_OTYPE_OD ((uint8_t)(0x01U)) /*!< open drain mode */ -/* gpio output max speed level */ +/* GPIO output max speed level */ #define OSPD_OSPD(regval) (BITS(0,1) & ((uint32_t)(regval) << 0)) -#define GPIO_OSPEED_LEVEL0 OSPD_OSPD(0) /*!< output max speed level 0 */ -#define GPIO_OSPEED_LEVEL1 OSPD_OSPD(1) /*!< output max speed level 1 */ -#define GPIO_OSPEED_LEVEL2 OSPD_OSPD(2) /*!< output max speed level 2 */ -#define GPIO_OSPEED_LEVEL3 OSPD_OSPD(3) /*!< output max speed level 3 */ +#define GPIO_OSPEED_LEVEL0 OSPD_OSPD(0) /*!< output max speed level 0 */ +#define GPIO_OSPEED_LEVEL1 OSPD_OSPD(1) /*!< output max speed level 1 */ +#define GPIO_OSPEED_LEVEL2 OSPD_OSPD(2) /*!< output max speed level 2 */ +#define GPIO_OSPEED_LEVEL3 OSPD_OSPD(3) /*!< output max speed level 3 */ -/* gpio output max speed value */ -#define GPIO_OSPEED_2MHZ GPIO_OSPEED_LEVEL0 /*!< output max speed 2M */ -#define GPIO_OSPEED_25MHZ GPIO_OSPEED_LEVEL1 /*!< output max speed 25M */ -#define GPIO_OSPEED_50MHZ GPIO_OSPEED_LEVEL2 /*!< output max speed 50M */ -#define GPIO_OSPEED_200MHZ GPIO_OSPEED_LEVEL3 /*!< output max speed 200M */ +/* GPIO output max speed value */ +#define GPIO_OSPEED_2MHZ GPIO_OSPEED_LEVEL0 /*!< output max speed 2MHz */ +#define GPIO_OSPEED_25MHZ GPIO_OSPEED_LEVEL1 /*!< output max speed 25MHz */ +#define GPIO_OSPEED_50MHZ GPIO_OSPEED_LEVEL2 /*!< output max speed 50MHz */ +#define GPIO_OSPEED_200MHZ GPIO_OSPEED_LEVEL3 /*!< output max speed 200MHz */ -/* gpio alternate function values */ +/* GPIO alternate function values */ #define GPIO_AFR_SET(n, af) ((uint32_t)((uint32_t)(af) << (4U * (n)))) #define GPIO_AFR_MASK(n) (0xFU << (4U * (n))) - -/* gpio alternate function */ -#define AF(regval) (BITS(0,3) & ((uint32_t)(regval) << 0)) -#define GPIO_AF_0 AF(0) /*!< alternate function selected 0 */ -#define GPIO_AF_1 AF(1) /*!< alternate function selected 1 */ -#define GPIO_AF_2 AF(2) /*!< alternate function selected 2 */ -#define GPIO_AF_3 AF(3) /*!< alternate function selected 3 */ -#define GPIO_AF_4 AF(4) /*!< alternate function selected 4 */ -#define GPIO_AF_5 AF(5) /*!< alternate function selected 5 */ -#define GPIO_AF_6 AF(6) /*!< alternate function selected 6 */ -#define GPIO_AF_7 AF(7) /*!< alternate function selected 7 */ -#define GPIO_AF_8 AF(8) /*!< alternate function selected 8 */ -#define GPIO_AF_9 AF(9) /*!< alternate function selected 9 */ -#define GPIO_AF_10 AF(10) /*!< alternate function selected 10 */ -#define GPIO_AF_11 AF(11) /*!< alternate function selected 11 */ -#define GPIO_AF_12 AF(12) /*!< alternate function selected 12 */ -#define GPIO_AF_13 AF(13) /*!< alternate function selected 13 */ -#define GPIO_AF_14 AF(14) /*!< alternate function selected 14 */ -#define GPIO_AF_15 AF(15) /*!< alternate function selected 15 */ + +/* GPIO alternate function */ +#define AF(regval) (BITS(0,3) & ((uint32_t)(regval) << 0)) +#define GPIO_AF_0 AF(0) /*!< alternate function 0 selected */ +#define GPIO_AF_1 AF(1) /*!< alternate function 1 selected */ +#define GPIO_AF_2 AF(2) /*!< alternate function 2 selected */ +#define GPIO_AF_3 AF(3) /*!< alternate function 3 selected */ +#define GPIO_AF_4 AF(4) /*!< alternate function 4 selected */ +#define GPIO_AF_5 AF(5) /*!< alternate function 5 selected */ +#define GPIO_AF_6 AF(6) /*!< alternate function 6 selected */ +#define GPIO_AF_7 AF(7) /*!< alternate function 7 selected */ +#define GPIO_AF_8 AF(8) /*!< alternate function 8 selected */ +#define GPIO_AF_9 AF(9) /*!< alternate function 9 selected */ +#define GPIO_AF_10 AF(10) /*!< alternate function 10 selected */ +#define GPIO_AF_11 AF(11) /*!< alternate function 11 selected */ +#define GPIO_AF_12 AF(12) /*!< alternate function 12 selected */ +#define GPIO_AF_13 AF(13) /*!< alternate function 13 selected */ +#define GPIO_AF_14 AF(14) /*!< alternate function 14 selected */ +#define GPIO_AF_15 AF(15) /*!< alternate function 15 selected */ /* function declarations */ -/* reset gpio port */ +/* reset GPIO port */ void gpio_deinit(uint32_t gpio_periph); -/* set gpio mode */ -void gpio_mode_set(uint32_t gpio_periph,uint32_t mode,uint32_t pull_up_down,uint32_t pin); -/* set gpio output type and speed */ -void gpio_output_options_set(uint32_t gpio_periph,uint8_t otype,uint32_t speed,uint32_t pin); +/* set GPIO mode */ +void gpio_mode_set(uint32_t gpio_periph, uint32_t mode, uint32_t pull_up_down, uint32_t pin); +/* set GPIO output type and speed */ +void gpio_output_options_set(uint32_t gpio_periph, uint8_t otype, uint32_t speed, uint32_t pin); -/* set gpio pin bit */ -void gpio_bit_set(uint32_t gpio_periph,uint32_t pin); -/* reset gpio pin bit */ -void gpio_bit_reset(uint32_t gpio_periph,uint32_t pin); -/* write data to the specified gpio pin */ -void gpio_bit_write(uint32_t gpio_periph,uint32_t pin,bit_status bit_value); -/* write data to the specified gpio port */ -void gpio_port_write(uint32_t gpio_periph,uint16_t data); +/* set GPIO pin bit */ +void gpio_bit_set(uint32_t gpio_periph, uint32_t pin); +/* reset GPIO pin bit */ +void gpio_bit_reset(uint32_t gpio_periph, uint32_t pin); +/* write data to the specified GPIO pin */ +void gpio_bit_write(uint32_t gpio_periph, uint32_t pin, bit_status bit_value); +/* write data to the specified GPIO port */ +void gpio_port_write(uint32_t gpio_periph, uint16_t data); -/* get gpio pin input status */ -FlagStatus gpio_input_bit_get(uint32_t gpio_periph,uint32_t pin); -/* get gpio port input status */ +/* get GPIO pin input status */ +FlagStatus gpio_input_bit_get(uint32_t gpio_periph, uint32_t pin); +/* get GPIO port input status */ uint16_t gpio_input_port_get(uint32_t gpio_periph); -/* get gpio pin output status */ -FlagStatus gpio_output_bit_get(uint32_t gpio_periph,uint32_t pin); -/* get gpio port output status */ +/* get GPIO pin output status */ +FlagStatus gpio_output_bit_get(uint32_t gpio_periph, uint32_t pin); +/* get GPIO port output status */ uint16_t gpio_output_port_get(uint32_t gpio_periph); -/* set gpio alternate function */ -void gpio_af_set(uint32_t gpio_periph,uint32_t alt_func_num,uint32_t pin); -/* lock gpio pin bit */ -void gpio_pin_lock(uint32_t gpio_periph,uint32_t pin); +/* set GPIO alternate function */ +void gpio_af_set(uint32_t gpio_periph, uint32_t alt_func_num, uint32_t pin); +/* lock GPIO pin bit */ +void gpio_pin_lock(uint32_t gpio_periph, uint32_t pin); -/* toggle gpio pin status */ -void gpio_bit_toggle(uint32_t gpio_periph,uint32_t pin); -/* toggle gpio port status */ +/* toggle GPIO pin status */ +void gpio_bit_toggle(uint32_t gpio_periph, uint32_t pin); +/* toggle GPIO port status */ void gpio_port_toggle(uint32_t gpio_periph); #endif /* GD32F4XX_GPIO_H */ diff --git a/bsp/gd32450z-eval/Libraries/GD32F4xx_standard_peripheral/Include/gd32f4xx_i2c.h b/bsp/gd32450z-eval/Libraries/GD32F4xx_standard_peripheral/Include/gd32f4xx_i2c.h index f7e93d3357..121e42f497 100644 --- a/bsp/gd32450z-eval/Libraries/GD32F4xx_standard_peripheral/Include/gd32f4xx_i2c.h +++ b/bsp/gd32450z-eval/Libraries/GD32F4xx_standard_peripheral/Include/gd32f4xx_i2c.h @@ -1,29 +1,56 @@ /*! - \file gd32f4xx_i2c.h - \brief definitions for the I2C + \file gd32f4xx_i2c.h + \brief definitions for the I2C + + \version 2016-08-15, V1.0.0, firmware for GD32F4xx + \version 2018-12-12, V2.0.0, firmware for GD32F4xx + \version 2019-04-16, V2.0.1, firmware for GD32F4xx + \version 2020-09-30, V2.1.0, firmware for GD32F4xx */ /* - Copyright (C) 2016 GigaDevice + Copyright (c) 2020, GigaDevice Semiconductor Inc. + + Redistribution and use in source and binary forms, with or without modification, +are permitted provided that the following conditions are met: + + 1. Redistributions of source code must retain the above copyright notice, this + list of conditions and the following disclaimer. + 2. Redistributions in binary form must reproduce the above copyright notice, + this list of conditions and the following disclaimer in the documentation + and/or other materials provided with the distribution. + 3. Neither the name of the copyright holder nor the names of its contributors + may be used to endorse or promote products derived from this software without + specific prior written permission. - 2016-08-15, V1.0.0, firmware for GD32F4xx + THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED +WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. +IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, +INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT +NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR +PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, +WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY +OF SUCH DAMAGE. */ + #ifndef GD32F4XX_I2C_H #define GD32F4XX_I2C_H #include "gd32f4xx.h" /* I2Cx(x=0,1,2) definitions */ -#define I2C0 I2C_BASE -#define I2C1 (I2C_BASE+0x400U) -#define I2C2 (I2C_BASE+0x800U) +#define I2C0 I2C_BASE /*!< I2C0 base address */ +#define I2C1 (I2C_BASE+0x400U) /*!< I2C1 base address */ +#define I2C2 (I2C_BASE+0x800U) /*!< I2C2 base address */ /* registers definitions */ #define I2C_CTL0(i2cx) REG32((i2cx) + 0x00U) /*!< I2C control register 0 */ #define I2C_CTL1(i2cx) REG32((i2cx) + 0x04U) /*!< I2C control register 1 */ -#define I2C_SADDR0(i2cx) REG32((i2cx) + 0x08U) /*!< I2C slave address register 0*/ -#define I2C_SADDR1(i2cx) REG32((i2cx) + 0x0CU) /*!< I2C slave address register */ +#define I2C_SADDR0(i2cx) REG32((i2cx) + 0x08U) /*!< I2C slave address register 0 */ +#define I2C_SADDR1(i2cx) REG32((i2cx) + 0x0CU) /*!< I2C slave address register 1 */ #define I2C_DATA(i2cx) REG32((i2cx) + 0x10U) /*!< I2C transfer buffer register */ #define I2C_STAT0(i2cx) REG32((i2cx) + 0x14U) /*!< I2C transfer status register 0 */ #define I2C_STAT1(i2cx) REG32((i2cx) + 0x18U) /*!< I2C transfer status register */ @@ -32,7 +59,6 @@ #define I2C_FCTL(i2cx) REG32((i2cx) + 0x24U) /*!< I2C filter control register */ #define I2C_SAMCS(i2cx) REG32((i2cx) + 0x80U) /*!< I2C SAM control and status register */ - /* bits definitions */ /* I2Cx_CTL0 */ #define I2C_CTL0_I2CEN BIT(0) /*!< peripheral enable */ @@ -41,7 +67,7 @@ #define I2C_CTL0_ARPEN BIT(4) /*!< ARP enable */ #define I2C_CTL0_PECEN BIT(5) /*!< PEC enable */ #define I2C_CTL0_GCEN BIT(6) /*!< general call enable */ -#define I2C_CTL0_DISSTRC BIT(7) /*!< clock stretching disable (slave mode) */ +#define I2C_CTL0_SS BIT(7) /*!< clock stretching disable (slave mode) */ #define I2C_CTL0_START BIT(8) /*!< start generation */ #define I2C_CTL0_STOP BIT(9) /*!< stop generation */ #define I2C_CTL0_ACKEN BIT(10) /*!< acknowledge enable */ @@ -52,7 +78,7 @@ /* I2Cx_CTL1 */ #define I2C_CTL1_I2CCLK BITS(0,5) /*!< I2CCLK[5:0] bits (peripheral clock frequency) */ -#define I2C_CTL1_ERRIE BIT(8) /*!< error interrupt inable */ +#define I2C_CTL1_ERRIE BIT(8) /*!< error interrupt enable */ #define I2C_CTL1_EVIE BIT(9) /*!< event interrupt enable */ #define I2C_CTL1_BUFIE BIT(10) /*!< buffer interrupt enable */ #define I2C_CTL1_DMAON BIT(11) /*!< DMA requests enable */ @@ -90,12 +116,12 @@ /* I2Cx_STAT1 */ #define I2C_STAT1_MASTER BIT(0) /*!< master/slave */ #define I2C_STAT1_I2CBSY BIT(1) /*!< bus busy */ -#define I2C_STAT1_TRS BIT(2) /*!< transmitter/receiver */ +#define I2C_STAT1_TR BIT(2) /*!< transmitter/receiver */ #define I2C_STAT1_RXGC BIT(4) /*!< general call address (slave mode) */ #define I2C_STAT1_DEFSMB BIT(5) /*!< SMBus device default address (slave mode) */ #define I2C_STAT1_HSTSMB BIT(6) /*!< SMBus host header (slave mode) */ #define I2C_STAT1_DUMODF BIT(7) /*!< dual flag (slave mode) */ -#define I2C_STAT1_ECV BITS(8,15) /*!< packet error checking register */ +#define I2C_STAT1_PECV BITS(8,15) /*!< packet error checking value */ /* I2Cx_CKCFG */ #define I2C_CKCFG_CLKC BITS(0,11) /*!< clock control register in fast/standard mode (master mode) */ @@ -123,7 +149,6 @@ #define I2C_SAMCS_RFF BIT(14) /*!< rxframe fall flag, cleared by software write 0 */ #define I2C_SAMCS_RFR BIT(15) /*!< rxframe rise flag, cleared by software write 0 */ - /* constants definitions */ /* the digital noise filter can filter spikes's length */ @@ -146,6 +171,94 @@ typedef enum { I2C_DF_15PCLKS /*!< enable digital noise filter and the maximum filtered spiker's length 15 PCLK1 */ }i2c_digital_filter_enum; +/* constants definitions */ +/* define the I2C bit position and its register index offset */ +#define I2C_REGIDX_BIT(regidx, bitpos) (((uint32_t)(regidx) << 6) | (uint32_t)(bitpos)) +#define I2C_REG_VAL(i2cx, offset) (REG32((i2cx) + (((uint32_t)(offset) & 0xFFFFU) >> 6))) +#define I2C_BIT_POS(val) ((uint32_t)(val) & 0x1FU) +#define I2C_REGIDX_BIT2(regidx, bitpos, regidx2, bitpos2) (((uint32_t)(regidx2) << 22) | (uint32_t)((bitpos2) << 16)\ + | (((uint32_t)(regidx) << 6) | (uint32_t)(bitpos))) +#define I2C_REG_VAL2(i2cx, offset) (REG32((i2cx) + ((uint32_t)(offset) >> 22))) +#define I2C_BIT_POS2(val) (((uint32_t)(val) & 0x1F0000U) >> 16) + +/* register offset */ +#define I2C_CTL1_REG_OFFSET 0x04U /*!< CTL1 register offset */ +#define I2C_STAT0_REG_OFFSET 0x14U /*!< STAT0 register offset */ +#define I2C_STAT1_REG_OFFSET 0x18U /*!< STAT1 register offset */ +#define I2C_SAMCS_REG_OFFSET 0x80U /*!< SAMCS register offset */ + +/* I2C flags */ +typedef enum +{ + /* flags in STAT0 register */ + I2C_FLAG_SBSEND = I2C_REGIDX_BIT(I2C_STAT0_REG_OFFSET, 0U), /*!< start condition sent out in master mode */ + I2C_FLAG_ADDSEND = I2C_REGIDX_BIT(I2C_STAT0_REG_OFFSET, 1U), /*!< address is sent in master mode or received and matches in slave mode */ + I2C_FLAG_BTC = I2C_REGIDX_BIT(I2C_STAT0_REG_OFFSET, 2U), /*!< byte transmission finishes */ + I2C_FLAG_ADD10SEND = I2C_REGIDX_BIT(I2C_STAT0_REG_OFFSET, 3U), /*!< header of 10-bit address is sent in master mode */ + I2C_FLAG_STPDET = I2C_REGIDX_BIT(I2C_STAT0_REG_OFFSET, 4U), /*!< stop condition detected in slave mode */ + I2C_FLAG_RBNE = I2C_REGIDX_BIT(I2C_STAT0_REG_OFFSET, 6U), /*!< I2C_DATA is not Empty during receiving */ + I2C_FLAG_TBE = I2C_REGIDX_BIT(I2C_STAT0_REG_OFFSET, 7U), /*!< I2C_DATA is empty during transmitting */ + I2C_FLAG_BERR = I2C_REGIDX_BIT(I2C_STAT0_REG_OFFSET, 8U), /*!< a bus error occurs indication a unexpected start or stop condition on I2C bus */ + I2C_FLAG_LOSTARB = I2C_REGIDX_BIT(I2C_STAT0_REG_OFFSET, 9U), /*!< arbitration lost in master mode */ + I2C_FLAG_AERR = I2C_REGIDX_BIT(I2C_STAT0_REG_OFFSET, 10U), /*!< acknowledge error */ + I2C_FLAG_OUERR = I2C_REGIDX_BIT(I2C_STAT0_REG_OFFSET, 11U), /*!< over-run or under-run situation occurs in slave mode */ + I2C_FLAG_PECERR = I2C_REGIDX_BIT(I2C_STAT0_REG_OFFSET, 12U), /*!< PEC error when receiving data */ + I2C_FLAG_SMBTO = I2C_REGIDX_BIT(I2C_STAT0_REG_OFFSET, 14U), /*!< timeout signal in SMBus mode */ + I2C_FLAG_SMBALT = I2C_REGIDX_BIT(I2C_STAT0_REG_OFFSET, 15U), /*!< SMBus alert status */ + /* flags in STAT1 register */ + I2C_FLAG_MASTER = I2C_REGIDX_BIT(I2C_STAT1_REG_OFFSET, 0U), /*!< a flag indicating whether I2C block is in master or slave mode */ + I2C_FLAG_I2CBSY = I2C_REGIDX_BIT(I2C_STAT1_REG_OFFSET, 1U), /*!< busy flag */ + I2C_FLAG_TRS = I2C_REGIDX_BIT(I2C_STAT1_REG_OFFSET, 2U), /*!< whether the I2C is a transmitter or a receiver */ + I2C_FLAG_RXGC = I2C_REGIDX_BIT(I2C_STAT1_REG_OFFSET, 4U), /*!< general call address (00h) received */ + I2C_FLAG_DEFSMB = I2C_REGIDX_BIT(I2C_STAT1_REG_OFFSET, 5U), /*!< default address of SMBus device */ + I2C_FLAG_HSTSMB = I2C_REGIDX_BIT(I2C_STAT1_REG_OFFSET, 6U), /*!< SMBus host header detected in slave mode */ + I2C_FLAG_DUMOD = I2C_REGIDX_BIT(I2C_STAT1_REG_OFFSET, 7U), /*!< dual flag in slave mode indicating which address is matched in dual-address mode */ + /* flags in SAMCS register */ + I2C_FLAG_TFF = I2C_REGIDX_BIT(I2C_SAMCS_REG_OFFSET, 12U), /*!< txframe fall flag */ + I2C_FLAG_TFR = I2C_REGIDX_BIT(I2C_SAMCS_REG_OFFSET, 13U), /*!< txframe rise flag */ + I2C_FLAG_RFF = I2C_REGIDX_BIT(I2C_SAMCS_REG_OFFSET, 14U), /*!< rxframe fall flag */ + I2C_FLAG_RFR = I2C_REGIDX_BIT(I2C_SAMCS_REG_OFFSET, 15U) /*!< rxframe rise flag */ +}i2c_flag_enum; + +/* I2C interrupt flags */ +typedef enum +{ + /* interrupt flags in CTL1 register */ + I2C_INT_FLAG_SBSEND = I2C_REGIDX_BIT2(I2C_CTL1_REG_OFFSET, 9U, I2C_STAT0_REG_OFFSET, 0U), /*!< start condition sent out in master mode interrupt flag */ + I2C_INT_FLAG_ADDSEND = I2C_REGIDX_BIT2(I2C_CTL1_REG_OFFSET, 9U, I2C_STAT0_REG_OFFSET, 1U), /*!< address is sent in master mode or received and matches in slave mode interrupt flag */ + I2C_INT_FLAG_BTC = I2C_REGIDX_BIT2(I2C_CTL1_REG_OFFSET, 9U, I2C_STAT0_REG_OFFSET, 2U), /*!< byte transmission finishes */ + I2C_INT_FLAG_ADD10SEND = I2C_REGIDX_BIT2(I2C_CTL1_REG_OFFSET, 9U, I2C_STAT0_REG_OFFSET, 3U), /*!< header of 10-bit address is sent in master mode interrupt flag */ + I2C_INT_FLAG_STPDET = I2C_REGIDX_BIT2(I2C_CTL1_REG_OFFSET, 9U, I2C_STAT0_REG_OFFSET, 4U), /*!< stop condition detected in slave mode interrupt flag */ + I2C_INT_FLAG_RBNE = I2C_REGIDX_BIT2(I2C_CTL1_REG_OFFSET, 9U, I2C_STAT0_REG_OFFSET, 6U), /*!< I2C_DATA is not Empty during receiving interrupt flag */ + I2C_INT_FLAG_TBE = I2C_REGIDX_BIT2(I2C_CTL1_REG_OFFSET, 9U, I2C_STAT0_REG_OFFSET, 7U), /*!< I2C_DATA is empty during transmitting interrupt flag */ + I2C_INT_FLAG_BERR = I2C_REGIDX_BIT2(I2C_CTL1_REG_OFFSET, 8U, I2C_STAT0_REG_OFFSET, 8U), /*!< a bus error occurs indication a unexpected start or stop condition on I2C bus interrupt flag */ + I2C_INT_FLAG_LOSTARB = I2C_REGIDX_BIT2(I2C_CTL1_REG_OFFSET, 8U, I2C_STAT0_REG_OFFSET, 9U), /*!< arbitration lost in master mode interrupt flag */ + I2C_INT_FLAG_AERR = I2C_REGIDX_BIT2(I2C_CTL1_REG_OFFSET, 8U, I2C_STAT0_REG_OFFSET, 10U), /*!< acknowledge error interrupt flag */ + I2C_INT_FLAG_OUERR = I2C_REGIDX_BIT2(I2C_CTL1_REG_OFFSET, 8U, I2C_STAT0_REG_OFFSET, 11U), /*!< over-run or under-run situation occurs in slave mode interrupt flag */ + I2C_INT_FLAG_PECERR = I2C_REGIDX_BIT2(I2C_CTL1_REG_OFFSET, 8U, I2C_STAT0_REG_OFFSET, 12U), /*!< PEC error when receiving data interrupt flag */ + I2C_INT_FLAG_SMBTO = I2C_REGIDX_BIT2(I2C_CTL1_REG_OFFSET, 8U, I2C_STAT0_REG_OFFSET, 14U), /*!< timeout signal in SMBus mode interrupt flag */ + I2C_INT_FLAG_SMBALT = I2C_REGIDX_BIT2(I2C_CTL1_REG_OFFSET, 8U, I2C_STAT0_REG_OFFSET, 15U), /*!< SMBus Alert status interrupt flag */ + /* interrupt flags in SAMCS register */ + I2C_INT_FLAG_TFF = I2C_REGIDX_BIT2(I2C_SAMCS_REG_OFFSET, 4U, I2C_SAMCS_REG_OFFSET, 12U), /*!< txframe fall interrupt flag */ + I2C_INT_FLAG_TFR = I2C_REGIDX_BIT2(I2C_SAMCS_REG_OFFSET, 5U, I2C_SAMCS_REG_OFFSET, 13U), /*!< txframe rise interrupt flag */ + I2C_INT_FLAG_RFF = I2C_REGIDX_BIT2(I2C_SAMCS_REG_OFFSET, 6U, I2C_SAMCS_REG_OFFSET, 14U), /*!< rxframe fall interrupt flag */ + I2C_INT_FLAG_RFR = I2C_REGIDX_BIT2(I2C_SAMCS_REG_OFFSET, 7U, I2C_SAMCS_REG_OFFSET, 15U) /*!< rxframe rise interrupt flag */ +}i2c_interrupt_flag_enum; + +/* I2C interrupt enable or disable */ +typedef enum +{ + /* interrupt in CTL1 register */ + I2C_INT_ERR = I2C_REGIDX_BIT(I2C_CTL1_REG_OFFSET, 8U), /*!< error interrupt enable */ + I2C_INT_EV = I2C_REGIDX_BIT(I2C_CTL1_REG_OFFSET, 9U), /*!< event interrupt enable */ + I2C_INT_BUF = I2C_REGIDX_BIT(I2C_CTL1_REG_OFFSET, 10U), /*!< buffer interrupt enable */ + /* interrupt in SAMCS register */ + I2C_INT_TFF = I2C_REGIDX_BIT(I2C_SAMCS_REG_OFFSET, 4U), /*!< txframe fall interrupt enable */ + I2C_INT_TFR = I2C_REGIDX_BIT(I2C_SAMCS_REG_OFFSET, 5U), /*!< txframe rise interrupt enable */ + I2C_INT_RFF = I2C_REGIDX_BIT(I2C_SAMCS_REG_OFFSET, 6U), /*!< rxframe fall interrupt enable */ + I2C_INT_RFR = I2C_REGIDX_BIT(I2C_SAMCS_REG_OFFSET, 7U) /*!< rxframe rise interrupt enable */ +}i2c_interrupt_enum; + /* SMBus/I2C mode switch and SMBus type selection */ #define I2C_I2CMODE_ENABLE ((uint32_t)0x00000000U) /*!< I2C mode */ #define I2C_SMBUSMODE_ENABLE I2C_CTL0_SMBEN /*!< SMBus mode */ @@ -153,27 +266,28 @@ typedef enum { /* SMBus/I2C mode switch and SMBus type selection */ #define I2C_SMBUS_DEVICE ((uint32_t)0x00000000U) /*!< SMBus mode device type */ #define I2C_SMBUS_HOST I2C_CTL0_SMBSEL /*!< SMBus mode host type */ + /* I2C transfer direction */ -#define I2C_TRANSMITTER (~BIT(0)) /*!< transmitter */ -#define I2C_RECEIVER BIT(0) /*!< receiver */ +#define I2C_RECEIVER ((uint32_t)0x00000001U) /*!< receiver */ +#define I2C_TRANSMITTER ((uint32_t)0xFFFFFFFEU) /*!< transmitter */ /* whether or not to send an ACK */ -#define I2C_ACK_ENABLE ((uint8_t)0x01U) /*!< ACK will be sent */ -#define I2C_ACK_DISABLE ((uint8_t)0x00U) /*!< ACK will be not sent */ +#define I2C_ACK_DISABLE ((uint32_t)0x00000000U) /*!< ACK will be not sent */ +#define I2C_ACK_ENABLE ((uint32_t)0x00000001U) /*!< ACK will be sent */ /* I2C POAP position*/ -#define I2C_ACKPOS_CURRENT ((uint8_t)0x01U) /*!< ACKEN bit decides whether to send ACK or not for the current */ -#define I2C_ACKPOS_NEXT ((uint8_t)0x00U) /*!< ACKEN bit decides whether to send ACK or not for the next byte */ +#define I2C_ACKPOS_NEXT ((uint32_t)0x00000000U) /*!< ACKEN bit decides whether or not to send ACK for the next byte */ +#define I2C_ACKPOS_CURRENT ((uint32_t)0x00000001U) /*!< ACKEN bit decides whether or not to send ACK or not for the current byte */ /* I2C dual-address mode switch */ -#define I2C_DUADEN_DISABLE ((uint8_t)0x00U) /*!< dual-address mode disabled */ -#define I2C_DUADEN_ENABLE ((uint8_t)0x01U) /*!< dual-address mode enabled */ +#define I2C_DUADEN_DISABLE ((uint32_t)0x00000000U) /*!< dual-address mode disabled */ +#define I2C_DUADEN_ENABLE ((uint32_t)0x00000001U) /*!< dual-address mode enabled */ /* whether or not to stretch SCL low */ #define I2C_SCLSTRETCH_ENABLE ((uint32_t)0x00000000U) /*!< SCL stretching is enabled */ -#define I2C_SCLSTRETCH_DISABLE I2C_CTL0_DISSTRC /*!< SCL stretching is disabled */ +#define I2C_SCLSTRETCH_DISABLE I2C_CTL0_SS /*!< SCL stretching is disabled */ -/* whether or not to response to a General Call */ +/* whether or not to response to a general call */ #define I2C_GCEN_ENABLE I2C_CTL0_GCEN /*!< slave will response to a general call */ #define I2C_GCEN_DISABLE ((uint32_t)0x00000000U) /*!< slave will not response to a general call */ @@ -185,11 +299,11 @@ typedef enum { /* DMA mode switch */ #define I2C_DMA_ON I2C_CTL1_DMAON /*!< DMA mode enabled */ #define I2C_DMA_OFF ((uint32_t)0x00000000U) /*!< DMA mode disabled */ + /* flag indicating DMA last transfer */ #define I2C_DMALST_ON I2C_CTL1_DMALST /*!< next DMA EOT is the last transfer */ #define I2C_DMALST_OFF ((uint32_t)0x00000000U) /*!< next DMA EOT is not the last transfer */ - /* I2C PEC configure */ /* PEC enable */ #define I2C_PEC_ENABLE I2C_CTL0_PECEN /*!< PEC calculation on */ @@ -203,105 +317,78 @@ typedef enum { /* issue or not alert through SMBA pin */ #define I2C_SALTSEND_ENABLE I2C_CTL0_SALT /*!< issue alert through SMBA pin */ #define I2C_SALTSEND_DISABLE ((uint32_t)0x00000000U) /*!< not issue alert through SMBA */ + /* ARP protocol in SMBus switch */ #define I2C_ARP_ENABLE I2C_CTL0_ARPEN /*!< ARP is enabled */ #define I2C_ARP_DISABLE ((uint32_t)0x00000000U) /*!< ARP is disabled */ -/* I2C state */ -/* I2C bit state */ -#define I2C_SBSEND BIT(0) /*!< start condition sent out in master mode */ -#define I2C_ADDSEND BIT(1) /*!< address is sent in master mode or received and matches in slave mode */ -#define I2C_BTC BIT(2) /*!< byte transmission finishes */ -#define I2C_ADD10SEND BIT(3) /*!< header of 10-bit address is sent in master mode */ -#define I2C_STPDET BIT(4) /*!< etop condition detected in slave mode */ -#define I2C_RBNE BIT(6) /*!< I2C_DATA is not Empty during receiving */ -#define I2C_TBE BIT(7) /*!< I2C_DATA is empty during transmitting */ -#define I2C_BERR BIT(8) /*!< a bus error occurs indication a unexpected start or stop condition on I2C bus */ -#define I2C_LOSTARB BIT(9) /*!< arbitration lost in master mode */ -#define I2C_AERR BIT(10) /*!< acknowledge error */ -#define I2C_OUERR BIT(11) /*!< over-run or under-run situation occurs in slave mode */ -#define I2C_PECERR BIT(12) /*!< PEC error when receiving data */ -#define I2C_SMBTO BIT(14) /*!< timeout signal in SMBus mode */ -#define I2C_SMBALT BIT(15) /*!< SMBus alert status */ -#define I2C_MASTER (BIT(0)|BIT(31)) /*!< a flag indicating whether I2C block is in master or slave mode */ -#define I2C_I2CBSY (BIT(1)|BIT(31)) /*!< busy flag */ -#define I2C_TRS (BIT(2)|BIT(31)) /*!< whether the I2C is a transmitter or a receiver */ -#define I2C_RXGC (BIT(4)|BIT(31)) /*!< general call address (00h) received */ -#define I2C_DEFSMB (BIT(5)|BIT(31)) /*!< default address of SMBus device */ -#define I2C_HSTSMB (BIT(6)|BIT(31)) /*!< SMBus host header detected in slave mode */ -#define I2C_DUMODF (BIT(7)|BIT(31)) /*!< dual flag in slave mode indicating which address is matched in dual-address mode */ +/* transmit I2C data */ +#define DATA_TRANS(regval) (BITS(0,7) & ((uint32_t)(regval) << 0)) + +/* receive I2C data */ +#define DATA_RECV(regval) GET_BITS((uint32_t)(regval), 0, 7) /* I2C duty cycle in fast mode */ -#define CKCFG_DTCY(regval) (BIT(14) & ((uint32_t)(regval) << 14)) -#define I2C_DTCY_2 CKCFG_DTCY(0) /*!< I2C fast mode Tlow/Thigh = 2 */ -#define I2C_DTCY_16_9 CKCFG_DTCY(1) /*!< I2C fast mode Tlow/Thigh = 16/9 */ +#define I2C_DTCY_2 ((uint32_t)0x00000000U) /*!< I2C fast mode Tlow/Thigh = 2 */ +#define I2C_DTCY_16_9 I2C_CKCFG_DTCY /*!< I2C fast mode Tlow/Thigh = 16/9 */ /* address mode for the I2C slave */ -#define SADDR0_ADDFORMAT(regval) (BIT(15) & ((regval) << 15)) -#define I2C_ADDFORMAT_7BITS SADDR0_ADDFORMAT(0) /*!< address:7 bits */ -#define I2C_ADDFORMAT_10BITS SADDR0_ADDFORMAT(1) /*!< address:10 bits */ +#define I2C_ADDFORMAT_7BITS ((uint32_t)0x00000000U) /*!< address:7 bits */ +#define I2C_ADDFORMAT_10BITS I2C_SADDR0_ADDFORMAT /*!< address:10 bits */ /* function declarations */ /* reset I2C */ void i2c_deinit(uint32_t i2c_periph); -/* I2C clock configure */ -void i2c_clock_config(uint32_t i2c_periph,uint32_t clkspeed,uint32_t dutycyc); -/* I2C address configure */ -void i2c_mode_addr_config(uint32_t i2c_periph,uint32_t i2cmod,uint32_t addformat,uint32_t addr); +/* configure I2C clock */ +void i2c_clock_config(uint32_t i2c_periph, uint32_t clkspeed, uint32_t dutycyc); +/* configure I2C address */ +void i2c_mode_addr_config(uint32_t i2c_periph, uint32_t mode, uint32_t addformat, uint32_t addr); /* SMBus type selection */ -void i2c_smbus_type_config(uint32_t i2c_periph,uint32_t type); +void i2c_smbus_type_config(uint32_t i2c_periph, uint32_t type); /* whether or not to send an ACK */ -void i2c_ack_config(uint32_t i2c_periph,uint8_t ack); -/* I2C POAP position configure */ -void i2c_ackpos_config(uint32_t i2c_periph,uint8_t pos); -/* master send slave address */ -void i2c_master_addressing(uint32_t i2c_periph,uint8_t addr,uint32_t trandirection); -/* dual-address mode switch */ -void i2c_dualaddr_enable(uint32_t i2c_periph, uint8_t dualaddr); - -/* enable i2c */ +void i2c_ack_config(uint32_t i2c_periph, uint32_t ack); +/* configure I2C POAP position */ +void i2c_ackpos_config(uint32_t i2c_periph, uint32_t pos); +/* master sends slave address */ +void i2c_master_addressing(uint32_t i2c_periph, uint32_t addr, uint32_t trandirection); +/* enable dual-address mode */ +void i2c_dualaddr_enable(uint32_t i2c_periph, uint32_t addr); +/* disable dual-address mode */ +void i2c_dualaddr_disable(uint32_t i2c_periph); +/* enable I2C */ void i2c_enable(uint32_t i2c_periph); -/* disable i2c */ +/* disable I2C */ void i2c_disable(uint32_t i2c_periph); + /* generate a START condition on I2C bus */ void i2c_start_on_bus(uint32_t i2c_periph); /* generate a STOP condition on I2C bus */ void i2c_stop_on_bus(uint32_t i2c_periph); -/* i2c transmit data function */ -void i2c_transmit_data(uint32_t i2c_periph,uint8_t data); -/* i2c receive data function */ -uint8_t i2c_receive_data(uint32_t i2c_periph); -/* I2C DMA mode enable */ -void i2c_dma_enable(uint32_t i2c_periph,uint32_t dmastste); -/* flag indicating DMA last transfer */ -void i2c_dma_last_transfer_enable(uint32_t i2c_periph,uint32_t dmalast); -/* whether to stretch SCL low when data is not ready in slave mode */ -void i2c_stretch_scl_low_config(uint32_t i2c_periph,uint32_t stretchpara ); -/* whether or not to response to a general call */ -void i2c_slave_response_to_gcall_config(uint32_t i2c_periph,uint32_t gcallpara); -/* software reset I2C */ +/* I2C transmit data function */ +void i2c_data_transmit(uint32_t i2c_periph, uint8_t data); +/* I2C receive data function */ +uint8_t i2c_data_receive(uint32_t i2c_periph); +/* enable I2C DMA mode */ +void i2c_dma_enable(uint32_t i2c_periph, uint32_t dmastate); +/* configure whether next DMA EOT is DMA last transfer or not */ +void i2c_dma_last_transfer_config(uint32_t i2c_periph, uint32_t dmalast); +/* whether to stretch SCL low when data is not ready in slave mode */ +void i2c_stretch_scl_low_config(uint32_t i2c_periph, uint32_t stretchpara); +/* whether or not to response to a general call */ +void i2c_slave_response_to_gcall_config(uint32_t i2c_periph, uint32_t gcallpara); +/* software reset I2C */ void i2c_software_reset_config(uint32_t i2c_periph, uint32_t sreset); -/* check i2c state */ -FlagStatus i2c_flag_get(uint32_t i2c_periph,uint32_t state); -/* clear i2c state */ -void i2c_flag_clear(uint32_t i2c_periph,uint32_t state); -/* enable i2c interrupt */ -void i2c_interrupt_enable(uint32_t i2c_periph,uint32_t inttype); -/* disable i2c interrupt */ -void i2c_interrupt_disable(uint32_t i2c_periph,uint32_t inttype); - /* I2C PEC calculation on or off */ -void i2c_pec_enable(uint32_t i2c_periph,uint32_t pecstate); +void i2c_pec_enable(uint32_t i2c_periph, uint32_t pecstate); /* I2C whether to transfer PEC value */ -void i2c_pec_transfer_enable(uint32_t i2c_periph,uint32_t pecpara); -/* packet error checking value */ -uint8_t i2c_pec_value(uint32_t i2c_periph); - +void i2c_pec_transfer_enable(uint32_t i2c_periph, uint32_t pecpara); +/* packet error checking value */ +uint8_t i2c_pec_value_get(uint32_t i2c_periph); /* I2C issue alert through SMBA pin */ -void i2c_smbus_alert_issue(uint32_t i2c_periph,uint32_t smbuspara); -/* I2C ARP protocol in SMBus switch */ -void i2c_smbus_arp_enable(uint32_t i2c_periph,uint32_t arpstate); +void i2c_smbus_issue_alert(uint32_t i2c_periph, uint32_t smbuspara); +/* I2C ARP protocol in SMBus switch */ +void i2c_smbus_arp_enable(uint32_t i2c_periph, uint32_t arpstate); /* I2C analog noise filter disable */ void i2c_analog_noise_filter_disable(uint32_t i2c_periph); @@ -318,14 +405,18 @@ void i2c_sam_disable(uint32_t i2c_periph); void i2c_sam_timeout_enable(uint32_t i2c_periph); /* disable SAM_V interface timeout detect */ void i2c_sam_timeout_disable(uint32_t i2c_periph); -/* enable the specified I2C SAM interrupt */ -void i2c_sam_interrupt_enable(uint32_t i2c_periph,uint32_t inttype); -/* disable the specified I2C SAM interrupt */ -void i2c_sam_interrupt_disable(uint32_t i2c_periph,uint32_t inttype); -/* check i2c SAM state */ -FlagStatus i2c_sam_flag_get(uint32_t i2c_periph,uint32_t samstate); -/* clear i2c SAM state */ -void i2c_sam_flag_clear(uint32_t i2c_periph,uint32_t samstate); +/* check I2C flag is set or not */ +FlagStatus i2c_flag_get(uint32_t i2c_periph, i2c_flag_enum flag); +/* clear I2C flag */ +void i2c_flag_clear(uint32_t i2c_periph, i2c_flag_enum flag); +/* enable I2C interrupt */ +void i2c_interrupt_enable(uint32_t i2c_periph, i2c_interrupt_enum interrupt); +/* disable I2C interrupt */ +void i2c_interrupt_disable(uint32_t i2c_periph, i2c_interrupt_enum interrupt); +/* check I2C interrupt flag */ +FlagStatus i2c_interrupt_flag_get(uint32_t i2c_periph, i2c_interrupt_flag_enum int_flag); +/* clear I2C interrupt flag */ +void i2c_interrupt_flag_clear(uint32_t i2c_periph, i2c_interrupt_flag_enum int_flag); #endif /* GD32F4XX_I2C_H */ diff --git a/bsp/gd32450z-eval/Libraries/GD32F4xx_standard_peripheral/Include/gd32f4xx_ipa.h b/bsp/gd32450z-eval/Libraries/GD32F4xx_standard_peripheral/Include/gd32f4xx_ipa.h index d356ac8c3d..d9ae8ce33a 100644 --- a/bsp/gd32450z-eval/Libraries/GD32F4xx_standard_peripheral/Include/gd32f4xx_ipa.h +++ b/bsp/gd32450z-eval/Libraries/GD32F4xx_standard_peripheral/Include/gd32f4xx_ipa.h @@ -1,12 +1,37 @@ /*! - \file gd32f4xx_ipa.h - \brief definitions for the IPA + \file gd32f4xx_ipa.h + \brief definitions for the IPA + + \version 2016-08-15, V1.0.0, firmware for GD32F4xx + \version 2018-12-12, V2.0.0, firmware for GD32F4xx + \version 2020-09-30, V2.1.0, firmware for GD32F4xx */ /* - Copyright (C) 2016 GigaDevice + Copyright (c) 2020, GigaDevice Semiconductor Inc. + + Redistribution and use in source and binary forms, with or without modification, +are permitted provided that the following conditions are met: - 2016-08-15, V1.0.0, firmware for GD32F4xx + 1. Redistributions of source code must retain the above copyright notice, this + list of conditions and the following disclaimer. + 2. Redistributions in binary form must reproduce the above copyright notice, + this list of conditions and the following disclaimer in the documentation + and/or other materials provided with the distribution. + 3. Neither the name of the copyright holder nor the names of its contributors + may be used to endorse or promote products derived from this software without + specific prior written permission. + + THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED +WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. +IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, +INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT +NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR +PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, +WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY +OF SUCH DAMAGE. */ #ifndef GD32F4XX_IPA_H @@ -24,7 +49,7 @@ #define IPA_INTC REG32(IPA + 0x08U) /*!< IPA interrupt flag clear register */ #define IPA_FMADDR REG32(IPA + 0x0CU) /*!< IPA foreground memory base address register */ #define IPA_FLOFF REG32(IPA + 0x10U) /*!< IPA foreground line offset register */ -#define IPA_BMADDR REG32(IPA + 0x14U) /*!< IPA background memory base address register */ +#define IPA_BMADDR REG32(IPA + 0x14U) /*!< IPA background memory base address register */ #define IPA_BLOFF REG32(IPA + 0x18U) /*!< IPA background line offset register */ #define IPA_FPCTL REG32(IPA + 0x1CU) /*!< IPA foreground pixel control register */ #define IPA_FPV REG32(IPA + 0x20U) /*!< IPA foreground pixel value register */ @@ -33,11 +58,11 @@ #define IPA_FLMADDR REG32(IPA + 0x2CU) /*!< IPA foreground LUT memory base address register */ #define IPA_BLMADDR REG32(IPA + 0x30U) /*!< IPA background LUT memory base address register */ #define IPA_DPCTL REG32(IPA + 0x34U) /*!< IPA destination pixel control register */ -#define IPA_DPV REG32(IPA + 0x38U) /*!< IPA destination pixel value register */ +#define IPA_DPV REG32(IPA + 0x38U) /*!< IPA destination pixel value register */ #define IPA_DMADDR REG32(IPA + 0x3CU) /*!< IPA destination memory base address register */ #define IPA_DLOFF REG32(IPA + 0x40U) /*!< IPA destination line offset register */ #define IPA_IMS REG32(IPA + 0x44U) /*!< IPA image size register */ -#define IPA_LM REG32(IPA + 0x48U) /*!< IPA line mark register */ +#define IPA_LM REG32(IPA + 0x48U) /*!< IPA line mark register */ #define IPA_ITCTL REG32(IPA + 0x4CU) /*!< IPA inter-timer control register */ /* IPA_CTL */ @@ -113,7 +138,7 @@ #define IPA_BLMADDR_BLMADDR BITS(0,31) /*!< background LUT memory base address */ /* IPA_DPCTL */ -#define IPA_DPCTL_DPF BITS(0,2) /*!< destination pixel control register */ +#define IPA_DPCTL_DPF BITS(0,2) /*!< destination pixel control register */ /* IPA_DPV */ /* destination pixel format ARGB8888 */ @@ -165,7 +190,7 @@ /* constants definitions */ /* IPA foreground parameter struct definitions */ typedef struct -{ +{ uint32_t foreground_memaddr; /*!< foreground memory base address */ uint32_t foreground_lineoff; /*!< foreground line offset */ uint32_t foreground_prealpha; /*!< foreground pre-defined alpha value */ @@ -174,25 +199,25 @@ typedef struct uint32_t foreground_prered; /*!< foreground pre-defined red value */ uint32_t foreground_pregreen; /*!< foreground pre-defined green value */ uint32_t foreground_preblue; /*!< foreground pre-defined blue value */ -}ipa_foreground_parameter_struct; +}ipa_foreground_parameter_struct; /* IPA background parameter struct definitions */ typedef struct -{ +{ uint32_t background_memaddr; /*!< background memory base address */ uint32_t background_lineoff; /*!< background line offset */ uint32_t background_prealpha; /*!< background pre-defined alpha value */ - uint32_t background_alpha_algorithm; /*!< background alpha value calculation algorithm */ + uint32_t background_alpha_algorithm; /*!< background alpha value calculation algorithm */ uint32_t background_pf; /*!< background pixel format */ uint32_t background_prered; /*!< background pre-defined red value */ uint32_t background_pregreen; /*!< background pre-defined green value */ uint32_t background_preblue; /*!< background pre-defined blue value */ -}ipa_background_parameter_struct; +}ipa_background_parameter_struct; /* IPA destination parameter struct definitions */ typedef struct { - uint32_t destination_memaddr; /*!< destination memory base address */ + uint32_t destination_memaddr; /*!< destination memory base address */ uint32_t destination_lineoff; /*!< destination line offset */ uint32_t destination_prealpha; /*!< destination pre-defined alpha value */ uint32_t destination_pf; /*!< destination pixel format */ @@ -200,17 +225,17 @@ typedef struct uint32_t destination_pregreen; /*!< destination pre-defined green value */ uint32_t destination_preblue; /*!< destination pre-defined blue value */ uint32_t image_width; /*!< width of the image to be processed */ - uint32_t image_height; /*!< height of the image to be processed */ -}ipa_destination_parameter_struct; + uint32_t image_height; /*!< height of the image to be processed */ +}ipa_destination_parameter_struct; /* destination pixel format */ -typedef enum +typedef enum { - IPA_DPF_ARGB8888, /*!< destination pixel format ARGB8888 */ - IPA_DPF_RGB888, /*!< destination pixel format RGB888 */ - IPA_DPF_RGB565, /*!< destination pixel format RGB565 */ - IPA_DPF_ARGB1555, /*!< destination pixel format ARGB1555 */ - IPA_DPF_ARGB4444 /*!< destination pixel format ARGB4444 */ + IPA_DPF_ARGB8888, /*!< destination pixel format ARGB8888 */ + IPA_DPF_RGB888, /*!< destination pixel format RGB888 */ + IPA_DPF_RGB565, /*!< destination pixel format RGB565 */ + IPA_DPF_ARGB1555, /*!< destination pixel format ARGB1555 */ + IPA_DPF_ARGB4444 /*!< destination pixel format ARGB4444 */ } ipa_dpf_enum; /* LUT pixel format */ @@ -218,30 +243,30 @@ typedef enum #define IPA_LUT_PF_RGB888 ((uint8_t)0x01U) /*!< LUT pixel format RGB888 */ /* Inter-timer */ -#define IPA_INTER_TIMER_DISABLE ((uint8_t)0x00U) /*!< Inter-timer disable */ -#define IPA_INTER_TIMER_ENABLE ((uint8_t)0x01U) /*!< Inter-timer enable */ +#define IPA_INTER_TIMER_DISABLE ((uint8_t)0x00U) /*!< inter-timer disable */ +#define IPA_INTER_TIMER_ENABLE ((uint8_t)0x01U) /*!< inter-timer enable */ /* IPA pixel format convert mode */ -#define CTL_PFCM(regval) (BITS(16,17) & ((regval) << 16)) +#define CTL_PFCM(regval) (BITS(16,17) & ((uint32_t)(regval) << 16)) #define IPA_FGTODE CTL_PFCM(0) /*!< foreground memory to destination memory without pixel format convert */ #define IPA_FGTODE_PF_CONVERT CTL_PFCM(1) /*!< foreground memory to destination memory with pixel format convert */ #define IPA_FGBGTODE CTL_PFCM(2) /*!< blending foreground and background memory to destination memory */ #define IPA_FILL_UP_DE CTL_PFCM(3) /*!< fill up destination memory with specific color */ /* foreground alpha value calculation algorithm */ -#define FPCTL_FAVCA(regval) (BITS(16,17) & ((regval) << 16)) +#define FPCTL_FAVCA(regval) (BITS(16,17) & ((uint32_t)(regval) << 16)) #define IPA_FG_ALPHA_MODE_0 FPCTL_FAVCA(0) /*!< no effect */ #define IPA_FG_ALPHA_MODE_1 FPCTL_FAVCA(1) /*!< FPDAV[7:0] is selected as the foreground alpha value */ #define IPA_FG_ALPHA_MODE_2 FPCTL_FAVCA(2) /*!< FPDAV[7:0] multiplied by read alpha value */ /* background alpha value calculation algorithm */ -#define BPCTL_BAVCA(regval) (BITS(16,17) & ((regval) << 16)) +#define BPCTL_BAVCA(regval) (BITS(16,17) & ((uint32_t)(regval) << 16)) #define IPA_BG_ALPHA_MODE_0 BPCTL_BAVCA(0) /*!< no effect */ #define IPA_BG_ALPHA_MODE_1 BPCTL_BAVCA(1) /*!< BPDAV[7:0] is selected as the background alpha value */ #define IPA_BG_ALPHA_MODE_2 BPCTL_BAVCA(2) /*!< BPDAV[7:0] multiplied by read alpha value */ /* foreground pixel format */ -#define FPCTL_PPF(regval) (BITS(0,3) & ((regval))) +#define FPCTL_PPF(regval) (BITS(0,3) & ((uint32_t)(regval))) #define FOREGROUND_PPF_ARGB8888 FPCTL_PPF(0) /*!< foreground pixel format ARGB8888 */ #define FOREGROUND_PPF_RGB888 FPCTL_PPF(1) /*!< foreground pixel format RGB888 */ #define FOREGROUND_PPF_RGB565 FPCTL_PPF(2) /*!< foreground pixel format RGB565 */ @@ -255,7 +280,7 @@ typedef enum #define FOREGROUND_PPF_A4 FPCTL_PPF(10) /*!< foreground pixel format A4 */ /* background pixel format */ -#define BPCTL_PPF(regval) (BITS(0,3) & ((regval))) +#define BPCTL_PPF(regval) (BITS(0,3) & ((uint32_t)(regval))) #define BACKGROUND_PPF_ARGB8888 BPCTL_PPF(0) /*!< background pixel format ARGB8888 */ #define BACKGROUND_PPF_RGB888 BPCTL_PPF(1) /*!< background pixel format RGB888 */ #define BACKGROUND_PPF_RGB565 BPCTL_PPF(2) /*!< background pixel format RGB565 */ @@ -268,53 +293,92 @@ typedef enum #define BACKGROUND_PPF_A8 BPCTL_PPF(9) /*!< background pixel format A8 */ #define BACKGROUND_PPF_A4 BPCTL_PPF(10) /*!< background pixel format A4 */ +/* IPA flags */ +#define IPA_FLAG_TAE IPA_INTF_TAEIF /*!< transfer access error interrupt flag */ +#define IPA_FLAG_FTF IPA_INTF_FTFIF /*!< full transfer finish interrupt flag */ +#define IPA_FLAG_TLM IPA_INTF_TLMIF /*!< transfer line mark interrupt flag */ +#define IPA_FLAG_LAC IPA_INTF_LACIF /*!< LUT access conflict interrupt flag */ +#define IPA_FLAG_LLF IPA_INTF_LLFIF /*!< LUT loading finish interrupt flag */ +#define IPA_FLAG_WCF IPA_INTF_WCFIF /*!< wrong configuration interrupt flag */ -/* function declarations */ +/* IPA interrupt enable or disable */ +#define IPA_INT_TAE IPA_CTL_TAEIE /*!< transfer access error interrupt */ +#define IPA_INT_FTF IPA_CTL_FTFIE /*!< full transfer finish interrupt */ +#define IPA_INT_TLM IPA_CTL_TLMIE /*!< transfer line mark interrupt */ +#define IPA_INT_LAC IPA_CTL_LACIE /*!< LUT access conflict interrupt */ +#define IPA_INT_LLF IPA_CTL_LLFIE /*!< LUT loading finish interrupt */ +#define IPA_INT_WCF IPA_CTL_WCFIE /*!< wrong configuration interrupt */ +/* IPA interrupt flags */ +#define IPA_INT_FLAG_TAE IPA_INTF_TAEIF /*!< transfer access error interrupt flag */ +#define IPA_INT_FLAG_FTF IPA_INTF_FTFIF /*!< full transfer finish interrupt flag */ +#define IPA_INT_FLAG_TLM IPA_INTF_TLMIF /*!< transfer line mark interrupt flag */ +#define IPA_INT_FLAG_LAC IPA_INTF_LACIF /*!< LUT access conflict interrupt flag */ +#define IPA_INT_FLAG_LLF IPA_INTF_LLFIF /*!< LUT loading finish interrupt flag */ +#define IPA_INT_FLAG_WCF IPA_INTF_WCFIF /*!< wrong configuration interrupt flag */ + +/* function declarations */ +/* functions enable or disable, pixel format convert mode set */ /* deinitialize IPA */ void ipa_deinit(void); -/* IPA transfer enable */ +/* enable IPA transfer */ void ipa_transfer_enable(void); -/* IPA transfer hang up enable */ +/* enable IPA transfer hang up */ void ipa_transfer_hangup_enable(void); -/* IPA transfer hang up disable */ +/* disable IPA transfer hang up */ void ipa_transfer_hangup_disable(void); -/* IPA transfer stop enable */ +/* enable IPA transfer stop */ void ipa_transfer_stop_enable(void); -/* IPA transfer stop disable */ +/* disable IPA transfer stop */ void ipa_transfer_stop_disable(void); -/* IPA foreground LUT loading enable */ +/* enable IPA foreground LUT loading */ void ipa_foreground_lut_loading_enable(void); -/* IPA background LUT loading enable */ +/* enable IPA background LUT loading */ void ipa_background_lut_loading_enable(void); -/* IPA transfer enable */ -void ipa_pixel_format_convert_mod(uint32_t pfcm); +/* set pixel format convert mode, the function is invalid when the IPA transfer is enabled */ +void ipa_pixel_format_convert_mode_set(uint32_t pfcm); +/* structure initialization, foreground, background, destination and LUT initialization */ +/* initialize the structure of IPA foreground parameter struct with the default values, it is + suggested that call this function after an ipa_foreground_parameter_struct structure is defined */ +void ipa_foreground_struct_para_init(ipa_foreground_parameter_struct* foreground_struct); /* initialize foreground parameters */ void ipa_foreground_init(ipa_foreground_parameter_struct* foreground_struct); +/* initialize the structure of IPA background parameter struct with the default values, it is + suggested that call this function after an ipa_background_parameter_struct structure is defined */ +void ipa_background_struct_para_init(ipa_background_parameter_struct* background_struct); /* initialize background parameters */ void ipa_background_init(ipa_background_parameter_struct* background_struct); +/* initialize the structure of IPA destination parameter struct with the default values, it is + suggested that call this function after an ipa_destination_parameter_struct structure is defined */ +void ipa_destination_struct_para_init(ipa_destination_parameter_struct* destination_struct); /* initialize destination parameters */ void ipa_destination_init(ipa_destination_parameter_struct* destination_struct); /* initialize IPA foreground LUT parameters */ -void ipa_foreground_lut_init(uint32_t fg_lut_num,uint8_t fg_lut_pf, uint32_t fg_lut_addr); +void ipa_foreground_lut_init(uint8_t fg_lut_num, uint8_t fg_lut_pf, uint32_t fg_lut_addr); /* initialize IPA background LUT parameters */ -void ipa_background_lut_init(uint32_t bg_lut_num,uint8_t bg_lut_pf, uint32_t bg_lut_addr); +void ipa_background_lut_init(uint8_t bg_lut_num, uint8_t bg_lut_pf, uint32_t bg_lut_addr); -/* configure line mark */ -void ipa_line_mark_config(uint32_t linenum); -/* Inter-timer enable or disable */ -void ipa_inter_timer_config(uint8_t timercfg); -/* number of clock cycles interval set */ -void ipa_interval_clock_num_config(uint32_t clk_num ); +/* configuration functions */ +/* configure IPA line mark */ +void ipa_line_mark_config(uint16_t line_num); +/* inter-timer enable or disable */ +void ipa_inter_timer_config(uint8_t timer_cfg); +/* configure the number of clock cycles interval */ +void ipa_interval_clock_num_config(uint8_t clk_num); -/* IPA interrupt enable */ -void ipa_interrupt_enable(uint32_t inttype); -/* IPA interrupt disable */ -void ipa_interrupt_disable(uint32_t inttype); +/* flag and interrupt functions */ +/* get IPA flag status in IPA_INTF register */ +FlagStatus ipa_flag_get(uint32_t flag); +/* clear IPA flag in IPA_INTF register */ +void ipa_flag_clear(uint32_t flag); +/* enable IPA interrupt */ +void ipa_interrupt_enable(uint32_t int_flag); +/* disable IPA interrupt */ +void ipa_interrupt_disable(uint32_t int_flag); /* get IPA interrupt flag */ -FlagStatus ipa_interrupt_flag_get(uint32_t intflag); +FlagStatus ipa_interrupt_flag_get(uint32_t int_flag); /* clear IPA interrupt flag */ -void ipa_interrupt_flag_clear(uint32_t intflag); +void ipa_interrupt_flag_clear(uint32_t int_flag); #endif /* GD32F4XX_IPA_H */ diff --git a/bsp/gd32450z-eval/Libraries/GD32F4xx_standard_peripheral/Include/gd32f4xx_iref.h b/bsp/gd32450z-eval/Libraries/GD32F4xx_standard_peripheral/Include/gd32f4xx_iref.h index 0b7b3224d9..4be9181ed8 100644 --- a/bsp/gd32450z-eval/Libraries/GD32F4xx_standard_peripheral/Include/gd32f4xx_iref.h +++ b/bsp/gd32450z-eval/Libraries/GD32F4xx_standard_peripheral/Include/gd32f4xx_iref.h @@ -1,12 +1,37 @@ /*! - \file gd32f4xx_iref.h - \brief definitions for the IREF + \file gd32f4xx_iref.h + \brief definitions for the IREF + + \version 2016-08-15, V1.0.0, firmware for GD32F4xx + \version 2018-12-12, V2.0.0, firmware for GD32F4xx + \version 2020-09-30, V2.1.0, firmware for GD32F4xx */ /* - Copyright (C) 2016 GigaDevice + Copyright (c) 2020, GigaDevice Semiconductor Inc. + + Redistribution and use in source and binary forms, with or without modification, +are permitted provided that the following conditions are met: + + 1. Redistributions of source code must retain the above copyright notice, this + list of conditions and the following disclaimer. + 2. Redistributions in binary form must reproduce the above copyright notice, + this list of conditions and the following disclaimer in the documentation + and/or other materials provided with the distribution. + 3. Neither the name of the copyright holder nor the names of its contributors + may be used to endorse or promote products derived from this software without + specific prior written permission. - 2016-08-15, V1.0.0, firmware for GD32F4xx + THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED +WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. +IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, +INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT +NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR +PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, +WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY +OF SUCH DAMAGE. */ #ifndef GD32F4XX_IREF_H @@ -25,7 +50,7 @@ #define IREF_CTL_CSDT BITS(0,5) /*!< current step data */ #define IREF_CTL_SCMOD BIT(7) /*!< sink current mode */ #define IREF_CTL_CPT BITS(8,12) /*!< current precision trim */ -#define IREF_CTL_SSEL BIT(14) /*!< step selection */ +#define IREF_CTL_SSEL BIT(14) /*!< step selection */ #define IREF_CTL_CREN BIT(15) /*!< current reference enable */ /* constants definitions */ @@ -130,13 +155,13 @@ #define IREF_CUR_STEP_DATA_61 CTL_CSDT(61) /*!< IREF current step data 61 */ #define IREF_CUR_STEP_DATA_62 CTL_CSDT(62) /*!< IREF current step data 62 */ #define IREF_CUR_STEP_DATA_63 CTL_CSDT(63) /*!< IREF current step data 63 */ - + /* IREF mode selection */ #define IREF_STEP(regval) (BIT(14) & ((uint32_t)(regval) << 14)) #define IREF_MODE_LOW_POWER IREF_STEP(0) /*!< low power, 1uA step */ #define IREF_MODE_HIGH_CURRENT IREF_STEP(1) /*!< high current, 8uA step */ - -/* IREF sink current mode*/ + +/* IREF sink current mode*/ #define IREF_CURRENT(regval) (BIT(7) & ((uint32_t)(regval) << 7)) #define IREF_SOURCE_CURRENT IREF_CURRENT(0) /*!< IREF source current */ #define IREF_SINK_CURRENT IREF_CURRENT(1) /*!< IREF sink current */ diff --git a/bsp/gd32450z-eval/Libraries/GD32F4xx_standard_peripheral/Include/gd32f4xx_misc.h b/bsp/gd32450z-eval/Libraries/GD32F4xx_standard_peripheral/Include/gd32f4xx_misc.h index 2052abe9a0..21ae664c14 100644 --- a/bsp/gd32450z-eval/Libraries/GD32F4xx_standard_peripheral/Include/gd32f4xx_misc.h +++ b/bsp/gd32450z-eval/Libraries/GD32F4xx_standard_peripheral/Include/gd32f4xx_misc.h @@ -1,12 +1,37 @@ /*! - \file gd32f4xx_misc.h - \brief definitions for the MISC + \file gd32f4xx_misc.h + \brief definitions for the MISC + + \version 2016-08-15, V1.0.0, firmware for GD32F4xx + \version 2018-12-12, V2.0.0, firmware for GD32F4xx + \version 2020-09-30, V2.1.0, firmware for GD32F4xx */ /* - Copyright (C) 2016 GigaDevice + Copyright (c) 2020, GigaDevice Semiconductor Inc. + + Redistribution and use in source and binary forms, with or without modification, +are permitted provided that the following conditions are met: + + 1. Redistributions of source code must retain the above copyright notice, this + list of conditions and the following disclaimer. + 2. Redistributions in binary form must reproduce the above copyright notice, + this list of conditions and the following disclaimer in the documentation + and/or other materials provided with the distribution. + 3. Neither the name of the copyright holder nor the names of its contributors + may be used to endorse or promote products derived from this software without + specific prior written permission. - 2016-08-15, V1.0.0, firmware for GD32F4xx + THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED +WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. +IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, +INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT +NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR +PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, +WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY +OF SUCH DAMAGE. */ #ifndef GD32F4XX_MISC_H diff --git a/bsp/gd32450z-eval/Libraries/GD32F4xx_standard_peripheral/Include/gd32f4xx_pmu.h b/bsp/gd32450z-eval/Libraries/GD32F4xx_standard_peripheral/Include/gd32f4xx_pmu.h index 74a857e96c..f19b1cb2ec 100644 --- a/bsp/gd32450z-eval/Libraries/GD32F4xx_standard_peripheral/Include/gd32f4xx_pmu.h +++ b/bsp/gd32450z-eval/Libraries/GD32F4xx_standard_peripheral/Include/gd32f4xx_pmu.h @@ -1,14 +1,40 @@ /*! - \file gd32f4xx_pmu.h - \brief definitions for the PMU + \file gd32f4xx_pmu.h + \brief definitions for the PMU + + \version 2016-08-15, V1.0.0, firmware for GD32F4xx + \version 2018-12-12, V2.0.0, firmware for GD32F4xx + \version 2020-09-30, V2.1.0, firmware for GD32F4xx */ /* - Copyright (C) 2016 GigaDevice + Copyright (c) 2020, GigaDevice Semiconductor Inc. + + Redistribution and use in source and binary forms, with or without modification, +are permitted provided that the following conditions are met: - 2016-08-15, V1.0.0, firmware for GD32F4xx + 1. Redistributions of source code must retain the above copyright notice, this + list of conditions and the following disclaimer. + 2. Redistributions in binary form must reproduce the above copyright notice, + this list of conditions and the following disclaimer in the documentation + and/or other materials provided with the distribution. + 3. Neither the name of the copyright holder nor the names of its contributors + may be used to endorse or promote products derived from this software without + specific prior written permission. + + THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED +WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. +IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, +INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT +NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR +PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, +WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY +OF SUCH DAMAGE. */ + #ifndef GD32F4XX_PMU_H #define GD32F4XX_PMU_H @@ -52,14 +78,14 @@ /* constants definitions */ /* PMU low voltage detector threshold definitions */ #define CTL_LVDT(regval) (BITS(5,7)&((uint32_t)(regval)<<5)) -#define PMU_LVDT_0 CTL_LVDT(0) /*!< voltage threshold is 2.2V */ +#define PMU_LVDT_0 CTL_LVDT(0) /*!< voltage threshold is 2.1V */ #define PMU_LVDT_1 CTL_LVDT(1) /*!< voltage threshold is 2.3V */ #define PMU_LVDT_2 CTL_LVDT(2) /*!< voltage threshold is 2.4V */ -#define PMU_LVDT_3 CTL_LVDT(3) /*!< voltage threshold is 2.5V */ -#define PMU_LVDT_4 CTL_LVDT(4) /*!< voltage threshold is 2.6V */ -#define PMU_LVDT_5 CTL_LVDT(5) /*!< voltage threshold is 2.7V */ -#define PMU_LVDT_6 CTL_LVDT(6) /*!< voltage threshold is 2.8V */ -#define PMU_LVDT_7 CTL_LVDT(7) /*!< voltage threshold is 2.9V */ +#define PMU_LVDT_3 CTL_LVDT(3) /*!< voltage threshold is 2.6V */ +#define PMU_LVDT_4 CTL_LVDT(4) /*!< voltage threshold is 2.7V */ +#define PMU_LVDT_5 CTL_LVDT(5) /*!< voltage threshold is 2.9V */ +#define PMU_LVDT_6 CTL_LVDT(6) /*!< voltage threshold is 3.0V */ +#define PMU_LVDT_7 CTL_LVDT(7) /*!< voltage threshold is 3.1V */ /* PMU LDO output voltage select definitions */ #define CTL_LDOVS(regval) (BITS(14,15)&((uint32_t)(regval)<<14)) @@ -124,7 +150,7 @@ void pmu_deinit(void); /* select low voltage detector threshold */ -void pmu_lvd_select(uint32_t pmu_lvdt_n); +void pmu_lvd_select(uint32_t lvdt_n); /* LDO output voltage select */ void pmu_ldo_output_select(uint32_t ldo_output); /* PMU lvd disable */ @@ -148,7 +174,7 @@ void pmu_lowdriver_normalpower_config(uint32_t mode); /* PMU work at sleep mode */ void pmu_to_sleepmode(uint8_t sleepmodecmd); /* PMU work at deepsleep mode */ -void pmu_to_deepsleepmode(uint32_t pmu_ldo, uint8_t deepsleepmodecmd); +void pmu_to_deepsleepmode(uint32_t ldo, uint8_t deepsleepmodecmd); /* PMU work at standby mode */ void pmu_to_standbymode(uint8_t standbymodecmd); /* PMU wakeup pin enable */ diff --git a/bsp/gd32450z-eval/Libraries/GD32F4xx_standard_peripheral/Include/gd32f4xx_rcu.h b/bsp/gd32450z-eval/Libraries/GD32F4xx_standard_peripheral/Include/gd32f4xx_rcu.h index 6851c2e22f..0445df4eb0 100644 --- a/bsp/gd32450z-eval/Libraries/GD32F4xx_standard_peripheral/Include/gd32f4xx_rcu.h +++ b/bsp/gd32450z-eval/Libraries/GD32F4xx_standard_peripheral/Include/gd32f4xx_rcu.h @@ -1,12 +1,37 @@ /*! - \file gd32f4xx_rcu.h - \brief definitions for the RCU + \file gd32f4xx_rcu.h + \brief definitions for the RCU + + \version 2016-08-15, V1.0.0, firmware for GD32F4xx + \version 2018-12-12, V2.0.0, firmware for GD32F4xx + \version 2020-09-30, V2.1.0, firmware for GD32F4xx */ /* - Copyright (C) 2016 GigaDevice + Copyright (c) 2020, GigaDevice Semiconductor Inc. + + Redistribution and use in source and binary forms, with or without modification, +are permitted provided that the following conditions are met: - 2016-08-15, V1.0.0, firmware for GD32F4xx + 1. Redistributions of source code must retain the above copyright notice, this + list of conditions and the following disclaimer. + 2. Redistributions in binary form must reproduce the above copyright notice, + this list of conditions and the following disclaimer in the documentation + and/or other materials provided with the distribution. + 3. Neither the name of the copyright holder nor the names of its contributors + may be used to endorse or promote products derived from this software without + specific prior written permission. + + THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED +WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. +IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, +INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT +NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR +PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, +WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY +OF SUCH DAMAGE. */ #ifndef GD32F4XX_RCU_H @@ -34,14 +59,14 @@ #define RCU_APB2EN REG32(RCU + 0x44U) /*!< APB2 enable register */ #define RCU_AHB1SPEN REG32(RCU + 0x50U) /*!< AHB1 sleep mode enable register */ #define RCU_AHB2SPEN REG32(RCU + 0x54U) /*!< AHB2 sleep mode enable register */ -#define RCU_AHB3SPEN REG32(RCU + 0x58U) /*!< AHB3 sleep mode enable register */ +#define RCU_AHB3SPEN REG32(RCU + 0x58U) /*!< AHB3 sleep mode enable register */ #define RCU_APB1SPEN REG32(RCU + 0x60U) /*!< APB1 sleep mode enable register */ #define RCU_APB2SPEN REG32(RCU + 0x64U) /*!< APB2 sleep mode enable register */ #define RCU_BDCTL REG32(RCU + 0x70U) /*!< backup domain control register */ #define RCU_RSTSCK REG32(RCU + 0x74U) /*!< reset source / clock register */ #define RCU_PLLSSCTL REG32(RCU + 0x80U) /*!< PLL clock spread spectrum control register */ -#define RCU_PLLI2S REG32(RCU + 0x84U) /*!< PLLI2S register */ -#define RCU_PLLSAI REG32(RCU + 0x88U) /*!< PLLSAI register */ +#define RCU_PLLI2S REG32(RCU + 0x84U) /*!< PLLI2S register */ +#define RCU_PLLSAI REG32(RCU + 0x88U) /*!< PLLSAI register */ #define RCU_CFG1 REG32(RCU + 0x8CU) /*!< clock configuration register 1 */ #define RCU_ADDCTL REG32(RCU + 0xC0U) /*!< Additional clock control register */ #define RCU_ADDINT REG32(RCU + 0xCCU) /*!< Additional clock interrupt register */ @@ -54,7 +79,7 @@ /* bits definitions */ /* RCU_CTL */ #define RCU_CTL_IRC16MEN BIT(0) /*!< internal high speed oscillator enable */ -#define RCU_CTL_IRC16MSTB BIT(1) /*!< IRC8M high speed internal oscillator stabilization flag */ +#define RCU_CTL_IRC16MSTB BIT(1) /*!< IRC16M high speed internal oscillator stabilization flag */ #define RCU_CTL_IRC16MADJ BITS(3,7) /*!< high speed internal oscillator clock trim adjust value */ #define RCU_CTL_IRC16MCALIB BITS(8,15) /*!< high speed internal oscillator calibration value register */ #define RCU_CTL_HXTALEN BIT(16) /*!< external high speed oscillator enable */ @@ -64,7 +89,7 @@ #define RCU_CTL_PLLEN BIT(24) /*!< PLL enable */ #define RCU_CTL_PLLSTB BIT(25) /*!< PLL Clock Stabilization Flag */ #define RCU_CTL_PLLI2SEN BIT(26) /*!< PLLI2S enable */ -#define RCU_CTL_PLLI2STB BIT(27) /*!< PLLI2S Clock Stabilization Flag */ +#define RCU_CTL_PLLI2SSTB BIT(27) /*!< PLLI2S Clock Stabilization Flag */ #define RCU_CTL_PLLSAIEN BIT(28) /*!< PLLSAI enable */ #define RCU_CTL_PLLSAISTB BIT(29) /*!< PLLSAI Clock Stabilization Flag */ @@ -123,7 +148,7 @@ #define RCU_AHB1RST_PGRST BIT(6) /*!< GPIO port G reset */ #define RCU_AHB1RST_PHRST BIT(7) /*!< GPIO port H reset */ #define RCU_AHB1RST_PIRST BIT(8) /*!< GPIO port I reset */ -#define RCU_AHB1RST_CRCRST BIT(12) /*!< CRC reset */ +#define RCU_AHB1RST_CRCRST BIT(12) /*!< CRC reset */ #define RCU_AHB1RST_DMA0RST BIT(21) /*!< DMA0 reset */ #define RCU_AHB1RST_DMA1RST BIT(22) /*!< DMA1 reset */ #define RCU_AHB1RST_IPARST BIT(23) /*!< IPA reset */ @@ -134,7 +159,7 @@ #define RCU_AHB2RST_DCIRST BIT(0) /*!< DCI reset */ #define RCU_AHB2RST_TRNGRST BIT(6) /*!< TRNG reset */ #define RCU_AHB2RST_USBFSRST BIT(7) /*!< USBFS reset */ - + /* RCU_AHB3RST */ #define RCU_AHB3RST_EXMCRST BIT(0) /*!< EXMC reset */ @@ -167,9 +192,9 @@ /* RCU_APB2RST */ #define RCU_APB2RST_TIMER0RST BIT(0) /*!< TIMER0 reset */ -#define RCU_APB2RST_TIMER7RST BIT(1) /*!< TIMER7 reset */ +#define RCU_APB2RST_TIMER7RST BIT(1) /*!< TIMER7 reset */ #define RCU_APB2RST_USART0RST BIT(4) /*!< USART0 reset */ -#define RCU_APB2RST_USART5RST BIT(5) /*!< USART5 reset */ +#define RCU_APB2RST_USART5RST BIT(5) /*!< USART5 reset */ #define RCU_APB2RST_ADCRST BIT(8) /*!< ADC reset */ #define RCU_APB2RST_SDIORST BIT(11) /*!< SDIO reset */ #define RCU_APB2RST_SPI0RST BIT(12) /*!< SPI0 reset */ @@ -361,11 +386,11 @@ #define RCU_RSTSCK_LPRSTF BIT(31) /*!< low-power reset flag */ /* RCU_PLLSSCTL */ -#define RCU_PLLSSCTL_MODCNT BITS(0,12) /*!< these bits configure PLL spread spectrum modulation - profile amplitude and frequency. the following criteria +#define RCU_PLLSSCTL_MODCNT BITS(0,12) /*!< these bits configure PLL spread spectrum modulation + profile amplitude and frequency. the following criteria must be met: MODSTEP*MODCNT=215-1 */ -#define RCU_PLLSSCTL_MODSTEP BITS(13,27) /*!< these bits configure PLL spread spectrum modulation - profile amplitude and frequency. the following criteria +#define RCU_PLLSSCTL_MODSTEP BITS(13,27) /*!< these bits configure PLL spread spectrum modulation + profile amplitude and frequency. the following criteria must be met: MODSTEP*MODCNT=215-1 */ #define RCU_PLLSSCTL_SS_TYPE BIT(30) /*!< PLL spread spectrum modulation type select */ #define RCU_PLLSSCTL_SSCGON BIT(31) /*!< PLL spread spectrum modulation enable */ @@ -438,7 +463,7 @@ #define ADD_APB1EN_REG_OFFSET 0xE4U /*!< APB1 additional enable register offset */ #define ADD_APB1SPEN_REG_OFFSET 0xE8U /*!< APB1 additional sleep mode enable register offset */ -/* peripherals reset */ +/* peripherals reset */ #define AHB1RST_REG_OFFSET 0x10U /*!< AHB1 reset register offset */ #define AHB2RST_REG_OFFSET 0x14U /*!< AHB2 reset register offset */ #define AHB3RST_REG_OFFSET 0x18U /*!< AHB3 reset register offset */ @@ -504,7 +529,7 @@ typedef enum RCU_TIMER6 = RCU_REGIDX_BIT(APB1EN_REG_OFFSET, 5U), /*!< TIMER6 clock */ RCU_TIMER11 = RCU_REGIDX_BIT(APB1EN_REG_OFFSET, 6U), /*!< TIMER11 clock */ RCU_TIMER12 = RCU_REGIDX_BIT(APB1EN_REG_OFFSET, 7U), /*!< TIMER12 clock */ - RCU_TIMER13 = RCU_REGIDX_BIT(APB1EN_REG_OFFSET, 8U), /*!< TIMER13 clock */ + RCU_TIMER13 = RCU_REGIDX_BIT(APB1EN_REG_OFFSET, 8U), /*!< TIMER13 clock */ RCU_WWDGT = RCU_REGIDX_BIT(APB1EN_REG_OFFSET, 11U), /*!< WWDGT clock */ RCU_SPI1 = RCU_REGIDX_BIT(APB1EN_REG_OFFSET, 14U), /*!< SPI1 clock */ RCU_SPI2 = RCU_REGIDX_BIT(APB1EN_REG_OFFSET, 15U), /*!< SPI2 clock */ @@ -514,7 +539,7 @@ typedef enum RCU_UART4 = RCU_REGIDX_BIT(APB1EN_REG_OFFSET, 20U), /*!< UART4 clock */ RCU_I2C0 = RCU_REGIDX_BIT(APB1EN_REG_OFFSET, 21U), /*!< I2C0 clock */ RCU_I2C1 = RCU_REGIDX_BIT(APB1EN_REG_OFFSET, 22U), /*!< I2C1 clock */ - RCU_I2C2 = RCU_REGIDX_BIT(APB1EN_REG_OFFSET, 23U), /*!< I2C2 clock */ + RCU_I2C2 = RCU_REGIDX_BIT(APB1EN_REG_OFFSET, 23U), /*!< I2C2 clock */ RCU_CAN0 = RCU_REGIDX_BIT(APB1EN_REG_OFFSET, 25U), /*!< CAN0 clock */ RCU_CAN1 = RCU_REGIDX_BIT(APB1EN_REG_OFFSET, 26U), /*!< CAN1 clock */ RCU_PMU = RCU_REGIDX_BIT(APB1EN_REG_OFFSET, 28U), /*!< PMU clock */ @@ -540,7 +565,7 @@ typedef enum RCU_SPI4 = RCU_REGIDX_BIT(APB2EN_REG_OFFSET, 20U), /*!< SPI4 clock */ RCU_SPI5 = RCU_REGIDX_BIT(APB2EN_REG_OFFSET, 21U), /*!< SPI5 clock */ RCU_TLI = RCU_REGIDX_BIT(APB2EN_REG_OFFSET, 26U), /*!< TLI clock */ - /* APB2 additional peripherals */ + /* APB1 additional peripherals */ RCU_CTC = RCU_REGIDX_BIT(ADD_APB1EN_REG_OFFSET, 27U), /*!< CTC clock */ RCU_IREF = RCU_REGIDX_BIT(ADD_APB1EN_REG_OFFSET, 31U), /*!< IREF clock */ }rcu_periph_enum; @@ -588,7 +613,7 @@ typedef enum RCU_TIMER6_SLP = RCU_REGIDX_BIT(APB1SPEN_REG_OFFSET, 5U), /*!< TIMER6 clock */ RCU_TIMER11_SLP = RCU_REGIDX_BIT(APB1SPEN_REG_OFFSET, 6U), /*!< TIMER11 clock */ RCU_TIMER12_SLP = RCU_REGIDX_BIT(APB1SPEN_REG_OFFSET, 7U), /*!< TIMER12 clock */ - RCU_TIMER13_SLP = RCU_REGIDX_BIT(APB1SPEN_REG_OFFSET, 8U), /*!< TIMER13 clock */ + RCU_TIMER13_SLP = RCU_REGIDX_BIT(APB1SPEN_REG_OFFSET, 8U), /*!< TIMER13 clock */ RCU_WWDGT_SLP = RCU_REGIDX_BIT(APB1SPEN_REG_OFFSET, 11U), /*!< WWDGT clock */ RCU_SPI1_SLP = RCU_REGIDX_BIT(APB1SPEN_REG_OFFSET, 14U), /*!< SPI1 clock */ RCU_SPI2_SLP = RCU_REGIDX_BIT(APB1SPEN_REG_OFFSET, 15U), /*!< SPI2 clock */ @@ -598,7 +623,7 @@ typedef enum RCU_UART4_SLP = RCU_REGIDX_BIT(APB1SPEN_REG_OFFSET, 20U), /*!< UART4 clock */ RCU_I2C0_SLP = RCU_REGIDX_BIT(APB1SPEN_REG_OFFSET, 21U), /*!< I2C0 clock */ RCU_I2C1_SLP = RCU_REGIDX_BIT(APB1SPEN_REG_OFFSET, 22U), /*!< I2C1 clock */ - RCU_I2C2_SLP = RCU_REGIDX_BIT(APB1SPEN_REG_OFFSET, 23U), /*!< I2C2 clock */ + RCU_I2C2_SLP = RCU_REGIDX_BIT(APB1SPEN_REG_OFFSET, 23U), /*!< I2C2 clock */ RCU_CAN0_SLP = RCU_REGIDX_BIT(APB1SPEN_REG_OFFSET, 25U), /*!< CAN0 clock */ RCU_CAN1_SLP = RCU_REGIDX_BIT(APB1SPEN_REG_OFFSET, 26U), /*!< CAN1 clock */ RCU_PMU_SLP = RCU_REGIDX_BIT(APB1SPEN_REG_OFFSET, 28U), /*!< PMU clock */ @@ -644,8 +669,8 @@ typedef enum RCU_CRCRST = RCU_REGIDX_BIT(AHB1RST_REG_OFFSET, 12U), /*!< CRC clock reset */ RCU_DMA0RST = RCU_REGIDX_BIT(AHB1RST_REG_OFFSET, 21U), /*!< DMA0 clock reset */ RCU_DMA1RST = RCU_REGIDX_BIT(AHB1RST_REG_OFFSET, 22U), /*!< DMA1 clock reset */ - RCU_IPAENRST = RCU_REGIDX_BIT(AHB1RST_REG_OFFSET, 23U), /*!< IPA clock reset */ - RCU_ENETRST = RCU_REGIDX_BIT(AHB1RST_REG_OFFSET, 25U), /*!< ENET clock reset */ + RCU_IPARST = RCU_REGIDX_BIT(AHB1RST_REG_OFFSET, 23U), /*!< IPA clock reset */ + RCU_ENETRST = RCU_REGIDX_BIT(AHB1RST_REG_OFFSET, 25U), /*!< ENET clock reset */ RCU_USBHSRST = RCU_REGIDX_BIT(AHB1RST_REG_OFFSET, 29U), /*!< USBHS clock reset */ /* AHB2 peripherals */ RCU_DCIRST = RCU_REGIDX_BIT(AHB2RST_REG_OFFSET, 0U), /*!< DCI clock reset */ @@ -662,7 +687,7 @@ typedef enum RCU_TIMER6RST = RCU_REGIDX_BIT(APB1RST_REG_OFFSET, 5U), /*!< TIMER6 clock reset */ RCU_TIMER11RST = RCU_REGIDX_BIT(APB1RST_REG_OFFSET, 6U), /*!< TIMER11 clock reset */ RCU_TIMER12RST = RCU_REGIDX_BIT(APB1RST_REG_OFFSET, 7U), /*!< TIMER12 clock reset */ - RCU_TIMER13RST = RCU_REGIDX_BIT(APB1RST_REG_OFFSET, 8U), /*!< TIMER13 clock reset */ + RCU_TIMER13RST = RCU_REGIDX_BIT(APB1RST_REG_OFFSET, 8U), /*!< TIMER13 clock reset */ RCU_WWDGTRST = RCU_REGIDX_BIT(APB1RST_REG_OFFSET, 11U), /*!< WWDGT clock reset */ RCU_SPI1RST = RCU_REGIDX_BIT(APB1RST_REG_OFFSET, 14U), /*!< SPI1 clock reset */ RCU_SPI2RST = RCU_REGIDX_BIT(APB1RST_REG_OFFSET, 15U), /*!< SPI2 clock reset */ @@ -672,7 +697,7 @@ typedef enum RCU_UART4RST = RCU_REGIDX_BIT(APB1RST_REG_OFFSET, 20U), /*!< UART4 clock reset */ RCU_I2C0RST = RCU_REGIDX_BIT(APB1RST_REG_OFFSET, 21U), /*!< I2C0 clock reset */ RCU_I2C1RST = RCU_REGIDX_BIT(APB1RST_REG_OFFSET, 22U), /*!< I2C1 clock reset */ - RCU_I2C2RST = RCU_REGIDX_BIT(APB1RST_REG_OFFSET, 23U), /*!< I2C2 clock reset */ + RCU_I2C2RST = RCU_REGIDX_BIT(APB1RST_REG_OFFSET, 23U), /*!< I2C2 clock reset */ RCU_CAN0RST = RCU_REGIDX_BIT(APB1RST_REG_OFFSET, 25U), /*!< CAN0 clock reset */ RCU_CAN1RST = RCU_REGIDX_BIT(APB1RST_REG_OFFSET, 26U), /*!< CAN1 clock reset */ RCU_PMURST = RCU_REGIDX_BIT(APB1RST_REG_OFFSET, 28U), /*!< PMU clock reset */ @@ -695,7 +720,7 @@ typedef enum RCU_SPI4RST = RCU_REGIDX_BIT(APB2RST_REG_OFFSET, 20U), /*!< SPI4 clock reset */ RCU_SPI5RST = RCU_REGIDX_BIT(APB2RST_REG_OFFSET, 21U), /*!< SPI5 clock reset */ RCU_TLIRST = RCU_REGIDX_BIT(APB2RST_REG_OFFSET, 26U), /*!< TLI clock reset */ - /* APB2 additional peripherals */ + /* APB1 additional peripherals */ RCU_CTCRST = RCU_REGIDX_BIT(ADD_APB1RST_REG_OFFSET, 27U), /*!< CTC clock reset */ RCU_IREFRST = RCU_REGIDX_BIT(ADD_APB1RST_REG_OFFSET, 31U) /*!< IREF clock reset */ }rcu_periph_reset_enum; @@ -727,7 +752,7 @@ typedef enum { RCU_INT_FLAG_IRC32KSTB = RCU_REGIDX_BIT(INT_REG_OFFSET, 0U), /*!< IRC32K stabilization interrupt flag */ RCU_INT_FLAG_LXTALSTB = RCU_REGIDX_BIT(INT_REG_OFFSET, 1U), /*!< LXTAL stabilization interrupt flag */ - RCU_INT_FLAG_IRC8MSTB = RCU_REGIDX_BIT(INT_REG_OFFSET, 2U), /*!< IRC8M stabilization interrupt flag */ + RCU_INT_FLAG_IRC16MSTB = RCU_REGIDX_BIT(INT_REG_OFFSET, 2U), /*!< IRC16M stabilization interrupt flag */ RCU_INT_FLAG_HXTALSTB = RCU_REGIDX_BIT(INT_REG_OFFSET, 3U), /*!< HXTAL stabilization interrupt flag */ RCU_INT_FLAG_PLLSTB = RCU_REGIDX_BIT(INT_REG_OFFSET, 4U), /*!< PLL stabilization interrupt flag */ RCU_INT_FLAG_PLLI2SSTB = RCU_REGIDX_BIT(INT_REG_OFFSET, 5U), /*!< PLLI2S stabilization interrupt flag */ @@ -755,7 +780,7 @@ typedef enum { RCU_INT_IRC32KSTB = RCU_REGIDX_BIT(INT_REG_OFFSET, 8U), /*!< IRC32K stabilization interrupt */ RCU_INT_LXTALSTB = RCU_REGIDX_BIT(INT_REG_OFFSET, 9U), /*!< LXTAL stabilization interrupt */ - RCU_INT_IRC16MSTB = RCU_REGIDX_BIT(INT_REG_OFFSET, 10U), /*!< IRC8M stabilization interrupt */ + RCU_INT_IRC16MSTB = RCU_REGIDX_BIT(INT_REG_OFFSET, 10U), /*!< IRC16M stabilization interrupt */ RCU_INT_HXTALSTB = RCU_REGIDX_BIT(INT_REG_OFFSET, 11U), /*!< HXTAL stabilization interrupt */ RCU_INT_PLLSTB = RCU_REGIDX_BIT(INT_REG_OFFSET, 12U), /*!< PLL stabilization interrupt */ RCU_INT_PLLI2SSTB = RCU_REGIDX_BIT(INT_REG_OFFSET, 13U), /*!< PLLI2S stabilization interrupt */ @@ -890,7 +915,7 @@ typedef enum /* CKOUT1 Clock source selection */ #define CFG0_CKOUT1SEL(regval) (BITS(30,31) & ((uint32_t)(regval) << 30)) #define RCU_CKOUT1SRC_SYSTEMCLOCK CFG0_CKOUT1SEL(0) /*!< system clock selected */ -#define RCU_CKOUT1SRC_PLLI2SR CFG0_CKOUT1SEL(1) /*!< low speed crystal oscillator clock (LXTAL) selected */ +#define RCU_CKOUT1SRC_PLLI2SR CFG0_CKOUT1SEL(1) /*!< CK_PLLI2SR clock selected */ #define RCU_CKOUT1SRC_HXTAL CFG0_CKOUT1SEL(2) /*!< high speed crystal oscillator clock (HXTAL) selected */ #define RCU_CKOUT1SRC_PLLP CFG0_CKOUT1SEL(3) /*!< CK_PLLP clock selected */ @@ -938,13 +963,13 @@ typedef enum #define RCU_PLLSAIR_DIV16 CFG1_PLLSAIRDIV(3) /*!< CK_PLLSAIRDIV clock select CK_PLLSAIR/16 */ /* TIMER clock selection */ -#define RCU_TIMER_PSC_MUL2 ~RCU_CFG1_TIMERSEL /*!< if APB1PSC/APB2PSC in RCU_CFG0 register is 0b0xx(CK_APBx = CK_AHB) +#define RCU_TIMER_PSC_MUL2 ~RCU_CFG1_TIMERSEL /*!< if APB1PSC/APB2PSC in RCU_CFG0 register is 0b0xx(CK_APBx = CK_AHB) or 0b100(CK_APBx = CK_AHB/2), the TIMER clock is equal to CK_AHB(CK_TIMERx = CK_AHB). - or else, the TIMER clock is twice the corresponding APB clock (TIMER in APB1 domain: CK_TIMERx = 2 x CK_APB1; + or else, the TIMER clock is twice the corresponding APB clock (TIMER in APB1 domain: CK_TIMERx = 2 x CK_APB1; TIMER in APB2 domain: CK_TIMERx = 2 x CK_APB2) */ -#define RCU_TIMER_PSC_MUL4 RCU_CFG1_TIMERSEL /*!< if APB1PSC/APB2PSC in RCU_CFG0 register is 0b0xx(CK_APBx = CK_AHB), - 0b100(CK_APBx = CK_AHB/2), or 0b101(CK_APBx = CK_AHB/4), the TIMER clock is equal to CK_AHB(CK_TIMERx = CK_AHB). - or else, the TIMER clock is four timers the corresponding APB clock (TIMER in APB1 domain: CK_TIMERx = 4 x CK_APB1; +#define RCU_TIMER_PSC_MUL4 RCU_CFG1_TIMERSEL /*!< if APB1PSC/APB2PSC in RCU_CFG0 register is 0b0xx(CK_APBx = CK_AHB), + 0b100(CK_APBx = CK_AHB/2), or 0b101(CK_APBx = CK_AHB/4), the TIMER clock is equal to CK_AHB(CK_TIMERx = CK_AHB). + or else, the TIMER clock is four timers the corresponding APB clock (TIMER in APB1 domain: CK_TIMERx = 4 x CK_APB1; TIMER in APB2 domain: CK_TIMERx = 4 x CK_APB2) */ /* RCU_PLLSSCTL register bit define */ @@ -966,7 +991,7 @@ typedef enum /* The PLLP output frequency division factor from PLL VCO clock */ #define RCU_PLLP_DIV_MIN ((uint32_t)2U) /*!< PLLP_DIV min value */ #define RCU_PLLP_DIV_MAX ((uint32_t)8U) /*!< PLLP_DIV max value */ - + /* PLL Clock Source Selection */ #define RCU_PLLSRC_IRC16M ((uint32_t)0x00000000U) /*!< IRC16M clock selected as source clock of PLL, PLLSAI, PLLI2S */ #define RCU_PLLSRC_HXTAL RCU_PLL_PLLSEL /*!< HXTAL clock selected as source clock of PLL, PLLSAI, PLLI2S */ @@ -975,10 +1000,10 @@ typedef enum #define RCU_PLLQ_DIV_MIN ((uint32_t)2U) /*!< PLLQ_DIV min value */ #define RCU_PLLQ_DIV_MAX ((uint32_t)15U) /*!< PLLQ_DIV max value */ -#define CHECK_PLL_PSC_VALID(val) (((val) >= RCU_PLLPSC_DIV_MIN)&&((val) <= RCU_PLLPSC_DIV_MAX)) -#define CHECK_PLL_N_VALID(val, inc) (((val) >= (RCU_PLLN_MUL_MIN + (inc)))&&((val) <= RCU_PLLN_MUL_MAX)) -#define CHECK_PLL_P_VALID(val) (((val) == 2U) || ((val) == 4U) || ((val) == 6U) || ((val) == 8U)) -#define CHECK_PLL_Q_VALID(val) (((val) >= RCU_PLLQ_DIV_MIN)&&((val) <= RCU_PLLQ_DIV_MAX)) +#define CHECK_PLL_PSC_VALID(val) (((val) >= RCU_PLLPSC_DIV_MIN)&&((val) <= RCU_PLLPSC_DIV_MAX)) +#define CHECK_PLL_N_VALID(val, inc) (((val) >= (RCU_PLLN_MUL_MIN + (inc)))&&((val) <= RCU_PLLN_MUL_MAX)) +#define CHECK_PLL_P_VALID(val) (((val) == 2U) || ((val) == 4U) || ((val) == 6U) || ((val) == 8U)) +#define CHECK_PLL_Q_VALID(val) (((val) >= RCU_PLLQ_DIV_MIN)&&((val) <= RCU_PLLQ_DIV_MAX)) /* RCU_BDCTL register bit define */ /* LXTAL drive capability */ @@ -1033,7 +1058,7 @@ typedef enum #define CHECK_PLLSAI_R_VALID(val) (((val) >= RCU_PLLSAIR_DIV_MIN)&&((val) <= RCU_PLLSAIR_DIV_MAX)) /* RCU_ADDCTL register bit define */ -/* 48MHz clock selection */ +/* 48MHz clock selection */ #define RCU_CK48MSRC_PLL48M ((uint32_t)0x00000000U) /*!< CK48M source clock select PLL48M */ #define RCU_CK48MSRC_IRC48M RCU_ADDCTL_CK48MSEL /*!< CK48M source clock select IRC48M */ @@ -1086,11 +1111,13 @@ void rcu_ckout1_config(uint32_t ckout1_src, uint32_t ckout1_div); /* configure the PLL clock source selection and PLL multiply factor */ ErrStatus rcu_pll_config(uint32_t pll_src, uint32_t pll_psc, uint32_t pll_n, uint32_t pll_p, uint32_t pll_q); /* configure the PLLI2S clock */ -ErrStatus rcu_plli2s_config(uint32_t plli2s_n, uint32_t plli2s_q, uint32_t plli2s_r); +ErrStatus rcu_plli2s_config(uint32_t plli2s_n, uint32_t plli2s_r); /* configure the PLLSAI clock */ -ErrStatus rcu_pllsai_config(uint32_t pllsai_n, uint32_t pllsai_p, uint32_t pllsai_q, uint32_t pllsai_r); +ErrStatus rcu_pllsai_config(uint32_t pllsai_n, uint32_t pllsai_p, uint32_t pllsai_r); /* configure the RTC clock source selection */ void rcu_rtc_clock_config(uint32_t rtc_clock_source); +/* cconfigure the frequency division of RTC clock when HXTAL was selected as its clock source */ +void rcu_rtc_div_config(uint32_t rtc_div); /* configure the I2S clock source selection */ void rcu_i2s_clock_config(uint32_t i2s_clock_source); /* configure the CK48M clock selection */ @@ -1098,7 +1125,7 @@ void rcu_ck48m_clock_config(uint32_t ck48m_clock_source); /* configure the PLL48M clock selection */ void rcu_pll48m_clock_config(uint32_t pll48m_clock_source); /* configure the TIMER clock prescaler selection */ -void rcu_timer_clock_prescaler_config(uint32_t timer_clock_prescaler); +void rcu_timer_clock_prescaler_config(uint32_t timer_clock_prescaler); /* configure the TLI clock division selection */ void rcu_tli_clock_div_config(uint32_t pllsai_r_div); @@ -1110,11 +1137,11 @@ void rcu_all_reset_flag_clear(void); /* get the clock stabilization interrupt and ckm flags */ FlagStatus rcu_interrupt_flag_get(rcu_int_flag_enum int_flag); /* clear the interrupt flags */ -void rcu_interrupt_flag_clear(rcu_int_flag_clear_enum int_flag_clear); +void rcu_interrupt_flag_clear(rcu_int_flag_clear_enum int_flag); /* enable the stabilization interrupt */ -void rcu_interrupt_enable(rcu_int_enum stab_int); +void rcu_interrupt_enable(rcu_int_enum interrupt); /* disable the stabilization interrupt */ -void rcu_interrupt_disable(rcu_int_enum stab_int); +void rcu_interrupt_disable(rcu_int_enum interrupt); /* configure the LXTAL drive capability */ void rcu_lxtal_drive_capability_config(uint32_t lxtal_dricap); @@ -1140,7 +1167,7 @@ void rcu_spread_spectrum_config(uint32_t spread_spectrum_type, uint32_t modstep, /* enable the spread spectrum modulation for the main PLL clock */ void rcu_spread_spectrum_enable(void); /* disable the spread spectrum modulation for the main PLL clock */ -void rcu_spread_spectrum_disable(void); +void rcu_spread_spectrum_disable(void); /* unlock the voltage key */ void rcu_voltage_key_unlock(void); /* set the deep sleep mode voltage */ diff --git a/bsp/gd32450z-eval/Libraries/GD32F4xx_standard_peripheral/Include/gd32f4xx_rtc.h b/bsp/gd32450z-eval/Libraries/GD32F4xx_standard_peripheral/Include/gd32f4xx_rtc.h index 27155a3076..75e66f236e 100644 --- a/bsp/gd32450z-eval/Libraries/GD32F4xx_standard_peripheral/Include/gd32f4xx_rtc.h +++ b/bsp/gd32450z-eval/Libraries/GD32F4xx_standard_peripheral/Include/gd32f4xx_rtc.h @@ -1,14 +1,40 @@ /*! - \file gd32f4xx_rtc.h - \brief definitions for the RTC + \file gd32f4xx_rtc.c + \brief definitions for the RTC + + \version 2016-08-15, V1.0.0, firmware for GD32F4xx + \version 2018-12-12, V2.0.0, firmware for GD32F4xx + \version 2020-09-30, V2.1.0, firmware for GD32F4xx */ /* - Copyright (C) 2016 GigaDevice + Copyright (c) 2020, GigaDevice Semiconductor Inc. + + Redistribution and use in source and binary forms, with or without modification, +are permitted provided that the following conditions are met: + + 1. Redistributions of source code must retain the above copyright notice, this + list of conditions and the following disclaimer. + 2. Redistributions in binary form must reproduce the above copyright notice, + this list of conditions and the following disclaimer in the documentation + and/or other materials provided with the distribution. + 3. Neither the name of the copyright holder nor the names of its contributors + may be used to endorse or promote products derived from this software without + specific prior written permission. - 2016-08-15, V1.0.0, firmware for GD32F4xx + THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED +WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. +IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, +INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT +NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR +PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, +WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY +OF SUCH DAMAGE. */ + #ifndef GD32F4XX_RTC_H #define GD32F4XX_RTC_H @@ -254,7 +280,7 @@ typedef struct ControlStatus tamper_precharge_enable; /*!< RTC tamper precharge feature during a voltage level detection */ uint32_t tamper_precharge_time; /*!< RTC tamper precharge duration if precharge feature is enabled */ ControlStatus tamper_with_timestamp; /*!< RTC tamper time-stamp feature */ -}rtc_tamper_struct; +}rtc_tamper_struct; /* time register value */ #define TIME_SC(regval) (BITS(0,6) & ((uint32_t)(regval) << 0)) /*!< write value to RTC_TIME_SC bit field */ @@ -380,7 +406,7 @@ typedef struct #define GET_DTS_DAY(regval) GET_BITS((regval),0,5) /*!< get value of RTC_DTS_DAY bit field */ #define DTS_MON(regval) (BITS(8,12) & ((uint32_t)(regval) << 8)) /*!< write value to RTC_DTS_MON bit field */ -#define GET_DTS_MON(regval) GET_BITS((regval),8,11) /*!< get value of RTC_DTS_MON bit field */ +#define GET_DTS_MON(regval) GET_BITS((regval),8,12) /*!< get value of RTC_DTS_MON bit field */ #define DTS_DOW(regval) (BITS(13,15) & ((uint32_t)(regval) << 13)) /*!< write value to RTC_DTS_DOW bit field */ #define GET_DTS_DOW(regval) GET_BITS((regval),13,15) /*!< get value of RTC_DTS_DOW bit field */ @@ -399,7 +425,7 @@ typedef struct #define RTC_CALIBRATION_PLUS_RESET ((uint32_t)0x00000000U) /*!< no effect */ /* tamp register value */ -#define TAMP_FREQ(regval) (BITS(8,10) & ((uint32_t)(regval) << 10)) /*!< write value to RTC_TAMP_FREQ bit field */ +#define TAMP_FREQ(regval) (BITS(8,10) & ((uint32_t)(regval) << 8)) /*!< write value to RTC_TAMP_FREQ bit field */ #define RTC_FREQ_DIV32768 TAMP_FREQ(0) /*!< sample once every 32768 RTCCLK(1Hz if RTCCLK=32.768KHz) */ #define RTC_FREQ_DIV16384 TAMP_FREQ(1) /*!< sample once every 16384 RTCCLK(2Hz if RTCCLK=32.768KHz) */ #define RTC_FREQ_DIV8192 TAMP_FREQ(2) /*!< sample once every 8192 RTCCLK(4Hz if RTCCLK=32.768KHz) */ @@ -475,12 +501,12 @@ typedef struct #define RTC_WUT_RESET ((uint32_t)0x0000FFFFU) /*!< RTC_WUT register reset value */ /* RTC alarm */ -#define RTC_ALARM0 ((uint8_t)0x01U) /*!< RTC alarm 0 */ -#define RTC_ALARM1 ((uint8_t)0x02U) /*!< RTC alarm 1 */ +#define RTC_ALARM0 ((uint8_t)0x01U) /*!< RTC alarm 0 */ +#define RTC_ALARM1 ((uint8_t)0x02U) /*!< RTC alarm 1 */ /* RTC coarse calibration direction */ -#define CALIB_INCREASE ((uint8_t)0x01U) /*!< RTC coarse calibration increase */ -#define CALIB_DECREASE ((uint8_t)0x02U) /*!< RTC coarse calibration decrease */ +#define CALIB_INCREASE ((uint8_t)0x01U) /*!< RTC coarse calibration increase */ +#define CALIB_DECREASE ((uint8_t)0x02U) /*!< RTC coarse calibration decrease */ /* RTC wakeup timer clock */ #define CTL_WTCS(regval) (BITS(0,2) & ((regval)<< 0)) @@ -490,13 +516,30 @@ typedef struct #define WAKEUP_RTCCK_DIV2 CTL_WTCS(3) /*!< wakeup timer clock is RTC clock divided by 2 */ #define WAKEUP_CKSPRE CTL_WTCS(4) /*!< wakeup timer clock is ckapre */ #define WAKEUP_CKSPRE_2EXP16 CTL_WTCS(6) /*!< wakeup timer clock is ckapre and wakeup timer add 2exp16 */ - + /* RTC_AF pin */ #define RTC_AF0_TIMESTAMP ((uint32_t)0x00000000) /*!< RTC_AF0 use for timestamp */ #define RTC_AF1_TIMESTAMP RTC_TAMP_TSSEL /*!< RTC_AF1 use for timestamp */ #define RTC_AF0_TAMPER0 ((uint32_t)0x00000000) /*!< RTC_AF0 use for tamper0 */ #define RTC_AF1_TAMPER0 RTC_TAMP_TP0SEL /*!< RTC_AF1 use for tamper0 */ +/* RTC flags */ +#define RTC_FLAG_ALRM0W RTC_STAT_ALRM0WF /*!< alarm0 configuration can be write flag */ +#define RTC_FLAG_ALRM1W RTC_STAT_ALRM1WF /*!< alarm1 configuration can be write flag */ +#define RTC_FLAG_WTW RTC_STAT_WTWF /*!< wakeup timer can be write flag */ +#define RTC_FLAG_SOP RTC_STAT_SOPF /*!< shift function operation pending flag */ +#define RTC_FLAG_YCM RTC_STAT_YCM /*!< year configuration mark status flag */ +#define RTC_FLAG_RSYN RTC_STAT_RSYNF /*!< register synchronization flag */ +#define RTC_FLAG_INIT RTC_STAT_INITF /*!< initialization state flag */ +#define RTC_FLAG_ALRM0 RTC_STAT_ALRM0F /*!< alarm0 occurs flag */ +#define RTC_FLAG_ALRM1 RTC_STAT_ALRM1F /*!< alarm1 occurs flag */ +#define RTC_FLAG_WT RTC_STAT_WTF /*!< wakeup timer occurs flag */ +#define RTC_FLAG_TS RTC_STAT_TSF /*!< time-stamp flag */ +#define RTC_FLAG_TSOVR RTC_STAT_TSOVRF /*!< time-stamp overflow flag */ +#define RTC_FLAG_TP0 RTC_STAT_TP0F /*!< RTC tamper 0 detected flag */ +#define RTC_FLAG_TP1 RTC_STAT_TP1F /*!< RTC tamper 1 detected flag */ +#define RTC_STAT_SCP RTC_STAT_SCPF /*!< smooth calibration pending flag */ + /* function declarations */ /* reset most of the RTC registers */ ErrStatus rtc_deinit(void); diff --git a/bsp/gd32450z-eval/Libraries/GD32F4xx_standard_peripheral/Include/gd32f4xx_sdio.h b/bsp/gd32450z-eval/Libraries/GD32F4xx_standard_peripheral/Include/gd32f4xx_sdio.h index bd3b2c8fc6..a18214c023 100644 --- a/bsp/gd32450z-eval/Libraries/GD32F4xx_standard_peripheral/Include/gd32f4xx_sdio.h +++ b/bsp/gd32450z-eval/Libraries/GD32F4xx_standard_peripheral/Include/gd32f4xx_sdio.h @@ -1,12 +1,37 @@ /*! - \file gd32f4xx_sdio.h - \brief definitions for the SDIO + \file gd32f4xx_sdio.h + \brief definitions for the SDIO + + \version 2016-08-15, V1.0.0, firmware for GD32F4xx + \version 2018-12-12, V2.0.0, firmware for GD32F4xx + \version 2020-09-30, V2.1.0, firmware for GD32F4xx */ /* - Copyright (C) 2016 GigaDevice + Copyright (c) 2020, GigaDevice Semiconductor Inc. + + Redistribution and use in source and binary forms, with or without modification, +are permitted provided that the following conditions are met: + + 1. Redistributions of source code must retain the above copyright notice, this + list of conditions and the following disclaimer. + 2. Redistributions in binary form must reproduce the above copyright notice, + this list of conditions and the following disclaimer in the documentation + and/or other materials provided with the distribution. + 3. Neither the name of the copyright holder nor the names of its contributors + may be used to endorse or promote products derived from this software without + specific prior written permission. - 2016-08-15, V1.0.0, firmware for GD32F4xx + THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED +WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. +IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, +INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT +NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR +PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, +WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY +OF SUCH DAMAGE. */ #ifndef GD32F4XX_SDIO_H @@ -179,7 +204,7 @@ #define SDIO_FLAG_SDIOINT BIT(22) /*!< SD I/O interrupt received flag */ #define SDIO_FLAG_ATAEND BIT(23) /*!< CE-ATA command completion signal received (only for CMD61) flag */ -/* SDIO interrupt flags */ +/* SDIO interrupt enable or disable */ #define SDIO_INT_CCRCERR BIT(0) /*!< SDIO CCRCERR interrupt */ #define SDIO_INT_DTCRCERR BIT(1) /*!< SDIO DTCRCERR interrupt */ #define SDIO_INT_CMDTMOUT BIT(2) /*!< SDIO CMDTMOUT interrupt */ @@ -205,6 +230,32 @@ #define SDIO_INT_SDIOINT BIT(22) /*!< SDIO SDIOINT interrupt */ #define SDIO_INT_ATAEND BIT(23) /*!< SDIO ATAEND interrupt */ +/* SDIO interrupt flags */ +#define SDIO_INT_FLAG_CCRCERR BIT(0) /*!< SDIO CCRCERR interrupt flag */ +#define SDIO_INT_FLAG_DTCRCERR BIT(1) /*!< SDIO DTCRCERR interrupt flag */ +#define SDIO_INT_FLAG_CMDTMOUT BIT(2) /*!< SDIO CMDTMOUT interrupt flag */ +#define SDIO_INT_FLAG_DTTMOUT BIT(3) /*!< SDIO DTTMOUT interrupt flag */ +#define SDIO_INT_FLAG_TXURE BIT(4) /*!< SDIO TXURE interrupt flag */ +#define SDIO_INT_FLAG_RXORE BIT(5) /*!< SDIO RXORE interrupt flag */ +#define SDIO_INT_FLAG_CMDRECV BIT(6) /*!< SDIO CMDRECV interrupt flag */ +#define SDIO_INT_FLAG_CMDSEND BIT(7) /*!< SDIO CMDSEND interrupt flag */ +#define SDIO_INT_FLAG_DTEND BIT(8) /*!< SDIO DTEND interrupt flag */ +#define SDIO_INT_FLAG_STBITE BIT(9) /*!< SDIO STBITE interrupt flag */ +#define SDIO_INT_FLAG_DTBLKEND BIT(10) /*!< SDIO DTBLKEND interrupt flag */ +#define SDIO_INT_FLAG_CMDRUN BIT(11) /*!< SDIO CMDRUN interrupt flag */ +#define SDIO_INT_FLAG_TXRUN BIT(12) /*!< SDIO TXRUN interrupt flag */ +#define SDIO_INT_FLAG_RXRUN BIT(13) /*!< SDIO RXRUN interrupt flag */ +#define SDIO_INT_FLAG_TFH BIT(14) /*!< SDIO TFH interrupt flag */ +#define SDIO_INT_FLAG_RFH BIT(15) /*!< SDIO RFH interrupt flag */ +#define SDIO_INT_FLAG_TFF BIT(16) /*!< SDIO TFF interrupt flag */ +#define SDIO_INT_FLAG_RFF BIT(17) /*!< SDIO RFF interrupt flag */ +#define SDIO_INT_FLAG_TFE BIT(18) /*!< SDIO TFE interrupt flag */ +#define SDIO_INT_FLAG_RFE BIT(19) /*!< SDIO RFE interrupt flag */ +#define SDIO_INT_FLAG_TXDTVAL BIT(20) /*!< SDIO TXDTVAL interrupt flag */ +#define SDIO_INT_FLAG_RXDTVAL BIT(21) /*!< SDIO RXDTVAL interrupt flag */ +#define SDIO_INT_FLAG_SDIOINT BIT(22) /*!< SDIO SDIOINT interrupt flag */ +#define SDIO_INT_FLAG_ATAEND BIT(23) /*!< SDIO ATAEND interrupt flag */ + /* SDIO power control */ #define PWRCTL_PWRCTL(regval) (BITS(0,1) & ((uint32_t)(regval) << 0)) #define SDIO_POWER_OFF PWRCTL_PWRCTL(0) /*!< SDIO power off */ @@ -275,6 +326,7 @@ #define SDIO_READWAITTYPE_CLK SDIO_DATACTL_RWTYPE /*!< read wait control by stopping SDIO_CLK */ /* function declarations */ +/* de/initialization functions, hardware clock, bus mode, power_state and SDIO clock configuration */ /* deinitialize the SDIO */ void sdio_deinit(void); /* configure the SDIO clock */ @@ -294,7 +346,7 @@ void sdio_clock_enable(void); /* disable SDIO_CLK clock output */ void sdio_clock_disable(void); -/* configure the command index, argument, response type, wait type and CSM to send command */ +/* configure the command index, argument, response type, wait type and CSM to send command functions */ /* configure the command and response */ void sdio_command_response_config(uint32_t cmd_index, uint32_t cmd_argument, uint32_t response_type); /* set the command state machine wait type */ @@ -308,7 +360,7 @@ uint8_t sdio_command_index_get(void); /* get the response for the last received command */ uint32_t sdio_response_get(uint32_t sdio_responsex); -/* configure the data timeout, length, block size, transfer mode, direction and DSM for data transfer */ +/* configure the data timeout, length, block size, transfer mode, direction and DSM for data transfer functions */ /* configure the data timeout, data length and data block size */ void sdio_data_config(uint32_t data_timeout, uint32_t data_length, uint32_t data_blocksize); /* configure the data transfer mode and direction */ @@ -330,6 +382,7 @@ void sdio_dma_enable(void); /* disable the DMA request for SDIO */ void sdio_dma_disable(void); +/* flag and interrupt functions */ /* get the flags state of SDIO */ FlagStatus sdio_flag_get(uint32_t flag); /* clear the pending flags of SDIO */ @@ -343,6 +396,7 @@ FlagStatus sdio_interrupt_flag_get(uint32_t int_flag); /* clear the interrupt pending flags of SDIO */ void sdio_interrupt_flag_clear(uint32_t int_flag); +/* SD I/O card functions */ /* enable the read wait mode(SD I/O only) */ void sdio_readwait_enable(void); /* disable the read wait mode(SD I/O only) */ @@ -362,6 +416,7 @@ void sdio_suspend_enable(void); /* disable the SD I/O suspend operation(SD I/O only) */ void sdio_suspend_disable(void); +/* CE-ATA functions */ /* enable the CE-ATA command(CE-ATA only) */ void sdio_ceata_command_enable(void); /* disable the CE-ATA command(CE-ATA only) */ diff --git a/bsp/gd32450z-eval/Libraries/GD32F4xx_standard_peripheral/Include/gd32f4xx_spi.h b/bsp/gd32450z-eval/Libraries/GD32F4xx_standard_peripheral/Include/gd32f4xx_spi.h index 422df94a6f..61bf8b1af2 100644 --- a/bsp/gd32450z-eval/Libraries/GD32F4xx_standard_peripheral/Include/gd32f4xx_spi.h +++ b/bsp/gd32450z-eval/Libraries/GD32F4xx_standard_peripheral/Include/gd32f4xx_spi.h @@ -1,14 +1,40 @@ /*! - \file gd32f4xx_spi.h - \brief definitions for the SPI + \file gd32f4xx_spi.h + \brief definitions for the SPI + + \version 2016-08-15, V1.0.0, firmware for GD32F4xx + \version 2018-12-12, V2.0.0, firmware for GD32F4xx + \version 2020-09-30, V2.1.0, firmware for GD32F4xx */ /* - Copyright (C) 2016 GigaDevice + Copyright (c) 2020, GigaDevice Semiconductor Inc. + + Redistribution and use in source and binary forms, with or without modification, +are permitted provided that the following conditions are met: - 2016-08-15, V1.0.0, firmware for GD32F4xx + 1. Redistributions of source code must retain the above copyright notice, this + list of conditions and the following disclaimer. + 2. Redistributions in binary form must reproduce the above copyright notice, + this list of conditions and the following disclaimer in the documentation + and/or other materials provided with the distribution. + 3. Neither the name of the copyright holder nor the names of its contributors + may be used to endorse or promote products derived from this software without + specific prior written permission. + + THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED +WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. +IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, +INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT +NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR +PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, +WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY +OF SUCH DAMAGE. */ + #ifndef GD32F4XX_SPI_H #define GD32F4XX_SPI_H @@ -50,7 +76,7 @@ #define I2S_ADD_I2SPSC(i2sx_add) REG32((i2sx_add) + 0x20U) /*!< I2S_ADD I2S clock prescaler register */ /* bits definitions */ -/* SPIx_CTL0 */ +/* SPI_CTL0 */ #define SPI_CTL0_CKPH BIT(0) /*!< clock phase selection*/ #define SPI_CTL0_CKPL BIT(1) /*!< clock polarity selection */ #define SPI_CTL0_MSTMOD BIT(2) /*!< master mode enable */ @@ -66,7 +92,7 @@ #define SPI_CTL0_BDOEN BIT(14) /*!< bidirectional transmit output enable*/ #define SPI_CTL0_BDEN BIT(15) /*!< bidirectional enable */ -/* SPIx_CTL1 */ +/* SPI_CTL1 */ #define SPI_CTL1_DMAREN BIT(0) /*!< receive buffer dma enable */ #define SPI_CTL1_DMATEN BIT(1) /*!< transmit buffer dma enable */ #define SPI_CTL1_NSSDRV BIT(2) /*!< drive nss output */ @@ -75,16 +101,16 @@ #define SPI_CTL1_RBNEIE BIT(6) /*!< receive buffer not empty interrupt enable */ #define SPI_CTL1_TBEIE BIT(7) /*!< transmit buffer empty interrupt enable */ -/* SPIx_STAT */ +/* SPI_STAT */ #define SPI_STAT_RBNE BIT(0) /*!< receive buffer not empty */ #define SPI_STAT_TBE BIT(1) /*!< transmit buffer empty */ #define SPI_STAT_I2SCH BIT(2) /*!< I2S channel side */ #define SPI_STAT_TXURERR BIT(3) /*!< I2S transmission underrun error bit */ #define SPI_STAT_CRCERR BIT(4) /*!< SPI CRC error bit */ -#define SPI_STAT_CONFERR BIT(5) /*!< SPI configuration error */ -#define SPI_STAT_RXORERR BIT(6) /*!< SPI reception overrun error Bit */ -#define SPI_STAT_TRANS BIT(7) /*!< transmitting on-going Bit */ -#define SPI_STAT_FERR BIT(8) /*!< format error */ +#define SPI_STAT_CONFERR BIT(5) /*!< SPI configuration error bit */ +#define SPI_STAT_RXORERR BIT(6) /*!< SPI reception overrun error bit */ +#define SPI_STAT_TRANS BIT(7) /*!< transmitting on-going bit */ +#define SPI_STAT_FERR BIT(8) /*!< format error bit */ /* SPI_DATA */ #define SPI_DATA_DATA BITS(0,15) /*!< data transfer register */ @@ -96,9 +122,9 @@ #define SPI_RCRC_RCR BITS(0,15) /*!< RX CRC register */ /* SPI_TCRC */ -#define SPI_TCRC_TCR BITS(0,15) /*!< RX CRC register */ +#define SPI_TCRC_TCR BITS(0,15) /*!< TX CRC register */ -/* SPIx_I2SCTL */ +/* SPI_I2SCTL */ #define SPI_I2SCTL_CHLEN BIT(0) /*!< channel length */ #define SPI_I2SCTL_DTLEN BITS(1,2) /*!< data length */ #define SPI_I2SCTL_CKPL BIT(3) /*!< idle state clock polarity */ @@ -108,12 +134,12 @@ #define SPI_I2SCTL_I2SEN BIT(10) /*!< I2S enable */ #define SPI_I2SCTL_I2SSEL BIT(11) /*!< I2S mode selection */ -/* SPIx_I2S_PSC */ +/* SPI_I2S_PSC */ #define SPI_I2SPSC_DIV BITS(0,7) /*!< dividing factor for the prescaler */ #define SPI_I2SPSC_OF BIT(8) /*!< odd factor for the prescaler */ #define SPI_I2SPSC_MCKOEN BIT(9) /*!< I2S MCK output enable */ -/* SPIx_SPI_QCTL(only SPI5) */ +/* SPI_SPI_QCTL(only SPI5) */ #define SPI_QCTL_QMOD BIT(0) /*!< quad-SPI mode enable */ #define SPI_QCTL_QRD BIT(1) /*!< quad-SPI mode read select */ #define SPI_QCTL_IO23_DRV BIT(2) /*!< drive SPI_IO2 and SPI_IO3 enable */ @@ -121,7 +147,7 @@ /* constants definitions */ /* SPI and I2S parameter struct definitions */ typedef struct -{ +{ uint32_t device_mode; /*!< SPI master or slave */ uint32_t trans_mode; /*!< SPI transtype */ uint32_t frame_size; /*!< SPI frame size */ @@ -131,32 +157,39 @@ typedef struct uint32_t prescale; /*!< SPI prescale factor */ }spi_parameter_struct; -/* SPI struct parameter options */ +/* SPI mode definitions */ #define SPI_MASTER (SPI_CTL0_MSTMOD | SPI_CTL0_SWNSS) /*!< SPI as master */ #define SPI_SLAVE ((uint32_t)0x00000000U) /*!< SPI as slave */ -#define SPI_BIDIRECTIONAL_TEANSMIT SPI_CTL0_BDOEN /*!< SPI work in transmit-only mode */ -#define SPI_BIDIRECTIONAL_RECEIVE ~SPI_CTL0_BDOEN /*!< SPI work in receive-only mode */ +/* SPI bidirectional transfer direction */ +#define SPI_BIDIRECTIONAL_TRANSMIT SPI_CTL0_BDOEN /*!< SPI work in transmit-only mode */ +#define SPI_BIDIRECTIONAL_RECEIVE (~SPI_CTL0_BDOEN) /*!< SPI work in receive-only mode */ +/* SPI transmit type */ #define SPI_TRANSMODE_FULLDUPLEX ((uint32_t)0x00000000U) /*!< SPI receive and send data at fullduplex communication */ #define SPI_TRANSMODE_RECEIVEONLY SPI_CTL0_RO /*!< SPI only receive data */ #define SPI_TRANSMODE_BDRECEIVE SPI_CTL0_BDEN /*!< bidirectional receive data */ #define SPI_TRANSMODE_BDTRANSMIT (SPI_CTL0_BDEN | SPI_CTL0_BDOEN) /*!< bidirectional transmit data*/ +/* SPI frame size */ #define SPI_FRAMESIZE_16BIT SPI_CTL0_FF16 /*!< SPI frame size is 16 bits */ #define SPI_FRAMESIZE_8BIT ((uint32_t)0x00000000U) /*!< SPI frame size is 8 bits */ +/* SPI NSS control mode */ #define SPI_NSS_SOFT SPI_CTL0_SWNSSEN /*!< SPI nss control by sofrware */ #define SPI_NSS_HARD ((uint32_t)0x00000000U) /*!< SPI nss control by hardware */ -#define SPI_ENDIAN_MSB ((uint32_t)0x00000000U) /*!< SPI transmit way is big endian:transmit MSB first */ -#define SPI_ENDIAN_LSB SPI_CTL0_LF /*!< SPI transmit way is little endian:transmit LSB first */ +/* SPI transmit way */ +#define SPI_ENDIAN_MSB ((uint32_t)0x00000000U) /*!< SPI transmit way is big endian: transmit MSB first */ +#define SPI_ENDIAN_LSB SPI_CTL0_LF /*!< SPI transmit way is little endian: transmit LSB first */ +/* SPI clock polarity and phase */ #define SPI_CK_PL_LOW_PH_1EDGE ((uint32_t)0x00000000U) /*!< SPI clock polarity is low level and phase is first edge */ #define SPI_CK_PL_HIGH_PH_1EDGE SPI_CTL0_CKPL /*!< SPI clock polarity is high level and phase is first edge */ #define SPI_CK_PL_LOW_PH_2EDGE SPI_CTL0_CKPH /*!< SPI clock polarity is low level and phase is second edge */ #define SPI_CK_PL_HIGH_PH_2EDGE (SPI_CTL0_CKPL|SPI_CTL0_CKPH) /*!< SPI clock polarity is high level and phase is second edge */ +/* SPI clock prescale factor */ #define CTL0_PSC(regval) (BITS(3,5)&((uint32_t)(regval)<<3)) #define SPI_PSC_2 CTL0_PSC(0) /*!< SPI clock prescale factor is 2 */ #define SPI_PSC_4 CTL0_PSC(1) /*!< SPI clock prescale factor is 4 */ @@ -167,161 +200,180 @@ typedef struct #define SPI_PSC_128 CTL0_PSC(6) /*!< SPI clock prescale factor is 128 */ #define SPI_PSC_256 CTL0_PSC(7) /*!< SPI clock prescale factor is 256 */ -/* I2S parameter options */ -#define I2S_AUDIOSAMPLE_8K ((uint32_t)8000U) /*!< I2S audio sample rate is 8khz */ -#define I2S_AUDIOSAMPLE_11K ((uint32_t)11025U) /*!< I2S audio sample rate is 11khz */ -#define I2S_AUDIOSAMPLE_16K ((uint32_t)16000U) /*!< I2S audio sample rate is 16khz */ -#define I2S_AUDIOSAMPLE_22K ((uint32_t)22050U) /*!< I2S audio sample rate is 22khz */ -#define I2S_AUDIOSAMPLE_32K ((uint32_t)32000U) /*!< I2S audio sample rate is 32khz */ -#define I2S_AUDIOSAMPLE_44K ((uint32_t)44100U) /*!< I2S audio sample rate is 44khz */ -#define I2S_AUDIOSAMPLE_48K ((uint32_t)48000U) /*!< I2S audio sample rate is 48khz */ -#define I2S_AUDIOSAMPLE_96K ((uint32_t)96000U) /*!< I2S audio sample rate is 96khz */ -#define I2S_AUDIOSAMPLE_192K ((uint32_t)192000U) /*!< I2S audio sample rate is 192khz */ +/* I2S audio sample rate */ +#define I2S_AUDIOSAMPLE_8K ((uint32_t)8000U) /*!< I2S audio sample rate is 8KHz */ +#define I2S_AUDIOSAMPLE_11K ((uint32_t)11025U) /*!< I2S audio sample rate is 11KHz */ +#define I2S_AUDIOSAMPLE_16K ((uint32_t)16000U) /*!< I2S audio sample rate is 16KHz */ +#define I2S_AUDIOSAMPLE_22K ((uint32_t)22050U) /*!< I2S audio sample rate is 22KHz */ +#define I2S_AUDIOSAMPLE_32K ((uint32_t)32000U) /*!< I2S audio sample rate is 32KHz */ +#define I2S_AUDIOSAMPLE_44K ((uint32_t)44100U) /*!< I2S audio sample rate is 44KHz */ +#define I2S_AUDIOSAMPLE_48K ((uint32_t)48000U) /*!< I2S audio sample rate is 48KHz */ +#define I2S_AUDIOSAMPLE_96K ((uint32_t)96000U) /*!< I2S audio sample rate is 96KHz */ +#define I2S_AUDIOSAMPLE_192K ((uint32_t)192000U) /*!< I2S audio sample rate is 192KHz */ +/* I2S frame format */ #define I2SCTL_DTLEN(regval) (BITS(1,2)&((uint32_t)(regval)<<1)) #define I2S_FRAMEFORMAT_DT16B_CH16B I2SCTL_DTLEN(0) /*!< I2S data length is 16 bit and channel length is 16 bit */ #define I2S_FRAMEFORMAT_DT16B_CH32B (I2SCTL_DTLEN(0)|SPI_I2SCTL_CHLEN) /*!< I2S data length is 16 bit and channel length is 32 bit */ #define I2S_FRAMEFORMAT_DT24B_CH32B (I2SCTL_DTLEN(1)|SPI_I2SCTL_CHLEN) /*!< I2S data length is 24 bit and channel length is 32 bit */ #define I2S_FRAMEFORMAT_DT32B_CH32B (I2SCTL_DTLEN(2)|SPI_I2SCTL_CHLEN) /*!< I2S data length is 32 bit and channel length is 32 bit */ - + +/* I2S master clock output */ #define I2S_MCKOUT_DISABLE ((uint32_t)0x00000000U) /*!< I2S master clock output disable */ #define I2S_MCKOUT_ENABLE SPI_I2SPSC_MCKOEN /*!< I2S master clock output enable */ - + +/* I2S operation mode */ #define I2SCTL_I2SOPMOD(regval) (BITS(8,9)&((uint32_t)(regval)<<8)) #define I2S_MODE_SLAVETX I2SCTL_I2SOPMOD(0) /*!< I2S slave transmit mode */ #define I2S_MODE_SLAVERX I2SCTL_I2SOPMOD(1) /*!< I2S slave receive mode */ #define I2S_MODE_MASTERTX I2SCTL_I2SOPMOD(2) /*!< I2S master transmit mode */ #define I2S_MODE_MASTERRX I2SCTL_I2SOPMOD(3) /*!< I2S master receive mode */ +/* I2S standard */ #define I2SCTL_I2SSTD(regval) (BITS(4,5)&((uint32_t)(regval)<<4)) #define I2S_STD_PHILLIPS I2SCTL_I2SSTD(0) /*!< I2S phillips standard */ #define I2S_STD_MSB I2SCTL_I2SSTD(1) /*!< I2S MSB standard */ #define I2S_STD_LSB I2SCTL_I2SSTD(2) /*!< I2S LSB standard */ #define I2S_STD_PCMSHORT I2SCTL_I2SSTD(3) /*!< I2S PCM short standard */ -#define I2S_STD_PCMLONG (I2SCTL_I2SSTD(3)|SPI_I2SCTL_PCMSMOD) /*!< I2S PCM long standard */ +#define I2S_STD_PCMLONG (I2SCTL_I2SSTD(3) | SPI_I2SCTL_PCMSMOD) /*!< I2S PCM long standard */ +/* I2S clock polarity */ #define I2S_CKPL_LOW ((uint32_t)0x00000000U) /*!< I2S clock polarity low level */ #define I2S_CKPL_HIGH SPI_I2SCTL_CKPL /*!< I2S clock polarity high level */ -/* SPI dma constants definitions */ -#define SPI_DMA_TRANSMIT ((uint8_t)0x00U) /*!< SPI transmit data DMA */ -#define SPI_DMA_RECEIVE ((uint8_t)0x01U) /*!< SPI receive data DMA */ +/* SPI DMA constants definitions */ +#define SPI_DMA_TRANSMIT ((uint8_t)0x00U) /*!< SPI transmit data use DMA */ +#define SPI_DMA_RECEIVE ((uint8_t)0x01U) /*!< SPI receive data use DMA */ /* SPI CRC constants definitions */ #define SPI_CRC_TX ((uint8_t)0x00U) /*!< SPI transmit CRC value */ #define SPI_CRC_RX ((uint8_t)0x01U) /*!< SPI receive CRC value */ -/* SPI interrupt constants definitions */ +/* SPI/I2S interrupt enable/disable constants definitions */ #define SPI_I2S_INT_TBE ((uint8_t)0x00U) /*!< transmit buffer empty interrupt */ #define SPI_I2S_INT_RBNE ((uint8_t)0x01U) /*!< receive buffer not empty interrupt */ -#define SPI_I2S_INT_RXORERR ((uint8_t)0x02U) /*!< overrun interrupt */ -#define SPI_INT_CONFERR ((uint8_t)0x03U) /*!< config error interrupt */ -#define SPI_INT_CRCERR ((uint8_t)0x04U) /*!< CRC error interrupt */ -#define I2S_INT_TXURERR ((uint8_t)0x05U) /*!< underrun error interrupt */ -#define SPI_I2S_INT_ERR ((uint8_t)0x06U) /*!< error interrupt */ -#define SPI_I2S_INT_FERR ((uint8_t)0x07U) /*!< format error interrupt */ +#define SPI_I2S_INT_ERR ((uint8_t)0x02U) /*!< error interrupt */ -/* SPI flag definitions */ +/* SPI/I2S interrupt flag constants definitions */ +#define SPI_I2S_INT_FLAG_TBE ((uint8_t)0x00U) /*!< transmit buffer empty interrupt flag */ +#define SPI_I2S_INT_FLAG_RBNE ((uint8_t)0x01U) /*!< receive buffer not empty interrupt flag */ +#define SPI_I2S_INT_FLAG_RXORERR ((uint8_t)0x02U) /*!< overrun interrupt flag */ +#define SPI_INT_FLAG_CONFERR ((uint8_t)0x03U) /*!< config error interrupt flag */ +#define SPI_INT_FLAG_CRCERR ((uint8_t)0x04U) /*!< CRC error interrupt flag */ +#define I2S_INT_FLAG_TXURERR ((uint8_t)0x05U) /*!< underrun error interrupt flag */ +#define SPI_I2S_INT_FLAG_FERR ((uint8_t)0x06U) /*!< format error interrupt flag */ + +/* SPI/I2S flag definitions */ #define SPI_FLAG_RBNE SPI_STAT_RBNE /*!< receive buffer not empty flag */ #define SPI_FLAG_TBE SPI_STAT_TBE /*!< transmit buffer empty flag */ #define SPI_FLAG_CRCERR SPI_STAT_CRCERR /*!< CRC error flag */ #define SPI_FLAG_CONFERR SPI_STAT_CONFERR /*!< mode config error flag */ -#define SPI_FLAG_RXORERR SPI_STAT_RXORERR /*!< receive overrun flag */ +#define SPI_FLAG_RXORERR SPI_STAT_RXORERR /*!< receive overrun error flag */ #define SPI_FLAG_TRANS SPI_STAT_TRANS /*!< transmit on-going flag */ -#define SPI_FLAG_FERR SPI_STAT_FERR /*!< format error interrupt flag */ +#define SPI_FLAG_FERR SPI_STAT_FERR /*!< format error flag */ #define I2S_FLAG_RBNE SPI_STAT_RBNE /*!< receive buffer not empty flag */ #define I2S_FLAG_TBE SPI_STAT_TBE /*!< transmit buffer empty flag */ -#define I2S_FLAG_CH SPI_STAT_I2SCH /*!< transmit buffer empty interrupt */ +#define I2S_FLAG_CH SPI_STAT_I2SCH /*!< channel side flag */ #define I2S_FLAG_TXURERR SPI_STAT_TXURERR /*!< underrun error flag */ -#define I2S_FLAG_RXORERR SPI_STAT_RXORERR /*!< overrun flag */ +#define I2S_FLAG_RXORERR SPI_STAT_RXORERR /*!< overrun error flag */ #define I2S_FLAG_TRANS SPI_STAT_TRANS /*!< transmit on-going flag */ -#define I2S_FLAG_FERR SPI_STAT_FERR /*!< format error interrupt flag */ +#define I2S_FLAG_FERR SPI_STAT_FERR /*!< format error flag */ /* function declarations */ -/* SPI and I2S reset */ +/* initialization functions */ +/* deinitialize SPI and I2S */ void spi_i2s_deinit(uint32_t spi_periph); -/* SPI parameter initialization */ +/* initialize the parameters of SPI struct with the default values */ +void spi_struct_para_init(spi_parameter_struct* spi_struct); +/* initialize SPI parameter */ void spi_init(uint32_t spi_periph,spi_parameter_struct* spi_struct); -/* SPI enable */ +/* enable SPI */ void spi_enable(uint32_t spi_periph); -/* SPI disable */ +/* disable SPI */ void spi_disable(uint32_t spi_periph); -/* I2S parameter initialization */ +/* initialize I2S parameter */ void i2s_init(uint32_t spi_periph,uint32_t i2s_mode,uint32_t i2s_standard,uint32_t i2s_ckpl); -/* I2S prescale configuration */ +/* configure I2S prescale */ void i2s_psc_config(uint32_t spi_periph,uint32_t i2s_audiosample,uint32_t i2s_frameformat,uint32_t i2s_mckout); -/* I2S enable */ +/* enable I2S */ void i2s_enable(uint32_t spi_periph); -/* I2S disable */ +/* disable I2S */ void i2s_disable(uint32_t spi_periph); -/* SPI nss output enable */ +/* NSS functions */ +/* enable SPI nss output */ void spi_nss_output_enable(uint32_t spi_periph); -/* SPI nss output disable */ +/* disable SPI nss output */ void spi_nss_output_disable(uint32_t spi_periph); /* SPI nss pin high level in software mode */ void spi_nss_internal_high(uint32_t spi_periph); /* SPI nss pin low level in software mode */ void spi_nss_internal_low(uint32_t spi_periph); -/* SPI dma enable */ +/* SPI DMA functions */ +/* enable SPI DMA */ void spi_dma_enable(uint32_t spi_periph,uint8_t spi_dma); -/* SPI dma disable */ +/* disable SPI DMA */ void spi_dma_disable(uint32_t spi_periph,uint8_t spi_dma); +/* SPI/I2S transfer configure functions */ /* configure SPI/I2S data frame format */ void spi_i2s_data_frame_format_config(uint32_t spi_periph,uint16_t frame_format); -/* transmit data */ +/* SPI transmit data */ void spi_i2s_data_transmit(uint32_t spi_periph,uint16_t data); -/* receive data */ +/* SPI receive data */ uint16_t spi_i2s_data_receive(uint32_t spi_periph); /* configure SPI bidirectional transfer direction */ void spi_bidirectional_transfer_config(uint32_t spi_periph,uint32_t transfer_direction); -/* enable SPI interrupt */ -void spi_i2s_interrupt_enable(uint32_t spi_periph,uint8_t spi_i2s_int); -/* disable SPI interrupt */ -void spi_i2s_interrupt_disable(uint32_t spi_periph,uint8_t spi_i2s_int); -/* get SPI and I2S interrupt status*/ -FlagStatus spi_i2s_interrupt_flag_get(uint32_t spi_periph,uint8_t spi_i2s_int); -/* get SPI and I2S flag status */ -FlagStatus spi_i2s_flag_get(uint32_t spi_periph,uint32_t spi_i2s_flag); -/* clear SPI CRC error flag status */ -void spi_crc_error_clear(uint32_t spi_periph); - -/* SPI CRC polynomial set */ +/* SPI CRC functions */ +/* set SPI CRC polynomial */ void spi_crc_polynomial_set(uint32_t spi_periph,uint16_t crc_poly); -/* SPI CRC polynomial get */ +/* get SPI CRC polynomial */ uint16_t spi_crc_polynomial_get(uint32_t spi_periph); -/* SPI CRC function turn on */ +/* turn on SPI CRC function */ void spi_crc_on(uint32_t spi_periph); -/* SPI CRC function turn off */ +/* turn off SPI CRC function */ void spi_crc_off(uint32_t spi_periph); /* SPI next data is CRC value */ void spi_crc_next(uint32_t spi_periph); /* get SPI CRC send value or receive value */ uint16_t spi_crc_get(uint32_t spi_periph,uint8_t spi_crc); -/* SPI TI mode enable */ +/* SPI TI mode functions */ +/* enable SPI TI mode */ void spi_ti_mode_enable(uint32_t spi_periph); -/* SPI TI mode disable */ +/* disable SPI TI mode */ void spi_ti_mode_disable(uint32_t spi_periph); /* configure i2s full duplex mode */ void i2s_full_duplex_mode_config(uint32_t i2s_add_periph,uint32_t i2s_mode,uint32_t i2s_standard,uint32_t i2s_ckpl,uint32_t i2s_frameformat); -/* quad wire SPI enable */ +/* quad wire SPI functions */ +/* enable quad wire SPI */ void qspi_enable(uint32_t spi_periph); -/* quad wire SPI disable */ +/* disable quad wire SPI */ void qspi_disable(uint32_t spi_periph); -/* quad wire SPI write enable */ +/* enable quad wire SPI write */ void qspi_write_enable(uint32_t spi_periph); -/* quad wire SPI read enable */ +/* enable quad wire SPI read */ void qspi_read_enable(uint32_t spi_periph); -/* quad wire SPI_IO2 and SPI_IO3 pin output enable */ +/* enable quad wire SPI_IO2 and SPI_IO3 pin output */ void qspi_io23_output_enable(uint32_t spi_periph); -/* quad wire SPI_IO2 and SPI_IO3 pin output disable */ +/* disable quad wire SPI_IO2 and SPI_IO3 pin output */ void qspi_io23_output_disable(uint32_t spi_periph); +/* flag & interrupt functions */ +/* enable SPI interrupt */ +void spi_i2s_interrupt_enable(uint32_t spi_periph,uint8_t spi_i2s_int); +/* disable SPI interrupt */ +void spi_i2s_interrupt_disable(uint32_t spi_periph,uint8_t spi_i2s_int); +/* get SPI and I2S interrupt status*/ +FlagStatus spi_i2s_interrupt_flag_get(uint32_t spi_periph,uint8_t spi_i2s_int); +/* get SPI and I2S flag status */ +FlagStatus spi_i2s_flag_get(uint32_t spi_periph,uint32_t spi_i2s_flag); +/* clear SPI CRC error flag status */ +void spi_crc_error_clear(uint32_t spi_periph); + #endif /* GD32F4XX_SPI_H */ diff --git a/bsp/gd32450z-eval/Libraries/GD32F4xx_standard_peripheral/Include/gd32f4xx_syscfg.h b/bsp/gd32450z-eval/Libraries/GD32F4xx_standard_peripheral/Include/gd32f4xx_syscfg.h index 42ae5599c7..047910478a 100644 --- a/bsp/gd32450z-eval/Libraries/GD32F4xx_standard_peripheral/Include/gd32f4xx_syscfg.h +++ b/bsp/gd32450z-eval/Libraries/GD32F4xx_standard_peripheral/Include/gd32f4xx_syscfg.h @@ -1,12 +1,37 @@ /*! - \file gd32f4xx_syscfg.h - \brief definitions for the SYSCFG + \file gd32f4xx_syscfg.h + \brief definitions for the SYSCFG + + \version 2016-08-15, V1.0.0, firmware for GD32F4xx + \version 2018-12-12, V2.0.0, firmware for GD32F4xx + \version 2020-09-30, V2.1.0, firmware for GD32F4xx */ /* - Copyright (C) 2016 GigaDevice + Copyright (c) 2020, GigaDevice Semiconductor Inc. + + Redistribution and use in source and binary forms, with or without modification, +are permitted provided that the following conditions are met: - 2016-08-15, V1.0.0, firmware for GD32F4xx + 1. Redistributions of source code must retain the above copyright notice, this + list of conditions and the following disclaimer. + 2. Redistributions in binary form must reproduce the above copyright notice, + this list of conditions and the following disclaimer in the documentation + and/or other materials provided with the distribution. + 3. Neither the name of the copyright holder nor the names of its contributors + may be used to endorse or promote products derived from this software without + specific prior written permission. + + THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED +WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. +IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, +INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT +NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR +PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, +WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY +OF SUCH DAMAGE. */ #ifndef GD32F4XX_SYSCFG_H @@ -85,13 +110,13 @@ #define EXTISS3 ((uint8_t)0x03U) /*!< EXTI source select GPIOx pin 12~15 */ /* EXTI source select mask bits definition */ -#define EXTI_SS_MASK BITS(0,3) +#define EXTI_SS_MASK BITS(0,3) /*!< EXTI source select mask */ /* EXTI source select jumping step definition */ -#define EXTI_SS_JSTEP ((uint8_t)(0x04U)) +#define EXTI_SS_JSTEP ((uint8_t)(0x04U)) /*!< EXTI source select jumping step */ /* EXTI source select moving step definition */ -#define EXTI_SS_MSTEP(pin) (EXTI_SS_JSTEP*((pin)%EXTI_SS_JSTEP)) +#define EXTI_SS_MSTEP(pin) (EXTI_SS_JSTEP*((pin)%EXTI_SS_JSTEP)) /*!< EXTI source select moving step */ /* EXTI source port definitions */ #define EXTI_SOURCE_GPIOA ((uint8_t)0x00U) /*!< EXTI GPIOA configuration */ @@ -123,35 +148,33 @@ #define EXTI_SOURCE_PIN15 ((uint8_t)0x0FU) /*!< EXTI GPIO pin15 configuration */ /* ethernet PHY selection */ -#define SYSCFG_ENET_PHY_MII ((uint32_t)0x00000000U) -#define SYSCFG_ENET_PHY_RMII ((uint32_t)0x00800000U) +#define SYSCFG_ENET_PHY_MII ((uint32_t)0x00000000U) /*!< MII is selected for the Ethernet MAC */ +#define SYSCFG_ENET_PHY_RMII ((uint32_t)0x00800000U) /*!< RMII is selected for the Ethernet MAC */ /* I/O compensation cell enable/disable */ -#define SYSCFG_COMPENSATION_ENABLE ((uint32_t)0x00000001U) -#define SYSCFG_COMPENSATION_DISABLE ((uint32_t)0x00000000U) +#define SYSCFG_COMPENSATION_ENABLE ((uint32_t)0x00000001U) /*!< I/O compensation cell enable */ +#define SYSCFG_COMPENSATION_DISABLE ((uint32_t)0x00000000U) /*!< I/O compensation cell disable */ /* function declarations */ +/* initialization functions */ /* deinit syscfg module */ void syscfg_deinit(void); +/* function configuration */ /* configure the boot mode */ void syscfg_bootmode_config(uint8_t syscfg_bootmode); - -/* FMC memory mapping swap */ +/* configure FMC memory mapping swap */ void syscfg_fmc_swap_config(uint32_t syscfg_fmc_swap); - /* configure the EXMC swap */ -void syscfg_exmc_swap_config(uint32_t syscfg_exmc_swap); - +void syscfg_exmc_swap_config(uint32_t syscfg_exmc_swap); /* configure the GPIO pin as EXTI Line */ void syscfg_exti_line_config(uint8_t exti_port, uint8_t exti_pin); - /* configure the PHY interface for the ethernet MAC */ void syscfg_enet_phy_interface_config(uint32_t syscfg_enet_phy_interface); - /* configure the I/O compensation cell */ -void syscfg_compensation_config(uint32_t syscfg_compensation); +void syscfg_compensation_config(uint32_t syscfg_compensation); +/* interrupt & flag functions */ /* check the I/O compensation cell is ready or not */ FlagStatus syscfg_flag_get(void); diff --git a/bsp/gd32450z-eval/Libraries/GD32F4xx_standard_peripheral/Include/gd32f4xx_timer.h b/bsp/gd32450z-eval/Libraries/GD32F4xx_standard_peripheral/Include/gd32f4xx_timer.h index e856ec03ac..9da6e12bdd 100644 --- a/bsp/gd32450z-eval/Libraries/GD32F4xx_standard_peripheral/Include/gd32f4xx_timer.h +++ b/bsp/gd32450z-eval/Libraries/GD32F4xx_standard_peripheral/Include/gd32f4xx_timer.h @@ -1,12 +1,38 @@ /*! - \file gd32f4xx_timer.h - \brief definitions for the TIMER + \file gd32f4xx_timer.h + \brief definitions for the TIMER + + \version 2016-08-15, V1.0.0, firmware for GD32F4xx + \version 2018-12-12, V2.0.0, firmware for GD32F4xx + \version 2020-09-30, V2.1.0, firmware for GD32F4xx */ /* - Copyright (C) 2016 GigaDevice + Copyright (c) 2020, GigaDevice Semiconductor Inc. + All rights reserved. + + Redistribution and use in source and binary forms, with or without modification, +are permitted provided that the following conditions are met: + + 1. Redistributions of source code must retain the above copyright notice, this + list of conditions and the following disclaimer. + 2. Redistributions in binary form must reproduce the above copyright notice, + this list of conditions and the following disclaimer in the documentation + and/or other materials provided with the distribution. + 3. Neither the name of the copyright holder nor the names of its contributors + may be used to endorse or promote products derived from this software without + specific prior written permission. - 2016-08-15, V1.0.0, firmware for GD32F4xx + THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED +WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. +IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, +INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT +NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR +PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, +WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY +OF SUCH DAMAGE. */ #ifndef GD32F4XX_TIMER_H @@ -66,8 +92,8 @@ #define TIMER_CTL0_CKDIV BITS(8,9) /*!< clock division */ /* TIMER_CTL1 */ -#define TIMER_CTL1_CCSE BIT(0) /*!< capture/compare control shadow register enable */ -#define TIMER_CTL1_CCUC BIT(2) /*!< capture/compare control shadow register update control */ +#define TIMER_CTL1_CCSE BIT(0) /*!< commutation control shadow enable */ +#define TIMER_CTL1_CCUC BIT(2) /*!< commutation control shadow register update control */ #define TIMER_CTL1_DMAS BIT(3) /*!< DMA request source selection */ #define TIMER_CTL1_MMC BITS(4,6) /*!< master mode control */ #define TIMER_CTL1_TI0S BIT(7) /*!< channel 0 trigger input selection(hall mode selection) */ @@ -87,30 +113,30 @@ #define TIMER_SMCFG_ETPSC BITS(12,13) /*!< external trigger prescaler */ #define TIMER_SMCFG_SMC1 BIT(14) /*!< part of SMC for enable external clock mode 1 */ #define TIMER_SMCFG_ETP BIT(15) /*!< external trigger polarity */ - + /* TIMER_DMAINTEN */ #define TIMER_DMAINTEN_UPIE BIT(0) /*!< update interrupt enable */ -#define TIMER_DMAINTEN_CH0IE BIT(1) /*!< channel 0 interrupt enable */ -#define TIMER_DMAINTEN_CH1IE BIT(2) /*!< channel 1 interrupt enable */ -#define TIMER_DMAINTEN_CH2IE BIT(3) /*!< channel 2 interrupt enable */ -#define TIMER_DMAINTEN_CH3IE BIT(4) /*!< channel 3 interrupt enable */ -#define TIMER_DMAINTEN_CMTIE BIT(5) /*!< commutation DMA request enable */ +#define TIMER_DMAINTEN_CH0IE BIT(1) /*!< channel 0 capture/compare interrupt enable */ +#define TIMER_DMAINTEN_CH1IE BIT(2) /*!< channel 1 capture/compare interrupt enable */ +#define TIMER_DMAINTEN_CH2IE BIT(3) /*!< channel 2 capture/compare interrupt enable */ +#define TIMER_DMAINTEN_CH3IE BIT(4) /*!< channel 3 capture/compare interrupt enable */ +#define TIMER_DMAINTEN_CMTIE BIT(5) /*!< commutation interrupt request enable */ #define TIMER_DMAINTEN_TRGIE BIT(6) /*!< trigger interrupt enable */ #define TIMER_DMAINTEN_BRKIE BIT(7) /*!< break interrupt enable */ #define TIMER_DMAINTEN_UPDEN BIT(8) /*!< update DMA request enable */ -#define TIMER_DMAINTEN_CH0DEN BIT(8) /*!< channel 0 DMA request enable */ +#define TIMER_DMAINTEN_CH0DEN BIT(9) /*!< channel 0 DMA request enable */ #define TIMER_DMAINTEN_CH1DEN BIT(10) /*!< channel 1 DMA request enable */ #define TIMER_DMAINTEN_CH2DEN BIT(11) /*!< channel 2 DMA request enable */ #define TIMER_DMAINTEN_CH3DEN BIT(12) /*!< channel 3 DMA request enable */ -#define TIMER_DMAINTEN_CMTDEN BIT(13) /*!< channel control update DMA request enable */ +#define TIMER_DMAINTEN_CMTDEN BIT(13) /*!< commutation DMA request enable */ #define TIMER_DMAINTEN_TRGDEN BIT(14) /*!< trigger DMA request enable */ /* TIMER_INTF */ #define TIMER_INTF_UPIF BIT(0) /*!< update interrupt flag */ -#define TIMER_INTF_CH0IF BIT(1) /*!< channel 0 interrupt flag */ -#define TIMER_INTF_CH1IF BIT(2) /*!< channel 1 interrupt flag */ -#define TIMER_INTF_CH2IF BIT(3) /*!< channel 2 interrupt flag */ -#define TIMER_INTF_CH3IF BIT(4) /*!< channel 3 interrupt flag */ +#define TIMER_INTF_CH0IF BIT(1) /*!< channel 0 capture/compare interrupt flag */ +#define TIMER_INTF_CH1IF BIT(2) /*!< channel 1 capture/compare interrupt flag */ +#define TIMER_INTF_CH2IF BIT(3) /*!< channel 2 capture/compare interrupt flag */ +#define TIMER_INTF_CH3IF BIT(4) /*!< channel 3 capture/compare interrupt flag */ #define TIMER_INTF_CMTIF BIT(5) /*!< channel commutation interrupt flag */ #define TIMER_INTF_TRGIF BIT(6) /*!< trigger interrupt flag */ #define TIMER_INTF_BRKIF BIT(7) /*!< break interrupt flag */ @@ -166,20 +192,20 @@ #define TIMER_CHCTL1_CH3CAPFLT BITS(12,15) /*!< channel 3 input capture filter control */ /* TIMER_CHCTL2 */ -#define TIMER_CHCTL2_CH0EN BIT(0) /*!< channel 0 enable */ -#define TIMER_CHCTL2_CH0P BIT(1) /*!< channel 0 polarity */ +#define TIMER_CHCTL2_CH0EN BIT(0) /*!< channel 0 capture/compare function enable */ +#define TIMER_CHCTL2_CH0P BIT(1) /*!< channel 0 capture/compare function polarity */ #define TIMER_CHCTL2_CH0NEN BIT(2) /*!< channel 0 complementary output enable */ #define TIMER_CHCTL2_CH0NP BIT(3) /*!< channel 0 complementary output polarity */ -#define TIMER_CHCTL2_CH1EN BIT(4) /*!< channel 1 enable */ -#define TIMER_CHCTL2_CH1P BIT(5) /*!< channel 1 polarity */ +#define TIMER_CHCTL2_CH1EN BIT(4) /*!< channel 1 capture/compare function enable */ +#define TIMER_CHCTL2_CH1P BIT(5) /*!< channel 1 capture/compare function polarity */ #define TIMER_CHCTL2_CH1NEN BIT(6) /*!< channel 1 complementary output enable */ #define TIMER_CHCTL2_CH1NP BIT(7) /*!< channel 1 complementary output polarity */ -#define TIMER_CHCTL2_CH2EN BIT(8) /*!< channel 2 enable */ -#define TIMER_CHCTL2_CH2P BIT(9) /*!< channel 2 polarity */ +#define TIMER_CHCTL2_CH2EN BIT(8) /*!< channel 2 capture/compare function enable */ +#define TIMER_CHCTL2_CH2P BIT(9) /*!< channel 2 capture/compare function polarity */ #define TIMER_CHCTL2_CH2NEN BIT(10) /*!< channel 2 complementary output enable */ #define TIMER_CHCTL2_CH2NP BIT(11) /*!< channel 2 complementary output polarity */ -#define TIMER_CHCTL2_CH3EN BIT(12) /*!< channel 3 enable */ -#define TIMER_CHCTL2_CH3P BIT(13) /*!< channel 3 polarity */ +#define TIMER_CHCTL2_CH3EN BIT(12) /*!< channel 3 capture/compare function enable */ +#define TIMER_CHCTL2_CH3P BIT(13) /*!< channel 3 capture/compare function polarity */ /* TIMER_CNT */ #define TIMER_CNT_CNT16 BITS(0,15) /*!< 16 bit timer counter */ @@ -200,16 +226,16 @@ #define TIMER_CH0CV_CH0VAL32 BITS(0,31) /*!< 32 bit(TIMER1,TIMER4) capture/compare value of channel 0 */ /* TIMER_CH1CV */ -#define TIMER_CH1CV_CH0VAL16 BITS(0,15) /*!< 16 bit capture/compare value of channel 1 */ -#define TIMER_CH1CV_CH0VAL32 BITS(0,31) /*!< 32 bit(TIMER1,TIMER4) capture/compare value of channel 1 */ +#define TIMER_CH1CV_CH1VAL16 BITS(0,15) /*!< 16 bit capture/compare value of channel 1 */ +#define TIMER_CH1CV_CH1VAL32 BITS(0,31) /*!< 32 bit(TIMER1,TIMER4) capture/compare value of channel 1 */ /* TIMER_CH2CV */ -#define TIMER_CH2CV_CH0VAL16 BITS(0,15) /*!< 16 bit capture/compare value of channel 2 */ -#define TIMER_CH2CV_CH0VAL32 BITS(0,31) /*!< 32 bit(TIMER1,TIMER4) capture/compare value of channel 2 */ +#define TIMER_CH2CV_CH2VAL16 BITS(0,15) /*!< 16 bit capture/compare value of channel 2 */ +#define TIMER_CH2CV_CH2VAL32 BITS(0,31) /*!< 32 bit(TIMER1,TIMER4) capture/compare value of channel 2 */ /* TIMER_CH3CV */ -#define TIMER_CH3CV_CH0VAL16 BITS(0,15) /*!< 16 bit capture/compare value of channel 3 */ -#define TIMER_CH3CV_CH0VAL32 BITS(0,31) /*!< 32 bit(TIMER1,TIMER4) capture/compare value of channel 3 */ +#define TIMER_CH3CV_CH3VAL16 BITS(0,15) /*!< 16 bit capture/compare value of channel 3 */ +#define TIMER_CH3CV_CH3VAL32 BITS(0,31) /*!< 32 bit(TIMER1,TIMER4) capture/compare value of channel 3 */ /* TIMER_CCHP */ #define TIMER_CCHP_DTCFG BITS(0,7) /*!< dead time configure */ @@ -240,31 +266,31 @@ /* constants definitions */ /* TIMER init parameter struct definitions*/ typedef struct -{ +{ uint16_t prescaler; /*!< prescaler value */ uint16_t alignedmode; /*!< aligned mode */ uint16_t counterdirection; /*!< counter direction */ - uint32_t period; /*!< period value */ uint16_t clockdivision; /*!< clock division value */ + uint32_t period; /*!< period value */ uint8_t repetitioncounter; /*!< the counter repetition value */ }timer_parameter_struct; /* break parameter struct definitions*/ typedef struct -{ - uint16_t runoffstate; /*!< run mode off-state */ - uint32_t ideloffstate; /*!< idle mode off-state */ - uint16_t deadtime; /*!< delay time between the switching off and on of the outputs */ +{ + uint16_t runoffstate; /*!< run mode off-state */ + uint16_t ideloffstate; /*!< idle mode off-state */ + uint16_t deadtime; /*!< dead time */ uint16_t breakpolarity; /*!< break polarity */ - uint16_t outputautostate; /*!< output automatic enable */ - uint16_t protectmode; /*!< complementary register protect control */ - uint16_t breakstate; /*!< break enable */ + uint16_t outputautostate; /*!< output automatic enable */ + uint16_t protectmode; /*!< complementary register protect control */ + uint16_t breakstate; /*!< break enable */ }timer_break_parameter_struct; /* channel output parameter struct definitions */ typedef struct -{ - uint32_t outputstate; /*!< channel output state */ +{ + uint16_t outputstate; /*!< channel output state */ uint16_t outputnstate; /*!< channel complementary output state */ uint16_t ocpolarity; /*!< channel output polarity */ uint16_t ocnpolarity; /*!< channel complementary output polarity */ @@ -274,47 +300,59 @@ typedef struct /* channel input parameter struct definitions */ typedef struct -{ +{ uint16_t icpolarity; /*!< channel input polarity */ uint16_t icselection; /*!< channel input mode selection */ uint16_t icprescaler; /*!< channel input capture prescaler */ uint16_t icfilter; /*!< channel input capture filter control */ }timer_ic_parameter_struct; -/* TIMER interrupt source */ -#define TIMER_INT_UP ((uint32_t)0x00000001U) /*!< update interrupt */ -#define TIMER_INT_CH0 ((uint32_t)0x00000002U) /*!< channel 0 interrupt */ -#define TIMER_INT_CH1 ((uint32_t)0x00000004U) /*!< channel 1 interrupt */ -#define TIMER_INT_CH2 ((uint32_t)0x00000008U) /*!< channel 2 interrupt */ -#define TIMER_INT_CH3 ((uint32_t)0x00000010U) /*!< channel 3 interrupt */ -#define TIMER_INT_CMT ((uint32_t)0x00000020U) /*!< channel commutation interrupt flag */ -#define TIMER_INT_TRG ((uint32_t)0x00000040U) /*!< trigger interrupt */ -#define TIMER_INT_BRK ((uint32_t)0x00000080U) /*!< break interrupt */ +/* TIMER interrupt enable or disable */ +#define TIMER_INT_UP TIMER_DMAINTEN_UPIE /*!< update interrupt */ +#define TIMER_INT_CH0 TIMER_DMAINTEN_CH0IE /*!< channel 0 interrupt */ +#define TIMER_INT_CH1 TIMER_DMAINTEN_CH1IE /*!< channel 1 interrupt */ +#define TIMER_INT_CH2 TIMER_DMAINTEN_CH2IE /*!< channel 2 interrupt */ +#define TIMER_INT_CH3 TIMER_DMAINTEN_CH3IE /*!< channel 3 interrupt */ +#define TIMER_INT_CMT TIMER_DMAINTEN_CMTIE /*!< channel commutation interrupt flag */ +#define TIMER_INT_TRG TIMER_DMAINTEN_TRGIE /*!< trigger interrupt */ +#define TIMER_INT_BRK TIMER_DMAINTEN_BRKIE /*!< break interrupt */ /* TIMER flag */ -#define TIMER_FLAG_UP ((uint32_t)0x00000001U) /*!< update flag */ -#define TIMER_FLAG_CH0 ((uint32_t)0x00000002U) /*!< channel 0 flag */ -#define TIMER_FLAG_CH1 ((uint32_t)0x00000004U) /*!< channel 1 flag */ -#define TIMER_FLAG_CH2 ((uint32_t)0x00000008U) /*!< channel 2 flag */ -#define TIMER_FLAG_CH3 ((uint32_t)0x00000010U) /*!< channel 3 flag */ -#define TIMER_FLAG_CMT ((uint32_t)0x00000020U) /*!< channel control update flag */ -#define TIMER_FLAG_TRG ((uint32_t)0x00000040U) /*!< trigger flag */ -#define TIMER_FLAG_BRK ((uint32_t)0x00000080U) /*!< break flag */ -#define TIMER_FLAG_CH0OF ((uint32_t)0x00000200U) /*!< channel 0 overcapture flag */ -#define TIMER_FLAG_CH1OF ((uint32_t)0x00000400U) /*!< channel 1 overcapture flag */ -#define TIMER_FLAG_CH2OF ((uint32_t)0x00000800U) /*!< channel 2 overcapture flag */ -#define TIMER_FLAG_CH3OF ((uint32_t)0x00001000U) /*!< channel 3 overcapture flag */ +#define TIMER_FLAG_UP TIMER_INTF_UPIF /*!< update flag */ +#define TIMER_FLAG_CH0 TIMER_INTF_CH0IF /*!< channel 0 flag */ +#define TIMER_FLAG_CH1 TIMER_INTF_CH1IF /*!< channel 1 flag */ +#define TIMER_FLAG_CH2 TIMER_INTF_CH2IF /*!< channel 2 flag */ +#define TIMER_FLAG_CH3 TIMER_INTF_CH3IF /*!< channel 3 flag */ +#define TIMER_FLAG_CMT TIMER_INTF_CMTIF /*!< channel commutation flag */ +#define TIMER_FLAG_TRG TIMER_INTF_TRGIF /*!< trigger flag */ +#define TIMER_FLAG_BRK TIMER_INTF_BRKIF /*!< break flag */ +#define TIMER_FLAG_CH0O TIMER_INTF_CH0OF /*!< channel 0 overcapture flag */ +#define TIMER_FLAG_CH1O TIMER_INTF_CH1OF /*!< channel 1 overcapture flag */ +#define TIMER_FLAG_CH2O TIMER_INTF_CH2OF /*!< channel 2 overcapture flag */ +#define TIMER_FLAG_CH3O TIMER_INTF_CH3OF /*!< channel 3 overcapture flag */ + +/* TIMER interrupt flag */ +#define TIMER_INT_FLAG_UP TIMER_INTF_UPIF /*!< update interrupt flag */ +#define TIMER_INT_FLAG_CH0 TIMER_INTF_CH0IF /*!< channel 0 interrupt flag */ +#define TIMER_INT_FLAG_CH1 TIMER_INTF_CH1IF /*!< channel 1 interrupt flag */ +#define TIMER_INT_FLAG_CH2 TIMER_INTF_CH2IF /*!< channel 2 interrupt flag */ +#define TIMER_INT_FLAG_CH3 TIMER_INTF_CH3IF /*!< channel 3 interrupt flag */ +#define TIMER_INT_FLAG_CMT TIMER_INTF_CMTIF /*!< channel commutation interrupt flag */ +#define TIMER_INT_FLAG_TRG TIMER_INTF_TRGIF /*!< trigger interrupt flag */ +#define TIMER_INT_FLAG_BRK TIMER_INTF_BRKIF + + /* TIMER DMA source enable */ -#define TIMER_DMA_UPD ((uint16_t)0x0100U) /*!< update DMA enable */ -#define TIMER_DMA_CH0D ((uint16_t)0x0200U) /*!< channel 0 DMA enable */ -#define TIMER_DMA_CH1D ((uint16_t)0x0400U) /*!< channel 1 DMA enable */ -#define TIMER_DMA_CH2D ((uint16_t)0x0800U) /*!< channel 2 DMA enable */ -#define TIMER_DMA_CH3D ((uint16_t)0x1000U) /*!< channel 3 DMA enable */ -#define TIMER_DMA_CMTD ((uint16_t)0x2000U) /*!< commutation DMA request enable */ -#define TIMER_DMA_TRGD ((uint16_t)0x4000U) /*!< trigger DMA enable */ +#define TIMER_DMA_UPD ((uint16_t)TIMER_DMAINTEN_UPDEN) /*!< update DMA enable */ +#define TIMER_DMA_CH0D ((uint16_t)TIMER_DMAINTEN_CH0DEN) /*!< channel 0 DMA enable */ +#define TIMER_DMA_CH1D ((uint16_t)TIMER_DMAINTEN_CH1DEN) /*!< channel 1 DMA enable */ +#define TIMER_DMA_CH2D ((uint16_t)TIMER_DMAINTEN_CH2DEN) /*!< channel 2 DMA enable */ +#define TIMER_DMA_CH3D ((uint16_t)TIMER_DMAINTEN_CH3DEN) /*!< channel 3 DMA enable */ +#define TIMER_DMA_CMTD ((uint16_t)TIMER_DMAINTEN_CMTDEN) /*!< commutation DMA request enable */ +#define TIMER_DMA_TRGD ((uint16_t)TIMER_DMAINTEN_TRGDEN) /*!< trigger DMA enable */ -/* channel DMA request source selection */ +/* channel DMA request source selection */ #define TIMER_DMAREQUEST_UPDATEEVENT ((uint8_t)0x00U) /*!< DMA request of channel y is sent when update event occurs */ #define TIMER_DMAREQUEST_CHANNELEVENT ((uint8_t)0x01U) /*!< DMA request of channel y is sent when channel y event occurs */ @@ -380,12 +418,12 @@ typedef struct #define TIMER_COUNTER_CENTER_BOTH CTL0_CAM(3) /*!< center-aligned and counting up/down assert mode */ /* TIMER prescaler reload mode */ -#define TIMER_PSC_RELOAD_NOW ((uint8_t)0x00U) /*!< the prescaler is loaded right now */ -#define TIMER_PSC_RELOAD_UPDATE ((uint8_t)0x01U) /*!< the prescaler is loaded at the next update event */ +#define TIMER_PSC_RELOAD_NOW ((uint32_t)0x00000000U) /*!< the prescaler is loaded right now */ +#define TIMER_PSC_RELOAD_UPDATE ((uint32_t)0x00000001U) /*!< the prescaler is loaded at the next update event */ /* count direction */ #define TIMER_COUNTER_UP ((uint16_t)0x0000U) /*!< counter up direction */ -#define TIMER_COUNTER_DOWN ((uint16_t)0x0010U) /*!< counter down direction */ +#define TIMER_COUNTER_DOWN ((uint16_t)TIMER_CTL0_DIR) /*!< counter down direction */ /* specify division ratio between TIMER clock and dead-time and sampling clock */ #define CTL0_CKDIV(regval) ((uint16_t)(BITS(8, 9) & ((uint32_t)(regval) << 8U))) @@ -394,27 +432,27 @@ typedef struct #define TIMER_CKDIV_DIV4 CTL0_CKDIV(2) /*!< clock division value is 4, fDTS= fTIMER_CK/4 */ /* single pulse mode */ -#define TIMER_SP_MODE_SINGLE ((uint8_t)0x00U) /*!< single pulse mode */ -#define TIMER_SP_MODE_REPETITIVE ((uint8_t)0x01U) /*!< repetitive pulse mode */ +#define TIMER_SP_MODE_SINGLE ((uint32_t)0x00000000U) /*!< single pulse mode */ +#define TIMER_SP_MODE_REPETITIVE ((uint32_t)0x00000001U) /*!< repetitive pulse mode */ /* update source */ -#define TIMER_UPDATE_SRC_REGULAR ((uint8_t)0x00U) /*!< update generate only by counter overflow/underflow */ -#define TIMER_UPDATE_SRC_GLOBAL ((uint8_t)0x01U) /*!< update generate by setting of UPG bit or the counter overflow/underflow,or the slave mode controller trigger */ +#define TIMER_UPDATE_SRC_REGULAR ((uint32_t)0x00000000U) /*!< update generate only by counter overflow/underflow */ +#define TIMER_UPDATE_SRC_GLOBAL ((uint32_t)0x00000001U) /*!< update generate by setting of UPG bit or the counter overflow/underflow,or the slave mode controller trigger */ /* run mode off-state configure */ -#define TIMER_ROS_STATE_ENABLE ((uint32_t)0x00000800U) /*!< when POEN bit is set, the channel output signals (CHx_O/CHx_ON) are enabled, with relationship to CHxEN/CHxNEN bits */ -#define TIMER_ROS_STATE_DISABLE ((uint32_t)0x00000000U) /*!< when POEN bit is set, the channel output signals (CHx_O/CHx_ON) are disabled */ +#define TIMER_ROS_STATE_ENABLE ((uint16_t)TIMER_CCHP_ROS) /*!< when POEN bit is set, the channel output signals (CHx_O/CHx_ON) are enabled, with relationship to CHxEN/CHxNEN bits */ +#define TIMER_ROS_STATE_DISABLE ((uint16_t)0x0000U) /*!< when POEN bit is set, the channel output signals (CHx_O/CHx_ON) are disabled */ -/* idle mode off-state configure */ -#define TIMER_IOS_STATE_ENABLE ((uint16_t)0x0400U) /*!< when POEN bit is reset, he channel output signals (CHx_O/CHx_ON) are enabled, with relationship to CHxEN/CHxNEN bits */ +/* idle mode off-state configure */ +#define TIMER_IOS_STATE_ENABLE ((uint16_t)TIMER_CCHP_IOS) /*!< when POEN bit is reset, the channel output signals (CHx_O/CHx_ON) are enabled, with relationship to CHxEN/CHxNEN bits */ #define TIMER_IOS_STATE_DISABLE ((uint16_t)0x0000U) /*!< when POEN bit is reset, the channel output signals (CHx_O/CHx_ON) are disabled */ /* break input polarity */ #define TIMER_BREAK_POLARITY_LOW ((uint16_t)0x0000U) /*!< break input polarity is low */ -#define TIMER_BREAK_POLARITY_HIGH ((uint16_t)0x2000U) /*!< break input polarity is high */ +#define TIMER_BREAK_POLARITY_HIGH ((uint16_t)TIMER_CCHP_BRKP) /*!< break input polarity is high */ /* output automatic enable */ -#define TIMER_OUTAUTO_ENABLE ((uint16_t)0x4000U) /*!< output automatic enable */ +#define TIMER_OUTAUTO_ENABLE ((uint16_t)TIMER_CCHP_OAEN) /*!< output automatic enable */ #define TIMER_OUTAUTO_DISABLE ((uint16_t)0x0000U) /*!< output automatic disable */ /* complementary register protect control */ @@ -425,10 +463,10 @@ typedef struct #define TIMER_CCHP_PROT_2 CCHP_PROT(3) /*!< PROT mode 2 */ /* break input enable */ -#define TIMER_BREAK_ENABLE ((uint16_t)0x1000U) /*!< break input enable */ +#define TIMER_BREAK_ENABLE ((uint16_t)TIMER_CCHP_BRKEN) /*!< break input enable */ #define TIMER_BREAK_DISABLE ((uint16_t)0x0000U) /*!< break input disable */ -/* TIMER channel y(y=0,1,2,3) */ +/* TIMER channel n(n=0,1,2,3) */ #define TIMER_CH_0 ((uint16_t)0x0000U) /*!< TIMER channel 0(TIMERx(x=0..4,7..13)) */ #define TIMER_CH_1 ((uint16_t)0x0001U) /*!< TIMER channel 1(TIMERx(x=0..4,7,8,11)) */ #define TIMER_CH_2 ((uint16_t)0x0002U) /*!< TIMER channel 2(TIMERx(x=0..4,7)) */ @@ -450,11 +488,11 @@ typedef struct #define TIMER_OCN_POLARITY_HIGH ((uint16_t)0x0000U) /*!< channel complementary output polarity is high */ #define TIMER_OCN_POLARITY_LOW ((uint16_t)0x0008U) /*!< channel complementary output polarity is low */ -/* idle state of channel output */ +/* idle state of channel output */ #define TIMER_OC_IDLE_STATE_HIGH ((uint16_t)0x0100) /*!< idle state of channel output is high */ #define TIMER_OC_IDLE_STATE_LOW ((uint16_t)0x0000) /*!< idle state of channel output is low */ -/* idle state of channel complementary output */ +/* idle state of channel complementary output */ #define TIMER_OCN_IDLE_STATE_HIGH ((uint16_t)0x0200U) /*!< idle state of channel complementary output is high */ #define TIMER_OCN_IDLE_STATE_LOW ((uint16_t)0x0000U) /*!< idle state of channel complementary output is low */ @@ -476,20 +514,20 @@ typedef struct #define TIMER_OC_FAST_ENABLE ((uint16_t)0x0004) /*!< channel output fast function enable */ #define TIMER_OC_FAST_DISABLE ((uint16_t)0x0000) /*!< channel output fast function disable */ -/* channel output compare clear enable. */ +/* channel output compare clear enable */ #define TIMER_OC_CLEAR_ENABLE ((uint16_t)0x0080U) /*!< channel output clear function enable */ #define TIMER_OC_CLEAR_DISABLE ((uint16_t)0x0000U) /*!< channel output clear function disable */ -/* channel control shadow register update control */ -#define TIMER_UPDATECTL_CCU ((uint8_t)0x00U) /*!< the shadow registers update by when CMTG bit is set */ -#define TIMER_UPDATECTL_CCUTRI ((uint8_t)0x01U) /*!< the shadow registers update by when CMTG bit is set or an rising edge of TRGI occurs */ +/* channel control shadow register update control */ +#define TIMER_UPDATECTL_CCU ((uint32_t)0x00000000U) /*!< the shadow registers are updated when CMTG bit is set */ +#define TIMER_UPDATECTL_CCUTRI ((uint32_t)0x00000001U) /*!< the shadow registers update by when CMTG bit is set or an rising edge of TRGI occurs */ /* channel input capture polarity */ #define TIMER_IC_POLARITY_RISING ((uint16_t)0x0000U) /*!< input capture rising edge */ #define TIMER_IC_POLARITY_FALLING ((uint16_t)0x0002U) /*!< input capture falling edge */ #define TIMER_IC_POLARITY_BOTH_EDGE ((uint16_t)0x000AU) /*!< input capture both edge */ -/* timer input capture selection */ +/* TIMER input capture selection */ #define TIMER_IC_SELECTION_DIRECTTI ((uint16_t)0x0001U) /*!< channel y is configured as input and icy is mapped on CIy */ #define TIMER_IC_SELECTION_INDIRECTTI ((uint16_t)0x0002U) /*!< channel y is configured as input and icy is mapped on opposite input */ #define TIMER_IC_SELECTION_ITS ((uint16_t)0x0003U) /*!< channel y is configured as input and icy is mapped on ITS */ @@ -502,28 +540,28 @@ typedef struct /* trigger selection */ #define SMCFG_TRGSEL(regval) (BITS(4, 6) & ((uint32_t)(regval) << 4U)) -#define TIMER_SMCFG_TRGSEL_ITI0 SMCFG_TRGSEL(0) /*!< internal trigger 0 */ -#define TIMER_SMCFG_TRGSEL_ITI1 SMCFG_TRGSEL(1) /*!< internal trigger 1 */ -#define TIMER_SMCFG_TRGSEL_ITI2 SMCFG_TRGSEL(2) /*!< internal trigger 2 */ -#define TIMER_SMCFG_TRGSEL_ITI3 SMCFG_TRGSEL(3) /*!< internal trigger 3 */ -#define TIMER_SMCFG_TRGSEL_CI0F_ED SMCFG_TRGSEL(4) /*!< TI0 Edge Detector */ -#define TIMER_SMCFG_TRGSEL_CI0FE0 SMCFG_TRGSEL(5) /*!< filtered TIMER input 0 */ -#define TIMER_SMCFG_TRGSEL_CI1FE1 SMCFG_TRGSEL(6) /*!< filtered TIMER input 1 */ -#define TIMER_SMCFG_TRGSEL_ETIFP SMCFG_TRGSEL(7) /*!< external trigger */ +#define TIMER_SMCFG_TRGSEL_ITI0 SMCFG_TRGSEL(0) /*!< internal trigger 0 */ +#define TIMER_SMCFG_TRGSEL_ITI1 SMCFG_TRGSEL(1) /*!< internal trigger 1 */ +#define TIMER_SMCFG_TRGSEL_ITI2 SMCFG_TRGSEL(2) /*!< internal trigger 2 */ +#define TIMER_SMCFG_TRGSEL_ITI3 SMCFG_TRGSEL(3) /*!< internal trigger 3 */ +#define TIMER_SMCFG_TRGSEL_CI0F_ED SMCFG_TRGSEL(4) /*!< TI0 Edge Detector */ +#define TIMER_SMCFG_TRGSEL_CI0FE0 SMCFG_TRGSEL(5) /*!< filtered TIMER input 0 */ +#define TIMER_SMCFG_TRGSEL_CI1FE1 SMCFG_TRGSEL(6) /*!< filtered TIMER input 1 */ +#define TIMER_SMCFG_TRGSEL_ETIFP SMCFG_TRGSEL(7) /*!< external trigger */ /* master mode control */ #define CTL1_MMC(regval) (BITS(4, 6) & ((uint32_t)(regval) << 4U)) #define TIMER_TRI_OUT_SRC_RESET CTL1_MMC(0) /*!< the UPG bit as trigger output */ #define TIMER_TRI_OUT_SRC_ENABLE CTL1_MMC(1) /*!< the counter enable signal TIMER_CTL0_CEN as trigger output */ #define TIMER_TRI_OUT_SRC_UPDATE CTL1_MMC(2) /*!< update event as trigger output */ -#define TIMER_TRI_OUT_SRC_CC0 CTL1_MMC(3) /*!< a capture or a compare match occurred in channal0 as trigger output TRGO */ +#define TIMER_TRI_OUT_SRC_CH0 CTL1_MMC(3) /*!< a capture or a compare match occurred in channal0 as trigger output TRGO */ #define TIMER_TRI_OUT_SRC_O0CPRE CTL1_MMC(4) /*!< O0CPRE as trigger output */ #define TIMER_TRI_OUT_SRC_O1CPRE CTL1_MMC(5) /*!< O1CPRE as trigger output */ #define TIMER_TRI_OUT_SRC_O2CPRE CTL1_MMC(6) /*!< O2CPRE as trigger output */ #define TIMER_TRI_OUT_SRC_O3CPRE CTL1_MMC(7) /*!< O3CPRE as trigger output */ /* slave mode control */ -#define SMCFG_SMC(regval) (BITS(0, 2) & ((uint32_t)(regval) << 0U)) +#define SMCFG_SMC(regval) (BITS(0, 2) & ((uint32_t)(regval) << 0U)) #define TIMER_SLAVE_MODE_DISABLE SMCFG_SMC(0) /*!< slave mode disable */ #define TIMER_ENCODER_MODE0 SMCFG_SMC(1) /*!< encoder mode 0 */ #define TIMER_ENCODER_MODE1 SMCFG_SMC(2) /*!< encoder mode 1 */ @@ -533,9 +571,9 @@ typedef struct #define TIMER_SLAVE_MODE_EVENT SMCFG_SMC(6) /*!< event mode */ #define TIMER_SLAVE_MODE_EXTERNAL0 SMCFG_SMC(7) /*!< external clock mode 0 */ -/* master slave mode selection */ -#define TIMER_MASTER_SLAVE_MODE_ENABLE ((uint8_t)0x00U) /*!< master slave mode enable */ -#define TIMER_MASTER_SLAVE_MODE_DISABLE ((uint8_t)0x01U) /*!< master slave mode disable */ +/* master slave mode selection */ +#define TIMER_MASTER_SLAVE_MODE_ENABLE ((uint32_t)0x00000000U) /*!< master slave mode enable */ +#define TIMER_MASTER_SLAVE_MODE_DISABLE ((uint32_t)0x00000001U) /*!< master slave mode disable */ /* external trigger prescaler */ #define SMCFG_ETPSC(regval) (BITS(12, 13) & ((uint32_t)(regval) << 12U)) @@ -548,19 +586,19 @@ typedef struct #define TIMER_ETP_FALLING TIMER_SMCFG_ETP /*!< active low or falling edge active */ #define TIMER_ETP_RISING ((uint32_t)0x00000000U) /*!< active high or rising edge active */ -/* channel 0 trigger input selection */ -#define TIMER_HALLINTERFACE_ENABLE ((uint8_t)0x00U) /*!< TIMER hall sensor mode enable */ -#define TIMER_HALLINTERFACE_DISABLE ((uint8_t)0x01U) /*!< TIMER hall sensor mode disable */ +/* channel 0 trigger input selection */ +#define TIMER_HALLINTERFACE_ENABLE ((uint32_t)0x00000000U) /*!< TIMER hall sensor mode enable */ +#define TIMER_HALLINTERFACE_DISABLE ((uint32_t)0x00000001U) /*!< TIMER hall sensor mode disable */ /* timer1 internal trigger input1 remap */ -#define TIMER1_IRMP(regval) (BITS(10, 11) & ((uint32_t)(regval) << 10U)) +#define TIMER1_IRMP(regval) (BITS(10, 11) & ((uint32_t)(regval) << 10U)) #define TIMER1_ITI1_RMP_TIMER7_TRGO TIMER1_IRMP(0) /*!< timer1 internal trigger input 1 remap to TIMER7_TRGO */ #define TIMER1_ITI1_RMP_ETHERNET_PTP TIMER1_IRMP(1) /*!< timer1 internal trigger input 1 remap to ethernet PTP */ #define TIMER1_ITI1_RMP_USB_FS_SOF TIMER1_IRMP(2) /*!< timer1 internal trigger input 1 remap to USB FS SOF */ #define TIMER1_ITI1_RMP_USB_HS_SOF TIMER1_IRMP(3) /*!< timer1 internal trigger input 1 remap to USB HS SOF */ /* timer4 channel 3 input remap */ -#define TIMER4_IRMP(regval) (BITS(6, 7) & ((uint32_t)(regval) << 6U)) +#define TIMER4_IRMP(regval) (BITS(6, 7) & ((uint32_t)(regval) << 6U)) #define TIMER4_CI3_RMP_GPIO TIMER4_IRMP(0) /*!< timer4 channel 3 input remap to GPIO pin */ #define TIMER4_CI3_RMP_IRC32K TIMER4_IRMP(1) /*!< timer4 channel 3 input remap to IRC32K */ #define TIMER4_CI3_RMP_LXTAL TIMER4_IRMP(2) /*!< timer4 channel 3 input remap to LXTAL */ @@ -572,19 +610,21 @@ typedef struct #define TIMER10_ITI1_RMP_RTC_HXTAL_DIV TIMER10_IRMP(2) /*!< timer10 internal trigger input1 remap HXTAL _DIV(clock used for RTC which is HXTAL clock divided by RTCDIV bits in RCU_CFG0 register) */ /* timerx(x=0,1,2,13,14,15,16) write cc register selection */ -#define TIMER_CCSEL_DISABLE ((uint16_t)0x0000U) /*!< write CC register selection disable */ -#define TIMER_CCSEL_ENABLE ((uint16_t)0x0002U) /*!< write CC register selection enable */ +#define TIMER_CHVSEL_ENABLE ((uint16_t)0x0002U) /*!< write CHxVAL register selection enable */ +#define TIMER_CHVSEL_DISABLE ((uint16_t)0x0000U) /*!< write CHxVAL register selection disable */ /* the output value selection */ -#define TIMER_OUTSEL_DISABLE ((uint16_t)0x0000U) /*!< output value selection disable */ #define TIMER_OUTSEL_ENABLE ((uint16_t)0x0001U) /*!< output value selection enable */ +#define TIMER_OUTSEL_DISABLE ((uint16_t)0x0000U) /*!< output value selection disable */ /* function declarations */ /* TIMER timebase*/ /* deinit a TIMER */ void timer_deinit(uint32_t timer_periph); +/* initialize TIMER init parameter struct */ +void timer_struct_para_init(timer_parameter_struct* initpara); /* initialize TIMER counter */ -void timer_init(uint32_t timer_periph, timer_parameter_struct* timer_initpara); +void timer_init(uint32_t timer_periph, timer_parameter_struct* initpara); /* enable a TIMER */ void timer_enable(uint32_t timer_periph); /* disable a TIMER */ @@ -598,57 +638,59 @@ void timer_update_event_enable(uint32_t timer_periph); /* disable the update event */ void timer_update_event_disable(uint32_t timer_periph); /* set TIMER counter alignment mode */ -void timer_counter_alignment(uint32_t timer_periph,uint16_t timer_aligned); +void timer_counter_alignment(uint32_t timer_periph, uint16_t aligned); /* set TIMER counter up direction */ void timer_counter_up_direction(uint32_t timer_periph); /* set TIMER counter down direction */ void timer_counter_down_direction(uint32_t timer_periph); /* configure TIMER prescaler */ -void timer_prescaler_config(uint32_t timer_periph,uint16_t timer_prescaler,uint8_t timer_pscreload); +void timer_prescaler_config(uint32_t timer_periph, uint16_t prescaler, uint8_t pscreload); /* configure TIMER repetition register value */ -void timer_repetition_value_config(uint32_t timer_periph,uint16_t timer_repetition); +void timer_repetition_value_config(uint32_t timer_periph, uint16_t repetition); /* configure TIMER autoreload register value */ -void timer_autoreload_value_config(uint32_t timer_periph,uint32_t timer_autoreload); +void timer_autoreload_value_config(uint32_t timer_periph,uint32_t autoreload); /* configure TIMER counter register value */ -void timer_counter_value_config(uint32_t timer_periph , uint32_t timer_counter); +void timer_counter_value_config(uint32_t timer_periph , uint32_t counter); /* read TIMER counter value */ uint32_t timer_counter_read(uint32_t timer_periph); /* read TIMER prescaler value */ uint16_t timer_prescaler_read(uint32_t timer_periph); /* configure TIMER single pulse mode */ -void timer_single_pulse_mode_config(uint32_t timer_periph,uint8_t timer_spmode); +void timer_single_pulse_mode_config(uint32_t timer_periph, uint32_t spmode); /* configure TIMER update source */ -void timer_update_source_config(uint32_t timer_periph,uint8_t timer_update); +void timer_update_source_config(uint32_t timer_periph, uint32_t update); /* TIMER interrupt and flag*/ /* enable the TIMER interrupt */ -void timer_interrupt_enable(uint32_t timer_periph,uint32_t timer_interrupt); +void timer_interrupt_enable(uint32_t timer_periph, uint32_t interrupt); /* disable the TIMER interrupt */ -void timer_interrupt_disable(uint32_t timer_periph,uint32_t timer_interrupt); +void timer_interrupt_disable(uint32_t timer_periph, uint32_t interrupt); /* get timer interrupt flag */ -FlagStatus timer_interrupt_flag_get(uint32_t timer_periph,uint32_t timer_interrupt); +FlagStatus timer_interrupt_flag_get(uint32_t timer_periph, uint32_t interrupt); /* clear TIMER interrupt flag */ -void timer_interrupt_flag_clear(uint32_t timer_periph,uint32_t timer_interrupt); +void timer_interrupt_flag_clear(uint32_t timer_periph, uint32_t interrupt); /* get TIMER flags */ -FlagStatus timer_flag_get(uint32_t timer_periph , uint32_t timer_flag); +FlagStatus timer_flag_get(uint32_t timer_periph, uint32_t flag); /* clear TIMER flags */ -void timer_flag_clear(uint32_t timer_periph , uint32_t timer_flag); +void timer_flag_clear(uint32_t timer_periph, uint32_t flag); /* timer DMA and event*/ /* enable the TIMER DMA */ -void timer_dma_enable(uint32_t timer_periph,uint16_t timer_dma); +void timer_dma_enable(uint32_t timer_periph, uint16_t dma); /* disable the TIMER DMA */ -void timer_dma_disable(uint32_t timer_periph,uint16_t timer_dma); +void timer_dma_disable(uint32_t timer_periph, uint16_t dma); /* channel DMA request source selection */ -void timer_channel_dma_request_source_select(uint32_t timer_periph,uint8_t dma_request); +void timer_channel_dma_request_source_select(uint32_t timer_periph, uint8_t dma_request); /* configure the TIMER DMA transfer */ -void timer_dma_transfer_config(uint32_t timer_periph,uint32_t dma_baseaddr,uint32_t dma_lenth); +void timer_dma_transfer_config(uint32_t timer_periph,uint32_t dma_baseaddr, uint32_t dma_lenth); /* software generate events */ -void timer_event_software_generate(uint32_t timer_periph,uint16_t timer_event); +void timer_event_software_generate(uint32_t timer_periph, uint16_t event); -/* timer channel complementary protection */ +/* TIMER channel complementary protection */ +/* initialize TIMER break parameter struct */ +void timer_break_struct_para_init(timer_break_parameter_struct* breakpara); /* configure TIMER break function */ -void timer_break_config(uint32_t timer_periph,timer_break_parameter_struct* timer_bkdtpara); +void timer_break_config(uint32_t timer_periph, timer_break_parameter_struct* breakpara); /* enable TIMER break function */ void timer_break_enable(uint32_t timer_periph); /* disable TIMER break function */ @@ -657,79 +699,83 @@ void timer_break_disable(uint32_t timer_periph); void timer_automatic_output_enable(uint32_t timer_periph); /* disable TIMER output automatic function */ void timer_automatic_output_disable(uint32_t timer_periph); -/* configure TIMER primary output function */ -void timer_primary_output_config(uint32_t timer_periph,ControlStatus newvalue); -/* channel capture/compare control shadow register enable */ -void timer_channel_control_shadow_config(uint32_t timer_periph,ControlStatus newvalue); +/* enable or disable TIMER primary output function */ +void timer_primary_output_config(uint32_t timer_periph, ControlStatus newvalue); +/* enable or disable channel capture/compare control shadow register */ +void timer_channel_control_shadow_config(uint32_t timer_periph, ControlStatus newvalue); /* configure TIMER channel control shadow register update control */ -void timer_channel_control_shadow_update_config(uint32_t timer_periph,uint8_t timer_ccuctl); +void timer_channel_control_shadow_update_config(uint32_t timer_periph, uint8_t ccuctl); /* TIMER channel output */ +/* initialize TIMER channel output parameter struct */ +void timer_channel_output_struct_para_init(timer_oc_parameter_struct* ocpara); /* configure TIMER channel output function */ -void timer_channel_output_config(uint32_t timer_periph,uint16_t timer_channel,timer_oc_parameter_struct* timer_ocpara); +void timer_channel_output_config(uint32_t timer_periph,uint16_t channel, timer_oc_parameter_struct* ocpara); /* configure TIMER channel output compare mode */ -void timer_channel_output_mode_config(uint32_t timer_periph,uint16_t timer_channel,uint16_t timer_ocmode); +void timer_channel_output_mode_config(uint32_t timer_periph, uint16_t channel,uint16_t ocmode); /* configure TIMER channel output pulse value */ -void timer_channel_output_pulse_value_config(uint32_t timer_periph,uint16_t timer_channel,uint32_t timer_pluse); +void timer_channel_output_pulse_value_config(uint32_t timer_periph, uint16_t channel, uint32_t pulse); /* configure TIMER channel output shadow function */ -void timer_channel_output_shadow_config(uint32_t timer_periph,uint16_t timer_channel,uint16_t timer_ocshadow); +void timer_channel_output_shadow_config(uint32_t timer_periph, uint16_t channel, uint16_t ocshadow); /* configure TIMER channel output fast function */ -void timer_channel_output_fast_config(uint32_t timer_periph,uint16_t timer_channel,uint16_t timer_ocfast); +void timer_channel_output_fast_config(uint32_t timer_periph, uint16_t channel, uint16_t ocfast); /* configure TIMER channel output clear function */ -void timer_channel_output_clear_config(uint32_t timer_periph,uint16_t timer_channel,uint16_t timer_occlear); +void timer_channel_output_clear_config(uint32_t timer_periph,uint16_t channel,uint16_t occlear); /* configure TIMER channel output polarity */ -void timer_channel_output_polarity_config(uint32_t timer_periph,uint16_t timer_channel,uint16_t timer_ocpolarity); +void timer_channel_output_polarity_config(uint32_t timer_periph, uint16_t channel, uint16_t ocpolarity); /* configure TIMER channel complementary output polarity */ -void timer_channel_complementary_output_polarity_config(uint32_t timer_periph,uint16_t timer_channel,uint16_t timer_ocnpolarity); +void timer_channel_complementary_output_polarity_config(uint32_t timer_periph, uint16_t channel, uint16_t ocnpolarity); /* configure TIMER channel enable state */ -void timer_channel_output_state_config(uint32_t timer_periph,uint16_t timer_channel,uint32_t timer_state); +void timer_channel_output_state_config(uint32_t timer_periph, uint16_t channel, uint32_t state); /* configure TIMER channel complementary output enable state */ -void timer_channel_complementary_output_state_config(uint32_t timer_periph,uint16_t timer_channel,uint16_t timer_ocnstate); +void timer_channel_complementary_output_state_config(uint32_t timer_periph, uint16_t channel, uint16_t ocnstate); /* TIMER channel input */ +/* initialize TIMER channel input parameter struct */ +void timer_channel_input_struct_para_init(timer_ic_parameter_struct* icpara); /* configure TIMER input capture parameter */ -void timer_input_capture_config(uint32_t timer_periph,uint16_t timer_channel,timer_ic_parameter_struct* timer_icpara); +void timer_input_capture_config(uint32_t timer_periph, uint16_t channel, timer_ic_parameter_struct* icpara); /* configure TIMER channel input capture prescaler value */ -void timer_channel_input_capture_prescaler_config(uint32_t timer_periph,uint16_t timer_channel,uint16_t timer_prescaler); +void timer_channel_input_capture_prescaler_config(uint32_t timer_periph, uint16_t channel, uint16_t prescaler); /* read TIMER channel capture compare register value */ -uint32_t timer_channel_capture_value_register_read(uint32_t timer_periph,uint16_t timer_channel); +uint32_t timer_channel_capture_value_register_read(uint32_t timer_periph, uint16_t channel); /* configure TIMER input pwm capture function */ -void timer_input_pwm_capture_config(uint32_t timer_periph,uint16_t timer_channel,timer_ic_parameter_struct* timer_icpwm); +void timer_input_pwm_capture_config(uint32_t timer_periph, uint16_t channel, timer_ic_parameter_struct* icpwm); /* configure TIMER hall sensor mode */ -void timer_hall_mode_config(uint32_t timer_periph,uint8_t timer_hallmode); +void timer_hall_mode_config(uint32_t timer_periph, uint32_t hallmode); /* TIMER master and slave */ /* select TIMER input trigger source */ -void timer_input_trigger_source_select(uint32_t timer_periph,uint32_t timer_intrigger); +void timer_input_trigger_source_select(uint32_t timer_periph, uint32_t intrigger); /* select TIMER master mode output trigger source */ -void timer_master_output_trigger_source_select(uint32_t timer_periph,uint32_t timer_outrigger); +void timer_master_output_trigger_source_select(uint32_t timer_periph, uint32_t outrigger); /* select TIMER slave mode */ -void timer_slave_mode_select(uint32_t timer_periph,uint32_t timer_slavemode); +void timer_slave_mode_select(uint32_t timer_periph,uint32_t slavemode); /* configure TIMER master slave mode */ -void timer_master_slave_mode_config(uint32_t timer_periph,uint8_t timer_masterslave); +void timer_master_slave_mode_config(uint32_t timer_periph, uint32_t masterslave); /* configure TIMER external trigger input */ -void timer_external_trigger_config(uint32_t timer_periph,uint32_t timer_extprescaler,uint32_t timer_expolarity,uint32_t timer_extfilter); +void timer_external_trigger_config(uint32_t timer_periph, uint32_t extprescaler, uint32_t extpolarity, uint32_t extfilter); /* configure TIMER quadrature decoder mode */ -void timer_quadrature_decoder_mode_config(uint32_t timer_periph,uint32_t timer_decomode,uint16_t timer_ic0polarity,uint16_t timer_ic1polarity); +void timer_quadrature_decoder_mode_config(uint32_t timer_periph, uint32_t decomode, uint16_t ic0polarity, uint16_t ic1polarity); /* configure TIMER internal clock mode */ void timer_internal_clock_config(uint32_t timer_periph); /* configure TIMER the internal trigger as external clock input */ -void timer_internal_trigger_as_external_clock_config(uint32_t timer_periph, uint32_t timer_intrigger); +void timer_internal_trigger_as_external_clock_config(uint32_t timer_periph, uint32_t intrigger); /* configure TIMER the external trigger as external clock input */ -void timer_external_trigger_as_external_clock_config(uint32_t timer_periph,uint32_t timer_extrigger,uint16_t timer_expolarity,uint32_t timer_extfilter); +void timer_external_trigger_as_external_clock_config(uint32_t timer_periph, uint32_t extrigger, uint16_t extpolarity,uint32_t extfilter); /* configure TIMER the external clock mode 0 */ -void timer_external_clock_mode0_config(uint32_t timer_periph,uint32_t timer_extprescaler,uint32_t timer_expolarity,uint32_t timer_extfilter); +void timer_external_clock_mode0_config(uint32_t timer_periph, uint32_t extprescaler, uint32_t extpolarity, uint32_t extfilter); /* configure TIMER the external clock mode 1 */ -void timer_external_clock_mode1_config(uint32_t timer_periph,uint32_t timer_extprescaler,uint32_t timer_expolarity,uint32_t timer_extfilter); +void timer_external_clock_mode1_config(uint32_t timer_periph, uint32_t extprescaler, uint32_t extpolarity, uint32_t extfilter); /* disable TIMER the external clock mode 1 */ void timer_external_clock_mode1_disable(uint32_t timer_periph); -/* configure TIMER1 channel 0 remap function */ -void timer_channel_remap_config(uint32_t timer_periph,uint32_t timer_remap); +/* configure TIMER channel remap function */ +void timer_channel_remap_config(uint32_t timer_periph,uint32_t remap); /* TIMER configure */ /* configure TIMER write CHxVAL register selection */ -void timer_write_cc_register_config(uint32_t timer_periph, uint16_t timer_ccsel); +void timer_write_chxval_register_config(uint32_t timer_periph, uint16_t ccsel); /* configure TIMER output value selection */ -void timer_output_value_selection_config(uint32_t timer_periph, uint16_t timer_outsel); +void timer_output_value_selection_config(uint32_t timer_periph, uint16_t outsel); #endif /* GD32F4XX_TIMER_H */ diff --git a/bsp/gd32450z-eval/Libraries/GD32F4xx_standard_peripheral/Include/gd32f4xx_tli.h b/bsp/gd32450z-eval/Libraries/GD32F4xx_standard_peripheral/Include/gd32f4xx_tli.h index f2f8f9d71e..8b1232fa17 100644 --- a/bsp/gd32450z-eval/Libraries/GD32F4xx_standard_peripheral/Include/gd32f4xx_tli.h +++ b/bsp/gd32450z-eval/Libraries/GD32F4xx_standard_peripheral/Include/gd32f4xx_tli.h @@ -1,12 +1,37 @@ /*! - \file gd32f4xx_tli.h - \brief definitions for the TLI + \file gd32f4xx_tli.h + \brief definitions for the TLI + + \version 2016-08-15, V1.0.0, firmware for GD32F4xx + \version 2018-12-12, V2.0.0, firmware for GD32F4xx + \version 2020-09-30, V2.1.0, firmware for GD32F4xx */ /* - Copyright (C) 2016 GigaDevice + Copyright (c) 2020, GigaDevice Semiconductor Inc. + + Redistribution and use in source and binary forms, with or without modification, +are permitted provided that the following conditions are met: + + 1. Redistributions of source code must retain the above copyright notice, this + list of conditions and the following disclaimer. + 2. Redistributions in binary form must reproduce the above copyright notice, + this list of conditions and the following disclaimer in the documentation + and/or other materials provided with the distribution. + 3. Neither the name of the copyright holder nor the names of its contributors + may be used to endorse or promote products derived from this software without + specific prior written permission. - 2016-08-15, V1.0.1, firmware for GD32F4xx + THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED +WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. +IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, +INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT +NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR +PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, +WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY +OF SUCH DAMAGE. */ #ifndef GD32F4XX_TLI_H @@ -17,8 +42,8 @@ /* TLI definitions */ #define TLI TLI_BASE /*!< TLI base address */ /* TLI layer definitions */ -#define LAYER0 TLI_BASE /*!< Layer0 base address */ -#define LAYER1 (TLI_BASE+0x80) /*!< Layer1 base address */ +#define LAYER0 TLI_BASE /*!< TLI layer0 base address */ +#define LAYER1 (TLI_BASE+0x80) /*!< TLI layer1 base address */ /* registers definitions */ #define TLI_SPSZ REG32(TLI + 0x08U) /*!< TLI synchronous pulse size register */ @@ -45,8 +70,7 @@ #define TLI_LxFBADDR(layerx) REG32((layerx) + 0xACU) /*!< TLI layer x frame base address register */ #define TLI_LxFLLEN(layerx) REG32((layerx) + 0xB0U) /*!< TLI layer x frame line length register */ #define TLI_LxFTLN(layerx) REG32((layerx) + 0xB4U) /*!< TLI layer x frame total line number register */ -#define TLI_LxLUT(layerx) REG32((layerx) + 0xC4U) /*!< TLI ayer x Look Up Table register */ - +#define TLI_LxLUT(layerx) REG32((layerx) + 0xC4U) /*!< TLI layer x look up table register */ /* bits definitions */ /* TLI_SPSZ */ @@ -154,8 +178,8 @@ #define TLI_LxFBADDR_FBADD BITS(0,31) /*!< frame buffer base address */ /* TLI_LxFLLEN */ -#define TLI_LxFLLEN_FLL BITS(0,12) /*!< frame line length */ -#define TLI_LxFLLEN_STDOFF BITS(16,28) /*!< frame buffer stride offset */ +#define TLI_LxFLLEN_FLL BITS(0,13) /*!< frame line length */ +#define TLI_LxFLLEN_STDOFF BITS(16,29) /*!< frame buffer stride offset */ /* TLI_LxFTLN */ #define TLI_LxFTLN_FTLN BITS(0,10) /*!< frame total line number */ @@ -167,14 +191,13 @@ #define TLI_LxLUT_TADD BITS(24,31) /*!< look up table write address */ /* constants definitions */ - /* TLI parameter struct definitions */ typedef struct -{ - uint32_t synpsz_vpsz; /*!< size of the vertical synchronous pulse */ - uint32_t synpsz_hpsz; /*!< size of the horizontal synchronous pulse */ - uint32_t backpsz_vbpsz; /*!< size of the vertical back porch plus synchronous pulse */ - uint32_t backpsz_hbpsz; /*!< size of the horizontal back porch plus synchronous pulse */ +{ + uint16_t synpsz_vpsz; /*!< size of the vertical synchronous pulse */ + uint16_t synpsz_hpsz; /*!< size of the horizontal synchronous pulse */ + uint16_t backpsz_vbpsz; /*!< size of the vertical back porch plus synchronous pulse */ + uint16_t backpsz_hbpsz; /*!< size of the horizontal back porch plus synchronous pulse */ uint32_t activesz_vasz; /*!< size of the vertical active area width plus back porch and synchronous pulse */ uint32_t activesz_hasz; /*!< size of the horizontal active area width plus back porch and synchronous pulse */ uint32_t totalsz_vtsz; /*!< vertical total size of the display */ @@ -186,141 +209,168 @@ typedef struct uint32_t signalpolarity_vs; /*!< vertical pulse polarity selection */ uint32_t signalpolarity_de; /*!< data enable polarity selection */ uint32_t signalpolarity_pixelck; /*!< pixel clock polarity selection */ -}tli_parameter_struct; +}tli_parameter_struct; -/* TLI Layer parameter struct definitions */ +/* TLI layer parameter struct definitions */ typedef struct -{ - uint32_t layer_window_rightpos; /*!< window right position */ - uint32_t layer_window_leftpos; /*!< window left position */ - uint32_t layer_window_bottompos; /*!< window bottom position */ - uint32_t layer_window_toppos; /*!< window top position */ +{ + uint16_t layer_window_rightpos; /*!< window right position */ + uint16_t layer_window_leftpos; /*!< window left position */ + uint16_t layer_window_bottompos; /*!< window bottom position */ + uint16_t layer_window_toppos; /*!< window top position */ uint32_t layer_ppf; /*!< packeted pixel format */ - uint32_t layer_sa; /*!< specified alpha */ - uint32_t layer_default_alpha; /*!< the default color alpha */ - uint32_t layer_default_red; /*!< the default color red */ - uint32_t layer_default_green; /*!< the default color green */ - uint32_t layer_default_blue; /*!< the default color blue */ + uint8_t layer_sa; /*!< specified alpha */ + uint8_t layer_default_alpha; /*!< the default color alpha */ + uint8_t layer_default_red; /*!< the default color red */ + uint8_t layer_default_green; /*!< the default color green */ + uint8_t layer_default_blue; /*!< the default color blue */ uint32_t layer_acf1; /*!< alpha calculation factor 1 of blending method */ uint32_t layer_acf2; /*!< alpha calculation factor 2 of blending method */ uint32_t layer_frame_bufaddr; /*!< frame buffer base address */ - uint32_t layer_frame_buf_stride_offset; /*!< frame buffer stride offset */ - uint32_t layer_frame_line_length; /*!< frame line length */ - uint32_t layer_frame_total_line_number; /*!< frame total line number */ -}tli_layer_parameter_struct; + uint16_t layer_frame_buf_stride_offset; /*!< frame buffer stride offset */ + uint16_t layer_frame_line_length; /*!< frame line length */ + uint16_t layer_frame_total_line_number; /*!< frame total line number */ +}tli_layer_parameter_struct; /* TLI layer LUT parameter struct definitions */ typedef struct -{ +{ uint32_t layer_table_addr; /*!< look up table write address */ - uint32_t layer_lut_channel_red; /*!< red channel of a LUT entry */ - uint32_t layer_lut_channel_green; /*!< green channel of a LUT entry */ - uint32_t layer_lut_channel_blue; /*!< blue channel of a LUT entry */ -}tli_layer_lut_parameter_struct; + uint8_t layer_lut_channel_red; /*!< red channel of a LUT entry */ + uint8_t layer_lut_channel_green; /*!< green channel of a LUT entry */ + uint8_t layer_lut_channel_blue; /*!< blue channel of a LUT entry */ +}tli_layer_lut_parameter_struct; /* packeted pixel format */ -typedef enum +typedef enum { - LAYER_PPF_ARGB8888, /*!< layerx pixel format ARGB8888 */ - LAYER_PPF_RGB888, /*!< layerx pixel format RGB888 */ - LAYER_PPF_RGB565, /*!< layerx pixel format RGB565 */ - LAYER_PPF_ARGB1555, /*!< layerx pixel format ARGB1555 */ - LAYER_PPF_ARGB4444, /*!< layerx pixel format ARGB4444 */ - LAYER_PPF_L8, /*!< layerx pixel format L8 */ - LAYER_PPF_AL44, /*!< layerx pixel format AL44 */ - LAYER_PPF_AL88 /*!< layerx pixel format AL88 */ -} tli_layer_ppf_enum; + LAYER_PPF_ARGB8888, /*!< layerx pixel format ARGB8888 */ + LAYER_PPF_RGB888, /*!< layerx pixel format RGB888 */ + LAYER_PPF_RGB565, /*!< layerx pixel format RGB565 */ + LAYER_PPF_ARGB1555, /*!< layerx pixel format ARGB1555 */ + LAYER_PPF_ARGB4444, /*!< layerx pixel format ARGB4444 */ + LAYER_PPF_L8, /*!< layerx pixel format L8 */ + LAYER_PPF_AL44, /*!< layerx pixel format AL44 */ + LAYER_PPF_AL88 /*!< layerx pixel format AL88 */ +}tli_layer_ppf_enum; -/* layer reload configure */ -#define TLI_FRAME_BLANK_RELOAD_EN ((uint8_t)0x00U) /*!< the layer configuration will be reloaded at frame blank */ -#define TLI_REQUEST_RELOAD_EN ((uint8_t)0x01U) /*!< the layer configuration will be reloaded after this bit sets */ +/* TLI flags */ +#define TLI_FLAG_VDE TLI_STAT_VDE /*!< current VDE status */ +#define TLI_FLAG_HDE TLI_STAT_HDE /*!< current HDE status */ +#define TLI_FLAG_VS TLI_STAT_VS /*!< current VS status of the TLI */ +#define TLI_FLAG_HS TLI_STAT_HS /*!< current HS status of the TLI */ +#define TLI_FLAG_LM BIT(0) | BIT(31) /*!< line mark interrupt flag */ +#define TLI_FLAG_FE BIT(1) | BIT(31) /*!< FIFO error interrupt flag */ +#define TLI_FLAG_TE BIT(2) | BIT(31) /*!< transaction error interrupt flag */ +#define TLI_FLAG_LCR BIT(3) | BIT(31) /*!< layer configuration reloaded interrupt flag */ -/* dither Function */ -#define TLI_DITHER_DISABLE ((uint8_t)0x00U) /*!< dither function disable */ -#define TLI_DITHER_ENABLE ((uint8_t)0x01U) /*!< dither function enable */ +/* TLI interrupt enable or disable */ +#define TLI_INT_LM BIT(0) /*!< line mark interrupt */ +#define TLI_INT_FE BIT(1) /*!< FIFO error interrupt */ +#define TLI_INT_TE BIT(2) /*!< transaction error interrupt */ +#define TLI_INT_LCR BIT(3) /*!< layer configuration reloaded interrupt */ -/* horizontal pulse polarity selection */ - -#define TLI_HSYN_ACTLIVE_LOW ((uint32_t)0x00000000U) /*!< horizontal synchronous pulse active low */ -#define TLI_HSYN_ACTLIVE_HIGHT TLI_CTL_HPPS /*!< horizontal synchronous pulse active high */ - - -/* vertical pulse polarity selection */ - -#define TLI_VSYN_ACTLIVE_LOW ((uint32_t)0x00000000U) /*!< vertical synchronous pulse active low */ -#define TLI_VSYN_ACTLIVE_HIGHT TLI_CTL_VPPS /*!< vertical synchronous pulse active high */ +/* TLI interrupt flag */ +#define TLI_INT_FLAG_LM BIT(0) /*!< line mark interrupt flag */ +#define TLI_INT_FLAG_FE BIT(1) /*!< FIFO error interrupt flag */ +#define TLI_INT_FLAG_TE BIT(2) /*!< transaction error interrupt flag */ +#define TLI_INT_FLAG_LCR BIT(3) /*!< layer configuration reloaded interrupt flag */ +/* layer reload configure */ +#define TLI_FRAME_BLANK_RELOAD_EN ((uint8_t)0x00U) /*!< the layer configuration will be reloaded at frame blank */ +#define TLI_REQUEST_RELOAD_EN ((uint8_t)0x01U) /*!< the layer configuration will be reloaded after this bit sets */ -/* pixel Clock Polarity Selection */ +/* dither function */ +#define TLI_DITHER_DISABLE ((uint8_t)0x00U) /*!< dither function disable */ +#define TLI_DITHER_ENABLE ((uint8_t)0x01U) /*!< dither function enable */ -#define TLI_PIXEL_CLOCK_TLI ((uint32_t)0x00000000U) /*!< pixel clock is TLI clock */ -#define TLI_PIXEL_CLOCK_INVERTEDTLI TLI_CTL_CLKPS /*!< pixel clock is inverted TLI clock */ +/* horizontal pulse polarity selection */ +#define TLI_HSYN_ACTLIVE_LOW ((uint32_t)0x00000000U) /*!< horizontal synchronous pulse active low */ +#define TLI_HSYN_ACTLIVE_HIGHT TLI_CTL_HPPS /*!< horizontal synchronous pulse active high */ +/* vertical pulse polarity selection */ +#define TLI_VSYN_ACTLIVE_LOW ((uint32_t)0x00000000U) /*!< vertical synchronous pulse active low */ +#define TLI_VSYN_ACTLIVE_HIGHT TLI_CTL_VPPS /*!< vertical synchronous pulse active high */ -/* data Enable Polarity Selection */ +/* pixel clock polarity selection */ +#define TLI_PIXEL_CLOCK_TLI ((uint32_t)0x00000000U) /*!< pixel clock is TLI clock */ +#define TLI_PIXEL_CLOCK_INVERTEDTLI TLI_CTL_CLKPS /*!< pixel clock is inverted TLI clock */ -#define TLI_DE_ACTLIVE_LOW ((uint32_t)0x00000000U) /*!< data enable active low */ -#define TLI_DE_ACTLIVE_HIGHT TLI_CTL_DEPS /*!< data enable active high */ +/* data enable polarity selection */ +#define TLI_DE_ACTLIVE_LOW ((uint32_t)0x00000000U) /*!< data enable active low */ +#define TLI_DE_ACTLIVE_HIGHT TLI_CTL_DEPS /*!< data enable active high */ /* alpha calculation factor 1 of blending method */ -#define LxBLEND_ACF1(regval) (BITS(8,10) & ((regval)<<8)) -#define LAYER_ACF1_SA LxBLEND_ACF1(4) /*!< normalization specified alpha */ -#define LAYER_ACF1_PASA LxBLEND_ACF1(6) /*!< normalization pixel alpha * normalization specified alpha */ +#define LxBLEND_ACF1(regval) (BITS(8,10) & ((uint32_t)(regval)<<8)) +#define LAYER_ACF1_SA LxBLEND_ACF1(4) /*!< normalization specified alpha */ +#define LAYER_ACF1_PASA LxBLEND_ACF1(6) /*!< normalization pixel alpha * normalization specified alpha */ -/* alpha calculation factor 2 of blending method*/ -#define LxBLEND_ACF2(regval) (BITS(0,2) & ((regval))) -#define LAYER_ACF2_SA LxBLEND_ACF2(5) /*!< normalization specified alpha */ -#define LAYER_ACF2_PASA LxBLEND_ACF2(7) /*!< normalization pixel alpha x normalization specified alpha */ -/* function declarations */ +/* alpha calculation factor 2 of blending method */ +#define LxBLEND_ACF2(regval) (BITS(0,2) & ((uint32_t)(regval))) +#define LAYER_ACF2_SA LxBLEND_ACF2(5) /*!< normalization specified alpha */ +#define LAYER_ACF2_PASA LxBLEND_ACF2(7) /*!< normalization pixel alpha * normalization specified alpha */ -/* deinitialize TLI */ +/* function declarations */ +/* initialization functions, TLI enable or disable, TLI reload mode configuration */ +/* deinitialize TLI registers */ void tli_deinit(void); +/* initialize the parameters of TLI parameter structure with the default values, it is suggested + that call this function after a tli_parameter_struct structure is defined */ +void tli_struct_para_init(tli_parameter_struct *tli_struct); /* initialize TLI */ void tli_init(tli_parameter_struct *tli_struct); -/* TLI dither function enable */ -void tli_dither_config(uint8_t ditherstat); +/* configure TLI dither function */ +void tli_dither_config(uint8_t dither_stat); /* enable TLI */ void tli_enable(void); /* disable TLI */ void tli_disable(void); -/* TLI reload mode config*/ -void tli_reload_config(uint8_t reloadmod); - -/* TLI interrupt enable */ -void tli_interrupt_enable(uint32_t inttype); -/* TLI interrupt disable */ -void tli_interrupt_disable(uint32_t inttype); -/* get TLI interrupt flag */ -FlagStatus tli_interrupt_flag_get(uint32_t intflag); -/* clear TLI interrupt flag */ -void tli_interrupt_flag_clear(uint32_t intflag); - -/* set line mark value */ -void tli_line_mark_set(uint32_t linenum); -/* get current displayed position */ -uint32_t tli_current_pos_get(void); -/* get TLI state */ -FlagStatus tli_flag_get(uint32_t state); +/* configurate TLI reload mode */ +void tli_reload_config(uint8_t reload_mod); -/* TLI layer enable */ +/* TLI layer configuration functions */ +/* initialize the parameters of TLI layer structure with the default values, it is suggested + that call this function after a tli_layer_parameter_struct structure is defined */ +void tli_layer_struct_para_init(tli_layer_parameter_struct *layer_struct); +/* initialize TLI layer */ +void tli_layer_init(uint32_t layerx,tli_layer_parameter_struct *layer_struct); +/* reconfigure window position */ +void tli_layer_window_offset_modify(uint32_t layerx,uint16_t offset_x,uint16_t offset_y); +/* initialize the parameters of TLI layer LUT structure with the default values, it is suggested + that call this function after a tli_layer_lut_parameter_struct structure is defined */ +void tli_lut_struct_para_init(tli_layer_lut_parameter_struct *lut_struct); +/* initialize TLI layer LUT */ +void tli_lut_init(uint32_t layerx,tli_layer_lut_parameter_struct *lut_struct); +/* initialize TLI layer color key */ +void tli_color_key_init(uint32_t layerx,uint8_t redkey,uint8_t greenkey,uint8_t bluekey); +/* enable TLI layer */ void tli_layer_enable(uint32_t layerx); -/* TLI layer disable */ +/* disable TLI layer */ void tli_layer_disable(uint32_t layerx); -/* TLI layer color keying enable */ +/* enable TLI layer color keying */ void tli_color_key_enable(uint32_t layerx); -/* TLI layer color keying disable */ +/* disable TLI layer color keying */ void tli_color_key_disable(uint32_t layerx); -/* TLI layer LUT enable */ +/* enable TLI layer LUT */ void tli_lut_enable(uint32_t layerx); -/* TLI layer LUT disable */ +/* disable TLI layer LUT */ void tli_lut_disable(uint32_t layerx); -/* TLI layer initialize */ -void tli_layer_init(uint32_t layerx,tli_layer_parameter_struct *layer_struct); -/* TLI layer initialize */ -void tli_layer_window_offset_modify(uint32_t layerx,uint32_t offset_x,uint32_t offset_y); -/* TLI layer lut initialize */ -void tli_lut_init(uint32_t layerx,tli_layer_lut_parameter_struct *lut_struct); -/* TLI layer key initialize */ -void tli_ckey_init(uint32_t layerx,uint32_t redkey,uint32_t greenkey,uint32_t bluekey); + +/* set line mark value */ +void tli_line_mark_set(uint16_t line_num); +/* get current displayed position */ +uint32_t tli_current_pos_get(void); + +/* flag and interrupt functions */ +/* enable TLI interrupt */ +void tli_interrupt_enable(uint32_t int_flag); +/* disable TLI interrupt */ +void tli_interrupt_disable(uint32_t int_flag); +/* get TLI interrupt flag */ +FlagStatus tli_interrupt_flag_get(uint32_t int_flag); +/* clear TLI interrupt flag */ +void tli_interrupt_flag_clear(uint32_t int_flag); +/* get TLI flag or state in TLI_INTF register or TLI_STAT register */ +FlagStatus tli_flag_get(uint32_t flag); #endif /* GD32F4XX_TLI_H */ diff --git a/bsp/gd32450z-eval/Libraries/GD32F4xx_standard_peripheral/Include/gd32f4xx_trng.h b/bsp/gd32450z-eval/Libraries/GD32F4xx_standard_peripheral/Include/gd32f4xx_trng.h index 7925b91af3..f321b15d28 100644 --- a/bsp/gd32450z-eval/Libraries/GD32F4xx_standard_peripheral/Include/gd32f4xx_trng.h +++ b/bsp/gd32450z-eval/Libraries/GD32F4xx_standard_peripheral/Include/gd32f4xx_trng.h @@ -1,12 +1,37 @@ /*! - \file gd32f4xx_trng.h - \brief definitions for the TRNG + \file gd32f4xx_trng.h + \brief definitions for the TRNG + + \version 2016-08-15, V1.0.0, firmware for GD32F4xx + \version 2018-12-12, V2.0.0, firmware for GD32F4xx + \version 2020-09-30, V2.1.0, firmware for GD32F4xx */ /* - Copyright (C) 2016 GigaDevice + Copyright (c) 2020, GigaDevice Semiconductor Inc. + + Redistribution and use in source and binary forms, with or without modification, +are permitted provided that the following conditions are met: + + 1. Redistributions of source code must retain the above copyright notice, this + list of conditions and the following disclaimer. + 2. Redistributions in binary form must reproduce the above copyright notice, + this list of conditions and the following disclaimer in the documentation + and/or other materials provided with the distribution. + 3. Neither the name of the copyright holder nor the names of its contributors + may be used to endorse or promote products derived from this software without + specific prior written permission. - 2016-08-15, V1.0.0, firmware for GD32F4xx + THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED +WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. +IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, +INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT +NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR +PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, +WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY +OF SUCH DAMAGE. */ #ifndef GD32F4XX_TRNG_H @@ -14,13 +39,13 @@ #include "gd32f4xx.h" -/* EXTI definitions */ +/* TRNG definitions */ #define TRNG TRNG_BASE /* registers definitions */ -#define TRNG_CTL REG32(TRNG + 0x00U) /*!< interrupt enable register */ -#define TRNG_STAT REG32(TRNG + 0x04U) /*!< event enable register */ -#define TRNG_DATA REG32(TRNG + 0x08U) /*!< rising edge trigger enable register */ +#define TRNG_CTL REG32(TRNG + 0x00U) /*!< control register */ +#define TRNG_STAT REG32(TRNG + 0x04U) /*!< status register */ +#define TRNG_DATA REG32(TRNG + 0x08U) /*!< data register */ /* bits definitions */ /* TRNG_CTL */ @@ -40,7 +65,7 @@ /* constants definitions */ /* trng status flag */ typedef enum -{ +{ TRNG_FLAG_DRDY = TRNG_STAT_DRDY, /*!< random Data ready status */ TRNG_FLAG_CECS = TRNG_STAT_CECS, /*!< clock error current status */ TRNG_FLAG_SECS = TRNG_STAT_SECS /*!< seed error current status */ @@ -54,6 +79,7 @@ typedef enum }trng_int_flag_enum; /* function declarations */ +/* initialization functions */ /* deinitialize the TRNG */ void trng_deinit(void); /* enable the TRNG interface */ @@ -62,14 +88,14 @@ void trng_enable(void); void trng_disable(void); /* get the true random data */ uint32_t trng_get_true_random_data(void); -/* get the trng status flags */ -FlagStatus trng_flag_get(trng_flag_enum flag); -/* clear the trng status flags */ -void trng_flag_clear(trng_flag_enum flag); -/* the trng interrupt enable */ + +/* flag & interrupt functions */ +/* trng interrupt enable */ void trng_interrupt_enable(void); -/* the trng interrupt disable */ +/* trng interrupt disable */ void trng_interrupt_disable(void); +/* get the trng status flags */ +FlagStatus trng_flag_get(trng_flag_enum flag); /* get the trng interrupt flags */ FlagStatus trng_interrupt_flag_get(trng_int_flag_enum int_flag); /* clear the trng interrupt flags */ diff --git a/bsp/gd32450z-eval/Libraries/GD32F4xx_standard_peripheral/Include/gd32f4xx_usart.h b/bsp/gd32450z-eval/Libraries/GD32F4xx_standard_peripheral/Include/gd32f4xx_usart.h index 5350f5e5b5..3cd49d827f 100644 --- a/bsp/gd32450z-eval/Libraries/GD32F4xx_standard_peripheral/Include/gd32f4xx_usart.h +++ b/bsp/gd32450z-eval/Libraries/GD32F4xx_standard_peripheral/Include/gd32f4xx_usart.h @@ -1,12 +1,37 @@ /*! - \file gd32f4xx_usart.h - \brief definitions for the USART + \file gd32f4xx_usart.h + \brief definitions for the USART + + \version 2016-08-15, V1.0.0, firmware for GD32F4xx + \version 2018-12-12, V2.0.0, firmware for GD32F4xx + \version 2020-09-30, V2.1.0, firmware for GD32F4xx */ /* - Copyright (C) 2016 GigaDevice + Copyright (c) 2020, GigaDevice Semiconductor Inc. + + Redistribution and use in source and binary forms, with or without modification, +are permitted provided that the following conditions are met: + + 1. Redistributions of source code must retain the above copyright notice, this + list of conditions and the following disclaimer. + 2. Redistributions in binary form must reproduce the above copyright notice, + this list of conditions and the following disclaimer in the documentation + and/or other materials provided with the distribution. + 3. Neither the name of the copyright holder nor the names of its contributors + may be used to endorse or promote products derived from this software without + specific prior written permission. - 2016-08-15, V1.0.0, firmware for GD32F4xx + THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED +WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. +IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, +INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT +NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR +PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, +WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY +OF SUCH DAMAGE. */ #ifndef GD32F4XX_USART_H @@ -14,8 +39,8 @@ #include "gd32f4xx.h" -/* USARTx(x=0,1) definitions */ -#define USART1 USART_BASE +/* USARTx(x=0,1,2,5)/UARTx(x=3,4,6,7) definitions */ +#define USART1 USART_BASE /*!< USART1 base address */ #define USART2 (USART_BASE+0x00000400U) /*!< USART2 base address */ #define UART3 (USART_BASE+0x00000800U) /*!< UART3 base address */ #define UART4 (USART_BASE+0x00000C00U) /*!< UART4 base address */ @@ -102,7 +127,7 @@ /* USARTx_GP */ #define USART_GP_PSC BITS(0,7) /*!< prescaler value for dividing the system clock */ #define USART_GP_GUAT BITS(8,15) /*!< guard time value in smartcard mode */ - + /* USARTx_CTL3 */ #define USART_CTL3_RTEN BIT(0) /*!< receiver timeout enable */ #define USART_CTL3_SCRTNUM BITS(1,3) /*!< smartcard auto-retry number */ @@ -131,59 +156,85 @@ /* constants definitions */ /* define the USART bit position and its register index offset */ #define USART_REGIDX_BIT(regidx, bitpos) (((uint32_t)(regidx) << 6) | (uint32_t)(bitpos)) -#define USART_REG_VAL(usartx, offset) (REG32((usartx) + ((uint32_t)(offset) >> 6))) +#define USART_REG_VAL(usartx, offset) (REG32((usartx) + (((uint32_t)(offset) & 0xFFFFU) >> 6))) #define USART_BIT_POS(val) ((uint32_t)(val) & 0x1FU) +#define USART_REGIDX_BIT2(regidx, bitpos, regidx2, bitpos2) (((uint32_t)(regidx2) << 22) | (uint32_t)((bitpos2) << 16)\ + | (((uint32_t)(regidx) << 6) | (uint32_t)(bitpos))) +#define USART_REG_VAL2(usartx, offset) (REG32((usartx) + ((uint32_t)(offset) >> 22))) +#define USART_BIT_POS2(val) (((uint32_t)(val) & 0x1F0000U) >> 16) /* register offset */ -#define STAT0_REG_OFFSET 0x00U /*!< STAT0 register offset */ -#define STAT1_REG_OFFSET 0x88U /*!< STAT1 register offset */ -#define CHC_REG_OFFSET 0xC0U /*!< CHC register offset */ -#define CTL0_REG_OFFSET 0x0CU /*!< CTL0 register offset */ -#define CTL1_REG_OFFSET 0x10U /*!< CTL1 register offset */ -#define CTL2_REG_OFFSET 0x14U /*!< CTL2 register offset */ -#define CTL3_REG_OFFSET 0x80U /*!< CTL2 register offset */ +#define USART_STAT0_REG_OFFSET 0x00U /*!< STAT0 register offset */ +#define USART_STAT1_REG_OFFSET 0x88U /*!< STAT1 register offset */ +#define USART_CTL0_REG_OFFSET 0x0CU /*!< CTL0 register offset */ +#define USART_CTL1_REG_OFFSET 0x10U /*!< CTL1 register offset */ +#define USART_CTL2_REG_OFFSET 0x14U /*!< CTL2 register offset */ +#define USART_CTL3_REG_OFFSET 0x80U /*!< CTL3 register offset */ +#define USART_CHC_REG_OFFSET 0xC0U /*!< CHC register offset */ /* USART flags */ typedef enum { /* flags in STAT0 register */ - USART_FLAG_CTSF = USART_REGIDX_BIT(STAT0_REG_OFFSET, 9U), /*!< CTS change flag */ - USART_FLAG_LBDF = USART_REGIDX_BIT(STAT0_REG_OFFSET, 8U), /*!< LIN break detected flag */ - USART_FLAG_TBE = USART_REGIDX_BIT(STAT0_REG_OFFSET, 7U), /*!< transmit data buffer empty */ - USART_FLAG_TC = USART_REGIDX_BIT(STAT0_REG_OFFSET, 6U), /*!< transmission complete */ - USART_FLAG_RBNE = USART_REGIDX_BIT(STAT0_REG_OFFSET, 5U), /*!< read data buffer not empty */ - USART_FLAG_IDLEF = USART_REGIDX_BIT(STAT0_REG_OFFSET, 4U), /*!< IDLE frame detected flag */ - USART_FLAG_ORERR = USART_REGIDX_BIT(STAT0_REG_OFFSET, 3U), /*!< overrun error */ - USART_FLAG_NERR = USART_REGIDX_BIT(STAT0_REG_OFFSET, 2U), /*!< noise error flag */ - USART_FLAG_FERR = USART_REGIDX_BIT(STAT0_REG_OFFSET, 1U), /*!< frame error flag */ - USART_FLAG_PERR = USART_REGIDX_BIT(STAT0_REG_OFFSET, 0U), /*!< parity error flag */ + USART_FLAG_CTS = USART_REGIDX_BIT(USART_STAT0_REG_OFFSET, 9U), /*!< CTS change flag */ + USART_FLAG_LBD = USART_REGIDX_BIT(USART_STAT0_REG_OFFSET, 8U), /*!< LIN break detected flag */ + USART_FLAG_TBE = USART_REGIDX_BIT(USART_STAT0_REG_OFFSET, 7U), /*!< transmit data buffer empty */ + USART_FLAG_TC = USART_REGIDX_BIT(USART_STAT0_REG_OFFSET, 6U), /*!< transmission complete */ + USART_FLAG_RBNE = USART_REGIDX_BIT(USART_STAT0_REG_OFFSET, 5U), /*!< read data buffer not empty */ + USART_FLAG_IDLE = USART_REGIDX_BIT(USART_STAT0_REG_OFFSET, 4U), /*!< IDLE frame detected flag */ + USART_FLAG_ORERR = USART_REGIDX_BIT(USART_STAT0_REG_OFFSET, 3U), /*!< overrun error */ + USART_FLAG_NERR = USART_REGIDX_BIT(USART_STAT0_REG_OFFSET, 2U), /*!< noise error flag */ + USART_FLAG_FERR = USART_REGIDX_BIT(USART_STAT0_REG_OFFSET, 1U), /*!< frame error flag */ + USART_FLAG_PERR = USART_REGIDX_BIT(USART_STAT0_REG_OFFSET, 0U), /*!< parity error flag */ /* flags in STAT1 register */ - USART_FLAG_BSY = USART_REGIDX_BIT(STAT1_REG_OFFSET, 16U), /*!< busy flag */ - USART_FLAG_EBF = USART_REGIDX_BIT(STAT1_REG_OFFSET, 12U), /*!< end of block flag */ - USART_FLAG_RTF = USART_REGIDX_BIT(STAT1_REG_OFFSET, 11U), /*!< receiver timeout flag */ + USART_FLAG_BSY = USART_REGIDX_BIT(USART_STAT1_REG_OFFSET, 16U), /*!< busy flag */ + USART_FLAG_EB = USART_REGIDX_BIT(USART_STAT1_REG_OFFSET, 12U), /*!< end of block flag */ + USART_FLAG_RT = USART_REGIDX_BIT(USART_STAT1_REG_OFFSET, 11U), /*!< receiver timeout flag */ /* flags in CHC register */ - USART_FLAG_EPERR = USART_REGIDX_BIT(CHC_REG_OFFSET, 8U), /*!< early parity error flag */ + USART_FLAG_EPERR = USART_REGIDX_BIT(USART_CHC_REG_OFFSET, 8U), /*!< early parity error flag */ }usart_flag_enum; /* USART interrupt flags */ typedef enum { /* interrupt flags in CTL0 register */ - USART_INT_PERRIE = USART_REGIDX_BIT(CTL0_REG_OFFSET, 8U), /*!< parity error interrupt */ - USART_INT_TBEIE = USART_REGIDX_BIT(CTL0_REG_OFFSET, 7U), /*!< transmitter buffer empty interrupt */ - USART_INT_TCIE = USART_REGIDX_BIT(CTL0_REG_OFFSET, 6U), /*!< transmission complete interrupt */ - USART_INT_RBNEIE = USART_REGIDX_BIT(CTL0_REG_OFFSET, 5U), /*!< read data buffer not empty interrupt and overrun error interrupt */ - USART_INT_IDLEIE = USART_REGIDX_BIT(CTL0_REG_OFFSET, 4U), /*!< IDLE line detected interrupt */ + USART_INT_FLAG_PERR = USART_REGIDX_BIT2(USART_CTL0_REG_OFFSET, 8U, USART_STAT0_REG_OFFSET, 0U), /*!< parity error interrupt and flag */ + USART_INT_FLAG_TBE = USART_REGIDX_BIT2(USART_CTL0_REG_OFFSET, 7U, USART_STAT0_REG_OFFSET, 7U), /*!< transmitter buffer empty interrupt and flag */ + USART_INT_FLAG_TC = USART_REGIDX_BIT2(USART_CTL0_REG_OFFSET, 6U, USART_STAT0_REG_OFFSET, 6U), /*!< transmission complete interrupt and flag */ + USART_INT_FLAG_RBNE = USART_REGIDX_BIT2(USART_CTL0_REG_OFFSET, 5U, USART_STAT0_REG_OFFSET, 5U), /*!< read data buffer not empty interrupt and flag */ + USART_INT_FLAG_RBNE_ORERR = USART_REGIDX_BIT2(USART_CTL0_REG_OFFSET, 5U, USART_STAT0_REG_OFFSET, 3U), /*!< read data buffer not empty interrupt and overrun error flag */ + USART_INT_FLAG_IDLE = USART_REGIDX_BIT2(USART_CTL0_REG_OFFSET, 4U, USART_STAT0_REG_OFFSET, 4U), /*!< IDLE line detected interrupt and flag */ /* interrupt flags in CTL1 register */ - USART_INT_LBDIE = USART_REGIDX_BIT(CTL1_REG_OFFSET, 6U), /*!< LIN break detected interrupt */ + USART_INT_FLAG_LBD = USART_REGIDX_BIT2(USART_CTL1_REG_OFFSET, 6U, USART_STAT0_REG_OFFSET, 8U), /*!< LIN break detected interrupt and flag */ /* interrupt flags in CTL2 register */ - USART_INT_CTSIE = USART_REGIDX_BIT(CTL2_REG_OFFSET, 10U), /*!< CTS interrupt */ - USART_INT_ERRIE = USART_REGIDX_BIT(CTL2_REG_OFFSET, 0U), /*!< error interrupt */ + USART_INT_FLAG_CTS = USART_REGIDX_BIT2(USART_CTL2_REG_OFFSET, 10U, USART_STAT0_REG_OFFSET, 9U), /*!< CTS interrupt and flag */ + USART_INT_FLAG_ERR_ORERR = USART_REGIDX_BIT2(USART_CTL2_REG_OFFSET, 0U, USART_STAT0_REG_OFFSET, 3U), /*!< error interrupt and overrun error */ + USART_INT_FLAG_ERR_NERR = USART_REGIDX_BIT2(USART_CTL2_REG_OFFSET, 0U, USART_STAT0_REG_OFFSET, 2U), /*!< error interrupt and noise error flag */ + USART_INT_FLAG_ERR_FERR = USART_REGIDX_BIT2(USART_CTL2_REG_OFFSET, 0U, USART_STAT0_REG_OFFSET, 1U), /*!< error interrupt and frame error flag */ /* interrupt flags in CTL3 register */ - USART_INT_EBIE = USART_REGIDX_BIT(CTL3_REG_OFFSET, 5U), /*!< interrupt enable bit of end of block event */ - USART_INT_RTIE = USART_REGIDX_BIT(CTL3_REG_OFFSET, 4U), /*!< interrupt enable bit of receive timeout event */ + USART_INT_FLAG_EB = USART_REGIDX_BIT2(USART_CTL3_REG_OFFSET, 5U, USART_STAT1_REG_OFFSET, 12U), /*!< interrupt enable bit of end of block event and flag */ + USART_INT_FLAG_RT = USART_REGIDX_BIT2(USART_CTL3_REG_OFFSET, 4U, USART_STAT1_REG_OFFSET, 11U), /*!< interrupt enable bit of receive timeout event and flag */ }usart_interrupt_flag_enum; +/* USART interrupt flags */ +typedef enum +{ + /* interrupt in CTL0 register */ + USART_INT_PERR = USART_REGIDX_BIT(USART_CTL0_REG_OFFSET, 8U), /*!< parity error interrupt */ + USART_INT_TBE = USART_REGIDX_BIT(USART_CTL0_REG_OFFSET, 7U), /*!< transmitter buffer empty interrupt */ + USART_INT_TC = USART_REGIDX_BIT(USART_CTL0_REG_OFFSET, 6U), /*!< transmission complete interrupt */ + USART_INT_RBNE = USART_REGIDX_BIT(USART_CTL0_REG_OFFSET, 5U), /*!< read data buffer not empty interrupt and overrun error interrupt */ + USART_INT_IDLE = USART_REGIDX_BIT(USART_CTL0_REG_OFFSET, 4U), /*!< IDLE line detected interrupt */ + /* interrupt in CTL1 register */ + USART_INT_LBD = USART_REGIDX_BIT(USART_CTL1_REG_OFFSET, 6U), /*!< LIN break detected interrupt */ + /* interrupt in CTL2 register */ + USART_INT_CTS = USART_REGIDX_BIT(USART_CTL2_REG_OFFSET, 10U), /*!< CTS interrupt */ + USART_INT_ERR = USART_REGIDX_BIT(USART_CTL2_REG_OFFSET, 0U), /*!< error interrupt */ + /* interrupt in CTL3 register */ + USART_INT_EB = USART_REGIDX_BIT(USART_CTL3_REG_OFFSET, 5U), /*!< interrupt enable bit of end of block event */ + USART_INT_RT = USART_REGIDX_BIT(USART_CTL3_REG_OFFSET, 4U), /*!< interrupt enable bit of receive timeout event */ +}usart_interrupt_enum; + /* USART invert configure */ typedef enum { @@ -211,8 +262,8 @@ typedef enum /* USART parity bits definitions */ #define CTL0_PM(regval) (BITS(9,10) & ((uint32_t)(regval) << 9)) #define USART_PM_NONE CTL0_PM(0) /*!< no parity */ -#define USART_PM_ODD CTL0_PM(2) /*!< odd parity */ -#define USART_PM_EVEN CTL0_PM(3) /*!< even parity */ +#define USART_PM_EVEN CTL0_PM(2) /*!< even parity */ +#define USART_PM_ODD CTL0_PM(3) /*!< odd parity */ /* USART wakeup method in mute mode */ #define CTL0_WM(regval) (BIT(11) & ((uint32_t)(regval) << 11)) @@ -306,30 +357,6 @@ typedef enum #define USART_HCM_NONE CHC_HCM(0) /*!< nRTS signal equals to the rxne status register */ #define USART_HCM_EN CHC_HCM(1) /*!< nRTS signal is set when the last data bit has been sampled */ -/* interrupt enable in USART_CTL0 */ -#define USART_INTEN_PERRIE ((uint32_t)0x10000100U) /*!< parity error interrupt */ -#define USART_INTEN_TBEIE ((uint32_t)0x10000080U) /*!< transmitter buffer empty interrupt */ -#define USART_INTEN_TCIE ((uint32_t)0x10000040U) /*!< transmission complete interrupt */ -#define USART_INTEN_RBNEIE ((uint32_t)0x10000020U) /*!< read data buffer not empty interrupt and overrun error interrupt */ -#define USART_INTEN_IDLEIE ((uint32_t)0x10000010U) /*!< IDLE line detected interrupt */ - -/* interrupt enable flag in USART_CTL1 */ -#define USART_INTEN_LBDIE ((uint32_t)0x20000040U) /*!< LIN break detected interrupt */ - -/* interrupt enable flag in USART_CTL2 */ -#define USART_INTEN_ERRIE ((uint32_t)0x40000001U) /*!< error interrupt */ -#define USART_INTEN_CTSIE ((uint32_t)0x40000400U) /*!< CTS interrupt*/ - -/* interrupt enable flag in USART_CTL3 */ -#define USART_INTEN_RTIE ((uint32_t)0x80000010U) /*!< interrupt enable bit of receive timeout event */ -#define USART_INTEN_EBIE ((uint32_t)0x80000020U) /*!< interrupt enable bit of end of block event */ - -#define USART_INTEN_MASK ((uint32_t)0x00000FFFU) /*!< USART interrupt mask */ -#define USART_INTS_CTL0 ((uint32_t)0x10000000U) /*!< interrupt in USART_CTL0 */ -#define USART_INTS_CTL1 ((uint32_t)0x20000000U) /*!< interrupt in USART_CTL1 */ -#define USART_INTS_CTL2 ((uint32_t)0x40000000U) /*!< interrupt in USART_CTL2 */ -#define USART_INTS_CTL3 ((uint32_t)0x80000000U) /*!< interrupt in USART_CTL3 */ - /* function declarations */ /* initialization functions */ /* reset USART */ @@ -342,8 +369,6 @@ void usart_parity_config(uint32_t usart_periph, uint32_t paritycfg); void usart_word_length_set(uint32_t usart_periph, uint32_t wlen); /* configure usart stop bit length */ void usart_stop_bit_set(uint32_t usart_periph, uint32_t stblen); - -/* USART normal mode communication */ /* enable usart */ void usart_enable(uint32_t usart_periph); /* disable usart */ @@ -352,6 +377,8 @@ void usart_disable(uint32_t usart_periph); void usart_transmit_config(uint32_t usart_periph, uint32_t txconfig); /* configure USART receiver */ void usart_receive_config(uint32_t usart_periph, uint32_t rxconfig); + +/* USART normal mode communication */ /* data is transmitted/received with the LSB/MSB first */ void usart_data_first_config(uint32_t usart_periph, uint32_t msbf); /* configure USART inverted */ @@ -382,43 +409,43 @@ void usart_mute_mode_disable(uint32_t usart_periph); void usart_mute_mode_wakeup_config(uint32_t usart_periph, uint32_t wmehtod); /* LIN mode communication */ -/* LIN mode enable */ +/* enable LIN mode */ void usart_lin_mode_enable(uint32_t usart_periph); -/* LIN mode disable */ +/* disable LIN mode */ void usart_lin_mode_disable(uint32_t usart_periph); /* LIN break detection length */ -void usart_lin_break_dection_length_config(uint32_t usart_periph, uint32_t lblen); +void usart_lin_break_detection_length_config(uint32_t usart_periph, uint32_t lblen); /* send break frame */ void usart_send_break(uint32_t usart_periph); /* half-duplex communication */ -/* half-duplex enable */ +/* enable half-duplex mode */ void usart_halfduplex_enable(uint32_t usart_periph); -/* half-duplex disable */ +/* disable half-duplex mode */ void usart_halfduplex_disable(uint32_t usart_periph); /* synchronous communication */ -/* clock enable */ +/* enable CK pin in synchronous mode */ void usart_synchronous_clock_enable(uint32_t usart_periph); -/* clock disable */ +/* disable CK pin in synchronous mode */ void usart_synchronous_clock_disable(uint32_t usart_periph); /* configure usart synchronous mode parameters */ void usart_synchronous_clock_config(uint32_t usart_periph, uint32_t clen, uint32_t cph, uint32_t cpl); /* smartcard communication */ -/* guard time value configure in smartcard mode */ -void usart_guard_time_config(uint32_t usart_periph,uint32_t gaut); -/* smartcard mode enable */ +/* configure guard time value in smartcard mode */ +void usart_guard_time_config(uint32_t usart_periph, uint32_t guat); +/* enable smartcard mode */ void usart_smartcard_mode_enable(uint32_t usart_periph); -/* smartcard mode disable */ +/* disable smartcard mode */ void usart_smartcard_mode_disable(uint32_t usart_periph); -/* NACK enable in smartcard mode */ +/* enable NACK in smartcard mode */ void usart_smartcard_mode_nack_enable(uint32_t usart_periph); -/* NACK disable in smartcard mode */ +/* disable NACK in smartcard mode */ void usart_smartcard_mode_nack_disable(uint32_t usart_periph); -/* smartcard auto-retry number configure */ +/* configure smartcard auto-retry number */ void usart_smartcard_autoretry_config(uint32_t usart_periph, uint32_t scrtnum); -/* block length configure */ +/* configure block length */ void usart_block_length_config(uint32_t usart_periph, uint32_t bl); /* IrDA communication */ @@ -427,7 +454,7 @@ void usart_irda_mode_enable(uint32_t usart_periph); /* disable IrDA mode */ void usart_irda_mode_disable(uint32_t usart_periph); /* configure the peripheral clock prescaler */ -void usart_prescaler_config(uint32_t usart_periph, uint32_t psc); +void usart_prescaler_config(uint32_t usart_periph, uint8_t psc); /* configure IrDA low-power */ void usart_irda_lowpower_config(uint32_t usart_periph, uint32_t irlp); @@ -445,23 +472,24 @@ void usart_parity_check_coherence_config(uint32_t usart_periph, uint32_t pcm); /* configure hardware flow control coherence mode */ void usart_hardware_flow_coherence_config(uint32_t usart_periph, uint32_t hcm); +/* DMA communication */ /* configure USART DMA for reception */ void usart_dma_receive_config(uint32_t usart_periph, uint32_t dmacmd); /* configure USART DMA for transmission */ void usart_dma_transmit_config(uint32_t usart_periph, uint32_t dmacmd); -/* flag functions */ -/* get flag in STAT0/STAT1/CHC register */ +/* flag & interrupt functions */ +/* get flag in STAT0/STAT1 register */ FlagStatus usart_flag_get(uint32_t usart_periph, usart_flag_enum flag); -/* clear flag in STAT0/STAT1/CHC register */ +/* clear flag in STAT0/STAT1 register */ void usart_flag_clear(uint32_t usart_periph, usart_flag_enum flag); - -/* interrupt functions */ /* enable USART interrupt */ -void usart_interrupt_enable(uint32_t usart_periph, uint32_t int_flag); +void usart_interrupt_enable(uint32_t usart_periph, usart_interrupt_enum interrupt); /* disable USART interrupt */ -void usart_interrupt_disable(uint32_t usart_periph, uint32_t int_flag); -/* get USART interrupt enable flag */ -FlagStatus usart_interrupt_flag_get(uint32_t usart_periph, uint32_t int_flag); +void usart_interrupt_disable(uint32_t usart_periph, usart_interrupt_enum interrupt); +/* get USART interrupt and flag status */ +FlagStatus usart_interrupt_flag_get(uint32_t usart_periph, usart_interrupt_flag_enum int_flag); +/* clear interrupt flag in STAT0/STAT1 register */ +void usart_interrupt_flag_clear(uint32_t usart_periph, usart_interrupt_flag_enum int_flag); -#endif /* GD32F4XX_USART_H */ +#endif /* GD32F4XX_USART_H */ diff --git a/bsp/gd32450z-eval/Libraries/GD32F4xx_standard_peripheral/Include/gd32f4xx_wwdgt.h b/bsp/gd32450z-eval/Libraries/GD32F4xx_standard_peripheral/Include/gd32f4xx_wwdgt.h index d76cbce32c..525b9a6e5a 100644 --- a/bsp/gd32450z-eval/Libraries/GD32F4xx_standard_peripheral/Include/gd32f4xx_wwdgt.h +++ b/bsp/gd32450z-eval/Libraries/GD32F4xx_standard_peripheral/Include/gd32f4xx_wwdgt.h @@ -1,12 +1,37 @@ /*! - \file gd32f4xx_wwdgt.h - \brief definitions for the WWDGT + \file gd32f4xx_wwdgt.h + \brief definitions for the WWDGT + + \version 2016-08-15, V1.0.0, firmware for GD32F4xx + \version 2018-12-12, V2.0.0, firmware for GD32F4xx + \version 2020-09-30, V2.1.0, firmware for GD32F4xx */ /* - Copyright (C) 2016 GigaDevice + Copyright (c) 2020, GigaDevice Semiconductor Inc. + + Redistribution and use in source and binary forms, with or without modification, +are permitted provided that the following conditions are met: + + 1. Redistributions of source code must retain the above copyright notice, this + list of conditions and the following disclaimer. + 2. Redistributions in binary form must reproduce the above copyright notice, + this list of conditions and the following disclaimer in the documentation + and/or other materials provided with the distribution. + 3. Neither the name of the copyright holder nor the names of its contributors + may be used to endorse or promote products derived from this software without + specific prior written permission. - 2016-08-15, V1.0.0, firmware for GD32F4xx + THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED +WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. +IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, +INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT +NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR +PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, +WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY +OF SUCH DAMAGE. */ #ifndef GD32F4XX_WWDGT_H diff --git a/bsp/gd32450z-eval/Libraries/GD32F4xx_standard_peripheral/Source/gd32f4xx_adc.c b/bsp/gd32450z-eval/Libraries/GD32F4xx_standard_peripheral/Source/gd32f4xx_adc.c index 73f89207ba..f249e6c840 100644 --- a/bsp/gd32450z-eval/Libraries/GD32F4xx_standard_peripheral/Source/gd32f4xx_adc.c +++ b/bsp/gd32450z-eval/Libraries/GD32F4xx_standard_peripheral/Source/gd32f4xx_adc.c @@ -1,24 +1,67 @@ /*! - \file gd32f4xx_adc.c - \brief ADC driver + \file gd32f4xx_adc.c + \brief ADC driver + + \version 2016-08-15, V1.0.0, firmware for GD32F4xx + \version 2018-12-12, V2.0.0, firmware for GD32F4xx + \version 2020-09-30, V2.1.0, firmware for GD32F4xx */ /* - Copyright (C) 2016 GigaDevice + Copyright (c) 2020, GigaDevice Semiconductor Inc. + + Redistribution and use in source and binary forms, with or without modification, +are permitted provided that the following conditions are met: - 2016-08-15, V1.0.0, firmware for GD32F4xx + 1. Redistributions of source code must retain the above copyright notice, this + list of conditions and the following disclaimer. + 2. Redistributions in binary form must reproduce the above copyright notice, + this list of conditions and the following disclaimer in the documentation + and/or other materials provided with the distribution. + 3. Neither the name of the copyright holder nor the names of its contributors + may be used to endorse or promote products derived from this software without + specific prior written permission. + + THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED +WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. +IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, +INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT +NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR +PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, +WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY +OF SUCH DAMAGE. */ #include "gd32f4xx_adc.h" -#define REGULAR_CHANNEL_LENGTH_OFFSET ((uint32_t)20U) -#define INSERTED_CHANNEL_LENGTH_OFFSET ((uint32_t)20U) -#define REGULAR_DISCONTINUOUS_NUMBER ((uint32_t)13U) #define REGULAR_TRIGGER_MODE ((uint32_t)28U) #define INSERTED_TRIGGER_MODE ((uint32_t)20U) +/* discontinuous mode macro*/ +#define ADC_CHANNEL_LENGTH_SUBTRACT_ONE ((uint8_t)1U) + +/* ADC regular channel macro */ +#define ADC_REGULAR_CHANNEL_RANK_SIX ((uint8_t)6U) +#define ADC_REGULAR_CHANNEL_RANK_TWELVE ((uint8_t)12U) +#define ADC_REGULAR_CHANNEL_RANK_SIXTEEN ((uint8_t)16U) +#define ADC_REGULAR_CHANNEL_RANK_LENGTH ((uint8_t)5U) + +/* ADC sampling time macro */ +#define ADC_CHANNEL_SAMPLE_TEN ((uint8_t)10U) +#define ADC_CHANNEL_SAMPLE_EIGHTEEN ((uint8_t)18U) +#define ADC_CHANNEL_SAMPLE_LENGTH ((uint8_t)3U) + +/* ADC inserted channel macro */ +#define ADC_INSERTED_CHANNEL_RANK_LENGTH ((uint8_t)5U) +#define ADC_INSERTED_CHANNEL_SHIFT_LENGTH ((uint8_t)15U) + +/* ADC inserted channel offset macro */ +#define ADC_OFFSET_LENGTH ((uint8_t)3U) +#define ADC_OFFSET_SHIFT_LENGTH ((uint8_t)4U) /*! - \brief ADC reset + \brief reset ADC \param[in] none \param[out] none \retval none @@ -30,53 +73,174 @@ void adc_deinit(void) } /*! + \brief configure the ADC clock for all the ADCs + \param[in] prescaler: configure ADCs prescaler ratio + only one parameter can be selected which is shown as below: + \arg ADC_ADCCK_PCLK2_DIV2: PCLK2 div2 + \arg ADC_ADCCK_PCLK2_DIV4: PCLK2 div4 + \arg ADC_ADCCK_PCLK2_DIV6: PCLK2 div6 + \arg ADC_ADCCK_PCLK2_DIV8: PCLK2 div8 + \arg ADC_ADCCK_HCLK_DIV5: HCLK div5 + \arg ADC_ADCCK_HCLK_DIV6: HCLK div6 + \arg ADC_ADCCK_HCLK_DIV10: HCLK div10 + \arg ADC_ADCCK_HCLK_DIV20: HCLK div20 + \param[out] none + \retval none +*/ +void adc_clock_config(uint32_t prescaler) +{ + ADC_SYNCCTL &= ~((uint32_t)ADC_SYNCCTL_ADCCK); + ADC_SYNCCTL |= (uint32_t) prescaler; +} + +/*! + \brief enable or disable ADC special function + \param[in] adc_periph: ADCx,x=0,1,2 + \param[in] function: the function to config + only one parameter can be selected which is shown as below: + \arg ADC_SCAN_MODE: scan mode select + \arg ADC_INSERTED_CHANNEL_AUTO: inserted channel group convert automatically + \arg ADC_CONTINUOUS_MODE: continuous mode select + \param[in] newvalue: ENABLE or DISABLE + \param[out] none + \retval none +*/ +void adc_special_function_config(uint32_t adc_periph , uint32_t function , ControlStatus newvalue) +{ + if(newvalue){ + if(0U != (function & ADC_SCAN_MODE)){ + /* enable scan mode */ + ADC_CTL0(adc_periph) |= ADC_SCAN_MODE; + } + if(0U != (function & ADC_INSERTED_CHANNEL_AUTO)){ + /* enable inserted channel group convert automatically */ + ADC_CTL0(adc_periph) |= ADC_INSERTED_CHANNEL_AUTO; + } + if(0U != (function & ADC_CONTINUOUS_MODE)){ + /* enable continuous mode */ + ADC_CTL1(adc_periph) |= ADC_CONTINUOUS_MODE; + } + }else{ + if(0U != (function & ADC_SCAN_MODE)){ + /* disable scan mode */ + ADC_CTL0(adc_periph) &= ~ADC_SCAN_MODE; + } + if(0U != (function & ADC_INSERTED_CHANNEL_AUTO)){ + /* disable inserted channel group convert automatically */ + ADC_CTL0(adc_periph) &= ~ADC_INSERTED_CHANNEL_AUTO; + } + if(0U != (function & ADC_CONTINUOUS_MODE)){ + /* disable continuous mode */ + ADC_CTL1(adc_periph) &= ~ADC_CONTINUOUS_MODE; + } + } +} + +/*! + \brief configure ADC data alignment + \param[in] adc_periph: ADCx,x=0,1,2 + \param[in] data_alignment: data alignment select + only one parameter can be selected which is shown as below: + \arg ADC_DATAALIGN_RIGHT: LSB alignment + \arg ADC_DATAALIGN_LEFT: MSB alignment + \param[out] none + \retval none +*/ +void adc_data_alignment_config(uint32_t adc_periph , uint32_t data_alignment) +{ + if(ADC_DATAALIGN_RIGHT != data_alignment){ + /* MSB alignment */ + ADC_CTL1(adc_periph) |= ADC_CTL1_DAL; + }else{ + /* LSB alignment */ + ADC_CTL1(adc_periph) &= ~((uint32_t)ADC_CTL1_DAL); + } +} + +/*! \brief enable ADC interface \param[in] adc_periph: ADCx,x=0,1,2 - \param[in] none \param[out] none \retval none */ void adc_enable(uint32_t adc_periph) { - if(RESET == (ADC_CTL1(adc_periph) & ADC_CTL1_ADCON)){ - ADC_CTL1(adc_periph) |= (uint32_t)ADC_CTL1_ADCON; - } + if(RESET == (ADC_CTL1(adc_periph) & ADC_CTL1_ADCON)){ + /* enable ADC */ + ADC_CTL1(adc_periph) |= (uint32_t)ADC_CTL1_ADCON; + } } /*! \brief disable ADC interface \param[in] adc_periph: ADCx,x=0,1,2 - \param[in] none \param[out] none \retval none */ void adc_disable(uint32_t adc_periph) { + /* disable ADC */ ADC_CTL1(adc_periph) &= ~((uint32_t)ADC_CTL1_ADCON); } /*! - \brief ADC data alignment config + \brief ADC calibration and reset calibration \param[in] adc_periph: ADCx,x=0,1,2 - \param[in] inserted_channel : insert channel select - \arg ADC_DATAALIGN_RIGHT: LSB alignment - \arg ADC_DATAALIGN_LEFT: MSB alignment \param[out] none \retval none */ -void adc_data_alignment_config(uint32_t adc_periph , uint8_t data_alignment) +void adc_calibration_enable(uint32_t adc_periph) { - if(data_alignment){ - ADC_CTL1(adc_periph) |= ADC_CTL1_DAL; + /* reset the selected ADC calibration registers */ + ADC_CTL1(adc_periph) |= (uint32_t) ADC_CTL1_RSTCLB; + /* check the RSTCLB bit state */ + while(RESET != (ADC_CTL1(adc_periph) & ADC_CTL1_RSTCLB)){ + } + /* enable ADC calibration process */ + ADC_CTL1(adc_periph) |= ADC_CTL1_CLB; + /* check the CLB bit state */ + while(RESET != (ADC_CTL1(adc_periph) & ADC_CTL1_CLB)){ + } +} + +/*! + \brief configure temperature sensor and internal reference voltage channel or VBAT channel function + \param[in] function: temperature sensor and internal reference voltage channel or VBAT channel + only one parameter can be selected which is shown as below: + \arg ADC_VBAT_CHANNEL_SWITCH: channel 18 (1/4 voltate of external battery) switch of ADC0 + \arg ADC_TEMP_VREF_CHANNEL_SWITCH: channel 16 (temperature sensor) and 17 (internal reference voltage) switch of ADC0 + \param[in] newvalue: ENABLE or DISABLE +\param[out] none + \retval none +*/ +void adc_channel_16_to_18(uint32_t function, ControlStatus newvalue) +{ + if(newvalue){ + if(RESET != (function & ADC_VBAT_CHANNEL_SWITCH)){ + /* enable ADC0 Vbat channel */ + ADC_SYNCCTL |= ADC_VBAT_CHANNEL_SWITCH; + } + if(RESET != (function & ADC_TEMP_VREF_CHANNEL_SWITCH)){ + /* enable ADC0 Vref and Temperature channel */ + ADC_SYNCCTL |= ADC_TEMP_VREF_CHANNEL_SWITCH; + } }else{ - ADC_CTL1(adc_periph) &= ~((uint32_t)ADC_CTL1_DAL); + if(RESET != (function & ADC_VBAT_CHANNEL_SWITCH)){ + /* disable ADC0 Vbat channel */ + ADC_SYNCCTL &= ~ADC_VBAT_CHANNEL_SWITCH; + } + if(RESET != (function & ADC_TEMP_VREF_CHANNEL_SWITCH)){ + /* disable ADC0 Vref and Temperature channel */ + ADC_SYNCCTL &= ~ADC_TEMP_VREF_CHANNEL_SWITCH; + } } } /*! - \brief ADC resolution config + \brief configure ADC resolution \param[in] adc_periph: ADCx,x=0,1,2 \param[in] resolution: ADC resolution + only one parameter can be selected which is shown as below: \arg ADC_RESOLUTION_12B: 12-bit ADC resolution \arg ADC_RESOLUTION_10B: 10-bit ADC resolution \arg ADC_RESOLUTION_8B: 8-bit ADC resolution @@ -91,206 +255,397 @@ void adc_resolution_config(uint32_t adc_periph , uint32_t resolution) } /*! - \brief ADC calibration and reset calibration + \brief configure ADC oversample mode \param[in] adc_periph: ADCx,x=0,1,2 - \param[in] none + \param[in] mode: ADC oversampling mode + only one parameter can be selected which is shown as below: + \arg ADC_OVERSAMPLING_ALL_CONVERT: all oversampled conversions for a channel are done consecutively after a trigger + \arg ADC_OVERSAMPLING_ONE_CONVERT: each oversampled conversion for a channel needs a trigger + \param[in] shift: ADC oversampling shift + only one parameter can be selected which is shown as below: + \arg ADC_OVERSAMPLING_SHIFT_NONE: no oversampling shift + \arg ADC_OVERSAMPLING_SHIFT_1B: 1-bit oversampling shift + \arg ADC_OVERSAMPLING_SHIFT_2B: 2-bit oversampling shift + \arg ADC_OVERSAMPLING_SHIFT_3B: 3-bit oversampling shift + \arg ADC_OVERSAMPLING_SHIFT_4B: 3-bit oversampling shift + \arg ADC_OVERSAMPLING_SHIFT_5B: 5-bit oversampling shift + \arg ADC_OVERSAMPLING_SHIFT_6B: 6-bit oversampling shift + \arg ADC_OVERSAMPLING_SHIFT_7B: 7-bit oversampling shift + \arg ADC_OVERSAMPLING_SHIFT_8B: 8-bit oversampling shift + \param[in] ratio: ADC oversampling ratio + only one parameter can be selected which is shown as below: + \arg ADC_OVERSAMPLING_RATIO_MUL2: oversampling ratio multiple 2 + \arg ADC_OVERSAMPLING_RATIO_MUL4: oversampling ratio multiple 4 + \arg ADC_OVERSAMPLING_RATIO_MUL8: oversampling ratio multiple 8 + \arg ADC_OVERSAMPLING_RATIO_MUL16: oversampling ratio multiple 16 + \arg ADC_OVERSAMPLING_RATIO_MUL32: oversampling ratio multiple 32 + \arg ADC_OVERSAMPLING_RATIO_MUL64: oversampling ratio multiple 64 + \arg ADC_OVERSAMPLING_RATIO_MUL128: oversampling ratio multiple 128 + \arg ADC_OVERSAMPLING_RATIO_MUL256: oversampling ratio multiple 256 \param[out] none \retval none */ -void adc_calibration_enable(uint32_t adc_periph) +void adc_oversample_mode_config(uint32_t adc_periph , uint32_t mode , uint16_t shift , uint8_t ratio) { - /* reset the selected ADC1 calibration registers */ - ADC_CTL1(adc_periph) |= (uint32_t) ADC_CTL1_RSTCLB; - /* check the RSTCLB bit state */ - while((ADC_CTL1(adc_periph) & ADC_CTL1_RSTCLB)){ - } - /* enable ADC calibration process */ - ADC_CTL1(adc_periph) |= ADC_CTL1_CLB; - /* check the CLB bit state */ - while((ADC_CTL1(adc_periph) & ADC_CTL1_CLB)){ + if(ADC_OVERSAMPLING_ONE_CONVERT == mode){ + ADC_OVSAMPCTL(adc_periph) |= (uint32_t)ADC_OVSAMPCTL_TOVS; + }else{ + ADC_OVSAMPCTL(adc_periph) &= ~((uint32_t)ADC_OVSAMPCTL_TOVS); } + /* config the shift and ratio */ + ADC_OVSAMPCTL(adc_periph) &= ~((uint32_t)(ADC_OVSAMPCTL_OVSR | ADC_OVSAMPCTL_OVSS)); + ADC_OVSAMPCTL(adc_periph) |= ((uint32_t)shift | (uint32_t)ratio); +} + +/*! + \brief enable ADC oversample mode + \param[in] adc_periph: ADCx,x=0,1,2 + \param[out] none + \retval none +*/ +void adc_oversample_mode_enable(uint32_t adc_periph) +{ + ADC_OVSAMPCTL(adc_periph) |= ADC_OVSAMPCTL_OVSEN; +} + +/*! + \brief disable ADC oversample mode + \param[in] adc_periph: ADCx,x=0,1,2 + \param[out] none + \retval none +*/ +void adc_oversample_mode_disable(uint32_t adc_periph) +{ + ADC_OVSAMPCTL(adc_periph) &= ~((uint32_t)ADC_OVSAMPCTL_OVSEN); +} + +/*! + \brief enable DMA request + \param[in] adc_periph: ADCx,x=0,1,2 + \param[out] none + \retval none +*/ +void adc_dma_mode_enable(uint32_t adc_periph) +{ + /* enable DMA request */ + ADC_CTL1(adc_periph) |= (uint32_t)(ADC_CTL1_DMA); +} + +/*! + \brief disable DMA request + \param[in] adc_periph: ADCx,x=0,1,2 + \param[out] none + \retval none +*/ +void adc_dma_mode_disable(uint32_t adc_periph) +{ + /* disable DMA request */ + ADC_CTL1(adc_periph) &= ~((uint32_t)ADC_CTL1_DMA); +} + +/*! + \brief when DMA=1, the DMA engine issues a request at end of each regular conversion + \param[in] adc_periph: ADCx,x=0,1,2 + \param[out] none + \retval none +*/ +void adc_dma_request_after_last_enable(uint32_t adc_periph) +{ + ADC_CTL1(adc_periph) |= (uint32_t)(ADC_CTL1_DDM); } /*! - \brief ADC discontinuous mode config + \brief the DMA engine is disabled after the end of transfer signal from DMA controller is detected + \param[in] adc_periph: ADCx,x=0,1,2 + \param[out] none + \retval none +*/ +void adc_dma_request_after_last_disable(uint32_t adc_periph) +{ + ADC_CTL1(adc_periph) &= ~((uint32_t)ADC_CTL1_DDM); +} + +/*! + \brief configure ADC discontinuous mode \param[in] adc_periph: ADCx,x=0,1,2 \param[in] adc_channel_group: select the channel group + only one parameter can be selected which is shown as below: \arg ADC_REGULAR_CHANNEL: regular channel group \arg ADC_INSERTED_CHANNEL: inserted channel group + \arg ADC_CHANNEL_DISCON_DISABLE: disable discontinuous mode of regular & inserted channel \param[in] length: number of conversions in discontinuous mode,the number can be 1..8 - for regular channel ,the number is no effect for inserted channel + for regular channel ,the number has no effect for inserted channel \param[out] none \retval none */ void adc_discontinuous_mode_config(uint32_t adc_periph , uint8_t adc_channel_group , uint8_t length) { + /* disable discontinuous mode of regular & inserted channel */ ADC_CTL0(adc_periph) &= ~((uint32_t)( ADC_CTL0_DISRC | ADC_CTL0_DISIC )); switch(adc_channel_group){ case ADC_REGULAR_CHANNEL: /* config the number of conversions in discontinuous mode */ ADC_CTL0(adc_periph) &= ~((uint32_t)ADC_CTL0_DISNUM); if((length <= 8U) && (length >= 1U)){ - ADC_CTL0(adc_periph) |= ((uint32_t)length - 1U) << REGULAR_DISCONTINUOUS_NUMBER; + ADC_CTL0(adc_periph) |= CTL0_DISNUM(((uint32_t)length - ADC_CHANNEL_LENGTH_SUBTRACT_ONE)); } + /* enable regular channel group discontinuous mode */ ADC_CTL0(adc_periph) |= (uint32_t)ADC_CTL0_DISRC; break; case ADC_INSERTED_CHANNEL: + /* enable inserted channel group discontinuous mode */ ADC_CTL0(adc_periph) |= (uint32_t)ADC_CTL0_DISIC; break; + case ADC_CHANNEL_DISCON_DISABLE: + /* disable discontinuous mode of regular & inserted channel */ default: break; } } /*! - \brief config end of conversion mode + \brief configure the length of regular channel group or inserted channel group \param[in] adc_periph: ADCx,x=0,1,2 - \param[in] end_selection: end of conversion mode - \arg ADC_EOC_SET_SEQUENCE: only at the end of a sequence of regular conversions, the EOC bit is set - \arg ADC_EOC_SET_CONVERSION: at the end of each regular conversion, the EOC bit is set. + \param[in] adc_channel_group: select the channel group + only one parameter can be selected which is shown as below: + \arg ADC_REGULAR_CHANNEL: regular channel group + \arg ADC_INSERTED_CHANNEL: inserted channel group + \param[in] length: the length of the channel + regular channel 1-16 + inserted channel 1-4 \param[out] none \retval none */ -void adc_end_of_conversion_config(uint32_t adc_periph , uint8_t end_selection) +void adc_channel_length_config(uint32_t adc_periph , uint8_t adc_channel_group , uint32_t length) { - switch(end_selection){ - case ADC_EOC_SET_SEQUENCE: - ADC_CTL1(adc_periph) &= ~((uint32_t)ADC_CTL1_EOCM); - break; - case ADC_EOC_SET_CONVERSION: - ADC_CTL1(adc_periph) |= (uint32_t)(ADC_CTL1_EOCM); - break; - default: - break; + switch(adc_channel_group){ + case ADC_REGULAR_CHANNEL: + if((length >= 1U) && (length <= 16U)){ + ADC_RSQ0(adc_periph) &= ~((uint32_t)ADC_RSQ0_RL); + ADC_RSQ0(adc_periph) |= RSQ0_RL((uint32_t)(length-ADC_CHANNEL_LENGTH_SUBTRACT_ONE)); + } + break; + case ADC_INSERTED_CHANNEL: + if((length >= 1U) && (length <= 4U)){ + ADC_ISQ(adc_periph) &= ~((uint32_t)ADC_ISQ_IL); + ADC_ISQ(adc_periph) |= ISQ_IL((uint32_t)(length-ADC_CHANNEL_LENGTH_SUBTRACT_ONE)); + } + break; + default: + break; } } /*! - \brief ADC special function enable or disable + \brief configure ADC regular channel \param[in] adc_periph: ADCx,x=0,1,2 - \param[in] function: select the function to config - \arg ADC_SCAN_MODE: scan mode select - \arg ADC_INSERTED_CHANNEL_AUTO: inserted channel group convert automatically - \arg ADC_CONTINUOUS_MODE: continuous mode select - \param[in] newvalue: ENABLE or DISABLE + \param[in] rank: the regular group sequencer rank,this parameter must be between 0 to 15 + \param[in] adc_channel: the selected ADC channel + only one parameter can be selected which is shown as below: + \arg ADC_CHANNEL_x(x=0..18): ADC Channelx + \param[in] sample_time: the sample time value + only one parameter can be selected which is shown as below: + \arg ADC_SAMPLETIME_3: 3 cycles + \arg ADC_SAMPLETIME_15: 15 cycles + \arg ADC_SAMPLETIME_28: 28 cycles + \arg ADC_SAMPLETIME_56: 56 cycles + \arg ADC_SAMPLETIME_84: 84 cycles + \arg ADC_SAMPLETIME_112: 112 cycles + \arg ADC_SAMPLETIME_144: 144 cycles + \arg ADC_SAMPLETIME_480: 480 cycles \param[out] none \retval none */ -void adc_special_function_config(uint32_t adc_periph , uint8_t function , ControlStatus newvalue) +void adc_regular_channel_config(uint32_t adc_periph , uint8_t rank , uint8_t adc_channel , uint32_t sample_time) { - if(newvalue){ - switch(function){ - case ADC_SCAN_MODE: - ADC_CTL0(adc_periph) |= (uint32_t)ADC_CTL0_SM; - break; - case ADC_INSERTED_CHANNEL_AUTO: - ADC_CTL0(adc_periph) |= (uint32_t)ADC_CTL0_ICA; - break; - case ADC_CONTINUOUS_MODE: - ADC_CTL1(adc_periph) |= (uint32_t)ADC_CTL1_CTN; - break; - default: - break; - } + uint32_t rsq,sampt; + + /* ADC regular sequence config */ + if(rank < ADC_REGULAR_CHANNEL_RANK_SIX){ + /* the regular group sequence rank is smaller than six */ + rsq = ADC_RSQ2(adc_periph); + rsq &= ~((uint32_t)(ADC_RSQX_RSQN << (ADC_REGULAR_CHANNEL_RANK_LENGTH*rank))); + /* the channel number is written to these bits to select a channel as the nth conversion in the regular channel group */ + rsq |= ((uint32_t)adc_channel << (ADC_REGULAR_CHANNEL_RANK_LENGTH*rank)); + ADC_RSQ2(adc_periph) = rsq; + }else if(rank < ADC_REGULAR_CHANNEL_RANK_TWELVE){ + /* the regular group sequence rank is smaller than twelve */ + rsq = ADC_RSQ1(adc_periph); + rsq &= ~((uint32_t)(ADC_RSQX_RSQN << (ADC_REGULAR_CHANNEL_RANK_LENGTH*(rank-ADC_REGULAR_CHANNEL_RANK_SIX)))); + /* the channel number is written to these bits to select a channel as the nth conversion in the regular channel group */ + rsq |= ((uint32_t)adc_channel << (ADC_REGULAR_CHANNEL_RANK_LENGTH*(rank-ADC_REGULAR_CHANNEL_RANK_SIX))); + ADC_RSQ1(adc_periph) = rsq; + }else if(rank < ADC_REGULAR_CHANNEL_RANK_SIXTEEN){ + /* the regular group sequence rank is smaller than sixteen */ + rsq = ADC_RSQ0(adc_periph); + rsq &= ~((uint32_t)(ADC_RSQX_RSQN << (ADC_REGULAR_CHANNEL_RANK_LENGTH*(rank-ADC_REGULAR_CHANNEL_RANK_TWELVE)))); + /* the channel number is written to these bits to select a channel as the nth conversion in the regular channel group */ + rsq |= ((uint32_t)adc_channel << (ADC_REGULAR_CHANNEL_RANK_LENGTH*(rank-ADC_REGULAR_CHANNEL_RANK_TWELVE))); + ADC_RSQ0(adc_periph) = rsq; + }else{ + } + + /* ADC sampling time config */ + if(adc_channel < ADC_CHANNEL_SAMPLE_TEN){ + /* the regular group sequence rank is smaller than ten */ + sampt = ADC_SAMPT1(adc_periph); + sampt &= ~((uint32_t)(ADC_SAMPTX_SPTN << (ADC_CHANNEL_SAMPLE_LENGTH*adc_channel))); + /* channel sample time set*/ + sampt |= (uint32_t)(sample_time << (ADC_CHANNEL_SAMPLE_LENGTH*adc_channel)); + ADC_SAMPT1(adc_periph) = sampt; + }else if(adc_channel <= ADC_CHANNEL_SAMPLE_EIGHTEEN){ + /* the regular group sequence rank is smaller than eighteen */ + sampt = ADC_SAMPT0(adc_periph); + sampt &= ~((uint32_t)(ADC_SAMPTX_SPTN << (ADC_CHANNEL_SAMPLE_LENGTH*(adc_channel-ADC_CHANNEL_SAMPLE_TEN)))); + /* channel sample time set*/ + sampt |= (uint32_t)(sample_time << (ADC_CHANNEL_SAMPLE_LENGTH*(adc_channel-ADC_CHANNEL_SAMPLE_TEN))); + ADC_SAMPT0(adc_periph) = sampt; }else{ - switch(function){ - case ADC_SCAN_MODE: - ADC_CTL0(adc_periph) &= ~((uint32_t)ADC_CTL0_SM); - break; - case ADC_INSERTED_CHANNEL_AUTO: - ADC_CTL0(adc_periph) &= ~((uint32_t)ADC_CTL0_ICA); - break; - case ADC_CONTINUOUS_MODE: - ADC_CTL1(adc_periph) &= ~((uint32_t)ADC_CTL1_CTN); - break; - default: - break; - } } } /*! - \brief configure the ADC clock for all the ADCs - \param[in] prescaler: configure ADCs prescaler ratio - \arg ADC_ADCCK_PCLK2_DIV2: PCLK2 div2 - \arg ADC_ADCCK_PCLK2_DIV4: PCLK2 div4 - \arg ADC_ADCCK_PCLK2_DIV6: PCLK2 div6 - \arg ADC_ADCCK_PCLK2_DIV8: PCLK2 div8 - \arg ADC_ADCCK_HCLK_DIV5: HCLK div5 - \arg ADC_ADCCK_HCLK_DIV6: HCLK div6 - \arg ADC_ADCCK_HCLK_DIV10: HCLK div10 - \arg ADC_ADCCK_HCLK_DIV20: HCLK div20 + \brief configure ADC inserted channel + \param[in] adc_periph: ADCx,x=0,1,2 + \param[in] rank: the inserted group sequencer rank,this parameter must be between 0 to 3 + \param[in] adc_channel: the selected ADC channel + only one parameter can be selected which is shown as below: + \arg ADC_CHANNEL_x(x=0..18): ADC Channelx + \param[in] sample_time: The sample time value + only one parameter can be selected which is shown as below: + \arg ADC_SAMPLETIME_3: 3 cycles + \arg ADC_SAMPLETIME_15: 15 cycles + \arg ADC_SAMPLETIME_28: 28 cycles + \arg ADC_SAMPLETIME_56: 56 cycles + \arg ADC_SAMPLETIME_84: 84 cycles + \arg ADC_SAMPLETIME_112: 112 cycles + \arg ADC_SAMPLETIME_144: 144 cycles + \arg ADC_SAMPLETIME_480: 480 cycles \param[out] none \retval none */ -void adc_clock_config(uint32_t prescaler) +void adc_inserted_channel_config(uint32_t adc_periph , uint8_t rank , uint8_t adc_channel , uint32_t sample_time) { - ADC_SYNCCTL &= ~((uint32_t)ADC_SYNCCTL_ADCCK); - ADC_SYNCCTL |= (uint32_t) prescaler; + uint8_t inserted_length; + uint32_t isq,sampt; + + /* get inserted channel group length */ + inserted_length = (uint8_t)GET_BITS(ADC_ISQ(adc_periph) , 20U , 21U); + /* the channel number is written to these bits to select a channel as the nth conversion in the inserted channel group */ + if(rank < 4U){ + isq = ADC_ISQ(adc_periph); + isq &= ~((uint32_t)(ADC_ISQ_ISQN << (ADC_INSERTED_CHANNEL_SHIFT_LENGTH-(inserted_length-rank)*ADC_INSERTED_CHANNEL_RANK_LENGTH))); + isq |= ((uint32_t)adc_channel << (ADC_INSERTED_CHANNEL_SHIFT_LENGTH-(inserted_length-rank)*ADC_INSERTED_CHANNEL_RANK_LENGTH)); + ADC_ISQ(adc_periph) = isq; + } + + /* ADC sampling time config */ + if(adc_channel < ADC_CHANNEL_SAMPLE_TEN){ + /* the inserted group sequence rank is smaller than ten */ + sampt = ADC_SAMPT1(adc_periph); + sampt &= ~((uint32_t)(ADC_SAMPTX_SPTN << (ADC_CHANNEL_SAMPLE_LENGTH*adc_channel))); + /* channel sample time set*/ + sampt |= (uint32_t) sample_time << (ADC_CHANNEL_SAMPLE_LENGTH*adc_channel); + ADC_SAMPT1(adc_periph) = sampt; + }else if(adc_channel <= ADC_CHANNEL_SAMPLE_EIGHTEEN){ + /* the inserted group sequence rank is smaller than eighteen */ + sampt = ADC_SAMPT0(adc_periph); + sampt &= ~((uint32_t)(ADC_SAMPTX_SPTN << (ADC_CHANNEL_SAMPLE_LENGTH*(adc_channel - ADC_CHANNEL_SAMPLE_TEN)))); + /* channel sample time set*/ + sampt |= ((uint32_t)sample_time << (ADC_CHANNEL_SAMPLE_LENGTH*(adc_channel - ADC_CHANNEL_SAMPLE_TEN))); + ADC_SAMPT0(adc_periph) = sampt; + }else{ + } } /*! - \brief configure the ADC clock for all the ADCs - \param[in] function: temperature sensor and internal reference voltage channel or VBAT channel - \arg ADC_VBAT_CHANNEL_SWITCH: channel 18 (1/4 voltate of external battery) switch of ADC0 - \arg ADC_TEMP_VREF_CHANNEL_SWITCH: channel 16 (temperature sensor) and 17 (internal reference voltage) switch of ADC0 - \param[in] newvalue: ENABLE or DISABLE -\param[out] none + \brief configure ADC inserted channel offset + \param[in] adc_periph: ADCx,x=0,1,2 + \param[in] inserted_channel : insert channel select + only one parameter can be selected which is shown as below: + \arg ADC_INSERTED_CHANNEL_0: inserted channel0 + \arg ADC_INSERTED_CHANNEL_1: inserted channel1 + \arg ADC_INSERTED_CHANNEL_2: inserted channel2 + \arg ADC_INSERTED_CHANNEL_3: inserted channel3 + \param[in] offset : the offset data + \param[out] none \retval none */ -void adc_channel_16_to_18(uint8_t function,ControlStatus newvalue) +void adc_inserted_channel_offset_config(uint32_t adc_periph , uint8_t inserted_channel , uint16_t offset) { - if(newvalue){ - switch(function){ - case ADC_VBAT_CHANNEL_SWITCH: - ADC_SYNCCTL |= (uint32_t)ADC_SYNCCTL_VBATEN; - break; - case ADC_TEMP_VREF_CHANNEL_SWITCH: - ADC_SYNCCTL |= (uint32_t)ADC_SYNCCTL_TSVREN; - break; - default: - break; - } - }else{ - switch(function){ - case ADC_VBAT_CHANNEL_SWITCH: - ADC_SYNCCTL &= ~((uint32_t)ADC_SYNCCTL_VBATEN); - break; - case ADC_TEMP_VREF_CHANNEL_SWITCH: - ADC_SYNCCTL &= ~((uint32_t)ADC_SYNCCTL_TSVREN); - break; - default: - break; - } + uint8_t inserted_length; + uint32_t num = 0U; + + inserted_length = (uint8_t)GET_BITS(ADC_ISQ(adc_periph) , 20U , 21U); + num = ((uint32_t)ADC_OFFSET_LENGTH - ((uint32_t)inserted_length - (uint32_t)inserted_channel)); + + if(num <= ADC_OFFSET_LENGTH){ + /* calculate the offset of the register */ + num = num * ADC_OFFSET_SHIFT_LENGTH; + /* config the offset of the selected channels */ + REG32((adc_periph) + 0x14U + num) = IOFFX_IOFF((uint32_t)offset); } } /*! - \brief config the length of regular channel group or inserted channel group + \brief configure ADC external trigger source \param[in] adc_periph: ADCx,x=0,1,2 \param[in] adc_channel_group: select the channel group + only one parameter can be selected which is shown as below: \arg ADC_REGULAR_CHANNEL: regular channel group \arg ADC_INSERTED_CHANNEL: inserted channel group - \param[in] length: the length of the channel - regular channel 1-16 - inserted channel 1-4 + \param[in] external_trigger_source: regular or inserted group trigger source + for regular channel: + only one parameter can be selected which is shown as below: + \arg ADC_EXTTRIG_REGULAR_T0_CH0: external trigger timer 0 CC0 event select for regular channel + \arg ADC_EXTTRIG_REGULAR_T0_CH1: external trigger timer 0 CC1 event select for regular channel + \arg ADC_EXTTRIG_REGULAR_T0_CH2: external trigger timer 0 CC2 event select for regular channel + \arg ADC_EXTTRIG_REGULAR_T1_CH1: external trigger timer 1 CC1 event select for regular channel + \arg ADC_EXTTRIG_REGULAR_T1_CH2: external trigger timer 1 CC2 event select for regular channel + \arg ADC_EXTTRIG_REGULAR_T1_CH3: external trigger timer 1 CC3 event select for regular channel + \arg ADC_EXTTRIG_REGULAR_T1_TRGO: external trigger timer 1 TRGO event select for regular channel + \arg ADC_EXTTRIG_REGULAR_T2_CH0 : external trigger timer 2 CC0 event select for regular channel + \arg ADC_EXTTRIG_REGULAR_T2_TRGO : external trigger timer 2 TRGO event select for regular channel + \arg ADC_EXTTRIG_REGULAR_T3_CH3: external trigger timer 3 CC3 event select for regular channel + \arg ADC_EXTTRIG_REGULAR_T4_CH0: external trigger timer 4 CC0 event select for regular channel + \arg ADC_EXTTRIG_REGULAR_T4_CH1: external trigger timer 4 CC1 event select for regular channel + \arg ADC_EXTTRIG_REGULAR_T4_CH2: external trigger timer 4 CC2 event select for regular channel + \arg ADC_EXTTRIG_REGULAR_T7_CH0: external trigger timer 7 CC0 event select for regular channel + \arg ADC_EXTTRIG_REGULAR_T7_TRGO: external trigger timer 7 TRGO event select for regular channel + \arg ADC_EXTTRIG_REGULAR_EXTI_11: external trigger extiline 11 select for regular channel + for inserted channel: + only one parameter can be selected which is shown as below: + \arg ADC_EXTTRIG_INSERTED_T0_CH3: timer0 capture compare 3 + \arg ADC_EXTTRIG_INSERTED_T0_TRGO: timer0 TRGO event + \arg ADC_EXTTRIG_INSERTED_T1_CH0: timer1 capture compare 0 + \arg ADC_EXTTRIG_INSERTED_T1_TRGO: timer1 TRGO event + \arg ADC_EXTTRIG_INSERTED_T2_CH1: timer2 capture compare 1 + \arg ADC_EXTTRIG_INSERTED_T2_CH3: timer2 capture compare 3 + \arg ADC_EXTTRIG_INSERTED_T3_CH0: timer3 capture compare 0 + \arg ADC_EXTTRIG_INSERTED_T3_CH1: timer3 capture compare 1 + \arg ADC_EXTTRIG_INSERTED_T3_CH2: timer3 capture compare 2 + \arg ADC_EXTTRIG_INSERTED_T3_TRGO: timer3 capture compare TRGO + \arg ADC_EXTTRIG_INSERTED_T4_CH3: timer4 capture compare 3 + \arg ADC_EXTTRIG_INSERTED_T4_TRGO: timer4 capture compare TRGO + \arg ADC_EXTTRIG_INSERTED_T7_CH1: timer7 capture compare 1 + \arg ADC_EXTTRIG_INSERTED_T7_CH2: timer7 capture compare 2 + \arg ADC_EXTTRIG_INSERTED_T7_CH3: timer7 capture compare 3 + \arg ADC_EXTTRIG_INSERTED_EXTI_15: external interrupt line 15 \param[out] none \retval none */ -void adc_channel_length_config(uint32_t adc_periph , uint8_t adc_channel_group , uint32_t length) +void adc_external_trigger_source_config(uint32_t adc_periph , uint8_t adc_channel_group , uint32_t external_trigger_source) { switch(adc_channel_group){ case ADC_REGULAR_CHANNEL: - if((length >= 1U) && (length <= 16U)){ - ADC_RSQ0(adc_periph) &= ~((uint32_t)ADC_RSQ0_RL); - ADC_RSQ0(adc_periph) |= (uint32_t)((length-1U) << REGULAR_CHANNEL_LENGTH_OFFSET); - } + /* configure ADC regular group external trigger source */ + ADC_CTL1(adc_periph) &= ~((uint32_t)ADC_CTL1_ETSRC); + ADC_CTL1(adc_periph) |= (uint32_t)external_trigger_source; break; case ADC_INSERTED_CHANNEL: - if((length >= 1U) && (length <= 4U)){ - ADC_ISQ(adc_periph) &= ~((uint32_t)ADC_ISQ_IL); - ADC_ISQ(adc_periph) |= (uint32_t)((length-1U) << INSERTED_CHANNEL_LENGTH_OFFSET); - } + /* configure ADC inserted group external trigger source */ + ADC_CTL1(adc_periph) &= ~((uint32_t)ADC_CTL1_ETSIC); + ADC_CTL1(adc_periph) |= (uint32_t)external_trigger_source; break; default: break; @@ -298,12 +653,14 @@ void adc_channel_length_config(uint32_t adc_periph , uint8_t adc_channel_group , } /*! - \brief ADC external trigger enable + \brief enable ADC external trigger \param[in] adc_periph: ADCx,x=0,1,2 \param[in] adc_channel_group: select the channel group + only one parameter can be selected which is shown as below: \arg ADC_REGULAR_CHANNEL: regular channel group \arg ADC_INSERTED_CHANNEL: inserted channel group \param[in] trigger_mode: external trigger mode + only one parameter can be selected which is shown as below: \arg EXTERNAL_TRIGGER_DISABLE: external trigger disable \arg EXTERNAL_TRIGGER_RISING: rising edge of external trigger \arg EXTERNAL_TRIGGER_FALLING: falling edge of external trigger @@ -315,10 +672,12 @@ void adc_external_trigger_config(uint32_t adc_periph , uint8_t adc_channel_group { switch(adc_channel_group){ case ADC_REGULAR_CHANNEL: + /* configure ADC regular channel group external trigger mode */ ADC_CTL1(adc_periph) &= ~((uint32_t)ADC_CTL1_ETMRC); ADC_CTL1(adc_periph) |= (uint32_t) (trigger_mode << REGULAR_TRIGGER_MODE); break; case ADC_INSERTED_CHANNEL: + /* configure ADC inserted channel group external trigger mode */ ADC_CTL1(adc_periph) &= ~((uint32_t)ADC_CTL1_ETMIC); ADC_CTL1(adc_periph) |= (uint32_t) (trigger_mode << INSERTED_TRIGGER_MODE); break; @@ -328,69 +687,10 @@ void adc_external_trigger_config(uint32_t adc_periph , uint8_t adc_channel_group } /*! - \brief ADC external trigger source config - \param[in] adc_periph: ADCx,x=0,1,2 - \param[in] adc_channel_group: select the channel group - \arg ADC_REGULAR_CHANNEL: regular channel group - \arg ADC_INSERTED_CHANNEL: inserted channel group - \param[in] external_trigger_source: regular or inserted group trigger source - for regular channel: - \arg ADC_EXTTRIG_REGULAR_T0_CH0: external trigger timer 0 CC0 event select for regular channel - \arg ADC_EXTTRIG_REGULAR_T0_CH1: external trigger timer 0 CC1 event select for regular channel - \arg ADC_EXTTRIG_REGULAR_T0_CH2: external trigger timer 0 CC2 event select for regular channel - \arg ADC_EXTTRIG_REGULAR_T1_CH1: external trigger timer 1 CC1 event select for regular channel - \arg ADC_EXTTRIG_REGULAR_T1_CH2: external trigger timer 1 CC2 event select for regular channel - \arg ADC_EXTTRIG_REGULAR_T1_CH3: external trigger timer 1 CC3 event select for regular channel - \arg ADC_EXTTRIG_REGULAR_T1_TRGO: external trigger timer 1 TRGO event select for regular channel - \arg ADC_EXTTRIG_REGULAR_T2_CH0 : external trigger timer 2 CC0 event select for regular channel - \arg ADC_EXTTRIG_REGULAR_T2_TRGO : external trigger timer 2 TRGO event select for regular channel - \arg ADC_EXTTRIG_REGULAR_T3_CH3: external trigger timer 3 CC3 event select for regular channel - \arg ADC_EXTTRIG_REGULAR_T4_CH0: external trigger timer 4 CC0 event select for regular channel - \arg ADC_EXTTRIG_REGULAR_T4_CH1: external trigger timer 4 CC1 event select for regular channel - \arg ADC_EXTTRIG_REGULAR_T4_CH2: external trigger timer 4 CC2 event select for regular channel - \arg ADC_EXTTRIG_REGULAR_T7_CH0: external trigger timer 7 CC0 event select for regular channel - \arg ADC_EXTTRIG_REGULAR_T7_TRGO: external trigger timer 7 TRGO event select for regular channel - \arg ADC_EXTTRIG_REGULAR_EXTI_11: external trigger extiline 11 select for regular channel - for inserted channel: - \arg ADC_EXTTRIG_INSERTED_T0_CH3: timer0 capture compare 3 - \arg ADC_EXTTRIG_INSERTED_T0_TRGO: timer0 TRGO event - \arg ADC_EXTTRIG_INSERTED_T1_CH0: timer1 capture compare 0 - \arg ADC_EXTTRIG_INSERTED_T1_TRGO: timer1 TRGO event - \arg ADC_EXTTRIG_INSERTED_T2_CH1: timer2 capture compare 1 - \arg ADC_EXTTRIG_INSERTED_T2_CH3: timer2 capture compare 3 - \arg ADC_EXTTRIG_INSERTED_T3_CH0: timer3 capture compare 0 - \arg ADC_EXTTRIG_INSERTED_T3_CH1: timer3 capture compare 1 - \arg ADC_EXTTRIG_INSERTED_T3_CH2: timer3 capture compare 2 - \arg ADC_EXTTRIG_INSERTED_T3_TRGO: timer3 capture compare TRGO - \arg ADC_EXTTRIG_INSERTED_T4_CH3: timer4 capture compare 3 - \arg ADC_EXTTRIG_INSERTED_T4_TRGO: timer4 capture compare TRGO - \arg ADC_EXTTRIG_INSERTED_T7_CH1: timer7 capture compare 1 - \arg ADC_EXTTRIG_INSERTED_T7_CH2: timer7 capture compare 2 - \arg ADC_EXTTRIG_INSERTED_T7_CH3: timer7 capture compare 3 - \arg ADC_EXTTRIG_INSERTED_EXTI_15: external interrupt line 15 - \param[out] none - \retval none -*/ -void adc_external_trigger_source_config(uint32_t adc_periph , uint8_t adc_channel_group , uint32_t external_trigger_source) -{ - switch(adc_channel_group){ - case ADC_REGULAR_CHANNEL: - ADC_CTL1(adc_periph) &= ~((uint32_t)ADC_CTL1_ETSRC); - ADC_CTL1(adc_periph) |= (uint32_t)external_trigger_source; - break; - case ADC_INSERTED_CHANNEL: - ADC_CTL1(adc_periph) &= ~((uint32_t)ADC_CTL1_ETSIC); - ADC_CTL1(adc_periph) |= (uint32_t)external_trigger_source; - break; - default: - break; - } -} - -/*! - \brief ADC software trigger enable + \brief enable ADC software trigger \param[in] adc_periph: ADCx,x=0,1,2 \param[in] adc_channel_group: select the channel group + only one parameter can be selected which is shown as below: \arg ADC_REGULAR_CHANNEL: regular channel group \arg ADC_INSERTED_CHANNEL: inserted channel group \param[out] none @@ -400,9 +700,11 @@ void adc_software_trigger_enable(uint32_t adc_periph , uint8_t adc_channel_group { switch(adc_channel_group){ case ADC_REGULAR_CHANNEL: + /* enable ADC regular channel group software trigger */ ADC_CTL1(adc_periph) |= (uint32_t)ADC_CTL1_SWRCST; break; case ADC_INSERTED_CHANNEL: + /* enable ADC inserted channel group software trigger */ ADC_CTL1(adc_periph) |= (uint32_t)ADC_CTL1_SWICST; break; default: @@ -411,173 +713,85 @@ void adc_software_trigger_enable(uint32_t adc_periph , uint8_t adc_channel_group } /*! - \brief get the ADC flag bits - \param[in] adc_periph: ADCx,x=0,1,2 - \param[in] adc_flag: the adc flag bits - \arg ADC_FLAG_WDE: analog watchdog event flag - \arg ADC_FLAG_EOC: end of group conversion flag - \arg ADC_FLAG_EOIC: end of inserted group conversion flag - \arg ADC_FLAG_STIC: start flag of inserted channel group - \arg ADC_FLAG_STRC: start flag of regular channel group - \arg ADC_FLAG_ROVF: regular data register overflow flag - \param[out] none - \retval FlagStatus: SET or RESET -*/ -FlagStatus adc_flag_get(uint32_t adc_periph , uint32_t adc_flag) -{ - if(ADC_STAT(adc_periph) & adc_flag){ - return SET; - } - return RESET; - -} - -/*! - \brief clear the ADC flag bits + \brief configure end of conversion mode \param[in] adc_periph: ADCx,x=0,1,2 - \param[in] adc_flag: the adc flag bits - \arg ADC_FLAG_WDE: analog watchdog event flag - \arg ADC_FLAG_EOC: end of group conversion flag - \arg ADC_FLAG_EOIC: end of inserted group conversion flag - \arg ADC_FLAG_STIC: start flag of inserted channel group - \arg ADC_FLAG_STRC: start flag of regular channel group - \arg ADC_FLAG_ROVF: regular data register overflow flag + \param[in] end_selection: end of conversion mode + only one parameter can be selected which is shown as below: + \arg ADC_EOC_SET_SEQUENCE: only at the end of a sequence of regular conversions, the EOC bit is set.Overflow detection is disabled unless DMA=1. + \arg ADC_EOC_SET_CONVERSION: at the end of each regular conversion, the EOC bit is set.Overflow is detected automatically. \param[out] none \retval none */ -void adc_flag_clear(uint32_t adc_periph , uint32_t adc_flag) -{ - ADC_STAT(adc_periph) &= ~((uint32_t)adc_flag); -} - -/*! - \brief get the ADC interrupt bits - \param[in] adc_periph: ADCx,x=0,1,2 - \param[in] adc_interrupt: the adc interrupt bits - \arg ADC_INT_WDE: analog watchdog interrupt - \arg ADC_INT_EOC: end of group conversion interrupt - \arg ADC_INT_EOIC: end of inserted group conversion interrupt - \arg ADC_INT_ROVF: regular data register overflow interrupt - \param[out] none - \retval FlagStatus: SET or RESET -*/ -FlagStatus adc_interrupt_flag_get(uint32_t adc_periph , uint32_t adc_interrupt) +void adc_end_of_conversion_config(uint32_t adc_periph , uint8_t end_selection) { - FlagStatus interrupt_flag = RESET; - uint32_t state; - /* check the interrupt bits */ - switch(adc_interrupt){ - case ADC_INT_WDE: - state = ADC_STAT(adc_periph) & ADC_STAT_WDE; - if((ADC_CTL0(adc_periph) & ADC_CTL0_WDEIE) && state){ - interrupt_flag = SET; - } - break; - case ADC_INT_EOC: - state = ADC_STAT(adc_periph) & ADC_STAT_EOC; - if((ADC_CTL0(adc_periph) & ADC_CTL0_EOCIE) && state){ - interrupt_flag = SET; - } - break; - case ADC_INT_EOIC: - state = ADC_STAT(adc_periph) & ADC_STAT_EOIC; - if((ADC_CTL0(adc_periph) & ADC_CTL0_EOICIE) && state){ - interrupt_flag = SET; - } - break; - case ADC_INT_ROVF: - state = ADC_STAT(adc_periph) & ADC_STAT_ROVF; - if((ADC_CTL0(adc_periph) & ADC_CTL0_ROVFIE) && state){ - interrupt_flag = SET; - } - break; - default: - break; + switch(end_selection){ + case ADC_EOC_SET_SEQUENCE: + /* only at the end of a sequence of regular conversions, the EOC bit is set */ + ADC_CTL1(adc_periph) &= ~((uint32_t)ADC_CTL1_EOCM); + break; + case ADC_EOC_SET_CONVERSION: + /* at the end of each regular conversion, the EOC bit is set.Overflow is detected automatically */ + ADC_CTL1(adc_periph) |= (uint32_t)(ADC_CTL1_EOCM); + break; + default: + break; } - return interrupt_flag; } /*! - \brief clear the ADC flag + \brief read ADC regular group data register \param[in] adc_periph: ADCx,x=0,1,2 - \param[in] adc_flag: the adc status flag - \arg ADC_INT_WDE: analog watchdog interrupt - \arg ADC_INT_EOC: end of group conversion interrupt - \arg ADC_INT_EOIC: end of inserted group conversion interrupt - \arg ADC_INT_ROVF: regular data register overflow interrupt - \param[out] none - \retval none -*/ -void adc_interrupt_flag_clear(uint32_t adc_periph , uint32_t adc_interrupt) -{ - ADC_STAT(adc_periph) &= ~((uint32_t)adc_interrupt); -} - -/*! - \brief ADC interrupt enable - \param[in] adc_periph: ADCx,x=0,1,2 - \param[in] adc_flag: the adc interrupt flag - \arg ADC_INT_WDE: analog watchdog interrupt flag - \arg ADC_INT_EOC: end of group conversion interrupt flag - \arg ADC_INT_EOIC: end of inserted group conversion interrupt flag - \arg ADC_INT_ROVF: regular data register overflow interrupt flag + \param[in] none \param[out] none - \retval none + \retval the conversion value */ -void adc_interrupt_enable(uint32_t adc_periph , uint32_t adc_interrupt) +uint16_t adc_regular_data_read(uint32_t adc_periph) { - switch(adc_interrupt){ - case ADC_INT_WDE: - ADC_CTL0(adc_periph) |= (uint32_t) ADC_CTL0_WDEIE; - break; - case ADC_INT_EOC: - ADC_CTL0(adc_periph) |= (uint32_t) ADC_CTL0_EOCIE; - break; - case ADC_INT_EOIC: - ADC_CTL0(adc_periph) |= (uint32_t) ADC_CTL0_EOICIE; - break; - case ADC_INT_ROVF: - ADC_CTL0(adc_periph) |= (uint32_t) ADC_CTL0_ROVFIE; - break; - default: - break; - } + return (uint16_t)(ADC_RDATA(adc_periph)); } /*! - \brief ADC interrupt disable + \brief read ADC inserted group data register \param[in] adc_periph: ADCx,x=0,1,2 - \param[in] adc_flag: the adc interrupt flag - \arg ADC_INT_WDE: analog watchdog interrupt flag - \arg ADC_INT_EOC: end of group conversion interrupt flag - \arg ADC_INT_EOIC: end of inserted group conversion interrupt flag - \arg ADC_INT_ROVF: regular data register overflow interrupt flag + \param[in] inserted_channel : insert channel select + only one parameter can be selected which is shown as below: + \arg ADC_INSERTED_CHANNEL_0: inserted Channel0 + \arg ADC_INSERTED_CHANNEL_1: inserted channel1 + \arg ADC_INSERTED_CHANNEL_2: inserted Channel2 + \arg ADC_INSERTED_CHANNEL_3: inserted Channel3 \param[out] none - \retval none + \retval the conversion value */ -void adc_interrupt_disable(uint32_t adc_periph , uint32_t adc_interrupt) +uint16_t adc_inserted_data_read(uint32_t adc_periph , uint8_t inserted_channel) { - switch(adc_interrupt){ - /* select the interrupt source */ - case ADC_INT_WDE: - ADC_CTL0(adc_periph) &= ~((uint32_t)ADC_CTL0_WDEIE); + uint32_t idata; + /* read the data of the selected channel */ + switch(inserted_channel){ + case ADC_INSERTED_CHANNEL_0: + /* read the data of channel 0 */ + idata = ADC_IDATA0(adc_periph); break; - case ADC_INT_EOC: - ADC_CTL0(adc_periph) &= ~((uint32_t)ADC_CTL0_EOCIE); + case ADC_INSERTED_CHANNEL_1: + /* read the data of channel 1 */ + idata = ADC_IDATA1(adc_periph); break; - case ADC_INT_EOIC: - ADC_CTL0(adc_periph) &= ~((uint32_t)ADC_CTL0_EOICIE); + case ADC_INSERTED_CHANNEL_2: + /* read the data of channel 2 */ + idata = ADC_IDATA2(adc_periph); break; - case ADC_INT_ROVF: - ADC_CTL0(adc_periph) &= ~((uint32_t)ADC_CTL0_ROVFIE); + case ADC_INSERTED_CHANNEL_3: + /* read the data of channel 3 */ + idata = ADC_IDATA3(adc_periph); break; default: + idata = 0U; break; } + return (uint16_t)idata; } /*! - \brief ADC analog watchdog single channel disable + \brief disable ADC analog watchdog single channel \param[in] adc_periph: ADCx,x=0,1,2 \param[out] none \retval none @@ -588,9 +802,10 @@ void adc_watchdog_single_channel_disable(uint32_t adc_periph ) } /*! - \brief ADC analog watchdog single channel enable + \brief enable ADC analog watchdog single channel \param[in] adc_periph: ADCx,x=0,1,2 \param[in] adc_channel: the selected ADC channel + only one parameter can be selected which is shown as below: \arg ADC_CHANNEL_x: ADC Channelx(x=0..18) \param[out] none \retval none @@ -599,32 +814,37 @@ void adc_watchdog_single_channel_enable(uint32_t adc_periph , uint8_t adc_channe { ADC_CTL0(adc_periph) &= ~((uint32_t)ADC_CTL0_WDCHSEL); + /* analog watchdog channel select */ ADC_CTL0(adc_periph) |= (uint32_t)adc_channel; ADC_CTL0(adc_periph) |= (uint32_t) ADC_CTL0_WDSC; } /*! - \brief adc analog watchdog group channel config + \brief configure ADC analog watchdog group channel \param[in] adc_periph: ADCx,x=0,1,2 - \param[in] adc_channel_group: the channel group use analog watchdog + \param[in] adc_channel_group: the channel group use analog watchdog + only one parameter can be selected which is shown as below: \arg ADC_REGULAR_CHANNEL: regular channel group \arg ADC_INSERTED_CHANNEL: inserted channel group \arg ADC_REGULAR_INSERTED_CHANNEL: both regular and inserted group \param[out] none \retval none */ -void adc_watchdog_enable(uint32_t adc_periph , uint8_t adc_channel_group) +void adc_watchdog_group_channel_enable(uint32_t adc_periph , uint8_t adc_channel_group) { ADC_CTL0(adc_periph) &= ~((uint32_t)(ADC_CTL0_RWDEN | ADC_CTL0_IWDEN | ADC_CTL0_WDSC)); /* select the group */ switch(adc_channel_group){ case ADC_REGULAR_CHANNEL: + /* regular channel analog watchdog enable */ ADC_CTL0(adc_periph) |= (uint32_t) ADC_CTL0_RWDEN; break; case ADC_INSERTED_CHANNEL: + /* inserted channel analog watchdog enable */ ADC_CTL0(adc_periph) |= (uint32_t) ADC_CTL0_IWDEN; break; case ADC_REGULAR_INSERTED_CHANNEL: + /* regular and inserted channel analog watchdog enable */ ADC_CTL0(adc_periph) |= (uint32_t)(ADC_CTL0_RWDEN | ADC_CTL0_IWDEN); break; default: @@ -633,9 +853,10 @@ void adc_watchdog_enable(uint32_t adc_periph , uint8_t adc_channel_group) } /*! - \brief ADC analog watchdog disable + \brief disable ADC analog watchdog \param[in] adc_periph: ADCx,x=0,1,2 - \param[in] adc_channel_group: the channel group use analog watchdog + \param[in] adc_channel_group: the channel group use analog watchdog + only one parameter can be selected which is shown as below: \arg ADC_REGULAR_CHANNEL: regular channel group \arg ADC_INSERTED_CHANNEL: inserted channel group \arg ADC_REGULAR_INSERTED_CHANNEL: both regular and inserted group @@ -647,12 +868,15 @@ void adc_watchdog_disable(uint32_t adc_periph , uint8_t adc_channel_group) /* select the group */ switch(adc_channel_group){ case ADC_REGULAR_CHANNEL: + /* disable ADC analog watchdog regular channel group */ ADC_CTL0(adc_periph) &= ~((uint32_t)ADC_CTL0_RWDEN); break; case ADC_INSERTED_CHANNEL: + /* disable ADC analog watchdog inserted channel group */ ADC_CTL0(adc_periph) &= ~((uint32_t)ADC_CTL0_IWDEN); break; case ADC_REGULAR_INSERTED_CHANNEL: + /* disable ADC analog watchdog regular and inserted channel group */ ADC_CTL0(adc_periph) &= ~((uint32_t)(ADC_CTL0_RWDEN | ADC_CTL0_IWDEN)); break; default: @@ -661,7 +885,7 @@ void adc_watchdog_disable(uint32_t adc_periph , uint8_t adc_channel_group) } /*! - \brief ADC analog watchdog threshold config + \brief configure ADC analog watchdog threshold \param[in] adc_periph: ADCx,x=0,1,2 \param[in] low_threshold: analog watchdog low threshold,0..4095 \param[in] high_threshold: analog watchdog high threshold,0..4095 @@ -670,294 +894,228 @@ void adc_watchdog_disable(uint32_t adc_periph , uint8_t adc_channel_group) */ void adc_watchdog_threshold_config(uint32_t adc_periph , uint16_t low_threshold , uint16_t high_threshold) { - ADC_WDLT(adc_periph) = (uint32_t)low_threshold; - ADC_WDHT(adc_periph) = (uint32_t)high_threshold; + /* configure ADC analog watchdog low threshold */ + ADC_WDLT(adc_periph) = (uint32_t)WDLT_WDLT(low_threshold); + /* configure ADC analog watchdog high threshold */ + ADC_WDHT(adc_periph) = (uint32_t)WDHT_WDHT(high_threshold); } /*! - \brief ADC regular channel config + \brief get the ADC flag bits \param[in] adc_periph: ADCx,x=0,1,2 - \param[in] rank: the regular group sequencer rank,this parameter must be between 0 to 15 - \param[in] adc_channel: the selected ADC channel - \arg ADC_CHANNEL_x(x=0..18): ADC Channelx - \param[in] sample_time: the sample time value - \arg ADC_SAMPLETIME_3: 3 cycles - \arg ADC_SAMPLETIME_15: 15 cycles - \arg ADC_SAMPLETIME_28: 28 cycles - \arg ADC_SAMPLETIME_56: 56 cycles - \arg ADC_SAMPLETIME_84: 84 cycles - \arg ADC_SAMPLETIME_112: 112 cycles - \arg ADC_SAMPLETIME_144: 144 cycles - \arg ADC_SAMPLETIME_480: 480 cycles + \param[in] adc_flag: the adc flag bits + only one parameter can be selected which is shown as below: + \arg ADC_FLAG_WDE: analog watchdog event flag + \arg ADC_FLAG_EOC: end of group conversion flag + \arg ADC_FLAG_EOIC: end of inserted group conversion flag + \arg ADC_FLAG_STIC: start flag of inserted channel group + \arg ADC_FLAG_STRC: start flag of regular channel group + \arg ADC_FLAG_ROVF: regular data register overflow flag \param[out] none - \retval none + \retval FlagStatus: SET or RESET */ -void adc_regular_channel_config(uint32_t adc_periph , uint8_t rank , uint8_t adc_channel , uint32_t sample_time) +FlagStatus adc_flag_get(uint32_t adc_periph , uint32_t adc_flag) { - uint32_t rsq,sampt; - - /* ADC regular sequence config */ - if(rank < 6U){ - rsq = ADC_RSQ2(adc_periph); - rsq &= ~((uint32_t)(ADC_RSQX_RSQN << (5U*rank))); - rsq |= ((uint32_t)adc_channel << (5U*rank)); - ADC_RSQ2(adc_periph) = rsq; - }else if(rank < 12U){ - rsq = ADC_RSQ1(adc_periph); - rsq &= ~((uint32_t)(ADC_RSQX_RSQN << (5U*(rank-6U)))); - rsq |= ((uint32_t)adc_channel << (5U*(rank-6U))); - ADC_RSQ1(adc_periph) = rsq; - }else if(rank < 16U){ - rsq = ADC_RSQ0(adc_periph); - rsq &= ~((uint32_t)(ADC_RSQX_RSQN << (5U*(rank-12U)))); - rsq |= ((uint32_t)adc_channel << (5U*(rank-12U))); - ADC_RSQ0(adc_periph) = rsq; - }else{ - } - - /* ADC sampling time config */ - if(adc_channel < 10U){ - sampt = ADC_SAMPT1(adc_periph); - sampt &= ~((uint32_t)(ADC_SAMPTX_SPTN << (3U*adc_channel))); - sampt |= (uint32_t)(sample_time << (3U*adc_channel)); - ADC_SAMPT1(adc_periph) = sampt; - }else if(adc_channel < 19U){ - sampt = ADC_SAMPT0(adc_periph); - sampt &= ~((uint32_t)(ADC_SAMPTX_SPTN << (3U*(adc_channel-10U)))); - sampt |= (uint32_t)(sample_time << (3U*(adc_channel-10U))); - ADC_SAMPT0(adc_periph) = sampt; - }else{ + FlagStatus reval = RESET; + if(ADC_STAT(adc_periph) & adc_flag){ + reval = SET; } + return reval; + } /*! - \brief ADC regular group data register read + \brief clear the ADC flag bits \param[in] adc_periph: ADCx,x=0,1,2 - \param[in] none + \param[in] adc_flag: the adc flag bits + only one parameter can be selected which is shown as below: + \arg ADC_FLAG_WDE: analog watchdog event flag + \arg ADC_FLAG_EOC: end of group conversion flag + \arg ADC_FLAG_EOIC: end of inserted group conversion flag + \arg ADC_FLAG_STIC: start flag of inserted channel group + \arg ADC_FLAG_STRC: start flag of regular channel group + \arg ADC_FLAG_ROVF: regular data register overflow flag \param[out] none - \retval the conversion value + \retval none */ -uint16_t adc_regular_data_read(uint32_t adc_periph) +void adc_flag_clear(uint32_t adc_periph , uint32_t adc_flag) { - return (uint16_t)(ADC_RDATA(adc_periph)); + ADC_STAT(adc_periph) &= ~((uint32_t)adc_flag); } /*! - \brief ADC inserted channel config - \param[in] adc_periph: ADCx,x=0,1,2 - \param[in] rank: the inserted group sequencer rank,this parameter must be between 0 to 3 - \param[in] adc_channel: the selected ADC channel - \arg ADC_CHANNEL_x(x=0..18): ADC Channelx - \param[in] sample_time: The sample time value - \arg ADC_SAMPLETIME_3: 3 cycles - \arg ADC_SAMPLETIME_15: 15 cycles - \arg ADC_SAMPLETIME_28: 28 cycles - \arg ADC_SAMPLETIME_56: 56 cycles - \arg ADC_SAMPLETIME_84: 84 cycles - \arg ADC_SAMPLETIME_112: 112 cycles - \arg ADC_SAMPLETIME_144: 144 cycles - \arg ADC_SAMPLETIME_480: 480 cycles + \brief get the bit state of ADCx software start conversion + \param[in] adc_periph: ADCx, x=0,1,2 only one among these parameters can be selected + \param[in] none \param[out] none - \retval none + \retval FlagStatus: SET or RESET */ -void adc_inserted_channel_config(uint32_t adc_periph , uint8_t rank , uint8_t adc_channel , uint8_t sample_time) +FlagStatus adc_regular_software_startconv_flag_get(uint32_t adc_periph) { - uint8_t inserted_length; - uint32_t isq,sampt; - - inserted_length = (uint8_t)GET_BITS(ADC_ISQ(adc_periph) , 20U , 21U); - if(rank < 4U){ - isq = ADC_ISQ(adc_periph); - isq &= ~((uint32_t)(ADC_ISQ_ISQN << (15U-(inserted_length-rank)*5U))); - isq |= ((uint32_t)adc_channel << (15U-(inserted_length-rank)*5U)); - ADC_ISQ(adc_periph) = isq; - } - - if(adc_channel < 10U){ - sampt = ADC_SAMPT1(adc_periph); - sampt &= ~((uint32_t)(ADC_SAMPTX_SPTN << (3U*adc_channel))); - sampt |= (uint32_t) sample_time << (3U*adc_channel); - ADC_SAMPT1(adc_periph) = sampt; - }else if(adc_channel < 19U){ - sampt = ADC_SAMPT0(adc_periph); - sampt &= ~((uint32_t)(ADC_SAMPTX_SPTN << (3U*(adc_channel-10U)))); - sampt |= ((uint32_t)sample_time << (3U*(adc_channel-10U))); - ADC_SAMPT0(adc_periph) = sampt; - }else{ + FlagStatus reval = RESET; + if((uint32_t)RESET != (ADC_STAT(adc_periph) & ADC_STAT_STRC)){ + reval = SET; } + return reval; } /*! - \brief ADC inserted channel offset config - \param[in] adc_periph: ADCx,x=0,1,2 - \param[in] inserted_channel : insert channel select - \arg ADC_INSERTED_CHANNEL_0: inserted channel0 - \arg ADC_INSERTED_CHANNEL_1: inserted channel1 - \arg ADC_INSERTED_CHANNEL_2: inserted channel2 - \arg ADC_INSERTED_CHANNEL_3: inserted channel3 - \param[in] offset : the offset data + \brief get the bit state of ADCx software inserted channel start conversion + \param[in] adc_periph: ADCx, x=0,1,2 only one among these parameters can be selected + \param[in] none \param[out] none - \retval the conversion value + \retval FlagStatus: SET or RESET */ -void adc_inserted_channel_offset_config(uint32_t adc_periph , uint8_t inserted_channel , uint16_t offset) +FlagStatus adc_inserted_software_startconv_flag_get(uint32_t adc_periph) { - /* config the offset of the selected channels */ - if(ADC_INSERTED_CHANNEL_0 == inserted_channel){ - ADC_IOFF0(adc_periph) = (uint32_t)offset; - }else if(ADC_INSERTED_CHANNEL_1 == inserted_channel){ - ADC_IOFF1(adc_periph) = (uint32_t)offset; - }else if(ADC_INSERTED_CHANNEL_2 == inserted_channel){ - ADC_IOFF2(adc_periph) = (uint32_t)offset; - }else if(ADC_INSERTED_CHANNEL_3 == inserted_channel){ - ADC_IOFF3(adc_periph) = (uint32_t)offset; - }else{ - } + FlagStatus reval = RESET; + if((uint32_t)RESET != (ADC_STAT(adc_periph) & ADC_STAT_STIC)){ + reval = SET; + } + return reval; } /*! - \brief ADC inserted group data register read + \brief get the ADC interrupt bits \param[in] adc_periph: ADCx,x=0,1,2 - \param[in] inserted_channel : insert channel select - \arg ADC_INSERTED_CHANNEL_0: inserted Channel0 - \arg ADC_INSERTED_CHANNEL_1: inserted channel1 - \arg ADC_INSERTED_CHANNEL_2: inserted Channel2 - \arg ADC_INSERTED_CHANNEL_3: inserted Channel3 + \param[in] adc_interrupt: the adc interrupt bits + only one parameter can be selected which is shown as below: + \arg ADC_INT_FLAG_WDE: analog watchdog interrupt + \arg ADC_INT_FLAG_EOC: end of group conversion interrupt + \arg ADC_INT_FLAG_EOIC: end of inserted group conversion interrupt + \arg ADC_INT_FLAG_ROVF: regular data register overflow interrupt \param[out] none - \retval the conversion value + \retval FlagStatus: SET or RESET */ -uint16_t adc_inserted_data_read(uint32_t adc_periph , uint8_t inserted_channel) +FlagStatus adc_interrupt_flag_get(uint32_t adc_periph , uint32_t adc_interrupt) { - uint32_t idata; - /* read the data of the selected channel */ - switch(inserted_channel){ - case ADC_INSERTED_CHANNEL_0: - idata = ADC_IDATA0(adc_periph); + FlagStatus interrupt_flag = RESET; + uint32_t state; + /* check the interrupt bits */ + switch(adc_interrupt){ + case ADC_INT_FLAG_WDE: + /* get the ADC analog watchdog interrupt bits */ + state = ADC_STAT(adc_periph) & ADC_STAT_WDE; + if((ADC_CTL0(adc_periph) & ADC_CTL0_WDEIE) && state){ + interrupt_flag = SET; + } break; - case ADC_INSERTED_CHANNEL_1: - idata = ADC_IDATA1(adc_periph); + case ADC_INT_FLAG_EOC: + /* get the ADC end of group conversion interrupt bits */ + state = ADC_STAT(adc_periph) & ADC_STAT_EOC; + if((ADC_CTL0(adc_periph) & ADC_CTL0_EOCIE) && state){ + interrupt_flag = SET; + } break; - case ADC_INSERTED_CHANNEL_2: - idata = ADC_IDATA2(adc_periph); + case ADC_INT_FLAG_EOIC: + /* get the ADC end of inserted group conversion interrupt bits */ + state = ADC_STAT(adc_periph) & ADC_STAT_EOIC; + if((ADC_CTL0(adc_periph) & ADC_CTL0_EOICIE) && state){ + interrupt_flag = SET; + } break; - case ADC_INSERTED_CHANNEL_3: - idata = ADC_IDATA3(adc_periph); + case ADC_INT_FLAG_ROVF: + /* get the ADC regular data register overflow interrupt bits */ + state = ADC_STAT(adc_periph) & ADC_STAT_ROVF; + if((ADC_CTL0(adc_periph) & ADC_CTL0_ROVFIE) && state){ + interrupt_flag = SET; + } break; default: - idata = 0U; break; } - return (uint16_t)idata; -} - -/*! - \brief DMA request enable - \param[in] adc_periph: ADCx,x=0,1,2 - \param[out] none - \retval none -*/ -void adc_dma_mode_enable(uint32_t adc_periph) -{ - ADC_CTL1(adc_periph) |= (uint32_t)(ADC_CTL1_DMA); -} - -/*! - \brief DMA request disable - \param[in] adc_periph: ADCx,x=0,1,2 - \param[out] none - \retval none -*/ -void adc_dma_mode_disable(uint32_t adc_periph) -{ - ADC_CTL1(adc_periph) &= ~((uint32_t)ADC_CTL1_DMA); -} - -/*! - \brief when DMA=1, the DMA engine issues a request at end of each regular conversion - \param[in] adc_periph: ADCx,x=0,1,2 - \param[out] none - \retval none -*/ -void adc_dma_request_after_last_enable(uint32_t adc_periph) -{ - ADC_CTL1(adc_periph) |= (uint32_t)(ADC_CTL1_DDM); + return interrupt_flag; } /*! - \brief the DMA engine is disabled after the end of transfer signal from DMA controller is detected + \brief clear the ADC flag \param[in] adc_periph: ADCx,x=0,1,2 + \param[in] adc_interrupt: the adc status flag + only one parameter can be selected which is shown as below: + \arg ADC_INT_FLAG_WDE: analog watchdog interrupt + \arg ADC_INT_FLAG_EOC: end of group conversion interrupt + \arg ADC_INT_FLAG_EOIC: end of inserted group conversion interrupt + \arg ADC_INT_FLAG_ROVF: regular data register overflow interrupt \param[out] none \retval none */ -void adc_dma_request_after_last_disable(uint32_t adc_periph) +void adc_interrupt_flag_clear(uint32_t adc_periph , uint32_t adc_interrupt) { - ADC_CTL1(adc_periph) &= ~((uint32_t)ADC_CTL1_DDM); + ADC_STAT(adc_periph) &= ~((uint32_t)adc_interrupt); } /*! - \brief ADC oversample mode config + \brief enable ADC interrupt \param[in] adc_periph: ADCx,x=0,1,2 - \param[in] mode: ADC oversampling mode - \arg ADC_OVERSAMPLING_ALL_CONVERT: all oversampled conversions for a channel are done consecutively after a trigger - \arg ADC_OVERSAMPLING_ONE_CONVERT: each oversampled conversion for a channel needs a trigger - \param[in] shift: ADC oversampling shift - \arg ADC_OVERSAMPLING_SHIFT_NONE: no oversampling shift - \arg ADC_OVERSAMPLING_SHIFT_1B: 1-bit oversampling shift - \arg ADC_OVERSAMPLING_SHIFT_2B: 2-bit oversampling shift - \arg ADC_OVERSAMPLING_SHIFT_3B: 3-bit oversampling shift - \arg ADC_OVERSAMPLING_SHIFT_4B: 3-bit oversampling shift - \arg ADC_OVERSAMPLING_SHIFT_5B: 5-bit oversampling shift - \arg ADC_OVERSAMPLING_SHIFT_6B: 6-bit oversampling shift - \arg ADC_OVERSAMPLING_SHIFT_7B: 7-bit oversampling shift - \arg ADC_OVERSAMPLING_SHIFT_8B: 8-bit oversampling shift - \param[in] ratio: ADC oversampling ratio - \arg ADC_OVERSAMPLING_RATIO_MUL2: oversampling ratio multiple 2 - \arg ADC_OVERSAMPLING_RATIO_MUL4: oversampling ratio multiple 4 - \arg ADC_OVERSAMPLING_RATIO_MUL8: oversampling ratio multiple 8 - \arg ADC_OVERSAMPLING_RATIO_MUL16: oversampling ratio multiple 16 - \arg ADC_OVERSAMPLING_RATIO_MUL32: oversampling ratio multiple 32 - \arg ADC_OVERSAMPLING_RATIO_MUL64: oversampling ratio multiple 64 - \arg ADC_OVERSAMPLING_RATIO_MUL128: oversampling ratio multiple 128 - \arg ADC_OVERSAMPLING_RATIO_MUL256: oversampling ratio multiple 256 + \param[in] adc_interrupt: the adc interrupt flag + only one parameter can be selected which is shown as below: + \arg ADC_INT_WDE: analog watchdog interrupt flag + \arg ADC_INT_EOC: end of group conversion interrupt flag + \arg ADC_INT_EOIC: end of inserted group conversion interrupt flag + \arg ADC_INT_ROVF: regular data register overflow interrupt flag \param[out] none \retval none */ -void adc_oversample_mode_config(uint32_t adc_periph , uint8_t mode , uint16_t shift , uint8_t ratio) +void adc_interrupt_enable(uint32_t adc_periph , uint32_t adc_interrupt) { - if(ADC_OVERSAMPLING_ONE_CONVERT == mode){ - ADC_OVSAMPCTL(adc_periph) |= (uint32_t)ADC_OVSAMPCTL_TOVS; - }else{ - ADC_OVSAMPCTL(adc_periph) &= ~((uint32_t)ADC_OVSAMPCTL_TOVS); + switch(adc_interrupt){ + case ADC_INT_WDE: + /* enable analog watchdog interrupt */ + ADC_CTL0(adc_periph) |= (uint32_t) ADC_CTL0_WDEIE; + break; + case ADC_INT_EOC: + /* enable end of group conversion interrupt */ + ADC_CTL0(adc_periph) |= (uint32_t) ADC_CTL0_EOCIE; + break; + case ADC_INT_EOIC: + /* enable end of inserted group conversion interrupt */ + ADC_CTL0(adc_periph) |= (uint32_t) ADC_CTL0_EOICIE; + break; + case ADC_INT_ROVF: + ADC_CTL0(adc_periph) |= (uint32_t) ADC_CTL0_ROVFIE; + break; + default: + break; } - /* config the shift and ratio */ - ADC_OVSAMPCTL(adc_periph) &= ~((uint32_t)(ADC_OVSAMPCTL_OVSR | ADC_OVSAMPCTL_OVSS)); - ADC_OVSAMPCTL(adc_periph) |= ((uint32_t)shift | (uint32_t)ratio); -} - -/*! - \brief ADC oversample mode enable - \param[in] adc_periph: ADCx,x=0,1,2 - \param[out] none - \retval none -*/ -void adc_oversample_mode_enable(uint32_t adc_periph) -{ - ADC_OVSAMPCTL(adc_periph) |= ADC_OVSAMPCTL_OVSEN; } /*! - \brief ADC oversample mode disable + \brief disable ADC interrupt \param[in] adc_periph: ADCx,x=0,1,2 + \param[in] adc_flag: the adc interrupt flag + only one parameter can be selected which is shown as below: + \arg ADC_INT_WDE: analog watchdog interrupt flag + \arg ADC_INT_EOC: end of group conversion interrupt flag + \arg ADC_INT_EOIC: end of inserted group conversion interrupt flag + \arg ADC_INT_ROVF: regular data register overflow interrupt flag \param[out] none \retval none */ -void adc_oversample_mode_disable(uint32_t adc_periph) +void adc_interrupt_disable(uint32_t adc_periph , uint32_t adc_interrupt) { - ADC_OVSAMPCTL(adc_periph) &= ~((uint32_t)ADC_OVSAMPCTL_OVSEN); + switch(adc_interrupt){ + /* select the interrupt source */ + case ADC_INT_WDE: + ADC_CTL0(adc_periph) &= ~((uint32_t)ADC_CTL0_WDEIE); + break; + case ADC_INT_EOC: + ADC_CTL0(adc_periph) &= ~((uint32_t)ADC_CTL0_EOCIE); + break; + case ADC_INT_EOIC: + ADC_CTL0(adc_periph) &= ~((uint32_t)ADC_CTL0_EOICIE); + break; + case ADC_INT_ROVF: + ADC_CTL0(adc_periph) &= ~((uint32_t)ADC_CTL0_ROVFIE); + break; + default: + break; + } } /*! \brief configure the ADC sync mode - \param[in] sync_mode: ADC sync mode + \param[in] sync_mode: ADC sync mode + only one parameter can be selected which is shown as below: \arg ADC_SYNC_MODE_INDEPENDENT: all the ADCs work independently \arg ADC_DAUL_REGULAL_PARALLEL_INSERTED_PARALLEL: ADC0 and ADC1 work in combined regular parallel & inserted parallel mode \arg ADC_DAUL_REGULAL_PARALLEL_INSERTED_ROTATION: ADC0 and ADC1 work in combined regular parallel & trigger rotation mode @@ -982,7 +1140,8 @@ void adc_sync_mode_config(uint32_t sync_mode) /*! \brief configure the delay between 2 sampling phases in ADC sync modes - \param[in] sample_delay: the delay between 2 sampling phases in ADC sync modes + \param[in] sample_delay: the delay between 2 sampling phases in ADC sync modes + only one parameter can be selected which is shown as below: \arg ADC_SYNC_DELAY_xCYCLE: x=5..20,the delay between 2 sampling phases in ADC sync modes is x ADC clock cycles \param[out] none \retval none @@ -996,9 +1155,10 @@ void adc_sync_delay_config(uint32_t sample_delay) /*! \brief configure ADC sync DMA mode selection \param[in] dma_mode: ADC sync DMA mode + only one parameter can be selected which is shown as below: \arg ADC_SYNC_DMA_DISABLE: ADC sync DMA disabled - \arg ADC_SYNC_DMA_MODE0: ADC sync DMA disabled - \arg ADC_SYNC_DMA_MODE1: ADC sync DMA disabled + \arg ADC_SYNC_DMA_MODE0: ADC sync DMA mode 0 + \arg ADC_SYNC_DMA_MODE1: ADC sync DMA mode 1 \param[out] none \retval none */ @@ -1031,7 +1191,7 @@ void adc_sync_dma_request_after_last_disable(void) } /*! - \brief ADC sync regular data register read + \brief read ADC sync regular data register \param[in] none \param[out] none \retval sync regular data diff --git a/bsp/gd32450z-eval/Libraries/GD32F4xx_standard_peripheral/Source/gd32f4xx_can.c b/bsp/gd32450z-eval/Libraries/GD32F4xx_standard_peripheral/Source/gd32f4xx_can.c index eb03822acf..5eb2974739 100644 --- a/bsp/gd32450z-eval/Libraries/GD32F4xx_standard_peripheral/Source/gd32f4xx_can.c +++ b/bsp/gd32450z-eval/Libraries/GD32F4xx_standard_peripheral/Source/gd32f4xx_can.c @@ -1,18 +1,47 @@ /*! - \file gd32f4xx_can.c - \brief CAN driver + \file gd32f4xx_can.c + \brief CAN driver + + \version 2016-08-15, V1.0.0, firmware for GD32F4xx + \version 2018-12-12, V2.0.0, firmware for GD32F4xx + \version 2019-11-27, V2.0.1, firmware for GD32F4xx + \version 2020-07-14, V2.0.2, firmware for GD32F4xx + \version 2020-09-30, V2.1.0, firmware for GD32F4xx */ /* - Copyright (C) 2016 GigaDevice + Copyright (c) 2020, GigaDevice Semiconductor Inc. + + Redistribution and use in source and binary forms, with or without modification, +are permitted provided that the following conditions are met: + + 1. Redistributions of source code must retain the above copyright notice, this + list of conditions and the following disclaimer. + 2. Redistributions in binary form must reproduce the above copyright notice, + this list of conditions and the following disclaimer in the documentation + and/or other materials provided with the distribution. + 3. Neither the name of the copyright holder nor the names of its contributors + may be used to endorse or promote products derived from this software without + specific prior written permission. - 2016-08-15, V1.0.0, firmware for GD32F4xx + THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED +WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. +IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, +INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT +NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR +PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, +WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY +OF SUCH DAMAGE. */ #include "gd32f4xx_can.h" +#define CAN_ERROR_HANDLE(s) do{}while(1) + /*! - \brief deinitialize CAN + \brief deinitialize CAN \param[in] can_periph \arg CANx(x=0,1) \param[out] none @@ -30,21 +59,100 @@ void can_deinit(uint32_t can_periph) } /*! + \brief initialize CAN parameter struct with a default value + \param[in] type: the type of CAN parameter struct + only one parameter can be selected which is shown as below: + \arg CAN_INIT_STRUCT: the CAN initial struct + \arg CAN_FILTER_STRUCT: the CAN filter struct + \arg CAN_TX_MESSAGE_STRUCT: the CAN TX message struct + \arg CAN_RX_MESSAGE_STRUCT: the CAN RX message struct + \param[in] p_struct: the pointer of the specific struct + \param[out] none + \retval none +*/ +void can_struct_para_init(can_struct_type_enum type, void* p_struct) +{ + uint8_t i; + + /* get type of the struct */ + switch(type){ + /* used for can_init() */ + case CAN_INIT_STRUCT: + ((can_parameter_struct*)p_struct)->auto_bus_off_recovery = DISABLE; + ((can_parameter_struct*)p_struct)->no_auto_retrans = DISABLE; + ((can_parameter_struct*)p_struct)->auto_wake_up = DISABLE; + ((can_parameter_struct*)p_struct)->prescaler = 0x03FFU; + ((can_parameter_struct*)p_struct)->rec_fifo_overwrite = DISABLE; + ((can_parameter_struct*)p_struct)->resync_jump_width = CAN_BT_SJW_1TQ; + ((can_parameter_struct*)p_struct)->time_segment_1 = CAN_BT_BS1_3TQ; + ((can_parameter_struct*)p_struct)->time_segment_2 = CAN_BT_BS2_1TQ; + ((can_parameter_struct*)p_struct)->time_triggered = DISABLE; + ((can_parameter_struct*)p_struct)->trans_fifo_order = DISABLE; + ((can_parameter_struct*)p_struct)->working_mode = CAN_NORMAL_MODE; + + break; + /* used for can_filter_init() */ + case CAN_FILTER_STRUCT: + ((can_filter_parameter_struct*)p_struct)->filter_bits = CAN_FILTERBITS_32BIT; + ((can_filter_parameter_struct*)p_struct)->filter_enable = DISABLE; + ((can_filter_parameter_struct*)p_struct)->filter_fifo_number = CAN_FIFO0; + ((can_filter_parameter_struct*)p_struct)->filter_list_high = 0x0000U; + ((can_filter_parameter_struct*)p_struct)->filter_list_low = 0x0000U; + ((can_filter_parameter_struct*)p_struct)->filter_mask_high = 0x0000U; + ((can_filter_parameter_struct*)p_struct)->filter_mask_low = 0x0000U; + ((can_filter_parameter_struct*)p_struct)->filter_mode = CAN_FILTERMODE_MASK; + ((can_filter_parameter_struct*)p_struct)->filter_number = 0U; + + break; + /* used for can_message_transmit() */ + case CAN_TX_MESSAGE_STRUCT: + for(i = 0U; i < 8U; i++){ + ((can_trasnmit_message_struct*)p_struct)->tx_data[i] = 0U; + } + + ((can_trasnmit_message_struct*)p_struct)->tx_dlen = 0u; + ((can_trasnmit_message_struct*)p_struct)->tx_efid = 0U; + ((can_trasnmit_message_struct*)p_struct)->tx_ff = (uint8_t)CAN_FF_STANDARD; + ((can_trasnmit_message_struct*)p_struct)->tx_ft = (uint8_t)CAN_FT_DATA; + ((can_trasnmit_message_struct*)p_struct)->tx_sfid = 0U; + + break; + /* used for can_message_receive() */ + case CAN_RX_MESSAGE_STRUCT: + for(i = 0U; i < 8U; i++){ + ((can_receive_message_struct*)p_struct)->rx_data[i] = 0U; + } + + ((can_receive_message_struct*)p_struct)->rx_dlen = 0U; + ((can_receive_message_struct*)p_struct)->rx_efid = 0U; + ((can_receive_message_struct*)p_struct)->rx_ff = (uint8_t)CAN_FF_STANDARD; + ((can_receive_message_struct*)p_struct)->rx_fi = 0U; + ((can_receive_message_struct*)p_struct)->rx_ft = (uint8_t)CAN_FT_DATA; + ((can_receive_message_struct*)p_struct)->rx_sfid = 0U; + + break; + + default: + CAN_ERROR_HANDLE("parameter is invalid \r\n"); + } +} + +/*! \brief initialize CAN \param[in] can_periph \arg CANx(x=0,1) - \param[in] can_parameter_struct: parameters for CAN initializtion - can_mode: CAN_NORMAL_MODE, CAN_LOOPBACK_MODE, CAN_SILENT_MODE, CAN_SILENT_LOOPBACK_MODE - can_sjw: CAN_BT_SJW_xTQ(x=1, 2, 3, 4) - can_bs1: CAN_BT_BS1_xTQ(1..16) - can_bs2: CAN_BT_BS2_xTQ(1..8) - can_ttc: ENABLE or DISABLE - can_abor: ENABLE or DISABLE - can_awu: ENABLE or DISABLE - can_ard: ENABLE or DISABLE - can_rfod: ENABLE or DISABLE - can_tfo: ENABLE or DISABLE - can_psc: 0x0001 - 0x03FF + \param[in] can_parameter_init: parameters for CAN initializtion + \arg working_mode: CAN_NORMAL_MODE, CAN_LOOPBACK_MODE, CAN_SILENT_MODE, CAN_SILENT_LOOPBACK_MODE + \arg resync_jump_width: CAN_BT_SJW_xTQ(x=1, 2, 3, 4) + \arg time_segment_1: CAN_BT_BS1_xTQ(1..16) + \arg time_segment_2: CAN_BT_BS2_xTQ(1..8) + \arg time_triggered: ENABLE or DISABLE + \arg auto_bus_off_recovery: ENABLE or DISABLE + \arg auto_wake_up: ENABLE or DISABLE + \arg no_auto_retrans: ENABLE or DISABLE + \arg rec_fifo_overwrite: ENABLE or DISABLE + \arg trans_fifo_order: ENABLE or DISABLE + \arg prescaler: 0x0001 - 0x0400 \param[out] none \retval ErrStatus: SUCCESS or ERROR */ @@ -52,19 +160,19 @@ ErrStatus can_init(uint32_t can_periph, can_parameter_struct* can_parameter_init { uint32_t timeout = CAN_TIMEOUT; ErrStatus flag = ERROR; - + /* disable sleep mode */ CAN_CTL(can_periph) &= ~CAN_CTL_SLPWMOD; /* enable initialize mode */ CAN_CTL(can_periph) |= CAN_CTL_IWMOD; /* wait ACK */ - while((CAN_STAT_IWS != (CAN_STAT(can_periph) & CAN_STAT_IWS)) && (timeout)){ + while((CAN_STAT_IWS != (CAN_STAT(can_periph) & CAN_STAT_IWS)) && (0U != timeout)){ timeout--; } /* check initialize working success */ if(CAN_STAT_IWS != (CAN_STAT(can_periph) & CAN_STAT_IWS)){ flag = ERROR; - } else { + }else{ /* set the bit timing register */ CAN_BT(can_periph) = (BT_MODE((uint32_t)can_parameter_init->working_mode) | \ BT_SJW((uint32_t)can_parameter_init->resync_jump_width) | \ @@ -89,64 +197,64 @@ ErrStatus can_init(uint32_t can_periph, can_parameter_struct* can_parameter_init }else{ CAN_CTL(can_periph) &= ~CAN_CTL_AWU; } - /* automatic retransmission mode */ - if(ENABLE == can_parameter_init->auto_retrans){ + /* automatic retransmission mode disable*/ + if(ENABLE == can_parameter_init->no_auto_retrans){ CAN_CTL(can_periph) |= CAN_CTL_ARD; }else{ CAN_CTL(can_periph) &= ~CAN_CTL_ARD; } - /* receive fifo overwrite mode */ + /* receive fifo overwrite mode */ if(ENABLE == can_parameter_init->rec_fifo_overwrite){ CAN_CTL(can_periph) |= CAN_CTL_RFOD; }else{ CAN_CTL(can_periph) &= ~CAN_CTL_RFOD; - } + } /* transmit fifo order */ if(ENABLE == can_parameter_init->trans_fifo_order){ CAN_CTL(can_periph) |= CAN_CTL_TFO; }else{ CAN_CTL(can_periph) &= ~CAN_CTL_TFO; - } + } /* disable initialize mode */ CAN_CTL(can_periph) &= ~CAN_CTL_IWMOD; timeout = CAN_TIMEOUT; /* wait the ACK */ - while((CAN_STAT_IWS == (CAN_STAT(can_periph) & CAN_STAT_IWS)) && (timeout)){ + while((CAN_STAT_IWS == (CAN_STAT(can_periph) & CAN_STAT_IWS)) && (0U != timeout)){ timeout--; } /* check exit initialize mode */ if(CAN_STAT_IWS == (CAN_STAT(can_periph) & CAN_STAT_IWS)){ flag = SUCCESS; } - } + } return flag; } /*! - \brief initialize CAN filter - \param[in] can_filter_parameter_struct: struct for CAN filter initialization - can_filter_list_high: 0x0000 - 0xFFFF - can_filter_list_low: 0x0000 - 0xFFFF - can_filter_mask_high: 0x0000 - 0xFFFF - can_filter_mask_low: 0x0000 - 0xFFFF - can_filter_fifo_number: CAN_FIFO0, CAN_FIFO1 - can_filter_number: 0 - 27 - can_filter_mode: CAN_FILTERMODE_MASK, CAN_FILTERMODE_LIST - can_filter_bits: CAN_FILTERBITS_32BIT, CAN_FILTERBITS_16BIT - can_filter_enable: ENABLE or DISABLE + \brief initialize CAN filter + \param[in] can_filter_parameter_init: struct for CAN filter initialization + \arg filter_list_high: 0x0000 - 0xFFFF + \arg filter_list_low: 0x0000 - 0xFFFF + \arg filter_mask_high: 0x0000 - 0xFFFF + \arg filter_mask_low: 0x0000 - 0xFFFF + \arg filter_fifo_number: CAN_FIFO0, CAN_FIFO1 + \arg filter_number: 0 - 27 + \arg filter_mode: CAN_FILTERMODE_MASK, CAN_FILTERMODE_LIST + \arg filter_bits: CAN_FILTERBITS_32BIT, CAN_FILTERBITS_16BIT + \arg filter_enable: ENABLE or DISABLE \param[out] none \retval none */ void can_filter_init(can_filter_parameter_struct* can_filter_parameter_init) { uint32_t val = 0U; - + val = ((uint32_t)1) << (can_filter_parameter_init->filter_number); /* filter lock disable */ CAN_FCTL(CAN0) |= CAN_FCTL_FLD; /* disable filter */ CAN_FW(CAN0) &= ~(uint32_t)val; - + /* filter 16 bits */ if(CAN_FILTERBITS_16BIT == can_filter_parameter_init->filter_bits){ /* set filter 16 bits */ @@ -173,7 +281,7 @@ void can_filter_init(can_filter_parameter_struct* can_filter_parameter_init) FDATA_MASK_HIGH((can_filter_parameter_init->filter_mask_high) & CAN_FILTER_MASK_16BITS) | FDATA_MASK_LOW((can_filter_parameter_init->filter_mask_low) & CAN_FILTER_MASK_16BITS); } - + /* filter mode */ if(CAN_FILTERMODE_MASK == can_filter_parameter_init->filter_mode){ /* mask mode */ @@ -182,24 +290,24 @@ void can_filter_init(can_filter_parameter_struct* can_filter_parameter_init) /* list mode */ CAN_FMCFG(CAN0) |= (uint32_t)val; } - + /* filter FIFO */ if(CAN_FIFO0 == (can_filter_parameter_init->filter_fifo_number)){ /* FIFO0 */ CAN_FAFIFO(CAN0) &= ~(uint32_t)val; } - + if(CAN_FIFO1 == can_filter_parameter_init->filter_fifo_number){ /* FIFO1 */ CAN_FAFIFO(CAN0) |= (uint32_t)val; } - + /* filter working */ if(ENABLE == can_filter_parameter_init->filter_enable){ - + CAN_FW(CAN0) |= (uint32_t)val; } - + /* filter lock enable */ CAN_FCTL(CAN0) &= ~CAN_FCTL_FLD; } @@ -266,11 +374,11 @@ void can_debug_freeze_disable(uint32_t can_periph) void can_time_trigger_mode_enable(uint32_t can_periph) { uint8_t mailbox_number; - + /* enable the tcc mode */ CAN_CTL(can_periph) |= CAN_CTL_TTC; /* enable time stamp */ - for(mailbox_number=0U; mailbox_number<3U; mailbox_number++){ + for(mailbox_number = 0U; mailbox_number < 3U; mailbox_number++){ CAN_TMP(can_periph, mailbox_number) |= CAN_TMP_TSEN; } } @@ -284,29 +392,29 @@ void can_time_trigger_mode_enable(uint32_t can_periph) */ void can_time_trigger_mode_disable(uint32_t can_periph) { - uint8_t mailbox_number; - + uint8_t mailbox_number; + /* disable the TCC mode */ CAN_CTL(can_periph) &= ~CAN_CTL_TTC; /* reset TSEN bits */ - for(mailbox_number=0U; mailbox_number<3U; mailbox_number++){ + for(mailbox_number = 0U; mailbox_number < 3U; mailbox_number++){ CAN_TMP(can_periph, mailbox_number) &= ~CAN_TMP_TSEN; } } /*! - \brief CAN transmit message + \brief transmit CAN message \param[in] can_periph \arg CANx(x=0,1) - \param[in] can_trasnmit_message_struct: struct for CAN transmit message - can_rx_sfid: 0x00000000 - 0x000007FF - can_rx_efid: 0x00000000 - 0x1FFFFFFF - can_rx_ff: CAN_FF_STANDARD, CAN_FF_EXTENDED - can_rx_ft: CAN_FT_DATA, CAN_FT_REMOTE - can_rx_dlenc: 1 - 7 - can_rx_data[]: 0x00 - 0xFF + \param[in] transmit_message: struct for CAN transmit message + \arg tx_sfid: 0x00000000 - 0x000007FF + \arg tx_efid: 0x00000000 - 0x1FFFFFFF + \arg tx_ff: CAN_FF_STANDARD, CAN_FF_EXTENDED + \arg tx_ft: CAN_FT_DATA, CAN_FT_REMOTE + \arg tx_dlen: 0 - 8 + \arg tx_data[]: 0x00 - 0xFF \param[out] none - \retval none + \retval mailbox_number */ uint8_t can_message_transmit(uint32_t can_periph, can_trasnmit_message_struct* transmit_message) { @@ -322,10 +430,11 @@ uint8_t can_message_transmit(uint32_t can_periph, can_trasnmit_message_struct* t }else{ mailbox_number = CAN_NOMAILBOX; } + /* return no mailbox empty */ if(CAN_NOMAILBOX == mailbox_number){ return CAN_NOMAILBOX; } - + CAN_TMI(can_periph, mailbox_number) &= CAN_TMI_TEN; if(CAN_FF_STANDARD == transmit_message->tx_ff){ /* set transmit mailbox standard identifier */ @@ -357,10 +466,11 @@ uint8_t can_message_transmit(uint32_t can_periph, can_trasnmit_message_struct* t } /*! - \brief CAN transmit state + \brief get CAN transmit state \param[in] can_periph \arg CANx(x=0,1) \param[in] mailbox_number + only one parameter can be selected which is shown as below: \arg CAN_MAILBOX(x=0,1,2) \param[out] none \retval can_transmit_state_enum @@ -369,14 +479,18 @@ can_transmit_state_enum can_transmit_states(uint32_t can_periph, uint8_t mailbox { can_transmit_state_enum state = CAN_TRANSMIT_FAILED; uint32_t val = 0U; - + + /* check selected mailbox state */ switch(mailbox_number){ + /* mailbox0 */ case CAN_MAILBOX0: val = CAN_TSTAT(can_periph) & (CAN_TSTAT_MTF0 | CAN_TSTAT_MTFNERR0 | CAN_TSTAT_TME0); break; + /* mailbox1 */ case CAN_MAILBOX1: val = CAN_TSTAT(can_periph) & (CAN_TSTAT_MTF1 | CAN_TSTAT_MTFNERR1 | CAN_TSTAT_TME1); break; + /* mailbox2 */ case CAN_MAILBOX2: val = CAN_TSTAT(can_periph) & (CAN_TSTAT_MTF2 | CAN_TSTAT_MTFNERR2 | CAN_TSTAT_TME2); break; @@ -384,32 +498,36 @@ can_transmit_state_enum can_transmit_states(uint32_t can_periph, uint8_t mailbox val = CAN_TRANSMIT_FAILED; break; } + switch(val){ - /* transmit pending */ - case (CAN_STATE_PENDING): + /* transmit pending */ + case (CAN_STATE_PENDING): state = CAN_TRANSMIT_PENDING; break; /* transmit failed */ - case (CAN_TSTAT_MTF0 | CAN_TSTAT_TME0): + case (CAN_TSTAT_MTF0 | CAN_TSTAT_TME0): state = CAN_TRANSMIT_FAILED; break; - case (CAN_TSTAT_MTF1 | CAN_TSTAT_TME1): + case (CAN_TSTAT_MTF1 | CAN_TSTAT_TME1): state = CAN_TRANSMIT_FAILED; break; - case (CAN_TSTAT_MTF2 | CAN_TSTAT_TME2): + case (CAN_TSTAT_MTF2 | CAN_TSTAT_TME2): state = CAN_TRANSMIT_FAILED; break; /* transmit succeeded */ case (CAN_TSTAT_MTF0 | CAN_TSTAT_MTFNERR0 | CAN_TSTAT_TME0): state = CAN_TRANSMIT_OK; break; + /* mailbox1 transmit succeeded */ case (CAN_TSTAT_MTF1 | CAN_TSTAT_MTFNERR1 | CAN_TSTAT_TME1): state = CAN_TRANSMIT_OK; break; + /* mailbox2 transmit succeeded */ case (CAN_TSTAT_MTF2 | CAN_TSTAT_MTFNERR2 | CAN_TSTAT_TME2): state = CAN_TRANSMIT_OK; break; - default: + /* transmit failed */ + default: state = CAN_TRANSMIT_FAILED; break; } @@ -417,10 +535,11 @@ can_transmit_state_enum can_transmit_states(uint32_t can_periph, uint8_t mailbox } /*! - \brief CAN stop transmission + \brief stop CAN transmission \param[in] can_periph \arg CANx(x=0,1) \param[in] mailbox_number + only one parameter can be selected which is shown as below: \arg CAN_MAILBOXx(x=0,1,2) \param[out] none \retval none @@ -429,12 +548,18 @@ void can_transmission_stop(uint32_t can_periph, uint8_t mailbox_number) { if(CAN_MAILBOX0 == mailbox_number){ CAN_TSTAT(can_periph) |= CAN_TSTAT_MST0; + while(CAN_TSTAT_MST0 == (CAN_TSTAT(can_periph) & CAN_TSTAT_MST0)){ + } }else if(CAN_MAILBOX1 == mailbox_number){ CAN_TSTAT(can_periph) |= CAN_TSTAT_MST1; + while(CAN_TSTAT_MST1 == (CAN_TSTAT(can_periph) & CAN_TSTAT_MST1)){ + } }else if(CAN_MAILBOX2 == mailbox_number){ CAN_TSTAT(can_periph) |= CAN_TSTAT_MST2; + while(CAN_TSTAT_MST2 == (CAN_TSTAT(can_periph) & CAN_TSTAT_MST2)){ + } }else{ - /* illegal parameter*/ + /* illegal parameters */ } } @@ -443,15 +568,15 @@ void can_transmission_stop(uint32_t can_periph, uint8_t mailbox_number) \param[in] can_periph \arg CANx(x=0,1) \param[in] fifo_number - \arg CAN_FIFO0x(x=0,1) - \param[out] can_receive_message_struct: struct for CAN receive message - can_rx_sfid: 0x00000000 - 0x000007FF - can_rx_efid: 0x00000000 - 0x1FFFFFFF - can_rx_ff: CAN_FF_STANDARD, CAN_FF_EXTENDED - can_rx_ft: CAN_FT_DATA, CAN_FT_REMOTE - can_rx_dlenc: 1 - 7 - can_rx_data[]: 0x00 - 0xFF - can_rx_fi: 0 - 27 + \arg CAN_FIFOx(x=0,1) + \param[out] receive_message: struct for CAN receive message + \arg rx_sfid: 0x00000000 - 0x000007FF + \arg rx_efid: 0x00000000 - 0x1FFFFFFF + \arg rx_ff: CAN_FF_STANDARD, CAN_FF_EXTENDED + \arg rx_ft: CAN_FT_DATA, CAN_FT_REMOTE + \arg rx_dlen: 0 - 8 + \arg rx_data[]: 0x00 - 0xFF + \arg rx_fi: 0 - 27 \retval none */ void can_message_receive(uint32_t can_periph, uint8_t fifo_number, can_receive_message_struct* receive_message) @@ -460,29 +585,29 @@ void can_message_receive(uint32_t can_periph, uint8_t fifo_number, can_receive_m receive_message->rx_ff = (uint8_t)(CAN_RFIFOMI_FF & CAN_RFIFOMI(can_periph, fifo_number)); if(CAN_FF_STANDARD == receive_message->rx_ff){ /* get standard identifier */ - receive_message -> rx_sfid = (uint32_t)(RFIFOMI_SFID(CAN_RFIFOMI(can_periph, fifo_number))); + receive_message->rx_sfid = (uint32_t)(GET_RFIFOMI_SFID(CAN_RFIFOMI(can_periph, fifo_number))); }else{ /* get extended identifier */ - receive_message -> rx_efid = (uint32_t)(RFIFOMI_EFID(CAN_RFIFOMI(can_periph, fifo_number))); + receive_message->rx_efid = (uint32_t)(GET_RFIFOMI_EFID(CAN_RFIFOMI(can_periph, fifo_number))); } - + /* get frame type */ - receive_message -> rx_ft = (uint8_t)(CAN_RFIFOMI_FT & CAN_RFIFOMI(can_periph, fifo_number)); - /* get recevie data length */ - receive_message -> rx_dlen = (uint8_t)(RFIFOMP_DLENC(CAN_RFIFOMP(can_periph, fifo_number))); + receive_message->rx_ft = (uint8_t)(CAN_RFIFOMI_FT & CAN_RFIFOMI(can_periph, fifo_number)); /* filtering index */ - receive_message -> rx_fi = (uint8_t)(RFIFOMP_FI(CAN_RFIFOMP(can_periph, fifo_number))); - + receive_message->rx_fi = (uint8_t)(GET_RFIFOMP_FI(CAN_RFIFOMP(can_periph, fifo_number))); + /* get recevie data length */ + receive_message->rx_dlen = (uint8_t)(GET_RFIFOMP_DLENC(CAN_RFIFOMP(can_periph, fifo_number))); + /* receive data */ - receive_message -> rx_data[0] = (uint8_t)(RFIFOMDATA0_DB0(CAN_RFIFOMDATA0(can_periph, fifo_number))); - receive_message -> rx_data[1] = (uint8_t)(RFIFOMDATA0_DB1(CAN_RFIFOMDATA0(can_periph, fifo_number))); - receive_message -> rx_data[2] = (uint8_t)(RFIFOMDATA0_DB2(CAN_RFIFOMDATA0(can_periph, fifo_number))); - receive_message -> rx_data[3] = (uint8_t)(RFIFOMDATA0_DB3(CAN_RFIFOMDATA0(can_periph, fifo_number))); - receive_message -> rx_data[4] = (uint8_t)(RFIFOMDATA1_DB4(CAN_RFIFOMDATA1(can_periph, fifo_number))); - receive_message -> rx_data[5] = (uint8_t)(RFIFOMDATA1_DB5(CAN_RFIFOMDATA1(can_periph, fifo_number))); - receive_message -> rx_data[6] = (uint8_t)(RFIFOMDATA1_DB6(CAN_RFIFOMDATA1(can_periph, fifo_number))); - receive_message -> rx_data[7] = (uint8_t)(RFIFOMDATA1_DB7(CAN_RFIFOMDATA1(can_periph, fifo_number))); - + receive_message -> rx_data[0] = (uint8_t)(GET_RFIFOMDATA0_DB0(CAN_RFIFOMDATA0(can_periph, fifo_number))); + receive_message -> rx_data[1] = (uint8_t)(GET_RFIFOMDATA0_DB1(CAN_RFIFOMDATA0(can_periph, fifo_number))); + receive_message -> rx_data[2] = (uint8_t)(GET_RFIFOMDATA0_DB2(CAN_RFIFOMDATA0(can_periph, fifo_number))); + receive_message -> rx_data[3] = (uint8_t)(GET_RFIFOMDATA0_DB3(CAN_RFIFOMDATA0(can_periph, fifo_number))); + receive_message -> rx_data[4] = (uint8_t)(GET_RFIFOMDATA1_DB4(CAN_RFIFOMDATA1(can_periph, fifo_number))); + receive_message -> rx_data[5] = (uint8_t)(GET_RFIFOMDATA1_DB5(CAN_RFIFOMDATA1(can_periph, fifo_number))); + receive_message -> rx_data[6] = (uint8_t)(GET_RFIFOMDATA1_DB6(CAN_RFIFOMDATA1(can_periph, fifo_number))); + receive_message -> rx_data[7] = (uint8_t)(GET_RFIFOMDATA1_DB7(CAN_RFIFOMDATA1(can_periph, fifo_number))); + /* release FIFO */ if(CAN_FIFO0 == fifo_number){ CAN_RFIFO0(can_periph) |= CAN_RFIFO0_RFD0; @@ -495,7 +620,9 @@ void can_message_receive(uint32_t can_periph, uint8_t fifo_number, can_receive_m \brief release FIFO0 \param[in] can_periph \arg CANx(x=0,1) - \arg CAN_FIFO0x(x=0,1) + \param[in] fifo_number + only one parameter can be selected which is shown as below: + \arg CAN_FIFOx(x=0,1) \param[out] none \retval none */ @@ -506,7 +633,8 @@ void can_fifo_release(uint32_t can_periph, uint8_t fifo_number) }else if(CAN_FIFO1 == fifo_number){ CAN_RFIFO1(can_periph) |= CAN_RFIFO1_RFD1; }else{ - /* illegal parameter */ + /* illegal parameters */ + CAN_ERROR_HANDLE("CAN FIFO NUM is invalid \r\n"); } } @@ -514,20 +642,24 @@ void can_fifo_release(uint32_t can_periph, uint8_t fifo_number) \brief CAN receive message length \param[in] can_periph \arg CANx(x=0,1) - \arg CAN_FIFO0x(x=0,1) + \param[in] fifo_number + only one parameter can be selected which is shown as below: + \arg CAN_FIFOx(x=0,1) \param[out] none \retval message length */ -uint8_t can_receive_message_length(uint32_t can_periph, uint8_t fifo_number) +uint8_t can_receive_message_length_get(uint32_t can_periph, uint8_t fifo_number) { uint8_t val = 0U; - + if(CAN_FIFO0 == fifo_number){ - val = (uint8_t)(CAN_RFIFO0(can_periph) & CAN_RFIFO_RFL0_MASK); - }else if(CAN_FIFO0 == fifo_number){ - val = (uint8_t)(CAN_RFIFO1(can_periph) & CAN_RFIFO_RFL0_MASK); + /* FIFO0 */ + val = (uint8_t)(CAN_RFIFO0(can_periph) & CAN_RFIF_RFL_MASK); + }else if(CAN_FIFO1 == fifo_number){ + /* FIFO1 */ + val = (uint8_t)(CAN_RFIFO1(can_periph) & CAN_RFIF_RFL_MASK); }else{ - /* illegal parameter */ + /* illegal parameters */ } return val; } @@ -537,25 +669,26 @@ uint8_t can_receive_message_length(uint32_t can_periph, uint8_t fifo_number) \param[in] can_periph \arg CANx(x=0,1) \param[in] can_working_mode - \arg CAN_INITIALIZE_MODE - \arg CAN_NORMAL_MODE - \arg CAN_SLEEP_MODE + only one parameter can be selected which is shown as below: + \arg CAN_MODE_INITIALIZE + \arg CAN_MODE_NORMAL + \arg CAN_MODE_SLEEP \param[out] none \retval ErrStatus: SUCCESS or ERROR */ ErrStatus can_working_mode_set(uint32_t can_periph, uint8_t working_mode) { ErrStatus flag = ERROR; - /* timeout for IWS or also for SLPWS bits*/ - uint32_t timeout = CAN_TIMEOUT; - + /* timeout for IWS or also for SLPWS bits */ + uint32_t timeout = CAN_TIMEOUT; + if(CAN_MODE_INITIALIZE == working_mode){ /* disable sleep mode */ CAN_CTL(can_periph) &= (~(uint32_t)CAN_CTL_SLPWMOD); /* set initialize mode */ CAN_CTL(can_periph) |= (uint8_t)CAN_CTL_IWMOD; /* wait the acknowledge */ - while((CAN_STAT_IWS != (CAN_STAT(can_periph) & CAN_STAT_IWS)) && (timeout != 0U)){ + while((CAN_STAT_IWS != (CAN_STAT(can_periph) & CAN_STAT_IWS)) && (0U != timeout)){ timeout--; } if(CAN_STAT_IWS != (CAN_STAT(can_periph) & CAN_STAT_IWS)){ @@ -567,7 +700,7 @@ ErrStatus can_working_mode_set(uint32_t can_periph, uint8_t working_mode) /* enter normal mode */ CAN_CTL(can_periph) &= ~(uint32_t)(CAN_CTL_SLPWMOD | CAN_CTL_IWMOD); /* wait the acknowledge */ - while((0U != (CAN_STAT(can_periph) & (CAN_STAT_IWS | CAN_STAT_SLPWS))) && (timeout != 0U)){ + while((0U != (CAN_STAT(can_periph) & (CAN_STAT_IWS | CAN_STAT_SLPWS))) && (0U != timeout)){ timeout--; } if(0U != (CAN_STAT(can_periph) & (CAN_STAT_IWS | CAN_STAT_SLPWS))){ @@ -581,10 +714,10 @@ ErrStatus can_working_mode_set(uint32_t can_periph, uint8_t working_mode) /* set sleep mode */ CAN_CTL(can_periph) |= (uint8_t)CAN_CTL_SLPWMOD; /* wait the acknowledge */ - while((CAN_STAT_SLPWS != (CAN_STAT(can_periph) & CAN_STAT_SLPWS)) && (timeout != 0U)){ + while((CAN_STAT_SLPWS != (CAN_STAT(can_periph) & CAN_STAT_SLPWS)) && (0U != timeout)){ timeout--; } - if (CAN_STAT_SLPWS != (CAN_STAT(can_periph) & CAN_STAT_SLPWS)){ + if(CAN_STAT_SLPWS != (CAN_STAT(can_periph) & CAN_STAT_SLPWS)){ flag = ERROR; }else{ flag = SUCCESS; @@ -592,7 +725,7 @@ ErrStatus can_working_mode_set(uint32_t can_periph, uint8_t working_mode) }else{ flag = ERROR; } - return flag; + return flag; } /*! @@ -606,13 +739,14 @@ ErrStatus can_wakeup(uint32_t can_periph) { ErrStatus flag = ERROR; uint32_t timeout = CAN_TIMEOUT; - + /* wakeup */ CAN_CTL(can_periph) &= ~CAN_CTL_SLPWMOD; - - while((0U != (CAN_STAT(can_periph) & CAN_STAT_SLPWS)) && (timeout != 0x00U)){ + + while((0U != (CAN_STAT(can_periph) & CAN_STAT_SLPWS)) && (0x00U != timeout)){ timeout--; } + /* check state */ if(0U != (CAN_STAT(can_periph) & CAN_STAT_SLPWS)){ flag = ERROR; }else{ @@ -627,66 +761,76 @@ ErrStatus can_wakeup(uint32_t can_periph) \arg CANx(x=0,1) \param[out] none \retval can_error_enum + \arg CAN_ERROR_NONE: no error + \arg CAN_ERROR_FILL: fill error + \arg CAN_ERROR_FORMATE: format error + \arg CAN_ERROR_ACK: ACK error + \arg CAN_ERROR_BITRECESSIVE: bit recessive + \arg CAN_ERROR_BITDOMINANTER: bit dominant error + \arg CAN_ERROR_CRC: CRC error + \arg CAN_ERROR_SOFTWARECFG: software configure */ can_error_enum can_error_get(uint32_t can_periph) { can_error_enum error; error = CAN_ERROR_NONE; - + /* get error type */ - error = (can_error_enum)((CAN_ERR(can_periph) & CAN_ERR_ERRN) >> 4U); + error = (can_error_enum)(GET_ERR_ERRN(CAN_ERR(can_periph))); return error; } /*! - \brief CAN receive error number + \brief get CAN receive error number \param[in] can_periph \arg CANx(x=0,1) \param[out] none \retval error number */ -uint8_t can_receive_error_number(uint32_t can_periph) +uint8_t can_receive_error_number_get(uint32_t can_periph) { uint8_t val; - - val = (uint8_t)((CAN_ERR(can_periph) & CAN_ERR_RECNT) >> 24U); + + /* get error count */ + val = (uint8_t)(GET_ERR_RECNT(CAN_ERR(can_periph))); return val; } /*! - \brief CAN transmit error number + \brief get CAN transmit error number \param[in] can_periph \arg CANx(x=0,1) \param[out] none \retval error number */ -uint8_t can_transmit_error_number(uint32_t can_periph) +uint8_t can_transmit_error_number_get(uint32_t can_periph) { uint8_t val; - - val = (uint8_t)((CAN_ERR(can_periph) & CAN_ERR_TECNT) >> 16U); + + val = (uint8_t)(GET_ERR_TECNT(CAN_ERR(can_periph))); return val; } /*! - \brief enable CAN interrupt + \brief enable CAN interrupt \param[in] can_periph \arg CANx(x=0,1) - \param[in] interrupt - \arg CAN_INTEN_TMEIE - \arg CAN_INTEN_RFNEIE0 - \arg CAN_INTEN_RFFIE0 - \arg CAN_INTEN_RFOIE0 - \arg CAN_INTEN_RFNEIE1 - \arg CAN_INTEN_RFFIE1 - \arg CAN_INTEN_RFOIE1 - \arg CAN_INTEN_WERRIE - \arg CAN_INTEN_PERRIE - \arg CAN_INTEN_BOIE - \arg CAN_INTEN_ERRNIE - \arg CAN_INTEN_ERRIE - \arg CAN_INTEN_WUIE - \arg CAN_INTEN_SLPWIE + \param[in] interrupt + one or more parameters can be selected which are shown as below: + \arg CAN_INT_TME: transmit mailbox empty interrupt enable + \arg CAN_INT_RFNE0: receive FIFO0 not empty interrupt enable + \arg CAN_INT_RFF0: receive FIFO0 full interrupt enable + \arg CAN_INT_RFO0: receive FIFO0 overfull interrupt enable + \arg CAN_INT_RFNE1: receive FIFO1 not empty interrupt enable + \arg CAN_INT_RFF1: receive FIFO1 full interrupt enable + \arg CAN_INT_RFO1: receive FIFO1 overfull interrupt enable + \arg CAN_INT_WERR: warning error interrupt enable + \arg CAN_INT_PERR: passive error interrupt enable + \arg CAN_INT_BO: bus-off interrupt enable + \arg CAN_INT_ERRN: error number interrupt enable + \arg CAN_INT_ERR: error interrupt enable + \arg CAN_INT_WU: wakeup interrupt enable + \arg CAN_INT_SLPW: sleep working interrupt enable \param[out] none \retval none */ @@ -696,24 +840,25 @@ void can_interrupt_enable(uint32_t can_periph, uint32_t interrupt) } /*! - \brief disable CAN interrupt + \brief disable CAN interrupt \param[in] can_periph \arg CANx(x=0,1) \param[in] interrupt - \arg CAN_INTEN_TMEIE - \arg CAN_INTEN_RFNEIE0 - \arg CAN_INTEN_RFFIE0 - \arg CAN_INTEN_RFOIE0 - \arg CAN_INTEN_RFNEIE1 - \arg CAN_INTEN_RFFIE1 - \arg CAN_INTEN_RFOIE1 - \arg CAN_INTEN_WERRIE - \arg CAN_INTEN_PERRIE - \arg CAN_INTEN_BOIE - \arg CAN_INTEN_ERRNIE - \arg CAN_INTEN_ERRIE - \arg CAN_INTEN_WUIE - \arg CAN_INTEN_SLPWIE + one or more parameters can be selected which are shown as below: + \arg CAN_INT_TME: transmit mailbox empty interrupt enable + \arg CAN_INT_RFNE0: receive FIFO0 not empty interrupt enable + \arg CAN_INT_RFF0: receive FIFO0 full interrupt enable + \arg CAN_INT_RFO0: receive FIFO0 overfull interrupt enable + \arg CAN_INT_RFNE1: receive FIFO1 not empty interrupt enable + \arg CAN_INT_RFF1: receive FIFO1 full interrupt enable + \arg CAN_INT_RFO1: receive FIFO1 overfull interrupt enable + \arg CAN_INT_WERR: warning error interrupt enable + \arg CAN_INT_PERR: passive error interrupt enable + \arg CAN_INT_BO: bus-off interrupt enable + \arg CAN_INT_ERRN: error number interrupt enable + \arg CAN_INT_ERR: error interrupt enable + \arg CAN_INT_WU: wakeup interrupt enable + \arg CAN_INT_SLPW: sleep working interrupt enable \param[out] none \retval none */ @@ -728,24 +873,46 @@ void can_interrupt_disable(uint32_t can_periph, uint32_t interrupt) \arg CANx(x=0,1) \param[in] flag: CAN flags, refer to can_flag_enum only one parameter can be selected which is shown as below: - \arg CAN_FLAG_MTE2 - \arg CAN_FLAG_MTE1 - \arg CAN_FLAG_MTE0 - \arg CAN_FLAG_MTF2 - \arg CAN_FLAG_MTF1 - \arg CAN_FLAG_MTF0 - \arg CAN_FLAG_RFO0 - \arg CAN_FLAG_RFF0 - \arg CAN_FLAG_RFO1 - \arg CAN_FLAG_RFF1 - \arg CAN_FLAG_BOERR - \arg CAN_FLAG_PERR - \arg CAN_FLAG_WERR + \arg CAN_FLAG_RXL: RX level + \arg CAN_FLAG_LASTRX: last sample value of RX pin + \arg CAN_FLAG_RS: receiving state + \arg CAN_FLAG_TS: transmitting state + \arg CAN_FLAG_SLPIF: status change flag of entering sleep working mode + \arg CAN_FLAG_WUIF: status change flag of wakeup from sleep working mode + \arg CAN_FLAG_ERRIF: error flag + \arg CAN_FLAG_SLPWS: sleep working state + \arg CAN_FLAG_IWS: initial working state + \arg CAN_FLAG_TMLS2: transmit mailbox 2 last sending in Tx FIFO + \arg CAN_FLAG_TMLS1: transmit mailbox 1 last sending in Tx FIFO + \arg CAN_FLAG_TMLS0: transmit mailbox 0 last sending in Tx FIFO + \arg CAN_FLAG_TME2: transmit mailbox 2 empty + \arg CAN_FLAG_TME1: transmit mailbox 1 empty + \arg CAN_FLAG_TME0: transmit mailbox 0 empty + \arg CAN_FLAG_MTE2: mailbox 2 transmit error + \arg CAN_FLAG_MTE1: mailbox 1 transmit error + \arg CAN_FLAG_MTE0: mailbox 0 transmit error + \arg CAN_FLAG_MAL2: mailbox 2 arbitration lost + \arg CAN_FLAG_MAL1: mailbox 1 arbitration lost + \arg CAN_FLAG_MAL0: mailbox 0 arbitration lost + \arg CAN_FLAG_MTFNERR2: mailbox 2 transmit finished with no error + \arg CAN_FLAG_MTFNERR1: mailbox 1 transmit finished with no error + \arg CAN_FLAG_MTFNERR0: mailbox 0 transmit finished with no error + \arg CAN_FLAG_MTF2: mailbox 2 transmit finished + \arg CAN_FLAG_MTF1: mailbox 1 transmit finished + \arg CAN_FLAG_MTF0: mailbox 0 transmit finished + \arg CAN_FLAG_RFO0: receive FIFO0 overfull + \arg CAN_FLAG_RFF0: receive FIFO0 full + \arg CAN_FLAG_RFO1: receive FIFO1 overfull + \arg CAN_FLAG_RFF1: receive FIFO1 full + \arg CAN_FLAG_BOERR: bus-off error + \arg CAN_FLAG_PERR: passive error + \arg CAN_FLAG_WERR: warning error \param[out] none \retval FlagStatus: SET or RESET */ FlagStatus can_flag_get(uint32_t can_periph, can_flag_enum flag) -{ +{ + /* get flag and interrupt enable state */ if(RESET != (CAN_REG_VAL(can_periph, flag) & BIT(CAN_BIT_POS(flag)))){ return SET; }else{ @@ -755,26 +922,35 @@ FlagStatus can_flag_get(uint32_t can_periph, can_flag_enum flag) /*! \brief clear CAN flag state - \param[in] can_periph + \param[in] can_periph \arg CANx(x=0,1) \param[in] flag: CAN flags, refer to can_flag_enum only one parameter can be selected which is shown as below: - \arg CAN_FLAG_MTE2 - \arg CAN_FLAG_MTE1 - \arg CAN_FLAG_MTE0 - \arg CAN_FLAG_MTF2 - \arg CAN_FLAG_MTF1 - \arg CAN_FLAG_MTF0 - \arg CAN_FLAG_RFO0 - \arg CAN_FLAG_RFF0 - \arg CAN_FLAG_RFO1 - \arg CAN_FLAG_RFF1 + \arg CAN_FLAG_SLPIF: status change flag of entering sleep working mode + \arg CAN_FLAG_WUIF: status change flag of wakeup from sleep working mode + \arg CAN_FLAG_ERRIF: error flag + \arg CAN_FLAG_MTE2: mailbox 2 transmit error + \arg CAN_FLAG_MTE1: mailbox 1 transmit error + \arg CAN_FLAG_MTE0: mailbox 0 transmit error + \arg CAN_FLAG_MAL2: mailbox 2 arbitration lost + \arg CAN_FLAG_MAL1: mailbox 1 arbitration lost + \arg CAN_FLAG_MAL0: mailbox 0 arbitration lost + \arg CAN_FLAG_MTFNERR2: mailbox 2 transmit finished with no error + \arg CAN_FLAG_MTFNERR1: mailbox 1 transmit finished with no error + \arg CAN_FLAG_MTFNERR0: mailbox 0 transmit finished with no error + \arg CAN_FLAG_MTF2: mailbox 2 transmit finished + \arg CAN_FLAG_MTF1: mailbox 1 transmit finished + \arg CAN_FLAG_MTF0: mailbox 0 transmit finished + \arg CAN_FLAG_RFO0: receive FIFO0 overfull + \arg CAN_FLAG_RFF0: receive FIFO0 full + \arg CAN_FLAG_RFO1: receive FIFO1 overfull + \arg CAN_FLAG_RFF1: receive FIFO1 full \param[out] none \retval none */ void can_flag_clear(uint32_t can_periph, can_flag_enum flag) { - CAN_REG_VAL(can_periph, flag) |= BIT(CAN_BIT_POS(flag)); + CAN_REG_VAL(can_periph, flag) = BIT(CAN_BIT_POS(flag)); } /*! @@ -783,62 +959,43 @@ void can_flag_clear(uint32_t can_periph, can_flag_enum flag) \arg CANx(x=0,1) \param[in] flag: CAN interrupt flags, refer to can_interrupt_flag_enum only one parameter can be selected which is shown as below: - \arg CAN_INT_SLPIF - \arg CAN_INT_WUIF - \arg CAN_INT_ERRIF + \arg CAN_INT_FLAG_SLPIF: status change interrupt flag of sleep working mode entering + \arg CAN_INT_FLAG_WUIF: status change interrupt flag of wakeup from sleep working mode + \arg CAN_INT_FLAG_ERRIF: error interrupt flag + \arg CAN_INT_FLAG_MTF2: mailbox 2 transmit finished interrupt flag + \arg CAN_INT_FLAG_MTF1: mailbox 1 transmit finished interrupt flag + \arg CAN_INT_FLAG_MTF0: mailbox 0 transmit finished interrupt flag + \arg CAN_INT_FLAG_RFO0: receive FIFO0 overfull interrupt flag + \arg CAN_INT_FLAG_RFF0: receive FIFO0 full interrupt flag + \arg CAN_INT_FLAG_RFL0: receive FIFO0 not empty interrupt flag + \arg CAN_INT_FLAG_RFO1: receive FIFO1 overfull interrupt flag + \arg CAN_INT_FLAG_RFF1: receive FIFO1 full interrupt flag + \arg CAN_INT_FLAG_RFL1: receive FIFO1 not empty interrupt flag + \arg CAN_INT_FLAG_ERRN: error number interrupt flag + \arg CAN_INT_FLAG_BOERR: bus-off error interrupt flag + \arg CAN_INT_FLAG_PERR: passive error interrupt flag + \arg CAN_INT_FLAG_WERR: warning error interrupt flag \param[out] none \retval FlagStatus: SET or RESET */ FlagStatus can_interrupt_flag_get(uint32_t can_periph, can_interrupt_flag_enum flag) -{ - FlagStatus inten = RESET; - FlagStatus temp = RESET; - FlagStatus status1 = RESET; - FlagStatus status2 = RESET; - - switch(flag){ - /* get the status of sleep working interrupt enable bit */ - case CAN_INT_SLPIF: - inten = (FlagStatus)(CAN_INTEN(can_periph) & CAN_INTEN_SLPWIE); - break; - /* get the status of wakeup interrupt enable bit */ - case CAN_INT_WUIF: - inten = (FlagStatus)(CAN_INTEN(can_periph) & CAN_INTEN_WUIE); - break; - /* get the status of error falgs and its enable bit */ - case CAN_INT_ERRIF: - /* check if the BOERR bit in CAN_ERR register and BOIE bit in CAN_INTEN register are set */ - status1 = (FlagStatus)(CAN_INTEN(can_periph) & CAN_INTEN_BOIE); - status2 = (FlagStatus)(CAN_ERR(can_periph) & CAN_ERR_BOERR); - if((RESET != status1) && (RESET != status2)){ - inten = SET; - } - /* check if the WERR bit in CAN_ERR register and WERRIE bit in CAN_INTEN register are set */ - status1 = (FlagStatus)(CAN_INTEN(can_periph) & CAN_INTEN_WERRIE); - status2 = (FlagStatus)(CAN_ERR(can_periph) & CAN_ERR_WERR); - if((RESET != status1) && (RESET != status2)){ - inten = SET; - } - /* check if the PERR bit in CAN_ERR register and PERRIE bit in CAN_INTEN register are set */ - status1 = (FlagStatus)(CAN_INTEN(can_periph) & CAN_INTEN_PERRIE); - status2 = (FlagStatus)(CAN_ERR(can_periph) & CAN_ERR_PERR); - if((RESET != status1) && (RESET != status2)){ - inten = SET; - } - /* check if the ERRN bit in CAN_ERR register and ERRNIE bit in CAN_INTEN register are set */ - status1 = (FlagStatus)(CAN_INTEN(can_periph) & CAN_INTEN_ERRNIE); - status2 = (FlagStatus)(CAN_ERR(can_periph) & CAN_ERR_ERRN); - if((RESET != status1) && (RESET != status2)){ - inten = SET; - } - break; - default: - break; +{ + uint32_t ret1 = RESET; + uint32_t ret2 = RESET; + + /* get the staus of interrupt flag */ + if (flag == CAN_INT_FLAG_RFF0) { + ret1 = can_receive_message_length_get(can_periph, CAN_FIFO0); + } else if (flag == CAN_INT_FLAG_RFF1) { + ret1 = can_receive_message_length_get(can_periph, CAN_FIFO1); + } else if (flag == CAN_INT_FLAG_ERRN) { + ret1 = can_error_get(can_periph); + } else { + ret1 = CAN_REG_VALS(can_periph, flag) & BIT(CAN_BIT_POS0(flag)); } - /* get the interrupt flag */ - temp = (FlagStatus)(CAN_REG_VAL(can_periph, flag) & BIT(CAN_BIT_POS(flag))); - /* check the interrupt enable bit and corresponding flag bit are set */ - if((RESET != inten) && (RESET != temp)){ + /* get the staus of interrupt enale bit */ + ret2 = CAN_INTEN(can_periph) & BIT(CAN_BIT_POS1(flag)); + if(ret1 && ret2){ return SET; }else{ return RESET; @@ -851,13 +1008,20 @@ FlagStatus can_interrupt_flag_get(uint32_t can_periph, can_interrupt_flag_enum f \arg CANx(x=0,1) \param[in] flag: CAN interrupt flags, refer to can_interrupt_flag_enum only one parameter can be selected which is shown as below: - \arg CAN_INT_SLPIF - \arg CAN_INT_WUIF - \arg CAN_INT_ERRIF + \arg CAN_INT_FLAG_SLPIF: status change interrupt flag of sleep working mode entering + \arg CAN_INT_FLAG_WUIF: status change interrupt flag of wakeup from sleep working mode + \arg CAN_INT_FLAG_ERRIF: error interrupt flag + \arg CAN_INT_FLAG_MTF2: mailbox 2 transmit finished interrupt flag + \arg CAN_INT_FLAG_MTF1: mailbox 1 transmit finished interrupt flag + \arg CAN_INT_FLAG_MTF0: mailbox 0 transmit finished interrupt flag + \arg CAN_INT_FLAG_RFO0: receive FIFO0 overfull interrupt flag + \arg CAN_INT_FLAG_RFF0: receive FIFO0 full interrupt flag + \arg CAN_INT_FLAG_RFO1: receive FIFO1 overfull interrupt flag + \arg CAN_INT_FLAG_RFF1: receive FIFO1 full interrupt flag \param[out] none \retval none */ void can_interrupt_flag_clear(uint32_t can_periph, can_interrupt_flag_enum flag) { - CAN_REG_VAL(can_periph, flag) |= BIT(CAN_BIT_POS(flag)); + CAN_REG_VALS(can_periph, flag) = BIT(CAN_BIT_POS0(flag)); } diff --git a/bsp/gd32450z-eval/Libraries/GD32F4xx_standard_peripheral/Source/gd32f4xx_crc.c b/bsp/gd32450z-eval/Libraries/GD32F4xx_standard_peripheral/Source/gd32f4xx_crc.c index e51d8dc483..bfe79cb9aa 100644 --- a/bsp/gd32450z-eval/Libraries/GD32F4xx_standard_peripheral/Source/gd32f4xx_crc.c +++ b/bsp/gd32450z-eval/Libraries/GD32F4xx_standard_peripheral/Source/gd32f4xx_crc.c @@ -1,16 +1,43 @@ /*! - \file gd32f4xx_crc.c - \brief CRC driver + \file gd32f4xx_crc.c + \brief CRC driver + + \version 2016-08-15, V1.0.0, firmware for GD32F4xx + \version 2018-12-12, V2.0.0, firmware for GD32F4xx + \version 2020-09-30, V2.1.0, firmware for GD32F4xx */ /* - Copyright (C) 2016 GigaDevice + Copyright (c) 2020, GigaDevice Semiconductor Inc. + + Redistribution and use in source and binary forms, with or without modification, +are permitted provided that the following conditions are met: + + 1. Redistributions of source code must retain the above copyright notice, this + list of conditions and the following disclaimer. + 2. Redistributions in binary form must reproduce the above copyright notice, + this list of conditions and the following disclaimer in the documentation + and/or other materials provided with the distribution. + 3. Neither the name of the copyright holder nor the names of its contributors + may be used to endorse or promote products derived from this software without + specific prior written permission. - 2016-08-15, V1.0.0, firmware for GD32F4xx + THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED +WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. +IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, +INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT +NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR +PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, +WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY +OF SUCH DAMAGE. */ #include "gd32f4xx_crc.h" +#define CRC_DATA_RESET_VALUE ((uint32_t)0xFFFFFFFFU) +#define CRC_FDATA_RESET_VALUE ((uint32_t)0x00000000U) /*! \brief deinit CRC calculation unit \param[in] none @@ -19,13 +46,13 @@ */ void crc_deinit(void) { - CRC_DATA = (uint32_t)0xFFFFFFFFU; - CRC_FDATA = (uint32_t)0x00000000U; - CRC_CTL = CRC_CTL_RST; + CRC_DATA = CRC_DATA_RESET_VALUE; + CRC_FDATA = CRC_FDATA_RESET_VALUE; + CRC_CTL = (uint32_t)CRC_CTL_RST; } /*! - \brief reset data register to the value of initializaiton data register + \brief reset data register(CRC_DATA) to the value of 0xFFFFFFFF \param[in] none \param[out] none \retval none @@ -36,7 +63,7 @@ void crc_data_register_reset(void) } /*! - \brief read the data register + \brief read the value of the data register \param[in] none \param[out] none \retval 32-bit value of the data register @@ -49,7 +76,7 @@ uint32_t crc_data_register_read(void) } /*! - \brief read the free data register + \brief read the value of the free data register \param[in] none \param[out] none \retval 8-bit value of the free data register @@ -62,8 +89,8 @@ uint8_t crc_free_data_register_read(void) } /*! - \brief write the free data register - \param[in] free_data: specify 8-bit data + \brief write data to the free data register + \param[in] free_data: specified 8-bit data \param[out] none \retval none */ @@ -73,10 +100,10 @@ void crc_free_data_register_write(uint8_t free_data) } /*! - \brief CRC calculate a 32-bit data - \param[in] sdata: specify 32-bit data + \brief calculate the CRC value of a 32-bit data + \param[in] sdata: specified 32-bit data \param[out] none - \retval 32-bit CRC calculate value + \retval 32-bit value calculated by CRC */ uint32_t crc_single_data_calculate(uint32_t sdata) { @@ -85,11 +112,11 @@ uint32_t crc_single_data_calculate(uint32_t sdata) } /*! - \brief CRC calculate a 32-bit data array - \param[in] array: pointer to an array of 32 bit data words + \brief calculate the CRC value of an array of 32-bit values + \param[in] array: pointer to an array of 32-bit values \param[in] size: size of the array \param[out] none - \retval 32-bit CRC calculate value + \retval 32-bit value calculated by CRC */ uint32_t crc_block_data_calculate(uint32_t array[], uint32_t size) { diff --git a/bsp/gd32450z-eval/Libraries/GD32F4xx_standard_peripheral/Source/gd32f4xx_ctc.c b/bsp/gd32450z-eval/Libraries/GD32F4xx_standard_peripheral/Source/gd32f4xx_ctc.c index 34431164a3..ab67c4ad73 100644 --- a/bsp/gd32450z-eval/Libraries/GD32F4xx_standard_peripheral/Source/gd32f4xx_ctc.c +++ b/bsp/gd32450z-eval/Libraries/GD32F4xx_standard_peripheral/Source/gd32f4xx_ctc.c @@ -1,18 +1,49 @@ /*! - \file gd32f4xx_ctc.c - \brief CTC driver + \file gd32f4xx_ctc.c + \brief CTC driver + + \version 2016-08-15, V1.0.0, firmware for GD32F4xx + \version 2018-12-12, V2.0.0, firmware for GD32F4xx + \version 2020-09-30, V2.1.0, firmware for GD32F4xx */ /* - Copyright (C) 2016 GigaDevice + Copyright (c) 2020, GigaDevice Semiconductor Inc. + + Redistribution and use in source and binary forms, with or without modification, +are permitted provided that the following conditions are met: + + 1. Redistributions of source code must retain the above copyright notice, this + list of conditions and the following disclaimer. + 2. Redistributions in binary form must reproduce the above copyright notice, + this list of conditions and the following disclaimer in the documentation + and/or other materials provided with the distribution. + 3. Neither the name of the copyright holder nor the names of its contributors + may be used to endorse or promote products derived from this software without + specific prior written permission. - 2016-08-15, V1.0.0, firmware for GD32F4xx + THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED +WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. +IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, +INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT +NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR +PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, +WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY +OF SUCH DAMAGE. */ #include "gd32f4xx_ctc.h" #define CTC_FLAG_MASK ((uint32_t)0x00000700U) +/* CTC register bit offset */ +#define CTC_TRIMVALUE_OFFSET ((uint32_t)8U) +#define CTC_TRIM_VALUE_OFFSET ((uint32_t)8U) +#define CTC_REFCAP_OFFSET ((uint32_t)16U) +#define CTC_LIMIT_VALUE_OFFSET ((uint32_t)16U) + /*! \brief reset CTC clock trim controller \param[in] none @@ -27,112 +58,117 @@ void ctc_deinit(void) } /*! - \brief configure the IRC48M trim value - \param[in] ctc_trim_value: 8-bit IRC48M trim value + \brief enable CTC trim counter + \param[in] none \param[out] none \retval none */ -void ctc_irc48m_trim_value_config(uint8_t ctc_trim_value) +void ctc_counter_enable(void) { - /* clear TRIMVALUE bits */ - CTC_CTL0 &= (~(uint32_t)CTC_CTL0_TRIMVALUE); - /* set TRIMVALUE bits */ - CTC_CTL0 |= ((uint32_t)ctc_trim_value << 8); + CTC_CTL0 |= (uint32_t)CTC_CTL0_CNTEN; } /*! - \brief generate software reference source sync pulse + \brief disable CTC trim counter \param[in] none \param[out] none \retval none */ -void ctc_software_refsource_pulse_generate(void) +void ctc_counter_disable(void) { - CTC_CTL0 |= (uint32_t)CTC_CTL0_SWREFPUL; + CTC_CTL0 &= (uint32_t)(~CTC_CTL0_CNTEN); } /*! - \brief configure hardware automatically trim mode - \param[in] ctc_hardmode: - \arg CTC_HARDWARE_TRIM_MODE_ENABLE: hardware automatically trim mode enable - \arg CTC_HARDWARE_TRIM_MODE_DISABLE: hardware automatically trim mode disable + \brief configure the IRC48M trim value + \param[in] ctc_trim_value: 8-bit IRC48M trim value + \arg 0x00 - 0x3F \param[out] none \retval none */ -void ctc_hardware_trim_mode_config(uint32_t ctc_hardmode) +void ctc_irc48m_trim_value_config(uint8_t trim_value) { - CTC_CTL0 &= (uint32_t)(~CTC_CTL0_AUTOTRIM); - CTC_CTL0 |= (uint32_t)ctc_hardmode; + /* clear TRIMVALUE bits */ + CTC_CTL0 &= (~(uint32_t)CTC_CTL0_TRIMVALUE); + /* set TRIMVALUE bits */ + CTC_CTL0 |= ((uint32_t)trim_value << CTC_TRIM_VALUE_OFFSET); } /*! - \brief enable CTC counter + \brief generate software reference source sync pulse \param[in] none \param[out] none \retval none */ -void ctc_counter_enable(void) +void ctc_software_refsource_pulse_generate(void) { - CTC_CTL0 |= (uint32_t)CTC_CTL0_CNTEN; + CTC_CTL0 |= (uint32_t)CTC_CTL0_SWREFPUL; } /*! - \brief disable CTC counter - \param[in] none + \brief configure hardware automatically trim mode + \param[in] hardmode: + only one parameter can be selected which is shown as below: + \arg CTC_HARDWARE_TRIM_MODE_ENABLE: hardware automatically trim mode enable + \arg CTC_HARDWARE_TRIM_MODE_DISABLE: hardware automatically trim mode disable \param[out] none \retval none */ -void ctc_counter_disable(void) +void ctc_hardware_trim_mode_config(uint32_t hardmode) { - CTC_CTL0 &= (uint32_t)(~CTC_CTL0_CNTEN); + CTC_CTL0 &= (uint32_t)(~CTC_CTL0_AUTOTRIM); + CTC_CTL0 |= (uint32_t)hardmode; } /*! \brief configure reference signal source polarity - \param[in] ctc_polarity: + \param[in] polarity: + only one parameter can be selected which is shown as below: \arg CTC_REFSOURCE_POLARITY_FALLING: reference signal source polarity is falling edge \arg CTC_REFSOURCE_POLARITY_RISING: reference signal source polarity is rising edge \param[out] none \retval none */ -void ctc_refsource_polarity_config(uint32_t ctc_polarity) +void ctc_refsource_polarity_config(uint32_t polarity) { CTC_CTL1 &= (uint32_t)(~CTC_CTL1_REFPOL); - CTC_CTL1 |= (uint32_t)ctc_polarity; + CTC_CTL1 |= (uint32_t)polarity; } /*! \brief select USBFS or USBHS SOF signal - \param[in] ctc_usbsof: + \param[in] usbsof: \arg CTC_USBSOFSEL_USBHS: USBHS SOF signal is selected \arg CTC_USBSOFSEL_USBFS: USBFS SOF signal is selected \param[out] none \retval none */ -void ctc_usbsof_signal_select(uint32_t ctc_usbsof) +void ctc_usbsof_signal_select(uint32_t usbsof) { CTC_CTL1 &= (uint32_t)(~CTC_CTL1_USBSOFSEL); - CTC_CTL1 |= (uint32_t)ctc_usbsof; + CTC_CTL1 |= (uint32_t)usbsof; } /*! \brief select reference signal source - \param[in] ctc_refs: + \param[in] refs: + only one parameter can be selected which is shown as below: \arg CTC_REFSOURCE_GPIO: GPIO is selected - \arg CTC_REFSOURCE_LXTAL: LXTAL is clock selected + \arg CTC_REFSOURCE_LXTAL: LXTAL is selected \arg CTC_REFSOURCE_USBSOF: USBSOF is selected \param[out] none \retval none */ -void ctc_refsource_signal_select(uint32_t ctc_refs) +void ctc_refsource_signal_select(uint32_t refs) { CTC_CTL1 &= (uint32_t)(~CTC_CTL1_REFSEL); - CTC_CTL1 |= (uint32_t)ctc_refs; + CTC_CTL1 |= (uint32_t)refs; } /*! \brief configure reference signal source prescaler - \param[in] ctc_prescaler: + \param[in] prescaler: + only one parameter can be selected which is shown as below: \arg CTC_REFSOURCE_PSC_OFF: reference signal not divided \arg CTC_REFSOURCE_PSC_DIV2: reference signal divided by 2 \arg CTC_REFSOURCE_PSC_DIV4: reference signal divided by 4 @@ -144,34 +180,36 @@ void ctc_refsource_signal_select(uint32_t ctc_refs) \param[out] none \retval none */ -void ctc_refsource_prescaler_config(uint32_t ctc_prescaler) +void ctc_refsource_prescaler_config(uint32_t prescaler) { CTC_CTL1 &= (uint32_t)(~CTC_CTL1_REFPSC); - CTC_CTL1 |= (uint32_t)ctc_prescaler; + CTC_CTL1 |= (uint32_t)prescaler; } /*! \brief configure clock trim base limit value - \param[in] ctc_limit_value: 8-bit clock trim base limit value + \param[in] limit_value: 8-bit clock trim base limit value + \arg 0x00 - 0xFF \param[out] none \retval none */ -void ctc_clock_limit_value_config(uint8_t ctc_limit_value) +void ctc_clock_limit_value_config(uint8_t limit_value) { CTC_CTL1 &= (uint32_t)(~CTC_CTL1_CKLIM); - CTC_CTL1 |= (uint32_t)((uint32_t)ctc_limit_value << 16); + CTC_CTL1 |= (uint32_t)((uint32_t)limit_value << CTC_LIMIT_VALUE_OFFSET); } /*! \brief configure CTC counter reload value - \param[in] ctc_reload_value: 16-bit CTC counter reload value + \param[in] reload_value: 16-bit CTC counter reload value + \arg 0x0000 - 0xFFFF \param[out] none \retval none */ -void ctc_counter_reload_value_config(uint16_t ctc_reload_value) +void ctc_counter_reload_value_config(uint16_t reload_value) { CTC_CTL1 &= (uint32_t)(~CTC_CTL1_RLVALUE); - CTC_CTL1 |= (uint32_t)ctc_reload_value; + CTC_CTL1 |= (uint32_t)reload_value; } /*! @@ -183,7 +221,7 @@ void ctc_counter_reload_value_config(uint16_t ctc_reload_value) uint16_t ctc_counter_capture_value_read(void) { uint16_t capture_value = 0U; - capture_value = (uint16_t)((CTC_STAT & CTC_STAT_REFCAP)>> 16); + capture_value = (uint16_t)((CTC_STAT & CTC_STAT_REFCAP)>> CTC_REFCAP_OFFSET); return (capture_value); } @@ -226,65 +264,71 @@ uint16_t ctc_counter_reload_value_read(void) uint8_t ctc_irc48m_trim_value_read(void) { uint8_t trim_value = 0U; - trim_value = (uint8_t)((CTC_CTL0 & CTC_CTL0_TRIMVALUE) >> 8); + trim_value = (uint8_t)((CTC_CTL0 & CTC_CTL0_TRIMVALUE) >> CTC_TRIMVALUE_OFFSET); return (trim_value); } /*! \brief enable the CTC interrupt - \param[in] ctc_interrupt: CTC interrupt enable - \arg CTC_INT_CKOKIE: clock trim OK interrupt enable - \arg CTC_INT_CKWARNIE: clock trim warning interrupt enable - \arg CTC_INT_ERRIE: error interrupt enable - \arg CTC_INT_EREFIE: expect reference interrupt enable + \param[in] interrupt: CTC interrupt enable + one or more parameters can be selected which are shown as below: + \arg CTC_INT_CKOK: clock trim OK interrupt enable + \arg CTC_INT_CKWARN: clock trim warning interrupt enable + \arg CTC_INT_ERR: error interrupt enable + \arg CTC_INT_EREF: expect reference interrupt enable \param[out] none \retval none */ -void ctc_interrupt_enable(uint32_t ctc_interrupt) +void ctc_interrupt_enable(uint32_t interrupt) { - CTC_CTL0 |= (uint32_t)ctc_interrupt; + CTC_CTL0 |= (uint32_t)interrupt; } /*! \brief disable the CTC interrupt - \param[in] ctc_interrupt: CTC interrupt enable source - \arg CTC_INT_CKOKIE: clock trim OK interrupt enable - \arg CTC_INT_CKWARNIE: clock trim warning interrupt enable - \arg CTC_INT_ERRIE: error interrupt enable - \arg CTC_INT_EREFIE: expect reference interrupt enable + \param[in] interrupt: CTC interrupt enable source + one or more parameters can be selected which are shown as below: + \arg CTC_INT_CKOK: clock trim OK interrupt enable + \arg CTC_INT_CKWARN: clock trim warning interrupt enable + \arg CTC_INT_ERR: error interrupt enable + \arg CTC_INT_EREF: expect reference interrupt enable \param[out] none \retval none */ -void ctc_interrupt_disable(uint32_t ctc_interrupt) +void ctc_interrupt_disable(uint32_t interrupt) { - CTC_CTL0 &= (uint32_t)(~ctc_interrupt); + CTC_CTL0 &= (uint32_t)(~interrupt); } /*! \brief get CTC interrupt flag - \param[in] ctc_interrupt: the CTC interrupt flag - \arg CTC_INT_CKOK: clock trim OK interrupt - \arg CTC_INT_CKWARN: clock trim warning interrupt - \arg CTC_INT_ERR: error interrupt - \arg CTC_INT_EREF: expect reference interrupt - \arg CTC_INT_CKERR: clock trim error bit interrupt - \arg CTC_INT_REFMISS: reference sync pulse miss interrupt - \arg CTC_INT_TRIMERR: trim value error interrupt + \param[in] int_flag: the CTC interrupt flag + only one parameter can be selected which is shown as below: + \arg CTC_INT_FLAG_CKOK: clock trim OK interrupt + \arg CTC_INT_FLAG_CKWARN: clock trim warning interrupt + \arg CTC_INT_FLAG_ERR: error interrupt + \arg CTC_INT_FLAG_EREF: expect reference interrupt + \arg CTC_INT_FLAG_CKERR: clock trim error bit interrupt + \arg CTC_INT_FLAG_REFMISS: reference sync pulse miss interrupt + \arg CTC_INT_FLAG_TRIMERR: trim value error interrupt \param[out] none \retval FlagStatus: SET or RESET */ -FlagStatus ctc_interrupt_flag_get(uint32_t ctc_interrupt) +FlagStatus ctc_interrupt_flag_get(uint32_t int_flag) { - uint32_t interrupt = 0U, intenable = 0U; + uint32_t interrupt_flag = 0U, intenable = 0U; - if(ctc_interrupt & CTC_FLAG_MASK){ - intenable = CTC_CTL0 & CTC_INT_ERRIE; + /* check whether the interrupt is enabled */ + if(RESET != (int_flag & CTC_FLAG_MASK)){ + intenable = CTC_CTL0 & CTC_CTL0_ERRIE; }else{ - intenable = CTC_CTL0 & ctc_interrupt; + intenable = CTC_CTL0 & int_flag; } - interrupt = CTC_STAT & ctc_interrupt; - if(interrupt && intenable){ + /* get interrupt flag status */ + interrupt_flag = CTC_STAT & int_flag; + + if(interrupt_flag && intenable){ return SET; }else{ return RESET; @@ -293,32 +337,34 @@ FlagStatus ctc_interrupt_flag_get(uint32_t ctc_interrupt) /*! \brief clear CTC interrupt flag - \param[in] ctc_interrupt: the CTC interrupt flag - \arg CTC_INT_CKOK: clock trim OK interrupt - \arg CTC_INT_CKWARN: clock trim warning interrupt - \arg CTC_INT_ERR: error interrupt - \arg CTC_INT_EREF: expect reference interrupt - \arg CTC_INT_CKERR: clock trim error bit interrupt - \arg CTC_INT_REFMISS: reference sync pulse miss interrupt - \arg CTC_INT_TRIMERR: trim value error interrupt + \param[in] int_flag: the CTC interrupt flag + only one parameter can be selected which is shown as below: + \arg CTC_INT_FLAG_CKOK: clock trim OK interrupt + \arg CTC_INT_FLAG_CKWARN: clock trim warning interrupt + \arg CTC_INT_FLAG_ERR: error interrupt + \arg CTC_INT_FLAG_EREF: expect reference interrupt + \arg CTC_INT_FLAG_CKERR: clock trim error bit interrupt + \arg CTC_INT_FLAG_REFMISS: reference sync pulse miss interrupt + \arg CTC_INT_FLAG_TRIMERR: trim value error interrupt \param[out] none \retval none -*/ -void ctc_interrupt_flag_clear(uint32_t ctc_interrupt) +*/ +void ctc_interrupt_flag_clear(uint32_t int_flag) { - if(ctc_interrupt & CTC_FLAG_MASK){ + if(RESET != (int_flag & CTC_FLAG_MASK)){ CTC_INTC |= CTC_INTC_ERRIC; }else{ - CTC_INTC |= ctc_interrupt; + CTC_INTC |= int_flag; } } /*! \brief get CTC flag - \param[in] ctc_flag: the CTC flag + \param[in] flag: the CTC flag + only one parameter can be selected which is shown as below: \arg CTC_FLAG_CKOK: clock trim OK flag - \arg CTC_FLAG_CKWARN: clock trim warning flag - \arg CTC_FLAG_ERR: error flag + \arg CTC_FLAG_CKWARN: clock trim warning flag + \arg CTC_FLAG_ERR: error flag \arg CTC_FLAG_EREF: expect reference flag \arg CTC_FLAG_CKERR: clock trim error bit \arg CTC_FLAG_REFMISS: reference sync pulse miss @@ -326,9 +372,9 @@ void ctc_interrupt_flag_clear(uint32_t ctc_interrupt) \param[out] none \retval FlagStatus: SET or RESET */ -FlagStatus ctc_flag_get(uint32_t ctc_flag) +FlagStatus ctc_flag_get(uint32_t flag) { - if(RESET != (CTC_STAT & ctc_flag)){ + if(RESET != (CTC_STAT & flag)){ return SET; }else{ return RESET; @@ -337,10 +383,11 @@ FlagStatus ctc_flag_get(uint32_t ctc_flag) /*! \brief clear CTC flag - \param[in] ctc_flag: the CTC flag + \param[in] flag: the CTC flag + only one parameter can be selected which is shown as below: \arg CTC_FLAG_CKOK: clock trim OK flag - \arg CTC_FLAG_CKWARN: clock trim warning flag - \arg CTC_FLAG_ERR: error flag + \arg CTC_FLAG_CKWARN: clock trim warning flag + \arg CTC_FLAG_ERR: error flag \arg CTC_FLAG_EREF: expect reference flag \arg CTC_FLAG_CKERR: clock trim error bit \arg CTC_FLAG_REFMISS: reference sync pulse miss @@ -348,11 +395,11 @@ FlagStatus ctc_flag_get(uint32_t ctc_flag) \param[out] none \retval none */ -void ctc_flag_clear(uint32_t ctc_flag) +void ctc_flag_clear(uint32_t flag) { - if(ctc_flag & CTC_FLAG_MASK){ + if(RESET != (flag & CTC_FLAG_MASK)){ CTC_INTC |= CTC_INTC_ERRIC; }else{ - CTC_INTC |= ctc_flag; + CTC_INTC |= flag; } } diff --git a/bsp/gd32450z-eval/Libraries/GD32F4xx_standard_peripheral/Source/gd32f4xx_dac.c b/bsp/gd32450z-eval/Libraries/GD32F4xx_standard_peripheral/Source/gd32f4xx_dac.c index 2204d08c21..3a5dd52cdd 100644 --- a/bsp/gd32450z-eval/Libraries/GD32F4xx_standard_peripheral/Source/gd32f4xx_dac.c +++ b/bsp/gd32450z-eval/Libraries/GD32F4xx_standard_peripheral/Source/gd32f4xx_dac.c @@ -1,16 +1,46 @@ /*! - \file gd32f4xx_dac.c - \brief DAC driver + \file gd32f4xx_dac.c + \brief DAC driver + + \version 2016-08-15, V1.0.0, firmware for GD32F4xx + \version 2018-12-12, V2.0.0, firmware for GD32F4xx + \version 2020-09-30, V2.1.0, firmware for GD32F4xx */ /* - Copyright (C) 2016 GigaDevice + Copyright (c) 2020, GigaDevice Semiconductor Inc. + + Redistribution and use in source and binary forms, with or without modification, +are permitted provided that the following conditions are met: - 2016-08-15, V1.0.0, firmware for GD32F4xx + 1. Redistributions of source code must retain the above copyright notice, this + list of conditions and the following disclaimer. + 2. Redistributions in binary form must reproduce the above copyright notice, + this list of conditions and the following disclaimer in the documentation + and/or other materials provided with the distribution. + 3. Neither the name of the copyright holder nor the names of its contributors + may be used to endorse or promote products derived from this software without + specific prior written permission. + + THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED +WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. +IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, +INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT +NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR +PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, +WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY +OF SUCH DAMAGE. */ #include "gd32f4xx_dac.h" +/* DAC register bit offset */ +#define DAC1_REG_OFFSET ((uint32_t)16U) +#define DH_12BIT_OFFSET ((uint32_t)16U) +#define DH_8BIT_OFFSET ((uint32_t)8U) + /*! \brief deinitialize DAC \param[in] none @@ -25,8 +55,7 @@ void dac_deinit(void) /*! \brief enable DAC - \param[in] dac_periph - \arg DACx(x =0,1) + \param[in] dac_periph: DACx(x = 0,1) \param[out] none \retval none */ @@ -37,12 +66,11 @@ void dac_enable(uint32_t dac_periph) }else{ DAC_CTL |= DAC_CTL_DEN1; } -} +} /*! \brief disable DAC - \param[in] dac_periph - \arg DACx(x =0,1) + \param[in] dac_periph: DACx(x = 0,1) \param[out] none \retval none */ @@ -57,8 +85,7 @@ void dac_disable(uint32_t dac_periph) /*! \brief enable DAC DMA function - \param[in] dac_periph - \arg DACx(x=0,1) + \param[in] dac_periph: DACx(x = 0,1) \param[out] none \retval none */ @@ -73,8 +100,7 @@ void dac_dma_enable(uint32_t dac_periph) /*! \brief disable DAC DMA function - \param[in] dac_periph - \arg DACx(x=0,1) + \param[in] dac_periph: DACx(x = 0,1) \param[out] none \retval none */ @@ -89,8 +115,7 @@ void dac_dma_disable(uint32_t dac_periph) /*! \brief enable DAC output buffer - \param[in] dac_periph - \arg DACx(x =0,1) + \param[in] dac_periph: DACx(x = 0,1) \param[out] none \retval none */ @@ -105,8 +130,7 @@ void dac_output_buffer_enable(uint32_t dac_periph) /*! \brief disable DAC output buffer - \param[in] dac_periph - \arg DACx(x =0,1) + \param[in] dac_periph: DACx(x = 0,1) \param[out] none \retval none */ @@ -120,132 +144,168 @@ void dac_output_buffer_disable(uint32_t dac_periph) } /*! - \brief enable DAC trigger - \param[in] dac_periph - \arg DACx(x =0,1) + \brief get DAC output value + \param[in] dac_periph: DACx(x = 0,1) \param[out] none - \retval none + \retval DAC output data */ -void dac_trigger_enable(uint32_t dac_periph) +uint16_t dac_output_value_get(uint32_t dac_periph) { + uint16_t data = 0U; if(DAC0 == dac_periph){ - DAC_CTL |= DAC_CTL_DTEN0; + /* store the DAC0 output value */ + data = (uint16_t)DAC0_DO; }else{ - DAC_CTL |= DAC_CTL_DTEN1; + /* store the DAC1 output value */ + data = (uint16_t)DAC1_DO; } + return data; } /*! - \brief disable DAC trigger - \param[in] dac_periph - \arg DACx(x =0,1) + \brief set the DAC specified data holding register value + \param[in] dac_periph: DACx(x = 0,1) + \param[in] dac_align: data alignment + only one parameter can be selected which is shown as below: + \arg DAC_ALIGN_8B_R: data right 8 bit alignment + \arg DAC_ALIGN_12B_R: data right 12 bit alignment + \arg DAC_ALIGN_12B_L: data left 12 bit alignment + \param[in] data: data to be loaded \param[out] none \retval none */ -void dac_trigger_disable(uint32_t dac_periph) +void dac_data_set(uint32_t dac_periph, uint32_t dac_align, uint16_t data) { if(DAC0 == dac_periph){ - DAC_CTL &= ~DAC_CTL_DTEN0; + switch(dac_align){ + /* data right 12 bit alignment */ + case DAC_ALIGN_12B_R: + DAC0_R12DH = data; + break; + /* data left 12 bit alignment */ + case DAC_ALIGN_12B_L: + DAC0_L12DH = data; + break; + /* data right 8 bit alignment */ + case DAC_ALIGN_8B_R: + DAC0_R8DH = data; + break; + default: + break; + } }else{ - DAC_CTL &= ~DAC_CTL_DTEN1; + switch(dac_align){ + /* data right 12 bit alignment */ + case DAC_ALIGN_12B_R: + DAC1_R12DH = data; + break; + /* data left 12 bit alignment */ + case DAC_ALIGN_12B_L: + DAC1_L12DH = data; + break; + /* data right 8 bit alignment */ + case DAC_ALIGN_8B_R: + DAC1_R8DH = data; + break; + default: + break; + } } } /*! - \brief enable DAC software trigger - \param[in] dac_periph - \arg DACx(x =0,1) + \brief enable DAC trigger + \param[in] dac_periph: DACx(x = 0,1) + \param[out] none \retval none */ -void dac_software_trigger_enable(uint32_t dac_periph) +void dac_trigger_enable(uint32_t dac_periph) { if(DAC0 == dac_periph){ - DAC_SWT |= DAC_SWT_SWTR0; + DAC_CTL |= DAC_CTL_DTEN0; }else{ - DAC_SWT |= DAC_SWT_SWTR1; + DAC_CTL |= DAC_CTL_DTEN1; } } /*! - \brief disable DAC software trigger - \param[in] dac_periph - \arg DACx(x =0,1) + \brief disable DAC trigger + \param[in] dac_periph: DACx(x = 0,1) \param[out] none \retval none */ -void dac_software_trigger_disable(uint32_t dac_periph) +void dac_trigger_disable(uint32_t dac_periph) { if(DAC0 == dac_periph){ - DAC_SWT &= ~DAC_SWT_SWTR0; + DAC_CTL &= ~DAC_CTL_DTEN0; }else{ - DAC_SWT &= ~DAC_SWT_SWTR1; + DAC_CTL &= ~DAC_CTL_DTEN1; } } /*! - \brief enable DAC interrupt(DAC0 DMA underrun interrupt) - \param[in] dac_periph - \arg DACx(x=0,1) + \brief set DAC trigger source + \param[in] dac_periph: DACx(x = 0,1) + \param[in] triggersource: external triggers of DAC + only one parameter can be selected which is shown as below: + \arg DAC_TRIGGER_T1_TRGO: TIMER1 TRGO + \arg DAC_TRIGGER_T3_TRGO: TIMER3 TRGO + \arg DAC_TRIGGER_T4_TRGO: TIMER4 TRGO + \arg DAC_TRIGGER_T5_TRGO: TIMER5 TRGO + \arg DAC_TRIGGER_T6_TRGO: TIMER6 TRGO + \arg DAC_TRIGGER_T7_TRGO: TIMER7 TRGO + \arg DAC_TRIGGER_EXTI_9: EXTI interrupt line9 event + \arg DAC_TRIGGER_SOFTWARE: software trigger \param[out] none \retval none */ -void dac_interrupt_enable(uint32_t dac_periph) +void dac_trigger_source_config(uint32_t dac_periph,uint32_t triggersource) { if(DAC0 == dac_periph){ - DAC_CTL |= DAC_CTL_DDUDRIE0; + /* configure DAC0 trigger source */ + DAC_CTL &= ~DAC_CTL_DTSEL0; + DAC_CTL |= triggersource; }else{ - DAC_CTL |= DAC_CTL_DDUDRIE1; + /* configure DAC1 trigger source */ + DAC_CTL &= ~DAC_CTL_DTSEL1; + DAC_CTL |= (triggersource << DAC1_REG_OFFSET); } } /*! - \brief disable DAC interrupt(DAC0 DMA underrun interrupt) - \param[in] dac_periph - \arg DACx(x=0,1) - \param[out] none + \brief enable DAC software trigger + \param[in] dac_periph: DACx(x = 0,1) \retval none */ -void dac_interrupt_disable(uint32_t dac_periph) +void dac_software_trigger_enable(uint32_t dac_periph) { if(DAC0 == dac_periph){ - DAC_CTL &= ~DAC_CTL_DDUDRIE0; + DAC_SWT |= DAC_SWT_SWTR0; }else{ - DAC_CTL &= ~DAC_CTL_DDUDRIE1; + DAC_SWT |= DAC_SWT_SWTR1; } } /*! - \brief set DAC trigger source - \param[in] dac_periph - \arg DACx(x =0,1) - \param[in] triggersource: external triggers of DAC - \arg DAC_TRIGGER_T1_TRGO: TIMER1 TRGO - \arg DAC_TRIGGER_T3_TRGO: TIMER3 TRGO - \arg DAC_TRIGGER_T4_TRGO: TIMER4 TRGO - \arg DAC_TRIGGER_T5_TRGO: TIMER5 TRGO - \arg DAC_TRIGGER_T6_TRGO: TIMER6 TRGO - \arg DAC_TRIGGER_T7_TRGO: TIMER7 TRGO - \arg DAC_TRIGGER_EXTI_9: EXTI interrupt line9 event - \arg DAC_TRIGGER_SOFTWARE: software trigger + \brief disable DAC software trigger + \param[in] dac_periph: DACx(x = 0,1) \param[out] none \retval none */ -void dac_trigger_source_config(uint32_t dac_periph,uint32_t triggersource) +void dac_software_trigger_disable(uint32_t dac_periph) { if(DAC0 == dac_periph){ - DAC_CTL &= ~DAC_CTL_DTSEL0; - DAC_CTL |= triggersource; + DAC_SWT &= ~DAC_SWT_SWTR0; }else{ - DAC_CTL &= ~DAC_CTL_DTSEL1; - DAC_CTL |= (triggersource << 16); + DAC_SWT &= ~DAC_SWT_SWTR1; } } /*! \brief configure DAC wave mode - \param[in] dac_periph - \arg DACx(x=0,1) - \param[in] wave_mode + \param[in] dac_periph: DACx(x = 0,1) + \param[in] wave_mode: noise wave mode + only one parameter can be selected which is shown as below: \arg DAC_WAVE_DISABLE: wave disable \arg DAC_WAVE_MODE_LFSR: LFSR noise mode \arg DAC_WAVE_MODE_TRIANGLE: triangle noise mode @@ -255,19 +315,21 @@ void dac_trigger_source_config(uint32_t dac_periph,uint32_t triggersource) void dac_wave_mode_config(uint32_t dac_periph, uint32_t wave_mode) { if(DAC0 == dac_periph){ + /* configure DAC0 wave mode */ DAC_CTL &= ~DAC_CTL_DWM0; DAC_CTL |= wave_mode; }else{ + /* configure DAC1 wave mode */ DAC_CTL &= ~DAC_CTL_DWM1; - DAC_CTL |= wave_mode << 16; + DAC_CTL |= (wave_mode << DAC1_REG_OFFSET); } } /*! \brief configure DAC wave bit width - \param[in] dac_periph - \arg DACx(x=0,1) - \param[in] bit_width + \param[in] dac_periph: DACx(x = 0,1) + \param[in] bit_width: noise wave bit width + only one parameter can be selected which is shown as below: \arg DAC_WAVE_BIT_WIDTH_1: bit width of the wave signal is 1 \arg DAC_WAVE_BIT_WIDTH_2: bit width of the wave signal is 2 \arg DAC_WAVE_BIT_WIDTH_3: bit width of the wave signal is 3 @@ -286,19 +348,21 @@ void dac_wave_mode_config(uint32_t dac_periph, uint32_t wave_mode) void dac_wave_bit_width_config(uint32_t dac_periph, uint32_t bit_width) { if(DAC0 == dac_periph){ + /* configure DAC0 wave bit width */ DAC_CTL &= ~DAC_CTL_DWBW0; DAC_CTL |= bit_width; }else{ + /* configure DAC1 wave bit width */ DAC_CTL &= ~DAC_CTL_DWBW1; - DAC_CTL |= bit_width << 16; + DAC_CTL |= (bit_width << DAC1_REG_OFFSET); } } /*! \brief configure DAC LFSR noise mode - \param[in] dac_periph - \arg DACx(x=0,1) - \param[in] unmask_bits + \param[in] dac_periph: DACx(x = 0,1) + \param[in] unmask_bits: unmask LFSR bits in DAC LFSR noise mode + only one parameter can be selected which is shown as below: \arg DAC_LFSR_BIT0: unmask the LFSR bit0 \arg DAC_LFSR_BITS1_0: unmask the LFSR bits[1:0] \arg DAC_LFSR_BITS2_0: unmask the LFSR bits[2:0] @@ -317,19 +381,21 @@ void dac_wave_bit_width_config(uint32_t dac_periph, uint32_t bit_width) void dac_lfsr_noise_config(uint32_t dac_periph, uint32_t unmask_bits) { if(DAC0 == dac_periph){ + /* configure DAC0 LFSR noise mode */ DAC_CTL &= ~DAC_CTL_DWBW0; DAC_CTL |= unmask_bits; }else{ + /* configure DAC1 LFSR noise mode */ DAC_CTL &= ~DAC_CTL_DWBW1; - DAC_CTL |= unmask_bits << 16; + DAC_CTL |= (unmask_bits << DAC1_REG_OFFSET); } } /*! \brief configure DAC triangle noise mode - \param[in] dac_periph - \arg DACx(x=0,1) - \param[in] amplitude + \param[in] dac_periph: DACx(x = 0,1) + \param[in] amplitude: triangle amplitude in DAC triangle noise mode + only one parameter can be selected which is shown as below: \arg DAC_TRIANGLE_AMPLITUDE_1: triangle amplitude is 1 \arg DAC_TRIANGLE_AMPLITUDE_3: triangle amplitude is 3 \arg DAC_TRIANGLE_AMPLITUDE_7: triangle amplitude is 7 @@ -348,33 +414,17 @@ void dac_lfsr_noise_config(uint32_t dac_periph, uint32_t unmask_bits) void dac_triangle_noise_config(uint32_t dac_periph, uint32_t amplitude) { if(DAC0 == dac_periph){ + /* configure DAC0 triangle noise mode */ DAC_CTL &= ~DAC_CTL_DWBW0; DAC_CTL |= amplitude; }else{ + /* configure DAC1 triangle noise mode */ DAC_CTL &= ~DAC_CTL_DWBW1; - DAC_CTL |= amplitude << 16; + DAC_CTL |= (amplitude << DAC1_REG_OFFSET); } } /*! - \brief get DAC output value - \param[in] dac_periph - \arg DACx(x=0,1) - \param[out] none - \retval DAC output data -*/ -uint16_t dac_output_value_get(uint32_t dac_periph) -{ - uint16_t data = 0U; - if(DAC0 == dac_periph){ - data = (uint16_t)DAC0_DO; - }else{ - data = (uint16_t)DAC1_DO; - } - return data; -} - -/*! \brief enable DAC concurrent mode \param[in] none \param[out] none @@ -410,7 +460,7 @@ void dac_concurrent_software_trigger_enable(void) { uint32_t swt = 0U; swt = DAC_SWT_SWTR0 | DAC_SWT_SWTR1; - DAC_SWT |= (swt); + DAC_SWT |= (swt); } /*! @@ -453,6 +503,42 @@ void dac_concurrent_output_buffer_disable(void) } /*! + \brief set DAC concurrent mode data holding register value + \param[in] dac_align: data alignment + only one parameter can be selected which is shown as below: + \arg DAC_ALIGN_8B_R: data right 8b alignment + \arg DAC_ALIGN_12B_R: data right 12b alignment + \arg DAC_ALIGN_12B_L: data left 12b alignment + \param[in] data0: data to be loaded + \param[in] data1: data to be loaded + \param[out] none + \retval none +*/ +void dac_concurrent_data_set(uint32_t dac_align, uint16_t data0, uint16_t data1) +{ + uint32_t data = 0U; + switch(dac_align){ + /* data right 12b alignment */ + case DAC_ALIGN_12B_R: + data = ((uint32_t)data1 << DH_12BIT_OFFSET) | data0; + DACC_R12DH = data; + break; + /* data left 12b alignment */ + case DAC_ALIGN_12B_L: + data = ((uint32_t)data1 << DH_12BIT_OFFSET) | data0; + DACC_L12DH = data; + break; + /* data right 8b alignment */ + case DAC_ALIGN_8B_R: + data = ((uint32_t)data1 << DH_8BIT_OFFSET) | data0; + DACC_R8DH = data; + break; + default: + break; + } +} + +/*! \brief enable DAC concurrent interrupt funcution \param[in] none \param[out] none @@ -479,97 +565,40 @@ void dac_concurrent_interrupt_disable(void) } /*! - \brief set the DAC specified data holding register value - \param[in] dac_periph - \arg DACx(x=0,1) - \param[in] dac_align - \arg DAC_ALIGN_8B_R: data right 8b alignment - \arg DAC_ALIGN_12B_R: data right 12b alignment - \arg DAC_ALIGN_12B_L: data left 12b alignment - \param[in] data: data to be loaded + \brief enable DAC interrupt(DAC DMA underrun interrupt) + \param[in] dac_periph: DACx(x = 0,1) \param[out] none \retval none */ -void dac_data_set(uint32_t dac_periph, uint32_t dac_align, uint16_t data) +void dac_interrupt_enable(uint32_t dac_periph) { if(DAC0 == dac_periph){ - switch(dac_align){ - /* data right 12b alignment */ - case DAC_ALIGN_12B_R: - DAC0_R12DH = data; - break; - /* data left 12b alignment */ - case DAC_ALIGN_12B_L: - DAC0_L12DH = data; - break; - /* data right 8b alignment */ - case DAC_ALIGN_8B_R: - DAC0_R8DH = data; - break; - default: - break; - } + DAC_CTL |= DAC_CTL_DDUDRIE0; }else{ - switch(dac_align){ - /* data right 12b alignment */ - case DAC_ALIGN_12B_R: - DAC1_R12DH = data; - break; - /* data left 12b alignment */ - case DAC_ALIGN_12B_L: - DAC1_L12DH = data; - break; - /* data right 8b alignment */ - case DAC_ALIGN_8B_R: - DAC1_R8DH = data; - break; - default: - break; - } + DAC_CTL |= DAC_CTL_DDUDRIE1; } } /*! - \brief set DAC concurrent mode data holding register value - \param[in] dac_align - \arg DAC_ALIGN_8B_R: data right 8b alignment - \arg DAC_ALIGN_12B_R: data right 12b alignment - \arg DAC_ALIGN_12B_L: data left 12b alignment - \param[in] data0: data to be loaded - \param[in] data1: data to be loaded + \brief disable DAC interrupt(DAC DMA underrun interrupt) + \param[in] dac_periph: DACx(x = 0,1) \param[out] none \retval none */ -void dac_concurrent_data_set(uint32_t dac_align, uint16_t data0, uint16_t data1) +void dac_interrupt_disable(uint32_t dac_periph) { - uint32_t data = 0U; - switch(dac_align){ - /* data right 12b alignment */ - case DAC_ALIGN_12B_R: - data = ((uint32_t)data1 << 16) | data0; - DACC_R12DH = data; - break; - /* data left 12b alignment */ - case DAC_ALIGN_12B_L: - data = ((uint32_t)data1 << 16) | data0; - DACC_L12DH = data; - break; - /* data right 8b alignment */ - case DAC_ALIGN_8B_R: - data = ((uint32_t)data1 << 8) | data0; - DACC_R8DH = data; - break; - default: - break; + if(DAC0 == dac_periph){ + DAC_CTL &= ~DAC_CTL_DDUDRIE0; + }else{ + DAC_CTL &= ~DAC_CTL_DDUDRIE1; } } /*! - \brief get the specified DAC flag(DAC DMA underrun flag) - \param[in] dac_periph - \arg DACx(x=0,1) + \brief get the specified DAC flag (DAC DMA underrun flag) + \param[in] dac_periph: DACx(x = 0,1) \param[out] none - \retval the state of dac bit(SET or RESET) + \retval FlagStatus: SET or RESET */ FlagStatus dac_flag_get(uint32_t dac_periph) { @@ -589,9 +618,8 @@ FlagStatus dac_flag_get(uint32_t dac_periph) } /*! - \brief clear the specified DAC flag(DAC DMA underrun flag) - \param[in] dac_periph - \arg DACx(x=0,1) + \brief clear the specified DAC flag (DAC DMA underrun flag) + \param[in] dac_periph: DACx(x = 0,1) \param[out] none \retval none */ @@ -605,16 +633,16 @@ void dac_flag_clear(uint32_t dac_periph) } /*! - \brief get the specified DAC interrupt flag(DAC DMA underrun interrupt flag) - \param[in] dac_periph - \arg DACx(x=0,1) + \brief get the specified DAC interrupt flag (DAC DMA underrun interrupt flag) + \param[in] dac_periph: DACx(x = 0,1) \param[out] none - \retval the state of DAC interrupt flag(SET or RESET) + \retval FlagStatus: SET or RESET */ FlagStatus dac_interrupt_flag_get(uint32_t dac_periph) { FlagStatus temp_flag = RESET; uint32_t ddudr_flag = 0U, ddudrie_flag = 0U; + if(DAC0 == dac_periph){ /* check the DMA underrun flag and DAC DMA underrun interrupt enable flag */ ddudr_flag = DAC_STAT & DAC_STAT_DDUDR0; @@ -634,9 +662,8 @@ FlagStatus dac_interrupt_flag_get(uint32_t dac_periph) } /*! - \brief clear the specified DAC interrupt flag(DAC DMA underrun interrupt flag) - \param[in] dac_periph - \arg DACx(x=0,1) + \brief clear the specified DAC interrupt flag (DAC DMA underrun interrupt flag) + \param[in] dac_periph: DACx(x = 0,1) \param[out] none \retval none */ diff --git a/bsp/gd32450z-eval/Libraries/GD32F4xx_standard_peripheral/Source/gd32f4xx_dbg.c b/bsp/gd32450z-eval/Libraries/GD32F4xx_standard_peripheral/Source/gd32f4xx_dbg.c index a017c7e3e5..a408136ea4 100644 --- a/bsp/gd32450z-eval/Libraries/GD32F4xx_standard_peripheral/Source/gd32f4xx_dbg.c +++ b/bsp/gd32450z-eval/Libraries/GD32F4xx_standard_peripheral/Source/gd32f4xx_dbg.c @@ -1,16 +1,55 @@ /*! - \file gd32f4xx_dbg.c - \brief DBG driver + \file gd32f4xx_dbg.c + \brief DBG driver + + \version 2016-08-15, V1.0.0, firmware for GD32F4xx + \version 2018-12-12, V2.0.0, firmware for GD32F4xx + \version 2020-09-30, V2.1.0, firmware for GD32F4xx */ /* - Copyright (C) 2016 GigaDevice + Copyright (c) 2020, GigaDevice Semiconductor Inc. + + Redistribution and use in source and binary forms, with or without modification, +are permitted provided that the following conditions are met: - 2016-08-15, V1.0.0, firmware for GD32F4xx + 1. Redistributions of source code must retain the above copyright notice, this + list of conditions and the following disclaimer. + 2. Redistributions in binary form must reproduce the above copyright notice, + this list of conditions and the following disclaimer in the documentation + and/or other materials provided with the distribution. + 3. Neither the name of the copyright holder nor the names of its contributors + may be used to endorse or promote products derived from this software without + specific prior written permission. + + THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED +WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. +IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, +INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT +NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR +PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, +WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY +OF SUCH DAMAGE. */ #include "gd32f4xx_dbg.h" +#define DBG_RESET_VAL 0x00000000U + +/*! + \brief deinitialize the DBG + \param[in] none + \param[out] none + \retval none +*/ +void dbg_deinit(void) +{ + DBG_CTL0 = DBG_RESET_VAL; + DBG_CTL1 = DBG_RESET_VAL; +} + /*! \brief read DBG_ID code register \param[in] none @@ -55,32 +94,69 @@ void dbg_low_power_disable(uint32_t dbg_low_power) /*! \brief enable peripheral behavior when the mcu is in debug mode \param[in] dbg_periph: dbg_periph_enum - \param[out] none + only one parameter can be selected which is shown as below: + \arg DBG_TIMER1_HOLD: hold TIMER1 counter when core is halted + \arg DBG_TIMER2_HOLD: hold TIMER2 counter when core is halted + \arg DBG_TIMER3_HOLD: hold TIMER3 counter when core is halted + \arg DBG_TIMER4_HOLD: hold TIMER4 counter when core is halted + \arg DBG_TIMER5_HOLD: hold TIMER5 counter when core is halted + \arg DBG_TIMER6_HOLD: hold TIMER6 counter when core is halted + \arg DBG_TIMER11_HOLD: hold TIMER11 counter when core is halted + \arg DBG_TIMER12_HOLD: hold TIMER12 counter when core is halted + \arg DBG_TIMER13_HOLD: hold TIMER13 counter when core is halted + \arg DBG_RTC_HOLD: hold RTC calendar and wakeup counter when core is halted + \arg DBG_WWDGT_HOLD: debug WWDGT kept when core is halted + \arg DBG_FWDGT_HOLD: debug FWDGT kept when core is halted + \arg DBG_I2C0_HOLD: hold I2C0 smbus when core is halted + \arg DBG_I2C1_HOLD: hold I2C1 smbus when core is halted + \arg DBG_I2C2_HOLD: hold I2C2 smbus when core is halted + \arg DBG_CAN0_HOLD: debug CAN0 kept when core is halted + \arg DBG_CAN1_HOLD: debug CAN1 kept when core is halted + \arg DBG_TIMER0_HOLD: hold TIMER0 counter when core is halted + \arg DBG_TIMER7_HOLD: hold TIMER7 counter when core is halted + \arg DBG_TIMER8_HOLD: hold TIMER8 counter when core is halted + \arg DBG_TIMER9_HOLD: hold TIMER9 counter when core is halted + \arg DBG_TIMER10_HOLD: hold TIMER10 counter when core is halted + \arg \param[out] none \retval none */ void dbg_periph_enable(dbg_periph_enum dbg_periph) { - if(RESET == ((uint32_t)dbg_periph & BIT(30))){ - DBG_CTL1 |= (uint32_t)dbg_periph; - }else{ - DBG_CTL2 |= ((uint32_t)dbg_periph & (~BIT(30))); - } - + DBG_REG_VAL(dbg_periph) |= BIT(DBG_BIT_POS(dbg_periph)); } /*! \brief disable peripheral behavior when the mcu is in debug mode \param[in] dbg_periph: dbg_periph_enum + only one parameter can be selected which is shown as below: + \arg DBG_TIMER1_HOLD: hold TIMER1 counter when core is halted + \arg DBG_TIMER2_HOLD: hold TIMER2 counter when core is halted + \arg DBG_TIMER3_HOLD: hold TIMER3 counter when core is halted + \arg DBG_TIMER4_HOLD: hold TIMER4 counter when core is halted + \arg DBG_TIMER5_HOLD: hold TIMER5 counter when core is halted + \arg DBG_TIMER6_HOLD: hold TIMER6 counter when core is halted + \arg DBG_TIMER11_HOLD: hold TIMER11 counter when core is halted + \arg DBG_TIMER12_HOLD: hold TIMER12 counter when core is halted + \arg DBG_TIMER13_HOLD: hold TIMER13 counter when core is halted + \arg DBG_RTC_HOLD: hold RTC calendar and wakeup counter when core is halted + \arg DBG_WWDGT_HOLD: debug WWDGT kept when core is halted + \arg DBG_FWDGT_HOLD: debug FWDGT kept when core is halted + \arg DBG_I2C0_HOLD: hold I2C0 smbus when core is halted + \arg DBG_I2C1_HOLD: hold I2C1 smbus when core is halted + \arg DBG_I2C2_HOLD: hold I2C2 smbus when core is halted + \arg DBG_CAN0_HOLD: debug CAN0 kept when core is halted + \arg DBG_CAN1_HOLD: debug CAN1 kept when core is halted + \arg DBG_TIMER0_HOLD: hold TIMER0 counter when core is halted + \arg DBG_TIMER7_HOLD: hold TIMER7 counter when core is halted + \arg DBG_TIMER8_HOLD: hold TIMER8 counter when core is halted + \arg DBG_TIMER9_HOLD: hold TIMER9 counter when core is halted + \arg DBG_TIMER10_HOLD: hold TIMER10 counter when core is halted \param[out] none \retval none */ void dbg_periph_disable(dbg_periph_enum dbg_periph) { - if(RESET == ((uint32_t)dbg_periph & BIT(30))){ - DBG_CTL1 &= ~(uint32_t)dbg_periph; - }else{ - DBG_CTL2 &= ~((uint32_t)dbg_periph & (~BIT(30))); - } + DBG_REG_VAL(dbg_periph) &= ~BIT(DBG_BIT_POS(dbg_periph)); } /*! @@ -106,9 +182,9 @@ void dbg_trace_pin_disable(void) } /*! - \brief trace pin mode selection + \brief trace pin mode selection \param[in] trace_mode: - \arg TRACE_MODE_ASYNC: trace pin used for async mode + \arg TRACE_MODE_ASYNC: trace pin used for async mode \arg TRACE_MODE_SYNC_DATASIZE_1: trace pin used for sync mode and data size is 1 \arg TRACE_MODE_SYNC_DATASIZE_2: trace pin used for sync mode and data size is 2 \arg TRACE_MODE_SYNC_DATASIZE_4: trace pin used for sync mode and data size is 4 diff --git a/bsp/gd32450z-eval/Libraries/GD32F4xx_standard_peripheral/Source/gd32f4xx_dci.c b/bsp/gd32450z-eval/Libraries/GD32F4xx_standard_peripheral/Source/gd32f4xx_dci.c index 2984ff11f7..a1ddcab384 100644 --- a/bsp/gd32450z-eval/Libraries/GD32F4xx_standard_peripheral/Source/gd32f4xx_dci.c +++ b/bsp/gd32450z-eval/Libraries/GD32F4xx_standard_peripheral/Source/gd32f4xx_dci.c @@ -1,12 +1,37 @@ /*! - \file gd32f4xx_dci.c - \brief DCI driver + \file gd32f4xx_dci.c + \brief DCI driver + + \version 2016-08-15, V1.0.0, firmware for GD32F4xx + \version 2018-12-12, V2.0.0, firmware for GD32F4xx + \version 2020-09-30, V2.1.0, firmware for GD32F4xx */ /* - Copyright (C) 2016 GigaDevice + Copyright (c) 2020, GigaDevice Semiconductor Inc. + + Redistribution and use in source and binary forms, with or without modification, +are permitted provided that the following conditions are met: - 2016-08-15, V1.0.0, firmware for GD32F4xx + 1. Redistributions of source code must retain the above copyright notice, this + list of conditions and the following disclaimer. + 2. Redistributions in binary form must reproduce the above copyright notice, + this list of conditions and the following disclaimer in the documentation + and/or other materials provided with the distribution. + 3. Neither the name of the copyright holder nor the names of its contributors + may be used to endorse or promote products derived from this software without + specific prior written permission. + + THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED +WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. +IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, +INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT +NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR +PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, +WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY +OF SUCH DAMAGE. */ #include "gd32f4xx_dci.h" @@ -25,11 +50,11 @@ void dci_deinit(void) /*! \brief initialize DCI registers - \param[in] dci_struct: DCI parameter initialization stuct + \param[in] dci_struct: DCI parameter initialization structure members of the structure and the member values are shown as below: capture_mode : DCI_CAPTURE_MODE_CONTINUOUS, DCI_CAPTURE_MODE_SNAPSHOT colck_polarity : DCI_CK_POLARITY_FALLING, DCI_CK_POLARITY_RISING - hsync_polarity : DCI_HSYNC_POLARITY_LOW, DCI_HSYNC_POLARITY_HIGH + hsync_polarity : DCI_HSYNC_POLARITY_LOW, DCI_HSYNC_POLARITY_HIGH vsync_polarity : DCI_VSYNC_POLARITY_LOW, DCI_VSYNC_POLARITY_HIGH frame_rate : DCI_FRAME_RATE_ALL, DCI_FRAME_RATE_1_2, DCI_FRAME_RATE_1_4 interface_format: DCI_INTERFACE_FORMAT_8BITS, DCI_INTERFACE_FORMAT_10BITS, @@ -39,10 +64,10 @@ void dci_deinit(void) */ void dci_init(dci_parameter_struct* dci_struct) { - uint32_t reg =0U; + uint32_t reg = 0U; /* disable capture function and DCI */ DCI_CTL &= ~(DCI_CTL_CAP | DCI_CTL_DCIEN); - /* config DCI parameter */ + /* configure DCI parameter */ reg |= dci_struct->capture_mode; reg |= dci_struct->clock_polarity; reg |= dci_struct->hsync_polarity; @@ -54,18 +79,18 @@ void dci_init(dci_parameter_struct* dci_struct) } /*! - \brief enable DCI function + \brief enable DCI function \param[in] none \param[out] none \retval none */ void dci_enable(void) { - DCI_CTL |= DCI_CTL_DCIEN; + DCI_CTL |= DCI_CTL_DCIEN; } /*! - \brief disable DCI function + \brief disable DCI function \param[in] none \param[out] none \retval none @@ -76,7 +101,7 @@ void dci_disable(void) } /*! - \brief enable DCI capture + \brief enable DCI capture \param[in] none \param[out] none \retval none @@ -87,7 +112,7 @@ void dci_capture_enable(void) } /*! - \brief disable DCI capture + \brief disable DCI capture \param[in] none \param[out] none \retval none @@ -98,7 +123,7 @@ void dci_capture_disable(void) } /*! - \brief enable DCI jpeg mode + \brief enable DCI jpeg mode \param[in] none \param[out] none \retval none @@ -109,7 +134,7 @@ void dci_jpeg_enable(void) } /*! - \brief disable DCI jpeg mode + \brief disable DCI jpeg mode \param[in] none \param[out] none \retval none @@ -142,11 +167,11 @@ void dci_crop_window_disable(void) } /*! - \brief config DCI cropping window + \brief configure DCI cropping window \param[in] start_x: window horizontal start position \param[in] start_y: window vertical start position - \param[in] size_height: window horizontal size - \param[in] size_width: window vertical size + \param[in] size_width: window horizontal size + \param[in] size_height: window vertical size \param[out] none \retval none */ @@ -157,28 +182,28 @@ void dci_crop_window_config(uint16_t start_x, uint16_t start_y, uint16_t size_wi } /*! - \brief enable sync codes function + \brief enable embedded synchronous mode \param[in] none \param[out] none \retval none */ -void dci_sync_codes_enable(void) +void dci_embedded_sync_enable(void) { DCI_CTL |= DCI_CTL_ESM; } /*! - \brief disable sync codes function + \brief disble embedded synchronous mode \param[in] none \param[out] none \retval none */ -void dci_sync_codes_disable(void) +void dci_embedded_sync_disable(void) { DCI_CTL &= ~DCI_CTL_ESM; } /*! - \brief config sync codes + \brief config synchronous codes in embedded synchronous mode \param[in] frame_start: frame start code in embedded synchronous mode \param[in] line_start: line start code in embedded synchronous mode \param[in] line_end: line end code in embedded synchronous mode @@ -192,7 +217,7 @@ void dci_sync_codes_config(uint8_t frame_start, uint8_t line_start, uint8_t line } /*! - \brief config sync codes unmask + \brief config synchronous codes unmask in embedded synchronous mode \param[in] frame_start: frame start code unmask bits in embedded synchronous mode \param[in] line_start: line start code unmask bits in embedded synchronous mode \param[in] line_end: line end code unmask bits in embedded synchronous mode @@ -202,7 +227,7 @@ void dci_sync_codes_config(uint8_t frame_start, uint8_t line_start, uint8_t line */ void dci_sync_codes_unmask_config(uint8_t frame_start, uint8_t line_start, uint8_t line_end, uint8_t frame_end) { - DCI_SCUMSK = ((uint32_t)frame_start | ((uint32_t)line_start<<8) | ((uint32_t)line_end<<16) | ((uint32_t)frame_end<<24)); + DCI_SCUMSK = ((uint32_t)frame_start | ((uint32_t)line_start<<8) | ((uint32_t)line_end<<16) | ((uint32_t)frame_end<<24)); } /*! @@ -217,12 +242,45 @@ uint32_t dci_data_read(void) } /*! + \brief get specified flag + \param[in] flag: + \arg DCI_FLAG_HS: HS line status + \arg DCI_FLAG_VS: VS line status + \arg DCI_FLAG_FV:FIFO valid + \arg DCI_FLAG_EF: end of frame flag + \arg DCI_FLAG_OVR: FIFO overrun flag + \arg DCI_FLAG_ESE: embedded synchronous error flag + \arg DCI_FLAG_VSYNC: vsync flag + \arg DCI_FLAG_EL: end of line flag + \param[out] none + \retval FlagStatus: SET or RESET +*/ +FlagStatus dci_flag_get(uint32_t flag) +{ + uint32_t stat = 0U; + + if(flag >> 31){ + /* get flag status from DCI_STAT1 register */ + stat = DCI_STAT1; + }else{ + /* get flag status from DCI_STAT0 register */ + stat = DCI_STAT0; + } + + if(flag & stat){ + return SET; + }else{ + return RESET; + } +} + +/*! \brief enable specified DCI interrupt \param[in] interrupt: \arg DCI_INT_EF: end of frame interrupt \arg DCI_INT_OVR: FIFO overrun interrupt - \arg DCI_INT_ESE: embedded synchronous error interrupt - \arg DCI_INT_VS: vsync interrupt + \arg DCI_INT_ESE: embedded synchronous error interrupt + \arg DCI_INT_VSYNC: vsync interrupt \arg DCI_INT_EL: end of line interrupt \param[out] none \retval none @@ -237,8 +295,8 @@ void dci_interrupt_enable(uint32_t interrupt) \param[in] interrupt: \arg DCI_INT_EF: end of frame interrupt \arg DCI_INT_OVR: FIFO overrun interrupt - \arg DCI_INT_ESE: embedded synchronous error interrupt - \arg DCI_INT_VS: vsync interrupt + \arg DCI_INT_ESE: embedded synchronous error interrupt + \arg DCI_INT_VSYNC: vsync interrupt \arg DCI_INT_EL: end of line interrupt \param[out] none \retval none @@ -249,93 +307,39 @@ void dci_interrupt_disable(uint32_t interrupt) } /*! - \brief clear specified interrupt - \param[in] interrupt: + \brief clear specified interrupt flag + \param[in] int_flag: \arg DCI_INT_EF: end of frame interrupt \arg DCI_INT_OVR: FIFO overrun interrupt - \arg DCI_INT_ESE: embedded synchronous error interrupt - \arg DCI_INT_VS: vsync interrupt + \arg DCI_INT_ESE: embedded synchronous error interrupt + \arg DCI_INT_VSYNC: vsync interrupt \arg DCI_INT_EL: end of line interrupt \param[out] none \retval none */ -void dci_interrupt_clear(uint32_t interrupt) +void dci_interrupt_flag_clear(uint32_t int_flag) { - DCI_INTC |= interrupt; -} - -/*! - \brief get specified flag - \param[in] flag: - \arg DCI_FLAG_HS: HS line status - \arg DCI_FLAG_VS: VS line status - \arg DCI_FLAG_FV:FIFO valid - \arg DCI_FLAG_EFF: end of frame flag - \arg DCI_FLAG_OVRF: FIFO overrun flag - \arg DCI_FLAG_ESEF: embedded synchronous error flag - \arg DCI_FLAG_VSF: vsync flag - \arg DCI_FLAG_ELF: end of line flag - \param[out] none - \retval FlagStatus: SET or RESET -*/ -FlagStatus dci_flag_get(uint32_t flag) -{ - uint32_t ret = 0U; - - switch(flag){ - /* get flag status from DCI_STAT0 register */ - case DCI_FLAG_HS: - ret = (DCI_STAT0 & DCI_STAT0_HS); - break; - case DCI_FLAG_VS: - ret = (DCI_STAT0 & DCI_STAT0_VS); - break; - case DCI_FLAG_FV: - ret = (DCI_STAT0 & DCI_STAT0_FV); - break; - /* get flag status from DCI_STAT1 register */ - case DCI_FLAG_EFF: - ret = (DCI_STAT1 & DCI_STAT1_EFF); - break; - case DCI_FLAG_OVRF: - ret = (DCI_STAT1 & DCI_STAT1_OVRF); - break; - case DCI_FLAG_ESEF: - ret = (DCI_STAT1 & DCI_STAT1_ESEF); - break; - case DCI_FLAG_VSF: - ret = (DCI_STAT1 & DCI_STAT1_VSF); - break; - case DCI_FLAG_ELF: - ret = (DCI_STAT1 & DCI_STAT1_ELF); - break; - default : - break; - } - - if(RESET == ret){ - return RESET; - }else{ - return SET; - } + DCI_INTC |= int_flag; } /*! \brief get specified interrupt flag - \param[in] interrupt: - \arg DCI_INT_EF: end of frame interrupt - \arg DCI_INT_OVR: FIFO overrun interrupt - \arg DCI_INT_ESE: embedded synchronous error interrupt - \arg DCI_INT_VS: vsync interrupt - \arg DCI_INT_EL: end of line interrupt + \param[in] int_flag: + \arg DCI_INT_FLAG_EF: end of frame interrupt flag + \arg DCI_INT_FLAG_OVR: FIFO overrun interrupt flag + \arg DCI_INT_FLAG_ESE: embedded synchronous error interrupt flag + \arg DCI_INT_FLAG_VSYNC: vsync interrupt flag + \arg DCI_INT_FLAG_EL: end of line interrupt flag \param[out] none \retval FlagStatus: SET or RESET */ -FlagStatus dci_interrupt_flag_get(uint32_t interrupt) +FlagStatus dci_interrupt_flag_get(uint32_t int_flag) { - if(RESET == (DCI_INTF & interrupt)){ + if(RESET == (DCI_INTF & int_flag)){ return RESET; }else{ return SET; } } + + diff --git a/bsp/gd32450z-eval/Libraries/GD32F4xx_standard_peripheral/Source/gd32f4xx_dma.c b/bsp/gd32450z-eval/Libraries/GD32F4xx_standard_peripheral/Source/gd32f4xx_dma.c index c7f5ce9a70..d8bd7be2d7 100644 --- a/bsp/gd32450z-eval/Libraries/GD32F4xx_standard_peripheral/Source/gd32f4xx_dma.c +++ b/bsp/gd32450z-eval/Libraries/GD32F4xx_standard_peripheral/Source/gd32f4xx_dma.c @@ -1,14 +1,40 @@ /*! - \file gd32f4xx_dma.c - \brief DMA driver + \file gd32f4xx_dma.c + \brief DMA driver + + \version 2016-08-15, V1.0.0, firmware for GD32F4xx + \version 2018-12-12, V2.0.0, firmware for GD32F4xx + \version 2020-09-30, V2.1.0, firmware for GD32F4xx */ /* - Copyright (C) 2016 GigaDevice + Copyright (c) 2020, GigaDevice Semiconductor Inc. + + Redistribution and use in source and binary forms, with or without modification, +are permitted provided that the following conditions are met: - 2016-08-15, V1.0.0, firmware for GD32F4xx + 1. Redistributions of source code must retain the above copyright notice, this + list of conditions and the following disclaimer. + 2. Redistributions in binary form must reproduce the above copyright notice, + this list of conditions and the following disclaimer in the documentation + and/or other materials provided with the distribution. + 3. Neither the name of the copyright holder nor the names of its contributors + may be used to endorse or promote products derived from this software without + specific prior written permission. + + THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED +WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. +IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, +INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT +NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR +PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, +WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY +OF SUCH DAMAGE. */ + #include "gd32f4xx_dma.h" /* DMA register bit offset */ @@ -23,7 +49,7 @@ \param[out] none \retval none */ -void dma_deinit(uint32_t dma_periph,dma_channel_enum channelx) +void dma_deinit(uint32_t dma_periph, dma_channel_enum channelx) { /* disable DMA a channel */ DMA_CHCTL(dma_periph,channelx) &= ~DMA_CHXCTL_CHEN; @@ -37,11 +63,55 @@ void dma_deinit(uint32_t dma_periph,dma_channel_enum channelx) if(channelx < DMA_CH4){ DMA_INTC0(dma_periph) |= DMA_FLAG_ADD(DMA_CHINTF_RESET_VALUE,channelx); }else{ + channelx -= (dma_channel_enum)4; DMA_INTC1(dma_periph) |= DMA_FLAG_ADD(DMA_CHINTF_RESET_VALUE,channelx); } } /*! + \brief initialize the DMA single data mode parameters struct with the default values + \param[in] init_struct: the initialization data needed to initialize DMA channel + \param[out] none + \retval none +*/ +void dma_single_data_para_struct_init(dma_single_data_parameter_struct* init_struct) +{ + /* set the DMA struct with the default values */ + init_struct->periph_addr = 0U; + init_struct->periph_inc = DMA_PERIPH_INCREASE_DISABLE; + init_struct->memory0_addr = 0U; + init_struct->memory_inc = DMA_MEMORY_INCREASE_DISABLE; + init_struct->periph_memory_width = 0U; + init_struct->circular_mode = DMA_CIRCULAR_MODE_DISABLE; + init_struct->direction = DMA_PERIPH_TO_MEMORY; + init_struct->number = 0U; + init_struct->priority = DMA_PRIORITY_LOW; +} + +/*! + \brief initialize the DMA multi data mode parameters struct with the default values + \param[in] init_struct: the initialization data needed to initialize DMA channel + \param[out] none + \retval none +*/ +void dma_multi_data_para_struct_init(dma_multi_data_parameter_struct* init_struct) +{ + /* set the DMA struct with the default values */ + init_struct->periph_addr = 0U; + init_struct->periph_width = 0U; + init_struct->periph_inc = DMA_PERIPH_INCREASE_DISABLE; + init_struct->memory0_addr = 0U; + init_struct->memory_width = 0U; + init_struct->memory_inc = DMA_MEMORY_INCREASE_DISABLE; + init_struct->memory_burst_width = 0U; + init_struct->periph_burst_width = 0U; + init_struct->circular_mode = DMA_CIRCULAR_MODE_DISABLE; + init_struct->direction = DMA_PERIPH_TO_MEMORY; + init_struct->number = 0U; + init_struct->priority = DMA_PRIORITY_LOW; +} + +/*! \brief initialize DMA single data mode \param[in] dma_periph: DMAx(x=0,1) \arg DMAx(x=0,1) @@ -49,57 +119,57 @@ void dma_deinit(uint32_t dma_periph,dma_channel_enum channelx) \arg DMA_CHx(x=0..7) \param[in] init_struct: the data needed to initialize DMA single data mode periph_addr: peripheral base address - periph_memory_width: DMA_PERIPH_WIDTH_8BIT,DMA_PERIPH_WIDTH_16BIT,DMA_PERIPH_WIDTH_32BIT - periph_inc: DMA_PERIPH_INCREASE_ENABLE,DMA_PERIPH_INCREASE_DISABLE,DMA_PERIPH_INCREASE_FIX + periph_inc: DMA_PERIPH_INCREASE_ENABLE,DMA_PERIPH_INCREASE_DISABLE,DMA_PERIPH_INCREASE_FIX memory0_addr: memory base address memory_inc: DMA_MEMORY_INCREASE_ENABLE,DMA_MEMORY_INCREASE_DISABLE + periph_memory_width: DMA_PERIPH_WIDTH_8BIT,DMA_PERIPH_WIDTH_16BIT,DMA_PERIPH_WIDTH_32BIT + circular_mode: DMA_CIRCULAR_MODE_ENABLE,DMA_CIRCULAR_MODE_DISABLE direction: DMA_PERIPH_TO_MEMORY,DMA_MEMORY_TO_PERIPH,DMA_MEMORY_TO_MEMORY number: the number of remaining data to be transferred by the DMA priority: DMA_PRIORITY_LOW,DMA_PRIORITY_MEDIUM,DMA_PRIORITY_HIGH,DMA_PRIORITY_ULTRA_HIGH - circular_mode: DMA_CIRCULAR_MODE_ENABLE,DMA_CIRCULAR_MODE_DISABLE \param[out] none \retval none */ -void dma_single_data_mode_init(uint32_t dma_periph,dma_channel_enum channelx,dma_single_data_parameter_struct init_struct) +void dma_single_data_mode_init(uint32_t dma_periph, dma_channel_enum channelx, dma_single_data_parameter_struct* init_struct) { uint32_t ctl; - + /* select single data mode */ DMA_CHFCTL(dma_periph,channelx) &= ~DMA_CHXFCTL_MDMEN; - + /* configure peripheral base address */ - DMA_CHPADDR(dma_periph,channelx) = init_struct.periph_addr; - + DMA_CHPADDR(dma_periph,channelx) = init_struct->periph_addr; + /* configure memory base address */ - DMA_CHM0ADDR(dma_periph,channelx) = init_struct.memory0_addr; - + DMA_CHM0ADDR(dma_periph,channelx) = init_struct->memory0_addr; + /* configure the number of remaining data to be transferred */ - DMA_CHCNT(dma_periph,channelx) = init_struct.number; - + DMA_CHCNT(dma_periph,channelx) = init_struct->number; + /* configure peripheral and memory transfer width,channel priotity,transfer mode */ ctl = DMA_CHCTL(dma_periph,channelx); ctl &= ~(DMA_CHXCTL_PWIDTH | DMA_CHXCTL_MWIDTH | DMA_CHXCTL_PRIO | DMA_CHXCTL_TM); - ctl |= (init_struct.periph_memory_width | (init_struct.periph_memory_width << 2) | init_struct.priority | init_struct.direction); + ctl |= (init_struct->periph_memory_width | (init_struct->periph_memory_width << 2) | init_struct->priority | init_struct->direction); DMA_CHCTL(dma_periph,channelx) = ctl; /* configure peripheral increasing mode */ - if(DMA_PERIPH_INCREASE_ENABLE == init_struct.periph_inc){ + if(DMA_PERIPH_INCREASE_ENABLE == init_struct->periph_inc){ DMA_CHCTL(dma_periph,channelx) |= DMA_CHXCTL_PNAGA; - }else if(DMA_PERIPH_INCREASE_DISABLE == init_struct.periph_inc){ + }else if(DMA_PERIPH_INCREASE_DISABLE == init_struct->periph_inc){ DMA_CHCTL(dma_periph,channelx) &= ~DMA_CHXCTL_PNAGA; }else{ DMA_CHCTL(dma_periph,channelx) |= DMA_CHXCTL_PAIF; } /* configure memory increasing mode */ - if(DMA_MEMORY_INCREASE_ENABLE == init_struct.memory_inc){ + if(DMA_MEMORY_INCREASE_ENABLE == init_struct->memory_inc){ DMA_CHCTL(dma_periph,channelx) |= DMA_CHXCTL_MNAGA; }else{ DMA_CHCTL(dma_periph,channelx) &= ~DMA_CHXCTL_MNAGA; } /* configure DMA circular mode */ - if(DMA_CIRCULAR_MODE_ENABLE == init_struct.circular_mode){ + if(DMA_CIRCULAR_MODE_ENABLE == init_struct->circular_mode){ DMA_CHCTL(dma_periph,channelx) |= DMA_CHXCTL_CMEN; }else{ DMA_CHCTL(dma_periph,channelx) &= ~DMA_CHXCTL_CMEN; @@ -115,60 +185,60 @@ void dma_single_data_mode_init(uint32_t dma_periph,dma_channel_enum channelx,dma \param[in] dma_multi_data_parameter_struct: the data needed to initialize DMA multi data mode periph_addr: peripheral base address periph_width: DMA_PERIPH_WIDTH_8BIT,DMA_PERIPH_WIDTH_16BIT,DMA_PERIPH_WIDTH_32BIT - periph_inc: DMA_PERIPH_INCREASE_ENABLE,DMA_PERIPH_INCREASE_DISABLE,DMA_PERIPH_INCREASE_FIX + periph_inc: DMA_PERIPH_INCREASE_ENABLE,DMA_PERIPH_INCREASE_DISABLE,DMA_PERIPH_INCREASE_FIX memory0_addr: memory0 base address memory_width: DMA_MEMORY_WIDTH_8BIT,DMA_MEMORY_WIDTH_16BIT,DMA_MEMORY_WIDTH_32BIT memory_inc: DMA_MEMORY_INCREASE_ENABLE,DMA_MEMORY_INCREASE_DISABLE - direction: DMA_PERIPH_TO_MEMORY,DMA_MEMORY_TO_PERIPH,DMA_MEMORY_TO_MEMORY - number: the number of remaining data to be transferred by the DMA - priority: DMA_PRIORITY_LOW,DMA_PRIORITY_MEDIUM,DMA_PRIORITY_HIGH,DMA_PRIORITY_ULTRA_HIGH - circular_mode: DMA_CIRCULAR_MODE_ENABLE,DMA_CIRCULAR_MODE_DISABLE memory_burst_width: DMA_MEMORY_BURST_SINGLE,DMA_MEMORY_BURST_4_BEAT,DMA_MEMORY_BURST_8_BEAT,DMA_MEMORY_BURST_16_BEAT periph_burst_width: DMA_PERIPH_BURST_SINGLE,DMA_PERIPH_BURST_4_BEAT,DMA_PERIPH_BURST_8_BEAT,DMA_PERIPH_BURST_16_BEAT critical_value: DMA_FIFO_1_WORD,DMA_FIFO_2_WORD,DMA_FIFO_3_WORD,DMA_FIFO_4_WORD + circular_mode: DMA_CIRCULAR_MODE_ENABLE,DMA_CIRCULAR_MODE_DISABLE + direction: DMA_PERIPH_TO_MEMORY,DMA_MEMORY_TO_PERIPH,DMA_MEMORY_TO_MEMORY + number: the number of remaining data to be transferred by the DMA + priority: DMA_PRIORITY_LOW,DMA_PRIORITY_MEDIUM,DMA_PRIORITY_HIGH,DMA_PRIORITY_ULTRA_HIGH \param[out] none \retval none */ -void dma_multi_data_mode_init(uint32_t dma_periph,dma_channel_enum channelx,dma_multi_data_parameter_struct init_struct) +void dma_multi_data_mode_init(uint32_t dma_periph, dma_channel_enum channelx, dma_multi_data_parameter_struct* init_struct) { uint32_t ctl; - + /* select multi data mode and configure FIFO critical value */ - DMA_CHFCTL(dma_periph,channelx) |= (DMA_CHXFCTL_MDMEN | init_struct.critical_value); - + DMA_CHFCTL(dma_periph,channelx) |= (DMA_CHXFCTL_MDMEN | init_struct->critical_value); + /* configure peripheral base address */ - DMA_CHPADDR(dma_periph,channelx) = init_struct.periph_addr; - + DMA_CHPADDR(dma_periph,channelx) = init_struct->periph_addr; + /* configure memory base address */ - DMA_CHM0ADDR(dma_periph,channelx) = init_struct.memory0_addr; - + DMA_CHM0ADDR(dma_periph,channelx) = init_struct->memory0_addr; + /* configure the number of remaining data to be transferred */ - DMA_CHCNT(dma_periph,channelx) = init_struct.number; - + DMA_CHCNT(dma_periph,channelx) = init_struct->number; + /* configure peripheral and memory transfer width,channel priotity,transfer mode,peripheral and memory burst transfer width */ ctl = DMA_CHCTL(dma_periph,channelx); ctl &= ~(DMA_CHXCTL_PWIDTH | DMA_CHXCTL_MWIDTH | DMA_CHXCTL_PRIO | DMA_CHXCTL_TM | DMA_CHXCTL_PBURST | DMA_CHXCTL_MBURST); - ctl |= (init_struct.periph_width | (init_struct.memory_width ) | init_struct.priority | init_struct.direction | init_struct.memory_burst_width | init_struct.periph_burst_width); + ctl |= (init_struct->periph_width | (init_struct->memory_width ) | init_struct->priority | init_struct->direction | init_struct->memory_burst_width | init_struct->periph_burst_width); DMA_CHCTL(dma_periph,channelx) = ctl; /* configure peripheral increasing mode */ - if(DMA_PERIPH_INCREASE_ENABLE == init_struct.periph_inc){ + if(DMA_PERIPH_INCREASE_ENABLE == init_struct->periph_inc){ DMA_CHCTL(dma_periph,channelx) |= DMA_CHXCTL_PNAGA; - }else if(DMA_PERIPH_INCREASE_DISABLE == init_struct.periph_inc){ + }else if(DMA_PERIPH_INCREASE_DISABLE == init_struct->periph_inc){ DMA_CHCTL(dma_periph,channelx) &= ~DMA_CHXCTL_PNAGA; }else{ DMA_CHCTL(dma_periph,channelx) |= DMA_CHXCTL_PAIF; } /* configure memory increasing mode */ - if(DMA_MEMORY_INCREASE_ENABLE == init_struct.memory_inc){ + if(DMA_MEMORY_INCREASE_ENABLE == init_struct->memory_inc){ DMA_CHCTL(dma_periph,channelx) |= DMA_CHXCTL_MNAGA; }else{ DMA_CHCTL(dma_periph,channelx) &= ~DMA_CHXCTL_MNAGA; } /* configure DMA circular mode */ - if(DMA_CIRCULAR_MODE_ENABLE == init_struct.circular_mode){ + if(DMA_CIRCULAR_MODE_ENABLE == init_struct->circular_mode){ DMA_CHCTL(dma_periph,channelx) |= DMA_CHXCTL_CMEN; }else{ DMA_CHCTL(dma_periph,channelx) &= ~DMA_CHXCTL_CMEN; @@ -176,216 +246,6 @@ void dma_multi_data_mode_init(uint32_t dma_periph,dma_channel_enum channelx,dma_ } /*! - \brief get DMA flag is set or not - \param[in] dma_periph: DMAx(x=0,1) - \arg DMAx(x=0,1) - \param[in] channelx: specify which DMA channel to get flag - \arg DMA_CHx(x=0..7) - \param[in] flag: specify get which flag - \arg DMA_INTF_FEEIF: FIFO error and exception flag - \arg DMA_INTF_SDEIF: single data mode exception flag - \arg DMA_INTF_TAEIF: transfer access error flag - \arg DMA_INTF_HTFIF: half transfer finish flag - \arg DMA_INTF_FTFIF: full transger finish flag - \param[out] none - \retval FlagStatus: SET or RESET -*/ -FlagStatus dma_flag_get(uint32_t dma_periph,dma_channel_enum channelx,uint32_t flag) -{ - if(channelx < DMA_CH4){ - if(DMA_INTF0(dma_periph) & DMA_FLAG_ADD(flag,channelx)){ - return SET; - }else{ - return RESET; - } - }else{ - channelx -= (dma_channel_enum)4; - if(DMA_INTF1(dma_periph) & DMA_FLAG_ADD(flag,channelx)){ - return SET; - }else{ - return RESET; - } - } -} - -/*! - \brief clear DMA a channel flag - \param[in] dma_periph: DMAx(x=0,1) - \arg DMAx(x=0,1) - \param[in] channelx: specify which DMA channel to get flag - \arg DMA_CHx(x=0..7) - \param[in] flag: specify get which flag - \arg DMA_INTF_FEEIF: FIFO error and exception flag - \arg DMA_INTF_SDEIF: single data mode exception flag - \arg DMA_INTF_TAEIF: transfer access error flag - \arg DMA_INTF_HTFIF: half transfer finish flag - \arg DMA_INTF_FTFIF: full transger finish flag - \param[out] none - \retval none -*/ -void dma_flag_clear(uint32_t dma_periph,dma_channel_enum channelx,uint32_t flag) -{ - if(channelx < DMA_CH4){ - DMA_INTC0(dma_periph) |= DMA_FLAG_ADD(flag,channelx); - }else{ - channelx -= (dma_channel_enum)4; - DMA_INTC1(dma_periph) |= DMA_FLAG_ADD(flag,channelx); - } -} - -/*! - \brief get DMA interrupt flag is set or not - \param[in] dma_periph: DMAx(x=0,1) - \arg DMAx(x=0,1) - \param[in] channelx: specify which DMA channel to get interrupt flag - \arg DMA_CHx(x=0..7) - \param[in] interrupt: specify get which flag - \arg DMA_INTF_FEEIF: FIFO error and exception flag - \arg DMA_INTF_SDEIF: single data mode exception flag - \arg DMA_INTF_TAEIF: transfer access error flag - \arg DMA_INTF_HTFIF: half transfer finish flag - \arg DMA_INTF_FTFIF: full transger finish flag - \param[out] none - \retval FlagStatus: SET or RESET -*/ -FlagStatus dma_interrupt_flag_get(uint32_t dma_periph,dma_channel_enum channelx,uint32_t interrupt) -{ - uint32_t interrupt_enable = 0U,interrupt_flag = 0U; - dma_channel_enum channel_flag_offset = channelx; - if(channelx < DMA_CH4){ - switch(interrupt){ - case DMA_INTF_FEEIF: - interrupt_flag = DMA_INTF0(dma_periph) & DMA_FLAG_ADD(interrupt,channelx); - interrupt_enable = DMA_CHFCTL(dma_periph,channelx) & DMA_CHXFCTL_FEEIE; - break; - case DMA_INTF_SDEIF: - interrupt_flag = DMA_INTF0(dma_periph) & DMA_FLAG_ADD(interrupt,channelx); - interrupt_enable = DMA_CHCTL(dma_periph,channelx) & DMA_CHXCTL_SDEIE; - break; - case DMA_INTF_TAEIF: - interrupt_flag = DMA_INTF0(dma_periph) & DMA_FLAG_ADD(interrupt,channelx); - interrupt_enable = DMA_CHCTL(dma_periph,channelx) & DMA_CHXCTL_TAEIE; - break; - case DMA_INTF_HTFIF: - interrupt_flag = DMA_INTF0(dma_periph) & DMA_FLAG_ADD(interrupt,channelx); - interrupt_enable = DMA_CHCTL(dma_periph,channelx) & DMA_CHXCTL_HTFIE; - break; - case DMA_INTF_FTFIF: - interrupt_flag = (DMA_INTF0(dma_periph) & DMA_FLAG_ADD(interrupt,channelx)); - interrupt_enable = (DMA_CHCTL(dma_periph,channelx) & DMA_CHXCTL_FTFIE); - break; - default: - break; - } - }else{ - channel_flag_offset -= (dma_channel_enum)4; - switch(interrupt){ - case DMA_INTF_FEEIF: - interrupt_flag = DMA_INTF1(dma_periph) & DMA_FLAG_ADD(interrupt,channel_flag_offset); - interrupt_enable = DMA_CHFCTL(dma_periph,channelx) & DMA_CHXFCTL_FEEIE; - break; - case DMA_INTF_SDEIF: - interrupt_flag = DMA_INTF1(dma_periph) & DMA_FLAG_ADD(interrupt,channel_flag_offset); - interrupt_enable = DMA_CHCTL(dma_periph,channelx) & DMA_CHXCTL_SDEIE; - break; - case DMA_INTF_TAEIF: - interrupt_flag = DMA_INTF1(dma_periph) & DMA_FLAG_ADD(interrupt,channel_flag_offset); - interrupt_enable = DMA_CHCTL(dma_periph,channelx) & DMA_CHXCTL_TAEIE; - break; - case DMA_INTF_HTFIF: - interrupt_flag = DMA_INTF1(dma_periph) & DMA_FLAG_ADD(interrupt,channel_flag_offset); - interrupt_enable = DMA_CHCTL(dma_periph,channelx) & DMA_CHXCTL_HTFIE; - break; - case DMA_INTF_FTFIF: - interrupt_flag = DMA_INTF1(dma_periph) & DMA_FLAG_ADD(interrupt,channel_flag_offset); - interrupt_enable = DMA_CHCTL(dma_periph,channelx) & DMA_CHXCTL_FTFIE; - break; - default: - break; - } - } - - if(interrupt_flag && interrupt_enable){ - return SET; - }else{ - return RESET; - } -} - -/*! - \brief clear DMA a channel interrupt flag - \param[in] dma_periph: DMAx(x=0,1) - \arg DMAx(x=0,1) - \param[in] channelx: specify which DMA channel to clear interrupt flag - \arg DMA_CHx(x=0..7) - \param[in] interrupt: specify get which flag - \arg DMA_INTC_FEEIFC: clear FIFO error and exception flag - \arg DMA_INTC_SDEIFC: clear single data mode exception flag - \arg DMA_INTC_TAEIFC: clear transfer access error flag - \arg DMA_INTC_HTFIFC: clear half transfer finish flag - \arg DMA_INTC_FTFIFC: clear full transger finish flag - \param[out] none - \retval none -*/ -void dma_interrupt_flag_clear(uint32_t dma_periph,dma_channel_enum channelx,uint32_t interrupt) -{ - if(channelx < DMA_CH4){ - DMA_INTC0(dma_periph) |= DMA_FLAG_ADD(interrupt,channelx); - }else{ - channelx -= (dma_channel_enum)4; - DMA_INTC1(dma_periph) |= DMA_FLAG_ADD(interrupt,channelx); - } -} - -/*! - \brief enable DMA interrupt - \param[in] dma_periph: DMAx(x=0,1) - \arg DMAx(x=0,1) - \param[in] channelx: specify which DMA channel - \arg DMA_CHx(x=0..7) - \param[in] source: specify which interrupt to enbale - \arg DMA_CHXCTL_SDEIE: single data mode exception interrupt enable - \arg DMA_CHXCTL_TAEIE: tranfer access error interrupt enable - \arg DMA_CHXCTL_HTFIE: half transfer finish interrupt enable - \arg DMA_CHXCTL_FTFIE: full transfer finish interrupt enable - \arg DMA_CHXFCTL_FEEIE: FIFO exception interrupt enable - \param[out] none - \retval none -*/ -void dma_interrupt_enable(uint32_t dma_periph,dma_channel_enum channelx,uint32_t source) -{ - if(DMA_CHXFCTL_FEEIE != source){ - DMA_CHCTL(dma_periph,channelx) |= source; - }else{ - DMA_CHFCTL(dma_periph,channelx) |= source; - } -} - -/*! - \brief disable DMA interrupt - \param[in] dma_periph: DMAx(x=0,1) - \arg DMAx(x=0,1) - \param[in] channelx: specify which DMA channel - \arg DMA_CHx(x=0..7) - \param[in] source: specify which interrupt to disbale - \arg DMA_CHXCTL_SDEIE: single data mode exception interrupt enable - \arg DMA_CHXCTL_TAEIE: tranfer access error interrupt enable - \arg DMA_CHXCTL_HTFIE: half transfer finish interrupt enable - \arg DMA_CHXCTL_FTFIE: full transfer finish interrupt enable - \arg DMA_CHXFCTL_FEEIE: FIFO exception interrupt enable - \param[out] none - \retval none -*/ -void dma_interrupt_disable(uint32_t dma_periph,dma_channel_enum channelx,uint32_t source) -{ - if(DMA_CHXFCTL_FEEIE != source){ - DMA_CHCTL(dma_periph,channelx) &= ~source; - }else{ - DMA_CHFCTL(dma_periph,channelx) &= ~source; - } -} - -/*! \brief set DMA peripheral base address \param[in] dma_periph: DMAx(x=0,1) \arg DMAx(x=0,1) @@ -395,7 +255,7 @@ void dma_interrupt_disable(uint32_t dma_periph,dma_channel_enum channelx,uint32_ \param[out] none \retval none */ -void dma_periph_address_config(uint32_t dma_periph,dma_channel_enum channelx,uint32_t address) +void dma_periph_address_config(uint32_t dma_periph, dma_channel_enum channelx, uint32_t address) { DMA_CHPADDR(dma_periph,channelx) = address; } @@ -404,14 +264,14 @@ void dma_periph_address_config(uint32_t dma_periph,dma_channel_enum channelx,uin \brief set DMA Memory0 base address \param[in] dma_periph: DMAx(x=0,1) \arg DMAx(x=0,1) - \param[in] channelx: specify which DMA channel to set Memory base address + \param[in] channelx: specify which DMA channel to set Memory base address \arg DMA_CHx(x=0..7) \param[in] memory_flag: DMA_MEMORY_x(x=0,1) \param[in] address: Memory base address \param[out] none \retval none */ -void dma_memory_address_config(uint32_t dma_periph,dma_channel_enum channelx,uint8_t memory_flag,uint32_t address) +void dma_memory_address_config(uint32_t dma_periph, dma_channel_enum channelx, uint8_t memory_flag, uint32_t address) { if(memory_flag){ DMA_CHM1ADDR(dma_periph,channelx) = address; @@ -430,7 +290,7 @@ void dma_memory_address_config(uint32_t dma_periph,dma_channel_enum channelx,uin \param[out] none \retval none */ -void dma_transfer_number_config(uint32_t dma_periph,dma_channel_enum channelx,uint32_t number) +void dma_transfer_number_config(uint32_t dma_periph, dma_channel_enum channelx, uint32_t number) { DMA_CHCNT(dma_periph,channelx) = number; } @@ -439,12 +299,12 @@ void dma_transfer_number_config(uint32_t dma_periph,dma_channel_enum channelx,ui \brief get the number of remaining data to be transferred by the DMA \param[in] dma_periph: DMAx(x=0,1) \arg DMAx(x=0,1) - \param[in] channelx: specify which DMA channel to set number + \param[in] channelx: specify which DMA channel to set number \arg DMA_CHx(x=0..7) \param[out] none - \retval uint32_t: the number of remaining data to be transferred by the DMA + \retval uint32_t: the number of remaining data to be transferred by the DMA */ -uint32_t dma_transfer_number_get(uint32_t dma_periph,dma_channel_enum channelx) +uint32_t dma_transfer_number_get(uint32_t dma_periph, dma_channel_enum channelx) { return (uint32_t)DMA_CHCNT(dma_periph,channelx); } @@ -456,14 +316,15 @@ uint32_t dma_transfer_number_get(uint32_t dma_periph,dma_channel_enum channelx) \param[in] channelx: specify which DMA channel \arg DMA_CHx(x=0..7) \param[in] priority: priority Level of this channel + only one parameter can be selected which is shown as below: \arg DMA_PRIORITY_LOW: low priority \arg DMA_PRIORITY_MEDIUM: medium priority \arg DMA_PRIORITY_HIGH: high priority \arg DMA_PRIORITY_ULTRA_HIGH: ultra high priority \param[out] none - \retval none + \retval none */ -void dma_priority_config(uint32_t dma_periph,dma_channel_enum channelx,uint32_t priority) +void dma_priority_config(uint32_t dma_periph, dma_channel_enum channelx, uint32_t priority) { uint32_t ctl; /* acquire DMA_CHxCTL register */ @@ -488,7 +349,7 @@ void dma_priority_config(uint32_t dma_periph,dma_channel_enum channelx,uint32_t \param[out] none \retval none */ -void dma_memory_burst_beats_config (uint32_t dma_periph,dma_channel_enum channelx,uint32_t mbeat) +void dma_memory_burst_beats_config (uint32_t dma_periph, dma_channel_enum channelx, uint32_t mbeat) { uint32_t ctl; /* acquire DMA_CHxCTL register */ @@ -506,6 +367,7 @@ void dma_memory_burst_beats_config (uint32_t dma_periph,dma_channel_enum channel \param[in] channelx: specify which DMA channel \arg DMA_CHx(x=0..7) \param[in] pbeat: transfer burst beats + only one parameter can be selected which is shown as below: \arg DMA_PERIPH_BURST_SINGLE: peripheral transfer single burst \arg DMA_PERIPH_BURST_4_BEAT: peripheral transfer 4-beat burst \arg DMA_PERIPH_BURST_8_BEAT: peripheral transfer 8-beat burst @@ -513,7 +375,7 @@ void dma_memory_burst_beats_config (uint32_t dma_periph,dma_channel_enum channel \param[out] none \retval none */ -void dma_periph_burst_beats_config (uint32_t dma_periph,dma_channel_enum channelx,uint32_t pbeat) +void dma_periph_burst_beats_config (uint32_t dma_periph, dma_channel_enum channelx, uint32_t pbeat) { uint32_t ctl; /* acquire DMA_CHxCTL register */ @@ -531,13 +393,14 @@ void dma_periph_burst_beats_config (uint32_t dma_periph,dma_channel_enum channel \param[in] channelx: specify which DMA channel \arg DMA_CHx(x=0..7) \param[in] msize: transfer data size of memory + only one parameter can be selected which is shown as below: \arg DMA_MEMORY_WIDTH_8BIT: transfer data size of memory is 8-bit \arg DMA_MEMORY_WIDTH_16BIT: transfer data size of memory is 16-bit \arg DMA_MEMORY_WIDTH_32BIT: transfer data size of memory is 32-bit \param[out] none \retval none */ -void dma_memory_width_config(uint32_t dma_periph,dma_channel_enum channelx,uint32_t msize) +void dma_memory_width_config(uint32_t dma_periph, dma_channel_enum channelx, uint32_t msize) { uint32_t ctl; /* acquire DMA_CHxCTL register */ @@ -549,19 +412,20 @@ void dma_memory_width_config(uint32_t dma_periph,dma_channel_enum channelx,uint3 } /*! - \brief configure transfer data size of peripheral + \brief configure transfer data size of peripheral \param[in] dma_periph: DMAx(x=0,1) \arg DMAx(x=0,1) - \param[in] channelx: specify which DMA channel + \param[in] channelx: specify which DMA channel \arg DMA_CHx(x=0..7) \param[in] msize: transfer data size of peripheral + only one parameter can be selected which is shown as below: \arg DMA_PERIPHERAL_WIDTH_8BIT: transfer data size of peripheral is 8-bit \arg DMA_PERIPHERAL_WIDTH_16BIT: transfer data size of peripheral is 16-bit \arg DMA_PERIPHERAL_WIDTH_32BIT: transfer data size of peripheral is 32-bit \param[out] none \retval none */ -void dma_periph_width_config (uint32_t dma_periph,dma_channel_enum channelx,uint32_t psize) +void dma_periph_width_config (uint32_t dma_periph, dma_channel_enum channelx, uint32_t psize) { uint32_t ctl; /* acquire DMA_CHxCTL register */ @@ -576,15 +440,16 @@ void dma_periph_width_config (uint32_t dma_periph,dma_channel_enum channelx,uint \brief configure memory address generation generation_algorithm \param[in] dma_periph: DMAx(x=0,1) \arg DMAx(x=0,1) - \param[in] channelx: specify which DMA channel + \param[in] channelx: specify which DMA channel \arg DMA_CHx(x=0..7) \param[in] generation_algorithm: the address generation algorithm + only one parameter can be selected which is shown as below: \arg DMA_MEMORY_INCREASE_ENABLE: next address of memory is increasing address mode \arg DMA_MEMORY_INCREASE_DISABLE: next address of memory is fixed address mode \param[out] none \retval none */ -void dma_memory_address_generation_config(uint32_t dma_periph,dma_channel_enum channelx,uint8_t generation_algorithm) +void dma_memory_address_generation_config(uint32_t dma_periph, dma_channel_enum channelx, uint8_t generation_algorithm) { if(DMA_MEMORY_INCREASE_ENABLE == generation_algorithm){ DMA_CHCTL(dma_periph,channelx) |= DMA_CHXCTL_MNAGA; @@ -594,19 +459,20 @@ void dma_memory_address_generation_config(uint32_t dma_periph,dma_channel_enum c } /*! - \brief configure peripheral address generation generation_algorithm + \brief configure peripheral address generation_algorithm \param[in] dma_periph: DMAx(x=0,1) \arg DMAx(x=0,1) - \param[in] channelx: specify which DMA channel + \param[in] channelx: specify which DMA channel \arg DMA_CHx(x=0..7) \param[in] generation_algorithm: the address generation algorithm + only one parameter can be selected which is shown as below: \arg DMA_PERIPH_INCREASE_ENABLE: next address of peripheral is increasing address mode \arg DMA_PERIPH_INCREASE_DISABLE: next address of peripheral is fixed address mode \arg DMA_PERIPH_INCREASE_FIX: increasing steps of peripheral address is fixed \param[out] none \retval none */ -void dma_peripheral_address_generation_config(uint32_t dma_periph,dma_channel_enum channelx,uint8_t generation_algorithm) +void dma_peripheral_address_generation_config(uint32_t dma_periph, dma_channel_enum channelx, uint8_t generation_algorithm) { if(DMA_PERIPH_INCREASE_ENABLE == generation_algorithm){ DMA_CHCTL(dma_periph,channelx) |= DMA_CHXCTL_PNAGA; @@ -622,12 +488,12 @@ void dma_peripheral_address_generation_config(uint32_t dma_periph,dma_channel_en \brief enable DMA circulation mode \param[in] dma_periph: DMAx(x=0,1) \arg DMAx(x=0,1) - \param[in] channelx: specify which DMA channel + \param[in] channelx: specify which DMA channel \arg DMA_CHx(x=0..7) \param[out] none - \retval none + \retval none */ -void dma_circulation_enable(uint32_t dma_periph,dma_channel_enum channelx) +void dma_circulation_enable(uint32_t dma_periph, dma_channel_enum channelx) { DMA_CHCTL(dma_periph,channelx) |= DMA_CHXCTL_CMEN; } @@ -636,30 +502,59 @@ void dma_circulation_enable(uint32_t dma_periph,dma_channel_enum channelx) \brief disable DMA circulation mode \param[in] dma_periph: DMAx(x=0,1) \arg DMAx(x=0,1) - \param[in] channelx: specify which DMA channel + \param[in] channelx: specify which DMA channel \arg DMA_CHx(x=0..7) \param[out] none - \retval none + \retval none */ -void dma_circulation_disable(uint32_t dma_periph,dma_channel_enum channelx) +void dma_circulation_disable(uint32_t dma_periph, dma_channel_enum channelx) { DMA_CHCTL(dma_periph,channelx) &= ~DMA_CHXCTL_CMEN; } /*! + \brief enable DMA channel + \param[in] dma_periph: DMAx(x=0,1) + \arg DMAx(x=0,1) + \param[in] channelx: specify which DMA channel + \arg DMA_CHx(x=0..7) + \param[out] none + \retval none +*/ +void dma_channel_enable(uint32_t dma_periph, dma_channel_enum channelx) +{ + DMA_CHCTL(dma_periph,channelx) |= DMA_CHXCTL_CHEN; +} + +/*! + \brief disable DMA channel + \param[in] dma_periph: DMAx(x=0,1) + \arg DMAx(x=0,1) + \param[in] channelx: specify which DMA channel + \arg DMA_CHx(x=0..7) + \param[out] none + \retval none +*/ +void dma_channel_disable(uint32_t dma_periph, dma_channel_enum channelx) +{ + DMA_CHCTL(dma_periph,channelx) &= ~DMA_CHXCTL_CHEN; +} + +/*! \brief configure the direction of data transfer on the channel \param[in] dma_periph: DMAx(x=0,1) \arg DMAx(x=0,1) - \param[in] channelx: specify which DMA channel + \param[in] channelx: specify which DMA channel \arg DMA_CHx(x=0..7) \param[in] direction: specify the direction of data transfer + only one parameter can be selected which is shown as below: \arg DMA_PERIPH_TO_MEMORY: read from peripheral and write to memory \arg DMA_MEMORY_TO_PERIPH: read from memory and write to peripheral \arg DMA_MEMORY_TO_MEMORY: read from memory and write to memory \param[out] none \retval none */ -void dma_transfer_direction_config(uint32_t dma_periph,dma_channel_enum channelx,uint8_t direction) +void dma_transfer_direction_config(uint32_t dma_periph, dma_channel_enum channelx, uint8_t direction) { uint32_t ctl; /* acquire DMA_CHxCTL register */ @@ -667,50 +562,63 @@ void dma_transfer_direction_config(uint32_t dma_periph,dma_channel_enum channelx /* assign regiser */ ctl &= ~DMA_CHXCTL_TM; ctl |= direction; - + DMA_CHCTL(dma_periph,channelx) = ctl; } /*! - \brief enable DMA channel + \brief DMA switch buffer mode config \param[in] dma_periph: DMAx(x=0,1) \arg DMAx(x=0,1) - \param[in] channelx: specify which DMA channel + \param[in] channelx: specify which DMA channel \arg DMA_CHx(x=0..7) + \param[in] memory1_addr: memory1 base address + \param[in] memory_select: DMA_MEMORY_0 or DMA_MEMORY_1 \param[out] none - \retval none + \retval none */ -void dma_channel_enable(uint32_t dma_periph,dma_channel_enum channelx) +void dma_switch_buffer_mode_config(uint32_t dma_periph, dma_channel_enum channelx, uint32_t memory1_addr, uint32_t memory_select) { - DMA_CHCTL(dma_periph,channelx) |= DMA_CHXCTL_CHEN; + /* configure memory1 base address */ + DMA_CHM1ADDR(dma_periph,channelx) = memory1_addr; + + if(DMA_MEMORY_0 == memory_select){ + DMA_CHCTL(dma_periph,channelx) &= ~DMA_CHXCTL_MBS; + }else{ + DMA_CHCTL(dma_periph,channelx) |= DMA_CHXCTL_MBS; + } } /*! - \brief disable DMA channel + \brief DMA using memory get \param[in] dma_periph: DMAx(x=0,1) \arg DMAx(x=0,1) - \param[in] channelx: specify which DMA channel + \param[in] channelx: specify which DMA channel \arg DMA_CHx(x=0..7) \param[out] none - \retval none + \retval the using memory */ -void dma_channel_disable(uint32_t dma_periph,dma_channel_enum channelx) +uint32_t dma_using_memory_get(uint32_t dma_periph, dma_channel_enum channelx) { - DMA_CHCTL(dma_periph,channelx) &= ~DMA_CHXCTL_CHEN; + if((DMA_CHCTL(dma_periph,channelx)) & DMA_CHXCTL_MBS){ + return DMA_MEMORY_1; + }else{ + return DMA_MEMORY_0; + } } /*! \brief DMA channel peripheral select \param[in] dma_periph: DMAx(x=0,1) \arg DMAx(x=0,1) - \param[in] channelx: specify which DMA channel + \param[in] channelx: specify which DMA channel \arg DMA_CHx(x=0..7) \param[in] sub_periph: specify DMA channel peripheral \arg DMA_SUBPERIx(x=0..7) \param[out] none - \retval none + \retval none */ -void dma_channel_subperipheral_select(uint32_t dma_periph,dma_channel_enum channelx,dma_subperipheral_enum sub_periph) +void dma_channel_subperipheral_select(uint32_t dma_periph, dma_channel_enum channelx, dma_subperipheral_enum sub_periph) { uint32_t ctl; /* acquire DMA_CHxCTL register */ @@ -718,30 +626,29 @@ void dma_channel_subperipheral_select(uint32_t dma_periph,dma_channel_enum chann /* assign regiser */ ctl &= ~DMA_CHXCTL_PERIEN; ctl |= ((uint32_t)sub_periph << CHXCTL_PERIEN_OFFSET); - + DMA_CHCTL(dma_periph,channelx) = ctl; } /*! - \brief DMA switch buffer mode config + \brief DMA flow controller configure \param[in] dma_periph: DMAx(x=0,1) \arg DMAx(x=0,1) - \param[in] channelx: specify which DMA channel + \param[in] channelx: specify which DMA channel \arg DMA_CHx(x=0..7) - \param[in] memory1_addr: memory1 base address - \param[in] memory_select: DMA_MEMORY_0 or DMA_MEMORY_1 + \param[in] controller: specify DMA flow controler + only one parameter can be selected which is shown as below: + \arg DMA_FLOW_CONTROLLER_DMA: DMA is the flow controller + \arg DMA_FLOW_CONTROLLER_PERI: peripheral is the flow controller \param[out] none - \retval none + \retval none */ -void dma_switch_buffer_mode_config(uint32_t dma_periph,dma_channel_enum channelx,uint32_t memory1_addr,uint32_t memory_select) +void dma_flow_controller_config(uint32_t dma_periph, dma_channel_enum channelx, uint32_t controller) { - /* configure memory1 base address */ - DMA_CHM1ADDR(dma_periph,channelx) = memory1_addr; - - if(DMA_MEMORY_0 == memory_select){ - DMA_CHCTL(dma_periph,channelx) &= ~DMA_CHXCTL_MBS; + if(DMA_FLOW_CONTROLLER_DMA == controller){ + DMA_CHCTL(dma_periph,channelx) &= ~DMA_CHXCTL_TFCS; }else{ - DMA_CHCTL(dma_periph,channelx) |= DMA_CHXCTL_MBS; + DMA_CHCTL(dma_periph,channelx) |= DMA_CHXCTL_TFCS; } } @@ -749,13 +656,13 @@ void dma_switch_buffer_mode_config(uint32_t dma_periph,dma_channel_enum channelx \brief DMA switch buffer mode enable \param[in] dma_periph: DMAx(x=0,1) \arg DMAx(x=0,1) - \param[in] channelx: specify which DMA channel + \param[in] channelx: specify which DMA channel \arg DMA_CHx(x=0..7) \param[in] newvalue: ENABLE or DISABLE \param[out] none - \retval none + \retval none */ -void dma_switch_buffer_mode_enable(uint32_t dma_periph,dma_channel_enum channelx,ControlStatus newvalue) +void dma_switch_buffer_mode_enable(uint32_t dma_periph, dma_channel_enum channelx, ControlStatus newvalue) { if(ENABLE == newvalue){ /* switch buffer mode enable */ @@ -767,54 +674,232 @@ void dma_switch_buffer_mode_enable(uint32_t dma_periph,dma_channel_enum channelx } /*! - \brief DMA using memory get + \brief DMA FIFO status get \param[in] dma_periph: DMAx(x=0,1) \arg DMAx(x=0,1) - \param[in] channelx: specify which DMA channel + \param[in] channelx: specify which DMA channel \arg DMA_CHx(x=0..7) \param[out] none - \retval the using memory + \retval the using memory */ -uint32_t dma_using_memory_get(uint32_t dma_periph,dma_channel_enum channelx) +uint32_t dma_fifo_status_get(uint32_t dma_periph, dma_channel_enum channelx) { - if((DMA_CHCTL(dma_periph,channelx)) & DMA_CHXCTL_MBS){ - return DMA_MEMORY_1; + return (DMA_CHFCTL(dma_periph,channelx) & DMA_CHXFCTL_FCNT); +} + +/*! + \brief get DMA flag is set or not + \param[in] dma_periph: DMAx(x=0,1) + \arg DMAx(x=0,1) + \param[in] channelx: specify which DMA channel to get flag + \arg DMA_CHx(x=0..7) + \param[in] flag: specify get which flag + only one parameter can be selected which is shown as below: + \arg DMA_FLAG_FEE: FIFO error and exception flag + \arg DMA_FLAG_SDE: single data mode exception flag + \arg DMA_FLAG_TAE: transfer access error flag + \arg DMA_FLAG_HTF: half transfer finish flag + \arg DMA_FLAG_FTF: full transger finish flag + \param[out] none + \retval FlagStatus: SET or RESET +*/ +FlagStatus dma_flag_get(uint32_t dma_periph, dma_channel_enum channelx, uint32_t flag) +{ + if(channelx < DMA_CH4){ + if(DMA_INTF0(dma_periph) & DMA_FLAG_ADD(flag,channelx)){ + return SET; + }else{ + return RESET; + } }else{ - return DMA_MEMORY_0; + channelx -= (dma_channel_enum)4; + if(DMA_INTF1(dma_periph) & DMA_FLAG_ADD(flag,channelx)){ + return SET; + }else{ + return RESET; + } } } /*! - \brief DMA flow controller configure + \brief clear DMA a channel flag \param[in] dma_periph: DMAx(x=0,1) \arg DMAx(x=0,1) - \param[in] channelx: specify which DMA channel + \param[in] channelx: specify which DMA channel to get flag \arg DMA_CHx(x=0..7) - \param[in] controller: specify DMA flow controler - \arg DMA_FLOW_CONTROLLER_DMA: DMA is the flow controller - \arg DMA_FLOW_CONTROLLER_PERI: peripheral is the flow controller + \param[in] flag: specify get which flag + only one parameter can be selected which is shown as below: + \arg DMA_FLAG_FEE: FIFO error and exception flag + \arg DMA_FLAG_SDE: single data mode exception flag + \arg DMA_FLAG_TAE: transfer access error flag + \arg DMA_FLAG_HTF: half transfer finish flag + \arg DMA_FLAG_FTF: full transger finish flag \param[out] none \retval none */ -void dma_flow_controller_config(uint32_t dma_periph,dma_channel_enum channelx,uint32_t controller) +void dma_flag_clear(uint32_t dma_periph, dma_channel_enum channelx, uint32_t flag) { - if(DMA_FLOW_CONTROLLER_DMA == controller){ - DMA_CHCTL(dma_periph,channelx) &= ~DMA_CHXCTL_TFCS; + if(channelx < DMA_CH4){ + DMA_INTC0(dma_periph) |= DMA_FLAG_ADD(flag,channelx); }else{ - DMA_CHCTL(dma_periph,channelx) |= DMA_CHXCTL_TFCS; + channelx -= (dma_channel_enum)4; + DMA_INTC1(dma_periph) |= DMA_FLAG_ADD(flag,channelx); } } /*! - \brief DMA FIFO status get + \brief get DMA interrupt flag is set or not \param[in] dma_periph: DMAx(x=0,1) \arg DMAx(x=0,1) - \param[in] channelx: specify which DMA channel + \param[in] channelx: specify which DMA channel to get interrupt flag \arg DMA_CHx(x=0..7) + \param[in] interrupt: specify get which flag + only one parameter can be selected which is shown as below: + \arg DMA_INT_FLAG_FEE: FIFO error and exception flag + \arg DMA_INT_FLAG_SDE: single data mode exception flag + \arg DMA_INT_FLAG_TAE: transfer access error flag + \arg DMA_INT_FLAG_HTF: half transfer finish flag + \arg DMA_INT_FLAG_FTF: full transger finish flag \param[out] none - \retval the using memory + \retval FlagStatus: SET or RESET */ -uint32_t dma_fifo_status_get(uint32_t dma_periph,dma_channel_enum channelx) +FlagStatus dma_interrupt_flag_get(uint32_t dma_periph, dma_channel_enum channelx, uint32_t interrupt) { - return (DMA_CHFCTL(dma_periph,channelx) & DMA_CHXFCTL_FCNT); + uint32_t interrupt_enable = 0U,interrupt_flag = 0U; + dma_channel_enum channel_flag_offset = channelx; + if(channelx < DMA_CH4){ + switch(interrupt){ + case DMA_INTF_FEEIF: + interrupt_flag = DMA_INTF0(dma_periph) & DMA_FLAG_ADD(interrupt,channelx); + interrupt_enable = DMA_CHFCTL(dma_periph,channelx) & DMA_CHXFCTL_FEEIE; + break; + case DMA_INTF_SDEIF: + interrupt_flag = DMA_INTF0(dma_periph) & DMA_FLAG_ADD(interrupt,channelx); + interrupt_enable = DMA_CHCTL(dma_periph,channelx) & DMA_CHXCTL_SDEIE; + break; + case DMA_INTF_TAEIF: + interrupt_flag = DMA_INTF0(dma_periph) & DMA_FLAG_ADD(interrupt,channelx); + interrupt_enable = DMA_CHCTL(dma_periph,channelx) & DMA_CHXCTL_TAEIE; + break; + case DMA_INTF_HTFIF: + interrupt_flag = DMA_INTF0(dma_periph) & DMA_FLAG_ADD(interrupt,channelx); + interrupt_enable = DMA_CHCTL(dma_periph,channelx) & DMA_CHXCTL_HTFIE; + break; + case DMA_INTF_FTFIF: + interrupt_flag = (DMA_INTF0(dma_periph) & DMA_FLAG_ADD(interrupt,channelx)); + interrupt_enable = (DMA_CHCTL(dma_periph,channelx) & DMA_CHXCTL_FTFIE); + break; + default: + break; + } + }else{ + channel_flag_offset -= (dma_channel_enum)4; + switch(interrupt){ + case DMA_INTF_FEEIF: + interrupt_flag = DMA_INTF1(dma_periph) & DMA_FLAG_ADD(interrupt,channel_flag_offset); + interrupt_enable = DMA_CHFCTL(dma_periph,channelx) & DMA_CHXFCTL_FEEIE; + break; + case DMA_INTF_SDEIF: + interrupt_flag = DMA_INTF1(dma_periph) & DMA_FLAG_ADD(interrupt,channel_flag_offset); + interrupt_enable = DMA_CHCTL(dma_periph,channelx) & DMA_CHXCTL_SDEIE; + break; + case DMA_INTF_TAEIF: + interrupt_flag = DMA_INTF1(dma_periph) & DMA_FLAG_ADD(interrupt,channel_flag_offset); + interrupt_enable = DMA_CHCTL(dma_periph,channelx) & DMA_CHXCTL_TAEIE; + break; + case DMA_INTF_HTFIF: + interrupt_flag = DMA_INTF1(dma_periph) & DMA_FLAG_ADD(interrupt,channel_flag_offset); + interrupt_enable = DMA_CHCTL(dma_periph,channelx) & DMA_CHXCTL_HTFIE; + break; + case DMA_INTF_FTFIF: + interrupt_flag = DMA_INTF1(dma_periph) & DMA_FLAG_ADD(interrupt,channel_flag_offset); + interrupt_enable = DMA_CHCTL(dma_periph,channelx) & DMA_CHXCTL_FTFIE; + break; + default: + break; + } + } + + if(interrupt_flag && interrupt_enable){ + return SET; + }else{ + return RESET; + } } + +/*! + \brief clear DMA a channel interrupt flag + \param[in] dma_periph: DMAx(x=0,1) + \arg DMAx(x=0,1) + \param[in] channelx: specify which DMA channel to clear interrupt flag + \arg DMA_CHx(x=0..7) + \param[in] interrupt: specify get which flag + only one parameter can be selected which is shown as below: + \arg DMA_INT_FLAG_FEE: FIFO error and exception flag + \arg DMA_INT_FLAG_SDE: single data mode exception flag + \arg DMA_INT_FLAG_TAE: transfer access error flag + \arg DMA_INT_FLAG_HTF: half transfer finish flag + \arg DMA_INT_FLAG_FTF: full transger finish flag + \param[out] none + \retval none +*/ +void dma_interrupt_flag_clear(uint32_t dma_periph, dma_channel_enum channelx, uint32_t interrupt) +{ + if(channelx < DMA_CH4){ + DMA_INTC0(dma_periph) |= DMA_FLAG_ADD(interrupt,channelx); + }else{ + channelx -= (dma_channel_enum)4; + DMA_INTC1(dma_periph) |= DMA_FLAG_ADD(interrupt,channelx); + } +} + +/*! + \brief enable DMA interrupt + \param[in] dma_periph: DMAx(x=0,1) + \arg DMAx(x=0,1) + \param[in] channelx: specify which DMA channel + \arg DMA_CHx(x=0..7) + \param[in] source: specify which interrupt to enbale + one or more parameters can be selected which are shown as below: + \arg DMA_CHXCTL_SDEIE: single data mode exception interrupt enable + \arg DMA_CHXCTL_TAEIE: tranfer access error interrupt enable + \arg DMA_CHXCTL_HTFIE: half transfer finish interrupt enable + \arg DMA_CHXCTL_FTFIE: full transfer finish interrupt enable + \arg DMA_CHXFCTL_FEEIE: FIFO exception interrupt enable + \param[out] none + \retval none +*/ +void dma_interrupt_enable(uint32_t dma_periph, dma_channel_enum channelx, uint32_t source) +{ + if(DMA_CHXFCTL_FEEIE != source){ + DMA_CHCTL(dma_periph,channelx) |= source; + }else{ + DMA_CHFCTL(dma_periph,channelx) |= source; + } +} + +/*! + \brief disable DMA interrupt + \param[in] dma_periph: DMAx(x=0,1) + \arg DMAx(x=0,1) + \param[in] channelx: specify which DMA channel + \arg DMA_CHx(x=0..7) + \param[in] source: specify which interrupt to disbale + one or more parameters can be selected which are shown as below: + \arg DMA_CHXCTL_SDEIE: single data mode exception interrupt enable + \arg DMA_CHXCTL_TAEIE: tranfer access error interrupt enable + \arg DMA_CHXCTL_HTFIE: half transfer finish interrupt enable + \arg DMA_CHXCTL_FTFIE: full transfer finish interrupt enable + \arg DMA_CHXFCTL_FEEIE: FIFO exception interrupt enable + \param[out] none + \retval none +*/ +void dma_interrupt_disable(uint32_t dma_periph, dma_channel_enum channelx, uint32_t source) +{ + if(DMA_CHXFCTL_FEEIE != source){ + DMA_CHCTL(dma_periph,channelx) &= ~source; + }else{ + DMA_CHFCTL(dma_periph,channelx) &= ~source; + } +} + diff --git a/bsp/gd32450z-eval/Libraries/GD32F4xx_standard_peripheral/Source/gd32f4xx_enet.c b/bsp/gd32450z-eval/Libraries/GD32F4xx_standard_peripheral/Source/gd32f4xx_enet.c index 55ed8a9145..456e476fd8 100644 --- a/bsp/gd32450z-eval/Libraries/GD32F4xx_standard_peripheral/Source/gd32f4xx_enet.c +++ b/bsp/gd32450z-eval/Libraries/GD32F4xx_standard_peripheral/Source/gd32f4xx_enet.c @@ -1,24 +1,49 @@ /*! - \file gd32f4xx_enet.c - \brief ENET driver + \file gd32f4xx_enet.c + \brief ENET driver + + \version 2016-08-15, V1.0.0, firmware for GD32F4xx + \version 2018-12-12, V2.0.0, firmware for GD32F4xx + \version 2020-09-30, V2.1.0, firmware for GD32F4xx */ /* - Copyright (C) 2016 GigaDevice + Copyright (c) 2020, GigaDevice Semiconductor Inc. + + Redistribution and use in source and binary forms, with or without modification, +are permitted provided that the following conditions are met: + + 1. Redistributions of source code must retain the above copyright notice, this + list of conditions and the following disclaimer. + 2. Redistributions in binary form must reproduce the above copyright notice, + this list of conditions and the following disclaimer in the documentation + and/or other materials provided with the distribution. + 3. Neither the name of the copyright holder nor the names of its contributors + may be used to endorse or promote products derived from this software without + specific prior written permission. - 2016-08-15, V1.0.1, firmware for GD32F4xx + THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED +WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. +IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, +INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT +NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR +PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, +WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY +OF SUCH DAMAGE. */ #include "gd32f4xx_enet.h" #if defined (__CC_ARM) /*!< ARM compiler */ -__align(4) +__align(4) enet_descriptors_struct rxdesc_tab[ENET_RXBUF_NUM]; /*!< ENET RxDMA descriptor */ -__align(4) +__align(4) enet_descriptors_struct txdesc_tab[ENET_TXBUF_NUM]; /*!< ENET TxDMA descriptor */ -__align(4) +__align(4) uint8_t rx_buff[ENET_RXBUF_NUM][ENET_RXBUF_SIZE]; /*!< ENET receive buffer */ -__align(4) +__align(4) uint8_t tx_buff[ENET_TXBUF_NUM][ENET_TXBUF_SIZE]; /*!< ENET transmit buffer */ #elif defined ( __ICCARM__ ) /*!< IAR compiler */ @@ -31,15 +56,11 @@ uint8_t rx_buff[ENET_RXBUF_NUM][ENET_RXBUF_SIZE]; /*!< ENET receive bu #pragma data_alignment=4 uint8_t tx_buff[ENET_TXBUF_NUM][ENET_TXBUF_SIZE]; /*!< ENET transmit buffer */ -#elif defined ( __GNUC__ ) -__attribute__((aligned(4))) -enet_descriptors_struct rxdesc_tab[ENET_RXBUF_NUM]; /*!< ENET RxDMA descriptor */ -__attribute__((aligned(4))) -enet_descriptors_struct txdesc_tab[ENET_TXBUF_NUM]; /*!< ENET TxDMA descriptor */ -__attribute__((aligned(4))) -uint8_t rx_buff[ENET_RXBUF_NUM][ENET_RXBUF_SIZE]; /*!< ENET receive buffer */ -__attribute__((aligned(4))) -uint8_t tx_buff[ENET_TXBUF_NUM][ENET_TXBUF_SIZE]; /*!< ENET transmit buffer */ +#elif defined (__GNUC__) /* GNU Compiler */ +enet_descriptors_struct rxdesc_tab[ENET_RXBUF_NUM] __attribute__ ((aligned (4))); /*!< ENET RxDMA descriptor */ +enet_descriptors_struct txdesc_tab[ENET_TXBUF_NUM] __attribute__ ((aligned (4))); /*!< ENET TxDMA descriptor */ +uint8_t rx_buff[ENET_RXBUF_NUM][ENET_RXBUF_SIZE] __attribute__ ((aligned (4))); /*!< ENET receive buffer */ +uint8_t tx_buff[ENET_TXBUF_NUM][ENET_TXBUF_SIZE] __attribute__ ((aligned (4))); /*!< ENET transmit buffer */ #endif /* __CC_ARM */ @@ -53,19 +74,31 @@ enet_descriptors_struct *dma_current_ptp_rxdesc = NULL; /* init structure parameters for ENET initialization */ static enet_initpara_struct enet_initpara ={0,0,0,0,0,0,0,0,0,0,0,0,0,0,0}; - +static uint32_t enet_unknow_err = 0U; /* array of register offset for debug information get */ static const uint16_t enet_reg_tab[] = { 0x0000, 0x0004, 0x0008, 0x000C, 0x0010, 0x0014, 0x0018, 0x001C, 0x0028, 0x002C, 0x0034, 0x0038, 0x003C, 0x0040, 0x0044, 0x0048, 0x004C, 0x0050, 0x0054, 0x0058, 0x005C, 0x1080, - -0x0100, 0x0104, 0x0108, 0x010C, 0x0110, 0x014C, 0x0150, 0x0168, 0x0194, 0x0198, 0x01C4, - -0x0700, 0x0704,0x0708, 0x070C, 0x0710, 0x0714, 0x0718, 0x071C, 0x0720, 0x0728, 0x072C, - + +0x0100, 0x0104, 0x0108, 0x010C, 0x0110, 0x014C, 0x0150, 0x0168, 0x0194, 0x0198, 0x01C4, + +0x0700, 0x0704,0x0708, 0x070C, 0x0710, 0x0714, 0x0718, 0x071C, 0x0720, 0x0728, 0x072C, + 0x1000, 0x1004, 0x1008, 0x100C, 0x1010, 0x1014, 0x1018, 0x101C, 0x1020, 0x1024, 0x1048, 0x104C, 0x1050, 0x1054}; +/* initialize ENET peripheral with generally concerned parameters, call it by enet_init() */ +static void enet_default_init(void); +#ifdef USE_DELAY +/* user can provide more timing precise _ENET_DELAY_ function */ +#define _ENET_DELAY_ delay_ms +#else +/* insert a delay time */ +static void enet_delay(uint32_t ncount); +/* default _ENET_DELAY_ function with less precise timing */ +#define _ENET_DELAY_ enet_delay +#endif + /*! \brief deinitialize the ENET, and reset structure parameters for ENET initialization @@ -82,16 +115,16 @@ void enet_deinit(void) /*! \brief configure the parameters which are usually less cared for initialization - note -- this function must be called before enet_init(), otherwise + note -- this function must be called before enet_init(), otherwise configuration will be no effect - \param[in] option: different function option, which is related to several parameters, - only one parameter can be selected which is shown as below, refer to enet_option_enum + \param[in] option: different function option, which is related to several parameters, refer to enet_option_enum + only one parameter can be selected which is shown as below \arg FORWARD_OPTION: choose to configure the frame forward related parameters \arg DMABUS_OPTION: choose to configure the DMA bus mode related parameters \arg DMA_MAXBURST_OPTION: choose to configure the DMA max burst related parameters \arg DMA_ARBITRATION_OPTION: choose to configure the DMA arbitration related parameters \arg STORE_OPTION: choose to configure the store forward mode related parameters - \arg DMA_OPTION: choose to configure the DMA descriptor related parameters + \arg DMA_OPTION: choose to configure the DMA descriptor related parameters \arg VLAN_OPTION: choose to configure vlan related parameters \arg FLOWCTL_OPTION: choose to configure flow control related parameters \arg HASHH_OPTION: choose to configure hash high @@ -100,8 +133,8 @@ void enet_deinit(void) \arg HALFDUPLEX_OPTION: choose to configure halfduplex mode related parameters \arg TIMER_OPTION: choose to configure time counter related parameters \arg INTERFRAMEGAP_OPTION: choose to configure the inter frame gap related parameters - \param[in] para: the related parameters according to the option - all the related parameters should be configured which are shown as below + \param[in] para: the related parameters according to the option + all the related parameters should be configured which are shown as below FORWARD_OPTION related parameters: - ENET_AUTO_PADCRC_DROP_ENABLE/ ENET_AUTO_PADCRC_DROP_DISABLE ; - ENET_TYPEFRAME_CRC_DROP_ENABLE/ ENET_TYPEFRAME_CRC_DROP_DISABLE ; @@ -110,7 +143,7 @@ void enet_deinit(void) DMABUS_OPTION related parameters: - ENET_ADDRESS_ALIGN_ENABLE/ ENET_ADDRESS_ALIGN_DISABLE ; - ENET_FIXED_BURST_ENABLE/ ENET_FIXED_BURST_DISABLE ; - - ENET_MIXED_BURST_ENABLE/ ENET_MIXED_BURST_DISABLE ; + - ENET_MIXED_BURST_ENABLE/ ENET_MIXED_BURST_DISABLE ; DMA_MAXBURST_OPTION related parameters: - ENET_RXDP_1BEAT/ ENET_RXDP_2BEAT/ ENET_RXDP_4BEAT/ ENET_RXDP_8BEAT/ ENET_RXDP_16BEAT/ ENET_RXDP_32BEAT/ @@ -146,7 +179,7 @@ void enet_deinit(void) FLOWCTL_OPTION related parameters: - MAC_FCTL_PTM(regval) ; - ENET_ZERO_QUANTA_PAUSE_ENABLE/ ENET_ZERO_QUANTA_PAUSE_DISABLE ; - - ENET_PAUSETIME_MINUS4/ ENET_PAUSETIME_MINUS28/ + - ENET_PAUSETIME_MINUS4/ ENET_PAUSETIME_MINUS28/ ENET_PAUSETIME_MINUS144/ENET_PAUSETIME_MINUS256 ; - ENET_MAC0_AND_UNIQUE_ADDRESS_PAUSEDETECT/ ENET_UNIQUE_PAUSEDETECT ; - ENET_RX_FLOWCONTROL_ENABLE/ ENET_RX_FLOWCONTROL_DISABLE ; @@ -180,7 +213,7 @@ void enet_deinit(void) ENET_INTERFRAMEGAP_80BIT/ ENET_INTERFRAMEGAP_72BIT/ ENET_INTERFRAMEGAP_64BIT/ ENET_INTERFRAMEGAP_56BIT/ ENET_INTERFRAMEGAP_48BIT/ ENET_INTERFRAMEGAP_40BIT . - \param[out] none + \param[out] none \retval none */ void enet_initpara_config(enet_option_enum option, uint32_t para) @@ -214,11 +247,11 @@ void enet_initpara_config(enet_option_enum option, uint32_t para) case DMA_OPTION: /* choose to configure dma_function, and save the configuration parameters */ enet_initpara.option_enable |= (uint32_t)DMA_OPTION; - + #ifndef SELECT_DESCRIPTORS_ENHANCED_MODE para &= ~ENET_ENHANCED_DESCRIPTOR; -#endif /* SELECT_DESCRIPTORS_ENHANCED_MODE */ - +#endif /* SELECT_DESCRIPTORS_ENHANCED_MODE */ + enet_initpara.dma_function = para; break; case VLAN_OPTION: @@ -254,7 +287,7 @@ void enet_initpara_config(enet_option_enum option, uint32_t para) case TIMER_OPTION: /* choose to configure timer_config, and save the configuration parameters */ enet_initpara.option_enable |= (uint32_t)TIMER_OPTION; - enet_initpara.timer_config = para; + enet_initpara.timer_config = para; break; case INTERFRAMEGAP_OPTION: /* choose to configure interframegap, and save the configuration parameters */ @@ -262,34 +295,34 @@ void enet_initpara_config(enet_option_enum option, uint32_t para) enet_initpara.interframegap = para; break; default: - break; - } -} + break; + } +} /*! - \brief initialize ENET peripheral with generally concerned parameters and the less cared + \brief initialize ENET peripheral with generally concerned parameters and the less cared parameters - \param[in] mediamode: PHY mode and mac loopback configurations, only one parameter can be selected - which is shown as below, refer to enet_mediamode_enum + \param[in] mediamode: PHY mode and mac loopback configurations, refer to enet_mediamode_enum + only one parameter can be selected which is shown as below \arg ENET_AUTO_NEGOTIATION: PHY auto negotiation \arg ENET_100M_FULLDUPLEX: 100Mbit/s, full-duplex \arg ENET_100M_HALFDUPLEX: 100Mbit/s, half-duplex \arg ENET_10M_FULLDUPLEX: 10Mbit/s, full-duplex \arg ENET_10M_HALFDUPLEX: 10Mbit/s, half-duplex \arg ENET_LOOPBACKMODE: MAC in loopback mode at the MII - \param[in] checksum: IP frame checksum offload function, only one parameter can be selected - which is shown as below, refer to enet_mediamode_enum + \param[in] checksum: IP frame checksum offload function, refer to enet_mediamode_enum + only one parameter can be selected which is shown as below \arg ENET_NO_AUTOCHECKSUM: disable IP frame checksum function \arg ENET_AUTOCHECKSUM_DROP_FAILFRAMES: enable IP frame checksum function \arg ENET_AUTOCHECKSUM_ACCEPT_FAILFRAMES: enable IP frame checksum function, and the received frame with only payload error but no other errors will not be dropped - \param[in] recept: frame filter function, only one parameter can be selected - which is shown as below, refer to enet_frmrecept_enum + \param[in] recept: frame filter function, refer to enet_frmrecept_enum + only one parameter can be selected which is shown as below \arg ENET_PROMISCUOUS_MODE: promiscuous mode enabled \arg ENET_RECEIVEALL: all received frame are forwarded to application \arg ENET_BROADCAST_FRAMES_PASS: the address filters pass all received broadcast frames \arg ENET_BROADCAST_FRAMES_DROP: the address filters filter all incoming broadcast frames - \param[out] none + \param[out] none \retval ErrStatus: ERROR or SUCCESS */ ErrStatus enet_init(enet_mediamode_enum mediamode, enet_chksumconf_enum checksum, enet_frmrecept_enum recept) @@ -297,19 +330,19 @@ ErrStatus enet_init(enet_mediamode_enum mediamode, enet_chksumconf_enum checksum uint32_t reg_value=0U, reg_temp = 0U, temp = 0U; uint32_t media_temp = 0U; uint32_t timeout = 0U; - uint16_t phy_value = 0U; + uint16_t phy_value = 0U; ErrStatus phy_state= ERROR, enet_state = ERROR; - + /* PHY interface configuration, configure SMI clock and reset PHY chip */ if(ERROR == enet_phy_config()){ _ENET_DELAY_(PHY_RESETDELAY); if(ERROR == enet_phy_config()){ return enet_state; - } + } } /* initialize ENET peripheral with generally concerned parameters */ enet_default_init(); - + /* 1st, configure mediamode */ media_temp = (uint32_t)mediamode; /* if is PHY auto negotiation */ @@ -317,7 +350,7 @@ ErrStatus enet_init(enet_mediamode_enum mediamode, enet_chksumconf_enum checksum /* wait for PHY_LINKED_STATUS bit be set */ do{ enet_phy_write_read(ENET_PHY_READ, PHY_ADDRESS, PHY_REG_BSR, &phy_value); - phy_value &= PHY_LINKED_STATUS; + phy_value &= PHY_LINKED_STATUS; timeout++; }while((RESET == phy_value) && (timeout < PHY_READ_TO)); /* return ERROR due to timeout */ @@ -326,7 +359,7 @@ ErrStatus enet_init(enet_mediamode_enum mediamode, enet_chksumconf_enum checksum } /* reset timeout counter */ timeout = 0U; - + /* enable auto-negotiation */ phy_value = PHY_AUTONEGOTIATION; phy_state = enet_phy_write_read(ENET_PHY_WRITE, PHY_ADDRESS, PHY_REG_BCR, &phy_value); @@ -334,22 +367,22 @@ ErrStatus enet_init(enet_mediamode_enum mediamode, enet_chksumconf_enum checksum /* return ERROR due to write timeout */ return enet_state; } - + /* wait for the PHY_AUTONEGO_COMPLETE bit be set */ do{ enet_phy_write_read(ENET_PHY_READ, PHY_ADDRESS, PHY_REG_BSR, &phy_value); phy_value &= PHY_AUTONEGO_COMPLETE; timeout++; - }while((RESET == phy_value) && (timeout < (uint32_t)PHY_READ_TO)); + }while((RESET == phy_value) && (timeout < (uint32_t)PHY_READ_TO)); /* return ERROR due to timeout */ if(PHY_READ_TO == timeout){ return enet_state; } /* reset timeout counter */ timeout = 0U; - + /* read the result of the auto-negotiation */ - enet_phy_write_read(ENET_PHY_READ, PHY_ADDRESS, PHY_SR, &phy_value); + enet_phy_write_read(ENET_PHY_READ, PHY_ADDRESS, PHY_SR, &phy_value); /* configure the duplex mode of MAC following the auto-negotiation result */ if((uint16_t)RESET != (phy_value & PHY_DUPLEX_STATUS)){ media_temp = ENET_MODE_FULLDUPLEX; @@ -361,7 +394,7 @@ ErrStatus enet_init(enet_mediamode_enum mediamode, enet_chksumconf_enum checksum media_temp |= ENET_SPEEDMODE_10M; }else{ media_temp |= ENET_SPEEDMODE_100M; - } + } }else{ phy_value = (uint16_t)((media_temp & ENET_MAC_CFG_DPM) >> 3); phy_value |= (uint16_t)((media_temp & ENET_MAC_CFG_SPD) >> 1); @@ -371,7 +404,7 @@ ErrStatus enet_init(enet_mediamode_enum mediamode, enet_chksumconf_enum checksum return enet_state; } /* PHY configuration need some time */ - _ENET_DELAY_(PHY_CONFIGDELAY); + _ENET_DELAY_(PHY_CONFIGDELAY); } /* after configuring the PHY, use mediamode to configure registers */ reg_value = ENET_MAC_CFG; @@ -379,27 +412,27 @@ ErrStatus enet_init(enet_mediamode_enum mediamode, enet_chksumconf_enum checksum reg_value &= (~(ENET_MAC_CFG_SPD |ENET_MAC_CFG_DPM |ENET_MAC_CFG_LBM)); reg_value |= media_temp; ENET_MAC_CFG = reg_value; - - + + /* 2st, configure checksum */ if(RESET != ((uint32_t)checksum & ENET_CHECKSUMOFFLOAD_ENABLE)){ ENET_MAC_CFG |= ENET_CHECKSUMOFFLOAD_ENABLE; - + reg_value = ENET_DMA_CTL; /* configure ENET_DMA_CTL register */ reg_value &= ~ENET_DMA_CTL_DTCERFD; reg_value |= ((uint32_t)checksum & ENET_DMA_CTL_DTCERFD); ENET_DMA_CTL = reg_value; } - + /* 3rd, configure recept */ ENET_MAC_FRMF |= (uint32_t)recept; - + /* 4th, configure different function options */ /* configure forward_frame related registers */ if(RESET != (enet_initpara.option_enable & (uint32_t)FORWARD_OPTION)){ reg_temp = enet_initpara.forward_frame; - + reg_value = ENET_MAC_CFG; temp = reg_temp; /* configure ENET_MAC_CFG register */ @@ -407,7 +440,7 @@ ErrStatus enet_init(enet_mediamode_enum mediamode, enet_chksumconf_enum checksum temp &= (ENET_MAC_CFG_TFCD | ENET_MAC_CFG_APCD); reg_value |= temp; ENET_MAC_CFG = reg_value; - + reg_value = ENET_DMA_CTL; temp = reg_temp; /* configure ENET_DMA_CTL register */ @@ -420,7 +453,7 @@ ErrStatus enet_init(enet_mediamode_enum mediamode, enet_chksumconf_enum checksum /* configure dmabus_mode related registers */ if(RESET != (enet_initpara.option_enable & (uint32_t)DMABUS_OPTION)){ temp = enet_initpara.dmabus_mode; - + reg_value = ENET_DMA_BCTL; /* configure ENET_DMA_BCTL register */ reg_value &= ~(ENET_DMA_BCTL_AA | ENET_DMA_BCTL_FB \ @@ -430,31 +463,31 @@ ErrStatus enet_init(enet_mediamode_enum mediamode, enet_chksumconf_enum checksum } /* configure dma_maxburst related registers */ - if(RESET != (enet_initpara.option_enable & (uint32_t)DMA_MAXBURST_OPTION)){ + if(RESET != (enet_initpara.option_enable & (uint32_t)DMA_MAXBURST_OPTION)){ temp = enet_initpara.dma_maxburst; - + reg_value = ENET_DMA_BCTL; /* configure ENET_DMA_BCTL register */ - reg_value &= ~(ENET_DMA_BCTL_RXDP| ENET_DMA_BCTL_PGBL | ENET_DMA_BCTL_UIP); + reg_value &= ~(ENET_DMA_BCTL_RXDP| ENET_DMA_BCTL_PGBL | ENET_DMA_BCTL_UIP); reg_value |= temp; ENET_DMA_BCTL = reg_value; } /* configure dma_arbitration related registers */ - if(RESET != (enet_initpara.option_enable & (uint32_t)DMA_ARBITRATION_OPTION)){ + if(RESET != (enet_initpara.option_enable & (uint32_t)DMA_ARBITRATION_OPTION)){ temp = enet_initpara.dma_arbitration; - + reg_value = ENET_DMA_BCTL; /* configure ENET_DMA_BCTL register */ reg_value &= ~(ENET_DMA_BCTL_RTPR | ENET_DMA_BCTL_DAB); reg_value |= temp; ENET_DMA_BCTL = reg_value; } - + /* configure store_forward_mode related registers */ - if(RESET != (enet_initpara.option_enable & (uint32_t)STORE_OPTION)){ + if(RESET != (enet_initpara.option_enable & (uint32_t)STORE_OPTION)){ temp = enet_initpara.store_forward_mode; - + reg_value = ENET_DMA_CTL; /* configure ENET_DMA_CTL register */ reg_value &= ~(ENET_DMA_CTL_RSFD | ENET_DMA_CTL_TSFD| ENET_DMA_CTL_RTHC| ENET_DMA_CTL_TTHC); @@ -463,9 +496,9 @@ ErrStatus enet_init(enet_mediamode_enum mediamode, enet_chksumconf_enum checksum } /* configure dma_function related registers */ - if(RESET != (enet_initpara.option_enable & (uint32_t)DMA_OPTION)){ + if(RESET != (enet_initpara.option_enable & (uint32_t)DMA_OPTION)){ reg_temp = enet_initpara.dma_function; - + reg_value = ENET_DMA_CTL; temp = reg_temp; /* configure ENET_DMA_CTL register */ @@ -473,7 +506,7 @@ ErrStatus enet_init(enet_mediamode_enum mediamode, enet_chksumconf_enum checksum temp &= (ENET_DMA_CTL_DAFRF | ENET_DMA_CTL_OSF); reg_value |= temp; ENET_DMA_CTL = reg_value; - + reg_value = ENET_DMA_BCTL; temp = reg_temp; /* configure ENET_DMA_BCTL register */ @@ -484,9 +517,9 @@ ErrStatus enet_init(enet_mediamode_enum mediamode, enet_chksumconf_enum checksum } /* configure vlan_config related registers */ - if(RESET != (enet_initpara.option_enable & (uint32_t)VLAN_OPTION)){ + if(RESET != (enet_initpara.option_enable & (uint32_t)VLAN_OPTION)){ reg_temp = enet_initpara.vlan_config; - + reg_value = ENET_MAC_VLT; /* configure ENET_MAC_VLT register */ reg_value &= ~(ENET_MAC_VLT_VLTI | ENET_MAC_VLT_VLTC); @@ -495,9 +528,9 @@ ErrStatus enet_init(enet_mediamode_enum mediamode, enet_chksumconf_enum checksum } /* configure flow_control related registers */ - if(RESET != (enet_initpara.option_enable & (uint32_t)FLOWCTL_OPTION)){ + if(RESET != (enet_initpara.option_enable & (uint32_t)FLOWCTL_OPTION)){ reg_temp = enet_initpara.flow_control; - + reg_value = ENET_MAC_FCTL; temp = reg_temp; /* configure ENET_MAC_FCTL register */ @@ -507,7 +540,7 @@ ErrStatus enet_init(enet_mediamode_enum mediamode, enet_chksumconf_enum checksum | ENET_MAC_FCTL_UPFDT |ENET_MAC_FCTL_RFCEN |ENET_MAC_FCTL_TFCEN); reg_value |= temp; ENET_MAC_FCTL = reg_value; - + reg_value = ENET_MAC_FCTH; temp = reg_temp; /* configure ENET_MAC_FCTH register */ @@ -515,22 +548,22 @@ ErrStatus enet_init(enet_mediamode_enum mediamode, enet_chksumconf_enum checksum temp &= ((ENET_MAC_FCTH_RFA | ENET_MAC_FCTH_RFD )<<8); reg_value |= (temp >> 8); ENET_MAC_FCTH = reg_value; - } - + } + /* configure hashtable_high related registers */ - if(RESET != (enet_initpara.option_enable & (uint32_t)HASHH_OPTION)){ + if(RESET != (enet_initpara.option_enable & (uint32_t)HASHH_OPTION)){ ENET_MAC_HLH = enet_initpara.hashtable_high; - } + } /* configure hashtable_low related registers */ - if(RESET != (enet_initpara.option_enable & (uint32_t)HASHL_OPTION)){ + if(RESET != (enet_initpara.option_enable & (uint32_t)HASHL_OPTION)){ ENET_MAC_HLL = enet_initpara.hashtable_low; - } + } /* configure framesfilter_mode related registers */ - if(RESET != (enet_initpara.option_enable & (uint32_t)FILTER_OPTION)){ + if(RESET != (enet_initpara.option_enable & (uint32_t)FILTER_OPTION)){ reg_temp = enet_initpara.framesfilter_mode; - + reg_value = ENET_MAC_FRMF; /* configure ENET_MAC_FRMF register */ reg_value &= ~(ENET_MAC_FRMF_SAFLT | ENET_MAC_FRMF_SAIFLT | ENET_MAC_FRMF_DAIFLT \ @@ -538,41 +571,41 @@ ErrStatus enet_init(enet_mediamode_enum mediamode, enet_chksumconf_enum checksum | ENET_MAC_FRMF_HUF | ENET_MAC_FRMF_PCFRM); reg_value |= reg_temp; ENET_MAC_FRMF = reg_value; - } + } /* configure halfduplex_param related registers */ - if(RESET != (enet_initpara.option_enable & (uint32_t)HALFDUPLEX_OPTION)){ + if(RESET != (enet_initpara.option_enable & (uint32_t)HALFDUPLEX_OPTION)){ reg_temp = enet_initpara.halfduplex_param; - + reg_value = ENET_MAC_CFG; /* configure ENET_MAC_CFG register */ reg_value &= ~(ENET_MAC_CFG_CSD | ENET_MAC_CFG_ROD | ENET_MAC_CFG_RTD \ | ENET_MAC_CFG_BOL | ENET_MAC_CFG_DFC); reg_value |= reg_temp; ENET_MAC_CFG = reg_value; - } + } /* configure timer_config related registers */ - if(RESET != (enet_initpara.option_enable & (uint32_t)TIMER_OPTION)){ + if(RESET != (enet_initpara.option_enable & (uint32_t)TIMER_OPTION)){ reg_temp = enet_initpara.timer_config; - + reg_value = ENET_MAC_CFG; /* configure ENET_MAC_CFG register */ reg_value &= ~(ENET_MAC_CFG_WDD | ENET_MAC_CFG_JBD); reg_value |= reg_temp; ENET_MAC_CFG = reg_value; - } - + } + /* configure interframegap related registers */ - if(RESET != (enet_initpara.option_enable & (uint32_t)INTERFRAMEGAP_OPTION)){ + if(RESET != (enet_initpara.option_enable & (uint32_t)INTERFRAMEGAP_OPTION)){ reg_temp = enet_initpara.interframegap; - + reg_value = ENET_MAC_CFG; /* configure ENET_MAC_CFG register */ reg_value &= ~ENET_MAC_CFG_IGBS; reg_value |= reg_temp; ENET_MAC_CFG = reg_value; - } + } enet_state = SUCCESS; return enet_state; @@ -589,21 +622,21 @@ ErrStatus enet_software_reset(void) uint32_t timeout = 0U; ErrStatus enet_state = ERROR; uint32_t dma_flag; - + /* reset all core internal registers located in CLK_TX and CLK_RX */ ENET_DMA_BCTL |= ENET_DMA_BCTL_SWR; - + /* wait for reset operation complete */ do{ dma_flag = (ENET_DMA_BCTL & ENET_DMA_BCTL_SWR); timeout++; }while((RESET != dma_flag) && (ENET_DELAY_TO != timeout)); - /* reset operation complete */ + /* reset operation complete */ if(RESET == (ENET_DMA_BCTL & ENET_DMA_BCTL_SWR)){ enet_state = SUCCESS; } - + return enet_state; } @@ -617,15 +650,15 @@ uint32_t enet_rxframe_size_get(void) { uint32_t size = 0U; uint32_t status; - + /* get rdes0 information of current RxDMA descriptor */ status = dma_current_rxdesc->status; - + /* if the desciptor is owned by DMA */ if((uint32_t)RESET != (status & ENET_RDES0_DAV)){ return 0U; } - + /* if has any error, or the frame uses two or more descriptors */ if((((uint32_t)RESET) != (status & ENET_RDES0_ERRS)) || (((uint32_t)RESET) == (status & ENET_RDES0_LDES)) || @@ -633,7 +666,7 @@ uint32_t enet_rxframe_size_get(void) /* drop current receive frame */ enet_rxframe_drop(); - return 0U; + return 1U; } #ifdef SELECT_DESCRIPTORS_ENHANCED_MODE /* if is an ethernet-type frame, and IP frame payload error occurred */ @@ -642,18 +675,18 @@ uint32_t enet_rxframe_size_get(void) /* drop current receive frame */ enet_rxframe_drop(); - return 0U; + return 1U; } -#else +#else /* if is an ethernet-type frame, and IP frame payload error occurred */ if((((uint32_t)RESET) != (status & ENET_RDES0_FRMT)) && (((uint32_t)RESET) != (status & ENET_RDES0_PCERR))){ /* drop current receive frame */ enet_rxframe_drop(); - return 0U; - } -#endif + return 1U; + } +#endif /* if CPU owns current descriptor, no error occured, the frame uses only one descriptor */ if((((uint32_t)RESET) == (status & ENET_RDES0_DAV)) && (((uint32_t)RESET) == (status & ENET_RDES0_ERRS)) && @@ -661,22 +694,27 @@ uint32_t enet_rxframe_size_get(void) (((uint32_t)RESET) != (status & ENET_RDES0_FDES))){ /* get the size of the received data including CRC */ size = GET_RDES0_FRML(status); - /* substract the CRC size */ + /* substract the CRC size */ size = size - 4U; - - /* if is a type frame, and CRC is not included in forwarding frame */ + + /* if is a type frame, and CRC is not included in forwarding frame */ if((RESET != (ENET_MAC_CFG & ENET_MAC_CFG_TFCD)) && (RESET != (status & ENET_RDES0_FRMT))){ size = size + 4U; } + }else{ + enet_unknow_err++; + enet_rxframe_drop(); + + return 1U; } - - /* return packet size */ + + /* return packet size */ return size; } /*! \brief initialize the DMA Tx/Rx descriptors's parameters in chain mode - \param[in] direction: the descriptors which users want to init, refer to enet_dmadirection_enum, + \param[in] direction: the descriptors which users want to init, refer to enet_dmadirection_enum only one parameter can be selected which is shown as below \arg ENET_DMA_TX: DMA Tx descriptors \arg ENET_DMA_RX: DMA Rx descriptors @@ -688,7 +726,7 @@ void enet_descriptors_chain_init(enet_dmadirection_enum direction) uint32_t num = 0U, count = 0U, maxsize = 0U; uint32_t desc_status = 0U, desc_bufsize = 0U; enet_descriptors_struct *desc, *desc_tab; - uint8_t *buf; + uint8_t *buf; /* if want to initialize DMA Tx descriptors */ if (ENET_DMA_TX == direction){ @@ -697,58 +735,58 @@ void enet_descriptors_chain_init(enet_dmadirection_enum direction) buf = &tx_buff[0][0]; count = ENET_TXBUF_NUM; maxsize = ENET_TXBUF_SIZE; - + /* select chain mode */ desc_status = ENET_TDES0_TCHM; - + /* configure DMA Tx descriptor table address register */ ENET_DMA_TDTADDR = (uint32_t)desc_tab; dma_current_txdesc = desc_tab; - }else{ + }else{ /* if want to initialize DMA Rx descriptors */ /* save a copy of the DMA Rx descriptors */ desc_tab = rxdesc_tab; buf = &rx_buff[0][0]; count = ENET_RXBUF_NUM; maxsize = ENET_RXBUF_SIZE; - + /* enable receiving */ desc_status = ENET_RDES0_DAV; /* select receive chained mode and set buffer1 size */ desc_bufsize = ENET_RDES1_RCHM | (uint32_t)ENET_RXBUF_SIZE; - + /* configure DMA Rx descriptor table address register */ ENET_DMA_RDTADDR = (uint32_t)desc_tab; - dma_current_rxdesc = desc_tab; + dma_current_rxdesc = desc_tab; } dma_current_ptp_rxdesc = NULL; dma_current_ptp_txdesc = NULL; - - /* configure each descriptor */ + + /* configure each descriptor */ for(num=0U; num < count; num++){ /* get the pointer to the next descriptor of the descriptor table */ desc = desc_tab + num; /* configure descriptors */ - desc->status = desc_status; + desc->status = desc_status; desc->control_buffer_size = desc_bufsize; desc->buffer1_addr = (uint32_t)(&buf[num * maxsize]); - + /* if is not the last descriptor */ if(num < (count - 1U)){ /* configure the next descriptor address */ desc->buffer2_next_desc_addr = (uint32_t)(desc_tab + num + 1U); }else{ - /* when it is the last descriptor, the next descriptor address - equals to first descriptor address in descriptor table */ - desc->buffer2_next_desc_addr = (uint32_t) desc_tab; + /* when it is the last descriptor, the next descriptor address + equals to first descriptor address in descriptor table */ + desc->buffer2_next_desc_addr = (uint32_t) desc_tab; } - } + } } /*! \brief initialize the DMA Tx/Rx descriptors's parameters in ring mode - \param[in] direction: the descriptors which users want to init, refer to enet_dmadirection_enum, + \param[in] direction: the descriptors which users want to init, refer to enet_dmadirection_enum only one parameter can be selected which is shown as below \arg ENET_DMA_TX: DMA Tx descriptors \arg ENET_DMA_RX: DMA Rx descriptors @@ -761,20 +799,20 @@ void enet_descriptors_ring_init(enet_dmadirection_enum direction) uint32_t desc_status = 0U, desc_bufsize = 0U; enet_descriptors_struct *desc; enet_descriptors_struct *desc_tab; - uint8_t *buf; - + uint8_t *buf; + /* configure descriptor skip length */ ENET_DMA_BCTL &= ~ENET_DMA_BCTL_DPSL; ENET_DMA_BCTL |= DMA_BCTL_DPSL(0); - + /* if want to initialize DMA Tx descriptors */ if (ENET_DMA_TX == direction){ /* save a copy of the DMA Tx descriptors */ desc_tab = txdesc_tab; buf = &tx_buff[0][0]; count = ENET_TXBUF_NUM; - maxsize = ENET_TXBUF_SIZE; - + maxsize = ENET_TXBUF_SIZE; + /* configure DMA Tx descriptor table address register */ ENET_DMA_TDTADDR = (uint32_t)desc_tab; dma_current_txdesc = desc_tab; @@ -784,41 +822,41 @@ void enet_descriptors_ring_init(enet_dmadirection_enum direction) desc_tab = rxdesc_tab; buf = &rx_buff[0][0]; count = ENET_RXBUF_NUM; - maxsize = ENET_RXBUF_SIZE; - + maxsize = ENET_RXBUF_SIZE; + /* enable receiving */ desc_status = ENET_RDES0_DAV; /* set buffer1 size */ desc_bufsize = ENET_RXBUF_SIZE; - + /* configure DMA Rx descriptor table address register */ ENET_DMA_RDTADDR = (uint32_t)desc_tab; - dma_current_rxdesc = desc_tab; + dma_current_rxdesc = desc_tab; } dma_current_ptp_rxdesc = NULL; dma_current_ptp_txdesc = NULL; - - /* configure each descriptor */ + + /* configure each descriptor */ for(num=0U; num < count; num++){ /* get the pointer to the next descriptor of the descriptor table */ desc = desc_tab + num; /* configure descriptors */ - desc->status = desc_status; - desc->control_buffer_size = desc_bufsize; - desc->buffer1_addr = (uint32_t)(&buf[num * maxsize]); - + desc->status = desc_status; + desc->control_buffer_size = desc_bufsize; + desc->buffer1_addr = (uint32_t)(&buf[num * maxsize]); + /* when it is the last descriptor */ if(num == (count - 1U)){ if (ENET_DMA_TX == direction){ - /* configure transmit end of ring mode */ + /* configure transmit end of ring mode */ desc->status |= ENET_TDES0_TERM; }else{ /* configure receive end of ring mode */ desc->control_buffer_size |= ENET_RDES1_RERM; } } - } + } } /*! @@ -831,46 +869,46 @@ void enet_descriptors_ring_init(enet_dmadirection_enum direction) ErrStatus enet_frame_receive(uint8_t *buffer, uint32_t bufsize) { uint32_t offset = 0U, size = 0U; - + /* the descriptor is busy due to own by the DMA */ if((uint32_t)RESET != (dma_current_rxdesc->status & ENET_RDES0_DAV)){ - return ERROR; + return ERROR; } - + /* if buffer pointer is null, indicates that users has copied data in application */ if(NULL != buffer){ /* if no error occurs, and the frame uses only one descriptor */ - if((((uint32_t)RESET) == (dma_current_rxdesc->status & ENET_RDES0_ERRS)) && - (((uint32_t)RESET) != (dma_current_rxdesc->status & ENET_RDES0_LDES)) && - (((uint32_t)RESET) != (dma_current_rxdesc->status & ENET_RDES0_FDES))){ + if((((uint32_t)RESET) == (dma_current_rxdesc->status & ENET_RDES0_ERRS)) && + (((uint32_t)RESET) != (dma_current_rxdesc->status & ENET_RDES0_LDES)) && + (((uint32_t)RESET) != (dma_current_rxdesc->status & ENET_RDES0_FDES))){ /* get the frame length except CRC */ size = GET_RDES0_FRML(dma_current_rxdesc->status); size = size - 4U; - - /* if is a type frame, and CRC is not included in forwarding frame */ + + /* if is a type frame, and CRC is not included in forwarding frame */ if((RESET != (ENET_MAC_CFG & ENET_MAC_CFG_TFCD)) && (RESET != (dma_current_rxdesc->status & ENET_RDES0_FRMT))){ size = size + 4U; } - + /* to avoid situation that the frame size exceeds the buffer length */ if(size > bufsize){ return ERROR; } - + /* copy data from Rx buffer to application buffer */ for(offset = 0U; offset<size; offset++){ (*(buffer + offset)) = (*(__IO uint8_t *) (uint32_t)((dma_current_rxdesc->buffer1_addr) + offset)); } - + }else{ /* return ERROR */ return ERROR; } } /* enable reception, descriptor is owned by DMA */ - dma_current_rxdesc->status = ENET_RDES0_DAV; - + dma_current_rxdesc->status = ENET_RDES0_DAV; + /* check Rx buffer unavailable flag status */ if ((uint32_t)RESET != (ENET_DMA_STAT & ENET_DMA_STAT_RBU)){ /* clear RBU flag */ @@ -878,22 +916,22 @@ ErrStatus enet_frame_receive(uint8_t *buffer, uint32_t bufsize) /* resume DMA reception by writing to the RPEN register*/ ENET_DMA_RPEN = 0U; } - - /* update the current RxDMA descriptor pointer to the next decriptor in RxDMA decriptor table */ + + /* update the current RxDMA descriptor pointer to the next decriptor in RxDMA decriptor table */ /* chained mode */ - if((uint32_t)RESET != (dma_current_rxdesc->control_buffer_size & ENET_RDES1_RCHM)){ - dma_current_rxdesc = (enet_descriptors_struct*) (dma_current_rxdesc->buffer2_next_desc_addr); - }else{ + if((uint32_t)RESET != (dma_current_rxdesc->control_buffer_size & ENET_RDES1_RCHM)){ + dma_current_rxdesc = (enet_descriptors_struct*) (dma_current_rxdesc->buffer2_next_desc_addr); + }else{ /* ring mode */ if((uint32_t)RESET != (dma_current_rxdesc->control_buffer_size & ENET_RDES1_RERM)){ /* if is the last descriptor in table, the next descriptor is the table header */ - dma_current_rxdesc = (enet_descriptors_struct*) (ENET_DMA_RDTADDR); - }else{ + dma_current_rxdesc = (enet_descriptors_struct*) (ENET_DMA_RDTADDR); + }else{ /* the next descriptor is the current address, add the descriptor size, and descriptor skip length */ - dma_current_rxdesc = (enet_descriptors_struct*) (uint32_t)((uint32_t)dma_current_rxdesc + ETH_DMARXDESC_SIZE + (GET_DMA_BCTL_DPSL(ENET_DMA_BCTL))); + dma_current_rxdesc = (enet_descriptors_struct*) (uint32_t)((uint32_t)dma_current_rxdesc + ETH_DMARXDESC_SIZE + (GET_DMA_BCTL_DPSL(ENET_DMA_BCTL))); } } - + return SUCCESS; } @@ -909,52 +947,52 @@ ErrStatus enet_frame_transmit(uint8_t *buffer, uint32_t length) { uint32_t offset = 0U; uint32_t dma_tbu_flag, dma_tu_flag; - + /* the descriptor is busy due to own by the DMA */ if((uint32_t)RESET != (dma_current_txdesc->status & ENET_TDES0_DAV)){ return ERROR; } - + /* only frame length no more than ENET_MAX_FRAME_SIZE is allowed */ if(length > ENET_MAX_FRAME_SIZE){ return ERROR; - } - + } + /* if buffer pointer is null, indicates that users has handled data in application */ - if(NULL != buffer){ + if(NULL != buffer){ /* copy frame data from application buffer to Tx buffer */ for(offset = 0U; offset < length; offset++){ (*(__IO uint8_t *) (uint32_t)((dma_current_txdesc->buffer1_addr) + offset)) = (*(buffer + offset)); } } - + /* set the frame length */ dma_current_txdesc->control_buffer_size = length; - /* set the segment of frame, frame is transmitted in one descriptor */ + /* set the segment of frame, frame is transmitted in one descriptor */ dma_current_txdesc->status |= ENET_TDES0_LSG | ENET_TDES0_FSG; /* enable the DMA transmission */ dma_current_txdesc->status |= ENET_TDES0_DAV; - + /* check Tx buffer unavailable flag status */ - dma_tbu_flag = (ENET_DMA_STAT & ENET_DMA_STAT_TBU); + dma_tbu_flag = (ENET_DMA_STAT & ENET_DMA_STAT_TBU); dma_tu_flag = (ENET_DMA_STAT & ENET_DMA_STAT_TU); - + if ((RESET != dma_tbu_flag) || (RESET != dma_tu_flag)){ /* clear TBU and TU flag */ ENET_DMA_STAT = (dma_tbu_flag | dma_tu_flag); /* resume DMA transmission by writing to the TPEN register*/ ENET_DMA_TPEN = 0U; } - - /* update the current TxDMA descriptor pointer to the next decriptor in TxDMA decriptor table*/ + + /* update the current TxDMA descriptor pointer to the next decriptor in TxDMA decriptor table*/ /* chained mode */ - if((uint32_t)RESET != (dma_current_txdesc->status & ENET_TDES0_TCHM)){ - dma_current_txdesc = (enet_descriptors_struct*) (dma_current_txdesc->buffer2_next_desc_addr); - }else{ + if((uint32_t)RESET != (dma_current_txdesc->status & ENET_TDES0_TCHM)){ + dma_current_txdesc = (enet_descriptors_struct*) (dma_current_txdesc->buffer2_next_desc_addr); + }else{ /* ring mode */ if((uint32_t)RESET != (dma_current_txdesc->status & ENET_TDES0_TERM)){ /* if is the last descriptor in table, the next descriptor is the table header */ - dma_current_txdesc = (enet_descriptors_struct*) (ENET_DMA_TDTADDR); + dma_current_txdesc = (enet_descriptors_struct*) (ENET_DMA_TDTADDR); }else{ /* the next descriptor is the current address, add the descriptor size, and descriptor skip length */ dma_current_txdesc = (enet_descriptors_struct*) (uint32_t)((uint32_t)dma_current_txdesc + ETH_DMATXDESC_SIZE + (GET_DMA_BCTL_DPSL(ENET_DMA_BCTL))); @@ -966,7 +1004,7 @@ ErrStatus enet_frame_transmit(uint8_t *buffer, uint32_t length) /*! \brief configure the transmit IP frame checksum offload calculation and insertion - \param[in] desc: the descriptor pointer which users want to configure + \param[in] desc: the descriptor pointer which users want to configure, refer to enet_descriptors_struct \param[in] checksum: IP frame checksum configuration only one parameter can be selected which is shown as below \arg ENET_CHECKSUM_DISABLE: checksum insertion disabled @@ -1007,18 +1045,18 @@ void enet_disable(void) } /*! - \brief configure MAC address - \param[in] mac_addr: select which MAC address will be set, - only one parameter can be selected which is shown as below + \brief configure MAC address + \param[in] mac_addr: select which MAC address will be set, refer to enet_macaddress_enum + only one parameter can be selected which is shown as below \arg ENET_MAC_ADDRESS0: set MAC address 0 filter \arg ENET_MAC_ADDRESS1: set MAC address 1 filter \arg ENET_MAC_ADDRESS2: set MAC address 2 filter \arg ENET_MAC_ADDRESS3: set MAC address 3 filter \param[in] paddr: the buffer pointer which stores the MAC address - (little-ending store, such as MAC address is aa:bb:cc:dd:ee:22, the buffer is {22, ee, dd, cc, bb, aa}) + (little-ending store, such as MAC address is aa:bb:cc:dd:ee:22, the buffer is {22, ee, dd, cc, bb, aa}) \param[out] none \retval none -*/ +*/ void enet_mac_address_set(enet_macaddress_enum mac_addr, uint8_t paddr[]) { REG32(ENET_ADDRH_BASE + (uint32_t)mac_addr) = ENET_SET_MACADDRH(paddr); @@ -1026,17 +1064,17 @@ void enet_mac_address_set(enet_macaddress_enum mac_addr, uint8_t paddr[]) } /*! - \brief get MAC address - \param[in] mac_addr: select which MAC address will be get, + \brief get MAC address + \param[in] mac_addr: select which MAC address will be get, refer to enet_macaddress_enum only one parameter can be selected which is shown as below \arg ENET_MAC_ADDRESS0: get MAC address 0 filter \arg ENET_MAC_ADDRESS1: get MAC address 1 filter \arg ENET_MAC_ADDRESS2: get MAC address 2 filter \arg ENET_MAC_ADDRESS3: get MAC address 3 filter \param[out] paddr: the buffer pointer which is stored the MAC address - (little-ending store, such as mac address is aa:bb:cc:dd:ee:22, the buffer is {22, ee, dd, cc, bb, aa}) + (little-ending store, such as mac address is aa:bb:cc:dd:ee:22, the buffer is {22, ee, dd, cc, bb, aa}) \retval none -*/ +*/ void enet_mac_address_get(enet_macaddress_enum mac_addr, uint8_t paddr[]) { paddr[0] = ENET_GET_MACADDR(mac_addr, 0U); @@ -1048,12 +1086,12 @@ void enet_mac_address_get(enet_macaddress_enum mac_addr, uint8_t paddr[]) } /*! - \brief get the ENET MAC/MSC/PTP/DMA status flag + \brief get the ENET MAC/MSC/PTP/DMA status flag \param[in] enet_flag: ENET status flag, refer to enet_flag_enum, only one parameter can be selected which is shown as below - \arg ENET_MAC_FLAG_MPKR: magic packet received flag + \arg ENET_MAC_FLAG_MPKR: magic packet received flag \arg ENET_MAC_FLAG_WUFR: wakeup frame received flag - \arg ENET_MAC_FLAG_FLOWCONTROL: flow control status flag + \arg ENET_MAC_FLAG_FLOWCONTROL: flow control status flag \arg ENET_MAC_FLAG_WUM: WUM status flag \arg ENET_MAC_FLAG_MSC: MSC status flag \arg ENET_MAC_FLAG_MSCR: MSC receive status flag @@ -1101,7 +1139,7 @@ FlagStatus enet_flag_get(enet_flag_enum enet_flag) } /*! - \brief clear the ENET DMA status flag + \brief clear the ENET DMA status flag \param[in] enet_flag: ENET DMA flag clear, refer to enet_flag_clear_enum only one parameter can be selected which is shown as below \arg ENET_DMA_FLAG_TS_CLR: transmit status flag clear @@ -1129,8 +1167,8 @@ void enet_flag_clear(enet_flag_clear_enum enet_flag) } /*! - \brief enable ENET MAC/MSC/DMA interrupt - \param[in] enet_int: ENET interrupt, + \brief enable ENET MAC/MSC/DMA interrupt + \param[in] enet_int: ENET interrupt,, refer to enet_int_enum only one parameter can be selected which is shown as below \arg ENET_MAC_INT_WUMIM: WUM interrupt mask \arg ENET_MAC_INT_TMSTIM: timestamp trigger interrupt mask @@ -1170,8 +1208,8 @@ void enet_interrupt_enable(enet_int_enum enet_int) } /*! - \brief disable ENET MAC/MSC/DMA interrupt - \param[in] enet_int: ENET interrupt, + \brief disable ENET MAC/MSC/DMA interrupt + \param[in] enet_int: ENET interrupt, refer to enet_int_enum only one parameter can be selected which is shown as below \arg ENET_MAC_INT_WUMIM: WUM interrupt mask \arg ENET_MAC_INT_TMSTIM: timestamp trigger interrupt mask @@ -1211,8 +1249,8 @@ void enet_interrupt_disable(enet_int_enum enet_int) } /*! - \brief get ENET MAC/MSC/DMA interrupt flag - \param[in] int_flag: ENET interrupt flag, + \brief get ENET MAC/MSC/DMA interrupt flag + \param[in] int_flag: ENET interrupt flag, refer to enet_int_flag_enum only one parameter can be selected which is shown as below \arg ENET_MAC_INT_FLAG_WUM: WUM status flag \arg ENET_MAC_INT_FLAG_MSC: MSC status flag @@ -1256,8 +1294,8 @@ FlagStatus enet_interrupt_flag_get(enet_int_flag_enum int_flag) } /*! - \brief clear ENET DMA interrupt flag - \param[in] int_flag_clear: clear ENET interrupt flag, + \brief clear ENET DMA interrupt flag + \param[in] int_flag_clear: clear ENET interrupt flag, refer to enet_int_flag_clear_enum only one parameter can be selected which is shown as below \arg ENET_DMA_INT_FLAG_TS_CLR: transmit status flag \arg ENET_DMA_INT_FLAG_TPS_CLR: transmit process stopped status flag @@ -1303,7 +1341,7 @@ void enet_tx_enable(void) \retval none */ void enet_tx_disable(void) -{ +{ ENET_DMA_CTL &= ~ENET_DMA_CTL_STE; enet_txfifo_flush(); ENET_MAC_CFG &= ~ENET_MAC_CFG_TEN; @@ -1334,10 +1372,10 @@ void enet_rx_disable(void) } /*! - \brief put registers value into the application buffer + \brief put registers value into the application buffer \param[in] type: register type which will be get, refer to enet_registers_type_enum, only one parameter can be selected which is shown as below - \arg ALL_MAC_REG: get the registers within the offset scope between ENET_MAC_CFG and ENET_MAC_FCTH + \arg ALL_MAC_REG: get the registers within the offset scope between ENET_MAC_CFG and ENET_MAC_FCTH \arg ALL_MSC_REG: get the registers within the offset scope between ENET_MSC_CTL and ENET_MSC_RGUFCNT \arg ALL_PTP_REG: get the registers within the offset scope between ENET_PTP_TSCTL and ENET_PTP_PPSCTL \arg ALL_DMA_REG: get the registers within the offset scope between ENET_DMA_BCTL and ENET_DMA_CRBADDR @@ -1348,37 +1386,37 @@ void enet_rx_disable(void) void enet_registers_get(enet_registers_type_enum type, uint32_t *preg, uint32_t num) { uint32_t offset = 0U, max = 0U, limit = 0U; - + offset = (uint32_t)type; max = (uint32_t)type + num; limit = sizeof(enet_reg_tab)/sizeof(uint16_t); - + /* prevent element in this array is out of range */ - if(max > limit){ + if(max > limit){ max = limit; } - + for(; offset < max; offset++){ /* get value of the corresponding register */ - *preg = REG32((ENET) + enet_reg_tab[offset]); + *preg = REG32((ENET) + enet_reg_tab[offset]); preg++; } -} +} /*! \brief get the enet debug status from the debug register - \param[in] mac_debug: enet debug status, + \param[in] mac_debug: enet debug status only one parameter can be selected which is shown as below \arg ENET_MAC_RECEIVER_NOT_IDLE: MAC receiver is not in idle state \arg ENET_RX_ASYNCHRONOUS_FIFO_STATE: Rx asynchronous FIFO status - \arg ENET_RXFIFO_NOT_WRITING: RxFIFO is not doing write operation + \arg ENET_RXFIFO_WRITING: RxFIFO is doing write operation \arg ENET_RXFIFO_READ_STATUS: RxFIFO read operation status \arg ENET_RXFIFO_STATE: RxFIFO state \arg ENET_MAC_TRANSMITTER_NOT_IDLE: MAC transmitter is not in idle state \arg ENET_MAC_TRANSMITTER_STATUS: status of MAC transmitter \arg ENET_PAUSE_CONDITION_STATUS: pause condition status \arg ENET_TXFIFO_READ_STATUS: TxFIFO read operation status - \arg ENET_TXFIFO_NOT_WRITING: TxFIFO is not doing write operation + \arg ENET_TXFIFO_WRITING: TxFIFO is doing write operation \arg ENET_TXFIFO_NOT_EMPTY: TxFIFO is not empty \arg ENET_TXFIFO_FULL: TxFIFO is full \param[out] none @@ -1387,7 +1425,7 @@ void enet_registers_get(enet_registers_type_enum type, uint32_t *preg, uint32_t uint32_t enet_debug_status_get(uint32_t mac_debug) { uint32_t temp_state = 0U; - + switch(mac_debug){ case ENET_RX_ASYNCHRONOUS_FIFO_STATE: temp_state = GET_MAC_DBG_RXAFS(ENET_MAC_DBG); @@ -1408,14 +1446,14 @@ uint32_t enet_debug_status_get(uint32_t mac_debug) if(RESET != (ENET_MAC_DBG & mac_debug)){ temp_state = 0x1U; } - break; + break; } return temp_state; } /*! - \brief enable the MAC address filter - \param[in] mac_addr: select which MAC address will be enable + \brief enable the MAC address filter + \param[in] mac_addr: select which MAC address will be enable, refer to enet_macaddress_enum \arg ENET_MAC_ADDRESS1: enable MAC address 1 filter \arg ENET_MAC_ADDRESS2: enable MAC address 2 filter \arg ENET_MAC_ADDRESS3: enable MAC address 3 filter @@ -1428,8 +1466,8 @@ void enet_address_filter_enable(enet_macaddress_enum mac_addr) } /*! - \brief disable the MAC address filter - \param[in] mac_addr: select which MAC address will be disable, + \brief disable the MAC address filter + \param[in] mac_addr: select which MAC address will be disable, refer to enet_macaddress_enum only one parameter can be selected which is shown as below \arg ENET_MAC_ADDRESS1: disable MAC address 1 filter \arg ENET_MAC_ADDRESS2: disable MAC address 2 filter @@ -1443,21 +1481,21 @@ void enet_address_filter_disable(enet_macaddress_enum mac_addr) } /*! - \brief configure the MAC address filter - \param[in] mac_addr: select which MAC address will be configured, + \brief configure the MAC address filter + \param[in] mac_addr: select which MAC address will be configured, refer to enet_macaddress_enum only one parameter can be selected which is shown as below \arg ENET_MAC_ADDRESS1: configure MAC address 1 filter \arg ENET_MAC_ADDRESS2: configure MAC address 2 filter \arg ENET_MAC_ADDRESS3: configure MAC address 3 filter - \param[in] addr_mask: select which MAC address bytes will be mask, + \param[in] addr_mask: select which MAC address bytes will be mask one or more parameters can be selected which are shown as below \arg ENET_ADDRESS_MASK_BYTE0: mask ENET_MAC_ADDR1L[7:0] bits - \arg ENET_ADDRESS_MASK_BYTE1: mask ENET_MAC_ADDR1L[15:8] bits + \arg ENET_ADDRESS_MASK_BYTE1: mask ENET_MAC_ADDR1L[15:8] bits \arg ENET_ADDRESS_MASK_BYTE2: mask ENET_MAC_ADDR1L[23:16] bits \arg ENET_ADDRESS_MASK_BYTE3: mask ENET_MAC_ADDR1L [31:24] bits \arg ENET_ADDRESS_MASK_BYTE4: mask ENET_MAC_ADDR1H [7:0] bits \arg ENET_ADDRESS_MASK_BYTE5: mask ENET_MAC_ADDR1H [15:8] bits - \param[in] filter_type: select which MAC address filter type will be selected, + \param[in] filter_type: select which MAC address filter type will be selected only one parameter can be selected which is shown as below \arg ENET_ADDRESS_FILTER_SA: The MAC address is used to compared with the SA field of the received frame \arg ENET_ADDRESS_FILTER_DA: The MAC address is used to compared with the DA field of the received frame @@ -1467,7 +1505,7 @@ void enet_address_filter_disable(enet_macaddress_enum mac_addr) void enet_address_filter_config(enet_macaddress_enum mac_addr, uint32_t addr_mask, uint32_t filter_type) { uint32_t reg; - + /* get the address filter register value which is to be configured */ reg = REG32(ENET_ADDRH_BASE + mac_addr); @@ -1482,21 +1520,21 @@ void enet_address_filter_config(enet_macaddress_enum mac_addr, uint32_t addr_mas \param[in] none \param[out] none \retval ErrStatus: SUCCESS or ERROR -*/ +*/ ErrStatus enet_phy_config(void) { uint32_t ahbclk; uint32_t reg; uint16_t phy_value; ErrStatus enet_state = ERROR; - + /* clear the previous MDC clock */ reg = ENET_MAC_PHY_CTL; reg &= ~ENET_MAC_PHY_CTL_CLR; /* get the HCLK frequency */ ahbclk = rcu_clock_freq_get(CK_AHB); - + /* configure MDC clock according to HCLK frequency range */ if(ENET_RANGE(ahbclk, 20000000U, 35000000U)){ reg |= ENET_MDC_HCLK_DIV16; @@ -1507,7 +1545,7 @@ ErrStatus enet_phy_config(void) }else if(ENET_RANGE(ahbclk, 100000000U, 150000000U)){ reg |= ENET_MDC_HCLK_DIV62; }else if((ENET_RANGE(ahbclk, 150000000U, 200000000U))||(200000000U == ahbclk)){ - reg |= ENET_MDC_HCLK_DIV102; + reg |= ENET_MDC_HCLK_DIV102; }else{ return enet_state; } @@ -1518,9 +1556,9 @@ ErrStatus enet_phy_config(void) if(ERROR == (enet_phy_write_read(ENET_PHY_WRITE, PHY_ADDRESS, PHY_REG_BCR, &phy_value))){ return enet_state; } - /* PHY reset need some time */ + /* PHY reset need some time */ _ENET_DELAY_(ENET_DELAY_TO); - + /* check whether PHY reset is complete */ if(ERROR == (enet_phy_write_read(ENET_PHY_READ, PHY_ADDRESS, PHY_REG_BCR, &phy_value))){ return enet_state; @@ -1530,18 +1568,18 @@ ErrStatus enet_phy_config(void) if(RESET == (phy_value & PHY_RESET)){ enet_state = SUCCESS; } - + return enet_state; } /*! \brief write to / read from a PHY register - \param[in] direction: only one parameter can be selected which is shown as below + \param[in] direction: only one parameter can be selected which is shown as below, refer to enet_phydirection_enum \arg ENET_PHY_WRITE: write data to phy register \arg ENET_PHY_READ: read data from phy register - \param[in] phy_address: 0x0 - 0x1F - \param[in] phy_reg: 0x0 - 0x1F - \param[in] pvalue: the value will be written to the PHY register in ENET_PHY_WRITE direction + \param[in] phy_address: 0x0000 - 0x001F + \param[in] phy_reg: 0x0000 - 0x001F + \param[in] pvalue: the value will be written to the PHY register in ENET_PHY_WRITE direction \param[out] pvalue: the value will be read from the PHY register in ENET_PHY_READ direction \retval ErrStatus: SUCCESS or ERROR */ @@ -1551,16 +1589,16 @@ ErrStatus enet_phy_write_read(enet_phydirection_enum direction, uint16_t phy_add uint32_t timeout = 0U; ErrStatus enet_state = ERROR; - /* configure ENET_MAC_PHY_CTL with write/read operation */ + /* configure ENET_MAC_PHY_CTL with write/read operation */ reg = ENET_MAC_PHY_CTL; reg &= ~(ENET_MAC_PHY_CTL_PB | ENET_MAC_PHY_CTL_PW | ENET_MAC_PHY_CTL_PR | ENET_MAC_PHY_CTL_PA); - reg |= (direction | MAC_PHY_CTL_PR(phy_reg) | MAC_PHY_CTL_PA(phy_address) | ENET_MAC_PHY_CTL_PB); + reg |= (direction | MAC_PHY_CTL_PR(phy_reg) | MAC_PHY_CTL_PA(phy_address) | ENET_MAC_PHY_CTL_PB); /* if do the write operation, write value to the register */ if(ENET_PHY_WRITE == direction){ - ENET_MAC_PHY_DATA = *pvalue; + ENET_MAC_PHY_DATA = *pvalue; } - + /* do PHY write/read operation, and wait the operation complete */ ENET_MAC_PHY_CTL = reg; do{ @@ -1569,16 +1607,16 @@ ErrStatus enet_phy_write_read(enet_phydirection_enum direction, uint16_t phy_add } while((RESET != phy_flag) && (ENET_DELAY_TO != timeout)); - /* write/read operation complete */ + /* write/read operation complete */ if(RESET == (ENET_MAC_PHY_CTL & ENET_MAC_PHY_CTL_PB)){ enet_state = SUCCESS; } - /* if do the read operation, get value from the register */ + /* if do the read operation, get value from the register */ if(ENET_PHY_READ == direction){ - *pvalue = (uint16_t)ENET_MAC_PHY_DATA; + *pvalue = (uint16_t)ENET_MAC_PHY_DATA; } - + return enet_state; } @@ -1594,7 +1632,7 @@ ErrStatus enet_phyloopback_enable(void) ErrStatus phy_state = ERROR; /* get the PHY configuration to update it */ - enet_phy_write_read(ENET_PHY_READ, PHY_ADDRESS, PHY_REG_BCR, &temp_phy); + enet_phy_write_read(ENET_PHY_READ, PHY_ADDRESS, PHY_REG_BCR, &temp_phy); /* enable the PHY loopback mode */ temp_phy |= PHY_LOOPBACK; @@ -1617,7 +1655,7 @@ ErrStatus enet_phyloopback_disable(void) ErrStatus phy_state = ERROR; /* get the PHY configuration to update it */ - enet_phy_write_read(ENET_PHY_READ, PHY_ADDRESS, PHY_REG_BCR, &temp_phy); + enet_phy_write_read(ENET_PHY_READ, PHY_ADDRESS, PHY_REG_BCR, &temp_phy); /* disable the PHY loopback mode */ temp_phy &= (uint16_t)~PHY_LOOPBACK; @@ -1630,7 +1668,7 @@ ErrStatus enet_phyloopback_disable(void) /*! \brief enable ENET forward feature - \param[in] feature: the feature of ENET forward mode, + \param[in] feature: the feature of ENET forward mode one or more parameters can be selected which are shown as below \arg ENET_AUTO_PADCRC_DROP: the function of the MAC strips the Pad/FCS field on received frames \arg ENET_TYPEFRAME_CRC_DROP: the function that FCS field(last 4 bytes) of frame will be dropped before forwarding @@ -1642,17 +1680,17 @@ ErrStatus enet_phyloopback_disable(void) void enet_forward_feature_enable(uint32_t feature) { uint32_t mask; - + mask = (feature & (~(ENET_FORWARD_ERRFRAMES | ENET_FORWARD_UNDERSZ_GOODFRAMES))); ENET_MAC_CFG |= mask; - + mask = (feature & (~(ENET_AUTO_PADCRC_DROP | ENET_TYPEFRAME_CRC_DROP))); ENET_DMA_CTL |= (mask >> 2); } /*! \brief disable ENET forward feature - \param[in] feature: the feature of ENET forward mode, + \param[in] feature: the feature of ENET forward mode one or more parameters can be selected which are shown as below \arg ENET_AUTO_PADCRC_DROP: the automatic zero-quanta generation function \arg ENET_TYPEFRAME_CRC_DROP: the flow control operation in the MAC @@ -1664,17 +1702,17 @@ void enet_forward_feature_enable(uint32_t feature) void enet_forward_feature_disable(uint32_t feature) { uint32_t mask; - + mask = (feature & (~(ENET_FORWARD_ERRFRAMES | ENET_FORWARD_UNDERSZ_GOODFRAMES))); ENET_MAC_CFG &= ~mask; - + mask = (feature & (~(ENET_AUTO_PADCRC_DROP | ENET_TYPEFRAME_CRC_DROP))); ENET_DMA_CTL &= ~(mask >> 2); } - -/*! + +/*! \brief enable ENET fliter feature - \param[in] feature: the feature of ENET fliter mode, + \param[in] feature: the feature of ENET fliter mode one or more parameters can be selected which are shown as below \arg ENET_SRC_FILTER: filter source address function \arg ENET_SRC_FILTER_INVERSE: inverse source address filtering result function @@ -1693,7 +1731,7 @@ void enet_fliter_feature_enable(uint32_t feature) /*! \brief disable ENET fliter feature - \param[in] feature: the feature of ENET fliter mode, + \param[in] feature: the feature of ENET fliter mode one or more parameters can be selected which are shown as below \arg ENET_SRC_FILTER: filter source address function \arg ENET_SRC_FILTER_INVERSE: inverse source address filtering result function @@ -1717,8 +1755,8 @@ void enet_fliter_feature_disable(uint32_t feature) \param[out] none \retval ErrStatus: ERROR or SUCCESS */ -ErrStatus enet_pauseframe_generate(void) -{ +ErrStatus enet_pauseframe_generate(void) +{ ErrStatus enet_state =ERROR; uint32_t temp = 0U; @@ -1728,16 +1766,16 @@ ErrStatus enet_pauseframe_generate(void) ENET_MAC_FCTL |= ENET_MAC_FCTL_FLCBBKPA; enet_state = SUCCESS; } - return enet_state; + return enet_state; } /*! \brief configure the pause frame detect type - \param[in] detect: pause frame detect type, + \param[in] detect: pause frame detect type only one parameter can be selected which is shown as below \arg ENET_MAC0_AND_UNIQUE_ADDRESS_PAUSEDETECT: besides the unique multicast address, MAC can also use the MAC0 address to detecting pause frame - \arg ENET_UNIQUE_PAUSEDETECT: only the unique multicast address for pause frame which is specified + \arg ENET_UNIQUE_PAUSEDETECT: only the unique multicast address for pause frame which is specified in IEEE802.3 can be detected \param[out] none \retval none @@ -1751,9 +1789,9 @@ void enet_pauseframe_detect_config(uint32_t detect) /*! \brief configure the pause frame parameters \param[in] pausetime: pause time in transmit pause control frame - \param[in] pause_threshold: the threshold of the pause timer for retransmitting frames automatically, - this value must make sure to be less than configured pause time, only one parameter can be - selected which is shown as below + \param[in] pause_threshold: the threshold of the pause timer for retransmitting frames automatically + this value must make sure to be less than configured pause time + only one parameter can be selected which is shown as below \arg ENET_PAUSETIME_MINUS4: pause time minus 4 slot times \arg ENET_PAUSETIME_MINUS28: pause time minus 28 slot times \arg ENET_PAUSETIME_MINUS144: pause time minus 144 slot times @@ -1769,9 +1807,9 @@ void enet_pauseframe_config(uint32_t pausetime, uint32_t pause_threshold) /*! \brief configure the threshold of the flow control(deactive and active threshold) - \param[in] deactive: the threshold of the deactive flow control, this value - should always be less than active flow control value, only one - parameter can be selected which is shown as below + \param[in] deactive: the threshold of the deactive flow control + this value should always be less than active flow control value + only one parameter can be selected which is shown as below \arg ENET_DEACTIVE_THRESHOLD_256BYTES: threshold level is 256 bytes \arg ENET_DEACTIVE_THRESHOLD_512BYTES: threshold level is 512 bytes \arg ENET_DEACTIVE_THRESHOLD_768BYTES: threshold level is 768 bytes @@ -1779,8 +1817,8 @@ void enet_pauseframe_config(uint32_t pausetime, uint32_t pause_threshold) \arg ENET_DEACTIVE_THRESHOLD_1280BYTES: threshold level is 1280 bytes \arg ENET_DEACTIVE_THRESHOLD_1536BYTES: threshold level is 1536 bytes \arg ENET_DEACTIVE_THRESHOLD_1792BYTES: threshold level is 1792 bytes - \param[in] active: the threshold of the active flow control, only one parameter - can be selected which is shown as below + \param[in] active: the threshold of the active flow control + only one parameter can be selected which is shown as below \arg ENET_ACTIVE_THRESHOLD_256BYTES: threshold level is 256 bytes \arg ENET_ACTIVE_THRESHOLD_512BYTES: threshold level is 512 bytes \arg ENET_ACTIVE_THRESHOLD_768BYTES: threshold level is 768 bytes @@ -1793,7 +1831,7 @@ void enet_pauseframe_config(uint32_t pausetime, uint32_t pause_threshold) */ void enet_flowcontrol_threshold_config(uint32_t deactive, uint32_t active) { - ENET_MAC_FCTH = ((deactive | active) >> 8); + ENET_MAC_FCTH = ((deactive | active) >> 8); } /*! @@ -1838,8 +1876,8 @@ void enet_flowcontrol_feature_disable(uint32_t feature) /*! \brief get the dma transmit/receive process state - \param[in] direction: choose the direction of dma process which users want to check, - refer to enet_dmadirection_enum, only one parameter can be selected which is shown as below + \param[in] direction: choose the direction of dma process which users want to check, refer to enet_dmadirection_enum + only one parameter can be selected which is shown as below \arg ENET_DMA_TX: dma transmit process \arg ENET_DMA_RX: dma receive process \param[out] none @@ -1857,10 +1895,10 @@ uint32_t enet_dmaprocess_state_get(enet_dmadirection_enum direction) } /*! - \brief poll the DMA transmission/reception enable by writing any value to the + \brief poll the DMA transmission/reception enable by writing any value to the ENET_DMA_TPEN/ENET_DMA_RPEN register, this will make the DMA to resume transmission/reception - \param[in] direction: choose the direction of DMA process which users want to resume, - refer to enet_dmadirection_enum, only one parameter can be selected which is shown as below + \param[in] direction: choose the direction of DMA process which users want to resume, refer to enet_dmadirection_enum + only one parameter can be selected which is shown as below \arg ENET_DMA_TX: DMA transmit process \arg ENET_DMA_RX: DMA receive process \param[out] none @@ -1876,7 +1914,7 @@ void enet_dmaprocess_resume(enet_dmadirection_enum direction) } /*! - \brief check and recover the Rx process + \brief check and recover the Rx process \param[in] none \param[out] none \retval none @@ -1885,11 +1923,11 @@ void enet_rxprocess_check_recovery(void) { uint32_t status; - /* get DAV information of current RxDMA descriptor */ + /* get DAV information of current RxDMA descriptor */ status = dma_current_rxdesc->status; status &= ENET_RDES0_DAV; - - /* if current descriptor is owned by DMA, but the descriptor address mismatches with + + /* if current descriptor is owned by DMA, but the descriptor address mismatches with receive descriptor address pointer updated by RxDMA controller */ if((ENET_DMA_CRDADDR != ((uint32_t)dma_current_rxdesc)) && (ENET_RDES0_DAV == status)){ @@ -1908,25 +1946,25 @@ ErrStatus enet_txfifo_flush(void) uint32_t flush_state; uint32_t timeout = 0U; ErrStatus enet_state = ERROR; - + /* set the FTF bit for flushing transmit FIFO */ - ENET_DMA_CTL |= ENET_DMA_CTL_FTF; + ENET_DMA_CTL |= ENET_DMA_CTL_FTF; /* wait until the flush operation completes */ do{ - flush_state = ENET_DMA_CTL & ENET_DMA_CTL_FTF; + flush_state = ENET_DMA_CTL & ENET_DMA_CTL_FTF; timeout++; }while((RESET != flush_state) && (timeout < ENET_DELAY_TO)); /* return ERROR due to timeout */ if(RESET == flush_state){ enet_state = SUCCESS; } - + return enet_state; } /*! \brief get the transmit/receive address of current descriptor, or current buffer, or descriptor table - \param[in] addr_get: choose the address which users want to get, refer to enet_desc_reg_enum, + \param[in] addr_get: choose the address which users want to get, refer to enet_desc_reg_enum only one parameter can be selected which is shown as below \arg ENET_RX_DESC_TABLE: the start address of the receive descriptor table \arg ENET_RX_CURRENT_DESC: the start descriptor address of the current receive descriptor read by @@ -1936,7 +1974,7 @@ ErrStatus enet_txfifo_flush(void) \arg ENET_TX_CURRENT_DESC: the start descriptor address of the current transmit descriptor read by the TxDMA controller \arg ENET_TX_CURRENT_BUFFER: the current transmit buffer address being read by the TxDMA controller - \param[out] none + \param[out] none \retval address value */ uint32_t enet_current_desc_address_get(enet_desc_reg_enum addr_get) @@ -1950,7 +1988,7 @@ uint32_t enet_current_desc_address_get(enet_desc_reg_enum addr_get) /*! \brief get the Tx or Rx descriptor information \param[in] desc: the descriptor pointer which users want to get information - \param[in] info_get: the descriptor information type which is selected, + \param[in] info_get: the descriptor information type which is selected, refer to enet_descstate_enum only one parameter can be selected which is shown as below \arg RXDESC_BUFFER_1_SIZE: receive buffer 1 size \arg RXDESC_BUFFER_2_SIZE: receive buffer 2 size @@ -1971,25 +2009,30 @@ uint32_t enet_desc_information_get(enet_descriptors_struct *desc, enet_descstate break; case RXDESC_BUFFER_2_SIZE: reval = GET_RDES1_RB2S(desc->control_buffer_size); - break; - case RXDESC_FRAME_LENGTH: + break; + case RXDESC_FRAME_LENGTH: reval = GET_RDES0_FRML(desc->status); - reval = reval - 4U; - - /* if is a type frame, and CRC is not included in forwarding frame */ - if((RESET != (ENET_MAC_CFG & ENET_MAC_CFG_TFCD)) && (RESET != (desc->status & ENET_RDES0_FRMT))){ - reval = reval + 4U; - } + if(reval > 4U){ + reval = reval - 4U; + + /* if is a type frame, and CRC is not included in forwarding frame */ + if((RESET != (ENET_MAC_CFG & ENET_MAC_CFG_TFCD)) && (RESET != (desc->status & ENET_RDES0_FRMT))){ + reval = reval + 4U; + } + }else{ + reval = 0U; + } + break; - case RXDESC_BUFFER_1_ADDR: - reval = desc->buffer1_addr; + case RXDESC_BUFFER_1_ADDR: + reval = desc->buffer1_addr; break; - case TXDESC_BUFFER_1_ADDR: - reval = desc->buffer1_addr; + case TXDESC_BUFFER_1_ADDR: + reval = desc->buffer1_addr; break; - case TXDESC_COLLISION_COUNT: + case TXDESC_COLLISION_COUNT: reval = GET_TDES0_COCNT(desc->status); - break; + break; default: break; } @@ -2006,7 +2049,7 @@ uint32_t enet_desc_information_get(enet_descriptors_struct *desc, enet_descstate void enet_missed_frame_counter_get(uint32_t *rxfifo_drop, uint32_t *rxdma_drop) { uint32_t temp_counter = 0U; - + temp_counter = ENET_DMA_MFBOCNT; *rxfifo_drop = GET_DMA_MFBOCNT_MSFA(temp_counter); *rxdma_drop = GET_DMA_MFBOCNT_MSFC(temp_counter); @@ -2015,9 +2058,9 @@ void enet_missed_frame_counter_get(uint32_t *rxfifo_drop, uint32_t *rxdma_drop) /*! \brief get the bit flag of ENET DMA descriptor \param[in] desc: the descriptor pointer which users want to get flag - \param[in] desc_flag: the bit flag of ENET DMA descriptor, + \param[in] desc_flag: the bit flag of ENET DMA descriptor only one parameter can be selected which is shown as below - \arg ENET_TDES0_DB: deferred + \arg ENET_TDES0_DB: deferred \arg ENET_TDES0_UFE: underflow error \arg ENET_TDES0_EXD: excessive deferral \arg ENET_TDES0_VFRM: VLAN frame @@ -2030,18 +2073,18 @@ void enet_missed_frame_counter_get(uint32_t *rxfifo_drop, uint32_t *rxdma_drop) \arg ENET_TDES0_JT: jabber timeout \arg ENET_TDES0_ES: error summary \arg ENET_TDES0_IPHE: IP header error - \arg ENET_TDES0_TTMSS: transmit timestamp status + \arg ENET_TDES0_TTMSS: transmit timestamp status \arg ENET_TDES0_TCHM: the second address chained mode \arg ENET_TDES0_TERM: transmit end of ring mode \arg ENET_TDES0_TTSEN: transmit timestamp function enable - \arg ENET_TDES0_DPAD: disable adding pad + \arg ENET_TDES0_DPAD: disable adding pad \arg ENET_TDES0_DCRC: disable CRC \arg ENET_TDES0_FSG: first segment \arg ENET_TDES0_LSG: last segment \arg ENET_TDES0_INTC: interrupt on completion \arg ENET_TDES0_DAV: DAV bit - - \arg ENET_RDES0_PCERR: payload checksum error + + \arg ENET_RDES0_PCERR: payload checksum error \arg ENET_RDES0_EXSV: extended status valid \arg ENET_RDES0_CERR: CRC error \arg ENET_RDES0_DBERR: dribble bit error @@ -2054,11 +2097,11 @@ void enet_missed_frame_counter_get(uint32_t *rxfifo_drop, uint32_t *rxdma_drop) \arg ENET_RDES0_LDES: last descriptor \arg ENET_RDES0_FDES: first descriptor \arg ENET_RDES0_VTAG: VLAN tag - \arg ENET_RDES0_OERR: overflow error + \arg ENET_RDES0_OERR: overflow error \arg ENET_RDES0_LERR: length error \arg ENET_RDES0_SAFF: SA filter fail \arg ENET_RDES0_DERR: descriptor error - \arg ENET_RDES0_ERRS: error summary + \arg ENET_RDES0_ERRS: error summary \arg ENET_RDES0_DAFF: destination address filter fail \arg ENET_RDES0_DAV: descriptor available \param[out] none @@ -2067,7 +2110,7 @@ void enet_missed_frame_counter_get(uint32_t *rxfifo_drop, uint32_t *rxdma_drop) FlagStatus enet_desc_flag_get(enet_descriptors_struct *desc, uint32_t desc_flag) { FlagStatus enet_flag = RESET; - + if ((uint32_t)RESET != (desc->status & desc_flag)){ enet_flag = SET; } @@ -2078,20 +2121,20 @@ FlagStatus enet_desc_flag_get(enet_descriptors_struct *desc, uint32_t desc_flag) /*! \brief set the bit flag of ENET DMA descriptor \param[in] desc: the descriptor pointer which users want to set flag - \param[in] desc_flag: the bit flag of ENET DMA descriptor, + \param[in] desc_flag: the bit flag of ENET DMA descriptor only one parameter can be selected which is shown as below \arg ENET_TDES0_VFRM: VLAN frame \arg ENET_TDES0_FRMF: frame flushed \arg ENET_TDES0_TCHM: the second address chained mode \arg ENET_TDES0_TERM: transmit end of ring mode \arg ENET_TDES0_TTSEN: transmit timestamp function enable - \arg ENET_TDES0_DPAD: disable adding pad + \arg ENET_TDES0_DPAD: disable adding pad \arg ENET_TDES0_DCRC: disable CRC \arg ENET_TDES0_FSG: first segment \arg ENET_TDES0_LSG: last segment \arg ENET_TDES0_INTC: interrupt on completion \arg ENET_TDES0_DAV: DAV bit - \arg ENET_RDES0_DAV: descriptor available + \arg ENET_RDES0_DAV: descriptor available \param[out] none \retval none */ @@ -2103,20 +2146,20 @@ void enet_desc_flag_set(enet_descriptors_struct *desc, uint32_t desc_flag) /*! \brief clear the bit flag of ENET DMA descriptor \param[in] desc: the descriptor pointer which users want to clear flag - \param[in] desc_flag: the bit flag of ENET DMA descriptor, + \param[in] desc_flag: the bit flag of ENET DMA descriptor only one parameter can be selected which is shown as below \arg ENET_TDES0_VFRM: VLAN frame \arg ENET_TDES0_FRMF: frame flushed \arg ENET_TDES0_TCHM: the second address chained mode \arg ENET_TDES0_TERM: transmit end of ring mode \arg ENET_TDES0_TTSEN: transmit timestamp function enable - \arg ENET_TDES0_DPAD: disable adding pad + \arg ENET_TDES0_DPAD: disable adding pad \arg ENET_TDES0_DCRC: disable CRC \arg ENET_TDES0_FSG: first segment \arg ENET_TDES0_LSG: last segment \arg ENET_TDES0_INTC: interrupt on completion \arg ENET_TDES0_DAV: DAV bit - \arg ENET_RDES0_DAV: descriptor available + \arg ENET_RDES0_DAV: descriptor available \param[out] none \retval none */ @@ -2126,7 +2169,7 @@ void enet_desc_flag_clear(enet_descriptors_struct *desc, uint32_t desc_flag) } /*! - \brief when receiving completed, set RS bit in ENET_DMA_STAT register will immediately set + \brief when receiving completed, set RS bit in ENET_DMA_STAT register will immediately set \param[in] desc: the descriptor pointer which users want to configure \param[out] none \retval none @@ -2137,9 +2180,9 @@ void enet_rx_desc_immediate_receive_complete_interrupt(enet_descriptors_struct * } /*! - \brief when receiving completed, set RS bit in ENET_DMA_STAT register will is set after a configurable delay time + \brief when receiving completed, set RS bit in ENET_DMA_STAT register will is set after a configurable delay time \param[in] desc: the descriptor pointer which users want to configure - \param[in] delay_time: delay a time of 256*delay_time HCLK, this value must be between 0 and 0xFF + \param[in] delay_time: delay a time of 256*delay_time HCLK(0x00000000 - 0x000000FF) \param[out] none \retval none */ @@ -2158,10 +2201,10 @@ void enet_rx_desc_delay_receive_complete_interrupt(enet_descriptors_struct *desc void enet_rxframe_drop(void) { /* enable reception, descriptor is owned by DMA */ - dma_current_rxdesc->status = ENET_RDES0_DAV; - + dma_current_rxdesc->status = ENET_RDES0_DAV; + /* chained mode */ - if((uint32_t)RESET != (dma_current_rxdesc->control_buffer_size & ENET_RDES1_RCHM)){ + if((uint32_t)RESET != (dma_current_rxdesc->control_buffer_size & ENET_RDES1_RCHM)){ if(NULL != dma_current_ptp_rxdesc){ dma_current_rxdesc = (enet_descriptors_struct*) (dma_current_ptp_rxdesc->buffer2_next_desc_addr); /* if it is the last ptp descriptor */ @@ -2175,9 +2218,9 @@ void enet_rxframe_drop(void) }else{ dma_current_rxdesc = (enet_descriptors_struct*) (dma_current_rxdesc->buffer2_next_desc_addr); } - + }else{ - /* ring mode */ + /* ring mode */ if((uint32_t)RESET != (dma_current_rxdesc->control_buffer_size & ENET_RDES1_RERM)){ /* if is the last descriptor in table, the next descriptor is the table header */ dma_current_rxdesc = (enet_descriptors_struct*) (ENET_DMA_RDTADDR); @@ -2196,9 +2239,9 @@ void enet_rxframe_drop(void) /*! \brief enable DMA feature - \param[in] feature: the feature of DMA mode, + \param[in] feature: the feature of DMA mode one or more parameters can be selected which are shown as below - \arg ENET_FLUSH_RXFRAME: RxDMA flushes frames function + \arg ENET_NO_FLUSH_RXFRAME: RxDMA does not flushes frames function \arg ENET_SECONDFRAME_OPT: TxDMA controller operate on second frame function \param[out] none \retval none @@ -2210,9 +2253,9 @@ void enet_dma_feature_enable(uint32_t feature) /*! \brief disable DMA feature - \param[in] feature: the feature of DMA mode, + \param[in] feature: the feature of DMA mode one or more parameters can be selected which are shown as below - \arg ENET_FLUSH_RXFRAME: RxDMA flushes frames function + \arg ENET_NO_FLUSH_RXFRAME: RxDMA does not flushes frames function \arg ENET_SECONDFRAME_OPT: TxDMA controller operate on second frame function \param[out] none \retval none @@ -2226,7 +2269,7 @@ void enet_dma_feature_disable(uint32_t feature) /*! \brief get the bit of extended status flag in ENET DMA descriptor \param[in] desc: the descriptor pointer which users want to get the extended status flag - \param[in] desc_status: the extended status want to get, + \param[in] desc_status: the extended status want to get only one parameter can be selected which is shown as below \arg ENET_RDES4_IPPLDT: IP frame payload type \arg ENET_RDES4_IPHERR: IP frame header error @@ -2243,7 +2286,7 @@ void enet_dma_feature_disable(uint32_t feature) uint32_t enet_rx_desc_enhanced_status_get(enet_descriptors_struct *desc, uint32_t desc_status) { uint32_t reval = 0xFFFFFFFFU; - + switch (desc_status){ case ENET_RDES4_IPPLDT: reval = GET_RDES4_IPPLDT(desc->extended_status); @@ -2256,9 +2299,9 @@ uint32_t enet_rx_desc_enhanced_status_get(enet_descriptors_struct *desc, uint32_ reval = 1U; }else{ reval = 0U; - } + } } - + return reval; } @@ -2275,7 +2318,7 @@ void enet_desc_select_enhanced_mode(void) /*! \brief initialize the DMA Tx/Rx descriptors's parameters in enhanced chain mode with ptp function - \param[in] direction: the descriptors which users want to init, refer to enet_dmadirection_enum, + \param[in] direction: the descriptors which users want to init, refer to enet_dmadirection_enum only one parameter can be selected which is shown as below \arg ENET_DMA_TX: DMA Tx descriptors \arg ENET_DMA_RX: DMA Rx descriptors @@ -2288,18 +2331,18 @@ void enet_ptp_enhanced_descriptors_chain_init(enet_dmadirection_enum direction) uint32_t desc_status = 0U, desc_bufsize = 0U; enet_descriptors_struct *desc, *desc_tab; uint8_t *buf; - + /* if want to initialize DMA Tx descriptors */ if (ENET_DMA_TX == direction){ /* save a copy of the DMA Tx descriptors */ desc_tab = txdesc_tab; buf = &tx_buff[0][0]; count = ENET_TXBUF_NUM; - maxsize = ENET_TXBUF_SIZE; - + maxsize = ENET_TXBUF_SIZE; + /* select chain mode, and enable transmit timestamp function */ desc_status = ENET_TDES0_TCHM | ENET_TDES0_TTSEN; - + /* configure DMA Tx descriptor table address register */ ENET_DMA_TDTADDR = (uint32_t)desc_tab; dma_current_txdesc = desc_tab; @@ -2309,43 +2352,43 @@ void enet_ptp_enhanced_descriptors_chain_init(enet_dmadirection_enum direction) desc_tab = rxdesc_tab; buf = &rx_buff[0][0]; count = ENET_RXBUF_NUM; - maxsize = ENET_RXBUF_SIZE; - + maxsize = ENET_RXBUF_SIZE; + /* enable receiving */ desc_status = ENET_RDES0_DAV; /* select receive chained mode and set buffer1 size */ desc_bufsize = ENET_RDES1_RCHM | (uint32_t)ENET_RXBUF_SIZE; - + /* configure DMA Rx descriptor table address register */ ENET_DMA_RDTADDR = (uint32_t)desc_tab; - dma_current_rxdesc = desc_tab; + dma_current_rxdesc = desc_tab; } - - /* configuration each descriptor */ + + /* configuration each descriptor */ for(num = 0U; num < count; num++){ /* get the pointer to the next descriptor of the descriptor table */ desc = desc_tab + num; /* configure descriptors */ - desc->status = desc_status; + desc->status = desc_status; desc->control_buffer_size = desc_bufsize; desc->buffer1_addr = (uint32_t)(&buf[num * maxsize]); - + /* if is not the last descriptor */ if(num < (count - 1U)){ /* configure the next descriptor address */ desc->buffer2_next_desc_addr = (uint32_t)(desc_tab + num + 1U); }else{ - /* when it is the last descriptor, the next descriptor address - equals to first descriptor address in descriptor table */ - desc->buffer2_next_desc_addr = (uint32_t)desc_tab; + /* when it is the last descriptor, the next descriptor address + equals to first descriptor address in descriptor table */ + desc->buffer2_next_desc_addr = (uint32_t)desc_tab; } - } + } } /*! \brief initialize the DMA Tx/Rx descriptors's parameters in enhanced ring mode with ptp function - \param[in] direction: the descriptors which users want to init, refer to enet_dmadirection_enum, + \param[in] direction: the descriptors which users want to init, refer to enet_dmadirection_enum only one parameter can be selected which is shown as below \arg ENET_DMA_TX: DMA Tx descriptors \arg ENET_DMA_RX: DMA Rx descriptors @@ -2358,23 +2401,23 @@ void enet_ptp_enhanced_descriptors_ring_init(enet_dmadirection_enum direction) uint32_t desc_status = 0U, desc_bufsize = 0U; enet_descriptors_struct *desc; enet_descriptors_struct *desc_tab; - uint8_t *buf; - + uint8_t *buf; + /* configure descriptor skip length */ ENET_DMA_BCTL &= ~ENET_DMA_BCTL_DPSL; ENET_DMA_BCTL |= DMA_BCTL_DPSL(0); - + /* if want to initialize DMA Tx descriptors */ if (ENET_DMA_TX == direction){ /* save a copy of the DMA Tx descriptors */ desc_tab = txdesc_tab; buf = &tx_buff[0][0]; count = ENET_TXBUF_NUM; - maxsize = ENET_TXBUF_SIZE; + maxsize = ENET_TXBUF_SIZE; /* select ring mode, and enable transmit timestamp function */ desc_status = ENET_TDES0_TTSEN; - + /* configure DMA Tx descriptor table address register */ ENET_DMA_TDTADDR = (uint32_t)desc_tab; dma_current_txdesc = desc_tab; @@ -2384,43 +2427,43 @@ void enet_ptp_enhanced_descriptors_ring_init(enet_dmadirection_enum direction) desc_tab = rxdesc_tab; buf = &rx_buff[0][0]; count = ENET_RXBUF_NUM; - maxsize = ENET_RXBUF_SIZE; - + maxsize = ENET_RXBUF_SIZE; + /* enable receiving */ desc_status = ENET_RDES0_DAV; /* set buffer1 size */ desc_bufsize = ENET_RXBUF_SIZE; - + /* configure DMA Rx descriptor table address register */ ENET_DMA_RDTADDR = (uint32_t)desc_tab; - dma_current_rxdesc = desc_tab; + dma_current_rxdesc = desc_tab; } - - /* configure each descriptor */ + + /* configure each descriptor */ for(num=0U; num < count; num++){ /* get the pointer to the next descriptor of the descriptor table */ desc = desc_tab + num; /* configure descriptors */ - desc->status = desc_status; - desc->control_buffer_size = desc_bufsize; - desc->buffer1_addr = (uint32_t)(&buf[num * maxsize]); - + desc->status = desc_status; + desc->control_buffer_size = desc_bufsize; + desc->buffer1_addr = (uint32_t)(&buf[num * maxsize]); + /* when it is the last descriptor */ if(num == (count - 1U)){ if (ENET_DMA_TX == direction){ - /* configure transmit end of ring mode */ + /* configure transmit end of ring mode */ desc->status |= ENET_TDES0_TERM; }else{ /* configure receive end of ring mode */ desc->control_buffer_size |= ENET_RDES1_RERM; } } - } + } } /*! - \brief receive a packet data with timestamp values to application buffer, when the DMA is in enhanced mode + \brief receive a packet data with timestamp values to application buffer, when the DMA is in enhanced mode \param[in] bufsize: the size of buffer which is the parameter in function \param[out] buffer: pointer to the application buffer note -- if the input is NULL, user should copy data in application by himself @@ -2433,26 +2476,26 @@ ErrStatus enet_ptpframe_receive_enhanced_mode(uint8_t *buffer, uint32_t bufsize, uint32_t offset = 0U, size = 0U; uint32_t timeout = 0U; uint32_t rdes0_tsv_flag; - + /* the descriptor is busy due to own by the DMA */ if((uint32_t)RESET != (dma_current_rxdesc->status & ENET_RDES0_DAV)){ - return ERROR; + return ERROR; } - + /* if buffer pointer is null, indicates that users has copied data in application */ if(NULL != buffer){ - /* if no error occurs, and the frame uses only one descriptor */ - if(((uint32_t)RESET == (dma_current_rxdesc->status & ENET_RDES0_ERRS)) && - ((uint32_t)RESET != (dma_current_rxdesc->status & ENET_RDES0_LDES)) && - ((uint32_t)RESET != (dma_current_rxdesc->status & ENET_RDES0_FDES))){ + /* if no error occurs, and the frame uses only one descriptor */ + if(((uint32_t)RESET == (dma_current_rxdesc->status & ENET_RDES0_ERRS)) && + ((uint32_t)RESET != (dma_current_rxdesc->status & ENET_RDES0_LDES)) && + ((uint32_t)RESET != (dma_current_rxdesc->status & ENET_RDES0_FDES))){ /* get the frame length except CRC */ size = GET_RDES0_FRML(dma_current_rxdesc->status) - 4U; - /* if is a type frame, and CRC is not included in forwarding frame */ + /* if is a type frame, and CRC is not included in forwarding frame */ if((RESET != (ENET_MAC_CFG & ENET_MAC_CFG_TFCD)) && (RESET != (dma_current_rxdesc->status & ENET_RDES0_FRMT))){ size = size + 4U; } - + /* to avoid situation that the frame size exceeds the buffer length */ if(size > bufsize){ return ERROR; @@ -2465,22 +2508,22 @@ ErrStatus enet_ptpframe_receive_enhanced_mode(uint8_t *buffer, uint32_t bufsize, }else{ return ERROR; } - } - + } + /* if timestamp pointer is null, indicates that users don't care timestamp in application */ if(NULL != timestamp){ /* wait for ENET_RDES0_TSV flag to be set, the timestamp value is taken and write to the RDES6 and RDES7 */ - do{ + do{ rdes0_tsv_flag = (dma_current_rxdesc->status & ENET_RDES0_TSV); timeout++; }while ((RESET == rdes0_tsv_flag) && (timeout < ENET_DELAY_TO)); - + /* return ERROR due to timeout */ if(ENET_DELAY_TO == timeout){ return ERROR; } - + /* clear the ENET_RDES0_TSV flag */ dma_current_rxdesc->status &= ~ENET_RDES0_TSV; /* get the timestamp value of the received frame */ @@ -2490,7 +2533,7 @@ ErrStatus enet_ptpframe_receive_enhanced_mode(uint8_t *buffer, uint32_t bufsize, /* enable reception, descriptor is owned by DMA */ dma_current_rxdesc->status = ENET_RDES0_DAV; - + /* check Rx buffer unavailable flag status */ if ((uint32_t)RESET != (ENET_DMA_STAT & ENET_DMA_STAT_RBU)){ /* Clear RBU flag */ @@ -2498,33 +2541,32 @@ ErrStatus enet_ptpframe_receive_enhanced_mode(uint8_t *buffer, uint32_t bufsize, /* resume DMA reception by writing to the RPEN register*/ ENET_DMA_RPEN = 0; } - - /* update the current RxDMA descriptor pointer to the next decriptor in RxDMA decriptor table */ + + /* update the current RxDMA descriptor pointer to the next decriptor in RxDMA decriptor table */ /* chained mode */ - if((uint32_t)RESET != (dma_current_rxdesc->control_buffer_size & ENET_RDES1_RCHM)){ - dma_current_rxdesc = (enet_descriptors_struct*) (dma_current_rxdesc->buffer2_next_desc_addr); - }else{ - /* ring mode */ + if((uint32_t)RESET != (dma_current_rxdesc->control_buffer_size & ENET_RDES1_RCHM)){ + dma_current_rxdesc = (enet_descriptors_struct*) (dma_current_rxdesc->buffer2_next_desc_addr); + }else{ + /* ring mode */ if((uint32_t)RESET != (dma_current_rxdesc->control_buffer_size & ENET_RDES1_RERM)){ /* if is the last descriptor in table, the next descriptor is the table header */ - dma_current_rxdesc = (enet_descriptors_struct*) (ENET_DMA_RDTADDR); - }else{ + dma_current_rxdesc = (enet_descriptors_struct*) (ENET_DMA_RDTADDR); + }else{ /* the next descriptor is the current address, add the descriptor size, and descriptor skip length */ - dma_current_rxdesc = (enet_descriptors_struct*) ((uint32_t)dma_current_rxdesc + ETH_DMARXDESC_SIZE + GET_DMA_BCTL_DPSL(ENET_DMA_BCTL)); + dma_current_rxdesc = (enet_descriptors_struct*) ((uint32_t)dma_current_rxdesc + ETH_DMARXDESC_SIZE + GET_DMA_BCTL_DPSL(ENET_DMA_BCTL)); } } - + return SUCCESS; } /*! - \brief send data with timestamp values in application buffer as a transmit packet, when the DMA is in enhanced mode + \brief send data with timestamp values in application buffer as a transmit packet, when the DMA is in enhanced mode \param[in] buffer: pointer on the application buffer note -- if the input is NULL, user should copy data in application by himself \param[in] length: the length of frame data to be transmitted \param[out] timestamp: pointer to the table which stores the timestamp high and low note -- if the input is NULL, timestamp is ignored - \param[out] none \retval ErrStatus: SUCCESS or ERROR */ ErrStatus enet_ptpframe_transmit_enhanced_mode(uint8_t *buffer, uint32_t length, uint32_t timestamp[]) @@ -2532,17 +2574,17 @@ ErrStatus enet_ptpframe_transmit_enhanced_mode(uint8_t *buffer, uint32_t length, uint32_t offset = 0; uint32_t dma_tbu_flag, dma_tu_flag; uint32_t tdes0_ttmss_flag; - uint32_t timeout = 0; - + uint32_t timeout = 0; + /* the descriptor is busy due to own by the DMA */ if((uint32_t)RESET != (dma_current_txdesc->status & ENET_TDES0_DAV)){ return ERROR; } - + /* only frame length no more than ENET_MAX_FRAME_SIZE is allowed */ if(length > ENET_MAX_FRAME_SIZE){ return ERROR; - } + } /* if buffer pointer is null, indicates that users has handled data in application */ if(NULL != buffer){ @@ -2553,22 +2595,22 @@ ErrStatus enet_ptpframe_transmit_enhanced_mode(uint8_t *buffer, uint32_t length, } /* set the frame length */ dma_current_txdesc->control_buffer_size = length; - /* set the segment of frame, frame is transmitted in one descriptor */ + /* set the segment of frame, frame is transmitted in one descriptor */ dma_current_txdesc->status |= ENET_TDES0_LSG | ENET_TDES0_FSG; /* enable the DMA transmission */ dma_current_txdesc->status |= ENET_TDES0_DAV; /* check Tx buffer unavailable flag status */ - dma_tbu_flag = (ENET_DMA_STAT & ENET_DMA_STAT_TBU); + dma_tbu_flag = (ENET_DMA_STAT & ENET_DMA_STAT_TBU); dma_tu_flag = (ENET_DMA_STAT & ENET_DMA_STAT_TU); - + if ((RESET != dma_tbu_flag) || (RESET != dma_tu_flag)){ /* Clear TBU and TU flag */ ENET_DMA_STAT = (dma_tbu_flag | dma_tu_flag); /* resume DMA transmission by writing to the TPEN register*/ ENET_DMA_TPEN = 0; } - + /* if timestamp pointer is null, indicates that users don't care timestamp in application */ if(NULL != timestamp){ /* wait for ENET_TDES0_TTMSS flag to be set, a timestamp was captured */ @@ -2576,12 +2618,12 @@ ErrStatus enet_ptpframe_transmit_enhanced_mode(uint8_t *buffer, uint32_t length, tdes0_ttmss_flag = (dma_current_txdesc->status & ENET_TDES0_TTMSS); timeout++; }while((RESET == tdes0_ttmss_flag) && (timeout < ENET_DELAY_TO)); - + /* return ERROR due to timeout */ if(ENET_DELAY_TO == timeout){ return ERROR; } - + /* clear the ENET_TDES0_TTMSS flag */ dma_current_txdesc->status &= ~ENET_TDES0_TTMSS; /* get the timestamp value of the transmit frame */ @@ -2589,16 +2631,16 @@ ErrStatus enet_ptpframe_transmit_enhanced_mode(uint8_t *buffer, uint32_t length, timestamp[1] = dma_current_txdesc->timestamp_high; } - /* update the current TxDMA descriptor pointer to the next decriptor in TxDMA decriptor table*/ + /* update the current TxDMA descriptor pointer to the next decriptor in TxDMA decriptor table*/ /* chained mode */ - if((uint32_t)RESET != (dma_current_txdesc->status & ENET_TDES0_TCHM)){ - dma_current_txdesc = (enet_descriptors_struct*) (dma_current_txdesc->buffer2_next_desc_addr); + if((uint32_t)RESET != (dma_current_txdesc->status & ENET_TDES0_TCHM)){ + dma_current_txdesc = (enet_descriptors_struct*) (dma_current_txdesc->buffer2_next_desc_addr); }else{ - /* ring mode */ + /* ring mode */ if((uint32_t)RESET != (dma_current_txdesc->status & ENET_TDES0_TERM)){ /* if is the last descriptor in table, the next descriptor is the table header */ - dma_current_txdesc = (enet_descriptors_struct*) (ENET_DMA_TDTADDR); - }else{ + dma_current_txdesc = (enet_descriptors_struct*) (ENET_DMA_TDTADDR); + }else{ /* the next descriptor is the current address, add the descriptor size, and descriptor skip length */ dma_current_txdesc = (enet_descriptors_struct*) ((uint32_t)dma_current_txdesc + ETH_DMATXDESC_SIZE + GET_DMA_BCTL_DPSL(ENET_DMA_BCTL)); } @@ -2622,7 +2664,7 @@ void enet_desc_select_normal_mode(void) /*! \brief initialize the DMA Tx/Rx descriptors's parameters in normal chain mode with PTP function - \param[in] direction: the descriptors which users want to init, refer to enet_dmadirection_enum, + \param[in] direction: the descriptors which users want to init, refer to enet_dmadirection_enum only one parameter can be selected which is shown as below \arg ENET_DMA_TX: DMA Tx descriptors \arg ENET_DMA_RX: DMA Rx descriptors @@ -2636,18 +2678,18 @@ void enet_ptp_normal_descriptors_chain_init(enet_dmadirection_enum direction, en uint32_t desc_status = 0U, desc_bufsize = 0U; enet_descriptors_struct *desc, *desc_tab; uint8_t *buf; - + /* if want to initialize DMA Tx descriptors */ if (ENET_DMA_TX == direction){ /* save a copy of the DMA Tx descriptors */ desc_tab = txdesc_tab; buf = &tx_buff[0][0]; count = ENET_TXBUF_NUM; - maxsize = ENET_TXBUF_SIZE; - + maxsize = ENET_TXBUF_SIZE; + /* select chain mode, and enable transmit timestamp function */ desc_status = ENET_TDES0_TCHM | ENET_TDES0_TTSEN; - + /* configure DMA Tx descriptor table address register */ ENET_DMA_TDTADDR = (uint32_t)desc_tab; dma_current_txdesc = desc_tab; @@ -2658,50 +2700,50 @@ void enet_ptp_normal_descriptors_chain_init(enet_dmadirection_enum direction, en desc_tab = rxdesc_tab; buf = &rx_buff[0][0]; count = ENET_RXBUF_NUM; - maxsize = ENET_RXBUF_SIZE; - + maxsize = ENET_RXBUF_SIZE; + /* enable receiving */ desc_status = ENET_RDES0_DAV; /* select receive chained mode and set buffer1 size */ desc_bufsize = ENET_RDES1_RCHM | (uint32_t)ENET_RXBUF_SIZE; - + /* configure DMA Rx descriptor table address register */ ENET_DMA_RDTADDR = (uint32_t)desc_tab; dma_current_rxdesc = desc_tab; - dma_current_ptp_rxdesc = desc_ptptab; + dma_current_ptp_rxdesc = desc_ptptab; } - - /* configure each descriptor */ + + /* configure each descriptor */ for(num = 0U; num < count; num++){ /* get the pointer to the next descriptor of the descriptor table */ desc = desc_tab + num; /* configure descriptors */ - desc->status = desc_status; + desc->status = desc_status; desc->control_buffer_size = desc_bufsize; desc->buffer1_addr = (uint32_t)(&buf[num * maxsize]); - + /* if is not the last descriptor */ if(num < (count - 1U)){ /* configure the next descriptor address */ desc->buffer2_next_desc_addr = (uint32_t)(desc_tab + num + 1U); }else{ - /* when it is the last descriptor, the next descriptor address - equals to first descriptor address in descriptor table */ - desc->buffer2_next_desc_addr = (uint32_t)desc_tab; + /* when it is the last descriptor, the next descriptor address + equals to first descriptor address in descriptor table */ + desc->buffer2_next_desc_addr = (uint32_t)desc_tab; } /* set desc_ptptab equal to desc_tab */ (&desc_ptptab[num])->buffer1_addr = desc->buffer1_addr; (&desc_ptptab[num])->buffer2_next_desc_addr = desc->buffer2_next_desc_addr; - } - /* when it is the last ptp descriptor, preserve the first descriptor + } + /* when it is the last ptp descriptor, preserve the first descriptor address of desc_ptptab in ptp descriptor status */ (&desc_ptptab[num-1U])->status = (uint32_t)desc_ptptab; } /*! \brief initialize the DMA Tx/Rx descriptors's parameters in normal ring mode with PTP function - \param[in] direction: the descriptors which users want to init, refer to enet_dmadirection_enum, + \param[in] direction: the descriptors which users want to init, refer to enet_dmadirection_enum only one parameter can be selected which is shown as below \arg ENET_DMA_TX: DMA Tx descriptors \arg ENET_DMA_RX: DMA Rx descriptors @@ -2719,18 +2761,18 @@ void enet_ptp_normal_descriptors_ring_init(enet_dmadirection_enum direction, ene /* configure descriptor skip length */ ENET_DMA_BCTL &= ~ENET_DMA_BCTL_DPSL; ENET_DMA_BCTL |= DMA_BCTL_DPSL(0); - + /* if want to initialize DMA Tx descriptors */ if (ENET_DMA_TX == direction){ /* save a copy of the DMA Tx descriptors */ desc_tab = txdesc_tab; buf = &tx_buff[0][0]; count = ENET_TXBUF_NUM; - maxsize = ENET_TXBUF_SIZE; - + maxsize = ENET_TXBUF_SIZE; + /* select ring mode, and enable transmit timestamp function */ desc_status = ENET_TDES0_TTSEN; - + /* configure DMA Tx descriptor table address register */ ENET_DMA_TDTADDR = (uint32_t)desc_tab; dma_current_txdesc = desc_tab; @@ -2741,33 +2783,33 @@ void enet_ptp_normal_descriptors_ring_init(enet_dmadirection_enum direction, ene desc_tab = rxdesc_tab; buf = &rx_buff[0][0]; count = ENET_RXBUF_NUM; - maxsize = ENET_RXBUF_SIZE; - + maxsize = ENET_RXBUF_SIZE; + /* enable receiving */ desc_status = ENET_RDES0_DAV; /* select receive ring mode and set buffer1 size */ desc_bufsize = (uint32_t)ENET_RXBUF_SIZE; - + /* configure DMA Rx descriptor table address register */ ENET_DMA_RDTADDR = (uint32_t)desc_tab; dma_current_rxdesc = desc_tab; - dma_current_ptp_rxdesc = desc_ptptab; + dma_current_ptp_rxdesc = desc_ptptab; } - - /* configure each descriptor */ + + /* configure each descriptor */ for(num = 0U; num < count; num++){ /* get the pointer to the next descriptor of the descriptor table */ desc = desc_tab + num; /* configure descriptors */ - desc->status = desc_status; + desc->status = desc_status; desc->control_buffer_size = desc_bufsize; desc->buffer1_addr = (uint32_t)(&buf[num * maxsize]); - + /* when it is the last descriptor */ if(num == (count - 1U)){ if (ENET_DMA_TX == direction){ - /* configure transmit end of ring mode */ + /* configure transmit end of ring mode */ desc->status |= ENET_TDES0_TERM; }else{ /* configure receive end of ring mode */ @@ -2777,43 +2819,43 @@ void enet_ptp_normal_descriptors_ring_init(enet_dmadirection_enum direction, ene /* set desc_ptptab equal to desc_tab */ (&desc_ptptab[num])->buffer1_addr = desc->buffer1_addr; (&desc_ptptab[num])->buffer2_next_desc_addr = desc->buffer2_next_desc_addr; - } - /* when it is the last ptp descriptor, preserve the first descriptor + } + /* when it is the last ptp descriptor, preserve the first descriptor address of desc_ptptab in ptp descriptor status */ (&desc_ptptab[num-1U])->status = (uint32_t)desc_ptptab; } /*! - \brief receive a packet data with timestamp values to application buffer, when the DMA is in normal mode + \brief receive a packet data with timestamp values to application buffer, when the DMA is in normal mode \param[in] bufsize: the size of buffer which is the parameter in function - \param[out] timestamp: pointer to the table which stores the timestamp high and low \param[out] buffer: pointer to the application buffer note -- if the input is NULL, user should copy data in application by himself + \param[out] timestamp: pointer to the table which stores the timestamp high and low \retval ErrStatus: SUCCESS or ERROR */ ErrStatus enet_ptpframe_receive_normal_mode(uint8_t *buffer, uint32_t bufsize, uint32_t timestamp[]) { uint32_t offset = 0U, size = 0U; - + /* the descriptor is busy due to own by the DMA */ if((uint32_t)RESET != (dma_current_rxdesc->status & ENET_RDES0_DAV)){ return ERROR; } - + /* if buffer pointer is null, indicates that users has copied data in application */ if(NULL != buffer){ /* if no error occurs, and the frame uses only one descriptor */ if(((uint32_t)RESET == (dma_current_rxdesc->status & ENET_RDES0_ERRS)) && ((uint32_t)RESET != (dma_current_rxdesc->status & ENET_RDES0_LDES)) && ((uint32_t)RESET != (dma_current_rxdesc->status & ENET_RDES0_FDES))){ - + /* get the frame length except CRC */ size = GET_RDES0_FRML(dma_current_rxdesc->status) - 4U; /* if is a type frame, and CRC is not included in forwarding frame */ if((RESET != (ENET_MAC_CFG & ENET_MAC_CFG_TFCD)) && (RESET != (dma_current_rxdesc->status & ENET_RDES0_FRMT))){ size = size + 4U; } - + /* to avoid situation that the frame size exceeds the buffer length */ if(size > bufsize){ return ERROR; @@ -2823,7 +2865,7 @@ ErrStatus enet_ptpframe_receive_normal_mode(uint8_t *buffer, uint32_t bufsize, u for(offset = 0U; offset < size; offset++){ (*(buffer + offset)) = (*(__IO uint8_t *)(uint32_t)((dma_current_ptp_rxdesc->buffer1_addr) + offset)); } - + }else{ return ERROR; } @@ -2834,10 +2876,10 @@ ErrStatus enet_ptpframe_receive_normal_mode(uint8_t *buffer, uint32_t bufsize, u dma_current_rxdesc->buffer1_addr = dma_current_ptp_rxdesc ->buffer1_addr ; dma_current_rxdesc->buffer2_next_desc_addr = dma_current_ptp_rxdesc ->buffer2_next_desc_addr; - + /* enable reception, descriptor is owned by DMA */ dma_current_rxdesc->status = ENET_RDES0_DAV; - + /* check Rx buffer unavailable flag status */ if ((uint32_t)RESET != (ENET_DMA_STAT & ENET_DMA_STAT_RBU)){ /* clear RBU flag */ @@ -2845,9 +2887,9 @@ ErrStatus enet_ptpframe_receive_normal_mode(uint8_t *buffer, uint32_t bufsize, u /* resume DMA reception by writing to the RPEN register*/ ENET_DMA_RPEN = 0U; } - - /* update the current RxDMA descriptor pointer to the next decriptor in RxDMA decriptor table */ + + /* update the current RxDMA descriptor pointer to the next decriptor in RxDMA decriptor table */ /* chained mode */ if((uint32_t)RESET != (dma_current_rxdesc->control_buffer_size & ENET_RDES1_RCHM)){ dma_current_rxdesc = (enet_descriptors_struct*) (dma_current_ptp_rxdesc->buffer2_next_desc_addr); @@ -2860,16 +2902,16 @@ ErrStatus enet_ptpframe_receive_normal_mode(uint8_t *buffer, uint32_t bufsize, u dma_current_ptp_rxdesc++; } }else{ - /* ring mode */ + /* ring mode */ if((uint32_t)RESET != (dma_current_rxdesc->control_buffer_size & ENET_RDES1_RERM)){ /* if is the last descriptor in table, the next descriptor is the table header */ dma_current_rxdesc = (enet_descriptors_struct*) (ENET_DMA_RDTADDR); /* RDES2 and RDES3 will not be covered by buffer address, so do not need to preserve a new table, use the same table with RxDMA descriptor */ - dma_current_ptp_rxdesc = (enet_descriptors_struct*) (dma_current_ptp_rxdesc->status); + dma_current_ptp_rxdesc = (enet_descriptors_struct*) (dma_current_ptp_rxdesc->status); }else{ /* the next descriptor is the current address, add the descriptor size, and descriptor skip length */ - dma_current_rxdesc = (enet_descriptors_struct*) (uint32_t)((uint32_t)dma_current_rxdesc + ETH_DMARXDESC_SIZE + GET_DMA_BCTL_DPSL(ENET_DMA_BCTL)); + dma_current_rxdesc = (enet_descriptors_struct*) (uint32_t)((uint32_t)dma_current_rxdesc + ETH_DMARXDESC_SIZE + GET_DMA_BCTL_DPSL(ENET_DMA_BCTL)); dma_current_ptp_rxdesc ++; } } @@ -2878,7 +2920,7 @@ ErrStatus enet_ptpframe_receive_normal_mode(uint8_t *buffer, uint32_t bufsize, u } /*! - \brief send data with timestamp values in application buffer as a transmit packet, when the DMA is in normal mode + \brief send data with timestamp values in application buffer as a transmit packet, when the DMA is in normal mode \param[in] buffer: pointer on the application buffer note -- if the input is NULL, user should copy data in application by himself \param[in] length: the length of frame data to be transmitted @@ -2889,8 +2931,8 @@ ErrStatus enet_ptpframe_receive_normal_mode(uint8_t *buffer, uint32_t bufsize, u ErrStatus enet_ptpframe_transmit_normal_mode(uint8_t *buffer, uint32_t length, uint32_t timestamp[]) { uint32_t offset = 0U, timeout = 0U; - uint32_t dma_tbu_flag, dma_tu_flag, tdes0_ttmss_flag; - + uint32_t dma_tbu_flag, dma_tu_flag, tdes0_ttmss_flag; + /* the descriptor is busy due to own by the DMA */ if((uint32_t)RESET != (dma_current_txdesc->status & ENET_TDES0_DAV)){ return ERROR; @@ -2900,7 +2942,7 @@ ErrStatus enet_ptpframe_transmit_normal_mode(uint8_t *buffer, uint32_t length, u if(length > ENET_MAX_FRAME_SIZE){ return ERROR; } - + /* if buffer pointer is null, indicates that users has handled data in application */ if(NULL != buffer){ /* copy frame data from application buffer to Tx buffer */ @@ -2914,31 +2956,31 @@ ErrStatus enet_ptpframe_transmit_normal_mode(uint8_t *buffer, uint32_t length, u dma_current_txdesc->status |= ENET_TDES0_LSG | ENET_TDES0_FSG; /* enable the DMA transmission */ dma_current_txdesc->status |= ENET_TDES0_DAV; - + /* check Tx buffer unavailable flag status */ - dma_tbu_flag = (ENET_DMA_STAT & ENET_DMA_STAT_TBU); + dma_tbu_flag = (ENET_DMA_STAT & ENET_DMA_STAT_TBU); dma_tu_flag = (ENET_DMA_STAT & ENET_DMA_STAT_TU); - + if((RESET != dma_tbu_flag) || (RESET != dma_tu_flag)){ /* clear TBU and TU flag */ ENET_DMA_STAT = (dma_tbu_flag | dma_tu_flag); /* resume DMA transmission by writing to the TPEN register*/ ENET_DMA_TPEN = 0U; } - + /* if timestamp pointer is null, indicates that users don't care timestamp in application */ if(NULL != timestamp){ /* wait for ENET_TDES0_TTMSS flag to be set, a timestamp was captured */ - do{ + do{ tdes0_ttmss_flag = (dma_current_txdesc->status & ENET_TDES0_TTMSS); timeout++; }while((RESET == tdes0_ttmss_flag) && (timeout < ENET_DELAY_TO)); - + /* return ERROR due to timeout */ if(ENET_DELAY_TO == timeout){ return ERROR; - } - + } + /* clear the ENET_TDES0_TTMSS flag */ dma_current_txdesc->status &= ~ENET_TDES0_TTMSS; /* get the timestamp value of the transmit frame */ @@ -2948,12 +2990,12 @@ ErrStatus enet_ptpframe_transmit_normal_mode(uint8_t *buffer, uint32_t length, u dma_current_txdesc->buffer1_addr = dma_current_ptp_txdesc ->buffer1_addr ; dma_current_txdesc->buffer2_next_desc_addr = dma_current_ptp_txdesc ->buffer2_next_desc_addr; - /* update the current TxDMA descriptor pointer to the next decriptor in TxDMA decriptor table */ + /* update the current TxDMA descriptor pointer to the next decriptor in TxDMA decriptor table */ /* chained mode */ - if((uint32_t)RESET != (dma_current_txdesc->status & ENET_TDES0_TCHM)){ + if((uint32_t)RESET != (dma_current_txdesc->status & ENET_TDES0_TCHM)){ dma_current_txdesc = (enet_descriptors_struct*) (dma_current_ptp_txdesc->buffer2_next_desc_addr); /* if it is the last ptp descriptor */ - if(0U != dma_current_ptp_txdesc->status){ + if(0U != dma_current_ptp_txdesc->status){ /* pointer back to the first ptp descriptor address in the desc_ptptab list address */ dma_current_ptp_txdesc = (enet_descriptors_struct*) (dma_current_ptp_txdesc->status); }else{ @@ -2961,17 +3003,17 @@ ErrStatus enet_ptpframe_transmit_normal_mode(uint8_t *buffer, uint32_t length, u dma_current_ptp_txdesc++; } }else{ - /* ring mode */ + /* ring mode */ if((uint32_t)RESET != (dma_current_txdesc->status & ENET_TDES0_TERM)){ /* if is the last descriptor in table, the next descriptor is the table header */ - dma_current_txdesc = (enet_descriptors_struct*) (ENET_DMA_TDTADDR); + dma_current_txdesc = (enet_descriptors_struct*) (ENET_DMA_TDTADDR); /* TDES2 and TDES3 will not be covered by buffer address, so do not need to preserve a new table, use the same table with TxDMA descriptor */ dma_current_ptp_txdesc = (enet_descriptors_struct*) (dma_current_ptp_txdesc->status); }else{ /* the next descriptor is the current address, add the descriptor size, and descriptor skip length */ - dma_current_txdesc = (enet_descriptors_struct*) (uint32_t)((uint32_t)dma_current_txdesc + ETH_DMATXDESC_SIZE + GET_DMA_BCTL_DPSL(ENET_DMA_BCTL)); - dma_current_ptp_txdesc ++; + dma_current_txdesc = (enet_descriptors_struct*) (uint32_t)((uint32_t)dma_current_txdesc + ETH_DMATXDESC_SIZE + GET_DMA_BCTL_DPSL(ENET_DMA_BCTL)); + dma_current_ptp_txdesc ++; } } return SUCCESS; @@ -2980,7 +3022,7 @@ ErrStatus enet_ptpframe_transmit_normal_mode(uint8_t *buffer, uint32_t length, u #endif /* SELECT_DESCRIPTORS_ENHANCED_MODE */ /*! - \brief wakeup frame filter register pointer reset + \brief wakeup frame filter register pointer reset \param[in] none \param[out] none \retval none @@ -2991,7 +3033,7 @@ void enet_wum_filter_register_pointer_reset(void) } /*! - \brief set the remote wakeup frame registers + \brief set the remote wakeup frame registers \param[in] pdata: pointer to buffer data which is written to remote wakeup frame registers (8 words total) \param[out] none \retval none @@ -2999,7 +3041,7 @@ void enet_wum_filter_register_pointer_reset(void) void enet_wum_filter_config(uint32_t pdata[]) { uint32_t num = 0U; - + /* configure ENET_MAC_RWFF register */ for(num = 0U; num < ETH_WAKEUP_REGISTER_LENGTH; num++){ ENET_MAC_RWFF = pdata[num]; @@ -3007,8 +3049,9 @@ void enet_wum_filter_config(uint32_t pdata[]) } /*! - \brief enable wakeup management features - \param[in] feature: one or more parameters can be selected which are shown as below + \brief enable wakeup management features + \param[in] feature: the wake up type which is selected + one or more parameters can be selected which are shown as below \arg ENET_WUM_POWER_DOWN: power down mode \arg ENET_WUM_MAGIC_PACKET_FRAME: enable a wakeup event due to magic packet reception \arg ENET_WUM_WAKE_UP_FRAME: enable a wakeup event due to wakeup frame reception @@ -3022,8 +3065,9 @@ void enet_wum_feature_enable(uint32_t feature) } /*! - \brief disable wakeup management features - \param[in] feature: one or more parameters can be selected which are shown as below + \brief disable wakeup management features + \param[in] feature: the wake up type which is selected + one or more parameters can be selected which are shown as below \arg ENET_WUM_MAGIC_PACKET_FRAME: enable a wakeup event due to magic packet reception \arg ENET_WUM_WAKE_UP_FRAME: enable a wakeup event due to wakeup frame reception \arg ENET_WUM_GLOBAL_UNICAST: any received unicast frame passed filter is considered to be a wakeup frame @@ -3036,8 +3080,8 @@ void enet_wum_feature_disable(uint32_t feature) } /*! - \brief reset the MAC statistics counters - \param[in] none + \brief reset the MAC statistics counters + \param[in] none \param[out] none \retval none */ @@ -3049,7 +3093,8 @@ void enet_msc_counters_reset(void) /*! \brief enable the MAC statistics counter features - \param[in] feature: one or more parameters can be selected which are shown as below + \param[in] feature: the feature of MAC statistics counter + one or more parameters can be selected which are shown as below \arg ENET_MSC_COUNTER_STOP_ROLLOVER: counter stop rollover \arg ENET_MSC_RESET_ON_READ: reset on read \arg ENET_MSC_COUNTERS_FREEZE: MSC counter freeze @@ -3063,7 +3108,8 @@ void enet_msc_feature_enable(uint32_t feature) /*! \brief disable the MAC statistics counter features - \param[in] feature: one or more parameters can be selected which are shown as below + \param[in] feature: the feature of MAC statistics counter + one or more parameters can be selected which are shown as below \arg ENET_MSC_COUNTER_STOP_ROLLOVER: counter stop rollover \arg ENET_MSC_RESET_ON_READ: reset on read \arg ENET_MSC_COUNTERS_FREEZE: MSC counter freeze @@ -3076,8 +3122,8 @@ void enet_msc_feature_disable(uint32_t feature) } /*! - \brief configure MAC statistics counters preset mode - \param[in] mode: MSC counters preset mode, refer to enet_msc_preset_enum, + \brief configure MAC statistics counters preset mode + \param[in] mode: MSC counters preset mode, refer to enet_msc_preset_enum only one parameter can be selected which is shown as below \arg ENET_MSC_PRESET_NONE: do not preset MSC counter \arg ENET_MSC_PRESET_HALF: preset all MSC counters to almost-half(0x7FFF FFF0) value @@ -3092,8 +3138,8 @@ void enet_msc_counters_preset_config(enet_msc_preset_enum mode) } /*! - \brief get MAC statistics counter - \param[in] counter: MSC counters which is selected, refer to enet_msc_counter_enum, + \brief get MAC statistics counter + \param[in] counter: MSC counters which is selected, refer to enet_msc_counter_enum only one parameter can be selected which is shown as below \arg ENET_MSC_TX_SCCNT: MSC transmitted good frames after a single collision counter \arg ENET_MSC_TX_MSCCNT: MSC transmitted good frames after more than a single collision counter @@ -3107,9 +3153,9 @@ void enet_msc_counters_preset_config(enet_msc_preset_enum mode) uint32_t enet_msc_counters_get(enet_msc_counter_enum counter) { uint32_t reval; - + reval = REG32((ENET + (uint32_t)counter)); - + return reval; } @@ -3153,7 +3199,8 @@ void enet_ptp_feature_disable(uint32_t feature) /*! \brief configure the PTP timestamp function - \param[in] func: only one parameter can be selected which is shown as below + \param[in] func: the function of PTP timestamp + only one parameter can be selected which is shown as below \arg ENET_CKNT_ORDINARY: type of ordinary clock node type for timestamp \arg ENET_CKNT_BOUNDARY: type of boundary clock node type for timestamp \arg ENET_CKNT_END_TO_END: type of end-to-end transparent clock node type for timestamp @@ -3168,7 +3215,7 @@ void enet_ptp_feature_disable(uint32_t feature) \arg ENET_SNOOPING_PTP_VERSION_2: version 2 \arg ENET_SNOOPING_PTP_VERSION_1: version 1 \arg ENET_EVENT_TYPE_MESSAGES_SNAPSHOT: only event type messages are taken snapshot - \arg ENET_ALL_TYPE_MESSAGES_SNAPSHOT: all type messages are taken snapshot except announce, + \arg ENET_ALL_TYPE_MESSAGES_SNAPSHOT: all type messages are taken snapshot except announce, management and signaling message \arg ENET_MASTER_NODE_MESSAGE_SNAPSHOT: snapshot is only take for master node message \arg ENET_SLAVE_NODE_MESSAGE_SNAPSHOT: snapshot is only taken for slave node message @@ -3189,10 +3236,10 @@ ErrStatus enet_ptp_timestamp_function_config(enet_ptp_function_enum func) ENET_PTP_TSCTL &= ~ENET_PTP_TSCTL_CKNT; ENET_PTP_TSCTL |= (uint32_t)func; break; - case ENET_PTP_ADDEND_UPDATE: + case ENET_PTP_ADDEND_UPDATE: /* this bit must be read as zero before application set it */ do{ - temp_state = ENET_PTP_TSCTL & ENET_PTP_TSCTL_TMSARU; + temp_state = ENET_PTP_TSCTL & ENET_PTP_TSCTL_TMSARU; timeout++; }while((RESET != temp_state) && (timeout < ENET_DELAY_TO)); /* return ERROR due to timeout */ @@ -3200,12 +3247,12 @@ ErrStatus enet_ptp_timestamp_function_config(enet_ptp_function_enum func) enet_state = ERROR; }else{ ENET_PTP_TSCTL |= ENET_PTP_TSCTL_TMSARU; - } + } break; case ENET_PTP_SYSTIME_UPDATE: /* both the TMSSTU and TMSSTI bits must be read as zero before application set this bit */ do{ - temp_state = ENET_PTP_TSCTL & (ENET_PTP_TSCTL_TMSSTU | ENET_PTP_TSCTL_TMSSTI); + temp_state = ENET_PTP_TSCTL & (ENET_PTP_TSCTL_TMSSTU | ENET_PTP_TSCTL_TMSSTI); timeout++; }while((RESET != temp_state) && (timeout < ENET_DELAY_TO)); /* return ERROR due to timeout */ @@ -3213,12 +3260,12 @@ ErrStatus enet_ptp_timestamp_function_config(enet_ptp_function_enum func) enet_state = ERROR; }else{ ENET_PTP_TSCTL |= ENET_PTP_TSCTL_TMSSTU; - } - break; + } + break; case ENET_PTP_SYSTIME_INIT: /* this bit must be read as zero before application set it */ do{ - temp_state = ENET_PTP_TSCTL & ENET_PTP_TSCTL_TMSSTI; + temp_state = ENET_PTP_TSCTL & ENET_PTP_TSCTL_TMSSTI; timeout++; }while((RESET != temp_state) && (timeout < ENET_DELAY_TO)); /* return ERROR due to timeout */ @@ -3226,16 +3273,16 @@ ErrStatus enet_ptp_timestamp_function_config(enet_ptp_function_enum func) enet_state = ERROR; }else{ ENET_PTP_TSCTL |= ENET_PTP_TSCTL_TMSSTI; - } - break; + } + break; default: - temp_config = (uint32_t)func & (~BIT(31)); + temp_config = (uint32_t)func & (~BIT(31)); if(RESET != ((uint32_t)func & BIT(31))){ - ENET_PTP_TSCTL |= temp_config; + ENET_PTP_TSCTL |= temp_config; }else{ - ENET_PTP_TSCTL &= ~temp_config; + ENET_PTP_TSCTL &= ~temp_config; } - break; + break; } return enet_state; @@ -3243,8 +3290,7 @@ ErrStatus enet_ptp_timestamp_function_config(enet_ptp_function_enum func) /*! \brief configure system time subsecond increment value - \param[in] subsecond: the value will be added to the subsecond value of system time, - this value must be between 0 and 0xFF + \param[in] subsecond: the value will be added to the subsecond value of system time(0x00000000 - 0x000000FF) \param[out] none \retval none */ @@ -3266,12 +3312,12 @@ void enet_ptp_timestamp_addend_config(uint32_t add) /*! \brief initialize or add/subtract to second of the system time - \param[in] sign: timestamp update positive or negative sign, + \param[in] sign: timestamp update positive or negative sign only one parameter can be selected which is shown as below \arg ENET_PTP_ADD_TO_TIME: timestamp update value is added to system time \arg ENET_PTP_SUBSTRACT_FROM_TIME: timestamp update value is subtracted from system time \param[in] second: initializing or adding/subtracting to second of the system time - \param[in] subsecond: the current subsecond of the system time + \param[in] subsecond: the current subsecond of the system time with 0.46 ns accuracy if required accuracy is 20 ns \param[out] none \retval none @@ -3279,7 +3325,7 @@ void enet_ptp_timestamp_addend_config(uint32_t add) void enet_ptp_timestamp_update_config(uint32_t sign, uint32_t second, uint32_t subsecond) { ENET_PTP_TSUH = second; - ENET_PTP_TSUL = sign | PTP_TSUL_TMSUSS(subsecond); + ENET_PTP_TSUL = sign | PTP_TSUL_TMSUSS(subsecond); } /*! @@ -3298,7 +3344,7 @@ void enet_ptp_expected_time_config(uint32_t second, uint32_t nanosecond) /*! \brief get the current system time \param[in] none - \param[out] systime_struct: pointer to a enet_ptp_systime_struct structure which contains + \param[out] systime_struct: pointer to a enet_ptp_systime_struct structure which contains parameters of PTP system time members of the structure and the member values are shown as below: second: 0x0 - 0xFFFF FFFF @@ -3311,9 +3357,9 @@ void enet_ptp_system_time_get(enet_ptp_systime_struct *systime_struct) uint32_t temp_sec = 0U, temp_subs = 0U; /* get the value of sysytem time registers */ - temp_sec = (uint32_t)ENET_PTP_TSH; + temp_sec = (uint32_t)ENET_PTP_TSH; temp_subs = (uint32_t)ENET_PTP_TSL; - + /* get sysytem time and construct the enet_ptp_systime_struct structure */ systime_struct->second = temp_sec; systime_struct->subsecond = GET_PTP_TSL_STMSS(temp_subs); @@ -3322,18 +3368,18 @@ void enet_ptp_system_time_get(enet_ptp_systime_struct *systime_struct) /*! \brief configure the PPS output frequency - \param[in] freq: PPS output frequency, + \param[in] freq: PPS output frequency only one parameter can be selected which is shown as below \arg ENET_PPSOFC_1HZ: PPS output 1Hz frequency - \arg ENET_PPSOFC_2HZ: PPS output 2Hz frequency - \arg ENET_PPSOFC_4HZ: PPS output 4Hz frequency - \arg ENET_PPSOFC_8HZ: PPS output 8Hz frequency - \arg ENET_PPSOFC_16HZ: PPS output 16Hz frequency - \arg ENET_PPSOFC_32HZ: PPS output 32Hz frequency + \arg ENET_PPSOFC_2HZ: PPS output 2Hz frequency + \arg ENET_PPSOFC_4HZ: PPS output 4Hz frequency + \arg ENET_PPSOFC_8HZ: PPS output 8Hz frequency + \arg ENET_PPSOFC_16HZ: PPS output 16Hz frequency + \arg ENET_PPSOFC_32HZ: PPS output 32Hz frequency \arg ENET_PPSOFC_64HZ: PPS output 64Hz frequency \arg ENET_PPSOFC_128HZ: PPS output 128Hz frequency \arg ENET_PPSOFC_256HZ: PPS output 256Hz frequency - \arg ENET_PPSOFC_512HZ: PPS output 512Hz frequency + \arg ENET_PPSOFC_512HZ: PPS output 512Hz frequency \arg ENET_PPSOFC_1024HZ: PPS output 1024Hz frequency \arg ENET_PPSOFC_2048HZ: PPS output 2048Hz frequency \arg ENET_PPSOFC_4096HZ: PPS output 4096Hz frequency @@ -3362,7 +3408,7 @@ void enet_initpara_reset(void) enet_initpara.dma_maxburst = 0U; enet_initpara.dma_arbitration = 0U; enet_initpara.store_forward_mode = 0U; - enet_initpara.dma_function = 0U; + enet_initpara.dma_function = 0U; enet_initpara.vlan_config = 0U; enet_initpara.flow_control = 0U; enet_initpara.hashtable_high = 0U; @@ -3371,10 +3417,10 @@ void enet_initpara_reset(void) enet_initpara.halfduplex_param = 0U; enet_initpara.timer_config = 0U; enet_initpara.interframegap = 0U; -} +} /*! - \brief initialize ENET peripheral with generally concerned parameters, call it by enet_init() + \brief initialize ENET peripheral with generally concerned parameters, call it by enet_init() \param[in] none \param[out] none \retval none @@ -3396,7 +3442,7 @@ static void enet_default_init(void) | ENET_AUTO_PADCRC_DROP_DISABLE \ | ENET_CHECKSUMOFFLOAD_DISABLE; ENET_MAC_CFG = reg_value; - + /* configure ENET_MAC_FRMF register */ ENET_MAC_FRMF = ENET_SRC_FILTER_DISABLE |ENET_DEST_FILTER_INVERSE_DISABLE \ |ENET_MULTICAST_FILTER_PERFECT |ENET_UNICAST_FILTER_PERFECT \ @@ -3405,7 +3451,7 @@ static void enet_default_init(void) /* configure ENET_MAC_HLH, ENET_MAC_HLL register */ ENET_MAC_HLH = 0x0U; - + ENET_MAC_HLL = 0x0U; /* configure ENET_MAC_FCTL, ENET_MAC_FCTH register */ @@ -3414,13 +3460,13 @@ static void enet_default_init(void) reg_value |= MAC_FCTL_PTM(0) |ENET_ZERO_QUANTA_PAUSE_DISABLE \ |ENET_PAUSETIME_MINUS4 |ENET_UNIQUE_PAUSEDETECT \ |ENET_RX_FLOWCONTROL_DISABLE |ENET_TX_FLOWCONTROL_DISABLE; - ENET_MAC_FCTL = reg_value; - + ENET_MAC_FCTL = reg_value; + ENET_MAC_FCTH = ENET_DEACTIVE_THRESHOLD_512BYTES |ENET_ACTIVE_THRESHOLD_1536BYTES; - + /* configure ENET_MAC_VLT register */ ENET_MAC_VLT = ENET_VLANTAGCOMPARISON_16BIT |MAC_VLT_VLTI(0); - + /* DMA */ /* configure ENET_DMA_CTL register */ reg_value = ENET_DMA_CTL; @@ -3429,8 +3475,8 @@ static void enet_default_init(void) |ENET_FLUSH_RXFRAME_ENABLE |ENET_TX_MODE_STOREFORWARD \ |ENET_TX_THRESHOLD_64BYTES |ENET_RX_THRESHOLD_64BYTES \ |ENET_FORWARD_ERRFRAMES_DISABLE |ENET_FORWARD_UNDERSZ_GOODFRAMES_DISABLE \ - |ENET_SECONDFRAME_OPT_DISABLE; - ENET_DMA_CTL = reg_value; + |ENET_SECONDFRAME_OPT_DISABLE; + ENET_DMA_CTL = reg_value; /* configure ENET_DMA_BCTL register */ reg_value = ENET_DMA_BCTL; @@ -3439,7 +3485,7 @@ static void enet_default_init(void) |ENET_RXDP_32BEAT |ENET_PGBL_32BEAT |ENET_RXTX_DIFFERENT_PGBL \ |ENET_FIXED_BURST_ENABLE |ENET_MIXED_BURST_DISABLE \ |ENET_NORMAL_DESCRIPTOR; - ENET_DMA_BCTL = reg_value; + ENET_DMA_BCTL = reg_value; } #ifndef USE_DELAY @@ -3451,8 +3497,8 @@ static void enet_default_init(void) */ static void enet_delay(uint32_t ncount) { - uint32_t delay_time = 0U; - + __IO uint32_t delay_time = 0U; + for(delay_time = ncount; delay_time != 0U; delay_time--){ } } diff --git a/bsp/gd32450z-eval/Libraries/GD32F4xx_standard_peripheral/Source/gd32f4xx_exmc.c b/bsp/gd32450z-eval/Libraries/GD32F4xx_standard_peripheral/Source/gd32f4xx_exmc.c index a3049a7448..e225258eb5 100644 --- a/bsp/gd32450z-eval/Libraries/GD32F4xx_standard_peripheral/Source/gd32f4xx_exmc.c +++ b/bsp/gd32450z-eval/Libraries/GD32F4xx_standard_peripheral/Source/gd32f4xx_exmc.c @@ -1,33 +1,58 @@ /*! - \file gd32f4xx_exmc.c - \brief EXMC driver + \file gd32f4xx_exmc.c + \brief EXMC driver + + \version 2016-08-15, V1.0.0, firmware for GD32F4xx + \version 2018-12-12, V2.0.0, firmware for GD32F4xx + \version 2020-09-30, V2.1.0, firmware for GD32F4xx */ /* - Copyright (C) 2016 GigaDevice + Copyright (c) 2020, GigaDevice Semiconductor Inc. + + Redistribution and use in source and binary forms, with or without modification, +are permitted provided that the following conditions are met: + + 1. Redistributions of source code must retain the above copyright notice, this + list of conditions and the following disclaimer. + 2. Redistributions in binary form must reproduce the above copyright notice, + this list of conditions and the following disclaimer in the documentation + and/or other materials provided with the distribution. + 3. Neither the name of the copyright holder nor the names of its contributors + may be used to endorse or promote products derived from this software without + specific prior written permission. - 2016-08-15, V1.0.0, firmware for GD32F4xx + THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED +WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. +IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, +INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT +NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR +PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, +WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY +OF SUCH DAMAGE. */ #include "gd32f4xx_exmc.h" /* EXMC bank0 register reset value */ -#define BANK0_SNCTL_REGION_RESET ((uint32_t)0x000030DAU) +#define BANK0_SNCTL_RESET ((uint32_t)0x000030DAU) #define BANK0_SNTCFG_RESET ((uint32_t)0x0FFFFFFFU) #define BANK0_SNWTCFG_RESET ((uint32_t)0x0FFFFFFFU) -/* EXMC bank1/2 register reset mask*/ -#define BANK1_2_NPCTL_RESET ((uint32_t)0x00000018U) -#define BANK1_2_NPINTEN_RESET ((uint32_t)0x00000040U) -#define BANK1_2_NPCTCFG_RESET ((uint32_t)0xFCFCFCFCU) -#define BANK1_2_NPATCFG_RESET ((uint32_t)0xFCFCFCFCU) +/* EXMC bank1/2 register reset mask */ +#define BANK1_2_NPCTL_RESET ((uint32_t)0x00000008U) +#define BANK1_2_NPINTEN_RESET ((uint32_t)0x00000042U) +#define BANK1_2_NPCTCFG_RESET ((uint32_t)0xFFFFFFFFU) +#define BANK1_2_NPATCFG_RESET ((uint32_t)0xFFFFFFFFU) -/* EXMC bank3 register reset mask*/ -#define BANK3_NPCTL_RESET ((uint32_t)0x00000018U) -#define BANK3_NPINTEN_RESET ((uint32_t)0x00000000U) -#define BANK3_NPCTCFG_RESET ((uint32_t)0xFCFCFCFCU) -#define BANK3_NPATCFG_RESET ((uint32_t)0xFCFCFCFCU) -#define BANK3_PIOTCFG3_RESET ((uint32_t)0xFCFCFCFCU) +/* EXMC bank3 register reset mask */ +#define BANK3_NPCTL_RESET ((uint32_t)0x00000008U) +#define BANK3_NPINTEN_RESET ((uint32_t)0x00000040U) +#define BANK3_NPCTCFG_RESET ((uint32_t)0xFFFFFFFFU) +#define BANK3_NPATCFG_RESET ((uint32_t)0xFFFFFFFFU) +#define BANK3_PIOTCFG3_RESET ((uint32_t)0xFFFFFFFFU) /* EXMC SDRAM device register reset mask */ #define SDRAM_DEVICE_SDCTL_RESET ((uint32_t)0x000002D0U) @@ -64,13 +89,13 @@ #define NPCTCFG_COMHLD_OFFSET ((uint32_t)16U) #define NPCTCFG_COMHIZ_OFFSET ((uint32_t)24U) -#define NPATCFG_COMWAIT_OFFSET ((uint32_t)8U) -#define NPATCFG_COMHLD_OFFSET ((uint32_t)16U) -#define NPATCFG_COMHIZ_OFFSET ((uint32_t)24U) +#define NPATCFG_ATTWAIT_OFFSET ((uint32_t)8U) +#define NPATCFG_ATTHLD_OFFSET ((uint32_t)16U) +#define NPATCFG_ATTHIZ_OFFSET ((uint32_t)24U) -#define PIOTCFG_COMWAIT_OFFSET ((uint32_t)8U) -#define PIOTCFG_COMHLD_OFFSET ((uint32_t)16U) -#define PIOTCFG_COMHIZ_OFFSET ((uint32_t)24U) +#define PIOTCFG_IOWAIT_OFFSET ((uint32_t)8U) +#define PIOTCFG_IOHLD_OFFSET ((uint32_t)16U) +#define PIOTCFG_IOHIZ_OFFSET ((uint32_t)24U) #define SDCTL_WPEN_OFFSET ((uint32_t)9U) #define SDCTL_BRSTRD_OFFSET ((uint32_t)12U) @@ -96,11 +121,12 @@ #define SRCMD_RWAITCYCLE_OFFSET ((uint32_t)16U) #define SWCMD_WWAITCYCLE_OFFSET ((uint32_t)16U) -#define INTEN_INTEN_OFFSET ((uint32_t)3U) +#define INTEN_INTS_OFFSET ((uint32_t)3U) /*! \brief deinitialize EXMC NOR/SRAM region \param[in] exmc_norsram_region: select the region of bank0 + only one parameter can be selected which is shown as below: \arg EXMC_BANK0_NORSRAM_REGIONx(x=0..3) \param[out] none \retval none @@ -108,29 +134,83 @@ void exmc_norsram_deinit(uint32_t exmc_norsram_region) { /* reset the registers */ - EXMC_SNCTL(exmc_norsram_region) = BANK0_SNCTL_REGION_RESET; + EXMC_SNCTL(exmc_norsram_region) = BANK0_SNCTL_RESET; EXMC_SNTCFG(exmc_norsram_region) = BANK0_SNTCFG_RESET; EXMC_SNWTCFG(exmc_norsram_region) = BANK0_SNWTCFG_RESET; } /*! + \brief initialize exmc_norsram_parameter_struct with the default values + \param[in] none + \param[out] exmc_norsram_init_struct: the initialized struct exmc_norsram_parameter_struct pointer + \retval none +*/ +void exmc_norsram_struct_para_init(exmc_norsram_parameter_struct* exmc_norsram_init_struct) +{ + /* configure the structure with default values */ + exmc_norsram_init_struct->norsram_region = EXMC_BANK0_NORSRAM_REGION0; + exmc_norsram_init_struct->address_data_mux = ENABLE; + exmc_norsram_init_struct->memory_type = EXMC_MEMORY_TYPE_SRAM; + exmc_norsram_init_struct->databus_width = EXMC_NOR_DATABUS_WIDTH_8B; + exmc_norsram_init_struct->burst_mode = DISABLE; + exmc_norsram_init_struct->nwait_polarity = EXMC_NWAIT_POLARITY_LOW; + exmc_norsram_init_struct->wrap_burst_mode = DISABLE; + exmc_norsram_init_struct->nwait_config = EXMC_NWAIT_CONFIG_BEFORE; + exmc_norsram_init_struct->memory_write = ENABLE; + exmc_norsram_init_struct->nwait_signal = ENABLE; + exmc_norsram_init_struct->extended_mode = DISABLE; + exmc_norsram_init_struct->asyn_wait = DISABLE; + exmc_norsram_init_struct->write_mode = EXMC_ASYN_WRITE; + + /* configure read/write timing */ + exmc_norsram_init_struct->read_write_timing->asyn_address_setuptime = 0xFU; + exmc_norsram_init_struct->read_write_timing->asyn_address_holdtime = 0xFU; + exmc_norsram_init_struct->read_write_timing->asyn_data_setuptime = 0xFFU; + exmc_norsram_init_struct->read_write_timing->bus_latency = 0xFU; + exmc_norsram_init_struct->read_write_timing->syn_clk_division = EXMC_SYN_CLOCK_RATIO_16_CLK; + exmc_norsram_init_struct->read_write_timing->syn_data_latency = EXMC_DATALAT_17_CLK; + exmc_norsram_init_struct->read_write_timing->asyn_access_mode = EXMC_ACCESS_MODE_A; + + /* write timing configure, when extended mode is used */ + exmc_norsram_init_struct->write_timing->asyn_address_setuptime = 0xFU; + exmc_norsram_init_struct->write_timing->asyn_address_holdtime = 0xFU; + exmc_norsram_init_struct->write_timing->asyn_data_setuptime = 0xFFU; + exmc_norsram_init_struct->write_timing->bus_latency = 0xFU; + exmc_norsram_init_struct->write_timing->asyn_access_mode = EXMC_ACCESS_MODE_A; +} + +/*! \brief initialize EXMC NOR/SRAM region \param[in] exmc_norsram_parameter_struct: configure the EXMC NOR/SRAM parameter - norsram_region: EXMC_BANK0_NORSRAM_REGIONx,x=0..3 - write_mode: EXMC_ASYN_WRITE,EXMC_SYN_WRITE - extended_mode: ENABLE or DISABLE + norsram_region: EXMC_BANK0_NORSRAM_REGIONx, x=0..3 + write_mode: EXMC_ASYN_WRITE, EXMC_SYN_WRITE + extended_mode: ENABLE or DISABLE asyn_wait: ENABLE or DISABLE nwait_signal: ENABLE or DISABLE memory_write: ENABLE or DISABLE - nwait_config: EXMC_NWAIT_CONFIG_BEFORE,EXMC_NWAIT_CONFIG_DURING + nwait_config: EXMC_NWAIT_CONFIG_BEFORE, EXMC_NWAIT_CONFIG_DURING wrap_burst_mode: ENABLE or DISABLE - nwait_polarity: EXMC_NWAIT_POLARITY_LOW,EXMC_NWAIT_POLARITY_HIGH + nwait_polarity: EXMC_NWAIT_POLARITY_LOW, EXMC_NWAIT_POLARITY_HIGH burst_mode: ENABLE or DISABLE - databus_width: EXMC_NOR_DATABUS_WIDTH_8B,EXMC_NOR_DATABUS_WIDTH_16B - memory_type: EXMC_MEMORY_TYPE_SRAM,EXMC_MEMORY_TYPE_PSRAM,EXMC_MEMORY_TYPE_NOR + databus_width: EXMC_NOR_DATABUS_WIDTH_8B, EXMC_NOR_DATABUS_WIDTH_16B + memory_type: EXMC_MEMORY_TYPE_SRAM, EXMC_MEMORY_TYPE_PSRAM, EXMC_MEMORY_TYPE_NOR address_data_mux: ENABLE or DISABLE read_write_timing: struct exmc_norsram_timing_parameter_struct set the time + asyn_access_mode: EXMC_ACCESS_MODE_A, EXMC_ACCESS_MODE_B, EXMC_ACCESS_MODE_C, EXMC_ACCESS_MODE_D + syn_data_latency: EXMC_DATALAT_x_CLK, x=2..17 + syn_clk_division: EXMC_SYN_CLOCK_RATIO_x_CLK, x=2..16 + bus_latency: 0x0U~0xFU + asyn_data_setuptime: 0x01U~0xFFU + asyn_address_holdtime: 0x1U~0xFU + asyn_address_setuptime: 0x0U~0xFU write_timing: struct exmc_norsram_timing_parameter_struct set the time + asyn_access_mode: EXMC_ACCESS_MODE_A, EXMC_ACCESS_MODE_B, EXMC_ACCESS_MODE_C, EXMC_ACCESS_MODE_D + syn_data_latency: EXMC_DATALAT_x_CLK, x=2..17 + syn_clk_division: EXMC_SYN_CLOCK_RATIO_x_CLK, x=2..16 + bus_latency: 0x0U~0xFU + asyn_data_setuptime: 0x01U~0xFFU + asyn_address_holdtime: 0x1U~0xFU + asyn_address_setuptime: 0x0U~0xFU \param[out] none \retval none */ @@ -142,23 +222,23 @@ void exmc_norsram_init(exmc_norsram_parameter_struct* exmc_norsram_init_struct) snctl = EXMC_SNCTL(exmc_norsram_init_struct->norsram_region); /* clear relative bits */ - snctl &= ((uint32_t)~(EXMC_SNCTL_EXMODEN | EXMC_SNCTL_NRTP | EXMC_SNCTL_NRW | EXMC_SNCTL_SBRSTEN | - EXMC_SNCTL_NRWTPOL | EXMC_SNCTL_WRAPEN | EXMC_SNCTL_NRWTCFG | EXMC_SNCTL_WREN | - EXMC_SNCTL_NRWTEN | EXMC_SNCTL_EXMODEN | EXMC_SNCTL_ASYNCWAIT | EXMC_SNCTL_SYNCWR | - EXMC_SNCTL_NRBKEN)); + snctl &= ((uint32_t)~(EXMC_SNCTL_NREN | EXMC_SNCTL_NRTP | EXMC_SNCTL_NRW | EXMC_SNCTL_SBRSTEN | + EXMC_SNCTL_NRWTPOL | EXMC_SNCTL_WRAPEN | EXMC_SNCTL_NRWTCFG | EXMC_SNCTL_WREN | + EXMC_SNCTL_NRWTEN | EXMC_SNCTL_EXMODEN | EXMC_SNCTL_ASYNCWAIT | EXMC_SNCTL_SYNCWR | + EXMC_SNCTL_NRMUX )); - snctl = (uint32_t)(exmc_norsram_init_struct->address_data_mux << SNCTL_NRMUX_OFFSET) | - exmc_norsram_init_struct->memory_type | - exmc_norsram_init_struct->databus_width | - (exmc_norsram_init_struct->burst_mode << SNCTL_SBRSTEN_OFFSET) | - exmc_norsram_init_struct->nwait_polarity | - (exmc_norsram_init_struct->wrap_burst_mode << SNCTL_WRAPEN_OFFSET) | - exmc_norsram_init_struct->nwait_config | - (exmc_norsram_init_struct->memory_write << SNCTL_WREN_OFFSET) | - (exmc_norsram_init_struct->nwait_signal << SNCTL_NRWTEN_OFFSET) | - (exmc_norsram_init_struct->extended_mode << SNCTL_EXMODEN_OFFSET) | - (exmc_norsram_init_struct->asyn_wait << SNCTL_ASYNCWAIT_OFFSET) | - exmc_norsram_init_struct->write_mode; + snctl |= (uint32_t)(exmc_norsram_init_struct->address_data_mux << SNCTL_NRMUX_OFFSET) | + exmc_norsram_init_struct->memory_type | + exmc_norsram_init_struct->databus_width | + (exmc_norsram_init_struct->burst_mode << SNCTL_SBRSTEN_OFFSET) | + exmc_norsram_init_struct->nwait_polarity | + (exmc_norsram_init_struct->wrap_burst_mode << SNCTL_WRAPEN_OFFSET) | + exmc_norsram_init_struct->nwait_config | + (exmc_norsram_init_struct->memory_write << SNCTL_WREN_OFFSET) | + (exmc_norsram_init_struct->nwait_signal << SNCTL_NRWTEN_OFFSET) | + (exmc_norsram_init_struct->extended_mode << SNCTL_EXMODEN_OFFSET) | + (exmc_norsram_init_struct->asyn_wait << SNCTL_ASYNCWAIT_OFFSET) | + exmc_norsram_init_struct->write_mode; sntcfg = (uint32_t)exmc_norsram_init_struct->read_write_timing->asyn_address_setuptime | (exmc_norsram_init_struct->read_write_timing->asyn_address_holdtime << SNTCFG_AHLD_OFFSET) | @@ -169,22 +249,18 @@ void exmc_norsram_init(exmc_norsram_parameter_struct* exmc_norsram_init_struct) exmc_norsram_init_struct->read_write_timing->asyn_access_mode; /* nor flash access enable */ - if(EXMC_MEMORY_TYPE_NOR == exmc_norsram_init_struct->memory_type) - { + if(EXMC_MEMORY_TYPE_NOR == exmc_norsram_init_struct->memory_type){ snctl |= (uint32_t)EXMC_SNCTL_NREN; } /* extended mode configure */ - if(ENABLE == exmc_norsram_init_struct->extended_mode) - { + if(ENABLE == exmc_norsram_init_struct->extended_mode){ snwtcfg = (uint32_t)exmc_norsram_init_struct->write_timing->asyn_address_setuptime | (exmc_norsram_init_struct->write_timing->asyn_address_holdtime << SNTCFG_AHLD_OFFSET )| (exmc_norsram_init_struct->write_timing->asyn_data_setuptime << SNTCFG_DSET_OFFSET) | (exmc_norsram_init_struct->write_timing->bus_latency << SNTCFG_BUSLAT_OFFSET) | exmc_norsram_init_struct->write_timing->asyn_access_mode; - } - else - { + }else{ snwtcfg = BANK0_SNWTCFG_RESET; } @@ -195,85 +271,9 @@ void exmc_norsram_init(exmc_norsram_parameter_struct* exmc_norsram_init_struct) } /*! - \brief initialize the struct exmc_norsram_parameter_struct - \param[in] none - \param[out] exmc_norsram_init_struct: the initialized struct exmc_norsram_parameter_struct pointer - \retval none -*/ -void exmc_norsram_parameter_init(exmc_norsram_parameter_struct* exmc_norsram_init_struct) -{ - /* configure the structure with default value */ - exmc_norsram_init_struct->norsram_region = EXMC_BANK0_NORSRAM_REGION0; - exmc_norsram_init_struct->address_data_mux = ENABLE; - exmc_norsram_init_struct->memory_type = EXMC_MEMORY_TYPE_SRAM; - exmc_norsram_init_struct->databus_width = EXMC_NOR_DATABUS_WIDTH_8B; - exmc_norsram_init_struct->burst_mode = DISABLE; - exmc_norsram_init_struct->nwait_polarity = EXMC_NWAIT_POLARITY_LOW; - exmc_norsram_init_struct->wrap_burst_mode = DISABLE; - exmc_norsram_init_struct->nwait_config = EXMC_NWAIT_CONFIG_BEFORE; - exmc_norsram_init_struct->memory_write = ENABLE; - exmc_norsram_init_struct->nwait_signal = ENABLE; - exmc_norsram_init_struct->extended_mode = DISABLE; - exmc_norsram_init_struct->asyn_wait = DISABLE; - exmc_norsram_init_struct->write_mode = EXMC_ASYN_WRITE; - - /* read/write timing configure */ - exmc_norsram_init_struct->read_write_timing->asyn_address_setuptime = 0xFU; - exmc_norsram_init_struct->read_write_timing->asyn_address_holdtime = 0xFU; - exmc_norsram_init_struct->read_write_timing->asyn_data_setuptime = 0xFFU; - exmc_norsram_init_struct->read_write_timing->bus_latency = 0xFU; - exmc_norsram_init_struct->read_write_timing->syn_clk_division = EXMC_SYN_CLOCK_RATIO_16_CLK; - exmc_norsram_init_struct->read_write_timing->syn_data_latency = EXMC_DATALAT_17_CLK; - exmc_norsram_init_struct->read_write_timing->asyn_access_mode = EXMC_ACCESS_MODE_A; - - /* write timing configure, when extended mode is used */ - exmc_norsram_init_struct->write_timing->asyn_address_setuptime = 0xFU; - exmc_norsram_init_struct->write_timing->asyn_address_holdtime = 0xFU; - exmc_norsram_init_struct->write_timing->asyn_data_setuptime = 0xFFU; - exmc_norsram_init_struct->write_timing->bus_latency = 0xFU; - exmc_norsram_init_struct->write_timing->asyn_access_mode = EXMC_ACCESS_MODE_A; -} - -/*! - \brief consecutive clock configure - \param[in] clock_mode: specifie when the clock is generated - \arg EXMC_CLOCK_SYN_MODE: the clock is generated only during synchronous access - \arg EXMC_CLOCK_UNCONDITIONALLY: the clock is generated unconditionally - \param[out] none - \retval none -*/ -void exmc_norsram_consecutive_clock_config(uint32_t clock_mode) -{ - if (EXMC_CLOCK_UNCONDITIONALLY == clock_mode){ - EXMC_SNCTL(EXMC_BANK0_NORSRAM_REGION0) |= EXMC_CLOCK_UNCONDITIONALLY; - }else{ - EXMC_SNCTL(EXMC_BANK0_NORSRAM_REGION0) &= ~EXMC_CLOCK_UNCONDITIONALLY; - } -} - -/*! - \brief CRAM page size configure - \param[in] page_size: CRAM page size - \arg EXMC_CRAM_AUTO_SPLIT: the clock is generated only during synchronous access - \arg EXMC_CRAM_PAGE_SIZE_128_BYTES: page size is 128 bytes - \arg EXMC_CRAM_PAGE_SIZE_256_BYTES: page size is 256 bytes - \arg EXMC_CRAM_PAGE_SIZE_512_BYTES: page size is 512 bytes - \arg EXMC_CRAM_PAGE_SIZE_1024_BYTES: page size is 1024 bytes - \param[out] none - \retval none -*/ -void exmc_norsram_page_size_config(uint32_t page_size) -{ - /* reset the bits */ - EXMC_SNCTL(EXMC_BANK0_NORSRAM_REGION0) &= ~EXMC_SNCTL_CPS; - - /* set the CPS bits */ - EXMC_SNCTL(EXMC_BANK0_NORSRAM_REGION0) |= page_size; -} - -/*! \brief enable EXMC NOR/PSRAM bank region \param[in] exmc_norsram_region: specifie the region of NOR/PSRAM bank + only one parameter can be selected which is shown as below: \arg EXMC_BANK0_NORSRAM_REGIONx(x=0..3) \param[out] none \retval none @@ -286,6 +286,7 @@ void exmc_norsram_enable(uint32_t exmc_norsram_region) /*! \brief disable EXMC NOR/PSRAM bank region \param[in] exmc_norsram_region: specifie the region of NOR/PSRAM Bank + only one parameter can be selected which is shown as below: \arg EXMC_BANK0_NORSRAM_REGIONx(x=0..3) \param[out] none \retval none @@ -298,6 +299,7 @@ void exmc_norsram_disable(uint32_t exmc_norsram_region) /*! \brief deinitialize EXMC NAND bank \param[in] exmc_nand_bank: select the bank of NAND + only one parameter can be selected which is shown as below: \arg EXMC_BANKx_NAND(x=1..2) \param[out] none \retval none @@ -312,6 +314,32 @@ void exmc_nand_deinit(uint32_t exmc_nand_bank) } /*! + \brief initialize exmc_norsram_parameter_struct with the default values + \param[in] none + \param[out] the initialized struct exmc_norsram_parameter_struct pointer + \retval none +*/ +void exmc_nand_struct_para_init(exmc_nand_parameter_struct* exmc_nand_init_struct) +{ + /* configure the structure with default values */ + exmc_nand_init_struct->nand_bank = EXMC_BANK1_NAND; + exmc_nand_init_struct->wait_feature = DISABLE; + exmc_nand_init_struct->databus_width = EXMC_NAND_DATABUS_WIDTH_8B; + exmc_nand_init_struct->ecc_logic = DISABLE; + exmc_nand_init_struct->ecc_size = EXMC_ECC_SIZE_256BYTES; + exmc_nand_init_struct->ctr_latency = 0x0U; + exmc_nand_init_struct->atr_latency = 0x0U; + exmc_nand_init_struct->common_space_timing->setuptime = 0xFCU; + exmc_nand_init_struct->common_space_timing->waittime = 0xFCU; + exmc_nand_init_struct->common_space_timing->holdtime = 0xFCU; + exmc_nand_init_struct->common_space_timing->databus_hiztime = 0xFCU; + exmc_nand_init_struct->attribute_space_timing->setuptime = 0xFCU; + exmc_nand_init_struct->attribute_space_timing->waittime = 0xFCU; + exmc_nand_init_struct->attribute_space_timing->holdtime = 0xFCU; + exmc_nand_init_struct->attribute_space_timing->databus_hiztime = 0xFCU; +} + +/*! \brief initialize EXMC NAND bank \param[in] exmc_nand_parameter_struct: configure the EXMC NAND parameter nand_bank: EXMC_BANK1_NAND,EXMC_BANK2_NAND @@ -322,14 +350,22 @@ void exmc_nand_deinit(uint32_t exmc_nand_bank) databus_width: EXMC_NAND_DATABUS_WIDTH_8B,EXMC_NAND_DATABUS_WIDTH_16B wait_feature: ENABLE or DISABLE common_space_timing: struct exmc_nand_pccard_timing_parameter_struct set the time + databus_hiztime: 0x01U~0xFFU + holdtime: 0x01U~0xFEU + waittime: 0x02U~0xFFU + setuptime: 0x01U~0xFFU attribute_space_timing: struct exmc_nand_pccard_timing_parameter_struct set the time + databus_hiztime: 0x00U~0xFEU + holdtime: 0x01U~0xFEU + waittime: 0x02U~0xFFU + setuptime: 0x01U~0xFFU \param[out] none \retval none */ void exmc_nand_init(exmc_nand_parameter_struct* exmc_nand_init_struct) { uint32_t npctl = 0x00000000U, npctcfg = 0x00000000U, npatcfg = 0x00000000U; - + npctl = (uint32_t)(exmc_nand_init_struct->wait_feature << NPCTL_NDWTEN_OFFSET)| EXMC_NPCTL_NDTP | exmc_nand_init_struct->databus_width | @@ -338,15 +374,15 @@ void exmc_nand_init(exmc_nand_parameter_struct* exmc_nand_init_struct) exmc_nand_init_struct->ctr_latency | exmc_nand_init_struct->atr_latency; - npctcfg = (uint32_t)(exmc_nand_init_struct->common_space_timing->setuptime - 1U) | - ((exmc_nand_init_struct->common_space_timing->waittime - 1U) << NPCTCFG_COMWAIT_OFFSET) | - (exmc_nand_init_struct->common_space_timing->holdtime << NPCTCFG_COMHLD_OFFSET)| - ((exmc_nand_init_struct->common_space_timing->databus_hiztime - 1U) << NPCTCFG_COMHIZ_OFFSET); + npctcfg = (uint32_t)((exmc_nand_init_struct->common_space_timing->setuptime - 1U) & EXMC_NPCTCFG_COMSET ) | + (((exmc_nand_init_struct->common_space_timing->waittime - 1U) << NPCTCFG_COMWAIT_OFFSET) & EXMC_NPCTCFG_COMWAIT ) | + ((exmc_nand_init_struct->common_space_timing->holdtime << NPCTCFG_COMHLD_OFFSET) & EXMC_NPCTCFG_COMHLD ) | + (((exmc_nand_init_struct->common_space_timing->databus_hiztime - 1U) << NPCTCFG_COMHIZ_OFFSET) & EXMC_NPCTCFG_COMHIZ ); - npatcfg = (uint32_t)(exmc_nand_init_struct->attribute_space_timing->setuptime - 1U) | - ((exmc_nand_init_struct->attribute_space_timing->waittime - 1U) << NPATCFG_COMWAIT_OFFSET) | - (exmc_nand_init_struct->attribute_space_timing->holdtime << NPATCFG_COMHLD_OFFSET)| - (exmc_nand_init_struct->attribute_space_timing->databus_hiztime << NPATCFG_COMHIZ_OFFSET); + npatcfg = (uint32_t)((exmc_nand_init_struct->attribute_space_timing->setuptime - 1U) & EXMC_NPATCFG_ATTSET ) | + (((exmc_nand_init_struct->attribute_space_timing->waittime - 1U) << NPATCFG_ATTWAIT_OFFSET) & EXMC_NPATCFG_ATTWAIT ) | + ((exmc_nand_init_struct->attribute_space_timing->holdtime << NPATCFG_ATTHLD_OFFSET) & EXMC_NPATCFG_ATTHLD ) | + ((exmc_nand_init_struct->attribute_space_timing->databus_hiztime << NPATCFG_ATTHIZ_OFFSET) & EXMC_NPATCFG_ATTHIZ ); /* EXMC_BANK1_NAND or EXMC_BANK2_NAND initialize */ EXMC_NPCTL(exmc_nand_init_struct->nand_bank) = npctl; @@ -355,34 +391,9 @@ void exmc_nand_init(exmc_nand_parameter_struct* exmc_nand_init_struct) } /*! - \brief initialize the struct exmc_norsram_parameter_struct - \param[in] none - \param[out] the initialized struct exmc_norsram_parameter_struct pointer - \retval none -*/ -void exmc_nand_parameter_init(exmc_nand_parameter_struct* exmc_nand_init_struct) -{ - /* configure the structure with default value */ - exmc_nand_init_struct->nand_bank = EXMC_BANK1_NAND; - exmc_nand_init_struct->wait_feature = DISABLE; - exmc_nand_init_struct->databus_width = EXMC_NAND_DATABUS_WIDTH_8B; - exmc_nand_init_struct->ecc_logic = DISABLE; - exmc_nand_init_struct->ecc_size = EXMC_ECC_SIZE_256BYTES; - exmc_nand_init_struct->ctr_latency = 0x0U; - exmc_nand_init_struct->atr_latency = 0x0U; - exmc_nand_init_struct->common_space_timing->setuptime = 0xfcU; - exmc_nand_init_struct->common_space_timing->waittime = 0xfcU; - exmc_nand_init_struct->common_space_timing->holdtime = 0xfcU; - exmc_nand_init_struct->common_space_timing->databus_hiztime = 0xfcU; - exmc_nand_init_struct->attribute_space_timing->setuptime = 0xfcU; - exmc_nand_init_struct->attribute_space_timing->waittime = 0xfcU; - exmc_nand_init_struct->attribute_space_timing->holdtime = 0xfcU; - exmc_nand_init_struct->attribute_space_timing->databus_hiztime = 0xfcU; -} - -/*! \brief enable NAND bank \param[in] exmc_nand_bank: specifie the NAND bank + only one parameter can be selected which is shown as below: \arg EXMC_BANKx_NAND(x=1,2) \param[out] none \retval none @@ -395,6 +406,7 @@ void exmc_nand_enable(uint32_t exmc_nand_bank) /*! \brief disable NAND bank \param[in] exmc_nand_bank: specifie the NAND bank + only one parameter can be selected which is shown as below: \arg EXMC_BANKx_NAND(x=1,2) \param[out] none \retval none @@ -405,40 +417,6 @@ void exmc_nand_disable(uint32_t exmc_nand_bank) } /*! - \brief enable or disable the EXMC NAND ECC function - \param[in] exmc_nand_bank: specifie the NAND bank - \arg EXMC_BANKx_NAND(x=1,2) - \param[in] newvalue: ENABLE or DISABLE - \param[out] none - \retval none -*/ -void exmc_nand_ecc_config(uint32_t exmc_nand_bank, ControlStatus newvalue) -{ - if (ENABLE == newvalue) - { - /* enable the selected NAND bank ECC function */ - EXMC_NPCTL(exmc_nand_bank) |= EXMC_NPCTL_ECCEN; - } - else - { - /* disable the selected NAND bank ECC function */ - EXMC_NPCTL(exmc_nand_bank) &= ~EXMC_NPCTL_ECCEN; - } -} - -/*! - \brief get the EXMC ECC value - \param[in] exmc_nand_bank: specifie the NAND bank - \arg EXMC_BANKx_NAND(x=1,2) - \param[out] none - \retval the error correction code(ECC) value -*/ -uint32_t exmc_ecc_get(uint32_t exmc_nand_bank) -{ - return(EXMC_NECC(exmc_nand_bank)); -} - -/*! \brief deinitialize EXMC PC card bank \param[in] none \param[out] none @@ -455,14 +433,52 @@ void exmc_pccard_deinit(void) } /*! + \brief initialize exmc_pccard_parameter_struct with the default values + \param[in] none + \param[out] the initialized struct exmc_pccard_parameter_struct pointer + \retval none +*/ +void exmc_pccard_struct_para_init(exmc_pccard_parameter_struct* exmc_pccard_init_struct) +{ + /* configure the structure with default values */ + exmc_pccard_init_struct->wait_feature = DISABLE; + exmc_pccard_init_struct->ctr_latency = 0x0U; + exmc_pccard_init_struct->atr_latency = 0x0U; + exmc_pccard_init_struct->common_space_timing->setuptime = 0xFCU; + exmc_pccard_init_struct->common_space_timing->waittime = 0xFCU; + exmc_pccard_init_struct->common_space_timing->holdtime = 0xFCU; + exmc_pccard_init_struct->common_space_timing->databus_hiztime = 0xFCU; + exmc_pccard_init_struct->attribute_space_timing->setuptime = 0xFCU; + exmc_pccard_init_struct->attribute_space_timing->waittime = 0xFCU; + exmc_pccard_init_struct->attribute_space_timing->holdtime = 0xFCU; + exmc_pccard_init_struct->attribute_space_timing->databus_hiztime = 0xFCU; + exmc_pccard_init_struct->io_space_timing->setuptime = 0xFCU; + exmc_pccard_init_struct->io_space_timing->waittime = 0xFCU; + exmc_pccard_init_struct->io_space_timing->holdtime = 0xFCU; + exmc_pccard_init_struct->io_space_timing->databus_hiztime = 0xFCU; +} + +/*! \brief initialize EXMC PC card bank \param[in] exmc_pccard_parameter_struct: configure the EXMC NAND parameter atr_latency: EXMC_ALE_RE_DELAY_x_HCLK,x=1..16 ctr_latency: EXMC_CLE_RE_DELAY_x_HCLK,x=1..16 wait_feature: ENABLE or DISABLE common_space_timing: struct exmc_nand_pccard_timing_parameter_struct set the time + databus_hiztime: 0x01U~0xFFU + holdtime: 0x01U~0xFEU + waittime: 0x02U~0xFFU + setuptime: 0x01U~0xFFU attribute_space_timing: struct exmc_nand_pccard_timing_parameter_struct set the time + databus_hiztime: 0x00U~0xFEU + holdtime: 0x01U~0xFEU + waittime: 0x02U~0xFFU + setuptime: 0x01U~0xFFU io_space_timing: exmc_nand_pccard_timing_parameter_struct set the time + databus_hiztime: 0x00U~0xFFU + holdtime: 0x01U~0xFFU + waittime: 0x02U~0x100U + setuptime: 0x01U~0x100U \param[out] none \retval none */ @@ -470,53 +486,27 @@ void exmc_pccard_init(exmc_pccard_parameter_struct* exmc_pccard_init_struct) { /* configure the EXMC bank3 PC card control register */ EXMC_NPCTL3 = (uint32_t)(exmc_pccard_init_struct->wait_feature << NPCTL_NDWTEN_OFFSET) | - EXMC_NAND_DATABUS_WIDTH_16B | + EXMC_NAND_DATABUS_WIDTH_16B | exmc_pccard_init_struct->ctr_latency | exmc_pccard_init_struct->atr_latency ; - + /* configure the EXMC bank3 PC card common space timing configuration register */ - EXMC_NPCTCFG3 = (uint32_t)(exmc_pccard_init_struct->common_space_timing->setuptime - 1U) | - ((exmc_pccard_init_struct->common_space_timing->waittime - 1U) << NPCTCFG_COMWAIT_OFFSET) | - (exmc_pccard_init_struct->common_space_timing->holdtime << NPCTCFG_COMHLD_OFFSET)| - ((exmc_pccard_init_struct->common_space_timing->databus_hiztime - 1U) << NPCTCFG_COMHIZ_OFFSET); + EXMC_NPCTCFG3 = (uint32_t)((exmc_pccard_init_struct->common_space_timing->setuptime - 1U) & EXMC_NPCTCFG_COMSET ) | + (((exmc_pccard_init_struct->common_space_timing->waittime - 1U) << NPCTCFG_COMWAIT_OFFSET) & EXMC_NPCTCFG_COMWAIT ) | + ((exmc_pccard_init_struct->common_space_timing->holdtime << NPCTCFG_COMHLD_OFFSET) & EXMC_NPCTCFG_COMHLD ) | + (((exmc_pccard_init_struct->common_space_timing->databus_hiztime - 1U) << NPCTCFG_COMHIZ_OFFSET) & EXMC_NPCTCFG_COMHIZ ); /* configure the EXMC bank3 PC card attribute space timing configuration register */ - EXMC_NPATCFG3 = (uint32_t)(exmc_pccard_init_struct->attribute_space_timing->setuptime - 1U) | - ((exmc_pccard_init_struct->attribute_space_timing->waittime - 1U) << NPATCFG_COMWAIT_OFFSET) | - (exmc_pccard_init_struct->attribute_space_timing->holdtime << NPATCFG_COMHLD_OFFSET)| - (exmc_pccard_init_struct->attribute_space_timing->databus_hiztime << NPATCFG_COMHIZ_OFFSET); + EXMC_NPATCFG3 = (uint32_t)((exmc_pccard_init_struct->attribute_space_timing->setuptime - 1U) & EXMC_NPATCFG_ATTSET ) | + (((exmc_pccard_init_struct->attribute_space_timing->waittime - 1U) << NPATCFG_ATTWAIT_OFFSET) & EXMC_NPATCFG_ATTWAIT ) | + ((exmc_pccard_init_struct->attribute_space_timing->holdtime << NPATCFG_ATTHLD_OFFSET) & EXMC_NPATCFG_ATTHLD ) | + ((exmc_pccard_init_struct->attribute_space_timing->databus_hiztime << NPATCFG_ATTHIZ_OFFSET) & EXMC_NPATCFG_ATTHIZ); /* configure the EXMC bank3 PC card io space timing configuration register */ - EXMC_PIOTCFG3 = (uint32_t)(exmc_pccard_init_struct->io_space_timing->setuptime - 1U) | - ((exmc_pccard_init_struct->io_space_timing->waittime - 1U) << PIOTCFG_COMWAIT_OFFSET) | - (exmc_pccard_init_struct->io_space_timing->holdtime << PIOTCFG_COMHLD_OFFSET)| - (exmc_pccard_init_struct->io_space_timing->databus_hiztime << PIOTCFG_COMHIZ_OFFSET); -} - -/*! - \brief initialize the struct exmc_pccard_parameter_struct - \param[in] none - \param[out] the initialized struct exmc_pccard_parameter_struct pointer - \retval none -*/ -void exmc_pccard_parameter_init(exmc_pccard_parameter_struct* exmc_pccard_init_struct) -{ - /* configure the structure with default value */ - exmc_pccard_init_struct->wait_feature = DISABLE; - exmc_pccard_init_struct->ctr_latency = 0x0U; - exmc_pccard_init_struct->atr_latency = 0x0U; - exmc_pccard_init_struct->common_space_timing->setuptime = 0xFCU; - exmc_pccard_init_struct->common_space_timing->waittime = 0xFCU; - exmc_pccard_init_struct->common_space_timing->holdtime = 0xFCU; - exmc_pccard_init_struct->common_space_timing->databus_hiztime = 0xFCU; - exmc_pccard_init_struct->attribute_space_timing->setuptime = 0xFCU; - exmc_pccard_init_struct->attribute_space_timing->waittime = 0xFCU; - exmc_pccard_init_struct->attribute_space_timing->holdtime = 0xFCU; - exmc_pccard_init_struct->attribute_space_timing->databus_hiztime = 0xFCU; - exmc_pccard_init_struct->io_space_timing->setuptime = 0xFCU; - exmc_pccard_init_struct->io_space_timing->waittime = 0xFCU; - exmc_pccard_init_struct->io_space_timing->holdtime = 0xFCU; - exmc_pccard_init_struct->io_space_timing->databus_hiztime = 0xFCU; + EXMC_PIOTCFG3 = (uint32_t)((exmc_pccard_init_struct->io_space_timing->setuptime - 1U) & EXMC_PIOTCFG3_IOSET ) | + (((exmc_pccard_init_struct->io_space_timing->waittime - 1U) << PIOTCFG_IOWAIT_OFFSET) & EXMC_PIOTCFG3_IOWAIT ) | + ((exmc_pccard_init_struct->io_space_timing->holdtime << PIOTCFG_IOHLD_OFFSET) & EXMC_PIOTCFG3_IOHLD ) | + ((exmc_pccard_init_struct->io_space_timing->databus_hiztime << PIOTCFG_IOHIZ_OFFSET) & EXMC_PIOTCFG3_IOHIZ ); } /*! @@ -543,6 +533,9 @@ void exmc_pccard_disable(void) /*! \brief deinitialize EXMC SDRAM device + \param[in] exmc_sdram_device: select the SRAM device + only one parameter can be selected which is shown as below: + \arg EXMC_SDRAM_DEVICEx(x=0, 1) \param[in] none \param[out] none \retval none @@ -558,6 +551,35 @@ void exmc_sdram_deinit(uint32_t exmc_sdram_device) } /*! + \brief initialize exmc_sdram_parameter_struct with the default values + \param[in] none + \param[out] the initialized struct exmc_pccard_parameter_struct pointer + \retval none +*/ +void exmc_sdram_struct_para_init(exmc_sdram_parameter_struct* exmc_sdram_init_struct) +{ + /* configure the structure with default values */ + exmc_sdram_init_struct->sdram_device = EXMC_SDRAM_DEVICE0; + exmc_sdram_init_struct->column_address_width = EXMC_SDRAM_COW_ADDRESS_8; + exmc_sdram_init_struct->row_address_width = EXMC_SDRAM_ROW_ADDRESS_11; + exmc_sdram_init_struct->data_width = EXMC_SDRAM_DATABUS_WIDTH_16B; + exmc_sdram_init_struct->internal_bank_number = EXMC_SDRAM_4_INTER_BANK; + exmc_sdram_init_struct->cas_latency = EXMC_CAS_LATENCY_1_SDCLK; + exmc_sdram_init_struct->write_protection = ENABLE; + exmc_sdram_init_struct->sdclock_config = EXMC_SDCLK_DISABLE; + exmc_sdram_init_struct->brust_read_switch = DISABLE; + exmc_sdram_init_struct->pipeline_read_delay = EXMC_PIPELINE_DELAY_0_HCLK; + + exmc_sdram_init_struct->timing->load_mode_register_delay = 16U; + exmc_sdram_init_struct->timing->exit_selfrefresh_delay = 16U; + exmc_sdram_init_struct->timing->row_address_select_delay = 16U; + exmc_sdram_init_struct->timing->auto_refresh_delay = 16U; + exmc_sdram_init_struct->timing->write_recovery_delay = 16U; + exmc_sdram_init_struct->timing->row_precharge_delay = 16U; + exmc_sdram_init_struct->timing->row_to_column_delay = 16U; +} + +/*! \brief initialize EXMC SDRAM device \param[in] exmc_sdram_parameter_struct: configure the EXMC SDRAM parameter sdram_device: EXMC_SDRAM_DEVICE0,EXMC_SDRAM_DEVICE1 @@ -571,6 +593,13 @@ void exmc_sdram_deinit(uint32_t exmc_sdram_device) row_address_width: EXMC_SDRAM_ROW_ADDRESS_x,x=11..13 column_address_width: EXMC_SDRAM_COW_ADDRESS_x,x=8..11 timing: exmc_sdram_timing_parameter_struct set the time + row_to_column_delay: 1U~16U + row_precharge_delay: 1U~16U + write_recovery_delay: 1U~16U + auto_refresh_delay: 1U~16U + row_address_select_delay: 1U~16U + exit_selfrefresh_delay: 1U~16U + load_mode_register_delay: 1U~16U \param[out] none \retval none */ @@ -578,7 +607,7 @@ void exmc_sdram_init(exmc_sdram_parameter_struct* exmc_sdram_init_struct) { uint32_t sdctl0, sdctl1, sdtcfg0, sdtcfg1; - /* configuration EXMC_SDCTL0 or EXMC_SDCTL1 */ + /* configuration EXMC_SDCTL0 or EXMC_SDCTL1 */ if(EXMC_SDRAM_DEVICE0 == exmc_sdram_init_struct->sdram_device){ /* configuration EXMC_SDCTL0 */ EXMC_SDCTL(EXMC_SDRAM_DEVICE0) = (uint32_t)exmc_sdram_init_struct->column_address_width | @@ -588,9 +617,9 @@ void exmc_sdram_init(exmc_sdram_parameter_struct* exmc_sdram_init_struct) exmc_sdram_init_struct->cas_latency | (exmc_sdram_init_struct->write_protection << SDCTL_WPEN_OFFSET)| exmc_sdram_init_struct->sdclock_config | - (exmc_sdram_init_struct->brust_read_switch << SDCTL_BRSTRD_OFFSET)| + (exmc_sdram_init_struct->brust_read_switch << SDCTL_BRSTRD_OFFSET)| exmc_sdram_init_struct->pipeline_read_delay; - + /* configuration EXMC_SDTCFG0 */ EXMC_SDTCFG(EXMC_SDRAM_DEVICE0) = (uint32_t)((exmc_sdram_init_struct->timing->load_mode_register_delay)-1U) | (((exmc_sdram_init_struct->timing->exit_selfrefresh_delay)-1U) << SDTCFG_XSRD_OFFSET) | @@ -603,11 +632,11 @@ void exmc_sdram_init(exmc_sdram_parameter_struct* exmc_sdram_init_struct) /* configuration EXMC_SDCTL0 and EXMC_SDCTL1 */ /* some bits in the EXMC_SDCTL1 register are reserved */ sdctl0 = EXMC_SDCTL(EXMC_SDRAM_DEVICE0) & (~( EXMC_SDCTL_PIPED | EXMC_SDCTL_BRSTRD | EXMC_SDCTL_SDCLK )); - + sdctl0 |= (uint32_t)exmc_sdram_init_struct->sdclock_config | - exmc_sdram_init_struct->brust_read_switch | + exmc_sdram_init_struct->brust_read_switch | exmc_sdram_init_struct->pipeline_read_delay; - + sdctl1 = (uint32_t)exmc_sdram_init_struct->column_address_width | exmc_sdram_init_struct->row_address_width | exmc_sdram_init_struct->data_width | @@ -617,7 +646,7 @@ void exmc_sdram_init(exmc_sdram_parameter_struct* exmc_sdram_init_struct) EXMC_SDCTL(EXMC_SDRAM_DEVICE0) = sdctl0; EXMC_SDCTL(EXMC_SDRAM_DEVICE1) = sdctl1; - + /* configuration EXMC_SDTCFG0 and EXMC_SDTCFG1 */ /* some bits in the EXMC_SDTCFG1 register are reserved */ sdtcfg0 = EXMC_SDTCFG(EXMC_SDRAM_DEVICE0) & (~(EXMC_SDTCFG_RPD | EXMC_SDTCFG_WRD | EXMC_SDTCFG_ARFD)); @@ -629,7 +658,7 @@ void exmc_sdram_init(exmc_sdram_parameter_struct* exmc_sdram_init_struct) sdtcfg1 = (uint32_t)((exmc_sdram_init_struct->timing->load_mode_register_delay)-1U) | (((exmc_sdram_init_struct->timing->exit_selfrefresh_delay)-1U) << SDTCFG_XSRD_OFFSET) | (((exmc_sdram_init_struct->timing->row_address_select_delay)-1U) << SDTCFG_RASD_OFFSET) | - (((exmc_sdram_init_struct->timing->row_to_column_delay)-1U) << SDTCFG_RCD_OFFSET); + (((exmc_sdram_init_struct->timing->row_to_column_delay)-1U) << SDTCFG_RCD_OFFSET); EXMC_SDTCFG(EXMC_SDRAM_DEVICE0) = sdtcfg0; EXMC_SDTCFG(EXMC_SDRAM_DEVICE1) = sdtcfg1; @@ -637,121 +666,152 @@ void exmc_sdram_init(exmc_sdram_parameter_struct* exmc_sdram_init_struct) } /*! - \brief initialize the struct exmc_pccard_parameter_struct + \brief deinitialize exmc SQPIPSRAM \param[in] none - \param[out] the initialized struct exmc_pccard_parameter_struct pointer + \param[out] none \retval none */ -void exmc_sdram_parameter_init(exmc_sdram_parameter_struct* exmc_sdram_init_struct) +void exmc_sqpipsram_deinit(void) { - /* configure the structure with default value */ - exmc_sdram_init_struct->sdram_device = EXMC_SDRAM_DEVICE0; - exmc_sdram_init_struct->column_address_width = EXMC_SDRAM_COW_ADDRESS_8; - exmc_sdram_init_struct->row_address_width = EXMC_SDRAM_ROW_ADDRESS_11; - exmc_sdram_init_struct->data_width = EXMC_SDRAM_DATABUS_WIDTH_16B; - exmc_sdram_init_struct->internal_bank_number = EXMC_SDRAM_4_INTER_BANK; - exmc_sdram_init_struct->cas_latency = EXMC_CAS_LATENCY_1_SDCLK; - exmc_sdram_init_struct->write_protection = ENABLE; - exmc_sdram_init_struct->sdclock_config = EXMC_SDCLK_DISABLE; - exmc_sdram_init_struct->brust_read_switch = DISABLE; - exmc_sdram_init_struct->pipeline_read_delay = EXMC_PIPELINE_DELAY_0_HCLK; + /* reset the registers */ + EXMC_SINIT = BANK0_SQPI_SINIT_RESET; + EXMC_SRCMD = BANK0_SQPI_SRCMD_RESET; + EXMC_SWCMD = BANK0_SQPI_SWCMD_RESET; + EXMC_SIDL = BANK0_SQPI_SIDL_RESET; + EXMC_SIDH = BANK0_SQPI_SIDH_RESET; +} - exmc_sdram_init_struct->timing->load_mode_register_delay = 16U; - exmc_sdram_init_struct->timing->exit_selfrefresh_delay = 16U; - exmc_sdram_init_struct->timing->row_address_select_delay = 16U; - exmc_sdram_init_struct->timing->auto_refresh_delay = 16U; - exmc_sdram_init_struct->timing->write_recovery_delay = 16U; - exmc_sdram_init_struct->timing->row_precharge_delay = 16U; - exmc_sdram_init_struct->timing->row_to_column_delay = 16U; +/*! + \brief initialize exmc_sqpipsram_parameter_struct with the default values + \param[in] the struct exmc_sqpipsram_parameter_struct pointer + \param[out] none + \retval none +*/ +void exmc_sqpipsram_struct_para_init(exmc_sqpipsram_parameter_struct* exmc_sqpipsram_init_struct) +{ + /* configure the structure with default values */ + exmc_sqpipsram_init_struct->sample_polarity = EXMC_SQPIPSRAM_SAMPLE_RISING_EDGE; + exmc_sqpipsram_init_struct->id_length = EXMC_SQPIPSRAM_ID_LENGTH_64B; + exmc_sqpipsram_init_struct->address_bits = EXMC_SQPIPSRAM_ADDR_LENGTH_24B; + exmc_sqpipsram_init_struct->command_bits = EXMC_SQPIPSRAM_COMMAND_LENGTH_8B; } /*! - \brief configure the SDRAM memory command - \param[in] the struct exmc_sdram_command_parameter_struct pointer + \brief initialize EXMC SQPIPSRAM + \param[in] exmc_sqpipsram_parameter_struct: configure the EXMC SQPIPSRAM parameter + sample_polarity: EXMC_SQPIPSRAM_SAMPLE_RISING_EDGE,EXMC_SQPIPSRAM_SAMPLE_FALLING_EDGE + id_length: EXMC_SQPIPSRAM_ID_LENGTH_xB,x=8,16,32,64 + address_bits: EXMC_SQPIPSRAM_ADDR_LENGTH_xB,x=1..26 + command_bits: EXMC_SQPIPSRAM_COMMAND_LENGTH_xB,x=4,8,16 \param[out] none \retval none */ -void exmc_sdram_command_config(exmc_sdram_command_parameter_struct* exmc_sdram_command_init_struct) +void exmc_sqpipsram_init(exmc_sqpipsram_parameter_struct* exmc_sqpipsram_init_struct) { - /* configure command register */ - EXMC_SDCMD = (uint32_t)((exmc_sdram_command_init_struct->command) | - (exmc_sdram_command_init_struct->bank_select) | - ((exmc_sdram_command_init_struct->auto_refresh_number)) | - ((exmc_sdram_command_init_struct->mode_register_content)<<SDCMD_MRC_OFFSET) ); + /* initialize SQPI controller */ + EXMC_SINIT = (uint32_t)exmc_sqpipsram_init_struct->sample_polarity | + exmc_sqpipsram_init_struct->id_length | + exmc_sqpipsram_init_struct->address_bits | + exmc_sqpipsram_init_struct->command_bits; } /*! - \brief set auto-refresh interval - \param[in] exmc_count: the number SDRAM clock cycles unit between two successive auto-refresh commands + \brief configure consecutive clock + \param[in] clock_mode: specifie when the clock is generated + only one parameter can be selected which is shown as below: + \arg EXMC_CLOCK_SYN_MODE: the clock is generated only during synchronous access + \arg EXMC_CLOCK_UNCONDITIONALLY: the clock is generated unconditionally \param[out] none \retval none */ -void exmc_sdram_refresh_count_set(uint32_t exmc_count) +void exmc_norsram_consecutive_clock_config(uint32_t clock_mode) { - uint32_t sdari; - sdari = EXMC_SDARI & (~EXMC_SDARI_ARINTV); - EXMC_SDARI = sdari | (uint32_t)((exmc_count << SDARI_ARINTV_OFFSET) & EXMC_SDARI_ARINTV); + if (EXMC_CLOCK_UNCONDITIONALLY == clock_mode){ + EXMC_SNCTL(EXMC_BANK0_NORSRAM_REGION0) |= EXMC_CLOCK_UNCONDITIONALLY; + }else{ + EXMC_SNCTL(EXMC_BANK0_NORSRAM_REGION0) &= ~EXMC_CLOCK_UNCONDITIONALLY; + } } /*! - \brief set the number of successive auto-refresh command - \param[in] exmc_number: the number SDRAM clock cycles unit between two successive auto-refresh commands + \brief configure CRAM page size + \param[in] exmc_norsram_region: select the region of bank0 + only one parameter can be selected which is shown as below: + \arg EXMC_BANK0_NORSRAM_REGIONx(x=0..3) + \param[in] page_size: CRAM page size + only one parameter can be selected which is shown as below: + \arg EXMC_CRAM_AUTO_SPLIT: the clock is generated only during synchronous access + \arg EXMC_CRAM_PAGE_SIZE_128_BYTES: page size is 128 bytes + \arg EXMC_CRAM_PAGE_SIZE_256_BYTES: page size is 256 bytes + \arg EXMC_CRAM_PAGE_SIZE_512_BYTES: page size is 512 bytes + \arg EXMC_CRAM_PAGE_SIZE_1024_BYTES: page size is 1024 bytes \param[out] none \retval none */ -void exmc_sdram_autorefresh_number_set(uint32_t exmc_number) +void exmc_norsram_page_size_config(uint32_t exmc_norsram_region, uint32_t page_size) { - uint32_t sdcmd; - sdcmd = EXMC_SDCMD & (~EXMC_SDCMD_NARF); - EXMC_SDCMD = sdcmd | (uint32_t)((exmc_number << SDCMD_NARF_OFFSET) & EXMC_SDCMD_NARF) ; + /* reset the bits */ + EXMC_SNCTL(exmc_norsram_region) &= ~EXMC_SNCTL_CPS; + + /* set the CPS bits */ + EXMC_SNCTL(exmc_norsram_region) |= page_size; } /*! - \brief config the write protection function - \param[in] exmc_sdram_device: specifie the SDRAM device - \arg EXMC_SDRAM_DEVICEx(x=0,1) + \brief enable or disable the EXMC NAND ECC function + \param[in] exmc_nand_bank: specifie the NAND bank + only one parameter can be selected which is shown as below: + \arg EXMC_BANKx_NAND(x=1,2) \param[in] newvalue: ENABLE or DISABLE \param[out] none \retval none */ -void exmc_sdram_write_protection_config(uint32_t exmc_sdram_device, ControlStatus newvalue) +void exmc_nand_ecc_config(uint32_t exmc_nand_bank, ControlStatus newvalue) { if (ENABLE == newvalue){ - EXMC_SDCTL(exmc_sdram_device) |= (uint32_t)EXMC_SDCTL_WPEN; + /* enable the selected NAND bank ECC function */ + EXMC_NPCTL(exmc_nand_bank) |= EXMC_NPCTL_ECCEN; }else{ - EXMC_SDCTL(exmc_sdram_device) &= ~((uint32_t)EXMC_SDCTL_WPEN); + /* disable the selected NAND bank ECC function */ + EXMC_NPCTL(exmc_nand_bank) &= ~EXMC_NPCTL_ECCEN; } - } /*! - \brief get the status of SDRAM device0 or device1 - \param[in] exmc_sdram_device: specifie the SDRAM device - \arg EXMC_SDRAM_DEVICEx(x=0,1) + \brief get the EXMC ECC value + \param[in] exmc_nand_bank: specifie the NAND bank + only one parameter can be selected which is shown as below: + \arg EXMC_BANKx_NAND(x=1,2) \param[out] none - \retval the status of SDRAM device + \retval the error correction code(ECC) value */ -uint32_t exmc_sdram_bankstatus_get(uint32_t exmc_sdram_device) +uint32_t exmc_ecc_get(uint32_t exmc_nand_bank) { - uint32_t sdstat = 0U; + return(EXMC_NECC(exmc_nand_bank)); +} - if(EXMC_SDRAM_DEVICE0 == exmc_sdram_device) - { - sdstat = ((uint32_t)(EXMC_SDSTAT & EXMC_SDSDAT_STA0) >> SDSTAT_STA0_OFFSET); - } - else - { - sdstat = ((uint32_t)(EXMC_SDSTAT & EXMC_SDSDAT_STA1) >> SDSTAT_STA1_OFFSET); +/*! + \brief enable or disable read sample + \param[in] newvalue: ENABLE or DISABLE + \param[out] none + \retval none +*/ +void exmc_sdram_readsample_enable(ControlStatus newvalue) +{ + if (ENABLE == newvalue){ + EXMC_SDRSCTL |= EXMC_SDRSCTL_RSEN; + }else{ + EXMC_SDRSCTL &= (uint32_t)(~EXMC_SDRSCTL_RSEN); } - - return sdstat; } /*! \brief configure the delayed sample clock of read data \param[in] delay_cell: SDRAM the delayed sample clock of read data + only one parameter can be selected which is shown as below: \arg EXMC_SDRAM_x_DELAY_CELL(x=0..15) \param[in] extra_hclk: sample cycle of read data + only one parameter can be selected which is shown as below: \arg EXMC_SDRAM_READSAMPLE_x_EXTRAHCLK(x=0,1) \param[out] none \retval none @@ -759,81 +819,106 @@ uint32_t exmc_sdram_bankstatus_get(uint32_t exmc_sdram_device) void exmc_sdram_readsample_config(uint32_t delay_cell, uint32_t extra_hclk) { uint32_t sdrsctl = 0U; - + + /* reset the bits */ sdrsctl = EXMC_SDRSCTL & (~(EXMC_SDRSCTL_SDSC | EXMC_SDRSCTL_SSCR)); + /* set the bits */ sdrsctl |= (uint32_t)(delay_cell & EXMC_SDRSCTL_SDSC) | ((extra_hclk << SDRSCTL_SSCR_OFFSET) & EXMC_SDRSCTL_SSCR); EXMC_SDRSCTL = sdrsctl; } /*! - \brief enable or disable read sample - \param[in] newvalue: ENABLE or DISABLE + \brief configure the SDRAM memory command + \param[in] exmc_sdram_command_init_struct: initialize EXMC SDRAM command + mode_register_content: + auto_refresh_number: EXMC_SDRAM_AUTO_REFLESH_x_SDCLK, x=1..15 + bank_select: EXMC_SDRAM_DEVICE0_SELECT, EXMC_SDRAM_DEVICE1_SELECT, EXMC_SDRAM_DEVICE0_1_SELECT + command: EXMC_SDRAM_NORMAL_OPERATION, EXMC_SDRAM_CLOCK_ENABLE, EXMC_SDRAM_PRECHARGE_ALL, + EXMC_SDRAM_AUTO_REFRESH, EXMC_SDRAM_LOAD_MODE_REGISTER, EXMC_SDRAM_SELF_REFRESH, + EXMC_SDRAM_POWERDOWN_ENTRY \param[out] none \retval none */ -void exmc_sdram_readsample_enable(ControlStatus newvalue) +void exmc_sdram_command_config(exmc_sdram_command_parameter_struct* exmc_sdram_command_init_struct) { - if (ENABLE == newvalue){ - EXMC_SDRSCTL |= EXMC_SDRSCTL_RSEN; - }else{ - EXMC_SDRSCTL &= (uint32_t)(~EXMC_SDRSCTL_RSEN); - } + /* configure command register */ + EXMC_SDCMD = (uint32_t)((exmc_sdram_command_init_struct->command) | + (exmc_sdram_command_init_struct->bank_select) | + ((exmc_sdram_command_init_struct->auto_refresh_number)) | + ((exmc_sdram_command_init_struct->mode_register_content)<<SDCMD_MRC_OFFSET) ); } /*! - \brief deinitialize exmc SQPIPSRAM - \param[in] none + \brief set auto-refresh interval + \param[in] exmc_count: the number SDRAM clock cycles unit between two successive auto-refresh commands, 0x0000~0x1FFF \param[out] none \retval none */ -void exmc_sqpipsram_deinit(void) +void exmc_sdram_refresh_count_set(uint32_t exmc_count) { - /* reset the registers */ - EXMC_SINIT = BANK0_SQPI_SINIT_RESET; - EXMC_SRCMD = BANK0_SQPI_SRCMD_RESET; - EXMC_SWCMD = BANK0_SQPI_SWCMD_RESET; - EXMC_SIDL = BANK0_SQPI_SIDL_RESET; - EXMC_SIDH = BANK0_SQPI_SIDH_RESET; + uint32_t sdari; + sdari = EXMC_SDARI & (~EXMC_SDARI_ARINTV); + EXMC_SDARI = sdari | (uint32_t)((exmc_count << SDARI_ARINTV_OFFSET) & EXMC_SDARI_ARINTV); } /*! - \brief initialize EXMC SQPIPSRAM - \param[in] exmc_sqpipsram_parameter_struct: configure the EXMC SQPIPSRAM parameter - sample_polarity: EXMC_SDRAM_SAMPLE_RISING_EDGE,EXMC_SDRAM_SAMPLE_FALLING_EDGE - id_length: EXMC_SQPIPSRAM_ID_LENGTH_xB,x=8,16,32,64 - address_bits: EXMC_SQPIPSRAM_ADDR_LENGTH_xB,x=1..26 - command_bits: EXMC_SQPIPSRAM_COMMAND_LENGTH_xB,x=4,8,16 + \brief set the number of successive auto-refresh command + \param[in] exmc_number: the number of successive Auto-refresh cycles will be send, 1~15 \param[out] none \retval none */ -void exmc_sqpipsram_init(exmc_sqpipsram_parameter_struct* exmc_sqpipsram_init_struct) +void exmc_sdram_autorefresh_number_set(uint32_t exmc_number) { - /* initialize SQPI controller */ - EXMC_SINIT = (uint32_t)exmc_sqpipsram_init_struct->sample_polarity | - exmc_sqpipsram_init_struct->id_length | - exmc_sqpipsram_init_struct->address_bits | - exmc_sqpipsram_init_struct->command_bits; + uint32_t sdcmd; + sdcmd = EXMC_SDCMD & (~EXMC_SDCMD_NARF); + EXMC_SDCMD = sdcmd | (uint32_t)((exmc_number << SDCMD_NARF_OFFSET) & EXMC_SDCMD_NARF) ; } /*! - \brief initialize the struct exmc_sqpipsram_parameter_struct - \param[in] the struct exmc_sqpipsram_parameter_struct pointer + \brief config the write protection function + \param[in] exmc_sdram_device: specifie the SDRAM device + only one parameter can be selected which is shown as below: + \arg EXMC_SDRAM_DEVICEx(x=0,1) + \param[in] newvalue: ENABLE or DISABLE \param[out] none \retval none */ -void exmc_sqpipsram_parameter_init(exmc_sqpipsram_parameter_struct* exmc_sqpipsram_init_struct) +void exmc_sdram_write_protection_config(uint32_t exmc_sdram_device, ControlStatus newvalue) { - /* configure the structure with default value */ - exmc_sqpipsram_init_struct->sample_polarity = EXMC_SDRAM_SAMPLE_RISING_EDGE; - exmc_sqpipsram_init_struct->id_length = EXMC_SQPIPSRAM_ID_LENGTH_64B; - exmc_sqpipsram_init_struct->address_bits = EXMC_SQPIPSRAM_ADDR_LENGTH_24B; - exmc_sqpipsram_init_struct->command_bits = EXMC_SQPIPSRAM_COMMAND_LENGTH_8B; + if (ENABLE == newvalue){ + EXMC_SDCTL(exmc_sdram_device) |= (uint32_t)EXMC_SDCTL_WPEN; + }else{ + EXMC_SDCTL(exmc_sdram_device) &= ~((uint32_t)EXMC_SDCTL_WPEN); + } + +} + +/*! + \brief get the status of SDRAM device0 or device1 + \param[in] exmc_sdram_device: specifie the SDRAM device + only one parameter can be selected which is shown as below: + \arg EXMC_SDRAM_DEVICEx(x=0,1) + \param[out] none + \retval the status of SDRAM device +*/ +uint32_t exmc_sdram_bankstatus_get(uint32_t exmc_sdram_device) +{ + uint32_t sdstat = 0U; + + if(EXMC_SDRAM_DEVICE0 == exmc_sdram_device){ + sdstat = ((uint32_t)(EXMC_SDSTAT & EXMC_SDSDAT_STA0) >> SDSTAT_STA0_OFFSET); + }else{ + sdstat = ((uint32_t)(EXMC_SDSTAT & EXMC_SDSDAT_STA1) >> SDSTAT_STA1_OFFSET); + } + + return sdstat; } /*! \brief set the read command \param[in] read_command_mode: configure SPI PSRAM read command mode + only one parameter can be selected which is shown as below: \arg EXMC_SQPIPSRAM_READ_MODE_DISABLE: not SPI mode \arg EXMC_SQPIPSRAM_READ_MODE_SPI: SPI mode \arg EXMC_SQPIPSRAM_READ_MODE_SQPI: SQPI mode @@ -843,10 +928,10 @@ void exmc_sqpipsram_parameter_init(exmc_sqpipsram_parameter_struct* exmc_sqpipsr \param[out] none \retval none */ -void exmc_sqpipsram_read_command_set(uint32_t read_command_mode,uint32_t read_wait_cycle,uint32_t read_command_code) +void exmc_sqpipsram_read_command_set(uint32_t read_command_mode,uint32_t read_wait_cycle, uint32_t read_command_code) { uint32_t srcmd; - + srcmd = (uint32_t) read_command_mode | ((read_wait_cycle << SRCMD_RWAITCYCLE_OFFSET) & EXMC_SRCMD_RWAITCYCLE) | ((read_command_code & EXMC_SRCMD_RCMD)); @@ -856,6 +941,7 @@ void exmc_sqpipsram_read_command_set(uint32_t read_command_mode,uint32_t read_wa /*! \brief set the write command \param[in] write_command_mode: configure SPI PSRAM write command mode + only one parameter can be selected which is shown as below: \arg EXMC_SQPIPSRAM_WRITE_MODE_DISABLE: not SPI mode \arg EXMC_SQPIPSRAM_WRITE_MODE_SPI: SPI mode \arg EXMC_SQPIPSRAM_WRITE_MODE_SQPI: SQPI mode @@ -865,10 +951,10 @@ void exmc_sqpipsram_read_command_set(uint32_t read_command_mode,uint32_t read_wa \param[out] none \retval none */ -void exmc_sqpipsram_write_command_set(uint32_t write_command_mode,uint32_t write_wait_cycle,uint32_t write_command_code) +void exmc_sqpipsram_write_command_set(uint32_t write_command_mode,uint32_t write_wait_cycle, uint32_t write_command_code) { uint32_t swcmd; - + swcmd = (uint32_t) write_command_mode | ((write_wait_cycle << SWCMD_WWAITCYCLE_OFFSET) & EXMC_SWCMD_WWAITCYCLE) | ((write_command_code & EXMC_SWCMD_WCMD)); @@ -922,6 +1008,7 @@ uint32_t exmc_sqpipsram_high_id_get(void) /*! \brief get the bit value of EXMC send write command bit or read ID command \param[in] send_command_flag: the send command flag + only one parameter can be selected which is shown as below: \arg EXMC_SEND_COMMAND_FLAG_RDID: EXMC_SRCMD_RDID flag bit \arg EXMC_SEND_COMMAND_FLAG_SC: EXMC_SWCMD_SC flag bit \param[out] none @@ -930,14 +1017,14 @@ uint32_t exmc_sqpipsram_high_id_get(void) FlagStatus exmc_sqpipsram_send_command_state_get(uint32_t send_command_flag) { uint32_t flag = 0x00000000U; - + if(EXMC_SEND_COMMAND_FLAG_RDID == send_command_flag){ flag = EXMC_SRCMD; }else if(EXMC_SEND_COMMAND_FLAG_SC == send_command_flag){ flag = EXMC_SWCMD; }else{ } - + if (flag & send_command_flag){ /* flag is set */ return SET; @@ -948,14 +1035,74 @@ FlagStatus exmc_sqpipsram_send_command_state_get(uint32_t send_command_flag) } /*! - \brief check EXMC flag is set or not + \brief enable EXMC interrupt + \param[in] exmc_bank: specifies the NAND bank,PC card bank or SDRAM device + only one parameter can be selected which is shown as below: + \arg EXMC_BANK1_NAND: the NAND bank1 + \arg EXMC_BANK2_NAND: the NAND bank2 + \arg EXMC_BANK3_PCCARD: the PC card bank + \arg EXMC_SDRAM_DEVICE0: the SDRAM device0 + \arg EXMC_SDRAM_DEVICE1: the SDRAM device1 + \param[in] interrupt: specify get which interrupt flag + only one parameter can be selected which is shown as below: + \arg EXMC_NAND_PCCARD_INT_FLAG_RISE: rising edge interrupt and flag + \arg EXMC_NAND_PCCARD_INT_FLAG_LEVEL: high-level interrupt and flag + \arg EXMC_NAND_PCCARD_INT_FLAG_FALL: falling edge interrupt and flag + \arg EXMC_SDRAM_INT_FLAG_REFRESH: refresh error interrupt and flag + \param[out] none + \retval none +*/ +void exmc_interrupt_enable(uint32_t exmc_bank, uint32_t interrupt) +{ + if((EXMC_BANK1_NAND == exmc_bank) || (EXMC_BANK2_NAND == exmc_bank) || (EXMC_BANK3_PCCARD == exmc_bank)){ + /* NAND bank1,bank2 or PC card bank3 */ + EXMC_NPINTEN(exmc_bank) |= interrupt; + }else{ + /* SDRAM device0 or device1 */ + EXMC_SDARI |= EXMC_SDARI_REIE; + } +} + +/*! + \brief disable EXMC interrupt + \param[in] exmc_bank: specifies the NAND bank , PC card bank or SDRAM device + only one parameter can be selected which is shown as below: + \arg EXMC_BANK1_NAND: the NAND bank1 + \arg EXMC_BANK2_NAND: the NAND bank2 + \arg EXMC_BANK3_PCCARD: the PC card bank + \arg EXMC_SDRAM_DEVICE0: the SDRAM device0 + \arg EXMC_SDRAM_DEVICE1: the SDRAM device1 + \param[in] interrupt: specify get which interrupt flag + only one parameter can be selected which is shown as below: + \arg EXMC_NAND_PCCARD_INT_FLAG_RISE: rising edge interrupt and flag + \arg EXMC_NAND_PCCARD_INT_FLAG_LEVEL: high-level interrupt and flag + \arg EXMC_NAND_PCCARD_INT_FLAG_FALL: falling edge interrupt and flag + \arg EXMC_SDRAM_INT_FLAG_REFRESH: refresh error interrupt and flag + \param[out] none + \retval none +*/ +void exmc_interrupt_disable(uint32_t exmc_bank, uint32_t interrupt) +{ + if((EXMC_BANK1_NAND == exmc_bank) || (EXMC_BANK2_NAND == exmc_bank) || (EXMC_BANK3_PCCARD == exmc_bank)){ + /* NAND bank1,bank2 or PC card bank3 */ + EXMC_NPINTEN(exmc_bank) &= ~interrupt; + }else{ + /* SDRAM device0 or device1 */ + EXMC_SDARI &= ~EXMC_SDARI_REIE; + } +} + +/*! + \brief get EXMC flag status \param[in] exmc_bank: specifies the NAND bank , PC card bank or SDRAM device + only one parameter can be selected which is shown as below: \arg EXMC_BANK1_NAND: the NAND bank1 \arg EXMC_BANK2_NAND: the NAND bank2 \arg EXMC_BANK3_PCCARD: the PC Card bank \arg EXMC_SDRAM_DEVICE0: the SDRAM device0 \arg EXMC_SDRAM_DEVICE1: the SDRAM device1 - \param[in] flag: specify get which flag + \param[in] flag: EXMC status and flag + only one parameter can be selected which is shown as below: \arg EXMC_NAND_PCCARD_FLAG_RISE: interrupt rising edge status \arg EXMC_NAND_PCCARD_FLAG_LEVEL: interrupt high-level status \arg EXMC_NAND_PCCARD_FLAG_FALL: interrupt falling edge status @@ -976,7 +1123,7 @@ FlagStatus exmc_flag_get(uint32_t exmc_bank,uint32_t flag) /* SDRAM device0 or device1 */ status = EXMC_SDSTAT; } - + if ((status & flag) != (uint32_t)flag ){ /* flag is reset */ return RESET; @@ -987,14 +1134,16 @@ FlagStatus exmc_flag_get(uint32_t exmc_bank,uint32_t flag) } /*! - \brief clear EXMC a channel flag + \brief clear EXMC flag status \param[in] exmc_bank: specifie the NAND bank , PCCARD bank or SDRAM device + only one parameter can be selected which is shown as below: \arg EXMC_BANK1_NAND: the NAND bank1 \arg EXMC_BANK2_NAND: the NAND bank2 \arg EXMC_BANK3_PCCARD: the PC card bank \arg EXMC_SDRAM_DEVICE0: the SDRAM device0 \arg EXMC_SDRAM_DEVICE1: the SDRAM device1 - \param[in] flag: specify get which flag + \param[in] flag: EXMC status and flag + only one parameter can be selected which is shown as below: \arg EXMC_NAND_PCCARD_FLAG_RISE: interrupt rising edge status \arg EXMC_NAND_PCCARD_FLAG_LEVEL: interrupt high-level status \arg EXMC_NAND_PCCARD_FLAG_FALL: interrupt falling edge status @@ -1004,7 +1153,7 @@ FlagStatus exmc_flag_get(uint32_t exmc_bank,uint32_t flag) \param[out] none \retval none */ -void exmc_flag_clear(uint32_t exmc_bank,uint32_t flag) +void exmc_flag_clear(uint32_t exmc_bank, uint32_t flag) { if((EXMC_BANK1_NAND == exmc_bank) || (EXMC_BANK2_NAND == exmc_bank) || (EXMC_BANK3_PCCARD == exmc_bank)){ /* NAND bank1,bank2 or PC card bank3 */ @@ -1012,40 +1161,42 @@ void exmc_flag_clear(uint32_t exmc_bank,uint32_t flag) }else{ /* SDRAM device0 or device1 */ EXMC_SDSTAT &= ~flag; - } + } } /*! - \brief check EXMC interrupt flag is set or not + \brief get EXMC interrupt flag \param[in] exmc_bank: specifies the NAND bank , PC card bank or SDRAM device + only one parameter can be selected which is shown as below: \arg EXMC_BANK1_NAND: the NAND bank1 \arg EXMC_BANK2_NAND: the NAND bank2 \arg EXMC_BANK3_PCCARD: the PC card bank \arg EXMC_SDRAM_DEVICE0: the SDRAM device0 \arg EXMC_SDRAM_DEVICE1: the SDRAM device1 - \param[in] interrupt_source: specify get which interrupt flag - \arg EXMC_NAND_PCCARD_INT_RISE: interrupt source of rising edge - \arg EXMC_NAND_PCCARD_INT_LEVEL: interrupt source of high-level - \arg EXMC_NAND_PCCARD_INT_FALL: interrupt source of falling edge - \arg EXMC_SDRAM_INT_REFRESH: interrupt source of refresh error + \param[in] interrupt: EXMC interrupt flag + only one parameter can be selected which is shown as below: + \arg EXMC_NAND_PCCARD_INT_FLAG_RISE: rising edge interrupt and flag + \arg EXMC_NAND_PCCARD_INT_FLAG_LEVEL: high-level interrupt and flag + \arg EXMC_NAND_PCCARD_INT_FLAG_FALL: falling edge interrupt and flag + \arg EXMC_SDRAM_INT_FLAG_REFRESH: refresh error interrupt and flag \param[out] none \retval FlagStatus: SET or RESET */ -FlagStatus exmc_interrupt_flag_get(uint32_t exmc_bank,uint32_t interrupt_source) +FlagStatus exmc_interrupt_flag_get(uint32_t exmc_bank, uint32_t interrupt) { uint32_t status = 0x00000000U,interrupt_enable = 0x00000000U,interrupt_state = 0x00000000U; if((EXMC_BANK1_NAND == exmc_bank) || (EXMC_BANK2_NAND == exmc_bank) || (EXMC_BANK3_PCCARD == exmc_bank)){ /* NAND bank1,bank2 or PC card bank3 */ status = EXMC_NPINTEN(exmc_bank); - interrupt_enable = (status & (interrupt_source >> INTEN_INTEN_OFFSET)); + interrupt_state = (status & (interrupt >> INTEN_INTS_OFFSET)); }else{ /* SDRAM device0 or device1 */ status = EXMC_SDARI; - interrupt_enable = (EXMC_SDSTAT & EXMC_SDSDAT_REIF); + interrupt_state = (EXMC_SDSTAT & EXMC_SDSDAT_REIF); } - interrupt_state = (status & interrupt_source); + interrupt_enable = (status & interrupt); if ((interrupt_enable) && (interrupt_state)){ /* interrupt flag is set */ @@ -1057,82 +1208,30 @@ FlagStatus exmc_interrupt_flag_get(uint32_t exmc_bank,uint32_t interrupt_source) } /*! - \brief clear EXMC one channel interrupt flag + \brief clear EXMC interrupt flag \param[in] exmc_bank: specifies the NAND bank , PC card bank or SDRAM device + only one parameter can be selected which is shown as below: \arg EXMC_BANK1_NAND: the NAND bank1 \arg EXMC_BANK2_NAND: the NAND bank2 \arg EXMC_BANK3_PCCARD: the PC card bank \arg EXMC_SDRAM_DEVICE0: the SDRAM device0 \arg EXMC_SDRAM_DEVICE1: the SDRAM device1 - \param[in] interrupt_source: specify get which interrupt flag - \arg EXMC_NAND_PCCARD_INT_RISE: interrupt source of rising edge - \arg EXMC_NAND_PCCARD_INT_LEVEL: interrupt source of high-level - \arg EXMC_NAND_PCCARD_INT_FALL: interrupt source of falling edge - \arg EXMC_SDRAM_INT_REFRESH: interrupt source of refresh error + \param[in] interrupt: EXMC interrupt flag + only one parameter can be selected which is shown as below: + \arg EXMC_NAND_PCCARD_INT_FLAG_RISE: rising edge interrupt and flag + \arg EXMC_NAND_PCCARD_INT_FLAG_LEVEL: high-level interrupt and flag + \arg EXMC_NAND_PCCARD_INT_FLAG_FALL: falling edge interrupt and flag + \arg EXMC_SDRAM_INT_FLAG_REFRESH: refresh error interrupt and flag \param[out] none \retval none */ -void exmc_interrupt_flag_clear(uint32_t exmc_bank,uint32_t interrupt_source) +void exmc_interrupt_flag_clear(uint32_t exmc_bank, uint32_t interrupt) { if((EXMC_BANK1_NAND == exmc_bank) || (EXMC_BANK2_NAND == exmc_bank) || (EXMC_BANK3_PCCARD == exmc_bank)){ /* NAND bank1,bank2 or PC card bank3 */ - EXMC_NPINTEN(exmc_bank) &= ~(interrupt_source >> INTEN_INTEN_OFFSET); + EXMC_NPINTEN(exmc_bank) &= ~(interrupt >> INTEN_INTS_OFFSET); }else{ /* SDRAM device0 or device1 */ EXMC_SDARI |= EXMC_SDARI_REC; } } - -/*! - \brief enable EXMC interrupt - \param[in] exmc_bank: specifies the NAND bank,PC card bank or SDRAM device - \arg EXMC_BANK1_NAND: the NAND bank1 - \arg EXMC_BANK2_NAND: the NAND bank2 - \arg EXMC_BANK3_PCCARD: the PC card bank - \arg EXMC_SDRAM_DEVICE0: the SDRAM device0 - \arg EXMC_SDRAM_DEVICE1: the SDRAM device1 - \param[in] interrupt_source: specify get which interrupt flag - \arg EXMC_NAND_PCCARD_INT_RISE: interrupt source of rising edge - \arg EXMC_NAND_PCCARD_INT_LEVEL: interrupt source of high-level - \arg EXMC_NAND_PCCARD_INT_FALL: interrupt source of falling edge - \arg EXMC_SDRAM_INT_REFRESH: interrupt source of refresh error - \param[out] none - \retval none -*/ -void exmc_interrupt_enable(uint32_t exmc_bank,uint32_t interrupt_source) -{ - if((EXMC_BANK1_NAND == exmc_bank) || (EXMC_BANK2_NAND == exmc_bank) || (EXMC_BANK3_PCCARD == exmc_bank)){ - /* NAND bank1,bank2 or PC card bank3 */ - EXMC_NPINTEN(exmc_bank) |= interrupt_source; - }else{ - /* SDRAM device0 or device1 */ - EXMC_SDARI |= EXMC_SDARI_REIE; - } -} - -/*! - \brief disable EXMC interrupt - \param[in] exmc_bank: specifies the NAND bank , PC card bank or SDRAM device - \arg EXMC_BANK1_NAND: the NAND bank1 - \arg EXMC_BANK2_NAND: the NAND bank2 - \arg EXMC_BANK3_PCCARD: the PC card bank - \arg EXMC_SDRAM_DEVICE0: the SDRAM device0 - \arg EXMC_SDRAM_DEVICE1: the SDRAM device1 - \param[in] interrupt_source: specify get which interrupt flag - \arg EXMC_NAND_PCCARD_INT_RISE: interrupt source of rising edge - \arg EXMC_NAND_PCCARD_INT_LEVEL: interrupt source of high-level - \arg EXMC_NAND_PCCARD_INT_FALL: interrupt source of falling edge - \arg EXMC_SDRAM_INT_REFRESH: interrupt source of refresh error - \param[out] none - \retval none -*/ -void exmc_interrupt_disable(uint32_t exmc_bank,uint32_t interrupt_source) -{ - if((EXMC_BANK1_NAND == exmc_bank) || (EXMC_BANK2_NAND == exmc_bank) || (EXMC_BANK3_PCCARD == exmc_bank)){ - /* NAND bank1,bank2 or PC card bank3 */ - EXMC_NPINTEN(exmc_bank) &= ~interrupt_source; - }else{ - /* SDRAM device0 or device1 */ - EXMC_SDARI &= ~EXMC_SDARI_REIE; - } -} diff --git a/bsp/gd32450z-eval/Libraries/GD32F4xx_standard_peripheral/Source/gd32f4xx_exti.c b/bsp/gd32450z-eval/Libraries/GD32F4xx_standard_peripheral/Source/gd32f4xx_exti.c index 24bffea316..a3eacb0202 100644 --- a/bsp/gd32450z-eval/Libraries/GD32F4xx_standard_peripheral/Source/gd32f4xx_exti.c +++ b/bsp/gd32450z-eval/Libraries/GD32F4xx_standard_peripheral/Source/gd32f4xx_exti.c @@ -1,12 +1,37 @@ /*! - \file gd32f4xx_exti.c - \brief EXTI driver + \file gd32f4xx_exti.c + \brief EXTI driver + + \version 2016-08-15, V1.0.0, firmware for GD32F4xx + \version 2018-12-12, V2.0.1, firmware for GD32F4xx + \version 2020-09-30, V2.1.0, firmware for GD32F4xx */ /* - Copyright (C) 2016 GigaDevice + Copyright (c) 2020, GigaDevice Semiconductor Inc. + + Redistribution and use in source and binary forms, with or without modification, +are permitted provided that the following conditions are met: + + 1. Redistributions of source code must retain the above copyright notice, this + list of conditions and the following disclaimer. + 2. Redistributions in binary form must reproduce the above copyright notice, + this list of conditions and the following disclaimer in the documentation + and/or other materials provided with the distribution. + 3. Neither the name of the copyright holder nor the names of its contributors + may be used to endorse or promote products derived from this software without + specific prior written permission. - 2016-08-15, V1.0.0, firmware for GD32F4xx + THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED +WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. +IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, +INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT +NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR +PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, +WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY +OF SUCH DAMAGE. */ #include "gd32f4xx_exti.h" @@ -41,6 +66,7 @@ void exti_deinit(void) \arg EXTI_TRIG_RISING: rising edge trigger \arg EXTI_TRIG_FALLING: falling trigger \arg EXTI_TRIG_BOTH: rising and falling trigger + \arg EXTI_TRIG_NONE: without rising edge or falling edge trigger \param[out] none \retval none */ @@ -53,7 +79,7 @@ void exti_init(exti_line_enum linex, \ EXTI_EVEN &= ~(uint32_t)linex; EXTI_RTEN &= ~(uint32_t)linex; EXTI_FTEN &= ~(uint32_t)linex; - + /* set the EXTI mode and enable the interrupts or events from EXTI line x */ switch(mode){ case EXTI_INTERRUPT: @@ -65,7 +91,7 @@ void exti_init(exti_line_enum linex, \ default: break; } - + /* set the EXTI trigger type */ switch(trig_type){ case EXTI_TRIG_RISING: @@ -80,6 +106,7 @@ void exti_init(exti_line_enum linex, \ EXTI_RTEN |= (uint32_t)linex; EXTI_FTEN |= (uint32_t)linex; break; + case EXTI_TRIG_NONE: default: break; } @@ -99,29 +126,29 @@ void exti_interrupt_enable(exti_line_enum linex) } /*! - \brief enable the events from EXTI line x + \brief disable the interrupt from EXTI line x \param[in] linex: EXTI line number, refer to exti_line_enum only one parameter can be selected which is shown as below: \arg EXTI_x (x=0..22): EXTI line x \param[out] none \retval none */ -void exti_event_enable(exti_line_enum linex) +void exti_interrupt_disable(exti_line_enum linex) { - EXTI_EVEN |= (uint32_t)linex; + EXTI_INTEN &= ~(uint32_t)linex; } /*! - \brief disable the interrupt from EXTI line x + \brief enable the events from EXTI line x \param[in] linex: EXTI line number, refer to exti_line_enum only one parameter can be selected which is shown as below: \arg EXTI_x (x=0..22): EXTI line x \param[out] none \retval none */ -void exti_interrupt_disable(exti_line_enum linex) +void exti_event_enable(exti_line_enum linex) { - EXTI_INTEN &= ~(uint32_t)linex; + EXTI_EVEN |= (uint32_t)linex; } /*! @@ -138,51 +165,42 @@ void exti_event_disable(exti_line_enum linex) } /*! - \brief get EXTI lines flag + \brief enable EXTI software interrupt event \param[in] linex: EXTI line number, refer to exti_line_enum only one parameter can be selected which is shown as below: \arg EXTI_x (x=0..22): EXTI line x \param[out] none - \retval FlagStatus: status of flag (RESET or SET) + \retval none */ -FlagStatus exti_flag_get(exti_line_enum linex) +void exti_software_interrupt_enable(exti_line_enum linex) { - if(RESET != (EXTI_PD & (uint32_t)linex)){ - return SET; - }else{ - return RESET; - } + EXTI_SWIEV |= (uint32_t)linex; } /*! - \brief clear EXTI lines pending flag + \brief disable EXTI software interrupt event \param[in] linex: EXTI line number, refer to exti_line_enum only one parameter can be selected which is shown as below: \arg EXTI_x (x=0..22): EXTI line x \param[out] none \retval none */ -void exti_flag_clear(exti_line_enum linex) +void exti_software_interrupt_disable(exti_line_enum linex) { - EXTI_PD = (uint32_t)linex; + EXTI_SWIEV &= ~(uint32_t)linex; } /*! - \brief get EXTI lines flag when the interrupt flag is set + \brief get EXTI lines flag \param[in] linex: EXTI line number, refer to exti_line_enum only one parameter can be selected which is shown as below: \arg EXTI_x (x=0..22): EXTI line x \param[out] none \retval FlagStatus: status of flag (RESET or SET) */ -FlagStatus exti_interrupt_flag_get(exti_line_enum linex) +FlagStatus exti_flag_get(exti_line_enum linex) { - uint32_t flag_left, flag_right; - - flag_left = EXTI_PD & (uint32_t)linex; - flag_right = EXTI_INTEN & (uint32_t)linex; - - if((RESET != flag_left) && (RESET != flag_right)){ + if(RESET != (EXTI_PD & (uint32_t)linex)){ return SET; }else{ return RESET; @@ -197,33 +215,43 @@ FlagStatus exti_interrupt_flag_get(exti_line_enum linex) \param[out] none \retval none */ -void exti_interrupt_flag_clear(exti_line_enum linex) +void exti_flag_clear(exti_line_enum linex) { EXTI_PD = (uint32_t)linex; } /*! - \brief enable EXTI software interrupt event + \brief get EXTI lines flag when the interrupt flag is set \param[in] linex: EXTI line number, refer to exti_line_enum only one parameter can be selected which is shown as below: \arg EXTI_x (x=0..22): EXTI line x \param[out] none - \retval none + \retval FlagStatus: status of flag (RESET or SET) */ -void exti_software_interrupt_enable(exti_line_enum linex) +FlagStatus exti_interrupt_flag_get(exti_line_enum linex) { - EXTI_SWIEV |= (uint32_t)linex; + uint32_t flag_left, flag_right; + + flag_left = EXTI_PD & (uint32_t)linex; + flag_right = EXTI_INTEN & (uint32_t)linex; + + if((RESET != flag_left) && (RESET != flag_right)){ + return SET; + }else{ + return RESET; + } } /*! - \brief disable EXTI software interrupt event + \brief clear EXTI lines pending flag \param[in] linex: EXTI line number, refer to exti_line_enum only one parameter can be selected which is shown as below: \arg EXTI_x (x=0..22): EXTI line x \param[out] none \retval none */ -void exti_software_interrupt_disable(exti_line_enum linex) +void exti_interrupt_flag_clear(exti_line_enum linex) { - EXTI_SWIEV &= ~(uint32_t)linex; + EXTI_PD = (uint32_t)linex; } + diff --git a/bsp/gd32450z-eval/Libraries/GD32F4xx_standard_peripheral/Source/gd32f4xx_fmc.c b/bsp/gd32450z-eval/Libraries/GD32F4xx_standard_peripheral/Source/gd32f4xx_fmc.c index 2bfc2f1caa..4e2b0db9a5 100644 --- a/bsp/gd32450z-eval/Libraries/GD32F4xx_standard_peripheral/Source/gd32f4xx_fmc.c +++ b/bsp/gd32450z-eval/Libraries/GD32F4xx_standard_peripheral/Source/gd32f4xx_fmc.c @@ -1,19 +1,46 @@ /*! - \file gd32f4xx_fmc.c - \brief FMC driver + \file gd32f4xx_fmc.c + \brief FMC driver + + \version 2016-08-15, V1.0.0, firmware for GD32F4xx + \version 2018-12-12, V2.0.0, firmware for GD32F4xx + \version 2020-09-30, V2.1.0, firmware for GD32F4xx */ /* - Copyright (C) 2016 GigaDevice + Copyright (c) 2020, GigaDevice Semiconductor Inc. + + Redistribution and use in source and binary forms, with or without modification, +are permitted provided that the following conditions are met: - 2016-08-15, V1.0.0, firmware for GD32F4xx + 1. Redistributions of source code must retain the above copyright notice, this + list of conditions and the following disclaimer. + 2. Redistributions in binary form must reproduce the above copyright notice, + this list of conditions and the following disclaimer in the documentation + and/or other materials provided with the distribution. + 3. Neither the name of the copyright holder nor the names of its contributors + may be used to endorse or promote products derived from this software without + specific prior written permission. + + THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED +WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. +IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, +INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT +NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR +PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, +WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY +OF SUCH DAMAGE. */ + #include "gd32f4xx_fmc.h" /*! \brief set the wait state counter value - \param[in] wscnt��wait state counter value + \param[in] wscnt: wait state counter value + only one parameter can be selected which is shown as below: \arg WS_WSCNT_0: FMC 0 wait \arg WS_WSCNT_1: FMC 1 wait \arg WS_WSCNT_2: FMC 2 wait @@ -36,7 +63,7 @@ void fmc_wscnt_set(uint32_t wscnt) { uint32_t reg; - + reg = FMC_WS; /* set the wait state counter value */ reg &= ~FMC_WC_WSCNT; @@ -73,58 +100,64 @@ void fmc_lock(void) /*! \brief erase sector \param[in] fmc_sector: select the sector to erase - \arg CTL_SECTOR_NUMBER_0: sector 0 - \arg CTL_SECTOR_NUMBER_1: sector 1 - \arg CTL_SECTOR_NUMBER_2: sector 2 - \arg CTL_SECTOR_NUMBER_3: sector 3 - \arg CTL_SECTOR_NUMBER_4: sector 4 - \arg CTL_SECTOR_NUMBER_5: sector 5 - \arg CTL_SECTOR_NUMBER_6: sector 6 - \arg CTL_SECTOR_NUMBER_7: sector 7 - \arg CTL_SECTOR_NUMBER_8: sector 8 - \arg CTL_SECTOR_NUMBER_9: sector 9 - \arg CTL_SECTOR_NUMBER_10: sector 10 - \arg CTL_SECTOR_NUMBER_11: sector 11 - \arg CTL_SECTOR_NUMBER_12: sector 12 - \arg CTL_SECTOR_NUMBER_13: sector 13 - \arg CTL_SECTOR_NUMBER_14: sector 14 - \arg CTL_SECTOR_NUMBER_15: sector 15 - \arg CTL_SECTOR_NUMBER_16: sector 16 - \arg CTL_SECTOR_NUMBER_17: sector 17 - \arg CTL_SECTOR_NUMBER_18: sector 18 - \arg CTL_SECTOR_NUMBER_19: sector 19 - \arg CTL_SECTOR_NUMBER_20: sector 20 - \arg CTL_SECTOR_NUMBER_21: sector 21 - \arg CTL_SECTOR_NUMBER_22: sector 22 - \arg CTL_SECTOR_NUMBER_23: sector 23 - \arg CTL_SECTOR_NUMBER_24: sector 24 - \arg CTL_SECTOR_NUMBER_25: sector 25 - \arg CTL_SECTOR_NUMBER_26: sector 26 - \arg CTL_SECTOR_NUMBER_27: sector 27 - \arg CTL_SECTOR_NUMBER_28: sector 28 - \arg CTL_SECTOR_NUMBER_29: sector 29 - \arg CTL_SECTOR_NUMBER_30: sector 30 + only one parameter can be selected which is shown as below: + \arg CTL_SECTOR_NUMBER_0: sector 0 + \arg CTL_SECTOR_NUMBER_1: sector 1 + \arg CTL_SECTOR_NUMBER_2: sector 2 + \arg CTL_SECTOR_NUMBER_3: sector 3 + \arg CTL_SECTOR_NUMBER_4: sector 4 + \arg CTL_SECTOR_NUMBER_5: sector 5 + \arg CTL_SECTOR_NUMBER_6: sector 6 + \arg CTL_SECTOR_NUMBER_7: sector 7 + \arg CTL_SECTOR_NUMBER_8: sector 8 + \arg CTL_SECTOR_NUMBER_9: sector 9 + \arg CTL_SECTOR_NUMBER_10: sector 10 + \arg CTL_SECTOR_NUMBER_11: sector 11 + \arg CTL_SECTOR_NUMBER_12: sector 12 + \arg CTL_SECTOR_NUMBER_13: sector 13 + \arg CTL_SECTOR_NUMBER_14: sector 14 + \arg CTL_SECTOR_NUMBER_15: sector 15 + \arg CTL_SECTOR_NUMBER_16: sector 16 + \arg CTL_SECTOR_NUMBER_17: sector 17 + \arg CTL_SECTOR_NUMBER_18: sector 18 + \arg CTL_SECTOR_NUMBER_19: sector 19 + \arg CTL_SECTOR_NUMBER_20: sector 20 + \arg CTL_SECTOR_NUMBER_21: sector 21 + \arg CTL_SECTOR_NUMBER_22: sector 22 + \arg CTL_SECTOR_NUMBER_23: sector 23 + \arg CTL_SECTOR_NUMBER_24: sector 24 + \arg CTL_SECTOR_NUMBER_25: sector 25 + \arg CTL_SECTOR_NUMBER_26: sector 26 + \arg CTL_SECTOR_NUMBER_27: sector 27 \param[out] none - \retval fmc_state_enum + \retval state of FMC + \arg FMC_READY: the operation has been completed + \arg FMC_BUSY: the operation is in progress + \arg FMC_RDDERR: read D-bus protection error + \arg FMC_PGSERR: program sequence error + \arg FMC_PGMERR: program size not match error + \arg FMC_WPERR: erase/program protection error + \arg FMC_OPERR: operation error + \arg FMC_PGERR: program error */ fmc_state_enum fmc_sector_erase(uint32_t fmc_sector) { fmc_state_enum fmc_state = FMC_READY; /* wait for the FMC ready */ - fmc_state = fmc_ready_wait(FMC_TIMEOUT_COUNT); - - if(FMC_READY == fmc_state){ + fmc_state = fmc_ready_wait(); + + if(FMC_READY == fmc_state){ /* start sector erase */ FMC_CTL &= ~FMC_CTL_SN; FMC_CTL |= (FMC_CTL_SER | fmc_sector); FMC_CTL |= FMC_CTL_START; /* wait for the FMC ready */ - fmc_state = fmc_ready_wait(FMC_TIMEOUT_COUNT); - + fmc_state = fmc_ready_wait(); + /* reset the SER bit */ FMC_CTL &= (~FMC_CTL_SER); - FMC_CTL &= ~FMC_CTL_SN; + FMC_CTL &= ~FMC_CTL_SN; } /* return the FMC state */ @@ -135,21 +168,29 @@ fmc_state_enum fmc_sector_erase(uint32_t fmc_sector) \brief erase whole chip \param[in] none \param[out] none - \retval fmc_state_enum + \retval state of FMC + \arg FMC_READY: the operation has been completed + \arg FMC_BUSY: the operation is in progress + \arg FMC_RDDERR: read D-bus protection error + \arg FMC_PGSERR: program sequence error + \arg FMC_PGMERR: program size not match error + \arg FMC_WPERR: erase/program protection error + \arg FMC_OPERR: operation error + \arg FMC_PGERR: program error */ fmc_state_enum fmc_mass_erase(void) { fmc_state_enum fmc_state = FMC_READY; /* wait for the FMC ready */ - fmc_state = fmc_ready_wait(FMC_TIMEOUT_COUNT); + fmc_state = fmc_ready_wait(); - if(FMC_READY == fmc_state){ - /* start whole chip erase */ + if(FMC_READY == fmc_state){ + /* start whole chip erase */ FMC_CTL |= (FMC_CTL_MER0 | FMC_CTL_MER1); FMC_CTL |= FMC_CTL_START; - + /* wait for the FMC ready */ - fmc_state = fmc_ready_wait(FMC_TIMEOUT_COUNT); + fmc_state = fmc_ready_wait(); /* reset the MER bits */ FMC_CTL &= ~(FMC_CTL_MER0 | FMC_CTL_MER1); @@ -163,21 +204,29 @@ fmc_state_enum fmc_mass_erase(void) \brief erase all FMC sectors in bank0 \param[in] none \param[out] none - \retval fmc_state_enum + \retval state of FMC + \arg FMC_READY: the operation has been completed + \arg FMC_BUSY: the operation is in progress + \arg FMC_RDDERR: read D-bus protection error + \arg FMC_PGSERR: program sequence error + \arg FMC_PGMERR: program size not match error + \arg FMC_WPERR: erase/program protection error + \arg FMC_OPERR: operation error + \arg FMC_PGERR: program error */ fmc_state_enum fmc_bank0_erase(void) { fmc_state_enum fmc_state = FMC_READY; /* wait for the FMC ready */ - fmc_state = fmc_ready_wait(FMC_TIMEOUT_COUNT); + fmc_state = fmc_ready_wait(); if(FMC_READY == fmc_state){ /* start FMC bank0 erase */ FMC_CTL |= FMC_CTL_MER0; FMC_CTL |= FMC_CTL_START; - + /* wait for the FMC ready */ - fmc_state = fmc_ready_wait(FMC_TIMEOUT_COUNT); + fmc_state = fmc_ready_wait(); /* reset the MER0 bit */ FMC_CTL &= (~FMC_CTL_MER0); @@ -191,21 +240,29 @@ fmc_state_enum fmc_bank0_erase(void) \brief erase all FMC sectors in bank1 \param[in] none \param[out] none - \retval fmc_state_enum + \retval state of FMC + \arg FMC_READY: the operation has been completed + \arg FMC_BUSY: the operation is in progress + \arg FMC_RDDERR: read D-bus protection error + \arg FMC_PGSERR: program sequence error + \arg FMC_PGMERR: program size not match error + \arg FMC_WPERR: erase/program protection error + \arg FMC_OPERR: operation error + \arg FMC_PGERR: program error */ fmc_state_enum fmc_bank1_erase(void) { fmc_state_enum fmc_state = FMC_READY; /* wait for the FMC ready */ - fmc_state = fmc_ready_wait(FMC_TIMEOUT_COUNT); - + fmc_state = fmc_ready_wait(); + if(FMC_READY == fmc_state){ /* start FMC bank1 erase */ FMC_CTL |= FMC_CTL_MER1; FMC_CTL |= FMC_CTL_START; - + /* wait for the FMC ready */ - fmc_state = fmc_ready_wait(FMC_TIMEOUT_COUNT); + fmc_state = fmc_ready_wait(); /* reset the MER1 bit */ FMC_CTL &= (~FMC_CTL_MER1); @@ -218,31 +275,39 @@ fmc_state_enum fmc_bank1_erase(void) /*! \brief program a word at the corresponding address \param[in] address: address to program - \param[in] data: word to program + \param[in] data: word to program(0x00000000 - 0xFFFFFFFF) \param[out] none - \retval fmc_state_enum + \retval state of FMC + \arg FMC_READY: the operation has been completed + \arg FMC_BUSY: the operation is in progress + \arg FMC_RDDERR: read D-bus protection error + \arg FMC_PGSERR: program sequence error + \arg FMC_PGMERR: program size not match error + \arg FMC_WPERR: erase/program protection error + \arg FMC_OPERR: operation error + \arg FMC_PGERR: program error */ fmc_state_enum fmc_word_program(uint32_t address, uint32_t data) { fmc_state_enum fmc_state = FMC_READY; /* wait for the FMC ready */ - fmc_state = fmc_ready_wait(FMC_TIMEOUT_COUNT); - + fmc_state = fmc_ready_wait(); + if(FMC_READY == fmc_state){ /* set the PG bit to start program */ FMC_CTL &= ~FMC_CTL_PSZ; FMC_CTL |= CTL_PSZ_WORD; - FMC_CTL |= FMC_CTL_PG; - + FMC_CTL |= FMC_CTL_PG; + REG32(address) = data; /* wait for the FMC ready */ - fmc_state = fmc_ready_wait(FMC_TIMEOUT_COUNT); - + fmc_state = fmc_ready_wait(); + /* reset the PG bit */ - FMC_CTL &= ~FMC_CTL_PG; - } - + FMC_CTL &= ~FMC_CTL_PG; + } + /* return the FMC state */ return fmc_state; } @@ -250,31 +315,39 @@ fmc_state_enum fmc_word_program(uint32_t address, uint32_t data) /*! \brief program a half word at the corresponding address \param[in] address: address to program - \param[in] data: halfword to program + \param[in] data: halfword to program(0x0000 - 0xFFFF) \param[out] none - \retval fmc_state_enum + \retval state of FMC + \arg FMC_READY: the operation has been completed + \arg FMC_BUSY: the operation is in progress + \arg FMC_RDDERR: read D-bus protection error + \arg FMC_PGSERR: program sequence error + \arg FMC_PGMERR: program size not match error + \arg FMC_WPERR: erase/program protection error + \arg FMC_OPERR: operation error + \arg FMC_PGERR: program error */ fmc_state_enum fmc_halfword_program(uint32_t address, uint16_t data) { fmc_state_enum fmc_state = FMC_READY; /* wait for the FMC ready */ - fmc_state = fmc_ready_wait(FMC_TIMEOUT_COUNT); - - if(FMC_READY == fmc_state){ + fmc_state = fmc_ready_wait(); + + if(FMC_READY == fmc_state){ /* set the PG bit to start program */ FMC_CTL &= ~FMC_CTL_PSZ; FMC_CTL |= CTL_PSZ_HALF_WORD; - FMC_CTL |= FMC_CTL_PG; - + FMC_CTL |= FMC_CTL_PG; + REG16(address) = data; /* wait for the FMC ready */ - fmc_state = fmc_ready_wait(FMC_TIMEOUT_COUNT); - + fmc_state = fmc_ready_wait(); + /* reset the PG bit */ - FMC_CTL &= ~FMC_CTL_PG; - } - + FMC_CTL &= ~FMC_CTL_PG; + } + /* return the FMC state */ return fmc_state; } @@ -282,31 +355,39 @@ fmc_state_enum fmc_halfword_program(uint32_t address, uint16_t data) /*! \brief program a byte at the corresponding address \param[in] address: address to program - \param[in] data: byte to program + \param[in] data: byte to program(0x00 - 0xFF) \param[out] none - \retval fmc_state_enum + \retval state of FMC + \arg FMC_READY: the operation has been completed + \arg FMC_BUSY: the operation is in progress + \arg FMC_RDDERR: read D-bus protection error + \arg FMC_PGSERR: program sequence error + \arg FMC_PGMERR: program size not match error + \arg FMC_WPERR: erase/program protection error + \arg FMC_OPERR: operation error + \arg FMC_PGERR: program error */ fmc_state_enum fmc_byte_program(uint32_t address, uint8_t data) { fmc_state_enum fmc_state = FMC_READY; /* wait for the FMC ready */ - fmc_state = fmc_ready_wait(FMC_TIMEOUT_COUNT); - + fmc_state = fmc_ready_wait(); + if(FMC_READY == fmc_state){ /* set the PG bit to start program */ FMC_CTL &= ~FMC_CTL_PSZ; FMC_CTL |= CTL_PSZ_BYTE; FMC_CTL |= FMC_CTL_PG; - + REG8(address) = data; /* wait for the FMC ready */ - fmc_state = fmc_ready_wait(FMC_TIMEOUT_COUNT); - + fmc_state = fmc_ready_wait(); + /* reset the PG bit */ - FMC_CTL &= ~FMC_CTL_PG; - } - + FMC_CTL &= ~FMC_CTL_PG; + } + /* return the FMC state */ return fmc_state; } @@ -335,7 +416,7 @@ void ob_unlock(void) void ob_lock(void) { /* reset the OB_LK bit */ - FMC_OBCTL0 &= ~FMC_OBCTL0_OB_LK; + FMC_OBCTL0 |= FMC_OBCTL0_OB_LK; } /*! @@ -346,178 +427,183 @@ void ob_lock(void) */ void ob_start(void) { + fmc_state_enum fmc_state = FMC_READY; /* set the OB_START bit in OBCTL0 register */ FMC_OBCTL0 |= FMC_OBCTL0_OB_START; + fmc_state = fmc_ready_wait(); + if(FMC_READY != fmc_state){ + while(1){ + } + } } /*! - \brief enable write protection - \param[in] ob_wp: specify sector to be write protected - \arg OB_WPx(x=0..11): write protect specify sector - \arg OB_WP_ALL: write protect all sector + \brief erase option byte + \param[in] none \param[out] none \retval none */ -void ob_write_protection0_enable(uint32_t ob_wp) +void ob_erase(void) { + uint32_t reg, reg1; fmc_state_enum fmc_state = FMC_READY; /* wait for the FMC ready */ - fmc_state = fmc_ready_wait(FMC_TIMEOUT_COUNT); + fmc_state = fmc_ready_wait(); if(FMC_READY == fmc_state){ - FMC_OBCTL0 &= (~((uint32_t)ob_wp << 16)); - } -} + reg = FMC_OBCTL0; + reg1 = FMC_OBCTL1; -/*! - \brief disable write protection - \param[in] ob_wp: specify sector to be write protected - \arg OB_WPx(x=0..11): write protect specify sector - \arg OB_WP_ALL: write protect all sector - \param[out] none - \retval none -*/ -void ob_write_protection0_disable(uint32_t ob_wp) -{ - fmc_state_enum fmc_state = FMC_READY; - /* wait for the FMC ready */ - fmc_state = fmc_ready_wait(FMC_TIMEOUT_COUNT); + /* reset the OB_FWDGT, OB_DEEPSLEEP and OB_STDBY, set according to ob_fwdgt ,ob_deepsleep and ob_stdby */ + reg |= (FMC_OBCTL0_NWDG_HW | FMC_OBCTL0_NRST_DPSLP | FMC_OBCTL0_NRST_STDBY); + /* reset the BOR level */ + reg |= FMC_OBCTL0_BOR_TH; + /* reset option byte boot bank value */ + reg &= ~FMC_OBCTL0_BB; + /* reset option byte dbs value */ + reg &= ~FMC_OBCTL0_DBS; - if(FMC_READY == fmc_state){ - FMC_OBCTL0 |= ((uint32_t)ob_wp << 16); + /* reset drp and wp value */ + reg |= FMC_OBCTL0_WP0; + reg &= (~FMC_OBCTL0_DRP); + FMC_OBCTL0 = reg; + + reg1 |= FMC_OBCTL1_WP1; + FMC_OBCTL1 = reg1; + + FMC_OBCTL0 = reg; } } /*! \brief enable write protection \param[in] ob_wp: specify sector to be write protected - \arg OB_WPx(x=12..30): write protect specify sector - \arg OB_WP_ALL: write protect all sector + one or more parameters can be selected which are shown as below: + \arg OB_WP_x(x=0..22):sector x(x = 0,1,2...22) + \arg OB_WP_23_27: sector23~27 + \arg OB_WP_ALL: all sector \param[out] none \retval none */ -void ob_write_protection1_enable(uint32_t ob_wp) +void ob_write_protection_enable(uint32_t ob_wp) { + uint32_t reg0 = FMC_OBCTL0; + uint32_t reg1 = FMC_OBCTL1; fmc_state_enum fmc_state = FMC_READY; + if(RESET != (FMC_OBCTL0 & FMC_OBCTL0_DRP)){ + while(1){ + } + } /* wait for the FMC ready */ - fmc_state = fmc_ready_wait(FMC_TIMEOUT_COUNT); + fmc_state = fmc_ready_wait(); if(FMC_READY == fmc_state){ - FMC_OBCTL1 &= (~((uint32_t)ob_wp << 16)); + reg0 &= (~((uint32_t)ob_wp << 16)); + reg1 &= (~(ob_wp & 0xFFFF0000U)); + FMC_OBCTL0 = reg0; + FMC_OBCTL1 = reg1; } } /*! \brief disable write protection \param[in] ob_wp: specify sector to be write protected - \arg OB_WPx(x=12..30): write protect specify sector - \arg OB_WP_ALL: write protect all sector - \param[out] none - \retval none -*/ -void ob_write_protection1_disable(uint32_t ob_wp) -{ - fmc_state_enum fmc_state = FMC_READY; - /* wait for the FMC ready */ - fmc_state = fmc_ready_wait(FMC_TIMEOUT_COUNT); - - if(FMC_READY == fmc_state){ - FMC_OBCTL1 |= ((uint32_t)ob_wp << 16); - } -} -/*! - \brief configure the protection mode - \param[in] ob_drp: configure the protection mode of WPx bits - \arg OB_DRP_DISABLE: the WPx bits used as erase/program protection of each sector - \arg OB_DRP_ENABLE: the WPx bits used as erase/program protection and D-bus read protection of each sector + one or more parameters can be selected which are shown as below: + \arg OB_WP_x(x=0..22):sector x(x = 0,1,2...22) + \arg OB_WP_23_27: sector23~27 + \arg OB_WP_ALL: all sector \param[out] none \retval none */ -void ob_drp_config(uint32_t ob_drp) -{ - FMC_OBCTL0 &= ~FMC_OBCTL0_DRP; - FMC_OBCTL0 |= ob_drp; -} - -/*! - \brief enable erase/program protection and D-bus read protection - \param[in] ob_drp: enable the WPx bits used as erase/program protection and D-bus read protection of each sector - \arg OB_DRPx(x=0..11): erase/program protection and D-bus read protection of specify sector - \arg OB_DRP_ALL: erase/program protection and D-bus read protection of all sector - \param[out] none - \retval none -*/ -void ob_drp0_enable(uint32_t ob_drp) +void ob_write_protection_disable(uint32_t ob_wp) { + uint32_t reg0 = FMC_OBCTL0; + uint32_t reg1 = FMC_OBCTL1; fmc_state_enum fmc_state = FMC_READY; - /* wait for the FMC ready */ - fmc_state = fmc_ready_wait(FMC_TIMEOUT_COUNT); - - if(FMC_READY == fmc_state){ - FMC_OBCTL0 |= ((uint32_t)ob_drp << 16); + if(RESET != (FMC_OBCTL0 & FMC_OBCTL0_DRP)){ + while(1){ + } } -} - -/*! - \brief disable erase/program protection and D-bus read protection - \param[in] ob_drp: disable the WPx bits used as erase/program protection and D-bus read protection of each sector - \arg OB_DRPx(x=0..11): erase/program protection and D-bus read protection of specify sector - \arg OB_DRP_ALL: erase/program protection and D-bus read protection of all sector - \param[out] none - \retval none -*/ -void ob_drp0_disable(uint32_t ob_drp) -{ - fmc_state_enum fmc_state = FMC_READY; /* wait for the FMC ready */ - fmc_state = fmc_ready_wait(FMC_TIMEOUT_COUNT); + fmc_state = fmc_ready_wait(); if(FMC_READY == fmc_state){ - FMC_OBCTL0 &= (~((uint32_t)ob_drp << 16)); + reg0 |= ((uint32_t)ob_wp << 16); + reg1 |= (ob_wp & 0xFFFF0000U); + FMC_OBCTL0 = reg0; + FMC_OBCTL1 = reg1; } } /*! \brief enable erase/program protection and D-bus read protection - \param[in] ob_drp: enable the WPx bits used as erase/program protection and D-bus read protection of each sector - \arg OB_DRPx(x=12..30): erase/program protection and D-bus read protection of specify sector - \arg OB_DRP_ALL: erase/program protection and D-bus read protection of all sector + \param[in] ob_drp: enable the WPx bits used as erase/program protection and D-bus read protection of each sector + one or more parameters can be selected which are shown as below: + \arg OB_DRP_x(x=0..22): sector x(x = 0,1,2...22) + \arg OB_DRP_23_27: sector23~27 + \arg OB_DRP_ALL: all sector \param[out] none \retval none */ -void ob_drp1_enable(uint32_t ob_drp) +void ob_drp_enable(uint32_t ob_drp) { + uint32_t reg0 = FMC_OBCTL0; + uint32_t reg1 = FMC_OBCTL1; fmc_state_enum fmc_state = FMC_READY; + uint32_t drp_state = FMC_OBCTL0 & FMC_OBCTL0_DRP; + uint32_t wp0_state = FMC_OBCTL0 & FMC_OBCTL0_WP0; + uint32_t wp1_state = FMC_OBCTL1 & FMC_OBCTL1_WP1; + /*disable write protection before enable D-bus read protection*/ + if((RESET != drp_state) && ((FMC_OBCTL0_WP0 != wp0_state) && (FMC_OBCTL1_WP1 != wp1_state))){ + while(1){ + } + } /* wait for the FMC ready */ - fmc_state = fmc_ready_wait(FMC_TIMEOUT_COUNT); + fmc_state = fmc_ready_wait(); if(FMC_READY == fmc_state){ - FMC_OBCTL1 |= ((uint32_t)ob_drp << 16); + reg0 &= ~FMC_OBCTL0_WP0; + reg1 &= ~FMC_OBCTL1_WP1; + reg0 |= ((uint32_t)ob_drp << 16); + reg1 |= ((uint32_t)ob_drp & 0xFFFF0000U); + FMC_OBCTL0 = reg0; + FMC_OBCTL1 = reg1; + FMC_OBCTL0 |= FMC_OBCTL0_DRP; } } /*! \brief disable erase/program protection and D-bus read protection \param[in] ob_drp: disable the WPx bits used as erase/program protection and D-bus read protection of each sector - \arg OB_DRPx(x=12..30): erase/program protection and D-bus read protection of specify sector - \arg OB_DRP_ALL: erase/program protection and D-bus read protection of all sector + one or more parameters can be selected which are shown as below: + \arg OB_DRP_x(x=0..22): sector x(x = 0,1,2...22) + \arg OB_DRP_23_27: sector23~27 + \arg OB_DRP_ALL: all sector \param[out] none \retval none */ -void ob_drp1_disable(uint32_t ob_drp) +void ob_drp_disable(uint32_t ob_drp) { + uint32_t reg0 = FMC_OBCTL0; + uint32_t reg1 = FMC_OBCTL1; fmc_state_enum fmc_state = FMC_READY; /* wait for the FMC ready */ - fmc_state = fmc_ready_wait(FMC_TIMEOUT_COUNT); + fmc_state = fmc_ready_wait(); if(FMC_READY == fmc_state){ - FMC_OBCTL1 &= (~((uint32_t)ob_drp << 16)); + reg0 |= FMC_OBCTL0_WP0; + reg0 &= (~FMC_OBCTL0_DRP); + FMC_OBCTL0 = reg0; + + reg1 |= FMC_OBCTL1_WP1; + FMC_OBCTL1 = reg1; } } /*! \brief configure security protection level \param[in] ob_spc: specify security protection level + only one parameter can be selected which is shown as below: \arg FMC_NSPC: no security protection \arg FMC_LSPC: low security protection \arg FMC_HSPC: high security protection @@ -528,29 +614,33 @@ void ob_security_protection_config(uint8_t ob_spc) { fmc_state_enum fmc_state = FMC_READY; /* wait for the FMC ready */ - fmc_state = fmc_ready_wait(FMC_TIMEOUT_COUNT); + fmc_state = fmc_ready_wait(); if(FMC_READY == fmc_state){ uint32_t reg; - + reg = FMC_OBCTL0; /* reset the OBCTL0_SPC, set according to ob_spc */ reg &= ~FMC_OBCTL0_SPC; - FMC_OBCTL0 |= ((uint32_t)ob_spc << 8); + reg |= ((uint32_t)ob_spc << 8); + FMC_OBCTL0 = reg; } } /*! - \brief program the FMC user option byte + \brief program the FMC user option byte \param[in] ob_fwdgt: option byte watchdog value + only one parameter can be selected which is shown as below: \arg OB_FWDGT_SW: software free watchdog \arg OB_FWDGT_HW: hardware free watchdog \param[in] ob_deepsleep: option byte deepsleep reset value + only one parameter can be selected which is shown as below: \arg OB_DEEPSLEEP_NRST: no reset when entering deepsleep mode - \arg OB_DEEPSLEEP_RST: generate a reset instead of entering deepsleep mode + \arg OB_DEEPSLEEP_RST: generate a reset instead of entering deepsleep mode \param[in] ob_stdby:option byte standby reset value + only one parameter can be selected which is shown as below: \arg OB_STDBY_NRST: no reset when entering standby mode - \arg OB_STDBY_RST: generate a reset instead of entering standby mode + \arg OB_STDBY_RST: generate a reset instead of entering standby mode \param[out] none \retval none */ @@ -559,11 +649,11 @@ void ob_user_write(uint32_t ob_fwdgt, uint32_t ob_deepsleep, uint32_t ob_stdby) fmc_state_enum fmc_state = FMC_READY; /* wait for the FMC ready */ - fmc_state = fmc_ready_wait(FMC_TIMEOUT_COUNT); - + fmc_state = fmc_ready_wait(); + if(FMC_READY == fmc_state){ uint32_t reg; - + reg = FMC_OBCTL0; /* reset the OB_FWDGT, OB_DEEPSLEEP and OB_STDBY, set according to ob_fwdgt ,ob_deepsleep and ob_stdby */ reg &= ~(FMC_OBCTL0_NWDG_HW | FMC_OBCTL0_NRST_DPSLP | FMC_OBCTL0_NRST_STDBY); @@ -574,17 +664,18 @@ void ob_user_write(uint32_t ob_fwdgt, uint32_t ob_deepsleep, uint32_t ob_stdby) /*! \brief program the option byte BOR threshold value \param[in] ob_bor_th: user option byte + only one parameter can be selected which is shown as below: \arg OB_BOR_TH_VALUE3: BOR threshold value 3 \arg OB_BOR_TH_VALUE2: BOR threshold value 2 \arg OB_BOR_TH_VALUE1: BOR threshold value 1 - \arg OB_BOR_TH_OFF: no BOR function. + \arg OB_BOR_TH_OFF: no BOR function \param[out] none \retval none */ void ob_user_bor_threshold(uint32_t ob_bor_th) { uint32_t reg; - + reg = FMC_OBCTL0; /* set the BOR level */ reg &= ~FMC_OBCTL0_BOR_TH; @@ -594,6 +685,7 @@ void ob_user_bor_threshold(uint32_t ob_bor_th) /*! \brief configure the option byte boot bank value \param[in] boot_mode: specifies the option byte boot bank value + only one parameter can be selected which is shown as below: \arg OB_BB_DISABLE: boot from bank0 \arg OB_BB_ENABLE: boot from bank1 or bank0 if bank1 is void \param[out] none @@ -602,7 +694,7 @@ void ob_user_bor_threshold(uint32_t ob_bor_th) void ob_boot_mode_config(uint32_t boot_mode) { uint32_t reg; - + reg = FMC_OBCTL0; /* set option byte boot bank value */ reg &= ~FMC_OBCTL0_BB; @@ -613,7 +705,7 @@ void ob_boot_mode_config(uint32_t boot_mode) \brief get the FMC user option byte \param[in] none \param[out] none - \retval the FMC user option byte values: ob_fwdgt(Bit0), ob_deepsleep(Bit1), ob_stdby(Bit2). + \retval the FMC user option byte values: ob_fwdgt(Bit0), ob_deepsleep(Bit1), ob_stdby(Bit2) */ uint8_t ob_user_get(void) { @@ -677,7 +769,7 @@ uint16_t ob_drp1_get(void) FlagStatus ob_spc_get(void) { FlagStatus spc_state = RESET; - + if (((uint8_t)(FMC_OBCTL0 >> 8)) != (uint8_t)FMC_NSPC){ spc_state = SET; }else{ @@ -700,9 +792,10 @@ uint8_t ob_user_bor_threshold_get(void) /*! \brief enable FMC interrupt - \param[in] the FMC interrupt source - \arg FMC_INTEN_END: enable FMC end of program interrupt - \arg FMC_INTEN_ERR: enable FMC error interrupt + \param[in] fmc_int: the FMC interrupt source + only one parameter can be selected which is shown as below: + \arg FMC_INT_END: enable FMC end of program interrupt + \arg FMC_INT_ERR: enable FMC error interrupt \param[out] none \retval none */ @@ -713,9 +806,10 @@ void fmc_interrupt_enable(uint32_t fmc_int) /*! \brief disable FMC interrupt - \param[in] the FMC interrupt source - \arg FMC_INTEN_END: disable FMC end of program interrupt - \arg FMC_INTEN_ERR: disable FMC error interrupt + \param[in] fmc_int: the FMC interrupt source + only one parameter can be selected which is shown as below: + \arg FMC_INT_END: disable FMC end of program interrupt + \arg FMC_INT_ERR: disable FMC error interrupt \param[out] none \retval none */ @@ -727,12 +821,13 @@ void fmc_interrupt_disable(uint32_t fmc_int) /*! \brief get flag set or reset \param[in] fmc_flag: check FMC flag - \arg FMC_FLAG_BUSY: FMC busy flag + only one parameter can be selected which is shown as below: + \arg FMC_FLAG_BUSY: FMC busy flag bit \arg FMC_FLAG_RDDERR: FMC read D-bus protection error flag bit \arg FMC_FLAG_PGSERR: FMC program sequence error flag bit \arg FMC_FLAG_PGMERR: FMC program size not match error flag bit \arg FMC_FLAG_WPERR: FMC Erase/Program protection error flag bit - \arg FMC_FLAG_OPERR: FMC operation error flag bit + \arg FMC_FLAG_OPERR: FMC operation error flag bit \arg FMC_FLAG_END: FMC end of operation flag bit \param[out] none \retval FlagStatus: SET or RESET @@ -743,17 +838,18 @@ FlagStatus fmc_flag_get(uint32_t fmc_flag) return SET; } /* return the state of corresponding FMC flag */ - return RESET; + return RESET; } /*! \brief clear the FMC pending flag \param[in] FMC_flag: clear FMC flag + only one parameter can be selected which is shown as below: \arg FMC_FLAG_RDDERR: FMC read D-bus protection error flag bit \arg FMC_FLAG_PGSERR: FMC program sequence error flag bit \arg FMC_FLAG_PGMERR: FMC program size not match error flag bit \arg FMC_FLAG_WPERR: FMC erase/program protection error flag bit - \arg FMC_FLAG_OPERR: FMC operation error flag bit + \arg FMC_FLAG_OPERR: FMC operation error flag bit \arg FMC_FLAG_END: FMC end of operation flag bit \param[out] none \retval none @@ -768,23 +864,31 @@ void fmc_flag_clear(uint32_t fmc_flag) \brief get the FMC state \param[in] none \param[out] none - \retval fmc_state_enum + \retval state of FMC + \arg FMC_READY: the operation has been completed + \arg FMC_BUSY: the operation is in progress + \arg FMC_RDDERR: read D-bus protection error + \arg FMC_PGSERR: program sequence error + \arg FMC_PGMERR: program size not match error + \arg FMC_WPERR: erase/program protection error + \arg FMC_OPERR: operation error + \arg FMC_PGERR: program error */ fmc_state_enum fmc_state_get(void) { fmc_state_enum fmc_state = FMC_READY; - + if((FMC_STAT & FMC_FLAG_BUSY) == FMC_FLAG_BUSY){ fmc_state = FMC_BUSY; }else{ - if((FMC_STAT & FMC_FLAG_WPERR) != (uint32_t)0x00){ + if((FMC_STAT & FMC_FLAG_WPERR) != (uint32_t)0x00){ fmc_state = FMC_WPERR; }else{ - if((FMC_STAT & FMC_FLAG_RDDERR) != (uint32_t)0x00){ + if((FMC_STAT & FMC_FLAG_RDDERR) != (uint32_t)0x00){ fmc_state = FMC_RDDERR; }else{ if((FMC_STAT & (uint32_t)0xEF) != (uint32_t)0x00){ - fmc_state = FMC_PGERR; + fmc_state = FMC_PGERR; }else{ if((FMC_STAT & FMC_FLAG_OPERR) != (uint32_t)0x00){ fmc_state = FMC_OPERR; @@ -801,24 +905,28 @@ fmc_state_enum fmc_state_get(void) /*! \brief check whether FMC is ready or not - \param[in] count: FMC_TIMEOUT_COUNT + \param[in] none \param[out] none - \retval fmc_state_enum + \retval state of FMC + \arg FMC_READY: the operation has been completed + \arg FMC_BUSY: the operation is in progress + \arg FMC_RDDERR: read D-bus protection error + \arg FMC_PGSERR: program sequence error + \arg FMC_PGMERR: program size not match error + \arg FMC_WPERR: erase/program protection error + \arg FMC_OPERR: operation error + \arg FMC_PGERR: program error */ -fmc_state_enum fmc_ready_wait(uint32_t count) +fmc_state_enum fmc_ready_wait(void) { fmc_state_enum fmc_state = FMC_BUSY; - + /* wait for FMC ready */ do{ /* get FMC state */ fmc_state = fmc_state_get(); - count--; - }while((FMC_BUSY == fmc_state) && ((uint32_t)RESET != count)); - - if(FMC_BUSY == fmc_state){ - fmc_state = FMC_TOERR; - } + }while(FMC_BUSY == fmc_state); + /* return the FMC state */ return fmc_state; } diff --git a/bsp/gd32450z-eval/Libraries/GD32F4xx_standard_peripheral/Source/gd32f4xx_fwdgt.c b/bsp/gd32450z-eval/Libraries/GD32F4xx_standard_peripheral/Source/gd32f4xx_fwdgt.c index 4762344417..04e2c5b99d 100644 --- a/bsp/gd32450z-eval/Libraries/GD32F4xx_standard_peripheral/Source/gd32f4xx_fwdgt.c +++ b/bsp/gd32450z-eval/Libraries/GD32F4xx_standard_peripheral/Source/gd32f4xx_fwdgt.c @@ -1,12 +1,37 @@ /*! - \file gd32f4xx_fwdgt.c - \brief FWDGT driver + \file gd32f4xx_fwdgt.c + \brief FWDGT driver + + \version 2016-08-15, V1.0.0, firmware for GD32F4xx + \version 2018-12-12, V2.0.0, firmware for GD32F4xx + \version 2020-09-30, V2.1.0, firmware for GD32F4xx */ /* - Copyright (C) 2016 GigaDevice + Copyright (c) 2020, GigaDevice Semiconductor Inc. + + Redistribution and use in source and binary forms, with or without modification, +are permitted provided that the following conditions are met: - 2016-08-15, V1.0.0, firmware for GD32F4xx + 1. Redistributions of source code must retain the above copyright notice, this + list of conditions and the following disclaimer. + 2. Redistributions in binary form must reproduce the above copyright notice, + this list of conditions and the following disclaimer in the documentation + and/or other materials provided with the distribution. + 3. Neither the name of the copyright holder nor the names of its contributors + may be used to endorse or promote products derived from this software without + specific prior written permission. + + THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED +WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. +IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, +INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT +NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR +PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, +WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY +OF SUCH DAMAGE. */ #include "gd32f4xx_fwdgt.h" @@ -17,25 +42,25 @@ #define RLD_RLD(regval) (BITS(0,11) & ((uint32_t)(regval) << 0)) /*! - \brief disable write access to FWDGT_PSC and FWDGT_RLD + \brief enable write access to FWDGT_PSC and FWDGT_RLD \param[in] none \param[out] none \retval none */ -void fwdgt_write_disable(void) +void fwdgt_write_enable(void) { - FWDGT_CTL = FWDGT_WRITEACCESS_DISABLE; + FWDGT_CTL = FWDGT_WRITEACCESS_ENABLE; } /*! - \brief reload the counter of FWDGT + \brief disable write access to FWDGT_PSC and FWDGT_RLD \param[in] none \param[out] none \retval none */ -void fwdgt_counter_reload(void) +void fwdgt_write_disable(void) { - FWDGT_CTL = FWDGT_KEY_RELOAD; + FWDGT_CTL = FWDGT_WRITEACCESS_DISABLE; } /*! @@ -49,11 +74,22 @@ void fwdgt_enable(void) FWDGT_CTL = FWDGT_KEY_ENABLE; } +/*! + \brief reload the counter of FWDGT + \param[in] none + \param[out] none + \retval none +*/ +void fwdgt_counter_reload(void) +{ + FWDGT_CTL = FWDGT_KEY_RELOAD; +} /*! \brief configure counter reload value, and prescaler divider value \param[in] reload_value: specify reload value(0x0000 - 0x0FFF) \param[in] prescaler_div: FWDGT prescaler value + only one parameter can be selected which is shown as below: \arg FWDGT_PSC_DIV4: FWDGT prescaler set to 4 \arg FWDGT_PSC_DIV8: FWDGT prescaler set to 8 \arg FWDGT_PSC_DIV16: FWDGT prescaler set to 16 @@ -68,15 +104,15 @@ ErrStatus fwdgt_config(uint16_t reload_value, uint8_t prescaler_div) { uint32_t timeout = FWDGT_PSC_TIMEOUT; uint32_t flag_status = RESET; - + /* enable write access to FWDGT_PSC,and FWDGT_RLD */ FWDGT_CTL = FWDGT_WRITEACCESS_ENABLE; - + /* wait until the PUD flag to be reset */ do{ flag_status = FWDGT_STAT & FWDGT_STAT_PUD; }while((--timeout > 0U) && ((uint32_t)RESET != flag_status)); - + if ((uint32_t)RESET != flag_status){ return ERROR; } @@ -89,13 +125,13 @@ ErrStatus fwdgt_config(uint16_t reload_value, uint8_t prescaler_div) do{ flag_status = FWDGT_STAT & FWDGT_STAT_RUD; }while((--timeout > 0U) && ((uint32_t)RESET != flag_status)); - + if ((uint32_t)RESET != flag_status){ return ERROR; } - + FWDGT_RLD = RLD_RLD(reload_value); - + /* reload the counter */ FWDGT_CTL = FWDGT_KEY_RELOAD; @@ -104,7 +140,8 @@ ErrStatus fwdgt_config(uint16_t reload_value, uint8_t prescaler_div) /*! \brief get flag state of FWDGT - \param[in] flag: flag to get + \param[in] flag: flag to get + only one parameter can be selected which is shown as below: \arg FWDGT_STAT_PUD: a write operation to FWDGT_PSC register is on going \arg FWDGT_STAT_RUD: a write operation to FWDGT_RLD register is on going \param[out] none @@ -112,7 +149,7 @@ ErrStatus fwdgt_config(uint16_t reload_value, uint8_t prescaler_div) */ FlagStatus fwdgt_flag_get(uint16_t flag) { - if(FWDGT_STAT & flag){ + if(RESET != (FWDGT_STAT & flag)){ return SET; } diff --git a/bsp/gd32450z-eval/Libraries/GD32F4xx_standard_peripheral/Source/gd32f4xx_gpio.c b/bsp/gd32450z-eval/Libraries/GD32F4xx_standard_peripheral/Source/gd32f4xx_gpio.c index ccce538926..d3693abb17 100644 --- a/bsp/gd32450z-eval/Libraries/GD32F4xx_standard_peripheral/Source/gd32f4xx_gpio.c +++ b/bsp/gd32450z-eval/Libraries/GD32F4xx_standard_peripheral/Source/gd32f4xx_gpio.c @@ -1,19 +1,46 @@ /*! - \file gd32f4xx_gpio.c - \brief GPIO driver + \file gd32f4xx_gpio.c + \brief GPIO driver + + \version 2016-08-15, V1.0.0, firmware for GD32F4xx + \version 2018-12-12, V2.0.0, firmware for GD32F4xx + \version 2020-09-30, V2.1.0, firmware for GD32F4xx */ /* - Copyright (C) 2016 GigaDevice + Copyright (c) 2020, GigaDevice Semiconductor Inc. + + Redistribution and use in source and binary forms, with or without modification, +are permitted provided that the following conditions are met: + + 1. Redistributions of source code must retain the above copyright notice, this + list of conditions and the following disclaimer. + 2. Redistributions in binary form must reproduce the above copyright notice, + this list of conditions and the following disclaimer in the documentation + and/or other materials provided with the distribution. + 3. Neither the name of the copyright holder nor the names of its contributors + may be used to endorse or promote products derived from this software without + specific prior written permission. - 2016-08-15, V1.0.0, firmware for GD32F4xx + THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED +WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. +IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, +INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT +NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR +PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, +WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY +OF SUCH DAMAGE. */ #include "gd32f4xx_gpio.h" /*! \brief reset GPIO port - \param[in] gpio_periph: GPIOx(x = A,B,C,D,E,F,G,H,I) + \param[in] gpio_periph: GPIO port + only one parameter can be selected which is shown as below: + \arg GPIOx(x = A,B,C,D,E,F,G,H,I) \param[out] none \retval none */ @@ -71,22 +98,26 @@ void gpio_deinit(uint32_t gpio_periph) } /*! - \brief set GPIO output mode - \param[in] gpio_periph: GPIOx(x = A,B,C,D,E,F,G,H,I) - \param[in] mode: gpio pin mode + \brief set GPIO mode + \param[in] gpio_periph: GPIO port + only one parameter can be selected which is shown as below: + \arg GPIOx(x = A,B,C,D,E,F,G,H,I) + \param[in] mode: GPIO pin mode \arg GPIO_MODE_INPUT: input mode \arg GPIO_MODE_OUTPUT: output mode \arg GPIO_MODE_AF: alternate function mode \arg GPIO_MODE_ANALOG: analog mode - \param[in] pull_up_down: gpio pin with pull-up or pull-down resistor - \arg GPIO_PUPD_NONE: without weak pull-up and pull-down resistors - \arg GPIO_PUPD_PULLUP: with weak pull-up resistor - \arg GPIO_PUPD_PULLDOWN:with weak pull-down resistor - \param[in] pin: GPIO_PIN_x(x=0..15), GPIO_PIN_ALL + \param[in] pull_up_down: GPIO pin with pull-up or pull-down resistor + \arg GPIO_PUPD_NONE: floating mode, no pull-up and pull-down resistors + \arg GPIO_PUPD_PULLUP: with pull-up resistor + \arg GPIO_PUPD_PULLDOWN:with pull-down resistor + \param[in] pin: GPIO pin + one or more parameters can be selected which are shown as below: + \arg GPIO_PIN_x(x=0..15), GPIO_PIN_ALL \param[out] none \retval none */ -void gpio_mode_set(uint32_t gpio_periph,uint32_t mode,uint32_t pull_up_down,uint32_t pin) +void gpio_mode_set(uint32_t gpio_periph, uint32_t mode, uint32_t pull_up_down, uint32_t pin) { uint16_t i; uint32_t ctl, pupd; @@ -114,25 +145,29 @@ void gpio_mode_set(uint32_t gpio_periph,uint32_t mode,uint32_t pull_up_down,uint /*! \brief set GPIO output type and speed - \param[in] gpio_periph: GPIOx(x = A,B,C,D,E,F,G,H,I) - \param[in] otype: gpio pin output mode + \param[in] gpio_periph: GPIO port + only one parameter can be selected which is shown as below: + \arg GPIOx(x = A,B,C,D,E,F,G,H,I) + \param[in] otype: GPIO pin output mode \arg GPIO_OTYPE_PP: push pull mode \arg GPIO_OTYPE_OD: open drain mode - \param[in] speed: gpio pin output max speed - \arg GPIO_OSPEED_2MHZ: output max speed 2M - \arg GPIO_OSPEED_25MHZ: output max speed 25M - \arg GPIO_OSPEED_50MHZ: output max speed 50M - \arg GPIO_OSPEED_200MHZ: output max speed 200M - \param[in] pin: GPIO_PIN_x(x=0..15), GPIO_PIN_ALL + \param[in] speed: GPIO pin output max speed + \arg GPIO_OSPEED_2MHZ: output max speed 2MHz + \arg GPIO_OSPEED_25MHZ: output max speed 25MHz + \arg GPIO_OSPEED_50MHZ: output max speed 50MHz + \arg GPIO_OSPEED_200MHZ: output max speed 200MHz + \param[in] pin: GPIO pin + one or more parameters can be selected which are shown as below: + \arg GPIO_PIN_x(x=0..15), GPIO_PIN_ALL \param[out] none \retval none */ -void gpio_output_options_set(uint32_t gpio_periph,uint8_t otype,uint32_t speed,uint32_t pin) +void gpio_output_options_set(uint32_t gpio_periph, uint8_t otype, uint32_t speed, uint32_t pin) { uint16_t i; uint32_t ospeedr; - if(0x1U == otype){ + if(GPIO_OTYPE_OD == otype){ GPIO_OMODE(gpio_periph) |= (uint32_t)pin; }else{ GPIO_OMODE(gpio_periph) &= (uint32_t)(~pin); @@ -153,40 +188,52 @@ void gpio_output_options_set(uint32_t gpio_periph,uint8_t otype,uint32_t speed,u } /*! - \brief set GPIO pin - \param[in] gpio_periph: GPIOx(x = A,B,C,D,E,F,G,H,I) - \param[in] pin: GPIO_PIN_x(x=0..15), GPIO_PIN_ALL + \brief set GPIO pin bit + \param[in] gpio_periph: GPIO port + only one parameter can be selected which is shown as below: + \arg GPIOx(x = A,B,C,D,E,F,G,H,I) + \param[in] pin: GPIO pin + one or more parameters can be selected which are shown as below: + \arg GPIO_PIN_x(x=0..15), GPIO_PIN_ALL \param[out] none \retval none */ -void gpio_bit_set(uint32_t gpio_periph,uint32_t pin) +void gpio_bit_set(uint32_t gpio_periph, uint32_t pin) { GPIO_BOP(gpio_periph) = (uint32_t)pin; } /*! - \brief reset GPIO pin - \param[in] gpio_periph: GPIOx(x = A,B,C,D,E,F,G,H,I) - \param[in] pin: GPIO_PIN_x(x=0..15), GPIO_PIN_ALL + \brief reset GPIO pin bit + \param[in] gpio_periph: GPIO port + only one parameter can be selected which is shown as below: + \arg GPIOx(x = A,B,C,D,E,F,G,H,I) + \param[in] pin: GPIO pin + one or more parameters can be selected which are shown as below: + \arg GPIO_PIN_x(x=0..15), GPIO_PIN_ALL \param[out] none \retval none */ -void gpio_bit_reset(uint32_t gpio_periph,uint32_t pin) +void gpio_bit_reset(uint32_t gpio_periph, uint32_t pin) { GPIO_BC(gpio_periph) = (uint32_t)pin; } /*! \brief write data to the specified GPIO pin - \param[in] gpio_periph: GPIOx(x = A,B,C,D,E,F,G,H,I) - \param[in] pin: GPIO_PIN_x(x=0..15), GPIO_PIN_ALL - \param[in] bitvalue: SET or RESET + \param[in] gpio_periph: GPIO port + only one parameter can be selected which is shown as below: + \arg GPIOx(x = A,B,C,D,E,F,G,H,I) + \param[in] pin: GPIO pin + one or more parameters can be selected which are shown as below: + \arg GPIO_PIN_x(x=0..15), GPIO_PIN_ALL + \param[in] bit_value: SET or RESET \arg RESET: clear the port pin \arg SET: set the port pin \param[out] none \retval none */ -void gpio_bit_write(uint32_t gpio_periph,uint32_t pin,bit_status bit_value) +void gpio_bit_write(uint32_t gpio_periph, uint32_t pin, bit_status bit_value) { if(RESET != bit_value){ GPIO_BOP(gpio_periph) = (uint32_t)pin; @@ -197,27 +244,33 @@ void gpio_bit_write(uint32_t gpio_periph,uint32_t pin,bit_status bit_value) /*! \brief write data to the specified GPIO port - \param[in] gpio_periph: GPIOx(x = A,B,C,D,E,F,G,H,I) - \param[in] data: specify the value to be written to the port output data register + \param[in] gpio_periph: GPIO port + only one parameter can be selected which is shown as below: + \arg GPIOx(x = A,B,C,D,E,F,G,H,I) + \param[in] data: specify the value to be written to the port output control register \param[out] none \retval none */ -void gpio_port_write(uint32_t gpio_periph,uint16_t data) +void gpio_port_write(uint32_t gpio_periph, uint16_t data) { GPIO_OCTL(gpio_periph) = (uint32_t)data; } /*! \brief get GPIO pin input status - \param[in] gpio_periph: GPIOx(x = A,B,C,D,E,F,G,H,I) - \param[in] pin: GPIO_PIN_x(x=0..15), GPIO_PIN_ALL + \param[in] gpio_periph: GPIO port + only one parameter can be selected which is shown as below: + \arg GPIOx(x = A,B,C,D,E,F,G,H,I) + \param[in] pin: GPIO pin + one or more parameters can be selected which are shown as below: + \arg GPIO_PIN_x(x=0..15), GPIO_PIN_ALL \param[out] none - \retval input state of gpio pin: SET or RESET + \retval input status of GPIO pin: SET or RESET */ -FlagStatus gpio_input_bit_get(uint32_t gpio_periph,uint32_t pin) +FlagStatus gpio_input_bit_get(uint32_t gpio_periph, uint32_t pin) { if((uint32_t)RESET != (GPIO_ISTAT(gpio_periph)&(pin))){ - return SET; + return SET; }else{ return RESET; } @@ -225,23 +278,29 @@ FlagStatus gpio_input_bit_get(uint32_t gpio_periph,uint32_t pin) /*! \brief get GPIO all pins input status - \param[in] gpio_periph: GPIOx(x = A,B,C,D,E,F,G,H,I) + \param[in] gpio_periph: GPIO port + only one parameter can be selected which is shown as below: + \arg GPIOx(x = A,B,C,D,E,F,G,H,I) \param[out] none - \retval input state of gpio all pins + \retval input status of GPIO all pins */ uint16_t gpio_input_port_get(uint32_t gpio_periph) { - return (uint16_t)(GPIO_ISTAT(gpio_periph)); + return ((uint16_t)GPIO_ISTAT(gpio_periph)); } /*! \brief get GPIO pin output status - \param[in] gpio_periph: GPIOx(x = A,B,C,D,E,F,G,H,I) - \param[in] pin: GPIO_PIN_x(x=0..15), GPIO_PIN_ALL + \param[in] gpio_periph: GPIO port + only one parameter can be selected which is shown as below: + \arg GPIOx(x = A,B,C,D,E,F,G,H,I) + \param[in] pin: GPIO pin + one or more parameters can be selected which are shown as below: + \arg GPIO_PIN_x(x=0..15), GPIO_PIN_ALL \param[out] none - \retval output state of gpio pin: SET or RESET + \retval output status of GPIO pin: SET or RESET */ -FlagStatus gpio_output_bit_get(uint32_t gpio_periph,uint32_t pin) +FlagStatus gpio_output_bit_get(uint32_t gpio_periph, uint32_t pin) { if((uint32_t)RESET !=(GPIO_OCTL(gpio_periph)&(pin))){ return SET; @@ -252,9 +311,11 @@ FlagStatus gpio_output_bit_get(uint32_t gpio_periph,uint32_t pin) /*! \brief get GPIO all pins output status - \param[in] gpio_periph: GPIOx(x = A,B,C,D,E,F,G,H,I) + \param[in] gpio_periph: GPIO port + only one parameter can be selected which is shown as below: + \arg GPIOx(x = A,B,C,D,E,F,G,H,I) \param[out] none - \retval output state of gpio all pins + \retval output status of GPIO all pins */ uint16_t gpio_output_port_get(uint32_t gpio_periph) { @@ -263,29 +324,33 @@ uint16_t gpio_output_port_get(uint32_t gpio_periph) /*! \brief set GPIO alternate function - \param[in] gpio_periph: GPIOx(x = A,B,C,D,E,F,G,H,I) - \param[in] alt_func_num: gpio pin af function + \param[in] gpio_periph: GPIO port + only one parameter can be selected which is shown as below: + \arg GPIOx(x = A,B,C,D,E,F,G,H,I) + \param[in] alt_func_num: GPIO pin af function \arg GPIO_AF_0: SYSTEM \arg GPIO_AF_1: TIMER0, TIMER1 \arg GPIO_AF_2: TIMER2, TIMER3, TIMER4 \arg GPIO_AF_3: TIMER7, TIMER8, TIMER9, TIMER10 \arg GPIO_AF_4: I2C0, I2C1, I2C2 \arg GPIO_AF_5: SPI0, SPI1, SPI2, SPI3, SPI4, SPI5 - \arg GPIO_AF_6: SPI1, SPI2, SAI0 + \arg GPIO_AF_6: SPI1, SPI2, SAI0 \arg GPIO_AF_7: USART0, USART1, USART2 \arg GPIO_AF_8: UART3, UART4, USART5, UART6, UART7 - \arg GPIO_AF_9: CAN0,CAN1, TLI, TIMER11, TIMER12, TIMER13 + \arg GPIO_AF_9: CAN0, CAN1, TLI, TIMER11, TIMER12, TIMER13 \arg GPIO_AF_10: USB_FS, USB_HS \arg GPIO_AF_11: ENET - \arg GPIO_AF_12: FMC, SDIO, USB_HS + \arg GPIO_AF_12: EXMC, SDIO, USB_HS \arg GPIO_AF_13: DCI \arg GPIO_AF_14: TLI \arg GPIO_AF_15: EVENTOUT - \param[in] pin: GPIO_PIN_x(x=0..15), GPIO_PIN_ALL + \param[in] pin: GPIO pin + one or more parameters can be selected which are shown as below: + \arg GPIO_PIN_x(x=0..15), GPIO_PIN_ALL \param[out] none \retval none */ -void gpio_af_set(uint32_t gpio_periph,uint32_t alt_func_num,uint32_t pin) +void gpio_af_set(uint32_t gpio_periph, uint32_t alt_func_num, uint32_t pin) { uint16_t i; uint32_t afrl, afrh; @@ -314,18 +379,22 @@ void gpio_af_set(uint32_t gpio_periph,uint32_t alt_func_num,uint32_t pin) } /*! - \brief lock GPIO pin - \param[in] gpio_periph: GPIOx(x = A,B,C,D,E,F,G,H,I) - \param[in] pin: GPIO_PIN_x(x=0..15), GPIO_PIN_ALL + \brief lock GPIO pin bit + \param[in] gpio_periph: GPIO port + only one parameter can be selected which is shown as below: + \arg GPIOx(x = A,B,C,D,E,F,G,H,I) + \param[in] pin: GPIO pin + one or more parameters can be selected which are shown as below: + \arg GPIO_PIN_x(x=0..15), GPIO_PIN_ALL \param[out] none \retval none */ -void gpio_pin_lock(uint32_t gpio_periph,uint32_t pin) +void gpio_pin_lock(uint32_t gpio_periph, uint32_t pin) { uint32_t lock = 0x00010000U; lock |= pin; - /* lock key writing sequence: write 1->write 0->write 1-> read 0-> read 1 */ + /* lock key writing sequence: write 1->write 0->write 1->read 0->read 1 */ GPIO_LOCK(gpio_periph) = (uint32_t)lock; GPIO_LOCK(gpio_periph) = (uint32_t)pin; GPIO_LOCK(gpio_periph) = (uint32_t)lock; @@ -334,20 +403,27 @@ void gpio_pin_lock(uint32_t gpio_periph,uint32_t pin) } /*! - \brief toggle GPIO pin - \param[in] gpio_periph: GPIOx(x = A,B,C,D,E,F,G,H,I) - \param[in] pin: GPIO_PIN_x(x=0..15), GPIO_PIN_ALL + \brief toggle GPIO pin status + \param[in] gpio_periph: GPIO port + only one parameter can be selected which is shown as below: + \arg GPIOx(x = A,B,C,D,E,F,G,H,I) + \param[in] pin: GPIO pin + one or more parameters can be selected which are shown as below: + \arg GPIO_PIN_x(x=0..15), GPIO_PIN_ALL \param[out] none \retval none */ -void gpio_bit_toggle(uint32_t gpio_periph,uint32_t pin) +void gpio_bit_toggle(uint32_t gpio_periph, uint32_t pin) { GPIO_TG(gpio_periph) = (uint32_t)pin; } /*! - \brief toggle GPIO port - \param[in] gpio_periph: GPIOx(x = A,B,C,D,E,F,G,H,I) + \brief toggle GPIO port status + \param[in] gpio_periph: GPIO port + only one parameter can be selected which is shown as below: + \arg GPIOx(x = A,B,C,D,E,F,G,H,I) + \param[out] none \retval none */ diff --git a/bsp/gd32450z-eval/Libraries/GD32F4xx_standard_peripheral/Source/gd32f4xx_i2c.c b/bsp/gd32450z-eval/Libraries/GD32F4xx_standard_peripheral/Source/gd32f4xx_i2c.c index 79480b63e5..c3ac50c178 100644 --- a/bsp/gd32450z-eval/Libraries/GD32F4xx_standard_peripheral/Source/gd32f4xx_i2c.c +++ b/bsp/gd32450z-eval/Libraries/GD32F4xx_standard_peripheral/Source/gd32f4xx_i2c.c @@ -1,19 +1,51 @@ /*! - \file gd32f4xx_i2c.c - \brief I2C driver + \file gd32f4xx_i2c.c + \brief I2C driver + \version 2016-08-15, V1.0.0, firmware for GD32F4xx + \version 2018-12-12, V2.0.0, firmware for GD32F4xx + \version 2019-04-16, V2.0.2, firmware for GD32F4xx + \version 2020-09-30, V2.1.0, firmware for GD32F4xx */ /* - Copyright (C) 2016 GigaDevice + Copyright (c) 2020, GigaDevice Semiconductor Inc. - 2016-08-15, V1.0.0, firmware for GD32F4xx + Redistribution and use in source and binary forms, with or without modification, +are permitted provided that the following conditions are met: + + 1. Redistributions of source code must retain the above copyright notice, this + list of conditions and the following disclaimer. + 2. Redistributions in binary form must reproduce the above copyright notice, + this list of conditions and the following disclaimer in the documentation + and/or other materials provided with the distribution. + 3. Neither the name of the copyright holder nor the names of its contributors + may be used to endorse or promote products derived from this software without + specific prior written permission. + + THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED +WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. +IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, +INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT +NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR +PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, +WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY +OF SUCH DAMAGE. */ #include "gd32f4xx_i2c.h" -#define I2CCLK_MAX 0x3fU /*!< i2cclk max value */ -#define I2C_STATE_MASK 0x0000FFFFU /*!< i2c state mask */ +/* I2C register bit mask */ +#define I2CCLK_MAX ((uint32_t)0x00000032U) /*!< i2cclk maximum value */ +#define I2CCLK_MIN ((uint32_t)0x00000002U) /*!< i2cclk minimum value */ +#define I2C_FLAG_MASK ((uint32_t)0x0000FFFFU) /*!< i2c flag mask */ +#define I2C_ADDRESS_MASK ((uint32_t)0x000003FFU) /*!< i2c address mask */ +#define I2C_ADDRESS2_MASK ((uint32_t)0x000000FEU) /*!< the second i2c address mask */ + +/* I2C register bit offset */ +#define STAT1_PECV_OFFSET ((uint32_t)8U) /* bit offset of PECV in I2C_STAT1 */ /*! \brief reset I2C @@ -25,202 +57,229 @@ void i2c_deinit(uint32_t i2c_periph) { switch(i2c_periph){ case I2C0: + /* reset I2C0 */ rcu_periph_reset_enable(RCU_I2C0RST); rcu_periph_reset_disable(RCU_I2C0RST); break; case I2C1: + /* reset I2C1 */ rcu_periph_reset_enable(RCU_I2C1RST); rcu_periph_reset_disable(RCU_I2C1RST); break; case I2C2: + /* reset I2C2 */ rcu_periph_reset_enable(RCU_I2C2RST); rcu_periph_reset_disable(RCU_I2C2RST); break; default: break; - } } /*! - \brief I2C clock configure + \brief configure I2C clock \param[in] i2c_periph: I2Cx(x=0,1,2) - \param[in] clkspeed: i2c clock speed + \param[in] clkspeed: I2C clock speed, supports standard mode (up to 100 kHz), fast mode (up to 400 kHz) \param[in] dutycyc: duty cycle in fast mode - \arg I2C_DTCY_2: T_low/T_high=2 + only one parameter can be selected which is shown as below: + \arg I2C_DTCY_2: T_low/T_high=2 \arg I2C_DTCY_16_9: T_low/T_high=16/9 \param[out] none \retval none */ -void i2c_clock_config(uint32_t i2c_periph,uint32_t clkspeed,uint32_t dutycyc) +void i2c_clock_config(uint32_t i2c_periph, uint32_t clkspeed, uint32_t dutycyc) { - uint32_t pclk1,clkc,i2cclk,risetime; + uint32_t pclk1, clkc, freq, risetime; + uint32_t temp; + pclk1 = rcu_clock_freq_get(CK_APB1); - /* I2C Peripheral clock frequency */ - i2cclk=((pclk1)/(uint32_t)(1000000)); - if(i2cclk >= I2CCLK_MAX){ - i2cclk = I2CCLK_MAX; + /* I2C peripheral clock frequency */ + freq = (uint32_t)(pclk1/1000000U); + if(freq >= I2CCLK_MAX){ + freq = I2CCLK_MAX; } - - I2C_CTL1(i2c_periph) |= (I2C_CTL1_I2CCLK & i2cclk) ; - + temp = I2C_CTL1(i2c_periph); + temp &= ~I2C_CTL1_I2CCLK; + temp |= freq; + + I2C_CTL1(i2c_periph) = temp; + if(100000U >= clkspeed){ - /* standard mode the maximum SCL rise time in standard mode is 1000ns */ + /* the maximum SCL rise time is 1000ns in standard mode */ risetime = (uint32_t)((pclk1/1000000U)+1U); if(risetime >= I2CCLK_MAX){ - I2C_RT(i2c_periph) |= I2CCLK_MAX; + I2C_RT(i2c_periph) = I2CCLK_MAX; }else{ - I2C_RT(i2c_periph) |= (uint32_t)((pclk1/1000000U)+1U); + I2C_RT(i2c_periph) = risetime; } clkc = (uint32_t)(pclk1/(clkspeed*2U)); if(clkc < 0x04U){ - /* The CLKC in standard mode minmum value is 4*/ + /* the CLKC in standard mode minmum value is 4 */ clkc = 0x04U; } - I2C_CKCFG(i2c_periph) |= (I2C_CKCFG_CLKC & clkc); - }else{ - /* fast mode the maximum SCL rise time in standard mode is 300ns */ - I2C_RT(i2c_periph) |= (uint16_t)(((i2cclk*(uint16_t)300)/(uint16_t)1000)+(uint16_t)1); + I2C_CKCFG(i2c_periph) |= (I2C_CKCFG_CLKC & clkc); + + }else if(400000U >= clkspeed){ + /* the maximum SCL rise time is 300ns in fast mode */ + I2C_RT(i2c_periph) = (uint32_t)(((freq*(uint32_t)300U)/(uint32_t)1000U)+(uint32_t)1U); if(I2C_DTCY_2 == dutycyc){ - /* I2C_DutyCycle == 2 */ - clkc = (uint16_t)(pclk1/(clkspeed*3U)); - } else{ - /* I2C_DutyCycle == 16/9 */ - clkc = (uint16_t)(pclk1/(clkspeed*25U)); + /* I2C duty cycle is 2 */ + clkc = (uint32_t)(pclk1/(clkspeed*3U)); + I2C_CKCFG(i2c_periph) &= ~I2C_CKCFG_DTCY; + }else{ + /* I2C duty cycle is 16/9 */ + clkc = (uint32_t)(pclk1/(clkspeed*25U)); I2C_CKCFG(i2c_periph) |= I2C_CKCFG_DTCY; } - if((clkc & I2C_CKCFG_CLKC) == 0U){ - /* The CLKC in standard mode minmum value is 1*/ - clkc |= (uint16_t)0x0001; + if(0U == (clkc & I2C_CKCFG_CLKC)){ + /* the CLKC in fast mode minmum value is 1 */ + clkc |= 0x0001U; } + I2C_CKCFG(i2c_periph) |= I2C_CKCFG_FAST; I2C_CKCFG(i2c_periph) |= clkc; + }else{ } } /*! - \brief I2C address configure + \brief configure I2C address \param[in] i2c_periph: I2Cx(x=0,1,2) - \param[in] i2cmod: - \arg I2C_I2CMODE_ENABLE: I2C mode + \param[in] mode: + only one parameter can be selected which is shown as below: + \arg I2C_I2CMODE_ENABLE: I2C mode \arg I2C_SMBUSMODE_ENABLE: SMBus mode \param[in] addformat: 7bits or 10bits - \arg I2C_ADDFORMAT_7BITS: 7bits + only one parameter can be selected which is shown as below: + \arg I2C_ADDFORMAT_7BITS: 7bits \arg I2C_ADDFORMAT_10BITS: 10bits \param[in] addr: I2C address \param[out] none \retval none */ -void i2c_mode_addr_config(uint32_t i2c_periph,uint32_t i2cmod,uint32_t addformat,uint32_t addr) +void i2c_mode_addr_config(uint32_t i2c_periph, uint32_t mode, uint32_t addformat, uint32_t addr) { /* SMBus/I2C mode selected */ uint32_t ctl = 0U; + ctl = I2C_CTL0(i2c_periph); - ctl &= ~(I2C_CTL0_SMBEN); - ctl |= i2cmod; + ctl &= ~(I2C_CTL0_SMBEN); + ctl |= mode; I2C_CTL0(i2c_periph) = ctl; /* configure address */ - I2C_SADDR0(i2c_periph) = (addformat|addr); - + addr = addr & I2C_ADDRESS_MASK; + I2C_SADDR0(i2c_periph) = (addformat | addr); } /*! \brief SMBus type selection \param[in] i2c_periph: I2Cx(x=0,1,2) - \param[in] ack: + \param[in] type: + only one parameter can be selected which is shown as below: \arg I2C_SMBUS_DEVICE: device \arg I2C_SMBUS_HOST: host \param[out] none \retval none */ -void i2c_smbus_type_config(uint32_t i2c_periph,uint32_t type) +void i2c_smbus_type_config(uint32_t i2c_periph, uint32_t type) { if(I2C_SMBUS_HOST == type){ - I2C_CTL0(i2c_periph) |= I2C_CTL0_SMBSEL; + I2C_CTL0(i2c_periph) |= I2C_CTL0_SMBSEL; }else{ - I2C_CTL0(i2c_periph) &= ~(I2C_CTL0_SMBSEL); - } + I2C_CTL0(i2c_periph) &= ~(I2C_CTL0_SMBSEL); + } } /*! \brief whether or not to send an ACK \param[in] i2c_periph: I2Cx(x=0,1,2) \param[in] ack: - \arg I2C_ACK_ENABLE: ACK will be sent - \arg I2C_ACK_DISABLE: ACK will not be sent + only one parameter can be selected which is shown as below: + \arg I2C_ACK_ENABLE: ACK will be sent + \arg I2C_ACK_DISABLE: ACK will not be sent \param[out] none \retval none */ -void i2c_ack_config(uint32_t i2c_periph,uint8_t ack) +void i2c_ack_config(uint32_t i2c_periph, uint32_t ack) { if(I2C_ACK_ENABLE == ack){ - I2C_CTL0(i2c_periph) |= I2C_CTL0_ACKEN; + I2C_CTL0(i2c_periph) |= I2C_CTL0_ACKEN; }else{ - I2C_CTL0(i2c_periph) &= ~(I2C_CTL0_ACKEN); - } + I2C_CTL0(i2c_periph) &= ~(I2C_CTL0_ACKEN); + } } /*! - \brief I2C POAP position configure + \brief configure I2C POAP position \param[in] i2c_periph: I2Cx(x=0,1,2) \param[in] pos: - \arg I2C_ACK_ENABLE: ACK will be sent - \arg I2C_ACK_DISABLE: ACK will not be sent + only one parameter can be selected which is shown as below: + \arg I2C_ACKPOS_CURRENT: whether to send ACK or not for the current + \arg I2C_ACKPOS_NEXT: whether to send ACK or not for the next byte \param[out] none \retval none */ -void i2c_ackpos_config(uint32_t i2c_periph,uint8_t pos) +void i2c_ackpos_config(uint32_t i2c_periph, uint32_t pos) { - /* configure i2c POAP position */ + /* configure I2C POAP position */ if(I2C_ACKPOS_NEXT == pos){ - I2C_CTL0(i2c_periph) |= I2C_CTL0_POAP; + I2C_CTL0(i2c_periph) |= I2C_CTL0_POAP; }else{ - I2C_CTL0(i2c_periph) &= ~(I2C_CTL0_POAP); - } - + I2C_CTL0(i2c_periph) &= ~(I2C_CTL0_POAP); + } } /*! - \brief master send slave address + \brief master sends slave address \param[in] i2c_periph: I2Cx(x=0,1,2) - \param[in] addr: slave address + \param[in] addr: slave address \param[in] trandirection: transmitter or receiver - \arg I2C_TRANSMITTER: transmitter - \arg I2C_RECEIVER: receiver + only one parameter can be selected which is shown as below: + \arg I2C_TRANSMITTER: transmitter + \arg I2C_RECEIVER: receiver \param[out] none \retval none */ -void i2c_master_addressing(uint32_t i2c_periph,uint8_t addr,uint32_t trandirection) +void i2c_master_addressing(uint32_t i2c_periph, uint32_t addr, uint32_t trandirection) { - if(I2C_TRANSMITTER==trandirection){ - addr = (uint8_t)((uint32_t)addr & I2C_TRANSMITTER); + /* master is a transmitter or a receiver */ + if(I2C_TRANSMITTER == trandirection){ + addr = addr & I2C_TRANSMITTER; }else{ - addr = (uint8_t)((uint32_t)addr|I2C_RECEIVER); + addr = addr | I2C_RECEIVER; } + /* send slave address */ I2C_DATA(i2c_periph) = addr; } /*! - \brief dual-address mode switch + \brief enable dual-address mode \param[in] i2c_periph: I2Cx(x=0,1,2) - \param[in] dualaddr: - \arg I2C_DUADEN_DISABLE: dual-address mode disabled - \arg I2C_DUADEN_ENABLE: dual-address mode enabled + \param[in] addr: the second address in dual-address mode \param[out] none \retval none */ -void i2c_dualaddr_enable(uint32_t i2c_periph,uint8_t dualaddr) +void i2c_dualaddr_enable(uint32_t i2c_periph, uint32_t addr) { - if(I2C_DUADEN_ENABLE == dualaddr){ - I2C_SADDR1(i2c_periph) |= I2C_SADDR1_DUADEN; - }else{ - I2C_SADDR1(i2c_periph) &= ~(I2C_SADDR1_DUADEN); - } + /* configure address */ + addr = addr & I2C_ADDRESS2_MASK; + I2C_SADDR1(i2c_periph) = (I2C_SADDR1_DUADEN | addr); } /*! - \brief enable i2c - \param[in] i2c_periph: I2Cx(x=0,1,2) + \brief disable dual-address mode + \param[in] i2c_periph: I2Cx(x=0,1,2) + \param[out] none + \retval none +*/ +void i2c_dualaddr_disable(uint32_t i2c_periph) +{ + I2C_SADDR1(i2c_periph) &= ~(I2C_SADDR1_DUADEN); +} + +/*! + \brief enable I2C + \param[in] i2c_periph: I2Cx(x=0,1,2) \param[out] none \retval none */ @@ -230,15 +289,14 @@ void i2c_enable(uint32_t i2c_periph) } /*! - \brief disable i2c - \param[in] i2c_periph: I2Cx(x=0,1,2) + \brief disable I2C + \param[in] i2c_periph: I2Cx(x=0,1,2) \param[out] none \retval none */ void i2c_disable(uint32_t i2c_periph) { I2C_CTL0(i2c_periph) &= ~(I2C_CTL0_I2CEN); - } /*! @@ -264,91 +322,96 @@ void i2c_stop_on_bus(uint32_t i2c_periph) } /*! - \brief i2c transmit data function + \brief I2C transmit data function \param[in] i2c_periph: I2Cx(x=0,1,2) - \param[in] data: data of transmission + \param[in] data: data of transmission \param[out] none \retval none */ -void i2c_transmit_data(uint32_t i2c_periph,uint8_t data) +void i2c_data_transmit(uint32_t i2c_periph, uint8_t data) { - I2C_DATA(i2c_periph) = data; + I2C_DATA(i2c_periph) = DATA_TRANS(data); } /*! - \brief i2c receive data function + \brief I2C receive data function \param[in] i2c_periph: I2Cx(x=0,1,2) \param[out] none \retval data of received */ -uint8_t i2c_receive_data(uint32_t i2c_periph) +uint8_t i2c_data_receive(uint32_t i2c_periph) { - return (uint8_t)I2C_DATA(i2c_periph); + return (uint8_t)DATA_RECV(I2C_DATA(i2c_periph)); } /*! - \brief I2C DMA mode enable + \brief enable I2C DMA mode \param[in] i2c_periph: I2Cx(x=0,1,2) - \param[in] dmastste: - \arg I2C_DMA_ON: DMA mode enabled - \arg I2C_DMA_OFF: DMA mode disabled + \param[in] dmastate: + only one parameter can be selected which is shown as below: + \arg I2C_DMA_ON: DMA mode enable + \arg I2C_DMA_OFF: DMA mode disable \param[out] none \retval none */ -void i2c_dma_enable(uint32_t i2c_periph,uint32_t dmastste) +void i2c_dma_enable(uint32_t i2c_periph, uint32_t dmastate) { - /* configure i2c DMA function */ + /* configure I2C DMA function */ uint32_t ctl = 0U; + ctl = I2C_CTL1(i2c_periph); - ctl &= ~(I2C_CTL1_DMAON); - ctl |= dmastste; + ctl &= ~(I2C_CTL1_DMAON); + ctl |= dmastate; I2C_CTL1(i2c_periph) = ctl; - } /*! - \brief flag indicating DMA last transfer + \brief configure whether next DMA EOT is DMA last transfer or not \param[in] i2c_periph: I2Cx(x=0,1,2) - \param[in] dmastste: + \param[in] dmalast: + only one parameter can be selected which is shown as below: \arg I2C_DMALST_ON: next DMA EOT is the last transfer \arg I2C_DMALST_OFF: next DMA EOT is not the last transfer \param[out] none \retval none */ -void i2c_dma_last_transfer_enable(uint32_t i2c_periph,uint32_t dmalast) +void i2c_dma_last_transfer_config(uint32_t i2c_periph, uint32_t dmalast) { /* configure DMA last transfer */ uint32_t ctl = 0U; + ctl = I2C_CTL1(i2c_periph); - ctl &= ~(I2C_CTL1_DMALST); + ctl &= ~(I2C_CTL1_DMALST); ctl |= dmalast; I2C_CTL1(i2c_periph) = ctl; - } /*! - \brief whether to stretch SCL low when data is not ready in slave mode + \brief whether to stretch SCL low when data is not ready in slave mode \param[in] i2c_periph: I2Cx(x=0,1,2) \param[in] stretchpara: + only one parameter can be selected which is shown as below: \arg I2C_SCLSTRETCH_ENABLE: SCL stretching is enabled \arg I2C_SCLSTRETCH_DISABLE: SCL stretching is disabled \param[out] none \retval none */ -void i2c_stretch_scl_low_config(uint32_t i2c_periph,uint32_t stretchpara) +void i2c_stretch_scl_low_config(uint32_t i2c_periph, uint32_t stretchpara) { /* configure I2C SCL strerching enable or disable */ uint32_t ctl = 0U; + ctl = I2C_CTL0(i2c_periph); - ctl &= ~(I2C_CTL0_DISSTRC); + ctl &= ~(I2C_CTL0_SS); ctl |= stretchpara; I2C_CTL0(i2c_periph) = ctl; } /*! - \brief whether or not to response to a general Cal + \brief whether or not to response to a general call \param[in] i2c_periph: I2Cx(x=0,1,2) \param[in] gcallpara: + only one parameter can be selected which is shown as below: \arg I2C_GCEN_ENABLE: slave will response to a general call \arg I2C_GCEN_DISABLE: slave will not response to a general call \param[out] none @@ -358,16 +421,18 @@ void i2c_slave_response_to_gcall_config(uint32_t i2c_periph, uint32_t gcallpara) { /* configure slave response to a general call enable or disable */ uint32_t ctl = 0U; + ctl = I2C_CTL0(i2c_periph); - ctl &= ~(I2C_CTL0_GCEN); + ctl &= ~(I2C_CTL0_GCEN); ctl |= gcallpara; I2C_CTL0(i2c_periph) = ctl; } /*! - \brief software reset I2C + \brief software reset I2C \param[in] i2c_periph: I2Cx(x=0,1,2) \param[in] sreset: + only one parameter can be selected which is shown as below: \arg I2C_SRESET_SET: I2C is under reset \arg I2C_SRESET_RESET: I2C is not under reset \param[out] none @@ -377,134 +442,30 @@ void i2c_software_reset_config(uint32_t i2c_periph, uint32_t sreset) { /* modify CTL0 and configure software reset I2C state */ uint32_t ctl = 0U; + ctl = I2C_CTL0(i2c_periph); - ctl &= ~(I2C_CTL0_SRESET); + ctl &= ~(I2C_CTL0_SRESET); ctl |= sreset; I2C_CTL0(i2c_periph) = ctl; } /*! - \brief check i2c state - \param[in] i2c_periph: I2Cx(x=0,1,2) - \param[in] state: - \arg I2C_SBSEND: start condition send out - \arg I2C_ADDSEND: address is sent in master mode or received and matches in slave mode - \arg I2C_BTC: byte transmission finishes - \arg I2C_ADD10SEND: header of 10-bit address is sent in master mode - \arg I2C_STPDET: etop condition detected in slave mode - \arg I2C_RBNE: I2C_DATA is not Empty during receiving - \arg I2C_TBE: I2C_DATA is empty during transmitting - \arg I2C_BERR: a bus error occurs indication a unexpected start or stop condition on I2C bus - \arg I2C_LOSTARB: arbitration lost in master mode - \arg I2C_AERR: acknowledge error - \arg I2C_OUERR: over-run or under-run situation occurs in slave mode - \arg I2C_PECERR: PEC error when receiving data - \arg I2C_SMBTO: timeout signal in SMBus mode - \arg I2C_SMBALT: SMBus alert status - \arg I2C_MASTER: a flag indicating whether I2C block is in master or slave mode - \arg I2C_I2CBSY: busy flag - \arg I2C_TRS: whether the I2C is a transmitter or a receiver - \arg I2C_RXGC: general call address (00h) received - \arg I2C_DEFSMB: default address of SMBus device - \arg I2C_HSTSMB: SMBus host header detected in slave mode - \arg I2C_DUMODF: dual flag in slave mode indicating which address is matched in dual-address mode - \param[out] none - \retval state of i2c -*/ -FlagStatus i2c_flag_get(uint32_t i2c_periph,uint32_t state ) -{ - uint32_t reg = 0U; - FlagStatus regstate = RESET; - /* get the state in which register */ - reg = (BIT(31) & state); - if((BIT(31) == reg)){ - if((I2C_STAT1(i2c_periph)&(state & I2C_STATE_MASK))){ - regstate = SET; - }else{ - regstate = RESET; - } - }else{ - if((I2C_STAT0(i2c_periph)&(state & I2C_STATE_MASK))){ - regstate = SET; - }else{ - regstate = RESET; - } - } - /* return the state */ - return regstate; -} - -/*! - \brief clear i2c state - \param[in] i2c_periph: I2Cx(x=0,1,2) - \param[in] state: state type - \@arg I2C_STAT0_SMBALT: SMBus Alert status - \@arg I2C_STAT0_SMBTO: timeout signal in SMBus mode - \@arg I2C_STAT0_PECERR: PEC error when receiving data - \@arg I2C_STAT0_OUERR: over-run or under-run situation occurs in slave mode - \@arg I2C_STAT0_AERR: acknowledge error - \@arg I2C_STAT0_LOSTARB: arbitration lost in master mode - \@arg I2C_STAT0_BERR: a bus error - \@arg I2C_STAT0_ADDSEND: cleared by reading I2C_STAT0 and reading I2C_STAT1 - \param[out] none - \retval none -*/ -void i2c_flag_clear(uint32_t i2c_periph,uint32_t state) -{ - if(I2C_STAT0_ADDSEND == state){ - /* read I2C_STAT0 and then read I2C_STAT1 to clear ADDSEND */ - I2C_STAT0(i2c_periph); - I2C_STAT1(i2c_periph); - }else{ - I2C_STAT0(i2c_periph) &= ~(state); - } -} - -/*! - \brief enable i2c interrupt - \param[in] i2c_periph: I2Cx(x=0,1,2) - \param[in] inttype: interrupt type - \arg I2C_CTL1_ERRIE: error interrupt enable - \arg I2C_CTL1_EVIE: event interrupt enable - \arg I2C_CTL1_BUFIE: buffer interrupt enable - \param[out] none - \retval none -*/ -void i2c_interrupt_enable(uint32_t i2c_periph,uint32_t inttype) -{ - I2C_CTL1(i2c_periph) |= (inttype); -} - -/*! - \brief disable i2c interrupt - \param[in] i2c_periph: I2Cx(x=0,1,2) - \param[in] inttype: interrupt type - \arg I2C_CTL1_ERRIE: error interrupt enable - \arg I2C_CTL1_EVIE: event interrupt enable - \arg I2C_CTL1_BUFIE: buffer interrupt enable - \param[out] none - \retval none -*/ -void i2c_interrupt_disable(uint32_t i2c_periph,uint32_t inttype) -{ - I2C_CTL1(i2c_periph) &= ~(inttype); -} - -/*! \brief I2C PEC calculation on or off \param[in] i2c_periph: I2Cx(x=0,1,2) - \param[in] pecpara: - \arg I2C_PEC_ENABLE: PEC calculation on - \arg I2C_PEC_DISABLE: PEC calculation off + \param[in] pecstate: + only one parameter can be selected which is shown as below: + \arg I2C_PEC_ENABLE: PEC calculation on + \arg I2C_PEC_DISABLE: PEC calculation off \param[out] none \retval none */ -void i2c_pec_enable(uint32_t i2c_periph,uint32_t pecstate) +void i2c_pec_enable(uint32_t i2c_periph, uint32_t pecstate) { /* on/off PEC calculation */ uint32_t ctl = 0U; + ctl = I2C_CTL0(i2c_periph); - ctl &= ~(I2C_CTL0_PECEN); + ctl &= ~(I2C_CTL0_PECEN); ctl |= pecstate; I2C_CTL0(i2c_periph) = ctl; } @@ -513,66 +474,72 @@ void i2c_pec_enable(uint32_t i2c_periph,uint32_t pecstate) \brief I2C whether to transfer PEC value \param[in] i2c_periph: I2Cx(x=0,1,2) \param[in] pecpara: - \arg I2C_PECTRANS_ENABLE: transfer PEC - \arg I2C_PECTRANS_DISABLE: not transfer PEC + only one parameter can be selected which is shown as below: + \arg I2C_PECTRANS_ENABLE: transfer PEC + \arg I2C_PECTRANS_DISABLE: not transfer PEC \param[out] none \retval none */ -void i2c_pec_transfer_enable(uint32_t i2c_periph,uint32_t pecpara) +void i2c_pec_transfer_enable(uint32_t i2c_periph, uint32_t pecpara) { /* whether to transfer PEC */ uint32_t ctl = 0U; + ctl = I2C_CTL0(i2c_periph); - ctl &= ~(I2C_CTL0_PECTRANS); + ctl &= ~(I2C_CTL0_PECTRANS); ctl |= pecpara; I2C_CTL0(i2c_periph) = ctl; } /*! - \brief packet error checking value + \brief get packet error checking value \param[in] i2c_periph: I2Cx(x=0,1,2) \param[out] none \retval PEC value */ -uint8_t i2c_pec_value(uint32_t i2c_periph) +uint8_t i2c_pec_value_get(uint32_t i2c_periph) { - return (uint8_t)((I2C_STAT1(i2c_periph) &I2C_STAT1_ECV)>>8); + return (uint8_t)((I2C_STAT1(i2c_periph) & I2C_STAT1_PECV)>>STAT1_PECV_OFFSET); } /*! - \brief I2C issue alert through SMBA pin + \brief I2C issue alert through SMBA pin \param[in] i2c_periph: I2Cx(x=0,1,2) \param[in] smbuspara: - \arg I2C_SALTSEND_ENABLE: issue alert through SMBA pin - \arg I2C_SALTSEND_DISABLE: not issue alert through SMBA pin + only one parameter can be selected which is shown as below: + \arg I2C_SALTSEND_ENABLE: issue alert through SMBA pin + \arg I2C_SALTSEND_DISABLE: not issue alert through SMBA pin \param[out] none \retval none */ -void i2c_smbus_alert_issue(uint32_t i2c_periph,uint32_t smbuspara) +void i2c_smbus_issue_alert(uint32_t i2c_periph, uint32_t smbuspara) { /* issue alert through SMBA pin configure*/ uint32_t ctl = 0U; + ctl = I2C_CTL0(i2c_periph); - ctl &= ~(I2C_CTL0_SALT); + ctl &= ~(I2C_CTL0_SALT); ctl |= smbuspara; I2C_CTL0(i2c_periph) = ctl; } /*! - \brief I2C ARP protocol in SMBus switch enable or disable + \brief enable or disable I2C ARP protocol in SMBus switch \param[in] i2c_periph: I2Cx(x=0,1,2) - \param[in] smbuspara: - \arg I2C_ARP_ENABLE: ARP is enabled - \arg I2C_ARP_DISABLE: ARP is disabled + \param[in] arpstate: + only one parameter can be selected which is shown as below: + \arg I2C_ARP_ENABLE: enable ARP + \arg I2C_ARP_DISABLE: disable ARP \param[out] none \retval none */ -void i2c_smbus_arp_enable(uint32_t i2c_periph,uint32_t arpstate) +void i2c_smbus_arp_enable(uint32_t i2c_periph, uint32_t arpstate) { /* enable or disable I2C ARP protocol*/ uint32_t ctl = 0U; + ctl = I2C_CTL0(i2c_periph); - ctl &= ~(I2C_CTL0_ARPEN); + ctl &= ~(I2C_CTL0_ARPEN); ctl |= arpstate; I2C_CTL0(i2c_periph) = ctl; } @@ -585,7 +552,7 @@ void i2c_smbus_arp_enable(uint32_t i2c_periph,uint32_t arpstate) */ void i2c_analog_noise_filter_disable(uint32_t i2c_periph) { - I2C_FCTL(i2c_periph) |= I2C_FCTL_AFD; + I2C_FCTL(i2c_periph) |= I2C_FCTL_AFD; } /*! @@ -596,19 +563,19 @@ void i2c_analog_noise_filter_disable(uint32_t i2c_periph) */ void i2c_analog_noise_filter_enable(uint32_t i2c_periph) { - I2C_FCTL(i2c_periph) &= ~(I2C_FCTL_AFD); + I2C_FCTL(i2c_periph) &= ~(I2C_FCTL_AFD); } /*! \brief digital noise filter configuration \param[in] i2c_periph: I2Cx(x=0,1,2) - \param[in] dfilterpara: refer to enum i2c_gcall_config_enum + \param[in] dfilterpara: refer to enum i2c_digital_filter_enum \param[out] none \retval none */ void i2c_digital_noise_filter_config(uint32_t i2c_periph,i2c_digital_filter_enum dfilterpara) { - I2C_FCTL(i2c_periph) |= dfilterpara; + I2C_FCTL(i2c_periph) |= dfilterpara; } /*! @@ -619,7 +586,7 @@ void i2c_digital_noise_filter_config(uint32_t i2c_periph,i2c_digital_filter_enum */ void i2c_sam_enable(uint32_t i2c_periph) { - I2C_SAMCS(i2c_periph) |= I2C_SAMCS_SAMEN; + I2C_SAMCS(i2c_periph) |= I2C_SAMCS_SAMEN; } /*! @@ -630,7 +597,7 @@ void i2c_sam_enable(uint32_t i2c_periph) */ void i2c_sam_disable(uint32_t i2c_periph) { - I2C_SAMCS(i2c_periph) &= ~(I2C_SAMCS_SAMEN); + I2C_SAMCS(i2c_periph) &= ~(I2C_SAMCS_SAMEN); } /*! @@ -641,7 +608,7 @@ void i2c_sam_disable(uint32_t i2c_periph) */ void i2c_sam_timeout_enable(uint32_t i2c_periph) { - I2C_SAMCS(i2c_periph) |= I2C_SAMCS_STOEN; + I2C_SAMCS(i2c_periph) |= I2C_SAMCS_STOEN; } /*! @@ -652,79 +619,201 @@ void i2c_sam_timeout_enable(uint32_t i2c_periph) */ void i2c_sam_timeout_disable(uint32_t i2c_periph) { - I2C_SAMCS(i2c_periph) &= ~(I2C_SAMCS_STOEN); + I2C_SAMCS(i2c_periph) &= ~(I2C_SAMCS_STOEN); +} + +/*! + \brief check I2C flag is set or not + \param[in] i2c_periph: I2Cx(x=0,1,2) + \param[in] flag: I2C flags, refer to i2c_flag_enum + only one parameter can be selected which is shown as below: + \arg I2C_FLAG_SBSEND: start condition send out + \arg I2C_FLAG_ADDSEND: address is sent in master mode or received and matches in slave mode + \arg I2C_FLAG_BTC: byte transmission finishes + \arg I2C_FLAG_ADD10SEND: header of 10-bit address is sent in master mode + \arg I2C_FLAG_STPDET: stop condition detected in slave mode + \arg I2C_FLAG_RBNE: I2C_DATA is not Empty during receiving + \arg I2C_FLAG_TBE: I2C_DATA is empty during transmitting + \arg I2C_FLAG_BERR: a bus error occurs indication a unexpected start or stop condition on I2C bus + \arg I2C_FLAG_LOSTARB: arbitration lost in master mode + \arg I2C_FLAG_AERR: acknowledge error + \arg I2C_FLAG_OUERR: overrun or underrun situation occurs in slave mode + \arg I2C_FLAG_PECERR: PEC error when receiving data + \arg I2C_FLAG_SMBTO: timeout signal in SMBus mode + \arg I2C_FLAG_SMBALT: SMBus alert status + \arg I2C_FLAG_MASTER: a flag indicating whether I2C block is in master or slave mode + \arg I2C_FLAG_I2CBSY: busy flag + \arg I2C_FLAG_TRS: whether the I2C is a transmitter or a receiver + \arg I2C_FLAG_RXGC: general call address (00h) received + \arg I2C_FLAG_DEFSMB: default address of SMBus device + \arg I2C_FLAG_HSTSMB: SMBus host header detected in slave mode + \arg I2C_FLAG_DUMOD: dual flag in slave mode indicating which address is matched in dual-address mode + \arg I2C_FLAG_TFF: txframe fall flag + \arg I2C_FLAG_TFR: txframe rise flag + \arg I2C_FLAG_RFF: rxframe fall flag + \arg I2C_FLAG_RFR: rxframe rise flag + \param[out] none + \retval FlagStatus: SET or RESET +*/ +FlagStatus i2c_flag_get(uint32_t i2c_periph, i2c_flag_enum flag) +{ + if(RESET != (I2C_REG_VAL(i2c_periph, flag) & BIT(I2C_BIT_POS(flag)))){ + return SET; + }else{ + return RESET; + } +} + +/*! + \brief clear I2C flag + \param[in] i2c_periph: I2Cx(x=0,1,2) + \param[in] flag: I2C flags, refer to i2c_flag_enum + only one parameter can be selected which is shown as below: + \arg I2C_FLAG_SMBALT: SMBus Alert status + \arg I2C_FLAG_SMBTO: timeout signal in SMBus mode + \arg I2C_FLAG_PECERR: PEC error when receiving data + \arg I2C_FLAG_OUERR: over-run or under-run situation occurs in slave mode + \arg I2C_FLAG_AERR: acknowledge error + \arg I2C_FLAG_LOSTARB: arbitration lost in master mode + \arg I2C_FLAG_BERR: a bus error + \arg I2C_FLAG_ADDSEND: cleared by reading I2C_STAT0 and reading I2C_STAT1 + \arg I2C_FLAG_TFF: txframe fall flag + \arg I2C_FLAG_TFR: txframe rise flag + \arg I2C_FLAG_RFF: rxframe fall flag + \arg I2C_FLAG_RFR: rxframe rise flag + \param[out] none + \retval none +*/ +void i2c_flag_clear(uint32_t i2c_periph, i2c_flag_enum flag) +{ + if(I2C_FLAG_ADDSEND == flag){ + /* read I2C_STAT0 and then read I2C_STAT1 to clear ADDSEND */ + I2C_STAT0(i2c_periph); + I2C_STAT1(i2c_periph); + }else{ + I2C_REG_VAL(i2c_periph, flag) &= ~BIT(I2C_BIT_POS(flag)); + } } /*! - \brief enable the specified I2C SAM interrupt + \brief enable I2C interrupt \param[in] i2c_periph: I2Cx(x=0,1,2) - \param[in] inttype: interrupt type - \@arg I2C_SAMCS_TFFIE: txframe fall interrupt - \@arg I2C_SAMCS_TFRIE: txframe rise interrupt - \@arg I2C_SAMCS_RFFIE: rxframe fall interrupt - \@arg I2C_SAMCS_RFRIE: rxframe rise interrupt - \param[out] none - \retval none + \param[in] interrupt: I2C interrupts, refer to i2c_interrupt_enum + only one parameter can be selected which is shown as below: + \arg I2C_INT_ERR: error interrupt enable + \arg I2C_INT_EV: event interrupt enable + \arg I2C_INT_BUF: buffer interrupt enable + \arg I2C_INT_TFF: txframe fall interrupt enable + \arg I2C_INT_TFR: txframe rise interrupt enable + \arg I2C_INT_RFF: rxframe fall interrupt enable + \arg I2C_INT_RFR: rxframe rise interrupt enable + \param[out] none + \retval none */ -void i2c_sam_interrupt_enable(uint32_t i2c_periph,uint32_t inttype) +void i2c_interrupt_enable(uint32_t i2c_periph, i2c_interrupt_enum interrupt) { - I2C_SAMCS(i2c_periph) |= (inttype); + I2C_REG_VAL(i2c_periph, interrupt) |= BIT(I2C_BIT_POS(interrupt)); } /*! - \brief disable i2c interrupt + \brief disable I2C interrupt \param[in] i2c_periph: I2Cx(x=0,1,2) - \param[in] inttype: interrupt type - \@arg I2C_SAMCS_TFFIE: txframe fall interrupt - \@arg I2C_SAMCS_TFRIE: txframe rise interrupt - \@arg I2C_SAMCS_RFFIE: rxframe fall interrupt - \@arg I2C_SAMCS_RFRIE: rxframe rise interrupt + \param[in] interrupt: I2C interrupts, refer to i2c_flag_enum + only one parameter can be selected which is shown as below: + \arg I2C_INT_ERR: error interrupt enable + \arg I2C_INT_EV: event interrupt enable + \arg I2C_INT_BUF: buffer interrupt enable + \arg I2C_INT_TFF: txframe fall interrupt enable + \arg I2C_INT_TFR: txframe rise interrupt enable + \arg I2C_INT_RFF: rxframe fall interrupt enable + \arg I2C_INT_RFR: rxframe rise interrupt enable \param[out] none \retval none */ -void i2c_sam_interrupt_disable(uint32_t i2c_periph,uint32_t inttype) +void i2c_interrupt_disable(uint32_t i2c_periph, i2c_interrupt_enum interrupt) { - I2C_SAMCS(i2c_periph) &= ~(inttype); + I2C_REG_VAL(i2c_periph, interrupt) &= ~BIT(I2C_BIT_POS(interrupt)); } /*! - \brief check i2c SAM state + \brief check I2C interrupt flag \param[in] i2c_periph: I2Cx(x=0,1,2) - \param[in] samstate: state type - \@arg I2C_SAMCS_TXF: level of txframe signal - \@arg I2C_SAMCS_RXF: level of rxframe signal - \@arg I2C_SAMCS_TFF: txframe fall flag - \@arg I2C_SAMCS_TFR: txframe rise flag - \@arg I2C_SAMCS_RFF: rxframe fall flag - \@arg I2C_SAMCS_RFR: rxframe rise flag + \param[in] int_flag: I2C interrupt flags, refer to i2c_interrupt_flag_enum + only one parameter can be selected which is shown as below: + \arg I2C_INT_FLAG_SBSEND: start condition sent out in master mode interrupt flag + \arg I2C_INT_FLAG_ADDSEND: address is sent in master mode or received and matches in slave mode interrupt flag + \arg I2C_INT_FLAG_BTC: byte transmission finishes + \arg I2C_INT_FLAG_ADD10SEND: header of 10-bit address is sent in master mode interrupt flag + \arg I2C_INT_FLAG_STPDET: etop condition detected in slave mode interrupt flag + \arg I2C_INT_FLAG_RBNE: I2C_DATA is not Empty during receiving interrupt flag + \arg I2C_INT_FLAG_TBE: I2C_DATA is empty during transmitting interrupt flag + \arg I2C_INT_FLAG_BERR: a bus error occurs indication a unexpected start or stop condition on I2C bus interrupt flag + \arg I2C_INT_FLAG_LOSTARB: arbitration lost in master mode interrupt flag + \arg I2C_INT_FLAG_AERR: acknowledge error interrupt flag + \arg I2C_INT_FLAG_OUERR: over-run or under-run situation occurs in slave mode interrupt flag + \arg I2C_INT_FLAG_PECERR: PEC error when receiving data interrupt flag + \arg I2C_INT_FLAG_SMBTO: timeout signal in SMBus mode interrupt flag + \arg I2C_INT_FLAG_SMBALT: SMBus Alert status interrupt flag + \arg I2C_INT_FLAG_TFF: txframe fall interrupt flag + \arg I2C_INT_FLAG_TFR: txframe rise interrupt flag + \arg I2C_INT_FLAG_RFF: rxframe fall interrupt flag + \arg I2C_INT_FLAG_RFR: rxframe rise interrupt flag \param[out] none - \retval state of i2c SAM + \retval FlagStatus: SET or RESET */ -FlagStatus i2c_sam_flag_get(uint32_t i2c_periph,uint32_t samstate) +FlagStatus i2c_interrupt_flag_get(uint32_t i2c_periph, i2c_interrupt_flag_enum int_flag) { - FlagStatus reg = RESET; - if(I2C_SAMCS(i2c_periph)&samstate){ - reg =SET; + uint32_t intenable = 0U, flagstatus = 0U, bufie; + + /* check BUFIE */ + bufie = I2C_CTL1(i2c_periph)&I2C_CTL1_BUFIE; + + /* get the interrupt enable bit status */ + intenable = (I2C_REG_VAL(i2c_periph, int_flag) & BIT(I2C_BIT_POS(int_flag))); + /* get the corresponding flag bit status */ + flagstatus = (I2C_REG_VAL2(i2c_periph, int_flag) & BIT(I2C_BIT_POS2(int_flag))); + + if((I2C_INT_FLAG_RBNE == int_flag) || (I2C_INT_FLAG_TBE == int_flag)){ + if(intenable && bufie){ + intenable = 1U; + }else{ + intenable = 0U; + } + } + if((0U != flagstatus) && (0U != intenable)){ + return SET; }else{ - reg =RESET; + return RESET; } - return reg; } /*! - \brief clear i2c SAM state + \brief clear I2C interrupt flag \param[in] i2c_periph: I2Cx(x=0,1,2) - \param[in] samstate: state type - \@arg I2C_SAMCS_TFF: txframe fall flag - \@arg I2C_SAMCS_TFR: txframe rise flag - \@arg I2C_SAMCS_RFF: rxframe fall flag - \@arg I2C_SAMCS_RFR: rxframe rise flag + \param[in] int_flag: I2C interrupt flags, refer to i2c_interrupt_flag_enum + only one parameter can be selected which is shown as below: + \arg I2C_INT_FLAG_ADDSEND: address is sent in master mode or received and matches in slave mode interrupt flag + \arg I2C_INT_FLAG_BERR: a bus error occurs indication a unexpected start or stop condition on I2C bus interrupt flag + \arg I2C_INT_FLAG_LOSTARB: arbitration lost in master mode interrupt flag + \arg I2C_INT_FLAG_AERR: acknowledge error interrupt flag + \arg I2C_INT_FLAG_OUERR: over-run or under-run situation occurs in slave mode interrupt flag + \arg I2C_INT_FLAG_PECERR: PEC error when receiving data interrupt flag + \arg I2C_INT_FLAG_SMBTO: timeout signal in SMBus mode interrupt flag + \arg I2C_INT_FLAG_SMBALT: SMBus Alert status interrupt flag + \arg I2C_INT_FLAG_TFF: txframe fall interrupt flag + \arg I2C_INT_FLAG_TFR: txframe rise interrupt flag + \arg I2C_INT_FLAG_RFF: rxframe fall interrupt flag + \arg I2C_INT_FLAG_RFR: rxframe rise interrupt flag \param[out] none \retval none */ -void i2c_sam_flag_clear(uint32_t i2c_periph,uint32_t samstate) +void i2c_interrupt_flag_clear(uint32_t i2c_periph, i2c_interrupt_flag_enum int_flag) { - I2C_SAMCS(i2c_periph) &= ~(samstate); - + if(I2C_INT_FLAG_ADDSEND == int_flag){ + /* read I2C_STAT0 and then read I2C_STAT1 to clear ADDSEND */ + I2C_STAT0(i2c_periph); + I2C_STAT1(i2c_periph); + }else{ + I2C_REG_VAL2(i2c_periph, int_flag) &= ~BIT(I2C_BIT_POS2(int_flag)); + } } - diff --git a/bsp/gd32450z-eval/Libraries/GD32F4xx_standard_peripheral/Source/gd32f4xx_ipa.c b/bsp/gd32450z-eval/Libraries/GD32F4xx_standard_peripheral/Source/gd32f4xx_ipa.c index d50b473ab9..5afcc48e0d 100644 --- a/bsp/gd32450z-eval/Libraries/GD32F4xx_standard_peripheral/Source/gd32f4xx_ipa.c +++ b/bsp/gd32450z-eval/Libraries/GD32F4xx_standard_peripheral/Source/gd32f4xx_ipa.c @@ -1,30 +1,57 @@ /*! - \file gd32f4xx_ipa.c - \brief IPA driver + \file gd32f4xx_ipa.c + \brief IPA driver + + \version 2016-08-15, V1.0.0, firmware for GD32F4xx + \version 2018-12-12, V2.0.0, firmware for GD32F4xx + \version 2020-09-30, V2.1.0, firmware for GD32F4xx */ /* - Copyright (C) 2016 GigaDevice + Copyright (c) 2020, GigaDevice Semiconductor Inc. + + Redistribution and use in source and binary forms, with or without modification, +are permitted provided that the following conditions are met: + + 1. Redistributions of source code must retain the above copyright notice, this + list of conditions and the following disclaimer. + 2. Redistributions in binary form must reproduce the above copyright notice, + this list of conditions and the following disclaimer in the documentation + and/or other materials provided with the distribution. + 3. Neither the name of the copyright holder nor the names of its contributors + may be used to endorse or promote products derived from this software without + specific prior written permission. - 2016-08-15, V1.0.0, firmware for GD32F4xx + THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED +WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. +IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, +INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT +NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR +PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, +WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY +OF SUCH DAMAGE. */ #include "gd32f4xx_ipa.h" +#define IPA_DEFAULT_VALUE 0x00000000U + /*! - \brief deinitialize IPA registers + \brief deinitialize IPA registers \param[in] none \param[out] none \retval none */ void ipa_deinit(void) { - rcu_periph_reset_enable(RCU_IPAENRST); - rcu_periph_reset_disable(RCU_IPAENRST); + rcu_periph_reset_enable(RCU_IPARST); + rcu_periph_reset_disable(RCU_IPARST); } /*! - \brief IPA transfer enable + \brief enable IPA transfer \param[in] none \param[out] none \retval none @@ -35,8 +62,8 @@ void ipa_transfer_enable(void) } /*! - \brief IPA transfer hang up enable - \param[in] none. + \brief enable IPA transfer hang up + \param[in] none \param[out] none \retval none */ @@ -46,8 +73,8 @@ void ipa_transfer_hangup_enable(void) } /*! - \brief IPA transfer hang up disable - \param[in] none. + \brief disable IPA transfer hang up + \param[in] none \param[out] none \retval none */ @@ -57,8 +84,8 @@ void ipa_transfer_hangup_disable(void) } /*! - \brief IPA transfer stop enable - \param[in] none. + \brief enable IPA transfer stop + \param[in] none \param[out] none \retval none */ @@ -68,8 +95,8 @@ void ipa_transfer_stop_enable(void) } /*! - \brief IPA transfer stop disable - \param[in] none. + \brief disable IPA transfer stop + \param[in] none \param[out] none \retval none */ @@ -78,8 +105,8 @@ void ipa_transfer_stop_disable(void) IPA_CTL &= ~(IPA_CTL_TST); } /*! - \brief IPA foreground LUT loading enable - \param[in] none. + \brief enable IPA foreground LUT loading + \param[in] none \param[out] none \retval none */ @@ -89,8 +116,8 @@ void ipa_foreground_lut_loading_enable(void) } /*! - \brief IPA background LUT loading enable - \param[in] none. + \brief enable IPA background LUT loading + \param[in] none \param[out] none \retval none */ @@ -100,94 +127,217 @@ void ipa_background_lut_loading_enable(void) } /*! - \brief Pixel format convert mode - \param[in] pfcm: - \arg IPA_FGTODE: foreground memory to destination memory without pixel format convert - \arg IPA_FGTODE_PF_CONVERT: foreground memory to destination memory with pixel format convert - \arg IPA_FGBGTODE: blending foreground and background memory to destination memory - \arg IPA_FILL_UP_DE: fill up destination memory with specific color + \brief set pixel format convert mode, the function is invalid when the IPA transfer is enabled + \param[in] pfcm: pixel format convert mode + only one parameter can be selected which is shown as below: + \arg IPA_FGTODE: foreground memory to destination memory without pixel format convert + \arg IPA_FGTODE_PF_CONVERT: foreground memory to destination memory with pixel format convert + \arg IPA_FGBGTODE: blending foreground and background memory to destination memory + \arg IPA_FILL_UP_DE: fill up destination memory with specific color \param[out] none \retval none */ -void ipa_pixel_format_convert_mod(uint32_t pfcm) +void ipa_pixel_format_convert_mode_set(uint32_t pfcm) { IPA_CTL |= pfcm; } /*! - \brief initialize foreground parameters - \param[in] foreground_struct: the data needed to initialize fore. + \brief initialize the structure of IPA foreground parameter struct with the default values, it is + suggested that call this function after an ipa_foreground_parameter_struct structure is defined + \param[in] none + \param[out] foreground_struct: the data needed to initialize foreground + foreground_memaddr: foreground memory base address + foreground_lineoff: foreground line offset + foreground_prealpha: foreground pre-defined alpha value + foreground_alpha_algorithm: IPA_FG_ALPHA_MODE_0,IPA_FG_ALPHA_MODE_1,IPA_FG_ALPHA_MODE_2 + foreground_pf: foreground pixel format(FOREGROUND_PPF_ARGB8888,FOREGROUND_PPF_RGB888,FOREGROUND_PPF_RGB565, + FOREGROUND_PPF_ARG1555,FOREGROUND_PPF_ARGB4444,FOREGROUND_PPF_L8,FOREGROUND_PPF_AL44, + FOREGROUND_PPF_AL88,FOREGROUND_PPF_L4,FOREGROUND_PPF_A8,FOREGROUND_PPF_A4) + foreground_prered: foreground pre-defined red value + foreground_pregreen: foreground pre-defined green value + foreground_preblue: foreground pre-defined blue value + \retval none +*/ +void ipa_foreground_struct_para_init(ipa_foreground_parameter_struct* foreground_struct) +{ + /* initialize the struct parameters with default values */ + foreground_struct->foreground_memaddr = IPA_DEFAULT_VALUE; + foreground_struct->foreground_lineoff = IPA_DEFAULT_VALUE; + foreground_struct->foreground_prealpha = IPA_DEFAULT_VALUE; + foreground_struct->foreground_alpha_algorithm = IPA_FG_ALPHA_MODE_0; + foreground_struct->foreground_pf = FOREGROUND_PPF_ARGB8888; + foreground_struct->foreground_prered = IPA_DEFAULT_VALUE; + foreground_struct->foreground_pregreen = IPA_DEFAULT_VALUE; + foreground_struct->foreground_preblue = IPA_DEFAULT_VALUE; +} + +/*! + \brief initialize foreground parameters + \param[in] foreground_struct: the data needed to initialize foreground foreground_memaddr: foreground memory base address foreground_lineoff: foreground line offset - foreground_prealpha: foreground pre-defined alpha value + foreground_prealpha: foreground pre-defined alpha value foreground_alpha_algorithm: IPA_FG_ALPHA_MODE_0,IPA_FG_ALPHA_MODE_1,IPA_FG_ALPHA_MODE_2 - foreground_pf: foreground pixel format + foreground_pf: foreground pixel format(FOREGROUND_PPF_ARGB8888,FOREGROUND_PPF_RGB888,FOREGROUND_PPF_RGB565, + FOREGROUND_PPF_ARG1555,FOREGROUND_PPF_ARGB4444,FOREGROUND_PPF_L8,FOREGROUND_PPF_AL44, + FOREGROUND_PPF_AL88,FOREGROUND_PPF_L4,FOREGROUND_PPF_A8,FOREGROUND_PPF_A4) foreground_prered: foreground pre-defined red value - foreground_pregreen: foreground pre-defined green value + foreground_pregreen: foreground pre-defined green value foreground_preblue: foreground pre-defined blue value \param[out] none \retval none */ void ipa_foreground_init(ipa_foreground_parameter_struct* foreground_struct) { + FlagStatus tempflag = RESET; + if(RESET != (IPA_CTL & IPA_CTL_TEN)){ + tempflag = SET; + /* reset the TEN in order to configure the following bits */ + IPA_CTL &= ~IPA_CTL_TEN; + } + /* foreground memory base address configuration */ IPA_FMADDR &= ~(IPA_FMADDR_FMADDR); IPA_FMADDR = foreground_struct->foreground_memaddr; /* foreground line offset configuration */ IPA_FLOFF &= ~(IPA_FLOFF_FLOFF); IPA_FLOFF = foreground_struct->foreground_lineoff; - /* foreground pixel format pre-defined alpha, alpha calculation algorithm configuration */ - IPA_FPCTL &= ~(IPA_FPCTL_FAVCA|IPA_FPCTL_FAVCA|IPA_FPCTL_FPF); + /* foreground pixel format pre-defined alpha, alpha calculation algorithm configuration */ + IPA_FPCTL &= ~(IPA_FPCTL_FPDAV|IPA_FPCTL_FAVCA|IPA_FPCTL_FPF); IPA_FPCTL |= (foreground_struct->foreground_prealpha<<24U); IPA_FPCTL |= foreground_struct->foreground_alpha_algorithm; IPA_FPCTL |= foreground_struct->foreground_pf; - /* foreground pre-defined red green blue configuration */ + /* foreground pre-defined red green blue configuration */ IPA_FPV &= ~(IPA_FPV_FPDRV|IPA_FPV_FPDGV|IPA_FPV_FPDBV); - IPA_FPV |= ((foreground_struct->foreground_prered<<16U)|(foreground_struct->foreground_pregreen<<8U)|(foreground_struct->foreground_preblue)); + IPA_FPV |= ((foreground_struct->foreground_prered<<16U)|(foreground_struct->foreground_pregreen<<8U) + |(foreground_struct->foreground_preblue)); + + if(SET == tempflag){ + /* restore the state of TEN */ + IPA_CTL |= IPA_CTL_TEN; + } +} + +/*! + \brief initialize the structure of IPA background parameter struct with the default values, it is + suggested that call this function after an ipa_background_parameter_struct structure is defined + \param[in] none + \param[out] background_struct: the data needed to initialize background + background_memaddr: background memory base address + background_lineoff: background line offset + background_prealpha: background pre-defined alpha value + background_alpha_algorithm: IPA_BG_ALPHA_MODE_0,IPA_BG_ALPHA_MODE_1,IPA_BG_ALPHA_MODE_2 + background_pf: background pixel format(BACKGROUND_PPF_ARGB8888,BACKGROUND_PPF_RGB888,BACKGROUND_PPF_RGB565, + BACKGROUND_PPF_ARG1555,BACKGROUND_PPF_ARGB4444,BACKGROUND_PPF_L8,BACKGROUND_PPF_AL44, + BACKGROUND_PPF_AL88,BACKGROUND_PPF_L4,BACKGROUND_PPF_A8,BACKGROUND_PPF_A4) + background_prered: background pre-defined red value + background_pregreen: background pre-defined green value + background_preblue: background pre-defined blue value + \retval none +*/ +void ipa_background_struct_para_init(ipa_background_parameter_struct* background_struct) +{ + /* initialize the struct parameters with default values */ + background_struct->background_memaddr = IPA_DEFAULT_VALUE; + background_struct->background_lineoff = IPA_DEFAULT_VALUE; + background_struct->background_prealpha = IPA_DEFAULT_VALUE; + background_struct->background_alpha_algorithm = IPA_BG_ALPHA_MODE_0; + background_struct->background_pf = BACKGROUND_PPF_ARGB8888; + background_struct->background_prered = IPA_DEFAULT_VALUE; + background_struct->background_pregreen = IPA_DEFAULT_VALUE; + background_struct->background_preblue = IPA_DEFAULT_VALUE; } /*! - \brief initialize background parameters - \param[in] background_struct: the data needed to initialize fore. + \brief initialize background parameters + \param[in] background_struct: the data needed to initialize background background_memaddr: background memory base address background_lineoff: background line offset - background_prealpha: background pre-defined alpha value + background_prealpha: background pre-defined alpha value background_alpha_algorithm: IPA_BG_ALPHA_MODE_0,IPA_FG_ALPHA_MODE_1,IPA_FG_ALPHA_MODE_2 - background_pf: background pixel format + background_pf: background pixel format(BACKGROUND_PPF_ARGB8888,BACKGROUND_PPF_RGB888,BACKGROUND_PPF_RGB565, + BACKGROUND_PPF_ARG1555,BACKGROUND_PPF_ARGB4444,BACKGROUND_PPF_L8,BACKGROUND_PPF_AL44, + BACKGROUND_PPF_AL88,BACKGROUND_PPF_L4,BACKGROUND_PPF_A8,BACKGROUND_PPF_A4) background_prered: background pre-defined red value - background_pregreen: background pre-defined green value + background_pregreen: background pre-defined green value background_preblue: background pre-defined blue value \param[out] none \retval none */ void ipa_background_init(ipa_background_parameter_struct* background_struct) { + FlagStatus tempflag = RESET; + if(RESET != (IPA_CTL & IPA_CTL_TEN)){ + tempflag = SET; + /* reset the TEN in order to configure the following bits */ + IPA_CTL &= ~IPA_CTL_TEN; + } + /* background memory base address configuration */ IPA_BMADDR &= ~(IPA_BMADDR_BMADDR); IPA_BMADDR = background_struct->background_memaddr; /* background line offset configuration */ IPA_BLOFF &= ~(IPA_BLOFF_BLOFF); - IPA_BLOFF =background_struct->background_lineoff; - /* background pixel format pre-defined alpha, alpha calculation algorithm configuration */ - IPA_BPCTL &= ~(IPA_BPCTL_BAVCA|IPA_BPCTL_BAVCA|IPA_BPCTL_BPF); + IPA_BLOFF = background_struct->background_lineoff; + /* background pixel format pre-defined alpha, alpha calculation algorithm configuration */ + IPA_BPCTL &= ~(IPA_BPCTL_BPDAV|IPA_BPCTL_BAVCA|IPA_BPCTL_BPF); IPA_BPCTL |= (background_struct->background_prealpha<<24U); IPA_BPCTL |= background_struct->background_alpha_algorithm; - IPA_BPCTL |= background_struct->background_pf; - /* background pre-defined red green blue configuration */ + IPA_BPCTL |= background_struct->background_pf; + /* background pre-defined red green blue configuration */ IPA_BPV &= ~(IPA_BPV_BPDRV|IPA_BPV_BPDGV|IPA_BPV_BPDBV); - IPA_BPV |= ((background_struct->background_prered<<16U)|(background_struct->background_pregreen<<8U)|(background_struct->background_preblue)); + IPA_BPV |= ((background_struct->background_prered<<16U)|(background_struct->background_pregreen<<8U) + |(background_struct->background_preblue)); + + if(SET == tempflag){ + /* restore the state of TEN */ + IPA_CTL |= IPA_CTL_TEN; + } +} + +/*! + \brief initialize the structure of IPA destination parameter struct with the default values, it is + suggested that call this function after an ipa_destination_parameter_struct structure is defined + \param[in] none + \param[out] destination_struct: the data needed to initialize destination parameter + destination_pf: IPA_DPF_ARGB8888,IPA_DPF_RGB888,IPA_DPF_RGB565,IPA_DPF_ARGB1555, + IPA_DPF_ARGB4444,refer to ipa_dpf_enum + destination_lineoff: destination line offset + destination_prealpha: destination pre-defined alpha value + destination_prered: destination pre-defined red value + destination_pregreen: destination pre-defined green value + destination_preblue: destination pre-defined blue value + destination_memaddr: destination memory base address + image_width: width of the image to be processed + image_height: height of the image to be processed + \retval none +*/ +void ipa_destination_struct_para_init(ipa_destination_parameter_struct* destination_struct) +{ + /* initialize the struct parameters with default values */ + destination_struct->destination_pf = IPA_DPF_ARGB8888; + destination_struct->destination_lineoff = IPA_DEFAULT_VALUE; + destination_struct->destination_prealpha = IPA_DEFAULT_VALUE; + destination_struct->destination_prered = IPA_DEFAULT_VALUE; + destination_struct->destination_pregreen = IPA_DEFAULT_VALUE; + destination_struct->destination_preblue = IPA_DEFAULT_VALUE; + destination_struct->destination_memaddr = IPA_DEFAULT_VALUE; + destination_struct->image_width = IPA_DEFAULT_VALUE; + destination_struct->image_height = IPA_DEFAULT_VALUE; } /*! - \brief initialize destination parameters - \param[in] destination_struct: the data needed to initialize tli. - destination_pf: refer to ipa_dpf_enum + \brief initialize destination parameters + \param[in] destination_struct: the data needed to initialize destination parameters + destination_pf: IPA_DPF_ARGB8888,IPA_DPF_RGB888,IPA_DPF_RGB565,IPA_DPF_ARGB1555, + IPA_DPF_ARGB4444,refer to ipa_dpf_enum destination_lineoff: destination line offset - destination_prealpha: destination pre-defined alpha value + destination_prealpha: destination pre-defined alpha value destination_prered: destination pre-defined red value destination_pregreen: destination pre-defined green value destination_preblue: destination pre-defined blue value - destination_memaddr: destination memory base address + destination_memaddr: destination memory base address image_width: width of the image to be processed image_height: height of the image to be processed \param[out] none @@ -196,6 +346,13 @@ void ipa_background_init(ipa_background_parameter_struct* background_struct) void ipa_destination_init(ipa_destination_parameter_struct* destination_struct) { uint32_t destination_pixelformat; + FlagStatus tempflag = RESET; + if(RESET != (IPA_CTL & IPA_CTL_TEN)){ + tempflag = SET; + /* reset the TEN in order to configure the following bits */ + IPA_CTL &= ~IPA_CTL_TEN; + } + /* destination pixel format configuration */ IPA_DPCTL &= ~(IPA_DPCTL_DPF); IPA_DPCTL = destination_struct->destination_pf; @@ -230,36 +387,48 @@ void ipa_destination_init(ipa_destination_parameter_struct* destination_struct) /* destination pixel format ARGB4444 */ case IPA_DPF_ARGB4444: IPA_DPV &= ~(IPA_DPV_DPDBV_4|(IPA_DPV_DPDGV_4)|(IPA_DPV_DPDRV_4)|(IPA_DPV_DPDAV_4)); - IPA_DPV = (destination_struct->destination_preblue|(destination_struct->destination_pregreen<<5U) - |(destination_struct->destination_prered<<10U) - |(destination_struct->destination_prealpha<<15U)); + IPA_DPV = (destination_struct->destination_preblue|(destination_struct->destination_pregreen<<4U) + |(destination_struct->destination_prered<<8U) + |(destination_struct->destination_prealpha<<12U)); break; default: break; } /* destination memory base address configuration */ IPA_DMADDR &= ~(IPA_DMADDR_DMADDR); - IPA_DMADDR =destination_struct->destination_memaddr; - /* destination line offset configuration */ + IPA_DMADDR = destination_struct->destination_memaddr; + /* destination line offset configuration */ IPA_DLOFF &= ~(IPA_DLOFF_DLOFF); IPA_DLOFF =destination_struct->destination_lineoff; - /* image size configuration */ + /* image size configuration */ IPA_IMS &= ~(IPA_IMS_HEIGHT|IPA_IMS_WIDTH); - IPA_IMS |= ((destination_struct->image_width<<16)|(destination_struct->image_height)); + IPA_IMS |= ((destination_struct->image_width<<16U)|(destination_struct->image_height)); + + if(SET == tempflag){ + /* restore the state of TEN */ + IPA_CTL |= IPA_CTL_TEN; + } } /*! - \brief initialize IPA foreground LUT parameters - \param[in] fg_lut_num: foreground LUT number of pixel. - \param[in] fg_lut_pf: foreground LUT pixel format,IPA_LUT_PF_ARGB8888,IPA_LUT_PF_RGB888. - \param[in] fg_lut_addr: foreground LUT memory base address. + \brief initialize IPA foreground LUT parameters + \param[in] fg_lut_num: foreground LUT number of pixel + \param[in] fg_lut_pf: foreground LUT pixel format(IPA_LUT_PF_ARGB8888, IPA_LUT_PF_RGB888) + \param[in] fg_lut_addr: foreground LUT memory base address \param[out] none \retval none */ -void ipa_foreground_lut_init(uint32_t fg_lut_num,uint8_t fg_lut_pf, uint32_t fg_lut_addr) +void ipa_foreground_lut_init(uint8_t fg_lut_num, uint8_t fg_lut_pf, uint32_t fg_lut_addr) { + FlagStatus tempflag = RESET; + if(RESET != (IPA_FPCTL & IPA_FPCTL_FLLEN)){ + tempflag = SET; + /* reset the FLLEN in order to configure the following bits */ + IPA_FPCTL &= ~IPA_FPCTL_FLLEN; + } + /* foreground LUT number of pixel configuration */ - IPA_FPCTL |= (fg_lut_num<<8U); + IPA_FPCTL |= ((uint32_t)fg_lut_num<<8U); /* foreground LUT pixel format configuration */ if(IPA_LUT_PF_RGB888 == fg_lut_pf){ IPA_FPCTL |= IPA_FPCTL_FLPF; @@ -269,20 +438,32 @@ void ipa_foreground_lut_init(uint32_t fg_lut_num,uint8_t fg_lut_pf, uint32_t fg_ /* foreground LUT memory base address configuration */ IPA_FLMADDR &= ~(IPA_FLMADDR_FLMADDR); IPA_FLMADDR = fg_lut_addr; + + if(SET == tempflag){ + /* restore the state of FLLEN */ + IPA_FPCTL |= IPA_FPCTL_FLLEN; + } } /*! - \brief initialize IPA background LUT parameters - \param[in] bg_lut_num: background LUT number of pixel. - \param[in] bg_lut_pf: background LUT pixel format, IPA_LUT_PF_ARGB8888,IPA_LUT_PF_RGB888. - \param[in] bg_lut_addr: background LUT memory base address. + \brief initialize IPA background LUT parameters + \param[in] bg_lut_num: background LUT number of pixel + \param[in] bg_lut_pf: background LUT pixel format(IPA_LUT_PF_ARGB8888, IPA_LUT_PF_RGB888) + \param[in] bg_lut_addr: background LUT memory base address \param[out] none \retval none */ -void ipa_background_lut_init(uint32_t bg_lut_num,uint8_t bg_lut_pf, uint32_t bg_lut_addr) +void ipa_background_lut_init(uint8_t bg_lut_num, uint8_t bg_lut_pf, uint32_t bg_lut_addr) { + FlagStatus tempflag = RESET; + if(RESET != (IPA_BPCTL & IPA_BPCTL_BLLEN)){ + tempflag = SET; + /* reset the BLLEN in order to configure the following bits */ + IPA_BPCTL &= ~IPA_BPCTL_BLLEN; + } + /* background LUT number of pixel configuration */ - IPA_BPCTL|=(bg_lut_num<<8U); + IPA_BPCTL |= ((uint32_t)bg_lut_num<<8U); /* background LUT pixel format configuration */ if(IPA_LUT_PF_RGB888 == bg_lut_pf){ IPA_BPCTL |= IPA_BPCTL_BLPF; @@ -292,29 +473,34 @@ void ipa_background_lut_init(uint32_t bg_lut_num,uint8_t bg_lut_pf, uint32_t bg_ /* background LUT memory base address configuration */ IPA_BLMADDR &= ~(IPA_BLMADDR_BLMADDR); IPA_BLMADDR = bg_lut_addr; + + if(SET == tempflag){ + /* restore the state of BLLEN */ + IPA_BPCTL |= IPA_BPCTL_BLLEN; + } } /*! - \brief configure line mark - \param[in] linenum: line number. + \brief configure IPA line mark + \param[in] line_num: line number \param[out] none \retval none */ -void ipa_line_mark_config(uint32_t linenum) +void ipa_line_mark_config(uint16_t line_num) { IPA_LM &= ~(IPA_LM_LM); - IPA_LM = linenum; + IPA_LM = line_num; } /*! - \brief Inter-timer enable or disable - \param[in] timercfg: IPA_INTER_TIMER_ENABLE,IPA_INTER_TIMER_DISABLE + \brief inter-timer enable or disable + \param[in] timer_cfg: IPA_INTER_TIMER_ENABLE,IPA_INTER_TIMER_DISABLE \param[out] none \retval none */ -void ipa_inter_timer_config(uint8_t timercfg) +void ipa_inter_timer_config(uint8_t timer_cfg) { - if(IPA_INTER_TIMER_ENABLE == timercfg){ + if(IPA_INTER_TIMER_ENABLE == timer_cfg){ IPA_ITCTL |= IPA_ITCTL_ITEN; }else{ IPA_ITCTL &= ~(IPA_ITCTL_ITEN); @@ -322,68 +508,110 @@ void ipa_inter_timer_config(uint8_t timercfg) } /*! - \brief number of clock cycles interval set - \param[in] clk_num: the number of clock cycles. + \brief configure the number of clock cycles interval + \param[in] clk_num: the number of clock cycles \param[out] none \retval none */ -void ipa_interval_clock_num_config(uint32_t clk_num ) +void ipa_interval_clock_num_config(uint8_t clk_num) { + /* NCCI[7:0] bits have no meaning if ITEN is '0' */ IPA_ITCTL &= ~(IPA_ITCTL_NCCI); - IPA_ITCTL |= (clk_num<<8U); + IPA_ITCTL |= ((uint32_t)clk_num<<8U); +} + +/*! + \brief get IPA flag status in IPA_INTF register + \param[in] flag: IPA flags + one or more parameters can be selected which are shown as below: + \arg IPA_FLAG_TAE: transfer access error interrupt flag + \arg IPA_FLAG_FTF: full transfer finish interrupt flag + \arg IPA_FLAG_TLM: transfer line mark interrupt flag + \arg IPA_FLAG_LAC: LUT access conflict interrupt flag + \arg IPA_FLAG_LLF: LUT loading finish interrupt flag + \arg IPA_FLAG_WCF: wrong configuration interrupt flag + \param[out] none + \retval none +*/ +FlagStatus ipa_flag_get(uint32_t flag) +{ + if(RESET != (IPA_INTF & flag)){ + return SET; + }else{ + return RESET; + } } /*! - \brief IPA interrupt enable - \param[in] inttype: IPA interrupt bits. - \arg IPA_CTL_TAEIE: transfer access error interrupt - \arg IPA_CTL_FTFIE: full transfer finish interrupt - \arg IPA_CTL_TLMIE: transfer line mark interrupt - \arg IPA_CTL_LACIE: LUT access conflict interrupt - \arg IPA_CTL_LLFIE: LUT loading finish interrupt - \arg IPA_CTL_WCFIE: wrong configuration interrupt + \brief clear IPA flag in IPA_INTF register + \param[in] flag: IPA flags + one or more parameters can be selected which are shown as below: + \arg IPA_FLAG_TAE: transfer access error interrupt flag + \arg IPA_FLAG_FTF: full transfer finish interrupt flag + \arg IPA_FLAG_TLM: transfer line mark interrupt flag + \arg IPA_FLAG_LAC: LUT access conflict interrupt flag + \arg IPA_FLAG_LLF: LUT loading finish interrupt flag + \arg IPA_FLAG_WCF: wrong configuration interrupt flag \param[out] none \retval none */ -void ipa_interrupt_enable(uint32_t inttype) +void ipa_flag_clear(uint32_t flag) { - IPA_CTL |= (inttype); + IPA_INTC |= (flag); } /*! - \brief IPA interrupt disable - \param[in] inttype: IPA interrupt bits. - \arg IPA_CTL_TAEIE: transfer access error interrupt - \arg IPA_CTL_FTFIE: full transfer finish interrupt - \arg IPA_CTL_TLMIE: transfer line mark interrupt - \arg IPA_CTL_LACIE: LUT access conflict interrupt - \arg IPA_CTL_LLFIE: LUT loading finish interrupt - \arg IPA_CTL_WCFIE: wrong configuration interrupt + \brief enable IPA interrupt + \param[in] int_flag: IPA interrupt flags + one or more parameters can be selected which are shown as below: + \arg IPA_INT_TAE: transfer access error interrupt + \arg IPA_INT_FTF: full transfer finish interrupt + \arg IPA_INT_TLM: transfer line mark interrupt + \arg IPA_INT_LAC: LUT access conflict interrupt + \arg IPA_INT_LLF: LUT loading finish interrupt + \arg IPA_INT_WCF: wrong configuration interrupt \param[out] none \retval none */ -void ipa_interrupt_disable(uint32_t inttype) +void ipa_interrupt_enable(uint32_t int_flag) { - IPA_CTL &= ~(inttype); + IPA_CTL |= (int_flag); } /*! - \brief get IPA interrupt flag - \param[in] intflag: tli interrupt flag bits. - \arg IPA_INTF_TAEIF: transfer access error interrupt flag - \arg IPA_INTF_FTFIF: full transfer finish interrupt flag - \arg IPA_INTF_TLMIF: transfer line mark interrupt flag - \arg IPA_INTF_LACIF: LUT access conflict interrupt flag - \arg IPA_INTF_LLFIF: LUT loading finish interrupt flag - \arg IPA_INTF_WCFIF: wrong configuration interrupt flag + \brief disable IPA interrupt + \param[in] int_flag: IPA interrupt flags + one or more parameters can be selected which are shown as below: + \arg IPA_INT_TAE: transfer access error interrupt + \arg IPA_INT_FTF: full transfer finish interrupt + \arg IPA_INT_TLM: transfer line mark interrupt + \arg IPA_INT_LAC: LUT access conflict interrupt + \arg IPA_INT_LLF: LUT loading finish interrupt + \arg IPA_INT_WCF: wrong configuration interrupt \param[out] none \retval none */ -FlagStatus ipa_interrupt_flag_get(uint32_t intflag) +void ipa_interrupt_disable(uint32_t int_flag) { - uint32_t state; - state = IPA_INTF; - if(state & intflag){ + IPA_CTL &= ~(int_flag); +} + +/*! + \brief get IPA interrupt flag + \param[in] int_flag: IPA interrupt flag flags + one or more parameters can be selected which are shown as below: + \arg IPA_INT_FLAG_TAE: transfer access error interrupt flag + \arg IPA_INT_FLAG_FTF: full transfer finish interrupt flag + \arg IPA_INT_FLAG_TLM: transfer line mark interrupt flag + \arg IPA_INT_FLAG_LAC: LUT access conflict interrupt flag + \arg IPA_INT_FLAG_LLF: LUT loading finish interrupt flag + \arg IPA_INT_FLAG_WCF: wrong configuration interrupt flag + \param[out] none + \retval none +*/ +FlagStatus ipa_interrupt_flag_get(uint32_t int_flag) +{ + if(0U != (IPA_INTF & int_flag)){ return SET; }else{ return RESET; @@ -391,19 +619,19 @@ FlagStatus ipa_interrupt_flag_get(uint32_t intflag) } /*! - \brief clear IPA interrupt flag - \param[in] intflag: tli interrupt flag bits. - \arg IPA_INTC_TAEIFC: transfer access error interrupt flag - \arg IPA_INTC_FTFIFC: full transfer finish interrupt flag - \arg IPA_INTC_TLMIFC: transfer line mark interrupt flag - \arg IPA_INTC_LACIFC: LUT access conflict interrupt flag - \arg IPA_INTC_LLFIFC: LUT loading finish interrupt flag - \arg IPA_INTC_WCFIFC: wrong configuration interrupt flag + \brief clear IPA interrupt flag + \param[in] int_flag: IPA interrupt flag flags + one or more parameters can be selected which are shown as below: + \arg IPA_INT_FLAG_TAE: transfer access error interrupt flag + \arg IPA_INT_FLAG_FTF: full transfer finish interrupt flag + \arg IPA_INT_FLAG_TLM: transfer line mark interrupt flag + \arg IPA_INT_FLAG_LAC: LUT access conflict interrupt flag + \arg IPA_INT_FLAG_LLF: LUT loading finish interrupt flag + \arg IPA_INT_FLAG_WCF: wrong configuration interrupt flag \param[out] none \retval none */ -void ipa_interrupt_flag_clear(uint32_t intflag) +void ipa_interrupt_flag_clear(uint32_t int_flag) { - IPA_INTC |= (intflag); + IPA_INTC |= (int_flag); } - diff --git a/bsp/gd32450z-eval/Libraries/GD32F4xx_standard_peripheral/Source/gd32f4xx_iref.c b/bsp/gd32450z-eval/Libraries/GD32F4xx_standard_peripheral/Source/gd32f4xx_iref.c index 237fc2ee75..218a070ef4 100644 --- a/bsp/gd32450z-eval/Libraries/GD32F4xx_standard_peripheral/Source/gd32f4xx_iref.c +++ b/bsp/gd32450z-eval/Libraries/GD32F4xx_standard_peripheral/Source/gd32f4xx_iref.c @@ -1,12 +1,37 @@ /*! - \file gd32f4xx_iref.c - \brief IREF driver + \file gd32f4xx_iref.c + \brief IREF driver + + \version 2016-08-15, V1.0.0, firmware for GD32F4xx + \version 2018-12-12, V2.0.0, firmware for GD32F4xx + \version 2020-09-30, V2.1.0, firmware for GD32F4xx */ /* - Copyright (C) 2016 GigaDevice + Copyright (c) 2020, GigaDevice Semiconductor Inc. + + Redistribution and use in source and binary forms, with or without modification, +are permitted provided that the following conditions are met: + + 1. Redistributions of source code must retain the above copyright notice, this + list of conditions and the following disclaimer. + 2. Redistributions in binary form must reproduce the above copyright notice, + this list of conditions and the following disclaimer in the documentation + and/or other materials provided with the distribution. + 3. Neither the name of the copyright holder nor the names of its contributors + may be used to endorse or promote products derived from this software without + specific prior written permission. - 2016-08-15, V1.0.0, firmware for GD32F4xx + THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED +WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. +IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, +INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT +NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR +PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, +WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY +OF SUCH DAMAGE. */ #include "gd32f4xx_iref.h" @@ -87,7 +112,7 @@ void iref_sink_set(uint32_t sinkmode) } /*! - \brief set IREF step data + \brief set IREF step data \param[in] stepdata \arg IREF_CUR_STEP_DATA_X:(x=0..63): step*x \param[out] none diff --git a/bsp/gd32450z-eval/Libraries/GD32F4xx_standard_peripheral/Source/gd32f4xx_misc.c b/bsp/gd32450z-eval/Libraries/GD32F4xx_standard_peripheral/Source/gd32f4xx_misc.c index 1649929a4b..c826722f13 100644 --- a/bsp/gd32450z-eval/Libraries/GD32F4xx_standard_peripheral/Source/gd32f4xx_misc.c +++ b/bsp/gd32450z-eval/Libraries/GD32F4xx_standard_peripheral/Source/gd32f4xx_misc.c @@ -1,12 +1,37 @@ /*! - \file gd32f4xx_misc.c - \brief MISC driver + \file gd32f4xx_misc.c + \brief MISC driver + + \version 2016-08-15, V1.0.0, firmware for GD32F4xx + \version 2018-12-12, V2.0.0, firmware for GD32F4xx + \version 2020-09-30, V2.1.0, firmware for GD32F4xx */ /* - Copyright (C) 2016 GigaDevice + Copyright (c) 2020, GigaDevice Semiconductor Inc. + + Redistribution and use in source and binary forms, with or without modification, +are permitted provided that the following conditions are met: + + 1. Redistributions of source code must retain the above copyright notice, this + list of conditions and the following disclaimer. + 2. Redistributions in binary form must reproduce the above copyright notice, + this list of conditions and the following disclaimer in the documentation + and/or other materials provided with the distribution. + 3. Neither the name of the copyright holder nor the names of its contributors + may be used to endorse or promote products derived from this software without + specific prior written permission. - 2016-08-15, V1.0.0, firmware for GD32F4xx + THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED +WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. +IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, +INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT +NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR +PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, +WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY +OF SUCH DAMAGE. */ #include "gd32f4xx_misc.h" @@ -36,7 +61,7 @@ void nvic_priority_group_set(uint32_t nvic_prigroup) \param[out] none \retval none */ -void nvic_irq_enable(uint8_t nvic_irq, uint8_t nvic_irq_pre_priority, +void nvic_irq_enable(uint8_t nvic_irq, uint8_t nvic_irq_pre_priority, uint8_t nvic_irq_sub_priority) { uint32_t temp_priority = 0x00U, temp_pre = 0x00U, temp_sub = 0x00U; @@ -57,6 +82,9 @@ void nvic_irq_enable(uint8_t nvic_irq, uint8_t nvic_irq_pre_priority, temp_pre=4U; temp_sub=0x0U; }else{ + nvic_priority_group_set(NVIC_PRIGROUP_PRE2_SUB2); + temp_pre=2U; + temp_sub=0x2U; } /* get the temp_priority to fill the NVIC->IP register */ temp_priority = (uint32_t)nvic_irq_pre_priority << (0x4U - temp_pre); @@ -96,10 +124,10 @@ void nvic_vector_table_set(uint32_t nvic_vict_tab, uint32_t offset) /*! \brief set the state of the low power mode \param[in] lowpower_mode: the low power mode state - \arg SCB_LPM_SLEEP_EXIT_ISR: if chose this para, the system always enter low power + \arg SCB_LPM_SLEEP_EXIT_ISR: if chose this para, the system always enter low power mode by exiting from ISR \arg SCB_LPM_DEEPSLEEP: if chose this para, the system will enter the DEEPSLEEP mode - \arg SCB_LPM_WAKE_BY_ALL_INT: if chose this para, the lowpower mode can be woke up + \arg SCB_LPM_WAKE_BY_ALL_INT: if chose this para, the lowpower mode can be woke up by all the enable and disable interrupts \param[out] none \retval none @@ -112,10 +140,10 @@ void system_lowpower_set(uint8_t lowpower_mode) /*! \brief reset the state of the low power mode \param[in] lowpower_mode: the low power mode state - \arg SCB_LPM_SLEEP_EXIT_ISR: if chose this para, the system will exit low power + \arg SCB_LPM_SLEEP_EXIT_ISR: if chose this para, the system will exit low power mode by exiting from ISR \arg SCB_LPM_DEEPSLEEP: if chose this para, the system will enter the SLEEP mode - \arg SCB_LPM_WAKE_BY_ALL_INT: if chose this para, the lowpower mode only can be + \arg SCB_LPM_WAKE_BY_ALL_INT: if chose this para, the lowpower mode only can be woke up by the enable interrupts \param[out] none \retval none diff --git a/bsp/gd32450z-eval/Libraries/GD32F4xx_standard_peripheral/Source/gd32f4xx_pmu.c b/bsp/gd32450z-eval/Libraries/GD32F4xx_standard_peripheral/Source/gd32f4xx_pmu.c index 267e4c32fd..05f4cd7c3a 100644 --- a/bsp/gd32450z-eval/Libraries/GD32F4xx_standard_peripheral/Source/gd32f4xx_pmu.c +++ b/bsp/gd32450z-eval/Libraries/GD32F4xx_standard_peripheral/Source/gd32f4xx_pmu.c @@ -1,12 +1,37 @@ /*! - \file gd32f4xx_pmu.c - \brief PMU driver + \file gd32f4xx_pmu.c + \brief PMU driver + + \version 2016-08-15, V1.0.0, firmware for GD32F4xx + \version 2018-12-12, V2.0.0, firmware for GD32F4xx + \version 2020-09-30, V2.1.0, firmware for GD32F4xx */ /* - Copyright (C) 2016 GigaDevice + Copyright (c) 2020, GigaDevice Semiconductor Inc. + + Redistribution and use in source and binary forms, with or without modification, +are permitted provided that the following conditions are met: - 2016-08-15, V1.0.0, firmware for GD32F4xx + 1. Redistributions of source code must retain the above copyright notice, this + list of conditions and the following disclaimer. + 2. Redistributions in binary form must reproduce the above copyright notice, + this list of conditions and the following disclaimer in the documentation + and/or other materials provided with the distribution. + 3. Neither the name of the copyright holder nor the names of its contributors + may be used to endorse or promote products derived from this software without + specific prior written permission. + + THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED +WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. +IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, +INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT +NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR +PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, +WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY +OF SUCH DAMAGE. */ #include "gd32f4xx_pmu.h" @@ -26,37 +51,37 @@ void pmu_deinit(void) /*! \brief select low voltage detector threshold - \param[in] pmu_lvdt_n: - \arg PMU_LVDT_0: voltage threshold is 2.2V + \param[in] lvdt_n: + \arg PMU_LVDT_0: voltage threshold is 2.1V \arg PMU_LVDT_1: voltage threshold is 2.3V \arg PMU_LVDT_2: voltage threshold is 2.4V - \arg PMU_LVDT_3: voltage threshold is 2.5V - \arg PMU_LVDT_4: voltage threshold is 2.6V - \arg PMU_LVDT_5: voltage threshold is 2.7V - \arg PMU_LVDT_6: voltage threshold is 2.8V - \arg PMU_LVDT_7: voltage threshold is 2.9V + \arg PMU_LVDT_3: voltage threshold is 2.6V + \arg PMU_LVDT_4: voltage threshold is 2.7V + \arg PMU_LVDT_5: voltage threshold is 2.9V + \arg PMU_LVDT_6: voltage threshold is 3.0V + \arg PMU_LVDT_7: voltage threshold is 3.1V \param[out] none \retval none */ -void pmu_lvd_select(uint32_t pmu_lvdt_n) +void pmu_lvd_select(uint32_t lvdt_n) { /* disable LVD */ PMU_CTL &= ~PMU_CTL_LVDEN; /* clear LVDT bits */ PMU_CTL &= ~PMU_CTL_LVDT; /* set LVDT bits according to pmu_lvdt_n */ - PMU_CTL |= pmu_lvdt_n; + PMU_CTL |= lvdt_n; /* enable LVD */ PMU_CTL |= PMU_CTL_LVDEN; } /*! - \brief LDO output voltage select + \brief select LDO output voltage this bit set by software when the main PLL closed, before closing PLL, change the system clock to IRC16M or HXTAL \param[in] ldo_output: \arg PMU_LDOVS_LOW: low-driver mode enable in deep-sleep mode - \arg PMU_LDOVS_MID: low-driver mode disable in deep-sleep mode - \arg PMU_LDOVS_HIGH: low-driver mode disable in deep-sleep mode + \arg PMU_LDOVS_MID: mid-driver mode disable in deep-sleep mode + \arg PMU_LDOVS_HIGH: high-driver mode disable in deep-sleep mode \param[out] none \retval none */ @@ -67,10 +92,10 @@ void pmu_ldo_output_select(uint32_t ldo_output) } /*! - \brief low-driver mode enable in deep-sleep mode + \brief enable low-driver mode in deep-sleep mode \param[in] lowdr_mode: - \arg PMU_LOWDRIVER_ENABLE: low-driver mode enable in deep-sleep mode - \arg PMU_LOWDRIVER_DISABLE: low-driver mode disable in deep-sleep mode + \arg PMU_LOWDRIVER_ENABLE: enable low-driver mode in deep-sleep mode + \arg PMU_LOWDRIVER_DISABLE: disable low-driver mode in deep-sleep mode \param[out] none \retval none */ @@ -81,11 +106,11 @@ void pmu_low_driver_mode_enable(uint32_t lowdr_mode) } /*! - \brief high-driver mode switch + \brief switch high-driver mode this bit set by software only when IRC16M or HXTAL used as system clock \param[in] highdr_switch: - \arg PMU_HIGHDR_SWITCH_NONE: no high-driver mode switch - \arg PMU_HIGHDR_SWITCH_EN: high-driver mode switch + \arg PMU_HIGHDR_SWITCH_NONE: disable high-driver mode switch + \arg PMU_HIGHDR_SWITCH_EN: enable high-driver mode switch \param[out] none \retval none */ @@ -150,8 +175,8 @@ void pmu_lowdriver_lowpower_config(uint32_t mode) /*! \brief low-driver mode when use normal power LDO \param[in] mode: - \arg PMU_NORMALDR_NORMALPWR: normal driver when use low power LDO - \arg PMU_LOWDR_NORMALPWR: low-driver mode enabled when LDEN is 11 and use low power LDO + \arg PMU_NORMALDR_NORMALPWR: normal driver when use normal power LDO + \arg PMU_LOWDR_NORMALPWR: low-driver mode enabled when LDEN is 11 and use normal power LDO \param[out] none \retval none */ @@ -173,7 +198,7 @@ void pmu_to_sleepmode(uint8_t sleepmodecmd) { /* clear sleepdeep bit of Cortex-M4 system control register */ SCB->SCR &= ~((uint32_t)SCB_SCR_SLEEPDEEP_Msk); - + /* select WFI or WFE command to enter sleep mode */ if(WFI_CMD == sleepmodecmd){ __WFI(); @@ -184,26 +209,37 @@ void pmu_to_sleepmode(uint8_t sleepmodecmd) /*! \brief PMU work at deepsleep mode - \param[in] pmu_ldo + \param[in] ldo \arg PMU_LDO_NORMAL: LDO normal work when pmu enter deepsleep mode \arg PMU_LDO_LOWPOWER: LDO work at low power mode when pmu enter deepsleep mode - \param[in] deepsleepmodecmd: + \param[in] deepsleepmodecmd: \arg WFI_CMD: use WFI command \arg WFE_CMD: use WFE command \param[out] none \retval none */ -void pmu_to_deepsleepmode(uint32_t pmu_ldo,uint8_t deepsleepmodecmd) +void pmu_to_deepsleepmode(uint32_t ldo,uint8_t deepsleepmodecmd) { + static uint32_t reg_snap[ 4 ]; /* clear stbmod and ldolp bits */ PMU_CTL &= ~((uint32_t)(PMU_CTL_STBMOD | PMU_CTL_LDOLP)); - + /* set ldolp bit according to pmu_ldo */ - PMU_CTL |= pmu_ldo; - + PMU_CTL |= ldo; + /* set sleepdeep bit of Cortex-M4 system control register */ SCB->SCR |= SCB_SCR_SLEEPDEEP_Msk; - + + reg_snap[ 0 ] = REG32( 0xE000E010U ); + reg_snap[ 1 ] = REG32( 0xE000E100U ); + reg_snap[ 2 ] = REG32( 0xE000E104U ); + reg_snap[ 3 ] = REG32( 0xE000E108U ); + + REG32( 0xE000E010U ) &= 0x00010004U; + REG32( 0xE000E180U ) = 0XFF7FF831U; + REG32( 0xE000E184U ) = 0XBFFFF8FFU; + REG32( 0xE000E188U ) = 0xFFFFEFFFU; + /* select WFI or WFE command to enter deepsleep mode */ if(WFI_CMD == deepsleepmodecmd){ __WFI(); @@ -212,6 +248,12 @@ void pmu_to_deepsleepmode(uint32_t pmu_ldo,uint8_t deepsleepmodecmd) __WFE(); __WFE(); } + + REG32( 0xE000E010U ) = reg_snap[ 0 ] ; + REG32( 0xE000E100U ) = reg_snap[ 1 ] ; + REG32( 0xE000E104U ) = reg_snap[ 2 ] ; + REG32( 0xE000E108U ) = reg_snap[ 3 ] ; + /* reset sleepdeep bit of Cortex-M4 system control register */ SCB->SCR &= ~((uint32_t)SCB_SCR_SLEEPDEEP_Msk); } @@ -231,10 +273,10 @@ void pmu_to_standbymode(uint8_t standbymodecmd) /* set stbmod bit */ PMU_CTL |= PMU_CTL_STBMOD; - + /* reset wakeup flag */ PMU_CTL |= PMU_CTL_WURST; - + /* select WFI or WFE command to enter standby mode */ if(WFI_CMD == standbymodecmd){ __WFI(); @@ -282,25 +324,26 @@ void pmu_flag_reset(uint32_t flag_reset) } /*! - \brief get flag status + \brief get flag state \param[in] pmu_flag: - \arg PMU_FLAG_WAKEUP: wakeup flag status - \arg PMU_FLAG_STANDBY: standby flag status - \arg PMU_FLAG_LVD: lvd flag status + \arg PMU_FLAG_WAKEUP: wakeup flag + \arg PMU_FLAG_STANDBY: standby flag + \arg PMU_FLAG_LVD: lvd flag \arg PMU_FLAG_BLDORF: backup SRAM LDO ready flag \arg PMU_FLAG_LDOVSRF: LDO voltage select ready flag \arg PMU_FLAG_HDRF: high-driver ready flag \arg PMU_FLAG_HDSRF: high-driver switch ready flag - \arg PMU_FLAG_LDRF: low-driver mode ready flag + \arg PMU_FLAG_LDRF: low-driver mode ready flag \param[out] none - \retval FlagStatus SET or RESET + \retval FlagStatus: SET or RESET */ -FlagStatus pmu_flag_get(uint32_t pmu_flag ) +FlagStatus pmu_flag_get(uint32_t pmu_flag) { if(PMU_CS & pmu_flag){ return SET; + }else{ + return RESET; } - return RESET; } /*! diff --git a/bsp/gd32450z-eval/Libraries/GD32F4xx_standard_peripheral/Source/gd32f4xx_rcu.c b/bsp/gd32450z-eval/Libraries/GD32F4xx_standard_peripheral/Source/gd32f4xx_rcu.c index e37b9f9808..aecc895a09 100644 --- a/bsp/gd32450z-eval/Libraries/GD32F4xx_standard_peripheral/Source/gd32f4xx_rcu.c +++ b/bsp/gd32450z-eval/Libraries/GD32F4xx_standard_peripheral/Source/gd32f4xx_rcu.c @@ -1,21 +1,52 @@ /*! - \file gd32f4xx_rcu.c - \brief RCU driver + \file gd32f4xx_rcu.c + \brief RCU driver + + \version 2016-08-15, V1.0.0, firmware for GD32F4xx + \version 2018-12-12, V2.0.0, firmware for GD32F4xx + \version 2020-09-30, V2.1.0, firmware for GD32F4xx */ /* - Copyright (C) 2016 GigaDevice + Copyright (c) 2020, GigaDevice Semiconductor Inc. + + Redistribution and use in source and binary forms, with or without modification, +are permitted provided that the following conditions are met: + + 1. Redistributions of source code must retain the above copyright notice, this + list of conditions and the following disclaimer. + 2. Redistributions in binary form must reproduce the above copyright notice, + this list of conditions and the following disclaimer in the documentation + and/or other materials provided with the distribution. + 3. Neither the name of the copyright holder nor the names of its contributors + may be used to endorse or promote products derived from this software without + specific prior written permission. - 2016-08-15, V1.0.1, firmware for GD32F4xx + THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED +WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. +IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, +INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT +NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR +PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, +WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY +OF SUCH DAMAGE. */ #include "gd32f4xx_rcu.h" -#define SEL_IRC16M 0U -#define SEL_HXTAL 1U -#define SEL_PLLP 2U -#define OSC_STARTUP_TIMEOUT ((uint16_t)0xfffffU) -#define LXTAL_STARTUP_TIMEOUT ((uint16_t)0x3ffffffU) +/* define clock source */ +#define SEL_IRC16M ((uint16_t)0U) /* IRC16M is selected as CK_SYS */ +#define SEL_HXTAL ((uint16_t)1U) /* HXTAL is selected as CK_SYS */ +#define SEL_PLLP ((uint16_t)2U) /* PLLP is selected as CK_SYS */ +/* define startup timeout count */ +#define OSC_STARTUP_TIMEOUT ((uint32_t)0x000fffffU) +#define LXTAL_STARTUP_TIMEOUT ((uint32_t)0x0fffffffU) + +/* RCU IRC16M adjust value mask and offset*/ +#define RCU_IRC16M_ADJUST_MASK ((uint8_t)0x1FU) +#define RCU_IRC16M_ADJUST_OFFSET ((uint32_t)3U) /*! \brief deinitialize the RCU @@ -33,8 +64,9 @@ void rcu_deinit(void) RCU_CFG0_RTCDIV | RCU_CFG0_CKOUT0SEL | RCU_CFG0_I2SSEL | RCU_CFG0_CKOUT0DIV | RCU_CFG0_CKOUT1DIV | RCU_CFG0_CKOUT1SEL); /* reset CTL register */ - RCU_CTL &= ~(RCU_CTL_HXTALEN | RCU_CTL_CKMEN | RCU_CTL_PLLEN | RCU_CTL_PLLI2SEN | - RCU_CTL_PLLSAIEN | RCU_CTL_HXTALBPS); + RCU_CTL &= ~(RCU_CTL_HXTALEN | RCU_CTL_CKMEN | RCU_CTL_PLLEN | RCU_CTL_PLLI2SEN + | RCU_CTL_PLLSAIEN); + RCU_CTL &= ~(RCU_CTL_HXTALBPS); /* reset PLL register */ RCU_PLL = 0x24003010U; /* reset PLLI2S register */ @@ -44,7 +76,7 @@ void rcu_deinit(void) /* reset INT register */ RCU_INT = 0x00000000U; /* reset CFG1 register */ - RCU_CFG1 &= ~(RCU_CFG1_PLLSAIRDIV | RCU_CFG1_TIMERSEL); + RCU_CFG1 &= ~(RCU_CFG1_PLLSAIRDIV | RCU_CFG1_TIMERSEL); } /*! @@ -236,7 +268,7 @@ void rcu_periph_clock_sleep_disable(rcu_periph_sleep_enum periph) \arg RCU_GPIOxRST (x=A,B,C,D,E,F,G,H,I): reset GPIO ports \arg RCU_CRCRST: reset CRC \arg RCU_DMAxRST (x=0,1): reset DMA - \arg RCU_IPAENRST: reset IPA + \arg RCU_IPARST: reset IPA \arg RCU_ENETRST: reset ENET \arg RCU_USBHSRST: reset USBHS \arg RCU_DCIRST: reset DCI @@ -273,7 +305,7 @@ void rcu_periph_reset_enable(rcu_periph_reset_enum periph_reset) \arg RCU_GPIOxRST (x=A,B,C,D,E,F,G,H,I): reset GPIO ports \arg RCU_CRCRST: reset CRC \arg RCU_DMAxRST (x=0,1): reset DMA - \arg RCU_IPAENRST: reset IPA + \arg RCU_IPARST: reset IPA \arg RCU_ENETRST: reset ENET \arg RCU_USBHSRST: reset USBHS \arg RCU_DCIRST: reset DCI @@ -338,7 +370,7 @@ void rcu_bkp_reset_disable(void) void rcu_system_clock_source_config(uint32_t ck_sys) { uint32_t reg; - + reg = RCU_CFG0; /* reset the SCS bits and set according to ck_sys */ reg &= ~RCU_CFG0_SCS; @@ -370,9 +402,9 @@ uint32_t rcu_system_clock_source_get(void) void rcu_ahb_clock_config(uint32_t ck_ahb) { uint32_t reg; - + reg = RCU_CFG0; - /* reset the AHBPS bits and set according to ck_ahb */ + /* reset the AHBPSC bits and set according to ck_ahb */ reg &= ~RCU_CFG0_AHBPSC; RCU_CFG0 = (reg | ck_ahb); } @@ -392,9 +424,9 @@ void rcu_ahb_clock_config(uint32_t ck_ahb) void rcu_apb1_clock_config(uint32_t ck_apb1) { uint32_t reg; - + reg = RCU_CFG0; - /* reset the APB1PS and set according to ck_apb1 */ + /* reset the APB1PSC and set according to ck_apb1 */ reg &= ~RCU_CFG0_APB1PSC; RCU_CFG0 = (reg | ck_apb1); } @@ -414,9 +446,9 @@ void rcu_apb1_clock_config(uint32_t ck_apb1) void rcu_apb2_clock_config(uint32_t ck_apb2) { uint32_t reg; - + reg = RCU_CFG0; - /* reset the APB2PS and set according to ck_apb2 */ + /* reset the APB2PSC and set according to ck_apb2 */ reg &= ~RCU_CFG0_APB2PSC; RCU_CFG0 = (reg | ck_apb2); } @@ -429,7 +461,7 @@ void rcu_apb2_clock_config(uint32_t ck_apb2) \arg RCU_CKOUT0SRC_LXTAL: LXTAL selected \arg RCU_CKOUT0SRC_HXTAL: HXTAL selected \arg RCU_CKOUT0SRC_PLLP: PLLP selected - \param[in] ckout0_div: CK_OUT0 divider + \param[in] ckout0_div: CK_OUT0 divider \arg RCU_CKOUT0_DIVx(x=1,2,3,4,5): CK_OUT0 is divided by x \param[out] none \retval none @@ -437,7 +469,7 @@ void rcu_apb2_clock_config(uint32_t ck_apb2) void rcu_ckout0_config(uint32_t ckout0_src, uint32_t ckout0_div) { uint32_t reg; - + reg = RCU_CFG0; /* reset the CKOUT0SRC, CKOUT0DIV and set according to ckout0_src and ckout0_div */ reg &= ~(RCU_CFG0_CKOUT0SEL | RCU_CFG0_CKOUT0DIV ); @@ -451,8 +483,8 @@ void rcu_ckout0_config(uint32_t ckout0_src, uint32_t ckout0_div) \arg RCU_CKOUT1SRC_SYSTEMCLOCK: system clock selected \arg RCU_CKOUT1SRC_PLLI2SR: PLLI2SR selected \arg RCU_CKOUT1SRC_HXTAL: HXTAL selected - \arg RCU_CKOUT1SRC_PLLP: PLLP selected - \param[in] ckout1_div: CK_OUT1 divider + \arg RCU_CKOUT1SRC_PLLP: PLLP selected + \param[in] ckout1_div: CK_OUT1 divider \arg RCU_CKOUT1_DIVx(x=1,2,3,4,5): CK_OUT1 is divided by x \param[out] none \retval none @@ -460,7 +492,7 @@ void rcu_ckout0_config(uint32_t ckout0_src, uint32_t ckout0_div) void rcu_ckout1_config(uint32_t ckout1_src, uint32_t ckout1_div) { uint32_t reg; - + reg = RCU_CFG0; /* reset the CKOUT1SRC, CKOUT1DIV and set according to ckout1_src and ckout1_div */ reg &= ~(RCU_CFG0_CKOUT1SEL | RCU_CFG0_CKOUT1DIV); @@ -468,7 +500,7 @@ void rcu_ckout1_config(uint32_t ckout1_src, uint32_t ckout1_div) } /*! - \brief configure the main PLL clock + \brief configure the main PLL clock \param[in] pll_src: PLL clock source selection \arg RCU_PLLSRC_IRC16M: select IRC16M as PLL source clock \arg RCU_PLLSRC_HXTAL: select HXTAL as PLL source clock @@ -487,7 +519,7 @@ ErrStatus rcu_pll_config(uint32_t pll_src, uint32_t pll_psc, uint32_t pll_n, uin { uint32_t ss_modulation_inc; uint32_t ss_modulation_reg; - + ss_modulation_inc = 0U; ss_modulation_reg = RCU_PLLSSCTL; @@ -499,9 +531,9 @@ ErrStatus rcu_pll_config(uint32_t pll_src, uint32_t pll_psc, uint32_t pll_n, uin ss_modulation_inc += RCU_SS_MODULATION_CENTER_INC; } } - + /* check the function parameter */ - if(CHECK_PLL_PSC_VALID(pll_psc) && CHECK_PLL_N_VALID(pll_n,ss_modulation_inc) && + if(CHECK_PLL_PSC_VALID(pll_psc) && CHECK_PLL_N_VALID(pll_n,ss_modulation_inc) && CHECK_PLL_P_VALID(pll_p) && CHECK_PLL_Q_VALID(pll_q)){ RCU_PLL = pll_psc | (pll_n << 6) | (((pll_p >> 1) - 1U) << 16) | (pll_src) | (pll_q << 24); @@ -509,60 +541,55 @@ ErrStatus rcu_pll_config(uint32_t pll_src, uint32_t pll_psc, uint32_t pll_n, uin /* return status */ return ERROR; } - + /* return status */ return SUCCESS; } /*! - \brief configure the PLLI2S clock + \brief configure the PLLI2S clock \param[in] plli2s_n: the PLLI2S VCO clock multi factor \arg this parameter should be selected between 50 and 500 - \param[in] plli2s_q: the PLLI2S Q output frequency division factor from PLLI2S VCO clock - \arg this parameter should be selected between 2 and 15 \param[in] plli2s_r: the PLLI2S R output frequency division factor from PLLI2S VCO clock \arg this parameter should be selected between 2 and 7 \param[out] none \retval ErrStatus: SUCCESS or ERROR */ -ErrStatus rcu_plli2s_config(uint32_t plli2s_n, uint32_t plli2s_q, uint32_t plli2s_r) +ErrStatus rcu_plli2s_config(uint32_t plli2s_n, uint32_t plli2s_r) { /* check the function parameter */ - if(CHECK_PLLI2S_N_VALID(plli2s_n) && CHECK_PLLI2S_Q_VALID(plli2s_q) && CHECK_PLLI2S_R_VALID(plli2s_r)){ - RCU_PLLI2S = (plli2s_n << 6) | (plli2s_q << 24) | (plli2s_r << 28); + if(CHECK_PLLI2S_N_VALID(plli2s_n) && CHECK_PLLI2S_R_VALID(plli2s_r)){ + RCU_PLLI2S = (plli2s_n << 6) | (plli2s_r << 28); }else{ /* return status */ return ERROR; } - + /* return status */ - return SUCCESS; + return SUCCESS; } /*! - \brief configure the PLLSAI clock + \brief configure the PLLSAI clock \param[in] pllsai_n: the PLLSAI VCO clock multi factor \arg this parameter should be selected between 50 and 500 \param[in] pllsai_p: the PLLSAI P output frequency division factor from PLL VCO clock \arg this parameter should be selected 2,4,6,8 - \param[in] pllsai_q: the PLLSAI Q output frequency division factor from PLL VCO clock - \arg this parameter should be selected between 2 and 15 \param[in] pllsai_r: the PLLSAI R output frequency division factor from PLL VCO clock \arg this parameter should be selected between 2 and 7 \param[out] none \retval ErrStatus: SUCCESS or ERROR */ -ErrStatus rcu_pllsai_config(uint32_t pllsai_n, uint32_t pllsai_p, uint32_t pllsai_q, uint32_t pllsai_r) +ErrStatus rcu_pllsai_config(uint32_t pllsai_n, uint32_t pllsai_p, uint32_t pllsai_r) { /* check the function parameter */ - if(CHECK_PLLSAI_N_VALID(pllsai_n) && CHECK_PLLSAI_P_VALID(pllsai_p) && - CHECK_PLLSAI_Q_VALID(pllsai_q) && CHECK_PLLSAI_R_VALID(pllsai_r)){ - RCU_PLLSAI = (pllsai_n << 6U) | (((pllsai_p >> 1U) - 1U) << 16U) | (pllsai_q << 24U) | (pllsai_r << 28U); + if(CHECK_PLLSAI_N_VALID(pllsai_n) && CHECK_PLLSAI_P_VALID(pllsai_p) && CHECK_PLLSAI_R_VALID(pllsai_r)){ + RCU_PLLSAI = (pllsai_n << 6U) | (((pllsai_p >> 1U) - 1U) << 16U) | (pllsai_r << 28U); }else{ /* return status */ return ERROR; } - + /* return status */ return SUCCESS; } @@ -581,14 +608,34 @@ ErrStatus rcu_pllsai_config(uint32_t pllsai_n, uint32_t pllsai_p, uint32_t pllsa void rcu_rtc_clock_config(uint32_t rtc_clock_source) { uint32_t reg; - - reg = RCU_BDCTL; + + reg = RCU_BDCTL; /* reset the RTCSRC bits and set according to rtc_clock_source */ reg &= ~RCU_BDCTL_RTCSRC; RCU_BDCTL = (reg | rtc_clock_source); } /*! + \brief configure the frequency division of RTC clock when HXTAL was selected as its clock source + \param[in] rtc_div: RTC clock frequency division + only one parameter can be selected which is shown as below: + \arg RCU_RTC_HXTAL_NONE: no clock for RTC + \arg RCU_RTC_HXTAL_DIVx: RTCDIV clock select CK_HXTAL/x, x = 2....31 + \param[out] none + \retval none +*/ +void rcu_rtc_div_config(uint32_t rtc_div) +{ + uint32_t reg; + + reg = RCU_CFG0; + /* reset the RTCDIV bits and set according to rtc_div value */ + reg &= ~RCU_CFG0_RTCDIV; + RCU_CFG0 = (reg | rtc_div); +} + + +/*! \brief configure the I2S clock source selection \param[in] i2s_clock_source: I2S clock source selection only one parameter can be selected which is shown as below: @@ -600,8 +647,8 @@ void rcu_rtc_clock_config(uint32_t rtc_clock_source) void rcu_i2s_clock_config(uint32_t i2s_clock_source) { uint32_t reg; - - reg = RCU_CFG0; + + reg = RCU_CFG0; /* reset the I2SSEL bit and set according to i2s_clock_source */ reg &= ~RCU_CFG0_I2SSEL; RCU_CFG0 = (reg | i2s_clock_source); @@ -619,9 +666,9 @@ void rcu_i2s_clock_config(uint32_t i2s_clock_source) void rcu_ck48m_clock_config(uint32_t ck48m_clock_source) { uint32_t reg; - + reg = RCU_ADDCTL; - /* reset the I2SSEL bit and set according to i2s_clock_source */ + /* reset the CK48MSEL bit and set according to i2s_clock_source */ reg &= ~RCU_ADDCTL_CK48MSEL; RCU_ADDCTL = (reg | ck48m_clock_source); } @@ -638,7 +685,7 @@ void rcu_ck48m_clock_config(uint32_t ck48m_clock_source) void rcu_pll48m_clock_config(uint32_t pll48m_clock_source) { uint32_t reg; - + reg = RCU_ADDCTL; /* reset the PLL48MSEL bit and set according to pll48m_clock_source */ reg &= ~RCU_ADDCTL_PLL48MSEL; @@ -649,13 +696,13 @@ void rcu_pll48m_clock_config(uint32_t pll48m_clock_source) \brief configure the TIMER clock prescaler selection \param[in] timer_clock_prescaler: TIMER clock selection only one parameter can be selected which is shown as below: - \arg RCU_TIMER_PSC_MUL2: if APB1PSC/APB2PSC in RCU_CFG0 register is 0b0xx(CK_APBx = CK_AHB) + \arg RCU_TIMER_PSC_MUL2: if APB1PSC/APB2PSC in RCU_CFG0 register is 0b0xx(CK_APBx = CK_AHB) or 0b100(CK_APBx = CK_AHB/2), the TIMER clock is equal to CK_AHB(CK_TIMERx = CK_AHB). - or else, the TIMER clock is twice the corresponding APB clock (TIMER in APB1 domain: CK_TIMERx = 2 x CK_APB1; + or else, the TIMER clock is twice the corresponding APB clock (TIMER in APB1 domain: CK_TIMERx = 2 x CK_APB1; TIMER in APB2 domain: CK_TIMERx = 2 x CK_APB2) - \arg RCU_TIMER_PSC_MUL4: if APB1PSC/APB2PSC in RCU_CFG0 register is 0b0xx(CK_APBx = CK_AHB), - 0b100(CK_APBx = CK_AHB/2), or 0b101(CK_APBx = CK_AHB/4), the TIMER clock is equal to CK_AHB(CK_TIMERx = CK_AHB). - or else, the TIMER clock is four timers the corresponding APB clock (TIMER in APB1 domain: CK_TIMERx = 4 x CK_APB1; + \arg RCU_TIMER_PSC_MUL4: if APB1PSC/APB2PSC in RCU_CFG0 register is 0b0xx(CK_APBx = CK_AHB), + 0b100(CK_APBx = CK_AHB/2), or 0b101(CK_APBx = CK_AHB/4), the TIMER clock is equal to CK_AHB(CK_TIMERx = CK_AHB). + or else, the TIMER clock is four timers the corresponding APB clock (TIMER in APB1 domain: CK_TIMERx = 4 x CK_APB1; TIMER in APB2 domain: CK_TIMERx = 4 x CK_APB2) \param[out] none \retval none @@ -681,7 +728,7 @@ void rcu_timer_clock_prescaler_config(uint32_t timer_clock_prescaler) void rcu_tli_clock_div_config(uint32_t pllsai_r_div) { uint32_t reg; - + reg = RCU_CFG1; /* reset the PLLSAIRDIV bit and set according to pllsai_r_div */ reg &= ~RCU_CFG1_PLLSAIRDIV; @@ -735,9 +782,9 @@ void rcu_all_reset_flag_clear(void) \brief get the clock stabilization interrupt and ckm flags \param[in] int_flag: interrupt and ckm flags, refer to rcu_int_flag_enum only one parameter can be selected which is shown as below: - \arg RCU_INT_FLAG_IRC32KSTB: IRC40K stabilization interrupt flag + \arg RCU_INT_FLAG_IRC32KSTB: IRC32K stabilization interrupt flag \arg RCU_INT_FLAG_LXTALSTB: LXTAL stabilization interrupt flag - \arg RCU_INT_FLAG_IRC8MSTB: IRC8M stabilization interrupt flag + \arg RCU_INT_FLAG_IRC16MSTB: IRC16M stabilization interrupt flag \arg RCU_INT_FLAG_HXTALSTB: HXTAL stabilization interrupt flag \arg RCU_INT_FLAG_PLLSTB: PLL stabilization interrupt flag \arg RCU_INT_FLAG_PLLI2SSTB: PLLI2S stabilization interrupt flag @@ -759,7 +806,7 @@ FlagStatus rcu_interrupt_flag_get(rcu_int_flag_enum int_flag) /*! \brief clear the interrupt flags - \param[in] int_flag_clear: clock stabilization and stuck interrupt flags clear, refer to rcu_int_flag_clear_enum + \param[in] int_flag: clock stabilization and stuck interrupt flags clear, refer to rcu_int_flag_clear_enum only one parameter can be selected which is shown as below: \arg RCU_INT_FLAG_IRC32KSTB_CLR: IRC32K stabilization interrupt flag clear \arg RCU_INT_FLAG_LXTALSTB_CLR: LXTAL stabilization interrupt flag clear @@ -773,14 +820,14 @@ FlagStatus rcu_interrupt_flag_get(rcu_int_flag_enum int_flag) \param[out] none \retval none */ -void rcu_interrupt_flag_clear(rcu_int_flag_clear_enum int_flag_clear) +void rcu_interrupt_flag_clear(rcu_int_flag_clear_enum int_flag) { - RCU_REG_VAL(int_flag_clear) |= BIT(RCU_BIT_POS(int_flag_clear)); + RCU_REG_VAL(int_flag) |= BIT(RCU_BIT_POS(int_flag)); } /*! \brief enable the stabilization interrupt - \param[in] stab_int: clock stabilization interrupt, refer to rcu_int_enum + \param[in] interrupt: clock stabilization interrupt, refer to rcu_int_enum Only one parameter can be selected which is shown as below: \arg RCU_INT_IRC32KSTB: IRC32K stabilization interrupt enable \arg RCU_INT_LXTALSTB: LXTAL stabilization interrupt enable @@ -793,15 +840,15 @@ void rcu_interrupt_flag_clear(rcu_int_flag_clear_enum int_flag_clear) \param[out] none \retval none */ -void rcu_interrupt_enable(rcu_int_enum stab_int) +void rcu_interrupt_enable(rcu_int_enum interrupt) { - RCU_REG_VAL(stab_int) |= BIT(RCU_BIT_POS(stab_int)); + RCU_REG_VAL(interrupt) |= BIT(RCU_BIT_POS(interrupt)); } /*! \brief disable the stabilization interrupt - \param[in] stab_int: clock stabilization interrupt, refer to rcu_int_enum + \param[in] interrupt: clock stabilization interrupt, refer to rcu_int_enum only one parameter can be selected which is shown as below: \arg RCU_INT_IRC32KSTB: IRC32K stabilization interrupt disable \arg RCU_INT_LXTALSTB: LXTAL stabilization interrupt disable @@ -814,9 +861,9 @@ void rcu_interrupt_enable(rcu_int_enum stab_int) \param[out] none \retval none */ -void rcu_interrupt_disable(rcu_int_enum stab_int) +void rcu_interrupt_disable(rcu_int_enum interrupt) { - RCU_REG_VAL(stab_int) &= ~BIT(RCU_BIT_POS(stab_int)); + RCU_REG_VAL(interrupt) &= ~BIT(RCU_BIT_POS(interrupt)); } /*! @@ -831,9 +878,9 @@ void rcu_interrupt_disable(rcu_int_enum stab_int) void rcu_lxtal_drive_capability_config(uint32_t lxtal_dricap) { uint32_t reg; - + reg = RCU_BDCTL; - + /* reset the LXTALDRI bits and set according to lxtal_dricap */ reg &= ~RCU_BDCTL_LXTALDRI; RCU_BDCTL = (reg | lxtal_dricap); @@ -859,7 +906,7 @@ ErrStatus rcu_osci_stab_wait(rcu_osci_type_enum osci) uint32_t stb_cnt = 0U; ErrStatus reval = ERROR; FlagStatus osci_stat = RESET; - + switch(osci){ /* wait HXTAL stable */ case RCU_HXTAL: @@ -867,7 +914,7 @@ ErrStatus rcu_osci_stab_wait(rcu_osci_type_enum osci) osci_stat = rcu_flag_get(RCU_FLAG_HXTALSTB); stb_cnt++; } - + /* check whether flag is set */ if(RESET != rcu_flag_get(RCU_FLAG_HXTALSTB)){ reval = SUCCESS; @@ -879,31 +926,31 @@ ErrStatus rcu_osci_stab_wait(rcu_osci_type_enum osci) osci_stat = rcu_flag_get(RCU_FLAG_LXTALSTB); stb_cnt++; } - + /* check whether flag is set */ if(RESET != rcu_flag_get(RCU_FLAG_LXTALSTB)){ reval = SUCCESS; } break; - /* wait IRC16M stable */ + /* wait IRC16M stable */ case RCU_IRC16M: while((RESET == osci_stat) && (IRC16M_STARTUP_TIMEOUT != stb_cnt)){ osci_stat = rcu_flag_get(RCU_FLAG_IRC16MSTB); stb_cnt++; } - + /* check whether flag is set */ if(RESET != rcu_flag_get(RCU_FLAG_IRC16MSTB)){ reval = SUCCESS; } break; - /* wait IRC48M stable */ + /* wait IRC48M stable */ case RCU_IRC48M: while((RESET == osci_stat) && (OSC_STARTUP_TIMEOUT != stb_cnt)){ osci_stat = rcu_flag_get(RCU_FLAG_IRC48MSTB); stb_cnt++; } - + /* check whether flag is set */ if (RESET != rcu_flag_get(RCU_FLAG_IRC48MSTB)){ reval = SUCCESS; @@ -915,19 +962,19 @@ ErrStatus rcu_osci_stab_wait(rcu_osci_type_enum osci) osci_stat = rcu_flag_get(RCU_FLAG_IRC32KSTB); stb_cnt++; } - + /* check whether flag is set */ if(RESET != rcu_flag_get(RCU_FLAG_IRC32KSTB)){ reval = SUCCESS; } break; - /* wait PLL stable */ + /* wait PLL stable */ case RCU_PLL_CK: while((RESET == osci_stat) && (OSC_STARTUP_TIMEOUT != stb_cnt)){ osci_stat = rcu_flag_get(RCU_FLAG_PLLSTB); stb_cnt++; } - + /* check whether flag is set */ if(RESET != rcu_flag_get(RCU_FLAG_PLLSTB)){ reval = SUCCESS; @@ -939,29 +986,29 @@ ErrStatus rcu_osci_stab_wait(rcu_osci_type_enum osci) osci_stat = rcu_flag_get(RCU_FLAG_PLLI2SSTB); stb_cnt++; } - + /* check whether flag is set */ if(RESET != rcu_flag_get(RCU_FLAG_PLLI2SSTB)){ reval = SUCCESS; } break; - /* wait PLLSAI stable */ + /* wait PLLSAI stable */ case RCU_PLLSAI_CK: while((RESET == osci_stat) && (OSC_STARTUP_TIMEOUT != stb_cnt)){ osci_stat = rcu_flag_get(RCU_FLAG_PLLSAISTB); stb_cnt++; } - + /* check whether flag is set */ if(RESET != rcu_flag_get(RCU_FLAG_PLLSAISTB)){ reval = SUCCESS; } break; - + default: break; } - + /* return value */ return reval; } @@ -1010,8 +1057,8 @@ void rcu_osci_off(rcu_osci_type_enum osci) \brief enable the oscillator bypass mode, HXTALEN or LXTALEN must be reset before it \param[in] osci: oscillator types, refer to rcu_osci_type_enum only one parameter can be selected which is shown as below: - \arg RCU_HXTAL: HXTAL - \arg RCU_LXTAL: LXTAL + \arg RCU_HXTAL: high speed crystal oscillator(HXTAL) + \arg RCU_LXTAL: low speed crystal oscillator(LXTAL) \param[out] none \retval none */ @@ -1020,7 +1067,7 @@ void rcu_osci_bypass_mode_enable(rcu_osci_type_enum osci) uint32_t reg; switch(osci){ - /* enable HXTAL to bypass mode */ + /* enable HXTAL to bypass mode */ case RCU_HXTAL: reg = RCU_CTL; RCU_CTL &= ~RCU_CTL_HXTALEN; @@ -1037,7 +1084,7 @@ void rcu_osci_bypass_mode_enable(rcu_osci_type_enum osci) case RCU_IRC32K: case RCU_PLL_CK: case RCU_PLLI2S_CK: - case RCU_PLLSAI_CK: + case RCU_PLLSAI_CK: break; default: break; @@ -1048,17 +1095,17 @@ void rcu_osci_bypass_mode_enable(rcu_osci_type_enum osci) \brief disable the oscillator bypass mode, HXTALEN or LXTALEN must be reset before it \param[in] osci: oscillator types, refer to rcu_osci_type_enum only one parameter can be selected which is shown as below: - \arg RCU_HXTAL: HXTAL - \arg RCU_LXTAL: LXTAL + \arg RCU_HXTAL: high speed crystal oscillator(HXTAL) + \arg RCU_LXTAL: low speed crystal oscillator(LXTAL) \param[out] none \retval none */ void rcu_osci_bypass_mode_disable(rcu_osci_type_enum osci) { uint32_t reg; - + switch(osci){ - /* disable HXTAL to bypass mode */ + /* disable HXTAL to bypass mode */ case RCU_HXTAL: reg = RCU_CTL; RCU_CTL &= ~RCU_CTL_HXTALEN; @@ -1075,7 +1122,7 @@ void rcu_osci_bypass_mode_disable(rcu_osci_type_enum osci) case RCU_IRC32K: case RCU_PLL_CK: case RCU_PLLI2S_CK: - case RCU_PLLSAI_CK: + case RCU_PLLSAI_CK: break; default: break; @@ -1108,17 +1155,18 @@ void rcu_hxtal_clock_monitor_disable(void) /*! \brief set the IRC16M adjust value \param[in] irc16m_adjval: IRC16M adjust value, must be between 0 and 0x1F + \arg 0x00 - 0x1F \param[out] none \retval none */ void rcu_irc16m_adjust_value_set(uint32_t irc16m_adjval) { uint32_t reg; - + reg = RCU_CTL; /* reset the IRC16MADJ bits and set according to irc16m_adjval */ reg &= ~RCU_CTL_IRC16MADJ; - RCU_CTL = (reg | ((irc16m_adjval & 0x1FU) << 3)); + RCU_CTL = (reg | ((irc16m_adjval & RCU_IRC16M_ADJUST_MASK) << RCU_IRC16M_ADJUST_OFFSET)); } /*! @@ -1144,7 +1192,7 @@ void rcu_voltage_key_unlock(void) \retval none */ void rcu_deepsleep_voltage_set(uint32_t dsvol) -{ +{ dsvol &= RCU_DSV_DSLPVS; RCU_DSV = dsvol; } @@ -1155,16 +1203,16 @@ void rcu_deepsleep_voltage_set(uint32_t dsvol) \arg RCU_SS_TYPE_CENTER: center spread type is selected \arg RCU_SS_TYPE_DOWN: down spread type is selected \param[in] modstep: configure PLL spread spectrum modulation profile amplitude and frequency - \arg This parameter should be selected between 0 and 7FFF.The following criteria must be met: MODSTEP*MODCNT=215-1 + \arg This parameter should be selected between 0 and 7FFF.The following criteria must be met: MODSTEP*MODCNT <=2^15-1 \param[in] modcnt: configure PLL spread spectrum modulation profile amplitude and frequency - \arg This parameter should be selected between 0 and 1FFF.The following criteria must be met: MODSTEP*MODCNT=215-1 + \arg This parameter should be selected between 0 and 1FFF.The following criteria must be met: MODSTEP*MODCNT <=2^15-1 \param[out] none \retval none */ void rcu_spread_spectrum_config(uint32_t spread_spectrum_type, uint32_t modstep, uint32_t modcnt) { uint32_t reg; - + reg = RCU_PLLSSCTL; /* reset the RCU_PLLSSCTL register bits */ reg &= ~(RCU_PLLSSCTL_MODCNT | RCU_PLLSSCTL_MODSTEP | RCU_PLLSSCTL_SS_TYPE); @@ -1209,7 +1257,7 @@ uint32_t rcu_clock_freq_get(rcu_clock_freq_enum clock) uint32_t sws, ck_freq = 0U; uint32_t cksys_freq, ahb_freq, apb1_freq, apb2_freq; uint32_t pllpsc, plln, pllsel, pllp, ck_src, idx, clk_exp; - + /* exponent of AHB, APB1 and APB2 clock divider */ const uint8_t ahb_exp[16] = {0, 0, 0, 0, 0, 0, 0, 0, 1, 2, 3, 4, 6, 7, 8, 9}; const uint8_t apb1_exp[8] = {0, 0, 0, 0, 1, 2, 3, 4}; @@ -1231,7 +1279,7 @@ uint32_t rcu_clock_freq_get(rcu_clock_freq_enum clock) pllpsc = GET_BITS(RCU_PLL, 0U, 5U); plln = GET_BITS(RCU_PLL, 6U, 14U); pllp = (GET_BITS(RCU_PLL, 16U, 17U) + 1U) * 2U; - /* PLL clock source selection, HXTAL or IRC8M/2 */ + /* PLL clock source selection, HXTAL or IRC16M/2 */ pllsel = (RCU_PLL & RCU_PLL_PLLSEL); if (RCU_PLLSRC_HXTAL == pllsel) { ck_src = HXTAL_VALUE; @@ -1249,17 +1297,17 @@ uint32_t rcu_clock_freq_get(rcu_clock_freq_enum clock) idx = GET_BITS(RCU_CFG0, 4, 7); clk_exp = ahb_exp[idx]; ahb_freq = cksys_freq >> clk_exp; - + /* calculate APB1 clock frequency */ idx = GET_BITS(RCU_CFG0, 10, 12); clk_exp = apb1_exp[idx]; apb1_freq = ahb_freq >> clk_exp; - + /* calculate APB2 clock frequency */ idx = GET_BITS(RCU_CFG0, 13, 15); clk_exp = apb2_exp[idx]; apb2_freq = ahb_freq >> clk_exp; - + /* return the clocks frequency */ switch(clock){ case CK_SYS: diff --git a/bsp/gd32450z-eval/Libraries/GD32F4xx_standard_peripheral/Source/gd32f4xx_rtc.c b/bsp/gd32450z-eval/Libraries/GD32F4xx_standard_peripheral/Source/gd32f4xx_rtc.c index 8e2713ceb1..12ee6c3207 100644 --- a/bsp/gd32450z-eval/Libraries/GD32F4xx_standard_peripheral/Source/gd32f4xx_rtc.c +++ b/bsp/gd32450z-eval/Libraries/GD32F4xx_standard_peripheral/Source/gd32f4xx_rtc.c @@ -1,14 +1,40 @@ /*! - \file gd32f4xx_rtc.c - \brief RTC driver + \file gd32f4xx_rtc.c + \brief RTC driver + + \version 2016-08-15, V1.0.0, firmware for GD32F4xx + \version 2018-12-12, V2.0.0, firmware for GD32F4xx + \version 2020-09-30, V2.1.0, firmware for GD32F4xx */ /* - Copyright (C) 2016 GigaDevice + Copyright (c) 2020, GigaDevice Semiconductor Inc. + + Redistribution and use in source and binary forms, with or without modification, +are permitted provided that the following conditions are met: + + 1. Redistributions of source code must retain the above copyright notice, this + list of conditions and the following disclaimer. + 2. Redistributions in binary form must reproduce the above copyright notice, + this list of conditions and the following disclaimer in the documentation + and/or other materials provided with the distribution. + 3. Neither the name of the copyright holder nor the names of its contributors + may be used to endorse or promote products derived from this software without + specific prior written permission. - 2016-08-15, V1.0.0, firmware for GD32F4xx + THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED +WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. +IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, +INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT +NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR +PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, +WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY +OF SUCH DAMAGE. */ + #include "gd32f4xx_rtc.h" /* RTC timeout value */ @@ -42,7 +68,7 @@ ErrStatus rtc_deinit(void) error_status = rtc_init_mode_enter(); if(ERROR != error_status){ - /* reset RTC_CTL register, but RTC_CTL[2��0] */ + /* reset RTC_CTL register, but RTC_CTL[2��0] */ RTC_CTL &= (RTC_REGISTER_RESET | RTC_CTL_WTCS); /* before reset RTC_TIME and RTC_DATE, BPSHAD bit in RTC_CTL should be reset as the condition. in order to read calendar from shadow register, not the real registers being reset */ @@ -50,7 +76,7 @@ ErrStatus rtc_deinit(void) RTC_DATE = RTC_DATE_RESET; RTC_PSC = RTC_PSC_RESET; - /* only when RTC_CTL_WTEN=0 and RTC_STAT_WTWF=1 can write RTC_CTL[2��0] */ + /* only when RTC_CTL_WTEN=0 and RTC_STAT_WTWF=1 can write RTC_CTL[2��0] */ /* wait until the WTWF flag to be set */ do{ flag_status = RTC_STAT & RTC_STAT_WTWF; @@ -63,7 +89,7 @@ ErrStatus rtc_deinit(void) RTC_WUT = RTC_WUT_RESET; RTC_COSC = RTC_REGISTER_RESET; /* to write RTC_ALRMxSS register, ALRMxEN bit in RTC_CTL register should be reset as the condition */ - RTC_ALRM0TD = RTC_REGISTER_RESET; + RTC_ALRM0TD = RTC_REGISTER_RESET; RTC_ALRM1TD = RTC_REGISTER_RESET; RTC_ALRM0SS = RTC_REGISTER_RESET; RTC_ALRM1SS = RTC_REGISTER_RESET; @@ -71,9 +97,9 @@ ErrStatus rtc_deinit(void) at the same time, RTC_STAT_SOPF bit is reset, as the condition to reset RTC_SHIFTCTL register later */ RTC_STAT = RTC_STAT_RESET; /* reset RTC_SHIFTCTL and RTC_HRFC register, this can be done without the init mode */ - RTC_SHIFTCTL = RTC_REGISTER_RESET; + RTC_SHIFTCTL = RTC_REGISTER_RESET; RTC_HRFC = RTC_REGISTER_RESET; - error_status = rtc_register_sync_wait(); + error_status = rtc_register_sync_wait(); } } @@ -85,7 +111,7 @@ ErrStatus rtc_deinit(void) /*! \brief initialize RTC registers - \param[in] rtc_initpara_struct: pointer to a rtc_parameter_struct structure which contains + \param[in] rtc_initpara_struct: pointer to a rtc_parameter_struct structure which contains parameters for initialization of the rtc peripheral members of the structure and the member values are shown as below: year: 0x0 - 0x99(BCD format) @@ -112,13 +138,13 @@ ErrStatus rtc_init(rtc_parameter_struct* rtc_initpara_struct) reg_date = (DATE_YR(rtc_initpara_struct->year) | \ DATE_DOW(rtc_initpara_struct->day_of_week) | \ DATE_MON(rtc_initpara_struct->month) | \ - DATE_DAY(rtc_initpara_struct->date)); - + DATE_DAY(rtc_initpara_struct->date)); + reg_time = (rtc_initpara_struct->am_pm| \ TIME_HR(rtc_initpara_struct->hour) | \ TIME_MN(rtc_initpara_struct->minute) | \ - TIME_SC(rtc_initpara_struct->second)); - + TIME_SC(rtc_initpara_struct->second)); + /* 1st: disable the write protection */ RTC_WPK = RTC_UNLOCK_KEY1; RTC_WPK = RTC_UNLOCK_KEY2; @@ -126,7 +152,7 @@ ErrStatus rtc_init(rtc_parameter_struct* rtc_initpara_struct) /* 2nd: enter init mode */ error_status = rtc_init_mode_enter(); - if(ERROR != error_status){ + if(ERROR != error_status){ RTC_PSC = (uint32_t)(PSC_FACTOR_A(rtc_initpara_struct->factor_asyn)| \ PSC_FACTOR_S(rtc_initpara_struct->factor_syn)); @@ -135,11 +161,11 @@ ErrStatus rtc_init(rtc_parameter_struct* rtc_initpara_struct) RTC_CTL &= (uint32_t)(~RTC_CTL_CS); RTC_CTL |= rtc_initpara_struct->display_format; - - /* 3rd: exit init mode */ + + /* 3rd: exit init mode */ rtc_init_mode_exit(); - - /* 4th: wait the RSYNF flag to set */ + + /* 4th: wait the RSYNF flag to set */ error_status = rtc_register_sync_wait(); } @@ -162,15 +188,15 @@ ErrStatus rtc_init_mode_enter(void) ErrStatus error_status = ERROR; /* check whether it has been in init mode */ - if ((uint32_t)RESET == (RTC_STAT & RTC_STAT_INITF)){ + if ((uint32_t)RESET == (RTC_STAT & RTC_STAT_INITF)){ RTC_STAT |= RTC_STAT_INITM; - + /* wait until the INITF flag to be set */ do{ flag_status = RTC_STAT & RTC_STAT_INITF; }while((--time_index > 0U) && ((uint32_t)RESET == flag_status)); - if ((uint32_t)RESET != flag_status){ + if ((uint32_t)RESET != flag_status){ error_status = SUCCESS; } }else{ @@ -191,7 +217,7 @@ void rtc_init_mode_exit(void) } /*! - \brief wait until RTC_TIME and RTC_DATE registers are synchronized with APB clock, and the shadow + \brief wait until RTC_TIME and RTC_DATE registers are synchronized with APB clock, and the shadow registers are updated \param[in] none \param[out] none @@ -216,13 +242,13 @@ ErrStatus rtc_register_sync_wait(void) flag_status = RTC_STAT & RTC_STAT_RSYNF; }while((--time_index > 0U) && ((uint32_t)RESET == flag_status)); - if ((uint32_t)RESET != flag_status){ + if ((uint32_t)RESET != flag_status){ error_status = SUCCESS; } - + /* enable the write protection */ RTC_WPK = RTC_LOCK_KEY; - }else{ + }else{ error_status = SUCCESS; } @@ -232,7 +258,7 @@ ErrStatus rtc_register_sync_wait(void) /*! \brief get current time and date \param[in] none - \param[out] rtc_initpara_struct: pointer to a rtc_parameter_struct structure which contains + \param[out] rtc_initpara_struct: pointer to a rtc_parameter_struct structure which contains parameters for initialization of the rtc peripheral members of the structure and the member values are shown as below: year: 0x0 - 0x99(BCD format) @@ -254,22 +280,22 @@ void rtc_current_time_get(rtc_parameter_struct* rtc_initpara_struct) { uint32_t temp_tr = 0U, temp_dr = 0U, temp_pscr = 0U, temp_ctlr = 0U; - temp_tr = (uint32_t)RTC_TIME; + temp_tr = (uint32_t)RTC_TIME; temp_dr = (uint32_t)RTC_DATE; temp_pscr = (uint32_t)RTC_PSC; temp_ctlr = (uint32_t)RTC_CTL; - + /* get current time and construct rtc_parameter_struct structure */ rtc_initpara_struct->year = (uint8_t)GET_DATE_YR(temp_dr); rtc_initpara_struct->month = (uint8_t)GET_DATE_MON(temp_dr); rtc_initpara_struct->date = (uint8_t)GET_DATE_DAY(temp_dr); - rtc_initpara_struct->day_of_week = (uint8_t)GET_DATE_DOW(temp_dr); + rtc_initpara_struct->day_of_week = (uint8_t)GET_DATE_DOW(temp_dr); rtc_initpara_struct->hour = (uint8_t)GET_TIME_HR(temp_tr); rtc_initpara_struct->minute = (uint8_t)GET_TIME_MN(temp_tr); rtc_initpara_struct->second = (uint8_t)GET_TIME_SC(temp_tr); rtc_initpara_struct->factor_asyn = (uint16_t)GET_PSC_FACTOR_A(temp_pscr); rtc_initpara_struct->factor_syn = (uint16_t)GET_PSC_FACTOR_S(temp_pscr); - rtc_initpara_struct->am_pm = (uint32_t)(temp_pscr & RTC_TIME_PM); + rtc_initpara_struct->am_pm = (uint32_t)(temp_pscr & RTC_TIME_PM); rtc_initpara_struct->display_format = (uint32_t)(temp_ctlr & RTC_CTL_CS); } @@ -293,7 +319,7 @@ uint32_t rtc_subsecond_get(void) /*! \brief configure RTC alarm \param[in] rtc_alarm: RTC_ALARM0 or RTC_ALARM1 - \param[in] rtc_alarm_time: pointer to a rtc_alarm_struct structure which contains + \param[in] rtc_alarm_time: pointer to a rtc_alarm_struct structure which contains parameters for RTC alarm configuration members of the structure and the member values are shown as below: alarm_mask: RTC_ALARM_NONE_MASK, RTC_ALARM_DATE_MASK, RTC_ALARM_HOUR_MASK @@ -327,7 +353,7 @@ void rtc_alarm_config(uint8_t rtc_alarm, rtc_alarm_struct* rtc_alarm_time) if(RTC_ALARM0 == rtc_alarm){ RTC_ALRM0TD = (uint32_t)reg_alrmtd; - + }else{ RTC_ALRM1TD = (uint32_t)reg_alrmtd; } @@ -363,12 +389,12 @@ void rtc_alarm_subsecond_config(uint8_t rtc_alarm, uint32_t mask_subsecond, uint { /* disable the write protection */ RTC_WPK = RTC_UNLOCK_KEY1; - RTC_WPK = RTC_UNLOCK_KEY2; + RTC_WPK = RTC_UNLOCK_KEY2; if(RTC_ALARM0 == rtc_alarm){ - RTC_ALRM0SS = mask_subsecond | subsecond; + RTC_ALRM0SS = mask_subsecond | subsecond; }else{ - RTC_ALRM1SS = mask_subsecond | subsecond; + RTC_ALRM1SS = mask_subsecond | subsecond; } /* enable the write protection */ RTC_WPK = RTC_LOCK_KEY; @@ -377,7 +403,7 @@ void rtc_alarm_subsecond_config(uint8_t rtc_alarm, uint32_t mask_subsecond, uint /*! \brief get RTC alarm \param[in] rtc_alarm: RTC_ALARM0 or RTC_ALARM1 - \param[out] rtc_alarm_time: pointer to a rtc_alarm_struct structure which contains + \param[out] rtc_alarm_time: pointer to a rtc_alarm_struct structure which contains parameters for RTC alarm configuration members of the structure and the member values are shown as below: alarm_mask: RTC_ALARM_NONE_MASK, RTC_ALARM_DATE_MASK, RTC_ALARM_HOUR_MASK @@ -403,13 +429,13 @@ void rtc_alarm_get(uint8_t rtc_alarm, rtc_alarm_struct* rtc_alarm_time) reg_alrmtd = RTC_ALRM1TD; } /* get alarm parameters and construct the rtc_alarm_struct structure */ - rtc_alarm_time->alarm_mask = reg_alrmtd & RTC_ALARM_ALL_MASK; + rtc_alarm_time->alarm_mask = reg_alrmtd & RTC_ALARM_ALL_MASK; rtc_alarm_time->am_pm = (uint32_t)(reg_alrmtd & RTC_ALRMXTD_PM); rtc_alarm_time->weekday_or_date = (uint32_t)(reg_alrmtd & RTC_ALRMXTD_DOWS); rtc_alarm_time->alarm_day = (uint8_t)GET_ALRMTD_DAY(reg_alrmtd); rtc_alarm_time->alarm_hour = (uint8_t)GET_ALRMTD_HR(reg_alrmtd); rtc_alarm_time->alarm_minute = (uint8_t)GET_ALRMTD_MN(reg_alrmtd); - rtc_alarm_time->alarm_second = (uint8_t)GET_ALRMTD_SC(reg_alrmtd); + rtc_alarm_time->alarm_second = (uint8_t)GET_ALRMTD_SC(reg_alrmtd); } /*! @@ -463,23 +489,23 @@ ErrStatus rtc_alarm_disable(uint8_t rtc_alarm) /* disable the write protection */ RTC_WPK = RTC_UNLOCK_KEY1; RTC_WPK = RTC_UNLOCK_KEY2; - + /* clear the state of alarm */ if(RTC_ALARM0 == rtc_alarm){ - RTC_CTL &= (uint32_t)(~RTC_CTL_ALRM0EN); + RTC_CTL &= (uint32_t)(~RTC_CTL_ALRM0EN); /* wait until ALRM0WF flag to be set after the alarm is disabled */ do{ flag_status = RTC_STAT & RTC_STAT_ALRM0WF; - }while((--time_index > 0U) && ((uint32_t)RESET == flag_status)); + }while((--time_index > 0U) && ((uint32_t)RESET == flag_status)); }else{ - RTC_CTL &= (uint32_t)(~RTC_CTL_ALRM1EN); + RTC_CTL &= (uint32_t)(~RTC_CTL_ALRM1EN); /* wait until ALRM1WF flag to be set after the alarm is disabled */ do{ flag_status = RTC_STAT & RTC_STAT_ALRM1WF; }while((--time_index > 0U) && ((uint32_t)RESET == flag_status)); } - - if ((uint32_t)RESET != flag_status){ + + if ((uint32_t)RESET != flag_status){ error_status = SUCCESS; } @@ -506,7 +532,7 @@ void rtc_timestamp_enable(uint32_t edge) /* new configuration */ reg_ctl |= (uint32_t)(edge | RTC_CTL_TSEN); - + /* disable the write protection */ RTC_WPK = RTC_UNLOCK_KEY1; RTC_WPK = RTC_UNLOCK_KEY2; @@ -528,7 +554,7 @@ void rtc_timestamp_disable(void) /* disable the write protection */ RTC_WPK = RTC_UNLOCK_KEY1; RTC_WPK = RTC_UNLOCK_KEY2; - + /* clear the TSEN bit */ RTC_CTL &= (uint32_t)(~ RTC_CTL_TSEN); @@ -539,7 +565,7 @@ void rtc_timestamp_disable(void) /*! \brief get RTC timestamp time and date \param[in] none - \param[out] rtc_timestamp: pointer to a rtc_timestamp_struct structure which contains + \param[out] rtc_timestamp: pointer to a rtc_timestamp_struct structure which contains parameters for RTC time-stamp configuration members of the structure and the member values are shown as below: timestamp_month: RTC_JAN, RTC_FEB, RTC_MAR, RTC_APR, RTC_MAY, RTC_JUN, @@ -560,7 +586,7 @@ void rtc_timestamp_get(rtc_timestamp_struct* rtc_timestamp) /* get the value of time_stamp registers */ temp_tts = (uint32_t)RTC_TTS; temp_dts = (uint32_t)RTC_DTS; - + /* get timestamp time and construct the rtc_timestamp_struct structure */ rtc_timestamp->am_pm = (uint32_t)(temp_tts & RTC_TTS_PM); rtc_timestamp->timestamp_month = (uint8_t)GET_DTS_MON(temp_dts); @@ -583,7 +609,7 @@ uint32_t rtc_timestamp_subsecond_get(void) } /*! - \brief RTC time-stamp mapping + \brief RTC time-stamp mapping \param[in] rtc_af: \arg RTC_AF0_TIMESTAMP: RTC_AF0 use for timestamp \arg RTC_AF1_TIMESTAMP: RTC_AF1 use for timestamp @@ -598,13 +624,19 @@ void rtc_timestamp_pin_map(uint32_t rtc_af) /*! \brief enable RTC tamper - \param[in] rtc_tamper: pointer to a rtc_tamper_struct structure which contains + \param[in] rtc_tamper: pointer to a rtc_tamper_struct structure which contains parameters for RTC tamper configuration members of the structure and the member values are shown as below: + detecting tamper event can using edge mode or level mode + (1) using edge mode configuration: tamper_source: RTC_TAMPER0, RTC_TAMPER1 tamper_trigger: RTC_TAMPER_TRIGGER_EDGE_RISING, RTC_TAMPER_TRIGGER_EDGE_FALLING - RTC_TAMPER_TRIGGER_LEVEL_LOW, RTC_TAMPER_TRIGGER_LEVEL_HIGH - tamper_filter: RTC_FLT_EDGE, RTC_FLT_2S, RTC_FLT_4S, RTC_FLT_8S + tamper_filter: RTC_FLT_EDGE + tamper_with_timestamp: DISABLE, ENABLE + (2) using level mode configuration: + tamper_source: RTC_TAMPER0, RTC_TAMPER1 + tamper_trigger:RTC_TAMPER_TRIGGER_LEVEL_LOW, RTC_TAMPER_TRIGGER_LEVEL_HIGH + tamper_filter: RTC_FLT_2S, RTC_FLT_4S, RTC_FLT_8S tamper_sample_frequency: RTC_FREQ_DIV32768, RTC_FREQ_DIV16384, RTC_FREQ_DIV8192, RTC_FREQ_DIV4096, RTC_FREQ_DIV2048, RTC_FREQ_DIV1024, RTC_FREQ_DIV512, RTC_FREQ_DIV256 @@ -617,40 +649,46 @@ void rtc_timestamp_pin_map(uint32_t rtc_af) void rtc_tamper_enable(rtc_tamper_struct* rtc_tamper) { /* disable tamper */ - RTC_TAMP &= (uint32_t)~(rtc_tamper->tamper_source); + RTC_TAMP &= (uint32_t)~(rtc_tamper->tamper_source); /* tamper filter must be used when the tamper source is voltage level detection */ RTC_TAMP &= (uint32_t)~RTC_TAMP_FLT; - + /* the tamper source is voltage level detection */ - if((uint32_t)(rtc_tamper->tamper_filter) != RTC_FLT_EDGE ){ + if((uint32_t)(rtc_tamper->tamper_filter) != RTC_FLT_EDGE ){ RTC_TAMP &= (uint32_t)~(RTC_TAMP_DISPU | RTC_TAMP_PRCH | RTC_TAMP_FREQ | RTC_TAMP_FLT); /* check if the tamper pin need precharge, if need, then configure the precharge time */ if(DISABLE == rtc_tamper->tamper_precharge_enable){ - RTC_TAMP |= (uint32_t)RTC_TAMP_DISPU; + RTC_TAMP |= (uint32_t)RTC_TAMP_DISPU; }else{ RTC_TAMP |= (uint32_t)(rtc_tamper->tamper_precharge_time); } RTC_TAMP |= (uint32_t)(rtc_tamper->tamper_sample_frequency); RTC_TAMP |= (uint32_t)(rtc_tamper->tamper_filter); + + /* configure the tamper trigger */ + RTC_TAMP &= ((uint32_t)~((rtc_tamper->tamper_source) << RTC_TAMPER_TRIGGER_POS)); + if(RTC_TAMPER_TRIGGER_LEVEL_LOW != rtc_tamper->tamper_trigger){ + RTC_TAMP |= (uint32_t)((rtc_tamper->tamper_source)<< RTC_TAMPER_TRIGGER_POS); + } + }else{ + + /* configure the tamper trigger */ + RTC_TAMP &= ((uint32_t)~((rtc_tamper->tamper_source) << RTC_TAMPER_TRIGGER_POS)); + if(RTC_TAMPER_TRIGGER_EDGE_RISING != rtc_tamper->tamper_trigger){ + RTC_TAMP |= (uint32_t)((rtc_tamper->tamper_source)<< RTC_TAMPER_TRIGGER_POS); + } } - - RTC_TAMP &= (uint32_t)~RTC_TAMP_TPTS; - - if(DISABLE != rtc_tamper->tamper_with_timestamp){ + + RTC_TAMP &= (uint32_t)~RTC_TAMP_TPTS; + if(DISABLE != rtc_tamper->tamper_with_timestamp){ /* the tamper event also cause a time-stamp event */ RTC_TAMP |= (uint32_t)RTC_TAMP_TPTS; - } - - /* configure the tamper trigger */ - RTC_TAMP &= ((uint32_t)~((rtc_tamper->tamper_source) << RTC_TAMPER_TRIGGER_POS)); - if(RTC_TAMPER_TRIGGER_EDGE_RISING != rtc_tamper->tamper_trigger){ - RTC_TAMP |= (uint32_t)((rtc_tamper->tamper_source)<< RTC_TAMPER_TRIGGER_POS); - } + } /* enable tamper */ - RTC_TAMP |= (uint32_t)(rtc_tamper->tamper_source); + RTC_TAMP |= (uint32_t)(rtc_tamper->tamper_source); } /*! @@ -664,12 +702,12 @@ void rtc_tamper_enable(rtc_tamper_struct* rtc_tamper) void rtc_tamper_disable(uint32_t source) { /* disable tamper */ - RTC_TAMP &= (uint32_t)~source; + RTC_TAMP &= (uint32_t)~source; } /*! - \brief RTC tamper0 mapping + \brief RTC tamper0 mapping \param[in] rtc_af: \arg RTC_AF0_TAMPER0: RTC_AF0 use for tamper0 \arg RTC_AF1_TAMPER0: RTC_AF1 use for tamper0 @@ -681,30 +719,31 @@ void rtc_tamper0_pin_map(uint32_t rtc_af) RTC_TAMP &= ~(RTC_TAMP_TP0EN | RTC_TAMP_TP0SEL); RTC_TAMP |= rtc_af; } + /*! \brief enable specified RTC interrupt \param[in] interrupt: specify which interrupt source to be enabled \arg RTC_INT_TIMESTAMP: timestamp interrupt \arg RTC_INT_ALARM0: alarm0 interrupt \arg RTC_INT_ALARM1: alarm1 interrupt - \arg RTC_INT_TAMP: tamp interrupt + \arg RTC_INT_TAMP: tamper detection interrupt \arg RTC_INT_WAKEUP: wakeup timer interrupt \param[out] none \retval none */ void rtc_interrupt_enable(uint32_t interrupt) -{ +{ /* disable the write protection */ RTC_WPK = RTC_UNLOCK_KEY1; RTC_WPK = RTC_UNLOCK_KEY2; - + /* enable the interrupts in RTC_CTL register */ RTC_CTL |= (uint32_t)(interrupt & (uint32_t)~RTC_TAMP_TPIE); /* enable the interrupts in RTC_TAMP register */ RTC_TAMP |= (uint32_t)(interrupt & RTC_TAMP_TPIE); - + /* enable the write protection */ - RTC_WPK = RTC_LOCK_KEY; + RTC_WPK = RTC_LOCK_KEY; } /*! @@ -713,17 +752,17 @@ void rtc_interrupt_enable(uint32_t interrupt) \arg RTC_INT_TIMESTAMP: timestamp interrupt \arg RTC_INT_ALARM0: alarm interrupt \arg RTC_INT_ALARM1: alarm interrupt - \arg RTC_INT_TAMP: tamp interrupt + \arg RTC_INT_TAMP: tamper detection interrupt \arg RTC_INT_WAKEUP: wakeup timer interrupt \param[out] none \retval none */ void rtc_interrupt_disable(uint32_t interrupt) -{ +{ /* disable the write protection */ RTC_WPK = RTC_UNLOCK_KEY1; RTC_WPK = RTC_UNLOCK_KEY2; - + /* disable the interrupts in RTC_CTL register */ RTC_CTL &= (uint32_t)~(interrupt & (uint32_t)~RTC_TAMP_TPIE); /* disable the interrupts in RTC_TAMP register */ @@ -736,28 +775,28 @@ void rtc_interrupt_disable(uint32_t interrupt) /*! \brief check specified flag \param[in] flag: specify which flag to check - \arg RTC_STAT_RECPF: recalibration pending flag - \arg RTC_STAT_TP1F: tamper 1 event flag - \arg RTC_STAT_TP0F: tamper 0 event flag - \arg RTC_STAT_TSOVRF: time-stamp overflow event flag - \arg RTC_STAT_TSF: time-stamp event flag - \arg RTC_STAT_ALRM0F: alarm0 event flag - \arg RTC_STAT_ALRM1F: alarm1 event flag - \arg RTC_STAT_WTF: wakeup timer event flag - \arg RTC_STAT_INITF: init mode event flag - \arg RTC_STAT_RSYNF: time and date registers synchronized event flag - \arg RTC_STAT_YCM: year parameter configured event flag - \arg RTC_STAT_SOPF: shift operation pending flag - \arg RTC_STAT_ALRM0WF: alarm0 writen available flag - \arg RTC_STAT_ALRM1WF: alarm1 writen available flag - \arg RTC_STAT_WTWF: wakeup timer writen available flag + \arg RTC_STAT_SCP: smooth calibration pending flag + \arg RTC_FLAG_TP1: RTC tamper 1 detected flag + \arg RTC_FLAG_TP0: RTC tamper 0 detected flag + \arg RTC_FLAG_TSOVR: time-stamp overflow flag + \arg RTC_FLAG_TS: time-stamp flag + \arg RTC_FLAG_ALARM0: alarm0 occurs flag + \arg RTC_FLAG_ALARM1: alarm1 occurs flag + \arg RTC_FLAG_WT: wakeup timer occurs flag + \arg RTC_FLAG_INIT: initialization state flag + \arg RTC_FLAG_RSYN: register synchronization flag + \arg RTC_FLAG_YCM: year configuration mark status flag + \arg RTC_FLAG_SOP: shift function operation pending flag + \arg RTC_FLAG_ALRM0W: alarm0 configuration can be write flag + \arg RTC_FLAG_ALRM1W: alarm1 configuration can be write flag + \arg RTC_FLAG_WTW: wakeup timer can be write flag \param[out] none \retval FlagStatus: SET or RESET */ FlagStatus rtc_flag_get(uint32_t flag) { FlagStatus flag_state = RESET; - + if ((uint32_t)RESET != (RTC_STAT & flag)){ flag_state = SET; } @@ -766,21 +805,20 @@ FlagStatus rtc_flag_get(uint32_t flag) /*! \brief clear specified flag - \param[in] flag: specify which flag to clear - \arg RTC_STAT_TP1F: tamper 1 event flag - \arg RTC_STAT_TP0F: tamper 0 event flag - \arg RTC_STAT_TSOVRF: time-stamp overflow event flag - \arg RTC_STAT_TSF: time-stamp event flag - \arg RTC_STAT_WTF: time-stamp event flag - \arg RTC_STAT_ALRM0F: alarm0 event flag - \arg RTC_STAT_ALRM1F: alarm1 event flag - \arg RTC_STAT_RSYNF: time and date registers synchronized event flag + \arg RTC_FLAG_TP1: RTC tamper 1 detected flag + \arg RTC_FLAG_TP0: RTC tamper 0 detected flag + \arg RTC_FLAG_TSOVR: time-stamp overflow flag + \arg RTC_FLAG_TS: time-stamp flag + \arg RTC_FLAG_WT: wakeup timer occurs flag + \arg RTC_FLAG_ALARM0: alarm0 occurs flag + \arg RTC_FLAG_ALARM1: alarm1 occurs flag + \arg RTC_FLAG_RSYN: register synchronization flag \param[out] none \retval none */ void rtc_flag_clear(uint32_t flag) { - RTC_STAT &= (uint32_t)(~flag); + RTC_STAT &= (uint32_t)(~flag); } /*! @@ -818,10 +856,10 @@ void rtc_alarm_output_config(uint32_t source, uint32_t mode) /*! \brief configure rtc calibration output source \param[in] source: specify signal to output - \arg RTC_CALIBRATION_512HZ: when the LSE freqency is 32768Hz and the RTC_PSC + \arg RTC_CALIBRATION_512HZ: when the LSE freqency is 32768Hz and the RTC_PSC is the default value, output 512Hz signal - \arg RTC_CALIBRATION_1HZ: when the LSE freqency is 32768Hz and the RTC_PSC - is the default value, output 512Hz signal + \arg RTC_CALIBRATION_1HZ: when the LSE freqency is 32768Hz and the RTC_PSC + is the default value, output 1Hz signal \param[out] none \retval none */ @@ -852,7 +890,7 @@ void rtc_hour_adjust(uint32_t operation) /* disable the write protection */ RTC_WPK = RTC_UNLOCK_KEY1; RTC_WPK = RTC_UNLOCK_KEY2; - + RTC_CTL |= (uint32_t)(operation); /* enable the write protection */ @@ -877,17 +915,17 @@ ErrStatus rtc_second_adjust(uint32_t add, uint32_t minus) /* disable the write protection */ RTC_WPK = RTC_UNLOCK_KEY1; RTC_WPK = RTC_UNLOCK_KEY2; - - /* check if a shift operation is ongoing */ + + /* check if a shift operation is ongoing */ do{ flag_status = RTC_STAT & RTC_STAT_SOPF; }while((--time_index > 0U) && ((uint32_t)RESET != flag_status)); - + /* check if the function of reference clock detection is disabled */ temp = RTC_CTL & RTC_CTL_REFEN; - if((RESET == flag_status) && (RESET == temp)){ + if((RESET == flag_status) && (RESET == temp)){ RTC_SHIFTCTL = (uint32_t)(add | SHIFTCTL_SFS(minus)); - error_status = rtc_register_sync_wait(); + error_status = rtc_register_sync_wait(); } /* enable the write protection */ @@ -903,7 +941,7 @@ ErrStatus rtc_second_adjust(uint32_t add, uint32_t minus) \retval none */ void rtc_bypass_shadow_enable(void) -{ +{ /* disable the write protection */ RTC_WPK = RTC_UNLOCK_KEY1; RTC_WPK = RTC_UNLOCK_KEY2; @@ -921,7 +959,7 @@ void rtc_bypass_shadow_enable(void) \retval none */ void rtc_bypass_shadow_disable(void) -{ +{ /* disable the write protection */ RTC_WPK = RTC_UNLOCK_KEY1; RTC_WPK = RTC_UNLOCK_KEY2; @@ -941,7 +979,7 @@ void rtc_bypass_shadow_disable(void) ErrStatus rtc_refclock_detection_enable(void) { ErrStatus error_status = ERROR; - + /* disable the write protection */ RTC_WPK = RTC_UNLOCK_KEY1; RTC_WPK = RTC_UNLOCK_KEY2; @@ -970,7 +1008,7 @@ ErrStatus rtc_refclock_detection_enable(void) ErrStatus rtc_refclock_detection_disable(void) { ErrStatus error_status = ERROR; - + /* disable the write protection */ RTC_WPK = RTC_UNLOCK_KEY1; RTC_WPK = RTC_UNLOCK_KEY2; @@ -978,7 +1016,7 @@ ErrStatus rtc_refclock_detection_disable(void) /* enter init mode */ error_status = rtc_init_mode_enter(); - if(ERROR != error_status){ + if(ERROR != error_status){ RTC_CTL &= (uint32_t)~RTC_CTL_REFEN; /* exit init mode */ rtc_init_mode_exit(); @@ -1000,7 +1038,7 @@ void rtc_wakeup_enable(void) { /* disable the write protection */ RTC_WPK = RTC_UNLOCK_KEY1; - RTC_WPK = RTC_UNLOCK_KEY2; + RTC_WPK = RTC_UNLOCK_KEY2; RTC_CTL |= RTC_CTL_WTEN; @@ -1041,12 +1079,12 @@ ErrStatus rtc_wakeup_disable(void) /*! \brief set RTC auto wakeup timer clock \param[in] wakeup_clock: - \arg WAKEUP_RTCCK_DIV16: RTC auto wakeup timer clock is RTC clock divided by 16 - \arg WAKEUP_RTCCK_DIV8: RTC auto wakeup timer clock is RTC clock divided by 8 - \arg WAKEUP_RTCCK_DIV4: RTC auto wakeup timer clock is RTC clock divided by 4 - \arg WAKEUP_RTCCK_DIV2: RTC auto wakeup timer clock is RTC clock divided by 2 + \arg WAKEUP_RTCCK_DIV16: RTC auto wakeup timer clock is RTC clock divided by 16 + \arg WAKEUP_RTCCK_DIV8: RTC auto wakeup timer clock is RTC clock divided by 8 + \arg WAKEUP_RTCCK_DIV4: RTC auto wakeup timer clock is RTC clock divided by 4 + \arg WAKEUP_RTCCK_DIV2: RTC auto wakeup timer clock is RTC clock divided by 2 \arg WAKEUP_CKSPRE: RTC auto wakeup timer clock is ckspre - \arg WAKEUP_CKSPRE_2EXP16: RTC auto wakeup timer clock is ckspre and wakeup timer add 2exp16 + \arg WAKEUP_CKSPRE_2EXP16: RTC auto wakeup timer clock is ckspre and wakeup timer add 2exp16 \param[out] none \retval ErrStatus: ERROR or SUCCESS */ @@ -1057,8 +1095,8 @@ ErrStatus rtc_wakeup_clock_set(uint8_t wakeup_clock) uint32_t flag_status = RESET; /* disable the write protection */ RTC_WPK = RTC_UNLOCK_KEY1; - RTC_WPK = RTC_UNLOCK_KEY2; - /* only when RTC_CTL_WTEN=0 and RTC_STAT_WTWF=1 can write RTC_CTL[2��0] */ + RTC_WPK = RTC_UNLOCK_KEY2; + /* only when RTC_CTL_WTEN=0 and RTC_STAT_WTWF=1 can write RTC_CTL[2��0] */ /* wait until the WTWF flag to be set */ do{ flag_status = RTC_STAT & RTC_STAT_WTWF; @@ -1073,7 +1111,7 @@ ErrStatus rtc_wakeup_clock_set(uint8_t wakeup_clock) } /* enable the write protection */ RTC_WPK = RTC_LOCK_KEY; - + return error_status; } @@ -1136,16 +1174,16 @@ ErrStatus rtc_smooth_calibration_config(uint32_t window, uint32_t plus, uint32_t volatile uint32_t time_index = RTC_HRFC_TIMEOUT; ErrStatus error_status = ERROR; uint32_t flag_status = RESET; - + /* disable the write protection */ RTC_WPK = RTC_UNLOCK_KEY1; - RTC_WPK = RTC_UNLOCK_KEY2; - - /* check if a smooth calibration operation is ongoing */ + RTC_WPK = RTC_UNLOCK_KEY2; + + /* check if a smooth calibration operation is ongoing */ do{ flag_status = RTC_STAT & RTC_STAT_SCPF; }while((--time_index > 0U) && ((uint32_t)RESET != flag_status)); - + if((uint32_t)RESET == flag_status){ RTC_HRFC = (uint32_t)(window | plus | HRFC_CMSK(minus)); error_status = SUCCESS; @@ -1172,12 +1210,12 @@ ErrStatus rtc_coarse_calibration_enable(void) /* enter init mode */ error_status = rtc_init_mode_enter(); - if(ERROR != error_status){ + if(ERROR != error_status){ RTC_CTL |= (uint32_t)RTC_CTL_CCEN; /* exit init mode */ rtc_init_mode_exit(); } - + /* enable the write protection */ RTC_WPK = RTC_LOCK_KEY; return error_status; @@ -1194,24 +1232,24 @@ ErrStatus rtc_coarse_calibration_disable(void) ErrStatus error_status = ERROR; /* disable the write protection */ RTC_WPK = RTC_UNLOCK_KEY1; - RTC_WPK = RTC_UNLOCK_KEY2; + RTC_WPK = RTC_UNLOCK_KEY2; /* enter init mode */ error_status = rtc_init_mode_enter(); - if(ERROR != error_status){ + if(ERROR != error_status){ RTC_CTL &= (uint32_t)~RTC_CTL_CCEN; /* exit init mode */ rtc_init_mode_exit(); } - + /* enable the write protection */ - RTC_WPK = RTC_LOCK_KEY; + RTC_WPK = RTC_LOCK_KEY; return error_status; } /*! \brief config coarse calibration direction and step - \param[in] direction: CALIB_INCREASE or CALIB_DECREASE + \param[in] direction: CALIB_INCREASE or CALIB_DECREASE \param[in] step: 0x00-0x1F COSD=0: 0x00:+0 PPM @@ -1234,11 +1272,11 @@ ErrStatus rtc_coarse_calibration_config(uint8_t direction, uint8_t step) /* disable the write protection */ RTC_WPK = RTC_UNLOCK_KEY1; RTC_WPK = RTC_UNLOCK_KEY2; - + /* enter init mode */ error_status = rtc_init_mode_enter(); - if(ERROR != error_status){ + if(ERROR != error_status){ if(CALIB_DECREASE == direction){ RTC_COSC |= (uint32_t)RTC_COSC_COSD; }else{ @@ -1249,9 +1287,9 @@ ErrStatus rtc_coarse_calibration_config(uint8_t direction, uint8_t step) /* exit init mode */ rtc_init_mode_exit(); } - + /* enable the write protection */ RTC_WPK = RTC_LOCK_KEY; - + return error_status; } diff --git a/bsp/gd32450z-eval/Libraries/GD32F4xx_standard_peripheral/Source/gd32f4xx_sdio.c b/bsp/gd32450z-eval/Libraries/GD32F4xx_standard_peripheral/Source/gd32f4xx_sdio.c index f7b26358b5..d1d0a0be32 100644 --- a/bsp/gd32450z-eval/Libraries/GD32F4xx_standard_peripheral/Source/gd32f4xx_sdio.c +++ b/bsp/gd32450z-eval/Libraries/GD32F4xx_standard_peripheral/Source/gd32f4xx_sdio.c @@ -1,12 +1,37 @@ /*! - \file gd32f4xx_sdio.c - \brief SDIO driver + \file gd32f4xx_sdio.c + \brief SDIO driver + + \version 2016-08-15, V1.0.0, firmware for GD32F4xx + \version 2018-12-12, V2.0.1, firmware for GD32F4xx + \version 2020-09-30, V2.1.0, firmware for GD32F4xx */ /* - Copyright (C) 2016 GigaDevice + Copyright (c) 2020, GigaDevice Semiconductor Inc. + + Redistribution and use in source and binary forms, with or without modification, +are permitted provided that the following conditions are met: - 2016-08-15, V1.0.0, firmware for GD32F4xx + 1. Redistributions of source code must retain the above copyright notice, this + list of conditions and the following disclaimer. + 2. Redistributions in binary form must reproduce the above copyright notice, + this list of conditions and the following disclaimer in the documentation + and/or other materials provided with the distribution. + 3. Neither the name of the copyright holder nor the names of its contributors + may be used to endorse or promote products derived from this software without + specific prior written permission. + + THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED +WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. +IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, +INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT +NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR +PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, +WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY +OF SUCH DAMAGE. */ #include "gd32f4xx_sdio.h" @@ -26,12 +51,15 @@ void sdio_deinit(void) /*! \brief configure the SDIO clock \param[in] clock_edge: SDIO_CLK clock edge + only one parameter can be selected which is shown as below: \arg SDIO_SDIOCLKEDGE_RISING: select the rising edge of the SDIOCLK to generate SDIO_CLK \arg SDIO_SDIOCLKEDGE_FALLING: select the falling edge of the SDIOCLK to generate SDIO_CLK \param[in] clock_bypass: clock bypass + only one parameter can be selected which is shown as below: \arg SDIO_CLOCKBYPASS_ENABLE: clock bypass \arg SDIO_CLOCKBYPASS_DISABLE: no bypass \param[in] clock_powersave: SDIO_CLK clock dynamic switch on/off for power saving + only one parameter can be selected which is shown as below: \arg SDIO_CLOCKPWRSAVE_ENABLE: SDIO_CLK closed when bus is idle \arg SDIO_CLOCKPWRSAVE_DISABLE: SDIO_CLK clock is always on \param[in] clock_division: clock division, less than 512 @@ -79,6 +107,7 @@ void sdio_hardware_clock_disable(void) /*! \brief set different SDIO card bus mode \param[in] bus_mode: SDIO card bus mode + only one parameter can be selected which is shown as below: \arg SDIO_BUSMODE_1BIT: 1-bit SDIO card bus mode \arg SDIO_BUSMODE_4BIT: 4-bit SDIO card bus mode \arg SDIO_BUSMODE_8BIT: 8-bit SDIO card bus mode @@ -95,6 +124,7 @@ void sdio_bus_mode_set(uint32_t bus_mode) /*! \brief set the SDIO power state \param[in] power_state: SDIO power state + only one parameter can be selected which is shown as below: \arg SDIO_POWER_ON: SDIO power on \arg SDIO_POWER_OFF: SDIO power off \param[out] none @@ -105,7 +135,6 @@ void sdio_power_state_set(uint32_t power_state) SDIO_PWRCTL = power_state; } -/* get the SDIO power state */ /*! \brief get the SDIO power state \param[in] none @@ -146,6 +175,7 @@ void sdio_clock_disable(void) \param[in] cmd_index: command index, refer to the related specifications \param[in] cmd_argument: command argument, refer to the related specifications \param[in] response_type: response type + only one parameter can be selected which is shown as below: \arg SDIO_RESPONSETYPE_NO: no response \arg SDIO_RESPONSETYPE_SHORT: short response \arg SDIO_RESPONSETYPE_LONG: long response @@ -155,6 +185,8 @@ void sdio_clock_disable(void) void sdio_command_response_config(uint32_t cmd_index, uint32_t cmd_argument, uint32_t response_type) { uint32_t cmd_config = 0U; + /* disable the CSM */ + SDIO_CMDCTL &= ~SDIO_CMDCTL_CSMEN; /* reset the command index, command argument and response type */ SDIO_CMDAGMT &= ~SDIO_CMDAGMT_CMDAGMT; SDIO_CMDAGMT = cmd_argument; @@ -168,6 +200,7 @@ void sdio_command_response_config(uint32_t cmd_index, uint32_t cmd_argument, uin /*! \brief set the command state machine wait type \param[in] wait_type: wait type + only one parameter can be selected which is shown as below: \arg SDIO_WAITTYPE_NO: not wait interrupt \arg SDIO_WAITTYPE_INTERRUPT: wait interrupt \arg SDIO_WAITTYPE_DATAEND: wait the end of data transfer @@ -218,6 +251,7 @@ uint8_t sdio_command_index_get(void) /*! \brief get the response for the last received command \param[in] sdio_responsex: SDIO response + only one parameter can be selected which is shown as below: \arg SDIO_RESPONSE0: card response[31:0]/card response[127:96] \arg SDIO_RESPONSE1: card response[95:64] \arg SDIO_RESPONSE2: card response[63:32] @@ -252,6 +286,7 @@ uint32_t sdio_response_get(uint32_t sdio_responsex) \param[in] data_timeout: data timeout period in card bus clock periods \param[in] data_length: number of data bytes to be transferred \param[in] data_blocksize: size of data block for block transfer + only one parameter can be selected which is shown as below: \arg SDIO_DATABLOCKSIZE_1BYTE: block size = 1 byte \arg SDIO_DATABLOCKSIZE_2BYTES: block size = 2 bytes \arg SDIO_DATABLOCKSIZE_4BYTES: block size = 4 bytes @@ -285,9 +320,11 @@ void sdio_data_config(uint32_t data_timeout, uint32_t data_length, uint32_t data /*! \brief configure the data transfer mode and direction \param[in] transfer_mode: mode of data transfer + only one parameter can be selected which is shown as below: \arg SDIO_TRANSMODE_BLOCK: block transfer \arg SDIO_TRANSMODE_STREAM: stream transfer or SDIO multibyte transfer \param[in] transfer_direction: data transfer direction, read or write + only one parameter can be selected which is shown as below: \arg SDIO_TRANSDIRECTION_TOCARD: write data to card \arg SDIO_TRANSDIRECTION_TOSDIO: read data from card \param[out] none @@ -394,6 +431,7 @@ void sdio_dma_disable(void) /*! \brief get the flags state of SDIO \param[in] flag: flags state of SDIO + one or more parameters can be selected which are shown as below: \arg SDIO_FLAG_CCRCERR: command response received (CRC check failed) flag \arg SDIO_FLAG_DTCRCERR: data block sent/received (CRC check failed) flag \arg SDIO_FLAG_CMDTMOUT: command response timeout flag @@ -433,6 +471,7 @@ FlagStatus sdio_flag_get(uint32_t flag) /*! \brief clear the pending flags of SDIO \param[in] flag: flags state of SDIO + one or more parameters can be selected which are shown as below: \arg SDIO_FLAG_CCRCERR: command response received (CRC check failed) flag \arg SDIO_FLAG_DTCRCERR: data block sent/received (CRC check failed) flag \arg SDIO_FLAG_CMDTMOUT: command response timeout flag @@ -457,6 +496,7 @@ void sdio_flag_clear(uint32_t flag) /*! \brief enable the SDIO interrupt \param[in] int_flag: interrupt flags state of SDIO + one or more parameters can be selected which are shown as below: \arg SDIO_INT_CCRCERR: SDIO CCRCERR interrupt \arg SDIO_INT_DTCRCERR: SDIO DTCRCERR interrupt \arg SDIO_INT_CMDTMOUT: SDIO CMDTMOUT interrupt @@ -492,6 +532,7 @@ void sdio_interrupt_enable(uint32_t int_flag) /*! \brief disable the SDIO interrupt \param[in] int_flag: interrupt flags state of SDIO + one or more parameters can be selected which are shown as below: \arg SDIO_INT_CCRCERR: SDIO CCRCERR interrupt \arg SDIO_INT_DTCRCERR: SDIO DTCRCERR interrupt \arg SDIO_INT_CMDTMOUT: SDIO CMDTMOUT interrupt @@ -527,30 +568,31 @@ void sdio_interrupt_disable(uint32_t int_flag) /*! \brief get the interrupt flags state of SDIO \param[in] int_flag: interrupt flags state of SDIO - \arg SDIO_INT_CCRCERR: SDIO CCRCERR interrupt - \arg SDIO_INT_DTCRCERR: SDIO DTCRCERR interrupt - \arg SDIO_INT_CMDTMOUT: SDIO CMDTMOUT interrupt - \arg SDIO_INT_DTTMOUT: SDIO DTTMOUT interrupt - \arg SDIO_INT_TXURE: SDIO TXURE interrupt - \arg SDIO_INT_RXORE: SDIO RXORE interrupt - \arg SDIO_INT_CMDRECV: SDIO CMDRECV interrupt - \arg SDIO_INT_CMDSEND: SDIO CMDSEND interrupt - \arg SDIO_INT_DTEND: SDIO DTEND interrupt - \arg SDIO_INT_STBITE: SDIO STBITE interrupt - \arg SDIO_INT_DTBLKEND: SDIO DTBLKEND interrupt - \arg SDIO_INT_CMDRUN: SDIO CMDRUN interrupt - \arg SDIO_INT_TXRUN: SDIO TXRUN interrupt - \arg SDIO_INT_RXRUN: SDIO RXRUN interrupt - \arg SDIO_INT_TFH: SDIO TFH interrupt - \arg SDIO_INT_RFH: SDIO RFH interrupt - \arg SDIO_INT_TFF: SDIO TFF interrupt - \arg SDIO_INT_RFF: SDIO RFF interrupt - \arg SDIO_INT_TFE: SDIO TFE interrupt - \arg SDIO_INT_RFE: SDIO RFE interrupt - \arg SDIO_INT_TXDTVAL: SDIO TXDTVAL interrupt - \arg SDIO_INT_RXDTVAL: SDIO RXDTVAL interrupt - \arg SDIO_INT_SDIOINT: SDIO SDIOINT interrupt - \arg SDIO_INT_ATAEND: SDIO ATAEND interrupt + one or more parameters can be selected which are shown as below: + \arg SDIO_INT_FLAG_CCRCERR: SDIO CCRCERR interrupt flag + \arg SDIO_INT_FLAG_DTCRCERR: SDIO DTCRCERR interrupt flag + \arg SDIO_INT_FLAG_CMDTMOUT: SDIO CMDTMOUT interrupt flag + \arg SDIO_INT_FLAG_DTTMOUT: SDIO DTTMOUT interrupt flag + \arg SDIO_INT_FLAG_TXURE: SDIO TXURE interrupt flag + \arg SDIO_INT_FLAG_RXORE: SDIO RXORE interrupt flag + \arg SDIO_INT_FLAG_CMDRECV: SDIO CMDRECV interrupt flag + \arg SDIO_INT_FLAG_CMDSEND: SDIO CMDSEND interrupt flag + \arg SDIO_INT_FLAG_DTEND: SDIO DTEND interrupt flag + \arg SDIO_INT_FLAG_STBITE: SDIO STBITE interrupt flag + \arg SDIO_INT_FLAG_DTBLKEND: SDIO DTBLKEND interrupt flag + \arg SDIO_INT_FLAG_CMDRUN: SDIO CMDRUN interrupt flag + \arg SDIO_INT_FLAG_TXRUN: SDIO TXRUN interrupt flag + \arg SDIO_INT_FLAG_RXRUN: SDIO RXRUN interrupt flag + \arg SDIO_INT_FLAG_TFH: SDIO TFH interrupt flag + \arg SDIO_INT_FLAG_RFH: SDIO RFH interrupt flag + \arg SDIO_INT_FLAG_TFF: SDIO TFF interrupt flag + \arg SDIO_INT_FLAG_RFF: SDIO RFF interrupt flag + \arg SDIO_INT_FLAG_TFE: SDIO TFE interrupt flag + \arg SDIO_INT_FLAG_RFE: SDIO RFE interrupt flag + \arg SDIO_INT_FLAG_TXDTVAL: SDIO TXDTVAL interrupt flag + \arg SDIO_INT_FLAG_RXDTVAL: SDIO RXDTVAL interrupt flag + \arg SDIO_INT_FLAG_SDIOINT: SDIO SDIOINT interrupt flag + \arg SDIO_INT_FLAG_ATAEND: SDIO ATAEND interrupt flag \param[out] none \retval FlagStatus: SET or RESET */ @@ -566,19 +608,20 @@ FlagStatus sdio_interrupt_flag_get(uint32_t int_flag) /*! \brief clear the interrupt pending flags of SDIO \param[in] int_flag: interrupt flags state of SDIO - \arg SDIO_INT_CCRCERR: command response received (CRC check failed) flag - \arg SDIO_INT_DTCRCERR: data block sent/received (CRC check failed) flag - \arg SDIO_INT_CMDTMOUT: command response timeout flag - \arg SDIO_INT_DTTMOUT: data timeout flag - \arg SDIO_INT_TXURE: transmit FIFO underrun error occurs flag - \arg SDIO_INT_RXORE: received FIFO overrun error occurs flag - \arg SDIO_INT_CMDRECV: command response received (CRC check passed) flag - \arg SDIO_INT_CMDSEND: command sent (no response required) flag - \arg SDIO_INT_DTEND: data end (data counter, SDIO_DATACNT, is zero) flag - \arg SDIO_INT_STBITE: start bit error in the bus flag - \arg SDIO_INT_DTBLKEND: data block sent/received (CRC check passed) flag - \arg SDIO_INT_SDIOINT: SD I/O interrupt received flag - \arg SDIO_INT_ATAEND: CE-ATA command completion signal received (only for CMD61) flag + one or more parameters can be selected which are shown as below: + \arg SDIO_INT_FLAG_CCRCERR: command response received (CRC check failed) flag + \arg SDIO_INT_FLAG_DTCRCERR: data block sent/received (CRC check failed) flag + \arg SDIO_INT_FLAG_CMDTMOUT: command response timeout flag + \arg SDIO_INT_FLAG_DTTMOUT: data timeout flag + \arg SDIO_INT_FLAG_TXURE: transmit FIFO underrun error occurs flag + \arg SDIO_INT_FLAG_RXORE: received FIFO overrun error occurs flag + \arg SDIO_INT_FLAG_CMDRECV: command response received (CRC check passed) flag + \arg SDIO_INT_FLAG_CMDSEND: command sent (no response required) flag + \arg SDIO_INT_FLAG_DTEND: data end (data counter, SDIO_DATACNT, is zero) flag + \arg SDIO_INT_FLAG_STBITE: start bit error in the bus flag + \arg SDIO_INT_FLAG_DTBLKEND: data block sent/received (CRC check passed) flag + \arg SDIO_INT_FLAG_SDIOINT: SD I/O interrupt received flag + \arg SDIO_INT_FLAG_ATAEND: CE-ATA command completion signal received (only for CMD61) flag \param[out] none \retval none */ @@ -634,6 +677,7 @@ void sdio_stop_readwait_disable(void) /*! \brief set the read wait type(SD I/O only) \param[in] readwait_type: SD I/O read wait type + only one parameter can be selected which is shown as below: \arg SDIO_READWAITTYPE_CLK: read wait control by stopping SDIO_CLK \arg SDIO_READWAITTYPE_DAT2: read wait control using SDIO_DAT[2] \param[out] none diff --git a/bsp/gd32450z-eval/Libraries/GD32F4xx_standard_peripheral/Source/gd32f4xx_spi.c b/bsp/gd32450z-eval/Libraries/GD32F4xx_standard_peripheral/Source/gd32f4xx_spi.c index c5947cf174..3f842251fc 100644 --- a/bsp/gd32450z-eval/Libraries/GD32F4xx_standard_peripheral/Source/gd32f4xx_spi.c +++ b/bsp/gd32450z-eval/Libraries/GD32F4xx_standard_peripheral/Source/gd32f4xx_spi.c @@ -1,23 +1,53 @@ /*! - \file gd32f4xx_spi.c - \brief SPI driver + \file gd32f4xx_spi.c + \brief SPI driver + + \version 2016-08-15, V1.0.0, firmware for GD32F4xx + \version 2018-12-12, V2.0.0, firmware for GD32F4xx + \version 2020-09-30, V2.1.0, firmware for GD32F4xx */ /* - Copyright (C) 2016 GigaDevice + Copyright (c) 2020, GigaDevice Semiconductor Inc. + + Redistribution and use in source and binary forms, with or without modification, +are permitted provided that the following conditions are met: + + 1. Redistributions of source code must retain the above copyright notice, this + list of conditions and the following disclaimer. + 2. Redistributions in binary form must reproduce the above copyright notice, + this list of conditions and the following disclaimer in the documentation + and/or other materials provided with the distribution. + 3. Neither the name of the copyright holder nor the names of its contributors + may be used to endorse or promote products derived from this software without + specific prior written permission. - 2016-08-15, V1.0.1, firmware for GD32F4xx + THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED +WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. +IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, +INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT +NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR +PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, +WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY +OF SUCH DAMAGE. */ + #include "gd32f4xx_spi.h" #include "gd32f4xx_rcu.h" -#define SPI_INIT_MASK ((uint32_t)0x00003040U) -#define I2S_INIT_MASK ((uint32_t)0x0000F047U) -#define I2S_FULL_DUPLEX_MASK ((uint32_t)0x0000F040U) +/* SPI/I2S parameter initialization mask */ +#define SPI_INIT_MASK ((uint32_t)0x00003040U) /*!< SPI parameter initialization mask */ +#define I2S_INIT_MASK ((uint32_t)0x0000F047U) /*!< I2S parameter initialization mask */ +#define I2S_FULL_DUPLEX_MASK ((uint32_t)0x00000480U) /*!< I2S full duples mode configure parameter initialization mask */ + +/* default value */ +#define SPI_I2SPSC_DEFAULT_VALUE ((uint32_t)0x00000002U) /*!< default value of SPI_I2SPSC register */ /*! - \brief SPI and I2S reset + \brief deinitialize SPI and I2S \param[in] spi_periph: SPIx(x=0,1,2,3,4,5),include I2S1_ADD and I2S2_ADD \param[out] none \retval none @@ -26,7 +56,7 @@ void spi_i2s_deinit(uint32_t spi_periph) { switch(spi_periph){ case SPI0: - /* reset SPI0 and I2S0 */ + /* reset SPI0 */ rcu_periph_reset_enable(RCU_SPI0RST); rcu_periph_reset_disable(RCU_SPI0RST); break; @@ -41,12 +71,12 @@ void spi_i2s_deinit(uint32_t spi_periph) rcu_periph_reset_disable(RCU_SPI2RST); break; case SPI3: - /* reset SPI3 and I2S3 */ + /* reset SPI3 */ rcu_periph_reset_enable(RCU_SPI3RST); rcu_periph_reset_disable(RCU_SPI3RST); break; case SPI4: - /* reset SPI4 and I2S4 */ + /* reset SPI4 */ rcu_periph_reset_enable(RCU_SPI4RST); rcu_periph_reset_disable(RCU_SPI4RST); break; @@ -61,41 +91,58 @@ void spi_i2s_deinit(uint32_t spi_periph) } /*! - \brief SPI parameter initialization + \brief initialize the parameters of SPI struct with default values + \param[in] none + \param[out] spi_parameter_struct: the initialized struct spi_parameter_struct pointer + \retval none +*/ +void spi_struct_para_init(spi_parameter_struct *spi_struct) +{ + /* configure the structure with default value */ + spi_struct->device_mode = SPI_SLAVE; + spi_struct->trans_mode = SPI_TRANSMODE_FULLDUPLEX; + spi_struct->frame_size = SPI_FRAMESIZE_8BIT; + spi_struct->nss = SPI_NSS_HARD; + spi_struct->clock_polarity_phase = SPI_CK_PL_LOW_PH_1EDGE; + spi_struct->prescale = SPI_PSC_2; + spi_struct->endian = SPI_ENDIAN_MSB; +} +/*! + \brief initialize SPI parameter \param[in] spi_periph: SPIx(x=0,1,2,3,4,5) - \param[in] spi_struct: SPI parameter initialization stuct - members of the structure and the member values are shown as below: - device_mode : SPI_MASTER, SPI_SLAVE. - trans_mode : SPI_TRANSMODE_FULLDUPLEX, SPI_TRANSMODE_RECEIVEONLY, - SPI_TRANSMODE_BDRECEIVE, SPI_TRANSMODE_BDTRANSMIT - frame_size : SPI_FRAMESIZE_16BIT, SPI_FRAMESIZE_8BIT - nss: : SPI_NSS_SOFT, SPI_NSS_HARD - endian : SPI_ENDIAN_MSB, SPI_ENDIAN_LSB - clock_polarity_phase : SPI_CK_PL_LOW_PH_1EDGE, SPI_CK_PL_HIGH_PH_1EDGE - SPI_CK_PL_LOW_PH_2EDGE, SPI_CK_PL_HIGH_PH_2EDGE - prescale : SPI_PSC_n (n=2,4,8,16,32,64,128,256) + \param[in] spi_struct: SPI parameter initialization stuct members of the structure + and the member values are shown as below: + device_mode: SPI_MASTER, SPI_SLAVE. + trans_mode: SPI_TRANSMODE_FULLDUPLEX, SPI_TRANSMODE_RECEIVEONLY, + SPI_TRANSMODE_BDRECEIVE, SPI_TRANSMODE_BDTRANSMIT + frame_size: SPI_FRAMESIZE_16BIT, SPI_FRAMESIZE_8BIT + nss: SPI_NSS_SOFT, SPI_NSS_HARD + endian: SPI_ENDIAN_MSB, SPI_ENDIAN_LSB + clock_polarity_phase: SPI_CK_PL_LOW_PH_1EDGE, SPI_CK_PL_HIGH_PH_1EDGE + SPI_CK_PL_LOW_PH_2EDGE, SPI_CK_PL_HIGH_PH_2EDGE + prescale: SPI_PSC_n (n=2,4,8,16,32,64,128,256) \param[out] none \retval none */ void spi_init(uint32_t spi_periph, spi_parameter_struct* spi_struct) -{ +{ uint32_t reg = 0U; reg = SPI_CTL0(spi_periph); reg &= SPI_INIT_MASK; - /* (1) select SPI as master or slave */ + /* select SPI as master or slave */ reg |= spi_struct->device_mode; - /* (2) select SPI transfer mode */ + /* select SPI transfer mode */ reg |= spi_struct->trans_mode; - /* (3) select SPI frame size */ + /* select SPI frame size */ reg |= spi_struct->frame_size; - /* (4) select SPI nss use hardware or software */ + /* select SPI nss use hardware or software */ reg |= spi_struct->nss; - /* (5) select SPI LSB or MSB */ + /* select SPI LSB or MSB */ reg |= spi_struct->endian; - /* (6) select SPI polarity and phase */ + /* select SPI polarity and phase */ reg |= spi_struct->clock_polarity_phase; - /* (7) select SPI prescale to adjust transmit speed */ + /* select SPI prescale to adjust transmit speed */ reg |= spi_struct->prescale; /* write to SPI_CTL0 register */ @@ -105,7 +152,7 @@ void spi_init(uint32_t spi_periph, spi_parameter_struct* spi_struct) } /*! - \brief SPI enable + \brief enable SPI \param[in] spi_periph: SPIx(x=0,1,2,3,4,5) \param[out] none \retval none @@ -116,7 +163,7 @@ void spi_enable(uint32_t spi_periph) } /*! - \brief SPI disable + \brief disable SPI \param[in] spi_periph: SPIx(x=0,1,2,3,4,5) \param[out] none \retval none @@ -127,24 +174,69 @@ void spi_disable(uint32_t spi_periph) } /*! - \brief I2S prescale config - \param[in] spi_periph: SPIx(x=0,1,2,3,4) - \param[in] audiosample: - \arg I2S_AUDIOSAMPLE_8K: audio sample rate is 8khz - \arg I2S_AUDIOSAMPLE_11K: audio sample rate is 11khz - \arg I2S_AUDIOSAMPLE_16K: audio sample rate is 16khz - \arg I2S_AUDIOSAMPLE_22K: audio sample rate is 22khz - \arg I2S_AUDIOSAMPLE_32K: audio sample rate is 32khz - \arg I2S_AUDIOSAMPLE_44K: audio sample rate is 44khz - \arg I2S_AUDIOSAMPLE_48K: audio sample rate is 48khz - \arg I2S_AUDIOSAMPLE_96K: audio sample rate is 96khz - \arg I2S_AUDIOSAMPLE_192K: audio sample rate is 192khz - \param[in] frameformat: + \brief initialize I2S parameter + \param[in] spi_periph: SPIx(x=1,2) + \param[in] i2s_mode: I2S operation mode + only one parameter can be selected which is shown as below: + \arg I2S_MODE_SLAVETX : I2S slave transmit mode + \arg I2S_MODE_SLAVERX : I2S slave receive mode + \arg I2S_MODE_MASTERTX : I2S master transmit mode + \arg I2S_MODE_MASTERRX : I2S master receive mode + \param[in] i2s_standard: I2S standard + only one parameter can be selected which is shown as below: + \arg I2S_STD_PHILLIPS : I2S phillips standard + \arg I2S_STD_MSB : I2S MSB standard + \arg I2S_STD_LSB : I2S LSB standard + \arg I2S_STD_PCMSHORT : I2S PCM short standard + \arg I2S_STD_PCMLONG : I2S PCM long standard + \param[in] i2s_ckpl: I2S idle state clock polarity + only one parameter can be selected which is shown as below: + \arg I2S_CKPL_LOW : I2S clock polarity low level + \arg I2S_CKPL_HIGH : I2S clock polarity high level + \param[out] none + \retval none +*/ +void i2s_init(uint32_t spi_periph, uint32_t i2s_mode, uint32_t i2s_standard, uint32_t i2s_ckpl) +{ + uint32_t reg= 0U; + reg = SPI_I2SCTL(spi_periph); + reg &= I2S_INIT_MASK; + + /* enable I2S mode */ + reg |= (uint32_t)SPI_I2SCTL_I2SSEL; + /* select I2S mode */ + reg |= (uint32_t)i2s_mode; + /* select I2S standard */ + reg |= (uint32_t)i2s_standard; + /* select I2S polarity */ + reg |= (uint32_t)i2s_ckpl; + + /* write to SPI_I2SCTL register */ + SPI_I2SCTL(spi_periph) = (uint32_t)reg; +} + +/*! + \brief configure I2S prescale + \param[in] spi_periph: SPIx(x=1,2) + \param[in] i2s_audiosample: I2S audio sample rate + only one parameter can be selected which is shown as below: + \arg I2S_AUDIOSAMPLE_8K: audio sample rate is 8KHz + \arg I2S_AUDIOSAMPLE_11K: audio sample rate is 11KHz + \arg I2S_AUDIOSAMPLE_16K: audio sample rate is 16KHz + \arg I2S_AUDIOSAMPLE_22K: audio sample rate is 22KHz + \arg I2S_AUDIOSAMPLE_32K: audio sample rate is 32KHz + \arg I2S_AUDIOSAMPLE_44K: audio sample rate is 44KHz + \arg I2S_AUDIOSAMPLE_48K: audio sample rate is 48KHz + \arg I2S_AUDIOSAMPLE_96K: audio sample rate is 96KHz + \arg I2S_AUDIOSAMPLE_192K: audio sample rate is 192KHz + \param[in] i2s_frameformat: I2S data length and channel length + only one parameter can be selected which is shown as below: \arg I2S_FRAMEFORMAT_DT16B_CH16B: I2S data length is 16 bit and channel length is 16 bit \arg I2S_FRAMEFORMAT_DT16B_CH32B: I2S data length is 16 bit and channel length is 32 bit \arg I2S_FRAMEFORMAT_DT24B_CH32B: I2S data length is 24 bit and channel length is 32 bit \arg I2S_FRAMEFORMAT_DT32B_CH32B: I2S data length is 32 bit and channel length is 32 bit - \param[in] mckout: + \param[in] i2s_mckout: I2S master clock output + only one parameter can be selected which is shown as below: \arg I2S_MCKOUT_ENABLE: I2S master clock output enable \arg I2S_MCKOUT_DISABLE: I2S master clock output disable \param[out] none @@ -152,8 +244,8 @@ void spi_disable(uint32_t spi_periph) */ void i2s_psc_config(uint32_t spi_periph, uint32_t i2s_audiosample, uint32_t i2s_frameformat, uint32_t i2s_mckout) { - uint32_t temp_div = 2U, temp_of = 0U; - uint32_t temp = 0U; + uint32_t i2sdiv = 2U, i2sof = 0U; + uint32_t clks = 0U; uint32_t i2sclock = 0U; #ifndef I2S_EXTERNAL_CLOCK_IN @@ -161,7 +253,7 @@ void i2s_psc_config(uint32_t spi_periph, uint32_t i2s_audiosample, uint32_t i2s_ #endif /* I2S_EXTERNAL_CLOCK_IN */ /* deinit SPI_I2SPSC register */ - SPI_I2SPSC(spi_periph) = 0x0002U; + SPI_I2SPSC(spi_periph) = SPI_I2SPSC_DEFAULT_VALUE; #ifdef I2S_EXTERNAL_CLOCK_IN rcu_i2s_clock_config(RCU_I2SSRC_I2S_CKIN); @@ -201,28 +293,28 @@ void i2s_psc_config(uint32_t spi_periph, uint32_t i2s_audiosample, uint32_t i2s_ /* config the prescaler depending on the mclk output state, the frame format and audio sample rate */ if(I2S_MCKOUT_ENABLE == i2s_mckout){ - temp = (uint32_t)(((i2sclock / 256U) * 10U) / i2s_audiosample); + clks = (uint32_t)(((i2sclock / 256U) * 10U) / i2s_audiosample); }else{ if(I2S_FRAMEFORMAT_DT16B_CH16B == i2s_frameformat){ - temp = (uint32_t)(((i2sclock / 32U) *10U ) / i2s_audiosample); + clks = (uint32_t)(((i2sclock / 32U) *10U ) / i2s_audiosample); }else{ - temp = (uint32_t)(((i2sclock / 64U) *10U ) / i2s_audiosample); + clks = (uint32_t)(((i2sclock / 64U) *10U ) / i2s_audiosample); } } /* remove the floating point */ - temp = (temp + 5U) / 10U; - temp_of = (temp & 0x00000001U); - temp_div = ((temp - temp_of) / 2U); - temp_of = (temp_of << 8); + clks = (clks + 5U) / 10U; + i2sof = (clks & 0x00000001U); + i2sdiv = ((clks - i2sof) / 2U); + i2sof = (i2sof << 8U); /* set the default values */ - if((temp_div< 2U) || (temp_div > 255U)){ - temp_div = 2U; - temp_of = 0U; + if((i2sdiv< 2U) || (i2sdiv > 255U)){ + i2sdiv = 2U; + i2sof = 0U; } /* configure SPI_I2SPSC */ - SPI_I2SPSC(spi_periph) = (uint32_t)(temp_div | temp_of | i2s_mckout); + SPI_I2SPSC(spi_periph) = (uint32_t)(i2sdiv | i2sof | i2s_mckout); /* clear SPI_I2SCTL_DTLEN and SPI_I2SCTL_CHLEN bits */ SPI_I2SCTL(spi_periph) &= (uint32_t)(~(SPI_I2SCTL_DTLEN|SPI_I2SCTL_CHLEN)); @@ -231,47 +323,8 @@ void i2s_psc_config(uint32_t spi_periph, uint32_t i2s_audiosample, uint32_t i2s_ } /*! - \brief I2S parameter configuration - \param[in] spi_periph: SPIx(x=0,1,2,3,4) - \param[in] i2s_mode: - \arg I2S_MODE_SLAVETX : I2S slave transmit mode - \arg I2S_MODE_SLAVERX : I2S slave receive mode - \arg I2S_MODE_MASTERTX : I2S master transmit mode - \arg I2S_MODE_MASTERRX : I2S master receive mode - \param[in] i2s_std: - \arg I2S_STD_PHILLIPS : I2S phillips standard - \arg I2S_STD_MSB : I2S MSB standard - \arg I2S_STD_LSB : I2S LSB standard - \arg I2S_STD_PCMSHORT : I2S PCM short standard - \arg I2S_STD_PCMLONG : I2S PCM long standard - \param[in] i2s_ckpl: - \arg I2S_CKPL_LOW : I2S clock polarity low level - \arg I2S_CKPL_HIGH : I2S clock polarity high level - \param[out] none - \retval none -*/ -void i2s_init(uint32_t spi_periph, uint32_t i2s_mode, uint32_t i2s_standard, uint32_t i2s_ckpl) -{ - uint32_t reg= 0U; - reg = SPI_I2SCTL(spi_periph); - reg &= I2S_INIT_MASK; - - /* enable I2S mode */ - reg |= (uint32_t)SPI_I2SCTL_I2SSEL; - /* select I2S mode */ - reg |= (uint32_t)i2s_mode; - /* select I2S standard */ - reg |= (uint32_t)i2s_standard; - /* select I2S polarity */ - reg |= (uint32_t)i2s_ckpl; - - /* write to SPI_I2SCTL register */ - SPI_I2SCTL(spi_periph) = (uint32_t)reg; -} - -/*! - \brief I2S enable - \param[in] spi_periph: SPIx(x=0,1,2,3,4) + \brief enable I2S + \param[in] spi_periph: SPIx(x=1,2) \param[out] none \retval none */ @@ -281,8 +334,8 @@ void i2s_enable(uint32_t spi_periph) } /*! - \brief I2S disable - \param[in] spi_periph: SPIx(x=0,1,2,3,4) + \brief disable I2S + \param[in] spi_periph: SPIx(x=1,2) \param[out] none \retval none */ @@ -292,7 +345,7 @@ void i2s_disable(uint32_t spi_periph) } /*! - \brief SPI nss output enable + \brief enable SPI nss output \param[in] spi_periph: SPIx(x=0,1,2,3,4,5) \param[out] none \retval none @@ -303,7 +356,7 @@ void spi_nss_output_enable(uint32_t spi_periph) } /*! - \brief SPI nss output disable + \brief disable SPI nss output \param[in] spi_periph: SPIx(x=0,1,2,3,4,5) \param[out] none \retval none @@ -336,11 +389,12 @@ void spi_nss_internal_low(uint32_t spi_periph) } /*! - \brief SPI dma send or receive enable + \brief enable SPI DMA send or receive \param[in] spi_periph: SPIx(x=0,1,2,3,4,5) - \param[in] spi_dma: - \arg SPI_DMA_TRANSMIT: enable DMA transmit - \arg SPI_DMA_RECEIVE: enable DMA receive + \param[in] spi_dma: SPI DMA mode + only one parameter can be selected which is shown as below: + \arg SPI_DMA_TRANSMIT: SPI transmit data use DMA + \arg SPI_DMA_RECEIVE: SPI receive data use DMA \param[out] none \retval none */ @@ -354,11 +408,12 @@ void spi_dma_enable(uint32_t spi_periph, uint8_t spi_dma) } /*! - \brief SPI dma send or receive diable + \brief diable SPI DMA send or receive \param[in] spi_periph: SPIx(x=0,1,2,3,4,5) - \param[in] spi_dma: - \arg SPI_DMA_TRANSMIT: disable DMA transmit - \arg SPI_DMA_RECEIVE: disable DMA receive + \param[in] spi_dma: SPI DMA mode + only one parameter can be selected which is shown as below: + \arg SPI_DMA_TRANSMIT: SPI transmit data use DMA + \arg SPI_DMA_RECEIVE: SPI receive data use DMA \param[out] none \retval none */ @@ -374,7 +429,8 @@ void spi_dma_disable(uint32_t spi_periph, uint8_t spi_dma) /*! \brief configure SPI/I2S data frame format \param[in] spi_periph: SPIx(x=0,1,2,3,4,5) - \param[in] frame_format: + \param[in] frame_format: SPI frame size + only one parameter can be selected which is shown as below: \arg SPI_FRAMESIZE_16BIT: SPI frame size is 16 bits \arg SPI_FRAMESIZE_8BIT: SPI frame size is 8 bits \param[out] none @@ -384,7 +440,7 @@ void spi_i2s_data_frame_format_config(uint32_t spi_periph, uint16_t frame_format { /* clear SPI_CTL0_FF16 bit */ SPI_CTL0(spi_periph) &= (uint32_t)(~SPI_CTL0_FF16); - /* confige SPI_CTL0_FF16 bit */ + /* configure SPI_CTL0_FF16 bit */ SPI_CTL0(spi_periph) |= (uint32_t)frame_format; } @@ -401,7 +457,7 @@ void spi_i2s_data_transmit(uint32_t spi_periph, uint16_t data) } /*! - \brief receive data + \brief SPI receive data \param[in] spi_periph: SPIx(x=0,1,2,3,4,5) \param[out] none \retval 16-bit data @@ -414,16 +470,17 @@ uint16_t spi_i2s_data_receive(uint32_t spi_periph) /*! \brief configure SPI bidirectional transfer direction \param[in] spi_periph: SPIx(x=0,1,2,3,4,5) - \param[in] transfer_direction: - \arg SPI_BIDIRECTIONAL_TEANSMIT: SPI work in transmit-only mode + \param[in] transfer_direction: SPI transfer direction + only one parameter can be selected which is shown as below: + \arg SPI_BIDIRECTIONAL_TRANSMIT: SPI work in transmit-only mode \arg SPI_BIDIRECTIONAL_RECEIVE: SPI work in receive-only mode \retval none */ void spi_bidirectional_transfer_config(uint32_t spi_periph, uint32_t transfer_direction) { - if(SPI_BIDIRECTIONAL_TEANSMIT == transfer_direction){ + if(SPI_BIDIRECTIONAL_TRANSMIT == transfer_direction){ /* set the transmit only mode */ - SPI_CTL0(spi_periph) |= (uint32_t)SPI_BIDIRECTIONAL_TEANSMIT; + SPI_CTL0(spi_periph) |= (uint32_t)SPI_BIDIRECTIONAL_TRANSMIT; }else{ /* set the receive only mode */ SPI_CTL0(spi_periph) &= SPI_BIDIRECTIONAL_RECEIVE; @@ -431,166 +488,34 @@ void spi_bidirectional_transfer_config(uint32_t spi_periph, uint32_t transfer_di } /*! - \brief SPI and I2S interrupt enable + \brief set SPI CRC polynomial \param[in] spi_periph: SPIx(x=0,1,2,3,4,5) - \param[in] spi_i2s_int: - \arg SPI_I2S_INT_TBE: transmit buffer empty interrupt - \arg SPI_I2S_INT_RBNE: receive buffer not empty interrupt - \arg SPI_I2S_INT_ERR: CRC error,configuration error,reception overrun error, - transmission underrun error and format error interrupt - \param[out] none - \retval none -*/ -void spi_i2s_interrupt_enable(uint32_t spi_periph, uint8_t spi_i2s_int) -{ - switch(spi_i2s_int){ - case SPI_I2S_INT_TBE: - SPI_CTL1(spi_periph) |= (uint32_t)SPI_CTL1_TBEIE; - break; - case SPI_I2S_INT_RBNE: - SPI_CTL1(spi_periph) |= (uint32_t)SPI_CTL1_RBNEIE; - break; - case SPI_I2S_INT_ERR: - SPI_CTL1(spi_periph) |= (uint32_t)SPI_CTL1_ERRIE; - break; - default: - break; - } -} - -/*! - \brief SPI and I2S interrupt disable - \param[in] spi_periph: SPIx(x=0,1,2,3,4,5) - \param[in] spi_i2s_int: - \arg SPI_I2S_INT_TBE: transmit buffer empty interrupt - \arg SPI_I2S_INT_RBNE: receive buffer not empty interrupt - \arg SPI_I2S_INT_ERR: CRC error,configuration error,reception overrun error, - transmission underrun error and format error interrupt + \param[in] crc_poly: CRC polynomial value \param[out] none \retval none */ -void spi_i2s_interrupt_disable(uint32_t spi_periph, uint8_t spi_i2s_int) -{ - switch(spi_i2s_int){ - case SPI_I2S_INT_TBE : - SPI_CTL1(spi_periph) &= (uint32_t)(~SPI_CTL1_TBEIE); - break; - case SPI_I2S_INT_RBNE : - SPI_CTL1(spi_periph) &= (uint32_t)(~SPI_CTL1_RBNEIE); - break; - case SPI_I2S_INT_ERR : - SPI_CTL1(spi_periph) &= (uint32_t)(~SPI_CTL1_ERRIE); - break; - default : - break; - } -} - -/*! - \brief get interrupt flag status - \param[in] spi_periph: SPIx(x=0,1,2,3,4,5) - \param[in] spi_i2s_int: - \arg SPI_I2S_INT_TBE: transmit buffer empty interrupt - \arg SPI_I2S_INT_RBNE: receive buffer not empty interrupt - \arg SPI_I2S_INT_RXORERR: overrun interrupt - \arg SPI_INT_CONFERR: config error interrupt - \arg SPI_INT_CRCERR: CRC error interrupt - \arg I2S_INT_TXURERR: underrun error interrupt - \arg SPI_I2S_INT_FERR: format error interrupt - \param[out] none - \retval FlagStatus: SET or RESET -*/ -FlagStatus spi_i2s_interrupt_flag_get(uint32_t spi_periph, uint8_t spi_i2s_int) +void spi_crc_polynomial_set(uint32_t spi_periph,uint16_t crc_poly) { - uint32_t reg1 = SPI_STAT(spi_periph); - uint32_t reg2 = SPI_CTL1(spi_periph); - - uint32_t temp1 = 0U; - uint32_t temp2 = 0U; - - switch(spi_i2s_int){ - case SPI_I2S_INT_TBE : - temp1 = reg1 & SPI_STAT_TBE; - temp2 = reg2 & SPI_CTL1_TBEIE; - break; - case SPI_I2S_INT_RBNE : - temp1 = reg1 & SPI_STAT_RBNE; - temp2 = reg2 & SPI_CTL1_RBNEIE; - break; - case SPI_I2S_INT_RXORERR : - temp1 = reg1 & SPI_STAT_RXORERR; - temp2 = reg2 & SPI_CTL1_ERRIE; - break; - case SPI_INT_CONFERR : - temp1 = reg1 & SPI_STAT_CONFERR; - temp2 = reg2 & SPI_CTL1_ERRIE; - break; - case SPI_INT_CRCERR : - temp1 = reg1 & SPI_STAT_CRCERR; - temp2 = reg2 & SPI_CTL1_ERRIE; - break; - case I2S_INT_TXURERR : - temp1 = reg1 & SPI_STAT_TXURERR; - temp2 = reg2 & SPI_CTL1_ERRIE; - break; - case SPI_I2S_INT_FERR : - temp1 = reg1 & SPI_STAT_FERR; - temp2 = reg2 & SPI_CTL1_ERRIE; - break; - default : - break; - } - - if(temp1 && temp2){ - return SET; - }else{ - return RESET; - } -} + /* enable SPI CRC */ + SPI_CTL0(spi_periph) |= (uint32_t)SPI_CTL0_CRCEN; -/*! - \brief get flag status - \param[in] spi_periph: SPIx(x=0,1,2,3,4,5) - \param[in] spi_i2s_flag: - \arg SPI_FLAG_TBE: transmit buffer empty flag - \arg SPI_FLAG_RBNE: receive buffer not empty flag - \arg SPI_FLAG_TRANS: transmit on-going flag - \arg SPI_FLAG_RXORERR: receive Overrun flag - \arg SPI_FLAG_CONFERR: mode config error flag - \arg SPI_FLAG_CRCERR: CRC error flag - \arg SPI_FLAG_FERR: format error interrupt flag - \arg I2S_FLAG_TBE: transmit buffer empty flag - \arg I2S_FLAG_RBNE: receive buffer not empty flag - \arg I2S_FLAG_TRANS: transmit on-going flag - \arg I2S_FLAG_RXORERR: overrun flag - \arg I2S_FLAG_TXURERR: underrun error flag - \arg I2S_FLAG_CH: channel side flag - \arg I2S_FLAG_FERR: format error interrupt flag - \param[out] none - \retval FlagStatus: SET or RESET -*/ -FlagStatus spi_i2s_flag_get(uint32_t spi_periph, uint32_t spi_i2s_flag) -{ - if(SPI_STAT(spi_periph) & spi_i2s_flag){ - return SET; - }else{ - return RESET; - } + /* set SPI CRC polynomial */ + SPI_CRCPOLY(spi_periph) = (uint32_t)crc_poly; } /*! - \brief clear SPI CRC error flag status + \brief get SPI CRC polynomial \param[in] spi_periph: SPIx(x=0,1,2,3,4,5) \param[out] none - \retval none + \retval 16-bit CRC polynomial */ -void spi_crc_error_clear(uint32_t spi_periph) +uint16_t spi_crc_polynomial_get(uint32_t spi_periph) { - SPI_STAT(spi_periph) &= (uint32_t)(~SPI_FLAG_CRCERR); + return ((uint16_t)SPI_CRCPOLY(spi_periph)); } /*! - \brief CRC function turn on + \brief turn on CRC function \param[in] spi_periph: SPIx(x=0,1,2,3,4,5) \param[out] none \retval none @@ -601,7 +526,7 @@ void spi_crc_on(uint32_t spi_periph) } /*! - \brief CRC function turn off + \brief turn off CRC function \param[in] spi_periph: SPIx(x=0,1,2,3,4,5) \param[out] none \retval none @@ -612,33 +537,6 @@ void spi_crc_off(uint32_t spi_periph) } /*! - \brief CRC polynomial set - \param[in] spi_periph: SPIx(x=0,1,2,3,4,5) - \param[in] crc_poly: CRC polynomial value - \param[out] none - \retval none -*/ -void spi_crc_polynomial_set(uint32_t spi_periph,uint16_t crc_poly) -{ - /* enable SPI CRC */ - SPI_CTL0(spi_periph) |= (uint32_t)SPI_CTL0_CRCEN; - - /* set SPI CRC polynomial */ - SPI_CRCPOLY(spi_periph) = (uint32_t)crc_poly; -} - -/*! - \brief get SPI CRC polynomial - \param[in] spi_periph: SPIx(x=0,1,2,3,4,5) - \param[out] none - \retval 16-bit CRC polynomial -*/ -uint16_t spi_crc_polynomial_get(uint32_t spi_periph) -{ - return ((uint16_t)SPI_CRCPOLY(spi_periph)); -} - -/*! \brief SPI next data is CRC value \param[in] spi_periph: SPIx(x=0,1,2,3,4,5) \param[out] none @@ -652,7 +550,8 @@ void spi_crc_next(uint32_t spi_periph) /*! \brief get SPI CRC send value or receive value \param[in] spi_periph: SPIx(x=0,1,2,3,4,5) - \param[in] spi_crc: + \param[in] spi_crc: SPI crc value + only one parameter can be selected which is shown as below: \arg SPI_CRC_TX: get transmit crc value \arg SPI_CRC_RX: get receive crc value \param[out] none @@ -692,18 +591,18 @@ void spi_ti_mode_disable(uint32_t spi_periph) /*! \brief configure i2s full duplex mode \param[in] i2s_add_periph: I2Sx_ADD(x=1,2) - \param[in] i2s_mode: + \param[in] i2s_mode: \arg I2S_MODE_SLAVETX : I2S slave transmit mode \arg I2S_MODE_SLAVERX : I2S slave receive mode \arg I2S_MODE_MASTERTX : I2S master transmit mode \arg I2S_MODE_MASTERRX : I2S master receive mode - \param[in] i2s_standard: + \param[in] i2s_standard: \arg I2S_STD_PHILLIPS : I2S phillips standard \arg I2S_STD_MSB : I2S MSB standard \arg I2S_STD_LSB : I2S LSB standard \arg I2S_STD_PCMSHORT : I2S PCM short standard \arg I2S_STD_PCMLONG : I2S PCM long standard - \param[in] i2s_ckpl: + \param[in] i2s_ckpl: \arg I2S_CKPL_LOW : I2S clock polarity low level \arg I2S_CKPL_HIGH : I2S clock polarity high level \param[in] i2s_frameformat: @@ -720,7 +619,7 @@ void i2s_full_duplex_mode_config(uint32_t i2s_add_periph, uint32_t i2s_mode, uin uint32_t reg = 0U, tmp = 0U; reg = I2S_ADD_I2SCTL(i2s_add_periph); - reg &= I2S_FULL_DUPLEX_MASK; + reg &= I2S_FULL_DUPLEX_MASK; /* get the mode of the extra I2S module I2Sx_ADD */ if((I2S_MODE_MASTERTX == i2s_mode) || (I2S_MODE_SLAVETX == i2s_mode)){ @@ -730,7 +629,7 @@ void i2s_full_duplex_mode_config(uint32_t i2s_add_periph, uint32_t i2s_mode, uin } /* enable I2S mode */ - reg |= (uint32_t)SPI_I2SCTL_I2SSEL; + reg |= (uint32_t)SPI_I2SCTL_I2SSEL; /* select I2S mode */ reg |= (uint32_t)tmp; /* select I2S standard */ @@ -745,7 +644,7 @@ void i2s_full_duplex_mode_config(uint32_t i2s_add_periph, uint32_t i2s_mode, uin } /*! - \brief quad wire SPI enable + \brief enable quad wire SPI \param[in] spi_periph: SPIx(only x=5) \param[out] none \retval none @@ -756,7 +655,7 @@ void qspi_enable(uint32_t spi_periph) } /*! - \brief quad wire SPI disable + \brief disable quad wire SPI \param[in] spi_periph: SPIx(only x=5) \param[out] none \retval none @@ -767,7 +666,7 @@ void qspi_disable(uint32_t spi_periph) } /*! - \brief quad wire SPI write enable + \brief enable quad wire SPI write \param[in] spi_periph: SPIx(only x=5) \param[out] none \retval none @@ -778,7 +677,7 @@ void qspi_write_enable(uint32_t spi_periph) } /*! - \brief quad wire SPI read enable + \brief enable quad wire SPI read \param[in] spi_periph: SPIx(only x=5) \param[out] none \retval none @@ -789,7 +688,7 @@ void qspi_read_enable(uint32_t spi_periph) } /*! - \brief SPI_IO2 and SPI_IO3 pin output enable + \brief enable SPI_IO2 and SPI_IO3 pin output \param[in] spi_periph: SPIx(only x=5) \param[out] none \retval none @@ -800,7 +699,7 @@ void qspi_io23_output_enable(uint32_t spi_periph) } /*! - \brief SPI_IO2 and SPI_IO3 pin output disable + \brief disable SPI_IO2 and SPI_IO3 pin output \param[in] spi_periph: SPIx(only x=5) \param[out] none \retval none @@ -809,3 +708,175 @@ void qspi_io23_output_enable(uint32_t spi_periph) { SPI_QCTL(spi_periph) &= (uint32_t)(~SPI_QCTL_IO23_DRV); } + +/*! + \brief enable SPI and I2S interrupt + \param[in] spi_periph: SPIx(x=0,1,2,3,4,5) + \param[in] spi_i2s_int: SPI/I2S interrupt + only one parameter can be selected which is shown as below: + \arg SPI_I2S_INT_TBE: transmit buffer empty interrupt + \arg SPI_I2S_INT_RBNE: receive buffer not empty interrupt + \arg SPI_I2S_INT_ERR: CRC error,configuration error,reception overrun error, + transmission underrun error and format error interrupt + \param[out] none + \retval none +*/ +void spi_i2s_interrupt_enable(uint32_t spi_periph, uint8_t spi_i2s_int) +{ + switch(spi_i2s_int){ + /* SPI/I2S transmit buffer empty interrupt */ + case SPI_I2S_INT_TBE: + SPI_CTL1(spi_periph) |= (uint32_t)SPI_CTL1_TBEIE; + break; + /* SPI/I2S receive buffer not empty interrupt */ + case SPI_I2S_INT_RBNE: + SPI_CTL1(spi_periph) |= (uint32_t)SPI_CTL1_RBNEIE; + break; + /* SPI/I2S error */ + case SPI_I2S_INT_ERR: + SPI_CTL1(spi_periph) |= (uint32_t)SPI_CTL1_ERRIE; + break; + default: + break; + } +} + +/*! + \brief disable SPI and I2S interrupt + \param[in] spi_periph: SPIx(x=0,1,2,3,4,5) + \param[in] spi_i2s_int: SPI/I2S interrupt + only one parameter can be selected which is shown as below: + \arg SPI_I2S_INT_TBE: transmit buffer empty interrupt + \arg SPI_I2S_INT_RBNE: receive buffer not empty interrupt + \arg SPI_I2S_INT_ERR: CRC error,configuration error,reception overrun error, + transmission underrun error and format error interrupt + \param[out] none + \retval none +*/ +void spi_i2s_interrupt_disable(uint32_t spi_periph, uint8_t spi_i2s_int) +{ + switch(spi_i2s_int){ + /* SPI/I2S transmit buffer empty interrupt */ + case SPI_I2S_INT_TBE : + SPI_CTL1(spi_periph) &= (uint32_t)(~SPI_CTL1_TBEIE); + break; + /* SPI/I2S receive buffer not empty interrupt */ + case SPI_I2S_INT_RBNE : + SPI_CTL1(spi_periph) &= (uint32_t)(~SPI_CTL1_RBNEIE); + break; + /* SPI/I2S error */ + case SPI_I2S_INT_ERR : + SPI_CTL1(spi_periph) &= (uint32_t)(~SPI_CTL1_ERRIE); + break; + default : + break; + } +} + +/*! + \brief get SPI and I2S interrupt flag status + \param[in] spi_periph: SPIx(x=0,1,2,3,4,5) + \param[in] spi_i2s_int: SPI/I2S interrupt flag status + \arg SPI_I2S_INT_FLAG_TBE: transmit buffer empty interrupt flag + \arg SPI_I2S_INT_FLAG_RBNE: receive buffer not empty interrupt flag + \arg SPI_I2S_INT_FLAG_RXORERR: overrun interrupt flag + \arg SPI_INT_FLAG_CONFERR: config error interrupt flag + \arg SPI_INT_FLAG_CRCERR: CRC error interrupt flag + \arg I2S_INT_FLAG_TXURERR: underrun error interrupt flag + \arg SPI_I2S_INT_FLAG_FERR: format error interrupt flag + \param[out] none + \retval FlagStatus: SET or RESET +*/ +FlagStatus spi_i2s_interrupt_flag_get(uint32_t spi_periph, uint8_t spi_i2s_int) +{ + uint32_t reg1 = SPI_STAT(spi_periph); + uint32_t reg2 = SPI_CTL1(spi_periph); + + switch(spi_i2s_int){ + /* SPI/I2S transmit buffer empty interrupt */ + case SPI_I2S_INT_FLAG_TBE : + reg1 = reg1 & SPI_STAT_TBE; + reg2 = reg2 & SPI_CTL1_TBEIE; + break; + /* SPI/I2S receive buffer not empty interrupt */ + case SPI_I2S_INT_FLAG_RBNE : + reg1 = reg1 & SPI_STAT_RBNE; + reg2 = reg2 & SPI_CTL1_RBNEIE; + break; + /* SPI/I2S overrun interrupt */ + case SPI_I2S_INT_FLAG_RXORERR : + reg1 = reg1 & SPI_STAT_RXORERR; + reg2 = reg2 & SPI_CTL1_ERRIE; + break; + /* SPI config error interrupt */ + case SPI_INT_FLAG_CONFERR : + reg1 = reg1 & SPI_STAT_CONFERR; + reg2 = reg2 & SPI_CTL1_ERRIE; + break; + /* SPI CRC error interrupt */ + case SPI_INT_FLAG_CRCERR : + reg1 = reg1 & SPI_STAT_CRCERR; + reg2 = reg2 & SPI_CTL1_ERRIE; + break; + /* I2S underrun error interrupt */ + case I2S_INT_FLAG_TXURERR : + reg1 = reg1 & SPI_STAT_TXURERR; + reg2 = reg2 & SPI_CTL1_ERRIE; + break; + /* SPI/I2S format error interrupt */ + case SPI_I2S_INT_FLAG_FERR : + reg1 = reg1 & SPI_STAT_FERR; + reg2 = reg2 & SPI_CTL1_ERRIE; + break; + default : + break; + } + /*get SPI/I2S interrupt flag status */ + if(reg1 && reg2){ + return SET; + }else{ + return RESET; + } +} + +/*! + \brief get SPI and I2S flag status + \param[in] spi_periph: SPIx(x=0,1,2,3,4,5) + \param[in] spi_i2s_flag: SPI/I2S flag status + \arg SPI_FLAG_TBE: transmit buffer empty flag + \arg SPI_FLAG_RBNE: receive buffer not empty flag + \arg SPI_FLAG_TRANS: transmit on-going flag + \arg SPI_FLAG_RXORERR: receive overrun error flag + \arg SPI_FLAG_CONFERR: mode config error flag + \arg SPI_FLAG_CRCERR: CRC error flag + \arg SPI_FLAG_FERR: format error flag + \arg I2S_FLAG_TBE: transmit buffer empty flag + \arg I2S_FLAG_RBNE: receive buffer not empty flag + \arg I2S_FLAG_TRANS: transmit on-going flag + \arg I2S_FLAG_RXORERR: overrun error flag + \arg I2S_FLAG_TXURERR: underrun error flag + \arg I2S_FLAG_CH: channel side flag + \arg I2S_FLAG_FERR: format error flag + \param[out] none + \retval FlagStatus: SET or RESET +*/ +FlagStatus spi_i2s_flag_get(uint32_t spi_periph, uint32_t spi_i2s_flag) +{ + if(SPI_STAT(spi_periph) & spi_i2s_flag){ + return SET; + }else{ + return RESET; + } +} + +/*! + \brief clear SPI CRC error flag status + \param[in] spi_periph: SPIx(x=0,1,2,3,4,5) + \param[out] none + \retval none +*/ +void spi_crc_error_clear(uint32_t spi_periph) +{ + SPI_STAT(spi_periph) &= (uint32_t)(~SPI_FLAG_CRCERR); +} + diff --git a/bsp/gd32450z-eval/Libraries/GD32F4xx_standard_peripheral/Source/gd32f4xx_syscfg.c b/bsp/gd32450z-eval/Libraries/GD32F4xx_standard_peripheral/Source/gd32f4xx_syscfg.c index d834462aba..6fa0a776d0 100644 --- a/bsp/gd32450z-eval/Libraries/GD32F4xx_standard_peripheral/Source/gd32f4xx_syscfg.c +++ b/bsp/gd32450z-eval/Libraries/GD32F4xx_standard_peripheral/Source/gd32f4xx_syscfg.c @@ -1,12 +1,37 @@ /*! - \file gd32f4xx_syscfg.c - \brief SYSCFG driver + \file gd32f4xx_syscfg.c + \brief SYSCFG driver + + \version 2016-08-15, V1.0.0, firmware for GD32F4xx + \version 2018-12-12, V2.0.0, firmware for GD32F4xx + \version 2020-09-30, V2.1.0, firmware for GD32F4xx */ /* - Copyright (C) 2016 GigaDevice + Copyright (c) 2020, GigaDevice Semiconductor Inc. + + Redistribution and use in source and binary forms, with or without modification, +are permitted provided that the following conditions are met: + + 1. Redistributions of source code must retain the above copyright notice, this + list of conditions and the following disclaimer. + 2. Redistributions in binary form must reproduce the above copyright notice, + this list of conditions and the following disclaimer in the documentation + and/or other materials provided with the distribution. + 3. Neither the name of the copyright holder nor the names of its contributors + may be used to endorse or promote products derived from this software without + specific prior written permission. - 2016-08-15, V1.0.0, firmware for GD32F4xx + THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED +WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. +IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, +INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT +NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR +PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, +WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY +OF SUCH DAMAGE. */ #include "gd32f4xx_syscfg.h" @@ -24,8 +49,9 @@ void syscfg_deinit(void) } /*! - \brief configure the boot mode + \brief configure the boot mode \param[in] syscfg_bootmode: selects the memory remapping + only one parameter can be selected which is shown as below: \arg SYSCFG_BOOTMODE_FLASH: main flash memory (0x08000000~0x083BFFFF) is mapped at address 0x00000000 \arg SYSCFG_BOOTMODE_BOOTLOADER: boot loader (0x1FFF0000 - 0x1FFF77FF) is mapped at address 0x00000000 \arg SYSCFG_BOOTMODE_EXMC_SRAM: SRAM/NOR 0 and 1 of EXMC (0x60000000~0x67FFFFFF) is mapped at address 0x00000000 @@ -44,6 +70,7 @@ void syscfg_bootmode_config(uint8_t syscfg_bootmode) /*! \brief FMC memory mapping swap \param[in] syscfg_fmc_swap: selects the interal flash bank swapping + only one parameter can be selected which is shown as below: \arg SYSCFG_FMC_SWP_BANK0: bank 0 is mapped at address 0x08000000 and bank 1 is mapped at address 0x08100000 \arg SYSCFG_FMC_SWP_BANK1: bank 1 is mapped at address 0x08000000 and bank 0 is mapped at address 0x08100000 \param[out] none @@ -61,6 +88,7 @@ void syscfg_fmc_swap_config(uint32_t syscfg_fmc_swap) /*! \brief EXMC memory mapping swap \param[in] syscfg_exmc_swap: selects the memories in EXMC swapping + only one parameter can be selected which is shown as below: \arg SYSCFG_EXMC_SWP_ENABLE: SDRAM bank 0 and bank 1 are swapped with NAND bank 1 and PC card \arg SYSCFG_EXMC_SWP_DISABLE: no memory mapping swap \param[out] none @@ -79,8 +107,10 @@ void syscfg_exmc_swap_config(uint32_t syscfg_exmc_swap) /*! \brief configure the GPIO pin as EXTI Line \param[in] exti_port: specify the GPIO port used in EXTI + only one parameter can be selected which is shown as below: \arg EXTI_SOURCE_GPIOx(x = A,B,C,D,E,F,G,H,I): EXTI GPIO port \param[in] exti_pin: specify the EXTI line + only one parameter can be selected which is shown as below: \arg EXTI_SOURCE_PINx(x = 0..15): EXTI GPIO pin \param[out] none \retval none @@ -123,15 +153,16 @@ void syscfg_exti_line_config(uint8_t exti_port, uint8_t exti_pin) /*! \brief configure the PHY interface for the ethernet MAC \param[in] syscfg_enet_phy_interface: specifies the media interface mode. + only one parameter can be selected which is shown as below: \arg SYSCFG_ENET_PHY_MII: MII mode is selected - \arg SYSCFG_ENET_PHY_RMII: RMII mode is selected + \arg SYSCFG_ENET_PHY_RMII: RMII mode is selected \param[out] none \retval none */ void syscfg_enet_phy_interface_config(uint32_t syscfg_enet_phy_interface) -{ +{ uint32_t reg; - + reg = SYSCFG_CFG1; /* reset the ENET_PHY_SEL bit and set according to syscfg_enet_phy_interface */ reg &= ~SYSCFG_CFG1_ENET_PHY_SEL; @@ -141,12 +172,13 @@ void syscfg_enet_phy_interface_config(uint32_t syscfg_enet_phy_interface) /*! \brief configure the I/O compensation cell \param[in] syscfg_compensation: specifies the I/O compensation cell mode + only one parameter can be selected which is shown as below: \arg SYSCFG_COMPENSATION_ENABLE: I/O compensation cell is enabled \arg SYSCFG_COMPENSATION_DISABLE: I/O compensation cell is disabled \param[out] none \retval none */ -void syscfg_compensation_config(uint32_t syscfg_compensation) +void syscfg_compensation_config(uint32_t syscfg_compensation) { uint32_t reg; diff --git a/bsp/gd32450z-eval/Libraries/GD32F4xx_standard_peripheral/Source/gd32f4xx_timer.c b/bsp/gd32450z-eval/Libraries/GD32F4xx_standard_peripheral/Source/gd32f4xx_timer.c index 04c8fab0d3..e312680222 100644 --- a/bsp/gd32450z-eval/Libraries/GD32F4xx_standard_peripheral/Source/gd32f4xx_timer.c +++ b/bsp/gd32450z-eval/Libraries/GD32F4xx_standard_peripheral/Source/gd32f4xx_timer.c @@ -1,14 +1,40 @@ /*! - \file gd32f4xx_timer.c - \brief TIMER driver + \file gd32f4xx_timer.c + \brief TIMER driver + + \version 2016-08-15, V1.0.0, firmware for GD32F4xx + \version 2018-12-12, V2.0.0, firmware for GD32F4xx + \version 2020-09-30, V2.1.0, firmware for GD32F4xx */ /* - Copyright (C) 2016 GigaDevice + Copyright (c) 2020, GigaDevice Semiconductor Inc. + + Redistribution and use in source and binary forms, with or without modification, +are permitted provided that the following conditions are met: + + 1. Redistributions of source code must retain the above copyright notice, this + list of conditions and the following disclaimer. + 2. Redistributions in binary form must reproduce the above copyright notice, + this list of conditions and the following disclaimer in the documentation + and/or other materials provided with the distribution. + 3. Neither the name of the copyright holder nor the names of its contributors + may be used to endorse or promote products derived from this software without + specific prior written permission. - 2016-08-15, V1.0.0, firmware for GD32F4xx + THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED +WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. +IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, +INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT +NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR +PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, +WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY +OF SUCH DAMAGE. */ + #include "gd32f4xx_timer.h" /*! @@ -96,9 +122,26 @@ void timer_deinit(uint32_t timer_periph) } /*! + \brief initialize TIMER init parameter struct with a default value + \param[in] initpara: init parameter struct + \param[out] none + \retval none +*/ +void timer_struct_para_init(timer_parameter_struct* initpara) +{ + /* initialize the init parameter struct member with the default value */ + initpara->prescaler = 0U; + initpara->alignedmode = TIMER_COUNTER_EDGE; + initpara->counterdirection = TIMER_COUNTER_UP; + initpara->period = 65535U; + initpara->clockdivision = TIMER_CKDIV_DIV1; + initpara->repetitioncounter = 0U; +} + +/*! \brief initialize TIMER counter \param[in] timer_periph: TIMERx(x=0..13) - \param[in] timer_initpara: init parameter struct + \param[in] initpara: init parameter struct prescaler: prescaler value of the counter clock,0~65535 alignedmode: TIMER_COUNTER_EDGE,TIMER_COUNTER_CENTER_DOWN,TIMER_COUNTER_CENTER_UP,TIMER_COUNTER_CENTER_BOTH counterdirection: TIMER_COUNTER_UP,TIMER_COUNTER_DOWN @@ -108,31 +151,31 @@ void timer_deinit(uint32_t timer_periph) \param[out] none \retval none */ -void timer_init(uint32_t timer_periph, timer_parameter_struct* timer_initpara) +void timer_init(uint32_t timer_periph, timer_parameter_struct* initpara) { /* configure the counter prescaler value */ - TIMER_PSC(timer_periph) = (uint16_t)timer_initpara->prescaler; + TIMER_PSC(timer_periph) = (uint16_t)initpara->prescaler; /* configure the counter direction and aligned mode */ if((TIMER0 == timer_periph) || (TIMER1 == timer_periph) || (TIMER2 == timer_periph) || (TIMER3 == timer_periph) || (TIMER4 == timer_periph) || (TIMER7 == timer_periph)){ TIMER_CTL0(timer_periph) &= ~(uint32_t)(TIMER_CTL0_DIR|TIMER_CTL0_CAM); - TIMER_CTL0(timer_periph) |= (uint32_t)timer_initpara->alignedmode; - TIMER_CTL0(timer_periph) |= (uint32_t)timer_initpara->counterdirection; + TIMER_CTL0(timer_periph) |= (uint32_t)initpara->alignedmode; + TIMER_CTL0(timer_periph) |= (uint32_t)initpara->counterdirection; } /* configure the autoreload value */ - TIMER_CAR(timer_periph) = (uint32_t)timer_initpara->period; + TIMER_CAR(timer_periph) = (uint32_t)initpara->period; if((TIMER5 != timer_periph) && (TIMER6 != timer_periph)){ /* reset the CKDIV bit */ TIMER_CTL0(timer_periph) &= ~(uint32_t)TIMER_CTL0_CKDIV; - TIMER_CTL0(timer_periph) |= (uint32_t)timer_initpara->clockdivision; + TIMER_CTL0(timer_periph) |= (uint32_t)initpara->clockdivision; } if((TIMER0 == timer_periph) || (TIMER7 == timer_periph)){ /* configure the repetition counter value */ - TIMER_CREP(timer_periph) = (uint32_t)timer_initpara->repetitioncounter; + TIMER_CREP(timer_periph) = (uint32_t)initpara->repetitioncounter; } /* generate an update event */ @@ -208,7 +251,8 @@ void timer_update_event_disable(uint32_t timer_periph) /*! \brief set TIMER counter alignment mode \param[in] timer_periph: TIMERx(x=0..4,7) - \param[in] timer_aligned: + \param[in] aligned: + only one parameter can be selected which is shown as below: \arg TIMER_COUNTER_EDGE: edge-aligned mode \arg TIMER_COUNTER_CENTER_DOWN: center-aligned and counting down assert mode \arg TIMER_COUNTER_CENTER_UP: center-aligned and counting up assert mode @@ -216,10 +260,10 @@ void timer_update_event_disable(uint32_t timer_periph) \param[out] none \retval none */ -void timer_counter_alignment(uint32_t timer_periph,uint16_t timer_aligned) +void timer_counter_alignment(uint32_t timer_periph, uint16_t aligned) { TIMER_CTL0(timer_periph) &= ~(uint32_t)TIMER_CTL0_CAM; - TIMER_CTL0(timer_periph) |= (uint32_t)timer_aligned; + TIMER_CTL0(timer_periph) |= (uint32_t)aligned; } /*! @@ -247,18 +291,19 @@ void timer_counter_down_direction(uint32_t timer_periph) /*! \brief configure TIMER prescaler \param[in] timer_periph: TIMERx(x=0..13) - \param[in] timer_prescaler: prescaler value - \param[in] timer_pscreload: prescaler reload mode + \param[in] prescaler: prescaler value,0~65535 + \param[in] pscreload: prescaler reload mode + only one parameter can be selected which is shown as below: \arg TIMER_PSC_RELOAD_NOW: the prescaler is loaded right now \arg TIMER_PSC_RELOAD_UPDATE: the prescaler is loaded at the next update event \param[out] none \retval none */ -void timer_prescaler_config(uint32_t timer_periph,uint16_t timer_prescaler,uint8_t timer_pscreload) +void timer_prescaler_config(uint32_t timer_periph, uint16_t prescaler, uint8_t pscreload) { - TIMER_PSC(timer_periph) = (uint32_t)timer_prescaler; - - if(TIMER_PSC_RELOAD_NOW == timer_pscreload){ + TIMER_PSC(timer_periph) = (uint32_t)prescaler; + + if(TIMER_PSC_RELOAD_NOW == pscreload){ TIMER_SWEVG(timer_periph) |= (uint32_t)TIMER_SWEVG_UPG; } } @@ -266,37 +311,37 @@ void timer_prescaler_config(uint32_t timer_periph,uint16_t timer_prescaler,uint8 /*! \brief configure TIMER repetition register value \param[in] timer_periph: TIMERx(x=0,7) - \param[in] timer_repetition: the counter repetition value,0~255 + \param[in] repetition: the counter repetition value,0~255 \param[out] none \retval none */ -void timer_repetition_value_config(uint32_t timer_periph,uint16_t timer_repetition) +void timer_repetition_value_config(uint32_t timer_periph, uint16_t repetition) { - TIMER_CREP(timer_periph) = (uint32_t)timer_repetition; -} - + TIMER_CREP(timer_periph) = (uint32_t)repetition; +} + /*! \brief configure TIMER autoreload register value \param[in] timer_periph: TIMERx(x=0..13) - \param[in] timer_autoreload: the counter auto-reload value + \param[in] autoreload: the counter auto-reload value \param[out] none \retval none -*/ -void timer_autoreload_value_config(uint32_t timer_periph,uint32_t timer_autoreload) +*/ +void timer_autoreload_value_config(uint32_t timer_periph,uint32_t autoreload) { - TIMER_CAR(timer_periph) = (uint32_t)timer_autoreload; + TIMER_CAR(timer_periph) = (uint32_t)autoreload; } /*! \brief configure TIMER counter register value \param[in] timer_periph: TIMERx(x=0..13) - \param[in] timer_counter: the counter value + \param[in] counter: the counter value,0~65535 \param[out] none \retval none -*/ -void timer_counter_value_config(uint32_t timer_periph , uint32_t timer_counter) +*/ +void timer_counter_value_config(uint32_t timer_periph , uint32_t counter) { - TIMER_CNT(timer_periph) = (uint32_t)timer_counter; + TIMER_CNT(timer_periph) = (uint32_t)counter; } /*! @@ -304,7 +349,7 @@ void timer_counter_value_config(uint32_t timer_periph , uint32_t timer_counter) \param[in] timer_periph: TIMERx(x=0..13) \param[out] none \retval counter value -*/ +*/ uint32_t timer_counter_read(uint32_t timer_periph) { uint32_t count_value = 0U; @@ -317,56 +362,61 @@ uint32_t timer_counter_read(uint32_t timer_periph) \param[in] timer_periph: TIMERx(x=0..13) \param[out] none \retval prescaler register value -*/ +*/ uint16_t timer_prescaler_read(uint32_t timer_periph) { uint16_t prescaler_value = 0U; - prescaler_value = (uint16_t)(TIMER_CAR(timer_periph)); + prescaler_value = (uint16_t)(TIMER_PSC(timer_periph)); return (prescaler_value); } /*! \brief configure TIMER single pulse mode \param[in] timer_periph: TIMERx(x=0..8,11) - \param[in] timer_spmode: + \param[in] spmode: + only one parameter can be selected which is shown as below: \arg TIMER_SP_MODE_SINGLE: single pulse mode \arg TIMER_SP_MODE_REPETITIVE: repetitive pulse mode \param[out] none \retval none */ -void timer_single_pulse_mode_config(uint32_t timer_periph,uint8_t timer_spmode) +void timer_single_pulse_mode_config(uint32_t timer_periph, uint32_t spmode) { - if(TIMER_SP_MODE_SINGLE == timer_spmode){ + if(TIMER_SP_MODE_SINGLE == spmode){ TIMER_CTL0(timer_periph) |= (uint32_t)TIMER_CTL0_SPM; - }else if(TIMER_SP_MODE_REPETITIVE == timer_spmode){ + }else if(TIMER_SP_MODE_REPETITIVE == spmode){ TIMER_CTL0(timer_periph) &= ~((uint32_t)TIMER_CTL0_SPM); }else{ + /* illegal parameters */ } } /*! - \brief configure TIMER update source + \brief configure TIMER update source \param[in] timer_periph: TIMERx(x=0..13) - \param[in] timer_update: + \param[in] update: + only one parameter can be selected which is shown as below: \arg TIMER_UPDATE_SRC_GLOBAL: update generate by setting of UPG bit or the counter overflow/underflow,or the slave mode controller trigger \arg TIMER_UPDATE_SRC_REGULAR: update generate only by counter overflow/underflow \param[out] none \retval none */ -void timer_update_source_config(uint32_t timer_periph,uint8_t timer_update) +void timer_update_source_config(uint32_t timer_periph, uint32_t update) { - if(TIMER_UPDATE_SRC_REGULAR == timer_update){ + if(TIMER_UPDATE_SRC_REGULAR == update){ TIMER_CTL0(timer_periph) |= (uint32_t)TIMER_CTL0_UPS; - }else if(timer_update == TIMER_UPDATE_SRC_GLOBAL){ + }else if(TIMER_UPDATE_SRC_GLOBAL == update){ TIMER_CTL0(timer_periph) &= ~(uint32_t)TIMER_CTL0_UPS; }else{ + /* illegal parameters */ } } /*! \brief enable the TIMER interrupt - \param[in] timer_periph: please refer to the following parameters - \param[in] timer_interrupt: timer interrupt enable source + \param[in] timer_periph: please refer to the following parameters + \param[in] interrupt: timer interrupt enable source + only one parameter can be selected which is shown as below: \arg TIMER_INT_UP: update interrupt enable, TIMERx(x=0..13) \arg TIMER_INT_CH0: channel 0 interrupt enable, TIMERx(x=0..4,7..13) \arg TIMER_INT_CH1: channel 1 interrupt enable, TIMERx(x=0..4,7,8,11) @@ -378,15 +428,16 @@ void timer_update_source_config(uint32_t timer_periph,uint8_t timer_update) \param[out] none \retval none */ -void timer_interrupt_enable(uint32_t timer_periph,uint32_t timer_interrupt) +void timer_interrupt_enable(uint32_t timer_periph, uint32_t interrupt) { - TIMER_DMAINTEN(timer_periph) |= (uint32_t) timer_interrupt; + TIMER_DMAINTEN(timer_periph) |= (uint32_t) interrupt; } /*! \brief disable the TIMER interrupt \param[in] timer_periph: please refer to the following parameters - \param[in] timer_interrupt: timer interrupt source enable + \param[in] interrupt: timer interrupt source enable + only one parameter can be selected which is shown as below: \arg TIMER_INT_UP: update interrupt enable, TIMERx(x=0..13) \arg TIMER_INT_CH0: channel 0 interrupt enable, TIMERx(x=0..4,7..13) \arg TIMER_INT_CH1: channel 1 interrupt enable, TIMERx(x=0..4,7,8,11) @@ -398,31 +449,32 @@ void timer_interrupt_enable(uint32_t timer_periph,uint32_t timer_interrupt) \param[out] none \retval none */ -void timer_interrupt_disable(uint32_t timer_periph,uint32_t timer_interrupt) +void timer_interrupt_disable(uint32_t timer_periph, uint32_t interrupt) { - TIMER_DMAINTEN(timer_periph) &= (~(uint32_t)timer_interrupt); + TIMER_DMAINTEN(timer_periph) &= (~(uint32_t)interrupt); } /*! \brief get timer interrupt flag \param[in] timer_periph: please refer to the following parameters - \param[in] timer_interrupt: the timer interrupt bits - \arg TIMER_INT_UP: update interrupt flag,TIMERx(x=0..13) - \arg TIMER_INT_CH0: channel 0 interrupt flag,TIMERx(x=0..4,7..13) - \arg TIMER_INT_CH1: channel 1 interrupt flag,TIMERx(x=0..4,7,8,11) - \arg TIMER_INT_CH2: channel 2 interrupt flag,TIMERx(x=0..4,7) - \arg TIMER_INT_CH3: channel 3 interrupt flag,TIMERx(x=0..4,7) - \arg TIMER_INT_CMT: channel commutation interrupt flag,TIMERx(x=0,7) - \arg TIMER_INT_TRG: trigger interrupt flag,TIMERx(x=0,7,8,11) - \arg TIMER_INT_BRK: break interrupt flag,TIMERx(x=0,7) + \param[in] interrupt: the timer interrupt bits + only one parameter can be selected which is shown as below: + \arg TIMER_INT_FLAG_UP: update interrupt flag,TIMERx(x=0..13) + \arg TIMER_INT_FLAG_CH0: channel 0 interrupt flag,TIMERx(x=0..4,7..13) + \arg TIMER_INT_FLAG_CH1: channel 1 interrupt flag,TIMERx(x=0..4,7,8,11) + \arg TIMER_INT_FLAG_CH2: channel 2 interrupt flag,TIMERx(x=0..4,7) + \arg TIMER_INT_FLAG_CH3: channel 3 interrupt flag,TIMERx(x=0..4,7) + \arg TIMER_INT_FLAG_CMT: channel commutation interrupt flag,TIMERx(x=0,7) + \arg TIMER_INT_FLAG_TRG: trigger interrupt flag,TIMERx(x=0,7,8,11) + \arg TIMER_INT_FLAG_BRK: break interrupt flag,TIMERx(x=0,7) \param[out] none \retval FlagStatus: SET or RESET */ -FlagStatus timer_interrupt_flag_get(uint32_t timer_periph,uint32_t timer_interrupt) +FlagStatus timer_interrupt_flag_get(uint32_t timer_periph, uint32_t interrupt) { uint32_t val; - val = (TIMER_DMAINTEN(timer_periph) & timer_interrupt); - if((RESET != (TIMER_INTF(timer_periph) & timer_interrupt) ) && (RESET != val)){ + val = (TIMER_DMAINTEN(timer_periph) & interrupt); + if((RESET != (TIMER_INTF(timer_periph) & interrupt) ) && (RESET != val)){ return SET; }else{ return RESET; @@ -432,34 +484,36 @@ FlagStatus timer_interrupt_flag_get(uint32_t timer_periph,uint32_t timer_interru /*! \brief clear TIMER interrupt flag \param[in] timer_periph: please refer to the following parameters - \param[in] timer_interrupt: the timer interrupt bits - \arg TIMER_INT_UP: update interrupt flag,TIMERx(x=0..13) - \arg TIMER_INT_CH0: channel 0 interrupt flag,TIMERx(x=0..4,7..13) - \arg TIMER_INT_CH1: channel 1 interrupt flag,TIMERx(x=0..4,7,8,11) - \arg TIMER_INT_CH2: channel 2 interrupt flag,TIMERx(x=0..4,7) - \arg TIMER_INT_CH3: channel 3 interrupt flag,TIMERx(x=0..4,7) - \arg TIMER_INT_CMT: channel commutation interrupt flag,TIMERx(x=0,7) - \arg TIMER_INT_TRG: trigger interrupt flag,TIMERx(x=0,7,8,11) - \arg TIMER_INT_BRK: break interrupt flag,TIMERx(x=0,7) + \param[in] interrupt: the timer interrupt bits + only one parameter can be selected which is shown as below: + \arg TIMER_INT_FLAG_UP: update interrupt flag,TIMERx(x=0..13) + \arg TIMER_INT_FLAG_CH0: channel 0 interrupt flag,TIMERx(x=0..4,7..13) + \arg TIMER_INT_FLAG_CH1: channel 1 interrupt flag,TIMERx(x=0..4,7,8,11) + \arg TIMER_INT_FLAG_CH2: channel 2 interrupt flag,TIMERx(x=0..4,7) + \arg TIMER_INT_FLAG_CH3: channel 3 interrupt flag,TIMERx(x=0..4,7) + \arg TIMER_INT_FLAG_CMT: channel commutation interrupt flag,TIMERx(x=0,7) + \arg TIMER_INT_FLAG_TRG: trigger interrupt flag,TIMERx(x=0,7,8,11) + \arg TIMER_INT_FLAG_BRK: break interrupt flag,TIMERx(x=0,7) \param[out] none \retval none */ -void timer_interrupt_flag_clear(uint32_t timer_periph,uint32_t timer_interrupt) +void timer_interrupt_flag_clear(uint32_t timer_periph, uint32_t interrupt) { - TIMER_INTF(timer_periph) &= (~(uint32_t)timer_interrupt); + TIMER_INTF(timer_periph) = (~(uint32_t)interrupt); } /*! \brief get TIMER flags \param[in] timer_periph: please refer to the following parameters - \param[in] timer_flag: the timer interrupt flags + \param[in] flag: the timer interrupt flags + only one parameter can be selected which is shown as below: \arg TIMER_FLAG_UP: update flag,TIMERx(x=0..13) \arg TIMER_FLAG_CH0: channel 0 flag,TIMERx(x=0..4,7..13) \arg TIMER_FLAG_CH1: channel 1 flag,TIMERx(x=0..4,7,8,11) \arg TIMER_FLAG_CH2: channel 2 flag,TIMERx(x=0..4,7) \arg TIMER_FLAG_CH3: channel 3 flag,TIMERx(x=0..4,7) - \arg TIMER_FLAG_CMT: channel control update flag,TIMERx(x=0,7) - \arg TIMER_FLAG_TRG: trigger flag,TIMERx(x=0,7,8,11) + \arg TIMER_FLAG_CMT: channel control update flag,TIMERx(x=0,7) + \arg TIMER_FLAG_TRG: trigger flag,TIMERx(x=0,7,8,11) \arg TIMER_FLAG_BRK: break flag,TIMERx(x=0,7) \arg TIMER_FLAG_CH0OF: channel 0 overcapture flag,TIMERx(x=0..4,7..11) \arg TIMER_FLAG_CH1OF: channel 1 overcapture flag,TIMERx(x=0..4,7,8,11) @@ -468,9 +522,9 @@ void timer_interrupt_flag_clear(uint32_t timer_periph,uint32_t timer_interrupt) \param[out] none \retval FlagStatus: SET or RESET */ -FlagStatus timer_flag_get(uint32_t timer_periph , uint32_t timer_flag) +FlagStatus timer_flag_get(uint32_t timer_periph, uint32_t flag) { - if(RESET != (TIMER_INTF(timer_periph) & timer_flag)){ + if(RESET != (TIMER_INTF(timer_periph) & flag)){ return SET; }else{ return RESET; @@ -480,14 +534,15 @@ FlagStatus timer_flag_get(uint32_t timer_periph , uint32_t timer_flag) /*! \brief clear TIMER flags \param[in] timer_periph: please refer to the following parameters - \param[in] timer_flag: the timer interrupt flags + \param[in] flag: the timer interrupt flags + only one parameter can be selected which is shown as below: \arg TIMER_FLAG_UP: update flag,TIMERx(x=0..13) \arg TIMER_FLAG_CH0: channel 0 flag,TIMERx(x=0..4,7..13) \arg TIMER_FLAG_CH1: channel 1 flag,TIMERx(x=0..4,7,8,11) \arg TIMER_FLAG_CH2: channel 2 flag,TIMERx(x=0..4,7) \arg TIMER_FLAG_CH3: channel 3 flag,TIMERx(x=0..4,7) - \arg TIMER_FLAG_CMT: channel control update flag,TIMERx(x=0,7) - \arg TIMER_FLAG_TRG: trigger flag,TIMERx(x=0,7,8,11) + \arg TIMER_FLAG_CMT: channel control update flag,TIMERx(x=0,7) + \arg TIMER_FLAG_TRG: trigger flag,TIMERx(x=0,7,8,11) \arg TIMER_FLAG_BRK: break flag,TIMERx(x=0,7) \arg TIMER_FLAG_CH0OF: channel 0 overcapture flag,TIMERx(x=0..4,7..11) \arg TIMER_FLAG_CH1OF: channel 1 overcapture flag,TIMERx(x=0..4,7,8,11) @@ -496,72 +551,77 @@ FlagStatus timer_flag_get(uint32_t timer_periph , uint32_t timer_flag) \param[out] none \retval none */ -void timer_flag_clear(uint32_t timer_periph , uint32_t timer_flag) +void timer_flag_clear(uint32_t timer_periph, uint32_t flag) { - TIMER_INTF(timer_periph) &= (~(uint32_t)timer_flag); + TIMER_INTF(timer_periph) = (~(uint32_t)flag); } /*! \brief enable the TIMER DMA - \param[in] timer_periph: TIMERx(x=0,1,2,5,14,15,16) - \param[in] timer_dma: timer DMA source enable - \arg TIMER_DMA_UPD: update DMA enable,TIMERx(x=0..7) - \arg TIMER_DMA_CH0D: channel 0 DMA enable,TIMERx(x=0..4,7) - \arg TIMER_DMA_CH1D: channel 1 DMA enable,TIMERx(x=0..4,7) - \arg TIMER_DMA_CH2D: channel 2 DMA enable,TIMERx(x=0..4,7) - \arg TIMER_DMA_CH3D: channel 3 DMA enable,TIMERx(x=0..4,7) - \arg TIMER_DMA_CMTD: commutation DMA request enable,TIMERx(x=0,7) - \arg TIMER_DMA_TRGD: trigger DMA enable,TIMERx(x=0..4,7) + \param[in] timer_periph: please refer to the following parameters + \param[in] dma: specify which DMA to enable + one or more parameters can be selected which is shown as below: + \arg TIMER_DMA_UPD: update DMA,TIMERx(x=0..7) + \arg TIMER_DMA_CH0D: channel 0 DMA request,TIMERx(x=0..4,7) + \arg TIMER_DMA_CH1D: channel 1 DMA request,TIMERx(x=0..4,7) + \arg TIMER_DMA_CH2D: channel 2 DMA request,TIMERx(x=0..4,7) + \arg TIMER_DMA_CH3D: channel 3 DMA request,TIMERx(x=0..4,7) + \arg TIMER_DMA_CMTD: commutation DMA request,TIMERx(x=0,7) + \arg TIMER_DMA_TRGD: trigger DMA request,TIMERx(x=0..4,7) \param[out] none \retval none */ -void timer_dma_enable(uint32_t timer_periph,uint16_t timer_dma) +void timer_dma_enable(uint32_t timer_periph, uint16_t dma) { - TIMER_DMAINTEN(timer_periph) |= (uint32_t) timer_dma; + TIMER_DMAINTEN(timer_periph) |= (uint32_t) dma; } /*! \brief disable the TIMER DMA \param[in] timer_periph: please refer to the following parameters - \param[in] timer_dma: timer DMA source enable - \arg TIMER_DMA_UPD: update DMA enable,TIMERx(x=0..7) - \arg TIMER_DMA_CH0D: channel 0 DMA enable,TIMERx(x=0..4,7) - \arg TIMER_DMA_CH1D: channel 1 DMA enable,TIMERx(x=0..4,7) - \arg TIMER_DMA_CH2D: channel 2 DMA enable,TIMERx(x=0..4,7) - \arg TIMER_DMA_CH3D: channel 3 DMA enable,TIMERx(x=0..4,7) - \arg TIMER_DMA_CMTD: commutation DMA request enable,TIMERx(x=0,7) - \arg TIMER_DMA_TRGD: trigger DMA enable,TIMERx(x=0..4,7) + \param[in] dma: specify which DMA to disable + one or more parameters can be selected which are shown as below: + \arg TIMER_DMA_UPD: update DMA,TIMERx(x=0..7) + \arg TIMER_DMA_CH0D: channel 0 DMA request,TIMERx(x=0..4,7) + \arg TIMER_DMA_CH1D: channel 1 DMA request,TIMERx(x=0..4,7) + \arg TIMER_DMA_CH2D: channel 2 DMA request,TIMERx(x=0..4,7) + \arg TIMER_DMA_CH3D: channel 3 DMA request,TIMERx(x=0..4,7) + \arg TIMER_DMA_CMTD: commutation DMA request ,TIMERx(x=0,7) + \arg TIMER_DMA_TRGD: trigger DMA request,TIMERx(x=0..4,7) \param[out] none \retval none */ -void timer_dma_disable(uint32_t timer_periph,uint16_t timer_dma) +void timer_dma_disable(uint32_t timer_periph, uint16_t dma) { - TIMER_DMAINTEN(timer_periph) &= (~(uint32_t)(timer_dma)); + TIMER_DMAINTEN(timer_periph) &= (~(uint32_t)(dma)); } /*! \brief channel DMA request source selection \param[in] timer_periph: TIMERx(x=0..4,7) \param[in] dma_request: channel DMA request source selection + only one parameter can be selected which is shown as below: \arg TIMER_DMAREQUEST_CHANNELEVENT: DMA request of channel y is sent when channel y event occurs - \arg TIMER_DMAREQUEST_UPDATEEVENT: DMA request of channel y is sent when update event occurs + \arg TIMER_DMAREQUEST_UPDATEEVENT: DMA request of channel y is sent when update event occurs \param[out] none \retval none */ -void timer_channel_dma_request_source_select(uint32_t timer_periph,uint8_t dma_request) +void timer_channel_dma_request_source_select(uint32_t timer_periph, uint8_t dma_request) { if(TIMER_DMAREQUEST_UPDATEEVENT == dma_request){ TIMER_CTL1(timer_periph) |= (uint32_t)TIMER_CTL1_DMAS; }else if(TIMER_DMAREQUEST_CHANNELEVENT == dma_request){ TIMER_CTL1(timer_periph) &= ~(uint32_t)TIMER_CTL1_DMAS; }else{ + /* illegal parameters */ } } /*! \brief configure the TIMER DMA transfer \param[in] timer_periph: please refer to the following parameters - \param[in] dma_baseaddr: + \param[in] dma_baseaddr: + only one parameter can be selected which is shown as below: \arg TIMER_DMACFG_DMATA_CTL0: DMA transfer address is TIMER_CTL0,TIMERx(x=0..4,7) \arg TIMER_DMACFG_DMATA_CTL1: DMA transfer address is TIMER_CTL1,TIMERx(x=0..4,7) \arg TIMER_DMACFG_DMATA_SMCFG: DMA transfer address is TIMER_SMCFG,TIMERx(x=0..4,7) @@ -579,44 +639,64 @@ void timer_channel_dma_request_source_select(uint32_t timer_periph,uint8_t dma_r \arg TIMER_DMACFG_DMATA_CH1CV: DMA transfer address is TIMER_CH1CV,TIMERx(x=0..4,7) \arg TIMER_DMACFG_DMATA_CH2CV: DMA transfer address is TIMER_CH2CV,TIMERx(x=0..4,7) \arg TIMER_DMACFG_DMATA_CH3CV: DMA transfer address is TIMER_CH3CV,TIMERx(x=0..4,7) - \arg TIMER_DMACFG_DMATA_CCHP: DMA transfer address is TIMER_CCHP,TIMERx(x=0,7) + \arg TIMER_DMACFG_DMATA_CCHP: DMA transfer address is TIMER_CCHP,TIMERx(x=0..4,7) \arg TIMER_DMACFG_DMATA_DMACFG: DMA transfer address is TIMER_DMACFG,TIMERx(x=0..4,7) \arg TIMER_DMACFG_DMATA_DMATB: DMA transfer address is TIMER_DMATB,TIMERx(x=0..4,7) \param[in] dma_lenth: + only one parameter can be selected which is shown as below: \arg TIMER_DMACFG_DMATC_xTRANSFER(x=1..18): DMA transfer x time \param[out] none \retval none */ -void timer_dma_transfer_config(uint32_t timer_periph,uint32_t dma_baseaddr,uint32_t dma_lenth) +void timer_dma_transfer_config(uint32_t timer_periph, uint32_t dma_baseaddr, uint32_t dma_lenth) { TIMER_DMACFG(timer_periph) &= (~(uint32_t)(TIMER_DMACFG_DMATA | TIMER_DMACFG_DMATC)); TIMER_DMACFG(timer_periph) |= (uint32_t)(dma_baseaddr | dma_lenth); } /*! - \brief software generate events + \brief software generate events \param[in] timer_periph: please refer to the following parameters - \param[in] timer_event: the timer software event generation sources + \param[in] event: the timer software event generation sources + one or more parameters can be selected which are shown as below: \arg TIMER_EVENT_SRC_UPG: update event,TIMERx(x=0..13) - \arg TIMER_EVENT_SRC_CH0G: channel 0 capture or compare event generation,TIMERx(x=0..4,7..13) + \arg TIMER_EVENT_SRC_CH0G: channel 0 capture or compare event generation,TIMERx(x=0..4,7..13) \arg TIMER_EVENT_SRC_CH1G: channel 1 capture or compare event generation,TIMERx(x=0..4,7,8,11) - \arg TIMER_EVENT_SRC_CH2G: channel 2 capture or compare event generation,TIMERx(x=0..4,7) - \arg TIMER_EVENT_SRC_CH3G: channel 3 capture or compare event generation,TIMERx(x=0..4,7) - \arg TIMER_EVENT_SRC_CMTG: channel commutation event generation,TIMERx(x=0,7) + \arg TIMER_EVENT_SRC_CH2G: channel 2 capture or compare event generation,TIMERx(x=0..4,7) + \arg TIMER_EVENT_SRC_CH3G: channel 3 capture or compare event generation,TIMERx(x=0..4,7) + \arg TIMER_EVENT_SRC_CMTG: channel commutation event generation,TIMERx(x=0,7) \arg TIMER_EVENT_SRC_TRGG: trigger event generation,TIMERx(x=0..4,7,8,11) \arg TIMER_EVENT_SRC_BRKG: break event generation,TIMERx(x=0,7) \param[out] none \retval none */ -void timer_event_software_generate(uint32_t timer_periph,uint16_t timer_event) +void timer_event_software_generate(uint32_t timer_periph, uint16_t event) { - TIMER_SWEVG(timer_periph) |= (uint32_t)timer_event; + TIMER_SWEVG(timer_periph) |= (uint32_t)event; } /*! - \brief configure TIMER break function + \brief initialize TIMER break parameter struct with a default value + \param[in] breakpara: TIMER break parameter struct + \param[out] none + \retval none +*/ +void timer_break_struct_para_init(timer_break_parameter_struct* breakpara) +{ + /* initialize the break parameter struct member with the default value */ + breakpara->runoffstate = TIMER_ROS_STATE_DISABLE; + breakpara->ideloffstate = TIMER_IOS_STATE_DISABLE; + breakpara->deadtime = 0U; + breakpara->breakpolarity = TIMER_BREAK_POLARITY_LOW; + breakpara->outputautostate = TIMER_OUTAUTO_DISABLE; + breakpara->protectmode = TIMER_CCHP_PROT_OFF; + breakpara->breakstate = TIMER_BREAK_DISABLE; +} + +/*! + \brief configure TIMER break function \param[in] timer_periph: TIMERx(x=0,7) - \param[in] timer_bkdtpara: TIMER break parameter struct + \param[in] breakpara: TIMER break parameter struct runoffstate: TIMER_ROS_STATE_ENABLE,TIMER_ROS_STATE_DISABLE ideloffstate: TIMER_IOS_STATE_ENABLE,TIMER_IOS_STATE_DISABLE deadtime: 0~255 @@ -627,15 +707,15 @@ void timer_event_software_generate(uint32_t timer_periph,uint16_t timer_event) \param[out] none \retval none */ -void timer_break_config(uint32_t timer_periph,timer_break_parameter_struct* timer_bkdtpara) +void timer_break_config(uint32_t timer_periph, timer_break_parameter_struct* breakpara) { - TIMER_CCHP(timer_periph) = (uint32_t)(((uint32_t)(timer_bkdtpara->runoffstate))| - ((uint32_t)(timer_bkdtpara->ideloffstate))| - ((uint32_t)(timer_bkdtpara->deadtime))| - ((uint32_t)(timer_bkdtpara->breakpolarity))| - ((uint32_t)(timer_bkdtpara->outputautostate)) | - ((uint32_t)(timer_bkdtpara->protectmode))| - ((uint32_t)(timer_bkdtpara->breakstate))) ; + TIMER_CCHP(timer_periph) = (uint32_t)(((uint32_t)(breakpara->runoffstate))| + ((uint32_t)(breakpara->ideloffstate))| + ((uint32_t)(breakpara->deadtime))| + ((uint32_t)(breakpara->breakpolarity))| + ((uint32_t)(breakpara->outputautostate)) | + ((uint32_t)(breakpara->protectmode))| + ((uint32_t)(breakpara->breakstate))) ; } /*! @@ -689,7 +769,7 @@ void timer_automatic_output_disable(uint32_t timer_periph) \param[out] none \retval none */ -void timer_primary_output_config(uint32_t timer_periph,ControlStatus newvalue) +void timer_primary_output_config(uint32_t timer_periph, ControlStatus newvalue) { if(ENABLE == newvalue){ TIMER_CCHP(timer_periph) |= (uint32_t)TIMER_CCHP_POEN; @@ -699,13 +779,13 @@ void timer_primary_output_config(uint32_t timer_periph,ControlStatus newvalue) } /*! - \brief channel capture/compare control shadow register enable + \brief enable or disable channel capture/compare control shadow register \param[in] timer_periph: TIMERx(x=0,7) - \param[in] newvalue: ENABLE or DISABLE + \param[in] newvalue: ENABLE or DISABLE \param[out] none \retval none */ -void timer_channel_control_shadow_config(uint32_t timer_periph,ControlStatus newvalue) +void timer_channel_control_shadow_config(uint32_t timer_periph, ControlStatus newvalue) { if(ENABLE == newvalue){ TIMER_CTL1(timer_periph) |= (uint32_t)TIMER_CTL1_CCSE; @@ -717,31 +797,51 @@ void timer_channel_control_shadow_config(uint32_t timer_periph,ControlStatus new /*! \brief configure TIMER channel control shadow register update control \param[in] timer_periph: TIMERx(x=0,7) - \param[in] timer_ccuctl: channel control shadow register update control + \param[in] ccuctl: channel control shadow register update control + only one parameter can be selected which is shown as below: \arg TIMER_UPDATECTL_CCU: the shadow registers update by when CMTG bit is set - \arg TIMER_UPDATECTL_CCUTRI: the shadow registers update by when CMTG bit is set or an rising edge of TRGI occurs + \arg TIMER_UPDATECTL_CCUTRI: the shadow registers update by when CMTG bit is set or an rising edge of TRGI occurs \param[out] none \retval none -*/ -void timer_channel_control_shadow_update_config(uint32_t timer_periph,uint8_t timer_ccuctl) +*/ +void timer_channel_control_shadow_update_config(uint32_t timer_periph, uint8_t ccuctl) { - if(TIMER_UPDATECTL_CCU == timer_ccuctl){ + if(TIMER_UPDATECTL_CCU == ccuctl){ TIMER_CTL1(timer_periph) &= (~(uint32_t)TIMER_CTL1_CCUC); - }else if(TIMER_UPDATECTL_CCUTRI == timer_ccuctl){ + }else if(TIMER_UPDATECTL_CCUTRI == ccuctl){ TIMER_CTL1(timer_periph) |= (uint32_t)TIMER_CTL1_CCUC; }else{ + /* illegal parameters */ } } /*! + \brief initialize TIMER channel output parameter struct with a default value + \param[in] ocpara: TIMER channel n output parameter struct + \param[out] none + \retval none +*/ +void timer_channel_output_struct_para_init(timer_oc_parameter_struct* ocpara) +{ + /* initialize the channel output parameter struct member with the default value */ + ocpara->outputstate = (uint16_t)TIMER_CCX_DISABLE; + ocpara->outputnstate = TIMER_CCXN_DISABLE; + ocpara->ocpolarity = TIMER_OC_POLARITY_HIGH; + ocpara->ocnpolarity = TIMER_OCN_POLARITY_HIGH; + ocpara->ocidlestate = TIMER_OC_IDLE_STATE_LOW; + ocpara->ocnidlestate = TIMER_OCN_IDLE_STATE_LOW; +} + +/*! \brief configure TIMER channel output function \param[in] timer_periph: please refer to the following parameters - \param[in] timer_channel: + \param[in] channel: + only one parameter can be selected which is shown as below: \arg TIMER_CH_0: TIMER channel 0(TIMERx(x=0..4,7..13)) \arg TIMER_CH_1: TIMER channel 1(TIMERx(x=0..4,7,8,11)) \arg TIMER_CH_2: TIMER channel 2(TIMERx(x=0..4,7)) \arg TIMER_CH_3: TIMER channel 3(TIMERx(x=0..4,7)) - \param[in] timer_ocpara: TIMER channeln output parameter struct + \param[in] ocpara: TIMER channeln output parameter struct outputstate: TIMER_CCX_ENABLE,TIMER_CCX_DISABLE outputnstate: TIMER_CCXN_ENABLE,TIMER_CCXN_DISABLE ocpolarity: TIMER_OC_POLARITY_HIGH,TIMER_OC_POLARITY_LOW @@ -751,120 +851,120 @@ void timer_channel_control_shadow_update_config(uint32_t timer_periph,uint8_t ti \param[out] none \retval none */ -void timer_channel_output_config(uint32_t timer_periph,uint16_t timer_channel,timer_oc_parameter_struct* timer_ocpara) +void timer_channel_output_config(uint32_t timer_periph, uint16_t channel, timer_oc_parameter_struct* ocpara) { - switch(timer_channel){ + switch(channel){ /* configure TIMER_CH_0 */ case TIMER_CH_0: /* reset the CH0EN bit */ TIMER_CHCTL2(timer_periph) &= (~(uint32_t)TIMER_CHCTL2_CH0EN); + TIMER_CHCTL0(timer_periph) &= ~(uint32_t)TIMER_CHCTL0_CH0MS; /* set the CH0EN bit */ - TIMER_CHCTL2(timer_periph) |= (uint32_t)timer_ocpara->outputstate; + TIMER_CHCTL2(timer_periph) |= (uint32_t)ocpara->outputstate; /* reset the CH0P bit */ TIMER_CHCTL2(timer_periph) &= (~(uint32_t)TIMER_CHCTL2_CH0P); /* set the CH0P bit */ - TIMER_CHCTL2(timer_periph) |= (uint32_t)timer_ocpara->ocpolarity; + TIMER_CHCTL2(timer_periph) |= (uint32_t)ocpara->ocpolarity; if((TIMER0 == timer_periph) || (TIMER7 == timer_periph)){ /* reset the CH0NEN bit */ TIMER_CHCTL2(timer_periph) &= (~(uint32_t)TIMER_CHCTL2_CH0NEN); /* set the CH0NEN bit */ - TIMER_CHCTL2(timer_periph) |= (uint32_t)timer_ocpara->outputnstate; + TIMER_CHCTL2(timer_periph) |= (uint32_t)ocpara->outputnstate; /* reset the CH0NP bit */ TIMER_CHCTL2(timer_periph) &= (~(uint32_t)TIMER_CHCTL2_CH0NP); /* set the CH0NP bit */ - TIMER_CHCTL2(timer_periph) |= (uint32_t)timer_ocpara->ocnpolarity; + TIMER_CHCTL2(timer_periph) |= (uint32_t)ocpara->ocnpolarity; /* reset the ISO0 bit */ TIMER_CTL1(timer_periph) &= (~(uint32_t)TIMER_CTL1_ISO0); /* set the ISO0 bit */ - TIMER_CTL1(timer_periph) |= (uint32_t)timer_ocpara->ocidlestate; + TIMER_CTL1(timer_periph) |= (uint32_t)ocpara->ocidlestate; /* reset the ISO0N bit */ TIMER_CTL1(timer_periph) &= (~(uint32_t)TIMER_CTL1_ISO0N); /* set the ISO0N bit */ - TIMER_CTL1(timer_periph) |= (uint32_t)timer_ocpara->ocnidlestate; + TIMER_CTL1(timer_periph) |= (uint32_t)ocpara->ocnidlestate; } - TIMER_CHCTL0(timer_periph) &= ~(uint32_t)TIMER_CHCTL0_CH0MS; break; /* configure TIMER_CH_1 */ case TIMER_CH_1: /* reset the CH1EN bit */ TIMER_CHCTL2(timer_periph) &= (~(uint32_t)TIMER_CHCTL2_CH1EN); + TIMER_CHCTL0(timer_periph) &= ~(uint32_t)TIMER_CHCTL0_CH1MS; /* set the CH1EN bit */ - TIMER_CHCTL2(timer_periph) |= (uint32_t)(timer_ocpara->outputstate<< 4U); + TIMER_CHCTL2(timer_periph) |= (uint32_t)((uint32_t)ocpara->outputstate << 4U); /* reset the CH1P bit */ TIMER_CHCTL2(timer_periph) &= (~(uint32_t)TIMER_CHCTL2_CH1P); /* set the CH1P bit */ - TIMER_CHCTL2(timer_periph) |= (uint32_t)((uint32_t)(timer_ocpara->ocpolarity)<< 4U); + TIMER_CHCTL2(timer_periph) |= (uint32_t)((uint32_t)(ocpara->ocpolarity) << 4U); if((TIMER0 == timer_periph) || (TIMER7 == timer_periph)){ /* reset the CH1NEN bit */ TIMER_CHCTL2(timer_periph) &= (~(uint32_t)TIMER_CHCTL2_CH1NEN); /* set the CH1NEN bit */ - TIMER_CHCTL2(timer_periph) |= (uint32_t)((uint32_t)(timer_ocpara->outputnstate)<< 4U); + TIMER_CHCTL2(timer_periph) |= (uint32_t)((uint32_t)(ocpara->outputnstate) << 4U); /* reset the CH1NP bit */ TIMER_CHCTL2(timer_periph) &= (~(uint32_t)TIMER_CHCTL2_CH1NP); /* set the CH1NP bit */ - TIMER_CHCTL2(timer_periph) |= (uint32_t)((uint32_t)(timer_ocpara->ocnpolarity)<< 4U); + TIMER_CHCTL2(timer_periph) |= (uint32_t)((uint32_t)(ocpara->ocnpolarity) << 4U); /* reset the ISO1 bit */ TIMER_CTL1(timer_periph) &= (~(uint32_t)TIMER_CTL1_ISO1); /* set the ISO1 bit */ - TIMER_CTL1(timer_periph) |= (uint32_t)((uint32_t)(timer_ocpara->ocidlestate)<< 2U); + TIMER_CTL1(timer_periph) |= (uint32_t)((uint32_t)(ocpara->ocidlestate) << 2U); /* reset the ISO1N bit */ TIMER_CTL1(timer_periph) &= (~(uint32_t)TIMER_CTL1_ISO1N); /* set the ISO1N bit */ - TIMER_CTL1(timer_periph) |= (uint32_t)((uint32_t)(timer_ocpara->ocnidlestate)<< 2U); + TIMER_CTL1(timer_periph) |= (uint32_t)((uint32_t)(ocpara->ocnidlestate) << 2U); } - TIMER_CHCTL0(timer_periph) &= ~(uint32_t)TIMER_CHCTL0_CH1MS; break; /* configure TIMER_CH_2 */ case TIMER_CH_2: /* reset the CH2EN bit */ TIMER_CHCTL2(timer_periph) &= (~(uint32_t)TIMER_CHCTL2_CH2EN); + TIMER_CHCTL1(timer_periph) &= ~(uint32_t)TIMER_CHCTL1_CH2MS; /* set the CH2EN bit */ - TIMER_CHCTL2(timer_periph) |= (uint32_t)(timer_ocpara->outputstate<< 8U); + TIMER_CHCTL2(timer_periph) |= (uint32_t)((uint32_t)ocpara->outputstate << 8U); /* reset the CH2P bit */ TIMER_CHCTL2(timer_periph) &= (~(uint32_t)TIMER_CHCTL2_CH2P); /* set the CH2P bit */ - TIMER_CHCTL2(timer_periph) |= (uint32_t)((uint32_t)(timer_ocpara->ocpolarity)<< 8U); + TIMER_CHCTL2(timer_periph) |= (uint32_t)((uint32_t)(ocpara->ocpolarity) << 8U); if((TIMER0 == timer_periph) || (TIMER7 == timer_periph)){ /* reset the CH2NEN bit */ TIMER_CHCTL2(timer_periph) &= (~(uint32_t)TIMER_CHCTL2_CH2NEN); /* set the CH2NEN bit */ - TIMER_CHCTL2(timer_periph) |= (uint32_t)((uint32_t)(timer_ocpara->outputnstate)<< 8U); + TIMER_CHCTL2(timer_periph) |= (uint32_t)((uint32_t)(ocpara->outputnstate) << 8U); /* reset the CH2NP bit */ TIMER_CHCTL2(timer_periph) &= (~(uint32_t)TIMER_CHCTL2_CH2NP); /* set the CH2NP bit */ - TIMER_CHCTL2(timer_periph) |= (uint32_t)((uint32_t)(timer_ocpara->ocnpolarity)<< 8U); + TIMER_CHCTL2(timer_periph) |= (uint32_t)((uint32_t)(ocpara->ocnpolarity) << 8U); /* reset the ISO2 bit */ TIMER_CTL1(timer_periph) &= (~(uint32_t)TIMER_CTL1_ISO2); /* set the ISO2 bit */ - TIMER_CTL1(timer_periph) |= (uint32_t)((uint32_t)(timer_ocpara->ocidlestate)<< 4U); + TIMER_CTL1(timer_periph) |= (uint32_t)((uint32_t)(ocpara->ocidlestate) << 4U); /* reset the ISO2N bit */ TIMER_CTL1(timer_periph) &= (~(uint32_t)TIMER_CTL1_ISO2N); /* set the ISO2N bit */ - TIMER_CTL1(timer_periph) |= (uint32_t)((uint32_t)(timer_ocpara->ocnidlestate)<< 4U); + TIMER_CTL1(timer_periph) |= (uint32_t)((uint32_t)(ocpara->ocnidlestate) << 4U); } - TIMER_CHCTL1(timer_periph) &= ~(uint32_t)TIMER_CHCTL1_CH2MS; break; /* configure TIMER_CH_3 */ case TIMER_CH_3: /* reset the CH3EN bit */ TIMER_CHCTL2(timer_periph) &=(~(uint32_t)TIMER_CHCTL2_CH3EN); + TIMER_CHCTL1(timer_periph) &= ~(uint32_t)TIMER_CHCTL1_CH3MS; /* set the CH3EN bit */ - TIMER_CHCTL2(timer_periph) |= (uint32_t)(timer_ocpara->outputstate<< 12U); + TIMER_CHCTL2(timer_periph) |= (uint32_t)((uint32_t)ocpara->outputstate << 12U); /* reset the CH3P bit */ TIMER_CHCTL2(timer_periph) &= (~(uint32_t)TIMER_CHCTL2_CH3P); /* set the CH3P bit */ - TIMER_CHCTL2(timer_periph) |= (uint32_t)((uint32_t)(timer_ocpara->ocpolarity)<< 12U); + TIMER_CHCTL2(timer_periph) |= (uint32_t)((uint32_t)(ocpara->ocpolarity) << 12U); if((TIMER0 == timer_periph) || (TIMER7 == timer_periph)){ /* reset the ISO3 bit */ TIMER_CTL1(timer_periph) &= (~(uint32_t)TIMER_CTL1_ISO3); /* set the ISO3 bit */ - TIMER_CTL1(timer_periph) |= (uint32_t)((uint32_t)(timer_ocpara->ocidlestate)<< 6U); + TIMER_CTL1(timer_periph) |= (uint32_t)((uint32_t)(ocpara->ocidlestate) << 6U); } - TIMER_CHCTL1(timer_periph) &= ~(uint32_t)TIMER_CHCTL1_CH3MS; break; default: break; @@ -874,12 +974,14 @@ void timer_channel_output_config(uint32_t timer_periph,uint16_t timer_channel,ti /*! \brief configure TIMER channel output compare mode \param[in] timer_periph: please refer to the following parameters - \param[in] timer_channel: + \param[in] channel: + only one parameter can be selected which is shown as below: \arg TIMER_CH_0: TIMER channel0(TIMERx(x=0..4,7..13)) \arg TIMER_CH_1: TIMER channel1(TIMERx(x=0..4,7,8,11)) \arg TIMER_CH_2: TIMER channel2(TIMERx(x=0..4,7)) \arg TIMER_CH_3: TIMER channel3(TIMERx(x=0..4,7)) - \param[in] timer_ocmode: channel output compare mode + \param[in] ocmode: channel output compare mode + only one parameter can be selected which is shown as below: \arg TIMER_OC_MODE_TIMING: timing mode \arg TIMER_OC_MODE_ACTIVE: active mode \arg TIMER_OC_MODE_INACTIVE: inactive mode @@ -891,28 +993,28 @@ void timer_channel_output_config(uint32_t timer_periph,uint16_t timer_channel,ti \param[out] none \retval none */ -void timer_channel_output_mode_config(uint32_t timer_periph,uint16_t timer_channel,uint16_t timer_ocmode) +void timer_channel_output_mode_config(uint32_t timer_periph, uint16_t channel, uint16_t ocmode) { - switch(timer_channel){ + switch(channel){ /* configure TIMER_CH_0 */ case TIMER_CH_0: TIMER_CHCTL0(timer_periph) &= (~(uint32_t)TIMER_CHCTL0_CH0COMCTL); - TIMER_CHCTL0(timer_periph) |= (uint32_t)timer_ocmode; + TIMER_CHCTL0(timer_periph) |= (uint32_t)ocmode; break; /* configure TIMER_CH_1 */ case TIMER_CH_1: TIMER_CHCTL0(timer_periph) &= (~(uint32_t)TIMER_CHCTL0_CH1COMCTL); - TIMER_CHCTL0(timer_periph) |= (uint32_t)((uint32_t)(timer_ocmode)<< 8U); + TIMER_CHCTL0(timer_periph) |= (uint32_t)((uint32_t)(ocmode) << 8U); break; /* configure TIMER_CH_2 */ case TIMER_CH_2: TIMER_CHCTL1(timer_periph) &= (~(uint32_t)TIMER_CHCTL1_CH2COMCTL); - TIMER_CHCTL1(timer_periph) |= (uint32_t)timer_ocmode; + TIMER_CHCTL1(timer_periph) |= (uint32_t)ocmode; break; /* configure TIMER_CH_3 */ case TIMER_CH_3: TIMER_CHCTL1(timer_periph) &= (~(uint32_t)TIMER_CHCTL1_CH3COMCTL); - TIMER_CHCTL1(timer_periph) |= (uint32_t)((uint32_t)(timer_ocmode)<< 8U); + TIMER_CHCTL1(timer_periph) |= (uint32_t)((uint32_t)(ocmode) << 8U); break; default: break; @@ -922,29 +1024,34 @@ void timer_channel_output_mode_config(uint32_t timer_periph,uint16_t timer_chann /*! \brief configure TIMER channel output pulse value \param[in] timer_periph: please refer to the following parameters - \param[in] timer_channel: + \param[in] channel: + only one parameter can be selected which is shown as below: \arg TIMER_CH_0: TIMER channel0(TIMERx(x=0..4,7..13)) \arg TIMER_CH_1: TIMER channel1(TIMERx(x=0..4,7,8,11)) \arg TIMER_CH_2: TIMER channel2(TIMERx(x=0..4,7)) \arg TIMER_CH_3: TIMER channel3(TIMERx(x=0..4,7)) - \param[in] timer_pluse: channel output pulse value + \param[in] pulse: channel output pulse value,0~65535 \param[out] none \retval none */ -void timer_channel_output_pulse_value_config(uint32_t timer_periph,uint16_t timer_channel,uint32_t timer_pluse) +void timer_channel_output_pulse_value_config(uint32_t timer_periph, uint16_t channel, uint32_t pulse) { - switch(timer_channel){ + switch(channel){ + /* configure TIMER_CH_0 */ case TIMER_CH_0: - TIMER_CH0CV(timer_periph) = (uint32_t)timer_pluse; + TIMER_CH0CV(timer_periph) = (uint32_t)pulse; break; + /* configure TIMER_CH_1 */ case TIMER_CH_1: - TIMER_CH1CV(timer_periph) = (uint32_t)timer_pluse; + TIMER_CH1CV(timer_periph) = (uint32_t)pulse; break; + /* configure TIMER_CH_2 */ case TIMER_CH_2: - TIMER_CH2CV(timer_periph) = (uint32_t)timer_pluse; + TIMER_CH2CV(timer_periph) = (uint32_t)pulse; break; + /* configure TIMER_CH_3 */ case TIMER_CH_3: - TIMER_CH3CV(timer_periph) = (uint32_t)timer_pluse; + TIMER_CH3CV(timer_periph) = (uint32_t)pulse; break; default: break; @@ -954,39 +1061,41 @@ void timer_channel_output_pulse_value_config(uint32_t timer_periph,uint16_t time /*! \brief configure TIMER channel output shadow function \param[in] timer_periph: please refer to the following parameters - \param[in] timer_channel: + \param[in] channel: + only one parameter can be selected which is shown as below: \arg TIMER_CH_0: TIMER channel0(TIMERx(x=0..4,7..13)) \arg TIMER_CH_1: TIMER channel1(TIMERx(x=0..4,7,8,11)) \arg TIMER_CH_2: TIMER channel2(TIMERx(x=0..4,7)) \arg TIMER_CH_3: TIMER channel3(TIMERx(x=0..4,7)) - \param[in] timer_ocshadow: channel output shadow state + \param[in] ocshadow: channel output shadow state + only one parameter can be selected which is shown as below: \arg TIMER_OC_SHADOW_ENABLE: channel output shadow state enable \arg TIMER_OC_SHADOW_DISABLE: channel output shadow state disable \param[out] none \retval none */ -void timer_channel_output_shadow_config(uint32_t timer_periph,uint16_t timer_channel,uint16_t timer_ocshadow) +void timer_channel_output_shadow_config(uint32_t timer_periph, uint16_t channel, uint16_t ocshadow) { - switch(timer_channel){ + switch(channel){ /* configure TIMER_CH_0 */ case TIMER_CH_0: TIMER_CHCTL0(timer_periph) &= (~(uint32_t)TIMER_CHCTL0_CH0COMSEN); - TIMER_CHCTL0(timer_periph) |= (uint32_t)timer_ocshadow; + TIMER_CHCTL0(timer_periph) |= (uint32_t)ocshadow; break; /* configure TIMER_CH_1 */ case TIMER_CH_1: TIMER_CHCTL0(timer_periph) &= (~(uint32_t)TIMER_CHCTL0_CH1COMSEN); - TIMER_CHCTL0(timer_periph) |= (uint32_t)((uint32_t)(timer_ocshadow) << 8U); + TIMER_CHCTL0(timer_periph) |= (uint32_t)((uint32_t)(ocshadow) << 8U); break; /* configure TIMER_CH_2 */ case TIMER_CH_2: TIMER_CHCTL1(timer_periph) &= (~(uint32_t)TIMER_CHCTL1_CH2COMSEN); - TIMER_CHCTL1(timer_periph) |= (uint32_t)timer_ocshadow; + TIMER_CHCTL1(timer_periph) |= (uint32_t)ocshadow; break; /* configure TIMER_CH_3 */ case TIMER_CH_3: TIMER_CHCTL1(timer_periph) &= (~(uint32_t)TIMER_CHCTL1_CH3COMSEN); - TIMER_CHCTL1(timer_periph) |= (uint32_t)((uint32_t)(timer_ocshadow) << 8U); + TIMER_CHCTL1(timer_periph) |= (uint32_t)((uint32_t)(ocshadow) << 8U); break; default: break; @@ -996,39 +1105,41 @@ void timer_channel_output_shadow_config(uint32_t timer_periph,uint16_t timer_cha /*! \brief configure TIMER channel output fast function \param[in] timer_periph: please refer to the following parameters - \param[in] timer_channel: + \param[in] channel: + only one parameter can be selected which is shown as below: \arg TIMER_CH_0: TIMER channel0(TIMERx(x=0..4,7..13)) \arg TIMER_CH_1: TIMER channel1(TIMERx(x=0..4,7,8,11)) \arg TIMER_CH_2: TIMER channel2(TIMERx(x=0..4,7)) \arg TIMER_CH_3: TIMER channel3(TIMERx(x=0..4,7)) - \param[in] timer_ocfast: channel output fast function + \param[in] ocfast: channel output fast function + only one parameter can be selected which is shown as below: \arg TIMER_OC_FAST_ENABLE: channel output fast function enable \arg TIMER_OC_FAST_DISABLE: channel output fast function disable \param[out] none \retval none */ -void timer_channel_output_fast_config(uint32_t timer_periph,uint16_t timer_channel,uint16_t timer_ocfast) +void timer_channel_output_fast_config(uint32_t timer_periph, uint16_t channel, uint16_t ocfast) { - switch(timer_channel){ + switch(channel){ /* configure TIMER_CH_0 */ case TIMER_CH_0: TIMER_CHCTL0(timer_periph) &= (~(uint32_t)TIMER_CHCTL0_CH0COMFEN); - TIMER_CHCTL0(timer_periph) |= (uint32_t)timer_ocfast; + TIMER_CHCTL0(timer_periph) |= (uint32_t)ocfast; break; /* configure TIMER_CH_1 */ case TIMER_CH_1: TIMER_CHCTL0(timer_periph) &= (~(uint32_t)TIMER_CHCTL0_CH1COMFEN); - TIMER_CHCTL0(timer_periph) |= (uint32_t)((uint32_t)timer_ocfast << 8U); + TIMER_CHCTL0(timer_periph) |= (uint32_t)((uint32_t)ocfast << 8U); break; /* configure TIMER_CH_2 */ case TIMER_CH_2: TIMER_CHCTL1(timer_periph) &= (~(uint32_t)TIMER_CHCTL1_CH2COMFEN); - TIMER_CHCTL1(timer_periph) |= (uint32_t)timer_ocfast; + TIMER_CHCTL1(timer_periph) |= (uint32_t)ocfast; break; /* configure TIMER_CH_3 */ case TIMER_CH_3: TIMER_CHCTL1(timer_periph) &= (~(uint32_t)TIMER_CHCTL1_CH3COMFEN); - TIMER_CHCTL1(timer_periph) |= (uint32_t)((uint32_t)timer_ocfast << 8U); + TIMER_CHCTL1(timer_periph) |= (uint32_t)((uint32_t)ocfast << 8U); break; default: break; @@ -1037,40 +1148,42 @@ void timer_channel_output_fast_config(uint32_t timer_periph,uint16_t timer_chann /*! \brief configure TIMER channel output clear function - \param[in] timer_periph: TIMERx(x=0..4,7) - \param[in] timer_channel: - \arg TIMER_CH_0: TIMER channel0 - \arg TIMER_CH_1: TIMER channel1 - \arg TIMER_CH_2: TIMER channel2 - \arg TIMER_CH_3: TIMER channel3 - \param[in] timer_occlear: channel output clear function + \param[in] timer_periph: please refer to the following parameters + \param[in] channel: + only one parameter can be selected which is shown as below: + \arg TIMER_CH_0: TIMER channel0(TIMERx(x=0..4,7)) + \arg TIMER_CH_1: TIMER channel1(TIMERx(x=0..4,7)) + \arg TIMER_CH_2: TIMER channel2(TIMERx(x=0..4,7)) + \arg TIMER_CH_3: TIMER channel3(TIMERx(x=0..4,7)) + \param[in] occlear: channel output clear function + only one parameter can be selected which is shown as below: \arg TIMER_OC_CLEAR_ENABLE: channel output clear function enable \arg TIMER_OC_CLEAR_DISABLE: channel output clear function disable \param[out] none \retval none */ -void timer_channel_output_clear_config(uint32_t timer_periph,uint16_t timer_channel,uint16_t timer_occlear) +void timer_channel_output_clear_config(uint32_t timer_periph, uint16_t channel, uint16_t occlear) { - switch(timer_channel){ + switch(channel){ /* configure TIMER_CH_0 */ case TIMER_CH_0: TIMER_CHCTL0(timer_periph) &= (~(uint32_t)TIMER_CHCTL0_CH0COMCEN); - TIMER_CHCTL0(timer_periph) |= (uint32_t)timer_occlear; + TIMER_CHCTL0(timer_periph) |= (uint32_t)occlear; break; /* configure TIMER_CH_1 */ case TIMER_CH_1: TIMER_CHCTL0(timer_periph) &= (~(uint32_t)TIMER_CHCTL0_CH1COMCEN); - TIMER_CHCTL0(timer_periph) |= (uint32_t)((uint32_t)timer_occlear << 8U); + TIMER_CHCTL0(timer_periph) |= (uint32_t)((uint32_t)occlear << 8U); break; /* configure TIMER_CH_2 */ case TIMER_CH_2: TIMER_CHCTL1(timer_periph) &= (~(uint32_t)TIMER_CHCTL1_CH2COMCEN); - TIMER_CHCTL1(timer_periph) |= (uint32_t)timer_occlear; + TIMER_CHCTL1(timer_periph) |= (uint32_t)occlear; break; /* configure TIMER_CH_3 */ case TIMER_CH_3: TIMER_CHCTL1(timer_periph) &= (~(uint32_t)TIMER_CHCTL1_CH3COMCEN); - TIMER_CHCTL1(timer_periph) |= (uint32_t)((uint32_t)timer_occlear << 8U); + TIMER_CHCTL1(timer_periph) |= (uint32_t)((uint32_t)occlear << 8U); break; default: break; @@ -1078,41 +1191,43 @@ void timer_channel_output_clear_config(uint32_t timer_periph,uint16_t timer_chan } /*! - \brief configure TIMER channel output polarity + \brief configure TIMER channel output polarity \param[in] timer_periph: please refer to the following parameters - \param[in] timer_channel: + \param[in] channel: + only one parameter can be selected which is shown as below: \arg TIMER_CH_0: TIMER channel0(TIMERx(x=0..4,7..13)) \arg TIMER_CH_1: TIMER channel1(TIMERx(x=0..4,7,8,11)) \arg TIMER_CH_2: TIMER channel2(TIMERx(x=0..4,7)) \arg TIMER_CH_3: TIMER channel3(TIMERx(x=0..4,7)) - \param[in] timer_ocpolarity: channel output polarity + \param[in] ocpolarity: channel output polarity + only one parameter can be selected which is shown as below: \arg TIMER_OC_POLARITY_HIGH: channel output polarity is high \arg TIMER_OC_POLARITY_LOW: channel output polarity is low \param[out] none \retval none */ -void timer_channel_output_polarity_config(uint32_t timer_periph,uint16_t timer_channel,uint16_t timer_ocpolarity) +void timer_channel_output_polarity_config(uint32_t timer_periph, uint16_t channel, uint16_t ocpolarity) { - switch(timer_channel){ + switch(channel){ /* configure TIMER_CH_0 */ case TIMER_CH_0: TIMER_CHCTL2(timer_periph) &= (~(uint32_t)TIMER_CHCTL2_CH0P); - TIMER_CHCTL2(timer_periph) |= (uint32_t)timer_ocpolarity; + TIMER_CHCTL2(timer_periph) |= (uint32_t)ocpolarity; break; /* configure TIMER_CH_1 */ case TIMER_CH_1: TIMER_CHCTL2(timer_periph) &= (~(uint32_t)TIMER_CHCTL2_CH1P); - TIMER_CHCTL2(timer_periph) |= (uint32_t)((uint32_t)timer_ocpolarity << 4U); + TIMER_CHCTL2(timer_periph) |= (uint32_t)((uint32_t)ocpolarity << 4U); break; /* configure TIMER_CH_2 */ case TIMER_CH_2: TIMER_CHCTL2(timer_periph) &= (~(uint32_t)TIMER_CHCTL2_CH2P); - TIMER_CHCTL2(timer_periph) |= (uint32_t)((uint32_t)timer_ocpolarity << 8U); + TIMER_CHCTL2(timer_periph) |= (uint32_t)((uint32_t)ocpolarity << 8U); break; /* configure TIMER_CH_3 */ case TIMER_CH_3: TIMER_CHCTL2(timer_periph) &= (~(uint32_t)TIMER_CHCTL2_CH3P); - TIMER_CHCTL2(timer_periph) |= (uint32_t)((uint32_t)timer_ocpolarity << 12U); + TIMER_CHCTL2(timer_periph) |= (uint32_t)((uint32_t)ocpolarity << 12U); break; default: break; @@ -1120,35 +1235,37 @@ void timer_channel_output_polarity_config(uint32_t timer_periph,uint16_t timer_c } /*! - \brief configure TIMER channel complementary output polarity - \param[in] timer_periph: TIMERx(x=0,7) - \param[in] timer_channel: + \brief configure TIMER channel complementary output polarity + \param[in] timer_periph: please refer to the following parameters + \param[in] channel: + only one parameter can be selected which is shown as below: \arg TIMER_CH_0: TIMER channel0(TIMERx(x=0..4,7..13)) \arg TIMER_CH_1: TIMER channel1(TIMERx(x=0..4,7,8,11)) \arg TIMER_CH_2: TIMER channel2(TIMERx(x=0..4,7)) - \param[in] timer_ocnpolarity: channel complementary output polarity + \param[in] ocnpolarity: channel complementary output polarity + only one parameter can be selected which is shown as below: \arg TIMER_OCN_POLARITY_HIGH: channel complementary output polarity is high \arg TIMER_OCN_POLARITY_LOW: channel complementary output polarity is low \param[out] none \retval none */ -void timer_channel_complementary_output_polarity_config(uint32_t timer_periph,uint16_t timer_channel,uint16_t timer_ocnpolarity) +void timer_channel_complementary_output_polarity_config(uint32_t timer_periph, uint16_t channel, uint16_t ocnpolarity) { - switch(timer_channel){ + switch(channel){ /* configure TIMER_CH_0 */ case TIMER_CH_0: TIMER_CHCTL2(timer_periph) &= (~(uint32_t)TIMER_CHCTL2_CH0NP); - TIMER_CHCTL2(timer_periph) |= (uint32_t)timer_ocnpolarity; + TIMER_CHCTL2(timer_periph) |= (uint32_t)ocnpolarity; break; /* configure TIMER_CH_1 */ case TIMER_CH_1: TIMER_CHCTL2(timer_periph) &= (~(uint32_t)TIMER_CHCTL2_CH1NP); - TIMER_CHCTL2(timer_periph) |= (uint32_t)((uint32_t)timer_ocnpolarity << 4U); + TIMER_CHCTL2(timer_periph) |= (uint32_t)((uint32_t)ocnpolarity << 4U); break; /* configure TIMER_CH_2 */ case TIMER_CH_2: TIMER_CHCTL2(timer_periph) &= (~(uint32_t)TIMER_CHCTL2_CH2NP); - TIMER_CHCTL2(timer_periph) |= (uint32_t)((uint32_t)timer_ocnpolarity << 8U); + TIMER_CHCTL2(timer_periph) |= (uint32_t)((uint32_t)ocnpolarity << 8U); break; default: break; @@ -1158,39 +1275,41 @@ void timer_channel_complementary_output_polarity_config(uint32_t timer_periph,ui /*! \brief configure TIMER channel enable state \param[in] timer_periph: please refer to the following parameters - \param[in] timer_channel: + \param[in] channel: + only one parameter can be selected which is shown as below: \arg TIMER_CH_0: TIMER channel0(TIMERx(x=0..4,7..13)) \arg TIMER_CH_1: TIMER channel1(TIMERx(x=0..4,7,8,11)) \arg TIMER_CH_2: TIMER channel2(TIMERx(x=0..4,7)) \arg TIMER_CH_3: TIMER channel3(TIMERx(x=0..4,7)) - \param[in] timer_state: TIMER channel enable state - \arg TIMER_CCX_ENABLE: channel enable - \arg TIMER_CCX_DISABLE: channel disable + \param[in] state: TIMER channel enable state + only one parameter can be selected which is shown as below: + \arg TIMER_CCX_ENABLE: channel enable + \arg TIMER_CCX_DISABLE: channel disable \param[out] none \retval none */ -void timer_channel_output_state_config(uint32_t timer_periph,uint16_t timer_channel,uint32_t timer_state) +void timer_channel_output_state_config(uint32_t timer_periph, uint16_t channel, uint32_t state) { - switch(timer_channel){ + switch(channel){ /* configure TIMER_CH_0 */ case TIMER_CH_0: TIMER_CHCTL2(timer_periph) &= (~(uint32_t)TIMER_CHCTL2_CH0EN); - TIMER_CHCTL2(timer_periph) |= (uint32_t)timer_state; + TIMER_CHCTL2(timer_periph) |= (uint32_t)state; break; /* configure TIMER_CH_1 */ case TIMER_CH_1: TIMER_CHCTL2(timer_periph) &= (~(uint32_t)TIMER_CHCTL2_CH1EN); - TIMER_CHCTL2(timer_periph) |= (uint32_t)((uint32_t)timer_state << 4U); + TIMER_CHCTL2(timer_periph) |= (uint32_t)((uint32_t)state << 4U); break; /* configure TIMER_CH_2 */ case TIMER_CH_2: TIMER_CHCTL2(timer_periph) &= (~(uint32_t)TIMER_CHCTL2_CH2EN); - TIMER_CHCTL2(timer_periph) |= (uint32_t)((uint32_t)timer_state << 8U); + TIMER_CHCTL2(timer_periph) |= (uint32_t)((uint32_t)state << 8U); break; /* configure TIMER_CH_3 */ case TIMER_CH_3: TIMER_CHCTL2(timer_periph) &= (~(uint32_t)TIMER_CHCTL2_CH3EN); - TIMER_CHCTL2(timer_periph) |= (uint32_t)((uint32_t)timer_state << 12U); + TIMER_CHCTL2(timer_periph) |= (uint32_t)((uint32_t)state << 12U); break; default: break; @@ -1200,33 +1319,35 @@ void timer_channel_output_state_config(uint32_t timer_periph,uint16_t timer_chan /*! \brief configure TIMER channel complementary output enable state \param[in] timer_periph: TIMERx(x=0,7) - \param[in] timer_channel: + \param[in] channel: + only one parameter can be selected which is shown as below: \arg TIMER_CH_0: TIMER channel0 \arg TIMER_CH_1: TIMER channel1 \arg TIMER_CH_2: TIMER channel2 - \param[in] timer_ocnstate: TIMER channel complementary output enable state - \arg TIMER_CCXN_ENABLE: channel complementary enable - \arg TIMER_CCXN_DISABLE: channel complementary disable + \param[in] ocnstate: TIMER channel complementary output enable state + only one parameter can be selected which is shown as below: + \arg TIMER_CCXN_ENABLE: channel complementary enable + \arg TIMER_CCXN_DISABLE: channel complementary disable \param[out] none \retval none */ -void timer_channel_complementary_output_state_config(uint32_t timer_periph,uint16_t timer_channel,uint16_t timer_ocnstate) +void timer_channel_complementary_output_state_config(uint32_t timer_periph, uint16_t channel, uint16_t ocnstate) { - switch(timer_channel){ + switch(channel){ /* configure TIMER_CH_0 */ case TIMER_CH_0: TIMER_CHCTL2(timer_periph) &= (~(uint32_t)TIMER_CHCTL2_CH0NEN); - TIMER_CHCTL2(timer_periph) |= (uint32_t)timer_ocnstate; + TIMER_CHCTL2(timer_periph) |= (uint32_t)ocnstate; break; /* configure TIMER_CH_1 */ case TIMER_CH_1: TIMER_CHCTL2(timer_periph) &= (~(uint32_t)TIMER_CHCTL2_CH1NEN); - TIMER_CHCTL2(timer_periph) |= (uint32_t)((uint32_t)timer_ocnstate << 4U); + TIMER_CHCTL2(timer_periph) |= (uint32_t)((uint32_t)ocnstate << 4U); break; /* configure TIMER_CH_2 */ case TIMER_CH_2: TIMER_CHCTL2(timer_periph) &= (~(uint32_t)TIMER_CHCTL2_CH2NEN); - TIMER_CHCTL2(timer_periph) |= (uint32_t)((uint32_t)timer_ocnstate << 8U); + TIMER_CHCTL2(timer_periph) |= (uint32_t)((uint32_t)ocnstate << 8U); break; default: break; @@ -1234,14 +1355,30 @@ void timer_channel_complementary_output_state_config(uint32_t timer_periph,uint1 } /*! - \brief configure TIMER input capture parameter + \brief initialize TIMER channel input parameter struct with a default value + \param[in] icpara: TIMER channel intput parameter struct + \param[out] none + \retval none +*/ +void timer_channel_input_struct_para_init(timer_ic_parameter_struct* icpara) +{ + /* initialize the channel input parameter struct member with the default value */ + icpara->icpolarity = TIMER_IC_POLARITY_RISING; + icpara->icselection = TIMER_IC_SELECTION_DIRECTTI; + icpara->icprescaler = TIMER_IC_PSC_DIV1; + icpara->icfilter = 0U; +} + +/*! + \brief configure TIMER input capture parameter \param[in] timer_periph: please refer to the following parameters - \param[in] timer_channel: + \param[in] channel: + only one parameter can be selected which is shown as below: \arg TIMER_CH_0: TIMER channel0(TIMERx(x=0..4,7..13)) \arg TIMER_CH_1: TIMER channel1(TIMERx(x=0..4,7,8,11)) \arg TIMER_CH_2: TIMER channel2(TIMERx(x=0..4,7)) \arg TIMER_CH_3: TIMER channel3(TIMERx(x=0..4,7)) - \param[in] timer_icpara: TIMER channel intput parameter struct + \param[in] icpara: TIMER channel intput parameter struct icpolarity: TIMER_IC_POLARITY_RISING,TIMER_IC_POLARITY_FALLING,TIMER_IC_POLARITY_BOTH_EDGE icselection: TIMER_IC_SELECTION_DIRECTTI,TIMER_IC_SELECTION_INDIRECTTI,TIMER_IC_SELECTION_ITS icprescaler: TIMER_IC_PSC_DIV1,TIMER_IC_PSC_DIV2,TIMER_IC_PSC_DIV4,TIMER_IC_PSC_DIV8 @@ -1249,9 +1386,9 @@ void timer_channel_complementary_output_state_config(uint32_t timer_periph,uint1 \param[out] none \retval none */ -void timer_input_capture_config(uint32_t timer_periph,uint16_t timer_channel,timer_ic_parameter_struct* timer_icpara) +void timer_input_capture_config(uint32_t timer_periph,uint16_t channel, timer_ic_parameter_struct* icpara) { - switch(timer_channel){ + switch(channel){ /* configure TIMER_CH_0 */ case TIMER_CH_0: /* reset the CH0EN bit */ @@ -1259,18 +1396,18 @@ void timer_input_capture_config(uint32_t timer_periph,uint16_t timer_channel,tim /* reset the CH0P and CH0NP bits */ TIMER_CHCTL2(timer_periph) &= (~(uint32_t)(TIMER_CHCTL2_CH0P | TIMER_CHCTL2_CH0NP)); - TIMER_CHCTL2(timer_periph) |= (uint32_t)(timer_icpara->icpolarity); + TIMER_CHCTL2(timer_periph) |= (uint32_t)(icpara->icpolarity); /* reset the CH0MS bit */ TIMER_CHCTL0(timer_periph) &= (~(uint32_t)TIMER_CHCTL0_CH0MS); - TIMER_CHCTL0(timer_periph) |= (uint32_t)(timer_icpara->icselection); + TIMER_CHCTL0(timer_periph) |= (uint32_t)(icpara->icselection); /* reset the CH0CAPFLT bit */ TIMER_CHCTL0(timer_periph) &= (~(uint32_t)TIMER_CHCTL0_CH0CAPFLT); - TIMER_CHCTL0(timer_periph) |= (uint32_t)((uint32_t)(timer_icpara->icfilter) << 4U); + TIMER_CHCTL0(timer_periph) |= (uint32_t)((uint32_t)(icpara->icfilter) << 4U); /* set the CH0EN bit */ TIMER_CHCTL2(timer_periph) |= (uint32_t)TIMER_CHCTL2_CH0EN; break; - + /* configure TIMER_CH_1 */ case TIMER_CH_1: /* reset the CH1EN bit */ @@ -1278,13 +1415,13 @@ void timer_input_capture_config(uint32_t timer_periph,uint16_t timer_channel,tim /* reset the CH1P and CH1NP bits */ TIMER_CHCTL2(timer_periph) &= (~(uint32_t)(TIMER_CHCTL2_CH1P | TIMER_CHCTL2_CH1NP)); - TIMER_CHCTL2(timer_periph) |= (uint32_t)((uint32_t)(timer_icpara->icpolarity)<< 4U); + TIMER_CHCTL2(timer_periph) |= (uint32_t)((uint32_t)(icpara->icpolarity) << 4U); /* reset the CH1MS bit */ TIMER_CHCTL0(timer_periph) &= (~(uint32_t)TIMER_CHCTL0_CH1MS); - TIMER_CHCTL0(timer_periph) |= (uint32_t)((uint32_t)(timer_icpara->icselection)<< 8U); + TIMER_CHCTL0(timer_periph) |= (uint32_t)((uint32_t)(icpara->icselection) << 8U); /* reset the CH1CAPFLT bit */ TIMER_CHCTL0(timer_periph) &= (~(uint32_t)TIMER_CHCTL0_CH1CAPFLT); - TIMER_CHCTL0(timer_periph) |= (uint32_t)((uint32_t)(timer_icpara->icfilter)<< 12U); + TIMER_CHCTL0(timer_periph) |= (uint32_t)((uint32_t)(icpara->icfilter) << 12U); /* set the CH1EN bit */ TIMER_CHCTL2(timer_periph) |= (uint32_t)TIMER_CHCTL2_CH1EN; @@ -1296,15 +1433,15 @@ void timer_input_capture_config(uint32_t timer_periph,uint16_t timer_channel,tim /* reset the CH2P and CH2NP bits */ TIMER_CHCTL2(timer_periph) &= (~(uint32_t)(TIMER_CHCTL2_CH2P|TIMER_CHCTL2_CH2NP)); - TIMER_CHCTL2(timer_periph) |= (uint32_t)((uint32_t)(timer_icpara->icpolarity)<< 8U); + TIMER_CHCTL2(timer_periph) |= (uint32_t)((uint32_t)(icpara->icpolarity) << 8U); /* reset the CH2MS bit */ TIMER_CHCTL1(timer_periph) &= (~(uint32_t)TIMER_CHCTL1_CH2MS); - TIMER_CHCTL1(timer_periph) |= (uint32_t)((uint32_t)(timer_icpara->icselection)); + TIMER_CHCTL1(timer_periph) |= (uint32_t)((uint32_t)(icpara->icselection)); /* reset the CH2CAPFLT bit */ TIMER_CHCTL1(timer_periph) &= (~(uint32_t)TIMER_CHCTL1_CH2CAPFLT); - TIMER_CHCTL1(timer_periph) |= (uint32_t)((uint32_t)(timer_icpara->icfilter)<< 4U); + TIMER_CHCTL1(timer_periph) |= (uint32_t)((uint32_t)(icpara->icfilter) << 4U); /* set the CH2EN bit */ TIMER_CHCTL2(timer_periph) |= (uint32_t)TIMER_CHCTL2_CH2EN; @@ -1316,15 +1453,15 @@ void timer_input_capture_config(uint32_t timer_periph,uint16_t timer_channel,tim /* reset the CH3P bits */ TIMER_CHCTL2(timer_periph) &= (~(uint32_t)(TIMER_CHCTL2_CH3P)); - TIMER_CHCTL2(timer_periph) |= (uint32_t)((uint32_t)(timer_icpara->icpolarity)<< 12U); + TIMER_CHCTL2(timer_periph) |= (uint32_t)((uint32_t)(icpara->icpolarity) << 12U); /* reset the CH3MS bit */ TIMER_CHCTL1(timer_periph) &= (~(uint32_t)TIMER_CHCTL1_CH3MS); - TIMER_CHCTL1(timer_periph) |= (uint32_t)((uint32_t)(timer_icpara->icselection)<< 8U); + TIMER_CHCTL1(timer_periph) |= (uint32_t)((uint32_t)(icpara->icselection) << 8U); /* reset the CH3CAPFLT bit */ TIMER_CHCTL1(timer_periph) &= (~(uint32_t)TIMER_CHCTL1_CH3CAPFLT); - TIMER_CHCTL1(timer_periph) |= (uint32_t)((uint32_t)(timer_icpara->icfilter)<< 12U); + TIMER_CHCTL1(timer_periph) |= (uint32_t)((uint32_t)(icpara->icfilter) << 12U); /* set the CH3EN bit */ TIMER_CHCTL2(timer_periph) |= (uint32_t)TIMER_CHCTL2_CH3EN; @@ -1333,18 +1470,20 @@ void timer_input_capture_config(uint32_t timer_periph,uint16_t timer_channel,tim break; } /* configure TIMER channel input capture prescaler value */ - timer_channel_input_capture_prescaler_config(timer_periph,timer_channel,(uint16_t)(timer_icpara->icprescaler)); + timer_channel_input_capture_prescaler_config(timer_periph, channel, (uint16_t)(icpara->icprescaler)); } /*! \brief configure TIMER channel input capture prescaler value \param[in] timer_periph: please refer to the following parameters - \param[in] timer_channel: + \param[in] channel: + only one parameter can be selected which is shown as below: \arg TIMER_CH_0: TIMER channel0(TIMERx(x=0..4,7..13)) \arg TIMER_CH_1: TIMER channel1(TIMERx(x=0..4,7,8,11)) \arg TIMER_CH_2: TIMER channel2(TIMERx(x=0..4,7)) \arg TIMER_CH_3: TIMER channel3(TIMERx(x=0..4,7)) - \param[in] timer_prescaler: channel input capture prescaler value + \param[in] prescaler: channel input capture prescaler value + only one parameter can be selected which is shown as below: \arg TIMER_IC_PSC_DIV1: no prescaler \arg TIMER_IC_PSC_DIV2: divided by 2 \arg TIMER_IC_PSC_DIV4: divided by 4 @@ -1352,28 +1491,28 @@ void timer_input_capture_config(uint32_t timer_periph,uint16_t timer_channel,tim \param[out] none \retval none */ -void timer_channel_input_capture_prescaler_config(uint32_t timer_periph,uint16_t timer_channel,uint16_t timer_prescaler) +void timer_channel_input_capture_prescaler_config(uint32_t timer_periph, uint16_t channel, uint16_t prescaler) { - switch(timer_channel){ + switch(channel){ /* configure TIMER_CH_0 */ case TIMER_CH_0: TIMER_CHCTL0(timer_periph) &= (~(uint32_t)TIMER_CHCTL0_CH0CAPPSC); - TIMER_CHCTL0(timer_periph) |= (uint32_t)timer_prescaler; + TIMER_CHCTL0(timer_periph) |= (uint32_t)prescaler; break; /* configure TIMER_CH_1 */ case TIMER_CH_1: TIMER_CHCTL0(timer_periph) &= (~(uint32_t)TIMER_CHCTL0_CH1CAPPSC); - TIMER_CHCTL0(timer_periph) |= ((uint32_t)timer_prescaler << 8U); + TIMER_CHCTL0(timer_periph) |= ((uint32_t)prescaler << 8U); break; /* configure TIMER_CH_2 */ case TIMER_CH_2: TIMER_CHCTL1(timer_periph) &= (~(uint32_t)TIMER_CHCTL1_CH2CAPPSC); - TIMER_CHCTL1(timer_periph) |= (uint32_t)timer_prescaler; + TIMER_CHCTL1(timer_periph) |= (uint32_t)prescaler; break; /* configure TIMER_CH_3 */ case TIMER_CH_3: TIMER_CHCTL1(timer_periph) &= (~(uint32_t)TIMER_CHCTL1_CH3CAPPSC); - TIMER_CHCTL1(timer_periph) |= ((uint32_t)timer_prescaler << 8U); + TIMER_CHCTL1(timer_periph) |= ((uint32_t)prescaler << 8U); break; default: break; @@ -1383,7 +1522,8 @@ void timer_channel_input_capture_prescaler_config(uint32_t timer_periph,uint16_t /*! \brief read TIMER channel capture compare register value \param[in] timer_periph: please refer to the following parameters - \param[in] timer_channel: + \param[in] channel: + only one parameter can be selected which is shown as below: \arg TIMER_CH_0: TIMER channel0(TIMERx(x=0..4,7..13)) \arg TIMER_CH_1: TIMER channel1(TIMERx(x=0..4,7,8,11)) \arg TIMER_CH_2: TIMER channel2(TIMERx(x=0..4,7)) @@ -1391,20 +1531,24 @@ void timer_channel_input_capture_prescaler_config(uint32_t timer_periph,uint16_t \param[out] none \retval channel capture compare register value */ -uint32_t timer_channel_capture_value_register_read(uint32_t timer_periph,uint16_t timer_channel) +uint32_t timer_channel_capture_value_register_read(uint32_t timer_periph, uint16_t channel) { uint32_t count_value = 0U; - switch(timer_channel){ + switch(channel){ + /* read TIMER channel 0 capture compare register value */ case TIMER_CH_0: count_value = TIMER_CH0CV(timer_periph); break; + /* read TIMER channel 1 capture compare register value */ case TIMER_CH_1: count_value = TIMER_CH1CV(timer_periph); break; + /* read TIMER channel 2 capture compare register value */ case TIMER_CH_2: count_value = TIMER_CH2CV(timer_periph); break; + /* read TIMER channel 3 capture compare register value */ case TIMER_CH_3: count_value = TIMER_CH3CV(timer_periph); break; @@ -1415,12 +1559,13 @@ uint32_t timer_channel_capture_value_register_read(uint32_t timer_periph,uint16_ } /*! - \brief configure TIMER input pwm capture function + \brief configure TIMER input pwm capture function \param[in] timer_periph: TIMERx(x=0..4,7,8,11) - \param[in] timer_channel: + \param[in] channel: + only one parameter can be selected which is shown as below: \arg TIMER_CH_0: TIMER channel0 \arg TIMER_CH_1: TIMER channel1 - \param[in] timer_icpwm:TIMER channel intput pwm parameter struct + \param[in] icpwm:TIMER channel intput pwm parameter struct icpolarity: TIMER_IC_POLARITY_RISING,TIMER_IC_POLARITY_FALLING icselection: TIMER_IC_SELECTION_DIRECTTI,TIMER_IC_SELECTION_INDIRECTTI icprescaler: TIMER_IC_PSC_DIV1,TIMER_IC_PSC_DIV2,TIMER_IC_PSC_DIV4,TIMER_IC_PSC_DIV8 @@ -1428,80 +1573,82 @@ uint32_t timer_channel_capture_value_register_read(uint32_t timer_periph,uint16_ \param[out] none \retval none */ -void timer_input_pwm_capture_config(uint32_t timer_periph,uint16_t timer_channel,timer_ic_parameter_struct* timer_icpwm) +void timer_input_pwm_capture_config(uint32_t timer_periph, uint16_t channel, timer_ic_parameter_struct* icpwm) { uint16_t icpolarity = 0x0U; uint16_t icselection = 0x0U; - if(TIMER_IC_POLARITY_RISING == timer_icpwm->icpolarity){ + /* Set channel input polarity */ + if(TIMER_IC_POLARITY_RISING == icpwm->icpolarity){ icpolarity = TIMER_IC_POLARITY_FALLING; }else{ icpolarity = TIMER_IC_POLARITY_RISING; } - if(TIMER_IC_SELECTION_DIRECTTI == timer_icpwm->icselection){ + /* Set channel input mode selection */ + if(TIMER_IC_SELECTION_DIRECTTI == icpwm->icselection){ icselection = TIMER_IC_SELECTION_INDIRECTTI; }else{ icselection = TIMER_IC_SELECTION_DIRECTTI; } - if(TIMER_CH_0 == timer_channel){ + if(TIMER_CH_0 == channel){ /* reset the CH0EN bit */ TIMER_CHCTL2(timer_periph) &= (~(uint32_t)TIMER_CHCTL2_CH0EN); /* reset the CH0P and CH0NP bits */ TIMER_CHCTL2(timer_periph) &= (~(uint32_t)(TIMER_CHCTL2_CH0P|TIMER_CHCTL2_CH0NP)); /* set the CH0P and CH0NP bits */ - TIMER_CHCTL2(timer_periph) |= (uint32_t)(timer_icpwm->icpolarity); + TIMER_CHCTL2(timer_periph) |= (uint32_t)(icpwm->icpolarity); /* reset the CH0MS bit */ TIMER_CHCTL0(timer_periph) &= (~(uint32_t)TIMER_CHCTL0_CH0MS); /* set the CH0MS bit */ - TIMER_CHCTL0(timer_periph) |= (uint32_t)(timer_icpwm->icselection); + TIMER_CHCTL0(timer_periph) |= (uint32_t)(icpwm->icselection); /* reset the CH0CAPFLT bit */ TIMER_CHCTL0(timer_periph) &= (~(uint32_t)TIMER_CHCTL0_CH0CAPFLT); /* set the CH0CAPFLT bit */ - TIMER_CHCTL0(timer_periph) |= ((uint32_t)(timer_icpwm->icfilter) << 4U); + TIMER_CHCTL0(timer_periph) |= ((uint32_t)(icpwm->icfilter) << 4U); /* set the CH0EN bit */ TIMER_CHCTL2(timer_periph) |= (uint32_t)TIMER_CHCTL2_CH0EN; /* configure TIMER channel input capture prescaler value */ - timer_channel_input_capture_prescaler_config(timer_periph,TIMER_CH_0,(uint16_t)(timer_icpwm->icprescaler)); + timer_channel_input_capture_prescaler_config(timer_periph,TIMER_CH_0,(uint16_t)(icpwm->icprescaler)); /* reset the CH1EN bit */ TIMER_CHCTL2(timer_periph) &= (~(uint32_t)TIMER_CHCTL2_CH1EN); /* reset the CH1P and CH1NP bits */ TIMER_CHCTL2(timer_periph) &= (~(uint32_t)(TIMER_CHCTL2_CH1P|TIMER_CHCTL2_CH1NP)); /* set the CH1P and CH1NP bits */ - TIMER_CHCTL2(timer_periph) |= (uint32_t)((uint32_t)icpolarity<< 4U); + TIMER_CHCTL2(timer_periph) |= (uint32_t)((uint32_t)icpolarity << 4U); /* reset the CH1MS bit */ TIMER_CHCTL0(timer_periph) &= (~(uint32_t)TIMER_CHCTL0_CH1MS); /* set the CH1MS bit */ - TIMER_CHCTL0(timer_periph) |= (uint32_t)((uint32_t)icselection<< 8U); + TIMER_CHCTL0(timer_periph) |= (uint32_t)((uint32_t)icselection << 8U); /* reset the CH1CAPFLT bit */ TIMER_CHCTL0(timer_periph) &= (~(uint32_t)TIMER_CHCTL0_CH1CAPFLT); /* set the CH1CAPFLT bit */ - TIMER_CHCTL0(timer_periph) |= (uint32_t)((uint32_t)(timer_icpwm->icfilter)<< 12U); + TIMER_CHCTL0(timer_periph) |= (uint32_t)((uint32_t)(icpwm->icfilter) << 12U); /* set the CH1EN bit */ TIMER_CHCTL2(timer_periph) |= (uint32_t)TIMER_CHCTL2_CH1EN; /* configure TIMER channel input capture prescaler value */ - timer_channel_input_capture_prescaler_config(timer_periph,TIMER_CH_1,(uint16_t)(timer_icpwm->icprescaler)); + timer_channel_input_capture_prescaler_config(timer_periph,TIMER_CH_1,(uint16_t)(icpwm->icprescaler)); }else{ /* reset the CH1EN bit */ TIMER_CHCTL2(timer_periph) &= (~(uint32_t)TIMER_CHCTL2_CH1EN); /* reset the CH1P and CH1NP bits */ TIMER_CHCTL2(timer_periph) &= (~(uint32_t)(TIMER_CHCTL2_CH1P|TIMER_CHCTL2_CH1NP)); /* set the CH1P and CH1NP bits */ - TIMER_CHCTL2(timer_periph) |= (uint32_t)((uint32_t)(timer_icpwm->icpolarity)<< 4U); + TIMER_CHCTL2(timer_periph) |= (uint32_t)((uint32_t)(icpwm->icpolarity) << 4U); /* reset the CH1MS bit */ TIMER_CHCTL0(timer_periph) &= (~(uint32_t)TIMER_CHCTL0_CH1MS); /* set the CH1MS bit */ - TIMER_CHCTL0(timer_periph) |= (uint32_t)((uint32_t)(timer_icpwm->icselection)<< 8U); + TIMER_CHCTL0(timer_periph) |= (uint32_t)((uint32_t)(icpwm->icselection) << 8U); /* reset the CH1CAPFLT bit */ TIMER_CHCTL0(timer_periph) &= (~(uint32_t)TIMER_CHCTL0_CH1CAPFLT); /* set the CH1CAPFLT bit */ - TIMER_CHCTL0(timer_periph) |= (uint32_t)((uint32_t)(timer_icpwm->icfilter)<< 12U); + TIMER_CHCTL0(timer_periph) |= (uint32_t)((uint32_t)(icpwm->icfilter) << 12U); /* set the CH1EN bit */ TIMER_CHCTL2(timer_periph) |= (uint32_t)TIMER_CHCTL2_CH1EN; /* configure TIMER channel input capture prescaler value */ - timer_channel_input_capture_prescaler_config(timer_periph,TIMER_CH_1,(uint16_t)(timer_icpwm->icprescaler)); + timer_channel_input_capture_prescaler_config(timer_periph, TIMER_CH_1, (uint16_t)(icpwm->icprescaler)); /* reset the CH0EN bit */ TIMER_CHCTL2(timer_periph) &= (~(uint32_t)TIMER_CHCTL2_CH0EN); @@ -1516,168 +1663,180 @@ void timer_input_pwm_capture_config(uint32_t timer_periph,uint16_t timer_channel /* reset the CH0CAPFLT bit */ TIMER_CHCTL0(timer_periph) &= (~(uint32_t)TIMER_CHCTL0_CH0CAPFLT); /* set the CH0CAPFLT bit */ - TIMER_CHCTL0(timer_periph) |= ((uint32_t)(timer_icpwm->icfilter) << 4U); + TIMER_CHCTL0(timer_periph) |= ((uint32_t)(icpwm->icfilter) << 4U); /* set the CH0EN bit */ TIMER_CHCTL2(timer_periph) |= (uint32_t)TIMER_CHCTL2_CH0EN; /* configure TIMER channel input capture prescaler value */ - timer_channel_input_capture_prescaler_config(timer_periph,TIMER_CH_0,(uint16_t)(timer_icpwm->icprescaler)); + timer_channel_input_capture_prescaler_config(timer_periph, TIMER_CH_0, (uint16_t)(icpwm->icprescaler)); } } /*! \brief configure TIMER hall sensor mode \param[in] timer_periph: TIMERx(x=0..4,7) - \param[in] timer_hallmode: + \param[in] hallmode: + only one parameter can be selected which is shown as below: \arg TIMER_HALLINTERFACE_ENABLE: TIMER hall sensor mode enable \arg TIMER_HALLINTERFACE_DISABLE: TIMER hall sensor mode disable \param[out] none \retval none */ -void timer_hall_mode_config(uint32_t timer_periph,uint8_t timer_hallmode) +void timer_hall_mode_config(uint32_t timer_periph, uint32_t hallmode) { - if(TIMER_HALLINTERFACE_ENABLE == timer_hallmode){ + if(TIMER_HALLINTERFACE_ENABLE == hallmode){ TIMER_CTL1(timer_periph) |= (uint32_t)TIMER_CTL1_TI0S; - }else if(TIMER_HALLINTERFACE_DISABLE == timer_hallmode){ + }else if(TIMER_HALLINTERFACE_DISABLE == hallmode){ TIMER_CTL1(timer_periph) &= ~(uint32_t)TIMER_CTL1_TI0S; }else{ + /* illegal parameters */ } } /*! - \brief select TIMER input trigger source - \param[in] timer_periph: TIMERx(x=0..4,7,8,11) - \param[in] timer_intrigger: - \arg TIMER_SMCFG_TRGSEL_ITI0: internal trigger 0 - \arg TIMER_SMCFG_TRGSEL_ITI1: internal trigger 1 - \arg TIMER_SMCFG_TRGSEL_ITI2: internal trigger 2 - \arg TIMER_SMCFG_TRGSEL_ITI3: internal trigger 3 - \arg TIMER_SMCFG_TRGSEL_CI0F_ED: TI0 Edge Detector - \arg TIMER_SMCFG_TRGSEL_CI0FE0: filtered TIMER input 0 - \arg TIMER_SMCFG_TRGSEL_CI1FE1: filtered TIMER input 1 - \arg TIMER_SMCFG_TRGSEL_ETIFP: external trigger + \brief select TIMER input trigger source + \param[in] timer_periph: please refer to the following parameters + \param[in] intrigger: + only one parameter can be selected which is shown as below: + \arg TIMER_SMCFG_TRGSEL_ITI0: internal trigger 0(TIMERx(x=0..4,7,8,11)) + \arg TIMER_SMCFG_TRGSEL_ITI1: internal trigger 1(TIMERx(x=0..4,7,8,11)) + \arg TIMER_SMCFG_TRGSEL_ITI2: internal trigger 2(TIMERx(x=0..4,7,8,11)) + \arg TIMER_SMCFG_TRGSEL_ITI3: internal trigger 3(TIMERx(x=0..4,7,8,11)) + \arg TIMER_SMCFG_TRGSEL_CI0F_ED: TI0 edge detector(TIMERx(x=0..4,7,8,11)) + \arg TIMER_SMCFG_TRGSEL_CI0FE0: filtered TIMER input 0(TIMERx(x=0..4,7,8,11)) + \arg TIMER_SMCFG_TRGSEL_CI1FE1: filtered TIMER input 1(TIMERx(x=0..4,7,8,11)) + \arg TIMER_SMCFG_TRGSEL_ETIFP: external trigger(TIMERx(x=0..4,7,8,11)) \param[out] none \retval none */ -void timer_input_trigger_source_select(uint32_t timer_periph,uint32_t timer_intrigger) +void timer_input_trigger_source_select(uint32_t timer_periph, uint32_t intrigger) { TIMER_SMCFG(timer_periph) &= (~(uint32_t)TIMER_SMCFG_TRGS); - TIMER_SMCFG(timer_periph) |= (uint32_t)timer_intrigger; + TIMER_SMCFG(timer_periph) |= (uint32_t)intrigger; } /*! - \brief select TIMER master mode output trigger source + \brief select TIMER master mode output trigger source \param[in] timer_periph: TIMERx(x=0..7) - \param[in] timer_outrigger: - \arg TIMER_TRI_OUT_SRC_RESET: the UPG bit as trigger output - \arg TIMER_TRI_OUT_SRC_ENABLE: the counter enable signal TIMER_CTL0_CEN as trigger output - \arg TIMER_TRI_OUT_SRC_UPDATE: update event as trigger output - \arg TIMER_TRI_OUT_SRC_CC0: a capture or a compare match occurred in channal0 as trigger output TRGO - \arg TIMER_TRI_OUT_SRC_O0CPRE: O0CPRE as trigger output - \arg TIMER_TRI_OUT_SRC_O1CPRE: O1CPRE as trigger output - \arg TIMER_TRI_OUT_SRC_O2CPRE: O2CPRE as trigger output - \arg TIMER_TRI_OUT_SRC_O3CPRE: O3CPRE as trigger output + \param[in] outrigger: + only one parameter can be selected which is shown as below: + \arg TIMER_TRI_OUT_SRC_RESET: the UPG bit as trigger output(TIMERx(x=0..7,9,10,12,13)) + \arg TIMER_TRI_OUT_SRC_ENABLE: the counter enable signal TIMER_CTL0_CEN as trigger output(TIMERx(x=0..7,9,10,12,13)) + \arg TIMER_TRI_OUT_SRC_UPDATE: update event as trigger output(TIMERx(x=0..7,9,10,12,13)) + \arg TIMER_TRI_OUT_SRC_CH0: a capture or a compare match occurred in channal0 as trigger output TRGO(TIMERx(x=0..4,7,9,10,12,13)) + \arg TIMER_TRI_OUT_SRC_O0CPRE: O0CPRE as trigger output(TIMERx(x=0..4,7,9,10,12,13)) + \arg TIMER_TRI_OUT_SRC_O1CPRE: O1CPRE as trigger output(TIMERx(x=0..4,7)) + \arg TIMER_TRI_OUT_SRC_O2CPRE: O2CPRE as trigger output(TIMERx(x=0..4,7)) + \arg TIMER_TRI_OUT_SRC_O3CPRE: O3CPRE as trigger output(TIMERx(x=0..4,7)) \param[out] none \retval none */ -void timer_master_output_trigger_source_select(uint32_t timer_periph,uint32_t timer_outrigger) +void timer_master_output_trigger_source_select(uint32_t timer_periph, uint32_t outrigger) { TIMER_CTL1(timer_periph) &= (~(uint32_t)TIMER_CTL1_MMC); - TIMER_CTL1(timer_periph) |= (uint32_t)timer_outrigger; + TIMER_CTL1(timer_periph) |= (uint32_t)outrigger; } /*! - \brief select TIMER slave mode + \brief select TIMER slave mode \param[in] timer_periph: TIMERx(x=0..4,7,8,11) - \param[in] timer_slavemode: - \arg TIMER_SLAVE_MODE_DISABLE: slave mode disable - \arg TIMER_ENCODER_MODE0: encoder mode 0 - \arg TIMER_ENCODER_MODE1: encoder mode 1 - \arg TIMER_ENCODER_MODE2: encoder mode 2 - \arg TIMER_SLAVE_MODE_RESTART: restart mode - \arg TIMER_SLAVE_MODE_PAUSE: pause mode - \arg TIMER_SLAVE_MODE_EVENT: event mode - \arg TIMER_SLAVE_MODE_EXTERNAL0: external clock mode 0. + \param[in] slavemode: + only one parameter can be selected which is shown as below: + \arg TIMER_SLAVE_MODE_DISABLE: slave mode disable(TIMERx(x=0..4,7,8,11)) + \arg TIMER_ENCODER_MODE0: encoder mode 0(TIMERx(x=0..4,7)) + \arg TIMER_ENCODER_MODE1: encoder mode 1(TIMERx(x=0..4,7)) + \arg TIMER_ENCODER_MODE2: encoder mode 2(TIMERx(x=0..4,7)) + \arg TIMER_SLAVE_MODE_RESTART: restart mode(TIMERx(x=0..4,7,8,11)) + \arg TIMER_SLAVE_MODE_PAUSE: pause mode(TIMERx(x=0..4,7,8,11)) + \arg TIMER_SLAVE_MODE_EVENT: event mode(TIMERx(x=0..4,7,8,11)) + \arg TIMER_SLAVE_MODE_EXTERNAL0: external clock mode 0.(TIMERx(x=0..4,7,8,11)) \param[out] none \retval none */ -void timer_slave_mode_select(uint32_t timer_periph,uint32_t timer_slavemode) +void timer_slave_mode_select(uint32_t timer_periph, uint32_t slavemode) { TIMER_SMCFG(timer_periph) &= (~(uint32_t)TIMER_SMCFG_SMC); - TIMER_SMCFG(timer_periph) |= (uint32_t)timer_slavemode; + TIMER_SMCFG(timer_periph) |= (uint32_t)slavemode; } /*! - \brief configure TIMER master slave mode + \brief configure TIMER master slave mode \param[in] timer_periph: TIMERx(x=0..4,7,8,11) - \param[in] timer_masterslave: + \param[in] masterslave: + only one parameter can be selected which is shown as below: \arg TIMER_MASTER_SLAVE_MODE_ENABLE: master slave mode enable \arg TIMER_MASTER_SLAVE_MODE_DISABLE: master slave mode disable \param[out] none \retval none -*/ -void timer_master_slave_mode_config(uint32_t timer_periph,uint8_t timer_masterslave) +*/ +void timer_master_slave_mode_config(uint32_t timer_periph, uint32_t masterslave) { - if(TIMER_MASTER_SLAVE_MODE_ENABLE == timer_masterslave){ + if(TIMER_MASTER_SLAVE_MODE_ENABLE == masterslave){ TIMER_SMCFG(timer_periph) |= (uint32_t)TIMER_SMCFG_MSM; - }else if(TIMER_MASTER_SLAVE_MODE_DISABLE == timer_masterslave){ + }else if(TIMER_MASTER_SLAVE_MODE_DISABLE == masterslave){ TIMER_SMCFG(timer_periph) &= ~(uint32_t)TIMER_SMCFG_MSM; }else{ + /* illegal parameters */ } } /*! \brief configure TIMER external trigger input \param[in] timer_periph: TIMERx(x=0..4,7) - \param[in] timer_extprescaler: + \param[in] extprescaler: + only one parameter can be selected which is shown as below: \arg TIMER_EXT_TRI_PSC_OFF: no divided \arg TIMER_EXT_TRI_PSC_DIV2: divided by 2 \arg TIMER_EXT_TRI_PSC_DIV4: divided by 4 \arg TIMER_EXT_TRI_PSC_DIV8: divided by 8 - \param[in] timer_expolarity: + \param[in] extpolarity: + only one parameter can be selected which is shown as below: \arg TIMER_ETP_FALLING: active low or falling edge active \arg TIMER_ETP_RISING: active high or rising edge active - \param[in] timer_extfilter: a value between 0 and 15 + \param[in] extfilter: a value between 0 and 15 \param[out] none \retval none */ -void timer_external_trigger_config(uint32_t timer_periph,uint32_t timer_extprescaler, - uint32_t timer_expolarity,uint32_t timer_extfilter) +void timer_external_trigger_config(uint32_t timer_periph, uint32_t extprescaler, + uint32_t extpolarity, uint32_t extfilter) { - TIMER_SMCFG(timer_periph) &= (~(uint32_t)(TIMER_SMCFG_ETP|TIMER_SMCFG_ETPSC|TIMER_SMCFG_ETFC)); - TIMER_SMCFG(timer_periph) |= (uint32_t)(timer_extprescaler|timer_expolarity); - TIMER_SMCFG(timer_periph) |= (uint32_t)(timer_extfilter<< 8U); + TIMER_SMCFG(timer_periph) &= (~(uint32_t)(TIMER_SMCFG_ETP | TIMER_SMCFG_ETPSC | TIMER_SMCFG_ETFC)); + TIMER_SMCFG(timer_periph) |= (uint32_t)(extprescaler | extpolarity); + TIMER_SMCFG(timer_periph) |= (uint32_t)(extfilter << 8U); } /*! \brief configure TIMER quadrature decoder mode \param[in] timer_periph: TIMERx(x=0..4,7,8,11) - \param[in] timer_decomode: + \param[in] decomode: + only one parameter can be selected which is shown as below: \arg TIMER_ENCODER_MODE0: counter counts on CI0FE0 edge depending on CI1FE1 level \arg TIMER_ENCODER_MODE1: counter counts on CI1FE1 edge depending on CI0FE0 level \arg TIMER_ENCODER_MODE2: counter counts on both CI0FE0 and CI1FE1 edges depending on the level of the other input - \param[in] timer_ic0polarity: + \param[in] ic0polarity: + only one parameter can be selected which is shown as below: \arg TIMER_IC_POLARITY_RISING: capture rising edge \arg TIMER_IC_POLARITY_FALLING: capture falling edge - \param[in] timer_ic1polarity: + \param[in] ic1polarity: + only one parameter can be selected which is shown as below: \arg TIMER_IC_POLARITY_RISING: capture rising edge \arg TIMER_IC_POLARITY_FALLING: capture falling edge \param[out] none \retval none */ -void timer_quadrature_decoder_mode_config(uint32_t timer_periph,uint32_t timer_decomode, - uint16_t timer_ic0polarity,uint16_t timer_ic1polarity) +void timer_quadrature_decoder_mode_config(uint32_t timer_periph, uint32_t decomode, + uint16_t ic0polarity, uint16_t ic1polarity) { TIMER_SMCFG(timer_periph) &= (~(uint32_t)TIMER_SMCFG_SMC); - TIMER_SMCFG(timer_periph) |= (uint32_t)timer_decomode; + TIMER_SMCFG(timer_periph) |= (uint32_t)decomode; TIMER_CHCTL0(timer_periph) &= (uint32_t)(((~(uint32_t)TIMER_CHCTL0_CH0MS))&((~(uint32_t)TIMER_CHCTL0_CH1MS))); - TIMER_CHCTL0(timer_periph) |= (uint32_t)(TIMER_IC_SELECTION_DIRECTTI|((uint32_t)TIMER_IC_SELECTION_DIRECTTI<< 8U)); + TIMER_CHCTL0(timer_periph) |= (uint32_t)(TIMER_IC_SELECTION_DIRECTTI|((uint32_t)TIMER_IC_SELECTION_DIRECTTI << 8U)); TIMER_CHCTL2(timer_periph) &= (~(uint32_t)(TIMER_CHCTL2_CH0P|TIMER_CHCTL2_CH0NP)); TIMER_CHCTL2(timer_periph) &= (~(uint32_t)(TIMER_CHCTL2_CH1P|TIMER_CHCTL2_CH1NP)); - TIMER_CHCTL2(timer_periph) |= ((uint32_t)timer_ic0polarity|((uint32_t)timer_ic1polarity<< 4U)); + TIMER_CHCTL2(timer_periph) |= ((uint32_t)ic0polarity|((uint32_t)ic1polarity << 4U)); } /*! @@ -1694,7 +1853,8 @@ void timer_internal_clock_config(uint32_t timer_periph) /*! \brief configure TIMER the internal trigger as external clock input \param[in] timer_periph: TIMERx(x=0..4,7,8,11) - \param[in] timer_intrigger: + \param[in] intrigger: + only one parameter can be selected which is shown as below: \arg TIMER_SMCFG_TRGSEL_ITI0: internal trigger 0 \arg TIMER_SMCFG_TRGSEL_ITI1: internal trigger 1 \arg TIMER_SMCFG_TRGSEL_ITI2: internal trigger 2 @@ -1702,9 +1862,9 @@ void timer_internal_clock_config(uint32_t timer_periph) \param[out] none \retval none */ -void timer_internal_trigger_as_external_clock_config(uint32_t timer_periph, uint32_t timer_intrigger) +void timer_internal_trigger_as_external_clock_config(uint32_t timer_periph, uint32_t intrigger) { - timer_input_trigger_source_select(timer_periph,timer_intrigger); + timer_input_trigger_source_select(timer_periph, intrigger); TIMER_SMCFG(timer_periph) &= ~(uint32_t)TIMER_SMCFG_SMC; TIMER_SMCFG(timer_periph) |= (uint32_t)TIMER_SLAVE_MODE_EXTERNAL0; } @@ -1712,35 +1872,37 @@ void timer_internal_trigger_as_external_clock_config(uint32_t timer_periph, uint /*! \brief configure TIMER the external trigger as external clock input \param[in] timer_periph: TIMERx(x=0..4,7,8,11) - \param[in] timer_extrigger: - \arg TIMER_SMCFG_TRGSEL_CI0F_ED: TI0 Edge Detector + \param[in] extrigger: + only one parameter can be selected which is shown as below: + \arg TIMER_SMCFG_TRGSEL_CI0F_ED: TI0 edge detector \arg TIMER_SMCFG_TRGSEL_CI0FE0: filtered TIMER input 0 \arg TIMER_SMCFG_TRGSEL_CI1FE1: filtered TIMER input 1 - \param[in] timer_expolarity: - \arg TIMER_IC_POLARITY_RISING: active low or falling edge active - \arg TIMER_IC_POLARITY_FALLING: active high or rising edge active - \param[in] timer_extfilter: a value between 0 and 15 + \param[in] extpolarity: + only one parameter can be selected which is shown as below: + \arg TIMER_IC_POLARITY_RISING: active high or rising edge active + \arg TIMER_IC_POLARITY_FALLING: active low or falling edge active + \param[in] extfilter: a value between 0 and 15 \param[out] none \retval none */ -void timer_external_trigger_as_external_clock_config(uint32_t timer_periph,uint32_t timer_extrigger, - uint16_t timer_expolarity,uint32_t timer_extfilter) +void timer_external_trigger_as_external_clock_config(uint32_t timer_periph, uint32_t extrigger, + uint16_t extpolarity, uint32_t extfilter) { - if(TIMER_SMCFG_TRGSEL_CI1FE1 == timer_extrigger){ + if(TIMER_SMCFG_TRGSEL_CI1FE1 == extrigger){ /* reset the CH1EN bit */ TIMER_CHCTL2(timer_periph) &= (~(uint32_t)TIMER_CHCTL2_CH1EN); /* reset the CH1NP bit */ TIMER_CHCTL2(timer_periph) &= (~(uint32_t)(TIMER_CHCTL2_CH1P|TIMER_CHCTL2_CH1NP)); /* set the CH1NP bit */ - TIMER_CHCTL2(timer_periph) |= (uint32_t)((uint32_t)timer_expolarity << 4U); + TIMER_CHCTL2(timer_periph) |= (uint32_t)((uint32_t)extpolarity << 4U); /* reset the CH1MS bit */ TIMER_CHCTL0(timer_periph) &= (~(uint32_t)TIMER_CHCTL0_CH1MS); /* set the CH1MS bit */ - TIMER_CHCTL0(timer_periph) |= (uint32_t)((uint32_t)TIMER_IC_SELECTION_DIRECTTI<< 8U); + TIMER_CHCTL0(timer_periph) |= (uint32_t)((uint32_t)TIMER_IC_SELECTION_DIRECTTI << 8U); /* reset the CH1CAPFLT bit */ TIMER_CHCTL0(timer_periph) &= (~(uint32_t)TIMER_CHCTL0_CH1CAPFLT); /* set the CH1CAPFLT bit */ - TIMER_CHCTL0(timer_periph) |= (uint32_t)(timer_extfilter<< 8U); + TIMER_CHCTL0(timer_periph) |= (uint32_t)(extfilter << 12U); /* set the CH1EN bit */ TIMER_CHCTL2(timer_periph) |= (uint32_t)TIMER_CHCTL2_CH1EN; }else{ @@ -1749,7 +1911,7 @@ void timer_external_trigger_as_external_clock_config(uint32_t timer_periph,uint3 /* reset the CH0P and CH0NP bits */ TIMER_CHCTL2(timer_periph) &= (~(uint32_t)(TIMER_CHCTL2_CH0P|TIMER_CHCTL2_CH0NP)); /* set the CH0P and CH0NP bits */ - TIMER_CHCTL2(timer_periph) |= (uint32_t)timer_expolarity; + TIMER_CHCTL2(timer_periph) |= (uint32_t)extpolarity; /* reset the CH0MS bit */ TIMER_CHCTL0(timer_periph) &= (~(uint32_t)TIMER_CHCTL0_CH0MS); /* set the CH0MS bit */ @@ -1757,12 +1919,12 @@ void timer_external_trigger_as_external_clock_config(uint32_t timer_periph,uint3 /* reset the CH0CAPFLT bit */ TIMER_CHCTL0(timer_periph) &= (~(uint32_t)TIMER_CHCTL0_CH0CAPFLT); /* reset the CH0CAPFLT bit */ - TIMER_CHCTL0(timer_periph) |= (uint32_t)timer_extfilter; + TIMER_CHCTL0(timer_periph) |= (uint32_t)(extfilter << 4U); /* set the CH0EN bit */ TIMER_CHCTL2(timer_periph) |= (uint32_t)TIMER_CHCTL2_CH0EN; } /* select TIMER input trigger source */ - timer_input_trigger_source_select(timer_periph,timer_extrigger); + timer_input_trigger_source_select(timer_periph,extrigger); /* reset the SMC bit */ TIMER_SMCFG(timer_periph) &= (~(uint32_t)TIMER_SMCFG_SMC); /* set the SMC bit */ @@ -1772,23 +1934,25 @@ void timer_external_trigger_as_external_clock_config(uint32_t timer_periph,uint3 /*! \brief configure TIMER the external clock mode0 \param[in] timer_periph: TIMERx(x=0..4,7,8,11) - \param[in] timer_extprescaler: + \param[in] extprescaler: + only one parameter can be selected which is shown as below: \arg TIMER_EXT_TRI_PSC_OFF: no divided \arg TIMER_EXT_TRI_PSC_DIV2: divided by 2 \arg TIMER_EXT_TRI_PSC_DIV4: divided by 4 \arg TIMER_EXT_TRI_PSC_DIV8: divided by 8 - \param[in] timer_expolarity: + \param[in] extpolarity: + only one parameter can be selected which is shown as below: \arg TIMER_ETP_FALLING: active low or falling edge active \arg TIMER_ETP_RISING: active high or rising edge active - \param[in] timer_extfilter: a value between 0 and 15 + \param[in] extfilter: a value between 0 and 15 \param[out] none \retval none */ -void timer_external_clock_mode0_config(uint32_t timer_periph,uint32_t timer_extprescaler, - uint32_t timer_expolarity,uint32_t timer_extfilter) +void timer_external_clock_mode0_config(uint32_t timer_periph, uint32_t extprescaler, + uint32_t extpolarity, uint32_t extfilter) { /* configure TIMER external trigger input */ - timer_external_trigger_config(timer_periph,timer_extprescaler,timer_expolarity,timer_extfilter); + timer_external_trigger_config(timer_periph, extprescaler, extpolarity, extfilter); /* reset the SMC bit,TRGS bit */ TIMER_SMCFG(timer_periph) &= (~(uint32_t)(TIMER_SMCFG_SMC | TIMER_SMCFG_TRGS)); @@ -1799,23 +1963,25 @@ void timer_external_clock_mode0_config(uint32_t timer_periph,uint32_t timer_extp /*! \brief configure TIMER the external clock mode1 \param[in] timer_periph: TIMERx(x=0..4,7) - \param[in] timer_extprescaler: + \param[in] extprescaler: + only one parameter can be selected which is shown as below: \arg TIMER_EXT_TRI_PSC_OFF: no divided \arg TIMER_EXT_TRI_PSC_DIV2: divided by 2 \arg TIMER_EXT_TRI_PSC_DIV4: divided by 4 \arg TIMER_EXT_TRI_PSC_DIV8: divided by 8 - \param[in] timer_expolarity: + \param[in] extpolarity: + only one parameter can be selected which is shown as below: \arg TIMER_ETP_FALLING: active low or falling edge active \arg TIMER_ETP_RISING: active high or rising edge active - \param[in] timer_extfilter: a value between 0 and 15 + \param[in] extfilter: a value between 0 and 15 \param[out] none \retval none */ -void timer_external_clock_mode1_config(uint32_t timer_periph,uint32_t timer_extprescaler, - uint32_t timer_expolarity,uint32_t timer_extfilter) +void timer_external_clock_mode1_config(uint32_t timer_periph, uint32_t extprescaler, + uint32_t extpolarity, uint32_t extfilter) { /* configure TIMER external trigger input */ - timer_external_trigger_config(timer_periph,timer_extprescaler,timer_expolarity,timer_extfilter); + timer_external_trigger_config(timer_periph, extprescaler, extpolarity, extfilter); TIMER_SMCFG(timer_periph) |= (uint32_t)TIMER_SMCFG_SMC1; } @@ -1832,9 +1998,10 @@ void timer_external_clock_mode1_disable(uint32_t timer_periph) } /*! - \brief configure TIMER1 channel0 remap function + \brief configure TIMER channel remap function \param[in] timer_periph: TIMERx(x=1,4,10) - \param[in] timer_remap: + \param[in] remap: + only one parameter can be selected which is shown as below: \arg TIMER1_ITI1_RMP_TIMER7_TRGO: timer1 internal trigger input1 remap to TIMER7_TRGO \arg TIMER1_ITI1_RMP_ETHERNET_PTP: timer1 internal trigger input1 remap to ethernet PTP \arg TIMER1_ITI1_RMP_USB_FS_SOF: timer1 internal trigger input1 remap to USB FS SOF @@ -1842,51 +2009,55 @@ void timer_external_clock_mode1_disable(uint32_t timer_periph) \arg TIMER4_CI3_RMP_GPIO: timer4 channel 3 input remap to GPIO pin \arg TIMER4_CI3_RMP_IRC32K: timer4 channel 3 input remap to IRC32K \arg TIMER4_CI3_RMP_LXTAL: timer4 channel 3 input remap to LXTAL - \arg TIMER4_CI3_RMP_RTC_WAKEUP_INT: timer4 channel 3 input remap to RTC wakeup interrupt + \arg TIMER4_CI3_RMP_RTC_WAKEUP_INT: timer4 channel 3 input remap to RTC wakeup interrupt \arg TIMER10_ITI1_RMP_GPIO: timer10 internal trigger input1 remap based on GPIO setting \arg TIMER10_ITI1_RMP_RTC_HXTAL_DIV: timer10 internal trigger input1 remap HXTAL _DIV(clock used for RTC which is HXTAL clock divided by RTCDIV bits in RCU_CFG0 register) \param[out] none \retval none */ -void timer_channel_remap_config(uint32_t timer_periph,uint32_t timer_remap) +void timer_channel_remap_config(uint32_t timer_periph, uint32_t remap) { - TIMER_IRMP(timer_periph) = (uint32_t)timer_remap; + TIMER_IRMP(timer_periph) = (uint32_t)remap; } /*! \brief configure TIMER write CHxVAL register selection \param[in] timer_periph: TIMERx(x=0,1,2,13,14,15,16) - \param[in] timer_ccsel: - \arg TIMER_CCSEL_DISABLE: no effect - \arg TIMER_CCSEL_ENABLE: if write the CHxVAL register, the write value is same as the CHxVAL value, the write access ignored + \param[in] ccsel: + only one parameter can be selected which is shown as below: + \arg TIMER_CHVSEL_DISABLE: no effect + \arg TIMER_CHVSEL_ENABLE: when write the CHxVAL register, if the write value is same as the CHxVAL value, the write access is ignored \param[out] none \retval none */ -void timer_write_cc_register_config(uint32_t timer_periph, uint16_t timer_ccsel) +void timer_write_chxval_register_config(uint32_t timer_periph, uint16_t ccsel) { - if(TIMER_CCSEL_ENABLE == timer_ccsel){ + if(TIMER_CHVSEL_ENABLE == ccsel){ TIMER_CFG(timer_periph) |= (uint32_t)TIMER_CFG_CHVSEL; - }else if(TIMER_CCSEL_DISABLE == timer_ccsel){ + }else if(TIMER_CHVSEL_DISABLE == ccsel){ TIMER_CFG(timer_periph) &= ~(uint32_t)TIMER_CFG_CHVSEL; }else{ + /* illegal parameters */ } } /*! \brief configure TIMER output value selection \param[in] timer_periph: TIMERx(x=0,7) - \param[in] timer_outsel: + \param[in] outsel: + only one parameter can be selected which is shown as below: \arg TIMER_OUTSEL_DISABLE: no effect \arg TIMER_OUTSEL_ENABLE: if POEN and IOS is 0, the output disabled \param[out] none \retval none */ -void timer_output_value_selection_config(uint32_t timer_periph, uint16_t timer_outsel) +void timer_output_value_selection_config(uint32_t timer_periph, uint16_t outsel) { - if(TIMER_OUTSEL_ENABLE == timer_outsel){ + if(TIMER_OUTSEL_ENABLE == outsel){ TIMER_CFG(timer_periph) |= (uint32_t)TIMER_CFG_OUTSEL; - }else if(TIMER_OUTSEL_DISABLE == timer_outsel){ + }else if(TIMER_OUTSEL_DISABLE == outsel){ TIMER_CFG(timer_periph) &= ~(uint32_t)TIMER_CFG_OUTSEL; }else{ + /* illegal parameters */ } } diff --git a/bsp/gd32450z-eval/Libraries/GD32F4xx_standard_peripheral/Source/gd32f4xx_tli.c b/bsp/gd32450z-eval/Libraries/GD32F4xx_standard_peripheral/Source/gd32f4xx_tli.c index dfa65744ba..9d719bb29b 100644 --- a/bsp/gd32450z-eval/Libraries/GD32F4xx_standard_peripheral/Source/gd32f4xx_tli.c +++ b/bsp/gd32450z-eval/Libraries/GD32F4xx_standard_peripheral/Source/gd32f4xx_tli.c @@ -1,18 +1,46 @@ /*! - \file gd32f4xx_tli.c - \brief TLI driver + \file gd32f4xx_tli.c + \brief TLI driver + + \version 2016-08-15, V1.0.0, firmware for GD32F4xx + \version 2018-12-12, V2.0.0, firmware for GD32F4xx + \version 2020-09-30, V2.1.0, firmware for GD32F4xx */ /* - Copyright (C) 2016 GigaDevice + Copyright (c) 2020, GigaDevice Semiconductor Inc. + + Redistribution and use in source and binary forms, with or without modification, +are permitted provided that the following conditions are met: + + 1. Redistributions of source code must retain the above copyright notice, this + list of conditions and the following disclaimer. + 2. Redistributions in binary form must reproduce the above copyright notice, + this list of conditions and the following disclaimer in the documentation + and/or other materials provided with the distribution. + 3. Neither the name of the copyright holder nor the names of its contributors + may be used to endorse or promote products derived from this software without + specific prior written permission. - 2016-08-15, V1.0.1, firmware for GD32F4xx + THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED +WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. +IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, +INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT +NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR +PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, +WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY +OF SUCH DAMAGE. */ #include "gd32f4xx_tli.h" +#define TLI_DEFAULT_VALUE 0x00000000U +#define TLI_OPAQUE_VALUE 0x000000FFU + /*! - \brief deinitialize TLI registers + \brief deinitialize TLI registers \param[in] none \param[out] none \retval none @@ -24,15 +52,57 @@ void tli_deinit(void) } /*! - \brief initialize TLI display timing parameters - \param[in] tli_struct: the data needed to initialize tli. + \brief initialize the parameters of TLI parameter structure with the default values, it is suggested + that call this function after a tli_parameter_struct structure is defined + \param[in] none + \param[out] tli_struct: the data needed to initialize TLI synpsz_vpsz: size of the vertical synchronous pulse synpsz_hpsz: size of the horizontal synchronous pulse - backpsz_vbpsz: size of the vertical back porch plus synchronous pulse + backpsz_vbpsz: size of the vertical back porch plus synchronous pulse backpsz_hbpsz: size of the horizontal back porch plus synchronous pulse activesz_vasz: size of the vertical active area width plus back porch and synchronous pulse activesz_hasz: size of the horizontal active area width plus back porch and synchronous pulse - totalsz_vtsz: vertical total size of the display, including active area, back porch, synchronous + totalsz_vtsz: vertical total size of the display, including active area, back porch, synchronous + totalsz_htsz: vorizontal total size of the display, including active area, back porch, synchronous + backcolor_red: background value red + backcolor_green: background value green + backcolor_blue: background value blue + signalpolarity_hs: TLI_HSYN_ACTLIVE_LOW,TLI_HSYN_ACTLIVE_HIGHT + signalpolarity_vs: TLI_VSYN_ACTLIVE_LOW,TLI_VSYN_ACTLIVE_HIGHT + signalpolarity_de: TLI_DE_ACTLIVE_LOW,TLI_DE_ACTLIVE_HIGHT + signalpolarity_pixelck: TLI_PIXEL_CLOCK_TLI,TLI_PIXEL_CLOCK_INVERTEDTLI + \retval none +*/ +void tli_struct_para_init(tli_parameter_struct *tli_struct) +{ + /* initialize the struct parameters with default values */ + tli_struct->synpsz_vpsz = TLI_DEFAULT_VALUE; + tli_struct->synpsz_hpsz = TLI_DEFAULT_VALUE; + tli_struct->backpsz_vbpsz = TLI_DEFAULT_VALUE; + tli_struct->backpsz_hbpsz = TLI_DEFAULT_VALUE; + tli_struct->activesz_vasz = TLI_DEFAULT_VALUE; + tli_struct->activesz_hasz = TLI_DEFAULT_VALUE; + tli_struct->totalsz_vtsz = TLI_DEFAULT_VALUE; + tli_struct->totalsz_htsz = TLI_DEFAULT_VALUE; + tli_struct->backcolor_red = TLI_DEFAULT_VALUE; + tli_struct->backcolor_green = TLI_DEFAULT_VALUE; + tli_struct->backcolor_blue = TLI_DEFAULT_VALUE; + tli_struct->signalpolarity_hs = TLI_HSYN_ACTLIVE_LOW; + tli_struct->signalpolarity_vs = TLI_VSYN_ACTLIVE_LOW; + tli_struct->signalpolarity_de = TLI_DE_ACTLIVE_LOW; + tli_struct->signalpolarity_pixelck = TLI_PIXEL_CLOCK_TLI; +} + +/*! + \brief initialize TLI display timing parameters + \param[in] tli_struct: the data needed to initialize TLI + synpsz_vpsz: size of the vertical synchronous pulse + synpsz_hpsz: size of the horizontal synchronous pulse + backpsz_vbpsz: size of the vertical back porch plus synchronous pulse + backpsz_hbpsz: size of the horizontal back porch plus synchronous pulse + activesz_vasz: size of the vertical active area width plus back porch and synchronous pulse + activesz_hasz: size of the horizontal active area width plus back porch and synchronous pulse + totalsz_vtsz: vertical total size of the display, including active area, back porch, synchronous totalsz_htsz: vorizontal total size of the display, including active area, back porch, synchronous backcolor_red: background value red backcolor_green: background value green @@ -48,19 +118,19 @@ void tli_init(tli_parameter_struct *tli_struct) { /* synchronous pulse size configuration */ TLI_SPSZ &= ~(TLI_SPSZ_VPSZ|TLI_SPSZ_HPSZ); - TLI_SPSZ = (tli_struct->synpsz_vpsz|(tli_struct->synpsz_hpsz<<16U)); + TLI_SPSZ = (uint32_t)((uint32_t)tli_struct->synpsz_vpsz|((uint32_t)tli_struct->synpsz_hpsz<<16U)); /* back-porch size configuration */ TLI_BPSZ &= ~(TLI_BPSZ_VBPSZ|TLI_BPSZ_HBPSZ); - TLI_BPSZ = (tli_struct->backpsz_vbpsz|(tli_struct->backpsz_hbpsz<<16U)); - /* active size configuration */ + TLI_BPSZ = (uint32_t)((uint32_t)tli_struct->backpsz_vbpsz|((uint32_t)tli_struct->backpsz_hbpsz<<16U)); + /* active size configuration */ TLI_ASZ &= ~(TLI_ASZ_VASZ|TLI_ASZ_HASZ); TLI_ASZ = (tli_struct->activesz_vasz|(tli_struct->activesz_hasz<<16U)); - /* total size configuration */ + /* total size configuration */ TLI_TSZ &= ~(TLI_TSZ_VTSZ|TLI_TSZ_HTSZ); TLI_TSZ = (tli_struct->totalsz_vtsz|(tli_struct->totalsz_htsz<<16U)); - /* background color configuration */ + /* background color configuration */ TLI_BGC &= ~(TLI_BGC_BVB|(TLI_BGC_BVG)|(TLI_BGC_BVR)); - TLI_BGC = (tli_struct->backcolor_blue|(tli_struct->backcolor_green<<8U)|(tli_struct->backcolor_red<<16U)); + TLI_BGC = (tli_struct->backcolor_blue|(tli_struct->backcolor_green<<8U)|(tli_struct->backcolor_red<<16U)); TLI_CTL &= ~(TLI_CTL_HPPS|TLI_CTL_VPPS|TLI_CTL_DEPS|TLI_CTL_CLKPS); TLI_CTL |= (tli_struct->signalpolarity_hs|tli_struct->signalpolarity_vs|\ tli_struct->signalpolarity_de|tli_struct->signalpolarity_pixelck); @@ -68,14 +138,17 @@ void tli_init(tli_parameter_struct *tli_struct) } /*! - \brief dither function configure - \param[in] ditherstat: TLI_DITHER_ENABLE,TLI_DITHER_DISABLE + \brief configure TLI dither function + \param[in] dither_stat + only one parameter can be selected which is shown as below: + \arg TLI_DITHER_ENABLE + \arg TLI_DITHER_DISABLE \param[out] none \retval none */ -void tli_dither_config(uint8_t ditherstat) +void tli_dither_config(uint8_t dither_stat) { - if(TLI_DITHER_ENABLE == ditherstat){ + if(TLI_DITHER_ENABLE == dither_stat){ TLI_CTL |= TLI_CTL_DFEN; }else{ TLI_CTL &= ~(TLI_CTL_DFEN); @@ -83,8 +156,8 @@ void tli_dither_config(uint8_t ditherstat) } /*! - \brief TLI enable - \param[in] none. + \brief enable TLI + \param[in] none \param[out] none \retval none */ @@ -94,145 +167,247 @@ void tli_enable(void) } /*! - \brief TLI disable - \param[in] none. + \brief disable TLI + \param[in] none \param[out] none \retval none */ void tli_disable(void) { - TLI_CTL &= ~(TLI_CTL_DFEN); + TLI_CTL &= ~(TLI_CTL_TLIEN); } /*! - \brief TLI reload layer configure - \param[in] reloadmod: TLI_FRAME_BLANK_RELOAD_EN,TLI_REQUEST_RELOAD_EN + \brief configure TLI reload mode + \param[in] reload_mod + only one parameter can be selected which is shown as below: + \arg TLI_FRAME_BLANK_RELOAD_EN + \arg TLI_REQUEST_RELOAD_EN \param[out] none \retval none */ -void tli_reload_config(uint8_t reloadmod) +void tli_reload_config(uint8_t reload_mod) { - if(TLI_FRAME_BLANK_RELOAD_EN == reloadmod){ + if(TLI_FRAME_BLANK_RELOAD_EN == reload_mod){ + /* the layer configuration will be reloaded at frame blank */ TLI_RL |= TLI_RL_FBR; }else{ + /* the layer configuration will be reloaded after this bit sets */ TLI_RL |= TLI_RL_RQR; } } /*! - \brief TLI interrupt enable - \param[in] inttype: TLI interrupt bits. - \arg TLI_INTEN_LMIE: line mark interrupt - \arg TLI_INTEN_FEIE: FIFO error interrupt - \arg TLI_INTEN_TEIE: transaction error interrupt - \arg TLI_INTEN_LCRIE: layer configuration reloaded interrupt - \param[out] none + \brief initialize the parameters of TLI layer structure with the default values, it is suggested + that call this function after a tli_layer_parameter_struct structure is defined + \param[in] none + \param[out] layer_struct: TLI Layer parameter struct + layer_window_rightpos: window right position + layer_window_leftpos: window left position + layer_window_bottompos: window bottom position + layer_window_toppos: window top position + layer_ppf: LAYER_PPF_ARGB8888,LAYER_PPF_RGB888,LAYER_PPF_RGB565, + LAYER_PPF_ARG1555,LAYER_PPF_ARGB4444,LAYER_PPF_L8, + LAYER_PPF_AL44,LAYER_PPF_AL88 + layer_sa: specified alpha + layer_default_alpha: the default color alpha + layer_default_red: the default color red + layer_default_green: the default color green + layer_default_blue: the default color blue + layer_acf1: LAYER_ACF1_SA,LAYER_ACF1_PASA + layer_acf2: LAYER_ACF2_SA,LAYER_ACF2_PASA + layer_frame_bufaddr: frame buffer base address + layer_frame_buf_stride_offset: frame buffer stride offset + layer_frame_line_length: frame line length + layer_frame_total_line_number: frame total line number \retval none */ -void tli_interrupt_enable(uint32_t inttype) +void tli_layer_struct_para_init(tli_layer_parameter_struct *layer_struct) { - TLI_INTEN |= (inttype); + /* initialize the struct parameters with default values */ + layer_struct->layer_window_rightpos = TLI_DEFAULT_VALUE; + layer_struct->layer_window_leftpos = TLI_DEFAULT_VALUE; + layer_struct->layer_window_bottompos = TLI_DEFAULT_VALUE; + layer_struct->layer_window_toppos = TLI_DEFAULT_VALUE; + layer_struct->layer_ppf = LAYER_PPF_ARGB8888; + layer_struct->layer_sa = TLI_OPAQUE_VALUE; + layer_struct->layer_default_alpha = TLI_DEFAULT_VALUE; + layer_struct->layer_default_red = TLI_DEFAULT_VALUE; + layer_struct->layer_default_green = TLI_DEFAULT_VALUE; + layer_struct->layer_default_blue = TLI_DEFAULT_VALUE; + layer_struct->layer_acf1 = LAYER_ACF1_PASA; + layer_struct->layer_acf2 = LAYER_ACF2_PASA; + layer_struct->layer_frame_bufaddr = TLI_DEFAULT_VALUE; + layer_struct->layer_frame_buf_stride_offset = TLI_DEFAULT_VALUE; + layer_struct->layer_frame_line_length = TLI_DEFAULT_VALUE; + layer_struct->layer_frame_total_line_number = TLI_DEFAULT_VALUE; } /*! - \brief TLI interrupt disable - \param[in] inttype: TLI interrupt bits. - \arg TLI_INTEN_LMIE: line mark interrupt - \arg TLI_INTEN_FEIE: FIFO error interrupt - \arg TLI_INTEN_TEIE: transaction error interrupt - \arg TLI_INTEN_LCRIE: layer configuration reloaded interrupt + \brief initialize TLI layer + \param[in] layerx: LAYERx(x=0,1) + \param[in] layer_struct: TLI Layer parameter struct + layer_window_rightpos: window right position + layer_window_leftpos: window left position + layer_window_bottompos: window bottom position + layer_window_toppos: window top position + layer_ppf: LAYER_PPF_ARGB8888,LAYER_PPF_RGB888,LAYER_PPF_RGB565, + LAYER_PPF_ARG1555,LAYER_PPF_ARGB4444,LAYER_PPF_L8, + LAYER_PPF_AL44,LAYER_PPF_AL88 + layer_sa: specified alpha + layer_default_alpha: the default color alpha + layer_default_red: the default color red + layer_default_green: the default color green + layer_default_blue: the default color blue + layer_acf1: LAYER_ACF1_SA,LAYER_ACF1_PASA + layer_acf2: LAYER_ACF2_SA,LAYER_ACF2_PASA + layer_frame_bufaddr: frame buffer base address + layer_frame_buf_stride_offset: frame buffer stride offset + layer_frame_line_length: frame line length + layer_frame_total_line_number: frame total line number \param[out] none \retval none */ -void tli_interrupt_disable(uint32_t inttype) +void tli_layer_init(uint32_t layerx,tli_layer_parameter_struct *layer_struct) { - TLI_INTEN &= ~(inttype); -} + /* configure layer window horizontal position */ + TLI_LxHPOS(layerx) &= ~(TLI_LxHPOS_WLP|(TLI_LxHPOS_WRP)); + TLI_LxHPOS(layerx) = (uint32_t)((uint32_t)layer_struct->layer_window_leftpos|((uint32_t)layer_struct->layer_window_rightpos<<16U)); + /* configure layer window vertical position */ + TLI_LxVPOS(layerx) &= ~(TLI_LxVPOS_WTP|(TLI_LxVPOS_WBP)); + TLI_LxVPOS(layerx) = (uint32_t)((uint32_t)layer_struct->layer_window_toppos|((uint32_t)layer_struct->layer_window_bottompos<<16U)); + /* configure layer packeted pixel format */ + TLI_LxPPF(layerx) &= ~(TLI_LxPPF_PPF); + TLI_LxPPF(layerx) = layer_struct->layer_ppf; + /* configure layer specified alpha */ + TLI_LxSA(layerx) &= ~(TLI_LxSA_SA); + TLI_LxSA(layerx) = layer_struct->layer_sa; + /* configure layer default color */ + TLI_LxDC(layerx) &= ~(TLI_LxDC_DCB|(TLI_LxDC_DCG)|(TLI_LxDC_DCR)|(TLI_LxDC_DCA)); + TLI_LxDC(layerx) = (uint32_t)((uint32_t)layer_struct->layer_default_blue|((uint32_t)layer_struct->layer_default_green<<8U) + |((uint32_t)layer_struct->layer_default_red<<16U) + |((uint32_t)layer_struct->layer_default_alpha<<24U)); + + /* configure layer alpha calculation factors */ + TLI_LxBLEND(layerx) &= ~(TLI_LxBLEND_ACF2|(TLI_LxBLEND_ACF1)); + TLI_LxBLEND(layerx) = ((layer_struct->layer_acf2)|(layer_struct->layer_acf1)); + /* configure layer frame buffer base address */ + TLI_LxFBADDR(layerx) &= ~(TLI_LxFBADDR_FBADD); + TLI_LxFBADDR(layerx) = (layer_struct->layer_frame_bufaddr); + /* configure layer frame line length */ + TLI_LxFLLEN(layerx) &= ~(TLI_LxFLLEN_FLL|(TLI_LxFLLEN_STDOFF)); + TLI_LxFLLEN(layerx) = (uint32_t)((uint32_t)layer_struct->layer_frame_line_length|((uint32_t)layer_struct->layer_frame_buf_stride_offset<<16U)); + /* configure layer frame total line number */ + TLI_LxFTLN(layerx) &= ~(TLI_LxFTLN_FTLN); + TLI_LxFTLN(layerx) = (uint32_t)(layer_struct->layer_frame_total_line_number); -/*! - \brief get TLI interrupt flag - \param[in] intflag: TLI interrupt flag bits. - \arg TLI_INTF_LMF: line mark flag - \arg TLI_INTF_FEF: FIFO error flag - \arg TLI_INTF_TEF: transaction error flag - \arg TLI_INTF_LCRF: layer configuration reloaded flag - \param[out] none - \retval none -*/ -FlagStatus tli_interrupt_flag_get(uint32_t intflag) -{ - uint32_t state; - state = TLI_INTF; - if(state & intflag){ - return SET; - }else{ - return RESET; - } } /*! - \brief clear TLI interrupt flag - \param[in] intflag: TLI interrupt flag bits. - \arg TLI_INTC_LMC: line mark flag - \arg TLI_INTC_FEC: FIFO error flag - \arg TLI_INTC_TEC: transaction error flag - \arg TLI_INTC_LCRC: layer configuration reloaded flag + \brief reconfigure window position + \param[in] layerx: LAYERx(x=0,1) + \param[in] offset_x: new horizontal offset + \param[in] offset_y: new vertical offset \param[out] none \retval none */ -void tli_interrupt_flag_clear(uint32_t intflag) +void tli_layer_window_offset_modify(uint32_t layerx,uint16_t offset_x,uint16_t offset_y) { - TLI_INTC |= (intflag); + /* configure window start position */ + uint32_t layer_ppf, line_num, hstart, vstart; + uint32_t line_length = 0U; + TLI_LxHPOS(layerx) &= ~(TLI_LxHPOS_WLP|(TLI_LxHPOS_WRP)); + TLI_LxVPOS(layerx) &= ~(TLI_LxVPOS_WTP|(TLI_LxVPOS_WBP)); + hstart = (uint32_t)offset_x+(((TLI_BPSZ & TLI_BPSZ_HBPSZ)>>16U)+1U); + vstart = (uint32_t)offset_y+((TLI_BPSZ & TLI_BPSZ_VBPSZ)+1U); + line_num = (TLI_LxFTLN(layerx) & TLI_LxFTLN_FTLN); + layer_ppf = (TLI_LxPPF(layerx) & TLI_LxPPF_PPF); + /* the bytes of a line equal TLI_LxFLLEN_FLL bits value minus 3 */ + switch(layer_ppf){ + case LAYER_PPF_ARGB8888: + /* each pixel includes 4bytes, when pixel format is ARGB8888 */ + line_length = (((TLI_LxFLLEN(layerx) & TLI_LxFLLEN_FLL)-3U)/4U); + break; + case LAYER_PPF_RGB888: + /* each pixel includes 3bytes, when pixel format is RGB888 */ + line_length = (((TLI_LxFLLEN(layerx) & TLI_LxFLLEN_FLL)-3U)/3U); + break; + case LAYER_PPF_RGB565: + case LAYER_PPF_ARGB1555: + case LAYER_PPF_ARGB4444: + case LAYER_PPF_AL88: + /* each pixel includes 2bytes, when pixel format is RGB565,ARG1555,ARGB4444 or AL88 */ + line_length = (((TLI_LxFLLEN(layerx) & TLI_LxFLLEN_FLL)-3U)/2U); + break; + case LAYER_PPF_L8: + case LAYER_PPF_AL44: + /* each pixel includes 1byte, when pixel format is L8 or AL44 */ + line_length = (((TLI_LxFLLEN(layerx) & TLI_LxFLLEN_FLL)-3U)); + break; + default: + break; + } + /* reconfigure window position */ + TLI_LxHPOS(layerx) = (hstart|((hstart+line_length-1U)<<16U)); + TLI_LxVPOS(layerx) = (vstart|((vstart+line_num-1U)<<16U)); } /*! - \brief set line mark value - \param[in] linenum: line number. - \param[out] none + \brief initialize the parameters of TLI layer LUT structure with the default values, it is suggested + that call this function after a tli_layer_lut_parameter_struct structure is defined + \param[in] none + \param[out] lut_struct: TLI layer LUT parameter struct + layer_table_addr: look up table write address + layer_lut_channel_red: red channel of a LUT entry + layer_lut_channel_green: green channel of a LUT entry + layer_lut_channel_blue: blue channel of a LUT entry \retval none */ -void tli_line_mark_set(uint32_t linenum) +void tli_lut_struct_para_init(tli_layer_lut_parameter_struct *lut_struct) { - TLI_LM &= ~(TLI_LM_LM); - TLI_LM = linenum; + /* initialize the struct parameters with default values */ + lut_struct->layer_table_addr = TLI_DEFAULT_VALUE; + lut_struct->layer_lut_channel_red = TLI_DEFAULT_VALUE; + lut_struct->layer_lut_channel_green = TLI_DEFAULT_VALUE; + lut_struct->layer_lut_channel_blue = TLI_DEFAULT_VALUE; } /*! - \brief get current displayed position - \param[in] none + \brief initialize TLI layer LUT + \param[in] layerx: LAYERx(x=0,1) + \param[in] lut_struct: TLI layer LUT parameter struct + layer_table_addr: look up table write address + layer_lut_channel_red: red channel of a LUT entry + layer_lut_channel_green: green channel of a LUT entry + layer_lut_channel_blue: blue channel of a LUT entry \param[out] none \retval none */ -uint32_t tli_current_pos_get(void) +void tli_lut_init(uint32_t layerx,tli_layer_lut_parameter_struct *lut_struct) { - return TLI_CPPOS; + TLI_LxLUT(layerx) &= ~(TLI_LxLUT_TB|TLI_LxLUT_TG|TLI_LxLUT_TR|TLI_LxLUT_TADD); + TLI_LxLUT(layerx) = (uint32_t)(((uint32_t)lut_struct->layer_lut_channel_blue)|((uint32_t)lut_struct->layer_lut_channel_green<<8U) + |((uint32_t)lut_struct->layer_lut_channel_red<<16U + |((uint32_t)lut_struct->layer_table_addr<<24U))); } - /*! - \brief get TLI state - \param[in] state: TLI state. - \arg TLI_STAT_VDE: current VDE state - \arg TLI_STAT_HDE: current HDE state - \arg TLI_STAT_VS: current vs state - \arg TLI_STAT_HS: current hs state + \brief initialize TLI layer color key + \param[in] layerx: LAYERx(x=0,1) + \param[in] redkey: color key red + \param[in] greenkey: color key green + \param[in] bluekey: color key blue \param[out] none \retval none */ -FlagStatus tli_flag_get(uint32_t state) +void tli_color_key_init(uint32_t layerx,uint8_t redkey,uint8_t greenkey,uint8_t bluekey) { - uint32_t stat; - stat = TLI_STAT; - if(state & stat){ - return SET; - }else{ - return RESET; - } + TLI_LxCKEY(layerx) = (((uint32_t)bluekey)|((uint32_t)greenkey<<8U)|((uint32_t)redkey<<16U)); } /*! - \brief TLI layer enable - \param[in] layerx: LAYERx(x=0,1). + \brief enable TLI layer + \param[in] layerx: LAYERx(x=0,1) \param[out] none \retval none */ @@ -242,8 +417,8 @@ void tli_layer_enable(uint32_t layerx) } /*! - \brief TLI layer disable - \param[in] layerx: LAYERx(x=0,1). + \brief disable TLI layer + \param[in] layerx: LAYERx(x=0,1) \param[out] none \retval none */ @@ -253,8 +428,8 @@ void tli_layer_disable(uint32_t layerx) } /*! - \brief TLI layer color keying enable - \param[in] layerx: LAYERx(x=0,1). + \brief enable TLI layer color keying + \param[in] layerx: LAYERx(x=0,1) \param[out] none \retval none */ @@ -264,8 +439,8 @@ void tli_color_key_enable(uint32_t layerx) } /*! - \brief TLI layer color keying disable - \param[in] layerx: LAYERx(x=0,1). + \brief disable TLI layer color keying + \param[in] layerx: LAYERx(x=0,1) \param[out] none \retval none */ @@ -275,8 +450,8 @@ void tli_color_key_disable(uint32_t layerx) } /*! - \brief TLI layer LUT enable - \param[in] layerx: LAYERx(x=0,1). + \brief enable TLI layer LUT + \param[in] layerx: LAYERx(x=0,1) \param[out] none \retval none */ @@ -286,8 +461,8 @@ void tli_lut_enable(uint32_t layerx) } /*! - \brief TLI layer LUT disable - \param[in] layerx: LAYERx(x=0,1). + \brief disable TLI layer LUT + \param[in] layerx: LAYERx(x=0,1) \param[out] none \retval none */ @@ -297,147 +472,127 @@ void tli_lut_disable(uint32_t layerx) } /*! - \brief TLI layer initialize - \param[in] layerx: LAYERx(x=0,1) - \param[in] layer_struct: TLI Layer parameter struct - layer_window_rightpos: window right position - layer_window_leftpos: window left position - layer_window_bottompos: window bottom position - layer_window_toppos: window top position - layer_ppf: LAYER_PPF_ARGB8888,LAYER_PPF_RGB888,LAYER_PPF_RGB565, - LAYER_PPF_ARG1555,LAYER_PPF_ARGB4444,LAYER_PPF_L8, - LAYER_PPF_AL44,LAYER_PPF_AL88 - layer_sa: specified alpha - layer_default_alpha: the default color alpha - layer_default_red: the default color red - layer_default_green: the default color green - layer_default_blue: the default color blue - layer_acf1: LAYER_ACF1_SA,LAYER_ACF1_PASA - layer_acf2: LAYER_ACF2_SA,LAYER_ACF2_PASA - layer_frame_bufaddr: frame buffer base address - layer_frame_buf_stride_offset: frame buffer stride offset - layer_frame_line_length: frame line length - layer_frame_total_line_number: frame total line number + \brief set line mark value + \param[in] line_num: line number \param[out] none \retval none */ -void tli_layer_init(uint32_t layerx,tli_layer_parameter_struct *layer_struct) +void tli_line_mark_set(uint16_t line_num) { - /* configure layer window horizontal position */ - TLI_LxHPOS(layerx) &= ~(TLI_LxHPOS_WLP|(TLI_LxHPOS_WRP)); - TLI_LxHPOS(layerx) = (layer_struct->layer_window_leftpos | (layer_struct->layer_window_rightpos<<16U)); - /* configure layer window vertical position */ - TLI_LxVPOS(layerx) &= ~(TLI_LxVPOS_WTP|(TLI_LxVPOS_WBP)); - TLI_LxVPOS(layerx) = (layer_struct->layer_window_toppos |(layer_struct->layer_window_bottompos<<16U)); - /* configure layer packeted pixel format */ - TLI_LxPPF(layerx) &= ~(TLI_LxPPF_PPF); - TLI_LxPPF(layerx) = layer_struct->layer_ppf; - /* configure layer specified alpha */ - TLI_LxSA(layerx) &= ~(TLI_LxSA_SA); - TLI_LxSA(layerx) = layer_struct->layer_sa; - /* configure layer default color */ - TLI_LxDC(layerx) &= ~(TLI_LxDC_DCB|(TLI_LxDC_DCG)|(TLI_LxDC_DCR)|(TLI_LxDC_DCA)); - TLI_LxDC(layerx) = (layer_struct->layer_default_blue |(layer_struct->layer_default_green<<8U) - |(layer_struct->layer_default_red<<16U) - |(layer_struct->layer_default_alpha<<24U)); + TLI_LM &= ~(TLI_LM_LM); + TLI_LM = (uint32_t)line_num; +} - /* configure layer alpha calculation factors */ - TLI_LxBLEND(layerx) &= ~(TLI_LxBLEND_ACF2|(TLI_LxBLEND_ACF1)); - TLI_LxBLEND(layerx) = ((layer_struct->layer_acf2)|(layer_struct->layer_acf1)); - /* configure layer frame buffer base address */ - TLI_LxFBADDR(layerx) &= ~(TLI_LxFBADDR_FBADD); - TLI_LxFBADDR(layerx) = (layer_struct->layer_frame_bufaddr); - /* configure layer frame line length */ - TLI_LxFLLEN(layerx) &= ~(TLI_LxFLLEN_FLL|(TLI_LxFLLEN_STDOFF)); - TLI_LxFLLEN(layerx) = (layer_struct->layer_frame_line_length|(layer_struct->layer_frame_buf_stride_offset<<16U)); - /* configure layer frame buffer base address */ - TLI_LxFBADDR(layerx) &= ~(TLI_LxFBADDR_FBADD); - TLI_LxFBADDR(layerx) = (layer_struct->layer_frame_bufaddr); - /* configure layer frame total line number */ - TLI_LxFTLN(layerx) &= ~(TLI_LxFTLN_FTLN); - TLI_LxFTLN(layerx) = (layer_struct->layer_frame_total_line_number); +/*! + \brief get current displayed position + \param[in] none + \param[out] none + \retval position of current pixel +*/ +uint32_t tli_current_pos_get(void) +{ + return TLI_CPPOS; +} +/*! + \brief enable TLI interrupt + \param[in] int_flag: TLI interrupt flags + one or more parameters can be selected which are shown as below: + \arg TLI_INT_LM: line mark interrupt + \arg TLI_INT_FE: FIFO error interrupt + \arg TLI_INT_TE: transaction error interrupt + \arg TLI_INT_LCR: layer configuration reloaded interrupt + \param[out] none + \retval none +*/ +void tli_interrupt_enable(uint32_t int_flag) +{ + TLI_INTEN |= (int_flag); } /*! - \brief reconfigure window position - \param[in] layerx: LAYERx(x=0,1). - \param[in] offset_x: new horizontal offset . - \param[in] offset_y: new vertical offset. + \brief disable TLI interrupt + \param[in] int_flag: TLI interrupt flags + one or more parameters can be selected which are shown as below: + \arg TLI_INT_LM: line mark interrupt + \arg TLI_INT_FE: FIFO error interrupt + \arg TLI_INT_TE: transaction error interrupt + \arg TLI_INT_LCR: layer configuration reloaded interrupt \param[out] none \retval none */ -void tli_layer_window_offset_modify(uint32_t layerx,uint32_t offset_x,uint32_t offset_y) +void tli_interrupt_disable(uint32_t int_flag) { - /* configure window start position */ - uint32_t layer_ppf,line_length,line_num,hstart,vstart; - TLI_LxHPOS(layerx) &= ~(TLI_LxHPOS_WLP|(TLI_LxHPOS_WRP)); - TLI_LxVPOS(layerx) &= ~(TLI_LxVPOS_WTP|(TLI_LxVPOS_WBP)); - hstart = offset_x+(((TLI_BPSZ & TLI_BPSZ_HBPSZ)>>16U)+1U); - vstart = offset_y+((TLI_BPSZ & TLI_BPSZ_VBPSZ)+1U); - line_num = (TLI_LxFTLN(layerx) & TLI_LxFTLN_FTLN); - layer_ppf = (TLI_LxPPF(layerx) & TLI_LxPPF_PPF); - /* the bytes of a line equal TLI_LxFLLEN_FLL bits value minus 3 */ - switch(layer_ppf){ - case LAYER_PPF_ARGB8888: - /* each pixel includes 4bytes,when pixel format is ARGB8888 */ - line_length = (((TLI_LxFLLEN(layerx) & TLI_LxFLLEN_FLL)-3U)/4U); - break; - case LAYER_PPF_RGB888: - /* each pixel includes 3bytes,when pixel format is RGB888 */ - line_length = (((TLI_LxFLLEN(layerx) & TLI_LxFLLEN_FLL)-3U)/3U); - break; - case LAYER_PPF_RGB565: - case LAYER_PPF_ARGB1555: - case LAYER_PPF_ARGB4444: - case LAYER_PPF_AL88: - /* each pixel includes 2bytes,when pixel format is RGB565,ARG1555,ARGB4444 or AL88 */ - line_length = (((TLI_LxFLLEN(layerx) & TLI_LxFLLEN_FLL)-3U)/2U); - break; - case LAYER_PPF_L8: - case LAYER_PPF_AL44: - /* each pixel includes 1byte,when pixel format is L8 or AL44 */ - line_length = (((TLI_LxFLLEN(layerx) & TLI_LxFLLEN_FLL)-3U)); - break; - default: - break; + TLI_INTEN &= ~(int_flag); +} + +/*! + \brief get TLI interrupt flag + \param[in] int_flag: TLI interrupt flags + one or more parameters can be selected which are shown as below: + \arg TLI_INT_FLAG_LM: line mark interrupt flag + \arg TLI_INT_FLAG_FE: FIFO error interrupt flag + \arg TLI_INT_FLAG_TE: transaction error interrupt flag + \arg TLI_INT_FLAG_LCR: layer configuration reloaded interrupt flag + \param[out] none + \retval FlagStatus: SET or RESET +*/ +FlagStatus tli_interrupt_flag_get(uint32_t int_flag) +{ + uint32_t state; + state = TLI_INTF; + if(state & int_flag){ + state = TLI_INTEN; + if(state & int_flag){ + return SET; + } } - /* reconfigure window position */ - TLI_LxHPOS(layerx) = (hstart|((hstart+line_length-1U)<<16U)); - TLI_LxVPOS(layerx) = (vstart|((vstart+line_num-1U)<<16U)); - - + return RESET; } /*! - \brief TLI layer lut initialize - \param[in] layerx: LAYERx(x=0,1) - \param[in] lut_struct: TLI layer LUT parameter struct - layer_table_addr: window right position - layer_lut_channel_red: window left position - layer_window_bottompos: window bottom position - layer_window_toppos: window top position + \brief clear TLI interrupt flag + \param[in] int_flag: TLI interrupt flags + one or more parameters can be selected which are shown as below: + \arg TLI_INT_FLAG_LM: line mark interrupt flag + \arg TLI_INT_FLAG_FE: FIFO error interrupt flag + \arg TLI_INT_FLAG_TE: transaction error interrupt flag + \arg TLI_INT_FLAG_LCR: layer configuration reloaded interrupt flag \param[out] none \retval none */ -void tli_lut_init(uint32_t layerx,tli_layer_lut_parameter_struct *lut_struct) +void tli_interrupt_flag_clear(uint32_t int_flag) { - TLI_LxLUT(layerx) &= ~(TLI_LxLUT_TB|TLI_LxLUT_TG|TLI_LxLUT_TR|TLI_LxLUT_TADD); - TLI_LxLUT(layerx) = ((lut_struct->layer_lut_channel_blue)|(lut_struct->layer_lut_channel_green<<8) - |(lut_struct->layer_lut_channel_red<<16 - |(lut_struct->layer_table_addr<<24))); + TLI_INTC |= (int_flag); } /*! - \brief TLI layer key initialize - \param[in] layerx: LAYERx(x=0,1). - \param[in] redkey: color key red. - \param[in] greenkey: color key green - \param[in] bluekey: color key blue. + \brief get TLI flag or state in TLI_INTF register or TLI_STAT register + \param[in] flag: TLI flags or states + only one parameter can be selected which is shown as below: + \arg TLI_FLAG_VDE: current VDE state + \arg TLI_FLAG_HDE: current HDE state + \arg TLI_FLAG_VS: current VS status of the TLI + \arg TLI_FLAG_HS: current HS status of the TLI + \arg TLI_FLAG_LM: line mark interrupt flag + \arg TLI_FLAG_FE: FIFO error interrupt flag + \arg TLI_FLAG_TE: transaction error interrupt flag + \arg TLI_FLAG_LCR: layer configuration reloaded interrupt flag \param[out] none - \retval none + \retval FlagStatus: SET or RESET */ -void tli_ckey_init(uint32_t layerx,uint32_t redkey,uint32_t greenkey,uint32_t bluekey) +FlagStatus tli_flag_get(uint32_t flag) { - TLI_LxCKEY(layerx) = ((bluekey)|(greenkey<<8U)|(redkey<<16U)); + uint32_t stat; + /* choose which register to get flag or state */ + if(flag >> 31U){ + stat = TLI_INTF; + }else{ + stat = TLI_STAT; + } + if(flag & stat){ + return SET; + }else{ + return RESET; + } } diff --git a/bsp/gd32450z-eval/Libraries/GD32F4xx_standard_peripheral/Source/gd32f4xx_trng.c b/bsp/gd32450z-eval/Libraries/GD32F4xx_standard_peripheral/Source/gd32f4xx_trng.c index f0defdcd51..8c86bb832e 100644 --- a/bsp/gd32450z-eval/Libraries/GD32F4xx_standard_peripheral/Source/gd32f4xx_trng.c +++ b/bsp/gd32450z-eval/Libraries/GD32F4xx_standard_peripheral/Source/gd32f4xx_trng.c @@ -1,12 +1,37 @@ /*! - \file gd32f4xx_trng.c - \brief TRNG driver + \file gd32f4xx_trng.c + \brief TRNG driver + + \version 2016-08-15, V1.0.0, firmware for GD32F4xx + \version 2018-12-12, V2.0.0, firmware for GD32F4xx + \version 2020-09-30, V2.1.0, firmware for GD32F4xx */ /* - Copyright (C) 2016 GigaDevice + Copyright (c) 2020, GigaDevice Semiconductor Inc. + + Redistribution and use in source and binary forms, with or without modification, +are permitted provided that the following conditions are met: - 2016-08-15, V1.0.0, firmware for GD32F4xx + 1. Redistributions of source code must retain the above copyright notice, this + list of conditions and the following disclaimer. + 2. Redistributions in binary form must reproduce the above copyright notice, + this list of conditions and the following disclaimer in the documentation + and/or other materials provided with the distribution. + 3. Neither the name of the copyright holder nor the names of its contributors + may be used to endorse or promote products derived from this software without + specific prior written permission. + + THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED +WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. +IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, +INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT +NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR +PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, +WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY +OF SUCH DAMAGE. */ #include "gd32f4xx_trng.h" @@ -57,45 +82,12 @@ uint32_t trng_get_true_random_data(void) } /*! - \brief get the trng status flags - \param[in] flag: trng status flag, refer to trng_flag_enum - only one parameter can be selected which is shown as below: - \arg TRNG_FLAG_DRDY: Random Data ready status - \arg TRNG_FLAG_CECS: Clock error current status - \arg TRNG_FLAG_SECS: Seed error current status - \param[out] none - \retval FlagStatus: SET or RESET -*/ -FlagStatus trng_flag_get(trng_flag_enum flag) -{ - if(RESET != (TRNG_STAT & flag)){ - return SET; - }else{ - return RESET; - } -} - -/*! - \brief clear the trng status flags - \param[in] flag: the special status flag - only one parameter can be selected which is shown as below: - \arg TRNG_FLAG_CECS: Clock error current status - \arg TRNG_FLAG_SECS: Seed error current status - \param[out] none - \retval none -*/ -void trng_flag_clear(trng_flag_enum flag) -{ - TRNG_STAT &= ~(uint32_t)flag; -} - -/*! \brief enable the TRNG interrupt \param[in] none \param[out] none \retval none */ -void trng_interrupt_enable(void) +void trng_interrupt_enable(void) { TRNG_CTL |= TRNG_CTL_IE; } @@ -112,6 +104,25 @@ void trng_interrupt_disable(void) } /*! + \brief get the trng status flags + \param[in] flag: trng status flag, refer to trng_flag_enum + only one parameter can be selected which is shown as below: + \arg TRNG_FLAG_DRDY: Random Data ready status + \arg TRNG_FLAG_CECS: Clock error current status + \arg TRNG_FLAG_SECS: Seed error current status + \param[out] none + \retval FlagStatus: SET or RESET +*/ +FlagStatus trng_flag_get(trng_flag_enum flag) +{ + if(RESET != (TRNG_STAT & flag)){ + return SET; + }else{ + return RESET; + } +} + +/*! \brief get the trng interrupt flags \param[in] int_flag: trng interrupt flag, refer to trng_int_flag_enum only one parameter can be selected which is shown as below: diff --git a/bsp/gd32450z-eval/Libraries/GD32F4xx_standard_peripheral/Source/gd32f4xx_usart.c b/bsp/gd32450z-eval/Libraries/GD32F4xx_standard_peripheral/Source/gd32f4xx_usart.c index 945e60bc73..1b864e3b96 100644 --- a/bsp/gd32450z-eval/Libraries/GD32F4xx_standard_peripheral/Source/gd32f4xx_usart.c +++ b/bsp/gd32450z-eval/Libraries/GD32F4xx_standard_peripheral/Source/gd32f4xx_usart.c @@ -1,18 +1,49 @@ /*! - \file gd32f4xx_usart.c - \brief USART driver + \file gd32f4xx_usart.c + \brief USART driver + + \version 2016-08-15, V1.0.0, firmware for GD32F4xx + \version 2018-12-12, V2.0.0, firmware for GD32F4xx + \version 2020-09-30, V2.1.0, firmware for GD32F4xx */ /* - Copyright (C) 2016 GigaDevice + Copyright (c) 2020, GigaDevice Semiconductor Inc. + + Redistribution and use in source and binary forms, with or without modification, +are permitted provided that the following conditions are met: + + 1. Redistributions of source code must retain the above copyright notice, this + list of conditions and the following disclaimer. + 2. Redistributions in binary form must reproduce the above copyright notice, + this list of conditions and the following disclaimer in the documentation + and/or other materials provided with the distribution. + 3. Neither the name of the copyright holder nor the names of its contributors + may be used to endorse or promote products derived from this software without + specific prior written permission. - 2016-08-15, V1.0.0, firmware for GD32F4xx + THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED +WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. +IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, +INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT +NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR +PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, +WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY +OF SUCH DAMAGE. */ + #include "gd32f4xx_usart.h" +/* USART register bit offset */ +#define GP_GUAT_OFFSET ((uint32_t)8U) /* bit offset of GUAT in USART_GP */ +#define CTL3_SCRTNUM_OFFSET ((uint32_t)1U) /* bit offset of SCRTNUM in USART_CTL3 */ +#define RT_BL_OFFSET ((uint32_t)24U) /* bit offset of BL in USART_RT */ + /*! - \brief reset USART/UART + \brief reset USART/UART \param[in] usart_periph: USARTx(x=0,1,2,5)/UARTx(x=3,4,6,7) \param[out] none \retval none @@ -63,7 +94,7 @@ void usart_deinit(uint32_t usart_periph) \param[in] baudval: baud rate value \param[out] none \retval none -*/ +*/ void usart_baudrate_set(uint32_t usart_periph, uint32_t baudval) { uint32_t uclk=0U, intdiv=0U, fradiv=0U, udiv=0U; @@ -100,24 +131,25 @@ void usart_baudrate_set(uint32_t usart_periph, uint32_t baudval) /* when oversampling by 8, configure the value of USART_BAUD */ udiv = ((2U*uclk) + baudval/2U)/baudval; intdiv = udiv & 0xfff0U; - fradiv = udiv & 0x7U; - USART_BAUD(usart_periph) |= ((USART_BAUD_FRADIV | USART_BAUD_INTDIV) & (intdiv | fradiv)); + fradiv = (udiv>>1U) & 0x7U; + USART_BAUD(usart_periph) = ((USART_BAUD_FRADIV | USART_BAUD_INTDIV) & (intdiv | fradiv)); }else{ /* when oversampling by 16, configure the value of USART_BAUD */ udiv = (uclk+baudval/2U)/baudval; intdiv = udiv & 0xfff0U; fradiv = udiv & 0xfU; - USART_BAUD(usart_periph) |= ((USART_BAUD_FRADIV | USART_BAUD_INTDIV) & (intdiv | fradiv)); - } + USART_BAUD(usart_periph) = ((USART_BAUD_FRADIV | USART_BAUD_INTDIV) & (intdiv | fradiv)); + } } /*! \brief configure USART parity function \param[in] usart_periph: USARTx(x=0,1,2,5)/UARTx(x=3,4,6,7) \param[in] paritycfg: configure USART parity + only one parameter can be selected which is shown as below: \arg USART_PM_NONE: no parity + \arg USART_PM_EVEN: even parity \arg USART_PM_ODD: odd parity - \arg USART_PM_EVEN: even parity \param[out] none \retval none */ @@ -133,6 +165,7 @@ void usart_parity_config(uint32_t usart_periph, uint32_t paritycfg) \brief configure USART word length \param[in] usart_periph: USARTx(x=0,1,2,5)/UARTx(x=3,4,6,7) \param[in] wlen: USART word length configure + only one parameter can be selected which is shown as below: \arg USART_WL_8BIT: 8 bits \arg USART_WL_9BIT: 9 bits \param[out] none @@ -150,17 +183,18 @@ void usart_word_length_set(uint32_t usart_periph, uint32_t wlen) \brief configure USART stop bit length \param[in] usart_periph: USARTx(x=0,1,2,5)/UARTx(x=3,4,6,7) \param[in] stblen: USART stop bit configure + only one parameter can be selected which is shown as below: \arg USART_STB_1BIT: 1 bit - \arg USART_STB_0_5BIT: 0.5 bit + \arg USART_STB_0_5BIT: 0.5 bit(not available for UARTx(x=3,4,6,7)) \arg USART_STB_2BIT: 2 bits - \arg USART_STB_1_5BIT: 1.5 bits + \arg USART_STB_1_5BIT: 1.5 bits(not available for UARTx(x=3,4,6,7)) \param[out] none \retval none */ void usart_stop_bit_set(uint32_t usart_periph, uint32_t stblen) { /* clear USART_CTL1 STB bits */ - USART_CTL1(usart_periph) &= ~USART_CTL1_STB; + USART_CTL1(usart_periph) &= ~USART_CTL1_STB; /* configure USART stop bits */ USART_CTL1(usart_periph) |= stblen; } @@ -189,7 +223,8 @@ void usart_disable(uint32_t usart_periph) /*! \brief configure USART transmitter \param[in] usart_periph: USARTx(x=0,1,2,5)/UARTx(x=3,4,6,7) - \param[in] rtconfig: enable or disable USART transmitter + \param[in] txconfig: enable or disable USART transmitter + only one parameter can be selected which is shown as below: \arg USART_TRANSMIT_ENABLE: enable USART transmission \arg USART_TRANSMIT_DISABLE: enable USART transmission \param[out] none @@ -198,7 +233,7 @@ void usart_disable(uint32_t usart_periph) void usart_transmit_config(uint32_t usart_periph, uint32_t txconfig) { uint32_t ctl = 0U; - + ctl = USART_CTL0(usart_periph); ctl &= ~USART_CTL0_TEN; ctl |= txconfig; @@ -209,7 +244,8 @@ void usart_transmit_config(uint32_t usart_periph, uint32_t txconfig) /*! \brief configure USART receiver \param[in] usart_periph: USARTx(x=0,1,2,5)/UARTx(x=3,4,6,7) - \param[in] rtconfig: enable or disable USART receiver + \param[in] rxconfig: enable or disable USART receiver + only one parameter can be selected which is shown as below: \arg USART_RECEIVE_ENABLE: enable USART reception \arg USART_RECEIVE_DISABLE: disable USART reception \param[out] none @@ -218,7 +254,7 @@ void usart_transmit_config(uint32_t usart_periph, uint32_t txconfig) void usart_receive_config(uint32_t usart_periph, uint32_t rxconfig) { uint32_t ctl = 0U; - + ctl = USART_CTL0(usart_periph); ctl &= ~USART_CTL0_REN; ctl |= rxconfig; @@ -230,6 +266,7 @@ void usart_receive_config(uint32_t usart_periph, uint32_t rxconfig) \brief data is transmitted/received with the LSB/MSB first \param[in] usart_periph: USARTx(x=0,1,2,5) \param[in] msbf: LSB/MSB + only one parameter can be selected which is shown as below: \arg USART_MSBF_LSB: LSB first \arg USART_MSBF_MSB: MSB first \param[out] none @@ -237,14 +274,20 @@ void usart_receive_config(uint32_t usart_periph, uint32_t rxconfig) */ void usart_data_first_config(uint32_t usart_periph, uint32_t msbf) { - USART_CTL3(usart_periph) &= ~(USART_CTL3_MSBF); - USART_CTL3(usart_periph) |= msbf; + uint32_t ctl = 0U; + + ctl = USART_CTL3(usart_periph); + ctl &= ~(USART_CTL3_MSBF); + ctl |= msbf; + /* configure data transmitted/received mode */ + USART_CTL3(usart_periph) = ctl; } /*! \brief configure USART inversion \param[in] usart_periph: USARTx(x=0,1,2,5) \param[in] invertpara: refer to enum USART_INVERT_CONFIG + only one parameter can be selected which is shown as below: \arg USART_DINV_ENABLE: data bit level inversion \arg USART_DINV_DISABLE: data bit level not inversion \arg USART_TXPIN_ENABLE: TX pin level inversion @@ -256,7 +299,7 @@ void usart_data_first_config(uint32_t usart_periph, uint32_t msbf) */ void usart_invert_config(uint32_t usart_periph, usart_invert_enum invertpara) { - /* inverted or not the specified siginal */ + /* inverted or not the specified siginal */ switch(invertpara){ case USART_DINV_ENABLE: USART_CTL3(usart_periph) |= USART_CTL3_DINV; @@ -282,9 +325,10 @@ void usart_invert_config(uint32_t usart_periph, usart_invert_enum invertpara) } /*! - \brief configure the USART oversample mode + \brief configure the USART oversample mode \param[in] usart_periph: USARTx(x=0,1,2,5)/UARTx(x=3,4,6,7) \param[in] oversamp: oversample value + only one parameter can be selected which is shown as below: \arg USART_OVSMOD_8: 8 bits \arg USART_OVSMOD_16: 16 bits \param[out] none @@ -301,6 +345,7 @@ void usart_oversample_config(uint32_t usart_periph, uint32_t oversamp) \brief configure sample bit method \param[in] usart_periph: USARTx(x=0,1,2,5)/UARTx(x=3,4,6,7) \param[in] obsm: sample bit + only one parameter can be selected which is shown as below: \arg USART_OSB_1bit: 1 bit \arg USART_OSB_3bit: 3 bits \param[out] none @@ -308,7 +353,7 @@ void usart_oversample_config(uint32_t usart_periph, uint32_t oversamp) */ void usart_sample_bit_config(uint32_t usart_periph, uint32_t obsm) { - USART_CTL2(usart_periph) &= ~(USART_CTL2_OSB); + USART_CTL2(usart_periph) &= ~(USART_CTL2_OSB); USART_CTL2(usart_periph) |= obsm; } @@ -350,7 +395,7 @@ void usart_receiver_timeout_threshold_config(uint32_t usart_periph, uint32_t rti /*! \brief USART transmit data function \param[in] usart_periph: USARTx(x=0,1,2,5)/UARTx(x=3,4,6,7) - \param[in] data: data of transmission + \param[in] data: data of transmission \param[out] none \retval none */ @@ -367,7 +412,7 @@ void usart_data_transmit(uint32_t usart_periph, uint32_t data) */ uint16_t usart_data_receive(uint32_t usart_periph) { - return (uint16_t)(USART_DATA(usart_periph) & (uint16_t)USART_DATA_DATA); + return (uint16_t)(GET_BITS(USART_DATA(usart_periph), 0U, 8U)); } /*! @@ -384,7 +429,7 @@ void usart_address_config(uint32_t usart_periph, uint8_t addr) } /*! - \brief receiver in mute mode + \brief enable mute mode \param[in] usart_periph: USARTx(x=0,1,2,5)/UARTx(x=3,4,6,7) \param[out] none \retval none @@ -395,7 +440,7 @@ void usart_mute_mode_enable(uint32_t usart_periph) } /*! - \brief receiver in active mode + \brief disable mute mode \param[in] usart_periph: USARTx(x=0,1,2,5)/UARTx(x=3,4,6,7) \param[out] none \retval none @@ -409,6 +454,7 @@ void usart_mute_mode_disable(uint32_t usart_periph) \brief configure wakeup method in mute mode \param[in] usart_periph: USARTx(x=0,1,2,5)/UARTx(x=3,4,6,7) \param[in] wmehtod: two method be used to enter or exit the mute mode + only one parameter can be selected which is shown as below: \arg USART_WM_IDLE: idle line \arg USART_WM_ADDR: address mask \param[out] none @@ -427,7 +473,7 @@ void usart_mute_mode_wakeup_config(uint32_t usart_periph, uint32_t wmehtod) \retval none */ void usart_lin_mode_enable(uint32_t usart_periph) -{ +{ USART_CTL1(usart_periph) |= USART_CTL1_LMEN; } @@ -438,7 +484,7 @@ void usart_lin_mode_enable(uint32_t usart_periph) \retval none */ void usart_lin_mode_disable(uint32_t usart_periph) -{ +{ USART_CTL1(usart_periph) &= ~(USART_CTL1_LMEN); } @@ -446,12 +492,13 @@ void usart_lin_mode_disable(uint32_t usart_periph) \brief configure lin break frame length \param[in] usart_periph: USARTx(x=0,1,2,5)/UARTx(x=3,4,6,7) \param[in] lblen: lin break frame length + only one parameter can be selected which is shown as below: \arg USART_LBLEN_10B: 10 bits \arg USART_LBLEN_11B: 11 bits \param[out] none \retval none */ -void usart_lin_break_dection_length_config(uint32_t usart_periph, uint32_t lblen) +void usart_lin_break_detection_length_config(uint32_t usart_periph, uint32_t lblen) { USART_CTL1(usart_periph) &= ~(USART_CTL1_LBLEN); USART_CTL1(usart_periph) |= (USART_CTL1_LBLEN & lblen); @@ -475,7 +522,7 @@ void usart_send_break(uint32_t usart_periph) \retval none */ void usart_halfduplex_enable(uint32_t usart_periph) -{ +{ USART_CTL2(usart_periph) |= USART_CTL2_HDEN; } @@ -486,7 +533,7 @@ void usart_halfduplex_enable(uint32_t usart_periph) \retval none */ void usart_halfduplex_disable(uint32_t usart_periph) -{ +{ USART_CTL2(usart_periph) &= ~(USART_CTL2_HDEN); } @@ -516,13 +563,16 @@ void usart_synchronous_clock_disable(uint32_t usart_periph) \brief configure USART synchronous mode parameters \param[in] usart_periph: USARTx(x=0,1,2,5) \param[in] clen: CK length - \arg USART_CLEN_NONE: there are 7 CK pulses for an 8 bit frame and 8 CK pulses for a 9 bit frame + only one parameter can be selected which is shown as below: + \arg USART_CLEN_NONE: there are 7 CK pulses for an 8 bit frame and 8 CK pulses for a 9 bit frame \arg USART_CLEN_EN: there are 8 CK pulses for an 8 bit frame and 9 CK pulses for a 9 bit frame \param[in] cph: clock phase - \arg USART_CPH_1CK: first clock transition is the first data capture edge + only one parameter can be selected which is shown as below: + \arg USART_CPH_1CK: first clock transition is the first data capture edge \arg USART_CPH_2CK: second clock transition is the first data capture edge - \param[in] cpl: clock polarity - \arg USART_CPL_LOW: steady low value on CK pin + \param[in] cpl: clock polarity + only one parameter can be selected which is shown as below: + \arg USART_CPL_LOW: steady low value on CK pin \arg USART_CPL_HIGH: steady high value on CK pin \param[out] none \retval none @@ -530,26 +580,27 @@ void usart_synchronous_clock_disable(uint32_t usart_periph) void usart_synchronous_clock_config(uint32_t usart_periph, uint32_t clen, uint32_t cph, uint32_t cpl) { uint32_t ctl = 0U; - + /* read USART_CTL1 register */ ctl = USART_CTL1(usart_periph); + ctl &= ~(USART_CTL1_CLEN | USART_CTL1_CPH | USART_CTL1_CPL); /* set CK length, CK phase, CK polarity */ ctl |= (USART_CTL1_CLEN & clen) | (USART_CTL1_CPH & cph) | (USART_CTL1_CPL & cpl); - USART_CTL1(usart_periph) |= ctl; + USART_CTL1(usart_periph) = ctl; } /*! \brief configure guard time value in smartcard mode \param[in] usart_periph: USARTx(x=0,1,2,5) - \param[in] gaut: guard time value + \param[in] guat: guard time value, 0-0xFF \param[out] none \retval none */ -void usart_guard_time_config(uint32_t usart_periph,uint32_t gaut) +void usart_guard_time_config(uint32_t usart_periph,uint32_t guat) { USART_GP(usart_periph) &= ~(USART_GP_GUAT); - USART_GP(usart_periph) |= (USART_GP_GUAT & ((gaut)<<8)); + USART_GP(usart_periph) |= (USART_GP_GUAT & ((guat)<<GP_GUAT_OFFSET)); } /*! @@ -606,7 +657,7 @@ void usart_smartcard_mode_nack_disable(uint32_t usart_periph) void usart_smartcard_autoretry_config(uint32_t usart_periph, uint32_t scrtnum) { USART_CTL3(usart_periph) &= ~(USART_CTL3_SCRTNUM); - USART_CTL3(usart_periph) |= (USART_CTL3_SCRTNUM & ((scrtnum)<<1)); + USART_CTL3(usart_periph) |= (USART_CTL3_SCRTNUM & ((scrtnum)<<CTL3_SCRTNUM_OFFSET)); } /*! @@ -619,7 +670,7 @@ void usart_smartcard_autoretry_config(uint32_t usart_periph, uint32_t scrtnum) void usart_block_length_config(uint32_t usart_periph, uint32_t bl) { USART_RT(usart_periph) &= ~(USART_RT_BL); - USART_RT(usart_periph) |= (USART_RT_BL & ((bl)<<24)); + USART_RT(usart_periph) |= (USART_RT_BL & ((bl)<<RT_BL_OFFSET)); } /*! @@ -647,11 +698,11 @@ void usart_irda_mode_disable(uint32_t usart_periph) /*! \brief configure the peripheral clock prescaler in USART IrDA low-power mode \param[in] usart_periph: USARTx(x=0,1,2,5)/UARTx(x=3,4,6,7) - \param[in] psc: 0-0x00FFFFFF + \param[in] psc: 0-0xFF \param[out] none \retval none */ -void usart_prescaler_config(uint32_t usart_periph, uint32_t psc) +void usart_prescaler_config(uint32_t usart_periph, uint8_t psc) { USART_GP(usart_periph) &= ~(USART_GP_PSC); USART_GP(usart_periph) |= psc; @@ -661,7 +712,8 @@ void usart_prescaler_config(uint32_t usart_periph, uint32_t psc) \brief configure IrDA low-power \param[in] usart_periph: USARTx(x=0,1,2,5)/UARTx(x=3,4,6,7) \param[in] irlp: IrDA low-power or normal - \arg USART_IRLP_LOW: low-power + only one parameter can be selected which is shown as below: + \arg USART_IRLP_LOW: low-power \arg USART_IRLP_NORMAL: normal \param[out] none \retval none @@ -675,7 +727,8 @@ void usart_irda_lowpower_config(uint32_t usart_periph, uint32_t irlp) /*! \brief configure hardware flow control RTS \param[in] usart_periph: USARTx(x=0,1,2,5) - \param[in] hardwareflow: enable or disable RTS + \param[in] rtsconfig: enable or disable RTS + only one parameter can be selected which is shown as below: \arg USART_RTS_ENABLE: enable RTS \arg USART_RTS_DISABLE: disable RTS \param[out] none @@ -684,7 +737,7 @@ void usart_irda_lowpower_config(uint32_t usart_periph, uint32_t irlp) void usart_hardware_flow_rts_config(uint32_t usart_periph, uint32_t rtsconfig) { uint32_t ctl = 0U; - + ctl = USART_CTL2(usart_periph); ctl &= ~USART_CTL2_RTSEN; ctl |= rtsconfig; @@ -695,7 +748,8 @@ void usart_hardware_flow_rts_config(uint32_t usart_periph, uint32_t rtsconfig) /*! \brief configure hardware flow control CTS \param[in] usart_periph: USARTx(x=0,1,2,5) - \param[in] hardwareflow: enable or disable CTS + \param[in] ctsconfig: enable or disable CTS + only one parameter can be selected which is shown as below: \arg USART_CTS_ENABLE: enable CTS \arg USART_CTS_DISABLE: disable CTS \param[out] none @@ -704,7 +758,7 @@ void usart_hardware_flow_rts_config(uint32_t usart_periph, uint32_t rtsconfig) void usart_hardware_flow_cts_config(uint32_t usart_periph, uint32_t ctsconfig) { uint32_t ctl = 0U; - + ctl = USART_CTL2(usart_periph); ctl &= ~USART_CTL2_CTSEN; ctl |= ctsconfig; @@ -715,7 +769,8 @@ void usart_hardware_flow_cts_config(uint32_t usart_periph, uint32_t ctsconfig) /*! \brief configure break frame coherence mode \param[in] usart_periph: USARTx(x=0,1,2,5) - \param[in] bcm: + \param[in] bcm: + only one parameter can be selected which is shown as below: \arg USART_BCM_NONE: no parity error is detected \arg USART_BCM_EN: parity error is detected \param[out] none @@ -730,7 +785,8 @@ void usart_break_frame_coherence_config(uint32_t usart_periph, uint32_t bcm) /*! \brief configure parity check coherence mode \param[in] usart_periph: USARTx(x=0,1,2,5)/UARTx(x=3,4,6,7) - \param[in] pcm: + \param[in] pcm: + only one parameter can be selected which is shown as below: \arg USART_PCM_NONE: not check parity \arg USART_PCM_EN: check the parity \param[out] none @@ -745,7 +801,8 @@ void usart_parity_check_coherence_config(uint32_t usart_periph, uint32_t pcm) /*! \brief configure hardware flow control coherence mode \param[in] usart_periph: USARTx(x=0,1,2,5) - \param[in] hcm: + \param[in] hcm: + only one parameter can be selected which is shown as below: \arg USART_HCM_NONE: nRTS signal equals to the rxne status register \arg USART_HCM_EN: nRTS signal is set when the last data bit has been sampled \param[out] none @@ -761,6 +818,7 @@ void usart_hardware_flow_coherence_config(uint32_t usart_periph, uint32_t hcm) \brief configure USART DMA reception \param[in] usart_periph: USARTx(x=0,1,2,5)/UARTx(x=3,4,6,7) \param[in] dmacmd: enable or disable DMA for reception + only one parameter can be selected which is shown as below: \arg USART_DENR_ENABLE: DMA enable for reception \arg USART_DENR_DISABLE: DMA disable for reception \param[out] none @@ -769,7 +827,7 @@ void usart_hardware_flow_coherence_config(uint32_t usart_periph, uint32_t hcm) void usart_dma_receive_config(uint32_t usart_periph, uint32_t dmacmd) { uint32_t ctl = 0U; - + ctl = USART_CTL2(usart_periph); ctl &= ~USART_CTL2_DENR; ctl |= dmacmd; @@ -781,6 +839,7 @@ void usart_dma_receive_config(uint32_t usart_periph, uint32_t dmacmd) \brief configure USART DMA transmission \param[in] usart_periph: USARTx(x=0,1,2,5)/UARTx(x=3,4,6,7) \param[in] dmacmd: enable or disable DMA for transmission + only one parameter can be selected which is shown as below: \arg USART_DENT_ENABLE: DMA enable for transmission \arg USART_DENT_DISABLE: DMA disable for transmission \param[out] none @@ -789,7 +848,7 @@ void usart_dma_receive_config(uint32_t usart_periph, uint32_t dmacmd) void usart_dma_transmit_config(uint32_t usart_periph, uint32_t dmacmd) { uint32_t ctl = 0U; - + ctl = USART_CTL2(usart_periph); ctl &= ~USART_CTL2_DENT; ctl |= dmacmd; @@ -801,19 +860,20 @@ void usart_dma_transmit_config(uint32_t usart_periph, uint32_t dmacmd) \brief get flag in STAT0/STAT1/CHC register \param[in] usart_periph: USARTx(x=0,1,2,5)/UARTx(x=3,4,6,7) \param[in] flag: USART flags, refer to usart_flag_enum - \arg USART_FLAG_CTSF: CTS change flag - \arg USART_FLAG_LBDF: LIN break detected flag - \arg USART_FLAG_TBE: transmit data buffer empty - \arg USART_FLAG_TC: transmission complete - \arg USART_FLAG_RBNE: read data buffer not empty - \arg USART_FLAG_IDLEF: IDLE frame detected flag - \arg USART_FLAG_ORERR: overrun error - \arg USART_FLAG_NERR: noise error flag - \arg USART_FLAG_FERR: frame error flag - \arg USART_FLAG_PERR: parity error flag - \arg USART_FLAG_BSY: busy flag - \arg USART_FLAG_EBF: end of block flag - \arg USART_FLAG_RTF: receiver timeout flag + only one parameter can be selected which is shown as below: + \arg USART_FLAG_CTS: CTS change flag + \arg USART_FLAG_LBD: LIN break detected flag + \arg USART_FLAG_TBE: transmit data buffer empty + \arg USART_FLAG_TC: transmission complete + \arg USART_FLAG_RBNE: read data buffer not empty + \arg USART_FLAG_IDLE: IDLE frame detected flag + \arg USART_FLAG_ORERR: overrun error + \arg USART_FLAG_NERR: noise error flag + \arg USART_FLAG_FERR: frame error flag + \arg USART_FLAG_PERR: parity error flag + \arg USART_FLAG_BSY: busy flag + \arg USART_FLAG_EB: end of block flag + \arg USART_FLAG_RT: receiver timeout flag \arg USART_FLAG_EPERR: early parity error flag \param[out] none \retval FlagStatus: SET or RESET @@ -831,12 +891,13 @@ FlagStatus usart_flag_get(uint32_t usart_periph, usart_flag_enum flag) \brief clear flag in STAT0/STAT1/CHC register \param[in] usart_periph: USARTx(x=0,1,2,5)/UARTx(x=3,4,6,7) \param[in] flag: USART flags, refer to usart_flag_enum - \arg USART_FLAG_CTSF: CTS change flag - \arg USART_FLAG_LBDF: LIN break detected flag + only one parameter can be selected which is shown as below: + \arg USART_FLAG_CTS: CTS change flag + \arg USART_FLAG_LBD: LIN break detected flag \arg USART_FLAG_TC: transmission complete \arg USART_FLAG_RBNE: read data buffer not empty - \arg USART_FLAG_EBF: end of block flag - \arg USART_FLAG_RTF: receiver timeout flag + \arg USART_FLAG_EB: end of block flag + \arg USART_FLAG_RT: receiver timeout flag \arg USART_FLAG_EPERR: early parity error flag \param[out] none \retval none @@ -848,105 +909,101 @@ void usart_flag_clear(uint32_t usart_periph, usart_flag_enum flag) /*! \brief enable USART interrupt - \param[in] usart_periph: USARTx(x=0,1,2,5)/UARTx(x=3,4,6,7) - \param[in] int_flag - \arg USART_INTEN_PERRIE: parity error interrupt - \arg USART_INTEN_TBEIE: transmitter buffer empty interrupt - \arg USART_INTEN_TCIE: transmission complete interrupt - \arg USART_INTEN_RBNEIE: read data buffer not empty interrupt and overrun error interrupt - \arg USART_INTEN_IDLEIE: IDLE line detected interrupt - \arg USART_INTEN_LBDIE: LIN break detected interrupt - \arg USART_INTEN_ERRIE: error interrupt - \arg USART_INTEN_CTSIE: CTS interrupt - \arg USART_INTEN_RTIE: interrupt enable bit of receive timeout event - \arg USART_INTEN_EBIE: interrupt enable bit of end of block event + \param[in] usart_periph: USARTx(x=0,1,2,5)/UARTx(x=3,4,6,7) + \param[in] interrupt: USART interrupts, refer to usart_interrupt_enum + only one parameter can be selected which is shown as below: + \arg USART_INT_PERR: parity error interrupt + \arg USART_INT_TBE: transmitter buffer empty interrupt + \arg USART_INT_TC: transmission complete interrupt + \arg USART_INT_RBNE: read data buffer not empty interrupt and overrun error interrupt + \arg USART_INT_IDLE: IDLE line detected interrupt + \arg USART_INT_LBD: LIN break detected interrupt + \arg USART_INT_ERR: error interrupt + \arg USART_INT_CTS: CTS interrupt + \arg USART_INT_RT: interrupt enable bit of receive timeout event + \arg USART_INT_EB: interrupt enable bit of end of block event \param[out] none + \retval none */ -void usart_interrupt_enable(uint32_t usart_periph, uint32_t int_flag) +void usart_interrupt_enable(uint32_t usart_periph, usart_interrupt_enum interrupt) { - uint32_t usart_reg = 0U; - - usart_reg = int_flag & (~(uint32_t)USART_INTEN_MASK); - int_flag &= USART_INTEN_MASK; - /* flags in USART_CTL0 */ - if(USART_INTS_CTL0 == usart_reg){ - USART_CTL0(usart_periph) |= int_flag; - /* flags in USART_CTL1 */ - }else if(USART_INTS_CTL1 == usart_reg){ - USART_CTL1(usart_periph) |= int_flag; - /* flags in USART_CTL2 */ - }else if(USART_INTS_CTL2 == usart_reg){ - USART_CTL2(usart_periph) |= int_flag; - /* flags in USART_CTL3 */ - }else if(USART_INTS_CTL3 == usart_reg){ - USART_CTL3(usart_periph) |= int_flag; - }else{ - /* illegal parameters */ - } + USART_REG_VAL(usart_periph, interrupt) |= BIT(USART_BIT_POS(interrupt)); } /*! \brief disable USART interrupt - \param[in] usart_periph: USARTx(x=0,1,2,5)/UARTx(x=3,4,6,7) - \param[in] int_flag - \arg USART_INTEN_PERRIE: parity error interrupt - \arg USART_INTEN_TBEIE: transmitter buffer empty interrupt - \arg USART_INTEN_TCIE: transmission complete interrupt - \arg USART_INTEN_RBNEIE: read data buffer not empty interrupt and overrun error interrupt - \arg USART_INTEN_IDLEIE: IDLE line detected interrupt - \arg USART_INTEN_LBDIE: LIN break detected interrupt - \arg USART_INTEN_ERRIE: error interrupt - \arg USART_INTEN_CTSIE: CTS interrupt - \arg USART_INTEN_RTIE: interrupt enable bit of receive timeout event - \arg USART_INTEN_EBIE: interrupt enable bit of end of block event + \param[in] usart_periph: USARTx(x=0,1,2,5)/UARTx(x=3,4,6,7) + \param[in] interrupt: USART interrupts, refer to usart_interrupt_enum + only one parameter can be selected which is shown as below: + \arg USART_INT_PERR: parity error interrupt + \arg USART_INT_TBE: transmitter buffer empty interrupt + \arg USART_INT_TC: transmission complete interrupt + \arg USART_INT_RBNE: read data buffer not empty interrupt and overrun error interrupt + \arg USART_INT_IDLE: IDLE line detected interrupt + \arg USART_INT_LBD: LIN break detected interrupt + \arg USART_INT_ERR: error interrupt + \arg USART_INT_CTS: CTS interrupt + \arg USART_INT_RT: interrupt enable bit of receive timeout event + \arg USART_INT_EB: interrupt enable bit of end of block event \param[out] none + \retval none */ -void usart_interrupt_disable(uint32_t usart_periph, uint32_t int_flag) +void usart_interrupt_disable(uint32_t usart_periph, usart_interrupt_enum interrupt) { - uint32_t usart_reg = 0U; - - usart_reg = int_flag & (~(uint32_t)USART_INTEN_MASK); - int_flag &= USART_INTEN_MASK; - /* flags in USART_CTL0 */ - if(USART_INTS_CTL0 == usart_reg){ - USART_CTL0(usart_periph) &= ~(int_flag); - /* flags in USART_CTL1 */ - }else if(USART_INTS_CTL1 == usart_reg){ - USART_CTL1(usart_periph) &= ~(int_flag); - /* flags in USART_CTL2 */ - }else if(USART_INTS_CTL2 == usart_reg){ - USART_CTL2(usart_periph) &= ~(int_flag); - /* flags in USART_CTL3 */ - }else if(USART_INTS_CTL3 == usart_reg){ - USART_CTL3(usart_periph) &= ~(int_flag); - }else{ - /* illegal parameters */ - } + USART_REG_VAL(usart_periph, interrupt) &= ~BIT(USART_BIT_POS(interrupt)); } /*! - \brief get USART interrupt enable flag - \param[in] usart_periph: USARTx(x=0,1,2,5)/UARTx(x=3,4,6,7) - \param[in] int_flag - \arg USART_INT_PERRIE: parity error interrupt - \arg USART_INT_TBEIE: transmitter buffer empty interrupt - \arg USART_INT_TCIE: transmission complete interrupt - \arg USART_INT_RBNEIE: read data buffer not empty interrupt and overrun error interrupt - \arg USART_INT_IDLEIE: IDLE line detected interrupt - \arg USART_INT_LBDIE: LIN break detected interrupt - \arg USART_INT_CTSIE: CTS interrupt - \arg USART_INT_ERRIE: error interrupt - \arg USART_INT_EBIE: interrupt enable bit of end of block event - \arg USART_INT_RTIE: interrupt enable bit of receive timeout event + \brief get USART interrupt and flag status + \param[in] usart_periph: USARTx(x=0,1,2,5)/UARTx(x=3,4,6,7) + \param[in] int_flag: USART interrupt flags, refer to usart_interrupt_flag_enum + only one parameter can be selected which is shown as below: + \arg USART_INT_FLAG_PERR: parity error interrupt and flag + \arg USART_INT_FLAG_TBE: transmitter buffer empty interrupt and flag + \arg USART_INT_FLAG_TC: transmission complete interrupt and flag + \arg USART_INT_FLAG_RBNE: read data buffer not empty interrupt and flag + \arg USART_INT_FLAG_RBNE_ORERR: read data buffer not empty interrupt and overrun error flag + \arg USART_INT_FLAG_IDLE: IDLE line detected interrupt and flag + \arg USART_INT_FLAG_LBD: LIN break detected interrupt and flag + \arg USART_INT_FLAG_CTS: CTS interrupt and flag + \arg USART_INT_FLAG_ERR_ORERR: error interrupt and overrun error + \arg USART_INT_FLAG_ERR_NERR: error interrupt and noise error flag + \arg USART_INT_FLAG_ERR_FERR: error interrupt and frame error flag + \arg USART_INT_FLAG_EB: interrupt enable bit of end of block event and flag + \arg USART_INT_FLAG_RT: interrupt enable bit of receive timeout event and flag \param[out] none - \retval FlagStatus + \retval FlagStatus: SET or RESET */ -FlagStatus usart_interrupt_flag_get(uint32_t usart_periph, uint32_t int_flag) +FlagStatus usart_interrupt_flag_get(uint32_t usart_periph, usart_interrupt_flag_enum int_flag) { - if(RESET != (USART_REG_VAL(usart_periph, int_flag) & BIT(USART_BIT_POS(int_flag)))){ + uint32_t intenable = 0U, flagstatus = 0U; + /* get the interrupt enable bit status */ + intenable = (USART_REG_VAL(usart_periph, int_flag) & BIT(USART_BIT_POS(int_flag))); + /* get the corresponding flag bit status */ + flagstatus = (USART_REG_VAL2(usart_periph, int_flag) & BIT(USART_BIT_POS2(int_flag))); + + if((0U != flagstatus) && (0U != intenable)){ return SET; }else{ return RESET; } } +/*! + \brief clear USART interrupt flag in STAT0/STAT1 register + \param[in] usart_periph: USARTx(x=0,1,2,5)/UARTx(x=3,4,6,7) + \param[in] int_flag: USART interrupt flags, refer to usart_interrupt_flag_enum + only one parameter can be selected which is shown as below: + \arg USART_INT_FLAG_CTS: CTS change flag + \arg USART_INT_FLAG_LBD: LIN break detected flag + \arg USART_INT_FLAG_TC: transmission complete + \arg USART_INT_FLAG_RBNE: read data buffer not empty + \arg USART_INT_FLAG_EB: end of block flag + \arg USART_INT_FLAG_RT: receiver timeout flag + \param[out] none + \retval none +*/ +void usart_interrupt_flag_clear(uint32_t usart_periph, usart_interrupt_flag_enum int_flag) +{ + USART_REG_VAL2(usart_periph, int_flag) &= ~BIT(USART_BIT_POS2(int_flag)); +} diff --git a/bsp/gd32450z-eval/Libraries/GD32F4xx_standard_peripheral/Source/gd32f4xx_wwdgt.c b/bsp/gd32450z-eval/Libraries/GD32F4xx_standard_peripheral/Source/gd32f4xx_wwdgt.c index 94a50ac996..e788c26614 100644 --- a/bsp/gd32450z-eval/Libraries/GD32F4xx_standard_peripheral/Source/gd32f4xx_wwdgt.c +++ b/bsp/gd32450z-eval/Libraries/GD32F4xx_standard_peripheral/Source/gd32f4xx_wwdgt.c @@ -1,12 +1,37 @@ /*! - \file gd32f4xx_wwdgt.c - \brief WWDGT driver + \file gd32f4xx_wwdgt.c + \brief WWDGT driver + + \version 2016-08-15, V1.0.0, firmware for GD32F4xx + \version 2018-12-12, V2.0.0, firmware for GD32F4xx + \version 2020-09-30, V2.1.0, firmware for GD32F4xx */ /* - Copyright (C) 2016 GigaDevice + Copyright (c) 2020, GigaDevice Semiconductor Inc. + + Redistribution and use in source and binary forms, with or without modification, +are permitted provided that the following conditions are met: - 2016-08-15, V1.0.0, firmware for GD32F4xx + 1. Redistributions of source code must retain the above copyright notice, this + list of conditions and the following disclaimer. + 2. Redistributions in binary form must reproduce the above copyright notice, + this list of conditions and the following disclaimer in the documentation + and/or other materials provided with the distribution. + 3. Neither the name of the copyright holder nor the names of its contributors + may be used to endorse or promote products derived from this software without + specific prior written permission. + + THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED +WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. +IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, +INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT +NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR +PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, +WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY +OF SUCH DAMAGE. */ #include "gd32f4xx_wwdgt.h" @@ -29,37 +54,38 @@ void wwdgt_deinit(void) } /*! - \brief configure the window watchdog timer counter value - \param[in] counter_value: 0x00 - 0x7F + \brief start the window watchdog timer counter + \param[in] none \param[out] none \retval none */ -void wwdgt_counter_update(uint16_t counter_value) +void wwdgt_enable(void) { - uint32_t reg = 0U; - - reg = (WWDGT_CTL & (~WWDGT_CTL_CNT)); - reg |= CTL_CNT(counter_value); - - WWDGT_CTL = reg; + WWDGT_CTL |= WWDGT_CTL_WDGTEN; } /*! - \brief start the window watchdog timer counter - \param[in] none + \brief configure the window watchdog timer counter value + \param[in] counter_value: 0x00 - 0x7F \param[out] none \retval none */ -void wwdgt_enable(void) +void wwdgt_counter_update(uint16_t counter_value) { - WWDGT_CTL |= WWDGT_CTL_WDGTEN; + uint32_t reg = 0U; + + reg = (WWDGT_CTL & (~WWDGT_CTL_CNT)); + reg |= CTL_CNT(counter_value); + + WWDGT_CTL = reg; } /*! - \brief configure counter value, window value, and prescaler divider value - \param[in] counter: 0x00 - 0x7F + \brief configure counter value, window value, and prescaler divider value + \param[in] counter: 0x00 - 0x7F \param[in] window: 0x00 - 0x7F \param[in] prescaler: wwdgt prescaler value + only one parameter can be selected which is shown as below: \arg WWDGT_CFG_PSC_DIV1: the time base of window watchdog counter = (PCLK1/4096)/1 \arg WWDGT_CFG_PSC_DIV2: the time base of window watchdog counter = (PCLK1/4096)/2 \arg WWDGT_CFG_PSC_DIV4: the time base of window watchdog counter = (PCLK1/4096)/4 @@ -74,12 +100,12 @@ void wwdgt_config(uint16_t counter, uint16_t window, uint32_t prescaler) /* clear WIN and PSC bits, clear CNT bit */ reg_cfg = (WWDGT_CFG &(~(WWDGT_CFG_WIN|WWDGT_CFG_PSC))); reg_ctl = (WWDGT_CTL &(~WWDGT_CTL_CNT)); - + /* configure WIN and PSC bits, configure CNT bit */ reg_cfg |= CFG_WIN(window); reg_cfg |= prescaler; reg_ctl |= CTL_CNT(counter); - + WWDGT_CTL = reg_ctl; WWDGT_CFG = reg_cfg; } @@ -103,7 +129,7 @@ void wwdgt_interrupt_enable(void) */ FlagStatus wwdgt_flag_get(void) { - if(WWDGT_STAT & WWDGT_STAT_EWIF){ + if(RESET != (WWDGT_STAT & WWDGT_STAT_EWIF)){ return SET; } diff --git a/bsp/gd32450z-eval/Libraries/GD32F4xx_usb_driver/Include/usb_core.h b/bsp/gd32450z-eval/Libraries/GD32F4xx_usb_driver/Include/usb_core.h deleted file mode 100644 index 2891e0219c..0000000000 --- a/bsp/gd32450z-eval/Libraries/GD32F4xx_usb_driver/Include/usb_core.h +++ /dev/null @@ -1,287 +0,0 @@ -/*! - \file usb_core.h - \brief USB core driver header file -*/ - -/* - Copyright (C) 2016 GigaDevice - - 2016-08-15, V1.0.0, firmware for GD32F4xx -*/ - -#ifndef USB_CORE_H -#define USB_CORE_H - -#include "usb_conf.h" -#include "usb_regs.h" -#include "usb_defines.h" - -#define USB_MAX_EP0_SIZE 64U /* endpoint 0 max packet size */ -#define RX_MAX_DATA_LENGTH 512U /* host rx buffer max data length */ -#define HC_MAX_PACKET_COUNT 140U /* host channel max packet count */ - -#ifdef USE_USBFS - #define USB_MAX_DEV_EPCOUNT USBFS_MAX_DEV_EPCOUNT - #define USB_MAX_FIFOS (USBFS_MAX_HOST_CHANNELCOUNT * 2U - 1U) -#elif defined(USE_USBHS) - #define USB_MAX_DEV_EPCOUNT USBHS_MAX_DEV_EPCOUNT - #define USB_MAX_FIFOS (USBHS_MAX_HOST_CHANNELCOUNT * 2U - 1U) -#endif /* USE_USBFS */ - -/* USB core status */ -typedef enum -{ - USB_OK = 0, /* USB core OK status */ - USB_FAIL /* USB core fail status */ -}usb_status_enum; - -/* USB host channel status */ -typedef enum -{ - HC_IDLE = 0, /* USB host channel idle status */ - HC_XF, /* USB host channel transfer status */ - HC_HALTED, /* USB host channel halted status */ - HC_NAK, /* USB host channel nak status */ - HC_NYET, /* USB host channel nyet status */ - HC_STALL, /* USB host channel stall status */ - HC_TRACERR, /* USB host channel tracerr status */ - HC_BBERR, /* USB host channel bberr status */ - HC_DTGERR, /* USB host channel dtgerr status */ -}hc_status_enum; - -/* USB URB(USB request block) state */ -typedef enum -{ - URB_IDLE = 0, /* USB URB idle status */ - URB_DONE, /* USB URB done status */ - URB_NOTREADY, /* USB URB notready status */ - URB_ERROR, /* USB URB error status */ - URB_STALL, /* USB URB stall status */ - URB_PING /* USB URB ping status */ -}urb_state_enum; - -/* USB core configuration */ -typedef struct -{ - uint8_t core_id; /* USB core id */ - uint8_t core_speed; /* USB core speed */ - uint8_t phy_interface; /* USB PHY interface */ - uint8_t host_channel_num; /* USB host channel number */ - uint8_t dev_endp_num; /* USB device endpoint number */ - uint8_t dma_enable; /* USBHS can use DMA */ - uint8_t sof_output; /* USB SOF output */ - uint8_t low_power; /* USB low power */ - uint16_t max_packet_size; /* USB max packet size */ - uint16_t max_fifo_size; /* USB fifo size */ -}usb_core_cfgs_struct; - -typedef enum -{ - USBD_OK = 0, /* USB device ok status */ - USBD_BUSY, /* USB device busy status */ - USBD_FAIL, /* USB device fail stauts */ -}usbd_status_enum; - -/* USB control transfer state */ -typedef enum -{ - USB_CTRL_IDLE = 0, /* USB control transfer idle state */ - USB_CTRL_SETUP, /* USB control transfer setup state */ - USB_CTRL_DATA_IN, /* USB control transfer data in state */ - USB_CTRL_DATA_OUT, /* USB control transfer data out state */ - USB_CTRL_STATUS_IN, /* USB control transfer status in state*/ - USB_CTRL_STATUS_OUT, /* USB control transfer status out state */ - USB_CTRL_STALL /* USB control transfer stall state */ -}usbd_control_state_enum; - -/* USB transfer direction */ -typedef enum -{ - USBD_RX = 0, /* receive direction type value */ - USBD_TX /* transmit direction type value */ -}usbd_dir_enum; - -/* USB endpoint in device mode */ -typedef struct -{ - uint8_t endp_type; /* USB endpoint type */ - uint8_t endp_frame; /* USB endpoint frame */ - uint32_t endp_mps; /* USB endpoint max packet size */ - - /* Transaction level variables */ - uint8_t *xfer_buff; /* USB transfer buffer */ - uint32_t xfer_len; /* USB transfer length */ - uint32_t xfer_count; /* USB transfer count */ - - uint32_t dma_addr; /* USBHS can use DMA */ -}usb_ep_struct; - -/* USB device standard request */ -typedef struct -{ - uint8_t bmRequestType; /* USB device request type */ - uint8_t bRequest; /* USB device request */ - uint16_t wValue; /* USB device request value */ - uint16_t wIndex; /* USB device request index */ - uint16_t wLength; /* USB device request length */ -}usb_device_req_struct; - -/* USB core device driver */ -typedef struct -{ - uint8_t config_num; /* USB configuration number */ - uint8_t status; /* USB status */ - uint8_t ctl_status; /* USB control status */ - uint8_t prev_status; /* USB previous status */ - uint8_t connection_status; /* USB connection status */ - uint32_t remote_wakeup; /* USB remote wakeup */ - - /* transfer level variables */ - uint32_t remain_len; /* USB remain length */ - uint32_t sum_len; /* USB sum length */ - uint32_t ctl_len; /* USB control length */ - uint8_t setup_packet[8 * 3]; /* USB setup packet */ - - usb_ep_struct in_ep[USB_MAX_DEV_EPCOUNT]; /* USB IN endpoint */ - usb_ep_struct out_ep[USB_MAX_DEV_EPCOUNT]; /* USB OUT endpoint */ - - uint8_t *dev_desc; /* device descriptor */ - uint8_t *config_desc; /* configuration descriptor */ - uint8_t* *strings; /* configuration strings */ - - /* device class handler */ - uint8_t (*class_init) (void *pudev, uint8_t config_index); /* device class initialize */ - uint8_t (*class_deinit) (void *pudev, uint8_t config_index); /* device class deinitialize */ - uint8_t (*class_req_handler) (void *pudev, usb_device_req_struct *req); /* device request handler */ - uint8_t (*class_data_handler) (void *pudev, usbd_dir_enum rx_tx, uint8_t ep_id); /* device data handler */ -}dcd_dev_struct; - -/* USB core host mode channel */ -typedef struct -{ - uint8_t dev_addr; /* device address */ - uint8_t dev_speed; /* device speed */ - uint8_t DPID; /* endpoint transfer data pid */ - uint8_t endp_id; /* endpoint id */ - uint8_t endp_in; /* endpoint in */ - uint8_t endp_type; /* endpoint type */ - uint16_t endp_mps; /* endpoint max pactet size */ - uint16_t info; /* channel information */ - - uint8_t do_ping; /* USBHS ping */ - - uint8_t *xfer_buff; /* transfer buffer */ - uint32_t xfer_len; /* transfer length */ - uint32_t xfer_count; /* trasnfer count */ - - uint32_t err_count; /* USB transfer error count */ - uint32_t dma_addr; /* USBHS can use DMA */ - - hc_status_enum status; /* channel status */ - urb_state_enum urb_state; /* URB state */ - - uint8_t data_tg_in; /* data in toggle */ - uint8_t data_tg_out; /* data out toggle */ -}usb_hostchannel_struct; - -/* USB core host driver */ -typedef struct -{ - uint8_t rx_buffer[RX_MAX_DATA_LENGTH]; /* rx buffer */ - uint8_t connect_status; /* device connect status */ - usb_hostchannel_struct host_channel[USB_MAX_FIFOS]; /* host channel */ - void (*vbus_drive) (void *pudev, uint8_t state); /* the vbus driver function */ -}hcd_dev_struct; - -#ifdef USE_OTG_MODE - -/* USB core OTG-mode driver */ -typedef struct -{ - uint8_t OTG_State; /* OTG state */ - uint8_t OTG_PrevState; /* OTG previous state */ - uint8_t OTG_Mode; /* OTG mode */ -}otg_dev_struct; - -#endif /* USE_OTG_MODE */ - -/* USB core driver */ -typedef struct -{ - usb_core_cfgs_struct cfg; - -#ifdef USE_DEVICE_MODE - dcd_dev_struct dev; -#endif /* USE_DEVICE_MODE */ - -#ifdef USE_HOST_MODE - hcd_dev_struct host; -#endif /* USE_HOST_MODE */ - -#ifdef USE_OTG_MODE - otg_dev_struct otg; -#endif /* USE_OTG_MODE */ - - void (*udelay) (const uint32_t usec); - void (*mdelay) (const uint32_t msec); -}usb_core_handle_struct; - -/* function declarations */ - -/* global APIs */ -/* initializes the USB controller registers and prepares the core device mode or host mode operation */ -usb_status_enum usb_core_init (usb_core_handle_struct *pudev); -/* initialize core parameters */ -usb_status_enum usb_core_select (usb_core_handle_struct *pudev, usb_core_id_enum core_id); -/* read a packet from the Rx FIFO associated with the endpoint */ -void* usb_fifo_read (uint8_t *dest, uint16_t len); -/* write a packet into the Tx FIFO associated with the endpoint */ -usb_status_enum usb_fifo_write (uint8_t *src, uint8_t ep_id, uint16_t len); -/* flush a Tx FIFO or all Tx FIFOs */ -usb_status_enum usb_txfifo_flush (usb_core_handle_struct *pudev, uint8_t fifo_num); -/* flush the entire Rx FIFO */ -usb_status_enum usb_rxfifo_flush (usb_core_handle_struct *pudev); -/* set operation mode (host or device) */ -usb_status_enum usb_mode_set (usb_core_handle_struct *pudev, uint8_t mode); - -/* host APIs */ -#ifdef USE_HOST_MODE - -/* initializes USB core for host mode */ -usb_status_enum usb_hostcore_init (usb_core_handle_struct *pudev); -/* enables the host mode interrupts */ -usb_status_enum usb_hostint_enable (usb_core_handle_struct *pudev); -/* initialize host channel */ -usb_status_enum usb_hostchannel_init (usb_core_handle_struct *pudev, uint8_t hc_num); -/* halt channel */ -usb_status_enum usb_hostchannel_halt (usb_core_handle_struct *pudev, uint8_t hc_num); -/* prepare host channel for transferring packets */ -usb_status_enum usb_hostchannel_startxfer (usb_core_handle_struct *pudev, uint8_t hc_num); -/* issue a ping token */ -usb_status_enum usb_hostchannel_ping (usb_core_handle_struct *pudev, uint8_t hc_num); -/* reset host port */ -uint32_t usb_port_reset (usb_core_handle_struct *pudev); -/* control the VBUS to power */ -void usb_vbus_drive (usb_core_handle_struct *pudev, uint8_t state); -/* stop the USB host and clean up fifos */ -void usb_host_stop (usb_core_handle_struct *pudev); - -#endif /* USE_HOST_MODE */ - -/* device APIs */ -#ifdef USE_DEVICE_MODE - -/* initialize USB core registers for device mode */ -usb_status_enum usb_devcore_init (usb_core_handle_struct *pudev); -/* configures endpoint 0 to receive SETUP packets */ -void usb_ep0_startout (usb_core_handle_struct *pudev); -/* active remote wakeup signalling */ -void usb_remotewakeup_active (usb_core_handle_struct *pudev); -/* active USB core clock */ -void usb_clock_ungate (usb_core_handle_struct *pudev); -/* stop the device and clean up fifos */ -void usb_device_stop (usb_core_handle_struct *pudev); - -#endif /* USE_DEVICE_MODE */ - -#endif /* USB_CORE_H */ diff --git a/bsp/gd32450z-eval/Libraries/GD32F4xx_usb_driver/Include/usb_defines.h b/bsp/gd32450z-eval/Libraries/GD32F4xx_usb_driver/Include/usb_defines.h deleted file mode 100644 index 309e23f32f..0000000000 --- a/bsp/gd32450z-eval/Libraries/GD32F4xx_usb_driver/Include/usb_defines.h +++ /dev/null @@ -1,100 +0,0 @@ -/*! - \file usb_defines.h - \brief USB core defines -*/ - -/* - Copyright (C) 2016 GigaDevice - - 2016-08-15, V1.0.0, firmware for GD32F4xx -*/ - -#ifndef USB_DEFINES_H -#define USB_DEFINES_H - -#include "usb_conf.h" - -#ifndef NULL - #define NULL (void *)0 /*!< USB null marco value*/ -#endif /* NULL */ - -#define USB_CORE_SPEED_HIGH 0U /* USB core speed is high-speed */ -#define USB_CORE_SPEED_FULL 1U /* USB core speed is full-speed */ - -#define USBFS_MAX_PACKET_SIZE 64U /* USBFS max packet size */ -#define USBFS_MAX_HOST_CHANNELCOUNT 8U /* USBFS host channel count */ -#define USBFS_MAX_DEV_EPCOUNT 4U /* USBFS device endpoint count */ -#define USBFS_MAX_FIFO_WORDLEN 320U /* USBFS max fifo size in words */ - -#define USBHS_MAX_PACKET_SIZE 512U /* USBHS max packet size */ -#define USBHS_MAX_HOST_CHANNELCOUNT 12U /* USBHS host channel count */ -#define USBHS_MAX_DEV_EPCOUNT 6U /* USBHS device endpoint count */ -#define USBHS_MAX_FIFO_WORDLEN 1280U /* USBHS max fifo size in words */ - -#define USB_CORE_ULPI_PHY 1U /* USB core use external ULPI PHY */ -#define USB_CORE_EMBEDDED_PHY 2U /* USB core use embedded PHY */ - -#define DSTAT_ENUMSPD_HS_PHY_30MHZ_OR_60MHZ 0U /* USB enumerate speed use high-speed PHY clock in 30MHz or 60MHz */ -#define DSTAT_ENUMSPD_FS_PHY_30MHZ_OR_60MHZ 1U /* USB enumerate speed use full-speed PHY clock in 30MHz or 60MHz */ -#define DSTAT_ENUMSPD_LS_PHY_6MHZ 2U /* USB enumerate speed use low-speed PHY clock in 6MHz */ -#define DSTAT_ENUMSPD_FS_PHY_48MHZ 3U /* USB enumerate speed use full-speed PHY clock in 48MHz */ - -#define GRSTATR_RPCKST_IN 2U /* IN data packet received */ -#define GRSTATR_RPCKST_IN_XFER_COMP 3U /* IN transfer completed (generates an interrupt if poped) */ -#define GRSTATR_RPCKST_DATA_TOGGLE_ERR 5U /* Data toggle error (generates an interrupt if poped) */ -#define GRSTATR_RPCKST_CH_HALTED 7U /* Channel halted (generates an interrupt if poped) */ - -#define DEVICE_MODE 0U /* USB core in device mode */ -#define HOST_MODE 1U /* USB core in host mode */ -#define OTG_MODE 2U /* USB core in OTG mode */ - -#define USB_EPTYPE_CTRL 0U /* USB control endpoint type */ -#define USB_EPTYPE_ISOC 1U /* USB synchronous endpoint type */ -#define USB_EPTYPE_BULK 2U /* USB bulk endpoint type */ -#define USB_EPTYPE_INTR 3U /* USB interrupt endpoint type */ -#define USB_EPTYPE_MASK 3U /* USB endpoint type mask */ - -#define RXSTAT_GOUT_NAK 1U /* global OUT NAK (triggers an interrupt) */ -#define RXSTAT_DATA_UPDT 2U /* OUT data packet received */ -#define RXSTAT_XFER_COMP 3U /* OUT transfer completed (triggers an interrupt) */ -#define RXSTAT_SETUP_COMP 4U /* SETUP transaction completed (triggers an interrupt) */ -#define RXSTAT_SETUP_UPDT 6U /* SETUP data packet received */ - -#define DPID_DATA0 0U /* device endpoint data PID is DATA0 */ -#define DPID_DATA1 2U /* device endpoint data PID is DATA1 */ -#define DPID_DATA2 1U /* device endpoint data PID is DATA2 */ -#define DPID_MDATA 3U /* device endpoint data PID is MDATA */ - -#define HC_PID_DATA0 0U /* host channel data PID is DATA0 */ -#define HC_PID_DATA2 1U /* host channel data PID is DATA2 */ -#define HC_PID_DATA1 2U /* host channel data PID is DATA1 */ -#define HC_PID_SETUP 3U /* host channel data PID is SETUP */ - -#define HPRT_PRTSPD_HIGH_SPEED 0U /* host port speed use high speed */ -#define HPRT_PRTSPD_FULL_SPEED 1U /* host port speed use full speed */ -#define HPRT_PRTSPD_LOW_SPEED 2U /* host port speed use low speed */ - -#define HCTLR_30_60_MHZ 0U /* USB PHY(ULPI) clock is 60MHz */ -#define HCTLR_48_MHZ 1U /* USB PHY(embedded full-speed) clock is 48MHz */ -#define HCTLR_6_MHZ 2U /* USB PHY(embedded low-speed) clock is 6MHz */ - -#define HCCHAR_CTRL 0U /* control channel type */ -#define HCCHAR_ISOC 1U /* synchronous channel type */ -#define HCCHAR_BULK 2U /* bulk channel type */ -#define HCCHAR_INTR 3U /* interrupt channel type */ - -typedef enum -{ - USB_HS_CORE_ID = 0, - USB_FS_CORE_ID = 1 -}usb_core_id_enum; - -typedef enum -{ - USB_SPEED_UNKNOWN = 0, - USB_SPEED_LOW, - USB_SPEED_FULL, - USB_SPEED_HIGH -}usb_speed_enum; - -#endif /* USB_DEFINES_H */ diff --git a/bsp/gd32450z-eval/Libraries/GD32F4xx_usb_driver/Include/usb_regs.h b/bsp/gd32450z-eval/Libraries/GD32F4xx_usb_driver/Include/usb_regs.h deleted file mode 100644 index db05aa25ff..0000000000 --- a/bsp/gd32450z-eval/Libraries/GD32F4xx_usb_driver/Include/usb_regs.h +++ /dev/null @@ -1,676 +0,0 @@ -/*! - \file usb_regs.h - \brief USB FS&HS cell registers definition and handle macros -*/ - -/* - Copyright (C) 2016 GigaDevice - - 2016-08-15, V1.0.0, firmware for GD32F4xx -*/ - -#ifndef USB_REGS_H -#define USB_REGS_H - -#include "usb_conf.h" - -#define USBFS USBFS_BASE /*!< base address of USBFS registers */ -#define USBHS USBHS_BASE /*!< base address of USBHS registers */ - -#ifdef USE_USBFS - #define USBX USBFS /*!< USB full speed mode */ -#endif /* USE_USBFS */ - -#ifdef USE_USBHS - #define USBX USBHS /*!< USB high speed mode */ -#endif /* USE_USBHS */ - -/* registers location definitions */ -#define LOCATE_DIEPTFLEN(x) (0x104U + 4U * ((x) - 1U)) /*!< locate device IN endpoint-x transfer length registers */ -#define LOCATE_HCHCTL(x) (0x500U + 0x20U * (x)) /*!< locate host channel-x control registers */ -#define LOCATE_HCHSTCTL(x) (0x504U + 0x20U * (x)) /*!< locate host channel-x split transaction control registers */ -#define LOCATE_HCHINTF(x) (0x508U + 0x20U * (x)) /*!< locate host channel-x interrupt flag registers */ -#define LOCATE_HCHINTEN(x) (0x50CU + 0x20U * (x)) /*!< locate host channel-x interrupt enable registers */ -#define LOCATE_HCHLEN(x) (0x510U + 0x20U * (x)) /*!< locate host channel-x transfer length registers */ -#define LOCATE_HCHDMAADDR(x) (0x514U + 0x20U * (x)) /*!< locate host channel-x DMA address registers */ -#define LOCATE_DIEPCTL(x) (0x900U + 0x20U * (x)) /*!< locate device IN endpoint-x control registers */ -#define LOCATE_DOEPCTL(x) (0xB00U + 0x20U * (x)) /*!< locate device OUT endpoint-x control registers */ -#define LOCATE_DIEPINTF(x) (0x908U + 0x20U * (x)) /*!< locate device IN endpoint-x interrupt flag registers */ -#define LOCATE_DOEPINTF(x) (0xB08U + 0x20U * (x)) /*!< locate device OUT endpoint-x interrupt flag registers */ -#define LOCATE_DIEPLEN(x) (0x910U + 0x20U * (x)) /*!< locate device IN endpoint-x transfer length registers */ -#define LOCATE_DOEPLEN(x) (0xB10U + 0x20U * (x)) /*!< locate device OUT endpoint-x transfer length registers */ -#define LOCATE_DIEPxDMAADDR(x) (0x914U + 0x20U * (x)) /*!< locate device IN endpoint-x DMA address registers */ -#define LOCATE_DOEPxDMAADDR(x) (0xB14U + 0x20U * (x)) /*!< locate device OUT endpoint-x DMA address registers */ -#define LOCATE_DIEPxTFSTAT(x) (0x918U + 0x20U * (x)) /*!< locate Device IN endpoint-x transmit FIFO status register */ -#define LOCATE_FIFO(x) (((x) + 1U) << 12U) /*!< locate FIFO-x memory */ - -/* registers definitions */ -#define USB_GOTGCS REG32(((USBX) + 0x0000U)) /*!< global OTG control and status register */ -#define USB_GOTGINTF REG32(((USBX) + 0x0004U)) /*!< global OTG interrupt flag register */ -#define USB_GAHBCS REG32(((USBX) + 0x0008U)) /*!< global AHB control and status register */ -#define USB_GUSBCS REG32(((USBX) + 0x000CU)) /*!< global USB control and status register */ -#define USB_GRSTCTL REG32(((USBX) + 0x0010U)) /*!< global reset control register */ -#define USB_GINTF REG32(((USBX) + 0x0014U)) /*!< global interrupt flag register */ -#define USB_GINTEN REG32(((USBX) + 0x0018U)) /*!< global interrupt enable register */ -#define USB_GRSTATR REG32(((USBX) + 0x001CU)) /*!< global receive status read register */ -#define USB_GRSTATP REG32(((USBX) + 0x0020U)) /*!< global receive status read and pop register */ -#define USB_GRFLEN REG32(((USBX) + 0x0024U)) /*!< global receive FIFO length register */ -#define USB_HNPTFLEN REG32(((USBX) + 0x0028U)) /*!< host non-periodic transmit FIFO length register */ -#define USB_DIEP0TFLEN REG32(((USBX) + 0x0028U)) /*!< device IN endpoint 0 transmit FIFO length register */ -#define USB_HNPTFQSTAT REG32(((USBX) + 0x002CU)) /*!< host non-periodic transmint FIFO/queue status register */ -#define USB_GCCFG REG32(((USBX) + 0x0038U)) /*!< global core configuration register */ -#define USB_CID REG32(((USBX) + 0x003CU)) /*!< core id register */ -#define USB_HPTFLEN REG32(((USBX) + 0x0100U)) /*!< host periodic transmit FIFO length register */ -#define USB_DIEPxTFLEN(x) REG32(((USBX) + LOCATE_DIEPTFLEN(x))) /*!< device IN endpoint transmit FIFO length register */ - -#define USB_HCTL REG32(((USBX) + 0x0400U)) /*!< host control register */ -#define USB_HFT REG32(((USBX) + 0x0404U)) /*!< host frame interval register */ -#define USB_HFINFR REG32(((USBX) + 0x0408U)) /*!< host frame information remaining register */ -#define USB_HPTFQSTAT REG32(((USBX) + 0x0410U)) /*!< host periodic transmit FIFO/queue status register */ -#define USB_HACHINT REG32(((USBX) + 0x0414U)) /*!< host all channels interrupt register */ -#define USB_HACHINTEN REG32(((USBX) + 0x0418U)) /*!< host all channels interrupt enable register */ -#define USB_HPCS REG32(((USBX) + 0x0440U)) /*!< host port control and status register */ -#define USB_HCHxCTL(x) REG32(((USBX) + LOCATE_HCHCTL(x))) /*!< host channel-x control register */ -#define USB_HCHxSTCTL(x) REG32(((USBX) + LOCATE_HCHSTCTL(x))) /*!< host channel-x split transaction control register */ -#define USB_HCHxINTF(x) REG32(((USBX) + LOCATE_HCHINTF(x))) /*!< host channel-x interrupt flag register */ -#define USB_HCHxINTEN(x) REG32(((USBX) + LOCATE_HCHINTEN(x))) /*!< host channel-x interrupt enable register */ -#define USB_HCHxLEN(x) REG32(((USBX) + LOCATE_HCHLEN(x))) /*!< host channel-x tranfer length register */ -#define USB_HCHxDMAADDR(x) REG32(((USBX) + LOCATE_HCHDMAADDR(x))) /*!< host channel-x DMA address register */ - -#define USB_DCFG REG32(((USBX) + 0x0800U)) /*!< device configuration register */ -#define USB_DCTL REG32(((USBX) + 0x0804U)) /*!< device control register */ -#define USB_DSTAT REG32(((USBX) + 0x0808U)) /*!< device status register */ -#define USB_DIEPINTEN REG32(((USBX) + 0x0810U)) /*!< device IN endpoint common interrupt enable register */ -#define USB_DOEPINTEN REG32(((USBX) + 0x0814U)) /*!< device OUT endpoint common interrupt enable register */ -#define USB_DAEPINT REG32(((USBX) + 0x0818U)) /*!< device all endpoints interrupt register */ -#define USB_DAEPINTEN REG32(((USBX) + 0x081CU)) /*!< device all endpoints interrupt enable register */ -#define USB_DVBUSDT REG32(((USBX) + 0x0828U)) /*!< device vbus discharge time register */ -#define USB_DVBUSPT REG32(((USBX) + 0x082CU)) /*!< device vbus pulsing time register */ -#define USB_DIEPFEINTEN REG32(((USBX) + 0x0834U)) /*!< device IN endpoint FIFO empty interrupt enable register */ -#define USB_DEP1INT REG32(((USBX) + 0x0838U)) /*!< device endpoint 1 interrupt register */ -#define USB_DEP1INTEN REG32(((USBX) + 0x083CU)) /*!< device endpoint 1 interrupt enable register */ -#define USB_DIEP1INTEN REG32(((USBX) + 0x0844U)) /*!< device IN endpoint 1 interrupt enable register */ -#define USB_DOEP1INTEN REG32(((USBX) + 0x0884U)) /*!< device OUT endpoint 1 interrupt enable register */ -#define USB_DIEP0CTL REG32(((USBX) + 0x0900U)) /*!< device IN endpoint 0 control register */ -#define USB_DIEP0LEN REG32(((USBX) + 0x0910U)) /*!< device IN endpoint 0 transfer length register */ -#define USB_DOEP0CTL REG32(((USBX) + 0x0B00U)) /*!< device OUT endpoint 0 control register */ -#define USB_DOEP0LEN REG32(((USBX) + 0x0B10U)) /*!< device OUT endpoint 0 transfer length register */ -#define USB_DIEPxCTL(x) REG32(((USBX) + LOCATE_DIEPCTL(x))) /*!< device IN endpoint-x control register */ -#define USB_DOEPxCTL(x) REG32(((USBX) + LOCATE_DOEPCTL(x))) /*!< device OUT endpoint-x control register */ -#define USB_DIEPxINTF(x) REG32(((USBX) + LOCATE_DIEPINTF(x))) /*!< device IN endpoint-x interrupt flag register */ -#define USB_DOEPxINTF(x) REG32(((USBX) + LOCATE_DOEPINTF(x))) /*!< device OUT endpoint-x interrupt flag register */ -#define USB_DIEPxLEN(x) REG32(((USBX) + LOCATE_DIEPLEN(x))) /*!< device IN endpoint-x transfer length register */ -#define USB_DOEPxLEN(x) REG32(((USBX) + LOCATE_DOEPLEN(x))) /*!< device OUT endpoint-x transfer length register */ -#define USB_DIEPxDMAADDR(x) REG32(((USBX) + LOCATE_DIEPxDMAADDR(x)))/*!< device IN endpoint-x DMA address register */ -#define USB_DOEPxDMAADDR(x) REG32(((USBX) + LOCATE_DOEPxDMAADDR(x)))/*!< device OUT endpoint-x DMA address register */ -#define USB_DIEPxTFSTAT(x) REG32(((USBX) + LOCATE_DIEPxTFSTAT(x))) /*!< device IN endpoint-x transmit FIFO status register */ - -#define USB_PWRCLKCTL REG32(((USBX) + 0x0E00U)) /*!< power and clock register */ - -#define USB_FIFO(x) (®32(((USBX) + LOCATE_FIFO(x)))) /*!< FIFO memory */ - -/* global OTG control and status register bits definitions */ -#define GOTGCS_BSV BIT(19) /*!< B-Session Valid */ -#define GOTGCS_ASV BIT(18) /*!< A-session valid */ -#define GOTGCS_DI BIT(17) /*!< debounce interval */ -#define GOTGCS_CIDPS BIT(16) /*!< id pin status */ -#define GOTGCS_DHNPEN BIT(11) /*!< device HNP enable */ -#define GOTGCS_HHNPEN BIT(10) /*!< host HNP enable */ -#define GOTGCS_HNPREQ BIT(9) /*!< HNP request */ -#define GOTGCS_HNPS BIT(8) /*!< HNP successes */ -#define GOTGCS_SRPREQ BIT(1) /*!< SRP request */ -#define GOTGCS_SRPS BIT(0) /*!< SRP successes */ - -/* global OTG interrupt flag register bits definitions */ -#define GOTGINTF_DF BIT(19) /*!< debounce finish */ -#define GOTGINTF_ADTO BIT(18) /*!< A-device timeout */ -#define GOTGINTF_HNPDET BIT(17) /*!< host negotiation request detected */ -#define GOTGINTF_HNPEND BIT(9) /*!< HNP end */ -#define GOTGINTF_SRPEND BIT(8) /*!< SRP end */ -#define GOTGINTF_SESEND BIT(2) /*!< session end */ - -/* global AHB control and status register bits definitions */ -#define GAHBCS_PTXFTH BIT(8) /*!< periodic Tx FIFO threshold */ -#define GAHBCS_TXFTH BIT(7) /*!< tx FIFO threshold */ -#define GAHBCS_DMAEN BIT(5) /*!< DMA function Enable */ -#define GAHBCS_BURST BITS(1, 4) /*!< the AHB burst type used by DMA */ -#define GAHBCS_GINTEN BIT(0) /*!< global interrupt enable */ - -/* global USB control and status register bits definitions */ -#define GUSBCS_FDM BIT(30) /*!< force device mode */ -#define GUSBCS_FHM BIT(29) /*!< force host mode */ -#define GUSBCS_ULPIEOI BIT(21) /*!< ULPI external over-current indicator */ -#define GUSBCS_ULPIEVD BIT(20) /*!< ULPI external VBUS driver */ -#define GUSBCS_UTT BITS(10, 13) /*!< USB turnaround time */ -#define GUSBCS_HNPCEN BIT(9) /*!< HNP capability enable */ -#define GUSBCS_SRPCEN BIT(8) /*!< SRP capability enable */ -#define GUSBCS_EMBPHY BIT(6) /*!< embedded PHY selected */ -#define GUSBCS_TOC BITS(0, 2) /*!< timeout calibration */ - -/* global reset control register bits definitions */ -#define GRSTCTL_DMAIDL BIT(31) /*!< DMA idle state */ -#define GRSTCTL_DMABSY BIT(30) /*!< DMA busy */ -#define GRSTCTL_TXFNUM BITS(6, 10) /*!< tx FIFO number */ -#define GRSTCTL_TXFF BIT(5) /*!< tx FIFO flush */ -#define GRSTCTL_RXFF BIT(4) /*!< rx FIFO flush */ -#define GRSTCTL_HFCRST BIT(2) /*!< host frame counter reset */ -#define GRSTCTL_HCSRST BIT(1) /*!< HCLK soft reset */ -#define GRSTCTL_CSRST BIT(0) /*!< core soft reset */ - -/* global interrupt flag register bits definitions */ -#define GINTF_WKUPIF BIT(31) /*!< wakeup interrupt flag */ -#define GINTF_SESIF BIT(30) /*!< session interrupt flag */ -#define GINTF_DISCIF BIT(29) /*!< disconnect interrupt flag */ -#define GINTF_IDPSC BIT(28) /*!< id pin status change */ -#define GINTF_PTXFEIF BIT(26) /*!< periodic tx FIFO empty interrupt flag */ -#define GINTF_HCIF BIT(25) /*!< host channels interrupt flag */ -#define GINTF_HPIF BIT(24) /*!< host port interrupt flag */ -#define GINTF_PXNCIF BIT(21) /*!< periodic transfer not complete interrupt flag */ -#define GINTF_ISOONCIF BIT(21) /*!< isochronous OUT transfer not complete interrupt flag */ -#define GINTF_ISOINCIF BIT(20) /*!< isochronous IN transfer not complete interrupt flag */ -#define GINTF_OEPIF BIT(19) /*!< OUT endpoint interrupt flag */ -#define GINTF_IEPIF BIT(18) /*!< IN endpoint interrupt flag */ -#define GINTF_EOPFIF BIT(15) /*!< end of periodic frame interrupt flag */ -#define GINTF_ISOOPDIF BIT(14) /*!< isochronous OUT packet dropped interrupt flag */ -#define GINTF_ENUMFIF BIT(13) /*!< enumeration finished */ -#define GINTF_RST BIT(12) /*!< USB reset */ -#define GINTF_SP BIT(11) /*!< USB suspend */ -#define GINTF_ESP BIT(10) /*!< early suspend */ -#define GINTF_GONAK BIT(7) /*!< global OUT NAK effective */ -#define GINTF_GNPINAK BIT(6) /*!< global IN non-periodic NAK effective */ -#define GINTF_NPTXFEIF BIT(5) /*!< non-periodic tx FIFO empty interrupt flag */ -#define GINTF_RXFNEIF BIT(4) /*!< rx FIFO non-empty interrupt flag */ -#define GINTF_SOF BIT(3) /*!< start of frame */ -#define GINTF_OTGIF BIT(2) /*!< OTG interrupt flag */ -#define GINTF_MFIF BIT(1) /*!< mode fault interrupt flag */ -#define GINTF_COPM BIT(0) /*!< current operation mode */ - -/* global interrupt enable register bits definitions */ -#define GINTEN_WKUPIE BIT(31) /*!< wakeup interrupt enable */ -#define GINTEN_SESIE BIT(30) /*!< session interrupt enable */ -#define GINTEN_DISCIE BIT(29) /*!< disconnect interrupt enable */ -#define GINTEN_IDPSCIE BIT(28) /*!< id pin status change interrupt enable */ -#define GINTEN_PTXFEIE BIT(26) /*!< periodic tx FIFO empty interrupt enable */ -#define GINTEN_HCIE BIT(25) /*!< host channels interrupt enable */ -#define GINTEN_HPIE BIT(24) /*!< host port interrupt enable */ -#define GINTEN_IPXIE BIT(21) /*!< periodic transfer not complete interrupt enable */ -#define GINTEN_ISOONCIE BIT(21) /*!< isochronous OUT transfer not complete interrupt enable */ -#define GINTEN_ISOINCIE BIT(20) /*!< isochronous IN transfer not complete interrupt enable */ -#define GINTEN_OEPIE BIT(19) /*!< OUT endpoints interrupt enable */ -#define GINTEN_IEPIE BIT(18) /*!< IN endpoints interrupt enable */ -#define GINTEN_EOPFIE BIT(15) /*!< end of periodic frame interrupt enable */ -#define GINTEN_ISOOPDIE BIT(14) /*!< isochronous OUT packet dropped interrupt enable */ -#define GINTEN_ENUMFIE BIT(13) /*!< enumeration finish enable */ -#define GINTEN_RSTIE BIT(12) /*!< USB reset interrupt enable */ -#define GINTEN_SPIE BIT(11) /*!< USB suspend interrupt enable */ -#define GINTEN_ESPIE BIT(10) /*!< early suspend interrupt enable */ -#define GINTEN_GONAKIE BIT(7) /*!< global OUT NAK effective interrupt enable */ -#define GINTEN_GNPINAKIE BIT(6) /*!< global non-periodic IN NAK effective interrupt enable */ -#define GINTEN_NPTXFEIE BIT(5) /*!< non-periodic Tx FIFO empty interrupt enable */ -#define GINTEN_RXFNEIE BIT(4) /*!< receive FIFO non-empty interrupt enable */ -#define GINTEN_SOFIE BIT(3) /*!< start of frame interrupt enable */ -#define GINTEN_OTGIE BIT(2) /*!< OTG interrupt enable */ -#define GINTEN_MFIE BIT(1) /*!< mode fault interrupt enable */ - -/* global receive status debug read register bits definitions */ -#define GRSTATR_RPCKST BITS(17, 20) /*!< received packet status */ -#define GRSTATR_DPID BITS(15, 16) /*!< data PID */ -#define GRSTATR_BCOUNT BITS(4, 14) /*!< byte count */ -#define GRSTATR_CNUM BITS(0, 3) /*!< channel number */ - -/* global status read and pop register bits definitions */ -#define GRSTATP_RPCKST BITS(17, 20) /*!< received packet status */ -#define GRSTATP_DPID BITS(15, 16) /*!< data PID */ -#define GRSTATP_BCOUNT BITS(4, 14) /*!< byte count */ -#define GRSTATP_EPNUM BITS(0, 3) /*!< endpoint number */ - -/* global receive FIFO length register bits definitions */ -#define GRFLEN_RXFD BITS(0, 15) /*!< rx FIFO depth */ - -/* host non-periodic transmit FIFO length register bits definitions */ -#define HNPTFLEN_HNPTXFD BITS(16, 31) /*!< non-periodic Tx FIFO depth */ -#define HNPTFLEN_HNPTXRSAR BITS(0, 15) /*!< non-periodic Tx RAM start address */ - -/* IN endpoint 0 transmit FIFO length register bits definitions */ -#define DIEP0TFLEN_IEP0TXFD BITS(16, 31) /*!< IN Endpoint 0 Tx FIFO depth */ -#define DIEP0TFLEN_IEP0TXRSAR BITS(0, 15) /*!< IN Endpoint 0 TX RAM start address */ - -/* host non-periodic transmit FIFO/queue status register bits definitions */ -#define HNPTFQSTAT_NPTXRQTOP BITS(24, 30) /*!< top entry of the non-periodic Tx request queue */ -#define HNPTFQSTAT_NPTXRQS BITS(16, 23) /*!< non-periodic Tx request queue space */ -#define HNPTFQSTAT_NPTXFS BITS(0, 15) /*!< non-periodic Tx FIFO space */ -#define HNPTFQSTAT_CNUM BITS(27, 30) /*!< channel number*/ -#define HNPTFQSTAT_EPNUM BITS(27, 30) /*!< endpoint number */ -#define HNPTFQSTAT_TYPE BITS(25, 26) /*!< token type */ -#define HNPTFQSTAT_TMF BIT(24) /*!< terminate flag */ - -/* global core configuration register bits definitions */ -#define GCCFG_VBUSIG BIT(21) /*!< vbus ignored */ -#define GCCFG_SOFOEN BIT(20) /*!< SOF output enable */ -#define GCCFG_VBUSBCEN BIT(19) /*!< the VBUS B-device comparer enable */ -#define GCCFG_VBUSACEN BIT(18) /*!< the VBUS A-device comparer enable */ -#define GCCFG_PWRON BIT(16) /*!< power on */ - -/* core ID register bits definitions */ -#define CID_CID BITS(0, 31) /*!< core ID */ - -/* host periodic transmit FIFO length register bits definitions */ -#define HPTFLEN_HPTXFD BITS(16, 31) /*!< host periodic Tx FIFO depth */ -#define HPTFLEN_HPTXFSAR BITS(0, 15) /*!< host periodic Tx RAM start address */ - -/* device IN endpoint transmit FIFO length register bits definitions */ -#define DIEPTFLEN_IEPTXFD BITS(16, 31) /*!< IN endpoint Tx FIFO x depth */ -#define DIEPTFLEN_IEPTXRSAR BITS(0, 15) /*!< IN endpoint FIFOx Tx x RAM start address */ - -/* host control register bits definitions */ -#define HCTL_SPDFSLS BIT(2) /*!< speed limited to FS and LS */ -#define HCTL_CLKSEL BITS(0, 1) /*!< clock select for USB clock */ - -/* host frame interval register bits definitions */ -#define HFT_FRI BITS(0, 15) /*!< frame interval */ - -/* host frame information remaining register bits definitions */ -#define HFINFR_FRT BITS(16, 31) /*!< frame remaining time */ -#define HFINFR_FRNUM BITS(0, 15) /*!< frame number */ - -/* host periodic transmit FIFO/queue status register bits definitions */ -#define HPTFQSTAT_PTXREQT BITS(24, 31) /*!< top entry of the periodic Tx request queue */ -#define HPTFQSTAT_PTXREQS BITS(16, 23) /*!< periodic Tx request queue space */ -#define HPTFQSTAT_PTXFS BITS(0, 15) /*!< periodic Tx FIFO space */ -#define HPTFQSTAT_OEFRM BIT(31) /*!< odd/eveb frame */ -#define HPTFQSTAT_CNUM BITS(27, 30) /*!< channel number */ -#define HPTFQSTAT_EPNUM BITS(27, 30) /*!< endpoint number */ -#define HPTFQSTAT_TYPE BITS(25, 26) /*!< token type */ -#define HPTFQSTAT_TMF BIT(24) /*!< terminate flag */ - -/* host all channels interrupt register bits definitions */ -#define HACHINT_HACHINT BITS(0, 11) /*!< host all channel interrupts */ - -/* host all channels interrupt enable register bits definitions */ -#define HACHINTEN_CINTEN BITS(0, 11) /*!< channel interrupt enable */ - -/* host port control and status register bits definitions */ -#define HPCS_PS BITS(17, 18) /*!< port speed */ -#define HPCS_PP BIT(12) /*!< port power */ -#define HPCS_PLST BITS(10, 11) /*!< port line status */ -#define HPCS_PRST BIT(8) /*!< port reset */ -#define HPCS_PSP BIT(7) /*!< port suspend */ -#define HPCS_PREM BIT(6) /*!< port resume */ -#define HPCS_PEDC BIT(3) /*!< port enable/disable change */ -#define HPCS_PE BIT(2) /*!< port enable */ -#define HPCS_PCD BIT(1) /*!< port connect detected */ -#define HPCS_PCST BIT(0) /*!< port connect status */ - -/* host channel-x control register bits definitions */ -#define HCHCTL_CEN BIT(31) /*!< channel enable */ -#define HCHCTL_CDIS BIT(30) /*!< channel disable */ -#define HCHCTL_ODDFRM BIT(29) /*!< odd frame */ -#define HCHCTL_DAR BITS(22, 28) /*!< device address */ -#define HCHCTL_MPC BITS(20, 21) /*!< multiple packet count */ -#define HCHCTL_EPTYPE BITS(18, 19) /*!< endpoint type */ -#define HCHCTL_LSD BIT(17) /*!< low-speed device */ -#define HCHCTL_EPDIR BIT(15) /*!< endpoint direction */ -#define HCHCTL_EPNUM BITS(11, 14) /*!< endpoint number */ -#define HCHCTL_MPL BITS(0, 10) /*!< maximum packet length */ - -/* host channel-x split transaction register bits definitions */ -#define HCHSTCTL_SPLEN BIT(31) /*!< enable high-speed split transaction */ -#define HCHSTCTL_CSPLT BIT(16) /*!< complete-split enable */ -#define HCHSTCTL_ISOPCE BITS(14, 15) /*!< isochronous OUT payload continuation encoding */ -#define HCHSTCTL_HADDR BITS(7, 13) /*!< HUB address */ -#define HCHSTCTL_PADDR BITS(0, 6) /*!< port address */ - -/* host channel-x interrupt flag register bits definitions */ -#define HCHINTF_DTER BIT(10) /*!< data toggle error */ -#define HCHINTF_REQOVR BIT(9) /*!< request queue overrun */ -#define HCHINTF_BBER BIT(8) /*!< babble error */ -#define HCHINTF_USBER BIT(7) /*!< USB bus Error */ -#define HCHINTF_NYET BIT(6) /*!< NYET */ -#define HCHINTF_ACK BIT(5) /*!< ACK */ -#define HCHINTF_NAK BIT(4) /*!< NAK */ -#define HCHINTF_STALL BIT(3) /*!< STALL */ -#define HCHINTF_DMAER BIT(2) /*!< DMA error */ -#define HCHINTF_CH BIT(1) /*!< channel halted */ -#define HCHINTF_TF BIT(0) /*!< transfer finished */ - -/* host channel-x interrupt enable register bits definitions */ -#define HCHINTEN_DTERIE BIT(10) /*!< data toggle error interrupt enable */ -#define HCHINTEN_REQOVRIE BIT(9) /*!< request queue overrun interrupt enable */ -#define HCHINTEN_BBERIE BIT(8) /*!< babble error interrupt enable */ -#define HCHINTEN_USBERIE BIT(7) /*!< USB bus error interrupt enable */ -#define HCHINTEN_NYETIE BIT(6) /*!< NYET interrupt enable */ -#define HCHINTEN_ACKIE BIT(5) /*!< ACK interrupt enable */ -#define HCHINTEN_NAKIE BIT(4) /*!< NAK interrupt enable */ -#define HCHINTEN_STALLIE BIT(3) /*!< STALL interrupt enable */ -#define HCHINTEN_DMAERIE BIT(2) /*!< DMA error interrupt enable */ -#define HCHINTEN_CHIE BIT(1) /*!< channel halted interrupt enable */ -#define HCHINTEN_TFIE BIT(0) /*!< transfer finished interrupt enable */ - -/* host channel-x transfer length register bits definitions */ -#define HCHLEN_PING BIT(31) /*!< PING token request */ -#define HCHLEN_DPID BITS(29, 30) /*!< data PID */ -#define HCHLEN_PCNT BITS(19, 28) /*!< packet count */ -#define HCHLEN_TLEN BITS(0, 18) /*!< transfer length */ - -/* host channel-x DMA address register bits definitions */ -#define HCHDMAADDR_DMAADDR BITS(0, 31) /*!< DMA address */ - -/* device control and status registers */ -/* device configuration registers bits definitions */ -#define DCFG_EOPFT BITS(11, 12) /*!< end of periodic frame time */ -#define DCFG_DAR BITS(4, 10) /*!< device address */ -#define DCFG_NZLSOH BIT(2) /*!< non-zero-length status OUT handshake */ -#define DCFG_DS BITS(0, 1) /*!< device speed */ - -/* device control registers bits definitions */ -#define DCTL_POIF BIT(11) /*!< power-on initialization finished */ -#define DCTL_CGONAK BIT(10) /*!< clear global OUT NAK */ -#define DCTL_SGONAK BIT(9) /*!< set global OUT NAK */ -#define DCTL_CGINAK BIT(8) /*!< clear global IN NAK */ -#define DCTL_SGINAK BIT(7) /*!< set global IN NAK */ -#define DCTL_GONS BIT(3) /*!< global OUT NAK status */ -#define DCTL_GINS BIT(2) /*!< global IN NAK status */ -#define DCTL_SD BIT(1) /*!< soft disconnect */ -#define DCTL_RWKUP BIT(0) /*!< remote wakeup */ - -/* device status registers bits definitions */ -#define DSTAT_FNRSOF BITS(8, 21) /*!< the frame number of the received SOF. */ -#define DSTAT_ES BITS(1, 2) /*!< enumerated speed */ -#define DSTAT_SPST BIT(0) /*!< suspend status */ - -/* device IN endpoint common interrupt enable registers bits definitions */ -#define DIEPINTEN_NAKEN BIT(13) /*!< NAK handshake sent by USBHS interrupt enable bit */ -#define DIEPINTEN_TXFEEN BIT(7) /*!< transmit FIFO empty interrupt enable bit */ -#define DIEPINTEN_IEPNEEN BIT(6) /*!< IN endpoint NAK effective interrupt enable bit */ -#define DIEPINTEN_EPTXFUDEN BIT(4) /*!< endpoint Tx FIFO underrun interrupt enable bit */ -#define DIEPINTEN_CITOEN BIT(3) /*!< control In Timeout interrupt enable bit */ -#define DIEPINTEN_EPDISEN BIT(1) /*!< endpoint disabled interrupt enable bit */ -#define DIEPINTEN_TFEN BIT(0) /*!< transfer finished interrupt enable bit */ - -/* device OUT endpoint common interrupt enable registers bits definitions */ -#define DOEPINTEN_NYETEN BIT(14) /*!< NYET handshake is sent interrupt enable bit */ -#define DOEPINTEN_BTBSTPEN BIT(6) /*!< back-to-back SETUP packets interrupt enable bit */ -#define DOEPINTEN_EPRXFOVREN BIT(4) /*!< endpoint Rx FIFO overrun interrupt enable bit */ -#define DOEPINTEN_STPFEN BIT(3) /*!< SETUP phase finished interrupt enable bit */ -#define DOEPINTEN_EPDISEN BIT(1) /*!< endpoint disabled interrupt enable bit */ -#define DOEPINTEN_TFEN BIT(0) /*!< transfer finished interrupt enable bit */ - -/* device all endpoints interrupt registers bits definitions */ -#define DAEPINT_OEPITB BITS(16, 21) /*!< device all OUT endpoint interrupt bits */ -#define DAEPINT_IEPITB BITS(0, 5) /*!< device all IN endpoint interrupt bits */ - -/* device all endpoints interrupt enable registers bits definitions */ -#define DAEPINTEN_OEPIE BITS(16, 21) /*!< OUT endpoint interrupt enable */ -#define DAEPINTEN_IEPIE BITS(0, 3) /*!< IN endpoint interrupt enable */ - -/* device Vbus discharge time registers bits definitions */ -#define DVBUSDT_DVBUSDT BITS(0, 15) /*!< device VBUS discharge time */ - -/* device Vbus pulsing time registers bits definitions */ -#define DVBUSPT_DVBUSPT BITS(0, 11) /*!< device VBUS pulsing time */ - -/* device IN endpoint FIFO empty interrupt enable register bits definitions */ -#define DIEPFEINTEN_IEPTXFEIE BITS(0, 5) /*!< IN endpoint Tx FIFO empty interrupt enable bits */ - -/* device endpoint 1 interrupt register bits definitions */ -#define DEP1INT_OEP1INT BIT(17) /*!< OUT Endpoint 1 interrupt */ -#define DEP1INT_IEP1INT BIT(1) /*!< IN Endpoint 1 interrupt */ - -/* device endpoint 1 interrupt register enable bits definitions */ -#define DEP1INTEN_OEP1INTEN BIT(17) /*!< OUT Endpoint 1 interrupt enable */ -#define DEP1INTEN_IEP1INTEN BIT(1) /*!< IN Endpoint 1 interrupt enable */ - -/* device IN endpoint 1 interrupt enable register bits definitions */ -#define DIEP1INTEN_NAKEN BIT(13) /*!< NAK handshake sent by USBHS interrupt enable bit */ -#define DIEP1INTEN_IEPNEEN BIT(6) /*!< IN endpoint NAK effective interrupt enable bit */ -#define DIEP1INTEN_EPTXFUDEN BIT(4) /*!< endpoint Tx FIFO underrun interrupt enable bit */ -#define DIEP1INTEN_CITOEN BIT(3) /*!< control In Timeout interrupt enable bit */ -#define DIEP1INTEN_EPDISEN BIT(1) /*!< endpoint disabled interrupt enable bit */ -#define DIEP1INTEN_TFEN BIT(0) /*!< transfer finished interrupt enable bit */ - -/* device OUT endpoint 1 interrupt enable register bits definitions */ -#define DOEP1INTEN_NYETEN BIT(14) /*!< NYET handshake is sent interrupt enable bit */ -#define DOEP1INTEN_BTBSTPEN BIT(6) /*!< back-to-back SETUP packets interrupt enable bit */ -#define DOEP1INTEN_EPRXOVREN BIT(4) /*!< endpoint Rx FIFO over run interrupt enable bit */ -#define DOEP1INTEN_STPFEN BIT(3) /*!< SETUP phase finished interrupt enable bit */ -#define DOEP1INTEN_EPDISEN BIT(1) /*!< endpoint disabled interrupt enable bit */ -#define DOEP1INTEN_TFEN BIT(0) /*!< back-to-back SETUP packets interrupt enable bit */ - -/* device IN endpoint 0 control register bits definitions */ -#define DIEP0CTL_EPEN BIT(31) /*!< endpoint enable */ -#define DIEP0CTL_EPD BIT(30) /*!< endpoint disable */ -#define DIEP0CTL_SNAK BIT(27) /*!< set NAK */ -#define DIEP0CTL_CNAK BIT(26) /*!< clear NAK */ -#define DIEP0CTL_TXFNUM BITS(22, 25) /*!< tx FIFO number */ -#define DIEP0CTL_STALL BIT(21) /*!< STALL handshake */ -#define DIEP0CTL_EPTYPE BITS(18, 19) /*!< endpoint type */ -#define DIEP0CTL_NAKS BIT(17) /*!< NAK status */ -#define DIEP0CTL_EPACT BIT(15) /*!< endpoint active */ -#define DIEP0CTL_MPL BITS(0, 1) /*!< maximum packet length */ - -/* device IN endpoint x control register bits definitions */ -#define DIEPCTL_EPEN BIT(31) /*!< endpoint enable */ -#define DIEPCTL_EPD BIT(30) /*!< endpoint disable */ -#define DIEPCTL_SODDFRM BIT(29) /*!< set odd frame */ -#define DIEPCTL_SD1PID BIT(29) /*!< set DATA1 PID */ -#define DIEPCTL_SEVNFRM BIT(28) /*!< set even frame */ -#define DIEPCTL_SD0PID BIT(28) /*!< set DATA0 PID */ -#define DIEPCTL_SNAK BIT(27) /*!< set NAK */ -#define DIEPCTL_CNAK BIT(26) /*!< clear NAK */ -#define DIEPCTL_TXFNUM BITS(22, 25) /*!< tx FIFO number */ -#define DIEPCTL_STALL BIT(21) /*!< STALL handshake */ -#define DIEPCTL_EPTYPE BITS(18, 19) /*!< endpoint type */ -#define DIEPCTL_NAKS BIT(17) /*!< NAK status */ -#define DIEPCTL_EOFRM BIT(16) /*!< even/odd frame */ -#define DIEPCTL_DPID BIT(16) /*!< endpoint data PID */ -#define DIEPCTL_EPACT BIT(15) /*!< endpoint active */ -#define DIEPCTL_MPL BITS(0, 10) /*!< maximum packet length */ - -/* device OUT endpoint 0 control register bits definitions */ -#define DOEP0CTL_EPEN BIT(31) /*!< endpoint enable */ -#define DOEP0CTL_EPD BIT(30) /*!< endpoint disable */ -#define DOEP0CTL_SNAK BIT(27) /*!< set NAK */ -#define DOEP0CTL_CNAK BIT(26) /*!< clear NAK */ -#define DOEP0CTL_STALL BIT(21) /*!< STALL handshake */ -#define DOEP0CTL_SNOOP BIT(20) /*!< snoop mode */ -#define DOEP0CTL_EPTYPE BITS(18, 19) /*!< endpoint type */ -#define DOEP0CTL_NAKS BIT(17) /*!< NAK status */ -#define DOEP0CTL_EPACT BIT(15) /*!< endpoint active */ -#define DOEP0CTL_MPL BITS(0, 1) /*!< maximum packet length */ - -/* device OUT endpoint-x control register bits definitions */ -#define DOEPCTL_EPEN BIT(31) /*!< endpoint enable */ -#define DOEPCTL_EPD BIT(30) /*!< endpoint disable */ -#define DOEPCTL_SODDFRM BIT(29) /*!< set odd frame */ -#define DOEPCTL_SD1PID BIT(29) /*!< set DATA1 PID */ -#define DOEPCTL_SEVNFRM BIT(28) /*!< set even frame */ -#define DOEPCTL_SD0PID BIT(28) /*!< set DATA0 PID */ -#define DOEPCTL_SNAK BIT(27) /*!< set NAK */ -#define DOEPCTL_CNAK BIT(26) /*!< clear NAK */ -#define DOEPCTL_STALL BIT(21) /*!< STALL handshake */ -#define DOEPCTL_SNOOP BIT(20) /*!< snoop mode */ -#define DOEPCTL_EPTYPE BITS(18, 19) /*!< endpoint type */ -#define DOEPCTL_NAKS BIT(17) /*!< NAK status */ -#define DOEPCTL_EOFRM BIT(16) /*!< even/odd frame */ -#define DOEPCTL_DPID BIT(16) /*!< endpoint data PID */ -#define DOEPCTL_EPACT BIT(15) /*!< endpoint active */ -#define DOEPCTL_MPL BITS(0, 10) /*!< maximum packet length */ - -/* device IN endpoint-x interrupt flag register bits definitions */ -#define DIEPINTF_NAK BIT(13) /*!< NAK handshake sent by USBHS */ -#define DIEPINTF_TXFE BIT(7) /*!< transmit FIFO empty */ -#define DIEPINTF_IEPNE BIT(6) /*!< IN endpoint NAK effective */ -#define DIEPINTF_EPTXFUD BIT(4) /*!< endpoint Tx FIFO underrun */ -#define DIEPINTF_CITO BIT(3) /*!< control In Timeout interrupt */ -#define DIEPINTF_EPDIS BIT(1) /*!< endpoint disabled */ -#define DIEPINTF_TF BIT(0) /*!< transfer finished */ - -/* device OUT endpoint-x interrupt flag register bits definitions */ -#define DOEPINTF_NYET BIT(14) /*!< NYET handshake is sent */ -#define DOEPINTF_BTBSTP BIT(6) /*!< back-to-back SETUP packets */ -#define DOEPINTF_EPRXFOVR BIT(4) /*!< endpoint Rx FIFO overrun */ -#define DOEPINTF_STPF BIT(3) /*!< SETUP phase finished */ -#define DOEPINTF_EPDIS BIT(1) /*!< endpoint disabled */ -#define DOEPINTF_TF BIT(0) /*!< transfer finished */ - -/* device IN endpoint 0 transfer length register bits definitions */ -#define DIEP0LEN_PCNT BITS(19, 20) /*!< packet count */ -#define DIEP0LEN_TLEN BITS(0, 6) /*!< transfer length */ - -/* device OUT endpoint 0 transfer length register bits definitions */ -#define DOEP0LEN_STPCNT BITS(29, 30) /*!< SETUP packet count */ -#define DOEP0LEN_PCNT BIT(19) /*!< packet count */ -#define DOEP0LEN_TLEN BITS(0, 6) /*!< transfer length */ - -/* device IN endpoint-x transfer length register bits definitions */ -#define DIEPLEN_MCNT BITS(29, 30) /*!< multi count */ -#define DIEPLEN_PCNT BITS(19, 28) /*!< packet count */ -#define DIEPLEN_TLEN BITS(0, 18) /*!< transfer length */ - -/* device OUT endpoint-x transfer length register bits definitions */ -#define DOEPLEN_RXDPID BITS(29, 30) /*!< received data PID */ -#define DOEPLEN_STPCNT BITS(29, 30) /*!< SETUP packet count */ -#define DOEPLEN_PCNT BITS(19, 28) /*!< packet count */ -#define DOEPLEN_TLEN BITS(0, 18) /*!< transfer length */ - -/* device IN endpoint-x DMA address register bits definitions */ -#define DIEPDMAADDR_DMAADDR BITS(0, 31) /*!< DMA address */ - -/* device OUT endpoint-x DMA address register bits definitions */ -#define DOEPDMAADDR_DMAADDR BITS(0, 31) /*!< DMA address */ - -/* device IN endpoint-x transmit FIFO status register bits definitions */ -#define DIEPTFSTAT_IEPTFS BITS(0, 15) /*!< IN endpoint��s Tx FIFO space remaining */ - -/* USB power and clock registers bits definition */ -#define PWRCLKCTL_SHCLK BIT(1) /*!< stop HCLK */ -#define PWRCLKCTL_SUCLK BIT(0) /*!< stop the USB clock */ - -/* register options defines */ -#define DCFG_DEVSPEED(regval) (DCFG_DS & ((regval) << 0U)) /*!< device speed configuration */ - -#define USB_SPEED_EXP_HIGH DCFG_DEVSPEED(0U) /*!< device external PHY high speed */ -#define USB_SPEED_EXP_FULL DCFG_DEVSPEED(1U) /*!< device external PHY full speed */ -#define USB_SPEED_INP_FULL DCFG_DEVSPEED(3U) /*!< device internal PHY full speed */ - -#define GAHBCS_TFEL(regval) (GAHBCS_TXFTH & ((regval) << 7U)) /*!< device speed configuration */ - -#define TXFIFO_EMPTY_HALF GAHBCS_TFEL(0U) /*!< Tx FIFO half empty */ -#define TXFIFO_EMPTY GAHBCS_TFEL(1U) /*!< Tx FIFO completely empty */ - -#define GAHBCS_DMAINCR(regval) (GAHBCS_BURST & ((regval) << 1U)) /*!< AHB burst type used by DMA*/ - -#define DMA_INCR0 GAHBCS_DMAINCR(0U) /*!< single burst type used by DMA*/ -#define DMA_INCR1 GAHBCS_DMAINCR(1U) /*!< 4-beat incrementing burst type used by DMA*/ -#define DMA_INCR4 GAHBCS_DMAINCR(3U) /*!< 8-beat incrementing burst type used by DMA*/ -#define DMA_INCR8 GAHBCS_DMAINCR(5U) /*!< 16-beat incrementing burst type used by DMA*/ -#define DMA_INCR16 GAHBCS_DMAINCR(7U) /*!< 32-beat incrementing burst type used by DMA*/ - -#define DCFG_PFRI(regval) (DCFG_EOPFT & ((regval) << 11U)) /*!< end of periodic frame time configuration */ - -#define FRAME_INTERVAL_80 DCFG_PFRI(0U) /*!< 80% of the frame time */ -#define FRAME_INTERVAL_85 DCFG_PFRI(1U) /*!< 85% of the frame time */ -#define FRAME_INTERVAL_90 DCFG_PFRI(2U) /*!< 90% of the frame time */ -#define FRAME_INTERVAL_95 DCFG_PFRI(3U) /*!< 95% of the frame time */ - -#define DEP0CTL_MPL(regval) (DOEP0CTL_MPL & ((regval) << 0U)) /*!< maximum packet length configuration */ - -#define EP0MPL_64 DEP0CTL_MPL(0U) /*!< maximum packet length 64 bytes */ -#define EP0MPL_32 DEP0CTL_MPL(1U) /*!< maximum packet length 32 bytes */ -#define EP0MPL_16 DEP0CTL_MPL(2U) /*!< maximum packet length 16 bytes */ -#define EP0MPL_8 DEP0CTL_MPL(3U) /*!< maximum packet length 8 bytes */ - -/* endpoints address */ - -/* first bit is direction(0 for Rx and 1 for Tx) */ -#define EP0_OUT ((uint8_t)0x00U) /*!< endpoint out 0 */ -#define EP0_IN ((uint8_t)0x80U) /*!< endpoint in 0 */ -#define EP1_OUT ((uint8_t)0x01U) /*!< endpoint out 1 */ -#define EP1_IN ((uint8_t)0x81U) /*!< endpoint in 1 */ -#define EP2_OUT ((uint8_t)0x02U) /*!< endpoint out 2 */ -#define EP2_IN ((uint8_t)0x82U) /*!< endpoint in 2 */ -#define EP3_OUT ((uint8_t)0x03U) /*!< endpoint out 3 */ -#define EP3_IN ((uint8_t)0x83U) /*!< endpoint in 3 */ - -/* enable global interrupt */ -#define USB_GLOBAL_INT_ENABLE() (USB_GAHBCS |= GAHBCS_GINTEN) - -/* disable global interrupt */ -#define USB_GLOBAL_INT_DISABLE() (USB_GAHBCS &= ~GAHBCS_GINTEN) - -/* get current operation mode */ -#define USB_CURRENT_MODE_GET() (USB_GINTF & GINTF_COPM) - -/* read global interrupt flag */ -#define USB_CORE_INTR_READ(x) \ -do { \ - uint32_t global_intf = USB_GINTF; \ - (x) = global_intf & USB_GINTEN; \ -} while(0) - -/* read global interrupt flag */ -#define USB_DAOEP_INTR_READ(x) \ -do { \ - uint32_t dev_all_ep_inten = USB_DAEPINTEN; \ - uint32_t dev_all_ep_int = USB_DAEPINT; \ - uint32_t out_ep_intb = DAEPINT_OEPITB; \ - (x) = (dev_all_ep_inten & dev_all_ep_int & out_ep_intb) >> 16; \ -} while(0) - -/* read out endpoint-x interrupt flag */ -#define USB_DOEP_INTR_READ(x, EpID) \ -do { \ - uint32_t out_epintf = USB_DOEPxINTF(EpID); \ - (x) = out_epintf & USB_DOEPINTEN; \ -} while(0) - -/* read all in endpoint interrupt flag */ -#define USB_DAIEP_INTR_READ(x) \ -do { \ - uint32_t dev_all_ep_inten = USB_DAEPINTEN; \ - uint32_t dev_all_ep_int = USB_DAEPINT; \ - uint32_t in_ep_intb = DAEPINT_IEPITB; \ - (x) = dev_all_ep_inten & dev_all_ep_int & in_ep_intb; \ -} while(0) - - -/* read in endpoint-x interrupt flag */ -#define USB_DIEP_INTR_READ(x, EpID) \ -do { \ - uint32_t dev_ep_intf = USB_DIEPxINTF(EpID); \ - uint32_t dev_ep_fifoempty_intf = (((USB_DIEPFEINTEN >> (EpID)) & 0x1U) << 7U); \ - uint32_t dev_inep_inten = USB_DIEPINTEN; \ - (x) = dev_ep_intf & (dev_ep_fifoempty_intf | dev_inep_inten); \ -} while(0) - -/* generate remote wakup signal */ -#define USB_REMOTE_WAKEUP_SET() (USB_DCTL |= DCTL_RWKUP) - -/* no remote wakup signal generate */ -#define USB_REMOTE_WAKEUP_RESET() (USB_DCTL &= ~DCTL_RWKUP) - -/* generate soft disconnect */ -#define USB_SOFT_DISCONNECT_ENABLE() (USB_DCTL |= DCTL_SD) - -/* no soft disconnect generate */ -#define USB_SOFT_DISCONNECT_DISABLE() (USB_DCTL &= ~DCTL_SD) - -/* set device address */ -#define USB_SET_DEVADDR(DevAddr) (USB_DCFG |= (DevAddr) << 4U) - -/* check whether frame is even */ -#define USB_EVEN_FRAME() (!(USB_HFINFR & 0x01U)) - -/* read port status */ -#define USB_PORT_READ() (USB_HPCS & (~HPCS_PE) & (~HPCS_PCD) & (~HPCS_PEDC)) - -/* usb clock initialize */ -#define USB_FSLSCLOCK_INIT(ClockFreq) (USB_HCTL &= ~HCTL_CLKSEL | (ClockFreq)) - -/* get usb current speed */ -#define USB_CURRENT_SPEED_GET() ((USB_HPCS & HPCS_PS) >> 17) - -/* get usb current frame */ -#define USB_CURRENT_FRAME_GET() (USB_HFINFR & 0xFFFFU) - -#endif /* USB_REGS_H */ diff --git a/bsp/gd32450z-eval/Libraries/GD32F4xx_usb_driver/Include/usb_std.h b/bsp/gd32450z-eval/Libraries/GD32F4xx_usb_driver/Include/usb_std.h deleted file mode 100644 index b7fa5d8e9a..0000000000 --- a/bsp/gd32450z-eval/Libraries/GD32F4xx_usb_driver/Include/usb_std.h +++ /dev/null @@ -1,188 +0,0 @@ -/*! - \file usb_std.h - \brief USB 2.0 standard defines -*/ - -/* - Copyright (C) 2016 GigaDevice - - 2016-08-15, V1.0.0, firmware for GD32F4xx -*/ - -#ifndef USB_STD_H -#define USB_STD_H - -#include "usb_conf.h" - -#define USB_DEV_QUALIFIER_DESC_LEN 0x0AU /*!< USB device qualifier descriptor length */ -#define USB_DEV_DESC_LEN 0x12U /*!< USB device descriptor length */ -#define USB_CFG_DESC_LEN 0x09U /*!< USB device configuration descriptor length */ -#define USB_IF_DESC_LEN 0x09U /*!< USB device interface descriptor length */ -#define USB_EP_DESC_LEN 0x07U /*!< USB device endpoint descriptor length */ -#define USB_OTG_DESC_LEN 0x03U /*!< USB device OTG descriptor length */ - -/* bit 7 of bmRequestType: data phase transfer direction */ -#define USB_DIR_MASK 0x80U /*!< USB transfer direction mask */ -#define USB_DIR_OUT 0x00U /*!< USB transfer OUT direction */ -#define USB_DIR_IN 0x80U /*!< USB transfer IN direction */ - -/* bit 6..5 of bmRequestType: request type */ -#define USB_STANDARD_REQ 0x00U /*!< USB standard request */ -#define USB_CLASS_REQ 0x20U /*!< USB class request */ -#define USB_VENDOR_REQ 0x40U /*!< USB vebdor request */ -#define USB_REQ_MASK 0x60U /*!< USB request mask */ - -/* bit 4..0 of bmRequestType: recipient type */ -#define USB_REQTYPE_DEVICE 0x00U /*!< USB device request type */ -#define USB_REQTYPE_INTERFACE 0x01U /*!< USB interface request type*/ -#define USB_REQTYPE_ENDPOINT 0x02U /*!< USB endpoint request type*/ -#define USB_REQTYPE_MASK 0x03U /*!< USB request type mask*/ - -/* bRequest value */ -#define USBREQ_GET_STATUS 0x00U /*!< USB get status request*/ -#define USBREQ_CLEAR_FEATURE 0x01U /*!< USB clear feature request*/ -#define USBREQ_SET_FEATURE 0x03U /*!< USB set feature request*/ -#define USBREQ_SET_ADDRESS 0x05U /*!< USB set address request*/ -#define USBREQ_GET_DESCRIPTOR 0x06U /*!< USB get descriptor request*/ -#define USBREQ_SET_DESCRIPTOR 0x07U /*!< USB set descriptor request*/ -#define USBREQ_GET_CONFIGURATION 0x08U /*!< USB get configuration request*/ -#define USBREQ_SET_CONFIGURATION 0x09U /*!< USB set configuration request*/ -#define USBREQ_GET_INTERFACE 0x0AU /*!< USB get interface request*/ -#define USBREQ_SET_INTERFACE 0x0BU /*!< USB set interface request*/ -#define USBREQ_SYNCH_FRAME 0x0CU /*!< USB synchronize frame request*/ - -/* descriptor types of usb specifications */ -#define USB_DESCTYPE_DEVICE 0x01U /*!< USB device descriptor type*/ -#define USB_DESCTYPE_CONFIGURATION 0x02U /*!< USB configuration descriptor type*/ -#define USB_DESCTYPE_STRING 0x03U /*!< USB string descriptor type*/ -#define USB_DESCTYPE_INTERFACE 0x04U /*!< USB interface descriptor type*/ -#define USB_DESCTYPE_ENDPOINT 0x05U /*!< USB endpoint descriptor type*/ -#define USB_DESCTYPE_DEVICE_QUALIFIER 0x06U /*!< USB device qualtfier descriptor type*/ -#define USB_DESCTYPE_OTHER_SPEED_CONFIGURATION 0x07U /*!< USB other speed configuration descriptor type*/ -#define USB_DESCTYPE_INTERFACE_POWER 0x08U /*!< USB interface power descriptor type*/ - -#define USB_DESCTYPE_HID 0x21U /*!< USB HID descriptor type*/ -#define USB_DESCTYPE_HID_REPORT 0x22U /*!< USB HID report descriptor type*/ - -#define USB_DEVDESC_SIZE 18U /*!< USB device descriptor size*/ -#define USB_CFGDESC_SIZE 9U /*!< USB configure descriptor size*/ -#define USB_INTDESC_SIZE 9U /*!< USB interface descriptor size*/ -#define USB_EPDESC_SIZE 7U /*!< USB endpoint descriptor size*/ - -/* descriptor type and descriptor index */ -/* use the following values when USB host need to get descriptor */ -#define USB_DEVDESC ((USB_DESCTYPE_DEVICE << 8U) & 0xFF00U) /*!< USB device operation marco */ -#define USB_CFGDESC ((USB_DESCTYPE_CONFIGURATION << 8U) & 0xFF00U) /*!< USB configuration operation marco */ -#define USB_STRDESC ((USB_DESCTYPE_STRING << 8U) & 0xFF00U) /*!< USB string operation marco */ -#define USB_INTDESC ((USB_DESCTYPE_INTERFACE << 8U) & 0xFF00U) /*!< USB interface operation marco */ -#define USB_EPDESC ((USB_DESCTYPE_INTERFACE << 8U) & 0xFF00U) /*!< USB endpoint operation marco */ -#define USB_DEVQUADESC ((USB_DESCTYPE_DEVICE_QUALIFIER << 8U) & 0xFF00U) /*!< USB device qualifier operation marco */ -#define USB_OSPCFGDESC ((USB_DESCTYPE_OTHER_SPEED_CONFIGURATION << 8U) & 0xFF00U) /*!< USB other speed configuration operation marco */ -#define USB_INTPWRDESC ((USB_DESCTYPE_INTERFACE_POWER << 8U) & 0xFF00U) /*!< USB interface power operation marco */ -#define USB_HIDREPDESC ((USB_DESCTYPE_HID_REPORT << 8U) & 0xFF00U) /*!< USB HID report operation marco */ -#define USB_HIDDESC ((USB_DESCTYPE_HID << 8U) & 0xFF00U) /*!< USB HID operation marco */ - -#define SWAPBYTE(addr) (((uint16_t)(*((uint8_t *)(addr)))) + \ - (uint16_t)(((uint16_t)(*(((uint8_t *)(addr)) + 1U))) << 8U)) - -/* supported classes */ -#define USB_MSC_CLASS 0x08U /*!< USB MSC class*/ -#define USB_HID_CLASS 0x03U /*!< USB HID class*/ - -/* interface descriptor field values for hid boot protocol */ -#define HID_BOOT_CODE 0x01U /*!< USB HID boot code*/ -#define HID_KEYBRD_BOOT_CODE 0x01U /*!< USB HID keyboard boot code*/ -#define HID_MOUSE_BOOT_CODE 0x02U /*!< USB HID mouse boot code*/ - -/* as per usb specs 9.2.6.4 :standard request with data request timeout: 5sec - standard request with no data stage timeout : 50ms */ -#define DATA_STAGE_TIMEOUT 5000U /*!< USB data stage timeout*/ -#define NODATA_STAGE_TIMEOUT 50U /*!< USB no data stage timeout*/ - -#define USBH_CFG_DESC_SET_SIZE (USB_CFGDESC_SIZE + USB_INTDESC_SIZE \ - + (USBH_MAX_EP_NUM * USB_EPDESC_SIZE)) /*!< USB host set configuration descriptor size */ - -#pragma pack(1) - -typedef union -{ - uint8_t data[8]; - - struct _setup_packet_struct - { - uint8_t bmRequestType; /*!< type of request */ - uint8_t bRequest; /*!< request of setup packet */ - uint16_t wValue; /*!< value of setup packet */ - uint16_t wIndex; /*!< index of setup packet */ - uint16_t wLength; /*!< length of setup packet */ - } b; -}usb_setup_union; - -typedef struct -{ - uint8_t bLength; /*!< size of the descriptor */ - uint8_t bDescriptorType; /*!< type of the descriptor */ -} usb_descriptor_header_struct; - -typedef struct -{ - usb_descriptor_header_struct Header; /*!< descriptor header, including type and size */ - - uint16_t bcdUSB; /*!< BCD of the supported USB specification */ - uint8_t bDeviceClass; /*!< USB device class */ - uint8_t bDeviceSubClass; /*!< USB device subclass */ - uint8_t bDeviceProtocol; /*!< USB device protocol */ - uint8_t bMaxPacketSize0; /*!< size of the control (address 0) endpoint's bank in bytes */ - uint16_t idVendor; /*!< vendor ID for the USB product */ - uint16_t idProduct; /*!< unique product ID for the USB product */ - uint16_t bcdDevice; /*!< product release (version) number */ - uint8_t iManufacturer; /*!< string index for the manufacturer's name */ - uint8_t iProduct; /*!< string index for the product name/details */ - uint8_t iSerialNumber; /*!< string index for the product's globally unique hexadecimal serial number */ - uint8_t bNumberConfigurations; /*!< total number of configurations supported by the device */ -} usb_descriptor_device_struct; - -typedef struct -{ - usb_descriptor_header_struct Header; /*!< descriptor header, including type and size */ - - uint16_t wTotalLength; /*!< size of the configuration descriptor header,and all sub descriptors inside the configuration */ - uint8_t bNumInterfaces; /*!< total number of interfaces in the configuration */ - uint8_t bConfigurationValue; /*!< configuration index of the current configuration */ - uint8_t iConfiguration; /*!< index of a string descriptor describing the configuration */ - uint8_t bmAttributes; /*!< configuration attributes */ - uint8_t bMaxPower; /*!< maximum power consumption of the device while in the current configuration */ -} usb_descriptor_configuration_struct; - -typedef struct -{ - usb_descriptor_header_struct Header; /*!< descriptor header, including type and size */ - - uint8_t bInterfaceNumber; /*!< index of the interface in the current configuration */ - uint8_t bAlternateSetting; /*!< alternate setting for the interface number */ - uint8_t bNumEndpoints; /*!< total number of endpoints in the interface */ - uint8_t bInterfaceClass; /*!< interface class ID */ - uint8_t bInterfaceSubClass; /*!< interface subclass ID */ - uint8_t bInterfaceProtocol; /*!< interface protocol ID */ - uint8_t iInterface; /*!< index of the string descriptor describing the interface */ -} usb_descriptor_interface_struct; - -typedef struct -{ - usb_descriptor_header_struct Header; /*!< descriptor header, including type and size. */ - - uint8_t bEndpointAddress; /*!< logical address of the endpoint */ - uint8_t bmAttributes; /*!< endpoint attributes */ - uint16_t wMaxPacketSize; /*!< size of the endpoint bank, in bytes */ - uint8_t bInterval; /*!< polling interval in milliseconds for the endpoint if it is an INTERRUPT or ISOCHRONOUS type */ -} usb_descriptor_endpoint_struct; - -typedef struct -{ - usb_descriptor_header_struct Header; /*!< descriptor header, including type and size. */ - uint16_t wLANGID; /*!< LANGID code */ -}usb_descriptor_language_id_struct; - -#pragma pack() - -#endif /* USB_STD_H */ diff --git a/bsp/gd32450z-eval/Libraries/GD32F4xx_usb_driver/Include/usbd_core.h b/bsp/gd32450z-eval/Libraries/GD32F4xx_usb_driver/Include/usbd_core.h deleted file mode 100644 index 8b79c2ed5a..0000000000 --- a/bsp/gd32450z-eval/Libraries/GD32F4xx_usb_driver/Include/usbd_core.h +++ /dev/null @@ -1,54 +0,0 @@ -/*! - \file usbd_core.h - \brief USB device-mode core driver header file -*/ - -/* - Copyright (C) 2016 GigaDevice - - 2016-08-15, V1.0.0, firmware for GD32F4xx -*/ - - -#ifndef USBD_CORE_H -#define USBD_CORE_H - -#include "usbd_conf.h" -#include "usb_core.h" -#include "usbd_std.h" - -/* device status */ -#define USB_STATUS_DEFAULT 1U /* default status */ -#define USB_STATUS_ADDRESSED 2U /* addressed status */ -#define USB_STATUS_CONFIGURED 3U /* configured status */ -#define USB_STATUS_SUSPENDED 4U /* suspended status */ - -/* function declarations */ -/* initailizes the USB device-mode handler stack */ -void usbd_init (usb_core_handle_struct *pudev, usb_core_id_enum core_id); -/* endpoint initialization */ -void usbd_ep_init (usb_core_handle_struct *pudev, const usb_descriptor_endpoint_struct *pep_desc); -/* endpoint deinitialize */ -void usbd_ep_deinit (usb_core_handle_struct *pudev, uint8_t ep_addr); -/* endpoint prepare to receive data */ -void usbd_ep_rx (usb_core_handle_struct *pudev, uint8_t ep_addr, uint8_t *pbuf, uint16_t buf_len); -/* endpoint prepare to transmit data */ -void usbd_ep_tx (usb_core_handle_struct *pudev, uint8_t ep_addr, uint8_t *pbuf, uint32_t buf_len); -/* transmit data on the control channel */ -usbd_status_enum usbd_ctltx (usb_core_handle_struct *pudev, uint8_t *pbuf, uint16_t len); -/* receive data on the control channel */ -usbd_status_enum usbd_ctlrx (usb_core_handle_struct *pudev, uint8_t *pbuf, uint16_t len); -/* transmit status on the control channel */ -usbd_status_enum usbd_ctlstatus_tx (usb_core_handle_struct *pudev); -/* receive status on the control channel */ -usbd_status_enum usbd_ctlstatus_rx (usb_core_handle_struct *pudev); -/* set an endpoint to STALL status */ -void usbd_ep_stall (usb_core_handle_struct *pudev, uint8_t ep_addr); -/* clear endpoint stalled status */ -void usbd_ep_clear_stall (usb_core_handle_struct *pudev, uint8_t ep_addr); -/* flushes the FIFOs */ -void usbd_ep_fifo_flush (usb_core_handle_struct *pudev, uint8_t ep_addr); -/* get the received data length */ -uint16_t usbd_rxcount_get (usb_core_handle_struct *pudev, uint8_t ep_id); - -#endif /* USBD_CORE_H */ diff --git a/bsp/gd32450z-eval/Libraries/GD32F4xx_usb_driver/Include/usbd_int.h b/bsp/gd32450z-eval/Libraries/GD32F4xx_usb_driver/Include/usbd_int.h deleted file mode 100644 index 3247853be5..0000000000 --- a/bsp/gd32450z-eval/Libraries/GD32F4xx_usb_driver/Include/usbd_int.h +++ /dev/null @@ -1,31 +0,0 @@ -/*! - \file usbd_int.h - \brief USB device-mode interrupt handler header file -*/ - -/* - Copyright (C) 2016 GigaDevice - - 2016-08-15, V1.0.0, firmware for GD32F4xx -*/ - -#ifndef USBD_INT_H -#define USBD_INT_H - -#include "usbd_core.h" - -/* function declarations */ -/* USB device-mode interrupts global service routine handler */ -uint32_t usbd_isr (usb_core_handle_struct *pudev); - -#ifdef USBHS_DEDICATED_EP1_ENABLED - -/* USB dedicated OUT endpoint 1 interrupt service routine handler */ -uint32_t USBD_EP1OUT_ISR_Handler (usb_core_handle_struct *pudev); -/* USB dedicated IN endpoint 1 interrupt service routine handler */ -uint32_t USBD_EP1IN_ISR_Handler (usb_core_handle_struct *pudev); - -#endif /* USBHS_DEDICATED_EP1_ENABLED */ - -#endif /* USBD_INT_H */ - diff --git a/bsp/gd32450z-eval/Libraries/GD32F4xx_usb_driver/Include/usbd_std.h b/bsp/gd32450z-eval/Libraries/GD32F4xx_usb_driver/Include/usbd_std.h deleted file mode 100644 index 494f0ec3aa..0000000000 --- a/bsp/gd32450z-eval/Libraries/GD32F4xx_usb_driver/Include/usbd_std.h +++ /dev/null @@ -1,70 +0,0 @@ -/*! - \file usbd_std.h - \brief USB 2.0 standard driver -*/ - -/* - Copyright (C) 2016 GigaDevice - - 2016-06-30, V1.0.0, firmware for GD32F4xx -*/ - -#ifndef USBD_STD_H -#define USBD_STD_H - -#include "usb_std.h" -#include "usbd_core.h" -#include "usbd_conf.h" -#include <wchar.h> - -#define USBD_LANGID_STR_IDX 0x00U /*!< USB language ID string index*/ -#define USBD_MFC_STR_IDX 0x01U /*!< USB manufacturer string index*/ -#define USBD_PRODUCT_STR_IDX 0x02U /*!< USB product string index*/ -#define USBD_SERIAL_STR_IDX 0x03U /*!< USB serial string index*/ -#define USBD_CONFIG_STR_IDX 0x04U /*!< USB configuration string index*/ -#define USBD_INTERFACE_STR_IDX 0x05U /*!< USB interface string index*/ - -#define USB_STATUS_REMOTE_WAKEUP 0x02U /*!< USB remote wakeup status*/ -#define USB_STATUS_SELF_POWERED 0x01U /*!< USB self power status*/ - -#define USB_FEATURE_ENDP_HALT 0x00U /*!< USB halt endpoint feature*/ -#define USB_FEATURE_REMOTE_WAKEUP 0x01U /*!< USB remote wakeup feature*/ -#define USB_FEATURE_TEST_MODE 0x02U /*!< USB test mode feature*/ - -#define ENG_LANGID 0x0409U /*!< USB english language id*/ -#define CHN_LANGID 0x0804U /*!< USB chinese language id*/ - -#define USB_DEVICE_DESC_SIZE 0x12U /*!< USB device descriptor size*/ - -#define LOWBYTE(x) ((uint8_t)((x) & 0x00FFU)) /*!< USB lowbyte operation marco*/ -#define HIGHBYTE(x) ((uint8_t)(((x) & 0xFF00U) >> 8U)) /*!< USB highbyte operation marco*/ - -#define USB_MIN(a, b) (((a) < (b)) ? (a) : (b)) /*!< USB minimum operation marco*/ - -#define WIDE_STRING(string) _WIDE_STRING(string) -#define _WIDE_STRING(string) L##string - -#define USBD_STRING_DESC(string) \ - (uint8_t *)&(struct { \ - uint8_t _len; \ - uint8_t _type; \ - wchar_t _data[sizeof(string)]; \ - }) { \ - sizeof(WIDE_STRING(string)) + 2U - 2U, \ - USB_DESCTYPE_STRING, \ - WIDE_STRING(string) \ - } - -#define IS_NOT_EP0(ep_addr) (((ep_addr) != 0x00U) && ((ep_addr) != 0x80U)) - -/* function declarations */ -/* USB device setup transaction*/ -usbd_status_enum usbd_setup_transaction (usb_core_handle_struct *pudev); -/* USB device out transaction*/ -usbd_status_enum usbd_out_transaction (usb_core_handle_struct *pudev, uint8_t endp_num); -/* USB device in transaction*/ -usbd_status_enum usbd_in_transaction (usb_core_handle_struct *pudev, uint8_t endp_num); -/* USB device enum error handle*/ -void usbd_enum_error (usb_core_handle_struct *pudev, usb_device_req_struct *req); - -#endif /* USBD_STD_H */ diff --git a/bsp/gd32450z-eval/Libraries/GD32F4xx_usb_driver/Include/usbh_core.h b/bsp/gd32450z-eval/Libraries/GD32F4xx_usb_driver/Include/usbh_core.h deleted file mode 100644 index f4e8739687..0000000000 --- a/bsp/gd32450z-eval/Libraries/GD32F4xx_usb_driver/Include/usbh_core.h +++ /dev/null @@ -1,283 +0,0 @@ -/*! - \file usbh_core.h - \brief header file for usbh_core.c -*/ - -/* - Copyright (C) 2016 GigaDevice - - 2016-08-15, V1.0.1, firmware for GD32F4xx -*/ - -#ifndef USBH_CORE_H -#define USBH_CORE_H - -#include "usbh_conf.h" -#include "usb_std.h" -#include "usb_core.h" - -#define MSC_CLASS 0x08 /*!< the MSC class define */ -#define HID_CLASS 0x03 /*!< the HID class define */ -#define MSC_PROTOCOL 0x50 /*!< the MSC protocal define */ -#define CBI_PROTOCOL 0x01 /*!< the CBI protocal define */ - -#define USBH_DEVICE_ADDRESS_DEFAULT 0U /*!< the default device address define */ -#define USBH_DEVICE_ADDRESS 1U /*!< the device address define */ -#define USBH_MAX_ERROR_COUNT 2U /*!< the max error count define */ - -#define HOST_USER_SELECT_CONFIGURATION 1U /*!< the user select configuration define */ -#define HOST_USER_CLASS_ACTIVE 2U /*!< the user class active define */ -#define HOST_USER_CLASS_SELECTED 3U /*!< the user class selected define */ -#define HOST_USER_CONNECTION 4U /*!< the user connecttion define */ -#define HOST_USER_DISCONNECTION 5U /*!< the user disconnection define */ -#define HOST_USER_UNRECOVERED_ERROR 6U /*!< the user unrecovered error define */ - -#define MAX_USBH_STATE_STACK_DEEP 4 /*!< the max state stack deep define */ -#define MAX_USBH_STATE_TABLE_NUM 10U /*!< the max state table number */ - -#define HOST_FSM_ID 0U /*!< the host state table id */ -#define ENUM_FSM_ID 1U /*!< the enum state table id */ -#define CMD_FSM_ID 2U /*!< the cmd state table id */ -#define CTRL_FSM_ID 3U /*!< the ctrl state table id */ -#define CLASS_REQ_FSM_ID 4U /*!< the class req state table id */ -#define CLASS_FSM_ID 5U /*!< the class state table id */ - -#define UP_STATE 100U /*!< up state define */ -#define GO_TO_UP_STATE_EVENT 100U /*!< go to up state event define */ - -#define HOST_HANDLE_TABLE_SIZE 9U /*!< the host handle table size define */ - -/* the enum of host state */ -typedef enum -{ - HOST_IDLE = 0, /* the host idle state definition */ - HOST_DEV_ATTACHED, /* the host device attached state definition */ - HOST_DEV_DETACHED, /* the host device detached state definition */ - HOST_DETECT_DEV_SPEED, /* the host detect device speed state definition */ - HOST_ENUMERATION, /* the host enumeration state definition */ - HOST_CLASS_REQUEST, /* the host class request state definition */ - HOST_CLASS, /* the host class state definition */ - HOST_USER_INPUT, /* the host user input state definition */ - HOST_SUSPENDED, /* the host suspended state definition */ - HOST_ERROR /* the host error state definition */ -}host_state_enum; - -/* the enum of host event */ -typedef enum -{ - HOST_EVENT_ATTACHED = 0, /* the host attached event */ - HOST_EVENT_ENUM, /* the host enum event */ - HOST_EVENT_USER_INPUT, /* the host user input event */ - HOST_EVENT_CLASS_REQ, /* the host class request event */ - HOST_EVENT_CLASS, /* the host class event */ - HOST_EVENT_ERROR, /* the host error event */ - HOST_EVENT_DEV_DETACHED, /* the host device detached event */ - HOST_EVENT_IDLE /* the host idle event */ -}host_event_enum; - -/* the enum of enum state */ -typedef enum -{ - ENUM_IDLE = 0, /* the enum idle state definition */ - ENUM_SET_ADDR, /* the enum set address state definition */ - ENUM_GET_FULL_DEV_DESC, /* the enum get full device descripter state definition */ - ENUM_GET_CFG_DESC, /* the enum get configuration descripter state definition */ - ENUM_GET_FULL_CFG_DESC, /* the enum get full configuration descripter state definition */ - ENUM_GET_MFC_STRING_DESC, /* the enum get MFC string descripter state definition */ - ENUM_GET_PRODUCT_STRING_DESC, /* the enum get product string descripter state definition */ - ENUM_GET_SERIALNUM_STRING_DESC, /* the enum get serialnum string descripter state definition */ - ENUM_SET_CONFIGURATION, /* the enum set congiguration state definition */ - ENUM_DEV_CONFIGURED /* the enum device configuration state definition */ -}enum_state_enum; - -/* the enum of ctrl state */ -typedef enum -{ - CTRL_IDLE = 0, /* the ctrl idle state definition */ - CTRL_SETUP, /* the ctrl setup state definition */ - CTRL_DATA, /* the ctrl data state definition */ - CTRL_STATUS, /* the ctrl status state definition */ - CTRL_ERROR, /* the ctrl error state definition */ - CTRL_STALLED, /* the ctrl stalled state definition */ - CTRL_COMPLETE /* the ctrl complete state definition */ -}ctrl_state_enum; - -/* the enum of host status */ -typedef enum -{ - USBH_OK = 0, /* the usbh ok status definition */ - USBH_BUSY, /* the usbh busy status definition */ - USBH_FAIL, /* the usbh fail status definition */ - USBH_NOT_SUPPORTED, /* the usbh not supported status definition */ - USBH_UNRECOVERED_ERROR, /* the usbh unrecovered error status definition */ - USBH_SPEED_UNKNOWN_ERROR, /* the usbh speed unknown error status definition */ - USBH_APPLY_DEINIT /* the usbh apply deinit status definition */ -}usbh_status_enum; - -/* the state of user action */ -typedef enum -{ - USBH_USER_NO_RESP = 0, /* the user no response */ - USBH_USER_RESP_OK = 1, /* the user response ok */ -}usbh_user_status_enum; - -/* control transfer information */ -typedef struct -{ - uint8_t hc_in_num; /* the host in channel number */ - uint8_t hc_out_num; /* the host out channel number */ - uint8_t ep0_size; /* the endpoint 0 max packet size */ - uint8_t error_count; /* the error count */ - uint16_t length; /* the length */ - uint16_t timer; /* the timer */ - uint8_t *buff; /* the buffer */ - usb_setup_union setup; /* the setup packet */ -}usbh_ctrl_struct; - -/* device property */ -typedef struct -{ - uint8_t address; /* the device address */ - uint8_t speed; /* the device speed */ - usb_descriptor_device_struct dev_desc; /* the device descripter */ - usb_descriptor_configuration_struct cfg_desc; /* the configuration descripter */ - usb_descriptor_interface_struct itf_desc[USBH_MAX_INTERFACES_NUM]; /* the interface descripter */ - usb_descriptor_endpoint_struct ep_desc[USBH_MAX_INTERFACES_NUM][USBH_MAX_EP_NUM]; /* the endpoint descripter */ -}usbh_device_struct; - -/* user callbacks */ -typedef struct -{ - void (*init) (void); /* the user callback init function */ - void (*deinit) (void); /* the user callback deinit function */ - void (*device_connected) (void); /* the user callback device connected function */ - void (*device_reset) (void); /* the user callback device reset function */ - void (*device_disconnected) (void); /* the user callback device disconnected function */ - void (*over_current_detected) (void); /* the user callback over current detected function */ - void (*device_speed_detected) (uint8_t device_speed); /* the user callback device speed detected function */ - void (*device_desc_available) (void *devDesc); /* the user callback device descrpiter available function */ - void (*device_address_set) (void); /* the user callback set device address function */ - - void (*configuration_desc_available)(usb_descriptor_configuration_struct *cfg_desc, - usb_descriptor_interface_struct *itf_desc, - usb_descriptor_endpoint_struct *ep_desc); - /* the configuration descripter available function */ - - void (*manufacturer_string) (void *mfc_string); /* the user callback manufacturer string function */ - void (*product_string) (void *prod_string); /* the user callback product string function */ - void (*serial_num_string) (void *serial_string); /* the user callback serial number string function */ - void (*enumeration_finish) (void); /* the user callback enumeration finish function */ - usbh_user_status_enum (*user_input) (void); /* the user callback user input function */ - int (*user_application) (usb_core_handle_struct *pudev, uint8_t id); - /* the user callback user appliction function */ - void (*device_not_supported) (void); /* the user callback device not supported function */ - void (*unrecovered_error) (void); /* the user callback unrecovered error function */ -}usbh_user_callback_struct; - -/* the backup state struct */ -typedef struct -{ - host_state_enum host_backup_state; /* the host backup state */ - enum_state_enum enum_backup_state; /* the enum backup state */ - ctrl_state_enum ctrl_backup_state; /* the ctrl backup state */ - uint8_t class_req_backup_state;/* the class request backup state */ - uint8_t class_backup_state; /* the class backup state */ -} backup_state_struct; - -/* host information */ -typedef struct -{ - backup_state_struct usbh_backup_state; /* the usbh backup state variable */ - usbh_ctrl_struct control; /* the control struct variable */ - usbh_device_struct device; /* the device struct variable */ - usbh_user_callback_struct *usr_cb; /* the user callback function */ - usbh_status_enum (*class_init) (usb_core_handle_struct *pudev, void *phost); /* the class init function */ - void (*class_deinit) (usb_core_handle_struct *pudev, void *phost); /* the class deinit function */ -}usbh_host_struct; - -/* the action function definition */ -typedef usbh_status_enum (*ACT_FUN) (usb_core_handle_struct *pudev, usbh_host_struct *puhost, void* pustate); - -/* the state table struct */ -typedef struct -{ - uint8_t cur_state; /* the current state */ - uint8_t cur_event; /* the current event */ - uint8_t next_state; /* the next state */ - ACT_FUN event_action_fun; /* the event action function entry */ -} state_table_struct; - -/* the state stack struct */ -typedef struct -{ - uint8_t state; /* the state in state stack */ - state_table_struct* table; /* the table in state stack */ - uint8_t table_size; /* the table size in state stack */ -} usbh_state_stack_struct; - -/* the state regist table struct */ -typedef struct -{ - uint8_t id; /* the id of the state table */ - state_table_struct* table; /* the table entry to regist */ - uint8_t table_size; /* the table size to regist */ -} usbh_state_regist_table_struct; - -/* the state handle struct */ -typedef struct -{ - uint8_t usbh_current_state; /* current state */ - uint8_t usbh_current_state_table_size; /* current state table size */ - state_table_struct* usbh_current_state_table; /* current state table */ - - usbh_state_stack_struct stack[MAX_USBH_STATE_STACK_DEEP]; /* the stack of state table */ - int8_t usbh_current_state_stack_top; /* the current state top */ - - usbh_state_regist_table_struct usbh_regist_state_table[MAX_USBH_STATE_TABLE_NUM]; /* the array of regist state table */ - uint8_t usbh_regist_state_table_num; /* the number of regist state table */ -} usbh_state_handle_struct; - -/* function declarations */ -/* the host core driver function */ -usbh_status_enum host_state_polling_fun (usb_core_handle_struct *pudev, usbh_host_struct *puhost, void *pustate); -/* initialize the host portion of the driver */ -uint32_t hcd_init (usb_core_handle_struct *pudev, usb_core_id_enum core_id); -/* check if the device is connected */ -uint32_t hcd_is_device_connected (usb_core_handle_struct *pudev); -/* this function returns the last URBstate */ -urb_state_enum hcd_urb_state_get (usb_core_handle_struct *pudev, uint8_t channel_num); -/* this function returns the last URBstate */ -uint32_t hcd_xfer_count_get (usb_core_handle_struct *pudev, uint8_t channel_num); -/* de-initialize host */ -usbh_status_enum usbh_deinit (usb_core_handle_struct *pudev, - usbh_host_struct *puhost, - usbh_state_handle_struct* pustate); - -/* the state core driver function */ -/* state core driver init */ -void scd_init (usbh_state_handle_struct* pustate); -/* state core driver table regist */ -void scd_table_regist (usbh_state_handle_struct* pustate, - state_table_struct* pstate_table, - uint8_t table_id, - uint8_t current_table_size); -/* state core driver begin */ -void scd_begin (usbh_state_handle_struct* pustate, uint8_t table_id); -/* state core driver move state */ -void scd_state_move (usbh_state_handle_struct* pustate, uint8_t state); -/* state core driver event handle */ -usbh_status_enum scd_event_handle (usb_core_handle_struct *pudev, - usbh_host_struct *puhost, - usbh_state_handle_struct* pustate, - uint8_t event, - uint8_t state); -/* state core driver table push */ -void scd_table_push (usbh_state_handle_struct* pustate); -/* state core driver table pop */ -void scd_table_pop (usbh_state_handle_struct* pustate); -/* the function is only used to state move */ -usbh_status_enum only_state_move (usb_core_handle_struct *pudev, usbh_host_struct *puhost, void *pustate); -/* the function to the up state */ -usbh_status_enum goto_up_state_fun (usb_core_handle_struct *pudev, usbh_host_struct *puhost, void *pustate); - -#endif /* USBH_CORE_H */ diff --git a/bsp/gd32450z-eval/Libraries/GD32F4xx_usb_driver/Include/usbh_ctrl.h b/bsp/gd32450z-eval/Libraries/GD32F4xx_usb_driver/Include/usbh_ctrl.h deleted file mode 100644 index 4b30c64d1a..0000000000 --- a/bsp/gd32450z-eval/Libraries/GD32F4xx_usb_driver/Include/usbh_ctrl.h +++ /dev/null @@ -1,45 +0,0 @@ -/*! - \file usbh_ctrl.h - \brief header file for usbh_ctrl.c -*/ - -/* - Copyright (C) 2016 GigaDevice - - 2016-08-15, V1.0.0, firmware for GD32F4xx -*/ - -#ifndef USBH_CTRL_H -#define USBH_CTRL_H - -#include "usbh_core.h" -#include "usbh_usr.h" - -#define CTRL_HANDLE_TABLE_SIZE 13U /*!< the ctrl handle table size define */ - -extern state_table_struct ctrl_handle_table[CTRL_HANDLE_TABLE_SIZE]; -extern uint8_t ctrl_polling_handle_flag; - -/* the enum of CTRL event */ -typedef enum -{ - CTRL_EVENT_IDLE = 0, /* the ctrl idle event */ - CTRL_EVENT_SETUP, /* the ctrl setup event */ - CTRL_EVENT_DATA, /* the ctrl data event */ - CTRL_EVENT_STATUS, /* the ctrl status event */ - CTRL_EVENT_COMPLETE, /* the ctrl complete event */ - CTRL_EVENT_ERROR, /* the ctrl error event */ - CTRL_EVENT_STALLED, /* the ctrl stalled event */ -}ctrl_event_enum; - -/* function declarations */ -/* the polling function of control transfer state handle */ -usbh_status_enum ctrl_state_polling_fun (usb_core_handle_struct *pudev, usbh_host_struct *puhost, void *pustate); -/* send datas from the host channel */ -usbh_status_enum usbh_xfer (usb_core_handle_struct *pudev, uint8_t *buf, uint8_t hc_num, uint16_t len); -/* send the setup packet to the device */ -usbh_status_enum usbh_ctltx_setup (usb_core_handle_struct *pudev, uint8_t *buf, uint8_t hc_num); -/* this function prepare a hc and start a transfer */ -uint32_t hcd_submit_request (usb_core_handle_struct *pudev, uint8_t channel_num); - -#endif /* USBH_CTRL_H */ diff --git a/bsp/gd32450z-eval/Libraries/GD32F4xx_usb_driver/Include/usbh_hcs.h b/bsp/gd32450z-eval/Libraries/GD32F4xx_usb_driver/Include/usbh_hcs.h deleted file mode 100644 index 34bdff55b7..0000000000 --- a/bsp/gd32450z-eval/Libraries/GD32F4xx_usb_driver/Include/usbh_hcs.h +++ /dev/null @@ -1,46 +0,0 @@ -/*! - \file usbh_hcs.h - \brief header file for usbh_hcs.c -*/ - -/* - Copyright (C) 2016 GigaDevice - - 2016-08-15, V1.0.0, firmware for GD32F4xx -*/ - -#ifndef USBH_HCS_H -#define USBH_HCS_H - -#include "usbh_core.h" - -#define HC_MAX 8U - -#define HC_OK 0x0000U -#define HC_USED 0x8000U -#define HC_ERROR 0xFFFFU -#define HC_USED_MASK 0x7FFFU - -/* function declarations */ -/* allocate a new channel for the pipe */ -uint8_t usbh_channel_alloc (usb_core_handle_struct *pudev, uint8_t ep_addr); -/* free all usb host channel */ -uint8_t usbh_allchannel_dealloc (usb_core_handle_struct *pudev); -/* free the usb host channel */ -uint8_t usbh_channel_free (usb_core_handle_struct *pudev, uint8_t index); -/* open a channel */ -uint8_t usbh_channel_open (usb_core_handle_struct *pudev, - uint8_t channel_num, - uint8_t dev_addr, - uint8_t dev_speed, - uint8_t ep_type, - uint16_t ep_mps); -/* modify a channel */ -uint8_t usbh_channel_modify (usb_core_handle_struct *pudev, - uint8_t channel_num, - uint8_t dev_addr, - uint8_t dev_speed, - uint8_t ep_type, - uint16_t ep_mps); - -#endif /* USBH_HCS_H */ diff --git a/bsp/gd32450z-eval/Libraries/GD32F4xx_usb_driver/Include/usbh_int.h b/bsp/gd32450z-eval/Libraries/GD32F4xx_usb_driver/Include/usbh_int.h deleted file mode 100644 index 9fac257295..0000000000 --- a/bsp/gd32450z-eval/Libraries/GD32F4xx_usb_driver/Include/usbh_int.h +++ /dev/null @@ -1,30 +0,0 @@ -/*! - \file usbh_int.h - \brief USB host mode interrupt handler header file -*/ - -/* - Copyright (C) 2016 GigaDevice - - 2016-08-15, V1.0.1, firmware for GD32F4xx -*/ - -#ifndef USBH_INT_H -#define USBH_INT_H - -#include "usb_core.h" - -typedef struct -{ - uint8_t (*sof) (usb_core_handle_struct *pudev); - uint8_t (*device_connected) (usb_core_handle_struct *pudev); - uint8_t (*device_disconnected) (usb_core_handle_struct *pudev); -}usbh_hcd_int_cb_struct; - -extern usbh_hcd_int_cb_struct *usbh_hcd_int_fops; - -/* function declarations */ -/* handle global host interrupt */ -uint32_t usbh_isr (usb_core_handle_struct *pudev); - -#endif /* USBH_INT_H */ diff --git a/bsp/gd32450z-eval/Libraries/GD32F4xx_usb_driver/Include/usbh_std.h b/bsp/gd32450z-eval/Libraries/GD32F4xx_usb_driver/Include/usbh_std.h deleted file mode 100644 index 2dbc45ee30..0000000000 --- a/bsp/gd32450z-eval/Libraries/GD32F4xx_usb_driver/Include/usbh_std.h +++ /dev/null @@ -1,74 +0,0 @@ -/*! - \file usbh_std.h - \brief header file for usbh_std.c -*/ - -/* - Copyright (C) 2016 GigaDevice - - 2016-08-15, V1.0.0, firmware for GD32F4xx -*/ - -#ifndef USBH_STD_H -#define USBH_STD_H - -#include "usbh_core.h" -#include "usbh_usr.h" - -/* standard feature selector for clear feature command */ -#define FEATURE_SELECTOR_ENDPOINT 0x00U -#define FEATURE_SELECTOR_DEVICE 0x01U - -#define USBH_SETUP_PACKET_SIZE 8U /* setup packet size */ -#define ENUM_HANDLE_TABLE_SIZE 10U /* enumerate handle table size */ - -extern uint8_t usbh_cfg_desc[512]; -extern uint8_t enum_polling_handle_flag; -extern state_table_struct enum_handle_table[ENUM_HANDLE_TABLE_SIZE]; - -typedef enum -{ - ENUN_EVENT_IDLE = 0, /* the enum idle event */ - ENUM_EVENT_SET_ADDR, /* the enum set address event */ - ENUN_EVENT_GET_FULL_DEV_DESC, /* the enum get full device descripter event */ - ENUN_EVENT_GET_CFG_DESC, /* the enum get congiguration descripter event */ - ENUN_EVENT_GET_FULL_CFG_DESC, /* the enum get full configuration descripter event */ - ENUN_EVENT_GET_MFC_STRING_DESC, /* the enum get MFC string descripter event */ - ENUN_EVENT_GET_PRODUCT_STRING_DESC, /* the enum get product string event */ - ENUN_EVENT_GET_SERIALNUM_STRING_DESC, /* the enum get serialnum string event */ - ENUN_EVENT_SET_CONFIGURATION, /* the enum set configuration event */ - ENUN_EVENT_DEV_CONFIGURED /* the enum device configured event */ -}enum_event_enum; - -/* function declarations */ -/* the polling function of enumeration state */ -usbh_status_enum enum_state_polling_fun (usb_core_handle_struct *pudev, usbh_host_struct *puhost, void *pustate); -/* get descriptor in usb host enumeration stage */ -void usbh_enum_desc_get (usb_core_handle_struct *pudev, - usbh_host_struct *puhost, - uint8_t *buf, - uint8_t req_type, - uint16_t value_idx, - uint16_t len); -/* set address in usb host enumeration stage */ -void usbh_enum_addr_set (usb_core_handle_struct *pudev, usbh_host_struct *puhost, uint8_t device_address); -/* set configuration in usb host enumeration stage */ -void usbh_enum_cfg_set (usb_core_handle_struct *pudev, usbh_host_struct *puhost, uint16_t cfg_idx); -/* parse the device descriptor */ -void usbh_device_desc_parse (usb_descriptor_device_struct *dev_desc, uint8_t *buf, uint16_t len); -/* parse the configuration descriptor */ -void usbh_cfg_desc_parse (usb_descriptor_configuration_struct *cfg_desc, - usb_descriptor_interface_struct *itf_desc, - usb_descriptor_endpoint_struct ep_desc[][USBH_MAX_EP_NUM], - uint8_t *buf, - uint16_t len); -/* parse the interface descriptor */ -void usbh_interface_desc_parse (usb_descriptor_interface_struct *itf_desc, uint8_t *buf); -/* parse the endpoint descriptor */ -void usbh_endpoint_desc_parse (usb_descriptor_endpoint_struct *ep_desc, uint8_t *buf); -/* parse the string descriptor */ -void usbh_string_desc_parse (uint8_t *psrc, uint8_t *pdest, uint16_t len); -/* get the next descriptor header */ -usb_descriptor_header_struct *usbh_next_desc_get (uint8_t *pbuf, uint16_t *ptr); - -#endif /* USBH_STD_H */ diff --git a/bsp/gd32450z-eval/Libraries/GD32F4xx_usb_driver/Source/usb_core.c b/bsp/gd32450z-eval/Libraries/GD32F4xx_usb_driver/Source/usb_core.c deleted file mode 100644 index 18834acd9e..0000000000 --- a/bsp/gd32450z-eval/Libraries/GD32F4xx_usb_driver/Source/usb_core.c +++ /dev/null @@ -1,1132 +0,0 @@ -/*! - \file usb_core.c - \brief USB core driver which can operate in host-mode and device-mode -*/ - -/* - Copyright (C) 2016 GigaDevice - - 2016-08-15, V1.0.0, firmware for GD32F4xx -*/ - -#include "usb_core.h" - -static void usb_commonint_enable (usb_core_handle_struct *pudev); -static usb_status_enum usb_core_reset (usb_core_handle_struct *pudev); - -/*! - \brief enable the commmon interrupts which are used in both device and host modes - \param[in] pudev: pointer to selected usb device - \param[out] none - \retval none -*/ -static void usb_commonint_enable (usb_core_handle_struct *pudev) -{ -#ifndef USE_OTG_MODE - - /* clear any pending USB interrupts */ - USB_GOTGINTF = 0xFFFFFFFFU; - -#endif /* USE_OTG_MODE */ - - /* enable the usb wakeup and suspend interrupts */ - USB_GINTEN = GINTEN_WKUPIE | GINTEN_SPIE; - -#ifdef USE_OTG_MODE - - /* enable the OTG interrupts, session interrrupts and connector ID pin interrupt */ - USB_GINTEN |= GINTEN_OTGIE | GINTEN_SESIE | GINTEN_CIDPSCIE; - -#endif /* USE_OTG_MODE */ -} - -/*! - \brief soft reset of the OTG_FS core - \param[in] pudev: pointer to usb device - \param[out] none - \retval operation status -*/ -static usb_status_enum usb_core_reset (usb_core_handle_struct *pudev) -{ - uint32_t count = 0U; - - /* enable core soft reset */ - USB_GRSTCTL |= GRSTCTL_CSRST; - - /* wait for the core to be soft reset */ - do { - if (++count > 200000U) { - break; - } - } while (1U == (USB_GRSTCTL & GRSTCTL_CSRST)); - - /* wait for addtional 3 PHY clocks */ - if (NULL != pudev->udelay) { - pudev->udelay(3U); - } - - return USB_OK; -} - -/*! - \brief write a packet into the Tx FIFO associated with the endpoint - \param[in] src: pointer to source buffer - \param[in] ep_id: endpoint identifier which is in (0..3) - \param[in] len: packet length - \param[out] none - \retval operation status -*/ -usb_status_enum usb_fifo_write (uint8_t *src, uint8_t ep_id, uint16_t len) -{ - uint32_t count32b = 0U, i = 0U; - __IO uint32_t *fifo = USB_FIFO(ep_id); - - count32b = (len + 3U) / 4U; - - for (i = 0U; i < count32b; i++) { - *fifo = *((__packed uint32_t *)src); - - src += 4U; - } - - return USB_OK; -} - -/*! - \brief read a packet from the Rx FIFO associated with the endpoint - \param[in] dest: pointer to destination buffer - \param[in] len: packet length - \param[out] none - \retval void type pointer -*/ -void *usb_fifo_read (uint8_t *dest, uint16_t len) -{ - uint32_t i = 0U; - uint32_t count32b = (len + 3U) / 4U; - - __IO uint32_t *fifo = USB_FIFO(0U); - - for (i = 0U; i < count32b; i++) { - *(__packed uint32_t *)dest = *fifo; - - dest += 4U; - } - - return ((void *)dest); -} - -/*! - \brief initialize core parameters - \param[in] pudev: pointer to usb device - \param[in] core_id: USB core id - \param[out] none - \retval operation status -*/ -usb_status_enum usb_core_select (usb_core_handle_struct *pudev, usb_core_id_enum core_id) -{ - /* at startup the core is in FS mode */ - pudev->cfg.core_speed = USB_CORE_SPEED_FULL; - pudev->cfg.max_packet_size = USBFS_MAX_PACKET_SIZE; - - pudev->cfg.dma_enable = 0U; - - /* initialize the core parameters */ - if (USB_FS_CORE_ID == core_id) { - pudev->cfg.core_id = USB_FS_CORE_ID; - - /* set the host channel numbers */ - pudev->cfg.host_channel_num = USBFS_MAX_HOST_CHANNELCOUNT; - - /* set the device endpoint numbers */ - pudev->cfg.dev_endp_num = USBFS_MAX_DEV_EPCOUNT; - - /* fifo size is in terms of DWORD */ - pudev->cfg.max_fifo_size = USBFS_MAX_FIFO_WORDLEN; - - /* OTG_FS core use embedded physical layer */ - pudev->cfg.phy_interface = USB_CORE_EMBEDDED_PHY; - -#ifdef USBFS_SOF_OUTPUT_ENABLED - pudev->cfg.sof_output = 1U; -#endif /* USBFS_SOF_OUTPUT_ENABLED */ - -#ifdef USBFS_LOW_PWR_MGMT_SUPPORT - pudev->cfg.low_power = 1U; -#endif /* USBFS_LOW_PWR_MGMT_SUPPORT */ - - } else if (USB_HS_CORE_ID == core_id) { - pudev->cfg.core_id = USB_HS_CORE_ID; - - /* set the host channel numbers */ - pudev->cfg.host_channel_num = USBHS_MAX_HOST_CHANNELCOUNT; - - /* set the device endpoint numbers */ - pudev->cfg.dev_endp_num = USBHS_MAX_DEV_EPCOUNT; - - /* fifo size is in terms of DWORD */ - pudev->cfg.max_fifo_size = USBHS_MAX_FIFO_WORDLEN; - -#ifdef USB_ULPI_PHY_ENABLED - pudev->cfg.phy_interface = USB_CORE_ULPI_PHY; -#elif defined(USB_EMBEDDED_PHY_ENABLED) - pudev->cfg.phy_interface = USB_CORE_EMBEDDED_PHY; -#endif /* USB_ULPI_PHY_ENABLED */ - -#ifdef USBHS_INTERNAL_DMA_ENABLED - pudev->cfg.dma_enable = 1U; -#endif /* USBHS_INTERNAL_DMA_ENABLED */ - -#ifdef USBHS_SOF_OUTPUT_ENABLED - pudev->cfg.sof_output = 1U; -#endif /* USBHS_SOF_OUTPUT_ENABLED */ - -#ifdef USBHS_LOW_PWR_MGMT_SUPPORT - pudev->cfg.low_power = 1U; -#endif /* USBHS_LOW_PWR_MGMT_SUPPORT */ - } else { - /* no operation */ - } - - return USB_OK; -} - -/*! - \brief initializes the USB controller registers and - prepares the core device mode or host mode operation - \param[in] pudev: pointer to usb device - \param[out] none - \retval operation status -*/ -usb_status_enum usb_core_init (usb_core_handle_struct *pudev) -{ - if (USB_CORE_ULPI_PHY == pudev->cfg.phy_interface) { - USB_GCCFG &= ~GCCFG_PWRON; - - if (pudev->cfg.sof_output) { - USB_GCCFG |= GCCFG_SOFOEN; - } - - /* use high-speed interface */ - USB_GUSBCS &= ~GUSBCS_EMBPHY; - - /* use internal over-current indicator */ - USB_GUSBCS &= ~GUSBCS_ULPIEOI; - -#ifdef USBHS_EXTERNAL_VBUS_ENABLED - /* use external VBUS driver */ - USB_GUSBCS |= GUSBCS_ULPIEVD; -#else - /* use internal VBUS driver */ - USB_GUSBCS &= ~GUSBCS_ULPIEVD; -#endif - - /* soft reset the core */ - usb_core_reset(pudev); - } else if (USB_CORE_EMBEDDED_PHY == pudev->cfg.phy_interface) { - if (USB_HS_CORE_ID == pudev->cfg.core_id) { - USB_GUSBCS |= GUSBCS_EMBPHY; - } - - /* soft reset the core */ - usb_core_reset(pudev); - - /* active the transceiver and enable vbus sensing */ - USB_GCCFG |= GCCFG_PWRON | GCCFG_VBUSACEN | GCCFG_VBUSBCEN; - - /* set Tx FIFO empty level to half empty mode */ - USB_GAHBCS &= ~GAHBCS_TXFTH | TXFIFO_EMPTY_HALF; - -#ifndef VBUS_SENSING_ENABLED - USB_GCCFG |= GCCFG_VBUSIG; -#endif /* VBUS_SENSING_ENABLED */ - - if(pudev->cfg.sof_output){ - USB_GCCFG |= GCCFG_SOFOEN; - } - - if (NULL != pudev->mdelay) { - pudev->mdelay(20U); - } - } else { - /* no operation */ - } - - if (1U == pudev->cfg.dma_enable) { - USB_GAHBCS = DMA_INCR8 | GAHBCS_DMAEN; - } - -#ifdef USE_OTG_MODE - /* enable OTG features */ - USB_GUSBCS |= GUSBCS_HNPCAP | GUSBCS_SRPCAP; - USB_OTG_EnableCommonInt(pudev); - -#endif /* USE_OTG_MODE */ - - return USB_OK; -} - -/*! - \brief flush a Tx FIFO or all Tx FIFOs - \param[in] pudev: pointer to usb device - \param[in] fifo_num: FIFO number which is in (0..3) - \param[out] none - \retval operation status -*/ -usb_status_enum usb_txfifo_flush (usb_core_handle_struct *pudev, uint8_t fifo_num) -{ - uint32_t count = 0U; - - USB_GRSTCTL = ((uint32_t)fifo_num << 6U) | GRSTCTL_TXFF; - - /* wait for Tx FIFO flush bit is set */ - do { - if (++count > 200000U) { - break; - } - } while (USB_GRSTCTL & GRSTCTL_TXFF); - - /* wait for 3 PHY clocks */ - if (NULL != pudev->udelay) { - pudev->udelay(3U); - } - - return USB_OK; -} - -/*! - \brief flush the entire Rx FIFO - \param[in] pudev: pointer to usb device - \param[out] none - \retval operation status -*/ -usb_status_enum usb_rxfifo_flush (usb_core_handle_struct *pudev) -{ - uint32_t count = 0U; - - USB_GRSTCTL = GRSTCTL_RXFF; - - /* wait for Rx FIFO flush bit is set */ - do { - if (++count > 200000U) { - break; - } - } while (USB_GRSTCTL & GRSTCTL_RXFF); - - /* wait for 3 PHY clocks */ - if (NULL != pudev->udelay) { - pudev->udelay(3U); - } - - return USB_OK; -} - -/*! - \brief set operation mode (host or device) - \param[in] pudev: pointer to usb device - \param[in] mode: operation mode which need to set - \arg HOST_MODE - \arg DEVICE_MODE - \param[out] none - \retval operation status -*/ -usb_status_enum usb_mode_set (usb_core_handle_struct *pudev, uint8_t mode) -{ - if (HOST_MODE == mode) { - USB_GUSBCS &= ~GUSBCS_FDM; - USB_GUSBCS |= GUSBCS_FHM; - } else if (DEVICE_MODE == mode) { - USB_GUSBCS &= ~GUSBCS_FHM; - USB_GUSBCS |= GUSBCS_FDM; - } else { - /* no operation */ - } - - if (NULL != pudev->mdelay) { - pudev->mdelay(50U); - } - - return USB_OK; -} - -#ifdef USE_HOST_MODE - -/*! - \brief initializes USB core for host mode - \param[in] pudev: pointer to selected usb host - \param[out] none - \retval operation status -*/ -usb_status_enum usb_hostcore_init (usb_core_handle_struct *pudev) -{ - uint32_t i = 0U; - __IO uint32_t host_nptxfifo_size = 0U; - __IO uint32_t host_ptxfifo_size = 0U; - -#ifdef USE_OTG_MODE - __IO uint32_t OtgCtrl = 0; -#endif /* USE_OTG_MODE */ - - /* restart the PHY clock */ - USB_PWRCLKCTL = 0U; - - /* initialize host configuration register */ - if (USB_CORE_ULPI_PHY == pudev->cfg.phy_interface) { - USB_FSLSCLOCK_INIT(HCTLR_30_60_MHZ); - } else { - USB_FSLSCLOCK_INIT(HCTLR_48_MHZ); - } - - /* configure data FIFO sizes */ -#ifdef USBFS_CORE - if (USB_FS_CORE_ID == pudev->cfg.core_id) { - /* set Rx FIFO size */ - USB_GRFLEN = USBFS_RX_FIFO_SIZE; - - /* set non-periodic Tx FIFO size and address */ - host_nptxfifo_size &= ~HNPTFLEN_HNPTXRSAR; - host_nptxfifo_size |= USBFS_RX_FIFO_SIZE; - host_nptxfifo_size &= ~HNPTFLEN_HNPTXFD; - host_nptxfifo_size |= USBFS_HTX_NPFIFO_SIZE << 16; - USB_HNPTFLEN = host_nptxfifo_size; - - /* set periodic Tx FIFO size and address */ - host_ptxfifo_size &= ~HPTFLEN_HPTXFSAR; - host_ptxfifo_size |= USBFS_RX_FIFO_SIZE + USBFS_HTX_PFIFO_SIZE; - host_ptxfifo_size &= ~HPTFLEN_HPTXFD; - host_ptxfifo_size |= USBFS_HTX_PFIFO_SIZE << 16; - USB_HPTFLEN = host_ptxfifo_size; - } -#endif /* USBFS_CORE */ - -#ifdef USBHS_CORE - if (USB_HS_CORE_ID == pudev->cfg.core_id) { - /* set Rx FIFO size */ - USB_GRFLEN = USBHS_RX_FIFO_SIZE; - - /* set non-periodic Tx FIFO size and address */ - host_nptxfifo_size &= ~HNPTFLEN_HNPTXRSAR; - host_nptxfifo_size |= USBHS_RX_FIFO_SIZE; - host_nptxfifo_size &= ~HNPTFLEN_HNPTXFD; - host_nptxfifo_size |= USBHS_HTX_NPFIFO_SIZE << 16; - USB_HNPTFLEN = host_nptxfifo_size; - - /* set periodic Tx FIFO size and address */ - host_ptxfifo_size &= ~HPTFLEN_HPTXFSAR; - host_ptxfifo_size |= USBHS_RX_FIFO_SIZE + USBHS_HTX_PFIFO_SIZE; - host_ptxfifo_size &= ~HPTFLEN_HPTXFD; - host_ptxfifo_size |= USBHS_HTX_PFIFO_SIZE << 16; - USB_HPTFLEN = host_ptxfifo_size; - } -#endif /* USBHS_CORE */ - -#ifdef USE_OTG_MODE - - /* clear Host Set HNP Enable bit in the USB OTG Control Register */ - OtgCtrl |= GOTGCS_HHNPEN; - USB_GOTGCS &= ~OtgCtrl; - USB_GOTGCS |= 0; - -#endif /* USE_OTG_MODE */ - - /* make sure the FIFOs are flushed */ - - /* flush all Tx FIFOs in device or host mode */ - usb_txfifo_flush(pudev, 0x10U); - - /* flush the entire Rx FIFO */ - usb_rxfifo_flush(pudev); - - /* clear all pending host channel interrupts */ - USB_HACHINTEN &= ~HACHINTEN_CINTEN; - - for (i = 0U; i < pudev->cfg.host_channel_num; i++) { - USB_HCHxINTEN(i) = 0U; - USB_HCHxINTF(i) = 0xFFFFFFFFU; - } - -#ifndef USE_OTG_MODE - usb_vbus_drive(pudev, 1U); -#endif /* USE_OTG_MODE */ - - usb_hostint_enable(pudev); - - return USB_OK; -} - -/*! - \brief control the VBUS to power - \param[in] pudev: pointer to selected usb host - \param[in] state: VBUS state - \param[out] none - \retval none -*/ -void usb_vbus_drive (usb_core_handle_struct *pudev, uint8_t state) -{ - __IO uint32_t host_port = 0U; - - /* enable or disable the external charge pump */ - if ((void *)0 != pudev->host.vbus_drive) { - pudev->host.vbus_drive(pudev, state); - } - - /* turn on the host port power. */ - host_port = USB_PORT_READ(); - - if ((0U == (host_port & HPCS_PP)) && (1U == state)) { - host_port |= HPCS_PP; - } else if ((1U == (host_port & HPCS_PP)) && (0U == state)) { - host_port &= ~HPCS_PP; - } else { - /* no operation */ - } - - USB_HPCS = host_port; - - if (NULL != pudev->mdelay) { - pudev->mdelay(200U); - } -} - -/*! - \brief enables the host mode interrupts - \param[in] pudev: pointer to selected usb host - \param[out] none - \retval operation status -*/ -usb_status_enum usb_hostint_enable (usb_core_handle_struct *pudev) -{ - uint32_t global_int_flag = 0U; - - /* disable all interrupts */ - USB_GINTEN = 0U; - - /* clear any pending interrupts */ - USB_GINTF = 0xFFFFFFFFU; - - /* enable the common interrupts */ - usb_commonint_enable(pudev); - - if (0U == pudev->cfg.dma_enable) { - global_int_flag |= GINTF_RXFNEIF; - } - - /* enable host_mode-related interrupts */ - global_int_flag |= GINTF_HPIF | GINTF_HCIF | GINTF_DISCIF \ - | GINTF_SOF | GINTF_ISOONCIF; - - USB_GINTEN &= ~global_int_flag; - USB_GINTEN |= global_int_flag; - - return USB_OK; -} - -/*! - \brief reset host port - \param[in] pudev: pointer to usb device - \param[out] none - \retval operation status -*/ -uint32_t usb_port_reset (usb_core_handle_struct *pudev) -{ - USB_HPCS = USB_PORT_READ() | HPCS_PRST; - - if (NULL != pudev->mdelay) { - pudev->mdelay(10U); - } - - USB_HPCS &= ~HPCS_PRST; - - if (NULL != pudev->mdelay) { - pudev->mdelay(20U); - } - - return USB_OK; -} - -/*! - \brief initialize host channel - \param[in] pudev: pointer to usb device - \param[in] hc_num: host channel number which is in (0..7) - \param[out] none - \retval operation status -*/ -usb_status_enum usb_hostchannel_init(usb_core_handle_struct *pudev, uint8_t hc_num) -{ - usb_status_enum status = USB_OK; - uint8_t is_low_speed = 0U; - __IO uint32_t host_channel_inten = 0U; - __IO uint32_t host_channel_ctlr = 0U; - - usb_hostchannel_struct *puhc = &pudev->host.host_channel[hc_num]; - - /* clear old interrupt conditions for this host channel */ - USB_HCHxINTF((uint16_t)hc_num) = 0xFFFFFFFFU; - - if (1U == pudev->cfg.dma_enable) { - host_channel_inten |= HCHINTEN_DMAERIE; - } - - /* enable channel interrupts required for this transfer */ - switch (puhc->endp_type) { - case USB_EPTYPE_CTRL: - case USB_EPTYPE_BULK: - host_channel_inten |= HCHINTEN_TFIE | HCHINTEN_STALLIE | HCHINTEN_USBERIE \ - | HCHINTEN_DTERIE | HCHINTEN_NAKIE; - - if (puhc->endp_in) { - host_channel_inten |= HCHINTEN_BBERIE; - } else { - host_channel_inten |= HCHINTEN_NYETIE; - - if (puhc->do_ping) { - host_channel_inten |= HCHINTEN_ACKIE; - } - } - break; - - case USB_EPTYPE_INTR: - host_channel_inten |= HCHINTEN_TFIE | HCHINTEN_STALLIE | HCHINTEN_USBERIE | HCHINTEN_DTERIE \ - | HCHINTEN_NAKIE | HCHINTEN_REQOVRIE; - - if (puhc->endp_in) { - host_channel_inten |= HCHINTEN_BBERIE; - } - break; - - case USB_EPTYPE_ISOC: - host_channel_inten |= HCHINTEN_TFIE | HCHINTEN_REQOVRIE | HCHINTEN_ACKIE; - - if (puhc->endp_in) { - host_channel_inten |= HCHINTEN_USBERIE | HCHINTEN_BBERIE; - } - break; - - default: - break; - } - - USB_HCHxINTEN((uint16_t)hc_num) = host_channel_inten; - - /* enable the top level host channel interrupt */ - USB_HACHINTEN |= 1U << hc_num; - - /* make sure host channel interrupts are enabled */ - USB_GINTEN |= GINTEN_HCIE; - - /* program the hcctlr register */ - host_channel_ctlr = 0U; - - if (HPRT_PRTSPD_LOW_SPEED == puhc->dev_speed) { - is_low_speed = 1U; - } - - host_channel_ctlr |= (uint32_t)puhc->dev_addr << 22U; - host_channel_ctlr |= (uint32_t)puhc->endp_type << 18U; - host_channel_ctlr |= (uint32_t)puhc->endp_id << 11U; - host_channel_ctlr |= (uint32_t)puhc->endp_in << 15U; - host_channel_ctlr |= (uint32_t)is_low_speed << 17U; - host_channel_ctlr |= puhc->endp_mps; - - if (HCCHAR_INTR == puhc->endp_type) { - host_channel_ctlr |= HCHCTL_ODDFRM; - } - - USB_HCHxCTL((uint16_t)hc_num) = host_channel_ctlr; - - return status; -} - -/*! - \brief prepare host channel for transferring packets - \param[in] pudev: pointer to usb device - \param[in] hc_num: host channel number which is in (0..7) - \param[out] none - \retval operation status -*/ -usb_status_enum usb_hostchannel_startxfer(usb_core_handle_struct *pudev, uint8_t hc_num) -{ - usb_status_enum status = USB_OK; - - uint16_t dword_len = 0U; - uint16_t packet_num = 0U; - - __IO uint32_t host_channel_xlen = 0U; - __IO uint32_t host_channel_ctlr = 0U; - - usb_hostchannel_struct *puhc = &pudev->host.host_channel[hc_num]; - - /* compute the expected number of packets associated to the transfer */ - if (puhc->xfer_len > 0U) { - packet_num = ((uint16_t)puhc->xfer_len + puhc->endp_mps - 1U) / puhc->endp_mps; - - if (packet_num > HC_MAX_PACKET_COUNT) { - packet_num = HC_MAX_PACKET_COUNT; - puhc->xfer_len = (uint32_t)(packet_num) * (uint32_t)(puhc->endp_mps); - } - } else { - packet_num = 1U; - } - - if (puhc->endp_in) { - puhc->xfer_len = (uint32_t)(packet_num) * (uint32_t)(puhc->endp_mps); - } - - /* initialize the host channel length register */ - host_channel_xlen &= ~HCHLEN_TLEN; - host_channel_xlen |= puhc->xfer_len; - host_channel_xlen &= ~HCHLEN_PCNT; - host_channel_xlen |= (uint32_t)packet_num << 19U; - host_channel_xlen &= ~HCHLEN_DPID; - host_channel_xlen |= (uint32_t)(puhc->DPID) << 29U; - USB_HCHxLEN((uint16_t)hc_num) = (uint32_t)host_channel_xlen; - - if (1U == pudev->cfg.dma_enable) { - USB_HCHxDMAADDR((uint16_t)hc_num) = (uint32_t)puhc->xfer_buff; - } - - /* set host channel enable */ - host_channel_ctlr = USB_HCHxCTL((uint16_t)hc_num); - - if (1U == USB_EVEN_FRAME()) { - host_channel_ctlr |= HCHCTL_ODDFRM; - } else { - host_channel_ctlr &= ~HCHCTL_ODDFRM; - } - - host_channel_ctlr |= HCHCTL_CEN; - host_channel_ctlr &= ~HCHCTL_CDIS; - USB_HCHxCTL((uint16_t)hc_num) = host_channel_ctlr; - - if (0U == pudev->cfg.dma_enable) { - if ((0U == puhc->endp_in) && (puhc->xfer_len > 0U)) { - dword_len = (uint16_t)(puhc->xfer_len + 3U) / 4U; - - switch (puhc->endp_type) { - /* non-periodic transfer */ - case USB_EPTYPE_CTRL: - case USB_EPTYPE_BULK: - /* check if there is enough space in fifo space */ - if (dword_len > (USB_HNPTFQSTAT & HNPTFQSTAT_NPTXFS)) { - /* need to process data in non-periodic transfer fifo empty interrupt */ - USB_GINTEN |= GINTEN_NPTXFEIE; - } - break; - - /* periodic transfer */ - case USB_EPTYPE_INTR: - case USB_EPTYPE_ISOC: - /* check if there is enough space in FIFO space */ - if (dword_len > (USB_HPTFQSTAT & HPTFQSTAT_PTXFS)) { - /* need to process data in periodic transfer fifo empty interrupt */ - USB_GINTEN |= GINTEN_PTXFEIE; - } - break; - - default: - break; - } - - /* write packet into the Tx FIFO. */ - usb_fifo_write(puhc->xfer_buff, hc_num, (uint16_t)puhc->xfer_len); - } - } - - return status; -} - -/*! - \brief halt channel - \param[in] pudev: pointer to usb device - \param[in] hc_num: host channel number which is in (0..7) - \param[out] none - \retval operation status -*/ -usb_status_enum usb_hostchannel_halt(usb_core_handle_struct *pudev, uint8_t hc_num) -{ - uint8_t endp_type = 0U; - __IO uint32_t host_channel_ctrl = USB_HCHxCTL((uint16_t)hc_num); - - host_channel_ctrl |= HCHCTL_CEN | HCHCTL_CDIS; - - endp_type = (uint8_t)((host_channel_ctrl & HCHCTL_EPTYPE) >> 18U); - - /* check for space in the request queue to issue the halt. */ - if ((HCCHAR_CTRL == endp_type) || (HCCHAR_BULK == endp_type)) { - if (0U == (USB_HNPTFQSTAT & HNPTFQSTAT_NPTXFS)) { - host_channel_ctrl |= HCHCTL_CDIS; - } - } else { - if (0U == (USB_HPTFQSTAT & HPTFQSTAT_PTXFS)) { - host_channel_ctrl |= HCHCTL_CEN; - } - } - - USB_HCHxCTL((uint16_t)hc_num) = host_channel_ctrl; - - return USB_OK; -} - -/*! - \brief issue a ping token - \param[in] pudev: pointer to usb device - \param[in] hc_num: host channel number which is in (0..7) - \param[out] none - \retval operation status -*/ -usb_status_enum usb_hostchannel_ping(usb_core_handle_struct *pudev, uint8_t hc_num) -{ - uint32_t host_channel_ctrl = 0U; - - USB_HCHxLEN((uint16_t)hc_num) = HCHLEN_PING | (HCHLEN_PCNT & (1U << 19U)); - - host_channel_ctrl = USB_HCHxCTL((uint16_t)hc_num); - host_channel_ctrl |= HCHCTL_CEN; - host_channel_ctrl &= ~HCHCTL_CDIS; - - USB_HCHxCTL((uint16_t)hc_num) = host_channel_ctrl; - - return USB_OK; -} - -/*! - \brief stop the USB host and clean up fifos - \param[in] none - \param[out] none - \retval none -*/ -void usb_host_stop(usb_core_handle_struct *pudev) -{ - uint32_t i; - - /* disable all host channel interrupt */ - USB_HACHINTEN = 0U; - USB_HACHINT = 0xFFFFFFFFU; - - /* flush out any leftover queued requests */ - for (i = 0U; i < pudev->cfg.host_channel_num; i++) { - USB_HCHxCTL(i) |= HCHCTL_CEN | HCHCTL_CDIS | HCHCTL_EPDIR; - } - - /* flush the FIFO */ - usb_rxfifo_flush(pudev); - usb_txfifo_flush(pudev, 0x10U); -} - -#endif /* USE_HOST_MODE */ - - -#ifdef USE_DEVICE_MODE - -#ifdef USBFS_CORE - -/* USB endpoint Tx FIFO size */ -static uint16_t USBFS_TX_FIFO_SIZE[USBFS_MAX_DEV_EPCOUNT] = -{ - (uint16_t)TX0_FIFO_FS_SIZE, - (uint16_t)TX1_FIFO_FS_SIZE, - (uint16_t)TX2_FIFO_FS_SIZE, - (uint16_t)TX3_FIFO_FS_SIZE -}; - -#elif defined(USBHS_CORE) - -uint16_t USBHS_TX_FIFO_SIZE[USBHS_MAX_DEV_EPCOUNT] = -{ - (uint16_t)TX0_FIFO_HS_SIZE, - (uint16_t)TX1_FIFO_HS_SIZE, - (uint16_t)TX2_FIFO_HS_SIZE, - (uint16_t)TX3_FIFO_HS_SIZE, - (uint16_t)TX4_FIFO_HS_SIZE, - (uint16_t)TX5_FIFO_HS_SIZE -}; - -#endif /* USBFS_CORE */ - -static usb_status_enum usb_devint_enable(usb_core_handle_struct *pudev); - -/*! - \brief initialize USB core registers for device mode - \param[in] pudev: pointer to usb device - \param[out] none - \retval operation status -*/ -usb_status_enum usb_devcore_init (usb_core_handle_struct *pudev) -{ - uint32_t i, ram_address = 0U; - __IO uint32_t dev_in_ep0_inf = USB_DIEP0TFLEN; - __IO uint32_t dev_in_ep_inf = 0U; - - /* restart the Phy Clock (Maybe don't need to...) */ - USB_PWRCLKCTL = 0U; - - /* config periodic frmae interval to default */ - USB_DCFG &= ~DCFG_EOPFT; - USB_DCFG |= FRAME_INTERVAL_80; - -#ifdef USBFS_CORE - if (USB_FS_CORE_ID == pudev->cfg.core_id) { - /* set full speed PHY */ - USB_DCFG &= ~DCFG_DS; - USB_DCFG |= USB_SPEED_INP_FULL; - - /* set Rx FIFO size */ - USB_GRFLEN &= ~GRFLEN_RXFD; - USB_GRFLEN |= RX_FIFO_FS_SIZE; - - /* set endpoint 0 Tx FIFO length and RAM address */ - dev_in_ep0_inf &= ~DIEP0TFLEN_IEP0TXFD; - dev_in_ep0_inf |= TX0_FIFO_FS_SIZE << 16; - dev_in_ep0_inf &= ~DIEP0TFLEN_IEP0TXRSAR; - dev_in_ep0_inf |= RX_FIFO_FS_SIZE; - - USB_DIEP0TFLEN = dev_in_ep0_inf; - - ram_address = RX_FIFO_FS_SIZE; - - /* set endpoint 1 to 3's Tx FIFO length and RAM address */ - for (i = 1U; i < USBFS_MAX_DEV_EPCOUNT; i++) { - ram_address += USBFS_TX_FIFO_SIZE[i - 1U]; - - dev_in_ep_inf &= ~DIEPTFLEN_IEPTXFD; - dev_in_ep_inf |= (uint32_t)USBFS_TX_FIFO_SIZE[i] << 16U; - dev_in_ep_inf &= ~DIEPTFLEN_IEPTXRSAR; - dev_in_ep_inf |= ram_address; - - USB_DIEPxTFLEN(i) = dev_in_ep_inf; - } - } -#endif /* USBFS_CORE */ - -#ifdef USBHS_CORE - if (USB_HS_CORE_ID == pudev->cfg.core_id) { - USB_DCFG &= ~DCFG_DS; - - if (USB_CORE_EMBEDDED_PHY == pudev->cfg.phy_interface) { - /* set full speed PHY in USB high speed core */ - USB_DCFG |= USB_SPEED_INP_FULL; - } else if (USB_CORE_ULPI_PHY == pudev->cfg.phy_interface) { - USB_DCFG |= USB_SPEED_EXP_HIGH; - } - - /* set Rx FIFO size */ - USB_GRFLEN &= ~GRFLEN_RXFD; - USB_GRFLEN |= RX_FIFO_HS_SIZE; - - /* set endpoint 0 Tx FIFO length and RAM address */ - dev_in_ep0_inf &= ~DIEP0TFLEN_IEP0TXFD; - dev_in_ep0_inf |= TX0_FIFO_HS_SIZE << 16; - dev_in_ep0_inf &= ~DIEP0TFLEN_IEP0TXRSAR; - dev_in_ep0_inf |= RX_FIFO_HS_SIZE; - - USB_DIEP0TFLEN = dev_in_ep0_inf; - - ram_address = RX_FIFO_HS_SIZE; - - /* set endpoint 1 to 3's Tx FIFO length and RAM address */ - for (i = 1; i < USBHS_MAX_DEV_EPCOUNT; i++) { - ram_address += USBHS_TX_FIFO_SIZE[i - 1]; - - dev_in_ep_inf &= ~DIEPTFLEN_IEPTXFD; - dev_in_ep_inf |= USBHS_TX_FIFO_SIZE[i] << 16; - dev_in_ep_inf &= ~DIEPTFLEN_IEPTXRSAR; - dev_in_ep_inf |= ram_address; - - USB_DIEPxTFLEN(i) = dev_in_ep_inf; - } - } -#endif /* USBHS_CORE */ - - /* make sure all FIFOs are flushed */ - - /* flush all Tx FIFOs */ - usb_txfifo_flush(pudev, 0x10U); - - /* flush entire Rx FIFO */ - usb_rxfifo_flush(pudev); - - /* clear all pending device interrupts */ - USB_DIEPINTEN = 0U; - USB_DOEPINTEN = 0U; - USB_DAEPINT = 0xFFFFFFFF; - USB_DAEPINTEN = 0U; - - /* configure all IN/OUT endpoints */ - for (i = 0U; i < pudev->cfg.dev_endp_num; i++) { - if (USB_DIEPxCTL(i) & DIEPCTL_EPEN) { - USB_DIEPxCTL(i) |= DIEPCTL_EPD | DIEPCTL_SNAK; - } else { - USB_DIEPxCTL(i) = 0U; - } - - if (USB_DOEPxCTL(i) & DOEPCTL_EPEN) { - USB_DOEPxCTL(i) |= DOEPCTL_EPD | DOEPCTL_SNAK; - } else { - USB_DOEPxCTL(i) = 0U; - } - - /* set IN/OUT endpoint transfer length to 0 */ - USB_DIEPxLEN(i) = 0U; - USB_DOEPxLEN(i) = 0U; - - /* clear all pending IN/OUT endpoints interrupts */ - USB_DIEPxINTF(i) = 0xFFU; - USB_DOEPxINTF(i) = 0xFFU; - } - - USB_DIEPINTEN |= DIEPINTEN_EPTXFUDEN; - usb_devint_enable(pudev); - - return USB_OK; -} - -/*! - \brief enable the device mode interrupts - \param[in] pudev: pointer to usb device - \param[out] none - \retval status -*/ -static usb_status_enum usb_devint_enable(usb_core_handle_struct *pudev) -{ - uint32_t int_mask = 0U; - - /* disable all interrupts */ - USB_GINTEN = 0U; - - /* clear any pending interrupts */ - USB_GINTF = 0xBFFFFFFFU; - - /* enable the common interrupts */ - usb_commonint_enable(pudev); - - if (0U == pudev->cfg.dma_enable) { - int_mask = GINTEN_RXFNEIE; - } - - /* enable device_mode-related interrupts */ - int_mask |= GINTEN_SPIE | GINTEN_RSTIE | GINTEN_ENUMFIE \ - | GINTEN_IEPIE | GINTEN_OEPIE | GINTEN_SOFIE | GINTEN_ISOONCIE \ - | GINTEN_ISOINCIE; - -#ifdef VBUS_SENSING_ENABLED - int_mask |= GINTEN_SESIE | GINTEN_OTGIE; -#endif /* VBUS_SENSING_ENABLED */ - - USB_GINTEN &= ~int_mask; - USB_GINTEN |= int_mask; - - return USB_OK; -} - -/*! - \brief configures endpoint 0 to receive SETUP packets - \param[in] pudev: pointer to usb device - \param[out] none - \retval none -*/ -void usb_ep0_startout(usb_core_handle_struct *pudev) -{ - __IO uint32_t ep0_xlen = 0U; - - /* set OUT endpoint 0 receive length to 24 bytes */ - ep0_xlen &= ~DOEP0LEN_TLEN; - ep0_xlen |= 8U * 3U; - - /* set OUT endpoint 0 receive length to 1 packet */ - ep0_xlen &= ~DOEP0LEN_PCNT; - ep0_xlen |= 1U << 19; - - /* set SETUP packet count to 3 */ - ep0_xlen &= ~DOEP0LEN_STPCNT; - ep0_xlen |= 3U << 29; - - USB_DOEPxLEN(0U) = ep0_xlen; - - if (1U == pudev->cfg.dma_enable) { - USB_DOEPxDMAADDR(0U) = (uint32_t)&pudev->dev.setup_packet; - - USB_DOEPxCTL(0U) = DOEPCTL_EPEN | DOEPCTL_EPACT; - } -} - -/*! - \brief active remote wakeup signalling - \param[in] pudev: pointer to usb device - \param[out] none - \retval none -*/ -void usb_remotewakeup_active(usb_core_handle_struct *pudev) -{ - __IO uint32_t power_clock; - - if (pudev->dev.remote_wakeup) { - if (1U == (USB_DSTAT & DSTAT_SPST)) { - if (pudev->cfg.low_power) { - /* ungate USB core clock */ - power_clock = USB_PWRCLKCTL; - power_clock &= ~PWRCLKCTL_SHCLK; - power_clock &= ~PWRCLKCTL_SUCLK; - - USB_PWRCLKCTL = power_clock; - } - - /* active remote wakeup signaling */ - USB_DCTL |= DCTL_RWKUP; - - if (pudev->mdelay != (void *)0) { - pudev->mdelay(5U); - } - - USB_DCTL &= ~DCTL_RWKUP; - } - } -} - -/*! - \brief active USB core clock - \param[in] pudev: pointer to usb device - \param[out] none - \retval none -*/ -void usb_clock_ungate(usb_core_handle_struct *pudev) -{ - if (pudev->cfg.low_power) { - __IO uint32_t power_clock; - - if (1U == (USB_DSTAT & DSTAT_SPST)) { - /* un-gate USB core clock */ - power_clock = USB_PWRCLKCTL; - power_clock &= ~PWRCLKCTL_SHCLK; - power_clock &= ~PWRCLKCTL_SUCLK; - - USB_PWRCLKCTL = power_clock; - } - } -} - -/*! - \brief stop the device and clean up fifos - \param[in] pudev: pointer to usb device - \param[out] none - \retval none -*/ -void usb_device_stop (usb_core_handle_struct *pudev) -{ - uint32_t i; - - pudev->dev.status = 1U; - - for (i = 0U; i < pudev->cfg.dev_endp_num; i++) { - USB_DIEPxINTF(i) = 0xFFU; - USB_DOEPxINTF(i) = 0xFFU; - } - - USB_DIEPINTEN = 0U; - USB_DOEPINTEN = 0U; - USB_DAEPINTEN = 0U; - USB_DAEPINT = 0xFFFFFFFFU; - - /* flush the FIFO */ - usb_rxfifo_flush(pudev); - usb_txfifo_flush(pudev, 0x10U); -} -#endif /* USE_DEVICE_MODE */ diff --git a/bsp/gd32450z-eval/Libraries/GD32F4xx_usb_driver/Source/usbd_core.c b/bsp/gd32450z-eval/Libraries/GD32F4xx_usb_driver/Source/usbd_core.c deleted file mode 100644 index 0d15a7950f..0000000000 --- a/bsp/gd32450z-eval/Libraries/GD32F4xx_usb_driver/Source/usbd_core.c +++ /dev/null @@ -1,520 +0,0 @@ -/*! - \file usbd_core.c - \brief USB device-mode core driver -*/ - -/* - Copyright (C) 2016 GigaDevice - - 2016-08-15, V1.0.0, firmware for GD32F4xx -*/ - -#include "usbd_core.h" -#include "usbd_std.h" - -/*! - \brief initailizes the USB device-mode handler stack - \param[in] pudev: pointer to usb device instance - \param[in] core_id: USB core ID - \param[out] none - \retval none -*/ -void usbd_init (usb_core_handle_struct *pudev, usb_core_id_enum core_id) -{ - /* select USB core */ - usb_core_select (pudev, core_id); - - pudev->dev.status = USB_STATUS_DEFAULT; - - /* disable USB global interrupt */ - USB_GLOBAL_INT_DISABLE(); - - /* init the core (common init.) */ - usb_core_init(pudev); - - /* force device mode*/ - usb_mode_set(pudev, DEVICE_MODE); - - /* set device disconnect */ - USB_SOFT_DISCONNECT_ENABLE(); - - if ((void *)0 != pudev->mdelay) { - pudev->mdelay(3U); - } - - /* init device */ - usb_devcore_init(pudev); - - /* set device Connect */ - USB_SOFT_DISCONNECT_DISABLE(); - - if ((void *)0 != pudev->mdelay) { - pudev->mdelay(3U); - } - - /* enable USB global interrupt */ - USB_GLOBAL_INT_ENABLE(); -} - -/*! - \brief endpoint initialization - \param[in] pudev: pointer to usb device instance - \param[in] pep_desc: pointer to usb endpoint descriptor - \param[out] none - \retval none -*/ -void usbd_ep_init (usb_core_handle_struct *pudev, const usb_descriptor_endpoint_struct *pep_desc) -{ - usb_ep_struct *ep; - - uint32_t dev_all_ep_int_en = 0U; - uint32_t dev_ep_ctlr = 0U; - - uint8_t ep_id = pep_desc->bEndpointAddress & 0x7FU; - uint8_t ep_type = pep_desc->bmAttributes & USB_EPTYPE_MASK; - uint16_t ep_mps = pep_desc->wMaxPacketSize; - - if (pep_desc->bEndpointAddress >> 7) { - ep = &pudev->dev.in_ep[ep_id]; - - dev_all_ep_int_en |= 1U << ep_id; - dev_ep_ctlr = USB_DIEPxCTL((uint16_t)ep_id); - - /* if the endpoint is not active, need change the endpoint control register */ - if (!(dev_ep_ctlr & DIEPCTL_EPACT)) { - if (0U == ep_id) { - dev_ep_ctlr &= ~DIEP0CTL_MPL; - } else { - dev_ep_ctlr &= ~DIEPCTL_MPL; - } - dev_ep_ctlr |= ep_mps; - - dev_ep_ctlr &= ~DIEPCTL_EPTYPE; - dev_ep_ctlr |= (uint32_t)ep_type << 18; - - dev_ep_ctlr &= ~DIEPCTL_TXFNUM; - dev_ep_ctlr |= (uint32_t)ep_id << 22; - - if (0U != ep_id) { - dev_ep_ctlr |= DIEPCTL_SD0PID; - dev_ep_ctlr |= DIEPCTL_EPACT; - } - - USB_DIEPxCTL((uint16_t)ep_id) = dev_ep_ctlr; - } - } else { - ep = &pudev->dev.out_ep[ep_id]; - - dev_all_ep_int_en |= (1U << ep_id) << 16; - dev_ep_ctlr = USB_DOEPxCTL((uint16_t)ep_id); - - /* if the endpoint is not active, need change the endpoint control register */ - if (!(dev_ep_ctlr & DOEPCTL_EPACT)) { - if (0U == ep_id) { - dev_ep_ctlr &= ~DOEP0CTL_MPL; - } else { - dev_ep_ctlr &= ~DOEPCTL_MPL; - } - dev_ep_ctlr |= ep_mps; - - dev_ep_ctlr &= ~DOEPCTL_EPTYPE; - dev_ep_ctlr |= (uint32_t)ep_type << 18; - - if (0U != ep_id) { - dev_ep_ctlr |= DOEPCTL_SD0PID; - dev_ep_ctlr |= DOEPCTL_EPACT; - } - - USB_DOEPxCTL((uint16_t)ep_id) = dev_ep_ctlr; - } - } - - ep->endp_mps = ep_mps; - ep->endp_type = ep_type; - - /* enable the interrupts for this endpoint */ -#ifdef USBHS_DEDICATED_EP1_ENABLED - if ((1 == ep_id) && (USB_HS_CORE_ID == pudev->cfg.core_id)) { - USB_DEP1INTEN |= dev_all_ep_int_en; - } else -#endif /* USBHS_DEDICATED_EP1_ENABLED */ - { - USB_DAEPINTEN |= dev_all_ep_int_en; - } -} - -/*! - \brief endpoint deinitialize - \param[in] pudev: pointer to usb device instance - \param[in] ep_addr: endpoint address - \param[out] none - \retval none -*/ -void usbd_ep_deinit (usb_core_handle_struct *pudev, uint8_t ep_addr) -{ - uint32_t dev_all_ep_int_en = 0U; - uint8_t ep_id = ep_addr & 0x7FU; - - if (ep_addr >> 7) { - dev_all_ep_int_en |= 1U << ep_id; - - USB_DIEPxCTL((uint16_t)ep_id) &= ~DIEPCTL_EPACT; - } else { - dev_all_ep_int_en |= (1U << ep_id) << 16U; - - USB_DOEPxCTL((uint16_t)ep_id) &= ~DOEPCTL_EPACT; - } - - /* disable the interrupts for this endpoint */ -#ifdef USBHS_DEDICATED_EP1_ENABLED - if ((1U == ep_id) && (USB_HS_CORE_ID == pudev->cfg.core_id)) { - USB_DEP1INTEN &= ~dev_all_ep_int_en; - } else -#endif /* USBHS_DEDICATED_EP1_ENABLED */ - { - USB_DAEPINTEN &= ~dev_all_ep_int_en; - } -} - -/*! - \brief endpoint prepare to receive data - \param[in] pudev: pointer to usb device instance - \param[in] ep_addr: endpoint address - \param[in] pbuf: pointer to buffer - \param[in] buf_len: buffer length - \param[out] none - \retval none -*/ -void usbd_ep_rx (usb_core_handle_struct *pudev, uint8_t ep_addr, uint8_t *pbuf, uint16_t buf_len) -{ - usb_ep_struct *ep; - uint8_t ep_id = ep_addr & 0x7FU; - uint32_t dev_ep_ctlr = 0U, dev_ep_xlen = 0U; - - ep = &pudev->dev.out_ep[ep_id]; - - /* setup and start the Xfer */ - ep->xfer_buff = pbuf; - ep->xfer_len = buf_len; - ep->xfer_count = 0U; - - if (1U == pudev->cfg.dma_enable) { - ep->dma_addr = (uint32_t)pbuf; - } - - dev_ep_ctlr = USB_DOEPxCTL((uint16_t)ep_id); - dev_ep_xlen = USB_DOEPxLEN((uint16_t)ep_id); - - dev_ep_xlen &= ~DOEPLEN_TLEN; - dev_ep_xlen &= ~DOEPLEN_PCNT; - - /* zero length packet */ - if (0U == ep->xfer_len) { - /* set the transfer length to max packet size */ - dev_ep_xlen |= ep->endp_mps; - - /* set the transfer packet count to 1 */ - dev_ep_xlen |= 1U << 19U; - } else { - if (0U == ep_id) { - /* set the transfer length to max packet size */ - dev_ep_xlen |= ep->endp_mps; - - /* set the transfer packet count to 1 */ - dev_ep_xlen |= 1U << 19U; - } else { - /* configure the transfer size and packet count as follows: - * pktcnt = N - * xfersize = N * maxpacket - */ - dev_ep_xlen |= ((ep->xfer_len + ep->endp_mps - 1U) / ep->endp_mps) << 19U; - dev_ep_xlen |= ((dev_ep_xlen & DOEPLEN_PCNT) >> 19U) * ep->endp_mps; - } - } - - USB_DOEPxLEN((uint16_t)ep_id) = dev_ep_xlen; - - if (1U == pudev->cfg.dma_enable) { - USB_DOEPxDMAADDR((uint16_t)ep_id) = ep->dma_addr; - } - - if (USB_EPTYPE_ISOC == ep->endp_type) { - if (ep->endp_frame) { - dev_ep_ctlr |= DOEPCTL_SODDFRM; - } else { - dev_ep_ctlr |= DOEPCTL_SEVNFRM; - } - } - - /* enable the endpoint and clear the NAK */ - dev_ep_ctlr |= DOEPCTL_EPEN | DOEPCTL_CNAK; - - USB_DOEPxCTL((uint16_t)ep_id) = dev_ep_ctlr; -} - -/*! - \brief endpoint prepare to transmit data - \param[in] pudev: pointer to usb device instance - \param[in] ep_addr: endpoint address - \param[in] pbuf: pointer to buffer - \param[in] len: buffer length - \param[out] none - \retval none -*/ -void usbd_ep_tx (usb_core_handle_struct *pudev, uint8_t ep_addr, uint8_t *pbuf, uint32_t buf_len) -{ - usb_ep_struct *ep; - uint8_t ep_id = ep_addr & 0x7FU; - __IO uint32_t dev_ep_ctlr = 0U; - __IO uint32_t dev_ep_xlen = 0U; - - ep = &pudev->dev.in_ep[ep_id]; - - /* setup and start the transfer */ - ep->xfer_buff = pbuf; - ep->xfer_len = buf_len; - ep->xfer_count = 0U; - - if (1U == pudev->cfg.dma_enable) { - ep->dma_addr = (uint32_t)pbuf; - } - - dev_ep_ctlr = USB_DIEPxCTL((uint16_t)ep_id); - dev_ep_xlen = USB_DIEPxLEN((uint16_t)ep_id); - - /* clear transfer length to 0 */ - dev_ep_xlen &= ~DIEPLEN_TLEN; - - /* clear transfer packet to 0 */ - dev_ep_xlen &= ~DIEPLEN_PCNT; - - /* zero length packet */ - if (0U == ep->xfer_len) { - /* set transfer packet count to 1 */ - dev_ep_xlen |= 1U << 19U; - } else { - if (0U == ep_id) { - if (ep->xfer_len > ep->endp_mps) { - ep->xfer_len = ep->endp_mps; - } - - dev_ep_xlen |= 1U << 19U; - } else { - dev_ep_xlen |= ((ep->xfer_len - 1U + ep->endp_mps) / ep->endp_mps) << 19U; - } - - /* configure the transfer size and packet count as follows: - * xfersize = N * maxpacket + short_packet - * pktcnt = N + (short_packet exist ? 1 : 0) - */ - dev_ep_xlen |= ep->xfer_len; - - if (USB_EPTYPE_ISOC == ep->endp_type) { - dev_ep_xlen |= DIEPLEN_MCNT & (1U << 29U); - } - } - - USB_DIEPxLEN((uint16_t)ep_id) = dev_ep_xlen; - - if (USB_EPTYPE_ISOC == ep->endp_type) { - if (0U == (((USB_DSTAT & DSTAT_FNRSOF) >> 8U) & 0x1U)) { - dev_ep_ctlr |= DIEPCTL_SODDFRM; - } else { - dev_ep_ctlr |= DIEPCTL_SEVNFRM; - } - } - - if (1U == pudev->cfg.dma_enable) { - USB_DIEPxDMAADDR((uint16_t)ep_id) = ep->dma_addr; - } - - /* enable the endpoint and clear the NAK */ - dev_ep_ctlr |= DIEPCTL_EPEN | DIEPCTL_CNAK; - - USB_DIEPxCTL((uint16_t)ep_id) = dev_ep_ctlr; - - if (0U == pudev->cfg.dma_enable) { - if (USB_EPTYPE_ISOC != ep->endp_type) { - /* enable the Tx FIFO empty interrupt for this endpoint */ - if (ep->xfer_len > 0U) { - USB_DIEPFEINTEN |= 1U << ep_id; - } - } else { - usb_fifo_write(ep->xfer_buff, ep_id, (uint16_t)ep->xfer_len); - } - } -} - -/*! - \brief transmit data on the control channel - \param[in] pudev: pointer to usb device instance - \param[in] pbuf: pointer to buffer - \param[in] len: buffer length - \param[out] none - \retval usb device operation status -*/ -usbd_status_enum usbd_ctltx (usb_core_handle_struct *pudev, uint8_t *pbuf, uint16_t len) -{ - usbd_status_enum ret = USBD_OK; - - pudev->dev.sum_len = len; - pudev->dev.remain_len = len; - pudev->dev.ctl_status = USB_CTRL_DATA_IN; - - usbd_ep_tx (pudev, 0U, pbuf, (uint32_t)len); - - return ret; -} - -/*! - \brief receive data on the control channel - \param[in] pudev: pointer to usb device instance - \param[in] pbuf: pointer to buffer - \param[in] len: buffer length - \param[out] none - \retval usb device operation status -*/ -usbd_status_enum usbd_ctlrx (usb_core_handle_struct *pudev, uint8_t *pbuf, uint16_t len) -{ - pudev->dev.sum_len = len; - pudev->dev.remain_len = len; - pudev->dev.ctl_status = USB_CTRL_DATA_OUT; - - usbd_ep_rx (pudev, 0U, pbuf, len); - - return USBD_OK; -} - -/*! - \brief transmit status on the control channel - \param[in] pudev: pointer to usb device instance - \param[out] none - \retval usb device operation status -*/ -usbd_status_enum usbd_ctlstatus_tx (usb_core_handle_struct *pudev) -{ - pudev->dev.ctl_status = USB_CTRL_STATUS_IN; - - usbd_ep_tx (pudev, 0U, NULL, 0U); - - usb_ep0_startout(pudev); - - return USBD_OK; -} - -/*! - \brief receive status on the control channel - \param[in] pudev: pointer to usb device instance - \param[out] none - \retval usb device operation status -*/ -usbd_status_enum usbd_ctlstatus_rx (usb_core_handle_struct *pudev) -{ - pudev->dev.ctl_status = USB_CTRL_STATUS_OUT; - - usbd_ep_rx (pudev, 0U, NULL, 0U); - - usb_ep0_startout(pudev); - - return USBD_OK; -} - -/*! - \brief set an endpoint to STALL status - \param[in] pudev: pointer to usb device instance - \param[in] ep_addr: endpoint address - \param[out] none - \retval none -*/ -void usbd_ep_stall (usb_core_handle_struct *pudev, uint8_t ep_addr) -{ - uint8_t ep_id = ep_addr & 0x7FU; - __IO uint32_t dev_ep_ctlr = 0U; - - if (ep_addr >> 7U) { - dev_ep_ctlr = USB_DIEPxCTL((uint16_t)ep_id); - - /* set the endpoint disable bit */ - if (dev_ep_ctlr & DIEPCTL_EPEN) { - dev_ep_ctlr |= DIEPCTL_EPD; - } - - /* set the endpoint stall bit */ - dev_ep_ctlr |= DIEPCTL_STALL; - - USB_DIEPxCTL((uint16_t)ep_id) = dev_ep_ctlr; - } else { - /* set the endpoint stall bit */ - USB_DOEPxCTL((uint16_t)ep_id) |= DOEPCTL_STALL; - } -} - -/*! - \brief clear endpoint stalled status - \param[in] pudev: pointer to usb device instance - \param[in] ep_addr: endpoint address - \param[out] none - \retval none -*/ -void usbd_ep_clear_stall (usb_core_handle_struct *pudev, uint8_t ep_addr) -{ - usb_ep_struct *ep; - uint8_t ep_id = ep_addr & 0x7FU; - __IO uint32_t dev_ep_ctlr = 0U; - - if(ep_addr >> 7){ - ep = &pudev->dev.in_ep[ep_id]; - - dev_ep_ctlr = USB_DIEPxCTL((uint16_t)ep_id); - - /* clear the IN endpoint stall bits */ - dev_ep_ctlr &= ~DIEPCTL_STALL; - - if ((USB_EPTYPE_INTR == ep->endp_type) || (USB_EPTYPE_BULK == ep->endp_type)) { - dev_ep_ctlr |= DIEPCTL_SEVNFRM; - } - - USB_DIEPxCTL((uint16_t)ep_id) = dev_ep_ctlr; - } else { - ep = &pudev->dev.out_ep[ep_id]; - - dev_ep_ctlr = USB_DOEPxCTL((uint16_t)ep_id); - - /* clear the OUT endpoint stall bits */ - dev_ep_ctlr &= ~DOEPCTL_STALL; - - if ((USB_EPTYPE_INTR == ep->endp_type) || (USB_EPTYPE_BULK == ep->endp_type)) { - dev_ep_ctlr |= DOEPCTL_SEVNFRM; - } - - USB_DOEPxCTL((uint16_t)ep_id) = dev_ep_ctlr; - } -} - -/*! - \brief flushes the FIFOs - \param[in] pudev: pointer to usb device instance - \param[in] ep_addr: endpoint address - \param[out] none - \retval none -*/ -void usbd_ep_fifo_flush (usb_core_handle_struct *pudev, uint8_t ep_addr) -{ - if (ep_addr >> 7) { - usb_txfifo_flush(pudev, ep_addr & 0x7FU); - } else { - usb_rxfifo_flush(pudev); - } -} - -/*! - \brief get the received data length - \param[in] pudev: pointer to usb device instance - \param[in] ep_id: endpoint identifier which is in (0..3) - \param[out] none - \retval received data length -*/ -uint16_t usbd_rxcount_get (usb_core_handle_struct *pudev, uint8_t ep_id) -{ - return (uint16_t)pudev->dev.out_ep[ep_id].xfer_count; -} diff --git a/bsp/gd32450z-eval/Libraries/GD32F4xx_usb_driver/Source/usbd_int.c b/bsp/gd32450z-eval/Libraries/GD32F4xx_usb_driver/Source/usbd_int.c deleted file mode 100644 index 01338e2e9b..0000000000 --- a/bsp/gd32450z-eval/Libraries/GD32F4xx_usb_driver/Source/usbd_int.c +++ /dev/null @@ -1,758 +0,0 @@ -/*! - \file usbd_int.c - \brief USB device mode interrupt routines -*/ - -/* - Copyright (C) 2016 GigaDevice - - 2016-08-15, V1.0.0, firmware for GD32F4xx -*/ - -#include "usbd_int.h" -#include "usbd_std.h" - -/* interrupt handlers */ -static uint32_t usbd_intf_outep (usb_core_handle_struct *pudev); -static uint32_t usbd_intf_inep (usb_core_handle_struct *pudev); -static uint32_t usbd_intf_earlysuspend (usb_core_handle_struct *pudev); -static uint32_t usbd_intf_suspend (usb_core_handle_struct *pudev); -static uint32_t usbd_intf_resume (usb_core_handle_struct *pudev); -static uint32_t usbd_intf_sof (usb_core_handle_struct *pudev); -static uint32_t usbd_intf_rxfifo (usb_core_handle_struct *pudev); -static uint32_t usbd_intf_reset (usb_core_handle_struct *pudev); -static uint32_t usbd_intf_enumfinish (usb_core_handle_struct *pudev); -static uint32_t usbd_intf_isoinincomplete (usb_core_handle_struct *pudev); -static uint32_t usbd_intf_isooutincomplete (usb_core_handle_struct *pudev); - -static uint32_t usbd_emptytxfifo_write (usb_core_handle_struct *pudev, uint8_t ep_num); - -#ifdef VBUS_SENSING_ENABLED - - static uint32_t usbd_intf_otg (usb_core_handle_struct *pudev); - static uint32_t usbd_intf_sessionrequest (usb_core_handle_struct *pudev); - -#endif - -static usb_speed_enum USB_SPEED[4] = { - [DSTAT_ENUMSPD_HS_PHY_30MHZ_OR_60MHZ] = USB_SPEED_HIGH, - [DSTAT_ENUMSPD_FS_PHY_30MHZ_OR_60MHZ] = USB_SPEED_FULL, - [DSTAT_ENUMSPD_FS_PHY_48MHZ] = USB_SPEED_FULL, - [DSTAT_ENUMSPD_LS_PHY_6MHZ] = USB_SPEED_LOW -}; - -static const uint8_t EP0_MAXLEN[4] = { - [DSTAT_ENUMSPD_HS_PHY_30MHZ_OR_60MHZ] = EP0MPL_64, - [DSTAT_ENUMSPD_FS_PHY_30MHZ_OR_60MHZ] = EP0MPL_64, - [DSTAT_ENUMSPD_FS_PHY_48MHZ] = EP0MPL_64, - [DSTAT_ENUMSPD_LS_PHY_6MHZ] = EP0MPL_8 -}; - -#ifdef USBHS_DEDICATED_EP1_ENABLED - -/*! - \brief USB dedicated OUT endpoint 1 interrupt service routine handler - \param[in] pudev: pointer to usb device instance - \param[out] none - \retval operation status -*/ -uint32_t USBD_EP1OUT_ISR_Handler (usb_core_handle_struct *pudev) -{ - uint32_t out_endp_int = 0; - uint32_t out_endp_size = 0; - - out_endp_int = USB_DOEPxINTF(1); - out_endp_int &= USB_DOEP1INTEN; - - /* transfer complete */ - if (out_endp_int & DOEPINTF_TF) { - /* clear the interrupt bit */ - USB_DOEPxINTF(1) = DOEPINTF_TF; - - if (1U == pudev->cfg.dma_enable) { - out_endp_size = USB_DOEPxLEN(1); - - /* handle more than one single MPS size packet */ - pudev->dev.out_ep[1].xfer_count = pudev->dev.out_ep[1].endp_mps - \ - (out_endp_size & DOEPLEN_TLEN); - } - - /* inform upper layer: data ready */ - - /* receive complete */ - usbd_out_transaction(pudev, 1); - } - - /* endpoint disable interrupt */ - if (out_endp_int & DOEPINTF_EPDIS) { - /* clear the interrupt bit */ - USB_DOEPxINTF(1) = DOEPINTF_EPDIS; - } - - return 1; -} - -/*! - \brief USB dedicated IN endpoint 1 interrupt service routine handler - \param[in] pudev: pointer to usb device instance - \param[out] none - \retval operation status -*/ -uint32_t USBD_EP1IN_ISR_Handler (usb_core_handle_struct *pudev) -{ - uint32_t fifoemptymask = 0, mask = 0; - uint32_t in_endp_int = 0; - - mask = USB_DIEP1INTEN; - mask |= ((USB_DIEPFEINTEN >> 1) & 0x01) << 7; - in_endp_int = USB_DIEPxINTF(1) & mask; - - if (in_endp_int & DIEPINTF_TF) { - fifoemptymask = 0x01 << 1; - USB_DIEPFEINTEN &= ~fifoemptymask; - - USB_DIEPxINTF(1) = DIEPINTF_TF; - - /* transmit complete */ - usbd_in_transaction(pudev , 1); - } - - if (in_endp_int & DIEPINTF_EPDIS) { - USB_DIEPxINTF(1) = DIEPINTF_EPDIS; - } - - if (in_endp_int & DIEPINTF_CITO) { - USB_DIEPxINTF(1) = DIEPINTF_CITO; - } - - if (in_endp_int & DIEPINTF_EPTXFUD) { - USB_DIEPxINTF(1) = DIEPINTF_EPTXFUD; - } - - if (in_endp_int & DIEPINTF_IEPNE) { - USB_DIEPxINTF(1) = DIEPINTF_IEPNE; - } - - if (in_endp_int & DIEPINTF_TXFE) { - usbd_emptytxfifo_write(pudev, 1); - - USB_DIEPxINTF(1) = DIEPINTF_IEPNE; - } - - return 1; -} - -#endif - - -/*! - \brief USB device-mode interrupts global service routine handler - \param[in] pudev: pointer to usb device instance - \param[out] none - \retval operation status -*/ -uint32_t usbd_isr (usb_core_handle_struct *pudev) -{ - uint32_t retval = 0U; - uint32_t int_status = 0U, gintf = USB_GINTF, ginten = USB_GINTEN; - - /* ensure the core is in device mode */ - if (DEVICE_MODE == USB_CURRENT_MODE_GET()) { - int_status = gintf & ginten; - - /* there are no interrupts, avoid spurious interrupt */ - if (!int_status) { - return 0U; - } - - /* OUT endpoints interrupts */ - if (int_status & GINTF_OEPIF) { - retval |= usbd_intf_outep(pudev); - } - - /* IN endpoints interrupts */ - if (int_status & GINTF_IEPIF) { - retval |= usbd_intf_inep(pudev); - } - - /* mode mismatch interrupt */ - if (int_status & GINTF_MFIF) { - /* clear interrupt */ - USB_GINTF = GINTF_MFIF; - } - - /* early suspend interrupt */ - if (int_status & GINTF_ESP) { - retval |= usbd_intf_earlysuspend(pudev); - } - - /* suspend interrupt */ - if (int_status & GINTF_SP) { - retval |= usbd_intf_suspend(pudev); - } - - /* wakeup interrupt */ - if (int_status & GINTF_WKUPIF) { - retval |= usbd_intf_resume(pudev); - } - - /* start of frame interrupt */ - if (int_status & GINTF_SOF) { - retval |= usbd_intf_sof(pudev); - } - - /* reveive fifo not empty interrupt */ - if (int_status & GINTF_RXFNEIF) { - retval |= usbd_intf_rxfifo(pudev); - } - - /* USB reset interrupt */ - if (int_status & GINTF_RST) { - retval |= usbd_intf_reset(pudev); - } - - /* enumeration has been finished interrupt */ - if (int_status & GINTF_ENUMFIF) { - retval |= usbd_intf_enumfinish(pudev); - } - - /* incomplete synchronization in transfer interrupt*/ - if (int_status & GINTF_ISOINCIF) { - retval |= usbd_intf_isoinincomplete(pudev); - } - - /* incomplete synchronization out transfer interrupt*/ - if (int_status & GINTF_ISOONCIF) { - retval |= usbd_intf_isooutincomplete(pudev); - } - -#ifdef VBUS_SENSING_ENABLED - - /* session request interrupt */ - if (int_status & GINTF_SESIF) { - retval |= usbd_intf_sessionrequest(pudev); - } - - /* OTG mode interrupt */ - if (int_status & GINTF_OTGIF) { - retval |= usbd_intf_otg(pudev); - } -#endif /* VBUS_SENSING_ENABLED */ - } - - return retval; -} - -/*! - \brief indicates that an OUT endpoint has a pending interrupt - \param[in] pudev: pointer to usb device instance - \param[out] none - \retval operation status -*/ -static uint32_t usbd_intf_outep (usb_core_handle_struct *pudev) -{ - uint8_t endp_num = 0U; - uint32_t endp_intr = 0U; - - __IO uint32_t out_endp_intr = 0U; - - /* read in the device interrupt bits */ - USB_DAOEP_INTR_READ(endp_intr); - - while (endp_intr) { - if (endp_intr & 0x1U) { - USB_DOEP_INTR_READ(out_endp_intr, (uint16_t)endp_num); - - /* transfer complete interrupt */ - if (out_endp_intr & DOEPINTF_TF) { - USB_DOEPxINTF((uint16_t)endp_num) = DOEPINTF_TF; - - if (1U == pudev->cfg.dma_enable) { - uint32_t xfer_size = USB_DOEPxLEN((uint16_t)endp_num) & DOEPLEN_TLEN; - - pudev->dev.out_ep[endp_num].xfer_count = pudev->dev.out_ep[endp_num].endp_mps - \ - xfer_size; - } - - /* data receive is completed */ - usbd_out_transaction(pudev, endp_num); - - if (1U == pudev->cfg.dma_enable) { - if ((0U == endp_num) && (USB_CTRL_STATUS_OUT == pudev->dev.ctl_status)) { - /* prepare to receive more setup packets */ - usb_ep0_startout(pudev); - } - } - } - - /* endpoint disable interrupt */ - if (out_endp_intr & DOEPINTF_EPDIS) { - USB_DOEPxINTF((uint16_t)endp_num) = DOEPINTF_EPDIS; - } - - /* setup phase finished interrupt (just for control endpoints) */ - if (out_endp_intr & DOEPINTF_STPF) { - /* setup phase is completed */ - usbd_setup_transaction(pudev); - - USB_DOEPxINTF((uint16_t)endp_num) = DOEPINTF_STPF; - } - - /* back to back setup packets received */ - if (out_endp_intr & DOEPINTF_BTBSTP) { - USB_DOEPxINTF((uint16_t)endp_num) = DOEPINTF_BTBSTP; - } - } - - endp_num ++; - endp_intr >>= 1; - } - - return 1U; -} - -/*! - \brief indicates that an IN endpoint has a pending interrupt - \param[in] pudev: pointer to usb device instance - \param[out] none - \retval operation status -*/ -static uint32_t usbd_intf_inep(usb_core_handle_struct *pudev) -{ - uint8_t endp_num = 0U; - uint32_t endp_intr = 0U; - - __IO uint32_t in_endp_intr = 0U; - - /* get all in endpoints which have interrupts */ - USB_DAIEP_INTR_READ(endp_intr); - - while (endp_intr) { - if (endp_intr & 0x1U) { - USB_DIEP_INTR_READ(in_endp_intr, (uint16_t)endp_num); - - if (in_endp_intr & DIEPINTF_TF) { - /* disable the fifo empty interrupt for the endpoint */ - USB_DIEPFEINTEN &= ~(0x1U << endp_num); - - USB_DIEPxINTF((uint16_t)endp_num) = DIEPINTF_TF; - - /* data transmittion is completed */ - usbd_in_transaction(pudev, endp_num); - - if (1U == pudev->cfg.dma_enable) { - if ((0U == endp_num) && (USB_CTRL_STATUS_IN == pudev->dev.ctl_status)) { - /* prepare to receive more setup packets */ - usb_ep0_startout(pudev); - } - } - } - - if (in_endp_intr & DIEPINTF_CITO) { - USB_DIEPxINTF((uint16_t)endp_num) = DIEPINTF_CITO; - } - - if (in_endp_intr & DIEPINTF_IEPNE) { - USB_DIEPxINTF((uint16_t)endp_num) = DIEPINTF_IEPNE; - } - - if (in_endp_intr & DIEPINTF_EPDIS) { - USB_DIEPxINTF((uint16_t)endp_num) = DIEPINTF_EPDIS; - } - - if (in_endp_intr & DIEPINTF_TXFE) { - usbd_emptytxfifo_write(pudev, endp_num); - USB_DIEPxINTF((uint16_t)endp_num) = DIEPINTF_TXFE; - } - } - - endp_num ++; - endp_intr >>= 1; - } - - return 1U; -} - -/*! - \brief indicates that early SUSPEND state has been detected on the USB - \param[in] pudev: pointer to usb device instance - \param[out] none - \retval operation status -*/ -static uint32_t usbd_intf_earlysuspend (usb_core_handle_struct *pudev) -{ - USB_GINTEN &= ~GINTEN_ESPIE; - USB_GINTF = GINTF_ESP; - - return 1U; -} - -/*! - \brief indicates that SUSPEND state has been detected on the USB - \param[in] pudev: pointer to usb device instance - \param[out] none - \retval operation status -*/ -static uint32_t usbd_intf_suspend(usb_core_handle_struct *pudev) -{ - __IO uint8_t low_power = pudev->cfg.low_power; - __IO uint8_t suspend = (uint8_t)(USB_DSTAT & DSTAT_SPST); - __IO uint8_t is_configured = (pudev->dev.status == USB_STATUS_CONFIGURED)? 1U : 0U; - - pudev->dev.prev_status = pudev->dev.status; - pudev->dev.status = USB_STATUS_SUSPENDED; - - if (low_power && suspend && is_configured) { - /* switch-off the otg clocks */ - USB_PWRCLKCTL |= PWRCLKCTL_SUCLK | PWRCLKCTL_SHCLK; - - /* enter DEEP_SLEEP mode with LDO in low power mode */ - pmu_to_deepsleepmode(PMU_LDO_LOWPOWER, WFI_CMD); - } - - /* clear interrupt */ - USB_GINTF = GINTF_SP; - - return 1U; -} - -/*! - \brief indicates that the USB controller has detected a resume or remote Wake-up sequence - \param[in] pudev: pointer to usb device instance - \param[out] none - \retval operation status -*/ -static uint32_t usbd_intf_resume (usb_core_handle_struct *pudev) -{ - pudev->dev.status = pudev->dev.prev_status; - pudev->dev.status = USB_STATUS_CONFIGURED; - - /* clear interrupt */ - USB_GINTF = GINTF_WKUPIF; - - return 1U; -} - -/*! - \brief handle the SOF interrupts - \param[in] pudev: pointer to usb device instance - \param[out] none - \retval operation status -*/ -static uint32_t usbd_intf_sof(usb_core_handle_struct *pudev) -{ -// USBD_DCD_INT_fops->SOF(pudev); - - USB_GINTF = GINTF_SOF; - - return 1U; -} - -/*! - \brief handle the Rx status queue level interrupt - \param[in] pudev: pointer to usb device instance - \param[out] none - \retval operation status -*/ -static uint32_t usbd_intf_rxfifo (usb_core_handle_struct *pudev) -{ - usb_ep_struct *ep; - uint8_t data_pid = 0U, endp_num = 0U; - uint32_t bcount = 0U; - - /* get the status from the top of the fifo (must be read to a variable) */ - __IO uint32_t rx_status = USB_GRSTATP; - - /* disable the rx fifo non-empty interrupt */ - USB_GINTEN &= ~GINTEN_RXFNEIE; - - endp_num = (uint8_t)(rx_status & GRSTATP_EPNUM); - bcount = (rx_status & GRSTATP_BCOUNT) >> 4U; - data_pid = (uint8_t)((rx_status & GRSTATP_DPID) >> 15U); - - if ((endp_num == 1) && ((*(uint32_t *)0x40040B30 & 0x1FF80000) == 0)) { - *(uint32_t *)0x40040B20 = ((*(uint32_t *)0x40040B20 | 0x08000000) & 0x3FFFFFFF); - } - - ep = &pudev->dev.out_ep[endp_num]; - - switch ((rx_status & GRSTATP_RPCKST) >> 17U) { - case RXSTAT_GOUT_NAK: - if(0U != bcount) { - return 0U; - } - break; - case RXSTAT_DATA_UPDT: - if (bcount > 0U) { - usb_fifo_read(ep->xfer_buff, (uint16_t)bcount); - ep->xfer_buff += bcount; - ep->xfer_count += bcount; - } - break; - case RXSTAT_XFER_COMP: - if (0U != bcount) { - return 0U; - } - break; - case RXSTAT_SETUP_COMP: - if(0U != bcount) { - return 0U; - } - break; - case RXSTAT_SETUP_UPDT: - if ((0U == endp_num) && (8U == bcount) && (DPID_DATA0 == data_pid)) { - /* copy the setup packet received in fifo into the setup buffer in ram */ - usb_fifo_read(pudev->dev.setup_packet, 8U); - - ep->xfer_count += bcount; - } - break; - default: - break; - } - - /* enable the Rx fifo non-empty interrupt */ - USB_GINTEN |= GINTEN_RXFNEIE; - - return 1U; -} - -/*! - \brief handle USB reset interrupt - \param[in] pudev: pointer to usb device instance - \param[out] none - \retval status -*/ -static uint32_t usbd_intf_reset(usb_core_handle_struct *pudev) -{ - uint8_t i = 0U; - usb_ep_struct *ep; - - /* clear the remote wakeup signaling */ - USB_DCTL &= ~DCTL_RWKUP; - - /* flush the tx fifo */ - usb_txfifo_flush(pudev, 0U); - - for (i = 0U; i < pudev->cfg.dev_endp_num; i++) { - USB_DIEPxINTF((uint16_t)i) = 0xFFU; - USB_DOEPxINTF((uint16_t)i) = 0xFFU; - } - - /* clear all pending device endpoint interrupts */ - USB_DAEPINT = 0xFFFFFFFF; - - /* enable endpoint 0 interrupts */ - USB_DAEPINTEN &= ~DAEPINTEN_OEPIE; - USB_DAEPINTEN &= ~DAEPINTEN_IEPIE; - USB_DAEPINTEN = (1U << 16) | 1U; - - /* enable out endpoint interrupts */ - USB_DOEPINTEN = DOEPINTEN_STPFEN | DOEPINTEN_TFEN | DOEPINTEN_EPDISEN; - -#ifdef USBHS_DEDICATED_EP1_ENABLED - USB_DOEP1INTEN = DOEPINTEN_STPFEN | DOEPINTEN_TFEN | DOEPINTEN_EPDISEN; -#endif - - /* enable in endpoint interrupts */ - USB_DIEPINTEN = DIEPINTEN_TFEN | DIEPINTEN_CITOEN | DIEPINTEN_EPDISEN; - -#ifdef USBHS_DEDICATED_EP1_ENABLED - USB_DIEP1INTEN = DIEPINTEN_TFEN | DIEPINTEN_CITOEN | DIEPINTEN_EPDISEN; -#endif - - /* reset device address */ - USB_DCFG &= ~DCFG_DAR; - USB_DCFG |= 0U << 4U; - - /* configure endpoint 0 to receive setup packets */ - usb_ep0_startout(pudev); - - /* clear usb reset interrupt */ - USB_GINTF = GINTF_RST; - - /* open EP0 IN */ - ep = &pudev->dev.in_ep[0]; - - USB_DIEPxCTL(0U) &= ~DIEP0CTL_MPL; - USB_DIEPxCTL(0U) &= ~DIEPCTL_EPTYPE; - USB_DIEPxCTL(0U) &= ~DIEPCTL_TXFNUM; - - if (!(USB_DIEPxCTL(0U) & DIEPCTL_EPACT)) { - USB_DIEPxCTL(0U) |= USB_MAX_EP0_SIZE; - USB_DIEPxCTL(0U) |= (USB_EPTYPE_CTRL << 18U); - USB_DIEPxCTL(0U) |= DIEP0CTL_EPACT; - } - - ep->endp_mps = USB_MAX_EP0_SIZE; - ep->endp_type = USB_EPTYPE_CTRL; - - /* open EP0 OUT */ - ep = &pudev->dev.out_ep[0]; - - USB_DOEPxCTL(0U) &= ~DOEP0CTL_MPL; - USB_DOEPxCTL(0U) &= ~DOEPCTL_EPTYPE; - - if (!(USB_DOEPxCTL(0U) & DOEPCTL_EPACT)) { - USB_DOEPxCTL(0U) |= USB_MAX_EP0_SIZE; - USB_DOEPxCTL(0U) |= (USB_EPTYPE_CTRL << 18U); - USB_DOEPxCTL(0U) |= DOEP0CTL_EPACT; - } - - ep->endp_mps = USB_MAX_EP0_SIZE; - ep->endp_type = USB_EPTYPE_CTRL; - - pudev->dev.status = USB_STATUS_DEFAULT; - - return 1U; -} - -/*! - \brief handle enumeration finish interrupt - \param[in] pudev: pointer to usb device instance - \param[out] none - \retval status -*/ -static uint32_t usbd_intf_enumfinish(usb_core_handle_struct *pudev) -{ - uint8_t enum_speed = (uint8_t)((USB_DSTAT & DSTAT_ES) >> 1U); - - /* set the max packet size of devie in endpoint based on the enumeration speed */ - USB_DIEPxCTL(0U) |= EP0_MAXLEN[enum_speed]; - - /* clear global IN NAK */ - USB_DCTL &= ~DCTL_CGINAK; - USB_DCTL |= DCTL_CGINAK; - - /* set USB turn-around time based on device speed and PHY interface */ - if (USB_SPEED_HIGH == USB_SPEED[enum_speed]) { - pudev->cfg.core_speed = USB_CORE_SPEED_HIGH; - pudev->cfg.max_packet_size = USBHS_MAX_PACKET_SIZE; - - USB_GUSBCS &= ~GUSBCS_UTT; - USB_GUSBCS |= 0x09U << 10; - } else { - pudev->cfg.core_speed = USB_CORE_SPEED_FULL; - pudev->cfg.max_packet_size = USBFS_MAX_PACKET_SIZE; - - USB_GUSBCS &= ~GUSBCS_UTT; - USB_GUSBCS |= 0x05U << 10; - } - - /* clear interrupt */ - USB_GINTF = GINTF_ENUMFIF; - - return 1U; -} - -/*! - \brief handle the ISO IN incomplete interrupt - \param[in] pudev: pointer to usb device instance - \param[out] none - \retval status -*/ -static uint32_t usbd_intf_isoinincomplete(usb_core_handle_struct *pudev) -{ -// USBD_DCD_INT_fops->IsoINIncomplete (pudev); - - /* clear interrupt */ - USB_GINTF = GINTF_ISOINCIF; - - return 1U; -} - -/*! - \brief handle the ISO OUT incomplete interrupt - \param[in] pudev: pointer to usb device instance - \param[out] none - \retval status -*/ -static uint32_t usbd_intf_isooutincomplete(usb_core_handle_struct *pudev) -{ -// USBD_DCD_INT_fops->IsoOUTIncomplete (pudev); - - /* clear interrupt */ - USB_GINTF = GINTF_ISOONCIF; - - return 1U; -} - -/*! - \brief check FIFO for the next packet to be loaded - \param[in] pudev: pointer to usb device instance - \param[in] ep_id: endpoint identifier which is in (0..3) - \param[out] none - \retval status -*/ -static uint32_t usbd_emptytxfifo_write(usb_core_handle_struct *pudev, uint8_t ep_num) -{ - uint32_t len = 0U, word_len = 0U; - usb_ep_struct *ep; - - ep = &pudev->dev.in_ep[ep_num]; - len = ep->xfer_len - ep->xfer_count; - - if (len > ep->endp_mps) { - len = ep->endp_mps; - } - - word_len = (len + 3U) / 4U; - - while (((USB_DIEPxTFSTAT((uint16_t)ep_num) & DIEPTFSTAT_IEPTFS) > word_len) && - (ep->xfer_count < ep->xfer_len)) { - /* write the FIFO */ - len = ep->xfer_len - ep->xfer_count; - - if (len > ep->endp_mps) { - len = ep->endp_mps; - } - - word_len = (len + 3U) / 4U; - - usb_fifo_write (ep->xfer_buff, ep_num, (uint16_t)len); - - ep->xfer_buff += len; - ep->xfer_count += len; - } - - return 1U; -} - -#ifdef VBUS_SENSING_ENABLED - -/*! - \brief indicates that the USB_OTG controller has detected a connection - \param[in] pudev: pointer to usb device instance - \param[out] none - \retval status -*/ -static uint32_t usbd_intf_sessionrequest(usb_core_handle_struct *pudev) -{ - pudev->dev.connection_status = 1U; - - /* clear the interrupt bit */ - USB_GINTF = GINTF_SESIF; - - return 1; -} - -/*! - \brief indicates that the USB_OTG controller has detected an OTG event - \param[in] pudev: pointer to usb device instance - \param[out] none - \retval status -*/ -static uint32_t usbd_intf_otg(usb_core_handle_struct *pudev) -{ - if (USB_GOTGINTF & GOTGINTF_SESEND) { - pudev->dev.class_deinit(pudev, 0); - pudev->dev.connection_status = 0; - } - - /* clear OTG interrupt */ - USB_GOTGINTF |= GOTGINTF_SESEND; - - return 1; -} - -#endif /* VBUS_SENSING_ENABLED */ diff --git a/bsp/gd32450z-eval/Libraries/GD32F4xx_usb_driver/Source/usbd_std.c b/bsp/gd32450z-eval/Libraries/GD32F4xx_usb_driver/Source/usbd_std.c deleted file mode 100644 index 0ae93e4472..0000000000 --- a/bsp/gd32450z-eval/Libraries/GD32F4xx_usb_driver/Source/usbd_std.c +++ /dev/null @@ -1,699 +0,0 @@ -/*! - \file usbd_std.c - \brief USB 2.0 standard handler driver -*/ - -/* - Copyright (C) 2016 GigaDevice - - 2016-08-15, V1.0.0, firmware for GD32F4xx -*/ - -#include "usbd_std.h" -#include "usb_core.h" - -static usbd_status_enum usbd_standard_request (usb_core_handle_struct *pudev, usb_device_req_struct *req); -static usbd_status_enum usbd_device_class_request (usb_core_handle_struct *pudev, usb_device_req_struct *req); -static usbd_status_enum usbd_vendor_request (usb_core_handle_struct *pudev, usb_device_req_struct *req); - -static void usbd_setup_request_parse(usb_core_handle_struct *pudev, usb_device_req_struct *req); - -static void usbd_getdescriptor (usb_core_handle_struct *pudev, usb_device_req_struct *req); -static void usbd_setaddress (usb_core_handle_struct *pudev, usb_device_req_struct *req); -static void usbd_setconfig (usb_core_handle_struct *pudev, usb_device_req_struct *req); -static void usbd_getconfig (usb_core_handle_struct *pudev, usb_device_req_struct *req); -static void usbd_getstatus (usb_core_handle_struct *pudev, usb_device_req_struct *req); -static void usbd_setfeature (usb_core_handle_struct *pudev, usb_device_req_struct *req); -static void usbd_clrfeature (usb_core_handle_struct *pudev, usb_device_req_struct *req); -static void usbd_reserved (usb_core_handle_struct *pudev, usb_device_req_struct *req); -static void usbd_setdescriptor (usb_core_handle_struct *pudev, usb_device_req_struct *req); -static void usbd_getinterface (usb_core_handle_struct *pudev, usb_device_req_struct *req); -static void usbd_setinterface (usb_core_handle_struct *pudev, usb_device_req_struct *req); -static void usbd_synchframe (usb_core_handle_struct *pudev, usb_device_req_struct *req); - -static uint8_t* usbd_device_descriptor_get (usb_core_handle_struct *pudev, uint8_t index, uint16_t *pLen); -static uint8_t* usbd_configuration_descriptor_get (usb_core_handle_struct *pudev, uint8_t index, uint16_t *pLen); -static uint8_t* usbd_string_descriptor_get (usb_core_handle_struct *pudev, uint8_t index, uint16_t *pLen); - -static void (*StandardDeviceRequest[])(usb_core_handle_struct *pudev, usb_device_req_struct *req) = -{ - usbd_getstatus, - usbd_clrfeature, - usbd_reserved, - usbd_setfeature, - usbd_reserved, - usbd_setaddress, - usbd_getdescriptor, - usbd_setdescriptor, - usbd_getconfig, - usbd_setconfig, - usbd_getinterface, - usbd_setinterface, - usbd_synchframe, -}; - -/* get standard descriptor handler */ -static uint8_t* (*standard_descriptor_get[])(usb_core_handle_struct *pudev, uint8_t index, uint16_t *pLen) = -{ - usbd_device_descriptor_get, - usbd_configuration_descriptor_get, - usbd_string_descriptor_get -}; - -/*! - \brief USB setup stage processing - \param[in] pudev: pointer to USB device instance - \param[out] none - \retval USB device operation status -*/ -usbd_status_enum usbd_setup_transaction(usb_core_handle_struct *pudev) -{ - usb_device_req_struct req; - - usbd_setup_request_parse(pudev, &req); - - switch (req.bmRequestType & USB_REQ_MASK) { - /* standard device request */ - case USB_STANDARD_REQ: - usbd_standard_request(pudev, &req); - break; - /* device class request */ - case USB_CLASS_REQ: - usbd_device_class_request(pudev, &req); - break; - /* vendor defined request */ - case USB_VENDOR_REQ: - usbd_vendor_request(pudev, &req); - break; - default: - usbd_ep_stall(pudev, req.bmRequestType & 0x80U); - break; - } - - return USBD_OK; -} - -/*! - \brief data out stage processing - \param[in] pudev: pointer to USB device instance - \param[in] ep_id: endpoint identifier(0..7) - \param[out] none - \retval USB device operation status -*/ -usbd_status_enum usbd_out_transaction (usb_core_handle_struct *pudev, uint8_t endp_num) -{ - usb_ep_struct *ep; - - if (0U == endp_num) { - ep = &pudev->dev.out_ep[0]; - - if (USB_CTRL_DATA_OUT == pudev->dev.ctl_status) { - if (pudev->dev.remain_len > ep->endp_mps) { - pudev->dev.remain_len -= ep->endp_mps; - - if (1U == pudev->cfg.dma_enable) { - /* update buffer location */ - ep->xfer_buff += ep->endp_mps; - } - - usbd_ep_rx (pudev, - 0U, - ep->xfer_buff, - (uint16_t)USB_MIN(pudev->dev.remain_len, ep->endp_mps)); - } else { - if (USB_STATUS_CONFIGURED == pudev->dev.status) { - pudev->dev.class_data_handler(pudev, USBD_RX, 0U); - } - - usbd_ctlstatus_tx(pudev); - } - } - } else if (USB_STATUS_CONFIGURED == pudev->dev.status) { - pudev->dev.class_data_handler(pudev, USBD_RX, endp_num); - } else { - /* no operation */ - } - - return USBD_OK; -} - -/*! - \brief data in stage processing - \param[in] pudev: pointer to USB device instance - \param[in] ep_id: endpoint identifier(0..7) - \param[out] none - \retval USB device operation status -*/ -usbd_status_enum usbd_in_transaction (usb_core_handle_struct *pudev, uint8_t endp_num) -{ - usb_ep_struct *ep; - - if (0U == endp_num) { - ep = &pudev->dev.in_ep[0]; - - if (USB_CTRL_DATA_IN == pudev->dev.ctl_status) { - if (pudev->dev.remain_len > ep->endp_mps) { - pudev->dev.remain_len -= ep->endp_mps; - - if (1U == pudev->cfg.dma_enable) { - /* update buffer location */ - ep->xfer_buff += ep->endp_mps; - } - - usbd_ep_tx (pudev, 0U, ep->xfer_buff, pudev->dev.remain_len); - } else { - /* last packet is MPS multiple, so send ZLP packet */ - if ((pudev->dev.sum_len % ep->endp_mps == 0U) && - (pudev->dev.sum_len >= ep->endp_mps) && - (pudev->dev.sum_len < pudev->dev.ctl_len)) { - usbd_ep_tx (pudev, 0U, NULL, 0U); - pudev->dev.ctl_len = 0U; - } else { - if (USB_STATUS_CONFIGURED == pudev->dev.status) { - pudev->dev.class_data_handler(pudev, USBD_TX, 0U); - } - - usbd_ctlstatus_rx(pudev); - } - } - } - } else if (USB_STATUS_CONFIGURED == pudev->dev.status) { - pudev->dev.class_data_handler(pudev, USBD_TX, endp_num); - } else { - /* no operation */ - } - - return USBD_OK; -} - -/*! - \brief handle USB standard device request - \param[in] pudev: pointer to USB device instance - \param[in] req: pointer to USB device request - \param[out] none - \retval USB device operation status -*/ -static usbd_status_enum usbd_standard_request (usb_core_handle_struct *pudev, usb_device_req_struct *req) -{ - /* call device request handle function */ - (*StandardDeviceRequest[req->bRequest])(pudev, req); - - return USBD_OK; -} - -/*! - \brief handle USB device class request - \param[in] pudev: pointer to USB device instance - \param[in] req: pointer to USB device class request - \param[out] none - \retval USB device operation status -*/ -static usbd_status_enum usbd_device_class_request (usb_core_handle_struct *pudev, usb_device_req_struct *req) -{ - usbd_status_enum ret = USBD_OK; - - switch (pudev->dev.status) { - case USB_STATUS_CONFIGURED: - if (LOWBYTE(req->wIndex) <= USBD_ITF_MAX_NUM) { - ret = (usbd_status_enum)(pudev->dev.class_req_handler(pudev, req)); - - if ((0U == req->wLength) && (USBD_OK == ret)) { - /* no data stage */ - usbd_ctlstatus_tx(pudev); - } - } else { - usbd_enum_error(pudev, req); - } - break; - - default: - usbd_enum_error(pudev, req); - break; - } - - return ret; -} - -/*! - \brief handle USB vendor request - \param[in] pudev: pointer to USB device instance - \param[in] req: pointer to USB vendor request - \param[out] none - \retval USB device operation status -*/ -static usbd_status_enum usbd_vendor_request (usb_core_handle_struct *pudev, usb_device_req_struct *req) -{ - /* added by user... */ - - return USBD_OK; -} - -/*! - \brief no operation, just for reserved - \param[in] pudev: pointer to USB device instance - \param[in] req: pointer to USB device request - \param[out] none - \retval none -*/ -static void usbd_reserved (usb_core_handle_struct *pudev, usb_device_req_struct *req) -{ - /* no operation... */ -} - -/*! - \brief get the device descriptor - \brief[in] index: no use - \param[in] none - \param[out] pLen: data length pointer - \retval descriptor buffer pointer -*/ -static uint8_t* usbd_device_descriptor_get (usb_core_handle_struct *pudev, uint8_t index, uint16_t *pLen) -{ - *pLen = pudev->dev.dev_desc[0]; - - return pudev->dev.dev_desc; -} - -/*! - \brief get the configuration descriptor - \brief[in] index: no use - \param[in] none - \param[out] pLen: data length pointer - \retval descriptor buffer pointer -*/ -static uint8_t* usbd_configuration_descriptor_get (usb_core_handle_struct *pudev, uint8_t index, uint16_t *pLen) -{ - *pLen = pudev->dev.config_desc[2]; - - return pudev->dev.config_desc; -} - -/*! - \brief get string descriptor - \param[in] index: string descriptor index - \param[in] pLen: pointer to string length - \param[out] none - \retval none -*/ -static uint8_t* usbd_string_descriptor_get (usb_core_handle_struct *pudev, uint8_t index, uint16_t *pLen) -{ - uint8_t *desc = pudev->dev.strings[index]; - - *pLen = desc[0]; - - return desc; -} - -/*! - \brief handle Get_Status request - \param[in] pudev: pointer to USB device instance - \param[in] req: pointer to USB device request - \param[out] none - \retval none -*/ -static void usbd_getstatus (usb_core_handle_struct *pudev, usb_device_req_struct *req) -{ -} - -/*! - \brief handle USB Clear_Feature request - \param[in] pudev: pointer to USB device instance - \param[in] req: USB device request - \param[out] none - \retval none -*/ -static void usbd_clrfeature (usb_core_handle_struct *pudev, usb_device_req_struct *req) -{ - uint8_t ep_addr = 0U; - - switch (req->bmRequestType & USB_REQTYPE_MASK) { - case USB_REQTYPE_DEVICE: - switch (pudev->dev.status) { - case USB_STATUS_ADDRESSED: - case USB_STATUS_CONFIGURED: - if (USB_FEATURE_REMOTE_WAKEUP == req->wValue) { - pudev->dev.remote_wakeup = 0U; - pudev->dev.class_req_handler(pudev, req); - - usbd_ctlstatus_tx(pudev); - } - break; - - default: - usbd_enum_error(pudev, req); - break; - } - break; - case USB_REQTYPE_INTERFACE: - switch (pudev->dev.status) { - case USB_STATUS_ADDRESSED: - usbd_enum_error(pudev, req); - break; - case USB_STATUS_CONFIGURED: - if (LOWBYTE(req->wIndex) <= USBD_ITF_MAX_NUM) { - /* no operation */ - } else { - usbd_enum_error(pudev, req); - } - break; - default: - break; - } - break; - case USB_REQTYPE_ENDPOINT: - ep_addr = LOWBYTE(req->wIndex); - - switch (pudev->dev.status) { - case USB_STATUS_ADDRESSED: - if (IS_NOT_EP0(ep_addr)) { - usbd_ep_stall(pudev, ep_addr); - } - break; - case USB_STATUS_CONFIGURED: - if (USB_FEATURE_ENDP_HALT == req->wValue) { - if (IS_NOT_EP0(ep_addr)) { - usbd_ep_clear_stall(pudev, ep_addr); - - pudev->dev.class_req_handler(pudev, req); - } - } - usbd_ctlstatus_tx(pudev); - break; - default: - break; - } - break; - default: - usbd_enum_error(pudev, req); - break; - } -} - -/*! - \brief handle USB Set_Feature request - \param[in] pudev: pointer to USB device instance - \param[in] req: pointer to USB device request - \param[out] none - \retval none -*/ -static void usbd_setfeature (usb_core_handle_struct *pudev, usb_device_req_struct *req) -{ - uint8_t ep_addr = 0U; - __IO uint32_t DctlrStatus; - - switch (req->bmRequestType & USB_REQ_MASK) { - case USB_REQTYPE_DEVICE: - switch (pudev->dev.status) { - case USB_STATUS_ADDRESSED: - case USB_STATUS_CONFIGURED: - if (USB_FEATURE_REMOTE_WAKEUP == req->wValue) { - pudev->dev.remote_wakeup = 1U; - pudev->dev.class_req_handler(pudev, req); - - usbd_ctlstatus_tx(pudev); - } else if ((req->wValue == USB_FEATURE_TEST_MODE) && - (0U == (req->wIndex & 0xFFU))) { - DctlrStatus = USB_DCTL; - - usbd_ctlstatus_tx(pudev); - } else { - /* no operation */ - } - break; - default: - break; - } - break; - case USB_REQTYPE_INTERFACE: - switch (pudev->dev.status) { - case USB_STATUS_ADDRESSED: - usbd_enum_error(pudev, req); - break; - case USB_STATUS_CONFIGURED: - if (LOWBYTE(req->wIndex) <= USBD_ITF_MAX_NUM) { - /* no operation */ - } else { - usbd_enum_error(pudev, req); - } - break; - default: - break; - } - break; - case USB_REQTYPE_ENDPOINT: - switch (pudev->dev.status) { - case USB_STATUS_ADDRESSED: - if (IS_NOT_EP0(ep_addr)) { - usbd_ep_stall(pudev, ep_addr); - } - break; - case USB_STATUS_CONFIGURED: - if (USB_FEATURE_ENDP_HALT == req->wValue) { - if (IS_NOT_EP0(ep_addr)) { - usbd_ep_stall(pudev, ep_addr); - } - } - pudev->dev.class_req_handler(pudev, req); - - usbd_ctlstatus_tx(pudev); - break; - default: - break; - } - break; - default: - usbd_enum_error(pudev, req); - break; - } -} - -/*! - \brief handle USB Set_Address request - \param[in] pudev: pointer to USB device instance - \param[in] req: pointer to USB device request - \param[out] none - \retval none -*/ -static void usbd_setaddress (usb_core_handle_struct *pudev, usb_device_req_struct *req) -{ - uint8_t DevAddr; - - if ((0U == req->wIndex) && (0U == req->wLength)) { - DevAddr = (uint8_t)(req->wValue) & 0x7FU; - - if (USB_STATUS_CONFIGURED == pudev->dev.status) { - usbd_enum_error(pudev, req); - } else { - USB_SET_DEVADDR((uint32_t)DevAddr); - - usbd_ctlstatus_tx(pudev); - - if (0U != DevAddr) { - pudev->dev.status = USB_STATUS_ADDRESSED; - } else { - pudev->dev.status = USB_STATUS_DEFAULT; - } - } - } else { - usbd_enum_error(pudev, req); - } -} - -/*! - \brief handle USB Get_Descriptor request - \param[in] pudev: pointer to USB device instance - \param[in] req: pointer to USB device request - \param[out] none - \retval none -*/ -static void usbd_getdescriptor (usb_core_handle_struct *pudev, usb_device_req_struct *req) -{ - if (USB_REQTYPE_DEVICE == (req->bmRequestType & USB_REQTYPE_MASK)) { - uint8_t desc_index = (uint8_t)(req->wValue >> 8U); - - if (desc_index <= 0x03U) { - uint16_t len; - uint8_t *pbuf; - - /* call corresponding descriptor get function */ - pbuf = standard_descriptor_get[desc_index - 1U](pudev, (uint8_t)(req->wValue) & 0xFFU, &len); - - if ((0U != len) && (0U != req->wLength)) { - len = USB_MIN(len, req->wLength); - - if ((1U == desc_index) && (64U == req->wLength)) { - len = 8U; - } - - usbd_ctltx(pudev, pbuf, len); - } - } else { - usbd_enum_error(pudev, req); - } - } else if (USB_REQTYPE_INTERFACE == (req->bmRequestType & USB_REQTYPE_MASK)) { - pudev->dev.class_req_handler(pudev, req); - } else { - /* no operation */ - } -} - -/*! - \brief handle USB Set_Descriptor request - \param[in] pudev: pointer to USB device instance - \param[in] req: pointer to USB device request - \param[out] none - \retval none -*/ -static void usbd_setdescriptor (usb_core_handle_struct *pudev, usb_device_req_struct *req) -{ - /* no handle... */ -} - -/*! - \brief handle USB Get_Configuration request - \param[in] pudev: pointer to USB device instance - \param[in] req: pointer to USB device request - \param[out] none - \retval none -*/ -static void usbd_getconfig (usb_core_handle_struct *pudev, usb_device_req_struct *req) -{ - uint32_t USBD_default_config = 0U; - - if (1U != req->wLength) { - usbd_enum_error(pudev, req); - } else { - switch (pudev->dev.status) { - case USB_STATUS_ADDRESSED: - usbd_ctltx(pudev, (uint8_t *)&USBD_default_config, 1U); - break; - case USB_STATUS_CONFIGURED: - usbd_ctltx(pudev, &pudev->dev.config_num, 1U); - break; - default: - usbd_enum_error(pudev, req); - break; - } - } -} - -/*! - \brief handle USB Set_Configuration request - \param[in] pudev: pointer to USB device instance - \param[in] req: pointer to USB device request - \param[out] none - \retval none -*/ -static void usbd_setconfig (usb_core_handle_struct *pudev, usb_device_req_struct *req) -{ - static uint8_t cfgidx; - - cfgidx = (uint8_t)(req->wValue); - - if (cfgidx > USBD_CFG_MAX_NUM) { - usbd_enum_error(pudev, req); - } else { - switch (pudev->dev.status) { - case USB_STATUS_ADDRESSED: - if (cfgidx) { - pudev->dev.config_num = cfgidx; - pudev->dev.status = USB_STATUS_CONFIGURED; - pudev->dev.class_init(pudev, cfgidx); - } - - usbd_ctlstatus_tx(pudev); - break; - case USB_STATUS_CONFIGURED: - if (0U == cfgidx) { - pudev->dev.status = USB_STATUS_ADDRESSED; - pudev->dev.config_num = cfgidx; - pudev->dev.class_deinit(pudev, cfgidx); - } else if (cfgidx != pudev->dev.config_num) { - /* clear old configuration */ - pudev->dev.class_deinit(pudev, pudev->dev.config_num); - - /* set new configuration */ - pudev->dev.config_num = cfgidx; - pudev->dev.class_init(pudev, cfgidx); - } else { - /* no operation */ - } - - usbd_ctlstatus_tx(pudev); - break; - default: - usbd_enum_error(pudev, req); - break; - } - } -} - -/*! - \brief handle USB Get_Interface request - \param[in] pudev: pointer to USB device instance - \param[in] req: pointer to USB device request - \param[out] none - \retval none -*/ -static void usbd_getinterface (usb_core_handle_struct *pudev, usb_device_req_struct *req) -{ - pudev->dev.class_req_handler(pudev, req); -} - -/*! - \brief handle USB Set_Interface request - \param[in] pudev: pointer to USB device instance - \param[in] req: pointer to USB device request - \param[out] none - \retval none -*/ -static void usbd_setinterface (usb_core_handle_struct *pudev, usb_device_req_struct *req) -{ - pudev->dev.class_req_handler(pudev, req); -} - -/*! - \brief handle USB SynchFrame request - \param[in] pudev: pointer to USB device instance - \param[in] req: pointer to USB device request - \param[out] none - \retval none -*/ -static void usbd_synchframe (usb_core_handle_struct *pudev, usb_device_req_struct *req) -{ - /* no handle... */ -} - -/*! - \brief decode setup data packet - \param[in] pudev: pointer to USB device instance - \param[in] req: pointer to USB device request - \param[out] none - \retval none -*/ -static void usbd_setup_request_parse(usb_core_handle_struct *pudev, usb_device_req_struct *req) -{ - uint8_t *psetup = pudev->dev.setup_packet; - - req->bmRequestType = *psetup; - req->bRequest = *(uint8_t *)(psetup + 1U); - req->wValue = SWAPBYTE (psetup + 2U); - req->wIndex = SWAPBYTE (psetup + 4U); - req->wLength = SWAPBYTE (psetup + 6U); - - pudev->dev.ctl_len = req->wLength; -} - -/*! - \brief handle USB low level error event - \param[in] pudev: pointer to USB device instance - \param[in] req: pointer to USB device request - \param[out] none - \retval none -*/ -void usbd_enum_error(usb_core_handle_struct *pudev, usb_device_req_struct *req) -{ - usbd_ep_stall(pudev, 0x80U); - usbd_ep_stall(pudev, 0x00U); - usb_ep0_startout(pudev); -} diff --git a/bsp/gd32450z-eval/Libraries/GD32F4xx_usb_driver/Source/usbh_core.c b/bsp/gd32450z-eval/Libraries/GD32F4xx_usb_driver/Source/usbh_core.c deleted file mode 100644 index 1c90b55187..0000000000 --- a/bsp/gd32450z-eval/Libraries/GD32F4xx_usb_driver/Source/usbh_core.c +++ /dev/null @@ -1,710 +0,0 @@ -/*! - \file usbh_core.c - \brief this file implements the functions for the core state machine process -*/ - -/* - Copyright (C) 2016 GigaDevice - - 2016-08-15, V1.0.0, firmware for GD32F4xx -*/ - -#include "usbh_hcs.h" -#include "usbh_core.h" -#include "usbh_int.h" -#include "stdio.h" -#include "usbh_std.h" -#include "usbh_ctrl.h" -#include "usb_core.h" - -extern class_polling_fun_cb_struct class_polling_cb; - -uint8_t usbh_sof (usb_core_handle_struct *pudev); -uint8_t usbh_connected (usb_core_handle_struct *pudev); -uint8_t usbh_disconnected (usb_core_handle_struct *pudev); - -usbh_hcd_int_cb_struct usbh_hcd_int_cb = -{ - usbh_sof, - usbh_connected, - usbh_disconnected, -}; - -usbh_hcd_int_cb_struct *usbh_hcd_int_fops = &usbh_hcd_int_cb; -extern usbh_state_handle_struct usbh_state_core; - -static void host_idle_handle (usb_core_handle_struct *pudev, usbh_host_struct *puhost, usbh_state_handle_struct *pustate); -static void host_dev_attached_handle (usb_core_handle_struct *pudev, usbh_host_struct *puhost, usbh_state_handle_struct *pustate); -static void host_dev_detached_handle (usb_core_handle_struct *pudev, usbh_host_struct *puhost, usbh_state_handle_struct *pustate); -static void host_detect_dev_speed_handle (usb_core_handle_struct *pudev, usbh_host_struct *puhost, usbh_state_handle_struct *pustate); -static void host_enum_handle (usb_core_handle_struct *pudev, usbh_host_struct *puhost, usbh_state_handle_struct *pustate); -static void host_class_request_handle (usb_core_handle_struct *pudev, usbh_host_struct *puhost, usbh_state_handle_struct *pustate); -static void host_class_handle (usb_core_handle_struct *pudev, usbh_host_struct *puhost, usbh_state_handle_struct *pustate); -static void host_user_input_handle (usb_core_handle_struct *pudev, usbh_host_struct *puhost, usbh_state_handle_struct *pustate); -static void host_suspended_handle (usb_core_handle_struct *pudev, usbh_host_struct *puhost, usbh_state_handle_struct *pustate); -static void host_error_handle (usb_core_handle_struct *pudev, usbh_host_struct *puhost, usbh_state_handle_struct *pustate); - -static usbh_status_enum class_req_state_polling_fun (usb_core_handle_struct *pudev, usbh_host_struct *puhost, void *pustate); -static usbh_status_enum class_state_polling_fun (usb_core_handle_struct *pudev, usbh_host_struct *puhost, void *pustate); - -/* the host state handle function array */ -void (*host_state_handle[]) (usb_core_handle_struct *pudev, usbh_host_struct *puhost, usbh_state_handle_struct *pustate) = -{ - host_idle_handle, - host_dev_attached_handle, - host_dev_detached_handle, - host_detect_dev_speed_handle, - host_enum_handle, - host_class_request_handle, - host_class_handle, - host_user_input_handle, - host_suspended_handle, - host_error_handle, -}; - -/* the host state handle table */ -state_table_struct host_handle_table[HOST_HANDLE_TABLE_SIZE] = -{ - /* the current state the current event the next state the event function */ - {HOST_IDLE, HOST_EVENT_ATTACHED, HOST_DEV_ATTACHED, only_state_move }, - {HOST_DEV_ATTACHED, HOST_EVENT_ENUM, HOST_ENUMERATION, only_state_move }, - {HOST_ENUMERATION, HOST_EVENT_USER_INPUT, HOST_USER_INPUT, only_state_move }, - {HOST_USER_INPUT, HOST_EVENT_CLASS_REQ, HOST_CLASS_REQUEST, only_state_move }, - {HOST_CLASS_REQUEST, HOST_EVENT_CLASS, HOST_CLASS, only_state_move }, - {HOST_CLASS, HOST_EVENT_ERROR, HOST_ERROR, only_state_move }, - {HOST_ERROR, HOST_EVENT_IDLE, HOST_IDLE, only_state_move }, - {HOST_DEV_DETACHED, HOST_EVENT_IDLE, HOST_IDLE, only_state_move }, - {HOST_CLASS_REQUEST, HOST_EVENT_ERROR, HOST_ERROR, only_state_move }, -}; - -/*! - \brief the polling function of HOST state - \param[in] pudev: pointer to usb device - \param[in] puhost: pointer to usb host - \param[in] pustate: pointer to usb state driver - \param[out] none - \retval none -*/ -usbh_status_enum host_state_polling_fun (usb_core_handle_struct *pudev, - usbh_host_struct *puhost, - void *pustate) -{ - usbh_state_handle_struct *p_state = (usbh_state_handle_struct *)pustate; - - scd_begin(p_state, HOST_FSM_ID); - - if (-1 == p_state->usbh_current_state_stack_top) { - uint8_t cur_state = p_state->usbh_current_state; - - if ((0U == hcd_is_device_connected(pudev)) && (HOST_IDLE != cur_state)) { - if (HOST_DEV_DETACHED != cur_state) { - p_state->usbh_current_state = HOST_DEV_DETACHED; - cur_state = HOST_DEV_DETACHED; - } - } - - host_state_handle[cur_state](pudev, puhost, p_state); - } else { - uint8_t stack0_state = p_state->stack[0].state; - - if ((0U == hcd_is_device_connected(pudev)) && (HOST_IDLE != stack0_state)) { - if (HOST_DEV_DETACHED != stack0_state) { - p_state->stack[0].state = HOST_DEV_DETACHED; - stack0_state = HOST_DEV_DETACHED; - p_state->usbh_current_state = HOST_DEV_DETACHED; - } - } - - host_state_handle[stack0_state](pudev, puhost, p_state); - } - - return USBH_OK; -} - -/*! - \brief the handle function of HOST_IDLE state - \param[in] pudev: pointer to usb device - \param[in] puhost: pointer to usb host - \param[in] pustate: pointer to usb state driver - \param[out] none - \retval none -*/ -static void host_idle_handle (usb_core_handle_struct *pudev, - usbh_host_struct *puhost, - usbh_state_handle_struct *pustate) -{ - if (hcd_is_device_connected(pudev)) { - scd_event_handle(pudev, puhost, pustate, HOST_EVENT_ATTACHED, pustate->usbh_current_state); - - if ((void *)0 != pudev->mdelay) { - pudev->mdelay(100U); - } - } -} - -/*! - \brief the handle function of HOST_DEV_ATTACHED state - \param[in] pudev: pointer to usb device - \param[in] puhost: pointer to usb host - \param[in] pustate: pointer to usb state driver - \param[out] none - \retval none -*/ -static void host_dev_attached_handle (usb_core_handle_struct *pudev, - usbh_host_struct *puhost, - usbh_state_handle_struct *pustate) -{ - puhost->usr_cb->device_connected(); - puhost->control.hc_out_num = usbh_channel_alloc(pudev, 0x00U); - puhost->control.hc_in_num = usbh_channel_alloc(pudev, 0x80U); - - /* reset usb device */ - if (0U == usb_port_reset(pudev)) { - puhost->usr_cb->device_reset(); - - /* wait for USB USBH_ISR_PrtEnDisableChange() - * host is now ready to start the enumeration - */ - puhost->device.speed = (uint8_t)USB_CURRENT_SPEED_GET(); - puhost->usr_cb->device_speed_detected(puhost->device.speed); - - /* open IN control pipes */ - usbh_channel_open (pudev, - puhost->control.hc_in_num, - puhost->device.address, - puhost->device.speed, - USB_EPTYPE_CTRL, - (uint16_t)puhost->control.ep0_size); - - /* open OUT control pipes */ - usbh_channel_open (pudev, - puhost->control.hc_out_num, - puhost->device.address, - puhost->device.speed, - USB_EPTYPE_CTRL, - (uint16_t)puhost->control.ep0_size); - - scd_event_handle(pudev, puhost, pustate, HOST_EVENT_ENUM, pustate->usbh_current_state); - } -} - -/*! - \brief the handle function of HOST_ENUMERATION state - \param[in] pudev: pointer to usb device - \param[in] puhost: pointer to usb host - \param[in] pustate: pointer to usb state driver - \param[out] none - \retval none -*/ -static void host_enum_handle (usb_core_handle_struct *pudev, - usbh_host_struct *puhost, - usbh_state_handle_struct *pustate) -{ - if (USBH_OK == enum_state_polling_fun(pudev, puhost, pustate)) { - puhost->usr_cb->enumeration_finish(); - scd_event_handle(pudev, - puhost, - pustate, - HOST_EVENT_USER_INPUT, - pustate->usbh_current_state); - } -} - -/*! - \brief the handle function of HOST_USER_INPUT state - \param[in] pudev: pointer to usb device - \param[in] puhost: pointer to usb host - \param[in] pustate: pointer to usb state driver - \param[out] none - \retval none -*/ -static void host_user_input_handle (usb_core_handle_struct *pudev, - usbh_host_struct *puhost, - usbh_state_handle_struct *pustate) -{ - if (USBH_USER_RESP_OK == puhost->usr_cb->user_input()) { - if (USBH_OK == (puhost->class_init(pudev, puhost))) { - scd_event_handle(pudev, - puhost, - pustate, - HOST_EVENT_CLASS_REQ, - pustate->usbh_current_state); - } - } -} - -/*! - \brief the handle function of HOST_CLASS_REQUEST state - \param[in] pudev: pointer to usb device - \param[in] puhost: pointer to usb host - \param[in] pustate: pointer to usb state driver - \param[out] none - \retval none -*/ -static void host_class_request_handle (usb_core_handle_struct *pudev, - usbh_host_struct *puhost, - usbh_state_handle_struct *pustate) -{ - if (USBH_OK == class_req_state_polling_fun(pudev, puhost, pustate)) { - scd_event_handle(pudev, puhost, pustate, HOST_EVENT_CLASS, pustate->usbh_current_state); - } -} - -/*! - \brief the handle function of HOST_CLASS state - \param[in] pudev: pointer to usb device - \param[in] puhost: pointer to usb host - \param[in] pustate: pointer to usb state driver - \param[out] none - \retval none -*/ -static void host_class_handle (usb_core_handle_struct *pudev, - usbh_host_struct *puhost, - usbh_state_handle_struct *pustate) -{ - class_state_polling_fun(pudev, puhost, pustate); -} - -/*! - \brief the handle function of HOST_SUSPENDED state - \param[in] pudev: pointer to usb device - \param[in] puhost: pointer to usb host - \param[in] pustate: pointer to usb state driver - \param[out] none - \retval none -*/ -static void host_suspended_handle (usb_core_handle_struct *pudev, - usbh_host_struct *puhost, - usbh_state_handle_struct *pustate) -{ - /* no operation */ -} - -/*! - \brief the handle function of HOST_ERROR state - \param[in] pudev: pointer to usb device - \param[in] puhost: pointer to usb host - \param[in] pustate: pointer to usb state driver - \param[out] none - \retval none -*/ -static void host_error_handle (usb_core_handle_struct *pudev, - usbh_host_struct *puhost, - usbh_state_handle_struct *pustate) -{ - /* re-initilaize host for new enumeration */ - usbh_deinit (pudev, puhost,&usbh_state_core); - puhost->usr_cb->deinit(); - puhost->class_deinit(pudev, &puhost->device); - scd_event_handle(pudev, puhost, pustate, HOST_EVENT_IDLE, pustate->usbh_current_state); -} - -/*! - \brief the handle function of HOST_DEV_DETACHED state - \param[in] pudev: pointer to usb device - \param[in] puhost: pointer to usb host - \param[in] pustate: pointer to usb state driver - \param[out] none - \retval none -*/ -static void host_dev_detached_handle (usb_core_handle_struct *pudev, - usbh_host_struct *puhost, - usbh_state_handle_struct *pustate) -{ - /* manage user disconnect operations*/ - puhost->usr_cb->device_disconnected(); - - /* re-initilaize host for new enumeration */ - usbh_deinit(pudev, puhost,&usbh_state_core); - puhost->usr_cb->deinit(); - puhost->class_deinit(pudev, &puhost->device); - usbh_allchannel_dealloc(pudev); - scd_event_handle(pudev, puhost, pustate, HOST_EVENT_IDLE, pustate->usbh_current_state); -} - -/*! - \brief the handle function of HOST_DETECT_DEV_SPEED state - \param[in] pudev: pointer to usb device - \param[in] puhost: pointer to usb host - \param[in] pustate: pointer to usb state driver - \param[out] none - \retval none -*/ -static void host_detect_dev_speed_handle (usb_core_handle_struct *pudev, - usbh_host_struct *puhost, - usbh_state_handle_struct *pustate) -{ - /* no operation */ -} - -/*! - \brief usb connect callback function from the interrupt. - \param[in] pudev: pointer to usb device - \param[out] none - \retval operation status -*/ -uint8_t usbh_connected (usb_core_handle_struct *pudev) -{ - pudev->host.connect_status = 1U; - - return 0U; -} - -/*! - \brief usb disconnect callback function from the interrupt. - \param[in] pudev: pointer to usb device - \param[out] none - \retval operation status -*/ -uint8_t usbh_disconnected (usb_core_handle_struct *pudev) -{ - pudev->host.connect_status = 0U; - - return 0U; -} - -/*! - \brief usb sof callback function from the interrupt. - \param[in] pudev: pointer to usb device - \param[out] none - \retval operation status -*/ -uint8_t usbh_sof (usb_core_handle_struct *pudev) -{ - /* this callback could be used to implement a scheduler process */ - return 0U; -} - -/*! - \brief initialize the host portion of the driver. - \param[in] pudev: pointer to usb device - \param[in] core_id: usb otg core identifier(high-speed or full-speed) - \param[out] none - \retval operation status -*/ -uint32_t hcd_init(usb_core_handle_struct *pudev, usb_core_id_enum core_id) -{ - pudev->host.connect_status = 0U; - - pudev->host.host_channel[0].endp_mps = 8U; - - usb_core_select(pudev, core_id); - -#ifndef DUAL_ROLE_MODE_ENABLED - - USB_GLOBAL_INT_DISABLE(); - - usb_core_init(pudev); - - /* force host mode*/ - usb_mode_set(pudev, HOST_MODE); - - usb_hostcore_init(pudev); - - USB_GLOBAL_INT_ENABLE(); - -#endif - - return 0U; -} - -/*! - \brief check if the device is connected. - \param[in] pudev: pointer to usb device - \param[out] none - \retval device connection status. 1 -> connected and 0 -> disconnected -*/ -uint32_t hcd_is_device_connected(usb_core_handle_struct *pudev) -{ - return (uint32_t)(pudev->host.connect_status); -} - -/*! - \brief this function returns the last URBstate - \param[in] pudev: pointer to usb device - \param[in] channel_num: host channel number which is in (0..7) - \param[out] none - \retval urb_state_enum -*/ -urb_state_enum hcd_urb_state_get (usb_core_handle_struct *pudev, uint8_t channel_num) -{ - return pudev->host.host_channel[channel_num].urb_state; -} - -/*! - \brief this function returns the last URBstate - \param[in] pudev: pointer to usb device - \param[in] channel_num: host channel number which is in (0..7) - \param[out] none - \retval No. of data bytes transferred -*/ -uint32_t hcd_xfer_count_get (usb_core_handle_struct *pudev, uint8_t channel_num) -{ - return pudev->host.host_channel[channel_num].xfer_count; -} - -/*! - \brief de-initialize host - \param[in] pudev: pointer to usb device - \param[in] puhost: pointer to usb host - \param[out] none - \retval host status -*/ -usbh_status_enum usbh_deinit(usb_core_handle_struct *pudev, - usbh_host_struct *puhost, - usbh_state_handle_struct* pustate) -{ - /* software init */ - - puhost->control.ep0_size = USB_MAX_EP0_SIZE; - - puhost->device.address = USBH_DEVICE_ADDRESS_DEFAULT; - puhost->device.speed = HPRT_PRTSPD_FULL_SPEED; - - usbh_channel_free(pudev, puhost->control.hc_in_num); - usbh_channel_free(pudev, puhost->control.hc_out_num); - - scd_init(pustate); - scd_table_regist(pustate, host_handle_table, HOST_FSM_ID, HOST_HANDLE_TABLE_SIZE); - scd_table_regist(pustate, enum_handle_table, ENUM_FSM_ID, ENUM_HANDLE_TABLE_SIZE); - scd_table_regist(pustate, ctrl_handle_table, CTRL_FSM_ID, CTRL_HANDLE_TABLE_SIZE); - - scd_begin(pustate,HOST_FSM_ID); - scd_state_move(pustate, HOST_IDLE); - - return USBH_OK; -} - -/*! - \brief state core driver init - \param[in] pustate: pointer to usb state driver - \param[out] none - \retval none -*/ -void scd_init(usbh_state_handle_struct* pustate) -{ - /* init the state core */ - pustate->usbh_current_state = 0U; - pustate->usbh_current_state_table = NULL; - pustate->usbh_current_state_table_size = 0U; - - pustate->usbh_current_state_stack_top = -1; - pustate->stack->state = 0U; - pustate->stack->table_size = 0U; - pustate->stack->table = NULL; - - pustate->usbh_regist_state_table_num = 0U; - pustate->usbh_regist_state_table->table = NULL; - pustate->usbh_regist_state_table->table_size = 0U; - pustate->usbh_regist_state_table->id = 0U; - - /* init the control and the enumeration polling handle flag */ - ctrl_polling_handle_flag = 0U; - enum_polling_handle_flag = 0U; -} - -/*! - \brief state core driver table regist - \param[in] pustate: pointer to usb state driver - \param[in] pstate_table: pointer to the table to regist - \param[in] table_id: the id of the table to regist - \param[in] current_table_size: the size of the current table to regist - \param[out] none - \retval none -*/ -void scd_table_regist (usbh_state_handle_struct* pustate, - state_table_struct* pstate_table, - uint8_t table_id, - uint8_t current_table_size) -{ - usbh_state_regist_table_struct *cur_state_reg_table; - - cur_state_reg_table = &pustate->usbh_regist_state_table[pustate->usbh_regist_state_table_num]; - - cur_state_reg_table->id = table_id; - cur_state_reg_table->table = pstate_table; - cur_state_reg_table->table_size = current_table_size; - - pustate->usbh_regist_state_table_num++; -} - -/*! - \brief state core driver begin - \param[in] pustate: pointer to usb state driver - \param[in] table_id: the id of the table to begin - \param[out] none - \retval none -*/ -void scd_begin(usbh_state_handle_struct* pustate, uint8_t table_id) -{ - uint8_t i = 0, table_num = pustate->usbh_regist_state_table_num; - usbh_state_regist_table_struct *cur_state_reg_table; - - for (i = 0; i < table_num; i++) { - cur_state_reg_table = &pustate->usbh_regist_state_table[i]; - - if (table_id == cur_state_reg_table->id) { - pustate->usbh_current_state_table = cur_state_reg_table->table; - pustate->usbh_current_state_table_size = cur_state_reg_table->table_size; - break; - } - } -} - -/*! - \brief state core driver move state - \param[in] pustate: pointer to usb state driver - \param[in] state: the state to move - \param[out] none - \retval none -*/ -void scd_state_move(usbh_state_handle_struct* pustate, uint8_t state) -{ - pustate->usbh_current_state = state; -} - -/*! - \brief state core driver event handle - \param[in] pudev: pointer to usb device - \param[in] puhost: pointer to usb host - \param[in] pustate: pointer to usb state driver - \param[in] event: the current event - \param[in] state: the current state - \param[out] none - \retval host status -*/ -usbh_status_enum scd_event_handle (usb_core_handle_struct *pudev, - usbh_host_struct *puhost, - usbh_state_handle_struct* pustate, - uint8_t event, - uint8_t state) -{ - uint8_t i = 0; - ACT_FUN event_act_fun = NULL; - state_table_struct *backup_state_t = pustate->usbh_current_state_table; - state_table_struct *executive_state_table = pustate->usbh_current_state_table; - - /* look up the table to find the action function */ - for (i = 0; i < pustate->usbh_current_state_table_size; i++) { - if (state == executive_state_table->cur_state) { - if (event == executive_state_table->cur_event) { - state = executive_state_table->next_state; - event_act_fun = executive_state_table->event_action_fun; - break; - } else { - executive_state_table++; - } - } else { - executive_state_table++; - } - } - - pustate->usbh_current_state_table = backup_state_t; - - /* if the action function is not NULL, execute the action function */ - if (event_act_fun) { - if (event_act_fun == &only_state_move) { - pustate->usbh_current_state = state; - } else { - return event_act_fun(pudev, puhost, pustate); - } - } - - return USBH_BUSY; -} - -/*! - \brief state core driver table push - \param[in] pustate: pointer to usb state driver - \param[out] none - \retval none -*/ -void scd_table_push(usbh_state_handle_struct* pustate) -{ - usbh_state_stack_struct *top_state_element; - - if (pustate->usbh_current_state_stack_top < MAX_USBH_STATE_STACK_DEEP) { - pustate->usbh_current_state_stack_top++; - - top_state_element = &pustate->stack[pustate->usbh_current_state_stack_top]; - - /* put the current state table into the state stack */ - top_state_element->state = pustate->usbh_current_state; - top_state_element->table = pustate->usbh_current_state_table; - top_state_element->table_size = pustate->usbh_current_state_table_size; - } -} - -/*! - \brief state core driver table pop - \param[in] pustate: pointer to usb state driver - \param[out] none - \retval none -*/ -void scd_table_pop (usbh_state_handle_struct* pustate) -{ - usbh_state_stack_struct *top_state_element; - - top_state_element = &pustate->stack[pustate->usbh_current_state_stack_top]; - - if (pustate->usbh_current_state_stack_top > -1) { - /* get the current state table from the state stack */ - pustate->usbh_current_state = top_state_element->state; - pustate->usbh_current_state_table = top_state_element->table; - pustate->usbh_current_state_table_size = top_state_element->table_size; - pustate->usbh_current_state_stack_top--; - } -} -/*! - \brief the polling function of class req state - \param[in] pudev: pointer to usb device - \param[in] puhost: pointer to usb host - \param[in] pustate: pointer to usb state driver - \param[out] none - \retval host status -*/ -static usbh_status_enum class_req_state_polling_fun (usb_core_handle_struct *pudev, usbh_host_struct *puhost, void *pustate) -{ - return class_polling_cb.class_req_polling(pudev, puhost, pustate); -} - -/*! - \brief the polling function of class state - \param[in] pudev: pointer to usb device - \param[in] puhost: pointer to usb host - \param[in] pustate: pointer to usb state driver - \param[out] none - \retval host status -*/ -static usbh_status_enum class_state_polling_fun (usb_core_handle_struct *pudev, usbh_host_struct *puhost, void *pustate) -{ - return class_polling_cb.class_polling(pudev, puhost, pustate); -} - -/*! - \brief the function is only used to state move - \param[in] pudev: pointer to usb device - \param[in] puhost: pointer to usb host - \param[in] pustate: pointer to usb state driver - \param[out] none - \retval none -*/ -usbh_status_enum only_state_move (usb_core_handle_struct *pudev, usbh_host_struct *puhost, void *pustate) -{ - return USBH_OK; -} - -/*! - \brief the function to the up state - \param[in] pudev: pointer to usb device - \param[in] puhost: pointer to usb host - \param[in] pustate: pointer to usb state driver - \param[out] none - \retval none -*/ -usbh_status_enum goto_up_state_fun (usb_core_handle_struct *pudev, usbh_host_struct *puhost, void *pustate) -{ - scd_table_pop((usbh_state_handle_struct *)pustate); - - return USBH_OK; -} diff --git a/bsp/gd32450z-eval/Libraries/GD32F4xx_usb_driver/Source/usbh_ctrl.c b/bsp/gd32450z-eval/Libraries/GD32F4xx_usb_driver/Source/usbh_ctrl.c deleted file mode 100644 index b61484053e..0000000000 --- a/bsp/gd32450z-eval/Libraries/GD32F4xx_usb_driver/Source/usbh_ctrl.c +++ /dev/null @@ -1,620 +0,0 @@ -/*! - \file usbh_ctrl.c - \brief this file implements the functions for the control transmit process -*/ - -/* - Copyright (C) 2016 GigaDevice - - 2016-08-15, V1.0.0, firmware for GD32F4xx -*/ -#include "usbh_core.h" -#include "usbh_std.h" -#include "usbh_ctrl.h" - -uint8_t ctrl_polling_handle_flag = 0U; -uint8_t ctrl_setup_wait_flag = 0U; -uint8_t ctrl_data_wait_flag = 0U; -uint8_t ctrl_status_wait_flag = 0U; - -static uint16_t timeout = 0U; - -static void ctrl_idle_handle (usb_core_handle_struct *pudev, usbh_host_struct *puhost, usbh_state_handle_struct *pustate); -static void ctrl_setup_handle (usb_core_handle_struct *pudev, usbh_host_struct *puhost, usbh_state_handle_struct *pustate); -static void ctrl_data_handle (usb_core_handle_struct *pudev, usbh_host_struct *puhost, usbh_state_handle_struct *pustate); -static void ctrl_status_handle (usb_core_handle_struct *pudev, usbh_host_struct *puhost, usbh_state_handle_struct *pustate); -static void ctrl_error_handle (usb_core_handle_struct *pudev, usbh_host_struct *puhost, usbh_state_handle_struct *pustate); -static void ctrl_stalled_handle (usb_core_handle_struct *pudev, usbh_host_struct *puhost, usbh_state_handle_struct *pustate); -static void ctrl_complete_handle (usb_core_handle_struct *pudev, usbh_host_struct *puhost, usbh_state_handle_struct *pustate); - -/* the ctrl state handle function array */ -void (*ctrl_state_handle[]) (usb_core_handle_struct *pudev, - usbh_host_struct *puhost, - usbh_state_handle_struct *pustate) = -{ - ctrl_idle_handle, - ctrl_setup_handle, - ctrl_data_handle, - ctrl_status_handle, - ctrl_error_handle, - ctrl_stalled_handle, - ctrl_complete_handle, -}; - -/* the ctrl state handle table */ -state_table_struct ctrl_handle_table[CTRL_HANDLE_TABLE_SIZE] = -{ - /* the current state the current event the next state the event function */ - {CTRL_IDLE, CTRL_EVENT_SETUP, CTRL_SETUP, only_state_move }, - {CTRL_SETUP, CTRL_EVENT_DATA, CTRL_DATA, only_state_move }, - {CTRL_SETUP, CTRL_EVENT_STATUS, CTRL_STATUS, only_state_move }, - {CTRL_SETUP, CTRL_EVENT_ERROR, CTRL_ERROR, only_state_move }, - {CTRL_DATA, CTRL_EVENT_STATUS, CTRL_STATUS, only_state_move }, - {CTRL_DATA, CTRL_EVENT_ERROR, CTRL_ERROR, only_state_move }, - {CTRL_DATA, CTRL_EVENT_STALLED, CTRL_STALLED, only_state_move }, - {CTRL_STATUS, CTRL_EVENT_COMPLETE, CTRL_COMPLETE, only_state_move }, - {CTRL_STATUS, CTRL_EVENT_ERROR, CTRL_ERROR, only_state_move }, - {CTRL_STATUS, CTRL_EVENT_STALLED, CTRL_STALLED, only_state_move }, - {CTRL_ERROR, GO_TO_UP_STATE_EVENT, UP_STATE, goto_up_state_fun }, - {CTRL_STALLED, GO_TO_UP_STATE_EVENT, UP_STATE, goto_up_state_fun }, - {CTRL_COMPLETE, GO_TO_UP_STATE_EVENT, UP_STATE, goto_up_state_fun }, -}; - -/*! - \brief the polling function of CTRL state - \param[in] pudev: pointer to usb device - \param[in] puhost: pointer to usb host - \param[in] pustate: pointer to usb state driver - \param[out] none - \retval none -*/ -usbh_status_enum ctrl_state_polling_fun (usb_core_handle_struct *pudev, - usbh_host_struct *puhost, - void *pustate) -{ - usbh_status_enum exe_state = USBH_BUSY; - usbh_state_handle_struct *p_state; - - p_state = (usbh_state_handle_struct *)pustate; - - /* if first enter this function, begin the ctrl state */ - if (0U == ctrl_polling_handle_flag) { - ctrl_polling_handle_flag = 1U; - scd_table_push(p_state); - scd_state_move(p_state, CTRL_IDLE); - } - - /* base on the current state to handle the ctrl state */ - scd_begin(p_state, CTRL_FSM_ID); - ctrl_state_handle[p_state->usbh_current_state](pudev, puhost, p_state); - - /* determine the control transfer whether to complete */ - switch (puhost->usbh_backup_state.ctrl_backup_state) { - case CTRL_COMPLETE: - ctrl_polling_handle_flag = 0U; - puhost->usbh_backup_state.ctrl_backup_state = CTRL_IDLE; - exe_state = USBH_OK; - break; - case CTRL_STALLED: - ctrl_polling_handle_flag = 0U; - puhost->usbh_backup_state.ctrl_backup_state = CTRL_IDLE; - exe_state = USBH_NOT_SUPPORTED; - break; - case CTRL_ERROR: - ctrl_polling_handle_flag = 0U; - puhost->usbh_backup_state.ctrl_backup_state = CTRL_IDLE; - exe_state = USBH_FAIL; - break; - default: - exe_state = USBH_BUSY; - break; - } - - return exe_state; -} - -/*! - \brief the handle function of CTRL_IDLE state - \param[in] pudev: pointer to usb device - \param[in] puhost: pointer to usb host - \param[in] pustate: pointer to usb state driver - \param[out] none - \retval none -*/ -static void ctrl_idle_handle (usb_core_handle_struct *pudev, - usbh_host_struct *puhost, - usbh_state_handle_struct *pustate) -{ - puhost->usbh_backup_state.ctrl_backup_state = CTRL_IDLE; - scd_event_handle(pudev, puhost, pustate, CTRL_EVENT_SETUP, pustate->usbh_current_state); -} - -/*! - \brief the handle function of CTRL_SETUP state - \param[in] pudev: pointer to usb device - \param[in] puhost: pointer to usb host - \param[in] pustate: pointer to usb state driver - \param[out] none - \retval none -*/ -static void ctrl_setup_handle (usb_core_handle_struct *pudev, - usbh_host_struct *puhost, - usbh_state_handle_struct *pustate) -{ - urb_state_enum urb_status = URB_IDLE; - puhost->usbh_backup_state.ctrl_backup_state = CTRL_SETUP; - - if (0U == ctrl_setup_wait_flag) { - ctrl_setup_wait_flag = 1U; - - /* send a setup packet */ - usbh_ctltx_setup (pudev, - puhost->control.setup.data, - puhost->control.hc_out_num); - } else { - urb_status = hcd_urb_state_get(pudev, puhost->control.hc_out_num); - - /* case setup packet sent successfully */ - if (URB_DONE == urb_status) { - /* check if there is a data stage */ - if (0U != puhost->control.setup.b.wLength) { - ctrl_setup_wait_flag = 0U; - timeout = DATA_STAGE_TIMEOUT; - scd_event_handle(pudev, puhost, pustate, CTRL_EVENT_DATA, pustate->usbh_current_state); - /* no data stage */ - } else { - timeout = NODATA_STAGE_TIMEOUT; - ctrl_setup_wait_flag = 0U; - scd_event_handle(pudev, - puhost, - pustate, - CTRL_EVENT_STATUS, - pustate->usbh_current_state); - } - - /* set the delay timer to enable timeout for data stage completion */ - puhost->control.timer = (uint16_t)USB_CURRENT_FRAME_GET(); - } else if (URB_ERROR == urb_status) { - ctrl_setup_wait_flag = 0U; - scd_event_handle(pudev, puhost, pustate, CTRL_EVENT_ERROR, pustate->usbh_current_state); - } else { - /* no operation */ - } - } -} - -/*! - \brief the handle function of CTRL_DATA state - \param[in] pudev: pointer to usb device - \param[in] puhost: pointer to usb host - \param[in] pustate: pointer to usb state driver - \param[out] none - \retval none -*/ -static void ctrl_data_handle (usb_core_handle_struct *pudev, - usbh_host_struct *puhost, - usbh_state_handle_struct *pustate) -{ - uint8_t direction; - urb_state_enum urb_status = URB_IDLE; - puhost->usbh_backup_state.ctrl_backup_state = CTRL_DATA; - - direction = (puhost->control.setup.b.bmRequestType & USB_DIR_MASK); - - if (USB_DIR_IN == direction) { - if (0U == ctrl_data_wait_flag) { - ctrl_data_wait_flag = 1U; - - /* issue an IN token */ - usbh_xfer(pudev, - puhost->control.buff, - puhost->control.hc_in_num, - puhost->control.length); - } else { - urb_status = hcd_urb_state_get(pudev, puhost->control.hc_in_num); - - /* check is data packet transfered successfully */ - switch (urb_status) { - case URB_DONE: - ctrl_data_wait_flag = 0U; - - scd_event_handle(pudev, - puhost, - pustate, - CTRL_EVENT_STATUS, - pustate->usbh_current_state); - break; - case URB_STALL: - ctrl_data_wait_flag = 0U; - - scd_event_handle(pudev, - puhost, - pustate, - CTRL_EVENT_STALLED, - pustate->usbh_current_state); - break; - case URB_ERROR: - ctrl_data_wait_flag = 0U; - - /* device error */ - scd_event_handle(pudev, - puhost, - pustate, - CTRL_EVENT_ERROR, - pustate->usbh_current_state); - break; - default: - if (((uint16_t)USB_CURRENT_FRAME_GET() - puhost->control.timer) > timeout) { - ctrl_data_wait_flag = 0U; - - /* timeout for IN transfer */ - scd_event_handle(pudev, - puhost, - pustate, - CTRL_EVENT_ERROR, - pustate->usbh_current_state); - } - break; - } - } - } else { - if (0U == ctrl_data_wait_flag) { - ctrl_data_wait_flag = 1U; - - /* start DATA out transfer (only one DATA packet)*/ - pudev->host.host_channel[puhost->control.hc_out_num].data_tg_out = 1U; - - usbh_xfer(pudev, - puhost->control.buff, - puhost->control.hc_out_num, - puhost->control.length); - } else { - urb_status = hcd_urb_state_get(pudev, puhost->control.hc_out_num); - - switch (urb_status) { - case URB_DONE: - ctrl_data_wait_flag = 0U; - - /* if the setup pkt is sent successful, then change the state */ - scd_event_handle(pudev, - puhost, - pustate, - CTRL_EVENT_STATUS, - pustate->usbh_current_state); - break; - case URB_STALL: - ctrl_data_wait_flag = 0U; - - scd_event_handle(pudev, - puhost, - pustate, - CTRL_EVENT_STALLED, - pustate->usbh_current_state); - break; - case URB_NOTREADY: - /* nack received from device */ - ctrl_data_wait_flag = 0U; - break; - case URB_ERROR: - ctrl_data_wait_flag = 0U; - - /* device error */ - scd_event_handle(pudev, - puhost, - pustate, - CTRL_EVENT_ERROR, - pustate->usbh_current_state); - break; - default: - break; - } - } - } -} - -/*! - \brief the handle function of CTRL_STATUS state - \param[in] pudev: pointer to usb device - \param[in] puhost: pointer to usb host - \param[in] pustate: pointer to usb state driver - \param[out] none - \retval none -*/ -static void ctrl_status_handle (usb_core_handle_struct *pudev, - usbh_host_struct *puhost, - usbh_state_handle_struct *pustate) -{ - uint8_t direction; - urb_state_enum urb_status = URB_IDLE; - - puhost->usbh_backup_state.ctrl_backup_state = CTRL_STATUS; - - /* get the transfer direction in the data state, but the transfer direction in the status state is opposite */ - direction = (puhost->control.setup.b.bmRequestType & USB_DIR_MASK); - - if (USB_DIR_OUT == direction) { - /* handle status in */ - if (0U == ctrl_status_wait_flag) { - ctrl_status_wait_flag = 1U; - usbh_xfer (pudev, 0U, puhost->control.hc_in_num, 0U); - } else { - urb_status = hcd_urb_state_get(pudev, puhost->control.hc_in_num); - - switch (urb_status) { - case URB_DONE: - ctrl_status_wait_flag = 0U; - - /* handle URB_DONE status */ - scd_event_handle(pudev, - puhost, - pustate, - CTRL_EVENT_COMPLETE, - pustate->usbh_current_state); - break; - case URB_ERROR: - ctrl_status_wait_flag = 0U; - - /* handle URB_STALL status*/ - scd_event_handle(pudev, - puhost, - pustate, - CTRL_EVENT_ERROR, - pustate->usbh_current_state); - break; - case URB_STALL: - ctrl_status_wait_flag = 0U; - - /* handle URB_STALL status */ - scd_event_handle(pudev, - puhost, - pustate, - CTRL_EVENT_STALLED, - pustate->usbh_current_state); - break; - default: - if (((uint16_t)USB_CURRENT_FRAME_GET() - puhost->control.timer) > timeout) { - ctrl_status_wait_flag = 0U; - - /* handle timeout */ - scd_event_handle(pudev, - puhost, - pustate, - CTRL_EVENT_ERROR, - pustate->usbh_current_state); - } - break; - } - } - } else { - /* handle status out */ - if (0U == ctrl_status_wait_flag) { - ctrl_status_wait_flag = 1U; - pudev->host.host_channel[puhost->control.hc_out_num].data_tg_out ^= 1U; - usbh_xfer (pudev, 0U, puhost->control.hc_out_num, 0U); - - { - uint32_t host_ctlr = 0; - - host_ctlr = USB_HCHxLEN(puhost->control.hc_out_num); - USB_HCHxLEN(puhost->control.hc_out_num) = host_ctlr | 1; - host_ctlr = USB_HCHxCTL(puhost->control.hc_out_num); - USB_HCHxCTL(puhost->control.hc_out_num) = (host_ctlr & 0x3FFFFFFF) | 0x80000000; - } - } else { - urb_status = hcd_urb_state_get(pudev, puhost->control.hc_out_num); - - switch (urb_status) { - case URB_DONE: - ctrl_status_wait_flag = 0U; - - /* handle URB_DONE status */ - scd_event_handle(pudev, - puhost, - pustate, - CTRL_EVENT_COMPLETE, - pustate->usbh_current_state); - break; - case URB_NOTREADY: - /* handle URB_NOTREADY status */ - ctrl_status_wait_flag = 0U; - break; - case URB_ERROR: - ctrl_status_wait_flag = 0U; - - /* handle URB_ERROR status */ - scd_event_handle(pudev, - puhost, - pustate, - CTRL_EVENT_ERROR, - pustate->usbh_current_state); - break; - default: - break; - } - } - } -} - -/*! - \brief the handle function of CTRL_ERROR state - \param[in] pudev: pointer to usb device - \param[in] puhost: pointer to usb host - \param[in] pustate: pointer to usb state driver - \param[out] none - \retval none -*/ -static void ctrl_error_handle (usb_core_handle_struct *pudev, - usbh_host_struct *puhost, - usbh_state_handle_struct *pustate) -{ - puhost->usbh_backup_state.ctrl_backup_state = CTRL_ERROR; - - if (++puhost->control.error_count <= USBH_MAX_ERROR_COUNT) { - /* do the transmission again, starting from SETUP Packet */ - scd_event_handle(pudev, puhost, pustate, CTRL_EVENT_SETUP, pustate->usbh_current_state); - } else { - scd_event_handle(pudev, puhost, pustate, GO_TO_UP_STATE_EVENT, pustate->usbh_current_state); - } -} - -/*! - \brief the handle function of CTRL_STALLED state - \param[in] pudev: pointer to usb device - \param[in] puhost: pointer to usb host - \param[in] pustate: pointer to usb state driver - \param[out] none - \retval none -*/ -static void ctrl_stalled_handle (usb_core_handle_struct *pudev, - usbh_host_struct *puhost, - usbh_state_handle_struct *pustate) -{ - puhost->usbh_backup_state.ctrl_backup_state = CTRL_STALLED; - scd_event_handle(pudev, puhost, pustate, GO_TO_UP_STATE_EVENT, pustate->usbh_current_state); -} - -/*! - \brief the handle function of CTRL_COMPLETE state - \param[in] pudev: pointer to usb device - \param[in] puhost: pointer to usb host - \param[in] pustate: pointer to usb state driver - \param[out] none - \retval none -*/ -static void ctrl_complete_handle (usb_core_handle_struct *pudev, - usbh_host_struct *puhost, - usbh_state_handle_struct *pustate) -{ - puhost->usbh_backup_state.ctrl_backup_state = CTRL_COMPLETE; - scd_event_handle(pudev, puhost, pustate, GO_TO_UP_STATE_EVENT, pustate->usbh_current_state); -} - -/*! - \brief send datas from the host channel - \param[in] pudev: pointer to usb device - \param[in] buf: data buffer address to send datas - \param[in] hc_num: the number of the host channel - \param[in] len: length of the send data - \param[out] none - \retval host operation status -*/ -usbh_status_enum usbh_xfer (usb_core_handle_struct *pudev, - uint8_t *buf, - uint8_t hc_num, - uint16_t len) -{ - usb_hostchannel_struct *puhc = &pudev->host.host_channel[hc_num]; - - puhc->xfer_buff = buf; - puhc->xfer_len = len; - - switch (puhc->endp_type) { - case USB_EPTYPE_CTRL: - if (0U == puhc->endp_in) { - if (0U == len) { - /* for status out stage, length = 0, status out pid = 1 */ - puhc->data_tg_out = 1U; - } - - /* set the data toggle bit as per the flag */ - if (0U == puhc->data_tg_out) { - /* put the pid 0 */ - puhc->DPID = HC_PID_DATA0; - } else { - /* put the pid 1 */ - puhc->DPID = HC_PID_DATA1; - } - } else { - puhc->DPID = HC_PID_DATA1; - } - break; - - case USB_EPTYPE_ISOC: - puhc->DPID = HC_PID_DATA0; - break; - - case USB_EPTYPE_BULK: - if (0U == puhc->endp_in) { - /* set the data toggle bit as per the flag */ - if (0U == puhc->data_tg_out) { - /* put the pid 0 */ - puhc->DPID = HC_PID_DATA0; - } else { - /* put the pid 1 */ - puhc->DPID = HC_PID_DATA1; - } - } else { - if (0U == puhc->data_tg_in) { - puhc->DPID = HC_PID_DATA0; - } else { - puhc->DPID = HC_PID_DATA1; - } - } - break; - - case USB_EPTYPE_INTR: - if (0U == puhc->endp_in) { - if (0U == puhc->data_tg_out) { - puhc->DPID = HC_PID_DATA0; - } else { - puhc->DPID = HC_PID_DATA1; - } - - /* toggle data pid */ - puhc->data_tg_out ^= 1U; - } else { - if (0U == puhc->data_tg_in) { - puhc->DPID = HC_PID_DATA0; - } else { - puhc->DPID = HC_PID_DATA1; - } - - /* toggle data pid */ - puhc->data_tg_in ^= 1U; - } - break; - - default: - break; - } - - hcd_submit_request (pudev, hc_num); - - return USBH_OK; -} - -/*! - \brief send the setup packet to the device - \param[in] pudev: pointer to usb device - \param[in] buf: buffer pointer from which the data will be send to device - \param[in] hc_num: host channel number - \param[out] none - \retval host operation status -*/ -usbh_status_enum usbh_ctltx_setup (usb_core_handle_struct *pudev, uint8_t *buf, uint8_t hc_num) -{ - usb_hostchannel_struct *puhc = &pudev->host.host_channel[hc_num]; - - puhc->DPID = HC_PID_SETUP; - puhc->xfer_buff = buf; - puhc->xfer_len = USBH_SETUP_PACKET_SIZE; - - return (usbh_status_enum)hcd_submit_request (pudev, hc_num); -} - -/*! - \brief this function prepare a hc and start a transfer - \param[in] pudev: pointer to usb device - \param[in] channel_num: host channel number which is in (0..7) - \param[out] none - \retval host operation status -*/ -uint32_t hcd_submit_request (usb_core_handle_struct *pudev, uint8_t channel_num) -{ - usb_hostchannel_struct *puhc = &pudev->host.host_channel[channel_num]; - - puhc->urb_state = URB_IDLE; - puhc->xfer_count = 0U; - - return (uint32_t)usb_hostchannel_startxfer(pudev, channel_num); -} diff --git a/bsp/gd32450z-eval/Libraries/GD32F4xx_usb_driver/Source/usbh_hcs.c b/bsp/gd32450z-eval/Libraries/GD32F4xx_usb_driver/Source/usbh_hcs.c deleted file mode 100644 index 035459d195..0000000000 --- a/bsp/gd32450z-eval/Libraries/GD32F4xx_usb_driver/Source/usbh_hcs.c +++ /dev/null @@ -1,162 +0,0 @@ -/*! - \file usbh_hcs.c - \brief this file implements functions for opening and closing host channels -*/ - -/* - Copyright (C) 2016 GigaDevice - - 2016-08-15, V1.0.0, firmware for GD32F4xx -*/ - -#include "usbh_hcs.h" - -static uint16_t usbh_freechannel_get (usb_core_handle_struct *pudev); - -/*! - \brief open a channel - \param[in] pudev: pointer to usb device - \param[in] channel_num: host channel number which is in (0..7) - \param[in] dev_addr: USB device address allocated to attached device - \param[in] dev_speed: USB device speed (Full speed/Low speed) - \param[in] ep_type: endpoint type (bulk/int/ctl) - \param[in] ep_mps: max packet size - \param[out] none - \retval operation status -*/ -uint8_t usbh_channel_open (usb_core_handle_struct *pudev, - uint8_t channel_num, - uint8_t dev_addr, - uint8_t dev_speed, - uint8_t ep_type, - uint16_t ep_mps) -{ - usb_hostchannel_struct *puhc = &pudev->host.host_channel[channel_num]; - uint16_t channel_info = puhc->info; - - puhc->endp_id = (uint8_t)channel_info & 0x7FU; - puhc->endp_in = (uint8_t)(channel_info & 0x80U) >> 7; - puhc->endp_type = ep_type; - puhc->endp_mps = ep_mps; - puhc->dev_addr = dev_addr; - puhc->dev_speed = dev_speed; - - puhc->data_tg_in = 0U; - puhc->data_tg_out = 0U; - - if (HPRT_PRTSPD_HIGH_SPEED == dev_speed) { - puhc->do_ping = 1U; - } - - usb_hostchannel_init(pudev, channel_num); - - return (uint8_t)HC_OK; -} - -/*! - \brief modify a channel - \param[in] pudev: pointer to usb device - \param[in] channel_num: host channel number which is in (0..7) - \param[in] dev_addr: USB Device address allocated to attached device - \param[in] dev_speed: USB device speed (Full speed/Low speed) - \param[in] ep_type: endpoint type (bulk/int/ctl) - \param[in] ep_mps: max packet size - \param[out] none - \retval operation status -*/ -uint8_t usbh_channel_modify (usb_core_handle_struct *pudev, - uint8_t channel_num, - uint8_t dev_addr, - uint8_t dev_speed, - uint8_t ep_type, - uint16_t ep_mps) -{ - usb_hostchannel_struct *puhc = &pudev->host.host_channel[channel_num]; - - if (0U != dev_addr) { - puhc->dev_addr = dev_addr; - } - - if ((puhc->endp_mps != ep_mps) && (0U != ep_mps)) { - puhc->endp_mps = ep_mps; - } - - if ((puhc->dev_speed != dev_speed) && (0U != dev_speed)) { - puhc->dev_speed = dev_speed; - } - - usb_hostchannel_init(pudev, channel_num); - - return (uint8_t)HC_OK; -} - -/*! - \brief allocate a new channel for the pipe - \param[in] pudev: pointer to usb device - \param[in] ep_addr: endpoint for which the channel to be allocated - \param[out] none - \retval host channel number -*/ -uint8_t usbh_channel_alloc (usb_core_handle_struct *pudev, uint8_t ep_addr) -{ - uint16_t hc_num = usbh_freechannel_get(pudev); - - if ((uint16_t)HC_ERROR != hc_num) { - pudev->host.host_channel[hc_num].info = HC_USED | ep_addr; - } - - return (uint8_t)hc_num; -} - -/*! - \brief free the usb host channel - \param[in] pudev: pointer to usb device - \param[in] index: channel number to be freed which is in (0..7) - \param[out] none - \retval host operation status -*/ -uint8_t usbh_channel_free (usb_core_handle_struct *pudev, uint8_t index) -{ - if (index < HC_MAX) { - pudev->host.host_channel[index].info &= HC_USED_MASK; - } - - return USBH_OK; -} - -/*! - \brief free all usb host channel - \param[in] pudev: pointer to usb device - \param[out] none - \retval host operation status -*/ -uint8_t usbh_allchannel_dealloc (usb_core_handle_struct *pudev) -{ - uint8_t index; - - for (index = 2U; index < HC_MAX; index ++) { - pudev->host.host_channel[index].info = 0U; - } - - return USBH_OK; -} - -/*! - \brief get a free channel number for allocation to a device endpoint - \param[in] pudev: pointer to usb device - \param[out] none - \retval free channel number -*/ -static uint16_t usbh_freechannel_get (usb_core_handle_struct *pudev) -{ - uint8_t index = 0U; - - for (index = 0U; index < HC_MAX; index++) { - if (0U == (pudev->host.host_channel[index].info & HC_USED)) { - return (uint16_t)index; - } - } - - return HC_ERROR; -} - diff --git a/bsp/gd32450z-eval/Libraries/GD32F4xx_usb_driver/Source/usbh_int.c b/bsp/gd32450z-eval/Libraries/GD32F4xx_usb_driver/Source/usbh_int.c deleted file mode 100644 index a386d185ed..0000000000 --- a/bsp/gd32450z-eval/Libraries/GD32F4xx_usb_driver/Source/usbh_int.c +++ /dev/null @@ -1,591 +0,0 @@ -/*! - \file usbh_int.c - \brief USB host mode interrupt handler file -*/ - -/* - Copyright (C) 2016 GigaDevice - - 2016-08-15, V1.0.1, firmware for GD32F4xx -*/ - -#include "usb_core.h" -#include "usb_defines.h" -#include "usbh_int.h" - -static uint32_t usbh_intf_sof (usb_core_handle_struct *pudev); -static uint32_t usbh_intf_port (usb_core_handle_struct *pudev); -static uint32_t usbh_intf_hc (usb_core_handle_struct *pudev); -static uint32_t usbh_intf_hc_in (usb_core_handle_struct *pudev, uint8_t channel_num); -static uint32_t usbh_intf_hc_out (usb_core_handle_struct *pudev, uint8_t channel_num); -static uint32_t usbh_intf_rxfifo_noempty (usb_core_handle_struct *pudev); -static uint32_t usbh_intf_nptxfifo_empty (usb_core_handle_struct *pudev); -static uint32_t usbh_intf_ptxfifo_empty (usb_core_handle_struct *pudev); -static uint32_t usbh_intf_disconnect (usb_core_handle_struct *pudev); -static uint32_t usbh_intf_iso_incomplete_xfer (usb_core_handle_struct *pudev); - -/*! - \brief handle global host interrupt - \param[in] pudev: pointer to usb device instance - \param[out] none - \retval operation status -*/ -uint32_t usbh_isr (usb_core_handle_struct *pudev) -{ - uint32_t retval = 0U; - uint32_t int_flag = 0U; - - /* check if host mode */ - if (USB_CURRENT_MODE_GET() == HOST_MODE) { - USB_CORE_INTR_READ(int_flag); - - if (!int_flag) { - return 0U; - } - - /* start of frame interrupt handle */ - if (int_flag & GINTF_SOF) { - retval |= usbh_intf_sof (pudev); - } - - /* Rx FIFO non-empty interrupt handle */ - if (int_flag & GINTF_RXFNEIF) { - retval |= usbh_intf_rxfifo_noempty (pudev); - } - - /* Non-Periodic Tx FIFO empty interrupt hanlde */ - if (int_flag & GINTF_NPTXFEIF) { - retval |= usbh_intf_nptxfifo_empty (pudev); - } - - /* periodic Tx FIFO empty interrupt handle */ - if (int_flag & GINTF_PTXFEIF) { - retval |= usbh_intf_ptxfifo_empty (pudev); - } - - /* host channels interrupt handle */ - if (int_flag & GINTF_HCIF) { - retval |= usbh_intf_hc (pudev); - } - - /* host port interrupt handle */ - if (int_flag & GINTF_HPIF) { - retval |= usbh_intf_port (pudev); - } - - /* disconnect interrupt handle */ - if (int_flag & GINTF_DISCIF) { - retval |= usbh_intf_disconnect (pudev); - } - - /* isochronous IN transfer not complete interrupt handle */ - if (int_flag & GINTF_ISOONCIF) { - retval |= usbh_intf_iso_incomplete_xfer (pudev); - } - } - - return retval; -} - -/*! - \brief handle the start-of-frame interrupt in host mode - \param[in] pudev: pointer to usb device instance - \param[out] none - \retval operation status -*/ -static uint32_t usbh_intf_sof (usb_core_handle_struct *pudev) -{ - usbh_hcd_int_fops->sof(pudev); - - /* clear interrupt */ - USB_GINTF = GINTF_SOF; - - return 1U; -} - -/*! - \brief handle all host channels interrupt in host mode - \param[in] pudev: pointer to usb device instance - \param[out] none - \retval operation status -*/ -static uint32_t usbh_intf_hc (usb_core_handle_struct *pudev) -{ - uint8_t i = 0U; - uint32_t retval = 0U; - - for (i = 0U; i < pudev->cfg.host_channel_num; i++) { - if ((USB_HACHINT & HACHINT_HACHINT) & ((uint32_t)1U << i)) { - if ((USB_HCHxCTL((uint16_t)i) & HCHCTL_EPDIR) >> 15U) { - retval |= usbh_intf_hc_in (pudev, i); - } else { - retval |= usbh_intf_hc_out (pudev, i); - } - } - } - - return retval; -} - -/*! - \brief handle the disconnect interrupt - \param[in] pudev: pointer to usb device instance - \param[out] none - \retval operation status -*/ -static uint32_t usbh_intf_disconnect (usb_core_handle_struct *pudev) -{ - usbh_hcd_int_fops->device_disconnected(pudev); - - /* clear interrupt */ - USB_GINTF = GINTF_DISCIF; - - return 1U; -} - -/*! - \brief handle the non-periodic tx fifo empty interrupt - \param[in] pudev: pointer to usb device instance - \param[out] none - \retval operation status -*/ -static uint32_t usbh_intf_nptxfifo_empty (usb_core_handle_struct *pudev) -{ - uint8_t channel_num = 0U; - uint32_t dword_len = 0U, len = 0U; - usb_hostchannel_struct *puhc; - - channel_num = (uint8_t)((USB_HNPTFQSTAT & HNPTFQSTAT_CNUM) >> 27U); - puhc = &pudev->host.host_channel[channel_num]; - dword_len = (puhc->xfer_len + 3U) / 4U; - - while (((USB_HNPTFQSTAT & HNPTFQSTAT_NPTXFS) > dword_len) && (0U != puhc->xfer_len)) { - len = (USB_HNPTFQSTAT & HNPTFQSTAT_NPTXFS) * 4U; - - if (len > puhc->xfer_len) { - /* last packet */ - len = (uint16_t)puhc->xfer_len; - - USB_GINTEN &= ~GINTF_NPTXFEIF; - - } - - dword_len = (puhc->xfer_len + 3U) / 4U; - usb_fifo_write (puhc->xfer_buff, channel_num, (uint16_t)len); - - puhc->xfer_buff += len; - puhc->xfer_len -= len; - puhc->xfer_count += len; - } - - return 1U; -} - -/*! - \brief handle the periodic tx fifo empty interrupt - \param[in] pudev: pointer to usb device instance - \param[out] none - \retval operation status -*/ -static uint32_t usbh_intf_ptxfifo_empty (usb_core_handle_struct *pudev) -{ - uint8_t channel_num = 0U; - uint32_t dword_len = 0U, len = 0U; - usb_hostchannel_struct *puhc; - - channel_num = (uint8_t)((USB_HPTFQSTAT & HPTFQSTAT_CNUM) >> 27U); - puhc = &pudev->host.host_channel[channel_num]; - dword_len = (puhc->xfer_len + 3U) / 4U; - - while (((USB_HPTFQSTAT & HPTFQSTAT_PTXFS) > dword_len) && (0U != puhc->xfer_len)) { - len = (USB_HPTFQSTAT & HPTFQSTAT_PTXFS) * 4U; - - if (len > puhc->xfer_len) { - len = puhc->xfer_len; - - /* last packet */ - USB_GINTEN &= ~GINTF_PTXFEIF; - } - - dword_len = (puhc->xfer_len + 3U) / 4U; - usb_fifo_write (puhc->xfer_buff, channel_num, (uint16_t)len); - - puhc->xfer_buff += len; - puhc->xfer_len -= len; - puhc->xfer_count += len; - } - - return 1U; -} - -/*! - \brief handle the host port interrupt - \param[in] pudev: pointer to usb device instance - \param[out] none - \retval operation status -*/ -static uint32_t usbh_intf_port (usb_core_handle_struct *pudev) -{ - uint8_t port_speed = 0U; - uint8_t port_reset = 0U; - uint32_t retval = 0U; - __IO uint32_t hostportdup = USB_HPCS; - - /* clear the interrupt bits in gintsts */ - hostportdup &= ~HPCS_PE; - hostportdup &= ~HPCS_PCD; - hostportdup &= ~HPCS_PEDC; - - /* port connect detected */ - if (USB_HPCS & HPCS_PCD) { - hostportdup |= HPCS_PCD; - usbh_hcd_int_fops->device_connected(pudev); - retval |= 1U; - } - - /* port enable changed */ - if (USB_HPCS & HPCS_PEDC) { - hostportdup |= HPCS_PEDC; - - if (USB_HPCS & HPCS_PE) { - port_speed = (uint8_t)((USB_HPCS & HPCS_PS) >> 17U); - - if (HPRT_PRTSPD_LOW_SPEED == port_speed) { - USB_HFT = 6000U; - - if (HCTLR_6_MHZ != (USB_HCTL & HCTL_CLKSEL)) { - if (USB_CORE_EMBEDDED_PHY == pudev->cfg.phy_interface) { - USB_FSLSCLOCK_INIT(HCTLR_6_MHZ); - } - port_reset = 1U; - } - } else if(HPRT_PRTSPD_FULL_SPEED == port_speed) { - USB_HFT = 48000U; - - if (HCTLR_48_MHZ != (USB_HCTL & HCTL_CLKSEL)) { - if (USB_CORE_EMBEDDED_PHY == pudev->cfg.phy_interface) { - USB_FSLSCLOCK_INIT(HCTLR_48_MHZ); - } - port_reset = 1U; - } - } else { - /* for high speed device and others */ - port_reset = 1U; - } - - - } - } - - if (port_reset) { - usb_port_reset(pudev); - } - - /* clear port interrupts */ - USB_HPCS = hostportdup; - - return retval; -} - -/*! - \brief handle the OUT channel interrupt - \param[in] pudev: pointer to usb device instance - \param[in] channel_num: host channel number which is in (0..7) - \param[out] none - \retval operation status -*/ -static uint32_t usbh_intf_hc_out (usb_core_handle_struct *pudev, uint8_t channel_num) -{ - uint32_t channel_intr = USB_HCHxINTF((uint16_t)channel_num); - usb_hostchannel_struct *puhc = &pudev->host.host_channel[channel_num]; - - channel_intr &= USB_HCHxINTEN((uint16_t)channel_num); - - if (channel_intr & HCHINTF_ACK) { - if (URB_PING == puhc->urb_state) { - puhc->err_count = 0U; - USB_HCHxINTEN((uint16_t)channel_num) |= HCHINTEN_CHIE; - usb_hostchannel_halt(pudev, channel_num); - USB_HCHxINTF((uint16_t)channel_num) = HCHINTF_TF; - puhc->status = HC_XF; - } - - USB_HCHxINTF((uint16_t)channel_num) = HCHINTF_ACK; - } else if (channel_intr & HCHINTF_REQOVR) { - USB_HCHxINTEN((uint16_t)channel_num) |= HCHINTEN_CHIE; - usb_hostchannel_halt(pudev, channel_num); - USB_HCHxINTF((uint16_t)channel_num) = HCHINTF_REQOVR; - } else if (channel_intr & HCHINTF_TF) { - puhc->err_count = 0U; - USB_HCHxINTEN((uint16_t)channel_num) |= HCHINTEN_CHIE; - usb_hostchannel_halt(pudev, channel_num); - USB_HCHxINTF((uint16_t)channel_num) = HCHINTF_TF; - puhc->status = HC_XF; - } else if (channel_intr & HCHINTF_STALL) { - USB_HCHxINTEN((uint16_t)channel_num) |= HCHINTEN_CHIE; - USB_HCHxINTF((uint16_t)channel_num) = HCHINTF_STALL; - usb_hostchannel_halt(pudev, channel_num); - puhc->status = HC_STALL; - } else if (channel_intr & HCHINTF_NAK) { - puhc->err_count = 0U; - USB_HCHxINTEN((uint16_t)channel_num) |= HCHINTEN_CHIE; - usb_hostchannel_halt(pudev, channel_num); - USB_HCHxINTF((uint16_t)channel_num) = HCHINTF_NAK; - puhc->status = HC_NAK; - } else if (channel_intr & HCHINTF_USBER) { - USB_HCHxINTEN((uint16_t)channel_num) |= HCHINTEN_CHIE; - usb_hostchannel_halt(pudev, channel_num); - puhc->err_count ++; - puhc->status = HC_TRACERR; - USB_HCHxINTF((uint16_t)channel_num) = HCHINTF_USBER; - } else if (channel_intr & HCHINTF_NYET) { - puhc->err_count = 0U; - USB_HCHxINTEN((uint16_t)channel_num) |= HCHINTEN_CHIE; - puhc->status = HC_NYET; - USB_HCHxINTF((uint16_t)channel_num) = HCHINTF_NYET; - } else if (channel_intr & HCHINTF_DTER) { - USB_HCHxINTEN((uint16_t)channel_num) |= HCHINTEN_CHIE; - usb_hostchannel_halt(pudev, channel_num); - puhc->status= HC_DTGERR; - USB_HCHxINTF((uint16_t)channel_num) = HCHINTF_DTER; - } else if (channel_intr & HCHINTF_CH) { - USB_HCHxINTEN((uint16_t)channel_num) &= ~HCHINTEN_CHIE; - - switch (puhc->status) { - case HC_XF: - puhc->urb_state = URB_DONE; - - if (USB_EPTYPE_BULK == ((USB_HCHxCTL((uint16_t)channel_num) & HCHCTL_EPTYPE) >> 18)) { - puhc->data_tg_out ^= 1U; - } - break; - case HC_NAK: - if (URB_PING == puhc->urb_state) { - usb_hostchannel_ping(pudev, channel_num); - } else { - puhc->urb_state = URB_NOTREADY; - } - break; - case HC_NYET: - if (1U == puhc->do_ping) { - usb_hostchannel_ping(pudev, channel_num); - puhc->urb_state = URB_PING; - } - break; - case HC_STALL: - puhc->urb_state = URB_STALL; - break; - case HC_TRACERR: - if (3U == puhc->err_count) { - puhc->urb_state = URB_ERROR; - puhc->err_count = 0U; - } - break; - default: - break; - } - - USB_HCHxINTF((uint16_t)channel_num) = HCHINTF_CH; - } else { - /* no operation */ - } - - return 1U; -} - -/*! - \brief handle the IN channel interrupt - \param[in] pudev: pointer to usb device instance - \param[in] channel_num: host channel number which is in (0..7) - \param[out] none - \retval operation status -*/ -static uint32_t usbh_intf_hc_in (usb_core_handle_struct *pudev, uint8_t channel_num) -{ - uint8_t endp_type = 0U; - usb_hostchannel_struct *puhc = &pudev->host.host_channel[channel_num]; - - uint32_t channle_intf = USB_HCHxINTF((uint16_t)channel_num); - __IO uint32_t channel_ctrl = USB_HCHxCTL((uint16_t)channel_num); - - channle_intf &= USB_HCHxINTEN((uint16_t)channel_num); - - endp_type = (uint8_t)((channel_ctrl & HCHCTL_EPTYPE) >> 18U); - - if (channle_intf & HCHINTF_ACK) { - USB_HCHxINTF((uint16_t)channel_num) = HCHINTF_ACK; - } else if (channle_intf & HCHINTF_STALL) { - USB_HCHxINTEN((uint16_t)channel_num) |= HCHINTEN_CHIE; - puhc->status = HC_STALL; - USB_HCHxINTF((uint16_t)channel_num) = HCHINTF_NAK; - USB_HCHxINTF((uint16_t)channel_num) = HCHINTF_STALL; - - /* NOTE: When there is a 'stall', reset also nak, - else, the pudev->host.status = HC_STALL - will be overwritten by 'nak' in code below */ - channle_intf &= ~HCHINTF_NAK; - - usb_hostchannel_halt(pudev, channel_num); - } else if (channle_intf & HCHINTF_DTER) { - USB_HCHxINTEN((uint16_t)channel_num) |= HCHINTEN_CHIE; - usb_hostchannel_halt(pudev, channel_num); - USB_HCHxINTF((uint16_t)channel_num) = HCHINTF_NAK; - puhc->status = HC_DTGERR; - USB_HCHxINTF((uint16_t)channel_num) = HCHINTF_DTER; - } else { - /* no operation */ - } - - if (channle_intf & HCHINTF_REQOVR) { - USB_HCHxINTEN((uint16_t)channel_num) |= HCHINTEN_CHIE; - usb_hostchannel_halt(pudev, channel_num); - USB_HCHxINTF((uint16_t)channel_num) = HCHINTF_REQOVR; - } else if (channle_intf & HCHINTF_TF) { - if (pudev->cfg.dma_enable == 1U) { - uint32_t xfer_size = USB_HCHxLEN((uint16_t)channel_num) & HCHLEN_TLEN; - puhc->xfer_count = puhc->xfer_len - xfer_size; - } - - puhc->status = HC_XF; - puhc->err_count = 0U; - USB_HCHxINTF((uint16_t)channel_num) = HCHINTF_TF; - - if ((USB_EPTYPE_CTRL == endp_type) || (USB_EPTYPE_BULK == endp_type)) { - USB_HCHxINTEN((uint16_t)channel_num) |= HCHINTEN_CHIE; - usb_hostchannel_halt(pudev, channel_num); - USB_HCHxINTF((uint16_t)channel_num) = HCHINTF_NAK; - puhc->data_tg_in ^= 1U; - } else if (USB_EPTYPE_INTR == endp_type) { - channel_ctrl |= HCHCTL_ODDFRM; - USB_HCHxCTL((uint16_t)channel_num) = channel_ctrl; - puhc->urb_state = URB_DONE; - } else { - /* no operation */ - } - } else if (channle_intf & HCHINTF_CH) { - USB_HCHxINTEN((uint16_t)channel_num) &= ~HCHINTEN_CHIE; - - switch (puhc->status) { - case HC_XF: - puhc->urb_state = URB_DONE; - break; - case HC_TRACERR: - case HC_DTGERR: - puhc->err_count = 0U; - puhc->urb_state = URB_ERROR; - break; - case HC_STALL: - puhc->urb_state = URB_STALL; - break; - default: - if (USB_EPTYPE_INTR == endp_type) { - puhc->data_tg_in ^= 1U; - } - break; - } - - USB_HCHxINTF((uint16_t)channel_num) = HCHINTF_CH; - } else if (channle_intf & HCHINTF_USBER) { - USB_HCHxINTEN((uint16_t)channel_num) |= HCHINTEN_CHIE; - (puhc->err_count)++; - puhc->status = HC_TRACERR; - usb_hostchannel_halt(pudev, channel_num); - USB_HCHxINTF((uint16_t)channel_num) = HCHINTF_USBER; - } else if (channle_intf & HCHINTF_NAK) { - if (USB_EPTYPE_INTR == endp_type) { - USB_HCHxINTEN((uint16_t)channel_num) |= HCHINTEN_CHIE; - usb_hostchannel_halt(pudev, channel_num); - } else if ((USB_EPTYPE_CTRL == endp_type) || (USB_EPTYPE_BULK == endp_type)) { - /* re-activate the channel */ - channel_ctrl |= HCHCTL_CEN; - channel_ctrl &= ~HCHCTL_CDIS; - USB_HCHxCTL((uint16_t)channel_num) = channel_ctrl; - } else { - /* no operation */ - } - - puhc->status = HC_NAK; - USB_HCHxINTF((uint16_t)channel_num) = HCHINTF_NAK; - } else { - /* no operation */ - } - - return 1U; -} - -/*! - \brief handle the rx fifo non-empty interrupt - \param[in] pudev: pointer to usb device instance - \param[out] none - \retval operation status -*/ -static uint32_t usbh_intf_rxfifo_noempty (usb_core_handle_struct *pudev) -{ - uint32_t count = 0U; - __IO uint8_t channel_num = 0U; - __IO uint32_t rx_status = 0U; - uint32_t usbh_ch_ctl_reg = 0U; - usb_hostchannel_struct *puhc; - - /* disable the Rx status queue level interrupt */ - USB_GINTEN &= ~GINTF_RXFNEIF; - - rx_status = USB_GRSTATP; - channel_num = (uint8_t)(rx_status & GRSTATR_CNUM); - puhc = &pudev->host.host_channel[channel_num]; - - switch ((rx_status & GRSTATR_RPCKST) >> 17) { - case GRSTATR_RPCKST_IN: - count = (rx_status & GRSTATR_BCOUNT) >> 4; - - /* read the data into the host buffer. */ - if ((count > 0U) && (puhc->xfer_buff != (void *)0)) { - usb_fifo_read(puhc->xfer_buff, (uint16_t)count); - - /* manage multiple Xfer */ - puhc->xfer_buff += count; - puhc->xfer_count += count; - - if (USB_HCHxLEN((uint16_t)channel_num) & HCHLEN_PCNT) { - /* re-activate the channel when more packets are expected */ - usbh_ch_ctl_reg = USB_HCHxCTL((uint16_t)channel_num); - usbh_ch_ctl_reg |= HCHCTL_CEN; - usbh_ch_ctl_reg &= ~HCHCTL_CDIS; - USB_HCHxCTL((uint16_t)channel_num) = usbh_ch_ctl_reg; - } - } - break; - case GRSTATR_RPCKST_IN_XFER_COMP: - case GRSTATR_RPCKST_DATA_TOGGLE_ERR: - case GRSTATR_RPCKST_CH_HALTED: - default: - break; - } - - /* enable the Rx status queue level interrupt */ - USB_GINTEN |= GINTF_RXFNEIF; - - return 1U; -} - -/*! - \brief handle the incomplete periodic transfer interrupt - \param[in] pudev: pointer to usb device instance - \param[out] none - \retval operation status -*/ -static uint32_t usbh_intf_iso_incomplete_xfer (usb_core_handle_struct *pudev) -{ - __IO uint32_t gint_flag = 0U; - - gint_flag = USB_HCHxCTL(0U); - USB_HCHxCTL(0U) = 0U; - - gint_flag = 0U; - - /* clear interrupt */ - gint_flag |= GINTF_ISOONCIF; - USB_GINTF = gint_flag; - - return 1U; -} diff --git a/bsp/gd32450z-eval/Libraries/GD32F4xx_usb_driver/Source/usbh_std.c b/bsp/gd32450z-eval/Libraries/GD32F4xx_usb_driver/Source/usbh_std.c deleted file mode 100644 index 57f9e996a4..0000000000 --- a/bsp/gd32450z-eval/Libraries/GD32F4xx_usb_driver/Source/usbh_std.c +++ /dev/null @@ -1,808 +0,0 @@ -/*! - \file usbh_std.c - \brief USB 2.0 standard function definition -*/ - -/* - Copyright (C) 2016 GigaDevice - - 2016-08-15, V1.0.1, firmware for GD32F4xx -*/ - -#include "usbh_core.h" -#include "usbh_usr.h" -#include "usbh_std.h" -#include "usbh_ctrl.h" - -uint8_t local_buffer[64]; -uint8_t usbh_cfg_desc[512]; -uint8_t enum_polling_handle_flag = 0U; - -static void enum_idle_handle (usb_core_handle_struct *pudev, usbh_host_struct *puhost, usbh_state_handle_struct *pustate); -static void enum_get_full_dev_desc_handle (usb_core_handle_struct *pudev, usbh_host_struct *puhost, usbh_state_handle_struct *pustate); -static void enum_set_addr_handle (usb_core_handle_struct *pudev, usbh_host_struct *puhost, usbh_state_handle_struct *pustate); -static void enum_get_cfg_desc_handle (usb_core_handle_struct *pudev, usbh_host_struct *puhost, usbh_state_handle_struct *pustate); -static void enum_get_full_cfg_desc_handle (usb_core_handle_struct *pudev, usbh_host_struct *puhost, usbh_state_handle_struct *pustate); -static void enum_get_mfc_string_desc_handle (usb_core_handle_struct *pudev, usbh_host_struct *puhost, usbh_state_handle_struct *pustate); -static void enum_get_product_string_desc_handle (usb_core_handle_struct *pudev, usbh_host_struct *puhost, usbh_state_handle_struct *pustate); -static void enum_get_serialnum_string_desc_handle (usb_core_handle_struct *pudev, usbh_host_struct *puhost, usbh_state_handle_struct *pustate); -static void enum_set_configuration_handle (usb_core_handle_struct *pudev, usbh_host_struct *puhost, usbh_state_handle_struct *pustate); -static void enum_dev_configured_handle (usb_core_handle_struct *pudev, usbh_host_struct *puhost, usbh_state_handle_struct *pustate); - -/* the enumeration state handle function array */ -void (*enum_state_handle[]) (usb_core_handle_struct *pudev, usbh_host_struct *puhost, usbh_state_handle_struct *pustate) = -{ - enum_idle_handle, - enum_set_addr_handle, - enum_get_full_dev_desc_handle, - enum_get_cfg_desc_handle, - enum_get_full_cfg_desc_handle, - enum_get_mfc_string_desc_handle, - enum_get_product_string_desc_handle, - enum_get_serialnum_string_desc_handle, - enum_set_configuration_handle, - enum_dev_configured_handle, -}; - -/* the enumeration state handle table */ -state_table_struct enum_handle_table[ENUM_HANDLE_TABLE_SIZE] = -{ - /* the current state the current event the next state the event function */ - {ENUM_IDLE, ENUM_EVENT_SET_ADDR, ENUM_SET_ADDR, only_state_move }, - {ENUM_SET_ADDR, ENUN_EVENT_GET_FULL_DEV_DESC, ENUM_GET_FULL_DEV_DESC, only_state_move }, - {ENUM_GET_FULL_DEV_DESC, ENUN_EVENT_GET_CFG_DESC, ENUM_GET_CFG_DESC, only_state_move }, - {ENUM_GET_CFG_DESC, ENUN_EVENT_GET_FULL_CFG_DESC, ENUM_GET_FULL_CFG_DESC, only_state_move }, - {ENUM_GET_FULL_CFG_DESC, ENUN_EVENT_GET_MFC_STRING_DESC, ENUM_GET_MFC_STRING_DESC, only_state_move }, - {ENUM_GET_MFC_STRING_DESC, ENUN_EVENT_GET_PRODUCT_STRING_DESC, ENUM_GET_PRODUCT_STRING_DESC, only_state_move }, - {ENUM_GET_PRODUCT_STRING_DESC, ENUN_EVENT_GET_SERIALNUM_STRING_DESC, ENUM_GET_SERIALNUM_STRING_DESC, only_state_move }, - {ENUM_GET_SERIALNUM_STRING_DESC, ENUN_EVENT_SET_CONFIGURATION, ENUM_SET_CONFIGURATION, only_state_move }, - {ENUM_SET_CONFIGURATION, ENUN_EVENT_DEV_CONFIGURED, ENUM_DEV_CONFIGURED, only_state_move }, - {ENUM_DEV_CONFIGURED, GO_TO_UP_STATE_EVENT, UP_STATE, goto_up_state_fun }, -}; - -/*! - \brief the polling function of enumeration state - \param[in] pudev: pointer to USB device - \param[in] puhost: pointer to USB host - \param[in] pustate: pointer to USB state driver - \param[out] none - \retval usb host status -*/ -usbh_status_enum enum_state_polling_fun (usb_core_handle_struct *pudev, usbh_host_struct *puhost, void *pustate) -{ - usbh_status_enum exe_state = USBH_BUSY; - usbh_state_handle_struct *p_state; - p_state = (usbh_state_handle_struct *)pustate; - - if (0U == enum_polling_handle_flag) { - enum_polling_handle_flag = 1U; - scd_table_push(p_state); - scd_state_move(p_state, ENUM_IDLE); - } - - /* start the enumeration state handle */ - scd_begin(p_state,ENUM_FSM_ID); - - if (0U == p_state->usbh_current_state_stack_top) { - enum_state_handle[p_state->usbh_current_state](pudev, puhost, p_state); - } else { - enum_state_handle[p_state->stack[1].state](pudev, puhost, p_state); - } - - /* determine the enumeration whether to complete */ - if (ENUM_DEV_CONFIGURED == puhost->usbh_backup_state.enum_backup_state) { - puhost->usbh_backup_state.enum_backup_state = ENUM_IDLE; - enum_polling_handle_flag = 0U; - exe_state = USBH_OK; - } - - return exe_state; -} - -/*! - \brief the handle function of ENUM_IDLE state - \param[in] pudev: pointer to USB device - \param[in] puhost: pointer to USB host - \param[in] pustate: pointer to USB state driver - \param[out] none - \retval none -*/ -static void enum_idle_handle (usb_core_handle_struct *pudev, usbh_host_struct *puhost, usbh_state_handle_struct *pustate) -{ - puhost->usbh_backup_state.enum_backup_state = ENUM_IDLE; - - if (CTRL_IDLE == puhost->usbh_backup_state.ctrl_backup_state) { - usbh_enum_desc_get(pudev, - puhost, - pudev->host.rx_buffer, - USB_REQTYPE_DEVICE | USB_STANDARD_REQ, - USB_DEVDESC, - 8U); - if ((void *)0 != pudev->mdelay) { - pudev->mdelay(100U); - } - } - - if (USBH_OK == ctrl_state_polling_fun(pudev, puhost, pustate)) { - usbh_device_desc_parse(&puhost->device.dev_desc, pudev->host.rx_buffer, 8U); - puhost->control.ep0_size = puhost->device.dev_desc.bMaxPacketSize0; - - /* issue reset */ - usb_port_reset(pudev); - - /* modify control channels configuration for maxpacket size */ - usbh_channel_modify (pudev, - puhost->control.hc_out_num, - 0U, - 0U, - 0U, - (uint16_t)puhost->control.ep0_size); - - usbh_channel_modify (pudev, - puhost->control.hc_in_num, - 0U, - 0U, - 0U, - (uint16_t)puhost->control.ep0_size); - - scd_event_handle(pudev, - puhost, - pustate, - ENUM_EVENT_SET_ADDR, - pustate->usbh_current_state); - } -} - -/*! - \brief the handle function of ENUM_GET_FULL_DEV_DESC state - \param[in] pudev: pointer to USB device - \param[in] puhost: pointer to USB host - \param[in] pustate: pointer to USB state driver - \param[out] none - \retval none -*/ -static void enum_get_full_dev_desc_handle (usb_core_handle_struct *pudev, - usbh_host_struct *puhost, - usbh_state_handle_struct *pustate) -{ - puhost->usbh_backup_state.enum_backup_state = ENUM_GET_FULL_DEV_DESC; - - if (CTRL_IDLE == puhost->usbh_backup_state.ctrl_backup_state) { - usbh_enum_desc_get(pudev, - puhost, - pudev->host.rx_buffer, - USB_REQTYPE_DEVICE | USB_STANDARD_REQ, - USB_DEVDESC, - USB_DEVDESC_SIZE); - } - - if(USBH_OK == ctrl_state_polling_fun(pudev, puhost, pustate)){ - usbh_device_desc_parse(&puhost->device.dev_desc, pudev->host.rx_buffer, USB_DEVDESC_SIZE); - puhost->usr_cb->device_desc_available(&puhost->device.dev_desc); - - scd_event_handle(pudev, - puhost, - pustate, - ENUN_EVENT_GET_CFG_DESC, - pustate->usbh_current_state); - } -} - -/*! - \brief the handle function of ENUM_SET_ADDR state - \param[in] pudev: pointer to USB device - \param[in] puhost: pointer to USB host - \param[in] pustate: pointer to USB state driver - \param[out] none - \retval none -*/ -static void enum_set_addr_handle (usb_core_handle_struct *pudev, - usbh_host_struct *puhost, - usbh_state_handle_struct *pustate) -{ - puhost->usbh_backup_state.enum_backup_state = ENUM_SET_ADDR; - - if (CTRL_IDLE == puhost->usbh_backup_state.ctrl_backup_state) { - usbh_enum_addr_set(pudev, puhost,USBH_DEVICE_ADDRESS); - if ((void *)0 != pudev->mdelay) { - pudev->mdelay(100U); - } - } - - if (USBH_OK == ctrl_state_polling_fun(pudev, puhost, pustate)) { - if ((void *)0 != pudev->mdelay) { - pudev->mdelay(2U); - } - puhost->device.address = USBH_DEVICE_ADDRESS; - - /* user callback for device address assigned */ - puhost->usr_cb->device_address_set(); - - /* modify control channels to update device address */ - usbh_channel_modify (pudev, - puhost->control.hc_in_num, - puhost->device.address, - 0U, - 0U, - 0U); - - usbh_channel_modify (pudev, - puhost->control.hc_out_num, - puhost->device.address, - 0U, - 0U, - 0U); - - scd_event_handle(pudev, - puhost, - pustate, - ENUN_EVENT_GET_FULL_DEV_DESC, - pustate->usbh_current_state); - } -} - -/*! - \brief the handle function of ENUM_GET_CFG_DESC state - \param[in] pudev: pointer to USB device - \param[in] puhost: pointer to USB host - \param[in] pustate: pointer to USB state driver - \param[out] none - \retval none -*/ -static void enum_get_cfg_desc_handle (usb_core_handle_struct *pudev, - usbh_host_struct *puhost, - usbh_state_handle_struct *pustate) -{ - uint16_t index = 0U; - - puhost->usbh_backup_state.enum_backup_state = ENUM_GET_CFG_DESC; - - if (CTRL_IDLE == puhost->usbh_backup_state.ctrl_backup_state) { - usbh_enum_desc_get(pudev, - puhost, - pudev->host.rx_buffer, - USB_REQTYPE_DEVICE | USB_STANDARD_REQ, - USB_CFGDESC, - USB_CFGDESC_SIZE); - } - - if (USBH_OK == ctrl_state_polling_fun(pudev, puhost, pustate)) { - /* save configuration descriptor for class parsing usage */ - for (; index < USB_CFGDESC_SIZE; index ++) { - usbh_cfg_desc[index] = pudev->host.rx_buffer[index]; - } - - /* commands successfully sent and response received */ - usbh_cfg_desc_parse (&puhost->device.cfg_desc, - puhost->device.itf_desc, - puhost->device.ep_desc, - pudev->host.rx_buffer, - USB_CFGDESC_SIZE); - - scd_event_handle(pudev, - puhost, - pustate, - ENUN_EVENT_GET_FULL_CFG_DESC, - pustate->usbh_current_state); - } -} - -/*! - \brief the handle function of ENUM_GET_FULL_CFG_DESC state - \param[in] pudev: pointer to USB device - \param[in] puhost: pointer to USB host - \param[in] pustate: pointer to USB state driver - \param[out] none - \retval none -*/ -static void enum_get_full_cfg_desc_handle (usb_core_handle_struct *pudev, - usbh_host_struct *puhost, - usbh_state_handle_struct *pustate) -{ - - uint16_t index = 0U; - - puhost->usbh_backup_state.enum_backup_state = ENUM_GET_FULL_CFG_DESC; - - if (CTRL_IDLE == puhost->usbh_backup_state.ctrl_backup_state) { - usbh_enum_desc_get (pudev, puhost, pudev->host.rx_buffer, - USB_REQTYPE_DEVICE | USB_STANDARD_REQ, - USB_CFGDESC, puhost->device.cfg_desc.wTotalLength); - } - - - if (USBH_OK == ctrl_state_polling_fun(pudev, puhost, pustate)) { - /* save configuration descriptor for class parsing usage */ - for (; index < puhost->device.cfg_desc.wTotalLength; index ++) { - usbh_cfg_desc[index] = pudev->host.rx_buffer[index]; - } - - /* commands successfully sent and response received */ - usbh_cfg_desc_parse (&puhost->device.cfg_desc, - puhost->device.itf_desc, - puhost->device.ep_desc, - pudev->host.rx_buffer, - puhost->device.cfg_desc.wTotalLength); - - /* User callback for configuration descriptors available */ - puhost->usr_cb->configuration_desc_available(&puhost->device.cfg_desc, - puhost->device.itf_desc, - puhost->device.ep_desc[0]); - - scd_event_handle(pudev, - puhost, - pustate, - ENUN_EVENT_GET_MFC_STRING_DESC, - pustate->usbh_current_state); - } -} - -/*! - \brief the handle function of ENUM_GET_MFC_STRING_DESC state - \param[in] pudev: pointer to USB device - \param[in] puhost: pointer to USB host - \param[in] pustate: pointer to USB state driver - \param[out] none - \retval none -*/ -static void enum_get_mfc_string_desc_handle (usb_core_handle_struct *pudev, - usbh_host_struct *puhost, - usbh_state_handle_struct *pustate) -{ - puhost->usbh_backup_state.enum_backup_state = ENUM_GET_MFC_STRING_DESC; - - if (0U != puhost->device.dev_desc.iManufacturer) { - if(CTRL_IDLE == puhost->usbh_backup_state.ctrl_backup_state) { - usbh_enum_desc_get(pudev, - puhost, - pudev->host.rx_buffer, - USB_REQTYPE_DEVICE | USB_STANDARD_REQ, - USB_STRDESC | puhost->device.dev_desc.iManufacturer, - 0xffU); - } - - if (USBH_OK == ctrl_state_polling_fun(pudev, puhost, pustate)) { - usbh_string_desc_parse(pudev->host.rx_buffer, local_buffer, 0xffU); - puhost->usr_cb->manufacturer_string(local_buffer); - - scd_event_handle(pudev, - puhost, - pustate, - ENUN_EVENT_GET_PRODUCT_STRING_DESC, - pustate->usbh_current_state); - } - } else { - puhost->usr_cb->manufacturer_string("N/A"); - scd_state_move((usbh_state_handle_struct *)pustate, ENUM_GET_PRODUCT_STRING_DESC); - } -} - -/*! - \brief the handle function of ENUM_GET_PRODUCT_STRING_DESC state - \param[in] pudev: pointer to USB device - \param[in] puhost: pointer to USB host - \param[in] pustate: pointer to USB state driver - \param[out] none - \retval none -*/ -static void enum_get_product_string_desc_handle (usb_core_handle_struct *pudev, - usbh_host_struct *puhost, - usbh_state_handle_struct *pustate) -{ - puhost->usbh_backup_state.enum_backup_state = ENUM_GET_PRODUCT_STRING_DESC; - - if (0U != puhost->device.dev_desc.iProduct) { - if (CTRL_IDLE == puhost->usbh_backup_state.ctrl_backup_state) { - usbh_enum_desc_get(pudev, - puhost, - pudev->host.rx_buffer, - USB_REQTYPE_DEVICE | USB_STANDARD_REQ, - USB_STRDESC | puhost->device.dev_desc.iProduct, - 0xffU); - } - - if (USBH_OK == ctrl_state_polling_fun(pudev, puhost, pustate)) { - usbh_string_desc_parse(pudev->host.rx_buffer, local_buffer, 0xffU); - - /* User callback for Product string */ - puhost->usr_cb->product_string(local_buffer); - - scd_event_handle(pudev, - puhost, - pustate, - ENUN_EVENT_GET_SERIALNUM_STRING_DESC, - pustate->usbh_current_state); - } - - } else { - puhost->usr_cb->product_string("N/A"); - scd_event_handle(pudev, - puhost, - pustate, - ENUN_EVENT_GET_SERIALNUM_STRING_DESC, - pustate->usbh_current_state); - } -} - -/*! - \brief the handle function of ENUM_GET_SERIALNUM_STRING_DESC state - \param[in] pudev: pointer to USB device - \param[in] puhost: pointer to USB host - \param[in] pustate: pointer to USB state driver - \param[out] none - \retval none -*/ -static void enum_get_serialnum_string_desc_handle (usb_core_handle_struct *pudev, - usbh_host_struct *puhost, - usbh_state_handle_struct *pustate) -{ - puhost->usbh_backup_state.enum_backup_state = ENUM_GET_SERIALNUM_STRING_DESC; - - if (0U != puhost->device.dev_desc.iSerialNumber) { - if (CTRL_IDLE == puhost->usbh_backup_state.ctrl_backup_state) { - usbh_enum_desc_get(pudev, - puhost, - pudev->host.rx_buffer, - USB_REQTYPE_DEVICE | USB_STANDARD_REQ, - USB_STRDESC | puhost->device.dev_desc.iSerialNumber, - 0xffU); - } - - if (USBH_OK == ctrl_state_polling_fun(pudev, puhost, pustate)){ - usbh_string_desc_parse(pudev->host.rx_buffer, local_buffer, 0xffU); - - /* user callback for product string */ - puhost->usr_cb->serial_num_string(local_buffer); - scd_event_handle(pudev, - puhost, - pustate, - ENUN_EVENT_SET_CONFIGURATION, - pustate->usbh_current_state); - } - } else { - puhost->usr_cb->serial_num_string("N/A"); - scd_event_handle(pudev, - puhost, - pustate, - ENUN_EVENT_SET_CONFIGURATION, - pustate->usbh_current_state); - } -} - -/*! - \brief the handle function of ENUM_SET_CONFIGURATION state - \param[in] pudev: pointer to USB device - \param[in] puhost: pointer to USB host - \param[in] pustate: pointer to USB state driver - \param[out] none - \retval none -*/ -static void enum_set_configuration_handle (usb_core_handle_struct *pudev, - usbh_host_struct *puhost, - usbh_state_handle_struct *pustate) -{ - puhost->usbh_backup_state.enum_backup_state = ENUM_SET_CONFIGURATION; - - if (CTRL_IDLE == puhost->usbh_backup_state.ctrl_backup_state ) { - usbh_enum_cfg_set(pudev, puhost, (uint16_t)puhost->device.cfg_desc.bConfigurationValue); - } - - if (USBH_OK == ctrl_state_polling_fun(pudev, puhost, pustate)) { - scd_event_handle(pudev, - puhost, - pustate, - ENUN_EVENT_DEV_CONFIGURED, - pustate->usbh_current_state); - } -} - -/*! - \brief the handle function of ENUM_DEV_CONFIGURED state - \param[in] pudev: pointer to USB device - \param[in] puhost: pointer to USB host - \param[in] pustate: pointer to USB state driver - \param[out] none - \retval none -*/ -static void enum_dev_configured_handle (usb_core_handle_struct *pudev, - usbh_host_struct *puhost, - usbh_state_handle_struct *pustate) -{ - puhost->usbh_backup_state.enum_backup_state = ENUM_DEV_CONFIGURED; - scd_event_handle(pudev, puhost, pustate, GO_TO_UP_STATE_EVENT, pustate->usbh_current_state); -} - -/*! - \brief get descriptor in usb host enumeration stage - \param[in] pudev: pointer to USB device - \param[in] puhost: pointer to USB host - \param[in] buf: buffer to store the descriptor - \param[in] ReqType: descriptor type - \param[in] ValueIdx: wValue for the GetDescriptr request - \param[in] Len: length of the descriptor - \param[out] none - \retval none -*/ -void usbh_enum_desc_get(usb_core_handle_struct *pudev, - usbh_host_struct *puhost, - uint8_t *buf, - uint8_t req_type, - uint16_t value_idx, - uint16_t len) -{ - usb_setup_union *pSetup = &(puhost->control.setup); - - pSetup->b.bmRequestType = USB_DIR_IN | req_type; - pSetup->b.bRequest = USBREQ_GET_DESCRIPTOR; - pSetup->b.wValue = value_idx; - - if (USB_STRDESC == (value_idx & 0xff00U)){ - pSetup->b.wIndex = 0x0409U; - } else { - pSetup->b.wIndex = 0U; - } - - pSetup->b.wLength = len; - - puhost->control.buff = buf; - puhost->control.length = len; - -} - -/*! - \brief set address in usb host enumeration stage - \param[in] pudev: pointer to USB device - \param[in] puhost: pointer to USB host - \param[in] device_address: the device address - \param[out] none - \retval none -*/ -void usbh_enum_addr_set(usb_core_handle_struct *pudev, - usbh_host_struct *puhost, - uint8_t device_address) -{ - usb_setup_union *p_setup = &(puhost->control.setup); - - p_setup->b.bmRequestType = USB_DIR_OUT | USB_REQTYPE_DEVICE | USB_STANDARD_REQ; - p_setup->b.bRequest = USBREQ_SET_ADDRESS; - p_setup->b.wValue = (uint16_t)device_address; - p_setup->b.wIndex = 0U; - p_setup->b.wLength = 0U; - puhost->control.buff = 0U; - puhost->control.length = 0U; -} - -/*! - \brief set configuration in usb host enumeration stage - \param[in] pudev: pointer to USB device - \param[in] puhost: pointer to USB host - \param[in] cfg_idx: the index of the configuration - \param[out] none - \retval none -*/ -void usbh_enum_cfg_set(usb_core_handle_struct *pudev, - usbh_host_struct *puhost, - uint16_t cfg_idx) -{ - usb_setup_union *p_setup = &(puhost->control.setup); - - p_setup->b.bmRequestType = USB_DIR_OUT | USB_REQTYPE_DEVICE | USB_STANDARD_REQ; - p_setup->b.bRequest = USBREQ_SET_CONFIGURATION; - p_setup->b.wValue = cfg_idx; - p_setup->b.wIndex = 0U; - p_setup->b.wLength = 0U; - puhost->control.buff = 0; - puhost->control.length = 0U; -} - -/*! - \brief parse the device descriptor - \param[in] dev_desc: device_descriptor destinaton address - \param[in] buf: buffer where the source descriptor is available - \param[in] len: length of the descriptor - \param[out] none - \retval none -*/ -void usbh_device_desc_parse (usb_descriptor_device_struct *dev_desc, uint8_t *buf, uint16_t len) -{ - dev_desc->Header.bLength = *(uint8_t *)(buf + 0); - dev_desc->Header.bDescriptorType = *(uint8_t *)(buf + 1); - dev_desc->bcdUSB = SWAPBYTE(buf + 2); - dev_desc->bDeviceClass = *(uint8_t *)(buf + 4); - dev_desc->bDeviceSubClass = *(uint8_t *)(buf + 5); - dev_desc->bDeviceProtocol = *(uint8_t *)(buf + 6); - dev_desc->bMaxPacketSize0 = *(uint8_t *)(buf + 7); - - if (len > 8U){ - /* for 1st time after device connection, host may issue only 8 bytes for device descriptor length */ - dev_desc->idVendor = SWAPBYTE(buf + 8); - dev_desc->idProduct = SWAPBYTE(buf + 10); - dev_desc->bcdDevice = SWAPBYTE(buf + 12); - dev_desc->iManufacturer = *(uint8_t *)(buf + 14); - dev_desc->iProduct = *(uint8_t *)(buf + 15); - dev_desc->iSerialNumber = *(uint8_t *)(buf + 16); - dev_desc->bNumberConfigurations = *(uint8_t *)(buf + 17); - } -} - -/*! - \brief parse the configuration descriptor - \param[in] cfg_desc: configuration descriptor address - \param[in] itf_desc: interface descriptor address - \param[in] ep_desc: endpoint descriptor address - \param[in] buf: buffer where the source descriptor is available - \param[in] len: length of the descriptor - \param[out] none - \retval none -*/ -void usbh_cfg_desc_parse (usb_descriptor_configuration_struct *cfg_desc, - usb_descriptor_interface_struct *itf_desc, - usb_descriptor_endpoint_struct ep_desc[][USBH_MAX_EP_NUM], - uint8_t *buf, - uint16_t len) -{ - usb_descriptor_interface_struct *pitf = NULL; - usb_descriptor_interface_struct temp_pitf; - usb_descriptor_endpoint_struct *pep = NULL; - usb_descriptor_header_struct *pdesc = (usb_descriptor_header_struct *)buf; - - uint8_t itf_ix = 0U; - uint8_t ep_ix = 0U; - uint16_t ptr = 0U; - static uint8_t prev_itf = 0U; - static uint16_t prev_ep_size = 0U; - - /* parse configuration descriptor */ - cfg_desc->Header.bLength = *(uint8_t *)(buf + 0); - cfg_desc->Header.bDescriptorType = *(uint8_t *)(buf + 1); - cfg_desc->wTotalLength = SWAPBYTE(buf + 2); - cfg_desc->bNumInterfaces = *(uint8_t *)(buf + 4); - cfg_desc->bConfigurationValue = *(uint8_t *)(buf + 5); - cfg_desc->iConfiguration = *(uint8_t *)(buf + 6); - cfg_desc->bmAttributes = *(uint8_t *)(buf + 7); - cfg_desc->bMaxPower = *(uint8_t *)(buf + 8); - - if (len > USB_CFGDESC_SIZE) { - ptr = USB_CFG_DESC_LEN; - - if (cfg_desc->bNumInterfaces <= USBH_MAX_INTERFACES_NUM) { - pitf = (usb_descriptor_interface_struct *)0; - - for (; ptr < cfg_desc->wTotalLength; ) { - pdesc = usbh_next_desc_get((uint8_t *)pdesc, &ptr); - - if (USB_DESCTYPE_INTERFACE == pdesc->bDescriptorType) { - itf_ix = *((uint8_t *)pdesc + 2U); - pitf = &itf_desc[itf_ix]; - - if (*((uint8_t *)pdesc + 3U) < 3U) { - usbh_interface_desc_parse (&temp_pitf, (uint8_t *)pdesc); - - /* parse endpoint descriptors relative to the current interface */ - if (temp_pitf.bNumEndpoints <= USBH_MAX_EP_NUM) { - for (ep_ix = 0U; ep_ix < temp_pitf.bNumEndpoints;) { - pdesc = usbh_next_desc_get((void* )pdesc, &ptr); - - if (USB_DESCTYPE_ENDPOINT == pdesc->bDescriptorType) { - pep = &ep_desc[itf_ix][ep_ix]; - - if (prev_itf != itf_ix) { - prev_itf = itf_ix; - usbh_interface_desc_parse (pitf, (uint8_t *)&temp_pitf); - } else { - if (prev_ep_size > SWAPBYTE((uint8_t *)pdesc + 4)) { - break; - } else { - usbh_interface_desc_parse (pitf, (uint8_t *)&temp_pitf); - } - } - - usbh_endpoint_desc_parse (pep, (uint8_t *)pdesc); - prev_ep_size = SWAPBYTE((uint8_t *)pdesc + 4); - ep_ix++; - } - } - } - } - } - } - } - - prev_ep_size = 0U; - prev_itf = 0U; - } -} - -/*! - \brief parse the interface descriptor - \param[in] itf_desc: interface descriptor destination - \param[in] buf: buffer where the descriptor data is available - \param[out] none - \retval none -*/ -void usbh_interface_desc_parse (usb_descriptor_interface_struct *itf_desc, uint8_t *buf) -{ - itf_desc->Header.bLength = *(uint8_t *)(buf + 0); - itf_desc->Header.bDescriptorType = *(uint8_t *)(buf + 1); - itf_desc->bInterfaceNumber = *(uint8_t *)(buf + 2); - itf_desc->bAlternateSetting = *(uint8_t *)(buf + 3); - itf_desc->bNumEndpoints = *(uint8_t *)(buf + 4); - itf_desc->bInterfaceClass = *(uint8_t *)(buf + 5); - itf_desc->bInterfaceSubClass = *(uint8_t *)(buf + 6); - itf_desc->bInterfaceProtocol = *(uint8_t *)(buf + 7); - itf_desc->iInterface = *(uint8_t *)(buf + 8); -} - -/*! - \brief parse the endpoint descriptor - \param[in] ep_desc: endpoint descriptor destination address - \param[in] buf: buffer where the parsed descriptor stored - \param[out] none - \retval none -*/ -void usbh_endpoint_desc_parse (usb_descriptor_endpoint_struct *ep_desc, uint8_t *buf) -{ - ep_desc->Header.bLength = *(uint8_t *)(buf + 0); - ep_desc->Header.bDescriptorType = *(uint8_t *)(buf + 1); - ep_desc->bEndpointAddress = *(uint8_t *)(buf + 2); - ep_desc->bmAttributes = *(uint8_t *)(buf + 3); - ep_desc->wMaxPacketSize = SWAPBYTE(buf + 4); - ep_desc->bInterval = *(uint8_t *)(buf + 6); -} - -/*! - \brief parse the string descriptor - \param[in] psrc: source pointer containing the descriptor data - \param[in] pdest: destination address pointer - \param[in] len: length of the descriptor - \param[out] none - \retval none -*/ -void usbh_string_desc_parse (uint8_t* psrc, uint8_t* pdest, uint16_t len) -{ - uint16_t strlength; - uint16_t idx; - - /* the unicode string descriptor is not null-terminated. the string length is - computed by substracting two from the value of the first byte of the descriptor. - */ - - /* check which is lower size, the size of string or the length of bytes read from the device */ - - if (USB_DESCTYPE_STRING == psrc[1]){ - /* make sure the descriptor is string type */ - - /* psrc[0] contains size of descriptor, subtract 2 to get the length of string */ - strlength = ((((uint16_t)psrc[0] - 2U) <= len) ? ((uint16_t)psrc[0] - 2U) : len); - psrc += 2; /* adjust the offset ignoring the string len and descriptor type */ - - for (idx = 0U; idx < strlength; idx += 2U) { - /* copy only the string and ignore the unicode id, hence add the src */ - *pdest = psrc[idx]; - pdest++; - } - - *pdest = 0U; /* mark end of string */ - } -} - -/*! - \brief get the next descriptor header - \param[in] pbuf: pointer to buffer where the cfg descriptor is available - \param[in] ptr: data popinter inside the configuration descriptor - \param[out] none - \retval next descriptor header -*/ -usb_descriptor_header_struct *usbh_next_desc_get (uint8_t *pbuf, uint16_t *ptr) -{ - uint8_t len = ((usb_descriptor_header_struct *)pbuf)->bLength; - - usb_descriptor_header_struct *pnext; - - *ptr += len; - - pnext = (usb_descriptor_header_struct *)((uint8_t *)pbuf + len); - - return(pnext); -} - diff --git a/bsp/gd32450z-eval/Libraries/SConscript b/bsp/gd32450z-eval/Libraries/SConscript index 75df263b3e..e9d6e45aae 100644 --- a/bsp/gd32450z-eval/Libraries/SConscript +++ b/bsp/gd32450z-eval/Libraries/SConscript @@ -21,12 +21,12 @@ path = [ cwd + '/CMSIS/GD/GD32F4xx/Include', cwd + '/CMSIS', cwd + '/GD32F4xx_standard_peripheral/Include',] - + if GetDepend(['RT_USING_BSP_USB']): path += [cwd + '/GD32F4xx_usb_driver/Include'] src += [cwd + '/GD32F4xx_usb_driver/Source'] -CPPDEFINES = ['USE_STDPERIPH_DRIVER', 'GD32F4XX'] +CPPDEFINES = ['USE_STDPERIPH_DRIVER'] group = DefineGroup('Libraries', src, depend = [''], CPPPATH = path, CPPDEFINES = CPPDEFINES) diff --git a/bsp/gd32450z-eval/drivers/drv_usart.c b/bsp/gd32450z-eval/drivers/drv_usart.c index fa691a42b9..423befbc93 100644 --- a/bsp/gd32450z-eval/drivers/drv_usart.c +++ b/bsp/gd32450z-eval/drivers/drv_usart.c @@ -377,14 +377,14 @@ static rt_err_t gd32_control(struct rt_serial_device *serial, int cmd, void *arg /* disable rx irq */ NVIC_DisableIRQ(uart->irqn); /* disable interrupt */ - usart_interrupt_disable(uart->uart_periph, USART_INTEN_RBNEIE); + usart_interrupt_disable(uart->uart_periph, USART_INT_RBNE); break; case RT_DEVICE_CTRL_SET_INT: /* enable rx irq */ NVIC_EnableIRQ(uart->irqn); /* enable interrupt */ - usart_interrupt_enable(uart->uart_periph, USART_INTEN_RBNEIE); + usart_interrupt_enable(uart->uart_periph, USART_INT_RBNE); break; } @@ -430,7 +430,7 @@ static void uart_isr(struct rt_serial_device *serial) RT_ASSERT(uart != RT_NULL); /* UART in mode Receiver -------------------------------------------------*/ - if ((usart_interrupt_flag_get(uart->uart_periph, USART_INT_RBNEIE) != RESET) && + if ((usart_interrupt_flag_get(uart->uart_periph, USART_INT_FLAG_RBNE) != RESET) && (usart_flag_get(uart->uart_periph, USART_FLAG_RBNE) != RESET)) { rt_hw_serial_isr(serial, RT_SERIAL_EVENT_RX_IND); diff --git a/bsp/gd32450z-eval/rtconfig.py b/bsp/gd32450z-eval/rtconfig.py index f137cf5a65..1f01ffe88b 100644 --- a/bsp/gd32450z-eval/rtconfig.py +++ b/bsp/gd32450z-eval/rtconfig.py @@ -38,7 +38,7 @@ if PLATFORM == 'gcc': OBJDUMP = PREFIX + 'objdump' OBJCPY = PREFIX + 'objcopy' - DEVICE = ' -mcpu=cortex-m4 -mthumb -mfpu=fpv4-sp-d16 -mfloat-abi=hard -ffunction-sections -fdata-sections' + DEVICE = ' -mcpu=cortex-m4 -mthumb -mfpu=fpv4-sp-d16 -mfloat-abi=hard -ffunction-sections -fdata-sections -DGD32F450' CFLAGS = DEVICE + ' -Dgcc' # -D' + PART_TYPE AFLAGS = ' -c' + DEVICE + ' -x assembler-with-cpp -Wa,-mimplicit-it=thumb ' LFLAGS = DEVICE + ' -Wl,--gc-sections,-Map=rtthread-gd32.map,-cref,-u,Reset_Handler -T gd32_rom.ld' |