diff options
| -rw-r--r-- | bsp/raspberry-pi/raspi4-32/.config | 12 | ||||
| -rw-r--r-- | bsp/raspberry-pi/raspi4-32/driver/Kconfig | 19 | ||||
| -rw-r--r-- | bsp/raspberry-pi/raspi4-32/driver/SConscript | 12 | ||||
| -rw-r--r-- | bsp/raspberry-pi/raspi4-32/driver/drv_gpio.c | 53 | ||||
| -rw-r--r-- | bsp/raspberry-pi/raspi4-32/driver/drv_gpio.h | 1 | ||||
| -rw-r--r-- | bsp/raspberry-pi/raspi4-32/driver/drv_spi.c | 296 | ||||
| -rw-r--r-- | bsp/raspberry-pi/raspi4-32/driver/drv_spi.h | 87 | ||||
| -rw-r--r-- | bsp/raspberry-pi/raspi4-32/driver/raspi4.h | 12 | ||||
| -rw-r--r-- | bsp/raspberry-pi/raspi4-32/rtconfig.h | 4 |
9 files changed, 470 insertions, 26 deletions
diff --git a/bsp/raspberry-pi/raspi4-32/.config b/bsp/raspberry-pi/raspi4-32/.config index 6f7fc20100..e0db6a3e95 100644 --- a/bsp/raspberry-pi/raspi4-32/.config +++ b/bsp/raspberry-pi/raspi4-32/.config @@ -134,13 +134,19 @@ CONFIG_RT_SERIAL_RB_BUFSZ=64 # CONFIG_RT_USING_I2C is not set CONFIG_RT_USING_PIN=y # CONFIG_RT_USING_ADC is not set +# CONFIG_RT_USING_DAC is not set # CONFIG_RT_USING_PWM is not set # CONFIG_RT_USING_MTD_NOR is not set # CONFIG_RT_USING_MTD_NAND is not set # CONFIG_RT_USING_PM is not set # CONFIG_RT_USING_RTC is not set # CONFIG_RT_USING_SDIO is not set -# CONFIG_RT_USING_SPI is not set +CONFIG_RT_USING_SPI=y +# CONFIG_RT_USING_QSPI is not set +# CONFIG_RT_USING_SPI_MSD is not set +# CONFIG_RT_USING_SFUD is not set +# CONFIG_RT_USING_ENC28J60 is not set +# CONFIG_RT_USING_SPI_WIFI is not set # CONFIG_RT_USING_WDT is not set # CONFIG_RT_USING_AUDIO is not set # CONFIG_RT_USING_SENSOR is not set @@ -475,6 +481,10 @@ CONFIG_BSP_USING_GIC=y CONFIG_BSP_USING_GIC400=y # CONFIG_BSP_USING_GIC500 is not set CONFIG_BSP_USING_PIN=y +CONFIG_BSP_USING_SPI=y +CONFIG_BSP_USING_SPI0_BUS=y +CONFIG_BSP_USING_SPI0_DEVICE0=y +# CONFIG_BSP_USING_SPI0_DEVICE1 is not set CONFIG_BSP_USING_CORETIMER=y # CONFIG_BSP_USING_SYSTIMER is not set # CONFIG_BSP_USING_WDT is not set diff --git a/bsp/raspberry-pi/raspi4-32/driver/Kconfig b/bsp/raspberry-pi/raspi4-32/driver/Kconfig index fb750ff60e..5dca313513 100644 --- a/bsp/raspberry-pi/raspi4-32/driver/Kconfig +++ b/bsp/raspberry-pi/raspi4-32/driver/Kconfig @@ -50,6 +50,25 @@ menu "Hardware Drivers Config" select RT_USING_PIN default y + menuconfig BSP_USING_SPI + bool "Enable SPI" + select RT_USING_SPI + default n + + if BSP_USING_SPI + config BSP_USING_SPI0_BUS + bool "Enable SPI0 BUS" + default n + config BSP_USING_SPI0_DEVICE0 + bool "Enable SPI0 DEVICE0" + select BSP_USING_SPI0_BUS + default n + config BSP_USING_SPI0_DEVICE1 + bool "Enable SPI0 DEVICE1" + select BSP_USING_SPI0_BUS + default n + endif + config BSP_USING_CORETIMER bool "Using core timer" select RT_USING_CORETIMER diff --git a/bsp/raspberry-pi/raspi4-32/driver/SConscript b/bsp/raspberry-pi/raspi4-32/driver/SConscript index 533df8ac31..64c764c1b3 100644 --- a/bsp/raspberry-pi/raspi4-32/driver/SConscript +++ b/bsp/raspberry-pi/raspi4-32/driver/SConscript @@ -4,6 +4,16 @@ cwd = GetCurrentDir() src = Glob('*.c') + Glob('*.cpp') CPPPATH = [cwd, str(Dir('#'))] -group = DefineGroup('Applications', src, depend = [''], CPPPATH = CPPPATH) +group = DefineGroup('driver', src, depend = [''], CPPPATH = CPPPATH) + +# build for sub-directory +list = os.listdir(cwd) +objs = [] + +for d in list: + path = os.path.join(cwd, d) + if os.path.isfile(os.path.join(path, 'SConscript')): + objs = objs + SConscript(os.path.join(d, 'SConscript')) +group = group + objs Return('group') diff --git a/bsp/raspberry-pi/raspi4-32/driver/drv_gpio.c b/bsp/raspberry-pi/raspi4-32/driver/drv_gpio.c index e342032d55..b45fb8574f 100644 --- a/bsp/raspberry-pi/raspi4-32/driver/drv_gpio.c +++ b/bsp/raspberry-pi/raspi4-32/driver/drv_gpio.c @@ -120,6 +120,34 @@ void prev_raspi_pin_mode(GPIO_PIN pin, GPIO_FUNC mode) raspi_set_pin_state(fselnum, gpfsel); } +void prev_raspi_pin_write(GPIO_PIN pin, int pin_value) +{ + uint32_t num = pin / 32; + + if(num == 0) + { + if(pin_value == 1) + { + GPIO_REG_GPSET0(GPIO_BASE) = 1 << (pin % 32); + } + else + { + GPIO_REG_GPCLR0(GPIO_BASE) = 1 << (pin % 32); + } + } + else + { + if(pin_value == 1) + { + GPIO_REG_GPSET1(GPIO_BASE) = 1 << (pin % 32); + } + else + { + GPIO_REG_GPCLR1(GPIO_BASE) = 1 << (pin % 32); + } + } +} + static void raspi_pin_mode(struct rt_device *dev, rt_base_t pin, rt_base_t mode) { GPIO_FUNC raspi_mode = OUTPUT; @@ -149,30 +177,7 @@ static void raspi_pin_mode(struct rt_device *dev, rt_base_t pin, rt_base_t mode) static void raspi_pin_write(struct rt_device *dev, rt_base_t pin, rt_base_t value) { - uint32_t num = pin / 32; - - if(num == 0) - { - if(value == 0) - { - GPIO_REG_GPSET0(GPIO_BASE) = 1 << (pin % 32); - } - else - { - GPIO_REG_GPCLR0(GPIO_BASE) = 1 << (pin % 32); - } - } - else - { - if(value == 0) - { - GPIO_REG_GPSET1(GPIO_BASE) = 1 << (pin % 32); - } - else - { - GPIO_REG_GPCLR1(GPIO_BASE) = 1 << (pin % 32); - } - } + prev_raspi_pin_write(pin, value); } static int raspi_pin_read(struct rt_device *device, rt_base_t pin) diff --git a/bsp/raspberry-pi/raspi4-32/driver/drv_gpio.h b/bsp/raspberry-pi/raspi4-32/driver/drv_gpio.h index 44fa0464fd..7594759f97 100644 --- a/bsp/raspberry-pi/raspi4-32/driver/drv_gpio.h +++ b/bsp/raspberry-pi/raspi4-32/driver/drv_gpio.h @@ -134,6 +134,7 @@ typedef enum { } GPIO_PUPD_FUNC; void prev_raspi_pin_mode(GPIO_PIN pin, GPIO_FUNC mode); +void prev_raspi_pin_write(GPIO_PIN pin, int pin_value); int rt_hw_gpio_init(void); #endif /* __DRV_GPIO_H__ */ diff --git a/bsp/raspberry-pi/raspi4-32/driver/drv_spi.c b/bsp/raspberry-pi/raspi4-32/driver/drv_spi.c new file mode 100644 index 0000000000..bbf64be95d --- /dev/null +++ b/bsp/raspberry-pi/raspi4-32/driver/drv_spi.c @@ -0,0 +1,296 @@ +/* + * Copyright (c) 2006-2020, RT-Thread Development Team + * + * SPDX-License-Identifier: Apache-2.0 + * + * Change Logs: + * Date Author Notes + * 2020-06-22 bigmagic first version + */ +#include <rtthread.h> +#include <rthw.h> +#include <rtdevice.h> + +#include "raspi4.h" +#include "drv_spi.h" + +#ifdef RT_USING_SPI + +#define RPI_CORE_CLK_HZ (250000000) +#define BSP_SPI_MAX_HZ (30* 1000 *1000) +#define SPITIMEOUT 0x0FFF + +static rt_uint8_t raspi_byte_reverse_table[] = +{ + 0x00, 0x80, 0x40, 0xc0, 0x20, 0xa0, 0x60, 0xe0, + 0x10, 0x90, 0x50, 0xd0, 0x30, 0xb0, 0x70, 0xf0, + 0x08, 0x88, 0x48, 0xc8, 0x28, 0xa8, 0x68, 0xe8, + 0x18, 0x98, 0x58, 0xd8, 0x38, 0xb8, 0x78, 0xf8, + 0x04, 0x84, 0x44, 0xc4, 0x24, 0xa4, 0x64, 0xe4, + 0x14, 0x94, 0x54, 0xd4, 0x34, 0xb4, 0x74, 0xf4, + 0x0c, 0x8c, 0x4c, 0xcc, 0x2c, 0xac, 0x6c, 0xec, + 0x1c, 0x9c, 0x5c, 0xdc, 0x3c, 0xbc, 0x7c, 0xfc, + 0x02, 0x82, 0x42, 0xc2, 0x22, 0xa2, 0x62, 0xe2, + 0x12, 0x92, 0x52, 0xd2, 0x32, 0xb2, 0x72, 0xf2, + 0x0a, 0x8a, 0x4a, 0xca, 0x2a, 0xaa, 0x6a, 0xea, + 0x1a, 0x9a, 0x5a, 0xda, 0x3a, 0xba, 0x7a, 0xfa, + 0x06, 0x86, 0x46, 0xc6, 0x26, 0xa6, 0x66, 0xe6, + 0x16, 0x96, 0x56, 0xd6, 0x36, 0xb6, 0x76, 0xf6, + 0x0e, 0x8e, 0x4e, 0xce, 0x2e, 0xae, 0x6e, 0xee, + 0x1e, 0x9e, 0x5e, 0xde, 0x3e, 0xbe, 0x7e, 0xfe, + 0x01, 0x81, 0x41, 0xc1, 0x21, 0xa1, 0x61, 0xe1, + 0x11, 0x91, 0x51, 0xd1, 0x31, 0xb1, 0x71, 0xf1, + 0x09, 0x89, 0x49, 0xc9, 0x29, 0xa9, 0x69, 0xe9, + 0x19, 0x99, 0x59, 0xd9, 0x39, 0xb9, 0x79, 0xf9, + 0x05, 0x85, 0x45, 0xc5, 0x25, 0xa5, 0x65, 0xe5, + 0x15, 0x95, 0x55, 0xd5, 0x35, 0xb5, 0x75, 0xf5, + 0x0d, 0x8d, 0x4d, 0xcd, 0x2d, 0xad, 0x6d, 0xed, + 0x1d, 0x9d, 0x5d, 0xdd, 0x3d, 0xbd, 0x7d, 0xfd, + 0x03, 0x83, 0x43, 0xc3, 0x23, 0xa3, 0x63, 0xe3, + 0x13, 0x93, 0x53, 0xd3, 0x33, 0xb3, 0x73, 0xf3, + 0x0b, 0x8b, 0x4b, 0xcb, 0x2b, 0xab, 0x6b, 0xeb, + 0x1b, 0x9b, 0x5b, 0xdb, 0x3b, 0xbb, 0x7b, 0xfb, + 0x07, 0x87, 0x47, 0xc7, 0x27, 0xa7, 0x67, 0xe7, + 0x17, 0x97, 0x57, 0xd7, 0x37, 0xb7, 0x77, 0xf7, + 0x0f, 0x8f, 0x4f, 0xcf, 0x2f, 0xaf, 0x6f, 0xef, + 0x1f, 0x9f, 0x5f, 0xdf, 0x3f, 0xbf, 0x7f, 0xff +}; + +#if defined (BSP_USING_SPI0_BUS) +#define SPI0_BUS_NAME "spi0" +#define SPI0_DEVICE0_NAME "spi0.0" +#define SPI0_DEVICE1_NAME "spi0.1" + +struct rt_spi_bus spi0_bus; + +#if defined (BSP_USING_SPI0_DEVICE0) +static struct rt_spi_device spi0_device0; +#endif + +#if defined (BSP_USING_SPI0_DEVICE1) +static struct rt_spi_device spi0_device1; +#endif +#endif + +static rt_err_t raspi_spi_configure(struct rt_spi_device *device, struct rt_spi_configuration *cfg) +{ + RT_ASSERT(cfg != RT_NULL); + RT_ASSERT(device != RT_NULL); + rt_uint16_t divider; + struct raspi_spi_device* hw_config = (struct raspi_spi_device *)(device->parent.user_data); + struct raspi_spi_hw_config *hwcfg = (struct raspi_spi_hw_config *)hw_config->spi_hw_config; + // spi clear fifo + SPI_REG_CS(hwcfg->hw_base) = (SPI_CS_CLEAR_TX | SPI_CS_CLEAR_RX); + if(cfg->mode & RT_SPI_CPOL) + { + SPI_REG_CS(hwcfg->hw_base) |= SPI_CS_CPOL; + } + + if(cfg->mode & RT_SPI_CPHA) + { + SPI_REG_CS(hwcfg->hw_base) |= SPI_CS_CPHA; + } + + if(cfg->mode & RT_SPI_CS_HIGH) + { + SPI_REG_CS(hwcfg->hw_base) |= SPI_CS_CSPOL_HIGH; + } + + //set clk + if (cfg->max_hz > BSP_SPI_MAX_HZ) + cfg->max_hz = BSP_SPI_MAX_HZ; + + divider = (rt_uint16_t) ((rt_uint32_t) RPI_CORE_CLK_HZ / cfg->max_hz); + divider &= 0xFFFE; + + SPI_REG_CLK(hwcfg->hw_base) = divider; + + return RT_EOK; +} + +rt_uint8_t correct_order(rt_uint8_t b, rt_uint8_t flag) +{ + if (flag) + return raspi_byte_reverse_table[b];//reverse + else + return b; +} + +static rt_err_t spi_transfernb(struct raspi_spi_hw_config *hwcfg, rt_uint8_t* tbuf, rt_uint8_t* rbuf, rt_uint32_t len, rt_uint8_t flag) +{ + rt_uint32_t TXCnt=0; + rt_uint32_t RXCnt=0; + + /* Clear TX and RX fifos */ + SPI_REG_CS(hwcfg->hw_base) |= (SPI_CS_CLEAR_TX | SPI_CS_CLEAR_RX); + + /* Set TA = 1 */ + SPI_REG_CS(hwcfg->hw_base) |= SPI_CS_TA; + + /* Use the FIFO's to reduce the interbyte times */ + while ((TXCnt < len) || (RXCnt < len)) + { + /* TX fifo not full, so add some more bytes */ + while (((SPI_REG_CS(hwcfg->hw_base) & SPI_CS_TX_DATA)) && (TXCnt < len)) + { + SPI_REG_FIFO(hwcfg->hw_base) = correct_order(tbuf[TXCnt],flag); + TXCnt++; + } + /* Rx fifo not empty, so get the next received bytes */ + while (((SPI_REG_CS(hwcfg->hw_base) & SPI_CS_RX_DATA)) && (RXCnt < len)) + { + rbuf[RXCnt] = correct_order(SPI_REG_FIFO(hwcfg->hw_base), flag); + RXCnt++; + } + } + /* Wait for DONE to be set */ + while (!(SPI_REG_CS(hwcfg->hw_base) & SPI_CS_DONE)); + /* Set TA = 0, and also set the barrier */ + SPI_REG_CS(hwcfg->hw_base) |= (0 & SPI_CS_TA); + return RT_EOK; +} + +static rt_uint32_t raspi_spi_xfer(struct rt_spi_device *device, struct rt_spi_message *message) +{ + rt_err_t res; + rt_uint8_t flag; + RT_ASSERT(device != RT_NULL); + RT_ASSERT(device->bus != RT_NULL); + RT_ASSERT(device->parent.user_data != RT_NULL); + RT_ASSERT(message->send_buf != RT_NULL || message->recv_buf != RT_NULL); + + struct rt_spi_configuration config = device->config; + struct raspi_spi_device * hw_config = (struct raspi_spi_device *)device->parent.user_data; + GPIO_PIN cs_pin = (GPIO_PIN)hw_config->cs_pin; + struct raspi_spi_hw_config *hwcfg = (struct raspi_spi_hw_config *)hw_config->spi_hw_config; + + if (config.mode & RT_SPI_MSB) + { + flag = 0; + } + else + { + flag = 1; + } + + if (message->cs_take) + { + (config.mode & RT_SPI_CS_HIGH)?prev_raspi_pin_write(cs_pin, 1):prev_raspi_pin_write(cs_pin, 0); + } + + res = spi_transfernb(hwcfg, (rt_uint8_t *)message->send_buf, (rt_uint8_t *)message->recv_buf, (rt_int32_t)message->length, flag); + if (message->cs_release) + { + (config.mode & RT_SPI_CS_HIGH)?prev_raspi_pin_write(cs_pin, 0):prev_raspi_pin_write(cs_pin, 1); + } + if (res != RT_EOK) + return RT_ERROR; + + return message->length; +} + +rt_err_t raspi_spi_bus_attach_device(const char *bus_name, struct raspi_spi_device *device) +{ + rt_err_t ret; + RT_ASSERT(device != RT_NULL); + ret = rt_spi_bus_attach_device(device->spi_device, device->device_name, bus_name, (void *)(device)); + return ret; +} + +rt_err_t raspi_spi_hw_init(struct raspi_spi_hw_config *hwcfg) +{ + prev_raspi_pin_mode(hwcfg->sclk_pin, hwcfg->sclk_mode); + prev_raspi_pin_mode(hwcfg->miso_pin, hwcfg->miso_mode); + prev_raspi_pin_mode(hwcfg->mosi_pin, hwcfg->mosi_mode); +#if defined (BSP_USING_SPI0_DEVICE0) + prev_raspi_pin_mode(hwcfg->ce0_pin, hwcfg->ce0_mode); +#endif + +#if defined (BSP_USING_SPI0_DEVICE1) + prev_raspi_pin_mode(hwcfg->ce1_pin, hwcfg->ce1_mode); +#endif + //clear rx and tx + SPI_REG_CS(hwcfg->hw_base) = (SPI_CS_CLEAR_TX | SPI_CS_CLEAR_RX); + //enable chip select +#if defined (BSP_USING_SPI0_DEVICE0) + SPI_REG_CS(hwcfg->hw_base) |= SPI_CS_CHIP_SELECT_0; +#endif + +#if defined (BSP_USING_SPI0_DEVICE1) + SPI_REG_CS(hwcfg->hw_base) |= SPI_CS_CHIP_SELECT_1; +#endif + +#if defined (BSP_USING_SPI0_DEVICE0) && defined (BSP_USING_SPI0_DEVICE1) + HWREG32(SPI_REG_CS(hwcfg->hw_base)) |= (SPI_CS_CHIP_SELECT_0 | SPI_CS_CHIP_SELECT_1); +#endif + return RT_EOK; +} + +static struct rt_spi_ops raspi_spi_ops = +{ + .configure = raspi_spi_configure, + .xfer = raspi_spi_xfer +}; + +struct raspi_spi_hw_config raspi_spi0_hw = +{ + .spi_num = 0, + .sclk_pin = GPIO_PIN_11, + .sclk_mode = ALT0, + .mosi_pin = GPIO_PIN_10, + .mosi_mode = ALT0, + .miso_pin = GPIO_PIN_9, + .miso_mode = ALT0, + +#if defined (BSP_USING_SPI0_DEVICE0) + .ce0_pin = GPIO_PIN_8, + .ce0_mode = ALT0, +#endif + +#if defined (BSP_USING_SPI0_DEVICE1) + .ce1_pin = GPIO_PIN_7, + .ce1_mode = ALT0, +#endif + .hw_base = SPI_0_BASE, +}; +#endif + +#if defined (BSP_USING_SPI0_DEVICE0) +struct raspi_spi_device raspi_spi0_device0 = +{ + .device_name = SPI0_DEVICE0_NAME, + .spi_bus = &spi0_bus, + .spi_device = &spi0_device0, + .spi_hw_config = &raspi_spi0_hw, + .cs_pin = GPIO_PIN_8, +}; +#endif + +#if defined (BSP_USING_SPI0_DEVICE1) +struct raspi_spi_device raspi_spi0_device1 = +{ + .device_name = SPI0_DEVICE1_NAME, + .spi_bus = &spi0_bus, + .spi_device = &spi0_device1, + .cs_pin = GPIO_PIN_7, +}; +#endif + +int rt_hw_spi_init(void) +{ +#if defined (BSP_USING_SPI0_BUS) + raspi_spi_hw_init(&raspi_spi0_hw); + rt_spi_bus_register(&spi0_bus, SPI0_BUS_NAME, &raspi_spi_ops); + +#if defined (BSP_USING_SPI0_DEVICE0) + raspi_spi_bus_attach_device(SPI0_BUS_NAME, &raspi_spi0_device0); +#endif + +#if defined (BSP_USING_SPI0_DEVICE1) + raspi_spi_bus_attach_device(SPI0_BUS_NAME, &raspi_spi0_device1); +#endif +#endif + return RT_EOK; +} +INIT_DEVICE_EXPORT(rt_hw_spi_init); + diff --git a/bsp/raspberry-pi/raspi4-32/driver/drv_spi.h b/bsp/raspberry-pi/raspi4-32/driver/drv_spi.h new file mode 100644 index 0000000000..407913b886 --- /dev/null +++ b/bsp/raspberry-pi/raspi4-32/driver/drv_spi.h @@ -0,0 +1,87 @@ +/* + * Copyright (c) 2006-2020, RT-Thread Development Team + * + * SPDX-License-Identifier: Apache-2.0 + * + * Change Logs: + * Date Author Notes + * 2020-06-16 bigmagic first version + */ +#ifndef __DRV_SPI_H__ +#define __DRV_SPI_H__ + +#include "drv_gpio.h" + +#define SPI_REG_CS(BASE) HWREG32(BASE + 0x00) +#define SPI_REG_FIFO(BASE) HWREG32(BASE + 0x04) +#define SPI_REG_CLK(BASE) HWREG32(BASE + 0x08) +#define SPI_REG_DLEN(BASE) HWREG32(BASE + 0x0C) +#define SPI_REG_LTOH(BASE) HWREG32(BASE + 0x10) +#define SPI_REG_DC(BASE) HWREG32(BASE + 0x14) + +/* CS Register */ +#define SPI_CS_LOSSI_LONG_32BIT (1 << 25) +#define SPI_CS_LOSSI_DMA_MODE (1 << 24) +#define SPI_CS_CSPOL2 (1 << 23) +#define SPI_CS_CSPOL1 (1 << 22) +#define SPI_CS_CSPOL0 (1 << 21) +#define SPI_CS_RX_FIFO_FULL (1 << 20) +#define SPI_CS_RX_FIFO_3_QUARTER (1 << 19) +#define SPI_CS_TX_DATA (1 << 18) +#define SPI_CS_RX_DATA (1 << 17) +#define SPI_CS_DONE (1 << 16) +#define SPI_CS_LOSSI_EN (1 << 13) +#define SPI_CS_READ_EN (1 << 12) +#define SPI_CS_AUTO_CS (1 << 11) +#define SPI_CS_INTR_RXR (1 << 10) +#define SPI_CS_INTR_DONE (1 << 9) +#define SPI_CS_DMA_EN (1 << 8) +#define SPI_CS_TA (1 << 7) +#define SPI_CS_CSPOL_HIGH (1 << 6) +#define SPI_CS_CLEAR_RX (2 << 4) +#define SPI_CS_CLEAR_TX (1 << 4) +#define SPI_CS_CPOL (1 << 3) +#define SPI_CS_CPHA (1 << 2) +#define SPI_CS_CHIP_SELECT_2 (2 << 0) +#define SPI_CS_CHIP_SELECT_1 (1 << 0) +#define SPI_CS_CHIP_SELECT_0 (0 << 0) + +struct raspi_spi_hw_config +{ + rt_uint8_t spi_num; + GPIO_PIN sclk_pin; + GPIO_FUNC sclk_mode; + GPIO_PIN mosi_pin; + GPIO_FUNC mosi_mode; + GPIO_PIN miso_pin; + GPIO_FUNC miso_mode; +#if defined (BSP_USING_SPI0_DEVICE0) || defined (BSP_USING_SPI1_DEVICE0) + GPIO_PIN ce0_pin; + GPIO_FUNC ce0_mode; +#endif + +#if defined (BSP_USING_SPI0_DEVICE1) || defined (BSP_USING_SPI1_DEVICE1) + GPIO_PIN ce1_pin; + GPIO_FUNC ce1_mode; +#endif + +#if defined (BSP_USING_SPI1_DEVICE2) + GPIO_PIN ce2_pin; + GPIO_FUNC ce2_mode; +#endif + rt_ubase_t hw_base; + +}; + +struct raspi_spi_device +{ + char *device_name; + struct rt_spi_bus *spi_bus; + struct rt_spi_device *spi_device; + struct raspi_spi_hw_config *spi_hw_config; + GPIO_PIN cs_pin; +}; + +int rt_hw_spi_init(void); + +#endif
\ No newline at end of file diff --git a/bsp/raspberry-pi/raspi4-32/driver/raspi4.h b/bsp/raspberry-pi/raspi4-32/driver/raspi4.h index bfdf7bfecc..f874696705 100644 --- a/bsp/raspberry-pi/raspi4-32/driver/raspi4.h +++ b/bsp/raspberry-pi/raspi4-32/driver/raspi4.h @@ -61,6 +61,18 @@ #define AUX_BASE (PER_BASE + AUX_BASE_OFFSET) #define IRQ_PL011 (96 + 57) +/* SPI */ +#define SPI_0_BASE_OFFSET (0x00204000) +#define SPI_3_BASE_OFFSET (0x00204600) +#define SPI_4_BASE_OFFSET (0x00204800) +#define SPI_5_BASE_OFFSET (0x00204A00) +#define SPI_6_BASE_OFFSET (0x00204C00) + +#define SPI_0_BASE (PER_BASE + SPI_0_BASE_OFFSET) +#define SPI_3_BASE (PER_BASE + SPI_3_BASE_OFFSET) +#define SPI_4_BASE (PER_BASE + SPI_4_BASE_OFFSET) +#define SPI_5_BASE (PER_BASE + SPI_5_BASE_OFFSET) +#define SPI_6_BASE (PER_BASE + SPI_6_BASE_OFFSET) /* Peripheral IRQ OR-ing */ #define PACTL_CS HWREG32((PER_BASE + PACTL_CS_OFFSET)) typedef enum { diff --git a/bsp/raspberry-pi/raspi4-32/rtconfig.h b/bsp/raspberry-pi/raspi4-32/rtconfig.h index c073fa5003..c5ad40fc0b 100644 --- a/bsp/raspberry-pi/raspi4-32/rtconfig.h +++ b/bsp/raspberry-pi/raspi4-32/rtconfig.h @@ -86,6 +86,7 @@ #define RT_SERIAL_USING_DMA #define RT_SERIAL_RB_BUFSZ 64 #define RT_USING_PIN +#define RT_USING_SPI /* Using USB */ @@ -173,6 +174,9 @@ #define BSP_USING_GIC #define BSP_USING_GIC400 #define BSP_USING_PIN +#define BSP_USING_SPI +#define BSP_USING_SPI0_BUS +#define BSP_USING_SPI0_DEVICE0 #define BSP_USING_CORETIMER /* Board Peripheral Drivers */ |