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-rw-r--r--bsp/ls2kdev/drivers/SConscript10
-rw-r--r--bsp/ls2kdev/drivers/board.c99
-rw-r--r--bsp/ls2kdev/drivers/board.h24
-rw-r--r--bsp/ls2kdev/drivers/drv_uart.c178
-rw-r--r--bsp/ls2kdev/drivers/drv_uart.h114
-rw-r--r--bsp/ls2kdev/drivers/interrupt.c89
-rw-r--r--bsp/ls2kdev/drivers/ls2k1000.h13
7 files changed, 527 insertions, 0 deletions
diff --git a/bsp/ls2kdev/drivers/SConscript b/bsp/ls2kdev/drivers/SConscript
new file mode 100644
index 0000000000..d5542b768f
--- /dev/null
+++ b/bsp/ls2kdev/drivers/SConscript
@@ -0,0 +1,10 @@
+from building import *
+
+cwd = GetCurrentDir()
+src = Glob('*.c') + Glob('*.cpp') + Glob('*_gcc.S')
+
+CPPPATH = [cwd]
+
+group = DefineGroup('Drivers', src, depend = [''], CPPPATH = CPPPATH)
+
+Return('group')
diff --git a/bsp/ls2kdev/drivers/board.c b/bsp/ls2kdev/drivers/board.c
new file mode 100644
index 0000000000..3edbae9ee7
--- /dev/null
+++ b/bsp/ls2kdev/drivers/board.c
@@ -0,0 +1,99 @@
+/*
+ * Copyright (c) 2006-2020, RT-Thread Development Team
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Change Logs:
+ * Date Author Notes
+ * 2020-04-05 bigmagic Initial version
+ */
+
+#include <rtthread.h>
+#include <rthw.h>
+
+#include "mips_regs.h"
+#include "exception.h"
+#include "drv_uart.h"
+#include "board.h"
+/**
+ * this function will reset CPU
+ *
+ */
+void rt_hw_cpu_reset(void)
+{
+ rt_kprintf("reboot system...\n");
+ while (1);
+}
+
+/**
+ * this function will shutdown CPU
+ *
+ */
+void rt_hw_cpu_shutdown(void)
+{
+ rt_kprintf("shutdown...\n");
+
+ while (1);
+}
+
+
+/**
+ * This is the timer interrupt service routine.
+ */
+void rt_hw_timer_handler(void)
+{
+ unsigned int count;
+
+ count = read_c0_compare();
+ write_c0_compare(count);
+ write_c0_count(0);
+ /* increase a OS tick */
+ rt_tick_increase();
+}
+
+/**
+ * This function will initial OS timer
+ */
+void rt_hw_timer_init(void)
+{
+ write_c0_compare(CPU_HZ/2/RT_TICK_PER_SECOND);
+ write_c0_count(0);
+ mips_unmask_cpu_irq(7);
+}
+
+/**
+ * Board level initialization
+ */
+void rt_hw_board_init(void)
+{
+ rt_hw_exception_init();
+ /* init hardware interrupt */
+ rt_hw_interrupt_init();
+
+ #ifdef RT_USING_FPU
+ /* init hardware fpu */
+ rt_hw_fpu_init();
+ #endif
+
+#ifdef RT_USING_SERIAL
+ /* init hardware UART device */
+ rt_hw_uart_init();
+ /* set console device */
+ rt_console_set_device("uart");
+#endif
+
+#ifdef RT_USING_HEAP
+ rt_system_heap_init((void*)RT_HW_HEAP_BEGIN, (void*)RT_HW_HEAP_END);
+#endif
+
+ /* init operating system timer */
+ rt_hw_timer_init();
+
+
+#ifdef RT_USING_COMPONENTS_INIT
+ rt_components_board_init();
+#endif
+
+ rt_kprintf("Current SR: 0x%08x\n", read_c0_status());
+
+}
diff --git a/bsp/ls2kdev/drivers/board.h b/bsp/ls2kdev/drivers/board.h
new file mode 100644
index 0000000000..df4b40fb78
--- /dev/null
+++ b/bsp/ls2kdev/drivers/board.h
@@ -0,0 +1,24 @@
+/*
+ * Copyright (c) 2006-2020, RT-Thread Development Team
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Change Logs:
+ * Date Author Notes
+ * 2020-04-05 bigmagic the first version
+ */
+
+#ifndef BOARD_H__
+#define BOARD_H__
+
+#include <stdint.h>
+
+extern unsigned char __bss_end;
+
+#define CPU_HZ (100 * 1000 * 1000)
+#define RT_HW_HEAP_BEGIN (void*)&__bss_end
+#define RT_HW_HEAP_END (void*)(RT_HW_HEAP_BEGIN + 64 * 1024 * 1024)
+
+void rt_hw_board_init(void);
+
+#endif
diff --git a/bsp/ls2kdev/drivers/drv_uart.c b/bsp/ls2kdev/drivers/drv_uart.c
new file mode 100644
index 0000000000..428393dcc4
--- /dev/null
+++ b/bsp/ls2kdev/drivers/drv_uart.c
@@ -0,0 +1,178 @@
+/*
+ * Copyright (c) 2006-2020, RT-Thread Development Team
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Change Logs:
+ * Date Author Notes
+ * 2020-04-05 bigmagic Initial version
+ */
+
+/**
+ * @addtogroup ls2k
+ */
+
+/*@{*/
+
+#include <rtthread.h>
+#include <rtdevice.h>
+#include <rthw.h>
+#include "drv_uart.h"
+
+#define TRUE 1
+#define FALSE 0
+
+struct rt_uart_ls2k
+{
+ void *base;
+ rt_uint32_t IRQ;
+};
+
+static rt_err_t mipssim_uart_configure(struct rt_serial_device *serial, struct serial_configure *cfg)
+{
+ struct rt_uart_ls2k *uart_dev = RT_NULL;
+
+ RT_ASSERT(serial != RT_NULL);
+ RT_ASSERT(cfg != RT_NULL);
+
+ uart_dev = (struct rt_uart_ls2k *)serial->parent.user_data;
+
+ UART_IER(uart_dev->base) = 0; /* clear interrupt */
+ UART_FCR(uart_dev->base) = 0xc1; /* reset UART Rx/Tx */
+ /* set databits, stopbits and parity. (8-bit data, 1 stopbit, no parity) */
+ UART_LCR(uart_dev->base) = 0x3;
+ UART_MCR(uart_dev->base) = 0x3;
+ UART_LSR(uart_dev->base) = 0x60;
+ UART_MSR(uart_dev->base) = 0xb0;
+
+ return RT_EOK;
+}
+
+static rt_err_t mipssim_uart_control(struct rt_serial_device *serial, int cmd, void *arg)
+{
+ struct rt_uart_ls2k *uart_dev = RT_NULL;
+
+ RT_ASSERT(serial != RT_NULL);
+ uart_dev = (struct rt_uart_ls2k *)serial->parent.user_data;
+
+ switch (cmd)
+ {
+ case RT_DEVICE_CTRL_CLR_INT: /* Disable RX IRQ */
+ rt_hw_interrupt_mask(uart_dev->IRQ);
+ break;
+
+ case RT_DEVICE_CTRL_SET_INT: /* Enable RX IRQ */
+ rt_hw_interrupt_umask(uart_dev->IRQ);
+ UART_IER(uart_dev->base) |= (IER_IRxE|IER_ILE);
+ break;
+
+ default:
+ break;
+ }
+
+ return RT_EOK;
+
+}
+
+static rt_bool_t uart_is_transmit_empty(struct rt_uart_ls2k *uart_dev)
+{
+ unsigned char status = UART_LSR(uart_dev->base);
+
+ if (status & (UARTLSR_TE | UARTLSR_TFE))
+ {
+ return TRUE;
+ }
+ else
+ {
+ return FALSE;
+ }
+}
+
+static int mipssim_uart_putc(struct rt_serial_device *serial, char c)
+{
+ struct rt_uart_ls2k *uart_dev = RT_NULL;
+
+ RT_ASSERT(serial != RT_NULL);
+
+ uart_dev = (struct rt_uart_ls2k *)serial->parent.user_data;
+
+ while (FALSE == uart_is_transmit_empty(uart_dev))
+ ;
+
+ UART_DAT(uart_dev->base) = c;
+
+ return 1;
+}
+
+static int mipssim_uart_getc(struct rt_serial_device *serial)
+{
+ struct rt_uart_ls2k *uart_dev = RT_NULL;
+
+ RT_ASSERT(serial != RT_NULL);
+
+ uart_dev = (struct rt_uart_ls2k *)serial->parent.user_data;
+
+ if (LSR_RXRDY & UART_LSR(uart_dev->base))
+ {
+ return UART_DAT(uart_dev->base);
+ }
+
+ return -1;
+}
+
+/* UART interrupt handler */
+static void uart_irq_handler(int vector, void *param)
+{
+ struct rt_serial_device *serial = (struct rt_serial_device *)param;
+ struct rt_uart_ls2k *uart_dev = RT_NULL;
+
+ RT_ASSERT(serial != RT_NULL);
+
+ uart_dev = (struct rt_uart_ls2k *)serial->parent.user_data;
+ unsigned char iir = UART_IIR(uart_dev->base);
+
+ /* Find out interrupt reason */
+ if ((IIR_RXTOUT & iir) || (IIR_RXRDY & iir))
+ {
+ rt_interrupt_enter();
+ rt_hw_serial_isr(serial, RT_SERIAL_EVENT_RX_IND);
+ rt_interrupt_leave();
+ }
+
+}
+
+static const struct rt_uart_ops mipssim_uart_ops =
+{
+ mipssim_uart_configure,
+ mipssim_uart_control,
+ mipssim_uart_putc,
+ mipssim_uart_getc,
+};
+
+struct rt_uart_ls2k uart_dev0 =
+{
+ (void *)UART0_BASE,
+ 4,
+};
+struct rt_serial_device serial;
+
+
+void rt_hw_uart_init(void)
+{
+ struct rt_uart_ls2k *uart;
+ struct serial_configure config = RT_SERIAL_CONFIG_DEFAULT;
+
+ uart = &uart_dev0;
+
+ serial.ops = &mipssim_uart_ops;
+ serial.config = config;
+
+ rt_hw_interrupt_install(uart->IRQ, uart_irq_handler, &serial, "UART");
+
+ /* register UART device */
+ rt_hw_serial_register(&serial,
+ "uart",
+ RT_DEVICE_FLAG_RDWR | RT_DEVICE_FLAG_INT_RX,
+ uart);
+}
+/*@}*/
diff --git a/bsp/ls2kdev/drivers/drv_uart.h b/bsp/ls2kdev/drivers/drv_uart.h
new file mode 100644
index 0000000000..95c69a0442
--- /dev/null
+++ b/bsp/ls2kdev/drivers/drv_uart.h
@@ -0,0 +1,114 @@
+/*
+ * Copyright (c) 2006-2020, RT-Thread Development Team
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Change Logs:
+ * Date Author Notes
+ * 2019-04-05 bigmagic Initial version
+ */
+
+#ifndef _DRV_UART_H__
+#define _DRV_UART_H__
+
+#include "ls2k1000.h"
+#include <rthw.h>
+
+/* UART registers */
+#define UART_DAT(base) HWREG8(base + 0x00)
+#define UART_IER(base) HWREG8(base + 0x01)
+#define UART_IIR(base) HWREG8(base + 0x02)
+#define UART_FCR(base) HWREG8(base + 0x02)
+#define UART_LCR(base) HWREG8(base + 0x03)
+#define UART_MCR(base) HWREG8(base + 0x04)
+#define UART_LSR(base) HWREG8(base + 0x05)
+#define UART_MSR(base) HWREG8(base + 0x06)
+
+#define UART_LSB(base) HWREG8(base + 0x00)
+#define UART_MSB(base) HWREG8(base + 0x01)
+
+/* interrupt enable register */
+#define IER_IRxE 0x1
+#define IER_ITxE 0x2
+#define IER_ILE 0x4
+#define IER_IME 0x8
+
+/* interrupt identification register */
+#define IIR_IMASK 0xf /* mask */
+#define IIR_RXTOUT 0xc /* receive timeout */
+#define IIR_RLS 0x6 /* receive line status */
+#define IIR_RXRDY 0x4 /* receive ready */
+#define IIR_TXRDY 0x2 /* transmit ready */
+#define IIR_NOPEND 0x1 /* nothing */
+#define IIR_MLSC 0x0 /* modem status */
+#define IIR_FIFO_MASK 0xc0 /* set if FIFOs are enabled */
+
+/* fifo control register */
+#define FIFO_ENABLE 0x01 /* enable fifo */
+#define FIFO_RCV_RST 0x02 /* reset receive fifo */
+#define FIFO_XMT_RST 0x04 /* reset transmit fifo */
+#define FIFO_DMA_MODE 0x08 /* enable dma mode */
+#define FIFO_TRIGGER_1 0x00 /* trigger at 1 char */
+#define FIFO_TRIGGER_4 0x40 /* trigger at 4 chars */
+#define FIFO_TRIGGER_8 0x80 /* trigger at 8 chars */
+#define FIFO_TRIGGER_14 0xc0 /* trigger at 14 chars */
+
+// 线路控制寄存器
+/* character format control register */
+#define CFCR_DLAB 0x80 /* divisor latch */
+#define CFCR_SBREAK 0x40 /* send break */
+#define CFCR_PZERO 0x30 /* zero parity */
+#define CFCR_PONE 0x20 /* one parity */
+#define CFCR_PEVEN 0x10 /* even parity */
+#define CFCR_PODD 0x00 /* odd parity */
+#define CFCR_PENAB 0x08 /* parity enable */
+#define CFCR_STOPB 0x04 /* 2 stop bits */
+#define CFCR_8BITS 0x03 /* 8 data bits */
+#define CFCR_7BITS 0x02 /* 7 data bits */
+#define CFCR_6BITS 0x01 /* 6 data bits */
+#define CFCR_5BITS 0x00 /* 5 data bits */
+
+/* modem control register */
+#define MCR_LOOPBACK 0x10 /* loopback */
+#define MCR_IENABLE 0x08 /* output 2 = int enable */
+#define MCR_DRS 0x04 /* output 1 = xxx */
+#define MCR_RTS 0x02 /* enable RTS */
+#define MCR_DTR 0x01 /* enable DTR */
+
+/* line status register */
+#define LSR_RCV_FIFO 0x80 /* error in receive fifo */
+#define LSR_TSRE 0x40 /* transmitter empty */
+#define LSR_TXRDY 0x20 /* transmitter ready */
+#define LSR_BI 0x10 /* break detected */
+#define LSR_FE 0x08 /* framing error */
+#define LSR_PE 0x04 /* parity error */
+#define LSR_OE 0x02 /* overrun error */
+#define LSR_RXRDY 0x01 /* receiver ready */
+#define LSR_RCV_MASK 0x1f
+
+
+/* UART interrupt enable register value */
+#define UARTIER_IME (1 << 3)
+#define UARTIER_ILE (1 << 2)
+#define UARTIER_ITXE (1 << 1)
+#define UARTIER_IRXE (1 << 0)
+
+/* UART line control register value */
+#define UARTLCR_DLAB (1 << 7)
+#define UARTLCR_BCB (1 << 6)
+#define UARTLCR_SPB (1 << 5)
+#define UARTLCR_EPS (1 << 4)
+#define UARTLCR_PE (1 << 3)
+#define UARTLCR_SB (1 << 2)
+
+/* UART line status register value */
+#define UARTLSR_ERROR (1 << 7)
+#define UARTLSR_TE (1 << 6)
+#define UARTLSR_TFE (1 << 5)
+#define UARTLSR_BI (1 << 4)
+#define UARTLSR_FE (1 << 3)
+#define UARTLSR_PE (1 << 2)
+#define UARTLSR_OE (1 << 1)
+#define UARTLSR_DR (1 << 0)
+
+#endif
diff --git a/bsp/ls2kdev/drivers/interrupt.c b/bsp/ls2kdev/drivers/interrupt.c
new file mode 100644
index 0000000000..6473e5aa94
--- /dev/null
+++ b/bsp/ls2kdev/drivers/interrupt.c
@@ -0,0 +1,89 @@
+/*
+ * Copyright (c) 2006-2019, RT-Thread Development Team
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Change Logs:
+ * Date Author Notes
+ * 2020-04-05 bigmagic Initial version
+ */
+
+/**
+ * @addtogroup ls2k
+ */
+
+/*@{*/
+
+#include <rtthread.h>
+#include <rthw.h>
+#include <exception.h>
+
+#define MAX_INTR 32
+
+static struct rt_irq_desc irq_handle_table[MAX_INTR];
+
+static void rt_hw_interrupt_handler(int vector, void *param)
+{
+ rt_kprintf("Unhandled interrupt %d occured!!!\n", vector);
+}
+
+/**
+ * This function will initialize hardware interrupt
+ */
+void rt_hw_interrupt_init(void)
+{
+ rt_uint32_t idx;
+ rt_memset(irq_handle_table, 0x00, sizeof(irq_handle_table));
+ for (idx = 0; idx < MAX_INTR; idx ++)
+ {
+ irq_handle_table[idx].handler = rt_hw_interrupt_handler;
+ }
+}
+
+rt_isr_handler_t rt_hw_interrupt_install(int vector, rt_isr_handler_t handler,
+ void *param, const char *name)
+{
+ rt_isr_handler_t old_handler = RT_NULL;
+
+ if (vector >= 0 && vector < MAX_INTR)
+ {
+ old_handler = irq_handle_table[vector].handler;
+
+#ifdef RT_USING_INTERRUPT_INFO
+ rt_strncpy(irq_handle_table[vector].name, name, RT_NAME_MAX);
+#endif /* RT_USING_INTERRUPT_INFO */
+ irq_handle_table[vector].handler = handler;
+ irq_handle_table[vector].param = param;
+ }
+
+ return old_handler;
+}
+
+void rt_hw_timer_handler(void);
+
+void rt_do_mips_cpu_irq(rt_uint32_t ip)
+{
+ void *param;
+ rt_isr_handler_t irq_func;
+
+ if (ip == 7) {
+ rt_hw_timer_handler();
+ } else {
+ irq_func = irq_handle_table[ip].handler;
+ param = irq_handle_table[ip].param;
+
+ /* do interrupt */
+ irq_func(ip, param);
+ }
+}
+
+void rt_hw_interrupt_umask(int irq)
+{
+ mips_unmask_cpu_irq(irq);
+}
+
+void rt_hw_interrupt_mask(int irq)
+{
+ mips_mask_cpu_irq(irq);
+}
+/*@}*/
diff --git a/bsp/ls2kdev/drivers/ls2k1000.h b/bsp/ls2kdev/drivers/ls2k1000.h
new file mode 100644
index 0000000000..8c2d84bfaa
--- /dev/null
+++ b/bsp/ls2kdev/drivers/ls2k1000.h
@@ -0,0 +1,13 @@
+#ifndef _LS2K1000_H__
+#define _LS2K1000_H__
+
+#include <mips.h>
+
+#define UART0_BASE_ADDR 0xbfe00000
+#define UART0_OFF 0x0
+#define UART0_BASE CKSEG1ADDR(UART0_BASE_ADDR + UART0_OFF)
+
+void rt_hw_timer_handler(void);
+void rt_hw_uart_init(void);
+
+#endif \ No newline at end of file
generated by cgit v1.3.1 (git 2.54.0) at 2026-10-30 13:11:55 +0000