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-rw-r--r--bsp/zynq7000/README.txt5
-rw-r--r--bsp/zynq7000/SConscript14
-rw-r--r--bsp/zynq7000/SConstruct35
-rw-r--r--bsp/zynq7000/applications/SConscript11
-rw-r--r--bsp/zynq7000/applications/application.c47
-rw-r--r--bsp/zynq7000/applications/startup.c81
-rw-r--r--bsp/zynq7000/drivers/SConscript22
-rw-r--r--bsp/zynq7000/drivers/board.c87
-rw-r--r--bsp/zynq7000/drivers/board.h64
-rw-r--r--bsp/zynq7000/drivers/uart.c301
-rw-r--r--bsp/zynq7000/drivers/uart_hw.h307
-rw-r--r--bsp/zynq7000/drivers/zynq7000.h59
-rw-r--r--bsp/zynq7000/rtconfig.h147
-rw-r--r--bsp/zynq7000/rtconfig.py49
-rw-r--r--bsp/zynq7000/zynq7000.ld116
15 files changed, 0 insertions, 1345 deletions
diff --git a/bsp/zynq7000/README.txt b/bsp/zynq7000/README.txt
deleted file mode 100644
index f84aaa81e7..0000000000
--- a/bsp/zynq7000/README.txt
+++ /dev/null
@@ -1,5 +0,0 @@
-Place the rtthread.bin in the SD card and run:
-
- mmcinfo; fatload mmc 0 0x1ff00000 rtthread.bin; go 0x1ff00000
-
-in the uboot console.
diff --git a/bsp/zynq7000/SConscript b/bsp/zynq7000/SConscript
deleted file mode 100644
index fe0ae941ae..0000000000
--- a/bsp/zynq7000/SConscript
+++ /dev/null
@@ -1,14 +0,0 @@
-# for module compiling
-import os
-Import('RTT_ROOT')
-
-cwd = str(Dir('#'))
-objs = []
-list = os.listdir(cwd)
-
-for d in list:
- path = os.path.join(cwd, d)
- if os.path.isfile(os.path.join(path, 'SConscript')):
- objs = objs + SConscript(os.path.join(d, 'SConscript'))
-
-Return('objs')
diff --git a/bsp/zynq7000/SConstruct b/bsp/zynq7000/SConstruct
deleted file mode 100644
index d06010997d..0000000000
--- a/bsp/zynq7000/SConstruct
+++ /dev/null
@@ -1,35 +0,0 @@
-import os
-import sys
-import rtconfig
-
-if os.path.isdir('./rt-thread'):
- RTT_ROOT = os.path.normpath(os.path.join(os.getcwd(), 'rt-thread/'))
-elif os.getenv('RTT_ROOT'):
- RTT_ROOT = os.getenv('RTT_ROOT')
-else:
- RTT_ROOT = os.path.normpath(os.getcwd() + '/../..')
-
-sys.path = sys.path + [os.path.join(RTT_ROOT, 'tools')]
-from building import *
-
-TARGET = 'rtthread-zynq7000.' + rtconfig.TARGET_EXT
-
-DefaultEnvironment(tools=[])
-env = Environment(tools = ['mingw'],
- AS = rtconfig.AS, ASFLAGS = rtconfig.AFLAGS,
- CC = rtconfig.CC, CCFLAGS = rtconfig.CFLAGS,
- AR = rtconfig.AR, ARFLAGS = '-rc',
- LINK = rtconfig.LINK, LINKFLAGS = rtconfig.LFLAGS)
-env.PrependENVPath('PATH', rtconfig.EXEC_PATH)
-
-Export('RTT_ROOT')
-Export('rtconfig')
-
-# prepare building environment
-objs = PrepareBuilding(env, RTT_ROOT)
-
-# if the linker script changed, relink the target
-Depends(TARGET, rtconfig.LINK_SCRIPT)
-
-# make a building
-DoBuilding(TARGET, objs)
diff --git a/bsp/zynq7000/applications/SConscript b/bsp/zynq7000/applications/SConscript
deleted file mode 100644
index 01eb940dfb..0000000000
--- a/bsp/zynq7000/applications/SConscript
+++ /dev/null
@@ -1,11 +0,0 @@
-Import('RTT_ROOT')
-Import('rtconfig')
-from building import *
-
-cwd = os.path.join(str(Dir('#')), 'applications')
-src = Glob('*.c')
-CPPPATH = [cwd, str(Dir('#'))]
-
-group = DefineGroup('Applications', src, depend = [''], CPPPATH = CPPPATH)
-
-Return('group')
diff --git a/bsp/zynq7000/applications/application.c b/bsp/zynq7000/applications/application.c
deleted file mode 100644
index 0e4bf433d4..0000000000
--- a/bsp/zynq7000/applications/application.c
+++ /dev/null
@@ -1,47 +0,0 @@
-/*
- * COPYRIGHT (C) 2013-2014, Shanghai Real-Thread Technology Co., Ltd
- *
- * All rights reserved.
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; either version 2 of the License, or
- * (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License along
- * with this program; if not, write to the Free Software Foundation, Inc.,
- * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA.
- */
-
-#include <rtthread.h>
-
-#include <cp15.h>
-
-/* thread phase init */
-static void rt_init_thread_entry(void *parameter)
-{
- /* do component initialization */
- rt_components_init();
- rt_kprintf("running on cpu %d\n",
- rt_cpu_get_smp_id() & 0x0f);
-
- /* add your initialization here */
-}
-
-int rt_application_init()
-{
- rt_thread_t tid;
-
- tid = rt_thread_create("init", rt_init_thread_entry, RT_NULL, 2048,
- RT_THREAD_PRIORITY_MAX/3, 20);
- if (tid != RT_NULL)
- rt_thread_startup(tid);
-
- return 0;
-}
-
diff --git a/bsp/zynq7000/applications/startup.c b/bsp/zynq7000/applications/startup.c
deleted file mode 100644
index d2958a2c58..0000000000
--- a/bsp/zynq7000/applications/startup.c
+++ /dev/null
@@ -1,81 +0,0 @@
-/*
- * COPYRIGHT (C) 2013-2014, Shanghai Real-Thread Technology Co., Ltd
- *
- * All rights reserved.
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; either version 2 of the License, or
- * (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License along
- * with this program; if not, write to the Free Software Foundation, Inc.,
- * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA.
- */
-
-#include <rthw.h>
-#include <rtthread.h>
-
-#include <board.h>
-
-extern int rt_application_init(void);
-
-/**
- * This function will startup RT-Thread RTOS.
- */
-void rtthread_startup(void)
-{
- rt_hw_mmu_init();
-
- /* initialzie hardware interrupt */
- rt_hw_interrupt_init();
-
- /* initialize board */
- rt_hw_board_init();
-
- /* show RT-Thread version */
- rt_show_version();
-
- /* initialize memory system */
-#ifdef RT_USING_HEAP
- rt_system_heap_init(HEAP_BEGIN, HEAP_END);
-#endif
-
- /* initialize scheduler system */
- rt_system_scheduler_init();
-
- /* initialize system timer */
- rt_system_timer_init();
-
- /* initialize soft timer thread */
- rt_system_timer_thread_init();
-
- /* initialize application */
- rt_application_init();
-
- /* initialize idle thread */
- rt_thread_idle_init();
-
- /* start scheduler */
- rt_system_scheduler_start();
-
- /* never reach here */
- return ;
-}
-
-int main(void)
-{
- /* disable interrupt first */
- rt_hw_interrupt_disable();
-
- /* invoke rtthread_startup */
- rtthread_startup();
-
- return 0;
-}
-
diff --git a/bsp/zynq7000/drivers/SConscript b/bsp/zynq7000/drivers/SConscript
deleted file mode 100644
index a630c8a7c4..0000000000
--- a/bsp/zynq7000/drivers/SConscript
+++ /dev/null
@@ -1,22 +0,0 @@
-import copy
-Import('RTT_ROOT')
-Import('rtconfig')
-from building import *
-
-cwd = GetCurrentDir()
-src = Glob('*.c')
-
-# remove no need file.
-if GetDepend('RT_USING_LWIP') == False:
- src_need_remove = ['dm9000.c'] # need remove file list.
- SrcRemove(src, src_need_remove)
-
-if GetDepend('RT_USING_DFS') == False:
- src_need_remove = ['sd.c'] # need remove file list.
- SrcRemove(src, src_need_remove)
-
-CPPPATH = [cwd]
-
-group = DefineGroup('Drivers', src, depend = [''], CPPPATH = CPPPATH)
-
-Return('group')
diff --git a/bsp/zynq7000/drivers/board.c b/bsp/zynq7000/drivers/board.c
deleted file mode 100644
index 5696fbbf2c..0000000000
--- a/bsp/zynq7000/drivers/board.c
+++ /dev/null
@@ -1,87 +0,0 @@
-/*
- * COPYRIGHT (C) 2013-2014, Shanghai Real-Thread Technology Co., Ltd
- *
- * All rights reserved.
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; either version 2 of the License, or
- * (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License along
- * with this program; if not, write to the Free Software Foundation, Inc.,
- * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA.
- */
-
-#include <rthw.h>
-#include <rtthread.h>
-
-#include "board.h"
-
-typedef struct
-{
- volatile rt_uint32_t LOAD;
- volatile rt_uint32_t COUNTER;
- volatile rt_uint32_t CONTROL;
- volatile rt_uint32_t ISR;
-} ptimer_reg_t;
-
-/* Values for control register */
-#define PRIVATE_TIMER_CONTROL_PRESCALER_MASK 0x0000FF00
-#define PRIVATE_TIMER_CONTROL_PRESCALER_SHIFT 8
-#define PRIVATE_TIMER_CONTROL_IRQ_ENABLE_MASK 0x00000004
-#define PRIVATE_TIMER_CONTROL_AUTO_RELOAD_MASK 0x00000002
-#define PRIVATE_TIMER_CONTROL_ENABLE_MASK 0x00000001
-
-/* Values for ISR register */
-#define PRIVATE_TIMER_ISR_EVENT_FLAG_MASK 0x00000001
-
-
-#define PRIVATE_TIMER_BASE 0xF8F00600
-#define PRIVATE_TIMER ((ptimer_reg_t*)PRIVATE_TIMER_BASE)
-
-static void rt_hw_timer_isr(int vector, void *param)
-{
- rt_tick_increase();
- /* clear interrupt */
- PRIVATE_TIMER->ISR = PRIVATE_TIMER_ISR_EVENT_FLAG_MASK;
-}
-
-int rt_hw_timer_init(void)
-{
- PRIVATE_TIMER->CONTROL &= ~PRIVATE_TIMER_CONTROL_ENABLE_MASK;
- {
- /* Clear the prescaler. */
- rt_uint32_t ctrl = PRIVATE_TIMER->CONTROL;
- ctrl &= ~PRIVATE_TIMER_CONTROL_PRESCALER_MASK;
- PRIVATE_TIMER->CONTROL = ctrl;
- }
- /* The processor timer is always clocked at 1/2 CPU frequency(CPU_3x2x). */
- PRIVATE_TIMER->COUNTER = APU_FREQ/2/RT_TICK_PER_SECOND;
- /* Set reload value. */
- PRIVATE_TIMER->LOAD = APU_FREQ/2/RT_TICK_PER_SECOND;
- PRIVATE_TIMER->CONTROL |= PRIVATE_TIMER_CONTROL_AUTO_RELOAD_MASK;
-
- PRIVATE_TIMER->CONTROL |= PRIVATE_TIMER_CONTROL_IRQ_ENABLE_MASK;
- PRIVATE_TIMER->ISR = PRIVATE_TIMER_ISR_EVENT_FLAG_MASK;
-
- rt_hw_interrupt_install(IRQ_Zynq7000_PTIMER, rt_hw_timer_isr, RT_NULL, "tick");
- rt_hw_interrupt_umask(IRQ_Zynq7000_PTIMER);
-
- PRIVATE_TIMER->CONTROL |= PRIVATE_TIMER_CONTROL_ENABLE_MASK;
-
- return 0;
-}
-INIT_BOARD_EXPORT(rt_hw_timer_init);
-
-void rt_hw_board_init()
-{
- rt_components_board_init();
- rt_console_set_device(RT_CONSOLE_DEVICE_NAME);
-}
-
diff --git a/bsp/zynq7000/drivers/board.h b/bsp/zynq7000/drivers/board.h
deleted file mode 100644
index cfd617f824..0000000000
--- a/bsp/zynq7000/drivers/board.h
+++ /dev/null
@@ -1,64 +0,0 @@
-/*
- * COPYRIGHT (C) 2013-2014, Shanghai Real-Thread Technology Co., Ltd
- *
- * All rights reserved.
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; either version 2 of the License, or
- * (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License along
- * with this program; if not, write to the Free Software Foundation, Inc.,
- * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA.
- */
-
-#ifndef __BOARD_H__
-#define __BOARD_H__
-
-#include <zynq7000.h>
-
-/* Freq of all peripherals */
-#define APU_FREQ 666666667
-#define DDR_FREQ 533333313
-#define DCI_FREQ 10159000
-#define QSPI_FREQ 200000000
-#define SMC_FREQ 100000000
-#define ENET0_FREQ 125000000
-#define ENET1_FREQ 125000000
-#define USB0_FREQ 60000000
-#define USB1_FREQ 60000000
-#define SDIO_FREQ 50000000
-#define UART_FREQ 50000000
-#define SPI_FREQ 166666666
-#define I2C_FREQ 25000000
-#define WDT_FREQ 133333333
-#define TTC_FREQ 50000000
-#define CAN_FREQ 100000000
-#define PCAP_FREQ 200000000
-#define TPIU_FREQ 0
-#define FPGA0_FREQ 100000000
-#define FPGA1_FREQ 200000000
-#define FPGA2_FREQ 200000000
-#define FPGA3_FREQ 80000000
-
-#if defined(__CC_ARM)
-extern int Image$$RW_IRAM1$$ZI$$Limit;
-#define HEAP_BEGIN ((void*)&Image$$RW_IRAM1$$ZI$$Limit)
-#elif defined(__GNUC__)
-extern int __bss_end;
-#define HEAP_BEGIN ((void*)&__bss_end)
-#endif
-
-#define HEAP_END (void*)(0x20000000)
-
-void rt_hw_board_init();
-
-int rt_hw_uart_init(void);
-
-#endif
diff --git a/bsp/zynq7000/drivers/uart.c b/bsp/zynq7000/drivers/uart.c
deleted file mode 100644
index df4250b399..0000000000
--- a/bsp/zynq7000/drivers/uart.c
+++ /dev/null
@@ -1,301 +0,0 @@
-/*
- * serial.c UART driver
- *
- * COPYRIGHT (C) 2013, Shanghai Real-Thread Technology Co., Ltd
- *
- * All rights reserved.
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; either version 2 of the License, or
- * (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License along
- * with this program; if not, write to the Free Software Foundation, Inc.,
- * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA.
- *
- * Change Logs:
- * Date Author Notes
- * 2013-03-30 Bernard the first verion
- */
-
-#include <rthw.h>
-#include <rtdevice.h>
-
-#include "board.h"
-
-#include "gic.h"
-#include "cp15.h"
-
-#include "uart_hw.h"
-
-#define Zynq7000_UART_INT_DISABLE(UART) \
- (UART->IER &= ~(UART_IXR_RXOVR | UART_IXR_RXFULL))
-#define Zynq7000_UART_INT_ENABLE(UART) \
- (UART->IER |= (UART_IXR_RXOVR | UART_IXR_RXFULL))
-
-#define Zynq7000_UART_SENDCHAR(UART, ch) \
- do { \
- while ((UART->SR) & UART_SR_TXFULL); \
- UART->FIFO = ch; \
- } while(0)
-
-#define Zynq7000_UART_GETCHAR(UART, ch) \
- do { \
- if (UART->ISR & UART_SR_RXOVR) \
- { \
- ch = UART->FIFO & 0xff; \
- UART->ISR = (UART_IXR_RXOVR | UART_IXR_RXFULL); \
- } \
- } while(0)
-
-static void UartEnable(UART_Registers* uart)
-{
- uint32_t tmp = uart->CR;
- tmp &= ~UART_CR_EN_DIS_MASK;
- tmp |= (UART_CR_TX_EN | UART_CR_RX_EN);
-
- uart->CR = tmp;
-}
-
-static void UartDisable(UART_Registers* uart)
-{
- uint32_t tmp = uart->CR;
- tmp &= ~UART_CR_EN_DIS_MASK;
- tmp |= (UART_CR_TX_DIS | UART_CR_RX_DIS);
- uart->CR = tmp;
-}
-
-static void UartResetTXRXLogic(UART_Registers* uart)
-{
- uart->CR |= 0x03;
- while (uart->CR & 0x03)
- ;
-}
-
-/* PULLUP | LVCMOS18 | Fast CMOS | UART */
-#define RX_MIO_PIN_MODE ((0x1UL << 12) | (0x1UL << 9) | (0x01UL << 8) | (0x7UL << 5))
-#define TX_MIO_PIN_MODE ( (0x1UL << 9) | (0x01UL << 8) | (0x7UL << 5))
-
-struct hw_uart_device
-{
- UART_Registers * uart;
- rt_uint32_t irqno;
-
- /* MIO pin mode address */
- rt_uint32_t *rxmio;
- rt_uint32_t *txmio;
-};
-
-/* RT-Thread UART interface */
-
-static void rt_hw_uart_isr(int irqno, void *param)
-{
- struct rt_serial_device *serial = (struct rt_serial_device *)param;
-
- rt_hw_serial_isr(serial, RT_SERIAL_EVENT_RX_IND);
-}
-
-static rt_err_t uart_configure(struct rt_serial_device *serial, struct serial_configure *cfg)
-{
- uint32_t mr;
- struct hw_uart_device *pdev = serial->parent.user_data;
- UART_Registers *uart = pdev->uart;
-
- /* unlock SLCR */
- __REG32(Zynq7000_SLCR_BASE+Zynq7000_SLCR_UNLOCK) = 0xDF0D;
-
- /* no loopback */
- __REG32(Zynq7000_SLCR_BASE+Zynq7000_SLCR_MIO_LOOPBACK) &= ~(1 << 1);
-
- if (uart == (void*)Zynq7000_UART0_BASE)
- {
- /* enable the coresponding AMBA Peripheral Clock */
- __REG32(Zynq7000_SLCR_BASE+Zynq7000_SLCR_APER_CLK_CTRL) |= 1 << 20;
- /* enable uart clock. Divider 0x14 gives 50MHZ ref clock on IO PLL input. */
- __REG32(Zynq7000_SLCR_BASE+Zynq7000_SLCR_UART_CLK_CTRL) |= (0x14 << 8) | 0x01;
- /* deassert the AMBA clock and software reset */
- __REG32(Zynq7000_SLCR_BASE+Zynq7000_SLCR_UART_RST_CTRL) &= ~((0x01 << 2)|(0x01 << 0));
- }
- else if (uart == (void*)Zynq7000_UART1_BASE)
- {
- __REG32(Zynq7000_SLCR_BASE+Zynq7000_SLCR_APER_CLK_CTRL) |= 1 << 21;
- __REG32(Zynq7000_SLCR_BASE+Zynq7000_SLCR_UART_CLK_CTRL) |= (0x14 << 8) | 0x02;
- __REG32(Zynq7000_SLCR_BASE+Zynq7000_SLCR_UART_RST_CTRL) &= ~((0x01 << 3)|(0x01 << 1));
- }
- else
- return -RT_ERROR;
-
- UartDisable(uart);
- UartResetTXRXLogic(uart);
- UartEnable(uart);
-
- mr = uart->MR & ~(UART_MR_CHARLEN_MASK |
- UART_MR_STOPMODE_MASK |
- UART_MR_PARITY_MASK);
-
- if (cfg->stop_bits == STOP_BITS_2)
- mr |= UART_MR_STOPMODE_2_BIT;
- else if (cfg->stop_bits == STOP_BITS_1)
- mr |= UART_MR_STOPMODE_1_BIT;
- else
- return -RT_ERROR;
-
- if (cfg->parity == PARITY_EVEN)
- mr |= UART_MR_PARITY_EVEN;
- else if (cfg->parity == PARITY_ODD)
- mr |= UART_MR_PARITY_ODD;
- else if (cfg->parity == PARITY_NONE)
- mr |= UART_MR_PARITY_NONE;
- else
- return -1;
-
- if (cfg->data_bits == DATA_BITS_8)
- mr |= UART_MR_CHARLEN_8_BIT;
- else if (cfg->data_bits == DATA_BITS_7)
- mr |= UART_MR_CHARLEN_7_BIT;
- else if (cfg->data_bits == DATA_BITS_6)
- mr |= UART_MR_CHARLEN_6_BIT;
- else
- return -RT_ERROR;
-
- uart->MR = mr;
-
- uart->TXWM = 8;
- uart->RXWM = 1;
-
- if (cfg->baud_rate == BAUD_RATE_115200)
- {
- uart->BAUDGEN = UART_BAUDGEN_115200;
- uart->BAUDDIV = UART_BAUDDIV_115200;
- }
- else
- {
- rt_kprintf("baudrate %d not implemented yet\n", cfg->baud_rate);
- }
-
- /* disable all interrupts */
- uart->IDR = UART_IXR_MASK;
-
- /* configure the pin */
- *(pdev->txmio) = TX_MIO_PIN_MODE;
- *(pdev->rxmio) = RX_MIO_PIN_MODE;
-
- return RT_EOK;
-}
-
-static rt_err_t uart_control(struct rt_serial_device *serial, int cmd, void *arg)
-{
- struct hw_uart_device *pdev;
-
- RT_ASSERT(serial != RT_NULL);
-
- pdev = serial->parent.user_data;
-
- switch (cmd)
- {
- case RT_DEVICE_CTRL_CLR_INT:
- /* disable rx irq */
- Zynq7000_UART_INT_DISABLE(pdev->uart);
- break;
-
- case RT_DEVICE_CTRL_SET_INT:
- /* enable rx irq */
- Zynq7000_UART_INT_ENABLE(pdev->uart);
- rt_hw_interrupt_install(pdev->irqno, rt_hw_uart_isr, serial, "uart");
- /* set the interrupt to this cpu */
- arm_gic_set_cpu(0, pdev->irqno, 1 << rt_cpu_get_smp_id());
- rt_hw_interrupt_umask(pdev->irqno);
- break;
- }
-
- return RT_EOK;
-}
-
-static int uart_putc(struct rt_serial_device *serial, char c)
-{
- struct hw_uart_device *dev;
-
- RT_ASSERT(serial != RT_NULL);
- dev = (struct hw_uart_device *)serial->parent.user_data;
-
- Zynq7000_UART_SENDCHAR(dev->uart, c);
-
- return 1;
-}
-
-static int uart_getc(struct rt_serial_device *serial)
-{
- int ch;
- struct hw_uart_device *dev;
-
- RT_ASSERT(serial != RT_NULL);
- dev = (struct hw_uart_device *)serial->parent.user_data;
-
- ch = -1;
- Zynq7000_UART_GETCHAR(dev->uart, ch);
-
- return ch;
-}
-
-static const struct rt_uart_ops _uart_ops =
-{
- uart_configure,
- uart_control,
- uart_putc,
- uart_getc,
-};
-
-/* UART device driver structure */
-static struct hw_uart_device _uart_device0 =
-{
- .uart = (UART_Registers*)Zynq7000_UART0_BASE,
- .irqno = IRQ_Zynq7000_UART0,
- .rxmio = (rt_uint32_t*)(Zynq7000_SLCR_BASE+0x0728), /* MIO10 */
- .txmio = (rt_uint32_t*)(Zynq7000_SLCR_BASE+0x072C), /* MIO11 */
-};
-static struct hw_uart_device _uart_device1 =
-{
- .uart = (UART_Registers*)Zynq7000_UART1_BASE,
- .irqno = IRQ_Zynq7000_UART1,
- .rxmio = (rt_uint32_t*)(Zynq7000_SLCR_BASE+0x07C4), /* MIO49 */
- .txmio = (rt_uint32_t*)(Zynq7000_SLCR_BASE+0x07C0), /* MIO48 */
-};
-
-static struct rt_serial_device _serial0;
-static struct rt_serial_device _serial1;
-
-int rt_hw_uart_init(void)
-{
- struct serial_configure config;
-
- config.baud_rate = BAUD_RATE_115200;
- config.bit_order = BIT_ORDER_LSB;
- config.data_bits = DATA_BITS_8;
- config.parity = PARITY_NONE;
- config.stop_bits = STOP_BITS_1;
- config.invert = NRZ_NORMAL;
- config.bufsz = RT_SERIAL_RB_BUFSZ;
-
- _serial0.ops = &_uart_ops;
- _serial0.config = config;
-
- _serial1.ops = &_uart_ops;
- _serial1.config = config;
-
- /* register uart device */
- rt_hw_serial_register(&_serial0, "uart0",
- RT_DEVICE_FLAG_RDWR | RT_DEVICE_FLAG_INT_RX,
- &_uart_device0);
- rt_hw_serial_register(&_serial1, "uart1",
- RT_DEVICE_FLAG_RDWR | RT_DEVICE_FLAG_INT_RX,
- &_uart_device1);
- return 0;
-}
-INIT_BOARD_EXPORT(rt_hw_uart_init);
-
diff --git a/bsp/zynq7000/drivers/uart_hw.h b/bsp/zynq7000/drivers/uart_hw.h
deleted file mode 100644
index 75e3937559..0000000000
--- a/bsp/zynq7000/drivers/uart_hw.h
+++ /dev/null
@@ -1,307 +0,0 @@
-#ifndef _UART_HW_H_
-#define _UART_HW_H_
-
-#include <stdint.h>
-
-/** @name Register Map
- *
- * Registers of the UART.
- * @{
- */
-typedef struct
-{
- volatile uint32_t CR; /**< Control Register */
- volatile uint32_t MR; /**< Mode Register */
- volatile uint32_t IER; /**< Interrupt Enable */
- volatile uint32_t IDR; /**< Interrupt Disable */
- volatile uint32_t IMR; /**< Interrupt Mask */
- volatile uint32_t ISR; /**< Interrupt Status */
- volatile uint32_t BAUDGEN; /**< Baud Rate Generator */
- volatile uint32_t RXTOUT; /**< RX Timeout */
- volatile uint32_t RXWM; /**< RX FIFO Trigger Level */
- volatile uint32_t MODEMCR; /**< Modem Control */
- volatile uint32_t MODEMSR; /**< Modem Status */
- volatile uint32_t SR; /**< Channel Status */
- volatile uint32_t FIFO; /**< FIFO */
- volatile uint32_t BAUDDIV; /**< Baud Rate Divider */
- volatile uint32_t FLOWDEL; /**< Flow Delay */
- volatile uint32_t RESERVED1;
- volatile uint32_t RESERVED2;
- volatile uint32_t TXWM; /* TX FIFO Trigger Level */
-} UART_Registers;
-/* @} */
-
-/** @name Control Register
- *
- * The Control register (CR) controls the major functions of the device.
- *
- * Control Register Bit Definition
- */
-#define UART_CR_STOPBRK 0x00000100 /**< Stop transmission of break */
-#define UART_CR_STARTBRK 0x00000080 /**< Set break */
-#define UART_CR_TORST 0x00000040 /**< RX timeout counter restart */
-#define UART_CR_TX_DIS 0x00000020 /**< TX disabled. */
-#define UART_CR_TX_EN 0x00000010 /**< TX enabled */
-#define UART_CR_RX_DIS 0x00000008 /**< RX disabled. */
-#define UART_CR_RX_EN 0x00000004 /**< RX enabled */
-#define UART_CR_EN_DIS_MASK 0x0000003C /**< Enable/disable Mask */
-#define UART_CR_TXRST 0x00000002 /**< TX logic reset */
-#define UART_CR_RXRST 0x00000001 /**< RX logic reset */
-/* @}*/
-
-/** @name Mode Register
- *
- * The mode register (MR) defines the mode of transfer as well as the data
- * format. If this register is modified during transmission or reception,
- * data validity cannot be guaranteed.
- *
- * Mode Register Bit Definition
- * @{
- */
-#define UART_MR_CCLK 0x00000400 /**< Input clock selection */
-#define UART_MR_CHMODE_R_LOOP 0x00000300 /**< Remote loopback mode */
-#define UART_MR_CHMODE_L_LOOP 0x00000200 /**< Local loopback mode */
-#define UART_MR_CHMODE_ECHO 0x00000100 /**< Auto echo mode */
-#define UART_MR_CHMODE_NORM 0x00000000 /**< Normal mode */
-#define UART_MR_CHMODE_SHIFT 8 /**< Mode shift */
-#define UART_MR_CHMODE_MASK 0x00000300 /**< Mode mask */
-#define UART_MR_STOPMODE_2_BIT 0x00000080 /**< 2 stop bits */
-#define UART_MR_STOPMODE_1_5_BIT 0x00000040 /**< 1.5 stop bits */
-#define UART_MR_STOPMODE_1_BIT 0x00000000 /**< 1 stop bit */
-#define UART_MR_STOPMODE_SHIFT 6 /**< Stop bits shift */
-#define UART_MR_STOPMODE_MASK 0x000000A0 /**< Stop bits mask */
-#define UART_MR_PARITY_NONE 0x00000020 /**< No parity mode */
-#define UART_MR_PARITY_MARK 0x00000018 /**< Mark parity mode */
-#define UART_MR_PARITY_SPACE 0x00000010 /**< Space parity mode */
-#define UART_MR_PARITY_ODD 0x00000008 /**< Odd parity mode */
-#define UART_MR_PARITY_EVEN 0x00000000 /**< Even parity mode */
-#define UART_MR_PARITY_SHIFT 3 /**< Parity setting shift */
-#define UART_MR_PARITY_MASK 0x00000038 /**< Parity mask */
-#define UART_MR_CHARLEN_6_BIT 0x00000006 /**< 6 bits data */
-#define UART_MR_CHARLEN_7_BIT 0x00000004 /**< 7 bits data */
-#define UART_MR_CHARLEN_8_BIT 0x00000000 /**< 8 bits data */
-#define UART_MR_CHARLEN_SHIFT 1 /**< Data Length shift */
-#define UART_MR_CHARLEN_MASK 0x00000006 /**< Data length mask */
-#define UART_MR_CLKSEL 0x00000001 /**< Input clock selection */
-/* @} */
-
-/** @name Interrupt Registers
- *
- * Interrupt control logic uses the interrupt enable register (IER) and the
- * interrupt disable register (IDR) to set the value of the bits in the
- * interrupt mask register (IMR). The IMR determines whether to pass an
- * interrupt to the interrupt status register (ISR).
- * Writing a 1 to IER Enbables an interrupt, writing a 1 to IDR disables an
- * interrupt. IMR and ISR are read only, and IER and IDR are write only.
- * Reading either IER or IDR returns 0x00.
- *
- * All four registers have the same bit definitions.
- *
- * @{
- */
-#define UART_IXR_DMS 0x00000200 /**< Modem status change interrupt */
-#define UART_IXR_TOUT 0x00000100 /**< Timeout error interrupt */
-#define UART_IXR_PARITY 0x00000080 /**< Parity error interrupt */
-#define UART_IXR_FRAMING 0x00000040 /**< Framing error interrupt */
-#define UART_IXR_OVER 0x00000020 /**< Overrun error interrupt */
-#define UART_IXR_TXFULL 0x00000010 /**< TX FIFO full interrupt. */
-#define UART_IXR_TXEMPTY 0x00000008 /**< TX FIFO empty interrupt. */
-#define UART_IXR_RXFULL 0x00000004 /**< RX FIFO full interrupt. */
-#define UART_IXR_RXEMPTY 0x00000002 /**< RX FIFO empty interrupt. */
-#define UART_IXR_RXOVR 0x00000001 /**< RX FIFO trigger interrupt. */
-#define UART_IXR_MASK 0x000003FF /**< Valid bit mask */
-/* @} */
-
-/** @name Baud Rate Generator Register
- *
- * The baud rate generator control register (BRGR) is a 16 bit register that
- * controls the receiver bit sample clock and baud rate.
- * Valid values are 1 - 65535.
- *
- * Bit Sample Rate = CCLK / BRGR, where the CCLK is selected by the MR_CCLK bit
- * in the MR register.
- * @{
- */
-#define UART_BAUDGEN_DISABLE 0x00000000 /**< Disable clock */
-#define UART_BAUDGEN_MASK 0x0000FFFF /**< Valid bits mask */
-/* @} */
-
-/** @name Baud Divisor Rate register
- *
- * The baud rate divider register (BDIV) controls how much the bit sample
- * rate is divided by. It sets the baud rate.
- * Valid values are 0x04 to 0xFF. Writing a value less than 4 will be ignored.
- *
- * Baud rate = CCLK / ((BAUDDIV + 1) x BRGR), where the CCLK is selected by
- * the MR_CCLK bit in the MR register.
- * @{
- */
-#define UART_BAUDDIV_MASK 0x000000FF /**< 8 bit baud divider mask */
-/* @} */
-
-/*
- Page 496
- Simplifyed Table 19-1 UART Parameter Value Examples
- Parameter Value Examples
- Clock Baud BRGR-CD BDIV-CD Actual Baud Rate
- UART Ref clock 600 10417 7
- UART Ref clock 9,600 651 7
- UART Ref clock 28,800 347 4
- UART Ref clock 115,200 62 6
- UART Ref clock 230,400 31 6
-*/
-
-/*Baudrates assuming input clock speed is 3125000L */
-/*Baud_rate_gen_reg0*/
-#define UART_BAUDGEN_115200 62 /*Baud Rate Clock Divisor*/
-
-/*Register Baud_rate_divider_reg0 Details*/
-#define UART_BAUDDIV_115200 6 /*Baud Rate Clock Divisor*/
-
-/** @name Receiver Timeout Register
- *
- * Use the receiver timeout register (RTR) to detect an idle condition on
- * the receiver data line.
- *
- * @{
- */
-#define UART_RXTOUT_DISABLE 0x00000000 /**< Disable time out */
-#define UART_RXTOUT_MASK 0x000000FF /**< Valid bits mask */
-/* @} */
-
-/** @name Receiver FIFO Trigger Level Register
- *
- * Use the Receiver FIFO Trigger Level Register (RTRIG) to set the value at
- * which the RX FIFO triggers an interrupt event.
- * @{
- */
-#define UART_RXWM_DISABLE 0x00000000 /**< Disable RX trigger interrupt */
-#define UART_RXWM_MASK 0x0000003F /**< Valid bits mask */
-/* @} */
-
-/** @name Modem Control Register
- *
- * This register (MODEMCR) controls the interface with the modem or data set,
- * or a peripheral device emulating a modem.
- *
- * @{
- */
-#define UART_MODEMCR_FCM 0x00000010 /**< Flow control mode */
-#define UART_MODEMCR_RTS 0x00000002 /**< Request to send */
-#define UART_MODEMCR_DTR 0x00000001 /**< Data terminal ready */
-/* @} */
-
-/** @name Modem Status Register
- *
- * This register (MODEMSR) indicates the current state of the control lines
- * from a modem, or another peripheral device, to the CPU. In addition, four
- * bits of the modem status register provide change information. These bits
- * are set to a logic 1 whenever a control input from the modem changes state.
- *
- * Note: Whenever the DCTS, DDSR, TERI, or DDCD bit is set to logic 1, a modem
- * status interrupt is generated and this is reflected in the modem status
- * register.
- *
- * @{
- */
-#define UART_MODEMSR_FCMS 0x00000100 /**< Flow control mode (FCMS) */
-#define UART_MODEMSR_DCD 0x00000080 /**< Complement of DCD input */
-#define UART_MODEMSR_RI 0x00000040 /**< Complement of RI input */
-#define UART_MODEMSR_DSR 0x00000020 /**< Complement of DSR input */
-#define UART_MODEMSR_CTS 0x00000010 /**< Complement of CTS input */
-#define UART_MEDEMSR_DCDX 0x00000008 /**< Delta DCD indicator */
-#define UART_MEDEMSR_RIX 0x00000004 /**< Change of RI */
-#define UART_MEDEMSR_DSRX 0x00000002 /**< Change of DSR */
-#define UART_MEDEMSR_CTSX 0x00000001 /**< Change of CTS */
-/* @} */
-
-/** @name Channel Status Register
- *
- * The channel status register (CSR) is provided to enable the control logic
- * to monitor the status of bits in the channel interrupt status register,
- * even if these are masked out by the interrupt mask register.
- *
- * @{
- */
-#define UART_SR_FLOWDEL 0x00001000 /**< RX FIFO fill over flow delay */
-#define UART_SR_TACTIVE 0x00000800 /**< TX active */
-#define UART_SR_RACTIVE 0x00000400 /**< RX active */
-#define UART_SR_DMS 0x00000200 /**< Delta modem status change */
-#define UART_SR_TOUT 0x00000100 /**< RX timeout */
-#define UART_SR_PARITY 0x00000080 /**< RX parity error */
-#define UART_SR_FRAME 0x00000040 /**< RX frame error */
-#define UART_SR_OVER 0x00000020 /**< RX overflow error */
-#define UART_SR_TXFULL 0x00000010 /**< TX FIFO full */
-#define UART_SR_TXEMPTY 0x00000008 /**< TX FIFO empty */
-#define UART_SR_RXFULL 0x00000004 /**< RX FIFO full */
-#define UART_SR_RXEMPTY 0x00000002 /**< RX FIFO empty */
-#define UART_SR_RXOVR 0x00000001 /**< RX FIFO fill over trigger */
-/* @} */
-
-/** @name Flow Delay Register
- *
- * Operation of the flow delay register (FLOWDEL) is very similar to the
- * receive FIFO trigger register. An internal trigger signal activates when the
- * FIFO is filled to the level set by this register. This trigger will not
- * cause an interrupt, although it can be read through the channel status
- * register. In hardware flow control mode, RTS is deactivated when the trigger
- * becomes active. RTS only resets when the FIFO level is four less than the
- * level of the flow delay trigger and the flow delay trigger is not activated.
- * A value less than 4 disables the flow delay.
- * @{
- */
-#define UART_FLOWDEL_MASK UART_RXWM_MASK /**< Valid bit mask */
-/* @} */
-
-
-/** @name Base Address of UART0
- *
- * The base address of UART0
- */
-#define UART0_BASE 0xE0000000
-
-/** @name Base Address of UART1
- *
- * The base address of UART1
- */
-#define UART1_BASE 0xE0001000
-
-
-#define UART0 ((UART_Registers*)UART0_BASE)
-#define UART1 ((UART_Registers*)UART1_BASE)
-
-/****************************************************************************/
-/**
-* Determine if there is receive data in the receiver and/or FIFO.
-*
-* @param BaseAddress contains the base address of the device.
-*
-* @return TRUE if there is receive data, FALSE otherwise.
-*
-* @note C-Style signature:
-* uint32_t UartDataReceived(uint32_t BaseAddress)
-*
-******************************************************************************/
-#define UartDataReceived(BaseAddress) \
- !((io_in32((BaseAddress) + UART_SR_OFFSET) & \
- UART_SR_RXEMPTY) == UART_SR_RXEMPTY)
-
-/****************************************************************************/
-/**
-* Determine if a byte of data can be sent with the transmitter.
-*
-* @param BaseAddress contains the base address of the device.
-*
-* @return TRUE if the TX FIFO is full, FALSE if a byte can be put in the
-* FIFO.
-*
-* @note C-Style signature:
-* uint32_t UartTXFIFOFull(uint32_t BaseAddress)
-*
-******************************************************************************/
-#define UartTXFIFOFull(BaseAddress) \
- ((io_in32((BaseAddress) + UART_SR_OFFSET) & \
- UART_SR_TXFULL) == UART_SR_TXFULL)
-
-#endif
-
diff --git a/bsp/zynq7000/drivers/zynq7000.h b/bsp/zynq7000/drivers/zynq7000.h
deleted file mode 100644
index fb3d349b04..0000000000
--- a/bsp/zynq7000/drivers/zynq7000.h
+++ /dev/null
@@ -1,59 +0,0 @@
-#ifndef __AM33XX_H__
-#define __AM33XX_H__
-/*
- * COPYRIGHT (C) 2013-2014, Shanghai Real-Thread Technology Co., Ltd
- *
- * All rights reserved.
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; either version 2 of the License, or
- * (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License along
- * with this program; if not, write to the Free Software Foundation, Inc.,
- * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA.
- */
-
-#include "armv7.h"
-
-#define __REG32(x) (*((volatile unsigned int *)(x)))
-#define __REG16(x) (*((volatile unsigned short *)(x)))
-
-#define Zynq7000_UART0_BASE 0xE0000000
-#define Zynq7000_UART1_BASE 0xE0001000
-
-#define Zynq7000_SLCR_BASE 0xF8000000
-#define Zynq7000_SLCR_LOCK 0x004
-#define Zynq7000_SLCR_UNLOCK 0x008
-#define Zynq7000_SLCR_APER_CLK_CTRL 0x12C
-#define Zynq7000_SLCR_UART_CLK_CTRL 0x154
-#define Zynq7000_SLCR_UART_RST_CTRL 0x228
-#define Zynq7000_SLCR_MIO_LOOPBACK 0x804
-#define Zynq7000_SLCR_MIO_MST_TRI0 0x80C
-#define Zynq7000_SLCR_MIO_MST_TRI1 0x810
-
-#define Zynq7000_SCTL_BASE 0xF8F00000 /* System Controller */
-#define Zynq7000_TIMER_GLOBAL_BASE 0xF8F00200 /* Global 64bit timer */
-
-#define Zynq7000_GIC_CPU_BASE 0xF8F00100 /* Generic interrupt controller CPU interface */
-#define Zynq7000_GIC_DIST_BASE 0xF8F01000 /* Generic interrupt controller distributor */
-
-/* zynq on-board gic irq sources */
-#define IRQ_Zynq7000_GTIMER 27
-#define IRQ_Zynq7000_PTIMER 29
-#define IRQ_Zynq7000_AWDT 30
-#define IRQ_Zynq7000_UART0 59
-#define IRQ_Zynq7000_UART1 82
-#define IRQ_Zynq7000_MAXNR 94
-
-#define ARM_GIC_NR_IRQS IRQ_Zynq7000_MAXNR
-/* only one GIC available */
-#define ARM_GIC_MAX_NR 1
-
-#endif
diff --git a/bsp/zynq7000/rtconfig.h b/bsp/zynq7000/rtconfig.h
deleted file mode 100644
index 21087f03b9..0000000000
--- a/bsp/zynq7000/rtconfig.h
+++ /dev/null
@@ -1,147 +0,0 @@
-/* RT-Thread config file */
-#ifndef __RTTHREAD_CFG_H__
-#define __RTTHREAD_CFG_H__
-
-// <RDTConfigurator URL="http://www.rt-thread.com/eclipse">
-
-// <integer name="RT_NAME_MAX" description="Maximal size of kernel object name length" default="6" />
-#define RT_NAME_MAX 6
-// <integer name="RT_ALIGN_SIZE" description="Alignment size for CPU architecture data access" default="4" />
-#define RT_ALIGN_SIZE 4
-// <integer name="RT_THREAD_PRIORITY_MAX" description="Maximal level of thread priority" default="32">
-// <item description="8">8</item>
-// <item description="32">32</item>
-// <item description="256">256</item>
-// </integer>
-#define RT_THREAD_PRIORITY_MAX 32
-// <integer name="RT_TICK_PER_SECOND" description="OS tick per second" default="1000" />
-#define RT_TICK_PER_SECOND 1000
-// <integer name="IDLE_THREAD_STACK_SIZE" description="The stack size of idle thread" default="512" />
-#define IDLE_THREAD_STACK_SIZE 512
-// <section name="RT_DEBUG" description="Kernel Debug Configuration" default="true" >
-#define RT_DEBUG
-#define RT_DEBUG_COLOR
-// <bool name="RT_THREAD_DEBUG" description="Thread debug enable" default="false" />
-// #define RT_THREAD_DEBUG
-// <bool name="RT_USING_OVERFLOW_CHECK" description="Thread stack over flow detect" default="true" />
-#define RT_USING_OVERFLOW_CHECK
-// </section>
-
-// <bool name="RT_USING_HOOK" description="Using hook functions" default="true" />
-#define RT_USING_HOOK
-// <section name="RT_USING_TIMER_SOFT" description="Using software timer which will start a thread to handle soft-timer" default="true" >
-// #define RT_USING_TIMER_SOFT
-// <integer name="RT_TIMER_THREAD_PRIO" description="The priority level of timer thread" default="4" />
-#define RT_TIMER_THREAD_PRIO 4
-// <integer name="RT_TIMER_THREAD_STACK_SIZE" description="The stack size of timer thread" default="512" />
-#define RT_TIMER_THREAD_STACK_SIZE 512
-// <integer name="RT_TIMER_TICK_PER_SECOND" description="The soft-timer tick per second" default="10" />
-#define RT_TIMER_TICK_PER_SECOND 10
-// </section>
-
-// <section name="IPC" description="Inter-Thread communication" default="always" >
-// <bool name="RT_USING_SEMAPHORE" description="Using semaphore in the system" default="true" />
-#define RT_USING_SEMAPHORE
-// <bool name="RT_USING_MUTEX" description="Using mutex in the system" default="true" />
-#define RT_USING_MUTEX
-// <bool name="RT_USING_EVENT" description="Using event group in the system" default="true" />
-#define RT_USING_EVENT
-// <bool name="RT_USING_MAILBOX" description="Using mailbox in the system" default="true" />
-#define RT_USING_MAILBOX
-// <bool name="RT_USING_MESSAGEQUEUE" description="Using message queue in the system" default="true" />
-#define RT_USING_MESSAGEQUEUE
-// </section>
-
-// <section name="MM" description="Memory Management" default="always" >
-// <bool name="RT_USING_MEMPOOL" description="Using Memory Pool Management in the system" default="true" />
-#define RT_USING_MEMPOOL
-// <bool name="RT_USING_MEMHEAP" description="Using Memory Heap Object in the system" default="true" />
-// #define RT_USING_MEMHEAP
-// <bool name="RT_USING_HEAP" description="Using Dynamic Heap Management in the system" default="true" />
-#define RT_USING_HEAP
-// <bool name="RT_USING_MEMHEAP_AS_HEAP" description="Using Memory Heap Object as system heap" default="true" />
-// #define RT_USING_MEMHEAP_AS_HEAP
-// <bool name="RT_USING_SMALL_MEM" description="Optimizing for small memory" default="false" />
-#define RT_USING_SMALL_MEM
-// <bool name="RT_USING_SLAB" description="Using SLAB memory management for large memory" default="false" />
-// #define RT_USING_SLAB
-// </section>
-
-// <section name="RT_USING_DEVICE" description="Using Device Driver Framework" default="true" >
-#define RT_USING_DEVICE
-// <bool name=RT_USING_DEVICE_IPC description="Using IPC in Device Driver Framework" default="true" />
-#define RT_USING_DEVICE_IPC
-// <bool name="RT_USING_SERIAL" description="Using Serial Device Driver Framework" default="true" />
-#define RT_USING_SERIAL
-#define RT_SERIAL_USING_DMA
-// <integer name="RT_UART_RX_BUFFER_SIZE" description="The buffer size for UART reception" default="64" />
-#define RT_UART_RX_BUFFER_SIZE 64
-// <bool name=RT_USING_INTERRUPT_INFO description="Using interrupt information description" default="true" />
-#define RT_USING_INTERRUPT_INFO
-// </section>
-
-// <section name="RT_USING_CONSOLE" description="Using console" default="true" >
-#define RT_USING_CONSOLE
-// <integer name="RT_CONSOLEBUF_SIZE" description="The buffer size for console output" default="128" />
-#define RT_CONSOLEBUF_SIZE 128
-// <string name="RT_CONSOLE_DEVICE_NAME" description="The device name for console" default="uart" />
-#define RT_CONSOLE_DEVICE_NAME "uart0"
-// </section>
-
-// <bool name="RT_USING_COMPONENTS_INIT" description="Using RT-Thread components initialization" default="true" />
-#define RT_USING_COMPONENTS_INIT
-// <section name="RT_USING_FINSH" description="Using finsh as shell, which is a C-Express shell" default="true" >
-#define RT_USING_FINSH
-// <bool name="FINSH_USING_MSH" description="Using module shell" default="true" />
-#define FINSH_USING_MSH
-// <bool name="FINSH_USING_MSH_DEFAULT" description="The default shell is msh" default="true" />
-#define FINSH_USING_MSH_DEFAULT
-// <bool name="FINSH_USING_SYMTAB" description="Using symbol table in finsh shell" default="true" />
-#define FINSH_USING_SYMTAB
-// <bool name="FINSH_USING_DESCRIPTION" description="Keeping description in symbol table" default="true" />
-#define FINSH_USING_DESCRIPTION
-// <integer name="FINSH_THREAD_STACK_SIZE" description="The stack size for finsh thread" default="4096" />
-#define FINSH_THREAD_STACK_SIZE 4096
-// </section>
-
-// <section name="LIBC" description="C Runtime library setting" default="always" >
-// <bool name="RT_USING_LIBC" description="Using C library" default="true" />
-#define RT_USING_LIBC
-// <bool name="RT_USING_POSIX" description="Using POSIX library" default="true" />
-#define RT_USING_POSIX
-// <bool name="RT_USING_PTHREADS" description="Using POSIX threads library" default="true" />
-#define RT_USING_PTHREADS
-// </section>
-
-// <section name="RT_USING_DFS" description="Device file system" default="true" >
-#define RT_USING_DFS
-// <bool name="DFS_USING_WORKDIR" description="Using working directory" default="true" />
-// #define DFS_USING_WORKDIR
-// <integer name="DFS_FILESYSTEMS_MAX" description="The maximal number of mounted file system" default="4" />
-#define DFS_FILESYSTEMS_MAX 2
-// <integer name="DFS_FD_MAX" description="The maximal number of opened files" default="4" />
-#define DFS_FD_MAX 4
-// <bool name="RT_USING_DFS_ELMFAT" description="Using ELM FatFs" default="true" />
-#define RT_USING_DFS_ELMFAT
-// <integer name="RT_DFS_ELM_USE_LFN" description="Support long file name" default="0">
-// <item description="LFN1">1</item>
-// <item description="LFN1">2</item>
-// </integer>
-#define RT_DFS_ELM_USE_LFN 1
-// <integer name="RT_DFS_ELM_MAX_LFN" description="Maximal size of file name length" default="255" />
-#define RT_DFS_ELM_MAX_LFN 64
-// <bool name="RT_USING_DFS_YAFFS2" description="Using YAFFS2" default="false" />
-// #define RT_USING_DFS_YAFFS2
-// <bool name="RT_USING_DFS_UFFS" description="Using UFFS" default="false" />
-// #define RT_USING_DFS_UFFS
-// <bool name="RT_USING_DFS_DEVFS" description="Using devfs for device objects" default="true" />
-#define RT_USING_DFS_DEVFS
-// <bool name="RT_USING_DFS_NFS" description="Using NFS v3 client file system" default="false" />
-// #define RT_USING_DFS_NFS
-// <string name="RT_NFS_HOST_EXPORT" description="NFSv3 host export" default="192.168.1.5:/" />
-#define RT_NFS_HOST_EXPORT "192.168.1.5:/"
-// </section>
-// </RDTConfigurator>
-
-
-#endif
diff --git a/bsp/zynq7000/rtconfig.py b/bsp/zynq7000/rtconfig.py
deleted file mode 100644
index 47c1fd7cb6..0000000000
--- a/bsp/zynq7000/rtconfig.py
+++ /dev/null
@@ -1,49 +0,0 @@
-import os
-
-# toolchains options
-ARCH='arm'
-CPU='zynq7000'
-CROSS_TOOL='gcc'
-
-if os.getenv('RTT_CC'):
- CROSS_TOOL = os.getenv('RTT_CC')
-
-# only support GNU GCC compiler
-PLATFORM = 'gcc'
-EXEC_PATH = '/opt/arm-none-eabi-gcc'
-
-if os.getenv('RTT_EXEC_PATH'):
- EXEC_PATH = os.getenv('RTT_EXEC_PATH')
-
-BUILD = 'debug'
-
-if PLATFORM == 'gcc':
- # toolchains
- PREFIX = 'arm-none-eabi-'
- CC = PREFIX + 'gcc'
- CXX = PREFIX + 'g++'
- AS = PREFIX + 'gcc'
- AR = PREFIX + 'ar'
- LINK = PREFIX + 'gcc'
- TARGET_EXT = 'elf'
- SIZE = PREFIX + 'size'
- OBJDUMP = PREFIX + 'objdump'
- OBJCPY = PREFIX + 'objcopy'
- #ARCH = -mcpu=cortex-a9 -mfpu=vfpv3
- DEVICE = ' -Wall -mcpu=cortex-a9 -mfpu=vfpv3 -ftree-vectorize -ffast-math -mfloat-abi=softfp'
- CFLAGS = DEVICE
- AFLAGS = ' -c' + DEVICE + ' -x assembler-with-cpp'
- LINK_SCRIPT = 'zynq7000.ld'
- LFLAGS = DEVICE + ' -Wl,--gc-sections,-Map=zynq7000.map,-cref,-u,system_vectors -T %s' % LINK_SCRIPT
-
- CPATH = ''
- LPATH = ''
-
- if BUILD == 'debug':
- CFLAGS += ' -O0 -gdwarf-2'
- AFLAGS += ' -gdwarf-2'
- else:
- CFLAGS += ' -O2'
-
- POST_ACTION = OBJCPY + ' -O binary $TARGET rtthread.bin\n' +\
- SIZE + ' $TARGET \n'
diff --git a/bsp/zynq7000/zynq7000.ld b/bsp/zynq7000/zynq7000.ld
deleted file mode 100644
index ae9b8ea38d..0000000000
--- a/bsp/zynq7000/zynq7000.ld
+++ /dev/null
@@ -1,116 +0,0 @@
-/*
- * COPYRIGHT (C) 2013-2014, Shanghai Real-Thread Technology Co., Ltd
- *
- * This file is part of RT-Thread (http://www.rt-thread.org)
- *
- * All rights reserved.
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; either version 2 of the License, or
- * (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License along
- * with this program; if not, write to the Free Software Foundation, Inc.,
- * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA.
- */
-
-OUTPUT_FORMAT("elf32-littlearm", "elf32-littlearm", "elf32-littlearm")
-OUTPUT_ARCH(arm)
-SECTIONS
-{
- . = 0x1ff00000;
- __text_start = .;
- .text :
- {
- *(.vectors)
- /* make the ISRs close to vectors may be more cache-friendly */
- *(.text.isr)
-
- *(.text)
- *(.text.*)
-
- /* section information for finsh shell */
- . = ALIGN(4);
- __fsymtab_start = .;
- KEEP(*(FSymTab))
- __fsymtab_end = .;
- . = ALIGN(4);
- __vsymtab_start = .;
- KEEP(*(VSymTab))
- __vsymtab_end = .;
- . = ALIGN(4);
-
- /* section information for modules */
- . = ALIGN(4);
- __rtmsymtab_start = .;
- KEEP(*(RTMSymTab))
- __rtmsymtab_end = .;
-
- /* section information for initialization */
- . = ALIGN(4);
- __rt_init_start = .;
- KEEP(*(SORT(.rti_fn*)))
- __rt_init_end = .;
- } =0
- __text_end = .;
-
- __rodata_start = .;
- .rodata : { *(.rodata) *(.rodata.*) }
- __rodata_end = .;
-
- . = ALIGN(4);
- .ctors :
- {
- PROVIDE(__ctors_start__ = .);
- KEEP(*(SORT(.ctors.*)))
- KEEP(*(.ctors))
- PROVIDE(__ctors_end__ = .);
- }
-
- .dtors :
- {
- PROVIDE(__dtors_start__ = .);
- KEEP(*(SORT(.dtors.*)))
- KEEP(*(.dtors))
- PROVIDE(__dtors_end__ = .);
- }
-
- __data_start = .;
- . = ALIGN(4);
- .data :
- {
- KEEP(*(.resource_table))
- *(.data)
- *(.data.*)
- }
- __data_end = .;
-
- . = ALIGN(4);
- __bss_start = __data_end;
- .bss :
- {
- *(.bss)
- *(.bss.*)
- *(COMMON)
- . = ALIGN(4);
- }
- . = ALIGN(4);
- __bss_end = .;
-
- /* Stabs debugging sections. */
- .stab 0 : { *(.stab) }
- .stabstr 0 : { *(.stabstr) }
- .stab.excl 0 : { *(.stab.excl) }
- .stab.exclstr 0 : { *(.stab.exclstr) }
- .stab.index 0 : { *(.stab.index) }
- .stab.indexstr 0 : { *(.stab.indexstr) }
- .comment 0 : { *(.comment) }
-
- _end = .;
-}
generated by cgit v1.3.1 (git 2.54.0) at 2026-10-30 13:51:51 +0000