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-rw-r--r--libcpu/aarch64/common/SConscript6
-rw-r--r--libcpu/aarch64/common/cpuport.h31
-rw-r--r--libcpu/aarch64/common/gic.c504
-rw-r--r--libcpu/aarch64/common/gic.h63
-rw-r--r--libcpu/aarch64/common/gic/SConscript30
-rw-r--r--libcpu/aarch64/common/gic/gic_pl390.c273
-rw-r--r--libcpu/aarch64/common/gic/gic_pl390.h27
-rw-r--r--libcpu/aarch64/common/gic/gic_pl400.c261
-rw-r--r--libcpu/aarch64/common/gic/gic_pl400.h61
-rw-r--r--libcpu/aarch64/common/interrupt.c409
-rw-r--r--libcpu/aarch64/common/interrupt.h60
-rw-r--r--libcpu/aarch64/common/stack.c89
-rw-r--r--libcpu/aarch64/common/trap.c172
13 files changed, 1333 insertions, 653 deletions
diff --git a/libcpu/aarch64/common/SConscript b/libcpu/aarch64/common/SConscript
index c51148525b..915b9d29aa 100644
--- a/libcpu/aarch64/common/SConscript
+++ b/libcpu/aarch64/common/SConscript
@@ -6,9 +6,13 @@ Import('rtconfig')
cwd = GetCurrentDir()
src = Glob('*.c') + Glob('*.cpp') + Glob('*.S')
+
+if not GetDepend('BSP_USING_GIC'):
+ SrcRemove(src, 'gic.c')
+
CPPPATH = [cwd]
-group = DefineGroup('CPU', src, depend = [''], CPPPATH = CPPPATH)
+group = DefineGroup('common', src, depend = [''], CPPPATH = CPPPATH)
# build for sub-directory
list = os.listdir(cwd)
diff --git a/libcpu/aarch64/common/cpuport.h b/libcpu/aarch64/common/cpuport.h
new file mode 100644
index 0000000000..91c4a7f77b
--- /dev/null
+++ b/libcpu/aarch64/common/cpuport.h
@@ -0,0 +1,31 @@
+/*
+ * Copyright (c) 2006-2021, RT-Thread Development Team
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Change Logs:
+ * Date Author Notes
+ * 2021-09-10 GuEe-GUI first version
+ */
+
+#ifndef __CPUPORT_H__
+#define __CPUPORT_H__
+
+#include <rtdef.h>
+
+rt_inline void rt_hw_isb(void)
+{
+ __asm__ volatile ("isb":::"memory");
+}
+
+rt_inline void rt_hw_dmb(void)
+{
+ __asm__ volatile ("dmb sy":::"memory");
+}
+
+rt_inline void rt_hw_dsb(void)
+{
+ __asm__ volatile ("dsb sy":::"memory");
+}
+
+#endif /* __CPUPORT_H__ */
diff --git a/libcpu/aarch64/common/gic.c b/libcpu/aarch64/common/gic.c
new file mode 100644
index 0000000000..d23ece42df
--- /dev/null
+++ b/libcpu/aarch64/common/gic.c
@@ -0,0 +1,504 @@
+/*
+ * Copyright (c) 2006-2021, RT-Thread Development Team
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Change Logs:
+ * Date Author Notes
+ * 2013-07-20 Bernard first version
+ * 2014-04-03 Grissiom many enhancements
+ * 2018-11-22 Jesven add rt_hw_ipi_send()
+ * add rt_hw_ipi_handler_install()
+ */
+
+#include <rthw.h>
+#include <rtthread.h>
+
+#include <gic.h>
+#include <cp15.h>
+
+struct arm_gic
+{
+ rt_uint64_t offset; /* the first interrupt index in the vector table */
+
+ rt_uint64_t dist_hw_base; /* the base address of the gic distributor */
+ rt_uint64_t cpu_hw_base; /* the base addrees of the gic cpu interface */
+};
+
+/* 'ARM_GIC_MAX_NR' is the number of cores */
+static struct arm_gic _gic_table[ARM_GIC_MAX_NR];
+
+/** Macro to access the Generic Interrupt Controller Interface (GICC)
+*/
+#define GIC_CPU_CTRL(hw_base) __REG32((hw_base) + 0x00U)
+#define GIC_CPU_PRIMASK(hw_base) __REG32((hw_base) + 0x04U)
+#define GIC_CPU_BINPOINT(hw_base) __REG32((hw_base) + 0x08U)
+#define GIC_CPU_INTACK(hw_base) __REG32((hw_base) + 0x0cU)
+#define GIC_CPU_EOI(hw_base) __REG32((hw_base) + 0x10U)
+#define GIC_CPU_RUNNINGPRI(hw_base) __REG32((hw_base) + 0x14U)
+#define GIC_CPU_HIGHPRI(hw_base) __REG32((hw_base) + 0x18U)
+#define GIC_CPU_IIDR(hw_base) __REG32((hw_base) + 0xFCU)
+
+/** Macro to access the Generic Interrupt Controller Distributor (GICD)
+*/
+#define GIC_DIST_CTRL(hw_base) __REG32((hw_base) + 0x000U)
+#define GIC_DIST_TYPE(hw_base) __REG32((hw_base) + 0x004U)
+#define GIC_DIST_IGROUP(hw_base, n) __REG32((hw_base) + 0x080U + ((n)/32U) * 4U)
+#define GIC_DIST_ENABLE_SET(hw_base, n) __REG32((hw_base) + 0x100U + ((n)/32U) * 4U)
+#define GIC_DIST_ENABLE_CLEAR(hw_base, n) __REG32((hw_base) + 0x180U + ((n)/32U) * 4U)
+#define GIC_DIST_PENDING_SET(hw_base, n) __REG32((hw_base) + 0x200U + ((n)/32U) * 4U)
+#define GIC_DIST_PENDING_CLEAR(hw_base, n) __REG32((hw_base) + 0x280U + ((n)/32U) * 4U)
+#define GIC_DIST_ACTIVE_SET(hw_base, n) __REG32((hw_base) + 0x300U + ((n)/32U) * 4U)
+#define GIC_DIST_ACTIVE_CLEAR(hw_base, n) __REG32((hw_base) + 0x380U + ((n)/32U) * 4U)
+#define GIC_DIST_PRI(hw_base, n) __REG32((hw_base) + 0x400U + ((n)/4U) * 4U)
+#define GIC_DIST_TARGET(hw_base, n) __REG32((hw_base) + 0x800U + ((n)/4U) * 4U)
+#define GIC_DIST_CONFIG(hw_base, n) __REG32((hw_base) + 0xc00U + ((n)/16U) * 4U)
+#define GIC_DIST_SOFTINT(hw_base) __REG32((hw_base) + 0xf00U)
+#define GIC_DIST_CPENDSGI(hw_base, n) __REG32((hw_base) + 0xf10U + ((n)/4U) * 4U)
+#define GIC_DIST_SPENDSGI(hw_base, n) __REG32((hw_base) + 0xf20U + ((n)/4U) * 4U)
+#define GIC_DIST_ICPIDR2(hw_base) __REG32((hw_base) + 0xfe8U)
+
+static unsigned int _gic_max_irq;
+
+int arm_gic_get_active_irq(rt_uint64_t index)
+{
+ int irq;
+
+ RT_ASSERT(index < ARM_GIC_MAX_NR);
+
+ irq = GIC_CPU_INTACK(_gic_table[index].cpu_hw_base);
+ irq += _gic_table[index].offset;
+ return irq;
+}
+
+void arm_gic_ack(rt_uint64_t index, int irq)
+{
+ rt_uint64_t mask = 1U << (irq % 32U);
+
+ RT_ASSERT(index < ARM_GIC_MAX_NR);
+
+ irq = irq - _gic_table[index].offset;
+ RT_ASSERT(irq >= 0U);
+
+ GIC_DIST_PENDING_CLEAR(_gic_table[index].dist_hw_base, irq) = mask;
+ GIC_CPU_EOI(_gic_table[index].cpu_hw_base) = irq;
+}
+
+void arm_gic_mask(rt_uint64_t index, int irq)
+{
+ rt_uint64_t mask = 1U << (irq % 32U);
+
+ RT_ASSERT(index < ARM_GIC_MAX_NR);
+
+ irq = irq - _gic_table[index].offset;
+ RT_ASSERT(irq >= 0U);
+
+ GIC_DIST_ENABLE_CLEAR(_gic_table[index].dist_hw_base, irq) = mask;
+}
+
+void arm_gic_umask(rt_uint64_t index, int irq)
+{
+ rt_uint64_t mask = 1U << (irq % 32U);
+
+ RT_ASSERT(index < ARM_GIC_MAX_NR);
+
+ irq = irq - _gic_table[index].offset;
+ RT_ASSERT(irq >= 0U);
+
+ GIC_DIST_ENABLE_SET(_gic_table[index].dist_hw_base, irq) = mask;
+}
+
+rt_uint64_t arm_gic_get_pending_irq(rt_uint64_t index, int irq)
+{
+ rt_uint64_t pend;
+
+ RT_ASSERT(index < ARM_GIC_MAX_NR);
+
+ irq = irq - _gic_table[index].offset;
+ RT_ASSERT(irq >= 0U);
+
+ if (irq >= 16U)
+ {
+ pend = (GIC_DIST_PENDING_SET(_gic_table[index].dist_hw_base, irq) >> (irq % 32U)) & 0x1UL;
+ }
+ else
+ {
+ /* INTID 0-15 Software Generated Interrupt */
+ pend = (GIC_DIST_SPENDSGI(_gic_table[index].dist_hw_base, irq) >> ((irq % 4U) * 8U)) & 0xFFUL;
+ /* No CPU identification offered */
+ if (pend != 0U)
+ {
+ pend = 1U;
+ }
+ else
+ {
+ pend = 0U;
+ }
+ }
+
+ return (pend);
+}
+
+void arm_gic_set_pending_irq(rt_uint64_t index, int irq)
+{
+ RT_ASSERT(index < ARM_GIC_MAX_NR);
+
+ irq = irq - _gic_table[index].offset;
+ RT_ASSERT(irq >= 0U);
+
+ if (irq >= 16U)
+ {
+ GIC_DIST_PENDING_SET(_gic_table[index].dist_hw_base, irq) = 1U << (irq % 32U);
+ }
+ else
+ {
+ /* INTID 0-15 Software Generated Interrupt */
+ /* Forward the interrupt to the CPU interface that requested it */
+ GIC_DIST_SOFTINT(_gic_table[index].dist_hw_base) = (irq | 0x02000000U);
+ }
+}
+
+void arm_gic_clear_pending_irq(rt_uint64_t index, int irq)
+{
+ rt_uint64_t mask;
+
+ RT_ASSERT(index < ARM_GIC_MAX_NR);
+
+ irq = irq - _gic_table[index].offset;
+ RT_ASSERT(irq >= 0U);
+
+ if (irq >= 16U)
+ {
+ mask = 1U << (irq % 32U);
+ GIC_DIST_PENDING_CLEAR(_gic_table[index].dist_hw_base, irq) = mask;
+ }
+ else
+ {
+ mask = 1U << ((irq % 4U) * 8U);
+ GIC_DIST_CPENDSGI(_gic_table[index].dist_hw_base, irq) = mask;
+ }
+}
+
+void arm_gic_set_configuration(rt_uint64_t index, int irq, uint32_t config)
+{
+ rt_uint64_t icfgr;
+ rt_uint64_t shift;
+
+ RT_ASSERT(index < ARM_GIC_MAX_NR);
+
+ irq = irq - _gic_table[index].offset;
+ RT_ASSERT(irq >= 0U);
+
+ icfgr = GIC_DIST_CONFIG(_gic_table[index].dist_hw_base, irq);
+ shift = (irq % 16U) << 1U;
+
+ icfgr &= (~(3U << shift));
+ icfgr |= (config << shift);
+
+ GIC_DIST_CONFIG(_gic_table[index].dist_hw_base, irq) = icfgr;
+}
+
+rt_uint64_t arm_gic_get_configuration(rt_uint64_t index, int irq)
+{
+ RT_ASSERT(index < ARM_GIC_MAX_NR);
+
+ irq = irq - _gic_table[index].offset;
+ RT_ASSERT(irq >= 0U);
+
+ return (GIC_DIST_CONFIG(_gic_table[index].dist_hw_base, irq) >> ((irq % 16U) >> 1U));
+}
+
+void arm_gic_clear_active(rt_uint64_t index, int irq)
+{
+ rt_uint64_t mask = 1U << (irq % 32U);
+
+ RT_ASSERT(index < ARM_GIC_MAX_NR);
+
+ irq = irq - _gic_table[index].offset;
+ RT_ASSERT(irq >= 0U);
+
+ GIC_DIST_ACTIVE_CLEAR(_gic_table[index].dist_hw_base, irq) = mask;
+}
+
+/* Set up the cpu mask for the specific interrupt */
+void arm_gic_set_cpu(rt_uint64_t index, int irq, unsigned int cpumask)
+{
+ rt_uint64_t old_tgt;
+
+ RT_ASSERT(index < ARM_GIC_MAX_NR);
+
+ irq = irq - _gic_table[index].offset;
+ RT_ASSERT(irq >= 0U);
+
+ old_tgt = GIC_DIST_TARGET(_gic_table[index].dist_hw_base, irq);
+
+ old_tgt &= ~(0x0FFUL << ((irq % 4U)*8U));
+ old_tgt |= cpumask << ((irq % 4U)*8U);
+
+ GIC_DIST_TARGET(_gic_table[index].dist_hw_base, irq) = old_tgt;
+}
+
+rt_uint64_t arm_gic_get_target_cpu(rt_uint64_t index, int irq)
+{
+ RT_ASSERT(index < ARM_GIC_MAX_NR);
+
+ irq = irq - _gic_table[index].offset;
+ RT_ASSERT(irq >= 0U);
+
+ return (GIC_DIST_TARGET(_gic_table[index].dist_hw_base, irq) >> ((irq % 4U) * 8U)) & 0xFFUL;
+}
+
+void arm_gic_set_priority(rt_uint64_t index, int irq, rt_uint64_t priority)
+{
+ rt_uint64_t mask;
+
+ RT_ASSERT(index < ARM_GIC_MAX_NR);
+
+ irq = irq - _gic_table[index].offset;
+ RT_ASSERT(irq >= 0U);
+
+ mask = GIC_DIST_PRI(_gic_table[index].dist_hw_base, irq);
+ mask &= ~(0xFFUL << ((irq % 4U) * 8U));
+ mask |= ((priority & 0xFFUL) << ((irq % 4U) * 8U));
+ GIC_DIST_PRI(_gic_table[index].dist_hw_base, irq) = mask;
+}
+
+rt_uint64_t arm_gic_get_priority(rt_uint64_t index, int irq)
+{
+ RT_ASSERT(index < ARM_GIC_MAX_NR);
+
+ irq = irq - _gic_table[index].offset;
+ RT_ASSERT(irq >= 0U);
+
+ return (GIC_DIST_PRI(_gic_table[index].dist_hw_base, irq) >> ((irq % 4U) * 8U)) & 0xFFUL;
+}
+
+void arm_gic_set_interface_prior_mask(rt_uint64_t index, rt_uint64_t priority)
+{
+ RT_ASSERT(index < ARM_GIC_MAX_NR);
+
+ /* set priority mask */
+ GIC_CPU_PRIMASK(_gic_table[index].cpu_hw_base) = priority & 0xFFUL;
+}
+
+rt_uint64_t arm_gic_get_interface_prior_mask(rt_uint64_t index)
+{
+ RT_ASSERT(index < ARM_GIC_MAX_NR);
+
+ return GIC_CPU_PRIMASK(_gic_table[index].cpu_hw_base);
+}
+
+void arm_gic_set_binary_point(rt_uint64_t index, rt_uint64_t binary_point)
+{
+ GIC_CPU_BINPOINT(_gic_table[index].cpu_hw_base) = binary_point & 0x7U;
+}
+
+rt_uint64_t arm_gic_get_binary_point(rt_uint64_t index)
+{
+ return GIC_CPU_BINPOINT(_gic_table[index].cpu_hw_base);
+}
+
+rt_uint64_t arm_gic_get_irq_status(rt_uint64_t index, int irq)
+{
+ rt_uint64_t pending;
+ rt_uint64_t active;
+
+ RT_ASSERT(index < ARM_GIC_MAX_NR);
+
+ irq = irq - _gic_table[index].offset;
+ RT_ASSERT(irq >= 0U);
+
+ active = (GIC_DIST_ACTIVE_SET(_gic_table[index].dist_hw_base, irq) >> (irq % 32U)) & 0x1UL;
+ pending = (GIC_DIST_PENDING_SET(_gic_table[index].dist_hw_base, irq) >> (irq % 32U)) & 0x1UL;
+
+ return ((active << 1U) | pending);
+}
+
+void arm_gic_send_sgi(rt_uint64_t index, int irq, rt_uint64_t target_list, rt_uint64_t filter_list)
+{
+ RT_ASSERT(index < ARM_GIC_MAX_NR);
+
+ irq = irq - _gic_table[index].offset;
+ RT_ASSERT(irq >= 0U);
+
+ GIC_DIST_SOFTINT(_gic_table[index].dist_hw_base) =
+ ((filter_list & 0x3U) << 24U) | ((target_list & 0xFFUL) << 16U) | (irq & 0x0FUL);
+}
+
+rt_uint64_t arm_gic_get_high_pending_irq(rt_uint64_t index)
+{
+ RT_ASSERT(index < ARM_GIC_MAX_NR);
+
+ return GIC_CPU_HIGHPRI(_gic_table[index].cpu_hw_base);
+}
+
+rt_uint64_t arm_gic_get_interface_id(rt_uint64_t index)
+{
+ RT_ASSERT(index < ARM_GIC_MAX_NR);
+
+ return GIC_CPU_IIDR(_gic_table[index].cpu_hw_base);
+}
+
+void arm_gic_set_group(rt_uint64_t index, int irq, rt_uint64_t group)
+{
+ uint32_t igroupr;
+ uint32_t shift;
+
+ RT_ASSERT(index < ARM_GIC_MAX_NR);
+ RT_ASSERT(group <= 1U);
+
+ irq = irq - _gic_table[index].offset;
+ RT_ASSERT(irq >= 0U);
+
+ igroupr = GIC_DIST_IGROUP(_gic_table[index].dist_hw_base, irq);
+ shift = (irq % 32U);
+ igroupr &= (~(1U << shift));
+ igroupr |= ((group & 0x1U) << shift);
+
+ GIC_DIST_IGROUP(_gic_table[index].dist_hw_base, irq) = igroupr;
+}
+
+rt_uint64_t arm_gic_get_group(rt_uint64_t index, int irq)
+{
+ RT_ASSERT(index < ARM_GIC_MAX_NR);
+
+ irq = irq - _gic_table[index].offset;
+ RT_ASSERT(irq >= 0U);
+
+ return (GIC_DIST_IGROUP(_gic_table[index].dist_hw_base, irq) >> (irq % 32U)) & 0x1UL;
+}
+
+int arm_gic_dist_init(rt_uint64_t index, rt_uint64_t dist_base, int irq_start)
+{
+ unsigned int gic_type, i;
+ rt_uint64_t cpumask = 1U << 0U;
+
+ RT_ASSERT(index < ARM_GIC_MAX_NR);
+
+ _gic_table[index].dist_hw_base = dist_base;
+ _gic_table[index].offset = irq_start;
+
+ /* Find out how many interrupts are supported. */
+ gic_type = GIC_DIST_TYPE(dist_base);
+ _gic_max_irq = ((gic_type & 0x1fU) + 1U) * 32U;
+
+ /*
+ * The GIC only supports up to 1020 interrupt sources.
+ * Limit this to either the architected maximum, or the
+ * platform maximum.
+ */
+ if (_gic_max_irq > 1020U)
+ {
+ _gic_max_irq = 1020U;
+ }
+ if (_gic_max_irq > ARM_GIC_NR_IRQS) /* the platform maximum interrupts */
+ {
+ _gic_max_irq = ARM_GIC_NR_IRQS;
+ }
+
+ cpumask |= cpumask << 8U;
+ cpumask |= cpumask << 16U;
+ cpumask |= cpumask << 24U;
+
+ GIC_DIST_CTRL(dist_base) = 0x0U;
+
+ /* Set all global interrupts to be level triggered, active low. */
+ for (i = 32U; i < _gic_max_irq; i += 16U)
+ {
+ GIC_DIST_CONFIG(dist_base, i) = 0x0U;
+ }
+
+ /* Set all global interrupts to this CPU only. */
+ for (i = 32U; i < _gic_max_irq; i += 4U)
+ {
+ GIC_DIST_TARGET(dist_base, i) = cpumask;
+ }
+
+ /* Set priority on all interrupts. */
+ for (i = 0U; i < _gic_max_irq; i += 4U)
+ {
+ GIC_DIST_PRI(dist_base, i) = 0xa0a0a0a0U;
+ }
+
+ /* Disable all interrupts. */
+ for (i = 0U; i < _gic_max_irq; i += 32U)
+ {
+ GIC_DIST_ENABLE_CLEAR(dist_base, i) = 0xffffffffU;
+ }
+
+ /* All interrupts defaults to IGROUP1(IRQ). */
+ for (i = 0U; i < _gic_max_irq; i += 32U)
+ {
+ GIC_DIST_IGROUP(dist_base, i) = 0U;
+ }
+
+ /* Enable group0 and group1 interrupt forwarding. */
+ GIC_DIST_CTRL(dist_base) = 0x01U;
+
+ return 0;
+}
+
+int arm_gic_cpu_init(rt_uint64_t index, rt_uint64_t cpu_base)
+{
+ RT_ASSERT(index < ARM_GIC_MAX_NR);
+
+ if (!_gic_table[index].cpu_hw_base)
+ {
+ _gic_table[index].cpu_hw_base = cpu_base;
+ }
+ cpu_base = _gic_table[index].cpu_hw_base;
+
+ GIC_CPU_PRIMASK(cpu_base) = 0xf0U;
+ GIC_CPU_BINPOINT(cpu_base) = 0x7U;
+ /* Enable CPU interrupt */
+ GIC_CPU_CTRL(cpu_base) = 0x01U;
+
+ return 0;
+}
+
+void arm_gic_dump_type(rt_uint64_t index)
+{
+ unsigned int gic_type;
+
+ gic_type = GIC_DIST_TYPE(_gic_table[index].dist_hw_base);
+ rt_kprintf("GICv%d on %p, max IRQs: %d, %s security extension(%08x)\n",
+ (GIC_DIST_ICPIDR2(_gic_table[index].dist_hw_base) >> 4U) & 0xfUL,
+ _gic_table[index].dist_hw_base,
+ _gic_max_irq,
+ gic_type & (1U << 10U) ? "has" : "no",
+ gic_type);
+}
+
+void arm_gic_dump(rt_uint64_t index)
+{
+ unsigned int i, k;
+
+ k = GIC_CPU_HIGHPRI(_gic_table[index].cpu_hw_base);
+ rt_kprintf("--- high pending priority: %d(%08x)\n", k, k);
+ rt_kprintf("--- hw mask ---\n");
+ for (i = 0U; i < _gic_max_irq / 32U; i++)
+ {
+ rt_kprintf("0x%08x, ", GIC_DIST_ENABLE_SET(_gic_table[index].dist_hw_base, i * 32U));
+ }
+ rt_kprintf("\n--- hw pending ---\n");
+ for (i = 0U; i < _gic_max_irq / 32U; i++)
+ {
+ rt_kprintf("0x%08x, ", GIC_DIST_PENDING_SET(_gic_table[index].dist_hw_base, i * 32U));
+ }
+ rt_kprintf("\n--- hw active ---\n");
+ for (i = 0U; i < _gic_max_irq / 32U; i++)
+ {
+ rt_kprintf("0x%08x, ", GIC_DIST_ACTIVE_SET(_gic_table[index].dist_hw_base, i * 32U));
+ }
+ rt_kprintf("\n");
+}
+
+long gic_dump(void)
+{
+ arm_gic_dump_type(0);
+ arm_gic_dump(0);
+
+ return 0;
+}
+MSH_CMD_EXPORT(gic_dump, show gic status);
+
diff --git a/libcpu/aarch64/common/gic.h b/libcpu/aarch64/common/gic.h
new file mode 100644
index 0000000000..54ab2bda18
--- /dev/null
+++ b/libcpu/aarch64/common/gic.h
@@ -0,0 +1,63 @@
+/*
+ * Copyright (c) 2006-2021, RT-Thread Development Team
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Change Logs:
+ * Date Author Notes
+ * 2013-07-20 Bernard first version
+ */
+
+#ifndef __GIC_H__
+#define __GIC_H__
+
+#include <rthw.h>
+#include <stdint.h>
+#include <board.h>
+
+int arm_gic_get_active_irq(rt_uint64_t index);
+void arm_gic_ack(rt_uint64_t index, int irq);
+
+void arm_gic_mask(rt_uint64_t index, int irq);
+void arm_gic_umask(rt_uint64_t index, int irq);
+
+rt_uint64_t arm_gic_get_pending_irq(rt_uint64_t index, int irq);
+void arm_gic_set_pending_irq(rt_uint64_t index, int irq);
+void arm_gic_clear_pending_irq(rt_uint64_t index, int irq);
+
+void arm_gic_set_configuration(rt_uint64_t index, int irq, uint32_t config);
+rt_uint64_t arm_gic_get_configuration(rt_uint64_t index, int irq);
+
+void arm_gic_clear_active(rt_uint64_t index, int irq);
+
+void arm_gic_set_cpu(rt_uint64_t index, int irq, unsigned int cpumask);
+rt_uint64_t arm_gic_get_target_cpu(rt_uint64_t index, int irq);
+
+void arm_gic_set_priority(rt_uint64_t index, int irq, rt_uint64_t priority);
+rt_uint64_t arm_gic_get_priority(rt_uint64_t index, int irq);
+
+void arm_gic_set_interface_prior_mask(rt_uint64_t index, rt_uint64_t priority);
+rt_uint64_t arm_gic_get_interface_prior_mask(rt_uint64_t index);
+
+void arm_gic_set_binary_point(rt_uint64_t index, rt_uint64_t binary_point);
+rt_uint64_t arm_gic_get_binary_point(rt_uint64_t index);
+
+rt_uint64_t arm_gic_get_irq_status(rt_uint64_t index, int irq);
+
+void arm_gic_send_sgi(rt_uint64_t index, int irq, rt_uint64_t target_list, rt_uint64_t filter_list);
+
+rt_uint64_t arm_gic_get_high_pending_irq(rt_uint64_t index);
+
+rt_uint64_t arm_gic_get_interface_id(rt_uint64_t index);
+
+void arm_gic_set_group(rt_uint64_t index, int irq, rt_uint64_t group);
+rt_uint64_t arm_gic_get_group(rt_uint64_t index, int irq);
+
+int arm_gic_dist_init(rt_uint64_t index, rt_uint64_t dist_base, int irq_start);
+int arm_gic_cpu_init(rt_uint64_t index, rt_uint64_t cpu_base);
+
+void arm_gic_dump_type(rt_uint64_t index);
+void arm_gic_dump(rt_uint64_t index);
+
+#endif
+
diff --git a/libcpu/aarch64/common/gic/SConscript b/libcpu/aarch64/common/gic/SConscript
deleted file mode 100644
index 28daac87ff..0000000000
--- a/libcpu/aarch64/common/gic/SConscript
+++ /dev/null
@@ -1,30 +0,0 @@
-# RT-Thread building script for component
-
-from building import *
-
-cwd = GetCurrentDir()
-CPPPATH = [cwd]
-
-gic390_group = Split('''
-gic_pl390.c
-''')
-
-gic400_group = Split('''
-gic_pl400.c
-''')
-
-gic500_group = Split('''
-gic_pl500.c
-''')
-
-src = ()
-if GetDepend('BSP_USING_GIC390'):
- src = gic390_group
-if GetDepend('BSP_USING_GIC400'):
- src = gic400_group
-if GetDepend('BSP_USING_GIC500'):
- src = gic500_group
-
-group = DefineGroup('gic', src, depend = ['BSP_USING_GIC'], CPPPATH = CPPPATH)
-
-Return('group')
diff --git a/libcpu/aarch64/common/gic/gic_pl390.c b/libcpu/aarch64/common/gic/gic_pl390.c
deleted file mode 100644
index a8e3b10d94..0000000000
--- a/libcpu/aarch64/common/gic/gic_pl390.c
+++ /dev/null
@@ -1,273 +0,0 @@
-/*
- * Copyright (c) 2006-2021, RT-Thread Development Team
- *
- * SPDX-License-Identifier: Apache-2.0
- *
- * Change Logs:
- * Date Author Notes
- * 2021-07-31 GuEe-GUI the first version
- */
-#include <rtthread.h>
-
-#include "gic_pl390.h"
-
-#define BIT(n) (1ul<<(n))
-#define MASK(n) (BIT(n)-1ul)
-
-#define IRQ_REG(IRQ) ((IRQ) / 32)
-#define IRQ_BIT(IRQ) BIT((IRQ) % 32)
-#define IRQ_MASK MASK(10)
-#define IRQ_SET_ALL 0xffffffff
-#define IS_IRQ_VALID(X) (((X)&IRQ_MASK) < GIC390_SPECIAL_IRQ_START)
-
-#define TARGET_CPU_ALLINT(CPU) \
-( \
- (((CPU) & 0xff) << 0 ) | \
- (((CPU) & 0xff) << 8 ) | \
- (((CPU) & 0xff) << 16) | \
- (((CPU) & 0xff) << 24) \
-)
-#define CPU(X) (1<<(X))
-#define TARGET_CPU0_ALLINT TARGET_CPU_ALLINT(CPU(0))
-
-/* memory map for GIC distributor */
-struct gic_dist_map
-{
- rt_uint32_t enable; /* 0x000 */
- rt_uint32_t ic_type; /* 0x004 */
- rt_uint32_t dist_ident; /* 0x008 */
- rt_uint32_t res1[29]; /* [0x00C, 0x080) */
-
- rt_uint32_t security[32]; /* [0x080, 0x100) */
-
- rt_uint32_t enable_set[32]; /* [0x100, 0x180) */
- rt_uint32_t enable_clr[32]; /* [0x180, 0x200) */
- rt_uint32_t pending_set[32]; /* [0x200, 0x280) */
- rt_uint32_t pending_clr[32]; /* [0x280, 0x300) */
- rt_uint32_t active[32]; /* [0x300, 0x380) */
- rt_uint32_t res2[32]; /* [0x380, 0x400) */
-
- rt_uint32_t priority[255]; /* [0x400, 0x7FC) */
- rt_uint32_t res3; /* 0x7FC */
-
- rt_uint32_t targets[255]; /* [0x800, 0xBFC) */
- rt_uint32_t res4; /* 0xBFC */
-
- rt_uint32_t config[64]; /* [0xC00, 0xD00) */
-
- rt_uint32_t spi[32]; /* [0xD00, 0xD80) */
- rt_uint32_t res5[20]; /* [0xD80, 0xDD0) */
- rt_uint32_t res6; /* 0xDD0 */
- rt_uint32_t legacy_int; /* 0xDD4 */
- rt_uint32_t res7[2]; /* [0xDD8, 0xDE0) */
- rt_uint32_t match_d; /* 0xDE0 */
- rt_uint32_t enable_d; /* 0xDE4 */
- rt_uint32_t res8[70]; /* [0xDE8, 0xF00) */
-
- rt_uint32_t sgi_control; /* 0xF00 */
- rt_uint32_t res9[3]; /* [0xF04, 0xF10) */
- rt_uint32_t sgi_pending_clr[4]; /* [0xF10, 0xF20) */
- rt_uint32_t res10[40]; /* [0xF20, 0xFC0) */
-
- rt_uint32_t periph_id[12]; /* [0xFC0, 0xFF0) */
- rt_uint32_t component_id[4]; /* [0xFF0, 0xFFF] */
-};
-
-/* memory map for GIC CPU interface */
-struct gic_cpu_iface_map
-{
- rt_uint32_t icontrol; /* 0x000 */
- rt_uint32_t pri_msk_c; /* 0x004 */
- rt_uint32_t pb_c; /* 0x008 */
- rt_uint32_t int_ack; /* 0x00C */
- rt_uint32_t eoi; /* 0x010 */
- rt_uint32_t run_priority; /* 0x014 */
- rt_uint32_t hi_pend; /* 0x018 */
- rt_uint32_t ns_alias_bp_c; /* 0x01C */
- rt_uint32_t ns_alias_ack; /* 0x020 GIC400 only */
- rt_uint32_t ns_alias_eoi; /* 0x024 GIC400 only */
- rt_uint32_t ns_alias_hi_pend; /* 0x028 GIC400 only */
-
- rt_uint32_t res1[5]; /* [0x02C, 0x040) */
-
- rt_uint32_t integ_en_c; /* 0x040 PL390 only */
- rt_uint32_t interrupt_out; /* 0x044 PL390 only */
- rt_uint32_t res2[2]; /* [0x048, 0x050) */
-
- rt_uint32_t match_c; /* 0x050 PL390 only */
- rt_uint32_t enable_c; /* 0x054 PL390 only */
-
- rt_uint32_t res3[30]; /* [0x058, 0x0FC) */
- rt_uint32_t active_priority[4]; /* [0x0D0, 0xDC] GIC400 only */
- rt_uint32_t ns_active_priority[4]; /* [0xE0,0xEC] GIC400 only */
- rt_uint32_t res4[3];
-
- rt_uint32_t cpu_if_ident; /* 0x0FC */
- rt_uint32_t res5[948]; /* [0x100. 0xFC0) */
-
- rt_uint32_t periph_id[8]; /* [0xFC0, 9xFF0) PL390 only */
- rt_uint32_t component_id[4]; /* [0xFF0, 0xFFF] PL390 only */
-};
-
-volatile struct gic_dist_map *gic_dist =
- (volatile struct gic_dist_map*)(GIC_PL390_DISTRIBUTOR_PPTR);
-
-volatile struct gic_cpu_iface_map *gic_cpuiface =
- (volatile struct gic_cpu_iface_map*)(GIC_PL390_CONTROLLER_PPTR);
-
-/*
- * The only sane way to get an GIC IRQ number that can be properly
- * ACKED later is through the int_ack register. Unfortunately, reading
- * this register changes the interrupt state to pending so future
- * reads will not return the same value For this reason, we have a
- * global variable to store the IRQ number.
- */
-static rt_uint32_t active_irq = GIC390_IRQ_NONE;
-
-rt_inline int is_irq_edge_triggered(int irq)
-{
- int word = irq / 16;
- int bit = ((irq & 0xf) * 2);
-
- return !!(gic_dist->config[word] & BIT(bit + 1));
-}
-
-rt_inline void dist_pending_clr(int irq)
-{
- int word = irq / 32;
- int bit = irq & 0x1f;
- gic_dist->pending_clr[word] = BIT(bit);
-}
-
-rt_inline void dist_init(void)
-{
- int i;
- int nirqs = 32 * ((gic_dist->ic_type & 0x1f) + 1);
- gic_dist->enable = 0;
-
- for (i = 0; i < nirqs; i += 32)
- {
- /* disable */
- gic_dist->enable_clr[i / 32] = IRQ_SET_ALL;
- /* clear pending */
- gic_dist->pending_clr[i / 32] = IRQ_SET_ALL;
- }
-
- /* reset interrupts priority */
- for (i = 32; i < nirqs; i += 4)
- {
- gic_dist->priority[i / 4] = 0x0;
- }
-
- /*
- * reset int target to cpu 0
- * (Should really query which processor we're running on and use that)
- */
- for (i = 0; i < nirqs; i += 4)
- {
- gic_dist->targets[i / 4] = TARGET_CPU0_ALLINT;
- }
-
- /* level-triggered, 1-N */
- for (i = 64; i < nirqs; i += 32)
- {
- gic_dist->config[i / 32] = 0;
- }
- /* enable the int controller */
- gic_dist->enable = 1;
-}
-
-rt_inline void cpu_iface_init(void)
-{
- rt_uint32_t i;
-
- /* For non-Exynos4, the registers are banked per CPU, need to clear them */
- gic_dist->enable_clr[0] = IRQ_SET_ALL;
- gic_dist->pending_clr[0] = IRQ_SET_ALL;
- gic_dist->priority[0] = 0x00;
- /* put everything in group 0 */
-
- /* clear any software generated interrupts */
- for (i = 0; i < 16; i += 4)
- {
- gic_dist->sgi_pending_clr[i / 4] = IRQ_SET_ALL;
- }
-
- gic_cpuiface->icontrol = 0;
- gic_cpuiface->pri_msk_c = 0x000000f0;
- gic_cpuiface->pb_c = 0x00000003;
-
- while (((i = gic_cpuiface->int_ack) & IRQ_MASK) != GIC390_IRQ_NONE)
- {
- gic_cpuiface->eoi = i;
- }
- gic_cpuiface->icontrol = 0x1;
-}
-
-
-void arm_gic_irq_init(void)
-{
- dist_init();
- cpu_iface_init();
-}
-
-int arm_gic_get_active_irq(void)
-{
- int irq;
- if (!IS_IRQ_VALID(active_irq))
- {
- active_irq = gic_cpuiface->int_ack;
- }
-
- if (IS_IRQ_VALID(active_irq))
- {
- irq = active_irq & IRQ_MASK;
- }
- else
- {
- irq = GIC390_IRQ_NONE;
- }
-
- return irq;
-}
-
-void arm_gic_mask(int irq)
-{
- int word = irq / 32;
- int bit = irq & 0x1f;
-
- gic_dist->enable_clr[word] = BIT(bit);
-}
-
-void arm_gic_umask(int irq)
-{
- int word = irq / 32;
- int bit = irq & 0x1f;
- gic_dist->enable_set[word] = BIT(bit);
-}
-
-void arm_gic_ack(int irq)
-{
- if (!(IS_IRQ_VALID(active_irq) && (active_irq & IRQ_MASK) == irq))
- {
- return;
- }
- if (is_irq_edge_triggered(irq))
- {
- dist_pending_clr(irq);
- }
-
- gic_cpuiface->eoi = active_irq;
- active_irq = GIC390_IRQ_NONE;
-}
-
-int rt_hw_interrupt_get_irq(void)
-{
- return arm_gic_get_active_irq();
-}
-
-void rt_hw_interrupt_ack(int fiq_irq)
-{
- return arm_gic_ack(fiq_irq);
-}
-
diff --git a/libcpu/aarch64/common/gic/gic_pl390.h b/libcpu/aarch64/common/gic/gic_pl390.h
deleted file mode 100644
index 7ea574967d..0000000000
--- a/libcpu/aarch64/common/gic/gic_pl390.h
+++ /dev/null
@@ -1,27 +0,0 @@
-/*
- * Copyright (c) 2006-2021, RT-Thread Development Team
- *
- * SPDX-License-Identifier: Apache-2.0
- *
- * Change Logs:
- * Date Author Notes
- * 2021-07-31 GuEe-GUI the first version
- */
-
-#ifndef GIC_PL390_H__
-#define GIC_PL390_H__
-
-#include <board.h>
-
-#define GIC390_SPECIAL_IRQ_START 1020
-#define GIC390_IRQ_NONE 1023
-
-void arm_gic_irq_init(void);
-
-int arm_gic_get_active_irq(void);
-void arm_gic_ack(int irq);
-
-void arm_gic_mask(int irq);
-void arm_gic_umask(int irq);
-
-#endif
diff --git a/libcpu/aarch64/common/gic/gic_pl400.c b/libcpu/aarch64/common/gic/gic_pl400.c
deleted file mode 100644
index ec690a1cc6..0000000000
--- a/libcpu/aarch64/common/gic/gic_pl400.c
+++ /dev/null
@@ -1,261 +0,0 @@
-/*
- * Copyright (c) 2006-2021, RT-Thread Development Team
- *
- * SPDX-License-Identifier: Apache-2.0
- *
- * Change Logs:
- * Date Author Notes
- * 2013-07-20 Bernard first version
- * 2014-04-03 Grissiom many enhancements
- * 2018-11-22 Jesven add rt_hw_ipi_send()
- * add rt_hw_ipi_handler_install()
- */
-#include <rtthread.h>
-
-#include "gic_pl400.h"
-#include "cp15.h"
-
-#define ARM_GIC_MAX_NR 1
-struct arm_gic
-{
- rt_uint32_t offset; /* the first interrupt index in the vector table */
-
- rt_uint32_t dist_hw_base; /* the base address of the gic distributor */
- rt_uint32_t cpu_hw_base; /* the base addrees of the gic cpu interface */
-};
-
-/* 'ARM_GIC_MAX_NR' is the number of cores */
-static struct arm_gic _gic_table[ARM_GIC_MAX_NR];
-
-static unsigned int _gic_max_irq;
-
-int arm_gic_get_active_irq(rt_uint32_t index)
-{
- int irq;
-
- RT_ASSERT(index < ARM_GIC_MAX_NR);
-
- irq = GIC_CPU_INTACK(_gic_table[index].cpu_hw_base);
- irq += _gic_table[index].offset;
- return irq;
-}
-
-void arm_gic_ack(rt_uint32_t index, int irq)
-{
- rt_uint32_t mask = 1 << (irq % 32);
-
- RT_ASSERT(index < ARM_GIC_MAX_NR);
-
- irq = irq - _gic_table[index].offset;
- RT_ASSERT(irq >= 0);
-
- GIC_DIST_ENABLE_CLEAR(_gic_table[index].dist_hw_base, irq) = mask;
- GIC_CPU_EOI(_gic_table[index].cpu_hw_base) = irq;
- GIC_DIST_ENABLE_SET(_gic_table[index].dist_hw_base, irq) = mask;
-}
-
-void arm_gic_mask(rt_uint32_t index, int irq)
-{
- rt_uint32_t mask = 1 << (irq % 32);
-
- RT_ASSERT(index < ARM_GIC_MAX_NR);
-
- irq = irq - _gic_table[index].offset;
- RT_ASSERT(irq >= 0);
-
- GIC_DIST_ENABLE_CLEAR(_gic_table[index].dist_hw_base, irq) = mask;
-}
-
-void arm_gic_clear_pending(rt_uint32_t index, int irq)
-{
- rt_uint32_t mask = 1 << (irq % 32);
-
- RT_ASSERT(index < ARM_GIC_MAX_NR);
-
- irq = irq - _gic_table[index].offset;
- RT_ASSERT(irq >= 0);
-
- GIC_DIST_PENDING_CLEAR(_gic_table[index].dist_hw_base, irq) = mask;
-}
-
-void arm_gic_clear_active(rt_uint32_t index, int irq)
-{
- rt_uint32_t mask = 1 << (irq % 32);
-
- RT_ASSERT(index < ARM_GIC_MAX_NR);
-
- irq = irq - _gic_table[index].offset;
- RT_ASSERT(irq >= 0);
-
- GIC_DIST_ACTIVE_CLEAR(_gic_table[index].dist_hw_base, irq) = mask;
-}
-
-/* Set up the cpu mask for the specific interrupt */
-void arm_gic_set_cpu(rt_uint32_t index, int irq, unsigned int cpumask)
-{
- rt_uint32_t old_tgt;
-
- RT_ASSERT(index < ARM_GIC_MAX_NR);
-
- irq = irq - _gic_table[index].offset;
- RT_ASSERT(irq >= 0);
-
- old_tgt = GIC_DIST_TARGET(_gic_table[index].dist_hw_base, irq);
-
- old_tgt &= ~(0x0FFUL << ((irq % 4)*8));
- old_tgt |= cpumask << ((irq % 4)*8);
-
- GIC_DIST_TARGET(_gic_table[index].dist_hw_base, irq) = old_tgt;
-}
-
-void arm_gic_umask(rt_uint32_t index, int irq)
-{
- rt_uint32_t mask = 1 << (irq % 32);
-
- RT_ASSERT(index < ARM_GIC_MAX_NR);
-
- irq = irq - _gic_table[index].offset;
- RT_ASSERT(irq >= 0);
-
- GIC_DIST_ENABLE_SET(_gic_table[index].dist_hw_base, irq) = mask;
-}
-
-void arm_gic_dump_type(rt_uint32_t index)
-{
- unsigned int gic_type;
-
- gic_type = GIC_DIST_TYPE(_gic_table[index].dist_hw_base);
- rt_kprintf("GICv%d on %p, max IRQs: %d, %s security extension(%08x)\n",
- (GIC_DIST_ICPIDR2(_gic_table[index].dist_hw_base) >> 4) & 0xf,
- _gic_table[index].dist_hw_base,
- _gic_max_irq,
- gic_type & (1 << 10) ? "has" : "no",
- gic_type);
-}
-
-void arm_gic_dump(rt_uint32_t index)
-{
- unsigned int i, k;
-
- k = GIC_CPU_HIGHPRI(_gic_table[index].cpu_hw_base);
- rt_kprintf("--- high pending priority: %d(%08x)\n", k, k);
- rt_kprintf("--- hw mask ---\n");
- for (i = 0; i < _gic_max_irq / 32; i++)
- {
- rt_kprintf("0x%08x, ",
- GIC_DIST_ENABLE_SET(_gic_table[index].dist_hw_base,
- i * 32));
- }
- rt_kprintf("\n--- hw pending ---\n");
- for (i = 0; i < _gic_max_irq / 32; i++)
- {
- rt_kprintf("0x%08x, ",
- GIC_DIST_PENDING_SET(_gic_table[index].dist_hw_base,
- i * 32));
- }
- rt_kprintf("\n--- hw active ---\n");
- for (i = 0; i < _gic_max_irq / 32; i++)
- {
- rt_kprintf("0x%08x, ",
- GIC_DIST_ACTIVE_SET(_gic_table[index].dist_hw_base,
- i * 32));
- }
- rt_kprintf("\n");
-}
-#ifdef RT_USING_FINSH
-#include <finsh.h>
-FINSH_FUNCTION_EXPORT_ALIAS(arm_gic_dump, gic, show gic status);
-#endif
-
-int arm_gic_dist_init(rt_uint32_t index, rt_uint32_t dist_base, int irq_start)
-{
- unsigned int gic_type, i;
- rt_uint32_t cpumask = 1 << 0;
-
- RT_ASSERT(index < ARM_GIC_MAX_NR);
-
- _gic_table[index].dist_hw_base = dist_base;
- _gic_table[index].offset = irq_start;
-
- /* Find out how many interrupts are supported. */
- gic_type = GIC_DIST_TYPE(dist_base);
- _gic_max_irq = ((gic_type & 0x1f) + 1) * 32;
-
- /*
- * The GIC only supports up to 1020 interrupt sources.
- * Limit this to either the architected maximum, or the
- * platform maximum.
- */
- if (_gic_max_irq > 1020)
- _gic_max_irq = 1020;
- if (_gic_max_irq > ARM_GIC_NR_IRQS) /* the platform maximum interrupts */
- _gic_max_irq = ARM_GIC_NR_IRQS;
-
- cpumask |= cpumask << 8;
- cpumask |= cpumask << 16;
- cpumask |= cpumask << 24;
-
- GIC_DIST_CTRL(dist_base) = 0x0;
-
- /* Set all global interrupts to be level triggered, active low. */
- for (i = 32; i < _gic_max_irq; i += 16)
- GIC_DIST_CONFIG(dist_base, i) = 0x0;
-
- /* Set all global interrupts to this CPU only. */
- for (i = 32; i < _gic_max_irq; i += 4)
- GIC_DIST_TARGET(dist_base, i) = cpumask;
-
- /* Set priority on all interrupts. */
- for (i = 0; i < _gic_max_irq; i += 4)
- GIC_DIST_PRI(dist_base, i) = 0xa0a0a0a0;
-
- /* Disable all interrupts. */
- for (i = 0; i < _gic_max_irq; i += 32)
- GIC_DIST_ENABLE_CLEAR(dist_base, i) = 0xffffffff;
-
-#if 0
- /* All interrupts defaults to IGROUP1(IRQ). */
- for (i = 0; i < _gic_max_irq; i += 32)
- GIC_DIST_IGROUP(dist_base, i) = 0xffffffff;
-#endif
- for (i = 0; i < _gic_max_irq; i += 32)
- GIC_DIST_IGROUP(dist_base, i) = 0;
-
- /* Enable group0 and group1 interrupt forwarding. */
- GIC_DIST_CTRL(dist_base) = 0x01;
-
- return 0;
-}
-
-int arm_gic_cpu_init(rt_uint32_t index, rt_uint32_t cpu_base)
-{
- RT_ASSERT(index < ARM_GIC_MAX_NR);
-
- _gic_table[index].cpu_hw_base = cpu_base;
-
- GIC_CPU_PRIMASK(cpu_base) = 0xf0;
- GIC_CPU_BINPOINT(cpu_base) = 0x7;
- /* Enable CPU interrupt */
- GIC_CPU_CTRL(cpu_base) = 0x01;
-
- return 0;
-}
-
-void arm_gic_set_group(rt_uint32_t index, int vector, int group)
-{
- /* As for GICv2, there are only group0 and group1. */
- RT_ASSERT(group <= 1);
- RT_ASSERT(vector < _gic_max_irq);
-
- if (group == 0)
- {
- GIC_DIST_IGROUP(_gic_table[index].dist_hw_base,
- vector) &= ~(1 << (vector % 32));
- }
- else if (group == 1)
- {
- GIC_DIST_IGROUP(_gic_table[index].dist_hw_base,
- vector) |= (1 << (vector % 32));
- }
-}
-
diff --git a/libcpu/aarch64/common/gic/gic_pl400.h b/libcpu/aarch64/common/gic/gic_pl400.h
deleted file mode 100644
index 9ca4835b9a..0000000000
--- a/libcpu/aarch64/common/gic/gic_pl400.h
+++ /dev/null
@@ -1,61 +0,0 @@
-/*
- * Copyright (c) 2006-2021, RT-Thread Development Team
- *
- * SPDX-License-Identifier: Apache-2.0
- *
- * Change Logs:
- * Date Author Notes
- * 2013-07-20 Bernard first version
- */
-
-#ifndef __GIC_PL400_H__
-#define __GIC_PL400_H__
-
-#include <rthw.h>
-#include <board.h>
-
-#define __REG32(x) (*((volatile unsigned int*)((rt_uint64_t)x)))
-
-#define GIC_CPU_CTRL(hw_base) __REG32((hw_base) + 0x00)
-#define GIC_CPU_PRIMASK(hw_base) __REG32((hw_base) + 0x04)
-#define GIC_CPU_BINPOINT(hw_base) __REG32((hw_base) + 0x08)
-#define GIC_CPU_INTACK(hw_base) __REG32((hw_base) + 0x0c)
-#define GIC_CPU_EOI(hw_base) __REG32((hw_base) + 0x10)
-#define GIC_CPU_RUNNINGPRI(hw_base) __REG32((hw_base) + 0x14)
-#define GIC_CPU_HIGHPRI(hw_base) __REG32((hw_base) + 0x18)
-
-#define GIC_DIST_CTRL(hw_base) __REG32((hw_base) + 0x000)
-#define GIC_DIST_TYPE(hw_base) __REG32((hw_base) + 0x004)
-#define GIC_DIST_IGROUP(hw_base, n) __REG32((hw_base) + 0x080 + ((n)/32) * 4)
-#define GIC_DIST_ENABLE_SET(hw_base, n) __REG32((hw_base) + 0x100 + ((n)/32) * 4)
-#define GIC_DIST_ENABLE_CLEAR(hw_base, n) __REG32((hw_base) + 0x180 + ((n)/32) * 4)
-#define GIC_DIST_PENDING_SET(hw_base, n) __REG32((hw_base) + 0x200 + ((n)/32) * 4)
-#define GIC_DIST_PENDING_CLEAR(hw_base, n) __REG32((hw_base) + 0x280 + ((n)/32) * 4)
-#define GIC_DIST_ACTIVE_SET(hw_base, n) __REG32((hw_base) + 0x300 + ((n)/32) * 4)
-#define GIC_DIST_ACTIVE_CLEAR(hw_base, n) __REG32((hw_base) + 0x380 + ((n)/32) * 4)
-#define GIC_DIST_PRI(hw_base, n) __REG32((hw_base) + 0x400 + ((n)/4) * 4)
-#define GIC_DIST_TARGET(hw_base, n) __REG32((hw_base) + 0x800 + ((n)/4) * 4)
-#define GIC_DIST_CONFIG(hw_base, n) __REG32((hw_base) + 0xc00 + ((n)/16) * 4)
-#define GIC_DIST_SOFTINT(hw_base) __REG32((hw_base) + 0xf00)
-#define GIC_DIST_CPENDSGI(hw_base, n) __REG32((hw_base) + 0xf10 + ((n)/4) * 4)
-#define GIC_DIST_ICPIDR2(hw_base) __REG32((hw_base) + 0xfe8)
-
-int arm_gic_dist_init(rt_uint32_t index, rt_uint32_t dist_base, int irq_start);
-int arm_gic_cpu_init(rt_uint32_t index, rt_uint32_t cpu_base);
-
-void arm_gic_mask(rt_uint32_t index, int irq);
-void arm_gic_umask(rt_uint32_t index, int irq);
-void arm_gic_set_cpu(rt_uint32_t index, int irq, unsigned int cpumask);
-void arm_gic_set_group(rt_uint32_t index, int vector, int group);
-
-int arm_gic_get_active_irq(rt_uint32_t index);
-void arm_gic_ack(rt_uint32_t index, int irq);
-
-void arm_gic_clear_active(rt_uint32_t index, int irq);
-void arm_gic_clear_pending(rt_uint32_t index, int irq);
-
-void arm_gic_dump_type(rt_uint32_t index);
-void arm_gic_dump(rt_uint32_t index);
-
-#endif
-
diff --git a/libcpu/aarch64/common/interrupt.c b/libcpu/aarch64/common/interrupt.c
new file mode 100644
index 0000000000..c4e3f20b46
--- /dev/null
+++ b/libcpu/aarch64/common/interrupt.c
@@ -0,0 +1,409 @@
+/*
+ * Copyright (c) 2006-2021, RT-Thread Development Team
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Change Logs:
+ * Date Author Notes
+ * 2013-07-06 Bernard first version
+ * 2018-11-22 Jesven add smp support
+ */
+
+#include <rthw.h>
+#include <rtthread.h>
+#include "interrupt.h"
+#include "gic.h"
+#include "armv8.h"
+#include "mmu.h"
+
+/* exception and interrupt handler table */
+struct rt_irq_desc isr_table[MAX_HANDLERS];
+
+#ifndef RT_USING_SMP
+/* Those variables will be accessed in ISR, so we need to share them. */
+rt_ubase_t rt_interrupt_from_thread = 0;
+rt_ubase_t rt_interrupt_to_thread = 0;
+rt_ubase_t rt_thread_switch_interrupt_flag = 0;
+#endif
+
+const unsigned int VECTOR_BASE = 0x00;
+extern int system_vectors;
+
+#ifdef RT_USING_SMP
+#define rt_interrupt_nest rt_cpu_self()->irq_nest
+#else
+extern volatile rt_uint8_t rt_interrupt_nest;
+#endif
+
+#ifndef BSP_USING_GIC
+static void default_isr_handler(int vector, void *param)
+{
+#ifdef RT_USING_SMP
+ rt_kprintf("cpu %d unhandled irq: %d\n", rt_hw_cpu_id(),vector);
+#else
+ rt_kprintf("unhandled irq: %d\n",vector);
+#endif
+}
+#endif
+
+void rt_hw_vector_init(void)
+{
+ rt_hw_set_current_vbar((rt_ubase_t)&system_vectors);
+}
+
+/**
+ * This function will initialize hardware interrupt
+ */
+void rt_hw_interrupt_init(void)
+{
+#ifndef BSP_USING_GIC
+ rt_uint32_t index;
+ /* initialize vector table */
+ rt_hw_vector_init();
+
+ /* initialize exceptions table */
+ rt_memset(isr_table, 0x00, sizeof(isr_table));
+
+ /* mask all of interrupts */
+ IRQ_DISABLE_BASIC = 0x000000ff;
+ IRQ_DISABLE1 = 0xffffffff;
+ IRQ_DISABLE2 = 0xffffffff;
+ for (index = 0; index < MAX_HANDLERS; index ++)
+ {
+ isr_table[index].handler = default_isr_handler;
+ isr_table[index].param = RT_NULL;
+#ifdef RT_USING_INTERRUPT_INFO
+ rt_strncpy(isr_table[index].name, "unknown", RT_NAME_MAX);
+ isr_table[index].counter = 0;
+#endif
+ }
+
+ /* init interrupt nest, and context in thread sp */
+ rt_interrupt_nest = 0;
+ rt_interrupt_from_thread = 0;
+ rt_interrupt_to_thread = 0;
+ rt_thread_switch_interrupt_flag = 0;
+#else
+ rt_uint64_t gic_cpu_base;
+ rt_uint64_t gic_dist_base;
+ rt_uint64_t gic_irq_start;
+
+ /* initialize vector table */
+ rt_hw_vector_init();
+
+ /* initialize exceptions table */
+ rt_memset(isr_table, 0x00, sizeof(isr_table));
+
+ /* initialize ARM GIC */
+ gic_dist_base = platform_get_gic_dist_base();
+ gic_cpu_base = platform_get_gic_cpu_base();
+
+ gic_irq_start = GIC_IRQ_START;
+
+ arm_gic_dist_init(0, gic_dist_base, gic_irq_start);
+ arm_gic_cpu_init(0, gic_cpu_base);
+#endif
+}
+
+/**
+ * This function will mask a interrupt.
+ * @param vector the interrupt number
+ */
+void rt_hw_interrupt_mask(int vector)
+{
+#ifndef BSP_USING_GIC
+ if (vector < 32)
+ {
+ IRQ_DISABLE1 = (1 << vector);
+ }
+ else if (vector < 64)
+ {
+ vector = vector % 32;
+ IRQ_DISABLE2 = (1 << vector);
+ }
+ else
+ {
+ vector = vector - 64;
+ IRQ_DISABLE_BASIC = (1 << vector);
+ }
+#else
+ arm_gic_mask(0, vector);
+#endif
+}
+
+/**
+ * This function will un-mask a interrupt.
+ * @param vector the interrupt number
+ */
+void rt_hw_interrupt_umask(int vector)
+{
+#ifndef BSP_USING_GIC
+if (vector < 32)
+ {
+ IRQ_ENABLE1 = (1 << vector);
+ }
+ else if (vector < 64)
+ {
+ vector = vector % 32;
+ IRQ_ENABLE2 = (1 << vector);
+ }
+ else
+ {
+ vector = vector - 64;
+ IRQ_ENABLE_BASIC = (1 << vector);
+ }
+#else
+ arm_gic_umask(0, vector);
+#endif
+}
+
+/**
+ * This function returns the active interrupt number.
+ * @param none
+ */
+int rt_hw_interrupt_get_irq(void)
+{
+#ifdef BSP_USING_GIC
+ return arm_gic_get_active_irq(0);
+#else
+ return 0;
+#endif
+}
+
+/**
+ * This function acknowledges the interrupt.
+ * @param vector the interrupt number
+ */
+void rt_hw_interrupt_ack(int vector)
+{
+#ifdef BSP_USING_GIC
+ arm_gic_ack(0, vector);
+#endif
+}
+
+/**
+ * This function set interrupt CPU targets.
+ * @param vector: the interrupt number
+ * cpu_mask: target cpus mask, one bit for one core
+ */
+void rt_hw_interrupt_set_target_cpus(int vector, unsigned int cpu_mask)
+{
+#ifdef BSP_USING_GIC
+ arm_gic_set_cpu(0, vector, cpu_mask);
+#endif
+}
+
+/**
+ * This function get interrupt CPU targets.
+ * @param vector: the interrupt number
+ * @return target cpus mask, one bit for one core
+ */
+unsigned int rt_hw_interrupt_get_target_cpus(int vector)
+{
+#ifdef BSP_USING_GIC
+ return arm_gic_get_target_cpu(0, vector);
+#else
+ return -RT_ERROR;
+#endif
+}
+
+/**
+ * This function set interrupt triger mode.
+ * @param vector: the interrupt number
+ * mode: interrupt triger mode; 0: level triger, 1: edge triger
+ */
+void rt_hw_interrupt_set_triger_mode(int vector, unsigned int mode)
+{
+#ifdef BSP_USING_GIC
+ arm_gic_set_configuration(0, vector, mode);
+#endif
+}
+
+/**
+ * This function get interrupt triger mode.
+ * @param vector: the interrupt number
+ * @return interrupt triger mode; 0: level triger, 1: edge triger
+ */
+unsigned int rt_hw_interrupt_get_triger_mode(int vector)
+{
+#ifdef BSP_USING_GIC
+ return arm_gic_get_configuration(0, vector);
+#else
+ return -RT_ERROR;
+#endif
+}
+
+/**
+ * This function set interrupt pending flag.
+ * @param vector: the interrupt number
+ */
+void rt_hw_interrupt_set_pending(int vector)
+{
+#ifdef BSP_USING_GIC
+ arm_gic_set_pending_irq(0, vector);
+#endif
+}
+
+/**
+ * This function get interrupt pending flag.
+ * @param vector: the interrupt number
+ * @return interrupt pending flag, 0: not pending; 1: pending
+ */
+unsigned int rt_hw_interrupt_get_pending(int vector)
+{
+#ifdef BSP_USING_GIC
+ return arm_gic_get_pending_irq(0, vector);
+#else
+ return -RT_ERROR;
+#endif
+}
+
+/**
+ * This function clear interrupt pending flag.
+ * @param vector: the interrupt number
+ */
+void rt_hw_interrupt_clear_pending(int vector)
+{
+#ifdef BSP_USING_GIC
+ arm_gic_clear_pending_irq(0, vector);
+#endif
+}
+
+/**
+ * This function set interrupt priority value.
+ * @param vector: the interrupt number
+ * priority: the priority of interrupt to set
+ */
+void rt_hw_interrupt_set_priority(int vector, unsigned int priority)
+{
+#ifdef BSP_USING_GIC
+ arm_gic_set_priority(0, vector, priority);
+#endif
+}
+
+/**
+ * This function get interrupt priority.
+ * @param vector: the interrupt number
+ * @return interrupt priority value
+ */
+unsigned int rt_hw_interrupt_get_priority(int vector)
+{
+#ifdef BSP_USING_GIC
+ return arm_gic_get_priority(0, vector);
+#else
+ return -RT_ERROR;
+#endif
+}
+
+/**
+ * This function set priority masking threshold.
+ * @param priority: priority masking threshold
+ */
+void rt_hw_interrupt_set_priority_mask(unsigned int priority)
+{
+#ifdef BSP_USING_GIC
+ arm_gic_set_interface_prior_mask(0, priority);
+#endif
+}
+
+/**
+ * This function get priority masking threshold.
+ * @param none
+ * @return priority masking threshold
+ */
+unsigned int rt_hw_interrupt_get_priority_mask(void)
+{
+#ifdef BSP_USING_GIC
+ return arm_gic_get_interface_prior_mask(0);
+#else
+ return -RT_ERROR;
+#endif
+}
+
+/**
+ * This function set priority grouping field split point.
+ * @param bits: priority grouping field split point
+ * @return 0: success; -1: failed
+ */
+int rt_hw_interrupt_set_prior_group_bits(unsigned int bits)
+{
+#ifdef BSP_USING_GIC
+ int status;
+
+ if (bits < 8)
+ {
+ arm_gic_set_binary_point(0, (7 - bits));
+ status = 0;
+ }
+ else
+ {
+ status = -1;
+ }
+
+ return (status);
+#else
+ return -RT_ERROR;
+#endif
+}
+
+/**
+ * This function get priority grouping field split point.
+ * @param none
+ * @return priority grouping field split point
+ */
+unsigned int rt_hw_interrupt_get_prior_group_bits(void)
+{
+#ifdef BSP_USING_GIC
+ unsigned int bp;
+
+ bp = arm_gic_get_binary_point(0) & 0x07;
+
+ return (7 - bp);
+#else
+ return -RT_ERROR;
+#endif
+}
+
+/**
+ * This function will install a interrupt service routine to a interrupt.
+ * @param vector the interrupt number
+ * @param new_handler the interrupt service routine to be installed
+ * @param old_handler the old interrupt service routine
+ */
+rt_isr_handler_t rt_hw_interrupt_install(int vector, rt_isr_handler_t handler,
+ void *param, const char *name)
+{
+ rt_isr_handler_t old_handler = RT_NULL;
+
+ if (vector < MAX_HANDLERS)
+ {
+ old_handler = isr_table[vector].handler;
+
+ if (handler != RT_NULL)
+ {
+#ifdef RT_USING_INTERRUPT_INFO
+ rt_strncpy(isr_table[vector].name, name, RT_NAME_MAX);
+#endif /* RT_USING_INTERRUPT_INFO */
+ isr_table[vector].handler = handler;
+ isr_table[vector].param = param;
+ }
+ }
+
+ return old_handler;
+}
+
+#ifdef RT_USING_SMP
+void rt_hw_ipi_send(int ipi_vector, unsigned int cpu_mask)
+{
+#ifdef BSP_USING_GIC
+ arm_gic_send_sgi(0, ipi_vector, cpu_mask, 0);
+#endif
+}
+
+void rt_hw_ipi_handler_install(int ipi_vector, rt_isr_handler_t ipi_isr_handler)
+{
+ /* note: ipi_vector maybe different with irq_vector */
+ rt_hw_interrupt_install(ipi_vector, ipi_isr_handler, 0, "IPI_HANDLER");
+}
+#endif
+
diff --git a/libcpu/aarch64/common/interrupt.h b/libcpu/aarch64/common/interrupt.h
new file mode 100644
index 0000000000..dda6c5534a
--- /dev/null
+++ b/libcpu/aarch64/common/interrupt.h
@@ -0,0 +1,60 @@
+/*
+ * Copyright (c) 2006-2021, RT-Thread Development Team
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Change Logs:
+ * Date Author Notes
+ * 2013-07-06 Bernard first version
+ */
+
+#ifndef __INTERRUPT_H__
+#define __INTERRUPT_H__
+
+#include <rthw.h>
+#include <board.h>
+
+#define INT_IRQ 0x00
+#define INT_FIQ 0x01
+
+#define IRQ_MODE_TRIG_LEVEL (0x00) /* Trigger: level triggered interrupt */
+#define IRQ_MODE_TRIG_EDGE (0x01) /* Trigger: edge triggered interrupt */
+
+void rt_hw_vector_init(void);
+
+void rt_hw_interrupt_init(void);
+void rt_hw_interrupt_mask(int vector);
+void rt_hw_interrupt_umask(int vector);
+
+int rt_hw_interrupt_get_irq(void);
+void rt_hw_interrupt_ack(int vector);
+
+void rt_hw_interrupt_set_target_cpus(int vector, unsigned int cpu_mask);
+unsigned int rt_hw_interrupt_get_target_cpus(int vector);
+
+void rt_hw_interrupt_set_triger_mode(int vector, unsigned int mode);
+unsigned int rt_hw_interrupt_get_triger_mode(int vector);
+
+void rt_hw_interrupt_set_pending(int vector);
+unsigned int rt_hw_interrupt_get_pending(int vector);
+void rt_hw_interrupt_clear_pending(int vector);
+
+void rt_hw_interrupt_set_priority(int vector, unsigned int priority);
+unsigned int rt_hw_interrupt_get_priority(int vector);
+
+void rt_hw_interrupt_set_priority_mask(unsigned int priority);
+unsigned int rt_hw_interrupt_get_priority_mask(void);
+
+int rt_hw_interrupt_set_prior_group_bits(unsigned int bits);
+unsigned int rt_hw_interrupt_get_prior_group_bits(void);
+
+rt_isr_handler_t rt_hw_interrupt_install(int vector, rt_isr_handler_t handler,
+ void *param, const char *name);
+
+#ifdef RT_USING_SMP
+void rt_hw_ipi_send(int ipi_vector, unsigned int cpu_mask);
+void rt_hw_ipi_handler_install(int ipi_vector, rt_isr_handler_t ipi_isr_handler);
+#endif
+
+#endif
+
diff --git a/libcpu/aarch64/common/stack.c b/libcpu/aarch64/common/stack.c
new file mode 100644
index 0000000000..0fe00d8674
--- /dev/null
+++ b/libcpu/aarch64/common/stack.c
@@ -0,0 +1,89 @@
+/*
+ * Copyright (c) 2006-2021, RT-Thread Development Team
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Change Logs:
+ * Date Author Notes
+ * 2011-09-23 Bernard the first version
+ * 2011-10-05 Bernard add thumb mode
+ */
+#include <rtthread.h>
+#include <board.h>
+
+#include <armv8.h>
+
+#define INITIAL_SPSR_EL3 (PSTATE_EL3 | SP_EL0)
+#define INITIAL_SPSR_EL2 (PSTATE_EL2 | SP_EL0)
+#define INITIAL_SPSR_EL1 (PSTATE_EL1 | SP_EL0)
+
+/**
+ * This function will initialize thread stack
+ *
+ * @param tentry the entry of thread
+ * @param parameter the parameter of entry
+ * @param stack_addr the beginning stack address
+ * @param texit the function will be called when thread exit
+ *
+ * @return stack address
+ */
+rt_uint8_t *rt_hw_stack_init(void *tentry, void *parameter, rt_uint8_t *stack_addr, void *texit)
+{
+ rt_ubase_t *stk;
+ rt_ubase_t current_el;
+
+ stk = (rt_ubase_t*)stack_addr;
+
+ *(--stk) = ( rt_ubase_t ) 11; /* X1 */
+ *(--stk) = ( rt_ubase_t ) parameter; /* X0 */
+ *(--stk) = ( rt_ubase_t ) 33; /* X3 */
+ *(--stk) = ( rt_ubase_t ) 22; /* X2 */
+ *(--stk) = ( rt_ubase_t ) 55; /* X5 */
+ *(--stk) = ( rt_ubase_t ) 44; /* X4 */
+ *(--stk) = ( rt_ubase_t ) 77; /* X7 */
+ *(--stk) = ( rt_ubase_t ) 66; /* X6 */
+ *(--stk) = ( rt_ubase_t ) 99; /* X9 */
+ *(--stk) = ( rt_ubase_t ) 88; /* X8 */
+ *(--stk) = ( rt_ubase_t ) 11; /* X11 */
+ *(--stk) = ( rt_ubase_t ) 10; /* X10 */
+ *(--stk) = ( rt_ubase_t ) 13; /* X13 */
+ *(--stk) = ( rt_ubase_t ) 12; /* X12 */
+ *(--stk) = ( rt_ubase_t ) 15; /* X15 */
+ *(--stk) = ( rt_ubase_t ) 14; /* X14 */
+ *(--stk) = ( rt_ubase_t ) 17; /* X17 */
+ *(--stk) = ( rt_ubase_t ) 16; /* X16 */
+ *(--stk) = ( rt_ubase_t ) 19; /* X19 */
+ *(--stk) = ( rt_ubase_t ) 18; /* X18 */
+ *(--stk) = ( rt_ubase_t ) 21; /* X21 */
+ *(--stk) = ( rt_ubase_t ) 20; /* X20 */
+ *(--stk) = ( rt_ubase_t ) 23; /* X23 */
+ *(--stk) = ( rt_ubase_t ) 22; /* X22 */
+ *(--stk) = ( rt_ubase_t ) 25; /* X25 */
+ *(--stk) = ( rt_ubase_t ) 24; /* X24 */
+ *(--stk) = ( rt_ubase_t ) 27; /* X27 */
+ *(--stk) = ( rt_ubase_t ) 26; /* X26 */
+ *(--stk) = ( rt_ubase_t ) 29; /* X29 */
+ *(--stk) = ( rt_ubase_t ) 28; /* X28 */
+ *(--stk) = ( rt_ubase_t ) 0; /* XZR - has no effect, used so there are an even number of registers. */
+ *(--stk) = ( rt_ubase_t ) texit; /* X30 - procedure call link register. */
+
+ current_el = rt_hw_get_current_el();
+
+ if(current_el == 3)
+ {
+ *(--stk) = INITIAL_SPSR_EL3;
+ }
+ else if(current_el == 2)
+ {
+ *(--stk) = INITIAL_SPSR_EL2;
+ }
+ else
+ {
+ *(--stk) = INITIAL_SPSR_EL1;
+ }
+
+ *(--stk) = ( rt_ubase_t ) tentry; /* Exception return address. */
+
+ /* return task's current stack address */
+ return (rt_uint8_t *)stk;
+}
diff --git a/libcpu/aarch64/common/trap.c b/libcpu/aarch64/common/trap.c
new file mode 100644
index 0000000000..e93ad78fc5
--- /dev/null
+++ b/libcpu/aarch64/common/trap.c
@@ -0,0 +1,172 @@
+/*
+ * Copyright (c) 2006-2021, RT-Thread Development Team
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Change Logs:
+ * Date Author Notes
+ * 2013-07-20 Bernard first version
+ */
+
+#include <rtthread.h>
+#include <rthw.h>
+#include <board.h>
+
+#include <armv8.h>
+#include <interrupt.h>
+
+#ifdef RT_USING_FINSH
+extern long list_thread(void);
+#endif
+
+/**
+ * this function will show registers of CPU
+ *
+ * @param regs the registers point
+ */
+void rt_hw_show_register(struct rt_hw_exp_stack *regs)
+{
+ rt_kprintf("Execption:\n");
+ rt_kprintf("X00:0x%16.16p X01:0x%16.16p X02:0x%16.16p X03:0x%16.16p\n", (void *)regs->x0, (void *)regs->x1, (void *)regs->x2, (void *)regs->x3);
+ rt_kprintf("X04:0x%16.16p X05:0x%16.16p X06:0x%16.16p X07:0x%16.16p\n", (void *)regs->x4, (void *)regs->x5, (void *)regs->x6, (void *)regs->x7);
+ rt_kprintf("X08:0x%16.16p X09:0x%16.16p X10:0x%16.16p X11:0x%16.16p\n", (void *)regs->x8, (void *)regs->x9, (void *)regs->x10, (void *)regs->x11);
+ rt_kprintf("X12:0x%16.16p X13:0x%16.16p X14:0x%16.16p X15:0x%16.16p\n", (void *)regs->x12, (void *)regs->x13, (void *)regs->x14, (void *)regs->x15);
+ rt_kprintf("X16:0x%16.16p X17:0x%16.16p X18:0x%16.16p X19:0x%16.16p\n", (void *)regs->x16, (void *)regs->x17, (void *)regs->x18, (void *)regs->x19);
+ rt_kprintf("X20:0x%16.16p X21:0x%16.16p X22:0x%16.16p X23:0x%16.16p\n", (void *)regs->x20, (void *)regs->x21, (void *)regs->x22, (void *)regs->x23);
+ rt_kprintf("X24:0x%16.16p X25:0x%16.16p X26:0x%16.16p X27:0x%16.16p\n", (void *)regs->x24, (void *)regs->x25, (void *)regs->x26, (void *)regs->x27);
+ rt_kprintf("X28:0x%16.16p X29:0x%16.16p X30:0x%16.16p\n", (void *)regs->x28, (void *)regs->x29, (void *)regs->x30);
+ rt_kprintf("SPSR :0x%16.16p\n", (void *)regs->spsr);
+ rt_kprintf("EPC :0x%16.16p\n", (void *)regs->pc);
+}
+
+/**
+ * When comes across an instruction which it cannot handle,
+ * it takes the undefined instruction trap.
+ *
+ * @param regs system registers
+ *
+ * @note never invoke this function in application
+ */
+void rt_hw_trap_error(struct rt_hw_exp_stack *regs)
+{
+ rt_kprintf("error exception:\n");
+ rt_hw_show_register(regs);
+#ifdef RT_USING_FINSH
+ list_thread();
+#endif
+ rt_hw_cpu_shutdown();
+}
+
+void rt_hw_trap_irq(void)
+{
+#ifndef BSP_USING_GIC
+ void *param;
+ uint32_t irq;
+ rt_isr_handler_t isr_func;
+ extern struct rt_irq_desc isr_table[];
+ uint32_t value = 0;
+ value = IRQ_PEND_BASIC & 0x3ff;
+
+#ifdef BSP_USING_CORETIMER
+ uint32_t cpu_id = 0;
+#ifdef RT_USING_SMP
+ cpu_id = rt_hw_cpu_id();
+#endif
+ uint32_t int_source = CORE_IRQSOURCE(cpu_id) & 0x3ff;
+ if (int_source & 0x02)
+ {
+ isr_func = isr_table[IRQ_ARM_TIMER].handler;
+#ifdef RT_USING_INTERRUPT_INFO
+ isr_table[IRQ_ARM_TIMER].counter++;
+#endif
+ if (isr_func)
+ {
+ param = isr_table[IRQ_ARM_TIMER].param;
+ isr_func(IRQ_ARM_TIMER, param);
+ }
+ }
+#endif
+
+ /* local interrupt*/
+ if (value)
+ {
+ if (value & (1 << 8))
+ {
+ value = IRQ_PEND1;
+ irq = __rt_ffs(value) - 1;
+ }
+ else if (value & (1 << 9))
+ {
+ value = IRQ_PEND2;
+ irq = __rt_ffs(value) + 31;
+ }
+ else
+ {
+ value &= 0x0f;
+ irq = __rt_ffs(value) + 63;
+ }
+
+ /* get interrupt service routine */
+ isr_func = isr_table[irq].handler;
+#ifdef RT_USING_INTERRUPT_INFO
+ isr_table[irq].counter++;
+#endif
+ if (isr_func)
+ {
+ /* Interrupt for myself. */
+ param = isr_table[irq].param;
+ /* turn to interrupt service routine */
+ isr_func(irq, param);
+ }
+ }
+#else
+ void *param;
+ int ir;
+ rt_isr_handler_t isr_func;
+ extern struct rt_irq_desc isr_table[];
+
+ ir = rt_hw_interrupt_get_irq();
+
+ if (ir == 1023)
+ {
+ /* Spurious interrupt */
+ return;
+ }
+
+ /* get interrupt service routine */
+ isr_func = isr_table[ir].handler;
+#ifdef RT_USING_INTERRUPT_INFO
+ isr_table[ir].counter++;
+#endif
+ if (isr_func)
+ {
+ /* Interrupt for myself. */
+ param = isr_table[ir].param;
+ /* turn to interrupt service routine */
+ isr_func(ir, param);
+ }
+
+ /* end of interrupt */
+ rt_hw_interrupt_ack(ir);
+#endif
+}
+
+void rt_hw_trap_fiq(void)
+{
+ void *param;
+ int ir;
+ rt_isr_handler_t isr_func;
+ extern struct rt_irq_desc isr_table[];
+
+ ir = rt_hw_interrupt_get_irq();
+
+ /* get interrupt service routine */
+ isr_func = isr_table[ir].handler;
+ param = isr_table[ir].param;
+
+ /* turn to interrupt service routine */
+ isr_func(ir, param);
+
+ /* end of interrupt */
+ rt_hw_interrupt_ack(ir);
+}
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