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-rw-r--r--libcpu/arm/am335x/am33xx.h5
-rw-r--r--libcpu/arm/am335x/interrupt.c10
-rw-r--r--libcpu/arm/am335x/interrupt.h209
3 files changed, 224 insertions, 0 deletions
diff --git a/libcpu/arm/am335x/am33xx.h b/libcpu/arm/am335x/am33xx.h
index 3112a8ac15..c74a0c1d62 100644
--- a/libcpu/arm/am335x/am33xx.h
+++ b/libcpu/arm/am335x/am33xx.h
@@ -98,6 +98,8 @@
#define CM_PER_UART4_CLKCTRL(base) (CM_PER(base) + 0x78)
#define CM_PER_UART5_CLKCTRL(base) (CM_PER(base) + 0x38)
#define CM_WKUP(base) ((base) + 0x400)
+#define CM_WKUP_CLKSTCTRL(base) (CM_WKUP(base) + 0)
+#define CM_WKUP_UART0_CLKCTRL(base) (CM_WKUP(base) + 0xB4)
#define CM_DPLL(base) ((base) + 0x500)
#define CM_MPU(base) ((base) + 0x600)
#define CM_DEVICE(base) ((base) + 0x700)
@@ -194,6 +196,9 @@
#define PRM_PER_PWRSTST_REG(base) REG32(PRM_PER_PWRSTST(base))
#define PRM_PER_PWRSTCTRL_REG(base) REG32(PRM_PER_PWRSTCTRL(base))
+#define CM_WKUP_CLKSTCTRL_REG(base) REG32(CM_WKUP_CLKSTCTRL(base))
+#define CM_WKUP_UART0_CLKCTRL_REG(base) REG32(CM_WKUP_UART0_CLKCTRL(base))
+
#define CM_DPLL_CLKSEL_TIMER7_CLK(base) REG32(CM_DPLL(base) + 0x4)
#define CM_DPLL_CLKSEL_TIMER2_CLK(base) REG32(CM_DPLL(base) + 0x8)
diff --git a/libcpu/arm/am335x/interrupt.c b/libcpu/arm/am335x/interrupt.c
index c4c5e8d7eb..1810a92a65 100644
--- a/libcpu/arm/am335x/interrupt.c
+++ b/libcpu/arm/am335x/interrupt.c
@@ -75,6 +75,16 @@ static void rt_hw_vector_init(void)
*/
void rt_hw_interrupt_init(void)
{
+ /* Reset the ARM interrupt controller */
+ INTC_SYSCONFIG(AINTC_BASE) = INTC_SYSCONFIG_SOFTRESET;
+
+ /* Wait for the reset to complete */
+ while((INTC_SYSSTATUS(AINTC_BASE)
+ & INTC_SYSSTATUS_RESETDONE) != INTC_SYSSTATUS_RESETDONE);
+
+ /* Enable any interrupt generation by setting priority threshold */
+ INTC_THRESHOLD(AINTC_BASE) = INTC_THRESHOLD_PRIORITYTHRESHOLD;
+
/* initialize vector table */
rt_hw_vector_init();
diff --git a/libcpu/arm/am335x/interrupt.h b/libcpu/arm/am335x/interrupt.h
index 90f392f407..35239b198f 100644
--- a/libcpu/arm/am335x/interrupt.h
+++ b/libcpu/arm/am335x/interrupt.h
@@ -14,6 +14,9 @@
#define INT_IRQ 0x00
#define INT_FIQ 0x01
+/*************************************************************************\
+ * Registers Definition
+\*************************************************************************/
#define INTC_REVISION(hw_base) REG32((hw_base) + 0x0)
#define INTC_SYSCONFIG(hw_base) REG32((hw_base) + 0x10)
#define INTC_SYSSTATUS(hw_base) REG32((hw_base) + 0x14)
@@ -37,6 +40,212 @@
#define INTC_PENDING_FIQ(hw_base, n) REG32((hw_base) + 0x9c + ((n) * 0x20))
#define INTC_ILR(hw_base, n) REG32((hw_base) + 0x100 + ((n) * 0x04))
+/**************************************************************************\
+* Field Definition Macros
+\**************************************************************************/
+
+/* REVISION */
+#define INTC_REVISION_REV (0x000000FFu)
+#define INTC_REVISION_REV_SHIFT (0x00000000u)
+
+/* SYSCONFIG */
+#define INTC_SYSCONFIG_SOFTRESET (0x00000002u)
+#define INTC_SYSCONFIG_SOFTRESET_SHIFT (0x00000001u)
+
+#define INTC_SYSCONFIG_AUTOIDLE (0x00000001u)
+#define INTC_SYSCONFIG_AUTOIDLE_SHIFT (0x00000000u)
+
+/* SYSSTATUS */
+#define INTC_SYSSTATUS_RESETDONE (0x00000001u)
+#define INTC_SYSSTATUS_RESETDONE_SHIFT (0x00000000u)
+
+/* SIR_IRQ */
+#define INTC_SIR_IRQ_SPURIOUSIRQ (0xFFFFFF80u)
+#define INTC_SIR_IRQ_SPURIOUSIRQ_SHIFT (0x00000007u)
+
+#define INTC_SIR_IRQ_ACTIVEIRQ (0x0000007F)
+#define INTC_SIR_IRQ_ACTIVEIRQ_SHIFT (0x00000000)
+
+/* SIR_FIQ */
+#define INTC_SIR_FIQ_SPURIOUSFIQ (0xFFFFFF80)
+#define INTC_SIR_FIQ_SPURIOUSFIQ_SHIFT (0x00000007)
+
+#define INTC_SIR_FIQ_ACTIVEFIQ (0x0000007F)
+#define INTC_SIR_FIQ_ACTIVEFIQ_SHIFT (0x00000000)
+
+/* CONTROL */
+#define INTC_CONTROL_NEWFIQAGR (0x00000002)
+#define INTC_CONTROL_NEWFIQAGR_SHIFT (0x00000001)
+
+#define INTC_CONTROL_NEWIRQAGR (0x00000001)
+#define INTC_CONTROL_NEWIRQAGR_SHIFT (0x00000000)
+
+/* PROTECTION */
+#define INTC_PROTECTION_PROTECTION (0x00000001u)
+#define INTC_PROTECTION_PROTECTION_SHIFT (0x00000000u)
+
+/* IDLE */
+#define INTC_IDLE_TURBO (0x00000002u)
+#define INTC_IDLE_TURBO_SHIFT (0x00000001u)
+
+#define INTC_IDLE_FUNCIDLE (0x00000001u)
+#define INTC_IDLE_FUNCIDLE_SHIFT (0x00000000u)
+
+/* IRQ_PRIORITY */
+#define INTC_IRQ_PRIORITY_SPURIOUSIRQFLAG (0xFFFFFFC0u)
+#define INTC_IRQ_PRIORITY_SPURIOUSIRQFLAG_SHIFT (0x00000006u)
+
+#define INTC_IRQ_PRIORITY_IRQPRIORITY (0x0000003Fu)
+#define INTC_IRQ_PRIORITY_IRQPRIORITY_SHIFT (0x00000000u)
+
+/* FIQ_PRIORITY */
+#define INTC_FIQ_PRIORITY_SPURIOUSFIQFLAG (0xFFFFFFC0u)
+#define INTC_FIQ_PRIORITY_SPURIOUSFIQFLAG_SHIFT (0x00000006u)
+
+#define INTC_FIQ_PRIORITY_FIQPRIORITY (0x0000003Fu)
+#define INTC_FIQ_PRIORITY_FIQPRIORITY_SHIFT (0x00000000u)
+
+/* THRESHOLD */
+#define INTC_THRESHOLD_PRIORITYTHRESHOLD (0x000000FFu)
+#define INTC_THRESHOLD_PRIORITYTHRESHOLD_SHIFT (0x00000000u)
+
+/* SICR */
+#define INTC_SICR_GLOBALMASK (0x00000040u)
+#define INTC_SICR_GLOBALMASK_SHIFT (0x00000006u)
+
+#define INTC_SICR_SOFTRESETINH (0x00000020u)
+#define INTC_SICR_SOFTRESETINH_SHIFT (0x00000005u)
+
+#define INTC_SICR_PUBLICMASKFEEDBACK (0x00000010u)
+#define INTC_SICR_PUBLICMASKFEEDBACK_SHIFT (0x00000004u)
+
+#define INTC_SICR_PUBLICINHIBIT (0x00000008u)
+#define INTC_SICR_PUBLICINHIBIT_SHIFT (0x00000003u)
+
+#define INTC_SICR_AUTOINHIBIT (0x00000004u)
+#define INTC_SICR_AUTOINHIBIT_SHIFT (0x00000002u)
+
+#define INTC_SICR_SSMFIQENABLE (0x00000002u)
+#define INTC_SICR_SSMFIQENABLE_SHIFT (0x00000001u)
+
+#define INTC_SICR_SSMFIQSTATUS (0x00000001u)
+#define INTC_SICR_SSMFIQSTATUS_SHIFT (0x00000000u)
+
+/* SCR0 */
+#define INTC_SCR0_SECUREENABLE (0xFFFFFFFFu)
+#define INTC_SCR0_SECUREENABLE_SHIFT (0x00000000u)
+
+/* SCR1 */
+#define INTC_SCR1_SECUREENABLE (0xFFFFFFFFu)
+#define INTC_SCR1_SECUREENABLE_SHIFT (0x00000000u)
+
+/* SCR2 */
+#define INTC_SCR2_SECUREENABLE (0xFFFFFFFFu)
+#define INTC_SCR2_SECUREENABLE_SHIFT (0x00000000u)
+
+/* ITR0 */
+#define INTC_ITR0_ITR (0xFFFFFFFFu)
+#define INTC_ITR0_ITR_SHIFT (0x00000000u)
+
+/* MIR0 */
+#define INTC_MIR0_MIR (0xFFFFFFFFu)
+#define INTC_MIR0_MIR_SHIFT (0x00000000u)
+
+/* MIR_CLEAR0 */
+#define INTC_MIR_CLEAR0_MIRCLEAR (0xFFFFFFFFu)
+#define INTC_MIR_CLEAR0_MIRCLEAR_SHIFT (0x00000000u)
+
+/* MIR_SET0 */
+#define INTC_MIR_SET0_MIRSET (0xFFFFFFFFu)
+#define INTC_MIR_SET0_MIRSET_SHIFT (0x00000000u)
+
+/* ISR_SET0 */
+#define INTC_ISR_SET0_ISRSET (0xFFFFFFFFu)
+#define INTC_ISR_SET0_ISRSET_SHIFT (0x00000000u)
+
+/* ISR_CLEAR0 */
+#define INTC_ISR_CLEAR0_ISRCLEAR (0xFFFFFFFFu)
+#define INTC_ISR_CLEAR0_ISRCLEAR_SHIFT (0x00000000u)
+
+/* PENDING_IRQ0 */
+#define INTC_PENDING_IRQ0_PENDING_IRQ (0xFFFFFFFFu)
+#define INTC_PENDING_IRQ0_PENDING_IRQ_SHIFT (0x00000000u)
+
+/* PENDING_FIQ0 */
+#define INTC_PENDING_FIQ0_PENDING_FIQ (0xFFFFFFFFu)
+#define INTC_PENDING_FIQ0_PENDING_FIQ_SHIFT (0x00000000u)
+
+/* ITR1 */
+#define INTC_ITR1_ITR (0xFFFFFFFFu)
+#define INTC_ITR1_ITR_SHIFT (0x00000000u)
+
+/* MIR1 */
+#define INTC_MIR1_MIR (0xFFFFFFFFu)
+#define INTC_MIR1_MIR_SHIFT (0x00000000u)
+
+/* MIR_CLEAR1 */
+#define INTC_MIR_CLEAR1_MIRCLEAR (0xFFFFFFFFu)
+#define INTC_MIR_CLEAR1_MIRCLEAR_SHIFT (0x00000000u)
+
+/* MIR_SET1 */
+#define INTC_MIR_SET1_MIRSET (0xFFFFFFFFu)
+#define INTC_MIR_SET1_MIRSET_SHIFT (0x00000000u)
+
+/* ISR_SET1 */
+#define INTC_ISR_SET1_ISRSET (0xFFFFFFFFu)
+#define INTC_ISR_SET1_ISRSET_SHIFT (0x00000000u)
+
+/* ISR_CLEAR1 */
+#define INTC_ISR_CLEAR1_ISRCLEAR (0xFFFFFFFFu)
+#define INTC_ISR_CLEAR1_ISRCLEAR_SHIFT (0x00000000u)
+
+/* PENDING_IRQ1 */
+#define INTC_PENDING_IRQ1_PENDING_IRQ (0xFFFFFFFFu)
+#define INTC_PENDING_IRQ1_PENDING_IRQ_SHIFT (0x00000000u)
+
+/* PENDING_FIQ1 */
+#define INTC_PENDING_FIQ1_PENDING_FIQ (0xFFFFFFFFu)
+#define INTC_PENDING_FIQ1_PENDING_FIQ_SHIFT (0x00000000u)
+
+/* ITR2 */
+#define INTC_ITR2_ITR (0xFFFFFFFFu)
+#define INTC_ITR2_ITR_SHIFT (0x00000000u)
+
+/* MIR2 */
+#define INTC_MIR2_MIR (0xFFFFFFFFu)
+#define INTC_MIR2_MIR_SHIFT (0x00000000u)
+
+/* MIR_CLEAR2 */
+#define INTC_MIR_CLEAR2_MIRCLEAR (0xFFFFFFFFu)
+#define INTC_MIR_CLEAR2_MIRCLEAR_SHIFT (0x00000000u)
+
+/* MIR_SET2 */
+#define INTC_MIR_SET2_MIRSET (0xFFFFFFFFu)
+#define INTC_MIR_SET2_MIRSET_SHIFT (0x00000000u)
+
+/* ISR_SET2 */
+#define INTC_ISR_SET2_ISRSET (0xFFFFFFFFu)
+#define INTC_ISR_SET2_ISRSET_SHIFT (0x00000000u)
+
+/* ISR_CLEAR2 */
+#define INTC_ISR_CLEAR2_ISRCLEAR (0xFFFFFFFFu)
+#define INTC_ISR_CLEAR2_ISRCLEAR_SHIFT (0x00000000u)
+
+/* PENDING_IRQ2 */
+#define INTC_PENDING_IRQ2_PENDING_IRQ (0xFFFFFFFFu)
+#define INTC_PENDING_IRQ2_PENDING_IRQ_SHIFT (0x00000000u)
+
+/* PENDING_FIQ2 */
+#define INTC_PENDING_FIQ2_PENDING_FIQ (0xFFFFFFFFu)
+#define INTC_PENDING_FIQ2_PENDING_FIQ_SHIFT (0x00000000u)
+
+/* ILR */
+#define INTC_ILR_PRIORITY (0x000001FCu)
+#define INTC_ILR_PRIORITY_SHIFT (0x00000002u)
+
+#define INTC_ILR_FIQNIRQ (0x00000001u)
+#define INTC_ILR_FIQNIRQ_SHIFT (0x00000000u)
+
void rt_hw_interrupt_control(int vector, int priority, int route);
int rt_hw_interrupt_get_active(int fiq_irq);
void rt_hw_interrupt_ack(int fiq_irq);
generated by cgit v1.3.1 (git 2.54.0) at 2026-10-30 13:56:07 +0000