diff options
Diffstat (limited to 'libcpu/arm')
| -rw-r--r-- | libcpu/arm/cortex-a/cpuport.c | 2 | ||||
| -rw-r--r-- | libcpu/arm/cortex-a/interrupt.c | 3 | ||||
| -rw-r--r-- | libcpu/arm/cortex-a/start_gcc.S | 101 |
3 files changed, 57 insertions, 49 deletions
diff --git a/libcpu/arm/cortex-a/cpuport.c b/libcpu/arm/cortex-a/cpuport.c index e3ce568243..ec523f2aa7 100644 --- a/libcpu/arm/cortex-a/cpuport.c +++ b/libcpu/arm/cortex-a/cpuport.c @@ -13,7 +13,7 @@ #include <rtthread.h> #include <board.h> -int rt_hw_cpu_id(void) +rt_weak int rt_hw_cpu_id(void) { int cpu_id; __asm__ volatile ( diff --git a/libcpu/arm/cortex-a/interrupt.c b/libcpu/arm/cortex-a/interrupt.c index bfb3b27170..6fd74aaf76 100644 --- a/libcpu/arm/cortex-a/interrupt.c +++ b/libcpu/arm/cortex-a/interrupt.c @@ -100,8 +100,7 @@ void rt_hw_interrupt_init(void) /* initialize ARM GIC */ #ifdef RT_USING_SMART - gic_dist_base = (uint32_t)rt_ioremap((void*)platform_get_gic_dist_base(), 0x2000); - gic_cpu_base = (uint32_t)rt_ioremap((void*)platform_get_gic_cpu_base(), 0x1000); + gic_dist_base = (uint32_t)rt_ioremap((void*)platform_get_gic_dist_base(), 0x10000); #else gic_dist_base = platform_get_gic_dist_base(); #endif diff --git a/libcpu/arm/cortex-a/start_gcc.S b/libcpu/arm/cortex-a/start_gcc.S index 658ff5a649..1283686439 100644 --- a/libcpu/arm/cortex-a/start_gcc.S +++ b/libcpu/arm/cortex-a/start_gcc.S @@ -208,13 +208,22 @@ bss_loop: _rtthread_startup: .word rtthread_startup +.weak rt_asm_cpu_id +rt_asm_cpu_id: + mov r9, lr + mrc p15, 0, r0, c0, c0, 5 + and r0, r0, #0xf + mov lr, r9 + stack_setup: #ifdef RT_USING_SMP /* cpu id */ - mrc p15, 0, r0, c0, c0, 5 - and r0, r0, #0xf + mov r10, lr + bl rt_asm_cpu_id + mov lr, r10 add r0, r0, #1 + #else mov r0, #1 #endif @@ -300,6 +309,50 @@ _halt: wfe b _halt +#ifdef RT_USING_SMP + +.global rt_secondary_cpu_entry +rt_secondary_cpu_entry: +#ifdef RT_USING_SMART + ldr r0, =_reset + adr r5, _reset + sub r5, r5, r0 + + ldr lr, =after_enable_mmu_n + ldr r0, =init_mtbl + add r0, r5 + b enable_mmu + +after_enable_mmu_n: + ldr r0, =MMUTable + add r0, r5 + bl rt_hw_mmu_switch +#endif + +#ifdef RT_USING_FPU + mov r4, #0xfffffff + mcr p15, 0, r4, c1, c0, 2 +#endif + + mrc p15, 0, r1, c1, c0, 1 + mov r0, #(1<<6) + orr r1, r0 + mcr p15, 0, r1, c1, c0, 1 /* enable smp */ + + mrc p15, 0, r0, c1, c0, 0 + bic r0, #(1<<13) + mcr p15, 0, r0, c1, c0, 0 + + bl stack_setup + + /* initialize the mmu table and enable mmu */ +#ifndef RT_USING_SMART + bl rt_hw_mmu_init +#endif + + b rt_hw_secondary_cpu_bsp_start +#endif + /* exception handlers: undef, swi, padt, dabt, resv, irq, fiq */ .section .text.isr, "ax" .align 5 @@ -616,50 +669,6 @@ rt_hw_clz: clz r0, r0 bx lr -#ifdef RT_USING_SMP - -.global rt_secondary_cpu_entry -rt_secondary_cpu_entry: -#ifdef RT_USING_SMART - ldr r0, =_reset - adr r5, _reset - sub r5, r5, r0 - - ldr lr, =after_enable_mmu_n - ldr r0, =init_mtbl - add r0, r5 - b enable_mmu - -after_enable_mmu_n: - ldr r0, =MMUTable - add r0, r5 - bl rt_hw_mmu_switch -#endif - -#ifdef RT_USING_FPU - mov r4, #0xfffffff - mcr p15, 0, r4, c1, c0, 2 -#endif - - mrc p15, 0, r1, c1, c0, 1 - mov r0, #(1<<6) - orr r1, r0 - mcr p15, 0, r1, c1, c0, 1 /* enable smp */ - - mrc p15, 0, r0, c1, c0, 0 - bic r0, #(1<<13) - mcr p15, 0, r0, c1, c0, 0 - - bl stack_setup - - /* initialize the mmu table and enable mmu */ -#ifndef RT_USING_SMART - bl rt_hw_mmu_init -#endif - - b rt_hw_secondary_cpu_bsp_start -#endif - #ifndef RT_CPUS_NR #define RT_CPUS_NR 1 #endif |