diff options
Diffstat (limited to 'libcpu/arm')
146 files changed, 5964 insertions, 5857 deletions
diff --git a/libcpu/arm/AT91SAM7S/AT91SAM7S.h b/libcpu/arm/AT91SAM7S/AT91SAM7S.h index 130f9074d1..91b57053da 100644 --- a/libcpu/arm/AT91SAM7S/AT91SAM7S.h +++ b/libcpu/arm/AT91SAM7S/AT91SAM7S.h @@ -1,5 +1,5 @@ /* - * Copyright (c) 2006-2018, RT-Thread Development Team + * Copyright (c) 2006-2021, RT-Thread Development Team * * SPDX-License-Identifier: Apache-2.0 * @@ -15,276 +15,276 @@ extern "C" { #endif -#define AT91_REG *(volatile unsigned int *) /* Hardware register definition */ +#define AT91_REG *(volatile unsigned int *) /* Hardware register definition */ /* ========== Register definition for TC0 peripheral ========== */ -#define AT91C_TC0_SR (AT91_REG(0xFFFA0020)) /* TC0 Status Register */ -#define AT91C_TC0_RC (AT91_REG(0xFFFA001C)) /* TC0 Register C */ -#define AT91C_TC0_RB (AT91_REG(0xFFFA0018)) /* TC0 Register B */ -#define AT91C_TC0_CCR (AT91_REG(0xFFFA0000)) /* TC0 Channel Control Register */ -#define AT91C_TC0_CMR (AT91_REG(0xFFFA0004)) /* TC0 Channel Mode Register (Capture Mode / Waveform Mode) */ -#define AT91C_TC0_IER (AT91_REG(0xFFFA0024)) /* TC0 Interrupt Enable Register */ -#define AT91C_TC0_RA (AT91_REG(0xFFFA0014)) /* TC0 Register A */ -#define AT91C_TC0_IDR (AT91_REG(0xFFFA0028)) /* TC0 Interrupt Disable Register */ -#define AT91C_TC0_CV (AT91_REG(0xFFFA0010)) /* TC0 Counter Value */ -#define AT91C_TC0_IMR (AT91_REG(0xFFFA002C)) /* TC0 Interrupt Mask Register */ +#define AT91C_TC0_SR (AT91_REG(0xFFFA0020)) /* TC0 Status Register */ +#define AT91C_TC0_RC (AT91_REG(0xFFFA001C)) /* TC0 Register C */ +#define AT91C_TC0_RB (AT91_REG(0xFFFA0018)) /* TC0 Register B */ +#define AT91C_TC0_CCR (AT91_REG(0xFFFA0000)) /* TC0 Channel Control Register */ +#define AT91C_TC0_CMR (AT91_REG(0xFFFA0004)) /* TC0 Channel Mode Register (Capture Mode / Waveform Mode) */ +#define AT91C_TC0_IER (AT91_REG(0xFFFA0024)) /* TC0 Interrupt Enable Register */ +#define AT91C_TC0_RA (AT91_REG(0xFFFA0014)) /* TC0 Register A */ +#define AT91C_TC0_IDR (AT91_REG(0xFFFA0028)) /* TC0 Interrupt Disable Register */ +#define AT91C_TC0_CV (AT91_REG(0xFFFA0010)) /* TC0 Counter Value */ +#define AT91C_TC0_IMR (AT91_REG(0xFFFA002C)) /* TC0 Interrupt Mask Register */ /* ========== Register definition for TC1 peripheral ========== */ -#define AT91C_TC1_RB (AT91_REG(0xFFFA0058)) /* TC1 Register B */ -#define AT91C_TC1_CCR (AT91_REG(0xFFFA0040)) /* TC1 Channel Control Register */ -#define AT91C_TC1_IER (AT91_REG(0xFFFA0064)) /* TC1 Interrupt Enable Register */ -#define AT91C_TC1_IDR (AT91_REG(0xFFFA0068)) /* TC1 Interrupt Disable Register */ -#define AT91C_TC1_SR (AT91_REG(0xFFFA0060)) /* TC1 Status Register */ -#define AT91C_TC1_CMR (AT91_REG(0xFFFA0044)) /* TC1 Channel Mode Register (Capture Mode / Waveform Mode) */ -#define AT91C_TC1_RA (AT91_REG(0xFFFA0054)) /* TC1 Register A */ -#define AT91C_TC1_RC (AT91_REG(0xFFFA005C)) /* TC1 Register C */ -#define AT91C_TC1_IMR (AT91_REG(0xFFFA006C)) /* TC1 Interrupt Mask Register */ -#define AT91C_TC1_CV (AT91_REG(0xFFFA0050)) /* TC1 Counter Value */ +#define AT91C_TC1_RB (AT91_REG(0xFFFA0058)) /* TC1 Register B */ +#define AT91C_TC1_CCR (AT91_REG(0xFFFA0040)) /* TC1 Channel Control Register */ +#define AT91C_TC1_IER (AT91_REG(0xFFFA0064)) /* TC1 Interrupt Enable Register */ +#define AT91C_TC1_IDR (AT91_REG(0xFFFA0068)) /* TC1 Interrupt Disable Register */ +#define AT91C_TC1_SR (AT91_REG(0xFFFA0060)) /* TC1 Status Register */ +#define AT91C_TC1_CMR (AT91_REG(0xFFFA0044)) /* TC1 Channel Mode Register (Capture Mode / Waveform Mode) */ +#define AT91C_TC1_RA (AT91_REG(0xFFFA0054)) /* TC1 Register A */ +#define AT91C_TC1_RC (AT91_REG(0xFFFA005C)) /* TC1 Register C */ +#define AT91C_TC1_IMR (AT91_REG(0xFFFA006C)) /* TC1 Interrupt Mask Register */ +#define AT91C_TC1_CV (AT91_REG(0xFFFA0050)) /* TC1 Counter Value */ /* ========== Register definition for TC2 peripheral ========== */ -#define AT91C_TC2_CMR (AT91_REG(0xFFFA0084)) /* TC2 Channel Mode Register (Capture Mode / Waveform Mode) */ -#define AT91C_TC2_CCR (AT91_REG(0xFFFA0080)) /* TC2 Channel Control Register */ -#define AT91C_TC2_CV (AT91_REG(0xFFFA0090)) /* TC2 Counter Value */ -#define AT91C_TC2_RA (AT91_REG(0xFFFA0094)) /* TC2 Register A */ -#define AT91C_TC2_RB (AT91_REG(0xFFFA0098)) /* TC2 Register B */ -#define AT91C_TC2_IDR (AT91_REG(0xFFFA00A8)) /* TC2 Interrupt Disable Register */ -#define AT91C_TC2_IMR (AT91_REG(0xFFFA00AC)) /* TC2 Interrupt Mask Register */ -#define AT91C_TC2_RC (AT91_REG(0xFFFA009C)) /* TC2 Register C */ -#define AT91C_TC2_IER (AT91_REG(0xFFFA00A4)) /* TC2 Interrupt Enable Register */ -#define AT91C_TC2_SR (AT91_REG(0xFFFA00A0)) /* TC2 Status Register */ +#define AT91C_TC2_CMR (AT91_REG(0xFFFA0084)) /* TC2 Channel Mode Register (Capture Mode / Waveform Mode) */ +#define AT91C_TC2_CCR (AT91_REG(0xFFFA0080)) /* TC2 Channel Control Register */ +#define AT91C_TC2_CV (AT91_REG(0xFFFA0090)) /* TC2 Counter Value */ +#define AT91C_TC2_RA (AT91_REG(0xFFFA0094)) /* TC2 Register A */ +#define AT91C_TC2_RB (AT91_REG(0xFFFA0098)) /* TC2 Register B */ +#define AT91C_TC2_IDR (AT91_REG(0xFFFA00A8)) /* TC2 Interrupt Disable Register */ +#define AT91C_TC2_IMR (AT91_REG(0xFFFA00AC)) /* TC2 Interrupt Mask Register */ +#define AT91C_TC2_RC (AT91_REG(0xFFFA009C)) /* TC2 Register C */ +#define AT91C_TC2_IER (AT91_REG(0xFFFA00A4)) /* TC2 Interrupt Enable Register */ +#define AT91C_TC2_SR (AT91_REG(0xFFFA00A0)) /* TC2 Status Register */ /* ========== Register definition for PITC peripheral ========== */ -#define AT91C_PITC_PIVR (AT91_REG(0xFFFFFD38)) /* PITC Period Interval Value Register */ -#define AT91C_PITC_PISR (AT91_REG(0xFFFFFD34)) /* PITC Period Interval Status Register */ -#define AT91C_PITC_PIIR (AT91_REG(0xFFFFFD3C)) /* PITC Period Interval Image Register */ -#define AT91C_PITC_PIMR (AT91_REG(0xFFFFFD30)) /* PITC Period Interval Mode Register */ +#define AT91C_PITC_PIVR (AT91_REG(0xFFFFFD38)) /* PITC Period Interval Value Register */ +#define AT91C_PITC_PISR (AT91_REG(0xFFFFFD34)) /* PITC Period Interval Status Register */ +#define AT91C_PITC_PIIR (AT91_REG(0xFFFFFD3C)) /* PITC Period Interval Image Register */ +#define AT91C_PITC_PIMR (AT91_REG(0xFFFFFD30)) /* PITC Period Interval Mode Register */ /* ========== Register definition for UDP peripheral ========== */ -#define AT91C_UDP_NUM (AT91_REG(0xFFFB0000)) /* UDP Frame Number Register */ -#define AT91C_UDP_STAT (AT91_REG(0xFFFB0004)) /* UDP Global State Register */ -#define AT91C_UDP_FADDR (AT91_REG(0xFFFB0008)) /* UDP Function Address Register */ -#define AT91C_UDP_IER (AT91_REG(0xFFFB0010)) /* UDP Interrupt Enable Register */ -#define AT91C_UDP_IDR (AT91_REG(0xFFFB0014)) /* UDP Interrupt Disable Register */ -#define AT91C_UDP_IMR (AT91_REG(0xFFFB0018)) /* UDP Interrupt Mask Register */ -#define AT91C_UDP_ISR (AT91_REG(0xFFFB001C)) /* UDP Interrupt Status Register */ -#define AT91C_UDP_ICR (AT91_REG(0xFFFB0020)) /* UDP Interrupt Clear Register */ -#define AT91C_UDP_RSTEP (AT91_REG(0xFFFB0028)) /* UDP Reset Endpoint Register */ -#define AT91C_UDP_CSR0 (AT91_REG(0xFFFB0030)) /* UDP Endpoint Control and Status Register */ -#define AT91C_UDP_CSR(n) (*(&AT91C_UDP_CSR0 + n)) -#define AT91C_UDP_FDR0 (AT91_REG(0xFFFB0050)) /* UDP Endpoint FIFO Data Register */ -#define AT91C_UDP_FDR(n) (*(&AT91C_UDP_FDR0 + n)) -#define AT91C_UDP_TXVC (AT91_REG(0xFFFB0074)) /* UDP Transceiver Control Register */ +#define AT91C_UDP_NUM (AT91_REG(0xFFFB0000)) /* UDP Frame Number Register */ +#define AT91C_UDP_STAT (AT91_REG(0xFFFB0004)) /* UDP Global State Register */ +#define AT91C_UDP_FADDR (AT91_REG(0xFFFB0008)) /* UDP Function Address Register */ +#define AT91C_UDP_IER (AT91_REG(0xFFFB0010)) /* UDP Interrupt Enable Register */ +#define AT91C_UDP_IDR (AT91_REG(0xFFFB0014)) /* UDP Interrupt Disable Register */ +#define AT91C_UDP_IMR (AT91_REG(0xFFFB0018)) /* UDP Interrupt Mask Register */ +#define AT91C_UDP_ISR (AT91_REG(0xFFFB001C)) /* UDP Interrupt Status Register */ +#define AT91C_UDP_ICR (AT91_REG(0xFFFB0020)) /* UDP Interrupt Clear Register */ +#define AT91C_UDP_RSTEP (AT91_REG(0xFFFB0028)) /* UDP Reset Endpoint Register */ +#define AT91C_UDP_CSR0 (AT91_REG(0xFFFB0030)) /* UDP Endpoint Control and Status Register */ +#define AT91C_UDP_CSR(n) (*(&AT91C_UDP_CSR0 + n)) +#define AT91C_UDP_FDR0 (AT91_REG(0xFFFB0050)) /* UDP Endpoint FIFO Data Register */ +#define AT91C_UDP_FDR(n) (*(&AT91C_UDP_FDR0 + n)) +#define AT91C_UDP_TXVC (AT91_REG(0xFFFB0074)) /* UDP Transceiver Control Register */ /* ========== Register definition for US0 peripheral ========== */ -#define AT91C_US0_CR (AT91_REG(0xFFFC0000)) /* US0 Control Register */ -#define AT91C_US0_MR (AT91_REG(0xFFFC0004)) /* US0 Mode Register */ -#define AT91C_US0_IER (AT91_REG(0xFFFC0008)) /* US0 Interrupt Enable Register */ -#define AT91C_US0_IDR (AT91_REG(0xFFFC000C)) /* US0 Interrupt Disable Register */ -#define AT91C_US0_IMR (AT91_REG(0xFFFC0010)) /* US0 Interrupt Mask Register */ -#define AT91C_US0_CSR (AT91_REG(0xFFFC0014)) /* US0 Channel Status Register */ -#define AT91C_US0_RHR (AT91_REG(0xFFFC0018)) /* US0 Receiver Holding Register */ -#define AT91C_US0_THR (AT91_REG(0xFFFC001C)) /* US0 Transmitter Holding Register */ -#define AT91C_US0_BRGR (AT91_REG(0xFFFC0020)) /* US0 Baud Rate Generator Register */ -#define AT91C_US0_RTOR (AT91_REG(0xFFFC0024)) /* US0 Receiver Time-out Register */ -#define AT91C_US0_TTGR (AT91_REG(0xFFFC0028)) /* US0 Transmitter Time-guard Register */ -#define AT91C_US0_NER (AT91_REG(0xFFFC0044)) /* US0 Nb Errors Register */ -#define AT91C_US0_FIDI (AT91_REG(0xFFFC0040)) /* US0 FI_DI_Ratio Register */ -#define AT91C_US0_IF (AT91_REG(0xFFFC004C)) /* US0 IRDA_FILTER Register */ +#define AT91C_US0_CR (AT91_REG(0xFFFC0000)) /* US0 Control Register */ +#define AT91C_US0_MR (AT91_REG(0xFFFC0004)) /* US0 Mode Register */ +#define AT91C_US0_IER (AT91_REG(0xFFFC0008)) /* US0 Interrupt Enable Register */ +#define AT91C_US0_IDR (AT91_REG(0xFFFC000C)) /* US0 Interrupt Disable Register */ +#define AT91C_US0_IMR (AT91_REG(0xFFFC0010)) /* US0 Interrupt Mask Register */ +#define AT91C_US0_CSR (AT91_REG(0xFFFC0014)) /* US0 Channel Status Register */ +#define AT91C_US0_RHR (AT91_REG(0xFFFC0018)) /* US0 Receiver Holding Register */ +#define AT91C_US0_THR (AT91_REG(0xFFFC001C)) /* US0 Transmitter Holding Register */ +#define AT91C_US0_BRGR (AT91_REG(0xFFFC0020)) /* US0 Baud Rate Generator Register */ +#define AT91C_US0_RTOR (AT91_REG(0xFFFC0024)) /* US0 Receiver Time-out Register */ +#define AT91C_US0_TTGR (AT91_REG(0xFFFC0028)) /* US0 Transmitter Time-guard Register */ +#define AT91C_US0_NER (AT91_REG(0xFFFC0044)) /* US0 Nb Errors Register */ +#define AT91C_US0_FIDI (AT91_REG(0xFFFC0040)) /* US0 FI_DI_Ratio Register */ +#define AT91C_US0_IF (AT91_REG(0xFFFC004C)) /* US0 IRDA_FILTER Register */ /* ========== Register definition for AIC peripheral ========== */ -#define AT91C_AIC_SMR0 (AT91_REG(0xFFFFF000)) /* AIC Source Mode Register */ -#define AT91C_AIC_SMR(n) (*(&AT91C_AIC_SMR0 + n)) -#define AT91C_AIC_SVR0 (AT91_REG(0xFFFFF080)) /* AIC Source Vector Register */ -#define AT91C_AIC_SVR(n) (*(&AT91C_AIC_SVR0 + n)) -#define AT91C_AIC_IVR (AT91_REG(0xFFFFF100)) /* AIC Interrupt Vector Register */ -#define AT91C_AIC_FVR (AT91_REG(0xFFFFF104)) /* AIC FIQ Vector Register */ -#define AT91C_AIC_ISR (AT91_REG(0xFFFFF108)) /* AIC Interrupt Status Register */ -#define AT91C_AIC_IPR (AT91_REG(0xFFFFF10C)) /* AIC Interrupt Pending Register */ -#define AT91C_AIC_IMR (AT91_REG(0xFFFFF110)) /* AIC Interrupt Mask Register */ -#define AT91C_AIC_CISR (AT91_REG(0xFFFFF114)) /* AIC Core Interrupt Status Register */ -#define AT91C_AIC_IECR (AT91_REG(0xFFFFF120)) /* AIC Interrupt Enable Command Register */ -#define AT91C_AIC_IDCR (AT91_REG(0xFFFFF124)) /* AIC Interrupt Disable Command Register */ -#define AT91C_AIC_ICCR (AT91_REG(0xFFFFF128)) /* AIC Interrupt Clear Command Register */ -#define AT91C_AIC_ISCR (AT91_REG(0xFFFFF12C)) /* AIC Interrupt Set Command Register */ -#define AT91C_AIC_EOICR (AT91_REG(0xFFFFF130)) /* AIC End of Interrupt Command Register */ -#define AT91C_AIC_SPU (AT91_REG(0xFFFFF134)) /* AIC Spurious Vector Register */ -#define AT91C_AIC_DCR (AT91_REG(0xFFFFF138)) /* AIC Debug Control Register (Protect) */ -#define AT91C_AIC_FFER (AT91_REG(0xFFFFF140)) /* AIC Fast Forcing Enable Register */ -#define AT91C_AIC_FFDR (AT91_REG(0xFFFFF144)) /* AIC Fast Forcing Disable Register */ -#define AT91C_AIC_FFSR (AT91_REG(0xFFFFF148)) /* AIC Fast Forcing Status Register */ +#define AT91C_AIC_SMR0 (AT91_REG(0xFFFFF000)) /* AIC Source Mode Register */ +#define AT91C_AIC_SMR(n) (*(&AT91C_AIC_SMR0 + n)) +#define AT91C_AIC_SVR0 (AT91_REG(0xFFFFF080)) /* AIC Source Vector Register */ +#define AT91C_AIC_SVR(n) (*(&AT91C_AIC_SVR0 + n)) +#define AT91C_AIC_IVR (AT91_REG(0xFFFFF100)) /* AIC Interrupt Vector Register */ +#define AT91C_AIC_FVR (AT91_REG(0xFFFFF104)) /* AIC FIQ Vector Register */ +#define AT91C_AIC_ISR (AT91_REG(0xFFFFF108)) /* AIC Interrupt Status Register */ +#define AT91C_AIC_IPR (AT91_REG(0xFFFFF10C)) /* AIC Interrupt Pending Register */ +#define AT91C_AIC_IMR (AT91_REG(0xFFFFF110)) /* AIC Interrupt Mask Register */ +#define AT91C_AIC_CISR (AT91_REG(0xFFFFF114)) /* AIC Core Interrupt Status Register */ +#define AT91C_AIC_IECR (AT91_REG(0xFFFFF120)) /* AIC Interrupt Enable Command Register */ +#define AT91C_AIC_IDCR (AT91_REG(0xFFFFF124)) /* AIC Interrupt Disable Command Register */ +#define AT91C_AIC_ICCR (AT91_REG(0xFFFFF128)) /* AIC Interrupt Clear Command Register */ +#define AT91C_AIC_ISCR (AT91_REG(0xFFFFF12C)) /* AIC Interrupt Set Command Register */ +#define AT91C_AIC_EOICR (AT91_REG(0xFFFFF130)) /* AIC End of Interrupt Command Register */ +#define AT91C_AIC_SPU (AT91_REG(0xFFFFF134)) /* AIC Spurious Vector Register */ +#define AT91C_AIC_DCR (AT91_REG(0xFFFFF138)) /* AIC Debug Control Register (Protect) */ +#define AT91C_AIC_FFER (AT91_REG(0xFFFFF140)) /* AIC Fast Forcing Enable Register */ +#define AT91C_AIC_FFDR (AT91_REG(0xFFFFF144)) /* AIC Fast Forcing Disable Register */ +#define AT91C_AIC_FFSR (AT91_REG(0xFFFFF148)) /* AIC Fast Forcing Status Register */ /* ========== Register definition for DBGU peripheral ========== */ -#define AT91C_DBGU_EXID (AT91_REG(0xFFFFF244)) /* DBGU Chip ID Extension Register */ -#define AT91C_DBGU_BRGR (AT91_REG(0xFFFFF220)) /* DBGU Baud Rate Generator Register */ -#define AT91C_DBGU_IDR (AT91_REG(0xFFFFF20C)) /* DBGU Interrupt Disable Register */ -#define AT91C_DBGU_CSR (AT91_REG(0xFFFFF214)) /* DBGU Channel Status Register */ -#define AT91C_DBGU_CIDR (AT91_REG(0xFFFFF240)) /* DBGU Chip ID Register */ -#define AT91C_DBGU_MR (AT91_REG(0xFFFFF204)) /* DBGU Mode Register */ -#define AT91C_DBGU_IMR (AT91_REG(0xFFFFF210)) /* DBGU Interrupt Mask Register */ -#define AT91C_DBGU_CR (AT91_REG(0xFFFFF200)) /* DBGU Control Register */ -#define AT91C_DBGU_FNTR (AT91_REG(0xFFFFF248)) /* DBGU Force NTRST Register */ -#define AT91C_DBGU_THR (AT91_REG(0xFFFFF21C)) /* DBGU Transmitter Holding Register */ -#define AT91C_DBGU_RHR (AT91_REG(0xFFFFF218)) /* DBGU Receiver Holding Register */ -#define AT91C_DBGU_IER (AT91_REG(0xFFFFF208)) /* DBGU Interrupt Enable Register */ +#define AT91C_DBGU_EXID (AT91_REG(0xFFFFF244)) /* DBGU Chip ID Extension Register */ +#define AT91C_DBGU_BRGR (AT91_REG(0xFFFFF220)) /* DBGU Baud Rate Generator Register */ +#define AT91C_DBGU_IDR (AT91_REG(0xFFFFF20C)) /* DBGU Interrupt Disable Register */ +#define AT91C_DBGU_CSR (AT91_REG(0xFFFFF214)) /* DBGU Channel Status Register */ +#define AT91C_DBGU_CIDR (AT91_REG(0xFFFFF240)) /* DBGU Chip ID Register */ +#define AT91C_DBGU_MR (AT91_REG(0xFFFFF204)) /* DBGU Mode Register */ +#define AT91C_DBGU_IMR (AT91_REG(0xFFFFF210)) /* DBGU Interrupt Mask Register */ +#define AT91C_DBGU_CR (AT91_REG(0xFFFFF200)) /* DBGU Control Register */ +#define AT91C_DBGU_FNTR (AT91_REG(0xFFFFF248)) /* DBGU Force NTRST Register */ +#define AT91C_DBGU_THR (AT91_REG(0xFFFFF21C)) /* DBGU Transmitter Holding Register */ +#define AT91C_DBGU_RHR (AT91_REG(0xFFFFF218)) /* DBGU Receiver Holding Register */ +#define AT91C_DBGU_IER (AT91_REG(0xFFFFF208)) /* DBGU Interrupt Enable Register */ /* ========== Register definition for PIO peripheral ========== */ -#define AT91C_PIO_ODR (AT91_REG(0xFFFFF414)) /* PIOA Output Disable Registerr */ -#define AT91C_PIO_SODR (AT91_REG(0xFFFFF430)) /* PIOA Set Output Data Register */ -#define AT91C_PIO_ISR (AT91_REG(0xFFFFF44C)) /* PIOA Interrupt Status Register */ -#define AT91C_PIO_ABSR (AT91_REG(0xFFFFF478)) /* PIOA AB Select Status Register */ -#define AT91C_PIO_IER (AT91_REG(0xFFFFF440)) /* PIOA Interrupt Enable Register */ -#define AT91C_PIO_PPUDR (AT91_REG(0xFFFFF460)) /* PIOA Pull-up Disable Register */ -#define AT91C_PIO_IMR (AT91_REG(0xFFFFF448)) /* PIOA Interrupt Mask Register */ -#define AT91C_PIO_PER (AT91_REG(0xFFFFF400)) /* PIOA PIO Enable Register */ -#define AT91C_PIO_IFDR (AT91_REG(0xFFFFF424)) /* PIOA Input Filter Disable Register */ -#define AT91C_PIO_OWDR (AT91_REG(0xFFFFF4A4)) /* PIOA Output Write Disable Register */ -#define AT91C_PIO_MDSR (AT91_REG(0xFFFFF458)) /* PIOA Multi-driver Status Register */ -#define AT91C_PIO_IDR (AT91_REG(0xFFFFF444)) /* PIOA Interrupt Disable Register */ -#define AT91C_PIO_ODSR (AT91_REG(0xFFFFF438)) /* PIOA Output Data Status Register */ -#define AT91C_PIO_PPUSR (AT91_REG(0xFFFFF468)) /* PIOA Pull-up Status Register */ -#define AT91C_PIO_OWSR (AT91_REG(0xFFFFF4A8)) /* PIOA Output Write Status Register */ -#define AT91C_PIO_BSR (AT91_REG(0xFFFFF474)) /* PIOA Select B Register */ -#define AT91C_PIO_OWER (AT91_REG(0xFFFFF4A0)) /* PIOA Output Write Enable Register */ -#define AT91C_PIO_IFER (AT91_REG(0xFFFFF420)) /* PIOA Input Filter Enable Register */ -#define AT91C_PIO_PDSR (AT91_REG(0xFFFFF43C)) /* PIOA Pin Data Status Register */ -#define AT91C_PIO_PPUER (AT91_REG(0xFFFFF464)) /* PIOA Pull-up Enable Register */ -#define AT91C_PIO_OSR (AT91_REG(0xFFFFF418)) /* PIOA Output Status Register */ -#define AT91C_PIO_ASR (AT91_REG(0xFFFFF470)) /* PIOA Select A Register */ -#define AT91C_PIO_MDDR (AT91_REG(0xFFFFF454)) /* PIOA Multi-driver Disable Register */ -#define AT91C_PIO_CODR (AT91_REG(0xFFFFF434)) /* PIOA Clear Output Data Register */ -#define AT91C_PIO_MDER (AT91_REG(0xFFFFF450)) /* PIOA Multi-driver Enable Register */ -#define AT91C_PIO_PDR (AT91_REG(0xFFFFF404)) /* PIOA PIO Disable Register */ -#define AT91C_PIO_IFSR (AT91_REG(0xFFFFF428)) /* PIOA Input Filter Status Register */ -#define AT91C_PIO_OER (AT91_REG(0xFFFFF410)) /* PIOA Output Enable Register */ -#define AT91C_PIO_PSR (AT91_REG(0xFFFFF408)) /* PIOA PIO Status Register */ +#define AT91C_PIO_ODR (AT91_REG(0xFFFFF414)) /* PIOA Output Disable Registerr */ +#define AT91C_PIO_SODR (AT91_REG(0xFFFFF430)) /* PIOA Set Output Data Register */ +#define AT91C_PIO_ISR (AT91_REG(0xFFFFF44C)) /* PIOA Interrupt Status Register */ +#define AT91C_PIO_ABSR (AT91_REG(0xFFFFF478)) /* PIOA AB Select Status Register */ +#define AT91C_PIO_IER (AT91_REG(0xFFFFF440)) /* PIOA Interrupt Enable Register */ +#define AT91C_PIO_PPUDR (AT91_REG(0xFFFFF460)) /* PIOA Pull-up Disable Register */ +#define AT91C_PIO_IMR (AT91_REG(0xFFFFF448)) /* PIOA Interrupt Mask Register */ +#define AT91C_PIO_PER (AT91_REG(0xFFFFF400)) /* PIOA PIO Enable Register */ +#define AT91C_PIO_IFDR (AT91_REG(0xFFFFF424)) /* PIOA Input Filter Disable Register */ +#define AT91C_PIO_OWDR (AT91_REG(0xFFFFF4A4)) /* PIOA Output Write Disable Register */ +#define AT91C_PIO_MDSR (AT91_REG(0xFFFFF458)) /* PIOA Multi-driver Status Register */ +#define AT91C_PIO_IDR (AT91_REG(0xFFFFF444)) /* PIOA Interrupt Disable Register */ +#define AT91C_PIO_ODSR (AT91_REG(0xFFFFF438)) /* PIOA Output Data Status Register */ +#define AT91C_PIO_PPUSR (AT91_REG(0xFFFFF468)) /* PIOA Pull-up Status Register */ +#define AT91C_PIO_OWSR (AT91_REG(0xFFFFF4A8)) /* PIOA Output Write Status Register */ +#define AT91C_PIO_BSR (AT91_REG(0xFFFFF474)) /* PIOA Select B Register */ +#define AT91C_PIO_OWER (AT91_REG(0xFFFFF4A0)) /* PIOA Output Write Enable Register */ +#define AT91C_PIO_IFER (AT91_REG(0xFFFFF420)) /* PIOA Input Filter Enable Register */ +#define AT91C_PIO_PDSR (AT91_REG(0xFFFFF43C)) /* PIOA Pin Data Status Register */ +#define AT91C_PIO_PPUER (AT91_REG(0xFFFFF464)) /* PIOA Pull-up Enable Register */ +#define AT91C_PIO_OSR (AT91_REG(0xFFFFF418)) /* PIOA Output Status Register */ +#define AT91C_PIO_ASR (AT91_REG(0xFFFFF470)) /* PIOA Select A Register */ +#define AT91C_PIO_MDDR (AT91_REG(0xFFFFF454)) /* PIOA Multi-driver Disable Register */ +#define AT91C_PIO_CODR (AT91_REG(0xFFFFF434)) /* PIOA Clear Output Data Register */ +#define AT91C_PIO_MDER (AT91_REG(0xFFFFF450)) /* PIOA Multi-driver Enable Register */ +#define AT91C_PIO_PDR (AT91_REG(0xFFFFF404)) /* PIOA PIO Disable Register */ +#define AT91C_PIO_IFSR (AT91_REG(0xFFFFF428)) /* PIOA Input Filter Status Register */ +#define AT91C_PIO_OER (AT91_REG(0xFFFFF410)) /* PIOA Output Enable Register */ +#define AT91C_PIO_PSR (AT91_REG(0xFFFFF408)) /* PIOA PIO Status Register */ // ========== Register definition for PIOA peripheral ========== -#define AT91C_PIOA_IMR (AT91_REG(0xFFFFF448)) // (PIOA) Interrupt Mask Register -#define AT91C_PIOA_IER (AT91_REG(0xFFFFF440)) // (PIOA) Interrupt Enable Register -#define AT91C_PIOA_OWDR (AT91_REG(0xFFFFF4A4)) // (PIOA) Output Write Disable Register -#define AT91C_PIOA_ISR (AT91_REG(0xFFFFF44C)) // (PIOA) Interrupt Status Register -#define AT91C_PIOA_PPUDR (AT91_REG(0xFFFFF460)) // (PIOA) Pull-up Disable Register -#define AT91C_PIOA_MDSR (AT91_REG(0xFFFFF458)) // (PIOA) Multi-driver Status Register -#define AT91C_PIOA_MDER (AT91_REG(0xFFFFF450)) // (PIOA) Multi-driver Enable Register -#define AT91C_PIOA_PER (AT91_REG(0xFFFFF400)) // (PIOA) PIO Enable Register -#define AT91C_PIOA_PSR (AT91_REG(0xFFFFF408)) // (PIOA) PIO Status Register -#define AT91C_PIOA_OER (AT91_REG(0xFFFFF410)) // (PIOA) Output Enable Register -#define AT91C_PIOA_BSR (AT91_REG(0xFFFFF474)) // (PIOA) Select B Register -#define AT91C_PIOA_PPUER (AT91_REG(0xFFFFF464)) // (PIOA) Pull-up Enable Register -#define AT91C_PIOA_MDDR (AT91_REG(0xFFFFF454)) // (PIOA) Multi-driver Disable Register -#define AT91C_PIOA_PDR (AT91_REG(0xFFFFF404)) // (PIOA) PIO Disable Register -#define AT91C_PIOA_ODR (AT91_REG(0xFFFFF414)) // (PIOA) Output Disable Registerr -#define AT91C_PIOA_IFDR (AT91_REG(0xFFFFF424)) // (PIOA) Input Filter Disable Register -#define AT91C_PIOA_ABSR (AT91_REG(0xFFFFF478)) // (PIOA) AB Select Status Register -#define AT91C_PIOA_ASR (AT91_REG(0xFFFFF470)) // (PIOA) Select A Register -#define AT91C_PIOA_PPUSR (AT91_REG(0xFFFFF468)) // (PIOA) Pull-up Status Register -#define AT91C_PIOA_ODSR (AT91_REG(0xFFFFF438)) // (PIOA) Output Data Status Register -#define AT91C_PIOA_SODR (AT91_REG(0xFFFFF430)) // (PIOA) Set Output Data Register -#define AT91C_PIOA_IFSR (AT91_REG(0xFFFFF428)) // (PIOA) Input Filter Status Register -#define AT91C_PIOA_IFER (AT91_REG(0xFFFFF420)) // (PIOA) Input Filter Enable Register -#define AT91C_PIOA_OSR (AT91_REG(0xFFFFF418)) // (PIOA) Output Status Register -#define AT91C_PIOA_IDR (AT91_REG(0xFFFFF444)) // (PIOA) Interrupt Disable Register -#define AT91C_PIOA_PDSR (AT91_REG(0xFFFFF43C)) // (PIOA) Pin Data Status Register -#define AT91C_PIOA_CODR (AT91_REG(0xFFFFF434)) // (PIOA) Clear Output Data Register -#define AT91C_PIOA_OWSR (AT91_REG(0xFFFFF4A8)) // (PIOA) Output Write Status Register -#define AT91C_PIOA_OWER (AT91_REG(0xFFFFF4A0)) // (PIOA) Output Write Enable Register +#define AT91C_PIOA_IMR (AT91_REG(0xFFFFF448)) // (PIOA) Interrupt Mask Register +#define AT91C_PIOA_IER (AT91_REG(0xFFFFF440)) // (PIOA) Interrupt Enable Register +#define AT91C_PIOA_OWDR (AT91_REG(0xFFFFF4A4)) // (PIOA) Output Write Disable Register +#define AT91C_PIOA_ISR (AT91_REG(0xFFFFF44C)) // (PIOA) Interrupt Status Register +#define AT91C_PIOA_PPUDR (AT91_REG(0xFFFFF460)) // (PIOA) Pull-up Disable Register +#define AT91C_PIOA_MDSR (AT91_REG(0xFFFFF458)) // (PIOA) Multi-driver Status Register +#define AT91C_PIOA_MDER (AT91_REG(0xFFFFF450)) // (PIOA) Multi-driver Enable Register +#define AT91C_PIOA_PER (AT91_REG(0xFFFFF400)) // (PIOA) PIO Enable Register +#define AT91C_PIOA_PSR (AT91_REG(0xFFFFF408)) // (PIOA) PIO Status Register +#define AT91C_PIOA_OER (AT91_REG(0xFFFFF410)) // (PIOA) Output Enable Register +#define AT91C_PIOA_BSR (AT91_REG(0xFFFFF474)) // (PIOA) Select B Register +#define AT91C_PIOA_PPUER (AT91_REG(0xFFFFF464)) // (PIOA) Pull-up Enable Register +#define AT91C_PIOA_MDDR (AT91_REG(0xFFFFF454)) // (PIOA) Multi-driver Disable Register +#define AT91C_PIOA_PDR (AT91_REG(0xFFFFF404)) // (PIOA) PIO Disable Register +#define AT91C_PIOA_ODR (AT91_REG(0xFFFFF414)) // (PIOA) Output Disable Registerr +#define AT91C_PIOA_IFDR (AT91_REG(0xFFFFF424)) // (PIOA) Input Filter Disable Register +#define AT91C_PIOA_ABSR (AT91_REG(0xFFFFF478)) // (PIOA) AB Select Status Register +#define AT91C_PIOA_ASR (AT91_REG(0xFFFFF470)) // (PIOA) Select A Register +#define AT91C_PIOA_PPUSR (AT91_REG(0xFFFFF468)) // (PIOA) Pull-up Status Register +#define AT91C_PIOA_ODSR (AT91_REG(0xFFFFF438)) // (PIOA) Output Data Status Register +#define AT91C_PIOA_SODR (AT91_REG(0xFFFFF430)) // (PIOA) Set Output Data Register +#define AT91C_PIOA_IFSR (AT91_REG(0xFFFFF428)) // (PIOA) Input Filter Status Register +#define AT91C_PIOA_IFER (AT91_REG(0xFFFFF420)) // (PIOA) Input Filter Enable Register +#define AT91C_PIOA_OSR (AT91_REG(0xFFFFF418)) // (PIOA) Output Status Register +#define AT91C_PIOA_IDR (AT91_REG(0xFFFFF444)) // (PIOA) Interrupt Disable Register +#define AT91C_PIOA_PDSR (AT91_REG(0xFFFFF43C)) // (PIOA) Pin Data Status Register +#define AT91C_PIOA_CODR (AT91_REG(0xFFFFF434)) // (PIOA) Clear Output Data Register +#define AT91C_PIOA_OWSR (AT91_REG(0xFFFFF4A8)) // (PIOA) Output Write Status Register +#define AT91C_PIOA_OWER (AT91_REG(0xFFFFF4A0)) // (PIOA) Output Write Enable Register // ========== Register definition for PIOB peripheral ========== -#define AT91C_PIOB_OWSR (AT91_REG(0xFFFFF6A8)) // (PIOB) Output Write Status Register -#define AT91C_PIOB_PPUSR (AT91_REG(0xFFFFF668)) // (PIOB) Pull-up Status Register -#define AT91C_PIOB_PPUDR (AT91_REG(0xFFFFF660)) // (PIOB) Pull-up Disable Register -#define AT91C_PIOB_MDSR (AT91_REG(0xFFFFF658)) // (PIOB) Multi-driver Status Register -#define AT91C_PIOB_MDER (AT91_REG(0xFFFFF650)) // (PIOB) Multi-driver Enable Register -#define AT91C_PIOB_IMR (AT91_REG(0xFFFFF648)) // (PIOB) Interrupt Mask Register -#define AT91C_PIOB_OSR (AT91_REG(0xFFFFF618)) // (PIOB) Output Status Register -#define AT91C_PIOB_OER (AT91_REG(0xFFFFF610)) // (PIOB) Output Enable Register -#define AT91C_PIOB_PSR (AT91_REG(0xFFFFF608)) // (PIOB) PIO Status Register -#define AT91C_PIOB_PER (AT91_REG(0xFFFFF600)) // (PIOB) PIO Enable Register -#define AT91C_PIOB_BSR (AT91_REG(0xFFFFF674)) // (PIOB) Select B Register -#define AT91C_PIOB_PPUER (AT91_REG(0xFFFFF664)) // (PIOB) Pull-up Enable Register -#define AT91C_PIOB_IFDR (AT91_REG(0xFFFFF624)) // (PIOB) Input Filter Disable Register -#define AT91C_PIOB_ODR (AT91_REG(0xFFFFF614)) // (PIOB) Output Disable Registerr -#define AT91C_PIOB_ABSR (AT91_REG(0xFFFFF678)) // (PIOB) AB Select Status Register -#define AT91C_PIOB_ASR (AT91_REG(0xFFFFF670)) // (PIOB) Select A Register -#define AT91C_PIOB_IFER (AT91_REG(0xFFFFF620)) // (PIOB) Input Filter Enable Register -#define AT91C_PIOB_IFSR (AT91_REG(0xFFFFF628)) // (PIOB) Input Filter Status Register -#define AT91C_PIOB_SODR (AT91_REG(0xFFFFF630)) // (PIOB) Set Output Data Register -#define AT91C_PIOB_ODSR (AT91_REG(0xFFFFF638)) // (PIOB) Output Data Status Register -#define AT91C_PIOB_CODR (AT91_REG(0xFFFFF634)) // (PIOB) Clear Output Data Register -#define AT91C_PIOB_PDSR (AT91_REG(0xFFFFF63C)) // (PIOB) Pin Data Status Register -#define AT91C_PIOB_OWER (AT91_REG(0xFFFFF6A0)) // (PIOB) Output Write Enable Register -#define AT91C_PIOB_IER (AT91_REG(0xFFFFF640)) // (PIOB) Interrupt Enable Register -#define AT91C_PIOB_OWDR (AT91_REG(0xFFFFF6A4)) // (PIOB) Output Write Disable Register -#define AT91C_PIOB_MDDR (AT91_REG(0xFFFFF654)) // (PIOB) Multi-driver Disable Register -#define AT91C_PIOB_ISR (AT91_REG(0xFFFFF64C)) // (PIOB) Interrupt Status Register -#define AT91C_PIOB_IDR (AT91_REG(0xFFFFF644)) // (PIOB) Interrupt Disable Register -#define AT91C_PIOB_PDR (AT91_REG(0xFFFFF604)) // (PIOB) PIO Disable Register +#define AT91C_PIOB_OWSR (AT91_REG(0xFFFFF6A8)) // (PIOB) Output Write Status Register +#define AT91C_PIOB_PPUSR (AT91_REG(0xFFFFF668)) // (PIOB) Pull-up Status Register +#define AT91C_PIOB_PPUDR (AT91_REG(0xFFFFF660)) // (PIOB) Pull-up Disable Register +#define AT91C_PIOB_MDSR (AT91_REG(0xFFFFF658)) // (PIOB) Multi-driver Status Register +#define AT91C_PIOB_MDER (AT91_REG(0xFFFFF650)) // (PIOB) Multi-driver Enable Register +#define AT91C_PIOB_IMR (AT91_REG(0xFFFFF648)) // (PIOB) Interrupt Mask Register +#define AT91C_PIOB_OSR (AT91_REG(0xFFFFF618)) // (PIOB) Output Status Register +#define AT91C_PIOB_OER (AT91_REG(0xFFFFF610)) // (PIOB) Output Enable Register +#define AT91C_PIOB_PSR (AT91_REG(0xFFFFF608)) // (PIOB) PIO Status Register +#define AT91C_PIOB_PER (AT91_REG(0xFFFFF600)) // (PIOB) PIO Enable Register +#define AT91C_PIOB_BSR (AT91_REG(0xFFFFF674)) // (PIOB) Select B Register +#define AT91C_PIOB_PPUER (AT91_REG(0xFFFFF664)) // (PIOB) Pull-up Enable Register +#define AT91C_PIOB_IFDR (AT91_REG(0xFFFFF624)) // (PIOB) Input Filter Disable Register +#define AT91C_PIOB_ODR (AT91_REG(0xFFFFF614)) // (PIOB) Output Disable Registerr +#define AT91C_PIOB_ABSR (AT91_REG(0xFFFFF678)) // (PIOB) AB Select Status Register +#define AT91C_PIOB_ASR (AT91_REG(0xFFFFF670)) // (PIOB) Select A Register +#define AT91C_PIOB_IFER (AT91_REG(0xFFFFF620)) // (PIOB) Input Filter Enable Register +#define AT91C_PIOB_IFSR (AT91_REG(0xFFFFF628)) // (PIOB) Input Filter Status Register +#define AT91C_PIOB_SODR (AT91_REG(0xFFFFF630)) // (PIOB) Set Output Data Register +#define AT91C_PIOB_ODSR (AT91_REG(0xFFFFF638)) // (PIOB) Output Data Status Register +#define AT91C_PIOB_CODR (AT91_REG(0xFFFFF634)) // (PIOB) Clear Output Data Register +#define AT91C_PIOB_PDSR (AT91_REG(0xFFFFF63C)) // (PIOB) Pin Data Status Register +#define AT91C_PIOB_OWER (AT91_REG(0xFFFFF6A0)) // (PIOB) Output Write Enable Register +#define AT91C_PIOB_IER (AT91_REG(0xFFFFF640)) // (PIOB) Interrupt Enable Register +#define AT91C_PIOB_OWDR (AT91_REG(0xFFFFF6A4)) // (PIOB) Output Write Disable Register +#define AT91C_PIOB_MDDR (AT91_REG(0xFFFFF654)) // (PIOB) Multi-driver Disable Register +#define AT91C_PIOB_ISR (AT91_REG(0xFFFFF64C)) // (PIOB) Interrupt Status Register +#define AT91C_PIOB_IDR (AT91_REG(0xFFFFF644)) // (PIOB) Interrupt Disable Register +#define AT91C_PIOB_PDR (AT91_REG(0xFFFFF604)) // (PIOB) PIO Disable Register /* ========== Register definition for PMC peripheral ========== */ -#define AT91C_PMC_SCER (AT91_REG(0xFFFFFC00)) /* PMC System Clock Enable Register */ -#define AT91C_PMC_SCDR (AT91_REG(0xFFFFFC04)) /* PMC System Clock Disable Register */ -#define AT91C_PMC_SCSR (AT91_REG(0xFFFFFC08)) /* PMC System Clock Status Register */ -#define AT91C_PMC_PCER (AT91_REG(0xFFFFFC10)) /* PMC Peripheral Clock Enable Register */ -#define AT91C_PMC_PCDR (AT91_REG(0xFFFFFC14)) /* PMC Peripheral Clock Disable Register */ -#define AT91C_PMC_PCSR (AT91_REG(0xFFFFFC18)) /* PMC Peripheral Clock Status Register */ -#define AT91C_PMC_MOR (AT91_REG(0xFFFFFC20)) /* PMC Main Oscillator Register */ -#define AT91C_PMC_MCFR (AT91_REG(0xFFFFFC24)) /* PMC Main Clock Frequency Register */ -#define AT91C_PMC_PLLR (AT91_REG(0xFFFFFC2C)) /* PMC PLL Register */ -#define AT91C_PMC_MCKR (AT91_REG(0xFFFFFC30)) /* PMC Master Clock Register */ -#define AT91C_PMC_PCKR (AT91_REG(0xFFFFFC40)) /* PMC Programmable Clock Register */ -#define AT91C_PMC_IER (AT91_REG(0xFFFFFC60)) /* PMC Interrupt Enable Register */ -#define AT91C_PMC_IDR (AT91_REG(0xFFFFFC64)) /* PMC Interrupt Disable Register */ -#define AT91C_PMC_SR (AT91_REG(0xFFFFFC68)) /* PMC Status Register */ -#define AT91C_PMC_IMR (AT91_REG(0xFFFFFC6C)) /* PMC Interrupt Mask Register */ +#define AT91C_PMC_SCER (AT91_REG(0xFFFFFC00)) /* PMC System Clock Enable Register */ +#define AT91C_PMC_SCDR (AT91_REG(0xFFFFFC04)) /* PMC System Clock Disable Register */ +#define AT91C_PMC_SCSR (AT91_REG(0xFFFFFC08)) /* PMC System Clock Status Register */ +#define AT91C_PMC_PCER (AT91_REG(0xFFFFFC10)) /* PMC Peripheral Clock Enable Register */ +#define AT91C_PMC_PCDR (AT91_REG(0xFFFFFC14)) /* PMC Peripheral Clock Disable Register */ +#define AT91C_PMC_PCSR (AT91_REG(0xFFFFFC18)) /* PMC Peripheral Clock Status Register */ +#define AT91C_PMC_MOR (AT91_REG(0xFFFFFC20)) /* PMC Main Oscillator Register */ +#define AT91C_PMC_MCFR (AT91_REG(0xFFFFFC24)) /* PMC Main Clock Frequency Register */ +#define AT91C_PMC_PLLR (AT91_REG(0xFFFFFC2C)) /* PMC PLL Register */ +#define AT91C_PMC_MCKR (AT91_REG(0xFFFFFC30)) /* PMC Master Clock Register */ +#define AT91C_PMC_PCKR (AT91_REG(0xFFFFFC40)) /* PMC Programmable Clock Register */ +#define AT91C_PMC_IER (AT91_REG(0xFFFFFC60)) /* PMC Interrupt Enable Register */ +#define AT91C_PMC_IDR (AT91_REG(0xFFFFFC64)) /* PMC Interrupt Disable Register */ +#define AT91C_PMC_SR (AT91_REG(0xFFFFFC68)) /* PMC Status Register */ +#define AT91C_PMC_IMR (AT91_REG(0xFFFFFC6C)) /* PMC Interrupt Mask Register */ /******************************************************************************/ /* PERIPHERAL ID DEFINITIONS FOR AT91SAM7S64 */ /******************************************************************************/ -#define AT91C_ID_FIQ 0 /* Advanced Interrupt Controller (FIQ) */ -#define AT91C_ID_SYS 1 /* System Peripheral */ -#define AT91C_ID_PIOA 2 /* Parallel IO Controller A */ -#define AT91C_ID_PIOB 3 /* Parallel IO Controller B */ -#define AT91C_ID_ADC 4 /* Analog-to-Digital Converter */ -#define AT91C_ID_SPI 5 /* Serial Peripheral Interface */ -#define AT91C_ID_US0 6 /* USART 0 */ -#define AT91C_ID_US1 7 /* USART 1 */ -#define AT91C_ID_SSC 8 /* Serial Synchronous Controller */ -#define AT91C_ID_TWI 9 /* Two-Wire Interface */ -#define AT91C_ID_PWMC 10 /* PWM Controller */ -#define AT91C_ID_UDP 11 /* USB Device Port */ -#define AT91C_ID_TC0 12 /* Timer Counter 0 */ -#define AT91C_ID_TC1 13 /* Timer Counter 1 */ -#define AT91C_ID_TC2 14 /* Timer Counter 2 */ -#define AT91C_ID_15 15 /* Reserved */ -#define AT91C_ID_16 16 /* Reserved */ -#define AT91C_ID_17 17 /* Reserved */ -#define AT91C_ID_18 18 /* Reserved */ -#define AT91C_ID_19 19 /* Reserved */ -#define AT91C_ID_20 20 /* Reserved */ -#define AT91C_ID_21 21 /* Reserved */ -#define AT91C_ID_22 22 /* Reserved */ -#define AT91C_ID_23 23 /* Reserved */ -#define AT91C_ID_24 24 /* Reserved */ -#define AT91C_ID_25 25 /* Reserved */ -#define AT91C_ID_26 26 /* Reserved */ -#define AT91C_ID_27 27 /* Reserved */ -#define AT91C_ID_28 28 /* Reserved */ -#define AT91C_ID_29 29 /* Reserved */ -#define AT91C_ID_IRQ0 30 /* Advanced Interrupt Controller (IRQ0) */ -#define AT91C_ID_IRQ1 31 /* Advanced Interrupt Controller (IRQ1) */ -#define AT91C_ALL_INT 0xC0007FF7 /* ALL VALID INTERRUPTS */ +#define AT91C_ID_FIQ 0 /* Advanced Interrupt Controller (FIQ) */ +#define AT91C_ID_SYS 1 /* System Peripheral */ +#define AT91C_ID_PIOA 2 /* Parallel IO Controller A */ +#define AT91C_ID_PIOB 3 /* Parallel IO Controller B */ +#define AT91C_ID_ADC 4 /* Analog-to-Digital Converter */ +#define AT91C_ID_SPI 5 /* Serial Peripheral Interface */ +#define AT91C_ID_US0 6 /* USART 0 */ +#define AT91C_ID_US1 7 /* USART 1 */ +#define AT91C_ID_SSC 8 /* Serial Synchronous Controller */ +#define AT91C_ID_TWI 9 /* Two-Wire Interface */ +#define AT91C_ID_PWMC 10 /* PWM Controller */ +#define AT91C_ID_UDP 11 /* USB Device Port */ +#define AT91C_ID_TC0 12 /* Timer Counter 0 */ +#define AT91C_ID_TC1 13 /* Timer Counter 1 */ +#define AT91C_ID_TC2 14 /* Timer Counter 2 */ +#define AT91C_ID_15 15 /* Reserved */ +#define AT91C_ID_16 16 /* Reserved */ +#define AT91C_ID_17 17 /* Reserved */ +#define AT91C_ID_18 18 /* Reserved */ +#define AT91C_ID_19 19 /* Reserved */ +#define AT91C_ID_20 20 /* Reserved */ +#define AT91C_ID_21 21 /* Reserved */ +#define AT91C_ID_22 22 /* Reserved */ +#define AT91C_ID_23 23 /* Reserved */ +#define AT91C_ID_24 24 /* Reserved */ +#define AT91C_ID_25 25 /* Reserved */ +#define AT91C_ID_26 26 /* Reserved */ +#define AT91C_ID_27 27 /* Reserved */ +#define AT91C_ID_28 28 /* Reserved */ +#define AT91C_ID_29 29 /* Reserved */ +#define AT91C_ID_IRQ0 30 /* Advanced Interrupt Controller (IRQ0) */ +#define AT91C_ID_IRQ1 31 /* Advanced Interrupt Controller (IRQ1) */ +#define AT91C_ALL_INT 0xC0007FF7 /* ALL VALID INTERRUPTS */ /*****************************/ /* CPU Mode */ /*****************************/ -#define USERMODE 0x10 -#define FIQMODE 0x11 -#define IRQMODE 0x12 -#define SVCMODE 0x13 -#define ABORTMODE 0x17 -#define UNDEFMODE 0x1b -#define MODEMASK 0x1f -#define NOINT 0xc0 +#define USERMODE 0x10 +#define FIQMODE 0x11 +#define IRQMODE 0x12 +#define SVCMODE 0x13 +#define ABORTMODE 0x17 +#define UNDEFMODE 0x1b +#define MODEMASK 0x1f +#define NOINT 0xc0 #ifdef __cplusplus } diff --git a/libcpu/arm/AT91SAM7S/cpu.c b/libcpu/arm/AT91SAM7S/cpu.c index b24ab5644b..18d8d6208a 100644 --- a/libcpu/arm/AT91SAM7S/cpu.c +++ b/libcpu/arm/AT91SAM7S/cpu.c @@ -1,5 +1,5 @@ /* - * Copyright (c) 2006-2018, RT-Thread Development Team + * Copyright (c) 2006-2021, RT-Thread Development Team * * SPDX-License-Identifier: Apache-2.0 * @@ -30,9 +30,9 @@ RT_WEAK void rt_hw_cpu_reset() */ RT_WEAK void rt_hw_cpu_shutdown() { - rt_kprintf("shutdown...\n"); + rt_kprintf("shutdown...\n"); - while (1); + while (1); } /*@}*/ diff --git a/libcpu/arm/AT91SAM7S/interrupt.c b/libcpu/arm/AT91SAM7S/interrupt.c index db9d31fe28..e4aa8643f1 100644 --- a/libcpu/arm/AT91SAM7S/interrupt.c +++ b/libcpu/arm/AT91SAM7S/interrupt.c @@ -1,5 +1,5 @@ /* - * Copyright (c) 2006-2018, RT-Thread Development Team + * Copyright (c) 2006-2021, RT-Thread Development Team * * SPDX-License-Identifier: Apache-2.0 * @@ -11,7 +11,7 @@ #include <rtthread.h> #include "AT91SAM7S.h" -#define MAX_HANDLERS 32 +#define MAX_HANDLERS 32 extern rt_uint32_t rt_interrupt_nest; @@ -25,7 +25,7 @@ rt_uint32_t rt_thread_switch_interrupt_flag; void rt_hw_interrupt_handler(int vector) { - rt_kprintf("Unhandled interrupt %d occured!!!\n", vector); + rt_kprintf("Unhandled interrupt %d occured!!!\n", vector); } /** @@ -33,18 +33,18 @@ void rt_hw_interrupt_handler(int vector) */ void rt_hw_interrupt_init() { - rt_base_t index; + rt_base_t index; - for (index = 0; index < MAX_HANDLERS; index ++) - { - AT91C_AIC_SVR(index) = (rt_uint32_t)rt_hw_interrupt_handler; - } + for (index = 0; index < MAX_HANDLERS; index ++) + { + AT91C_AIC_SVR(index) = (rt_uint32_t)rt_hw_interrupt_handler; + } - /* init interrupt nest, and context in thread sp */ - rt_interrupt_nest = 0; - rt_interrupt_from_thread = 0; - rt_interrupt_to_thread = 0; - rt_thread_switch_interrupt_flag = 0; + /* init interrupt nest, and context in thread sp */ + rt_interrupt_nest = 0; + rt_interrupt_from_thread = 0; + rt_interrupt_to_thread = 0; + rt_thread_switch_interrupt_flag = 0; } /** @@ -53,11 +53,11 @@ void rt_hw_interrupt_init() */ void rt_hw_interrupt_mask(int vector) { - /* disable interrupt */ - AT91C_AIC_IDCR = 1 << vector; + /* disable interrupt */ + AT91C_AIC_IDCR = 1 << vector; - /* clear interrupt */ - AT91C_AIC_ICCR = 1 << vector; + /* clear interrupt */ + AT91C_AIC_ICCR = 1 << vector; } /** @@ -66,7 +66,7 @@ void rt_hw_interrupt_mask(int vector) */ void rt_hw_interrupt_umask(int vector) { - AT91C_AIC_IECR = 1 << vector; + AT91C_AIC_IECR = 1 << vector; } /** @@ -77,11 +77,11 @@ void rt_hw_interrupt_umask(int vector) */ void rt_hw_interrupt_install(int vector, rt_isr_handler_t new_handler, rt_isr_handler_t *old_handler) { - if(vector >= 0 && vector < MAX_HANDLERS) - { - if (*old_handler != RT_NULL) *old_handler = (rt_isr_handler_t)AT91C_AIC_SVR(vector); - if (new_handler != RT_NULL) AT91C_AIC_SVR(vector) = (rt_uint32_t)new_handler; - } + if(vector >= 0 && vector < MAX_HANDLERS) + { + if (*old_handler != RT_NULL) *old_handler = (rt_isr_handler_t)AT91C_AIC_SVR(vector); + if (new_handler != RT_NULL) AT91C_AIC_SVR(vector) = (rt_uint32_t)new_handler; + } } /*@}*/ diff --git a/libcpu/arm/AT91SAM7S/serial.c b/libcpu/arm/AT91SAM7S/serial.c index adbe8609d6..583443f4cb 100644 --- a/libcpu/arm/AT91SAM7S/serial.c +++ b/libcpu/arm/AT91SAM7S/serial.c @@ -1,5 +1,5 @@ /* - * Copyright (c) 2006-2018, RT-Thread Development Team + * Copyright (c) 2006-2021, RT-Thread Development Team * * SPDX-License-Identifier: Apache-2.0 * @@ -22,46 +22,46 @@ typedef volatile rt_uint32_t REG32; struct rt_at91serial_hw { - REG32 US_CR; // Control Register - REG32 US_MR; // Mode Register - REG32 US_IER; // Interrupt Enable Register - REG32 US_IDR; // Interrupt Disable Register - REG32 US_IMR; // Interrupt Mask Register - REG32 US_CSR; // Channel Status Register - REG32 US_RHR; // Receiver Holding Register - REG32 US_THR; // Transmitter Holding Register - REG32 US_BRGR; // Baud Rate Generator Register - REG32 US_RTOR; // Receiver Time-out Register - REG32 US_TTGR; // Transmitter Time-guard Register - REG32 Reserved0[5]; // - REG32 US_FIDI; // FI_DI_Ratio Register - REG32 US_NER; // Nb Errors Register - REG32 Reserved1[1]; // - REG32 US_IF; // IRDA_FILTER Register - REG32 Reserved2[44]; // - REG32 US_RPR; // Receive Pointer Register - REG32 US_RCR; // Receive Counter Register - REG32 US_TPR; // Transmit Pointer Register - REG32 US_TCR; // Transmit Counter Register - REG32 US_RNPR; // Receive Next Pointer Register - REG32 US_RNCR; // Receive Next Counter Register - REG32 US_TNPR; // Transmit Next Pointer Register - REG32 US_TNCR; // Transmit Next Counter Register - REG32 US_PTCR; // PDC Transfer Control Register - REG32 US_PTSR; // PDC Transfer Status Register + REG32 US_CR; // Control Register + REG32 US_MR; // Mode Register + REG32 US_IER; // Interrupt Enable Register + REG32 US_IDR; // Interrupt Disable Register + REG32 US_IMR; // Interrupt Mask Register + REG32 US_CSR; // Channel Status Register + REG32 US_RHR; // Receiver Holding Register + REG32 US_THR; // Transmitter Holding Register + REG32 US_BRGR; // Baud Rate Generator Register + REG32 US_RTOR; // Receiver Time-out Register + REG32 US_TTGR; // Transmitter Time-guard Register + REG32 Reserved0[5]; // + REG32 US_FIDI; // FI_DI_Ratio Register + REG32 US_NER; // Nb Errors Register + REG32 Reserved1[1]; // + REG32 US_IF; // IRDA_FILTER Register + REG32 Reserved2[44]; // + REG32 US_RPR; // Receive Pointer Register + REG32 US_RCR; // Receive Counter Register + REG32 US_TPR; // Transmit Pointer Register + REG32 US_TCR; // Transmit Counter Register + REG32 US_RNPR; // Receive Next Pointer Register + REG32 US_RNCR; // Receive Next Counter Register + REG32 US_TNPR; // Transmit Next Pointer Register + REG32 US_TNCR; // Transmit Next Counter Register + REG32 US_PTCR; // PDC Transfer Control Register + REG32 US_PTSR; // PDC Transfer Status Register }; struct rt_at91serial { - struct rt_device parent; + struct rt_device parent; - struct rt_at91serial_hw* hw_base; - rt_uint16_t peripheral_id; - rt_uint32_t baudrate; + struct rt_at91serial_hw* hw_base; + rt_uint16_t peripheral_id; + rt_uint32_t baudrate; - /* reception field */ - rt_uint16_t save_index, read_index; - rt_uint8_t rx_buffer[RT_UART_RX_BUFFER_SIZE]; + /* reception field */ + rt_uint16_t save_index, read_index; + rt_uint8_t rx_buffer[RT_UART_RX_BUFFER_SIZE]; }; #ifdef RT_USING_UART1 struct rt_at91serial serial1; @@ -72,312 +72,312 @@ struct rt_at91serial serial2; static void rt_hw_serial_isr(int irqno) { - rt_base_t level; - struct rt_device* device; - struct rt_at91serial* serial = RT_NULL; + rt_base_t level; + struct rt_device* device; + struct rt_at91serial* serial = RT_NULL; - if (irqno == AT91C_ID_US0) - { + if (irqno == AT91C_ID_US0) + { #ifdef RT_USING_UART1 - /* serial 1 */ - serial = &serial1; + /* serial 1 */ + serial = &serial1; #endif - } - else if (irqno == AT91C_ID_US1) - { + } + else if (irqno == AT91C_ID_US1) + { #ifdef RT_USING_UART2 - /* serial 2 */ - serial = &serial2; + /* serial 2 */ + serial = &serial2; #endif - } - RT_ASSERT(serial != RT_NULL); + } + RT_ASSERT(serial != RT_NULL); - /* get generic device object */ - device = (rt_device_t)serial; + /* get generic device object */ + device = (rt_device_t)serial; - /* disable interrupt */ - level = rt_hw_interrupt_disable(); + /* disable interrupt */ + level = rt_hw_interrupt_disable(); - /* get received character */ - serial->rx_buffer[serial->save_index] = serial->hw_base->US_RHR; + /* get received character */ + serial->rx_buffer[serial->save_index] = serial->hw_base->US_RHR; - /* move to next position */ - serial->save_index ++; - if (serial->save_index >= RT_UART_RX_BUFFER_SIZE) - serial->save_index = 0; + /* move to next position */ + serial->save_index ++; + if (serial->save_index >= RT_UART_RX_BUFFER_SIZE) + serial->save_index = 0; - /* if the next position is read index, discard this 'read char' */ - if (serial->save_index == serial->read_index) - { - serial->read_index ++; - if (serial->read_index >= RT_UART_RX_BUFFER_SIZE) - serial->read_index = 0; - } + /* if the next position is read index, discard this 'read char' */ + if (serial->save_index == serial->read_index) + { + serial->read_index ++; + if (serial->read_index >= RT_UART_RX_BUFFER_SIZE) + serial->read_index = 0; + } - /* enable interrupt */ - rt_hw_interrupt_enable(level); + /* enable interrupt */ + rt_hw_interrupt_enable(level); - /* indicate to upper layer application */ - if (device->rx_indicate != RT_NULL) - device->rx_indicate(device, 1); + /* indicate to upper layer application */ + if (device->rx_indicate != RT_NULL) + device->rx_indicate(device, 1); - /* ack interrupt */ - AT91C_AIC_EOICR = 1; + /* ack interrupt */ + AT91C_AIC_EOICR = 1; } static rt_err_t rt_serial_init (rt_device_t dev) { - rt_uint32_t bd; - struct rt_at91serial* serial = (struct rt_at91serial*) dev; + rt_uint32_t bd; + struct rt_at91serial* serial = (struct rt_at91serial*) dev; - RT_ASSERT(serial != RT_NULL); - /* must be US0 or US1 */ - RT_ASSERT(((serial->peripheral_id == AT91C_ID_US0) || - (serial->peripheral_id == AT91C_ID_US1))); + RT_ASSERT(serial != RT_NULL); + /* must be US0 or US1 */ + RT_ASSERT(((serial->peripheral_id == AT91C_ID_US0) || + (serial->peripheral_id == AT91C_ID_US1))); - /* Enable Clock for USART */ - AT91C_PMC_PCER = 1 << serial->peripheral_id; + /* Enable Clock for USART */ + AT91C_PMC_PCER = 1 << serial->peripheral_id; - /* Enable RxD0 and TxDO Pin */ - if (serial->peripheral_id == AT91C_ID_US0) - { - /* set pinmux */ - AT91C_PIO_PDR = (1 << 5) | (1 << 6); - } - else if (serial->peripheral_id == AT91C_ID_US1) - { - /* set pinmux */ - AT91C_PIO_PDR = (1 << 21) | (1 << 22); - } + /* Enable RxD0 and TxDO Pin */ + if (serial->peripheral_id == AT91C_ID_US0) + { + /* set pinmux */ + AT91C_PIO_PDR = (1 << 5) | (1 << 6); + } + else if (serial->peripheral_id == AT91C_ID_US1) + { + /* set pinmux */ + AT91C_PIO_PDR = (1 << 21) | (1 << 22); + } - serial->hw_base->US_CR = AT91C_US_RSTRX | /* Reset Receiver */ - AT91C_US_RSTTX | /* Reset Transmitter */ - AT91C_US_RXDIS | /* Receiver Disable */ - AT91C_US_TXDIS; /* Transmitter Disable */ + serial->hw_base->US_CR = AT91C_US_RSTRX | /* Reset Receiver */ + AT91C_US_RSTTX | /* Reset Transmitter */ + AT91C_US_RXDIS | /* Receiver Disable */ + AT91C_US_TXDIS; /* Transmitter Disable */ - serial->hw_base->US_MR = AT91C_US_USMODE_NORMAL | /* Normal Mode */ - AT91C_US_CLKS_CLOCK | /* Clock = MCK */ - AT91C_US_CHRL_8_BITS | /* 8-bit Data */ - AT91C_US_PAR_NONE | /* No Parity */ - AT91C_US_NBSTOP_1_BIT; /* 1 Stop Bit */ + serial->hw_base->US_MR = AT91C_US_USMODE_NORMAL | /* Normal Mode */ + AT91C_US_CLKS_CLOCK | /* Clock = MCK */ + AT91C_US_CHRL_8_BITS | /* 8-bit Data */ + AT91C_US_PAR_NONE | /* No Parity */ + AT91C_US_NBSTOP_1_BIT; /* 1 Stop Bit */ - /* set baud rate divisor */ - bd = ((MCK*10)/(serial->baudrate * 16)); - if ((bd % 10) >= 5) bd = (bd / 10) + 1; - else bd /= 10; + /* set baud rate divisor */ + bd = ((MCK*10)/(serial->baudrate * 16)); + if ((bd % 10) >= 5) bd = (bd / 10) + 1; + else bd /= 10; - serial->hw_base->US_BRGR = bd; - serial->hw_base->US_CR = AT91C_US_RXEN | /* Receiver Enable */ - AT91C_US_TXEN; /* Transmitter Enable */ + serial->hw_base->US_BRGR = bd; + serial->hw_base->US_CR = AT91C_US_RXEN | /* Receiver Enable */ + AT91C_US_TXEN; /* Transmitter Enable */ - /* reset rx index */ - serial->save_index = 0; - serial->read_index = 0; + /* reset rx index */ + serial->save_index = 0; + serial->read_index = 0; - /* reset rx buffer */ - rt_memset(serial->rx_buffer, 0, RT_UART_RX_BUFFER_SIZE); + /* reset rx buffer */ + rt_memset(serial->rx_buffer, 0, RT_UART_RX_BUFFER_SIZE); - return RT_EOK; + return RT_EOK; } static rt_err_t rt_serial_open(rt_device_t dev, rt_uint16_t oflag) { - struct rt_at91serial *serial = (struct rt_at91serial*)dev; - RT_ASSERT(serial != RT_NULL); + struct rt_at91serial *serial = (struct rt_at91serial*)dev; + RT_ASSERT(serial != RT_NULL); - if (dev->flag & RT_DEVICE_FLAG_INT_RX) - { - /* enable UART rx interrupt */ - serial->hw_base->US_IER = 1 << 0; /* RxReady interrupt */ - serial->hw_base->US_IMR |= 1 << 0; /* umask RxReady interrupt */ + if (dev->flag & RT_DEVICE_FLAG_INT_RX) + { + /* enable UART rx interrupt */ + serial->hw_base->US_IER = 1 << 0; /* RxReady interrupt */ + serial->hw_base->US_IMR |= 1 << 0; /* umask RxReady interrupt */ - /* install UART handler */ - rt_hw_interrupt_install(serial->peripheral_id, rt_hw_serial_isr, RT_NULL); - AT91C_AIC_SMR(serial->peripheral_id) = 5 | (0x01 << 5); - rt_hw_interrupt_umask(serial->peripheral_id); - } + /* install UART handler */ + rt_hw_interrupt_install(serial->peripheral_id, rt_hw_serial_isr, RT_NULL); + AT91C_AIC_SMR(serial->peripheral_id) = 5 | (0x01 << 5); + rt_hw_interrupt_umask(serial->peripheral_id); + } - return RT_EOK; + return RT_EOK; } static rt_err_t rt_serial_close(rt_device_t dev) { - struct rt_at91serial *serial = (struct rt_at91serial*)dev; - RT_ASSERT(serial != RT_NULL); + struct rt_at91serial *serial = (struct rt_at91serial*)dev; + RT_ASSERT(serial != RT_NULL); - if (dev->flag & RT_DEVICE_FLAG_INT_RX) - { - /* disable interrupt */ - serial->hw_base->US_IDR = 1 << 0; /* RxReady interrupt */ - serial->hw_base->US_IMR &= ~(1 << 0); /* mask RxReady interrupt */ - } + if (dev->flag & RT_DEVICE_FLAG_INT_RX) + { + /* disable interrupt */ + serial->hw_base->US_IDR = 1 << 0; /* RxReady interrupt */ + serial->hw_base->US_IMR &= ~(1 << 0); /* mask RxReady interrupt */ + } - return RT_EOK; + return RT_EOK; } static rt_size_t rt_serial_read (rt_device_t dev, rt_off_t pos, void* buffer, rt_size_t size) { - rt_uint8_t* ptr; - struct rt_at91serial *serial = (struct rt_at91serial*)dev; - RT_ASSERT(serial != RT_NULL); + rt_uint8_t* ptr; + struct rt_at91serial *serial = (struct rt_at91serial*)dev; + RT_ASSERT(serial != RT_NULL); - /* point to buffer */ - ptr = (rt_uint8_t*) buffer; + /* point to buffer */ + ptr = (rt_uint8_t*) buffer; - if (dev->flag & RT_DEVICE_FLAG_INT_RX) - { - while (size) - { - /* interrupt receive */ - rt_base_t level; + if (dev->flag & RT_DEVICE_FLAG_INT_RX) + { + while (size) + { + /* interrupt receive */ + rt_base_t level; - /* disable interrupt */ - level = rt_hw_interrupt_disable(); - if (serial->read_index != serial->save_index) - { - *ptr = serial->rx_buffer[serial->read_index]; + /* disable interrupt */ + level = rt_hw_interrupt_disable(); + if (serial->read_index != serial->save_index) + { + *ptr = serial->rx_buffer[serial->read_index]; - serial->read_index ++; - if (serial->read_index >= RT_UART_RX_BUFFER_SIZE) - serial->read_index = 0; - } - else - { - /* no data in rx buffer */ + serial->read_index ++; + if (serial->read_index >= RT_UART_RX_BUFFER_SIZE) + serial->read_index = 0; + } + else + { + /* no data in rx buffer */ - /* enable interrupt */ - rt_hw_interrupt_enable(level); - break; - } + /* enable interrupt */ + rt_hw_interrupt_enable(level); + break; + } - /* enable interrupt */ - rt_hw_interrupt_enable(level); + /* enable interrupt */ + rt_hw_interrupt_enable(level); - ptr ++; size --; - } + ptr ++; size --; + } - return (rt_uint32_t)ptr - (rt_uint32_t)buffer; - } - else if (dev->flag & RT_DEVICE_FLAG_DMA_RX) - { - /* not support right now */ - RT_ASSERT(0); - } - else - { - /* poll mode */ - while (size) - { - /* Wait for Full Rx Buffer */ - while (!(serial->hw_base->US_CSR & AT91C_US_RXRDY)); + return (rt_uint32_t)ptr - (rt_uint32_t)buffer; + } + else if (dev->flag & RT_DEVICE_FLAG_DMA_RX) + { + /* not support right now */ + RT_ASSERT(0); + } + else + { + /* poll mode */ + while (size) + { + /* Wait for Full Rx Buffer */ + while (!(serial->hw_base->US_CSR & AT91C_US_RXRDY)); - /* Read Character */ - *ptr = serial->hw_base->US_RHR; - ptr ++; - size --; - } + /* Read Character */ + *ptr = serial->hw_base->US_RHR; + ptr ++; + size --; + } - return (rt_size_t)ptr - (rt_size_t)buffer; - } + return (rt_size_t)ptr - (rt_size_t)buffer; + } - return 0; + return 0; } static rt_size_t rt_serial_write (rt_device_t dev, rt_off_t pos, const void* buffer, rt_size_t size) { - rt_uint8_t* ptr; - struct rt_at91serial *serial = (struct rt_at91serial*)dev; - RT_ASSERT(serial != RT_NULL); + rt_uint8_t* ptr; + struct rt_at91serial *serial = (struct rt_at91serial*)dev; + RT_ASSERT(serial != RT_NULL); - ptr = (rt_uint8_t*) buffer; - if (dev->open_flag & RT_DEVICE_OFLAG_WRONLY) - { - if (dev->flag & RT_DEVICE_FLAG_STREAM) - { - /* it's a stream mode device */ - while (size) - { - /* stream mode */ - if (*ptr == '\n') - { - while (!(serial->hw_base->US_CSR & AT91C_US_TXRDY)); - serial->hw_base->US_THR = '\r'; - } + ptr = (rt_uint8_t*) buffer; + if (dev->open_flag & RT_DEVICE_OFLAG_WRONLY) + { + if (dev->flag & RT_DEVICE_FLAG_STREAM) + { + /* it's a stream mode device */ + while (size) + { + /* stream mode */ + if (*ptr == '\n') + { + while (!(serial->hw_base->US_CSR & AT91C_US_TXRDY)); + serial->hw_base->US_THR = '\r'; + } - /* Wait for Empty Tx Buffer */ - while (!(serial->hw_base->US_CSR & AT91C_US_TXRDY)); + /* Wait for Empty Tx Buffer */ + while (!(serial->hw_base->US_CSR & AT91C_US_TXRDY)); - /* Transmit Character */ - serial->hw_base->US_THR = *ptr; - ptr ++; size --; - } - } - else - { - while (size) - { - /* Wait for Empty Tx Buffer */ - while (!(serial->hw_base->US_CSR & AT91C_US_TXRDY)); + /* Transmit Character */ + serial->hw_base->US_THR = *ptr; + ptr ++; size --; + } + } + else + { + while (size) + { + /* Wait for Empty Tx Buffer */ + while (!(serial->hw_base->US_CSR & AT91C_US_TXRDY)); - /* Transmit Character */ - serial->hw_base->US_THR = *ptr; - ptr ++; size --; - } - } - } + /* Transmit Character */ + serial->hw_base->US_THR = *ptr; + ptr ++; size --; + } + } + } - return (rt_size_t)ptr - (rt_size_t)buffer; + return (rt_size_t)ptr - (rt_size_t)buffer; } static rt_err_t rt_serial_control (rt_device_t dev, int cmd, void *args) { - return RT_EOK; + return RT_EOK; } rt_err_t rt_hw_serial_init() { - rt_device_t device; + rt_device_t device; #ifdef RT_USING_UART1 - device = (rt_device_t) &serial1; + device = (rt_device_t) &serial1; - /* init serial device private data */ - serial1.hw_base = (struct rt_at91serial_hw*)AT91C_BASE_US0; - serial1.peripheral_id = AT91C_ID_US0; - serial1.baudrate = 115200; + /* init serial device private data */ + serial1.hw_base = (struct rt_at91serial_hw*)AT91C_BASE_US0; + serial1.peripheral_id = AT91C_ID_US0; + serial1.baudrate = 115200; - /* set device virtual interface */ - device->init = rt_serial_init; - device->open = rt_serial_open; - device->close = rt_serial_close; - device->read = rt_serial_read; - device->write = rt_serial_write; - device->control = rt_serial_control; + /* set device virtual interface */ + device->init = rt_serial_init; + device->open = rt_serial_open; + device->close = rt_serial_close; + device->read = rt_serial_read; + device->write = rt_serial_write; + device->control = rt_serial_control; - /* register uart1 on device subsystem */ - rt_device_register(device, "uart1", RT_DEVICE_FLAG_RDWR | RT_DEVICE_FLAG_INT_RX); + /* register uart1 on device subsystem */ + rt_device_register(device, "uart1", RT_DEVICE_FLAG_RDWR | RT_DEVICE_FLAG_INT_RX); #endif #ifdef RT_USING_UART2 - device = (rt_device_t) &serial2; + device = (rt_device_t) &serial2; - serial2.hw_base = (struct rt_at91serial_hw*)AT91C_BASE_US1; - serial2.peripheral_id = AT91C_ID_US1; - serial2.baudrate = 115200; + serial2.hw_base = (struct rt_at91serial_hw*)AT91C_BASE_US1; + serial2.peripheral_id = AT91C_ID_US1; + serial2.baudrate = 115200; - /* set device virtual interface */ - device->init = rt_serial_init; - device->open = rt_serial_open; - device->close = rt_serial_close; - device->read = rt_serial_read; - device->write = rt_serial_write; - device->control = rt_serial_control; + /* set device virtual interface */ + device->init = rt_serial_init; + device->open = rt_serial_open; + device->close = rt_serial_close; + device->read = rt_serial_read; + device->write = rt_serial_write; + device->control = rt_serial_control; - /* register uart2 on device subsystem */ - rt_device_register(device, "uart2", RT_DEVICE_FLAG_RDWR | RT_DEVICE_FLAG_INT_RX); + /* register uart2 on device subsystem */ + rt_device_register(device, "uart2", RT_DEVICE_FLAG_RDWR | RT_DEVICE_FLAG_INT_RX); #endif - return RT_EOK; + return RT_EOK; } /*@}*/ diff --git a/libcpu/arm/AT91SAM7S/serial.h b/libcpu/arm/AT91SAM7S/serial.h index 0937e92f6c..7766053a7f 100644 --- a/libcpu/arm/AT91SAM7S/serial.h +++ b/libcpu/arm/AT91SAM7S/serial.h @@ -1,5 +1,5 @@ /* - * Copyright (c) 2006-2018, RT-Thread Development Team + * Copyright (c) 2006-2021, RT-Thread Development Team * * SPDX-License-Identifier: Apache-2.0 * @@ -17,48 +17,48 @@ #define AT91C_BASE_US1 (0xFFFC4000) // (US1) Base Address #endif -#define AT91C_US_RXRDY ((unsigned int) 0x1 << 0) /* US RXRDY Interrupt */ -#define AT91C_US_TXRDY ((unsigned int) 0x1 << 1) /* US TXRDY Interrupt */ -#define AT91C_US_RSTRX ((unsigned int) 0x1 << 2) /* US Reset Receiver */ -#define AT91C_US_RSTTX ((unsigned int) 0x1 << 3) /* US Reset Transmitter */ -#define AT91C_US_RXEN ((unsigned int) 0x1 << 4) /* US Receiver Enable */ -#define AT91C_US_RXDIS ((unsigned int) 0x1 << 5) /* US Receiver Disable */ -#define AT91C_US_TXEN ((unsigned int) 0x1 << 6) /* US Transmitter Enable */ -#define AT91C_US_TXDIS ((unsigned int) 0x1 << 7) /* US Transmitter Disable */ -#define AT91C_US_RSTSTA ((unsigned int) 0x1 << 8) /* US Reset Status Bits */ +#define AT91C_US_RXRDY ((unsigned int) 0x1 << 0) /* US RXRDY Interrupt */ +#define AT91C_US_TXRDY ((unsigned int) 0x1 << 1) /* US TXRDY Interrupt */ +#define AT91C_US_RSTRX ((unsigned int) 0x1 << 2) /* US Reset Receiver */ +#define AT91C_US_RSTTX ((unsigned int) 0x1 << 3) /* US Reset Transmitter */ +#define AT91C_US_RXEN ((unsigned int) 0x1 << 4) /* US Receiver Enable */ +#define AT91C_US_RXDIS ((unsigned int) 0x1 << 5) /* US Receiver Disable */ +#define AT91C_US_TXEN ((unsigned int) 0x1 << 6) /* US Transmitter Enable */ +#define AT91C_US_TXDIS ((unsigned int) 0x1 << 7) /* US Transmitter Disable */ +#define AT91C_US_RSTSTA ((unsigned int) 0x1 << 8) /* US Reset Status Bits */ -#define AT91C_US_USMODE_NORMAL ((unsigned int) 0x0) /* USAR) Normal */ -#define AT91C_US_USMODE_RS485 ((unsigned int) 0x1) /* USAR) RS485 */ -#define AT91C_US_USMODE_HWHSH ((unsigned int) 0x2) /* USAR) Hardware Handshaking */ -#define AT91C_US_USMODE_MODEM ((unsigned int) 0x3) /* USAR) Modem */ -#define AT91C_US_USMODE_ISO7816_0 ((unsigned int) 0x4) /* USAR) ISO7816 protocol: T = 0 */ -#define AT91C_US_USMODE_ISO7816_1 ((unsigned int) 0x6) /* USAR) ISO7816 protocol: T = 1 */ -#define AT91C_US_USMODE_IRDA ((unsigned int) 0x8) /* USAR) IrDA */ -#define AT91C_US_USMODE_SWHSH ((unsigned int) 0xC) /* USAR) Software Handshaking */ +#define AT91C_US_USMODE_NORMAL ((unsigned int) 0x0) /* USAR) Normal */ +#define AT91C_US_USMODE_RS485 ((unsigned int) 0x1) /* USAR) RS485 */ +#define AT91C_US_USMODE_HWHSH ((unsigned int) 0x2) /* USAR) Hardware Handshaking */ +#define AT91C_US_USMODE_MODEM ((unsigned int) 0x3) /* USAR) Modem */ +#define AT91C_US_USMODE_ISO7816_0 ((unsigned int) 0x4) /* USAR) ISO7816 protocol: T = 0 */ +#define AT91C_US_USMODE_ISO7816_1 ((unsigned int) 0x6) /* USAR) ISO7816 protocol: T = 1 */ +#define AT91C_US_USMODE_IRDA ((unsigned int) 0x8) /* USAR) IrDA */ +#define AT91C_US_USMODE_SWHSH ((unsigned int) 0xC) /* USAR) Software Handshaking */ -#define AT91C_US_CLKS_CLOCK ((unsigned int) 0x0 << 4) /* USAR) Clock */ -#define AT91C_US_CLKS_FDIV1 ((unsigned int) 0x1 << 4) /* USAR) fdiv1 */ -#define AT91C_US_CLKS_SLOW ((unsigned int) 0x2 << 4) /* USAR) slow_clock (ARM) */ -#define AT91C_US_CLKS_EXT ((unsigned int) 0x3 << 4) /* USAR) External (SCK) */ +#define AT91C_US_CLKS_CLOCK ((unsigned int) 0x0 << 4) /* USAR) Clock */ +#define AT91C_US_CLKS_FDIV1 ((unsigned int) 0x1 << 4) /* USAR) fdiv1 */ +#define AT91C_US_CLKS_SLOW ((unsigned int) 0x2 << 4) /* USAR) slow_clock (ARM) */ +#define AT91C_US_CLKS_EXT ((unsigned int) 0x3 << 4) /* USAR) External (SCK) */ -#define AT91C_US_CHRL_5_BITS ((unsigned int) 0x0 << 6) /* USAR) Character Length: 5 bits */ -#define AT91C_US_CHRL_6_BITS ((unsigned int) 0x1 << 6) /* USAR) Character Length: 6 bits */ -#define AT91C_US_CHRL_7_BITS ((unsigned int) 0x2 << 6) /* USAR) Character Length: 7 bits */ -#define AT91C_US_CHRL_8_BITS ((unsigned int) 0x3 << 6) /* USAR) Character Length: 8 bits */ +#define AT91C_US_CHRL_5_BITS ((unsigned int) 0x0 << 6) /* USAR) Character Length: 5 bits */ +#define AT91C_US_CHRL_6_BITS ((unsigned int) 0x1 << 6) /* USAR) Character Length: 6 bits */ +#define AT91C_US_CHRL_7_BITS ((unsigned int) 0x2 << 6) /* USAR) Character Length: 7 bits */ +#define AT91C_US_CHRL_8_BITS ((unsigned int) 0x3 << 6) /* USAR) Character Length: 8 bits */ -#define AT91C_US_PAR_EVEN ((unsigned int) 0x0 << 9) /* DBGU Even Parity */ -#define AT91C_US_PAR_ODD ((unsigned int) 0x1 << 9) /* DBGU Odd Parity */ -#define AT91C_US_PAR_SPACE ((unsigned int) 0x2 << 9) /* DBGU Parity forced to 0 (Space) */ -#define AT91C_US_PAR_MARK ((unsigned int) 0x3 << 9) /* DBGU Parity forced to 1 (Mark) */ -#define AT91C_US_PAR_NONE ((unsigned int) 0x4 << 9) /* DBGU No Parity */ -#define AT91C_US_PAR_MULTI_DROP ((unsigned int) 0x6 << 9) /* DBGU Multi-drop mode */ +#define AT91C_US_PAR_EVEN ((unsigned int) 0x0 << 9) /* DBGU Even Parity */ +#define AT91C_US_PAR_ODD ((unsigned int) 0x1 << 9) /* DBGU Odd Parity */ +#define AT91C_US_PAR_SPACE ((unsigned int) 0x2 << 9) /* DBGU Parity forced to 0 (Space) */ +#define AT91C_US_PAR_MARK ((unsigned int) 0x3 << 9) /* DBGU Parity forced to 1 (Mark) */ +#define AT91C_US_PAR_NONE ((unsigned int) 0x4 << 9) /* DBGU No Parity */ +#define AT91C_US_PAR_MULTI_DROP ((unsigned int) 0x6 << 9) /* DBGU Multi-drop mode */ -#define AT91C_US_NBSTOP_1_BIT ((unsigned int) 0x0 << 12) /* USART 1 stop bit */ -#define AT91C_US_NBSTOP_15_BIT ((unsigned int) 0x1 << 12) /* USART Asynchronous (SYNC=0) 2 stop bits Synchronous (SYNC=1) 2 stop bits */ -#define AT91C_US_NBSTOP_2_BIT ((unsigned int) 0x2 << 12) /* USART 2 stop bits */ +#define AT91C_US_NBSTOP_1_BIT ((unsigned int) 0x0 << 12) /* USART 1 stop bit */ +#define AT91C_US_NBSTOP_15_BIT ((unsigned int) 0x1 << 12) /* USART Asynchronous (SYNC=0) 2 stop bits Synchronous (SYNC=1) 2 stop bits */ +#define AT91C_US_NBSTOP_2_BIT ((unsigned int) 0x2 << 12) /* USART 2 stop bits */ -#define MCK 48054857 -#define BR 115200 /* Baud Rate */ -#define BRD (MCK/16/BR) /* Baud Rate Divisor */ +#define MCK 48054857 +#define BR 115200 /* Baud Rate */ +#define BRD (MCK/16/BR) /* Baud Rate Divisor */ #endif diff --git a/libcpu/arm/AT91SAM7S/stack.c b/libcpu/arm/AT91SAM7S/stack.c index 6f8bd13bf9..23fce8e6e2 100644 --- a/libcpu/arm/AT91SAM7S/stack.c +++ b/libcpu/arm/AT91SAM7S/stack.c @@ -1,5 +1,5 @@ /* - * Copyright (c) 2006-2018, RT-Thread Development Team + * Copyright (c) 2006-2021, RT-Thread Development Team * * SPDX-License-Identifier: Apache-2.0 * diff --git a/libcpu/arm/AT91SAM7S/trap.c b/libcpu/arm/AT91SAM7S/trap.c index 208e568950..aa9df7c74b 100644 --- a/libcpu/arm/AT91SAM7S/trap.c +++ b/libcpu/arm/AT91SAM7S/trap.c @@ -1,5 +1,5 @@ /* - * Copyright (c) 2006-2018, RT-Thread Development Team + * Copyright (c) 2006-2021, RT-Thread Development Team * * SPDX-License-Identifier: Apache-2.0 * @@ -20,12 +20,12 @@ void rt_hw_trap_irq() { - rt_isr_handler_t hander = (rt_isr_handler_t)AT91C_AIC_IVR; + rt_isr_handler_t hander = (rt_isr_handler_t)AT91C_AIC_IVR; - hander(AT91C_AIC_ISR); + hander(AT91C_AIC_ISR); - /* end of interrupt */ - AT91C_AIC_EOICR = 0; + /* end of interrupt */ + AT91C_AIC_EOICR = 0; } void rt_hw_trap_fiq() diff --git a/libcpu/arm/AT91SAM7X/cpu.c b/libcpu/arm/AT91SAM7X/cpu.c index 046f7e8ced..ffa4092900 100644 --- a/libcpu/arm/AT91SAM7X/cpu.c +++ b/libcpu/arm/AT91SAM7X/cpu.c @@ -1,5 +1,5 @@ /* - * Copyright (c) 2006-2018, RT-Thread Development Team + * Copyright (c) 2006-2021, RT-Thread Development Team * * SPDX-License-Identifier: Apache-2.0 * @@ -30,9 +30,9 @@ RT_WEAK void rt_hw_cpu_reset() */ RT_WEAK void rt_hw_cpu_shutdown() { - rt_kprintf("shutdown...\n"); + rt_kprintf("shutdown...\n"); - while (1); + while (1); } /*@}*/ diff --git a/libcpu/arm/AT91SAM7X/interrupt.c b/libcpu/arm/AT91SAM7X/interrupt.c index 0c37f63ada..3a28f507ca 100644 --- a/libcpu/arm/AT91SAM7X/interrupt.c +++ b/libcpu/arm/AT91SAM7X/interrupt.c @@ -1,5 +1,5 @@ /* - * Copyright (c) 2006-2018, RT-Thread Development Team + * Copyright (c) 2006-2021, RT-Thread Development Team * * SPDX-License-Identifier: Apache-2.0 * @@ -13,10 +13,10 @@ #include <rthw.h> #include "AT91SAM7X256.h" -#define MAX_HANDLERS 32 +#define MAX_HANDLERS 32 /* exception and interrupt handler table */ -struct rt_irq_desc irq_desc[MAX_HANDLERS]; +struct rt_irq_desc irq_desc[MAX_HANDLERS]; extern rt_uint32_t rt_interrupt_nest; @@ -30,7 +30,7 @@ rt_uint32_t rt_thread_switch_interrupt_flag; static void rt_hw_interrupt_handler(int vector, void *param) { - rt_kprintf("Unhandled interrupt %d occured!!!\n", vector); + rt_kprintf("Unhandled interrupt %d occured!!!\n", vector); } /** @@ -38,7 +38,7 @@ static void rt_hw_interrupt_handler(int vector, void *param) */ void rt_hw_interrupt_init(void) { - rt_base_t index; + rt_base_t index; /* init exceptions table */ for(index=0; index < MAX_HANDLERS; index++) @@ -47,16 +47,16 @@ void rt_hw_interrupt_init(void) irq_desc[index].param = RT_NULL; } - for (index = 0; index < MAX_HANDLERS; index ++) - { - AT91C_BASE_AIC->AIC_SVR[index] = (rt_uint32_t)rt_hw_interrupt_handler; - } + for (index = 0; index < MAX_HANDLERS; index ++) + { + AT91C_BASE_AIC->AIC_SVR[index] = (rt_uint32_t)rt_hw_interrupt_handler; + } - /* init interrupt nest, and context in thread sp */ - rt_interrupt_nest = 0; - rt_interrupt_from_thread = 0; - rt_interrupt_to_thread = 0; - rt_thread_switch_interrupt_flag = 0; + /* init interrupt nest, and context in thread sp */ + rt_interrupt_nest = 0; + rt_interrupt_from_thread = 0; + rt_interrupt_to_thread = 0; + rt_thread_switch_interrupt_flag = 0; } /** @@ -65,11 +65,11 @@ void rt_hw_interrupt_init(void) */ void rt_hw_interrupt_mask(int vector) { - /* disable interrupt */ - AT91C_BASE_AIC->AIC_IDCR = 1 << vector; + /* disable interrupt */ + AT91C_BASE_AIC->AIC_IDCR = 1 << vector; - /* clear interrupt */ - AT91C_BASE_AIC->AIC_ICCR = 1 << vector; + /* clear interrupt */ + AT91C_BASE_AIC->AIC_ICCR = 1 << vector; } /** @@ -78,7 +78,7 @@ void rt_hw_interrupt_mask(int vector) */ void rt_hw_interrupt_umask(int vector) { - AT91C_BASE_AIC->AIC_IECR = 1 << vector; + AT91C_BASE_AIC->AIC_IECR = 1 << vector; } /** @@ -90,21 +90,21 @@ void rt_hw_interrupt_umask(int vector) * * @return the old handler */ -rt_isr_handler_t rt_hw_interrupt_install(int vector, rt_isr_handler_t handler, - void *param, const char *name) +rt_isr_handler_t rt_hw_interrupt_install(int vector, rt_isr_handler_t handler, + void *param, const char *name) { - rt_isr_handler_t old_handler = RT_NULL; - if(vector >= 0 && vector < MAX_HANDLERS) - { - old_handler = irq_desc[vector].handler; - if (handler != RT_NULL) - { - irq_desc[vector].handler = (rt_isr_handler_t)handler; - irq_desc[vector].param = param; - } - } + rt_isr_handler_t old_handler = RT_NULL; + if(vector >= 0 && vector < MAX_HANDLERS) + { + old_handler = irq_desc[vector].handler; + if (handler != RT_NULL) + { + irq_desc[vector].handler = (rt_isr_handler_t)handler; + irq_desc[vector].param = param; + } + } - return old_handler; + return old_handler; } /*@}*/ diff --git a/libcpu/arm/AT91SAM7X/stack.c b/libcpu/arm/AT91SAM7X/stack.c index ef60b1a760..caa4826014 100644 --- a/libcpu/arm/AT91SAM7X/stack.c +++ b/libcpu/arm/AT91SAM7X/stack.c @@ -1,5 +1,5 @@ /* - * Copyright (c) 2006-2018, RT-Thread Development Team + * Copyright (c) 2006-2021, RT-Thread Development Team * * SPDX-License-Identifier: Apache-2.0 * diff --git a/libcpu/arm/AT91SAM7X/trap.c b/libcpu/arm/AT91SAM7X/trap.c index 1c1c351ff8..3c012dd85e 100644 --- a/libcpu/arm/AT91SAM7X/trap.c +++ b/libcpu/arm/AT91SAM7X/trap.c @@ -1,5 +1,5 @@ /* - * Copyright (c) 2006-2018, RT-Thread Development Team + * Copyright (c) 2006-2021, RT-Thread Development Team * * SPDX-License-Identifier: Apache-2.0 * @@ -20,17 +20,17 @@ void rt_hw_trap_irq(void) { - int irqno; - extern struct rt_irq_desc irq_desc[]; + int irqno; + extern struct rt_irq_desc irq_desc[]; - /* get interrupt number */ - irqno = AT91C_BASE_AIC->AIC_ISR; + /* get interrupt number */ + irqno = AT91C_BASE_AIC->AIC_ISR; - /* invoke isr with parameters */ - irq_desc[irqno].handler(irqno, irq_desc[irqno].param); + /* invoke isr with parameters */ + irq_desc[irqno].handler(irqno, irq_desc[irqno].param); - /* end of interrupt */ - AT91C_BASE_AIC->AIC_EOICR = 0; + /* end of interrupt */ + AT91C_BASE_AIC->AIC_EOICR = 0; } void rt_hw_trap_fiq(void) @@ -41,9 +41,9 @@ void rt_hw_trap_fiq(void) extern struct rt_thread* rt_current_thread; void rt_hw_trap_abort(void) { - rt_kprintf("Abort occured!!! Thread [%s] suspended.\n",rt_current_thread->name); - rt_thread_suspend(rt_current_thread); - rt_schedule(); + rt_kprintf("Abort occured!!! Thread [%s] suspended.\n",rt_current_thread->name); + rt_thread_suspend(rt_current_thread); + rt_schedule(); } /*@}*/ diff --git a/libcpu/arm/SConscript b/libcpu/arm/SConscript index f6ea13fb91..3d0147658f 100644 --- a/libcpu/arm/SConscript +++ b/libcpu/arm/SConscript @@ -6,11 +6,13 @@ from building import * Import('rtconfig') cwd = GetCurrentDir() +list = os.listdir(cwd) # add common code files group = SConscript(os.path.join('common', 'SConscript')) # cpu porting code files -group = group + SConscript(os.path.join(rtconfig.CPU, 'SConscript')) +if rtconfig.CPU in list: + group = group + SConscript(os.path.join(rtconfig.CPU, 'SConscript')) Return('group') diff --git a/libcpu/arm/am335x/am33xx.h b/libcpu/arm/am335x/am33xx.h index 99a65ac915..3112a8ac15 100644 --- a/libcpu/arm/am335x/am33xx.h +++ b/libcpu/arm/am335x/am33xx.h @@ -1,5 +1,5 @@ /* - * Copyright (c) 2006-2018, RT-Thread Development Team + * Copyright (c) 2006-2021, RT-Thread Development Team * * SPDX-License-Identifier: Apache-2.0 * @@ -9,8 +9,8 @@ #ifndef __AM33XX_H__ #define __AM33XX_H__ -#define REG32(x) (*((volatile unsigned int *)(x))) -#define REG16(x) (*((volatile unsigned short *)(x))) +#define REG32(x) (*((volatile unsigned int *)(x))) +#define REG16(x) (*((volatile unsigned short *)(x))) /** Cache Line size in ARM Cortex-A8. */ #define AM33XX_CACHELINE_SIZE (64) @@ -198,22 +198,22 @@ #define CM_DPLL_CLKSEL_TIMER2_CLK(base) REG32(CM_DPLL(base) + 0x8) /* timer registers */ -#define DMTIMER_TIDR(base) REG32(base + 0x0) -#define DMTIMER_TIOCP_CFG(base) REG32(base + 0x10) -#define DMTIMER_IRQ_EOI(base) REG32(base + 0x20) -#define DMTIMER_IRQSTATUS_RAW(base) REG32(base + 0x24) -#define DMTIMER_IRQSTATUS(base) REG32(base + 0x28) -#define DMTIMER_IRQENABLE_SET(base) REG32(base + 0x2C) -#define DMTIMER_IRQENABLE_CLR(base) REG32(base + 0x30) -#define DMTIMER_IRQWAKEEN(base) REG32(base + 0x34) -#define DMTIMER_TCLR(base) REG32(base + 0x38) -#define DMTIMER_TCRR(base) REG32(base + 0x3C) -#define DMTIMER_TLDR(base) REG32(base + 0x40) -#define DMTIMER_TTGR(base) REG32(base + 0x44) -#define DMTIMER_TWPS(base) REG32(base + 0x48) -#define DMTIMER_TMAR(base) REG32(base + 0x4C) -#define DMTIMER_TCAR(base, n) REG32(base + 0x50 + (((n) - 1) * 8)) -#define DMTIMER_TSICR(base) REG32(base + 0x54) +#define DMTIMER_TIDR(base) REG32(base + 0x0) +#define DMTIMER_TIOCP_CFG(base) REG32(base + 0x10) +#define DMTIMER_IRQ_EOI(base) REG32(base + 0x20) +#define DMTIMER_IRQSTATUS_RAW(base) REG32(base + 0x24) +#define DMTIMER_IRQSTATUS(base) REG32(base + 0x28) +#define DMTIMER_IRQENABLE_SET(base) REG32(base + 0x2C) +#define DMTIMER_IRQENABLE_CLR(base) REG32(base + 0x30) +#define DMTIMER_IRQWAKEEN(base) REG32(base + 0x34) +#define DMTIMER_TCLR(base) REG32(base + 0x38) +#define DMTIMER_TCRR(base) REG32(base + 0x3C) +#define DMTIMER_TLDR(base) REG32(base + 0x40) +#define DMTIMER_TTGR(base) REG32(base + 0x44) +#define DMTIMER_TWPS(base) REG32(base + 0x48) +#define DMTIMER_TMAR(base) REG32(base + 0x4C) +#define DMTIMER_TCAR(base, n) REG32(base + 0x50 + (((n) - 1) * 8)) +#define DMTIMER_TSICR(base) REG32(base + 0x54) #define EMU_INT 0 #define COMMTX_INT 1 @@ -317,33 +317,33 @@ struct rt_hw_register { - unsigned long r0; - unsigned long r1; - unsigned long r2; - unsigned long r3; - unsigned long r4; - unsigned long r5; - unsigned long r6; - unsigned long r7; - unsigned long r8; - unsigned long r9; - unsigned long r10; - unsigned long fp; - unsigned long ip; - unsigned long sp; - unsigned long lr; - unsigned long pc; - unsigned long cpsr; - unsigned long ORIG_r0; + unsigned long r0; + unsigned long r1; + unsigned long r2; + unsigned long r3; + unsigned long r4; + unsigned long r5; + unsigned long r6; + unsigned long r7; + unsigned long r8; + unsigned long r9; + unsigned long r10; + unsigned long fp; + unsigned long ip; + unsigned long sp; + unsigned long lr; + unsigned long pc; + unsigned long cpsr; + unsigned long ORIG_r0; }; -#define USERMODE 0x10 -#define FIQMODE 0x11 -#define IRQMODE 0x12 -#define SVCMODE 0x13 -#define ABORTMODE 0x17 -#define UNDEFMODE 0x1b -#define MODEMASK 0x1f -#define NOINT 0xc0 +#define USERMODE 0x10 +#define FIQMODE 0x11 +#define IRQMODE 0x12 +#define SVCMODE 0x13 +#define ABORTMODE 0x17 +#define UNDEFMODE 0x1b +#define MODEMASK 0x1f +#define NOINT 0xc0 #endif diff --git a/libcpu/arm/am335x/context_iar.S b/libcpu/arm/am335x/context_iar.S index c53e15a23a..1266d8cf74 100644 --- a/libcpu/arm/am335x/context_iar.S +++ b/libcpu/arm/am335x/context_iar.S @@ -1,21 +1,7 @@ ;/* -; * File : context_iar.S -; * This file is part of RT-Thread RTOS -; * COPYRIGHT (C) 2006, RT-Thread Development Team +; * Copyright (c) 2006-2021, RT-Thread Development Team ; * -; * This program is free software; you can redistribute it and/or modify -; * it under the terms of the GNU General Public License as published by -; * the Free Software Foundation; either version 2 of the License, or -; * (at your option) any later version. -; * -; * This program is distributed in the hope that it will be useful, -; * but WITHOUT ANY WARRANTY; without even the implied warranty of -; * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -; * GNU General Public License for more details. -; * -; * You should have received a copy of the GNU General Public License along -; * with this program; if not, write to the Free Software Foundation, Inc., -; * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA. +; * SPDX-License-Identifier: Apache-2.0 ; * ; * Change Logs: ; * Date Author Notes diff --git a/libcpu/arm/am335x/cpu.c b/libcpu/arm/am335x/cpu.c index 469276466b..19161a1817 100644 --- a/libcpu/arm/am335x/cpu.c +++ b/libcpu/arm/am335x/cpu.c @@ -1,5 +1,5 @@ /* - * Copyright (c) 2006-2018, RT-Thread Development Team + * Copyright (c) 2006-2021, RT-Thread Development Team * * SPDX-License-Identifier: Apache-2.0 * @@ -17,74 +17,74 @@ */ /*@{*/ -#define ICACHE_MASK (rt_uint32_t)(1 << 12) -#define DCACHE_MASK (rt_uint32_t)(1 << 2) +#define ICACHE_MASK (rt_uint32_t)(1 << 12) +#define DCACHE_MASK (rt_uint32_t)(1 << 2) #if defined(__CC_ARM) rt_inline rt_uint32_t cp15_rd(void) { - rt_uint32_t i; + rt_uint32_t i; - __asm - { - mrc p15, 0, i, c1, c0, 0 - } + __asm + { + mrc p15, 0, i, c1, c0, 0 + } - return i; + return i; } rt_inline void cache_enable(rt_uint32_t bit) { - rt_uint32_t value; + rt_uint32_t value; - __asm - { - mrc p15, 0, value, c1, c0, 0 - orr value, value, bit - mcr p15, 0, value, c1, c0, 0 - } + __asm + { + mrc p15, 0, value, c1, c0, 0 + orr value, value, bit + mcr p15, 0, value, c1, c0, 0 + } } rt_inline void cache_disable(rt_uint32_t bit) { - rt_uint32_t value; + rt_uint32_t value; - __asm - { - mrc p15, 0, value, c1, c0, 0 - bic value, value, bit - mcr p15, 0, value, c1, c0, 0 - } + __asm + { + mrc p15, 0, value, c1, c0, 0 + bic value, value, bit + mcr p15, 0, value, c1, c0, 0 + } } #elif defined(__GNUC__) rt_inline rt_uint32_t cp15_rd(void) { - rt_uint32_t i; + rt_uint32_t i; - asm ("mrc p15, 0, %0, c1, c0, 0":"=r" (i)); - return i; + asm ("mrc p15, 0, %0, c1, c0, 0":"=r" (i)); + return i; } rt_inline void cache_enable(rt_uint32_t bit) { - __asm__ __volatile__( \ - "mrc p15,0,r0,c1,c0,0\n\t" \ - "orr r0,r0,%0\n\t" \ - "mcr p15,0,r0,c1,c0,0" \ - : \ - :"r" (bit) \ - :"memory"); + __asm__ __volatile__( \ + "mrc p15,0,r0,c1,c0,0\n\t" \ + "orr r0,r0,%0\n\t" \ + "mcr p15,0,r0,c1,c0,0" \ + : \ + :"r" (bit) \ + :"memory"); } rt_inline void cache_disable(rt_uint32_t bit) { - __asm__ __volatile__( \ - "mrc p15,0,r0,c1,c0,0\n\t" \ - "bic r0,r0,%0\n\t" \ - "mcr p15,0,r0,c1,c0,0" \ - : \ - :"r" (bit) \ - :"memory"); + __asm__ __volatile__( \ + "mrc p15,0,r0,c1,c0,0\n\t" \ + "bic r0,r0,%0\n\t" \ + "mcr p15,0,r0,c1,c0,0" \ + : \ + :"r" (bit) \ + :"memory"); } #endif @@ -96,7 +96,7 @@ rt_inline void cache_disable(rt_uint32_t bit) */ void rt_hw_cpu_icache_enable() { - cache_enable(ICACHE_MASK); + cache_enable(ICACHE_MASK); } /** @@ -105,7 +105,7 @@ void rt_hw_cpu_icache_enable() */ void rt_hw_cpu_icache_disable() { - cache_disable(ICACHE_MASK); + cache_disable(ICACHE_MASK); } /** @@ -114,7 +114,7 @@ void rt_hw_cpu_icache_disable() */ rt_base_t rt_hw_cpu_icache_status() { - return (cp15_rd() & ICACHE_MASK); + return (cp15_rd() & ICACHE_MASK); } /** @@ -123,7 +123,7 @@ rt_base_t rt_hw_cpu_icache_status() */ void rt_hw_cpu_dcache_enable() { - cache_enable(DCACHE_MASK); + cache_enable(DCACHE_MASK); } /** @@ -132,7 +132,7 @@ void rt_hw_cpu_dcache_enable() */ void rt_hw_cpu_dcache_disable() { - cache_disable(DCACHE_MASK); + cache_disable(DCACHE_MASK); } /** @@ -141,7 +141,7 @@ void rt_hw_cpu_dcache_disable() */ rt_base_t rt_hw_cpu_dcache_status() { - return (cp15_rd() & DCACHE_MASK); + return (cp15_rd() & DCACHE_MASK); } #endif @@ -151,14 +151,14 @@ rt_base_t rt_hw_cpu_dcache_status() */ RT_WEAK void rt_hw_cpu_shutdown() { - rt_uint32_t level; - rt_kprintf("shutdown...\n"); + rt_uint32_t level; + rt_kprintf("shutdown...\n"); - level = rt_hw_interrupt_disable(); - while (level) - { - RT_ASSERT(0); - } + level = rt_hw_interrupt_disable(); + while (level) + { + RT_ASSERT(0); + } } /*@}*/ diff --git a/libcpu/arm/am335x/interrupt.c b/libcpu/arm/am335x/interrupt.c index 3acd868496..c4c5e8d7eb 100644 --- a/libcpu/arm/am335x/interrupt.c +++ b/libcpu/arm/am335x/interrupt.c @@ -1,5 +1,5 @@ /* - * Copyright (c) 2006-2018, RT-Thread Development Team + * Copyright (c) 2006-2021, RT-Thread Development Team * * SPDX-License-Identifier: Apache-2.0 * @@ -17,7 +17,7 @@ #define AINTC_BASE AM33XX_AINTC_REGS -#define MAX_HANDLERS 128 +#define MAX_HANDLERS 128 extern volatile rt_uint8_t rt_interrupt_nest; @@ -59,13 +59,13 @@ extern int system_vectors; static void rt_hw_vector_init(void) { unsigned int *dest = (unsigned int *)AM335X_VECTOR_BASE; - + #ifdef __ICCARM__ unsigned int *src = (unsigned int *)&__vector; #else unsigned int *src = (unsigned int *)&system_vectors; #endif - + rt_memcpy(dest, src, 16 * 4); rt_cpu_vector_set_base(AM335X_VECTOR_BASE); } diff --git a/libcpu/arm/am335x/interrupt.h b/libcpu/arm/am335x/interrupt.h index 7461f94da0..90f392f407 100644 --- a/libcpu/arm/am335x/interrupt.h +++ b/libcpu/arm/am335x/interrupt.h @@ -1,5 +1,5 @@ /* - * Copyright (c) 2006-2018, RT-Thread Development Team + * Copyright (c) 2006-2021, RT-Thread Development Team * * SPDX-License-Identifier: Apache-2.0 * @@ -14,28 +14,28 @@ #define INT_IRQ 0x00 #define INT_FIQ 0x01 -#define INTC_REVISION(hw_base) REG32((hw_base) + 0x0) -#define INTC_SYSCONFIG(hw_base) REG32((hw_base) + 0x10) -#define INTC_SYSSTATUS(hw_base) REG32((hw_base) + 0x14) -#define INTC_SIR_IRQ(hw_base) REG32((hw_base) + 0x40) -#define INTC_SIR_FIQ(hw_base) REG32((hw_base) + 0x44) -#define INTC_CONTROL(hw_base) REG32((hw_base) + 0x48) -#define INTC_PROTECTION(hw_base) REG32((hw_base) + 0x4c) -#define INTC_IDLE(hw_base) REG32((hw_base) + 0x50) -#define INTC_IRQ_PRIORITY(hw_base) REG32((hw_base) + 0x60) -#define INTC_FIQ_PRIORITY(hw_base) REG32((hw_base) + 0x64) -#define INTC_THRESHOLD(hw_base) REG32((hw_base) + 0x68) -#define INTC_SICR(hw_base) REG32((hw_base) + 0x6c) -#define INTC_SCR(hw_base, n) REG32((hw_base) + 0x70 + ((n) * 0x04)) -#define INTC_ITR(hw_base, n) REG32((hw_base) + 0x80 + ((n) * 0x20)) -#define INTC_MIR(hw_base, n) REG32((hw_base) + 0x84 + ((n) * 0x20)) -#define INTC_MIR_CLEAR(hw_base, n) REG32((hw_base) + 0x88 + ((n) * 0x20)) -#define INTC_MIR_SET(hw_base, n) REG32((hw_base) + 0x8c + ((n) * 0x20)) -#define INTC_ISR_SET(hw_base, n) REG32((hw_base) + 0x90 + ((n) * 0x20)) -#define INTC_ISR_CLEAR(hw_base, n) REG32((hw_base) + 0x94 + ((n) * 0x20)) +#define INTC_REVISION(hw_base) REG32((hw_base) + 0x0) +#define INTC_SYSCONFIG(hw_base) REG32((hw_base) + 0x10) +#define INTC_SYSSTATUS(hw_base) REG32((hw_base) + 0x14) +#define INTC_SIR_IRQ(hw_base) REG32((hw_base) + 0x40) +#define INTC_SIR_FIQ(hw_base) REG32((hw_base) + 0x44) +#define INTC_CONTROL(hw_base) REG32((hw_base) + 0x48) +#define INTC_PROTECTION(hw_base) REG32((hw_base) + 0x4c) +#define INTC_IDLE(hw_base) REG32((hw_base) + 0x50) +#define INTC_IRQ_PRIORITY(hw_base) REG32((hw_base) + 0x60) +#define INTC_FIQ_PRIORITY(hw_base) REG32((hw_base) + 0x64) +#define INTC_THRESHOLD(hw_base) REG32((hw_base) + 0x68) +#define INTC_SICR(hw_base) REG32((hw_base) + 0x6c) +#define INTC_SCR(hw_base, n) REG32((hw_base) + 0x70 + ((n) * 0x04)) +#define INTC_ITR(hw_base, n) REG32((hw_base) + 0x80 + ((n) * 0x20)) +#define INTC_MIR(hw_base, n) REG32((hw_base) + 0x84 + ((n) * 0x20)) +#define INTC_MIR_CLEAR(hw_base, n) REG32((hw_base) + 0x88 + ((n) * 0x20)) +#define INTC_MIR_SET(hw_base, n) REG32((hw_base) + 0x8c + ((n) * 0x20)) +#define INTC_ISR_SET(hw_base, n) REG32((hw_base) + 0x90 + ((n) * 0x20)) +#define INTC_ISR_CLEAR(hw_base, n) REG32((hw_base) + 0x94 + ((n) * 0x20)) #define INTC_PENDING_IRQ(hw_base, n) REG32((hw_base) + 0x98 + ((n) * 0x20)) #define INTC_PENDING_FIQ(hw_base, n) REG32((hw_base) + 0x9c + ((n) * 0x20)) -#define INTC_ILR(hw_base, n) REG32((hw_base) + 0x100 + ((n) * 0x04)) +#define INTC_ILR(hw_base, n) REG32((hw_base) + 0x100 + ((n) * 0x04)) void rt_hw_interrupt_control(int vector, int priority, int route); int rt_hw_interrupt_get_active(int fiq_irq); diff --git a/libcpu/arm/am335x/mmu.c b/libcpu/arm/am335x/mmu.c index babe825298..fbd886d0e6 100644 --- a/libcpu/arm/am335x/mmu.c +++ b/libcpu/arm/am335x/mmu.c @@ -1,5 +1,5 @@ /* - * Copyright (c) 2006-2018, RT-Thread Development Team + * Copyright (c) 2006-2021, RT-Thread Development Team * * SPDX-License-Identifier: Apache-2.0 * @@ -22,122 +22,122 @@ extern void rt_cpu_tlb_set(register rt_uint32_t i); void mmu_disable_dcache() { - rt_cpu_dcache_disable(); + rt_cpu_dcache_disable(); } void mmu_enable_dcache() { - rt_hw_cpu_dcache_enable(); + rt_hw_cpu_dcache_enable(); } void mmu_disable_icache() { - rt_cpu_icache_disable(); + rt_cpu_icache_disable(); } void mmu_enable_icache() { - rt_hw_cpu_icache_enable(); + rt_hw_cpu_icache_enable(); } void mmu_disable() { - rt_cpu_mmu_disable(); + rt_cpu_mmu_disable(); } void mmu_enable() { - rt_cpu_mmu_enable(); + rt_cpu_mmu_enable(); } void mmu_setttbase(register rt_uint32_t i) { - register rt_uint32_t value; + register rt_uint32_t value; /* Invalidates all TLBs.Domain access is selected as * client by configuring domain access register, * in that case access controlled by permission value * set by page table entry */ - value = 0; - asm volatile ("mcr p15, 0, %0, c8, c7, 0"::"r"(value)); + value = 0; + asm volatile ("mcr p15, 0, %0, c8, c7, 0"::"r"(value)); - value = 0x55555555; - asm volatile ("mcr p15, 0, %0, c3, c0, 0"::"r"(value)); - - rt_cpu_tlb_set(i); + value = 0x55555555; + asm volatile ("mcr p15, 0, %0, c3, c0, 0"::"r"(value)); + + rt_cpu_tlb_set(i); } void mmu_set_domain(register rt_uint32_t i) { - asm volatile ("mcr p15,0, %0, c3, c0, 0": :"r" (i)); + asm volatile ("mcr p15,0, %0, c3, c0, 0": :"r" (i)); } void mmu_enable_alignfault() { - register rt_uint32_t i; + register rt_uint32_t i; - /* read control register */ - asm volatile ("mrc p15, 0, %0, c1, c0, 0":"=r" (i)); + /* read control register */ + asm volatile ("mrc p15, 0, %0, c1, c0, 0":"=r" (i)); - i |= (1 << 1); + i |= (1 << 1); - /* write back to control register */ - asm volatile ("mcr p15, 0, %0, c1, c0, 0": :"r" (i)); + /* write back to control register */ + asm volatile ("mcr p15, 0, %0, c1, c0, 0": :"r" (i)); } void mmu_disable_alignfault() { - register rt_uint32_t i; + register rt_uint32_t i; - /* read control register */ - asm volatile ("mrc p15, 0, %0, c1, c0, 0":"=r" (i)); + /* read control register */ + asm volatile ("mrc p15, 0, %0, c1, c0, 0":"=r" (i)); - i &= ~(1 << 1); + i &= ~(1 << 1); - /* write back to control register */ - asm volatile ("mcr p15, 0, %0, c1, c0, 0": :"r" (i)); + /* write back to control register */ + asm volatile ("mcr p15, 0, %0, c1, c0, 0": :"r" (i)); } void mmu_clean_invalidated_cache_index(int index) { - asm volatile ("mcr p15, 0, %0, c7, c14, 2": :"r" (index)); + asm volatile ("mcr p15, 0, %0, c7, c14, 2": :"r" (index)); } void mmu_clean_dcache(rt_uint32_t buffer, rt_uint32_t size) { - unsigned int ptr; + unsigned int ptr; - ptr = buffer & ~0x1f; + ptr = buffer & ~0x1f; - while (ptr < buffer + size) - { - asm volatile ("mcr p15, 0, %0, c7, c10, 1": :"r" (ptr)); - ptr += 32; - } + while (ptr < buffer + size) + { + asm volatile ("mcr p15, 0, %0, c7, c10, 1": :"r" (ptr)); + ptr += 32; + } } void mmu_invalidate_dcache(rt_uint32_t buffer, rt_uint32_t size) { - unsigned int ptr; + unsigned int ptr; - ptr = buffer & ~0x1f; + ptr = buffer & ~0x1f; - while (ptr < buffer + size) - { - asm volatile ("mcr p15, 0, %0, c7, c6, 1": :"r" (ptr)); - ptr += 32; - } + while (ptr < buffer + size) + { + asm volatile ("mcr p15, 0, %0, c7, c6, 1": :"r" (ptr)); + ptr += 32; + } } void mmu_invalidate_tlb() { - asm volatile ("mcr p15, 0, %0, c8, c7, 0": :"r" (0)); + asm volatile ("mcr p15, 0, %0, c8, c7, 0": :"r" (0)); } void mmu_invalidate_icache() { - asm volatile ("mcr p15, 0, %0, c7, c5, 0": :"r" (0)); + asm volatile ("mcr p15, 0, %0, c7, c5, 0": :"r" (0)); } /* level1 page table */ @@ -150,8 +150,8 @@ void mmu_setmtt(rt_uint32_t vaddrStart, rt_uint32_t vaddrEnd, rt_uint32_t paddrS nSec=(vaddrEnd>>20)-(vaddrStart>>20); for(i=0;i<=nSec;i++) { - *pTT = attr |(((paddrStart>>20)+i)<<20); - pTT++; + *pTT = attr |(((paddrStart>>20)+i)<<20); + pTT++; } } @@ -161,21 +161,21 @@ RT_WEAK void mmu_setmtts(void) mmu_setmtt(0x00000000, 0xFFFFFFFF, 0x00000000, RW_NCNB); /* None cached for 4G memory */ mmu_setmtt(0x80200000, 0x80800000 - 1, 0x80200000, RW_CB); /* 126M cached DDR memory */ mmu_setmtt(0x80000000, 0x80200000 - 1, 0x80000000, RW_NCNB); /* 2M none-cached DDR memory */ - mmu_setmtt(0x402F0000, 0x40300000 - 1, 0x402F0000, RW_CB); /* 63K OnChip memory */ + mmu_setmtt(0x402F0000, 0x40300000 - 1, 0x402F0000, RW_CB); /* 63K OnChip memory */ } void rt_hw_mmu_init(void) { - /* disable I/D cache */ - mmu_disable_dcache(); - mmu_disable_icache(); - mmu_disable(); - mmu_invalidate_tlb(); + /* disable I/D cache */ + mmu_disable_dcache(); + mmu_disable_icache(); + mmu_disable(); + mmu_invalidate_tlb(); mmu_setmtts(); - /* set MMU table address */ - mmu_setttbase((rt_uint32_t)_page_table); + /* set MMU table address */ + mmu_setttbase((rt_uint32_t)_page_table); /* enables MMU */ mmu_enable(); diff --git a/libcpu/arm/am335x/mmu.h b/libcpu/arm/am335x/mmu.h index 73635d3a0e..706d669844 100644 --- a/libcpu/arm/am335x/mmu.h +++ b/libcpu/arm/am335x/mmu.h @@ -1,5 +1,5 @@ /* - * Copyright (c) 2006-2018, RT-Thread Development Team + * Copyright (c) 2006-2021, RT-Thread Development Team * * SPDX-License-Identifier: Apache-2.0 * @@ -13,27 +13,27 @@ #include <rtthread.h> -#define DESC_SEC (0x2) -#define CB (3<<2) //cache_on, write_back -#define CNB (2<<2) //cache_on, write_through -#define NCB (1<<2) //cache_off,WR_BUF on -#define NCNB (0<<2) //cache_off,WR_BUF off -#define AP_RW (3<<10) //supervisor=RW, user=RW -#define AP_RO (2<<10) //supervisor=RW, user=RO +#define DESC_SEC (0x2) +#define CB (3<<2) //cache_on, write_back +#define CNB (2<<2) //cache_on, write_through +#define NCB (1<<2) //cache_off,WR_BUF on +#define NCNB (0<<2) //cache_off,WR_BUF off +#define AP_RW (3<<10) //supervisor=RW, user=RW +#define AP_RO (2<<10) //supervisor=RW, user=RO -#define DOMAIN_FAULT (0x0) -#define DOMAIN_CHK (0x1) -#define DOMAIN_NOTCHK (0x3) -#define DOMAIN0 (0x0<<5) -#define DOMAIN1 (0x1<<5) +#define DOMAIN_FAULT (0x0) +#define DOMAIN_CHK (0x1) +#define DOMAIN_NOTCHK (0x3) +#define DOMAIN0 (0x0<<5) +#define DOMAIN1 (0x1<<5) -#define DOMAIN0_ATTR (DOMAIN_CHK<<0) -#define DOMAIN1_ATTR (DOMAIN_FAULT<<2) +#define DOMAIN0_ATTR (DOMAIN_CHK<<0) +#define DOMAIN1_ATTR (DOMAIN_FAULT<<2) -#define RW_CB (AP_RW|DOMAIN0|CB|DESC_SEC) /* Read/Write, cache, write back */ -#define RW_CNB (AP_RW|DOMAIN0|CNB|DESC_SEC) /* Read/Write, cache, write through */ -#define RW_NCNB (AP_RW|DOMAIN0|NCNB|DESC_SEC) /* Read/Write without cache and write buffer */ -#define RW_FAULT (AP_RW|DOMAIN1|NCNB|DESC_SEC) /* Read/Write without cache and write buffer */ +#define RW_CB (AP_RW|DOMAIN0|CB|DESC_SEC) /* Read/Write, cache, write back */ +#define RW_CNB (AP_RW|DOMAIN0|CNB|DESC_SEC) /* Read/Write, cache, write through */ +#define RW_NCNB (AP_RW|DOMAIN0|NCNB|DESC_SEC) /* Read/Write without cache and write buffer */ +#define RW_FAULT (AP_RW|DOMAIN1|NCNB|DESC_SEC) /* Read/Write without cache and write buffer */ void rt_hw_mmu_init(void); diff --git a/libcpu/arm/am335x/stack.c b/libcpu/arm/am335x/stack.c index 1dad930818..db3cb37e73 100644 --- a/libcpu/arm/am335x/stack.c +++ b/libcpu/arm/am335x/stack.c @@ -1,5 +1,5 @@ /* - * Copyright (c) 2006-2018, RT-Thread Development Team + * Copyright (c) 2006-2021, RT-Thread Development Team * * SPDX-License-Identifier: Apache-2.0 * diff --git a/libcpu/arm/am335x/trap.c b/libcpu/arm/am335x/trap.c index b77543da64..7c73ce93d3 100644 --- a/libcpu/arm/am335x/trap.c +++ b/libcpu/arm/am335x/trap.c @@ -1,5 +1,5 @@ /* - * Copyright (c) 2006-2018, RT-Thread Development Team + * Copyright (c) 2006-2021, RT-Thread Development Team * * SPDX-License-Identifier: Apache-2.0 * @@ -36,13 +36,13 @@ extern long list_thread(void); void rt_hw_show_register (struct rt_hw_register *regs) { - rt_kprintf("Execption:\n"); - rt_kprintf("r00:0x%08x r01:0x%08x r02:0x%08x r03:0x%08x\n", regs->r0, regs->r1, regs->r2, regs->r3); - rt_kprintf("r04:0x%08x r05:0x%08x r06:0x%08x r07:0x%08x\n", regs->r4, regs->r5, regs->r6, regs->r7); - rt_kprintf("r08:0x%08x r09:0x%08x r10:0x%08x\n", regs->r8, regs->r9, regs->r10); - rt_kprintf("fp :0x%08x ip :0x%08x\n", regs->fp, regs->ip); - rt_kprintf("sp :0x%08x lr :0x%08x pc :0x%08x\n", regs->sp, regs->lr, regs->pc); - rt_kprintf("cpsr:0x%08x\n", regs->cpsr); + rt_kprintf("Execption:\n"); + rt_kprintf("r00:0x%08x r01:0x%08x r02:0x%08x r03:0x%08x\n", regs->r0, regs->r1, regs->r2, regs->r3); + rt_kprintf("r04:0x%08x r05:0x%08x r06:0x%08x r07:0x%08x\n", regs->r4, regs->r5, regs->r6, regs->r7); + rt_kprintf("r08:0x%08x r09:0x%08x r10:0x%08x\n", regs->r8, regs->r9, regs->r10); + rt_kprintf("fp :0x%08x ip :0x%08x\n", regs->fp, regs->ip); + rt_kprintf("sp :0x%08x lr :0x%08x pc :0x%08x\n", regs->sp, regs->lr, regs->pc); + rt_kprintf("cpsr:0x%08x\n", regs->cpsr); } /** @@ -62,15 +62,15 @@ void rt_hw_trap_udef(struct rt_hw_register *regs) return; #endif - rt_hw_show_register(regs); + rt_hw_show_register(regs); - rt_kprintf("undefined instruction\n"); - rt_kprintf("thread %.*s stack:\n", RT_NAME_MAX, rt_current_thread->name); + rt_kprintf("undefined instruction\n"); + rt_kprintf("thread %.*s stack:\n", RT_NAME_MAX, rt_current_thread->name); #ifdef RT_USING_FINSH - list_thread(); + list_thread(); #endif - rt_hw_cpu_shutdown(); + rt_hw_cpu_shutdown(); } /** @@ -84,10 +84,10 @@ void rt_hw_trap_udef(struct rt_hw_register *regs) */ void rt_hw_trap_swi(struct rt_hw_register *regs) { - rt_hw_show_register(regs); + rt_hw_show_register(regs); - rt_kprintf("software interrupt\n"); - rt_hw_cpu_shutdown(); + rt_kprintf("software interrupt\n"); + rt_hw_cpu_shutdown(); } /** @@ -100,15 +100,15 @@ void rt_hw_trap_swi(struct rt_hw_register *regs) */ void rt_hw_trap_pabt(struct rt_hw_register *regs) { - rt_hw_show_register(regs); + rt_hw_show_register(regs); - rt_kprintf("prefetch abort\n"); - rt_kprintf("thread %.*s stack:\n", RT_NAME_MAX, rt_current_thread->name); + rt_kprintf("prefetch abort\n"); + rt_kprintf("thread %.*s stack:\n", RT_NAME_MAX, rt_current_thread->name); #ifdef RT_USING_FINSH - list_thread(); + list_thread(); #endif - rt_hw_cpu_shutdown(); + rt_hw_cpu_shutdown(); } /** @@ -124,29 +124,29 @@ void rt_hw_trap_dabt(struct rt_hw_register *regs) #ifdef RT_USING_GDB if (gdb_mem_fault_handler) { - regs->pc = (unsigned long)gdb_mem_fault_handler; + regs->pc = (unsigned long)gdb_mem_fault_handler; return; } #endif - rt_hw_show_register(regs); + rt_hw_show_register(regs); - rt_kprintf("data abort\n"); - rt_kprintf("thread %.*s stack:\n", RT_NAME_MAX, rt_current_thread->name); + rt_kprintf("data abort\n"); + rt_kprintf("thread %.*s stack:\n", RT_NAME_MAX, rt_current_thread->name); #ifdef RT_USING_FINSH - list_thread(); + list_thread(); #endif - rt_hw_cpu_shutdown(); + rt_hw_cpu_shutdown(); } void rt_hw_trap_irq() { void *param; - unsigned long ir; + unsigned long ir; rt_isr_handler_t isr_func; extern struct rt_irq_desc isr_table[]; - ir = rt_hw_interrupt_get_active(INT_IRQ); + ir = rt_hw_interrupt_get_active(INT_IRQ); if (ir == 127) { /* new IRQ generation */ @@ -169,18 +169,18 @@ void rt_hw_trap_irq() if (isr_func != RT_NULL) isr_func(ir, param); - /* new IRQ generation */ + /* new IRQ generation */ rt_hw_interrupt_ack(INT_IRQ); } void rt_hw_trap_fiq() { void *param; - unsigned long ir; + unsigned long ir; rt_isr_handler_t isr_func; extern struct rt_irq_desc isr_table[]; - ir = rt_hw_interrupt_get_active(INT_FIQ); + ir = rt_hw_interrupt_get_active(INT_FIQ); /* get interrupt service routine */ isr_func = isr_table[ir].handler; @@ -189,7 +189,7 @@ void rt_hw_trap_fiq() /* turn to interrupt service routine */ isr_func(ir, param); - /* new FIQ generation */ + /* new FIQ generation */ rt_hw_interrupt_ack(INT_FIQ); } diff --git a/libcpu/arm/arm926/cpuport.c b/libcpu/arm/arm926/cpuport.c index dc93f42ed6..9148afa401 100644 --- a/libcpu/arm/arm926/cpuport.c +++ b/libcpu/arm/arm926/cpuport.c @@ -1,5 +1,5 @@ /* - * Copyright (c) 2006-2018, RT-Thread Development Team + * Copyright (c) 2006-2021, RT-Thread Development Team * * SPDX-License-Identifier: Apache-2.0 * diff --git a/libcpu/arm/arm926/machine.c b/libcpu/arm/arm926/machine.c index aa26d10ec6..19baa4d9fe 100644 --- a/libcpu/arm/arm926/machine.c +++ b/libcpu/arm/arm926/machine.c @@ -1,5 +1,5 @@ /* - * Copyright (c) 2006-2018, RT-Thread Development Team + * Copyright (c) 2006-2021, RT-Thread Development Team * * SPDX-License-Identifier: Apache-2.0 * diff --git a/libcpu/arm/arm926/mmu.c b/libcpu/arm/arm926/mmu.c index 19d70b9b0b..50ada17f22 100644 --- a/libcpu/arm/arm926/mmu.c +++ b/libcpu/arm/arm926/mmu.c @@ -1,5 +1,5 @@ /* - * Copyright (c) 2006-2018, RT-Thread Development Team + * Copyright (c) 2006-2021, RT-Thread Development Team * * SPDX-License-Identifier: Apache-2.0 * diff --git a/libcpu/arm/arm926/mmu.h b/libcpu/arm/arm926/mmu.h index 36fdbeacd8..ecd39d4edf 100644 --- a/libcpu/arm/arm926/mmu.h +++ b/libcpu/arm/arm926/mmu.h @@ -1,5 +1,5 @@ /* - * Copyright (c) 2006-2018, RT-Thread Development Team + * Copyright (c) 2006-2021, RT-Thread Development Team * * SPDX-License-Identifier: Apache-2.0 * diff --git a/libcpu/arm/arm926/stack.c b/libcpu/arm/arm926/stack.c index f90bfa8c22..caf16c41bc 100644 --- a/libcpu/arm/arm926/stack.c +++ b/libcpu/arm/arm926/stack.c @@ -1,5 +1,5 @@ /* - * Copyright (c) 2006-2018, RT-Thread Development Team + * Copyright (c) 2006-2021, RT-Thread Development Team * * SPDX-License-Identifier: Apache-2.0 * diff --git a/libcpu/arm/arm926/trap.c b/libcpu/arm/arm926/trap.c index 9e7ba48037..c364b2addd 100644 --- a/libcpu/arm/arm926/trap.c +++ b/libcpu/arm/arm926/trap.c @@ -1,5 +1,5 @@ /* - * Copyright (c) 2006-2018, RT-Thread Development Team + * Copyright (c) 2006-2021, RT-Thread Development Team * * SPDX-License-Identifier: Apache-2.0 * diff --git a/libcpu/arm/armv6/armv6.h b/libcpu/arm/armv6/armv6.h index 659ce90721..522c35845f 100644 --- a/libcpu/arm/armv6/armv6.h +++ b/libcpu/arm/armv6/armv6.h @@ -1,12 +1,12 @@ /* - * Copyright (c) 2006-2018, RT-Thread Development Team + * Copyright (c) 2006-2021, RT-Thread Development Team * * SPDX-License-Identifier: Apache-2.0 * * Change Logs: * Date Author Notes */ - + #ifndef __ARMV6_H__ #define __ARMV6_H__ @@ -26,7 +26,7 @@ #ifndef __ASSEMBLY__ struct rt_hw_register { - rt_uint32_t cpsr; + rt_uint32_t cpsr; rt_uint32_t r0; rt_uint32_t r1; rt_uint32_t r2; @@ -46,24 +46,24 @@ struct rt_hw_register }; #if(0) struct rt_hw_register{ - rt_uint32_t r0; - rt_uint32_t r1; - rt_uint32_t r2; - rt_uint32_t r3; - rt_uint32_t r4; - rt_uint32_t r5; - rt_uint32_t r6; - rt_uint32_t r7; - rt_uint32_t r8; - rt_uint32_t r9; - rt_uint32_t r10; - rt_uint32_t fp; - rt_uint32_t ip; - rt_uint32_t sp; - rt_uint32_t lr; - rt_uint32_t pc; - rt_uint32_t cpsr; - rt_uint32_t ORIG_r0; + rt_uint32_t r0; + rt_uint32_t r1; + rt_uint32_t r2; + rt_uint32_t r3; + rt_uint32_t r4; + rt_uint32_t r5; + rt_uint32_t r6; + rt_uint32_t r7; + rt_uint32_t r8; + rt_uint32_t r9; + rt_uint32_t r10; + rt_uint32_t fp; + rt_uint32_t ip; + rt_uint32_t sp; + rt_uint32_t lr; + rt_uint32_t pc; + rt_uint32_t cpsr; + rt_uint32_t ORIG_r0; }; #endif #endif diff --git a/libcpu/arm/armv6/cpuport.c b/libcpu/arm/armv6/cpuport.c index f886e7e164..6e82539c6e 100644 --- a/libcpu/arm/armv6/cpuport.c +++ b/libcpu/arm/armv6/cpuport.c @@ -1,5 +1,5 @@ /* - * Copyright (c) 2006-2018, RT-Thread Development Team + * Copyright (c) 2006-2021, RT-Thread Development Team * * SPDX-License-Identifier: Apache-2.0 * @@ -11,8 +11,8 @@ #include <rthw.h> #include <rtthread.h> -#define ICACHE_MASK (rt_uint32_t)(1 << 12) -#define DCACHE_MASK (rt_uint32_t)(1 << 2) +#define ICACHE_MASK (rt_uint32_t)(1 << 12) +#define DCACHE_MASK (rt_uint32_t)(1 << 2) extern void machine_reset(void); extern void machine_shutdown(void); @@ -20,32 +20,32 @@ extern void machine_shutdown(void); #ifdef __GNUC__ rt_inline rt_uint32_t cp15_rd(void) { - rt_uint32_t i; + rt_uint32_t i; - asm ("mrc p15, 0, %0, c1, c0, 0":"=r" (i)); - return i; + asm ("mrc p15, 0, %0, c1, c0, 0":"=r" (i)); + return i; } rt_inline void cache_enable(rt_uint32_t bit) { - __asm__ __volatile__( \ - "mrc p15,0,r0,c1,c0,0\n\t" \ - "orr r0,r0,%0\n\t" \ - "mcr p15,0,r0,c1,c0,0" \ - : \ - :"r" (bit) \ - :"memory"); + __asm__ __volatile__( \ + "mrc p15,0,r0,c1,c0,0\n\t" \ + "orr r0,r0,%0\n\t" \ + "mcr p15,0,r0,c1,c0,0" \ + : \ + :"r" (bit) \ + :"memory"); } rt_inline void cache_disable(rt_uint32_t bit) { - __asm__ __volatile__( \ - "mrc p15,0,r0,c1,c0,0\n\t" \ - "bic r0,r0,%0\n\t" \ - "mcr p15,0,r0,c1,c0,0" \ - : \ - :"r" (bit) \ - :"memory"); + __asm__ __volatile__( \ + "mrc p15,0,r0,c1,c0,0\n\t" \ + "bic r0,r0,%0\n\t" \ + "mcr p15,0,r0,c1,c0,0" \ + : \ + :"r" (bit) \ + :"memory"); } @@ -54,38 +54,38 @@ rt_inline void cache_disable(rt_uint32_t bit) #ifdef __CC_ARM rt_inline rt_uint32_t cp15_rd(void) { - rt_uint32_t i; + rt_uint32_t i; - __asm - { - mrc p15, 0, i, c1, c0, 0 - } + __asm + { + mrc p15, 0, i, c1, c0, 0 + } - return i; + return i; } rt_inline void cache_enable(rt_uint32_t bit) { - rt_uint32_t value; + rt_uint32_t value; - __asm - { - mrc p15, 0, value, c1, c0, 0 - orr value, value, bit - mcr p15, 0, value, c1, c0, 0 - } + __asm + { + mrc p15, 0, value, c1, c0, 0 + orr value, value, bit + mcr p15, 0, value, c1, c0, 0 + } } rt_inline void cache_disable(rt_uint32_t bit) { - rt_uint32_t value; + rt_uint32_t value; - __asm - { - mrc p15, 0, value, c1, c0, 0 - bic value, value, bit - mcr p15, 0, value, c1, c0, 0 - } + __asm + { + mrc p15, 0, value, c1, c0, 0 + bic value, value, bit + mcr p15, 0, value, c1, c0, 0 + } } #endif @@ -95,7 +95,7 @@ rt_inline void cache_disable(rt_uint32_t bit) */ void rt_hw_cpu_icache_enable() { - cache_enable(ICACHE_MASK); + cache_enable(ICACHE_MASK); } /** @@ -104,7 +104,7 @@ void rt_hw_cpu_icache_enable() */ void rt_hw_cpu_icache_disable() { - cache_disable(ICACHE_MASK); + cache_disable(ICACHE_MASK); } /** @@ -113,7 +113,7 @@ void rt_hw_cpu_icache_disable() */ rt_base_t rt_hw_cpu_icache_status() { - return (cp15_rd() & ICACHE_MASK); + return (cp15_rd() & ICACHE_MASK); } /** @@ -122,7 +122,7 @@ rt_base_t rt_hw_cpu_icache_status() */ void rt_hw_cpu_dcache_enable() { - cache_enable(DCACHE_MASK); + cache_enable(DCACHE_MASK); } /** @@ -131,7 +131,7 @@ void rt_hw_cpu_dcache_enable() */ void rt_hw_cpu_dcache_disable() { - cache_disable(DCACHE_MASK); + cache_disable(DCACHE_MASK); } /** @@ -140,7 +140,7 @@ void rt_hw_cpu_dcache_disable() */ rt_base_t rt_hw_cpu_dcache_status() { - return (cp15_rd() & DCACHE_MASK); + return (cp15_rd() & DCACHE_MASK); } /** @@ -149,13 +149,13 @@ rt_base_t rt_hw_cpu_dcache_status() */ RT_WEAK void rt_hw_cpu_reset() { - - rt_kprintf("Restarting system...\n"); - machine_reset(); - while(1); /* loop forever and wait for reset to happen */ + rt_kprintf("Restarting system...\n"); + machine_reset(); - /* NEVER REACHED */ + while(1); /* loop forever and wait for reset to happen */ + + /* NEVER REACHED */ } /** @@ -164,67 +164,67 @@ RT_WEAK void rt_hw_cpu_reset() */ RT_WEAK void rt_hw_cpu_shutdown() { - rt_uint32_t level; - rt_kprintf("shutdown...\n"); + rt_uint32_t level; + rt_kprintf("shutdown...\n"); - level = rt_hw_interrupt_disable(); - machine_shutdown(); - while (level) - { - RT_ASSERT(0); - } + level = rt_hw_interrupt_disable(); + machine_shutdown(); + while (level) + { + RT_ASSERT(0); + } } #ifdef RT_USING_CPU_FFS /** - * This function finds the first bit set (beginning with the least significant bit) + * This function finds the first bit set (beginning with the least significant bit) * in value and return the index of that bit. * - * Bits are numbered starting at 1 (the least significant bit). A return value of + * Bits are numbered starting at 1 (the least significant bit). A return value of * zero from any of these functions means that the argument was zero. - * - * @return return the index of the first bit set. If value is 0, then this function + * + * @return return the index of the first bit set. If value is 0, then this function * shall return 0. */ #if defined(__CC_ARM) int __rt_ffs(int value) { - register rt_uint32_t x; + register rt_uint32_t x; + + if (value == 0) + return value; - if (value == 0) - return value; - - __asm - { - rsb x, value, #0 - and x, x, value - clz x, x - rsb x, x, #32 - } + __asm + { + rsb x, value, #0 + and x, x, value + clz x, x + rsb x, x, #32 + } - return x; + return x; } #elif defined(__IAR_SYSTEMS_ICC__) int __rt_ffs(int value) { - if (value == 0) - return value; + if (value == 0) + return value; - __ASM("RSB r4, r0, #0"); - __ASM("AND r4, r4, r0"); - __ASM("CLZ r4, r4"); - __ASM("RSB r0, r4, #32"); + __ASM("RSB r4, r0, #0"); + __ASM("AND r4, r4, r0"); + __ASM("CLZ r4, r4"); + __ASM("RSB r0, r4, #32"); } #elif defined(__GNUC__) int __rt_ffs(int value) { - if (value == 0) - return value; + if (value == 0) + return value; - value &= (-value); - asm ("clz %0, %1": "=r"(value) :"r"(value)); + value &= (-value); + asm ("clz %0, %1": "=r"(value) :"r"(value)); - return (32 - value); + return (32 - value); } #endif diff --git a/libcpu/arm/armv6/mmu.c b/libcpu/arm/armv6/mmu.c index ae3cf73559..deb2f8365f 100644 --- a/libcpu/arm/armv6/mmu.c +++ b/libcpu/arm/armv6/mmu.c @@ -1,5 +1,5 @@ /* - * Copyright (c) 2006-2018, RT-Thread Development Team + * Copyright (c) 2006-2021, RT-Thread Development Team * * SPDX-License-Identifier: Apache-2.0 * @@ -12,411 +12,411 @@ #ifdef __CC_ARM void mmu_setttbase(rt_uint32_t i) { - register rt_uint32_t value; + register rt_uint32_t value; - /* Invalidates all TLBs.Domain access is selected as - * client by configuring domain access register, - * in that case access controlled by permission value - * set by page table entry - */ - value = 0; - __asm volatile - { - mcr p15, 0, value, c8, c7, 0 - } + /* Invalidates all TLBs.Domain access is selected as + * client by configuring domain access register, + * in that case access controlled by permission value + * set by page table entry + */ + value = 0; + __asm volatile + { + mcr p15, 0, value, c8, c7, 0 + } - value = 0x55555555; - __asm volatile - { - mcr p15, 0, value, c3, c0, 0 - mcr p15, 0, i, c2, c0, 0 - } + value = 0x55555555; + __asm volatile + { + mcr p15, 0, value, c3, c0, 0 + mcr p15, 0, i, c2, c0, 0 + } } void mmu_set_domain(rt_uint32_t i) { - __asm volatile - { - mcr p15,0, i, c3, c0, 0 - } + __asm volatile + { + mcr p15,0, i, c3, c0, 0 + } } void mmu_enable() { - register rt_uint32_t value; + register rt_uint32_t value; - __asm volatile - { - mrc p15, 0, value, c1, c0, 0 - orr value, value, #0x01 - mcr p15, 0, value, c1, c0, 0 - } + __asm volatile + { + mrc p15, 0, value, c1, c0, 0 + orr value, value, #0x01 + mcr p15, 0, value, c1, c0, 0 + } } void mmu_disable() { - register rt_uint32_t value; + register rt_uint32_t value; - __asm volatile - { - mrc p15, 0, value, c1, c0, 0 - bic value, value, #0x01 - mcr p15, 0, value, c1, c0, 0 - } + __asm volatile + { + mrc p15, 0, value, c1, c0, 0 + bic value, value, #0x01 + mcr p15, 0, value, c1, c0, 0 + } } void mmu_enable_icache() { - register rt_uint32_t value; + register rt_uint32_t value; - __asm volatile - { - mrc p15, 0, value, c1, c0, 0 - orr value, value, #0x1000 - mcr p15, 0, value, c1, c0, 0 - } + __asm volatile + { + mrc p15, 0, value, c1, c0, 0 + orr value, value, #0x1000 + mcr p15, 0, value, c1, c0, 0 + } } void mmu_enable_dcache() { - register rt_uint32_t value; + register rt_uint32_t value; - __asm volatile - { - mrc p15, 0, value, c1, c0, 0 - orr value, value, #0x04 - mcr p15, 0, value, c1, c0, 0 - } + __asm volatile + { + mrc p15, 0, value, c1, c0, 0 + orr value, value, #0x04 + mcr p15, 0, value, c1, c0, 0 + } } void mmu_disable_icache() { - register rt_uint32_t value; + register rt_uint32_t value; - __asm volatile - { - mrc p15, 0, value, c1, c0, 0 - bic value, value, #0x1000 - mcr p15, 0, value, c1, c0, 0 - } + __asm volatile + { + mrc p15, 0, value, c1, c0, 0 + bic value, value, #0x1000 + mcr p15, 0, value, c1, c0, 0 + } } void mmu_disable_dcache() { - register rt_uint32_t value; + register rt_uint32_t value; - __asm volatile - { - mrc p15, 0, value, c1, c0, 0 - bic value, value, #0x04 - mcr p15, 0, value, c1, c0, 0 - } + __asm volatile + { + mrc p15, 0, value, c1, c0, 0 + bic value, value, #0x04 + mcr p15, 0, value, c1, c0, 0 + } } void mmu_enable_alignfault() { - register rt_uint32_t value; + register rt_uint32_t value; - __asm volatile - { - mrc p15, 0, value, c1, c0, 0 - orr value, value, #0x02 - mcr p15, 0, value, c1, c0, 0 - } + __asm volatile + { + mrc p15, 0, value, c1, c0, 0 + orr value, value, #0x02 + mcr p15, 0, value, c1, c0, 0 + } } void mmu_disable_alignfault() { - register rt_uint32_t value; + register rt_uint32_t value; - __asm volatile - { - mrc p15, 0, value, c1, c0, 0 - bic value, value, #0x02 - mcr p15, 0, value, c1, c0, 0 - } + __asm volatile + { + mrc p15, 0, value, c1, c0, 0 + bic value, value, #0x02 + mcr p15, 0, value, c1, c0, 0 + } } void mmu_clean_invalidated_cache_index(int index) { - __asm volatile - { - mcr p15, 0, index, c7, c14, 2 - } + __asm volatile + { + mcr p15, 0, index, c7, c14, 2 + } } void mmu_clean_invalidated_dcache(rt_uint32_t buffer, rt_uint32_t size) { - unsigned int ptr; + unsigned int ptr; - ptr = buffer & ~(CACHE_LINE_SIZE - 1); + ptr = buffer & ~(CACHE_LINE_SIZE - 1); - while(ptr < buffer + size) - { - __asm volatile - { - MCR p15, 0, ptr, c7, c14, 1 - } - ptr += CACHE_LINE_SIZE; - } + while(ptr < buffer + size) + { + __asm volatile + { + MCR p15, 0, ptr, c7, c14, 1 + } + ptr += CACHE_LINE_SIZE; + } } void mmu_clean_dcache(rt_uint32_t buffer, rt_uint32_t size) { - unsigned int ptr; + unsigned int ptr; - ptr = buffer & ~(CACHE_LINE_SIZE - 1); + ptr = buffer & ~(CACHE_LINE_SIZE - 1); - while (ptr < buffer + size) - { - __asm volatile - { - MCR p15, 0, ptr, c7, c10, 1 - } - ptr += CACHE_LINE_SIZE; - } + while (ptr < buffer + size) + { + __asm volatile + { + MCR p15, 0, ptr, c7, c10, 1 + } + ptr += CACHE_LINE_SIZE; + } } void mmu_invalidate_dcache(rt_uint32_t buffer, rt_uint32_t size) { - unsigned int ptr; + unsigned int ptr; - ptr = buffer & ~(CACHE_LINE_SIZE - 1); + ptr = buffer & ~(CACHE_LINE_SIZE - 1); - while (ptr < buffer + size) - { - __asm volatile - { - MCR p15, 0, ptr, c7, c6, 1 - } - ptr += CACHE_LINE_SIZE; - } + while (ptr < buffer + size) + { + __asm volatile + { + MCR p15, 0, ptr, c7, c6, 1 + } + ptr += CACHE_LINE_SIZE; + } } void mmu_invalidate_tlb() { - register rt_uint32_t value; + register rt_uint32_t value; - value = 0; - __asm volatile - { - mcr p15, 0, value, c8, c7, 0 - } + value = 0; + __asm volatile + { + mcr p15, 0, value, c8, c7, 0 + } } void mmu_invalidate_icache() { - register rt_uint32_t value; + register rt_uint32_t value; - value = 0; + value = 0; - __asm volatile - { - mcr p15, 0, value, c7, c5, 0 - } + __asm volatile + { + mcr p15, 0, value, c7, c5, 0 + } } void mmu_invalidate_dcache_all() { - register rt_uint32_t value; + register rt_uint32_t value; - value = 0; + value = 0; - __asm volatile - { - mcr p15, 0, value, c7, c6, 0 - } + __asm volatile + { + mcr p15, 0, value, c7, c6, 0 + } } #elif defined(__GNUC__) void mmu_setttbase(register rt_uint32_t i) { - register rt_uint32_t value; + register rt_uint32_t value; - /* Invalidates all TLBs.Domain access is selected as - * client by configuring domain access register, - * in that case access controlled by permission value - * set by page table entry - */ - value = 0; - asm volatile ("mcr p15, 0, %0, c8, c7, 0"::"r"(value)); + /* Invalidates all TLBs.Domain access is selected as + * client by configuring domain access register, + * in that case access controlled by permission value + * set by page table entry + */ + value = 0; + asm volatile ("mcr p15, 0, %0, c8, c7, 0"::"r"(value)); - value = 0x55555555; - asm volatile ("mcr p15, 0, %0, c3, c0, 0"::"r"(value)); - asm volatile ("mcr p15, 0, %0, c2, c0, 0"::"r"(i)); + value = 0x55555555; + asm volatile ("mcr p15, 0, %0, c3, c0, 0"::"r"(value)); + asm volatile ("mcr p15, 0, %0, c2, c0, 0"::"r"(i)); } void mmu_set_domain(register rt_uint32_t i) { - asm volatile ("mcr p15,0, %0, c3, c0, 0": :"r" (i)); + asm volatile ("mcr p15,0, %0, c3, c0, 0": :"r" (i)); } void mmu_enable() { - register rt_uint32_t i; + register rt_uint32_t i; - /* read control register */ - asm volatile ("mrc p15, 0, %0, c1, c0, 0":"=r" (i)); + /* read control register */ + asm volatile ("mrc p15, 0, %0, c1, c0, 0":"=r" (i)); - i |= 0x1; - /* Enables the extended page tables to be configured for - the hardware page translation mechanism, Subpage AP bits disabled */ - i |= (1 << 23); /* support for ARMv6 MMU features */ - i |= (1 << 13); /* High exception vectors selected, address range = 0xFFFF0000-0xFFFF001C */ + i |= 0x1; + /* Enables the extended page tables to be configured for + the hardware page translation mechanism, Subpage AP bits disabled */ + i |= (1 << 23); /* support for ARMv6 MMU features */ + i |= (1 << 13); /* High exception vectors selected, address range = 0xFFFF0000-0xFFFF001C */ - /* write back to control register */ - asm volatile ("mcr p15, 0, %0, c1, c0, 0": :"r" (i)); + /* write back to control register */ + asm volatile ("mcr p15, 0, %0, c1, c0, 0": :"r" (i)); } void mmu_disable() { - register rt_uint32_t i; + register rt_uint32_t i; - /* read control register */ - asm volatile ("mrc p15, 0, %0, c1, c0, 0":"=r" (i)); + /* read control register */ + asm volatile ("mrc p15, 0, %0, c1, c0, 0":"=r" (i)); - i &= ~0x1; + i &= ~0x1; - /* write back to control register */ - asm volatile ("mcr p15, 0, %0, c1, c0, 0": :"r" (i)); + /* write back to control register */ + asm volatile ("mcr p15, 0, %0, c1, c0, 0": :"r" (i)); } void mmu_enable_icache() { - register rt_uint32_t i; + register rt_uint32_t i; - /* read control register */ - asm volatile ("mrc p15, 0, %0, c1, c0, 0":"=r" (i)); + /* read control register */ + asm volatile ("mrc p15, 0, %0, c1, c0, 0":"=r" (i)); - i |= (1 << 12); + i |= (1 << 12); - /* write back to control register */ - asm volatile ("mcr p15, 0, %0, c1, c0, 0": :"r" (i)); + /* write back to control register */ + asm volatile ("mcr p15, 0, %0, c1, c0, 0": :"r" (i)); } void mmu_enable_dcache() { - register rt_uint32_t i; + register rt_uint32_t i; - /* read control register */ - asm volatile ("mrc p15, 0, %0, c1, c0, 0":"=r" (i)); + /* read control register */ + asm volatile ("mrc p15, 0, %0, c1, c0, 0":"=r" (i)); - i |= (1 << 2); + i |= (1 << 2); - /* write back to control register */ - asm volatile ("mcr p15, 0, %0, c1, c0, 0": :"r" (i)); + /* write back to control register */ + asm volatile ("mcr p15, 0, %0, c1, c0, 0": :"r" (i)); } void mmu_disable_icache() { - register rt_uint32_t i; + register rt_uint32_t i; - /* read control register */ - asm volatile ("mrc p15, 0, %0, c1, c0, 0":"=r" (i)); + /* read control register */ + asm volatile ("mrc p15, 0, %0, c1, c0, 0":"=r" (i)); - i &= ~(1 << 12); + i &= ~(1 << 12); - /* write back to control register */ - asm volatile ("mcr p15, 0, %0, c1, c0, 0": :"r" (i)); + /* write back to control register */ + asm volatile ("mcr p15, 0, %0, c1, c0, 0": :"r" (i)); } void mmu_disable_dcache() { - register rt_uint32_t i; + register rt_uint32_t i; - /* read control register */ - asm volatile ("mrc p15, 0, %0, c1, c0, 0":"=r" (i)); + /* read control register */ + asm volatile ("mrc p15, 0, %0, c1, c0, 0":"=r" (i)); - i &= ~(1 << 2); + i &= ~(1 << 2); - /* write back to control register */ - asm volatile ("mcr p15, 0, %0, c1, c0, 0": :"r" (i)); + /* write back to control register */ + asm volatile ("mcr p15, 0, %0, c1, c0, 0": :"r" (i)); } void mmu_enable_alignfault() { - register rt_uint32_t i; + register rt_uint32_t i; - /* read control register */ - asm volatile ("mrc p15, 0, %0, c1, c0, 0":"=r" (i)); + /* read control register */ + asm volatile ("mrc p15, 0, %0, c1, c0, 0":"=r" (i)); - i |= (1 << 1); + i |= (1 << 1); - /* write back to control register */ - asm volatile ("mcr p15, 0, %0, c1, c0, 0": :"r" (i)); + /* write back to control register */ + asm volatile ("mcr p15, 0, %0, c1, c0, 0": :"r" (i)); } void mmu_disable_alignfault() { - register rt_uint32_t i; + register rt_uint32_t i; - /* read control register */ - asm volatile ("mrc p15, 0, %0, c1, c0, 0":"=r" (i)); + /* read control register */ + asm volatile ("mrc p15, 0, %0, c1, c0, 0":"=r" (i)); - i &= ~(1 << 1); + i &= ~(1 << 1); - /* write back to control register */ - asm volatile ("mcr p15, 0, %0, c1, c0, 0": :"r" (i)); + /* write back to control register */ + asm volatile ("mcr p15, 0, %0, c1, c0, 0": :"r" (i)); } void mmu_clean_invalidated_cache_index(int index) { - asm volatile ("mcr p15, 0, %0, c7, c14, 2": :"r" (index)); + asm volatile ("mcr p15, 0, %0, c7, c14, 2": :"r" (index)); } void mmu_clean_invalidated_dcache(rt_uint32_t buffer, rt_uint32_t size) { - unsigned int ptr; + unsigned int ptr; - ptr = buffer & ~(CACHE_LINE_SIZE - 1); + ptr = buffer & ~(CACHE_LINE_SIZE - 1); - while(ptr < buffer + size) - { - asm volatile ("mcr p15, 0, %0, c7, c14, 1": :"r" (ptr)); - ptr += CACHE_LINE_SIZE; - } + while(ptr < buffer + size) + { + asm volatile ("mcr p15, 0, %0, c7, c14, 1": :"r" (ptr)); + ptr += CACHE_LINE_SIZE; + } } void mmu_clean_dcache(rt_uint32_t buffer, rt_uint32_t size) { - unsigned int ptr; + unsigned int ptr; - ptr = buffer & ~(CACHE_LINE_SIZE - 1); + ptr = buffer & ~(CACHE_LINE_SIZE - 1); - while (ptr < buffer + size) - { - asm volatile ("mcr p15, 0, %0, c7, c10, 1": :"r" (ptr)); - ptr += CACHE_LINE_SIZE; - } + while (ptr < buffer + size) + { + asm volatile ("mcr p15, 0, %0, c7, c10, 1": :"r" (ptr)); + ptr += CACHE_LINE_SIZE; + } } void mmu_invalidate_dcache(rt_uint32_t buffer, rt_uint32_t size) { - unsigned int ptr; + unsigned int ptr; - ptr = buffer & ~(CACHE_LINE_SIZE - 1); + ptr = buffer & ~(CACHE_LINE_SIZE - 1); - while (ptr < buffer + size) - { - asm volatile ("mcr p15, 0, %0, c7, c6, 1": :"r" (ptr)); - ptr += CACHE_LINE_SIZE; - } + while (ptr < buffer + size) + { + asm volatile ("mcr p15, 0, %0, c7, c6, 1": :"r" (ptr)); + ptr += CACHE_LINE_SIZE; + } } void mmu_invalidate_tlb() { - asm volatile ("mcr p15, 0, %0, c8, c7, 0": :"r" (0)); + asm volatile ("mcr p15, 0, %0, c8, c7, 0": :"r" (0)); } void mmu_invalidate_icache() { - asm volatile ("mcr p15, 0, %0, c7, c5, 0": :"r" (0)); + asm volatile ("mcr p15, 0, %0, c7, c5, 0": :"r" (0)); } void mmu_invalidate_dcache_all() { - asm volatile ("mcr p15, 0, %0, c7, c6, 0": :"r" (0)); + asm volatile ("mcr p15, 0, %0, c7, c6, 0": :"r" (0)); } #endif @@ -426,123 +426,123 @@ static volatile unsigned int _pgd_table[4*1024] ALIGN(16*1024); * level2 page table * RT_MMU_PTE_SIZE must be 1024*n */ -#define RT_MMU_PTE_SIZE 4096 +#define RT_MMU_PTE_SIZE 4096 static volatile unsigned int _pte_table[RT_MMU_PTE_SIZE] ALIGN(1*1024); void mmu_create_pgd(struct mem_desc *mdesc) { - volatile rt_uint32_t *pTT; - volatile int i, nSec; - pTT = (rt_uint32_t *)_pgd_table + (mdesc->vaddr_start >> 20); - nSec = (mdesc->vaddr_end >> 20) - (mdesc->vaddr_start >> 20); - for(i = 0; i <= nSec; i++) - { - *pTT = mdesc->sect_attr | (((mdesc->paddr_start >> 20) + i) << 20); - pTT++; - } + volatile rt_uint32_t *pTT; + volatile int i, nSec; + pTT = (rt_uint32_t *)_pgd_table + (mdesc->vaddr_start >> 20); + nSec = (mdesc->vaddr_end >> 20) - (mdesc->vaddr_start >> 20); + for(i = 0; i <= nSec; i++) + { + *pTT = mdesc->sect_attr | (((mdesc->paddr_start >> 20) + i) << 20); + pTT++; + } } void mmu_create_pte(struct mem_desc *mdesc) { - volatile rt_uint32_t *pTT; - volatile rt_uint32_t *p_pteentry; - int i; - rt_uint32_t vaddr; - rt_uint32_t total_page = 0; - rt_uint32_t pte_offset = 0; - rt_uint32_t sect_attr = 0; + volatile rt_uint32_t *pTT; + volatile rt_uint32_t *p_pteentry; + int i; + rt_uint32_t vaddr; + rt_uint32_t total_page = 0; + rt_uint32_t pte_offset = 0; + rt_uint32_t sect_attr = 0; - total_page = (mdesc->vaddr_end >> 12) - (mdesc->vaddr_start >> 12) + 1; - pte_offset = mdesc->sect_attr & 0xfffffc00; - sect_attr = mdesc->sect_attr & 0x3ff; - vaddr = mdesc->vaddr_start; + total_page = (mdesc->vaddr_end >> 12) - (mdesc->vaddr_start >> 12) + 1; + pte_offset = mdesc->sect_attr & 0xfffffc00; + sect_attr = mdesc->sect_attr & 0x3ff; + vaddr = mdesc->vaddr_start; - for(i = 0; i < total_page; i++) - { - pTT = (rt_uint32_t *)_pgd_table + (vaddr >> 20); - if (*pTT == 0) /* Level 1 page table item not used, now update pgd item */ - { - *pTT = pte_offset | sect_attr; - p_pteentry = (rt_uint32_t *)pte_offset + - ((vaddr & 0x000ff000) >> 12); - pte_offset += 1024; - } - else /* using old Level 1 page table item */ - { - p_pteentry = (rt_uint32_t *)(*pTT & 0xfffffc00) + - ((vaddr & 0x000ff000) >> 12); - } + for(i = 0; i < total_page; i++) + { + pTT = (rt_uint32_t *)_pgd_table + (vaddr >> 20); + if (*pTT == 0) /* Level 1 page table item not used, now update pgd item */ + { + *pTT = pte_offset | sect_attr; + p_pteentry = (rt_uint32_t *)pte_offset + + ((vaddr & 0x000ff000) >> 12); + pte_offset += 1024; + } + else /* using old Level 1 page table item */ + { + p_pteentry = (rt_uint32_t *)(*pTT & 0xfffffc00) + + ((vaddr & 0x000ff000) >> 12); + } - *p_pteentry = mdesc->page_attr | (((mdesc->paddr_start >> 12) + i) << 12); - vaddr += 0x1000; - } + *p_pteentry = mdesc->page_attr | (((mdesc->paddr_start >> 12) + i) << 12); + vaddr += 0x1000; + } } static void build_pte_mem_desc(struct mem_desc *mdesc, rt_uint32_t size) { - rt_uint32_t pte_offset = 0; - rt_uint32_t nsec = 0; - /* set page table */ - for (; size > 0; size--) - { - if (mdesc->mapped_mode == PAGE_MAPPED) - { - nsec = (RT_ALIGN(mdesc->vaddr_end, 0x100000) - RT_ALIGN_DOWN(mdesc->vaddr_start, 0x100000)) >> 20; - mdesc->sect_attr |= (((rt_uint32_t)_pte_table)& 0xfffffc00) + pte_offset; - pte_offset += nsec << 10; - } - if (pte_offset >= RT_MMU_PTE_SIZE) - { - rt_kprintf("PTE table size too little\n"); - RT_ASSERT(0); - } + rt_uint32_t pte_offset = 0; + rt_uint32_t nsec = 0; + /* set page table */ + for (; size > 0; size--) + { + if (mdesc->mapped_mode == PAGE_MAPPED) + { + nsec = (RT_ALIGN(mdesc->vaddr_end, 0x100000) - RT_ALIGN_DOWN(mdesc->vaddr_start, 0x100000)) >> 20; + mdesc->sect_attr |= (((rt_uint32_t)_pte_table)& 0xfffffc00) + pte_offset; + pte_offset += nsec << 10; + } + if (pte_offset >= RT_MMU_PTE_SIZE) + { + rt_kprintf("PTE table size too little\n"); + RT_ASSERT(0); + } - mdesc++; - } + mdesc++; + } } void rt_hw_mmu_init(struct mem_desc *mdesc, rt_uint32_t size) { - /* disable I/D cache */ - mmu_disable_dcache(); - mmu_disable_icache(); - mmu_disable(); - mmu_invalidate_tlb(); + /* disable I/D cache */ + mmu_disable_dcache(); + mmu_disable_icache(); + mmu_disable(); + mmu_invalidate_tlb(); - /* clear pgd and pte table */ - rt_memset((void *)_pgd_table, 0, 16*1024); - rt_memset((void *)_pte_table, 0, RT_MMU_PTE_SIZE); - build_pte_mem_desc(mdesc, size); - /* set page table */ - for (; size > 0; size--) - { - if (mdesc->mapped_mode == SECT_MAPPED) - { - mmu_create_pgd(mdesc); - } - else - { - mmu_create_pte(mdesc); - } + /* clear pgd and pte table */ + rt_memset((void *)_pgd_table, 0, 16*1024); + rt_memset((void *)_pte_table, 0, RT_MMU_PTE_SIZE); + build_pte_mem_desc(mdesc, size); + /* set page table */ + for (; size > 0; size--) + { + if (mdesc->mapped_mode == SECT_MAPPED) + { + mmu_create_pgd(mdesc); + } + else + { + mmu_create_pte(mdesc); + } - mdesc++; - } + mdesc++; + } - /* set MMU table address */ - mmu_setttbase((rt_uint32_t)_pgd_table); + /* set MMU table address */ + mmu_setttbase((rt_uint32_t)_pgd_table); - /* enables MMU */ - mmu_enable(); + /* enables MMU */ + mmu_enable(); - /* enable Instruction Cache */ - mmu_enable_icache(); + /* enable Instruction Cache */ + mmu_enable_icache(); - /* enable Data Cache */ - mmu_enable_dcache(); + /* enable Data Cache */ + mmu_enable_dcache(); - mmu_invalidate_icache(); - mmu_invalidate_dcache_all(); + mmu_invalidate_icache(); + mmu_invalidate_dcache_all(); } diff --git a/libcpu/arm/armv6/mmu.h b/libcpu/arm/armv6/mmu.h index 4df61ac21d..18355378bd 100644 --- a/libcpu/arm/armv6/mmu.h +++ b/libcpu/arm/armv6/mmu.h @@ -1,5 +1,5 @@ /* - * Copyright (c) 2006-2018, RT-Thread Development Team + * Copyright (c) 2006-2021, RT-Thread Development Team * * SPDX-License-Identifier: Apache-2.0 * @@ -12,7 +12,7 @@ #include <rtthread.h> -#define CACHE_LINE_SIZE 32 +#define CACHE_LINE_SIZE 32 /* * Hardware page table definitions. @@ -30,7 +30,7 @@ /* * - section */ -#define PGD_SECT_BUFFERABLE (1 << 2) +#define PGD_SECT_BUFFERABLE (1 << 2) #define PGD_SECT_CACHEABLE (1 << 3) #define PGD_SECT_XN (1 << 4) /* ARMv6 */ #define PGD_SECT_AP0 (1 << 10) @@ -155,35 +155,35 @@ #define PAGE_RONX_FAULT (PAGE_AP_RO|PTE_TYPE_SMALL|PTE_EXT_XN) /* Read Only without cache and write buffer */ -#define DESC_SEC (0x2|(1<<4)) -#define CB (3<<2) //cache_on, write_back -#define CNB (2<<2) //cache_on, write_through -#define NCB (1<<2) //cache_off,WR_BUF on -#define NCNB (0<<2) //cache_off,WR_BUF off -#define AP_RW (3<<10) //supervisor=RW, user=RW -#define AP_RO (2<<10) //supervisor=RW, user=RO +#define DESC_SEC (0x2|(1<<4)) +#define CB (3<<2) //cache_on, write_back +#define CNB (2<<2) //cache_on, write_through +#define NCB (1<<2) //cache_off,WR_BUF on +#define NCNB (0<<2) //cache_off,WR_BUF off +#define AP_RW (3<<10) //supervisor=RW, user=RW +#define AP_RO (2<<10) //supervisor=RW, user=RO -#define DOMAIN_FAULT (0x0) -#define DOMAIN_CHK (0x1) -#define DOMAIN_NOTCHK (0x3) -#define DOMAIN0 (0x0<<5) -#define DOMAIN1 (0x1<<5) +#define DOMAIN_FAULT (0x0) +#define DOMAIN_CHK (0x1) +#define DOMAIN_NOTCHK (0x3) +#define DOMAIN0 (0x0<<5) +#define DOMAIN1 (0x1<<5) -#define DOMAIN0_ATTR (DOMAIN_CHK<<0) -#define DOMAIN1_ATTR (DOMAIN_FAULT<<2) +#define DOMAIN0_ATTR (DOMAIN_CHK<<0) +#define DOMAIN1_ATTR (DOMAIN_FAULT<<2) -#define RW_CB (AP_RW|DOMAIN0|CB|DESC_SEC) /* Read/Write, cache, write back */ -#define RW_CNB (AP_RW|DOMAIN0|CNB|DESC_SEC) /* Read/Write, cache, write through */ -#define RW_NCNB (AP_RW|DOMAIN0|NCNB|DESC_SEC) /* Read/Write without cache and write buffer */ -#define RW_FAULT (AP_RW|DOMAIN1|NCNB|DESC_SEC) /* Read/Write without cache and write buffer */ +#define RW_CB (AP_RW|DOMAIN0|CB|DESC_SEC) /* Read/Write, cache, write back */ +#define RW_CNB (AP_RW|DOMAIN0|CNB|DESC_SEC) /* Read/Write, cache, write through */ +#define RW_NCNB (AP_RW|DOMAIN0|NCNB|DESC_SEC) /* Read/Write without cache and write buffer */ +#define RW_FAULT (AP_RW|DOMAIN1|NCNB|DESC_SEC) /* Read/Write without cache and write buffer */ struct mem_desc { - rt_uint32_t vaddr_start; - rt_uint32_t vaddr_end; - rt_uint32_t paddr_start; - rt_uint32_t sect_attr; /* when page mapped */ - rt_uint32_t page_attr; /* only sector mapped valid */ - rt_uint32_t mapped_mode; + rt_uint32_t vaddr_start; + rt_uint32_t vaddr_end; + rt_uint32_t paddr_start; + rt_uint32_t sect_attr; /* when page mapped */ + rt_uint32_t page_attr; /* only sector mapped valid */ + rt_uint32_t mapped_mode; #define SECT_MAPPED 0 #define PAGE_MAPPED 1 }; diff --git a/libcpu/arm/armv6/stack.c b/libcpu/arm/armv6/stack.c index 52de999fc2..33a8d96d48 100644 --- a/libcpu/arm/armv6/stack.c +++ b/libcpu/arm/armv6/stack.c @@ -1,5 +1,5 @@ /* - * Copyright (c) 2006-2018, RT-Thread Development Team + * Copyright (c) 2006-2021, RT-Thread Development Team * * SPDX-License-Identifier: Apache-2.0 * diff --git a/libcpu/arm/armv6/vfp.c b/libcpu/arm/armv6/vfp.c index 9aa8d34fcc..fc07f5a309 100644 --- a/libcpu/arm/armv6/vfp.c +++ b/libcpu/arm/armv6/vfp.c @@ -1,5 +1,5 @@ /* - * Copyright (c) 2006-2018, RT-Thread Development Team + * Copyright (c) 2006-2021, RT-Thread Development Team * * SPDX-License-Identifier: Apache-2.0 * diff --git a/libcpu/arm/armv6/vfp.h b/libcpu/arm/armv6/vfp.h index c347dbe0a6..fd084f3aef 100644 --- a/libcpu/arm/armv6/vfp.h +++ b/libcpu/arm/armv6/vfp.h @@ -1,5 +1,5 @@ /* - * Copyright (c) 2006-2018, RT-Thread Development Team + * Copyright (c) 2006-2021, RT-Thread Development Team * * SPDX-License-Identifier: Apache-2.0 * @@ -87,7 +87,7 @@ }) #define vmsr(vfp, var) \ - asm("vmsr "#vfp", %0" \ + asm("vmsr "#vfp", %0" \ : : "r" (var) : "cc") diff --git a/libcpu/arm/common/backtrace.c b/libcpu/arm/common/backtrace.c index 4fc87b20d1..388a409d88 100644 --- a/libcpu/arm/common/backtrace.c +++ b/libcpu/arm/common/backtrace.c @@ -1,5 +1,5 @@ /* - * Copyright (c) 2006-2018, RT-Thread Development Team + * Copyright (c) 2006-2021, RT-Thread Development Team * * SPDX-License-Identifier: Apache-2.0 * diff --git a/libcpu/arm/common/div0.c b/libcpu/arm/common/div0.c index 0cb3e09b54..113778b43f 100644 --- a/libcpu/arm/common/div0.c +++ b/libcpu/arm/common/div0.c @@ -1,5 +1,5 @@ /* - * Copyright (c) 2006-2018, RT-Thread Development Team + * Copyright (c) 2006-2021, RT-Thread Development Team * * SPDX-License-Identifier: Apache-2.0 * @@ -8,5 +8,5 @@ */ void __div0 (void) { - while (1) ; + while (1) ; } diff --git a/libcpu/arm/common/showmem.c b/libcpu/arm/common/showmem.c index b770e4ce17..1a94ff1d9f 100644 --- a/libcpu/arm/common/showmem.c +++ b/libcpu/arm/common/showmem.c @@ -1,5 +1,5 @@ /* - * Copyright (c) 2006-2018, RT-Thread Development Team + * Copyright (c) 2006-2021, RT-Thread Development Team * * SPDX-License-Identifier: Apache-2.0 * @@ -12,27 +12,27 @@ void rt_hw_show_memory(rt_uint32_t addr, rt_uint32_t size) { - int i = 0, j =0; + int i = 0, j =0; - RT_ASSERT(addr); + RT_ASSERT(addr); - addr = addr & ~0xF; - size = 4*((size + 3)/4); + addr = addr & ~0xF; + size = 4*((size + 3)/4); - while(i < size) - { - rt_kprintf("0x%08x: ", addr ); + while(i < size) + { + rt_kprintf("0x%08x: ", addr ); - for(j=0; j<4; j++) - { - rt_kprintf("0x%08x ", *(rt_uint32_t *)addr); + for(j=0; j<4; j++) + { + rt_kprintf("0x%08x ", *(rt_uint32_t *)addr); - addr += 4; - i++; - } + addr += 4; + i++; + } - rt_kprintf("\n"); - } + rt_kprintf("\n"); + } - return; + return; } diff --git a/libcpu/arm/cortex-a/SConscript b/libcpu/arm/cortex-a/SConscript index 28af7ba651..a9fe6f0bc9 100644 --- a/libcpu/arm/cortex-a/SConscript +++ b/libcpu/arm/cortex-a/SConscript @@ -5,9 +5,27 @@ from building import * Import('rtconfig') cwd = GetCurrentDir() -src = Glob('*.c') + Glob('*.cpp') +src = Split(''' +cache.c +cpu.c +gtimer.c +mmu.c +pmu.c +stack.c + +''') CPPPATH = [cwd] +if GetDepend('RT_USING_GIC_V2'): + src += ['interrupt.c'] + src += ['gic.c'] + src += ['trap.c'] + +if GetDepend('RT_USING_GIC_V3'): + src += ['interrupt.c'] + src += ['gicv3.c'] + src += ['trap.c'] + if rtconfig.PLATFORM == 'armcc': src += Glob('*_rvds.S') @@ -18,6 +36,9 @@ if rtconfig.PLATFORM == 'gcc': if rtconfig.PLATFORM == 'iar': src += Glob('*_iar.S') +if rtconfig.PLATFORM == 'iar': + src += Glob('*_iar.S') + group = DefineGroup('CPU', src, depend = [''], CPPPATH = CPPPATH) Return('group') diff --git a/libcpu/arm/cortex-a/armv7.h b/libcpu/arm/cortex-a/armv7.h index d22f72fa68..f284bb5255 100644 --- a/libcpu/arm/cortex-a/armv7.h +++ b/libcpu/arm/cortex-a/armv7.h @@ -1,5 +1,5 @@ /* - * Copyright (c) 2006-2018, RT-Thread Development Team + * Copyright (c) 2006-2021, RT-Thread Development Team * * SPDX-License-Identifier: Apache-2.0 * @@ -12,43 +12,43 @@ /* the exception stack without VFP registers */ struct rt_hw_exp_stack { - unsigned long r0; - unsigned long r1; - unsigned long r2; - unsigned long r3; - unsigned long r4; - unsigned long r5; - unsigned long r6; - unsigned long r7; - unsigned long r8; - unsigned long r9; - unsigned long r10; - unsigned long fp; - unsigned long ip; - unsigned long sp; - unsigned long lr; - unsigned long pc; - unsigned long cpsr; + unsigned long r0; + unsigned long r1; + unsigned long r2; + unsigned long r3; + unsigned long r4; + unsigned long r5; + unsigned long r6; + unsigned long r7; + unsigned long r8; + unsigned long r9; + unsigned long r10; + unsigned long fp; + unsigned long ip; + unsigned long sp; + unsigned long lr; + unsigned long pc; + unsigned long cpsr; }; struct rt_hw_stack { - unsigned long cpsr; - unsigned long r0; - unsigned long r1; - unsigned long r2; - unsigned long r3; - unsigned long r4; - unsigned long r5; - unsigned long r6; - unsigned long r7; - unsigned long r8; - unsigned long r9; - unsigned long r10; - unsigned long fp; - unsigned long ip; - unsigned long lr; - unsigned long pc; + unsigned long cpsr; + unsigned long r0; + unsigned long r1; + unsigned long r2; + unsigned long r3; + unsigned long r4; + unsigned long r5; + unsigned long r6; + unsigned long r7; + unsigned long r8; + unsigned long r9; + unsigned long r10; + unsigned long fp; + unsigned long ip; + unsigned long lr; + unsigned long pc; }; #define USERMODE 0x10 diff --git a/libcpu/arm/cortex-a/cache.c b/libcpu/arm/cortex-a/cache.c index 30af86baa1..0a7e702dbb 100644 --- a/libcpu/arm/cortex-a/cache.c +++ b/libcpu/arm/cortex-a/cache.c @@ -1,11 +1,11 @@ /* - * Copyright (c) 2006-2018, RT-Thread Development Team + * Copyright (c) 2006-2021, RT-Thread Development Team * * SPDX-License-Identifier: Apache-2.0 * * Change Logs: * Date Author Notes - * 2019-03-29 quanzhao the first version + * 2019-03-29 quanzhao the first version */ #include <rthw.h> #include <rtdef.h> diff --git a/libcpu/arm/cortex-a/cp15.h b/libcpu/arm/cortex-a/cp15.h index 97c5b93ad2..2bf91ac5ad 100644 --- a/libcpu/arm/cortex-a/cp15.h +++ b/libcpu/arm/cortex-a/cp15.h @@ -1,5 +1,5 @@ /* - * Copyright (c) 2006-2018, RT-Thread Development Team + * Copyright (c) 2006-2021, RT-Thread Development Team * * SPDX-License-Identifier: Apache-2.0 * @@ -10,8 +10,12 @@ #ifndef __CP15_H__ #define __CP15_H__ -unsigned long rt_cpu_get_smp_id(void); +#define __get_cp(cp, op1, Rt, CRn, CRm, op2) __asm__ volatile("MRC p" # cp ", " # op1 ", %0, c" # CRn ", c" # CRm ", " # op2 : "=r" (Rt) : : "memory" ) +#define __set_cp(cp, op1, Rt, CRn, CRm, op2) __asm__ volatile("MCR p" # cp ", " # op1 ", %0, c" # CRn ", c" # CRm ", " # op2 : : "r" (Rt) : "memory" ) +#define __get_cp64(cp, op1, Rt, CRm) __asm__ volatile("MRRC p" # cp ", " # op1 ", %Q0, %R0, c" # CRm : "=r" (Rt) : : "memory" ) +#define __set_cp64(cp, op1, Rt, CRm) __asm__ volatile("MCRR p" # cp ", " # op1 ", %Q0, %R0, c" # CRm : : "r" (Rt) : "memory" ) +int rt_hw_cpu_id(void); void rt_cpu_mmu_disable(void); void rt_cpu_mmu_enable(void); void rt_cpu_tlb_set(volatile unsigned long*); diff --git a/libcpu/arm/cortex-a/cp15_gcc.S b/libcpu/arm/cortex-a/cp15_gcc.S index dd2436ffee..983ae522ef 100644 --- a/libcpu/arm/cortex-a/cp15_gcc.S +++ b/libcpu/arm/cortex-a/cp15_gcc.S @@ -8,9 +8,11 @@ * 2013-07-05 Bernard the first version */ -.globl rt_cpu_get_smp_id -rt_cpu_get_smp_id: - mrc p15, #0, r0, c0, c0, #5 +.weak rt_hw_cpu_id +rt_hw_cpu_id: + mrc p15, #0, r0, c0, c0, #5 @ read multiprocessor affinity register + ldr r1, =0xFFFF03 @ Affinity mask off, leaving CPU ID field, [0:1]CPU ID, [8:15]Cluster ID Aff1, [16:23]Cluster ID Aff2 + and r0, r0, r1 bx lr .globl rt_cpu_vector_set_base diff --git a/libcpu/arm/cortex-a/cpu.c b/libcpu/arm/cortex-a/cpu.c index 6775b781bc..7367bddd9f 100644 --- a/libcpu/arm/cortex-a/cpu.c +++ b/libcpu/arm/cortex-a/cpu.c @@ -1,5 +1,5 @@ /* - * Copyright (c) 2006-2018, RT-Thread Development Team + * Copyright (c) 2006-2021, RT-Thread Development Team * * SPDX-License-Identifier: Apache-2.0 * @@ -15,17 +15,6 @@ #ifdef RT_USING_SMP -int rt_hw_cpu_id(void) -{ - int cpu_id; - __asm__ volatile ( - "mrc p15, 0, %0, c0, c0, 5" - :"=r"(cpu_id) - ); - cpu_id &= 0xf; - return cpu_id; -}; - void rt_hw_spin_lock_init(rt_hw_spinlock_t *lock) { lock->slock = 0; diff --git a/libcpu/arm/cortex-a/gic.c b/libcpu/arm/cortex-a/gic.c index 2e94b88277..60e924d405 100644 --- a/libcpu/arm/cortex-a/gic.c +++ b/libcpu/arm/cortex-a/gic.c @@ -1,5 +1,5 @@ /* - * Copyright (c) 2006-2018, RT-Thread Development Team + * Copyright (c) 2006-2021, RT-Thread Development Team * * SPDX-License-Identifier: Apache-2.0 * @@ -28,29 +28,35 @@ struct arm_gic /* 'ARM_GIC_MAX_NR' is the number of cores */ static struct arm_gic _gic_table[ARM_GIC_MAX_NR]; -#define GIC_CPU_CTRL(hw_base) __REG32((hw_base) + 0x00) -#define GIC_CPU_PRIMASK(hw_base) __REG32((hw_base) + 0x04) -#define GIC_CPU_BINPOINT(hw_base) __REG32((hw_base) + 0x08) -#define GIC_CPU_INTACK(hw_base) __REG32((hw_base) + 0x0c) -#define GIC_CPU_EOI(hw_base) __REG32((hw_base) + 0x10) -#define GIC_CPU_RUNNINGPRI(hw_base) __REG32((hw_base) + 0x14) -#define GIC_CPU_HIGHPRI(hw_base) __REG32((hw_base) + 0x18) +/** Macro to access the Generic Interrupt Controller Interface (GICC) +*/ +#define GIC_CPU_CTRL(hw_base) __REG32((hw_base) + 0x00U) +#define GIC_CPU_PRIMASK(hw_base) __REG32((hw_base) + 0x04U) +#define GIC_CPU_BINPOINT(hw_base) __REG32((hw_base) + 0x08U) +#define GIC_CPU_INTACK(hw_base) __REG32((hw_base) + 0x0cU) +#define GIC_CPU_EOI(hw_base) __REG32((hw_base) + 0x10U) +#define GIC_CPU_RUNNINGPRI(hw_base) __REG32((hw_base) + 0x14U) +#define GIC_CPU_HIGHPRI(hw_base) __REG32((hw_base) + 0x18U) +#define GIC_CPU_IIDR(hw_base) __REG32((hw_base) + 0xFCU) -#define GIC_DIST_CTRL(hw_base) __REG32((hw_base) + 0x000) -#define GIC_DIST_TYPE(hw_base) __REG32((hw_base) + 0x004) -#define GIC_DIST_IGROUP(hw_base, n) __REG32((hw_base) + 0x080 + ((n)/32) * 4) -#define GIC_DIST_ENABLE_SET(hw_base, n) __REG32((hw_base) + 0x100 + ((n)/32) * 4) -#define GIC_DIST_ENABLE_CLEAR(hw_base, n) __REG32((hw_base) + 0x180 + ((n)/32) * 4) -#define GIC_DIST_PENDING_SET(hw_base, n) __REG32((hw_base) + 0x200 + ((n)/32) * 4) -#define GIC_DIST_PENDING_CLEAR(hw_base, n) __REG32((hw_base) + 0x280 + ((n)/32) * 4) -#define GIC_DIST_ACTIVE_SET(hw_base, n) __REG32((hw_base) + 0x300 + ((n)/32) * 4) -#define GIC_DIST_ACTIVE_CLEAR(hw_base, n) __REG32((hw_base) + 0x380 + ((n)/32) * 4) -#define GIC_DIST_PRI(hw_base, n) __REG32((hw_base) + 0x400 + ((n)/4) * 4) -#define GIC_DIST_TARGET(hw_base, n) __REG32((hw_base) + 0x800 + ((n)/4) * 4) -#define GIC_DIST_CONFIG(hw_base, n) __REG32((hw_base) + 0xc00 + ((n)/16) * 4) -#define GIC_DIST_SOFTINT(hw_base) __REG32((hw_base) + 0xf00) -#define GIC_DIST_CPENDSGI(hw_base, n) __REG32((hw_base) + 0xf10 + ((n)/4) * 4) -#define GIC_DIST_ICPIDR2(hw_base) __REG32((hw_base) + 0xfe8) +/** Macro to access the Generic Interrupt Controller Distributor (GICD) +*/ +#define GIC_DIST_CTRL(hw_base) __REG32((hw_base) + 0x000U) +#define GIC_DIST_TYPE(hw_base) __REG32((hw_base) + 0x004U) +#define GIC_DIST_IGROUP(hw_base, n) __REG32((hw_base) + 0x080U + ((n)/32U) * 4U) +#define GIC_DIST_ENABLE_SET(hw_base, n) __REG32((hw_base) + 0x100U + ((n)/32U) * 4U) +#define GIC_DIST_ENABLE_CLEAR(hw_base, n) __REG32((hw_base) + 0x180U + ((n)/32U) * 4U) +#define GIC_DIST_PENDING_SET(hw_base, n) __REG32((hw_base) + 0x200U + ((n)/32U) * 4U) +#define GIC_DIST_PENDING_CLEAR(hw_base, n) __REG32((hw_base) + 0x280U + ((n)/32U) * 4U) +#define GIC_DIST_ACTIVE_SET(hw_base, n) __REG32((hw_base) + 0x300U + ((n)/32U) * 4U) +#define GIC_DIST_ACTIVE_CLEAR(hw_base, n) __REG32((hw_base) + 0x380U + ((n)/32U) * 4U) +#define GIC_DIST_PRI(hw_base, n) __REG32((hw_base) + 0x400U + ((n)/4U) * 4U) +#define GIC_DIST_TARGET(hw_base, n) __REG32((hw_base) + 0x800U + ((n)/4U) * 4U) +#define GIC_DIST_CONFIG(hw_base, n) __REG32((hw_base) + 0xc00U + ((n)/16U) * 4U) +#define GIC_DIST_SOFTINT(hw_base) __REG32((hw_base) + 0xf00U) +#define GIC_DIST_CPENDSGI(hw_base, n) __REG32((hw_base) + 0xf10U + ((n)/4U) * 4U) +#define GIC_DIST_SPENDSGI(hw_base, n) __REG32((hw_base) + 0xf20U + ((n)/4U) * 4U) +#define GIC_DIST_ICPIDR2(hw_base) __REG32((hw_base) + 0xfe8U) static unsigned int _gic_max_irq; @@ -67,12 +73,12 @@ int arm_gic_get_active_irq(rt_uint32_t index) void arm_gic_ack(rt_uint32_t index, int irq) { - rt_uint32_t mask = 1 << (irq % 32); + rt_uint32_t mask = 1U << (irq % 32U); RT_ASSERT(index < ARM_GIC_MAX_NR); irq = irq - _gic_table[index].offset; - RT_ASSERT(irq >= 0); + RT_ASSERT(irq >= 0U); GIC_DIST_PENDING_CLEAR(_gic_table[index].dist_hw_base, irq) = mask; GIC_CPU_EOI(_gic_table[index].cpu_hw_base) = irq; @@ -80,36 +86,136 @@ void arm_gic_ack(rt_uint32_t index, int irq) void arm_gic_mask(rt_uint32_t index, int irq) { - rt_uint32_t mask = 1 << (irq % 32); + rt_uint32_t mask = 1U << (irq % 32U); RT_ASSERT(index < ARM_GIC_MAX_NR); irq = irq - _gic_table[index].offset; - RT_ASSERT(irq >= 0); + RT_ASSERT(irq >= 0U); GIC_DIST_ENABLE_CLEAR(_gic_table[index].dist_hw_base, irq) = mask; } -void arm_gic_clear_pending(rt_uint32_t index, int irq) +void arm_gic_umask(rt_uint32_t index, int irq) { - rt_uint32_t mask = 1 << (irq % 32); + rt_uint32_t mask = 1U << (irq % 32U); RT_ASSERT(index < ARM_GIC_MAX_NR); irq = irq - _gic_table[index].offset; - RT_ASSERT(irq >= 0); + RT_ASSERT(irq >= 0U); - GIC_DIST_PENDING_CLEAR(_gic_table[index].dist_hw_base, irq) = mask; + GIC_DIST_ENABLE_SET(_gic_table[index].dist_hw_base, irq) = mask; +} + +rt_uint32_t arm_gic_get_pending_irq(rt_uint32_t index, int irq) +{ + rt_uint32_t pend; + + RT_ASSERT(index < ARM_GIC_MAX_NR); + + irq = irq - _gic_table[index].offset; + RT_ASSERT(irq >= 0U); + + if (irq >= 16U) + { + pend = (GIC_DIST_PENDING_SET(_gic_table[index].dist_hw_base, irq) >> (irq % 32U)) & 0x1UL; + } + else + { + /* INTID 0-15 Software Generated Interrupt */ + pend = (GIC_DIST_SPENDSGI(_gic_table[index].dist_hw_base, irq) >> ((irq % 4U) * 8U)) & 0xFFUL; + /* No CPU identification offered */ + if (pend != 0U) + { + pend = 1U; + } + else + { + pend = 0U; + } + } + + return (pend); +} + +void arm_gic_set_pending_irq(rt_uint32_t index, int irq) +{ + RT_ASSERT(index < ARM_GIC_MAX_NR); + + irq = irq - _gic_table[index].offset; + RT_ASSERT(irq >= 0U); + + if (irq >= 16U) + { + GIC_DIST_PENDING_SET(_gic_table[index].dist_hw_base, irq) = 1U << (irq % 32U); + } + else + { + /* INTID 0-15 Software Generated Interrupt */ + /* Forward the interrupt to the CPU interface that requested it */ + GIC_DIST_SOFTINT(_gic_table[index].dist_hw_base) = (irq | 0x02000000U); + } +} + +void arm_gic_clear_pending_irq(rt_uint32_t index, int irq) +{ + rt_uint32_t mask; + + RT_ASSERT(index < ARM_GIC_MAX_NR); + + irq = irq - _gic_table[index].offset; + RT_ASSERT(irq >= 0U); + + if (irq >= 16U) + { + mask = 1U << (irq % 32U); + GIC_DIST_PENDING_CLEAR(_gic_table[index].dist_hw_base, irq) = mask; + } + else + { + mask = 1U << ((irq % 4U) * 8U); + GIC_DIST_CPENDSGI(_gic_table[index].dist_hw_base, irq) = mask; + } +} + +void arm_gic_set_configuration(rt_uint32_t index, int irq, uint32_t config) +{ + rt_uint32_t icfgr; + rt_uint32_t shift; + + RT_ASSERT(index < ARM_GIC_MAX_NR); + + irq = irq - _gic_table[index].offset; + RT_ASSERT(irq >= 0U); + + icfgr = GIC_DIST_CONFIG(_gic_table[index].dist_hw_base, irq); + shift = (irq % 16U) << 1U; + + icfgr &= (~(3U << shift)); + icfgr |= (config << shift); + + GIC_DIST_CONFIG(_gic_table[index].dist_hw_base, irq) = icfgr; +} + +rt_uint32_t arm_gic_get_configuration(rt_uint32_t index, int irq) +{ + RT_ASSERT(index < ARM_GIC_MAX_NR); + + irq = irq - _gic_table[index].offset; + RT_ASSERT(irq >= 0U); + + return (GIC_DIST_CONFIG(_gic_table[index].dist_hw_base, irq) >> ((irq % 16U) >> 1U)); } void arm_gic_clear_active(rt_uint32_t index, int irq) { - rt_uint32_t mask = 1 << (irq % 32); + rt_uint32_t mask = 1U << (irq % 32U); RT_ASSERT(index < ARM_GIC_MAX_NR); irq = irq - _gic_table[index].offset; - RT_ASSERT(irq >= 0); + RT_ASSERT(irq >= 0U); GIC_DIST_ACTIVE_CLEAR(_gic_table[index].dist_hw_base, irq) = mask; } @@ -122,79 +228,149 @@ void arm_gic_set_cpu(rt_uint32_t index, int irq, unsigned int cpumask) RT_ASSERT(index < ARM_GIC_MAX_NR); irq = irq - _gic_table[index].offset; - RT_ASSERT(irq >= 0); + RT_ASSERT(irq >= 0U); old_tgt = GIC_DIST_TARGET(_gic_table[index].dist_hw_base, irq); - old_tgt &= ~(0x0FFUL << ((irq % 4)*8)); - old_tgt |= cpumask << ((irq % 4)*8); + old_tgt &= ~(0x0FFUL << ((irq % 4U)*8U)); + old_tgt |= cpumask << ((irq % 4U)*8U); GIC_DIST_TARGET(_gic_table[index].dist_hw_base, irq) = old_tgt; } -void arm_gic_umask(rt_uint32_t index, int irq) +rt_uint32_t arm_gic_get_target_cpu(rt_uint32_t index, int irq) { - rt_uint32_t mask = 1 << (irq % 32); + RT_ASSERT(index < ARM_GIC_MAX_NR); + + irq = irq - _gic_table[index].offset; + RT_ASSERT(irq >= 0U); + + return (GIC_DIST_TARGET(_gic_table[index].dist_hw_base, irq) >> ((irq % 4U) * 8U)) & 0xFFUL; +} + +void arm_gic_set_priority(rt_uint32_t index, int irq, rt_uint32_t priority) +{ + rt_uint32_t mask; RT_ASSERT(index < ARM_GIC_MAX_NR); irq = irq - _gic_table[index].offset; - RT_ASSERT(irq >= 0); + RT_ASSERT(irq >= 0U); - GIC_DIST_ENABLE_SET(_gic_table[index].dist_hw_base, irq) = mask; + mask = GIC_DIST_PRI(_gic_table[index].dist_hw_base, irq); + mask &= ~(0xFFUL << ((irq % 4U) * 8U)); + mask |= ((priority & 0xFFUL) << ((irq % 4U) * 8U)); + GIC_DIST_PRI(_gic_table[index].dist_hw_base, irq) = mask; } -void arm_gic_dump_type(rt_uint32_t index) +rt_uint32_t arm_gic_get_priority(rt_uint32_t index, int irq) { - unsigned int gic_type; + RT_ASSERT(index < ARM_GIC_MAX_NR); - gic_type = GIC_DIST_TYPE(_gic_table[index].dist_hw_base); - rt_kprintf("GICv%d on %p, max IRQs: %d, %s security extension(%08x)\n", - (GIC_DIST_ICPIDR2(_gic_table[index].dist_hw_base) >> 4) & 0xf, - _gic_table[index].dist_hw_base, - _gic_max_irq, - gic_type & (1 << 10) ? "has" : "no", - gic_type); + irq = irq - _gic_table[index].offset; + RT_ASSERT(irq >= 0U); + + return (GIC_DIST_PRI(_gic_table[index].dist_hw_base, irq) >> ((irq % 4U) * 8U)) & 0xFFUL; } -void arm_gic_dump(rt_uint32_t index) +void arm_gic_set_interface_prior_mask(rt_uint32_t index, rt_uint32_t priority) { - unsigned int i, k; + RT_ASSERT(index < ARM_GIC_MAX_NR); - k = GIC_CPU_HIGHPRI(_gic_table[index].cpu_hw_base); - rt_kprintf("--- high pending priority: %d(%08x)\n", k, k); - rt_kprintf("--- hw mask ---\n"); - for (i = 0; i < _gic_max_irq / 32; i++) - { - rt_kprintf("0x%08x, ", - GIC_DIST_ENABLE_SET(_gic_table[index].dist_hw_base, - i * 32)); - } - rt_kprintf("\n--- hw pending ---\n"); - for (i = 0; i < _gic_max_irq / 32; i++) - { - rt_kprintf("0x%08x, ", - GIC_DIST_PENDING_SET(_gic_table[index].dist_hw_base, - i * 32)); - } - rt_kprintf("\n--- hw active ---\n"); - for (i = 0; i < _gic_max_irq / 32; i++) - { - rt_kprintf("0x%08x, ", - GIC_DIST_ACTIVE_SET(_gic_table[index].dist_hw_base, - i * 32)); - } - rt_kprintf("\n"); + /* set priority mask */ + GIC_CPU_PRIMASK(_gic_table[index].cpu_hw_base) = priority & 0xFFUL; +} + +rt_uint32_t arm_gic_get_interface_prior_mask(rt_uint32_t index) +{ + RT_ASSERT(index < ARM_GIC_MAX_NR); + + return GIC_CPU_PRIMASK(_gic_table[index].cpu_hw_base); +} + +void arm_gic_set_binary_point(rt_uint32_t index, rt_uint32_t binary_point) +{ + GIC_CPU_BINPOINT(_gic_table[index].cpu_hw_base) = binary_point & 0x7U; +} + +rt_uint32_t arm_gic_get_binary_point(rt_uint32_t index) +{ + return GIC_CPU_BINPOINT(_gic_table[index].cpu_hw_base); +} + +rt_uint32_t arm_gic_get_irq_status(rt_uint32_t index, int irq) +{ + rt_uint32_t pending; + rt_uint32_t active; + + RT_ASSERT(index < ARM_GIC_MAX_NR); + + irq = irq - _gic_table[index].offset; + RT_ASSERT(irq >= 0U); + + active = (GIC_DIST_ACTIVE_SET(_gic_table[index].dist_hw_base, irq) >> (irq % 32U)) & 0x1UL; + pending = (GIC_DIST_PENDING_SET(_gic_table[index].dist_hw_base, irq) >> (irq % 32U)) & 0x1UL; + + return ((active << 1U) | pending); +} + +void arm_gic_send_sgi(rt_uint32_t index, int irq, rt_uint32_t target_list, rt_uint32_t filter_list) +{ + RT_ASSERT(index < ARM_GIC_MAX_NR); + + irq = irq - _gic_table[index].offset; + RT_ASSERT(irq >= 0U); + + GIC_DIST_SOFTINT(_gic_table[index].dist_hw_base) = ((filter_list & 0x3U) << 24U) | ((target_list & 0xFFUL) << 16U) | (irq & 0x0FUL); +} + +rt_uint32_t arm_gic_get_high_pending_irq(rt_uint32_t index) +{ + RT_ASSERT(index < ARM_GIC_MAX_NR); + + return GIC_CPU_HIGHPRI(_gic_table[index].cpu_hw_base); +} + +rt_uint32_t arm_gic_get_interface_id(rt_uint32_t index) +{ + RT_ASSERT(index < ARM_GIC_MAX_NR); + + return GIC_CPU_IIDR(_gic_table[index].cpu_hw_base); +} + +void arm_gic_set_group(rt_uint32_t index, int irq, rt_uint32_t group) +{ + uint32_t igroupr; + uint32_t shift; + + RT_ASSERT(index < ARM_GIC_MAX_NR); + RT_ASSERT(group <= 1U); + + irq = irq - _gic_table[index].offset; + RT_ASSERT(irq >= 0U); + + igroupr = GIC_DIST_IGROUP(_gic_table[index].dist_hw_base, irq); + shift = (irq % 32U); + igroupr &= (~(1U << shift)); + igroupr |= ( (group & 0x1U) << shift); + + GIC_DIST_IGROUP(_gic_table[index].dist_hw_base, irq) = igroupr; +} + +rt_uint32_t arm_gic_get_group(rt_uint32_t index, int irq) +{ + RT_ASSERT(index < ARM_GIC_MAX_NR); + + irq = irq - _gic_table[index].offset; + RT_ASSERT(irq >= 0U); + + return (GIC_DIST_IGROUP(_gic_table[index].dist_hw_base, irq) >> (irq % 32U)) & 0x1UL; } -#ifdef RT_USING_FINSH -#include <finsh.h> -FINSH_FUNCTION_EXPORT_ALIAS(arm_gic_dump, gic, show gic status); -#endif int arm_gic_dist_init(rt_uint32_t index, rt_uint32_t dist_base, int irq_start) { unsigned int gic_type, i; - rt_uint32_t cpumask = 1 << 0; + rt_uint32_t cpumask = 1U << 0U; RT_ASSERT(index < ARM_GIC_MAX_NR); @@ -203,50 +379,50 @@ int arm_gic_dist_init(rt_uint32_t index, rt_uint32_t dist_base, int irq_start) /* Find out how many interrupts are supported. */ gic_type = GIC_DIST_TYPE(dist_base); - _gic_max_irq = ((gic_type & 0x1f) + 1) * 32; + _gic_max_irq = ((gic_type & 0x1fU) + 1U) * 32U; /* * The GIC only supports up to 1020 interrupt sources. * Limit this to either the architected maximum, or the * platform maximum. */ - if (_gic_max_irq > 1020) - _gic_max_irq = 1020; + if (_gic_max_irq > 1020U) + _gic_max_irq = 1020U; if (_gic_max_irq > ARM_GIC_NR_IRQS) /* the platform maximum interrupts */ _gic_max_irq = ARM_GIC_NR_IRQS; - cpumask |= cpumask << 8; - cpumask |= cpumask << 16; - cpumask |= cpumask << 24; + cpumask |= cpumask << 8U; + cpumask |= cpumask << 16U; + cpumask |= cpumask << 24U; - GIC_DIST_CTRL(dist_base) = 0x0; + GIC_DIST_CTRL(dist_base) = 0x0U; /* Set all global interrupts to be level triggered, active low. */ - for (i = 32; i < _gic_max_irq; i += 16) - GIC_DIST_CONFIG(dist_base, i) = 0x0; + for (i = 32U; i < _gic_max_irq; i += 16U) + GIC_DIST_CONFIG(dist_base, i) = 0x0U; /* Set all global interrupts to this CPU only. */ - for (i = 32; i < _gic_max_irq; i += 4) + for (i = 32U; i < _gic_max_irq; i += 4U) GIC_DIST_TARGET(dist_base, i) = cpumask; /* Set priority on all interrupts. */ - for (i = 0; i < _gic_max_irq; i += 4) - GIC_DIST_PRI(dist_base, i) = 0xa0a0a0a0; + for (i = 0U; i < _gic_max_irq; i += 4U) + GIC_DIST_PRI(dist_base, i) = 0xa0a0a0a0U; /* Disable all interrupts. */ - for (i = 0; i < _gic_max_irq; i += 32) - GIC_DIST_ENABLE_CLEAR(dist_base, i) = 0xffffffff; + for (i = 0U; i < _gic_max_irq; i += 32U) + GIC_DIST_ENABLE_CLEAR(dist_base, i) = 0xffffffffU; #if 0 /* All interrupts defaults to IGROUP1(IRQ). */ for (i = 0; i < _gic_max_irq; i += 32) GIC_DIST_IGROUP(dist_base, i) = 0xffffffff; #endif - for (i = 0; i < _gic_max_irq; i += 32) - GIC_DIST_IGROUP(dist_base, i) = 0; + for (i = 0U; i < _gic_max_irq; i += 32U) + GIC_DIST_IGROUP(dist_base, i) = 0U; /* Enable group0 and group1 interrupt forwarding. */ - GIC_DIST_CTRL(dist_base) = 0x01; + GIC_DIST_CTRL(dist_base) = 0x01U; return 0; } @@ -257,44 +433,63 @@ int arm_gic_cpu_init(rt_uint32_t index, rt_uint32_t cpu_base) _gic_table[index].cpu_hw_base = cpu_base; - GIC_CPU_PRIMASK(cpu_base) = 0xf0; - GIC_CPU_BINPOINT(cpu_base) = 0x7; + GIC_CPU_PRIMASK(cpu_base) = 0xf0U; + GIC_CPU_BINPOINT(cpu_base) = 0x7U; /* Enable CPU interrupt */ - GIC_CPU_CTRL(cpu_base) = 0x01; + GIC_CPU_CTRL(cpu_base) = 0x01U; return 0; } -void arm_gic_set_group(rt_uint32_t index, int vector, int group) +void arm_gic_dump_type(rt_uint32_t index) +{ + unsigned int gic_type; + + gic_type = GIC_DIST_TYPE(_gic_table[index].dist_hw_base); + rt_kprintf("GICv%d on %p, max IRQs: %d, %s security extension(%08x)\n", + (GIC_DIST_ICPIDR2(_gic_table[index].dist_hw_base) >> 4U) & 0xfUL, + _gic_table[index].dist_hw_base, + _gic_max_irq, + gic_type & (1U << 10U) ? "has" : "no", + gic_type); +} + +void arm_gic_dump(rt_uint32_t index) { - /* As for GICv2, there are only group0 and group1. */ - RT_ASSERT(group <= 1); - RT_ASSERT(vector < _gic_max_irq); + unsigned int i, k; - if (group == 0) + k = GIC_CPU_HIGHPRI(_gic_table[index].cpu_hw_base); + rt_kprintf("--- high pending priority: %d(%08x)\n", k, k); + rt_kprintf("--- hw mask ---\n"); + for (i = 0U; i < _gic_max_irq / 32U; i++) { - GIC_DIST_IGROUP(_gic_table[index].dist_hw_base, - vector) &= ~(1 << (vector % 32)); + rt_kprintf("0x%08x, ", + GIC_DIST_ENABLE_SET(_gic_table[index].dist_hw_base, + i * 32U)); } - else if (group == 1) + rt_kprintf("\n--- hw pending ---\n"); + for (i = 0U; i < _gic_max_irq / 32U; i++) { - GIC_DIST_IGROUP(_gic_table[index].dist_hw_base, - vector) |= (1 << (vector % 32)); + rt_kprintf("0x%08x, ", + GIC_DIST_PENDING_SET(_gic_table[index].dist_hw_base, + i * 32U)); } + rt_kprintf("\n--- hw active ---\n"); + for (i = 0U; i < _gic_max_irq / 32U; i++) + { + rt_kprintf("0x%08x, ", + GIC_DIST_ACTIVE_SET(_gic_table[index].dist_hw_base, + i * 32U)); + } + rt_kprintf("\n"); } -#ifdef RT_USING_SMP -void rt_hw_ipi_send(int ipi_vector, unsigned int cpu_mask) - { - /* note: ipi_vector maybe different with irq_vector */ - GIC_DIST_SOFTINT(_gic_table[0].dist_hw_base) = (cpu_mask << 16) | ipi_vector; -} -#endif - -#ifdef RT_USING_SMP -void rt_hw_ipi_handler_install(int ipi_vector, rt_isr_handler_t ipi_isr_handler) +long gic_dump(void) { - /* note: ipi_vector maybe different with irq_vector */ - rt_hw_interrupt_install(ipi_vector, ipi_isr_handler, 0, "IPI_HANDLER"); + arm_gic_dump_type(0); + arm_gic_dump(0); + + return 0; } -#endif +MSH_CMD_EXPORT(gic_dump, show gic status); + diff --git a/libcpu/arm/cortex-a/gic.h b/libcpu/arm/cortex-a/gic.h index a16d0467fb..e74b760f45 100644 --- a/libcpu/arm/cortex-a/gic.h +++ b/libcpu/arm/cortex-a/gic.h @@ -1,5 +1,5 @@ /* - * Copyright (c) 2006-2018, RT-Thread Development Team + * Copyright (c) 2006-2021, RT-Thread Development Team * * SPDX-License-Identifier: Apache-2.0 * @@ -14,19 +14,46 @@ #include <rthw.h> #include <board.h> -int arm_gic_dist_init(rt_uint32_t index, rt_uint32_t dist_base, int irq_start); -int arm_gic_cpu_init(rt_uint32_t index, rt_uint32_t cpu_base); +int arm_gic_get_active_irq(rt_uint32_t index); +void arm_gic_ack(rt_uint32_t index, int irq); void arm_gic_mask(rt_uint32_t index, int irq); void arm_gic_umask(rt_uint32_t index, int irq); -void arm_gic_set_cpu(rt_uint32_t index, int irq, unsigned int cpumask); -void arm_gic_set_group(rt_uint32_t index, int vector, int group); -int arm_gic_get_active_irq(rt_uint32_t index); -void arm_gic_ack(rt_uint32_t index, int irq); +rt_uint32_t arm_gic_get_pending_irq(rt_uint32_t index, int irq); +void arm_gic_set_pending_irq(rt_uint32_t index, int irq); +void arm_gic_clear_pending_irq(rt_uint32_t index, int irq); + +void arm_gic_set_configuration(rt_uint32_t index, int irq, uint32_t config); +rt_uint32_t arm_gic_get_configuration(rt_uint32_t index, int irq); void arm_gic_clear_active(rt_uint32_t index, int irq); -void arm_gic_clear_pending(rt_uint32_t index, int irq); + +void arm_gic_set_cpu(rt_uint32_t index, int irq, unsigned int cpumask); +rt_uint32_t arm_gic_get_target_cpu(rt_uint32_t index, int irq); + +void arm_gic_set_priority(rt_uint32_t index, int irq, rt_uint32_t priority); +rt_uint32_t arm_gic_get_priority(rt_uint32_t index, int irq); + +void arm_gic_set_interface_prior_mask(rt_uint32_t index, rt_uint32_t priority); +rt_uint32_t arm_gic_get_interface_prior_mask(rt_uint32_t index); + +void arm_gic_set_binary_point(rt_uint32_t index, rt_uint32_t binary_point); +rt_uint32_t arm_gic_get_binary_point(rt_uint32_t index); + +rt_uint32_t arm_gic_get_irq_status(rt_uint32_t index, int irq); + +void arm_gic_send_sgi(rt_uint32_t index, int irq, rt_uint32_t target_list, rt_uint32_t filter_list); + +rt_uint32_t arm_gic_get_high_pending_irq(rt_uint32_t index); + +rt_uint32_t arm_gic_get_interface_id(rt_uint32_t index); + +void arm_gic_set_group(rt_uint32_t index, int irq, rt_uint32_t group); +rt_uint32_t arm_gic_get_group(rt_uint32_t index, int irq); + +int arm_gic_dist_init(rt_uint32_t index, rt_uint32_t dist_base, int irq_start); +int arm_gic_cpu_init(rt_uint32_t index, rt_uint32_t cpu_base); void arm_gic_dump_type(rt_uint32_t index); void arm_gic_dump(rt_uint32_t index); diff --git a/libcpu/arm/cortex-a/gicv3.c b/libcpu/arm/cortex-a/gicv3.c new file mode 100644 index 0000000000..a3fb0e767b --- /dev/null +++ b/libcpu/arm/cortex-a/gicv3.c @@ -0,0 +1,708 @@ +/* + * Copyright (c) 2006-2021, RT-Thread Development Team + * + * SPDX-License-Identifier: Apache-2.0 + * + * Change Logs: + * Date Author Notes + * 2013-07-20 Bernard first version + * 2014-04-03 Grissiom many enhancements + * 2018-11-22 Jesven add rt_hw_ipi_send() + * add rt_hw_ipi_handler_install() + */ + +#include <rthw.h> +#include <rtthread.h> + +#include "gicv3.h" +#include "cp15.h" + +#ifndef RT_CPUS_NR +#define RT_CPUS_NR 1 +#endif + +struct arm_gic_v3 +{ + rt_uint32_t offset; /* the first interrupt index in the vector table */ + rt_uint32_t redist_hw_base[RT_CPUS_NR]; /* the pointer of the gic redistributor */ + rt_uint32_t dist_hw_base; /* the base address of the gic distributor */ + rt_uint32_t cpu_hw_base[RT_CPUS_NR]; /* the base addrees of the gic cpu interface */ +}; + +/* 'ARM_GIC_MAX_NR' is the number of cores */ +static struct arm_gic_v3 _gic_table[ARM_GIC_MAX_NR]; +static unsigned int _gic_max_irq; + +/** + * @name: arm_gic_cpumask_to_affval + * @msg: + * @in param cpu_mask: + * @out param cluster_id: aff1 [0:7],aff2 [8:15],aff3 [16:23] + * @out param target_list: Target List. The set of PEs for which SGI interrupts will be generated. Each bit corresponds to the + * PE within a cluster with an Affinity 0 value equal to the bit number. + * @return {rt_uint32_t} 0 is finish , 1 is data valid + */ +RT_WEAK rt_uint32_t arm_gic_cpumask_to_affval(rt_uint32_t *cpu_mask, rt_uint32_t *cluster_id, rt_uint32_t *target_list) +{ + return 0; +} + +RT_WEAK rt_uint64_t get_main_cpu_affval(void) +{ + return 0; +} + +int arm_gic_get_active_irq(rt_uint32_t index) +{ + int irq; + + RT_ASSERT(index < ARM_GIC_MAX_NR); + + __get_gicv3_reg(ICC_IAR1, irq); + + irq = (irq & 0x1FFFFFF) + _gic_table[index].offset; + return irq; +} + +void arm_gic_ack(rt_uint32_t index, int irq) +{ + RT_ASSERT(index < ARM_GIC_MAX_NR); + RT_ASSERT(irq >= 0U); + + __asm__ volatile("dsb 0xF" :: + : "memory"); + __set_gicv3_reg(ICC_EOIR1, irq); +} + +void arm_gic_mask(rt_uint32_t index, int irq) +{ + rt_uint32_t mask = 1U << (irq % 32U); + + RT_ASSERT(index < ARM_GIC_MAX_NR); + + irq = irq - _gic_table[index].offset; + RT_ASSERT(irq >= 0U); + + if (irq < 32U) + { + rt_int32_t cpu_id = rt_hw_cpu_id(); + RT_ASSERT((cpu_id) < RT_CPUS_NR); + GIC_RDISTSGI_ICENABLER0(_gic_table[index].redist_hw_base[cpu_id]) = mask; + } + else + { + GIC_DIST_ENABLE_CLEAR(_gic_table[index].dist_hw_base, irq) = mask; + } +} + +void arm_gic_umask(rt_uint32_t index, int irq) +{ + rt_uint32_t mask = 1U << (irq % 32U); + + RT_ASSERT(index < ARM_GIC_MAX_NR); + + irq = irq - _gic_table[index].offset; + RT_ASSERT(irq >= 0U); + + if (irq < 32U) + { + rt_int32_t cpu_id = rt_hw_cpu_id(); + RT_ASSERT((cpu_id) < RT_CPUS_NR); + GIC_RDISTSGI_ISENABLER0(_gic_table[index].redist_hw_base[cpu_id]) = mask; + } + else + { + GIC_DIST_ENABLE_SET(_gic_table[index].dist_hw_base, irq) = mask; + } +} + +rt_uint32_t arm_gic_get_pending_irq(rt_uint32_t index, int irq) +{ + rt_uint32_t pend; + + RT_ASSERT(index < ARM_GIC_MAX_NR); + + irq = irq - _gic_table[index].offset; + RT_ASSERT(irq >= 0U); + + if (irq >= 16U) + { + pend = (GIC_DIST_PENDING_SET(_gic_table[index].dist_hw_base, irq) >> (irq % 32U)) & 0x1UL; + } + else + { + /* INTID 0-15 Software Generated Interrupt */ + pend = (GIC_DIST_SPENDSGI(_gic_table[index].dist_hw_base, irq) >> ((irq % 4U) * 8U)) & 0xFFUL; + /* No CPU identification offered */ + if (pend != 0U) + { + pend = 1U; + } + else + { + pend = 0U; + } + } + + return (pend); +} + +void arm_gic_set_pending_irq(rt_uint32_t index, int irq) +{ + RT_ASSERT(index < ARM_GIC_MAX_NR); + + irq = irq - _gic_table[index].offset; + RT_ASSERT(irq >= 0U); + + if (irq >= 16U) + { + GIC_DIST_PENDING_SET(_gic_table[index].dist_hw_base, irq) = 1U << (irq % 32U); + } + else + { + /* INTID 0-15 Software Generated Interrupt */ + /* Forward the interrupt to the CPU interface that requested it */ + GIC_DIST_SOFTINT(_gic_table[index].dist_hw_base) = (irq | 0x02000000U); + } +} + +void arm_gic_clear_pending_irq(rt_uint32_t index, int irq) +{ + rt_uint32_t mask; + + RT_ASSERT(index < ARM_GIC_MAX_NR); + + irq = irq - _gic_table[index].offset; + RT_ASSERT(irq >= 0U); + + if (irq >= 16U) + { + mask = 1U << (irq % 32U); + GIC_DIST_PENDING_CLEAR(_gic_table[index].dist_hw_base, irq) = mask; + } + else + { + mask = 1U << ((irq % 4U) * 8U); + GIC_DIST_CPENDSGI(_gic_table[index].dist_hw_base, irq) = mask; + } +} + +void arm_gic_set_configuration(rt_uint32_t index, int irq, uint32_t config) +{ + rt_uint32_t icfgr; + rt_uint32_t shift; + + RT_ASSERT(index < ARM_GIC_MAX_NR); + + irq = irq - _gic_table[index].offset; + RT_ASSERT(irq >= 0U); + + icfgr = GIC_DIST_CONFIG(_gic_table[index].dist_hw_base, irq); + shift = (irq % 16U) << 1U; + + icfgr &= (~(3U << shift)); + icfgr |= (config << shift); + + GIC_DIST_CONFIG(_gic_table[index].dist_hw_base, irq) = icfgr; +} + +rt_uint32_t arm_gic_get_configuration(rt_uint32_t index, int irq) +{ + RT_ASSERT(index < ARM_GIC_MAX_NR); + + irq = irq - _gic_table[index].offset; + RT_ASSERT(irq >= 0U); + + return (GIC_DIST_CONFIG(_gic_table[index].dist_hw_base, irq) >> ((irq % 16U) >> 1U)); +} + +void arm_gic_clear_active(rt_uint32_t index, int irq) +{ + rt_uint32_t mask = 1U << (irq % 32U); + + RT_ASSERT(index < ARM_GIC_MAX_NR); + + irq = irq - _gic_table[index].offset; + RT_ASSERT(irq >= 0U); + + GIC_DIST_ACTIVE_CLEAR(_gic_table[index].dist_hw_base, irq) = mask; +} + +/* Set up the cpu mask for the specific interrupt */ +void arm_gic_set_cpu(rt_uint32_t index, int irq, unsigned int cpumask) +{ + rt_uint32_t old_tgt; + + RT_ASSERT(index < ARM_GIC_MAX_NR); + + irq = irq - _gic_table[index].offset; + RT_ASSERT(irq >= 0U); + + old_tgt = GIC_DIST_TARGET(_gic_table[index].dist_hw_base, irq); + + old_tgt &= ~(0x0FFUL << ((irq % 4U) * 8U)); + old_tgt |= cpumask << ((irq % 4U) * 8U); + + GIC_DIST_TARGET(_gic_table[index].dist_hw_base, irq) = old_tgt; +} + +rt_uint32_t arm_gic_get_target_cpu(rt_uint32_t index, int irq) +{ + RT_ASSERT(index < ARM_GIC_MAX_NR); + + irq = irq - _gic_table[index].offset; + RT_ASSERT(irq >= 0U); + + return (GIC_DIST_TARGET(_gic_table[index].dist_hw_base, irq) >> ((irq % 4U) * 8U)) & 0xFFUL; +} + +void arm_gic_set_priority(rt_uint32_t index, int irq, rt_uint32_t priority) +{ + rt_uint32_t mask; + + RT_ASSERT(index < ARM_GIC_MAX_NR); + + irq = irq - _gic_table[index].offset; + RT_ASSERT(irq >= 0U); + + if (irq < 32U) + { + rt_int32_t cpu_id = rt_hw_cpu_id(); + RT_ASSERT((cpu_id) < RT_CPUS_NR); + + mask = GIC_RDISTSGI_IPRIORITYR(_gic_table[index].redist_hw_base[cpu_id], irq); + mask &= ~(0xFFUL << ((irq % 4U) * 8U)); + mask |= ((priority & 0xFFUL) << ((irq % 4U) * 8U)); + GIC_RDISTSGI_IPRIORITYR(_gic_table[index].redist_hw_base[cpu_id], irq) = mask; + } + else + { + mask = GIC_DIST_PRI(_gic_table[index].dist_hw_base, irq); + mask &= ~(0xFFUL << ((irq % 4U) * 8U)); + mask |= ((priority & 0xFFUL) << ((irq % 4U) * 8U)); + GIC_DIST_PRI(_gic_table[index].dist_hw_base, irq) = mask; + } +} + +rt_uint32_t arm_gic_get_priority(rt_uint32_t index, int irq) +{ + RT_ASSERT(index < ARM_GIC_MAX_NR); + + irq = irq - _gic_table[index].offset; + RT_ASSERT(irq >= 0U); + + if (irq < 32U) + { + rt_int32_t cpu_id = rt_hw_cpu_id(); + + RT_ASSERT((cpu_id) < RT_CPUS_NR); + return (GIC_RDISTSGI_IPRIORITYR(_gic_table[index].redist_hw_base[cpu_id], irq) >> ((irq % 4U) * 8U)) & 0xFFUL; + } + else + { + return (GIC_DIST_PRI(_gic_table[index].dist_hw_base, irq) >> ((irq % 4U) * 8U)) & 0xFFUL; + } +} + +void arm_gic_set_system_register_enable_mask(rt_uint32_t index, rt_uint32_t value) +{ + RT_ASSERT(index < ARM_GIC_MAX_NR); + + value &= 0xFFUL; + /* set priority mask */ + __set_gicv3_reg(ICC_SRE, value); + __asm__ volatile ("isb 0xF":: + :"memory"); +} + +rt_uint32_t arm_gic_get_system_register_enable_mask(rt_uint32_t index) +{ + RT_ASSERT(index < ARM_GIC_MAX_NR); + rt_uint32_t value; + + __get_gicv3_reg(ICC_SRE, value); + return value; +} + +void arm_gic_set_interface_prior_mask(rt_uint32_t index, rt_uint32_t priority) +{ + RT_ASSERT(index < ARM_GIC_MAX_NR); + + priority &= 0xFFUL; + /* set priority mask */ + __set_gicv3_reg(ICC_PMR, priority); +} + +rt_uint32_t arm_gic_get_interface_prior_mask(rt_uint32_t index) +{ + RT_ASSERT(index < ARM_GIC_MAX_NR); + rt_uint32_t priority; + + __get_gicv3_reg(ICC_PMR, priority); + return priority; +} + +void arm_gic_set_binary_point(rt_uint32_t index, rt_uint32_t binary_point) +{ + index = index; + binary_point &= 0x7U; + + __set_gicv3_reg(ICC_BPR1, binary_point); +} + +rt_uint32_t arm_gic_get_binary_point(rt_uint32_t index) +{ + rt_uint32_t binary_point; + + index = index; + __get_gicv3_reg(ICC_BPR1, binary_point); + return binary_point; +} + +rt_uint32_t arm_gic_get_irq_status(rt_uint32_t index, int irq) +{ + rt_uint32_t pending; + rt_uint32_t active; + + RT_ASSERT(index < ARM_GIC_MAX_NR); + + irq = irq - _gic_table[index].offset; + RT_ASSERT(irq >= 0U); + + active = (GIC_DIST_ACTIVE_SET(_gic_table[index].dist_hw_base, irq) >> (irq % 32U)) & 0x1UL; + pending = (GIC_DIST_PENDING_SET(_gic_table[index].dist_hw_base, irq) >> (irq % 32U)) & 0x1UL; + + return ((active << 1U) | pending); +} + +void arm_gic_send_affinity_sgi(rt_uint32_t index, int irq, rt_uint32_t cpu_mask, rt_uint32_t routing_mode) +{ + rt_uint64_t sgi_val; + + if (routing_mode) + { + sgi_val = (1ULL << 40) | ((irq & 0x0FULL) << 24); //Interrupts routed to all PEs in the system, excluding "self". + /* Write the ICC_SGI1R registers */ + __asm__ volatile("dsb 0xF" :: + : "memory"); + __set_cp64(15, 0, sgi_val, 12); + __asm__ volatile("isb 0xF" :: + : "memory"); + } + else + { + rt_uint32_t cluster_id, target_list; + while (arm_gic_cpumask_to_affval(&cpu_mask, &cluster_id, &target_list)) + { + sgi_val = ((irq & 0x0FULL) << 24 | + target_list | + ((cluster_id >> 8) & 0xFFULL) << GIC_RSGI_AFF1_OFFSET | + ((cluster_id >> 16) & 0xFFULL) << GIC_RSGI_AFF2_OFFSET | + ((cluster_id >> 24) & 0xFFull) << GIC_RSGI_AFF3_OFFSET); + + __asm__ volatile("dsb 0xF" :: + : "memory"); + __set_cp64(15, 0, sgi_val, 12); + __asm__ volatile("isb 0xF" :: + : "memory"); + } + } +} + +rt_uint32_t arm_gic_get_high_pending_irq(rt_uint32_t index) +{ + rt_uint32_t irq; + RT_ASSERT(index < ARM_GIC_MAX_NR); + + index = index; + __get_gicv3_reg(ICC_HPPIR1, irq); + return irq; +} + +rt_uint32_t arm_gic_get_interface_id(rt_uint32_t index) +{ + RT_ASSERT(index < ARM_GIC_MAX_NR); + + return GIC_CPU_IIDR(_gic_table[index].cpu_hw_base); +} + +void arm_gic_set_group(rt_uint32_t index, int irq, rt_uint32_t group) +{ + uint32_t igroupr; + uint32_t shift; + + RT_ASSERT(index < ARM_GIC_MAX_NR); + RT_ASSERT(group <= 1U); + + irq = irq - _gic_table[index].offset; + RT_ASSERT(irq >= 0U); + + igroupr = GIC_DIST_IGROUP(_gic_table[index].dist_hw_base, irq); + shift = (irq % 32U); + igroupr &= (~(1U << shift)); + igroupr |= ((group & 0x1U) << shift); + + GIC_DIST_IGROUP(_gic_table[index].dist_hw_base, irq) = igroupr; +} + +rt_uint32_t arm_gic_get_group(rt_uint32_t index, int irq) +{ + RT_ASSERT(index < ARM_GIC_MAX_NR); + + irq = irq - _gic_table[index].offset; + RT_ASSERT(irq >= 0U); + + return (GIC_DIST_IGROUP(_gic_table[index].dist_hw_base, irq) >> (irq % 32U)) & 0x1UL; +} + +static int arm_gicv3_wait_rwp(rt_uint32_t index, rt_uint32_t irq) +{ + rt_uint32_t rwp_bit; + rt_uint32_t base; + + RT_ASSERT(index < ARM_GIC_MAX_NR); + + if (irq < 32u) + { + rt_int32_t cpu_id = rt_hw_cpu_id(); + + RT_ASSERT((cpu_id) < RT_CPUS_NR); + base = _gic_table[index].redist_hw_base[cpu_id]; + rwp_bit = GICR_CTLR_RWP; + } + else + { + base = _gic_table[index].dist_hw_base; + rwp_bit = GICD_CTLR_RWP; + } + + while (__REG32(base) & rwp_bit) + { + ; + } + + return 0; +} + +int arm_gic_dist_init(rt_uint32_t index, rt_uint32_t dist_base, int irq_start) +{ + rt_uint64_t cpu0_affval; + unsigned int gic_type, i; + + RT_ASSERT(index < ARM_GIC_MAX_NR); + + _gic_table[index].dist_hw_base = dist_base; + _gic_table[index].offset = irq_start; + + /* Find out how many interrupts are supported. */ + gic_type = GIC_DIST_TYPE(dist_base); + _gic_max_irq = ((gic_type & 0x1fU) + 1U) * 32U; + + /* + * The GIC only supports up to 1020 interrupt sources. + * Limit this to either the architected maximum, or the + * platform maximum. + */ + if (_gic_max_irq > 1020U) + _gic_max_irq = 1020U; + if (_gic_max_irq > ARM_GIC_NR_IRQS) /* the platform maximum interrupts */ + _gic_max_irq = ARM_GIC_NR_IRQS; + + GIC_DIST_CTRL(dist_base) = 0x0U; + /* Wait for register write pending */ + arm_gicv3_wait_rwp(0, 32); + + /* Set all global interrupts to be level triggered, active low. */ + for (i = 32U; i < _gic_max_irq; i += 16U) + GIC_DIST_CONFIG(dist_base, i) = 0x0U; + + arm_gicv3_wait_rwp(0, 32); + + cpu0_affval = get_main_cpu_affval(); + /* Set all global interrupts to this CPU only. */ + for (i = 32U; i < _gic_max_irq; i++) + { + GIC_DIST_IROUTER_LOW(dist_base, i) = cpu0_affval; + GIC_DIST_IROUTER_HIGH(dist_base, i) = cpu0_affval >> 32; + } + + arm_gicv3_wait_rwp(0, 32); + + /* Set priority on spi interrupts. */ + for (i = 32U; i < _gic_max_irq; i += 4U) + GIC_DIST_PRI(dist_base, i) = 0xa0a0a0a0U; + + arm_gicv3_wait_rwp(0, 32); + /* Disable all interrupts. */ + for (i = 0U; i < _gic_max_irq; i += 32U) + { + GIC_DIST_PENDING_CLEAR(dist_base, i) = 0xffffffffU; + GIC_DIST_ENABLE_CLEAR(dist_base, i) = 0xffffffffU; + } + + arm_gicv3_wait_rwp(0, 32); + /* All interrupts defaults to IGROUP1(IRQ). */ + for (i = 0U; i < _gic_max_irq; i += 32U) + GIC_DIST_IGROUP(dist_base, i) = 0xffffffffU; + + arm_gicv3_wait_rwp(0, 32); + + /* + The Distributor control register (GICD_CTLR) must be configured to enable the interrupt groups and to set the routing mode. + Enable Affinity routing (ARE bits) The ARE bits in GICD_CTLR control whether affinity routing is enabled. + If affinity routing is not enabled, GICv3 can be configured for legacy operation. + Whether affinity routing is enabled or not can be controlled separately for Secure and Non-secure state. + Enables GICD_CTLR contains separate enable bits for Group 0, Secure Group 1 and Non-secure Group 1: + GICD_CTLR.EnableGrp1S enables distribution of Secure Group 1 interrupts. + GICD_CTLR.EnableGrp1NS enables distribution of Non-secure Group 1 interrupts. + GICD_CTLR.EnableGrp0 enables distribution of Group 0 interrupts. + */ + GIC_DIST_CTRL(dist_base) = GICD_CTLR_ARE_NS | GICD_CTLR_ENGRP1NS; + + return 0; +} + +int arm_gic_redist_address_set(rt_uint32_t index, rt_uint32_t redist_addr, rt_uint32_t cpu_id) +{ + RT_ASSERT(index < ARM_GIC_MAX_NR); + RT_ASSERT((cpu_id) < RT_CPUS_NR); + _gic_table[index].redist_hw_base[cpu_id] = redist_addr; + + return 0; +} + +int arm_gic_cpu_interface_address_set(rt_uint32_t index, rt_uint32_t interface_addr, rt_uint32_t cpu_id) +{ + RT_ASSERT(index < ARM_GIC_MAX_NR); + RT_ASSERT((cpu_id) < RT_CPUS_NR); + _gic_table[index].cpu_hw_base[cpu_id] = interface_addr; + + return 0; +} + +int arm_gic_redist_init(rt_uint32_t index) +{ + unsigned int i; + rt_uint32_t base; + rt_int32_t cpu_id = rt_hw_cpu_id(); + + RT_ASSERT(index < ARM_GIC_MAX_NR); + RT_ASSERT((cpu_id) < RT_CPUS_NR); + + base = _gic_table[index].redist_hw_base[cpu_id]; + /* redistributor enable */ + GIC_RDIST_WAKER(base) &= ~(1U << 1); + while (GIC_RDIST_WAKER(base) & (1 << 2)) + { + ; + } + + /* Disable all sgi and ppi interrupt */ + GIC_RDISTSGI_ICENABLER0(base) = 0xFFFFFFFF; + arm_gicv3_wait_rwp(0, 0); + + /* Clear all inetrrupt pending */ + GIC_RDISTSGI_ICPENDR0(base) = 0xFFFFFFFF; + + /* the corresponding interrupt is Group 1 or Non-secure Group 1. */ + GIC_RDISTSGI_IGROUPR0(base, 0) = 0xFFFFFFFF; + GIC_RDISTSGI_IGRPMODR0(base, 0) = 0xFFFFFFFF; + + /* Configure default priorities for SGI 0:15 and PPI 16:31. */ + for (i = 0; i < 32; i += 4) + { + GIC_RDISTSGI_IPRIORITYR(base, i) = 0xa0a0a0a0U; + } + + /* Trigger level for PPI interrupts*/ + GIC_RDISTSGI_ICFGR1(base) = 0x0U; // PPI is level-sensitive. + return 0; +} + +int arm_gic_cpu_init(rt_uint32_t index) +{ + rt_uint32_t value; + RT_ASSERT(index < ARM_GIC_MAX_NR); + + value = arm_gic_get_system_register_enable_mask(index); + value |= (1U << 0); + arm_gic_set_system_register_enable_mask(index, value); + __set_gicv3_reg(ICC_CTLR, 0); + + arm_gic_set_interface_prior_mask(index, 0xFFU); + + /* Enable group1 interrupt */ + value = 0x1U; + __set_gicv3_reg(ICC_IGRPEN1, value); + + arm_gic_set_binary_point(0, 0); + + /* ICC_BPR0_EL1 determines the preemption group for both + Group 0 and Group 1 interrupts. + */ + value = 0x1U; + __set_gicv3_reg(ICC_CTLR, value); + + return 0; +} + +#ifdef RT_USING_SMP +void arm_gic_secondary_cpu_init(void) +{ + arm_gic_redist_init(0); + + arm_gic_cpu_init(0); +} +#endif + +void arm_gic_dump_type(rt_uint32_t index) +{ + unsigned int gic_type; + + gic_type = GIC_DIST_TYPE(_gic_table[index].dist_hw_base); + rt_kprintf("GICv%d on %p, max IRQs: %d, %s security extension(%08x)\n", + (GIC_DIST_ICPIDR2(_gic_table[index].dist_hw_base) >> 4U) & 0xfUL, + _gic_table[index].dist_hw_base, + _gic_max_irq, + gic_type & (1U << 10U) ? "has" : "no", + gic_type); +} + +void arm_gic_dump(rt_uint32_t index) +{ + unsigned int i, k; + + k = arm_gic_get_high_pending_irq(0); + rt_kprintf("--- high pending priority: %d(%08x)\n", k, k); + rt_kprintf("--- hw mask ---\n"); + for (i = 0U; i < _gic_max_irq / 32U; i++) + { + rt_kprintf("0x%08x, ", + GIC_DIST_ENABLE_SET(_gic_table[index].dist_hw_base, + i * 32U)); + } + rt_kprintf("\n--- hw pending ---\n"); + for (i = 0U; i < _gic_max_irq / 32U; i++) + { + rt_kprintf("0x%08x, ", + GIC_DIST_PENDING_SET(_gic_table[index].dist_hw_base, + i * 32U)); + } + rt_kprintf("\n--- hw active ---\n"); + for (i = 0U; i < _gic_max_irq / 32U; i++) + { + rt_kprintf("0x%08x, ", + GIC_DIST_ACTIVE_SET(_gic_table[index].dist_hw_base, + i * 32U)); + } + rt_kprintf("\n"); +} + +long gic_dump(void) +{ + arm_gic_dump_type(0); + arm_gic_dump(0); + + return 0; +} +MSH_CMD_EXPORT(gic_dump, show gic status); diff --git a/libcpu/arm/cortex-a/gicv3.h b/libcpu/arm/cortex-a/gicv3.h new file mode 100644 index 0000000000..813a4f4c8d --- /dev/null +++ b/libcpu/arm/cortex-a/gicv3.h @@ -0,0 +1,194 @@ +/* + * Copyright (c) 2006-2021, RT-Thread Development Team + * + * SPDX-License-Identifier: Apache-2.0 + * + * Change Logs: + * Date Author Notes + * 2013-07-20 Bernard first version + */ + +#ifndef __GIC_V3_H__ +#define __GIC_V3_H__ + +#include <rthw.h> +#include <board.h> + +#define __get_gicv3_reg(CR, Rt) __asm__ volatile("MRC " CR \ + : "=r"(Rt) \ + : \ + : "memory") +#define __set_gicv3_reg(CR, Rt) __asm__ volatile("MCR " CR \ + : \ + : "r"(Rt) \ + : "memory") + + +/* AArch32 System register interface to GICv3 */ +#define ICC_IAR0 "p15, 0, %0, c12, c8, 0" +#define ICC_IAR1 "p15, 0, %0, c12, c12, 0" +#define ICC_EOIR0 "p15, 0, %0, c12, c8, 1" +#define ICC_EOIR1 "p15, 0, %0, c12, c12, 1" +#define ICC_HPPIR0 "p15, 0, %0, c12, c8, 2" +#define ICC_HPPIR1 "p15, 0, %0, c12, c12, 2" +#define ICC_BPR0 "p15, 0, %0, c12, c8, 3" +#define ICC_BPR1 "p15, 0, %0, c12, c12, 3" +#define ICC_DIR "p15, 0, %0, c12, c11, 1" +#define ICC_PMR "p15, 0, %0, c4, c6, 0" +#define ICC_RPR "p15, 0, %0, c12, c11, 3" +#define ICC_CTLR "p15, 0, %0, c12, c12, 4" +#define ICC_MCTLR "p15, 6, %0, c12, c12, 4" +#define ICC_SRE "p15, 0, %0, c12, c12, 5" +#define ICC_HSRE "p15, 4, %0, c12, c9, 5" +#define ICC_MSRE "p15, 6, %0, c12, c12, 5" +#define ICC_IGRPEN0 "p15, 0, %0, c12, c12, 6" +#define ICC_IGRPEN1 "p15, 0, %0, c12, c12, 7" +#define ICC_MGRPEN1 "p15, 6, %0, c12, c12, 7" + +#define __REG32(x) (*((volatile unsigned int*)((rt_uint32_t)x))) + +#define ROUTED_TO_ALL (1) +#define ROUTED_TO_SPEC (0) + +/** Macro to access the Distributor Control Register (GICD_CTLR) +*/ +#define GICD_CTLR_RWP (1<<31) +#define GICD_CTLR_E1NWF (1<<7) +#define GICD_CTLR_DS (1<<6) +#define GICD_CTLR_ARE_NS (1<<5) +#define GICD_CTLR_ARE_S (1<<4) +#define GICD_CTLR_ENGRP1S (1<<2) +#define GICD_CTLR_ENGRP1NS (1<<1) +#define GICD_CTLR_ENGRP0 (1<<0) + +/** Macro to access the Redistributor Control Register (GICR_CTLR) +*/ +#define GICR_CTLR_UWP (1<<31) +#define GICR_CTLR_DPG1S (1<<26) +#define GICR_CTLR_DPG1NS (1<<25) +#define GICR_CTLR_DPG0 (1<<24) +#define GICR_CTLR_RWP (1<<3) +#define GICR_CTLR_IR (1<<2) +#define GICR_CTLR_CES (1<<1) +#define GICR_CTLR_EnableLPI (1<<0) + +/** Macro to access the Generic Interrupt Controller Interface (GICC) +*/ +#define GIC_CPU_CTRL(hw_base) __REG32((hw_base) + 0x00U) +#define GIC_CPU_PRIMASK(hw_base) __REG32((hw_base) + 0x04U) +#define GIC_CPU_BINPOINT(hw_base) __REG32((hw_base) + 0x08U) +#define GIC_CPU_INTACK(hw_base) __REG32((hw_base) + 0x0cU) +#define GIC_CPU_EOI(hw_base) __REG32((hw_base) + 0x10U) +#define GIC_CPU_RUNNINGPRI(hw_base) __REG32((hw_base) + 0x14U) +#define GIC_CPU_HIGHPRI(hw_base) __REG32((hw_base) + 0x18U) +#define GIC_CPU_IIDR(hw_base) __REG32((hw_base) + 0xFCU) + +/** Macro to access the Generic Interrupt Controller Distributor (GICD) +*/ +#define GIC_DIST_CTRL(hw_base) __REG32((hw_base) + 0x000U) +#define GIC_DIST_TYPE(hw_base) __REG32((hw_base) + 0x004U) +#define GIC_DIST_IGROUP(hw_base, n) __REG32((hw_base) + 0x080U + ((n)/32U) * 4U) +#define GIC_DIST_ENABLE_SET(hw_base, n) __REG32((hw_base) + 0x100U + ((n)/32U) * 4U) +#define GIC_DIST_ENABLE_CLEAR(hw_base, n) __REG32((hw_base) + 0x180U + ((n)/32U) * 4U) +#define GIC_DIST_PENDING_SET(hw_base, n) __REG32((hw_base) + 0x200U + ((n)/32U) * 4U) +#define GIC_DIST_PENDING_CLEAR(hw_base, n) __REG32((hw_base) + 0x280U + ((n)/32U) * 4U) +#define GIC_DIST_ACTIVE_SET(hw_base, n) __REG32((hw_base) + 0x300U + ((n)/32U) * 4U) +#define GIC_DIST_ACTIVE_CLEAR(hw_base, n) __REG32((hw_base) + 0x380U + ((n)/32U) * 4U) +#define GIC_DIST_PRI(hw_base, n) __REG32((hw_base) + 0x400U + ((n)/4U) * 4U) +#define GIC_DIST_TARGET(hw_base, n) __REG32((hw_base) + 0x800U + ((n)/4U) * 4U) +#define GIC_DIST_CONFIG(hw_base, n) __REG32((hw_base) + 0xc00U + ((n)/16U) * 4U) +#define GIC_DIST_SOFTINT(hw_base) __REG32((hw_base) + 0xf00U) +#define GIC_DIST_CPENDSGI(hw_base, n) __REG32((hw_base) + 0xf10U + ((n)/4U) * 4U) +#define GIC_DIST_SPENDSGI(hw_base, n) __REG32((hw_base) + 0xf20U + ((n)/4U) * 4U) +#define GIC_DIST_ICPIDR2(hw_base) __REG32((hw_base) + 0xfe8U) +#define GIC_DIST_IROUTER_LOW(hw_base, n) __REG32((hw_base) + 0x6000U + (n)*8U) +#define GIC_DIST_IROUTER_HIGH(hw_base, n) __REG32((hw_base) + 0x6000U + (n)*8U + 4) + +/* SGI base address is at 64K offset from Redistributor base address */ +#define GIC_RSGI_OFFSET 0x10000 + +/** Macro to access the Generic Interrupt Controller Redistributor (GICD) +*/ +#define GIC_RDIST_CTRL(hw_base) __REG32((hw_base) + 0x000U) +#define GIC_RDIST_IIDR(hw_base) __REG32((hw_base) + 0x004U) +#define GIC_RDIST_TYPER(hw_base) __REG32((hw_base) + 0x008U) +#define GIC_RDIST_TSTATUSR(hw_base) __REG32((hw_base) + 0x010U) +#define GIC_RDIST_WAKER(hw_base) __REG32((hw_base) + 0x014U) +#define GIC_RDIST_SETLPIR(hw_base) __REG32((hw_base) + 0x040U) +#define GIC_RDIST_CLRLPIR(hw_base) __REG32((hw_base) + 0x048U) +#define GIC_RDIST_PROPBASER(hw_base) __REG32((hw_base) + 0x070U) +#define GIC_RDIST_PENDBASER(hw_base) __REG32((hw_base) + 0x078U) +#define GIC_RDIST_INVLPIR(hw_base) __REG32((hw_base) + 0x0A0U) +#define GIC_RDIST_INVALLR(hw_base) __REG32((hw_base) + 0x0B0U) +#define GIC_RDIST_SYNCR(hw_base) __REG32((hw_base) + 0x0C0U) + +#define GIC_RDISTSGI_IGROUPR0(hw_base, n) __REG32((hw_base) + GIC_RSGI_OFFSET + 0x080U + (n)*4U) +#define GIC_RDISTSGI_ISENABLER0(hw_base) __REG32((hw_base) + GIC_RSGI_OFFSET + 0x100U) +#define GIC_RDISTSGI_ICENABLER0(hw_base) __REG32((hw_base) + GIC_RSGI_OFFSET + 0x180U) +#define GIC_RDISTSGI_ISPENDR0(hw_base) __REG32((hw_base) + GIC_RSGI_OFFSET + 0x200U) +#define GIC_RDISTSGI_ICPENDR0(hw_base) __REG32((hw_base) + GIC_RSGI_OFFSET + 0x280U) +#define GIC_RDISTSGI_ISACTIVER0(hw_base) __REG32((hw_base) + GIC_RSGI_OFFSET + 0x300U) +#define GIC_RDISTSGI_ICACTIVER0(hw_base) __REG32((hw_base) + GIC_RSGI_OFFSET + 0x380U) +#define GIC_RDISTSGI_IPRIORITYR(hw_base, n) __REG32((hw_base) + GIC_RSGI_OFFSET + 0x400U + ((n) / 4U) * 4U) +#define GIC_RDISTSGI_ICFGR0(hw_base) __REG32((hw_base) + GIC_RSGI_OFFSET + 0xC00U) +#define GIC_RDISTSGI_ICFGR1(hw_base) __REG32((hw_base) + GIC_RSGI_OFFSET + 0xC04U) +#define GIC_RDISTSGI_IGRPMODR0(hw_base, n) __REG32((hw_base) + GIC_RSGI_OFFSET + 0xD00U + (n)*4) +#define GIC_RDISTSGI_NSACR(hw_base) __REG32((hw_base) + GIC_RSGI_OFFSET + 0xE00U) + +#define GIC_RSGI_AFF1_OFFSET 16 +#define GIC_RSGI_AFF2_OFFSET 32 +#define GIC_RSGI_AFF3_OFFSET 48 + +rt_uint32_t arm_gic_cpumask_to_affval(rt_uint32_t *cpu_mask, rt_uint32_t *cluster_id, rt_uint32_t *target_list); +rt_uint64_t get_main_cpu_affval(void); +int arm_gic_get_active_irq(rt_uint32_t index); +void arm_gic_ack(rt_uint32_t index, int irq); + +void arm_gic_mask(rt_uint32_t index, int irq); +void arm_gic_umask(rt_uint32_t index, int irq); + +rt_uint32_t arm_gic_get_pending_irq(rt_uint32_t index, int irq); +void arm_gic_set_pending_irq(rt_uint32_t index, int irq); +void arm_gic_clear_pending_irq(rt_uint32_t index, int irq); + +void arm_gic_set_configuration(rt_uint32_t index, int irq, uint32_t config); +rt_uint32_t arm_gic_get_configuration(rt_uint32_t index, int irq); + +void arm_gic_clear_active(rt_uint32_t index, int irq); + +void arm_gic_set_cpu(rt_uint32_t index, int irq, unsigned int cpumask); +rt_uint32_t arm_gic_get_target_cpu(rt_uint32_t index, int irq); + +void arm_gic_set_priority(rt_uint32_t index, int irq, rt_uint32_t priority); +rt_uint32_t arm_gic_get_priority(rt_uint32_t index, int irq); + +void arm_gic_set_interface_prior_mask(rt_uint32_t index, rt_uint32_t priority); +rt_uint32_t arm_gic_get_interface_prior_mask(rt_uint32_t index); + +void arm_gic_set_binary_point(rt_uint32_t index, rt_uint32_t binary_point); +rt_uint32_t arm_gic_get_binary_point(rt_uint32_t index); + +rt_uint32_t arm_gic_get_irq_status(rt_uint32_t index, int irq); + +void arm_gic_send_affinity_sgi(rt_uint32_t index, int irq, rt_uint32_t cpu_mask, rt_uint32_t routing_mode); +rt_uint32_t arm_gic_get_high_pending_irq(rt_uint32_t index); + +rt_uint32_t arm_gic_get_interface_id(rt_uint32_t index); + +void arm_gic_set_group(rt_uint32_t index, int irq, rt_uint32_t group); +rt_uint32_t arm_gic_get_group(rt_uint32_t index, int irq); + +int arm_gic_redist_address_set(rt_uint32_t index, rt_uint32_t redist_addr, rt_uint32_t cpu_id); +int arm_gic_cpu_interface_address_set(rt_uint32_t index, rt_uint32_t interface_addr, rt_uint32_t cpu_id); +int arm_gic_dist_init(rt_uint32_t index, rt_uint32_t dist_base, int irq_start); +int arm_gic_cpu_init(rt_uint32_t index); +int arm_gic_redist_init(rt_uint32_t index); + +void arm_gic_dump_type(rt_uint32_t index); +void arm_gic_dump(rt_uint32_t index); + +void arm_gic_set_system_register_enable_mask(rt_uint32_t index, rt_uint32_t value); +rt_uint32_t arm_gic_get_system_register_enable_mask(rt_uint32_t index); +void arm_gic_secondary_cpu_init(void); +#endif + diff --git a/libcpu/arm/cortex-a/gtimer.c b/libcpu/arm/cortex-a/gtimer.c new file mode 100644 index 0000000000..b35acc6e6f --- /dev/null +++ b/libcpu/arm/cortex-a/gtimer.c @@ -0,0 +1,179 @@ +/* + * Copyright (c) 2006-2021, RT-Thread Development Team + * + * SPDX-License-Identifier: Apache-2.0 + * + * Change Logs: + * Date Author Notes + * 2021-03-30 huijie.feng first version + */ + +#include "cp15.h" +#include <rtdef.h> + +/** Set CNTFRQ + * This function assigns the given value to PL1 Physical Timer Counter Frequency Register (CNTFRQ). + * @param value: CNTFRQ Register value to set + */ +static inline void __set_cntfrq(rt_uint32_t value) +{ + __set_cp(15, 0, value, 14, 0, 0); +} + +/** Get CNTFRQ + * This function returns the value of the PL1 Physical Timer Counter Frequency Register (CNTFRQ). + * return CNTFRQ Register value + */ +static inline rt_uint32_t __get_cntfrq(void) +{ + rt_uint32_t result; + __get_cp(15, 0, result, 14, 0 , 0); + return result; +} + +/** Set CNTP_TVAL + * This function assigns the given value to PL1 Physical Timer Value Register (CNTP_TVAL). + * param value: CNTP_TVAL Register value to set + */ +static inline void __set_cntp_tval(rt_uint32_t value) +{ + __set_cp(15, 0, value, 14, 2, 0); +} + +/** Get CNTP_TVAL + * This function returns the value of the PL1 Physical Timer Value Register (CNTP_TVAL). + * return CNTP_TVAL Register value + */ +static inline rt_uint32_t __get_cntp_tval(void) +{ + rt_uint32_t result; + __get_cp(15, 0, result, 14, 2, 0); + return result; +} + +/** Get CNTPCT + * This function returns the value of the 64 bits PL1 Physical Count Register (CNTPCT). + * return CNTPCT Register value + */ +static inline rt_uint64_t __get_cntpct(void) +{ + rt_uint64_t result; + __get_cp64(15, 0, result, 14); + return result; +} + +/** Set CNTP_CVAL + * This function assigns the given value to 64bits PL1 Physical Timer CompareValue Register (CNTP_CVAL). + * param value: CNTP_CVAL Register value to set +*/ +static inline void __set_cntp_cval(rt_uint64_t value) +{ + __set_cp64(15, 2, value, 14); +} + +/** Get CNTP_CVAL + * This function returns the value of the 64 bits PL1 Physical Timer CompareValue Register (CNTP_CVAL). + * return CNTP_CVAL Register value + */ +static inline rt_uint64_t __get_cntp_cval(void) +{ + rt_uint64_t result; + __get_cp64(15, 2, result, 14); + return result; +} + +/** Set CNTP_CTL + * This function assigns the given value to PL1 Physical Timer Control Register (CNTP_CTL). + * param value: CNTP_CTL Register value to set + */ +static inline void __set_cntp_ctl(uint32_t value) +{ + __set_cp(15, 0, value, 14, 2, 1); +} + +/** Get CNTP_CTL register + * return CNTP_CTL Register value + */ +static inline rt_uint32_t __get_cntp_ctl(void) +{ + rt_uint32_t result; + __get_cp(15, 0, result, 14, 2, 1); + return result; +} + +/** Configures the frequency the timer shall run at. + * param value The timer frequency in Hz. + */ +void gtimer_set_counter_frequency(rt_uint32_t value) +{ + __set_cntfrq(value); + __asm__ volatile ("isb 0xF":::"memory"); +} + +/** Get the frequency the timer shall run at. + * return timer frequency in Hz. + */ +rt_uint32_t gtimer_get_counter_frequency(void) +{ + return(__get_cntfrq()); +} + +/** Sets the reset value of the timer. + * param value: The value the timer is loaded with. + */ +void gtimer_set_load_value(rt_uint32_t value) +{ + __set_cntp_tval(value); + __asm__ volatile ("isb 0xF":::"memory"); +} + +/** Get the current counter value. + * return Current counter value. + */ +rt_uint32_t gtimer_get_current_value(void) +{ + return(__get_cntp_tval()); +} + +/** Get the current physical counter value. + * return Current physical counter value. + */ +rt_uint64_t gtimer_get_current_physical_value(void) +{ + return(__get_cntpct()); +} + +/** Set the physical compare value. + * param value: New physical timer compare value. + */ +void gtimer_set_physical_compare_value(rt_uint64_t value) +{ + __set_cntp_cval(value); + __asm__ volatile ("isb 0xF":::"memory"); +} + +/** Get the physical compare value. + * return Physical compare value. + */ +rt_uint64_t gtimer_get_physical_compare_value(void) +{ + return(__get_cntp_cval()); +} + +/** Configure the timer by setting the control value. + * param value: New timer control value. + */ +void gtimer_set_control(rt_uint32_t value) +{ + __set_cntp_ctl(value); + __asm__ volatile ("isb 0xF":::"memory"); +} + +/** Get the control value. + * return Control value. + */ +rt_uint32_t gtimer_get_control(void) +{ + return(__get_cntp_ctl()); +} + diff --git a/libcpu/arm/cortex-a/gtimer.h b/libcpu/arm/cortex-a/gtimer.h new file mode 100644 index 0000000000..ec5d54127e --- /dev/null +++ b/libcpu/arm/cortex-a/gtimer.h @@ -0,0 +1,27 @@ +/* + * Copyright (c) 2006-2021, RT-Thread Development Team + * + * SPDX-License-Identifier: Apache-2.0 + * + * Change Logs: + * Date Author Notes + * 2021-03-30 huijie.feng first version + */ + +#ifndef __GTIMER_H__ +#define __GTIMER_H__ + +#include <rtdef.h> + +void gtimer_set_counter_frequency(rt_uint32_t value); +rt_uint32_t gtimer_get_counter_frequency(void); +void gtimer_set_load_value(rt_uint32_t value); +rt_uint32_t gtimer_get_current_value(void); +rt_uint64_t gtimer_get_current_physical_value(void); +void gtimer_set_physical_compare_value(rt_uint64_t value); +rt_uint64_t gtimer_get_physical_compare_value(void); +void gtimer_set_control(rt_uint32_t value); +rt_uint32_t gtimer_get_control(void); + +#endif + diff --git a/libcpu/arm/cortex-a/interrupt.c b/libcpu/arm/cortex-a/interrupt.c index b7a70719a9..474a23fee1 100644 --- a/libcpu/arm/cortex-a/interrupt.c +++ b/libcpu/arm/cortex-a/interrupt.c @@ -1,5 +1,5 @@ /* - * Copyright (c) 2006-2018, RT-Thread Development Team + * Copyright (c) 2006-2021, RT-Thread Development Team * * SPDX-License-Identifier: Apache-2.0 * @@ -12,8 +12,12 @@ #include <rthw.h> #include <rtthread.h> #include "interrupt.h" -#include "gic.h" +#ifdef RT_USING_GIC_V2 +#include "gic.h" +#else +#include "gicv3.h" +#endif /* exception and interrupt handler table */ struct rt_irq_desc isr_table[MAX_HANDLERS]; @@ -34,6 +38,7 @@ void rt_hw_vector_init(void) rt_cpu_vector_set_base((unsigned int)&system_vectors); } +#ifdef RT_USING_GIC_V2 /** * This function will initialize hardware interrupt */ @@ -58,6 +63,33 @@ void rt_hw_interrupt_init(void) arm_gic_dist_init(0, gic_dist_base, gic_irq_start); arm_gic_cpu_init(0, gic_cpu_base); } +#else +/** + * This function will initialize hardware interrupt + * Called by the primary cpu(cpu0) + */ +void rt_hw_interrupt_init(void) +{ + rt_uint32_t gic_dist_base; + rt_uint32_t gic_irq_start; + + /* initialize vector table */ + rt_hw_vector_init(); + + /* initialize exceptions table */ + rt_memset(isr_table, 0x00, sizeof(isr_table)); + + /* initialize ARM GIC */ + gic_dist_base = platform_get_gic_dist_base(); + gic_irq_start = GIC_IRQ_START; + + arm_gic_dist_init(0, gic_dist_base, gic_irq_start); + + arm_gic_cpu_init(0); + arm_gic_redist_init(0); +} + +#endif /** * This function will mask a interrupt. @@ -83,7 +115,7 @@ void rt_hw_interrupt_umask(int vector) */ int rt_hw_interrupt_get_irq(void) { - return arm_gic_get_active_irq(0) & GIC_ACK_INTID_MASK; + return arm_gic_get_active_irq(0); } /** @@ -94,6 +126,150 @@ void rt_hw_interrupt_ack(int vector) { arm_gic_ack(0, vector); } + +/** + * This function set interrupt CPU targets. + * @param vector: the interrupt number + * cpu_mask: target cpus mask, one bit for one core + */ +void rt_hw_interrupt_set_target_cpus(int vector, unsigned int cpu_mask) +{ + arm_gic_set_cpu(0, vector, cpu_mask); +} + +/** + * This function get interrupt CPU targets. + * @param vector: the interrupt number + * @return target cpus mask, one bit for one core + */ +unsigned int rt_hw_interrupt_get_target_cpus(int vector) +{ + return arm_gic_get_target_cpu(0, vector); +} + +/** + * This function set interrupt triger mode. + * @param vector: the interrupt number + * mode: interrupt triger mode; 0: level triger, 1: edge triger + */ +void rt_hw_interrupt_set_triger_mode(int vector, unsigned int mode) +{ + arm_gic_set_configuration(0, vector, mode); +} + +/** + * This function get interrupt triger mode. + * @param vector: the interrupt number + * @return interrupt triger mode; 0: level triger, 1: edge triger + */ +unsigned int rt_hw_interrupt_get_triger_mode(int vector) +{ + return arm_gic_get_configuration(0, vector); +} + +/** + * This function set interrupt pending flag. + * @param vector: the interrupt number + */ +void rt_hw_interrupt_set_pending(int vector) +{ + arm_gic_set_pending_irq(0, vector); +} + +/** + * This function get interrupt pending flag. + * @param vector: the interrupt number + * @return interrupt pending flag, 0: not pending; 1: pending + */ +unsigned int rt_hw_interrupt_get_pending(int vector) +{ + return arm_gic_get_pending_irq(0, vector); +} + +/** + * This function clear interrupt pending flag. + * @param vector: the interrupt number + */ +void rt_hw_interrupt_clear_pending(int vector) +{ + arm_gic_clear_pending_irq(0, vector); +} + +/** + * This function set interrupt priority value. + * @param vector: the interrupt number + * priority: the priority of interrupt to set + */ +void rt_hw_interrupt_set_priority(int vector, unsigned int priority) +{ + arm_gic_set_priority(0, vector, priority); +} + +/** + * This function get interrupt priority. + * @param vector: the interrupt number + * @return interrupt priority value + */ +unsigned int rt_hw_interrupt_get_priority(int vector) +{ + return arm_gic_get_priority(0, vector); +} + +/** + * This function set priority masking threshold. + * @param priority: priority masking threshold + */ +void rt_hw_interrupt_set_priority_mask(unsigned int priority) +{ + arm_gic_set_interface_prior_mask(0, priority); +} + +/** + * This function get priority masking threshold. + * @param none + * @return priority masking threshold + */ +unsigned int rt_hw_interrupt_get_priority_mask(void) +{ + return arm_gic_get_interface_prior_mask(0); +} + +/** + * This function set priority grouping field split point. + * @param bits: priority grouping field split point + * @return 0: success; -1: failed + */ +int rt_hw_interrupt_set_prior_group_bits(unsigned int bits) +{ + int status; + + if (bits < 8) + { + arm_gic_set_binary_point(0, (7 - bits)); + status = 0; + } + else + { + status = -1; + } + + return (status); +} + +/** + * This function get priority grouping field split point. + * @param none + * @return priority grouping field split point + */ +unsigned int rt_hw_interrupt_get_prior_group_bits(void) +{ + unsigned int bp; + + bp = arm_gic_get_binary_point(0) & 0x07; + + return (7 - bp); +} + /** * This function will install a interrupt service routine to a interrupt. * @param vector the interrupt number @@ -101,7 +277,7 @@ void rt_hw_interrupt_ack(int vector) * @param old_handler the old interrupt service routine */ rt_isr_handler_t rt_hw_interrupt_install(int vector, rt_isr_handler_t handler, - void *param, const char *name) + void *param, const char *name) { rt_isr_handler_t old_handler = RT_NULL; @@ -121,3 +297,21 @@ rt_isr_handler_t rt_hw_interrupt_install(int vector, rt_isr_handler_t handler, return old_handler; } + +#ifdef RT_USING_SMP +void rt_hw_ipi_send(int ipi_vector, unsigned int cpu_mask) +{ +#ifdef RT_USING_GIC_V2 + arm_gic_send_sgi(0, ipi_vector, cpu_mask, 0); +#else + arm_gic_send_affinity_sgi(0, ipi_vector, cpu_mask, ROUTED_TO_SPEC); +#endif +} + +void rt_hw_ipi_handler_install(int ipi_vector, rt_isr_handler_t ipi_isr_handler) +{ + /* note: ipi_vector maybe different with irq_vector */ + rt_hw_interrupt_install(ipi_vector, ipi_isr_handler, 0, "IPI_HANDLER"); +} +#endif + diff --git a/libcpu/arm/cortex-a/interrupt.h b/libcpu/arm/cortex-a/interrupt.h index 442187edee..dda6c5534a 100644 --- a/libcpu/arm/cortex-a/interrupt.h +++ b/libcpu/arm/cortex-a/interrupt.h @@ -1,5 +1,5 @@ /* - * Copyright (c) 2006-2018, RT-Thread Development Team + * Copyright (c) 2006-2021, RT-Thread Development Team * * SPDX-License-Identifier: Apache-2.0 * @@ -17,9 +17,10 @@ #define INT_IRQ 0x00 #define INT_FIQ 0x01 -void rt_hw_vector_init(void); +#define IRQ_MODE_TRIG_LEVEL (0x00) /* Trigger: level triggered interrupt */ +#define IRQ_MODE_TRIG_EDGE (0x01) /* Trigger: edge triggered interrupt */ -void rt_hw_interrupt_control(int vector, int priority, int route); +void rt_hw_vector_init(void); void rt_hw_interrupt_init(void); void rt_hw_interrupt_mask(int vector); @@ -28,7 +29,32 @@ void rt_hw_interrupt_umask(int vector); int rt_hw_interrupt_get_irq(void); void rt_hw_interrupt_ack(int vector); +void rt_hw_interrupt_set_target_cpus(int vector, unsigned int cpu_mask); +unsigned int rt_hw_interrupt_get_target_cpus(int vector); + +void rt_hw_interrupt_set_triger_mode(int vector, unsigned int mode); +unsigned int rt_hw_interrupt_get_triger_mode(int vector); + +void rt_hw_interrupt_set_pending(int vector); +unsigned int rt_hw_interrupt_get_pending(int vector); +void rt_hw_interrupt_clear_pending(int vector); + +void rt_hw_interrupt_set_priority(int vector, unsigned int priority); +unsigned int rt_hw_interrupt_get_priority(int vector); + +void rt_hw_interrupt_set_priority_mask(unsigned int priority); +unsigned int rt_hw_interrupt_get_priority_mask(void); + +int rt_hw_interrupt_set_prior_group_bits(unsigned int bits); +unsigned int rt_hw_interrupt_get_prior_group_bits(void); + rt_isr_handler_t rt_hw_interrupt_install(int vector, rt_isr_handler_t handler, void *param, const char *name); +#ifdef RT_USING_SMP +void rt_hw_ipi_send(int ipi_vector, unsigned int cpu_mask); +void rt_hw_ipi_handler_install(int ipi_vector, rt_isr_handler_t ipi_isr_handler); #endif + +#endif + diff --git a/libcpu/arm/cortex-a/mmu.c b/libcpu/arm/cortex-a/mmu.c index 1260f41fe5..243fe19a0a 100644 --- a/libcpu/arm/cortex-a/mmu.c +++ b/libcpu/arm/cortex-a/mmu.c @@ -1,5 +1,5 @@ /* - * Copyright (c) 2006-2018, RT-Thread Development Team + * Copyright (c) 2006-2021, RT-Thread Development Team * * SPDX-License-Identifier: Apache-2.0 * diff --git a/libcpu/arm/cortex-a/mmu.h b/libcpu/arm/cortex-a/mmu.h index fbce6df935..5cc60a774d 100644 --- a/libcpu/arm/cortex-a/mmu.h +++ b/libcpu/arm/cortex-a/mmu.h @@ -1,5 +1,5 @@ /* - * Copyright (c) 2006-2018, RT-Thread Development Team + * Copyright (c) 2006-2021, RT-Thread Development Team * * SPDX-License-Identifier: Apache-2.0 * diff --git a/libcpu/arm/cortex-a/pmu.c b/libcpu/arm/cortex-a/pmu.c index 8ffc1dede6..2b9165cc8b 100644 --- a/libcpu/arm/cortex-a/pmu.c +++ b/libcpu/arm/cortex-a/pmu.c @@ -1,5 +1,5 @@ /* - * Copyright (c) 2006-2018, RT-Thread Development Team + * Copyright (c) 2006-2021, RT-Thread Development Team * * SPDX-License-Identifier: Apache-2.0 * diff --git a/libcpu/arm/cortex-a/pmu.h b/libcpu/arm/cortex-a/pmu.h index fb8390133d..64a74b5d39 100644 --- a/libcpu/arm/cortex-a/pmu.h +++ b/libcpu/arm/cortex-a/pmu.h @@ -1,5 +1,5 @@ /* - * Copyright (c) 2006-2018, RT-Thread Development Team + * Copyright (c) 2006-2021, RT-Thread Development Team * * SPDX-License-Identifier: Apache-2.0 * diff --git a/libcpu/arm/cortex-a/stack.c b/libcpu/arm/cortex-a/stack.c index 07d795ab5b..e68b324867 100644 --- a/libcpu/arm/cortex-a/stack.c +++ b/libcpu/arm/cortex-a/stack.c @@ -1,5 +1,5 @@ /* - * Copyright (c) 2006-2018, RT-Thread Development Team + * Copyright (c) 2006-2021, RT-Thread Development Team * * SPDX-License-Identifier: Apache-2.0 * diff --git a/libcpu/arm/cortex-a/start_gcc.S b/libcpu/arm/cortex-a/start_gcc.S index 2e99db7218..bd4bc84604 100644 --- a/libcpu/arm/cortex-a/start_gcc.S +++ b/libcpu/arm/cortex-a/start_gcc.S @@ -22,20 +22,26 @@ .equ I_Bit, 0x80 @ when I bit is set, IRQ is disabled .equ F_Bit, 0x40 @ when F bit is set, FIQ is disabled -#ifdef RT_USING_FPU .equ UND_Stack_Size, 0x00000400 -#else -.equ UND_Stack_Size, 0x00000000 -#endif .equ SVC_Stack_Size, 0x00000400 -.equ ABT_Stack_Size, 0x00000000 +.equ ABT_Stack_Size, 0x00000400 .equ RT_FIQ_STACK_PGSZ, 0x00000000 .equ RT_IRQ_STACK_PGSZ, 0x00000800 .equ USR_Stack_Size, 0x00000400 +.equ SUB_UND_Stack_Size, 0x00000400 +.equ SUB_SVC_Stack_Size, 0x00000400 +.equ SUB_ABT_Stack_Size, 0x00000400 +.equ SUB_RT_FIQ_STACK_PGSZ, 0x00000000 +.equ SUB_RT_IRQ_STACK_PGSZ, 0x00000400 +.equ SUB_USR_Stack_Size, 0x00000400 + #define ISR_Stack_Size (UND_Stack_Size + SVC_Stack_Size + ABT_Stack_Size + \ RT_FIQ_STACK_PGSZ + RT_IRQ_STACK_PGSZ) +#define SUB_ISR_Stack_Size (SUB_UND_Stack_Size + SUB_SVC_Stack_Size + SUB_ABT_Stack_Size + \ + SUB_RT_FIQ_STACK_PGSZ + SUB_RT_IRQ_STACK_PGSZ) + .section .data.share.isr /* stack */ .globl stack_start @@ -82,9 +88,40 @@ continue: /* disable the data alignment check */ mrc p15, 0, r1, c1, c0, 0 - bic r1, #(1<<1) + bic r1, #(1<<0) /* Disable MMU */ + bic r1, #(1<<1) /* Disable Alignment fault checking */ + bic r1, #(1<<2) /* Disable data cache */ + bic r1, #(1<<11) /* Disable program flow prediction */ + bic r1, #(1<<12) /* Disable instruction cache */ + bic r1, #(3<<19) /* bit[20:19] must be zero */ mcr p15, 0, r1, c1, c0, 0 + @ get cpu id, and subtract the offset from the stacks base address + bl rt_hw_cpu_id + mov r5, r0 + + cmp r5, #0 @ cpu id == 0 + beq normal_setup + + @ cpu id > 0, stop or wait +#ifdef RT_SMP_AUTO_BOOT + ldr r0, =secondary_cpu_entry + mov r1, #0 + str r1, [r0] /* clean secondary_cpu_entry */ +#endif /* RT_SMP_AUTO_BOOT */ + +secondary_loop: + @ cpu core 1 goes into sleep until core 0 wakeup it + wfe +#ifdef RT_SMP_AUTO_BOOT + ldr r1, =secondary_cpu_entry + ldr r0, [r1] + cmp r0, #0 + blxne r0 /* if(secondary_cpu_entry) secondary_cpu_entry(); */ +#endif /* RT_SMP_AUTO_BOOT */ + b secondary_loop + +normal_setup: /* setup stack */ bl stack_setup @@ -105,6 +142,11 @@ bss_loop: mcr p15, 0, r1, c1, c0, 1 //enable smp #endif + /* enable branch prediction */ + mrc p15, 0, r0, c1, c0, 0 + orr r0, r0, #(1<<11) + mcr p15, 0, r0, c1, c0, 0 + /* initialize the mmu table and enable mmu */ ldr r0, =platform_mem_desc ldr r1, =platform_mem_desc_size @@ -137,6 +179,7 @@ stack_setup: @ Set the startup stack for svc mov sp, r0 + sub r0, r0, #SVC_Stack_Size @ Enter Undefined Instruction Mode and set its Stack Pointer msr cpsr_c, #Mode_UND|I_Bit|F_Bit @@ -378,16 +421,6 @@ vector_resv: b . #ifdef RT_USING_SMP -.global set_secondary_cpu_boot_address -set_secondary_cpu_boot_address: - ldr r0, =secondary_cpu_start - - mvn r1, #0 //0xffffffff - ldr r2, =0x10000034 - str r1, [r2] - str r0, [r2, #-4] - mov pc, lr - .global secondary_cpu_start secondary_cpu_start: @@ -405,38 +438,52 @@ secondary_cpu_start: bic r0, #(1<<13) mcr p15, 0, r0, c1, c0, 0 -#ifdef RT_USING_FPU + /* enable branch prediction */ + mrc p15, 0, r0, c1, c0, 0 + orr r0, r0, #(1<<11) + mcr p15, 0, r0, c1, c0, 0 + + @ get cpu id, and subtract the offset from the stacks base address + bl rt_hw_cpu_id + sub r5, r0, #1 + + ldr r0, =SUB_ISR_Stack_Size + mul r0, r0, r5 @r0 = SUB_ISR_Stack_Size * (cpuid - 1) + ldr r1, =sub_stack_top + sub r0, r1, r0 @r0 = sub_stack_top - (SUB_ISR_Stack_Size * (cpuid - 1)) + + cps #Mode_SVC + mov sp, r0 + sub r0, r0, #SUB_SVC_Stack_Size + cps #Mode_UND - ldr sp, =und_stack_2_limit -#endif + mov sp, r0 + sub r0, r0, #SUB_UND_Stack_Size - cps #Mode_IRQ - ldr sp, =irq_stack_2_limit + cps #Mode_ABT + mov sp, r0 + sub r0, r0, #SUB_ABT_Stack_Size cps #Mode_FIQ - ldr sp, =irq_stack_2_limit + mov sp, r0 + sub r0, r0, #SUB_RT_FIQ_STACK_PGSZ + + cps #Mode_IRQ + mov sp, r0 + sub r0, r0, #SUB_RT_IRQ_STACK_PGSZ cps #Mode_SVC - ldr sp, =svc_stack_2_limit /* initialize the mmu table and enable mmu */ bl rt_hw_mmu_init b secondary_cpu_c_start -#endif .bss .align 2 //align to 2~2=4 -svc_stack_2: - .space (1 << 10) -svc_stack_2_limit: -irq_stack_2: - .space (1 << 10) -irq_stack_2_limit: +sub_stack_start: + .space (SUB_ISR_Stack_Size * (RT_CPUS_NR-1)) +sub_stack_top: -#ifdef RT_USING_FPU -und_stack_2: - .space (1 << 10) -und_stack_2_limit: #endif diff --git a/libcpu/arm/cortex-a/trap.c b/libcpu/arm/cortex-a/trap.c index dc232a46ee..3faa136677 100644 --- a/libcpu/arm/cortex-a/trap.c +++ b/libcpu/arm/cortex-a/trap.c @@ -1,5 +1,5 @@ /* - * Copyright (c) 2006-2018, RT-Thread Development Team + * Copyright (c) 2006-2021, RT-Thread Development Team * * SPDX-License-Identifier: Apache-2.0 * @@ -47,30 +47,24 @@ void rt_hw_trap_undef(struct rt_hw_exp_stack *regs) { #ifdef RT_USING_FPU { - uint32_t ins; + uint32_t val; uint32_t addr; if (regs->cpsr & (1 << 5)) { /* thumb mode */ addr = regs->pc - 2; - ins = (uint32_t)*(uint16_t*)addr; - if ((ins & (3 << 11)) != 0) - { - /* 32 bit ins */ - ins <<= 16; - ins += *(uint16_t*)(addr + 2); - } } else { addr = regs->pc - 4; - ins = *(uint32_t*)addr; } - if ((ins & 0xe00) == 0xa00) + asm volatile ("vmrs %0, fpexc" : "=r"(val)::"memory"); + + if (!(val & 0x40000000)) { /* float ins */ - uint32_t val = (1U << 30); + val = (1U << 30); asm volatile ("vmsr fpexc, %0"::"r"(val):"memory"); regs->pc = addr; diff --git a/libcpu/arm/cortex-m0/cpuport.c b/libcpu/arm/cortex-m0/cpuport.c index 19aec42230..49e15bf339 100644 --- a/libcpu/arm/cortex-m0/cpuport.c +++ b/libcpu/arm/cortex-m0/cpuport.c @@ -1,5 +1,5 @@ /* - * Copyright (c) 2006-2018, RT-Thread Development Team + * Copyright (c) 2006-2021, RT-Thread Development Team * * SPDX-License-Identifier: Apache-2.0 * diff --git a/libcpu/arm/cortex-m23/SConscript b/libcpu/arm/cortex-m23/SConscript index 28af7ba651..a4535c03ea 100644 --- a/libcpu/arm/cortex-m23/SConscript +++ b/libcpu/arm/cortex-m23/SConscript @@ -10,6 +10,8 @@ CPPPATH = [cwd] if rtconfig.PLATFORM == 'armcc': src += Glob('*_rvds.S') +elif rtconfig.PLATFORM == 'armclang': + src += Glob('*_rvds.S') if rtconfig.PLATFORM == 'gcc': src += Glob('*_init.S') diff --git a/libcpu/arm/cortex-m23/cpuport.c b/libcpu/arm/cortex-m23/cpuport.c index 842802c866..d8f9b12c2c 100644 --- a/libcpu/arm/cortex-m23/cpuport.c +++ b/libcpu/arm/cortex-m23/cpuport.c @@ -1,5 +1,5 @@ /* - * Copyright (c) 2006-2019, RT-Thread Development Team + * Copyright (c) 2006-2021, RT-Thread Development Team * * SPDX-License-Identifier: Apache-2.0 * diff --git a/libcpu/arm/cortex-m3/cpuport.c b/libcpu/arm/cortex-m3/cpuport.c index b6c4c9743c..19c33bd7c9 100644 --- a/libcpu/arm/cortex-m3/cpuport.c +++ b/libcpu/arm/cortex-m3/cpuport.c @@ -1,5 +1,5 @@ /* - * Copyright (c) 2006-2018, RT-Thread Development Team + * Copyright (c) 2006-2021, RT-Thread Development Team * * SPDX-License-Identifier: Apache-2.0 * diff --git a/libcpu/arm/cortex-m33/cpuport.c b/libcpu/arm/cortex-m33/cpuport.c index 42b5798507..928689d9c8 100644 --- a/libcpu/arm/cortex-m33/cpuport.c +++ b/libcpu/arm/cortex-m33/cpuport.c @@ -1,5 +1,5 @@ /* - * Copyright (c) 2006-2018, RT-Thread Development Team + * Copyright (c) 2006-2021, RT-Thread Development Team * * SPDX-License-Identifier: Apache-2.0 * @@ -457,7 +457,7 @@ RT_WEAK void rt_hw_cpu_reset(void) * @return return the index of the first bit set. If value is 0, then this function * shall return 0. */ -#if defined(__CC_ARM) +#if defined(__CC_ARM) __asm int __rt_ffs(int value) { CMP r0, #0x00 @@ -473,17 +473,13 @@ exit #elif defined(__CLANG_ARM) int __rt_ffs(int value) { - __asm volatile( - "CMP r0, #0x00 \n" - "BEQ 1f \n" + if (value == 0) return value; + __asm volatile( "RBIT r0, r0 \n" "CLZ r0, r0 \n" "ADDS r0, r0, #0x01 \n" - "1: \n" - "BX lr \n" - : "=r"(value) : "r"(value) ); diff --git a/libcpu/arm/cortex-m33/trustzone.c b/libcpu/arm/cortex-m33/trustzone.c index 86654a7199..f49f0c24f8 100644 --- a/libcpu/arm/cortex-m33/trustzone.c +++ b/libcpu/arm/cortex-m33/trustzone.c @@ -1,5 +1,5 @@ /* - * Copyright (c) 2006-2019, RT-Thread Development Team + * Copyright (c) 2006-2021, RT-Thread Development Team * * SPDX-License-Identifier: Apache-2.0 * @@ -10,11 +10,19 @@ #include <rtthread.h> +#ifdef ARM_CM33_ENABLE_TRUSTZONE extern void TZ_InitContextSystem_S(void); extern rt_uint32_t TZ_AllocModuleContext_S (rt_uint32_t module); extern rt_uint32_t TZ_FreeModuleContext_S(rt_uint32_t id); extern rt_uint32_t TZ_LoadContext_S(rt_uint32_t id); extern rt_uint32_t TZ_StoreContext_S(rt_uint32_t id); +#else +void TZ_InitContextSystem_S(void){} +rt_uint32_t TZ_AllocModuleContext_S (rt_uint32_t module){return 0;} +rt_uint32_t TZ_FreeModuleContext_S(rt_uint32_t id) {return 0;} +rt_uint32_t TZ_LoadContext_S(rt_uint32_t id){return 0;}; +rt_uint32_t TZ_StoreContext_S(rt_uint32_t id){return 0;}; +#endif extern int tzcall(int id, rt_ubase_t arg0, rt_ubase_t arg1, rt_ubase_t arg2); #define TZ_INIT_CONTEXT_ID (0x1001) @@ -23,7 +31,7 @@ extern int tzcall(int id, rt_ubase_t arg0, rt_ubase_t arg1, rt_ubase_t arg2); rt_ubase_t rt_trustzone_current_context; -#if defined(__CC_ARM) +#if defined(__CC_ARM) static __inline rt_uint32_t __get_IPSR(void) { register rt_uint32_t result __asm("ipsr"); @@ -70,7 +78,7 @@ rt_err_t rt_trustzone_enter(rt_ubase_t module) rt_trustzone_init(); if (tzcall(TZ_ALLOC_CONTEXT_ID, module, 0, 0)) { - return RT_EOK; + return RT_EOK; } return -RT_ERROR; } diff --git a/libcpu/arm/cortex-m4/SConscript b/libcpu/arm/cortex-m4/SConscript index 28af7ba651..73101dbcf3 100644 --- a/libcpu/arm/cortex-m4/SConscript +++ b/libcpu/arm/cortex-m4/SConscript @@ -11,6 +11,9 @@ CPPPATH = [cwd] if rtconfig.PLATFORM == 'armcc': src += Glob('*_rvds.S') +if rtconfig.PLATFORM == 'armclang': + src += Glob('*_rvds.S') + if rtconfig.PLATFORM == 'gcc': src += Glob('*_init.S') src += Glob('*_gcc.S') diff --git a/libcpu/arm/cortex-m4/cpuport.c b/libcpu/arm/cortex-m4/cpuport.c index 2e47832259..dbc42d21cf 100644 --- a/libcpu/arm/cortex-m4/cpuport.c +++ b/libcpu/arm/cortex-m4/cpuport.c @@ -1,5 +1,5 @@ /* - * Copyright (c) 2006-2018, RT-Thread Development Team + * Copyright (c) 2006-2021, RT-Thread Development Team * * SPDX-License-Identifier: Apache-2.0 * @@ -454,7 +454,7 @@ RT_WEAK void rt_hw_cpu_reset(void) * @return return the index of the first bit set. If value is 0, then this function * shall return 0. */ -#if defined(__CC_ARM) +#if defined(__CC_ARM) __asm int __rt_ffs(int value) { CMP r0, #0x00 diff --git a/libcpu/arm/cortex-m7/cpu_cache.c b/libcpu/arm/cortex-m7/cpu_cache.c index 350b819c00..417558e285 100644 --- a/libcpu/arm/cortex-m7/cpu_cache.c +++ b/libcpu/arm/cortex-m7/cpu_cache.c @@ -1,5 +1,5 @@ /* - * Copyright (c) 2006-2018, RT-Thread Development Team + * Copyright (c) 2006-2021, RT-Thread Development Team * * SPDX-License-Identifier: Apache-2.0 * @@ -13,7 +13,7 @@ #include <rtdef.h> #include <board.h> -/* The L1-caches on all Cortex®-M7s are divided into lines of 32 bytes. */ +/* The L1-caches on all Cortex®-M7s are divided into lines of 32 bytes. */ #define L1CACHE_LINESIZE_BYTE (32) void rt_hw_cpu_icache_enable(void) diff --git a/libcpu/arm/cortex-m7/cpuport.c b/libcpu/arm/cortex-m7/cpuport.c index aeb9f14ac5..dbc42d21cf 100644 --- a/libcpu/arm/cortex-m7/cpuport.c +++ b/libcpu/arm/cortex-m7/cpuport.c @@ -1,5 +1,5 @@ /* - * Copyright (c) 2006-2018, RT-Thread Development Team + * Copyright (c) 2006-2021, RT-Thread Development Team * * SPDX-License-Identifier: Apache-2.0 * diff --git a/libcpu/arm/cortex-r4/armv7.h b/libcpu/arm/cortex-r4/armv7.h index 3adcb92c5d..d29b41a213 100644 --- a/libcpu/arm/cortex-r4/armv7.h +++ b/libcpu/arm/cortex-r4/armv7.h @@ -1,5 +1,5 @@ /* - * Copyright (c) 2006-2018, RT-Thread Development Team + * Copyright (c) 2006-2021, RT-Thread Development Team * * SPDX-License-Identifier: Apache-2.0 * @@ -16,23 +16,23 @@ /* the exception stack without VFP registers */ struct rt_hw_exp_stack { - unsigned long r0; - unsigned long r1; - unsigned long r2; - unsigned long r3; - unsigned long r4; - unsigned long r5; - unsigned long r6; - unsigned long r7; - unsigned long r8; - unsigned long r9; - unsigned long r10; - unsigned long fp; - unsigned long ip; - unsigned long sp; - unsigned long lr; - unsigned long pc; - unsigned long cpsr; + unsigned long r0; + unsigned long r1; + unsigned long r2; + unsigned long r3; + unsigned long r4; + unsigned long r5; + unsigned long r6; + unsigned long r7; + unsigned long r8; + unsigned long r9; + unsigned long r10; + unsigned long fp; + unsigned long ip; + unsigned long sp; + unsigned long lr; + unsigned long pc; + unsigned long cpsr; }; #define USERMODE 0x10 diff --git a/libcpu/arm/cortex-r4/cpu.c b/libcpu/arm/cortex-r4/cpu.c index 23c16e383c..dd82ef1cf4 100644 --- a/libcpu/arm/cortex-r4/cpu.c +++ b/libcpu/arm/cortex-r4/cpu.c @@ -1,5 +1,5 @@ /* - * Copyright (c) 2006-2018, RT-Thread Development Team + * Copyright (c) 2006-2021, RT-Thread Development Team * * SPDX-License-Identifier: Apache-2.0 * @@ -30,22 +30,22 @@ RT_WEAK void rt_hw_cpu_reset() */ RT_WEAK void rt_hw_cpu_shutdown() { - rt_kprintf("shutdown...\n"); + rt_kprintf("shutdown...\n"); - while (1); + while (1); } #ifdef __TI_COMPILER_VERSION__ #ifdef RT_USING_CPU_FFS int __rt_ffs(int value) { - if (value == 0) - return value; + if (value == 0) + return value; - __asm(" rsb r1, r0, #0"); - __asm(" and r1, r1, r0"); - __asm(" clz r1, r1"); - __asm(" rsb r0, r1, #32"); + __asm(" rsb r1, r0, #0"); + __asm(" and r1, r1, r0"); + __asm(" clz r1, r1"); + __asm(" rsb r0, r1, #32"); } #endif diff --git a/libcpu/arm/cortex-r4/interrupt.c b/libcpu/arm/cortex-r4/interrupt.c index 30e14f5a2d..14a9023921 100644 --- a/libcpu/arm/cortex-r4/interrupt.c +++ b/libcpu/arm/cortex-r4/interrupt.c @@ -1,5 +1,5 @@ /* - * Copyright (c) 2006-2018, RT-Thread Development Team + * Copyright (c) 2006-2021, RT-Thread Development Team * * SPDX-License-Identifier: Apache-2.0 * @@ -17,7 +17,7 @@ #include "armv7.h" -#define MAX_HANDLERS 96 +#define MAX_HANDLERS 96 /* exception and interrupt handler table */ struct rt_irq_desc irq_desc[MAX_HANDLERS]; @@ -36,16 +36,16 @@ rt_uint32_t rt_thread_switch_interrupt_flag; static void rt_hw_int_not_handle(int vector, void *param) { - rt_kprintf("Unhandled interrupt %d occured!!!\n", vector); + rt_kprintf("Unhandled interrupt %d occured!!!\n", vector); } #define vimRAM (0xFFF82000U) void rt_hw_interrupt_init(void) { - register int i; + register int i; - rt_uint32_t *vect_addr; + rt_uint32_t *vect_addr; /* the initialization is done in sys_startup.c */ @@ -55,15 +55,15 @@ void rt_hw_interrupt_init(void) { irq_desc[i].handler = rt_hw_int_not_handle; - vect_addr = (rt_uint32_t *)(vimRAM + i*4); - *vect_addr = (rt_uint32_t)&irq_desc[i]; + vect_addr = (rt_uint32_t *)(vimRAM + i*4); + *vect_addr = (rt_uint32_t)&irq_desc[i]; } - /* init interrupt nest, and context in thread sp */ - rt_interrupt_nest = 0; - rt_interrupt_from_thread = 0; - rt_interrupt_to_thread = 0; - rt_thread_switch_interrupt_flag = 0; + /* init interrupt nest, and context in thread sp */ + rt_interrupt_nest = 0; + rt_interrupt_from_thread = 0; + rt_interrupt_to_thread = 0; + rt_thread_switch_interrupt_flag = 0; } void rt_hw_interrupt_mask(int vector) @@ -86,21 +86,21 @@ void rt_hw_interrupt_umask(int vector) * @return the old handler */ rt_isr_handler_t rt_hw_interrupt_install(int vector, rt_isr_handler_t handler, - void *param, const char *name) + void *param, const char *name) { - rt_isr_handler_t old_handler = RT_NULL; + rt_isr_handler_t old_handler = RT_NULL; - if(vector >= 0 && vector < MAX_HANDLERS) - { - old_handler = irq_desc[vector].handler; - if (handler != RT_NULL) - { - irq_desc[vector].handler = handler; - irq_desc[vector].param = param; - } - } + if(vector >= 0 && vector < MAX_HANDLERS) + { + old_handler = irq_desc[vector].handler; + if (handler != RT_NULL) + { + irq_desc[vector].handler = handler; + irq_desc[vector].param = param; + } + } - return old_handler; + return old_handler; } /*@}*/ diff --git a/libcpu/arm/cortex-r4/stack.c b/libcpu/arm/cortex-r4/stack.c index 612cde3bfb..539b47d3d2 100644 --- a/libcpu/arm/cortex-r4/stack.c +++ b/libcpu/arm/cortex-r4/stack.c @@ -1,5 +1,5 @@ /* - * Copyright (c) 2006-2018, RT-Thread Development Team + * Copyright (c) 2006-2021, RT-Thread Development Team * * SPDX-License-Identifier: Apache-2.0 * diff --git a/libcpu/arm/cortex-r4/trap.c b/libcpu/arm/cortex-r4/trap.c index d50ad06538..e6c62390c1 100644 --- a/libcpu/arm/cortex-r4/trap.c +++ b/libcpu/arm/cortex-r4/trap.c @@ -1,5 +1,5 @@ /* - * Copyright (c) 2006-2018, RT-Thread Development Team + * Copyright (c) 2006-2021, RT-Thread Development Team * * SPDX-License-Identifier: Apache-2.0 * @@ -28,13 +28,13 @@ */ void rt_hw_show_register (struct rt_hw_exp_stack *regs) { - rt_kprintf("Execption:\n"); - rt_kprintf("r00:0x%08x r01:0x%08x r02:0x%08x r03:0x%08x\n", regs->r0, regs->r1, regs->r2, regs->r3); - rt_kprintf("r04:0x%08x r05:0x%08x r06:0x%08x r07:0x%08x\n", regs->r4, regs->r5, regs->r6, regs->r7); - rt_kprintf("r08:0x%08x r09:0x%08x r10:0x%08x\n", regs->r8, regs->r9, regs->r10); - rt_kprintf("fp :0x%08x ip :0x%08x\n", regs->fp, regs->ip); - rt_kprintf("sp :0x%08x lr :0x%08x pc :0x%08x\n", regs->sp, regs->lr, regs->pc); - rt_kprintf("cpsr:0x%08x\n", regs->cpsr); + rt_kprintf("Execption:\n"); + rt_kprintf("r00:0x%08x r01:0x%08x r02:0x%08x r03:0x%08x\n", regs->r0, regs->r1, regs->r2, regs->r3); + rt_kprintf("r04:0x%08x r05:0x%08x r06:0x%08x r07:0x%08x\n", regs->r4, regs->r5, regs->r6, regs->r7); + rt_kprintf("r08:0x%08x r09:0x%08x r10:0x%08x\n", regs->r8, regs->r9, regs->r10); + rt_kprintf("fp :0x%08x ip :0x%08x\n", regs->fp, regs->ip); + rt_kprintf("sp :0x%08x lr :0x%08x pc :0x%08x\n", regs->sp, regs->lr, regs->pc); + rt_kprintf("cpsr:0x%08x\n", regs->cpsr); } /** @@ -49,8 +49,8 @@ void rt_hw_trap_udef(struct rt_hw_exp_stack *regs) { rt_kprintf("undefined instruction\n"); rt_hw_show_register(regs); - if (rt_thread_self() != RT_NULL) - rt_kprintf("Current Thread: %s\n", rt_thread_self()->name); + if (rt_thread_self() != RT_NULL) + rt_kprintf("Current Thread: %s\n", rt_thread_self()->name); rt_hw_cpu_shutdown(); } @@ -68,7 +68,7 @@ void rt_hw_trap_svc(struct rt_hw_exp_stack *regs) rt_kprintf("software interrupt\n"); rt_hw_show_register(regs); #ifdef RT_USING_FINSH - list_thread(); + list_thread(); #endif rt_hw_cpu_shutdown(); } @@ -86,7 +86,7 @@ void rt_hw_trap_pabt(struct rt_hw_exp_stack *regs) rt_kprintf("prefetch abort\n"); rt_hw_show_register(regs); #ifdef RT_USING_FINSH - list_thread(); + list_thread(); #endif rt_hw_cpu_shutdown(); } @@ -104,7 +104,7 @@ void rt_hw_trap_dabt(struct rt_hw_exp_stack *regs) rt_kprintf("Data Abort "); rt_hw_show_register(regs); #ifdef RT_USING_FINSH - list_thread(); + list_thread(); #endif rt_hw_cpu_shutdown(); } @@ -121,7 +121,7 @@ void rt_hw_trap_resv(struct rt_hw_exp_stack *regs) rt_kprintf("Reserved trap\n"); rt_hw_show_register(regs); #ifdef RT_USING_FINSH - list_thread(); + list_thread(); #endif rt_hw_cpu_shutdown(); } @@ -129,15 +129,15 @@ void rt_hw_trap_resv(struct rt_hw_exp_stack *regs) extern rt_isr_handler_t isr_table[]; void rt_hw_trap_irq(void) { - int irqno; - struct rt_irq_desc* irq; - extern struct rt_irq_desc irq_desc[]; + int irqno; + struct rt_irq_desc* irq; + extern struct rt_irq_desc irq_desc[]; - irq = (struct rt_irq_desc*) vimREG->IRQVECREG; - irqno = ((rt_uint32_t) irq - (rt_uint32_t) &irq_desc[0])/sizeof(struct rt_irq_desc); + irq = (struct rt_irq_desc*) vimREG->IRQVECREG; + irqno = ((rt_uint32_t) irq - (rt_uint32_t) &irq_desc[0])/sizeof(struct rt_irq_desc); - /* invoke isr */ - irq->handler(irqno, irq->param); + /* invoke isr */ + irq->handler(irqno, irq->param); } void rt_hw_trap_fiq(void) diff --git a/libcpu/arm/dm36x/cpuport.c b/libcpu/arm/dm36x/cpuport.c index 99edb96260..435ca2f15f 100644 --- a/libcpu/arm/dm36x/cpuport.c +++ b/libcpu/arm/dm36x/cpuport.c @@ -1,5 +1,5 @@ /* - * Copyright (c) 2006-2018, RT-Thread Development Team + * Copyright (c) 2006-2021, RT-Thread Development Team * * SPDX-License-Identifier: Apache-2.0 * @@ -11,8 +11,8 @@ #include <rthw.h> #include <rtthread.h> -#define ICACHE_MASK (rt_uint32_t)(1 << 12) -#define DCACHE_MASK (rt_uint32_t)(1 << 2) +#define ICACHE_MASK (rt_uint32_t)(1 << 12) +#define DCACHE_MASK (rt_uint32_t)(1 << 2) extern void machine_reset(void); extern void machine_shutdown(void); @@ -20,70 +20,70 @@ extern void machine_shutdown(void); #ifdef __GNUC__ rt_inline rt_uint32_t cp15_rd(void) { - rt_uint32_t i; + rt_uint32_t i; - asm ("mrc p15, 0, %0, c1, c0, 0":"=r" (i)); - return i; + asm ("mrc p15, 0, %0, c1, c0, 0":"=r" (i)); + return i; } rt_inline void cache_enable(rt_uint32_t bit) { - __asm__ __volatile__( \ - "mrc p15,0,r0,c1,c0,0\n\t" \ - "orr r0,r0,%0\n\t" \ - "mcr p15,0,r0,c1,c0,0" \ - : \ - :"r" (bit) \ - :"memory"); + __asm__ __volatile__( \ + "mrc p15,0,r0,c1,c0,0\n\t" \ + "orr r0,r0,%0\n\t" \ + "mcr p15,0,r0,c1,c0,0" \ + : \ + :"r" (bit) \ + :"memory"); } rt_inline void cache_disable(rt_uint32_t bit) { - __asm__ __volatile__( \ - "mrc p15,0,r0,c1,c0,0\n\t" \ - "bic r0,r0,%0\n\t" \ - "mcr p15,0,r0,c1,c0,0" \ - : \ - :"r" (bit) \ - :"memory"); + __asm__ __volatile__( \ + "mrc p15,0,r0,c1,c0,0\n\t" \ + "bic r0,r0,%0\n\t" \ + "mcr p15,0,r0,c1,c0,0" \ + : \ + :"r" (bit) \ + :"memory"); } #endif #ifdef __CC_ARM rt_inline rt_uint32_t cp15_rd(void) { - rt_uint32_t i; + rt_uint32_t i; - __asm - { - mrc p15, 0, i, c1, c0, 0 - } + __asm + { + mrc p15, 0, i, c1, c0, 0 + } - return i; + return i; } rt_inline void cache_enable(rt_uint32_t bit) { - rt_uint32_t value; + rt_uint32_t value; - __asm - { - mrc p15, 0, value, c1, c0, 0 - orr value, value, bit - mcr p15, 0, value, c1, c0, 0 - } + __asm + { + mrc p15, 0, value, c1, c0, 0 + orr value, value, bit + mcr p15, 0, value, c1, c0, 0 + } } rt_inline void cache_disable(rt_uint32_t bit) { - rt_uint32_t value; + rt_uint32_t value; - __asm - { - mrc p15, 0, value, c1, c0, 0 - bic value, value, bit - mcr p15, 0, value, c1, c0, 0 - } + __asm + { + mrc p15, 0, value, c1, c0, 0 + bic value, value, bit + mcr p15, 0, value, c1, c0, 0 + } } #endif @@ -93,7 +93,7 @@ rt_inline void cache_disable(rt_uint32_t bit) */ void rt_hw_cpu_icache_enable() { - cache_enable(ICACHE_MASK); + cache_enable(ICACHE_MASK); } /** @@ -102,7 +102,7 @@ void rt_hw_cpu_icache_enable() */ void rt_hw_cpu_icache_disable() { - cache_disable(ICACHE_MASK); + cache_disable(ICACHE_MASK); } /** @@ -111,7 +111,7 @@ void rt_hw_cpu_icache_disable() */ rt_base_t rt_hw_cpu_icache_status() { - return (cp15_rd() & ICACHE_MASK); + return (cp15_rd() & ICACHE_MASK); } /** @@ -120,7 +120,7 @@ rt_base_t rt_hw_cpu_icache_status() */ void rt_hw_cpu_dcache_enable() { - cache_enable(DCACHE_MASK); + cache_enable(DCACHE_MASK); } /** @@ -129,7 +129,7 @@ void rt_hw_cpu_dcache_enable() */ void rt_hw_cpu_dcache_disable() { - cache_disable(DCACHE_MASK); + cache_disable(DCACHE_MASK); } /** @@ -138,7 +138,7 @@ void rt_hw_cpu_dcache_disable() */ rt_base_t rt_hw_cpu_dcache_status() { - return (cp15_rd() & DCACHE_MASK); + return (cp15_rd() & DCACHE_MASK); } /** @@ -147,13 +147,13 @@ rt_base_t rt_hw_cpu_dcache_status() */ RT_WEAK void rt_hw_cpu_reset() { - - rt_kprintf("Restarting system...\n"); - machine_reset(); - while(1); /* loop forever and wait for reset to happen */ + rt_kprintf("Restarting system...\n"); + machine_reset(); - /* NEVER REACHED */ + while(1); /* loop forever and wait for reset to happen */ + + /* NEVER REACHED */ } /** @@ -162,67 +162,67 @@ RT_WEAK void rt_hw_cpu_reset() */ RT_WEAK void rt_hw_cpu_shutdown() { - rt_uint32_t level; - rt_kprintf("shutdown...\n"); + rt_uint32_t level; + rt_kprintf("shutdown...\n"); - level = rt_hw_interrupt_disable(); - machine_shutdown(); - while (level) - { - RT_ASSERT(0); - } + level = rt_hw_interrupt_disable(); + machine_shutdown(); + while (level) + { + RT_ASSERT(0); + } } #ifdef RT_USING_CPU_FFS /** - * This function finds the first bit set (beginning with the least significant bit) + * This function finds the first bit set (beginning with the least significant bit) * in value and return the index of that bit. * - * Bits are numbered starting at 1 (the least significant bit). A return value of + * Bits are numbered starting at 1 (the least significant bit). A return value of * zero from any of these functions means that the argument was zero. - * - * @return return the index of the first bit set. If value is 0, then this function + * + * @return return the index of the first bit set. If value is 0, then this function * shall return 0. */ #if defined(__CC_ARM) int __rt_ffs(int value) { - register rt_uint32_t x; + register rt_uint32_t x; + + if (value == 0) + return value; - if (value == 0) - return value; - - __asm - { - rsb x, value, #0 - and x, x, value - clz x, x - rsb x, x, #32 - } + __asm + { + rsb x, value, #0 + and x, x, value + clz x, x + rsb x, x, #32 + } - return x; + return x; } #elif defined(__IAR_SYSTEMS_ICC__) int __rt_ffs(int value) { - if (value == 0) - return value; + if (value == 0) + return value; - __ASM("RSB r4, r0, #0"); - __ASM("AND r4, r4, r0"); - __ASM("CLZ r4, r4"); - __ASM("RSB r0, r4, #32"); + __ASM("RSB r4, r0, #0"); + __ASM("AND r4, r4, r0"); + __ASM("CLZ r4, r4"); + __ASM("RSB r0, r4, #32"); } #elif defined(__GNUC__) int __rt_ffs(int value) { - if (value == 0) - return value; + if (value == 0) + return value; - value &= (-value); - asm ("clz %0, %1": "=r"(value) :"r"(value)); + value &= (-value); + asm ("clz %0, %1": "=r"(value) :"r"(value)); - return (32 - value); + return (32 - value); } #endif diff --git a/libcpu/arm/dm36x/mmu.c b/libcpu/arm/dm36x/mmu.c index abb2c1cd9e..bec2e6a71c 100644 --- a/libcpu/arm/dm36x/mmu.c +++ b/libcpu/arm/dm36x/mmu.c @@ -1,5 +1,5 @@ /* - * Copyright (c) 2006-2018, RT-Thread Development Team + * Copyright (c) 2006-2021, RT-Thread Development Team * * SPDX-License-Identifier: Apache-2.0 * @@ -12,22 +12,22 @@ #ifdef __CC_ARM void mmu_setttbase(rt_uint32_t i) { - register rt_uint32_t value; + register rt_uint32_t value; /* Invalidates all TLBs.Domain access is selected as * client by configuring domain access register, * in that case access controlled by permission value * set by page table entry */ - value = 0; + value = 0; __asm volatile { mcr p15, 0, value, c8, c7, 0 - } + } - value = 0x55555555; - __asm volatile - { + value = 0x55555555; + __asm volatile + { mcr p15, 0, value, c3, c0, 0 mcr p15, 0, i, c2, c0, 0 } @@ -153,44 +153,44 @@ void mmu_clean_invalidated_dcache(rt_uint32_t buffer, rt_uint32_t size) while(ptr < buffer + size) { - __asm volatile - { - MCR p15, 0, ptr, c7, c14, 1 - } + __asm volatile + { + MCR p15, 0, ptr, c7, c14, 1 + } ptr += CACHE_LINE_SIZE; } } void mmu_clean_dcache(rt_uint32_t buffer, rt_uint32_t size) { - unsigned int ptr; + unsigned int ptr; - ptr = buffer & ~(CACHE_LINE_SIZE - 1); + ptr = buffer & ~(CACHE_LINE_SIZE - 1); - while (ptr < buffer + size) - { - __asm volatile - { - MCR p15, 0, ptr, c7, c10, 1 - } - ptr += CACHE_LINE_SIZE; - } + while (ptr < buffer + size) + { + __asm volatile + { + MCR p15, 0, ptr, c7, c10, 1 + } + ptr += CACHE_LINE_SIZE; + } } void mmu_invalidate_dcache(rt_uint32_t buffer, rt_uint32_t size) { - unsigned int ptr; + unsigned int ptr; - ptr = buffer & ~(CACHE_LINE_SIZE - 1); + ptr = buffer & ~(CACHE_LINE_SIZE - 1); - while (ptr < buffer + size) - { - __asm volatile - { - MCR p15, 0, ptr, c7, c6, 1 - } - ptr += CACHE_LINE_SIZE; - } + while (ptr < buffer + size) + { + __asm volatile + { + MCR p15, 0, ptr, c7, c6, 1 + } + ptr += CACHE_LINE_SIZE; + } } void mmu_invalidate_tlb() @@ -231,137 +231,137 @@ void mmu_invalidate_dcache_all() #elif defined(__GNUC__) void mmu_setttbase(register rt_uint32_t i) { - register rt_uint32_t value; + register rt_uint32_t value; /* Invalidates all TLBs.Domain access is selected as * client by configuring domain access register, * in that case access controlled by permission value * set by page table entry */ - value = 0; - asm volatile ("mcr p15, 0, %0, c8, c7, 0"::"r"(value)); + value = 0; + asm volatile ("mcr p15, 0, %0, c8, c7, 0"::"r"(value)); - value = 0x55555555; - asm volatile ("mcr p15, 0, %0, c3, c0, 0"::"r"(value)); - asm volatile ("mcr p15, 0, %0, c2, c0, 0"::"r"(i)); + value = 0x55555555; + asm volatile ("mcr p15, 0, %0, c3, c0, 0"::"r"(value)); + asm volatile ("mcr p15, 0, %0, c2, c0, 0"::"r"(i)); } void mmu_set_domain(register rt_uint32_t i) { - asm volatile ("mcr p15,0, %0, c3, c0, 0": :"r" (i)); + asm volatile ("mcr p15,0, %0, c3, c0, 0": :"r" (i)); } void mmu_enable() { - register rt_uint32_t i; + register rt_uint32_t i; - /* read control register */ - asm volatile ("mrc p15, 0, %0, c1, c0, 0":"=r" (i)); + /* read control register */ + asm volatile ("mrc p15, 0, %0, c1, c0, 0":"=r" (i)); - i |= 0x1; - i |= (1 << 13); /* High exception vectors selected, address range = 0xFFFF0000-0xFFFF001C */ - /* S R bit=1 0 for system protection */ - i |= (1 << 8); - i &= ~(1 << 9); + i |= 0x1; + i |= (1 << 13); /* High exception vectors selected, address range = 0xFFFF0000-0xFFFF001C */ + /* S R bit=1 0 for system protection */ + i |= (1 << 8); + i &= ~(1 << 9); - /* write back to control register */ - asm volatile ("mcr p15, 0, %0, c1, c0, 0": :"r" (i)); + /* write back to control register */ + asm volatile ("mcr p15, 0, %0, c1, c0, 0": :"r" (i)); } void mmu_disable() { - register rt_uint32_t i; + register rt_uint32_t i; - /* read control register */ - asm volatile ("mrc p15, 0, %0, c1, c0, 0":"=r" (i)); + /* read control register */ + asm volatile ("mrc p15, 0, %0, c1, c0, 0":"=r" (i)); - i &= ~0x1; + i &= ~0x1; - /* write back to control register */ - asm volatile ("mcr p15, 0, %0, c1, c0, 0": :"r" (i)); + /* write back to control register */ + asm volatile ("mcr p15, 0, %0, c1, c0, 0": :"r" (i)); } void mmu_enable_icache() { - register rt_uint32_t i; + register rt_uint32_t i; - /* read control register */ - asm volatile ("mrc p15, 0, %0, c1, c0, 0":"=r" (i)); + /* read control register */ + asm volatile ("mrc p15, 0, %0, c1, c0, 0":"=r" (i)); - i |= (1 << 12); + i |= (1 << 12); - /* write back to control register */ - asm volatile ("mcr p15, 0, %0, c1, c0, 0": :"r" (i)); + /* write back to control register */ + asm volatile ("mcr p15, 0, %0, c1, c0, 0": :"r" (i)); } void mmu_enable_dcache() { - register rt_uint32_t i; + register rt_uint32_t i; - /* read control register */ - asm volatile ("mrc p15, 0, %0, c1, c0, 0":"=r" (i)); + /* read control register */ + asm volatile ("mrc p15, 0, %0, c1, c0, 0":"=r" (i)); - i |= (1 << 2); + i |= (1 << 2); - /* write back to control register */ - asm volatile ("mcr p15, 0, %0, c1, c0, 0": :"r" (i)); + /* write back to control register */ + asm volatile ("mcr p15, 0, %0, c1, c0, 0": :"r" (i)); } void mmu_disable_icache() { - register rt_uint32_t i; + register rt_uint32_t i; - /* read control register */ - asm volatile ("mrc p15, 0, %0, c1, c0, 0":"=r" (i)); + /* read control register */ + asm volatile ("mrc p15, 0, %0, c1, c0, 0":"=r" (i)); - i &= ~(1 << 12); + i &= ~(1 << 12); - /* write back to control register */ - asm volatile ("mcr p15, 0, %0, c1, c0, 0": :"r" (i)); + /* write back to control register */ + asm volatile ("mcr p15, 0, %0, c1, c0, 0": :"r" (i)); } void mmu_disable_dcache() { - register rt_uint32_t i; + register rt_uint32_t i; - /* read control register */ - asm volatile ("mrc p15, 0, %0, c1, c0, 0":"=r" (i)); + /* read control register */ + asm volatile ("mrc p15, 0, %0, c1, c0, 0":"=r" (i)); - i &= ~(1 << 2); + i &= ~(1 << 2); - /* write back to control register */ - asm volatile ("mcr p15, 0, %0, c1, c0, 0": :"r" (i)); + /* write back to control register */ + asm volatile ("mcr p15, 0, %0, c1, c0, 0": :"r" (i)); } void mmu_enable_alignfault() { - register rt_uint32_t i; + register rt_uint32_t i; - /* read control register */ - asm volatile ("mrc p15, 0, %0, c1, c0, 0":"=r" (i)); + /* read control register */ + asm volatile ("mrc p15, 0, %0, c1, c0, 0":"=r" (i)); - i |= (1 << 1); + i |= (1 << 1); - /* write back to control register */ - asm volatile ("mcr p15, 0, %0, c1, c0, 0": :"r" (i)); + /* write back to control register */ + asm volatile ("mcr p15, 0, %0, c1, c0, 0": :"r" (i)); } void mmu_disable_alignfault() { - register rt_uint32_t i; + register rt_uint32_t i; - /* read control register */ - asm volatile ("mrc p15, 0, %0, c1, c0, 0":"=r" (i)); + /* read control register */ + asm volatile ("mrc p15, 0, %0, c1, c0, 0":"=r" (i)); - i &= ~(1 << 1); + i &= ~(1 << 1); - /* write back to control register */ - asm volatile ("mcr p15, 0, %0, c1, c0, 0": :"r" (i)); + /* write back to control register */ + asm volatile ("mcr p15, 0, %0, c1, c0, 0": :"r" (i)); } void mmu_clean_invalidated_cache_index(int index) { - asm volatile ("mcr p15, 0, %0, c7, c14, 2": :"r" (index)); + asm volatile ("mcr p15, 0, %0, c7, c14, 2": :"r" (index)); } void mmu_clean_invalidated_dcache(rt_uint32_t buffer, rt_uint32_t size) @@ -372,7 +372,7 @@ void mmu_clean_invalidated_dcache(rt_uint32_t buffer, rt_uint32_t size) while(ptr < buffer + size) { - asm volatile ("mcr p15, 0, %0, c7, c14, 1": :"r" (ptr)); + asm volatile ("mcr p15, 0, %0, c7, c14, 1": :"r" (ptr)); ptr += CACHE_LINE_SIZE; } } @@ -380,38 +380,38 @@ void mmu_clean_invalidated_dcache(rt_uint32_t buffer, rt_uint32_t size) void mmu_clean_dcache(rt_uint32_t buffer, rt_uint32_t size) { - unsigned int ptr; + unsigned int ptr; - ptr = buffer & ~(CACHE_LINE_SIZE - 1); + ptr = buffer & ~(CACHE_LINE_SIZE - 1); - while (ptr < buffer + size) - { - asm volatile ("mcr p15, 0, %0, c7, c10, 1": :"r" (ptr)); - ptr += CACHE_LINE_SIZE; - } + while (ptr < buffer + size) + { + asm volatile ("mcr p15, 0, %0, c7, c10, 1": :"r" (ptr)); + ptr += CACHE_LINE_SIZE; + } } void mmu_invalidate_dcache(rt_uint32_t buffer, rt_uint32_t size) { - unsigned int ptr; + unsigned int ptr; - ptr = buffer & ~(CACHE_LINE_SIZE - 1); + ptr = buffer & ~(CACHE_LINE_SIZE - 1); - while (ptr < buffer + size) - { - asm volatile ("mcr p15, 0, %0, c7, c6, 1": :"r" (ptr)); - ptr += CACHE_LINE_SIZE; - } + while (ptr < buffer + size) + { + asm volatile ("mcr p15, 0, %0, c7, c6, 1": :"r" (ptr)); + ptr += CACHE_LINE_SIZE; + } } void mmu_invalidate_tlb() { - asm volatile ("mcr p15, 0, %0, c8, c7, 0": :"r" (0)); + asm volatile ("mcr p15, 0, %0, c8, c7, 0": :"r" (0)); } void mmu_invalidate_icache() { - asm volatile ("mcr p15, 0, %0, c7, c5, 0": :"r" (0)); + asm volatile ("mcr p15, 0, %0, c7, c5, 0": :"r" (0)); } void mmu_invalidate_dcache_all() @@ -462,13 +462,13 @@ void mmu_create_pte(struct mem_desc *mdesc) if (*pTT == 0) /* Level 1 page table item not used, now update pgd item */ { *pTT = pte_offset | sect_attr; - p_pteentry = (rt_uint32_t *)pte_offset + + p_pteentry = (rt_uint32_t *)pte_offset + ((vaddr & 0x000ff000) >> 12); pte_offset += 1024; } else /* using old Level 1 page table item */ { - p_pteentry = (rt_uint32_t *)(*pTT & 0xfffffc00) + + p_pteentry = (rt_uint32_t *)(*pTT & 0xfffffc00) + ((vaddr & 0x000ff000) >> 12); } @@ -503,13 +503,13 @@ static void build_pte_mem_desc(struct mem_desc *mdesc, rt_uint32_t size) void rt_hw_mmu_init(struct mem_desc *mdesc, rt_uint32_t size) { - /* disable I/D cache */ - mmu_disable_dcache(); - mmu_disable_icache(); - mmu_disable(); - mmu_invalidate_tlb(); + /* disable I/D cache */ + mmu_disable_dcache(); + mmu_disable_icache(); + mmu_disable(); + mmu_invalidate_tlb(); - /* clear pgd and pte table */ + /* clear pgd and pte table */ rt_memset((void *)_pgd_table, 0, 16*1024); rt_memset((void *)_pte_table, 0, RT_MMU_PTE_SIZE); build_pte_mem_desc(mdesc, size); diff --git a/libcpu/arm/dm36x/mmu.h b/libcpu/arm/dm36x/mmu.h index 3410b881ac..60a4e3c6e9 100644 --- a/libcpu/arm/dm36x/mmu.h +++ b/libcpu/arm/dm36x/mmu.h @@ -1,5 +1,5 @@ /* - * Copyright (c) 2006-2018, RT-Thread Development Team + * Copyright (c) 2006-2021, RT-Thread Development Team * * SPDX-License-Identifier: Apache-2.0 * @@ -12,7 +12,7 @@ #include <rtthread.h> -#define CACHE_LINE_SIZE 32 +#define CACHE_LINE_SIZE 32 /* * Hardware page table definitions. @@ -30,7 +30,7 @@ /* * - section */ -#define PGD_SECT_BUFFERABLE (1 << 2) +#define PGD_SECT_BUFFERABLE (1 << 2) #define PGD_SECT_CACHEABLE (1 << 3) #define PGD_SECT_XN (1 << 4) /* ARMv6 */ #define PGD_SECT_AP0 (1 << 10) @@ -133,14 +133,14 @@ #define PAGE_RO_FAULT (PAGE_AP_RO|PTE_TYPE_SMALL) /* Read Only without cache and write buffer */ struct mem_desc { - rt_uint32_t vaddr_start; - rt_uint32_t vaddr_end; - rt_uint32_t paddr_start; - rt_uint32_t sect_attr; /* when page mapped */ - rt_uint32_t page_attr; /* only sector mapped valid */ - rt_uint32_t mapped_mode; - #define SECT_MAPPED 0 - #define PAGE_MAPPED 1 + rt_uint32_t vaddr_start; + rt_uint32_t vaddr_end; + rt_uint32_t paddr_start; + rt_uint32_t sect_attr; /* when page mapped */ + rt_uint32_t page_attr; /* only sector mapped valid */ + rt_uint32_t mapped_mode; + #define SECT_MAPPED 0 + #define PAGE_MAPPED 1 }; diff --git a/libcpu/arm/dm36x/stack.c b/libcpu/arm/dm36x/stack.c index 9d7385b9c8..e725d060c1 100644 --- a/libcpu/arm/dm36x/stack.c +++ b/libcpu/arm/dm36x/stack.c @@ -1,5 +1,5 @@ /* - * Copyright (c) 2006-2018, RT-Thread Development Team + * Copyright (c) 2006-2021, RT-Thread Development Team * * SPDX-License-Identifier: Apache-2.0 * diff --git a/libcpu/arm/lpc214x/cpuport.c b/libcpu/arm/lpc214x/cpuport.c index 54e7e9b0c8..a1f594dcb9 100644 --- a/libcpu/arm/lpc214x/cpuport.c +++ b/libcpu/arm/lpc214x/cpuport.c @@ -1,5 +1,5 @@ /* - * Copyright (c) 2006-2018, RT-Thread Development Team + * Copyright (c) 2006-2021, RT-Thread Development Team * * SPDX-License-Identifier: Apache-2.0 * @@ -13,13 +13,13 @@ #include <rthw.h> #include "lpc214x.h" -#define MAX_HANDLERS 32 -#define SVCMODE 0x13 +#define MAX_HANDLERS 32 +#define SVCMODE 0x13 extern rt_uint32_t rt_interrupt_nest; /* exception and interrupt handler table */ -struct rt_irq_desc irq_desc[MAX_HANDLERS]; +struct rt_irq_desc irq_desc[MAX_HANDLERS]; /** * @addtogroup LPC214x @@ -37,35 +37,35 @@ struct rt_irq_desc irq_desc[MAX_HANDLERS]; * @return stack address */ rt_uint8_t *rt_hw_stack_init(void *tentry, void *parameter, - rt_uint8_t *stack_addr, void *texit) + rt_uint8_t *stack_addr, void *texit) { - unsigned long *stk; + unsigned long *stk; - stk = (unsigned long *)stack_addr; - *(stk) = (unsigned long)tentry; /* entry point */ - *(--stk) = (unsigned long)texit; /* lr */ - *(--stk) = 0; /* r12 */ - *(--stk) = 0; /* r11 */ - *(--stk) = 0; /* r10 */ - *(--stk) = 0; /* r9 */ - *(--stk) = 0; /* r8 */ - *(--stk) = 0; /* r7 */ - *(--stk) = 0; /* r6 */ - *(--stk) = 0; /* r5 */ - *(--stk) = 0; /* r4 */ - *(--stk) = 0; /* r3 */ - *(--stk) = 0; /* r2 */ - *(--stk) = 0; /* r1 */ - *(--stk) = (unsigned long)parameter; /* r0 : argument */ + stk = (unsigned long *)stack_addr; + *(stk) = (unsigned long)tentry; /* entry point */ + *(--stk) = (unsigned long)texit; /* lr */ + *(--stk) = 0; /* r12 */ + *(--stk) = 0; /* r11 */ + *(--stk) = 0; /* r10 */ + *(--stk) = 0; /* r9 */ + *(--stk) = 0; /* r8 */ + *(--stk) = 0; /* r7 */ + *(--stk) = 0; /* r6 */ + *(--stk) = 0; /* r5 */ + *(--stk) = 0; /* r4 */ + *(--stk) = 0; /* r3 */ + *(--stk) = 0; /* r2 */ + *(--stk) = 0; /* r1 */ + *(--stk) = (unsigned long)parameter; /* r0 : argument */ - /* cpsr */ - if ((rt_uint32_t)tentry & 0x01) - *(--stk) = SVCMODE | 0x20; /* thumb mode */ - else - *(--stk) = SVCMODE; /* arm mode */ + /* cpsr */ + if ((rt_uint32_t)tentry & 0x01) + *(--stk) = SVCMODE | 0x20; /* thumb mode */ + else + *(--stk) = SVCMODE; /* arm mode */ - /* return task's current stack address */ - return (rt_uint8_t *)stk; + /* return task's current stack address */ + return (rt_uint8_t *)stk; } /* exception and interrupt handler table */ @@ -74,7 +74,7 @@ rt_uint32_t rt_thread_switch_interrupt_flag; void rt_hw_interrupt_handler(int vector, void *param) { - rt_kprintf("Unhandled interrupt %d occured!!!\n", vector); + rt_kprintf("Unhandled interrupt %d occured!!!\n", vector); } /** @@ -82,32 +82,32 @@ void rt_hw_interrupt_handler(int vector, void *param) */ void rt_hw_interrupt_init(void) { - rt_base_t index; - rt_uint32_t *vect_addr, *vect_ctl; + rt_base_t index; + rt_uint32_t *vect_addr, *vect_ctl; - /* initialize VIC*/ - VICIntEnClr = 0xffffffff; - VICVectAddr = 0; - /* set all to IRQ */ - VICIntSelect = 0; + /* initialize VIC*/ + VICIntEnClr = 0xffffffff; + VICVectAddr = 0; + /* set all to IRQ */ + VICIntSelect = 0; rt_memset(irq_desc, 0x00, sizeof(irq_desc)); - for (index = 0; index < MAX_HANDLERS; index ++) - { + for (index = 0; index < MAX_HANDLERS; index ++) + { irq_desc[index].handler = rt_hw_interrupt_handler; - vect_addr = (rt_uint32_t *)(VIC_BASE_ADDR + 0x100 + (index << 2)); - vect_ctl = (rt_uint32_t *)(VIC_BASE_ADDR + 0x200 + (index << 2)); + vect_addr = (rt_uint32_t *)(VIC_BASE_ADDR + 0x100 + (index << 2)); + vect_ctl = (rt_uint32_t *)(VIC_BASE_ADDR + 0x200 + (index << 2)); - *vect_addr = (rt_uint32_t)&irq_desc[index]; - *vect_ctl = 0xF; - } + *vect_addr = (rt_uint32_t)&irq_desc[index]; + *vect_ctl = 0xF; + } - /* init interrupt nest, and context in thread sp */ - rt_interrupt_nest = 0; - rt_interrupt_from_thread = 0; - rt_interrupt_to_thread = 0; - rt_thread_switch_interrupt_flag = 0; + /* init interrupt nest, and context in thread sp */ + rt_interrupt_nest = 0; + rt_interrupt_from_thread = 0; + rt_interrupt_to_thread = 0; + rt_thread_switch_interrupt_flag = 0; } /** @@ -116,7 +116,7 @@ void rt_hw_interrupt_init(void) */ void rt_hw_interrupt_mask(int vector) { - VICIntEnClr = (1 << vector); + VICIntEnClr = (1 << vector); } /** @@ -125,7 +125,7 @@ void rt_hw_interrupt_mask(int vector) */ void rt_hw_interrupt_umask(int vector) { - VICIntEnable = (1 << vector); + VICIntEnable = (1 << vector); } /** @@ -143,17 +143,17 @@ rt_isr_handler_t rt_hw_interrupt_install(int vector, rt_isr_handler_t handler, if(vector >= 0 && vector < MAX_HANDLERS) { - rt_uint32_t* vect_ctl = (rt_uint32_t *)(VIC_BASE_ADDR + 0x200 + (vector << 2)); + rt_uint32_t* vect_ctl = (rt_uint32_t *)(VIC_BASE_ADDR + 0x200 + (vector << 2)); /* assign IRQ slot and enable this slot */ *vect_ctl = 0x20 | (vector & 0x1F); old_handler = irq_desc[vector].handler; - if (handler != RT_NULL) - { - irq_desc[vector].handler = handler; - irq_desc[vector].param = param; - } + if (handler != RT_NULL) + { + irq_desc[vector].handler = handler; + irq_desc[vector].param = param; + } } return old_handler; @@ -173,22 +173,22 @@ RT_WEAK void rt_hw_cpu_reset(void) */ RT_WEAK void rt_hw_cpu_shutdown() { - rt_kprintf("shutdown...\n"); + rt_kprintf("shutdown...\n"); - while (1); + while (1); } void rt_hw_trap_irq(void) { int irqno; - struct rt_irq_desc* irq; + struct rt_irq_desc* irq; extern struct rt_irq_desc irq_desc[]; - irq = (struct rt_irq_desc*) VICVectAddr; - irqno = ((rt_uint32_t) irq - (rt_uint32_t) &irq_desc[0])/sizeof(struct rt_irq_desc); + irq = (struct rt_irq_desc*) VICVectAddr; + irqno = ((rt_uint32_t) irq - (rt_uint32_t) &irq_desc[0])/sizeof(struct rt_irq_desc); - /* invoke isr */ - irq->handler(irqno, irq->param); + /* invoke isr */ + irq->handler(irqno, irq->param); /* acknowledge Interrupt */ // VICVectAddr = 0; diff --git a/libcpu/arm/lpc214x/lpc214x.h b/libcpu/arm/lpc214x/lpc214x.h index 1805bc6c03..21691f85ad 100644 --- a/libcpu/arm/lpc214x/lpc214x.h +++ b/libcpu/arm/lpc214x/lpc214x.h @@ -361,33 +361,33 @@ #define USBSysErrIntClr (*((volatile unsigned long *) 0xE00900BC)) #define USBSysErrIntSet (*((volatile unsigned long *) 0xE00900C0)) -#define VIC_BASE_ADDR 0xFFFFF000 +#define VIC_BASE_ADDR 0xFFFFF000 enum LPC214x_INT { - WDT_INT = 0, - SW_INT_reserved, - DbgCommRx_INT, - DbgCommTx_INT, - TIMER0_INT, - TIMER1_INT, - UART0_INT, - UART1_INT, - PWM0_INT, - I2C0_INT, - SP0_INT, - SP1_INT, - PLL_INT, - RTC_INT, - EINT0_INT, - EINT1_INT, - EINT2_INT, - EINT3_INT, - ADC0_INT, - I2C1_INT, - BOD_INT, - ADC1_INT, - USB_INT + WDT_INT = 0, + SW_INT_reserved, + DbgCommRx_INT, + DbgCommTx_INT, + TIMER0_INT, + TIMER1_INT, + UART0_INT, + UART1_INT, + PWM0_INT, + I2C0_INT, + SP0_INT, + SP1_INT, + PLL_INT, + RTC_INT, + EINT0_INT, + EINT1_INT, + EINT2_INT, + EINT3_INT, + ADC0_INT, + I2C1_INT, + BOD_INT, + ADC1_INT, + USB_INT }; #endif // __LPC214x_H diff --git a/libcpu/arm/lpc24xx/LPC24xx.h b/libcpu/arm/lpc24xx/LPC24xx.h index 5cb9730854..827310ca67 100644 --- a/libcpu/arm/lpc24xx/LPC24xx.h +++ b/libcpu/arm/lpc24xx/LPC24xx.h @@ -1,5 +1,5 @@ /* - * Copyright (c) 2006-2018, RT-Thread Development Team + * Copyright (c) 2006-2021, RT-Thread Development Team * * SPDX-License-Identifier: Apache-2.0 * @@ -14,20 +14,20 @@ #ifdef __cplusplus extern "C" { #endif - -#define USERMODE 0x10 -#define FIQMODE 0x11 -#define IRQMODE 0x12 -#define SVCMODE 0x13 -#define ABORTMODE 0x17 -#define UNDEFMODE 0x1b -#define MODEMASK 0x1f -#define NOINT 0xc0 - -#define MCLK (72000000) - + +#define USERMODE 0x10 +#define FIQMODE 0x11 +#define IRQMODE 0x12 +#define SVCMODE 0x13 +#define ABORTMODE 0x17 +#define UNDEFMODE 0x1b +#define MODEMASK 0x1f +#define NOINT 0xc0 + +#define MCLK (72000000) + /* Vectored Interrupt Controller (VIC) */ -#define VIC_BASE_ADDR 0xFFFFF000 +#define VIC_BASE_ADDR 0xFFFFF000 #define VICIRQStatus (*(volatile unsigned long *)(VIC_BASE_ADDR + 0x000)) #define VICFIQStatus (*(volatile unsigned long *)(VIC_BASE_ADDR + 0x004)) #define VICRawIntr (*(volatile unsigned long *)(VIC_BASE_ADDR + 0x008)) @@ -111,7 +111,7 @@ these registers are known as "VICVectPriority(x)". */ /* Pin Connect Block */ -#define PINSEL_BASE_ADDR 0xE002C000 +#define PINSEL_BASE_ADDR 0xE002C000 #define PINSEL0 (*(volatile unsigned long *)(PINSEL_BASE_ADDR + 0x00)) #define PINSEL1 (*(volatile unsigned long *)(PINSEL_BASE_ADDR + 0x04)) #define PINSEL2 (*(volatile unsigned long *)(PINSEL_BASE_ADDR + 0x08)) @@ -137,7 +137,7 @@ these registers are known as "VICVectPriority(x)". */ #define PINMODE9 (*(volatile unsigned long *)(PINSEL_BASE_ADDR + 0x64)) /* General Purpose Input/Output (GPIO) */ -#define GPIO_BASE_ADDR 0xE0028000 +#define GPIO_BASE_ADDR 0xE0028000 #define IOPIN0 (*(volatile unsigned long *)(GPIO_BASE_ADDR + 0x00)) #define IOSET0 (*(volatile unsigned long *)(GPIO_BASE_ADDR + 0x04)) #define IODIR0 (*(volatile unsigned long *)(GPIO_BASE_ADDR + 0x08)) @@ -148,13 +148,13 @@ these registers are known as "VICVectPriority(x)". */ #define IOCLR1 (*(volatile unsigned long *)(GPIO_BASE_ADDR + 0x1C)) /* GPIO Interrupt Registers */ -#define IO0_INT_EN_R (*(volatile unsigned long *)(GPIO_BASE_ADDR + 0x90)) +#define IO0_INT_EN_R (*(volatile unsigned long *)(GPIO_BASE_ADDR + 0x90)) #define IO0_INT_EN_F (*(volatile unsigned long *)(GPIO_BASE_ADDR + 0x94)) #define IO0_INT_STAT_R (*(volatile unsigned long *)(GPIO_BASE_ADDR + 0x84)) #define IO0_INT_STAT_F (*(volatile unsigned long *)(GPIO_BASE_ADDR + 0x88)) #define IO0_INT_CLR (*(volatile unsigned long *)(GPIO_BASE_ADDR + 0x8C)) -#define IO2_INT_EN_R (*(volatile unsigned long *)(GPIO_BASE_ADDR + 0xB0)) +#define IO2_INT_EN_R (*(volatile unsigned long *)(GPIO_BASE_ADDR + 0xB0)) #define IO2_INT_EN_F (*(volatile unsigned long *)(GPIO_BASE_ADDR + 0xB4)) #define IO2_INT_STAT_R (*(volatile unsigned long *)(GPIO_BASE_ADDR + 0xA4)) #define IO2_INT_STAT_F (*(volatile unsigned long *)(GPIO_BASE_ADDR + 0xA8)) @@ -162,227 +162,227 @@ these registers are known as "VICVectPriority(x)". */ #define IO_INT_STAT (*(volatile unsigned long *)(GPIO_BASE_ADDR + 0x80)) -#define PARTCFG_BASE_ADDR 0x3FFF8000 -#define PARTCFG (*(volatile unsigned long *)(PARTCFG_BASE_ADDR + 0x00)) +#define PARTCFG_BASE_ADDR 0x3FFF8000 +#define PARTCFG (*(volatile unsigned long *)(PARTCFG_BASE_ADDR + 0x00)) /* Fast I/O setup */ -#define FIO_BASE_ADDR 0x3FFFC000 -#define FIO0DIR (*(volatile unsigned long *)(FIO_BASE_ADDR + 0x00)) +#define FIO_BASE_ADDR 0x3FFFC000 +#define FIO0DIR (*(volatile unsigned long *)(FIO_BASE_ADDR + 0x00)) #define FIO0MASK (*(volatile unsigned long *)(FIO_BASE_ADDR + 0x10)) #define FIO0PIN (*(volatile unsigned long *)(FIO_BASE_ADDR + 0x14)) #define FIO0SET (*(volatile unsigned long *)(FIO_BASE_ADDR + 0x18)) #define FIO0CLR (*(volatile unsigned long *)(FIO_BASE_ADDR + 0x1C)) -#define FIO1DIR (*(volatile unsigned long *)(FIO_BASE_ADDR + 0x20)) +#define FIO1DIR (*(volatile unsigned long *)(FIO_BASE_ADDR + 0x20)) #define FIO1MASK (*(volatile unsigned long *)(FIO_BASE_ADDR + 0x30)) #define FIO1PIN (*(volatile unsigned long *)(FIO_BASE_ADDR + 0x34)) #define FIO1SET (*(volatile unsigned long *)(FIO_BASE_ADDR + 0x38)) #define FIO1CLR (*(volatile unsigned long *)(FIO_BASE_ADDR + 0x3C)) -#define FIO2DIR (*(volatile unsigned long *)(FIO_BASE_ADDR + 0x40)) +#define FIO2DIR (*(volatile unsigned long *)(FIO_BASE_ADDR + 0x40)) #define FIO2MASK (*(volatile unsigned long *)(FIO_BASE_ADDR + 0x50)) #define FIO2PIN (*(volatile unsigned long *)(FIO_BASE_ADDR + 0x54)) #define FIO2SET (*(volatile unsigned long *)(FIO_BASE_ADDR + 0x58)) #define FIO2CLR (*(volatile unsigned long *)(FIO_BASE_ADDR + 0x5C)) -#define FIO3DIR (*(volatile unsigned long *)(FIO_BASE_ADDR + 0x60)) +#define FIO3DIR (*(volatile unsigned long *)(FIO_BASE_ADDR + 0x60)) #define FIO3MASK (*(volatile unsigned long *)(FIO_BASE_ADDR + 0x70)) #define FIO3PIN (*(volatile unsigned long *)(FIO_BASE_ADDR + 0x74)) #define FIO3SET (*(volatile unsigned long *)(FIO_BASE_ADDR + 0x78)) #define FIO3CLR (*(volatile unsigned long *)(FIO_BASE_ADDR + 0x7C)) -#define FIO4DIR (*(volatile unsigned long *)(FIO_BASE_ADDR + 0x80)) +#define FIO4DIR (*(volatile unsigned long *)(FIO_BASE_ADDR + 0x80)) #define FIO4MASK (*(volatile unsigned long *)(FIO_BASE_ADDR + 0x90)) #define FIO4PIN (*(volatile unsigned long *)(FIO_BASE_ADDR + 0x94)) #define FIO4SET (*(volatile unsigned long *)(FIO_BASE_ADDR + 0x98)) #define FIO4CLR (*(volatile unsigned long *)(FIO_BASE_ADDR + 0x9C)) /* FIOs can be accessed through WORD, HALF-WORD or BYTE. */ -#define FIO0DIR0 (*(volatile unsigned char *)(FIO_BASE_ADDR + 0x00)) -#define FIO1DIR0 (*(volatile unsigned char *)(FIO_BASE_ADDR + 0x20)) -#define FIO2DIR0 (*(volatile unsigned char *)(FIO_BASE_ADDR + 0x40)) -#define FIO3DIR0 (*(volatile unsigned char *)(FIO_BASE_ADDR + 0x60)) -#define FIO4DIR0 (*(volatile unsigned char *)(FIO_BASE_ADDR + 0x80)) +#define FIO0DIR0 (*(volatile unsigned char *)(FIO_BASE_ADDR + 0x00)) +#define FIO1DIR0 (*(volatile unsigned char *)(FIO_BASE_ADDR + 0x20)) +#define FIO2DIR0 (*(volatile unsigned char *)(FIO_BASE_ADDR + 0x40)) +#define FIO3DIR0 (*(volatile unsigned char *)(FIO_BASE_ADDR + 0x60)) +#define FIO4DIR0 (*(volatile unsigned char *)(FIO_BASE_ADDR + 0x80)) -#define FIO0DIR1 (*(volatile unsigned char *)(FIO_BASE_ADDR + 0x01)) -#define FIO1DIR1 (*(volatile unsigned char *)(FIO_BASE_ADDR + 0x21)) -#define FIO2DIR1 (*(volatile unsigned char *)(FIO_BASE_ADDR + 0x41)) -#define FIO3DIR1 (*(volatile unsigned char *)(FIO_BASE_ADDR + 0x61)) -#define FIO4DIR1 (*(volatile unsigned char *)(FIO_BASE_ADDR + 0x81)) +#define FIO0DIR1 (*(volatile unsigned char *)(FIO_BASE_ADDR + 0x01)) +#define FIO1DIR1 (*(volatile unsigned char *)(FIO_BASE_ADDR + 0x21)) +#define FIO2DIR1 (*(volatile unsigned char *)(FIO_BASE_ADDR + 0x41)) +#define FIO3DIR1 (*(volatile unsigned char *)(FIO_BASE_ADDR + 0x61)) +#define FIO4DIR1 (*(volatile unsigned char *)(FIO_BASE_ADDR + 0x81)) -#define FIO0DIR2 (*(volatile unsigned char *)(FIO_BASE_ADDR + 0x02)) -#define FIO1DIR2 (*(volatile unsigned char *)(FIO_BASE_ADDR + 0x22)) -#define FIO2DIR2 (*(volatile unsigned char *)(FIO_BASE_ADDR + 0x42)) -#define FIO3DIR2 (*(volatile unsigned char *)(FIO_BASE_ADDR + 0x62)) -#define FIO4DIR2 (*(volatile unsigned char *)(FIO_BASE_ADDR + 0x82)) +#define FIO0DIR2 (*(volatile unsigned char *)(FIO_BASE_ADDR + 0x02)) +#define FIO1DIR2 (*(volatile unsigned char *)(FIO_BASE_ADDR + 0x22)) +#define FIO2DIR2 (*(volatile unsigned char *)(FIO_BASE_ADDR + 0x42)) +#define FIO3DIR2 (*(volatile unsigned char *)(FIO_BASE_ADDR + 0x62)) +#define FIO4DIR2 (*(volatile unsigned char *)(FIO_BASE_ADDR + 0x82)) -#define FIO0DIR3 (*(volatile unsigned char *)(FIO_BASE_ADDR + 0x03)) -#define FIO1DIR3 (*(volatile unsigned char *)(FIO_BASE_ADDR + 0x23)) -#define FIO2DIR3 (*(volatile unsigned char *)(FIO_BASE_ADDR + 0x43)) -#define FIO3DIR3 (*(volatile unsigned char *)(FIO_BASE_ADDR + 0x63)) -#define FIO4DIR3 (*(volatile unsigned char *)(FIO_BASE_ADDR + 0x83)) +#define FIO0DIR3 (*(volatile unsigned char *)(FIO_BASE_ADDR + 0x03)) +#define FIO1DIR3 (*(volatile unsigned char *)(FIO_BASE_ADDR + 0x23)) +#define FIO2DIR3 (*(volatile unsigned char *)(FIO_BASE_ADDR + 0x43)) +#define FIO3DIR3 (*(volatile unsigned char *)(FIO_BASE_ADDR + 0x63)) +#define FIO4DIR3 (*(volatile unsigned char *)(FIO_BASE_ADDR + 0x83)) -#define FIO0DIRL (*(volatile unsigned short *)(FIO_BASE_ADDR + 0x00)) -#define FIO1DIRL (*(volatile unsigned short *)(FIO_BASE_ADDR + 0x20)) -#define FIO2DIRL (*(volatile unsigned short *)(FIO_BASE_ADDR + 0x40)) -#define FIO3DIRL (*(volatile unsigned short *)(FIO_BASE_ADDR + 0x60)) -#define FIO4DIRL (*(volatile unsigned short *)(FIO_BASE_ADDR + 0x80)) +#define FIO0DIRL (*(volatile unsigned short *)(FIO_BASE_ADDR + 0x00)) +#define FIO1DIRL (*(volatile unsigned short *)(FIO_BASE_ADDR + 0x20)) +#define FIO2DIRL (*(volatile unsigned short *)(FIO_BASE_ADDR + 0x40)) +#define FIO3DIRL (*(volatile unsigned short *)(FIO_BASE_ADDR + 0x60)) +#define FIO4DIRL (*(volatile unsigned short *)(FIO_BASE_ADDR + 0x80)) -#define FIO0DIRU (*(volatile unsigned short *)(FIO_BASE_ADDR + 0x02)) -#define FIO1DIRU (*(volatile unsigned short *)(FIO_BASE_ADDR + 0x22)) -#define FIO2DIRU (*(volatile unsigned short *)(FIO_BASE_ADDR + 0x42)) -#define FIO3DIRU (*(volatile unsigned short *)(FIO_BASE_ADDR + 0x62)) -#define FIO4DIRU (*(volatile unsigned short *)(FIO_BASE_ADDR + 0x82)) +#define FIO0DIRU (*(volatile unsigned short *)(FIO_BASE_ADDR + 0x02)) +#define FIO1DIRU (*(volatile unsigned short *)(FIO_BASE_ADDR + 0x22)) +#define FIO2DIRU (*(volatile unsigned short *)(FIO_BASE_ADDR + 0x42)) +#define FIO3DIRU (*(volatile unsigned short *)(FIO_BASE_ADDR + 0x62)) +#define FIO4DIRU (*(volatile unsigned short *)(FIO_BASE_ADDR + 0x82)) -#define FIO0MASK0 (*(volatile unsigned char *)(FIO_BASE_ADDR + 0x10)) -#define FIO1MASK0 (*(volatile unsigned char *)(FIO_BASE_ADDR + 0x30)) -#define FIO2MASK0 (*(volatile unsigned char *)(FIO_BASE_ADDR + 0x50)) -#define FIO3MASK0 (*(volatile unsigned char *)(FIO_BASE_ADDR + 0x70)) -#define FIO4MASK0 (*(volatile unsigned char *)(FIO_BASE_ADDR + 0x90)) +#define FIO0MASK0 (*(volatile unsigned char *)(FIO_BASE_ADDR + 0x10)) +#define FIO1MASK0 (*(volatile unsigned char *)(FIO_BASE_ADDR + 0x30)) +#define FIO2MASK0 (*(volatile unsigned char *)(FIO_BASE_ADDR + 0x50)) +#define FIO3MASK0 (*(volatile unsigned char *)(FIO_BASE_ADDR + 0x70)) +#define FIO4MASK0 (*(volatile unsigned char *)(FIO_BASE_ADDR + 0x90)) -#define FIO0MASK1 (*(volatile unsigned char *)(FIO_BASE_ADDR + 0x11)) -#define FIO1MASK1 (*(volatile unsigned char *)(FIO_BASE_ADDR + 0x21)) -#define FIO2MASK1 (*(volatile unsigned char *)(FIO_BASE_ADDR + 0x51)) -#define FIO3MASK1 (*(volatile unsigned char *)(FIO_BASE_ADDR + 0x71)) -#define FIO4MASK1 (*(volatile unsigned char *)(FIO_BASE_ADDR + 0x91)) +#define FIO0MASK1 (*(volatile unsigned char *)(FIO_BASE_ADDR + 0x11)) +#define FIO1MASK1 (*(volatile unsigned char *)(FIO_BASE_ADDR + 0x21)) +#define FIO2MASK1 (*(volatile unsigned char *)(FIO_BASE_ADDR + 0x51)) +#define FIO3MASK1 (*(volatile unsigned char *)(FIO_BASE_ADDR + 0x71)) +#define FIO4MASK1 (*(volatile unsigned char *)(FIO_BASE_ADDR + 0x91)) -#define FIO0MASK2 (*(volatile unsigned char *)(FIO_BASE_ADDR + 0x12)) -#define FIO1MASK2 (*(volatile unsigned char *)(FIO_BASE_ADDR + 0x32)) -#define FIO2MASK2 (*(volatile unsigned char *)(FIO_BASE_ADDR + 0x52)) -#define FIO3MASK2 (*(volatile unsigned char *)(FIO_BASE_ADDR + 0x72)) -#define FIO4MASK2 (*(volatile unsigned char *)(FIO_BASE_ADDR + 0x92)) +#define FIO0MASK2 (*(volatile unsigned char *)(FIO_BASE_ADDR + 0x12)) +#define FIO1MASK2 (*(volatile unsigned char *)(FIO_BASE_ADDR + 0x32)) +#define FIO2MASK2 (*(volatile unsigned char *)(FIO_BASE_ADDR + 0x52)) +#define FIO3MASK2 (*(volatile unsigned char *)(FIO_BASE_ADDR + 0x72)) +#define FIO4MASK2 (*(volatile unsigned char *)(FIO_BASE_ADDR + 0x92)) -#define FIO0MASK3 (*(volatile unsigned char *)(FIO_BASE_ADDR + 0x13)) -#define FIO1MASK3 (*(volatile unsigned char *)(FIO_BASE_ADDR + 0x33)) -#define FIO2MASK3 (*(volatile unsigned char *)(FIO_BASE_ADDR + 0x53)) -#define FIO3MASK3 (*(volatile unsigned char *)(FIO_BASE_ADDR + 0x73)) -#define FIO4MASK3 (*(volatile unsigned char *)(FIO_BASE_ADDR + 0x93)) +#define FIO0MASK3 (*(volatile unsigned char *)(FIO_BASE_ADDR + 0x13)) +#define FIO1MASK3 (*(volatile unsigned char *)(FIO_BASE_ADDR + 0x33)) +#define FIO2MASK3 (*(volatile unsigned char *)(FIO_BASE_ADDR + 0x53)) +#define FIO3MASK3 (*(volatile unsigned char *)(FIO_BASE_ADDR + 0x73)) +#define FIO4MASK3 (*(volatile unsigned char *)(FIO_BASE_ADDR + 0x93)) -#define FIO0MASKL (*(volatile unsigned short *)(FIO_BASE_ADDR + 0x10)) -#define FIO1MASKL (*(volatile unsigned short *)(FIO_BASE_ADDR + 0x30)) -#define FIO2MASKL (*(volatile unsigned short *)(FIO_BASE_ADDR + 0x50)) -#define FIO3MASKL (*(volatile unsigned short *)(FIO_BASE_ADDR + 0x70)) -#define FIO4MASKL (*(volatile unsigned short *)(FIO_BASE_ADDR + 0x90)) +#define FIO0MASKL (*(volatile unsigned short *)(FIO_BASE_ADDR + 0x10)) +#define FIO1MASKL (*(volatile unsigned short *)(FIO_BASE_ADDR + 0x30)) +#define FIO2MASKL (*(volatile unsigned short *)(FIO_BASE_ADDR + 0x50)) +#define FIO3MASKL (*(volatile unsigned short *)(FIO_BASE_ADDR + 0x70)) +#define FIO4MASKL (*(volatile unsigned short *)(FIO_BASE_ADDR + 0x90)) -#define FIO0MASKU (*(volatile unsigned short *)(FIO_BASE_ADDR + 0x12)) -#define FIO1MASKU (*(volatile unsigned short *)(FIO_BASE_ADDR + 0x32)) -#define FIO2MASKU (*(volatile unsigned short *)(FIO_BASE_ADDR + 0x52)) -#define FIO3MASKU (*(volatile unsigned short *)(FIO_BASE_ADDR + 0x72)) -#define FIO4MASKU (*(volatile unsigned short *)(FIO_BASE_ADDR + 0x92)) +#define FIO0MASKU (*(volatile unsigned short *)(FIO_BASE_ADDR + 0x12)) +#define FIO1MASKU (*(volatile unsigned short *)(FIO_BASE_ADDR + 0x32)) +#define FIO2MASKU (*(volatile unsigned short *)(FIO_BASE_ADDR + 0x52)) +#define FIO3MASKU (*(volatile unsigned short *)(FIO_BASE_ADDR + 0x72)) +#define FIO4MASKU (*(volatile unsigned short *)(FIO_BASE_ADDR + 0x92)) -#define FIO0PIN0 (*(volatile unsigned char *)(FIO_BASE_ADDR + 0x14)) -#define FIO1PIN0 (*(volatile unsigned char *)(FIO_BASE_ADDR + 0x34)) -#define FIO2PIN0 (*(volatile unsigned char *)(FIO_BASE_ADDR + 0x54)) -#define FIO3PIN0 (*(volatile unsigned char *)(FIO_BASE_ADDR + 0x74)) -#define FIO4PIN0 (*(volatile unsigned char *)(FIO_BASE_ADDR + 0x94)) +#define FIO0PIN0 (*(volatile unsigned char *)(FIO_BASE_ADDR + 0x14)) +#define FIO1PIN0 (*(volatile unsigned char *)(FIO_BASE_ADDR + 0x34)) +#define FIO2PIN0 (*(volatile unsigned char *)(FIO_BASE_ADDR + 0x54)) +#define FIO3PIN0 (*(volatile unsigned char *)(FIO_BASE_ADDR + 0x74)) +#define FIO4PIN0 (*(volatile unsigned char *)(FIO_BASE_ADDR + 0x94)) -#define FIO0PIN1 (*(volatile unsigned char *)(FIO_BASE_ADDR + 0x15)) -#define FIO1PIN1 (*(volatile unsigned char *)(FIO_BASE_ADDR + 0x35)) -#define FIO2PIN1 (*(volatile unsigned char *)(FIO_BASE_ADDR + 0x55)) -#define FIO3PIN1 (*(volatile unsigned char *)(FIO_BASE_ADDR + 0x75)) -#define FIO4PIN1 (*(volatile unsigned char *)(FIO_BASE_ADDR + 0x95)) +#define FIO0PIN1 (*(volatile unsigned char *)(FIO_BASE_ADDR + 0x15)) +#define FIO1PIN1 (*(volatile unsigned char *)(FIO_BASE_ADDR + 0x35)) +#define FIO2PIN1 (*(volatile unsigned char *)(FIO_BASE_ADDR + 0x55)) +#define FIO3PIN1 (*(volatile unsigned char *)(FIO_BASE_ADDR + 0x75)) +#define FIO4PIN1 (*(volatile unsigned char *)(FIO_BASE_ADDR + 0x95)) -#define FIO0PIN2 (*(volatile unsigned char *)(FIO_BASE_ADDR + 0x16)) -#define FIO1PIN2 (*(volatile unsigned char *)(FIO_BASE_ADDR + 0x36)) -#define FIO2PIN2 (*(volatile unsigned char *)(FIO_BASE_ADDR + 0x56)) -#define FIO3PIN2 (*(volatile unsigned char *)(FIO_BASE_ADDR + 0x76)) -#define FIO4PIN2 (*(volatile unsigned char *)(FIO_BASE_ADDR + 0x96)) +#define FIO0PIN2 (*(volatile unsigned char *)(FIO_BASE_ADDR + 0x16)) +#define FIO1PIN2 (*(volatile unsigned char *)(FIO_BASE_ADDR + 0x36)) +#define FIO2PIN2 (*(volatile unsigned char *)(FIO_BASE_ADDR + 0x56)) +#define FIO3PIN2 (*(volatile unsigned char *)(FIO_BASE_ADDR + 0x76)) +#define FIO4PIN2 (*(volatile unsigned char *)(FIO_BASE_ADDR + 0x96)) -#define FIO0PIN3 (*(volatile unsigned char *)(FIO_BASE_ADDR + 0x17)) -#define FIO1PIN3 (*(volatile unsigned char *)(FIO_BASE_ADDR + 0x37)) -#define FIO2PIN3 (*(volatile unsigned char *)(FIO_BASE_ADDR + 0x57)) -#define FIO3PIN3 (*(volatile unsigned char *)(FIO_BASE_ADDR + 0x77)) -#define FIO4PIN3 (*(volatile unsigned char *)(FIO_BASE_ADDR + 0x97)) +#define FIO0PIN3 (*(volatile unsigned char *)(FIO_BASE_ADDR + 0x17)) +#define FIO1PIN3 (*(volatile unsigned char *)(FIO_BASE_ADDR + 0x37)) +#define FIO2PIN3 (*(volatile unsigned char *)(FIO_BASE_ADDR + 0x57)) +#define FIO3PIN3 (*(volatile unsigned char *)(FIO_BASE_ADDR + 0x77)) +#define FIO4PIN3 (*(volatile unsigned char *)(FIO_BASE_ADDR + 0x97)) -#define FIO0PINL (*(volatile unsigned short *)(FIO_BASE_ADDR + 0x14)) -#define FIO1PINL (*(volatile unsigned short *)(FIO_BASE_ADDR + 0x34)) -#define FIO2PINL (*(volatile unsigned short *)(FIO_BASE_ADDR + 0x54)) -#define FIO3PINL (*(volatile unsigned short *)(FIO_BASE_ADDR + 0x74)) -#define FIO4PINL (*(volatile unsigned short *)(FIO_BASE_ADDR + 0x94)) +#define FIO0PINL (*(volatile unsigned short *)(FIO_BASE_ADDR + 0x14)) +#define FIO1PINL (*(volatile unsigned short *)(FIO_BASE_ADDR + 0x34)) +#define FIO2PINL (*(volatile unsigned short *)(FIO_BASE_ADDR + 0x54)) +#define FIO3PINL (*(volatile unsigned short *)(FIO_BASE_ADDR + 0x74)) +#define FIO4PINL (*(volatile unsigned short *)(FIO_BASE_ADDR + 0x94)) -#define FIO0PINU (*(volatile unsigned short *)(FIO_BASE_ADDR + 0x16)) -#define FIO1PINU (*(volatile unsigned short *)(FIO_BASE_ADDR + 0x36)) -#define FIO2PINU (*(volatile unsigned short *)(FIO_BASE_ADDR + 0x56)) -#define FIO3PINU (*(volatile unsigned short *)(FIO_BASE_ADDR + 0x76)) -#define FIO4PINU (*(volatile unsigned short *)(FIO_BASE_ADDR + 0x96)) +#define FIO0PINU (*(volatile unsigned short *)(FIO_BASE_ADDR + 0x16)) +#define FIO1PINU (*(volatile unsigned short *)(FIO_BASE_ADDR + 0x36)) +#define FIO2PINU (*(volatile unsigned short *)(FIO_BASE_ADDR + 0x56)) +#define FIO3PINU (*(volatile unsigned short *)(FIO_BASE_ADDR + 0x76)) +#define FIO4PINU (*(volatile unsigned short *)(FIO_BASE_ADDR + 0x96)) -#define FIO0SET0 (*(volatile unsigned char *)(FIO_BASE_ADDR + 0x18)) -#define FIO1SET0 (*(volatile unsigned char *)(FIO_BASE_ADDR + 0x38)) -#define FIO2SET0 (*(volatile unsigned char *)(FIO_BASE_ADDR + 0x58)) -#define FIO3SET0 (*(volatile unsigned char *)(FIO_BASE_ADDR + 0x78)) -#define FIO4SET0 (*(volatile unsigned char *)(FIO_BASE_ADDR + 0x98)) +#define FIO0SET0 (*(volatile unsigned char *)(FIO_BASE_ADDR + 0x18)) +#define FIO1SET0 (*(volatile unsigned char *)(FIO_BASE_ADDR + 0x38)) +#define FIO2SET0 (*(volatile unsigned char *)(FIO_BASE_ADDR + 0x58)) +#define FIO3SET0 (*(volatile unsigned char *)(FIO_BASE_ADDR + 0x78)) +#define FIO4SET0 (*(volatile unsigned char *)(FIO_BASE_ADDR + 0x98)) -#define FIO0SET1 (*(volatile unsigned char *)(FIO_BASE_ADDR + 0x19)) -#define FIO1SET1 (*(volatile unsigned char *)(FIO_BASE_ADDR + 0x29)) -#define FIO2SET1 (*(volatile unsigned char *)(FIO_BASE_ADDR + 0x59)) -#define FIO3SET1 (*(volatile unsigned char *)(FIO_BASE_ADDR + 0x79)) -#define FIO4SET1 (*(volatile unsigned char *)(FIO_BASE_ADDR + 0x99)) +#define FIO0SET1 (*(volatile unsigned char *)(FIO_BASE_ADDR + 0x19)) +#define FIO1SET1 (*(volatile unsigned char *)(FIO_BASE_ADDR + 0x29)) +#define FIO2SET1 (*(volatile unsigned char *)(FIO_BASE_ADDR + 0x59)) +#define FIO3SET1 (*(volatile unsigned char *)(FIO_BASE_ADDR + 0x79)) +#define FIO4SET1 (*(volatile unsigned char *)(FIO_BASE_ADDR + 0x99)) -#define FIO0SET2 (*(volatile unsigned char *)(FIO_BASE_ADDR + 0x1A)) -#define FIO1SET2 (*(volatile unsigned char *)(FIO_BASE_ADDR + 0x3A)) -#define FIO2SET2 (*(volatile unsigned char *)(FIO_BASE_ADDR + 0x5A)) -#define FIO3SET2 (*(volatile unsigned char *)(FIO_BASE_ADDR + 0x7A)) -#define FIO4SET2 (*(volatile unsigned char *)(FIO_BASE_ADDR + 0x9A)) +#define FIO0SET2 (*(volatile unsigned char *)(FIO_BASE_ADDR + 0x1A)) +#define FIO1SET2 (*(volatile unsigned char *)(FIO_BASE_ADDR + 0x3A)) +#define FIO2SET2 (*(volatile unsigned char *)(FIO_BASE_ADDR + 0x5A)) +#define FIO3SET2 (*(volatile unsigned char *)(FIO_BASE_ADDR + 0x7A)) +#define FIO4SET2 (*(volatile unsigned char *)(FIO_BASE_ADDR + 0x9A)) -#define FIO0SET3 (*(volatile unsigned char *)(FIO_BASE_ADDR + 0x1B)) -#define FIO1SET3 (*(volatile unsigned char *)(FIO_BASE_ADDR + 0x3B)) -#define FIO2SET3 (*(volatile unsigned char *)(FIO_BASE_ADDR + 0x5B)) -#define FIO3SET3 (*(volatile unsigned char *)(FIO_BASE_ADDR + 0x7B)) -#define FIO4SET3 (*(volatile unsigned char *)(FIO_BASE_ADDR + 0x9B)) +#define FIO0SET3 (*(volatile unsigned char *)(FIO_BASE_ADDR + 0x1B)) +#define FIO1SET3 (*(volatile unsigned char *)(FIO_BASE_ADDR + 0x3B)) +#define FIO2SET3 (*(volatile unsigned char *)(FIO_BASE_ADDR + 0x5B)) +#define FIO3SET3 (*(volatile unsigned char *)(FIO_BASE_ADDR + 0x7B)) +#define FIO4SET3 (*(volatile unsigned char *)(FIO_BASE_ADDR + 0x9B)) -#define FIO0SETL (*(volatile unsigned short *)(FIO_BASE_ADDR + 0x18)) -#define FIO1SETL (*(volatile unsigned short *)(FIO_BASE_ADDR + 0x38)) -#define FIO2SETL (*(volatile unsigned short *)(FIO_BASE_ADDR + 0x58)) -#define FIO3SETL (*(volatile unsigned short *)(FIO_BASE_ADDR + 0x78)) -#define FIO4SETL (*(volatile unsigned short *)(FIO_BASE_ADDR + 0x98)) +#define FIO0SETL (*(volatile unsigned short *)(FIO_BASE_ADDR + 0x18)) +#define FIO1SETL (*(volatile unsigned short *)(FIO_BASE_ADDR + 0x38)) +#define FIO2SETL (*(volatile unsigned short *)(FIO_BASE_ADDR + 0x58)) +#define FIO3SETL (*(volatile unsigned short *)(FIO_BASE_ADDR + 0x78)) +#define FIO4SETL (*(volatile unsigned short *)(FIO_BASE_ADDR + 0x98)) -#define FIO0SETU (*(volatile unsigned short *)(FIO_BASE_ADDR + 0x1A)) -#define FIO1SETU (*(volatile unsigned short *)(FIO_BASE_ADDR + 0x3A)) -#define FIO2SETU (*(volatile unsigned short *)(FIO_BASE_ADDR + 0x5A)) -#define FIO3SETU (*(volatile unsigned short *)(FIO_BASE_ADDR + 0x7A)) -#define FIO4SETU (*(volatile unsigned short *)(FIO_BASE_ADDR + 0x9A)) +#define FIO0SETU (*(volatile unsigned short *)(FIO_BASE_ADDR + 0x1A)) +#define FIO1SETU (*(volatile unsigned short *)(FIO_BASE_ADDR + 0x3A)) +#define FIO2SETU (*(volatile unsigned short *)(FIO_BASE_ADDR + 0x5A)) +#define FIO3SETU (*(volatile unsigned short *)(FIO_BASE_ADDR + 0x7A)) +#define FIO4SETU (*(volatile unsigned short *)(FIO_BASE_ADDR + 0x9A)) -#define FIO0CLR0 (*(volatile unsigned char *)(FIO_BASE_ADDR + 0x1C)) -#define FIO1CLR0 (*(volatile unsigned char *)(FIO_BASE_ADDR + 0x3C)) -#define FIO2CLR0 (*(volatile unsigned char *)(FIO_BASE_ADDR + 0x5C)) -#define FIO3CLR0 (*(volatile unsigned char *)(FIO_BASE_ADDR + 0x7C)) -#define FIO4CLR0 (*(volatile unsigned char *)(FIO_BASE_ADDR + 0x9C)) +#define FIO0CLR0 (*(volatile unsigned char *)(FIO_BASE_ADDR + 0x1C)) +#define FIO1CLR0 (*(volatile unsigned char *)(FIO_BASE_ADDR + 0x3C)) +#define FIO2CLR0 (*(volatile unsigned char *)(FIO_BASE_ADDR + 0x5C)) +#define FIO3CLR0 (*(volatile unsigned char *)(FIO_BASE_ADDR + 0x7C)) +#define FIO4CLR0 (*(volatile unsigned char *)(FIO_BASE_ADDR + 0x9C)) -#define FIO0CLR1 (*(volatile unsigned char *)(FIO_BASE_ADDR + 0x1D)) -#define FIO1CLR1 (*(volatile unsigned char *)(FIO_BASE_ADDR + 0x2D)) -#define FIO2CLR1 (*(volatile unsigned char *)(FIO_BASE_ADDR + 0x5D)) -#define FIO3CLR1 (*(volatile unsigned char *)(FIO_BASE_ADDR + 0x7D)) -#define FIO4CLR1 (*(volatile unsigned char *)(FIO_BASE_ADDR + 0x9D)) +#define FIO0CLR1 (*(volatile unsigned char *)(FIO_BASE_ADDR + 0x1D)) +#define FIO1CLR1 (*(volatile unsigned char *)(FIO_BASE_ADDR + 0x2D)) +#define FIO2CLR1 (*(volatile unsigned char *)(FIO_BASE_ADDR + 0x5D)) +#define FIO3CLR1 (*(volatile unsigned char *)(FIO_BASE_ADDR + 0x7D)) +#define FIO4CLR1 (*(volatile unsigned char *)(FIO_BASE_ADDR + 0x9D)) -#define FIO0CLR2 (*(volatile unsigned char *)(FIO_BASE_ADDR + 0x1E)) -#define FIO1CLR2 (*(volatile unsigned char *)(FIO_BASE_ADDR + 0x3E)) -#define FIO2CLR2 (*(volatile unsigned char *)(FIO_BASE_ADDR + 0x5E)) -#define FIO3CLR2 (*(volatile unsigned char *)(FIO_BASE_ADDR + 0x7E)) -#define FIO4CLR2 (*(volatile unsigned char *)(FIO_BASE_ADDR + 0x9E)) +#define FIO0CLR2 (*(volatile unsigned char *)(FIO_BASE_ADDR + 0x1E)) +#define FIO1CLR2 (*(volatile unsigned char *)(FIO_BASE_ADDR + 0x3E)) +#define FIO2CLR2 (*(volatile unsigned char *)(FIO_BASE_ADDR + 0x5E)) +#define FIO3CLR2 (*(volatile unsigned char *)(FIO_BASE_ADDR + 0x7E)) +#define FIO4CLR2 (*(volatile unsigned char *)(FIO_BASE_ADDR + 0x9E)) -#define FIO0CLR3 (*(volatile unsigned char *)(FIO_BASE_ADDR + 0x1F)) -#define FIO1CLR3 (*(volatile unsigned char *)(FIO_BASE_ADDR + 0x3F)) -#define FIO2CLR3 (*(volatile unsigned char *)(FIO_BASE_ADDR + 0x5F)) -#define FIO3CLR3 (*(volatile unsigned char *)(FIO_BASE_ADDR + 0x7F)) -#define FIO4CLR3 (*(volatile unsigned char *)(FIO_BASE_ADDR + 0x9F)) +#define FIO0CLR3 (*(volatile unsigned char *)(FIO_BASE_ADDR + 0x1F)) +#define FIO1CLR3 (*(volatile unsigned char *)(FIO_BASE_ADDR + 0x3F)) +#define FIO2CLR3 (*(volatile unsigned char *)(FIO_BASE_ADDR + 0x5F)) +#define FIO3CLR3 (*(volatile unsigned char *)(FIO_BASE_ADDR + 0x7F)) +#define FIO4CLR3 (*(volatile unsigned char *)(FIO_BASE_ADDR + 0x9F)) -#define FIO0CLRL (*(volatile unsigned short *)(FIO_BASE_ADDR + 0x1C)) -#define FIO1CLRL (*(volatile unsigned short *)(FIO_BASE_ADDR + 0x3C)) -#define FIO2CLRL (*(volatile unsigned short *)(FIO_BASE_ADDR + 0x5C)) -#define FIO3CLRL (*(volatile unsigned short *)(FIO_BASE_ADDR + 0x7C)) -#define FIO4CLRL (*(volatile unsigned short *)(FIO_BASE_ADDR + 0x9C)) +#define FIO0CLRL (*(volatile unsigned short *)(FIO_BASE_ADDR + 0x1C)) +#define FIO1CLRL (*(volatile unsigned short *)(FIO_BASE_ADDR + 0x3C)) +#define FIO2CLRL (*(volatile unsigned short *)(FIO_BASE_ADDR + 0x5C)) +#define FIO3CLRL (*(volatile unsigned short *)(FIO_BASE_ADDR + 0x7C)) +#define FIO4CLRL (*(volatile unsigned short *)(FIO_BASE_ADDR + 0x9C)) -#define FIO0CLRU (*(volatile unsigned short *)(FIO_BASE_ADDR + 0x1E)) -#define FIO1CLRU (*(volatile unsigned short *)(FIO_BASE_ADDR + 0x3E)) -#define FIO2CLRU (*(volatile unsigned short *)(FIO_BASE_ADDR + 0x5E)) -#define FIO3CLRU (*(volatile unsigned short *)(FIO_BASE_ADDR + 0x7E)) -#define FIO4CLRU (*(volatile unsigned short *)(FIO_BASE_ADDR + 0x9E)) +#define FIO0CLRU (*(volatile unsigned short *)(FIO_BASE_ADDR + 0x1E)) +#define FIO1CLRU (*(volatile unsigned short *)(FIO_BASE_ADDR + 0x3E)) +#define FIO2CLRU (*(volatile unsigned short *)(FIO_BASE_ADDR + 0x5E)) +#define FIO3CLRU (*(volatile unsigned short *)(FIO_BASE_ADDR + 0x7E)) +#define FIO4CLRU (*(volatile unsigned short *)(FIO_BASE_ADDR + 0x9E)) /* System Control Block(SCB) modules include Memory Accelerator Module, -Phase Locked Loop, VPB divider, Power Control, External Interrupt, +Phase Locked Loop, VPB divider, Power Control, External Interrupt, Reset, and Code Security/Debugging */ -#define SCB_BASE_ADDR 0xE01FC000 +#define SCB_BASE_ADDR 0xE01FC000 /* Memory Accelerator Module (MAM) */ #define MAMCR (*(volatile unsigned long *)(SCB_BASE_ADDR + 0x000)) @@ -405,7 +405,7 @@ Reset, and Code Security/Debugging */ #define CLKSRCSEL (*(volatile unsigned long *)(SCB_BASE_ADDR + 0x10C)) #define PCLKSEL0 (*(volatile unsigned long *)(SCB_BASE_ADDR + 0x1A8)) #define PCLKSEL1 (*(volatile unsigned long *)(SCB_BASE_ADDR + 0x1AC)) - + /* External Interrupts */ #define EXTINT (*(volatile unsigned long *)(SCB_BASE_ADDR + 0x140)) #define INTWAKE (*(volatile unsigned long *)(SCB_BASE_ADDR + 0x144)) @@ -423,22 +423,22 @@ Reset, and Code Security/Debugging */ #define AHBCFG2 (*(volatile unsigned long *)(SCB_BASE_ADDR + 0x18C)) /* System Controls and Status */ -#define SCS (*(volatile unsigned long *)(SCB_BASE_ADDR + 0x1A0)) +#define SCS (*(volatile unsigned long *)(SCB_BASE_ADDR + 0x1A0)) -/* MPMC(EMC) registers, note: all the external memory controller(EMC) registers +/* MPMC(EMC) registers, note: all the external memory controller(EMC) registers are for LPC24xx only. */ -#define STATIC_MEM0_BASE 0x80000000 -#define STATIC_MEM1_BASE 0x81000000 -#define STATIC_MEM2_BASE 0x82000000 -#define STATIC_MEM3_BASE 0x83000000 +#define STATIC_MEM0_BASE 0x80000000 +#define STATIC_MEM1_BASE 0x81000000 +#define STATIC_MEM2_BASE 0x82000000 +#define STATIC_MEM3_BASE 0x83000000 -#define DYNAMIC_MEM0_BASE 0xA0000000 -#define DYNAMIC_MEM1_BASE 0xB0000000 -#define DYNAMIC_MEM2_BASE 0xC0000000 -#define DYNAMIC_MEM3_BASE 0xD0000000 +#define DYNAMIC_MEM0_BASE 0xA0000000 +#define DYNAMIC_MEM1_BASE 0xB0000000 +#define DYNAMIC_MEM2_BASE 0xC0000000 +#define DYNAMIC_MEM3_BASE 0xD0000000 /* External Memory Controller (EMC) */ -#define EMC_BASE_ADDR 0xFFE08000 +#define EMC_BASE_ADDR 0xFFE08000 #define EMC_CTRL (*(volatile unsigned long *)(EMC_BASE_ADDR + 0x000)) #define EMC_STAT (*(volatile unsigned long *)(EMC_BASE_ADDR + 0x004)) #define EMC_CONFIG (*(volatile unsigned long *)(EMC_BASE_ADDR + 0x008)) @@ -503,9 +503,9 @@ are for LPC24xx only. */ #define EMC_STA_EXT_WAIT (*(volatile unsigned long *)(EMC_BASE_ADDR + 0x880)) - + /* Timer 0 */ -#define TMR0_BASE_ADDR 0xE0004000 +#define TMR0_BASE_ADDR 0xE0004000 #define T0IR (*(volatile unsigned long *)(TMR0_BASE_ADDR + 0x00)) #define T0TCR (*(volatile unsigned long *)(TMR0_BASE_ADDR + 0x04)) #define T0TC (*(volatile unsigned long *)(TMR0_BASE_ADDR + 0x08)) @@ -525,7 +525,7 @@ are for LPC24xx only. */ #define T0CTCR (*(volatile unsigned long *)(TMR0_BASE_ADDR + 0x70)) /* Timer 1 */ -#define TMR1_BASE_ADDR 0xE0008000 +#define TMR1_BASE_ADDR 0xE0008000 #define T1IR (*(volatile unsigned long *)(TMR1_BASE_ADDR + 0x00)) #define T1TCR (*(volatile unsigned long *)(TMR1_BASE_ADDR + 0x04)) #define T1TC (*(volatile unsigned long *)(TMR1_BASE_ADDR + 0x08)) @@ -545,7 +545,7 @@ are for LPC24xx only. */ #define T1CTCR (*(volatile unsigned long *)(TMR1_BASE_ADDR + 0x70)) /* Timer 2 */ -#define TMR2_BASE_ADDR 0xE0070000 +#define TMR2_BASE_ADDR 0xE0070000 #define T2IR (*(volatile unsigned long *)(TMR2_BASE_ADDR + 0x00)) #define T2TCR (*(volatile unsigned long *)(TMR2_BASE_ADDR + 0x04)) #define T2TC (*(volatile unsigned long *)(TMR2_BASE_ADDR + 0x08)) @@ -565,7 +565,7 @@ are for LPC24xx only. */ #define T2CTCR (*(volatile unsigned long *)(TMR2_BASE_ADDR + 0x70)) /* Timer 3 */ -#define TMR3_BASE_ADDR 0xE0074000 +#define TMR3_BASE_ADDR 0xE0074000 #define T3IR (*(volatile unsigned long *)(TMR3_BASE_ADDR + 0x00)) #define T3TCR (*(volatile unsigned long *)(TMR3_BASE_ADDR + 0x04)) #define T3TC (*(volatile unsigned long *)(TMR3_BASE_ADDR + 0x08)) @@ -586,7 +586,7 @@ are for LPC24xx only. */ /* Pulse Width Modulator (PWM) */ -#define PWM0_BASE_ADDR 0xE0014000 +#define PWM0_BASE_ADDR 0xE0014000 #define PWM0IR (*(volatile unsigned long *)(PWM0_BASE_ADDR + 0x00)) #define PWM0TCR (*(volatile unsigned long *)(PWM0_BASE_ADDR + 0x04)) #define PWM0TC (*(volatile unsigned long *)(PWM0_BASE_ADDR + 0x08)) @@ -610,7 +610,7 @@ are for LPC24xx only. */ #define PWM0LER (*(volatile unsigned long *)(PWM0_BASE_ADDR + 0x50)) #define PWM0CTCR (*(volatile unsigned long *)(PWM0_BASE_ADDR + 0x70)) -#define PWM1_BASE_ADDR 0xE0018000 +#define PWM1_BASE_ADDR 0xE0018000 #define PWM1IR (*(volatile unsigned long *)(PWM1_BASE_ADDR + 0x00)) #define PWM1TCR (*(volatile unsigned long *)(PWM1_BASE_ADDR + 0x04)) #define PWM1TC (*(volatile unsigned long *)(PWM1_BASE_ADDR + 0x08)) @@ -636,7 +636,7 @@ are for LPC24xx only. */ /* Universal Asynchronous Receiver Transmitter 0 (UART0) */ -#define UART0_BASE_ADDR 0xE000C000 +#define UART0_BASE_ADDR 0xE000C000 #define U0RBR (*(volatile unsigned long *)(UART0_BASE_ADDR + 0x00)) #define U0THR (*(volatile unsigned long *)(UART0_BASE_ADDR + 0x00)) #define U0DLL (*(volatile unsigned long *)(UART0_BASE_ADDR + 0x00)) @@ -653,7 +653,7 @@ are for LPC24xx only. */ #define U0TER (*(volatile unsigned long *)(UART0_BASE_ADDR + 0x30)) /* Universal Asynchronous Receiver Transmitter 1 (UART1) */ -#define UART1_BASE_ADDR 0xE0010000 +#define UART1_BASE_ADDR 0xE0010000 #define U1RBR (*(volatile unsigned long *)(UART1_BASE_ADDR + 0x00)) #define U1THR (*(volatile unsigned long *)(UART1_BASE_ADDR + 0x00)) #define U1DLL (*(volatile unsigned long *)(UART1_BASE_ADDR + 0x00)) @@ -671,7 +671,7 @@ are for LPC24xx only. */ #define U1TER (*(volatile unsigned long *)(UART1_BASE_ADDR + 0x30)) /* Universal Asynchronous Receiver Transmitter 2 (UART2) */ -#define UART2_BASE_ADDR 0xE0078000 +#define UART2_BASE_ADDR 0xE0078000 #define U2RBR (*(volatile unsigned long *)(UART2_BASE_ADDR + 0x00)) #define U2THR (*(volatile unsigned long *)(UART2_BASE_ADDR + 0x00)) #define U2DLL (*(volatile unsigned long *)(UART2_BASE_ADDR + 0x00)) @@ -688,7 +688,7 @@ are for LPC24xx only. */ #define U2TER (*(volatile unsigned long *)(UART2_BASE_ADDR + 0x30)) /* Universal Asynchronous Receiver Transmitter 3 (UART3) */ -#define UART3_BASE_ADDR 0xE007C000 +#define UART3_BASE_ADDR 0xE007C000 #define U3RBR (*(volatile unsigned long *)(UART3_BASE_ADDR + 0x00)) #define U3THR (*(volatile unsigned long *)(UART3_BASE_ADDR + 0x00)) #define U3DLL (*(volatile unsigned long *)(UART3_BASE_ADDR + 0x00)) @@ -705,7 +705,7 @@ are for LPC24xx only. */ #define U3TER (*(volatile unsigned long *)(UART3_BASE_ADDR + 0x30)) /* I2C Interface 0 */ -#define I2C0_BASE_ADDR 0xE001C000 +#define I2C0_BASE_ADDR 0xE001C000 #define I20CONSET (*(volatile unsigned long *)(I2C0_BASE_ADDR + 0x00)) #define I20STAT (*(volatile unsigned long *)(I2C0_BASE_ADDR + 0x04)) #define I20DAT (*(volatile unsigned long *)(I2C0_BASE_ADDR + 0x08)) @@ -715,7 +715,7 @@ are for LPC24xx only. */ #define I20CONCLR (*(volatile unsigned long *)(I2C0_BASE_ADDR + 0x18)) /* I2C Interface 1 */ -#define I2C1_BASE_ADDR 0xE005C000 +#define I2C1_BASE_ADDR 0xE005C000 #define I21CONSET (*(volatile unsigned long *)(I2C1_BASE_ADDR + 0x00)) #define I21STAT (*(volatile unsigned long *)(I2C1_BASE_ADDR + 0x04)) #define I21DAT (*(volatile unsigned long *)(I2C1_BASE_ADDR + 0x08)) @@ -725,7 +725,7 @@ are for LPC24xx only. */ #define I21CONCLR (*(volatile unsigned long *)(I2C1_BASE_ADDR + 0x18)) /* I2C Interface 2 */ -#define I2C2_BASE_ADDR 0xE0080000 +#define I2C2_BASE_ADDR 0xE0080000 #define I22CONSET (*(volatile unsigned long *)(I2C2_BASE_ADDR + 0x00)) #define I22STAT (*(volatile unsigned long *)(I2C2_BASE_ADDR + 0x04)) #define I22DAT (*(volatile unsigned long *)(I2C2_BASE_ADDR + 0x08)) @@ -735,7 +735,7 @@ are for LPC24xx only. */ #define I22CONCLR (*(volatile unsigned long *)(I2C2_BASE_ADDR + 0x18)) /* SPI0 (Serial Peripheral Interface 0) */ -#define SPI0_BASE_ADDR 0xE0020000 +#define SPI0_BASE_ADDR 0xE0020000 #define S0SPCR (*(volatile unsigned long *)(SPI0_BASE_ADDR + 0x00)) #define S0SPSR (*(volatile unsigned long *)(SPI0_BASE_ADDR + 0x04)) #define S0SPDR (*(volatile unsigned long *)(SPI0_BASE_ADDR + 0x08)) @@ -743,7 +743,7 @@ are for LPC24xx only. */ #define S0SPINT (*(volatile unsigned long *)(SPI0_BASE_ADDR + 0x1C)) /* SSP0 Controller */ -#define SSP0_BASE_ADDR 0xE0068000 +#define SSP0_BASE_ADDR 0xE0068000 #define SSP0CR0 (*(volatile unsigned long *)(SSP0_BASE_ADDR + 0x00)) #define SSP0CR1 (*(volatile unsigned long *)(SSP0_BASE_ADDR + 0x04)) #define SSP0DR (*(volatile unsigned long *)(SSP0_BASE_ADDR + 0x08)) @@ -756,7 +756,7 @@ are for LPC24xx only. */ #define SSP0DMACR (*(volatile unsigned long *)(SSP0_BASE_ADDR + 0x24)) /* SSP1 Controller */ -#define SSP1_BASE_ADDR 0xE0030000 +#define SSP1_BASE_ADDR 0xE0030000 #define SSP1CR0 (*(volatile unsigned long *)(SSP1_BASE_ADDR + 0x00)) #define SSP1CR1 (*(volatile unsigned long *)(SSP1_BASE_ADDR + 0x04)) #define SSP1DR (*(volatile unsigned long *)(SSP1_BASE_ADDR + 0x08)) @@ -770,7 +770,7 @@ are for LPC24xx only. */ /* Real Time Clock */ -#define RTC_BASE_ADDR 0xE0024000 +#define RTC_BASE_ADDR 0xE0024000 #define RTC_ILR (*(volatile unsigned long *)(RTC_BASE_ADDR + 0x00)) #define RTC_CTC (*(volatile unsigned long *)(RTC_BASE_ADDR + 0x04)) #define RTC_CCR (*(volatile unsigned long *)(RTC_BASE_ADDR + 0x08)) @@ -801,7 +801,7 @@ are for LPC24xx only. */ /* A/D Converter 0 (AD0) */ -#define AD0_BASE_ADDR 0xE0034000 +#define AD0_BASE_ADDR 0xE0034000 #define AD0CR (*(volatile unsigned long *)(AD0_BASE_ADDR + 0x00)) #define AD0GDR (*(volatile unsigned long *)(AD0_BASE_ADDR + 0x04)) #define AD0INTEN (*(volatile unsigned long *)(AD0_BASE_ADDR + 0x0C)) @@ -817,12 +817,12 @@ are for LPC24xx only. */ /* D/A Converter */ -#define DAC_BASE_ADDR 0xE006C000 +#define DAC_BASE_ADDR 0xE006C000 #define DACR (*(volatile unsigned long *)(DAC_BASE_ADDR + 0x00)) /* Watchdog */ -#define WDG_BASE_ADDR 0xE0000000 +#define WDG_BASE_ADDR 0xE0000000 #define WDMOD (*(volatile unsigned long *)(WDG_BASE_ADDR + 0x00)) #define WDTC (*(volatile unsigned long *)(WDG_BASE_ADDR + 0x04)) #define WDFEED (*(volatile unsigned long *)(WDG_BASE_ADDR + 0x08)) @@ -830,78 +830,78 @@ are for LPC24xx only. */ #define WDCLKSEL (*(volatile unsigned long *)(WDG_BASE_ADDR + 0x10)) /* CAN CONTROLLERS AND ACCEPTANCE FILTER */ -#define CAN_ACCEPT_BASE_ADDR 0xE003C000 -#define CAN_AFMR (*(volatile unsigned long *)(CAN_ACCEPT_BASE_ADDR + 0x00)) -#define CAN_SFF_SA (*(volatile unsigned long *)(CAN_ACCEPT_BASE_ADDR + 0x04)) -#define CAN_SFF_GRP_SA (*(volatile unsigned long *)(CAN_ACCEPT_BASE_ADDR + 0x08)) -#define CAN_EFF_SA (*(volatile unsigned long *)(CAN_ACCEPT_BASE_ADDR + 0x0C)) -#define CAN_EFF_GRP_SA (*(volatile unsigned long *)(CAN_ACCEPT_BASE_ADDR + 0x10)) -#define CAN_EOT (*(volatile unsigned long *)(CAN_ACCEPT_BASE_ADDR + 0x14)) -#define CAN_LUT_ERR_ADR (*(volatile unsigned long *)(CAN_ACCEPT_BASE_ADDR + 0x18)) -#define CAN_LUT_ERR (*(volatile unsigned long *)(CAN_ACCEPT_BASE_ADDR + 0x1C)) +#define CAN_ACCEPT_BASE_ADDR 0xE003C000 +#define CAN_AFMR (*(volatile unsigned long *)(CAN_ACCEPT_BASE_ADDR + 0x00)) +#define CAN_SFF_SA (*(volatile unsigned long *)(CAN_ACCEPT_BASE_ADDR + 0x04)) +#define CAN_SFF_GRP_SA (*(volatile unsigned long *)(CAN_ACCEPT_BASE_ADDR + 0x08)) +#define CAN_EFF_SA (*(volatile unsigned long *)(CAN_ACCEPT_BASE_ADDR + 0x0C)) +#define CAN_EFF_GRP_SA (*(volatile unsigned long *)(CAN_ACCEPT_BASE_ADDR + 0x10)) +#define CAN_EOT (*(volatile unsigned long *)(CAN_ACCEPT_BASE_ADDR + 0x14)) +#define CAN_LUT_ERR_ADR (*(volatile unsigned long *)(CAN_ACCEPT_BASE_ADDR + 0x18)) +#define CAN_LUT_ERR (*(volatile unsigned long *)(CAN_ACCEPT_BASE_ADDR + 0x1C)) + +#define CAN_CENTRAL_BASE_ADDR 0xE0040000 +#define CAN_TX_SR (*(volatile unsigned long *)(CAN_CENTRAL_BASE_ADDR + 0x00)) +#define CAN_RX_SR (*(volatile unsigned long *)(CAN_CENTRAL_BASE_ADDR + 0x04)) +#define CAN_MSR (*(volatile unsigned long *)(CAN_CENTRAL_BASE_ADDR + 0x08)) + +#define CAN1_BASE_ADDR 0xE0044000 +#define CAN1MOD (*(volatile unsigned long *)(CAN1_BASE_ADDR + 0x00)) +#define CAN1CMR (*(volatile unsigned long *)(CAN1_BASE_ADDR + 0x04)) +#define CAN1GSR (*(volatile unsigned long *)(CAN1_BASE_ADDR + 0x08)) +#define CAN1ICR (*(volatile unsigned long *)(CAN1_BASE_ADDR + 0x0C)) +#define CAN1IER (*(volatile unsigned long *)(CAN1_BASE_ADDR + 0x10)) +#define CAN1BTR (*(volatile unsigned long *)(CAN1_BASE_ADDR + 0x14)) +#define CAN1EWL (*(volatile unsigned long *)(CAN1_BASE_ADDR + 0x18)) +#define CAN1SR (*(volatile unsigned long *)(CAN1_BASE_ADDR + 0x1C)) +#define CAN1RFS (*(volatile unsigned long *)(CAN1_BASE_ADDR + 0x20)) +#define CAN1RID (*(volatile unsigned long *)(CAN1_BASE_ADDR + 0x24)) +#define CAN1RDA (*(volatile unsigned long *)(CAN1_BASE_ADDR + 0x28)) +#define CAN1RDB (*(volatile unsigned long *)(CAN1_BASE_ADDR + 0x2C)) -#define CAN_CENTRAL_BASE_ADDR 0xE0040000 -#define CAN_TX_SR (*(volatile unsigned long *)(CAN_CENTRAL_BASE_ADDR + 0x00)) -#define CAN_RX_SR (*(volatile unsigned long *)(CAN_CENTRAL_BASE_ADDR + 0x04)) -#define CAN_MSR (*(volatile unsigned long *)(CAN_CENTRAL_BASE_ADDR + 0x08)) +#define CAN1TFI1 (*(volatile unsigned long *)(CAN1_BASE_ADDR + 0x30)) +#define CAN1TID1 (*(volatile unsigned long *)(CAN1_BASE_ADDR + 0x34)) +#define CAN1TDA1 (*(volatile unsigned long *)(CAN1_BASE_ADDR + 0x38)) +#define CAN1TDB1 (*(volatile unsigned long *)(CAN1_BASE_ADDR + 0x3C)) +#define CAN1TFI2 (*(volatile unsigned long *)(CAN1_BASE_ADDR + 0x40)) +#define CAN1TID2 (*(volatile unsigned long *)(CAN1_BASE_ADDR + 0x44)) +#define CAN1TDA2 (*(volatile unsigned long *)(CAN1_BASE_ADDR + 0x48)) +#define CAN1TDB2 (*(volatile unsigned long *)(CAN1_BASE_ADDR + 0x4C)) +#define CAN1TFI3 (*(volatile unsigned long *)(CAN1_BASE_ADDR + 0x50)) +#define CAN1TID3 (*(volatile unsigned long *)(CAN1_BASE_ADDR + 0x54)) +#define CAN1TDA3 (*(volatile unsigned long *)(CAN1_BASE_ADDR + 0x58)) +#define CAN1TDB3 (*(volatile unsigned long *)(CAN1_BASE_ADDR + 0x5C)) -#define CAN1_BASE_ADDR 0xE0044000 -#define CAN1MOD (*(volatile unsigned long *)(CAN1_BASE_ADDR + 0x00)) -#define CAN1CMR (*(volatile unsigned long *)(CAN1_BASE_ADDR + 0x04)) -#define CAN1GSR (*(volatile unsigned long *)(CAN1_BASE_ADDR + 0x08)) -#define CAN1ICR (*(volatile unsigned long *)(CAN1_BASE_ADDR + 0x0C)) -#define CAN1IER (*(volatile unsigned long *)(CAN1_BASE_ADDR + 0x10)) -#define CAN1BTR (*(volatile unsigned long *)(CAN1_BASE_ADDR + 0x14)) -#define CAN1EWL (*(volatile unsigned long *)(CAN1_BASE_ADDR + 0x18)) -#define CAN1SR (*(volatile unsigned long *)(CAN1_BASE_ADDR + 0x1C)) -#define CAN1RFS (*(volatile unsigned long *)(CAN1_BASE_ADDR + 0x20)) -#define CAN1RID (*(volatile unsigned long *)(CAN1_BASE_ADDR + 0x24)) -#define CAN1RDA (*(volatile unsigned long *)(CAN1_BASE_ADDR + 0x28)) -#define CAN1RDB (*(volatile unsigned long *)(CAN1_BASE_ADDR + 0x2C)) - -#define CAN1TFI1 (*(volatile unsigned long *)(CAN1_BASE_ADDR + 0x30)) -#define CAN1TID1 (*(volatile unsigned long *)(CAN1_BASE_ADDR + 0x34)) -#define CAN1TDA1 (*(volatile unsigned long *)(CAN1_BASE_ADDR + 0x38)) -#define CAN1TDB1 (*(volatile unsigned long *)(CAN1_BASE_ADDR + 0x3C)) -#define CAN1TFI2 (*(volatile unsigned long *)(CAN1_BASE_ADDR + 0x40)) -#define CAN1TID2 (*(volatile unsigned long *)(CAN1_BASE_ADDR + 0x44)) -#define CAN1TDA2 (*(volatile unsigned long *)(CAN1_BASE_ADDR + 0x48)) -#define CAN1TDB2 (*(volatile unsigned long *)(CAN1_BASE_ADDR + 0x4C)) -#define CAN1TFI3 (*(volatile unsigned long *)(CAN1_BASE_ADDR + 0x50)) -#define CAN1TID3 (*(volatile unsigned long *)(CAN1_BASE_ADDR + 0x54)) -#define CAN1TDA3 (*(volatile unsigned long *)(CAN1_BASE_ADDR + 0x58)) -#define CAN1TDB3 (*(volatile unsigned long *)(CAN1_BASE_ADDR + 0x5C)) +#define CAN2_BASE_ADDR 0xE0048000 +#define CAN2MOD (*(volatile unsigned long *)(CAN2_BASE_ADDR + 0x00)) +#define CAN2CMR (*(volatile unsigned long *)(CAN2_BASE_ADDR + 0x04)) +#define CAN2GSR (*(volatile unsigned long *)(CAN2_BASE_ADDR + 0x08)) +#define CAN2ICR (*(volatile unsigned long *)(CAN2_BASE_ADDR + 0x0C)) +#define CAN2IER (*(volatile unsigned long *)(CAN2_BASE_ADDR + 0x10)) +#define CAN2BTR (*(volatile unsigned long *)(CAN2_BASE_ADDR + 0x14)) +#define CAN2EWL (*(volatile unsigned long *)(CAN2_BASE_ADDR + 0x18)) +#define CAN2SR (*(volatile unsigned long *)(CAN2_BASE_ADDR + 0x1C)) +#define CAN2RFS (*(volatile unsigned long *)(CAN2_BASE_ADDR + 0x20)) +#define CAN2RID (*(volatile unsigned long *)(CAN2_BASE_ADDR + 0x24)) +#define CAN2RDA (*(volatile unsigned long *)(CAN2_BASE_ADDR + 0x28)) +#define CAN2RDB (*(volatile unsigned long *)(CAN2_BASE_ADDR + 0x2C)) -#define CAN2_BASE_ADDR 0xE0048000 -#define CAN2MOD (*(volatile unsigned long *)(CAN2_BASE_ADDR + 0x00)) -#define CAN2CMR (*(volatile unsigned long *)(CAN2_BASE_ADDR + 0x04)) -#define CAN2GSR (*(volatile unsigned long *)(CAN2_BASE_ADDR + 0x08)) -#define CAN2ICR (*(volatile unsigned long *)(CAN2_BASE_ADDR + 0x0C)) -#define CAN2IER (*(volatile unsigned long *)(CAN2_BASE_ADDR + 0x10)) -#define CAN2BTR (*(volatile unsigned long *)(CAN2_BASE_ADDR + 0x14)) -#define CAN2EWL (*(volatile unsigned long *)(CAN2_BASE_ADDR + 0x18)) -#define CAN2SR (*(volatile unsigned long *)(CAN2_BASE_ADDR + 0x1C)) -#define CAN2RFS (*(volatile unsigned long *)(CAN2_BASE_ADDR + 0x20)) -#define CAN2RID (*(volatile unsigned long *)(CAN2_BASE_ADDR + 0x24)) -#define CAN2RDA (*(volatile unsigned long *)(CAN2_BASE_ADDR + 0x28)) -#define CAN2RDB (*(volatile unsigned long *)(CAN2_BASE_ADDR + 0x2C)) - -#define CAN2TFI1 (*(volatile unsigned long *)(CAN2_BASE_ADDR + 0x30)) -#define CAN2TID1 (*(volatile unsigned long *)(CAN2_BASE_ADDR + 0x34)) -#define CAN2TDA1 (*(volatile unsigned long *)(CAN2_BASE_ADDR + 0x38)) -#define CAN2TDB1 (*(volatile unsigned long *)(CAN2_BASE_ADDR + 0x3C)) -#define CAN2TFI2 (*(volatile unsigned long *)(CAN2_BASE_ADDR + 0x40)) -#define CAN2TID2 (*(volatile unsigned long *)(CAN2_BASE_ADDR + 0x44)) -#define CAN2TDA2 (*(volatile unsigned long *)(CAN2_BASE_ADDR + 0x48)) -#define CAN2TDB2 (*(volatile unsigned long *)(CAN2_BASE_ADDR + 0x4C)) -#define CAN2TFI3 (*(volatile unsigned long *)(CAN2_BASE_ADDR + 0x50)) -#define CAN2TID3 (*(volatile unsigned long *)(CAN2_BASE_ADDR + 0x54)) -#define CAN2TDA3 (*(volatile unsigned long *)(CAN2_BASE_ADDR + 0x58)) -#define CAN2TDB3 (*(volatile unsigned long *)(CAN2_BASE_ADDR + 0x5C)) +#define CAN2TFI1 (*(volatile unsigned long *)(CAN2_BASE_ADDR + 0x30)) +#define CAN2TID1 (*(volatile unsigned long *)(CAN2_BASE_ADDR + 0x34)) +#define CAN2TDA1 (*(volatile unsigned long *)(CAN2_BASE_ADDR + 0x38)) +#define CAN2TDB1 (*(volatile unsigned long *)(CAN2_BASE_ADDR + 0x3C)) +#define CAN2TFI2 (*(volatile unsigned long *)(CAN2_BASE_ADDR + 0x40)) +#define CAN2TID2 (*(volatile unsigned long *)(CAN2_BASE_ADDR + 0x44)) +#define CAN2TDA2 (*(volatile unsigned long *)(CAN2_BASE_ADDR + 0x48)) +#define CAN2TDB2 (*(volatile unsigned long *)(CAN2_BASE_ADDR + 0x4C)) +#define CAN2TFI3 (*(volatile unsigned long *)(CAN2_BASE_ADDR + 0x50)) +#define CAN2TID3 (*(volatile unsigned long *)(CAN2_BASE_ADDR + 0x54)) +#define CAN2TDA3 (*(volatile unsigned long *)(CAN2_BASE_ADDR + 0x58)) +#define CAN2TDB3 (*(volatile unsigned long *)(CAN2_BASE_ADDR + 0x5C)) /* MultiMedia Card Interface(MCI) Controller */ -#define MCI_BASE_ADDR 0xE008C000 +#define MCI_BASE_ADDR 0xE008C000 #define MCI_POWER (*(volatile unsigned long *)(MCI_BASE_ADDR + 0x00)) #define MCI_CLOCK (*(volatile unsigned long *)(MCI_BASE_ADDR + 0x04)) #define MCI_ARGUMENT (*(volatile unsigned long *)(MCI_BASE_ADDR + 0x08)) @@ -924,7 +924,7 @@ are for LPC24xx only. */ /* I2S Interface Controller (I2S) */ -#define I2S_BASE_ADDR 0xE0088000 +#define I2S_BASE_ADDR 0xE0088000 #define I2S_DAO (*(volatile unsigned long *)(I2S_BASE_ADDR + 0x00)) #define I2S_DAI (*(volatile unsigned long *)(I2S_BASE_ADDR + 0x04)) #define I2S_TX_FIFO (*(volatile unsigned long *)(I2S_BASE_ADDR + 0x08)) @@ -938,7 +938,7 @@ are for LPC24xx only. */ /* General-purpose DMA Controller */ -#define DMA_BASE_ADDR 0xFFE04000 +#define DMA_BASE_ADDR 0xFFE04000 #define GPDMA_INT_STAT (*(volatile unsigned long *)(DMA_BASE_ADDR + 0x000)) #define GPDMA_INT_TCSTAT (*(volatile unsigned long *)(DMA_BASE_ADDR + 0x004)) #define GPDMA_INT_TCCLR (*(volatile unsigned long *)(DMA_BASE_ADDR + 0x008)) @@ -970,8 +970,8 @@ are for LPC24xx only. */ /* USB Controller */ -#define USB_INT_BASE_ADDR 0xE01FC1C0 -#define USB_BASE_ADDR 0xFFE0C200 /* USB Base Address */ +#define USB_INT_BASE_ADDR 0xE01FC1C0 +#define USB_BASE_ADDR 0xFFE0C200 /* USB Base Address */ #define USB_INT_STAT (*(volatile unsigned long *)(USB_INT_BASE_ADDR + 0x00)) @@ -1027,7 +1027,7 @@ are for LPC24xx only. */ /* USB Host and OTG registers are for LPC24xx only */ /* USB Host Controller */ -#define USBHC_BASE_ADDR 0xFFE0C000 +#define USBHC_BASE_ADDR 0xFFE0C000 #define HC_REVISION (*(volatile unsigned long *)(USBHC_BASE_ADDR + 0x00)) #define HC_CONTROL (*(volatile unsigned long *)(USBHC_BASE_ADDR + 0x04)) #define HC_CMD_STAT (*(volatile unsigned long *)(USBHC_BASE_ADDR + 0x08)) @@ -1053,16 +1053,16 @@ are for LPC24xx only. */ #define HC_RH_PORT_STAT2 (*(volatile unsigned long *)(USBHC_BASE_ADDR + 0x58)) /* USB OTG Controller */ -#define USBOTG_BASE_ADDR 0xFFE0C100 +#define USBOTG_BASE_ADDR 0xFFE0C100 #define OTG_INT_STAT (*(volatile unsigned long *)(USBOTG_BASE_ADDR + 0x00)) #define OTG_INT_EN (*(volatile unsigned long *)(USBOTG_BASE_ADDR + 0x04)) #define OTG_INT_SET (*(volatile unsigned long *)(USBOTG_BASE_ADDR + 0x08)) #define OTG_INT_CLR (*(volatile unsigned long *)(USBOTG_BASE_ADDR + 0x0C)) -/* On LPC23xx, the name is USBPortSel, on LPC24xx, the name is OTG_STAT_CTRL */ +/* On LPC23xx, the name is USBPortSel, on LPC24xx, the name is OTG_STAT_CTRL */ #define OTG_STAT_CTRL (*(volatile unsigned long *)(USBOTG_BASE_ADDR + 0x10)) #define OTG_TIMER (*(volatile unsigned long *)(USBOTG_BASE_ADDR + 0x14)) -#define USBOTG_I2C_BASE_ADDR 0xFFE0C300 +#define USBOTG_I2C_BASE_ADDR 0xFFE0C300 #define OTG_I2C_RX (*(volatile unsigned long *)(USBOTG_I2C_BASE_ADDR + 0x00)) #define OTG_I2C_TX (*(volatile unsigned long *)(USBOTG_I2C_BASE_ADDR + 0x00)) #define OTG_I2C_STS (*(volatile unsigned long *)(USBOTG_I2C_BASE_ADDR + 0x04)) @@ -1070,20 +1070,20 @@ are for LPC24xx only. */ #define OTG_I2C_CLKHI (*(volatile unsigned long *)(USBOTG_I2C_BASE_ADDR + 0x0C)) #define OTG_I2C_CLKLO (*(volatile unsigned long *)(USBOTG_I2C_BASE_ADDR + 0x10)) -/* On LPC23xx, the names are USBClkCtrl and USBClkSt; on LPC24xx, the names are +/* On LPC23xx, the names are USBClkCtrl and USBClkSt; on LPC24xx, the names are OTG_CLK_CTRL and OTG_CLK_STAT respectively. */ -#define USBOTG_CLK_BASE_ADDR 0xFFE0CFF0 +#define USBOTG_CLK_BASE_ADDR 0xFFE0CFF0 #define OTG_CLK_CTRL (*(volatile unsigned long *)(USBOTG_CLK_BASE_ADDR + 0x04)) #define OTG_CLK_STAT (*(volatile unsigned long *)(USBOTG_CLK_BASE_ADDR + 0x08)) /* Note: below three register name convention is for LPC23xx USB device only, match -with the spec. update in USB Device Section. */ +with the spec. update in USB Device Section. */ #define USBPortSel (*(volatile unsigned long *)(USBOTG_BASE_ADDR + 0x10)) #define USBClkCtrl (*(volatile unsigned long *)(USBOTG_CLK_BASE_ADDR + 0x04)) #define USBClkSt (*(volatile unsigned long *)(USBOTG_CLK_BASE_ADDR + 0x08)) /* Ethernet MAC (32 bit data bus) -- all registers are RW unless indicated in parentheses */ -#define MAC_BASE_ADDR 0xFFE00000 /* AHB Peripheral # 0 */ +#define MAC_BASE_ADDR 0xFFE00000 /* AHB Peripheral # 0 */ #define MAC_MAC1 (*(volatile unsigned long *)(MAC_BASE_ADDR + 0x000)) /* MAC config reg 1 */ #define MAC_MAC2 (*(volatile unsigned long *)(MAC_BASE_ADDR + 0x004)) /* MAC config reg 2 */ #define MAC_IPGT (*(volatile unsigned long *)(MAC_BASE_ADDR + 0x008)) /* b2b InterPacketGap reg */ @@ -1139,7 +1139,7 @@ with the spec. update in USB Device Section. */ #define MAC_MODULEID (*(volatile unsigned long *)(MAC_BASE_ADDR + 0xFFC)) /* Module ID reg (RO) */ /* LCD Controller registers */ -#define LCD_BASE_ADDR 0xFFE10000 /* AHB Peripheral # 4 */ +#define LCD_BASE_ADDR 0xFFE10000 /* AHB Peripheral # 4 */ #define LCD_CFG (*(volatile unsigned long *)(0xE01FC1B8)) #define LCD_TIMH (*(volatile unsigned long *)(LCD_BASE_ADDR + 0x000)) #define LCD_TIMV (*(volatile unsigned long *)(LCD_BASE_ADDR + 0x004)) @@ -1169,24 +1169,24 @@ with the spec. update in USB Device Section. */ struct rt_hw_register { - unsigned long r0; - unsigned long r1; - unsigned long r2; - unsigned long r3; - unsigned long r4; - unsigned long r5; - unsigned long r6; - unsigned long r7; - unsigned long r8; - unsigned long r9; - unsigned long r10; - unsigned long fp; - unsigned long ip; - unsigned long sp; - unsigned long lr; - unsigned long pc; - unsigned long cpsr; - unsigned long ORIG_r0; + unsigned long r0; + unsigned long r1; + unsigned long r2; + unsigned long r3; + unsigned long r4; + unsigned long r5; + unsigned long r6; + unsigned long r7; + unsigned long r8; + unsigned long r9; + unsigned long r10; + unsigned long fp; + unsigned long ip; + unsigned long sp; + unsigned long lr; + unsigned long pc; + unsigned long cpsr; + unsigned long ORIG_r0; }; #ifdef __cplusplus diff --git a/libcpu/arm/lpc24xx/cpu.c b/libcpu/arm/lpc24xx/cpu.c index 0453722d1d..d9c74020bb 100644 --- a/libcpu/arm/lpc24xx/cpu.c +++ b/libcpu/arm/lpc24xx/cpu.c @@ -1,5 +1,5 @@ /* - * Copyright (c) 2006-2018, RT-Thread Development Team + * Copyright (c) 2006-2021, RT-Thread Development Team * * SPDX-License-Identifier: Apache-2.0 * @@ -30,9 +30,9 @@ RT_WEAK void rt_hw_cpu_reset() */ RT_WEAK void rt_hw_cpu_shutdown() { - rt_kprintf("shutdown...\n"); + rt_kprintf("shutdown...\n"); - while (1); + while (1); } /*@}*/ diff --git a/libcpu/arm/lpc24xx/interrupt.c b/libcpu/arm/lpc24xx/interrupt.c index a855de1e11..87bb86b879 100644 --- a/libcpu/arm/lpc24xx/interrupt.c +++ b/libcpu/arm/lpc24xx/interrupt.c @@ -1,5 +1,5 @@ /* - * Copyright (c) 2006-2018, RT-Thread Development Team + * Copyright (c) 2006-2021, RT-Thread Development Team * * SPDX-License-Identifier: Apache-2.0 * @@ -13,10 +13,10 @@ #include <rthw.h> #include "LPC24xx.h" -#define MAX_HANDLERS 32 +#define MAX_HANDLERS 32 /* exception and interrupt handler table */ -struct rt_irq_desc irq_desc[MAX_HANDLERS]; +struct rt_irq_desc irq_desc[MAX_HANDLERS]; extern rt_uint32_t rt_interrupt_nest; @@ -30,19 +30,19 @@ rt_uint32_t rt_thread_switch_interrupt_flag; /*@{*/ void rt_hw_interrupt_handler(int vector, void *param) { - rt_kprintf("Unhandled interrupt %d occured!!!\n", vector); + rt_kprintf("Unhandled interrupt %d occured!!!\n", vector); } void rt_hw_interrupt_init(void) { - register int i; + register int i; - rt_uint32_t *vect_addr, *vect_cntl; - - /* initialize VIC*/ - VICIntEnClr = 0xffffffff; - VICVectAddr = 0; - VICIntSelect = 0; + rt_uint32_t *vect_addr, *vect_cntl; + + /* initialize VIC*/ + VICIntEnClr = 0xffffffff; + VICVectAddr = 0; + VICIntSelect = 0; /* init exceptions table */ rt_memset(irq_desc, 0x00, sizeof(irq_desc)); @@ -50,27 +50,27 @@ void rt_hw_interrupt_init(void) { irq_desc[i].handler = rt_hw_interrupt_handler; - vect_addr = (rt_uint32_t *)(VIC_BASE_ADDR + 0x100 + i*4); - vect_cntl = (rt_uint32_t *)(VIC_BASE_ADDR + 0x200 + i*4); - *vect_addr = (rt_uint32_t)&irq_desc[i]; - *vect_cntl = 0xF; + vect_addr = (rt_uint32_t *)(VIC_BASE_ADDR + 0x100 + i*4); + vect_cntl = (rt_uint32_t *)(VIC_BASE_ADDR + 0x200 + i*4); + *vect_addr = (rt_uint32_t)&irq_desc[i]; + *vect_cntl = 0xF; } - - /* init interrupt nest, and context in thread sp */ - rt_interrupt_nest = 0; - rt_interrupt_from_thread = 0; - rt_interrupt_to_thread = 0; - rt_thread_switch_interrupt_flag = 0; + + /* init interrupt nest, and context in thread sp */ + rt_interrupt_nest = 0; + rt_interrupt_from_thread = 0; + rt_interrupt_to_thread = 0; + rt_thread_switch_interrupt_flag = 0; } void rt_hw_interrupt_mask(int vector) { - VICIntEnClr = (1 << vector); + VICIntEnClr = (1 << vector); } void rt_hw_interrupt_umask(int vector) { - VICIntEnable = (1 << vector); + VICIntEnable = (1 << vector); } /** @@ -82,22 +82,22 @@ void rt_hw_interrupt_umask(int vector) * * @return the old handler */ -rt_isr_handler_t rt_hw_interrupt_install(int vector, rt_isr_handler_t handler, - void *param, const char *name) +rt_isr_handler_t rt_hw_interrupt_install(int vector, rt_isr_handler_t handler, + void *param, const char *name) { - rt_isr_handler_t old_handler = RT_NULL; + rt_isr_handler_t old_handler = RT_NULL; - if(vector >= 0 && vector < MAX_HANDLERS) - { - old_handler = irq_desc[vector].handler; - if (handler != RT_NULL) - { - irq_desc[vector].handler = handler; - irq_desc[vector].param = param; - } - } + if(vector >= 0 && vector < MAX_HANDLERS) + { + old_handler = irq_desc[vector].handler; + if (handler != RT_NULL) + { + irq_desc[vector].handler = handler; + irq_desc[vector].param = param; + } + } - return old_handler; + return old_handler; } /*@}*/ diff --git a/libcpu/arm/lpc24xx/stack.c b/libcpu/arm/lpc24xx/stack.c index 0378a5f658..a7bce755b3 100644 --- a/libcpu/arm/lpc24xx/stack.c +++ b/libcpu/arm/lpc24xx/stack.c @@ -1,5 +1,5 @@ /* - * Copyright (c) 2006-2018, RT-Thread Development Team + * Copyright (c) 2006-2021, RT-Thread Development Team * * SPDX-License-Identifier: Apache-2.0 * diff --git a/libcpu/arm/lpc24xx/trap.c b/libcpu/arm/lpc24xx/trap.c index d296bfdbfe..7ad7328a93 100644 --- a/libcpu/arm/lpc24xx/trap.c +++ b/libcpu/arm/lpc24xx/trap.c @@ -1,5 +1,5 @@ /* - * Copyright (c) 2006-2018, RT-Thread Development Team + * Copyright (c) 2006-2021, RT-Thread Development Team * * SPDX-License-Identifier: Apache-2.0 * @@ -27,13 +27,13 @@ */ void rt_hw_show_register (struct rt_hw_register *regs) { - rt_kprintf("Execption:\n"); - rt_kprintf("r00:0x%08x r01:0x%08x r02:0x%08x r03:0x%08x\n", regs->r0, regs->r1, regs->r2, regs->r3); - rt_kprintf("r04:0x%08x r05:0x%08x r06:0x%08x r07:0x%08x\n", regs->r4, regs->r5, regs->r6, regs->r7); - rt_kprintf("r08:0x%08x r09:0x%08x r10:0x%08x\n", regs->r8, regs->r9, regs->r10); - rt_kprintf("fp :0x%08x ip :0x%08x\n", regs->fp, regs->ip); - rt_kprintf("sp :0x%08x lr :0x%08x pc :0x%08x\n", regs->sp, regs->lr, regs->pc); - rt_kprintf("cpsr:0x%08x\n", regs->cpsr); + rt_kprintf("Execption:\n"); + rt_kprintf("r00:0x%08x r01:0x%08x r02:0x%08x r03:0x%08x\n", regs->r0, regs->r1, regs->r2, regs->r3); + rt_kprintf("r04:0x%08x r05:0x%08x r06:0x%08x r07:0x%08x\n", regs->r4, regs->r5, regs->r6, regs->r7); + rt_kprintf("r08:0x%08x r09:0x%08x r10:0x%08x\n", regs->r8, regs->r9, regs->r10); + rt_kprintf("fp :0x%08x ip :0x%08x\n", regs->fp, regs->ip); + rt_kprintf("sp :0x%08x lr :0x%08x pc :0x%08x\n", regs->sp, regs->lr, regs->pc); + rt_kprintf("cpsr:0x%08x\n", regs->cpsr); } /** @@ -48,8 +48,8 @@ void rt_hw_trap_udef(struct rt_hw_register *regs) { rt_kprintf("undefined instruction\n"); rt_hw_show_register(regs); - if (rt_thread_self() != RT_NULL) - rt_kprintf("Current Thread: %s\n", rt_thread_self()->name); + if (rt_thread_self() != RT_NULL) + rt_kprintf("Current Thread: %s\n", rt_thread_self()->name); rt_hw_cpu_shutdown(); } @@ -66,8 +66,8 @@ void rt_hw_trap_swi(struct rt_hw_register *regs) { rt_kprintf("software interrupt\n"); rt_hw_show_register(regs); - if (rt_thread_self() != RT_NULL) - rt_kprintf("Current Thread: %s\n", rt_thread_self()->name); + if (rt_thread_self() != RT_NULL) + rt_kprintf("Current Thread: %s\n", rt_thread_self()->name); rt_hw_cpu_shutdown(); } @@ -83,8 +83,8 @@ void rt_hw_trap_pabt(struct rt_hw_register *regs) { rt_kprintf("prefetch abort\n"); rt_hw_show_register(regs); - if (rt_thread_self() != RT_NULL) - rt_kprintf("Current Thread: %s\n", rt_thread_self()->name); + if (rt_thread_self() != RT_NULL) + rt_kprintf("Current Thread: %s\n", rt_thread_self()->name); rt_hw_cpu_shutdown(); } @@ -97,11 +97,11 @@ void rt_hw_trap_pabt(struct rt_hw_register *regs) * @note never invoke this function in application */ void rt_hw_trap_dabt(struct rt_hw_register *regs) -{ +{ rt_kprintf("Data Abort "); rt_hw_show_register(regs); - if (rt_thread_self() != RT_NULL) - rt_kprintf("Current Thread: %s\n", rt_thread_self()->name); + if (rt_thread_self() != RT_NULL) + rt_kprintf("Current Thread: %s\n", rt_thread_self()->name); rt_hw_cpu_shutdown(); } @@ -116,27 +116,27 @@ void rt_hw_trap_resv(struct rt_hw_register *regs) { rt_kprintf("not used\n"); rt_hw_show_register(regs); - if (rt_thread_self() != RT_NULL) - rt_kprintf("Current Thread: %s\n", rt_thread_self()->name); + if (rt_thread_self() != RT_NULL) + rt_kprintf("Current Thread: %s\n", rt_thread_self()->name); rt_hw_cpu_shutdown(); } extern rt_isr_handler_t isr_table[]; void rt_hw_trap_irq(void) { - int irqno; - struct rt_irq_desc* irq; - extern struct rt_irq_desc irq_desc[]; + int irqno; + struct rt_irq_desc* irq; + extern struct rt_irq_desc irq_desc[]; - irq = (struct rt_irq_desc*) VICVectAddr; - irqno = ((rt_uint32_t) irq - (rt_uint32_t) &irq_desc[0])/sizeof(struct rt_irq_desc); + irq = (struct rt_irq_desc*) VICVectAddr; + irqno = ((rt_uint32_t) irq - (rt_uint32_t) &irq_desc[0])/sizeof(struct rt_irq_desc); - /* invoke isr */ - irq->handler(irqno, irq->param); + /* invoke isr */ + irq->handler(irqno, irq->param); } void rt_hw_trap_fiq(void) -{ +{ rt_kprintf("fast interrupt request\n"); } diff --git a/libcpu/arm/realview-a8-vmm/armv7.h b/libcpu/arm/realview-a8-vmm/armv7.h index d22f72fa68..f284bb5255 100644 --- a/libcpu/arm/realview-a8-vmm/armv7.h +++ b/libcpu/arm/realview-a8-vmm/armv7.h @@ -1,5 +1,5 @@ /* - * Copyright (c) 2006-2018, RT-Thread Development Team + * Copyright (c) 2006-2021, RT-Thread Development Team * * SPDX-License-Identifier: Apache-2.0 * @@ -12,43 +12,43 @@ /* the exception stack without VFP registers */ struct rt_hw_exp_stack { - unsigned long r0; - unsigned long r1; - unsigned long r2; - unsigned long r3; - unsigned long r4; - unsigned long r5; - unsigned long r6; - unsigned long r7; - unsigned long r8; - unsigned long r9; - unsigned long r10; - unsigned long fp; - unsigned long ip; - unsigned long sp; - unsigned long lr; - unsigned long pc; - unsigned long cpsr; + unsigned long r0; + unsigned long r1; + unsigned long r2; + unsigned long r3; + unsigned long r4; + unsigned long r5; + unsigned long r6; + unsigned long r7; + unsigned long r8; + unsigned long r9; + unsigned long r10; + unsigned long fp; + unsigned long ip; + unsigned long sp; + unsigned long lr; + unsigned long pc; + unsigned long cpsr; }; struct rt_hw_stack { - unsigned long cpsr; - unsigned long r0; - unsigned long r1; - unsigned long r2; - unsigned long r3; - unsigned long r4; - unsigned long r5; - unsigned long r6; - unsigned long r7; - unsigned long r8; - unsigned long r9; - unsigned long r10; - unsigned long fp; - unsigned long ip; - unsigned long lr; - unsigned long pc; + unsigned long cpsr; + unsigned long r0; + unsigned long r1; + unsigned long r2; + unsigned long r3; + unsigned long r4; + unsigned long r5; + unsigned long r6; + unsigned long r7; + unsigned long r8; + unsigned long r9; + unsigned long r10; + unsigned long fp; + unsigned long ip; + unsigned long lr; + unsigned long pc; }; #define USERMODE 0x10 diff --git a/libcpu/arm/realview-a8-vmm/cp15.h b/libcpu/arm/realview-a8-vmm/cp15.h index 486f38200d..b18331af92 100644 --- a/libcpu/arm/realview-a8-vmm/cp15.h +++ b/libcpu/arm/realview-a8-vmm/cp15.h @@ -1,5 +1,5 @@ /* - * Copyright (c) 2006-2018, RT-Thread Development Team + * Copyright (c) 2006-2021, RT-Thread Development Team * * SPDX-License-Identifier: Apache-2.0 * diff --git a/libcpu/arm/realview-a8-vmm/cpu.c b/libcpu/arm/realview-a8-vmm/cpu.c index dbdb4ac515..8c5a6d16dd 100644 --- a/libcpu/arm/realview-a8-vmm/cpu.c +++ b/libcpu/arm/realview-a8-vmm/cpu.c @@ -1,5 +1,5 @@ /* - * Copyright (c) 2006-2018, RT-Thread Development Team + * Copyright (c) 2006-2021, RT-Thread Development Team * * SPDX-License-Identifier: Apache-2.0 * @@ -20,14 +20,14 @@ /** shutdown CPU */ RT_WEAK void rt_hw_cpu_shutdown() { - rt_uint32_t level; - rt_kprintf("shutdown...\n"); + rt_uint32_t level; + rt_kprintf("shutdown...\n"); - level = rt_hw_interrupt_disable(); - while (level) - { - RT_ASSERT(0); - } + level = rt_hw_interrupt_disable(); + while (level) + { + RT_ASSERT(0); + } } /*@}*/ diff --git a/libcpu/arm/realview-a8-vmm/gic.c b/libcpu/arm/realview-a8-vmm/gic.c index 82f87b7e8f..962317821a 100644 --- a/libcpu/arm/realview-a8-vmm/gic.c +++ b/libcpu/arm/realview-a8-vmm/gic.c @@ -1,5 +1,5 @@ /* - * Copyright (c) 2006-2018, RT-Thread Development Team + * Copyright (c) 2006-2021, RT-Thread Development Team * * SPDX-License-Identifier: Apache-2.0 * diff --git a/libcpu/arm/realview-a8-vmm/gic.h b/libcpu/arm/realview-a8-vmm/gic.h index 8fcdf05f6f..7c781ad4d9 100644 --- a/libcpu/arm/realview-a8-vmm/gic.h +++ b/libcpu/arm/realview-a8-vmm/gic.h @@ -1,5 +1,5 @@ /* - * Copyright (c) 2006-2018, RT-Thread Development Team + * Copyright (c) 2006-2021, RT-Thread Development Team * * SPDX-License-Identifier: Apache-2.0 * diff --git a/libcpu/arm/realview-a8-vmm/interrupt.c b/libcpu/arm/realview-a8-vmm/interrupt.c index 5fffb4ba36..23ff062a8b 100644 --- a/libcpu/arm/realview-a8-vmm/interrupt.c +++ b/libcpu/arm/realview-a8-vmm/interrupt.c @@ -1,5 +1,5 @@ /* - * Copyright (c) 2006-2018, RT-Thread Development Team + * Copyright (c) 2006-2021, RT-Thread Development Team * * SPDX-License-Identifier: Apache-2.0 * diff --git a/libcpu/arm/realview-a8-vmm/interrupt.h b/libcpu/arm/realview-a8-vmm/interrupt.h index 7461f94da0..90f392f407 100644 --- a/libcpu/arm/realview-a8-vmm/interrupt.h +++ b/libcpu/arm/realview-a8-vmm/interrupt.h @@ -1,5 +1,5 @@ /* - * Copyright (c) 2006-2018, RT-Thread Development Team + * Copyright (c) 2006-2021, RT-Thread Development Team * * SPDX-License-Identifier: Apache-2.0 * @@ -14,28 +14,28 @@ #define INT_IRQ 0x00 #define INT_FIQ 0x01 -#define INTC_REVISION(hw_base) REG32((hw_base) + 0x0) -#define INTC_SYSCONFIG(hw_base) REG32((hw_base) + 0x10) -#define INTC_SYSSTATUS(hw_base) REG32((hw_base) + 0x14) -#define INTC_SIR_IRQ(hw_base) REG32((hw_base) + 0x40) -#define INTC_SIR_FIQ(hw_base) REG32((hw_base) + 0x44) -#define INTC_CONTROL(hw_base) REG32((hw_base) + 0x48) -#define INTC_PROTECTION(hw_base) REG32((hw_base) + 0x4c) -#define INTC_IDLE(hw_base) REG32((hw_base) + 0x50) -#define INTC_IRQ_PRIORITY(hw_base) REG32((hw_base) + 0x60) -#define INTC_FIQ_PRIORITY(hw_base) REG32((hw_base) + 0x64) -#define INTC_THRESHOLD(hw_base) REG32((hw_base) + 0x68) -#define INTC_SICR(hw_base) REG32((hw_base) + 0x6c) -#define INTC_SCR(hw_base, n) REG32((hw_base) + 0x70 + ((n) * 0x04)) -#define INTC_ITR(hw_base, n) REG32((hw_base) + 0x80 + ((n) * 0x20)) -#define INTC_MIR(hw_base, n) REG32((hw_base) + 0x84 + ((n) * 0x20)) -#define INTC_MIR_CLEAR(hw_base, n) REG32((hw_base) + 0x88 + ((n) * 0x20)) -#define INTC_MIR_SET(hw_base, n) REG32((hw_base) + 0x8c + ((n) * 0x20)) -#define INTC_ISR_SET(hw_base, n) REG32((hw_base) + 0x90 + ((n) * 0x20)) -#define INTC_ISR_CLEAR(hw_base, n) REG32((hw_base) + 0x94 + ((n) * 0x20)) +#define INTC_REVISION(hw_base) REG32((hw_base) + 0x0) +#define INTC_SYSCONFIG(hw_base) REG32((hw_base) + 0x10) +#define INTC_SYSSTATUS(hw_base) REG32((hw_base) + 0x14) +#define INTC_SIR_IRQ(hw_base) REG32((hw_base) + 0x40) +#define INTC_SIR_FIQ(hw_base) REG32((hw_base) + 0x44) +#define INTC_CONTROL(hw_base) REG32((hw_base) + 0x48) +#define INTC_PROTECTION(hw_base) REG32((hw_base) + 0x4c) +#define INTC_IDLE(hw_base) REG32((hw_base) + 0x50) +#define INTC_IRQ_PRIORITY(hw_base) REG32((hw_base) + 0x60) +#define INTC_FIQ_PRIORITY(hw_base) REG32((hw_base) + 0x64) +#define INTC_THRESHOLD(hw_base) REG32((hw_base) + 0x68) +#define INTC_SICR(hw_base) REG32((hw_base) + 0x6c) +#define INTC_SCR(hw_base, n) REG32((hw_base) + 0x70 + ((n) * 0x04)) +#define INTC_ITR(hw_base, n) REG32((hw_base) + 0x80 + ((n) * 0x20)) +#define INTC_MIR(hw_base, n) REG32((hw_base) + 0x84 + ((n) * 0x20)) +#define INTC_MIR_CLEAR(hw_base, n) REG32((hw_base) + 0x88 + ((n) * 0x20)) +#define INTC_MIR_SET(hw_base, n) REG32((hw_base) + 0x8c + ((n) * 0x20)) +#define INTC_ISR_SET(hw_base, n) REG32((hw_base) + 0x90 + ((n) * 0x20)) +#define INTC_ISR_CLEAR(hw_base, n) REG32((hw_base) + 0x94 + ((n) * 0x20)) #define INTC_PENDING_IRQ(hw_base, n) REG32((hw_base) + 0x98 + ((n) * 0x20)) #define INTC_PENDING_FIQ(hw_base, n) REG32((hw_base) + 0x9c + ((n) * 0x20)) -#define INTC_ILR(hw_base, n) REG32((hw_base) + 0x100 + ((n) * 0x04)) +#define INTC_ILR(hw_base, n) REG32((hw_base) + 0x100 + ((n) * 0x04)) void rt_hw_interrupt_control(int vector, int priority, int route); int rt_hw_interrupt_get_active(int fiq_irq); diff --git a/libcpu/arm/realview-a8-vmm/mmu.c b/libcpu/arm/realview-a8-vmm/mmu.c index 58acdd8145..f4d6068099 100644 --- a/libcpu/arm/realview-a8-vmm/mmu.c +++ b/libcpu/arm/realview-a8-vmm/mmu.c @@ -1,5 +1,5 @@ /* - * Copyright (c) 2006-2018, RT-Thread Development Team + * Copyright (c) 2006-2021, RT-Thread Development Team * * SPDX-License-Identifier: Apache-2.0 * diff --git a/libcpu/arm/realview-a8-vmm/pmu.c b/libcpu/arm/realview-a8-vmm/pmu.c index 8ffc1dede6..2b9165cc8b 100644 --- a/libcpu/arm/realview-a8-vmm/pmu.c +++ b/libcpu/arm/realview-a8-vmm/pmu.c @@ -1,5 +1,5 @@ /* - * Copyright (c) 2006-2018, RT-Thread Development Team + * Copyright (c) 2006-2021, RT-Thread Development Team * * SPDX-License-Identifier: Apache-2.0 * diff --git a/libcpu/arm/realview-a8-vmm/pmu.h b/libcpu/arm/realview-a8-vmm/pmu.h index fb8390133d..64a74b5d39 100644 --- a/libcpu/arm/realview-a8-vmm/pmu.h +++ b/libcpu/arm/realview-a8-vmm/pmu.h @@ -1,5 +1,5 @@ /* - * Copyright (c) 2006-2018, RT-Thread Development Team + * Copyright (c) 2006-2021, RT-Thread Development Team * * SPDX-License-Identifier: Apache-2.0 * diff --git a/libcpu/arm/realview-a8-vmm/stack.c b/libcpu/arm/realview-a8-vmm/stack.c index 619a16c446..8cf73ac05c 100644 --- a/libcpu/arm/realview-a8-vmm/stack.c +++ b/libcpu/arm/realview-a8-vmm/stack.c @@ -1,5 +1,5 @@ /* - * Copyright (c) 2006-2018, RT-Thread Development Team + * Copyright (c) 2006-2021, RT-Thread Development Team * * SPDX-License-Identifier: Apache-2.0 * diff --git a/libcpu/arm/realview-a8-vmm/trap.c b/libcpu/arm/realview-a8-vmm/trap.c index 4a522f5126..c6ca45aee7 100644 --- a/libcpu/arm/realview-a8-vmm/trap.c +++ b/libcpu/arm/realview-a8-vmm/trap.c @@ -1,5 +1,5 @@ /* - * Copyright (c) 2006-2018, RT-Thread Development Team + * Copyright (c) 2006-2021, RT-Thread Development Team * * SPDX-License-Identifier: Apache-2.0 * @@ -131,7 +131,7 @@ void rt_hw_trap_resv(struct rt_hw_exp_stack *regs) rt_hw_cpu_shutdown(); } -#define GIC_ACK_INTID_MASK 0x000003ff +#define GIC_ACK_INTID_MASK 0x000003ff void rt_hw_trap_irq(void) { diff --git a/libcpu/arm/s3c24x0/cpu.c b/libcpu/arm/s3c24x0/cpu.c index 2adf526a5c..3a72782ae4 100644 --- a/libcpu/arm/s3c24x0/cpu.c +++ b/libcpu/arm/s3c24x0/cpu.c @@ -1,5 +1,5 @@ /* - * Copyright (c) 2006-2018, RT-Thread Development Team + * Copyright (c) 2006-2021, RT-Thread Development Team * * SPDX-License-Identifier: Apache-2.0 * @@ -17,76 +17,76 @@ */ /*@{*/ -#define ICACHE_MASK (rt_uint32_t)(1 << 12) -#define DCACHE_MASK (rt_uint32_t)(1 << 2) +#define ICACHE_MASK (rt_uint32_t)(1 << 12) +#define DCACHE_MASK (rt_uint32_t)(1 << 2) #ifdef __GNUC__ rt_inline rt_uint32_t cp15_rd(void) { - rt_uint32_t i; + rt_uint32_t i; - asm ("mrc p15, 0, %0, c1, c0, 0":"=r" (i)); - return i; + asm ("mrc p15, 0, %0, c1, c0, 0":"=r" (i)); + return i; } rt_inline void cache_enable(rt_uint32_t bit) { - __asm__ __volatile__( \ - "mrc p15,0,r0,c1,c0,0\n\t" \ - "orr r0,r0,%0\n\t" \ - "mcr p15,0,r0,c1,c0,0" \ - : \ - :"r" (bit) \ - :"memory"); + __asm__ __volatile__( \ + "mrc p15,0,r0,c1,c0,0\n\t" \ + "orr r0,r0,%0\n\t" \ + "mcr p15,0,r0,c1,c0,0" \ + : \ + :"r" (bit) \ + :"memory"); } rt_inline void cache_disable(rt_uint32_t bit) { - __asm__ __volatile__( \ - "mrc p15,0,r0,c1,c0,0\n\t" \ - "bic r0,r0,%0\n\t" \ - "mcr p15,0,r0,c1,c0,0" \ - : \ - :"r" (bit) \ - :"memory"); + __asm__ __volatile__( \ + "mrc p15,0,r0,c1,c0,0\n\t" \ + "bic r0,r0,%0\n\t" \ + "mcr p15,0,r0,c1,c0,0" \ + : \ + :"r" (bit) \ + :"memory"); } #endif #ifdef __CC_ARM rt_inline rt_uint32_t cp15_rd(void) { - rt_uint32_t i; + rt_uint32_t i; - __asm - { - mrc p15, 0, i, c1, c0, 0 - } + __asm + { + mrc p15, 0, i, c1, c0, 0 + } - return i; + return i; } rt_inline void cache_enable(rt_uint32_t bit) { - rt_uint32_t value; + rt_uint32_t value; - __asm - { - mrc p15, 0, value, c1, c0, 0 - orr value, value, bit - mcr p15, 0, value, c1, c0, 0 - } + __asm + { + mrc p15, 0, value, c1, c0, 0 + orr value, value, bit + mcr p15, 0, value, c1, c0, 0 + } } rt_inline void cache_disable(rt_uint32_t bit) { - rt_uint32_t value; + rt_uint32_t value; - __asm - { - mrc p15, 0, value, c1, c0, 0 - bic value, value, bit - mcr p15, 0, value, c1, c0, 0 - } + __asm + { + mrc p15, 0, value, c1, c0, 0 + bic value, value, bit + mcr p15, 0, value, c1, c0, 0 + } } #endif @@ -96,7 +96,7 @@ rt_inline void cache_disable(rt_uint32_t bit) */ void rt_hw_cpu_icache_enable() { - cache_enable(ICACHE_MASK); + cache_enable(ICACHE_MASK); } /** @@ -105,7 +105,7 @@ void rt_hw_cpu_icache_enable() */ void rt_hw_cpu_icache_disable() { - cache_disable(ICACHE_MASK); + cache_disable(ICACHE_MASK); } /** @@ -114,7 +114,7 @@ void rt_hw_cpu_icache_disable() */ rt_base_t rt_hw_cpu_icache_status() { - return (cp15_rd() & ICACHE_MASK); + return (cp15_rd() & ICACHE_MASK); } /** @@ -123,7 +123,7 @@ rt_base_t rt_hw_cpu_icache_status() */ void rt_hw_cpu_dcache_enable() { - cache_enable(DCACHE_MASK); + cache_enable(DCACHE_MASK); } /** @@ -132,7 +132,7 @@ void rt_hw_cpu_dcache_enable() */ void rt_hw_cpu_dcache_disable() { - cache_disable(DCACHE_MASK); + cache_disable(DCACHE_MASK); } /** @@ -141,7 +141,7 @@ void rt_hw_cpu_dcache_disable() */ rt_base_t rt_hw_cpu_dcache_status() { - return (cp15_rd() & DCACHE_MASK); + return (cp15_rd() & DCACHE_MASK); } /** @@ -150,21 +150,21 @@ rt_base_t rt_hw_cpu_dcache_status() */ RT_WEAK void rt_hw_cpu_reset() { - /* Disable all interrupt except the WDT */ - INTMSK = (~((rt_uint32_t)1 << INTWDT)); + /* Disable all interrupt except the WDT */ + INTMSK = (~((rt_uint32_t)1 << INTWDT)); - /* Disable watchdog */ - WTCON = 0x0000; + /* Disable watchdog */ + WTCON = 0x0000; - /* Initialize watchdog timer count register */ - WTCNT = 0x0001; + /* Initialize watchdog timer count register */ + WTCNT = 0x0001; - /* Enable watchdog timer; assert reset at timer timeout */ - WTCON = 0x0021; + /* Enable watchdog timer; assert reset at timer timeout */ + WTCON = 0x0021; - while(1); /* loop forever and wait for reset to happen */ + while(1); /* loop forever and wait for reset to happen */ - /* NEVER REACHED */ + /* NEVER REACHED */ } /** @@ -173,14 +173,14 @@ RT_WEAK void rt_hw_cpu_reset() */ RT_WEAK void rt_hw_cpu_shutdown() { - rt_uint32_t level; - rt_kprintf("shutdown...\n"); + rt_uint32_t level; + rt_kprintf("shutdown...\n"); - level = rt_hw_interrupt_disable(); - while (level) - { - RT_ASSERT(0); - } + level = rt_hw_interrupt_disable(); + while (level) + { + RT_ASSERT(0); + } } /*@}*/ diff --git a/libcpu/arm/s3c24x0/interrupt.c b/libcpu/arm/s3c24x0/interrupt.c index 8c7aebeb25..c985fc7c86 100644 --- a/libcpu/arm/s3c24x0/interrupt.c +++ b/libcpu/arm/s3c24x0/interrupt.c @@ -1,5 +1,5 @@ /* - * Copyright (c) 2006-2018, RT-Thread Development Team + * Copyright (c) 2006-2021, RT-Thread Development Team * * SPDX-License-Identifier: Apache-2.0 * @@ -13,7 +13,7 @@ #include <rthw.h> #include "s3c24x0.h" -#define MAX_HANDLERS 32 +#define MAX_HANDLERS 32 extern rt_uint32_t rt_interrupt_nest; @@ -29,7 +29,7 @@ rt_uint32_t rt_thread_switch_interrupt_flag; static void rt_hw_interrupt_handle(int vector, void *param) { - rt_kprintf("Unhandled interrupt %d occured!!!\n", vector); + rt_kprintf("Unhandled interrupt %d occured!!!\n", vector); } /** @@ -77,7 +77,7 @@ void rt_hw_interrupt_init(void) */ void rt_hw_interrupt_mask(int vector) { - INTMSK |= 1 << vector; + INTMSK |= 1 << vector; } /** @@ -86,15 +86,15 @@ void rt_hw_interrupt_mask(int vector) */ void rt_hw_interrupt_umask(int vector) { - if (vector == INTNOTUSED6) - { - rt_kprintf("Interrupt vec %d is not used!\n", vector); - // while(1); - } - else if (vector == INTGLOBAL) - INTMSK = 0x0; - else - INTMSK &= ~(1 << vector); + if (vector == INTNOTUSED6) + { + rt_kprintf("Interrupt vec %d is not used!\n", vector); + // while(1); + } + else if (vector == INTGLOBAL) + INTMSK = 0x0; + else + INTMSK &= ~(1 << vector); } /** @@ -115,9 +115,9 @@ rt_isr_handler_t rt_hw_interrupt_install(int vector, rt_isr_handler_t handler, if (handler != RT_NULL) { #ifdef RT_USING_INTERRUPT_INFO - rt_strncpy(isr_table[vector].name, name, RT_NAME_MAX); + rt_strncpy(isr_table[vector].name, name, RT_NAME_MAX); #endif /* RT_USING_INTERRUPT_INFO */ - isr_table[vector].handler = handler; + isr_table[vector].handler = handler; isr_table[vector].param = param; } } diff --git a/libcpu/arm/s3c24x0/mmu.c b/libcpu/arm/s3c24x0/mmu.c index dc993ec9a3..4e5ef8d3c6 100644 --- a/libcpu/arm/s3c24x0/mmu.c +++ b/libcpu/arm/s3c24x0/mmu.c @@ -1,5 +1,5 @@ /* - * Copyright (c) 2006-2018, RT-Thread Development Team + * Copyright (c) 2006-2021, RT-Thread Development Team * * SPDX-License-Identifier: Apache-2.0 * @@ -12,158 +12,158 @@ #include <rtthread.h> #include "s3c24x0.h" -#define _MMUTT_STARTADDRESS 0x33FF0000 +#define _MMUTT_STARTADDRESS 0x33FF0000 -#define DESC_SEC (0x2|(1<<4)) -#define CB (3<<2) //cache_on, write_back -#define CNB (2<<2) //cache_on, write_through -#define NCB (1<<2) //cache_off,WR_BUF on -#define NCNB (0<<2) //cache_off,WR_BUF off -#define AP_RW (3<<10) //supervisor=RW, user=RW -#define AP_RO (2<<10) //supervisor=RW, user=RO +#define DESC_SEC (0x2|(1<<4)) +#define CB (3<<2) //cache_on, write_back +#define CNB (2<<2) //cache_on, write_through +#define NCB (1<<2) //cache_off,WR_BUF on +#define NCNB (0<<2) //cache_off,WR_BUF off +#define AP_RW (3<<10) //supervisor=RW, user=RW +#define AP_RO (2<<10) //supervisor=RW, user=RO -#define DOMAIN_FAULT (0x0) -#define DOMAIN_CHK (0x1) -#define DOMAIN_NOTCHK (0x3) -#define DOMAIN0 (0x0<<5) -#define DOMAIN1 (0x1<<5) +#define DOMAIN_FAULT (0x0) +#define DOMAIN_CHK (0x1) +#define DOMAIN_NOTCHK (0x3) +#define DOMAIN0 (0x0<<5) +#define DOMAIN1 (0x1<<5) -#define DOMAIN0_ATTR (DOMAIN_CHK<<0) -#define DOMAIN1_ATTR (DOMAIN_FAULT<<2) +#define DOMAIN0_ATTR (DOMAIN_CHK<<0) +#define DOMAIN1_ATTR (DOMAIN_FAULT<<2) -#define RW_CB (AP_RW|DOMAIN0|CB|DESC_SEC) -#define RW_CNB (AP_RW|DOMAIN0|CNB|DESC_SEC) -#define RW_NCNB (AP_RW|DOMAIN0|NCNB|DESC_SEC) -#define RW_FAULT (AP_RW|DOMAIN1|NCNB|DESC_SEC) +#define RW_CB (AP_RW|DOMAIN0|CB|DESC_SEC) +#define RW_CNB (AP_RW|DOMAIN0|CNB|DESC_SEC) +#define RW_NCNB (AP_RW|DOMAIN0|NCNB|DESC_SEC) +#define RW_FAULT (AP_RW|DOMAIN1|NCNB|DESC_SEC) #ifdef __GNUC__ void mmu_setttbase(register rt_uint32_t i) { - asm volatile ("mcr p15, 0, %0, c2, c0, 0": :"r" (i)); + asm volatile ("mcr p15, 0, %0, c2, c0, 0": :"r" (i)); } void mmu_set_domain(register rt_uint32_t i) { - asm volatile ("mcr p15,0, %0, c3, c0, 0": :"r" (i)); + asm volatile ("mcr p15,0, %0, c3, c0, 0": :"r" (i)); } void mmu_enable() { - register rt_uint32_t i; + register rt_uint32_t i; - /* read control register */ - asm volatile ("mrc p15, 0, %0, c1, c0, 0":"=r" (i)); + /* read control register */ + asm volatile ("mrc p15, 0, %0, c1, c0, 0":"=r" (i)); - i |= 0x1; + i |= 0x1; - /* write back to control register */ - asm volatile ("mcr p15, 0, %0, c1, c0, 0": :"r" (i)); + /* write back to control register */ + asm volatile ("mcr p15, 0, %0, c1, c0, 0": :"r" (i)); } void mmu_disable() { - register rt_uint32_t i; + register rt_uint32_t i; - /* read control register */ - asm volatile ("mrc p15, 0, %0, c1, c0, 0":"=r" (i)); + /* read control register */ + asm volatile ("mrc p15, 0, %0, c1, c0, 0":"=r" (i)); - i &= ~0x1; + i &= ~0x1; - /* write back to control register */ - asm volatile ("mcr p15, 0, %0, c1, c0, 0": :"r" (i)); + /* write back to control register */ + asm volatile ("mcr p15, 0, %0, c1, c0, 0": :"r" (i)); } void mmu_enable_icache() { - register rt_uint32_t i; + register rt_uint32_t i; - /* read control register */ - asm volatile ("mrc p15, 0, %0, c1, c0, 0":"=r" (i)); + /* read control register */ + asm volatile ("mrc p15, 0, %0, c1, c0, 0":"=r" (i)); - i |= (1 << 12); + i |= (1 << 12); - /* write back to control register */ - asm volatile ("mcr p15, 0, %0, c1, c0, 0": :"r" (i)); + /* write back to control register */ + asm volatile ("mcr p15, 0, %0, c1, c0, 0": :"r" (i)); } void mmu_enable_dcache() { - register rt_uint32_t i; + register rt_uint32_t i; - /* read control register */ - asm volatile ("mrc p15, 0, %0, c1, c0, 0":"=r" (i)); + /* read control register */ + asm volatile ("mrc p15, 0, %0, c1, c0, 0":"=r" (i)); - i |= (1 << 2); + i |= (1 << 2); - /* write back to control register */ - asm volatile ("mcr p15, 0, %0, c1, c0, 0": :"r" (i)); + /* write back to control register */ + asm volatile ("mcr p15, 0, %0, c1, c0, 0": :"r" (i)); } void mmu_disable_icache() { - register rt_uint32_t i; + register rt_uint32_t i; - /* read control register */ - asm volatile ("mrc p15, 0, %0, c1, c0, 0":"=r" (i)); + /* read control register */ + asm volatile ("mrc p15, 0, %0, c1, c0, 0":"=r" (i)); - i &= ~(1 << 12); + i &= ~(1 << 12); - /* write back to control register */ - asm volatile ("mcr p15, 0, %0, c1, c0, 0": :"r" (i)); + /* write back to control register */ + asm volatile ("mcr p15, 0, %0, c1, c0, 0": :"r" (i)); } void mmu_disable_dcache() { - register rt_uint32_t i; + register rt_uint32_t i; - /* read control register */ - asm volatile ("mrc p15, 0, %0, c1, c0, 0":"=r" (i)); + /* read control register */ + asm volatile ("mrc p15, 0, %0, c1, c0, 0":"=r" (i)); - i &= ~(1 << 2); + i &= ~(1 << 2); - /* write back to control register */ - asm volatile ("mcr p15, 0, %0, c1, c0, 0": :"r" (i)); + /* write back to control register */ + asm volatile ("mcr p15, 0, %0, c1, c0, 0": :"r" (i)); } void mmu_enable_alignfault() { - register rt_uint32_t i; + register rt_uint32_t i; - /* read control register */ - asm volatile ("mrc p15, 0, %0, c1, c0, 0":"=r" (i)); + /* read control register */ + asm volatile ("mrc p15, 0, %0, c1, c0, 0":"=r" (i)); - i |= (1 << 1); + i |= (1 << 1); - /* write back to control register */ - asm volatile ("mcr p15, 0, %0, c1, c0, 0": :"r" (i)); + /* write back to control register */ + asm volatile ("mcr p15, 0, %0, c1, c0, 0": :"r" (i)); } void mmu_disable_alignfault() { - register rt_uint32_t i; + register rt_uint32_t i; - /* read control register */ - asm volatile ("mrc p15, 0, %0, c1, c0, 0":"=r" (i)); + /* read control register */ + asm volatile ("mrc p15, 0, %0, c1, c0, 0":"=r" (i)); - i &= ~(1 << 1); + i &= ~(1 << 1); - /* write back to control register */ - asm volatile ("mcr p15, 0, %0, c1, c0, 0": :"r" (i)); + /* write back to control register */ + asm volatile ("mcr p15, 0, %0, c1, c0, 0": :"r" (i)); } void mmu_clean_invalidated_cache_index(int index) { - asm volatile ("mcr p15, 0, %0, c7, c14, 2": :"r" (index)); + asm volatile ("mcr p15, 0, %0, c7, c14, 2": :"r" (index)); } void mmu_invalidate_tlb() { - asm volatile ("mcr p15, 0, %0, c8, c7, 0": :"r" (0)); + asm volatile ("mcr p15, 0, %0, c8, c7, 0": :"r" (0)); } void mmu_invalidate_icache() { - asm volatile ("mcr p15, 0, %0, c7, c5, 0": :"r" (0)); + asm volatile ("mcr p15, 0, %0, c7, c5, 0": :"r" (0)); } #endif @@ -320,71 +320,71 @@ void mmu_setmtt(int vaddrStart,int vaddrEnd,int paddrStart,int attr) nSec=(vaddrEnd>>20)-(vaddrStart>>20); for(i=0;i<=nSec;i++) { - *pTT = attr |(((paddrStart>>20)+i)<<20); - pTT++; + *pTT = attr |(((paddrStart>>20)+i)<<20); + pTT++; } } void rt_hw_mmu_init(void) { - int i,j; - //========================== IMPORTANT NOTE ========================= - //The current stack and code area can't be re-mapped in this routine. - //If you want memory map mapped freely, your own sophiscated mmu - //initialization code is needed. - //=================================================================== + int i,j; + //========================== IMPORTANT NOTE ========================= + //The current stack and code area can't be re-mapped in this routine. + //If you want memory map mapped freely, your own sophiscated mmu + //initialization code is needed. + //=================================================================== - mmu_disable_dcache(); - mmu_disable_icache(); + mmu_disable_dcache(); + mmu_disable_icache(); - //If write-back is used,the DCache should be cleared. - for(i=0;i<64;i++) - for(j=0;j<8;j++) - mmu_clean_invalidated_cache_index((i<<26)|(j<<5)); + //If write-back is used,the DCache should be cleared. + for(i=0;i<64;i++) + for(j=0;j<8;j++) + mmu_clean_invalidated_cache_index((i<<26)|(j<<5)); - mmu_invalidate_icache(); + mmu_invalidate_icache(); - //To complete mmu_Init() fast, Icache may be turned on here. - mmu_enable_icache(); + //To complete mmu_Init() fast, Icache may be turned on here. + mmu_enable_icache(); - mmu_disable(); - mmu_invalidate_tlb(); + mmu_disable(); + mmu_invalidate_tlb(); - //mmu_setmtt(int vaddrStart,int vaddrEnd,int paddrStart,int attr); - mmu_setmtt(0x00000000,0x07f00000,0x00000000,RW_CNB); //bank0 - mmu_setmtt(0x00000000,0x03f00000,(int)0x30000000,RW_CB); //bank0 - mmu_setmtt(0x04000000,0x07f00000,0,RW_NCNB); //bank0 - mmu_setmtt(0x08000000,0x0ff00000,0x08000000,RW_CNB); //bank1 - mmu_setmtt(0x10000000,0x17f00000,0x10000000,RW_NCNB); //bank2 - mmu_setmtt(0x18000000,0x1ff00000,0x18000000,RW_NCNB); //bank3 - //mmu_setmtt(0x20000000,0x27f00000,0x20000000,RW_CB); //bank4 - mmu_setmtt(0x20000000,0x27f00000,0x20000000,RW_NCNB); //bank4 for DM9000 - mmu_setmtt(0x28000000,0x2ff00000,0x28000000,RW_NCNB); //bank5 - //30f00000->30100000, 31000000->30200000 - mmu_setmtt(0x30000000,0x30100000,0x30000000,RW_CB); //bank6-1 - mmu_setmtt(0x30200000,0x33e00000,0x30200000,RW_CB); //bank6-2 + //mmu_setmtt(int vaddrStart,int vaddrEnd,int paddrStart,int attr); + mmu_setmtt(0x00000000,0x07f00000,0x00000000,RW_CNB); //bank0 + mmu_setmtt(0x00000000,0x03f00000,(int)0x30000000,RW_CB); //bank0 + mmu_setmtt(0x04000000,0x07f00000,0,RW_NCNB); //bank0 + mmu_setmtt(0x08000000,0x0ff00000,0x08000000,RW_CNB); //bank1 + mmu_setmtt(0x10000000,0x17f00000,0x10000000,RW_NCNB); //bank2 + mmu_setmtt(0x18000000,0x1ff00000,0x18000000,RW_NCNB); //bank3 + //mmu_setmtt(0x20000000,0x27f00000,0x20000000,RW_CB); //bank4 + mmu_setmtt(0x20000000,0x27f00000,0x20000000,RW_NCNB); //bank4 for DM9000 + mmu_setmtt(0x28000000,0x2ff00000,0x28000000,RW_NCNB); //bank5 + //30f00000->30100000, 31000000->30200000 + mmu_setmtt(0x30000000,0x30100000,0x30000000,RW_CB); //bank6-1 + mmu_setmtt(0x30200000,0x33e00000,0x30200000,RW_CB); //bank6-2 - mmu_setmtt(0x33f00000,0x34000000,0x33f00000,RW_NCNB); //bank6-3 - mmu_setmtt(0x38000000,0x3ff00000,0x38000000,RW_NCNB); //bank7 + mmu_setmtt(0x33f00000,0x34000000,0x33f00000,RW_NCNB); //bank6-3 + mmu_setmtt(0x38000000,0x3ff00000,0x38000000,RW_NCNB); //bank7 - mmu_setmtt(0x40000000,0x47f00000,0x40000000,RW_NCNB); //SFR - mmu_setmtt(0x48000000,0x5af00000,0x48000000,RW_NCNB); //SFR - mmu_setmtt(0x5b000000,0x5b000000,0x5b000000,RW_NCNB); //SFR - mmu_setmtt(0x5b100000,0xfff00000,0x5b100000,RW_FAULT);//not used - mmu_setmtt(0x60000000,0x67f00000,0x60000000,RW_NCNB); //SFR + mmu_setmtt(0x40000000,0x47f00000,0x40000000,RW_NCNB); //SFR + mmu_setmtt(0x48000000,0x5af00000,0x48000000,RW_NCNB); //SFR + mmu_setmtt(0x5b000000,0x5b000000,0x5b000000,RW_NCNB); //SFR + mmu_setmtt(0x5b100000,0xfff00000,0x5b100000,RW_FAULT);//not used + mmu_setmtt(0x60000000,0x67f00000,0x60000000,RW_NCNB); //SFR - mmu_setttbase(_MMUTT_STARTADDRESS); + mmu_setttbase(_MMUTT_STARTADDRESS); - /* DOMAIN1: no_access, DOMAIN0,2~15=client(AP is checked) */ - mmu_set_domain(0x55555550|DOMAIN1_ATTR|DOMAIN0_ATTR); + /* DOMAIN1: no_access, DOMAIN0,2~15=client(AP is checked) */ + mmu_set_domain(0x55555550|DOMAIN1_ATTR|DOMAIN0_ATTR); - mmu_enable_alignfault(); + mmu_enable_alignfault(); - mmu_enable(); + mmu_enable(); - /* ICache enable */ - mmu_enable_icache(); - /* DCache should be turned on after mmu is turned on. */ - mmu_enable_dcache(); + /* ICache enable */ + mmu_enable_icache(); + /* DCache should be turned on after mmu is turned on. */ + mmu_enable_dcache(); } diff --git a/libcpu/arm/s3c24x0/rtc.c b/libcpu/arm/s3c24x0/rtc.c index 73de840b37..0f9484405c 100644 --- a/libcpu/arm/s3c24x0/rtc.c +++ b/libcpu/arm/s3c24x0/rtc.c @@ -1,14 +1,14 @@ /* - * Copyright (c) 2006-2018, RT-Thread Development Team + * Copyright (c) 2006-2021, RT-Thread Development Team * * SPDX-License-Identifier: Apache-2.0 * * Change Logs: * Date Author Notes - * 2009-04-26 yi.qiu first version - * 2010-03-18 Gary Lee add functions such as GregorianDay - * and rtc_time_to_tm - * 2009-03-20 yi.qiu clean up + * 2009-04-26 yi.qiu first version + * 2010-03-18 Gary Lee add functions such as GregorianDay + * and rtc_time_to_tm + * 2009-03-20 yi.qiu clean up */ #include <rtthread.h> @@ -17,50 +17,50 @@ // #define RTC_DEBUG -#define RTC_ENABLE RTCCON |= 0x01; /*RTC read and write enable */ -#define RTC_DISABLE RTCCON &= ~0x01; /* RTC read and write disable */ -#define BCD2BIN(n) (((((n) >> 4) & 0x0F) * 10) + ((n) & 0x0F)) -#define BIN2BCD(n) ((((n) / 10) << 4) | ((n) % 10)) +#define RTC_ENABLE RTCCON |= 0x01; /*RTC read and write enable */ +#define RTC_DISABLE RTCCON &= ~0x01; /* RTC read and write disable */ +#define BCD2BIN(n) (((((n) >> 4) & 0x0F) * 10) + ((n) & 0x0F)) +#define BIN2BCD(n) ((((n) / 10) << 4) | ((n) % 10)) /** * This function get rtc time */ void rt_hw_rtc_get(struct tm *ti) { - rt_uint8_t sec, min, hour, mday, wday, mon, year; + rt_uint8_t sec, min, hour, mday, wday, mon, year; - /* enable access to RTC registers */ - RTCCON |= RTC_ENABLE; + /* enable access to RTC registers */ + RTCCON |= RTC_ENABLE; - /* read RTC registers */ - do - { - sec = BCDSEC; - min = BCDMIN; - hour = BCDHOUR; - mday = BCDDATE; - wday = BCDDAY; - mon = BCDMON; - year = BCDYEAR; + /* read RTC registers */ + do + { + sec = BCDSEC; + min = BCDMIN; + hour = BCDHOUR; + mday = BCDDATE; + wday = BCDDAY; + mon = BCDMON; + year = BCDYEAR; } while (sec != BCDSEC); #ifdef RTC_DEBUG - rt_kprintf("sec:%x min:%x hour:%x mday:%x wday:%x mon:%x year:%x\n", - sec, min, hour, mday, wday, mon, year); + rt_kprintf("sec:%x min:%x hour:%x mday:%x wday:%x mon:%x year:%x\n", + sec, min, hour, mday, wday, mon, year); #endif - /* disable access to RTC registers */ - RTC_DISABLE + /* disable access to RTC registers */ + RTC_DISABLE - ti->tm_sec = BCD2BIN(sec & 0x7F); - ti->tm_min = BCD2BIN(min & 0x7F); - ti->tm_hour = BCD2BIN(hour & 0x3F); - ti->tm_mday = BCD2BIN(mday & 0x3F); - ti->tm_mon = BCD2BIN(mon & 0x1F); - ti->tm_year = BCD2BIN(year); - ti->tm_wday = BCD2BIN(wday & 0x07); - ti->tm_yday = 0; - ti->tm_isdst = 0; + ti->tm_sec = BCD2BIN(sec & 0x7F); + ti->tm_min = BCD2BIN(min & 0x7F); + ti->tm_hour = BCD2BIN(hour & 0x3F); + ti->tm_mday = BCD2BIN(mday & 0x3F); + ti->tm_mon = BCD2BIN(mon & 0x1F); + ti->tm_year = BCD2BIN(year); + ti->tm_wday = BCD2BIN(wday & 0x07); + ti->tm_yday = 0; + ti->tm_isdst = 0; } /** @@ -68,32 +68,32 @@ void rt_hw_rtc_get(struct tm *ti) */ void rt_hw_rtc_set(struct tm *ti) { - rt_uint8_t sec, min, hour, mday, wday, mon, year; + rt_uint8_t sec, min, hour, mday, wday, mon, year; + + year = BIN2BCD(ti->tm_year); + mon = BIN2BCD(ti->tm_mon); + wday = BIN2BCD(ti->tm_wday); + mday = BIN2BCD(ti->tm_mday); + hour = BIN2BCD(ti->tm_hour); + min = BIN2BCD(ti->tm_min); + sec = BIN2BCD(ti->tm_sec); - year = BIN2BCD(ti->tm_year); - mon = BIN2BCD(ti->tm_mon); - wday = BIN2BCD(ti->tm_wday); - mday = BIN2BCD(ti->tm_mday); - hour = BIN2BCD(ti->tm_hour); - min = BIN2BCD(ti->tm_min); - sec = BIN2BCD(ti->tm_sec); + /* enable access to RTC registers */ + RTC_ENABLE - /* enable access to RTC registers */ - RTC_ENABLE + do{ + /* write RTC registers */ + BCDSEC = sec; + BCDMIN = min; + BCDHOUR = hour; + BCDDATE = mday; + BCDDAY = wday; + BCDMON = mon; + BCDYEAR = year; + }while (sec != BCDSEC); - do{ - /* write RTC registers */ - BCDSEC = sec; - BCDMIN = min; - BCDHOUR = hour; - BCDDATE = mday; - BCDDAY = wday; - BCDMON = mon; - BCDYEAR = year; - }while (sec != BCDSEC); - - /* disable access to RTC registers */ - RTC_DISABLE + /* disable access to RTC registers */ + RTC_DISABLE } /** @@ -101,26 +101,26 @@ void rt_hw_rtc_set(struct tm *ti) */ void rt_hw_rtc_reset (void) { - RTCCON = (RTCCON & ~0x06) | 0x08; - RTCCON &= ~(0x08|0x01); + RTCCON = (RTCCON & ~0x06) | 0x08; + RTCCON &= ~(0x08|0x01); } static struct rt_device rtc; static rt_err_t rtc_open(rt_device_t dev, rt_uint16_t oflag) { - RTC_ENABLE - return RT_EOK; + RTC_ENABLE + return RT_EOK; } static rt_err_t rtc_close(rt_device_t dev) { - RTC_DISABLE - return RT_EOK; + RTC_DISABLE + return RT_EOK; } static rt_size_t rtc_read(rt_device_t dev, rt_off_t pos, void* buffer, rt_size_t size) { - return RT_EOK; + return RT_EOK; } static rt_err_t rtc_control(rt_device_t dev, int cmd, void *args) @@ -150,36 +150,36 @@ static rt_err_t rtc_control(rt_device_t dev, int cmd, void *args) void rt_hw_rtc_init(void) { - rtc.type = RT_Device_Class_RTC; + rtc.type = RT_Device_Class_RTC; - /* register rtc device */ - rtc.init = RT_NULL; - rtc.open = rtc_open; - rtc.close = rtc_close; - rtc.read = rtc_read; - rtc.write = RT_NULL; - rtc.control = rtc_control; - - /* no private */ - rtc.user_data = RT_NULL; - - rt_device_register(&rtc, "rtc", RT_DEVICE_FLAG_RDWR); + /* register rtc device */ + rtc.init = RT_NULL; + rtc.open = rtc_open; + rtc.close = rtc_close; + rtc.read = rtc_read; + rtc.write = RT_NULL; + rtc.control = rtc_control; + + /* no private */ + rtc.user_data = RT_NULL; + + rt_device_register(&rtc, "rtc", RT_DEVICE_FLAG_RDWR); } #ifdef RT_USING_FINSH #include <finsh.h> void list_date() { - time_t time; - rt_device_t device; + time_t time; + rt_device_t device; - device = rt_device_find("rtc"); - if (device != RT_NULL) - { - rt_device_control(device, RT_DEVICE_CTRL_RTC_GET_TIME, &time); + device = rt_device_find("rtc"); + if (device != RT_NULL) + { + rt_device_control(device, RT_DEVICE_CTRL_RTC_GET_TIME, &time); - rt_kprintf("%d, %s\n", time, ctime(&time)); - } + rt_kprintf("%d, %s\n", time, ctime(&time)); + } } FINSH_FUNCTION_EXPORT(list_date, list date); #endif diff --git a/libcpu/arm/s3c24x0/rtc.h b/libcpu/arm/s3c24x0/rtc.h index aafa714b0e..78219325a5 100644 --- a/libcpu/arm/s3c24x0/rtc.h +++ b/libcpu/arm/s3c24x0/rtc.h @@ -1,5 +1,5 @@ /* - * Copyright (c) 2006-2018, RT-Thread Development Team + * Copyright (c) 2006-2021, RT-Thread Development Team * * SPDX-License-Identifier: Apache-2.0 * diff --git a/libcpu/arm/s3c24x0/s3c24x0.h b/libcpu/arm/s3c24x0/s3c24x0.h index 03749c5227..75e1eb0119 100644 --- a/libcpu/arm/s3c24x0/s3c24x0.h +++ b/libcpu/arm/s3c24x0/s3c24x0.h @@ -1,5 +1,5 @@ /* - * Copyright (c) 2006-2018, RT-Thread Development Team + * Copyright (c) 2006-2021, RT-Thread Development Team * * SPDX-License-Identifier: Apache-2.0 * @@ -22,7 +22,7 @@ extern "C" { */ /*@{*/ -// Memory control +// Memory control #define BWSCON (*(volatile unsigned *)0x48000000) //Bus width & wait status #define BANKCON0 (*(volatile unsigned *)0x48000004) //Boot ROM control #define BANKCON1 (*(volatile unsigned *)0x48000008) //BANK1 control @@ -101,7 +101,7 @@ extern "C" { #define CLKCON (*(volatile unsigned *)0x4c00000c) //Clock generator control #define CLKSLOW (*(volatile unsigned *)0x4c000010) //Slow clock control #define CLKDIVN (*(volatile unsigned *)0x4c000014) //Clock divider control -#define CAMDIVN (*(volatile unsigned *)0x4c000018) //USB, CAM Clock divider control +#define CAMDIVN (*(volatile unsigned *)0x4c000018) //USB, CAM Clock divider control // LCD CONTROLLER @@ -114,7 +114,7 @@ extern "C" { #define LCDSADDR2 (*(volatile unsigned *)0x4d000018) //STN/TFT Frame buffer start address 2 #define LCDSADDR3 (*(volatile unsigned *)0x4d00001c) //STN/TFT Virtual screen address set #define REDLUT (*(volatile unsigned *)0x4d000020) //STN Red lookup table -#define GREENLUT (*(volatile unsigned *)0x4d000024) //STN Green lookup table +#define GREENLUT (*(volatile unsigned *)0x4d000024) //STN Green lookup table #define BLUELUT (*(volatile unsigned *)0x4d000028) //STN Blue lookup table #define DITHMODE (*(volatile unsigned *)0x4d00004c) //STN Dithering mode #define TPAL (*(volatile unsigned *)0x4d000050) //TFT Temporary palette @@ -223,10 +223,10 @@ extern "C" { #define TCNTO4 (*(volatile unsigned *)0x51000040) //Timer count observation 4 // Added for 2440 -#define FLTOUT (*(volatile unsigned *)0x560000c0) // Filter output(Read only) -#define DSC0 (*(volatile unsigned *)0x560000c4) // Strength control register 0 -#define DSC1 (*(volatile unsigned *)0x560000c8) // Strength control register 1 -#define MSLCON (*(volatile unsigned *)0x560000cc) // Memory sleep control register +#define FLTOUT (*(volatile unsigned *)0x560000c0) // Filter output(Read only) +#define DSC0 (*(volatile unsigned *)0x560000c4) // Strength control register 0 +#define DSC1 (*(volatile unsigned *)0x560000c8) // Strength control register 1 +#define MSLCON (*(volatile unsigned *)0x560000cc) // Memory sleep control register // USB DEVICE @@ -388,9 +388,9 @@ extern "C" { #define GPHDAT (*(volatile unsigned *)0x56000074) //Port H data #define GPHUP (*(volatile unsigned *)0x56000078) //Pull-up control H -#define GPJCON (*(volatile unsigned *)0x560000d0) //Port J control -#define GPJDAT (*(volatile unsigned *)0x560000d4) //Port J data -#define GPJUP (*(volatile unsigned *)0x560000d8) //Pull-up control J +#define GPJCON (*(volatile unsigned *)0x560000d0) //Port J control +#define GPJDAT (*(volatile unsigned *)0x560000d4) //Port J data +#define GPJUP (*(volatile unsigned *)0x560000d8) //Pull-up control J #define MISCCR (*(volatile unsigned *)0x56000080) //Miscellaneous control #define DCLKCON (*(volatile unsigned *)0x56000084) //DCLK0/1 control @@ -495,7 +495,7 @@ extern "C" { #ifdef __BIG_ENDIAN /* edited for 2440A */ #define SDIDAT (*(volatile unsigned *)0x5a00004c) #else // Little Endian -#define SDIDAT (*(volatile unsigned *)0x5a000040) +#define SDIDAT (*(volatile unsigned *)0x5a000040) #endif //SD Interface // PENDING BIT @@ -562,40 +562,40 @@ extern "C" { #define ClearPending(bit) {SRCPND = bit;INTPND = bit;INTPND;} //Wait until INTPND is changed for the case that the ISR is very short. -#define INTGLOBAL 32 +#define INTGLOBAL 32 /*****************************/ /* CPU Mode */ /*****************************/ -#define USERMODE 0x10 -#define FIQMODE 0x11 -#define IRQMODE 0x12 -#define SVCMODE 0x13 -#define ABORTMODE 0x17 -#define UNDEFMODE 0x1b -#define MODEMASK 0x1f -#define NOINT 0xc0 +#define USERMODE 0x10 +#define FIQMODE 0x11 +#define IRQMODE 0x12 +#define SVCMODE 0x13 +#define ABORTMODE 0x17 +#define UNDEFMODE 0x1b +#define MODEMASK 0x1f +#define NOINT 0xc0 struct rt_hw_register { - rt_uint32_t r0; - rt_uint32_t r1; - rt_uint32_t r2; - rt_uint32_t r3; - rt_uint32_t r4; - rt_uint32_t r5; - rt_uint32_t r6; - rt_uint32_t r7; - rt_uint32_t r8; - rt_uint32_t r9; - rt_uint32_t r10; - rt_uint32_t fp; - rt_uint32_t ip; - rt_uint32_t sp; - rt_uint32_t lr; - rt_uint32_t pc; - rt_uint32_t cpsr; - rt_uint32_t ORIG_r0; + rt_uint32_t r0; + rt_uint32_t r1; + rt_uint32_t r2; + rt_uint32_t r3; + rt_uint32_t r4; + rt_uint32_t r5; + rt_uint32_t r6; + rt_uint32_t r7; + rt_uint32_t r8; + rt_uint32_t r9; + rt_uint32_t r10; + rt_uint32_t fp; + rt_uint32_t ip; + rt_uint32_t sp; + rt_uint32_t lr; + rt_uint32_t pc; + rt_uint32_t cpsr; + rt_uint32_t ORIG_r0; }; #ifdef __cplusplus diff --git a/libcpu/arm/s3c24x0/stack.c b/libcpu/arm/s3c24x0/stack.c index 82607c3590..99938e2317 100644 --- a/libcpu/arm/s3c24x0/stack.c +++ b/libcpu/arm/s3c24x0/stack.c @@ -1,5 +1,5 @@ /* - * Copyright (c) 2006-2018, RT-Thread Development Team + * Copyright (c) 2006-2021, RT-Thread Development Team * * SPDX-License-Identifier: Apache-2.0 * diff --git a/libcpu/arm/s3c24x0/system_clock.c b/libcpu/arm/s3c24x0/system_clock.c index 833b193cce..235c5e5e5c 100644 --- a/libcpu/arm/s3c24x0/system_clock.c +++ b/libcpu/arm/s3c24x0/system_clock.c @@ -1,5 +1,5 @@ /* - * Copyright (c) 2006-2018, RT-Thread Development Team + * Copyright (c) 2006-2021, RT-Thread Development Team * * SPDX-License-Identifier: Apache-2.0 * @@ -11,21 +11,21 @@ #include <rtthread.h> #include "s3c24x0.h" -#define CONFIG_SYS_CLK_FREQ 12000000 // Fin = 12.00MHz +#define CONFIG_SYS_CLK_FREQ 12000000 // Fin = 12.00MHz #if CONFIG_SYS_CLK_FREQ == 12000000 - /* MPLL=2*12*100/6=400MHz */ - #define MPL_MIDV 92 /* m=MPL_MDIV+8=100 */ - #define MPL_PDIV 4 /* p=MPL_PDIV+2=6 */ - #define MPL_SDIV 0 /* s=MPL_SDIV=0 */ - /* UPLL=12*64/8=96MHz */ - #define UPL_MDIV 56 /* m=UPL_MDIV+8=64 */ - #define UPL_PDIV 2 /* p=UPL_PDIV+2=4 */ - #define UPL_SDIV 1 /* s=UPL_SDIV=1 */ - /* System clock divider FCLK:HCLK:PCLK=1:4:8 */ - #define DIVN_UPLL 0x1 /* UCLK = UPLL clock / 2 */ - #define HDIVN 0x2 /* HCLK = FCLK / 4 */ - #define PDIVN 0x1 /* PCLK = HCLK / 2 */ + /* MPLL=2*12*100/6=400MHz */ + #define MPL_MIDV 92 /* m=MPL_MDIV+8=100 */ + #define MPL_PDIV 4 /* p=MPL_PDIV+2=6 */ + #define MPL_SDIV 0 /* s=MPL_SDIV=0 */ + /* UPLL=12*64/8=96MHz */ + #define UPL_MDIV 56 /* m=UPL_MDIV+8=64 */ + #define UPL_PDIV 2 /* p=UPL_PDIV+2=4 */ + #define UPL_SDIV 1 /* s=UPL_SDIV=1 */ + /* System clock divider FCLK:HCLK:PCLK=1:4:8 */ + #define DIVN_UPLL 0x1 /* UCLK = UPLL clock / 2 */ + #define HDIVN 0x2 /* HCLK = FCLK / 4 */ + #define PDIVN 0x1 /* PCLK = HCLK / 2 */ #endif rt_uint32_t PCLK; @@ -35,60 +35,60 @@ rt_uint32_t UCLK; void rt_hw_get_clock(void) { - rt_uint32_t val; - rt_uint8_t m, p, s; + rt_uint32_t val; + rt_uint8_t m, p, s; - val = MPLLCON; - m = (val>>12)&0xff; - p = (val>>4)&0x3f; - s = val&3; + val = MPLLCON; + m = (val>>12)&0xff; + p = (val>>4)&0x3f; + s = val&3; - FCLK = ((m+8)*(CONFIG_SYS_CLK_FREQ/100)*2)/((p+2)*(1<<s))*100; + FCLK = ((m+8)*(CONFIG_SYS_CLK_FREQ/100)*2)/((p+2)*(1<<s))*100; - val = CLKDIVN; - m = (val>>1)&3; - p = val&1; + val = CLKDIVN; + m = (val>>1)&3; + p = val&1; - switch (m) { - case 0: - HCLK = FCLK; - break; - case 1: - HCLK = FCLK>>1; - break; - case 2: - if(s&2) - HCLK = FCLK>>3; - else - HCLK = FCLK>>2; - break; - case 3: - if(s&1) - HCLK = FCLK/6; - else - HCLK = FCLK/3; - break; + switch (m) { + case 0: + HCLK = FCLK; + break; + case 1: + HCLK = FCLK>>1; + break; + case 2: + if(s&2) + HCLK = FCLK>>3; + else + HCLK = FCLK>>2; + break; + case 3: + if(s&1) + HCLK = FCLK/6; + else + HCLK = FCLK/3; + break; } - if(p) - PCLK = HCLK>>1; - else - PCLK = HCLK; + if(p) + PCLK = HCLK>>1; + else + PCLK = HCLK; } void rt_hw_set_mpll_clock(rt_uint8_t sdiv, rt_uint8_t pdiv, rt_uint8_t mdiv) { - MPLLCON = sdiv | (pdiv<<4) | (mdiv<<12); + MPLLCON = sdiv | (pdiv<<4) | (mdiv<<12); } void rt_hw_set_upll_clock(rt_uint8_t sdiv, rt_uint8_t pdiv, rt_uint8_t mdiv) { - UPLLCON = (mdiv<<12) | (pdiv<<4) | sdiv; + UPLLCON = (mdiv<<12) | (pdiv<<4) | sdiv; } void rt_hw_set_divider(rt_uint8_t hdivn, rt_uint8_t pdivn) { - CLKDIVN = (hdivn<<1) | pdivn; + CLKDIVN = (hdivn<<1) | pdivn; } /** @@ -96,9 +96,9 @@ void rt_hw_set_divider(rt_uint8_t hdivn, rt_uint8_t pdivn) */ void rt_hw_clock_init(void) { - LOCKTIME = 0xFFFFFFFF; - rt_hw_set_mpll_clock(MPL_SDIV, MPL_PDIV, MPL_MIDV); - rt_hw_set_upll_clock(UPL_SDIV, UPL_PDIV, UPL_MDIV); - rt_hw_set_divider(HDIVN, PDIVN); + LOCKTIME = 0xFFFFFFFF; + rt_hw_set_mpll_clock(MPL_SDIV, MPL_PDIV, MPL_MIDV); + rt_hw_set_upll_clock(UPL_SDIV, UPL_PDIV, UPL_MDIV); + rt_hw_set_divider(HDIVN, PDIVN); } diff --git a/libcpu/arm/s3c24x0/trap.c b/libcpu/arm/s3c24x0/trap.c index f2f389c6b0..f0e8a7097a 100644 --- a/libcpu/arm/s3c24x0/trap.c +++ b/libcpu/arm/s3c24x0/trap.c @@ -1,5 +1,5 @@ /* - * Copyright (c) 2006-2018, RT-Thread Development Team + * Copyright (c) 2006-2021, RT-Thread Development Team * * SPDX-License-Identifier: Apache-2.0 * @@ -34,13 +34,13 @@ extern long list_thread(void); void rt_hw_show_register (struct rt_hw_register *regs) { - rt_kprintf("Execption:\n"); - rt_kprintf("r00:0x%08x r01:0x%08x r02:0x%08x r03:0x%08x\n", regs->r0, regs->r1, regs->r2, regs->r3); - rt_kprintf("r04:0x%08x r05:0x%08x r06:0x%08x r07:0x%08x\n", regs->r4, regs->r5, regs->r6, regs->r7); - rt_kprintf("r08:0x%08x r09:0x%08x r10:0x%08x\n", regs->r8, regs->r9, regs->r10); - rt_kprintf("fp :0x%08x ip :0x%08x\n", regs->fp, regs->ip); - rt_kprintf("sp :0x%08x lr :0x%08x pc :0x%08x\n", regs->sp, regs->lr, regs->pc); - rt_kprintf("cpsr:0x%08x\n", regs->cpsr); + rt_kprintf("Execption:\n"); + rt_kprintf("r00:0x%08x r01:0x%08x r02:0x%08x r03:0x%08x\n", regs->r0, regs->r1, regs->r2, regs->r3); + rt_kprintf("r04:0x%08x r05:0x%08x r06:0x%08x r07:0x%08x\n", regs->r4, regs->r5, regs->r6, regs->r7); + rt_kprintf("r08:0x%08x r09:0x%08x r10:0x%08x\n", regs->r8, regs->r9, regs->r10); + rt_kprintf("fp :0x%08x ip :0x%08x\n", regs->fp, regs->ip); + rt_kprintf("sp :0x%08x lr :0x%08x pc :0x%08x\n", regs->sp, regs->lr, regs->pc); + rt_kprintf("cpsr:0x%08x\n", regs->cpsr); } /** @@ -53,15 +53,15 @@ void rt_hw_show_register (struct rt_hw_register *regs) */ void rt_hw_trap_udef(struct rt_hw_register *regs) { - rt_hw_show_register(regs); + rt_hw_show_register(regs); - rt_kprintf("undefined instruction\n"); - rt_kprintf("thread - %s stack:\n", rt_current_thread->name); + rt_kprintf("undefined instruction\n"); + rt_kprintf("thread - %s stack:\n", rt_current_thread->name); #ifdef RT_USING_FINSH - list_thread(); + list_thread(); #endif - rt_hw_cpu_shutdown(); + rt_hw_cpu_shutdown(); } /** @@ -75,10 +75,10 @@ void rt_hw_trap_udef(struct rt_hw_register *regs) */ void rt_hw_trap_swi(struct rt_hw_register *regs) { - rt_hw_show_register(regs); + rt_hw_show_register(regs); - rt_kprintf("software interrupt\n"); - rt_hw_cpu_shutdown(); + rt_kprintf("software interrupt\n"); + rt_hw_cpu_shutdown(); } /** @@ -91,15 +91,15 @@ void rt_hw_trap_swi(struct rt_hw_register *regs) */ void rt_hw_trap_pabt(struct rt_hw_register *regs) { - rt_hw_show_register(regs); + rt_hw_show_register(regs); - rt_kprintf("prefetch abort\n"); - rt_kprintf("thread - %s stack:\n", rt_current_thread->name); + rt_kprintf("prefetch abort\n"); + rt_kprintf("thread - %s stack:\n", rt_current_thread->name); #ifdef RT_USING_FINSH - list_thread(); + list_thread(); #endif - rt_hw_cpu_shutdown(); + rt_hw_cpu_shutdown(); } /** @@ -112,15 +112,15 @@ void rt_hw_trap_pabt(struct rt_hw_register *regs) */ void rt_hw_trap_dabt(struct rt_hw_register *regs) { - rt_hw_show_register(regs); + rt_hw_show_register(regs); - rt_kprintf("data abort\n"); - rt_kprintf("thread - %s stack:\n", rt_current_thread->name); + rt_kprintf("data abort\n"); + rt_kprintf("thread - %s stack:\n", rt_current_thread->name); #ifdef RT_USING_FINSH - list_thread(); + list_thread(); #endif - rt_hw_cpu_shutdown(); + rt_hw_cpu_shutdown(); } /** @@ -132,9 +132,9 @@ void rt_hw_trap_dabt(struct rt_hw_register *regs) */ void rt_hw_trap_resv(struct rt_hw_register *regs) { - rt_kprintf("not used\n"); - rt_hw_show_register(regs); - rt_hw_cpu_shutdown(); + rt_kprintf("not used\n"); + rt_hw_show_register(regs); + rt_hw_cpu_shutdown(); } extern struct rt_irq_desc isr_table[]; @@ -161,13 +161,13 @@ void rt_hw_trap_irq(void) ClearPending(1 << irq); #ifdef RT_USING_INTERRUPT_INFO - isr_table[irq].counter++; + isr_table[irq].counter++; #endif /* RT_USING_INTERRUPT_INFO */ } void rt_hw_trap_fiq(void) { - rt_kprintf("fast interrupt request\n"); + rt_kprintf("fast interrupt request\n"); } /*@}*/ diff --git a/libcpu/arm/s3c44b0/cpu.c b/libcpu/arm/s3c44b0/cpu.c index 9d60b09688..d80ca054e2 100644 --- a/libcpu/arm/s3c44b0/cpu.c +++ b/libcpu/arm/s3c44b0/cpu.c @@ -1,5 +1,5 @@ /* - * Copyright (c) 2006-2018, RT-Thread Development Team + * Copyright (c) 2006-2021, RT-Thread Development Team * * SPDX-License-Identifier: Apache-2.0 * @@ -22,29 +22,29 @@ */ void rt_hw_cpu_icache_enable() { - rt_base_t reg; + rt_base_t reg; - volatile int i; - /* flush cycle */ - for(i = 0x10002000; i < 0x10004800; i+=16) - { - *((int *)i)=0x0; - } + volatile int i; + /* flush cycle */ + for(i = 0x10002000; i < 0x10004800; i+=16) + { + *((int *)i)=0x0; + } - /* - * Init cache - * Non-cacheable area (everything outside RAM) - * 0x0000:0000 - 0x0C00:0000 - */ - NCACHBE0 = 0xC0000000; - NCACHBE1 = 0x00000000; + /* + * Init cache + * Non-cacheable area (everything outside RAM) + * 0x0000:0000 - 0x0C00:0000 + */ + NCACHBE0 = 0xC0000000; + NCACHBE1 = 0x00000000; - /* - Enable chache - */ - reg = SYSCFG; - reg |= 0x00000006; /* 8kB */ - SYSCFG = reg; + /* + Enable chache + */ + reg = SYSCFG; + reg |= 0x00000006; /* 8kB */ + SYSCFG = reg; } /** @@ -53,11 +53,11 @@ void rt_hw_cpu_icache_enable() */ void rt_hw_cpu_icache_disable() { - rt_base_t reg; + rt_base_t reg; - reg = SYSCFG; - reg &= ~0x00000006; /* 8kB */ - SYSCFG = reg; + reg = SYSCFG; + reg &= ~0x00000006; /* 8kB */ + SYSCFG = reg; } /** @@ -66,7 +66,7 @@ void rt_hw_cpu_icache_disable() */ rt_base_t rt_hw_cpu_icache_status() { - return 0; + return 0; } /** @@ -75,7 +75,7 @@ rt_base_t rt_hw_cpu_icache_status() */ void rt_hw_cpu_dcache_enable() { - rt_hw_cpu_icache_enable(); + rt_hw_cpu_icache_enable(); } /** @@ -84,7 +84,7 @@ void rt_hw_cpu_dcache_enable() */ void rt_hw_cpu_dcache_disable() { - rt_hw_cpu_icache_disable(); + rt_hw_cpu_icache_disable(); } /** @@ -93,7 +93,7 @@ void rt_hw_cpu_dcache_disable() */ rt_base_t rt_hw_cpu_dcache_status() { - return rt_hw_cpu_icache_status(); + return rt_hw_cpu_icache_status(); } /** @@ -110,9 +110,9 @@ RT_WEAK void rt_hw_cpu_reset() */ RT_WEAK void rt_hw_cpu_shutdown() { - rt_kprintf("shutdown...\n"); + rt_kprintf("shutdown...\n"); - while (1); + while (1); } /*@}*/ diff --git a/libcpu/arm/s3c44b0/interrupt.c b/libcpu/arm/s3c44b0/interrupt.c index 6b3eed4a39..5464011dd2 100644 --- a/libcpu/arm/s3c44b0/interrupt.c +++ b/libcpu/arm/s3c44b0/interrupt.c @@ -1,19 +1,19 @@ /* - * Copyright (c) 2006-2018, RT-Thread Development Team + * Copyright (c) 2006-2021, RT-Thread Development Team * * SPDX-License-Identifier: Apache-2.0 * * Change Logs: * Date Author Notes * 2006-09-06 XuXinming first version - * 2006-09-15 Bernard add interrupt bank 0..3 for more effective + * 2006-09-15 Bernard add interrupt bank 0..3 for more effective * in irq trap */ #include <rtthread.h> #include "s3c44b0.h" -#define MAX_HANDLERS 26 +#define MAX_HANDLERS 26 extern rt_uint32_t rt_interrupt_nest; @@ -34,7 +34,7 @@ unsigned char interrupt_bank3[256]; void rt_hw_interrupt_handle(int vector) { - rt_kprintf("Unhandled interrupt %d occured!!!\n", vector); + rt_kprintf("Unhandled interrupt %d occured!!!\n", vector); } /** @@ -42,70 +42,70 @@ void rt_hw_interrupt_handle(int vector) */ void rt_hw_interrupt_init() { - register int i; + register int i; - /* all interrupt disabled include global bit */ - INTMSK = 0x07ffffff; - - /* clear pending register */ - I_ISPC = 0x03ffffff; - - /* non-vector mode IRQ enable */ - INTCON = 0x5; - - /* all IRQ mode */ - INTMOD = 0x0; + /* all interrupt disabled include global bit */ + INTMSK = 0x07ffffff; - /* init exceptions table */ - for(i=0; i<MAX_HANDLERS; i++) - { - isr_table[i] = rt_hw_interrupt_handle; - } + /* clear pending register */ + I_ISPC = 0x03ffffff; - for ( i = 0; i < 256; i++) - { - interrupt_bank0[i] = 0; - interrupt_bank1[i] = 0; - interrupt_bank2[i] = 0; - interrupt_bank3[i] = 0; - } + /* non-vector mode IRQ enable */ + INTCON = 0x5; - /* setup interrupt bank table */ - interrupt_bank0[1] = 0; - interrupt_bank0[2] = 1; - interrupt_bank0[4] = 2; - interrupt_bank0[8] = 3; - interrupt_bank0[16] = 4; - interrupt_bank0[32] = 5; - interrupt_bank0[64] = 6; - interrupt_bank0[128]= 7; + /* all IRQ mode */ + INTMOD = 0x0; - interrupt_bank1[1] = 8; - interrupt_bank1[2] = 9; - interrupt_bank1[4] = 10; - interrupt_bank1[8] = 11; - interrupt_bank1[16] = 12; - interrupt_bank1[32] = 13; - interrupt_bank1[64] = 14; - interrupt_bank1[128]= 15; + /* init exceptions table */ + for(i=0; i<MAX_HANDLERS; i++) + { + isr_table[i] = rt_hw_interrupt_handle; + } - interrupt_bank2[1] = 16; - interrupt_bank2[2] = 17; - interrupt_bank2[4] = 18; - interrupt_bank2[8] = 19; - interrupt_bank2[16] = 20; - interrupt_bank2[32] = 21; - interrupt_bank2[64] = 22; - interrupt_bank2[128]= 23; + for ( i = 0; i < 256; i++) + { + interrupt_bank0[i] = 0; + interrupt_bank1[i] = 0; + interrupt_bank2[i] = 0; + interrupt_bank3[i] = 0; + } - interrupt_bank3[1] = 24; - interrupt_bank3[2] = 25; + /* setup interrupt bank table */ + interrupt_bank0[1] = 0; + interrupt_bank0[2] = 1; + interrupt_bank0[4] = 2; + interrupt_bank0[8] = 3; + interrupt_bank0[16] = 4; + interrupt_bank0[32] = 5; + interrupt_bank0[64] = 6; + interrupt_bank0[128]= 7; - /* init interrupt nest, and context in thread sp */ - rt_interrupt_nest = 0; - rt_interrupt_from_thread = 0; - rt_interrupt_to_thread = 0; - rt_thread_switch_interrupt_flag = 0; + interrupt_bank1[1] = 8; + interrupt_bank1[2] = 9; + interrupt_bank1[4] = 10; + interrupt_bank1[8] = 11; + interrupt_bank1[16] = 12; + interrupt_bank1[32] = 13; + interrupt_bank1[64] = 14; + interrupt_bank1[128]= 15; + + interrupt_bank2[1] = 16; + interrupt_bank2[2] = 17; + interrupt_bank2[4] = 18; + interrupt_bank2[8] = 19; + interrupt_bank2[16] = 20; + interrupt_bank2[32] = 21; + interrupt_bank2[64] = 22; + interrupt_bank2[128]= 23; + + interrupt_bank3[1] = 24; + interrupt_bank3[2] = 25; + + /* init interrupt nest, and context in thread sp */ + rt_interrupt_nest = 0; + rt_interrupt_from_thread = 0; + rt_interrupt_to_thread = 0; + rt_thread_switch_interrupt_flag = 0; } /** @@ -114,7 +114,7 @@ void rt_hw_interrupt_init() */ void rt_hw_interrupt_mask(int vector) { - INTMSK |= 1 << vector; + INTMSK |= 1 << vector; } /** @@ -123,7 +123,7 @@ void rt_hw_interrupt_mask(int vector) */ void rt_hw_interrupt_umask(int vector) { - INTMSK &= ~(1 << vector); + INTMSK &= ~(1 << vector); } /** @@ -134,11 +134,11 @@ void rt_hw_interrupt_umask(int vector) */ void rt_hw_interrupt_install(int vector, rt_isr_handler_t new_handler, rt_isr_handler_t *old_handler) { - if(vector < MAX_HANDLERS) - { - if (old_handler != RT_NULL) *old_handler = isr_table[vector]; - if (new_handler != RT_NULL) isr_table[vector] = new_handler; - } + if(vector < MAX_HANDLERS) + { + if (old_handler != RT_NULL) *old_handler = isr_table[vector]; + if (new_handler != RT_NULL) isr_table[vector] = new_handler; + } } /*@}*/ diff --git a/libcpu/arm/s3c44b0/s3c44b0.h b/libcpu/arm/s3c44b0/s3c44b0.h index 7b854b718a..a40946b573 100644 --- a/libcpu/arm/s3c44b0/s3c44b0.h +++ b/libcpu/arm/s3c44b0/s3c44b0.h @@ -1,5 +1,5 @@ /* - * Copyright (c) 2006-2018, RT-Thread Development Team + * Copyright (c) 2006-2021, RT-Thread Development Team * * SPDX-License-Identifier: Apache-2.0 * @@ -22,315 +22,315 @@ extern "C" { /*@{*/ /*------------------------------------------------------------------------ - * ASIC Address Definition + * ASIC Address Definition *----------------------------------------------------------------------*/ -#define S3C_REG *(volatile unsigned int *) -#define S3C_REGW *(volatile unsigned short *) -#define S3C_REGB *(volatile unsigned char *) +#define S3C_REG *(volatile unsigned int *) +#define S3C_REGW *(volatile unsigned short *) +#define S3C_REGB *(volatile unsigned char *) /* System */ -#define SYSCFG (S3C_REG(0x1c00000)) +#define SYSCFG (S3C_REG(0x1c00000)) /* Cache */ -#define NCACHBE0 (S3C_REG(0x1c00004)) -#define NCACHBE1 (S3C_REG(0x1c00008)) +#define NCACHBE0 (S3C_REG(0x1c00004)) +#define NCACHBE1 (S3C_REG(0x1c00008)) /* Bus control */ -#define SBUSCON (S3C_REG(0x1c40000)) +#define SBUSCON (S3C_REG(0x1c40000)) /* Memory control */ -#define BWSCON (S3C_REG(0x1c80000)) -#define BANKCON0 (S3C_REG(0x1c80004)) -#define BANKCON1 (S3C_REG(0x1c80008)) -#define BANKCON2 (S3C_REG(0x1c8000c)) -#define BANKCON3 (S3C_REG(0x1c80010)) -#define BANKCON4 (S3C_REG(0x1c80014)) -#define BANKCON5 (S3C_REG(0x1c80018)) -#define BANKCON6 (S3C_REG(0x1c8001c)) -#define BANKCON7 (S3C_REG(0x1c80020)) -#define REFRESH (S3C_REG(0x1c80024)) -#define BANKSIZE (S3C_REG(0x1c80028)) -#define MRSRB6 (S3C_REG(0x1c8002c)) -#define MRSRB7 (S3C_REG(0x1c80030)) +#define BWSCON (S3C_REG(0x1c80000)) +#define BANKCON0 (S3C_REG(0x1c80004)) +#define BANKCON1 (S3C_REG(0x1c80008)) +#define BANKCON2 (S3C_REG(0x1c8000c)) +#define BANKCON3 (S3C_REG(0x1c80010)) +#define BANKCON4 (S3C_REG(0x1c80014)) +#define BANKCON5 (S3C_REG(0x1c80018)) +#define BANKCON6 (S3C_REG(0x1c8001c)) +#define BANKCON7 (S3C_REG(0x1c80020)) +#define REFRESH (S3C_REG(0x1c80024)) +#define BANKSIZE (S3C_REG(0x1c80028)) +#define MRSRB6 (S3C_REG(0x1c8002c)) +#define MRSRB7 (S3C_REG(0x1c80030)) /* UART */ -#define ULCON0 (S3C_REG(0x1d00000)) -#define ULCON1 (S3C_REG(0x1d04000)) -#define UCON0 (S3C_REG(0x1d00004)) -#define UCON1 (S3C_REG(0x1d04004)) -#define UFCON0 (S3C_REG(0x1d00008)) -#define UFCON1 (S3C_REG(0x1d04008)) -#define UMCON0 (S3C_REG(0x1d0000c)) -#define UMCON1 (S3C_REG(0x1d0400c)) -#define UTRSTAT0 (S3C_REG(0x1d00010)) -#define UTRSTAT1 (S3C_REG(0x1d04010)) -#define UERSTAT0 (S3C_REG(0x1d00014)) -#define UERSTAT1 (S3C_REG(0x1d04014)) -#define UFSTAT0 (S3C_REG(0x1d00018)) -#define UFSTAT1 (S3C_REG(0x1d04018)) -#define UMSTAT0 (S3C_REG(0x1d0001c)) -#define UMSTAT1 (S3C_REG(0x1d0401c)) -#define UBRDIV0 (S3C_REG(0x1d00028)) -#define UBRDIV1 (S3C_REG(0x1d04028)) +#define ULCON0 (S3C_REG(0x1d00000)) +#define ULCON1 (S3C_REG(0x1d04000)) +#define UCON0 (S3C_REG(0x1d00004)) +#define UCON1 (S3C_REG(0x1d04004)) +#define UFCON0 (S3C_REG(0x1d00008)) +#define UFCON1 (S3C_REG(0x1d04008)) +#define UMCON0 (S3C_REG(0x1d0000c)) +#define UMCON1 (S3C_REG(0x1d0400c)) +#define UTRSTAT0 (S3C_REG(0x1d00010)) +#define UTRSTAT1 (S3C_REG(0x1d04010)) +#define UERSTAT0 (S3C_REG(0x1d00014)) +#define UERSTAT1 (S3C_REG(0x1d04014)) +#define UFSTAT0 (S3C_REG(0x1d00018)) +#define UFSTAT1 (S3C_REG(0x1d04018)) +#define UMSTAT0 (S3C_REG(0x1d0001c)) +#define UMSTAT1 (S3C_REG(0x1d0401c)) +#define UBRDIV0 (S3C_REG(0x1d00028)) +#define UBRDIV1 (S3C_REG(0x1d04028)) -#define UTXH0 (S3C_REGB(0x1d00020)) -#define UTXH1 (S3C_REGB(0x1d04020)) -#define URXH0 (S3C_REGB(0x1d00024)) -#define URXH1 (S3C_REGB(0x1d04024)) +#define UTXH0 (S3C_REGB(0x1d00020)) +#define UTXH1 (S3C_REGB(0x1d04020)) +#define URXH0 (S3C_REGB(0x1d00024)) +#define URXH1 (S3C_REGB(0x1d04024)) /* SIO */ -#define SIOCON (S3C_REG(0x1d14000)) -#define SIODAT (S3C_REG(0x1d14004)) -#define SBRDR (S3C_REG(0x1d14008)) -#define IVTCNT (S3C_REG(0x1d1400c)) -#define DCNTZ (S3C_REG(0x1d14010)) +#define SIOCON (S3C_REG(0x1d14000)) +#define SIODAT (S3C_REG(0x1d14004)) +#define SBRDR (S3C_REG(0x1d14008)) +#define IVTCNT (S3C_REG(0x1d1400c)) +#define DCNTZ (S3C_REG(0x1d14010)) /* IIS */ -#define IISCON (S3C_REG(0x1d18000)) -#define IISMOD (S3C_REG(0x1d18004)) -#define IISPSR (S3C_REG(0x1d18008)) -#define IISFCON (S3C_REG(0x1d1800c)) +#define IISCON (S3C_REG(0x1d18000)) +#define IISMOD (S3C_REG(0x1d18004)) +#define IISPSR (S3C_REG(0x1d18008)) +#define IISFCON (S3C_REG(0x1d1800c)) -#define IISFIF (S3C_REQW(0x1d18010)) +#define IISFIF (S3C_REQW(0x1d18010)) /* I/O Port */ -#define PCONA (S3C_REG(0x1d20000)) -#define PDATA (S3C_REG(0x1d20004)) +#define PCONA (S3C_REG(0x1d20000)) +#define PDATA (S3C_REG(0x1d20004)) -#define PCONB (S3C_REG(0x1d20008)) -#define PDATB (S3C_REG(0x1d2000c)) +#define PCONB (S3C_REG(0x1d20008)) +#define PDATB (S3C_REG(0x1d2000c)) -#define PCONC (S3C_REG(0x1d20010)) -#define PDATC (S3C_REG(0x1d20014)) -#define PUPC (S3C_REG(0x1d20018)) +#define PCONC (S3C_REG(0x1d20010)) +#define PDATC (S3C_REG(0x1d20014)) +#define PUPC (S3C_REG(0x1d20018)) -#define PCOND (S3C_REG(0x1d2001c)) -#define PDATD (S3C_REG(0x1d20020)) -#define PUPD (S3C_REG(0x1d20024)) +#define PCOND (S3C_REG(0x1d2001c)) +#define PDATD (S3C_REG(0x1d20020)) +#define PUPD (S3C_REG(0x1d20024)) -#define PCONE (S3C_REG(0x1d20028)) -#define PDATE (S3C_REG(0x1d2002c)) -#define PUPE (S3C_REG(0x1d20030)) +#define PCONE (S3C_REG(0x1d20028)) +#define PDATE (S3C_REG(0x1d2002c)) +#define PUPE (S3C_REG(0x1d20030)) -#define PCONF (S3C_REG(0x1d20034)) -#define PDATF (S3C_REG(0x1d20038)) -#define PUPF (S3C_REG(0x1d2003c)) +#define PCONF (S3C_REG(0x1d20034)) +#define PDATF (S3C_REG(0x1d20038)) +#define PUPF (S3C_REG(0x1d2003c)) -#define PCONG (S3C_REG(0x1d20040)) -#define PDATG (S3C_REG(0x1d20044)) -#define PUPG (S3C_REG(0x1d20048)) +#define PCONG (S3C_REG(0x1d20040)) +#define PDATG (S3C_REG(0x1d20044)) +#define PUPG (S3C_REG(0x1d20048)) -#define SPUCR (S3C_REG(0x1d2004c)) -#define EXTINT (S3C_REG(0x1d20050)) -#define EXTINTPND (S3C_REG(0x1d20054)) +#define SPUCR (S3C_REG(0x1d2004c)) +#define EXTINT (S3C_REG(0x1d20050)) +#define EXTINTPND (S3C_REG(0x1d20054)) /* Watchdog */ -#define WTCON (S3C_REG(0x1d30000)) -#define WTDAT (S3C_REG(0x1d30004)) -#define WTCNT (S3C_REG(0x1d30008)) +#define WTCON (S3C_REG(0x1d30000)) +#define WTDAT (S3C_REG(0x1d30004)) +#define WTCNT (S3C_REG(0x1d30008)) /* ADC */ -#define ADCCON (S3C_REG(0x1d40000)) -#define ADCPSR (S3C_REG(0x1d40004)) -#define ADCDAT (S3C_REG(0x1d40008)) +#define ADCCON (S3C_REG(0x1d40000)) +#define ADCPSR (S3C_REG(0x1d40004)) +#define ADCDAT (S3C_REG(0x1d40008)) /* Timer */ -#define TCFG0 (S3C_REG(0x1d50000)) -#define TCFG1 (S3C_REG(0x1d50004)) -#define TCON (S3C_REG(0x1d50008)) +#define TCFG0 (S3C_REG(0x1d50000)) +#define TCFG1 (S3C_REG(0x1d50004)) +#define TCON (S3C_REG(0x1d50008)) -#define TCNTB0 (S3C_REG(0x1d5000c)) -#define TCMPB0 (S3C_REG(0x1d50010)) -#define TCNTO0 (S3C_REG(0x1d50014)) +#define TCNTB0 (S3C_REG(0x1d5000c)) +#define TCMPB0 (S3C_REG(0x1d50010)) +#define TCNTO0 (S3C_REG(0x1d50014)) -#define TCNTB1 (S3C_REG(0x1d50018)) -#define TCMPB1 (S3C_REG(0x1d5001c)) -#define TCNTO1 (S3C_REG(0x1d50020)) +#define TCNTB1 (S3C_REG(0x1d50018)) +#define TCMPB1 (S3C_REG(0x1d5001c)) +#define TCNTO1 (S3C_REG(0x1d50020)) -#define TCNTB2 (S3C_REG(0x1d50024)) -#define TCMPB2 (S3C_REG(0x1d50028)) -#define TCNTO2 (S3C_REG(0x1d5002c)) +#define TCNTB2 (S3C_REG(0x1d50024)) +#define TCMPB2 (S3C_REG(0x1d50028)) +#define TCNTO2 (S3C_REG(0x1d5002c)) -#define TCNTB3 (S3C_REG(0x1d50030)) -#define TCMPB3 (S3C_REG(0x1d50034)) -#define TCNTO3 (S3C_REG(0x1d50038)) +#define TCNTB3 (S3C_REG(0x1d50030)) +#define TCMPB3 (S3C_REG(0x1d50034)) +#define TCNTO3 (S3C_REG(0x1d50038)) -#define TCNTB4 (S3C_REG(0x1d5003c)) -#define TCMPB4 (S3C_REG(0x1d50040)) -#define TCNTO4 (S3C_REG(0x1d50044)) +#define TCNTB4 (S3C_REG(0x1d5003c)) +#define TCMPB4 (S3C_REG(0x1d50040)) +#define TCNTO4 (S3C_REG(0x1d50044)) -#define TCNTB5 (S3C_REG(0x1d50048)) -#define TCNTO5 (S3C_REG(0x1d5004c)) +#define TCNTB5 (S3C_REG(0x1d50048)) +#define TCNTO5 (S3C_REG(0x1d5004c)) /* IIC */ -#define IICCON (S3C_REG(0x1d60000)) -#define IICSTAT (S3C_REG(0x1d60004)) -#define IICADD (S3C_REG(0x1d60008)) -#define IICDS (S3C_REG(0x1d6000c)) +#define IICCON (S3C_REG(0x1d60000)) +#define IICSTAT (S3C_REG(0x1d60004)) +#define IICADD (S3C_REG(0x1d60008)) +#define IICDS (S3C_REG(0x1d6000c)) /* RTC */ -#define RTCCON (S3C_REGB(0x1d70040) -#define RTCALM (S3C_REGB(0x1d70050) -#define ALMSEC (S3C_REGB(0x1d70054) -#define ALMMIN (S3C_REGB(0x1d70058) -#define ALMHOUR (S3C_REGB(0x1d7005c) -#define ALMDAY (S3C_REGB(0x1d70060) -#define ALMMON (S3C_REGB(0x1d70064) -#define ALMYEAR (S3C_REGB(0x1d70068) -#define RTCRST (S3C_REGB(0x1d7006c) -#define BCDSEC (S3C_REGB(0x1d70070) -#define BCDMIN (S3C_REGB(0x1d70074) -#define BCDHOUR (S3C_REGB(0x1d70078) -#define BCDDAY (S3C_REGB(0x1d7007c) -#define BCDDATE (S3C_REGB(0x1d70080) -#define BCDMON (S3C_REGB(0x1d70084) -#define BCDYEAR (S3C_REGB(0x1d70088) -#define TICINT (S3C_REGB(0x1d7008c) +#define RTCCON (S3C_REGB(0x1d70040) +#define RTCALM (S3C_REGB(0x1d70050) +#define ALMSEC (S3C_REGB(0x1d70054) +#define ALMMIN (S3C_REGB(0x1d70058) +#define ALMHOUR (S3C_REGB(0x1d7005c) +#define ALMDAY (S3C_REGB(0x1d70060) +#define ALMMON (S3C_REGB(0x1d70064) +#define ALMYEAR (S3C_REGB(0x1d70068) +#define RTCRST (S3C_REGB(0x1d7006c) +#define BCDSEC (S3C_REGB(0x1d70070) +#define BCDMIN (S3C_REGB(0x1d70074) +#define BCDHOUR (S3C_REGB(0x1d70078) +#define BCDDAY (S3C_REGB(0x1d7007c) +#define BCDDATE (S3C_REGB(0x1d70080) +#define BCDMON (S3C_REGB(0x1d70084) +#define BCDYEAR (S3C_REGB(0x1d70088) +#define TICINT (S3C_REGB(0x1d7008c) /* Clock & Power management */ -#define PLLCON (S3C_REG(0x1d80000)) -#define CLKCON (S3C_REG(0x1d80004)) -#define CLKSLOW (S3C_REG(0x1d80008)) -#define LOCKTIME (S3C_REG(0x1d8000c)) +#define PLLCON (S3C_REG(0x1d80000)) +#define CLKCON (S3C_REG(0x1d80004)) +#define CLKSLOW (S3C_REG(0x1d80008)) +#define LOCKTIME (S3C_REG(0x1d8000c)) /* Interrupt */ -#define INTCON (S3C_REG(0x1e00000)) -#define INTPND (S3C_REG(0x1e00004)) -#define INTMOD (S3C_REG(0x1e00008)) -#define INTMSK (S3C_REG(0x1e0000c)) +#define INTCON (S3C_REG(0x1e00000)) +#define INTPND (S3C_REG(0x1e00004)) +#define INTMOD (S3C_REG(0x1e00008)) +#define INTMSK (S3C_REG(0x1e0000c)) -#define I_PSLV (S3C_REG(0x1e00010)) -#define I_PMST (S3C_REG(0x1e00014)) -#define I_CSLV (S3C_REG(0x1e00018)) -#define I_CMST (S3C_REG(0x1e0001c)) -#define I_ISPR (S3C_REG(0x1e00020)) -#define I_ISPC (S3C_REG(0x1e00024)) +#define I_PSLV (S3C_REG(0x1e00010)) +#define I_PMST (S3C_REG(0x1e00014)) +#define I_CSLV (S3C_REG(0x1e00018)) +#define I_CMST (S3C_REG(0x1e0001c)) +#define I_ISPR (S3C_REG(0x1e00020)) +#define I_ISPC (S3C_REG(0x1e00024)) -#define F_ISPR (S3C_REG(0x1e00038)) -#define F_ISPC (S3C_REG(0x1e0003c)) +#define F_ISPR (S3C_REG(0x1e00038)) +#define F_ISPC (S3C_REG(0x1e0003c)) /********************************/ /* LCD Controller Registers */ /********************************/ -#define LCDCON1 (S3C_REG(0x300000)) -#define LCDCON2 (S3C_REG(0x300004)) -#define LCDSADDR1 (S3C_REG(0x300008)) -#define LCDSADDR2 (S3C_REG(0x30000c)) -#define LCDSADDR3 (S3C_REG(0x300010)) -#define REDLUT (S3C_REG(0x300014)) -#define GREENLUT (S3C_REG(0x300018)) -#define BLUELUT (S3C_REG(0x30001c)) -#define DP1_2 (S3C_REG(0x300020)) -#define DP4_7 (S3C_REG(0x300024)) -#define DP3_5 (S3C_REG(0x300028)) -#define DP2_3 (S3C_REG(0x30002c)) -#define DP5_7 (S3C_REG(0x300030)) -#define DP3_4 (S3C_REG(0x300034)) -#define DP4_5 (S3C_REG(0x300038)) -#define DP6_7 (S3C_REG(0x30003c)) -#define LCDCON3 (S3C_REG(0x300040)) -#define DITHMODE (S3C_REG(0x300044)) +#define LCDCON1 (S3C_REG(0x300000)) +#define LCDCON2 (S3C_REG(0x300004)) +#define LCDSADDR1 (S3C_REG(0x300008)) +#define LCDSADDR2 (S3C_REG(0x30000c)) +#define LCDSADDR3 (S3C_REG(0x300010)) +#define REDLUT (S3C_REG(0x300014)) +#define GREENLUT (S3C_REG(0x300018)) +#define BLUELUT (S3C_REG(0x30001c)) +#define DP1_2 (S3C_REG(0x300020)) +#define DP4_7 (S3C_REG(0x300024)) +#define DP3_5 (S3C_REG(0x300028)) +#define DP2_3 (S3C_REG(0x30002c)) +#define DP5_7 (S3C_REG(0x300030)) +#define DP3_4 (S3C_REG(0x300034)) +#define DP4_5 (S3C_REG(0x300038)) +#define DP6_7 (S3C_REG(0x30003c)) +#define LCDCON3 (S3C_REG(0x300040)) +#define DITHMODE (S3C_REG(0x300044)) /* ZDMA0 */ -#define ZDCON0 (S3C_REG(0x1e80000)) -#define ZDISRC0 (S3C_REG(0x1e80004)) -#define ZDIDES0 (S3C_REG(0x1e80008)) -#define ZDICNT0 (S3C_REG(0x1e8000c)) -#define ZDCSRC0 (S3C_REG(0x1e80010)) -#define ZDCDES0 (S3C_REG(0x1e80014)) -#define ZDCCNT0 (S3C_REG(0x1e80018)) +#define ZDCON0 (S3C_REG(0x1e80000)) +#define ZDISRC0 (S3C_REG(0x1e80004)) +#define ZDIDES0 (S3C_REG(0x1e80008)) +#define ZDICNT0 (S3C_REG(0x1e8000c)) +#define ZDCSRC0 (S3C_REG(0x1e80010)) +#define ZDCDES0 (S3C_REG(0x1e80014)) +#define ZDCCNT0 (S3C_REG(0x1e80018)) /* ZDMA1 */ -#define ZDCON1 (S3C_REG(0x1e80020)) -#define ZDISRC1 (S3C_REG(0x1e80024)) -#define ZDIDES1 (S3C_REG(0x1e80028)) -#define ZDICNT1 (S3C_REG(0x1e8002c)) -#define ZDCSRC1 (S3C_REG(0x1e80030)) -#define ZDCDES1 (S3C_REG(0x1e80034)) -#define ZDCCNT1 (S3C_REG(0x1e80038)) +#define ZDCON1 (S3C_REG(0x1e80020)) +#define ZDISRC1 (S3C_REG(0x1e80024)) +#define ZDIDES1 (S3C_REG(0x1e80028)) +#define ZDICNT1 (S3C_REG(0x1e8002c)) +#define ZDCSRC1 (S3C_REG(0x1e80030)) +#define ZDCDES1 (S3C_REG(0x1e80034)) +#define ZDCCNT1 (S3C_REG(0x1e80038)) /* BDMA0 */ -#define BDCON0 (S3C_REG(0x1f80000)) -#define BDISRC0 (S3C_REG(0x1f80004)) -#define BDIDES0 (S3C_REG(0x1f80008)) -#define BDICNT0 (S3C_REG(0x1f8000c)) -#define BDCSRC0 (S3C_REG(0x1f80010)) -#define BDCDES0 (S3C_REG(0x1f80014)) -#define BDCCNT0 (S3C_REG(0x1f80018)) +#define BDCON0 (S3C_REG(0x1f80000)) +#define BDISRC0 (S3C_REG(0x1f80004)) +#define BDIDES0 (S3C_REG(0x1f80008)) +#define BDICNT0 (S3C_REG(0x1f8000c)) +#define BDCSRC0 (S3C_REG(0x1f80010)) +#define BDCDES0 (S3C_REG(0x1f80014)) +#define BDCCNT0 (S3C_REG(0x1f80018)) /* BDMA1 */ -#define BDCON1 (S3C_REG(0x1f80020)) -#define BDISRC1 (S3C_REG(0x1f80024)) -#define BDIDES1 (S3C_REG(0x1f80028)) -#define BDICNT1 (S3C_REG(0x1f8002c)) -#define BDCSRC1 (S3C_REG(0x1f80030)) -#define BDCDES1 (S3C_REG(0x1f80034)) -#define BDCCNT1 (S3C_REG(0x1f80038)) +#define BDCON1 (S3C_REG(0x1f80020)) +#define BDISRC1 (S3C_REG(0x1f80024)) +#define BDIDES1 (S3C_REG(0x1f80028)) +#define BDICNT1 (S3C_REG(0x1f8002c)) +#define BDCSRC1 (S3C_REG(0x1f80030)) +#define BDCDES1 (S3C_REG(0x1f80034)) +#define BDCCNT1 (S3C_REG(0x1f80038)) /*****************************/ /* CPU Mode */ /*****************************/ -#define USERMODE 0x10 /* User Mode(USR) */ -#define FIQMODE 0x11 /* Fast Interrupt Mode (FIQ) */ -#define IRQMODE 0x12 /* Interrupt Mode (IRQ) */ -#define SVCMODE 0x13 /* Supervisor Mode (SVC) */ -#define ABORTMODE 0x17 /* Abort Mode(ABT) */ -#define UNDEFMODE 0x1b /* Undefine Mode(UDF) */ -#define MODEMASK 0x1f /* Processor Mode Mask */ -#define NOINT 0xc0 +#define USERMODE 0x10 /* User Mode(USR) */ +#define FIQMODE 0x11 /* Fast Interrupt Mode (FIQ) */ +#define IRQMODE 0x12 /* Interrupt Mode (IRQ) */ +#define SVCMODE 0x13 /* Supervisor Mode (SVC) */ +#define ABORTMODE 0x17 /* Abort Mode(ABT) */ +#define UNDEFMODE 0x1b /* Undefine Mode(UDF) */ +#define MODEMASK 0x1f /* Processor Mode Mask */ +#define NOINT 0xc0 /*****************************/ /* INT Define */ /*****************************/ -#define INT_ADC 0x00 -#define INT_RTC 0x01 -#define INT_UTXD1 0x02 -#define INT_UTXD0 0x03 -#define INT_SIO 0x04 -#define INT_IIC 0x05 -#define INT_URXD1 0x06 -#define INT_URXD0 0x07 -#define INT_TIMER5 0x08 -#define INT_TIMER4 0x09 -#define INT_TIMER3 0x0A -#define INT_TIMER2 0x0B -#define INT_TIMER1 0x0C -#define INT_TIMER0 0x0D -#define INT_UERR01 0x0E -#define INT_WDT 0x1F -#define INT_BDMA1 0x10 -#define INT_BDMA0 0x11 -#define INT_ZDMA1 0x12 -#define INT_ZDMA0 0x13 -#define INT_TICK 0x14 -#define INT_EINT4567 0x15 -#define INT_EINT3 0x16 -#define INT_EINT2 0x17 -#define INT_EINT1 0x18 -#define INT_EINT0 0x19 +#define INT_ADC 0x00 +#define INT_RTC 0x01 +#define INT_UTXD1 0x02 +#define INT_UTXD0 0x03 +#define INT_SIO 0x04 +#define INT_IIC 0x05 +#define INT_URXD1 0x06 +#define INT_URXD0 0x07 +#define INT_TIMER5 0x08 +#define INT_TIMER4 0x09 +#define INT_TIMER3 0x0A +#define INT_TIMER2 0x0B +#define INT_TIMER1 0x0C +#define INT_TIMER0 0x0D +#define INT_UERR01 0x0E +#define INT_WDT 0x1F +#define INT_BDMA1 0x10 +#define INT_BDMA0 0x11 +#define INT_ZDMA1 0x12 +#define INT_ZDMA0 0x13 +#define INT_TICK 0x14 +#define INT_EINT4567 0x15 +#define INT_EINT3 0x16 +#define INT_EINT2 0x17 +#define INT_EINT1 0x18 +#define INT_EINT0 0x19 -#define INT_GLOBAL 26 +#define INT_GLOBAL 26 struct rt_hw_register { - unsigned long r0; - unsigned long r1; - unsigned long r2; - unsigned long r3; - unsigned long r4; - unsigned long r5; - unsigned long r6; - unsigned long r7; - unsigned long r8; - unsigned long r9; - unsigned long r10; - unsigned long fp; - unsigned long ip; - unsigned long sp; - unsigned long lr; - unsigned long pc; - unsigned long cpsr; - unsigned long ORIG_r0; + unsigned long r0; + unsigned long r1; + unsigned long r2; + unsigned long r3; + unsigned long r4; + unsigned long r5; + unsigned long r6; + unsigned long r7; + unsigned long r8; + unsigned long r9; + unsigned long r10; + unsigned long fp; + unsigned long ip; + unsigned long sp; + unsigned long lr; + unsigned long pc; + unsigned long cpsr; + unsigned long ORIG_r0; }; /*@}*/ diff --git a/libcpu/arm/s3c44b0/serial.c b/libcpu/arm/s3c44b0/serial.c index 6af515b027..95f8cb3487 100644 --- a/libcpu/arm/s3c44b0/serial.c +++ b/libcpu/arm/s3c44b0/serial.c @@ -1,5 +1,5 @@ /* - * Copyright (c) 2006-2018, RT-Thread Development Team + * Copyright (c) 2006-2021, RT-Thread Development Team * * SPDX-License-Identifier: Apache-2.0 * @@ -18,21 +18,21 @@ void rt_serial_init(void); void rt_console_puts(const char* str); void rt_serial_putc(const char c); -#define USTAT_RCV_READY 0x01 /* receive data ready */ -#define USTAT_TXB_EMPTY 0x02 /* tx buffer empty */ +#define USTAT_RCV_READY 0x01 /* receive data ready */ +#define USTAT_TXB_EMPTY 0x02 /* tx buffer empty */ rt_inline void serial_flush_input(void) { - volatile unsigned int tmp; + volatile unsigned int tmp; - /* keep on reading as long as the receiver is not empty */ - while(UTRSTAT0 & USTAT_RCV_READY) tmp = URXH0; + /* keep on reading as long as the receiver is not empty */ + while(UTRSTAT0 & USTAT_RCV_READY) tmp = URXH0; } rt_inline void serial_flush_output(void) { - /* wait until the transmitter is no longer busy */ - while(!(UTRSTAT0 & USTAT_TXB_EMPTY)) ; + /* wait until the transmitter is no longer busy */ + while(!(UTRSTAT0 & USTAT_TXB_EMPTY)) ; } /** @@ -48,10 +48,10 @@ rt_inline void serial_flush_output(void) */ void rt_console_puts(const char* str) { - while (*str) - { - rt_serial_putc (*str++); - } + while (*str) + { + rt_serial_putc (*str++); + } } /** @@ -59,25 +59,25 @@ void rt_console_puts(const char* str) */ void rt_serial_init() { - rt_uint32_t divisor = 0; + rt_uint32_t divisor = 0; - divisor = 0x20; + divisor = 0x20; - serial_flush_output(); - serial_flush_input(); + serial_flush_output(); + serial_flush_input(); - /* UART interrupt off */ - UCON0 = 0; - /* FIFO disable */ - UFCON0 =0x0; - UMCON0 =0x0; - /* set baudrate */ - UBRDIV0 = divisor; + /* UART interrupt off */ + UCON0 = 0; + /* FIFO disable */ + UFCON0 =0x0; + UMCON0 =0x0; + /* set baudrate */ + UBRDIV0 = divisor; - /* word length=8bit, stop bit = 1, no parity, use external clock */ - ULCON0 = 0x03|0x00|0x00; + /* word length=8bit, stop bit = 1, no parity, use external clock */ + ULCON0 = 0x03|0x00|0x00; - UCON0 = 0x5; + UCON0 = 0x5; } /** @@ -87,9 +87,9 @@ void rt_serial_init() */ char rt_serial_getc() { - while ((UTRSTAT0 & USTAT_RCV_READY) == 0); + while ((UTRSTAT0 & USTAT_RCV_READY) == 0); - return URXH0; + return URXH0; } /** @@ -99,16 +99,16 @@ char rt_serial_getc() */ void rt_serial_putc(const char c) { - /* - to be polite with serial console add a line feed - to the carriage return character - */ - if (c=='\n')rt_serial_putc('\r'); + /* + to be polite with serial console add a line feed + to the carriage return character + */ + if (c=='\n')rt_serial_putc('\r'); - /* wait for room in the transmit FIFO */ - while(!(UTRSTAT0 & USTAT_TXB_EMPTY)); + /* wait for room in the transmit FIFO */ + while(!(UTRSTAT0 & USTAT_TXB_EMPTY)); - UTXH0 = (rt_uint8_t)c; + UTXH0 = (rt_uint8_t)c; } /*@}*/ diff --git a/libcpu/arm/s3c44b0/stack.c b/libcpu/arm/s3c44b0/stack.c index 12da611d5a..4ed4693994 100644 --- a/libcpu/arm/s3c44b0/stack.c +++ b/libcpu/arm/s3c44b0/stack.c @@ -1,5 +1,5 @@ /* - * Copyright (c) 2006-2018, RT-Thread Development Team + * Copyright (c) 2006-2021, RT-Thread Development Team * * SPDX-License-Identifier: Apache-2.0 * diff --git a/libcpu/arm/s3c44b0/trap.c b/libcpu/arm/s3c44b0/trap.c index 3b93d5457e..106a990262 100644 --- a/libcpu/arm/s3c44b0/trap.c +++ b/libcpu/arm/s3c44b0/trap.c @@ -1,5 +1,5 @@ /* - * Copyright (c) 2006-2018, RT-Thread Development Team + * Copyright (c) 2006-2021, RT-Thread Development Team * * SPDX-License-Identifier: Apache-2.0 * @@ -33,13 +33,13 @@ extern struct rt_thread *rt_current_thread; */ void rt_hw_show_register (struct rt_hw_register *regs) { - rt_kprintf("Execption:\n"); - rt_kprintf("r00:0x%08x r01:0x%08x r02:0x%08x r03:0x%08x\n", regs->r0, regs->r1, regs->r2, regs->r3); - rt_kprintf("r04:0x%08x r05:0x%08x r06:0x%08x r07:0x%08x\n", regs->r4, regs->r5, regs->r6, regs->r7); - rt_kprintf("r08:0x%08x r09:0x%08x r10:0x%08x\n", regs->r8, regs->r9, regs->r10); - rt_kprintf("fp :0x%08x ip :0x%08x\n", regs->fp, regs->ip); - rt_kprintf("sp :0x%08x lr :0x%08x pc :0x%08x\n", regs->sp, regs->lr, regs->pc); - rt_kprintf("cpsr:0x%08x\n", regs->cpsr); + rt_kprintf("Execption:\n"); + rt_kprintf("r00:0x%08x r01:0x%08x r02:0x%08x r03:0x%08x\n", regs->r0, regs->r1, regs->r2, regs->r3); + rt_kprintf("r04:0x%08x r05:0x%08x r06:0x%08x r07:0x%08x\n", regs->r4, regs->r5, regs->r6, regs->r7); + rt_kprintf("r08:0x%08x r09:0x%08x r10:0x%08x\n", regs->r8, regs->r9, regs->r10); + rt_kprintf("fp :0x%08x ip :0x%08x\n", regs->fp, regs->ip); + rt_kprintf("sp :0x%08x lr :0x%08x pc :0x%08x\n", regs->sp, regs->lr, regs->pc); + rt_kprintf("cpsr:0x%08x\n", regs->cpsr); } /** @@ -52,10 +52,10 @@ void rt_hw_show_register (struct rt_hw_register *regs) */ void rt_hw_trap_udef(struct rt_hw_register *regs) { - rt_hw_show_register(regs); + rt_hw_show_register(regs); - rt_kprintf("undefined instruction\n"); - rt_hw_cpu_shutdown(); + rt_kprintf("undefined instruction\n"); + rt_hw_cpu_shutdown(); } /** @@ -84,10 +84,10 @@ void rt_hw_trap_swi(struct rt_hw_register *regs) */ void rt_hw_trap_pabt(struct rt_hw_register *regs) { - rt_hw_show_register(regs); + rt_hw_show_register(regs); - rt_kprintf("prefetch abort\n"); - rt_hw_cpu_shutdown(); + rt_kprintf("prefetch abort\n"); + rt_hw_cpu_shutdown(); } /** @@ -100,10 +100,10 @@ void rt_hw_trap_pabt(struct rt_hw_register *regs) */ void rt_hw_trap_dabt(struct rt_hw_register *regs) { - rt_hw_show_register(regs); + rt_hw_show_register(regs); - rt_kprintf("data abort\n"); - rt_hw_cpu_shutdown(); + rt_kprintf("data abort\n"); + rt_hw_cpu_shutdown(); } /** @@ -123,50 +123,50 @@ void rt_hw_trap_resv(struct rt_hw_register *regs) extern rt_isr_handler_t isr_table[]; void rt_hw_trap_irq() { - register unsigned long ispr, intstat; - register rt_isr_handler_t isr_func; + register unsigned long ispr, intstat; + register rt_isr_handler_t isr_func; #ifdef BSP_INT_DEBUG - rt_kprintf("irq coming, "); + rt_kprintf("irq coming, "); #endif - intstat = I_ISPR & 0x7ffffff; + intstat = I_ISPR & 0x7ffffff; #ifdef BSP_INT_DEBUG - rt_kprintf("I_ISPR: %d\n", intstat); + rt_kprintf("I_ISPR: %d\n", intstat); #endif - ispr = intstat; + ispr = intstat; - /* to find interrupt */ - if ( intstat & 0xff ) /* lowest 8bits */ - { - intstat = interrupt_bank0[intstat & 0xff]; - isr_func = (rt_isr_handler_t)isr_table[ intstat ]; - } - else if ( intstat & 0xff00 ) /* low 8bits */ - { - intstat = interrupt_bank1[(intstat & 0xff00) >> 8]; - isr_func = (rt_isr_handler_t)isr_table[ intstat ]; - } - else if ( intstat & 0xff0000 ) /* high 8bits */ - { - intstat = interrupt_bank2[(intstat & 0xff0000) >> 16]; - isr_func = (rt_isr_handler_t)isr_table[ intstat ]; - } - else if ( intstat & 0xff000000 ) /* highest 8bits */ - { - intstat = interrupt_bank3[(intstat & 0xff000000) >> 24]; - isr_func = (rt_isr_handler_t)isr_table[ intstat ]; - } - else return; + /* to find interrupt */ + if ( intstat & 0xff ) /* lowest 8bits */ + { + intstat = interrupt_bank0[intstat & 0xff]; + isr_func = (rt_isr_handler_t)isr_table[ intstat ]; + } + else if ( intstat & 0xff00 ) /* low 8bits */ + { + intstat = interrupt_bank1[(intstat & 0xff00) >> 8]; + isr_func = (rt_isr_handler_t)isr_table[ intstat ]; + } + else if ( intstat & 0xff0000 ) /* high 8bits */ + { + intstat = interrupt_bank2[(intstat & 0xff0000) >> 16]; + isr_func = (rt_isr_handler_t)isr_table[ intstat ]; + } + else if ( intstat & 0xff000000 ) /* highest 8bits */ + { + intstat = interrupt_bank3[(intstat & 0xff000000) >> 24]; + isr_func = (rt_isr_handler_t)isr_table[ intstat ]; + } + else return; #ifdef BSP_INT_DEBUG - rt_kprintf("irq: %d happen\n", intstat); + rt_kprintf("irq: %d happen\n", intstat); #endif - /* turn to interrupt service routine */ - isr_func(intstat); + /* turn to interrupt service routine */ + isr_func(intstat); - I_ISPC = ispr; /* clear interrupt */ + I_ISPC = ispr; /* clear interrupt */ } void rt_hw_trap_fiq() diff --git a/libcpu/arm/sep4020/clk.c b/libcpu/arm/sep4020/clk.c index da69e25b6d..031d310fcf 100644 --- a/libcpu/arm/sep4020/clk.c +++ b/libcpu/arm/sep4020/clk.c @@ -1,5 +1,5 @@ /* - * Copyright (c) 2006-2018, RT-Thread Development Team + * Copyright (c) 2006-2021, RT-Thread Development Team * * SPDX-License-Identifier: Apache-2.0 * @@ -11,46 +11,46 @@ #include <rtthread.h> #include "sep4020.h" -#define CLK_IN 4000000 /* Fin = 4.00MHz */ -#define SYSCLK 72000000 /* system clock we want */ +#define CLK_IN 4000000 /* Fin = 4.00MHz */ +#define SYSCLK 72000000 /* system clock we want */ -#define CLK_ESRAM 0 -#define CLK_LCDC 1 -#define CLK_PWM 2 -#define CLK_DMAC 3 -#define CLK_EMI 4 -#define CLK_MMCSD 5 -#define CLK_SSI 7 -#define CLK_UART0 8 -#define CLK_UART1 9 -#define CLK_UART2 10 -#define CLK_UART3 11 -#define CLK_USB 12 -#define CLK_MAC 13 -#define CLK_SMC 14 -#define CLK_I2C 15 -#define CLK_GPT 16 +#define CLK_ESRAM 0 +#define CLK_LCDC 1 +#define CLK_PWM 2 +#define CLK_DMAC 3 +#define CLK_EMI 4 +#define CLK_MMCSD 5 +#define CLK_SSI 7 +#define CLK_UART0 8 +#define CLK_UART1 9 +#define CLK_UART2 10 +#define CLK_UART3 11 +#define CLK_USB 12 +#define CLK_MAC 13 +#define CLK_SMC 14 +#define CLK_I2C 15 +#define CLK_GPT 16 static void rt_hw_set_system_clock(void) { - rt_uint8_t pv; + rt_uint8_t pv; - /* pv value*/ - pv = SYSCLK/2/CLK_IN; - /* go to normal mode*/ - *(RP)PMU_PMDR = 0x01; - /* set the clock */ - *(RP)PMU_PMCR = 0x4000 | pv; - /* trige configurate*/ - *(RP)PMU_PMCR = 0xc000 | pv; + /* pv value*/ + pv = SYSCLK/2/CLK_IN; + /* go to normal mode*/ + *(RP)PMU_PMDR = 0x01; + /* set the clock */ + *(RP)PMU_PMCR = 0x4000 | pv; + /* trige configurate*/ + *(RP)PMU_PMCR = 0xc000 | pv; } static void rt_hw_set_usb_clock(void) { - /* set the clock */ - *(RP)PMU_PUCR = 0x000c; - /* trige configurate*/ - *(RP)PMU_PMCR = 0x800c; + /* set the clock */ + *(RP)PMU_PUCR = 0x000c; + /* trige configurate*/ + *(RP)PMU_PMCR = 0x800c; } @@ -59,10 +59,10 @@ static void rt_hw_set_usb_clock(void) */ void rt_hw_clock_init(void) { - /* set system clock */ - rt_hw_set_system_clock(); - /* set usb clock */ - rt_hw_set_usb_clock(); + /* set system clock */ + rt_hw_set_system_clock(); + /* set usb clock */ + rt_hw_set_usb_clock(); } /** @@ -70,22 +70,22 @@ void rt_hw_clock_init(void) */ rt_uint32_t rt_hw_get_clock(void) { - rt_uint32_t val; - rt_uint8_t pv, pd, npd; + rt_uint32_t val; + rt_uint8_t pv, pd, npd; - /* get PMCR value */ - val =*(RP) PMU_PMCR; - /* get NPD */ - npd = (val >> 14) & 0x01; - /* get PD */ - pd = (val >> 10) & 0x0f; - /* get PV */ - pv = val & 0x7f; - /* caculate the system clock */ - if(npd) - val = 2 * CLK_IN * pv; - else - val = CLK_IN * pv / (pd + 1); + /* get PMCR value */ + val =*(RP) PMU_PMCR; + /* get NPD */ + npd = (val >> 14) & 0x01; + /* get PD */ + pd = (val >> 10) & 0x0f; + /* get PV */ + pv = val & 0x7f; + /* caculate the system clock */ + if(npd) + val = 2 * CLK_IN * pv; + else + val = CLK_IN * pv / (pd + 1); return(val); } diff --git a/libcpu/arm/sep4020/cpu.c b/libcpu/arm/sep4020/cpu.c index 92ba2cf86a..256ede56e9 100644 --- a/libcpu/arm/sep4020/cpu.c +++ b/libcpu/arm/sep4020/cpu.c @@ -1,5 +1,5 @@ /* - * Copyright (c) 2006-2018, RT-Thread Development Team + * Copyright (c) 2006-2021, RT-Thread Development Team * * SPDX-License-Identifier: Apache-2.0 * @@ -21,76 +21,76 @@ extern rt_uint32_t rt_hw_interrupt_disable(void); */ /*@{*/ -#define ICACHE_MASK (rt_uint32_t)(1 << 12) -#define DCACHE_MASK (rt_uint32_t)(1 << 2) +#define ICACHE_MASK (rt_uint32_t)(1 << 12) +#define DCACHE_MASK (rt_uint32_t)(1 << 2) #ifdef __GNUC__ rt_inline rt_uint32_t cp15_rd(void) { - rt_uint32_t i; + rt_uint32_t i; - asm ("mrc p15, 0, %0, c1, c0, 0":"=r" (i)); - return i; + asm ("mrc p15, 0, %0, c1, c0, 0":"=r" (i)); + return i; } rt_inline void cache_enable(rt_uint32_t bit) { - __asm__ __volatile__( \ - "mrc p15,0,r0,c1,c0,0\n\t" \ - "orr r0,r0,%0\n\t" \ - "mcr p15,0,r0,c1,c0,0" \ - : \ - :"r" (bit) \ - :"memory"); + __asm__ __volatile__( \ + "mrc p15,0,r0,c1,c0,0\n\t" \ + "orr r0,r0,%0\n\t" \ + "mcr p15,0,r0,c1,c0,0" \ + : \ + :"r" (bit) \ + :"memory"); } rt_inline void cache_disable(rt_uint32_t bit) { - __asm__ __volatile__( \ - "mrc p15,0,r0,c1,c0,0\n\t" \ - "bic r0,r0,%0\n\t" \ - "mcr p15,0,r0,c1,c0,0" \ - : \ - :"r" (bit) \ - :"memory"); + __asm__ __volatile__( \ + "mrc p15,0,r0,c1,c0,0\n\t" \ + "bic r0,r0,%0\n\t" \ + "mcr p15,0,r0,c1,c0,0" \ + : \ + :"r" (bit) \ + :"memory"); } #endif #ifdef __CC_ARM rt_inline rt_uint32_t cp15_rd(void) { - rt_uint32_t i; + rt_uint32_t i; - __asm - { - mrc p15, 0, i, c1, c0, 0 - } + __asm + { + mrc p15, 0, i, c1, c0, 0 + } - return i; + return i; } rt_inline void cache_enable(rt_uint32_t bit) { - rt_uint32_t value; + rt_uint32_t value; - __asm - { - mrc p15, 0, value, c1, c0, 0 - orr value, value, bit - mcr p15, 0, value, c1, c0, 0 - } + __asm + { + mrc p15, 0, value, c1, c0, 0 + orr value, value, bit + mcr p15, 0, value, c1, c0, 0 + } } rt_inline void cache_disable(rt_uint32_t bit) { - rt_uint32_t value; + rt_uint32_t value; - __asm - { - mrc p15, 0, value, c1, c0, 0 - bic value, value, bit - mcr p15, 0, value, c1, c0, 0 - } + __asm + { + mrc p15, 0, value, c1, c0, 0 + bic value, value, bit + mcr p15, 0, value, c1, c0, 0 + } } #endif @@ -100,7 +100,7 @@ rt_inline void cache_disable(rt_uint32_t bit) */ void rt_hw_cpu_icache_enable() { - cache_enable(ICACHE_MASK); + cache_enable(ICACHE_MASK); } /** @@ -109,7 +109,7 @@ void rt_hw_cpu_icache_enable() */ void rt_hw_cpu_icache_disable() { - cache_disable(ICACHE_MASK); + cache_disable(ICACHE_MASK); } /** @@ -118,7 +118,7 @@ void rt_hw_cpu_icache_disable() */ rt_base_t rt_hw_cpu_icache_status() { - return (cp15_rd() & ICACHE_MASK); + return (cp15_rd() & ICACHE_MASK); } /** @@ -127,7 +127,7 @@ rt_base_t rt_hw_cpu_icache_status() */ void rt_hw_cpu_dcache_enable() { - cache_enable(DCACHE_MASK); + cache_enable(DCACHE_MASK); } /** @@ -136,7 +136,7 @@ void rt_hw_cpu_dcache_enable() */ void rt_hw_cpu_dcache_disable() { - cache_disable(DCACHE_MASK); + cache_disable(DCACHE_MASK); } /** @@ -145,7 +145,7 @@ void rt_hw_cpu_dcache_disable() */ rt_base_t rt_hw_cpu_dcache_status() { - return (cp15_rd() & DCACHE_MASK); + return (cp15_rd() & DCACHE_MASK); } /** @@ -155,18 +155,18 @@ rt_base_t rt_hw_cpu_dcache_status() RT_WEAK void rt_hw_cpu_reset() { - /* enable watchdog */ - *(RP)(RTC_CTR) = 0x02; + /* enable watchdog */ + *(RP)(RTC_CTR) = 0x02; - /*Enable watchdog reset*/ - *(RP)(RTC_INT_EN) = 0x20; + /*Enable watchdog reset*/ + *(RP)(RTC_INT_EN) = 0x20; - /* Initialize watchdog timer count register */ - *(RP)(RTC_WD_CNT) = 0x0001; + /* Initialize watchdog timer count register */ + *(RP)(RTC_WD_CNT) = 0x0001; - while(1); /* loop forever and wait for reset to happen */ + while(1); /* loop forever and wait for reset to happen */ - /* NEVER REACHED */ + /* NEVER REACHED */ } /** @@ -175,12 +175,12 @@ RT_WEAK void rt_hw_cpu_reset() */ RT_WEAK void rt_hw_cpu_shutdown() { - rt_uint32_t UNUSED level; - rt_kprintf("shutdown...\n"); + rt_uint32_t UNUSED level; + rt_kprintf("shutdown...\n"); - level = rt_hw_interrupt_disable(); + level = rt_hw_interrupt_disable(); - RT_ASSERT(RT_NULL); + RT_ASSERT(RT_NULL); } /*@}*/ diff --git a/libcpu/arm/sep4020/interrupt.c b/libcpu/arm/sep4020/interrupt.c index ebc9c9625b..24907c139f 100644 --- a/libcpu/arm/sep4020/interrupt.c +++ b/libcpu/arm/sep4020/interrupt.c @@ -1,5 +1,5 @@ /* - * Copyright (c) 2006-2018, RT-Thread Development Team + * Copyright (c) 2006-2021, RT-Thread Development Team * * SPDX-License-Identifier: Apache-2.0 * @@ -13,7 +13,7 @@ #include <rthw.h> #include <sep4020.h> -#define MAX_HANDLERS 32 +#define MAX_HANDLERS 32 extern rt_uint32_t rt_interrupt_nest; @@ -29,7 +29,7 @@ rt_uint32_t rt_thread_switch_interrupt_flag; static void rt_hw_interrupt_handle(int vector, void *param) { - rt_kprintf("Unhandled interrupt %d occured!!!\n", vector); + rt_kprintf("Unhandled interrupt %d occured!!!\n", vector); } /** @@ -45,7 +45,7 @@ void rt_hw_interrupt_init(void) *(RP)(INTC_IMR) = 0xFFFFFFFF; /*enable all the irq*/ - *(RP)(INTC_IER) = 0XFFFFFFFF; + *(RP)(INTC_IER) = 0XFFFFFFFF; /*Dont use any forced irq*/ *(RP)(INTC_IFR) = 0x0; @@ -82,7 +82,7 @@ void rt_hw_interrupt_init(void) */ void rt_hw_interrupt_mask(int vector) { - *(RP)(INTC_IMR) |= 1 << vector; + *(RP)(INTC_IMR) |= 1 << vector; } /** @@ -91,12 +91,12 @@ void rt_hw_interrupt_mask(int vector) */ void rt_hw_interrupt_umask(int vector) { - if(vector == 16) - { - rt_kprintf("Interrupt vec %d is not used!\n", vector); - } - else - *(RP)(INTC_IMR) &= ~(1 << vector); + if(vector == 16) + { + rt_kprintf("Interrupt vec %d is not used!\n", vector); + } + else + *(RP)(INTC_IMR) &= ~(1 << vector); } @@ -118,7 +118,7 @@ rt_isr_handler_t rt_hw_interrupt_install(int vector, rt_isr_handler_t handler, if (handler != RT_NULL) { #ifdef RT_USING_INTERRUPT_INFO - rt_strncpy(isr_table[vector].name, name, RT_NAME_MAX); + rt_strncpy(isr_table[vector].name, name, RT_NAME_MAX); #endif /* RT_USING_INTERRUPT_INFO */ isr_table[vector].handler = handler; isr_table[vector].param = param; diff --git a/libcpu/arm/sep4020/sep4020.h b/libcpu/arm/sep4020/sep4020.h index 4ae09d0275..bb8effbff0 100644 --- a/libcpu/arm/sep4020/sep4020.h +++ b/libcpu/arm/sep4020/sep4020.h @@ -1,5 +1,5 @@ /* - * Copyright (c) 2006-2018, RT-Thread Development Team + * Copyright (c) 2006-2021, RT-Thread Development Team * * SPDX-License-Identifier: Apache-2.0 * @@ -13,13 +13,13 @@ /*Core definations*/ #define SVCMODE -#define Mode_USR 0x10 -#define Mode_FIQ 0x11 -#define Mode_IRQ 0x12 -#define Mode_SVC 0x13 -#define Mode_ABT 0x17 -#define Mode_UND 0x1B -#define Mode_SYS 0x1F +#define Mode_USR 0x10 +#define Mode_FIQ 0x11 +#define Mode_IRQ 0x12 +#define Mode_SVC 0x13 +#define Mode_ABT 0x17 +#define Mode_UND 0x1B +#define Mode_SYS 0x1F @@ -106,7 +106,7 @@ #define RTC_INT_STS (RTC_BASE+0X014) /* 中断状态寄存器 */ #define RTC_SAMP (RTC_BASE+0X018) /* 采样周期寄存器 */ #define RTC_WD_CNT (RTC_BASE+0X01C) /* Watch-Dog计数值寄存器 */ -#define RTC_WD_SEV (RTC_BASE+0X020) /* Watch-Dog服务寄存器 */ +#define RTC_WD_SEV (RTC_BASE+0X020) /* Watch-Dog服务寄存器 */ #define RTC_CONFIG_CHECK (RTC_BASE+0X024) /* 配置时间确认寄存器 (在配置时间之前先写0xaaaaaaaa) */ #define RTC_KEY0 (RTC_BASE+0X02C) /* 密钥寄存器 */ @@ -325,18 +325,18 @@ * SD模块 * 基址: 0x1000B000 */ - -#define SDC_CLOCK_CONTROL (SD_BASE+0x00) /* SDIO时钟控制寄存器 */ -#define SDC_SOFTWARE_RESET (SD_BASE+0X04) /* SDIO软件复位寄存器 */ -#define SDC_ARGUMENT (SD_BASE+0X08) /* SDIO命令参数寄存器 */ -#define SDC_COMMAND (SD_BASE+0X0C) /* SDIO命令控制寄存器 */ + +#define SDC_CLOCK_CONTROL (SD_BASE+0x00) /* SDIO时钟控制寄存器 */ +#define SDC_SOFTWARE_RESET (SD_BASE+0X04) /* SDIO软件复位寄存器 */ +#define SDC_ARGUMENT (SD_BASE+0X08) /* SDIO命令参数寄存器 */ +#define SDC_COMMAND (SD_BASE+0X0C) /* SDIO命令控制寄存器 */ #define SDC_BLOCK_SIZE (SD_BASE+0X10) /* SDIO数据块长度寄存器 */ -#define SDC_BLOCK_COUNT (SD_BASE+0X14) /* SDIO数据块数目寄存器 */ -#define SDC_TRANSFER_MODE (SD_BASE+0X18) /* SDIO传输模式选择寄存器 */ -#define SDC_RESPONSE0 (SD_BASE+0X1c) /* SDIO响应寄存器0 */ -#define SDC_RESPONSE1 (SD_BASE+0X20) /* SDIO响应寄存器1 */ -#define SDC_RESPONSE2 (SD_BASE+0X24) /* SDIO响应寄存器2 */ -#define SDC_RESPONSE3 (SD_BASE+0X28) /* SDIO响应寄存器3 */ +#define SDC_BLOCK_COUNT (SD_BASE+0X14) /* SDIO数据块数目寄存器 */ +#define SDC_TRANSFER_MODE (SD_BASE+0X18) /* SDIO传输模式选择寄存器 */ +#define SDC_RESPONSE0 (SD_BASE+0X1c) /* SDIO响应寄存器0 */ +#define SDC_RESPONSE1 (SD_BASE+0X20) /* SDIO响应寄存器1 */ +#define SDC_RESPONSE2 (SD_BASE+0X24) /* SDIO响应寄存器2 */ +#define SDC_RESPONSE3 (SD_BASE+0X28) /* SDIO响应寄存器3 */ #define SDC_READ_TIMEOUT_CONTROL (SD_BASE+0X2c) /* SDIO读超时控制寄存器 */ #define SDC_INTERRUPT_STATUS (SD_BASE+0X30) /* SDIO中断状态寄存器 */ #define SDC_INTERRUPT_STATUS_MASK (SD_BASE+0X34) /* SDIO中断状态屏蔽寄存器 */ @@ -650,15 +650,15 @@ #define MAC_HASH0 (MAC_BASE+0X048) /* MAC HASH寄存器 */ #define MAC_HASH1 (MAC_BASE+0X04C) /* MAC HASH寄存器 */ #define MAC_TXPAUSE (MAC_BASE+0X050) /* MAC控制帧寄存器 */ -#define MAC_TX_BD (MAC_BASE+0X400) -#define MAC_RX_BD (MAC_BASE+0X600) +#define MAC_TX_BD (MAC_BASE+0X400) +#define MAC_RX_BD (MAC_BASE+0X600) /* ************************************** * Error Codes: * IF SUCCESS RETURN 0, ELSE RETURN OTHER ERROR CODE, - * parameter error return (-33)/E_PAR, + * parameter error return (-33)/E_PAR, * hardware error reture (-99)/E_HA ************************************** */ @@ -680,7 +680,7 @@ #define E_QOVR (-73) /* Queuing or nesting overflow */ #define E_DLT (-81) /* Object being waited for was deleted */ #define E_TMOUT (-85) /* Polling failure or timeout exceeded */ -#define E_RLWAI (-86) /* WAIT state was forcibly released */ +#define E_RLWAI (-86) /* WAIT state was forcibly released */ #define E_HA (-99) /* HARD WARE ERROR */ @@ -692,7 +692,7 @@ */ #define CLK_SGPT (1 << 16) -#define CLK_SI2S (1 << 15) +#define CLK_SI2S (1 << 15) #define CLK_SSMC (1 << 14) #define CLK_SMAC (1 << 13) #define CLK_SUSB (1 << 12) @@ -713,8 +713,8 @@ /*Interrupt Sources*/ -#define INTSRC_RTC 31 -#define INTSRC_DMAC 30 +#define INTSRC_RTC 31 +#define INTSRC_DMAC 30 #define INTSRC_EMI 29 #define INTSRC_MAC 28 #define INTSRC_TIMER1 27 @@ -732,17 +732,17 @@ #define INTSRC_USB 15 #define INTSRC_SMC0 14 #define INTSRC_SMC1 13 -#define INTSRC_SDIO 12 -#define INTSRC_EXINT10 11 -#define INTSRC_EXINT9 10 -#define INTSRC_EXINT8 9 -#define INTSRC_EXINT7 8 -#define INTSRC_EXINT6 7 -#define INTSRC_EXINT5 6 -#define INTSRC_EXINT4 5 -#define INTSRC_EXINT3 4 -#define INTSRC_EXINT2 3 -#define INTSRC_EXINT1 2 +#define INTSRC_SDIO 12 +#define INTSRC_EXINT10 11 +#define INTSRC_EXINT9 10 +#define INTSRC_EXINT8 9 +#define INTSRC_EXINT7 8 +#define INTSRC_EXINT6 7 +#define INTSRC_EXINT5 6 +#define INTSRC_EXINT4 5 +#define INTSRC_EXINT3 4 +#define INTSRC_EXINT2 3 +#define INTSRC_EXINT1 2 #define INTSRC_EXINT0 1 #define INTSRC_NULL 0 @@ -752,7 +752,7 @@ #define set_int_force(intnum) *(RP)INTC_IFR = (1 << intnum) //置1后，软件强制该位对应的中断源发出中断信号 #define enable_irq(intnum) *(RP)INTC_IER |= (1 << intnum) //置1后，允许中断源的IRQ 中断信号 #define disable_irq( intnum) *(RP)INTC_IER &= ~(1<< intnum) //置0后，不允许中断源的IRQ 中断信号 -#define mask_irq(intnum) *(RP)INTC_IMR |= (1 << intnum) //置1后，屏蔽对应的IRQ 中断信号 +#define mask_irq(intnum) *(RP)INTC_IMR |= (1 << intnum) //置1后，屏蔽对应的IRQ 中断信号 #define unmask_irq(intnum) *(RP)INTC_IMR &= ~(1 << intnum) //置0后，通过对应的IRQ 中断信号 #define mask_all_irq() *(RP)INTC_IMR = 0xFFFFFFFF //屏蔽对应的IRQ 中断信号 #define unmask_all_irq() *(RP)INTC_IMR = 0x00000000 //通过对应的IRQ 中断信号 @@ -765,7 +765,7 @@ * 所有程序中用到的Typedef ************************************** */ - + typedef char S8; /* signed 8-bit integer */ typedef short S16; /* signed 16-bit integer */ typedef long S32; /* signed 32-bit integer */ @@ -782,8 +782,8 @@ typedef void (*FP)(); /* program start address */ #ifndef _BOOL_TYPE_ #define _BOOL_TYPE_ -typedef int BOOL; /* Boolean value. TRUE (1) or FALSE (0). */ -#endif +typedef int BOOL; /* Boolean value. TRUE (1) or FALSE (0). */ +#endif typedef int ER; /* Error code. A signed integer. */ @@ -802,71 +802,71 @@ typedef int ER; /* Error code. A signed integer. */ /*Macros for debug*/ #define EOUT(fmt,...) \ - do \ - { \ - rt_kprintf("EOUT:(%s:%i) ",__FILE__,__LINE__); \ - rt_kprintf(fmt,##__VA_ARGS__); \ - }while(0) + do \ + { \ + rt_kprintf("EOUT:(%s:%i) ",__FILE__,__LINE__); \ + rt_kprintf(fmt,##__VA_ARGS__); \ + }while(0) #define RT_DEBUG #ifdef RT_DEBUG - #define DBOUT(fmt,...) \ - do \ - { \ - rt_kprintf("DBOUT:(%s:%i) ",__FILE__,__LINE__); \ - rt_kprintf(fmt,##__VA_ARGS__); \ - }while(0) + #define DBOUT(fmt,...) \ + do \ + { \ + rt_kprintf("DBOUT:(%s:%i) ",__FILE__,__LINE__); \ + rt_kprintf(fmt,##__VA_ARGS__); \ + }while(0) #else - #define DBOUT(fmt,...) \ - do{}while(0) + #define DBOUT(fmt,...) \ + do{}while(0) #endif -#ifdef RT_DEBUG - #define ASSERT(arg) \ - if((arg) == 0) \ - { \ - while(1) \ - { \ - rt_kprintf("have a assert failure\n"); \ - } \ - } +#ifdef RT_DEBUG + #define ASSERT(arg) \ + if((arg) == 0) \ + { \ + while(1) \ + { \ + rt_kprintf("have a assert failure\n"); \ + } \ + } #else - #define ASSERT(arg) \ - do \ - { \ - }while(0) + #define ASSERT(arg) \ + do \ + { \ + }while(0) #endif #define write_reg(reg,value) \ - do \ - { \ - *(RP)(reg) = value; \ - }while(0) + do \ + { \ + *(RP)(reg) = value; \ + }while(0) #define read_reg(reg) (*(RP)reg) struct rt_hw_register { - rt_uint32_t r0; - rt_uint32_t r1; - rt_uint32_t r2; - rt_uint32_t r3; - rt_uint32_t r4; - rt_uint32_t r5; - rt_uint32_t r6; - rt_uint32_t r7; - rt_uint32_t r8; - rt_uint32_t r9; - rt_uint32_t r10; - rt_uint32_t fp; - rt_uint32_t ip; - rt_uint32_t sp; - rt_uint32_t lr; - rt_uint32_t pc; - rt_uint32_t cpsr; - rt_uint32_t ORIG_r0; + rt_uint32_t r0; + rt_uint32_t r1; + rt_uint32_t r2; + rt_uint32_t r3; + rt_uint32_t r4; + rt_uint32_t r5; + rt_uint32_t r6; + rt_uint32_t r7; + rt_uint32_t r8; + rt_uint32_t r9; + rt_uint32_t r10; + rt_uint32_t fp; + rt_uint32_t ip; + rt_uint32_t sp; + rt_uint32_t lr; + rt_uint32_t pc; + rt_uint32_t cpsr; + rt_uint32_t ORIG_r0; }; diff --git a/libcpu/arm/sep4020/serial.c b/libcpu/arm/sep4020/serial.c index 713959238a..9bf1546c08 100644 --- a/libcpu/arm/sep4020/serial.c +++ b/libcpu/arm/sep4020/serial.c @@ -1,5 +1,5 @@ /* - * Copyright (c) 2006-2018, RT-Thread Development Team + * Copyright (c) 2006-2021, RT-Thread Development Team * * SPDX-License-Identifier: Apache-2.0 * @@ -7,7 +7,7 @@ * Date Author Notes * 2006-03-13 Bernard first version * 2009-04-20 yi.qiu modified according bernard's stm32 version - * 2010-10-6 wangmeng added sep4020 surpport + * 2010-10-6 wangmeng added sep4020 surpport */ #include <rtthread.h> #include <rthw.h> @@ -24,204 +24,204 @@ */ static rt_err_t rt_serial_init (rt_device_t dev) { - struct serial_device* uart = (struct serial_device*) dev->user_data; + struct serial_device* uart = (struct serial_device*) dev->user_data; - if (!(dev->flag & RT_DEVICE_FLAG_ACTIVATED)) - { + if (!(dev->flag & RT_DEVICE_FLAG_ACTIVATED)) + { - if (dev->flag & RT_DEVICE_FLAG_INT_RX) - { - rt_memset(uart->int_rx->rx_buffer, 0, - sizeof(uart->int_rx->rx_buffer)); - uart->int_rx->read_index = uart->int_rx->save_index = 0; - } - - if (dev->flag & RT_DEVICE_FLAG_INT_TX) - { - rt_memset(uart->int_tx->tx_buffer, 0, - sizeof(uart->int_tx->tx_buffer)); - uart->int_tx->write_index = uart->int_tx->save_index = 0; - } + if (dev->flag & RT_DEVICE_FLAG_INT_RX) + { + rt_memset(uart->int_rx->rx_buffer, 0, + sizeof(uart->int_rx->rx_buffer)); + uart->int_rx->read_index = uart->int_rx->save_index = 0; + } - dev->flag |= RT_DEVICE_FLAG_ACTIVATED; - } + if (dev->flag & RT_DEVICE_FLAG_INT_TX) + { + rt_memset(uart->int_tx->tx_buffer, 0, + sizeof(uart->int_tx->tx_buffer)); + uart->int_tx->write_index = uart->int_tx->save_index = 0; + } - return RT_EOK; + dev->flag |= RT_DEVICE_FLAG_ACTIVATED; + } + + return RT_EOK; } /* save a char to serial buffer */ static void rt_serial_savechar(struct serial_device* uart, char ch) { - rt_base_t level; - - /* disable interrupt */ - level = rt_hw_interrupt_disable(); + rt_base_t level; + + /* disable interrupt */ + level = rt_hw_interrupt_disable(); - uart->int_rx->rx_buffer[uart->int_rx->save_index] = ch; - uart->int_rx->save_index ++; - if (uart->int_rx->save_index >= UART_RX_BUFFER_SIZE) - uart->int_rx->save_index = 0; - - /* if the next position is read index, discard this 'read char' */ - if (uart->int_rx->save_index == uart->int_rx->read_index) - { - uart->int_rx->read_index ++; - if (uart->int_rx->read_index >= UART_RX_BUFFER_SIZE) - uart->int_rx->read_index = 0; - } + uart->int_rx->rx_buffer[uart->int_rx->save_index] = ch; + uart->int_rx->save_index ++; + if (uart->int_rx->save_index >= UART_RX_BUFFER_SIZE) + uart->int_rx->save_index = 0; - /* enable interrupt */ - rt_hw_interrupt_enable(level); + /* if the next position is read index, discard this 'read char' */ + if (uart->int_rx->save_index == uart->int_rx->read_index) + { + uart->int_rx->read_index ++; + if (uart->int_rx->read_index >= UART_RX_BUFFER_SIZE) + uart->int_rx->read_index = 0; + } + + /* enable interrupt */ + rt_hw_interrupt_enable(level); } static rt_err_t rt_serial_open(rt_device_t dev, rt_uint16_t oflag) { - RT_ASSERT(dev != RT_NULL); - return RT_EOK; + RT_ASSERT(dev != RT_NULL); + return RT_EOK; } static rt_err_t rt_serial_close(rt_device_t dev) { - RT_ASSERT(dev != RT_NULL); - return RT_EOK; + RT_ASSERT(dev != RT_NULL); + return RT_EOK; } static rt_size_t rt_serial_read (rt_device_t dev, rt_off_t pos, void* buffer, rt_size_t size) { - rt_uint8_t* ptr; - rt_err_t err_code; - struct serial_device* uart; - - ptr = buffer; - err_code = RT_EOK; - uart = (struct serial_device*)dev->user_data; + rt_uint8_t* ptr; + rt_err_t err_code; + struct serial_device* uart; + + ptr = buffer; + err_code = RT_EOK; + uart = (struct serial_device*)dev->user_data; - if (dev->flag & RT_DEVICE_FLAG_INT_RX) - { - rt_base_t level; + if (dev->flag & RT_DEVICE_FLAG_INT_RX) + { + rt_base_t level; - /* interrupt mode Rx */ - while (size) - { - if (uart->int_rx->read_index != uart->int_rx->save_index) - { - *ptr++ = uart->int_rx->rx_buffer[uart->int_rx->read_index]; - size --; + /* interrupt mode Rx */ + while (size) + { + if (uart->int_rx->read_index != uart->int_rx->save_index) + { + *ptr++ = uart->int_rx->rx_buffer[uart->int_rx->read_index]; + size --; - /* disable interrupt */ - level = rt_hw_interrupt_disable(); + /* disable interrupt */ + level = rt_hw_interrupt_disable(); - uart->int_rx->read_index ++; - if (uart->int_rx->read_index >= UART_RX_BUFFER_SIZE) - uart->int_rx->read_index = 0; + uart->int_rx->read_index ++; + if (uart->int_rx->read_index >= UART_RX_BUFFER_SIZE) + uart->int_rx->read_index = 0; - /* enable interrupt */ - rt_hw_interrupt_enable(level); - } - else - { - /* set error code */ - err_code = -RT_EEMPTY; - break; - } - } - } - else - { - /* polling mode */ - while ((rt_uint32_t)ptr - (rt_uint32_t)buffer < size) - { - while (uart->uart_device->lsr & USTAT_RCV_READY) - { - *ptr = uart->uart_device->dlbl_fifo.txfifo & 0xff; - ptr ++; - } - } - } + /* enable interrupt */ + rt_hw_interrupt_enable(level); + } + else + { + /* set error code */ + err_code = -RT_EEMPTY; + break; + } + } + } + else + { + /* polling mode */ + while ((rt_uint32_t)ptr - (rt_uint32_t)buffer < size) + { + while (uart->uart_device->lsr & USTAT_RCV_READY) + { + *ptr = uart->uart_device->dlbl_fifo.txfifo & 0xff; + ptr ++; + } + } + } - /* set error code */ - rt_set_errno(err_code); - return (rt_uint32_t)ptr - (rt_uint32_t)buffer; + /* set error code */ + rt_set_errno(err_code); + return (rt_uint32_t)ptr - (rt_uint32_t)buffer; } static rt_size_t rt_serial_write (rt_device_t dev, rt_off_t pos, const void* buffer, rt_size_t size) -{ - rt_uint8_t* ptr; - rt_err_t err_code; - struct serial_device* uart; - - err_code = RT_EOK; - ptr = (rt_uint8_t*)buffer; - uart = (struct serial_device*)dev->user_data; +{ + rt_uint8_t* ptr; + rt_err_t err_code; + struct serial_device* uart; + + err_code = RT_EOK; + ptr = (rt_uint8_t*)buffer; + uart = (struct serial_device*)dev->user_data; + + if (dev->flag & RT_DEVICE_FLAG_INT_TX) + { + /* interrupt mode Tx */ + while (uart->int_tx->save_index != uart->int_tx->write_index) + { + /* save on tx buffer */ + uart->int_tx->tx_buffer[uart->int_tx->save_index] = *ptr++; + + -- size; - if (dev->flag & RT_DEVICE_FLAG_INT_TX) - { - /* interrupt mode Tx */ - while (uart->int_tx->save_index != uart->int_tx->write_index) - { - /* save on tx buffer */ - uart->int_tx->tx_buffer[uart->int_tx->save_index] = *ptr++; - - -- size; + /* move to next position */ + uart->int_tx->save_index ++; - /* move to next position */ - uart->int_tx->save_index ++; - - /* wrap save index */ - if (uart->int_tx->save_index >= UART_TX_BUFFER_SIZE) - uart->int_tx->save_index = 0; - } - - /* set error code */ - if (size > 0) - err_code = -RT_EFULL; - } - else - { - /* polling mode */ - while (size) - { - /* - * to be polite with serial console add a line feed - * to the carriage return character - */ - if (*ptr == '\n' && (dev->flag & RT_DEVICE_FLAG_STREAM)) - { - while (!(uart->uart_device->lsr & USTAT_TXB_EMPTY)); - uart->uart_device->dlbl_fifo.txfifo = '\r'; - } + /* wrap save index */ + if (uart->int_tx->save_index >= UART_TX_BUFFER_SIZE) + uart->int_tx->save_index = 0; + } - while (!(uart->uart_device->lsr & USTAT_TXB_EMPTY)); - uart->uart_device->dlbl_fifo.txfifo = (*ptr & 0x1FF); + /* set error code */ + if (size > 0) + err_code = -RT_EFULL; + } + else + { + /* polling mode */ + while (size) + { + /* + * to be polite with serial console add a line feed + * to the carriage return character + */ + if (*ptr == '\n' && (dev->flag & RT_DEVICE_FLAG_STREAM)) + { + while (!(uart->uart_device->lsr & USTAT_TXB_EMPTY)); + uart->uart_device->dlbl_fifo.txfifo = '\r'; + } - ++ptr; --size; - } - } + while (!(uart->uart_device->lsr & USTAT_TXB_EMPTY)); + uart->uart_device->dlbl_fifo.txfifo = (*ptr & 0x1FF); - /* set error code */ - rt_set_errno(err_code); - - return (rt_uint32_t)ptr - (rt_uint32_t)buffer; + ++ptr; --size; + } + } + + /* set error code */ + rt_set_errno(err_code); + + return (rt_uint32_t)ptr - (rt_uint32_t)buffer; } static rt_err_t rt_serial_control (rt_device_t dev, int cmd, void *args) { - RT_ASSERT(dev != RT_NULL); + RT_ASSERT(dev != RT_NULL); + + switch (cmd) + { + case RT_DEVICE_CTRL_SUSPEND: + /* suspend device */ + dev->flag |= RT_DEVICE_FLAG_SUSPENDED; + break; + + case RT_DEVICE_CTRL_RESUME: + /* resume device */ + dev->flag &= ~RT_DEVICE_FLAG_SUSPENDED; + break; + } - switch (cmd) - { - case RT_DEVICE_CTRL_SUSPEND: - /* suspend device */ - dev->flag |= RT_DEVICE_FLAG_SUSPENDED; - break; - - case RT_DEVICE_CTRL_RESUME: - /* resume device */ - dev->flag &= ~RT_DEVICE_FLAG_SUSPENDED; - break; - } - - return RT_EOK; + return RT_EOK; } /* @@ -229,49 +229,49 @@ static rt_err_t rt_serial_control (rt_device_t dev, int cmd, void *args) */ rt_err_t rt_hw_serial_register(rt_device_t device, const char* name, rt_uint32_t flag, struct serial_device *serial) { - RT_ASSERT(device != RT_NULL); + RT_ASSERT(device != RT_NULL); - device->type = RT_Device_Class_Char; - device->rx_indicate = RT_NULL; - device->tx_complete = RT_NULL; - device->init = rt_serial_init; - device->open = rt_serial_open; - device->close = rt_serial_close; - device->read = rt_serial_read; - device->write = rt_serial_write; - device->control = rt_serial_control; - device->user_data = serial; + device->type = RT_Device_Class_Char; + device->rx_indicate = RT_NULL; + device->tx_complete = RT_NULL; + device->init = rt_serial_init; + device->open = rt_serial_open; + device->close = rt_serial_close; + device->read = rt_serial_read; + device->write = rt_serial_write; + device->control = rt_serial_control; + device->user_data = serial; - /* register a character device */ - return rt_device_register(device, name, RT_DEVICE_FLAG_RDWR | flag); + /* register a character device */ + return rt_device_register(device, name, RT_DEVICE_FLAG_RDWR | flag); } - + /* ISR for serial interrupt */ void rt_hw_serial_isr(rt_device_t device) { - struct serial_device* uart = (struct serial_device*) device->user_data; - - /* interrupt mode receive */ - RT_ASSERT(device->flag & RT_DEVICE_FLAG_INT_RX); + struct serial_device* uart = (struct serial_device*) device->user_data; + + /* interrupt mode receive */ + RT_ASSERT(device->flag & RT_DEVICE_FLAG_INT_RX); + + /* save on rx buffer */ + while (uart->uart_device->lsr & USTAT_RCV_READY) + { + rt_serial_savechar(uart, uart->uart_device->dlbl_fifo.rxfifo & 0xff); + } - /* save on rx buffer */ - while (uart->uart_device->lsr & USTAT_RCV_READY) - { - rt_serial_savechar(uart, uart->uart_device->dlbl_fifo.rxfifo & 0xff); - } + /* invoke callback */ + if (device->rx_indicate != RT_NULL) + { + rt_size_t rx_length; - /* invoke callback */ - if (device->rx_indicate != RT_NULL) - { - rt_size_t rx_length; - - /* get rx length */ - rx_length = uart->int_rx->read_index > uart->int_rx->save_index ? - UART_RX_BUFFER_SIZE - uart->int_rx->read_index + uart->int_rx->save_index : - uart->int_rx->save_index - uart->int_rx->read_index; + /* get rx length */ + rx_length = uart->int_rx->read_index > uart->int_rx->save_index ? + UART_RX_BUFFER_SIZE - uart->int_rx->read_index + uart->int_rx->save_index : + uart->int_rx->save_index - uart->int_rx->read_index; - device->rx_indicate(device, rx_length); - } + device->rx_indicate(device, rx_length); + } } /*@}*/ diff --git a/libcpu/arm/sep4020/serial.h b/libcpu/arm/sep4020/serial.h index 69e7df248c..26ec0f6cec 100644 --- a/libcpu/arm/sep4020/serial.h +++ b/libcpu/arm/sep4020/serial.h @@ -1,5 +1,5 @@ /* - * Copyright (c) 2006-2018, RT-Thread Development Team + * Copyright (c) 2006-2021, RT-Thread Development Team * * SPDX-License-Identifier: Apache-2.0 * @@ -7,7 +7,7 @@ * Date Author Notes * 2006-03-13 Bernard first version * 2009-04-20 yi.qiu modified according bernard's stm32 version - * 2010-10-6 wangmeng added sep4020 surpport + * 2010-10-6 wangmeng added sep4020 surpport */ #ifndef __SERIAL_H__ @@ -15,67 +15,67 @@ #include <sep4020.h> -#define USTAT_RCV_READY 0x01 /* receive data ready */ -#define USTAT_TXB_EMPTY 0x40 /* tx buffer empty */ -#define BPS 115200 /* serial baudrate */ +#define USTAT_RCV_READY 0x01 /* receive data ready */ +#define USTAT_TXB_EMPTY 0x40 /* tx buffer empty */ +#define BPS 115200 /* serial baudrate */ -#define UART_RX_BUFFER_SIZE 64 -#define UART_TX_BUFFER_SIZE 64 +#define UART_RX_BUFFER_SIZE 64 +#define UART_TX_BUFFER_SIZE 64 /*For sep4020's uart have several secondary function*/ /*we use union to decribe it*/ union dlbl_fifo { - rt_uint32_t dlbl; - rt_uint32_t rxfifo; - rt_uint32_t txfifo; + rt_uint32_t dlbl; + rt_uint32_t rxfifo; + rt_uint32_t txfifo; }; union dlbh_ier { - rt_uint32_t dlbh; - rt_uint32_t ier; + rt_uint32_t dlbh; + rt_uint32_t ier; }; union iir_fcr { - rt_uint32_t iir; - rt_uint32_t fcr; + rt_uint32_t iir; + rt_uint32_t fcr; }; struct serial_int_rx { - rt_uint8_t rx_buffer[UART_RX_BUFFER_SIZE]; - rt_uint32_t read_index, save_index; + rt_uint8_t rx_buffer[UART_RX_BUFFER_SIZE]; + rt_uint32_t read_index, save_index; }; struct serial_int_tx { - rt_uint8_t tx_buffer[UART_TX_BUFFER_SIZE]; - rt_uint32_t write_index, save_index; + rt_uint8_t tx_buffer[UART_TX_BUFFER_SIZE]; + rt_uint32_t write_index, save_index; }; typedef struct uartport { - union dlbl_fifo dlbl_fifo; - union dlbh_ier dlbh_ier; - union iir_fcr iir_fcr; - rt_uint32_t lcr; - rt_uint32_t mcr; - rt_uint32_t lsr; - rt_uint32_t msr; + union dlbl_fifo dlbl_fifo; + union dlbh_ier dlbh_ier; + union iir_fcr iir_fcr; + rt_uint32_t lcr; + rt_uint32_t mcr; + rt_uint32_t lsr; + rt_uint32_t msr; }uartport; struct serial_device { - uartport* uart_device; - - /* rx structure */ - struct serial_int_rx* int_rx; + uartport* uart_device; - /* tx structure */ - struct serial_int_tx* int_tx; + /* rx structure */ + struct serial_int_rx* int_rx; + + /* tx structure */ + struct serial_int_tx* int_tx; }; rt_err_t rt_hw_serial_register(rt_device_t device, const char* name, rt_uint32_t flag, struct serial_device *serial); diff --git a/libcpu/arm/sep4020/stack.c b/libcpu/arm/sep4020/stack.c index b2205c76d2..3a7b5fd87c 100644 --- a/libcpu/arm/sep4020/stack.c +++ b/libcpu/arm/sep4020/stack.c @@ -1,5 +1,5 @@ /* - * Copyright (c) 2006-2018, RT-Thread Development Team + * Copyright (c) 2006-2021, RT-Thread Development Team * * SPDX-License-Identifier: Apache-2.0 * diff --git a/libcpu/arm/sep4020/trap.c b/libcpu/arm/sep4020/trap.c index c551b2246c..441a55bd6d 100644 --- a/libcpu/arm/sep4020/trap.c +++ b/libcpu/arm/sep4020/trap.c @@ -1,5 +1,5 @@ /* - * Copyright (c) 2006-2018, RT-Thread Development Team + * Copyright (c) 2006-2021, RT-Thread Development Team * * SPDX-License-Identifier: Apache-2.0 * @@ -31,13 +31,13 @@ extern struct rt_thread *rt_current_thread; void rt_hw_show_register (struct rt_hw_register *regs) { - rt_kprintf("Execption:\n"); - rt_kprintf("r00:0x%08x r01:0x%08x r02:0x%08x r03:0x%08x\n", regs->r0, regs->r1, regs->r2, regs->r3); - rt_kprintf("r04:0x%08x r05:0x%08x r06:0x%08x r07:0x%08x\n", regs->r4, regs->r5, regs->r6, regs->r7); - rt_kprintf("r08:0x%08x r09:0x%08x r10:0x%08x\n", regs->r8, regs->r9, regs->r10); - rt_kprintf("fp :0x%08x ip :0x%08x\n", regs->fp, regs->ip); - rt_kprintf("sp :0x%08x lr :0x%08x pc :0x%08x\n", regs->sp, regs->lr, regs->pc); - rt_kprintf("cpsr:0x%08x\n", regs->cpsr); + rt_kprintf("Execption:\n"); + rt_kprintf("r00:0x%08x r01:0x%08x r02:0x%08x r03:0x%08x\n", regs->r0, regs->r1, regs->r2, regs->r3); + rt_kprintf("r04:0x%08x r05:0x%08x r06:0x%08x r07:0x%08x\n", regs->r4, regs->r5, regs->r6, regs->r7); + rt_kprintf("r08:0x%08x r09:0x%08x r10:0x%08x\n", regs->r8, regs->r9, regs->r10); + rt_kprintf("fp :0x%08x ip :0x%08x\n", regs->fp, regs->ip); + rt_kprintf("sp :0x%08x lr :0x%08x pc :0x%08x\n", regs->sp, regs->lr, regs->pc); + rt_kprintf("cpsr:0x%08x\n", regs->cpsr); } /** @@ -50,13 +50,13 @@ void rt_hw_show_register (struct rt_hw_register *regs) */ void rt_hw_trap_udef(struct rt_hw_register *regs) { - rt_hw_show_register(regs); + rt_hw_show_register(regs); - rt_kprintf("undefined instruction\n"); - rt_kprintf("thread - %s stack:\n", rt_current_thread->name); - rt_hw_backtrace((rt_uint32_t *)regs->fp, (rt_uint32_t)rt_current_thread->entry); + rt_kprintf("undefined instruction\n"); + rt_kprintf("thread - %s stack:\n", rt_current_thread->name); + rt_hw_backtrace((rt_uint32_t *)regs->fp, (rt_uint32_t)rt_current_thread->entry); - rt_hw_cpu_shutdown(); + rt_hw_cpu_shutdown(); } /** @@ -70,10 +70,10 @@ void rt_hw_trap_udef(struct rt_hw_register *regs) */ void rt_hw_trap_swi(struct rt_hw_register *regs) { - rt_hw_show_register(regs); + rt_hw_show_register(regs); - rt_kprintf("software interrupt\n"); - rt_hw_cpu_shutdown(); + rt_kprintf("software interrupt\n"); + rt_hw_cpu_shutdown(); } /** @@ -86,13 +86,13 @@ void rt_hw_trap_swi(struct rt_hw_register *regs) */ void rt_hw_trap_pabt(struct rt_hw_register *regs) { - rt_hw_show_register(regs); + rt_hw_show_register(regs); - rt_kprintf("prefetch abort\n"); - rt_kprintf("thread - %s stack:\n", rt_current_thread->name); - rt_hw_backtrace((rt_uint32_t *)regs->fp, (rt_uint32_t)rt_current_thread->entry); + rt_kprintf("prefetch abort\n"); + rt_kprintf("thread - %s stack:\n", rt_current_thread->name); + rt_hw_backtrace((rt_uint32_t *)regs->fp, (rt_uint32_t)rt_current_thread->entry); - rt_hw_cpu_shutdown(); + rt_hw_cpu_shutdown(); } /** @@ -105,13 +105,13 @@ void rt_hw_trap_pabt(struct rt_hw_register *regs) */ void rt_hw_trap_dabt(struct rt_hw_register *regs) { - rt_hw_show_register(regs); + rt_hw_show_register(regs); - rt_kprintf("data abort\n"); - rt_kprintf("thread - %s stack:\n", rt_current_thread->name); - rt_hw_backtrace((rt_uint32_t *)regs->fp, (rt_uint32_t)rt_current_thread->entry); + rt_kprintf("data abort\n"); + rt_kprintf("thread - %s stack:\n", rt_current_thread->name); + rt_hw_backtrace((rt_uint32_t *)regs->fp, (rt_uint32_t)rt_current_thread->entry); - rt_hw_cpu_shutdown(); + rt_hw_cpu_shutdown(); } /** @@ -123,9 +123,9 @@ void rt_hw_trap_dabt(struct rt_hw_register *regs) */ void rt_hw_trap_resv(struct rt_hw_register *regs) { - rt_kprintf("not used\n"); - rt_hw_show_register(regs); - rt_hw_cpu_shutdown(); + rt_kprintf("not used\n"); + rt_hw_show_register(regs); + rt_hw_cpu_shutdown(); } extern struct rt_irq_desc isr_table[]; @@ -155,13 +155,13 @@ void rt_hw_trap_irq(void) isr_func(irq, param); #ifdef RT_USING_INTERRUPT_INFO - isr_table[irq].counter++; + isr_table[irq].counter++; #endif /* RT_USING_INTERRUPT_INFO */ } void rt_hw_trap_fiq(void) { - rt_kprintf("fast interrupt request\n"); + rt_kprintf("fast interrupt request\n"); } /*@}*/ diff --git a/libcpu/arm/zynq7000/SConscript b/libcpu/arm/zynq7000/SConscript deleted file mode 100644 index 28af7ba651..0000000000 --- a/libcpu/arm/zynq7000/SConscript +++ /dev/null @@ -1,23 +0,0 @@ -# RT-Thread building script for component - -from building import * - -Import('rtconfig') - -cwd = GetCurrentDir() -src = Glob('*.c') + Glob('*.cpp') -CPPPATH = [cwd] - -if rtconfig.PLATFORM == 'armcc': - src += Glob('*_rvds.S') - -if rtconfig.PLATFORM == 'gcc': - src += Glob('*_init.S') - src += Glob('*_gcc.S') - -if rtconfig.PLATFORM == 'iar': - src += Glob('*_iar.S') - -group = DefineGroup('CPU', src, depend = [''], CPPPATH = CPPPATH) - -Return('group') diff --git a/libcpu/arm/zynq7000/armv7.h b/libcpu/arm/zynq7000/armv7.h deleted file mode 100644 index 65f6c27860..0000000000 --- a/libcpu/arm/zynq7000/armv7.h +++ /dev/null @@ -1,65 +0,0 @@ -#ifndef __ARMV7_H__ -#define __ARMV7_H__ -/* - * COPYRIGHT (C) 2013-2014, Shanghai Real-Thread Technology Co., Ltd - * - * All rights reserved. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 2 of the License, or - * (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License along - * with this program; if not, write to the Free Software Foundation, Inc., - * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA. - */ - -/* the exception stack without VFP registers */ -struct rt_hw_exp_stack -{ - unsigned long r0; - unsigned long r1; - unsigned long r2; - unsigned long r3; - unsigned long r4; - unsigned long r5; - unsigned long r6; - unsigned long r7; - unsigned long r8; - unsigned long r9; - unsigned long r10; - unsigned long fp; - unsigned long ip; - unsigned long sp; - unsigned long lr; - unsigned long pc; - unsigned long cpsr; -}; - -#define USERMODE 0x10 -#define FIQMODE 0x11 -#define IRQMODE 0x12 -#define SVCMODE 0x13 -#define MONITORMODE 0x16 -#define ABORTMODE 0x17 -#define HYPMODE 0x1b -#define UNDEFMODE 0x1b -#define MODEMASK 0x1f -#define NOINT 0xc0 - -#define T_Bit (1<<5) -#define F_Bit (1<<6) -#define I_Bit (1<<7) -#define A_Bit (1<<8) -#define E_Bit (1<<9) -#define J_Bit (1<<24) - -void rt_hw_mmu_init(void); - -#endif diff --git a/libcpu/arm/zynq7000/context_gcc.S b/libcpu/arm/zynq7000/context_gcc.S deleted file mode 100644 index 98f98a0244..0000000000 --- a/libcpu/arm/zynq7000/context_gcc.S +++ /dev/null @@ -1,92 +0,0 @@ -/* - * Copyright (c) 2006-2018, Shanghai Real-Thread Technology Co., Ltd - * - * SPDX-License-Identifier: Apache-2.0 - * - * Change Logs: - * Date Author Notes - * 2009-01-20 Bernard first version - */ - -#define NOINT 0xc0 - -/* - * rt_base_t rt_hw_interrupt_disable(); - */ -.globl rt_hw_interrupt_disable -rt_hw_interrupt_disable: - mrs r0, cpsr - orr r1, r0, #NOINT - msr cpsr_c, r1 - bx lr - -/* - * void rt_hw_interrupt_enable(rt_base_t level); - */ -.globl rt_hw_interrupt_enable -rt_hw_interrupt_enable: - msr cpsr, r0 - bx lr - -/* - * void rt_hw_context_switch(rt_uint32 from, rt_uint32 to); - * r0 --> from - * r1 --> to - */ -.globl rt_hw_context_switch -rt_hw_context_switch: - stmfd sp!, {lr} @ push pc (lr should be pushed in place of PC) - stmfd sp!, {r0-r12, lr} @ push lr & register file - - mrs r4, cpsr - tst lr, #0x01 - beq _ARM_MODE - orr r4, r4, #0x20 @ it's thumb code - -_ARM_MODE: - stmfd sp!, {r4} @ push cpsr - - str sp, [r0] @ store sp in preempted tasks TCB - ldr sp, [r1] @ get new task stack pointer - - ldmfd sp!, {r4} @ pop new task cpsr to spsr - msr spsr_cxsf, r4 - - ldmfd sp!, {r0-r12, lr, pc}^ @ pop new task r0-r12, lr & pc, copy spsr to cpsr - -/* - * void rt_hw_context_switch_to(rt_uint32 to); - * r0 --> to - */ -.globl rt_hw_context_switch_to -rt_hw_context_switch_to: - ldr sp, [r0] @ get new task stack pointer - - ldmfd sp!, {r4} @ pop new task spsr - msr spsr_cxsf, r4 - - bic r4, r4, #0x20 @ must be ARM mode - msr cpsr_cxsf, r4 - - ldmfd sp!, {r0-r12, lr, pc}^ @ pop new task r0-r12, lr & pc - -/* - * void rt_hw_context_switch_interrupt(rt_uint32 from, rt_uint32 to); - */ -.globl rt_thread_switch_interrupt_flag -.globl rt_interrupt_from_thread -.globl rt_interrupt_to_thread -.globl rt_hw_context_switch_interrupt -rt_hw_context_switch_interrupt: - ldr r2, =rt_thread_switch_interrupt_flag - ldr r3, [r2] - cmp r3, #1 - beq _reswitch - mov r3, #1 @ set rt_thread_switch_interrupt_flag to 1 - str r3, [r2] - ldr r2, =rt_interrupt_from_thread @ set rt_interrupt_from_thread - str r0, [r2] -_reswitch: - ldr r2, =rt_interrupt_to_thread @ set rt_interrupt_to_thread - str r1, [r2] - bx lr diff --git a/libcpu/arm/zynq7000/cp15.h b/libcpu/arm/zynq7000/cp15.h deleted file mode 100644 index 75d81736ab..0000000000 --- a/libcpu/arm/zynq7000/cp15.h +++ /dev/null @@ -1,22 +0,0 @@ -/* - * Copyright (c) 2006-2018, RT-Thread Development Team - * - * SPDX-License-Identifier: Apache-2.0 - * - * Change Logs: - * Date Author Notes - * 2013-07-20 Bernard first version - */ - -#ifndef __CP15_H__ -#define __CP15_H__ - -unsigned long rt_cpu_get_smp_id(void); - -void rt_cpu_mmu_disable(void); -void rt_cpu_mmu_enable(void); -void rt_cpu_tlb_set(volatile unsigned long*); - -void rt_cpu_vector_set_base(unsigned int addr); - -#endif diff --git a/libcpu/arm/zynq7000/cp15_gcc.S b/libcpu/arm/zynq7000/cp15_gcc.S deleted file mode 100644 index 0e3e60655c..0000000000 --- a/libcpu/arm/zynq7000/cp15_gcc.S +++ /dev/null @@ -1,125 +0,0 @@ -/* - * Copyright (c) 2006-2018, RT-Thread Development Team - * - * SPDX-License-Identifier: Apache-2.0 - * - * Change Logs: - * Date Author Notes - * 2013-07-05 Bernard the first version - */ - -.globl rt_cpu_get_smp_id -rt_cpu_get_smp_id: - mrc p15, #0, r0, c0, c0, #5 - bx lr - -.globl rt_cpu_vector_set_base -rt_cpu_vector_set_base: - mcr p15, #0, r0, c12, c0, #0 - dsb - bx lr - -.globl rt_hw_cpu_dcache_enable -rt_hw_cpu_dcache_enable: - mrc p15, #0, r0, c1, c0, #0 - orr r0, r0, #0x00000004 - mcr p15, #0, r0, c1, c0, #0 - bx lr - -.globl rt_hw_cpu_icache_enable -rt_hw_cpu_icache_enable: - mrc p15, #0, r0, c1, c0, #0 - orr r0, r0, #0x00001000 - mcr p15, #0, r0, c1, c0, #0 - bx lr - -_FLD_MAX_WAY: - .word 0x3ff -_FLD_MAX_IDX: - .word 0x7ff - -.globl rt_cpu_dcache_clean_flush -rt_cpu_dcache_clean_flush: - push {r4-r11} - dmb - mrc p15, #1, r0, c0, c0, #1 @ read clid register - ands r3, r0, #0x7000000 @ get level of coherency - mov r3, r3, lsr #23 - beq finished - mov r10, #0 -loop1: - add r2, r10, r10, lsr #1 - mov r1, r0, lsr r2 - and r1, r1, #7 - cmp r1, #2 - blt skip - mcr p15, #2, r10, c0, c0, #0 - isb - mrc p15, #1, r1, c0, c0, #0 - and r2, r1, #7 - add r2, r2, #4 - ldr r4, _FLD_MAX_WAY - ands r4, r4, r1, lsr #3 - clz r5, r4 - ldr r7, _FLD_MAX_IDX - ands r7, r7, r1, lsr #13 -loop2: - mov r9, r4 -loop3: - orr r11, r10, r9, lsl r5 - orr r11, r11, r7, lsl r2 - mcr p15, #0, r11, c7, c14, #2 - subs r9, r9, #1 - bge loop3 - subs r7, r7, #1 - bge loop2 -skip: - add r10, r10, #2 - cmp r3, r10 - bgt loop1 - -finished: - dsb - isb - pop {r4-r11} - bx lr - -.globl rt_hw_cpu_dcache_disable -rt_hw_cpu_dcache_disable: - push {r4-r11, lr} - bl rt_cpu_dcache_clean_flush - mrc p15, #0, r0, c1, c0, #0 - bic r0, r0, #0x00000004 - mcr p15, #0, r0, c1, c0, #0 - pop {r4-r11, lr} - bx lr - -.globl rt_hw_cpu_icache_disable -rt_hw_cpu_icache_disable: - mrc p15, #0, r0, c1, c0, #0 - bic r0, r0, #0x00001000 - mcr p15, #0, r0, c1, c0, #0 - bx lr - -.globl rt_cpu_mmu_disable -rt_cpu_mmu_disable: - mcr p15, #0, r0, c8, c7, #0 @ invalidate tlb - mrc p15, #0, r0, c1, c0, #0 - bic r0, r0, #1 - mcr p15, #0, r0, c1, c0, #0 @ clear mmu bit - dsb - bx lr - -.globl rt_cpu_mmu_enable -rt_cpu_mmu_enable: - mrc p15, #0, r0, c1, c0, #0 - orr r0, r0, #0x001 - mcr p15, #0, r0, c1, c0, #0 @ set mmu enable bit - dsb - bx lr - -.globl rt_cpu_tlb_set -rt_cpu_tlb_set: - mcr p15, #0, r0, c2, c0, #0 - dmb - bx lr diff --git a/libcpu/arm/zynq7000/cpu.c b/libcpu/arm/zynq7000/cpu.c deleted file mode 100644 index f6b7f5d852..0000000000 --- a/libcpu/arm/zynq7000/cpu.c +++ /dev/null @@ -1,41 +0,0 @@ -/* - * Copyright (c) 2006-2018, RT-Thread Development Team - * - * SPDX-License-Identifier: Apache-2.0 - * - * Change Logs: - * Date Author Notes - * 2013-07-20 Bernard first version - */ - -#include <rthw.h> -#include <rtthread.h> -#include "zynq7000.h" - -/** - * reset cpu by dog's time-out - * - */ -RT_WEAK void rt_hw_cpu_reset() -{ - while (1); /* loop forever and wait for reset to happen */ - - /* NEVER REACHED */ -} - -/** - * shutdown CPU - * - */ -RT_WEAK void rt_hw_cpu_shutdown() -{ - rt_uint32_t level; - rt_kprintf("shutdown...\n"); - - level = rt_hw_interrupt_disable(); - while (level) - { - RT_ASSERT(0); - } -} - diff --git a/libcpu/arm/zynq7000/gic.c b/libcpu/arm/zynq7000/gic.c deleted file mode 100644 index 76404d4c46..0000000000 --- a/libcpu/arm/zynq7000/gic.c +++ /dev/null @@ -1,228 +0,0 @@ -/* - * Copyright (c) 2006-2018, RT-Thread Development Team - * - * SPDX-License-Identifier: Apache-2.0 - * - * Change Logs: - * Date Author Notes - * 2013-07-20 Bernard first version - */ - -#include <rtthread.h> -#include <board.h> - -#include "gic.h" -#include "cp15.h" - -struct arm_gic -{ - rt_uint32_t offset; - - rt_uint32_t dist_hw_base; - rt_uint32_t cpu_hw_base; -}; -static struct arm_gic _gic_table[ARM_GIC_MAX_NR]; - -#define GIC_CPU_CTRL(hw_base) __REG32((hw_base) + 0x00) -#define GIC_CPU_PRIMASK(hw_base) __REG32((hw_base) + 0x04) -#define GIC_CPU_BINPOINT(hw_base) __REG32((hw_base) + 0x08) -#define GIC_CPU_INTACK(hw_base) __REG32((hw_base) + 0x0c) -#define GIC_CPU_EOI(hw_base) __REG32((hw_base) + 0x10) -#define GIC_CPU_RUNNINGPRI(hw_base) __REG32((hw_base) + 0x14) -#define GIC_CPU_HIGHPRI(hw_base) __REG32((hw_base) + 0x18) - -#define GIC_DIST_CTRL(hw_base) __REG32((hw_base) + 0x000) -#define GIC_DIST_TYPE(hw_base) __REG32((hw_base) + 0x004) -#define GIC_DIST_IGROUP(hw_base, n) __REG32((hw_base) + 0x080 + (n/32) * 4) -#define GIC_DIST_ENABLE_SET(hw_base, n) __REG32((hw_base) + 0x100 + (n/32) * 4) -#define GIC_DIST_ENABLE_CLEAR(hw_base, n) __REG32((hw_base) + 0x180 + (n/32) * 4) -#define GIC_DIST_PENDING_SET(hw_base, n) __REG32((hw_base) + 0x200) -#define GIC_DIST_PENDING_CLEAR(hw_base, n) __REG32((hw_base) + 0x280 + (n/32) * 4) -#define GIC_DIST_ACTIVE_BIT(hw_base) __REG32((hw_base) + 0x300) -#define GIC_DIST_PRI(hw_base, n) __REG32((hw_base) + 0x400 + (n/4) * 4) -#define GIC_DIST_TARGET(hw_base, n) __REG32((hw_base) + 0x800 + (n/4) * 4) -#define GIC_DIST_CONFIG(hw_base, n) __REG32((hw_base) + 0xc00 + (n/16) * 4) -#define GIC_DIST_SOFTINT(hw_base) __REG32((hw_base) + 0xf00) -#define GIC_DIST_CPENDSGI(hw_base, n) __REG32((hw_base) + 0xf10 + (n/4) * 4) -#define GIC_DIST_ICPIDR2(hw_base) __REG32((hw_base) + 0xfe8) - -static unsigned int _gic_max_irq; - -int arm_gic_get_active_irq(rt_uint32_t index) -{ - int irq; - - RT_ASSERT(index < ARM_GIC_MAX_NR); - - irq = GIC_CPU_INTACK(_gic_table[index].cpu_hw_base); - irq += _gic_table[index].offset; - return irq; -} - -void arm_gic_ack(rt_uint32_t index, int irq) -{ - rt_uint32_t mask = 1 << (irq % 32); - - RT_ASSERT(index < ARM_GIC_MAX_NR); - - irq = irq - _gic_table[index].offset; - RT_ASSERT(irq >= 0); - - GIC_DIST_PENDING_CLEAR(_gic_table[index].dist_hw_base, irq) = mask; - GIC_CPU_EOI(_gic_table[index].cpu_hw_base) = irq; -} - -void arm_gic_mask(rt_uint32_t index, int irq) -{ - rt_uint32_t mask = 1 << (irq % 32); - - RT_ASSERT(index < ARM_GIC_MAX_NR); - - irq = irq - _gic_table[index].offset; - RT_ASSERT(irq >= 0); - - GIC_DIST_ENABLE_CLEAR(_gic_table[index].dist_hw_base, irq) = mask; -} - -void arm_gic_set_cpu(rt_uint32_t index, int irq, unsigned int cpumask) -{ - rt_uint32_t old_tgt; - - RT_ASSERT(index < ARM_GIC_MAX_NR); - - irq = irq - _gic_table[index].offset; - RT_ASSERT(irq >= 0); - - old_tgt = GIC_DIST_TARGET(_gic_table[index].dist_hw_base, irq); - - old_tgt &= ~(0x0FFUL << ((irq % 4)*8)); - old_tgt |= cpumask << ((irq % 4)*8); - - GIC_DIST_TARGET(_gic_table[index].dist_hw_base, irq) = old_tgt; -} - -void arm_gic_umask(rt_uint32_t index, int irq) -{ - rt_uint32_t mask = 1 << (irq % 32); - - RT_ASSERT(index < ARM_GIC_MAX_NR); - - irq = irq - _gic_table[index].offset; - RT_ASSERT(irq >= 0); - - GIC_DIST_ENABLE_SET(_gic_table[index].dist_hw_base, irq) = mask; -} - -void arm_gic_dump_type(rt_uint32_t index) -{ - unsigned int gic_type; - - gic_type = GIC_DIST_TYPE(_gic_table[index].dist_hw_base); - rt_kprintf("GICv%d on %p, max IRQs: %d, %s security extension(%08x)\n", - (GIC_DIST_ICPIDR2(_gic_table[index].dist_hw_base) >> 4) & 0xf, - _gic_table[index].dist_hw_base, - _gic_max_irq, - gic_type & (1 << 10) ? "has" : "no", - gic_type); -} - -int arm_gic_dist_init(rt_uint32_t index, rt_uint32_t dist_base, int irq_start) -{ - unsigned int gic_type, i; - rt_uint32_t cpumask = 1 << 0; - - RT_ASSERT(index < ARM_GIC_MAX_NR); - - _gic_table[index].dist_hw_base = dist_base; - _gic_table[index].offset = irq_start; - - /* Find out how many interrupts are supported. */ - gic_type = GIC_DIST_TYPE(dist_base); - _gic_max_irq = ((gic_type & 0x1f) + 1) * 32; - - /* - * The GIC only supports up to 1020 interrupt sources. - * Limit this to either the architected maximum, or the - * platform maximum. - */ - if (_gic_max_irq > 1020) - _gic_max_irq = 1020; - if (_gic_max_irq > ARM_GIC_NR_IRQS) - _gic_max_irq = ARM_GIC_NR_IRQS; - - cpumask |= cpumask << 8; - cpumask |= cpumask << 16; - - GIC_DIST_CTRL(dist_base) = 0x0; - - /* Set all global interrupts to be level triggered, active low. */ - for (i = 32; i < _gic_max_irq; i += 16) - GIC_DIST_CONFIG(dist_base, i) = 0x0; - - /* Set all global interrupts to this CPU only. */ - for (i = 32; i < _gic_max_irq; i += 4) - GIC_DIST_TARGET(dist_base, i) = cpumask; - - /* Set priority on all interrupts. */ - for (i = 0; i < _gic_max_irq; i += 4) - GIC_DIST_PRI(dist_base, i) = 0xa0a0a0a0; - - /* Disable all interrupts. */ - for (i = 0; i < _gic_max_irq; i += 32) - GIC_DIST_ENABLE_CLEAR(dist_base, i) = 0xffffffff; - - /* Set the FIQEn bit, signal FIQ for IGROUP0. */ - GIC_DIST_CTRL(dist_base) = 0x01; - - return 0; -} - -int arm_gic_cpu_init(rt_uint32_t index, rt_uint32_t cpu_base) -{ - RT_ASSERT(index < ARM_GIC_MAX_NR); - - _gic_table[index].cpu_hw_base = cpu_base; - - GIC_CPU_PRIMASK(cpu_base) = 0xf0; - /* Enable CPU interrupt */ - GIC_CPU_CTRL(cpu_base) = 0x01; - - return 0; -} - -void arm_gic_set_group(rt_uint32_t index, int vector, int group) -{ - /* As for GICv2, there are only group0 and group1. */ - RT_ASSERT(group <= 1); - RT_ASSERT(vector < _gic_max_irq); - - if (group == 0) - { - GIC_DIST_IGROUP(_gic_table[index].dist_hw_base, - vector) &= ~(1 << (vector % 32)); - } - else if (group == 1) - { - GIC_DIST_IGROUP(_gic_table[index].dist_hw_base, - vector) |= (1 << (vector % 32)); - } -} - -void arm_gic_trigger(rt_uint32_t index, int target_cpu, int irq) -{ - unsigned int reg; - - RT_ASSERT(irq <= 15); - RT_ASSERT(target_cpu <= 255); - - reg = (target_cpu << 16) | irq; - GIC_DIST_SOFTINT(_gic_table[index].dist_hw_base) = reg; -} - -void arm_gic_clear_sgi(rt_uint32_t index, int target_cpu, int irq) -{ - RT_ASSERT(irq <= 15); - RT_ASSERT(target_cpu <= 255); - - GIC_DIST_CPENDSGI(_gic_table[index].dist_hw_base, irq) = target_cpu << (irq % 4); -} diff --git a/libcpu/arm/zynq7000/gic.h b/libcpu/arm/zynq7000/gic.h deleted file mode 100644 index 8fcdf05f6f..0000000000 --- a/libcpu/arm/zynq7000/gic.h +++ /dev/null @@ -1,31 +0,0 @@ -/* - * Copyright (c) 2006-2018, RT-Thread Development Team - * - * SPDX-License-Identifier: Apache-2.0 - * - * Change Logs: - * Date Author Notes - * 2013-07-20 Bernard first version - */ - -#ifndef __GIC_H__ -#define __GIC_H__ - -int arm_gic_dist_init(rt_uint32_t index, rt_uint32_t dist_base, int irq_start); -int arm_gic_cpu_init(rt_uint32_t index, rt_uint32_t cpu_base); - -void arm_gic_mask(rt_uint32_t index, int irq); -void arm_gic_umask(rt_uint32_t index, int irq); -void arm_gic_set_cpu(rt_uint32_t index, int irq, unsigned int cpumask); -void arm_gic_set_group(rt_uint32_t index, int vector, int group); - -int arm_gic_get_active_irq(rt_uint32_t index); -void arm_gic_ack(rt_uint32_t index, int irq); - -void arm_gic_trigger(rt_uint32_t index, int target_cpu, int irq); -void arm_gic_clear_sgi(rt_uint32_t index, int target_cpu, int irq); - -void arm_gic_dump_type(rt_uint32_t index); - -#endif - diff --git a/libcpu/arm/zynq7000/interrupt.c b/libcpu/arm/zynq7000/interrupt.c deleted file mode 100644 index 451785523a..0000000000 --- a/libcpu/arm/zynq7000/interrupt.c +++ /dev/null @@ -1,143 +0,0 @@ -/* - * COPYRIGHT (C) 2013-2014, Shanghai Real-Thread Technology Co., Ltd - * - * All rights reserved. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 2 of the License, or - * (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License along - * with this program; if not, write to the Free Software Foundation, Inc., - * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA. - */ - -#include <rthw.h> -#include <rtthread.h> -#include "zynq7000.h" -#include "cp15.h" -#include "gic.h" - -#define MAX_HANDLERS IRQ_Zynq7000_MAXNR - -extern volatile rt_uint8_t rt_interrupt_nest; - -/* exception and interrupt handler table */ -struct rt_irq_desc isr_table[MAX_HANDLERS]; -rt_uint32_t rt_interrupt_from_thread, rt_interrupt_to_thread; -rt_uint32_t rt_thread_switch_interrupt_flag; - -static void rt_hw_interrupt_handle(int vector, void *param) -{ - rt_kprintf("Unhandled interrupt %d occured!!!\n", vector); -} - -const unsigned int VECTOR_BASE = 0x00; -extern int system_vectors; - -static void rt_hw_vector_init(void) -{ - int sctrl; - unsigned int *src = (unsigned int *)&system_vectors; - - /* C12-C0 is only active when SCTLR.V = 0 */ - asm volatile ("mrc p15, #0, %0, c1, c0, #0" - :"=r" (sctrl)); - sctrl &= ~(1 << 13); - asm volatile ("mcr p15, #0, %0, c1, c0, #0" - : - :"r" (sctrl)); - - asm volatile ("mcr p15, #0, %0, c12, c0, #0" - : - :"r" (src)); -} - -/** - * This function will initialize hardware interrupt - */ -void rt_hw_interrupt_init(void) -{ - register rt_uint32_t idx; - - /* set vector table */ - rt_hw_vector_init(); - - /* init exceptions table */ - rt_memset(isr_table, 0x00, sizeof(isr_table)); - for (idx = 0; idx < MAX_HANDLERS; idx++) - { - isr_table[idx].handler = rt_hw_interrupt_handle; - } - - /* initialize ARM GIC */ - arm_gic_dist_init(0, Zynq7000_GIC_DIST_BASE, 0); - arm_gic_cpu_init(0, Zynq7000_GIC_CPU_BASE); - - /* init interrupt nest, and context in thread sp */ - rt_interrupt_nest = 0; - rt_interrupt_from_thread = 0; - rt_interrupt_to_thread = 0; - rt_thread_switch_interrupt_flag = 0; -} - -/** - * This function will mask a interrupt. - * @param vector the interrupt number - */ -void rt_hw_interrupt_mask(int vector) -{ - arm_gic_mask(0, vector); -} - -/** - * This function will un-mask a interrupt. - * @param vector the interrupt number - */ -void rt_hw_interrupt_umask(int vector) -{ - arm_gic_umask(0, vector); -} - -/** - * This function will install a interrupt service routine to a interrupt. - * @param vector the interrupt number - * @param new_handler the interrupt service routine to be installed - * @param old_handler the old interrupt service routine - */ -rt_isr_handler_t rt_hw_interrupt_install(int vector, rt_isr_handler_t handler, - void *param, const char *name) -{ - rt_isr_handler_t old_handler = RT_NULL; - - if (vector < MAX_HANDLERS) - { - old_handler = isr_table[vector].handler; - - if (handler != RT_NULL) - { -#ifdef RT_USING_INTERRUPT_INFO - rt_strncpy(isr_table[vector].name, name, RT_NAME_MAX); -#endif /* RT_USING_INTERRUPT_INFO */ - isr_table[vector].handler = handler; - isr_table[vector].param = param; - } - /* set the interrupt to this cpu */ - arm_gic_set_cpu(0, vector, 1 << rt_cpu_get_smp_id()); - } - - return old_handler; -} - -void rt_hw_interrupt_clear(int vector) -{ - /* SGI will be cleared automatically. */ - if (vector < 16) - return; -} diff --git a/libcpu/arm/zynq7000/interrupt.h b/libcpu/arm/zynq7000/interrupt.h deleted file mode 100644 index da266c42a2..0000000000 --- a/libcpu/arm/zynq7000/interrupt.h +++ /dev/null @@ -1,17 +0,0 @@ -/* - * Copyright (c) 2006-2018, RT-Thread Development Team - * - * SPDX-License-Identifier: Apache-2.0 - * - * Change Logs: - * Date Author Notes - * 2013-07-20 Bernard first version - */ - -#ifndef __INTERRUPT_H__ -#define __INTERRUPT_H__ - -void rt_hw_interrupt_clear(int vector); - -#endif /* end of include guard: __INTERRUPT_H__ */ - diff --git a/libcpu/arm/zynq7000/mmu.c b/libcpu/arm/zynq7000/mmu.c deleted file mode 100644 index 8674f9f60f..0000000000 --- a/libcpu/arm/zynq7000/mmu.c +++ /dev/null @@ -1,172 +0,0 @@ -/* - * Copyright (c) 2006-2018, RT-Thread Development Team - * - * SPDX-License-Identifier: Apache-2.0 - * - * Change Logs: - * Date Author Notes - * 2013-07-20 Bernard first version - */ - -#include <rtthread.h> -#include <rthw.h> -#include <board.h> - -#include "cp15.h" - -#define DESC_SEC (0x2) -#define CB (3<<2) //cache_on, write_back -#define CNB (2<<2) //cache_on, write_through -#define NCB (1<<2) //cache_off,WR_BUF on -#define NCNB (0<<2) //cache_off,WR_BUF off -#define AP_RW (3<<10) //supervisor=RW, user=RW -#define AP_RO (2<<10) //supervisor=RW, user=RO -#define XN (1<<4) //eXecute Never - -#define DOMAIN_FAULT (0x0) -#define DOMAIN_CHK (0x1) -#define DOMAIN_NOTCHK (0x3) -#define DOMAIN0 (0x0<<5) -#define DOMAIN1 (0x1<<5) - -#define DOMAIN0_ATTR (DOMAIN_CHK<<0) -#define DOMAIN1_ATTR (DOMAIN_FAULT<<2) - -/* Read/Write, cache, write back */ -#define RW_CB (AP_RW|DOMAIN0|CB|DESC_SEC) -/* Read/Write, cache, write through */ -#define RW_CNB (AP_RW|DOMAIN0|CNB|DESC_SEC) -/* Read/Write, device type */ -#define RW_NCB (AP_RW|DOMAIN0|NCB|DESC_SEC) -/* Read/Write strongly ordered type */ -#define RW_NCNB (AP_RW|DOMAIN0|NCNB|DESC_SEC) -/* Read/Write without cache and write buffer, no execute */ -#define RW_NCNBXN (AP_RW|DOMAIN0|NCNB|DESC_SEC|XN) -/* Read/Write without cache and write buffer */ -#define RW_FAULT (AP_RW|DOMAIN1|NCNB|DESC_SEC) - -void rt_hw_cpu_dump_page_table(rt_uint32_t *ptb) -{ - int i; - int fcnt = 0; - - rt_kprintf("page table@%p\n", ptb); - for (i = 0; i < 1024*4; i++) - { - rt_uint32_t pte1 = ptb[i]; - if ((pte1 & 0x3) == 0) - { - rt_kprintf("%03x: ", i); - fcnt++; - if (fcnt == 16) - { - rt_kprintf("fault\n"); - fcnt = 0; - } - continue; - } - if (fcnt != 0) - { - rt_kprintf("fault\n"); - fcnt = 0; - } - - rt_kprintf("%03x: %08x: ", i, pte1); - if ((pte1 & 0x3) == 0x3) - { - rt_kprintf("LPAE\n"); - } - else if ((pte1 & 0x3) == 0x1) - { - rt_kprintf("pte,ns:%d,domain:%d\n", - (pte1 >> 3) & 0x1, (pte1 >> 5) & 0xf); - /* - *rt_hw_cpu_dump_page_table_2nd((void*)((pte1 & 0xfffffc000) - * - 0x80000000 + 0xC0000000)); - */ - } - else if (pte1 & (1 << 18)) - { - rt_kprintf("super section,ns:%d,ap:%x,xn:%d,texcb:%02x\n", - (pte1 >> 19) & 0x1, - ((pte1 >> 13) | (pte1 >> 10))& 0xf, - (pte1 >> 4) & 0x1, - ((pte1 >> 10) | (pte1 >> 2)) & 0x1f); - } - else - { - rt_kprintf("section,ns:%d,ap:%x," - "xn:%d,texcb:%02x,domain:%d\n", - (pte1 >> 19) & 0x1, - ((pte1 >> 13) | (pte1 >> 10))& 0xf, - (pte1 >> 4) & 0x1, - (((pte1 & (0x7 << 12)) >> 10) | - ((pte1 & 0x0c) >> 2)) & 0x1f, - (pte1 >> 5) & 0xf); - } - } -} - -/* level1 page table, each entry for 1MB memory. */ -/* MMUTable is the name used by codes of Xilinx */ -volatile unsigned long MMUTable[4*1024] RT_SECTION("mmu_tbl") __attribute__((aligned(16*1024))); -void rt_hw_mmu_setmtt(rt_uint32_t vaddrStart, - rt_uint32_t vaddrEnd, - rt_uint32_t paddrStart, - rt_uint32_t attr) -{ - volatile rt_uint32_t *pTT; - volatile int i, nSec; - pTT = (rt_uint32_t *)MMUTable + (vaddrStart >> 20); - nSec = (vaddrEnd >> 20) - (vaddrStart >> 20); - for(i = 0; i <= nSec; i++) - { - *pTT = attr | (((paddrStart >> 20) + i) << 20); - pTT++; - } -} - -unsigned long rt_hw_set_domain_register(unsigned long domain_val) -{ - unsigned long old_domain; - - asm volatile ("mrc p15, 0, %0, c3, c0\n" : "=r" (old_domain)); - asm volatile ("mcr p15, 0, %0, c3, c0\n" : :"r" (domain_val) : "memory"); - - return old_domain; -} - -void rt_hw_mmu_init(void) -{ - extern rt_uint32_t __text_start; - rt_hw_cpu_dcache_disable(); - rt_hw_cpu_icache_disable(); - rt_cpu_mmu_disable(); - - /* set page table */ - /* no access to the memory below .text */ - /* 128M cached DDR memory */ - rt_hw_mmu_setmtt((rt_uint32_t)&__text_start, 0x20000000-1, - 0x1ff00000, RW_CB); - /* PL region */ - rt_hw_mmu_setmtt(0x40000000, 0xBFFFFFFF, 0x40000000, RW_NCNBXN); - /* IOP registers */ - rt_hw_mmu_setmtt(0xE0000000, 0xE02FFFFF, 0xE0000000, RW_NCNBXN); - /* no access to the SMC memory(enable it if you want) */ - /* SLCR, PS and CPU private registers, note we map more memory space as the - * entry is 1MB in size. */ - rt_hw_mmu_setmtt(0xF8000000, 0xF8FFFFFF, 0xF8000000, RW_NCNBXN); - - /*rt_hw_cpu_dump_page_table(MMUTable);*/ - - /* become clients for all domains */ - rt_hw_set_domain_register(0x55555555); - - rt_cpu_tlb_set(MMUTable); - - rt_cpu_mmu_enable(); - - rt_hw_cpu_icache_enable(); - rt_hw_cpu_dcache_enable(); -} - diff --git a/libcpu/arm/zynq7000/stack.c b/libcpu/arm/zynq7000/stack.c deleted file mode 100644 index b38dd160f7..0000000000 --- a/libcpu/arm/zynq7000/stack.c +++ /dev/null @@ -1,58 +0,0 @@ -/* - * Copyright (c) 2006-2018, RT-Thread Development Team - * - * SPDX-License-Identifier: Apache-2.0 - * - * Change Logs: - * Date Author Notes - * 2011-09-23 Bernard the first version - * 2011-10-05 Bernard add thumb mode - * 2013-07-15 Bernard add Cortex-A8 support. - */ -#include <rtthread.h> -#include "zynq7000.h" - -/** - * This function will initialize thread stack - * - * @param tentry the entry of thread - * @param parameter the parameter of entry - * @param stack_addr the beginning stack address - * @param texit the function will be called when thread exit - * - * @return stack address - */ -rt_uint8_t *rt_hw_stack_init(void *tentry, void *parameter, - rt_uint8_t *stack_addr, void *texit) -{ - rt_uint32_t *stk; - - stack_addr += sizeof(rt_uint32_t); - stack_addr = (rt_uint8_t *)RT_ALIGN_DOWN((rt_uint32_t)stack_addr, 8); - stk = (rt_uint32_t *)stack_addr; - *(--stk) = (rt_uint32_t)tentry; /* entry point */ - *(--stk) = (rt_uint32_t)texit; /* lr */ - *(--stk) = 0xdeadbeef; /* r12 */ - *(--stk) = 0xdeadbeef; /* r11 */ - *(--stk) = 0xdeadbeef; /* r10 */ - *(--stk) = 0xdeadbeef; /* r9 */ - *(--stk) = 0xdeadbeef; /* r8 */ - *(--stk) = 0xdeadbeef; /* r7 */ - *(--stk) = 0xdeadbeef; /* r6 */ - *(--stk) = 0xdeadbeef; /* r5 */ - *(--stk) = 0xdeadbeef; /* r4 */ - *(--stk) = 0xdeadbeef; /* r3 */ - *(--stk) = 0xdeadbeef; /* r2 */ - *(--stk) = 0xdeadbeef; /* r1 */ - *(--stk) = (rt_uint32_t)parameter; /* r0 : argument */ - - /* cpsr */ - if ((rt_uint32_t)tentry & 0x01) - *(--stk) = SVCMODE | 0x20; /* thumb mode */ - else - *(--stk) = SVCMODE; /* arm mode */ - - /* return task's current stack address */ - return (rt_uint8_t *)stk; -} - diff --git a/libcpu/arm/zynq7000/start_gcc.S b/libcpu/arm/zynq7000/start_gcc.S deleted file mode 100644 index 18056f0ad9..0000000000 --- a/libcpu/arm/zynq7000/start_gcc.S +++ /dev/null @@ -1,241 +0,0 @@ -/* - * Copyright (c) 2006-2018, RT-Thread Development Team - * - * SPDX-License-Identifier: Apache-2.0 - * - * Change Logs: - * Date Author Notes - * 2013-07-05 Bernard the first version - */ - -.equ Mode_USR, 0x10 -.equ Mode_FIQ, 0x11 -.equ Mode_IRQ, 0x12 -.equ Mode_SVC, 0x13 -.equ Mode_ABT, 0x17 -.equ Mode_UND, 0x1B -.equ Mode_SYS, 0x1F - -.equ I_Bit, 0x80 @ when I bit is set, IRQ is disabled -.equ F_Bit, 0x40 @ when F bit is set, FIQ is disabled - -.equ UND_Stack_Size, 0x00000000 -.equ SVC_Stack_Size, 0x00000000 -.equ ABT_Stack_Size, 0x00000000 -.equ FIQ_Stack_Size, 0x00000100 -.equ IRQ_Stack_Size, 0x00000100 -.equ USR_Stack_Size, 0x00000000 - -#define ISR_Stack_Size (UND_Stack_Size + SVC_Stack_Size + ABT_Stack_Size + \ - FIQ_Stack_Size + IRQ_Stack_Size) - -/* stack */ -.globl stack_start -.globl stack_top - -.align 3 -.bss -stack_start: -.rept ISR_Stack_Size -.long 0 -.endr -stack_top: - -.text -/* reset entry */ -.globl _reset -_reset: - /* invalidate SCU */ - ldr r7, =0xF8F0000C - ldr r6, =0xFFFF - str r6, [r7] - - /* disable MMU */ - mrc p15, 0, r0, c1, c0, 0 /* read CP15 register 1 */ - bic r0, r0, #0x1 /* clear bit 0 */ - mcr p15, 0, r0, c1, c0, 0 /* write value back */ - - /* set the cpu to SVC32 mode and disable interrupt */ - mrs r0, cpsr - bic r0, r0, #0x1f - orr r0, r0, #0x13 - msr cpsr_c, r0 - - /* setup stack */ - bl stack_setup - - /* clear .bss */ - mov r0,#0 /* get a zero */ - ldr r1,=__bss_start /* bss start */ - ldr r2,=__bss_end /* bss end */ - -bss_loop: - cmp r1,r2 /* check if data to clear */ - strlo r0,[r1],#4 /* clear 4 bytes */ - blo bss_loop /* loop until done */ - - /* call C++ constructors of global objects */ - ldr r0, =__ctors_start__ - ldr r1, =__ctors_end__ - -ctor_loop: - cmp r0, r1 - beq ctor_end - ldr r2, [r0], #4 - stmfd sp!, {r0-r1} - mov lr, pc - bx r2 - ldmfd sp!, {r0-r1} - b ctor_loop -ctor_end: - - /* start RT-Thread Kernel */ - ldr pc, _rtthread_startup - -_rtthread_startup: - .word rtthread_startup - -stack_setup: - ldr r0, =stack_top - - @ Set the startup stack for svc - mov sp, r0 - - @ Enter Undefined Instruction Mode and set its Stack Pointer - msr cpsr_c, #Mode_UND|I_Bit|F_Bit - mov sp, r0 - sub r0, r0, #UND_Stack_Size - - @ Enter Abort Mode and set its Stack Pointer - msr cpsr_c, #Mode_ABT|I_Bit|F_Bit - mov sp, r0 - sub r0, r0, #ABT_Stack_Size - - @ Enter FIQ Mode and set its Stack Pointer - msr cpsr_c, #Mode_FIQ|I_Bit|F_Bit - mov sp, r0 - sub r0, r0, #FIQ_Stack_Size - - @ Enter IRQ Mode and set its Stack Pointer - msr cpsr_c, #Mode_IRQ|I_Bit|F_Bit - mov sp, r0 - sub r0, r0, #IRQ_Stack_Size - - @ Switch back to SVC - msr cpsr_c, #Mode_SVC|I_Bit|F_Bit - - bx lr - -.section .text.isr, "ax" -/* exception handlers: undef, swi, padt, dabt, resv, irq, fiq */ - .align 5 -.globl vector_fiq -vector_fiq: - stmfd sp!,{r0-r7,lr} - bl rt_hw_trap_fiq - ldmfd sp!,{r0-r7,lr} - subs pc,lr,#4 - -.globl rt_interrupt_enter -.globl rt_interrupt_leave -.globl rt_thread_switch_interrupt_flag -.globl rt_interrupt_from_thread -.globl rt_interrupt_to_thread - - .align 5 -.globl vector_irq -vector_irq: - stmfd sp!, {r0-r12,lr} - bl rt_interrupt_enter - bl rt_hw_trap_irq - bl rt_interrupt_leave - - @ if rt_thread_switch_interrupt_flag set, jump to - @ rt_hw_context_switch_interrupt_do and don't return - ldr r0, =rt_thread_switch_interrupt_flag - ldr r1, [r0] - cmp r1, #1 - beq rt_hw_context_switch_interrupt_do - - ldmfd sp!, {r0-r12,lr} - subs pc, lr, #4 - -rt_hw_context_switch_interrupt_do: - mov r1, #0 @ clear flag - str r1, [r0] - - mov r1, sp @ r1 point to {r0-r3} in stack - add sp, sp, #4*4 - ldmfd sp!, {r4-r12,lr}@ reload saved registers - mrs r0, spsr @ get cpsr of interrupt thread - sub r2, lr, #4 @ save old task's pc to r2 - - @ Switch to SVC mode with no interrupt. - msr cpsr_c, #I_Bit|F_Bit|Mode_SVC - - stmfd sp!, {r2} @ push old task's pc - stmfd sp!, {r4-r12,lr}@ push old task's lr,r12-r4 - ldmfd r1, {r1-r4} @ restore r0-r3 of the interrupt thread - stmfd sp!, {r1-r4} @ push old task's r0-r3 - stmfd sp!, {r0} @ push old task's cpsr - - ldr r4, =rt_interrupt_from_thread - ldr r5, [r4] - str sp, [r5] @ store sp in preempted tasks's TCB - - ldr r6, =rt_interrupt_to_thread - ldr r7, [r6] - ldr sp, [r7] @ get new task's stack pointer - - ldmfd sp!, {r4} @ pop new task's cpsr to spsr - msr spsr_cxsf, r4 - - ldmfd sp!, {r0-r12,lr,pc}^ @ pop new task's r0-r12,lr & pc, copy spsr to cpsr - - -.macro push_svc_reg - sub sp, sp, #17 * 4 @/* Sizeof(struct rt_hw_exp_stack) */ - stmia sp, {r0 - r12} @/* Calling r0-r12 */ - mov r0, sp - mrs r6, spsr @/* Save CPSR */ - str lr, [r0, #15*4] @/* Push PC */ - str r6, [r0, #16*4] @/* Push CPSR */ - cps #Mode_SVC - str sp, [r0, #13*4] @/* Save calling SP */ - str lr, [r0, #14*4] @/* Save calling PC */ -.endm - - .align 5 - .globl vector_swi -vector_swi: - push_svc_reg - bl rt_hw_trap_swi - b . - - .align 5 - .globl vector_undef -vector_undef: - push_svc_reg - bl rt_hw_trap_undef - b . - - .align 5 - .globl vector_pabt -vector_pabt: - push_svc_reg - bl rt_hw_trap_pabt - b . - - .align 5 - .globl vector_dabt -vector_dabt: - push_svc_reg - bl rt_hw_trap_dabt - b . - - .align 5 - .globl vector_resv -vector_resv: - push_svc_reg - bl rt_hw_trap_resv - b . diff --git a/libcpu/arm/zynq7000/trap.c b/libcpu/arm/zynq7000/trap.c deleted file mode 100644 index 6243ea82b4..0000000000 --- a/libcpu/arm/zynq7000/trap.c +++ /dev/null @@ -1,175 +0,0 @@ -/* - * Copyright (c) 2006-2018, RT-Thread Development Team - * - * SPDX-License-Identifier: Apache-2.0 - * - * Change Logs: - * Date Author Notes - * 2013-07-20 Bernard first version - */ - -#include <rtthread.h> -#include <rthw.h> - -#include "zynq7000.h" -#include "gic.h" - -extern struct rt_thread *rt_current_thread; -#ifdef RT_USING_FINSH -extern long list_thread(void); -#endif - -/** - * this function will show registers of CPU - * - * @param regs the registers point - */ -void rt_hw_show_register (struct rt_hw_exp_stack *regs) -{ - rt_kprintf("Execption:\n"); - rt_kprintf("r00:0x%08x r01:0x%08x r02:0x%08x r03:0x%08x\n", regs->r0, regs->r1, regs->r2, regs->r3); - rt_kprintf("r04:0x%08x r05:0x%08x r06:0x%08x r07:0x%08x\n", regs->r4, regs->r5, regs->r6, regs->r7); - rt_kprintf("r08:0x%08x r09:0x%08x r10:0x%08x\n", regs->r8, regs->r9, regs->r10); - rt_kprintf("fp :0x%08x ip :0x%08x\n", regs->fp, regs->ip); - rt_kprintf("sp :0x%08x lr :0x%08x pc :0x%08x\n", regs->sp, regs->lr, regs->pc); - rt_kprintf("cpsr:0x%08x\n", regs->cpsr); -} - -/** - * When comes across an instruction which it cannot handle, - * it takes the undefined instruction trap. - * - * @param regs system registers - * - * @note never invoke this function in application - */ -void rt_hw_trap_undef(struct rt_hw_exp_stack *regs) -{ - rt_kprintf("undefined instruction:\n"); - rt_hw_show_register(regs); -#ifdef RT_USING_FINSH - list_thread(); -#endif - rt_hw_cpu_shutdown(); -} - -/** - * The software interrupt instruction (SWI) is used for entering - * Supervisor mode, usually to request a particular supervisor - * function. - * - * @param regs system registers - * - * @note never invoke this function in application - */ -void rt_hw_trap_swi(struct rt_hw_exp_stack *regs) -{ - rt_kprintf("software interrupt:\n"); - rt_hw_show_register(regs); -#ifdef RT_USING_FINSH - list_thread(); -#endif - rt_hw_cpu_shutdown(); -} - -/** - * An abort indicates that the current memory access cannot be completed, - * which occurs during an instruction prefetch. - * - * @param regs system registers - * - * @note never invoke this function in application - */ -void rt_hw_trap_pabt(struct rt_hw_exp_stack *regs) -{ - rt_kprintf("prefetch abort:\n"); - rt_hw_show_register(regs); -#ifdef RT_USING_FINSH - list_thread(); -#endif - rt_hw_cpu_shutdown(); -} - -/** - * An abort indicates that the current memory access cannot be completed, - * which occurs during a data access. - * - * @param regs system registers - * - * @note never invoke this function in application - */ -void rt_hw_trap_dabt(struct rt_hw_exp_stack *regs) -{ - rt_kprintf("data abort:"); - rt_hw_show_register(regs); -#ifdef RT_USING_FINSH - list_thread(); -#endif - rt_hw_cpu_shutdown(); -} - -/** - * Normally, system will never reach here - * - * @param regs system registers - * - * @note never invoke this function in application - */ -void rt_hw_trap_resv(struct rt_hw_exp_stack *regs) -{ - rt_kprintf("reserved trap:\n"); - rt_hw_show_register(regs); -#ifdef RT_USING_FINSH - list_thread(); -#endif - rt_hw_cpu_shutdown(); -} - -#define GIC_ACK_INTID_MASK 0x000003ff - -void rt_hw_trap_irq() -{ - void *param; - unsigned long ir; - unsigned long fullir; - rt_isr_handler_t isr_func; - extern struct rt_irq_desc isr_table[]; - - fullir = arm_gic_get_active_irq(0); - ir = fullir & GIC_ACK_INTID_MASK; - - /* get interrupt service routine */ - isr_func = isr_table[ir].handler; - if (isr_func) - { - param = isr_table[ir].param; - /* turn to interrupt service routine */ - isr_func(ir, param); - } - - /* end of interrupt */ - arm_gic_ack(0, fullir); -} - -void rt_hw_trap_fiq() -{ - void *param; - unsigned long ir; - unsigned long fullir; - rt_isr_handler_t isr_func; - extern struct rt_irq_desc isr_table[]; - - fullir = arm_gic_get_active_irq(0); - ir = fullir & GIC_ACK_INTID_MASK; - - /* get interrupt service routine */ - isr_func = isr_table[ir].handler; - param = isr_table[ir].param; - - /* turn to interrupt service routine */ - isr_func(ir, param); - - /* end of interrupt */ - arm_gic_ack(0, fullir); -} - diff --git a/libcpu/arm/zynq7000/vector_gcc.S b/libcpu/arm/zynq7000/vector_gcc.S deleted file mode 100644 index 60d3c6cf1d..0000000000 --- a/libcpu/arm/zynq7000/vector_gcc.S +++ /dev/null @@ -1,51 +0,0 @@ -/* - * Copyright (c) 2006-2018, RT-Thread Development Team - * - * SPDX-License-Identifier: Apache-2.0 - * - * Change Logs: - * Date Author Notes - * 2013-07-05 Bernard the first version - */ - -.section .vectors, "ax" -.code 32 - -.globl system_vectors -system_vectors: - ldr pc, _vector_reset - ldr pc, _vector_undef - ldr pc, _vector_swi - ldr pc, _vector_pabt - ldr pc, _vector_dabt - ldr pc, _vector_resv - ldr pc, _vector_irq - ldr pc, _vector_fiq - -.globl _reset -.globl vector_undef -.globl vector_swi -.globl vector_pabt -.globl vector_dabt -.globl vector_resv -.globl vector_irq -.globl vector_fiq - -_vector_reset: - .word _reset -_vector_undef: - .word vector_undef -_vector_swi: - .word vector_swi -_vector_pabt: - .word vector_pabt -_vector_dabt: - .word vector_dabt -_vector_resv: - .word vector_resv -_vector_irq: - .word vector_irq -_vector_fiq: - .word vector_fiq - -.balignl 16,0xdeadbeef diff --git a/libcpu/arm/zynqmp-r5/armv7.h b/libcpu/arm/zynqmp-r5/armv7.h index 4c34d7da8b..c70d210709 100644 --- a/libcpu/arm/zynqmp-r5/armv7.h +++ b/libcpu/arm/zynqmp-r5/armv7.h @@ -1,23 +1,10 @@ #ifndef __ARMV7_H__ #define __ARMV7_H__ /* - * COPYRIGHT (C) 2013-2014, Shanghai Real-Thread Technology Co., Ltd + * Copyright (c) 2006-2021, RT-Thread Development Team * - * All rights reserved. + * SPDX-License-Identifier: Apache-2.0 * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 2 of the License, or - * (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License along - * with this program; if not, write to the Free Software Foundation, Inc., - * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA. */ #ifndef VFP_DATA_NR @@ -27,23 +14,23 @@ /* the exception stack without VFP registers */ struct rt_hw_exp_stack { - unsigned long r0; - unsigned long r1; - unsigned long r2; - unsigned long r3; - unsigned long r4; - unsigned long r5; - unsigned long r6; - unsigned long r7; - unsigned long r8; - unsigned long r9; - unsigned long r10; - unsigned long fp; - unsigned long ip; - unsigned long sp; - unsigned long lr; - unsigned long pc; - unsigned long cpsr; + unsigned long r0; + unsigned long r1; + unsigned long r2; + unsigned long r3; + unsigned long r4; + unsigned long r5; + unsigned long r6; + unsigned long r7; + unsigned long r8; + unsigned long r9; + unsigned long r10; + unsigned long fp; + unsigned long ip; + unsigned long sp; + unsigned long lr; + unsigned long pc; + unsigned long cpsr; }; #define USERMODE 0x10 diff --git a/libcpu/arm/zynqmp-r5/cache.c b/libcpu/arm/zynqmp-r5/cache.c index aa8517e254..d6e7cd2d6d 100644 --- a/libcpu/arm/zynqmp-r5/cache.c +++ b/libcpu/arm/zynqmp-r5/cache.c @@ -1,11 +1,11 @@ /* - * Copyright (c) 2006-2018, RT-Thread Development Team + * Copyright (c) 2006-2021, RT-Thread Development Team * * SPDX-License-Identifier: Apache-2.0 * * Change Logs: * Date Author Notes - * 2020-03-19 WangHuachen first version + * 2020-03-19 WangHuachen first version */ #include <rthw.h> #include <rtdef.h> @@ -13,154 +13,154 @@ #include "xpseudo_asm_gcc.h" #include "xreg_cortexr5.h" -#define IRQ_FIQ_MASK 0xC0 /* Mask IRQ and FIQ interrupts in cpsr */ +#define IRQ_FIQ_MASK 0xC0 /* Mask IRQ and FIQ interrupts in cpsr */ typedef intptr_t INTPTR; typedef rt_uint32_t u32; #if defined (__GNUC__) #define asm_inval_dc_line_mva_poc(param) __asm__ __volatile__("mcr " \ - XREG_CP15_INVAL_DC_LINE_MVA_POC :: "r" (param)) + XREG_CP15_INVAL_DC_LINE_MVA_POC :: "r" (param)) #define asm_clean_inval_dc_line_sw(param) __asm__ __volatile__("mcr " \ - XREG_CP15_CLEAN_INVAL_DC_LINE_SW :: "r" (param)) + XREG_CP15_CLEAN_INVAL_DC_LINE_SW :: "r" (param)) #define asm_clean_inval_dc_line_mva_poc(param) __asm__ __volatile__("mcr " \ - XREG_CP15_CLEAN_INVAL_DC_LINE_MVA_POC :: "r" (param)) + XREG_CP15_CLEAN_INVAL_DC_LINE_MVA_POC :: "r" (param)) #define asm_inval_ic_line_mva_pou(param) __asm__ __volatile__("mcr " \ - XREG_CP15_INVAL_IC_LINE_MVA_POU :: "r" (param)) + XREG_CP15_INVAL_IC_LINE_MVA_POU :: "r" (param)) #elif defined (__ICCARM__) #define asm_inval_dc_line_mva_poc(param) __asm volatile("mcr " \ - XREG_CP15_INVAL_DC_LINE_MVA_POC :: "r" (param)) + XREG_CP15_INVAL_DC_LINE_MVA_POC :: "r" (param)) #define asm_clean_inval_dc_line_sw(param) __asm volatile("mcr " \ - XREG_CP15_CLEAN_INVAL_DC_LINE_SW :: "r" (param)) + XREG_CP15_CLEAN_INVAL_DC_LINE_SW :: "r" (param)) #define asm_clean_inval_dc_line_mva_poc(param) __asm volatile("mcr " \ - XREG_CP15_CLEAN_INVAL_DC_LINE_MVA_POC :: "r" (param)) + XREG_CP15_CLEAN_INVAL_DC_LINE_MVA_POC :: "r" (param)) #define asm_inval_ic_line_mva_pou(param) __asm volatile("mcr " \ - XREG_CP15_INVAL_IC_LINE_MVA_POU :: "r" (param)) + XREG_CP15_INVAL_IC_LINE_MVA_POU :: "r" (param)) #endif void Xil_ICacheInvalidateRange(INTPTR adr, u32 len) { - u32 LocalAddr = adr; - const u32 cacheline = 32U; - u32 end; - u32 currmask; + u32 LocalAddr = adr; + const u32 cacheline = 32U; + u32 end; + u32 currmask; - currmask = mfcpsr(); - mtcpsr(currmask | IRQ_FIQ_MASK); - if (len != 0x00000000U) { - /* Back the starting address up to the start of a cache line - * perform cache operations until adr+len - */ - end = LocalAddr + len; - LocalAddr = LocalAddr & ~(cacheline - 1U); + currmask = mfcpsr(); + mtcpsr(currmask | IRQ_FIQ_MASK); + if (len != 0x00000000U) { + /* Back the starting address up to the start of a cache line + * perform cache operations until adr+len + */ + end = LocalAddr + len; + LocalAddr = LocalAddr & ~(cacheline - 1U); - /* Select cache L0 I-cache in CSSR */ - mtcp(XREG_CP15_CACHE_SIZE_SEL, 1U); + /* Select cache L0 I-cache in CSSR */ + mtcp(XREG_CP15_CACHE_SIZE_SEL, 1U); - while (LocalAddr < end) { + while (LocalAddr < end) { - /* Invalidate L1 I-cache line */ - asm_inval_ic_line_mva_pou(LocalAddr); + /* Invalidate L1 I-cache line */ + asm_inval_ic_line_mva_pou(LocalAddr); - LocalAddr += cacheline; - } - } + LocalAddr += cacheline; + } + } - /* Wait for invalidate to complete */ - dsb(); - mtcpsr(currmask); + /* Wait for invalidate to complete */ + dsb(); + mtcpsr(currmask); } void Xil_DCacheFlushLine(INTPTR adr) { - u32 currmask; + u32 currmask; - currmask = mfcpsr(); - mtcpsr(currmask | IRQ_FIQ_MASK); + currmask = mfcpsr(); + mtcpsr(currmask | IRQ_FIQ_MASK); - mtcp(XREG_CP15_CACHE_SIZE_SEL, 0); + mtcp(XREG_CP15_CACHE_SIZE_SEL, 0); - mtcp(XREG_CP15_CLEAN_INVAL_DC_LINE_MVA_POC, (adr & (~0x1F))); + mtcp(XREG_CP15_CLEAN_INVAL_DC_LINE_MVA_POC, (adr & (~0x1F))); - /* Wait for flush to complete */ - dsb(); - mtcpsr(currmask); + /* Wait for flush to complete */ + dsb(); + mtcpsr(currmask); } void Xil_DCacheInvalidateRange(INTPTR adr, u32 len) { - const u32 cacheline = 32U; - u32 end; - u32 tempadr = adr; - u32 tempend; - u32 currmask; + const u32 cacheline = 32U; + u32 end; + u32 tempadr = adr; + u32 tempend; + u32 currmask; - currmask = mfcpsr(); - mtcpsr(currmask | IRQ_FIQ_MASK); + currmask = mfcpsr(); + mtcpsr(currmask | IRQ_FIQ_MASK); - if (len != 0U) { - end = tempadr + len; - tempend = end; - /* Select L1 Data cache in CSSR */ - mtcp(XREG_CP15_CACHE_SIZE_SEL, 0U); + if (len != 0U) { + end = tempadr + len; + tempend = end; + /* Select L1 Data cache in CSSR */ + mtcp(XREG_CP15_CACHE_SIZE_SEL, 0U); - if ((tempadr & (cacheline-1U)) != 0U) { - tempadr &= (~(cacheline - 1U)); + if ((tempadr & (cacheline-1U)) != 0U) { + tempadr &= (~(cacheline - 1U)); - Xil_DCacheFlushLine(tempadr); - } - if ((tempend & (cacheline-1U)) != 0U) { - tempend &= (~(cacheline - 1U)); + Xil_DCacheFlushLine(tempadr); + } + if ((tempend & (cacheline-1U)) != 0U) { + tempend &= (~(cacheline - 1U)); - Xil_DCacheFlushLine(tempend); - } + Xil_DCacheFlushLine(tempend); + } - while (tempadr < tempend) { + while (tempadr < tempend) { - /* Invalidate Data cache line */ - asm_inval_dc_line_mva_poc(tempadr); + /* Invalidate Data cache line */ + asm_inval_dc_line_mva_poc(tempadr); - tempadr += cacheline; - } - } + tempadr += cacheline; + } + } - dsb(); - mtcpsr(currmask); + dsb(); + mtcpsr(currmask); } void Xil_DCacheFlushRange(INTPTR adr, u32 len) { - u32 LocalAddr = adr; - const u32 cacheline = 32U; - u32 end; - u32 currmask; + u32 LocalAddr = adr; + const u32 cacheline = 32U; + u32 end; + u32 currmask; - currmask = mfcpsr(); - mtcpsr(currmask | IRQ_FIQ_MASK); + currmask = mfcpsr(); + mtcpsr(currmask | IRQ_FIQ_MASK); - if (len != 0x00000000U) { - /* Back the starting address up to the start of a cache line - * perform cache operations until adr+len - */ - end = LocalAddr + len; - LocalAddr &= ~(cacheline - 1U); + if (len != 0x00000000U) { + /* Back the starting address up to the start of a cache line + * perform cache operations until adr+len + */ + end = LocalAddr + len; + LocalAddr &= ~(cacheline - 1U); - while (LocalAddr < end) { - /* Flush Data cache line */ - asm_clean_inval_dc_line_mva_poc(LocalAddr); + while (LocalAddr < end) { + /* Flush Data cache line */ + asm_clean_inval_dc_line_mva_poc(LocalAddr); - LocalAddr += cacheline; - } - } - dsb(); - mtcpsr(currmask); + LocalAddr += cacheline; + } + } + dsb(); + mtcpsr(currmask); } void rt_hw_cpu_icache_ops(int ops, void *addr, int size) @@ -179,22 +179,22 @@ void rt_hw_cpu_dcache_ops(int ops, void *addr, int size) rt_base_t rt_hw_cpu_icache_status(void) { - register u32 CtrlReg; + register u32 CtrlReg; #if defined (__GNUC__) - CtrlReg = mfcp(XREG_CP15_SYS_CONTROL); + CtrlReg = mfcp(XREG_CP15_SYS_CONTROL); #elif defined (__ICCARM__) - mfcp(XREG_CP15_SYS_CONTROL,CtrlReg); + mfcp(XREG_CP15_SYS_CONTROL,CtrlReg); #endif - return CtrlReg & XREG_CP15_CONTROL_I_BIT; + return CtrlReg & XREG_CP15_CONTROL_I_BIT; } rt_base_t rt_hw_cpu_dcache_status(void) { - register u32 CtrlReg; + register u32 CtrlReg; #if defined (__GNUC__) - CtrlReg = mfcp(XREG_CP15_SYS_CONTROL); + CtrlReg = mfcp(XREG_CP15_SYS_CONTROL); #elif defined (__ICCARM__) - mfcp(XREG_CP15_SYS_CONTROL,CtrlReg); + mfcp(XREG_CP15_SYS_CONTROL,CtrlReg); #endif - return CtrlReg & XREG_CP15_CONTROL_C_BIT; + return CtrlReg & XREG_CP15_CONTROL_C_BIT; } diff --git a/libcpu/arm/zynqmp-r5/cpu.c b/libcpu/arm/zynqmp-r5/cpu.c index a2e3b85dc7..d0f1b0204c 100644 --- a/libcpu/arm/zynqmp-r5/cpu.c +++ b/libcpu/arm/zynqmp-r5/cpu.c @@ -1,11 +1,11 @@ /* - * Copyright (c) 2006-2018, RT-Thread Development Team + * Copyright (c) 2006-2021, RT-Thread Development Team * * SPDX-License-Identifier: Apache-2.0 * * Change Logs: * Date Author Notes - * 2020-03-19 WangHuachen first version + * 2020-03-19 WangHuachen first version */ #include <rthw.h> diff --git a/libcpu/arm/zynqmp-r5/gic.c b/libcpu/arm/zynqmp-r5/gic.c index 3acefbc9bf..67360d93ce 100644 --- a/libcpu/arm/zynqmp-r5/gic.c +++ b/libcpu/arm/zynqmp-r5/gic.c @@ -1,18 +1,18 @@ /* - * Copyright (c) 2006-2018, RT-Thread Development Team + * Copyright (c) 2006-2021, RT-Thread Development Team * * SPDX-License-Identifier: Apache-2.0 * * Change Logs: * Date Author Notes - * 2020-03-19 WangHuachen first version + * 2020-03-19 WangHuachen first version */ #include <rtthread.h> #include "board.h" #include "gic.h" -/* ZynqMP-RPU uses the Arm PL-390 generic interrupt controller that is +/* ZynqMP-RPU uses the Arm PL-390 generic interrupt controller that is * compliant to the GICv1 architecture specification. */ struct arm_gic @@ -39,12 +39,12 @@ static struct arm_gic _gic_table[ARM_GIC_MAX_NR]; #define GIC_DIST_ENABLE_SET(hw_base, n) __REG32((hw_base) + 0x100 + ((n)/32) * 4) #define GIC_DIST_ENABLE_CLEAR(hw_base, n) __REG32((hw_base) + 0x180 + ((n)/32) * 4) #define GIC_DIST_PENDING_SET(hw_base, n) __REG32((hw_base) + 0x200 + ((n)/32) * 4) -#define GIC_DIST_PENDING_CLEAR(hw_base, n) __REG32((hw_base) + 0x280 + ((n)/32) * 4) +#define GIC_DIST_PENDING_CLEAR(hw_base, n) __REG32((hw_base) + 0x280 + ((n)/32) * 4) #define GIC_DIST_ACTIVE_SET(hw_base, n) __REG32((hw_base) + 0x300 + ((n)/32) * 4) #define GIC_DIST_PRI(hw_base, n) __REG32((hw_base) + 0x400 + ((n)/4) * 4) #define GIC_DIST_TARGET(hw_base, n) __REG32((hw_base) + 0x800 + ((n)/4) * 4) #define GIC_DIST_CONFIG(hw_base, n) __REG32((hw_base) + 0xc00 + ((n)/16) * 4) -#define GIC_DIST_SOFTINT(hw_base) __REG32((hw_base) + 0xf00) +#define GIC_DIST_SOFTINT(hw_base) __REG32((hw_base) + 0xf00) #define GIC_DIST_ICPIDR2(hw_base) __REG32((hw_base) + 0xfe8) static unsigned int _gic_max_irq; @@ -206,4 +206,4 @@ void arm_gic_trigger(rt_uint32_t index, int target_cpu, int irq) void arm_gic_clear_sgi(rt_uint32_t index, int target_cpu, int irq) { /* SGI will be cleared automatically. */ -}
\ No newline at end of file +} diff --git a/libcpu/arm/zynqmp-r5/gic.h b/libcpu/arm/zynqmp-r5/gic.h index 7cffec3f88..3f591c0652 100644 --- a/libcpu/arm/zynqmp-r5/gic.h +++ b/libcpu/arm/zynqmp-r5/gic.h @@ -1,11 +1,11 @@ /* - * Copyright (c) 2006-2018, RT-Thread Development Team + * Copyright (c) 2006-2021, RT-Thread Development Team * * SPDX-License-Identifier: Apache-2.0 * * Change Logs: * Date Author Notes - * 2020-03-19 WangHuachen first version + * 2020-03-19 WangHuachen first version */ #ifndef __GIC_H__ diff --git a/libcpu/arm/zynqmp-r5/interrupt.c b/libcpu/arm/zynqmp-r5/interrupt.c index 12ba638345..fa37674761 100644 --- a/libcpu/arm/zynqmp-r5/interrupt.c +++ b/libcpu/arm/zynqmp-r5/interrupt.c @@ -1,11 +1,11 @@ /* - * Copyright (c) 2006-2018, RT-Thread Development Team + * Copyright (c) 2006-2021, RT-Thread Development Team * * SPDX-License-Identifier: Apache-2.0 * * Change Logs: * Date Author Notes - * 2020-03-19 WangHuachen first version + * 2020-03-19 WangHuachen first version */ #include <rthw.h> @@ -130,4 +130,4 @@ void rt_hw_interrupt_trigger(int vector) void rt_hw_interrupt_clear(int vector) { /* SGI will be cleared automatically. */ -}
\ No newline at end of file +} diff --git a/libcpu/arm/zynqmp-r5/interrupt.h b/libcpu/arm/zynqmp-r5/interrupt.h index 71459fa0a9..35490a047b 100644 --- a/libcpu/arm/zynqmp-r5/interrupt.h +++ b/libcpu/arm/zynqmp-r5/interrupt.h @@ -1,11 +1,11 @@ /* - * Copyright (c) 2006-2018, RT-Thread Development Team + * Copyright (c) 2006-2021, RT-Thread Development Team * * SPDX-License-Identifier: Apache-2.0 * * Change Logs: * Date Author Notes - * 2020-03-19 WangHuachen first version + * 2020-03-19 WangHuachen first version */ #ifndef __INTERRUPT_H__ diff --git a/libcpu/arm/zynqmp-r5/mpu.c b/libcpu/arm/zynqmp-r5/mpu.c index dc33a5fe65..fc2ae7dc44 100644 --- a/libcpu/arm/zynqmp-r5/mpu.c +++ b/libcpu/arm/zynqmp-r5/mpu.c @@ -14,8 +14,8 @@ * * Ver Who Date Changes * ----- ---- -------- --------------------------------------------------- -* 5.00 pkp 02/20/14 First release -* 5.04 pkp 12/18/15 Updated MPU initialization as per the proper address map +* 5.00 pkp 02/20/14 First release +* 5.04 pkp 12/18/15 Updated MPU initialization as per the proper address map * 6.00 pkp 06/27/16 moving the Init_MPU code to .boot section since it is a * part of processor boot process * 6.2 mus 01/27/17 Updated to support IAR compiler @@ -46,37 +46,37 @@ typedef rt_uint32_t u32; /************************** Variable Definitions *****************************/ static const struct { - u64 size; - unsigned int encoding; + u64 size; + unsigned int encoding; }region_size[] = { - { 0x20, REGION_32B }, - { 0x40, REGION_64B }, - { 0x80, REGION_128B }, - { 0x100, REGION_256B }, - { 0x200, REGION_512B }, - { 0x400, REGION_1K }, - { 0x800, REGION_2K }, - { 0x1000, REGION_4K }, - { 0x2000, REGION_8K }, - { 0x4000, REGION_16K }, - { 0x8000, REGION_32K }, - { 0x10000, REGION_64K }, - { 0x20000, REGION_128K }, - { 0x40000, REGION_256K }, - { 0x80000, REGION_512K }, - { 0x100000, REGION_1M }, - { 0x200000, REGION_2M }, - { 0x400000, REGION_4M }, - { 0x800000, REGION_8M }, - { 0x1000000, REGION_16M }, - { 0x2000000, REGION_32M }, - { 0x4000000, REGION_64M }, - { 0x8000000, REGION_128M }, - { 0x10000000, REGION_256M }, - { 0x20000000, REGION_512M }, - { 0x40000000, REGION_1G }, - { 0x80000000, REGION_2G }, - { 0x100000000, REGION_4G }, + { 0x20, REGION_32B }, + { 0x40, REGION_64B }, + { 0x80, REGION_128B }, + { 0x100, REGION_256B }, + { 0x200, REGION_512B }, + { 0x400, REGION_1K }, + { 0x800, REGION_2K }, + { 0x1000, REGION_4K }, + { 0x2000, REGION_8K }, + { 0x4000, REGION_16K }, + { 0x8000, REGION_32K }, + { 0x10000, REGION_64K }, + { 0x20000, REGION_128K }, + { 0x40000, REGION_256K }, + { 0x80000, REGION_512K }, + { 0x100000, REGION_1M }, + { 0x200000, REGION_2M }, + { 0x400000, REGION_4M }, + { 0x800000, REGION_8M }, + { 0x1000000, REGION_16M }, + { 0x2000000, REGION_32M }, + { 0x4000000, REGION_64M }, + { 0x8000000, REGION_128M }, + { 0x10000000, REGION_256M }, + { 0x20000000, REGION_512M }, + { 0x40000000, REGION_1G }, + { 0x80000000, REGION_2G }, + { 0x100000000, REGION_4G }, }; /************************** Function Prototypes ******************************/ @@ -96,129 +96,129 @@ static void Xil_DisableMPURegions(void); * MPU with default memory attributes for rest of address range for Cortex R5 * processor. * -* @param None. +* @param None. * -* @return None. +* @return None. * * ******************************************************************************/ void Init_MPU(void) { - u32 Addr; - u32 RegSize = 0U; - u32 Attrib; - u32 RegNum = 0, i, Offset = 0; - u64 size; + u32 Addr; + u32 RegSize = 0U; + u32 Attrib; + u32 RegNum = 0, i, Offset = 0; + u64 size; - Xil_DisableMPURegions(); + Xil_DisableMPURegions(); - Addr = 0x00000000U; -#ifdef XPAR_PSU_R5_DDR_0_S_AXI_BASEADDR - /* If the DDR is present, configure region as per DDR size */ - size = (XPAR_PSU_R5_DDR_0_S_AXI_HIGHADDR - XPAR_PSU_R5_DDR_0_S_AXI_BASEADDR) + 1; - if (size < 0x80000000) { - /* Lookup the size. */ - for (i = 0; i < sizeof region_size / sizeof region_size[0]; i++) { - if (size <= region_size[i].size) { - RegSize = region_size[i].encoding; + Addr = 0x00000000U; +#ifdef XPAR_PSU_R5_DDR_0_S_AXI_BASEADDR + /* If the DDR is present, configure region as per DDR size */ + size = (XPAR_PSU_R5_DDR_0_S_AXI_HIGHADDR - XPAR_PSU_R5_DDR_0_S_AXI_BASEADDR) + 1; + if (size < 0x80000000) { + /* Lookup the size. */ + for (i = 0; i < sizeof region_size / sizeof region_size[0]; i++) { + if (size <= region_size[i].size) { + RegSize = region_size[i].encoding; - /* Check if DDR size is in power of 2*/ - if ( XPAR_PSU_R5_DDR_0_S_AXI_BASEADDR == 0x100000) - Offset = XPAR_PSU_R5_DDR_0_S_AXI_BASEADDR; - if (region_size[i].size > (size + Offset + 1)) { - rt_kprintf ("WARNING: DDR size mapped to Cortexr5 processor is not \ - in power of 2. As processor allocates MPU regions size \ - in power of 2, address range %llx to %x has been \ - incorrectly mapped as normal memory \n", \ - region_size[i].size - 1, ((u32)XPAR_PSU_R5_DDR_0_S_AXI_HIGHADDR + 1)); - } - break; - } - } - } else { - /* if the DDR size is > 2GB, truncate it to 2GB */ - RegSize = REGION_2G; - } + /* Check if DDR size is in power of 2*/ + if ( XPAR_PSU_R5_DDR_0_S_AXI_BASEADDR == 0x100000) + Offset = XPAR_PSU_R5_DDR_0_S_AXI_BASEADDR; + if (region_size[i].size > (size + Offset + 1)) { + rt_kprintf ("WARNING: DDR size mapped to Cortexr5 processor is not \ + in power of 2. As processor allocates MPU regions size \ + in power of 2, address range %llx to %x has been \ + incorrectly mapped as normal memory \n", \ + region_size[i].size - 1, ((u32)XPAR_PSU_R5_DDR_0_S_AXI_HIGHADDR + 1)); + } + break; + } + } + } else { + /* if the DDR size is > 2GB, truncate it to 2GB */ + RegSize = REGION_2G; + } #else - /* For DDRless system, configure region for TCM */ - RegSize = REGION_256K; + /* For DDRless system, configure region for TCM */ + RegSize = REGION_256K; #endif - Attrib = NORM_NSHARED_WB_WA | PRIV_RW_USER_RW; - Xil_SetAttribute(Addr,RegSize,RegNum, Attrib); - RegNum++; + Attrib = NORM_NSHARED_WB_WA | PRIV_RW_USER_RW; + Xil_SetAttribute(Addr,RegSize,RegNum, Attrib); + RegNum++; - /* - * 1G of strongly ordered memory from 0x80000000 to 0xBFFFFFFF for PL. - * 512 MB - LPD-PL interface - * 256 MB - FPD-PL (HPM0) interface - * 256 MB - FPD-PL (HPM1) interface - */ - Addr = 0x80000000; - RegSize = REGION_1G; - Attrib = STRONG_ORDERD_SHARED | PRIV_RW_USER_RW ; - Xil_SetAttribute(Addr,RegSize,RegNum, Attrib); - RegNum++; + /* + * 1G of strongly ordered memory from 0x80000000 to 0xBFFFFFFF for PL. + * 512 MB - LPD-PL interface + * 256 MB - FPD-PL (HPM0) interface + * 256 MB - FPD-PL (HPM1) interface + */ + Addr = 0x80000000; + RegSize = REGION_1G; + Attrib = STRONG_ORDERD_SHARED | PRIV_RW_USER_RW ; + Xil_SetAttribute(Addr,RegSize,RegNum, Attrib); + RegNum++; - /* 512M of device memory from 0xC0000000 to 0xDFFFFFFF for QSPI */ - Addr = 0xC0000000U; - RegSize = REGION_512M; - Attrib = DEVICE_NONSHARED | PRIV_RW_USER_RW ; - Xil_SetAttribute(Addr,RegSize,RegNum, Attrib); - RegNum++; + /* 512M of device memory from 0xC0000000 to 0xDFFFFFFF for QSPI */ + Addr = 0xC0000000U; + RegSize = REGION_512M; + Attrib = DEVICE_NONSHARED | PRIV_RW_USER_RW ; + Xil_SetAttribute(Addr,RegSize,RegNum, Attrib); + RegNum++; - /* 256M of device memory from 0xE0000000 to 0xEFFFFFFF for PCIe Low */ - Addr = 0xE0000000U; - RegSize = REGION_256M; - Attrib = DEVICE_NONSHARED | PRIV_RW_USER_RW ; - Xil_SetAttribute(Addr,RegSize,RegNum, Attrib); - RegNum++; + /* 256M of device memory from 0xE0000000 to 0xEFFFFFFF for PCIe Low */ + Addr = 0xE0000000U; + RegSize = REGION_256M; + Attrib = DEVICE_NONSHARED | PRIV_RW_USER_RW ; + Xil_SetAttribute(Addr,RegSize,RegNum, Attrib); + RegNum++; - /* 16M of device memory from 0xF8000000 to 0xF8FFFFFF for STM_CORESIGHT */ - Addr = 0xF8000000U; - RegSize = REGION_16M; - Attrib = DEVICE_NONSHARED | PRIV_RW_USER_RW ; - Xil_SetAttribute(Addr,RegSize,RegNum, Attrib); - RegNum++; + /* 16M of device memory from 0xF8000000 to 0xF8FFFFFF for STM_CORESIGHT */ + Addr = 0xF8000000U; + RegSize = REGION_16M; + Attrib = DEVICE_NONSHARED | PRIV_RW_USER_RW ; + Xil_SetAttribute(Addr,RegSize,RegNum, Attrib); + RegNum++; - /* 1M of device memory from 0xF9000000 to 0xF90FFFFF for RPU_A53_GIC */ - Addr = 0xF9000000U; - RegSize = REGION_1M; - Attrib = DEVICE_NONSHARED | PRIV_RW_USER_RW ; - Xil_SetAttribute(Addr,RegSize,RegNum, Attrib); - RegNum++; + /* 1M of device memory from 0xF9000000 to 0xF90FFFFF for RPU_A53_GIC */ + Addr = 0xF9000000U; + RegSize = REGION_1M; + Attrib = DEVICE_NONSHARED | PRIV_RW_USER_RW ; + Xil_SetAttribute(Addr,RegSize,RegNum, Attrib); + RegNum++; - /* 16M of device memory from 0xFD000000 to 0xFDFFFFFF for FPS slaves */ - Addr = 0xFD000000U; - RegSize = REGION_16M; - Attrib = DEVICE_NONSHARED | PRIV_RW_USER_RW ; - Xil_SetAttribute(Addr,RegSize,RegNum, Attrib); - RegNum++; + /* 16M of device memory from 0xFD000000 to 0xFDFFFFFF for FPS slaves */ + Addr = 0xFD000000U; + RegSize = REGION_16M; + Attrib = DEVICE_NONSHARED | PRIV_RW_USER_RW ; + Xil_SetAttribute(Addr,RegSize,RegNum, Attrib); + RegNum++; - /* 16M of device memory from 0xFE000000 to 0xFEFFFFFF for Upper LPS slaves */ - Addr = 0xFE000000U; - RegSize = REGION_16M; - Attrib = DEVICE_NONSHARED | PRIV_RW_USER_RW ; - Xil_SetAttribute(Addr,RegSize,RegNum, Attrib); - RegNum++; + /* 16M of device memory from 0xFE000000 to 0xFEFFFFFF for Upper LPS slaves */ + Addr = 0xFE000000U; + RegSize = REGION_16M; + Attrib = DEVICE_NONSHARED | PRIV_RW_USER_RW ; + Xil_SetAttribute(Addr,RegSize,RegNum, Attrib); + RegNum++; - /* - * 16M of device memory from 0xFF000000 to 0xFFFFFFFF for Lower LPS slaves, - * CSU, PMU, TCM, OCM - */ - Addr = 0xFF000000U; - RegSize = REGION_16M; - Attrib = DEVICE_NONSHARED | PRIV_RW_USER_RW ; - Xil_SetAttribute(Addr,RegSize,RegNum, Attrib); - RegNum++; + /* + * 16M of device memory from 0xFF000000 to 0xFFFFFFFF for Lower LPS slaves, + * CSU, PMU, TCM, OCM + */ + Addr = 0xFF000000U; + RegSize = REGION_16M; + Attrib = DEVICE_NONSHARED | PRIV_RW_USER_RW ; + Xil_SetAttribute(Addr,RegSize,RegNum, Attrib); + RegNum++; - /* 256K of OCM RAM from 0xFFFC0000 to 0xFFFFFFFF marked as normal memory */ - Addr = 0xFFFC0000U; - RegSize = REGION_256K; - Attrib = NORM_NSHARED_WB_WA| PRIV_RW_USER_RW ; - Xil_SetAttribute(Addr,RegSize,RegNum, Attrib); + /* 256K of OCM RAM from 0xFFFC0000 to 0xFFFFFFFF marked as normal memory */ + Addr = 0xFFFC0000U; + RegSize = REGION_256K; + Attrib = NORM_NSHARED_WB_WA| PRIV_RW_USER_RW ; + Xil_SetAttribute(Addr,RegSize,RegNum, Attrib); - /* A total of 10 MPU regions are allocated with another 6 being free for users */ + /* A total of 10 MPU regions are allocated with another 6 being free for users */ } @@ -228,28 +228,28 @@ void Init_MPU(void) * of the region size defined by reg_size having attributes attrib of region number * reg_num * -* @param addr is the address for which attributes are to be set. -* @param attrib specifies the attributes for that memory region. -* @param reg_size specifies the size for that memory region. -* @param reg_num specifies the number for that memory region. -* @return None. +* @param addr is the address for which attributes are to be set. +* @param attrib specifies the attributes for that memory region. +* @param reg_size specifies the size for that memory region. +* @param reg_num specifies the number for that memory region. +* @return None. * * ******************************************************************************/ static void Xil_SetAttribute(u32 addr, u32 reg_size,s32 reg_num, u32 attrib) { - u32 Local_reg_size = reg_size; + u32 Local_reg_size = reg_size; - Local_reg_size = Local_reg_size<<1U; - Local_reg_size |= REGION_EN; - dsb(); - mtcp(XREG_CP15_MPU_MEMORY_REG_NUMBER,reg_num); - isb(); - mtcp(XREG_CP15_MPU_REG_BASEADDR,addr); /* Set base address of a region */ - mtcp(XREG_CP15_MPU_REG_ACCESS_CTRL,attrib); /* Set the control attribute */ - mtcp(XREG_CP15_MPU_REG_SIZE_EN,Local_reg_size); /* set the region size and enable it*/ - dsb(); - isb(); /* synchronize context on this processor */ + Local_reg_size = Local_reg_size<<1U; + Local_reg_size |= REGION_EN; + dsb(); + mtcp(XREG_CP15_MPU_MEMORY_REG_NUMBER,reg_num); + isb(); + mtcp(XREG_CP15_MPU_REG_BASEADDR,addr); /* Set base address of a region */ + mtcp(XREG_CP15_MPU_REG_ACCESS_CTRL,attrib); /* Set the control attribute */ + mtcp(XREG_CP15_MPU_REG_SIZE_EN,Local_reg_size); /* set the region size and enable it*/ + dsb(); + isb(); /* synchronize context on this processor */ } @@ -257,29 +257,29 @@ static void Xil_SetAttribute(u32 addr, u32 reg_size,s32 reg_num, u32 attrib) * * Disable all the MPU regions if any of them is enabled * -* @param None. +* @param None. * -* @return None. +* @return None. * * ******************************************************************************/ static void Xil_DisableMPURegions(void) { - u32 Temp = 0U; - u32 Index = 0U; - for (Index = 0; Index <= 15; Index++) { - mtcp(XREG_CP15_MPU_MEMORY_REG_NUMBER,Index); + u32 Temp = 0U; + u32 Index = 0U; + for (Index = 0; Index <= 15; Index++) { + mtcp(XREG_CP15_MPU_MEMORY_REG_NUMBER,Index); #if defined (__GNUC__) - Temp = mfcp(XREG_CP15_MPU_REG_SIZE_EN); + Temp = mfcp(XREG_CP15_MPU_REG_SIZE_EN); #elif defined (__ICCARM__) - mfcp(XREG_CP15_MPU_REG_SIZE_EN,Temp); + mfcp(XREG_CP15_MPU_REG_SIZE_EN,Temp); #endif - Temp &= (~REGION_EN); - dsb(); - mtcp(XREG_CP15_MPU_REG_SIZE_EN,Temp); - dsb(); - isb(); - } + Temp &= (~REGION_EN); + dsb(); + mtcp(XREG_CP15_MPU_REG_SIZE_EN,Temp); + dsb(); + isb(); + } } diff --git a/libcpu/arm/zynqmp-r5/stack.c b/libcpu/arm/zynqmp-r5/stack.c index c8ba712c49..20a6e23987 100644 --- a/libcpu/arm/zynqmp-r5/stack.c +++ b/libcpu/arm/zynqmp-r5/stack.c @@ -1,5 +1,5 @@ /* - * Copyright (c) 2006-2018, RT-Thread Development Team + * Copyright (c) 2006-2021, RT-Thread Development Team * * SPDX-License-Identifier: Apache-2.0 * diff --git a/libcpu/arm/zynqmp-r5/trap.c b/libcpu/arm/zynqmp-r5/trap.c index 7a48a3c190..64d4cbf5e8 100644 --- a/libcpu/arm/zynqmp-r5/trap.c +++ b/libcpu/arm/zynqmp-r5/trap.c @@ -1,5 +1,5 @@ /* - * Copyright (c) 2006-2018, RT-Thread Development Team + * Copyright (c) 2006-2021, RT-Thread Development Team * * SPDX-License-Identifier: Apache-2.0 * diff --git a/libcpu/arm/zynqmp-r5/xpseudo_asm_gcc.h b/libcpu/arm/zynqmp-r5/xpseudo_asm_gcc.h index f3f978d9eb..7a65ef6ece 100644 --- a/libcpu/arm/zynqmp-r5/xpseudo_asm_gcc.h +++ b/libcpu/arm/zynqmp-r5/xpseudo_asm_gcc.h @@ -36,7 +36,7 @@ * * Ver Who Date Changes * ----- -------- -------- ----------------------------------------------- -* 5.00 pkp 05/21/14 First release +* 5.00 pkp 05/21/14 First release * 6.0 mus 07/27/16 Consolidated file for a53,a9 and r5 processors * </pre> * @@ -59,38 +59,38 @@ extern "C" { /***************** Macros (Inline Functions) Definitions ********************/ /* necessary for pre-processor */ -#define stringify(s) tostring(s) -#define tostring(s) #s +#define stringify(s) tostring(s) +#define tostring(s) #s #if defined (__aarch64__) /* pseudo assembler instructions */ -#define mfcpsr() ({rt_uint32_t rval = 0U; \ - asm volatile("mrs %0, DAIF" : "=r" (rval));\ - rval;\ - }) +#define mfcpsr() ({rt_uint32_t rval = 0U; \ + asm volatile("mrs %0, DAIF" : "=r" (rval));\ + rval;\ + }) #define mtcpsr(v) __asm__ __volatile__ ("msr DAIF, %0" : : "r" (v)) -#define cpsiei() //__asm__ __volatile__("cpsie i\n") -#define cpsidi() //__asm__ __volatile__("cpsid i\n") +#define cpsiei() //__asm__ __volatile__("cpsie i\n") +#define cpsidi() //__asm__ __volatile__("cpsid i\n") -#define cpsief() //__asm__ __volatile__("cpsie f\n") -#define cpsidf() //__asm__ __volatile__("cpsid f\n") +#define cpsief() //__asm__ __volatile__("cpsie f\n") +#define cpsidf() //__asm__ __volatile__("cpsid f\n") -#define mtgpr(rn, v) /*__asm__ __volatile__(\ - "mov r" stringify(rn) ", %0 \n"\ - : : "r" (v)\ - )*/ +#define mtgpr(rn, v) /*__asm__ __volatile__(\ + "mov r" stringify(rn) ", %0 \n"\ + : : "r" (v)\ + )*/ -#define mfgpr(rn) /*({rt_uint32_t rval; \ - __asm__ __volatile__(\ - "mov %0,r" stringify(rn) "\n"\ - : "=r" (rval)\ - );\ - rval;\ - })*/ +#define mfgpr(rn) /*({rt_uint32_t rval; \ + __asm__ __volatile__(\ + "mov %0,r" stringify(rn) "\n"\ + : "=r" (rval)\ + );\ + rval;\ + })*/ /* memory synchronization operations */ @@ -105,13 +105,13 @@ extern "C" { /* Memory Operations */ -#define ldr(adr) ({u64 rval; \ - __asm__ __volatile__(\ - "ldr %0,[%1]"\ - : "=r" (rval) : "r" (adr)\ - );\ - rval;\ - }) +#define ldr(adr) ({u64 rval; \ + __asm__ __volatile__(\ + "ldr %0,[%1]"\ + : "=r" (rval) : "r" (adr)\ + );\ + rval;\ + }) #define mfelrel3() ({u64 rval = 0U; \ asm volatile("mrs %0, ELR_EL3" : "=r" (rval));\ @@ -123,39 +123,39 @@ extern "C" { #else /* pseudo assembler instructions */ -#define mfcpsr() ({rt_uint32_t rval = 0U; \ - __asm__ __volatile__(\ - "mrs %0, cpsr\n"\ - : "=r" (rval)\ - );\ - rval;\ - }) +#define mfcpsr() ({rt_uint32_t rval = 0U; \ + __asm__ __volatile__(\ + "mrs %0, cpsr\n"\ + : "=r" (rval)\ + );\ + rval;\ + }) -#define mtcpsr(v) __asm__ __volatile__(\ - "msr cpsr,%0\n"\ - : : "r" (v)\ - ) +#define mtcpsr(v) __asm__ __volatile__(\ + "msr cpsr,%0\n"\ + : : "r" (v)\ + ) -#define cpsiei() __asm__ __volatile__("cpsie i\n") -#define cpsidi() __asm__ __volatile__("cpsid i\n") +#define cpsiei() __asm__ __volatile__("cpsie i\n") +#define cpsidi() __asm__ __volatile__("cpsid i\n") -#define cpsief() __asm__ __volatile__("cpsie f\n") -#define cpsidf() __asm__ __volatile__("cpsid f\n") +#define cpsief() __asm__ __volatile__("cpsie f\n") +#define cpsidf() __asm__ __volatile__("cpsid f\n") -#define mtgpr(rn, v) __asm__ __volatile__(\ - "mov r" stringify(rn) ", %0 \n"\ - : : "r" (v)\ - ) +#define mtgpr(rn, v) __asm__ __volatile__(\ + "mov r" stringify(rn) ", %0 \n"\ + : : "r" (v)\ + ) -#define mfgpr(rn) ({rt_uint32_t rval; \ - __asm__ __volatile__(\ - "mov %0,r" stringify(rn) "\n"\ - : "=r" (rval)\ - );\ - rval;\ - }) +#define mfgpr(rn) ({rt_uint32_t rval; \ + __asm__ __volatile__(\ + "mov %0,r" stringify(rn) "\n"\ + : "=r" (rval)\ + );\ + rval;\ + }) /* memory synchronization operations */ @@ -170,72 +170,72 @@ extern "C" { /* Memory Operations */ -#define ldr(adr) ({rt_uint32_t rval; \ - __asm__ __volatile__(\ - "ldr %0,[%1]"\ - : "=r" (rval) : "r" (adr)\ - );\ - rval;\ - }) +#define ldr(adr) ({rt_uint32_t rval; \ + __asm__ __volatile__(\ + "ldr %0,[%1]"\ + : "=r" (rval) : "r" (adr)\ + );\ + rval;\ + }) #endif -#define ldrb(adr) ({rt_uint8_t rval; \ - __asm__ __volatile__(\ - "ldrb %0,[%1]"\ - : "=r" (rval) : "r" (adr)\ - );\ - rval;\ - }) +#define ldrb(adr) ({rt_uint8_t rval; \ + __asm__ __volatile__(\ + "ldrb %0,[%1]"\ + : "=r" (rval) : "r" (adr)\ + );\ + rval;\ + }) -#define str(adr, val) __asm__ __volatile__(\ - "str %0,[%1]\n"\ - : : "r" (val), "r" (adr)\ - ) +#define str(adr, val) __asm__ __volatile__(\ + "str %0,[%1]\n"\ + : : "r" (val), "r" (adr)\ + ) -#define strb(adr, val) __asm__ __volatile__(\ - "strb %0,[%1]\n"\ - : : "r" (val), "r" (adr)\ - ) +#define strb(adr, val) __asm__ __volatile__(\ + "strb %0,[%1]\n"\ + : : "r" (val), "r" (adr)\ + ) /* Count leading zeroes (clz) */ -#define clz(arg) ({rt_uint8_t rval; \ - __asm__ __volatile__(\ - "clz %0,%1"\ - : "=r" (rval) : "r" (arg)\ - );\ - rval;\ - }) +#define clz(arg) ({rt_uint8_t rval; \ + __asm__ __volatile__(\ + "clz %0,%1"\ + : "=r" (rval) : "r" (arg)\ + );\ + rval;\ + }) #if defined (__aarch64__) -#define mtcpdc(reg,val) __asm__ __volatile__("dc " #reg ",%0" : : "r" (val)) -#define mtcpic(reg,val) __asm__ __volatile__("ic " #reg ",%0" : : "r" (val)) +#define mtcpdc(reg,val) __asm__ __volatile__("dc " #reg ",%0" : : "r" (val)) +#define mtcpic(reg,val) __asm__ __volatile__("ic " #reg ",%0" : : "r" (val)) -#define mtcpicall(reg) __asm__ __volatile__("ic " #reg) -#define mtcptlbi(reg) __asm__ __volatile__("tlbi " #reg) -#define mtcpat(reg,val) __asm__ __volatile__("at " #reg ",%0" : : "r" (val)) +#define mtcpicall(reg) __asm__ __volatile__("ic " #reg) +#define mtcptlbi(reg) __asm__ __volatile__("tlbi " #reg) +#define mtcpat(reg,val) __asm__ __volatile__("at " #reg ",%0" : : "r" (val)) /* CP15 operations */ -#define mfcp(reg) ({u64 rval = 0U;\ - __asm__ __volatile__("mrs %0, " #reg : "=r" (rval));\ - rval;\ - }) +#define mfcp(reg) ({u64 rval = 0U;\ + __asm__ __volatile__("mrs %0, " #reg : "=r" (rval));\ + rval;\ + }) -#define mtcp(reg,val) __asm__ __volatile__("msr " #reg ",%0" : : "r" (val)) +#define mtcp(reg,val) __asm__ __volatile__("msr " #reg ",%0" : : "r" (val)) #else /* CP15 operations */ -#define mtcp(rn, v) __asm__ __volatile__(\ - "mcr " rn "\n"\ - : : "r" (v)\ - ); +#define mtcp(rn, v) __asm__ __volatile__(\ + "mcr " rn "\n"\ + : : "r" (v)\ + ); -#define mfcp(rn) ({rt_uint32_t rval = 0U; \ - __asm__ __volatile__(\ - "mrc " rn "\n"\ - : "=r" (rval)\ - );\ - rval;\ - }) +#define mfcp(rn) ({rt_uint32_t rval = 0U; \ + __asm__ __volatile__(\ + "mrc " rn "\n"\ + : "=r" (rval)\ + );\ + rval;\ + }) #endif /************************** Variable Definitions ****************************/ diff --git a/libcpu/arm/zynqmp-r5/xreg_cortexr5.h b/libcpu/arm/zynqmp-r5/xreg_cortexr5.h index 263f213567..9c0ae2b440 100644 --- a/libcpu/arm/zynqmp-r5/xreg_cortexr5.h +++ b/libcpu/arm/zynqmp-r5/xreg_cortexr5.h @@ -23,86 +23,86 @@ * </pre> * ******************************************************************************/ -#ifndef XREG_CORTEXR5_H /* prevent circular inclusions */ -#define XREG_CORTEXR5_H /* by using protection macros */ +#ifndef XREG_CORTEXR5_H /* prevent circular inclusions */ +#define XREG_CORTEXR5_H /* by using protection macros */ #ifdef __cplusplus extern "C" { #endif /* __cplusplus */ /* GPRs */ -#define XREG_GPR0 r0 -#define XREG_GPR1 r1 -#define XREG_GPR2 r2 -#define XREG_GPR3 r3 -#define XREG_GPR4 r4 -#define XREG_GPR5 r5 -#define XREG_GPR6 r6 -#define XREG_GPR7 r7 -#define XREG_GPR8 r8 -#define XREG_GPR9 r9 -#define XREG_GPR10 r10 -#define XREG_GPR11 r11 -#define XREG_GPR12 r12 -#define XREG_GPR13 r13 -#define XREG_GPR14 r14 -#define XREG_GPR15 r15 -#define XREG_CPSR cpsr +#define XREG_GPR0 r0 +#define XREG_GPR1 r1 +#define XREG_GPR2 r2 +#define XREG_GPR3 r3 +#define XREG_GPR4 r4 +#define XREG_GPR5 r5 +#define XREG_GPR6 r6 +#define XREG_GPR7 r7 +#define XREG_GPR8 r8 +#define XREG_GPR9 r9 +#define XREG_GPR10 r10 +#define XREG_GPR11 r11 +#define XREG_GPR12 r12 +#define XREG_GPR13 r13 +#define XREG_GPR14 r14 +#define XREG_GPR15 r15 +#define XREG_CPSR cpsr /* Coprocessor number defines */ -#define XREG_CP0 0 -#define XREG_CP1 1 -#define XREG_CP2 2 -#define XREG_CP3 3 -#define XREG_CP4 4 -#define XREG_CP5 5 -#define XREG_CP6 6 -#define XREG_CP7 7 -#define XREG_CP8 8 -#define XREG_CP9 9 -#define XREG_CP10 10 -#define XREG_CP11 11 -#define XREG_CP12 12 -#define XREG_CP13 13 -#define XREG_CP14 14 -#define XREG_CP15 15 +#define XREG_CP0 0 +#define XREG_CP1 1 +#define XREG_CP2 2 +#define XREG_CP3 3 +#define XREG_CP4 4 +#define XREG_CP5 5 +#define XREG_CP6 6 +#define XREG_CP7 7 +#define XREG_CP8 8 +#define XREG_CP9 9 +#define XREG_CP10 10 +#define XREG_CP11 11 +#define XREG_CP12 12 +#define XREG_CP13 13 +#define XREG_CP14 14 +#define XREG_CP15 15 /* Coprocessor control register defines */ -#define XREG_CR0 cr0 -#define XREG_CR1 cr1 -#define XREG_CR2 cr2 -#define XREG_CR3 cr3 -#define XREG_CR4 cr4 -#define XREG_CR5 cr5 -#define XREG_CR6 cr6 -#define XREG_CR7 cr7 -#define XREG_CR8 cr8 -#define XREG_CR9 cr9 -#define XREG_CR10 cr10 -#define XREG_CR11 cr11 -#define XREG_CR12 cr12 -#define XREG_CR13 cr13 -#define XREG_CR14 cr14 -#define XREG_CR15 cr15 +#define XREG_CR0 cr0 +#define XREG_CR1 cr1 +#define XREG_CR2 cr2 +#define XREG_CR3 cr3 +#define XREG_CR4 cr4 +#define XREG_CR5 cr5 +#define XREG_CR6 cr6 +#define XREG_CR7 cr7 +#define XREG_CR8 cr8 +#define XREG_CR9 cr9 +#define XREG_CR10 cr10 +#define XREG_CR11 cr11 +#define XREG_CR12 cr12 +#define XREG_CR13 cr13 +#define XREG_CR14 cr14 +#define XREG_CR15 cr15 /* Current Processor Status Register (CPSR) Bits */ -#define XREG_CPSR_THUMB_MODE 0x20U -#define XREG_CPSR_MODE_BITS 0x1FU -#define XREG_CPSR_SYSTEM_MODE 0x1FU -#define XREG_CPSR_UNDEFINED_MODE 0x1BU -#define XREG_CPSR_DATA_ABORT_MODE 0x17U -#define XREG_CPSR_SVC_MODE 0x13U -#define XREG_CPSR_IRQ_MODE 0x12U -#define XREG_CPSR_FIQ_MODE 0x11U -#define XREG_CPSR_USER_MODE 0x10U +#define XREG_CPSR_THUMB_MODE 0x20U +#define XREG_CPSR_MODE_BITS 0x1FU +#define XREG_CPSR_SYSTEM_MODE 0x1FU +#define XREG_CPSR_UNDEFINED_MODE 0x1BU +#define XREG_CPSR_DATA_ABORT_MODE 0x17U +#define XREG_CPSR_SVC_MODE 0x13U +#define XREG_CPSR_IRQ_MODE 0x12U +#define XREG_CPSR_FIQ_MODE 0x11U +#define XREG_CPSR_USER_MODE 0x10U -#define XREG_CPSR_IRQ_ENABLE 0x80U -#define XREG_CPSR_FIQ_ENABLE 0x40U +#define XREG_CPSR_IRQ_ENABLE 0x80U +#define XREG_CPSR_FIQ_ENABLE 0x40U -#define XREG_CPSR_N_BIT 0x80000000U -#define XREG_CPSR_Z_BIT 0x40000000U -#define XREG_CPSR_C_BIT 0x20000000U -#define XREG_CPSR_V_BIT 0x10000000U +#define XREG_CPSR_N_BIT 0x80000000U +#define XREG_CPSR_Z_BIT 0x40000000U +#define XREG_CPSR_C_BIT 0x20000000U +#define XREG_CPSR_V_BIT 0x10000000U /*MPU region definitions*/ #define REGION_32B 0x00000004U @@ -138,99 +138,99 @@ extern "C" { -#define SHAREABLE 0x00000004U /*shareable */ -#define STRONG_ORDERD_SHARED 0x00000000U /*strongly ordered, always shareable*/ +#define SHAREABLE 0x00000004U /*shareable */ +#define STRONG_ORDERD_SHARED 0x00000000U /*strongly ordered, always shareable*/ -#define DEVICE_SHARED 0x00000001U /*device, shareable*/ -#define DEVICE_NONSHARED 0x00000010U /*device, non shareable*/ +#define DEVICE_SHARED 0x00000001U /*device, shareable*/ +#define DEVICE_NONSHARED 0x00000010U /*device, non shareable*/ -#define NORM_NSHARED_WT_NWA 0x00000002U /*Outer and Inner write-through, no write-allocate non-shareable*/ -#define NORM_SHARED_WT_NWA 0x00000006U /*Outer and Inner write-through, no write-allocate shareable*/ +#define NORM_NSHARED_WT_NWA 0x00000002U /*Outer and Inner write-through, no write-allocate non-shareable*/ +#define NORM_SHARED_WT_NWA 0x00000006U /*Outer and Inner write-through, no write-allocate shareable*/ -#define NORM_NSHARED_WB_NWA 0x00000003U /*Outer and Inner write-back, no write-allocate non shareable*/ -#define NORM_SHARED_WB_NWA 0x00000007U /*Outer and Inner write-back, no write-allocate shareable*/ +#define NORM_NSHARED_WB_NWA 0x00000003U /*Outer and Inner write-back, no write-allocate non shareable*/ +#define NORM_SHARED_WB_NWA 0x00000007U /*Outer and Inner write-back, no write-allocate shareable*/ -#define NORM_NSHARED_NCACHE 0x00000008U /*Outer and Inner Non cacheable non shareable*/ -#define NORM_SHARED_NCACHE 0x0000000CU /*Outer and Inner Non cacheable shareable*/ +#define NORM_NSHARED_NCACHE 0x00000008U /*Outer and Inner Non cacheable non shareable*/ +#define NORM_SHARED_NCACHE 0x0000000CU /*Outer and Inner Non cacheable shareable*/ -#define NORM_NSHARED_WB_WA 0x0000000BU /*Outer and Inner write-back non shared*/ -#define NORM_SHARED_WB_WA 0x0000000FU /*Outer and Inner write-back shared*/ +#define NORM_NSHARED_WB_WA 0x0000000BU /*Outer and Inner write-back non shared*/ +#define NORM_SHARED_WB_WA 0x0000000FU /*Outer and Inner write-back shared*/ /* inner and outer cache policies can be combined for different combinations */ -#define NORM_IN_POLICY_NCACHE 0x00000020U /*inner non cacheable*/ -#define NORM_IN_POLICY_WB_WA 0x00000021U /*inner write back write allocate*/ -#define NORM_IN_POLICY_WT_NWA 0x00000022U /*inner write through no write allocate*/ -#define NORM_IN_POLICY_WB_NWA 0x00000023U /*inner write back no write allocate*/ +#define NORM_IN_POLICY_NCACHE 0x00000020U /*inner non cacheable*/ +#define NORM_IN_POLICY_WB_WA 0x00000021U /*inner write back write allocate*/ +#define NORM_IN_POLICY_WT_NWA 0x00000022U /*inner write through no write allocate*/ +#define NORM_IN_POLICY_WB_NWA 0x00000023U /*inner write back no write allocate*/ -#define NORM_OUT_POLICY_NCACHE 0x00000020U /*outer non cacheable*/ -#define NORM_OUT_POLICY_WB_WA 0x00000028U /*outer write back write allocate*/ -#define NORM_OUT_POLICY_WT_NWA 0x00000030U /*outer write through no write allocate*/ -#define NORM_OUT_POLICY_WB_NWA 0x00000038U /*outer write back no write allocate*/ +#define NORM_OUT_POLICY_NCACHE 0x00000020U /*outer non cacheable*/ +#define NORM_OUT_POLICY_WB_WA 0x00000028U /*outer write back write allocate*/ +#define NORM_OUT_POLICY_WT_NWA 0x00000030U /*outer write through no write allocate*/ +#define NORM_OUT_POLICY_WB_NWA 0x00000038U /*outer write back no write allocate*/ -#define NO_ACCESS (0x00000000U<<8U) /*No access*/ -#define PRIV_RW_USER_NA (0x00000001U<<8U) /*Privileged access only*/ -#define PRIV_RW_USER_RO (0x00000002U<<8U) /*Writes in User mode generate permission faults*/ -#define PRIV_RW_USER_RW (0x00000003U<<8U) /*Full Access*/ -#define PRIV_RO_USER_NA (0x00000005U<<8U) /*Privileged eead only*/ -#define PRIV_RO_USER_RO (0x00000006U<<8U) /*Privileged/User read-only*/ +#define NO_ACCESS (0x00000000U<<8U) /*No access*/ +#define PRIV_RW_USER_NA (0x00000001U<<8U) /*Privileged access only*/ +#define PRIV_RW_USER_RO (0x00000002U<<8U) /*Writes in User mode generate permission faults*/ +#define PRIV_RW_USER_RW (0x00000003U<<8U) /*Full Access*/ +#define PRIV_RO_USER_NA (0x00000005U<<8U) /*Privileged eead only*/ +#define PRIV_RO_USER_RO (0x00000006U<<8U) /*Privileged/User read-only*/ -#define EXECUTE_NEVER (0x00000001U<<12U) /* Bit 12*/ +#define EXECUTE_NEVER (0x00000001U<<12U) /* Bit 12*/ /* CP15 defines */ /* C0 Register defines */ -#define XREG_CP15_MAIN_ID "p15, 0, %0, c0, c0, 0" -#define XREG_CP15_CACHE_TYPE "p15, 0, %0, c0, c0, 1" -#define XREG_CP15_TCM_TYPE "p15, 0, %0, c0, c0, 2" -#define XREG_CP15_TLB_TYPE "p15, 0, %0, c0, c0, 3" -#define XREG_CP15_MPU_TYPE "p15, 0, %0, c0, c0, 4" -#define XREG_CP15_MULTI_PROC_AFFINITY "p15, 0, %0, c0, c0, 5" +#define XREG_CP15_MAIN_ID "p15, 0, %0, c0, c0, 0" +#define XREG_CP15_CACHE_TYPE "p15, 0, %0, c0, c0, 1" +#define XREG_CP15_TCM_TYPE "p15, 0, %0, c0, c0, 2" +#define XREG_CP15_TLB_TYPE "p15, 0, %0, c0, c0, 3" +#define XREG_CP15_MPU_TYPE "p15, 0, %0, c0, c0, 4" +#define XREG_CP15_MULTI_PROC_AFFINITY "p15, 0, %0, c0, c0, 5" -#define XREG_CP15_PROC_FEATURE_0 "p15, 0, %0, c0, c1, 0" -#define XREG_CP15_PROC_FEATURE_1 "p15, 0, %0, c0, c1, 1" -#define XREG_CP15_DEBUG_FEATURE_0 "p15, 0, %0, c0, c1, 2" -#define XREG_CP15_MEMORY_FEATURE_0 "p15, 0, %0, c0, c1, 4" -#define XREG_CP15_MEMORY_FEATURE_1 "p15, 0, %0, c0, c1, 5" -#define XREG_CP15_MEMORY_FEATURE_2 "p15, 0, %0, c0, c1, 6" -#define XREG_CP15_MEMORY_FEATURE_3 "p15, 0, %0, c0, c1, 7" +#define XREG_CP15_PROC_FEATURE_0 "p15, 0, %0, c0, c1, 0" +#define XREG_CP15_PROC_FEATURE_1 "p15, 0, %0, c0, c1, 1" +#define XREG_CP15_DEBUG_FEATURE_0 "p15, 0, %0, c0, c1, 2" +#define XREG_CP15_MEMORY_FEATURE_0 "p15, 0, %0, c0, c1, 4" +#define XREG_CP15_MEMORY_FEATURE_1 "p15, 0, %0, c0, c1, 5" +#define XREG_CP15_MEMORY_FEATURE_2 "p15, 0, %0, c0, c1, 6" +#define XREG_CP15_MEMORY_FEATURE_3 "p15, 0, %0, c0, c1, 7" -#define XREG_CP15_INST_FEATURE_0 "p15, 0, %0, c0, c2, 0" -#define XREG_CP15_INST_FEATURE_1 "p15, 0, %0, c0, c2, 1" -#define XREG_CP15_INST_FEATURE_2 "p15, 0, %0, c0, c2, 2" -#define XREG_CP15_INST_FEATURE_3 "p15, 0, %0, c0, c2, 3" -#define XREG_CP15_INST_FEATURE_4 "p15, 0, %0, c0, c2, 4" -#define XREG_CP15_INST_FEATURE_5 "p15, 0, %0, c0, c2, 5" +#define XREG_CP15_INST_FEATURE_0 "p15, 0, %0, c0, c2, 0" +#define XREG_CP15_INST_FEATURE_1 "p15, 0, %0, c0, c2, 1" +#define XREG_CP15_INST_FEATURE_2 "p15, 0, %0, c0, c2, 2" +#define XREG_CP15_INST_FEATURE_3 "p15, 0, %0, c0, c2, 3" +#define XREG_CP15_INST_FEATURE_4 "p15, 0, %0, c0, c2, 4" +#define XREG_CP15_INST_FEATURE_5 "p15, 0, %0, c0, c2, 5" -#define XREG_CP15_CACHE_SIZE_ID "p15, 1, %0, c0, c0, 0" -#define XREG_CP15_CACHE_LEVEL_ID "p15, 1, %0, c0, c0, 1" -#define XREG_CP15_AUXILARY_ID "p15, 1, %0, c0, c0, 7" +#define XREG_CP15_CACHE_SIZE_ID "p15, 1, %0, c0, c0, 0" +#define XREG_CP15_CACHE_LEVEL_ID "p15, 1, %0, c0, c0, 1" +#define XREG_CP15_AUXILARY_ID "p15, 1, %0, c0, c0, 7" -#define XREG_CP15_CACHE_SIZE_SEL "p15, 2, %0, c0, c0, 0" +#define XREG_CP15_CACHE_SIZE_SEL "p15, 2, %0, c0, c0, 0" /* C1 Register Defines */ -#define XREG_CP15_SYS_CONTROL "p15, 0, %0, c1, c0, 0" -#define XREG_CP15_AUX_CONTROL "p15, 0, %0, c1, c0, 1" -#define XREG_CP15_CP_ACCESS_CONTROL "p15, 0, %0, c1, c0, 2" +#define XREG_CP15_SYS_CONTROL "p15, 0, %0, c1, c0, 0" +#define XREG_CP15_AUX_CONTROL "p15, 0, %0, c1, c0, 1" +#define XREG_CP15_CP_ACCESS_CONTROL "p15, 0, %0, c1, c0, 2" /* XREG_CP15_CONTROL bit defines */ -#define XREG_CP15_CONTROL_TE_BIT 0x40000000U -#define XREG_CP15_CONTROL_AFE_BIT 0x20000000U -#define XREG_CP15_CONTROL_TRE_BIT 0x10000000U -#define XREG_CP15_CONTROL_NMFI_BIT 0x08000000U -#define XREG_CP15_CONTROL_EE_BIT 0x02000000U -#define XREG_CP15_CONTROL_HA_BIT 0x00020000U -#define XREG_CP15_CONTROL_RR_BIT 0x00004000U -#define XREG_CP15_CONTROL_V_BIT 0x00002000U -#define XREG_CP15_CONTROL_I_BIT 0x00001000U -#define XREG_CP15_CONTROL_Z_BIT 0x00000800U -#define XREG_CP15_CONTROL_SW_BIT 0x00000400U -#define XREG_CP15_CONTROL_B_BIT 0x00000080U -#define XREG_CP15_CONTROL_C_BIT 0x00000004U -#define XREG_CP15_CONTROL_A_BIT 0x00000002U -#define XREG_CP15_CONTROL_M_BIT 0x00000001U +#define XREG_CP15_CONTROL_TE_BIT 0x40000000U +#define XREG_CP15_CONTROL_AFE_BIT 0x20000000U +#define XREG_CP15_CONTROL_TRE_BIT 0x10000000U +#define XREG_CP15_CONTROL_NMFI_BIT 0x08000000U +#define XREG_CP15_CONTROL_EE_BIT 0x02000000U +#define XREG_CP15_CONTROL_HA_BIT 0x00020000U +#define XREG_CP15_CONTROL_RR_BIT 0x00004000U +#define XREG_CP15_CONTROL_V_BIT 0x00002000U +#define XREG_CP15_CONTROL_I_BIT 0x00001000U +#define XREG_CP15_CONTROL_Z_BIT 0x00000800U +#define XREG_CP15_CONTROL_SW_BIT 0x00000400U +#define XREG_CP15_CONTROL_B_BIT 0x00000080U +#define XREG_CP15_CONTROL_C_BIT 0x00000004U +#define XREG_CP15_CONTROL_A_BIT 0x00000002U +#define XREG_CP15_CONTROL_M_BIT 0x00000001U /* C2 Register Defines */ /* Not Used */ @@ -241,55 +241,55 @@ extern "C" { /* Not Used */ /* C5 Register Defines */ -#define XREG_CP15_DATA_FAULT_STATUS "p15, 0, %0, c5, c0, 0" -#define XREG_CP15_INST_FAULT_STATUS "p15, 0, %0, c5, c0, 1" +#define XREG_CP15_DATA_FAULT_STATUS "p15, 0, %0, c5, c0, 0" +#define XREG_CP15_INST_FAULT_STATUS "p15, 0, %0, c5, c0, 1" -#define XREG_CP15_AUX_DATA_FAULT_STATUS "p15, 0, %0, c5, c1, 0" -#define XREG_CP15_AUX_INST_FAULT_STATUS "p15, 0, %0, c5, c1, 1" +#define XREG_CP15_AUX_DATA_FAULT_STATUS "p15, 0, %0, c5, c1, 0" +#define XREG_CP15_AUX_INST_FAULT_STATUS "p15, 0, %0, c5, c1, 1" /* C6 Register Defines */ -#define XREG_CP15_DATA_FAULT_ADDRESS "p15, 0, %0, c6, c0, 0" -#define XREG_CP15_INST_FAULT_ADDRESS "p15, 0, %0, c6, c0, 2" +#define XREG_CP15_DATA_FAULT_ADDRESS "p15, 0, %0, c6, c0, 0" +#define XREG_CP15_INST_FAULT_ADDRESS "p15, 0, %0, c6, c0, 2" -#define XREG_CP15_MPU_REG_BASEADDR "p15, 0, %0, c6, c1, 0" -#define XREG_CP15_MPU_REG_SIZE_EN "p15, 0, %0, c6, c1, 2" -#define XREG_CP15_MPU_REG_ACCESS_CTRL "p15, 0, %0, c6, c1, 4" +#define XREG_CP15_MPU_REG_BASEADDR "p15, 0, %0, c6, c1, 0" +#define XREG_CP15_MPU_REG_SIZE_EN "p15, 0, %0, c6, c1, 2" +#define XREG_CP15_MPU_REG_ACCESS_CTRL "p15, 0, %0, c6, c1, 4" -#define XREG_CP15_MPU_MEMORY_REG_NUMBER "p15, 0, %0, c6, c2, 0" +#define XREG_CP15_MPU_MEMORY_REG_NUMBER "p15, 0, %0, c6, c2, 0" /* C7 Register Defines */ -#define XREG_CP15_NOP "p15, 0, %0, c7, c0, 4" +#define XREG_CP15_NOP "p15, 0, %0, c7, c0, 4" -#define XREG_CP15_INVAL_IC_POU "p15, 0, %0, c7, c5, 0" -#define XREG_CP15_INVAL_IC_LINE_MVA_POU "p15, 0, %0, c7, c5, 1" +#define XREG_CP15_INVAL_IC_POU "p15, 0, %0, c7, c5, 0" +#define XREG_CP15_INVAL_IC_LINE_MVA_POU "p15, 0, %0, c7, c5, 1" /* The CP15 register access below has been deprecated in favor of the new * isb instruction in Cortex R5. */ -#define XREG_CP15_INST_SYNC_BARRIER "p15, 0, %0, c7, c5, 4" -#define XREG_CP15_INVAL_BRANCH_ARRAY "p15, 0, %0, c7, c5, 6" -#define XREG_CP15_INVAL_BRANCH_ARRAY_LINE "p15, 0, %0, c7, c5, 7" +#define XREG_CP15_INST_SYNC_BARRIER "p15, 0, %0, c7, c5, 4" +#define XREG_CP15_INVAL_BRANCH_ARRAY "p15, 0, %0, c7, c5, 6" +#define XREG_CP15_INVAL_BRANCH_ARRAY_LINE "p15, 0, %0, c7, c5, 7" -#define XREG_CP15_INVAL_DC_LINE_MVA_POC "p15, 0, %0, c7, c6, 1" -#define XREG_CP15_INVAL_DC_LINE_SW "p15, 0, %0, c7, c6, 2" +#define XREG_CP15_INVAL_DC_LINE_MVA_POC "p15, 0, %0, c7, c6, 1" +#define XREG_CP15_INVAL_DC_LINE_SW "p15, 0, %0, c7, c6, 2" -#define XREG_CP15_CLEAN_DC_LINE_MVA_POC "p15, 0, %0, c7, c10, 1" -#define XREG_CP15_CLEAN_DC_LINE_SW "p15, 0, %0, c7, c10, 2" +#define XREG_CP15_CLEAN_DC_LINE_MVA_POC "p15, 0, %0, c7, c10, 1" +#define XREG_CP15_CLEAN_DC_LINE_SW "p15, 0, %0, c7, c10, 2" -#define XREG_CP15_INVAL_DC_ALL "p15, 0, %0, c15, c5, 0" +#define XREG_CP15_INVAL_DC_ALL "p15, 0, %0, c15, c5, 0" /* The next two CP15 register accesses below have been deprecated in favor * of the new dsb and dmb instructions in Cortex R5. */ -#define XREG_CP15_DATA_SYNC_BARRIER "p15, 0, %0, c7, c10, 4" -#define XREG_CP15_DATA_MEMORY_BARRIER "p15, 0, %0, c7, c10, 5" +#define XREG_CP15_DATA_SYNC_BARRIER "p15, 0, %0, c7, c10, 4" +#define XREG_CP15_DATA_MEMORY_BARRIER "p15, 0, %0, c7, c10, 5" -#define XREG_CP15_CLEAN_DC_LINE_MVA_POU "p15, 0, %0, c7, c11, 1" +#define XREG_CP15_CLEAN_DC_LINE_MVA_POU "p15, 0, %0, c7, c11, 1" -#define XREG_CP15_NOP2 "p15, 0, %0, c7, c13, 1" +#define XREG_CP15_NOP2 "p15, 0, %0, c7, c13, 1" -#define XREG_CP15_CLEAN_INVAL_DC_LINE_MVA_POC "p15, 0, %0, c7, c14, 1" -#define XREG_CP15_CLEAN_INVAL_DC_LINE_SW "p15, 0, %0, c7, c14, 2" +#define XREG_CP15_CLEAN_INVAL_DC_LINE_MVA_POC "p15, 0, %0, c7, c14, 1" +#define XREG_CP15_CLEAN_INVAL_DC_LINE_SW "p15, 0, %0, c7, c14, 2" /* C8 Register Defines */ /* Not Used */ @@ -297,24 +297,24 @@ extern "C" { /* C9 Register Defines */ -#define XREG_CP15_ATCM_REG_SIZE_ADDR "p15, 0, %0, c9, c1, 1" -#define XREG_CP15_BTCM_REG_SIZE_ADDR "p15, 0, %0, c9, c1, 0" -#define XREG_CP15_TCM_SELECTION "p15, 0, %0, c9, c2, 0" +#define XREG_CP15_ATCM_REG_SIZE_ADDR "p15, 0, %0, c9, c1, 1" +#define XREG_CP15_BTCM_REG_SIZE_ADDR "p15, 0, %0, c9, c1, 0" +#define XREG_CP15_TCM_SELECTION "p15, 0, %0, c9, c2, 0" -#define XREG_CP15_PERF_MONITOR_CTRL "p15, 0, %0, c9, c12, 0" -#define XREG_CP15_COUNT_ENABLE_SET "p15, 0, %0, c9, c12, 1" -#define XREG_CP15_COUNT_ENABLE_CLR "p15, 0, %0, c9, c12, 2" -#define XREG_CP15_V_FLAG_STATUS "p15, 0, %0, c9, c12, 3" -#define XREG_CP15_SW_INC "p15, 0, %0, c9, c12, 4" -#define XREG_CP15_EVENT_CNTR_SEL "p15, 0, %0, c9, c12, 5" +#define XREG_CP15_PERF_MONITOR_CTRL "p15, 0, %0, c9, c12, 0" +#define XREG_CP15_COUNT_ENABLE_SET "p15, 0, %0, c9, c12, 1" +#define XREG_CP15_COUNT_ENABLE_CLR "p15, 0, %0, c9, c12, 2" +#define XREG_CP15_V_FLAG_STATUS "p15, 0, %0, c9, c12, 3" +#define XREG_CP15_SW_INC "p15, 0, %0, c9, c12, 4" +#define XREG_CP15_EVENT_CNTR_SEL "p15, 0, %0, c9, c12, 5" -#define XREG_CP15_PERF_CYCLE_COUNTER "p15, 0, %0, c9, c13, 0" -#define XREG_CP15_EVENT_TYPE_SEL "p15, 0, %0, c9, c13, 1" -#define XREG_CP15_PERF_MONITOR_COUNT "p15, 0, %0, c9, c13, 2" +#define XREG_CP15_PERF_CYCLE_COUNTER "p15, 0, %0, c9, c13, 0" +#define XREG_CP15_EVENT_TYPE_SEL "p15, 0, %0, c9, c13, 1" +#define XREG_CP15_PERF_MONITOR_COUNT "p15, 0, %0, c9, c13, 2" -#define XREG_CP15_USER_ENABLE "p15, 0, %0, c9, c14, 0" -#define XREG_CP15_INTR_ENABLE_SET "p15, 0, %0, c9, c14, 1" -#define XREG_CP15_INTR_ENABLE_CLR "p15, 0, %0, c9, c14, 2" +#define XREG_CP15_USER_ENABLE "p15, 0, %0, c9, c14, 0" +#define XREG_CP15_INTR_ENABLE_SET "p15, 0, %0, c9, c14, 1" +#define XREG_CP15_INTR_ENABLE_CLR "p15, 0, %0, c9, c14, 2" /* C10 Register Defines */ /* Not used */ @@ -326,90 +326,90 @@ extern "C" { /* Not used */ /* C13 Register Defines */ -#define XREG_CP15_CONTEXT_ID "p15, 0, %0, c13, c0, 1" -#define USER_RW_THREAD_PID "p15, 0, %0, c13, c0, 2" -#define USER_RO_THREAD_PID "p15, 0, %0, c13, c0, 3" -#define USER_PRIV_THREAD_PID "p15, 0, %0, c13, c0, 4" +#define XREG_CP15_CONTEXT_ID "p15, 0, %0, c13, c0, 1" +#define USER_RW_THREAD_PID "p15, 0, %0, c13, c0, 2" +#define USER_RO_THREAD_PID "p15, 0, %0, c13, c0, 3" +#define USER_PRIV_THREAD_PID "p15, 0, %0, c13, c0, 4" /* C14 Register Defines */ /* not used */ /* C15 Register Defines */ -#define XREG_CP15_SEC_AUX_CTRL "p15, 0, %0, c15, c0, 0" +#define XREG_CP15_SEC_AUX_CTRL "p15, 0, %0, c15, c0, 0" /* MPE register definitions */ -#define XREG_FPSID c0 -#define XREG_FPSCR c1 -#define XREG_MVFR1 c6 -#define XREG_MVFR0 c7 -#define XREG_FPEXC c8 -#define XREG_FPINST c9 -#define XREG_FPINST2 c10 +#define XREG_FPSID c0 +#define XREG_FPSCR c1 +#define XREG_MVFR1 c6 +#define XREG_MVFR0 c7 +#define XREG_FPEXC c8 +#define XREG_FPINST c9 +#define XREG_FPINST2 c10 /* FPSID bits */ -#define XREG_FPSID_IMPLEMENTER_BIT (24U) -#define XREG_FPSID_IMPLEMENTER_MASK (0x000000FFU << FPSID_IMPLEMENTER_BIT) -#define XREG_FPSID_SOFTWARE (0X00000001U << 23U) -#define XREG_FPSID_ARCH_BIT (16U) -#define XREG_FPSID_ARCH_MASK (0x0000000FU << FPSID_ARCH_BIT) -#define XREG_FPSID_PART_BIT (8U) -#define XREG_FPSID_PART_MASK (0x000000FFU << FPSID_PART_BIT) -#define XREG_FPSID_VARIANT_BIT (4U) -#define XREG_FPSID_VARIANT_MASK (0x0000000FU << FPSID_VARIANT_BIT) -#define XREG_FPSID_REV_BIT (0U) -#define XREG_FPSID_REV_MASK (0x0000000FU << FPSID_REV_BIT) +#define XREG_FPSID_IMPLEMENTER_BIT (24U) +#define XREG_FPSID_IMPLEMENTER_MASK (0x000000FFU << FPSID_IMPLEMENTER_BIT) +#define XREG_FPSID_SOFTWARE (0X00000001U << 23U) +#define XREG_FPSID_ARCH_BIT (16U) +#define XREG_FPSID_ARCH_MASK (0x0000000FU << FPSID_ARCH_BIT) +#define XREG_FPSID_PART_BIT (8U) +#define XREG_FPSID_PART_MASK (0x000000FFU << FPSID_PART_BIT) +#define XREG_FPSID_VARIANT_BIT (4U) +#define XREG_FPSID_VARIANT_MASK (0x0000000FU << FPSID_VARIANT_BIT) +#define XREG_FPSID_REV_BIT (0U) +#define XREG_FPSID_REV_MASK (0x0000000FU << FPSID_REV_BIT) /* FPSCR bits */ -#define XREG_FPSCR_N_BIT (0X00000001U << 31U) -#define XREG_FPSCR_Z_BIT (0X00000001U << 30U) -#define XREG_FPSCR_C_BIT (0X00000001U << 29U) -#define XREG_FPSCR_V_BIT (0X00000001U << 28U) -#define XREG_FPSCR_QC (0X00000001U << 27U) -#define XREG_FPSCR_AHP (0X00000001U << 26U) -#define XREG_FPSCR_DEFAULT_NAN (0X00000001U << 25U) -#define XREG_FPSCR_FLUSHTOZERO (0X00000001U << 24U) -#define XREG_FPSCR_ROUND_NEAREST (0X00000000U << 22U) -#define XREG_FPSCR_ROUND_PLUSINF (0X00000001U << 22U) -#define XREG_FPSCR_ROUND_MINUSINF (0X00000002U << 22U) -#define XREG_FPSCR_ROUND_TOZERO (0X00000003U << 22U) -#define XREG_FPSCR_RMODE_BIT (22U) -#define XREG_FPSCR_RMODE_MASK (0X00000003U << FPSCR_RMODE_BIT) -#define XREG_FPSCR_STRIDE_BIT (20U) -#define XREG_FPSCR_STRIDE_MASK (0X00000003U << FPSCR_STRIDE_BIT) -#define XREG_FPSCR_LENGTH_BIT (16U) -#define XREG_FPSCR_LENGTH_MASK (0X00000007U << FPSCR_LENGTH_BIT) -#define XREG_FPSCR_IDC (0X00000001U << 7U) -#define XREG_FPSCR_IXC (0X00000001U << 4U) -#define XREG_FPSCR_UFC (0X00000001U << 3U) -#define XREG_FPSCR_OFC (0X00000001U << 2U) -#define XREG_FPSCR_DZC (0X00000001U << 1U) -#define XREG_FPSCR_IOC (0X00000001U << 0U) +#define XREG_FPSCR_N_BIT (0X00000001U << 31U) +#define XREG_FPSCR_Z_BIT (0X00000001U << 30U) +#define XREG_FPSCR_C_BIT (0X00000001U << 29U) +#define XREG_FPSCR_V_BIT (0X00000001U << 28U) +#define XREG_FPSCR_QC (0X00000001U << 27U) +#define XREG_FPSCR_AHP (0X00000001U << 26U) +#define XREG_FPSCR_DEFAULT_NAN (0X00000001U << 25U) +#define XREG_FPSCR_FLUSHTOZERO (0X00000001U << 24U) +#define XREG_FPSCR_ROUND_NEAREST (0X00000000U << 22U) +#define XREG_FPSCR_ROUND_PLUSINF (0X00000001U << 22U) +#define XREG_FPSCR_ROUND_MINUSINF (0X00000002U << 22U) +#define XREG_FPSCR_ROUND_TOZERO (0X00000003U << 22U) +#define XREG_FPSCR_RMODE_BIT (22U) +#define XREG_FPSCR_RMODE_MASK (0X00000003U << FPSCR_RMODE_BIT) +#define XREG_FPSCR_STRIDE_BIT (20U) +#define XREG_FPSCR_STRIDE_MASK (0X00000003U << FPSCR_STRIDE_BIT) +#define XREG_FPSCR_LENGTH_BIT (16U) +#define XREG_FPSCR_LENGTH_MASK (0X00000007U << FPSCR_LENGTH_BIT) +#define XREG_FPSCR_IDC (0X00000001U << 7U) +#define XREG_FPSCR_IXC (0X00000001U << 4U) +#define XREG_FPSCR_UFC (0X00000001U << 3U) +#define XREG_FPSCR_OFC (0X00000001U << 2U) +#define XREG_FPSCR_DZC (0X00000001U << 1U) +#define XREG_FPSCR_IOC (0X00000001U << 0U) /* MVFR0 bits */ -#define XREG_MVFR0_RMODE_BIT (28U) -#define XREG_MVFR0_RMODE_MASK (0x0000000FU << XREG_MVFR0_RMODE_BIT) -#define XREG_MVFR0_SHORT_VEC_BIT (24U) -#define XREG_MVFR0_SHORT_VEC_MASK (0x0000000FU << XREG_MVFR0_SHORT_VEC_BIT) -#define XREG_MVFR0_SQRT_BIT (20U) -#define XREG_MVFR0_SQRT_MASK (0x0000000FU << XREG_MVFR0_SQRT_BIT) -#define XREG_MVFR0_DIVIDE_BIT (16U) -#define XREG_MVFR0_DIVIDE_MASK (0x0000000FU << XREG_MVFR0_DIVIDE_BIT) -#define XREG_MVFR0_EXEC_TRAP_BIT (12U) -#define XREG_MVFR0_EXEC_TRAP_MASK (0x0000000FU << XREG_MVFR0_EXEC_TRAP_BIT) -#define XREG_MVFR0_DP_BIT (8U) -#define XREG_MVFR0_DP_MASK (0x0000000FU << XREG_MVFR0_DP_BIT) -#define XREG_MVFR0_SP_BIT (4U) -#define XREG_MVFR0_SP_MASK (0x0000000FU << XREG_MVFR0_SP_BIT) -#define XREG_MVFR0_A_SIMD_BIT (0U) -#define XREG_MVFR0_A_SIMD_MASK (0x0000000FU << MVFR0_A_SIMD_BIT) +#define XREG_MVFR0_RMODE_BIT (28U) +#define XREG_MVFR0_RMODE_MASK (0x0000000FU << XREG_MVFR0_RMODE_BIT) +#define XREG_MVFR0_SHORT_VEC_BIT (24U) +#define XREG_MVFR0_SHORT_VEC_MASK (0x0000000FU << XREG_MVFR0_SHORT_VEC_BIT) +#define XREG_MVFR0_SQRT_BIT (20U) +#define XREG_MVFR0_SQRT_MASK (0x0000000FU << XREG_MVFR0_SQRT_BIT) +#define XREG_MVFR0_DIVIDE_BIT (16U) +#define XREG_MVFR0_DIVIDE_MASK (0x0000000FU << XREG_MVFR0_DIVIDE_BIT) +#define XREG_MVFR0_EXEC_TRAP_BIT (12U) +#define XREG_MVFR0_EXEC_TRAP_MASK (0x0000000FU << XREG_MVFR0_EXEC_TRAP_BIT) +#define XREG_MVFR0_DP_BIT (8U) +#define XREG_MVFR0_DP_MASK (0x0000000FU << XREG_MVFR0_DP_BIT) +#define XREG_MVFR0_SP_BIT (4U) +#define XREG_MVFR0_SP_MASK (0x0000000FU << XREG_MVFR0_SP_BIT) +#define XREG_MVFR0_A_SIMD_BIT (0U) +#define XREG_MVFR0_A_SIMD_MASK (0x0000000FU << MVFR0_A_SIMD_BIT) /* FPEXC bits */ -#define XREG_FPEXC_EX (0X00000001U << 31U) -#define XREG_FPEXC_EN (0X00000001U << 30U) -#define XREG_FPEXC_DEX (0X00000001U << 29U) +#define XREG_FPEXC_EX (0X00000001U << 31U) +#define XREG_FPEXC_EN (0X00000001U << 30U) +#define XREG_FPEXC_DEX (0X00000001U << 29U) #ifdef __cplusplus |