diff options
Diffstat (limited to 'libcpu/mips/gs264')
| -rw-r--r-- | libcpu/mips/gs264/cache.c | 2 | ||||
| -rw-r--r-- | libcpu/mips/gs264/cache.h | 2 | ||||
| -rw-r--r-- | libcpu/mips/gs264/mips_mmu.c | 6 | ||||
| -rw-r--r-- | libcpu/mips/gs264/mips_mmu.h | 4 | ||||
| -rw-r--r-- | libcpu/mips/gs264/mipscfg.c | 2 | ||||
| -rw-r--r-- | libcpu/mips/gs264/mmu.c | 6 | ||||
| -rw-r--r-- | libcpu/mips/gs264/mmu.h | 2 |
7 files changed, 12 insertions, 12 deletions
diff --git a/libcpu/mips/gs264/cache.c b/libcpu/mips/gs264/cache.c index 54d38d0d3f..50976f2e4f 100644 --- a/libcpu/mips/gs264/cache.c +++ b/libcpu/mips/gs264/cache.c @@ -1,5 +1,5 @@ /* - * Copyright (c) 2006-2020, RT-Thread Development Team + * Copyright (c) 2006-2021, RT-Thread Development Team * * SPDX-License-Identifier: Apache-2.0 * diff --git a/libcpu/mips/gs264/cache.h b/libcpu/mips/gs264/cache.h index 10a4afd899..1e1bc52737 100644 --- a/libcpu/mips/gs264/cache.h +++ b/libcpu/mips/gs264/cache.h @@ -1,5 +1,5 @@ /* - * Copyright (c) 2006-2018, RT-Thread Development Team + * Copyright (c) 2006-2021, RT-Thread Development Team * * SPDX-License-Identifier: Apache-2.0 * diff --git a/libcpu/mips/gs264/mips_mmu.c b/libcpu/mips/gs264/mips_mmu.c index 7bed69596a..eae9b007de 100644 --- a/libcpu/mips/gs264/mips_mmu.c +++ b/libcpu/mips/gs264/mips_mmu.c @@ -1,5 +1,5 @@ /* - * Copyright (c) 2006-2020, RT-Thread Development Team + * Copyright (c) 2006-2021, RT-Thread Development Team * * SPDX-License-Identifier: Apache-2.0 * @@ -19,7 +19,7 @@ void mmu_init() uint32_t status = read_c0_status(); status |= 0x07 << 5;//ux = 1,sx = 1,kx = 1 write_c0_status(status); - + mmu_clear_tlb(); mmu_clear_itlb(); } @@ -154,7 +154,7 @@ void mmu_set_map(uint64_t vpn,uint64_t ppn,page_mask_enum_t page_mask,uint32_t a uint64_t even_vpn = vpn & (~lb); uint32_t index; tlb_item_t tlb_item,tlb2_item; - + mmu_tlb_item_init(&tlb_item); mmu_tlb_item_init(&tlb2_item); tlb_item.page_mask.mask = page_mask; diff --git a/libcpu/mips/gs264/mips_mmu.h b/libcpu/mips/gs264/mips_mmu.h index fcbcef3621..4c7af117d9 100644 --- a/libcpu/mips/gs264/mips_mmu.h +++ b/libcpu/mips/gs264/mips_mmu.h @@ -1,5 +1,5 @@ /* - * Copyright (c) 2006-2020, RT-Thread Development Team + * Copyright (c) 2006-2021, RT-Thread Development Team * * SPDX-License-Identifier: Apache-2.0 * @@ -96,4 +96,4 @@ uint64_t mmu_tlb_get_bad_vaddr(); void tlb_dump(); -#endif
\ No newline at end of file +#endif diff --git a/libcpu/mips/gs264/mipscfg.c b/libcpu/mips/gs264/mipscfg.c index b2aed120ae..0ce7000581 100644 --- a/libcpu/mips/gs264/mipscfg.c +++ b/libcpu/mips/gs264/mipscfg.c @@ -1,5 +1,5 @@ /* - * Copyright (c) 2006-2020, RT-Thread Development Team + * Copyright (c) 2006-2021, RT-Thread Development Team * * SPDX-License-Identifier: Apache-2.0 * diff --git a/libcpu/mips/gs264/mmu.c b/libcpu/mips/gs264/mmu.c index b5bedace50..cab73f37bd 100644 --- a/libcpu/mips/gs264/mmu.c +++ b/libcpu/mips/gs264/mmu.c @@ -1,5 +1,5 @@ /* - * Copyright (c) 2006-2020, RT-Thread Development Team + * Copyright (c) 2006-2021, RT-Thread Development Team * * SPDX-License-Identifier: Apache-2.0 * @@ -387,7 +387,7 @@ static void __rt_hw_mmu_unmap(rt_mmu_info *mmu_info, void* v_addr, size_t npages return; } - if (*(mmu_l2 + l2_off) & ARCH_MMU_USED_MASK) + if (*(mmu_l2 + l2_off) & ARCH_MMU_USED_MASK) { *(mmu_l2 + l2_off) = 0; /* cache maintain */ @@ -691,7 +691,7 @@ void *rt_hw_kernel_virt_to_phys(void *v_addr, size_t size) //pa --> va void *rt_hw_kernel_phys_to_virt(void *p_addr, size_t size) -{ +{ void *v_addr = 0; #ifdef RT_USING_USERSPACE diff --git a/libcpu/mips/gs264/mmu.h b/libcpu/mips/gs264/mmu.h index 2472bf975f..22a749af64 100644 --- a/libcpu/mips/gs264/mmu.h +++ b/libcpu/mips/gs264/mmu.h @@ -1,5 +1,5 @@ /* - * Copyright (c) 2006-2020, RT-Thread Development Team + * Copyright (c) 2006-2021, RT-Thread Development Team * * SPDX-License-Identifier: Apache-2.0 * |
